diff --git a/boards/GSE_ICI/GSE_ICI.pdc b/boards/GSE_ICI/GSE_ICI.pdc deleted file mode 100644 --- a/boards/GSE_ICI/GSE_ICI.pdc +++ /dev/null @@ -1,47 +0,0 @@ -# -# IO banks setting -# - -set_iobank Bank3 -vcci 3.30 -fixed no -set_iobank Bank2 -vcci 3.30 -fixed no -set_iobank Bank1 -vcci 3.30 -fixed no -set_iobank Bank0 -vcci 3.30 -fixed no - -# -# I/O constraints -# - -set_io Clock -iostd LVTTL -REGISTER No -RES_PULL None -pinname 151 -fixed yes -set_io DataRTX -iostd LVTTL -REGISTER No -RES_PULL None -pinname 190 -fixed yes -set_io DataRTX_echo -iostd LVTTL -REGISTER No -RES_PULL None -pinname 42 -fixed yes -set_io Gate -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 189 -fixed yes -set_io Major_Frame -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 185 -fixed yes -set_io Minor_Frame -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 183 -fixed yes -set_io SCLK -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 181 -fixed yes -#set_io Sdatabis -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 182 -fixed yes -set_io fdbusw\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 135 -fixed yes -set_io fdbusw\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 136 -fixed yes -set_io fdbusw\[2\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 137 -fixed yes -set_io fdbusw\[3\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 138 -fixed yes -set_io fdbusw\[4\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 139 -fixed yes -set_io fdbusw\[5\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 143 -fixed yes -set_io fdbusw\[6\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 144 -fixed yes -set_io fdbusw\[7\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 145 -fixed yes -set_io fifoadr\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 159 -fixed yes -set_io fifoadr\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 160 -fixed yes -set_io flagb -iostd LVTTL -REGISTER No -RES_PULL None -pinname 148 -fixed yes -#set_io gatebis -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 179 -fixed yes -set_io if_clk -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 152 -fixed yes -set_io pktend -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 161 -fixed yes -set_io reset -iostd LVTTL -REGISTER No -RES_PULL None -pinname 177 -fixed yes -#set_io sclkbis -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 180 -fixed yes -set_io sloe -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 153 -fixed yes -set_io slrd -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 167 -fixed yes -set_io slwr -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 166 -fixed yes -set_io BUS0 -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 48 -fixed yes -set_io BUS12 -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 9 -fixed yes -set_io BUS13 -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 7 -fixed yes -set_io BUS14 -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 5 -fixed yes - - - diff --git a/boards/GSE_ICI/Makefile.inc b/boards/GSE_ICI/Makefile.inc deleted file mode 100644 --- a/boards/GSE_ICI/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -TECHNOLOGY=PROASIC3 -PACKAGE=\"\" -SPEED=Std -SYNFREQ=50 - -PART=A3PE1500 -DESIGNER_PACKAGE=PQFF -DESIGNER_PINS=208 -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM - -MANUFACTURER=Actel -MGCPART=$(PART) -MGCTECHNOLOGY=ProASIC3E -MGCPACKAGE= {$(DESIGNER_PINS)$(DESIGNER_PACKAGE)} -LIBERO_DIE=IT10X10M3 -LIBERO_PACKAGE=pq$(DESIGNER_PINS) - diff --git a/boards/GSE_ICI/default.sdc b/boards/GSE_ICI/default.sdc deleted file mode 100644 --- a/boards/GSE_ICI/default.sdc +++ /dev/null @@ -1,61 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc -# Written on Wed Aug 1 19:29:24 2007 -# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk} -name {clk} -freq 48 -clockgroup default_clkgroup -route 5 - -define_clock {SCLKint} -name {SCLKint} -freq 3.3 -clockgroup default_clkgroup -route 5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# -define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} -define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} - - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -# -# Path Delay -# - -# -# Attributes -# -define_global_attribute syn_useioff {1} -define_global_attribute -disable syn_netlist_hierarchy {0} -define_attribute {etx_clk} syn_noclockbuf {1} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/ICI4-3DCAM/ICI4-Main-BD.ucf b/boards/ICI4-3DCAM/ICI4-Main-BD.ucf deleted file mode 100644 --- a/boards/ICI4-3DCAM/ICI4-Main-BD.ucf +++ /dev/null @@ -1,11 +0,0 @@ -NET "CLK" LOC = "B10"; -NET "RESET" LOC = "A5" | IOSTANDARD = LVTTL; -NET "SCLK" LOC = "V22" | IOSTANDARD = LVTTL; -NET "GATE" LOC = "T22" | IOSTANDARD = LVTTL; -NET "MINF" LOC = "T21" | IOSTANDARD = LVTTL; -NET "MAJF" LOC = "U22" | IOSTANDARD = LVTTL; -NET "DATA" LOC = "V21"; -NET "DC_ADC_SCLK" LOC = "AB17"; -NET "DC_ADC_IN(0)" LOC = "AB19" | IOSTANDARD = LVTTL; -NET "DC_ADC_IN(1)" LOC = "AA18" | IOSTANDARD = LVTTL; -NET "DC_ADC_FSynch" LOC = "AB18"; diff --git a/boards/ICI4-3DCAM/Makefile.inc b/boards/ICI4-3DCAM/Makefile.inc deleted file mode 100644 --- a/boards/ICI4-3DCAM/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -# -TECHNOLOGY=Spartan-3A -ISETECH="Spartan-3A" -PART=xc3s200a -PACKAGE=VQ100 -SPEED=-3 -SYNFREQ=220 -PROMGENPAR= - -MANUFACTURER=Xilinx -MGCPART=xc3s200a$(PACKAGE) -MGCTECHNOLOGY=SPARTAN-3A -MGCPACKAGE=$(PACKAGE) diff --git a/boards/ICI4-3DCAM/default.ut b/boards/ICI4-3DCAM/default.ut deleted file mode 100644 --- a/boards/ICI4-3DCAM/default.ut +++ /dev/null @@ -1,24 +0,0 @@ --g DebugBitstream:No --g Binary:no --b --g CRC:Enable --g ConfigRate:26 --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g SPI_buswidth:4 --g StartUpClk:CCLK --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g Persist:No --g ReadBack --g DonePipe:No --g DriveDone:Yes diff --git a/boards/ICI4-3DCAM/fpga-usb.cmd b/boards/ICI4-3DCAM/fpga-usb.cmd deleted file mode 100644 --- a/boards/ICI4-3DCAM/fpga-usb.cmd +++ /dev/null @@ -1,7 +0,0 @@ -setMode -bscan -setCable -p usb21 -identify -assignfile -p 1 -file xilinx-sp605-xc6slx45t.bit -program -p 1 -quit - diff --git a/boards/ICI4-3DCAM/fpga.cmd b/boards/ICI4-3DCAM/fpga.cmd deleted file mode 100644 --- a/boards/ICI4-3DCAM/fpga.cmd +++ /dev/null @@ -1,7 +0,0 @@ -setMode -bs -setCable -port auto -Identify -identifyMPM -assignFile -p 2 -file "xilinx-sp605-xc6slx45t.bit" -Program -p 2 -defaultVersion 0 -quit diff --git a/boards/ICI4-main-BD/ICI4-Main-BD.ucf b/boards/ICI4-main-BD/ICI4-Main-BD.ucf deleted file mode 100644 --- a/boards/ICI4-main-BD/ICI4-Main-BD.ucf +++ /dev/null @@ -1,31 +0,0 @@ -NET "CLK" LOC = "B10" | IOSTANDARD = LVCMOS33; - -NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; -NET "RESET" LOC = "A5" | IOSTANDARD = LVTTL; - -NET "SCLK" CLOCK_DEDICATED_ROUTE = FALSE; -NET "SCLK" LOC = "V22" | IOSTANDARD = LVTTL; - -NET "GATE" LOC = "T22" | IOSTANDARD = LVTTL; - -NET "MINF" CLOCK_DEDICATED_ROUTE = FALSE; -NET "MINF" LOC = "T21" | IOSTANDARD = LVTTL; - -NET "MAJF" LOC = "U22" | IOSTANDARD = LVTTL; -NET "DATA" LOC = "V21" | IOSTANDARD = LVCMOS33; -NET "DC_ADC_SCLK" LOC = "AB17" | IOSTANDARD = LVCMOS33; -NET "DC_ADC_IN(0)" LOC = "AB19" | IOSTANDARD = LVTTL; -NET "DC_ADC_IN(1)" LOC = "AA18" | IOSTANDARD = LVTTL; -NET "DC_ADC_FSynch" LOC = "AB18" | IOSTANDARD = LVCMOS33; -NET "LED" LOC = "A3" | IOSTANDARD = LVCMOS33; -NET "SET_RESET0" LOC = "AB21" | IOSTANDARD = LVCMOS33; -NET "SET_RESET1" LOC = "AB20" | IOSTANDARD = LVCMOS33; - - -NET "LF_SCK" LOC = "W20"| IOSTANDARD = LVCMOS33; -NET "LF_CNV" LOC = "Y18"| IOSTANDARD = LVCMOS33; -NET "LF_SDO1" LOC = "W17" | IOSTANDARD = LVTTL; -NET "LF_SDO2" LOC = "AA21" | IOSTANDARD = LVTTL; -NET "LF_SDO3" LOC = "AA16" | IOSTANDARD = LVTTL; - - diff --git a/boards/ICI4-main-BD/Makefile.inc b/boards/ICI4-main-BD/Makefile.inc deleted file mode 100644 --- a/boards/ICI4-main-BD/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -# -TECHNOLOGY=Spartan6 -ISETECH="Spartan6" -PART=XC6SLX45 -PACKAGE=fgg484 -SPEED=-3 -SYNFREQ=220 -PROMGENPAR= - -MANUFACTURER=Xilinx -MGCPART=XC6SLX45$(PACKAGE) -MGCTECHNOLOGY=SPARTAN-6 -MGCPACKAGE=$(PACKAGE) diff --git a/boards/ICI4-main-BD/default.ut b/boards/ICI4-main-BD/default.ut deleted file mode 100644 --- a/boards/ICI4-main-BD/default.ut +++ /dev/null @@ -1,24 +0,0 @@ --g DebugBitstream:No --g Binary:no --b --g CRC:Enable --g ConfigRate:26 --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g SPI_buswidth:4 --g StartUpClk:CCLK --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g Persist:No --g ReadBack --g DonePipe:No --g DriveDone:Yes diff --git a/boards/ICI4-main-BD/fpga-usb.cmd b/boards/ICI4-main-BD/fpga-usb.cmd deleted file mode 100644 --- a/boards/ICI4-main-BD/fpga-usb.cmd +++ /dev/null @@ -1,7 +0,0 @@ -setMode -bscan -setCable -p usb21 -identify -assignfile -p 1 -file xilinx-sp605-xc6slx45t.bit -program -p 1 -quit - diff --git a/boards/ICI4-main-BD/fpga.cmd b/boards/ICI4-main-BD/fpga.cmd deleted file mode 100644 --- a/boards/ICI4-main-BD/fpga.cmd +++ /dev/null @@ -1,7 +0,0 @@ -setMode -bs -setCable -port auto -Identify -identifyMPM -assignFile -p 2 -file "xilinx-sp605-xc6slx45t.bit" -Program -p 2 -defaultVersion 0 -quit diff --git a/boards/LeonLPP-A3PE3kL/Makefile.inc b/boards/LeonLPP-A3PE3kL/Makefile.inc deleted file mode 100644 --- a/boards/LeonLPP-A3PE3kL/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -TECHNOLOGY=PROASIC3 -PACKAGE=\"\" -SPEED=Std -SYNFREQ=50 - -PART=A3PE3000L -DESIGNER_PACKAGE=FBGA -DESIGNER_PINS=324 -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM - -MANUFACTURER=Actel -MGCPART=$(PART) -MGCTECHNOLOGY=PROASIC3 -MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} -LIBERO_DIE=IT14X14M4LDP -LIBERO_PACKAGE=fg$(DESIGNER_PINS) - diff --git a/boards/LeonLPP-A3PE3kL/Projet-Blanc-A3PE3kL.pdc b/boards/LeonLPP-A3PE3kL/Projet-Blanc-A3PE3kL.pdc deleted file mode 100644 --- a/boards/LeonLPP-A3PE3kL/Projet-Blanc-A3PE3kL.pdc +++ /dev/null @@ -1,570 +0,0 @@ -# Actel Physical design constraints file -# Generated file - -# Version: 9.1 SP3 9.1.3.4 -# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA -# Date generated: Tue Oct 18 08:21:45 2011 - - -# -# IO banks setting -# - - -# -# I/O constraints -# - -set_io CE2 \ - -pinname K14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io MODE \ - -pinname C15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SSRAM_CLK \ - -pinname D15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ZZ \ - -pinname E18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[0]} \ - -pinname D18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[1]} \ - -pinname B17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[2]} \ - -pinname A17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[3]} \ - -pinname B16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[4]} \ - -pinname A16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[5]} \ - -pinname A15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[6]} \ - -pinname A14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[7]} \ - -pinname B13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[8]} \ - -pinname B9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[9]} \ - -pinname A8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[10]} \ - -pinname B7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[11]} \ - -pinname A6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[12]} \ - -pinname B6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[13]} \ - -pinname A5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[14]} \ - -pinname A4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[15]} \ - -pinname B3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[16]} \ - -pinname B18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[17]} \ - -pinname A13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[18]} \ - -pinname B12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbrxd \ - -pinname V4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbtxd \ - -pinname V3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io clk50MHz \ - -pinname D13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[0]} \ - -pinname F10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[1]} \ - -pinname F9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[2]} \ - -pinname F8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[3]} \ - -pinname F7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[4]} \ - -pinname E6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[5]} \ - -pinname D5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[6]} \ - -pinname C4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[7]} \ - -pinname D3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[8]} \ - -pinname F18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[9]} \ - -pinname H18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[10]} \ - -pinname J18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[11]} \ - -pinname K18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[12]} \ - -pinname L18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[13]} \ - -pinname N18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[14]} \ - -pinname P18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[15]} \ - -pinname R18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[16]} \ - -pinname M16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[17]} \ - -pinname N17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[18]} \ - -pinname P16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[19]} \ - -pinname R13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[20]} \ - -pinname T13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[21]} \ - -pinname U13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[22]} \ - -pinname U12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[23]} \ - -pinname U10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[24]} \ - -pinname C16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[25]} \ - -pinname D16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[26]} \ - -pinname E15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[27]} \ - -pinname F16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[28]} \ - -pinname G16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[29]} \ - -pinname H16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[30]} \ - -pinname J15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[31]} \ - -pinname K15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsuact \ - -pinname N7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsubre \ - -pinname N6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io errorn \ - -pinname U6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {led[0]} \ - -pinname T11 \ - -fixed no \ - -DIRECTION Inout - - -set_io {led[1]} \ - -pinname R11 \ - -fixed no \ - -DIRECTION Inout - - -set_io nADSC \ - -pinname D10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADSP \ - -pinname C10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADV \ - -pinname B10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWE \ - -pinname F11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWa \ - -pinname F15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWb \ - -pinname G15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWc \ - -pinname H15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWd \ - -pinname J14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE1 \ - -pinname L15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE3 \ - -pinname E13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nGW \ - -pinname C11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nOE \ - -pinname E10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io reset \ - -pinname P13 \ - -fixed yes \ - -DIRECTION Inout - - - -set_io {gpio[0]} -pinname J7 -fixed yes -set_io {gpio[1]} -pinname C2 -fixed yes -set_io {gpio[2]} -pinname C3 -fixed yes -set_io {gpio[3]} -pinname D4 -fixed yes -set_io {gpio[4]} -pinname E4 -fixed yes -set_io {gpio[5]} -pinname F2 -fixed yes -set_io {gpio[6]} -pinname G3 -fixed yes - - -# -# Non IO constraints -# - - -# -# Old IO constraints, commented out for reference -# - -# set_io clk50MHz -pinname D13 -fixed yes -# set_io reset -pinname P13 -fixed yes -# set_io errorn -pinname U6 -fixed yes -# set_io dsubre -pinname N6 -fixed yes -# set_io dsuact -pinname N7 -fixed yes -# set_io {led[0]} -pinname T11 -fixed yes -# set_io {led[1]} -pinname R11 -fixed yes -# set_io ahbrxd -pinname V4 -fixed yes -# set_io ahbtxd -pinname V3 -fixed yes -# set_io urxd1 -pinname V9 -fixed yes -# set_io utxd1 -pinname V8 -fixed yes -# set_io {data[0]} -pinname F10 -fixed yes -# set_io {data[1]} -pinname F9 -fixed yes -# set_io {data[2]} -pinname F8 -fixed yes -# set_io {data[3]} -pinname F7 -fixed yes -# set_io {data[4]} -pinname E6 -fixed yes -# set_io {data[5]} -pinname D5 -fixed yes -# set_io {data[6]} -pinname C4 -fixed yes -# set_io {data[7]} -pinname D3 -fixed yes -# set_io {data[8]} -pinname F18 -fixed yes -# set_io {data[9]} -pinname H18 -fixed yes -# set_io {data[10]} -pinname J18 -fixed yes -# set_io {data[11]} -pinname K18 -fixed yes -# set_io {data[12]} -pinname L18 -fixed yes -# set_io {data[13]} -pinname N18 -fixed yes -# set_io {data[14]} -pinname P18 -fixed yes -# set_io {data[15]} -pinname R18 -fixed yes -# set_io {data[16]} -pinname M16 -fixed yes -# set_io {data[17]} -pinname N17 -fixed yes -# set_io {data[18]} -pinname P16 -fixed yes -# set_io {data[19]} -pinname R13 -fixed yes -# set_io {data[20]} -pinname T13 -fixed yes -# set_io {data[21]} -pinname U13 -fixed yes -# set_io {data[22]} -pinname U12 -fixed yes -# set_io {data[23]} -pinname U10 -fixed yes -# set_io {data[24]} -pinname C16 -fixed yes -# set_io {data[25]} -pinname D16 -fixed yes -# set_io {data[26]} -pinname E15 -fixed yes -# set_io {data[27]} -pinname F16 -fixed yes -# set_io {data[28]} -pinname G16 -fixed yes -# set_io {data[29]} -pinname H16 -fixed yes -# set_io {data[30]} -pinname J15 -fixed yes -# set_io {data[31]} -pinname K15 -fixed yes -# set_io {address[0]} -pinname D18 -fixed yes -# set_io {address[1]} -pinname B17 -fixed yes -# set_io {address[2]} -pinname A17 -fixed yes -# set_io {address[3]} -pinname B16 -fixed yes -# set_io {address[4]} -pinname A16 -fixed yes -# set_io {address[5]} -pinname A15 -fixed yes -# set_io {address[6]} -pinname A14 -fixed yes -# set_io {address[7]} -pinname B13 -fixed yes -# set_io {address[8]} -pinname B9 -fixed yes -# set_io {address[9]} -pinname A8 -fixed yes -# set_io {address[10]} -pinname B7 -fixed yes -# set_io {address[11]} -pinname A6 -fixed yes -# set_io {address[12]} -pinname B6 -fixed yes -# set_io {address[13]} -pinname A5 -fixed yes -# set_io {address[14]} -pinname A4 -fixed yes -# set_io {address[15]} -pinname B3 -fixed yes -# set_io {address[16]} -pinname B18 -fixed yes -# set_io {address[17]} -pinname A13 -fixed yes -# set_io {address[18]} -pinname B12 -fixed yes -# set_io nBWa -pinname F15 -fixed yes -# set_io nBWb -pinname G15 -fixed yes -# set_io nBWc -pinname H15 -fixed yes -# set_io nBWd -pinname J14 -fixed yes -# set_io nBWE -pinname F11 -fixed yes -# set_io nADSC -pinname D10 -fixed yes -# set_io nADSP -pinname C10 -fixed yes -# set_io nADV -pinname B10 -fixed yes -# set_io nGW -pinname C11 -fixed yes -# set_io nCE1 -pinname L15 -fixed yes -# set_io CE2 -pinname K14 -fixed yes -# set_io nCE3 -pinname E13 -fixed yes -# set_io nOE -pinname E10 -fixed yes -# set_io MODE -pinname C15 -fixed yes -# set_io SSRAM_CLK -pinname D15 -fixed yes -# set_io ZZ -pinname E18 -fixed yes diff --git a/boards/LeonLPP-A3PE3kL/Projet-LeonLFR-A3PE3kL-Sheldon.pdc b/boards/LeonLPP-A3PE3kL/Projet-LeonLFR-A3PE3kL-Sheldon.pdc deleted file mode 100644 --- a/boards/LeonLPP-A3PE3kL/Projet-LeonLFR-A3PE3kL-Sheldon.pdc +++ /dev/null @@ -1,728 +0,0 @@ -# Actel Physical design constraints file -# Generated file - -# Version: 9.1 9.1.0.18 -# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA -# Date generated: Tue Apr 23 13:43:46 2013 - - -# -# IO banks setting -# - - -# -# I/O constraints -# - -set_io Bias_Fails \ - -pinname G2 \ - -fixed yes \ - -DIRECTION Inout - - -set_io CE2 \ - -pinname K14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io CNV_CH1 \ - -pinname K1 \ - -fixed yes \ - -DIRECTION Inout - - -set_io MODE \ - -pinname C15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SCK_CH1 \ - -pinname L1 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SDO_CH1[0]} \ - -pinname D1 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SDO_CH1[1]} \ - -pinname E1 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SDO_CH1[2]} \ - -pinname F1 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SDO_CH1[3]} \ - -pinname H1 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SDO_CH1[4]} \ - -pinname J1 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SPW1_EN \ - -pinname T18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SPW2_EN \ - -pinname V16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SSRAM_CLK \ - -pinname D15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io testled0 \ - -pinname T11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io testled1 \ - -pinname R11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io testspw1D \ - -pinname V15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io testspw1S \ - -pinname V14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io UART_RXD \ - -pinname V9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io UART_TXD \ - -pinname V8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ZZ \ - -pinname E18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[0]} \ - -pinname D18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[1]} \ - -pinname B17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[2]} \ - -pinname A17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[3]} \ - -pinname B16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[4]} \ - -pinname A16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[5]} \ - -pinname A15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[6]} \ - -pinname A14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[7]} \ - -pinname B13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[8]} \ - -pinname B9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[9]} \ - -pinname A8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[10]} \ - -pinname B7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[11]} \ - -pinname A6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[12]} \ - -pinname B6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[13]} \ - -pinname A5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[14]} \ - -pinname A4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[15]} \ - -pinname B3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[16]} \ - -pinname B18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[17]} \ - -pinname A13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[18]} \ - -pinname B12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbrxd \ - -pinname V4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbtxd \ - -pinname V3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io clk50MHz \ - -pinname D13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[0]} \ - -pinname F10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[1]} \ - -pinname F9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[2]} \ - -pinname F8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[3]} \ - -pinname F7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[4]} \ - -pinname E6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[5]} \ - -pinname D5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[6]} \ - -pinname C4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[7]} \ - -pinname D3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[8]} \ - -pinname F18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[9]} \ - -pinname H18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[10]} \ - -pinname J18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[11]} \ - -pinname K18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[12]} \ - -pinname L18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[13]} \ - -pinname N18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[14]} \ - -pinname P18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[15]} \ - -pinname R18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[16]} \ - -pinname M16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[17]} \ - -pinname N17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[18]} \ - -pinname P16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[19]} \ - -pinname R13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[20]} \ - -pinname T13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[21]} \ - -pinname U13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[22]} \ - -pinname U12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[23]} \ - -pinname U10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[24]} \ - -pinname C16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[25]} \ - -pinname D16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[26]} \ - -pinname E15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[27]} \ - -pinname F16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[28]} \ - -pinname G16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[29]} \ - -pinname H16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[30]} \ - -pinname J15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[31]} \ - -pinname K15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsuact \ - -pinname N7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsubre \ - -pinname N6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io errorn \ - -pinname U6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {gpio[0]} \ - -pinname J7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {gpio[1]} \ - -pinname C2 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {gpio[2]} \ - -pinname C3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {gpio[3]} \ - -pinname D4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {gpio[4]} \ - -pinname E4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {gpio[5]} \ - -pinname F2 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {gpio[6]} \ - -pinname G3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADSC \ - -pinname D10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADSP \ - -pinname C10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADV \ - -pinname B10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWE \ - -pinname F11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWa \ - -pinname F15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWb \ - -pinname G15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWc \ - -pinname H15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWd \ - -pinname J14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE1 \ - -pinname L15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE3 \ - -pinname E13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nGW \ - -pinname C11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nOE \ - -pinname E10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io reset \ - -pinname P13 \ - -fixed yes \ - -DIRECTION Inout - -set_io DAC_EN \ - -pinname C1 \ - -fixed yes \ - -DIRECTION Inout - -set_io DAC_SYNC \ - -pinname B1 \ - -fixed yes \ - -DIRECTION Inout - -set_io DAC_SCLK \ - -pinname A3 \ - -fixed yes \ - -DIRECTION Inout - -set_io DAC_DATA \ - -pinname A2 \ - -fixed yes \ - -DIRECTION Inout - -# -# Non IO constraints -# - - -# -# Old IO constraints, commented out for reference -# - -# set_io CE2 -pinname K14 -fixed yes -DIRECTION Inout -# set_io MODE -pinname C15 -fixed yes -DIRECTION Inout -# set_io SSRAM_CLK -pinname D15 -fixed yes -DIRECTION Inout -# set_io ZZ -pinname E18 -fixed yes -DIRECTION Inout -# set_io {address[0]} -pinname D18 -fixed yes -DIRECTION Inout -# set_io {address[1]} -pinname B17 -fixed yes -DIRECTION Inout -# set_io {address[2]} -pinname A17 -fixed yes -DIRECTION Inout -# set_io {address[3]} -pinname B16 -fixed yes -DIRECTION Inout -# set_io {address[4]} -pinname A16 -fixed yes -DIRECTION Inout -# set_io {address[5]} -pinname A15 -fixed yes -DIRECTION Inout -# set_io {address[6]} -pinname A14 -fixed yes -DIRECTION Inout -# set_io {address[7]} -pinname B13 -fixed yes -DIRECTION Inout -# set_io {address[8]} -pinname B9 -fixed yes -DIRECTION Inout -# set_io {address[9]} -pinname A8 -fixed yes -DIRECTION Inout -# set_io {address[10]} -pinname B7 -fixed yes -DIRECTION Inout -# set_io {address[11]} -pinname A6 -fixed yes -DIRECTION Inout -# set_io {address[12]} -pinname B6 -fixed yes -DIRECTION Inout -# set_io {address[13]} -pinname A5 -fixed yes -DIRECTION Inout -# set_io {address[14]} -pinname A4 -fixed yes -DIRECTION Inout -# set_io {address[15]} -pinname B3 -fixed yes -DIRECTION Inout -# set_io {address[16]} -pinname B18 -fixed yes -DIRECTION Inout -# set_io {address[17]} -pinname A13 -fixed yes -DIRECTION Inout -# set_io {address[18]} -pinname B12 -fixed yes -DIRECTION Inout -# set_io ahbrxd -pinname V4 -fixed yes -DIRECTION Inout -# set_io ahbtxd -pinname V3 -fixed yes -DIRECTION Inout -# set_io clk50MHz -pinname D13 -fixed yes -DIRECTION Inout -# set_io {data[0]} -pinname F10 -fixed yes -DIRECTION Inout -# set_io {data[1]} -pinname F9 -fixed yes -DIRECTION Inout -# set_io {data[2]} -pinname F8 -fixed yes -DIRECTION Inout -# set_io {data[3]} -pinname F7 -fixed yes -DIRECTION Inout -# set_io {data[4]} -pinname E6 -fixed yes -DIRECTION Inout -# set_io {data[5]} -pinname D5 -fixed yes -DIRECTION Inout -# set_io {data[6]} -pinname C4 -fixed yes -DIRECTION Inout -# set_io {data[7]} -pinname D3 -fixed yes -DIRECTION Inout -# set_io {data[8]} -pinname F18 -fixed yes -DIRECTION Inout -# set_io {data[9]} -pinname H18 -fixed yes -DIRECTION Inout -# set_io {data[10]} -pinname J18 -fixed yes -DIRECTION Inout -# set_io {data[11]} -pinname K18 -fixed yes -DIRECTION Inout -# set_io {data[12]} -pinname L18 -fixed yes -DIRECTION Inout -# set_io {data[13]} -pinname N18 -fixed yes -DIRECTION Inout -# set_io {data[14]} -pinname P18 -fixed yes -DIRECTION Inout -# set_io {data[15]} -pinname R18 -fixed yes -DIRECTION Inout -# set_io {data[16]} -pinname M16 -fixed yes -DIRECTION Inout -# set_io {data[17]} -pinname N17 -fixed yes -DIRECTION Inout -# set_io {data[18]} -pinname P16 -fixed yes -DIRECTION Inout -# set_io {data[19]} -pinname R13 -fixed yes -DIRECTION Inout -# set_io {data[20]} -pinname T13 -fixed yes -DIRECTION Inout -# set_io {data[21]} -pinname U13 -fixed yes -DIRECTION Inout -# set_io {data[22]} -pinname U12 -fixed yes -DIRECTION Inout -# set_io {data[23]} -pinname U10 -fixed yes -DIRECTION Inout -# set_io {data[24]} -pinname C16 -fixed yes -DIRECTION Inout -# set_io {data[25]} -pinname D16 -fixed yes -DIRECTION Inout -# set_io {data[26]} -pinname E15 -fixed yes -DIRECTION Inout -# set_io {data[27]} -pinname F16 -fixed yes -DIRECTION Inout -# set_io {data[28]} -pinname G16 -fixed yes -DIRECTION Inout -# set_io {data[29]} -pinname H16 -fixed yes -DIRECTION Inout -# set_io {data[30]} -pinname J15 -fixed yes -DIRECTION Inout -# set_io {data[31]} -pinname K15 -fixed yes -DIRECTION Inout -# set_io dsuact -pinname N7 -fixed yes -DIRECTION Inout -# set_io dsubre -pinname N6 -fixed yes -DIRECTION Inout -# set_io errorn -pinname U6 -fixed yes -DIRECTION Inout -# set_io nADSC -pinname D10 -fixed yes -DIRECTION Inout -# set_io nADSP -pinname C10 -fixed yes -DIRECTION Inout -# set_io nADV -pinname B10 -fixed yes -DIRECTION Inout -# set_io nBWE -pinname F11 -fixed yes -DIRECTION Inout -# set_io nBWa -pinname F15 -fixed yes -DIRECTION Inout -# set_io nBWb -pinname G15 -fixed yes -DIRECTION Inout -# set_io nBWc -pinname H15 -fixed yes -DIRECTION Inout -# set_io nBWd -pinname J14 -fixed yes -DIRECTION Inout -# set_io nCE1 -pinname L15 -fixed yes -DIRECTION Inout -# set_io nCE3 -pinname E13 -fixed yes -DIRECTION Inout -# set_io nGW -pinname C11 -fixed yes -DIRECTION Inout -# set_io nOE -pinname E10 -fixed yes -DIRECTION Inout -# set_io reset -pinname P13 -fixed yes -DIRECTION Inout -# set_io UART_RXD -pinname V9 -fixed yes -DIRECTION Inout -# set_io UART_TXD -pinname V8 -fixed yes -DIRECTION Inout -# set_io CNV_CH1 -pinname K1 -fixed yes -# set_io SCK_CH1 -pinname L1 -fixed yes -# set_io {SDO_CH1[0]} -pinname D1 -fixed yes -# set_io {SDO_CH1[1]} -pinname E1 -fixed yes -# set_io {SDO_CH1[2]} -pinname F1 -fixed yes -# set_io {SDO_CH1[3]} -pinname H1 -fixed yes -# set_io {SDO_CH1[4]} -pinname J1 -fixed yes -# set_io Bias_Fails -pinname G2 -fixed yes -# set_io {gpio[0]} -pinname J7 -fixed yes -# set_io {gpio[1]} -pinname C2 -fixed yes -# set_io {gpio[2]} -pinname C3 -fixed yes -# set_io {gpio[3]} -pinname D4 -fixed yes -# set_io {gpio[4]} -pinname E4 -fixed yes -# set_io {gpio[5]} -pinname F2 -fixed yes -# set_io {gpio[6]} -pinname G3 -fixed yes -# set_io testspw1S -pinname V14 -fixed yes -# set_io testspw1D -pinname V15 -fixed yes -# set_io testled0 -pinname T11 -fixed yes -# set_io testled1 -pinname R11 -fixed yes -# set_io SPW1_EN -pinname T18 -fixed yes -# set_io SPW2_EN -pinname V16 -fixed yes -# set_io DAC_EN -pinname C1 -fixed yes -# set_io DAC_SYNC -pinname B1 -fixed yes -# set_io DAC_SCLK -pinname A3 -fixed yes -# set_io DAC_DATA -pinname A2 -fixed yes \ No newline at end of file diff --git a/boards/LeonLPP-A3PE3kL/default.sdc b/boards/LeonLPP-A3PE3kL/default.sdc deleted file mode 100644 --- a/boards/LeonLPP-A3PE3kL/default.sdc +++ /dev/null @@ -1,59 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc -# Written on Wed Aug 1 19:29:24 2007 -# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# -define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} -define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} - - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -# -# Path Delay -# - -# -# Attributes -# -define_global_attribute syn_useioff {1} -define_global_attribute -disable syn_netlist_hierarchy {0} -define_attribute {etx_clk} syn_noclockbuf {1} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/LeonLPP-M7A3P1k/Makefile.inc b/boards/LeonLPP-M7A3P1k/Makefile.inc deleted file mode 100644 --- a/boards/LeonLPP-M7A3P1k/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -TECHNOLOGY=PROASIC3 -PACKAGE=\"\" -SPEED=Std -SYNFREQ=50 - -PART=PROASIC3 -DESIGNER_PACKAGE=FBGA -DESIGNER_PINS=484 -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM - -MANUFACTURER=Actel -MGCPART=$(PART) -MGCTECHNOLOGY=PROASIC3 -MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} -LIBERO_DIE=IT14X14M4LDP -LIBERO_PACKAGE=fg$(DESIGNER_PINS) - diff --git a/boards/LeonLPP-M7A3P1k/Projet-Blanc-M7A3P1k.pdc b/boards/LeonLPP-M7A3P1k/Projet-Blanc-M7A3P1k.pdc deleted file mode 100644 --- a/boards/LeonLPP-M7A3P1k/Projet-Blanc-M7A3P1k.pdc +++ /dev/null @@ -1,124 +0,0 @@ -########################################################################## -# FILE NAME : LFR-142200-DM-MINIAMBA.pdc -# DATA : July 19, 2011 -# VERSION : 1.0 -# -# DESCRIPTION : Physical Constraints for LFR developpement model -# -# MODIFICATION HISTORY: -# 19/07/2011 1.0 Initial Release -########################################################################## - - -########################################################################## -# SYSTEM SIGNALS -########################################################################## -set_io clk50MHz -pinname W17 -fixed yes -set_io reset -pinname W15 -fixed yes - -########################################################################## -# FLASH/SRAM MEMORY INTERFACE SIGNALS -########################################################################## -set_io romsn -pinname B16 -fixed yes -set_io oen -pinname A16 -fixed yes -set_io writen -pinname A17 -fixed yes - -set_io sram_adsc -pinname E19 -fixed yes -set_io sram_adsp -pinname F19 -fixed yes -set_io sram_adv -pinname G20 -fixed yes -set_io sram_gwen -pinname J16 -fixed yes -set_io sram_pwrdwn -pinname A18 -fixed yes -set_io ramclk -pinname F18 -fixed yes -set_io ramsn -pinname H17 -fixed yes -set_io rwen -pinname G19 -fixed yes -set_io ramben\[0\] -pinname J18 -set_io ramben\[1\] -pinname J17 -set_io ramben\[2\] -pinname H19 -set_io ramben\[3\] -pinname H18 -set_io ramoen -pinname G18 -fixed yes - -set_io address\[0\] -pinname F12 -set_io address\[1\] -pinname E12 -set_io address\[2\] -pinname G12 -set_io address\[3\] -pinname H12 -set_io address\[4\] -pinname A12 -set_io address\[5\] -pinname B12 -set_io address\[6\] -pinname D13 -set_io address\[7\] -pinname D12 -set_io address\[8\] -pinname E14 -set_io address\[9\] -pinname E13 -set_io address\[10\] -pinname G13 -set_io address\[11\] -pinname F13 -set_io address\[12\] -pinname A13 -set_io address\[13\] -pinname B13 -set_io address\[14\] -pinname F14 -set_io address\[15\] -pinname G14 -set_io address\[16\] -pinname D15 -set_io address\[17\] -pinname D14 -set_io address\[18\] -pinname A15 - -set_io data\[0\] -pinname B5 -fixed yes -set_io data\[1\] -pinname B4 -fixed yes -set_io data\[2\] -pinname C7 -fixed yes -set_io data\[3\] -pinname C6 -fixed yes -set_io data\[4\] -pinname D8 -fixed yes -set_io data\[5\] -pinname E8 -fixed yes -set_io data\[6\] -pinname A5 -fixed yes -set_io data\[7\] -pinname A4 -fixed yes -set_io data\[8\] -pinname B7 -fixed yes -set_io data\[9\] -pinname B6 -fixed yes -set_io data\[10\] -pinname A7 -fixed yes -set_io data\[11\] -pinname A6 -fixed yes -set_io data\[12\] -pinname G10 -fixed yes -set_io data\[13\] -pinname G9 -fixed yes -set_io data\[14\] -pinname D9 -fixed yes -set_io data\[15\] -pinname E9 -fixed yes -set_io data\[16\] -pinname A8 -fixed yes -set_io data\[17\] -pinname B8 -fixed yes -set_io data\[18\] -pinname D10 -fixed yes -set_io data\[19\] -pinname E10 -fixed yes -set_io data\[20\] -pinname G11 -fixed yes -set_io data\[21\] -pinname H11 -fixed yes -set_io data\[22\] -pinname B10 -fixed yes -set_io data\[23\] -pinname C10 -fixed yes -set_io data\[24\] -pinname F11 -fixed yes -set_io data\[25\] -pinname F10 -fixed yes -set_io data\[26\] -pinname E11 -fixed yes -set_io data\[27\] -pinname D11 -fixed yes -set_io data\[28\] -pinname A9 -fixed yes -set_io data\[29\] -pinname B9 -fixed yes -set_io data\[30\] -pinname A11 -fixed yes -set_io data\[31\] -pinname A10 -fixed yes - - -########################################################################## -# PUSH-BUTTON SWITCHES SIGNALS -########################################################################## -set_io gpio\[0\] -pinname P7 -fixed yes -set_io gpio\[1\] -pinname R5 -fixed yes -set_io gpio\[2\] -pinname P6 -fixed yes -set_io gpio\[3\] -pinname R6 -fixed yes -set_io gpio\[4\] -pinname U3 -fixed yes -set_io gpio\[5\] -pinname T5 -fixed yes -set_io gpio\[6\] -pinname U2 -fixed yes -#set_io gpio\[7\] -pinname T4 -fixed yes - - -########################################################################## -# LED SIGNALS -########################################################################## -set_io led\[0\] -pinname R4 -fixed yes -set_io led\[1\] -pinname P5 -fixed yes -set_io led\[2\] -pinname R2 -fixed yes -set_io led\[3\] -pinname T2 -fixed yes -set_io led\[4\] -pinname P2 -fixed yes -set_io led\[5\] -pinname N2 -fixed yes -set_io errorn -pinname N6 -fixed yes -set_io dsuact -pinname N7 -fixed yes -set_io dsubre -pinname T4 -fixed yes - -########################################################################## -# RS-232 INTERFACE SIGNALS -########################################################################## -set_io ahbrxd -pinname K18 -fixed yes -set_io ahbtxd -pinname C11 -fixed yes diff --git a/boards/LeonLPP-M7A3P1k/default.sdc b/boards/LeonLPP-M7A3P1k/default.sdc deleted file mode 100644 --- a/boards/LeonLPP-M7A3P1k/default.sdc +++ /dev/null @@ -1,59 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc -# Written on Wed Aug 1 19:29:24 2007 -# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# -define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} -define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} - - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -# -# Path Delay -# - -# -# Attributes -# -define_global_attribute syn_useioff {1} -define_global_attribute -disable syn_netlist_hierarchy {0} -define_attribute {etx_clk} syn_noclockbuf {1} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/Projet-LeonLFR-A3P3K-Sheldon/LFR-142200-DM-LEON3-BASE.pdc b/boards/Projet-LeonLFR-A3P3K-Sheldon/LFR-142200-DM-LEON3-BASE.pdc deleted file mode 100644 --- a/boards/Projet-LeonLFR-A3P3K-Sheldon/LFR-142200-DM-LEON3-BASE.pdc +++ /dev/null @@ -1,573 +0,0 @@ -# Actel Physical design constraints file -# Generated file - -# Version: 9.1 SP3 9.1.3.4 -# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA -# Date generated: Tue Oct 18 08:21:45 2011 - - -# -# IO banks setting -# - - -# -# I/O constraints -# - -set_io CE2 \ - -pinname K14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io MODE \ - -pinname C15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SSRAM_CLK \ - -pinname D15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ZZ \ - -pinname E18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[0]} \ - -pinname D18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[1]} \ - -pinname B17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[2]} \ - -pinname A17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[3]} \ - -pinname B16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[4]} \ - -pinname A16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[5]} \ - -pinname A15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[6]} \ - -pinname A14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[7]} \ - -pinname B13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[8]} \ - -pinname B9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[9]} \ - -pinname A8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[10]} \ - -pinname B7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[11]} \ - -pinname A6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[12]} \ - -pinname B6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[13]} \ - -pinname A5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[14]} \ - -pinname A4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[15]} \ - -pinname B3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[16]} \ - -pinname B18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[17]} \ - -pinname A13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[18]} \ - -pinname B12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbrxd \ - -pinname V4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbtxd \ - -pinname V3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io clk50MHz \ - -pinname D13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[0]} \ - -pinname F10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[1]} \ - -pinname F9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[2]} \ - -pinname F8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[3]} \ - -pinname F7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[4]} \ - -pinname E6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[5]} \ - -pinname D5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[6]} \ - -pinname C4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[7]} \ - -pinname D3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[8]} \ - -pinname F18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[9]} \ - -pinname H18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[10]} \ - -pinname J18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[11]} \ - -pinname K18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[12]} \ - -pinname L18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[13]} \ - -pinname N18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[14]} \ - -pinname P18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[15]} \ - -pinname R18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[16]} \ - -pinname M16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[17]} \ - -pinname N17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[18]} \ - -pinname P16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[19]} \ - -pinname R13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[20]} \ - -pinname T13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[21]} \ - -pinname U13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[22]} \ - -pinname U12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[23]} \ - -pinname U10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[24]} \ - -pinname C16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[25]} \ - -pinname D16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[26]} \ - -pinname E15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[27]} \ - -pinname F16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[28]} \ - -pinname G16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[29]} \ - -pinname H16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[30]} \ - -pinname J15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[31]} \ - -pinname K15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsuact \ - -pinname N7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsubre \ - -pinname N6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io errorn \ - -pinname U6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {led[0]} \ - -pinname T11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {led[1]} \ - -pinname R11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADSC \ - -pinname D10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADSP \ - -pinname C10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADV \ - -pinname B10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWE \ - -pinname F11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWa \ - -pinname F15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWb \ - -pinname G15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWc \ - -pinname H15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWd \ - -pinname J14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE1 \ - -pinname L15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE3 \ - -pinname E13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nGW \ - -pinname C11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nOE \ - -pinname E10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io reset \ - -pinname P13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io urxd1 \ - -pinname V9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io utxd1 \ - -pinname V8 \ - -fixed yes \ - -DIRECTION Inout - - - -# -# Non IO constraints -# - - -# -# Old IO constraints, commented out for reference -# - -# set_io clk50MHz -pinname D13 -fixed yes -# set_io reset -pinname P13 -fixed yes -# set_io errorn -pinname U6 -fixed yes -# set_io dsubre -pinname N6 -fixed yes -# set_io dsuact -pinname N7 -fixed yes -# set_io {led[0]} -pinname T11 -fixed yes -# set_io {led[1]} -pinname R11 -fixed yes -# set_io ahbrxd -pinname V4 -fixed yes -# set_io ahbtxd -pinname V3 -fixed yes -# set_io urxd1 -pinname V9 -fixed yes -# set_io utxd1 -pinname V8 -fixed yes -# set_io {data[0]} -pinname F10 -fixed yes -# set_io {data[1]} -pinname F9 -fixed yes -# set_io {data[2]} -pinname F8 -fixed yes -# set_io {data[3]} -pinname F7 -fixed yes -# set_io {data[4]} -pinname E6 -fixed yes -# set_io {data[5]} -pinname D5 -fixed yes -# set_io {data[6]} -pinname C4 -fixed yes -# set_io {data[7]} -pinname D3 -fixed yes -# set_io {data[8]} -pinname F18 -fixed yes -# set_io {data[9]} -pinname H18 -fixed yes -# set_io {data[10]} -pinname J18 -fixed yes -# set_io {data[11]} -pinname K18 -fixed yes -# set_io {data[12]} -pinname L18 -fixed yes -# set_io {data[13]} -pinname N18 -fixed yes -# set_io {data[14]} -pinname P18 -fixed yes -# set_io {data[15]} -pinname R18 -fixed yes -# set_io {data[16]} -pinname M16 -fixed yes -# set_io {data[17]} -pinname N17 -fixed yes -# set_io {data[18]} -pinname P16 -fixed yes -# set_io {data[19]} -pinname R13 -fixed yes -# set_io {data[20]} -pinname T13 -fixed yes -# set_io {data[21]} -pinname U13 -fixed yes -# set_io {data[22]} -pinname U12 -fixed yes -# set_io {data[23]} -pinname U10 -fixed yes -# set_io {data[24]} -pinname C16 -fixed yes -# set_io {data[25]} -pinname D16 -fixed yes -# set_io {data[26]} -pinname E15 -fixed yes -# set_io {data[27]} -pinname F16 -fixed yes -# set_io {data[28]} -pinname G16 -fixed yes -# set_io {data[29]} -pinname H16 -fixed yes -# set_io {data[30]} -pinname J15 -fixed yes -# set_io {data[31]} -pinname K15 -fixed yes -# set_io {address[0]} -pinname D18 -fixed yes -# set_io {address[1]} -pinname B17 -fixed yes -# set_io {address[2]} -pinname A17 -fixed yes -# set_io {address[3]} -pinname B16 -fixed yes -# set_io {address[4]} -pinname A16 -fixed yes -# set_io {address[5]} -pinname A15 -fixed yes -# set_io {address[6]} -pinname A14 -fixed yes -# set_io {address[7]} -pinname B13 -fixed yes -# set_io {address[8]} -pinname B9 -fixed yes -# set_io {address[9]} -pinname A8 -fixed yes -# set_io {address[10]} -pinname B7 -fixed yes -# set_io {address[11]} -pinname A6 -fixed yes -# set_io {address[12]} -pinname B6 -fixed yes -# set_io {address[13]} -pinname A5 -fixed yes -# set_io {address[14]} -pinname A4 -fixed yes -# set_io {address[15]} -pinname B3 -fixed yes -# set_io {address[16]} -pinname B18 -fixed yes -# set_io {address[17]} -pinname A13 -fixed yes -# set_io {address[18]} -pinname B12 -fixed yes -# set_io nBWa -pinname F15 -fixed yes -# set_io nBWb -pinname G15 -fixed yes -# set_io nBWc -pinname H15 -fixed yes -# set_io nBWd -pinname J14 -fixed yes -# set_io nBWE -pinname F11 -fixed yes -# set_io nADSC -pinname D10 -fixed yes -# set_io nADSP -pinname C10 -fixed yes -# set_io nADV -pinname B10 -fixed yes -# set_io nGW -pinname C11 -fixed yes -# set_io nCE1 -pinname L15 -fixed yes -# set_io CE2 -pinname K14 -fixed yes -# set_io nCE3 -pinname E13 -fixed yes -# set_io nOE -pinname E10 -fixed yes -# set_io MODE -pinname C15 -fixed yes -# set_io SSRAM_CLK -pinname D15 -fixed yes -# set_io ZZ -pinname E18 -fixed yes diff --git a/boards/Projet-LeonLFR-A3P3K-Sheldon/LFR-142200-DM-MINIAMBA.pdc b/boards/Projet-LeonLFR-A3P3K-Sheldon/LFR-142200-DM-MINIAMBA.pdc deleted file mode 100644 --- a/boards/Projet-LeonLFR-A3P3K-Sheldon/LFR-142200-DM-MINIAMBA.pdc +++ /dev/null @@ -1,123 +0,0 @@ -########################################################################## -# FILE NAME : LFR-142200-DM-MINIAMBA.pdc -# DATA : July 19, 2011 -# VERSION : 1.0 -# -# DESCRIPTION : Physical Constraints for LFR developpement model -# -# MODIFICATION HISTORY: -# 19/07/2011 1.0 Initial Release -########################################################################## - - -########################################################################## -# SYSTEM SIGNALS -########################################################################## -set_io clk50MHz -pinname D13 -fixed yes -set_io reset -pinname P13 -fixed yes - - - - - - -########################################################################## -# PUSH-BUTTON SWITCHES SIGNALS -########################################################################## -#set_io gpio(0) -pinname P7 -fixed yes -#set_io gpio(1) -pinname R5 -fixed yes - - - -########################################################################## -# LED SIGNALS -########################################################################## -set_io led\[0\] -pinname T11 -fixed yes -set_io led\[1\] -pinname R11 -fixed yes - - - -########################################################################## -# RS-232 INTERFACE SIGNALS -########################################################################## -set_io ahbrxd -pinname V4 -fixed yes -set_io ahbtxd -pinname V3 -fixed yes -set_io urxd1 -pinname V9 -fixed yes -set_io utxd1 -pinname V8 -fixed yes - - -########################################################################## -# SRAM SIGNALS -########################################################################## - - -set_io data\[0\] -pinname F10 -fixed yes -set_io data\[1\] -pinname F9 -fixed yes -set_io data\[2\] -pinname F8 -fixed yes -set_io data\[3\] -pinname F7 -fixed yes -set_io data\[4\] -pinname E6 -fixed yes -set_io data\[5\] -pinname D5 -fixed yes -set_io data\[6\] -pinname C4 -fixed yes -set_io data\[7\] -pinname D3 -fixed yes -set_io data\[8\] -pinname F18 -fixed yes -set_io data\[9\] -pinname H18 -fixed yes -set_io data\[10\] -pinname J18 -fixed yes -set_io data\[11\] -pinname K18 -fixed yes -set_io data\[12\] -pinname L18 -fixed yes -set_io data\[13\] -pinname N18 -fixed yes -set_io data\[14\] -pinname P18 -fixed yes -set_io data\[15\] -pinname R18 -fixed yes -set_io data\[16\] -pinname M16 -fixed yes -set_io data\[17\] -pinname N17 -fixed yes -set_io data\[18\] -pinname P16 -fixed yes -set_io data\[19\] -pinname R13 -fixed yes -set_io data\[20\] -pinname T13 -fixed yes -set_io data\[21\] -pinname U13 -fixed yes -set_io data\[22\] -pinname U12 -fixed yes -set_io data\[23\] -pinname U10 -fixed yes -set_io data\[24\] -pinname C16 -fixed yes -set_io data\[25\] -pinname D16 -fixed yes -set_io data\[26\] -pinname E15 -fixed yes -set_io data\[27\] -pinname F16 -fixed yes -set_io data\[28\] -pinname G16 -fixed yes -set_io data\[29\] -pinname H16 -fixed yes -set_io data\[30\] -pinname J15 -fixed yes -set_io data\[31\] -pinname K15 -fixed yes - -set_io address\[0\] -pinname D18 -fixed yes -set_io address\[1\] -pinname B17 -fixed yes -set_io address\[2\] -pinname A17 -fixed yes -set_io address\[3\] -pinname B16 -fixed yes -set_io address\[4\] -pinname A16 -fixed yes -set_io address\[5\] -pinname A15 -fixed yes -set_io address\[6\] -pinname A14 -fixed yes -set_io address\[7\] -pinname B13 -fixed yes -set_io address\[8\] -pinname B9 -fixed yes -set_io address\[9\] -pinname A8 -fixed yes -set_io address\[10\] -pinname B7 -fixed yes -set_io address\[11\] -pinname A6 -fixed yes -set_io address\[12\] -pinname B6 -fixed yes -set_io address\[13\] -pinname A5 -fixed yes -set_io address\[14\] -pinname A4 -fixed yes -set_io address\[15\] -pinname B3 -fixed yes -set_io address\[16\] -pinname B18 -fixed yes -set_io address\[17\] -pinname A13 -fixed yes -set_io address\[18\] -pinname B12 -fixed yes - - -set_io nBWa -pinname F15 -fixed yes -set_io nBWb -pinname G15 -fixed yes -set_io nBWc -pinname H15 -fixed yes -set_io nBWd -pinname J14 -fixed yes -set_io nBWE -pinname F11 -fixed yes -set_io nADSC -pinname D10 -fixed yes -set_io nADSP -pinname C10 -fixed yes -set_io nADV -pinname B10 -fixed yes -set_io nGW -pinname C11 -fixed yes -set_io nCE1 -pinname L15 -fixed yes -set_io CE2 -pinname K14 -fixed yes -set_io nCE3 -pinname E13 -fixed yes -set_io nOE -pinname E10 -fixed yes -set_io MODE -pinname C15 -fixed yes -set_io SSRAM_CLK -pinname D15 -fixed yes -set_io ZZ -pinname E18 -fixed yes diff --git a/boards/Projet-LeonLFR-A3P3K-Sheldon/Makefile.inc b/boards/Projet-LeonLFR-A3P3K-Sheldon/Makefile.inc deleted file mode 100644 --- a/boards/Projet-LeonLFR-A3P3K-Sheldon/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -TECHNOLOGY=PROASIC3 -PACKAGE=\"\" -SPEED=Std -SYNFREQ=50 - -PART=A3PE3000L -DESIGNER_PACKAGE=FBGA -DESIGNER_PINS=324 -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM - -MANUFACTURER=Actel -MGCPART=$(PART) -MGCTECHNOLOGY=PROASIC3 -MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} -LIBERO_DIE=IT14X14M4LDP -LIBERO_PACKAGE=fg$(DESIGNER_PINS) - diff --git a/boards/Projet-LeonLFR-A3P3K-Sheldon/Projet-LeonLFR-A3P3K-Sheldon.pdc b/boards/Projet-LeonLFR-A3P3K-Sheldon/Projet-LeonLFR-A3P3K-Sheldon.pdc deleted file mode 100644 --- a/boards/Projet-LeonLFR-A3P3K-Sheldon/Projet-LeonLFR-A3P3K-Sheldon.pdc +++ /dev/null @@ -1,595 +0,0 @@ -# Actel Physical design constraints file -# Generated file - -# Version: 9.1 SP3 9.1.3.4 -# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA -# Date generated: Tue Oct 18 08:21:45 2011 - - -# -# IO banks setting -# - - -# -# I/O constraints -# - -set_io CE2 \ - -pinname K14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io MODE \ - -pinname C15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SSRAM_CLK \ - -pinname D15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ZZ \ - -pinname E18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[0]} \ - -pinname D18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[1]} \ - -pinname B17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[2]} \ - -pinname A17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[3]} \ - -pinname B16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[4]} \ - -pinname A16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[5]} \ - -pinname A15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[6]} \ - -pinname A14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[7]} \ - -pinname B13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[8]} \ - -pinname B9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[9]} \ - -pinname A8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[10]} \ - -pinname B7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[11]} \ - -pinname A6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[12]} \ - -pinname B6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[13]} \ - -pinname A5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[14]} \ - -pinname A4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[15]} \ - -pinname B3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[16]} \ - -pinname B18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[17]} \ - -pinname A13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[18]} \ - -pinname B12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbrxd \ - -pinname V4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbtxd \ - -pinname V3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io clk50MHz \ - -pinname D13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[0]} \ - -pinname F10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[1]} \ - -pinname F9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[2]} \ - -pinname F8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[3]} \ - -pinname F7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[4]} \ - -pinname E6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[5]} \ - -pinname D5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[6]} \ - -pinname C4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[7]} \ - -pinname D3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[8]} \ - -pinname F18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[9]} \ - -pinname H18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[10]} \ - -pinname J18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[11]} \ - -pinname K18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[12]} \ - -pinname L18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[13]} \ - -pinname N18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[14]} \ - -pinname P18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[15]} \ - -pinname R18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[16]} \ - -pinname M16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[17]} \ - -pinname N17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[18]} \ - -pinname P16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[19]} \ - -pinname R13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[20]} \ - -pinname T13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[21]} \ - -pinname U13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[22]} \ - -pinname U12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[23]} \ - -pinname U10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[24]} \ - -pinname C16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[25]} \ - -pinname D16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[26]} \ - -pinname E15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[27]} \ - -pinname F16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[28]} \ - -pinname G16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[29]} \ - -pinname H16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[30]} \ - -pinname J15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[31]} \ - -pinname K15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsuact \ - -pinname N7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsubre \ - -pinname N6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io errorn \ - -pinname U6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {led[0]} \ - -pinname T11 \ - -fixed no \ - -DIRECTION Inout - - -set_io {led[1]} \ - -pinname R11 \ - -fixed no \ - -DIRECTION Inout - - -set_io nADSC \ - -pinname D10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADSP \ - -pinname C10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADV \ - -pinname B10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWE \ - -pinname F11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWa \ - -pinname F15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWb \ - -pinname G15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWc \ - -pinname H15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWd \ - -pinname J14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE1 \ - -pinname L15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE3 \ - -pinname E13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nGW \ - -pinname C11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nOE \ - -pinname E10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io reset \ - -pinname P13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io UART_RXD \ - -pinname V9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io UART_TXD \ - -pinname V8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {gpio[0]} -pinname J7 -fixed yes -set_io {gpio[1]} -pinname C2 -fixed yes -set_io {gpio[2]} -pinname C3 -fixed yes -set_io {gpio[3]} -pinname D4 -fixed yes -set_io {gpio[4]} -pinname E4 -fixed yes -set_io {gpio[5]} -pinname F2 -fixed yes -set_io {gpio[6]} -pinname G3 -fixed yes - -set_io {ADC_in[0]} -pinname D1 -fixed yes -set_io {ADC_in[1]} -pinname E1 -fixed yes -set_io {ADC_in[2]} -pinname F1 -fixed yes -set_io {ADC_in[3]} -pinname H1 -fixed yes -set_io {ADC_in[4]} -pinname J1 -fixed yes -set_io {ADC_out[0]} -pinname K1 -fixed yes -set_io {ADC_out[1]} -pinname L1 -fixed yes -set_io Bias_Fails -pinname G2 -fixed yes - -set_io {TEST[0]} -pinname T11 -fixed yes -set_io {TEST[1]} -pinname R11 -fixed yes -#set_io {TEST[2]} -pinname V15 -fixed yes -#set_io {TEST[3]} -pinname V14 -fixed yes - - -# -# Non IO constraints -# - - -# -# Old IO constraints, commented out for reference -# - -# set_io clk50MHz -pinname D13 -fixed yes -# set_io reset -pinname P13 -fixed yes -# set_io errorn -pinname U6 -fixed yes -# set_io dsubre -pinname N6 -fixed yes -# set_io dsuact -pinname N7 -fixed yes -# set_io {led[0]} -pinname T11 -fixed yes -# set_io {led[1]} -pinname R11 -fixed yes -# set_io ahbrxd -pinname V4 -fixed yes -# set_io ahbtxd -pinname V3 -fixed yes -# set_io urxd1 -pinname V9 -fixed yes -# set_io utxd1 -pinname V8 -fixed yes -# set_io {data[0]} -pinname F10 -fixed yes -# set_io {data[1]} -pinname F9 -fixed yes -# set_io {data[2]} -pinname F8 -fixed yes -# set_io {data[3]} -pinname F7 -fixed yes -# set_io {data[4]} -pinname E6 -fixed yes -# set_io {data[5]} -pinname D5 -fixed yes -# set_io {data[6]} -pinname C4 -fixed yes -# set_io {data[7]} -pinname D3 -fixed yes -# set_io {data[8]} -pinname F18 -fixed yes -# set_io {data[9]} -pinname H18 -fixed yes -# set_io {data[10]} -pinname J18 -fixed yes -# set_io {data[11]} -pinname K18 -fixed yes -# set_io {data[12]} -pinname L18 -fixed yes -# set_io {data[13]} -pinname N18 -fixed yes -# set_io {data[14]} -pinname P18 -fixed yes -# set_io {data[15]} -pinname R18 -fixed yes -# set_io {data[16]} -pinname M16 -fixed yes -# set_io {data[17]} -pinname N17 -fixed yes -# set_io {data[18]} -pinname P16 -fixed yes -# set_io {data[19]} -pinname R13 -fixed yes -# set_io {data[20]} -pinname T13 -fixed yes -# set_io {data[21]} -pinname U13 -fixed yes -# set_io {data[22]} -pinname U12 -fixed yes -# set_io {data[23]} -pinname U10 -fixed yes -# set_io {data[24]} -pinname C16 -fixed yes -# set_io {data[25]} -pinname D16 -fixed yes -# set_io {data[26]} -pinname E15 -fixed yes -# set_io {data[27]} -pinname F16 -fixed yes -# set_io {data[28]} -pinname G16 -fixed yes -# set_io {data[29]} -pinname H16 -fixed yes -# set_io {data[30]} -pinname J15 -fixed yes -# set_io {data[31]} -pinname K15 -fixed yes -# set_io {address[0]} -pinname D18 -fixed yes -# set_io {address[1]} -pinname B17 -fixed yes -# set_io {address[2]} -pinname A17 -fixed yes -# set_io {address[3]} -pinname B16 -fixed yes -# set_io {address[4]} -pinname A16 -fixed yes -# set_io {address[5]} -pinname A15 -fixed yes -# set_io {address[6]} -pinname A14 -fixed yes -# set_io {address[7]} -pinname B13 -fixed yes -# set_io {address[8]} -pinname B9 -fixed yes -# set_io {address[9]} -pinname A8 -fixed yes -# set_io {address[10]} -pinname B7 -fixed yes -# set_io {address[11]} -pinname A6 -fixed yes -# set_io {address[12]} -pinname B6 -fixed yes -# set_io {address[13]} -pinname A5 -fixed yes -# set_io {address[14]} -pinname A4 -fixed yes -# set_io {address[15]} -pinname B3 -fixed yes -# set_io {address[16]} -pinname B18 -fixed yes -# set_io {address[17]} -pinname A13 -fixed yes -# set_io {address[18]} -pinname B12 -fixed yes -# set_io nBWa -pinname F15 -fixed yes -# set_io nBWb -pinname G15 -fixed yes -# set_io nBWc -pinname H15 -fixed yes -# set_io nBWd -pinname J14 -fixed yes -# set_io nBWE -pinname F11 -fixed yes -# set_io nADSC -pinname D10 -fixed yes -# set_io nADSP -pinname C10 -fixed yes -# set_io nADV -pinname B10 -fixed yes -# set_io nGW -pinname C11 -fixed yes -# set_io nCE1 -pinname L15 -fixed yes -# set_io CE2 -pinname K14 -fixed yes -# set_io nCE3 -pinname E13 -fixed yes -# set_io nOE -pinname E10 -fixed yes -# set_io MODE -pinname C15 -fixed yes -# set_io SSRAM_CLK -pinname D15 -fixed yes -# set_io ZZ -pinname E18 -fixed yes diff --git a/boards/Projet-LeonLFR-A3P3K-Sheldon/default.sdc b/boards/Projet-LeonLFR-A3P3K-Sheldon/default.sdc deleted file mode 100644 --- a/boards/Projet-LeonLFR-A3P3K-Sheldon/default.sdc +++ /dev/null @@ -1,59 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc -# Written on Wed Aug 1 19:29:24 2007 -# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# -define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} -define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} - - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -# -# Path Delay -# - -# -# Attributes -# -define_global_attribute syn_useioff {1} -define_global_attribute -disable syn_netlist_hierarchy {0} -define_attribute {etx_clk} syn_noclockbuf {1} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/SP601/ICI3.ucf b/boards/SP601/ICI3.ucf deleted file mode 100644 --- a/boards/SP601/ICI3.ucf +++ /dev/null @@ -1,102 +0,0 @@ -########################################################################## -# Target Board: Xilinx Spartan6 SP601 Board ## -########################################################################## - -# ==== Clock inputs (USER CLK 27 MHz) ==== -NET "clk" LOC = "V10"; -NET "clk" PERIOD = 37ns HIGH 50%; - -# ==== Pushbuttons ==== -NET reset LOC = "N4"; -NET "BP(0)" LOC = "P4"; -NET "BP(1)" LOC = "F6"; -NET "BP(2)" LOC = "E4"; -NET "BP(3)" LOC = "F5"; - -# ==== Discrete LEDs ==== -NET led(0) LOC = "E13"; -NET led(1) LOC = "C14"; -NET led(2) LOC = "C4"; -NET led(3) LOC = "A4" | IOSTANDARD = LVCMOS25; - -# ==== DIP Switches ==== -NET sw(0) LOC = "D14"; -NET sw(1) LOC = "E12"; -NET sw(2) LOC = "F12"; -NET sw(3) LOC = "V13"; - -# ==== Rocket Interface === -NET "SCLK" LOC = "C9"; #NET "FMC_LA00_CC_N" LOC = "C9"; -NET "Gate" LOC = "D9"; #NET "FMC_LA00_CC_P" LOC = "D9"; -NET "MinF" LOC = "C11"; #NET "FMC_LA01_CC_N" LOC = "C11"; -NET "MajF" LOC = "D11"; #NET "FMC_LA01_CC_P" LOC = "D11"; -NET "Data" LOC = "A15"; #NET "FMC_LA02_N" LOC = "A15"; - -# === AMR ADC === -NET "DC_ADC_Sclk" LOC = "C15"; #NET "FMC_LA02_P" LOC = "C15"; -NET "DC_ADC_IN(0)" LOC = "A13"; #NET "FMC_LA03_N" LOC = "A13"; -NET "DC_ADC_IN(1)" LOC = "C13"; #NET "FMC_LA03_P" LOC = "C13"; -NET "DC_ADC_IN(2)" LOC = "A16"; #NET "FMC_LA04_N" LOC = "A16"; -NET "DC_ADC_IN(3)" LOC = "B16"; #NET "FMC_LA04_P" LOC = "B16"; -NET "DC_ADC_FORMAT(0)" LOC = "A14"; #NET "FMC_LA05_N" LOC = "A14"; -NET "DC_ADC_FORMAT(1)" LOC = "B14"; #NET "FMC_LA05_P" LOC = "B14"; -NET "DC_ADC_FORMAT(2)" LOC = "C12"; #NET "FMC_LA06_N" LOC = "C12"; -NET "DC_ADC_Mode(0)" LOC = "D12"; #NET "FMC_LA06_P" LOC = "D12"; -NET "DC_ADC_Mode(1)" LOC = "E8"; #NET "FMC_LA07_N" LOC = "E8"; -NET "DC_ADC_ClkDiv" LOC = "E7"; #NET "FMC_LA07_P" LOC = "E7"; -NET "DC_ADC_PWDOWN(0)" LOC = "E11"; #NET "FMC_LA08_N" LOC = "E11"; -NET "DC_ADC_PWDOWN(1)" LOC = "F11"; #NET "FMC_LA08_P" LOC = "F11"; -NET "DC_ADC_PWDOWN(2)" LOC = "F10"; #NET "FMC_LA09_N" LOC = "F10"; -NET "DC_ADC_PWDOWN(3)" LOC = "G11"; #NET "FMC_LA09_P" LOC = "G11"; -NET "DC_ADC_FSynch" LOC = "C8"; #NET "FMC_LA10_N" LOC = "C8"; -NET "DC_ADC_Synch" LOC = "D8"; #NET "FMC_LA10_P" LOC = "D8"; - - -# === Search-Coil ADC -NET "LF_ADC_Sclk" LOC = "A12"; #NET "FMC_LA11_N" LOC = "A12"; -NET "LF_ADC_IN(0)" LOC = "B12"; #NET "FMC_LA11_P" LOC = "B12"; -NET "LF_ADC_IN(1)" LOC = "C6"; #NET "FMC_LA12_N" LOC = "C6"; -NET "LF_ADC_IN(2)" LOC = "D6"; #NET "FMC_LA12_P" LOC = "D6"; -NET "LF_ADC_IN(3)" LOC = "A11"; #NET "FMC_LA13_N" LOC = "A11"; -NET "LF_ADC_FORMAT(0)" LOC = "B11"; #NET "FMC_LA13_P" LOC = "B11"; -NET "LF_ADC_FORMAT(1)" LOC = "A2"; #NET "FMC_LA14_N" LOC = "A2"; -NET "LF_ADC_FORMAT(2)" LOC = "B2"; #NET "FMC_LA14_P" LOC = "B2"; -NET "LF_ADC_Mode(0)" LOC = "F9"; #NET "FMC_LA15_N" LOC = "F9"; -NET "LF_ADC_Mode(1)" LOC = "G9"; #NET "FMC_LA15_P" LOC = "G9"; -NET "LF_ADC_ClkDiv" LOC = "T8"; #NET "FMC_LA17_CC_N" LOC = "T8"; -NET "LF_ADC_PWDOWN(0)" LOC = "R8"; #NET "FMC_LA17_CC_P" LOC = "R8"; -NET "LF_ADC_PWDOWN(1)" LOC = "T10"; #NET "FMC_LA18_CC_N" LOC = "T10"; -NET "LF_ADC_PWDOWN(2)" LOC = "R10"; #NET "FMC_LA18_CC_P" LOC = "R10"; -NET "LF_ADC_PWDOWN(3)" LOC = "P7"; #NET "FMC_LA19_N" LOC = "P7"; -NET "LF_ADC_FSynch" LOC = "N6"; #NET "FMC_LA19_P" LOC = "N6"; -NET "LF_ADC_Synch" LOC = "P8"; #NET "FMC_LA20_N" LOC = "P8"; - -NET "FMC_LA16_N" LOC = "A7"; -NET "FMC_LA16_P" LOC = "C7"; -NET "FMC_LA20_P" LOC = "N7"; -NET "FMC_LA21_N" LOC = "V4"; -NET "FMC_LA21_P" LOC = "T4"; -NET "FMC_LA22_N" LOC = "T7"; -NET "FMC_LA22_P" LOC = "R7"; -NET "FMC_LA23_N" LOC = "P6"; -NET "FMC_LA23_P" LOC = "N5"; -NET "FMC_LA24_N" LOC = "V8"; -NET "FMC_LA24_P" LOC = "U8"; -NET "FMC_LA25_N" LOC = "N11"; -NET "FMC_LA25_P" LOC = "M11"; -NET "FMC_LA26_N" LOC = "V7"; -NET "FMC_LA26_P" LOC = "U7"; -NET "FMC_LA27_N" LOC = "T11"; -NET "FMC_LA27_P" LOC = "R11"; -NET "FMC_LA28_N" LOC = "V11"; -NET "FMC_LA28_P" LOC = "U11"; -NET "FMC_LA29_N" LOC = "N8"; -NET "FMC_LA29_P" LOC = "M8"; -NET "FMC_LA30_N" LOC = "V12"; -NET "FMC_LA30_P" LOC = "T12"; -NET "FMC_LA31_N" LOC = "V6"; -NET "FMC_LA31_P" LOC = "T6"; -NET "FMC_LA32_N" LOC = "V15"; -NET "FMC_LA32_P" LOC = "U15"; -NET "FMC_LA33_N" LOC = "N9"; -NET "FMC_LA33_P" LOC = "M10"; diff --git a/boards/SP601/Makefile.inc b/boards/SP601/Makefile.inc deleted file mode 100644 --- a/boards/SP601/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# Since synplify seems to cause a synthsis error involving -# the DSP macro blocks the Spartan 3A technology -# without DSP is used for synthesis -# -TECHNOLOGY=Spartan6 -ISETECH="Spartan6" -PART=XC6SLX16 -PACKAGE=csg324 -SPEED=-2 -SYNFREQ=220 -PROMGENPAR= -c FF -s 8192 -u 0 $(TOP).bit -p mcs -spi -w -o xilinx-sp601-xc6slx16 - -MANUFACTURER=Xilinx -MGCPART=XC6SLX16$(PACKAGE) -MGCTECHNOLOGY=SPARTAN-6 -MGCPACKAGE=$(PACKAGE) diff --git a/boards/SP601/default.sdc b/boards/SP601/default.sdc deleted file mode 100644 --- a/boards/SP601/default.sdc +++ /dev/null @@ -1,61 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/magnus/grlib-gpl-1.0.18-b2950/boards/xilinx-spa3-dsp1800a/default.sdc -# Written on Mon Jul 21 10:31:29 2008 -# by Synplify Pro, Synplify Pro 8.9 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk27} -name {clk27} -freq 30 -clockgroup default_clkgroup -route 0 -define_clock {clk200_p} -name {clk200_p} -freq 200 -clockgroup ddr2_clkgroup -route 0 -define_clock {clkm} -name {clkm} -freq 80 -clockgroup main_clkgroup -route 0 -define_clock {clkml} -name {clkml} -freq 135 -clockgroup ddr_clkgroup -route 0 -define_clock {etx_clk} -name {etx_clk} -freq 25 -clockgroup phy_rx_clkgroup -route 0 -define_clock {erx_clk} -name {erx_clk} -freq 25 -clockgroup phy_tx_clkgroup -route 0 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# -define_output_delay -disable -default 10.00 -improve 0.00 -route 0.00 -ref {clk:r} -define_input_delay -disable -default 10.00 -improve 0.00 -route 0.00 -ref {clk:r} - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -# -# Path Delay -# - -# -# Attributes -# -define_global_attribute syn_useioff {1} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/SP601/default.ut b/boards/SP601/default.ut deleted file mode 100644 --- a/boards/SP601/default.ut +++ /dev/null @@ -1,24 +0,0 @@ - --g DebugBitstream:No --g Binary:no --b --g CRC:Enable --g ConfigRate:6 --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CCLK --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g Persist:No --g ReadBack --g DonePipe:No --g DriveDone:Yes diff --git a/boards/SP601/fpga-usb.cmd b/boards/SP601/fpga-usb.cmd deleted file mode 100644 --- a/boards/SP601/fpga-usb.cmd +++ /dev/null @@ -1,7 +0,0 @@ -setMode -bscan -setCable -p usb21 -identify -assignfile -p 1 -file xilinx-sp601-xc6slx16.bit -program -p 1 -quit - diff --git a/boards/SP601/fpga.cmd b/boards/SP601/fpga.cmd deleted file mode 100644 --- a/boards/SP601/fpga.cmd +++ /dev/null @@ -1,7 +0,0 @@ -setMode -bs -setCable -port auto -Identify -identifyMPM -assignFile -p 1 -file "xilinx-sp601-xc6slx16.bit" -Program -p 1 -defaultVersion 0 -quit diff --git a/boards/SP601/prom.cmd b/boards/SP601/prom.cmd deleted file mode 100644 --- a/boards/SP601/prom.cmd +++ /dev/null @@ -1,8 +0,0 @@ -setMode -bs -setCable -port auto -identify -inferir -attachflash -position 1 -spi "W25Q64BV" -assignFile -p 1 -file "xilinx-sp601-xc6slx16.mcs" -assignfiletoattachedflash -position 1 -file "xilinx-sp601-xc6slx16.mcs" -program -p 1 -dataWidth 4 -spionly -e -v -loadfpga -quit diff --git a/boards/SP601/system.ucf b/boards/SP601/system.ucf deleted file mode 100644 --- a/boards/SP601/system.ucf +++ /dev/null @@ -1,79 +0,0 @@ -NET "RESET" LOC = "N4"; -NET "CLK" LOC = "V10"; -NET "BP_0" LOC = "P4"; -NET "BP_1" LOC = "F6"; -NET "BP_2" LOC = "E4"; -NET "BP_3" LOC = "F5"; -NET "LED0" LOC = "E13"; -NET "LED1" LOC = "C14"; -NET "LED2" LOC = "C4"; -NET "LED3" LOC = "A4"; -NET "FMC_LA00_CC_N" LOC = "C9"; -NET "FMC_LA00_CC_P" LOC = "D9"; -NET "FMC_LA01_CC_N" LOC = "C11"; -NET "FMC_LA01_CC_P" LOC = "D11"; -NET "FMC_LA02_N" LOC = "A15"; -NET "FMC_LA02_P" LOC = "C15"; -NET "FMC_LA03_N" LOC = "A13"; -NET "FMC_LA03_P" LOC = "C13"; -NET "FMC_LA04_N" LOC = "A16"; -NET "FMC_LA04_P" LOC = "B16"; -NET "FMC_LA05_N" LOC = "A14"; -NET "FMC_LA05_P" LOC = "B14"; -NET "FMC_LA06_N" LOC = "C12"; -NET "FMC_LA06_P" LOC = "D12"; -NET "FMC_LA07_N" LOC = "E8"; -NET "FMC_LA07_P" LOC = "E7"; -NET "FMC_LA08_N" LOC = "E11"; -NET "FMC_LA08_P" LOC = "F11"; -NET "FMC_LA09_N" LOC = "F10"; -NET "FMC_LA09_P" LOC = "G11"; -NET "FMC_LA10_N" LOC = "C8"; -NET "FMC_LA10_P" LOC = "D8"; -NET "FMC_LA11_N" LOC = "A12"; -NET "FMC_LA11_P" LOC = "B12"; -NET "FMC_LA12_N" LOC = "C6"; -NET "FMC_LA12_P" LOC = "D6"; -NET "FMC_LA13_N" LOC = "A11"; -NET "FMC_LA13_P" LOC = "B11"; -NET "FMC_LA14_N" LOC = "A2"; -NET "FMC_LA14_P" LOC = "B2"; -NET "FMC_LA15_N" LOC = "F9"; -NET "FMC_LA15_P" LOC = "G9"; -NET "FMC_LA16_N" LOC = "A7"; -NET "FMC_LA16_P" LOC = "C7"; -NET "FMC_LA17_CC_N" LOC = "T8"; -NET "FMC_LA17_CC_P" LOC = "R8"; -NET "FMC_LA18_CC_N" LOC = "T10"; -NET "FMC_LA18_CC_P" LOC = "R10"; -NET "FMC_LA19_N" LOC = "P7"; -NET "FMC_LA19_P" LOC = "N6"; -NET "FMC_LA20_N" LOC = "P8"; -NET "FMC_LA20_P" LOC = "N7"; -NET "FMC_LA21_N" LOC = "V4"; -NET "FMC_LA21_P" LOC = "T4"; -NET "FMC_LA22_N" LOC = "T7"; -NET "FMC_LA22_P" LOC = "R7"; -NET "FMC_LA23_N" LOC = "P6"; -NET "FMC_LA23_P" LOC = "N5"; -NET "FMC_LA24_N" LOC = "V8"; -NET "FMC_LA24_P" LOC = "U8"; -NET "FMC_LA25_N" LOC = "N11"; -NET "FMC_LA25_P" LOC = "M11"; -NET "FMC_LA26_N" LOC = "V7"; -NET "FMC_LA26_P" LOC = "U7"; -NET "FMC_LA27_N" LOC = "T11"; -NET "FMC_LA27_P" LOC = "R11"; -NET "FMC_LA28_N" LOC = "V11"; -NET "FMC_LA28_P" LOC = "U11"; -NET "FMC_LA29_N" LOC = "N8"; -NET "FMC_LA29_P" LOC = "M8"; -NET "FMC_LA30_N" LOC = "V12"; -NET "FMC_LA30_P" LOC = "T12"; -NET "FMC_LA31_N" LOC = "V6"; -NET "FMC_LA31_P" LOC = "T6"; -NET "FMC_LA32_N" LOC = "V15"; -NET "FMC_LA32_P" LOC = "U15"; -NET "FMC_LA33_N" LOC = "N9"; -NET "FMC_LA33_P" LOC = "M10"; - diff --git a/boards/UT8ER1M32-test-board/Makefile.inc b/boards/UT8ER1M32-test-board/Makefile.inc deleted file mode 100644 --- a/boards/UT8ER1M32-test-board/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -PACKAGE=\"\" -SPEED=Std -SYNFREQ=50 - -TECHNOLOGY=ProASIC3E -LIBERO_DIE=IT14X14M4 -PART=A3PE3000 - -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM -DESIGNER_PACKAGE=FBGA -DESIGNER_PINS=324 - -MANUFACTURER=Actel -MGCTECHNOLOGY=Proasic3 -MGCPART=$(PART) -MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} -LIBERO_PACKAGE=fg$(DESIGNER_PINS) - - diff --git a/boards/UT8ER1M32-test-board/default.pdc b/boards/UT8ER1M32-test-board/default.pdc deleted file mode 100644 --- a/boards/UT8ER1M32-test-board/default.pdc +++ /dev/null @@ -1,453 +0,0 @@ -# Actel Physical design constraints file -# Generated file - -# Version: 9.1 SP3 9.1.3.4 -# Family: ProASIC3E , Die: A3PE3000 , Package: 324 FBGA -# Date generated: Tue Dec 23 19:40:04 2014 - - -# -# IO banks setting -# - - -# -# I/O constraints -# - -set_io LED0 \ - -pinname R13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io LED1 \ - -pinname P13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io LED2 \ - -pinname N11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io RXD1 \ - -pinname N10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io RXD2 \ - -pinname F6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_A[0]} \ - -pinname T12 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[1]} \ - -pinname U13 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[2]} \ - -pinname T13 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[3]} \ - -pinname N15 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[4]} \ - -pinname P17 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[5]} \ - -pinname N13 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[6]} \ - -pinname M16 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[7]} \ - -pinname M13 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[8]} \ - -pinname U12 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[9]} \ - -pinname V11 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[10]} \ - -pinname V13 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[11]} \ - -pinname V14 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[12]} \ - -pinname V15 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[13]} \ - -pinname P16 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[14]} \ - -pinname N16 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[15]} \ - -pinname V16 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[16]} \ - -pinname V17 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[17]} \ - -pinname U18 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_A[18]} \ - -pinname R18 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io {SRAM_DQ[0]} \ - -pinname T18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[1]} \ - -pinname L15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[2]} \ - -pinname K18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[3]} \ - -pinname G17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[4]} \ - -pinname K17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[5]} \ - -pinname H18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[6]} \ - -pinname L18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[7]} \ - -pinname J18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[8]} \ - -pinname M17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[9]} \ - -pinname J17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[10]} \ - -pinname N18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[11]} \ - -pinname J13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[12]} \ - -pinname N17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[13]} \ - -pinname K13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[14]} \ - -pinname P18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[15]} \ - -pinname K14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[16]} \ - -pinname K15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[17]} \ - -pinname B18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[18]} \ - -pinname D16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[19]} \ - -pinname D15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[20]} \ - -pinname C18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[21]} \ - -pinname E15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[22]} \ - -pinname D18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[23]} \ - -pinname F15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[24]} \ - -pinname E18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[25]} \ - -pinname G15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[26]} \ - -pinname F17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[27]} \ - -pinname H15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[28]} \ - -pinname F18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[29]} \ - -pinname J15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[30]} \ - -pinname D11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {SRAM_DQ[31]} \ - -pinname C16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SRAM_MBE \ - -pinname D13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SRAM_nBUSY \ - -pinname D12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SRAM_nCE1 \ - -pinname C17 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io SRAM_nCE2 \ - -pinname B17 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io SRAM_nOE \ - -pinname J14 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io SRAM_nWE \ - -pinname B16 \ - -fixed yes \ - -DIRECTION Inout \ - -register yes - - -set_io TXD1 \ - -pinname N12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io TXD2 \ - -pinname G6 \ - -fixed yes \ - -DIRECTION Inout - - -#set_io clk_49 \ -# -pinname F8 \ -# -fixed yes \ -# -DIRECTION Inout - - -set_io clk_50 \ - -pinname F7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCTS1 \ - -pinname L13 \ - -fixed yes \ - -DIRECTION Inout - - -#set_io nRTS1 \ -# -pinname M9 \ -# -fixed yes \ -# -DIRECTION Inout - - -set_io reset \ - -pinname F16 \ - -fixed yes \ - -DIRECTION Inout - diff --git a/boards/digilent-xc3s1600e/system.ucf b/boards/digilent-xc3s1600e/system.ucf deleted file mode 100644 --- a/boards/digilent-xc3s1600e/system.ucf +++ /dev/null @@ -1,280 +0,0 @@ -## -########################################################################### -## Copyright(C) 2006 by Xilinx, Inc. All rights reserved. ## -## ## -## You may copy and modify these files for your own internal use solely ## -## with Xilinx programmable logic devices and Xilinx EDK system or ## -## create IP modules solely for Xilinx programmable logic devices and ## -## Xilinx EDK system. No rights are granted to distribute any files ## -## unless they are distributed in Xilinx programmable logic devices. ## -## ## -## Source code is provided "as-is", with no obligation on the part of ## -## Xilinx to provide support. ## -## ## -########################################################################### -# -########################################################################## -# Target Board: Xilinx Spartan-3E 1600E Board Rev A ## -# Family: spartan3e ## -# Device: XC3S1600e ## -# Package: FG320 ## -# Speed Grade: -4 ## -########################################################################## -# - -Net sys_clk_pin LOC=B8; -Net sys_clk_pin IOSTANDARD = LVCMOS33; -Net sys_rst_pin LOC=K17; -Net sys_rst_pin IOSTANDARD = LVCMOS33; -Net sys_rst_pin PULLDOWN; - -## System level constraints -Net sys_clk_pin TNM_NET = sys_clk_pin; -TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 14600 ps; -Net sys_rst_pin TIG; - -NET "dlmb_port_BRAM_Clk" TNM_NET = "sys_clk_s"; -NET "ddr_dev_clk_s" TNM_NET = "Device_Clk"; - -NET "fpga_0_DDR_CLK_FB" TNM_NET = "fpga_0_DDR_CLK_FB"; -TIMESPEC "TS_fpga_0_DDR_CLK_FB" = PERIOD "fpga_0_DDR_CLK_FB" 7.2 ns HIGH 50 %; - - -NET "DBG_CLK_s" TNM_NET = "DBG_CLK_s"; -TIMESPEC "TS_DBG_CLK_s" = PERIOD "DBG_CLK_s" 30 MHz HIGH 50 %; - -TIMESPEC "TS_OPB_TO_DDR" = FROM "sys_clk_s" TO "Device_Clk" TIG; -TIMESPEC "TS_DDR_TO_OPB" = FROM "Device_Clk" TO "sys_clk_s" TIG; - - -## IO Devices constraints - -#### Module RS232_DTE constraints - -Net fpga_0_RS232_DTE_RX_pin LOC=U8; -Net fpga_0_RS232_DTE_RX_pin IOSTANDARD = LVCMOS33; -Net fpga_0_RS232_DTE_TX_pin LOC=M13; -Net fpga_0_RS232_DTE_TX_pin IOSTANDARD = LVCMOS33; - -#### Module FLASH_16Mx8 constraints - -Net fpga_0_FLASH_16Mx8_Mem_A_pin<31> LOC=h17; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<31> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<30> LOC=j13; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<30> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<29> LOC=j12; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<29> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<28> LOC=j14; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<28> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<27> LOC=j15; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<27> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<26> LOC=j16; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<26> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<25> LOC=j17; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<25> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<24> LOC=k14; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<24> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<23> LOC=k15; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<23> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<22> LOC=k12; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<22> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<21> LOC=k13; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<21> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<20> LOC=l15; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<20> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<19> LOC=l16; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<19> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<18> LOC=t18; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<18> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<17> LOC=r18; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<17> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<16> LOC=t17; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<16> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<15> LOC=u18; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<15> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<14> LOC=t16; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<14> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<13> LOC=u15; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<13> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<12> LOC=v15; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<12> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<11> LOC=t12; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<11> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<10> LOC=v13; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<10> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<9> LOC=v12; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<9> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<8> LOC=n11; -Net fpga_0_FLASH_16Mx8_Mem_A_pin<8> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<7> LOC=n10; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<6> LOC=p10; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<5> LOC=r10; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<4> LOC=v9; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<3> LOC=u9; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<2> LOC=r9; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<1> LOC=m9; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<0> LOC=n9; -Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_OEN_pin LOC=c18; -Net fpga_0_FLASH_16Mx8_Mem_OEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_WEN_pin LOC=d17; -Net fpga_0_FLASH_16Mx8_Mem_WEN_pin IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_Mem_CEN_pin<0> LOC=d16; -Net fpga_0_FLASH_16Mx8_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_FLASH_16Mx8_emc_ben_gnd_pin LOC=c17; -Net fpga_0_FLASH_16Mx8_emc_ben_gnd_pin IOSTANDARD = LVCMOS33; - -#### Module DDR_SDRAM_32Mx16 constraints - -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin LOC=J5; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin LOC=J4; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<0> LOC=P2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<1> LOC=N5; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<2> LOC=T2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<3> LOC=N4; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<4> LOC=H2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<5> LOC=H1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<6> LOC=H3; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<7> LOC=H4; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<8> LOC=E4; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<9> LOC=P1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<10> LOC=R2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<11> LOC=R3; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<12> LOC=T1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<0> LOC=K6; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<1> LOC=K5; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin LOC=C2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin LOC=K3; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin LOC=K4; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin LOC=C1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin LOC=D1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<0> LOC=J1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<0> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<1> LOC=J2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<1> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<0> LOC=G3; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<0> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> LOC=L6; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> LOC=H5; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> LOC=H6; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> LOC=G5; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> LOC=G6; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> LOC=F2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> LOC=F1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> LOC=E1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> LOC=E2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> LOC=M6; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> LOC=M5; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> LOC=M4; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> LOC=M3; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> LOC=L4; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> LOC=L3; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> LOC=L1; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> PULLUP; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> LOC=L2; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> IOSTANDARD = SSTL2_I; -Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> PULLUP; - -#### Module Ethernet_MAC constraints - -Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=T7; -Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=V3; -Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=U13; -Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=V2; -Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=V8; -Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=T11; -Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=U11; -Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=V14; -Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=U6; -Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U14; -Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=P16; -Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=R11; -Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T15; -Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=R5; -Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=T5; -Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_Mii_clk_pin LOC=P9; -Net fpga_0_Ethernet_MAC_PHY_Mii_clk_pin IOSTANDARD = LVCMOS33; -Net fpga_0_Ethernet_MAC_PHY_Mii_data_pin LOC=U5; -Net fpga_0_Ethernet_MAC_PHY_Mii_data_pin IOSTANDARD = LVCMOS33; - -Net fpga_0_DDR_CLK_FB LOC=B9; -Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS33; - -Net SPI_ROM_CS_pin LOC=U3 | PULLUP; ## This is to force the SPI ROM to not be selected(drive high) -Net SPI_ROM_CS_pin IOSTANDARD = LVCMOS33; - diff --git a/boards/digilent-xc3s1600e/system2.ucf b/boards/digilent-xc3s1600e/system2.ucf deleted file mode 100644 --- a/boards/digilent-xc3s1600e/system2.ucf +++ /dev/null @@ -1,97 +0,0 @@ -# ==== Clock inputs (CLK) ==== -NET "clk_in" LOC = "C9" | IOSTANDARD = LVCMOS33 ; -NET "clk_in" PERIOD = 20ns HIGH 40%; - - -# ==== Pushbuttons (BTN) ==== -#NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; -#NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; -#NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; -NET "reset_in" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; -#NET "btn0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; -#NET "btn1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; -#NET "btn2" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; - - -# ==== Discrete LEDs (LED) ==== -# These are shared connections with the FX2 connector -NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "led<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "led<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "led<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "led<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; - -# ==== Rotary Encoder ==== -NET "rotary<0>" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ; -NET "rotary<1>" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ; -NET "rotary<2>" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ; - -# ==== Slide Switches (SW) ==== -NET "sw<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; -NET "sw<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; -NET "sw<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; -NET "sw<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; - -# ==== RS-232 Serial Ports (RS232) ==== -NET "uart_rx" LOC = "R7" | IOSTANDARD = LVTTL ; -NET "uart_tx" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; - - -# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V) -NET "ddr_addr<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ; -NET "ddr_addr<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ; -NET "ddr_ba<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ; -NET "ddr_ba<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ; -NET "ddr_cas_n" LOC = "C2" | IOSTANDARD = SSTL2_I ; -NET "ddr_clk_n" LOC = "J4" | IOSTANDARD = SSTL2_I ; -NET "ddr_clk" LOC = "J5" | IOSTANDARD = SSTL2_I ; -NET "ddr_cke" LOC = "K3" | IOSTANDARD = SSTL2_I ; -NET "ddr_cs_n" LOC = "K4" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ; -NET "ddr_dq<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ; -NET "ddr_dm<0>" LOC = "J2" | IOSTANDARD = SSTL2_I ; -NET "ddr_dqs<0>" LOC = "L6" | IOSTANDARD = SSTL2_I ; -NET "ddr_ras_n" LOC = "C1" | IOSTANDARD = SSTL2_I ; -NET "ddr_dm<1>" LOC = "J1" | IOSTANDARD = SSTL2_I ; -NET "ddr_dqs<1>" LOC = "G3" | IOSTANDARD = SSTL2_I ; -NET "ddr_we_n" LOC = "D1" | IOSTANDARD = SSTL2_I ; - -# Path to allow connection to top DCM connection -NET "ddr_clk_fb" LOC = "B9" | IOSTANDARD = LVCMOS33 ; -#NET "ddr_clk_fb" PERIOD = 7.5ns HIGH 40%; - -# Prohibit VREF pins -CONFIG PROHIBIT = D2; -CONFIG PROHIBIT = G4; -CONFIG PROHIBIT = J6; -CONFIG PROHIBIT = L5; -CONFIG PROHIBIT = R4; - diff --git a/boards/em-LeonLPP-A3PE3kL-v2/Makefile.inc b/boards/em-LeonLPP-A3PE3kL-v2/Makefile.inc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v2/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -PACKAGE=\"\" -SPEED=Std -SYNFREQ=50 - -TECHNOLOGY=ProASIC3E -LIBERO_DIE=IT14X14M4 -PART=A3PE3000 - -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM -DESIGNER_PACKAGE=FBGA -DESIGNER_PINS=324 - -MANUFACTURER=Actel -MGCTECHNOLOGY=Proasic3 -MGCPART=$(PART) -MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} -LIBERO_PACKAGE=fg$(DESIGNER_PINS) - diff --git a/boards/em-LeonLPP-A3PE3kL-v2/default.sdc b/boards/em-LeonLPP-A3PE3kL-v2/default.sdc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v2/default.sdc +++ /dev/null @@ -1,59 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc -# Written on Wed Aug 1 19:29:24 2007 -# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# -define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} -define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} - - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -# -# Path Delay -# - -# -# Attributes -# -define_global_attribute syn_useioff {1} -define_global_attribute -disable syn_netlist_hierarchy {0} -define_attribute {etx_clk} syn_noclockbuf {1} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc b/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc +++ /dev/null @@ -1,117 +0,0 @@ -set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout -set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout -set_io reset -pinname N18 -fixed yes -DIRECTION Inout - -set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout -set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout -set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout -set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout -set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout -set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout -set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout -set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout -set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout -set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout -set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout -set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout -set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout -set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout -set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout -set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout -set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout -set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout -set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout -set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout - -set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout -set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout -set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout -set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout -set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout -set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout -set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout -set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout -set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout -set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout -set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout -set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout -set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout -set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout -set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout -set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout -set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout -set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout -set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout -set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout -set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout -set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout -set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout -set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout -set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout -set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout -set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout -set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout -set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout -set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout -set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout -set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout - -set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout -set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout -set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout -set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout -set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout -set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout -set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout - -set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout -set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout -set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout -set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout - -set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout -set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout -set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout -set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout - -set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout -set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout -set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout - -set_io ahbtxd -pinname J12 -fixed yes -DIRECTION Inout -#set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout -set_io ahbrxd -pinname L16 -fixed yes -DIRECTION Inout -#set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout -set_io urxd1 -pinname M16 -fixed yes -DIRECTION Inout -set_io utxd1 -pinname L13 -fixed yes -DIRECTION Inout -set_io errorn -pinname P6 -fixed yes -DIRECTION Inout -#set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout -#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout - -set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout - -set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout - -set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout - -set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout -set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout -set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout -set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout -set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout -set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout -set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout -set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout -set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout -set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout -set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout -set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout -set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout -set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout diff --git a/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL_testData29.pdc b/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL_testData29.pdc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL_testData29.pdc +++ /dev/null @@ -1,8 +0,0 @@ -set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout -set_io data_29 -pinname J18 -fixed yes -DIRECTION Inout - -set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout -set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout -set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout - -set_io Reset -pinname N18 -fixed yes -DIRECTION Inout diff --git a/boards/em-LeonLPP-A3PE3kL-v2/lpp-dm-sheldon-a3pe3000.pdc b/boards/em-LeonLPP-A3PE3kL-v2/lpp-dm-sheldon-a3pe3000.pdc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v2/lpp-dm-sheldon-a3pe3000.pdc +++ /dev/null @@ -1,611 +0,0 @@ -# Actel Physical design constraints file -# Generated file - -# Version: 9.1 SP3 9.1.3.4 -# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA -# Date generated: Tue Oct 18 08:21:45 2011 - -# -# IO banks setting -# - - -# -# I/O constraints -# - -#set_io {scm_adc[0]} -pinname D1 -fixed yes -DIRECTION Inout -#set_io {scm_adc[1]} -pinname E1 -fixed yes -DIRECTION Inout -#set_io {scm_adc[2]} -pinname F1 -fixed yes -DIRECTION Inout -#set_io {bias_adc[0]} -pinname H1 -fixed yes -DIRECTION Inout -#set_io {bias_adc[1]} -pinname J1 -fixed yes -DIRECTION Inout -#set_io {bias_adc[2]} -pinname N1 -fixed yes -DIRECTION Inout -#set_io {bias_adc[3]} -pinname P1 -fixed yes -DIRECTION Inout -#set_io {bias_adc[4]} -pinname R1 -fixed yes -DIRECTION Inout - -#set_io {sdo_adc[0]} -pinname D1 -fixed yes -DIRECTION Inout -#set_io {sdo_adc[1]} -pinname E1 -fixed yes -DIRECTION Inout -#set_io {sdo_adc[2]} -pinname F1 -fixed yes -DIRECTION Inout -#set_io {sdo_adc[3]} -pinname H1 -fixed yes -DIRECTION Inout -#set_io {sdo_adc[4]} -pinname J1 -fixed yes -DIRECTION Inout -#set_io {sdo_adc[5]} -pinname N1 -fixed yes -DIRECTION Inout -#set_io {sdo_adc[6]} -pinname P1 -fixed yes -DIRECTION Inout -#set_io {sdo_adc[7]} -pinname R1 -fixed yes -DIRECTION Inout - -#set_io CNV_CH1 -pinname K1 -fixed yes -DIRECTION Inout -#set_io SCK_CH1 -pinname L1 -fixed yes -DIRECTION Inout -#set_io Bias_Fails -pinname G2 -fixed yes -DIRECTION Inout - -set_io CE2 \ - -pinname K14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io MODE \ - -pinname C15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io SSRAM_CLK \ - -pinname D15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ZZ \ - -pinname E18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[0]} \ - -pinname D18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[1]} \ - -pinname B17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[2]} \ - -pinname A17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[3]} \ - -pinname B16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[4]} \ - -pinname A16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[5]} \ - -pinname A15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[6]} \ - -pinname A14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[7]} \ - -pinname B13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[8]} \ - -pinname B9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[9]} \ - -pinname A8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[10]} \ - -pinname B7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[11]} \ - -pinname A6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[12]} \ - -pinname B6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[13]} \ - -pinname A5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[14]} \ - -pinname A4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[15]} \ - -pinname B3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[16]} \ - -pinname B18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[17]} \ - -pinname A13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {address[18]} \ - -pinname B12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbrxd \ - -pinname V4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io ahbtxd \ - -pinname V3 \ - -fixed yes \ - -DIRECTION Inout - -#set_io urxd1 \ -# -pinname V9 \ -# -fixed yes \ -# -DIRECTION Inout - -set_io utxd1 \ - -pinname V8 \ - -fixed yes \ - -DIRECTION Inout - -set_io clk49_152MHz \ - -pinname D13 \ - -fixed yes \ - -DIRECTION Inout - -set_io clk100MHz \ - -pinname D14 \ - -fixed yes \ - -DIRECTION Inout - -set_io {data[0]} \ - -pinname F10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[1]} \ - -pinname F9 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[2]} \ - -pinname F8 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[3]} \ - -pinname F7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[4]} \ - -pinname E6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[5]} \ - -pinname D5 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[6]} \ - -pinname C4 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[7]} \ - -pinname D3 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[8]} \ - -pinname F18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[9]} \ - -pinname H18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[10]} \ - -pinname J18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[11]} \ - -pinname K18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[12]} \ - -pinname L18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[13]} \ - -pinname N18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[14]} \ - -pinname P18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[15]} \ - -pinname R18 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[16]} \ - -pinname M16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[17]} \ - -pinname N17 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[18]} \ - -pinname P16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[19]} \ - -pinname R13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[20]} \ - -pinname T13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[21]} \ - -pinname U13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[22]} \ - -pinname U12 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[23]} \ - -pinname U10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[24]} \ - -pinname C16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[25]} \ - -pinname D16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[26]} \ - -pinname E15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[27]} \ - -pinname F16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[28]} \ - -pinname G16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[29]} \ - -pinname H16 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[30]} \ - -pinname J15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {data[31]} \ - -pinname K15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsuact \ - -pinname N7 \ - -fixed yes \ - -DIRECTION Inout - - -set_io dsubre \ - -pinname N6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io errorn \ - -pinname U6 \ - -fixed yes \ - -DIRECTION Inout - - -set_io {led[0]} \ - -pinname T11 \ - -fixed no \ - -DIRECTION Inout - - -set_io {led[1]} \ - -pinname R11 \ - -fixed no \ - -DIRECTION Inout - - -set_io nADSC \ - -pinname D10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADSP \ - -pinname C10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nADV \ - -pinname B10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWE \ - -pinname F11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWa \ - -pinname F15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWb \ - -pinname G15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWc \ - -pinname H15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nBWd \ - -pinname J14 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE1 \ - -pinname L15 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nCE3 \ - -pinname E13 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nGW \ - -pinname C11 \ - -fixed yes \ - -DIRECTION Inout - - -set_io nOE \ - -pinname E10 \ - -fixed yes \ - -DIRECTION Inout - - -set_io reset \ - -pinname P13 \ - -fixed yes \ - -DIRECTION Inout - - - -set_io {gpio[0]} -pinname J7 -fixed yes -set_io {gpio[1]} -pinname C2 -fixed yes -set_io {gpio[2]} -pinname C3 -fixed yes -set_io {gpio[3]} -pinname D4 -fixed yes -set_io {gpio[4]} -pinname E4 -fixed yes -set_io {gpio[5]} -pinname F2 -fixed yes -set_io {gpio[6]} -pinname G3 -fixed yes - -set_io spw1_din -pinname V11 -fixed yes -set_io spw1_sin -pinname V13 -fixed yes -set_io spw1_dout -pinname V15 -fixed yes -set_io spw1_sout -pinname V14 -fixed yes -set_io spw1_en_bar -pinname V16 -fixed yes -set_io spw2_en_bar -pinname T18 -fixed yes - - -# -# Non IO constraints -# - - -# -# Old IO constraints, commented out for reference -# - -# set_io clk50MHz -pinname D13 -fixed yes -# set_io reset -pinname P13 -fixed yes -# set_io errorn -pinname U6 -fixed yes -# set_io dsubre -pinname N6 -fixed yes -# set_io dsuact -pinname N7 -fixed yes -# set_io {led[0]} -pinname T11 -fixed yes -# set_io {led[1]} -pinname R11 -fixed yes -# set_io ahbrxd -pinname V4 -fixed yes -# set_io ahbtxd -pinname V3 -fixed yes -# set_io urxd1 -pinname V9 -fixed yes -# set_io utxd1 -pinname V8 -fixed yes -# set_io {data[0]} -pinname F10 -fixed yes -# set_io {data[1]} -pinname F9 -fixed yes -# set_io {data[2]} -pinname F8 -fixed yes -# set_io {data[3]} -pinname F7 -fixed yes -# set_io {data[4]} -pinname E6 -fixed yes -# set_io {data[5]} -pinname D5 -fixed yes -# set_io {data[6]} -pinname C4 -fixed yes -# set_io {data[7]} -pinname D3 -fixed yes -# set_io {data[8]} -pinname F18 -fixed yes -# set_io {data[9]} -pinname H18 -fixed yes -# set_io {data[10]} -pinname J18 -fixed yes -# set_io {data[11]} -pinname K18 -fixed yes -# set_io {data[12]} -pinname L18 -fixed yes -# set_io {data[13]} -pinname N18 -fixed yes -# set_io {data[14]} -pinname P18 -fixed yes -# set_io {data[15]} -pinname R18 -fixed yes -# set_io {data[16]} -pinname M16 -fixed yes -# set_io {data[17]} -pinname N17 -fixed yes -# set_io {data[18]} -pinname P16 -fixed yes -# set_io {data[19]} -pinname R13 -fixed yes -# set_io {data[20]} -pinname T13 -fixed yes -# set_io {data[21]} -pinname U13 -fixed yes -# set_io {data[22]} -pinname U12 -fixed yes -# set_io {data[23]} -pinname U10 -fixed yes -# set_io {data[24]} -pinname C16 -fixed yes -# set_io {data[25]} -pinname D16 -fixed yes -# set_io {data[26]} -pinname E15 -fixed yes -# set_io {data[27]} -pinname F16 -fixed yes -# set_io {data[28]} -pinname G16 -fixed yes -# set_io {data[29]} -pinname H16 -fixed yes -# set_io {data[30]} -pinname J15 -fixed yes -# set_io {data[31]} -pinname K15 -fixed yes -# set_io {address[0]} -pinname D18 -fixed yes -# set_io {address[1]} -pinname B17 -fixed yes -# set_io {address[2]} -pinname A17 -fixed yes -# set_io {address[3]} -pinname B16 -fixed yes -# set_io {address[4]} -pinname A16 -fixed yes -# set_io {address[5]} -pinname A15 -fixed yes -# set_io {address[6]} -pinname A14 -fixed yes -# set_io {address[7]} -pinname B13 -fixed yes -# set_io {address[8]} -pinname B9 -fixed yes -# set_io {address[9]} -pinname A8 -fixed yes -# set_io {address[10]} -pinname B7 -fixed yes -# set_io {address[11]} -pinname A6 -fixed yes -# set_io {address[12]} -pinname B6 -fixed yes -# set_io {address[13]} -pinname A5 -fixed yes -# set_io {address[14]} -pinname A4 -fixed yes -# set_io {address[15]} -pinname B3 -fixed yes -# set_io {address[16]} -pinname B18 -fixed yes -# set_io {address[17]} -pinname A13 -fixed yes -# set_io {address[18]} -pinname B12 -fixed yes -# set_io nBWa -pinname F15 -fixed yes -# set_io nBWb -pinname G15 -fixed yes -# set_io nBWc -pinname H15 -fixed yes -# set_io nBWd -pinname J14 -fixed yes -# set_io nBWE -pinname F11 -fixed yes -# set_io nADSC -pinname D10 -fixed yes -# set_io nADSP -pinname C10 -fixed yes -# set_io nADV -pinname B10 -fixed yes -# set_io nGW -pinname C11 -fixed yes -# set_io nCE1 -pinname L15 -fixed yes -# set_io CE2 -pinname K14 -fixed yes -# set_io nCE3 -pinname E13 -fixed yes -# set_io nOE -pinname E10 -fixed yes -# set_io MODE -pinname C15 -fixed yes -# set_io SSRAM_CLK -pinname D15 -fixed yes -# set_io ZZ -pinname E18 -fixed yes diff --git a/designs/MINI-LFR-WFRM-GPIO/MINI_LFR_top.vhd b/designs/MINI-LFR-WFRM-GPIO/MINI_LFR_top.vhd deleted file mode 100644 --- a/designs/MINI-LFR-WFRM-GPIO/MINI_LFR_top.vhd +++ /dev/null @@ -1,513 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; ---USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY MINI_LFR_top IS - - PORT ( - clk_50 : IN STD_LOGIC; - clk_49 : IN STD_LOGIC; - reset : IN STD_LOGIC; - --BPs - BP0 : IN STD_LOGIC; - BP1 : IN STD_LOGIC; - --LEDs - LED0 : OUT STD_LOGIC; - LED1 : OUT STD_LOGIC; - LED2 : OUT STD_LOGIC; - --UARTs - TXD1 : IN STD_LOGIC; - RXD1 : OUT STD_LOGIC; - nCTS1 : OUT STD_LOGIC; - nRTS1 : IN STD_LOGIC; - - TXD2 : IN STD_LOGIC; - RXD2 : OUT STD_LOGIC; - nCTS2 : OUT STD_LOGIC; - nDTR2 : IN STD_LOGIC; - nRTS2 : IN STD_LOGIC; - nDCD2 : OUT STD_LOGIC; - - --EXT CONNECTOR - IO0 : INOUT STD_LOGIC; - IO1 : INOUT STD_LOGIC; - IO2 : INOUT STD_LOGIC; - IO3 : INOUT STD_LOGIC; - IO4 : INOUT STD_LOGIC; - IO5 : INOUT STD_LOGIC; - IO6 : INOUT STD_LOGIC; - IO7 : INOUT STD_LOGIC; - IO8 : INOUT STD_LOGIC; - IO9 : INOUT STD_LOGIC; - IO10 : INOUT STD_LOGIC; - IO11 : INOUT STD_LOGIC; - - --SPACE WIRE - SPW_EN : OUT STD_LOGIC; -- 0 => off - SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK - SPW_NOM_SIN : IN STD_LOGIC; - SPW_NOM_DOUT : OUT STD_LOGIC; - SPW_NOM_SOUT : OUT STD_LOGIC; - SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK - SPW_RED_SIN : IN STD_LOGIC; - SPW_RED_DOUT : OUT STD_LOGIC; - SPW_RED_SOUT : OUT STD_LOGIC; - -- MINI LFR ADC INPUTS - ADC_nCS : OUT STD_LOGIC; - ADC_CLK : OUT STD_LOGIC; - ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - - -- SRAM - SRAM_nWE : OUT STD_LOGIC; - SRAM_CE : OUT STD_LOGIC; - SRAM_nOE : OUT STD_LOGIC; - SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END MINI_LFR_top; - - -ARCHITECTURE beh OF MINI_LFR_top IS - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - -- - SIGNAL errorn : STD_LOGIC; - -- UART AHB --------------------------------------------------------------- - SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data - SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data - SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data - -- - SIGNAL I00_s : STD_LOGIC; - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - -- - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; --- SIGNAL clkmn : STD_ULOGIC; --- SIGNAL txclk : STD_ULOGIC; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_nCS_sig : STD_LOGIC; - SIGNAL ADC_CLK_sig : STD_LOGIC; - SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); - - SIGNAL bias_fail_sw_sig : STD_LOGIC; - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - - PROCESS(clk_50) - BEGIN - IF clk_50'EVENT AND clk_50 = '1' THEN - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - LED0 <= '0'; - LED1 <= '0'; - LED2 <= '0'; - --IO1 <= '0'; - --IO2 <= '1'; - --IO3 <= '0'; - --IO4 <= '0'; - --IO5 <= '0'; - --IO6 <= '0'; - --IO7 <= '0'; - --IO8 <= '0'; - --IO9 <= '0'; - --IO10 <= '0'; - --IO11 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - LED0 <= '0'; - LED1 <= '1'; - LED2 <= BP0; - --IO1 <= '1'; - --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - --IO3 <= ADC_SDO(0); - --IO4 <= ADC_SDO(1); - --IO5 <= ADC_SDO(2); - --IO6 <= ADC_SDO(3); - --IO7 <= ADC_SDO(4); - --IO8 <= ADC_SDO(5); - --IO9 <= ADC_SDO(6); - --IO10 <= ADC_SDO(7); - IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; - END IF; - END PROCESS; - - PROCESS (clk_49, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - I00_s <= '0'; - ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge - I00_s <= NOT I00_s; - END IF; - END PROCESS; --- IO0 <= I00_s; - - --UARTs - nCTS1 <= '1'; - nCTS2 <= '1'; - nDCD2 <= '1'; - - --EXT CONNECTOR - - --SPACE WIRE - - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) - PORT MAP ( - clk => clk_25, - reset => reset, - errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_time_management_1 : apb_lfr_time_management - GENERIC MAP ( - pindex => 6, - paddr => 6, - pmask => 16#fff#, - pirq => 12) - PORT MAP ( - clk25MHz => clk_25, - clk49_152MHz => clk_49, - resetn => reset, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - coarse_time => coarse_time, - fine_time => fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - SPW_EN <= '1'; - - spw_clk <= clk_50_s; - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DIN, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SIN, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DOUT, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SOUT, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_SIN, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_DIN, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_DOUT, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_SOUT, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(reset, clk_25, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- --- lpp_lfr_1 : lpp_lfr --- GENERIC MAP ( --- Mem_use => use_RAM, --- nb_data_by_buffer_size => 32, --- nb_word_by_buffer_size => 30, --- nb_snapshot_param_size => 32, --- delta_vector_size => 32, --- delta_vector_size_f0_2 => 7, -- log2(96) --- pindex => 6, --- paddr => 6, --- pmask => 16#fff#, --- pirq_ms => 6, --- pirq_wfp => 14, --- hindex => 2, --- top_lfr_version => X"00000005") --- PORT MAP ( --- clk => clk_25, --- rstn => reset, --- sample_B => sample(2 DOWNTO 0), --- sample_E => sample(7 DOWNTO 3), --- sample_val => sample_val, --- apbi => apbi_ext, --- apbo => apbo_ext(6), --- ahbi => ahbi_m_ext, --- ahbo => ahbo_m_ext(2), --- coarse_time => coarse_time, --- fine_time => fine_time, --- data_shaping_BW => bias_fail_sw_sig); - - waveform_picker0 : top_wf_picker - GENERIC MAP( - hindex => 2, - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq => 14, - tech => apa3e, - nb_burst_available_size => 12, -- size of the register holding the nb of burst - nb_snapshot_param_size => 12, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot - ENABLE_FILTER => '1' - ) - PORT MAP( - cnv_clk => clk_25, - cnv_rstn => reset, - -- SAMPLES - sample_B => sample(2 DOWNTO 0), - sample_E => sample(7 DOWNTO 3), - sample_val => sample_val, - -- AMBA AHB system signals - HCLK => clk_25, - HRESETn => reset, - -- AMBA APB Slave Interface - apbi => apbi_ext, - apbo => apbo_ext(15), - -- AMBA AHB Master Interface - AHB_Master_In => ahbi_m_ext, - AHB_Master_Out => ahbo_m_ext(2), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => bias_fail_sw_sig - ); - - top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 - GENERIC MAP( - ChannelCount => 8, - SampleNbBits => 14, - ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 - ncycle_cnv => 500) -- 49 152 000 / 98304 - PORT MAP ( - -- CONV - cnv_clk => clk_49, - cnv_rstn => reset, - cnv => ADC_nCS_sig, - -- DATA - clk => clk_25, - rstn => reset, - sck => ADC_CLK_sig, - sdo => ADC_SDO_sig, - -- SAMPLE - sample => sample, - sample_val => sample_val); - - IO10 <= ADC_SDO_sig(5); - IO9 <= ADC_SDO_sig(4); - IO8 <= ADC_SDO_sig(3); - - ADC_nCS <= ADC_nCS_sig; - ADC_CLK <= ADC_CLK_sig; - ADC_SDO_sig <= ADC_SDO; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) - PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); - - pio_pad_0 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); - pio_pad_1 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); - pio_pad_2 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); - pio_pad_3 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); - pio_pad_4 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); - pio_pad_5 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); - pio_pad_6 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); - pio_pad_7 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); - -END beh; diff --git a/designs/MINI-LFR-WFRM-GPIO/Makefile b/designs/MINI-LFR-WFRM-GPIO/Makefile deleted file mode 100644 --- a/designs/MINI-LFR-WFRM-GPIO/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=MINI_LFR_top -BOARD=MINI-LFR -include $(VHDLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES= MINI_LFR_top.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./dsp/lpp_fft \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_demux \ - ./lpp_matrix \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_Header \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP =lpp_lfr_ms.vhd \ - i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/MINI-LFR/.config b/designs/MINI-LFR/.config deleted file mode 100644 --- a/designs/MINI-LFR/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/MINI-LFR/MINI_LFR_top.vhd b/designs/MINI-LFR/MINI_LFR_top.vhd deleted file mode 100644 --- a/designs/MINI-LFR/MINI_LFR_top.vhd +++ /dev/null @@ -1,281 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY MINI_LFR_top IS - - PORT ( - clk_50 : IN STD_LOGIC; - clk_49 : IN STD_LOGIC; - reset : IN STD_LOGIC; - --BPs - BP0 : IN STD_LOGIC; - BP1 : IN STD_LOGIC; - --LEDs - LED0 : OUT STD_LOGIC; - LED1 : OUT STD_LOGIC; - LED2 : OUT STD_LOGIC; - --UARTs - TXD1 : IN STD_LOGIC; - RXD1 : OUT STD_LOGIC; - nCTS1 : OUT STD_LOGIC; - nRTS1 : IN STD_LOGIC; - - TXD2 : IN STD_LOGIC; - RXD2 : OUT STD_LOGIC; - nCTS2 : OUT STD_LOGIC; - nDTR2 : IN STD_LOGIC; - nRTS2 : IN STD_LOGIC; - nDCD2 : OUT STD_LOGIC; - - --EXT CONNECTOR - IO0 : INOUT STD_LOGIC; - IO1 : INOUT STD_LOGIC; - IO2 : INOUT STD_LOGIC; - IO3 : INOUT STD_LOGIC; - IO4 : INOUT STD_LOGIC; - IO5 : INOUT STD_LOGIC; - IO6 : INOUT STD_LOGIC; - IO7 : INOUT STD_LOGIC; - IO8 : INOUT STD_LOGIC; - IO9 : INOUT STD_LOGIC; - IO10 : INOUT STD_LOGIC; - IO11 : INOUT STD_LOGIC; - - --SPACE WIRE - SPW_EN : OUT STD_LOGIC; -- 0 => off - SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK - SPW_NOM_SIN : IN STD_LOGIC; - SPW_NOM_DOUT : OUT STD_LOGIC; - SPW_NOM_SOUT : OUT STD_LOGIC; - SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK - SPW_RED_SIN : IN STD_LOGIC; - SPW_RED_DOUT : OUT STD_LOGIC; - SPW_RED_SOUT : OUT STD_LOGIC; - -- MINI LFR ADC INPUTS - ADC_nCS : OUT STD_LOGIC; - ADC_CLK : OUT STD_LOGIC; - ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - - -- SRAM - SRAM_nWE : OUT STD_LOGIC; - SRAM_CE : OUT STD_LOGIC; - SRAM_nOE : OUT STD_LOGIC; - SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END MINI_LFR_top; - - -ARCHITECTURE beh OF MINI_LFR_top IS - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - -- - SIGNAL errorn : STD_LOGIC; - -- UART AHB --------------------------------------------------------------- - SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data - SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data - SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data - -- - SIGNAL I00_s : STD_LOGIC; - -- - CONSTANT NB_APB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 1; - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); - - SIGNAL SRAM_CE_V : STD_LOGIC_VECTOR(1 downto 0); - - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - - PROCESS(clk_50) - BEGIN - IF clk_50'EVENT AND clk_50 = '1' THEN - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - LED0 <= '0'; - LED1 <= '0'; - LED2 <= '0'; - IO1 <= '0'; - IO2 <= '1'; - IO3 <= '0'; - IO4 <= '0'; - IO5 <= '0'; - IO6 <= '0'; - IO7 <= '0'; - IO8 <= '0'; - IO9 <= '0'; - IO10 <= '0'; - IO11 <= '0'; - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - LED0 <= '0'; - LED1 <= '1'; - LED2 <= BP0; - IO1 <= '1'; - IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - IO3 <= ADC_SDO(0); - IO4 <= ADC_SDO(1); - IO5 <= ADC_SDO(2); - IO6 <= ADC_SDO(3); - IO7 <= ADC_SDO(4); - IO8 <= ADC_SDO(5); - IO9 <= ADC_SDO(6); - IO10 <= ADC_SDO(7); - IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; - END IF; - END PROCESS; - - PROCESS (clk_49, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - I00_s <= '0'; - ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge - I00_s <= NOT I00_s; - END IF; - END PROCESS; - IO0 <= I00_s; - - --UARTs - nCTS1 <= '1'; - nCTS2 <= '1'; - nDCD2 <= '1'; - - --EXT CONNECTOR - - --SPACE WIRE - SPW_EN <= '0'; -- 0 => off - - SPW_NOM_DOUT <= '0'; - SPW_NOM_SOUT <= '0'; - SPW_RED_DOUT <= '0'; - SPW_RED_SOUT <= '0'; - - ADC_nCS <= '0'; - ADC_CLK <= '0'; - - - leon3_soc_1: leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - NB_CPU => 1, - ENABLE_FPU => 0, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) - PORT MAP ( - clk => clk_25, - reset => reset, - errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE_V, - nSRAM_OE => SRAM_nOE, - nSRAM_READY=> open, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - SRAM_CE <= SRAM_CE_V(0); - -END beh; diff --git a/designs/MINI-LFR/Makefile b/designs/MINI-LFR/Makefile deleted file mode 100644 --- a/designs/MINI-LFR/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=MINI_LFR_top -BOARD=MINI-LFR -include $(VHDLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES= MINI_LFR_top.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./dsp/lpp_fft \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_demux \ - ./lpp_matrix \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_Header \ - -FILESKIP =lpp_lfr_ms.vhd \ - i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -38,8 +38,8 @@ USE esa.memoryctrl.ALL; LIBRARY lpp; USE lpp.lpp_memory.ALL; USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; USE lpp.iir_filter.ALL; USE lpp.general_purpose.ALL; USE lpp.lpp_lfr_management.ALL; @@ -131,13 +131,6 @@ ARCHITECTURE beh OF MINI_LFR_top IS SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); -- SIGNAL errorn : STD_LOGIC; - -- UART AHB --------------------------------------------------------------- --- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data --- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- --- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data --- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data -- SIGNAL I00_s : STD_LOGIC; @@ -164,8 +157,6 @@ ARCHITECTURE beh OF MINI_LFR_top IS SIGNAL spw_clk : STD_LOGIC; SIGNAL swni : grspw_in_type; SIGNAL swno : grspw_out_type; --- SIGNAL clkmn : STD_ULOGIC; --- SIGNAL txclk : STD_ULOGIC; --GPIO SIGNAL gpioi : gpio_in_type; @@ -220,15 +211,12 @@ ARCHITECTURE beh OF MINI_LFR_top IS BEGIN -- beh ----------------------------------------------------------------------------- - -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - -- clk_50 frequency is 100 Mhz ! PROCESS (clk100MHz, reset) BEGIN -- PROCESS IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge clk_50_s <= NOT clk_50_s; END IF; END PROCESS; - -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ----------------------------------------------------------------------------- PROCESS (clk_50_s, reset) @@ -380,13 +368,10 @@ BEGIN -- beh pindex => 6, paddr => 6, pmask => 16#fff#, --- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set PORT MAP ( clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO --- clk24_576MHz => clk_24, -- 49.152MHz/2 --- resetn_24_576MHz => rstn_24, -- TODO + resetn_25MHz => rstn_25, grspw_tick => swno.tickout, apbi => apbi_ext, apbo => apbo_ext(6), @@ -432,7 +417,6 @@ BEGIN -- beh PORT MAP (SPW_RED_SOUT, swno.s(1)); -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate spw_inputloop : FOR j IN 0 TO 1 GENERATE spw_phy0 : grspw_phy GENERIC MAP( @@ -496,8 +480,7 @@ BEGIN -- beh LFR_rstn <= LFR_soft_rstn AND rstn_25; - --LFR_rstn <= rstn_25; - + lpp_lfr_1 : lpp_lfr GENERIC MAP ( Mem_use => use_RAM, @@ -533,7 +516,7 @@ BEGIN -- beh observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; --- IO0 <= rstn_25; + IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full @@ -566,10 +549,6 @@ BEGIN -- beh sample => sample, sample_val => sample_val); - --IO10 <= ADC_SDO_sig(5); - --IO9 <= ADC_SDO_sig(4); - --IO8 <= ADC_SDO_sig(3); - ADC_nCS <= ADC_nCS_sig; ADC_CLK <= ADC_CLK_sig; ADC_SDO_sig <= ADC_SDO; diff --git a/designs/MINI-LFR_WFP_MS/Makefile b/designs/MINI-LFR_WFP_MS/Makefile --- a/designs/MINI-LFR_WFP_MS/Makefile +++ b/designs/MINI-LFR_WFP_MS/Makefile @@ -22,7 +22,7 @@ CLEAN=soft-clean TECHLIBS = proasic3e LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc + tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ @@ -42,7 +42,8 @@ FILESKIP =i2cmst.vhd \ Top_MatrixSpec.vhd \ APB_FFT.vhd \ CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd + lpp_lfr_apbreg_simu.vhd \ + sgmii.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/MINI-LFR_testFFT-MS/MINI_LFR_top.vhd b/designs/MINI-LFR_testFFT-MS/MINI_LFR_top.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFT-MS/MINI_LFR_top.vhd +++ /dev/null @@ -1,696 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY MINI_LFR_top IS - - PORT ( - clk_50 : IN STD_LOGIC; - clk_49 : IN STD_LOGIC; - reset : IN STD_LOGIC; - --BPs - BP0 : IN STD_LOGIC; - BP1 : IN STD_LOGIC; - --LEDs - LED0 : OUT STD_LOGIC; - LED1 : OUT STD_LOGIC; - LED2 : OUT STD_LOGIC; - --UARTs - TXD1 : IN STD_LOGIC; - RXD1 : OUT STD_LOGIC; - nCTS1 : OUT STD_LOGIC; - nRTS1 : IN STD_LOGIC; - - TXD2 : IN STD_LOGIC; - RXD2 : OUT STD_LOGIC; - nCTS2 : OUT STD_LOGIC; - nDTR2 : IN STD_LOGIC; - nRTS2 : IN STD_LOGIC; - nDCD2 : OUT STD_LOGIC; - - --EXT CONNECTOR - IO0 : INOUT STD_LOGIC; - IO1 : INOUT STD_LOGIC; - IO2 : INOUT STD_LOGIC; - IO3 : INOUT STD_LOGIC; - IO4 : INOUT STD_LOGIC; - IO5 : INOUT STD_LOGIC; - IO6 : INOUT STD_LOGIC; - IO7 : INOUT STD_LOGIC; - IO8 : INOUT STD_LOGIC; - IO9 : INOUT STD_LOGIC; - IO10 : INOUT STD_LOGIC; - IO11 : INOUT STD_LOGIC; - - --SPACE WIRE - SPW_EN : OUT STD_LOGIC; -- 0 => off - SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK - SPW_NOM_SIN : IN STD_LOGIC; - SPW_NOM_DOUT : OUT STD_LOGIC; - SPW_NOM_SOUT : OUT STD_LOGIC; - SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK - SPW_RED_SIN : IN STD_LOGIC; - SPW_RED_DOUT : OUT STD_LOGIC; - SPW_RED_SOUT : OUT STD_LOGIC; - -- MINI LFR ADC INPUTS - ADC_nCS : OUT STD_LOGIC; - ADC_CLK : OUT STD_LOGIC; - ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - - -- SRAM - SRAM_nWE : OUT STD_LOGIC; - SRAM_CE : OUT STD_LOGIC; - SRAM_nOE : OUT STD_LOGIC; - SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END MINI_LFR_top; - - -ARCHITECTURE beh OF MINI_LFR_top IS - - COMPONENT lpp_lfr_ms_tb - GENERIC ( - Mem_use : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC; - MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_lfr_apbreg_tb - GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_2 : IN STD_LOGIC; - MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0)); - END COMPONENT; - - - - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - -- - SIGNAL errorn : STD_LOGIC; - -- UART AHB --------------------------------------------------------------- - SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data - SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data - SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data - -- - SIGNAL I00_s : STD_LOGIC; - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - -- - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; --- SIGNAL clkmn : STD_ULOGIC; --- SIGNAL txclk : STD_ULOGIC; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_s : Samples(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_nCS_sig : STD_LOGIC; - SIGNAL ADC_CLK_sig : STD_LOGIC; - SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); - - SIGNAL bias_fail_sw_sig : STD_LOGIC; - - SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); - ----------------------------------------------------------------------------- - - - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - SIGNAL MEM_OUT_SM_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full_pad : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full_pad_2 : STD_LOGIC; - SIGNAL MEM_OUT_SM_Empty_pad : STD_LOGIC_VECTOR(1 DOWNTO 0); - - - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - - PROCESS(clk_50) - BEGIN - IF clk_50'EVENT AND clk_50 = '1' THEN - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - - PROCESS(clk_49) - BEGIN - IF clk_49'EVENT AND clk_49 = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - LED0 <= '0'; - LED1 <= '0'; - LED2 <= '0'; - --IO1 <= '0'; - --IO2 <= '1'; - --IO3 <= '0'; - --IO4 <= '0'; - --IO5 <= '0'; - --IO6 <= '0'; - --IO7 <= '0'; - --IO8 <= '0'; - --IO9 <= '0'; - --IO10 <= '0'; - --IO11 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - LED0 <= '0'; - LED1 <= '1'; - LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; - --IO1 <= '1'; - --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - --IO3 <= ADC_SDO(0); - --IO4 <= ADC_SDO(1); - --IO5 <= ADC_SDO(2); - --IO6 <= ADC_SDO(3); - --IO7 <= ADC_SDO(4); - --IO8 <= ADC_SDO(5); - --IO9 <= ADC_SDO(6); - --IO10 <= ADC_SDO(7); - --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; - END IF; - END PROCESS; - - PROCESS (clk_24, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - I00_s <= '0'; - ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge - I00_s <= NOT I00_s; - END IF; - END PROCESS; --- IO0 <= I00_s; - - --UARTs - nCTS1 <= '1'; - nCTS2 <= '1'; - nDCD2 <= '1'; - - --EXT CONNECTOR - - --SPACE WIRE - - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) - PORT MAP ( - clk => clk_25, - reset => reset, - errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_time_management_1 : apb_lfr_time_management - GENERIC MAP ( - pindex => 6, - paddr => 6, - pmask => 16#fff#, - FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - clk24_576MHz => clk_24, -- 49.152MHz/2 - resetn => reset, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - coarse_time => coarse_time, - fine_time => fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - SPW_EN <= '1'; - - spw_clk <= clk_50_s; - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DIN, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SIN, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DOUT, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SOUT, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_SIN, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_DIN, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_DOUT, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_SOUT, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(reset, clk_25, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - - lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb - GENERIC MAP ( - pindex => 15, - paddr => 15, - pmask => 16#fff#) - PORT MAP ( - HCLK => clk_25, - HRESETn => reset, - apbi => apbi_ext, - apbo => apbo_ext(15), - - sample_f0_wen => sample_f0_wen, - sample_f1_wen => sample_f1_wen, - sample_f2_wen => sample_f2_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wdata => sample_f2_wdata, - - MEM_OUT_SM_ren => MEM_OUT_SM_ren , - MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , - MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad , - MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 , - MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad); - - lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb - GENERIC MAP ( - Mem_use =>use_RAM) - PORT MAP ( - clk => clk_25, - rstn => reset, - sample_f0_wen => sample_f0_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wen => sample_f1_wen, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wen => sample_f2_wen, - sample_f2_wdata => sample_f2_wdata, - - MEM_OUT_SM_Read => MEM_OUT_SM_ren , - MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , - MEM_OUT_SM_Full_pad => MEM_OUT_SM_Full_pad , - MEM_OUT_SM_Full_pad_2 => MEM_OUT_SM_Full_pad_2 , - MEM_OUT_SM_Empty_pad => MEM_OUT_SM_Empty_pad, - - error_input_fifo_write => OPEN, - observation_vector_0 => observation_vector_0, - observation_vector_1 => observation_vector_1); - - ----------------------------------------------------------------------------- - - - - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; - END GENERATE all_sample; - - - - top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 - GENERIC MAP( - ChannelCount => 8, - SampleNbBits => 14, - ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 - ncycle_cnv => 249) -- 49 152 000 / 98304 /2 - PORT MAP ( - -- CONV - cnv_clk => clk_24, - cnv_rstn => reset, - cnv => ADC_nCS_sig, - -- DATA - clk => clk_25, - rstn => reset, - sck => ADC_CLK_sig, - sdo => ADC_SDO_sig, - -- SAMPLE - sample => sample, - sample_val => sample_val); - - --IO10 <= ADC_SDO_sig(5); - --IO9 <= ADC_SDO_sig(4); - --IO8 <= ADC_SDO_sig(3); - - ADC_nCS <= ADC_nCS_sig; - ADC_CLK <= ADC_CLK_sig; - ADC_SDO_sig <= ADC_SDO; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) - PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); - - --pio_pad_0 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); - --pio_pad_1 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); - --pio_pad_2 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); - --pio_pad_3 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); - --pio_pad_4 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); - --pio_pad_5 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); - --pio_pad_6 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); - --pio_pad_7 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - IO0 <= '0'; - IO1 <= '0'; - IO2 <= '0'; - IO3 <= '0'; - IO4 <= '0'; - IO5 <= '0'; - IO6 <= '0'; - IO7 <= '0'; - IO8 <= '0'; - IO9 <= '0'; - IO10 <= '0'; - IO11 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - CASE gpioo.dout(2 DOWNTO 0) IS - WHEN "011" => - IO0 <= observation_reg(0); - IO1 <= observation_reg(1); - IO2 <= observation_reg(2); - IO3 <= observation_reg(3); - IO4 <= observation_reg(4); - IO5 <= observation_reg(5); - IO6 <= observation_reg(6); - IO7 <= observation_reg(7); - IO8 <= observation_reg(8); - IO9 <= observation_reg(9); - IO10 <= observation_reg(10); - IO11 <= observation_reg(11); - WHEN "001" => - IO0 <= observation_reg(0 + 12); - IO1 <= observation_reg(1 + 12); - IO2 <= observation_reg(2 + 12); - IO3 <= observation_reg(3 + 12); - IO4 <= observation_reg(4 + 12); - IO5 <= observation_reg(5 + 12); - IO6 <= observation_reg(6 + 12); - IO7 <= observation_reg(7 + 12); - IO8 <= observation_reg(8 + 12); - IO9 <= observation_reg(9 + 12); - IO10 <= observation_reg(10 + 12); - IO11 <= observation_reg(11 + 12); - WHEN "010" => - IO0 <= observation_reg(0 + 12 + 12); - IO1 <= observation_reg(1 + 12 + 12); - IO2 <= observation_reg(2 + 12 + 12); - IO3 <= observation_reg(3 + 12 + 12); - IO4 <= observation_reg(4 + 12 + 12); - IO5 <= observation_reg(5 + 12 + 12); - IO6 <= observation_reg(6 + 12 + 12); - IO7 <= observation_reg(7 + 12 + 12); - IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2); - IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5); - IO10 <= ADC_SDO(6) OR ADC_SDO(7) ; - IO11 <= '0'; - WHEN "000" => - IO0 <= observation_vector_0(0); - IO1 <= observation_vector_0(1); - IO2 <= observation_vector_0(2); - IO3 <= observation_vector_0(3); - IO4 <= observation_vector_0(4); - IO5 <= observation_vector_0(5); - IO6 <= observation_vector_0(6); - IO7 <= observation_vector_0(7); - IO8 <= observation_vector_0(8); - IO9 <= observation_vector_0(9); - IO10 <= observation_vector_0(10); - IO11 <= observation_vector_0(11); - WHEN "100" => - IO0 <= observation_vector_1(0); - IO1 <= observation_vector_1(1); - IO2 <= observation_vector_1(2); - IO3 <= observation_vector_1(3); - IO4 <= observation_vector_1(4); - IO5 <= observation_vector_1(5); - IO6 <= observation_vector_1(6); - IO7 <= observation_vector_1(7); - IO8 <= observation_vector_1(8); - IO9 <= observation_vector_1(9); - IO10 <= observation_vector_1(10); - IO11 <= observation_vector_1(11); - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - -END beh; \ No newline at end of file diff --git a/designs/MINI-LFR_testFFT-MS/Makefile b/designs/MINI-LFR_testFFT-MS/Makefile deleted file mode 100644 --- a/designs/MINI-LFR_testFFT-MS/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=MINI_LFR_top -BOARD=MINI-LFR -include $(VHDLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_uart \ - ./lpp_usb \ - ./dsp/lpp_fft_rtax \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP =i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/MINI-LFR_testFFT-MS/fft_test.vhd b/designs/MINI-LFR_testFFT-MS/fft_test.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFT-MS/fft_test.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - - -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.iir_filter.ALL; -USE lpp.spectral_matrix_package.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_Header.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.lpp_fft.ALL; -USE lpp.fft_components.ALL; - -ENTITY lpp_lfr_ms IS - GENERIC ( - Mem_use : INTEGER := use_RAM - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - ); -END; - -ARCHITECTURE Behavioral OF lpp_lfr_ms IS - -BEGIN - - ----------------------------------------------------------------------------- - - lppFIFOxN_f0_a : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f0_A_wen, - wdata => sample_f0_wdata, - - ren => sample_f0_A_ren, - rdata => sample_f0_A_rdata, - - empty => sample_f0_A_empty, - full => sample_f0_A_full, - almost_full => OPEN); - - ----------------------------------------------------------------------------- - - lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT - PORT MAP ( - clk => clk, - rstn => rstn, - sample_valid => sample_valid, -- WRITE in - fft_read => fft_read, -- READ in - sample_data => sample_data, -- WRITE in - sample_load => sample_load, -- WRITE out - fft_pong => fft_pong, -- READ out - fft_data_im => fft_data_im, -- READ out - fft_data_re => fft_data_re, -- READ out - fft_data_valid => fft_data_valid, -- READ out - fft_ready => fft_ready); -- READ out - - ----------------------------------------------------------------------------- - -END Behavioral; diff --git a/designs/MINI-LFR_testFFT-MS/lpp_lfr_apbreg.vhd b/designs/MINI-LFR_testFFT-MS/lpp_lfr_apbreg.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFT-MS/lpp_lfr_apbreg.vhd +++ /dev/null @@ -1,195 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -LIBRARY lpp; -USE lpp.lpp_lfr_pkg.ALL; ---USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_lfr_apbreg_tb IS - GENERIC ( - pindex : INTEGER := 4; - paddr : INTEGER := 4; - pmask : INTEGER := 16#fff#); - PORT ( - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - - -- AMBA APB Slave Interface - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - - --------------------------------------------------------------------------- - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - --------------------------------------------------------------------------- - MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_2 : IN STD_LOGIC; - MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0) - --------------------------------------------------------------------------- - ); - -END lpp_lfr_apbreg_tb; - -ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS - - CONSTANT REVISION : INTEGER := 1; - - CONSTANT pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1), - 1 => apb_iobar(paddr, pmask)); - - TYPE reg_debug_fft IS RECORD - in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - - in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0); - in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0); - in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - out_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); - END RECORD; - SIGNAL reg_ftt : reg_debug_fft; - - SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - -BEGIN -- beh - - --------------------------------------------------------------------------- - sample_f0_wen <= reg_ftt.in_wen_f0; - sample_f1_wen <= reg_ftt.in_wen_f1; - sample_f2_wen <= reg_ftt.in_wen_f2; - - sample_f0_wdata <= reg_ftt.in_data_f0; - sample_f1_wdata <= reg_ftt.in_data_f1; - sample_f2_wdata <= reg_ftt.in_data_f2; - --------------------------------------------------------------------------- - MEM_OUT_SM_ren <= reg_ftt.out_ren; - --------------------------------------------------------------------------- - - lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) - VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); - BEGIN - IF HRESETn = '0' THEN - - reg_ftt.in_data_f0 <= (OTHERS => '0'); - reg_ftt.in_data_f1 <= (OTHERS => '0'); - reg_ftt.in_data_f2 <= (OTHERS => '0'); - - reg_ftt.in_wen_f0 <= (OTHERS => '1'); - reg_ftt.in_wen_f1 <= (OTHERS => '1'); - reg_ftt.in_wen_f2 <= (OTHERS => '1'); - - reg_ftt.out_ren <= (OTHERS => '1'); - - ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - - - reg_ftt.in_wen_f0 <= (OTHERS => '1'); - reg_ftt.in_wen_f1 <= (OTHERS => '1'); - reg_ftt.in_wen_f2 <= (OTHERS => '1'); - reg_ftt.out_ren <= (OTHERS => '1'); - - paddr := "000000"; - paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); - prdata <= (OTHERS => '0'); - IF apbi.psel(pindex) = '1' THEN - -- APB DMA READ -- - CASE paddr(7 DOWNTO 2) IS - --0 - WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0); - WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32); - WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64); - WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0; - - WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0); - WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32); - WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64); - WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1; - - WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0); - WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32); - WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64); - WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2; - - WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*1-1 DOWNTO 32*0); - WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*2-1 DOWNTO 32*1); - - WHEN "001110" => prdata(1 DOWNTO 0) <= reg_ftt.out_ren; - prdata(3 DOWNTO 2) <= MEM_OUT_SM_Full; - prdata(5 DOWNTO 4) <= MEM_OUT_SM_Empty; - prdata(6) <= MEM_OUT_SM_Full_2; - WHEN OTHERS => NULL; - - END CASE; - IF (apbi.pwrite AND apbi.penable) = '1' THEN - -- APB DMA WRITE -- - CASE paddr(7 DOWNTO 2) IS - WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata; - WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata; - WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata; - WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata; - WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata; - WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata; - WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "001110" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0); - - WHEN OTHERS => NULL; - END CASE; - END IF; - END IF; - - END IF; - END PROCESS lpp_lfr_apbreg; - - apbo.pindex <= pindex; - apbo.pconfig <= pconfig; - apbo.prdata <= prdata; - -END beh; \ No newline at end of file diff --git a/designs/MINI-LFR_testFFT-MS/lpp_lfr_ms_validation.vhd b/designs/MINI-LFR_testFFT-MS/lpp_lfr_ms_validation.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFT-MS/lpp_lfr_ms_validation.vhd +++ /dev/null @@ -1,1014 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - - -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.iir_filter.ALL; -USE lpp.spectral_matrix_package.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_Header.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.lpp_fft.ALL; -USE lpp.fft_components.ALL; - -ENTITY lpp_lfr_ms_tb IS - GENERIC ( - Mem_use : INTEGER := use_RAM - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC; - MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - -- - observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS - - SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL error_wen_f0 : STD_LOGIC; - SIGNAL error_wen_f1 : STD_LOGIC; - SIGNAL error_wen_f2 : STD_LOGIC; - - SIGNAL one_sample_f1_full : STD_LOGIC; - SIGNAL one_sample_f1_wen : STD_LOGIC; - SIGNAL one_sample_f2_full : STD_LOGIC; - SIGNAL one_sample_f2_wen : STD_LOGIC; - - ----------------------------------------------------------------------------- - -- FSM / SWITCH SELECT CHANNEL - ----------------------------------------------------------------------------- - TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); - SIGNAL state_fsm_select_channel : fsm_select_channel; - SIGNAL pre_state_fsm_select_channel : fsm_select_channel; - - SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- FSM LOAD FFT - ----------------------------------------------------------------------------- - TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); - SIGNAL state_fsm_load_FFT : fsm_load_FFT; - SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; - - SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_load : STD_LOGIC; - SIGNAL sample_valid : STD_LOGIC; - SIGNAL sample_valid_r : STD_LOGIC; - SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); - - - ----------------------------------------------------------------------------- - -- FFT - ----------------------------------------------------------------------------- - SIGNAL fft_read : STD_LOGIC; - SIGNAL fft_pong : STD_LOGIC; - SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL fft_data_valid : STD_LOGIC; - SIGNAL fft_ready : STD_LOGIC; - ----------------------------------------------------------------------------- --- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); - SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; - SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL current_fifo_empty : STD_LOGIC; - SIGNAL current_fifo_locked : STD_LOGIC; - SIGNAL current_fifo_full : STD_LOGIC; - SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); - SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL SM_correlation_start : STD_LOGIC; - SIGNAL SM_correlation_auto : STD_LOGIC; - SIGNAL SM_correlation_done : STD_LOGIC; - SIGNAL SM_correlation_done_reg1 : STD_LOGIC; - SIGNAL SM_correlation_done_reg2 : STD_LOGIC; - SIGNAL SM_correlation_done_reg3 : STD_LOGIC; - SIGNAL SM_correlation_begin : STD_LOGIC; - - SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; - SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; - - SIGNAL current_matrix_write : STD_LOGIC; - SIGNAL current_matrix_wait_empty : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL fifo_0_ready : STD_LOGIC; - SIGNAL fifo_1_ready : STD_LOGIC; - SIGNAL fifo_ongoing : STD_LOGIC; - - SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; - SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; - SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); --- SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); --- SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- TIME REG & INFOs - ----------------------------------------------------------------------------- - SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); - - SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - - SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); - - --SIGNAL time_update_f0_A : STD_LOGIC; - --SIGNAL time_update_f0_B : STD_LOGIC; - --SIGNAL time_update_f1 : STD_LOGIC; - --SIGNAL time_update_f2 : STD_LOGIC; - -- - SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); - SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); - SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); - - SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); - SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); - SIGNAL status_component_fifo_0_end : STD_LOGIC; - SIGNAL status_component_fifo_1_end : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); - - SIGNAL fft_ready_reg : STD_LOGIC; - SIGNAL fft_ready_rising_down : STD_LOGIC; - - SIGNAL sample_load_reg : STD_LOGIC; - SIGNAL sample_load_rising_down : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wen_head_in : STD_LOGIC; - SIGNAL sample_f1_wen_head_out : STD_LOGIC; - SIGNAL sample_f1_full_head_in : STD_LOGIC; - SIGNAL sample_f1_full_head_out : STD_LOGIC; - SIGNAL sample_f1_empty_head_in : STD_LOGIC; - - SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -BEGIN - - - error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; - - - switch_f0_inst : spectral_matrix_switch_f0 - PORT MAP ( - clk => clk, - rstn => rstn, - - sample_wen => sample_f0_wen, - - fifo_A_empty => sample_f0_A_empty, - fifo_A_full => sample_f0_A_full, - fifo_A_wen => sample_f0_A_wen, - - fifo_B_empty => sample_f0_B_empty, - fifo_B_full => sample_f0_B_full, - fifo_B_wen => sample_f0_B_wen, - - error_wen => error_wen_f0); -- TODO - - ----------------------------------------------------------------------------- - -- FIFO IN - ----------------------------------------------------------------------------- - lppFIFOxN_f0_a : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f0_A_wen, - wdata => sample_f0_wdata, - - ren => sample_f0_A_ren, - rdata => sample_f0_A_rdata, - - empty => sample_f0_A_empty, - full => sample_f0_A_full, - almost_full => OPEN); - - lppFIFOxN_f0_b : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f0_B_wen, - wdata => sample_f0_wdata, - ren => sample_f0_B_ren, - rdata => sample_f0_B_rdata, - empty => sample_f0_B_empty, - full => sample_f0_B_full, - almost_full => OPEN); - - ----------------------------------------------------------------------------- - -- sample_f1_wen in - -- sample_f1_wdata in - -- sample_f1_full OUT - - sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; - sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; - sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; - - lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head - PORT MAP ( - clk => clk, - rstn => rstn, - in_wen => sample_f1_wen_head_in, - in_data => sample_f1_wdata, - in_full => sample_f1_full_head_in, - in_empty => sample_f1_empty_head_in, - out_wen => sample_f1_wen_head_out, - out_data => sample_f1_wdata_head, - out_full => sample_f1_full_head_out); - - sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; - - - lppFIFOxN_f1 : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f1_wen_head, - wdata => sample_f1_wdata_head, - ren => sample_f1_ren, - rdata => sample_f1_rdata, - empty => sample_f1_empty, - full => sample_f1_full, - almost_full => sample_f1_almost_full); - - - one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - one_sample_f1_full <= '0'; - error_wen_f1 <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF sample_f1_full_head_out = '0' THEN - one_sample_f1_full <= '0'; - ELSE - one_sample_f1_full <= '1'; - END IF; - error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - - lppFIFOxN_f2 : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f2_wen, - wdata => sample_f2_wdata, - ren => sample_f2_ren, - rdata => sample_f2_rdata, - empty => sample_f2_empty, - full => sample_f2_full, - almost_full => OPEN); - - - one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - one_sample_f2_full <= '0'; - error_wen_f2 <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF sample_f2_full = "00000" THEN - one_sample_f2_full <= '0'; - ELSE - one_sample_f2_full <= '1'; - END IF; - error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- FSM SELECT CHANNEL - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - state_fsm_select_channel <= IDLE; - ELSIF clk'EVENT AND clk = '1' THEN - CASE state_fsm_select_channel IS - WHEN IDLE => - IF sample_f1_full = "11111" THEN - state_fsm_select_channel <= SWITCH_F1; - ELSIF sample_f1_almost_full = "00000" THEN - IF sample_f0_A_full = "11111" THEN - state_fsm_select_channel <= SWITCH_F0_A; - ELSIF sample_f0_B_full = "11111" THEN - state_fsm_select_channel <= SWITCH_F0_B; - ELSIF sample_f2_full = "11111" THEN - state_fsm_select_channel <= SWITCH_F2; - END IF; - END IF; - - WHEN SWITCH_F0_A => - IF sample_f0_A_empty = "11111" THEN - state_fsm_select_channel <= IDLE; - END IF; - WHEN SWITCH_F0_B => - IF sample_f0_B_empty = "11111" THEN - state_fsm_select_channel <= IDLE; - END IF; - WHEN SWITCH_F1 => - IF sample_f1_empty = "11111" THEN - state_fsm_select_channel <= IDLE; - END IF; - WHEN SWITCH_F2 => - IF sample_f2_empty = "11111" THEN - state_fsm_select_channel <= IDLE; - END IF; - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - pre_state_fsm_select_channel <= IDLE; - ELSIF clk'EVENT AND clk = '1' THEN - pre_state_fsm_select_channel <= state_fsm_select_channel; - END IF; - END PROCESS; - - - ----------------------------------------------------------------------------- - -- SWITCH SELECT CHANNEL - ----------------------------------------------------------------------------- - sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE - sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE - sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE - sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE - (OTHERS => '1'); - - sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE - sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE - sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE - sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE - (OTHERS => '0'); - - sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE - sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE - sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE - sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE - - - sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); - sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); - sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); - sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); - - - status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE - time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE - time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE - time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 - - ----------------------------------------------------------------------------- - -- FSM LOAD FFT - ----------------------------------------------------------------------------- - - sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE - sample_ren_s WHEN sample_load = '1' ELSE - (OTHERS => '1'); - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= IDLE; - status_MS_input <= (OTHERS => '0'); - --next_state_fsm_load_FFT <= IDLE; - --sample_valid <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN - CASE state_fsm_load_FFT IS - WHEN IDLE => - --sample_valid <= '0'; - sample_ren_s <= (OTHERS => '1'); - IF sample_full = "11111" AND sample_load = '1' THEN - state_fsm_load_FFT <= FIFO_1; - status_MS_input <= status_channel; - END IF; - - WHEN FIFO_1 => - sample_ren_s <= "1111" & NOT(sample_load); - IF sample_empty(0) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_2; - END IF; - - WHEN FIFO_2 => - sample_ren_s <= "111" & NOT(sample_load) & '1'; - IF sample_empty(1) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_3; - END IF; - - WHEN FIFO_3 => - sample_ren_s <= "11" & NOT(sample_load) & "11"; - IF sample_empty(2) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_4; - END IF; - - WHEN FIFO_4 => - sample_ren_s <= '1' & NOT(sample_load) & "111"; - IF sample_empty(3) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_5; - END IF; - - WHEN FIFO_5 => - sample_ren_s <= NOT(sample_load) & "1111"; - IF sample_empty(4) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= IDLE; - END IF; - WHEN OTHERS => NULL; - END CASE; - END IF; - END PROCESS; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - sample_valid_r <= '0'; - next_state_fsm_load_FFT <= IDLE; - ELSIF clk'EVENT AND clk = '1' THEN - next_state_fsm_load_FFT <= state_fsm_load_FFT; - IF sample_ren_s = "11111" THEN - sample_valid_r <= '0'; - ELSE - sample_valid_r <= '1'; - END IF; - END IF; - END PROCESS; - - sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; - - sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE - sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE - sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE - sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE - sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE - - ----------------------------------------------------------------------------- - -- FFT - ----------------------------------------------------------------------------- - lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT - PORT MAP ( - clk => clk, - rstn => rstn, - sample_valid => sample_valid, - fft_read => fft_read, - sample_data => sample_data, - sample_load => sample_load, - fft_pong => fft_pong, - fft_data_im => fft_data_im, - fft_data_re => fft_data_re, - fft_data_valid => fft_data_valid, - fft_ready => fft_ready); - - observation_vector_0(11 DOWNTO 0) <= "000" & --11 10 - fft_ongoing_counter & --9 8 - sample_load_rising_down & --7 - fft_ready_rising_down & --6 - fft_ready & --5 - fft_data_valid & --4 - fft_pong & --3 - sample_load & --2 - fft_read & --1 - sample_valid; --0 - - ----------------------------------------------------------------------------- - fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; - sample_load_rising_down <= sample_load_reg AND NOT sample_load; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - fft_ready_reg <= '0'; - sample_load_reg <= '0'; - - fft_ongoing_counter <= '0'; - ELSIF clk'event AND clk = '1' THEN - fft_ready_reg <= fft_ready; - sample_load_reg <= sample_load; - - IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN - fft_ongoing_counter <= '0'; - --- CASE fft_ongoing_counter IS --- WHEN "01" => fft_ongoing_counter <= "00"; ----- WHEN "10" => fft_ongoing_counter <= "01"; --- WHEN OTHERS => NULL; --- END CASE; - ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN - fft_ongoing_counter <= '1'; --- CASE fft_ongoing_counter IS --- WHEN "00" => fft_ongoing_counter <= "01"; ----- WHEN "01" => fft_ongoing_counter <= "10"; --- WHEN OTHERS => NULL; --- END CASE; - END IF; - - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - state_fsm_load_MS_memory <= IDLE; - current_fifo_load <= "00001"; - ELSIF clk'EVENT AND clk = '1' THEN - CASE state_fsm_load_MS_memory IS - WHEN IDLE => - IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN - state_fsm_load_MS_memory <= LOAD_FIFO; - END IF; - WHEN LOAD_FIFO => - IF current_fifo_full = '1' THEN - state_fsm_load_MS_memory <= TRASH_FFT; - END IF; - WHEN TRASH_FFT => - IF fft_ready = '0' THEN - state_fsm_load_MS_memory <= IDLE; - current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); - END IF; - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - - current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE - MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE - MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE - MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE - MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE - - current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE - MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE - MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE - MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE - MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE - - current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE - MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE - MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE - MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE - MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE - - fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; - - all_fifo : FOR I IN 4 DOWNTO 0 GENERATE - MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' - AND state_fsm_load_MS_memory = LOAD_FIFO - AND current_fifo_load(I) = '1' - ELSE '1'; - END GENERATE all_fifo; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - MEM_IN_SM_wen <= (OTHERS => '1'); - ELSIF clk'EVENT AND clk = '1' THEN - MEM_IN_SM_wen <= MEM_IN_SM_wen_s; - END IF; - END PROCESS; - - MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & - (fft_data_im & fft_data_re) & - (fft_data_im & fft_data_re) & - (fft_data_im & fft_data_re) & - (fft_data_im & fft_data_re); - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - Mem_In_SpectralMatrix : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 32, --16, - Addr_sz => 7, --8 - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => MEM_IN_SM_ReUse, - - wen => MEM_IN_SM_wen, - wdata => MEM_IN_SM_wData, - - ren => MEM_IN_SM_ren, - rdata => MEM_IN_SM_rData, - full => MEM_IN_SM_Full, - empty => MEM_IN_SM_Empty, - almost_full => OPEN); - - ----------------------------------------------------------------------------- - - observation_vector_1(11 DOWNTO 0) <= '0' & - SM_correlation_done & --4 - SM_correlation_auto & --3 - SM_correlation_start & - SM_correlation_start & --7 - status_MS_input(1 DOWNTO 0)& --6..5 - MEM_IN_SM_locked(4 DOWNTO 0); --4..0 - - ----------------------------------------------------------------------------- - MS_control_1 : MS_control - PORT MAP ( - clk => clk, - rstn => rstn, - - current_status_ms => status_MS_input, - - fifo_in_lock => MEM_IN_SM_locked, - fifo_in_data => MEM_IN_SM_rdata, - fifo_in_full => MEM_IN_SM_Full, - fifo_in_empty => MEM_IN_SM_Empty, - fifo_in_ren => MEM_IN_SM_ren, - fifo_in_reuse => MEM_IN_SM_ReUse, - - fifo_out_data => SM_in_data, - fifo_out_ren => SM_in_ren, - fifo_out_empty => SM_in_empty, - - current_status_component => status_component, - - correlation_start => SM_correlation_start, - correlation_auto => SM_correlation_auto, - correlation_done => SM_correlation_done); - - - MS_calculation_1 : MS_calculation - PORT MAP ( - clk => clk, - rstn => rstn, - - fifo_in_data => SM_in_data, - fifo_in_ren => SM_in_ren, - fifo_in_empty => SM_in_empty, - - fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO - fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO - fifo_out_full => MEM_OUT_SM_Full_s, -- TODO - - correlation_start => SM_correlation_start, - correlation_auto => SM_correlation_auto, - correlation_begin => SM_correlation_begin, - correlation_done => SM_correlation_done); - - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - current_matrix_write <= '0'; - current_matrix_wait_empty <= '1'; - status_component_fifo_0 <= (OTHERS => '0'); - status_component_fifo_1 <= (OTHERS => '0'); - status_component_fifo_0_end <= '0'; - status_component_fifo_1_end <= '0'; - SM_correlation_done_reg1 <= '0'; - SM_correlation_done_reg2 <= '0'; - SM_correlation_done_reg3 <= '0'; - - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - SM_correlation_done_reg1 <= SM_correlation_done; - SM_correlation_done_reg2 <= SM_correlation_done_reg1; - SM_correlation_done_reg3 <= SM_correlation_done_reg2; - status_component_fifo_0_end <= '0'; - status_component_fifo_1_end <= '0'; - IF SM_correlation_begin = '1' THEN - IF current_matrix_write = '0' THEN - status_component_fifo_0 <= status_component; - ELSE - status_component_fifo_1 <= status_component; - END IF; - END IF; - - IF SM_correlation_done_reg3 = '1' THEN - IF current_matrix_write = '0' THEN - status_component_fifo_0_end <= '1'; - ELSE - status_component_fifo_1_end <= '1'; - END IF; - current_matrix_wait_empty <= '1'; - current_matrix_write <= NOT current_matrix_write; - END IF; - - IF current_matrix_wait_empty <= '1' THEN - IF current_matrix_write = '0' THEN - current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); - ELSE - current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); - END IF; - END IF; - - END IF; - END PROCESS; - - MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE - '1' WHEN SM_correlation_done_reg1 = '1' ELSE - '1' WHEN SM_correlation_done_reg2 = '1' ELSE - '1' WHEN SM_correlation_done_reg3 = '1' ELSE - '1' WHEN current_matrix_wait_empty = '1' ELSE - MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE - MEM_OUT_SM_Full(1); - - MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; - MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; - - MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; - ----------------------------------------------------------------------------- - - Mem_Out_SpectralMatrix : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 32, - Addr_sz => 8, - FifoCnt => 2) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => MEM_OUT_SM_Write, - wdata => MEM_OUT_SM_Data_in, - - ren => MEM_OUT_SM_Read, - rdata => MEM_OUT_SM_Data_out, - - full => MEM_OUT_SM_Full, - empty => MEM_OUT_SM_Empty, - almost_full => OPEN); - - MEM_OUT_SM_Full_pad <= MEM_OUT_SM_Full; - MEM_OUT_SM_Full_pad_2 <= MEM_OUT_SM_Full_s; - MEM_OUT_SM_Empty_pad <= MEM_OUT_SM_Empty; - --- ----------------------------------------------------------------------------- ----- MEM_OUT_SM_Read <= "00"; --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- fifo_0_ready <= '0'; --- fifo_1_ready <= '0'; --- fifo_ongoing <= '0'; --- ELSIF clk'EVENT AND clk = '1' THEN --- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN --- fifo_ongoing <= '1'; --- fifo_0_ready <= '0'; --- ELSIF status_component_fifo_0_end = '1' THEN --- fifo_0_ready <= '1'; --- END IF; - --- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN --- fifo_ongoing <= '0'; --- fifo_1_ready <= '0'; --- ELSIF status_component_fifo_1_end = '1' THEN --- fifo_1_ready <= '1'; --- END IF; - --- END IF; --- END PROCESS; - --- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE --- '1' WHEN fifo_0_ready = '0' ELSE --- FSM_DMA_fifo_ren; - --- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE --- '1' WHEN fifo_1_ready = '0' ELSE --- FSM_DMA_fifo_ren; - --- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE --- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE --- '1'; - --- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE --- status_component_fifo_1; - --- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE --- MEM_OUT_SM_Data_out(63 DOWNTO 32); - --- ----------------------------------------------------------------------------- --- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma --- PORT MAP ( --- HCLK => clk, --- HRESETn => rstn, - --- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --- fifo_data => FSM_DMA_fifo_data, --- fifo_empty => FSM_DMA_fifo_empty, --- fifo_ren => FSM_DMA_fifo_ren, - --- dma_addr => dma_addr, --- dma_data => dma_data, --- dma_valid => dma_valid, --- dma_valid_burst => dma_valid_burst, --- dma_ren => dma_ren, --- dma_done => dma_done, - --- ready_matrix_f0 => ready_matrix_f0, --- ready_matrix_f1 => ready_matrix_f1, --- ready_matrix_f2 => ready_matrix_f2, - --- error_bad_component_error => error_bad_component_error, --- error_buffer_full => error_buffer_full, - --- debug_reg => debug_reg, --- status_ready_matrix_f0 => status_ready_matrix_f0, --- status_ready_matrix_f1 => status_ready_matrix_f1, --- status_ready_matrix_f2 => status_ready_matrix_f2, - --- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, --- config_active_interruption_onError => config_active_interruption_onError, - --- addr_matrix_f0 => addr_matrix_f0, --- addr_matrix_f1 => addr_matrix_f1, --- addr_matrix_f2 => addr_matrix_f2, - --- matrix_time_f0 => matrix_time_f0, --- matrix_time_f1 => matrix_time_f1, --- matrix_time_f2 => matrix_time_f2 --- ); --- ----------------------------------------------------------------------------- - - - - - --- ----------------------------------------------------------------------------- --- -- TIME MANAGMENT --- ----------------------------------------------------------------------------- --- all_time <= coarse_time & fine_time; --- -- --- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; --- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; --- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; --- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; - --- all_time_reg: FOR I IN 0 TO 3 GENERATE - --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- f_empty_reg(I) <= '1'; --- ELSIF clk'event AND clk = '1' THEN --- f_empty_reg(I) <= f_empty(I); --- END IF; --- END PROCESS; - --- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; - --- s_m_t_m_f0_A : spectral_matrix_time_managment --- PORT MAP ( --- clk => clk, --- rstn => rstn, --- time_in => all_time, --- update_1 => time_update_f(I), --- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) --- ); - --- END GENERATE all_time_reg; - --- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); --- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); --- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); --- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); - --- ----------------------------------------------------------------------------- - -END Behavioral; \ No newline at end of file diff --git a/designs/MINI-LFR_testFFTb/MINI_LFR_top.vhd b/designs/MINI-LFR_testFFTb/MINI_LFR_top.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFTb/MINI_LFR_top.vhd +++ /dev/null @@ -1,731 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY MINI_LFR_top IS - - PORT ( - clk_50 : IN STD_LOGIC; - clk_49 : IN STD_LOGIC; - reset : IN STD_LOGIC; - --BPs - BP0 : IN STD_LOGIC; - BP1 : IN STD_LOGIC; - --LEDs - LED0 : OUT STD_LOGIC; - LED1 : OUT STD_LOGIC; - LED2 : OUT STD_LOGIC; - --UARTs - TXD1 : IN STD_LOGIC; - RXD1 : OUT STD_LOGIC; - nCTS1 : OUT STD_LOGIC; - nRTS1 : IN STD_LOGIC; - - TXD2 : IN STD_LOGIC; - RXD2 : OUT STD_LOGIC; - nCTS2 : OUT STD_LOGIC; - nDTR2 : IN STD_LOGIC; - nRTS2 : IN STD_LOGIC; - nDCD2 : OUT STD_LOGIC; - - --EXT CONNECTOR - IO0 : INOUT STD_LOGIC; - IO1 : INOUT STD_LOGIC; - IO2 : INOUT STD_LOGIC; - IO3 : INOUT STD_LOGIC; - IO4 : INOUT STD_LOGIC; - IO5 : INOUT STD_LOGIC; - IO6 : INOUT STD_LOGIC; - IO7 : INOUT STD_LOGIC; - IO8 : INOUT STD_LOGIC; - IO9 : INOUT STD_LOGIC; - IO10 : INOUT STD_LOGIC; - IO11 : INOUT STD_LOGIC; - - --SPACE WIRE - SPW_EN : OUT STD_LOGIC; -- 0 => off - SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK - SPW_NOM_SIN : IN STD_LOGIC; - SPW_NOM_DOUT : OUT STD_LOGIC; - SPW_NOM_SOUT : OUT STD_LOGIC; - SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK - SPW_RED_SIN : IN STD_LOGIC; - SPW_RED_DOUT : OUT STD_LOGIC; - SPW_RED_SOUT : OUT STD_LOGIC; - -- MINI LFR ADC INPUTS - ADC_nCS : OUT STD_LOGIC; - ADC_CLK : OUT STD_LOGIC; - ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - - -- SRAM - SRAM_nWE : OUT STD_LOGIC; - SRAM_CE : OUT STD_LOGIC; - SRAM_nOE : OUT STD_LOGIC; - SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END MINI_LFR_top; - - -ARCHITECTURE beh OF MINI_LFR_top IS - - COMPONENT lpp_lfr_ms_tb - GENERIC ( - Mem_use : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ReUse : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_rData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_Full_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_lfr_apbreg_tb - GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0)); - END COMPONENT; - - - - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - -- - SIGNAL errorn : STD_LOGIC; - -- UART AHB --------------------------------------------------------------- - SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data - SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data - SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data - -- - SIGNAL I00_s : STD_LOGIC; - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - -- - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; --- SIGNAL clkmn : STD_ULOGIC; --- SIGNAL txclk : STD_ULOGIC; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_s : Samples(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_nCS_sig : STD_LOGIC; - SIGNAL ADC_CLK_sig : STD_LOGIC; - SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); - - SIGNAL bias_fail_sw_sig : STD_LOGIC; - - SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); - ----------------------------------------------------------------------------- - - - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - SIGNAL MEM_IN_SM_Full_pad : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_Empty_pad : STD_LOGIC_VECTOR(4 DOWNTO 0); - - - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - - PROCESS(clk_50) - BEGIN - IF clk_50'EVENT AND clk_50 = '1' THEN - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - - PROCESS(clk_49) - BEGIN - IF clk_49'EVENT AND clk_49 = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - LED0 <= '0'; - LED1 <= '0'; - LED2 <= '0'; - --IO1 <= '0'; - --IO2 <= '1'; - --IO3 <= '0'; - --IO4 <= '0'; - --IO5 <= '0'; - --IO6 <= '0'; - --IO7 <= '0'; - --IO8 <= '0'; - --IO9 <= '0'; - --IO10 <= '0'; - --IO11 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - LED0 <= '0'; - LED1 <= '1'; - LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; - --IO1 <= '1'; - --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - --IO3 <= ADC_SDO(0); - --IO4 <= ADC_SDO(1); - --IO5 <= ADC_SDO(2); - --IO6 <= ADC_SDO(3); - --IO7 <= ADC_SDO(4); - --IO8 <= ADC_SDO(5); - --IO9 <= ADC_SDO(6); - --IO10 <= ADC_SDO(7); - --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; - END IF; - END PROCESS; - - PROCESS (clk_24, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - I00_s <= '0'; - ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge - I00_s <= NOT I00_s; - END IF; - END PROCESS; --- IO0 <= I00_s; - - --UARTs - nCTS1 <= '1'; - nCTS2 <= '1'; - nDCD2 <= '1'; - - --EXT CONNECTOR - - --SPACE WIRE - - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) - PORT MAP ( - clk => clk_25, - reset => reset, - errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_time_management_1 : apb_lfr_time_management - GENERIC MAP ( - pindex => 6, - paddr => 6, - pmask => 16#fff#, - FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - clk24_576MHz => clk_24, -- 49.152MHz/2 - resetn => reset, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - coarse_time => coarse_time, - fine_time => fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - SPW_EN <= '1'; - - spw_clk <= clk_50_s; - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DIN, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SIN, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DOUT, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SOUT, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_SIN, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_DIN, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_DOUT, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_SOUT, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(reset, clk_25, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - --lpp_lfr_1 : lpp_lfr - -- GENERIC MAP ( - -- Mem_use => use_RAM, - -- nb_data_by_buffer_size => 32, - -- nb_word_by_buffer_size => 30, - -- nb_snapshot_param_size => 32, - -- delta_vector_size => 32, - -- delta_vector_size_f0_2 => 7, -- log2(96) - -- pindex => 15, - -- paddr => 15, - -- pmask => 16#fff#, - -- pirq_ms => 6, - -- pirq_wfp => 14, - -- hindex => 2, - -- top_lfr_version => X"000117") -- aa.bb.cc version - -- PORT MAP ( - -- clk => clk_25, - -- rstn => reset, - -- sample_B => sample_s(2 DOWNTO 0), - -- sample_E => sample_s(7 DOWNTO 3), - -- sample_val => sample_val, - -- apbi => apbi_ext, - -- apbo => apbo_ext(15), - -- ahbi => ahbi_m_ext, - -- ahbo => ahbo_m_ext(2), - -- coarse_time => coarse_time, - -- fine_time => fine_time, - -- data_shaping_BW => bias_fail_sw_sig, - -- observation_vector_0=> observation_vector_0, - -- observation_vector_1 => observation_vector_1, - -- observation_reg => observation_reg); - - lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb - GENERIC MAP ( - pindex => 15, - paddr => 15, - pmask => 16#fff#) - PORT MAP ( - HCLK => clk_25, - HRESETn => reset, - apbi => apbi_ext, - apbo => apbo_ext(15), - - sample_f0_wen => sample_f0_wen, - sample_f1_wen => sample_f1_wen, - sample_f2_wen => sample_f2_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wdata => sample_f2_wdata, - MEM_IN_SM_locked => MEM_IN_SM_locked, - MEM_IN_SM_ReUse => MEM_IN_SM_ReUse, - MEM_IN_SM_ren => MEM_IN_SM_ren, - MEM_IN_SM_rData => MEM_IN_SM_rData, - MEM_IN_SM_Full => MEM_IN_SM_Full_pad, - MEM_IN_SM_Empty => MEM_IN_SM_Empty_pad); - - lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb - GENERIC MAP ( - Mem_use =>use_RAM) - PORT MAP ( - clk => clk_25, - rstn => reset, - sample_f0_wen => sample_f0_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wen => sample_f1_wen, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wen => sample_f2_wen, - sample_f2_wdata => sample_f2_wdata, - - MEM_IN_SM_locked => MEM_IN_SM_locked, - MEM_IN_SM_ReUse => MEM_IN_SM_ReUse, - MEM_IN_SM_ren => MEM_IN_SM_ren, - MEM_IN_SM_rData => MEM_IN_SM_rData, - MEM_IN_SM_Full_pad => MEM_IN_SM_Full_pad, - MEM_IN_SM_Empty_pad => MEM_IN_SM_Empty_pad, - - error_input_fifo_write => OPEN, - observation_vector_0 => observation_vector_0, - observation_vector_1 => observation_vector_1); - - ----------------------------------------------------------------------------- - - - - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; - END GENERATE all_sample; - - - - top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 - GENERIC MAP( - ChannelCount => 8, - SampleNbBits => 14, - ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 - ncycle_cnv => 249) -- 49 152 000 / 98304 /2 - PORT MAP ( - -- CONV - cnv_clk => clk_24, - cnv_rstn => reset, - cnv => ADC_nCS_sig, - -- DATA - clk => clk_25, - rstn => reset, - sck => ADC_CLK_sig, - sdo => ADC_SDO_sig, - -- SAMPLE - sample => sample, - sample_val => sample_val); - - --IO10 <= ADC_SDO_sig(5); - --IO9 <= ADC_SDO_sig(4); - --IO8 <= ADC_SDO_sig(3); - - ADC_nCS <= ADC_nCS_sig; - ADC_CLK <= ADC_CLK_sig; - ADC_SDO_sig <= ADC_SDO; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) - PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); - - --pio_pad_0 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); - --pio_pad_1 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); - --pio_pad_2 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); - --pio_pad_3 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); - --pio_pad_4 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); - --pio_pad_5 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); - --pio_pad_6 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); - --pio_pad_7 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - IO0 <= '0'; - IO1 <= '0'; - IO2 <= '0'; - IO3 <= '0'; - IO4 <= '0'; - IO5 <= '0'; - IO6 <= '0'; - IO7 <= '0'; - IO8 <= '0'; - IO9 <= '0'; - IO10 <= '0'; - IO11 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - CASE gpioo.dout(2 DOWNTO 0) IS - WHEN "011" => - IO0 <= observation_reg(0); - IO1 <= observation_reg(1); - IO2 <= observation_reg(2); - IO3 <= observation_reg(3); - IO4 <= observation_reg(4); - IO5 <= observation_reg(5); - IO6 <= observation_reg(6); - IO7 <= observation_reg(7); - IO8 <= observation_reg(8); - IO9 <= observation_reg(9); - IO10 <= observation_reg(10); - IO11 <= observation_reg(11); - WHEN "001" => - IO0 <= observation_reg(0 + 12); - IO1 <= observation_reg(1 + 12); - IO2 <= observation_reg(2 + 12); - IO3 <= observation_reg(3 + 12); - IO4 <= observation_reg(4 + 12); - IO5 <= observation_reg(5 + 12); - IO6 <= observation_reg(6 + 12); - IO7 <= observation_reg(7 + 12); - IO8 <= observation_reg(8 + 12); - IO9 <= observation_reg(9 + 12); - IO10 <= observation_reg(10 + 12); - IO11 <= observation_reg(11 + 12); - WHEN "010" => - IO0 <= observation_reg(0 + 12 + 12); - IO1 <= observation_reg(1 + 12 + 12); - IO2 <= observation_reg(2 + 12 + 12); - IO3 <= observation_reg(3 + 12 + 12); - IO4 <= observation_reg(4 + 12 + 12); - IO5 <= observation_reg(5 + 12 + 12); - IO6 <= observation_reg(6 + 12 + 12); - IO7 <= observation_reg(7 + 12 + 12); - IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2); - IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5); - IO10 <= ADC_SDO(6) OR ADC_SDO(7) ; - IO11 <= '0'; - WHEN "000" => - IO0 <= observation_vector_0(0); - IO1 <= observation_vector_0(1); - IO2 <= observation_vector_0(2); - IO3 <= observation_vector_0(3); - IO4 <= observation_vector_0(4); - IO5 <= observation_vector_0(5); - IO6 <= observation_vector_0(6); - IO7 <= observation_vector_0(7); - IO8 <= observation_vector_0(8); - IO9 <= observation_vector_0(9); - IO10 <= observation_vector_0(10); - IO11 <= observation_vector_0(11); - WHEN "100" => - IO0 <= observation_vector_1(0); - IO1 <= observation_vector_1(1); - IO2 <= observation_vector_1(2); - IO3 <= observation_vector_1(3); - IO4 <= observation_vector_1(4); - IO5 <= observation_vector_1(5); - IO6 <= observation_vector_1(6); - IO7 <= observation_vector_1(7); - IO8 <= observation_vector_1(8); - IO9 <= observation_vector_1(9); - IO10 <= observation_vector_1(10); - IO11 <= observation_vector_1(11); - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - -END beh; diff --git a/designs/MINI-LFR_testFFTb/Makefile b/designs/MINI-LFR_testFFTb/Makefile deleted file mode 100644 --- a/designs/MINI-LFR_testFFTb/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=MINI_LFR_top -BOARD=MINI-LFR -include $(VHDLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_uart \ - ./lpp_usb \ - ./dsp/lpp_fft_rtax \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP =i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/MINI-LFR_testFFTb/fft_test.vhd b/designs/MINI-LFR_testFFTb/fft_test.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFTb/fft_test.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - - -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.iir_filter.ALL; -USE lpp.spectral_matrix_package.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_Header.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.lpp_fft.ALL; -USE lpp.fft_components.ALL; - -ENTITY lpp_lfr_ms IS - GENERIC ( - Mem_use : INTEGER := use_RAM - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - ); -END; - -ARCHITECTURE Behavioral OF lpp_lfr_ms IS - -BEGIN - - ----------------------------------------------------------------------------- - - lppFIFOxN_f0_a : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f0_A_wen, - wdata => sample_f0_wdata, - - ren => sample_f0_A_ren, - rdata => sample_f0_A_rdata, - - empty => sample_f0_A_empty, - full => sample_f0_A_full, - almost_full => OPEN); - - ----------------------------------------------------------------------------- - - lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT - PORT MAP ( - clk => clk, - rstn => rstn, - sample_valid => sample_valid, -- WRITE in - fft_read => fft_read, -- READ in - sample_data => sample_data, -- WRITE in - sample_load => sample_load, -- WRITE out - fft_pong => fft_pong, -- READ out - fft_data_im => fft_data_im, -- READ out - fft_data_re => fft_data_re, -- READ out - fft_data_valid => fft_data_valid, -- READ out - fft_ready => fft_ready); -- READ out - - ----------------------------------------------------------------------------- - -END Behavioral; diff --git a/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd b/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg.vhd +++ /dev/null @@ -1,209 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -LIBRARY lpp; -USE lpp.lpp_lfr_pkg.ALL; ---USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_lfr_apbreg_tb IS - GENERIC ( - pindex : INTEGER := 4; - paddr : INTEGER := 4; - pmask : INTEGER := 16#fff#); - PORT ( - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - - -- AMBA APB Slave Interface - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - - --------------------------------------------------------------------------- - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - --------------------------------------------------------------------------- - MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0) - --------------------------------------------------------------------------- - ); - -END lpp_lfr_apbreg_tb; - -ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS - - CONSTANT REVISION : INTEGER := 1; - - CONSTANT pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1), - 1 => apb_iobar(paddr, pmask)); - - TYPE reg_debug_fft IS RECORD - in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - - in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0); - in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0); - in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - out_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); - out_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); - out_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - END RECORD; - SIGNAL reg_ftt : reg_debug_fft; - - SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - -BEGIN -- beh - - --------------------------------------------------------------------------- - sample_f0_wen <= reg_ftt.in_wen_f0; - sample_f1_wen <= reg_ftt.in_wen_f1; - sample_f2_wen <= reg_ftt.in_wen_f2; - - sample_f0_wdata <= reg_ftt.in_data_f0; - sample_f1_wdata <= reg_ftt.in_data_f1; - sample_f2_wdata <= reg_ftt.in_data_f2; - --------------------------------------------------------------------------- - MEM_IN_SM_ReUse <= reg_ftt.out_reuse; - MEM_IN_SM_locked <= reg_ftt.out_locked; - MEM_IN_SM_ren <= reg_ftt.out_ren; - --------------------------------------------------------------------------- - - lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) - VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); - BEGIN - IF HRESETn = '0' THEN - - reg_ftt.in_data_f0 <= (OTHERS => '0'); - reg_ftt.in_data_f1 <= (OTHERS => '0'); - reg_ftt.in_data_f2 <= (OTHERS => '0'); - - reg_ftt.in_wen_f0 <= (OTHERS => '1'); - reg_ftt.in_wen_f1 <= (OTHERS => '1'); - reg_ftt.in_wen_f2 <= (OTHERS => '1'); - - - reg_ftt.out_reuse <= (OTHERS => '0'); - reg_ftt.out_locked <= (OTHERS => '0'); - reg_ftt.out_ren <= (OTHERS => '1'); - - ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - - - reg_ftt.in_wen_f0 <= (OTHERS => '1'); - reg_ftt.in_wen_f1 <= (OTHERS => '1'); - reg_ftt.in_wen_f2 <= (OTHERS => '1'); - reg_ftt.out_ren <= (OTHERS => '1'); - - paddr := "000000"; - paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); - prdata <= (OTHERS => '0'); - IF apbi.psel(pindex) = '1' THEN - -- APB DMA READ -- - CASE paddr(7 DOWNTO 2) IS - --0 - WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0); - WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32); - WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64); - WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0; - - WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0); - WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32); - WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64); - WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1; - - WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0); - WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32); - WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64); - WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2; - - WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*1-1 DOWNTO 32*0); - WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*2-1 DOWNTO 32*1); - WHEN "001110" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*3-1 DOWNTO 32*2); - WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3); - WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4); - - WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren; - prdata(9 DOWNTO 5) <= reg_ftt.out_reuse; - prdata(14 DOWNTO 10) <= reg_ftt.out_locked; - prdata(19 DOWNTO 15) <= MEM_IN_SM_Full; - prdata(24 DOWNTO 20) <= MEM_IN_SM_Empty; - WHEN OTHERS => NULL; - - END CASE; - IF (apbi.pwrite AND apbi.penable) = '1' THEN - -- APB DMA WRITE -- - CASE paddr(7 DOWNTO 2) IS - WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata; - WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata; - WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata; - WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata; - WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata; - WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata; - WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "010001" => reg_ftt.out_ren <= apbi.pwdata(4 DOWNTO 0); - reg_ftt.out_reuse <= apbi.pwdata(9 DOWNTO 5); - reg_ftt.out_locked <= apbi.pwdata(14 DOWNTO 10); - - WHEN OTHERS => NULL; - END CASE; - END IF; - END IF; - - END IF; - END PROCESS lpp_lfr_apbreg; - - apbo.pindex <= pindex; - apbo.pconfig <= pconfig; - apbo.prdata <= prdata; - -END beh; diff --git a/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg_2.vhd b/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg_2.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFTb/lpp_lfr_apbreg_2.vhd +++ /dev/null @@ -1,209 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -LIBRARY lpp; -USE lpp.lpp_lfr_pkg.ALL; ---USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_lfr_apbreg_tb IS - GENERIC ( - pindex : INTEGER := 4; - paddr : INTEGER := 4; - pmask : INTEGER := 16#fff#); - PORT ( - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - - -- AMBA APB Slave Interface - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - - --------------------------------------------------------------------------- - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - --------------------------------------------------------------------------- - MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0) - --------------------------------------------------------------------------- - ); - -END lpp_lfr_apbreg_tb; - -ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS - - CONSTANT REVISION : INTEGER := 1; - - CONSTANT pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1), - 1 => apb_iobar(paddr, pmask)); - - TYPE reg_debug_fft IS RECORD - in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); - - in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0); - in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0); - in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - out_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0); - out_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); - out_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - END RECORD; - SIGNAL reg_ftt : reg_debug_fft; - - SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - -BEGIN -- beh - - --------------------------------------------------------------------------- - sample_f0_wen <= reg_ftt.in_wen_f0; - sample_f1_wen <= reg_ftt.in_wen_f1; - sample_f2_wen <= reg_ftt.in_wen_f2; - - sample_f0_wdata <= reg_ftt.in_data_f0; - sample_f1_wdata <= reg_ftt.in_data_f1; - sample_f2_wdata <= reg_ftt.in_data_f2; - --------------------------------------------------------------------------- - MEM_IN_SM_ReUse <= reg_ftt.out_reuse; - MEM_IN_SM_locked <= reg_ftt.out_locked; - MEM_IN_SM_ren <= reg_ftt.out_ren; - --------------------------------------------------------------------------- - - lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) - VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); - BEGIN - IF HRESETn = '0' THEN - - reg_ftt.in_data_f0 <= (OTHERS => '0'); - reg_ftt.in_data_f1 <= (OTHERS => '0'); - reg_ftt.in_data_f2 <= (OTHERS => '0'); - - reg_ftt.in_wen_f0 <= (OTHERS => '1'); - reg_ftt.in_wen_f1 <= (OTHERS => '1'); - reg_ftt.in_wen_f2 <= (OTHERS => '1'); - - - reg_ftt.out_reuse <= (OTHERS => '0'); - reg_ftt.out_locked <= (OTHERS => '0'); - reg_ftt.out_ren <= (OTHERS => '1'); - - ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - - - reg_ftt.in_wen_f0 <= (OTHERS => '1'); - reg_ftt.in_wen_f1 <= (OTHERS => '1'); - reg_ftt.in_wen_f2 <= (OTHERS => '1'); - reg_ftt.out_ren <= (OTHERS => '1'); - - paddr := "000000"; - paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); - prdata <= (OTHERS => '0'); - IF apbi.psel(pindex) = '1' THEN - -- APB DMA READ -- - CASE paddr(7 DOWNTO 2) IS - --0 - WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0); - WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32); - WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64); - WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0; - - WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0); - WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32); - WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64); - WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1; - - WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0); - WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32); - WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64); - WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2; - - WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*1-1 DOWNTO 32*0); - WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*2-1 DOWNTO 32*1); - WHEN "001110" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*3-1 DOWNTO 32*2); - WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3); - WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4); - - WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren; - prdata(9 DOWNTO 5) <= reg_ftt.out_reuse; - prdata(14 DOWNTO 10) <= reg_ftt.out_locked; - prdata(19 DOWNTO 15) <= MEM_IN_SM_Full; - prdata(24 DOWNTO 20) <= MEM_IN_SM_Empty; - WHEN OTHERS => NULL; - - END CASE; - IF (apbi.pwrite AND apbi.penable) = '1' THEN - -- APB DMA WRITE -- - CASE paddr(7 DOWNTO 2) IS - WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata; - WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata; - WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata; - WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata; - WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata; - WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata; - WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); - WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0); - - WHEN "010001" => reg_ftt.out_ren <= apbi.pwdata(4 DOWNTO 0); - reg_ftt.out_reuse <= apbi.pwdata(9 DOWNTO 5); - reg_ftt.out_locked <= apbi.pwdata(14 DOWNTO 10); - - WHEN OTHERS => NULL; - END CASE; - END IF; - END IF; - - END IF; - END PROCESS lpp_lfr_apbreg; - - apbo.pindex <= pindex; - apbo.pconfig <= pconfig; - apbo.prdata <= prdata; - -END beh; diff --git a/designs/MINI-LFR_testFFTb/lpp_lfr_ms_validation.vhd b/designs/MINI-LFR_testFFTb/lpp_lfr_ms_validation.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testFFTb/lpp_lfr_ms_validation.vhd +++ /dev/null @@ -1,1016 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - - -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.iir_filter.ALL; -USE lpp.spectral_matrix_package.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_Header.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.lpp_fft.ALL; -USE lpp.fft_components.ALL; - -ENTITY lpp_lfr_ms_tb IS - GENERIC ( - Mem_use : INTEGER := use_RAM - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ReUse : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_rData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_Full_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - -- - observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS - - SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL error_wen_f0 : STD_LOGIC; - SIGNAL error_wen_f1 : STD_LOGIC; - SIGNAL error_wen_f2 : STD_LOGIC; - - SIGNAL one_sample_f1_full : STD_LOGIC; - SIGNAL one_sample_f1_wen : STD_LOGIC; - SIGNAL one_sample_f2_full : STD_LOGIC; - SIGNAL one_sample_f2_wen : STD_LOGIC; - - ----------------------------------------------------------------------------- - -- FSM / SWITCH SELECT CHANNEL - ----------------------------------------------------------------------------- - TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); - SIGNAL state_fsm_select_channel : fsm_select_channel; - SIGNAL pre_state_fsm_select_channel : fsm_select_channel; - - SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- FSM LOAD FFT - ----------------------------------------------------------------------------- - TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); - SIGNAL state_fsm_load_FFT : fsm_load_FFT; - SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; - - SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_load : STD_LOGIC; - SIGNAL sample_valid : STD_LOGIC; - SIGNAL sample_valid_r : STD_LOGIC; - SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); - - - ----------------------------------------------------------------------------- - -- FFT - ----------------------------------------------------------------------------- - SIGNAL fft_read : STD_LOGIC; - SIGNAL fft_pong : STD_LOGIC; - SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL fft_data_valid : STD_LOGIC; - SIGNAL fft_ready : STD_LOGIC; - ----------------------------------------------------------------------------- --- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); - SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; - SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL current_fifo_empty : STD_LOGIC; - SIGNAL current_fifo_locked : STD_LOGIC; - SIGNAL current_fifo_full : STD_LOGIC; --- SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); - - ----------------------------------------------------------------------------- --- SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - --- SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); --- SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); - SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL SM_correlation_start : STD_LOGIC; - SIGNAL SM_correlation_auto : STD_LOGIC; - SIGNAL SM_correlation_done : STD_LOGIC; - SIGNAL SM_correlation_done_reg1 : STD_LOGIC; - SIGNAL SM_correlation_done_reg2 : STD_LOGIC; - SIGNAL SM_correlation_done_reg3 : STD_LOGIC; - SIGNAL SM_correlation_begin : STD_LOGIC; - - SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; - SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; - - SIGNAL current_matrix_write : STD_LOGIC; - SIGNAL current_matrix_wait_empty : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL fifo_0_ready : STD_LOGIC; - SIGNAL fifo_1_ready : STD_LOGIC; - SIGNAL fifo_ongoing : STD_LOGIC; - - SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; - SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; - SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); - SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- TIME REG & INFOs - ----------------------------------------------------------------------------- - SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); - - SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - - SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); - - --SIGNAL time_update_f0_A : STD_LOGIC; - --SIGNAL time_update_f0_B : STD_LOGIC; - --SIGNAL time_update_f1 : STD_LOGIC; - --SIGNAL time_update_f2 : STD_LOGIC; - -- - SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); - SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); - SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); - - SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); - SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); - SIGNAL status_component_fifo_0_end : STD_LOGIC; - SIGNAL status_component_fifo_1_end : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); - - SIGNAL fft_ready_reg : STD_LOGIC; - SIGNAL fft_ready_rising_down : STD_LOGIC; - - SIGNAL sample_load_reg : STD_LOGIC; - SIGNAL sample_load_rising_down : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wen_head_in : STD_LOGIC; - SIGNAL sample_f1_wen_head_out : STD_LOGIC; - SIGNAL sample_f1_full_head_in : STD_LOGIC; - SIGNAL sample_f1_full_head_out : STD_LOGIC; - SIGNAL sample_f1_empty_head_in : STD_LOGIC; - - SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -BEGIN - - - error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; - - - switch_f0_inst : spectral_matrix_switch_f0 - PORT MAP ( - clk => clk, - rstn => rstn, - - sample_wen => sample_f0_wen, - - fifo_A_empty => sample_f0_A_empty, - fifo_A_full => sample_f0_A_full, - fifo_A_wen => sample_f0_A_wen, - - fifo_B_empty => sample_f0_B_empty, - fifo_B_full => sample_f0_B_full, - fifo_B_wen => sample_f0_B_wen, - - error_wen => error_wen_f0); -- TODO - - ----------------------------------------------------------------------------- - -- FIFO IN - ----------------------------------------------------------------------------- - lppFIFOxN_f0_a : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f0_A_wen, - wdata => sample_f0_wdata, - - ren => sample_f0_A_ren, - rdata => sample_f0_A_rdata, - - empty => sample_f0_A_empty, - full => sample_f0_A_full, - almost_full => OPEN); - - lppFIFOxN_f0_b : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f0_B_wen, - wdata => sample_f0_wdata, - ren => sample_f0_B_ren, - rdata => sample_f0_B_rdata, - empty => sample_f0_B_empty, - full => sample_f0_B_full, - almost_full => OPEN); - - ----------------------------------------------------------------------------- - -- sample_f1_wen in - -- sample_f1_wdata in - -- sample_f1_full OUT - - sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; - sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; - sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; - - lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head - PORT MAP ( - clk => clk, - rstn => rstn, - in_wen => sample_f1_wen_head_in, - in_data => sample_f1_wdata, - in_full => sample_f1_full_head_in, - in_empty => sample_f1_empty_head_in, - out_wen => sample_f1_wen_head_out, - out_data => sample_f1_wdata_head, - out_full => sample_f1_full_head_out); - - sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; - - - lppFIFOxN_f1 : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f1_wen_head, - wdata => sample_f1_wdata_head, - ren => sample_f1_ren, - rdata => sample_f1_rdata, - empty => sample_f1_empty, - full => sample_f1_full, - almost_full => sample_f1_almost_full); - - - one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - one_sample_f1_full <= '0'; - error_wen_f1 <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF sample_f1_full_head_out = '0' THEN - one_sample_f1_full <= '0'; - ELSE - one_sample_f1_full <= '1'; - END IF; - error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - - lppFIFOxN_f2 : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f2_wen, - wdata => sample_f2_wdata, - ren => sample_f2_ren, - rdata => sample_f2_rdata, - empty => sample_f2_empty, - full => sample_f2_full, - almost_full => OPEN); - - - one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - one_sample_f2_full <= '0'; - error_wen_f2 <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF sample_f2_full = "00000" THEN - one_sample_f2_full <= '0'; - ELSE - one_sample_f2_full <= '1'; - END IF; - error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- FSM SELECT CHANNEL - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - state_fsm_select_channel <= IDLE; - ELSIF clk'EVENT AND clk = '1' THEN - CASE state_fsm_select_channel IS - WHEN IDLE => - IF sample_f1_full = "11111" THEN - state_fsm_select_channel <= SWITCH_F1; - ELSIF sample_f1_almost_full = "00000" THEN - IF sample_f0_A_full = "11111" THEN - state_fsm_select_channel <= SWITCH_F0_A; - ELSIF sample_f0_B_full = "11111" THEN - state_fsm_select_channel <= SWITCH_F0_B; - ELSIF sample_f2_full = "11111" THEN - state_fsm_select_channel <= SWITCH_F2; - END IF; - END IF; - - WHEN SWITCH_F0_A => - IF sample_f0_A_empty = "11111" THEN - state_fsm_select_channel <= IDLE; - END IF; - WHEN SWITCH_F0_B => - IF sample_f0_B_empty = "11111" THEN - state_fsm_select_channel <= IDLE; - END IF; - WHEN SWITCH_F1 => - IF sample_f1_empty = "11111" THEN - state_fsm_select_channel <= IDLE; - END IF; - WHEN SWITCH_F2 => - IF sample_f2_empty = "11111" THEN - state_fsm_select_channel <= IDLE; - END IF; - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - pre_state_fsm_select_channel <= IDLE; - ELSIF clk'EVENT AND clk = '1' THEN - pre_state_fsm_select_channel <= state_fsm_select_channel; - END IF; - END PROCESS; - - - ----------------------------------------------------------------------------- - -- SWITCH SELECT CHANNEL - ----------------------------------------------------------------------------- - sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE - sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE - sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE - sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE - (OTHERS => '1'); - - sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE - sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE - sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE - sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE - (OTHERS => '0'); - - sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE - sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE - sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE - sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE - - - sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); - sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); - sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); - sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); - - - status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE - time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE - time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE - time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 - - ----------------------------------------------------------------------------- - -- FSM LOAD FFT - ----------------------------------------------------------------------------- - - sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE - sample_ren_s WHEN sample_load = '1' ELSE - (OTHERS => '1'); - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= IDLE; - status_MS_input <= (OTHERS => '0'); - --next_state_fsm_load_FFT <= IDLE; - --sample_valid <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN - CASE state_fsm_load_FFT IS - WHEN IDLE => - --sample_valid <= '0'; - sample_ren_s <= (OTHERS => '1'); - IF sample_full = "11111" AND sample_load = '1' THEN - state_fsm_load_FFT <= FIFO_1; - status_MS_input <= status_channel; - END IF; - - WHEN FIFO_1 => - sample_ren_s <= "1111" & NOT(sample_load); - IF sample_empty(0) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_2; - END IF; - - WHEN FIFO_2 => - sample_ren_s <= "111" & NOT(sample_load) & '1'; - IF sample_empty(1) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_3; - END IF; - - WHEN FIFO_3 => - sample_ren_s <= "11" & NOT(sample_load) & "11"; - IF sample_empty(2) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_4; - END IF; - - WHEN FIFO_4 => - sample_ren_s <= '1' & NOT(sample_load) & "111"; - IF sample_empty(3) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_5; - END IF; - - WHEN FIFO_5 => - sample_ren_s <= NOT(sample_load) & "1111"; - IF sample_empty(4) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= IDLE; - END IF; - WHEN OTHERS => NULL; - END CASE; - END IF; - END PROCESS; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - sample_valid_r <= '0'; - next_state_fsm_load_FFT <= IDLE; - ELSIF clk'EVENT AND clk = '1' THEN - next_state_fsm_load_FFT <= state_fsm_load_FFT; - IF sample_ren_s = "11111" THEN - sample_valid_r <= '0'; - ELSE - sample_valid_r <= '1'; - END IF; - END IF; - END PROCESS; - - sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; - - sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE - sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE - sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE - sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE - sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE - - ----------------------------------------------------------------------------- - -- FFT - ----------------------------------------------------------------------------- - lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT - PORT MAP ( - clk => clk, - rstn => rstn, - sample_valid => sample_valid, - fft_read => fft_read, - sample_data => sample_data, - sample_load => sample_load, - fft_pong => fft_pong, - fft_data_im => fft_data_im, - fft_data_re => fft_data_re, - fft_data_valid => fft_data_valid, - fft_ready => fft_ready); - - observation_vector_0(11 DOWNTO 0) <= "000" & --11 10 - fft_ongoing_counter & --9 8 - sample_load_rising_down & --7 - fft_ready_rising_down & --6 - fft_ready & --5 - fft_data_valid & --4 - fft_pong & --3 - sample_load & --2 - fft_read & --1 - sample_valid; --0 - - ----------------------------------------------------------------------------- - fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; - sample_load_rising_down <= sample_load_reg AND NOT sample_load; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - fft_ready_reg <= '0'; - sample_load_reg <= '0'; - - fft_ongoing_counter <= '0'; - ELSIF clk'event AND clk = '1' THEN - fft_ready_reg <= fft_ready; - sample_load_reg <= sample_load; - - IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN - fft_ongoing_counter <= '0'; - --- CASE fft_ongoing_counter IS --- WHEN "01" => fft_ongoing_counter <= "00"; ----- WHEN "10" => fft_ongoing_counter <= "01"; --- WHEN OTHERS => NULL; --- END CASE; - ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN - fft_ongoing_counter <= '1'; --- CASE fft_ongoing_counter IS --- WHEN "00" => fft_ongoing_counter <= "01"; ----- WHEN "01" => fft_ongoing_counter <= "10"; --- WHEN OTHERS => NULL; --- END CASE; - END IF; - - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - state_fsm_load_MS_memory <= IDLE; - current_fifo_load <= "00001"; - ELSIF clk'EVENT AND clk = '1' THEN - CASE state_fsm_load_MS_memory IS - WHEN IDLE => - IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN - state_fsm_load_MS_memory <= LOAD_FIFO; - END IF; - WHEN LOAD_FIFO => - IF current_fifo_full = '1' THEN - state_fsm_load_MS_memory <= TRASH_FFT; - END IF; - WHEN TRASH_FFT => - IF fft_ready = '0' THEN - state_fsm_load_MS_memory <= IDLE; - current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); - END IF; - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - - current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE - MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE - MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE - MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE - MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE - - current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE - MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE - MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE - MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE - MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE - - current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE - MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE - MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE - MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE - MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE - - fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; - - all_fifo : FOR I IN 4 DOWNTO 0 GENERATE - MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' - AND state_fsm_load_MS_memory = LOAD_FIFO - AND current_fifo_load(I) = '1' - ELSE '1'; - END GENERATE all_fifo; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - MEM_IN_SM_wen <= (OTHERS => '1'); - ELSIF clk'EVENT AND clk = '1' THEN - MEM_IN_SM_wen <= MEM_IN_SM_wen_s; - END IF; - END PROCESS; - - MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & - (fft_data_im & fft_data_re) & - (fft_data_im & fft_data_re) & - (fft_data_im & fft_data_re) & - (fft_data_im & fft_data_re); - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - Mem_In_SpectralMatrix : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 32, --16, - Addr_sz => 8, --8 - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => MEM_IN_SM_ReUse, - - wen => MEM_IN_SM_wen, - wdata => MEM_IN_SM_wData, - - ren => MEM_IN_SM_ren, - rdata => MEM_IN_SM_rData, - full => MEM_IN_SM_Full, - empty => MEM_IN_SM_Empty, - almost_full => OPEN); - - MEM_IN_SM_Full_pad <= MEM_IN_SM_Full; - MEM_IN_SM_Empty_pad <= MEM_IN_SM_Empty; - - ------------------------------------------------------------------------------- - - --observation_vector_1(11 DOWNTO 0) <= '0' & - -- SM_correlation_done & --4 - -- SM_correlation_auto & --3 - -- SM_correlation_start & - -- SM_correlation_start & --7 - -- status_MS_input(1 DOWNTO 0)& --6..5 - -- MEM_IN_SM_locked(4 DOWNTO 0); --4..0 - - ------------------------------------------------------------------------------- - --MS_control_1 : MS_control - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - - -- current_status_ms => status_MS_input, - - -- fifo_in_lock => MEM_IN_SM_locked, - -- fifo_in_data => MEM_IN_SM_rdata, - -- fifo_in_full => MEM_IN_SM_Full, - -- fifo_in_empty => MEM_IN_SM_Empty, - -- fifo_in_ren => MEM_IN_SM_ren, - -- fifo_in_reuse => MEM_IN_SM_ReUse, - - -- fifo_out_data => SM_in_data, - -- fifo_out_ren => SM_in_ren, - -- fifo_out_empty => SM_in_empty, - - -- current_status_component => status_component, - - -- correlation_start => SM_correlation_start, - -- correlation_auto => SM_correlation_auto, - -- correlation_done => SM_correlation_done); - - - --MS_calculation_1 : MS_calculation - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - - -- fifo_in_data => SM_in_data, - -- fifo_in_ren => SM_in_ren, - -- fifo_in_empty => SM_in_empty, - - -- fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO - -- fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO - -- fifo_out_full => MEM_OUT_SM_Full_s, -- TODO - - -- correlation_start => SM_correlation_start, - -- correlation_auto => SM_correlation_auto, - -- correlation_begin => SM_correlation_begin, - -- correlation_done => SM_correlation_done); - - ------------------------------------------------------------------------------- - --PROCESS (clk, rstn) - --BEGIN -- PROCESS - -- IF rstn = '0' THEN -- asynchronous reset (active low) - -- current_matrix_write <= '0'; - -- current_matrix_wait_empty <= '1'; - -- status_component_fifo_0 <= (OTHERS => '0'); - -- status_component_fifo_1 <= (OTHERS => '0'); - -- status_component_fifo_0_end <= '0'; - -- status_component_fifo_1_end <= '0'; - -- SM_correlation_done_reg1 <= '0'; - -- SM_correlation_done_reg2 <= '0'; - -- SM_correlation_done_reg3 <= '0'; - - -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - -- SM_correlation_done_reg1 <= SM_correlation_done; - -- SM_correlation_done_reg2 <= SM_correlation_done_reg1; - -- SM_correlation_done_reg3 <= SM_correlation_done_reg2; - -- status_component_fifo_0_end <= '0'; - -- status_component_fifo_1_end <= '0'; - -- IF SM_correlation_begin = '1' THEN - -- IF current_matrix_write = '0' THEN - -- status_component_fifo_0 <= status_component; - -- ELSE - -- status_component_fifo_1 <= status_component; - -- END IF; - -- END IF; - - -- IF SM_correlation_done_reg3 = '1' THEN - -- IF current_matrix_write = '0' THEN - -- status_component_fifo_0_end <= '1'; - -- ELSE - -- status_component_fifo_1_end <= '1'; - -- END IF; - -- current_matrix_wait_empty <= '1'; - -- current_matrix_write <= NOT current_matrix_write; - -- END IF; - - -- IF current_matrix_wait_empty <= '1' THEN - -- IF current_matrix_write = '0' THEN - -- current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); - -- ELSE - -- current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); - -- END IF; - -- END IF; - - -- END IF; - --END PROCESS; - - --MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE - -- '1' WHEN SM_correlation_done_reg1 = '1' ELSE - -- '1' WHEN SM_correlation_done_reg2 = '1' ELSE - -- '1' WHEN SM_correlation_done_reg3 = '1' ELSE - -- '1' WHEN current_matrix_wait_empty = '1' ELSE - -- MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE - -- MEM_OUT_SM_Full(1); - - --MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; - --MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; - - --MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; - ------------------------------------------------------------------------------- - - --Mem_Out_SpectralMatrix : lppFIFOxN - -- GENERIC MAP ( - -- tech => 0, - -- Mem_use => Mem_use, - -- Data_sz => 32, - -- Addr_sz => 8, - -- FifoCnt => 2) - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - - -- ReUse => (OTHERS => '0'), - - -- wen => MEM_OUT_SM_Write, - -- wdata => MEM_OUT_SM_Data_in, - - -- ren => MEM_OUT_SM_Read, - -- rdata => MEM_OUT_SM_Data_out, - - -- full => MEM_OUT_SM_Full, - -- empty => MEM_OUT_SM_Empty, - -- almost_full => OPEN); - --- ----------------------------------------------------------------------------- ----- MEM_OUT_SM_Read <= "00"; --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- fifo_0_ready <= '0'; --- fifo_1_ready <= '0'; --- fifo_ongoing <= '0'; --- ELSIF clk'EVENT AND clk = '1' THEN --- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN --- fifo_ongoing <= '1'; --- fifo_0_ready <= '0'; --- ELSIF status_component_fifo_0_end = '1' THEN --- fifo_0_ready <= '1'; --- END IF; - --- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN --- fifo_ongoing <= '0'; --- fifo_1_ready <= '0'; --- ELSIF status_component_fifo_1_end = '1' THEN --- fifo_1_ready <= '1'; --- END IF; - --- END IF; --- END PROCESS; - --- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE --- '1' WHEN fifo_0_ready = '0' ELSE --- FSM_DMA_fifo_ren; - --- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE --- '1' WHEN fifo_1_ready = '0' ELSE --- FSM_DMA_fifo_ren; - --- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE --- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE --- '1'; - --- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE --- status_component_fifo_1; - --- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE --- MEM_OUT_SM_Data_out(63 DOWNTO 32); - --- ----------------------------------------------------------------------------- --- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma --- PORT MAP ( --- HCLK => clk, --- HRESETn => rstn, - --- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --- fifo_data => FSM_DMA_fifo_data, --- fifo_empty => FSM_DMA_fifo_empty, --- fifo_ren => FSM_DMA_fifo_ren, - --- dma_addr => dma_addr, --- dma_data => dma_data, --- dma_valid => dma_valid, --- dma_valid_burst => dma_valid_burst, --- dma_ren => dma_ren, --- dma_done => dma_done, - --- ready_matrix_f0 => ready_matrix_f0, --- ready_matrix_f1 => ready_matrix_f1, --- ready_matrix_f2 => ready_matrix_f2, - --- error_bad_component_error => error_bad_component_error, --- error_buffer_full => error_buffer_full, - --- debug_reg => debug_reg, --- status_ready_matrix_f0 => status_ready_matrix_f0, --- status_ready_matrix_f1 => status_ready_matrix_f1, --- status_ready_matrix_f2 => status_ready_matrix_f2, - --- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, --- config_active_interruption_onError => config_active_interruption_onError, - --- addr_matrix_f0 => addr_matrix_f0, --- addr_matrix_f1 => addr_matrix_f1, --- addr_matrix_f2 => addr_matrix_f2, - --- matrix_time_f0 => matrix_time_f0, --- matrix_time_f1 => matrix_time_f1, --- matrix_time_f2 => matrix_time_f2 --- ); --- ----------------------------------------------------------------------------- - - - - - --- ----------------------------------------------------------------------------- --- -- TIME MANAGMENT --- ----------------------------------------------------------------------------- --- all_time <= coarse_time & fine_time; --- -- --- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; --- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; --- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; --- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; - --- all_time_reg: FOR I IN 0 TO 3 GENERATE - --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- f_empty_reg(I) <= '1'; --- ELSIF clk'event AND clk = '1' THEN --- f_empty_reg(I) <= f_empty(I); --- END IF; --- END PROCESS; - --- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; - --- s_m_t_m_f0_A : spectral_matrix_time_managment --- PORT MAP ( --- clk => clk, --- rstn => rstn, --- time_in => all_time, --- update_1 => time_update_f(I), --- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) --- ); - --- END GENERATE all_time_reg; - --- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); --- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); --- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); --- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); - --- ----------------------------------------------------------------------------- - -END Behavioral; diff --git a/designs/MINI-LFR_testMS/MINI_LFR_top.vhd b/designs/MINI-LFR_testMS/MINI_LFR_top.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testMS/MINI_LFR_top.vhd +++ /dev/null @@ -1,700 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY MINI_LFR_top IS - - PORT ( - clk_50 : IN STD_LOGIC; - clk_49 : IN STD_LOGIC; - reset : IN STD_LOGIC; - --BPs - BP0 : IN STD_LOGIC; - BP1 : IN STD_LOGIC; - --LEDs - LED0 : OUT STD_LOGIC; - LED1 : OUT STD_LOGIC; - LED2 : OUT STD_LOGIC; - --UARTs - TXD1 : IN STD_LOGIC; - RXD1 : OUT STD_LOGIC; - nCTS1 : OUT STD_LOGIC; - nRTS1 : IN STD_LOGIC; - - TXD2 : IN STD_LOGIC; - RXD2 : OUT STD_LOGIC; - nCTS2 : OUT STD_LOGIC; - nDTR2 : IN STD_LOGIC; - nRTS2 : IN STD_LOGIC; - nDCD2 : OUT STD_LOGIC; - - --EXT CONNECTOR - IO0 : INOUT STD_LOGIC; - IO1 : INOUT STD_LOGIC; - IO2 : INOUT STD_LOGIC; - IO3 : INOUT STD_LOGIC; - IO4 : INOUT STD_LOGIC; - IO5 : INOUT STD_LOGIC; - IO6 : INOUT STD_LOGIC; - IO7 : INOUT STD_LOGIC; - IO8 : INOUT STD_LOGIC; - IO9 : INOUT STD_LOGIC; - IO10 : INOUT STD_LOGIC; - IO11 : INOUT STD_LOGIC; - - --SPACE WIRE - SPW_EN : OUT STD_LOGIC; -- 0 => off - SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK - SPW_NOM_SIN : IN STD_LOGIC; - SPW_NOM_DOUT : OUT STD_LOGIC; - SPW_NOM_SOUT : OUT STD_LOGIC; - SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK - SPW_RED_SIN : IN STD_LOGIC; - SPW_RED_DOUT : OUT STD_LOGIC; - SPW_RED_SOUT : OUT STD_LOGIC; - -- MINI LFR ADC INPUTS - ADC_nCS : OUT STD_LOGIC; - ADC_CLK : OUT STD_LOGIC; - ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - - -- SRAM - SRAM_nWE : OUT STD_LOGIC; - SRAM_CE : OUT STD_LOGIC; - SRAM_nOE : OUT STD_LOGIC; - SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END MINI_LFR_top; - - -ARCHITECTURE beh OF MINI_LFR_top IS - COMPONENT lpp_lfr_apbreg_tb - GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - MEM_IN_SM_wData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Full_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_locked_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_2 : IN STD_LOGIC; - MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_lfr_ms_tb - GENERIC ( - Mem_use : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - MEM_IN_SM_wData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Full_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_locked_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC; - MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); - END COMPONENT; - - - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - -- - SIGNAL errorn : STD_LOGIC; - -- UART AHB --------------------------------------------------------------- - SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data - SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data - SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data - -- - SIGNAL I00_s : STD_LOGIC; - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - -- - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; --- SIGNAL clkmn : STD_ULOGIC; --- SIGNAL txclk : STD_ULOGIC; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_s : Samples(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_nCS_sig : STD_LOGIC; - SIGNAL ADC_CLK_sig : STD_LOGIC; - SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); - - SIGNAL bias_fail_sw_sig : STD_LOGIC; - - SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); - ----------------------------------------------------------------------------- - - - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - SIGNAL MEM_OUT_SM_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full_pad : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full_pad_2 : STD_LOGIC; - SIGNAL MEM_OUT_SM_Empty_pad : STD_LOGIC_VECTOR(1 DOWNTO 0); - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_Full_out : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_Empty_out : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_locked_out : STD_LOGIC_VECTOR(4 DOWNTO 0); - - - - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - - PROCESS(clk_50) - BEGIN - IF clk_50'EVENT AND clk_50 = '1' THEN - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - - PROCESS(clk_49) - BEGIN - IF clk_49'EVENT AND clk_49 = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - LED0 <= '0'; - LED1 <= '0'; - LED2 <= '0'; - --IO1 <= '0'; - --IO2 <= '1'; - --IO3 <= '0'; - --IO4 <= '0'; - --IO5 <= '0'; - --IO6 <= '0'; - --IO7 <= '0'; - --IO8 <= '0'; - --IO9 <= '0'; - --IO10 <= '0'; - --IO11 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - LED0 <= '0'; - LED1 <= '1'; - LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; - --IO1 <= '1'; - --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - --IO3 <= ADC_SDO(0); - --IO4 <= ADC_SDO(1); - --IO5 <= ADC_SDO(2); - --IO6 <= ADC_SDO(3); - --IO7 <= ADC_SDO(4); - --IO8 <= ADC_SDO(5); - --IO9 <= ADC_SDO(6); - --IO10 <= ADC_SDO(7); - --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; - END IF; - END PROCESS; - - PROCESS (clk_24, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - I00_s <= '0'; - ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge - I00_s <= NOT I00_s; - END IF; - END PROCESS; --- IO0 <= I00_s; - - --UARTs - nCTS1 <= '1'; - nCTS2 <= '1'; - nDCD2 <= '1'; - - --EXT CONNECTOR - - --SPACE WIRE - - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) - PORT MAP ( - clk => clk_25, - reset => reset, - errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_time_management_1 : apb_lfr_time_management - GENERIC MAP ( - pindex => 6, - paddr => 6, - pmask => 16#fff#, - FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - clk24_576MHz => clk_24, -- 49.152MHz/2 - resetn => reset, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - coarse_time => coarse_time, - fine_time => fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - SPW_EN <= '1'; - - spw_clk <= clk_50_s; - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DIN, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SIN, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DOUT, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SOUT, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_SIN, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_DIN, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_DOUT, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_SOUT, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(reset, clk_25, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - - lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb - GENERIC MAP ( - pindex => 15, - paddr => 15, - pmask => 16#fff#) - PORT MAP ( - HCLK => clk_25, - HRESETn => reset, - apbi => apbi_ext, - apbo => apbo_ext(15), - - MEM_IN_SM_wData => MEM_IN_SM_wData, - MEM_IN_SM_wen => MEM_IN_SM_wen, - MEM_IN_SM_Full_out => MEM_IN_SM_Full_out, - MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out, - MEM_IN_SM_locked_out => MEM_IN_SM_locked_out, - - MEM_OUT_SM_ren => MEM_OUT_SM_ren , - MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , - MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad , - MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 , - MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad); - - lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb - GENERIC MAP ( - Mem_use =>use_RAM) - PORT MAP ( - clk => clk_25, - rstn => reset, - - MEM_IN_SM_wData => MEM_IN_SM_wData, - MEM_IN_SM_wen => MEM_IN_SM_wen, - MEM_IN_SM_Full_out => MEM_IN_SM_Full_out, - MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out, - MEM_IN_SM_locked_out => MEM_IN_SM_locked_out, - - MEM_OUT_SM_Read => MEM_OUT_SM_ren , - MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , - MEM_OUT_SM_Full_pad => MEM_OUT_SM_Full_pad , - MEM_OUT_SM_Full_pad_2 => MEM_OUT_SM_Full_pad_2 , - MEM_OUT_SM_Empty_pad => MEM_OUT_SM_Empty_pad, - - error_input_fifo_write => OPEN, - observation_vector_0 => observation_vector_0, - observation_vector_1 => observation_vector_1); - - ----------------------------------------------------------------------------- - - - - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; - END GENERATE all_sample; - - - - top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 - GENERIC MAP( - ChannelCount => 8, - SampleNbBits => 14, - ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 - ncycle_cnv => 249) -- 49 152 000 / 98304 /2 - PORT MAP ( - -- CONV - cnv_clk => clk_24, - cnv_rstn => reset, - cnv => ADC_nCS_sig, - -- DATA - clk => clk_25, - rstn => reset, - sck => ADC_CLK_sig, - sdo => ADC_SDO_sig, - -- SAMPLE - sample => sample, - sample_val => sample_val); - - --IO10 <= ADC_SDO_sig(5); - --IO9 <= ADC_SDO_sig(4); - --IO8 <= ADC_SDO_sig(3); - - ADC_nCS <= ADC_nCS_sig; - ADC_CLK <= ADC_CLK_sig; - ADC_SDO_sig <= ADC_SDO; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) - PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); - - --pio_pad_0 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); - --pio_pad_1 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); - --pio_pad_2 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); - --pio_pad_3 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); - --pio_pad_4 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); - --pio_pad_5 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); - --pio_pad_6 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); - --pio_pad_7 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - IO0 <= '0'; - IO1 <= '0'; - IO2 <= '0'; - IO3 <= '0'; - IO4 <= '0'; - IO5 <= '0'; - IO6 <= '0'; - IO7 <= '0'; - IO8 <= '0'; - IO9 <= '0'; - IO10 <= '0'; - IO11 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - CASE gpioo.dout(2 DOWNTO 0) IS - WHEN "011" => - IO0 <= observation_reg(0); - IO1 <= observation_reg(1); - IO2 <= observation_reg(2); - IO3 <= observation_reg(3); - IO4 <= observation_reg(4); - IO5 <= observation_reg(5); - IO6 <= observation_reg(6); - IO7 <= observation_reg(7); - IO8 <= observation_reg(8); - IO9 <= observation_reg(9); - IO10 <= observation_reg(10); - IO11 <= observation_reg(11); - WHEN "001" => - IO0 <= observation_reg(0 + 12); - IO1 <= observation_reg(1 + 12); - IO2 <= observation_reg(2 + 12); - IO3 <= observation_reg(3 + 12); - IO4 <= observation_reg(4 + 12); - IO5 <= observation_reg(5 + 12); - IO6 <= observation_reg(6 + 12); - IO7 <= observation_reg(7 + 12); - IO8 <= observation_reg(8 + 12); - IO9 <= observation_reg(9 + 12); - IO10 <= observation_reg(10 + 12); - IO11 <= observation_reg(11 + 12); - WHEN "010" => - IO0 <= observation_reg(0 + 12 + 12); - IO1 <= observation_reg(1 + 12 + 12); - IO2 <= observation_reg(2 + 12 + 12); - IO3 <= observation_reg(3 + 12 + 12); - IO4 <= observation_reg(4 + 12 + 12); - IO5 <= observation_reg(5 + 12 + 12); - IO6 <= observation_reg(6 + 12 + 12); - IO7 <= observation_reg(7 + 12 + 12); - IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2); - IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5); - IO10 <= ADC_SDO(6) OR ADC_SDO(7) ; - IO11 <= '0'; - WHEN "000" => - IO0 <= observation_vector_0(0); - IO1 <= observation_vector_0(1); - IO2 <= observation_vector_0(2); - IO3 <= observation_vector_0(3); - IO4 <= observation_vector_0(4); - IO5 <= observation_vector_0(5); - IO6 <= observation_vector_0(6); - IO7 <= observation_vector_0(7); - IO8 <= observation_vector_0(8); - IO9 <= observation_vector_0(9); - IO10 <= observation_vector_0(10); - IO11 <= observation_vector_0(11); - WHEN "100" => - IO0 <= observation_vector_1(0); - IO1 <= observation_vector_1(1); - IO2 <= observation_vector_1(2); - IO3 <= observation_vector_1(3); - IO4 <= observation_vector_1(4); - IO5 <= observation_vector_1(5); - IO6 <= observation_vector_1(6); - IO7 <= observation_vector_1(7); - IO8 <= observation_vector_1(8); - IO9 <= observation_vector_1(9); - IO10 <= observation_vector_1(10); - IO11 <= observation_vector_1(11); - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - -END beh; diff --git a/designs/MINI-LFR_testMS/Makefile b/designs/MINI-LFR_testMS/Makefile deleted file mode 100644 --- a/designs/MINI-LFR_testMS/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=MINI_LFR_top -BOARD=MINI-LFR -include $(VHDLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_uart \ - ./lpp_usb \ - ./dsp/lpp_fft_rtax \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP =i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/MINI-LFR_testMS/fft_test.vhd b/designs/MINI-LFR_testMS/fft_test.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testMS/fft_test.vhd +++ /dev/null @@ -1,75 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - - -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.iir_filter.ALL; -USE lpp.spectral_matrix_package.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_Header.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.lpp_fft.ALL; -USE lpp.fft_components.ALL; - -ENTITY lpp_lfr_ms IS - GENERIC ( - Mem_use : INTEGER := use_RAM - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - ); -END; - -ARCHITECTURE Behavioral OF lpp_lfr_ms IS - -BEGIN - - ----------------------------------------------------------------------------- - - lppFIFOxN_f0_a : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => sample_f0_A_wen, - wdata => sample_f0_wdata, - - ren => sample_f0_A_ren, - rdata => sample_f0_A_rdata, - - empty => sample_f0_A_empty, - full => sample_f0_A_full, - almost_full => OPEN); - - ----------------------------------------------------------------------------- - - lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT - PORT MAP ( - clk => clk, - rstn => rstn, - sample_valid => sample_valid, -- WRITE in - fft_read => fft_read, -- READ in - sample_data => sample_data, -- WRITE in - sample_load => sample_load, -- WRITE out - fft_pong => fft_pong, -- READ out - fft_data_im => fft_data_im, -- READ out - fft_data_re => fft_data_re, -- READ out - fft_data_valid => fft_data_valid, -- READ out - fft_ready => fft_ready); -- READ out - - ----------------------------------------------------------------------------- - -END Behavioral; diff --git a/designs/MINI-LFR_testMS/lpp_lfr_apbreg.vhd b/designs/MINI-LFR_testMS/lpp_lfr_apbreg.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testMS/lpp_lfr_apbreg.vhd +++ /dev/null @@ -1,169 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -LIBRARY lpp; -USE lpp.lpp_lfr_pkg.ALL; ---USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_lfr_apbreg_tb IS - GENERIC ( - pindex : INTEGER := 4; - paddr : INTEGER := 4; - pmask : INTEGER := 16#fff#); - PORT ( - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - - -- AMBA APB Slave Interface - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - - --------------------------------------------------------------------------- - MEM_IN_SM_wData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Full_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_locked_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - --------------------------------------------------------------------------- - MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_2 : IN STD_LOGIC; - MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0) - --------------------------------------------------------------------------- - ); - -END lpp_lfr_apbreg_tb; - -ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS - - CONSTANT REVISION : INTEGER := 1; - - CONSTANT pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, 16#19#, 0, REVISION, 1), - 1 => apb_iobar(paddr, pmask)); - - TYPE reg_debug_fft IS RECORD - MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - -- - out_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); - END RECORD; - SIGNAL reg_ftt : reg_debug_fft; - - SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - -BEGIN -- beh - - --------------------------------------------------------------------------- - MEM_IN_SM_wen <= reg_ftt.MEM_IN_SM_wen; - MEM_IN_SM_wData <= reg_ftt.MEM_IN_SM_wData; - --------------------------------------------------------------------------- - MEM_OUT_SM_ren <= reg_ftt.out_ren; - --------------------------------------------------------------------------- - - lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) - VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); - BEGIN - IF HRESETn = '0' THEN - reg_ftt.MEM_IN_SM_wData <= (OTHERS => '0'); - - reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); - reg_ftt.out_ren <= (OTHERS => '1'); - - ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - - reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); - reg_ftt.out_ren <= (OTHERS => '1'); - - paddr := "000000"; - paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); - prdata <= (OTHERS => '0'); - IF apbi.psel(pindex) = '1' THEN - -- APB DMA READ -- - CASE paddr(7 DOWNTO 2) IS - --0 - WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*1-1 DOWNTO 32*0); - WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*2-1 DOWNTO 32*1); - WHEN "000010" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2); - WHEN "000011" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3); - WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4); - WHEN "000101" => prdata( 4 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wen; - prdata( 9 DOWNTO 5) <= MEM_IN_SM_Full_out; - prdata(14 DOWNTO 10) <= MEM_IN_SM_Empty_out; - prdata(19 DOWNTO 15) <= MEM_IN_SM_locked_out; - - WHEN "000110" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*1-1 DOWNTO 32*0); - WHEN "000111" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*2-1 DOWNTO 32*1); - - WHEN "001000" => prdata(1 DOWNTO 0) <= reg_ftt.out_ren; - prdata(3 DOWNTO 2) <= MEM_OUT_SM_Full; - prdata(5 DOWNTO 4) <= MEM_OUT_SM_Empty; - prdata(6) <= MEM_OUT_SM_Full_2; - WHEN OTHERS => NULL; - - END CASE; - IF (apbi.pwrite AND apbi.penable) = '1' THEN - -- APB DMA WRITE -- - CASE paddr(7 DOWNTO 2) IS - WHEN "000000" => reg_ftt.MEM_IN_SM_wData(32*1-1 DOWNTO 32*0) <= apbi.pwdata(31 DOWNTO 0); - WHEN "000001" => reg_ftt.MEM_IN_SM_wData(32*2-1 DOWNTO 32*1) <= apbi.pwdata(31 DOWNTO 0); - WHEN "000010" => reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2) <= apbi.pwdata(31 DOWNTO 0); - WHEN "000011" => reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3) <= apbi.pwdata(31 DOWNTO 0); - WHEN "000100" => reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4) <= apbi.pwdata(31 DOWNTO 0); - WHEN "000101" => reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0); - - WHEN "001000" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0); - - WHEN OTHERS => NULL; - END CASE; - END IF; - - --IF (apbi.psel(pindex) AND apbi.pwrite AND apbi.penable) = '1' AND paddr(7 DOWNTO 2) = "000101" THEN - -- reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0); - --ELSE - -- reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); - --END IF; - - - END IF; - - END IF; - END PROCESS lpp_lfr_apbreg; - - apbo.pindex <= pindex; - apbo.pconfig <= pconfig; - apbo.prdata <= prdata ; - -END beh; diff --git a/designs/MINI-LFR_testMS/lpp_lfr_ms_validation.vhd b/designs/MINI-LFR_testMS/lpp_lfr_ms_validation.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testMS/lpp_lfr_ms_validation.vhd +++ /dev/null @@ -1,1014 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - - -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.iir_filter.ALL; -USE lpp.spectral_matrix_package.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_Header.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.lpp_fft.ALL; -USE lpp.fft_components.ALL; - -ENTITY lpp_lfr_ms_tb IS - GENERIC ( - Mem_use : INTEGER := use_RAM - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - MEM_IN_SM_wData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Full_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_locked_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC; - MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - - --------------------------------------------------------------------------- - -- - --------------------------------------------------------------------------- - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - -- - observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS - - SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - SIGNAL error_wen_f0 : STD_LOGIC; - SIGNAL error_wen_f1 : STD_LOGIC; - SIGNAL error_wen_f2 : STD_LOGIC; - - SIGNAL one_sample_f1_full : STD_LOGIC; - SIGNAL one_sample_f1_wen : STD_LOGIC; - SIGNAL one_sample_f2_full : STD_LOGIC; - SIGNAL one_sample_f2_wen : STD_LOGIC; - - ----------------------------------------------------------------------------- - -- FSM / SWITCH SELECT CHANNEL - ----------------------------------------------------------------------------- - TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); - SIGNAL state_fsm_select_channel : fsm_select_channel; - SIGNAL pre_state_fsm_select_channel : fsm_select_channel; - - SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- FSM LOAD FFT - ----------------------------------------------------------------------------- - TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); - SIGNAL state_fsm_load_FFT : fsm_load_FFT; - SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; - - SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_load : STD_LOGIC; - SIGNAL sample_valid : STD_LOGIC; - SIGNAL sample_valid_r : STD_LOGIC; - SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); - - - ----------------------------------------------------------------------------- - -- FFT - ----------------------------------------------------------------------------- - SIGNAL fft_read : STD_LOGIC; - SIGNAL fft_pong : STD_LOGIC; - SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL fft_data_valid : STD_LOGIC; - SIGNAL fft_ready : STD_LOGIC; - ----------------------------------------------------------------------------- --- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); - SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; - SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL current_fifo_empty : STD_LOGIC; - SIGNAL current_fifo_locked : STD_LOGIC; - SIGNAL current_fifo_full : STD_LOGIC; - SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); --- SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); --- SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); - SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL SM_correlation_start : STD_LOGIC; - SIGNAL SM_correlation_auto : STD_LOGIC; - SIGNAL SM_correlation_done : STD_LOGIC; - SIGNAL SM_correlation_done_reg1 : STD_LOGIC; - SIGNAL SM_correlation_done_reg2 : STD_LOGIC; - SIGNAL SM_correlation_done_reg3 : STD_LOGIC; - SIGNAL SM_correlation_begin : STD_LOGIC; - - SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; - SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; - - SIGNAL current_matrix_write : STD_LOGIC; - SIGNAL current_matrix_wait_empty : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL fifo_0_ready : STD_LOGIC; - SIGNAL fifo_1_ready : STD_LOGIC; - SIGNAL fifo_ongoing : STD_LOGIC; - - SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; - SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; - SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); --- SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); --- SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- TIME REG & INFOs - ----------------------------------------------------------------------------- - SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); - - SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - - SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); - - --SIGNAL time_update_f0_A : STD_LOGIC; - --SIGNAL time_update_f0_B : STD_LOGIC; - --SIGNAL time_update_f1 : STD_LOGIC; - --SIGNAL time_update_f2 : STD_LOGIC; - -- - SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); - SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); - SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); - - SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); - SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); - SIGNAL status_component_fifo_0_end : STD_LOGIC; - SIGNAL status_component_fifo_1_end : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); - - SIGNAL fft_ready_reg : STD_LOGIC; - SIGNAL fft_ready_rising_down : STD_LOGIC; - - SIGNAL sample_load_reg : STD_LOGIC; - SIGNAL sample_load_rising_down : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL sample_f1_wen_head_in : STD_LOGIC; - SIGNAL sample_f1_wen_head_out : STD_LOGIC; - SIGNAL sample_f1_full_head_in : STD_LOGIC; - SIGNAL sample_f1_full_head_out : STD_LOGIC; - SIGNAL sample_f1_empty_head_in : STD_LOGIC; - - SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -BEGIN - - error_input_fifo_write <=(others => '0'); - observation_vector_0(11 DOWNTO 0) <= (OTHERS => '0'); - --- error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; - - --- switch_f0_inst : spectral_matrix_switch_f0 --- PORT MAP ( --- clk => clk, --- rstn => rstn, - --- sample_wen => sample_f0_wen, - --- fifo_A_empty => sample_f0_A_empty, --- fifo_A_full => sample_f0_A_full, --- fifo_A_wen => sample_f0_A_wen, - --- fifo_B_empty => sample_f0_B_empty, --- fifo_B_full => sample_f0_B_full, --- fifo_B_wen => sample_f0_B_wen, - --- error_wen => error_wen_f0); -- TODO - --- ----------------------------------------------------------------------------- --- -- FIFO IN --- ----------------------------------------------------------------------------- --- lppFIFOxN_f0_a : lppFIFOxN --- GENERIC MAP ( --- tech => 0, --- Mem_use => Mem_use, --- Data_sz => 16, --- Addr_sz => 8, --- FifoCnt => 5) --- PORT MAP ( --- clk => clk, --- rstn => rstn, - --- ReUse => (OTHERS => '0'), - --- wen => sample_f0_A_wen, --- wdata => sample_f0_wdata, - --- ren => sample_f0_A_ren, --- rdata => sample_f0_A_rdata, - --- empty => sample_f0_A_empty, --- full => sample_f0_A_full, --- almost_full => OPEN); - --- lppFIFOxN_f0_b : lppFIFOxN --- GENERIC MAP ( --- tech => 0, --- Mem_use => Mem_use, --- Data_sz => 16, --- Addr_sz => 8, --- FifoCnt => 5) --- PORT MAP ( --- clk => clk, --- rstn => rstn, - --- ReUse => (OTHERS => '0'), - --- wen => sample_f0_B_wen, --- wdata => sample_f0_wdata, --- ren => sample_f0_B_ren, --- rdata => sample_f0_B_rdata, --- empty => sample_f0_B_empty, --- full => sample_f0_B_full, --- almost_full => OPEN); - --- ----------------------------------------------------------------------------- --- -- sample_f1_wen in --- -- sample_f1_wdata in --- -- sample_f1_full OUT - --- sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; --- sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; --- sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; - --- lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head --- PORT MAP ( --- clk => clk, --- rstn => rstn, --- in_wen => sample_f1_wen_head_in, --- in_data => sample_f1_wdata, --- in_full => sample_f1_full_head_in, --- in_empty => sample_f1_empty_head_in, --- out_wen => sample_f1_wen_head_out, --- out_data => sample_f1_wdata_head, --- out_full => sample_f1_full_head_out); - --- sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; - - --- lppFIFOxN_f1 : lppFIFOxN --- GENERIC MAP ( --- tech => 0, --- Mem_use => Mem_use, --- Data_sz => 16, --- Addr_sz => 8, --- FifoCnt => 5) --- PORT MAP ( --- clk => clk, --- rstn => rstn, - --- ReUse => (OTHERS => '0'), - --- wen => sample_f1_wen_head, --- wdata => sample_f1_wdata_head, --- ren => sample_f1_ren, --- rdata => sample_f1_rdata, --- empty => sample_f1_empty, --- full => sample_f1_full, --- almost_full => sample_f1_almost_full); - - --- one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; - --- PROCESS (clk, rstn) --- BEGIN -- PROCESS --- IF rstn = '0' THEN -- asynchronous reset (active low) --- one_sample_f1_full <= '0'; --- error_wen_f1 <= '0'; --- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge --- IF sample_f1_full_head_out = '0' THEN --- one_sample_f1_full <= '0'; --- ELSE --- one_sample_f1_full <= '1'; --- END IF; --- error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; --- END IF; --- END PROCESS; - --- ----------------------------------------------------------------------------- - - --- lppFIFOxN_f2 : lppFIFOxN --- GENERIC MAP ( --- tech => 0, --- Mem_use => Mem_use, --- Data_sz => 16, --- Addr_sz => 8, --- FifoCnt => 5) --- PORT MAP ( --- clk => clk, --- rstn => rstn, - --- ReUse => (OTHERS => '0'), - --- wen => sample_f2_wen, --- wdata => sample_f2_wdata, --- ren => sample_f2_ren, --- rdata => sample_f2_rdata, --- empty => sample_f2_empty, --- full => sample_f2_full, --- almost_full => OPEN); - - --- one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; - --- PROCESS (clk, rstn) --- BEGIN -- PROCESS --- IF rstn = '0' THEN -- asynchronous reset (active low) --- one_sample_f2_full <= '0'; --- error_wen_f2 <= '0'; --- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge --- IF sample_f2_full = "00000" THEN --- one_sample_f2_full <= '0'; --- ELSE --- one_sample_f2_full <= '1'; --- END IF; --- error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; --- END IF; --- END PROCESS; - --- ----------------------------------------------------------------------------- --- -- FSM SELECT CHANNEL --- ----------------------------------------------------------------------------- --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- state_fsm_select_channel <= IDLE; --- ELSIF clk'EVENT AND clk = '1' THEN --- CASE state_fsm_select_channel IS --- WHEN IDLE => --- IF sample_f1_full = "11111" THEN --- state_fsm_select_channel <= SWITCH_F1; --- ELSIF sample_f1_almost_full = "00000" THEN --- IF sample_f0_A_full = "11111" THEN --- state_fsm_select_channel <= SWITCH_F0_A; --- ELSIF sample_f0_B_full = "11111" THEN --- state_fsm_select_channel <= SWITCH_F0_B; --- ELSIF sample_f2_full = "11111" THEN --- state_fsm_select_channel <= SWITCH_F2; --- END IF; --- END IF; - --- WHEN SWITCH_F0_A => --- IF sample_f0_A_empty = "11111" THEN --- state_fsm_select_channel <= IDLE; --- END IF; --- WHEN SWITCH_F0_B => --- IF sample_f0_B_empty = "11111" THEN --- state_fsm_select_channel <= IDLE; --- END IF; --- WHEN SWITCH_F1 => --- IF sample_f1_empty = "11111" THEN --- state_fsm_select_channel <= IDLE; --- END IF; --- WHEN SWITCH_F2 => --- IF sample_f2_empty = "11111" THEN --- state_fsm_select_channel <= IDLE; --- END IF; --- WHEN OTHERS => NULL; --- END CASE; - --- END IF; --- END PROCESS; - --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- pre_state_fsm_select_channel <= IDLE; --- ELSIF clk'EVENT AND clk = '1' THEN --- pre_state_fsm_select_channel <= state_fsm_select_channel; --- END IF; --- END PROCESS; - - --- ----------------------------------------------------------------------------- --- -- SWITCH SELECT CHANNEL --- ----------------------------------------------------------------------------- --- sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE --- sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE --- sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE --- sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE --- (OTHERS => '1'); - --- sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE --- sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE --- sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE --- sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE --- (OTHERS => '0'); - --- sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE --- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE --- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE --- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE - - --- sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); --- sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); --- sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); --- sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); - - --- status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE --- time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE --- time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE --- time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 - --- ----------------------------------------------------------------------------- --- -- FSM LOAD FFT --- ----------------------------------------------------------------------------- - --- sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE --- sample_ren_s WHEN sample_load = '1' ELSE --- (OTHERS => '1'); - --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- sample_ren_s <= (OTHERS => '1'); --- state_fsm_load_FFT <= IDLE; --- status_MS_input <= (OTHERS => '0'); --- --next_state_fsm_load_FFT <= IDLE; --- --sample_valid <= '0'; --- ELSIF clk'EVENT AND clk = '1' THEN --- CASE state_fsm_load_FFT IS --- WHEN IDLE => --- --sample_valid <= '0'; --- sample_ren_s <= (OTHERS => '1'); --- IF sample_full = "11111" AND sample_load = '1' THEN --- state_fsm_load_FFT <= FIFO_1; --- status_MS_input <= status_channel; --- END IF; - --- WHEN FIFO_1 => --- sample_ren_s <= "1111" & NOT(sample_load); --- IF sample_empty(0) = '1' THEN --- sample_ren_s <= (OTHERS => '1'); --- state_fsm_load_FFT <= FIFO_2; --- END IF; - --- WHEN FIFO_2 => --- sample_ren_s <= "111" & NOT(sample_load) & '1'; --- IF sample_empty(1) = '1' THEN --- sample_ren_s <= (OTHERS => '1'); --- state_fsm_load_FFT <= FIFO_3; --- END IF; - --- WHEN FIFO_3 => --- sample_ren_s <= "11" & NOT(sample_load) & "11"; --- IF sample_empty(2) = '1' THEN --- sample_ren_s <= (OTHERS => '1'); --- state_fsm_load_FFT <= FIFO_4; --- END IF; - --- WHEN FIFO_4 => --- sample_ren_s <= '1' & NOT(sample_load) & "111"; --- IF sample_empty(3) = '1' THEN --- sample_ren_s <= (OTHERS => '1'); --- state_fsm_load_FFT <= FIFO_5; --- END IF; - --- WHEN FIFO_5 => --- sample_ren_s <= NOT(sample_load) & "1111"; --- IF sample_empty(4) = '1' THEN --- sample_ren_s <= (OTHERS => '1'); --- state_fsm_load_FFT <= IDLE; --- END IF; --- WHEN OTHERS => NULL; --- END CASE; --- END IF; --- END PROCESS; - --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- sample_valid_r <= '0'; --- next_state_fsm_load_FFT <= IDLE; --- ELSIF clk'EVENT AND clk = '1' THEN --- next_state_fsm_load_FFT <= state_fsm_load_FFT; --- IF sample_ren_s = "11111" THEN --- sample_valid_r <= '0'; --- ELSE --- sample_valid_r <= '1'; --- END IF; --- END IF; --- END PROCESS; - --- sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; - --- sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE --- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE --- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE --- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE --- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE - --- ----------------------------------------------------------------------------- --- -- FFT --- ----------------------------------------------------------------------------- --- lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT --- PORT MAP ( --- clk => clk, --- rstn => rstn, --- sample_valid => sample_valid, --- fft_read => fft_read, --- sample_data => sample_data, --- sample_load => sample_load, --- fft_pong => fft_pong, --- fft_data_im => fft_data_im, --- fft_data_re => fft_data_re, --- fft_data_valid => fft_data_valid, --- fft_ready => fft_ready); - --- observation_vector_0(11 DOWNTO 0) <= "000" & --11 10 --- fft_ongoing_counter & --9 8 --- sample_load_rising_down & --7 --- fft_ready_rising_down & --6 --- fft_ready & --5 --- fft_data_valid & --4 --- fft_pong & --3 --- sample_load & --2 --- fft_read & --1 --- sample_valid; --0 - --- ----------------------------------------------------------------------------- --- fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; --- sample_load_rising_down <= sample_load_reg AND NOT sample_load; - --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- fft_ready_reg <= '0'; --- sample_load_reg <= '0'; - --- fft_ongoing_counter <= '0'; --- ELSIF clk'event AND clk = '1' THEN --- fft_ready_reg <= fft_ready; --- sample_load_reg <= sample_load; - --- IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN --- fft_ongoing_counter <= '0'; - ----- CASE fft_ongoing_counter IS ----- WHEN "01" => fft_ongoing_counter <= "00"; ------- WHEN "10" => fft_ongoing_counter <= "01"; ----- WHEN OTHERS => NULL; ----- END CASE; --- ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN --- fft_ongoing_counter <= '1'; ----- CASE fft_ongoing_counter IS ----- WHEN "00" => fft_ongoing_counter <= "01"; ------- WHEN "01" => fft_ongoing_counter <= "10"; ----- WHEN OTHERS => NULL; ----- END CASE; --- END IF; - --- END IF; --- END PROCESS; - --- ----------------------------------------------------------------------------- --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- state_fsm_load_MS_memory <= IDLE; --- current_fifo_load <= "00001"; --- ELSIF clk'EVENT AND clk = '1' THEN --- CASE state_fsm_load_MS_memory IS --- WHEN IDLE => --- IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN --- state_fsm_load_MS_memory <= LOAD_FIFO; --- END IF; --- WHEN LOAD_FIFO => --- IF current_fifo_full = '1' THEN --- state_fsm_load_MS_memory <= TRASH_FFT; --- END IF; --- WHEN TRASH_FFT => --- IF fft_ready = '0' THEN --- state_fsm_load_MS_memory <= IDLE; --- current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); --- END IF; --- WHEN OTHERS => NULL; --- END CASE; - --- END IF; --- END PROCESS; - --- current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE --- MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE --- MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE --- MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE --- MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE - --- current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE --- MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE --- MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE --- MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE --- MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE - --- current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE --- MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE --- MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE --- MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE --- MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE - --- fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; - --- all_fifo : FOR I IN 4 DOWNTO 0 GENERATE --- MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' --- AND state_fsm_load_MS_memory = LOAD_FIFO --- AND current_fifo_load(I) = '1' --- ELSE '1'; --- END GENERATE all_fifo; - --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- MEM_IN_SM_wen <= (OTHERS => '1'); --- ELSIF clk'EVENT AND clk = '1' THEN --- MEM_IN_SM_wen <= MEM_IN_SM_wen_s; --- END IF; --- END PROCESS; - --- MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & --- (fft_data_im & fft_data_re) & --- (fft_data_im & fft_data_re) & --- (fft_data_im & fft_data_re) & --- (fft_data_im & fft_data_re); - ----------------------------------------------------------------------------- - - MEM_IN_SM_Full_out <= MEM_IN_SM_Full; - MEM_IN_SM_Empty_out <= MEM_IN_SM_Empty; - MEM_IN_SM_locked_out <= MEM_IN_SM_locked; - ----------------------------------------------------------------------------- - Mem_In_SpectralMatrix : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 32, --16, - Addr_sz => 7, --8 - FifoCnt => 5) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => MEM_IN_SM_ReUse, - - wen => MEM_IN_SM_wen, - wdata => MEM_IN_SM_wData, - - ren => MEM_IN_SM_ren, - rdata => MEM_IN_SM_rData, - full => MEM_IN_SM_Full, - empty => MEM_IN_SM_Empty, - almost_full => OPEN); - - ----------------------------------------------------------------------------- - - observation_vector_1(11 DOWNTO 0) <= '0' & - SM_correlation_done & --4 - SM_correlation_auto & --3 - SM_correlation_start & - SM_correlation_start & --7 - status_MS_input(1 DOWNTO 0)& --6..5 - MEM_IN_SM_locked(4 DOWNTO 0); --4..0 - - ----------------------------------------------------------------------------- - MS_control_1 : MS_control - PORT MAP ( - clk => clk, - rstn => rstn, - - current_status_ms => status_MS_input, - - fifo_in_lock => MEM_IN_SM_locked, - fifo_in_data => MEM_IN_SM_rdata, - fifo_in_full => MEM_IN_SM_Full, - fifo_in_empty => MEM_IN_SM_Empty, - fifo_in_ren => MEM_IN_SM_ren, - fifo_in_reuse => MEM_IN_SM_ReUse, - - fifo_out_data => SM_in_data, - fifo_out_ren => SM_in_ren, - fifo_out_empty => SM_in_empty, - - current_status_component => status_component, - - correlation_start => SM_correlation_start, - correlation_auto => SM_correlation_auto, - correlation_done => SM_correlation_done); - - - MS_calculation_1 : MS_calculation - PORT MAP ( - clk => clk, - rstn => rstn, - - fifo_in_data => SM_in_data, - fifo_in_ren => SM_in_ren, - fifo_in_empty => SM_in_empty, - - fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO - fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO - fifo_out_full => MEM_OUT_SM_Full_s, -- TODO - - correlation_start => SM_correlation_start, - correlation_auto => SM_correlation_auto, - correlation_begin => SM_correlation_begin, - correlation_done => SM_correlation_done); - - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - current_matrix_write <= '0'; - current_matrix_wait_empty <= '1'; - status_component_fifo_0 <= (OTHERS => '0'); - status_component_fifo_1 <= (OTHERS => '0'); - status_component_fifo_0_end <= '0'; - status_component_fifo_1_end <= '0'; - SM_correlation_done_reg1 <= '0'; - SM_correlation_done_reg2 <= '0'; - SM_correlation_done_reg3 <= '0'; - - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - SM_correlation_done_reg1 <= SM_correlation_done; - SM_correlation_done_reg2 <= SM_correlation_done_reg1; - SM_correlation_done_reg3 <= SM_correlation_done_reg2; - status_component_fifo_0_end <= '0'; - status_component_fifo_1_end <= '0'; - IF SM_correlation_begin = '1' THEN - IF current_matrix_write = '0' THEN - status_component_fifo_0 <= status_component; - ELSE - status_component_fifo_1 <= status_component; - END IF; - END IF; - - IF SM_correlation_done_reg3 = '1' THEN - IF current_matrix_write = '0' THEN - status_component_fifo_0_end <= '1'; - ELSE - status_component_fifo_1_end <= '1'; - END IF; - current_matrix_wait_empty <= '1'; - current_matrix_write <= NOT current_matrix_write; - END IF; - - IF current_matrix_wait_empty <= '1' THEN - IF current_matrix_write = '0' THEN - current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); - ELSE - current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); - END IF; - END IF; - - END IF; - END PROCESS; - - MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE - '1' WHEN SM_correlation_done_reg1 = '1' ELSE - '1' WHEN SM_correlation_done_reg2 = '1' ELSE - '1' WHEN SM_correlation_done_reg3 = '1' ELSE - '1' WHEN current_matrix_wait_empty = '1' ELSE - MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE - MEM_OUT_SM_Full(1); - - MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; - MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; - - MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; - ----------------------------------------------------------------------------- - - Mem_Out_SpectralMatrix : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Data_sz => 32, - Addr_sz => 8, - FifoCnt => 2) - PORT MAP ( - clk => clk, - rstn => rstn, - - ReUse => (OTHERS => '0'), - - wen => MEM_OUT_SM_Write, - wdata => MEM_OUT_SM_Data_in, - - ren => MEM_OUT_SM_Read, - rdata => MEM_OUT_SM_Data_out, - - full => MEM_OUT_SM_Full, - empty => MEM_OUT_SM_Empty, - almost_full => OPEN); - - MEM_OUT_SM_Full_pad <= MEM_OUT_SM_Full; - MEM_OUT_SM_Full_pad_2 <= MEM_OUT_SM_Full_s; - MEM_OUT_SM_Empty_pad <= MEM_OUT_SM_Empty; - --- ----------------------------------------------------------------------------- ----- MEM_OUT_SM_Read <= "00"; --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- fifo_0_ready <= '0'; --- fifo_1_ready <= '0'; --- fifo_ongoing <= '0'; --- ELSIF clk'EVENT AND clk = '1' THEN --- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN --- fifo_ongoing <= '1'; --- fifo_0_ready <= '0'; --- ELSIF status_component_fifo_0_end = '1' THEN --- fifo_0_ready <= '1'; --- END IF; - --- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN --- fifo_ongoing <= '0'; --- fifo_1_ready <= '0'; --- ELSIF status_component_fifo_1_end = '1' THEN --- fifo_1_ready <= '1'; --- END IF; - --- END IF; --- END PROCESS; - --- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE --- '1' WHEN fifo_0_ready = '0' ELSE --- FSM_DMA_fifo_ren; - --- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE --- '1' WHEN fifo_1_ready = '0' ELSE --- FSM_DMA_fifo_ren; - --- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE --- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE --- '1'; - --- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE --- status_component_fifo_1; - --- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE --- MEM_OUT_SM_Data_out(63 DOWNTO 32); - --- ----------------------------------------------------------------------------- --- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma --- PORT MAP ( --- HCLK => clk, --- HRESETn => rstn, - --- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --- fifo_data => FSM_DMA_fifo_data, --- fifo_empty => FSM_DMA_fifo_empty, --- fifo_ren => FSM_DMA_fifo_ren, - --- dma_addr => dma_addr, --- dma_data => dma_data, --- dma_valid => dma_valid, --- dma_valid_burst => dma_valid_burst, --- dma_ren => dma_ren, --- dma_done => dma_done, - --- ready_matrix_f0 => ready_matrix_f0, --- ready_matrix_f1 => ready_matrix_f1, --- ready_matrix_f2 => ready_matrix_f2, - --- error_bad_component_error => error_bad_component_error, --- error_buffer_full => error_buffer_full, - --- debug_reg => debug_reg, --- status_ready_matrix_f0 => status_ready_matrix_f0, --- status_ready_matrix_f1 => status_ready_matrix_f1, --- status_ready_matrix_f2 => status_ready_matrix_f2, - --- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, --- config_active_interruption_onError => config_active_interruption_onError, - --- addr_matrix_f0 => addr_matrix_f0, --- addr_matrix_f1 => addr_matrix_f1, --- addr_matrix_f2 => addr_matrix_f2, - --- matrix_time_f0 => matrix_time_f0, --- matrix_time_f1 => matrix_time_f1, --- matrix_time_f2 => matrix_time_f2 --- ); --- ----------------------------------------------------------------------------- - - - - - --- ----------------------------------------------------------------------------- --- -- TIME MANAGMENT --- ----------------------------------------------------------------------------- --- all_time <= coarse_time & fine_time; --- -- --- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; --- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; --- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; --- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; - --- all_time_reg: FOR I IN 0 TO 3 GENERATE - --- PROCESS (clk, rstn) --- BEGIN --- IF rstn = '0' THEN --- f_empty_reg(I) <= '1'; --- ELSIF clk'event AND clk = '1' THEN --- f_empty_reg(I) <= f_empty(I); --- END IF; --- END PROCESS; - --- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; - --- s_m_t_m_f0_A : spectral_matrix_time_managment --- PORT MAP ( --- clk => clk, --- rstn => rstn, --- time_in => all_time, --- update_1 => time_update_f(I), --- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) --- ); - --- END GENERATE all_time_reg; - --- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); --- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); --- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); --- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); - --- ----------------------------------------------------------------------------- - -END Behavioral; \ No newline at end of file diff --git a/designs/MINI-LFR_testMS/testbench_ms.vhd b/designs/MINI-LFR_testMS/testbench_ms.vhd deleted file mode 100644 --- a/designs/MINI-LFR_testMS/testbench_ms.vhd +++ /dev/null @@ -1,357 +0,0 @@ -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; - -LIBRARY lpp; -USE lpp.iir_filter.ALL; - -ENTITY testbench_ms IS - -END testbench_ms; - -ARCHITECTURE tb OF testbench_ms IS - ----------------------------------------------------------------------------- - -- COMPONENT ---------------------------------------------------------------- - ----------------------------------------------------------------------------- - COMPONENT lpp_lfr_apbreg_tb - GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - MEM_IN_SM_wData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Full_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_locked_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_2 : IN STD_LOGIC; - MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_lfr_ms_tb - GENERIC ( - Mem_use : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - MEM_IN_SM_wData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - MEM_IN_SM_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Full_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_Empty_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_IN_SM_locked_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC; - MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); - END COMPONENT; - - ----------------------------------------------------------------------------- - -- SIGNAL ------------------------------------------------------------------- - ----------------------------------------------------------------------------- - SIGNAL clk : STD_LOGIC := '0'; - SIGNAL rstn : STD_LOGIC := '0'; - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_type; - - SIGNAL MEM_OUT_SM_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full_pad : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL MEM_OUT_SM_Full_pad_2 : STD_LOGIC; - SIGNAL MEM_OUT_SM_Empty_pad : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); - SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_Full_out : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_Empty_out : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL MEM_IN_SM_locked_out : STD_LOGIC_VECTOR(4 DOWNTO 0); - - - ----------------------------------------------------------------------------- - -- FFT - ----------------------------------------------------------------------------- - TYPE fft_tab_type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL fft_1_re : fft_tab_type; - SIGNAL fft_1_im : fft_tab_type; - SIGNAL fft_2_re : fft_tab_type; - SIGNAL fft_2_im : fft_tab_type; - SIGNAL fft_3_re : fft_tab_type; - SIGNAL fft_3_im : fft_tab_type; - SIGNAL fft_4_re : fft_tab_type; - SIGNAL fft_4_im : fft_tab_type; - SIGNAL fft_5_re : fft_tab_type; - SIGNAL fft_5_im : fft_tab_type; - - SIGNAL counter_1 : INTEGER; - SIGNAL counter_2 : INTEGER; - SIGNAL counter_3 : INTEGER; - SIGNAL counter_4 : INTEGER; - SIGNAL counter_5 : INTEGER; - - SIGNAL not_full : STD_LOGIC; - - TYPE ms_component_tab_type IS ARRAY (0 TO 1, 127 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0); - TYPE spectral_matrix_type IS ARRAY (0 TO 5, 0 TO 5) OF ms_component_tab_type; - - SIGNAL spectral_matrix_data : spectral_matrix_type; - - CONSTANT DIRAC_FREQ : INTEGER := 0; - CONSTANT DIRAC_FREQ2 : INTEGER := 10; - CONSTANT DIRAC_FREQ3 : INTEGER := 127; - CONSTANT FFT_RE : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0020"; - CONSTANT FFT_IM : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0010"; - -BEGIN -- tb - - - clk <= NOT clk AFTER 20 ns; - rstn <= '1' AFTER 100 ns; - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN -- asynchronous reset (active low) - all_data: FOR i IN 127 DOWNTO 0 LOOP - fft_1_re(I) <= (OTHERS => '0'); - fft_1_im(I) <= (OTHERS => '0'); - fft_2_re(I) <= (OTHERS => '0'); - fft_2_im(I) <= (OTHERS => '0'); - fft_3_re(I) <= (OTHERS => '0'); - fft_3_im(I) <= (OTHERS => '0'); - fft_4_re(I) <= (OTHERS => '0'); - fft_4_im(I) <= (OTHERS => '0'); - fft_5_re(I) <= (OTHERS => '0'); - fft_5_im(I) <= (OTHERS => '0'); - END LOOP all_data; - - fft_1_re(DIRAC_FREQ) <= FFT_RE; - fft_1_im(DIRAC_FREQ) <= FFT_IM; - fft_1_re(DIRAC_FREQ) <= FFT_RE; - fft_1_im(DIRAC_FREQ) <= FFT_IM; - fft_2_re(DIRAC_FREQ) <= FFT_RE; - fft_2_im(DIRAC_FREQ) <= FFT_IM; - fft_3_re(DIRAC_FREQ) <= FFT_RE; - fft_3_im(DIRAC_FREQ) <= FFT_IM; - fft_4_re(DIRAC_FREQ) <= FFT_RE; - fft_4_im(DIRAC_FREQ) <= FFT_IM; - fft_5_re(DIRAC_FREQ) <= FFT_RE; - fft_5_im(DIRAC_FREQ) <= FFT_IM; - - --fft_1_re(DIRAC_FREQ2) <= FFT_RE; - --fft_1_im(DIRAC_FREQ2) <= FFT_IM; - --fft_1_re(DIRAC_FREQ2) <= FFT_RE; - --fft_1_im(DIRAC_FREQ2) <= FFT_IM; - --fft_2_re(DIRAC_FREQ2) <= FFT_RE; - --fft_2_im(DIRAC_FREQ2) <= FFT_IM; - --fft_3_re(DIRAC_FREQ2) <= FFT_RE; - --fft_3_im(DIRAC_FREQ2) <= FFT_IM; - --fft_4_re(DIRAC_FREQ2) <= FFT_RE; - --fft_4_im(DIRAC_FREQ2) <= FFT_IM; - --fft_5_re(DIRAC_FREQ2) <= FFT_RE; - --fft_5_im(DIRAC_FREQ2) <= FFT_IM; - - --fft_1_re(DIRAC_FREQ3) <= FFT_RE; - --fft_1_im(DIRAC_FREQ3) <= FFT_IM; - --fft_1_re(DIRAC_FREQ3) <= FFT_RE; - --fft_1_im(DIRAC_FREQ3) <= FFT_IM; - --fft_2_re(DIRAC_FREQ3) <= FFT_RE; - --fft_2_im(DIRAC_FREQ3) <= FFT_IM; - --fft_3_re(DIRAC_FREQ3) <= FFT_RE; - --fft_3_im(DIRAC_FREQ3) <= FFT_IM; - --fft_4_re(DIRAC_FREQ3) <= FFT_RE; - --fft_4_im(DIRAC_FREQ3) <= FFT_IM; - --fft_5_re(DIRAC_FREQ3) <= FFT_RE; - --fft_5_im(DIRAC_FREQ3) <= FFT_IM; - - counter_1 <= 0; - counter_2 <= 0; - counter_3 <= 0; - counter_4 <= 0; - counter_5 <= 0; - --- MEM_IN_SM_wen <= (OTHERS => '1'); --- MEM_OUT_SM_ren <= (OTHERS => '1'); - - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - --IF MEM_IN_SM_locked_out(0) = '0' AND MEM_IN_SM_Full_out(0) = '0' THEN - -- counter_1 <= counter_1 + 1; - -- MEM_IN_SM_wData(15 DOWNTO 0) <= fft_1_re(counter_1); - -- MEM_IN_SM_wData(31 DOWNTO 16) <= fft_1_im(counter_1); - -- MEM_IN_SM_wen(0) <= '0'; - --ELSE - -- counter_1 <= 0; - -- MEM_IN_SM_wData(31 DOWNTO 0) <= (OTHERS => 'X'); - -- MEM_IN_SM_wen(0) <= '1'; - --END IF; - - END IF; - END PROCESS; - - PROCESS - BEGIN -- PROCESS - WAIT FOR 1 us; - not_full <= '0'; - WAIT UNTIL clk = '1' AND clk'EVENT; - loop_DATA_write: FOR I IN 0 TO 127 LOOP - apbi.pwdata <= fft_1_im(I) & fft_1_re(I); - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "000000"; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - WAIT UNTIL clk = '1' AND clk'EVENT; - - apbi.pwdata <= fft_2_im(I) & fft_2_re(I); - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "000001"; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - WAIT UNTIL clk = '1' AND clk'EVENT; - - apbi.pwdata <= fft_3_im(I) & fft_3_re(I); - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "000010"; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - WAIT UNTIL clk = '1' AND clk'EVENT; - - apbi.pwdata <= fft_4_im(I) & fft_4_re(I); - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "000011"; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - WAIT UNTIL clk = '1' AND clk'EVENT; - - apbi.pwdata <= fft_5_im(I) & fft_5_re(I); - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "000100"; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - WAIT UNTIL clk = '1' AND clk'EVENT; - - apbi.pwdata <= X"FFFFFFE0"; - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "000101"; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - WAIT UNTIL clk = '1' AND clk'EVENT; - - apbi.pwrite <= '0'; - END LOOP loop_DATA_write; - - - WAIT UNTIL clk = '1' AND clk'EVENT; - - not_full <= '0'; - - tant_que_not_full: WHILE not_full = '0' LOOP --- apbi.pwdata <= X"FFFFFFE0"; - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "001000"; - apbi.penable <= '1'; - WAIT UNTIL clk = '1' AND clk'EVENT; - not_full <= apbo.prdata(3); - END LOOP tant_que_not_full; - - - all_data_0: FOR I IN 0 TO 127 LOOP - WAIT UNTIL clk = '1' AND clk'EVENT; - --apbi.pwdata <= X"FFFFFFFE"; - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "000110"; - apbi.penable <= '1'; - apbi.pwrite <= '0'; - WAIT UNTIL clk = '1' AND clk'EVENT; - apbi.penable <= '0'; - spectral_matrix_data(0,0)(0,I) <= apbo.prdata; - spectral_matrix_data(0,0)(1,I) <= (OTHERS => '0'); - WAIT UNTIL clk = '1' AND clk'EVENT; - apbi.pwdata <= X"FFFFFFFE"; - apbi.psel(15) <= '1'; - apbi.paddr(7 DOWNTO 2) <= "001000"; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - WAIT UNTIL clk = '1' AND clk'EVENT; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - WAIT UNTIL clk = '1' AND clk'EVENT; - END LOOP all_data_0; - - - - WAIT FOR 100 us; - - REPORT "*** END simulation ***" SEVERITY failure; - WAIT; - - END PROCESS; - - - - - - -------------------------------------------------------------------------------- --- MS ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - - lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb - GENERIC MAP ( - pindex => 15, - paddr => 15, - pmask => 16#fff#) - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - apbi => apbi, - apbo => apbo, - - MEM_IN_SM_wData => MEM_IN_SM_wData, - MEM_IN_SM_wen => MEM_IN_SM_wen, - MEM_IN_SM_Full_out => MEM_IN_SM_Full_out, - MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out, - MEM_IN_SM_locked_out => MEM_IN_SM_locked_out, - - MEM_OUT_SM_ren => MEM_OUT_SM_ren , - MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , - MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad , - MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 , - MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad); - - lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb - GENERIC MAP ( - Mem_use => use_RAM)-- use_RAM use_CEL - PORT MAP ( - clk => clk, - rstn => rstn, - - MEM_IN_SM_wData => MEM_IN_SM_wData, - MEM_IN_SM_wen => MEM_IN_SM_wen, - MEM_IN_SM_Full_out => MEM_IN_SM_Full_out, - MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out, - MEM_IN_SM_locked_out => MEM_IN_SM_locked_out, - - MEM_OUT_SM_Read => MEM_OUT_SM_ren , - MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , - MEM_OUT_SM_Full_pad => MEM_OUT_SM_Full_pad , - MEM_OUT_SM_Full_pad_2 => MEM_OUT_SM_Full_pad_2 , - MEM_OUT_SM_Empty_pad => MEM_OUT_SM_Empty_pad, - - error_input_fifo_write => OPEN, - observation_vector_0 => OPEN, - observation_vector_1 => OPEN); - - ----------------------------------------------------------------------------- -END tb; diff --git a/designs/MINI-LFR_testMS/wave.do b/designs/MINI-LFR_testMS/wave.do deleted file mode 100644 --- a/designs/MINI-LFR_testMS/wave.do +++ /dev/null @@ -1,41 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /testbench_ms/clk -add wave -noupdate /testbench_ms/rstn -add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_wen -add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_wdata -add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_locked_out -add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_full_out -add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_empty_out -add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_read -add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_full_pad_2 -add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_full_pad -add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_empty_pad -add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_data_out -add wave -noupdate -subitemconfig {/testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate /testbench_ms/counter_1 -add wave -noupdate /testbench_ms/counter_2 -add wave -noupdate /testbench_ms/counter_3 -add wave -noupdate /testbench_ms/counter_4 -add wave -noupdate /testbench_ms/counter_5 -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1282611 ps} 0} -configure wave -namecolwidth 564 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {0 ps} {23625 ns} diff --git a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd deleted file mode 100644 --- a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd +++ /dev/null @@ -1,580 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY MINI_LFR_top IS - - PORT ( - clk_50 : IN STD_LOGIC; - clk_49 : IN STD_LOGIC; - reset : IN STD_LOGIC; - --BPs - BP0 : IN STD_LOGIC; - BP1 : IN STD_LOGIC; - --LEDs - LED0 : OUT STD_LOGIC; - LED1 : OUT STD_LOGIC; - LED2 : OUT STD_LOGIC; - --UARTs - TXD1 : IN STD_LOGIC; - RXD1 : OUT STD_LOGIC; - nCTS1 : OUT STD_LOGIC; - nRTS1 : IN STD_LOGIC; - - TXD2 : IN STD_LOGIC; - RXD2 : OUT STD_LOGIC; - nCTS2 : OUT STD_LOGIC; - nDTR2 : IN STD_LOGIC; - nRTS2 : IN STD_LOGIC; - nDCD2 : OUT STD_LOGIC; - - --EXT CONNECTOR - IO0 : INOUT STD_LOGIC; - IO1 : INOUT STD_LOGIC; - IO2 : INOUT STD_LOGIC; - IO3 : INOUT STD_LOGIC; - IO4 : INOUT STD_LOGIC; - IO5 : INOUT STD_LOGIC; - IO6 : INOUT STD_LOGIC; - IO7 : INOUT STD_LOGIC; - IO8 : INOUT STD_LOGIC; - IO9 : INOUT STD_LOGIC; - IO10 : INOUT STD_LOGIC; - IO11 : INOUT STD_LOGIC; - - --SPACE WIRE - SPW_EN : OUT STD_LOGIC; -- 0 => off - SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK - SPW_NOM_SIN : IN STD_LOGIC; - SPW_NOM_DOUT : OUT STD_LOGIC; - SPW_NOM_SOUT : OUT STD_LOGIC; - SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK - SPW_RED_SIN : IN STD_LOGIC; - SPW_RED_DOUT : OUT STD_LOGIC; - SPW_RED_SOUT : OUT STD_LOGIC; - -- MINI LFR ADC INPUTS - ADC_nCS : OUT STD_LOGIC; - ADC_CLK : OUT STD_LOGIC; - ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - - -- SRAM - SRAM_nWE : OUT STD_LOGIC; - SRAM_CE : OUT STD_LOGIC; - SRAM_nOE : OUT STD_LOGIC; - SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END MINI_LFR_top; - - -ARCHITECTURE beh OF MINI_LFR_top IS - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - -- - SIGNAL errorn : STD_LOGIC; - -- UART AHB --------------------------------------------------------------- - SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data - SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data - SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data - -- - SIGNAL I00_s : STD_LOGIC; - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - -- - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; --- SIGNAL clkmn : STD_ULOGIC; --- SIGNAL txclk : STD_ULOGIC; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_nCS_sig : STD_LOGIC; - SIGNAL ADC_CLK_sig : STD_LOGIC; - SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); - - SIGNAL bias_fail_sw_sig : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - - PROCESS(clk_50) - BEGIN - IF clk_50'EVENT AND clk_50 = '1' THEN - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - - PROCESS(clk_49) - BEGIN - IF clk_49'EVENT AND clk_49 = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - LED0 <= '0'; - LED1 <= '0'; - LED2 <= '0'; - --IO1 <= '0'; - --IO2 <= '1'; - --IO3 <= '0'; - --IO4 <= '0'; - --IO5 <= '0'; - --IO6 <= '0'; - --IO7 <= '0'; - --IO8 <= '0'; - --IO9 <= '0'; - --IO10 <= '0'; - --IO11 <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - LED0 <= '0'; - LED1 <= '1'; - LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; - --IO1 <= '1'; - --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - --IO3 <= ADC_SDO(0); - --IO4 <= ADC_SDO(1); - --IO5 <= ADC_SDO(2); - --IO6 <= ADC_SDO(3); - --IO7 <= ADC_SDO(4); - --IO8 <= ADC_SDO(5); - --IO9 <= ADC_SDO(6); - --IO10 <= ADC_SDO(7); - --IO11 <= ; - END IF; - END PROCESS; - - PROCESS (clk_24, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - I00_s <= '0'; - ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge - I00_s <= NOT I00_s; - END IF; - END PROCESS; --- IO0 <= I00_s; - - --UARTs - nCTS1 <= '1'; - nCTS2 <= '1'; - nDCD2 <= '1'; - - --EXT CONNECTOR - - --SPACE WIRE - - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) - PORT MAP ( - clk => clk_25, - reset => reset, - errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_time_management_1 : apb_lfr_time_management - GENERIC MAP ( - pindex => 6, - paddr => 6, - pmask => 16#fff#, - pirq => 12, - nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 - PORT MAP ( - clk25MHz => clk_25, - clk49_152MHz => clk_24, -- 49.152MHz/2 - resetn => reset, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - coarse_time => coarse_time, - fine_time => fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - SPW_EN <= '1'; - - spw_clk <= clk_50_s; - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DIN, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SIN, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_DOUT, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_NOM_SOUT, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_SIN, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (SPW_RED_DIN, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_DOUT, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (SPW_RED_SOUT, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(reset, clk_25, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => use_RAM, - nb_data_by_buffer_size => 32, - nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"000010") -- aa.bb.cc version - PORT MAP ( - clk => clk_25, - rstn => reset, - sample_B => sample(2 DOWNTO 0), - sample_E => sample(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw_sig, - observation_reg => observation_reg); - - top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 - GENERIC MAP( - ChannelCount => 8, - SampleNbBits => 14, - ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 - ncycle_cnv => 249) -- 49 152 000 / 98304 /2 - PORT MAP ( - -- CONV - cnv_clk => clk_24, - cnv_rstn => reset, - cnv => ADC_nCS_sig, - -- DATA - clk => clk_25, - rstn => reset, - sck => ADC_CLK_sig, - sdo => ADC_SDO_sig, - -- SAMPLE - sample => sample, - sample_val => sample_val); - - --IO10 <= ADC_SDO_sig(5); - --IO9 <= ADC_SDO_sig(4); - --IO8 <= ADC_SDO_sig(3); - - ADC_nCS <= ADC_nCS_sig; - ADC_CLK <= ADC_CLK_sig; - ADC_SDO_sig <= ADC_SDO; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) - PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); - - --pio_pad_0 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); - --pio_pad_1 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); - --pio_pad_2 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); - --pio_pad_3 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); - --pio_pad_4 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); - --pio_pad_5 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); - --pio_pad_6 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); - --pio_pad_7 : iopad - -- GENERIC MAP (tech => CFG_PADTECH) - -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); - - PROCESS (clk_25, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - IO0 <= '0'; - IO1 <= '0'; - IO2 <= '0'; - IO3 <= '0'; - IO4 <= '0'; - IO5 <= '0'; - IO6 <= '0'; - IO7 <= '0'; - IO8 <= '0'; - IO9 <= '0'; - IO10 <= '0'; - IO11 <= '0'; - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - CASE gpioo.dout(1 DOWNTO 0) IS - WHEN "00" => - IO0 <= observation_reg(0 ); - IO1 <= observation_reg(1 ); - IO2 <= observation_reg(2 ); - IO3 <= observation_reg(3 ); - IO4 <= observation_reg(4 ); - IO5 <= observation_reg(5 ); - IO6 <= observation_reg(6 ); - IO7 <= observation_reg(7 ); - IO8 <= observation_reg(8 ); - IO9 <= observation_reg(9 ); - IO10 <= observation_reg(10); - IO11 <= observation_reg(11); - WHEN "01" => - IO0 <= observation_reg(0 + 12); - IO1 <= observation_reg(1 + 12); - IO2 <= observation_reg(2 + 12); - IO3 <= observation_reg(3 + 12); - IO4 <= observation_reg(4 + 12); - IO5 <= observation_reg(5 + 12); - IO6 <= observation_reg(6 + 12); - IO7 <= observation_reg(7 + 12); - IO8 <= observation_reg(8 + 12); - IO9 <= observation_reg(9 + 12); - IO10 <= observation_reg(10 + 12); - IO11 <= observation_reg(11 + 12); - WHEN "10" => - IO0 <= observation_reg(0 + 12 + 12); - IO1 <= observation_reg(1 + 12 + 12); - IO2 <= observation_reg(2 + 12 + 12); - IO3 <= observation_reg(3 + 12 + 12); - IO4 <= observation_reg(4 + 12 + 12); - IO5 <= observation_reg(5 + 12 + 12); - IO6 <= observation_reg(6 + 12 + 12); - IO7 <= observation_reg(7 + 12 + 12); - IO8 <= '0'; - IO9 <= '0'; - IO10 <= '0'; - IO11 <= '0'; - WHEN "11" => - IO0 <= '0'; - IO1 <= '0'; - IO2 <= '0'; - IO3 <= '0'; - IO4 <= '0'; - IO5 <= '0'; - IO6 <= '0'; - IO7 <= '0'; - IO8 <= '0'; - IO9 <= '0'; - IO10 <= '0'; - IO11 <= '0'; - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS; - -END beh; \ No newline at end of file diff --git a/designs/MINI-LFR_waveformPicker/Makefile b/designs/MINI-LFR_waveformPicker/Makefile deleted file mode 100644 --- a/designs/MINI-LFR_waveformPicker/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=MINI_LFR_top -BOARD=MINI-LFR -include $(VHDLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES= MINI_LFR_top.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./dsp/lpp_fft \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_demux \ - ./lpp_matrix \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_Header \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP =lpp_lfr_ms.vhd \ - i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/.config b/designs/Projet-LeonLFR-A3P3K-Sheldon/.config deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/971A_lqfp.bsd b/designs/Projet-LeonLFR-A3P3K-Sheldon/971A_lqfp.bsd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/971A_lqfp.bsd +++ /dev/null @@ -1,262 +0,0 @@ --- --- Device: LXT971A --- Package: LQFP --- File Name: 971A_lqfp.bsdl --- --- Revision History --- 1.0 - Tim Jackson (4/29/2002) --- Legacy file 971Alqfp.txt renamed to 971A_lqfp.bsdl. --- Updated attribute IDCODE_REGISTER to handle revision ids 1 --- and 2 and their appropriate jedec continuation codes. --- Changed PWRDWN to a compliance enable and added a design --- warning to that effect. --- --- Notes --- This file has successfully compiled on the Agilent Technologies 3070 --- BSDL compiler. --- --- Disclaimer --- Intel Corporation ("Intel") hereby grants the user of this BSDL file --- ("User") a non-exclusive, nontransferable license to use the file --- under the following terms. User may only to use the BSDL file and --- is not granted rights to sell, copy (except as needed to run the BSDL --- file), rent, lease or sub-license the BSDL file in whole or in part, --- or in modified form to anyone. User may modify the BSDL file to suit --- its specific applications, but rights to derivative works and such --- modifications shall belong to Intel. This BSDL file is provided on an --- "AS IS" basis and Intel makes absolutely no warranty with respect to --- the information contained herein. INTEL DISCLAIMS AND USER WAIVES --- ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF --- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY --- OF NON-INFRINGEMENT OF THE INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD --- PARTY. THE ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH USER. --- ACCORDINGLY, IN NO EVENT SHALL INTEL BE LIABLE FOR ANY DIRECT OR --- INDIRECT DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING, WITHOUT --- LIMITATION, LOST PROFITS, BUSINESS INTERRUPTION, OR LOST INFORMATION) --- ARISING OUT OF THE USE OF OR INABILITY TO USE THE FILE, EVEN IF INTEL --- HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. --- --- This file is the legal property of Copyright (c) 2002, Intel --- Corporation. --- - -entity shark is - generic (PHYSICAL_PIN_MAP : string := "LQFP64"); - - port ( - GND : linkage bit_vector (1 to 7); - VCCIO : linkage bit_vector (1 to 2); - VCCA : linkage bit_vector (1 to 2); - VCCD : linkage bit ; - NC : linkage bit_vector (1 to 3); - XI : linkage bit ; - XO : linkage bit ; - MDDIS : in bit ; - Reset : in bit ; - TXSLEW0: in bit ; - TXSLEW1: in bit ; - ADDR0 : in bit ; - ADDR1 : in bit ; - ADDR2 : in bit ; - ADDR3 : in bit ; - ADDR4 : in bit ; - RBIAS : linkage bit ; - TPFOP : linkage bit ; - TPFON : linkage bit ; - TPFIP : linkage bit ; - TPFIN : linkage bit ; - SD_TP : in bit ; - TDI : in bit ; - TDO : out bit ; - TMS : in bit ; - TCK : in bit ; - TRST : in bit ; - SLEEP : in bit ; - PAUSE : in bit ; - TEST0 : in bit ; - TEST1 : in bit ; - LEDCFG2: inout bit ; - LEDCFG1: inout bit ; - LEDCFG0: inout bit ; - PWRDWN : in bit ; - MDIO : inout bit ; - MDC : in bit ; - RXD3 : out bit ; - RXD2 : out bit ; - RXD1 : out bit ; - RXD0 : out bit ; - RX_DV : out bit ; - RX_CLK : out bit ; - RX_ER : out bit ; - TX_ER : in bit ; - TX_CLK : out bit ; - TX_EN : in bit ; - TXD0 : in bit ; - TXD1 : in bit ; - TXD2 : in bit ; - TXD3 : in bit ; - COL : out bit ; - CRS : out bit ; - MDINT : out bit - - ); - - use STD_1149_1_1994.all; - use LXT971A_BSCAN.all; - - attribute COMPONENT_CONFORMANCE of shark: entity is "STD_1149_1_1993"; - - -- Pin mappings - - attribute PIN_MAP of shark: entity is PHYSICAL_PIN_MAP; - - constant LQFP64: PIN_MAP_STRING:= - "GND : (7,11,18,25,41,50,61),"& - "VCCIO : (8,40) ,"& - "VCCA : (21,22) ,"& - "VCCD : 51 ,"& - "NC : (9,10,44) ,"& - "XI : 1 ,"& - "XO : 2 ,"& - "MDDIS : 3 ,"& - "Reset : 4 ,"& - "TXSLEW0: 5 ,"& - "TXSLEW1: 6 ,"& - "ADDR0 : 12 ,"& - "ADDR1 : 13 ,"& - "ADDR2 : 14 ,"& - "ADDR3 : 15 ,"& - "ADDR4 : 16 ,"& - "RBIAS : 17 ,"& - "TPFOP : 19 ,"& - "TPFON : 20 ,"& - "TPFIP : 23 ,"& - "TPFIN : 24 ,"& - "SD_TP : 26 ,"& - "TDI : 27 ,"& - "TDO : 28 ,"& - "TMS : 29 ,"& - "TCK : 30 ,"& - "TRST : 31 ,"& - "SLEEP : 32 ,"& - "PAUSE : 33 ,"& - "TEST0 : 34 ,"& - "TEST1 : 35 ,"& - "LEDCFG2: 36 ,"& - "LEDCFG1: 37 ,"& - "LEDCFG0: 38 ,"& - "PWRDWN : 39 ,"& - "MDIO : 42 ,"& - "MDC : 43 ,"& - "RXD3 : 45 ,"& - "RXD2 : 46 ,"& - "RXD1 : 47 ,"& - "RXD0 : 48 ,"& - "RX_DV : 49 ,"& - "RX_CLK : 52 ,"& - "RX_ER : 53 ,"& - "TX_ER : 54 ,"& - "TX_CLK : 55 ,"& - "TX_EN : 56 ,"& - "TXD0 : 57 ,"& - "TXD1 : 58 ,"& - "TXD2 : 59 ,"& - "TXD3 : 60 ,"& - "COL : 62 ,"& - "CRS : 63 ,"& - "MDINT : 64 "; - - - - -- IEEE 1149.1 pin definition - attribute TAP_SCAN_RESET of TRST : signal is true; - attribute TAP_SCAN_IN of TDI : signal is true; - attribute TAP_SCAN_MODE of TMS : signal is true; - attribute TAP_SCAN_OUT of TDO : signal is true; - attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); - - -- IEEE 1149.1 compliance enable - attribute COMPLIANCE_PATTERNS of shark: entity is - "(PWRDWN) (0)"; - - -- IEEE 1149.1 definition for LV Software TAP - attribute INSTRUCTION_LENGTH of shark: entity is 16; - - attribute INSTRUCTION_OPCODE of shark: entity is - "IDCODE (1111111111111110)," & - "BYPASS (1111111111111111)," & - "EXTEST (0000000000000000,1111111111101000)," & - "SAMPLE (1111111111111000)," & - "HIGHZ (1111111111001111)," & - "CLAMP (1111111111101111)" ; - attribute INSTRUCTION_CAPTURE of shark: entity is "xxxxxxxxxxxxxx01"; - - attribute IDCODE_REGISTER of shark: entity is - "0001" & -- revision id 1 - "0000001111001011" & -- part number - "11101111110" & -- manufacturer's ID - "1," & -- required by 1149.1 - "0010" & -- revision id 2 - "0000001111001011" & -- part number - "00001111110" & -- manufacturer's ID - "1"; -- required by 1149.1 - - attribute REGISTER_ACCESS of shark: entity is - "BYPASS (HIGHZ, CLAMP) " ; - - --Boundary scan definition - attribute BOUNDARY_LENGTH of shark: entity is 40; - - attribute BOUNDARY_REGISTER of shark: entity is - -- num cell port function safe [ccell disval rslt] - " 0 (BC_2 , MDDIS , input , X ) ,"& - " 1 (BC_2 , Reset , input , X ) ,"& - " 2 (BC_2 , TXSLEW0 , input , X ) ,"& - " 3 (BC_2 , TXSLEW1 , input , X ) ,"& - " 4 (BC_2 , ADDR0 , input , X ) ,"& - " 5 (BC_2 , ADDR1 , input , X ) ,"& - " 6 (BC_2 , ADDR2 , input , X ) ,"& - " 7 (BC_2 , ADDR3 , input , X ) ,"& - " 8 (BC_2 , ADDR4 , input , X ) ,"& - " 9 (BC_2 , SD_TP , input , X ) ,"& - " 10 (BC_2 , SLEEP , input , X ) ,"& - " 11 (BC_2 , PAUSE , input , X ) ,"& - " 12 (BC_2 , TEST0 , input , X ) ,"& - " 13 (BC_2 , TEST1 , input , X ) ,"& - " 14 (BC_2 , * , control , 1 ) ,"& - " 15 (LV_BC_7 , LEDCFG2 , bidir , X , 14 , 1 , Z ),"& - " 16 (LV_BC_7 , LEDCFG1 , bidir , X , 14 , 1 , Z ),"& - " 17 (LV_BC_7 , LEDCFG0 , bidir , X , 14 , 1 , Z ),"& - " 18 (BC_2 , * , internal , 0 ) ,"& - " 19 (LV_BC_7 , MDIO , bidir , X , 14 , 1 , Z ),"& - " 20 (BC_2 , MDC , input , X ) ,"& - " 21 (BC_2 , * , internal , X ) ,"& - " 22 (BC_2 , RXD3 , output3 , X , 14 , 1 , Z ),"& - " 23 (BC_2 , RXD2 , output3 , X , 14 , 1 , Z ),"& - " 24 (BC_2 , RXD1 , output3 , X , 14 , 1 , Z ),"& - " 25 (BC_2 , RXD0 , output3 , X , 14 , 1 , Z ),"& - " 26 (BC_2 , RX_DV , output3 , X , 14 , 1 , Z ),"& - " 27 (BC_2 , RX_CLK , output3 , X , 14 , 1 , Z ),"& - " 28 (BC_2 , RX_ER , output3 , X , 14 , 1 , Z ),"& - " 29 (BC_2 , TX_ER , input , X ) ,"& - " 30 (BC_2 , TX_CLK , output3 , X , 14 , 1 , Z ),"& - " 31 (BC_2 , TX_EN , input , X ) ,"& - " 32 (BC_2 , TXD0 , input , X ) ,"& - " 33 (BC_2 , TXD1 , input , X ) ,"& - " 34 (BC_2 , TXD2 , input , X ) ,"& - " 35 (BC_2 , TXD3 , input , X ) ,"& - " 36 (BC_2 , * , internal , 0 ) ,"& - " 37 (BC_2 , COL , output3 , X , 14 , 1 , Z ),"& - " 38 (BC_2 , CRS , output3 , X , 14 , 1 , Z ),"& - " 39 (BC_2 , MDINT , output3 , X , 14 , 1 , Z ) "; - --- 1149.1 Design Warnings - attribute DESIGN_WARNING of shark: entity is - "PWRDWN pin should be kept low to allow proper operation" & - "of TAP circuitry. There is a compliance enable on this" & - "pin to force the safe value. The boundary scan cell" & - "associated with the PWRDWN pin has been changed to an" & - "internal pin. It is cell number 18 in the boundary scan" & - "register description and has a safe value of 0 specified"; - -end shark; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/Makefile b/designs/Projet-LeonLFR-A3P3K-Sheldon/Makefile deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -#GRLIB=../.. -TOP=top -BOARD=Projet-LeonLFR-A3P3K-Sheldon -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSIMFILES=testbench.vhd -SIMTOP=testbench -SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/Projet-LeonLFR-A3P3K-Sheldon.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3 -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 - -FILESKIP = i2cmst.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/TestBench.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon/TestBench.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/TestBench.vhd +++ /dev/null @@ -1,295 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE - - -LIBRARY esa; -USE esa.memoryctrl.ALL; ---USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -use lpp.lpp_demux.all; -use lpp.lpp_dma_pkg.all; -use lpp.lpp_Header.all; -use lpp.lpp_fft.all; -use lpp.lpp_matrix.all; - - -ENTITY TestBench IS -END; - -ARCHITECTURE Behavioral OF TestBench IS - - - component TestModule_ADS7886 IS - GENERIC ( - freq : INTEGER ; - amplitude : INTEGER ; - impulsion : INTEGER - ); - PORT ( - -- CONV -- - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - - -- DATA -- - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC - ); - END component; - - SIGNAL clk49_152MHz : STD_LOGIC := '0'; - SIGNAL clkm : STD_LOGIC := '0'; - SIGNAL rstn : STD_LOGIC := '0'; - SIGNAL coarse_time_0 : STD_LOGIC := '0'; - --- -- ADC interface --- SIGNAL bias_fail_sw : STD_LOGIC; -- OUT --- SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT --- SIGNAL ADC_smpclk : STD_LOGIC; -- OUT --- SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN - - -- - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - --- -- internal --- SIGNAL sample : Samples14v(7 DOWNTO 0); --- SIGNAL sample_val : STD_LOGIC; - --- ACQ -signal CNV_CH1 : STD_LOGIC; -signal SCK_CH1 : STD_LOGIC; -signal SDO_CH1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -signal Bias_Fails : std_logic; -signal sample_val : STD_LOGIC; -signal sample : Samples(8-1 DOWNTO 0); - -signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- FIFOs -signal FifoF0_Empty : std_logic_vector(4 downto 0); -signal FifoF0_Data : std_logic_vector(79 downto 0); -signal FifoF1_Empty : std_logic_vector(4 downto 0); -signal FifoF1_Data : std_logic_vector(79 downto 0); -signal FifoF3_Empty : std_logic_vector(4 downto 0); -signal FifoF3_Data : std_logic_vector(79 downto 0); -signal FifoINT_Full : std_logic_vector(4 downto 0); -signal FifoINT_Data : std_logic_vector(79 downto 0); -signal FifoOUT_Full : std_logic_vector(1 downto 0); -signal FifoOUT_Empty : std_logic_vector(1 downto 0); -signal FifoOUT_Data : std_logic_vector(63 downto 0); --- MATRICE SPECTRALE -signal SM_FlagError : std_logic; -signal SM_Pong : std_logic; -signal SM_Wen : std_logic; -signal SM_Read : std_logic_vector(4 downto 0); -signal SM_Write : std_logic_vector(1 downto 0); -signal SM_ReUse : std_logic_vector(4 downto 0); -signal SM_Param : std_logic_vector(3 downto 0); -signal SM_Data : std_logic_vector(63 downto 0); --- FFT -signal FFT_Load : std_logic; -signal FFT_Read : std_logic_vector(4 downto 0); -signal FFT_Write : std_logic_vector(4 downto 0); -signal FFT_ReUse : std_logic_vector(4 downto 0); -signal FFT_Data : std_logic_vector(79 downto 0); --- DEMUX -signal DMUX_Read : std_logic_vector(14 downto 0); -signal DMUX_Empty : std_logic_vector(4 downto 0); -signal DMUX_Data : std_logic_vector(79 downto 0); -signal DMUX_WorkFreq : std_logic_vector(1 downto 0); --- Header -signal Head_Read : std_logic_vector(1 downto 0); -signal Head_Data : std_logic_vector(31 downto 0); -signal Head_Empty : std_logic; -signal Head_Header : std_logic_vector(31 DOWNTO 0); -signal Head_Valid : std_logic; -signal Head_Val : std_logic; ---DMA -signal DMA_Read : std_logic; -signal DMA_ack : std_logic; -signal AHB_Master_In : AHB_Mst_In_Type; -signal AHB_Master_Out : AHB_Mst_Out_Type; - - -BEGIN - - ----------------------------------------------------------------------------- - --- MODULE_RHF1401: FOR I IN 0 TO 7 GENERATE --- TestModule_RHF1401_1: TestModule_RHF1401 --- GENERIC MAP ( --- freq => 24*(I+1), --- amplitude => 8000/(I+1), --- impulsion => 0) --- PORT MAP ( --- ADC_smpclk => ADC_smpclk, --- ADC_OEB_bar => ADC_OEB_bar_CH(I), --- ADC_data => ADC_data); --- END GENERATE MODULE_RHF1401; - -MODULE_ADS7886: FOR I IN 0 TO 7 GENERATE -TestModule_ADS7886_0 : TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 8000/(I+1), - impulsion => 0) - PORT MAP( - -- CONV -- - cnv_run => '1', - cnv => CNV_CH1, - -- DATA -- - sck => SCK_CH1, - sdo => SDO_CH1(I)); - END GENERATE MODULE_ADS7886; - - - ----------------------------------------------------------------------------- - - clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz - clkm <= NOT clkm AFTER 20 ns; -- 25 MHz - coarse_time_0 <= NOT coarse_time_0 AFTER 100 ms; - - ----------------------------------------------------------------------------- - -- waveform generation - WaveGen_Proc : PROCESS - BEGIN - WAIT UNTIL clkm = '1'; - apbi <= apb_slv_in_none; - rstn <= '0'; --- cnv_rstn <= '0'; --- run_cnv <= '0'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - rstn <= '1'; --- cnv_rstn <= '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - - WAIT; - - END PROCESS WaveGen_Proc; - - - ahbmi.HGRANT(2) <= '1'; - ahbmi.HREADY <= '1'; - ahbmi.HRESP <= HRESP_OKAY; - - - -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --- DUT ------------------------------------------------------------------------ -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - ACQ0 : lpp_top_acq - port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk49_152MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3); - - Bias_Fails <= '0'; ---- FIFO IN ------------------------------------------------------------- - - Memf0 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); - - Memf1 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); - - Memf3 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); - ---- DEMUX ------------------------------------------------------------- - - DMUX0 : DEMUX - generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data); - ---- FFT ------------------------------------------------------------- - - FFT0 : FFT - generic map(Data_sz => 16,NbData => 256) - port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); - ------ LINK MEMORY ------------------------------------------------------- - - MemInt : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1') - port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); - ------ MATRICE SPECTRALE ---------------------5 FIFO Input--------------- - - SM0 : MatriceSpectrale - generic map(Input_SZ => 16,Result_SZ => 32) - port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); - - MemOut : lppFIFOxN - generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty); - ------ Header ------------------------------------------------------- - - Head0 : HeaderBuilder - generic map(Data_sz => 32) - port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); - ------ DMA ------------------------------------------------------- - - DMA0 : lpp_dma - generic map( - tech =>inferred, - hindex => 2, - pindex => 9, - paddr => 9, - pmask => 16#fff#, - pirq => 0) - port map(clkm,rstn,apbi,apbo(9),AHB_Master_In,AHB_Master_Out,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); - -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - -END Behavioral; \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/ahbrom.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon/ahbrom.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/ahbrom.vhd +++ /dev/null @@ -1,232 +0,0 @@ - ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2009 Aeroflex Gaisler ----------------------------------------------------------------------------- --- Entity: ahbrom --- File: ahbrom.vhd --- Author: Jiri Gaisler - Gaisler Research --- Description: AHB rom. 0/1-waitstate read ----------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; - -entity ahbrom is - generic ( - hindex : integer := 0; - haddr : integer := 0; - hmask : integer := 16#fff#; - pipe : integer := 0; - tech : integer := 0; - kbytes : integer := 1); - port ( - rst : in std_ulogic; - clk : in std_ulogic; - ahbsi : in ahb_slv_in_type; - ahbso : out ahb_slv_out_type - ); -end; - -architecture rtl of ahbrom is -constant abits : integer := 10; -constant bytes : integer := 560; - -constant hconfig : ahb_config_type := ( - 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), - 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); - -signal romdata : std_logic_vector(31 downto 0); -signal addr : std_logic_vector(abits-1 downto 2); -signal hsel, hready : std_ulogic; - -begin - - ahbso.hresp <= "00"; - ahbso.hsplit <= (others => '0'); - ahbso.hirq <= (others => '0'); - ahbso.hcache <= '1'; - ahbso.hconfig <= hconfig; - ahbso.hindex <= hindex; - - reg : process (clk) - begin - if rising_edge(clk) then - addr <= ahbsi.haddr(abits-1 downto 2); - end if; - end process; - - p0 : if pipe = 0 generate - ahbso.hrdata <= ahbdrivedata(romdata); - ahbso.hready <= '1'; - end generate; - - p1 : if pipe = 1 generate - reg2 : process (clk) - begin - if rising_edge(clk) then - hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1); - hready <= ahbsi.hready; - ahbso.hready <= (not rst) or (hsel and hready) or - (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready); - ahbso.hrdata <= ahbdrivedata(romdata); - end if; - end process; - end generate; - - comb : process (addr) - begin - case conv_integer(addr) is - when 16#00000# => romdata <= X"81D82000"; - when 16#00001# => romdata <= X"03000004"; - when 16#00002# => romdata <= X"821060E0"; - when 16#00003# => romdata <= X"81884000"; - when 16#00004# => romdata <= X"81900000"; - when 16#00005# => romdata <= X"81980000"; - when 16#00006# => romdata <= X"81800000"; - when 16#00007# => romdata <= X"A1800000"; - when 16#00008# => romdata <= X"01000000"; - when 16#00009# => romdata <= X"03002040"; - when 16#0000A# => romdata <= X"8210600F"; - when 16#0000B# => romdata <= X"C2A00040"; - when 16#0000C# => romdata <= X"84100000"; - when 16#0000D# => romdata <= X"01000000"; - when 16#0000E# => romdata <= X"01000000"; - when 16#0000F# => romdata <= X"01000000"; - when 16#00010# => romdata <= X"01000000"; - when 16#00011# => romdata <= X"01000000"; - when 16#00012# => romdata <= X"80108002"; - when 16#00013# => romdata <= X"01000000"; - when 16#00014# => romdata <= X"01000000"; - when 16#00015# => romdata <= X"01000000"; - when 16#00016# => romdata <= X"01000000"; - when 16#00017# => romdata <= X"01000000"; - when 16#00018# => romdata <= X"87444000"; - when 16#00019# => romdata <= X"8608E01F"; - when 16#0001A# => romdata <= X"88100000"; - when 16#0001B# => romdata <= X"8A100000"; - when 16#0001C# => romdata <= X"8C100000"; - when 16#0001D# => romdata <= X"8E100000"; - when 16#0001E# => romdata <= X"A0100000"; - when 16#0001F# => romdata <= X"A2100000"; - when 16#00020# => romdata <= X"A4100000"; - when 16#00021# => romdata <= X"A6100000"; - when 16#00022# => romdata <= X"A8100000"; - when 16#00023# => romdata <= X"AA100000"; - when 16#00024# => romdata <= X"AC100000"; - when 16#00025# => romdata <= X"AE100000"; - when 16#00026# => romdata <= X"90100000"; - when 16#00027# => romdata <= X"92100000"; - when 16#00028# => romdata <= X"94100000"; - when 16#00029# => romdata <= X"96100000"; - when 16#0002A# => romdata <= X"98100000"; - when 16#0002B# => romdata <= X"9A100000"; - when 16#0002C# => romdata <= X"9C100000"; - when 16#0002D# => romdata <= X"9E100000"; - when 16#0002E# => romdata <= X"86A0E001"; - when 16#0002F# => romdata <= X"16BFFFEF"; - when 16#00030# => romdata <= X"81E00000"; - when 16#00031# => romdata <= X"82102002"; - when 16#00032# => romdata <= X"81904000"; - when 16#00033# => romdata <= X"03000004"; - when 16#00034# => romdata <= X"821060E0"; - when 16#00035# => romdata <= X"81884000"; - when 16#00036# => romdata <= X"01000000"; - when 16#00037# => romdata <= X"01000000"; - when 16#00038# => romdata <= X"01000000"; - when 16#00039# => romdata <= X"83480000"; - when 16#0003A# => romdata <= X"8330600C"; - when 16#0003B# => romdata <= X"80886001"; - when 16#0003C# => romdata <= X"02800024"; - when 16#0003D# => romdata <= X"01000000"; - when 16#0003E# => romdata <= X"07000000"; - when 16#0003F# => romdata <= X"8610E178"; - when 16#00040# => romdata <= X"C108C000"; - when 16#00041# => romdata <= X"C118C000"; - when 16#00042# => romdata <= X"C518C000"; - when 16#00043# => romdata <= X"C918C000"; - when 16#00044# => romdata <= X"CD18C000"; - when 16#00045# => romdata <= X"D118C000"; - when 16#00046# => romdata <= X"D518C000"; - when 16#00047# => romdata <= X"D918C000"; - when 16#00048# => romdata <= X"DD18C000"; - when 16#00049# => romdata <= X"E118C000"; - when 16#0004A# => romdata <= X"E518C000"; - when 16#0004B# => romdata <= X"E918C000"; - when 16#0004C# => romdata <= X"ED18C000"; - when 16#0004D# => romdata <= X"F118C000"; - when 16#0004E# => romdata <= X"F518C000"; - when 16#0004F# => romdata <= X"F918C000"; - when 16#00050# => romdata <= X"FD18C000"; - when 16#00051# => romdata <= X"01000000"; - when 16#00052# => romdata <= X"01000000"; - when 16#00053# => romdata <= X"01000000"; - when 16#00054# => romdata <= X"01000000"; - when 16#00055# => romdata <= X"01000000"; - when 16#00056# => romdata <= X"89A00842"; - when 16#00057# => romdata <= X"01000000"; - when 16#00058# => romdata <= X"01000000"; - when 16#00059# => romdata <= X"01000000"; - when 16#0005A# => romdata <= X"01000000"; - when 16#0005B# => romdata <= X"10800005"; - when 16#0005C# => romdata <= X"01000000"; - when 16#0005D# => romdata <= X"01000000"; - when 16#0005E# => romdata <= X"00000000"; - when 16#0005F# => romdata <= X"00000000"; - when 16#00060# => romdata <= X"87444000"; - when 16#00061# => romdata <= X"8730E01C"; - when 16#00062# => romdata <= X"8688E00F"; - when 16#00063# => romdata <= X"12800016"; - when 16#00064# => romdata <= X"03200000"; - when 16#00065# => romdata <= X"05040E00"; - when 16#00066# => romdata <= X"8410A233"; - when 16#00067# => romdata <= X"C4204000"; - when 16#00068# => romdata <= X"0539A89B"; - when 16#00069# => romdata <= X"8410A260"; - when 16#0006A# => romdata <= X"C4206004"; - when 16#0006B# => romdata <= X"050003FC"; - when 16#0006C# => romdata <= X"C4206008"; - when 16#0006D# => romdata <= X"82103860"; - when 16#0006E# => romdata <= X"C4004000"; - when 16#0006F# => romdata <= X"8530A00C"; - when 16#00070# => romdata <= X"03000004"; - when 16#00071# => romdata <= X"82106009"; - when 16#00072# => romdata <= X"80A04002"; - when 16#00073# => romdata <= X"12800006"; - when 16#00074# => romdata <= X"033FFC00"; - when 16#00075# => romdata <= X"82106100"; - when 16#00076# => romdata <= X"0539A81B"; - when 16#00077# => romdata <= X"8410A260"; - when 16#00078# => romdata <= X"C4204000"; - when 16#00079# => romdata <= X"05000080"; - when 16#0007A# => romdata <= X"82100000"; - when 16#0007B# => romdata <= X"80A0E000"; - when 16#0007C# => romdata <= X"02800005"; - when 16#0007D# => romdata <= X"01000000"; - when 16#0007E# => romdata <= X"82004002"; - when 16#0007F# => romdata <= X"10BFFFFC"; - when 16#00080# => romdata <= X"8620E001"; - when 16#00081# => romdata <= X"3D1003FF"; - when 16#00082# => romdata <= X"BC17A3E0"; - when 16#00083# => romdata <= X"BC278001"; - when 16#00084# => romdata <= X"9C27A060"; - when 16#00085# => romdata <= X"03100000"; - when 16#00086# => romdata <= X"81C04000"; - when 16#00087# => romdata <= X"01000000"; - when 16#00088# => romdata <= X"00000000"; - when 16#00089# => romdata <= X"00000000"; - when 16#0008A# => romdata <= X"00000000"; - when 16#0008B# => romdata <= X"00000000"; - when 16#0008C# => romdata <= X"00000000"; - when others => romdata <= (others => '-'); - end case; - end process; - -- pragma translate_off - bootmsg : report_version - generic map ("ahbrom" & tost(hindex) & - ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" ); - -- pragma translate_on - end; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18.dc b/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18.dc deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18.dc +++ /dev/null @@ -1,102 +0,0 @@ -/*******************************************/ -/* Script to compile leon with synopsys DC */ -/* Jiri Gaisler, Gaisler Research, 2004 */ -/*******************************************/ - -search_path = {"." "/usr/local/synopsys/libraries/syn" "c:/Synopsys/libraries/syn"} -target_library = "SClib-max+ind.db" -link_library = "SClib-max+ind.db IO33lib-max+ind.db atc18mem.db PCIlib-max+ind.db" -link_library = "*" + link_library -symbol_library = "IO33lib-max+ind.sdb SClib-max+ind.sdb generic.sdb" -allow_newer_db_files = "true"; - -/* constraints - tailor to your own technology. An average 0.35 std-cell tech - should give you 80 - 100 MHz depending on ram access time. A 0.25 tech - should run at +150 MHz. Frequency in MHz, delays in ns ... */ - -frequency = 200 -clock_skew = 0.10 -input_setup = 2.0 -output_delay = 4.0 - -/* don't touch anything from here unless you know what you are doing */ - -include leon3mp.dc -include atc18cond.dc - -ungroup find(cell, "*pad*") -flatten - -group find(cell, {"sr*", "sdc", "apb*", "uart*", "timer*", "irq*" \ - "ahb*", "dsu0", "rst0", "dcom*" }) -design_name amod \ - -cell_name amod0 - -current_instance u0_0/p0 -ungroup -all -flatten -current_instance ../rf0 -ungroup -all -flatten -current_instance ../cmem0 -ungroup -all -flatten -current_instance ../../amod0 -ungroup -all -flatten -current_instance .. - -peri = 1000.0 / frequency -input_delay = peri - input_setup -tdelay = output_delay + 2 -create_clock -name "clk" -period peri -waveform { 0.0, peri / 2.0 } { "clk" } -set_wire_load_mode segmented - -set_clock_skew -plus_uncertainty clock_skew "clk" -set_clock_skew -minus_uncertainty clock_skew "clk" - -/* -set_input_delay input_delay -clock clk { \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" "brdyn" "bexcn" } - -set_max_delay tdelay -to { "errorn" "wdogn" \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" } - -set_max_delay output_delay -to { \ - "writen" "romsn[1]" "romsn[0]" "read" "oen" \ - "iosn" "rwen[3]" "rwen[2]" "rwen[1]" "rwen[0]" "ramsn[3]" \ - "ramsn[2]" "ramsn[1]" "ramsn[0]" \ - "ramoen[3]" "ramoen[2]" "ramoen[1]" "ramoen[0]" \ - "sdcsn[1]" "sdcsn[0]" "sdwen" "sdrasn" "sdcasn" \ - "sddqm[3]" "sddqm[2]" "sddqm[1]" "sddqm[0]" \ - "address[27]" "address[26]" "address[25]" "address[24]" \ - "address[23]" "address[22]" "address[21]" "address[20]" \ - "address[19]" "address[18]" "address[17]" "address[16]" \ - "address[15]" "address[14]" "address[13]" "address[12]" \ - "address[11]" "address[10]" "address[9]" "address[8]" \ - "address[7]" "address[6]" "address[5]" "address[4]" \ - "address[3]" "address[2]" "address[1]" "address[0]"} - -*/ -set_max_area 0 -set_max_transition 2.0 leon3mp -set_flatten false -design {"leon3mp.db:leon3mp"} -set_structure true -design {"leon3mp.db:leon3mp"} -boolean false -timing true - - -compile -map_effort medium -boundary_optimization - -write -f db -hier leon3mp -output leon3mp.db - -report_timing -report_area diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18.rc b/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18.rc deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18.rc +++ /dev/null @@ -1,8 +0,0 @@ -set_attribute lib_search_path {. /usr/local/rs41/libs} -set_attribute library {"SClib-max+ind.lib" "IO33lib-max+ind.lib" "/home/jiri/ibm/vhdl/temic/atc18/allmem.lib" } / -include leon3mp.rc -include atc18cond.rc -define_clock -period 5000 -name clock1 clk -synthesize -to_mapped -report_area -report_timing diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18cond.dc b/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18cond.dc deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18cond.dc +++ /dev/null @@ -1,536 +0,0 @@ -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[31] -to do[31] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[32] -to do[32] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[33] -to do[33] - -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[31] -to do[31] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[32] -to do[32] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[33] -to do[33] - -set_disable_timing IO33lib-max+ind/pt33b01 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b02 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b03 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b04 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b01u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b02u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b03u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b04u -from pad -to cin diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18cond.rc b/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18cond.rc deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/atc18cond.rc +++ /dev/null @@ -1,528 +0,0 @@ -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[31] -to do[31] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[32] -to do[32] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[33] -to do[33] - -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[31] -to do[31] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[32] -to do[32] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[33] -to do[33] - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.help b/designs/Projet-LeonLFR-A3P3K-Sheldon/config.help deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.help +++ /dev/null @@ -1,1171 +0,0 @@ - - -Prompt for target technology -CONFIG_SYN_INFERRED - Selects the target technology for memory and pads. - The following are available: - - - Inferred: Generic FPGA or ASIC targets if your synthesis tool - is capable of inferring RAMs and pads automatically. - - - Actel ProAsic/P/3 and Axellerator FPGAs - - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS - - Altera: Most Altera FPGA families - - Altera-Stratix: Altera Stratix FPGA family - - Altera-StratixII: Altera Stratix-II FPGA family - - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS - - IHP25: IHP 0.25 um CMOS - - IHP25RH: IHP Rad-Hard 0.25 um CMOS - - Lattice : EC/ECP/XP FPGAs - - Quicklogic : Eclipse/E/II FPGAs - - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries - - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries - - Xilinx-Spartan3E: Xilinx Spartan3E libraries - - Xilinx-Virtex/E: Xilinx Virtex/E libraries - - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries - - -Ram library -CONFIG_MEM_VIRAGE - Select RAM generators for ASIC targets. - -Infer ram -CONFIG_SYN_INFER_RAM - Say Y here if you want the synthesis tool to infer your - RAM automatically. Say N to directly instantiate technology- - specific RAM cells for the selected target technology package. - -Infer pads -CONFIG_SYN_INFER_PADS - Say Y here if you want the synthesis tool to infer pads. - Say N to directly instantiate technology-specific pads from - the selected target technology package. - -No async reset -CONFIG_SYN_NO_ASYNC - Say Y here if you disable asynchronous reset in some of the IP cores. - Might be necessary if the target library does not have cells with - asynchronous set/reset. - -Scan support -CONFIG_SYN_SCAN - Say Y here to enable scan support in some cores. This will enable - the scan support generics where available and add logic to make - the design testable using full-scan. - -Use Virtex CLKDLL for clock synchronisation -CONFIG_CLK_INFERRED - Certain target technologies include clock generators to scale or - phase-adjust the system and SDRAM clocks. This is currently supported - for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you - can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2), - the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL - (Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred' - option to skip a clock generator. - -Clock multiplier -CONFIG_CLK_MUL - When using the Xilinx DCM or Altera ALTPLL, the system clock can - be multiplied with a factor of 2 - 32, and divided by a factor of - 1 - 32. This makes it possible to generate almost any desired - processor frequency. When using the Xilinx CLKDLL generator, - the resulting frequency scale factor (mul/div) must be one of - 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128. - - WARNING: The resulting clock must be within the limits specified - by the target FPGA family. - -Clock divider -CONFIG_CLK_DIV - When using the Xilinx DCM or Altera ALTPLL, the system clock can - be multiplied with a factor of 2 - 32, and divided by a factor of - 1 - 32. This makes it possible to generate almost any desired - processor frequency. When using the Xilinx CLKDLL generator, - the resulting frequency scale factor (mul/div) must be one of - 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128. - - WARNING: The resulting clock must be within the limits specified - by the target FPGA family. - -Output clock divider -CONFIG_OCLK_DIV - When using the Proasic3 PLL, the system clock is generated by three - parameters: input clock multiplication, input clock division and - output clock division. Only certain values of these parameters - are allowed, but unfortunately this is not documented by Actel. - To find the correct values, run the Libero Smartgen tool and - insert you desired input and output clock frequencies in the - Static PLL configurator. The mul/div factors can then be read - out from tool. - -System clock multiplier -CONFIG_CLKDLL_1_2 - The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0, - or 2.0. Useful when the target board has an oscillator with a too high - (or low) frequency for your design. The divided clock will be used as the - main clock for the whole processor (except PCI and ethernet clocks). - -System clock multiplier -CONFIG_DCM_2_3 - The Xilinx DCM and Altera ALTDLL can scale the input clock with a large - range of factors. Useful when the target board has an oscillator with a - too high (or low) frequency for your design. The divided clock will - be used as the main clock for the whole processor (except PCI and - ethernet clocks). NOTE: the resulting frequency must be at least - 24 MHz or the DCM and ALTDLL might not work. - -Enable CLKDLL for PCI clock -CONFIG_PCI_CLKDLL - Say Y here to re-synchronize the PCI clock using a - Virtex BUFGDLL macro. Will improve PCI clock-to-output - delays on the expense of input-setup requirements. - -Use PCI clock system clock -CONFIG_PCI_SYSCLK - Say Y here to the PCI clock to generate the system clock. - The PCI clock can be scaled using the DCM or CLKDLL to - generate a suitable processor clock. - -External SDRAM clock feedback -CONFIG_CLK_NOFB - Say Y here to disable the external clock feedback to synchronize the - SDRAM clock. This option is necessary if your board or design does not - have an external clock feedback that is connected to the pllref input - of the clock generator. - -Number of processors -CONFIG_PROC_NUM - The number of processor cores. The LEON3MP design can accomodate - up to 4 LEON3 processor cores. Use 1 unless you know what you are - doing ... - -Number of SPARC register windows -CONFIG_IU_NWINDOWS - The SPARC architecture (and LEON) allows 2 - 32 register windows. - However, any number except 8 will require that you modify and - recompile your run-time system or kernel. Unless you know what - you are doing, use 8. - -SPARC V8 multiply and divide instruction -CONFIG_IU_V8MULDIV - If you say Y here, the SPARC V8 multiply and divide instructions - will be implemented. The instructions are: UMUL, UMULCC, SMUL, - SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent - integer multiplications and divisions, significant performance - increase can be achieved. Emulated floating-point operations will - also benefit from this option. - - By default, the gcc compiler does not emit multiply or divide - instructions and your code must be compiled with -mv8 to see any - performance increase. On the other hand, code compiled with -mv8 - will generate an illegal instruction trap when executed on processors - with this option disabled. - - The divider consumes approximately 2 kgates, the multiplier 6 kgates. - -Multiplier latency -CONFIG_IU_MUL_LATENCY_2 - Implementation options for the integer multiplier. - - Type Implementation issue-rate/latency - 2-clocks 32x32 pipelined multiplier 1/2 - 4-clocks 16x16 standard multiplier 4/4 - 5-clocks 16x16 pipelined multiplier 4/5 - -Multiplier latency -CONFIG_IU_MUL_MAC - If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate) - instructions will be enabled. The instructions implement a - single-cycle 16x16->32 bits multiply with a 40-bits accumulator. - The details of these instructions can be found in the LEON manual, - This option is only available when 16x16 multiplier is used. - -Single vector trapping -CONFIG_IU_SVT - Single-vector trapping is a SPARC V8e option to reduce code-size - in small applications. If enabled, the processor will jump to - the address of trap 0 (tt = 0x00) for all traps. No trap table - is then needed. The trap type is present in %psr.tt and must - be decoded by the O/S. Saves 4 Kbyte of code, but increases - trap and interrupt overhead. Currently, the only O/S supporting - this option is eCos. To enable SVT, the O/S must also set bit 13 - in %asr17. - -Load latency -CONFIG_IU_LDELAY - Defines the pipeline load delay (= pipeline cycles before the data - from a load instruction is available for the next instruction). - One cycle gives best performance, but might create a critical path - on targets with slow (data) cache memories. A 2-cycle delay can - improve timing but will reduce performance with about 5%. - -Reset address -CONFIG_IU_RSTADDR - By default, a SPARC processor starts execution at address 0. - With this option, any 4-kbyte aligned reset start address can be - choosen. Keep at 0 unless you really know what you are doing. - -Power-down -CONFIG_PWD - Say Y here to enable the power-down feature of the processor. - Might reduce the maximum frequency slightly on FPGA targets. - For details on the power-down operation, see the LEON3 manual. - -Hardware watchpoints -CONFIG_IU_WATCHPOINTS - The processor can have up to 4 hardware watchpoints, allowing to - create both data and instruction breakpoints at any memory location, - also in PROM. Each watchpoint will use approximately 500 gates. - Use 0 to disable the watchpoint function. - -Floating-point enable -CONFIG_FPU_ENABLE - Say Y here to enable the floating-point interface for the MEIKO - or GRFPU. Note that no FPU's are provided with the GPL version - of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial - cores and must be obtained separately. - -FPU selection -CONFIG_FPU_GRFPU - Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun - Meiko FPU core. All cores are fully IEEE-754 compatible and support - all SPARC FPU instructions. - -GRFPU Multiplier -CONFIG_FPU_GRFPU_INFMUL - On FPGA targets choose inferred multiplier. For ASIC implementations - choose between Synopsys Design Ware (DW) multiplier or Module - Generator (ModGen) multiplier. The DW multiplier gives better results - (smaller area and better timing) but requires a DW license. - The ModGen multiplier is part of GRLIB and does not require a license. - -Shared GRFPU -CONFIG_FPU_GRFPU_SH - If enabled multiple CPU cores will share one GRFPU. - -GRFPC Configuration -CONFIG_FPU_GRFPC0 - Configures the GRFPU-LITE controller. - - In simple configuration controller executes FP instructions - in parallel with integer instructions. FP operands are fetched - in the register file stage and the result is written in the write - stage. This option uses least area resources. - - Data forwarding configuration gives ~ 10 % higher FP performance than - the simple configuration by adding data forwarding between the pipeline - stages. - - Non-blocking controller allows FP load and store instructions to - execute in parallel with FP instructions. The performance increase is - ~ 20 % for FP applications. This option uses most logic resources and - is suitable for ASIC implementations. - -Floating-point netlist -CONFIG_FPU_NETLIST - Say Y here to use a VHDL netlist of the GRFPU-Lite. This is - only available in certain versions of grlib. - -Enable Instruction cache -CONFIG_ICACHE_ENABLE - The instruction cache should always be enabled to allow - maximum performance. Some low-end system might want to - save area and disable the cache, but this will reduce - the performance with a factor of 2 - 3. - -Enable Data cache -CONFIG_DCACHE_ENABLE - The data cache should always be enabled to allow - maximum performance. Some low-end system might want to - save area and disable the cache, but this will reduce - the performance with a factor of 2 at least. - -Instruction cache associativity -CONFIG_ICACHE_ASSO1 - The instruction cache can be implemented as a multi-set cache with - 1 - 4 sets. Higher associativity usually increases the cache hit - rate and thereby the performance. The downside is higher power - consumption and increased gate-count for tag comparators. - - Note that a 1-set cache is effectively a direct-mapped cache. - -Instruction cache set size -CONFIG_ICACHE_SZ1 - The size of each set in the instuction cache (kbytes). Valid values - are 1 - 64 in binary steps. Note that the full range is only supported - by the generic and virtex2 targets. Most target packages are limited - to 2 - 16 kbyte. Large set size gives higher performance but might - affect the maximum frequency (on ASIC targets). The total instruction - cache size is the number of set multiplied with the set size. - -Instruction cache line size -CONFIG_ICACHE_LZ16 - The instruction cache line size. Can be set to either 16 or 32 - bytes per line. Instruction caches typically benefit from larger - line sizes, but on small caches it migh be better with 16 bytes/line - to limit eviction miss rate. - -Instruction cache replacement algorithm -CONFIG_ICACHE_ALGORND - Cache replacement algorithm for caches with 2 - 4 sets. The 'random' - algorithm selects the set to evict randomly. The least-recently-replaced - (LRR) algorithm evicts the set least recently replaced. The least- - recently-used (LRU) algorithm evicts the set least recently accessed. - The random algorithm uses a simple 1- or 2-bit counter to select - the eviction set and has low area overhead. The LRR scheme uses one - extra bit in the tag ram and has therefore also low area overhead. - However, the LRR scheme can only be used with 2-set caches. The LRU - scheme has typically the best performance but also highest area overhead. - A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops - per line, and a 4-set LRU uses 5 flip-flops per line to store the access - history. - -Instruction cache locking -CONFIG_ICACHE_LOCK - Say Y here to enable cache locking in the instruction cache. - Locking can be done on cache-line level, but will increase the - width of the tag ram with one bit. If you don't know what - locking is good for, it is safe to say N. - -Data cache associativity -CONFIG_DCACHE_ASSO1 - The data cache can be implemented as a multi-set cache with - 1 - 4 sets. Higher associativity usually increases the cache hit - rate and thereby the performance. The downside is higher power - consumption and increased gate-count for tag comparators. - - Note that a 1-set cache is effectively a direct-mapped cache. - -Data cache set size -CONFIG_DCACHE_SZ1 - The size of each set in the data cache (kbytes). Valid values are - 1 - 64 in binary steps. Note that the full range is only supported - by the generic and virtex2 targets. Most target packages are limited - to 2 - 16 kbyte. A large cache gives higher performance but the - data cache is timing critical an a too large setting might affect - the maximum frequency (on ASIC targets). The total data cache size - is the number of set multiplied with the set size. - -Data cache line size -CONFIG_DCACHE_LZ16 - The data cache line size. Can be set to either 16 or 32 bytes per - line. A smaller line size gives better associativity and higher - cache hit rate, but requires a larger tag memory. - -Data cache replacement algorithm -CONFIG_DCACHE_ALGORND - See the explanation for instruction cache replacement algorithm. - -Data cache locking -CONFIG_DCACHE_LOCK - Say Y here to enable cache locking in the data cache. - Locking can be done on cache-line level, but will increase the - width of the tag ram with one bit. If you don't know what - locking is good for, it is safe to say N. - -Data cache snooping -CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. - -Separate snoop tags -CONFIG_DCACHE_SNOOP_SEPTAG - Enable a separate memory to store the data tags used for snooping. - This is necessary when snooping support is wanted in systems - with MMU, typically for SMP systems. In this case, the snoop - tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. - -Fixed cacheability map -CONFIG_CACHE_FIXED - If this variable is 0, the cacheable memory regions are defined - by the AHB plug&play information (default). To overriden the - plug&play settings, this variable can be set to indicate which - areas should be cached. The value is treated as a 16-bit hex value - with each bit defining if a 256 Mbyte segment should be cached or not. - The right-most (LSB) bit defines the cacheability of AHB address - 0 - 256 MByte, while the left-most bit (MSB) defines AHB address - 3840 - 4096 MByte. If the bit is set, the corresponding area is - cacheable. A value of 00F3 defines address 0 - 0x20000000 and - 0x40000000 - 0x80000000 as cacheable. - -Local data ram -CONFIG_DCACHE_LRAM - Say Y here to add a local ram to the data cache controller. - Accesses to the ram (load/store) will be performed at 0 waitstates - and store data will never be written back to the AHB bus. - -Size of local data ram -CONFIG_DCACHE_LRAM_SZ1 - Defines the size of the local data ram in Kbytes. Note that most - technology libraries do not support larger rams than 16 Kbyte. - -Start address of local data ram -CONFIG_DCACHE_LRSTART - Defines the 8 MSB bits of start address of the local data ram. - By default set to 8f (start address = 0x8f000000), but any value - (except 0) is possible. Note that the local data ram 'shadows' - a 16 Mbyte block of the address space. - -MMU enable -CONFIG_MMU_ENABLE - Say Y here to enable the Memory Management Unit. - -MMU split icache/dcache table lookaside buffer -CONFIG_MMU_COMBINED - Select "combined" for a combined icache/dcache table lookaside buffer, - "split" for a split icache/dcache table lookaside buffer - -MMU tlb replacement scheme -CONFIG_MMU_REPARRAY - Select "LRU" to use the "least recently used" algorithm for TLB - replacement, or "Increment" for a simple incremental replacement - scheme. - -Combined i/dcache tlb -CONFIG_MMU_I2 - Select the number of entries for the instruction TLB, or the - combined icache/dcache TLB if such is used. - -Split tlb, dcache -CONFIG_MMU_D2 - Select the number of entries for the dcache TLB. - -Fast writebuffer -CONFIG_MMU_FASTWB - Only selectable if split tlb is enabled. In case fast writebuffer is - enabled the tlb hit will be made concurrent to the cache hit. This - leads to higher store performance, but increased power and area. - -MMU pagesize -CONFIG_MMU_PAGE_4K - The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the - cache way size to 4 Kbyte, and total data cache size to 16 Kbyte, - when the MMU is used. To increase the maximum data cache size, - the MMU pages size can be increased to up 32 Kbyte. This will - give a maximum data cache size of 128 Kbyte. - - Note that an MMU page size different than 4 Kbyte will require - a special linux tool-chain if glibc is used. If you don't know - what you are doing, stay with 4 Kbyte ... - -DSU enable -CONFIG_DSU_ENABLE - The debug support unit (DSU) allows non-intrusive debugging and tracing - of both executed instructions and AHB transfers. If you want to enable - the DSU, say Y here and select the configuration below. - -Trace buffer enable -CONFIG_DSU_TRACEBUF - Say Y to enable the trace buffer. The buffer is not necessary for - debugging, only for tracing instructions and data transfers. - -Enable instruction tracing -CONFIG_DSU_ITRACE - If you say Y here, an instruction trace buffer will be implemented - in each processor. The trace buffer will trace executed instructions - and their results, and place them in a circular buffer. The buffer - can be read out by any AHB master, and in particular by the debug - communication link. - -Size of trace buffer -CONFIG_DSU_ITRACESZ1 - Select the buffer size (in kbytes) for the instruction trace buffer. - Each line in the buffer needs 16 bytes. A 128-entry buffer will thus - need 2 kbyte. - -Enable AHB tracing -CONFIG_DSU_ATRACE - If you say Y here, an AHB trace buffer will be implemented in the - debug support unit processor. The AHB buffer will trace all transfers - on the AHB bus and save them in a circular buffer. The trace buffer - can be read out by any AHB master, and in particular by the debug - communication link. - -Size of trace buffer -CONFIG_DSU_ATRACESZ1 - Select the buffer size (in kbytes) for the AHB trace buffer. - Each line in the buffer needs 16 bytes. A 128-entry buffer will thus - need 2 kbyte. - - -LEON3FT enable -CONFIG_LEON3FT_EN - Say Y here to use the fault-tolerant LEON3FT core instead of the - standard non-FT LEON3. - -IU Register file protection -CONFIG_IUFT_NONE - Select the FT implementation in the LEON3FT integer unit - register file. The options include parity, parity with - sparing, 7-bit BCH and TMR. - -FPU Register file protection -CONFIG_FPUFT_EN - Say Y to enable SEU protection of the FPU register file. - The GRFPU will be protected using 8-bit parity without restart, while - the GRFPU-Lite will be protected with 4-bit parity with restart. If - disabled the FPU register file will be implemented using flip-flops. - -Cache memory error injection -CONFIG_RF_ERRINJ - Say Y here to enable error injection in to the IU/FPU regfiles. - Affects only simulation. - -Cache memory protection -CONFIG_CACHE_FT_EN - Enable SEU error-correction in the cache memories. - -Cache memory error injection -CONFIG_CACHE_ERRINJ - Say Y here to enable error injection in to the cache memories. - Affects only simulation. - -Leon3ft netlist -CONFIG_LEON3_NETLIST - Say Y here to use a VHDL netlist of the LEON3FT. This is - only available in certain versions of grlib. - -IU assembly printing -CONFIG_IU_DISAS - Enable printing of executed instructions to the console. - -IU assembly printing in netlist -CONFIG_IU_DISAS_NET - Enable printing of executed instructions to the console also - when simulating a netlist. NOTE: with this option enabled, it - will not be possible to pass place&route. - -32-bit program counters -CONFIG_DEBUG_PC32 - Since the LSB 2 bits of the program counters always are zero, they are - normally not implemented. If you say Y here, the program counters will - be implemented with full 32 bits, making debugging of the VHDL model - much easier. Turn of this option for synthesis or you will be wasting - area. -CONFIG_AHB_DEFMST - Sets the default AHB master (see AMBA 2.0 specification for definition). - Should not be set to a value larger than the number of AHB masters - 1. - For highest processor performance, leave it at 0. - -Default AHB master -CONFIG_AHB_RROBIN - Say Y here to enable round-robin arbitration of the AHB bus. A N will - select fixed priority, with the master with the highest bus index having - the highest priority. - -Support AHB split-transactions -CONFIG_AHB_SPLIT - Say Y here to enable AHB split-transaction support in the AHB arbiter. - Unless you actually have an AHB slave that can generate AHB split - responses, say N and save some gates. - -Default AHB master -CONFIG_AHB_IOADDR - Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined - in the plug&play extentions of the AMBA bus. Should be kept to FFF - unless you really know what you are doing. - -APB bridge address -CONFIG_APB_HADDR - Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be - kept at 800 for software compatibility. - -AHB monitor -CONFIG_AHB_MON - Say Y to enable the AHB bus monitor. The monitor will check for - illegal AHB transactions during simulation. It has no impact on - synthesis. - -Report AHB errors -CONFIG_AHB_MONERR - Print out detected AHB violations on console. - -Report AHB warnings -CONFIG_AHB_MONWAR - Print out detected AHB warnings on console. - - -DSU enable -CONFIG_DSU_UART - Say Y to enable the AHB uart (serial-to-AHB). This is the most - commonly used debug communication link. - -JTAG Enable -CONFIG_DSU_JTAG - Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done - with GRMON through the boards JTAG chain at speed of 300 kbits/s. - Supported JTAG cables are Xilinx Parallel Cable III and IV. - -Ethernet DSU enable -CONFIG_DSU_ETH - Say Y to enable the Ethernet Debug Communication Link (EDCL). The link - provides a DSU gateway between ethernet and the AHB bus. Debugging is - done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must - enable the GRETH Ethernet MAC for this option to become active. - -Size of EDCL trace buffer -CONFIG_DSU_ETHSZ1 - Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is - usually enough, while a larger buffer will increase the transfer rate. - When operating at 100 Mbit, use a buffer size of at least 8 kbyte for - maximum throughput. - -MSB IP address -CONFIG_DSU_IPMSB - Set the MSB 16 bits of the IP address of the EDCL. - -LSB IP address -CONFIG_DSU_IPLSB - Set the LSB 16 bits of the IP address of the EDCL. - -MSB ethernet address -CONFIG_DSU_ETHMSB - Set the MSB 24 bits of the ethernet address of the EDCL. - -LSB ethernet address -CONFIG_DSU_ETHLSB - Set the LSB 24 bits of the ethernet address of the EDCL. - -Programmable MAC/IP address -CONFIG_DSU_ETH_PROG - Say Y to make the LSB 4 bits of the EDCL MAC and IP address - configurable using the ethi.edcladdr inputs. -PROM/SRAM memory controller -CONFIG_SRCTRL - Say Y here to enable a simple (and small) PROM/SRAM memory controller. - The controller has a fixed number of waitstates, and is primarily - intended for FPGA implementations. The RAM data bus is always 32 bits, - the PROM can be configured to either 8 or 32 bits (hardwired). - -8-bit memory support -CONFIG_SRCTRL_8BIT - If you say Y here, the simple PROM/SRAM memory controller will - implement 8-bit PROM mode. - -PROM waitstates -CONFIG_SRCTRL_PROMWS - Select the number of waitstates for PROM access. - -RAM waitstates -CONFIG_SRCTRL_RAMWS - Select the number of waitstates for RAM access. - -IO waitstates -CONFIG_SRCTRL_IOWS - Select the number of waitstates for IO access. - -Read-modify-write support -CONFIG_SRCTRL_RMW - Say Y here to perform byte- and half-word writes as a - read-modify-write sequence. This is necessary if your - SRAM does not have individual byte enables. If you are - unsure, it is safe to say Y. - -SRAM bank select -CONFIG_SRCTRL_SRBANKS - Select number of SRAM banks. - -SRAM bank size select -CONFIG_SRCTRL_BANKSZ - Select size of SRAM banks in kBytes. - -PROM address bit select -CONFIG_SRCTRL_ROMASEL - Select address bit for PROM bank decoding. -Leon2 memory controller -CONFIG_MCTRL_LEON2 - Say Y here to enable the LEON2 memory controller. The controller - can access PROM, I/O, SRAM and SDRAM. The bus width for PROM - and SRAM is programmable to 8-, 16- or 32-bits. - -8-bit memory support -CONFIG_MCTRL_8BIT - If you say Y here, the PROM/SRAM memory controller will support - 8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit. - Say N to save a few hundred gates. - -16-bit memory support -CONFIG_MCTRL_16BIT - If you say Y here, the PROM/SRAM memory controller will support - 16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit. - Say N to save a few hundred gates. - -Write strobe feedback -CONFIG_MCTRL_WFB - If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will - be used to enable the data bus drivers during write cycles. This - will guarantee that the data is still valid on the rising edge of - the write strobe. If you say N, the write strobes and the data bus - drivers will be clocked on the rising edge, potentially creating - a hold time problem in external memory or I/O. However, in all - practical cases, there is enough capacitance in the data bus lines - to keep the value stable for a few (many?) nano-seconds after the - buffers have been disabled, making it safe to say N and remove a - combinational path in the netlist that might be difficult to - analyze. - -Write strobe feedback -CONFIG_MCTRL_5CS - If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will - be enabled. If you don't intend to use it, say N and save some gates. - -SDRAM controller enable -CONFIG_MCTRL_SDRAM - Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't - intend to use SDRAM, say N and save about 1 kgates. - -SDRAM controller inverted clock -CONFIG_MCTRL_SDRAM_INVCLK - If you say Y here, the SDRAM controller output signals will be delayed - with 1/2 clock in respect to the SDRAM clock. This will allow the used - of an SDRAM clock which in not strictly in phase with the internal - clock. This option will limit the SDRAM frequency to 40 - 50 MHz. - - On FPGA targets without SDRAM clock synchronizations through PLL/DLL, - say Y. On ASIC targets, say N and tell your foundry to balance the - SDRAM clock output. - -SDRAM separate address buses -CONFIG_MCTRL_SDRAM_SEPBUS - Say Y here if your SDRAM is connected through separate address - and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000 - board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards. - -64-bit data bus -CONFIG_MCTRL_SDRAM_BUS64 - Say Y here to enable 64-bit SDRAM data bus. - -Page burst enable -CONFIG_MCTRL_PAGE - Say Y here to enable SDRAM page burst operation. This will implement - read operations using page bursts rather than 8-word bursts and save - about 500 gates (100 LUTs). Note that not all SDRAM supports page - burst, so use this option with care. - -Programmable page burst enable -CONFIG_MCTRL_PROGPAGE - Say Y here to enable programmable SDRAM page burst operation. This - will allow to dynamically enable/disable page burst by setting - bit 17 in MCFG2. - -SDRAM controller enable -CONFIG_SDCTRL - Say Y here to enabled a 32/64-bit PC133 SDRAM controller. - -SDRAM controller inverted clock -CONFIG_SDCTRL_INVCLK - If you say Y here, the SDRAM clock will be inverted in respect to the - system clock and the SDRAM signals. This will limit the SDRAM frequency - to 50/66 MHz, but has the benefit that you will not need a PLL to - generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets, - say N and tell your foundry to balance the SDRAM clock output. - -64-bit data bus -CONFIG_SDCTRL_BUS64 - Say Y here to enable 64-bit data bus. - -Page burst enable -CONFIG_SDCTRL_PAGE - Say Y here to enable SDRAM page burst operation. This will implement - read operations using page bursts rather than 8-word bursts and save - about 500 gates (100 LUTs). Note that not all SDRAM supports page - burst, so use this option with care. - -Programmable page burst enable -CONFIG_SDCTRL_PROGPAGE - Say Y here to enable programmable SDRAM page burst operation. This - will allow to dynamically enable/disable page burst by setting - bit 17 in MCFG2. - -On-chip rom -CONFIG_AHBROM_ENABLE - Say Y here to add a block on on-chip rom to the AHB bus. The ram - provides 0-waitstates read access, burst support, and 8-, 16- - and 32-bit data size. The rom will be syntheised into block rams - on Xilinx and Altera FPGA devices, and into gates on ASIC - technologies. GRLIB includes a utility to automatically create - the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB - documentation for details. - -On-chip rom address -CONFIG_AHBROM_START - Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy - a 1 Mbyte slot at the selected address. Default is 000, corresponding - to AHB address 0x00000000. When address 0x0 is selected, the rom area - of any other memory controller is set to 0x10000000 to avoid conflicts. - -Enable pipeline register for on-chip rom -CONFIG_AHBROM_PIPE - Say Y here to add a data pipeline register to the on-chip rom. - This should be done when the rom is implemenented in (ASIC) gates, - or in logic cells on FPGAs. Do not use this option when the rom is - implemented in block rams. If enabled, the rom will operate with - one waitstate. - -On-chip ram -CONFIG_AHBRAM_ENABLE - Say Y here to add a block on on-chip ram to the AHB bus. The ram - provides 0-waitstates read access and 0/1 waitstates write access. - All AHB burst types are supported, as well as 8-, 16- and 32-bit - data size. - -On-chip ram size -CONFIG_AHBRAM_SZ1 - Set the size of the on-chip AHB ram. The ram is infered/instantiated - as four byte-wide ram slices to allow byte and half-word write - accesses. It is therefore essential that the target package can - infer byte-wide rams. This is currently supported on the generic, - virtex, virtex2, proasic and axellerator targets. - -On-chip ram address -CONFIG_AHBRAM_START - Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy - a 1 Mbyte slot at the selected address. Default is A00, corresponding - to AHB address 0xA0000000. - -Gaisler Ethernet MAC enable -CONFIG_GRETH_ENABLE - Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has - one AHB master interface to read and write packets to memory, and one - APB slave interface for accessing the control registers. - -Gaisler Ethernet 1G MAC enable -CONFIG_GRETH_GIGA - Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC . - The 1G MAC is only available in the commercial version of GRLIB, - so do NOT enable it if you are using the GPL version. - -CONFIG_GRETH_FIFO4 - Set the depth of the receive and transmit FIFOs in the MAC core. - The MAC core will perform AHB burst read/writes with half the - size of the FIFO depth. - - -CAN interface enable -CONFIG_CAN_ENABLE - Say Y here to enable the CAN interace from OpenCores. The core has one - AHB slave interface for accessing the control registers. The CAN core - ir register-compatible with the SAJ1000 core from Philips. - -CAN register address -CONFIG_CANIO - The control registers of the CAN core occupy 4 kbyte, and are - mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting - defines at which address in the I/O area the registers appear (HADDR[19:8]). - -CAN interrupt -CONFIG_CANIRQ - Defines which interrupt number the CAN core will generate. - -CAN loob-back testing -CONFIG_CANLOOP - If you say Y here, the receiver and trasmitter of the CAN core will - be connected together in a loop-back fashion. This will make it - possible to perform loop-back test, but not data will be sent - or received from the outside. ONLY for testing! - -CAN Synchronous reset -CONFIG_CAN_SYNCRST - If you say Y here, the CAN core will be implemented with - synchronous reset rather than asynchronous. This is needed - when the target library does not implement registers with - async reset. Unless you know what you are doing, say N. - -CAN FT memories -CONFIG_CAN_FT - If you say Y here, the CAN FIFOs will be implemented using - SEU protected RAM blocks. Only applicable to the FT version - of grlib. -PCI interface type -CONFIG_PCI_SIMPLE_TARGET - The target-only PCI interface provides a simple target interface - without fifos. It is small and robust, and is suitable to be used - for DSU communications via PCI. - -PCI interface type -CONFIG_PCI_MASTER_TARGET - The master-target PCI interface provides a high-performance 32-bit - PCI interface with configurable FIFOs and optional DMA channel. - -PCI interface type -CONFIG_PCI_MASTER_TARGET_DMA - Say Y here to enable a DMA controller in the PCI master-target core. - The DMA controller can perform PCI<->memory data transfers - independently of the processor. - -PCI vendor id -CONFIG_PCI_VENDORID - Sets the PCI vendor ID in the PCI configuration area. - -PCI device id -CONFIG_PCI_DEVICEID - Sets the PCI device ID in the PCI configuration area. - -PCI initiator address -CONFIG_PCI_HADDR - Sets the MSB AHB adress (HADDR[31:20]) of the PCI initiator area. - -PCI FIFO depth -CONFIG_PCI_FIFO8 - The number words in the PCI FIFO buffers in the master-target - core. The master interface uses four 33-bit wide FIFOs, while the - target interface uses two. - - -PCI arbiter enable -CONFIG_PCI_ARBITER - To enable a PCI arbiter, say Y here. - -PCI APB interface enable -CONFIG_PCI_ARBITER_APB - Say Y here to enable the APB interface on the PCI arbiter. This makes - it possible to dynamically re-assign PCI master priorities. See the - PCI arbiter manual for details. - -PCI arbiter request signals -CONFIG_PCI_ARBITER_NREQ - The number of PCI bus request/grant pairs. Should be not - be more than 8. Note that the processor needs one, so the - minimum should be 2. - -PCI trace buffer -CONFIG_PCI_TRACE - The PCI trace buffer implements a simple on-chip logic analyzer - to trace the PCI signals. The PCI AD bus and most control signals - are stored in a circular buffer, and can be read out by the DSU - or any other AHB master. See the manual for detailed operation. - Only available for target technologies with dual-port rams. - -PCI trace buffer depth -CONFIG_PCI_TRACE256 - Select the number of entries in the PCI trace buffer. Each entry - will use 6 bytes of on-chip (block) ram. - - -Spacewire link -CONFIG_SPW_ENABLE - Say Y here to enable one or more Spacewire serial links. The links - are based on the GRSPW core from Gaisler Research. - -Number of spacewire links -CONFIG_SPW_NUM - Select the number of links to implement. Each link will be a - separate AHB master and APB slave for configuration. - -AHB FIFO depth -CONFIG_SPW_AHBFIFO4 - Select the AHB FIFO depth (in 32-bit words). - -RX FIFO depth -CONFIG_SPW_RXFIFO16 - Select the receiver FIFO depth (in bytes). - -RMAP protocol -CONFIG_SPW_RMAP - Enable hardware target support for the RMAP protocol ( - draft C for GRSPW1 and ECSS-E-ST-50-11C Draft V1.3 - for GRSPW2). - -RMAP Buffer depth -CONFIG_SPW_RMAPBUF2 - Select the size of the RMAP buffer (in bytes). - -RMAP CRC -CONFIG_SPW_RMAPCRC - Enable hardware calculation of the RMAP CRC checksum. RMAP CRC - is always enabled when the RMAP hardware target is enabled so this - parameter will have no effect in that case. - -Rx unaligned -CONFIG_SPW_RXUNAL - Enable support for byte writes used for non word-aligned - receiver buffer addresses. Without this enabled data will - still be written at the correct location but complete words - will always be written so data outside the intended boundaries - might be overwritten. - -Netlists -CONFIG_SPW_NETLIST - Use the netlist version of GRSPWC. This option is required if - you have not licensed the source code of the Spacewire core. - Currently only supported for Virtex and Axcelerator FPGAs. - The AHB/RX FIFO sizes should be set to 16 word/byte, and the - RMAP should be disabled. - -Spacewire FT -CONFIG_SPW_FT - Say Y here to implement the Spacewire block rams with fault-tolerance - against SEU errors. - -Spacewire core -CONFIG_SPW_GRSPW1 - Select to use GRSPW1 core or GRSPW2 core. - -DMA channels -CONFIG_SPW_DMACHAN - Set the number of DMA channels for the GRSPW2 core - -Ports -CONFIG_SPW_PORTS - Set the number of SpaceWire ports for the GRSPW2 core - -Same clock for SpaceWire receiver and transmitter -CONFIG_SPW_RTSAME - Say Y here if the same clock is connected to both the receiver - and transmitter in the GRSPW2 core. This will remove two - asynchronous resets and some synchronization logic. This is only - applicable for the SDR and DDR inputs modes. - - -Receiver clock type -CONFIG_SPW_RX_SDR - Selects the input clocking scheme for the GRSPW2. SDR means that the - core samples data and strobe using single data rate registers at the - receiver clock frequency. DDR is the same except DDR registers are used. - Xor selects the traditional self clocking scheme using a xor gate. - Aeroflex sets the receiver in a mode compatible with the Aeroflex - SpaceWire transceiver. - -Receiver clock type -CONFIG_SPW_TX_SDR - Selects the output clocking scheme for the GRSPW2. SDR means that the - core transmits data and strobe using single data rate registers at the - transmitter clock frequency. DDR is the same except DDR registers are used. - Aeroflex sets the transmitter in a mode compatible with the Aeroflex - SpaceWire transceiver. -UART1 enable -CONFIG_UART1_ENABLE - Say Y here to enable UART1, or the console UART. This is needed to - get any print-out from LEON3 systems regardless of operating system. - -UART1 FIFO -CONFIG_UA1_FIFO1 - The UART has configurable transmitt and receive FIFO's, which can - be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for - maximum throughput. - - -UART2 enable -CONFIG_UART2_ENABLE - Say Y here to enable UART2, or the secondary UART. This UART can be - used to connect a second console (uClinux) or to control external - equipment. - -UART2 FIFO -CONFIG_UA2_FIFO1 - The UART has configurable transmitt and receive FIFO's, which can - be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for - maximum throughput. - -LEON3 interrupt controller -CONFIG_IRQ3_ENABLE - Say Y here to enable the LEON3 interrupt controller. This is needed - if you want to be able to receive interrupts. Operating systems like - Linux, RTEMS and eCos needs this option to be enabled. If you intend - to use the Bare-C run-time and not use interrupts, you could disable - the interrupt controller and save about 500 gates. - -LEON3 interrupt controller broadcast -CONFIG_IRQ3_BROADCAST_ENABLE - If enabled the broadcast register is used to determine which - interrupt should be sent to all cpus instead of just the first - one that consumes it. - -Secondary interrupts -CONFIG_IRQ3_SEC - The interrupt controller handles 15 interrupts by default (1 - 15). - These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F), - and AMBA interrupts 1 - 15. This option will enable 16 additional - (secondary) interrupts, corresponding to AMBA interrupts 16 - 31. - The secondary interrupts will be multiplexed onto one of the first - 15 interrupts. The total number of handled interrupts can then - be up to 30 (14 primary and 16 secondary). - -Number of interrupts -CONFIG_IRQ3_NSEC - Defines which of the first 15 interrupts should be used for the - secondary (16 - 31) interrupts. Interrupt 15 should be avoided - since it is not maskable by the processor. -Timer module enable -CONFIG_GPT_ENABLE - Say Y here to enable the Modular Timer Unit. The timer unit consists - of one common scaler and up to 7 independent timers. The timer unit - is needed for Linux, RTEMS, eCos and the Bare-C run-times. - -Timer module enable -CONFIG_GPT_NTIM - Set the number of timers in the timer unit (1 - 7). - -Scaler width -CONFIG_GPT_SW - Set the width if the common pre-scaler (2 - 16 bits). The scaler - is used to divide the system clock down to 1 MHz, so 8 bits should - be sufficient for most implementations (allows clocks up to 256 MHz). - -Timer width -CONFIG_GPT_TW - Set the width if the timers (2 - 32 bits). 32 bits is recommended - for the Bare-C run-time, lower values (e.g. 16 bits) can work with - RTEMS and Linux. - -Timer Interrupt -CONFIG_GPT_IRQ - Set the interrupt number for the first timer. Remaining timers will - have incrementing interrupts, unless the separate-interrupts option - below is disabled. - -Watchdog enable -CONFIG_GPT_WDOGEN - Say Y here to enable the watchdog functionality in the timer unit. - -Watchdog time-out value -CONFIG_GPT_WDOG - This value will be loaded in the watchdog timer at reset. - -GPIO port -CONFIG_GRGPIO_ENABLE - Say Y here to enable a general purpose I/O port. The port can be - configured from 1 - 32 bits, whith each port signal individually - programmable as input or output. The port signals can also serve - as interrupt inputs. - -GPIO port witdth -CONFIG_GRGPIO_WIDTH - Number of bits in the I/O port. Must be in the range of 1 - 32. - -GPIO interrupt mask -CONFIG_GRGPIO_IMASK - The I/O port interrupt mask defines which bits in the I/O port - should be able to create an interrupt. - -UART debugging -CONFIG_DEBUG_UART - During simulation, the output from the UARTs is printed on the - simulator console. Since the ratio between the system clock and - UART baud-rate is quite high, simulating UART output will be very - slow. If you say Y here, the UARTs will print a character as soon - as it is stored in the transmitter data register. The transmitter - ready flag will be permanently set, speeding up simulation. However, - the output on the UART tx line will be garbled. Has not impact on - synthesis, but will cause the LEON test bench to fail. - -FPU register tracing -CONFIG_DEBUG_FPURF - If you say Y here, all writes to the floating-point unit register file - will be printed on the simulator console. - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.in b/designs/Projet-LeonLFR-A3P3K-Sheldon/config.in deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.in +++ /dev/null @@ -1,89 +0,0 @@ -# -# LEON3 configuration written in linux configuration language -# -# Written by Jiri Gaisler, Gaisler Research -# -# Comments and bug reports to jiri@gaisler.com -# -# - -#define_bool CONFIG_MCTRL_RMW y - -mainmenu_name "LEON3MP Design Configuration" - -mainmenu_option next_comment - comment 'Synthesis ' - source lib/techmap/gencomp/tech.in -endmenu - -mainmenu_option next_comment - comment 'Clock generation' - source lib/techmap/clocks/clkgen.in -endmenu - -source lib/gaisler/leon3/leon3.in -source lib/grlib/amba/amba.in - -mainmenu_option next_comment - comment 'Debug Link ' - source lib/gaisler/uart/dcom.in - source lib/gaisler/jtag/jtag.in - source lib/gaisler/net/edcl.in -endmenu - -mainmenu_option next_comment -comment 'Peripherals ' - - mainmenu_option next_comment - comment 'Memory controllers ' - source lib/gaisler/memctrl/srctrl.in - source lib/esa/memoryctrl/mctrl.in - source lib/gaisler/memctrl/sdctrl.in - endmenu - - mainmenu_option next_comment - comment 'On-chip RAM/ROM ' - source lib/gaisler/misc/ahbrom.in - source lib/gaisler/misc/ahbram.in - endmenu - - mainmenu_option next_comment - comment 'Ethernet ' - source lib/gaisler/greth/greth.in - endmenu - - mainmenu_option next_comment - comment 'CAN ' - source lib/gaisler/can/can_oc.in - endmenu - - mainmenu_option next_comment - comment 'PCI ' - source lib/gaisler/pci/pci_target.in - source lib/gaisler/pci/pci_mtf.in - source lib/gaisler/pci/pcidma.in - source lib/gaisler/pci/pci.in - source lib/esa/pci/pci_arb.in - source lib/gaisler/pci/pcitrace.in - endmenu - - mainmenu_option next_comment - comment 'Spacewire ' - source lib/gaisler/spacewire/spacewire.in - endmenu - - mainmenu_option next_comment - comment 'UARTs, timers and irq control ' - source lib/gaisler/uart/uart1.in - source lib/gaisler/uart/uart2.in - source lib/gaisler/leon3/irqmp.in - source lib/gaisler/misc/gptimer.in - source lib/gaisler/misc/grgpio.in - endmenu - -endmenu - -mainmenu_option next_comment -comment 'VHDL Debugging ' - source lib/grlib/util/debug.in -endmenu diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd +++ /dev/null @@ -1,180 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3; - constant CFG_MEMTECH : integer := apa3; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (5); - constant CFG_CLKDIV : integer := (10); - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - constant CFG_NWIN : integer := (7); - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 0 + 16*0; - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (2); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd.h b/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd.h deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd.h +++ /dev/null @@ -1,208 +0,0 @@ --- Technology and synthesis options - constant CFG_FABTECH : integer := CONFIG_SYN_TECH; - constant CFG_MEMTECH : integer := CFG_RAM_TECH; - constant CFG_PADTECH : integer := CFG_PAD_TECH; - constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; - constant CFG_SCAN : integer := CONFIG_SYN_SCAN; - --- Clock generator - constant CFG_CLKTECH : integer := CFG_CLK_TECH; - constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; - constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; - constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; - constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; - constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; - constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; - --- LEON3 processor core - constant CFG_LEON3 : integer := CONFIG_LEON3; - constant CFG_NCPU : integer := CONFIG_PROC_NUM; - constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; - constant CFG_V8 : integer := CFG_IU_V8; - constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; - constant CFG_SVT : integer := CONFIG_IU_SVT; - constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; - constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; - constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; - constant CFG_PWD : integer := CONFIG_PWD*2; - constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST; - constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; - constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; - constant CFG_ISETS : integer := CFG_IU_ISETS; - constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; - constant CFG_ILINE : integer := CFG_ILINE_SZ; - constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; - constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; - constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; - constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; - constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; - constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; - constant CFG_DSETS : integer := CFG_IU_DSETS; - constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; - constant CFG_DLINE : integer := CFG_DLINE_SZ; - constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; - constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; - constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; - constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; - constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; - constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; - constant CFG_MMUEN : integer := CONFIG_MMUEN; - constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; - constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; - constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; - constant CFG_TLB_REP : integer := CONFIG_TLB_REP; - constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; - constant CFG_DSU : integer := CONFIG_DSU_ENABLE; - constant CFG_ITBSZ : integer := CFG_DSU_ITB; - constant CFG_ATBSZ : integer := CFG_DSU_ATB; - constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; - constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; - constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; - constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; - constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; - constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; - constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; - constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; - constant CFG_PCLOW : integer := CFG_DEBUG_PC32; - --- AMBA settings - constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; - constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; - constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; - constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; - constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; - constant CFG_AHB_MON : integer := CONFIG_AHB_MON; - constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; - constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; - --- DSU UART - constant CFG_AHB_UART : integer := CONFIG_DSU_UART; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG; - constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; - constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; - constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; - constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; - constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; - --- PROM/SRAM controller - constant CFG_SRCTRL : integer := CONFIG_SRCTRL; - constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS; - constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS; - constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS; - constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW; - constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT; - - constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS; - constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ; - constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL; --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; - constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; - constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; - constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; - constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; - constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; - constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; - constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; - constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; - --- SDRAM controller - constant CFG_SDCTRL : integer := CONFIG_SDCTRL; - constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK; - constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64; - constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE; - --- AHB ROM - constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; - constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; - constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; - constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; - constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; - constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; - constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; - constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; - constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; - --- CAN 2.0 interface - constant CFG_CAN : integer := CONFIG_CAN_ENABLE; - constant CFG_CANIO : integer := 16#CONFIG_CANIO#; - constant CFG_CANIRQ : integer := CONFIG_CANIRQ; - constant CFG_CANLOOP : integer := CONFIG_CANLOOP; - constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST; - constant CFG_CANFT : integer := CONFIG_CAN_FT; - --- PCI interface - constant CFG_PCI : integer := CFG_PCITYPE; - constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#; - constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#; - constant CFG_PCIDEPTH : integer := CFG_PCIFIFO; - constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO; - --- PCI arbiter - constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER; - constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB; - constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ; - --- PCI trace buffer - constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE; - constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF; - --- Spacewire interface - constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE; - constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM; - constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO; - constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO; - constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP; - constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF; - constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC; - constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST; - constant CFG_SPW_FT : integer := CONFIG_SPW_FT; - constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW; - constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL; - constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN; - constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS; - constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT; - constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT; - constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME; --- UART 1 - constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; - constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; - --- UART 2 - constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE; - constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; - constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; - --- Modular timer - constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; - constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; - constant CFG_GPT_SW : integer := CONFIG_GPT_SW; - constant CFG_GPT_TW : integer := CONFIG_GPT_TW; - constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; - constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; - constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; - constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; - constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; - constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; - --- GRLIB debugging - constant CFG_DUART : integer := CONFIG_DEBUG_UART; - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd.in b/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd.in deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/config.vhd.in +++ /dev/null @@ -1,16 +0,0 @@ -#include "config.h" -#include "tkconfig.h" ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - -#include "config.vhd.h" - -end; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/defconfig b/designs/Projet-LeonLFR-A3P3K-Sheldon/defconfig deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/defconfig +++ /dev/null @@ -1,209 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -CONFIG_SYN_INFERRED=y -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -# CONFIG_SYN_PROASIC3 is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -CONFIG_MEM_INFERRED=y -# CONFIG_MEM_RHUMC is not set -# CONFIG_MEM_IHP25 is not set -# CONFIG_MEM_VIRAGE is not set - -# -# Clock generation -# -CONFIG_CLK_INFERRED=y -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -# CONFIG_PCI_SYSCLK is not set -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=2 -CONFIG_PWD=y -CONFIG_IU_RSTADDR=00000 -# CONFIG_IU_NOHALT is not set - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -# CONFIG_ICACHE_ASSO1 is not set -CONFIG_ICACHE_ASSO2=y -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -CONFIG_ICACHE_SZ2=y -# CONFIG_ICACHE_SZ4 is not set -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -# CONFIG_ICACHE_ALGORND is not set -CONFIG_ICACHE_ALGOLRR=y -# CONFIG_ICACHE_ALGOLRU is not set -# CONFIG_ICACHE_LOCK is not set -# CONFIG_ICACHE_LRAM is not set -CONFIG_DCACHE_ENABLE=y -# CONFIG_DCACHE_ASSO1 is not set -CONFIG_DCACHE_ASSO2=y -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -CONFIG_DCACHE_SZ2=y -# CONFIG_DCACHE_SZ4 is not set -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_ALGORND is not set -CONFIG_DCACHE_ALGOLRR=y -# CONFIG_DCACHE_ALGOLRU is not set -# CONFIG_DCACHE_LOCK is not set -# CONFIG_DCACHE_LRAM is not set - -# -# MMU -# -# CONFIG_MMU_ENABLE is not set - -# -# Debug Support Unit -# -CONFIG_DSU_ENABLE=y -CONFIG_DSU_ITRACE=y -CONFIG_DSU_ITRACESZ1=y -# CONFIG_DSU_ITRACESZ2 is not set -# CONFIG_DSU_ITRACESZ4 is not set -# CONFIG_DSU_ITRACESZ8 is not set -# CONFIG_DSU_ITRACESZ16 is not set -CONFIG_DSU_ATRACE=y -CONFIG_DSU_ATRACESZ1=y -# CONFIG_DSU_ATRACESZ2 is not set -# CONFIG_DSU_ATRACESZ4 is not set -# CONFIG_DSU_ATRACESZ8 is not set -# CONFIG_DSU_ATRACESZ16 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_ETH is not set - -# -# Peripherals -# - -# -# Memory controllers -# -CONFIG_MCTRL_SMALL=y -# CONFIG_MCTRL_SMALL_8BIT is not set -CONFIG_MCTRL_PROMWS=3 -CONFIG_MCTRL_RAMWS=0 -CONFIG_MCTRL_RMW=y -# CONFIG_MCTRL_SDRAM is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_ETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER_APB is not set -# CONFIG_PCI_TRACE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -CONFIG_UART2_ENABLE=y -# CONFIG_UA2_FIFO1 is not set -# CONFIG_UA2_FIFO2 is not set -CONFIG_UA2_FIFO4=y -# CONFIG_UA2_FIFO8 is not set -# CONFIG_UA2_FIFO16 is not set -# CONFIG_UA2_FIFO32 is not set -CONFIG_IRQ3_ENABLE=y -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y - -# -# VHDL Debugging -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_UART is not set -# CONFIG_DEBUG_PC32 is not set diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/hello.c b/designs/Projet-LeonLFR-A3P3K-Sheldon/hello.c deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/hello.c +++ /dev/null @@ -1,6 +0,0 @@ - -main() -{ - printf("\n\n Hello LEON3 World!!!\n"); - printf("\n Simulation will now be halted through error mode...\n\n"); -} diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/indata b/designs/Projet-LeonLFR-A3P3K-Sheldon/indata deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/indata +++ /dev/null @@ -1,2370 +0,0 @@ -NYTT1 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -1101 -0000 -0000 -0000 -0000 -1010 -0111 -0000 -0000 -0000 -0000 -0000 -0000 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1000 -0000 -0000 -0000 -0101 -1000 -0000 -0000 -0011 -0000 -1110 -1110 -0000 -0000 -0000 -0000 -0000 -0000 -0000 -0000 -0000 -0100 -0001 -0001 -0000 -0000 -0000 -0000 -0000 -1100 -1000 -1010 -0000 -0000 -1000 -0001 -0000 -1100 -1000 -1010 -0000 -0000 -0010 -0011 -0000 -0000 -0000 -0000 -0111 -0010 -0000 -0001 -0011 -0000 -1010 -1101 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xconfig'. -# -# CHANGES -# ======= -# -# 8 January 1999, Michael Elizabeth Chastain, -# - Remove unused do_cmd function (part of the 2.0 sound support). -# - Arrange buttons in three columns for better screen fitting. -# - Add CONSTANT_Y, CONSTANT_M, CONSTANT_N for commands like: -# dep_tristate 'foo' CONFIG_FOO m -# -# 23 January 1999, Michael Elizabeth Chastain, -# - Shut vfix the hell up. -# -# 24 January 1999, Michael Elizabeth Chastain, -# - Improve the exit message (Jeff Ronne). - -# -# This is a handy replacement for ".widget cget" that requires neither tk4 -# nor additional source code uglification. -# -proc cget { w option } { - return "[lindex [$w configure $option] 4]" -} - -# -# Function to compensate for broken config.in scripts like the sound driver, -# which make dependencies on variables that are never even conditionally -# defined. -# -proc vfix { var } { - global $var - if [ catch {eval concat $$var} ] { - set $var 4 - } -} - -# -# Constant values used by certain dep_tristate commands. -# -set CONSTANT_Y 1 -set CONSTANT_M 2 -set CONSTANT_N 0 -set CONSTANT_E 4 - -# -# Create a "reference" object to steal colors from. -# -button .ref - -# -# On monochrome displays, -disabledforeground is blank by default; that's -# bad. Fill it with -foreground instead. -# -if { [cget .ref -disabledforeground] == "" } { - .ref configure -disabledforeground [cget .ref -foreground] -} - - -# -# Define some macros we will need to parse the config.in file. -# - -proc mainmenu_name { text } { - wm title . "$text" -} - -proc menu_option { w menu_num text } { - global menus_per_column - global processed_top_level - set processed_top_level [expr $processed_top_level + 1] - if { $processed_top_level <= $menus_per_column } then { - set myframe left - } elseif { $processed_top_level <= [expr 2 * $menus_per_column] } then { - set myframe middle - } else { - set myframe right - } - button .f0.x$menu_num -anchor w -text "$text" \ - -command "$w .$w \"$text\"" - pack .f0.x$menu_num -pady 0 -side top -fill x -in .f0.$myframe -} - -proc load_configfile { w title func } { - catch {destroy $w} - toplevel $w -class Dialog - global loadfile - frame $w.x - label $w.bm -bitmap questhead - pack $w.bm -pady 10 -side top -padx 10 - label $w.x.l -text "Enter filename:" -relief raised - entry $w.x.x -width 35 -relief sunken -borderwidth 2 \ - -textvariable loadfile - pack $w.x.l $w.x.x -anchor w -side left - pack $w.x -side top -pady 10 - wm title $w "$title" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" -width 20 \ - -command "destroy $w; focus $oldFocus;$func .fileio" - button $w.f.canc -text "Cancel" \ - -width 20 -command "destroy $w; focus $oldFocus" - pack $w.f.back $w.f.canc -side left -pady 10 -padx 45 - pack $w.f -pady 10 -side bottom -padx 10 -anchor w - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy -} - -bind all {maybe_exit .maybe} - -proc maybe_exit { w } { - catch {destroy $w} - toplevel $w -class Dialog - label $w.bm -bitmap questhead - pack $w.bm -pady 10 -side top -padx 10 - message $w.m -width 400 -aspect 300 \ - -text "Changes will be lost. Are you sure?" -relief flat - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Are you sure?" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" -width 20 \ - -command "exit 1" - button $w.f.canc -text "Cancel" \ - -width 20 -command "destroy $w; focus $oldFocus" - pack $w.f.back $w.f.canc -side left -pady 10 -padx 45 - pack $w.f -pady 10 -side bottom -padx 10 -anchor w - bind $w "exit 1" - bind $w "destroy $w; focus $oldFocus" - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy -} - -proc read_config_file { w } { - global loadfile - if { [string length $loadfile] != 0 && [file readable $loadfile] == 1 } then { - read_config $loadfile - } else { - catch {destroy $w} - toplevel $w -class Dialog - message $w.m -width 400 -aspect 300 -text \ - "Unable to read file $loadfile" \ - -relief raised - label $w.bm -bitmap error - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "Xconfig Internal Error" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "Bummer" \ - -width 10 -command "destroy $w; focus $oldFocus" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - } -} - -proc write_config_file { w } { - global loadfile - if { [string length $loadfile] != 0 - && ([file writable $loadfile] == 1 || ([file exists $loadfile] == 0 && [file writable [file dirname $loadfile]] == 1)) } then { - writeconfig $loadfile .null - } else { - catch {destroy $w} - toplevel $w -class Dialog - message $w.m -width 400 -aspect 300 -text \ - "Unable to write file $loadfile" \ - -relief raised - label $w.bm -bitmap error - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "Xconfig Internal Error" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" \ - -width 10 -command "destroy $w; focus $oldFocus" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - } -} - -proc read_config { filename } { - set file1 [open $filename r] - clear_choices - while { [gets $file1 line] >= 0} { - if [regexp {([0-9A-Za-z_]+)=([ynm])} $line foo var value] { - if { $value == "y" } then { set cmd "global $var; set $var 1" } - if { $value == "n" } then { set cmd "global $var; set $var 0" } - if { $value == "m" } then { set cmd "global $var; set $var 2" } - eval $cmd - } - if [regexp {# ([0-9A-Za-z_]+) is not set} $line foo var] { - set cmd "global $var; set $var 0" - eval $cmd - } - if [regexp {([0-9A-Za-z_]+)=([0-9A-Fa-f]+)} $line foo var value] { - set cmd "global $var; set $var $value" - eval $cmd - } - if [regexp {([0-9A-Za-z_]+)="([^"]*)"} $line foo var value] { - set cmd "global $var; set $var \"$value\"" - eval $cmd - } - } - close $file1 - update_choices - update_mainmenu -} -proc write_comment { file1 file2 text } { - puts $file1 "" - puts $file1 "#" - puts $file1 "# $text" - puts $file1 "#" - puts $file2 "/*" - puts $file2 " * $text" - puts $file2 " */" -} - -proc effective_dep { deplist } { - global CONFIG_MODULES - set depend 1 - foreach i $deplist { - if {$i == 0} then {set depend 0} - if {$i == 2 && $depend == 1} then {set depend 2} - } - if {$depend == 2 && $CONFIG_MODULES == 0} then {set depend 0} - return $depend -} - -proc sync_tristate { var dep } { - global CONFIG_MODULES - if {$dep == 0 && ($var == 1 || $var == 2)} then { - set var 0 - } elseif {$dep == 2 && $var == 1} then { - set var 2 - } elseif {$var == 2 && $CONFIG_MODULES == 0} then { - if {$dep == 1} then {set var 1} else {set var 0} - } - return $var -} - -proc sync_bool { var dep modset } { - set var [sync_tristate $var $dep] - if {$dep == 2 && $var == 2} then { - set var $modset - } - return $var -} - -proc write_tristate { file1 file2 varname variable deplist modset } { - set variable [sync_tristate $variable [effective_dep $deplist]] - if { $variable == 2 } \ - then { set variable $modset } - if { $variable == 1 } \ - then { puts $file1 "$varname=y"; \ - puts $file2 "#define $varname 1" } \ - elseif { $variable == 2 } \ - then { puts $file1 "$varname=m"; \ - puts $file2 "#undef $varname"; \ - puts $file2 "#define ${varname}_MODULE 1" } \ - elseif { $variable == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { \ - puts stdout "ERROR - Attempting to write value for unconfigured variable ($varname)." \ - } -} - -proc write_int { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=$variable"; \ - puts $file2 "#define $varname ($variable)"; \ - } -} - -proc write_hex { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=$variable"; \ - puts -nonewline $file2 "#define $varname "; \ - puts $file2 [exec echo $variable | sed s/^0\[xX\]//]; \ - } -} - -proc write_string { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=\"$variable\""; \ - puts $file2 "#define $varname \"$variable\""; \ - } -} - -proc option_name {w mnum line text helpidx} { - button $w.x$line.l -text "$text" -relief groove -anchor w - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] - button $w.x$line.help -text "Help" -relief raised \ - -command "dohelp .dohelp $helpidx .menu$mnum" - pack $w.x$line.help -side right -fill y - pack $w.x$line.l -side right -fill both -expand on -} - -proc toggle_switch2 {w mnum line text variable} { - frame $w.x$line -relief sunken - radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \ - -relief groove -width 2 -command "update_active" -# radiobutton $w.x$line.m -text "-" -variable $variable -value 2 \ -# -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \ - -relief groove -width 2 -command "update_active" - - option_name $w $mnum $line $text $variable - - pack $w.x$line.n $w.x$line.y -side right -fill y -} - -proc toggle_switch3 {w mnum line text variable} { - frame $w.x$line -relief sunken - radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \ - -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.m -text "m" -variable $variable -value 2 \ - -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \ - -relief groove -width 2 -command "update_active" - - option_name $w $mnum $line $text $variable - - global CONFIG_MODULES - if {($CONFIG_MODULES == 0)} then { - $w.x$line.m configure -state disabled - } - pack $w.x$line.n $w.x$line.m $w.x$line.y -side right -fill y -} - -proc bool {w mnum line text variable} { - toggle_switch2 $w $mnum $line $text $variable -# $w.x$line.m configure -state disabled - pack $w.x$line -anchor w -fill both -expand on -} - -proc tristate {w mnum line text variable } { - toggle_switch3 $w $mnum $line $text $variable - pack $w.x$line -anchor w -fill both -expand on -} - -proc dep_tristate {w mnum line text variable } { - tristate $w $mnum $line $text $variable -} - -proc dep_bool {w mnum line text variable } { - bool $w $mnum $line $text $variable -} - -proc int { w mnum line text variable } { - frame $w.x$line - entry $w.x$line.x -width 11 -relief sunken -borderwidth 2 \ - -textvariable $variable - option_name $w $mnum $line $text $variable - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc hex { w mnum line text variable } { - int $w $mnum $line $text $variable -} - -proc istring { w mnum line text variable } { - frame $w.x$line - entry $w.x$line.x -width 18 -relief sunken -borderwidth 2 \ - -textvariable $variable - option_name $w $mnum $line $text $variable - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc minimenu { w mnum line text variable helpidx } { - frame $w.x$line - menubutton $w.x$line.x -textvariable $variable -menu \ - $w.x$line.x.menu -relief raised \ - -anchor w - option_name $w $mnum $line $text $helpidx - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc menusplit {w m n} { - if { $n > 2 } then { - update idletasks - set menuoptsize [expr [$m yposition 2] - [$m yposition 1]] - set maxsize [winfo screenheight $w] - set splitpoint [expr $maxsize * 4 / 5 / $menuoptsize - 1] - for {set i [expr $splitpoint + 1]} {$i <= $n} {incr i $splitpoint} { - $m entryconfigure $i -columnbreak 1 - } - } -} - -proc menutitle {text menu w} { - wm title $w "$text" -} - -proc submenu { w mnum line text subnum } { - frame $w.x$line - button $w.x$line.l -text "" -width 9 -relief groove - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] -state disabled - button $w.x$line.m -text "$text" -relief raised -anchor w \ - -command "catch {destroy .menu$subnum}; menu$subnum .menu$subnum \"$text\"" - pack $w.x$line.l -side left -fill both - pack $w.x$line.m -anchor w -side right -fill both -expand on - pack $w.x$line -anchor w -fill both -expand on -} - -proc comment {w mnum line text } { - frame $w.x$line - button $w.x$line.l -text "" -width 15 -relief groove - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] -state disabled - button $w.x$line.m -text "$text" -relief groove -anchor w - $w.x$line.m configure -activefore [cget $w.x$line.m -fg] \ - -activeback [cget $w.x$line.m -bg] - pack $w.x$line.l -side left -fill both - pack $w.x$line.m -anchor w -side right -fill both -expand on - pack $w.x$line -anchor w -fill both -expand on -} - -proc readhelp {tag fn} { - set message "" - set b 0 - if { [file readable $fn] == 1} then { - set fhandle [open $fn r] - while {[gets $fhandle inline] >= 0} { - if { $b == 0 } { - if { [regexp $tag $inline ] } { - set b 1 - set message "$inline:\n" - } - } else { - if { [regexp {^[^ \t]} $inline]} { - break - } - set message "$message\n$inline" - } - } - close $fhandle - } - return $message -} - -proc dohelp {w var parent} { - catch {destroy $w} - toplevel $w -class Dialog - - set filefound 0 - set found 0 - set lineno 0 - - if { [file readable config.help] == 1} then { - set filefound 1 - # First escape sed regexp special characters in var: - set var [exec echo "$var" | sed s/\[\]\[\/.^$*\]/\\\\&/g] - # Now pick out right help text: - set message [readhelp $var config.help] - set found [expr [string length "$message"] > 0] - } - - frame $w.f1 - pack $w.f1 -fill both -expand on - - # Do the OK button - # - set oldFocus [focus] - frame $w.f2 - button $w.f2.ok -text "OK" \ - -width 10 -command "destroy $w; catch {focus $oldFocus}" - pack $w.f2.ok -side bottom -pady 6 -anchor n - pack $w.f2 -side bottom -padx 10 -anchor s - - scrollbar $w.f1.vscroll -command "$w.f1.canvas yview" - pack $w.f1.vscroll -side right -fill y - - canvas $w.f1.canvas -relief flat -borderwidth 0 \ - -yscrollcommand "$w.f1.vscroll set" - frame $w.f1.f - pack $w.f1.canvas -side right -fill y -expand on - - if { $found == 0 } then { - if { $filefound == 0 } then { - message $w.f1.f.m -width 750 -aspect 300 -relief flat -text \ - "No help available - unable to open file config.help." - } else { - message $w.f1.f.m -width 400 -aspect 300 -relief flat -text \ - "No help available for $var" - } - label $w.f1.bm -bitmap error - wm title $w "RTFM" - } else { - text $w.f1.f.m -width 73 -relief flat -wrap word - $w.f1.f.m insert 0.0 $message - $w.f1.f.m conf -state disabled -height [$w.f1.f.m index end] - - label $w.f1.bm -bitmap info - wm title $w "Configuration help" - } - pack $w.f1.f.m -side left - pack $w.f1.bm $w.f1.f -side left -padx 10 - - focus $w - set winx [expr [winfo x $parent]+20] - set winy [expr [winfo y $parent]+20] - wm geometry $w +$winx+$winy - set sizok [expr [winfo reqheight $w.f2.ok] + 12] - set maxy [expr [winfo screenheight .] * 3 / 4] - set canvtotal [winfo reqheight $w.f1.f.m] - if [expr $sizok + $canvtotal < $maxy] { - set sizy $canvtotal - } else { - set sizy [expr $maxy - $sizok] - } - $w.f1.canvas configure -height $sizy -width [winfo reqwidth $w.f1.f.m] \ - -scrollregion "0 0 [winfo reqwidth $w.f1.f.m] \ - [winfo reqheight $w.f1.f.m]" - $w.f1.canvas create window 0 0 -anchor nw -window $w.f1.f - update idletasks - - set maxy [winfo screenheight .] - if [expr $sizok + $canvtotal < $maxy] { - set sizy [expr $sizok + $canvtotal] - } else { - set sizy $maxy - } - wm maxsize $w [winfo width $w] $sizy -} - -bind all { catch {exec cp -f .config .config.old}; \ - writeconfig .config config.h; wrapup .wrap } - -proc wrapup {w } { - catch {destroy $w} - toplevel $w -class Dialog - - global CONFIG_MODVERSIONS; vfix CONFIG_MODVERSIONS - message $w.m -width 460 -aspect 300 -relief raised -text \ - "End of design configuration. " - label $w.bm -bitmap info - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "LEON build instructions" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" \ - -width 10 -command "exit 2" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - bind $w "exit 2" - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - -} - -proc unregister_active {num} { - global active_menus - set index [lsearch -exact $active_menus $num] - if {$index != -1} then {set active_menus [lreplace $active_menus $index $index]} -} - -proc update_active {} { - global active_menus total_menus - set max 0 - if {[llength $active_menus] > 0} then { - set max [lindex $active_menus end] - update_define [toplevel_menu [lindex $active_menus 0]] $max 0 - } - foreach i $active_menus { - if {[winfo exists .menu$i] == 0} then { - unregister_active $i - } else { - update_menu$i - } - } - update_define [expr $max + 1] $total_menus 1 - update_mainmenu -} - -proc configure_entry {w option items} { - foreach i $items { - $w.$i configure -state $option - } -} - -proc validate_int {name val default} { - if {([exec echo $val | sed s/^-//g | tr -d \[:digit:\] ] != "")} then { - global $name; set $name $default - } -} - -proc validate_hex {name val default} { - if {([exec echo $val | tr -d \[:xdigit:\] ] != "")} then { - global $name; set $name $default - } -} - -proc update_define {first last allow_update} { - for {set i $first} {$i <= $last} {incr i} { - update_define_menu$i - if {$allow_update == 1} then update - } -} - -# -# Next set up the particulars for the top level menu, and define a few -# buttons which we will stick down at the bottom. -# - -frame .f0 -frame .f0.left -frame .f0.middle -frame .f0.right - -set active_menus [list] -set processed_top_level 0 -set ARCH sparc -set menus_per_column 4 -set total_menus 24 - -proc toplevel_menu {num} { - if {$num == 4} then {return 3} - if {$num == 5} then {return 3} - if {$num == 6} then {return 3} - if {$num == 7} then {return 3} - if {$num == 8} then {return 3} - if {$num == 9} then {return 3} - if {$num == 10} then {return 3} - if {$num == 14} then {return 13} - if {$num == 15} then {return 14} - if {$num == 16} then {return 14} - if {$num == 17} then {return 14} - if {$num == 18} then {return 13} - if {$num == 19} then {return 13} - if {$num == 20} then {return 13} - if {$num == 21} then {return 13} - if {$num == 22} then {return 13} - if {$num == 23} then {return 13} - return $num -} - -mainmenu_name "LEON3MP Design Configuration" -menu_option menu1 1 "Synthesis " -proc menu1 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 1} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 1]] - message $w.m -width 400 -aspect 300 -text \ - "Synthesis " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Synthesis " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 1; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu2 .menu2 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu0 .menu0 \"$title\"" - $w.f.prev configure -state disabled - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - global tmpvar_0 - minimenu $w.config.f 1 0 "Target technology " tmpvar_0 CONFIG_SYN_INFERRED - menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Target technology \"" - $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_0 -value "Inferred" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-Stratix" -variable tmpvar_0 -value "Altera-Stratix" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixII" -variable tmpvar_0 -value "Altera-StratixII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixIII" -variable tmpvar_0 -value "Altera-StratixIII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-CycloneIII" -variable tmpvar_0 -value "Altera-CycloneIII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-Others" -variable tmpvar_0 -value "Altera-Others" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator" -variable tmpvar_0 -value "Actel-Axcelerator" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic" -variable tmpvar_0 -value "Actel-Proasic" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-ProasicPlus" -variable tmpvar_0 -value "Actel-ProasicPlus" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic3" -variable tmpvar_0 -value "Actel-Proasic3" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT025CRH" -variable tmpvar_0 -value "Aeroflex-UT025CRH" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18" -variable tmpvar_0 -value "Atmel-ATC18" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18RHA" -variable tmpvar_0 -value "Atmel-ATC18RHA" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Custom1" -variable tmpvar_0 -value "Custom1" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "eASIC90" -variable tmpvar_0 -value "eASIC90" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "IHP25" -variable tmpvar_0 -value "IHP25" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "IHP25RH" -variable tmpvar_0 -value "IHP25RH" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Lattice-EC/ECP/XP" -variable tmpvar_0 -value "Lattice-EC/ECP/XP" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Quicklogic-Eclipse" -variable tmpvar_0 -value "Quicklogic-Eclipse" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Peregrine" -variable tmpvar_0 -value "Peregrine" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T" -variable tmpvar_0 -value "RH-LIB18T" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_0 -value "RH-UMC" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "SMIC130" -variable tmpvar_0 -value "SMIC130" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan2" -variable tmpvar_0 -value "Xilinx-Spartan2" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3" -variable tmpvar_0 -value "Xilinx-Spartan3" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3E" -variable tmpvar_0 -value "Xilinx-Spartan3E" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex" -variable tmpvar_0 -value "Xilinx-Virtex" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-VirtexE" -variable tmpvar_0 -value "Xilinx-VirtexE" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex2" -variable tmpvar_0 -value "Xilinx-Virtex2" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex4" -variable tmpvar_0 -value "Xilinx-Virtex4" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex5" -variable tmpvar_0 -value "Xilinx-Virtex5" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "UMC180" -variable tmpvar_0 -value "UMC180" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "TSMC90" -variable tmpvar_0 -value "TSMC90" -command "update_active" - menusplit $w $w.config.f.x0.x.menu 33 - global tmpvar_1 - minimenu $w.config.f 1 1 "Memory Library " tmpvar_1 CONFIG_MEM_INFERRED - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Memory Library \"" - $w.config.f.x1.x.menu add radiobutton -label "Inferred" -variable tmpvar_1 -value "Inferred" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "UMC18" -variable tmpvar_1 -value "UMC18" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_1 -value "RH-UMC" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Artisan" -variable tmpvar_1 -value "Artisan" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Custom1" -variable tmpvar_1 -value "Custom1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Virage" -variable tmpvar_1 -value "Virage" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Virage-TSMC90" -variable tmpvar_1 -value "Virage-TSMC90" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 7 - bool $w.config.f 1 2 "Infer RAM" CONFIG_SYN_INFER_RAM - bool $w.config.f 1 3 "Infer pads" CONFIG_SYN_INFER_PADS - bool $w.config.f 1 4 "Disable asynchronous reset" CONFIG_SYN_NO_ASYNC - bool $w.config.f 1 5 "Enable scan support " CONFIG_SYN_SCAN - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu1 {} { - global CONFIG_SYN_INFERRED - global CONFIG_SYN_CUSTOM1 - global CONFIG_SYN_ATC18 - global CONFIG_SYN_TSMC90 - global CONFIG_SYN_UMC - global CONFIG_SYN_RHUMC - global CONFIG_SYN_ARTISAN - if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then {configure_entry .menu1.config.f.x1 normal {x l}} else {configure_entry .menu1.config.f.x1 disabled {x l}} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then { - configure_entry .menu1.config.f.x2 normal {n l y}} else {configure_entry .menu1.config.f.x2 disabled {y n l}} - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then { - configure_entry .menu1.config.f.x3 normal {n l y}} else {configure_entry .menu1.config.f.x3 disabled {y n l}} -} - - -proc update_define_menu1 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_0 - global CONFIG_SYN_INFERRED - if {$tmpvar_0 == "Inferred"} then {set CONFIG_SYN_INFERRED 1} else {set CONFIG_SYN_INFERRED 0} - global CONFIG_SYN_STRATIX - if {$tmpvar_0 == "Altera-Stratix"} then {set CONFIG_SYN_STRATIX 1} else {set CONFIG_SYN_STRATIX 0} - global CONFIG_SYN_STRATIXII - if {$tmpvar_0 == "Altera-StratixII"} then {set CONFIG_SYN_STRATIXII 1} else {set CONFIG_SYN_STRATIXII 0} - global CONFIG_SYN_STRATIXIII - if {$tmpvar_0 == "Altera-StratixIII"} then {set CONFIG_SYN_STRATIXIII 1} else {set CONFIG_SYN_STRATIXIII 0} - global CONFIG_SYN_CYCLONEIII - if {$tmpvar_0 == "Altera-CycloneIII"} then {set CONFIG_SYN_CYCLONEIII 1} else {set CONFIG_SYN_CYCLONEIII 0} - global CONFIG_SYN_ALTERA - if {$tmpvar_0 == "Altera-Others"} then {set CONFIG_SYN_ALTERA 1} else {set CONFIG_SYN_ALTERA 0} - global CONFIG_SYN_AXCEL - if {$tmpvar_0 == "Actel-Axcelerator"} then {set CONFIG_SYN_AXCEL 1} else {set CONFIG_SYN_AXCEL 0} - global CONFIG_SYN_PROASIC - if {$tmpvar_0 == "Actel-Proasic"} then {set CONFIG_SYN_PROASIC 1} else {set CONFIG_SYN_PROASIC 0} - global CONFIG_SYN_PROASICPLUS - if {$tmpvar_0 == "Actel-ProasicPlus"} then {set CONFIG_SYN_PROASICPLUS 1} else {set CONFIG_SYN_PROASICPLUS 0} - global CONFIG_SYN_PROASIC3 - if {$tmpvar_0 == "Actel-Proasic3"} then {set CONFIG_SYN_PROASIC3 1} else {set CONFIG_SYN_PROASIC3 0} - global CONFIG_SYN_UT025CRH - if {$tmpvar_0 == "Aeroflex-UT025CRH"} then {set CONFIG_SYN_UT025CRH 1} else {set CONFIG_SYN_UT025CRH 0} - global CONFIG_SYN_ATC18 - if {$tmpvar_0 == "Atmel-ATC18"} then {set CONFIG_SYN_ATC18 1} else {set CONFIG_SYN_ATC18 0} - global CONFIG_SYN_ATC18RHA - if {$tmpvar_0 == "Atmel-ATC18RHA"} then {set CONFIG_SYN_ATC18RHA 1} else {set CONFIG_SYN_ATC18RHA 0} - global CONFIG_SYN_CUSTOM1 - if {$tmpvar_0 == "Custom1"} then {set CONFIG_SYN_CUSTOM1 1} else {set CONFIG_SYN_CUSTOM1 0} - global CONFIG_SYN_EASIC90 - if {$tmpvar_0 == "eASIC90"} then {set CONFIG_SYN_EASIC90 1} else {set CONFIG_SYN_EASIC90 0} - global CONFIG_SYN_IHP25 - if {$tmpvar_0 == "IHP25"} then {set CONFIG_SYN_IHP25 1} else {set CONFIG_SYN_IHP25 0} - global CONFIG_SYN_IHP25RH - if {$tmpvar_0 == "IHP25RH"} then {set CONFIG_SYN_IHP25RH 1} else {set CONFIG_SYN_IHP25RH 0} - global CONFIG_SYN_LATTICE - if {$tmpvar_0 == "Lattice-EC/ECP/XP"} then {set CONFIG_SYN_LATTICE 1} else {set CONFIG_SYN_LATTICE 0} - global CONFIG_SYN_ECLIPSE - if {$tmpvar_0 == "Quicklogic-Eclipse"} then {set CONFIG_SYN_ECLIPSE 1} else {set CONFIG_SYN_ECLIPSE 0} - global CONFIG_SYN_PEREGRINE - if {$tmpvar_0 == "Peregrine"} then {set CONFIG_SYN_PEREGRINE 1} else {set CONFIG_SYN_PEREGRINE 0} - global CONFIG_SYN_RH_LIB18T - if {$tmpvar_0 == "RH-LIB18T"} then {set CONFIG_SYN_RH_LIB18T 1} else {set CONFIG_SYN_RH_LIB18T 0} - global CONFIG_SYN_RHUMC - if {$tmpvar_0 == "RH-UMC"} then {set CONFIG_SYN_RHUMC 1} else {set CONFIG_SYN_RHUMC 0} - global CONFIG_SYN_SMIC13 - if {$tmpvar_0 == "SMIC130"} then {set CONFIG_SYN_SMIC13 1} else {set CONFIG_SYN_SMIC13 0} - global CONFIG_SYN_SPARTAN2 - if {$tmpvar_0 == "Xilinx-Spartan2"} then {set CONFIG_SYN_SPARTAN2 1} else {set CONFIG_SYN_SPARTAN2 0} - global CONFIG_SYN_SPARTAN3 - if {$tmpvar_0 == "Xilinx-Spartan3"} then {set CONFIG_SYN_SPARTAN3 1} else {set CONFIG_SYN_SPARTAN3 0} - global CONFIG_SYN_SPARTAN3E - if {$tmpvar_0 == "Xilinx-Spartan3E"} then {set CONFIG_SYN_SPARTAN3E 1} else {set CONFIG_SYN_SPARTAN3E 0} - global CONFIG_SYN_VIRTEX - if {$tmpvar_0 == "Xilinx-Virtex"} then {set CONFIG_SYN_VIRTEX 1} else {set CONFIG_SYN_VIRTEX 0} - global CONFIG_SYN_VIRTEXE - if {$tmpvar_0 == "Xilinx-VirtexE"} then {set CONFIG_SYN_VIRTEXE 1} else {set CONFIG_SYN_VIRTEXE 0} - global CONFIG_SYN_VIRTEX2 - if {$tmpvar_0 == "Xilinx-Virtex2"} then {set CONFIG_SYN_VIRTEX2 1} else {set CONFIG_SYN_VIRTEX2 0} - global CONFIG_SYN_VIRTEX4 - if {$tmpvar_0 == "Xilinx-Virtex4"} then {set CONFIG_SYN_VIRTEX4 1} else {set CONFIG_SYN_VIRTEX4 0} - global CONFIG_SYN_VIRTEX5 - if {$tmpvar_0 == "Xilinx-Virtex5"} then {set CONFIG_SYN_VIRTEX5 1} else {set CONFIG_SYN_VIRTEX5 0} - global CONFIG_SYN_UMC - if {$tmpvar_0 == "UMC180"} then {set CONFIG_SYN_UMC 1} else {set CONFIG_SYN_UMC 0} - global CONFIG_SYN_TSMC90 - if {$tmpvar_0 == "TSMC90"} then {set CONFIG_SYN_TSMC90 1} else {set CONFIG_SYN_TSMC90 0} - global tmpvar_1 - global CONFIG_MEM_INFERRED - if {$tmpvar_1 == "Inferred"} then {set CONFIG_MEM_INFERRED 1} else {set CONFIG_MEM_INFERRED 0} - global CONFIG_MEM_UMC - if {$tmpvar_1 == "UMC18"} then {set CONFIG_MEM_UMC 1} else {set CONFIG_MEM_UMC 0} - global CONFIG_MEM_RHUMC - if {$tmpvar_1 == "RH-UMC"} then {set CONFIG_MEM_RHUMC 1} else {set CONFIG_MEM_RHUMC 0} - global CONFIG_MEM_ARTISAN - if {$tmpvar_1 == "Artisan"} then {set CONFIG_MEM_ARTISAN 1} else {set CONFIG_MEM_ARTISAN 0} - global CONFIG_MEM_CUSTOM1 - if {$tmpvar_1 == "Custom1"} then {set CONFIG_MEM_CUSTOM1 1} else {set CONFIG_MEM_CUSTOM1 0} - global CONFIG_MEM_VIRAGE - if {$tmpvar_1 == "Virage"} then {set CONFIG_MEM_VIRAGE 1} else {set CONFIG_MEM_VIRAGE 0} - global CONFIG_MEM_VIRAGE90 - if {$tmpvar_1 == "Virage-TSMC90"} then {set CONFIG_MEM_VIRAGE90 1} else {set CONFIG_MEM_VIRAGE90 0} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then { - set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM&15]} else {set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM|16]} - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then { - set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS&15]} else {set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS|16]} -} - - -menu_option menu2 2 "Clock generation" -proc menu2 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 2} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 2]] - message $w.m -width 400 -aspect 300 -text \ - "Clock generation" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Clock generation" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 2; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu3 .menu3 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - global tmpvar_2 - minimenu $w.config.f 2 0 "Clock generator " tmpvar_2 CONFIG_CLK_INFERRED - menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Clock generator \"" - $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_2 -value "Inferred" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-HCLKBUF" -variable tmpvar_2 -value "Actel-HCLKBUF" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-ALTPLL" -variable tmpvar_2 -value "Altera-ALTPLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Lattice-EXPLL" -variable tmpvar_2 -value "Lattice-EXPLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Proasic3-PLLL" -variable tmpvar_2 -value "Proasic3-PLLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T-PLL" -variable tmpvar_2 -value "RH-LIB18T-PLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "DARE-PLL" -variable tmpvar_2 -value "DARE-PLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-CLKDLL" -variable tmpvar_2 -value "Xilinx-CLKDLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-DCM" -variable tmpvar_2 -value "Xilinx-DCM" -command "update_active" - menusplit $w $w.config.f.x0.x.menu 9 - int $w.config.f 2 1 "Clock multiplication factor (2 - 32)" CONFIG_CLK_MUL - int $w.config.f 2 2 "Clock division factor (2 - 32)" CONFIG_CLK_DIV - int $w.config.f 2 3 "Outout division factor (2 - 32)" CONFIG_OCLK_DIV - bool $w.config.f 2 4 "Enable Xilinx CLKDLL for PCI clock" CONFIG_PCI_CLKDLL - bool $w.config.f 2 5 "Disable external feedback for SDRAM clock" CONFIG_CLK_NOFB - bool $w.config.f 2 6 "Use PCI clock as system clock" CONFIG_PCI_SYSCLK - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu2 {} { - global CONFIG_CLK_DCM - global CONFIG_CLK_ALTDLL - global CONFIG_CLK_LATDLL - global CONFIG_CLK_PRO3PLL - global CONFIG_CLK_CLKDLL - global CONFIG_CLK_LIB18T - global CONFIG_CLK_MUL - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x1.l configure -state normal; } else {.menu2.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x1.l configure -state disabled} - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x2.l configure -state normal; } else {.menu2.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x2.l configure -state disabled} - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {.menu2.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x3.l configure -state normal; } else {.menu2.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x3.l configure -state disabled} - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then { - configure_entry .menu2.config.f.x4 normal {n l y}} else {configure_entry .menu2.config.f.x4 disabled {y n l}} - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then { - configure_entry .menu2.config.f.x5 normal {n l y}} else {configure_entry .menu2.config.f.x5 disabled {y n l}} - global CONFIG_PCI_ENABLE - global CONFIG_PCI_SYSCLK - if {($CONFIG_PCI_ENABLE != 1)} then { - configure_entry .menu2.config.f.x6 normal {n l y}} else {configure_entry .menu2.config.f.x6 disabled {y n l}} -} - - -proc update_define_menu2 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_2 - global CONFIG_CLK_INFERRED - if {$tmpvar_2 == "Inferred"} then {set CONFIG_CLK_INFERRED 1} else {set CONFIG_CLK_INFERRED 0} - global CONFIG_CLK_HCLKBUF - if {$tmpvar_2 == "Actel-HCLKBUF"} then {set CONFIG_CLK_HCLKBUF 1} else {set CONFIG_CLK_HCLKBUF 0} - global CONFIG_CLK_ALTDLL - if {$tmpvar_2 == "Altera-ALTPLL"} then {set CONFIG_CLK_ALTDLL 1} else {set CONFIG_CLK_ALTDLL 0} - global CONFIG_CLK_LATDLL - if {$tmpvar_2 == "Lattice-EXPLL"} then {set CONFIG_CLK_LATDLL 1} else {set CONFIG_CLK_LATDLL 0} - global CONFIG_CLK_PRO3PLL - if {$tmpvar_2 == "Proasic3-PLLL"} then {set CONFIG_CLK_PRO3PLL 1} else {set CONFIG_CLK_PRO3PLL 0} - global CONFIG_CLK_LIB18T - if {$tmpvar_2 == "RH-LIB18T-PLL"} then {set CONFIG_CLK_LIB18T 1} else {set CONFIG_CLK_LIB18T 0} - global CONFIG_CLK_RHUMC - if {$tmpvar_2 == "DARE-PLL"} then {set CONFIG_CLK_RHUMC 1} else {set CONFIG_CLK_RHUMC 0} - global CONFIG_CLK_CLKDLL - if {$tmpvar_2 == "Xilinx-CLKDLL"} then {set CONFIG_CLK_CLKDLL 1} else {set CONFIG_CLK_CLKDLL 0} - global CONFIG_CLK_DCM - if {$tmpvar_2 == "Xilinx-DCM"} then {set CONFIG_CLK_DCM 1} else {set CONFIG_CLK_DCM 0} - global CONFIG_CLK_MUL - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_MUL "$CONFIG_CLK_MUL" 2} - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_DIV "$CONFIG_CLK_DIV" 2} - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {validate_int CONFIG_OCLK_DIV "$CONFIG_OCLK_DIV" 2} - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then { - set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL&15]} else {set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL|16]} - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then { - set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB&15]} else {set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB|16]} - global CONFIG_PCI_ENABLE - global CONFIG_PCI_SYSCLK - if {($CONFIG_PCI_ENABLE != 1)} then { - set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK&15]} else {set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK|16]} -} - - -menu_option menu3 3 "Processor " -proc menu3 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 3} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 3]] - message $w.m -width 400 -aspect 300 -text \ - "Processor " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Processor " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 3; break" - set nextscript "catch {focus $oldFocus}; menu4 .menu4 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 3 0 "Enable LEON3 SPARC V8 Processor" CONFIG_LEON3 - int $w.config.f 3 1 "Number of processors" CONFIG_PROC_NUM - submenu $w.config.f 3 2 "Integer unit " 4 - submenu $w.config.f 3 3 "Floating-point unit" 5 - submenu $w.config.f 3 4 "Cache system" 6 - submenu $w.config.f 3 5 "MMU" 7 - submenu $w.config.f 3 6 "Debug Support Unit " 8 - submenu $w.config.f 3 7 "Fault-tolerance " 9 - submenu $w.config.f 3 8 "VHDL debug settings " 10 - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu3 {} { - global CONFIG_LEON3 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {.menu3.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu3.config.f.x1.l configure -state normal; } else {.menu3.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu3.config.f.x1.l configure -state disabled} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x2 normal {m}} else {configure_entry .menu3.config.f.x2 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x3 normal {m}} else {configure_entry .menu3.config.f.x3 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x4 normal {m}} else {configure_entry .menu3.config.f.x4 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x5 normal {m}} else {configure_entry .menu3.config.f.x5 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x6 normal {m}} else {configure_entry .menu3.config.f.x6 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x7 normal {m}} else {configure_entry .menu3.config.f.x7 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x8 normal {m}} else {configure_entry .menu3.config.f.x8 disabled {m}} -} - - -proc update_define_menu3 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_PROC_NUM "$CONFIG_PROC_NUM" 1} -} - - -proc menu4 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 4} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 4]] - message $w.m -width 400 -aspect 300 -text \ - "Integer unit " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Integer unit " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 4; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu5 .menu5 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - int $w.config.f 4 0 "SPARC register windows" CONFIG_IU_NWINDOWS - bool $w.config.f 4 1 "SPARC V8 MUL/DIV instructions" CONFIG_IU_V8MULDIV - global tmpvar_3 - minimenu $w.config.f 4 2 "Hardware multiplier latency" tmpvar_3 CONFIG_IU_MUL_LATENCY_2 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Hardware multiplier latency\"" - $w.config.f.x2.x.menu add radiobutton -label "2-cycles" -variable tmpvar_3 -value "2-cycles" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4-cycles" -variable tmpvar_3 -value "4-cycles" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "5-cycles" -variable tmpvar_3 -value "5-cycles" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 3 - bool $w.config.f 4 3 "SPARC V8e SMAC/UMAC instructions " CONFIG_IU_MUL_MAC - bool $w.config.f 4 4 "Single-vector trapping" CONFIG_IU_SVT - int $w.config.f 4 5 "Load delay" CONFIG_IU_LDELAY - int $w.config.f 4 6 "Hardware watchpoints" CONFIG_IU_WATCHPOINTS - bool $w.config.f 4 7 "Enable power-down mode " CONFIG_PWD - hex $w.config.f 4 8 " Reset start address (addr\[31:12\]) " CONFIG_IU_RSTADDR - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu4 {} { - global CONFIG_LEON3 - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x0.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x0.l configure -state normal; } else {.menu4.config.f.x0.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x0.l configure -state disabled} - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x1 normal {n l y}} else {configure_entry .menu4.config.f.x1 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {configure_entry .menu4.config.f.x2 normal {x l}} else {configure_entry .menu4.config.f.x2 disabled {x l}} - global CONFIG_IU_MUL_LATENCY_4 - global CONFIG_IU_MUL_LATENCY_5 - global CONFIG_IU_MUL_MAC - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then { - configure_entry .menu4.config.f.x3 normal {n l y}} else {configure_entry .menu4.config.f.x3 disabled {y n l}} - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x4 normal {n l y}} else {configure_entry .menu4.config.f.x4 disabled {y n l}} - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x5.l configure -state normal; } else {.menu4.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x5.l configure -state disabled} - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x6.l configure -state normal; } else {.menu4.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x6.l configure -state disabled} - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x7 normal {n l y}} else {configure_entry .menu4.config.f.x7 disabled {y n l}} - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x8.l configure -state normal; } else {.menu4.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x8.l configure -state disabled} -} - - -proc update_define_menu4 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_NWINDOWS "$CONFIG_IU_NWINDOWS" 8} - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV&15]} else {set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV|16]} - global tmpvar_3 - global CONFIG_IU_MUL_LATENCY_2 - if {$tmpvar_3 == "2-cycles"} then {set CONFIG_IU_MUL_LATENCY_2 1} else {set CONFIG_IU_MUL_LATENCY_2 0} - global CONFIG_IU_MUL_LATENCY_4 - if {$tmpvar_3 == "4-cycles"} then {set CONFIG_IU_MUL_LATENCY_4 1} else {set CONFIG_IU_MUL_LATENCY_4 0} - global CONFIG_IU_MUL_LATENCY_5 - if {$tmpvar_3 == "5-cycles"} then {set CONFIG_IU_MUL_LATENCY_5 1} else {set CONFIG_IU_MUL_LATENCY_5 0} - global CONFIG_IU_MUL_MAC - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then { - set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC&15]} else {set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC|16]} - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_SVT [expr $CONFIG_IU_SVT&15]} else {set CONFIG_IU_SVT [expr $CONFIG_IU_SVT|16]} - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_LDELAY "$CONFIG_IU_LDELAY" 1} - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_WATCHPOINTS "$CONFIG_IU_WATCHPOINTS" 0} - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_PWD [expr $CONFIG_PWD&15]} else {set CONFIG_PWD [expr $CONFIG_PWD|16]} - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {validate_hex CONFIG_IU_RSTADDR "$CONFIG_IU_RSTADDR" 00000} -} - - -proc menu5 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 5} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 5]] - message $w.m -width 400 -aspect 300 -text \ - "Floating-point unit" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Floating-point unit" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 5; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu6 .menu6 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 5 0 "Enable FPU " CONFIG_FPU_ENABLE - global tmpvar_4 - minimenu $w.config.f 5 1 "FPU core" tmpvar_4 CONFIG_FPU_GRFPU - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"FPU core\"" - $w.config.f.x1.x.menu add radiobutton -label "GRFPU" -variable tmpvar_4 -value "GRFPU" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "GRFPU-LITE" -variable tmpvar_4 -value "GRFPU-LITE" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Meiko" -variable tmpvar_4 -value "Meiko" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 3 - global tmpvar_5 - minimenu $w.config.f 5 2 "GRFPU multiplier" tmpvar_5 CONFIG_FPU_GRFPU_INFMUL - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"GRFPU multiplier\"" - $w.config.f.x2.x.menu add radiobutton -label "Inferred" -variable tmpvar_5 -value "Inferred" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "DW" -variable tmpvar_5 -value "DW" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "ModGen" -variable tmpvar_5 -value "ModGen" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 3 - global tmpvar_6 - minimenu $w.config.f 5 3 "GRFPU-LITE controller" tmpvar_6 CONFIG_FPU_GRFPC0 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"GRFPU-LITE controller\"" - $w.config.f.x3.x.menu add radiobutton -label "Simple" -variable tmpvar_6 -value "Simple" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "Data-forwarding" -variable tmpvar_6 -value "Data-forwarding" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "Non-blocking" -variable tmpvar_6 -value "Non-blocking" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 3 - bool $w.config.f 5 4 "Use VHDL netlist " CONFIG_FPU_NETLIST - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu5 {} { - global CONFIG_LEON3 - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu5.config.f.x0 normal {n l y}} else {configure_entry .menu5.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {configure_entry .menu5.config.f.x1 normal {x l}} else {configure_entry .menu5.config.f.x1 disabled {x l}} - global CONFIG_FPU_GRFPU - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then {configure_entry .menu5.config.f.x2 normal {x l}} else {configure_entry .menu5.config.f.x2 disabled {x l}} - global CONFIG_FPU_GRFPULITE - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then {configure_entry .menu5.config.f.x3 normal {x l}} else {configure_entry .menu5.config.f.x3 disabled {x l}} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - configure_entry .menu5.config.f.x4 normal {n l y}} else {configure_entry .menu5.config.f.x4 disabled {y n l}} -} - - -proc update_define_menu5 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE&15]} else {set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE|16]} - global tmpvar_4 - global CONFIG_FPU_GRFPU - if {$tmpvar_4 == "GRFPU"} then {set CONFIG_FPU_GRFPU 1} else {set CONFIG_FPU_GRFPU 0} - global CONFIG_FPU_GRFPULITE - if {$tmpvar_4 == "GRFPU-LITE"} then {set CONFIG_FPU_GRFPULITE 1} else {set CONFIG_FPU_GRFPULITE 0} - global CONFIG_FPU_MEIKO - if {$tmpvar_4 == "Meiko"} then {set CONFIG_FPU_MEIKO 1} else {set CONFIG_FPU_MEIKO 0} - global tmpvar_5 - global CONFIG_FPU_GRFPU_INFMUL - if {$tmpvar_5 == "Inferred"} then {set CONFIG_FPU_GRFPU_INFMUL 1} else {set CONFIG_FPU_GRFPU_INFMUL 0} - global CONFIG_FPU_GRFPU_DWMUL - if {$tmpvar_5 == "DW"} then {set CONFIG_FPU_GRFPU_DWMUL 1} else {set CONFIG_FPU_GRFPU_DWMUL 0} - global CONFIG_FPU_GRFPU_MODGEN - if {$tmpvar_5 == "ModGen"} then {set CONFIG_FPU_GRFPU_MODGEN 1} else {set CONFIG_FPU_GRFPU_MODGEN 0} - global tmpvar_6 - global CONFIG_FPU_GRFPC0 - if {$tmpvar_6 == "Simple"} then {set CONFIG_FPU_GRFPC0 1} else {set CONFIG_FPU_GRFPC0 0} - global CONFIG_FPU_GRFPC1 - if {$tmpvar_6 == "Data-forwarding"} then {set CONFIG_FPU_GRFPC1 1} else {set CONFIG_FPU_GRFPC1 0} - global CONFIG_FPU_GRFPC2 - if {$tmpvar_6 == "Non-blocking"} then {set CONFIG_FPU_GRFPC2 1} else {set CONFIG_FPU_GRFPC2 0} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST&15]} else {set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST|16]} -} - - -proc menu6 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 6} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 6]] - message $w.m -width 400 -aspect 300 -text \ - "Cache system" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Cache system" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 6; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu7 .menu7 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 6 0 "Enable instruction cache " CONFIG_ICACHE_ENABLE - global tmpvar_7 - minimenu $w.config.f 6 1 "Associativity (sets) " tmpvar_7 CONFIG_ICACHE_ASSO1 - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Associativity (sets) \"" - $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_7 -value "1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_7 -value "2" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "3" -variable tmpvar_7 -value "3" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_7 -value "4" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 4 - global tmpvar_8 - minimenu $w.config.f 6 2 "Set size (kbytes/set)" tmpvar_8 CONFIG_ICACHE_SZ1 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\"" - $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_8 -value "1" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_8 -value "2" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_8 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_8 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_8 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_8 -value "32" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_8 -value "64" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "128" -variable tmpvar_8 -value "128" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "256" -variable tmpvar_8 -value "256" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 9 - global tmpvar_9 - minimenu $w.config.f 6 3 "Line size (bytes/line)" tmpvar_9 CONFIG_ICACHE_LZ16 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\"" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_9 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_9 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 2 - global tmpvar_10 - minimenu $w.config.f 6 4 "Replacement alorithm" tmpvar_10 CONFIG_ICACHE_ALGORND - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Replacement alorithm\"" - $w.config.f.x4.x.menu add radiobutton -label "Random" -variable tmpvar_10 -value "Random" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "LRR" -variable tmpvar_10 -value "LRR" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "LRU" -variable tmpvar_10 -value "LRU" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 3 - bool $w.config.f 6 5 "Cache locking " CONFIG_ICACHE_LOCK - bool $w.config.f 6 6 "Enable local instruction RAM " CONFIG_ICACHE_LRAM - global tmpvar_11 - minimenu $w.config.f 6 7 "Local data RAM size (kbytes)" tmpvar_11 CONFIG_ICACHE_LRAM_SZ1 - menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x7.x.menu add radiobutton -label "1" -variable tmpvar_11 -value "1" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "2" -variable tmpvar_11 -value "2" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "4" -variable tmpvar_11 -value "4" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_11 -value "8" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_11 -value "16" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_11 -value "32" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_11 -value "64" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_11 -value "128" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_11 -value "256" -command "update_active" - menusplit $w $w.config.f.x7.x.menu 9 - hex $w.config.f 6 8 " Local instruction RAM start address (8 MSB) " CONFIG_ICACHE_LRSTART - bool $w.config.f 6 9 "Enable data cache " CONFIG_DCACHE_ENABLE - global tmpvar_12 - minimenu $w.config.f 6 10 "Associativity (sets)" tmpvar_12 CONFIG_DCACHE_ASSO1 - menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Associativity (sets)\"" - $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_12 -value "1" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_12 -value "2" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "3" -variable tmpvar_12 -value "3" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "4" -variable tmpvar_12 -value "4" -command "update_active" - menusplit $w $w.config.f.x10.x.menu 4 - global tmpvar_13 - minimenu $w.config.f 6 11 "Set size (kbytes/set)" tmpvar_13 CONFIG_DCACHE_SZ1 - menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\"" - $w.config.f.x11.x.menu add radiobutton -label "1" -variable tmpvar_13 -value "1" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "2" -variable tmpvar_13 -value "2" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "4" -variable tmpvar_13 -value "4" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "8" -variable tmpvar_13 -value "8" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "16" -variable tmpvar_13 -value "16" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "32" -variable tmpvar_13 -value "32" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "64" -variable tmpvar_13 -value "64" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "128" -variable tmpvar_13 -value "128" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_13 -value "256" -command "update_active" - menusplit $w $w.config.f.x11.x.menu 9 - global tmpvar_14 - minimenu $w.config.f 6 12 "Line size (bytes/line)" tmpvar_14 CONFIG_DCACHE_LZ16 - menu $w.config.f.x12.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\"" - $w.config.f.x12.x.menu add radiobutton -label "16" -variable tmpvar_14 -value "16" -command "update_active" - $w.config.f.x12.x.menu add radiobutton -label "32" -variable tmpvar_14 -value "32" -command "update_active" - menusplit $w $w.config.f.x12.x.menu 2 - global tmpvar_15 - minimenu $w.config.f 6 13 "Replacement alorithm" tmpvar_15 CONFIG_DCACHE_ALGORND - menu $w.config.f.x13.x.menu -tearoffcommand "menutitle \"Replacement alorithm\"" - $w.config.f.x13.x.menu add radiobutton -label "Random" -variable tmpvar_15 -value "Random" -command "update_active" - $w.config.f.x13.x.menu add radiobutton -label "LRR" -variable tmpvar_15 -value "LRR" -command "update_active" - $w.config.f.x13.x.menu add radiobutton -label "LRU" -variable tmpvar_15 -value "LRU" -command "update_active" - menusplit $w $w.config.f.x13.x.menu 3 - bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK - bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM - global tmpvar_16 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_16 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_16 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_16 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_16 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_16 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_16 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_16 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_16 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_16 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_16 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu6 {} { - global CONFIG_LEON3 - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu6.config.f.x0 normal {n l y}} else {configure_entry .menu6.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x1 normal {x l}} else {configure_entry .menu6.config.f.x1 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x2 normal {x l}} else {configure_entry .menu6.config.f.x2 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x3 normal {x l}} else {configure_entry .menu6.config.f.x3 disabled {x l}} - global CONFIG_ICACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x4 normal {x l}} else {configure_entry .menu6.config.f.x4 disabled {x l}} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - configure_entry .menu6.config.f.x5 normal {n l y}} else {configure_entry .menu6.config.f.x5 disabled {y n l}} - global CONFIG_MMU_ENABLE - global CONFIG_ICACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x6 normal {n l y}} else {configure_entry .menu6.config.f.x6 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x7 normal {x l}} else {configure_entry .menu6.config.f.x7 disabled {x l}} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {.menu6.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x8.l configure -state normal; } else {.menu6.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x8.l configure -state disabled} - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu6.config.f.x9 normal {n l y}} else {configure_entry .menu6.config.f.x9 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x10 normal {x l}} else {configure_entry .menu6.config.f.x10 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x11 normal {x l}} else {configure_entry .menu6.config.f.x11 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x12 normal {x l}} else {configure_entry .menu6.config.f.x12 disabled {x l}} - global CONFIG_DCACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x13 normal {x l}} else {configure_entry .menu6.config.f.x13 disabled {x l}} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - configure_entry .menu6.config.f.x14 normal {n l y}} else {configure_entry .menu6.config.f.x14 disabled {y n l}} - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} -} - - -proc update_define_menu6 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE&15]} else {set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE|16]} - global tmpvar_7 - global CONFIG_ICACHE_ASSO1 - if {$tmpvar_7 == "1"} then {set CONFIG_ICACHE_ASSO1 1} else {set CONFIG_ICACHE_ASSO1 0} - global CONFIG_ICACHE_ASSO2 - if {$tmpvar_7 == "2"} then {set CONFIG_ICACHE_ASSO2 1} else {set CONFIG_ICACHE_ASSO2 0} - global CONFIG_ICACHE_ASSO3 - if {$tmpvar_7 == "3"} then {set CONFIG_ICACHE_ASSO3 1} else {set CONFIG_ICACHE_ASSO3 0} - global CONFIG_ICACHE_ASSO4 - if {$tmpvar_7 == "4"} then {set CONFIG_ICACHE_ASSO4 1} else {set CONFIG_ICACHE_ASSO4 0} - global tmpvar_8 - global CONFIG_ICACHE_SZ1 - if {$tmpvar_8 == "1"} then {set CONFIG_ICACHE_SZ1 1} else {set CONFIG_ICACHE_SZ1 0} - global CONFIG_ICACHE_SZ2 - if {$tmpvar_8 == "2"} then {set CONFIG_ICACHE_SZ2 1} else {set CONFIG_ICACHE_SZ2 0} - global CONFIG_ICACHE_SZ4 - if {$tmpvar_8 == "4"} then {set CONFIG_ICACHE_SZ4 1} else {set CONFIG_ICACHE_SZ4 0} - global CONFIG_ICACHE_SZ8 - if {$tmpvar_8 == "8"} then {set CONFIG_ICACHE_SZ8 1} else {set CONFIG_ICACHE_SZ8 0} - global CONFIG_ICACHE_SZ16 - if {$tmpvar_8 == "16"} then {set CONFIG_ICACHE_SZ16 1} else {set CONFIG_ICACHE_SZ16 0} - global CONFIG_ICACHE_SZ32 - if {$tmpvar_8 == "32"} then {set CONFIG_ICACHE_SZ32 1} else {set CONFIG_ICACHE_SZ32 0} - global CONFIG_ICACHE_SZ64 - if {$tmpvar_8 == "64"} then {set CONFIG_ICACHE_SZ64 1} else {set CONFIG_ICACHE_SZ64 0} - global CONFIG_ICACHE_SZ128 - if {$tmpvar_8 == "128"} then {set CONFIG_ICACHE_SZ128 1} else {set CONFIG_ICACHE_SZ128 0} - global CONFIG_ICACHE_SZ256 - if {$tmpvar_8 == "256"} then {set CONFIG_ICACHE_SZ256 1} else {set CONFIG_ICACHE_SZ256 0} - global tmpvar_9 - global CONFIG_ICACHE_LZ16 - if {$tmpvar_9 == "16"} then {set CONFIG_ICACHE_LZ16 1} else {set CONFIG_ICACHE_LZ16 0} - global CONFIG_ICACHE_LZ32 - if {$tmpvar_9 == "32"} then {set CONFIG_ICACHE_LZ32 1} else {set CONFIG_ICACHE_LZ32 0} - global tmpvar_10 - global CONFIG_ICACHE_ALGORND - if {$tmpvar_10 == "Random"} then {set CONFIG_ICACHE_ALGORND 1} else {set CONFIG_ICACHE_ALGORND 0} - global CONFIG_ICACHE_ALGOLRR - if {$tmpvar_10 == "LRR"} then {set CONFIG_ICACHE_ALGOLRR 1} else {set CONFIG_ICACHE_ALGOLRR 0} - global CONFIG_ICACHE_ALGOLRU - if {$tmpvar_10 == "LRU"} then {set CONFIG_ICACHE_ALGOLRU 1} else {set CONFIG_ICACHE_ALGOLRU 0} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK&15]} else {set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK|16]} - global CONFIG_MMU_ENABLE - global CONFIG_ICACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM&15]} else {set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM|16]} - global tmpvar_11 - global CONFIG_ICACHE_LRAM_SZ1 - if {$tmpvar_11 == "1"} then {set CONFIG_ICACHE_LRAM_SZ1 1} else {set CONFIG_ICACHE_LRAM_SZ1 0} - global CONFIG_ICACHE_LRAM_SZ2 - if {$tmpvar_11 == "2"} then {set CONFIG_ICACHE_LRAM_SZ2 1} else {set CONFIG_ICACHE_LRAM_SZ2 0} - global CONFIG_ICACHE_LRAM_SZ4 - if {$tmpvar_11 == "4"} then {set CONFIG_ICACHE_LRAM_SZ4 1} else {set CONFIG_ICACHE_LRAM_SZ4 0} - global CONFIG_ICACHE_LRAM_SZ8 - if {$tmpvar_11 == "8"} then {set CONFIG_ICACHE_LRAM_SZ8 1} else {set CONFIG_ICACHE_LRAM_SZ8 0} - global CONFIG_ICACHE_LRAM_SZ16 - if {$tmpvar_11 == "16"} then {set CONFIG_ICACHE_LRAM_SZ16 1} else {set CONFIG_ICACHE_LRAM_SZ16 0} - global CONFIG_ICACHE_LRAM_SZ32 - if {$tmpvar_11 == "32"} then {set CONFIG_ICACHE_LRAM_SZ32 1} else {set CONFIG_ICACHE_LRAM_SZ32 0} - global CONFIG_ICACHE_LRAM_SZ64 - if {$tmpvar_11 == "64"} then {set CONFIG_ICACHE_LRAM_SZ64 1} else {set CONFIG_ICACHE_LRAM_SZ64 0} - global CONFIG_ICACHE_LRAM_SZ128 - if {$tmpvar_11 == "128"} then {set CONFIG_ICACHE_LRAM_SZ128 1} else {set CONFIG_ICACHE_LRAM_SZ128 0} - global CONFIG_ICACHE_LRAM_SZ256 - if {$tmpvar_11 == "256"} then {set CONFIG_ICACHE_LRAM_SZ256 1} else {set CONFIG_ICACHE_LRAM_SZ256 0} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {validate_hex CONFIG_ICACHE_LRSTART "$CONFIG_ICACHE_LRSTART" 8e} - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE&15]} else {set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE|16]} - global tmpvar_12 - global CONFIG_DCACHE_ASSO1 - if {$tmpvar_12 == "1"} then {set CONFIG_DCACHE_ASSO1 1} else {set CONFIG_DCACHE_ASSO1 0} - global CONFIG_DCACHE_ASSO2 - if {$tmpvar_12 == "2"} then {set CONFIG_DCACHE_ASSO2 1} else {set CONFIG_DCACHE_ASSO2 0} - global CONFIG_DCACHE_ASSO3 - if {$tmpvar_12 == "3"} then {set CONFIG_DCACHE_ASSO3 1} else {set CONFIG_DCACHE_ASSO3 0} - global CONFIG_DCACHE_ASSO4 - if {$tmpvar_12 == "4"} then {set CONFIG_DCACHE_ASSO4 1} else {set CONFIG_DCACHE_ASSO4 0} - global tmpvar_13 - global CONFIG_DCACHE_SZ1 - if {$tmpvar_13 == "1"} then {set CONFIG_DCACHE_SZ1 1} else {set CONFIG_DCACHE_SZ1 0} - global CONFIG_DCACHE_SZ2 - if {$tmpvar_13 == "2"} then {set CONFIG_DCACHE_SZ2 1} else {set CONFIG_DCACHE_SZ2 0} - global CONFIG_DCACHE_SZ4 - if {$tmpvar_13 == "4"} then {set CONFIG_DCACHE_SZ4 1} else {set CONFIG_DCACHE_SZ4 0} - global CONFIG_DCACHE_SZ8 - if {$tmpvar_13 == "8"} then {set CONFIG_DCACHE_SZ8 1} else {set CONFIG_DCACHE_SZ8 0} - global CONFIG_DCACHE_SZ16 - if {$tmpvar_13 == "16"} then {set CONFIG_DCACHE_SZ16 1} else {set CONFIG_DCACHE_SZ16 0} - global CONFIG_DCACHE_SZ32 - if {$tmpvar_13 == "32"} then {set CONFIG_DCACHE_SZ32 1} else {set CONFIG_DCACHE_SZ32 0} - global CONFIG_DCACHE_SZ64 - if {$tmpvar_13 == "64"} then {set CONFIG_DCACHE_SZ64 1} else {set CONFIG_DCACHE_SZ64 0} - global CONFIG_DCACHE_SZ128 - if {$tmpvar_13 == "128"} then {set CONFIG_DCACHE_SZ128 1} else {set CONFIG_DCACHE_SZ128 0} - global CONFIG_DCACHE_SZ256 - if {$tmpvar_13 == "256"} then {set CONFIG_DCACHE_SZ256 1} else {set CONFIG_DCACHE_SZ256 0} - global tmpvar_14 - global CONFIG_DCACHE_LZ16 - if {$tmpvar_14 == "16"} then {set CONFIG_DCACHE_LZ16 1} else {set CONFIG_DCACHE_LZ16 0} - global CONFIG_DCACHE_LZ32 - if {$tmpvar_14 == "32"} then {set CONFIG_DCACHE_LZ32 1} else {set CONFIG_DCACHE_LZ32 0} - global tmpvar_15 - global CONFIG_DCACHE_ALGORND - if {$tmpvar_15 == "Random"} then {set CONFIG_DCACHE_ALGORND 1} else {set CONFIG_DCACHE_ALGORND 0} - global CONFIG_DCACHE_ALGOLRR - if {$tmpvar_15 == "LRR"} then {set CONFIG_DCACHE_ALGOLRR 1} else {set CONFIG_DCACHE_ALGOLRR 0} - global CONFIG_DCACHE_ALGOLRU - if {$tmpvar_15 == "LRU"} then {set CONFIG_DCACHE_ALGOLRU 1} else {set CONFIG_DCACHE_ALGOLRU 0} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK&15]} else {set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK|16]} - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {validate_hex CONFIG_CACHE_FIXED "$CONFIG_CACHE_FIXED" 0} - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM&15]} else {set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM|16]} - global tmpvar_16 - global CONFIG_DCACHE_LRAM_SZ1 - if {$tmpvar_16 == "1"} then {set CONFIG_DCACHE_LRAM_SZ1 1} else {set CONFIG_DCACHE_LRAM_SZ1 0} - global CONFIG_DCACHE_LRAM_SZ2 - if {$tmpvar_16 == "2"} then {set CONFIG_DCACHE_LRAM_SZ2 1} else {set CONFIG_DCACHE_LRAM_SZ2 0} - global CONFIG_DCACHE_LRAM_SZ4 - if {$tmpvar_16 == "4"} then {set CONFIG_DCACHE_LRAM_SZ4 1} else {set CONFIG_DCACHE_LRAM_SZ4 0} - global CONFIG_DCACHE_LRAM_SZ8 - if {$tmpvar_16 == "8"} then {set CONFIG_DCACHE_LRAM_SZ8 1} else {set CONFIG_DCACHE_LRAM_SZ8 0} - global CONFIG_DCACHE_LRAM_SZ16 - if {$tmpvar_16 == "16"} then {set CONFIG_DCACHE_LRAM_SZ16 1} else {set CONFIG_DCACHE_LRAM_SZ16 0} - global CONFIG_DCACHE_LRAM_SZ32 - if {$tmpvar_16 == "32"} then {set CONFIG_DCACHE_LRAM_SZ32 1} else {set CONFIG_DCACHE_LRAM_SZ32 0} - global CONFIG_DCACHE_LRAM_SZ64 - if {$tmpvar_16 == "64"} then {set CONFIG_DCACHE_LRAM_SZ64 1} else {set CONFIG_DCACHE_LRAM_SZ64 0} - global CONFIG_DCACHE_LRAM_SZ128 - if {$tmpvar_16 == "128"} then {set CONFIG_DCACHE_LRAM_SZ128 1} else {set CONFIG_DCACHE_LRAM_SZ128 0} - global CONFIG_DCACHE_LRAM_SZ256 - if {$tmpvar_16 == "256"} then {set CONFIG_DCACHE_LRAM_SZ256 1} else {set CONFIG_DCACHE_LRAM_SZ256 0} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {validate_hex CONFIG_DCACHE_LRSTART "$CONFIG_DCACHE_LRSTART" 8f} -} - - -proc menu7 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 7} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 7]] - message $w.m -width 400 -aspect 300 -text \ - "MMU" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "MMU" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 7; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu8 .menu8 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 7 0 "Enable MMU " CONFIG_MMU_ENABLE - global tmpvar_17 - minimenu $w.config.f 7 1 "MMU type " tmpvar_17 CONFIG_MMU_COMBINED - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"MMU type \"" - $w.config.f.x1.x.menu add radiobutton -label "combined" -variable tmpvar_17 -value "combined" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "split" -variable tmpvar_17 -value "split" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 2 - global tmpvar_18 - minimenu $w.config.f 7 2 "TLB replacement sheme " tmpvar_18 CONFIG_MMU_REPARRAY - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"TLB replacement sheme \"" - $w.config.f.x2.x.menu add radiobutton -label "LRU" -variable tmpvar_18 -value "LRU" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "Increment" -variable tmpvar_18 -value "Increment" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 2 - global tmpvar_19 - minimenu $w.config.f 7 3 "Instruction (or combined) TLB entries" tmpvar_19 CONFIG_MMU_I2 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Instruction (or combined) TLB entries\"" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 5 - global tmpvar_20 - minimenu $w.config.f 7 4 "Data TLB entries" tmpvar_20 CONFIG_MMU_D2 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Data TLB entries\"" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_20 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_20 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_20 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_20 -value "16" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_20 -value "32" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 5 - bool $w.config.f 7 5 "Fast writebuffer " CONFIG_MMU_FASTWB - global tmpvar_21 - minimenu $w.config.f 7 6 "MMU page size" tmpvar_21 CONFIG_MMU_PAGE_4K - menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"MMU page size\"" - $w.config.f.x6.x.menu add radiobutton -label "4K" -variable tmpvar_21 -value "4K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "8K" -variable tmpvar_21 -value "8K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "16K" -variable tmpvar_21 -value "16K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "32K" -variable tmpvar_21 -value "32K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "Programmable" -variable tmpvar_21 -value "Programmable" -command "update_active" - menusplit $w $w.config.f.x6.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu7 {} { - global CONFIG_LEON3 - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu7.config.f.x0 normal {n l y}} else {configure_entry .menu7.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x1 normal {x l}} else {configure_entry .menu7.config.f.x1 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x2 normal {x l}} else {configure_entry .menu7.config.f.x2 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x3 normal {x l}} else {configure_entry .menu7.config.f.x3 disabled {x l}} - global CONFIG_MMU_SPLIT - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {configure_entry .menu7.config.f.x4 normal {x l}} else {configure_entry .menu7.config.f.x4 disabled {x l}} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - configure_entry .menu7.config.f.x5 normal {n l y}} else {configure_entry .menu7.config.f.x5 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x6 normal {x l}} else {configure_entry .menu7.config.f.x6 disabled {x l}} -} - - -proc update_define_menu7 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE&15]} else {set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE|16]} - global tmpvar_17 - global CONFIG_MMU_COMBINED - if {$tmpvar_17 == "combined"} then {set CONFIG_MMU_COMBINED 1} else {set CONFIG_MMU_COMBINED 0} - global CONFIG_MMU_SPLIT - if {$tmpvar_17 == "split"} then {set CONFIG_MMU_SPLIT 1} else {set CONFIG_MMU_SPLIT 0} - global tmpvar_18 - global CONFIG_MMU_REPARRAY - if {$tmpvar_18 == "LRU"} then {set CONFIG_MMU_REPARRAY 1} else {set CONFIG_MMU_REPARRAY 0} - global CONFIG_MMU_REPINCREMENT - if {$tmpvar_18 == "Increment"} then {set CONFIG_MMU_REPINCREMENT 1} else {set CONFIG_MMU_REPINCREMENT 0} - global tmpvar_19 - global CONFIG_MMU_I2 - if {$tmpvar_19 == "2"} then {set CONFIG_MMU_I2 1} else {set CONFIG_MMU_I2 0} - global CONFIG_MMU_I4 - if {$tmpvar_19 == "4"} then {set CONFIG_MMU_I4 1} else {set CONFIG_MMU_I4 0} - global CONFIG_MMU_I8 - if {$tmpvar_19 == "8"} then {set CONFIG_MMU_I8 1} else {set CONFIG_MMU_I8 0} - global CONFIG_MMU_I16 - if {$tmpvar_19 == "16"} then {set CONFIG_MMU_I16 1} else {set CONFIG_MMU_I16 0} - global CONFIG_MMU_I32 - if {$tmpvar_19 == "32"} then {set CONFIG_MMU_I32 1} else {set CONFIG_MMU_I32 0} - global tmpvar_20 - global CONFIG_MMU_D2 - if {$tmpvar_20 == "2"} then {set CONFIG_MMU_D2 1} else {set CONFIG_MMU_D2 0} - global CONFIG_MMU_D4 - if {$tmpvar_20 == "4"} then {set CONFIG_MMU_D4 1} else {set CONFIG_MMU_D4 0} - global CONFIG_MMU_D8 - if {$tmpvar_20 == "8"} then {set CONFIG_MMU_D8 1} else {set CONFIG_MMU_D8 0} - global CONFIG_MMU_D16 - if {$tmpvar_20 == "16"} then {set CONFIG_MMU_D16 1} else {set CONFIG_MMU_D16 0} - global CONFIG_MMU_D32 - if {$tmpvar_20 == "32"} then {set CONFIG_MMU_D32 1} else {set CONFIG_MMU_D32 0} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB&15]} else {set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB|16]} - global tmpvar_21 - global CONFIG_MMU_PAGE_4K - if {$tmpvar_21 == "4K"} then {set CONFIG_MMU_PAGE_4K 1} else {set CONFIG_MMU_PAGE_4K 0} - global CONFIG_MMU_PAGE_8K - if {$tmpvar_21 == "8K"} then {set CONFIG_MMU_PAGE_8K 1} else {set CONFIG_MMU_PAGE_8K 0} - global CONFIG_MMU_PAGE_16K - if {$tmpvar_21 == "16K"} then {set CONFIG_MMU_PAGE_16K 1} else {set CONFIG_MMU_PAGE_16K 0} - global CONFIG_MMU_PAGE_32K - if {$tmpvar_21 == "32K"} then {set CONFIG_MMU_PAGE_32K 1} else {set CONFIG_MMU_PAGE_32K 0} - global CONFIG_MMU_PAGE_PROG - if {$tmpvar_21 == "Programmable"} then {set CONFIG_MMU_PAGE_PROG 1} else {set CONFIG_MMU_PAGE_PROG 0} -} - - -proc menu8 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 8} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 8]] - message $w.m -width 400 -aspect 300 -text \ - "Debug Support Unit " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Debug Support Unit " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 8; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu9 .menu9 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 8 0 "Enable LEON3 Debug support unit " CONFIG_DSU_ENABLE - bool $w.config.f 8 1 "Instruction trace buffer" CONFIG_DSU_ITRACE - global tmpvar_22 - minimenu $w.config.f 8 2 "Instruction trace buffer size (kbytes)" tmpvar_22 CONFIG_DSU_ITRACESZ1 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Instruction trace buffer size (kbytes)\"" - $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_22 -value "1" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_22 -value "2" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_22 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_22 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_22 -value "16" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 5 - bool $w.config.f 8 3 "AHB trace buffer" CONFIG_DSU_ATRACE - global tmpvar_23 - minimenu $w.config.f 8 4 "AHB trace buffer size (kbytes)" tmpvar_23 CONFIG_DSU_ATRACESZ1 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB trace buffer size (kbytes)\"" - $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_23 -value "1" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_23 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_23 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_23 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_23 -value "16" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu8 {} { - global CONFIG_LEON3 - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu8.config.f.x0 normal {n l y}} else {configure_entry .menu8.config.f.x0 disabled {y n l}} - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - configure_entry .menu8.config.f.x1 normal {n l y}} else {configure_entry .menu8.config.f.x1 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then {configure_entry .menu8.config.f.x2 normal {x l}} else {configure_entry .menu8.config.f.x2 disabled {x l}} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - configure_entry .menu8.config.f.x3 normal {n l y}} else {configure_entry .menu8.config.f.x3 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then {configure_entry .menu8.config.f.x4 normal {x l}} else {configure_entry .menu8.config.f.x4 disabled {x l}} -} - - -proc update_define_menu8 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE&15]} else {set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE|16]} - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE&15]} else {set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE|16]} - global tmpvar_22 - global CONFIG_DSU_ITRACESZ1 - if {$tmpvar_22 == "1"} then {set CONFIG_DSU_ITRACESZ1 1} else {set CONFIG_DSU_ITRACESZ1 0} - global CONFIG_DSU_ITRACESZ2 - if {$tmpvar_22 == "2"} then {set CONFIG_DSU_ITRACESZ2 1} else {set CONFIG_DSU_ITRACESZ2 0} - global CONFIG_DSU_ITRACESZ4 - if {$tmpvar_22 == "4"} then {set CONFIG_DSU_ITRACESZ4 1} else {set CONFIG_DSU_ITRACESZ4 0} - global CONFIG_DSU_ITRACESZ8 - if {$tmpvar_22 == "8"} then {set CONFIG_DSU_ITRACESZ8 1} else {set CONFIG_DSU_ITRACESZ8 0} - global CONFIG_DSU_ITRACESZ16 - if {$tmpvar_22 == "16"} then {set CONFIG_DSU_ITRACESZ16 1} else {set CONFIG_DSU_ITRACESZ16 0} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE&15]} else {set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE|16]} - global tmpvar_23 - global CONFIG_DSU_ATRACESZ1 - if {$tmpvar_23 == "1"} then {set CONFIG_DSU_ATRACESZ1 1} else {set CONFIG_DSU_ATRACESZ1 0} - global CONFIG_DSU_ATRACESZ2 - if {$tmpvar_23 == "2"} then {set CONFIG_DSU_ATRACESZ2 1} else {set CONFIG_DSU_ATRACESZ2 0} - global CONFIG_DSU_ATRACESZ4 - if {$tmpvar_23 == "4"} then {set CONFIG_DSU_ATRACESZ4 1} else {set CONFIG_DSU_ATRACESZ4 0} - global CONFIG_DSU_ATRACESZ8 - if {$tmpvar_23 == "8"} then {set CONFIG_DSU_ATRACESZ8 1} else {set CONFIG_DSU_ATRACESZ8 0} - global CONFIG_DSU_ATRACESZ16 - if {$tmpvar_23 == "16"} then {set CONFIG_DSU_ATRACESZ16 1} else {set CONFIG_DSU_ATRACESZ16 0} -} - - -proc menu9 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 9} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 9]] - message $w.m -width 400 -aspect 300 -text \ - "Fault-tolerance " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Fault-tolerance " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 9; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu10 .menu10 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu9 {} { -} - - -proc update_define_menu9 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu10 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 10} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 10]] - message $w.m -width 400 -aspect 300 -text \ - "VHDL debug settings " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "VHDL debug settings " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 10; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 10; catch {destroy .menu3}; unregister_active 3; menu11 .menu11 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 10 0 "Processor disassembly to console " CONFIG_IU_DISAS - bool $w.config.f 10 1 "Processor disassembly in netlist " CONFIG_IU_DISAS_NET - bool $w.config.f 10 2 "32-bit program counters " CONFIG_DEBUG_PC32 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu10 {} { - global CONFIG_LEON3 - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu10.config.f.x0 normal {n l y}} else {configure_entry .menu10.config.f.x0 disabled {y n l}} - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then { - configure_entry .menu10.config.f.x1 normal {n l y}} else {configure_entry .menu10.config.f.x1 disabled {y n l}} - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu10.config.f.x2 normal {n l y}} else {configure_entry .menu10.config.f.x2 disabled {y n l}} -} - - -proc update_define_menu10 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS&15]} else {set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS|16]} - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then { - set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET&15]} else {set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET|16]} - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32&15]} else {set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32|16]} -} - - -menu_option menu11 11 "AMBA configuration" -proc menu11 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 11} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 11]] - message $w.m -width 400 -aspect 300 -text \ - "AMBA configuration" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "AMBA configuration" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu12 .menu12 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - int $w.config.f 11 0 "Default AHB master" CONFIG_AHB_DEFMST - bool $w.config.f 11 1 "Round-robin arbiter " CONFIG_AHB_RROBIN - bool $w.config.f 11 2 "AHB split-transaction support " CONFIG_AHB_SPLIT - hex $w.config.f 11 3 "I/O area start address (haddr\[31:20\]) " CONFIG_AHB_IOADDR - hex $w.config.f 11 4 "AHB/APB bridge address (haddr\[31:20\]) " CONFIG_APB_HADDR - bool $w.config.f 11 5 "Enable AMBA AHB monitor " CONFIG_AHB_MON - bool $w.config.f 11 6 "Report AHB errors " CONFIG_AHB_MONERR - bool $w.config.f 11 7 "Report AHB warings " CONFIG_AHB_MONWAR - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu11 {} { - global CONFIG_AHB_MON - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then { - configure_entry .menu11.config.f.x6 normal {n l y}} else {configure_entry .menu11.config.f.x6 disabled {y n l}} - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then { - configure_entry .menu11.config.f.x7 normal {n l y}} else {configure_entry .menu11.config.f.x7 disabled {y n l}} -} - - -proc update_define_menu11 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_AHB_MON - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then { - set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR&15]} else {set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR|16]} - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then { - set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR&15]} else {set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR|16]} -} - - -menu_option menu12 12 "Debug Link " -proc menu12 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 12} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 12]] - message $w.m -width 400 -aspect 300 -text \ - "Debug Link " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Debug Link " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu13 .menu13 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 12 0 "Serial Debug Link (RS232) " CONFIG_DSU_UART - bool $w.config.f 12 1 "JTAG Debug Link" CONFIG_DSU_JTAG - bool $w.config.f 12 2 "Ethernet Debug Communication Link (EDCL)" CONFIG_DSU_ETH - global tmpvar_25 - minimenu $w.config.f 12 3 "Ethernet/AHB bridge buffer size (kbytes)" tmpvar_25 CONFIG_DSU_ETHSZ1 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Ethernet/AHB bridge buffer size (kbytes)\"" - $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_25 -value "1" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_25 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_25 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_25 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_25 -value "16" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 5 - hex $w.config.f 12 4 "MSB 16 bits of IP address (hex) " CONFIG_DSU_IPMSB - hex $w.config.f 12 5 "LSB 16 bits of IP address (hex) " CONFIG_DSU_IPLSB - hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB - hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB - bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu12 {} { - global CONFIG_GRETH_ENABLE - global CONFIG_DSU_ETH - if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu12.config.f.x2 normal {n l y}} else {configure_entry .menu12.config.f.x2 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {configure_entry .menu12.config.f.x3 normal {x l}} else {configure_entry .menu12.config.f.x3 disabled {x l}} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x4.l configure -state normal; } else {.menu12.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x4.l configure -state disabled} - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x5.l configure -state normal; } else {.menu12.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x5.l configure -state disabled} - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA - global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} -} - - -proc update_define_menu12 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_GRETH_ENABLE - global CONFIG_DSU_ETH - if {($CONFIG_GRETH_ENABLE == 1)} then { - set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH&15]} else {set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH|16]} - global tmpvar_25 - global CONFIG_DSU_ETHSZ1 - if {$tmpvar_25 == "1"} then {set CONFIG_DSU_ETHSZ1 1} else {set CONFIG_DSU_ETHSZ1 0} - global CONFIG_DSU_ETHSZ2 - if {$tmpvar_25 == "2"} then {set CONFIG_DSU_ETHSZ2 1} else {set CONFIG_DSU_ETHSZ2 0} - global CONFIG_DSU_ETHSZ4 - if {$tmpvar_25 == "4"} then {set CONFIG_DSU_ETHSZ4 1} else {set CONFIG_DSU_ETHSZ4 0} - global CONFIG_DSU_ETHSZ8 - if {$tmpvar_25 == "8"} then {set CONFIG_DSU_ETHSZ8 1} else {set CONFIG_DSU_ETHSZ8 0} - global CONFIG_DSU_ETHSZ16 - if {$tmpvar_25 == "16"} then {set CONFIG_DSU_ETHSZ16 1} else {set CONFIG_DSU_ETHSZ16 0} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPMSB "$CONFIG_DSU_IPMSB" C0A8} - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPLSB "$CONFIG_DSU_IPLSB" 0033} - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA - global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} -} - - -menu_option menu13 13 "Peripherals " -proc menu13 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 13} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 13]] - message $w.m -width 400 -aspect 300 -text \ - "Peripherals " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Peripherals " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; break" - set nextscript "catch {focus $oldFocus}; menu14 .menu14 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - submenu $w.config.f 13 0 "Memory controllers " 14 - submenu $w.config.f 13 1 "On-chip RAM/ROM " 18 - submenu $w.config.f 13 2 "Ethernet " 19 - submenu $w.config.f 13 3 "CAN " 20 - submenu $w.config.f 13 4 "PCI " 21 - submenu $w.config.f 13 5 "Spacewire " 22 - submenu $w.config.f 13 6 "UARTs, timers and irq control " 23 - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu13 {} { -} - - -proc update_define_menu13 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu14 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 14} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 14]] - message $w.m -width 400 -aspect 300 -text \ - "Memory controllers " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Memory controllers " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; break" - set nextscript "catch {focus $oldFocus}; menu15 .menu15 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - submenu $w.config.f 14 0 "8/32-bit PROM/SRAM controller " 15 - submenu $w.config.f 14 1 "Leon2 memory controller " 16 - submenu $w.config.f 14 2 "PC133 SDRAM controller " 17 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu14 {} { -} - - -proc update_define_menu14 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu15 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 15} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 15]] - message $w.m -width 400 -aspect 300 -text \ - "8/32-bit PROM/SRAM controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "8/32-bit PROM/SRAM controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu16 .menu16 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 15 0 "Enable 8/32-bit PROM/SRAM controller " CONFIG_SRCTRL - bool $w.config.f 15 1 "8-bit PROM interface " CONFIG_SRCTRL_8BIT - int $w.config.f 15 2 "PROM waitstates" CONFIG_SRCTRL_PROMWS - int $w.config.f 15 3 "RAM waitstates" CONFIG_SRCTRL_RAMWS - int $w.config.f 15 4 "IO waitstates" CONFIG_SRCTRL_IOWS - bool $w.config.f 15 5 "Use read-modify-write for sub-word writes " CONFIG_SRCTRL_RMW - global tmpvar_26 - minimenu $w.config.f 15 6 "SRAM banks" tmpvar_26 CONFIG_SRCTRL_SRBANKS1 - menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"SRAM banks\"" - $w.config.f.x6.x.menu add radiobutton -label "1" -variable tmpvar_26 -value "1" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "2" -variable tmpvar_26 -value "2" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "3" -variable tmpvar_26 -value "3" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "4" -variable tmpvar_26 -value "4" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "5" -variable tmpvar_26 -value "5" -command "update_active" - menusplit $w $w.config.f.x6.x.menu 5 - global tmpvar_27 - minimenu $w.config.f 15 7 "SRAM bank size (kb) (0 for programmable)" tmpvar_27 CONFIG_SRCTRL_BANKSZ0 - menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"SRAM bank size (kb) (0 for programmable)\"" - $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_27 -value "8" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_27 -value "16" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_27 -value "32" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_27 -value "64" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_27 -value "128" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_27 -value "256" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "512" -variable tmpvar_27 -value "512" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "1024" -variable tmpvar_27 -value "1024" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "2048" -variable tmpvar_27 -value "2048" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "4096" -variable tmpvar_27 -value "4096" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "8192" -variable tmpvar_27 -value "8192" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16384" -variable tmpvar_27 -value "16384" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32768" -variable tmpvar_27 -value "32768" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "65536" -variable tmpvar_27 -value "65536" -command "update_active" - menusplit $w $w.config.f.x7.x.menu 14 - int $w.config.f 15 8 "PROM bank select address bit (0 - 28)" CONFIG_SRCTRL_ROMASEL - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu15 {} { - global CONFIG_SRCTRL - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then { - configure_entry .menu15.config.f.x1 normal {n l y}} else {configure_entry .menu15.config.f.x1 disabled {y n l}} - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x2.l configure -state normal; } else {.menu15.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x2.l configure -state disabled} - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x3.l configure -state normal; } else {.menu15.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x3.l configure -state disabled} - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x4.l configure -state normal; } else {.menu15.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x4.l configure -state disabled} - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then { - configure_entry .menu15.config.f.x5 normal {n l y}} else {configure_entry .menu15.config.f.x5 disabled {y n l}} - if {($CONFIG_SRCTRL == 1)} then {configure_entry .menu15.config.f.x6 normal {x l}} else {configure_entry .menu15.config.f.x6 disabled {x l}} - if {($CONFIG_SRCTRL == 1)} then {configure_entry .menu15.config.f.x7 normal {x l}} else {configure_entry .menu15.config.f.x7 disabled {x l}} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x8.l configure -state normal; } else {.menu15.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x8.l configure -state disabled} -} - - -proc update_define_menu15 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SRCTRL - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then { - set CONFIG_SRCTRL_8BIT [expr $CONFIG_SRCTRL_8BIT&15]} else {set CONFIG_SRCTRL_8BIT [expr $CONFIG_SRCTRL_8BIT|16]} - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_PROMWS "$CONFIG_SRCTRL_PROMWS" 3} - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_RAMWS "$CONFIG_SRCTRL_RAMWS" 0} - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_IOWS "$CONFIG_SRCTRL_IOWS" 0} - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then { - set CONFIG_SRCTRL_RMW [expr $CONFIG_SRCTRL_RMW&15]} else {set CONFIG_SRCTRL_RMW [expr $CONFIG_SRCTRL_RMW|16]} - global tmpvar_26 - global CONFIG_SRCTRL_SRBANKS1 - if {$tmpvar_26 == "1"} then {set CONFIG_SRCTRL_SRBANKS1 1} else {set CONFIG_SRCTRL_SRBANKS1 0} - global CONFIG_SRCTRL_SRBANKS2 - if {$tmpvar_26 == "2"} then {set CONFIG_SRCTRL_SRBANKS2 1} else {set CONFIG_SRCTRL_SRBANKS2 0} - global CONFIG_SRCTRL_SRBANKS3 - if {$tmpvar_26 == "3"} then {set CONFIG_SRCTRL_SRBANKS3 1} else {set CONFIG_SRCTRL_SRBANKS3 0} - global CONFIG_SRCTRL_SRBANKS4 - if {$tmpvar_26 == "4"} then {set CONFIG_SRCTRL_SRBANKS4 1} else {set CONFIG_SRCTRL_SRBANKS4 0} - global CONFIG_SRCTRL_SRBANKS5 - if {$tmpvar_26 == "5"} then {set CONFIG_SRCTRL_SRBANKS5 1} else {set CONFIG_SRCTRL_SRBANKS5 0} - global tmpvar_27 - global CONFIG_SRCTRL_BANKSZ0 - if {$tmpvar_27 == "8"} then {set CONFIG_SRCTRL_BANKSZ0 1} else {set CONFIG_SRCTRL_BANKSZ0 0} - global CONFIG_SRCTRL_BANKSZ1 - if {$tmpvar_27 == "16"} then {set CONFIG_SRCTRL_BANKSZ1 1} else {set CONFIG_SRCTRL_BANKSZ1 0} - global CONFIG_SRCTRL_BANKSZ2 - if {$tmpvar_27 == "32"} then {set CONFIG_SRCTRL_BANKSZ2 1} else {set CONFIG_SRCTRL_BANKSZ2 0} - global CONFIG_SRCTRL_BANKSZ3 - if {$tmpvar_27 == "64"} then {set CONFIG_SRCTRL_BANKSZ3 1} else {set CONFIG_SRCTRL_BANKSZ3 0} - global CONFIG_SRCTRL_BANKSZ4 - if {$tmpvar_27 == "128"} then {set CONFIG_SRCTRL_BANKSZ4 1} else {set CONFIG_SRCTRL_BANKSZ4 0} - global CONFIG_SRCTRL_BANKSZ5 - if {$tmpvar_27 == "256"} then {set CONFIG_SRCTRL_BANKSZ5 1} else {set CONFIG_SRCTRL_BANKSZ5 0} - global CONFIG_SRCTRL_BANKSZ6 - if {$tmpvar_27 == "512"} then {set CONFIG_SRCTRL_BANKSZ6 1} else {set CONFIG_SRCTRL_BANKSZ6 0} - global CONFIG_SRCTRL_BANKSZ7 - if {$tmpvar_27 == "1024"} then {set CONFIG_SRCTRL_BANKSZ7 1} else {set CONFIG_SRCTRL_BANKSZ7 0} - global CONFIG_SRCTRL_BANKSZ8 - if {$tmpvar_27 == "2048"} then {set CONFIG_SRCTRL_BANKSZ8 1} else {set CONFIG_SRCTRL_BANKSZ8 0} - global CONFIG_SRCTRL_BANKSZ9 - if {$tmpvar_27 == "4096"} then {set CONFIG_SRCTRL_BANKSZ9 1} else {set CONFIG_SRCTRL_BANKSZ9 0} - global CONFIG_SRCTRL_BANKSZ10 - if {$tmpvar_27 == "8192"} then {set CONFIG_SRCTRL_BANKSZ10 1} else {set CONFIG_SRCTRL_BANKSZ10 0} - global CONFIG_SRCTRL_BANKSZ11 - if {$tmpvar_27 == "16384"} then {set CONFIG_SRCTRL_BANKSZ11 1} else {set CONFIG_SRCTRL_BANKSZ11 0} - global CONFIG_SRCTRL_BANKSZ12 - if {$tmpvar_27 == "32768"} then {set CONFIG_SRCTRL_BANKSZ12 1} else {set CONFIG_SRCTRL_BANKSZ12 0} - global CONFIG_SRCTRL_BANKSZ13 - if {$tmpvar_27 == "65536"} then {set CONFIG_SRCTRL_BANKSZ13 1} else {set CONFIG_SRCTRL_BANKSZ13 0} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_ROMASEL "$CONFIG_SRCTRL_ROMASEL" 19} -} - - -proc menu16 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 16} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 16]] - message $w.m -width 400 -aspect 300 -text \ - "Leon2 memory controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Leon2 memory controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu17 .menu17 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 16 0 "Enable Leon2 memory controller " CONFIG_MCTRL_LEON2 - bool $w.config.f 16 1 "8-bit PROM/SRAM bus support " CONFIG_MCTRL_8BIT - bool $w.config.f 16 2 "16-bit PROM/SRAM bus support " CONFIG_MCTRL_16BIT - bool $w.config.f 16 3 "5th SRAM chip-select " CONFIG_MCTRL_5CS - bool $w.config.f 16 4 "SDRAM controller " CONFIG_MCTRL_SDRAM - bool $w.config.f 16 5 "Separate address and data buses" CONFIG_MCTRL_SDRAM_SEPBUS - bool $w.config.f 16 6 "64-bit SDRAM data bus" CONFIG_MCTRL_SDRAM_BUS64 - bool $w.config.f 16 7 "Unsynchronized sdclock" CONFIG_MCTRL_SDRAM_INVCLK - bool $w.config.f 16 8 "Enable page burst operation " CONFIG_MCTRL_PAGE - bool $w.config.f 16 9 "Enable programmable page burst " CONFIG_MCTRL_PROGPAGE - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu16 {} { - global CONFIG_MCTRL_LEON2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x1 normal {n l y}} else {configure_entry .menu16.config.f.x1 disabled {y n l}} - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x2 normal {n l y}} else {configure_entry .menu16.config.f.x2 disabled {y n l}} - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x3 normal {n l y}} else {configure_entry .menu16.config.f.x3 disabled {y n l}} - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x4 normal {n l y}} else {configure_entry .menu16.config.f.x4 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - configure_entry .menu16.config.f.x5 normal {n l y}} else {configure_entry .menu16.config.f.x5 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - configure_entry .menu16.config.f.x6 normal {n l y}} else {configure_entry .menu16.config.f.x6 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - configure_entry .menu16.config.f.x7 normal {n l y}} else {configure_entry .menu16.config.f.x7 disabled {y n l}} - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - configure_entry .menu16.config.f.x8 normal {n l y}} else {configure_entry .menu16.config.f.x8 disabled {y n l}} - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { - configure_entry .menu16.config.f.x9 normal {n l y}} else {configure_entry .menu16.config.f.x9 disabled {y n l}} -} - - -proc update_define_menu16 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_MCTRL_LEON2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT&15]} else {set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT|16]} - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT&15]} else {set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT|16]} - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS&15]} else {set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS|16]} - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM&15]} else {set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM|16]} - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS&15]} else {set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS|16]} - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64&15]} else {set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64|16]} - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK&15]} else {set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK|16]} - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE&15]} else {set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE|16]} - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { - set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE&15]} else {set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE|16]} -} - - -proc menu17 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 17} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 17]] - message $w.m -width 400 -aspect 300 -text \ - "PC133 SDRAM controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "PC133 SDRAM controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 17; catch {destroy .menu14}; unregister_active 14; menu18 .menu18 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 17 0 "Enable PC133 SDRAM controller " CONFIG_SDCTRL - bool $w.config.f 17 1 "64-bit SDRAM data bus" CONFIG_SDCTRL_BUS64 - bool $w.config.f 17 2 "Unsynchronized sdclock" CONFIG_SDCTRL_INVCLK - bool $w.config.f 17 3 "Enable page burst operation " CONFIG_SDCTRL_PAGE - bool $w.config.f 17 4 "Enable programmable page burst " CONFIG_SDCTRL_PROGPAGE - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu17 {} { - global CONFIG_SDCTRL - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x1 normal {n l y}} else {configure_entry .menu17.config.f.x1 disabled {y n l}} - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x2 normal {n l y}} else {configure_entry .menu17.config.f.x2 disabled {y n l}} - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x3 normal {n l y}} else {configure_entry .menu17.config.f.x3 disabled {y n l}} - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then { - configure_entry .menu17.config.f.x4 normal {n l y}} else {configure_entry .menu17.config.f.x4 disabled {y n l}} -} - - -proc update_define_menu17 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SDCTRL - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_BUS64 [expr $CONFIG_SDCTRL_BUS64&15]} else {set CONFIG_SDCTRL_BUS64 [expr $CONFIG_SDCTRL_BUS64|16]} - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_INVCLK [expr $CONFIG_SDCTRL_INVCLK&15]} else {set CONFIG_SDCTRL_INVCLK [expr $CONFIG_SDCTRL_INVCLK|16]} - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_PAGE [expr $CONFIG_SDCTRL_PAGE&15]} else {set CONFIG_SDCTRL_PAGE [expr $CONFIG_SDCTRL_PAGE|16]} - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then { - set CONFIG_SDCTRL_PROGPAGE [expr $CONFIG_SDCTRL_PROGPAGE&15]} else {set CONFIG_SDCTRL_PROGPAGE [expr $CONFIG_SDCTRL_PROGPAGE|16]} -} - - -proc menu18 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 18} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 18]] - message $w.m -width 400 -aspect 300 -text \ - "On-chip RAM/ROM " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "On-chip RAM/ROM " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu19 .menu19 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 18 0 "On-chip AHB ROM " CONFIG_AHBROM_ENABLE - hex $w.config.f 18 1 "ROM start address (haddr\[31:20\]) " CONFIG_AHBROM_START - bool $w.config.f 18 2 "Pipelined ROM access " CONFIG_AHBROM_PIPE - bool $w.config.f 18 3 "On-chip AHB RAM " CONFIG_AHBRAM_ENABLE - global tmpvar_28 - minimenu $w.config.f 18 4 "AHB RAM size (Kbyte)" tmpvar_28 CONFIG_AHBRAM_SZ1 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB RAM size (Kbyte)\"" - $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_28 -value "1" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_28 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_28 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_28 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_28 -value "16" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_28 -value "32" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "64" -variable tmpvar_28 -value "64" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 7 - hex $w.config.f 18 5 "RAM start address (haddr\[31:20\]) " CONFIG_AHBRAM_START - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu18 {} { - global CONFIG_AHBROM_ENABLE - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {.menu18.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x1.l configure -state normal; } else {.menu18.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x1.l configure -state disabled} - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then { - configure_entry .menu18.config.f.x2 normal {n l y}} else {configure_entry .menu18.config.f.x2 disabled {y n l}} - global CONFIG_AHBRAM_ENABLE - if {($CONFIG_AHBRAM_ENABLE == 1)} then {configure_entry .menu18.config.f.x4 normal {x l}} else {configure_entry .menu18.config.f.x4 disabled {x l}} - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {.menu18.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x5.l configure -state normal; } else {.menu18.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x5.l configure -state disabled} -} - - -proc update_define_menu18 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_AHBROM_ENABLE - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {validate_hex CONFIG_AHBROM_START "$CONFIG_AHBROM_START" 000} - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then { - set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE&15]} else {set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE|16]} - global tmpvar_28 - global CONFIG_AHBRAM_SZ1 - if {$tmpvar_28 == "1"} then {set CONFIG_AHBRAM_SZ1 1} else {set CONFIG_AHBRAM_SZ1 0} - global CONFIG_AHBRAM_SZ2 - if {$tmpvar_28 == "2"} then {set CONFIG_AHBRAM_SZ2 1} else {set CONFIG_AHBRAM_SZ2 0} - global CONFIG_AHBRAM_SZ4 - if {$tmpvar_28 == "4"} then {set CONFIG_AHBRAM_SZ4 1} else {set CONFIG_AHBRAM_SZ4 0} - global CONFIG_AHBRAM_SZ8 - if {$tmpvar_28 == "8"} then {set CONFIG_AHBRAM_SZ8 1} else {set CONFIG_AHBRAM_SZ8 0} - global CONFIG_AHBRAM_SZ16 - if {$tmpvar_28 == "16"} then {set CONFIG_AHBRAM_SZ16 1} else {set CONFIG_AHBRAM_SZ16 0} - global CONFIG_AHBRAM_SZ32 - if {$tmpvar_28 == "32"} then {set CONFIG_AHBRAM_SZ32 1} else {set CONFIG_AHBRAM_SZ32 0} - global CONFIG_AHBRAM_SZ64 - if {$tmpvar_28 == "64"} then {set CONFIG_AHBRAM_SZ64 1} else {set CONFIG_AHBRAM_SZ64 0} - global CONFIG_AHBRAM_ENABLE - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {validate_hex CONFIG_AHBRAM_START "$CONFIG_AHBRAM_START" A00} -} - - -proc menu19 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 19} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 19]] - message $w.m -width 400 -aspect 300 -text \ - "Ethernet " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Ethernet " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu20 .menu20 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 19 0 "Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH_ENABLE - bool $w.config.f 19 1 "Enable 1000 Mbit support " CONFIG_GRETH_GIGA - global tmpvar_29 - minimenu $w.config.f 19 2 "AHB FIFO size (words) " tmpvar_29 CONFIG_GRETH_FIFO4 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB FIFO size (words) \"" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_29 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_29 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_29 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_29 -value "32" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_29 -value "64" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu19 {} { - global CONFIG_GRETH_ENABLE - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu19.config.f.x1 normal {n l y}} else {configure_entry .menu19.config.f.x1 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {configure_entry .menu19.config.f.x2 normal {x l}} else {configure_entry .menu19.config.f.x2 disabled {x l}} -} - - -proc update_define_menu19 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_GRETH_ENABLE - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1)} then { - set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA&15]} else {set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA|16]} - global tmpvar_29 - global CONFIG_GRETH_FIFO4 - if {$tmpvar_29 == "4"} then {set CONFIG_GRETH_FIFO4 1} else {set CONFIG_GRETH_FIFO4 0} - global CONFIG_GRETH_FIFO8 - if {$tmpvar_29 == "8"} then {set CONFIG_GRETH_FIFO8 1} else {set CONFIG_GRETH_FIFO8 0} - global CONFIG_GRETH_FIFO16 - if {$tmpvar_29 == "16"} then {set CONFIG_GRETH_FIFO16 1} else {set CONFIG_GRETH_FIFO16 0} - global CONFIG_GRETH_FIFO32 - if {$tmpvar_29 == "32"} then {set CONFIG_GRETH_FIFO32 1} else {set CONFIG_GRETH_FIFO32 0} - global CONFIG_GRETH_FIFO64 - if {$tmpvar_29 == "64"} then {set CONFIG_GRETH_FIFO64 1} else {set CONFIG_GRETH_FIFO64 0} -} - - -proc menu20 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 20} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 20]] - message $w.m -width 400 -aspect 300 -text \ - "CAN " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "CAN " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu21 .menu21 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 20 0 "Enable CAN interface " CONFIG_CAN_ENABLE - hex $w.config.f 20 1 "CAN I/O area start address (haddr\[19:8\]) " CONFIG_CANIO - int $w.config.f 20 2 "Interrupt number " CONFIG_CANIRQ - bool $w.config.f 20 3 "Enable loop-back testing " CONFIG_CANLOOP - bool $w.config.f 20 4 "Enable synchronous reset " CONFIG_CAN_SYNCRST - bool $w.config.f 20 5 "Enable FT FIFO memory " CONFIG_CAN_FT - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu20 {} { - global CONFIG_CAN_ENABLE - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {.menu20.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x1.l configure -state normal; } else {.menu20.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x1.l configure -state disabled} - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {.menu20.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x2.l configure -state normal; } else {.menu20.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x2.l configure -state disabled} - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x3 normal {n l y}} else {configure_entry .menu20.config.f.x3 disabled {y n l}} - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x4 normal {n l y}} else {configure_entry .menu20.config.f.x4 disabled {y n l}} - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x5 normal {n l y}} else {configure_entry .menu20.config.f.x5 disabled {y n l}} -} - - -proc update_define_menu20 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_CAN_ENABLE - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {validate_hex CONFIG_CANIO "$CONFIG_CANIO" C00} - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {validate_int CONFIG_CANIRQ "$CONFIG_CANIRQ" 13} - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CANLOOP [expr $CONFIG_CANLOOP&15]} else {set CONFIG_CANLOOP [expr $CONFIG_CANLOOP|16]} - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CAN_SYNCRST [expr $CONFIG_CAN_SYNCRST&15]} else {set CONFIG_CAN_SYNCRST [expr $CONFIG_CAN_SYNCRST|16]} - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CAN_FT [expr $CONFIG_CAN_FT&15]} else {set CONFIG_CAN_FT [expr $CONFIG_CAN_FT|16]} -} - - -proc menu21 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 21} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 21]] - message $w.m -width 400 -aspect 300 -text \ - "PCI " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "PCI " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu22 .menu22 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 21 0 "PCI interface, target-only " CONFIG_PCI_SIMPLE_TARGET - bool $w.config.f 21 1 "PCI interface, master-target " CONFIG_PCI_MASTER_TARGET - bool $w.config.f 21 2 "PCI DMA controller " CONFIG_PCI_MASTER_TARGET_DMA - hex $w.config.f 21 3 "PCI vendor ID" CONFIG_PCI_VENDORID - hex $w.config.f 21 4 "PCI device ID" CONFIG_PCI_DEVICEID - global tmpvar_30 - minimenu $w.config.f 21 5 "PCI FIFO depth" tmpvar_30 CONFIG_PCI_FIFO0 - menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"PCI FIFO depth\"" - $w.config.f.x5.x.menu add radiobutton -label "None" -variable tmpvar_30 -value "None" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "8" -variable tmpvar_30 -value "8" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "16" -variable tmpvar_30 -value "16" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "32" -variable tmpvar_30 -value "32" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_30 -value "64" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "128" -variable tmpvar_30 -value "128" -command "update_active" - menusplit $w $w.config.f.x5.x.menu 6 - hex $w.config.f 21 6 "PCI initiator address (haddr\[31:20\]) " CONFIG_PCI_HADDR - bool $w.config.f 21 7 "PCI arbiter " CONFIG_PCI_ARBITER - bool $w.config.f 21 8 "PCI arbiter APB interface " CONFIG_PCI_ARBITER_APB - int $w.config.f 21 9 "Number of PCI REQ/GNT pairs" CONFIG_PCI_ARBITER_NREQ - bool $w.config.f 21 10 "Enable PCI trace buffer " CONFIG_PCI_TRACE - global tmpvar_31 - minimenu $w.config.f 21 11 "PCI trace buffer depth" tmpvar_31 CONFIG_PCI_TRACE256 - menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"PCI trace buffer depth\"" - $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_31 -value "256" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "512" -variable tmpvar_31 -value "512" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "1024" -variable tmpvar_31 -value "1024" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "2048" -variable tmpvar_31 -value "2048" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "4096" -variable tmpvar_31 -value "4096" -command "update_active" - menusplit $w $w.config.f.x11.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu21 {} { - global CONFIG_PCI_ACTEL - global CONFIG_PCI_SIMPLE_TARGET - if {($CONFIG_PCI_ACTEL != 1)} then { - configure_entry .menu21.config.f.x0 normal {n l y}} else {configure_entry .menu21.config.f.x0 disabled {y n l}} - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then { - configure_entry .menu21.config.f.x1 normal {n l y}} else {configure_entry .menu21.config.f.x1 disabled {y n l}} - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then { - configure_entry .menu21.config.f.x2 normal {n l y}} else {configure_entry .menu21.config.f.x2 disabled {y n l}} - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x3.l configure -state normal; } else {.menu21.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x3.l configure -state disabled} - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x4.l configure -state normal; } else {.menu21.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x4.l configure -state disabled} - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {configure_entry .menu21.config.f.x5 normal {x l}} else {configure_entry .menu21.config.f.x5 disabled {x l}} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x6.l configure -state normal; } else {.menu21.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x6.l configure -state disabled} - global CONFIG_PCI_ARBITER - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then { - configure_entry .menu21.config.f.x8 normal {n l y}} else {configure_entry .menu21.config.f.x8 disabled {y n l}} - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {.menu21.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x9.l configure -state normal; } else {.menu21.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x9.l configure -state disabled} - global CONFIG_PCI_TRACE - if {($CONFIG_PCI_TRACE == 1)} then {configure_entry .menu21.config.f.x11 normal {x l}} else {configure_entry .menu21.config.f.x11 disabled {x l}} -} - - -proc update_define_menu21 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_PCI_ACTEL - global CONFIG_PCI_SIMPLE_TARGET - if {($CONFIG_PCI_ACTEL != 1)} then { - set CONFIG_PCI_SIMPLE_TARGET [expr $CONFIG_PCI_SIMPLE_TARGET&15]} else {set CONFIG_PCI_SIMPLE_TARGET [expr $CONFIG_PCI_SIMPLE_TARGET|16]} - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then { - set CONFIG_PCI_MASTER_TARGET [expr $CONFIG_PCI_MASTER_TARGET&15]} else {set CONFIG_PCI_MASTER_TARGET [expr $CONFIG_PCI_MASTER_TARGET|16]} - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then { - set CONFIG_PCI_MASTER_TARGET_DMA [expr $CONFIG_PCI_MASTER_TARGET_DMA&15]} else {set CONFIG_PCI_MASTER_TARGET_DMA [expr $CONFIG_PCI_MASTER_TARGET_DMA|16]} - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_VENDORID "$CONFIG_PCI_VENDORID" 1AC8} - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_DEVICEID "$CONFIG_PCI_DEVICEID" 0054} - global tmpvar_30 - global CONFIG_PCI_FIFO0 - if {$tmpvar_30 == "None"} then {set CONFIG_PCI_FIFO0 1} else {set CONFIG_PCI_FIFO0 0} - global CONFIG_PCI_FIFO8 - if {$tmpvar_30 == "8"} then {set CONFIG_PCI_FIFO8 1} else {set CONFIG_PCI_FIFO8 0} - global CONFIG_PCI_FIFO16 - if {$tmpvar_30 == "16"} then {set CONFIG_PCI_FIFO16 1} else {set CONFIG_PCI_FIFO16 0} - global CONFIG_PCI_FIFO32 - if {$tmpvar_30 == "32"} then {set CONFIG_PCI_FIFO32 1} else {set CONFIG_PCI_FIFO32 0} - global CONFIG_PCI_FIFO64 - if {$tmpvar_30 == "64"} then {set CONFIG_PCI_FIFO64 1} else {set CONFIG_PCI_FIFO64 0} - global CONFIG_PCI_FIFO128 - if {$tmpvar_30 == "128"} then {set CONFIG_PCI_FIFO128 1} else {set CONFIG_PCI_FIFO128 0} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_HADDR "$CONFIG_PCI_HADDR" E00} - global CONFIG_PCI_ARBITER - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then { - set CONFIG_PCI_ARBITER_APB [expr $CONFIG_PCI_ARBITER_APB&15]} else {set CONFIG_PCI_ARBITER_APB [expr $CONFIG_PCI_ARBITER_APB|16]} - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {validate_int CONFIG_PCI_ARBITER_NREQ "$CONFIG_PCI_ARBITER_NREQ" 4} - global tmpvar_31 - global CONFIG_PCI_TRACE256 - if {$tmpvar_31 == "256"} then {set CONFIG_PCI_TRACE256 1} else {set CONFIG_PCI_TRACE256 0} - global CONFIG_PCI_TRACE512 - if {$tmpvar_31 == "512"} then {set CONFIG_PCI_TRACE512 1} else {set CONFIG_PCI_TRACE512 0} - global CONFIG_PCI_TRACE1024 - if {$tmpvar_31 == "1024"} then {set CONFIG_PCI_TRACE1024 1} else {set CONFIG_PCI_TRACE1024 0} - global CONFIG_PCI_TRACE2048 - if {$tmpvar_31 == "2048"} then {set CONFIG_PCI_TRACE2048 1} else {set CONFIG_PCI_TRACE2048 0} - global CONFIG_PCI_TRACE4096 - if {$tmpvar_31 == "4096"} then {set CONFIG_PCI_TRACE4096 1} else {set CONFIG_PCI_TRACE4096 0} -} - - -proc menu22 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 22} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 22]] - message $w.m -width 400 -aspect 300 -text \ - "Spacewire " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Spacewire " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu23 .menu23 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 22 0 "Enable Spacewire links " CONFIG_SPW_ENABLE - int $w.config.f 22 1 "Number of links (1 - 3)" CONFIG_SPW_NUM - global tmpvar_32 - minimenu $w.config.f 22 2 "AHB RX/TX FIFO size (32-bit words) " tmpvar_32 CONFIG_SPW_AHBFIFO4 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB RX/TX FIFO size (32-bit words) \"" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_32 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_32 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_32 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_32 -value "32" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 4 - global tmpvar_33 - minimenu $w.config.f 22 3 "Receiver FIFO size (bytes) " tmpvar_33 CONFIG_SPW_RXFIFO16 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Receiver FIFO size (bytes) \"" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_33 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_33 -value "32" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "64" -variable tmpvar_33 -value "64" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 3 - bool $w.config.f 22 4 "Enable RMAP protocol " CONFIG_SPW_RMAP - global tmpvar_34 - minimenu $w.config.f 22 5 "RMAP buffer size (bytes) " tmpvar_34 CONFIG_SPW_RMAPBUF2 - menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"RMAP buffer size (bytes) \"" - $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_34 -value "64" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "128" -variable tmpvar_34 -value "128" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "192" -variable tmpvar_34 -value "192" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "256" -variable tmpvar_34 -value "256" -command "update_active" - menusplit $w $w.config.f.x5.x.menu 4 - bool $w.config.f 22 6 "Enable RMAP CRC check " CONFIG_SPW_RMAPCRC - bool $w.config.f 22 7 "Enable Rx unaligned transfers " CONFIG_SPW_RXUNAL - bool $w.config.f 22 8 "Spacewire FIFO protection " CONFIG_SPW_FT - bool $w.config.f 22 9 "Use GRSPWC netlist " CONFIG_SPW_NETLIST - global tmpvar_35 - minimenu $w.config.f 22 10 "Select GRSPW core (GRSPW1/GRSPW2) " tmpvar_35 CONFIG_SPW_GRSPW1 - menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Select GRSPW core (GRSPW1/GRSPW2) \"" - $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_35 -value "1" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_35 -value "2" -command "update_active" - menusplit $w $w.config.f.x10.x.menu 2 - int $w.config.f 22 11 "Number of DMA channels (1 - 4)" CONFIG_SPW_DMACHAN - int $w.config.f 22 12 "Number of ports (1 - 2)" CONFIG_SPW_PORTS - bool $w.config.f 22 13 "Receiver and transmitter uses same clock " CONFIG_SPW_RTSAME - global tmpvar_36 - minimenu $w.config.f 22 14 "Select receiver clock type " tmpvar_36 CONFIG_SPW_RX_SDR - menu $w.config.f.x14.x.menu -tearoffcommand "menutitle \"Select receiver clock type \"" - $w.config.f.x14.x.menu add radiobutton -label "SDR" -variable tmpvar_36 -value "SDR" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "DDR" -variable tmpvar_36 -value "DDR" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "Xor" -variable tmpvar_36 -value "Xor" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "Aeroflex" -variable tmpvar_36 -value "Aeroflex" -command "update_active" - menusplit $w $w.config.f.x14.x.menu 4 - global tmpvar_37 - minimenu $w.config.f 22 15 "Select transmitter clock type " tmpvar_37 CONFIG_SPW_TX_SDR - menu $w.config.f.x15.x.menu -tearoffcommand "menutitle \"Select transmitter clock type \"" - $w.config.f.x15.x.menu add radiobutton -label "SDR" -variable tmpvar_37 -value "SDR" -command "update_active" - $w.config.f.x15.x.menu add radiobutton -label "DDR" -variable tmpvar_37 -value "DDR" -command "update_active" - $w.config.f.x15.x.menu add radiobutton -label "Aeroflex" -variable tmpvar_37 -value "Aeroflex" -command "update_active" - menusplit $w $w.config.f.x15.x.menu 3 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu22 {} { - global CONFIG_SPW_ENABLE - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {.menu22.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x1.l configure -state normal; } else {.menu22.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x1.l configure -state disabled} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x2 normal {x l}} else {configure_entry .menu22.config.f.x2 disabled {x l}} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x3 normal {x l}} else {configure_entry .menu22.config.f.x3 disabled {x l}} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x4 normal {n l y}} else {configure_entry .menu22.config.f.x4 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_RMAP == 1)} then {configure_entry .menu22.config.f.x5 normal {x l}} else {configure_entry .menu22.config.f.x5 disabled {x l}} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x6 normal {n l y}} else {configure_entry .menu22.config.f.x6 disabled {y n l}} - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x7 normal {n l y}} else {configure_entry .menu22.config.f.x7 disabled {y n l}} - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x8 normal {n l y}} else {configure_entry .menu22.config.f.x8 disabled {y n l}} - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x9 normal {n l y}} else {configure_entry .menu22.config.f.x9 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x10 normal {x l}} else {configure_entry .menu22.config.f.x10 disabled {x l}} - global CONFIG_SPW_GRSPW2 - global CONFIG_SPW_DMACHAN - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {.menu22.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x11.l configure -state normal; } else {.menu22.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x11.l configure -state disabled} - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {.menu22.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x12.l configure -state normal; } else {.menu22.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x12.l configure -state disabled} - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - configure_entry .menu22.config.f.x13 normal {n l y}} else {configure_entry .menu22.config.f.x13 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {configure_entry .menu22.config.f.x14 normal {x l}} else {configure_entry .menu22.config.f.x14 disabled {x l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {configure_entry .menu22.config.f.x15 normal {x l}} else {configure_entry .menu22.config.f.x15 disabled {x l}} -} - - -proc update_define_menu22 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SPW_ENABLE - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {validate_int CONFIG_SPW_NUM "$CONFIG_SPW_NUM" 1} - global tmpvar_32 - global CONFIG_SPW_AHBFIFO4 - if {$tmpvar_32 == "4"} then {set CONFIG_SPW_AHBFIFO4 1} else {set CONFIG_SPW_AHBFIFO4 0} - global CONFIG_SPW_AHBFIFO8 - if {$tmpvar_32 == "8"} then {set CONFIG_SPW_AHBFIFO8 1} else {set CONFIG_SPW_AHBFIFO8 0} - global CONFIG_SPW_AHBFIFO16 - if {$tmpvar_32 == "16"} then {set CONFIG_SPW_AHBFIFO16 1} else {set CONFIG_SPW_AHBFIFO16 0} - global CONFIG_SPW_AHBFIFO32 - if {$tmpvar_32 == "32"} then {set CONFIG_SPW_AHBFIFO32 1} else {set CONFIG_SPW_AHBFIFO32 0} - global tmpvar_33 - global CONFIG_SPW_RXFIFO16 - if {$tmpvar_33 == "16"} then {set CONFIG_SPW_RXFIFO16 1} else {set CONFIG_SPW_RXFIFO16 0} - global CONFIG_SPW_RXFIFO32 - if {$tmpvar_33 == "32"} then {set CONFIG_SPW_RXFIFO32 1} else {set CONFIG_SPW_RXFIFO32 0} - global CONFIG_SPW_RXFIFO64 - if {$tmpvar_33 == "64"} then {set CONFIG_SPW_RXFIFO64 1} else {set CONFIG_SPW_RXFIFO64 0} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RMAP [expr $CONFIG_SPW_RMAP&15]} else {set CONFIG_SPW_RMAP [expr $CONFIG_SPW_RMAP|16]} - global tmpvar_34 - global CONFIG_SPW_RMAPBUF2 - if {$tmpvar_34 == "64"} then {set CONFIG_SPW_RMAPBUF2 1} else {set CONFIG_SPW_RMAPBUF2 0} - global CONFIG_SPW_RMAPBUF4 - if {$tmpvar_34 == "128"} then {set CONFIG_SPW_RMAPBUF4 1} else {set CONFIG_SPW_RMAPBUF4 0} - global CONFIG_SPW_RMAPBUF6 - if {$tmpvar_34 == "192"} then {set CONFIG_SPW_RMAPBUF6 1} else {set CONFIG_SPW_RMAPBUF6 0} - global CONFIG_SPW_RMAPBUF8 - if {$tmpvar_34 == "256"} then {set CONFIG_SPW_RMAPBUF8 1} else {set CONFIG_SPW_RMAPBUF8 0} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RMAPCRC [expr $CONFIG_SPW_RMAPCRC&15]} else {set CONFIG_SPW_RMAPCRC [expr $CONFIG_SPW_RMAPCRC|16]} - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RXUNAL [expr $CONFIG_SPW_RXUNAL&15]} else {set CONFIG_SPW_RXUNAL [expr $CONFIG_SPW_RXUNAL|16]} - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_FT [expr $CONFIG_SPW_FT&15]} else {set CONFIG_SPW_FT [expr $CONFIG_SPW_FT|16]} - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_NETLIST [expr $CONFIG_SPW_NETLIST&15]} else {set CONFIG_SPW_NETLIST [expr $CONFIG_SPW_NETLIST|16]} - global tmpvar_35 - global CONFIG_SPW_GRSPW1 - if {$tmpvar_35 == "1"} then {set CONFIG_SPW_GRSPW1 1} else {set CONFIG_SPW_GRSPW1 0} - global CONFIG_SPW_GRSPW2 - if {$tmpvar_35 == "2"} then {set CONFIG_SPW_GRSPW2 1} else {set CONFIG_SPW_GRSPW2 0} - global CONFIG_SPW_DMACHAN - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {validate_int CONFIG_SPW_DMACHAN "$CONFIG_SPW_DMACHAN" 1} - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {validate_int CONFIG_SPW_PORTS "$CONFIG_SPW_PORTS" 1} - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - set CONFIG_SPW_RTSAME [expr $CONFIG_SPW_RTSAME&15]} else {set CONFIG_SPW_RTSAME [expr $CONFIG_SPW_RTSAME|16]} - global tmpvar_36 - global CONFIG_SPW_RX_SDR - if {$tmpvar_36 == "SDR"} then {set CONFIG_SPW_RX_SDR 1} else {set CONFIG_SPW_RX_SDR 0} - global CONFIG_SPW_RX_DDR - if {$tmpvar_36 == "DDR"} then {set CONFIG_SPW_RX_DDR 1} else {set CONFIG_SPW_RX_DDR 0} - global CONFIG_SPW_RX_XOR - if {$tmpvar_36 == "Xor"} then {set CONFIG_SPW_RX_XOR 1} else {set CONFIG_SPW_RX_XOR 0} - global CONFIG_SPW_RX_AFLEX - if {$tmpvar_36 == "Aeroflex"} then {set CONFIG_SPW_RX_AFLEX 1} else {set CONFIG_SPW_RX_AFLEX 0} - global tmpvar_37 - global CONFIG_SPW_TX_SDR - if {$tmpvar_37 == "SDR"} then {set CONFIG_SPW_TX_SDR 1} else {set CONFIG_SPW_TX_SDR 0} - global CONFIG_SPW_TX_DDR - if {$tmpvar_37 == "DDR"} then {set CONFIG_SPW_TX_DDR 1} else {set CONFIG_SPW_TX_DDR 0} - global CONFIG_SPW_TX_AFLEX - if {$tmpvar_37 == "Aeroflex"} then {set CONFIG_SPW_TX_AFLEX 1} else {set CONFIG_SPW_TX_AFLEX 0} -} - - -proc menu23 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 23} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 23]] - message $w.m -width 400 -aspect 300 -text \ - "UARTs, timers and irq control " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "UARTs, timers and irq control " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 23; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 23; catch {destroy .menu13}; unregister_active 13; menu24 .menu24 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 23 0 "Enable console UART " CONFIG_UART1_ENABLE - global tmpvar_38 - minimenu $w.config.f 23 1 "UART1 FIFO depth" tmpvar_38 CONFIG_UA1_FIFO1 - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"UART1 FIFO depth\"" - $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_38 -value "1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_38 -value "2" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_38 -value "4" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_38 -value "8" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_38 -value "16" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_38 -value "32" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 6 - bool $w.config.f 23 2 "Enable secondary UART " CONFIG_UART2_ENABLE - global tmpvar_39 - minimenu $w.config.f 23 3 "UART2 FIFO depth" tmpvar_39 CONFIG_UA2_FIFO1 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"UART2 FIFO depth\"" - $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_39 -value "1" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_39 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_39 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_39 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_39 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_39 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 6 - bool $w.config.f 23 4 "Enable LEON3 interrupt controller " CONFIG_IRQ3_ENABLE - bool $w.config.f 23 5 "Enable secondary interrupts " CONFIG_IRQ3_SEC - int $w.config.f 23 6 "Secondary interrupt number (1 - 15) " CONFIG_IRQ3_NSEC - bool $w.config.f 23 7 "Enable Timer Unit " CONFIG_GPT_ENABLE - int $w.config.f 23 8 "Number of timers (1 - 7) " CONFIG_GPT_NTIM - int $w.config.f 23 9 "Scaler width (2 - 16) " CONFIG_GPT_SW - int $w.config.f 23 10 "Timer width (2 - 32) " CONFIG_GPT_TW - int $w.config.f 23 11 "Timer unit interrupt " CONFIG_GPT_IRQ - bool $w.config.f 23 12 "Separate interrupts " CONFIG_GPT_SEPIRQ - bool $w.config.f 23 13 "Watchdog enable " CONFIG_GPT_WDOGEN - hex $w.config.f 23 14 "Initial watchdog time-out value " CONFIG_GPT_WDOG - bool $w.config.f 23 15 "Enable generic GPIO port " CONFIG_GRGPIO_ENABLE - int $w.config.f 23 16 "GPIO width " CONFIG_GRGPIO_WIDTH - hex $w.config.f 23 17 "GPIO interrupt mask " CONFIG_GRGPIO_IMASK - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu23 {} { - global CONFIG_UART1_ENABLE - if {($CONFIG_UART1_ENABLE == 1)} then {configure_entry .menu23.config.f.x1 normal {x l}} else {configure_entry .menu23.config.f.x1 disabled {x l}} - global CONFIG_UART2_ENABLE - if {($CONFIG_UART2_ENABLE == 1)} then {configure_entry .menu23.config.f.x3 normal {x l}} else {configure_entry .menu23.config.f.x3 disabled {x l}} - global CONFIG_IRQ3_ENABLE - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then { - configure_entry .menu23.config.f.x5 normal {n l y}} else {configure_entry .menu23.config.f.x5 disabled {y n l}} - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {.menu23.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x6.l configure -state normal; } else {.menu23.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x6.l configure -state disabled} - global CONFIG_GPT_ENABLE - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x8.l configure -state normal; } else {.menu23.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x8.l configure -state disabled} - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x9.l configure -state normal; } else {.menu23.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x9.l configure -state disabled} - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x10.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x10.l configure -state normal; } else {.menu23.config.f.x10.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x10.l configure -state disabled} - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x11.l configure -state normal; } else {.menu23.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x11.l configure -state disabled} - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then { - configure_entry .menu23.config.f.x12 normal {n l y}} else {configure_entry .menu23.config.f.x12 disabled {y n l}} - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then { - configure_entry .menu23.config.f.x13 normal {n l y}} else {configure_entry .menu23.config.f.x13 disabled {y n l}} - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {.menu23.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x14.l configure -state normal; } else {.menu23.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x14.l configure -state disabled} - global CONFIG_GRGPIO_ENABLE - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu23.config.f.x16.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x16.l configure -state normal; } else {.menu23.config.f.x16.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x16.l configure -state disabled} - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu23.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x17.l configure -state normal; } else {.menu23.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x17.l configure -state disabled} -} - - -proc update_define_menu23 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_38 - global CONFIG_UA1_FIFO1 - if {$tmpvar_38 == "1"} then {set CONFIG_UA1_FIFO1 1} else {set CONFIG_UA1_FIFO1 0} - global CONFIG_UA1_FIFO2 - if {$tmpvar_38 == "2"} then {set CONFIG_UA1_FIFO2 1} else {set CONFIG_UA1_FIFO2 0} - global CONFIG_UA1_FIFO4 - if {$tmpvar_38 == "4"} then {set CONFIG_UA1_FIFO4 1} else {set CONFIG_UA1_FIFO4 0} - global CONFIG_UA1_FIFO8 - if {$tmpvar_38 == "8"} then {set CONFIG_UA1_FIFO8 1} else {set CONFIG_UA1_FIFO8 0} - global CONFIG_UA1_FIFO16 - if {$tmpvar_38 == "16"} then {set CONFIG_UA1_FIFO16 1} else {set CONFIG_UA1_FIFO16 0} - global CONFIG_UA1_FIFO32 - if {$tmpvar_38 == "32"} then {set CONFIG_UA1_FIFO32 1} else {set CONFIG_UA1_FIFO32 0} - global tmpvar_39 - global CONFIG_UA2_FIFO1 - if {$tmpvar_39 == "1"} then {set CONFIG_UA2_FIFO1 1} else {set CONFIG_UA2_FIFO1 0} - global CONFIG_UA2_FIFO2 - if {$tmpvar_39 == "2"} then {set CONFIG_UA2_FIFO2 1} else {set CONFIG_UA2_FIFO2 0} - global CONFIG_UA2_FIFO4 - if {$tmpvar_39 == "4"} then {set CONFIG_UA2_FIFO4 1} else {set CONFIG_UA2_FIFO4 0} - global CONFIG_UA2_FIFO8 - if {$tmpvar_39 == "8"} then {set CONFIG_UA2_FIFO8 1} else {set CONFIG_UA2_FIFO8 0} - global CONFIG_UA2_FIFO16 - if {$tmpvar_39 == "16"} then {set CONFIG_UA2_FIFO16 1} else {set CONFIG_UA2_FIFO16 0} - global CONFIG_UA2_FIFO32 - if {$tmpvar_39 == "32"} then {set CONFIG_UA2_FIFO32 1} else {set CONFIG_UA2_FIFO32 0} - global CONFIG_IRQ3_ENABLE - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then { - set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC&15]} else {set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC|16]} - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {validate_int CONFIG_IRQ3_NSEC "$CONFIG_IRQ3_NSEC" 12} - global CONFIG_GPT_ENABLE - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_NTIM "$CONFIG_GPT_NTIM" 2} - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_SW "$CONFIG_GPT_SW" 8} - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_TW "$CONFIG_GPT_TW" 32} - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_IRQ "$CONFIG_GPT_IRQ" 8} - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then { - set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ&15]} else {set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ|16]} - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then { - set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN&15]} else {set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN|16]} - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {validate_hex CONFIG_GPT_WDOG "$CONFIG_GPT_WDOG" FFFF} - global CONFIG_GRGPIO_ENABLE - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_int CONFIG_GRGPIO_WIDTH "$CONFIG_GRGPIO_WIDTH" 8} - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_hex CONFIG_GRGPIO_IMASK "$CONFIG_GRGPIO_IMASK" 0000} -} - - -menu_option menu24 24 "VHDL Debugging " -proc menu24 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 24} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 24]] - message $w.m -width 400 -aspect 300 -text \ - "VHDL Debugging " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "VHDL Debugging " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 24; break" - set nextscript "catch {focus $oldFocus}; menu25 .menu25 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - $w.f.next configure -state disabled - bind all "puts \"no more menus\" " - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 24 0 "Accelerated UART tracing " CONFIG_DEBUG_UART - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu24 {} { -} - - -proc update_define_menu24 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc update_mainmenu {} { -} - - -set tmpvar_0 "(not set)" -set CONFIG_SYN_INFERRED 0 -set CONFIG_SYN_STRATIX 0 -set CONFIG_SYN_STRATIXII 0 -set CONFIG_SYN_STRATIXIII 0 -set CONFIG_SYN_CYCLONEIII 0 -set CONFIG_SYN_ALTERA 0 -set CONFIG_SYN_AXCEL 0 -set CONFIG_SYN_PROASIC 0 -set CONFIG_SYN_PROASICPLUS 0 -set CONFIG_SYN_PROASIC3 0 -set CONFIG_SYN_UT025CRH 0 -set CONFIG_SYN_ATC18 0 -set CONFIG_SYN_ATC18RHA 0 -set CONFIG_SYN_CUSTOM1 0 -set CONFIG_SYN_EASIC90 0 -set CONFIG_SYN_IHP25 0 -set CONFIG_SYN_IHP25RH 0 -set CONFIG_SYN_LATTICE 0 -set CONFIG_SYN_ECLIPSE 0 -set CONFIG_SYN_PEREGRINE 0 -set CONFIG_SYN_RH_LIB18T 0 -set CONFIG_SYN_RHUMC 0 -set CONFIG_SYN_SMIC13 0 -set CONFIG_SYN_SPARTAN2 0 -set CONFIG_SYN_SPARTAN3 0 -set CONFIG_SYN_SPARTAN3E 0 -set CONFIG_SYN_VIRTEX 0 -set CONFIG_SYN_VIRTEXE 0 -set CONFIG_SYN_VIRTEX2 0 -set CONFIG_SYN_VIRTEX4 0 -set CONFIG_SYN_VIRTEX5 0 -set CONFIG_SYN_UMC 0 -set CONFIG_SYN_TSMC90 0 -set tmpvar_1 "(not set)" -set CONFIG_MEM_INFERRED 0 -set CONFIG_MEM_UMC 0 -set CONFIG_MEM_RHUMC 0 -set CONFIG_MEM_ARTISAN 0 -set CONFIG_MEM_CUSTOM1 0 -set CONFIG_MEM_VIRAGE 0 -set CONFIG_MEM_VIRAGE90 0 -set CONFIG_SYN_INFER_RAM 0 -set CONFIG_SYN_INFER_PADS 0 -set CONFIG_SYN_NO_ASYNC 0 -set CONFIG_SYN_SCAN 0 -set tmpvar_2 "(not set)" -set CONFIG_CLK_INFERRED 0 -set CONFIG_CLK_HCLKBUF 0 -set CONFIG_CLK_ALTDLL 0 -set CONFIG_CLK_LATDLL 0 -set CONFIG_CLK_PRO3PLL 0 -set CONFIG_CLK_LIB18T 0 -set CONFIG_CLK_RHUMC 0 -set CONFIG_CLK_CLKDLL 0 -set CONFIG_CLK_DCM 0 -set CONFIG_CLK_MUL 2 -set CONFIG_CLK_DIV 2 -set CONFIG_OCLK_DIV 2 -set CONFIG_PCI_CLKDLL 0 -set CONFIG_CLK_NOFB 0 -set CONFIG_PCI_SYSCLK 0 -set CONFIG_LEON3 0 -set CONFIG_PROC_NUM 1 -set CONFIG_IU_NWINDOWS 8 -set CONFIG_IU_V8MULDIV 0 -set tmpvar_3 "(not set)" -set CONFIG_IU_MUL_LATENCY_2 0 -set CONFIG_IU_MUL_LATENCY_4 0 -set CONFIG_IU_MUL_LATENCY_5 0 -set CONFIG_IU_MUL_MAC 0 -set CONFIG_IU_SVT 0 -set CONFIG_IU_LDELAY 1 -set CONFIG_IU_WATCHPOINTS 0 -set CONFIG_PWD 0 -set CONFIG_IU_RSTADDR 00000 -set CONFIG_FPU_ENABLE 0 -set tmpvar_4 "(not set)" -set CONFIG_FPU_GRFPU 0 -set CONFIG_FPU_GRFPULITE 0 -set CONFIG_FPU_MEIKO 0 -set tmpvar_5 "(not set)" -set CONFIG_FPU_GRFPU_INFMUL 0 -set CONFIG_FPU_GRFPU_DWMUL 0 -set CONFIG_FPU_GRFPU_MODGEN 0 -set tmpvar_6 "(not set)" -set CONFIG_FPU_GRFPC0 0 -set CONFIG_FPU_GRFPC1 0 -set CONFIG_FPU_GRFPC2 0 -set CONFIG_FPU_NETLIST 0 -set CONFIG_ICACHE_ENABLE 0 -set tmpvar_7 "(not set)" -set CONFIG_ICACHE_ASSO1 0 -set CONFIG_ICACHE_ASSO2 0 -set CONFIG_ICACHE_ASSO3 0 -set CONFIG_ICACHE_ASSO4 0 -set tmpvar_8 "(not set)" -set CONFIG_ICACHE_SZ1 0 -set CONFIG_ICACHE_SZ2 0 -set CONFIG_ICACHE_SZ4 0 -set CONFIG_ICACHE_SZ8 0 -set CONFIG_ICACHE_SZ16 0 -set CONFIG_ICACHE_SZ32 0 -set CONFIG_ICACHE_SZ64 0 -set CONFIG_ICACHE_SZ128 0 -set CONFIG_ICACHE_SZ256 0 -set tmpvar_9 "(not set)" -set CONFIG_ICACHE_LZ16 0 -set CONFIG_ICACHE_LZ32 0 -set tmpvar_10 "(not set)" -set CONFIG_ICACHE_ALGORND 0 -set CONFIG_ICACHE_ALGOLRR 0 -set CONFIG_ICACHE_ALGOLRU 0 -set CONFIG_ICACHE_LOCK 0 -set CONFIG_ICACHE_LRAM 0 -set tmpvar_11 "(not set)" -set CONFIG_ICACHE_LRAM_SZ1 0 -set CONFIG_ICACHE_LRAM_SZ2 0 -set CONFIG_ICACHE_LRAM_SZ4 0 -set CONFIG_ICACHE_LRAM_SZ8 0 -set CONFIG_ICACHE_LRAM_SZ16 0 -set CONFIG_ICACHE_LRAM_SZ32 0 -set CONFIG_ICACHE_LRAM_SZ64 0 -set CONFIG_ICACHE_LRAM_SZ128 0 -set CONFIG_ICACHE_LRAM_SZ256 0 -set CONFIG_ICACHE_LRSTART 8e -set CONFIG_DCACHE_ENABLE 0 -set tmpvar_12 "(not set)" -set CONFIG_DCACHE_ASSO1 0 -set CONFIG_DCACHE_ASSO2 0 -set CONFIG_DCACHE_ASSO3 0 -set CONFIG_DCACHE_ASSO4 0 -set tmpvar_13 "(not set)" -set CONFIG_DCACHE_SZ1 0 -set CONFIG_DCACHE_SZ2 0 -set CONFIG_DCACHE_SZ4 0 -set CONFIG_DCACHE_SZ8 0 -set CONFIG_DCACHE_SZ16 0 -set CONFIG_DCACHE_SZ32 0 -set CONFIG_DCACHE_SZ64 0 -set CONFIG_DCACHE_SZ128 0 -set CONFIG_DCACHE_SZ256 0 -set tmpvar_14 "(not set)" -set CONFIG_DCACHE_LZ16 0 -set CONFIG_DCACHE_LZ32 0 -set tmpvar_15 "(not set)" -set CONFIG_DCACHE_ALGORND 0 -set CONFIG_DCACHE_ALGOLRR 0 -set CONFIG_DCACHE_ALGOLRU 0 -set CONFIG_DCACHE_LOCK 0 -set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 -set CONFIG_DCACHE_SNOOP_SEPTAG 0 -set CONFIG_CACHE_FIXED 0 -set CONFIG_DCACHE_LRAM 0 -set tmpvar_16 "(not set)" -set CONFIG_DCACHE_LRAM_SZ1 0 -set CONFIG_DCACHE_LRAM_SZ2 0 -set CONFIG_DCACHE_LRAM_SZ4 0 -set CONFIG_DCACHE_LRAM_SZ8 0 -set CONFIG_DCACHE_LRAM_SZ16 0 -set CONFIG_DCACHE_LRAM_SZ32 0 -set CONFIG_DCACHE_LRAM_SZ64 0 -set CONFIG_DCACHE_LRAM_SZ128 0 -set CONFIG_DCACHE_LRAM_SZ256 0 -set CONFIG_DCACHE_LRSTART 8f -set CONFIG_MMU_ENABLE 0 -set tmpvar_17 "(not set)" -set CONFIG_MMU_COMBINED 0 -set CONFIG_MMU_SPLIT 0 -set tmpvar_18 "(not set)" -set CONFIG_MMU_REPARRAY 0 -set CONFIG_MMU_REPINCREMENT 0 -set tmpvar_19 "(not set)" -set CONFIG_MMU_I2 0 -set CONFIG_MMU_I4 0 -set CONFIG_MMU_I8 0 -set CONFIG_MMU_I16 0 -set CONFIG_MMU_I32 0 -set tmpvar_20 "(not set)" -set CONFIG_MMU_D2 0 -set CONFIG_MMU_D4 0 -set CONFIG_MMU_D8 0 -set CONFIG_MMU_D16 0 -set CONFIG_MMU_D32 0 -set CONFIG_MMU_FASTWB 0 -set tmpvar_21 "(not set)" -set CONFIG_MMU_PAGE_4K 0 -set CONFIG_MMU_PAGE_8K 0 -set CONFIG_MMU_PAGE_16K 0 -set CONFIG_MMU_PAGE_32K 0 -set CONFIG_MMU_PAGE_PROG 0 -set CONFIG_DSU_ENABLE 0 -set CONFIG_DSU_ITRACE 0 -set tmpvar_22 "(not set)" -set CONFIG_DSU_ITRACESZ1 0 -set CONFIG_DSU_ITRACESZ2 0 -set CONFIG_DSU_ITRACESZ4 0 -set CONFIG_DSU_ITRACESZ8 0 -set CONFIG_DSU_ITRACESZ16 0 -set CONFIG_DSU_ATRACE 0 -set tmpvar_23 "(not set)" -set CONFIG_DSU_ATRACESZ1 0 -set CONFIG_DSU_ATRACESZ2 0 -set CONFIG_DSU_ATRACESZ4 0 -set CONFIG_DSU_ATRACESZ8 0 -set CONFIG_DSU_ATRACESZ16 0 -set CONFIG_IU_DISAS 0 -set CONFIG_IU_DISAS_NET 0 -set CONFIG_DEBUG_PC32 0 -set CONFIG_AHB_DEFMST 0 -set CONFIG_AHB_RROBIN 0 -set CONFIG_AHB_SPLIT 0 -set CONFIG_AHB_IOADDR FFF -set CONFIG_APB_HADDR 800 -set CONFIG_AHB_MON 0 -set CONFIG_AHB_MONERR 0 -set CONFIG_AHB_MONWAR 0 -set CONFIG_DSU_UART 0 -set CONFIG_DSU_JTAG 0 -set CONFIG_DSU_ETH 0 -set tmpvar_25 "(not set)" -set CONFIG_DSU_ETHSZ1 0 -set CONFIG_DSU_ETHSZ2 0 -set CONFIG_DSU_ETHSZ4 0 -set CONFIG_DSU_ETHSZ8 0 -set CONFIG_DSU_ETHSZ16 0 -set CONFIG_DSU_IPMSB C0A8 -set CONFIG_DSU_IPLSB 0033 -set CONFIG_DSU_ETHMSB 020000 -set CONFIG_DSU_ETHLSB 000000 -set CONFIG_DSU_ETH_PROG 0 -set CONFIG_SRCTRL 0 -set CONFIG_SRCTRL_8BIT 0 -set CONFIG_SRCTRL_PROMWS 3 -set CONFIG_SRCTRL_RAMWS 0 -set CONFIG_SRCTRL_IOWS 0 -set CONFIG_SRCTRL_RMW 0 -set tmpvar_26 "(not set)" -set CONFIG_SRCTRL_SRBANKS1 0 -set CONFIG_SRCTRL_SRBANKS2 0 -set CONFIG_SRCTRL_SRBANKS3 0 -set CONFIG_SRCTRL_SRBANKS4 0 -set CONFIG_SRCTRL_SRBANKS5 0 -set tmpvar_27 "(not set)" -set CONFIG_SRCTRL_BANKSZ0 0 -set CONFIG_SRCTRL_BANKSZ1 0 -set CONFIG_SRCTRL_BANKSZ2 0 -set CONFIG_SRCTRL_BANKSZ3 0 -set CONFIG_SRCTRL_BANKSZ4 0 -set CONFIG_SRCTRL_BANKSZ5 0 -set CONFIG_SRCTRL_BANKSZ6 0 -set CONFIG_SRCTRL_BANKSZ7 0 -set CONFIG_SRCTRL_BANKSZ8 0 -set CONFIG_SRCTRL_BANKSZ9 0 -set CONFIG_SRCTRL_BANKSZ10 0 -set CONFIG_SRCTRL_BANKSZ11 0 -set CONFIG_SRCTRL_BANKSZ12 0 -set CONFIG_SRCTRL_BANKSZ13 0 -set CONFIG_SRCTRL_ROMASEL 19 -set CONFIG_MCTRL_LEON2 0 -set CONFIG_MCTRL_8BIT 0 -set CONFIG_MCTRL_16BIT 0 -set CONFIG_MCTRL_5CS 0 -set CONFIG_MCTRL_SDRAM 0 -set CONFIG_MCTRL_SDRAM_SEPBUS 0 -set CONFIG_MCTRL_SDRAM_BUS64 0 -set CONFIG_MCTRL_SDRAM_INVCLK 0 -set CONFIG_MCTRL_PAGE 0 -set CONFIG_MCTRL_PROGPAGE 0 -set CONFIG_SDCTRL 0 -set CONFIG_SDCTRL_BUS64 0 -set CONFIG_SDCTRL_INVCLK 0 -set CONFIG_SDCTRL_PAGE 0 -set CONFIG_SDCTRL_PROGPAGE 0 -set CONFIG_AHBROM_ENABLE 0 -set CONFIG_AHBROM_START 000 -set CONFIG_AHBROM_PIPE 0 -set CONFIG_AHBRAM_ENABLE 0 -set tmpvar_28 "(not set)" -set CONFIG_AHBRAM_SZ1 0 -set CONFIG_AHBRAM_SZ2 0 -set CONFIG_AHBRAM_SZ4 0 -set CONFIG_AHBRAM_SZ8 0 -set CONFIG_AHBRAM_SZ16 0 -set CONFIG_AHBRAM_SZ32 0 -set CONFIG_AHBRAM_SZ64 0 -set CONFIG_AHBRAM_START A00 -set CONFIG_GRETH_ENABLE 0 -set CONFIG_GRETH_GIGA 0 -set tmpvar_29 "(not set)" -set CONFIG_GRETH_FIFO4 0 -set CONFIG_GRETH_FIFO8 0 -set CONFIG_GRETH_FIFO16 0 -set CONFIG_GRETH_FIFO32 0 -set CONFIG_GRETH_FIFO64 0 -set CONFIG_CAN_ENABLE 0 -set CONFIG_CANIO C00 -set CONFIG_CANIRQ 13 -set CONFIG_CANLOOP 0 -set CONFIG_CAN_SYNCRST 0 -set CONFIG_CAN_FT 0 -set CONFIG_PCI_SIMPLE_TARGET 0 -set CONFIG_PCI_MASTER_TARGET 0 -set CONFIG_PCI_MASTER_TARGET_DMA 0 -set CONFIG_PCI_VENDORID 1AC8 -set CONFIG_PCI_DEVICEID 0054 -set tmpvar_30 "(not set)" -set CONFIG_PCI_FIFO0 0 -set CONFIG_PCI_FIFO8 0 -set CONFIG_PCI_FIFO16 0 -set CONFIG_PCI_FIFO32 0 -set CONFIG_PCI_FIFO64 0 -set CONFIG_PCI_FIFO128 0 -set CONFIG_PCI_HADDR E00 -set CONFIG_PCI_ARBITER 0 -set CONFIG_PCI_ARBITER_APB 0 -set CONFIG_PCI_ARBITER_NREQ 4 -set CONFIG_PCI_TRACE 0 -set tmpvar_31 "(not set)" -set CONFIG_PCI_TRACE256 0 -set CONFIG_PCI_TRACE512 0 -set CONFIG_PCI_TRACE1024 0 -set CONFIG_PCI_TRACE2048 0 -set CONFIG_PCI_TRACE4096 0 -set CONFIG_SPW_ENABLE 0 -set CONFIG_SPW_NUM 1 -set tmpvar_32 "(not set)" -set CONFIG_SPW_AHBFIFO4 0 -set CONFIG_SPW_AHBFIFO8 0 -set CONFIG_SPW_AHBFIFO16 0 -set CONFIG_SPW_AHBFIFO32 0 -set tmpvar_33 "(not set)" -set CONFIG_SPW_RXFIFO16 0 -set CONFIG_SPW_RXFIFO32 0 -set CONFIG_SPW_RXFIFO64 0 -set CONFIG_SPW_RMAP 0 -set tmpvar_34 "(not set)" -set CONFIG_SPW_RMAPBUF2 0 -set CONFIG_SPW_RMAPBUF4 0 -set CONFIG_SPW_RMAPBUF6 0 -set CONFIG_SPW_RMAPBUF8 0 -set CONFIG_SPW_RMAPCRC 0 -set CONFIG_SPW_RXUNAL 0 -set CONFIG_SPW_FT 0 -set CONFIG_SPW_NETLIST 0 -set tmpvar_35 "(not set)" -set CONFIG_SPW_GRSPW1 0 -set CONFIG_SPW_GRSPW2 0 -set CONFIG_SPW_DMACHAN 1 -set CONFIG_SPW_PORTS 1 -set CONFIG_SPW_RTSAME 0 -set tmpvar_36 "(not set)" -set CONFIG_SPW_RX_SDR 0 -set CONFIG_SPW_RX_DDR 0 -set CONFIG_SPW_RX_XOR 0 -set CONFIG_SPW_RX_AFLEX 0 -set tmpvar_37 "(not set)" -set CONFIG_SPW_TX_SDR 0 -set CONFIG_SPW_TX_DDR 0 -set CONFIG_SPW_TX_AFLEX 0 -set CONFIG_UART1_ENABLE 0 -set tmpvar_38 "(not set)" -set CONFIG_UA1_FIFO1 0 -set CONFIG_UA1_FIFO2 0 -set CONFIG_UA1_FIFO4 0 -set CONFIG_UA1_FIFO8 0 -set CONFIG_UA1_FIFO16 0 -set CONFIG_UA1_FIFO32 0 -set CONFIG_UART2_ENABLE 0 -set tmpvar_39 "(not set)" -set CONFIG_UA2_FIFO1 0 -set CONFIG_UA2_FIFO2 0 -set CONFIG_UA2_FIFO4 0 -set CONFIG_UA2_FIFO8 0 -set CONFIG_UA2_FIFO16 0 -set CONFIG_UA2_FIFO32 0 -set CONFIG_IRQ3_ENABLE 0 -set CONFIG_IRQ3_SEC 0 -set CONFIG_IRQ3_NSEC 12 -set CONFIG_GPT_ENABLE 0 -set CONFIG_GPT_NTIM 2 -set CONFIG_GPT_SW 8 -set CONFIG_GPT_TW 32 -set CONFIG_GPT_IRQ 8 -set CONFIG_GPT_SEPIRQ 0 -set CONFIG_GPT_WDOGEN 0 -set CONFIG_GPT_WDOG FFFF -set CONFIG_GRGPIO_ENABLE 0 -set CONFIG_GRGPIO_WIDTH 8 -set CONFIG_GRGPIO_IMASK 0000 -set CONFIG_DEBUG_UART 0 -set CONFIG_SYN_ARTISAN 4 -set CONFIG_PCI_ENABLE 4 -set CONFIG_HAS_SHARED_GRFPU 4 -set CONFIG_FPU_GRFPU_SH 4 -set CONFIG_LEON3FT_PRESENT 4 -set CONFIG_LEON3FT_EN 4 -set CONFIG_IUFT_NONE 4 -set CONFIG_IUFT_PAR 4 -set CONFIG_IUFT_DMR 4 -set CONFIG_IUFT_BCH 4 -set CONFIG_IUFT_TMR 4 -set CONFIG_FPUFT_EN 4 -set CONFIG_RF_ERRINJ 4 -set CONFIG_CACHE_FT_EN 4 -set CONFIG_CACHE_ERRINJ 4 -set CONFIG_LEON3_NETLIST 4 -set CONFIG_PCI_ACTEL 4 -set CONFIG_MODULES 4 -proc writeconfig {file1 file2} { - set cfg [open $file1 w] - set autocfg [open $file2 w] - set notmod 1 - set notset 0 - puts $cfg "#" - puts $cfg "# Automatically generated make config: don't edit" - puts $cfg "#" - puts $autocfg "/*" - puts $autocfg " * Automatically generated C config: don't edit" - puts $autocfg " */" - puts $autocfg "#define AUTOCONF_INCLUDED" - write_comment $cfg $autocfg "Synthesis " - global tmpvar_0 - - if { $tmpvar_0 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-Stratix" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-StratixII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-StratixIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-CycloneIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-Others" } then { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Axcelerator" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Proasic" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-ProasicPlus" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Proasic3" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 0 [list $notmod] 2 } - if { $tmpvar_0 == "Aeroflex-UT025CRH" } then { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 0 [list $notmod] 2 } - if { $tmpvar_0 == "Atmel-ATC18" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 0 [list $notmod] 2 } - if { $tmpvar_0 == "Atmel-ATC18RHA" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 0 [list $notmod] 2 } - if { $tmpvar_0 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 0 [list $notmod] 2 } - if { $tmpvar_0 == "eASIC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 0 [list $notmod] 2 } - if { $tmpvar_0 == "IHP25" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 0 [list $notmod] 2 } - if { $tmpvar_0 == "IHP25RH" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 0 [list $notmod] 2 } - if { $tmpvar_0 == "Lattice-EC/ECP/XP" } then { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Quicklogic-Eclipse" } then { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Peregrine" } then { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 0 [list $notmod] 2 } - if { $tmpvar_0 == "RH-LIB18T" } then { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 0 [list $notmod] 2 } - if { $tmpvar_0 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_0 == "SMIC130" } then { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan2" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan3" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan3E" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-VirtexE" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex2" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex4" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex5" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 0 [list $notmod] 2 } - if { $tmpvar_0 == "UMC180" } then { write_tristate $cfg $autocfg CONFIG_SYN_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UMC 0 [list $notmod] 2 } - if { $tmpvar_0 == "TSMC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 0 [list $notmod] 2 } - global tmpvar_1 - global CONFIG_SYN_INFERRED - global CONFIG_SYN_CUSTOM1 - global CONFIG_SYN_ATC18 - global CONFIG_SYN_TSMC90 - global CONFIG_SYN_UMC - global CONFIG_SYN_RHUMC - global CONFIG_SYN_ARTISAN - if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then { - if { $tmpvar_1 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_1 == "UMC18" } then { write_tristate $cfg $autocfg CONFIG_MEM_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_UMC 0 [list $notmod] 2 } - if { $tmpvar_1 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_1 == "Artisan" } then { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 0 [list $notmod] 2 } - if { $tmpvar_1 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 0 [list $notmod] 2 } - if { $tmpvar_1 == "Virage" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 0 [list $notmod] 2 } - if { $tmpvar_1 == "Virage-TSMC90" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 0 [list $notmod] 2 }} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_RAM $CONFIG_SYN_INFER_RAM [list $notmod] 2 } - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_PADS $CONFIG_SYN_INFER_PADS [list $notmod] 2 } - global CONFIG_SYN_NO_ASYNC - write_tristate $cfg $autocfg CONFIG_SYN_NO_ASYNC $CONFIG_SYN_NO_ASYNC [list $notmod] 2 - global CONFIG_SYN_SCAN - write_tristate $cfg $autocfg CONFIG_SYN_SCAN $CONFIG_SYN_SCAN [list $notmod] 2 - write_comment $cfg $autocfg "Clock generation" - global tmpvar_2 - - if { $tmpvar_2 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_2 == "Actel-HCLKBUF" } then { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 0 [list $notmod] 2 } - if { $tmpvar_2 == "Altera-ALTPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Lattice-EXPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Proasic3-PLLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "RH-LIB18T-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 0 [list $notmod] 2 } - if { $tmpvar_2 == "DARE-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_2 == "Xilinx-CLKDLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Xilinx-DCM" } then { write_tristate $cfg $autocfg CONFIG_CLK_DCM 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_DCM 0 [list $notmod] 2 } - global CONFIG_CLK_MUL - global CONFIG_CLK_DCM - global CONFIG_CLK_ALTDLL - global CONFIG_CLK_LATDLL - global CONFIG_CLK_PRO3PLL - global CONFIG_CLK_CLKDLL - global CONFIG_CLK_LIB18T - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_MUL $CONFIG_CLK_MUL $notmod } - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_DIV $CONFIG_CLK_DIV $notmod } - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {write_int $cfg $autocfg CONFIG_OCLK_DIV $CONFIG_OCLK_DIV $notmod } - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_CLKDLL $CONFIG_PCI_CLKDLL [list $notmod] 2 } - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_CLK_NOFB $CONFIG_CLK_NOFB [list $notmod] 2 } - global CONFIG_PCI_SYSCLK - global CONFIG_PCI_ENABLE - if {($CONFIG_PCI_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SYSCLK $CONFIG_PCI_SYSCLK [list $notmod] 2 } - global CONFIG_LEON3 - write_tristate $cfg $autocfg CONFIG_LEON3 $CONFIG_LEON3 [list $notmod] 2 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_PROC_NUM $CONFIG_PROC_NUM $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Processor "} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Integer unit "} - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS $CONFIG_IU_NWINDOWS $notmod } - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONFIG_IU_V8MULDIV [list $notmod] 2 } - global tmpvar_3 - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then { - if { $tmpvar_3 == "2-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 0 [list $notmod] 2 } - if { $tmpvar_3 == "4-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 0 [list $notmod] 2 } - if { $tmpvar_3 == "5-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 0 [list $notmod] 2 }} - global CONFIG_IU_MUL_MAC - global CONFIG_IU_MUL_LATENCY_4 - global CONFIG_IU_MUL_LATENCY_5 - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_MAC $CONFIG_IU_MUL_MAC [list $notmod] 2 } - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONFIG_IU_SVT [list $notmod] 2 } - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY $CONFIG_IU_LDELAY $notmod } - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS $CONFIG_IU_WATCHPOINTS $notmod } - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONFIG_PWD [list $notmod] 2 } - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR $CONFIG_IU_RSTADDR $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Floating-point unit"} - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONFIG_FPU_ENABLE [list $notmod] 2 } - global tmpvar_4 - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - if { $tmpvar_4 == "GRFPU" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 0 [list $notmod] 2 } - if { $tmpvar_4 == "GRFPU-LITE" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 0 [list $notmod] 2 } - if { $tmpvar_4 == "Meiko" } then { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 0 [list $notmod] 2 }} - global tmpvar_5 - global CONFIG_FPU_GRFPU - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then { - if { $tmpvar_5 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 0 [list $notmod] 2 } - if { $tmpvar_5 == "DW" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 0 [list $notmod] 2 } - if { $tmpvar_5 == "ModGen" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 0 [list $notmod] 2 }} - global tmpvar_6 - global CONFIG_FPU_GRFPULITE - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then { - if { $tmpvar_6 == "Simple" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 0 [list $notmod] 2 } - if { $tmpvar_6 == "Data-forwarding" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 0 [list $notmod] 2 } - if { $tmpvar_6 == "Non-blocking" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 0 [list $notmod] 2 }} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_NETLIST $CONFIG_FPU_NETLIST [list $notmod] 2 } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Cache system"} - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONFIG_ICACHE_ENABLE [list $notmod] 2 } - global tmpvar_7 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_7 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 0 [list $notmod] 2 } - if { $tmpvar_7 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 0 [list $notmod] 2 } - if { $tmpvar_7 == "3" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 0 [list $notmod] 2 } - if { $tmpvar_7 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 0 [list $notmod] 2 }} - global tmpvar_8 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_8 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 0 [list $notmod] 2 } - if { $tmpvar_8 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 0 [list $notmod] 2 } - if { $tmpvar_8 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 0 [list $notmod] 2 } - if { $tmpvar_8 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 0 [list $notmod] 2 } - if { $tmpvar_8 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 0 [list $notmod] 2 } - if { $tmpvar_8 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 0 [list $notmod] 2 } - if { $tmpvar_8 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 0 [list $notmod] 2 } - if { $tmpvar_8 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 0 [list $notmod] 2 } - if { $tmpvar_8 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 0 [list $notmod] 2 }} - global tmpvar_9 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_9 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 0 [list $notmod] 2 } - if { $tmpvar_9 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 0 [list $notmod] 2 }} - global tmpvar_10 - global CONFIG_ICACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - if { $tmpvar_10 == "Random" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 0 [list $notmod] 2 } - if { $tmpvar_10 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 0 [list $notmod] 2 } - if { $tmpvar_10 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 0 [list $notmod] 2 }} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONFIG_ICACHE_LOCK [list $notmod] 2 } - global CONFIG_ICACHE_LRAM - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM $CONFIG_ICACHE_LRAM [list $notmod] 2 } - global tmpvar_11 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then { - if { $tmpvar_11 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_11 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_11 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_11 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_11 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_11 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_11 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 0 [list $notmod] 2 } - if { $tmpvar_11 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 0 [list $notmod] 2 } - if { $tmpvar_11 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 0 [list $notmod] 2 }} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_ICACHE_LRSTART $CONFIG_ICACHE_LRSTART $notmod } - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONFIG_DCACHE_ENABLE [list $notmod] 2 } - global tmpvar_12 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_12 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 0 [list $notmod] 2 } - if { $tmpvar_12 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 0 [list $notmod] 2 } - if { $tmpvar_12 == "3" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 0 [list $notmod] 2 } - if { $tmpvar_12 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 0 [list $notmod] 2 }} - global tmpvar_13 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_13 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 0 [list $notmod] 2 } - if { $tmpvar_13 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 0 [list $notmod] 2 } - if { $tmpvar_13 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 0 [list $notmod] 2 } - if { $tmpvar_13 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 0 [list $notmod] 2 } - if { $tmpvar_13 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 0 [list $notmod] 2 } - if { $tmpvar_13 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 0 [list $notmod] 2 } - if { $tmpvar_13 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 0 [list $notmod] 2 } - if { $tmpvar_13 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 0 [list $notmod] 2 } - if { $tmpvar_13 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 0 [list $notmod] 2 }} - global tmpvar_14 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_14 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 0 [list $notmod] 2 } - if { $tmpvar_14 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 0 [list $notmod] 2 }} - global tmpvar_15 - global CONFIG_DCACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - if { $tmpvar_15 == "Random" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 0 [list $notmod] 2 } - if { $tmpvar_15 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 0 [list $notmod] 2 } - if { $tmpvar_15 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } - global tmpvar_16 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then { - if { $tmpvar_16 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_16 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_16 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_16 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_16 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_16 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_16 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 0 [list $notmod] 2 } - if { $tmpvar_16 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 0 [list $notmod] 2 } - if { $tmpvar_16 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 0 [list $notmod] 2 }} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_DCACHE_LRSTART $CONFIG_DCACHE_LRSTART $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "MMU"} - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONFIG_MMU_ENABLE [list $notmod] 2 } - global tmpvar_17 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_17 == "combined" } then { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 0 [list $notmod] 2 } - if { $tmpvar_17 == "split" } then { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 0 [list $notmod] 2 }} - global tmpvar_18 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 0 [list $notmod] 2 } - if { $tmpvar_18 == "Increment" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 0 [list $notmod] 2 }} - global tmpvar_19 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_19 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_I2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I2 0 [list $notmod] 2 } - if { $tmpvar_19 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_I4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I4 0 [list $notmod] 2 } - if { $tmpvar_19 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_I8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I8 0 [list $notmod] 2 } - if { $tmpvar_19 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_I16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I16 0 [list $notmod] 2 } - if { $tmpvar_19 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_I32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I32 0 [list $notmod] 2 }} - global tmpvar_20 - global CONFIG_MMU_SPLIT - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - if { $tmpvar_20 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_D2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D2 0 [list $notmod] 2 } - if { $tmpvar_20 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_D4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D4 0 [list $notmod] 2 } - if { $tmpvar_20 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_D8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D8 0 [list $notmod] 2 } - if { $tmpvar_20 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_D16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D16 0 [list $notmod] 2 } - if { $tmpvar_20 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_D32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D32 0 [list $notmod] 2 }} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_FASTWB $CONFIG_MMU_FASTWB [list $notmod] 2 } - global tmpvar_21 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_21 == "4K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 0 [list $notmod] 2 } - if { $tmpvar_21 == "8K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 0 [list $notmod] 2 } - if { $tmpvar_21 == "16K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 0 [list $notmod] 2 } - if { $tmpvar_21 == "32K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 0 [list $notmod] 2 } - if { $tmpvar_21 == "Programmable" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 0 [list $notmod] 2 }} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Debug Support Unit "} - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONFIG_DSU_ENABLE [list $notmod] 2 } - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACE $CONFIG_DSU_ITRACE [list $notmod] 2 } - global tmpvar_22 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then { - if { $tmpvar_22 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 0 [list $notmod] 2 } - if { $tmpvar_22 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 0 [list $notmod] 2 } - if { $tmpvar_22 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 0 [list $notmod] 2 } - if { $tmpvar_22 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 0 [list $notmod] 2 } - if { $tmpvar_22 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 0 [list $notmod] 2 }} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ATRACE $CONFIG_DSU_ATRACE [list $notmod] 2 } - global tmpvar_23 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then { - if { $tmpvar_23 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 0 [list $notmod] 2 } - if { $tmpvar_23 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 0 [list $notmod] 2 } - if { $tmpvar_23 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 0 [list $notmod] 2 } - if { $tmpvar_23 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 0 [list $notmod] 2 } - if { $tmpvar_23 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 0 [list $notmod] 2 }} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Fault-tolerance "} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "VHDL debug settings "} - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS $CONFIG_IU_DISAS [list $notmod] 2 } - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS_NET $CONFIG_IU_DISAS_NET [list $notmod] 2 } - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DEBUG_PC32 $CONFIG_DEBUG_PC32 [list $notmod] 2 } - write_comment $cfg $autocfg "AMBA configuration" - global CONFIG_AHB_DEFMST - write_int $cfg $autocfg CONFIG_AHB_DEFMST $CONFIG_AHB_DEFMST $notmod - global CONFIG_AHB_RROBIN - write_tristate $cfg $autocfg CONFIG_AHB_RROBIN $CONFIG_AHB_RROBIN [list $notmod] 2 - global CONFIG_AHB_SPLIT - write_tristate $cfg $autocfg CONFIG_AHB_SPLIT $CONFIG_AHB_SPLIT [list $notmod] 2 - global CONFIG_AHB_IOADDR - write_hex $cfg $autocfg CONFIG_AHB_IOADDR $CONFIG_AHB_IOADDR $notmod - global CONFIG_APB_HADDR - write_hex $cfg $autocfg CONFIG_APB_HADDR $CONFIG_APB_HADDR $notmod - global CONFIG_AHB_MON - write_tristate $cfg $autocfg CONFIG_AHB_MON $CONFIG_AHB_MON [list $notmod] 2 - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONERR $CONFIG_AHB_MONERR [list $notmod] 2 } - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONWAR $CONFIG_AHB_MONWAR [list $notmod] 2 } - write_comment $cfg $autocfg "Debug Link " - global CONFIG_DSU_UART - write_tristate $cfg $autocfg CONFIG_DSU_UART $CONFIG_DSU_UART [list $notmod] 2 - global CONFIG_DSU_JTAG - write_tristate $cfg $autocfg CONFIG_DSU_JTAG $CONFIG_DSU_JTAG [list $notmod] 2 - global CONFIG_DSU_ETH - global CONFIG_GRETH_ENABLE - if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH $CONFIG_DSU_ETH [list $notmod] 2 } - global tmpvar_25 - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { - if { $tmpvar_25 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 0 [list $notmod] 2 } - if { $tmpvar_25 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 0 [list $notmod] 2 } - if { $tmpvar_25 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 0 [list $notmod] 2 } - if { $tmpvar_25 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 0 [list $notmod] 2 } - if { $tmpvar_25 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 0 [list $notmod] 2 }} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPMSB $CONFIG_DSU_IPMSB $notmod } - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPLSB $CONFIG_DSU_IPLSB $notmod } - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHMSB $CONFIG_DSU_ETHMSB $notmod } - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } - global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } - write_comment $cfg $autocfg "Peripherals " - write_comment $cfg $autocfg "Memory controllers " - write_comment $cfg $autocfg "8/32-bit PROM/SRAM controller " - global CONFIG_SRCTRL - write_tristate $cfg $autocfg CONFIG_SRCTRL $CONFIG_SRCTRL [list $notmod] 2 - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SRCTRL_8BIT $CONFIG_SRCTRL_8BIT [list $notmod] 2 } - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_PROMWS $CONFIG_SRCTRL_PROMWS $notmod } - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_RAMWS $CONFIG_SRCTRL_RAMWS $notmod } - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_IOWS $CONFIG_SRCTRL_IOWS $notmod } - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SRCTRL_RMW $CONFIG_SRCTRL_RMW [list $notmod] 2 } - global tmpvar_26 - if {($CONFIG_SRCTRL == 1)} then { - if { $tmpvar_26 == "1" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS1 0 [list $notmod] 2 } - if { $tmpvar_26 == "2" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS2 0 [list $notmod] 2 } - if { $tmpvar_26 == "3" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS3 0 [list $notmod] 2 } - if { $tmpvar_26 == "4" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS4 0 [list $notmod] 2 } - if { $tmpvar_26 == "5" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS5 0 [list $notmod] 2 }} - global tmpvar_27 - if {($CONFIG_SRCTRL == 1)} then { - if { $tmpvar_27 == "8" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ0 0 [list $notmod] 2 } - if { $tmpvar_27 == "16" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ1 0 [list $notmod] 2 } - if { $tmpvar_27 == "32" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ2 0 [list $notmod] 2 } - if { $tmpvar_27 == "64" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ3 0 [list $notmod] 2 } - if { $tmpvar_27 == "128" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ4 0 [list $notmod] 2 } - if { $tmpvar_27 == "256" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ5 0 [list $notmod] 2 } - if { $tmpvar_27 == "512" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ6 0 [list $notmod] 2 } - if { $tmpvar_27 == "1024" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ7 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ7 0 [list $notmod] 2 } - if { $tmpvar_27 == "2048" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ8 0 [list $notmod] 2 } - if { $tmpvar_27 == "4096" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ9 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ9 0 [list $notmod] 2 } - if { $tmpvar_27 == "8192" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ10 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ10 0 [list $notmod] 2 } - if { $tmpvar_27 == "16384" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ11 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ11 0 [list $notmod] 2 } - if { $tmpvar_27 == "32768" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ12 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ12 0 [list $notmod] 2 } - if { $tmpvar_27 == "65536" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ13 0 [list $notmod] 2 }} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_ROMASEL $CONFIG_SRCTRL_ROMASEL $notmod } - write_comment $cfg $autocfg "Leon2 memory controller " - global CONFIG_MCTRL_LEON2 - write_tristate $cfg $autocfg CONFIG_MCTRL_LEON2 $CONFIG_MCTRL_LEON2 [list $notmod] 2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_8BIT $CONFIG_MCTRL_8BIT [list $notmod] 2 } - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_16BIT $CONFIG_MCTRL_16BIT [list $notmod] 2 } - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_5CS $CONFIG_MCTRL_5CS [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM $CONFIG_MCTRL_SDRAM [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_SEPBUS $CONFIG_MCTRL_SDRAM_SEPBUS [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_BUS64 $CONFIG_MCTRL_SDRAM_BUS64 [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_INVCLK $CONFIG_MCTRL_SDRAM_INVCLK [list $notmod] 2 } - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PAGE $CONFIG_MCTRL_PAGE [list $notmod] 2 } - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PROGPAGE $CONFIG_MCTRL_PROGPAGE [list $notmod] 2 } - write_comment $cfg $autocfg "PC133 SDRAM controller " - global CONFIG_SDCTRL - write_tristate $cfg $autocfg CONFIG_SDCTRL $CONFIG_SDCTRL [list $notmod] 2 - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_BUS64 $CONFIG_SDCTRL_BUS64 [list $notmod] 2 } - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_INVCLK $CONFIG_SDCTRL_INVCLK [list $notmod] 2 } - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_PAGE $CONFIG_SDCTRL_PAGE [list $notmod] 2 } - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_PROGPAGE $CONFIG_SDCTRL_PROGPAGE [list $notmod] 2 } - write_comment $cfg $autocfg "On-chip RAM/ROM " - global CONFIG_AHBROM_ENABLE - write_tristate $cfg $autocfg CONFIG_AHBROM_ENABLE $CONFIG_AHBROM_ENABLE [list $notmod] 2 - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBROM_START $CONFIG_AHBROM_START $notmod } - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBROM_PIPE $CONFIG_AHBROM_PIPE [list $notmod] 2 } - global CONFIG_AHBRAM_ENABLE - write_tristate $cfg $autocfg CONFIG_AHBRAM_ENABLE $CONFIG_AHBRAM_ENABLE [list $notmod] 2 - global tmpvar_28 - if {($CONFIG_AHBRAM_ENABLE == 1)} then { - if { $tmpvar_28 == "1" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_28 == "2" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_28 == "4" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_28 == "8" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_28 == "16" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_28 == "32" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_28 == "64" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 0 [list $notmod] 2 }} - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBRAM_START $CONFIG_AHBRAM_START $notmod } - write_comment $cfg $autocfg "Ethernet " - write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 - if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } - global tmpvar_29 - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - if { $tmpvar_29 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_29 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_29 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_29 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 0 [list $notmod] 2 } - if { $tmpvar_29 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "CAN " - global CONFIG_CAN_ENABLE - write_tristate $cfg $autocfg CONFIG_CAN_ENABLE $CONFIG_CAN_ENABLE [list $notmod] 2 - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CANIO $CONFIG_CANIO $notmod } - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_CANIRQ $CONFIG_CANIRQ $notmod } - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CANLOOP $CONFIG_CANLOOP [list $notmod] 2 } - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CAN_SYNCRST $CONFIG_CAN_SYNCRST [list $notmod] 2 } - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CAN_FT $CONFIG_CAN_FT [list $notmod] 2 } - write_comment $cfg $autocfg "PCI " - global CONFIG_PCI_SIMPLE_TARGET - global CONFIG_PCI_ACTEL - if {($CONFIG_PCI_ACTEL != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SIMPLE_TARGET $CONFIG_PCI_SIMPLE_TARGET [list $notmod] 2 } - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_MASTER_TARGET $CONFIG_PCI_MASTER_TARGET [list $notmod] 2 } - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_MASTER_TARGET_DMA $CONFIG_PCI_MASTER_TARGET_DMA [list $notmod] 2 } - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_VENDORID $CONFIG_PCI_VENDORID $notmod } - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_DEVICEID $CONFIG_PCI_DEVICEID $notmod } - global tmpvar_30 - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then { - if { $tmpvar_30 == "None" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO0 0 [list $notmod] 2 } - if { $tmpvar_30 == "8" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_30 == "16" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_30 == "32" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO32 0 [list $notmod] 2 } - if { $tmpvar_30 == "64" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO64 0 [list $notmod] 2 } - if { $tmpvar_30 == "128" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO128 0 [list $notmod] 2 }} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_HADDR $CONFIG_PCI_HADDR $notmod } - global CONFIG_PCI_ARBITER - write_tristate $cfg $autocfg CONFIG_PCI_ARBITER $CONFIG_PCI_ARBITER [list $notmod] 2 - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_ARBITER_APB $CONFIG_PCI_ARBITER_APB [list $notmod] 2 } - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {write_int $cfg $autocfg CONFIG_PCI_ARBITER_NREQ $CONFIG_PCI_ARBITER_NREQ $notmod } - global CONFIG_PCI_TRACE - write_tristate $cfg $autocfg CONFIG_PCI_TRACE $CONFIG_PCI_TRACE [list $notmod] 2 - global tmpvar_31 - if {($CONFIG_PCI_TRACE == 1)} then { - if { $tmpvar_31 == "256" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE256 0 [list $notmod] 2 } - if { $tmpvar_31 == "512" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE512 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE512 0 [list $notmod] 2 } - if { $tmpvar_31 == "1024" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE1024 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE1024 0 [list $notmod] 2 } - if { $tmpvar_31 == "2048" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE2048 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE2048 0 [list $notmod] 2 } - if { $tmpvar_31 == "4096" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE4096 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE4096 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "Spacewire " - global CONFIG_SPW_ENABLE - write_tristate $cfg $autocfg CONFIG_SPW_ENABLE $CONFIG_SPW_ENABLE [list $notmod] 2 - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPW_NUM $CONFIG_SPW_NUM $notmod } - global tmpvar_32 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_32 == "4" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO4 0 [list $notmod] 2 } - if { $tmpvar_32 == "8" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO8 0 [list $notmod] 2 } - if { $tmpvar_32 == "16" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO16 0 [list $notmod] 2 } - if { $tmpvar_32 == "32" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO32 0 [list $notmod] 2 }} - global tmpvar_33 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_33 == "16" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO16 0 [list $notmod] 2 } - if { $tmpvar_33 == "32" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO32 0 [list $notmod] 2 } - if { $tmpvar_33 == "64" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO64 0 [list $notmod] 2 }} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RMAP $CONFIG_SPW_RMAP [list $notmod] 2 } - global tmpvar_34 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_RMAP == 1)} then { - if { $tmpvar_34 == "64" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF2 0 [list $notmod] 2 } - if { $tmpvar_34 == "128" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF4 0 [list $notmod] 2 } - if { $tmpvar_34 == "192" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF6 0 [list $notmod] 2 } - if { $tmpvar_34 == "256" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF8 0 [list $notmod] 2 }} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RMAPCRC $CONFIG_SPW_RMAPCRC [list $notmod] 2 } - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RXUNAL $CONFIG_SPW_RXUNAL [list $notmod] 2 } - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_FT $CONFIG_SPW_FT [list $notmod] 2 } - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_NETLIST $CONFIG_SPW_NETLIST [list $notmod] 2 } - global tmpvar_35 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_35 == "1" } then { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW1 0 [list $notmod] 2 } - if { $tmpvar_35 == "2" } then { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW2 0 [list $notmod] 2 }} - global CONFIG_SPW_DMACHAN - global CONFIG_SPW_GRSPW2 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_int $cfg $autocfg CONFIG_SPW_DMACHAN $CONFIG_SPW_DMACHAN $notmod } - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_int $cfg $autocfg CONFIG_SPW_PORTS $CONFIG_SPW_PORTS $notmod } - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RTSAME $CONFIG_SPW_RTSAME [list $notmod] 2 } - global tmpvar_36 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - if { $tmpvar_36 == "SDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_SDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_SDR 0 [list $notmod] 2 } - if { $tmpvar_36 == "DDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_DDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_DDR 0 [list $notmod] 2 } - if { $tmpvar_36 == "Xor" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_XOR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_XOR 0 [list $notmod] 2 } - if { $tmpvar_36 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_AFLEX 0 [list $notmod] 2 }} - global tmpvar_37 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - if { $tmpvar_37 == "SDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_SDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_SDR 0 [list $notmod] 2 } - if { $tmpvar_37 == "DDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_DDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_DDR 0 [list $notmod] 2 } - if { $tmpvar_37 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "UARTs, timers and irq control " - global CONFIG_UART1_ENABLE - write_tristate $cfg $autocfg CONFIG_UART1_ENABLE $CONFIG_UART1_ENABLE [list $notmod] 2 - global tmpvar_38 - if {($CONFIG_UART1_ENABLE == 1)} then { - if { $tmpvar_38 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 0 [list $notmod] 2 } - if { $tmpvar_38 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 0 [list $notmod] 2 } - if { $tmpvar_38 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_38 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_38 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_38 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 0 [list $notmod] 2 }} - global CONFIG_UART2_ENABLE - write_tristate $cfg $autocfg CONFIG_UART2_ENABLE $CONFIG_UART2_ENABLE [list $notmod] 2 - global tmpvar_39 - if {($CONFIG_UART2_ENABLE == 1)} then { - if { $tmpvar_39 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO1 0 [list $notmod] 2 } - if { $tmpvar_39 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO2 0 [list $notmod] 2 } - if { $tmpvar_39 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_39 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_39 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_39 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO32 0 [list $notmod] 2 }} - global CONFIG_IRQ3_ENABLE - write_tristate $cfg $autocfg CONFIG_IRQ3_ENABLE $CONFIG_IRQ3_ENABLE [list $notmod] 2 - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_IRQ3_SEC $CONFIG_IRQ3_SEC [list $notmod] 2 } - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {write_int $cfg $autocfg CONFIG_IRQ3_NSEC $CONFIG_IRQ3_NSEC $notmod } - global CONFIG_GPT_ENABLE - write_tristate $cfg $autocfg CONFIG_GPT_ENABLE $CONFIG_GPT_ENABLE [list $notmod] 2 - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_NTIM $CONFIG_GPT_NTIM $notmod } - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_SW $CONFIG_GPT_SW $notmod } - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_TW $CONFIG_GPT_TW $notmod } - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_IRQ $CONFIG_GPT_IRQ $notmod } - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_SEPIRQ $CONFIG_GPT_SEPIRQ [list $notmod] 2 } - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_WDOGEN $CONFIG_GPT_WDOGEN [list $notmod] 2 } - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {write_hex $cfg $autocfg CONFIG_GPT_WDOG $CONFIG_GPT_WDOG $notmod } - global CONFIG_GRGPIO_ENABLE - write_tristate $cfg $autocfg CONFIG_GRGPIO_ENABLE $CONFIG_GRGPIO_ENABLE [list $notmod] 2 - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRGPIO_WIDTH $CONFIG_GRGPIO_WIDTH $notmod } - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_GRGPIO_IMASK $CONFIG_GRGPIO_IMASK $notmod } - write_comment $cfg $autocfg "VHDL Debugging " - global CONFIG_DEBUG_UART - write_tristate $cfg $autocfg CONFIG_DEBUG_UART $CONFIG_DEBUG_UART [list $notmod] 2 - close $cfg - close $autocfg -} - - -proc clear_choices { } { - global CONFIG_SYN_INFERRED; set CONFIG_SYN_INFERRED 0 - global CONFIG_SYN_STRATIX; set CONFIG_SYN_STRATIX 0 - global CONFIG_SYN_STRATIXII; set CONFIG_SYN_STRATIXII 0 - global CONFIG_SYN_STRATIXIII; set CONFIG_SYN_STRATIXIII 0 - global CONFIG_SYN_CYCLONEIII; set CONFIG_SYN_CYCLONEIII 0 - global CONFIG_SYN_ALTERA; set CONFIG_SYN_ALTERA 0 - global CONFIG_SYN_AXCEL; set CONFIG_SYN_AXCEL 0 - global CONFIG_SYN_PROASIC; set CONFIG_SYN_PROASIC 0 - global CONFIG_SYN_PROASICPLUS; set CONFIG_SYN_PROASICPLUS 0 - global CONFIG_SYN_PROASIC3; set CONFIG_SYN_PROASIC3 0 - global CONFIG_SYN_UT025CRH; set CONFIG_SYN_UT025CRH 0 - global CONFIG_SYN_ATC18; set CONFIG_SYN_ATC18 0 - global CONFIG_SYN_ATC18RHA; set CONFIG_SYN_ATC18RHA 0 - global CONFIG_SYN_CUSTOM1; set CONFIG_SYN_CUSTOM1 0 - global CONFIG_SYN_EASIC90; set CONFIG_SYN_EASIC90 0 - global CONFIG_SYN_IHP25; set CONFIG_SYN_IHP25 0 - global CONFIG_SYN_IHP25RH; set CONFIG_SYN_IHP25RH 0 - global CONFIG_SYN_LATTICE; set CONFIG_SYN_LATTICE 0 - global CONFIG_SYN_ECLIPSE; set CONFIG_SYN_ECLIPSE 0 - global CONFIG_SYN_PEREGRINE; set CONFIG_SYN_PEREGRINE 0 - global CONFIG_SYN_RH_LIB18T; set CONFIG_SYN_RH_LIB18T 0 - global CONFIG_SYN_RHUMC; set CONFIG_SYN_RHUMC 0 - global CONFIG_SYN_SMIC13; set CONFIG_SYN_SMIC13 0 - global CONFIG_SYN_SPARTAN2; set CONFIG_SYN_SPARTAN2 0 - global CONFIG_SYN_SPARTAN3; set CONFIG_SYN_SPARTAN3 0 - global CONFIG_SYN_SPARTAN3E; set CONFIG_SYN_SPARTAN3E 0 - global CONFIG_SYN_VIRTEX; set CONFIG_SYN_VIRTEX 0 - global CONFIG_SYN_VIRTEXE; set CONFIG_SYN_VIRTEXE 0 - global CONFIG_SYN_VIRTEX2; set CONFIG_SYN_VIRTEX2 0 - global CONFIG_SYN_VIRTEX4; set CONFIG_SYN_VIRTEX4 0 - global CONFIG_SYN_VIRTEX5; set CONFIG_SYN_VIRTEX5 0 - global CONFIG_SYN_UMC; set CONFIG_SYN_UMC 0 - global CONFIG_SYN_TSMC90; set CONFIG_SYN_TSMC90 0 - global CONFIG_MEM_INFERRED; set CONFIG_MEM_INFERRED 0 - global CONFIG_MEM_UMC; set CONFIG_MEM_UMC 0 - global CONFIG_MEM_RHUMC; set CONFIG_MEM_RHUMC 0 - global CONFIG_MEM_ARTISAN; set CONFIG_MEM_ARTISAN 0 - global CONFIG_MEM_CUSTOM1; set CONFIG_MEM_CUSTOM1 0 - global CONFIG_MEM_VIRAGE; set CONFIG_MEM_VIRAGE 0 - global CONFIG_MEM_VIRAGE90; set CONFIG_MEM_VIRAGE90 0 - global CONFIG_CLK_INFERRED; set CONFIG_CLK_INFERRED 0 - global CONFIG_CLK_HCLKBUF; set CONFIG_CLK_HCLKBUF 0 - global CONFIG_CLK_ALTDLL; set CONFIG_CLK_ALTDLL 0 - global CONFIG_CLK_LATDLL; set CONFIG_CLK_LATDLL 0 - global CONFIG_CLK_PRO3PLL; set CONFIG_CLK_PRO3PLL 0 - global CONFIG_CLK_LIB18T; set CONFIG_CLK_LIB18T 0 - global CONFIG_CLK_RHUMC; set CONFIG_CLK_RHUMC 0 - global CONFIG_CLK_CLKDLL; set CONFIG_CLK_CLKDLL 0 - global CONFIG_CLK_DCM; set CONFIG_CLK_DCM 0 - global CONFIG_IU_MUL_LATENCY_2; set CONFIG_IU_MUL_LATENCY_2 0 - global CONFIG_IU_MUL_LATENCY_4; set CONFIG_IU_MUL_LATENCY_4 0 - global CONFIG_IU_MUL_LATENCY_5; set CONFIG_IU_MUL_LATENCY_5 0 - global CONFIG_FPU_GRFPU; set CONFIG_FPU_GRFPU 0 - global CONFIG_FPU_GRFPULITE; set CONFIG_FPU_GRFPULITE 0 - global CONFIG_FPU_MEIKO; set CONFIG_FPU_MEIKO 0 - global CONFIG_FPU_GRFPU_INFMUL; set CONFIG_FPU_GRFPU_INFMUL 0 - global CONFIG_FPU_GRFPU_DWMUL; set CONFIG_FPU_GRFPU_DWMUL 0 - global CONFIG_FPU_GRFPU_MODGEN; set CONFIG_FPU_GRFPU_MODGEN 0 - global CONFIG_FPU_GRFPC0; set CONFIG_FPU_GRFPC0 0 - global CONFIG_FPU_GRFPC1; set CONFIG_FPU_GRFPC1 0 - global CONFIG_FPU_GRFPC2; set CONFIG_FPU_GRFPC2 0 - global CONFIG_ICACHE_ASSO1; set CONFIG_ICACHE_ASSO1 0 - global CONFIG_ICACHE_ASSO2; set CONFIG_ICACHE_ASSO2 0 - global CONFIG_ICACHE_ASSO3; set CONFIG_ICACHE_ASSO3 0 - global CONFIG_ICACHE_ASSO4; set CONFIG_ICACHE_ASSO4 0 - global CONFIG_ICACHE_SZ1; set CONFIG_ICACHE_SZ1 0 - global CONFIG_ICACHE_SZ2; set CONFIG_ICACHE_SZ2 0 - global CONFIG_ICACHE_SZ4; set CONFIG_ICACHE_SZ4 0 - global CONFIG_ICACHE_SZ8; set CONFIG_ICACHE_SZ8 0 - global CONFIG_ICACHE_SZ16; set CONFIG_ICACHE_SZ16 0 - global CONFIG_ICACHE_SZ32; set CONFIG_ICACHE_SZ32 0 - global CONFIG_ICACHE_SZ64; set CONFIG_ICACHE_SZ64 0 - global CONFIG_ICACHE_SZ128; set CONFIG_ICACHE_SZ128 0 - global CONFIG_ICACHE_SZ256; set CONFIG_ICACHE_SZ256 0 - global CONFIG_ICACHE_LZ16; set CONFIG_ICACHE_LZ16 0 - global CONFIG_ICACHE_LZ32; set CONFIG_ICACHE_LZ32 0 - global CONFIG_ICACHE_ALGORND; set CONFIG_ICACHE_ALGORND 0 - global CONFIG_ICACHE_ALGOLRR; set CONFIG_ICACHE_ALGOLRR 0 - global CONFIG_ICACHE_ALGOLRU; set CONFIG_ICACHE_ALGOLRU 0 - global CONFIG_ICACHE_LRAM_SZ1; set CONFIG_ICACHE_LRAM_SZ1 0 - global CONFIG_ICACHE_LRAM_SZ2; set CONFIG_ICACHE_LRAM_SZ2 0 - global CONFIG_ICACHE_LRAM_SZ4; set CONFIG_ICACHE_LRAM_SZ4 0 - global CONFIG_ICACHE_LRAM_SZ8; set CONFIG_ICACHE_LRAM_SZ8 0 - global CONFIG_ICACHE_LRAM_SZ16; set CONFIG_ICACHE_LRAM_SZ16 0 - global CONFIG_ICACHE_LRAM_SZ32; set CONFIG_ICACHE_LRAM_SZ32 0 - global CONFIG_ICACHE_LRAM_SZ64; set CONFIG_ICACHE_LRAM_SZ64 0 - global CONFIG_ICACHE_LRAM_SZ128; set CONFIG_ICACHE_LRAM_SZ128 0 - global CONFIG_ICACHE_LRAM_SZ256; set CONFIG_ICACHE_LRAM_SZ256 0 - global CONFIG_DCACHE_ASSO1; set CONFIG_DCACHE_ASSO1 0 - global CONFIG_DCACHE_ASSO2; set CONFIG_DCACHE_ASSO2 0 - global CONFIG_DCACHE_ASSO3; set CONFIG_DCACHE_ASSO3 0 - global CONFIG_DCACHE_ASSO4; set CONFIG_DCACHE_ASSO4 0 - global CONFIG_DCACHE_SZ1; set CONFIG_DCACHE_SZ1 0 - global CONFIG_DCACHE_SZ2; set CONFIG_DCACHE_SZ2 0 - global CONFIG_DCACHE_SZ4; set CONFIG_DCACHE_SZ4 0 - global CONFIG_DCACHE_SZ8; set CONFIG_DCACHE_SZ8 0 - global CONFIG_DCACHE_SZ16; set CONFIG_DCACHE_SZ16 0 - global CONFIG_DCACHE_SZ32; set CONFIG_DCACHE_SZ32 0 - global CONFIG_DCACHE_SZ64; set CONFIG_DCACHE_SZ64 0 - global CONFIG_DCACHE_SZ128; set CONFIG_DCACHE_SZ128 0 - global CONFIG_DCACHE_SZ256; set CONFIG_DCACHE_SZ256 0 - global CONFIG_DCACHE_LZ16; set CONFIG_DCACHE_LZ16 0 - global CONFIG_DCACHE_LZ32; set CONFIG_DCACHE_LZ32 0 - global CONFIG_DCACHE_ALGORND; set CONFIG_DCACHE_ALGORND 0 - global CONFIG_DCACHE_ALGOLRR; set CONFIG_DCACHE_ALGOLRR 0 - global CONFIG_DCACHE_ALGOLRU; set CONFIG_DCACHE_ALGOLRU 0 - global CONFIG_DCACHE_LRAM_SZ1; set CONFIG_DCACHE_LRAM_SZ1 0 - global CONFIG_DCACHE_LRAM_SZ2; set CONFIG_DCACHE_LRAM_SZ2 0 - global CONFIG_DCACHE_LRAM_SZ4; set CONFIG_DCACHE_LRAM_SZ4 0 - global CONFIG_DCACHE_LRAM_SZ8; set CONFIG_DCACHE_LRAM_SZ8 0 - global CONFIG_DCACHE_LRAM_SZ16; set CONFIG_DCACHE_LRAM_SZ16 0 - global CONFIG_DCACHE_LRAM_SZ32; set CONFIG_DCACHE_LRAM_SZ32 0 - global CONFIG_DCACHE_LRAM_SZ64; set CONFIG_DCACHE_LRAM_SZ64 0 - global CONFIG_DCACHE_LRAM_SZ128; set CONFIG_DCACHE_LRAM_SZ128 0 - global CONFIG_DCACHE_LRAM_SZ256; set CONFIG_DCACHE_LRAM_SZ256 0 - global CONFIG_MMU_COMBINED; set CONFIG_MMU_COMBINED 0 - global CONFIG_MMU_SPLIT; set CONFIG_MMU_SPLIT 0 - global CONFIG_MMU_REPARRAY; set CONFIG_MMU_REPARRAY 0 - global CONFIG_MMU_REPINCREMENT; set CONFIG_MMU_REPINCREMENT 0 - global CONFIG_MMU_I2; set CONFIG_MMU_I2 0 - global CONFIG_MMU_I4; set CONFIG_MMU_I4 0 - global CONFIG_MMU_I8; set CONFIG_MMU_I8 0 - global CONFIG_MMU_I16; set CONFIG_MMU_I16 0 - global CONFIG_MMU_I32; set CONFIG_MMU_I32 0 - global CONFIG_MMU_D2; set CONFIG_MMU_D2 0 - global CONFIG_MMU_D4; set CONFIG_MMU_D4 0 - global CONFIG_MMU_D8; set CONFIG_MMU_D8 0 - global CONFIG_MMU_D16; set CONFIG_MMU_D16 0 - global CONFIG_MMU_D32; set CONFIG_MMU_D32 0 - global CONFIG_MMU_PAGE_4K; set CONFIG_MMU_PAGE_4K 0 - global CONFIG_MMU_PAGE_8K; set CONFIG_MMU_PAGE_8K 0 - global CONFIG_MMU_PAGE_16K; set CONFIG_MMU_PAGE_16K 0 - global CONFIG_MMU_PAGE_32K; set CONFIG_MMU_PAGE_32K 0 - global CONFIG_MMU_PAGE_PROG; set CONFIG_MMU_PAGE_PROG 0 - global CONFIG_DSU_ITRACESZ1; set CONFIG_DSU_ITRACESZ1 0 - global CONFIG_DSU_ITRACESZ2; set CONFIG_DSU_ITRACESZ2 0 - global CONFIG_DSU_ITRACESZ4; set CONFIG_DSU_ITRACESZ4 0 - global CONFIG_DSU_ITRACESZ8; set CONFIG_DSU_ITRACESZ8 0 - global CONFIG_DSU_ITRACESZ16; set CONFIG_DSU_ITRACESZ16 0 - global CONFIG_DSU_ATRACESZ1; set CONFIG_DSU_ATRACESZ1 0 - global CONFIG_DSU_ATRACESZ2; set CONFIG_DSU_ATRACESZ2 0 - global CONFIG_DSU_ATRACESZ4; set CONFIG_DSU_ATRACESZ4 0 - global CONFIG_DSU_ATRACESZ8; set CONFIG_DSU_ATRACESZ8 0 - global CONFIG_DSU_ATRACESZ16; set CONFIG_DSU_ATRACESZ16 0 - global CONFIG_DSU_ETHSZ1; set CONFIG_DSU_ETHSZ1 0 - global CONFIG_DSU_ETHSZ2; set CONFIG_DSU_ETHSZ2 0 - global CONFIG_DSU_ETHSZ4; set CONFIG_DSU_ETHSZ4 0 - global CONFIG_DSU_ETHSZ8; set CONFIG_DSU_ETHSZ8 0 - global CONFIG_DSU_ETHSZ16; set CONFIG_DSU_ETHSZ16 0 - global CONFIG_SRCTRL_SRBANKS1; set CONFIG_SRCTRL_SRBANKS1 0 - global CONFIG_SRCTRL_SRBANKS2; set CONFIG_SRCTRL_SRBANKS2 0 - global CONFIG_SRCTRL_SRBANKS3; set CONFIG_SRCTRL_SRBANKS3 0 - global CONFIG_SRCTRL_SRBANKS4; set CONFIG_SRCTRL_SRBANKS4 0 - global CONFIG_SRCTRL_SRBANKS5; set CONFIG_SRCTRL_SRBANKS5 0 - global CONFIG_SRCTRL_BANKSZ0; set CONFIG_SRCTRL_BANKSZ0 0 - global CONFIG_SRCTRL_BANKSZ1; set CONFIG_SRCTRL_BANKSZ1 0 - global CONFIG_SRCTRL_BANKSZ2; set CONFIG_SRCTRL_BANKSZ2 0 - global CONFIG_SRCTRL_BANKSZ3; set CONFIG_SRCTRL_BANKSZ3 0 - global CONFIG_SRCTRL_BANKSZ4; set CONFIG_SRCTRL_BANKSZ4 0 - global CONFIG_SRCTRL_BANKSZ5; set CONFIG_SRCTRL_BANKSZ5 0 - global CONFIG_SRCTRL_BANKSZ6; set CONFIG_SRCTRL_BANKSZ6 0 - global CONFIG_SRCTRL_BANKSZ7; set CONFIG_SRCTRL_BANKSZ7 0 - global CONFIG_SRCTRL_BANKSZ8; set CONFIG_SRCTRL_BANKSZ8 0 - global CONFIG_SRCTRL_BANKSZ9; set CONFIG_SRCTRL_BANKSZ9 0 - global CONFIG_SRCTRL_BANKSZ10; set CONFIG_SRCTRL_BANKSZ10 0 - global CONFIG_SRCTRL_BANKSZ11; set CONFIG_SRCTRL_BANKSZ11 0 - global CONFIG_SRCTRL_BANKSZ12; set CONFIG_SRCTRL_BANKSZ12 0 - global CONFIG_SRCTRL_BANKSZ13; set CONFIG_SRCTRL_BANKSZ13 0 - global CONFIG_AHBRAM_SZ1; set CONFIG_AHBRAM_SZ1 0 - global CONFIG_AHBRAM_SZ2; set CONFIG_AHBRAM_SZ2 0 - global CONFIG_AHBRAM_SZ4; set CONFIG_AHBRAM_SZ4 0 - global CONFIG_AHBRAM_SZ8; set CONFIG_AHBRAM_SZ8 0 - global CONFIG_AHBRAM_SZ16; set CONFIG_AHBRAM_SZ16 0 - global CONFIG_AHBRAM_SZ32; set CONFIG_AHBRAM_SZ32 0 - global CONFIG_AHBRAM_SZ64; set CONFIG_AHBRAM_SZ64 0 - global CONFIG_GRETH_FIFO4; set CONFIG_GRETH_FIFO4 0 - global CONFIG_GRETH_FIFO8; set CONFIG_GRETH_FIFO8 0 - global CONFIG_GRETH_FIFO16; set CONFIG_GRETH_FIFO16 0 - global CONFIG_GRETH_FIFO32; set CONFIG_GRETH_FIFO32 0 - global CONFIG_GRETH_FIFO64; set CONFIG_GRETH_FIFO64 0 - global CONFIG_PCI_FIFO0; set CONFIG_PCI_FIFO0 0 - global CONFIG_PCI_FIFO8; set CONFIG_PCI_FIFO8 0 - global CONFIG_PCI_FIFO16; set CONFIG_PCI_FIFO16 0 - global CONFIG_PCI_FIFO32; set CONFIG_PCI_FIFO32 0 - global CONFIG_PCI_FIFO64; set CONFIG_PCI_FIFO64 0 - global CONFIG_PCI_FIFO128; set CONFIG_PCI_FIFO128 0 - global CONFIG_PCI_TRACE256; set CONFIG_PCI_TRACE256 0 - global CONFIG_PCI_TRACE512; set CONFIG_PCI_TRACE512 0 - global CONFIG_PCI_TRACE1024; set CONFIG_PCI_TRACE1024 0 - global CONFIG_PCI_TRACE2048; set CONFIG_PCI_TRACE2048 0 - global CONFIG_PCI_TRACE4096; set CONFIG_PCI_TRACE4096 0 - global CONFIG_SPW_AHBFIFO4; set CONFIG_SPW_AHBFIFO4 0 - global CONFIG_SPW_AHBFIFO8; set CONFIG_SPW_AHBFIFO8 0 - global CONFIG_SPW_AHBFIFO16; set CONFIG_SPW_AHBFIFO16 0 - global CONFIG_SPW_AHBFIFO32; set CONFIG_SPW_AHBFIFO32 0 - global CONFIG_SPW_RXFIFO16; set CONFIG_SPW_RXFIFO16 0 - global CONFIG_SPW_RXFIFO32; set CONFIG_SPW_RXFIFO32 0 - global CONFIG_SPW_RXFIFO64; set CONFIG_SPW_RXFIFO64 0 - global CONFIG_SPW_RMAPBUF2; set CONFIG_SPW_RMAPBUF2 0 - global CONFIG_SPW_RMAPBUF4; set CONFIG_SPW_RMAPBUF4 0 - global CONFIG_SPW_RMAPBUF6; set CONFIG_SPW_RMAPBUF6 0 - global CONFIG_SPW_RMAPBUF8; set CONFIG_SPW_RMAPBUF8 0 - global CONFIG_SPW_GRSPW1; set CONFIG_SPW_GRSPW1 0 - global CONFIG_SPW_GRSPW2; set CONFIG_SPW_GRSPW2 0 - global CONFIG_SPW_RX_SDR; set CONFIG_SPW_RX_SDR 0 - global CONFIG_SPW_RX_DDR; set CONFIG_SPW_RX_DDR 0 - global CONFIG_SPW_RX_XOR; set CONFIG_SPW_RX_XOR 0 - global CONFIG_SPW_RX_AFLEX; set CONFIG_SPW_RX_AFLEX 0 - global CONFIG_SPW_TX_SDR; set CONFIG_SPW_TX_SDR 0 - global CONFIG_SPW_TX_DDR; set CONFIG_SPW_TX_DDR 0 - global CONFIG_SPW_TX_AFLEX; set CONFIG_SPW_TX_AFLEX 0 - global CONFIG_UA1_FIFO1; set CONFIG_UA1_FIFO1 0 - global CONFIG_UA1_FIFO2; set CONFIG_UA1_FIFO2 0 - global CONFIG_UA1_FIFO4; set CONFIG_UA1_FIFO4 0 - global CONFIG_UA1_FIFO8; set CONFIG_UA1_FIFO8 0 - global CONFIG_UA1_FIFO16; set CONFIG_UA1_FIFO16 0 - global CONFIG_UA1_FIFO32; set CONFIG_UA1_FIFO32 0 - global CONFIG_UA2_FIFO1; set CONFIG_UA2_FIFO1 0 - global CONFIG_UA2_FIFO2; set CONFIG_UA2_FIFO2 0 - global CONFIG_UA2_FIFO4; set CONFIG_UA2_FIFO4 0 - global CONFIG_UA2_FIFO8; set CONFIG_UA2_FIFO8 0 - global CONFIG_UA2_FIFO16; set CONFIG_UA2_FIFO16 0 - global CONFIG_UA2_FIFO32; set CONFIG_UA2_FIFO32 0 -} - - -proc update_choices { } { - global tmpvar_0 - set tmpvar_0 "Inferred" - global CONFIG_SYN_INFERRED - if { $CONFIG_SYN_INFERRED == 1 } then { set tmpvar_0 "Inferred" } - global CONFIG_SYN_STRATIX - if { $CONFIG_SYN_STRATIX == 1 } then { set tmpvar_0 "Altera-Stratix" } - global CONFIG_SYN_STRATIXII - if { $CONFIG_SYN_STRATIXII == 1 } then { set tmpvar_0 "Altera-StratixII" } - global CONFIG_SYN_STRATIXIII - if { $CONFIG_SYN_STRATIXIII == 1 } then { set tmpvar_0 "Altera-StratixIII" } - global CONFIG_SYN_CYCLONEIII - if { $CONFIG_SYN_CYCLONEIII == 1 } then { set tmpvar_0 "Altera-CycloneIII" } - global CONFIG_SYN_ALTERA - if { $CONFIG_SYN_ALTERA == 1 } then { set tmpvar_0 "Altera-Others" } - global CONFIG_SYN_AXCEL - if { $CONFIG_SYN_AXCEL == 1 } then { set tmpvar_0 "Actel-Axcelerator" } - global CONFIG_SYN_PROASIC - if { $CONFIG_SYN_PROASIC == 1 } then { set tmpvar_0 "Actel-Proasic" } - global CONFIG_SYN_PROASICPLUS - if { $CONFIG_SYN_PROASICPLUS == 1 } then { set tmpvar_0 "Actel-ProasicPlus" } - global CONFIG_SYN_PROASIC3 - if { $CONFIG_SYN_PROASIC3 == 1 } then { set tmpvar_0 "Actel-Proasic3" } - global CONFIG_SYN_UT025CRH - if { $CONFIG_SYN_UT025CRH == 1 } then { set tmpvar_0 "Aeroflex-UT025CRH" } - global CONFIG_SYN_ATC18 - if { $CONFIG_SYN_ATC18 == 1 } then { set tmpvar_0 "Atmel-ATC18" } - global CONFIG_SYN_ATC18RHA - if { $CONFIG_SYN_ATC18RHA == 1 } then { set tmpvar_0 "Atmel-ATC18RHA" } - global CONFIG_SYN_CUSTOM1 - if { $CONFIG_SYN_CUSTOM1 == 1 } then { set tmpvar_0 "Custom1" } - global CONFIG_SYN_EASIC90 - if { $CONFIG_SYN_EASIC90 == 1 } then { set tmpvar_0 "eASIC90" } - global CONFIG_SYN_IHP25 - if { $CONFIG_SYN_IHP25 == 1 } then { set tmpvar_0 "IHP25" } - global CONFIG_SYN_IHP25RH - if { $CONFIG_SYN_IHP25RH == 1 } then { set tmpvar_0 "IHP25RH" } - global CONFIG_SYN_LATTICE - if { $CONFIG_SYN_LATTICE == 1 } then { set tmpvar_0 "Lattice-EC/ECP/XP" } - global CONFIG_SYN_ECLIPSE - if { $CONFIG_SYN_ECLIPSE == 1 } then { set tmpvar_0 "Quicklogic-Eclipse" } - global CONFIG_SYN_PEREGRINE - if { $CONFIG_SYN_PEREGRINE == 1 } then { set tmpvar_0 "Peregrine" } - global CONFIG_SYN_RH_LIB18T - if { $CONFIG_SYN_RH_LIB18T == 1 } then { set tmpvar_0 "RH-LIB18T" } - global CONFIG_SYN_RHUMC - if { $CONFIG_SYN_RHUMC == 1 } then { set tmpvar_0 "RH-UMC" } - global CONFIG_SYN_SMIC13 - if { $CONFIG_SYN_SMIC13 == 1 } then { set tmpvar_0 "SMIC130" } - global CONFIG_SYN_SPARTAN2 - if { $CONFIG_SYN_SPARTAN2 == 1 } then { set tmpvar_0 "Xilinx-Spartan2" } - global CONFIG_SYN_SPARTAN3 - if { $CONFIG_SYN_SPARTAN3 == 1 } then { set tmpvar_0 "Xilinx-Spartan3" } - global CONFIG_SYN_SPARTAN3E - if { $CONFIG_SYN_SPARTAN3E == 1 } then { set tmpvar_0 "Xilinx-Spartan3E" } - global CONFIG_SYN_VIRTEX - if { $CONFIG_SYN_VIRTEX == 1 } then { set tmpvar_0 "Xilinx-Virtex" } - global CONFIG_SYN_VIRTEXE - if { $CONFIG_SYN_VIRTEXE == 1 } then { set tmpvar_0 "Xilinx-VirtexE" } - global CONFIG_SYN_VIRTEX2 - if { $CONFIG_SYN_VIRTEX2 == 1 } then { set tmpvar_0 "Xilinx-Virtex2" } - global CONFIG_SYN_VIRTEX4 - if { $CONFIG_SYN_VIRTEX4 == 1 } then { set tmpvar_0 "Xilinx-Virtex4" } - global CONFIG_SYN_VIRTEX5 - if { $CONFIG_SYN_VIRTEX5 == 1 } then { set tmpvar_0 "Xilinx-Virtex5" } - global CONFIG_SYN_UMC - if { $CONFIG_SYN_UMC == 1 } then { set tmpvar_0 "UMC180" } - global CONFIG_SYN_TSMC90 - if { $CONFIG_SYN_TSMC90 == 1 } then { set tmpvar_0 "TSMC90" } - global tmpvar_1 - set tmpvar_1 "Inferred" - global CONFIG_MEM_INFERRED - if { $CONFIG_MEM_INFERRED == 1 } then { set tmpvar_1 "Inferred" } - global CONFIG_MEM_UMC - if { $CONFIG_MEM_UMC == 1 } then { set tmpvar_1 "UMC18" } - global CONFIG_MEM_RHUMC - if { $CONFIG_MEM_RHUMC == 1 } then { set tmpvar_1 "RH-UMC" } - global CONFIG_MEM_ARTISAN - if { $CONFIG_MEM_ARTISAN == 1 } then { set tmpvar_1 "Artisan" } - global CONFIG_MEM_CUSTOM1 - if { $CONFIG_MEM_CUSTOM1 == 1 } then { set tmpvar_1 "Custom1" } - global CONFIG_MEM_VIRAGE - if { $CONFIG_MEM_VIRAGE == 1 } then { set tmpvar_1 "Virage" } - global CONFIG_MEM_VIRAGE90 - if { $CONFIG_MEM_VIRAGE90 == 1 } then { set tmpvar_1 "Virage-TSMC90" } - global tmpvar_2 - set tmpvar_2 "Inferred" - global CONFIG_CLK_INFERRED - if { $CONFIG_CLK_INFERRED == 1 } then { set tmpvar_2 "Inferred" } - global CONFIG_CLK_HCLKBUF - if { $CONFIG_CLK_HCLKBUF == 1 } then { set tmpvar_2 "Actel-HCLKBUF" } - global CONFIG_CLK_ALTDLL - if { $CONFIG_CLK_ALTDLL == 1 } then { set tmpvar_2 "Altera-ALTPLL" } - global CONFIG_CLK_LATDLL - if { $CONFIG_CLK_LATDLL == 1 } then { set tmpvar_2 "Lattice-EXPLL" } - global CONFIG_CLK_PRO3PLL - if { $CONFIG_CLK_PRO3PLL == 1 } then { set tmpvar_2 "Proasic3-PLLL" } - global CONFIG_CLK_LIB18T - if { $CONFIG_CLK_LIB18T == 1 } then { set tmpvar_2 "RH-LIB18T-PLL" } - global CONFIG_CLK_RHUMC - if { $CONFIG_CLK_RHUMC == 1 } then { set tmpvar_2 "DARE-PLL" } - global CONFIG_CLK_CLKDLL - if { $CONFIG_CLK_CLKDLL == 1 } then { set tmpvar_2 "Xilinx-CLKDLL" } - global CONFIG_CLK_DCM - if { $CONFIG_CLK_DCM == 1 } then { set tmpvar_2 "Xilinx-DCM" } - global tmpvar_3 - set tmpvar_3 "5-cycles" - global CONFIG_IU_MUL_LATENCY_2 - if { $CONFIG_IU_MUL_LATENCY_2 == 1 } then { set tmpvar_3 "2-cycles" } - global CONFIG_IU_MUL_LATENCY_4 - if { $CONFIG_IU_MUL_LATENCY_4 == 1 } then { set tmpvar_3 "4-cycles" } - global CONFIG_IU_MUL_LATENCY_5 - if { $CONFIG_IU_MUL_LATENCY_5 == 1 } then { set tmpvar_3 "5-cycles" } - global tmpvar_4 - set tmpvar_4 "GRFPU" - global CONFIG_FPU_GRFPU - if { $CONFIG_FPU_GRFPU == 1 } then { set tmpvar_4 "GRFPU" } - global CONFIG_FPU_GRFPULITE - if { $CONFIG_FPU_GRFPULITE == 1 } then { set tmpvar_4 "GRFPU-LITE" } - global CONFIG_FPU_MEIKO - if { $CONFIG_FPU_MEIKO == 1 } then { set tmpvar_4 "Meiko" } - global tmpvar_5 - set tmpvar_5 "Inferred" - global CONFIG_FPU_GRFPU_INFMUL - if { $CONFIG_FPU_GRFPU_INFMUL == 1 } then { set tmpvar_5 "Inferred" } - global CONFIG_FPU_GRFPU_DWMUL - if { $CONFIG_FPU_GRFPU_DWMUL == 1 } then { set tmpvar_5 "DW" } - global CONFIG_FPU_GRFPU_MODGEN - if { $CONFIG_FPU_GRFPU_MODGEN == 1 } then { set tmpvar_5 "ModGen" } - global tmpvar_6 - set tmpvar_6 "Simple" - global CONFIG_FPU_GRFPC0 - if { $CONFIG_FPU_GRFPC0 == 1 } then { set tmpvar_6 "Simple" } - global CONFIG_FPU_GRFPC1 - if { $CONFIG_FPU_GRFPC1 == 1 } then { set tmpvar_6 "Data-forwarding" } - global CONFIG_FPU_GRFPC2 - if { $CONFIG_FPU_GRFPC2 == 1 } then { set tmpvar_6 "Non-blocking" } - global tmpvar_7 - set tmpvar_7 "1" - global CONFIG_ICACHE_ASSO1 - if { $CONFIG_ICACHE_ASSO1 == 1 } then { set tmpvar_7 "1" } - global CONFIG_ICACHE_ASSO2 - if { $CONFIG_ICACHE_ASSO2 == 1 } then { set tmpvar_7 "2" } - global CONFIG_ICACHE_ASSO3 - if { $CONFIG_ICACHE_ASSO3 == 1 } then { set tmpvar_7 "3" } - global CONFIG_ICACHE_ASSO4 - if { $CONFIG_ICACHE_ASSO4 == 1 } then { set tmpvar_7 "4" } - global tmpvar_8 - set tmpvar_8 "4" - global CONFIG_ICACHE_SZ1 - if { $CONFIG_ICACHE_SZ1 == 1 } then { set tmpvar_8 "1" } - global CONFIG_ICACHE_SZ2 - if { $CONFIG_ICACHE_SZ2 == 1 } then { set tmpvar_8 "2" } - global CONFIG_ICACHE_SZ4 - if { $CONFIG_ICACHE_SZ4 == 1 } then { set tmpvar_8 "4" } - global CONFIG_ICACHE_SZ8 - if { $CONFIG_ICACHE_SZ8 == 1 } then { set tmpvar_8 "8" } - global CONFIG_ICACHE_SZ16 - if { $CONFIG_ICACHE_SZ16 == 1 } then { set tmpvar_8 "16" } - global CONFIG_ICACHE_SZ32 - if { $CONFIG_ICACHE_SZ32 == 1 } then { set tmpvar_8 "32" } - global CONFIG_ICACHE_SZ64 - if { $CONFIG_ICACHE_SZ64 == 1 } then { set tmpvar_8 "64" } - global CONFIG_ICACHE_SZ128 - if { $CONFIG_ICACHE_SZ128 == 1 } then { set tmpvar_8 "128" } - global CONFIG_ICACHE_SZ256 - if { $CONFIG_ICACHE_SZ256 == 1 } then { set tmpvar_8 "256" } - global tmpvar_9 - set tmpvar_9 "32" - global CONFIG_ICACHE_LZ16 - if { $CONFIG_ICACHE_LZ16 == 1 } then { set tmpvar_9 "16" } - global CONFIG_ICACHE_LZ32 - if { $CONFIG_ICACHE_LZ32 == 1 } then { set tmpvar_9 "32" } - global tmpvar_10 - set tmpvar_10 "Random" - global CONFIG_ICACHE_ALGORND - if { $CONFIG_ICACHE_ALGORND == 1 } then { set tmpvar_10 "Random" } - global CONFIG_ICACHE_ALGOLRR - if { $CONFIG_ICACHE_ALGOLRR == 1 } then { set tmpvar_10 "LRR" } - global CONFIG_ICACHE_ALGOLRU - if { $CONFIG_ICACHE_ALGOLRU == 1 } then { set tmpvar_10 "LRU" } - global tmpvar_11 - set tmpvar_11 "4" - global CONFIG_ICACHE_LRAM_SZ1 - if { $CONFIG_ICACHE_LRAM_SZ1 == 1 } then { set tmpvar_11 "1" } - global CONFIG_ICACHE_LRAM_SZ2 - if { $CONFIG_ICACHE_LRAM_SZ2 == 1 } then { set tmpvar_11 "2" } - global CONFIG_ICACHE_LRAM_SZ4 - if { $CONFIG_ICACHE_LRAM_SZ4 == 1 } then { set tmpvar_11 "4" } - global CONFIG_ICACHE_LRAM_SZ8 - if { $CONFIG_ICACHE_LRAM_SZ8 == 1 } then { set tmpvar_11 "8" } - global CONFIG_ICACHE_LRAM_SZ16 - if { $CONFIG_ICACHE_LRAM_SZ16 == 1 } then { set tmpvar_11 "16" } - global CONFIG_ICACHE_LRAM_SZ32 - if { $CONFIG_ICACHE_LRAM_SZ32 == 1 } then { set tmpvar_11 "32" } - global CONFIG_ICACHE_LRAM_SZ64 - if { $CONFIG_ICACHE_LRAM_SZ64 == 1 } then { set tmpvar_11 "64" } - global CONFIG_ICACHE_LRAM_SZ128 - if { $CONFIG_ICACHE_LRAM_SZ128 == 1 } then { set tmpvar_11 "128" } - global CONFIG_ICACHE_LRAM_SZ256 - if { $CONFIG_ICACHE_LRAM_SZ256 == 1 } then { set tmpvar_11 "256" } - global tmpvar_12 - set tmpvar_12 "1" - global CONFIG_DCACHE_ASSO1 - if { $CONFIG_DCACHE_ASSO1 == 1 } then { set tmpvar_12 "1" } - global CONFIG_DCACHE_ASSO2 - if { $CONFIG_DCACHE_ASSO2 == 1 } then { set tmpvar_12 "2" } - global CONFIG_DCACHE_ASSO3 - if { $CONFIG_DCACHE_ASSO3 == 1 } then { set tmpvar_12 "3" } - global CONFIG_DCACHE_ASSO4 - if { $CONFIG_DCACHE_ASSO4 == 1 } then { set tmpvar_12 "4" } - global tmpvar_13 - set tmpvar_13 "4" - global CONFIG_DCACHE_SZ1 - if { $CONFIG_DCACHE_SZ1 == 1 } then { set tmpvar_13 "1" } - global CONFIG_DCACHE_SZ2 - if { $CONFIG_DCACHE_SZ2 == 1 } then { set tmpvar_13 "2" } - global CONFIG_DCACHE_SZ4 - if { $CONFIG_DCACHE_SZ4 == 1 } then { set tmpvar_13 "4" } - global CONFIG_DCACHE_SZ8 - if { $CONFIG_DCACHE_SZ8 == 1 } then { set tmpvar_13 "8" } - global CONFIG_DCACHE_SZ16 - if { $CONFIG_DCACHE_SZ16 == 1 } then { set tmpvar_13 "16" } - global CONFIG_DCACHE_SZ32 - if { $CONFIG_DCACHE_SZ32 == 1 } then { set tmpvar_13 "32" } - global CONFIG_DCACHE_SZ64 - if { $CONFIG_DCACHE_SZ64 == 1 } then { set tmpvar_13 "64" } - global CONFIG_DCACHE_SZ128 - if { $CONFIG_DCACHE_SZ128 == 1 } then { set tmpvar_13 "128" } - global CONFIG_DCACHE_SZ256 - if { $CONFIG_DCACHE_SZ256 == 1 } then { set tmpvar_13 "256" } - global tmpvar_14 - set tmpvar_14 "32" - global CONFIG_DCACHE_LZ16 - if { $CONFIG_DCACHE_LZ16 == 1 } then { set tmpvar_14 "16" } - global CONFIG_DCACHE_LZ32 - if { $CONFIG_DCACHE_LZ32 == 1 } then { set tmpvar_14 "32" } - global tmpvar_15 - set tmpvar_15 "Random" - global CONFIG_DCACHE_ALGORND - if { $CONFIG_DCACHE_ALGORND == 1 } then { set tmpvar_15 "Random" } - global CONFIG_DCACHE_ALGOLRR - if { $CONFIG_DCACHE_ALGOLRR == 1 } then { set tmpvar_15 "LRR" } - global CONFIG_DCACHE_ALGOLRU - if { $CONFIG_DCACHE_ALGOLRU == 1 } then { set tmpvar_15 "LRU" } - global tmpvar_16 - set tmpvar_16 "4" - global CONFIG_DCACHE_LRAM_SZ1 - if { $CONFIG_DCACHE_LRAM_SZ1 == 1 } then { set tmpvar_16 "1" } - global CONFIG_DCACHE_LRAM_SZ2 - if { $CONFIG_DCACHE_LRAM_SZ2 == 1 } then { set tmpvar_16 "2" } - global CONFIG_DCACHE_LRAM_SZ4 - if { $CONFIG_DCACHE_LRAM_SZ4 == 1 } then { set tmpvar_16 "4" } - global CONFIG_DCACHE_LRAM_SZ8 - if { $CONFIG_DCACHE_LRAM_SZ8 == 1 } then { set tmpvar_16 "8" } - global CONFIG_DCACHE_LRAM_SZ16 - if { $CONFIG_DCACHE_LRAM_SZ16 == 1 } then { set tmpvar_16 "16" } - global CONFIG_DCACHE_LRAM_SZ32 - if { $CONFIG_DCACHE_LRAM_SZ32 == 1 } then { set tmpvar_16 "32" } - global CONFIG_DCACHE_LRAM_SZ64 - if { $CONFIG_DCACHE_LRAM_SZ64 == 1 } then { set tmpvar_16 "64" } - global CONFIG_DCACHE_LRAM_SZ128 - if { $CONFIG_DCACHE_LRAM_SZ128 == 1 } then { set tmpvar_16 "128" } - global CONFIG_DCACHE_LRAM_SZ256 - if { $CONFIG_DCACHE_LRAM_SZ256 == 1 } then { set tmpvar_16 "256" } - global tmpvar_17 - set tmpvar_17 "combined" - global CONFIG_MMU_COMBINED - if { $CONFIG_MMU_COMBINED == 1 } then { set tmpvar_17 "combined" } - global CONFIG_MMU_SPLIT - if { $CONFIG_MMU_SPLIT == 1 } then { set tmpvar_17 "split" } - global tmpvar_18 - set tmpvar_18 "Increment" - global CONFIG_MMU_REPARRAY - if { $CONFIG_MMU_REPARRAY == 1 } then { set tmpvar_18 "LRU" } - global CONFIG_MMU_REPINCREMENT - if { $CONFIG_MMU_REPINCREMENT == 1 } then { set tmpvar_18 "Increment" } - global tmpvar_19 - set tmpvar_19 "8" - global CONFIG_MMU_I2 - if { $CONFIG_MMU_I2 == 1 } then { set tmpvar_19 "2" } - global CONFIG_MMU_I4 - if { $CONFIG_MMU_I4 == 1 } then { set tmpvar_19 "4" } - global CONFIG_MMU_I8 - if { $CONFIG_MMU_I8 == 1 } then { set tmpvar_19 "8" } - global CONFIG_MMU_I16 - if { $CONFIG_MMU_I16 == 1 } then { set tmpvar_19 "16" } - global CONFIG_MMU_I32 - if { $CONFIG_MMU_I32 == 1 } then { set tmpvar_19 "32" } - global tmpvar_20 - set tmpvar_20 "8" - global CONFIG_MMU_D2 - if { $CONFIG_MMU_D2 == 1 } then { set tmpvar_20 "2" } - global CONFIG_MMU_D4 - if { $CONFIG_MMU_D4 == 1 } then { set tmpvar_20 "4" } - global CONFIG_MMU_D8 - if { $CONFIG_MMU_D8 == 1 } then { set tmpvar_20 "8" } - global CONFIG_MMU_D16 - if { $CONFIG_MMU_D16 == 1 } then { set tmpvar_20 "16" } - global CONFIG_MMU_D32 - if { $CONFIG_MMU_D32 == 1 } then { set tmpvar_20 "32" } - global tmpvar_21 - set tmpvar_21 "4K" - global CONFIG_MMU_PAGE_4K - if { $CONFIG_MMU_PAGE_4K == 1 } then { set tmpvar_21 "4K" } - global CONFIG_MMU_PAGE_8K - if { $CONFIG_MMU_PAGE_8K == 1 } then { set tmpvar_21 "8K" } - global CONFIG_MMU_PAGE_16K - if { $CONFIG_MMU_PAGE_16K == 1 } then { set tmpvar_21 "16K" } - global CONFIG_MMU_PAGE_32K - if { $CONFIG_MMU_PAGE_32K == 1 } then { set tmpvar_21 "32K" } - global CONFIG_MMU_PAGE_PROG - if { $CONFIG_MMU_PAGE_PROG == 1 } then { set tmpvar_21 "Programmable" } - global tmpvar_22 - set tmpvar_22 "1" - global CONFIG_DSU_ITRACESZ1 - if { $CONFIG_DSU_ITRACESZ1 == 1 } then { set tmpvar_22 "1" } - global CONFIG_DSU_ITRACESZ2 - if { $CONFIG_DSU_ITRACESZ2 == 1 } then { set tmpvar_22 "2" } - global CONFIG_DSU_ITRACESZ4 - if { $CONFIG_DSU_ITRACESZ4 == 1 } then { set tmpvar_22 "4" } - global CONFIG_DSU_ITRACESZ8 - if { $CONFIG_DSU_ITRACESZ8 == 1 } then { set tmpvar_22 "8" } - global CONFIG_DSU_ITRACESZ16 - if { $CONFIG_DSU_ITRACESZ16 == 1 } then { set tmpvar_22 "16" } - global tmpvar_23 - set tmpvar_23 "1" - global CONFIG_DSU_ATRACESZ1 - if { $CONFIG_DSU_ATRACESZ1 == 1 } then { set tmpvar_23 "1" } - global CONFIG_DSU_ATRACESZ2 - if { $CONFIG_DSU_ATRACESZ2 == 1 } then { set tmpvar_23 "2" } - global CONFIG_DSU_ATRACESZ4 - if { $CONFIG_DSU_ATRACESZ4 == 1 } then { set tmpvar_23 "4" } - global CONFIG_DSU_ATRACESZ8 - if { $CONFIG_DSU_ATRACESZ8 == 1 } then { set tmpvar_23 "8" } - global CONFIG_DSU_ATRACESZ16 - if { $CONFIG_DSU_ATRACESZ16 == 1 } then { set tmpvar_23 "16" } - global tmpvar_25 - set tmpvar_25 "2" - global CONFIG_DSU_ETHSZ1 - if { $CONFIG_DSU_ETHSZ1 == 1 } then { set tmpvar_25 "1" } - global CONFIG_DSU_ETHSZ2 - if { $CONFIG_DSU_ETHSZ2 == 1 } then { set tmpvar_25 "2" } - global CONFIG_DSU_ETHSZ4 - if { $CONFIG_DSU_ETHSZ4 == 1 } then { set tmpvar_25 "4" } - global CONFIG_DSU_ETHSZ8 - if { $CONFIG_DSU_ETHSZ8 == 1 } then { set tmpvar_25 "8" } - global CONFIG_DSU_ETHSZ16 - if { $CONFIG_DSU_ETHSZ16 == 1 } then { set tmpvar_25 "16" } - global tmpvar_26 - set tmpvar_26 "1" - global CONFIG_SRCTRL_SRBANKS1 - if { $CONFIG_SRCTRL_SRBANKS1 == 1 } then { set tmpvar_26 "1" } - global CONFIG_SRCTRL_SRBANKS2 - if { $CONFIG_SRCTRL_SRBANKS2 == 1 } then { set tmpvar_26 "2" } - global CONFIG_SRCTRL_SRBANKS3 - if { $CONFIG_SRCTRL_SRBANKS3 == 1 } then { set tmpvar_26 "3" } - global CONFIG_SRCTRL_SRBANKS4 - if { $CONFIG_SRCTRL_SRBANKS4 == 1 } then { set tmpvar_26 "4" } - global CONFIG_SRCTRL_SRBANKS5 - if { $CONFIG_SRCTRL_SRBANKS5 == 1 } then { set tmpvar_26 "5" } - global tmpvar_27 - set tmpvar_27 "0" - global CONFIG_SRCTRL_BANKSZ0 - if { $CONFIG_SRCTRL_BANKSZ0 == 1 } then { set tmpvar_27 "8" } - global CONFIG_SRCTRL_BANKSZ1 - if { $CONFIG_SRCTRL_BANKSZ1 == 1 } then { set tmpvar_27 "16" } - global CONFIG_SRCTRL_BANKSZ2 - if { $CONFIG_SRCTRL_BANKSZ2 == 1 } then { set tmpvar_27 "32" } - global CONFIG_SRCTRL_BANKSZ3 - if { $CONFIG_SRCTRL_BANKSZ3 == 1 } then { set tmpvar_27 "64" } - global CONFIG_SRCTRL_BANKSZ4 - if { $CONFIG_SRCTRL_BANKSZ4 == 1 } then { set tmpvar_27 "128" } - global CONFIG_SRCTRL_BANKSZ5 - if { $CONFIG_SRCTRL_BANKSZ5 == 1 } then { set tmpvar_27 "256" } - global CONFIG_SRCTRL_BANKSZ6 - if { $CONFIG_SRCTRL_BANKSZ6 == 1 } then { set tmpvar_27 "512" } - global CONFIG_SRCTRL_BANKSZ7 - if { $CONFIG_SRCTRL_BANKSZ7 == 1 } then { set tmpvar_27 "1024" } - global CONFIG_SRCTRL_BANKSZ8 - if { $CONFIG_SRCTRL_BANKSZ8 == 1 } then { set tmpvar_27 "2048" } - global CONFIG_SRCTRL_BANKSZ9 - if { $CONFIG_SRCTRL_BANKSZ9 == 1 } then { set tmpvar_27 "4096" } - global CONFIG_SRCTRL_BANKSZ10 - if { $CONFIG_SRCTRL_BANKSZ10 == 1 } then { set tmpvar_27 "8192" } - global CONFIG_SRCTRL_BANKSZ11 - if { $CONFIG_SRCTRL_BANKSZ11 == 1 } then { set tmpvar_27 "16384" } - global CONFIG_SRCTRL_BANKSZ12 - if { $CONFIG_SRCTRL_BANKSZ12 == 1 } then { set tmpvar_27 "32768" } - global CONFIG_SRCTRL_BANKSZ13 - if { $CONFIG_SRCTRL_BANKSZ13 == 1 } then { set tmpvar_27 "65536" } - global tmpvar_28 - set tmpvar_28 "4" - global CONFIG_AHBRAM_SZ1 - if { $CONFIG_AHBRAM_SZ1 == 1 } then { set tmpvar_28 "1" } - global CONFIG_AHBRAM_SZ2 - if { $CONFIG_AHBRAM_SZ2 == 1 } then { set tmpvar_28 "2" } - global CONFIG_AHBRAM_SZ4 - if { $CONFIG_AHBRAM_SZ4 == 1 } then { set tmpvar_28 "4" } - global CONFIG_AHBRAM_SZ8 - if { $CONFIG_AHBRAM_SZ8 == 1 } then { set tmpvar_28 "8" } - global CONFIG_AHBRAM_SZ16 - if { $CONFIG_AHBRAM_SZ16 == 1 } then { set tmpvar_28 "16" } - global CONFIG_AHBRAM_SZ32 - if { $CONFIG_AHBRAM_SZ32 == 1 } then { set tmpvar_28 "32" } - global CONFIG_AHBRAM_SZ64 - if { $CONFIG_AHBRAM_SZ64 == 1 } then { set tmpvar_28 "64" } - global tmpvar_29 - set tmpvar_29 "8" - global CONFIG_GRETH_FIFO4 - if { $CONFIG_GRETH_FIFO4 == 1 } then { set tmpvar_29 "4" } - global CONFIG_GRETH_FIFO8 - if { $CONFIG_GRETH_FIFO8 == 1 } then { set tmpvar_29 "8" } - global CONFIG_GRETH_FIFO16 - if { $CONFIG_GRETH_FIFO16 == 1 } then { set tmpvar_29 "16" } - global CONFIG_GRETH_FIFO32 - if { $CONFIG_GRETH_FIFO32 == 1 } then { set tmpvar_29 "32" } - global CONFIG_GRETH_FIFO64 - if { $CONFIG_GRETH_FIFO64 == 1 } then { set tmpvar_29 "64" } - global tmpvar_30 - set tmpvar_30 "8" - global CONFIG_PCI_FIFO0 - if { $CONFIG_PCI_FIFO0 == 1 } then { set tmpvar_30 "None" } - global CONFIG_PCI_FIFO8 - if { $CONFIG_PCI_FIFO8 == 1 } then { set tmpvar_30 "8" } - global CONFIG_PCI_FIFO16 - if { $CONFIG_PCI_FIFO16 == 1 } then { set tmpvar_30 "16" } - global CONFIG_PCI_FIFO32 - if { $CONFIG_PCI_FIFO32 == 1 } then { set tmpvar_30 "32" } - global CONFIG_PCI_FIFO64 - if { $CONFIG_PCI_FIFO64 == 1 } then { set tmpvar_30 "64" } - global CONFIG_PCI_FIFO128 - if { $CONFIG_PCI_FIFO128 == 1 } then { set tmpvar_30 "128" } - global tmpvar_31 - set tmpvar_31 "256" - global CONFIG_PCI_TRACE256 - if { $CONFIG_PCI_TRACE256 == 1 } then { set tmpvar_31 "256" } - global CONFIG_PCI_TRACE512 - if { $CONFIG_PCI_TRACE512 == 1 } then { set tmpvar_31 "512" } - global CONFIG_PCI_TRACE1024 - if { $CONFIG_PCI_TRACE1024 == 1 } then { set tmpvar_31 "1024" } - global CONFIG_PCI_TRACE2048 - if { $CONFIG_PCI_TRACE2048 == 1 } then { set tmpvar_31 "2048" } - global CONFIG_PCI_TRACE4096 - if { $CONFIG_PCI_TRACE4096 == 1 } then { set tmpvar_31 "4096" } - global tmpvar_32 - set tmpvar_32 "16" - global CONFIG_SPW_AHBFIFO4 - if { $CONFIG_SPW_AHBFIFO4 == 1 } then { set tmpvar_32 "4" } - global CONFIG_SPW_AHBFIFO8 - if { $CONFIG_SPW_AHBFIFO8 == 1 } then { set tmpvar_32 "8" } - global CONFIG_SPW_AHBFIFO16 - if { $CONFIG_SPW_AHBFIFO16 == 1 } then { set tmpvar_32 "16" } - global CONFIG_SPW_AHBFIFO32 - if { $CONFIG_SPW_AHBFIFO32 == 1 } then { set tmpvar_32 "32" } - global tmpvar_33 - set tmpvar_33 "16" - global CONFIG_SPW_RXFIFO16 - if { $CONFIG_SPW_RXFIFO16 == 1 } then { set tmpvar_33 "16" } - global CONFIG_SPW_RXFIFO32 - if { $CONFIG_SPW_RXFIFO32 == 1 } then { set tmpvar_33 "32" } - global CONFIG_SPW_RXFIFO64 - if { $CONFIG_SPW_RXFIFO64 == 1 } then { set tmpvar_33 "64" } - global tmpvar_34 - set tmpvar_34 "64" - global CONFIG_SPW_RMAPBUF2 - if { $CONFIG_SPW_RMAPBUF2 == 1 } then { set tmpvar_34 "64" } - global CONFIG_SPW_RMAPBUF4 - if { $CONFIG_SPW_RMAPBUF4 == 1 } then { set tmpvar_34 "128" } - global CONFIG_SPW_RMAPBUF6 - if { $CONFIG_SPW_RMAPBUF6 == 1 } then { set tmpvar_34 "192" } - global CONFIG_SPW_RMAPBUF8 - if { $CONFIG_SPW_RMAPBUF8 == 1 } then { set tmpvar_34 "256" } - global tmpvar_35 - set tmpvar_35 "2" - global CONFIG_SPW_GRSPW1 - if { $CONFIG_SPW_GRSPW1 == 1 } then { set tmpvar_35 "1" } - global CONFIG_SPW_GRSPW2 - if { $CONFIG_SPW_GRSPW2 == 1 } then { set tmpvar_35 "2" } - global tmpvar_36 - set tmpvar_36 "DDR" - global CONFIG_SPW_RX_SDR - if { $CONFIG_SPW_RX_SDR == 1 } then { set tmpvar_36 "SDR" } - global CONFIG_SPW_RX_DDR - if { $CONFIG_SPW_RX_DDR == 1 } then { set tmpvar_36 "DDR" } - global CONFIG_SPW_RX_XOR - if { $CONFIG_SPW_RX_XOR == 1 } then { set tmpvar_36 "Xor" } - global CONFIG_SPW_RX_AFLEX - if { $CONFIG_SPW_RX_AFLEX == 1 } then { set tmpvar_36 "Aeroflex" } - global tmpvar_37 - set tmpvar_37 "SDR" - global CONFIG_SPW_TX_SDR - if { $CONFIG_SPW_TX_SDR == 1 } then { set tmpvar_37 "SDR" } - global CONFIG_SPW_TX_DDR - if { $CONFIG_SPW_TX_DDR == 1 } then { set tmpvar_37 "DDR" } - global CONFIG_SPW_TX_AFLEX - if { $CONFIG_SPW_TX_AFLEX == 1 } then { set tmpvar_37 "Aeroflex" } - global tmpvar_38 - set tmpvar_38 "1" - global CONFIG_UA1_FIFO1 - if { $CONFIG_UA1_FIFO1 == 1 } then { set tmpvar_38 "1" } - global CONFIG_UA1_FIFO2 - if { $CONFIG_UA1_FIFO2 == 1 } then { set tmpvar_38 "2" } - global CONFIG_UA1_FIFO4 - if { $CONFIG_UA1_FIFO4 == 1 } then { set tmpvar_38 "4" } - global CONFIG_UA1_FIFO8 - if { $CONFIG_UA1_FIFO8 == 1 } then { set tmpvar_38 "8" } - global CONFIG_UA1_FIFO16 - if { $CONFIG_UA1_FIFO16 == 1 } then { set tmpvar_38 "16" } - global CONFIG_UA1_FIFO32 - if { $CONFIG_UA1_FIFO32 == 1 } then { set tmpvar_38 "32" } - global tmpvar_39 - set tmpvar_39 "1" - global CONFIG_UA2_FIFO1 - if { $CONFIG_UA2_FIFO1 == 1 } then { set tmpvar_39 "1" } - global CONFIG_UA2_FIFO2 - if { $CONFIG_UA2_FIFO2 == 1 } then { set tmpvar_39 "2" } - global CONFIG_UA2_FIFO4 - if { $CONFIG_UA2_FIFO4 == 1 } then { set tmpvar_39 "4" } - global CONFIG_UA2_FIFO8 - if { $CONFIG_UA2_FIFO8 == 1 } then { set tmpvar_39 "8" } - global CONFIG_UA2_FIFO16 - if { $CONFIG_UA2_FIFO16 == 1 } then { set tmpvar_39 "16" } - global CONFIG_UA2_FIFO32 - if { $CONFIG_UA2_FIFO32 == 1 } then { set tmpvar_39 "32" } -} - - -proc update_define_mainmenu {} { - global CONFIG_MODULES -} - - -# FILE: tail.tk -# This file is boilerplate TCL/TK function definitions for 'make xconfig'. -# -# CHANGES -# ======= -# -# 8 January 1998, Michael Elizabeth Chastain, -# Arrange buttons in three columns for better screen fitting. -# - -# -# Read the user's settings from .config. These will override whatever is -# in config.in. Don't do this if the user specified a -D to force -# the defaults. -# - -set defaults defconfig - -if { [file readable .config] == 1} then { - if { $argc > 0 } then { - if { [lindex $argv 0] != "-D" } then { - read_config .config - } - else - { - read_config $defaults - } - } else { - read_config .config - } -} else { - read_config $defaults -} - -update_define 1 $total_menus 0 -update_mainmenu - -button .f0.right.save -anchor w -text "Save and Exit" -underline 0\ - -command { catch {exec cp -f .config .config.old}; \ - writeconfig .config config.h; wrapup .wrap } - -button .f0.right.quit -anchor w -text "Quit Without Saving" -underline 0\ - -command { maybe_exit .maybe } - -button .f0.right.load -anchor w -text "Load Configuration from File" \ - -command { load_configfile .load "Load Configuration from file" read_config_file -} - -button .f0.right.store -anchor w -text "Store Configuration to File" \ - -command { load_configfile .load "Store Configuration to file" write_config_file } - -# -# Now pack everything. -# - -pack .f0.right.store .f0.right.load .f0.right.quit .f0.right.save \ - -padx 0 -pady 0 -side bottom -fill x -pack .f0.left .f0.middle .f0.right -side left -padx 5 -pady 0 -fill y -pack .f0 -padx 5 -pady 5 - -update idletasks -set winy [expr 10 + [winfo reqheight .f0]] -set scry [lindex [wm maxsize .] 1] -set winx [expr 10 + [winfo reqwidth .f0]] -set scrx [lindex [wm maxsize .] 0] -if {$winx < $scrx} then {set maxx -1} else {set maxx $winx} -if {$winy < $scry} then {set maxy -1} else {set maxy $winy} -.f0 configure -width $winx -height $winy -wm maxsize . $maxx $maxy - -# -# If we cannot write our config files, disable the write button. -# -if { [file exists .config] == 1 } then { - if { [file writable .config] == 0 } then { - .f0.right.save configure -state disabled - } - } else { - if { [file writable .] == 0 } then { - .f0.right.save configure -state disabled - } - } - -#if { [file exists include/linux/autoconf.h] == 1 } then { -# if { [file writable include/linux/autoconf.h] == 0 } then { -# .f0.right.save configure -state disabled -# } -# } else { -# if { [file writable include/linux/] == 0 } then { -# .f0.right.save configure -state disabled -# } -# } diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/leon3mp.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon/leon3mp.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/leon3mp.vhd +++ /dev/null @@ -1,570 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -library techmap; -use techmap.gencomp.all; -library gaisler; -use gaisler.memctrl.all; -use gaisler.leon3.all; -use gaisler.uart.all; -use gaisler.misc.all; -library esa; -use esa.memoryctrl.all; -use work.config.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.lpp_memory.all; -use lpp.lpp_uart.all; -use lpp.lpp_matrix.all; -use lpp.lpp_delay.all; -use lpp.lpp_fft.all; -use lpp.fft_components.all; -use lpp.lpp_ad_conv.all; -use lpp.iir_filter.all; -use lpp.general_purpose.all; -use lpp.Filtercfg.all; - -entity leon3mp is - generic ( - fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console - pclow : integer := CFG_PCLOW - ); - port ( - clk50MHz : in std_ulogic; - reset : in std_ulogic; - ramclk : out std_logic; - - ahbrxd : in std_ulogic; -- DSU rx data - ahbtxd : out std_ulogic; -- DSU tx data - dsubre : in std_ulogic; - dsuact : out std_ulogic; - urxd1 : in std_ulogic; -- UART1 rx data - utxd1 : out std_ulogic; -- UART1 tx data - errorn : out std_ulogic; - - address : out std_logic_vector(18 downto 0); - data : inout std_logic_vector(31 downto 0); - gpio : inout std_logic_vector(6 downto 0); -- I/O port - - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------In/Out----------------------- ---------------------------------------------------------------------- --- UART - UART_RXD : in std_logic; - UART_TXD : out std_logic; --- ADC - ADC_in : in AD7688_in(4 downto 0); - ADC_out : out AD7688_out; - Bias_Fails : out std_logic; --- CNA --- DAC_SYNC : out std_logic; --- DAC_SCLK : out std_logic; --- DAC_DATA : out std_logic; --- Diver - SPW1_EN : out std_logic; - SPW2_EN : out std_logic; - TEST : out std_logic_vector(3 downto 0); ---------------------------------------------------------------------- - led : out std_logic_vector(1 downto 0) - ); -end; - -architecture Behavioral of leon3mp is - -constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG; -constant maxahbm : integer := maxahbmsp; - ---Clk & Rst géné -signal vcc : std_logic_vector(4 downto 0); -signal gnd : std_logic_vector(4 downto 0); -signal resetnl : std_ulogic; -signal clk2x : std_ulogic; -signal lclk : std_ulogic; -signal lclk2x : std_ulogic; -signal clkm : std_ulogic; -signal rstn : std_ulogic; -signal rstraw : std_ulogic; -signal pciclk : std_ulogic; -signal sdclkl : std_ulogic; -signal cgi : clkgen_in_type; -signal cgo : clkgen_out_type; ---- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); ---UART -signal ahbuarti : uart_in_type; -signal ahbuarto : uart_out_type; -signal apbuarti : uart_in_type; -signal apbuarto : uart_out_type; ---MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal wpo : wprot_out_type; -signal sdo : sdram_out_type; ---IRQ -signal irqi : irq_in_vector(0 to CFG_NCPU-1); -signal irqo : irq_out_vector(0 to CFG_NCPU-1); ---Timer -signal gpti : gptimer_in_type; -signal gpto : gptimer_out_type; ---GPIO -signal gpioi : gpio_in_type; -signal gpioo : gpio_out_type; ---DSU -signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); -signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); -signal dsui : dsu_in_type; -signal dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- --- FIFOs -signal FifoIN_Full : std_logic_vector(4 downto 0); -signal FifoIN_Empty : std_logic_vector(4 downto 0); -signal FifoIN_Data : std_logic_vector(79 downto 0); - -signal FifoINT_Full : std_logic_vector(4 downto 0); -signal FifoINT_Data : std_logic_vector(79 downto 0); - -signal FifoOUT_FullV : std_logic; -signal FifoOUT_Full : std_logic_vector(0 downto 0); - --- MATRICE SPECTRALE -signal Matrix_Write : std_logic; -signal Matrix_WriteV : std_logic_vector(0 downto 0); -signal Matrix_Read : std_logic_vector(1 downto 0); -signal Matrix_Result : std_logic_vector(31 downto 0); - -signal TopSM_Start : std_logic; -signal TopSM_Statu : std_logic_vector(3 downto 0); -signal TopSM_Read : std_logic_vector(4 downto 0); -signal TopSM_Data1 : std_logic_vector(15 downto 0); -signal TopSM_Data2 : std_logic_vector(15 downto 0); - --- FFT -signal Drive_Write : std_logic; -signal Drive_Read : std_logic_vector(4 downto 0); -signal Drive_DataRE : std_logic_vector(15 downto 0); -signal Drive_DataIM : std_logic_vector(15 downto 0); - -signal Start : std_logic; -signal FFT_Load : std_logic; -signal FFT_Ready : std_logic; -signal FFT_Valid : std_logic; -signal FFT_DataRE : std_logic_vector(15 downto 0); -signal FFT_DataIM : std_logic_vector(15 downto 0); - -signal Link_Read : std_logic; -signal Link_Write : std_logic_vector(4 downto 0); -signal Link_ReUse : std_logic_vector(4 downto 0); -signal Link_Data : std_logic_vector(79 downto 0); - --- ADC -signal SmplClk : std_logic; -signal ADC_DataReady : std_logic; -signal ADC_SmplOut : Samples_out(4 downto 0); -signal enableADC : std_logic; - -signal WG_Write : std_logic_vector(4 downto 0); -signal WG_ReUse : std_logic_vector(4 downto 0); -signal WG_DATA : std_logic_vector(79 downto 0); -signal s_out : std_logic_vector(79 downto 0); - -signal fuller : std_logic_vector(4 downto 0); -signal reader : std_logic_vector(4 downto 0); -signal try : std_logic_vector(1 downto 0); -signal TXDint : std_logic; - --- IIR Filter -signal sample_clk_out : std_logic; - ---------------------------------------------------------------------- -constant IOAEN : integer := CFG_CAN; -constant boardfreq : integer := 50000; - -begin - ---------------------------------------------------------------------- ---- AJOUT TEST -------------------------------------IPs------------- ---------------------------------------------------------------------- -led(1 downto 0) <= gpio(1 downto 0); - ---- COM USB --------------------------------------------------------- --- MemIn0 : APB_FifoWrite --- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) --- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); --- --- BUF0 : APB_USB --- generic map (6,6,DataMax => 1024) --- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); --- --- MemOut0 : APB_FifoRead --- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) --- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); --- ---slrd <= usb_Read; ---slwr <= usb_Write; - ---- CNA ------------------------------------------------------------- - --- CONV : APB_CNA --- generic map (5,5) --- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); - ---TEST(0) <= SmplClk; ---TEST(1) <= WG_Write(0); ---TEST(2) <= Fuller(0); ---TEST(3) <= s_out(s_out'length-1); - - -SPW1_EN <= '1'; -SPW2_EN <= '0'; - ---- CAN ------------------------------------------------------------- - - Divider : Clk_divider - generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) - Port map(clkm,rstn,SmplClk); - - ADC : AD7688_drvr - generic map (ChanelCount => 5, clkkHz => 24_576) - port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); - - WG : WriteGen_ADC - port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); - -enableADC <= gpio(0); -Bias_Fails <= '0'; -WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); - --- MemIn :lppFIFOx5 --- generic map(Data_sz => 16, Enable_ReUse => '0') --- port map(rstn,clkm,clkm,WG_ReUse,WG_Write,reader,WG_DATA,FifoIN_Data,FifoIN_Full,FifoIN_Empty); - - MemIn : APB_FIFO - generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) - port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); - ---- FFT ------------------------------------------------------------- - --- MemIn : APB_FIFO --- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(6)); - -Start <= not rstn; - - DRIVE : Driver_FFT - generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Full,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM); - - FFT : CoreFFT - generic map( - LOGPTS => gLOGPTS, - LOGLOGPTS => gLOGLOGPTS, - WSIZE => gWSIZE, - TWIDTH => gTWIDTH, - DWIDTH => gDWIDTH, - TDWIDTH => gTDWIDTH, - RND_MODE => gRND_MODE, - SCALE_MODE => gSCALE_MODE, - PTS => gPTS, - HALFPTS => gHALFPTS, - inBuf_RWDLY => gInBuf_RWDLY) - port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); - - LINK : Linker_FFT - generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data); - ---- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- - - MemInt : lppFIFOx5 - generic map(Data_sz => 16, Enable_ReUse => '1') - port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); - -Matrix_WriteV(0) <= not Matrix_Write; -FifoOUT_FullV <= FifoOUT_Full(0); - - TopSM : TopMatrix_PDR - generic map (Input_SZ => 16) - port map (clkm,rstn,FifoINT_Data,FifoINT_Full,Matrix_Read,Matrix_Write,TopSM_Data1,TopSM_Data2,TopSM_Start,TopSM_Read,TopSM_Statu); - - SM : SpectralMatrix - generic map (Input_SZ => 16, Result_SZ => 32) - port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,FifoOUT_FullV,Matrix_Read,Matrix_Write,Matrix_Result); - ---- FIFO ------------------------------------------------------------- - - MemOut : APB_FIFO - generic map (pindex => 15, paddr => 15, FifoCnt => 1, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) - port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Matrix_WriteV,open,FifoOUT_Full,open,Matrix_Result,open,open,apbi,apbo(15)); - - Memtest : APB_FIFO - generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 1) - port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(9)); - ---- UART ------------------------------------------------------------- - - COM0 : APB_UART - generic map (pindex => 5, paddr => 5) - port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD); - ---- DELAY ------------------------------------------------------------ - - Delay0 : APB_Delay - generic map (pindex => 4, paddr => 4) - port map (clkm,rstn,apbi,apbo(4)); - ---- IIR Filter ------------------------------------------------------- -Test(0) <= sample_clk_out; - - - IIR1: APB_IIR_Filter - generic map( - tech => CFG_MEMTECH, - pindex => 8, - paddr => 8, - Sample_SZ => Sample_SZ, - ChanelsCount => ChanelsCount, - Coef_SZ => Coef_SZ, - CoefCntPerCel => CoefCntPerCel, - Cels_count => Cels_count, - virgPos => virgPos - ) - port map( - rst => rstn, - clk => clkm, - apbi => apbi, - apbo => apbo(8), - sample_clk_out => sample_clk_out, - GOtest => Test(1), - CoefsInitVal => (others => '1') - ); ----------------------------------------------------------------------- - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (others => '1'); gnd <= (others => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); - - clkgen0 : clkgen -- clock generator - generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; -process(lclk2x) -begin - if lclk2x'event and lclk2x = '1' then - lclk <= not lclk; - end if; -end process; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : if CFG_LEON3 = 1 generate - cpu : for i in 0 to CFG_NCPU-1 generate - u0 : leon3s -- LEON3 processor - generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - end generate; - errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); - - dsugen : if CFG_DSU = 1 generate - dsu0 : dsu3 -- LEON3 Debug Support Unit - generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); --- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); - dsui.enable <= '1'; - dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); - dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); - end generate; - end generate; - - nodsu : if CFG_DSU = 0 generate - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - end generate; - - irqctrl : if CFG_IRQ3_ENABLE /= 0 generate - irqctrl0 : irqmp -- interrupt controller - generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - port map (rstn, clkm, apbi, apbo(2), irqo, irqi); - end generate; - irq3 : if CFG_IRQ3_ENABLE = 0 generate - x : for i in 0 to CFG_NCPU-1 generate - irqi(i).irl <= "0000"; - end generate; - apbo(2) <= apb_none; - end generate; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - - memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - bdr : for i in 0 to 3 generate - data_pad : iopadv generic map (tech => padtech, width => 8) - port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), - memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); - end generate; - - - addr_pad : outpadv generic map (width => 19, tech => padtech) - port map (address, memo.address(20 downto 2)); - - - SSRAM_0:entity ssram_plugin - generic map (tech => padtech) - port map - (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - dcomgen : if CFG_AHB_UART = 1 generate - dcom0: ahbuart -- Debug UART - generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); - dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); --- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; - end generate; - nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR) - port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - - gpt : if CFG_GPT_ENABLE /= 0 generate - timer0 : gptimer -- timer unit - generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - port map (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; --- led(4) <= gpto.wdog; - end generate; - notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - ua1 : if CFG_UART1_ENABLE /= 0 generate - uart1 : apbuart -- UART 1 - generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); - apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; --- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; - end generate; - noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit - grgpio0: grgpio - generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) - port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : for i in 0 to 6 generate - pio_pad : iopad generic map (tech => padtech) - port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - end generate; - end generate; - - -end Behavioral; \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/leon3mp_libero.prj.convert.8.6.bak b/designs/Projet-LeonLFR-A3P3K-Sheldon/leon3mp_libero.prj.convert.8.6.bak deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/leon3mp_libero.prj.convert.8.6.bak +++ /dev/null @@ -1,2622 +0,0 @@ -KEY LIBERO "8.6" -KEY CAPTURE "8.6.2.10" -KEY HDLTechnology "VHDL" -KEY VendorTechnology_Family "Virtex2" -KEY VendorTechnology_Die "" -KEY VendorTechnology_Package "" -KEY ProjectLocation "." -KEY SimulationType "VHDL" -KEY Vendor "Actel" -KEY ActiveRoot "leon3mp" -LIST REVISIONS -VALUE="Impl1",NUM=1 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"/../../lib/gaisler/misc/logan.vhd,hdl" -VALUE "/../../lib/gaisler/misc/apbps2.vhd,hdl" -VALUE "/../../lib/gaisler/misc/charrom_package.vhd,hdl" -VALUE "/../../lib/gaisler/misc/charrom.vhd,hdl" -VALUE "/../../lib/gaisler/misc/apbvga.vhd,hdl" -VALUE "/../../lib/gaisler/misc/svgactrl.vhd,hdl" -VALUE "/../../lib/gaisler/misc/i2cmst.vhd,hdl" -VALUE "/../../lib/gaisler/misc/i2cmst_gen.vhd,hdl" -VALUE "/../../lib/gaisler/misc/spictrlx.vhd,hdl" -VALUE "/../../lib/gaisler/misc/spictrl.vhd,hdl" -VALUE "/../../lib/gaisler/misc/i2cslv.vhd,hdl" -VALUE "/../../lib/gaisler/misc/wild.vhd,hdl" -VALUE "/../../lib/gaisler/misc/wild2ahb.vhd,hdl" -VALUE "/../../lib/gaisler/misc/grsysmon.vhd,hdl" -VALUE "/../../lib/gaisler/misc/gracectrl.vhd,hdl" -VALUE "/../../lib/gaisler/misc/grgpreg.vhd,hdl" -VALUE "/../../lib/gaisler/misc/ahbmst2.vhd,hdl" -VALUE "/../../lib/gaisler/misc/ahb_mst_iface.vhd,hdl" -VALUE "/../../lib/gaisler/ambatest/ahbtbp.vhd,hdl" -VALUE "/../../lib/gaisler/ambatest/ahbtbm.vhd,hdl" -VALUE "/../../lib/gaisler/net/net.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pci.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pcilib.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pciahbmst.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pcitrace.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pci_target.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pci_mt.vhd,hdl" -VALUE "/../../lib/gaisler/pci/dmactrl.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pci_mtf.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pcipads.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pcidma.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pt/pt_pkg.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pt/pt_pci_master.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pt/pt_pci_target.vhd,hdl" -VALUE "/../../lib/gaisler/pci/pt/pt_pci_arb.vhd,hdl" -VALUE "/../../lib/gaisler/uart/uart.vhd,hdl" -VALUE "/../../lib/gaisler/uart/libdcom.vhd,hdl" -VALUE "/../../lib/gaisler/uart/apbuart.vhd,hdl" -VALUE "/../../lib/gaisler/uart/dcom.vhd,hdl" -VALUE "/../../lib/gaisler/uart/dcom_uart.vhd,hdl" -VALUE "/../../lib/gaisler/uart/ahbuart.vhd,hdl" -VALUE "/../../lib/gaisler/sim/i2c_slave_model.v,hdl" -VALUE "/../../lib/gaisler/sim/sim.vhd,hdl" -VALUE "/../../lib/gaisler/sim/sram.vhd,hdl" -VALUE "/../../lib/gaisler/sim/ata_device.vhd,hdl" -VALUE "/../../lib/gaisler/sim/sram16.vhd,hdl" -VALUE "/../../lib/gaisler/sim/phy.vhd,hdl" -VALUE "/../../lib/gaisler/sim/ahbrep.vhd,hdl" -VALUE "/../../lib/gaisler/sim/delay_wire.vhd,hdl" -VALUE "/../../lib/gaisler/sim/spi_flash.vhd,hdl" -VALUE "/../../lib/gaisler/sim/pwm_check.vhd,hdl" -VALUE "/../../lib/gaisler/sim/usbsim.vhd,hdl" -VALUE "/../../lib/gaisler/sim/grusbdcsim.vhd,hdl" -VALUE "/../../lib/gaisler/sim/grusb_dclsim.vhd,hdl" -VALUE "/../../lib/gaisler/jtag/jtag.vhd,hdl" -VALUE "/../../lib/gaisler/jtag/libjtagcom.vhd,hdl" -VALUE "/../../lib/gaisler/jtag/jtagcom.vhd,hdl" -VALUE "/../../lib/gaisler/jtag/ahbjtag.vhd,hdl" -VALUE "/../../lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl" -VALUE "/../../lib/gaisler/jtag/bscanregs.vhd,hdl" -VALUE "/../../lib/gaisler/jtag/bscanregsbd.vhd,hdl" -VALUE "/../../lib/gaisler/jtag/jtagtst.vhd,hdl" -VALUE "/../../lib/gaisler/greth/ethernet_mac.vhd,hdl" -VALUE "/../../lib/gaisler/greth/greth.vhd,hdl" -VALUE "/../../lib/gaisler/greth/greth_mb.vhd,hdl" -VALUE "/../../lib/gaisler/greth/greth_gbit.vhd,hdl" -VALUE "/../../lib/gaisler/greth/greth_gbit_mb.vhd,hdl" -VALUE "/../../lib/gaisler/greth/grethm.vhd,hdl" -VALUE "/../../lib/gaisler/spacewire/spacewire.vhd,hdl" -VALUE "/../../lib/gaisler/spacewire/grspw.vhd,hdl" -VALUE "/../../lib/gaisler/spacewire/grspw2.vhd,hdl" -VALUE "/../../lib/gaisler/spacewire/grspwm.vhd,hdl" -VALUE "/../../lib/gaisler/usb/grusb.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddrphy_wrap.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddrsp16a.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddrsp32a.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddrsp64a.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddrspa.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddr2spa.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddr2buf.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddr2spax.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddr2spax_ahb.vhd,hdl" -VALUE "/../../lib/gaisler/ddr/ddr2spax_ddr.vhd,hdl" -VALUE "/../../lib/gaisler/ata/ata.vhd,hdl" -VALUE "/../../lib/gaisler/ata/ata_inf.vhd,hdl" -VALUE "/../../lib/gaisler/ata/atahost_amba_slave.vhd,hdl" -VALUE "/../../lib/gaisler/ata/atahost_ahbmst.vhd,hdl" -VALUE "/../../lib/gaisler/ata/ocidec2_amba_slave.vhd,hdl" -VALUE "/../../lib/gaisler/ata/atactrl_nodma.vhd,hdl" -VALUE "/../../lib/gaisler/ata/atactrl_dma.vhd,hdl" -VALUE "/../../lib/gaisler/ata/atactrl.vhd,hdl" -VALUE "/../../lib/gaisler/gr1553b/gr1553b_pkg.vhd,hdl" -VALUE "/../../lib/esa/memoryctrl/memoryctrl.vhd,hdl" -VALUE "/../../lib/esa/memoryctrl/mctrl.vhd,hdl" -VALUE "/../../lib/esa/pci/pcicomp.vhd,hdl" -VALUE "/../../lib/esa/pci/pci_arb_pkg.vhd,hdl" -VALUE "/../../lib/esa/pci/pci_arb.vhd,hdl" -VALUE "/../../lib/esa/pci/pciarb.vhd,hdl" -VALUE "/../../lib/gleichmann/clockgen/ge_clkgen_p.vhd,hdl" -VALUE "/../../lib/gleichmann/clockgen/clockgenerator_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/miscellaneous/postponer.v,hdl" -VALUE "/../../lib/gleichmann/miscellaneous/ahb2wb.v,hdl" -VALUE "/../../lib/gleichmann/miscellaneous/miscellaneous_p.vhd,hdl" -VALUE "/../../lib/gleichmann/ahb2hpi/hpi_p.vhd,hdl" -VALUE "/../../lib/gleichmann/ahb2hpi/ahb2hpi2_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/ahb2hpi/hpi_ram_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/i2c/i2c.vhd,hdl" -VALUE "/../../lib/gleichmann/i2c/partoi2s.vhd,hdl" -VALUE "/../../lib/gleichmann/dac/dac_p.vhd,hdl" -VALUE "/../../lib/gleichmann/dac/dac_sigdelt_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/dac/adc_sigdelt_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/dac/adcdac_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/dac/dac_ahb_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/spi/sspi_p.vhd,hdl" -VALUE "/../../lib/gleichmann/spi/spi_oc_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/spi/spi_p.vhd,hdl" -VALUE "/../../lib/gleichmann/spi/spi_xmit_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/multiio/multiio_p.vhd,hdl" -VALUE "/../../lib/gleichmann/multiio/multiio_ea.vhd,hdl" -VALUE "/../../lib/gleichmann/ac97/ac97.vhd,hdl" -VALUE "/../../lib/gleichmann/ac97/ac97_oc.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/spi_slave_model.v,hdl" -VALUE "/../../lib/gleichmann/sim/txt_util.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/phy_ext.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/uart_ext.vhd,hdl" -VALUE "/../../lib/fmf/utilities/conversions.vhd,hdl" -VALUE "/../../lib/fmf/utilities/gen_utils.vhd,hdl" -VALUE "/../../lib/fmf/flash/flash.vhd,hdl" -VALUE "/../../lib/fmf/flash/s25fl064a.vhd,hdl" -VALUE "/../../lib/fmf/flash/m25p80.vhd,hdl" -VALUE "/../../lib/fmf/fifo/idt7202.vhd,hdl" -VALUE "/../../lib/gsi/ssram/functions.vhd,hdl" -VALUE "/../../lib/gsi/ssram/core_burst.vhd,hdl" -VALUE "/../../lib/gsi/ssram/g880e18bt.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTER.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/ALU.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Adder.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Clk_divider.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_MUX.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_REG.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MUX2.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Multiplier.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/REG.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Shifter.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/general_purpose.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/ApbDriver.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/UART.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" -VALUE "/../../lib/cypress/ssram/components.vhd,hdl" -VALUE "/../../lib/cypress/ssram/package_utility.vhd,hdl" -VALUE "/../../lib/cypress/ssram/cy7c1354b.vhd,hdl" -VALUE "/../../lib/cypress/ssram/cy7c1380d.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/HY5PS121621F.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/components.vhd,hdl" -VALUE "/../../lib/micron/sdram/mobile_sdr.v,hdl" -VALUE "/../../lib/micron/sdram/components.vhd,hdl" -VALUE "/../../lib/micron/sdram/mt48lc16m16a2.vhd,hdl" -VALUE "/../../lib/micron/ddr/ddr2.v,hdl" -VALUE "/../../lib/micron/ddr/mobile_ddr.v,hdl" -VALUE "/../../lib/micron/ddr/ddr3.v,hdl" -VALUE "/../../lib/micron/ddr/mt46v16m16.vhd,hdl" -VALUE "/../../lib/openchip/gpio/gpio.vhd,hdl" -VALUE "/../../lib/openchip/gpio/apbgpio.vhd,hdl" -VALUE "/../../lib/openchip/charlcd/charlcd.vhd,hdl" -VALUE "/../../lib/openchip/charlcd/apbcharlcd.vhd,hdl" -VALUE "/../../lib/openchip/sui/sui.vhd,hdl" -VALUE "/../../lib/openchip/sui/apbsui.vhd,hdl" -VALUE "/../../lib/work/debug/debug.vhd,hdl" -VALUE "/../../lib/work/debug/grtestmod.vhd,hdl" -VALUE "/../../lib/work/debug/cpu_disas.vhd,hdl" -VALUE "/config.vhd,hdl" -VALUE "/ahbrom.vhd,hdl" -VALUE "/leon3mp.vhd,hdl" -ENDFILELIST -ENDLIST -ENDLIST -ENDLIST diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/linkprom b/designs/Projet-LeonLFR-A3P3K-Sheldon/linkprom deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/linkprom +++ /dev/null @@ -1,155 +0,0 @@ -/* linkcmds - * - * $Id: linkcmds,v 1.8.2.1 2000/05/24 17:06:38 joel Exp $ - */ - -OUTPUT_ARCH(sparc) -__DYNAMIC = 0; - -/* - * The memory map looks like this: - * +--------------------+ <- low memory - * | .text | - * | etext | - * | ctor list | the ctor and dtor lists are for - * | dtor list | C++ support - * | _endtext | - * +--------------------+ - * | .data | initialized data goes here - * | _sdata | - * | _edata | - * +--------------------+ - * | .bss | - * | __bss_start | start of bss, cleared by crt0 - * | _end | start of heap, used by sbrk() - * +--------------------+ - * | heap space | - * | _ENDHEAP | - * | stack space | - * | __stack | top of stack - * +--------------------+ <- high memory - */ - - -/* Default values, can be overridden */ - -_PROM_SIZE = 2M; -_RAM_SIZE = 4M; - -_RAM_START = 0x02000000; -_RAM_END = _RAM_START + _RAM_SIZE; - -_PROM_START = 0x00000000; -_PROM_END = _PROM_START + _PROM_SIZE; - -/* - * Alternate names without leading _. - */ - -PROM_START = _PROM_START; -PROM_SIZE = _PROM_SIZE; -PROM_END = _PROM_END; - -RAM_START = _RAM_START; -RAM_SIZE = _RAM_SIZE; -RAM_END = _RAM_END; - -_LEON_REG = 0x80000000; -LEON_REG = 0x80000000; - -/* these are the maximum values */ - -MEMORY -{ - rom : ORIGIN = 0x00000000, LENGTH = 16M - ram : ORIGIN = 0x40000000, LENGTH = 1024M -} - -SECTIONS -{ - .text : - { - CREATE_OBJECT_SYMBOLS - text_start = .; - _text_start = .; - *(.text) - . = ALIGN (16); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t*) - - /* - * C++ constructors - */ - __CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - __CTOR_END__ = .; - __DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - __DTOR_END__ = .; - - _rodata_start = . ; - *(.rodata*) - *(.gnu.linkonce.r*) - _erodata = ALIGN( 0x10 ) ; - - etext = ALIGN(0x10); - _etext = .; - *(.init) - *(.fini) - *(.lit) - *(.shdata) - . = ALIGN (16); - _endtext = .; - } > rom - .dynamic : { *(.dynamic) } >ram - .got : { *(.got) } >ram - .plt : { *(.plt) } >ram - .hash : { *(.hash) } >ram - .dynrel : { *(.dynrel) } >ram - .dynsym : { *(.dynsym) } >ram - .dynstr : { *(.dynstr) } >ram - .hash : { *(.hash) } >ram - .data : - { - data_start = .; - _data_start = .; - _sdata = . ; - *(.data) - *(.gnu.linkonce.d*) - *(.gcc_except_table) - . = ALIGN(0x10); - edata = .; - _edata = .; - } > ram - .shbss : - { - *(.shbss) - } > ram - .bss : - { - __bss_start = ALIGN(0x8); - _bss_start = .; - bss_start = .; - *(.bss) - *(COMMON) - end = .; - _end = ALIGN(0x8); - __end = ALIGN(0x8); - } > ram - .jcr . (NOLOAD) : { *(.jcr) } - .stab . (NOLOAD) : - { - [ .stab ] - } - .stabstr . (NOLOAD) : - { - [ .stabstr ] - } -} diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/prom.h b/designs/Projet-LeonLFR-A3P3K-Sheldon/prom.h deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/prom.h +++ /dev/null @@ -1,10 +0,0 @@ -#define MCFG1 0x10380233 -#define MCFG2 0xe6A26e60 -#define MCFG3 0x000ff000 -#define ASDCFG 0xfff00100 -#define DSDCFG 0xe6A06e60 -#define L2MCTRLIO 0x80000000 -#define IRQCTRL 0x80000200 -#define RAMSTART 0x40000000 -#define RAMSIZE 0x00100000 - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/prom.srec b/designs/Projet-LeonLFR-A3P3K-Sheldon/prom.srec deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/prom.srec +++ /dev/null @@ -1,37 +0,0 @@ -S00C000070726F6D2E737265635A -S113000081D8200003000004821060E08188400051 -S1130010819000008198000081800000A180000090 -S113002001000000030020408210600FC2A00040C5 -S11300308410000001000000010000000100000025 -S11300400100000001000000801080020100000097 -S11300500100000001000000010000000100000098 -S1130060874440008608E01F881000008A100000C2 -S11300708C1000008E100000A0100000A2100000E0 -S1130080A4100000A6100000A8100000AA10000090 -S1130090AC100000AE1000009010000092100000A0 -S11300A09410000096100000981000009A100000B0 -S11300B09C1000009E10000086A0E00116BFFFEF18 -S11300C081E00000821020028190400003000004BF -S11300D0821060E0818840000100000001000000FF -S11300E001000000834800008330600C80886001B8 -S11300F00280002401000000070000008610E1785F -S1130100C108C000C118C000C518C000C918C0008B -S1130110CD18C000D118C000D518C000D918C0002F -S1130120DD18C000E118C000E518C000E918C000DF -S1130130ED18C000F118C000F518C000F918C0008F -S1130140FD18C000010000000100000001000000D3 -S1130150010000000100000089A008420100000025 -S113016001000000010000000100000010800005F3 -S11301700100000001000000000000000000000079 -S1130180874440008730E01C8688E00F1280001608 -S11301900320000005040E008410A233C420400094 -S11301A00539A89B8410A260C4206004050003FCE8 -S11301B0C420600882103860C40040008530A00C60 -S11301C0030000048210600980A04002128000062F -S11301D0033FFC00821061000539A81B8410A26053 -S11301E0C4204000050000808210000080A0E000D0 -S11301F002800005010000008200400210BFFFFCE5 -S11302008620E0013D1003FFBC17A3E0BC2780015A -S11302109C27A0600310000081C040000100000082 -S113022000000000000000000000000000000000CA -S9030000FC diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/rhumc.dc b/designs/Projet-LeonLFR-A3P3K-Sheldon/rhumc.dc deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/rhumc.dc +++ /dev/null @@ -1,101 +0,0 @@ -/*******************************************/ -/* Script to compile leon with synopsys DC */ -/* Jiri Gaisler, Gaisler Research, 2004 */ -/*******************************************/ - -search_path = {"." "/usr/local/synlibs/DesignKit_DARE_V2.0/DesignKit/IO/syn" "/usr/local/synlibs/DesignKit_DARE_V2.0/DesignKit/CORE/syn" "/usr/local/synlibs/rhumc" "/usr/local/synopsys/libraries/syn"} -target_library = "RadHardUMC18_CORE_WCMIL.db" -link_library = "RadHardUMC18_CORE_WCMIL.db rhmem_wcmil.db Post_RH_UMC018_IOLIB_WCMIL.db" -link_library = "*" + link_library -symbol_library = "generic.sdb" -allow_newer_db_files = "true"; - -/* constraints - tailor to your own technology. An average 0.35 std-cell tech - should give you 80 - 100 MHz depending on ram access time. A 0.25 tech - should run at +150 MHz. Frequency in MHz, delays in ns ... */ - -frequency = 200 -clock_skew = 0.10 -input_setup = 2.0 -output_delay = 4.0 - -/* don't touch anything from here unless you know what you are doing */ - -include leon3mp.dc - -ungroup find(cell, "*pad*") -flatten - -group find(cell, {"sr*", "sdc", "apb*", "uart*", "timer*", "irq*" \ - "ahb*", "dsu0", "rst0", "dcom*" }) -design_name amod \ - -cell_name amod0 - -current_instance u0_0/p0 -ungroup -all -flatten -current_instance ../rf0 -ungroup -all -flatten -current_instance ../cmem0 -ungroup -all -flatten -current_instance ../../amod0 -ungroup -all -flatten -current_instance .. - -peri = 1000.0 / frequency -input_delay = peri - input_setup -tdelay = output_delay + 2 -create_clock -name "clk" -period peri -waveform { 0.0, peri / 2.0 } { "clk" } -set_wire_load_mode segmented - -set_clock_skew -plus_uncertainty clock_skew "clk" -set_clock_skew -minus_uncertainty clock_skew "clk" - -/* -set_input_delay input_delay -clock clk { \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" "brdyn" "bexcn" } - -set_max_delay tdelay -to { "errorn" "wdogn" \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" } - -set_max_delay output_delay -to { \ - "writen" "romsn[1]" "romsn[0]" "read" "oen" \ - "iosn" "rwen[3]" "rwen[2]" "rwen[1]" "rwen[0]" "ramsn[3]" \ - "ramsn[2]" "ramsn[1]" "ramsn[0]" \ - "ramoen[3]" "ramoen[2]" "ramoen[1]" "ramoen[0]" \ - "sdcsn[1]" "sdcsn[0]" "sdwen" "sdrasn" "sdcasn" \ - "sddqm[3]" "sddqm[2]" "sddqm[1]" "sddqm[0]" \ - "address[27]" "address[26]" "address[25]" "address[24]" \ - "address[23]" "address[22]" "address[21]" "address[20]" \ - "address[19]" "address[18]" "address[17]" "address[16]" \ - "address[15]" "address[14]" "address[13]" "address[12]" \ - "address[11]" "address[10]" "address[9]" "address[8]" \ - "address[7]" "address[6]" "address[5]" "address[4]" \ - "address[3]" "address[2]" "address[1]" "address[0]"} - -*/ -set_max_area 0 -set_max_transition 2.0 leon3mp -set_flatten false -design {"leon3mp.db:leon3mp"} -set_structure true -design {"leon3mp.db:leon3mp"} -boolean false -timing true - - -compile -map_effort medium -boundary_optimization - -write -f db -hier leon3mp -output leon3mp.db - -report_timing -report_area diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/run_simu.do b/designs/Projet-LeonLFR-A3P3K-Sheldon/run_simu.do deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/run_simu.do +++ /dev/null @@ -1,33 +0,0 @@ - - -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actar.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actram.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftDp.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftSm.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fft_components.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/primitives.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/twiddle.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd - -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd -# vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd - - vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd - -vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/TestModule_ADS7886.vhd -vcom -quiet -93 -work work TestBench.vhd - -vsim work.testbench \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/sdram.srec b/designs/Projet-LeonLFR-A3P3K-Sheldon/sdram.srec deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/sdram.srec +++ /dev/null @@ -1,19492 +0,0 @@ -S00D0000736472616D2E7372656300 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-S31540050C100000000000000000000000000000000089 -S31540050C200000000000000000000000000000000079 -S31540050C3080000100000000080000000700000006D3 -S31540050C40000000030000000000000000FFFF8AD0FE -S30940050C5080000310C2 -S70540000000BA diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/systest.c b/designs/Projet-LeonLFR-A3P3K-Sheldon/systest.c deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/systest.c +++ /dev/null @@ -1,10 +0,0 @@ - -main() - -{ - report_start(); - - base_test(); - - report_end(); -} diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/tkconfig.h b/designs/Projet-LeonLFR-A3P3K-Sheldon/tkconfig.h deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/tkconfig.h +++ /dev/null @@ -1,1189 +0,0 @@ -#if defined CONFIG_SYN_INFERRED -#define CONFIG_SYN_TECH inferred -#elif defined CONFIG_SYN_UMC -#define CONFIG_SYN_TECH umc -#elif defined CONFIG_SYN_RHUMC -#define CONFIG_SYN_TECH rhumc -#elif defined CONFIG_SYN_ATC18 -#define CONFIG_SYN_TECH atc18s -#elif defined CONFIG_SYN_ATC18RHA -#define CONFIG_SYN_TECH atc18rha -#elif defined CONFIG_SYN_AXCEL -#define CONFIG_SYN_TECH axcel -#elif defined CONFIG_SYN_PROASICPLUS -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_ALTERA -#define CONFIG_SYN_TECH altera -#elif defined CONFIG_SYN_STRATIX -#define CONFIG_SYN_TECH stratix1 -#elif defined CONFIG_SYN_STRATIXII -#define CONFIG_SYN_TECH stratix2 -#elif defined CONFIG_SYN_STRATIXIII -#define CONFIG_SYN_TECH stratix3 -#elif defined CONFIG_SYN_CYCLONEIII -#define CONFIG_SYN_TECH cyclone3 -#elif defined CONFIG_SYN_EASIC90 -#define CONFIG_SYN_TECH easic90 -#elif defined CONFIG_SYN_IHP25 -#define CONFIG_SYN_TECH ihp25 -#elif defined CONFIG_SYN_IHP25RH -#define CONFIG_SYN_TECH ihp25rh -#elif defined CONFIG_SYN_LATTICE -#define CONFIG_SYN_TECH lattice -#elif defined CONFIG_SYN_ECLIPSE -#define CONFIG_SYN_TECH eclipse -#elif defined CONFIG_SYN_PEREGRINE -#define CONFIG_SYN_TECH peregrine -#elif defined CONFIG_SYN_PROASIC -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_PROASIC3 -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_SPARTAN2 -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEX -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEXE -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_SPARTAN3 -#define CONFIG_SYN_TECH spartan3 -#elif defined CONFIG_SYN_SPARTAN3E -#define CONFIG_SYN_TECH spartan3e -#elif defined CONFIG_SYN_VIRTEX2 -#define CONFIG_SYN_TECH virtex2 -#elif defined CONFIG_SYN_VIRTEX4 -#define CONFIG_SYN_TECH virtex4 -#elif defined CONFIG_SYN_VIRTEX5 -#define CONFIG_SYN_TECH virtex5 -#elif defined CONFIG_SYN_RH_LIB18T -#define CONFIG_SYN_TECH rhlib18t -#elif defined CONFIG_SYN_SMIC13 -#define CONFIG_SYN_TECH smic013 -#elif defined CONFIG_SYN_UT025CRH -#define CONFIG_SYN_TECH ut25 -#elif defined CONFIG_SYN_TSMC90 -#define CONFIG_SYN_TECH tsmc90 -#elif defined CONFIG_SYN_CUSTOM1 -#define CONFIG_SYN_TECH custom1 -#else -#error "unknown target technology" -#endif - -#if defined CONFIG_SYN_INFER_RAM -#define CFG_RAM_TECH inferred -#elif defined CONFIG_MEM_UMC -#define CFG_RAM_TECH umc -#elif defined CONFIG_MEM_RHUMC -#define CFG_RAM_TECH rhumc -#elif defined CONFIG_MEM_VIRAGE -#define CFG_RAM_TECH memvirage -#elif defined CONFIG_MEM_ARTISAN -#define CFG_RAM_TECH memartisan -#elif defined CONFIG_MEM_CUSTOM1 -#define CFG_RAM_TECH custom1 -#elif defined CONFIG_MEM_VIRAGE90 -#define CFG_RAM_TECH memvirage90 -#elif defined CONFIG_MEM_INFERRED -#define CFG_RAM_TECH inferred -#else -#define CFG_RAM_TECH CONFIG_SYN_TECH -#endif - -#if defined CONFIG_SYN_INFER_PADS -#define CFG_PAD_TECH inferred -#else -#define CFG_PAD_TECH CONFIG_SYN_TECH -#endif - -#ifndef CONFIG_SYN_NO_ASYNC -#define CONFIG_SYN_NO_ASYNC 0 -#endif - -#ifndef CONFIG_SYN_SCAN -#define CONFIG_SYN_SCAN 0 -#endif - - -#if defined CONFIG_CLK_ALTDLL -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_HCLKBUF -#define CFG_CLK_TECH axcel -#elif defined CONFIG_CLK_LATDLL -#define CFG_CLK_TECH lattice -#elif defined CONFIG_CLK_PRO3PLL -#define CFG_CLK_TECH apa3 -#elif defined CONFIG_CLK_CLKDLL -#define CFG_CLK_TECH virtex -#elif defined CONFIG_CLK_DCM -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_LIB18T -#define CFG_CLK_TECH rhlib18t -#elif defined CONFIG_CLK_RHUMC -#define CFG_CLK_TECH rhumc -#else -#define CFG_CLK_TECH inferred -#endif - -#ifndef CONFIG_CLK_MUL -#define CONFIG_CLK_MUL 2 -#endif - -#ifndef CONFIG_CLK_DIV -#define CONFIG_CLK_DIV 2 -#endif - -#ifndef CONFIG_OCLK_DIV -#define CONFIG_OCLK_DIV 2 -#endif - -#ifndef CONFIG_PCI_CLKDLL -#define CONFIG_PCI_CLKDLL 0 -#endif - -#ifndef CONFIG_PCI_SYSCLK -#define CONFIG_PCI_SYSCLK 0 -#endif - -#ifndef CONFIG_CLK_NOFB -#define CONFIG_CLK_NOFB 0 -#endif -#ifndef CONFIG_LEON3 -#define CONFIG_LEON3 0 -#endif - -#ifndef CONFIG_PROC_NUM -#define CONFIG_PROC_NUM 1 -#endif - -#ifndef CONFIG_IU_NWINDOWS -#define CONFIG_IU_NWINDOWS 8 -#endif - -#ifndef CONFIG_IU_RSTADDR -#define CONFIG_IU_RSTADDR 8 -#endif - -#ifndef CONFIG_IU_LDELAY -#define CONFIG_IU_LDELAY 1 -#endif - -#ifndef CONFIG_IU_WATCHPOINTS -#define CONFIG_IU_WATCHPOINTS 0 -#endif - -#ifdef CONFIG_IU_V8MULDIV -#ifdef CONFIG_IU_MUL_LATENCY_4 -#define CFG_IU_V8 1 -#elif defined CONFIG_IU_MUL_LATENCY_5 -#define CFG_IU_V8 2 -#elif defined CONFIG_IU_MUL_LATENCY_2 -#define CFG_IU_V8 16#32# -#endif -#else -#define CFG_IU_V8 0 -#endif - -#ifndef CONFIG_PWD -#define CONFIG_PWD 0 -#endif - -#ifndef CONFIG_IU_MUL_MAC -#define CONFIG_IU_MUL_MAC 0 -#endif - -#ifndef CONFIG_IU_SVT -#define CONFIG_IU_SVT 0 -#endif - -#if defined CONFIG_FPU_GRFPC1 -#define CONFIG_FPU_GRFPC 1 -#elif defined CONFIG_FPU_GRFPC2 -#define CONFIG_FPU_GRFPC 2 -#else -#define CONFIG_FPU_GRFPC 0 -#endif - -#if defined CONFIG_FPU_GRFPU_INFMUL -#define CONFIG_FPU_GRFPU_MUL 0 -#elif defined CONFIG_FPU_GRFPU_DWMUL -#define CONFIG_FPU_GRFPU_MUL 1 -#elif defined CONFIG_FPU_GRFPU_MODGEN -#define CONFIG_FPU_GRFPU_MUL 2 -#else -#define CONFIG_FPU_GRFPU_MUL 0 -#endif - -#if defined CONFIG_FPU_GRFPU_SH -#define CONFIG_FPU_GRFPU_SHARED 1 -#else -#define CONFIG_FPU_GRFPU_SHARED 0 -#endif - -#if defined CONFIG_FPU_GRFPU -#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) -#elif defined CONFIG_FPU_MEIKO -#define CONFIG_FPU 15 -#elif defined CONFIG_FPU_GRFPULITE -#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) -#else -#define CONFIG_FPU 0 -#endif - -#ifndef CONFIG_FPU_NETLIST -#define CONFIG_FPU_NETLIST 0 -#endif - -#ifndef CONFIG_ICACHE_ENABLE -#define CONFIG_ICACHE_ENABLE 0 -#endif - -#if defined CONFIG_ICACHE_ASSO1 -#define CFG_IU_ISETS 1 -#elif defined CONFIG_ICACHE_ASSO2 -#define CFG_IU_ISETS 2 -#elif defined CONFIG_ICACHE_ASSO3 -#define CFG_IU_ISETS 3 -#elif defined CONFIG_ICACHE_ASSO4 -#define CFG_IU_ISETS 4 -#else -#define CFG_IU_ISETS 1 -#endif - -#if defined CONFIG_ICACHE_SZ1 -#define CFG_ICACHE_SZ 1 -#elif defined CONFIG_ICACHE_SZ2 -#define CFG_ICACHE_SZ 2 -#elif defined CONFIG_ICACHE_SZ4 -#define CFG_ICACHE_SZ 4 -#elif defined CONFIG_ICACHE_SZ8 -#define CFG_ICACHE_SZ 8 -#elif defined CONFIG_ICACHE_SZ16 -#define CFG_ICACHE_SZ 16 -#elif defined CONFIG_ICACHE_SZ32 -#define CFG_ICACHE_SZ 32 -#elif defined CONFIG_ICACHE_SZ64 -#define CFG_ICACHE_SZ 64 -#elif defined CONFIG_ICACHE_SZ128 -#define CFG_ICACHE_SZ 128 -#elif defined CONFIG_ICACHE_SZ256 -#define CFG_ICACHE_SZ 256 -#else -#define CFG_ICACHE_SZ 1 -#endif - -#ifdef CONFIG_ICACHE_LZ16 -#define CFG_ILINE_SZ 4 -#else -#define CFG_ILINE_SZ 8 -#endif - -#if defined CONFIG_ICACHE_ALGORND -#define CFG_ICACHE_ALGORND 2 -#elif defined CONFIG_ICACHE_ALGOLRR -#define CFG_ICACHE_ALGORND 1 -#else -#define CFG_ICACHE_ALGORND 0 -#endif - -#ifndef CONFIG_ICACHE_LOCK -#define CONFIG_ICACHE_LOCK 0 -#endif - -#ifndef CONFIG_ICACHE_LRAM -#define CONFIG_ICACHE_LRAM 0 -#endif - -#ifndef CONFIG_ICACHE_LRSTART -#define CONFIG_ICACHE_LRSTART 8E -#endif - -#if defined CONFIG_ICACHE_LRAM_SZ2 -#define CFG_ILRAM_SIZE 2 -#elif defined CONFIG_ICACHE_LRAM_SZ4 -#define CFG_ILRAM_SIZE 4 -#elif defined CONFIG_ICACHE_LRAM_SZ8 -#define CFG_ILRAM_SIZE 8 -#elif defined CONFIG_ICACHE_LRAM_SZ16 -#define CFG_ILRAM_SIZE 16 -#elif defined CONFIG_ICACHE_LRAM_SZ32 -#define CFG_ILRAM_SIZE 32 -#elif defined CONFIG_ICACHE_LRAM_SZ64 -#define CFG_ILRAM_SIZE 64 -#elif defined CONFIG_ICACHE_LRAM_SZ128 -#define CFG_ILRAM_SIZE 128 -#elif defined CONFIG_ICACHE_LRAM_SZ256 -#define CFG_ILRAM_SIZE 256 -#else -#define CFG_ILRAM_SIZE 1 -#endif - - -#ifndef CONFIG_DCACHE_ENABLE -#define CONFIG_DCACHE_ENABLE 0 -#endif - -#if defined CONFIG_DCACHE_ASSO1 -#define CFG_IU_DSETS 1 -#elif defined CONFIG_DCACHE_ASSO2 -#define CFG_IU_DSETS 2 -#elif defined CONFIG_DCACHE_ASSO3 -#define CFG_IU_DSETS 3 -#elif defined CONFIG_DCACHE_ASSO4 -#define CFG_IU_DSETS 4 -#else -#define CFG_IU_DSETS 1 -#endif - -#if defined CONFIG_DCACHE_SZ1 -#define CFG_DCACHE_SZ 1 -#elif defined CONFIG_DCACHE_SZ2 -#define CFG_DCACHE_SZ 2 -#elif defined CONFIG_DCACHE_SZ4 -#define CFG_DCACHE_SZ 4 -#elif defined CONFIG_DCACHE_SZ8 -#define CFG_DCACHE_SZ 8 -#elif defined CONFIG_DCACHE_SZ16 -#define CFG_DCACHE_SZ 16 -#elif defined CONFIG_DCACHE_SZ32 -#define CFG_DCACHE_SZ 32 -#elif defined CONFIG_DCACHE_SZ64 -#define CFG_DCACHE_SZ 64 -#elif defined CONFIG_DCACHE_SZ128 -#define CFG_DCACHE_SZ 128 -#elif defined CONFIG_DCACHE_SZ256 -#define CFG_DCACHE_SZ 256 -#else -#define CFG_DCACHE_SZ 1 -#endif - -#ifdef CONFIG_DCACHE_LZ16 -#define CFG_DLINE_SZ 4 -#else -#define CFG_DLINE_SZ 8 -#endif - -#if defined CONFIG_DCACHE_ALGORND -#define CFG_DCACHE_ALGORND 2 -#elif defined CONFIG_DCACHE_ALGOLRR -#define CFG_DCACHE_ALGORND 1 -#else -#define CFG_DCACHE_ALGORND 0 -#endif - -#ifndef CONFIG_DCACHE_LOCK -#define CONFIG_DCACHE_LOCK 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP -#define CONFIG_DCACHE_SNOOP 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_SEPTAG -#define CONFIG_DCACHE_SNOOP_SEPTAG 0 -#endif - -#ifndef CONFIG_CACHE_FIXED -#define CONFIG_CACHE_FIXED 0 -#endif - -#ifndef CONFIG_DCACHE_LRAM -#define CONFIG_DCACHE_LRAM 0 -#endif - -#ifndef CONFIG_DCACHE_LRSTART -#define CONFIG_DCACHE_LRSTART 8F -#endif - -#if defined CONFIG_DCACHE_LRAM_SZ2 -#define CFG_DLRAM_SIZE 2 -#elif defined CONFIG_DCACHE_LRAM_SZ4 -#define CFG_DLRAM_SIZE 4 -#elif defined CONFIG_DCACHE_LRAM_SZ8 -#define CFG_DLRAM_SIZE 8 -#elif defined CONFIG_DCACHE_LRAM_SZ16 -#define CFG_DLRAM_SIZE 16 -#elif defined CONFIG_DCACHE_LRAM_SZ32 -#define CFG_DLRAM_SIZE 32 -#elif defined CONFIG_DCACHE_LRAM_SZ64 -#define CFG_DLRAM_SIZE 64 -#elif defined CONFIG_DCACHE_LRAM_SZ128 -#define CFG_DLRAM_SIZE 128 -#elif defined CONFIG_DCACHE_LRAM_SZ256 -#define CFG_DLRAM_SIZE 256 -#else -#define CFG_DLRAM_SIZE 1 -#endif - -#if defined CONFIG_MMU_PAGE_4K -#define CONFIG_MMU_PAGE 0 -#elif defined CONFIG_MMU_PAGE_8K -#define CONFIG_MMU_PAGE 1 -#elif defined CONFIG_MMU_PAGE_16K -#define CONFIG_MMU_PAGE 2 -#elif defined CONFIG_MMU_PAGE_32K -#define CONFIG_MMU_PAGE 3 -#elif defined CONFIG_MMU_PAGE_PROG -#define CONFIG_MMU_PAGE 4 -#else -#define CONFIG_MMU_PAGE 0 -#endif - -#ifdef CONFIG_MMU_ENABLE -#define CONFIG_MMUEN 1 - -#ifdef CONFIG_MMU_SPLIT -#define CONFIG_TLB_TYPE 0 -#endif -#ifdef CONFIG_MMU_COMBINED -#define CONFIG_TLB_TYPE 1 -#endif - -#ifdef CONFIG_MMU_REPARRAY -#define CONFIG_TLB_REP 0 -#endif -#ifdef CONFIG_MMU_REPINCREMENT -#define CONFIG_TLB_REP 1 -#endif - -#ifdef CONFIG_MMU_I2 -#define CONFIG_ITLBNUM 2 -#endif -#ifdef CONFIG_MMU_I4 -#define CONFIG_ITLBNUM 4 -#endif -#ifdef CONFIG_MMU_I8 -#define CONFIG_ITLBNUM 8 -#endif -#ifdef CONFIG_MMU_I16 -#define CONFIG_ITLBNUM 16 -#endif -#ifdef CONFIG_MMU_I32 -#define CONFIG_ITLBNUM 32 -#endif - -#define CONFIG_DTLBNUM 2 -#ifdef CONFIG_MMU_D2 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 2 -#endif -#ifdef CONFIG_MMU_D4 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 4 -#endif -#ifdef CONFIG_MMU_D8 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 8 -#endif -#ifdef CONFIG_MMU_D16 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 16 -#endif -#ifdef CONFIG_MMU_D32 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 32 -#endif -#ifdef CONFIG_MMU_FASTWB -#define CFG_MMU_FASTWB 1 -#else -#define CFG_MMU_FASTWB 0 -#endif - -#else -#define CONFIG_MMUEN 0 -#define CONFIG_ITLBNUM 2 -#define CONFIG_DTLBNUM 2 -#define CONFIG_TLB_TYPE 1 -#define CONFIG_TLB_REP 1 -#define CFG_MMU_FASTWB 0 -#endif - -#ifndef CONFIG_DSU_ENABLE -#define CONFIG_DSU_ENABLE 0 -#endif - -#if defined CONFIG_DSU_ITRACESZ1 -#define CFG_DSU_ITB 1 -#elif CONFIG_DSU_ITRACESZ2 -#define CFG_DSU_ITB 2 -#elif CONFIG_DSU_ITRACESZ4 -#define CFG_DSU_ITB 4 -#elif CONFIG_DSU_ITRACESZ8 -#define CFG_DSU_ITB 8 -#elif CONFIG_DSU_ITRACESZ16 -#define CFG_DSU_ITB 16 -#else -#define CFG_DSU_ITB 0 -#endif - -#if defined CONFIG_DSU_ATRACESZ1 -#define CFG_DSU_ATB 1 -#elif CONFIG_DSU_ATRACESZ2 -#define CFG_DSU_ATB 2 -#elif CONFIG_DSU_ATRACESZ4 -#define CFG_DSU_ATB 4 -#elif CONFIG_DSU_ATRACESZ8 -#define CFG_DSU_ATB 8 -#elif CONFIG_DSU_ATRACESZ16 -#define CFG_DSU_ATB 16 -#else -#define CFG_DSU_ATB 0 -#endif - -#ifndef CONFIG_LEON3FT_EN -#define CONFIG_LEON3FT_EN 0 -#endif - -#if defined CONFIG_IUFT_PAR -#define CONFIG_IUFT_EN 1 -#elif defined CONFIG_IUFT_DMR -#define CONFIG_IUFT_EN 2 -#elif defined CONFIG_IUFT_BCH -#define CONFIG_IUFT_EN 3 -#elif defined CONFIG_IUFT_TMR -#define CONFIG_IUFT_EN 4 -#else -#define CONFIG_IUFT_EN 0 -#endif -#ifndef CONFIG_RF_ERRINJ -#define CONFIG_RF_ERRINJ 0 -#endif - -#ifndef CONFIG_FPUFT_EN -#define CONFIG_FPUFT 0 -#else -#ifdef CONFIG_FPU_GRFPU -#define CONFIG_FPUFT 2 -#else -#define CONFIG_FPUFT 1 -#endif -#endif - -#ifndef CONFIG_CACHE_FT_EN -#define CONFIG_CACHE_FT_EN 0 -#endif -#ifndef CONFIG_CACHE_ERRINJ -#define CONFIG_CACHE_ERRINJ 0 -#endif - -#ifndef CONFIG_LEON3_NETLIST -#define CONFIG_LEON3_NETLIST 0 -#endif - -#ifdef CONFIG_DEBUG_PC32 -#define CFG_DEBUG_PC32 0 -#else -#define CFG_DEBUG_PC32 2 -#endif -#ifndef CONFIG_IU_DISAS -#define CONFIG_IU_DISAS 0 -#endif -#ifndef CONFIG_IU_DISAS_NET -#define CONFIG_IU_DISAS_NET 0 -#endif - - -#ifndef CONFIG_AHB_SPLIT -#define CONFIG_AHB_SPLIT 0 -#endif - -#ifndef CONFIG_AHB_RROBIN -#define CONFIG_AHB_RROBIN 0 -#endif - -#ifndef CONFIG_AHB_IOADDR -#define CONFIG_AHB_IOADDR FFF -#endif - -#ifndef CONFIG_APB_HADDR -#define CONFIG_APB_HADDR 800 -#endif - -#ifndef CONFIG_AHB_MON -#define CONFIG_AHB_MON 0 -#endif - -#ifndef CONFIG_AHB_MONERR -#define CONFIG_AHB_MONERR 0 -#endif - -#ifndef CONFIG_AHB_MONWAR -#define CONFIG_AHB_MONWAR 0 -#endif - -#ifndef CONFIG_DSU_UART -#define CONFIG_DSU_UART 0 -#endif - - -#ifndef CONFIG_DSU_JTAG -#define CONFIG_DSU_JTAG 0 -#endif - -#ifndef CONFIG_DSU_ETH -#define CONFIG_DSU_ETH 0 -#endif - -#ifndef CONFIG_DSU_IPMSB -#define CONFIG_DSU_IPMSB C0A8 -#endif - -#ifndef CONFIG_DSU_IPLSB -#define CONFIG_DSU_IPLSB 0033 -#endif - -#ifndef CONFIG_DSU_ETHMSB -#define CONFIG_DSU_ETHMSB 020000 -#endif - -#ifndef CONFIG_DSU_ETHLSB -#define CONFIG_DSU_ETHLSB 000009 -#endif - -#if defined CONFIG_DSU_ETHSZ1 -#define CFG_DSU_ETHB 1 -#elif CONFIG_DSU_ETHSZ2 -#define CFG_DSU_ETHB 2 -#elif CONFIG_DSU_ETHSZ4 -#define CFG_DSU_ETHB 4 -#elif CONFIG_DSU_ETHSZ8 -#define CFG_DSU_ETHB 8 -#elif CONFIG_DSU_ETHSZ16 -#define CFG_DSU_ETHB 16 -#elif CONFIG_DSU_ETHSZ32 -#define CFG_DSU_ETHB 32 -#else -#define CFG_DSU_ETHB 1 -#endif - -#ifndef CONFIG_DSU_ETH_PROG -#define CONFIG_DSU_ETH_PROG 0 -#endif - - -#ifndef CONFIG_SRCTRL -#define CONFIG_SRCTRL 0 -#endif - -#ifndef CONFIG_SRCTRL_PROMWS -#define CONFIG_SRCTRL_PROMWS 0 -#endif - -#ifndef CONFIG_SRCTRL_RAMWS -#define CONFIG_SRCTRL_RAMWS 0 -#endif - -#ifndef CONFIG_SRCTRL_IOWS -#define CONFIG_SRCTRL_IOWS 0 -#endif - -#ifndef CONFIG_SRCTRL_RMW -#define CONFIG_SRCTRL_RMW 0 -#endif - -#ifndef CONFIG_SRCTRL_8BIT -#define CONFIG_SRCTRL_8BIT 0 -#endif - - -#ifndef CONFIG_SRCTRL_ROMASEL -#define CONFIG_SRCTRL_ROMASEL 0 -#endif - -#if defined CONFIG_SRCTRL_SRBANKS1 -#define CFG_SR_CTRL_SRBANKS 1 -#elif defined CONFIG_SRCTRL_SRBANKS2 -#define CFG_SR_CTRL_SRBANKS 2 -#elif defined CONFIG_SRCTRL_SRBANKS3 -#define CFG_SR_CTRL_SRBANKS 3 -#elif defined CONFIG_SRCTRL_SRBANKS4 -#define CFG_SR_CTRL_SRBANKS 4 -#elif defined CONFIG_SRCTRL_SRBANKS5 -#define CFG_SR_CTRL_SRBANKS 5 -#else -#define CFG_SR_CTRL_SRBANKS 1 -#endif - -#if defined CONFIG_SRCTRL_BANKSZ0 -#define CFG_SR_CTRL_BANKSZ 0 -#elif defined CONFIG_SRCTRL_BANKSZ1 -#define CFG_SR_CTRL_BANKSZ 1 -#elif defined CONFIG_SRCTRL_BANKSZ2 -#define CFG_SR_CTRL_BANKSZ 2 -#elif defined CONFIG_SRCTRL_BANKSZ3 -#define CFG_SR_CTRL_BANKSZ 3 -#elif defined CONFIG_SRCTRL_BANKSZ4 -#define CFG_SR_CTRL_BANKSZ 4 -#elif defined CONFIG_SRCTRL_BANKSZ5 -#define CFG_SR_CTRL_BANKSZ 5 -#elif defined CONFIG_SRCTRL_BANKSZ6 -#define CFG_SR_CTRL_BANKSZ 6 -#elif defined CONFIG_SRCTRL_BANKSZ7 -#define CFG_SR_CTRL_BANKSZ 7 -#elif defined CONFIG_SRCTRL_BANKSZ8 -#define CFG_SR_CTRL_BANKSZ 8 -#elif defined CONFIG_SRCTRL_BANKSZ9 -#define CFG_SR_CTRL_BANKSZ 9 -#elif defined CONFIG_SRCTRL_BANKSZ10 -#define CFG_SR_CTRL_BANKSZ 10 -#elif defined CONFIG_SRCTRL_BANKSZ11 -#define CFG_SR_CTRL_BANKSZ 11 -#elif defined CONFIG_SRCTRL_BANKSZ12 -#define CFG_SR_CTRL_BANKSZ 12 -#elif defined CONFIG_SRCTRL_BANKSZ13 -#define CFG_SR_CTRL_BANKSZ 13 -#else -#define CFG_SR_CTRL_BANKSZ 0 -#endif -#ifndef CONFIG_MCTRL_LEON2 -#define CONFIG_MCTRL_LEON2 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM -#define CONFIG_MCTRL_SDRAM 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_SEPBUS -#define CONFIG_MCTRL_SDRAM_SEPBUS 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_INVCLK -#define CONFIG_MCTRL_SDRAM_INVCLK 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_BUS64 -#define CONFIG_MCTRL_SDRAM_BUS64 0 -#endif - -#ifndef CONFIG_MCTRL_8BIT -#define CONFIG_MCTRL_8BIT 0 -#endif - -#ifndef CONFIG_MCTRL_16BIT -#define CONFIG_MCTRL_16BIT 0 -#endif - -#ifndef CONFIG_MCTRL_5CS -#define CONFIG_MCTRL_5CS 0 -#endif - -#ifndef CONFIG_MCTRL_EDAC -#define CONFIG_MCTRL_EDAC 0 -#endif - -#ifndef CONFIG_MCTRL_PAGE -#define CONFIG_MCTRL_PAGE 0 -#endif - -#ifndef CONFIG_MCTRL_PROGPAGE -#define CONFIG_MCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_SDCTRL -#define CONFIG_SDCTRL 0 -#endif - -#ifndef CONFIG_SDCTRL_SEPBUS -#define CONFIG_SDCTRL_SEPBUS 0 -#endif - -#ifndef CONFIG_SDCTRL_INVCLK -#define CONFIG_SDCTRL_INVCLK 0 -#endif - -#ifndef CONFIG_SDCTRL_BUS64 -#define CONFIG_SDCTRL_BUS64 0 -#endif - -#ifndef CONFIG_SDCTRL_PAGE -#define CONFIG_SDCTRL_PAGE 0 -#endif - -#ifndef CONFIG_SDCTRL_PROGPAGE -#define CONFIG_SDCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBROM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBROM_START -#define CONFIG_AHBROM_START 000 -#endif - -#ifndef CONFIG_AHBROM_PIPE -#define CONFIG_AHBROM_PIPE 0 -#endif - -#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) -#define CONFIG_ROM_START 100 -#else -#define CONFIG_ROM_START 000 -#endif - - -#ifndef CONFIG_AHBRAM_ENABLE -#define CONFIG_AHBRAM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBRAM_START -#define CONFIG_AHBRAM_START A00 -#endif - -#if defined CONFIG_AHBRAM_SZ1 -#define CFG_AHBRAMSZ 1 -#elif CONFIG_AHBRAM_SZ2 -#define CFG_AHBRAMSZ 2 -#elif CONFIG_AHBRAM_SZ4 -#define CFG_AHBRAMSZ 4 -#elif CONFIG_AHBRAM_SZ8 -#define CFG_AHBRAMSZ 8 -#elif CONFIG_AHBRAM_SZ16 -#define CFG_AHBRAMSZ 16 -#elif CONFIG_AHBRAM_SZ32 -#define CFG_AHBRAMSZ 32 -#elif CONFIG_AHBRAM_SZ64 -#define CFG_AHBRAMSZ 64 -#else -#define CFG_AHBRAMSZ 1 -#endif - -#ifndef CONFIG_GRETH_ENABLE -#define CONFIG_GRETH_ENABLE 0 -#endif - -#ifndef CONFIG_GRETH_GIGA -#define CONFIG_GRETH_GIGA 0 -#endif - -#if defined CONFIG_GRETH_FIFO4 -#define CFG_GRETH_FIFO 4 -#elif defined CONFIG_GRETH_FIFO8 -#define CFG_GRETH_FIFO 8 -#elif defined CONFIG_GRETH_FIFO16 -#define CFG_GRETH_FIFO 16 -#elif defined CONFIG_GRETH_FIFO32 -#define CFG_GRETH_FIFO 32 -#elif defined CONFIG_GRETH_FIFO64 -#define CFG_GRETH_FIFO 64 -#else -#define CFG_GRETH_FIFO 8 -#endif - -#ifndef CONFIG_CAN_ENABLE -#define CONFIG_CAN_ENABLE 0 -#endif - -#ifndef CONFIG_CANIO -#define CONFIG_CANIO 0 -#endif - -#ifndef CONFIG_CANIRQ -#define CONFIG_CANIRQ 0 -#endif - -#ifndef CONFIG_CANLOOP -#define CONFIG_CANLOOP 0 -#endif - -#ifndef CONFIG_CAN_SYNCRST -#define CONFIG_CAN_SYNCRST 0 -#endif - - -#ifndef CONFIG_CAN_FT -#define CONFIG_CAN_FT 0 -#endif -#if defined CONFIG_PCI_SIMPLE_TARGET -#define CFG_PCITYPE 1 -#elif defined CONFIG_PCI_MASTER_TARGET_DMA -#define CFG_PCITYPE 3 -#elif defined CONFIG_PCI_MASTER_TARGET -#define CFG_PCITYPE 2 -#else -#define CFG_PCITYPE 0 -#endif - -#ifndef CONFIG_PCI_VENDORID -#define CONFIG_PCI_VENDORID 0 -#endif - -#ifndef CONFIG_PCI_DEVICEID -#define CONFIG_PCI_DEVICEID 0 -#endif - -#ifndef CONFIG_PCI_REVID -#define CONFIG_PCI_REVID 0 -#endif - -#if defined CONFIG_PCI_FIFO0 -#define CFG_PCIFIFO 8 -#define CFG_PCI_ENFIFO 0 -#elif defined CONFIG_PCI_FIFO16 -#define CFG_PCIFIFO 16 -#elif defined CONFIG_PCI_FIFO32 -#define CFG_PCIFIFO 32 -#elif defined CONFIG_PCI_FIFO64 -#define CFG_PCIFIFO 64 -#elif defined CONFIG_PCI_FIFO128 -#define CFG_PCIFIFO 128 -#elif defined CONFIG_PCI_FIFO256 -#define CFG_PCIFIFO 256 -#else -#define CFG_PCIFIFO 8 -#endif - -#ifndef CFG_PCI_ENFIFO -#define CFG_PCI_ENFIFO 1 -#endif - - -#ifndef CONFIG_PCI_ARBITER_APB -#define CONFIG_PCI_ARBITER_APB 0 -#endif - -#ifndef CONFIG_PCI_ARBITER -#define CONFIG_PCI_ARBITER 0 -#endif - -#ifndef CONFIG_PCI_ARBITER_NREQ -#define CONFIG_PCI_ARBITER_NREQ 4 -#endif - -#ifndef CONFIG_PCI_TRACE -#define CONFIG_PCI_TRACE 0 -#endif - -#if defined CONFIG_PCI_TRACE512 -#define CFG_PCI_TRACEBUF 512 -#elif defined CONFIG_PCI_TRACE1024 -#define CFG_PCI_TRACEBUF 1024 -#elif defined CONFIG_PCI_TRACE2048 -#define CFG_PCI_TRACEBUF 2048 -#elif defined CONFIG_PCI_TRACE4096 -#define CFG_PCI_TRACEBUF 4096 -#else -#define CFG_PCI_TRACEBUF 256 -#endif - - -#ifndef CONFIG_SPW_ENABLE -#define CONFIG_SPW_ENABLE 0 -#endif - -#ifndef CONFIG_SPW_NUM -#define CONFIG_SPW_NUM 1 -#endif - -#if defined CONFIG_SPW_AHBFIFO4 -#define CONFIG_SPW_AHBFIFO 4 -#elif defined CONFIG_SPW_AHBFIFO8 -#define CONFIG_SPW_AHBFIFO 8 -#elif defined CONFIG_SPW_AHBFIFO16 -#define CONFIG_SPW_AHBFIFO 16 -#elif defined CONFIG_SPW_AHBFIFO32 -#define CONFIG_SPW_AHBFIFO 32 -#elif defined CONFIG_SPW_AHBFIFO64 -#define CONFIG_SPW_AHBFIFO 64 -#else -#define CONFIG_SPW_AHBFIFO 4 -#endif - -#if defined CONFIG_SPW_RXFIFO16 -#define CONFIG_SPW_RXFIFO 16 -#elif defined CONFIG_SPW_RXFIFO32 -#define CONFIG_SPW_RXFIFO 32 -#elif defined CONFIG_SPW_RXFIFO64 -#define CONFIG_SPW_RXFIFO 64 -#else -#define CONFIG_SPW_RXFIFO 16 -#endif - -#ifndef CONFIG_SPW_RMAP -#define CONFIG_SPW_RMAP 0 -#endif - -#if defined CONFIG_SPW_RMAPBUF2 -#define CONFIG_SPW_RMAPBUF 2 -#elif defined CONFIG_SPW_RMAPBUF4 -#define CONFIG_SPW_RMAPBUF 4 -#elif defined CONFIG_SPW_RMAPBUF6 -#define CONFIG_SPW_RMAPBUF 6 -#elif defined CONFIG_SPW_RMAPBUF8 -#define CONFIG_SPW_RMAPBUF 8 -#else -#define CONFIG_SPW_RMAPBUF 4 -#endif - -#ifndef CONFIG_SPW_RMAPCRC -#define CONFIG_SPW_RMAPCRC 0 -#endif - -#ifndef CONFIG_SPW_RXUNAL -#define CONFIG_SPW_RXUNAL 0 -#endif - -#ifndef CONFIG_SPW_NETLIST -#define CONFIG_SPW_NETLIST 0 -#endif - -#ifndef CONFIG_SPW_FT -#define CONFIG_SPW_FT 0 -#endif - -#if defined CONFIG_SPW_GRSPW1 -#define CONFIG_SPW_GRSPW 1 -#else -#define CONFIG_SPW_GRSPW 2 -#endif - -#ifndef CONFIG_SPW_DMACHAN -#define CONFIG_SPW_DMACHAN 1 -#endif - -#ifndef CONFIG_SPW_PORTS -#define CONFIG_SPW_PORTS 1 -#endif - -#if defined CONFIG_SPW_RX_SDR -#define CONFIG_SPW_INPUT 2 -#elif defined CONFIG_SPW_RX_DDR -#define CONFIG_SPW_INPUT 3 -#elif defined CONFIG_SPW_RX_XOR -#define CONFIG_SPW_INPUT 0 -#elif defined CONFIG_SPW_RX_AFLEX -#define CONFIG_SPW_INPUT 1 -#else -#define CONFIG_SPW_INPUT 2 -#endif - -#if defined CONFIG_SPW_TX_SDR -#define CONFIG_SPW_OUTPUT 0 -#elif defined CONFIG_SPW_TX_DDR -#define CONFIG_SPW_OUTPUT 1 -#elif defined CONFIG_SPW_TX_AFLEX -#define CONFIG_SPW_OUTPUT 2 -#else -#define CONFIG_SPW_OUTPUT 0 -#endif - -#ifndef CONFIG_SPW_RTSAME -#define CONFIG_SPW_RTSAME 0 -#endif -#ifndef CONFIG_UART1_ENABLE -#define CONFIG_UART1_ENABLE 0 -#endif - -#if defined CONFIG_UA1_FIFO1 -#define CFG_UA1_FIFO 1 -#elif defined CONFIG_UA1_FIFO2 -#define CFG_UA1_FIFO 2 -#elif defined CONFIG_UA1_FIFO4 -#define CFG_UA1_FIFO 4 -#elif defined CONFIG_UA1_FIFO8 -#define CFG_UA1_FIFO 8 -#elif defined CONFIG_UA1_FIFO16 -#define CFG_UA1_FIFO 16 -#elif defined CONFIG_UA1_FIFO32 -#define CFG_UA1_FIFO 32 -#else -#define CFG_UA1_FIFO 1 -#endif - -#ifndef CONFIG_UART2_ENABLE -#define CONFIG_UART2_ENABLE 0 -#endif - -#if defined CONFIG_UA2_FIFO1 -#define CFG_UA2_FIFO 1 -#elif defined CONFIG_UA2_FIFO2 -#define CFG_UA2_FIFO 2 -#elif defined CONFIG_UA2_FIFO4 -#define CFG_UA2_FIFO 4 -#elif defined CONFIG_UA2_FIFO8 -#define CFG_UA2_FIFO 8 -#elif defined CONFIG_UA2_FIFO16 -#define CFG_UA2_FIFO 16 -#elif defined CONFIG_UA2_FIFO32 -#define CFG_UA2_FIFO 32 -#else -#define CFG_UA2_FIFO 1 -#endif - -#ifndef CONFIG_IRQ3_ENABLE -#define CONFIG_IRQ3_ENABLE 0 -#endif -#ifndef CONFIG_IRQ3_NSEC -#define CONFIG_IRQ3_NSEC 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif - -#ifndef CONFIG_GPT_WDOGEN -#define CONFIG_GPT_WDOGEN 0 -#endif - -#ifndef CONFIG_GPT_WDOG -#define CONFIG_GPT_WDOG 0 -#endif - -#ifndef CONFIG_GRGPIO_ENABLE -#define CONFIG_GRGPIO_ENABLE 0 -#endif -#ifndef CONFIG_GRGPIO_IMASK -#define CONFIG_GRGPIO_IMASK 0000 -#endif -#ifndef CONFIG_GRGPIO_WIDTH -#define CONFIG_GRGPIO_WIDTH 1 -#endif - - -#ifndef CONFIG_DEBUG_UART -#define CONFIG_DEBUG_UART 0 -#endif diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/top_libero.prj.convert.8.6.bak b/designs/Projet-LeonLFR-A3P3K-Sheldon/top_libero.prj.convert.8.6.bak deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/top_libero.prj.convert.8.6.bak +++ /dev/null @@ -1,2766 +0,0 @@ -KEY LIBERO "8.6" -KEY CAPTURE "8.6.2.10" -KEY HDLTechnology "VHDL" -KEY VendorTechnology_Family "PROASIC3" -KEY VendorTechnology_Die "IT14X14M4LDP" -KEY VendorTechnology_Package "fg324" -KEY ProjectLocation "." -KEY SimulationType "VHDL" -KEY Vendor "Actel" -KEY ActiveRoot "top" -LIST REVISIONS -VALUE="Impl1",NUM=1 -CURREV=1 -ENDLIST -LIST LIBRARIES -grlib -synplify -techmap -spw -eth -opencores -gaisler -esa -fmf -spansion -gsi -lpp -lpp -cypress -work -ENDLIST -LIST LIBRARIES_grlib -ALIAS=grlib -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_synplify -ALIAS=synplify -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_techmap -ALIAS=techmap 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-VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gptimer.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbram.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbdpram.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mmb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpio.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbstat.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/logan.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbps2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom_package.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom.vhd,hdl" -VALUE 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"/C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/mctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE 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-VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtag.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/libjtagcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtagcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregs.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregsbd.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtagtst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/ethernet_mac.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/grethm.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/spacewire.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspwm.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/gr1553b/gr1553b_pkg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/memoryctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/mctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/utilities/conversions.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/utilities/gen_utils.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/flash.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/s25fl064a.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/m25p80.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/fifo/idt7202.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/functions.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/core_burst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/g880e18bt.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/RAM.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd,hdl" -VALUE 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"/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/ApbDriver.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Link_Reg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/APB_UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/BaudGen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE 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"/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/APB_USB.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/RWbuf.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/lpp_usb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/MinF_Cntr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Rocket_PCM_Encoder.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver_Multiplexor.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Word_Cntr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/components.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/package_utility.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/cy7c1354b.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/cy7c1380d.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/debug.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/grtestmod.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/cpu_disas.vhd,hdl" -VALUE "/config.vhd,hdl" -VALUE "/ahbrom.vhd,hdl" -VALUE "/leon3mp.vhd,hdl" -ENDFILELIST -ENDLIST -ENDLIST -ENDLIST diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/tsmc13.rc b/designs/Projet-LeonLFR-A3P3K-Sheldon/tsmc13.rc deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/tsmc13.rc +++ /dev/null @@ -1,8 +0,0 @@ -set_attribute lib_search_path {. /usr/local/synlibs/TSMG13F210D3_1.1/lib} -set_attribute library {"tsmg13f210t3_wc_108V_125C.lib" "/home/jiri/ibm/vhdl/temic/atc18/allmem.lib" } / -include leon3mp.rc -include atc18cond.rc -define_clock -period 5000 -name clock1 clk -synthesize -to_mapped -report_area -report_timing diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon/wave.do b/designs/Projet-LeonLFR-A3P3K-Sheldon/wave.do deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon/wave.do +++ /dev/null @@ -1,66 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /testbench/clk -add wave -noupdate -format Logic /testbench/rst -add wave -noupdate -format Literal -radix hexadecimal /testbench/address -add wave -noupdate -format Literal -radix hexadecimal /testbench/data -add wave -noupdate -format Literal /testbench/ramsn -add wave -noupdate -format Literal /testbench/ramoen -add wave -noupdate -format Literal /testbench/rwen -add wave -noupdate -format Literal /testbench/rwenx -add wave -noupdate -format Literal /testbench/romsn -add wave -noupdate -format Logic /testbench/iosn -add wave -noupdate -format Logic /testbench/oen -add wave -noupdate -format Logic /testbench/read -add wave -noupdate -format Logic /testbench/writen -add wave -noupdate -format Literal -radix hexadecimal /testbench/sa -add wave -noupdate -format Literal -radix hexadecimal /testbench/sd -add wave -noupdate -format Literal /testbench/sdcke -add wave -noupdate -format Literal /testbench/sdcsn -add wave -noupdate -format Logic /testbench/sdwen -add wave -noupdate -format Logic /testbench/sdrasn -add wave -noupdate -format Logic /testbench/sdcasn -add wave -noupdate -format Literal /testbench/sddqm -add wave -noupdate -format Logic /testbench/sdclk -add wave -noupdate -divider {CPU 1} -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ici -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ico -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dci -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dco -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/rfi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/rfo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/irqi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/irqo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dbgi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dbgo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/wpr -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dsur -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ir -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/cmem0/crami -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/cmem0/cramo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/m0/c0/dcache0/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/mg2/sr1/sd0/sdctrl/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/apbi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/apbo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbsi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbso -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbmi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbmo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/mg2/sr1/r -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {35452000 ps} 0} -configure wave -namecolwidth 212 -configure wave -valuecolwidth 117 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {689872312 ps} {690294089 ps} diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/CY7C1360C.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/CY7C1360C.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/CY7C1360C.vhd +++ /dev/null @@ -1,561 +0,0 @@ ---*************************************************************************************** --- --- File Name: CY7C1360C.vhd --- Version: 1.0 --- Date: Aug 8th, 2005 --- Model: BUS Functional --- Simulator: Modelsim --- --- --- Queries: MPD Applications --- Website: www.cypress.com/support --- Company: Cypress Semiconductor --- Part #: CY7C1360C (256K x 36) --- --- Description: Cypress 9Mb Synburst SRAM (Pipelined SCD) --- --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright(c) Cypress Semiconductor, 2004 --- All rights reserved --- --- Rev Date Changes --- --- ---------- --------------------------------------- --- 1.0 12/22/2004 - New Model --- - New Test Bench --- - New Test Vectors --- ---*************************************************************************************** - --- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz - -LIBRARY ieee,work; - USE ieee.std_logic_1164.all; - USE ieee.std_logic_unsigned.all; - Use IEEE.Std_Logic_Arith.all; - USE work.package_utility.all; - -entity CY7C1360C is - GENERIC ( - -- Constant Parameters - addr_bits : INTEGER := 18; -- This is external address - data_bits : INTEGER := 36; - - ---Clock timings for 250Mhz - Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise - - Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time - Cyp_tCH : TIME := 1.8 ns; -- Clock HIGH time - Cyp_tCL : TIME := 1.8 ns; -- Clock LOW time - - Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z - Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z - Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z - Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z - Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid - - Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise - Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise - Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise - Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise - Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise - Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up - - Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise - Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise - Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise - Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise - Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise - Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise - ---Clock timings for 200Mhz --- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise - --- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time --- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time --- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time - --- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z --- Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z --- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z --- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z --- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid - --- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise --- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise --- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise --- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise --- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise --- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up - --- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise --- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise --- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise --- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise --- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise --- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise - ---Clock timings for 166Mhz --- Cyp_tCO : TIME := 3.5 ns; -- Data Output Valid After CLK Rise - --- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time --- Cyp_tCH : TIME := 2.4 ns; -- Clock HIGH time --- Cyp_tCL : TIME := 2.4 ns; -- Clock LOW time - --- Cyp_tCHZ : TIME := 3.5 ns; -- Clock to High-Z --- Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z --- Cyp_tOEHZ: TIME := 3.5 ns; -- OE# HIGH to Output High-Z --- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z --- Cyp_tOEV : TIME := 3.5 ns; -- OE# LOW to Output Valid - --- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise --- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise --- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise --- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise --- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise --- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up - --- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise --- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise --- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise --- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise --- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise --- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise - - ); - PORT (iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0); - iCLK : IN STD_LOGIC); - -end CY7C1360C; -ARCHITECTURE CY7C1360C_arch OF CY7C1360C IS - - - - signal Read_reg_o1, Read_reg1 : STD_LOGIC; - signal WrN_reg1 : STD_LOGIC; - signal ADSP_N_o : STD_LOGIC; - signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC; - signal Sys_clk : STD_LOGIC := '0'; - signal test : STD_LOGIC; - signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0); - signal ce : STD_LOGIC; - signal Write_n : STD_LOGIC; - signal Read : STD_LOGIC; - - signal bwa_n1 : STD_LOGIC; - signal bwb_n1 : STD_LOGIC; - signal bwc_n1 : STD_LOGIC; - signal bwd_n1 : STD_LOGIC; - - signal latch_addr : STD_LOGIC; - signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0); - - signal OeN_HZ : STD_LOGIC; - signal OeN_DataValid : STD_LOGIC; - signal OeN_efct : STD_LOGIC; - - signal WR_HZ : STD_LOGIC; - signal WR_LZ : STD_LOGIC; - signal WR_efct : STD_LOGIC; - - signal CE_HZ : STD_LOGIC; - signal CE_LZ : STD_LOGIC; - signal Pipe_efct : STD_LOGIC; - - signal RD_HZ : STD_LOGIC; - signal RD_LZ : STD_LOGIC; - signal RD_efct : STD_LOGIC; - -begin - - ce <= ((not inCE1) and (iCE2) and (not inCE3)); - Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW)); - Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce)); - bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa)))); - bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb)))); - bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc)))); - bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd)))); - latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1))); - OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ; - WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ; - Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ; - RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ; - - - Process (Read_reg_o1) - begin - if (Read_reg_o1 = '0') then - RD_HZ <= '0' after Cyp_tCHZ; - RD_LZ <= '0' after Cyp_tCLZ; - elsif (Read_reg_o1 = '1') then - RD_HZ <= '1' after Cyp_tCHZ; - RD_LZ <= '1' after Cyp_tCLZ; - else - RD_HZ <= 'X' after Cyp_tCHZ; - RD_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - - - Process (pipe_reg1) - begin - if (pipe_reg1 = '1') then - CE_LZ <= '1' after Cyp_tCLZ; - elsif (pipe_reg1 = '0') then - CE_LZ <= '0' after Cyp_tCLZ; - else - CE_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - -- System Clock Decode - Process (iclk) - variable Sys_clk1 : std_logic := '0'; - begin - if (rising_edge (iclk)) then - Sys_clk1 := not iZZ; - end if; - if (falling_edge (iCLK)) then - Sys_clk1 := '0'; - end if; - Sys_clk <= Sys_clk1; - end process; - - - - Process (WrN_reg1) - begin - if (WrN_reg1 = '1') then - WR_HZ <= '1' after Cyp_tCHZ; - WR_LZ <= '1' after Cyp_tCLZ; - elsif (WrN_reg1 = '0') then - WR_HZ <= '0' after Cyp_tCHZ; - WR_LZ <= '0' after Cyp_tCLZ; - else - WR_HZ <= 'X' after Cyp_tCHZ; - WR_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - Process (inOE) - begin - if (inOE = '1') then - OeN_HZ <= '1' after Cyp_tOEHZ; - OeN_DataValid <= '1' after Cyp_tOEV; - elsif (inOE = '0') then - OeN_HZ <= '0' after Cyp_tOEHZ; - OeN_DataValid <= '0' after Cyp_tOEV; - else - OeN_HZ <= 'X' after Cyp_tOEHZ; - OeN_DataValid <= 'X' after Cyp_tOEV; - end if; - end process; - - process (ce_reg1, pipe_reg1) - begin - if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then - CE_HZ <= '0' after Cyp_tCHZ; - elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then - CE_HZ <= '1' after Cyp_tCHZ; - else - CE_HZ <= 'X' after Cyp_tCHZ; - end if; - end process; - - Process (Sys_clk) - TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0); - variable Read_reg_o : std_logic; - variable Read_reg : std_logic; - variable pcsr_write, ctlr_write : std_logic; - variable WrN_reg : std_logic; - variable latch_addr_old, latch_addr_current : std_logic; - variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0'); - variable bcount, first_addr : std_logic_vector (1 downto 0) := "00"; - variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic; - variable din : std_logic_vector (data_bits-1 downto 0); - variable first_addr_int : integer; - variable bank0 : memory_array; - variable bank1 : memory_array; - variable bank2 : memory_array; - variable bank3 : memory_array; - - begin - if rising_edge (Sys_clk) then - - if (Write_n = '0') then - Read_reg_o := '0'; - else - Read_reg_o := Read_reg; - end if; - - if (Write_n = '0') then - Read_reg := '0'; - else - Read_reg := Read; - end if; - Read_reg1 <= Read_reg; - Read_reg_o1 <= Read_reg_o; - - if (Read_reg = '1') then - pcsr_write := '0'; - ctlr_write := '0'; - end if; - - -- Write Register - - if (Read_reg_o = '1') then - WrN_reg := '1'; - else - WrN_reg := Write_n; - end if; - WrN_reg1 <= WrN_reg; - - latch_addr_old := latch_addr_current; - latch_addr_current := latch_addr; - - if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then - pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1; - - elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then - ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1; - end if; - -- ADDRess Register - if (latch_addr = '1') then - addr_reg_in := iADDR; - bcount := iADDR (1 downto 0); - first_addr := iADDR (1 downto 0); - end if; - addr_reg_in1 <= addr_reg_in; - -- ADSP_N Previous-Cycle Register - ADSP_N_o <= inADSP; - pcsr_write1 <= pcsr_write; - ctlr_write1 <= ctlr_write; - first_addr_int := CONV_INTEGER1 (first_addr); - -- Binary Counter and Logic - - if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst - bcount := (bcount + '1'); -- Advance Counter - - elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst - if ((first_addr_int REM 2) = 0) then - bcount := (bcount + '1'); -- Increment Counter - elsif ((first_addr_int REM 2) = 1) then - bcount := (bcount - '1'); -- Decrement Counter - end if; - end if; - - -- Read ADDRess - addr_reg_read := addr_reg_write; - addr_reg_read1 <= addr_reg_read; - - -- Write ADDRess - addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0); - addr_reg_write1 <= addr_reg_write; - -- Byte Write Register - bwa_reg := not bwa_n1; - bwb_reg := not bwb_n1; - bwc_reg := not bwc_n1; - bwd_reg := not bwd_n1; - - -- Enable Register - pipe_reg := ce_reg; - - -- Enable Register - if (latch_addr = '1') then - ce_reg := ce; - end if; - - pipe_reg1 <= pipe_reg; - ce_reg1 <= ce_reg; - - -- Input Register - if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and - ((pcsr_write = '1') or (ctlr_write = '1'))) then - din := ioDQ; - end if; - din1 <= din; - - -- Byte Write Driver - if ((ce_reg = '1') and (bwa_reg = '1')) then - bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0); - end if; - if ((ce_reg = '1') and (bwb_reg = '1')) then - bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9); - end if; - if ((ce_reg = '1') and (bwc_reg = '1')) then - bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18); - end if; - if ((ce_reg = '1') and (bwd_reg = '1')) then - bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27); - end if; - - -- Output Registers - - if ((Write_n = '0') or (pipe_reg = '0')) then - dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ; - elsif (Read_reg_o = '1') then - dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - end if; - - end if; - end process; - - -- Output Buffers - ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1')) - else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; - - - clk_check : PROCESS - VARIABLE clk_high, clk_low : TIME := 0 ns; - BEGIN - WAIT ON iClk; - IF iClk = '1' AND NOW >= Cyp_tCYC THEN - ASSERT (NOW - clk_low >= Cyp_tCH) - REPORT "Clk width low - tCH violation" - SEVERITY ERROR; - ASSERT (NOW - clk_high >= Cyp_tCYC) - REPORT "Clk period high - tCYC violation" - SEVERITY ERROR; - clk_high := NOW; - ELSIF iClk = '0' AND NOW /= 0 ns THEN - ASSERT (NOW - clk_high >= Cyp_tCL) - REPORT "Clk width high - tCL violation" - SEVERITY ERROR; - ASSERT (NOW - clk_low >= Cyp_tCYC) - REPORT "Clk period low - tCYC violation" - SEVERITY ERROR; - clk_low := NOW; - END IF; - END PROCESS; - - -- Check for Setup Timing Violation - setup_check : PROCESS - BEGIN - WAIT ON iClk; - IF iClk = '1' THEN - ASSERT (iAddr'LAST_EVENT >= Cyp_tAS) - REPORT "Addr - tAS violation" - SEVERITY ERROR; - ASSERT (inGW'LAST_EVENT >= Cyp_tWES) - REPORT "GW# - tWES violation" - SEVERITY ERROR; - ASSERT (inBWE'LAST_EVENT >= Cyp_tWES) - REPORT "BWE# - tWES violation" - SEVERITY ERROR; - ASSERT (inCe1'LAST_EVENT >= Cyp_tWES) - REPORT "CE1# - tWES violation" - SEVERITY ERROR; - ASSERT (iCe2'LAST_EVENT >= Cyp_tWES) - REPORT "CE2 - tWES violation" - SEVERITY ERROR; - ASSERT (inCe3'LAST_EVENT >= Cyp_tWES) - REPORT "CE3# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS) - REPORT "ADV# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS) - REPORT "ADSP# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS) - REPORT "ADSC# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwa'LAST_EVENT >= Cyp_tWES) - REPORT "BWa# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwb'LAST_EVENT >= Cyp_tWES) - REPORT "BWb# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwc'LAST_EVENT >= Cyp_tWES) - REPORT "BWc# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwd'LAST_EVENT >= Cyp_tWES) - REPORT "BWd# - tWES violation" - SEVERITY ERROR; - ASSERT (ioDq'LAST_EVENT >= Cyp_tDS) - REPORT "Dq - tDS violation" - SEVERITY ERROR; - END IF; - END PROCESS; - - -- Check for Hold Timing Violation - hold_check : PROCESS - BEGIN - WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH); - IF iClk'DELAYED(Cyp_tAH) = '1' THEN - ASSERT (iAddr'LAST_EVENT > Cyp_tAH) - REPORT "Addr - tAH violation" - SEVERITY ERROR; - END IF; - IF iClk'DELAYED(Cyp_tDH) = '1' THEN - ASSERT (ioDq'LAST_EVENT > Cyp_tDH) - REPORT "Dq - tDH violation" - SEVERITY ERROR; - END IF; - IF iClk'DELAYED(Cyp_tWEH) = '1' THEN - ASSERT (inCe1'LAST_EVENT > Cyp_tWEH) - REPORT "CE1# - tWEH violation" - SEVERITY ERROR; - ASSERT (iCe2'LAST_EVENT > Cyp_tWEH) - REPORT "CE2 - tWEH violation" - SEVERITY ERROR; - ASSERT (inCe3'LAST_EVENT > Cyp_tWEH) - REPORT "CE3 - tWEH violation" - SEVERITY ERROR; - ASSERT (inAdv'LAST_EVENT > Cyp_tWEH) - REPORT "ADV# - tWEH violation" - SEVERITY ERROR; - ASSERT (inADSP'LAST_EVENT > Cyp_tWEH) - REPORT "ADSP# - tWEH violation" - SEVERITY ERROR; - ASSERT (inADSC'LAST_EVENT > Cyp_tWEH) - REPORT "ADSC# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwa'LAST_EVENT > Cyp_tWEH) - REPORT "BWa# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwb'LAST_EVENT > Cyp_tWEH) - REPORT "BWb# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwc'LAST_EVENT > Cyp_tWEH) - REPORT "BWc# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwd'LAST_EVENT > Cyp_tWEH) - REPORT "BWd# - tWEH violation" - SEVERITY ERROR; - END IF; - - END PROCESS; -end CY7C1360C_arch; - - - - - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/SS_PL_SCD_X36_vect.txt b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/SS_PL_SCD_X36_vect.txt deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/SS_PL_SCD_X36_vect.txt +++ /dev/null @@ -1,114 +0,0 @@ -0_0_00000_0_X_XXXX_0_1_0_1_0_X_X_111111111_111111111_111111111_000000001_ZZZZZZZZZ_ZZZZZZZZZ_ZZZZZZZZZ_ZZZZZZZZZ -0_0_XXXXX_0_X_XXXX_1_X_X_X_1_0_X_111111111_111111111_111111111_000000010_ZZZZZZZZZ_ZZZZZZZZZ_ZZZZZZZZZ_ZZZZZZZZZ -0_0_XXXXX_0_X_XXXX_1_X_X_X_1_0_X_111111111_111111111_111111111_000000100_ZZZZZZZZZ_ZZZZZZZZZ_ZZZZZZZZZ_ZZZZZZZZZ -0_0_XXXXX_0_X_XXXX_1_X_X_X_1_0_X_111111111_111111111_111111111_000000111_ZZZZZZZZZ_ZZZZZZZZZ_ZZZZZZZZZ_ZZZZZZZZZ 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---**************************************************************** ---** MODEL : package_utility ** ---** COMPANY : Cypress Semiconductor ** ---** REVISION: 1.0 Created new package utility model ** ---** ** ---**************************************************************** -Library ieee,work; - Use ieee.std_logic_1164.all; - Use IEEE.Std_Logic_Arith.all; - Use IEEE.std_logic_TextIO.all; - --- Use work.package_timing.all; - -Library Std; - Use STD.TextIO.all; - -Package package_utility is - -FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR; -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER; - -End; -- package package_utility - -Package body package_utility is - - ------------------------------------------------------------------------------------------------- ---Converts string into std_logic_vector ------------------------------------------------------------------------------------------------- - -FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS - VARIABLE result : STD_LOGIC_VECTOR(S'RANGE); - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '0' THEN - result(i) := '0'; - ELSIF S(i) = '1' THEN - result(i) := '1'; - ELSIF S(i) = 'X' THEN - result(i) := 'X'; - ELSE - result(i) := 'Z'; - END IF; - END LOOP; - RETURN result; -END convert_string; - ------------------------------------------------------------------------------------------------- ---Converts std_logic_vector into integer ------------------------------------------------------------------------------------------------- - -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS - VARIABLE result : INTEGER := 0; - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '1' THEN - result := result + (2**i); - ELSIF S(i) = '0' THEN - result := result; - ELSE - result := 0; - END IF; - END LOOP; - RETURN result; - END CONV_INTEGER1; - - - - -end package_utility; - - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/readme.txt b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/readme.txt deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/readme.txt +++ /dev/null @@ -1,41 +0,0 @@ - $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ - ########################### READ ME ##################################### - $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ - -**************************************************************************************************** -Cypress Semiconductor -MPD Applications - -VHDL Behavioral (Bus-functional) Model ---------------------------------------------------------------- -Product Family: Std Sync Pipelined (SCD) Burst SRAM -Part: CY7C1360C -Density: 9M -Organization: 256K X 36 ---------------------------------------------------------------- - -Rev: 1.0 -Created: Aug 8th, 2005 -Copyright(c) Cypress Semiconductor, 2004 -All rights reserved -**************************************************************************************************** - -This is the VHDL model for the CY7C1360C device with the testbench and test vectors. - -Contact "mpd_apps@cypress.com" if you have any questions. - -This directory has 4 files, including this "readme". - -FILE LIST: ----------- - -1) CY7C1360C.vhd -> Main File // VHDL model for CY7C1360C - -2) SS_PL_SCD_X36_vect.txt -> Test Vectors File // used for testing the vhdl model - -3) tb.vhd -> Test bench File // used for testing the vhdl model - - - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/tb.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/tb.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/CY7C1360C/tb.vhd +++ /dev/null @@ -1,369 +0,0 @@ ---*************************************************************************************** --- --- File Name: tb.vhd --- Version: 1.0 --- Date: Aug 8th, 2005 --- Simulator: Modelsim --- --- --- Queries: MPD Applications --- Website: www.cypress.com/support --- Company: Cypress Semiconductor --- Part #: testbench for CY7C1360C (256K x 36) --- --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright(c) Cypress Semiconductor, 2004 --- All rights reserved --- --- Rev Date Changes --- --- ---------- --------------------------------------- --- 1.0 12/22/2004 - New Model --- - New Test Bench --- - New Test Vectors --- ---*************************************************************************************** - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE std.textio.ALL; -USE ieee.std_logic_textio.ALL; - - -ENTITY tb IS -END tb; - -architecture tb_arch of tb is - - CONSTANT addr_bits : INTEGER := 18; - CONSTANT data_bits : INTEGER := 36; - - CONSTANT tx01 : TIME := 2.2 ns; -- 0.0 ns to 1.8 ns - - - COMPONENT CY7C1360C - PORT (iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0); - iCLK : IN STD_LOGIC); - END COMPONENT; - --------------------------------------------------------------------------- --- Function: to_slv --- --- Description: Converts string to std_logic_vector --------------------------------------------------------------------------- -function to_slv(value : in string) return std_logic_vector is -variable outvec : std_logic_vector(value'length -1 downto 0); -variable i : integer; -variable temp : character; -begin - for i in 1 to value'length loop - - temp := value(i); - - case temp is - when '0' => outvec(i-1) := '0'; - when '1' => outvec(i-1) := '1'; - when 'X' => outvec(i-1) := 'X'; - when 'Z' => outvec(i-1) := 'Z'; - when others => - assert false report "Illegal characters" severity note; - - end case; - end loop; - return outvec; -end to_slv; - --------------------------------------------------------------------------- --- Function: to_slv_char --- --- Description: Converts character to std_logic_vector --------------------------------------------------------------------------- -function to_slv_char(value : in character) return std_logic is -variable outvec_char : std_logic; - -begin - - case value is - when '0' => outvec_char := '0'; - when '1' => outvec_char := '1'; - when 'X' => outvec_char := 'X'; - when 'Z' => outvec_char := 'Z'; - when others => - assert false report "Illegal characters" severity note; - - end case; - - return outvec_char; -end to_slv_char; --------------------------------------------------------------------------- - --------------------------------------------------------------------------- --- Function: to_string --- --- Description: Converts time to string --------------------------------------------------------------------------- -function to_string (value : in integer) return string is -variable L : line; - -begin - write(L, value, RIGHT, 10); - return L.all; -end to_string; --------------------------------------------------------------------------- - - - FOR ALL: CY7C1360C USE ENTITY WORK.CY7C1360C(CY7C1360C_arch); - - SIGNAL DQ : STD_LOGIC_VECTOR((data_bits-1) DOWNTO 0); - SIGNAL Addr : STD_LOGIC_VECTOR((addr_bits-1) DOWNTO 0) := (OTHERS => '0'); - SIGNAL ZZ, clk : STD_LOGIC := '0'; - SIGNAL Mode : STD_LOGIC := '0'; - SIGNAL BWE_n : STD_LOGIC := '1'; - SIGNAL BWd_n : STD_LOGIC := '1'; - SIGNAL BWc_n : STD_LOGIC := '1'; - SIGNAL BWb_n : STD_LOGIC := '1'; - SIGNAL BWa_n : STD_LOGIC := '1'; - SIGNAL GW_n : STD_LOGIC := '1'; - signal CE1_n : STD_LOGIC := '1'; - signal CE2 : STD_LOGIC := '0'; - SIGNAL CE3_n : STD_LOGIC := '1'; - signal ADSP_n : STD_LOGIC := '1'; - signal ADSC_n : STD_LOGIC := '1'; - signal ADV_n : STD_LOGIC := '1'; - signal OE_n : STD_LOGIC := '1'; - signal count : integer := 0; - signal chkout : std_logic := '0'; - signal testin_tmp_slv : std_logic_vector ((data_bits-1) downto 0) := (others => '0'); - signal strb : std_logic := '0'; - signal temp : std_logic := '1'; - signal D : STD_LOGIC_VECTOR((data_bits-1) DOWNTO 0) := (OTHERS => '0'); - signal read_write : std_logic; - signal trigger : std_logic := '0'; -begin - - - - - -- Unit Under Test port map - UUT : CY7C1360C - PORT MAP (ioDq => Dq, - iAddr => Addr, - iClk => Clk, - iMode => Mode, - inAdv => Adv_n, - inBwa => Bwa_n, - inBwb => Bwb_n, - inBwc => Bwc_n, - inBwd => Bwd_n, - inOE => OE_n, - inCE1 => CE1_n, - inCE3 => CE3_n, - iCE2 => CE2, - inADSP => ADSP_n, - inADSC => ADSC_n, - inGW => GW_n, - inBWE => BWE_n, - iZZ => Zz - ); - -Process - begin - trigger <= '1' after 4 ns; - wait; -end process; - - with trigger select - strb <= not strb after 4.4 ns when '1', - '0' when others; --clock - -process(strb) - begin - clk <= strb after tx01; - end process; - -process - -variable l : line; -variable A_tmp : string (5 downto 1); -variable zz_tmp : character; -variable mode_tmp : character; -variable gw_tmp : character; -variable bwe_tmp : character; -variable bw_tmp : string (4 downto 1); -variable ce1_n_tmp : character; -variable ce2_tmp : character; -variable ce3_n_tmp : character; -variable adsp_n_tmp : character; -variable adsc_n_tmp : character; -variable adv_n_tmp : character; -variable oeb_tmp : character; -variable testout_tmp1, testout_tmp2, testout_tmp3, testout_tmp4 : string (9 downto 1); -variable testin_tmp1, testin_tmp2, testin_tmp3, testin_tmp4 : string (9 downto 1); -variable A_tmp_slv : STD_LOGIC_VECTOR (4 downto 0); -variable zz_tmp_slv : STD_LOGIC; -variable mode_tmp_slv : STD_LOGIC; -variable gw_tmp_slv : STD_LOGIC; -variable bwe_tmp_slv : STD_LOGIC; -variable bw_tmp_slv : STD_LOGIC_VECTOR (3 downto 0); -variable ce1_n_tmp_slv : STD_LOGIC; -variable ce2_tmp_slv : STD_LOGIC; -variable ce3_n_tmp_slv : STD_LOGIC; -variable adsp_n_tmp_slv : STD_LOGIC; -variable adsc_n_tmp_slv : STD_LOGIC; -variable adv_n_tmp_slv : STD_LOGIC; -variable oeb_tmp_slv : STD_LOGIC; -variable testout_tmp1_slv,testout_tmp2_slv,testout_tmp3_slv,testout_tmp4_slv : STD_LOGIC_VECTOR (8 downto 0); -variable US: character; -variable linecount: integer; -FILE test_vectors : text is in "SS_PL_SCD_X36_vect.txt"; -- preload file - - -begin - while not endfile(test_vectors) loop - assert false report "Line no" &to_string(count) severity note; - wait until strb = '1'; - readline (test_vectors,l); - read(l,zz_tmp); - read(l,US); - read(l,mode_tmp); - read(l,US); - read(l,A_tmp); - read(l,US); - read(l,gw_tmp); - read(l,US); - read(l,bwe_tmp); - read(l,US); - read(l,bw_tmp); - read(l,US); - read(l,ce1_n_tmp); - read(l,US); - read(l,ce2_tmp); - read(l,US); - read(l,ce3_n_tmp); - read(l,US); - read(l,ADSP_n_tmp); - read(l,US); - read(l,ADSC_n_tmp); - read(l,US); - read(l,ADV_n_tmp); - read(l,US); - read(l,oeb_tmp); - read(l,US); - read(l,testout_tmp1); - read(l,US); - read(l,testout_tmp2); - read(l,US); - read(l,testout_tmp3); - read(l,US); - read(l,testout_tmp4); - read(l,US); - read(l,testin_tmp1); - read(l,US); - read(l,testin_tmp2); - read(l,US); - read(l,testin_tmp3); - read(l,US); - read(l,testin_tmp4); - - - A_tmp_slv (4 downto 0) := to_slv(A_tmp); - zz_tmp_slv := to_slv_char(zz_tmp); - mode_tmp_slv := to_slv_char(mode_tmp); - gw_tmp_slv := to_slv_char(gw_tmp); - bwe_tmp_slv := to_slv_char(bwe_tmp); - bw_tmp_slv (3 downto 0) := to_slv(bw_tmp); - ce1_n_tmp_slv := to_slv_char(ce1_n_tmp); - ce2_tmp_slv := to_slv_char(ce2_tmp); - ce3_n_tmp_slv := to_slv_char(ce3_n_tmp); - ADSP_n_tmp_slv := to_slv_char(ADSP_n_tmp); - ADSC_n_tmp_slv := to_slv_char(ADSC_n_tmp); - ADV_n_tmp_slv := to_slv_char(ADV_n_tmp); - oeb_tmp_slv := to_slv_char(oeb_tmp); - testin_tmp_slv (8 downto 0) <= to_slv(testin_tmp4); - testout_tmp1_slv (8 downto 0) := to_slv(testout_tmp1); - testin_tmp_slv (17 downto 9) <= to_slv(testin_tmp3); - testout_tmp2_slv (8 downto 0) := to_slv(testout_tmp2); - testin_tmp_slv (26 downto 18) <= to_slv(testin_tmp2); - testout_tmp3_slv (8 downto 0) := to_slv(testout_tmp3); - testin_tmp_slv (35 downto 27) <= to_slv(testin_tmp1); - testout_tmp4_slv (8 downto 0) := to_slv(testout_tmp4); - - - Addr <= "0000000000000" & A_tmp_slv; - Mode <= mode_tmp_slv; - Adv_n <= Adv_n_tmp_slv; - Bwa_n <= Bw_tmp_slv (0); - Bwb_n <= Bw_tmp_slv (1); - Bwc_n <= Bw_tmp_slv (2); - Bwd_n <= Bw_tmp_slv (3); - OE_n <= OEb_tmp_slv; - CE1_n <= CE1_n_tmp_slv; - CE3_n <= CE3_n_tmp_slv; - CE2 <= CE2_tmp_slv; - ADSP_n <= ADSP_n_tmp_slv; - ADSC_n <= ADSC_n_tmp_slv; - GW_n <= GW_tmp_slv; - BWE_n <= BWE_tmp_slv; - ZZ <= zz_tmp_slv; - - D (35 downto 27) <= testout_tmp1_slv; - D (26 downto 18) <= testout_tmp2_slv; - D (17 downto 9) <= testout_tmp3_slv; - D (8 downto 0) <= testout_tmp4_slv; - - count <= count +1; - - - end loop; - chkout <= '1'; - wait; -end process; - - -read_write <= '0' when D = "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" else '1'; --1 means write -DQ <= D when read_write = '1' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; - -Process (clk) -begin - if rising_edge (clk) then - if (chkout = '0') then - if (D /= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ") then - assert false report "Write Cycle" severity note; - else - if (DQ(35 downto 0) = testin_tmp_slv(35 downto 0)) then - assert false report "OK" severity note; - else - assert false report "ERROR" severity note; - end if; - end if; - else - assert false report "TEST COMPLETE" severity note; - end if; - end if; -end process; - - -end tb_arch; - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Makefile b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Makefile deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -#GRLIB=../.. -TOP=leon3mp -BOARD=Projet-LeonLFR-A3P3K-Sheldon -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd Top_Data_Acquisition.vhd -VHDLSIMFILES=testbench.vhd TB_Data_Acquisition.vhd -SIMTOP=testbench -SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/Projet-LeonLFR-A3P3K-Sheldon.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3 -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 - -FILESKIP = i2cmst.vhd - -#TECHLIBS = unisim -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -my-clean: clean - -rm -rf *~ - -################## project specific targets ########################## - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd +++ /dev/null @@ -1,348 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -------------------------------------------------------------------------------- - -ENTITY TB_Data_Acquisition IS - -END TB_Data_Acquisition; - -------------------------------------------------------------------------------- - -ARCHITECTURE tb OF TB_Data_Acquisition IS - - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - --COMPONENT Top_Data_Acquisition - -- GENERIC ( - -- hindex : INTEGER; - -- nb_burst_available_size : INTEGER := 11; - -- nb_snapshot_param_size : INTEGER := 11; - -- delta_snapshot_size : INTEGER := 16; - -- delta_f2_f0_size : INTEGER := 10; - -- delta_f2_f1_size : INTEGER := 10; - -- tech : integer); - -- PORT ( - -- cnv_run : IN STD_LOGIC; - -- cnv : OUT STD_LOGIC; - -- sck : OUT STD_LOGIC; - -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- cnv_clk : IN STD_LOGIC; - -- cnv_rstn : IN STD_LOGIC; - -- clk : IN STD_LOGIC; - -- rstn : IN STD_LOGIC; - -- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- AHB_Master_In : IN AHB_Mst_In_Type; - -- AHB_Master_Out : OUT AHB_Mst_Out_Type; - -- coarse_time_0 : IN STD_LOGIC; - -- data_shaping_SP0 : IN STD_LOGIC; - -- data_shaping_SP1 : IN STD_LOGIC; - -- data_shaping_R0 : IN STD_LOGIC; - -- data_shaping_R1 : IN STD_LOGIC; - -- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - -- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - -- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - -- enable_f0 : IN STD_LOGIC; - -- enable_f1 : IN STD_LOGIC; - -- enable_f2 : IN STD_LOGIC; - -- enable_f3 : IN STD_LOGIC; - -- burst_f0 : IN STD_LOGIC; - -- burst_f1 : IN STD_LOGIC; - -- burst_f2 : IN STD_LOGIC; - -- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - -- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - -- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - -- component ports - SIGNAL cnv_rstn : STD_LOGIC; - SIGNAL cnv : STD_LOGIC; - SIGNAL rstn : STD_LOGIC; - SIGNAL sck : STD_LOGIC; - SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL run_cnv : STD_LOGIC; - - - -- clock - signal Clk : STD_LOGIC := '1'; - SIGNAL cnv_clk : STD_LOGIC := '1'; - - ----------------------------------------------------------------------------- - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - ----------------------------------------------------------------------------- - CONSTANT nb_burst_available_size : INTEGER := 11; - CONSTANT nb_snapshot_param_size : INTEGER := 11; - CONSTANT delta_snapshot_size : INTEGER := 16; - CONSTANT delta_f2_f0_size : INTEGER := 10; - CONSTANT delta_f2_f1_size : INTEGER := 10; - - SIGNAL AHB_Master_In : AHB_Mst_In_Type; - SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; - - SIGNAL coarse_time_0 : STD_LOGIC; - SIGNAL coarse_time_0_t : STD_LOGIC := '0'; - SIGNAL coarse_time_0_t2 : STD_LOGIC := '0'; - - SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - SIGNAL enable_f0 : STD_LOGIC; - SIGNAL enable_f1 : STD_LOGIC; - SIGNAL enable_f2 : STD_LOGIC; - SIGNAL enable_f3 : STD_LOGIC; - - SIGNAL burst_f0 : STD_LOGIC; - SIGNAL burst_f1 : STD_LOGIC; - SIGNAL burst_f2 : STD_LOGIC; - - SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - - SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - - SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); - - - SIGNAL data_shaping_SP0 : STD_LOGIC; - SIGNAL data_shaping_SP1 : STD_LOGIC; - SIGNAL data_shaping_R0 : STD_LOGIC; - SIGNAL data_shaping_R1 : STD_LOGIC; -BEGIN -- tb - - MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(7)); - - - -- clock generation - Clk <= not Clk after 20 ns; -- 25 Mhz - cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz - - -- waveform generation - WaveGen_Proc: process - begin - -- insert signal assignments here - wait until Clk = '1'; - rstn <= '0'; - cnv_rstn <= '0'; - run_cnv <= '0'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - rstn <= '1'; - cnv_rstn <= '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - run_cnv <= '1'; - wait; - - end process WaveGen_Proc; - - ----------------------------------------------------------------------------- - - Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip - GENERIC MAP ( - hindex => 2, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size =>16, - delta_f2_f0_size =>10, - delta_f2_f1_size =>10, - tech => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo, - cnv_clk => cnv_clk, - cnv_rstn => cnv_rstn, - clk => clk, - rstn => rstn, - sample_f0_wen => sample_f0_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wen => sample_f1_wen, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wen => sample_f2_wen, - sample_f2_wdata => sample_f2_wdata, - sample_f3_wen => sample_f3_wen, - sample_f3_wdata => sample_f3_wdata, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - coarse_time_0 => coarse_time_0, - data_shaping_SP0 => data_shaping_SP0, - data_shaping_SP1 => data_shaping_SP1, - data_shaping_R0 => data_shaping_R0, - data_shaping_R1 => data_shaping_R1, - delta_snapshot => delta_snapshot, - delta_f2_f1 => delta_f2_f1, - delta_f2_f0 => delta_f2_f0, - enable_f0 => enable_f0, - enable_f1 => enable_f1, - enable_f2 => enable_f2, - enable_f3 => enable_f3, - burst_f0 => burst_f0, - burst_f1 => burst_f1, - burst_f2 => burst_f2, - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - status_new_err => status_new_err, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3); - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - enable_f0 <= '0'; - enable_f1 <= '0'; - enable_f2 <= '0'; - enable_f3 <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - enable_f0 <= '1'; --TODO test - enable_f1 <= '1'; - enable_f2 <= '1'; - enable_f3 <= '1'; - END IF; - END PROCESS; - - burst_f0 <= '0'; --TODO test - burst_f1 <= '0'; --TODO test - burst_f2 <= '0'; - - data_shaping_SP0 <= '0'; - data_shaping_SP1 <= '0'; - data_shaping_R0 <= '1'; - data_shaping_R1 <= '1'; - - delta_snapshot <= "0000000000000001"; - --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 - --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2 - --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4 - - -- A redefinir car ca ne tombe pas correctement ... ??? - nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34 - nb_snapshot_param <= "00000001111"; -- x+1 = 16 - delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2 - delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4 - - addr_data_f0 <= "00000000000000000000000000000000"; - addr_data_f1 <= "00010000000000000000000000000000"; - addr_data_f2 <= "00100000000000000000000000000000"; - addr_data_f3 <= "00110000000000000000000000000000"; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - status_full_ack <= (OTHERS => '0'); - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - status_full_ack <= status_full; - END IF; - END PROCESS; - - - coarse_time_0_t <= not coarse_time_0_t after 50 ms; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - coarse_time_0_t2 <= '0'; - coarse_time_0 <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - coarse_time_0_t2 <= coarse_time_0_t; - coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2); - END IF; - END PROCESS; - - - AHB_Master_In.HGRANT(2) <= '1'; - AHB_Master_In.HREADY <= '1'; - - - AHB_Master_In.HRESP <= HRESP_OKAY; - - -END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd +++ /dev/null @@ -1,498 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -ENTITY Top_Data_Acquisition IS - GENERIC( - hindex : INTEGER := 2; - nb_burst_available_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_snapshot_size : INTEGER := 16; - delta_f2_f0_size : INTEGER := 10; - delta_f2_f1_size : INTEGER := 10; - tech : INTEGER := 0 - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - -- - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - -- - sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - - coarse_time_0 : IN STD_LOGIC; - - --config - data_shaping_SP0 : IN STD_LOGIC; - data_shaping_SP1 : IN STD_LOGIC; - data_shaping_R0 : IN STD_LOGIC; - data_shaping_R1 : IN STD_LOGIC; - - delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - enable_f0 : IN STD_LOGIC; - enable_f1 : IN STD_LOGIC; - enable_f2 : IN STD_LOGIC; - enable_f3 : IN STD_LOGIC; - - burst_f0 : IN STD_LOGIC; - burst_f1 : IN STD_LOGIC; - burst_f2 : IN STD_LOGIC; - - nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma - - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END Top_Data_Acquisition; - -ARCHITECTURE tb OF Top_Data_Acquisition IS - - COMPONENT Downsampling - GENERIC ( - ChanelCount : INTEGER; - SampleSize : INTEGER; - DivideParam : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); - sample_out_val : OUT STD_LOGIC; - sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); - END COMPONENT; - - ----------------------------------------------------------------------------- - CONSTANT ChanelCount : INTEGER := 8; - CONSTANT ncycle_cnv_high : INTEGER := 79; - CONSTANT ncycle_cnv : INTEGER := 500; - - ----------------------------------------------------------------------------- - SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL sample_val_delay : STD_LOGIC; - ----------------------------------------------------------------------------- - CONSTANT Coef_SZ : INTEGER := 9; - CONSTANT CoefCntPerCel : INTEGER := 6; - CONSTANT CoefPerCel : INTEGER := 5; - CONSTANT Cels_count : INTEGER := 5; - - SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_val : STD_LOGIC; - SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_data_shaping_out_val : STD_LOGIC; - SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; - SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - ----------------------------------------------------------------------------- - - SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -BEGIN - - -- component instantiation - ----------------------------------------------------------------------------- - DIGITAL_acquisition : AD7688_drvr - GENERIC MAP ( - ChanelCount => ChanelCount, - ncycle_cnv_high => ncycle_cnv_high, - ncycle_cnv => ncycle_cnv) - PORT MAP ( - cnv_clk => cnv_clk, -- - cnv_rstn => cnv_rstn, -- - cnv_run => cnv_run, -- - cnv => cnv, -- - clk => clk, -- - rstn => rstn, -- - sck => sck, -- - sdo => sdo(ChanelCount-1 DOWNTO 0), -- - sample => sample, - sample_val => sample_val); - - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_val_delay <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_val_delay <= sample_val; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE - SampleLoop : FOR j IN 0 TO 15 GENERATE - sample_filter_in(i, j) <= sample(i)(j); - END GENERATE; - - sample_filter_in(i, 16) <= sample(i)(15); - sample_filter_in(i, 17) <= sample(i)(15); - END GENERATE; - - coefs_v2 <= CoefsInitValCst_v2; - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => 0, - Mem_use => use_CEL, -- use_RAM - Sample_SZ => 18, - Coef_SZ => Coef_SZ, - Coef_Nb => 25, - Coef_sel_SZ => 5, - Cels_count => Cels_count, - ChanelsCount => ChanelCount) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => 7, - coefs => coefs_v2, - sample_in_val => sample_val_delay, - sample_in => sample_filter_in, - sample_out_val => sample_filter_v2_out_val, - sample_out => sample_filter_v2_out); - - ----------------------------------------------------------------------------- - -- DATA_SHAPING - ----------------------------------------------------------------------------- - all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE - sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); - sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); - sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); - END GENERATE all_data_shaping_in_loop; - - sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; - sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_data_shaping_out_val <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - sample_data_shaping_out_val <= sample_filter_v2_out_val; - END IF; - END PROCESS; - - SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - sample_data_shaping_out(0,j) <= '0'; - sample_data_shaping_out(1,j) <= '0'; - sample_data_shaping_out(2,j) <= '0'; - sample_data_shaping_out(3,j) <= '0'; - sample_data_shaping_out(4,j) <= '0'; - sample_data_shaping_out(5,j) <= '0'; - sample_data_shaping_out(6,j) <= '0'; - sample_data_shaping_out(7,j) <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); - IF data_shaping_SP0 = '1' THEN - sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); - ELSE - sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); - END IF; - IF data_shaping_SP1 = '1' THEN - sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); - ELSE - sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); - END IF; - sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); - sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); - sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); - sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); - END IF; - END PROCESS; - END GENERATE; - - sample_filter_v2_out_val_s <= sample_data_shaping_out_val; - ChanelLoopOut : FOR i IN 0 TO 7 GENERATE - SampleLoopOut : FOR j IN 0 TO 15 GENERATE - sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); - END GENERATE; - END GENERATE; - ----------------------------------------------------------------------------- - -- F0 -- @24.576 kHz - ----------------------------------------------------------------------------- - Downsampling_f0 : Downsampling - GENERIC MAP ( - ChanelCount => 8, - SampleSize => 16, - DivideParam => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_filter_v2_out_val_s, - sample_in => sample_filter_v2_out_s, - sample_out_val => sample_f0_val, - sample_out => sample_f0); - - all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_wdata_s(I) <= sample_f0(0, I); -- V - sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 - sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 - sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 - sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 - sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 - END GENERATE all_bit_sample_f0; - - sample_f0_wen <= NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val); - - ----------------------------------------------------------------------------- - -- F1 -- @4096 Hz - ----------------------------------------------------------------------------- - Downsampling_f1 : Downsampling - GENERIC MAP ( - ChanelCount => 8, - SampleSize => 16, - DivideParam => 6) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f1_val, - sample_out => sample_f1); - - all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_wdata_s(I) <= sample_f1(0, I); -- V - sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 - sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 - sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 - sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 - sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 - END GENERATE all_bit_sample_f1; - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); - - ----------------------------------------------------------------------------- - -- F2 -- @256 Hz - ----------------------------------------------------------------------------- - all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_s(0, I) <= sample_f0(0, I); -- V - sample_f0_s(1, I) <= sample_f0(1, I); -- E1 - sample_f0_s(2, I) <= sample_f0(2, I); -- E2 - sample_f0_s(3, I) <= sample_f0(5, I); -- B1 - sample_f0_s(4, I) <= sample_f0(6, I); -- B2 - sample_f0_s(5, I) <= sample_f0(7, I); -- B3 - END GENERATE all_bit_sample_f0_s; - - Downsampling_f2 : Downsampling - GENERIC MAP ( - ChanelCount => 6, - SampleSize => 16, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0_s, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - sample_f2_wen <= NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val); - - all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f2_wdata_s(I) <= sample_f2(0, I); - sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); - sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); - sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); - sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); - sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); - END GENERATE all_bit_sample_f2; - - ----------------------------------------------------------------------------- - -- F3 -- @16 Hz - ----------------------------------------------------------------------------- - all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_s(0, I) <= sample_f1(0, I); -- V - sample_f1_s(1, I) <= sample_f1(1, I); -- E1 - sample_f1_s(2, I) <= sample_f1(2, I); -- E2 - sample_f1_s(3, I) <= sample_f1(5, I); -- B1 - sample_f1_s(4, I) <= sample_f1(6, I); -- B2 - sample_f1_s(5, I) <= sample_f1(7, I); -- B3 - END GENERATE all_bit_sample_f1_s; - - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => 6, - SampleSize => 16, - DivideParam => 256) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f1_val , - sample_in => sample_f1_s, - sample_out_val => sample_f3_val, - sample_out => sample_f3); - - sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); - - all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f3_wdata_s(I) <= sample_f3(0, I); - sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); - sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); - sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); - sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); - sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); - END GENERATE all_bit_sample_f3; - - lpp_waveform_1 : lpp_waveform - GENERIC MAP ( - hindex => hindex, - tech => tech, - data_size => 160, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size => delta_snapshot_size, - delta_f2_f0_size => delta_f2_f0_size, - delta_f2_f1_size => delta_f2_f1_size) - PORT MAP ( - clk => clk, - rstn => rstn, - - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - - coarse_time_0 => coarse_time_0, -- IN - delta_snapshot => delta_snapshot, -- IN - delta_f2_f1 => delta_f2_f1, -- IN - delta_f2_f0 => delta_f2_f0, -- IN - enable_f0 => enable_f0, -- IN - enable_f1 => enable_f1, -- IN - enable_f2 => enable_f2, -- IN - enable_f3 => enable_f3, -- IN - burst_f0 => burst_f0, -- IN - burst_f1 => burst_f1, -- IN - burst_f2 => burst_f2, -- IN - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, -- IN - status_full_err => status_full_err, - status_new_err => status_new_err, - - addr_data_f0 => addr_data_f0, -- IN - addr_data_f1 => addr_data_f1, -- IN - addr_data_f2 => addr_data_f2, -- IN - addr_data_f3 => addr_data_f3, -- IN - - data_f0_in => data_f0_in_valid, - data_f1_in => data_f1_in_valid, - data_f2_in => data_f2_in_valid, - data_f3_in => data_f3_in_valid, - data_f0_in_valid => sample_f0_val, - data_f1_in_valid => sample_f1_val, - data_f2_in_valid => sample_f2_val, - data_f3_in_valid => sample_f3_val); - - data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; - data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; - data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; - data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; - - sample_f0_wdata <= sample_f0_wdata_s; - sample_f1_wdata <= sample_f1_wdata_s; - sample_f2_wdata <= sample_f2_wdata_s; - sample_f3_wdata <= sample_f3_wdata_s; - -END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/config.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/config.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/config.vhd +++ /dev/null @@ -1,218 +0,0 @@ - - - - ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------- - - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -PACKAGE config IS --- Technology and synthesis options - CONSTANT CFG_FABTECH : INTEGER := inferred; - CONSTANT CFG_MEMTECH : INTEGER := inferred; --- constant CFG_FABTECH : integer := apa3; --inferred; --- constant CFG_MEMTECH : integer := apa3; --inferred; - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT CFG_NOASYNC : INTEGER := 0; - CONSTANT CFG_SCAN : INTEGER := 0; --- Clock generator - CONSTANT CFG_CLKTECH : INTEGER := inferred; - CONSTANT CFG_CLKMUL : INTEGER := 2; - CONSTANT CFG_CLKDIV : INTEGER := 2; - CONSTANT CFG_OCLKDIV : INTEGER := 1; - CONSTANT CFG_OCLKBDIV : INTEGER := 0; - CONSTANT CFG_OCLKCDIV : INTEGER := 0; - CONSTANT CFG_PCIDLL : INTEGER := 0; - CONSTANT CFG_PCISYSCLK : INTEGER := 0; - CONSTANT CFG_CLK_NOFB : INTEGER := 0; --- LEON3 processor core - CONSTANT CFG_LEON3 : INTEGER := 1; - CONSTANT CFG_NCPU : INTEGER := (1); - CONSTANT CFG_NWIN : INTEGER := (8); - CONSTANT CFG_V8 : INTEGER := 0 + 4*0; - CONSTANT CFG_MAC : INTEGER := 0; - CONSTANT CFG_BP : INTEGER := 0; - CONSTANT CFG_SVT : INTEGER := 0; - CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; - CONSTANT CFG_LDDEL : INTEGER := (1); - CONSTANT CFG_NOTAG : INTEGER := 0; - CONSTANT CFG_NWP : INTEGER := (0); - CONSTANT CFG_PWD : INTEGER := 0*2; - CONSTANT CFG_FPU : INTEGER := 0 + 16*0 + 32*0; - CONSTANT CFG_GRFPUSH : INTEGER := 0; - CONSTANT CFG_ICEN : INTEGER := 1; - CONSTANT CFG_ISETS : INTEGER := 1; - CONSTANT CFG_ISETSZ : INTEGER := 4; - CONSTANT CFG_ILINE : INTEGER := 8; - CONSTANT CFG_IREPL : INTEGER := 0; - CONSTANT CFG_ILOCK : INTEGER := 0; - CONSTANT CFG_ILRAMEN : INTEGER := 0; - CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; - CONSTANT CFG_ILRAMSZ : INTEGER := 1; - CONSTANT CFG_DCEN : INTEGER := 1; - CONSTANT CFG_DSETS : INTEGER := 1; - CONSTANT CFG_DSETSZ : INTEGER := 4; - CONSTANT CFG_DLINE : INTEGER := 8; - CONSTANT CFG_DREPL : INTEGER := 0; - CONSTANT CFG_DLOCK : INTEGER := 0; - CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; - CONSTANT CFG_DFIXED : INTEGER := 16#0#; - CONSTANT CFG_DLRAMEN : INTEGER := 0; - CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; - CONSTANT CFG_DLRAMSZ : INTEGER := 1; - CONSTANT CFG_MMUEN : INTEGER := 1; - CONSTANT CFG_ITLBNUM : INTEGER := 8; - CONSTANT CFG_DTLBNUM : INTEGER := 8; - CONSTANT CFG_TLB_TYPE : INTEGER := 0 + 1*2; - CONSTANT CFG_TLB_REP : INTEGER := 1; - CONSTANT CFG_MMU_PAGE : INTEGER := 0; - CONSTANT CFG_DSU : INTEGER := 0; - CONSTANT CFG_ITBSZ : INTEGER := 0; - CONSTANT CFG_ATBSZ : INTEGER := 0; - CONSTANT CFG_LEON3FT_EN : INTEGER := 0; - CONSTANT CFG_IUFT_EN : INTEGER := 0; - CONSTANT CFG_FPUFT_EN : INTEGER := 0; - CONSTANT CFG_RF_ERRINJ : INTEGER := 0; - CONSTANT CFG_CACHE_FT_EN : INTEGER := 0; - CONSTANT CFG_CACHE_ERRINJ : INTEGER := 0; - CONSTANT CFG_LEON3_NETLIST : INTEGER := 0; - CONSTANT CFG_DISAS : INTEGER := 0 + 0; - CONSTANT CFG_PCLOW : INTEGER := 2; --- AMBA settings - CONSTANT CFG_DEFMST : INTEGER := (0); - CONSTANT CFG_RROBIN : INTEGER := 1; - CONSTANT CFG_SPLIT : INTEGER := 0; - CONSTANT CFG_FPNPEN : INTEGER := 0; - CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; - CONSTANT CFG_APBADDR : INTEGER := 16#800#; - CONSTANT CFG_AHB_MON : INTEGER := 0; - CONSTANT CFG_AHB_MONERR : INTEGER := 0; - CONSTANT CFG_AHB_MONWAR : INTEGER := 0; - CONSTANT CFG_AHB_DTRACE : INTEGER := 0; --- DSU UART - CONSTANT CFG_AHB_UART : INTEGER := 1; --- JTAG based DSU interface - CONSTANT CFG_AHB_JTAG : INTEGER := 0; --- Ethernet DSU - CONSTANT CFG_DSU_ETH : INTEGER := 0 + 0 + 0; - CONSTANT CFG_ETH_BUF : INTEGER := 1; - CONSTANT CFG_ETH_IPM : INTEGER := 16#C0A8#; - CONSTANT CFG_ETH_IPL : INTEGER := 16#0033#; - CONSTANT CFG_ETH_ENM : INTEGER := 16#020000#; - CONSTANT CFG_ETH_ENL : INTEGER := 16#000009#; --- PROM/SRAM controller - CONSTANT CFG_SRCTRL : INTEGER := 0; - CONSTANT CFG_SRCTRL_PROMWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_RAMWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_IOWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_RMW : INTEGER := 0; - CONSTANT CFG_SRCTRL_8BIT : INTEGER := 0; - CONSTANT CFG_SRCTRL_SRBANKS : INTEGER := 1; - CONSTANT CFG_SRCTRL_BANKSZ : INTEGER := 0; - CONSTANT CFG_SRCTRL_ROMASEL : INTEGER := 0; --- LEON2 memory controller - CONSTANT CFG_MCTRL_LEON2 : INTEGER := 1; - CONSTANT CFG_MCTRL_RAM8BIT : INTEGER := 0; - CONSTANT CFG_MCTRL_RAM16BIT : INTEGER := 0; - CONSTANT CFG_MCTRL_5CS : INTEGER := 0; - CONSTANT CFG_MCTRL_SDEN : INTEGER := 1; - CONSTANT CFG_MCTRL_SEPBUS : INTEGER := 0; - CONSTANT CFG_MCTRL_INVCLK : INTEGER := 0; - CONSTANT CFG_MCTRL_SD64 : INTEGER := 0; - CONSTANT CFG_MCTRL_PAGE : INTEGER := 1 + 0; --- SDRAM controller - CONSTANT CFG_SDCTRL : INTEGER := 0; - CONSTANT CFG_SDCTRL_INVCLK : INTEGER := 0; - CONSTANT CFG_SDCTRL_SD64 : INTEGER := 0; - CONSTANT CFG_SDCTRL_PAGE : INTEGER := 0 + 0; --- AHB ROM - CONSTANT CFG_AHBROMEN : INTEGER := 0; - CONSTANT CFG_AHBROPIP : INTEGER := 0; - CONSTANT CFG_AHBRODDR : INTEGER := 16#000#; - CONSTANT CFG_ROMADDR : INTEGER := 16#000#; - CONSTANT CFG_ROMMASK : INTEGER := 16#E00# + 16#000#; --- AHB RAM - CONSTANT CFG_AHBRAMEN : INTEGER := 1; - CONSTANT CFG_AHBRSZ : INTEGER := 1; - CONSTANT CFG_AHBRADDR : INTEGER := 16#A00#; --- Gaisler Ethernet core - CONSTANT CFG_GRETH : INTEGER := 0; - CONSTANT CFG_GRETH1G : INTEGER := 0; - CONSTANT CFG_ETH_FIFO : INTEGER := 8; - --- CAN 2.0 interface - CONSTANT CFG_CAN : INTEGER := 0; - CONSTANT CFG_CANIO : INTEGER := 16#0#; - CONSTANT CFG_CANIRQ : INTEGER := 0; - CONSTANT CFG_CANLOOP : INTEGER := 0; - CONSTANT CFG_CAN_SYNCRST : INTEGER := 0; - CONSTANT CFG_CANFT : INTEGER := 0; - --- PCI interface - CONSTANT CFG_PCI : INTEGER := 0; - CONSTANT CFG_PCIVID : INTEGER := 16#0#; - CONSTANT CFG_PCIDID : INTEGER := 16#0#; - CONSTANT CFG_PCIDEPTH : INTEGER := 8; - CONSTANT CFG_PCI_MTF : INTEGER := 1; - --- PCI arbiter - CONSTANT CFG_PCI_ARB : INTEGER := 0; - CONSTANT CFG_PCI_ARBAPB : INTEGER := 0; - CONSTANT CFG_PCI_ARB_NGNT : INTEGER := 4; - --- PCI trace buffer - CONSTANT CFG_PCITBUFEN : INTEGER := 0; - CONSTANT CFG_PCITBUF : INTEGER := 256; - --- Spacewire interface - CONSTANT CFG_SPW_EN : INTEGER := 0; - CONSTANT CFG_SPW_NUM : INTEGER := 1; - CONSTANT CFG_SPW_AHBFIFO : INTEGER := 4; - CONSTANT CFG_SPW_RXFIFO : INTEGER := 16; - CONSTANT CFG_SPW_RMAP : INTEGER := 0; - CONSTANT CFG_SPW_RMAPBUF : INTEGER := 4; - CONSTANT CFG_SPW_RMAPCRC : INTEGER := 0; - CONSTANT CFG_SPW_NETLIST : INTEGER := 0; - CONSTANT CFG_SPW_FT : INTEGER := 0; - CONSTANT CFG_SPW_GRSPW : INTEGER := 2; - CONSTANT CFG_SPW_RXUNAL : INTEGER := 0; - CONSTANT CFG_SPW_DMACHAN : INTEGER := 1; - CONSTANT CFG_SPW_PORTS : INTEGER := 1; - CONSTANT CFG_SPW_INPUT : INTEGER := 2; - CONSTANT CFG_SPW_OUTPUT : INTEGER := 0; - CONSTANT CFG_SPW_RTSAME : INTEGER := 0; --- UART 1 - CONSTANT CFG_UART1_ENABLE : INTEGER := 1; - CONSTANT CFG_UART1_FIFO : INTEGER := 4; - --- UART 2 - CONSTANT CFG_UART2_ENABLE : INTEGER := 0; - CONSTANT CFG_UART2_FIFO : INTEGER := 1; - --- LEON3 interrupt controller - CONSTANT CFG_IRQ3_ENABLE : INTEGER := 1; - CONSTANT CFG_IRQ3_NSEC : INTEGER := 0; - --- Modular timer - CONSTANT CFG_GPT_ENABLE : INTEGER := 1; - CONSTANT CFG_GPT_NTIM : INTEGER := (2); - CONSTANT CFG_GPT_SW : INTEGER := (8); - CONSTANT CFG_GPT_TW : INTEGER := (32); - CONSTANT CFG_GPT_IRQ : INTEGER := (8); - CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; - CONSTANT CFG_GPT_WDOGEN : INTEGER := 1; - CONSTANT CFG_GPT_WDOG : INTEGER := 16#FFFF#; - --- GPIO port - CONSTANT CFG_GRGPIO_ENABLE : INTEGER := 1; - CONSTANT CFG_GRGPIO_IMASK : INTEGER := 16#0000#; - CONSTANT CFG_GRGPIO_WIDTH : INTEGER := (8); - --- GRLIB debugging - CONSTANT CFG_DUART : INTEGER := 1; -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/leon3mp.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/leon3mp.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/leon3mp.vhd +++ /dev/null @@ -1,642 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2010, Aeroflex Gaisler AB - all rights reserved. --- --- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN --- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED --- IN ADVANCE IN WRITING. ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE GRLIB.DMA2AHB_Package.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.pci.ALL; -USE gaisler.net.ALL; -USE gaisler.jtag.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -USE esa.pcicomp.ALL; -USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_bootloader_pkg.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_memory.ALL; - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - resetn : IN STD_ULOGIC; - clk : IN STD_ULOGIC; - pllref : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - dsutx : OUT STD_ULOGIC; -- DSU tx data - dsurx : IN STD_ULOGIC; -- DSU rx data - dsuen : IN STD_ULOGIC; - dsubre : IN STD_ULOGIC; - dsuact : OUT STD_ULOGIC; - txd1 : OUT STD_ULOGIC; -- UART1 tx data - rxd1 : IN STD_ULOGIC; -- UART1 rx data - txd2 : OUT STD_ULOGIC; -- UART2 tx data - rxd2 : IN STD_ULOGIC; -- UART2 rx data - ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - oen : OUT STD_ULOGIC; - writen : OUT STD_ULOGIC; - read : OUT STD_ULOGIC; - iosn : OUT STD_ULOGIC; - romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - emddis : OUT STD_LOGIC; - epwrdwn : OUT STD_ULOGIC; - ereset : OUT STD_ULOGIC; - esleep : OUT STD_ULOGIC; - epause : OUT STD_ULOGIC; - - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC; - pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - spw_clk : IN STD_ULOGIC; - spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - ramclk : OUT STD_LOGIC; - - nBWa : OUT STD_LOGIC; - nBWb : OUT STD_LOGIC; - nBWc : OUT STD_LOGIC; - nBWd : OUT STD_LOGIC; - nBWE : OUT STD_LOGIC; - nADSC : OUT STD_LOGIC; - nADSP : OUT STD_LOGIC; - nADV : OUT STD_LOGIC; - nGW : OUT STD_LOGIC; - nCE1 : OUT STD_LOGIC; - CE2 : OUT STD_LOGIC; - nCE3 : OUT STD_LOGIC; - nOE : OUT STD_LOGIC; - MODE : OUT STD_LOGIC; - SSRAM_CLK : OUT STD_LOGIC; - ZZ : OUT STD_LOGIC; - - tck, tms, tdi : IN STD_ULOGIC; - tdo : OUT STD_ULOGIC - ); -END; - -ARCHITECTURE rtl OF leon3mp IS - - CONSTANT blength : INTEGER := 12; - - CONSTANT maxahbmsp : INTEGER := NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI); - CONSTANT maxahbm : INTEGER := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp + 1; -- +LPP_DMA - - - - SIGNAL vcc, gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdi : sdctrl_in_type; - SIGNAL sdo : sdram_out_type; - SIGNAL sdo2, sdo3 : sdctrl_out_type; - - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - - SIGNAL clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; - SIGNAL u1i, u2i, dui : uart_in_type; - SIGNAL u1o, u2o, duo : uart_out_type; - - SIGNAL irqi : irq_in_vector(0 TO NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO NCPU-1); - - SIGNAL dbgi : l3_debug_in_vector(0 TO NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO NCPU-1); - - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - - SIGNAL pcii : pci_in_type; - SIGNAL pcio : pci_out_type; - - SIGNAL ethi, ethi1, ethi2 : eth_in_type; - SIGNAL etho, etho1, etho2 : eth_out_type; - - SIGNAL gpti : gptimer_in_type; - - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - - - SIGNAL lclk, pci_lclk : STD_ULOGIC := '0'; - SIGNAL pci_arb_req_n, pci_arb_gnt_n : STD_LOGIC_VECTOR(0 TO 3); - - SIGNAL spwi : grspw_in_type_vector(0 TO 2); - SIGNAL spwo : grspw_out_type_vector(0 TO 2); - SIGNAL spw_rx_clk : STD_ULOGIC; - - ATTRIBUTE sync_set_reset : STRING; - ATTRIBUTE sync_set_reset OF rstn : SIGNAL IS "true"; - - CONSTANT BOARD_FREQ : INTEGER := 40000; -- Board frequency in KHz - CONSTANT CPU_FREQ : INTEGER := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; - CONSTANT IOAEN : INTEGER := CFG_SDCTRL; - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - - CONSTANT sysfreq : INTEGER := (CFG_CLKMUL/CFG_CLKDIV)*40000; - - ----------------------------------------------------------------------------- - - SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fifo_empty : STD_LOGIC; - SIGNAL fifo_ren : STD_LOGIC; - SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL dma_empty : STD_LOGIC; - SIGNAL dma_ren : STD_LOGIC; - SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL header_val : STD_LOGIC; - SIGNAL header_ack : STD_LOGIC; - - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - - CONSTANT boardfreq : INTEGER := 50000; - -BEGIN - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); - gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; - cgi.pllrst <= rstraw; - - pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref); - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x); - - PROCESS(lclk2x) - BEGIN - IF lclk2x'EVENT AND lclk2x = '1' THEN - lclk <= NOT lclk; - END IF; - END PROCESS; - - pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk, lclk, clkm, OPEN, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; - - rst0 : rstgen -- reset generator - PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw); - ----------------------------------------------------------------------- ---- AHB CONTROLLER -------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- LEON3 processor and DSU ----------------------------------------- ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : odpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsuen_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsuen, dsui.enable); - dsubre_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsubre, dsui.break); - dsuact_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsuact, dsuo.active); - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart -- Debug UART - GENERIC MAP (hindex => NCPU, pindex => 7, paddr => 7) - PORT MAP (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsurx, dui.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsutx, duo.txd); - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(7) <= apb_none; END GENERATE; - - ahbjtaggen0 : IF CFG_AHB_JTAG = 1 GENERATE - ahbjtag0 : ahbjtag GENERIC MAP(tech => fabtech, hindex => NCPU+CFG_AHB_UART) - PORT MAP(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), - OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, gnd(0)); - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers ---------------------------------------------- ----------------------------------------------------------------------- --- LEON2 memory controller - sr1 : mctrl - GENERIC MAP ( - hindex => 0, - pindex => 0, - romaddr => 16#000#, - rommask => 16#E00#, - ioaddr => 16#200#, - iomask => 16#E00#, - ramaddr => 16#400#, - rammask => 16#C00#, - paddr => 0, - pmask => 16#fff#, - wprot => 0, - invclk => 0, - fast => 0, - romasel => 28, - sdrasel => 29, - srbanks => 4, - ram8 => 0, - ram16 => 0, - sden => 0, - sepbus => 0, - sdbits => 32, - sdlsb => 2, -- set to 12 for the GE-HPE board - oepol => 0, - syncrst => 0, - pageburst => 0, - scantest => 0, - mobile => 0 - ) - PORT MAP ( - rst => rstn, - clk => clkm, - memi => memi, - memo => memo, - ahbsi => ahbsi, - ahbso => ahbso(0), - apbi => apbi, - apbo => apbo(0), - wpo => wpo, - sdo => sdo - ); - - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads - addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0)); - rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0)); - roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0)); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (oen, memo.oen); - rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn); - roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0)); - wri_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (writen, memo.writen); - read_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (read, memo.read); - iosn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (iosn, memo.iosn); - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP (data(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - END GENERATE; - - SSRAM_0 : ssram_plugin - GENERIC MAP (tech => padtech) - PORT MAP (lclk2x, memo, SSRAM_CLK, - nBWa, nBWb, nBWc, nBWd, nBWE, nADSC, nADSP, nADV, nGW, nCE1, CE2, nCE3, nOE, MODE, ZZ); - - - ----------------------------------------------------------------------- ---- APB Bridge and various periherals ------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), u1i, u1o); - u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - - ua2 : IF CFG_UART2_ENABLE /= 0 GENERATE - uart2 : apbuart -- UART 2 - GENERIC MAP (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(9), u2i, u2o); - u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd; - END GENERATE; - noua1 : IF CFG_UART2_ENABLE = 0 GENERATE apbo(9) <= apb_none; END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, OPEN); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - gpio0 : IF CFG_GRGPIO_ENABLE /= 0 GENERATE -- GR GPIO unit - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, - nbits => CFG_GRGPIO_WIDTH) - PORT MAP(rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : FOR i IN 0 TO CFG_GRGPIO_WIDTH-1 GENERATE - pio_pad : iopad GENERIC MAP (tech => padtech) - PORT MAP (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - END GENERATE; - END GENERATE; - ------------------------------------------------------------------------ ---- PCI ------------------------------------------------------------ ------------------------------------------------------------------------ - - pp : IF CFG_PCI /= 0 GENERATE - - pci_gr0 : IF CFG_PCI = 1 GENERATE -- simple target-only - pci0 : pci_target GENERIC MAP (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - device_id => CFG_PCIDID, vendor_id => CFG_PCIVID) - PORT MAP (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG)); - END GENERATE; - - pci_mtf0 : IF CFG_PCI = 2 GENERATE -- master/target with fifo - pci0 : pci_mtf GENERIC MAP (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, - ioaddr => 16#400#, nsync => 2, hostrst => 1) - PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4), - ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - END GENERATE; - - pci_mtf1 : IF CFG_PCI = 3 GENERATE -- master/target with fifo and DMA - dma : pcidma GENERIC MAP (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1, - dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, - nsync => 2, hostrst => 1) - PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1), - apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - END GENERATE; - - pci_trc0 : IF CFG_PCITBUFEN /= 0 GENERATE -- PCI trace buffer - pt0 : pcitrace GENERIC MAP (depth => (6 + log2(CFG_PCITBUF/256)), - memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#) - PORT MAP (rstn, clkm, pciclk, pcii, apbi, apbo(8)); - END GENERATE; - - pcia0 : IF CFG_PCI_ARB = 1 GENERATE -- PCI arbiter - pciarb0 : pciarb GENERIC MAP (pindex => 10, paddr => 10, - apb_en => CFG_PCI_ARBAPB) - PORT MAP (clk => pciclk, rst_n => pcii.rst, - req_n => pci_arb_req_n, frame_n => pcii.frame, - gnt_n => pci_arb_gnt_n, pclk => clkm, - prst_n => rstn, apbi => apbi, apbo => apbo(10) - ); - pgnt_pad : outpadv GENERIC MAP (tech => padtech, width => 4) - PORT MAP (pci_arb_gnt, pci_arb_gnt_n); - preq_pad : inpadv GENERIC MAP (tech => padtech, width => 4) - PORT MAP (pci_arb_req, pci_arb_req_n); - END GENERATE; - - pcipads0 : pcipads GENERIC MAP (padtech => padtech) -- PCI pads - PORT MAP (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, - pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio); - - END GENERATE; - --- nop1 : IF CFG_PCI <= 1 GENERATE apbo(4) <= apb_none; END GENERATE; --- nop2 : IF CFG_PCI <= 2 GENERATE apbo(5) <= apb_none; END GENERATE; - nop3 : IF CFG_PCI <= 1 GENERATE ahbso(4) <= ahbs_none; END GENERATE; - notrc : IF CFG_PCITBUFEN = 0 GENERATE apbo(8) <= apb_none; END GENERATE; - noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE; - - --- ahbso(6) <= ahbs_none; - ------------------------------------------------------------------------ ---- AHB RAM ---------------------------------------------------------- ------------------------------------------------------------------------ - - ocram : IF CFG_AHBRAMEN = 1 GENERATE - ahbram0 : ahbram GENERIC MAP (hindex => 7, haddr => CFG_AHBRADDR, - tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) - PORT MAP (rstn, clkm, ahbsi, ahbso(7)); - END GENERATE; - nram : IF CFG_AHBRAMEN = 0 GENERATE ahbso(7) <= ahbs_none; END GENERATE; - ------------------------------------------------------------------------ ---- SPACEWIRE ------------------------------------------------------- ------------------------------------------------------------------------ - --This template does NOT currently support grspw2 so only use grspw1 - spw : IF CFG_SPW_EN > 0 GENERATE - spw_rx_clk <= '0'; - spw_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (spw_clk, spw_lclk); - swloop : FOR i IN 0 TO CFG_SPW_NUM-1 GENERATE - sw0 : grspwm GENERIC MAP(tech => memtech, netlist => CFG_SPW_NETLIST, - hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i, - sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1, - fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO, - rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW) - PORT MAP(resetn, clkm, spw_rx_clk, spw_rx_clk, spw_lclk, spw_lclk, - ahbmi, ahbmo(maxahbmsp+i), - apbi, apbo(12+i), spwi(i), spwo(i)); - spwi(i).tickin <= '0'; spwi(i).rmapen <= '1'; - spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8); - spw_rxd_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxd(i), spw_rxdn(i), spwi(i).d(0)); - spw_rxs_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxs(i), spw_rxsn(i), spwi(i).s(0)); - spw_txd_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0)); - spw_txs_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0)); - END GENERATE; - END GENERATE; - - - -------------------------------------------------------------------------------- --- BOOT MEMORY AND REGISTER -------------------------------------------------------------------------------- - - lpp_bootloader_1: lpp_bootloader - GENERIC MAP ( - pindex => 13, - paddr => 13, - pmask => 16#fff#, - - hindex => 6, - haddr => 16#900#, - hmask => 16#F00#) - PORT MAP ( - HCLK => clkm, - HRESETn => resetn, - apbi => apbi, - apbo => apbo(13), - ahbsi => ahbsi, - ahbso => ahbso(6)); - - -------------------------------------------------------------------------------- --- AHB DMA -------------------------------------------------------------------------------- - - lpp_dma_1 : lpp_dma - GENERIC MAP ( - tech => fabtech, - hindex => 2, - pindex => 14, - paddr => 14, - pmask => 16#fff#, - pirq => 0) - PORT MAP ( - HCLK => clkm, - HRESETn => resetn, - apbi => apbi, - apbo => apbo(14), - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(2), - fifo_data => fifo_data, --dma_data, - fifo_empty => fifo_empty, --dma_empty, - fifo_ren => fifo_ren, --dma_ren, - header => header, - header_val => header_val, - header_ack => header_ack); - - fifo_test_dma_1 : fifo_test_dma - GENERIC MAP ( - tech => fabtech, - pindex => 15, - paddr => 15, - pmask => 16#fff#) - PORT MAP ( - HCLK => clkm, - HRESETn => resetn, - apbi => apbi, - apbo => apbo(15), - fifo_data => fifo_data, - fifo_empty => fifo_empty, - fifo_ren => fifo_ren, - header => header, - header_val => header_val, - header_ack => header_ack); - ------------------------------------------------------------------------ ---- Boot message ---------------------------------------------------- ------------------------------------------------------------------------ - --- pragma translate_off - x : report_version - GENERIC MAP ( - msg1 => "LEON3 MP Demonstration design", - msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION MOD 1000)/100) - & "." & tost(LIBVHDL_VERSION MOD 100) & ", build " & tost(LIBVHDL_BUILD), - msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech), - mdel => 1 - ); --- pragma translate_on -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/lpp-dm-sheldon-a3pe3000/config.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/lpp-dm-sheldon-a3pe3000/config.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/lpp-dm-sheldon-a3pe3000/config.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3e; - constant CFG_MEMTECH : integer := apa3e; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - --constant CFG_NWIN : integer := (7); -- PLE - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist - --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (3); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/lpp-dm-sheldon-a3pe3000/leon3mp.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/lpp-dm-sheldon-a3pe3000/leon3mp.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/lpp-dm-sheldon-a3pe3000/leon3mp.vhd +++ /dev/null @@ -1,508 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -library techmap; -use techmap.gencomp.all; -library gaisler; -use gaisler.memctrl.all; -use gaisler.leon3.all; -use gaisler.uart.all; -use gaisler.misc.all; -use gaisler.spacewire.all; -- PLE -library esa; -use esa.memoryctrl.all; -use work.config.all; -library lpp; ---use lpp.lpp_amba.all; -use lpp.lpp_memory.all; ---use lpp.lpp_uart.all; ---use lpp.lpp_matrix.all; ---use lpp.lpp_delay.all; ---use lpp.lpp_fft.all; ---use lpp.fft_components.all; ---use lpp.lpp_ad_conv.all; ---use lpp.iir_filter.all; -use lpp.general_purpose.all; ---use lpp.Filtercfg.all; -use lpp.lpp_lfr_time_management.all; -- PLE -use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE -use lpp.lpp_top_lfr_pkg.all; - -entity leon3mp is - generic ( - fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console - pclow : integer := CFG_PCLOW - ); - port ( - clk100MHz : in std_ulogic; - clk49_152MHz : in std_ulogic; - reset : in std_ulogic; - ramclk : out std_logic; - - ahbrxd : in std_ulogic; -- DSU rx data - ahbtxd : out std_ulogic; -- DSU tx data - dsubre : in std_ulogic; - dsuact : out std_ulogic; - urxd1 : in std_ulogic; -- UART1 rx data - utxd1 : out std_ulogic; -- UART1 tx data - errorn : out std_ulogic; - - address : out std_logic_vector(18 downto 0); - data : inout std_logic_vector(31 downto 0); - gpio : inout std_logic_vector(6 downto 0); -- I/O port - - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------In/Out----------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - led : out std_logic_vector(1 downto 0); - - -- waveform picker------ - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic; - - -- SPACEWIRE ----------- - spw1_din : in std_logic; -- PLE - spw1_sin : in std_logic; -- PLE - spw1_dout : out std_logic; -- PLE - spw1_sout : out std_logic; -- PLE - spw1_en_bar : out std_logic; - spw2_en_bar : out std_logic - ); -end; - -architecture Behavioral of leon3mp is - ---constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ --- CFG_GRETH+CFG_AHB_JTAG; -constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+1 -- 1 is for the SpaceWire module grspw2, which is a master - +1; -- 1 is for the waveform picker top -constant maxahbm : integer := maxahbmsp; - ---Clk & Rst géné -signal vcc : std_logic_vector(4 downto 0); -signal gnd : std_logic_vector(4 downto 0); -signal resetnl : std_ulogic; -signal clk2x : std_ulogic; -signal lclk2x : std_ulogic; -signal lclk25MHz : std_ulogic; -signal lclk50MHz : std_ulogic; -signal lclk100MHz : std_ulogic; -signal clkm : std_ulogic; -signal rstn : std_ulogic; -signal rstraw : std_ulogic; -signal pciclk : std_ulogic; -signal sdclkl : std_ulogic; -signal cgi : clkgen_in_type; -signal cgo : clkgen_out_type; ---- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); ---UART -signal ahbuarti : uart_in_type; -signal ahbuarto : uart_out_type; -signal apbuarti : uart_in_type; -signal apbuarto : uart_out_type; ---MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal wpo : wprot_out_type; -signal sdo : sdram_out_type; ---IRQ -signal irqi : irq_in_vector(0 to CFG_NCPU-1); -signal irqo : irq_out_vector(0 to CFG_NCPU-1); ---Timer -signal gpti : gptimer_in_type; -signal gpto : gptimer_out_type; ---GPIO -signal gpioi : gpio_in_type; -signal gpioo : gpio_out_type; ---DSU -signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); -signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); -signal dsui : dsu_in_type; -signal dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- -constant IOAEN : integer := CFG_CAN; -constant boardfreq : integer := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - signal coarse_time : std_logic_vector(31 downto 0); - signal fine_time : std_logic_vector(31 downto 0); - --- Spacewire signals - signal dtmp : std_ulogic; -- PLE - signal stmp : std_ulogic; -- PLE - signal rxclko : std_ulogic; -- PLE - signal swni : grspw_in_type; -- PLE - signal swno : grspw_out_type; -- PLE - signal clkmn : std_ulogic; -- PLE - signal txclk : std_ulogic; -- PLE 2013 02 14 - --- ahb status signals - signal stati : ahbstat_in_type; - -begin - ---------------------------------------------------------------------- ---- AJOUT TEST -------------------------------------IPs------------- ---------------------------------------------------------------------- - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (others => '1'); gnd <= (others => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad generic map (tech => padtech) port map (clk100MHz, lclk100MHz); - - -- IT SEEMS THAT THE PLL IS NOT INSTANTIATED AND THAT lclk2x is a 50 MHz CLOCK - clkgen0 : clkgen -- clock generator - generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - --port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); -- PLE - port map (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); -- PLE - - ramclk <= clkm; - -process(lclk100MHz) -begin - if lclk100MHz'event and lclk100MHz = '1' then - lclk50MHz <= not lclk50MHz; - end if; -end process; - -process(lclk50MHz) -begin - if lclk50MHz'event and lclk50MHz = '1' then - lclk25MHz <= not lclk25MHz; - end if; -end process; - -lclk2x <= lclk50MHz; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : if CFG_LEON3 = 1 generate - cpu : for i in 0 to CFG_NCPU-1 generate - u0 : leon3s -- LEON3 processor - generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - end generate; - errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); - - dsugen : if CFG_DSU = 1 generate - dsu0 : dsu3 -- LEON3 Debug Support Unit - generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); --- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); - dsui.enable <= '1'; - dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); - dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); - end generate; - end generate; - - nodsu : if CFG_DSU = 0 generate - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - end generate; - - irqctrl : if CFG_IRQ3_ENABLE /= 0 generate - irqctrl0 : irqmp -- interrupt controller - generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - port map (rstn, clkm, apbi, apbo(2), irqo, irqi); - end generate; - irq3 : if CFG_IRQ3_ENABLE = 0 generate - x : for i in 0 to CFG_NCPU-1 generate - irqi(i).irl <= "0000"; - end generate; - apbo(2) <= apb_none; - end generate; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - - memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - bdr : for i in 0 to 3 generate - data_pad : iopadv generic map (tech => padtech, width => 8) - port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), - memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); - end generate; - - - addr_pad : outpadv generic map (width => 19, tech => padtech) - port map (address, memo.address(20 downto 2)); - - - SSRAM_0:entity ssram_plugin - generic map (tech => padtech) - port map - (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - dcomgen : if CFG_AHB_UART = 1 generate - dcom0: ahbuart -- Debug UART - generic map (hindex => 3, pindex => 4, paddr => 4) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); - dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); - led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; - end generate; - nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR) - port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - - gpt : if CFG_GPT_ENABLE /= 0 generate - timer0 : gptimer -- timer unit - generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - port map (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; --- led(4) <= gpto.wdog; - end generate; - notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - ua1 : if CFG_UART1_ENABLE /= 0 generate - uart1 : apbuart -- UART 1 - generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; --- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; - end generate; - noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit - grgpio0: grgpio - generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) - port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : for i in 0 to 6 generate - pio_pad : iopad generic map (tech => padtech) - port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - end generate; - end generate; - --------------------------- --- APB_LFR_TIME_MANAGEMENT --------------------------- - lfrtimemanagement0 : apb_lfr_time_management - generic map(pindex => 6, paddr => 6, pmask => 16#fff#, - masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536, - pirq => 12) -- the IP uses 2 consecutive IRQ lines - port map(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6), - coarse_time, fine_time); - --------------------------------- --- APB_LFR_SPECTRAL_MATRICES_DMA --------------------------------- --- lfrspectralmatricesdma0 : apb_lfr_spectral_matrices_DMA --- generic map(pindex => 7, paddr =>7, pmask => 16#fff#) --- port map(clkm, rstn, apbi, apbo(7)); - ------------------------------- ---- AHB STATUS --------------- ------------------------------- - ---astat0 : ahbstat generic map(pindex => 13, paddr => 13, pirq => 14, nftslv => 3) --- port map(rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13)); --- stati.cerror(3 to NAHBSLV-1) <= (others => '0'); - ------------------- --- WAVEFORM PICKER ------------------- - -waveform_picker0 : lpp_top_lfr_wf_picker generic map( - hindex => 2, - pindex => 8, - paddr => 8, - pmask => 16#fff#, - pirq => 15, - tech => CFG_FABTECH, - nb_burst_available_size => 11, -- size of the register holding the nb of burst - nb_snapshot_param_size => 11, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 10, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 10 -- nb f0 ticks before starting the f1 snapshot - ) - port map( - -- ADS7886 - cnv_run => '1', -- stop the sampling request - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(8), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(2), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => Bias_Fails - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - -spw_phy0 : grspw2_phy generic map( - scantest => 0, - tech => memtech, - input_type => 0) -- self_clocking mode - port map( - rstn => rstn, - rxclki => clkm, rxclkin => clkmn, nrxclki => clkm, -- not used in self-clocking - di => dtmp, - si => stmp, - do => swni.d(1 downto 0), - dov => swni.dv(1 downto 0), - dconnect => swni.dconnect(1 downto 0), - rxclko => rxclko); - -sw0 : grspwm generic map(tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, usegen => 1, -- sysfreq not used by the core version 2? usegen? - nsync => 1, -- nsync not used by the core version 2? - rmap => 1, rmapcrc => 1, - fifosize1 => 16, fifosize2 => 16, - rxclkbuftype => 2, rxunaligned => 0, - spwcore => 2, - memtech => apa3e, - nodeaddr => 254, destkey => 2, - rmapbufs => 4, netlist => 0, ft => 0, ports => 2) - port map(rstn, clkm, rxclko, rxclko, txclk, txclk, - ahbmi, ahbmo(1), apbi, apbo(5), swni, swno); - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00001001"; -- divisor to get a 10M Hz tx clock from the txclk input - - - spw1_dout <= swno.d(0); - spw1_sout <= swno.s(0); - dtmp <= not(spw1_din); - stmp <= not(spw1_sin); - spw1_en_bar <= '0'; -- V16, connected to spw2_en - spw2_en_bar <= '1'; -- T18, connected to spw1_en - - txclk <= lclk100MHz; - -end Behavioral; \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/prom.srec b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/prom.srec deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/prom.srec +++ /dev/null @@ -1,2975 +0,0 @@ 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-S113B98000000000000000000000000000000000B3 -S113B99000000000000000000000000000000000A3 -S113B9A00000000000000000000000000000000093 -S113B9B00000000000000000000000000000000083 -S113B9C000000000000000000000000080000100F2 -S9030000FC diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim.do deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim.do +++ /dev/null @@ -1,34 +0,0 @@ -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/fifo_latency_correction.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/fifo_test_dma.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_pkg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_ip.vhd -##vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_fsm.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_memory/lpp_memory.vhd - -vcom -quiet -93 -work work CY7C1360C/package_utility.vhd -vcom -quiet -93 -work work CY7C1360C/CY7C1360C.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./bootrom.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./lpp_bootloader_pkg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./lpp_bootloader.vhd - -vcom -quiet -93 -work work config.vhd -vcom -quiet -93 -work work ahbrom.vhd -vcom -quiet -93 -work work leon3mp.vhd -vcom -quiet -93 -work work testbench.vhd - -vsim work.testbench - -log -r * -do wave_bootloader.do -run 20 us -force -freeze sim:/testbench/d3/lpp_bootloader_1/reg.addr_start_execution 00000000000000000000000000000000 0 -run 60 ns -force -freeze sim:/testbench/d3/lpp_bootloader_1/reg.config_start_execution 1 0 -run -all \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do +++ /dev/null @@ -1,72 +0,0 @@ - -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd -#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd - -vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd -vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd - - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd -#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd - -vcom -quiet -93 -work work Top_Data_Acquisition.vhd - -vcom -quiet -93 -work work TB_Data_Acquisition.vhd - -#vsim work.TB_Data_Acquisition - -#log -r * -#do wave_data_acquisition.do -#run 5 ms \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do +++ /dev/null @@ -1,83 +0,0 @@ - -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd -#vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd - -vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd -vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd - - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd -#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd -#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/apb_lfr_time_management.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lfr_time_management.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_burst.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd - -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd -#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd - -vcom -quiet -93 -work work Top_Data_Acquisition.vhd - -vcom -quiet -93 -work work TB_Data_Acquisition.vhd - -vsim work.TB_Data_Acquisition - -log -r * -do wave_waveform_picker.do -run 5 ms diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/sram.srec b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/sram.srec deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/sram.srec +++ /dev/null @@ -1,4968 +0,0 @@ -S00C00007372616D2E7372656365 -S31540000000881000000910004881C120B80100000096 -S31540000010A1480000A75000001080203EAC102001EF -S3154000002091D0200001000000010000000100000006 -S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910004881C5200C010000008D -S31540000050A14800002910004581C520C401000000C8 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a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/testbench.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/testbench.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/testbench.vhd +++ /dev/null @@ -1,521 +0,0 @@ ------------------------------------------------------------------------------- --- LEON3 Demonstration design test bench --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2010, Aeroflex Gaisler --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY micron; -USE micron.components.ALL; -USE work.debug.ALL; - -USE work.config.ALL; -- configuration - -ENTITY testbench IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW; - - clkperiod : INTEGER := 20; -- system clock period - romwidth : INTEGER := 32; -- rom data width (8/32) - romdepth : INTEGER := 16; -- rom address depth - sramwidth : INTEGER := 32; -- ram data width (8/16/32) - sramdepth : INTEGER := 21; -- ram address depth - srambanks : INTEGER := 2 -- number of ram banks - ); - PORT ( - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC - ); -END; - -ARCHITECTURE behav OF testbench IS - - CONSTANT promfile : STRING := "prom.srec"; -- rom contents - CONSTANT sramfile : STRING := "sram.srec"; -- ram contents - CONSTANT sdramfile : STRING := "sdram.srec"; -- sdram contents - - COMPONENT leon3mp - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - resetn : IN STD_ULOGIC; - clk : IN STD_ULOGIC; - pllref : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dsutx : OUT STD_ULOGIC; -- DSU tx data - dsurx : IN STD_ULOGIC; -- DSU rx data - dsuen : IN STD_ULOGIC; - dsubre : IN STD_ULOGIC; - dsuact : OUT STD_ULOGIC; - txd1 : OUT STD_ULOGIC; -- UART1 tx data - rxd1 : IN STD_ULOGIC; -- UART1 rx data - txd2 : OUT STD_ULOGIC; -- UART1 tx data - rxd2 : IN STD_ULOGIC; -- UART1 rx data - ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - oen : OUT STD_ULOGIC; - writen : OUT STD_ULOGIC; - read : OUT STD_ULOGIC; - iosn : OUT STD_ULOGIC; - romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - - emddis : OUT STD_LOGIC; - epwrdwn : OUT STD_LOGIC; - ereset : OUT STD_LOGIC; - esleep : OUT STD_LOGIC; - epause : OUT STD_LOGIC; - - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC; - pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - spw_clk : IN STD_ULOGIC; - spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - ramclk : OUT STD_LOGIC; - - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; - - tck, tms, tdi : IN STD_ULOGIC; - tdo : OUT STD_ULOGIC - - ); - END COMPONENT; - - COMPONENT CY7C1360C - GENERIC ( - addr_bits : INTEGER; - data_bits : INTEGER; - Cyp_tCO : TIME; - Cyp_tCYC : TIME; - Cyp_tCH : TIME; - Cyp_tCL : TIME; - Cyp_tCHZ : TIME; - Cyp_tCLZ : TIME; - Cyp_tOEHZ : TIME; - Cyp_tOELZ : TIME; - Cyp_tOEV : TIME; - Cyp_tAS : TIME; - Cyp_tADS : TIME; - Cyp_tADVS : TIME; - Cyp_tWES : TIME; - Cyp_tDS : TIME; - Cyp_tCES : TIME; - Cyp_tAH : TIME; - Cyp_tADH : TIME; - Cyp_tADVH : TIME; - Cyp_tWEH : TIME; - Cyp_tDH : TIME; - Cyp_tCEH : TIME); - PORT ( - iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0); - iCLK : IN STD_LOGIC); - END COMPONENT; - - - SIGNAL clk : STD_LOGIC := '0'; - SIGNAL Rst : STD_LOGIC := '0'; -- Reset - CONSTANT ct : INTEGER := clkperiod/2; - - SIGNAL address : STD_LOGIC_VECTOR(27 DOWNTO 0); - SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL ioData : STD_LOGIC_VECTOR(35 DOWNTO 0); - - SIGNAL ramsn : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL ramoen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL rwen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL rwenx : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL romsn : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL iosn : STD_ULOGIC; - SIGNAL oen : STD_ULOGIC; - SIGNAL read : STD_ULOGIC; - SIGNAL writen : STD_ULOGIC; - SIGNAL brdyn : STD_ULOGIC; - SIGNAL bexcn : STD_ULOGIC; - SIGNAL wdog : STD_ULOGIC; - SIGNAL dsuen, dsutx, dsurx, dsubre, dsuact : STD_ULOGIC; - SIGNAL dsurst : STD_ULOGIC; - SIGNAL test : STD_ULOGIC; - SIGNAL error : STD_LOGIC; - SIGNAL gpio : STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); - SIGNAL GND : STD_ULOGIC := '0'; - SIGNAL VCC : STD_ULOGIC := '1'; - SIGNAL NC : STD_ULOGIC := 'Z'; - SIGNAL clk2 : STD_ULOGIC := '1'; - - SIGNAL sdcke : STD_LOGIC_VECTOR (1 DOWNTO 0); -- clk en - SIGNAL sdcsn : STD_LOGIC_VECTOR (1 DOWNTO 0); -- chip sel - SIGNAL sdwen : STD_ULOGIC; -- write en - SIGNAL sdrasn : STD_ULOGIC; -- row addr stb - SIGNAL sdcasn : STD_ULOGIC; -- col addr stb - SIGNAL sddqm : STD_LOGIC_VECTOR (7 DOWNTO 0); -- data i/o mask - SIGNAL sdclk : STD_ULOGIC; - SIGNAL plllock : STD_ULOGIC; - SIGNAL txd1, rxd1 : STD_ULOGIC; - SIGNAL txd2, rxd2 : STD_ULOGIC; - - SIGNAL etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : STD_LOGIC := '0'; - SIGNAL erxd, etxd : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); - SIGNAL erxdt, etxdt : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); - SIGNAL emdc : STD_LOGIC; - SIGNAL gtx_clk : STD_ULOGIC; - - SIGNAL emddis : STD_LOGIC; - SIGNAL epwrdwn : STD_LOGIC; - SIGNAL ereset : STD_LOGIC; - SIGNAL esleep : STD_LOGIC; - SIGNAL epause : STD_LOGIC; - - CONSTANT lresp : BOOLEAN := false; - - SIGNAL sa : STD_LOGIC_VECTOR(14 DOWNTO 0); - SIGNAL sd : STD_LOGIC_VECTOR(63 DOWNTO 0); - - SIGNAL pci_arb_req, pci_arb_gnt : STD_LOGIC_VECTOR(0 TO 3); - - - SIGNAL spw_clk : STD_ULOGIC := '0'; - SIGNAL spw_rxd : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxdn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxs : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxsn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_txd : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txdn : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txs : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txsn : STD_LOGIC_VECTOR(0 TO 2); - - SIGNAL tck, tms, tdi, tdo : STD_ULOGIC; - - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - CONSTANT CFG_SD64 : INTEGER := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64; - - ----------------------------------------------------------------------------- - - SIGNAL ramclk : STD_LOGIC; - - SIGNAL nBWa : std_logic; - SIGNAL nBWb : std_logic; - SIGNAL nBWc : std_logic; - SIGNAL nBWd : std_logic; - SIGNAL nBWE : std_logic; - SIGNAL nADSC : std_logic; - SIGNAL nADSP : std_logic; - SIGNAL nADV : std_logic; - SIGNAL nGW : std_logic; - SIGNAL nCE1 : std_logic; - SIGNAL CE2 : std_logic; - SIGNAL nCE3 : std_logic; - SIGNAL nOE : std_logic; - SIGNAL MODE : std_logic; - SIGNAL SSRAM_CLK : std_logic; - SIGNAL ZZ : std_logic; - - -BEGIN - --- clock and reset - - spw_clk <= NOT spw_clk AFTER 20 ns; - spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0); - spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0); - spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1); - spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1); - spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2); - spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2); - clk <= NOT clk AFTER ct * 1 ns; - rst <= dsurst; - dsuen <= '1'; dsubre <= '0'; rxd1 <= '1'; - - d3 : leon3mp - GENERIC MAP (fabtech, - memtech, - padtech, - clktech, - disas, - dbguart, - pclow) - PORT MAP (rst, clk, sdclk, error, address(27 DOWNTO 0), data, - dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2, - ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio, - - emddis, epwrdwn, ereset, esleep, epause, - pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par, - pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt, - spw_clk, spw_rxd, spw_rxdn, spw_rxs, - spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, - - - ramclk , - - nBWa , - nBWb , - nBWc , - nBWd , - nBWE , - nADSC , - nADSP , - nADV , - nGW , - nCE1 , - CE2 , - nCE3 , - nOE , - MODE , - SSRAM_CLK , - ZZ , - - - - tck, tms, tdi, tdo); - - ----------------------------------------------------------------------------- - - prom0 : FOR i IN 0 TO (romwidth/8)-1 GENERATE - sr0 : sram GENERIC MAP (index => i, abits => romdepth, fname => promfile) - PORT MAP (address(romdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), romsn(0), - rwen(i), oen); - END GENERATE; - - ----------------------------------------------------------------------------- - CY7C1360C_2: CY7C1360C - GENERIC MAP ( - - - addr_bits => 19, - data_bits => 36, - - Cyp_tCO => 3.5 ns, -- Data Output Valid After CLK Rise - Cyp_tCYC => 6.0 ns, -- Clock cycle time - Cyp_tCH => 2.4 ns, -- Clock HIGH time - Cyp_tCL => 2.4 ns, -- Clock LOW time - Cyp_tCHZ => 3.5 ns, -- Clock to High-Z - Cyp_tCLZ => 1.25 ns, -- Clock to Low-Z - Cyp_tOEHZ => 3.5 ns, -- OE# HIGH to Output High-Z - Cyp_tOELZ => 0.0 ns, -- OE# LOW to Output Low-Z - Cyp_tOEV => 3.5 ns, -- OE# LOW to Output Valid - Cyp_tAS => 1.5 ns, -- Address Set-up Before CLK Rise - Cyp_tADS => 1.5 ns, -- ADSC#, ADSP# Set-up Before CLK Rise - Cyp_tADVS => 1.5 ns, -- ADV# Set-up Before CLK Rise - Cyp_tWES => 1.5 ns, -- BWx#, GW#, BWE# Set-up Before CLK Rise - Cyp_tDS => 1.5 ns, -- Data Input Set-up Before CLK Rise - Cyp_tCES => 1.5 ns, -- Chip Enable Set-up - Cyp_tAH => 0.5 ns, -- Address Hold After CLK Rise - Cyp_tADH => 0.5 ns, -- ADSC#, ADSP# Hold After CLK Rise - Cyp_tADVH => 0.5 ns, -- ADV# Hold After CLK Rise - Cyp_tWEH => 0.5 ns, -- BWx#, GW#, BWE# Hold After CLK Rise - Cyp_tDH => 0.5 ns, -- Data Input Hold After CLK Rise - Cyp_tCEH => 0.5 ns -- Chip Enable Hold After CLK Rise - - - --Cyp_tCO => 2.8 ns, - --Cyp_tCYC => 4.0 ns, - --Cyp_tCH => 1.8 ns, - --Cyp_tCL => 1.8 ns, - --Cyp_tCHZ => 2.8 ns, - --Cyp_tCLZ => 1.25 ns, - --Cyp_tOEHZ => 2.8 ns, - --Cyp_tOELZ => 0.0 ns, - --Cyp_tOEV => 2.8 ns, - --Cyp_tAS => 1.4 ns, - --Cyp_tADS => 1.4 ns, - --Cyp_tADVS => 1.4 ns, - --Cyp_tWES => 1.4 ns, - --Cyp_tDS => 1.4 ns, - --Cyp_tCES => 1.4 ns, - --Cyp_tAH => 0.4 ns, - --Cyp_tADH => 0.4 ns, - --Cyp_tADVH => 0.4 ns, - --Cyp_tWEH => 0.4 ns, - --Cyp_tDH => 0.4 ns, - --Cyp_tCEH => 0.4 ns - ) - PORT MAP ( - iZZ => ZZ, - iMode => MODE, - iADDR => address(20 DOWNTO 2), - inGW => nGW, - inBWE => nBWE, - inBWd => nBWd, - inBWc => nBWc, - inBWb => nBWb, - inBWa => nBWa, - inCE1 => nCE1, - iCE2 => CE2, - inCE3 => nCE3, - inADSP => nADSP, - inADSC => nADSC, - inADV => nADV, - inOE => nOE, - ioDQ => ioData, -- - iCLK => SSRAM_CLK); -- ?? - - - ioData <= "0" & data(31 DOWNTO 24) & - "0" & data(23 DOWNTO 16) & - "0" & data(15 DOWNTO 8) & - "0" & data( 7 DOWNTO 0) ; - - --sbanks : FOR k IN 0 TO srambanks-1 GENERATE - -- sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE - -- sr0 : sram GENERIC MAP (index => i, abits => sramdepth, fname => sramfile) - -- PORT MAP (address(sramdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), - -- ramsn(k), rwen(i), ramoen(k)); - -- END GENERATE; - --END GENERATE; - - error <= 'H'; -- ERROR pull-up - - iuerr : PROCESS - BEGIN - WAIT FOR 2500 ns; - IF to_x01(error) = '1' THEN WAIT ON error; END IF; - ASSERT (to_x01(error) = '1') - REPORT "*** IU in error mode, simulation halted ***" - SEVERITY failure; - END PROCESS; - - data <= buskeep(data), (OTHERS => 'H') AFTER 250 ns; - sd <= buskeep(sd), (OTHERS => 'H') AFTER 250 ns; - - test0 : grtestmod - PORT MAP (rst, clk, error, address(21 DOWNTO 2), data, iosn, oen, writen, brdyn); - - - dsucom : PROCESS - PROCEDURE dsucfg(SIGNAL dsurx : IN STD_ULOGIC; SIGNAL dsutx : OUT STD_ULOGIC) IS - VARIABLE w32 : STD_LOGIC_VECTOR(31 DOWNTO 0); - VARIABLE c8 : STD_LOGIC_VECTOR(7 DOWNTO 0); - CONSTANT txp : TIME := 160 * 1 ns; - BEGIN - dsutx <= '1'; - dsurst <= '0'; - WAIT FOR 500 ns; - dsurst <= '1'; - WAIT; - WAIT FOR 5000 ns; - END; - BEGIN - - dsucfg(dsutx, dsurx); - WAIT; - - END PROCESS; - -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_data_acquisition.do +++ /dev/null @@ -1,49 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample -add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val -add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val -add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in -add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val -add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in_val -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out_val -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in_val -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out_val -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in_val -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out_val -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in_val -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out_val -add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out -add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wen -add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wdata -add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wen -add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wdata -add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wen -add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wdata -add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wen -add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wdata -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -configure wave -namecolwidth 430 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {0 ps} {754717 ps} diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_dma.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_dma.do deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_dma.do +++ /dev/null @@ -1,196 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal -radix hexadecimal -expand /testbench/gpio -add wave -noupdate -format Literal -radix hexadecimal -expand /testbench/d3/lpp_dma_1/ahb_master_in -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/ahb_master_out -add wave -noupdate -format Logic -radix hexadecimal /testbench/clk -add wave -noupdate -format Logic -radix hexadecimal /testbench/rst -add wave -noupdate -expand -group AHB_BUS -add wave -noupdate -group AHB_BUS -format Logic -radix hexadecimal /testbench/d3/ahb0/rst -add wave -noupdate -group AHB_BUS -format Logic -radix hexadecimal /testbench/d3/ahb0/clk -add wave -noupdate -group AHB_BUS -format Literal -radix hexadecimal /testbench/d3/ahb0/msti -add wave -noupdate -group AHB_BUS -format Literal -radix hexadecimal /testbench/d3/ahb0/msto -add wave -noupdate -group AHB_BUS -format Literal -radix hexadecimal /testbench/d3/ahb0/slvi -add wave -noupdate -group AHB_BUS -format Literal -radix hexadecimal /testbench/d3/ahb0/slvo -add wave -noupdate -divider GPIO_TEST -add wave -noupdate -divider DMA -add wave -noupdate -expand -group DMA -add wave -noupdate -group DMA -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/hclk -add wave -noupdate -group DMA -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/hresetn -add wave -noupdate -group DMA -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/fifo_data -add wave -noupdate -group DMA -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/fifo_empty -add wave -noupdate -group DMA -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/fifo_ren -add wave -noupdate -group DMA -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/header -add wave -noupdate -group DMA -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/header_val -add wave -noupdate -group DMA -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/header_ack -add wave -noupdate -expand -group APB_s -add wave -noupdate -group APB_s -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/apbi -add wave -noupdate -group APB_s -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/apbo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/state -add wave -noupdate -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/send_matrix -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/matrix_type -add wave -noupdate -format Logic /testbench/d3/lpp_dma_1/status_ready_matrix_f0_0 -add wave -noupdate -format Logic /testbench/d3/lpp_dma_1/status_ready_matrix_f0_1 -add wave -noupdate -format Logic /testbench/d3/lpp_dma_1/status_ready_matrix_f1 -add wave -noupdate -format Logic /testbench/d3/lpp_dma_1/status_ready_matrix_f2 -add wave -noupdate -format Literal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/addr_matrix_f0_0 -add wave -noupdate -format Literal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/addr_matrix_f0_1 -add wave -noupdate -format Literal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/addr_matrix_f1 -add wave -noupdate -format Literal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/addr_matrix_f2 -add wave -noupdate -divider FIFO_DMA_TEST -add wave -noupdate -group APB -add wave -noupdate -group APB -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/apbi -add wave -noupdate -group APB -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/apbo -add wave -noupdate -group fifo -add wave -noupdate -group fifo -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/fifo_data -add wave -noupdate -group fifo -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/fifo_empty -add wave -noupdate -group fifo -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/fifo_ren -add wave -noupdate -group header -add wave -noupdate -group header -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/header -add wave -noupdate -group header -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/header_val -add wave -noupdate -group header -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/header_ack -add wave -noupdate -group lpp_DMA_APB_REGISTER -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/pindex -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/paddr -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/pmask -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/pirq -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/hclk -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/hresetn -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.paddr(7) -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.paddr(6) -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.paddr(5) -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.paddr(4) -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.paddr(3) -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.paddr(2) -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.penable -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.psel(4) -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.pwrite -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbi.paddr(7) -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/error_bad_component_error -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/ready_matrix_f0_0 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/ready_matrix_f0_1 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/ready_matrix_f1 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/ready_matrix_f2 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/error_anticipating_empty_fifo -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/reg -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/prdata -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/status_ready_matrix_f0_1 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/status_ready_matrix_f1 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/status_ready_matrix_f2 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/status_error_anticipating_empty_fifo -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/status_error_bad_component_error -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/config_active_interruption_onnewmatrix -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/config_active_interruption_onerror -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/addr_matrix_f0_0 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/addr_matrix_f0_1 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/addr_matrix_f1 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/addr_matrix_f2 -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/apbo -add wave -noupdate -group lpp_DMA_APB_REGISTER -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_apbreg_2/status_ready_matrix_f0_0 -add wave -noupdate -group fifo_test_out -add wave -noupdate -group fifo_test_out -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/full -add wave -noupdate -group fifo_test_out -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/rdata -add wave -noupdate -group fifo_test_out -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/empty -add wave -noupdate -group fifo_test_out -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/raddr -add wave -noupdate -group fifo_test_out -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/waddr -add wave -noupdate -group fifo_test_in -add wave -noupdate -group fifo_test_in -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/tech -add wave -noupdate -group fifo_test_in -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/enable_reuse -add wave -noupdate -group fifo_test_in -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/datasz -add wave -noupdate -group fifo_test_in -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/abits -add wave -noupdate -group fifo_test_in -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/rstn -add wave -noupdate -group fifo_test_in -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/reuse -add wave -noupdate -group fifo_test_in -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/rclk -add wave -noupdate -group fifo_test_in -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/ren -add wave -noupdate -group fifo_test_in -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/wdata -add wave -noupdate -group fifo_test_in -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/wen -add wave -noupdate -group fifo_test_in -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/wclk -add wave -noupdate -group fifo_test_internal -add wave -noupdate -group fifo_test_internal -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/sempty -add wave -noupdate -group fifo_test_internal -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/waddr_vect_d -add wave -noupdate -group fifo_test_internal -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/raddr_vect -add wave -noupdate -group fifo_test_internal -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/waddr_vect -add wave -noupdate -group fifo_test_internal -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/swen -add wave -noupdate -group fifo_test_internal -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/sfull -add wave -noupdate -group fifo_test_internal -format Literal -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/raddr_vect_d -add wave -noupdate -group fifo_test_internal -format Logic -radix hexadecimal /testbench/d3/fifo_test_dma_1/lpp_fifo_i/sren -add wave -noupdate -group DMA_BURST_16w -add wave -noupdate -group DMA_BURST_16w -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/hclk -add wave -noupdate -group DMA_BURST_16w -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/hresetn -add wave -noupdate -group DMA_BURST_16w -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/dmain -add wave -noupdate -group DMA_BURST_16w -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/dmaout -add wave -noupdate -group DMA_BURST_16w -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/send -add wave -noupdate -group DMA_BURST_16w -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/address -add wave -noupdate -group DMA_BURST_16w -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/data -add wave -noupdate -group DMA_BURST_16w -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/ren -add wave -noupdate -group DMA_BURST_16w -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/send_ok -add wave -noupdate -group DMA_BURST_16w -format Logic -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/send_ko -add wave -noupdate -group DMA_BURST_16w -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/state -add wave -noupdate -group DMA_BURST_16w -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/data_counter -add wave -noupdate -group DMA_BURST_16w -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/lpp_dma_send_16word_1/grant_counter -add wave -noupdate -group FIFO_LATENCY_CORRECTION -add wave -noupdate -group FIFO_LATENCY_CORRECTION -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/hclk -add wave -noupdate -group FIFO_LATENCY_CORRECTION -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/hresetn -add wave -noupdate -group FIFO_LATENCY_CORRECTION -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/fifo_ren_s -add wave -noupdate -group fifo_part -add wave -noupdate -group fifo_part -format Literal -radix hexadecimal /testbench/d3/fifo_latency_correction_1/fifo_data -add wave -noupdate -group fifo_part -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/fifo_empty -add wave -noupdate -group fifo_part -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/fifo_ren -add wave -noupdate -group dma_part -add wave -noupdate -group dma_part -format Literal -radix hexadecimal /testbench/d3/fifo_latency_correction_1/dma_data -add wave -noupdate -group dma_part -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/dma_empty -add wave -noupdate -group dma_part -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/dma_ren -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/header -add wave -noupdate -format Literal /testbench/d3/lpp_dma_1/matrix_type -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/lpp_dma_1/component_type -add wave -noupdate -format Literal /testbench/d3/lpp_dma_1/component_type_pre -add wave -noupdate -expand -group {LATENCY CORRECTION} -add wave -noupdate -group {LATENCY CORRECTION} -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/hclk -add wave -noupdate -group {LATENCY CORRECTION} -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/hresetn -add wave -noupdate -group {LATENCY CORRECTION} -group FIFO -add wave -noupdate -group {LATENCY CORRECTION} -format Literal -radix hexadecimal /testbench/d3/fifo_latency_correction_1/fifo_data -add wave -noupdate -group {LATENCY CORRECTION} -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/fifo_ren_s -add wave -noupdate -group {LATENCY CORRECTION} -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/ren_s2 -add wave -noupdate -group {LATENCY CORRECTION} -group S1 -add wave -noupdate -group {LATENCY CORRECTION} -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/valid_s1 -add wave -noupdate -group {LATENCY CORRECTION} -group S2 -add wave -noupdate -group {LATENCY CORRECTION} -format Logic -radix hexadecimal /testbench/d3/fifo_latency_correction_1/valid_s2 -add wave -noupdate -group {LATENCY CORRECTION} -group DMA -add wave -noupdate -group {LATENCY CORRECTION} -format Literal -radix hexadecimal /testbench/d3/fifo_latency_correction_1/dma_data -add wave -noupdate -expand -group CY7C1360C -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/izz -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/imode -add wave -noupdate -group CY7C1360C -format Literal /testbench/cy7c1360c_2/iaddr -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/ingw -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inbwe -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inbwd -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inbwc -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inbwb -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inbwa -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/ince1 -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/ice2 -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/ince3 -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inadsp -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inadsc -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inadv -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/inoe -add wave -noupdate -group CY7C1360C -format Logic /testbench/cy7c1360c_2/iclk -add wave -noupdate -group CY7C1360C -format Literal /testbench/cy7c1360c_2/iodq -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {178173000 ps} 0} -configure wave -namecolwidth 471 -configure wave -valuecolwidth 117 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {0 ps} {3975227550 ps} diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/wave_waveform_picker.do +++ /dev/null @@ -1,364 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /tb_data_acquisition/sample_f0_wen -add wave -noupdate /tb_data_acquisition/sample_f0_wdata -add wave -noupdate /tb_data_acquisition/sample_f1_wen -add wave -noupdate /tb_data_acquisition/sample_f1_wdata -add wave -noupdate /tb_data_acquisition/sample_f2_wen -add wave -noupdate /tb_data_acquisition/sample_f2_wdata -add wave -noupdate /tb_data_acquisition/sample_f3_wen -add wave -noupdate /tb_data_acquisition/sample_f3_wdata -add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_in -add wave -noupdate -group TOP /tb_data_acquisition/ahb_master_out -add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0 -add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t -add wave -noupdate -group TOP /tb_data_acquisition/coarse_time_0_t2 -add wave -noupdate -group TOP /tb_data_acquisition/delta_snapshot -add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f1 -add wave -noupdate -group TOP /tb_data_acquisition/delta_f2_f0 -add wave -noupdate -group TOP /tb_data_acquisition/enable_f0 -add wave -noupdate -group TOP /tb_data_acquisition/enable_f1 -add wave -noupdate -group TOP /tb_data_acquisition/enable_f2 -add wave -noupdate -group TOP /tb_data_acquisition/enable_f3 -add wave -noupdate -group TOP /tb_data_acquisition/burst_f0 -add wave -noupdate -group TOP /tb_data_acquisition/burst_f1 -add wave -noupdate -group TOP /tb_data_acquisition/burst_f2 -add wave -noupdate -group TOP /tb_data_acquisition/nb_snapshot_param -add wave -noupdate -group TOP /tb_data_acquisition/status_full -add wave -noupdate -group TOP /tb_data_acquisition/status_full_ack -add wave -noupdate -group TOP /tb_data_acquisition/status_full_err -add wave -noupdate -group TOP /tb_data_acquisition/status_new_err -add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f0 -add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f1 -add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f2 -add wave -noupdate -group TOP /tb_data_acquisition/addr_data_f3 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_size -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param_size -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot_size -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0_size -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1_size -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/clk -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/rstn -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_in -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/ahb_master_out -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/coarse_time_0 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_snapshot -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f1 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/delta_f2_f0 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f0 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f1 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f2 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/enable_f3 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f0 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f1 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/burst_f2 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/nb_snapshot_param -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_ack -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_full_err -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f0 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f1 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f2 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/addr_data_f3 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_in_valid -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_in_valid -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_in_valid -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_in_valid -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f0 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f1 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/start_snapshot_f2 -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f0_out_valid -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f1_out_valid -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f2_out_valid -add wave -noupdate -group waveform_picker /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/data_f3_out_valid -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/clk -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/rstn -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_snapshot -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f1 -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/delta_f2_f0 -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0 -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_in_valid -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot -add wave -noupdate -group waveform_controler /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_controler_1/coarse_time_0_r -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/clk -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/rstn -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/enable -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/nb_snapshot_param -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_in_valid -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid -add wave -noupdate -group waveform_snapshot_f0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f0/counter_points_snapshot -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/clk -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/rstn -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/enable -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/burst_enable -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/nb_snapshot_param -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/start_snapshot -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_in_valid -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid -add wave -noupdate -group waveform_snapshot_f1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f1/counter_points_snapshot -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/clk -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/rstn -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/enable -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/burst_enable -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/nb_snapshot_param -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/start_snapshot -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_in_valid -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid -add wave -noupdate -group waveform_snapshot_f2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_snapshot_f2/counter_points_snapshot -add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/clk -add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/rstn -add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/enable -add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in -add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_in_valid -add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out -add wave -noupdate -group waveform_burst____f3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_burst_f3/data_out_valid -add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hclk -add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/hresetn -add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_in -add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/ack_in -add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/valid_out -add wave -noupdate -group GEN_VALID_F0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(0)/lpp_waveform_dma_gen_valid_i/error -add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hclk -add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/hresetn -add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_in -add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/ack_in -add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/valid_out -add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/error -add wave -noupdate -group GEN_VALID_F1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(1)/lpp_waveform_dma_gen_valid_i/state -add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hclk -add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/hresetn -add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_in -add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/ack_in -add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/valid_out -add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/error -add wave -noupdate -group GEN_VALID_F2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(2)/lpp_waveform_dma_gen_valid_i/state -add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hclk -add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/hresetn -add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_in -add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/ack_in -add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/valid_out -add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/error -add wave -noupdate -group GEN_VALID_F3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/all_input_valid(3)/lpp_waveform_dma_gen_valid_i/state -add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_in -add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_out -add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/valid_ack -add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/status_new_err -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/clk -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/rstn -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/state -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0_valid -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1_valid -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2_valid -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3_valid -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_ack -add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f0 -add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f1 -add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f2 -add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_f3 -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/ready -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_wen -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_wen -add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_and_ready -add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_selected -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_valid_selected -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_ready_to_go -add wave -noupdate -group FIFO_ARB -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/data_temp -add wave -noupdate -group FIFO_ARB /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_arbiter_1/time_en_temp -add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rstn -add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ready -add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_ren -add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_ren -add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/rdata -add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_wen -add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_wen -add wave -noupdate -expand -group FIFO -expand -group {IN - OUT} -radix hexadecimal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wdata -add wave -noupdate -expand -group FIFO -expand -group read -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(3) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(2) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(1) {-radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r(0) {-radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_r -add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_r -add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_ren -add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_ren -add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_r -add wave -noupdate -expand -group FIFO -expand -group read /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren -add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_addr_w -add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_addr_w -add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_mem_wen -add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/time_mem_wen -add wave -noupdate -expand -group FIFO -group write -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/data_addr_w -add wave -noupdate -expand -group FIFO -group write /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen -add wave -noupdate -radix hexadecimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd -add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hclk -add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/hresetn -add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_in -add wave -noupdate -expand -group DMA -expand -group INOUT -subitemconfig {/tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/ahb_master_out -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ready -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_data_ren -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group FIFO_interface /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_time_ren -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG -radix unsigned /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/nb_burst_available -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f0 -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f1 -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f2 -add wave -noupdate -expand -group DMA -expand -group INOUT -expand -group REG_CONFIG /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_f3 -add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full -add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_ack -add wave -noupdate -expand -group DMA -expand -group INOUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/status_full_err -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmain -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/dmaout -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/state -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data_s -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/sel_data -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_select -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_write -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_already_send_s -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_dmai -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ok -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_send_ko -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_fifo_ren -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/time_ren -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_dmai -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ok -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_send_ko -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_fifo_ren -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_ren -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/data_address -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/update_and_sel -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_reg_vector -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/addr_data_vector -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/send_16_3_time -add wave -noupdate -expand -group DMA /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/pp_waveform_dma_1/count_send_time -add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/ren -add wave -noupdate /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/wen -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/clk -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/rstn -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ren -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/wen -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_re -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_we -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_ren -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/mem_addr_wen -add wave -noupdate -group fifo_ctrl_time_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(3)/lpp_waveform_fifo_ctrl_time/ready -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/clk -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/rstn -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ren -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/wen -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_re -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_we -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_ren -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/mem_addr_wen -add wave -noupdate -expand -group fifo_ctrl_time_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(2)/lpp_waveform_fifo_ctrl_time/ready -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/clk -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/rstn -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ren -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/wen -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_re -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_we -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_ren -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/mem_addr_wen -add wave -noupdate -expand -group fifo_ctrl_time_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(1)/lpp_waveform_fifo_ctrl_time/ready -add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk -add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn -add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren -add wave -noupdate -group fifo_ctrl_time_0 -group IN /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen -add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re -add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we -add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren -add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen -add wave -noupdate -group fifo_ctrl_time_0 -group OUT /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sfull_s -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty_s -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sempty -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sren -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swen -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/sre -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/swe -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/waddr_vect_s -add wave -noupdate -group fifo_ctrl_time_0 -group internal /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/raddr_vect_s -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/clk -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/rstn -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ren -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/wen -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_re -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_we -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_ren -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/mem_addr_wen -add wave -noupdate -group fifo_ctrl_time_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_time(0)/lpp_waveform_fifo_ctrl_time/ready -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/clk -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/rstn -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ren -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/wen -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_re -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_we -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_ren -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/mem_addr_wen -add wave -noupdate -group fifo_ctrl_data_3 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/ready -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/clk -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/rstn -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ren -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/wen -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_re -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_we -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_ren -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/mem_addr_wen -add wave -noupdate -expand -group fifo_ctrl_data_2 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/ready -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/clk -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/rstn -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ren -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/wen -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_re -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_we -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_ren -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/mem_addr_wen -add wave -noupdate -group fifo_ctrl_data_1 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/ready -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/clk -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/rstn -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ren -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/wen -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_re -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_we -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_ren -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/mem_addr_wen -add wave -noupdate -group fifo_ctrl_data_0 /tb_data_acquisition/top_data_acquisition_2/lpp_waveform_1/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/ready -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {70458134452 ps} 0} -configure wave -namecolwidth 842 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {70455153866 ps} {70464281299 ps} diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/CY7C1360C.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/CY7C1360C.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/CY7C1360C.vhd +++ /dev/null @@ -1,561 +0,0 @@ ---*************************************************************************************** --- --- File Name: CY7C1360C.vhd --- Version: 1.0 --- Date: Aug 8th, 2005 --- Model: BUS Functional --- Simulator: Modelsim --- --- --- Queries: MPD Applications --- Website: www.cypress.com/support --- Company: Cypress Semiconductor --- Part #: CY7C1360C (256K x 36) --- --- Description: Cypress 9Mb Synburst SRAM (Pipelined SCD) --- --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright(c) Cypress Semiconductor, 2004 --- All rights reserved --- --- Rev Date Changes --- --- ---------- --------------------------------------- --- 1.0 12/22/2004 - New Model --- - New Test Bench --- - New Test Vectors --- ---*************************************************************************************** - --- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz - -LIBRARY ieee,work; - USE ieee.std_logic_1164.all; - USE ieee.std_logic_unsigned.all; - Use IEEE.Std_Logic_Arith.all; - USE work.package_utility.all; - -entity CY7C1360C is - GENERIC ( - -- Constant Parameters - addr_bits : INTEGER := 18; -- This is external address - data_bits : INTEGER := 36; - - ---Clock timings for 250Mhz - Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise - - Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time - Cyp_tCH : TIME := 1.8 ns; -- Clock HIGH time - Cyp_tCL : TIME := 1.8 ns; -- Clock LOW time - - Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z - Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z - Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z - Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z - Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid - - Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise - Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise - Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise - Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise - Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise - Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up - - Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise - Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise - Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise - Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise - Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise - Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise - ---Clock timings for 200Mhz --- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise - --- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time --- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time --- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time - --- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z --- Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z --- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z --- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z --- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid - --- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise --- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise --- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise --- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise --- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise --- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up - --- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise --- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise --- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise --- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise --- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise --- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise - ---Clock timings for 166Mhz --- Cyp_tCO : TIME := 3.5 ns; -- Data Output Valid After CLK Rise - --- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time --- Cyp_tCH : TIME := 2.4 ns; -- Clock HIGH time --- Cyp_tCL : TIME := 2.4 ns; -- Clock LOW time - --- Cyp_tCHZ : TIME := 3.5 ns; -- Clock to High-Z --- Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z --- Cyp_tOEHZ: TIME := 3.5 ns; -- OE# HIGH to Output High-Z --- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z --- Cyp_tOEV : TIME := 3.5 ns; -- OE# LOW to Output Valid - --- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise --- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise --- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise --- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise --- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise --- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up - --- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise --- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise --- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise --- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise --- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise --- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise - - ); - PORT (iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0); - iCLK : IN STD_LOGIC); - -end CY7C1360C; -ARCHITECTURE CY7C1360C_arch OF CY7C1360C IS - - - - signal Read_reg_o1, Read_reg1 : STD_LOGIC; - signal WrN_reg1 : STD_LOGIC; - signal ADSP_N_o : STD_LOGIC; - signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC; - signal Sys_clk : STD_LOGIC := '0'; - signal test : STD_LOGIC; - signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0); - signal ce : STD_LOGIC; - signal Write_n : STD_LOGIC; - signal Read : STD_LOGIC; - - signal bwa_n1 : STD_LOGIC; - signal bwb_n1 : STD_LOGIC; - signal bwc_n1 : STD_LOGIC; - signal bwd_n1 : STD_LOGIC; - - signal latch_addr : STD_LOGIC; - signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0); - - signal OeN_HZ : STD_LOGIC; - signal OeN_DataValid : STD_LOGIC; - signal OeN_efct : STD_LOGIC; - - signal WR_HZ : STD_LOGIC; - signal WR_LZ : STD_LOGIC; - signal WR_efct : STD_LOGIC; - - signal CE_HZ : STD_LOGIC; - signal CE_LZ : STD_LOGIC; - signal Pipe_efct : STD_LOGIC; - - signal RD_HZ : STD_LOGIC; - signal RD_LZ : STD_LOGIC; - signal RD_efct : STD_LOGIC; - -begin - - ce <= ((not inCE1) and (iCE2) and (not inCE3)); - Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW)); - Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce)); - bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa)))); - bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb)))); - bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc)))); - bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd)))); - latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1))); - OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ; - WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ; - Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ; - RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ; - - - Process (Read_reg_o1) - begin - if (Read_reg_o1 = '0') then - RD_HZ <= '0' after Cyp_tCHZ; - RD_LZ <= '0' after Cyp_tCLZ; - elsif (Read_reg_o1 = '1') then - RD_HZ <= '1' after Cyp_tCHZ; - RD_LZ <= '1' after Cyp_tCLZ; - else - RD_HZ <= 'X' after Cyp_tCHZ; - RD_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - - - Process (pipe_reg1) - begin - if (pipe_reg1 = '1') then - CE_LZ <= '1' after Cyp_tCLZ; - elsif (pipe_reg1 = '0') then - CE_LZ <= '0' after Cyp_tCLZ; - else - CE_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - -- System Clock Decode - Process (iclk) - variable Sys_clk1 : std_logic := '0'; - begin - if (rising_edge (iclk)) then - Sys_clk1 := not iZZ; - end if; - if (falling_edge (iCLK)) then - Sys_clk1 := '0'; - end if; - Sys_clk <= Sys_clk1; - end process; - - - - Process (WrN_reg1) - begin - if (WrN_reg1 = '1') then - WR_HZ <= '1' after Cyp_tCHZ; - WR_LZ <= '1' after Cyp_tCLZ; - elsif (WrN_reg1 = '0') then - WR_HZ <= '0' after Cyp_tCHZ; - WR_LZ <= '0' after Cyp_tCLZ; - else - WR_HZ <= 'X' after Cyp_tCHZ; - WR_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - Process (inOE) - begin - if (inOE = '1') then - OeN_HZ <= '1' after Cyp_tOEHZ; - OeN_DataValid <= '1' after Cyp_tOEV; - elsif (inOE = '0') then - OeN_HZ <= '0' after Cyp_tOEHZ; - OeN_DataValid <= '0' after Cyp_tOEV; - else - OeN_HZ <= 'X' after Cyp_tOEHZ; - OeN_DataValid <= 'X' after Cyp_tOEV; - end if; - end process; - - process (ce_reg1, pipe_reg1) - begin - if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then - CE_HZ <= '0' after Cyp_tCHZ; - elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then - CE_HZ <= '1' after Cyp_tCHZ; - else - CE_HZ <= 'X' after Cyp_tCHZ; - end if; - end process; - - Process (Sys_clk) - TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0); - variable Read_reg_o : std_logic; - variable Read_reg : std_logic; - variable pcsr_write, ctlr_write : std_logic; - variable WrN_reg : std_logic; - variable latch_addr_old, latch_addr_current : std_logic; - variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0'); - variable bcount, first_addr : std_logic_vector (1 downto 0) := "00"; - variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic; - variable din : std_logic_vector (data_bits-1 downto 0); - variable first_addr_int : integer; - variable bank0 : memory_array; - variable bank1 : memory_array; - variable bank2 : memory_array; - variable bank3 : memory_array; - - begin - if rising_edge (Sys_clk) then - - if (Write_n = '0') then - Read_reg_o := '0'; - else - Read_reg_o := Read_reg; - end if; - - if (Write_n = '0') then - Read_reg := '0'; - else - Read_reg := Read; - end if; - Read_reg1 <= Read_reg; - Read_reg_o1 <= Read_reg_o; - - if (Read_reg = '1') then - pcsr_write := '0'; - ctlr_write := '0'; - end if; - - -- Write Register - - if (Read_reg_o = '1') then - WrN_reg := '1'; - else - WrN_reg := Write_n; - end if; - WrN_reg1 <= WrN_reg; - - latch_addr_old := latch_addr_current; - latch_addr_current := latch_addr; - - if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then - pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1; - - elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then - ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1; - end if; - -- ADDRess Register - if (latch_addr = '1') then - addr_reg_in := iADDR; - bcount := iADDR (1 downto 0); - first_addr := iADDR (1 downto 0); - end if; - addr_reg_in1 <= addr_reg_in; - -- ADSP_N Previous-Cycle Register - ADSP_N_o <= inADSP; - pcsr_write1 <= pcsr_write; - ctlr_write1 <= ctlr_write; - first_addr_int := CONV_INTEGER1 (first_addr); - -- Binary Counter and Logic - - if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst - bcount := (bcount + '1'); -- Advance Counter - - elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst - if ((first_addr_int REM 2) = 0) then - bcount := (bcount + '1'); -- Increment Counter - elsif ((first_addr_int REM 2) = 1) then - bcount := (bcount - '1'); -- Decrement Counter - end if; - end if; - - -- Read ADDRess - addr_reg_read := addr_reg_write; - addr_reg_read1 <= addr_reg_read; - - -- Write ADDRess - addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0); - addr_reg_write1 <= addr_reg_write; - -- Byte Write Register - bwa_reg := not bwa_n1; - bwb_reg := not bwb_n1; - bwc_reg := not bwc_n1; - bwd_reg := not bwd_n1; - - -- Enable Register - pipe_reg := ce_reg; - - -- Enable Register - if (latch_addr = '1') then - ce_reg := ce; - end if; - - pipe_reg1 <= pipe_reg; - ce_reg1 <= ce_reg; - - -- Input Register - if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and - ((pcsr_write = '1') or (ctlr_write = '1'))) then - din := ioDQ; - end if; - din1 <= din; - - -- Byte Write Driver - if ((ce_reg = '1') and (bwa_reg = '1')) then - bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0); - end if; - if ((ce_reg = '1') and (bwb_reg = '1')) then - bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9); - end if; - if ((ce_reg = '1') and (bwc_reg = '1')) then - bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18); - end if; - if ((ce_reg = '1') and (bwd_reg = '1')) then - bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27); - end if; - - -- Output Registers - - if ((Write_n = '0') or (pipe_reg = '0')) then - dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ; - elsif (Read_reg_o = '1') then - dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - end if; - - end if; - end process; - - -- Output Buffers - ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1')) - else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; - - - clk_check : PROCESS - VARIABLE clk_high, clk_low : TIME := 0 ns; - BEGIN - WAIT ON iClk; - IF iClk = '1' AND NOW >= Cyp_tCYC THEN - ASSERT (NOW - clk_low >= Cyp_tCH) - REPORT "Clk width low - tCH violation" - SEVERITY ERROR; - ASSERT (NOW - clk_high >= Cyp_tCYC) - REPORT "Clk period high - tCYC violation" - SEVERITY ERROR; - clk_high := NOW; - ELSIF iClk = '0' AND NOW /= 0 ns THEN - ASSERT (NOW - clk_high >= Cyp_tCL) - REPORT "Clk width high - tCL violation" - SEVERITY ERROR; - ASSERT (NOW - clk_low >= Cyp_tCYC) - REPORT "Clk period low - tCYC violation" - SEVERITY ERROR; - clk_low := NOW; - END IF; - END PROCESS; - - -- Check for Setup Timing Violation - setup_check : PROCESS - BEGIN - WAIT ON iClk; - IF iClk = '1' THEN - ASSERT (iAddr'LAST_EVENT >= Cyp_tAS) - REPORT "Addr - tAS violation" - SEVERITY ERROR; - ASSERT (inGW'LAST_EVENT >= Cyp_tWES) - REPORT "GW# - tWES violation" - SEVERITY ERROR; - ASSERT (inBWE'LAST_EVENT >= Cyp_tWES) - REPORT "BWE# - tWES violation" - SEVERITY ERROR; - ASSERT (inCe1'LAST_EVENT >= Cyp_tWES) - REPORT "CE1# - tWES violation" - SEVERITY ERROR; - ASSERT (iCe2'LAST_EVENT >= Cyp_tWES) - REPORT "CE2 - tWES violation" - SEVERITY ERROR; - ASSERT (inCe3'LAST_EVENT >= Cyp_tWES) - REPORT "CE3# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS) - REPORT "ADV# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS) - REPORT "ADSP# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS) - REPORT "ADSC# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwa'LAST_EVENT >= Cyp_tWES) - REPORT "BWa# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwb'LAST_EVENT >= Cyp_tWES) - REPORT "BWb# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwc'LAST_EVENT >= Cyp_tWES) - REPORT "BWc# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwd'LAST_EVENT >= Cyp_tWES) - REPORT "BWd# - tWES violation" - SEVERITY ERROR; - ASSERT (ioDq'LAST_EVENT >= Cyp_tDS) - REPORT "Dq - tDS violation" - SEVERITY ERROR; - END IF; - END PROCESS; - - -- Check for Hold Timing Violation - hold_check : PROCESS - BEGIN - WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH); - IF iClk'DELAYED(Cyp_tAH) = '1' THEN - ASSERT (iAddr'LAST_EVENT > Cyp_tAH) - REPORT "Addr - tAH violation" - SEVERITY ERROR; - END IF; - IF iClk'DELAYED(Cyp_tDH) = '1' THEN - ASSERT (ioDq'LAST_EVENT > Cyp_tDH) - REPORT "Dq - tDH violation" - SEVERITY ERROR; - END IF; - IF iClk'DELAYED(Cyp_tWEH) = '1' THEN - ASSERT (inCe1'LAST_EVENT > Cyp_tWEH) - REPORT "CE1# - tWEH violation" - SEVERITY ERROR; - ASSERT (iCe2'LAST_EVENT > Cyp_tWEH) - REPORT "CE2 - tWEH violation" - SEVERITY ERROR; - ASSERT (inCe3'LAST_EVENT > Cyp_tWEH) - REPORT "CE3 - tWEH violation" - SEVERITY ERROR; - ASSERT (inAdv'LAST_EVENT > Cyp_tWEH) - REPORT "ADV# - tWEH violation" - SEVERITY ERROR; - ASSERT (inADSP'LAST_EVENT > Cyp_tWEH) - REPORT "ADSP# - tWEH violation" - SEVERITY ERROR; - ASSERT (inADSC'LAST_EVENT > Cyp_tWEH) - REPORT "ADSC# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwa'LAST_EVENT > Cyp_tWEH) - REPORT "BWa# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwb'LAST_EVENT > Cyp_tWEH) - REPORT "BWb# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwc'LAST_EVENT > Cyp_tWEH) - REPORT "BWc# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwd'LAST_EVENT > Cyp_tWEH) - REPORT "BWd# - tWEH violation" - SEVERITY ERROR; - END IF; - - END PROCESS; -end CY7C1360C_arch; - - - - - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/package_utility.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/package_utility.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/package_utility.vhd +++ /dev/null @@ -1,73 +0,0 @@ ---**************************************************************** ---** MODEL : package_utility ** ---** COMPANY : Cypress Semiconductor ** ---** REVISION: 1.0 Created new package utility model ** ---** ** ---**************************************************************** -Library ieee,work; - Use ieee.std_logic_1164.all; - Use IEEE.Std_Logic_Arith.all; - Use IEEE.std_logic_TextIO.all; - --- Use work.package_timing.all; - -Library Std; - Use STD.TextIO.all; - -Package package_utility is - -FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR; -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER; - -End; -- package package_utility - -Package body package_utility is - - ------------------------------------------------------------------------------------------------- ---Converts string into std_logic_vector ------------------------------------------------------------------------------------------------- - -FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS - VARIABLE result : STD_LOGIC_VECTOR(S'RANGE); - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '0' THEN - result(i) := '0'; - ELSIF S(i) = '1' THEN - result(i) := '1'; - ELSIF S(i) = 'X' THEN - result(i) := 'X'; - ELSE - result(i) := 'Z'; - END IF; - END LOOP; - RETURN result; -END convert_string; - ------------------------------------------------------------------------------------------------- ---Converts std_logic_vector into integer ------------------------------------------------------------------------------------------------- - -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS - VARIABLE result : INTEGER := 0; - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '1' THEN - result := result + (2**i); - ELSIF S(i) = '0' THEN - result := result; - ELSE - result := 0; - END IF; - END LOOP; - RETURN result; - END CONV_INTEGER1; - - - - -end package_utility; - - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/tb.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/tb.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/CY7C1360C/tb.vhd +++ /dev/null @@ -1,369 +0,0 @@ ---*************************************************************************************** --- --- File Name: tb.vhd --- Version: 1.0 --- Date: Aug 8th, 2005 --- Simulator: Modelsim --- --- --- Queries: MPD Applications --- Website: www.cypress.com/support --- Company: Cypress Semiconductor --- Part #: testbench for CY7C1360C (256K x 36) --- --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright(c) Cypress Semiconductor, 2004 --- All rights reserved --- --- Rev Date Changes --- --- ---------- --------------------------------------- --- 1.0 12/22/2004 - New Model --- - New Test Bench --- - New Test Vectors --- ---*************************************************************************************** - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE std.textio.ALL; -USE ieee.std_logic_textio.ALL; - - -ENTITY tb IS -END tb; - -architecture tb_arch of tb is - - CONSTANT addr_bits : INTEGER := 18; - CONSTANT data_bits : INTEGER := 36; - - CONSTANT tx01 : TIME := 2.2 ns; -- 0.0 ns to 1.8 ns - - - COMPONENT CY7C1360C - PORT (iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0); - iCLK : IN STD_LOGIC); - END COMPONENT; - --------------------------------------------------------------------------- --- Function: to_slv --- --- Description: Converts string to std_logic_vector --------------------------------------------------------------------------- -function to_slv(value : in string) return std_logic_vector is -variable outvec : std_logic_vector(value'length -1 downto 0); -variable i : integer; -variable temp : character; -begin - for i in 1 to value'length loop - - temp := value(i); - - case temp is - when '0' => outvec(i-1) := '0'; - when '1' => outvec(i-1) := '1'; - when 'X' => outvec(i-1) := 'X'; - when 'Z' => outvec(i-1) := 'Z'; - when others => - assert false report "Illegal characters" severity note; - - end case; - end loop; - return outvec; -end to_slv; - --------------------------------------------------------------------------- --- Function: to_slv_char --- --- Description: Converts character to std_logic_vector --------------------------------------------------------------------------- -function to_slv_char(value : in character) return std_logic is -variable outvec_char : std_logic; - -begin - - case value is - when '0' => outvec_char := '0'; - when '1' => outvec_char := '1'; - when 'X' => outvec_char := 'X'; - when 'Z' => outvec_char := 'Z'; - when others => - assert false report "Illegal characters" severity note; - - end case; - - return outvec_char; -end to_slv_char; --------------------------------------------------------------------------- - --------------------------------------------------------------------------- --- Function: to_string --- --- Description: Converts time to string --------------------------------------------------------------------------- -function to_string (value : in integer) return string is -variable L : line; - -begin - write(L, value, RIGHT, 10); - return L.all; -end to_string; --------------------------------------------------------------------------- - - - FOR ALL: CY7C1360C USE ENTITY WORK.CY7C1360C(CY7C1360C_arch); - - SIGNAL DQ : STD_LOGIC_VECTOR((data_bits-1) DOWNTO 0); - SIGNAL Addr : STD_LOGIC_VECTOR((addr_bits-1) DOWNTO 0) := (OTHERS => '0'); - SIGNAL ZZ, clk : STD_LOGIC := '0'; - SIGNAL Mode : STD_LOGIC := '0'; - SIGNAL BWE_n : STD_LOGIC := '1'; - SIGNAL BWd_n : STD_LOGIC := '1'; - SIGNAL BWc_n : STD_LOGIC := '1'; - SIGNAL BWb_n : STD_LOGIC := '1'; - SIGNAL BWa_n : STD_LOGIC := '1'; - SIGNAL GW_n : STD_LOGIC := '1'; - signal CE1_n : STD_LOGIC := '1'; - signal CE2 : STD_LOGIC := '0'; - SIGNAL CE3_n : STD_LOGIC := '1'; - signal ADSP_n : STD_LOGIC := '1'; - signal ADSC_n : STD_LOGIC := '1'; - signal ADV_n : STD_LOGIC := '1'; - signal OE_n : STD_LOGIC := '1'; - signal count : integer := 0; - signal chkout : std_logic := '0'; - signal testin_tmp_slv : std_logic_vector ((data_bits-1) downto 0) := (others => '0'); - signal strb : std_logic := '0'; - signal temp : std_logic := '1'; - signal D : STD_LOGIC_VECTOR((data_bits-1) DOWNTO 0) := (OTHERS => '0'); - signal read_write : std_logic; - signal trigger : std_logic := '0'; -begin - - - - - -- Unit Under Test port map - UUT : CY7C1360C - PORT MAP (ioDq => Dq, - iAddr => Addr, - iClk => Clk, - iMode => Mode, - inAdv => Adv_n, - inBwa => Bwa_n, - inBwb => Bwb_n, - inBwc => Bwc_n, - inBwd => Bwd_n, - inOE => OE_n, - inCE1 => CE1_n, - inCE3 => CE3_n, - iCE2 => CE2, - inADSP => ADSP_n, - inADSC => ADSC_n, - inGW => GW_n, - inBWE => BWE_n, - iZZ => Zz - ); - -Process - begin - trigger <= '1' after 4 ns; - wait; -end process; - - with trigger select - strb <= not strb after 4.4 ns when '1', - '0' when others; --clock - -process(strb) - begin - clk <= strb after tx01; - end process; - -process - -variable l : line; -variable A_tmp : string (5 downto 1); -variable zz_tmp : character; -variable mode_tmp : character; -variable gw_tmp : character; -variable bwe_tmp : character; -variable bw_tmp : string (4 downto 1); -variable ce1_n_tmp : character; -variable ce2_tmp : character; -variable ce3_n_tmp : character; -variable adsp_n_tmp : character; -variable adsc_n_tmp : character; -variable adv_n_tmp : character; -variable oeb_tmp : character; -variable testout_tmp1, testout_tmp2, testout_tmp3, testout_tmp4 : string (9 downto 1); -variable testin_tmp1, testin_tmp2, testin_tmp3, testin_tmp4 : string (9 downto 1); -variable A_tmp_slv : STD_LOGIC_VECTOR (4 downto 0); -variable zz_tmp_slv : STD_LOGIC; -variable mode_tmp_slv : STD_LOGIC; -variable gw_tmp_slv : STD_LOGIC; -variable bwe_tmp_slv : STD_LOGIC; -variable bw_tmp_slv : STD_LOGIC_VECTOR (3 downto 0); -variable ce1_n_tmp_slv : STD_LOGIC; -variable ce2_tmp_slv : STD_LOGIC; -variable ce3_n_tmp_slv : STD_LOGIC; -variable adsp_n_tmp_slv : STD_LOGIC; -variable adsc_n_tmp_slv : STD_LOGIC; -variable adv_n_tmp_slv : STD_LOGIC; -variable oeb_tmp_slv : STD_LOGIC; -variable testout_tmp1_slv,testout_tmp2_slv,testout_tmp3_slv,testout_tmp4_slv : STD_LOGIC_VECTOR (8 downto 0); -variable US: character; -variable linecount: integer; -FILE test_vectors : text is in "SS_PL_SCD_X36_vect.txt"; -- preload file - - -begin - while not endfile(test_vectors) loop - assert false report "Line no" &to_string(count) severity note; - wait until strb = '1'; - readline (test_vectors,l); - read(l,zz_tmp); - read(l,US); - read(l,mode_tmp); - read(l,US); - read(l,A_tmp); - read(l,US); - read(l,gw_tmp); - read(l,US); - read(l,bwe_tmp); - read(l,US); - read(l,bw_tmp); - read(l,US); - read(l,ce1_n_tmp); - read(l,US); - read(l,ce2_tmp); - read(l,US); - read(l,ce3_n_tmp); - read(l,US); - read(l,ADSP_n_tmp); - read(l,US); - read(l,ADSC_n_tmp); - read(l,US); - read(l,ADV_n_tmp); - read(l,US); - read(l,oeb_tmp); - read(l,US); - read(l,testout_tmp1); - read(l,US); - read(l,testout_tmp2); - read(l,US); - read(l,testout_tmp3); - read(l,US); - read(l,testout_tmp4); - read(l,US); - read(l,testin_tmp1); - read(l,US); - read(l,testin_tmp2); - read(l,US); - read(l,testin_tmp3); - read(l,US); - read(l,testin_tmp4); - - - A_tmp_slv (4 downto 0) := to_slv(A_tmp); - zz_tmp_slv := to_slv_char(zz_tmp); - mode_tmp_slv := to_slv_char(mode_tmp); - gw_tmp_slv := to_slv_char(gw_tmp); - bwe_tmp_slv := to_slv_char(bwe_tmp); - bw_tmp_slv (3 downto 0) := to_slv(bw_tmp); - ce1_n_tmp_slv := to_slv_char(ce1_n_tmp); - ce2_tmp_slv := to_slv_char(ce2_tmp); - ce3_n_tmp_slv := to_slv_char(ce3_n_tmp); - ADSP_n_tmp_slv := to_slv_char(ADSP_n_tmp); - ADSC_n_tmp_slv := to_slv_char(ADSC_n_tmp); - ADV_n_tmp_slv := to_slv_char(ADV_n_tmp); - oeb_tmp_slv := to_slv_char(oeb_tmp); - testin_tmp_slv (8 downto 0) <= to_slv(testin_tmp4); - testout_tmp1_slv (8 downto 0) := to_slv(testout_tmp1); - testin_tmp_slv (17 downto 9) <= to_slv(testin_tmp3); - testout_tmp2_slv (8 downto 0) := to_slv(testout_tmp2); - testin_tmp_slv (26 downto 18) <= to_slv(testin_tmp2); - testout_tmp3_slv (8 downto 0) := to_slv(testout_tmp3); - testin_tmp_slv (35 downto 27) <= to_slv(testin_tmp1); - testout_tmp4_slv (8 downto 0) := to_slv(testout_tmp4); - - - Addr <= "0000000000000" & A_tmp_slv; - Mode <= mode_tmp_slv; - Adv_n <= Adv_n_tmp_slv; - Bwa_n <= Bw_tmp_slv (0); - Bwb_n <= Bw_tmp_slv (1); - Bwc_n <= Bw_tmp_slv (2); - Bwd_n <= Bw_tmp_slv (3); - OE_n <= OEb_tmp_slv; - CE1_n <= CE1_n_tmp_slv; - CE3_n <= CE3_n_tmp_slv; - CE2 <= CE2_tmp_slv; - ADSP_n <= ADSP_n_tmp_slv; - ADSC_n <= ADSC_n_tmp_slv; - GW_n <= GW_tmp_slv; - BWE_n <= BWE_tmp_slv; - ZZ <= zz_tmp_slv; - - D (35 downto 27) <= testout_tmp1_slv; - D (26 downto 18) <= testout_tmp2_slv; - D (17 downto 9) <= testout_tmp3_slv; - D (8 downto 0) <= testout_tmp4_slv; - - count <= count +1; - - - end loop; - chkout <= '1'; - wait; -end process; - - -read_write <= '0' when D = "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" else '1'; --1 means write -DQ <= D when read_write = '1' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; - -Process (clk) -begin - if rising_edge (clk) then - if (chkout = '0') then - if (D /= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ") then - assert false report "Write Cycle" severity note; - else - if (DQ(35 downto 0) = testin_tmp_slv(35 downto 0)) then - assert false report "OK" severity note; - else - assert false report "ERROR" severity note; - end if; - end if; - else - assert false report "TEST COMPLETE" severity note; - end if; - end if; -end process; - - -end tb_arch; - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/TB_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/TB_Data_Acquisition.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/TB_Data_Acquisition.vhd +++ /dev/null @@ -1,348 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -------------------------------------------------------------------------------- - -ENTITY TB_Data_Acquisition IS - -END TB_Data_Acquisition; - -------------------------------------------------------------------------------- - -ARCHITECTURE tb OF TB_Data_Acquisition IS - - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - --COMPONENT Top_Data_Acquisition - -- GENERIC ( - -- hindex : INTEGER; - -- nb_burst_available_size : INTEGER := 11; - -- nb_snapshot_param_size : INTEGER := 11; - -- delta_snapshot_size : INTEGER := 16; - -- delta_f2_f0_size : INTEGER := 10; - -- delta_f2_f1_size : INTEGER := 10; - -- tech : integer); - -- PORT ( - -- cnv_run : IN STD_LOGIC; - -- cnv : OUT STD_LOGIC; - -- sck : OUT STD_LOGIC; - -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- cnv_clk : IN STD_LOGIC; - -- cnv_rstn : IN STD_LOGIC; - -- clk : IN STD_LOGIC; - -- rstn : IN STD_LOGIC; - -- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- AHB_Master_In : IN AHB_Mst_In_Type; - -- AHB_Master_Out : OUT AHB_Mst_Out_Type; - -- coarse_time_0 : IN STD_LOGIC; - -- data_shaping_SP0 : IN STD_LOGIC; - -- data_shaping_SP1 : IN STD_LOGIC; - -- data_shaping_R0 : IN STD_LOGIC; - -- data_shaping_R1 : IN STD_LOGIC; - -- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - -- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - -- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - -- enable_f0 : IN STD_LOGIC; - -- enable_f1 : IN STD_LOGIC; - -- enable_f2 : IN STD_LOGIC; - -- enable_f3 : IN STD_LOGIC; - -- burst_f0 : IN STD_LOGIC; - -- burst_f1 : IN STD_LOGIC; - -- burst_f2 : IN STD_LOGIC; - -- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - -- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - -- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - -- component ports - SIGNAL cnv_rstn : STD_LOGIC; - SIGNAL cnv : STD_LOGIC; - SIGNAL rstn : STD_LOGIC; - SIGNAL sck : STD_LOGIC; - SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL run_cnv : STD_LOGIC; - - - -- clock - signal Clk : STD_LOGIC := '1'; - SIGNAL cnv_clk : STD_LOGIC := '1'; - - ----------------------------------------------------------------------------- - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - ----------------------------------------------------------------------------- - CONSTANT nb_burst_available_size : INTEGER := 11; - CONSTANT nb_snapshot_param_size : INTEGER := 11; - CONSTANT delta_snapshot_size : INTEGER := 16; - CONSTANT delta_f2_f0_size : INTEGER := 10; - CONSTANT delta_f2_f1_size : INTEGER := 10; - - SIGNAL AHB_Master_In : AHB_Mst_In_Type; - SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; - - SIGNAL coarse_time_0 : STD_LOGIC; - SIGNAL coarse_time_0_t : STD_LOGIC := '0'; - SIGNAL coarse_time_0_t2 : STD_LOGIC := '0'; - - SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - SIGNAL enable_f0 : STD_LOGIC; - SIGNAL enable_f1 : STD_LOGIC; - SIGNAL enable_f2 : STD_LOGIC; - SIGNAL enable_f3 : STD_LOGIC; - - SIGNAL burst_f0 : STD_LOGIC; - SIGNAL burst_f1 : STD_LOGIC; - SIGNAL burst_f2 : STD_LOGIC; - - SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - - SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - - SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); - - - SIGNAL data_shaping_SP0 : STD_LOGIC; - SIGNAL data_shaping_SP1 : STD_LOGIC; - SIGNAL data_shaping_R0 : STD_LOGIC; - SIGNAL data_shaping_R1 : STD_LOGIC; -BEGIN -- tb - - MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(7)); - - - -- clock generation - Clk <= not Clk after 20 ns; -- 25 Mhz - cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz - - -- waveform generation - WaveGen_Proc: process - begin - -- insert signal assignments here - wait until Clk = '1'; - rstn <= '0'; - cnv_rstn <= '0'; - run_cnv <= '0'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - rstn <= '1'; - cnv_rstn <= '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - run_cnv <= '1'; - wait; - - end process WaveGen_Proc; - - ----------------------------------------------------------------------------- - - Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip - GENERIC MAP ( - hindex => 2, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size =>16, - delta_f2_f0_size =>10, - delta_f2_f1_size =>10, - tech => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo, - cnv_clk => cnv_clk, - cnv_rstn => cnv_rstn, - clk => clk, - rstn => rstn, - sample_f0_wen => sample_f0_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wen => sample_f1_wen, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wen => sample_f2_wen, - sample_f2_wdata => sample_f2_wdata, - sample_f3_wen => sample_f3_wen, - sample_f3_wdata => sample_f3_wdata, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - coarse_time_0 => coarse_time_0, - data_shaping_SP0 => data_shaping_SP0, - data_shaping_SP1 => data_shaping_SP1, - data_shaping_R0 => data_shaping_R0, - data_shaping_R1 => data_shaping_R1, - delta_snapshot => delta_snapshot, - delta_f2_f1 => delta_f2_f1, - delta_f2_f0 => delta_f2_f0, - enable_f0 => enable_f0, - enable_f1 => enable_f1, - enable_f2 => enable_f2, - enable_f3 => enable_f3, - burst_f0 => burst_f0, - burst_f1 => burst_f1, - burst_f2 => burst_f2, - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - status_new_err => status_new_err, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3); - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - enable_f0 <= '0'; - enable_f1 <= '0'; - enable_f2 <= '0'; - enable_f3 <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - enable_f0 <= '1'; --TODO test - enable_f1 <= '1'; - enable_f2 <= '1'; - enable_f3 <= '1'; - END IF; - END PROCESS; - - burst_f0 <= '0'; --TODO test - burst_f1 <= '0'; --TODO test - burst_f2 <= '0'; - - data_shaping_SP0 <= '0'; - data_shaping_SP1 <= '0'; - data_shaping_R0 <= '1'; - data_shaping_R1 <= '1'; - - delta_snapshot <= "0000000000000001"; - --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 - --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2 - --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4 - - -- A redefinir car ca ne tombe pas correctement ... ??? - nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34 - nb_snapshot_param <= "00000001111"; -- x+1 = 16 - delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2 - delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4 - - addr_data_f0 <= "00000000000000000000000000000000"; - addr_data_f1 <= "00010000000000000000000000000000"; - addr_data_f2 <= "00100000000000000000000000000000"; - addr_data_f3 <= "00110000000000000000000000000000"; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - status_full_ack <= (OTHERS => '0'); - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - status_full_ack <= status_full; - END IF; - END PROCESS; - - - coarse_time_0_t <= not coarse_time_0_t after 50 ms; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - coarse_time_0_t2 <= '0'; - coarse_time_0 <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - coarse_time_0_t2 <= coarse_time_0_t; - coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2); - END IF; - END PROCESS; - - - AHB_Master_In.HGRANT(2) <= '1'; - AHB_Master_In.HREADY <= '1'; - - - AHB_Master_In.HRESP <= HRESP_OKAY; - - -END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/TB_Header.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/TB_Header.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/TB_Header.vhd +++ /dev/null @@ -1,334 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_Header.ALL; -USE lpp.lpp_dma_pkg.ALL; -use lpp.lpp_amba.all; -use lpp.lpp_memory.all; -use lpp.lpp_uart.all; -use lpp.lpp_matrix.all; -use lpp.lpp_delay.all; -use lpp.lpp_fft.all; -use lpp.fft_components.all; -use lpp.lpp_ad_conv.all; -use lpp.iir_filter.all; -use lpp.general_purpose.all; -use lpp.Filtercfg.all; -use lpp.lpp_demux.all; -use lpp.lpp_top_lfr_pkg.all; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -------------------------------------------------------------------------------- - -ENTITY TB_Header IS - -END TB_Header; - -------------------------------------------------------------------------------- - -ARCHITECTURE tb OF TB_Header IS - - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - -- component ports - SIGNAL cnv_rstn : STD_LOGIC; - SIGNAL cnv : STD_LOGIC; - SIGNAL rstn : STD_LOGIC; - SIGNAL sck : STD_LOGIC; - SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL run_cnv : STD_LOGIC; - - - -- clock - SIGNAL Clk : STD_LOGIC := '1'; - SIGNAL cnv_clk : STD_LOGIC := '1'; - - ----------------------------------------------------------------------------- --- FIFOs - SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - - SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - - SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); - --- MATRICE SPECTRALE - SIGNAL SM_FlagError : STD_LOGIC; - SIGNAL SM_Pong : STD_LOGIC; - SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); - - SIGNAL Dma_acq : STD_LOGIC; - --- FFT - SIGNAL FFT_Load : STD_LOGIC; - SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - --- DEMUX - SIGNAL DEMU_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); - SIGNAL DEMU_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL DEMU_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - --- ACQ - SIGNAL sample_val : STD_LOGIC; - SIGNAL sample : Samples(8-1 DOWNTO 0); - - SIGNAL TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - SIGNAL TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL pong : STD_LOGIC; - SIGNAL Statu : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL Matrix_Type : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL Matrix_Write : STD_LOGIC; - SIGNAL Valid : STD_LOGIC; - SIGNAL dataIN : STD_LOGIC_VECTOR((2*Data_sz)-1 DOWNTO 0); - SIGNAL emptyIN : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL RenOUT : STD_LOGIC_VECTOR(1 DOWNTO 0); - - ----------------------------------------------------------------------------- - - SIGNAL AHB_Master_In : AHB_Mst_In_Type; - SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; - - ----------------------------------------------------------------------------- - SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fifo_empty : STD_LOGIC; - SIGNAL fifo_ren : STD_LOGIC; - SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL header_val : STD_LOGIC; - SIGNAL header_ack : STD_LOGIC; - SIGNAL ready_matrix_f0_0 : STD_LOGIC; - SIGNAL ready_matrix_f0_1 : STD_LOGIC; - SIGNAL ready_matrix_f1 : STD_LOGIC; - SIGNAL ready_matrix_f2 : STD_LOGIC; - SIGNAL error_anticipating_empty_fifo : STD_LOGIC; - SIGNAL error_bad_component_error : STD_LOGIC; - SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; - SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; - SIGNAL status_ready_matrix_f1 : STD_LOGIC; - SIGNAL status_ready_matrix_f2 : STD_LOGIC; - SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; - SIGNAL status_error_bad_component_error : STD_LOGIC; - SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; - SIGNAL config_active_interruption_onError : STD_LOGIC; - SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - -BEGIN -- tb - - MODULE_ADS7886 : FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(7)); - - - -- clock generation - Clk <= NOT Clk AFTER 20 ns; -- 25 Mhz - cnv_clk <= NOT cnv_clk AFTER 10173 ps; -- 49.152 MHz - - -- waveform generation - WaveGen_Proc : PROCESS - BEGIN - -- insert signal assignments here - WAIT UNTIL Clk = '1'; - rstn <= '0'; - cnv_rstn <= '0'; - run_cnv <= '0'; - WAIT UNTIL Clk = '1'; - WAIT UNTIL Clk = '1'; - WAIT UNTIL Clk = '1'; - rstn <= '1'; - cnv_rstn <= '1'; - WAIT UNTIL Clk = '1'; - WAIT UNTIL Clk = '1'; - WAIT UNTIL Clk = '1'; - WAIT UNTIL Clk = '1'; - WAIT UNTIL Clk = '1'; - WAIT UNTIL Clk = '1'; - run_cnv <= '1'; - WAIT; - - END PROCESS WaveGen_Proc; - - ----------------------------------------------------------------------------- - - TopACQ : lpp_top_acq - PORT MAP(run_cnv, cnv,sck, sdo, cnv_clk, rstn, clk, rstn, TopACQ_WenF0, TopACQ_DataF0, TopACQ_WenF1, TopACQ_DataF1, OPEN, OPEN, TopACQ_WenF3, TopACQ_DataF3); - - Bias_Fails <= '0'; - Memf0 : lppFIFOxN - GENERIC MAP(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP(rstn, clk, clk, (OTHERS => '0'), TopACQ_WenF0, DEMU_Read(4 DOWNTO 0), TopACQ_DataF0, FifoF0_Data, OPEN, FifoF0_Empty); - - Memf1 : lppFIFOxN - GENERIC MAP(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP(rstn, clk, clk, (OTHERS => '0'), TopACQ_WenF1, DEMU_Read(9 DOWNTO 5), TopACQ_DataF1, FifoF1_Data, OPEN, FifoF1_Empty); - - Memf3 : lppFIFOxN - GENERIC MAP(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP(rstn, clk, clk, (OTHERS => '0'), TopACQ_WenF3, DEMU_Read(14 DOWNTO 10), TopACQ_DataF3, FifoF3_Data, OPEN, FifoF3_Empty); - ---- DEMUX ------------------------------------------------------------- - - DEMU0 : DEMUX - GENERIC MAP(Data_sz => 16) - PORT MAP(clk, rstn, FFT_Read, FFT_Load, FifoF0_Empty, FifoF1_Empty, FifoF3_Empty, FifoF0_Data, FifoF1_Data, FifoF3_Data,Matrix_Type ,DEMU_Read, DEMU_Empty, DEMU_Data); - ---- FFT ------------------------------------------------------------- - - FFT0 : FFT - GENERIC MAP(Data_sz => 16, NbData => 256) - PORT MAP(clk, rstn, DEMU_Empty, DEMU_Data, FifoINT_Full, FFT_Load, FFT_Read, FFT_Write, FFT_ReUse, FFT_Data); - ------ LINK MEMORY ------------------------------------------------------- - - MemInt : lppFIFOxN - GENERIC MAP(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') - PORT MAP(rstn, clk, clk, SM_ReUse, FFT_Write, SM_Read, FFT_Data, FifoINT_Data, FifoINT_Full, OPEN); - ------ MATRICE SPECTRALE ---------------------5 FIFO Input--------------- - - SM0 : MatriceSpectrale - GENERIC MAP(Input_SZ => 16, Result_SZ => 32) - PORT MAP(clk, rstn, FifoINT_Full, FFT_ReUse,Valid,-- FifoOUT_Full, - FifoINT_Data, Dma_acq, Matrix_Write,SM_FlagError, SM_Pong, SM_Param, - SM_Write, SM_Read, SM_ReUse, SM_Data); - - Dma_acq <= '1'; - - MemOut : APB_FIFO - GENERIC MAP (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) - PORT MAP (clk, rstn, clk, clk, (OTHERS => '0'), RenOUT, SM_Write, emptyIN, FifoOUT_Full, dataIN, SM_Data, OPEN, OPEN, apbi, apbo(9)); - - - ----------------------------------------------------------------------------- - HeaderBuilder_1 : HeaderBuilder - GENERIC MAP ( - Data_sz => Data_sz) - PORT MAP ( - clkm => clk, - rstn => rstn, - - pong => SM_Pong,--pong, - Statu => SM_Param,--Statu, - Matrix_Type => Matrix_Type, -- - Matrix_Write => Matrix_Write, - Valid => Valid, - - dataIN => dataIN, - emptyIN => emptyIN, - RenOUT => RenOUT, - - dataOUT => fifo_data, - emptyOUT => fifo_empty, - RenIN => fifo_ren, - - header => header, - header_val => header_val, - header_ack => header_ack); - ----------------------------------------------------------------------------- - lpp_dma_ip_1 : lpp_dma_ip - GENERIC MAP ( - tech => 0, - hindex => 2) - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - - fifo_data => fifo_data, - fifo_empty => fifo_empty, - fifo_ren => fifo_ren, - header => header, - header_val => header_val, - header_ack => header_ack, - --OUT - ready_matrix_f0_0 => ready_matrix_f0_0, - ready_matrix_f0_1 => ready_matrix_f0_1, - ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, - error_anticipating_empty_fifo => error_anticipating_empty_fifo, - error_bad_component_error => error_bad_component_error, - debug_reg => debug_reg, - -- IN - status_ready_matrix_f0_0 => status_ready_matrix_f0_0, - status_ready_matrix_f0_1 => status_ready_matrix_f0_1, - status_ready_matrix_f1 => status_ready_matrix_f1, - status_ready_matrix_f2 => status_ready_matrix_f2, - status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, - status_error_bad_component_error => status_error_bad_component_error, - config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, - config_active_interruption_onError => config_active_interruption_onError, - addr_matrix_f0_0 => addr_matrix_f0_0, - addr_matrix_f0_1 => addr_matrix_f0_1, - addr_matrix_f1 => addr_matrix_f1, - addr_matrix_f2 => addr_matrix_f2); - - ----------------------------------------------------------------------------- - AHB_Master_In.HGRANT(2) <= '1'; - AHB_Master_In.HREADY <= '1'; - - - AHB_Master_In.HRESP <= HRESP_OKAY; - - -END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/Top_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/Top_Data_Acquisition.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/Top_Data_Acquisition.vhd +++ /dev/null @@ -1,498 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -ENTITY Top_Data_Acquisition IS - GENERIC( - hindex : INTEGER := 2; - nb_burst_available_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_snapshot_size : INTEGER := 16; - delta_f2_f0_size : INTEGER := 10; - delta_f2_f1_size : INTEGER := 10; - tech : INTEGER := 0 - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - -- - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - -- - sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - - coarse_time_0 : IN STD_LOGIC; - - --config - data_shaping_SP0 : IN STD_LOGIC; - data_shaping_SP1 : IN STD_LOGIC; - data_shaping_R0 : IN STD_LOGIC; - data_shaping_R1 : IN STD_LOGIC; - - delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - enable_f0 : IN STD_LOGIC; - enable_f1 : IN STD_LOGIC; - enable_f2 : IN STD_LOGIC; - enable_f3 : IN STD_LOGIC; - - burst_f0 : IN STD_LOGIC; - burst_f1 : IN STD_LOGIC; - burst_f2 : IN STD_LOGIC; - - nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma - - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END Top_Data_Acquisition; - -ARCHITECTURE tb OF Top_Data_Acquisition IS - - COMPONENT Downsampling - GENERIC ( - ChanelCount : INTEGER; - SampleSize : INTEGER; - DivideParam : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); - sample_out_val : OUT STD_LOGIC; - sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); - END COMPONENT; - - ----------------------------------------------------------------------------- - CONSTANT ChanelCount : INTEGER := 8; - CONSTANT ncycle_cnv_high : INTEGER := 79; - CONSTANT ncycle_cnv : INTEGER := 500; - - ----------------------------------------------------------------------------- - SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL sample_val_delay : STD_LOGIC; - ----------------------------------------------------------------------------- - CONSTANT Coef_SZ : INTEGER := 9; - CONSTANT CoefCntPerCel : INTEGER := 6; - CONSTANT CoefPerCel : INTEGER := 5; - CONSTANT Cels_count : INTEGER := 5; - - SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_val : STD_LOGIC; - SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_data_shaping_out_val : STD_LOGIC; - SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; - SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - ----------------------------------------------------------------------------- - - SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -BEGIN - - -- component instantiation - ----------------------------------------------------------------------------- - DIGITAL_acquisition : AD7688_drvr - GENERIC MAP ( - ChanelCount => ChanelCount, - ncycle_cnv_high => ncycle_cnv_high, - ncycle_cnv => ncycle_cnv) - PORT MAP ( - cnv_clk => cnv_clk, -- - cnv_rstn => cnv_rstn, -- - cnv_run => cnv_run, -- - cnv => cnv, -- - clk => clk, -- - rstn => rstn, -- - sck => sck, -- - sdo => sdo(ChanelCount-1 DOWNTO 0), -- - sample => sample, - sample_val => sample_val); - - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_val_delay <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_val_delay <= sample_val; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE - SampleLoop : FOR j IN 0 TO 15 GENERATE - sample_filter_in(i, j) <= sample(i)(j); - END GENERATE; - - sample_filter_in(i, 16) <= sample(i)(15); - sample_filter_in(i, 17) <= sample(i)(15); - END GENERATE; - - coefs_v2 <= CoefsInitValCst_v2; - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => 0, - Mem_use => use_CEL, -- use_RAM - Sample_SZ => 18, - Coef_SZ => Coef_SZ, - Coef_Nb => 25, - Coef_sel_SZ => 5, - Cels_count => Cels_count, - ChanelsCount => ChanelCount) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => 7, - coefs => coefs_v2, - sample_in_val => sample_val_delay, - sample_in => sample_filter_in, - sample_out_val => sample_filter_v2_out_val, - sample_out => sample_filter_v2_out); - - ----------------------------------------------------------------------------- - -- DATA_SHAPING - ----------------------------------------------------------------------------- - all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE - sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); - sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); - sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); - END GENERATE all_data_shaping_in_loop; - - sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; - sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_data_shaping_out_val <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - sample_data_shaping_out_val <= sample_filter_v2_out_val; - END IF; - END PROCESS; - - SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - sample_data_shaping_out(0,j) <= '0'; - sample_data_shaping_out(1,j) <= '0'; - sample_data_shaping_out(2,j) <= '0'; - sample_data_shaping_out(3,j) <= '0'; - sample_data_shaping_out(4,j) <= '0'; - sample_data_shaping_out(5,j) <= '0'; - sample_data_shaping_out(6,j) <= '0'; - sample_data_shaping_out(7,j) <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); - IF data_shaping_SP0 = '1' THEN - sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); - ELSE - sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); - END IF; - IF data_shaping_SP1 = '1' THEN - sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); - ELSE - sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); - END IF; - sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); - sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); - sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); - sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); - END IF; - END PROCESS; - END GENERATE; - - sample_filter_v2_out_val_s <= sample_data_shaping_out_val; - ChanelLoopOut : FOR i IN 0 TO 7 GENERATE - SampleLoopOut : FOR j IN 0 TO 15 GENERATE - sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); - END GENERATE; - END GENERATE; - ----------------------------------------------------------------------------- - -- F0 -- @24.576 kHz - ----------------------------------------------------------------------------- - Downsampling_f0 : Downsampling - GENERIC MAP ( - ChanelCount => 8, - SampleSize => 16, - DivideParam => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_filter_v2_out_val_s, - sample_in => sample_filter_v2_out_s, - sample_out_val => sample_f0_val, - sample_out => sample_f0); - - all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_wdata_s(I) <= sample_f0(0, I); -- V - sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 - sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 - sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 - sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 - sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 - END GENERATE all_bit_sample_f0; - - sample_f0_wen <= NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val); - - ----------------------------------------------------------------------------- - -- F1 -- @4096 Hz - ----------------------------------------------------------------------------- - Downsampling_f1 : Downsampling - GENERIC MAP ( - ChanelCount => 8, - SampleSize => 16, - DivideParam => 6) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f1_val, - sample_out => sample_f1); - - all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_wdata_s(I) <= sample_f1(0, I); -- V - sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 - sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 - sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 - sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 - sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 - END GENERATE all_bit_sample_f1; - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); - - ----------------------------------------------------------------------------- - -- F2 -- @256 Hz - ----------------------------------------------------------------------------- - all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_s(0, I) <= sample_f0(0, I); -- V - sample_f0_s(1, I) <= sample_f0(1, I); -- E1 - sample_f0_s(2, I) <= sample_f0(2, I); -- E2 - sample_f0_s(3, I) <= sample_f0(5, I); -- B1 - sample_f0_s(4, I) <= sample_f0(6, I); -- B2 - sample_f0_s(5, I) <= sample_f0(7, I); -- B3 - END GENERATE all_bit_sample_f0_s; - - Downsampling_f2 : Downsampling - GENERIC MAP ( - ChanelCount => 6, - SampleSize => 16, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0_s, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - sample_f2_wen <= NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val); - - all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f2_wdata_s(I) <= sample_f2(0, I); - sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); - sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); - sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); - sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); - sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); - END GENERATE all_bit_sample_f2; - - ----------------------------------------------------------------------------- - -- F3 -- @16 Hz - ----------------------------------------------------------------------------- - all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_s(0, I) <= sample_f1(0, I); -- V - sample_f1_s(1, I) <= sample_f1(1, I); -- E1 - sample_f1_s(2, I) <= sample_f1(2, I); -- E2 - sample_f1_s(3, I) <= sample_f1(5, I); -- B1 - sample_f1_s(4, I) <= sample_f1(6, I); -- B2 - sample_f1_s(5, I) <= sample_f1(7, I); -- B3 - END GENERATE all_bit_sample_f1_s; - - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => 6, - SampleSize => 16, - DivideParam => 256) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f1_val , - sample_in => sample_f1_s, - sample_out_val => sample_f3_val, - sample_out => sample_f3); - - sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); - - all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f3_wdata_s(I) <= sample_f3(0, I); - sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); - sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); - sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); - sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); - sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); - END GENERATE all_bit_sample_f3; - - lpp_waveform_1 : lpp_waveform - GENERIC MAP ( - hindex => hindex, - tech => tech, - data_size => 160, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size => delta_snapshot_size, - delta_f2_f0_size => delta_f2_f0_size, - delta_f2_f1_size => delta_f2_f1_size) - PORT MAP ( - clk => clk, - rstn => rstn, - - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - - coarse_time_0 => coarse_time_0, -- IN - delta_snapshot => delta_snapshot, -- IN - delta_f2_f1 => delta_f2_f1, -- IN - delta_f2_f0 => delta_f2_f0, -- IN - enable_f0 => enable_f0, -- IN - enable_f1 => enable_f1, -- IN - enable_f2 => enable_f2, -- IN - enable_f3 => enable_f3, -- IN - burst_f0 => burst_f0, -- IN - burst_f1 => burst_f1, -- IN - burst_f2 => burst_f2, -- IN - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, -- IN - status_full_err => status_full_err, - status_new_err => status_new_err, - - addr_data_f0 => addr_data_f0, -- IN - addr_data_f1 => addr_data_f1, -- IN - addr_data_f2 => addr_data_f2, -- IN - addr_data_f3 => addr_data_f3, -- IN - - data_f0_in => data_f0_in_valid, - data_f1_in => data_f1_in_valid, - data_f2_in => data_f2_in_valid, - data_f3_in => data_f3_in_valid, - data_f0_in_valid => sample_f0_val, - data_f1_in_valid => sample_f1_val, - data_f2_in_valid => sample_f2_val, - data_f3_in_valid => sample_f3_val); - - data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; - data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; - data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; - data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; - - sample_f0_wdata <= sample_f0_wdata_s; - sample_f1_wdata <= sample_f1_wdata_s; - sample_f2_wdata <= sample_f2_wdata_s; - sample_f3_wdata <= sample_f3_wdata_s; - -END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/config.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/config.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/config.vhd +++ /dev/null @@ -1,218 +0,0 @@ - - - - ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------- - - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -PACKAGE config IS --- Technology and synthesis options - CONSTANT CFG_FABTECH : INTEGER := inferred; - CONSTANT CFG_MEMTECH : INTEGER := inferred; - --constant CFG_FABTECH : integer := apa3; --inferred; - --constant CFG_MEMTECH : integer := apa3; --inferred; - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT CFG_NOASYNC : INTEGER := 0; - CONSTANT CFG_SCAN : INTEGER := 0; --- Clock generator - CONSTANT CFG_CLKTECH : INTEGER := inferred; - CONSTANT CFG_CLKMUL : INTEGER := 2; - CONSTANT CFG_CLKDIV : INTEGER := 2; - CONSTANT CFG_OCLKDIV : INTEGER := 1; - CONSTANT CFG_OCLKBDIV : INTEGER := 0; - CONSTANT CFG_OCLKCDIV : INTEGER := 0; - CONSTANT CFG_PCIDLL : INTEGER := 0; - CONSTANT CFG_PCISYSCLK : INTEGER := 0; - CONSTANT CFG_CLK_NOFB : INTEGER := 0; --- LEON3 processor core - CONSTANT CFG_LEON3 : INTEGER := 1; - CONSTANT CFG_NCPU : INTEGER := (1); - CONSTANT CFG_NWIN : INTEGER := (8); - CONSTANT CFG_V8 : INTEGER := 0 + 4*0; - CONSTANT CFG_MAC : INTEGER := 0; - CONSTANT CFG_BP : INTEGER := 0; - CONSTANT CFG_SVT : INTEGER := 0; - CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; - CONSTANT CFG_LDDEL : INTEGER := (1); - CONSTANT CFG_NOTAG : INTEGER := 0; - CONSTANT CFG_NWP : INTEGER := (0); - CONSTANT CFG_PWD : INTEGER := 0*2; - CONSTANT CFG_FPU : INTEGER := 0 + 16*0 + 32*0; - CONSTANT CFG_GRFPUSH : INTEGER := 0; - CONSTANT CFG_ICEN : INTEGER := 1; - CONSTANT CFG_ISETS : INTEGER := 1; - CONSTANT CFG_ISETSZ : INTEGER := 4; - CONSTANT CFG_ILINE : INTEGER := 8; - CONSTANT CFG_IREPL : INTEGER := 0; - CONSTANT CFG_ILOCK : INTEGER := 0; - CONSTANT CFG_ILRAMEN : INTEGER := 0; - CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; - CONSTANT CFG_ILRAMSZ : INTEGER := 1; - CONSTANT CFG_DCEN : INTEGER := 1; - CONSTANT CFG_DSETS : INTEGER := 1; - CONSTANT CFG_DSETSZ : INTEGER := 4; - CONSTANT CFG_DLINE : INTEGER := 8; - CONSTANT CFG_DREPL : INTEGER := 0; - CONSTANT CFG_DLOCK : INTEGER := 0; - CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; - CONSTANT CFG_DFIXED : INTEGER := 16#0#; - CONSTANT CFG_DLRAMEN : INTEGER := 0; - CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; - CONSTANT CFG_DLRAMSZ : INTEGER := 1; - CONSTANT CFG_MMUEN : INTEGER := 1; - CONSTANT CFG_ITLBNUM : INTEGER := 8; - CONSTANT CFG_DTLBNUM : INTEGER := 8; - CONSTANT CFG_TLB_TYPE : INTEGER := 0 + 1*2; - CONSTANT CFG_TLB_REP : INTEGER := 1; - CONSTANT CFG_MMU_PAGE : INTEGER := 0; - CONSTANT CFG_DSU : INTEGER := 0; - CONSTANT CFG_ITBSZ : INTEGER := 0; - CONSTANT CFG_ATBSZ : INTEGER := 0; - CONSTANT CFG_LEON3FT_EN : INTEGER := 0; - CONSTANT CFG_IUFT_EN : INTEGER := 0; - CONSTANT CFG_FPUFT_EN : INTEGER := 0; - CONSTANT CFG_RF_ERRINJ : INTEGER := 0; - CONSTANT CFG_CACHE_FT_EN : INTEGER := 0; - CONSTANT CFG_CACHE_ERRINJ : INTEGER := 0; - CONSTANT CFG_LEON3_NETLIST : INTEGER := 0; - CONSTANT CFG_DISAS : INTEGER := 0 + 0; - CONSTANT CFG_PCLOW : INTEGER := 2; --- AMBA settings - CONSTANT CFG_DEFMST : INTEGER := (0); - CONSTANT CFG_RROBIN : INTEGER := 1; - CONSTANT CFG_SPLIT : INTEGER := 0; - CONSTANT CFG_FPNPEN : INTEGER := 0; - CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; - CONSTANT CFG_APBADDR : INTEGER := 16#800#; - CONSTANT CFG_AHB_MON : INTEGER := 0; - CONSTANT CFG_AHB_MONERR : INTEGER := 0; - CONSTANT CFG_AHB_MONWAR : INTEGER := 0; - CONSTANT CFG_AHB_DTRACE : INTEGER := 0; --- DSU UART - CONSTANT CFG_AHB_UART : INTEGER := 1; --- JTAG based DSU interface - CONSTANT CFG_AHB_JTAG : INTEGER := 0; --- Ethernet DSU - CONSTANT CFG_DSU_ETH : INTEGER := 0 + 0 + 0; - CONSTANT CFG_ETH_BUF : INTEGER := 1; - CONSTANT CFG_ETH_IPM : INTEGER := 16#C0A8#; - CONSTANT CFG_ETH_IPL : INTEGER := 16#0033#; - CONSTANT CFG_ETH_ENM : INTEGER := 16#020000#; - CONSTANT CFG_ETH_ENL : INTEGER := 16#000009#; --- PROM/SRAM controller - CONSTANT CFG_SRCTRL : INTEGER := 0; - CONSTANT CFG_SRCTRL_PROMWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_RAMWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_IOWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_RMW : INTEGER := 0; - CONSTANT CFG_SRCTRL_8BIT : INTEGER := 0; - CONSTANT CFG_SRCTRL_SRBANKS : INTEGER := 1; - CONSTANT CFG_SRCTRL_BANKSZ : INTEGER := 0; - CONSTANT CFG_SRCTRL_ROMASEL : INTEGER := 0; --- LEON2 memory controller - CONSTANT CFG_MCTRL_LEON2 : INTEGER := 1; - CONSTANT CFG_MCTRL_RAM8BIT : INTEGER := 0; - CONSTANT CFG_MCTRL_RAM16BIT : INTEGER := 0; - CONSTANT CFG_MCTRL_5CS : INTEGER := 0; - CONSTANT CFG_MCTRL_SDEN : INTEGER := 1; - CONSTANT CFG_MCTRL_SEPBUS : INTEGER := 0; - CONSTANT CFG_MCTRL_INVCLK : INTEGER := 0; - CONSTANT CFG_MCTRL_SD64 : INTEGER := 0; - CONSTANT CFG_MCTRL_PAGE : INTEGER := 1 + 0; --- SDRAM controller - CONSTANT CFG_SDCTRL : INTEGER := 0; - CONSTANT CFG_SDCTRL_INVCLK : INTEGER := 0; - CONSTANT CFG_SDCTRL_SD64 : INTEGER := 0; - CONSTANT CFG_SDCTRL_PAGE : INTEGER := 0 + 0; --- AHB ROM - CONSTANT CFG_AHBROMEN : INTEGER := 0; - CONSTANT CFG_AHBROPIP : INTEGER := 0; - CONSTANT CFG_AHBRODDR : INTEGER := 16#000#; - CONSTANT CFG_ROMADDR : INTEGER := 16#000#; - CONSTANT CFG_ROMMASK : INTEGER := 16#E00# + 16#000#; --- AHB RAM - CONSTANT CFG_AHBRAMEN : INTEGER := 1; - CONSTANT CFG_AHBRSZ : INTEGER := 1; - CONSTANT CFG_AHBRADDR : INTEGER := 16#A00#; --- Gaisler Ethernet core - CONSTANT CFG_GRETH : INTEGER := 0; - CONSTANT CFG_GRETH1G : INTEGER := 0; - CONSTANT CFG_ETH_FIFO : INTEGER := 8; - --- CAN 2.0 interface - CONSTANT CFG_CAN : INTEGER := 0; - CONSTANT CFG_CANIO : INTEGER := 16#0#; - CONSTANT CFG_CANIRQ : INTEGER := 0; - CONSTANT CFG_CANLOOP : INTEGER := 0; - CONSTANT CFG_CAN_SYNCRST : INTEGER := 0; - CONSTANT CFG_CANFT : INTEGER := 0; - --- PCI interface - CONSTANT CFG_PCI : INTEGER := 0; - CONSTANT CFG_PCIVID : INTEGER := 16#0#; - CONSTANT CFG_PCIDID : INTEGER := 16#0#; - CONSTANT CFG_PCIDEPTH : INTEGER := 8; - CONSTANT CFG_PCI_MTF : INTEGER := 1; - --- PCI arbiter - CONSTANT CFG_PCI_ARB : INTEGER := 0; - CONSTANT CFG_PCI_ARBAPB : INTEGER := 0; - CONSTANT CFG_PCI_ARB_NGNT : INTEGER := 4; - --- PCI trace buffer - CONSTANT CFG_PCITBUFEN : INTEGER := 0; - CONSTANT CFG_PCITBUF : INTEGER := 256; - --- Spacewire interface - CONSTANT CFG_SPW_EN : INTEGER := 0; - CONSTANT CFG_SPW_NUM : INTEGER := 1; - CONSTANT CFG_SPW_AHBFIFO : INTEGER := 4; - CONSTANT CFG_SPW_RXFIFO : INTEGER := 16; - CONSTANT CFG_SPW_RMAP : INTEGER := 0; - CONSTANT CFG_SPW_RMAPBUF : INTEGER := 4; - CONSTANT CFG_SPW_RMAPCRC : INTEGER := 0; - CONSTANT CFG_SPW_NETLIST : INTEGER := 0; - CONSTANT CFG_SPW_FT : INTEGER := 0; - CONSTANT CFG_SPW_GRSPW : INTEGER := 2; - CONSTANT CFG_SPW_RXUNAL : INTEGER := 0; - CONSTANT CFG_SPW_DMACHAN : INTEGER := 1; - CONSTANT CFG_SPW_PORTS : INTEGER := 1; - CONSTANT CFG_SPW_INPUT : INTEGER := 2; - CONSTANT CFG_SPW_OUTPUT : INTEGER := 0; - CONSTANT CFG_SPW_RTSAME : INTEGER := 0; --- UART 1 - CONSTANT CFG_UART1_ENABLE : INTEGER := 1; - CONSTANT CFG_UART1_FIFO : INTEGER := 4; - --- UART 2 - CONSTANT CFG_UART2_ENABLE : INTEGER := 0; - CONSTANT CFG_UART2_FIFO : INTEGER := 1; - --- LEON3 interrupt controller - CONSTANT CFG_IRQ3_ENABLE : INTEGER := 1; - CONSTANT CFG_IRQ3_NSEC : INTEGER := 0; - --- Modular timer - CONSTANT CFG_GPT_ENABLE : INTEGER := 1; - CONSTANT CFG_GPT_NTIM : INTEGER := (2); - CONSTANT CFG_GPT_SW : INTEGER := (8); - CONSTANT CFG_GPT_TW : INTEGER := (32); - CONSTANT CFG_GPT_IRQ : INTEGER := (8); - CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; - CONSTANT CFG_GPT_WDOGEN : INTEGER := 1; - CONSTANT CFG_GPT_WDOG : INTEGER := 16#FFFF#; - --- GPIO port - CONSTANT CFG_GRGPIO_ENABLE : INTEGER := 1; - CONSTANT CFG_GRGPIO_IMASK : INTEGER := 16#0000#; - CONSTANT CFG_GRGPIO_WIDTH : INTEGER := (8); - --- GRLIB debugging - CONSTANT CFG_DUART : INTEGER := 1; -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/ip_synthesis/lpp_top_lfr_wf_picker.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/ip_synthesis/lpp_top_lfr_wf_picker.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/ip_synthesis/lpp_top_lfr_wf_picker.vhd +++ /dev/null @@ -1,71110 +0,0 @@ --- Version: 9.1 SP5 9.1.5.1 - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_apbreg is - - port( status_full_ack : out std_logic_vector(3 downto 0); - prdata_c : out std_logic_vector(31 downto 0); - pirq_c : out std_logic_vector(15 to 15); - addr_data_f2 : out std_logic_vector(31 downto 0); - status_new_err_3 : in std_logic; - status_new_err_0_2 : in std_logic; - status_new_err_0_0 : in std_logic; - status_new_err_0_1 : in std_logic; - status_full_err_0 : in std_logic_vector(3 downto 0); - status_full : in std_logic_vector(3 downto 0); - addr_data_f3 : out std_logic_vector(31 downto 0); - nb_burst_available : out std_logic_vector(10 downto 0); - addr_data_f1 : out std_logic_vector(31 downto 0); - delta_f2_f1 : out std_logic_vector(9 downto 0); - addr_data_f0 : out std_logic_vector(31 downto 0); - delta_f2_f0 : out std_logic_vector(9 downto 0); - delta_snapshot : out std_logic_vector(15 downto 0); - nb_snapshot_param : out std_logic_vector(10 downto 0); - apbi_c_81 : in std_logic; - apbi_c_80 : in std_logic; - apbi_c_79 : in std_logic; - apbi_c_78 : in std_logic; - apbi_c_77 : in std_logic; - apbi_c_76 : in std_logic; - apbi_c_75 : in std_logic; - apbi_c_74 : in std_logic; - apbi_c_73 : in std_logic; - apbi_c_72 : in std_logic; - apbi_c_71 : in std_logic; - apbi_c_70 : in std_logic; - apbi_c_69 : in std_logic; - apbi_c_68 : in std_logic; - apbi_c_67 : in std_logic; - apbi_c_66 : in std_logic; - apbi_c_65 : in std_logic; - apbi_c_64 : in std_logic; - apbi_c_63 : in std_logic; - apbi_c_62 : in std_logic; - apbi_c_61 : in std_logic; - apbi_c_60 : in std_logic; - apbi_c_59 : in std_logic; - apbi_c_58 : in std_logic; - apbi_c_57 : in std_logic; - apbi_c_56 : in std_logic; - apbi_c_55 : in std_logic; - apbi_c_24 : in std_logic; - apbi_c_23 : in std_logic; - apbi_c_0 : in std_logic; - apbi_c_50 : in std_logic; - apbi_c_51 : in std_logic; - apbi_c_52 : in std_logic; - apbi_c_16 : in std_logic; - apbi_c_49 : in std_logic; - apbi_c_22 : in std_logic; - apbi_c_20 : in std_logic; - apbi_c_19 : in std_logic; - apbi_c_21 : in std_logic; - apbi_c_54 : in std_logic; - apbi_c_53 : in std_logic; - data_shaping_R0 : out std_logic; - data_shaping_R1 : out std_logic; - enable_f0 : out std_logic; - data_shaping_BW_c : out std_logic; - burst_f2 : out std_logic; - burst_f1 : out std_logic; - burst_f0 : out std_logic; - enable_f3 : out std_logic; - enable_f2 : out std_logic; - data_shaping_SP1 : out std_logic; - enable_f1 : out std_logic; - data_shaping_SP0 : out std_logic; - data_shaping_R1_0 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_shaping_R0_0 : out std_logic - ); - -end lpp_top_apbreg; - -architecture DEF_ARCH of lpp_top_apbreg is - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal data_shaping_BW_1_sqmuxa, prdata_9_sqmuxa_0, N_931, - prdata_10_sqmuxa_0, prdata_12_sqmuxa_0, N_168, N_157, - N_933_0, N_930, addr_matrix_f0_0_1_sqmuxa_0, N_159, N_928, - addr_matrix_f0_1_1_sqmuxa_0, N_166, - addr_matrix_f1_1_sqmuxa_0, N_172, - addr_matrix_f2_1_sqmuxa_0, un1_apbi_2, - addr_data_f0_1_sqmuxa_0, addr_data_f1_1_sqmuxa_0, - addr_data_f2_1_sqmuxa_0, addr_data_f3_1_sqmuxa_0, N_161_0, - prdata_2_sqmuxa_0, prdata_3_sqmuxa_0, prdata_4_sqmuxa_0, - prdata_5_sqmuxa_0, N_168_0, \prdata_39_0_iv_14[4]\, - \nb_burst_available_m_i[4]\, \prdata_39_0_iv_9[4]\, - data_shaping_R1_m_i, \prdata_39_0_iv_11[4]\, - \prdata_39_0_iv_3[4]\, burst_f0_m_i, - \prdata_39_0_iv_7[4]\, \prdata_39_0_iv_10[4]\, - prdata_18_sqmuxa, \prdata_39_0_iv_6[4]\, - \addr_data_f3_m_i[4]\, \addr_data_f2_m_i[4]\, - \prdata_39_0_iv_5[4]\, prdata_14_sqmuxa, - \prdata_39_0_iv_2[4]\, \addr_matrix_f0_1_m_i[4]\, - \addr_matrix_f0_0_m_i[4]\, \prdata_39_0_iv_1[4]\, - prdata_16_sqmuxa, \delta_f2_f1_m_i[4]\, - \addr_data_f1_m_i[4]\, \status_full_err[0]\, - prdata_13_sqmuxa, - status_error_anticipating_empty_fifo_m_i, - \addr_matrix_f1[4]\, \addr_matrix_f2_m_i[4]\, - \prdata_39_0_iv_13[3]\, \nb_snapshot_param_m_i[3]\, - \prdata_39_0_iv_6[3]\, \prdata_39_0_iv_11[3]\, - \prdata_39_0_iv_12[3]\, \prdata_39_0_iv_3[3]\, - \prdata_39_0_iv_2[3]\, \prdata_39_0_iv_9[3]\, - \delta_snapshot_m_i[3]\, \prdata_39_0_iv_1[3]\, - \nb_burst_available_m_i[3]\, \delta_f2_f0_m_i[3]\, - \addr_data_f3_m_i[3]\, \prdata_39_0_iv_5[3]\, - \addr_matrix_f0_1_m_i[3]\, \addr_matrix_f0_0_m_i[3]\, - \status_full_m_i[3]\, prdata_15_sqmuxa, enable_f3_m_i, - \addr_data_f2_m_i[3]\, status_ready_matrix_f2_m_i, - \addr_matrix_f1[3]\, \addr_matrix_f2_m_i[3]\, - \prdata_39_0_iv_14[1]\, \prdata_39_0_iv_7[1]\, - \prdata_39_0_iv_6[1]\, \prdata_39_0_iv_10[1]\, - \prdata_39_0_iv_13[1]\, \prdata_39_0_iv_4[1]\, - \prdata_39_0_iv_3[1]\, data_shaping_SP0_m_i, - \prdata_39_0_iv_12[1]\, prdata_17_sqmuxa, - \prdata_39_0_iv_8[1]\, \prdata_39_0_iv_5[1]\, - enable_f1_m_i, \addr_matrix_f2_m_i[1]\, - \addr_matrix_f1_m_i[1]\, \prdata_39_0_iv_2[1]\, - \addr_matrix_f0_1_m_i[1]\, \addr_matrix_f0_0_m_i[1]\, - \status_full_m_i[1]\, \delta_f2_f1_m_i[1]\, - \addr_data_f2_m_i[1]\, \addr_data_f1_m_i[1]\, - prdata_0_sqmuxa, config_active_interruption_onError, - status_ready_matrix_f0_1_m_i, \prdata_39_0_iv_13[2]\, - \prdata_39_0_iv_6[2]\, \nb_snapshot_param_m_i[2]\, - data_shaping_SP1_m_i, \prdata_39_0_iv_12[2]\, - \prdata_39_0_iv_3[2]\, \prdata_39_0_iv_2[2]\, - \prdata_39_0_iv_9[2]\, \prdata_39_0_iv_11[2]\, - \prdata_39_0_iv_7[2]\, \status_full_m_i[2]\, - \delta_f2_f1_m_i[2]\, \prdata_39_0_iv_4[2]\, - enable_f2_m_i, \addr_matrix_f0_1_m_i[2]\, - \addr_matrix_f0_0_m_i[2]\, \prdata_39_0_iv_1[2]\, - \delta_f2_f0_m_i[2]\, \addr_data_f2_m_i[2]\, - status_ready_matrix_f1_m_i, \addr_matrix_f1[2]\, - \addr_matrix_f2_m_i[2]\, \prdata_39_0_iv_12[5]\, - \prdata_39_0_iv_5[5]\, \prdata_39_0_iv_4[5]\, - \nb_burst_available_m_i[5]\, \prdata_39_0_iv_11[5]\, - \prdata_39_0_iv_3[5]\, burst_f1_m_i, - \prdata_39_0_iv_7[5]\, \prdata_39_0_iv_10[5]\, - \prdata_39_0_iv_6[5]\, \prdata_39_0_iv_2[5]\, - \addr_matrix_f0_1_m_i[5]\, \addr_matrix_f0_0_m_i[5]\, - \prdata_39_0_iv_1[5]\, \delta_f2_f1_m_i[5]\, - \addr_data_f2_m_i[5]\, \addr_data_f1_m_i[5]\, - \status_full_err[1]\, - status_error_bad_component_error_m_i, \addr_matrix_f1[5]\, - \addr_matrix_f2_m_i[5]\, \prdata_39_0_iv_10[8]\, - \prdata_39_0_iv_3[8]\, \prdata_39_0_iv_2[8]\, - \nb_burst_available_m_i[8]\, \prdata_39_0_iv_9[8]\, - \prdata_39_0_iv_0[8]\, \delta_f2_f1_m_i[8]\, - \prdata_39_0_iv_6[8]\, \prdata_39_0_iv_8[8]\, - \delta_f2_f0_m_i[8]\, \addr_data_f3_m_i[8]\, - \nb_snapshot_param_m_i[8]\, \addr_matrix_f2_m_i[8]\, - \addr_matrix_f1_m_i[8]\, \delta_snapshot_m_i[8]\, - \addr_data_f2_m_i[8]\, \status_new_err[0]\, - \addr_data_f0_m_i[8]\, \addr_matrix_f0_0[8]\, - \addr_matrix_f0_1_m_i[8]\, \prdata_39_0_iv_14[0]\, - \prdata_39_0_iv_4[0]\, \prdata_39_0_iv_3[0]\, - \prdata_39_0_iv_11[0]\, \prdata_39_0_iv_13[0]\, - \delta_snapshot_m_i[0]\, \prdata_39_0_iv_2[0]\, - \prdata_39_0_iv_9[0]\, \prdata_39_0_iv_12[0]\, - \prdata_39_0_iv_7[0]\, \status_full_m_i[0]\, - \delta_f2_f1_m_i[0]\, \prdata_39_0_iv_5[0]\, - enable_f0_m_i, \addr_matrix_f0_1_m_i[0]\, - \addr_matrix_f0_0_m_i[0]\, \prdata_39_0_iv_1[0]\, - data_shaping_BW_m_i, \addr_data_f2_m_i[0]\, - \addr_data_f1_m_i[0]\, - config_active_interruption_onNewMatrix, - status_ready_matrix_f0_0_m_i, \addr_matrix_f1[0]\, - \addr_matrix_f2_m_i[0]\, \prdata_39_0_iv_11[6]\, - \prdata_39_0_iv_3[6]\, \prdata_39_0_iv_2[6]\, - \prdata_39_0_iv_8[6]\, \prdata_39_0_iv_10[6]\, - \prdata_39_0_iv_6[6]\, \prdata_39_0_iv_9[6]\, - \prdata_39_0_iv_5[6]\, \delta_f2_f0_m_i[6]\, - \addr_data_f3_m_i[6]\, burst_f2_m_i, - \addr_matrix_f2_m_i[6]\, \addr_matrix_f1_m_i[6]\, - \delta_snapshot_m_i[6]\, \addr_matrix_f0_1_m_i[6]\, - \addr_matrix_f0_0_m_i[6]\, \delta_f2_f1_m_i[6]\, - \addr_data_f2_m_i[6]\, \status_full_err[2]\, - \addr_data_f0_m_i[6]\, \prdata_39_0_iv_10[7]\, - \prdata_39_0_iv_3[7]\, \prdata_39_0_iv_2[7]\, - \nb_burst_available_m_i[7]\, \prdata_39_0_iv_9[7]\, - \delta_snapshot_m_i[7]\, \prdata_39_0_iv_1[7]\, - \prdata_39_0_iv_5[7]\, \prdata_39_0_iv_8[7]\, - \delta_f2_f0_m_i[7]\, \addr_data_f3_m_i[7]\, - \nb_snapshot_param_m_i[7]\, \addr_matrix_f0_1_m_i[7]\, - \addr_matrix_f0_0_m_i[7]\, \delta_f2_f1_m_i[7]\, - \addr_data_f2_m_i[7]\, \status_full_err[3]\, - \addr_data_f0_m_i[7]\, \addr_matrix_f1[7]\, - \addr_matrix_f2_m_i[7]\, \prdata_39_0_iv_10[9]\, - \prdata_39_0_iv_3[9]\, \prdata_39_0_iv_2[9]\, - \nb_burst_available_m_i[9]\, \prdata_39_0_iv_9[9]\, - \delta_snapshot_m_i[9]\, \prdata_39_0_iv_1[9]\, - \prdata_39_0_iv_5[9]\, \prdata_39_0_iv_8[9]\, - \delta_f2_f0_m_i[9]\, \addr_data_f3_m_i[9]\, - \nb_snapshot_param_m_i[9]\, \addr_matrix_f0_1_m_i[9]\, - \addr_matrix_f0_0_m_i[9]\, \delta_f2_f1_m_i[9]\, - \addr_data_f2_m_i[9]\, \status_new_err[1]\, - \addr_data_f0_m_i[9]\, \addr_matrix_f1[9]\, - \addr_matrix_f2_m_i[9]\, \prdata_39_0_iv_8[10]\, - \prdata_39_0_iv_2[10]\, \nb_snapshot_param_m_i[10]\, - \prdata_39_0_iv_5[10]\, \prdata_39_0_iv_7[10]\, - \prdata_39_0_iv_0[10]\, \addr_data_f3_m_i[10]\, - \prdata_39_0_iv_3[10]\, \prdata_39_0_iv_1[10]\, - \addr_data_f2_m_i[10]\, \status_new_err[2]\, - \addr_data_f0_m_i[10]\, \addr_matrix_f1[10]\, - \addr_matrix_f2_m_i[10]\, \addr_matrix_f0_0[10]\, - \addr_matrix_f0_1_m_i[10]\, \prdata_39_0_iv_6[11]\, - \addr_data_f0_m_i[11]\, \status_new_err_m_i[3]\, - \prdata_39_0_iv_3[11]\, \prdata_39_0_iv_5[11]\, - \prdata_39_0_iv_1[11]\, \prdata_39_0_iv_4[11]\, - \addr_matrix_f0_1_m_i[11]\, \addr_matrix_f0_0_m_i[11]\, - \addr_data_f3_m_i[11]\, \addr_data_f2_m_i[11]\, - \addr_matrix_f1[11]\, \addr_matrix_f2_m_i[11]\, - \prdata_39_0_iv_6[12]\, \prdata_39_0_iv_1[12]\, - \prdata_39_0_iv_0[12]\, \prdata_39_0_iv_3[12]\, - \addr_data_f2_m_i[12]\, \prdata_39_0_iv_2[12]\, - \addr_data_f1_m_i[12]\, \addr_matrix_f1[12]\, - \addr_matrix_f2_m_i[12]\, \addr_matrix_f0_0[12]\, - \addr_matrix_f0_1_m_i[12]\, \prdata_39_0_iv_6[13]\, - \prdata_39_0_iv_1[13]\, \prdata_39_0_iv_0[13]\, - \prdata_39_0_iv_3[13]\, \addr_data_f2_m_i[13]\, - \prdata_39_0_iv_2[13]\, \addr_data_f1_m_i[13]\, - \addr_matrix_f1[13]\, \addr_matrix_f2_m_i[13]\, - \addr_matrix_f0_0[13]\, \addr_matrix_f0_1_m_i[13]\, - \prdata_39_0_iv_6[14]\, \prdata_39_0_iv_1[14]\, - \prdata_39_0_iv_0[14]\, \prdata_39_0_iv_3[14]\, - \addr_data_f2_m_i[14]\, \prdata_39_0_iv_2[14]\, - \addr_data_f1_m_i[14]\, \addr_matrix_f1[14]\, - \addr_matrix_f2_m_i[14]\, \addr_matrix_f0_0[14]\, - \addr_matrix_f0_1_m_i[14]\, \prdata_39_0_iv_5[15]\, - \addr_data_f1_m_i[15]\, \addr_data_f0_m_i[15]\, - \delta_snapshot_m_i[15]\, \prdata_39_0_iv_4[15]\, - \addr_matrix_f0_1_m_i[15]\, \addr_matrix_f0_0_m_i[15]\, - \prdata_39_0_iv_1[15]\, \prdata_39_0_iv_3[15]\, - \addr_data_f2_m_i[15]\, \addr_matrix_f1[15]\, - \addr_matrix_f2_m_i[15]\, \prdata_39_0_iv_4[16]\, - \addr_matrix_f0_1_m_i[16]\, \addr_matrix_f0_0_m_i[16]\, - \prdata_39_0_iv_1[16]\, \prdata_39_0_iv_3[16]\, - \addr_data_f2_m_i[16]\, \prdata_39_0_iv_2[16]\, - \addr_data_f1_m_i[16]\, \addr_matrix_f1[16]\, - \addr_matrix_f2_m_i[16]\, \prdata_39_0_iv_4[17]\, - \addr_matrix_f0_1_m_i[17]\, \addr_matrix_f0_0_m_i[17]\, - \prdata_39_0_iv_1[17]\, \prdata_39_0_iv_3[17]\, - \addr_data_f2_m_i[17]\, \prdata_39_0_iv_2[17]\, - \addr_data_f1_m_i[17]\, \addr_matrix_f1[17]\, - \addr_matrix_f2_m_i[17]\, \prdata_39_0_iv_5[18]\, - \addr_data_f3_m_i[18]\, \addr_data_f2_m_i[18]\, - \prdata_39_0_iv_2[18]\, \addr_data_f1_m_i[18]\, - \prdata_39_0_iv_1[18]\, \addr_matrix_f1[18]\, - \addr_matrix_f2_m_i[18]\, \prdata_39_0_iv_0[18]\, - \addr_matrix_f0_0[18]\, \addr_matrix_f0_1_m_i[18]\, - \prdata_39_0_iv_4[19]\, \addr_matrix_f0_1_m_i[19]\, - \addr_matrix_f0_0_m_i[19]\, \prdata_39_0_iv_1[19]\, - \prdata_39_0_iv_3[19]\, \addr_data_f2_m_i[19]\, - \prdata_39_0_iv_2[19]\, \addr_data_f1_m_i[19]\, - prdata_4_sqmuxa, \addr_matrix_f1[19]\, - \addr_matrix_f2_m_i[19]\, \prdata_39_0_iv_4[20]\, - \addr_matrix_f0_1_m_i[20]\, \addr_matrix_f0_0_m_i[20]\, - \prdata_39_0_iv_1[20]\, \prdata_39_0_iv_3[20]\, - \addr_data_f2_m_i[20]\, \prdata_39_0_iv_2[20]\, - \addr_data_f1_m_i[20]\, \addr_matrix_f1[20]\, - \addr_matrix_f2_m_i[20]\, \prdata_39_0_iv_5[21]\, - \addr_data_f3_m_i[21]\, \addr_data_f2_m_i[21]\, - \prdata_39_0_iv_2[21]\, \addr_data_f1_m_i[21]\, - \prdata_39_0_iv_1[21]\, \addr_matrix_f1[21]\, - \addr_matrix_f2_m_i[21]\, \prdata_39_0_iv_0[21]\, - \addr_matrix_f0_0[21]\, \addr_matrix_f0_1_m_i[21]\, - \prdata_39_0_iv_4[22]\, \addr_matrix_f0_1_m_i[22]\, - \addr_matrix_f0_0_m_i[22]\, \prdata_39_0_iv_1[22]\, - \prdata_39_0_iv_3[22]\, \addr_data_f2_m_i[22]\, - \prdata_39_0_iv_2[22]\, \addr_data_f1_m_i[22]\, - \addr_matrix_f1[22]\, \addr_matrix_f2_m_i[22]\, - \prdata_39_0_iv_5[23]\, \addr_data_f3_m_i[23]\, - \addr_data_f2_m_i[23]\, \prdata_39_0_iv_2[23]\, - prdata_9_sqmuxa, \addr_data_f1_m_i[23]\, - \prdata_39_0_iv_1[23]\, \addr_matrix_f1[23]\, - \addr_matrix_f2_m_i[23]\, \prdata_39_0_iv_0[23]\, - \addr_matrix_f0_0[23]\, \addr_matrix_f0_1_m_i[23]\, - \prdata_39_0_iv_4[24]\, \addr_matrix_f0_1_m_i[24]\, - \addr_matrix_f0_0_m_i[24]\, \prdata_39_0_iv_1[24]\, - \prdata_39_0_iv_3[24]\, \addr_data_f2_m_i[24]\, - \prdata_39_0_iv_2[24]\, \addr_data_f1_m_i[24]\, - \addr_matrix_f1[24]\, \addr_matrix_f2_m_i[24]\, - \prdata_39_0_iv_4[25]\, \addr_matrix_f0_1_m_i[25]\, - \addr_matrix_f0_0_m_i[25]\, \prdata_39_0_iv_1[25]\, - \prdata_39_0_iv_3[25]\, \addr_data_f2_m_i[25]\, - \prdata_39_0_iv_2[25]\, \addr_data_f1_m_i[25]\, - \addr_matrix_f1[25]\, \addr_matrix_f2_m_i[25]\, - \prdata_39_0_iv_4[26]\, \addr_matrix_f0_1_m_i[26]\, - \addr_matrix_f0_0_m_i[26]\, \prdata_39_0_iv_1[26]\, - \prdata_39_0_iv_3[26]\, \addr_data_f2_m_i[26]\, - \prdata_39_0_iv_2[26]\, \addr_data_f1_m_i[26]\, - \addr_matrix_f1[26]\, \addr_matrix_f2_m_i[26]\, - \prdata_39_0_iv_4[27]\, \addr_matrix_f0_1_m_i[27]\, - \addr_matrix_f0_0_m_i[27]\, \prdata_39_0_iv_1[27]\, - \prdata_39_0_iv_3[27]\, prdata_12_sqmuxa, - \addr_data_f2_m_i[27]\, \prdata_39_0_iv_2[27]\, - \addr_data_f1_m_i[27]\, \addr_matrix_f1[27]\, - \addr_matrix_f2_m_i[27]\, \prdata_39_0_iv_4[28]\, - \addr_matrix_f0_1_m_i[28]\, \addr_matrix_f0_0_m_i[28]\, - \prdata_39_0_iv_1[28]\, \prdata_39_0_iv_3[28]\, - \addr_data_f2_m_i[28]\, \prdata_39_0_iv_2[28]\, - \addr_data_f1_m_i[28]\, \addr_matrix_f1[28]\, - \addr_matrix_f2_m_i[28]\, \prdata_39_0_iv_4[29]\, - \addr_matrix_f0_1_m_i[29]\, \addr_matrix_f0_0_m_i[29]\, - \prdata_39_0_iv_1[29]\, \prdata_39_0_iv_3[29]\, - \addr_data_f2_m_i[29]\, \prdata_39_0_iv_2[29]\, - \addr_data_f1_m_i[29]\, \addr_matrix_f1[29]\, - \addr_matrix_f2_m_i[29]\, \prdata_39_0_iv_4[30]\, - \addr_matrix_f0_1_m_i[30]\, \addr_matrix_f0_0_m_i[30]\, - \prdata_39_0_iv_1[30]\, \prdata_39_0_iv_3[30]\, - \addr_data_f2_m_i[30]\, \prdata_39_0_iv_2[30]\, - \addr_data_f1_m_i[30]\, \addr_matrix_f1[30]\, - \addr_matrix_f2_m_i[30]\, \prdata_39_0_iv_4[31]\, - \addr_matrix_f0_1_m_i[31]\, \addr_matrix_f0_0_m_i[31]\, - \prdata_39_0_iv_1[31]\, \prdata_39_0_iv_3[31]\, - \addr_data_f2_m_i[31]\, \prdata_39_0_iv_2[31]\, - \addr_data_f1_m_i[31]\, \addr_matrix_f1[31]\, - \addr_matrix_f2_m_i[31]\, \pirq_2_i_a2_8[15]\, - \pirq_2_i_a2_5[15]\, \pirq_2_i_a2_7[15]\, - \pirq_2_i_a2_3[15]\, \pirq_2_i_a2_6[15]\, - \pirq_2_i_a2_1[15]\, N_153, \status_new_err_0[3]\, N_151, - N_149, N_147, N_145, N_143, N_141, N_139, N_137, - \status_full_0[2]\, N_136, \status_full_0[1]\, N_135, - \status_full_0[0]\, \prdata_39[31]\, \prdata_39[30]\, - \prdata_39[29]\, \prdata_39[28]\, \prdata_39[27]\, - \prdata_39[26]\, \prdata_39[25]\, \prdata_39[24]\, - \prdata_39[23]\, \prdata_39[22]\, \prdata_39[21]\, - \prdata_39[20]\, \prdata_39[19]\, \prdata_39[18]\, - \prdata_39[17]\, \prdata_39[16]\, \prdata_39[15]\, - \prdata_39[14]\, \delta_snapshot_m_i[14]\, - \prdata_39[13]\, \delta_snapshot_m_i[13]\, - \prdata_39[11]\, \prdata_39[10]\, - \nb_burst_available_m_i[10]\, \prdata_39[9]\, - \prdata_39[8]\, \prdata_39[7]\, \prdata_39[6]\, - \prdata_39[5]\, \prdata_39[4]\, \prdata_39[3]\, - data_shaping_R0_m_i, \prdata_39[2]\, \prdata_39[1]\, - \prdata_39[0]\, \prdata_39[12]\, \delta_snapshot_m_i[12]\, - N_155_i_0, N_138, \status_full_0[3]\, - status_ready_matrix_f0_1, N_169, \addr_matrix_f0_0[1]\, - \addr_matrix_f0_1[1]\, \addr_matrix_f1[1]\, - \addr_matrix_f2[1]\, N_163, prdata_8_sqmuxa, - status_ready_matrix_f1, \addr_matrix_f0_0[2]\, - \addr_matrix_f0_1[2]\, \addr_matrix_f2[2]\, - status_ready_matrix_f2, \addr_matrix_f0_0[3]\, - \addr_matrix_f0_1[3]\, \addr_matrix_f2[3]\, - \data_shaping_R0_0\, status_error_anticipating_empty_fifo, - \addr_matrix_f0_0[4]\, \addr_matrix_f0_1[4]\, - \addr_matrix_f2[4]\, \data_shaping_R1_0\, - status_error_bad_component_error, \addr_matrix_f0_0[5]\, - \addr_matrix_f0_1[5]\, \addr_matrix_f2[5]\, - \addr_matrix_f0_0[6]\, \addr_matrix_f0_1[6]\, - \addr_matrix_f1[6]\, \addr_matrix_f2[6]\, - \addr_matrix_f0_0[7]\, \addr_matrix_f0_1[7]\, - \addr_matrix_f2[7]\, \addr_matrix_f0_1[8]\, - \addr_matrix_f1[8]\, \addr_matrix_f2[8]\, - \addr_matrix_f0_0[9]\, \addr_matrix_f0_1[9]\, - \addr_matrix_f2[9]\, \addr_matrix_f0_1[10]\, - \addr_matrix_f2[10]\, prdata_2_sqmuxa, - \addr_matrix_f0_0[11]\, \addr_matrix_f0_1[11]\, - \addr_matrix_f2[11]\, \addr_matrix_f0_1[12]\, - \addr_matrix_f2[12]\, \addr_matrix_f0_1[13]\, - \addr_matrix_f2[13]\, \addr_matrix_f0_1[14]\, - \addr_matrix_f2[14]\, \addr_matrix_f0_0[15]\, - \addr_matrix_f0_1[15]\, \addr_matrix_f2[15]\, - \addr_matrix_f0_0[16]\, \addr_matrix_f0_1[16]\, - \addr_matrix_f2[16]\, \addr_matrix_f0_0[17]\, - prdata_3_sqmuxa, \addr_matrix_f0_1[17]\, prdata_5_sqmuxa, - \addr_matrix_f2[17]\, N_161, \addr_matrix_f0_1[18]\, - \addr_matrix_f2[18]\, prdata_10_sqmuxa, - \addr_matrix_f0_0[19]\, \addr_matrix_f0_1[19]\, - \addr_matrix_f2[19]\, \addr_matrix_f0_0[20]\, - \addr_matrix_f0_1[20]\, \addr_matrix_f2[20]\, - \addr_matrix_f0_1[21]\, \addr_matrix_f2[21]\, - \addr_matrix_f0_0[22]\, \addr_matrix_f0_1[22]\, - \addr_matrix_f2[22]\, \addr_matrix_f0_1[23]\, - \addr_matrix_f2[23]\, \addr_matrix_f0_0[24]\, - \addr_matrix_f0_1[24]\, \addr_matrix_f2[24]\, - \addr_matrix_f0_0[25]\, \addr_matrix_f0_1[25]\, - \addr_matrix_f2[25]\, \addr_matrix_f0_0[26]\, - \addr_matrix_f0_1[26]\, \addr_matrix_f2[26]\, - \addr_matrix_f0_0[27]\, \addr_matrix_f0_1[27]\, - \addr_matrix_f2[27]\, \addr_matrix_f0_0[28]\, - \addr_matrix_f0_1[28]\, \addr_matrix_f2[28]\, - \addr_matrix_f0_0[29]\, \addr_matrix_f0_1[29]\, - \addr_matrix_f2[29]\, \addr_matrix_f0_0[30]\, - \addr_matrix_f0_1[30]\, \addr_matrix_f2[30]\, - \addr_matrix_f0_0[31]\, \addr_matrix_f0_1[31]\, - \addr_matrix_f2[31]\, addr_matrix_f0_0_1_sqmuxa, - addr_matrix_f0_1_1_sqmuxa, addr_matrix_f1_1_sqmuxa, - addr_matrix_f2_1_sqmuxa, addr_data_f0_1_sqmuxa, - addr_data_f1_1_sqmuxa, addr_data_f2_1_sqmuxa, - addr_data_f3_1_sqmuxa, burst_f0_1_sqmuxa, - delta_f2_f0_1_sqmuxa, N_164, delta_f2_f1_1_sqmuxa, - delta_snapshot_1_sqmuxa, nb_burst_available_1_sqmuxa, - N_158, nb_snapshot_param_1_sqmuxa, \status_full_ack_8[2]\, - \status_full_ack_8[1]\, \status_full_ack_8[0]\, - \status_full_5_i_o2[0]\, \status_full_RNO[0]\, - \status_full_RNO[1]\, \status_full_RNO[2]\, - \status_full_err_RNO[0]\, \status_full_err_RNO[1]\, - \status_full_err_RNO[2]\, \status_full_err_RNO[3]\, - \status_new_err_RNO[0]\, \status_new_err_RNO[1]\, - \status_new_err_RNO[2]\, \status_new_err_RNO[3]\, - status_error_anticipating_empty_fifo_1_sqmuxa, - config_active_interruption_onError_0_sqmuxa, - \addr_matrix_f2[0]\, \addr_matrix_f0_1[0]\, - \addr_matrix_f0_0[0]\, status_ready_matrix_f0_0, - \status_full_ack_8[3]\, \status_full_RNO[3]\, \enable_f3\, - \enable_f2\, \enable_f1\, \enable_f0\, \data_shaping_SP1\, - \data_shaping_SP0\, \data_shaping_BW_c\, \burst_f2\, - \burst_f1\, \burst_f0\, \addr_data_f1[0]\, - \addr_data_f1[1]\, \addr_data_f1[2]\, \addr_data_f1[3]\, - \addr_data_f1[4]\, \addr_data_f1[5]\, \addr_data_f1[6]\, - \addr_data_f1[7]\, \addr_data_f1[8]\, \addr_data_f1[9]\, - \addr_data_f1[10]\, \addr_data_f1[11]\, - \addr_data_f1[12]\, \addr_data_f1[13]\, - \addr_data_f1[14]\, \addr_data_f1[15]\, - \addr_data_f1[16]\, \addr_data_f1[17]\, - \addr_data_f1[18]\, \addr_data_f1[19]\, - \addr_data_f1[20]\, \addr_data_f1[21]\, - \addr_data_f1[22]\, \addr_data_f1[23]\, - \addr_data_f1[24]\, \addr_data_f1[25]\, - \addr_data_f1[26]\, \addr_data_f1[27]\, - \addr_data_f1[28]\, \addr_data_f1[29]\, - \addr_data_f1[30]\, \addr_data_f1[31]\, \addr_data_f0[0]\, - \addr_data_f0[1]\, \addr_data_f0[2]\, \addr_data_f0[3]\, - \addr_data_f0[4]\, \addr_data_f0[5]\, \addr_data_f0[6]\, - \addr_data_f0[7]\, \addr_data_f0[8]\, \addr_data_f0[9]\, - \addr_data_f0[10]\, \addr_data_f0[11]\, - \addr_data_f0[12]\, \addr_data_f0[13]\, - \addr_data_f0[14]\, \addr_data_f0[15]\, - \addr_data_f0[16]\, \addr_data_f0[17]\, - \addr_data_f0[18]\, \addr_data_f0[19]\, - \addr_data_f0[20]\, \addr_data_f0[21]\, - \addr_data_f0[22]\, \addr_data_f0[23]\, - \addr_data_f0[24]\, \addr_data_f0[25]\, - \addr_data_f0[26]\, \addr_data_f0[27]\, - \addr_data_f0[28]\, \addr_data_f0[29]\, - \addr_data_f0[30]\, \addr_data_f0[31]\, - \delta_snapshot[0]\, \delta_snapshot[1]\, - \delta_snapshot[2]\, \delta_snapshot[3]\, - \delta_snapshot[4]\, \delta_snapshot[5]\, - \delta_snapshot[6]\, \delta_snapshot[7]\, - \delta_snapshot[8]\, \delta_snapshot[9]\, - \delta_snapshot[10]\, \delta_snapshot[11]\, - \delta_snapshot[12]\, \delta_snapshot[13]\, - \delta_snapshot[14]\, \delta_snapshot[15]\, - \nb_snapshot_param[0]\, \nb_snapshot_param[1]\, - \nb_snapshot_param[2]\, \nb_snapshot_param[3]\, - \nb_snapshot_param[4]\, \nb_snapshot_param[5]\, - \nb_snapshot_param[6]\, \nb_snapshot_param[7]\, - \nb_snapshot_param[8]\, \nb_snapshot_param[9]\, - \nb_snapshot_param[10]\, \nb_burst_available[0]\, - \nb_burst_available[1]\, \nb_burst_available[2]\, - \nb_burst_available[3]\, \nb_burst_available[4]\, - \nb_burst_available[5]\, \nb_burst_available[6]\, - \nb_burst_available[7]\, \nb_burst_available[8]\, - \nb_burst_available[9]\, \nb_burst_available[10]\, - \delta_f2_f1[0]\, \delta_f2_f1[1]\, \delta_f2_f1[2]\, - \delta_f2_f1[3]\, \delta_f2_f1[4]\, \delta_f2_f1[5]\, - \delta_f2_f1[6]\, \delta_f2_f1[7]\, \delta_f2_f1[8]\, - \delta_f2_f1[9]\, \delta_f2_f0[0]\, \delta_f2_f0[1]\, - \delta_f2_f0[2]\, \delta_f2_f0[3]\, \delta_f2_f0[4]\, - \delta_f2_f0[5]\, \delta_f2_f0[6]\, \delta_f2_f0[7]\, - \delta_f2_f0[8]\, \delta_f2_f0[9]\, \addr_data_f3[0]\, - \addr_data_f3[1]\, \addr_data_f3[2]\, \addr_data_f3[3]\, - \addr_data_f3[4]\, \addr_data_f3[5]\, \addr_data_f3[6]\, - \addr_data_f3[7]\, \addr_data_f3[8]\, \addr_data_f3[9]\, - \addr_data_f3[10]\, \addr_data_f3[11]\, - \addr_data_f3[12]\, \addr_data_f3[13]\, - \addr_data_f3[14]\, \addr_data_f3[15]\, - \addr_data_f3[16]\, \addr_data_f3[17]\, - \addr_data_f3[18]\, \addr_data_f3[19]\, - \addr_data_f3[20]\, \addr_data_f3[21]\, - \addr_data_f3[22]\, \addr_data_f3[23]\, - \addr_data_f3[24]\, \addr_data_f3[25]\, - \addr_data_f3[26]\, \addr_data_f3[27]\, - \addr_data_f3[28]\, \addr_data_f3[29]\, - \addr_data_f3[30]\, \addr_data_f3[31]\, \addr_data_f2[0]\, - \addr_data_f2[1]\, \addr_data_f2[2]\, \addr_data_f2[3]\, - \addr_data_f2[4]\, \addr_data_f2[5]\, \addr_data_f2[6]\, - \addr_data_f2[7]\, \addr_data_f2[8]\, \addr_data_f2[9]\, - \addr_data_f2[10]\, \addr_data_f2[11]\, - \addr_data_f2[12]\, \addr_data_f2[13]\, - \addr_data_f2[14]\, \addr_data_f2[15]\, - \addr_data_f2[16]\, \addr_data_f2[17]\, - \addr_data_f2[18]\, \addr_data_f2[19]\, - \addr_data_f2[20]\, \addr_data_f2[21]\, - \addr_data_f2[22]\, \addr_data_f2[23]\, - \addr_data_f2[24]\, \addr_data_f2[25]\, - \addr_data_f2[26]\, \addr_data_f2[27]\, - \addr_data_f2[28]\, \addr_data_f2[29]\, - \addr_data_f2[30]\, \addr_data_f2[31]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - addr_data_f2(31) <= \addr_data_f2[31]\; - addr_data_f2(30) <= \addr_data_f2[30]\; - addr_data_f2(29) <= \addr_data_f2[29]\; - addr_data_f2(28) <= \addr_data_f2[28]\; - addr_data_f2(27) <= \addr_data_f2[27]\; - addr_data_f2(26) <= \addr_data_f2[26]\; - addr_data_f2(25) <= \addr_data_f2[25]\; - addr_data_f2(24) <= \addr_data_f2[24]\; - addr_data_f2(23) <= \addr_data_f2[23]\; - addr_data_f2(22) <= \addr_data_f2[22]\; - addr_data_f2(21) <= \addr_data_f2[21]\; - addr_data_f2(20) <= \addr_data_f2[20]\; - addr_data_f2(19) <= \addr_data_f2[19]\; - addr_data_f2(18) <= \addr_data_f2[18]\; - addr_data_f2(17) <= \addr_data_f2[17]\; - addr_data_f2(16) <= \addr_data_f2[16]\; - addr_data_f2(15) <= \addr_data_f2[15]\; - addr_data_f2(14) <= \addr_data_f2[14]\; - addr_data_f2(13) <= \addr_data_f2[13]\; - addr_data_f2(12) <= \addr_data_f2[12]\; - addr_data_f2(11) <= \addr_data_f2[11]\; - addr_data_f2(10) <= \addr_data_f2[10]\; - addr_data_f2(9) <= \addr_data_f2[9]\; - addr_data_f2(8) <= \addr_data_f2[8]\; - addr_data_f2(7) <= \addr_data_f2[7]\; - addr_data_f2(6) <= \addr_data_f2[6]\; - addr_data_f2(5) <= \addr_data_f2[5]\; - addr_data_f2(4) <= \addr_data_f2[4]\; - addr_data_f2(3) <= \addr_data_f2[3]\; - addr_data_f2(2) <= \addr_data_f2[2]\; - addr_data_f2(1) <= \addr_data_f2[1]\; - addr_data_f2(0) <= \addr_data_f2[0]\; - addr_data_f3(31) <= \addr_data_f3[31]\; - addr_data_f3(30) <= \addr_data_f3[30]\; - addr_data_f3(29) <= \addr_data_f3[29]\; - addr_data_f3(28) <= \addr_data_f3[28]\; - addr_data_f3(27) <= \addr_data_f3[27]\; - addr_data_f3(26) <= \addr_data_f3[26]\; - addr_data_f3(25) <= \addr_data_f3[25]\; - addr_data_f3(24) <= \addr_data_f3[24]\; - addr_data_f3(23) <= \addr_data_f3[23]\; - addr_data_f3(22) <= \addr_data_f3[22]\; - addr_data_f3(21) <= \addr_data_f3[21]\; - addr_data_f3(20) <= \addr_data_f3[20]\; - addr_data_f3(19) <= \addr_data_f3[19]\; - addr_data_f3(18) <= \addr_data_f3[18]\; - addr_data_f3(17) <= \addr_data_f3[17]\; - addr_data_f3(16) <= \addr_data_f3[16]\; - addr_data_f3(15) <= \addr_data_f3[15]\; - addr_data_f3(14) <= \addr_data_f3[14]\; - addr_data_f3(13) <= \addr_data_f3[13]\; - addr_data_f3(12) <= \addr_data_f3[12]\; - addr_data_f3(11) <= \addr_data_f3[11]\; - addr_data_f3(10) <= \addr_data_f3[10]\; - addr_data_f3(9) <= \addr_data_f3[9]\; - addr_data_f3(8) <= \addr_data_f3[8]\; - addr_data_f3(7) <= \addr_data_f3[7]\; - addr_data_f3(6) <= \addr_data_f3[6]\; - addr_data_f3(5) <= \addr_data_f3[5]\; - addr_data_f3(4) <= \addr_data_f3[4]\; - addr_data_f3(3) <= \addr_data_f3[3]\; - addr_data_f3(2) <= \addr_data_f3[2]\; - addr_data_f3(1) <= \addr_data_f3[1]\; - addr_data_f3(0) <= \addr_data_f3[0]\; - nb_burst_available(10) <= \nb_burst_available[10]\; - nb_burst_available(9) <= \nb_burst_available[9]\; - nb_burst_available(8) <= \nb_burst_available[8]\; - nb_burst_available(7) <= \nb_burst_available[7]\; - nb_burst_available(6) <= \nb_burst_available[6]\; - nb_burst_available(5) <= \nb_burst_available[5]\; - nb_burst_available(4) <= \nb_burst_available[4]\; - nb_burst_available(3) <= \nb_burst_available[3]\; - nb_burst_available(2) <= \nb_burst_available[2]\; - nb_burst_available(1) <= \nb_burst_available[1]\; - nb_burst_available(0) <= \nb_burst_available[0]\; - addr_data_f1(31) <= \addr_data_f1[31]\; - addr_data_f1(30) <= \addr_data_f1[30]\; - addr_data_f1(29) <= \addr_data_f1[29]\; - addr_data_f1(28) <= \addr_data_f1[28]\; - addr_data_f1(27) <= \addr_data_f1[27]\; - addr_data_f1(26) <= \addr_data_f1[26]\; - addr_data_f1(25) <= \addr_data_f1[25]\; - addr_data_f1(24) <= \addr_data_f1[24]\; - addr_data_f1(23) <= \addr_data_f1[23]\; - addr_data_f1(22) <= \addr_data_f1[22]\; - addr_data_f1(21) <= \addr_data_f1[21]\; - addr_data_f1(20) <= \addr_data_f1[20]\; - addr_data_f1(19) <= \addr_data_f1[19]\; - addr_data_f1(18) <= \addr_data_f1[18]\; - addr_data_f1(17) <= \addr_data_f1[17]\; - addr_data_f1(16) <= \addr_data_f1[16]\; - addr_data_f1(15) <= \addr_data_f1[15]\; - addr_data_f1(14) <= \addr_data_f1[14]\; - addr_data_f1(13) <= \addr_data_f1[13]\; - addr_data_f1(12) <= \addr_data_f1[12]\; - addr_data_f1(11) <= \addr_data_f1[11]\; - addr_data_f1(10) <= \addr_data_f1[10]\; - addr_data_f1(9) <= \addr_data_f1[9]\; - addr_data_f1(8) <= \addr_data_f1[8]\; - addr_data_f1(7) <= \addr_data_f1[7]\; - addr_data_f1(6) <= \addr_data_f1[6]\; - addr_data_f1(5) <= \addr_data_f1[5]\; - addr_data_f1(4) <= \addr_data_f1[4]\; - addr_data_f1(3) <= \addr_data_f1[3]\; - addr_data_f1(2) <= \addr_data_f1[2]\; - addr_data_f1(1) <= \addr_data_f1[1]\; - addr_data_f1(0) <= \addr_data_f1[0]\; - delta_f2_f1(9) <= \delta_f2_f1[9]\; - delta_f2_f1(8) <= \delta_f2_f1[8]\; - delta_f2_f1(7) <= \delta_f2_f1[7]\; - delta_f2_f1(6) <= \delta_f2_f1[6]\; - delta_f2_f1(5) <= \delta_f2_f1[5]\; - delta_f2_f1(4) <= \delta_f2_f1[4]\; - delta_f2_f1(3) <= \delta_f2_f1[3]\; - delta_f2_f1(2) <= \delta_f2_f1[2]\; - delta_f2_f1(1) <= \delta_f2_f1[1]\; - delta_f2_f1(0) <= \delta_f2_f1[0]\; - addr_data_f0(31) <= \addr_data_f0[31]\; - addr_data_f0(30) <= \addr_data_f0[30]\; - addr_data_f0(29) <= \addr_data_f0[29]\; - addr_data_f0(28) <= \addr_data_f0[28]\; - addr_data_f0(27) <= \addr_data_f0[27]\; - addr_data_f0(26) <= \addr_data_f0[26]\; - addr_data_f0(25) <= \addr_data_f0[25]\; - addr_data_f0(24) <= \addr_data_f0[24]\; - addr_data_f0(23) <= \addr_data_f0[23]\; - addr_data_f0(22) <= \addr_data_f0[22]\; - addr_data_f0(21) <= \addr_data_f0[21]\; - addr_data_f0(20) <= \addr_data_f0[20]\; - addr_data_f0(19) <= \addr_data_f0[19]\; - addr_data_f0(18) <= \addr_data_f0[18]\; - addr_data_f0(17) <= \addr_data_f0[17]\; - addr_data_f0(16) <= \addr_data_f0[16]\; - addr_data_f0(15) <= \addr_data_f0[15]\; - addr_data_f0(14) <= \addr_data_f0[14]\; - addr_data_f0(13) <= \addr_data_f0[13]\; - addr_data_f0(12) <= \addr_data_f0[12]\; - addr_data_f0(11) <= \addr_data_f0[11]\; - addr_data_f0(10) <= \addr_data_f0[10]\; - addr_data_f0(9) <= \addr_data_f0[9]\; - addr_data_f0(8) <= \addr_data_f0[8]\; - addr_data_f0(7) <= \addr_data_f0[7]\; - addr_data_f0(6) <= \addr_data_f0[6]\; - addr_data_f0(5) <= \addr_data_f0[5]\; - addr_data_f0(4) <= \addr_data_f0[4]\; - addr_data_f0(3) <= \addr_data_f0[3]\; - addr_data_f0(2) <= \addr_data_f0[2]\; - addr_data_f0(1) <= \addr_data_f0[1]\; - addr_data_f0(0) <= \addr_data_f0[0]\; - delta_f2_f0(9) <= \delta_f2_f0[9]\; - delta_f2_f0(8) <= \delta_f2_f0[8]\; - delta_f2_f0(7) <= \delta_f2_f0[7]\; - delta_f2_f0(6) <= \delta_f2_f0[6]\; - delta_f2_f0(5) <= \delta_f2_f0[5]\; - delta_f2_f0(4) <= \delta_f2_f0[4]\; - delta_f2_f0(3) <= \delta_f2_f0[3]\; - delta_f2_f0(2) <= \delta_f2_f0[2]\; - delta_f2_f0(1) <= \delta_f2_f0[1]\; - delta_f2_f0(0) <= \delta_f2_f0[0]\; - delta_snapshot(15) <= \delta_snapshot[15]\; - delta_snapshot(14) <= \delta_snapshot[14]\; - delta_snapshot(13) <= \delta_snapshot[13]\; - delta_snapshot(12) <= \delta_snapshot[12]\; - delta_snapshot(11) <= \delta_snapshot[11]\; - delta_snapshot(10) <= \delta_snapshot[10]\; - delta_snapshot(9) <= \delta_snapshot[9]\; - delta_snapshot(8) <= \delta_snapshot[8]\; - delta_snapshot(7) <= \delta_snapshot[7]\; - delta_snapshot(6) <= \delta_snapshot[6]\; - delta_snapshot(5) <= \delta_snapshot[5]\; - delta_snapshot(4) <= \delta_snapshot[4]\; - delta_snapshot(3) <= \delta_snapshot[3]\; - delta_snapshot(2) <= \delta_snapshot[2]\; - delta_snapshot(1) <= \delta_snapshot[1]\; - delta_snapshot(0) <= \delta_snapshot[0]\; - nb_snapshot_param(10) <= \nb_snapshot_param[10]\; - nb_snapshot_param(9) <= \nb_snapshot_param[9]\; - nb_snapshot_param(8) <= \nb_snapshot_param[8]\; - nb_snapshot_param(7) <= \nb_snapshot_param[7]\; - nb_snapshot_param(6) <= \nb_snapshot_param[6]\; - nb_snapshot_param(5) <= \nb_snapshot_param[5]\; - nb_snapshot_param(4) <= \nb_snapshot_param[4]\; - nb_snapshot_param(3) <= \nb_snapshot_param[3]\; - nb_snapshot_param(2) <= \nb_snapshot_param[2]\; - nb_snapshot_param(1) <= \nb_snapshot_param[1]\; - nb_snapshot_param(0) <= \nb_snapshot_param[0]\; - enable_f0 <= \enable_f0\; - data_shaping_BW_c <= \data_shaping_BW_c\; - burst_f2 <= \burst_f2\; - burst_f1 <= \burst_f1\; - burst_f0 <= \burst_f0\; - enable_f3 <= \enable_f3\; - enable_f2 <= \enable_f2\; - data_shaping_SP1 <= \data_shaping_SP1\; - enable_f1 <= \enable_f1\; - data_shaping_SP0 <= \data_shaping_SP0\; - data_shaping_R1_0 <= \data_shaping_R1_0\; - data_shaping_R0_0 <= \data_shaping_R0_0\; - - \prdata_RNO_7[29]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[29]\, C - => \addr_matrix_f2_m_i[29]\, Y => \prdata_39_0_iv_1[29]\); - - \reg_wp.addr_data_f3[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[17]\); - - \reg_wp.delta_f2_f1[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[1]\); - - \reg_sp.addr_matrix_f1[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[6]\); - - \prdata_RNO_5[14]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[14]\, C => \addr_matrix_f0_1_m_i[14]\, - Y => \prdata_39_0_iv_0[14]\); - - \prdata_RNO_2[14]\ : NOR3C - port map(A => \prdata_39_0_iv_1[14]\, B => - \prdata_39_0_iv_0[14]\, C => \prdata_39_0_iv_3[14]\, Y - => \prdata_39_0_iv_6[14]\); - - \reg_sp.addr_matrix_f0_0[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[2]\); - - \reg_wp.addr_data_f3[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[25]\); - - \prdata_RNO_0[8]\ : NOR3C - port map(A => \prdata_39_0_iv_0[8]\, B => - \delta_f2_f1_m_i[8]\, C => \prdata_39_0_iv_6[8]\, Y => - \prdata_39_0_iv_9[8]\); - - \reg_wp.addr_data_f3[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[26]\); - - \reg_wp.nb_snapshot_param[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[2]\); - - \reg_wp.delta_f2_f0[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[2]\); - - \reg_wp.addr_data_f3_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_168, B => N_157, C => un1_apbi_2, Y => - addr_data_f3_1_sqmuxa); - - \prdata_RNO_5[7]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[7]\, B => - \addr_matrix_f0_0_m_i[7]\, C => \delta_f2_f1_m_i[7]\, Y - => \prdata_39_0_iv_5[7]\); - - \reg_wp.addr_data_f2[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[29]\); - - prdata_18_sqmuxa_0_a2 : NOR3C - port map(A => N_158, B => N_159, C => apbi_c_19, Y => - prdata_18_sqmuxa); - - \reg_sp.addr_matrix_f0_1[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[22]\); - - \prdata_RNO_7[3]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[3]\, B => - \addr_matrix_f0_0_m_i[3]\, C => \status_full_m_i[3]\, Y - => \prdata_39_0_iv_6[3]\); - - \prdata_RNO_8[28]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[28]\, Y - => \addr_matrix_f2_m_i[28]\); - - \prdata_RNO_6[1]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[1]\, C - => enable_f1_m_i, Y => \prdata_39_0_iv_8[1]\); - - \prdata_RNO_4[29]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[29]\, Y - => \addr_data_f1_m_i[29]\); - - \reg_wp.nb_snapshot_param[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[9]\); - - \reg_wp.nb_burst_available[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[7]\); - - \prdata_RNO[8]\ : OR3C - port map(A => \prdata_39_0_iv_9[8]\, B => - \prdata_39_0_iv_8[8]\, C => \prdata_39_0_iv_10[8]\, Y => - \prdata_39[8]\); - - \prdata_RNO_1[13]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[13]\, - Y => \delta_snapshot_m_i[13]\); - - \prdata_RNO_6[18]\ : OR3C - port map(A => N_161, B => N_168_0, C => \addr_data_f2[18]\, - Y => \addr_data_f2_m_i[18]\); - - \prdata[26]\ : DFN1C0 - port map(D => \prdata_39[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(26)); - - \prdata_RNO_19[0]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[0]\, C - => data_shaping_BW_m_i, Y => \prdata_39_0_iv_5[0]\); - - \reg_sp.addr_matrix_f0_0[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[4]\); - - \prdata_RNO_0[29]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[29]\, C - => \addr_data_f2_m_i[29]\, Y => \prdata_39_0_iv_3[29]\); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2_2\ : NOR3B - port map(A => apbi_c_0, B => apbi_c_23, C => apbi_c_24, Y - => N_158); - - \reg_wp.addr_data_f0_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_930, B => apbi_c_21, C => N_931, Y => - addr_data_f0_1_sqmuxa); - - \prdata_RNO_7[10]\ : OR2B - port map(A => \nb_snapshot_param[10]\, B => - prdata_18_sqmuxa, Y => \nb_snapshot_param_m_i[10]\); - - \reg_wp.addr_data_f2[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[13]\); - - \reg_wp.addr_data_f2[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[10]\); - - \reg_sp.addr_matrix_f0_1[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[2]\); - - \reg_wp.addr_data_f3[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[2]\); - - \reg_wp.addr_data_f3_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_168, B => N_157, C => un1_apbi_2, Y => - addr_data_f3_1_sqmuxa_0); - - \reg_sp.addr_matrix_f0_1[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[1]\); - - \prdata_RNO_11[1]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[1]\, Y - => \addr_data_f1_m_i[1]\); - - \apbo.pirq_RNO_4[15]\ : NOR2 - port map(A => status_new_err_0_2, B => status_new_err_3, Y - => \pirq_2_i_a2_1[15]\); - - \prdata_RNO_4[14]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[14]\, - C => \addr_matrix_f2_m_i[14]\, Y => - \prdata_39_0_iv_1[14]\); - - \reg_sp.addr_matrix_f0_0[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[31]\); - - \prdata_RNO_13[6]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[6]\, Y - => \delta_f2_f1_m_i[6]\); - - \prdata_RNO_16[6]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[6]\, Y - => \delta_f2_f0_m_i[6]\); - - \reg_sp.addr_matrix_f0_1[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[19]\); - - \reg_sp.status_ready_matrix_f2\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f2); - - \prdata_RNO_6[20]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[20]\, - Y => \addr_matrix_f0_0_m_i[20]\); - - \reg_wp.addr_data_f0[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[8]\); - - \prdata_RNO_6[4]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[4]\, B => - \addr_matrix_f0_0_m_i[4]\, C => \prdata_39_0_iv_1[4]\, Y - => \prdata_39_0_iv_6[4]\); - - \prdata_RNO_6[31]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[31]\, - Y => \addr_matrix_f0_0_m_i[31]\); - - \apbo.pirq_RNO_0[15]\ : NOR3A - port map(A => \pirq_2_i_a2_3[15]\, B => - status_full_err_0(1), C => status_full_err_0(0), Y => - \pirq_2_i_a2_7[15]\); - - \reg_sp.addr_matrix_f0_1[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[9]\); - - \prdata_RNO_3[6]\ : NOR3C - port map(A => \addr_matrix_f2_m_i[6]\, B => - \addr_matrix_f1_m_i[6]\, C => \delta_snapshot_m_i[6]\, Y - => \prdata_39_0_iv_6[6]\); - - \prdata_RNO_18[1]\ : OR2B - port map(A => \status_full_0[1]\, B => prdata_13_sqmuxa, Y - => \status_full_m_i[1]\); - - \reg_wp.delta_snapshot_1_sqmuxa_0_o2_0\ : OR3C - port map(A => apbi_c_22, B => N_928, C => apbi_c_20, Y => - N_931); - - \reg_sp.addr_matrix_f0_0[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[24]\); - - \prdata_RNO_11[10]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[10]\, Y - => \addr_data_f0_m_i[10]\); - - \reg_wp.addr_data_f2[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[11]\); - - \reg_sp.addr_matrix_f0_0[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[25]\); - - \reg_sp.addr_matrix_f0_0[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[16]\); - - \prdata_RNO_9[6]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[6]\, Y - => \addr_matrix_f1_m_i[6]\); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2_0\ : NOR2A - port map(A => apbi_c_19, B => un1_apbi_2, Y => N_166); - - \prdata_RNO_9[7]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[7]\, C - => \addr_data_f2_m_i[7]\, Y => \prdata_39_0_iv_3[7]\); - - \prdata_RNO_8[0]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[0]\, C - => \addr_data_f1_m_i[0]\, Y => \prdata_39_0_iv_3[0]\); - - \prdata_RNO_16[9]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[9]\, - Y => \addr_data_f2_m_i[9]\); - - \prdata_RNO[7]\ : OR3C - port map(A => \prdata_39_0_iv_9[7]\, B => - \prdata_39_0_iv_8[7]\, C => \prdata_39_0_iv_10[7]\, Y => - \prdata_39[7]\); - - \prdata_RNO_5[13]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[13]\, C => \addr_matrix_f0_1_m_i[13]\, - Y => \prdata_39_0_iv_0[13]\); - - \prdata_RNO_2[13]\ : NOR3C - port map(A => \prdata_39_0_iv_1[13]\, B => - \prdata_39_0_iv_0[13]\, C => \prdata_39_0_iv_3[13]\, Y - => \prdata_39_0_iv_6[13]\); - - prdata_16_sqmuxa_0_a2 : NOR2A - port map(A => N_164, B => N_157, Y => prdata_16_sqmuxa); - - \prdata_RNO_7[1]\ : NOR3C - port map(A => \addr_matrix_f2_m_i[1]\, B => - \addr_matrix_f1_m_i[1]\, C => \prdata_39_0_iv_2[1]\, Y - => \prdata_39_0_iv_7[1]\); - - \reg_wp.addr_data_f3[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[5]\); - - \prdata_RNO_9[15]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[15]\, - Y => \delta_snapshot_m_i[15]\); - - \prdata_RNO_7[25]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[25]\, C - => \addr_matrix_f2_m_i[25]\, Y => \prdata_39_0_iv_1[25]\); - - \prdata_RNO_10[2]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[2]\, - Y => \addr_data_f2_m_i[2]\); - - \reg_wp.addr_data_f3[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[22]\); - - \reg_wp.status_new_err_RNO_0[3]\ : NOR3A - port map(A => N_933_0, B => \status_new_err_0[3]\, C => - status_new_err_3, Y => N_153); - - \prdata_RNO_8[27]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[27]\, Y - => \addr_matrix_f2_m_i[27]\); - - \reg_sp.addr_matrix_f0_1[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[4]\); - - \reg_wp.burst_f2\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \burst_f2\); - - \reg_sp.addr_matrix_f1[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[0]\); - - \prdata_RNO_11[7]\ : OR2B - port map(A => \nb_burst_available[7]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[7]\); - - \reg_wp.status_full_err[3]\ : DFN1C0 - port map(D => \status_full_err_RNO[3]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_full_err[3]\); - - \prdata_RNO_20[1]\ : OR3A - port map(A => status_ready_matrix_f0_1, B => N_157, C => - N_169, Y => status_ready_matrix_f0_1_m_i); - - \prdata_RNO_19[4]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[4]\, - Y => \addr_matrix_f2_m_i[4]\); - - \prdata_RNO_2[24]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[24]\, B => - \addr_matrix_f0_0_m_i[24]\, C => \prdata_39_0_iv_1[24]\, - Y => \prdata_39_0_iv_4[24]\); - - \prdata_RNO_8[4]\ : NOR3C - port map(A => \addr_data_f3_m_i[4]\, B => - \addr_data_f2_m_i[4]\, C => \prdata_39_0_iv_5[4]\, Y => - \prdata_39_0_iv_9[4]\); - - \prdata_RNO[18]\ : OR3C - port map(A => \prdata_39_0_iv_1[18]\, B => - \prdata_39_0_iv_0[18]\, C => \prdata_39_0_iv_5[18]\, Y - => \prdata_39[18]\); - - \status_full_ack[1]\ : DFN1C0 - port map(D => \status_full_ack_8[1]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => status_full_ack(1)); - - \prdata_RNO_1[30]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[30]\, C - => \addr_data_f1_m_i[30]\, Y => \prdata_39_0_iv_2[30]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_o2\ : NOR2 - port map(A => un1_apbi_2, B => apbi_c_19, Y => N_930); - - \prdata_RNO_6[17]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[17]\, - Y => \addr_matrix_f0_0_m_i[17]\); - - \reg_sp.addr_matrix_f1[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[8]\); - - \prdata_RNO_4[25]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[25]\, Y - => \addr_data_f1_m_i[25]\); - - \prdata_RNO_1[3]\ : NOR3C - port map(A => \prdata_39_0_iv_3[3]\, B => - \prdata_39_0_iv_2[3]\, C => \prdata_39_0_iv_9[3]\, Y => - \prdata_39_0_iv_12[3]\); - - \prdata_RNO_16[8]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[8]\, - Y => \addr_data_f2_m_i[8]\); - - \prdata_RNO_5[21]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[21]\, Y - => \addr_data_f3_m_i[21]\); - - \prdata_RNO_5[26]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[26]\, - Y => \addr_matrix_f0_1_m_i[26]\); - - prdata_0_sqmuxa_0_a2_0 : NOR2 - port map(A => apbi_c_20, B => apbi_c_19, Y => N_161); - - \prdata[7]\ : DFN1C0 - port map(D => \prdata_39[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(7)); - - \reg_sp.config_active_interruption_onError\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => config_active_interruption_onError_0_sqmuxa, Q => - config_active_interruption_onError); - - \prdata_RNO_3[19]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[19]\, Y - => \addr_data_f2_m_i[19]\); - - \prdata_RNO_4[5]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f1\, Y => - burst_f1_m_i); - - \prdata_RNO_7[28]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[28]\, C - => \addr_matrix_f2_m_i[28]\, Y => \prdata_39_0_iv_1[28]\); - - \reg_wp.delta_f2_f1[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[7]\); - - \prdata_RNO_12[0]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[0]\, - Y => \addr_matrix_f0_1_m_i[0]\); - - \prdata_RNO_0[25]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[25]\, - C => \addr_data_f2_m_i[25]\, Y => \prdata_39_0_iv_3[25]\); - - \prdata[14]\ : DFN1C0 - port map(D => \prdata_39[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(14)); - - \prdata_RNO_11[3]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[3]\, Y - => \delta_f2_f0_m_i[3]\); - - \prdata_RNO_4[13]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[13]\, - C => \addr_matrix_f2_m_i[13]\, Y => - \prdata_39_0_iv_1[13]\); - - \prdata_RNO_2[9]\ : NOR3C - port map(A => \prdata_39_0_iv_3[9]\, B => - \prdata_39_0_iv_2[9]\, C => \nb_burst_available_m_i[9]\, - Y => \prdata_39_0_iv_10[9]\); - - prdata_12_sqmuxa_0_a2_0 : NOR2A - port map(A => N_168, B => N_157, Y => prdata_12_sqmuxa_0); - - \reg_wp.status_full_RNO_0[2]\ : NOR3A - port map(A => N_933_0, B => \status_full_0[2]\, C => - status_full(2), Y => N_137); - - \prdata_RNO_12[4]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[4]\, - Y => \addr_matrix_f0_1_m_i[4]\); - - \prdata_RNO_5[22]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[22]\, - Y => \addr_matrix_f0_1_m_i[22]\); - - \reg_wp.addr_data_f2[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[15]\); - - \reg_wp.addr_data_f2[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[16]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_a2\ : - NOR3A - port map(A => N_930, B => apbi_c_20, C => N_169, Y => - config_active_interruption_onError_0_sqmuxa); - - \reg_sp.addr_matrix_f2[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[15]\); - - \prdata_RNO[23]\ : OR3C - port map(A => \prdata_39_0_iv_1[23]\, B => - \prdata_39_0_iv_0[23]\, C => \prdata_39_0_iv_5[23]\, Y - => \prdata_39[23]\); - - \reg_wp.burst_f0_1_sqmuxa_0_a2\ : NOR3 - port map(A => N_157, B => un1_apbi_2, C => N_163, Y => - burst_f0_1_sqmuxa); - - \reg_wp.addr_data_f0[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[7]\); - - \reg_sp.addr_matrix_f0_0[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[10]\); - - \prdata_RNO_6[0]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[0]\, B => - \addr_matrix_f0_0_m_i[0]\, C => \prdata_39_0_iv_1[0]\, Y - => \prdata_39_0_iv_7[0]\); - - \reg_wp.addr_data_f1[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[27]\); - - \reg_wp.nb_burst_available[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[9]\); - - \reg_wp.addr_data_f1[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[8]\); - - \prdata_RNO_4[28]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[28]\, Y - => \addr_data_f1_m_i[28]\); - - \reg_sp.addr_matrix_f0_0[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[13]\); - - \apbo.pirq_RNO[15]\ : OR3C - port map(A => \pirq_2_i_a2_7[15]\, B => \pirq_2_i_a2_6[15]\, - C => \pirq_2_i_a2_8[15]\, Y => N_155_i_0); - - \reg_sp.addr_matrix_f2[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[12]\); - - \prdata_RNO_1[10]\ : OR2B - port map(A => \nb_burst_available[10]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[10]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_a2_0\ : - OR3A - port map(A => N_928, B => apbi_c_21, C => apbi_c_22, Y => - N_169); - - \reg_wp.addr_data_f1[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[5]\); - - \prdata_RNO_3[21]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[21]\, Y - => \addr_matrix_f2_m_i[21]\); - - \prdata_RNO_15[3]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[3]\, - Y => \addr_matrix_f0_0_m_i[3]\); - - \prdata_RNO_3[26]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[26]\, Y - => \addr_data_f2_m_i[26]\); - - \prdata_RNO_8[19]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[19]\, Y - => \addr_matrix_f2_m_i[19]\); - - \prdata_RNO_3[1]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[1]\, C - => \addr_data_f2_m_i[1]\, Y => \prdata_39_0_iv_4[1]\); - - \prdata_RNO_20[0]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[0]\, Y - => \addr_matrix_f2_m_i[0]\); - - \prdata[27]\ : DFN1C0 - port map(D => \prdata_39[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(27)); - - \prdata_RNO[12]\ : OR3C - port map(A => \prdata_39_0_iv_2[12]\, B => - \delta_snapshot_m_i[12]\, C => \prdata_39_0_iv_6[12]\, Y - => \prdata_39[12]\); - - \reg_sp.addr_matrix_f2[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[17]\); - - \reg_wp.addr_data_f2[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[4]\); - - \prdata_RNO_2[3]\ : NOR3C - port map(A => \nb_snapshot_param_m_i[3]\, B => - \prdata_39_0_iv_6[3]\, C => \prdata_39_0_iv_11[3]\, Y => - \prdata_39_0_iv_13[3]\); - - \prdata_RNO_15[4]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[4]\, Y - => \addr_data_f3_m_i[4]\); - - \prdata[28]\ : DFN1C0 - port map(D => \prdata_39[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(28)); - - \prdata_RNO_0[28]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[28]\, C - => \addr_data_f2_m_i[28]\, Y => \prdata_39_0_iv_3[28]\); - - \reg_wp.addr_data_f3[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[13]\); - - \prdata_RNO_2[23]\ : NOR3C - port map(A => \addr_data_f3_m_i[23]\, B => - \addr_data_f2_m_i[23]\, C => \prdata_39_0_iv_2[23]\, Y - => \prdata_39_0_iv_5[23]\); - - \reg_sp.addr_matrix_f2[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[25]\); - - \reg_wp.addr_data_f3[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[10]\); - - \prdata_RNO_9[8]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[8]\, C - => \addr_data_f2_m_i[8]\, Y => \prdata_39_0_iv_3[8]\); - - \prdata_RNO_13[0]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[0]\, - Y => \addr_matrix_f0_0_m_i[0]\); - - \reg_wp.data_shaping_R0\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => data_shaping_R0); - - \reg_wp.addr_data_f2[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[6]\); - - \prdata_RNO_14[7]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[7]\, - Y => \addr_matrix_f0_0_m_i[7]\); - - \prdata_RNO[24]\ : OR3C - port map(A => \prdata_39_0_iv_3[24]\, B => - \prdata_39_0_iv_2[24]\, C => \prdata_39_0_iv_4[24]\, Y - => \prdata_39[24]\); - - \prdata_RNO_7[0]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[0]\, C - => \addr_data_f2_m_i[0]\, Y => \prdata_39_0_iv_4[0]\); - - \prdata_RNO[10]\ : OR3C - port map(A => \prdata_39_0_iv_7[10]\, B => - \nb_burst_available_m_i[10]\, C => \prdata_39_0_iv_8[10]\, - Y => \prdata_39[10]\); - - \reg_sp.addr_matrix_f0_1[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[17]\); - - \reg_wp.data_shaping_SP1\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_SP1\); - - \reg_sp.addr_matrix_f2[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[22]\); - - \prdata_RNO_3[22]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[22]\, Y - => \addr_data_f2_m_i[22]\); - - \reg_wp.status_full_err_RNO[1]\ : OA1B - port map(A => apbi_c_55, B => \status_full_5_i_o2[0]\, C - => N_141, Y => \status_full_err_RNO[1]\); - - \reg_wp.delta_snapshot[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[1]\); - - \reg_sp.addr_matrix_f0_1[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[21]\); - - prdata_2_sqmuxa_0_a2_0 : NOR3B - port map(A => N_159, B => N_928, C => apbi_c_19, Y => - prdata_2_sqmuxa_0); - - \prdata_RNO_0[11]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[11]\, - C => \prdata_39_0_iv_1[11]\, Y => \prdata_39_0_iv_5[11]\); - - \prdata_RNO_7[27]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[27]\, C - => \addr_matrix_f2_m_i[27]\, Y => \prdata_39_0_iv_1[27]\); - - \prdata_RNO_0[16]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[16]\, - C => \addr_data_f2_m_i[16]\, Y => \prdata_39_0_iv_3[16]\); - - \reg_wp.addr_data_f3[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[11]\); - - \reg_sp.addr_matrix_f2[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[27]\); - - \reg_sp.addr_matrix_f1[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[29]\); - - \reg_wp.delta_f2_f0[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[1]\); - - \reg_wp.burst_f0_1_sqmuxa_0_a2_0\ : OR3B - port map(A => apbi_c_22, B => N_928, C => apbi_c_21, Y => - N_163); - - \reg_wp.addr_data_f1[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[17]\); - - \reg_wp.status_new_err_RNO[3]\ : OA1B - port map(A => apbi_c_61, B => \status_full_5_i_o2[0]\, C - => N_153, Y => \status_new_err_RNO[3]\); - - \prdata_RNO_6[6]\ : AOI1B - port map(A => \status_full_err[2]\, B => prdata_13_sqmuxa, - C => \addr_data_f0_m_i[6]\, Y => \prdata_39_0_iv_2[6]\); - - \reg_sp.addr_matrix_f2[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[4]\); - - \reg_wp.delta_f2_f1[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[2]\); - - \prdata_RNO_5[10]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[10]\, - C => \addr_data_f2_m_i[10]\, Y => \prdata_39_0_iv_3[10]\); - - \prdata_RNO_2[10]\ : NOR3C - port map(A => \prdata_39_0_iv_2[10]\, B => - \nb_snapshot_param_m_i[10]\, C => \prdata_39_0_iv_5[10]\, - Y => \prdata_39_0_iv_8[10]\); - - \prdata_RNO_16[5]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[5]\, - Y => \addr_data_f2_m_i[5]\); - - \prdata_RNO_3[15]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[15]\, Y => \addr_matrix_f0_1_m_i[15]\); - - \apbo.pirq_RNO_3[15]\ : NOR2 - port map(A => status_full_err_0(2), B => - status_full_err_0(3), Y => \pirq_2_i_a2_3[15]\); - - \prdata_RNO_2[4]\ : NOR3C - port map(A => \nb_burst_available_m_i[4]\, B => - \prdata_39_0_iv_9[4]\, C => data_shaping_R1_m_i, Y => - \prdata_39_0_iv_14[4]\); - - \prdata_RNO_16[3]\ : OR2B - port map(A => \status_full_0[3]\, B => prdata_13_sqmuxa, Y - => \status_full_m_i[3]\); - - \prdata_RNO_12[9]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[9]\, - Y => \addr_matrix_f2_m_i[9]\); - - \reg_sp.addr_matrix_f0_1[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[0]\); - - \reg_wp.addr_data_f2[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[0]\); - - \reg_wp.addr_data_f2[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[12]\); - - \reg_sp.addr_matrix_f1[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[23]\); - - \prdata_RNO_4[27]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[27]\, Y - => \addr_data_f1_m_i[27]\); - - \prdata_RNO_0[1]\ : NOR3C - port map(A => \prdata_39_0_iv_4[1]\, B => - \prdata_39_0_iv_3[1]\, C => data_shaping_SP0_m_i, Y => - \prdata_39_0_iv_13[1]\); - - \prdata[10]\ : DFN1C0 - port map(D => \prdata_39[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(10)); - - \reg_sp.status_ready_matrix_f1\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f1); - - \prdata_RNO_0[12]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[12]\, C - => \addr_data_f1_m_i[12]\, Y => \prdata_39_0_iv_2[12]\); - - \prdata_RNO_2[7]\ : NOR3C - port map(A => \prdata_39_0_iv_3[7]\, B => - \prdata_39_0_iv_2[7]\, C => \nb_burst_available_m_i[7]\, - Y => \prdata_39_0_iv_10[7]\); - - \reg_wp.addr_data_f0[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[4]\); - - prdata_2_sqmuxa_0_a2 : NOR3B - port map(A => N_159, B => N_928, C => apbi_c_19, Y => - prdata_2_sqmuxa); - - \prdata_RNO[1]\ : OR3C - port map(A => \prdata_39_0_iv_13[1]\, B => - \prdata_39_0_iv_12[1]\, C => \prdata_39_0_iv_14[1]\, Y - => \prdata_39[1]\); - - \prdata_RNO_1[5]\ : AOI1B - port map(A => \nb_snapshot_param[5]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_6[5]\, Y => \prdata_39_0_iv_10[5]\); - - \reg_sp.addr_matrix_f0_1[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[28]\); - - \reg_sp.addr_matrix_f0_0[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[14]\); - - \prdata_RNO_1[2]\ : AOI1B - port map(A => \nb_burst_available[2]\, B => - prdata_17_sqmuxa, C => \prdata_39_0_iv_7[2]\, Y => - \prdata_39_0_iv_11[2]\); - - \reg_sp.addr_matrix_f0_0[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[15]\); - - \reg_sp.addr_matrix_f0_0[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[1]\); - - \prdata_RNO_1[24]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[24]\, C - => \addr_data_f1_m_i[24]\, Y => \prdata_39_0_iv_2[24]\); - - \reg_sp.addr_matrix_f0_1[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[30]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_930, B => N_172, C => apbi_c_20, Y => - addr_matrix_f1_1_sqmuxa); - - \prdata_RNO_0[27]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[27]\, C - => \addr_data_f2_m_i[27]\, Y => \prdata_39_0_iv_3[27]\); - - \prdata[13]\ : DFN1C0 - port map(D => \prdata_39[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(13)); - - \reg_wp.delta_f2_f0[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[3]\); - - \reg_wp.enable_f0\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \enable_f0\); - - \reg_sp.addr_matrix_f1[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[15]\); - - \prdata_RNO_8[15]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[15]\, Y - => \addr_data_f0_m_i[15]\); - - \prdata_RNO_3[18]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[18]\, Y - => \addr_matrix_f2_m_i[18]\); - - \prdata_RNO[15]\ : OR3C - port map(A => \prdata_39_0_iv_4[15]\, B => - \prdata_39_0_iv_3[15]\, C => \prdata_39_0_iv_5[15]\, Y - => \prdata_39[15]\); - - \prdata_RNO_4[10]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[10]\, Y - => \addr_data_f3_m_i[10]\); - - \reg_wp.addr_data_f3[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[0]\); - - \prdata_RNO_7[11]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[11]\, Y - => \addr_data_f0_m_i[11]\); - - \reg_wp.addr_data_f0[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[5]\); - - \prdata_RNO_7[16]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[16]\, - C => \addr_matrix_f2_m_i[16]\, Y => - \prdata_39_0_iv_1[16]\); - - \reg_sp.addr_matrix_f1[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[12]\); - - \prdata[3]\ : DFN1C0 - port map(D => \prdata_39[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(3)); - - \reg_wp.addr_data_f2[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[27]\); - - \reg_wp.burst_f0\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \burst_f0\); - - \prdata_RNO_10[4]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[4]\, Y - => \addr_data_f1_m_i[4]\); - - \reg_wp.addr_data_f3[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[15]\); - - \prdata[5]\ : DFN1C0 - port map(D => \prdata_39[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(5)); - - \reg_sp.addr_matrix_f1[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[17]\); - - \reg_wp.addr_data_f3[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[16]\); - - \prdata_RNO_6[21]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[21]\, Y - => \addr_data_f2_m_i[21]\); - - \prdata_RNO_11[8]\ : OR2B - port map(A => \nb_burst_available[8]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[8]\); - - \prdata_RNO_6[26]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[26]\, - Y => \addr_matrix_f0_0_m_i[26]\); - - \reg_wp.addr_data_f0[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[24]\); - - \prdata_RNO_15[7]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[7]\, Y - => \delta_f2_f1_m_i[7]\); - - \reg_sp.addr_matrix_f2[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[9]\); - - \prdata_RNO_7[5]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[5]\, C - => \delta_f2_f1_m_i[5]\, Y => \prdata_39_0_iv_5[5]\); - - GND_i : GND - port map(Y => \GND\); - - \prdata_RNO_2[1]\ : NOR3C - port map(A => \prdata_39_0_iv_7[1]\, B => - \prdata_39_0_iv_6[1]\, C => \prdata_39_0_iv_10[1]\, Y => - \prdata_39_0_iv_14[1]\); - - \reg_wp.status_new_err[0]\ : DFN1C0 - port map(D => \status_new_err_RNO[0]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_new_err[0]\); - - \reg_wp.status_new_err_RNO[0]\ : OA1B - port map(A => apbi_c_58, B => \status_full_5_i_o2[0]\, C - => N_147, Y => \status_new_err_RNO[0]\); - - \prdata_RNO_7[12]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[12]\, - Y => \addr_matrix_f2_m_i[12]\); - - \prdata_RNO_9[2]\ : OR3B - port map(A => N_161_0, B => \data_shaping_SP1\, C => N_163, - Y => data_shaping_SP1_m_i); - - \reg_wp.status_full[1]\ : DFN1C0 - port map(D => \status_full_RNO[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \status_full_0[1]\); - - \reg_wp.addr_data_f0[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[0]\); - - \prdata_RNO_8[18]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[18]\, Y - => \addr_data_f1_m_i[18]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_o2\ : - NOR3A - port map(A => apbi_c_0, B => apbi_c_24, C => apbi_c_23, Y - => N_928); - - \reg_sp.addr_matrix_f1[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[28]\); - - \prdata_RNO_7[8]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[8]\, Y - => \addr_data_f3_m_i[8]\); - - \reg_wp.addr_data_f0[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[28]\); - - \prdata_RNO_14[1]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[1]\, Y - => \addr_matrix_f1_m_i[1]\); - - \reg_wp.delta_snapshot[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[5]\); - - \prdata_RNO_2[20]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[20]\, B => - \addr_matrix_f0_0_m_i[20]\, C => \prdata_39_0_iv_1[20]\, - Y => \prdata_39_0_iv_4[20]\); - - \prdata_RNO_6[22]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[22]\, - Y => \addr_matrix_f0_0_m_i[22]\); - - \prdata_RNO_10[11]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[11]\, - Y => \addr_matrix_f2_m_i[11]\); - - \reg_wp.nb_snapshot_param[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[0]\); - - \prdata_RNO_3[9]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[9]\, Y - => \delta_snapshot_m_i[9]\); - - \reg_wp.addr_data_f0[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[14]\); - - \prdata_RNO_1[31]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[31]\, C - => \addr_data_f1_m_i[31]\, Y => \prdata_39_0_iv_2[31]\); - - \prdata_RNO_6[8]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[8]\, Y - => \delta_f2_f0_m_i[8]\); - - \prdata_RNO_5[30]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[30]\, - Y => \addr_matrix_f0_1_m_i[30]\); - - \prdata_RNO_4[7]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[7]\, - C => \addr_matrix_f2_m_i[7]\, Y => \prdata_39_0_iv_1[7]\); - - \reg_sp.addr_matrix_f0_1[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[16]\); - - \prdata_RNO_5[29]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[29]\, - Y => \addr_matrix_f0_1_m_i[29]\); - - \prdata_RNO_5[4]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[4]\, C - => \prdata_39_0_iv_2[4]\, Y => \prdata_39_0_iv_7[4]\); - - \prdata_RNO_1[9]\ : NOR3C - port map(A => \delta_f2_f0_m_i[9]\, B => - \addr_data_f3_m_i[9]\, C => \nb_snapshot_param_m_i[9]\, Y - => \prdata_39_0_iv_8[9]\); - - \reg_wp.addr_data_f2[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[1]\); - - \reg_wp.delta_f2_f0[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[5]\); - - \prdata_RNO_3[17]\ : OR3C - port map(A => N_161, B => N_168_0, C => \addr_data_f2[17]\, - Y => \addr_data_f2_m_i[17]\); - - \prdata_RNO_1[23]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[23]\, C => \addr_matrix_f0_1_m_i[23]\, - Y => \prdata_39_0_iv_0[23]\); - - \prdata_RNO[2]\ : OR3C - port map(A => \prdata_39_0_iv_12[2]\, B => - \prdata_39_0_iv_11[2]\, C => \prdata_39_0_iv_13[2]\, Y - => \prdata_39[2]\); - - \reg_wp.delta_snapshot[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[6]\); - - \prdata[15]\ : DFN1C0 - port map(D => \prdata_39[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(15)); - - \reg_wp.delta_snapshot[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[8]\); - - \reg_wp.nb_burst_available[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[6]\); - - \reg_wp.status_full_err_RNO[2]\ : OA1B - port map(A => apbi_c_56, B => \status_full_5_i_o2[0]\, C - => N_143, Y => \status_full_err_RNO[2]\); - - \reg_wp.addr_data_f1[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[23]\); - - \reg_wp.addr_data_f0[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[18]\); - - \reg_wp.addr_data_f1[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[20]\); - - \prdata[6]\ : DFN1C0 - port map(D => \prdata_39[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(6)); - - \prdata_RNO_4[3]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[3]\, C - => status_ready_matrix_f2_m_i, Y => - \prdata_39_0_iv_2[3]\); - - \prdata_RNO_10[9]\ : AOI1B - port map(A => \status_new_err[1]\, B => prdata_13_sqmuxa, C - => \addr_data_f0_m_i[9]\, Y => \prdata_39_0_iv_2[9]\); - - \reg_wp.status_new_err_RNO[2]\ : OA1B - port map(A => apbi_c_60, B => \status_full_5_i_o2[0]\, C - => N_151, Y => \status_new_err_RNO[2]\); - - \prdata_RNO_11[6]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[6]\, - Y => \addr_matrix_f0_1_m_i[6]\); - - \reg_sp.addr_matrix_f0_0[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[22]\); - - \reg_wp.status_new_err[2]\ : DFN1C0 - port map(D => \status_new_err_RNO[2]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_new_err[2]\); - - \prdata_RNO_17[4]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[4]\, C - => \delta_f2_f1_m_i[4]\, Y => \prdata_39_0_iv_5[4]\); - - \reg_wp.addr_data_f0[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[3]\); - - \reg_wp.addr_data_f3[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[12]\); - - \prdata_RNO_0[6]\ : AOI1B - port map(A => \nb_burst_available[6]\, B => - prdata_17_sqmuxa, C => \prdata_39_0_iv_6[6]\, Y => - \prdata_39_0_iv_10[6]\); - - prdata_4_sqmuxa_0_a2_0 : NOR2B - port map(A => N_172, B => N_161_0, Y => prdata_4_sqmuxa_0); - - \reg_wp.delta_f2_f1[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[3]\); - - \prdata_RNO_8[24]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[24]\, Y - => \addr_matrix_f2_m_i[24]\); - - \reg_wp.addr_data_f1[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[21]\); - - \prdata_RNO_2[0]\ : NOR3C - port map(A => \prdata_39_0_iv_4[0]\, B => - \prdata_39_0_iv_3[0]\, C => \prdata_39_0_iv_11[0]\, Y => - \prdata_39_0_iv_14[0]\); - - \reg_wp.delta_f2_f0[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[8]\); - - \reg_wp.addr_data_f2[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[9]\); - - \prdata_RNO[27]\ : OR3C - port map(A => \prdata_39_0_iv_3[27]\, B => - \prdata_39_0_iv_2[27]\, C => \prdata_39_0_iv_4[27]\, Y - => \prdata_39[27]\); - - \prdata_RNO_8[30]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[30]\, Y - => \addr_matrix_f2_m_i[30]\); - - \prdata_RNO_3[29]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[29]\, Y - => \addr_data_f2_m_i[29]\); - - prdata_4_sqmuxa_0_a2 : NOR2B - port map(A => N_172, B => N_161, Y => prdata_4_sqmuxa); - - \prdata_RNO_8[17]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[17]\, Y - => \addr_matrix_f2_m_i[17]\); - - \reg_wp.status_full_RNO_0[3]\ : NOR3A - port map(A => N_933_0, B => \status_full_0[3]\, C => - status_full(3), Y => N_138); - - \prdata_RNO_18[2]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[2]\, - C => \addr_matrix_f2_m_i[2]\, Y => \prdata_39_0_iv_1[2]\); - - \apbo.pirq_RNO_1[15]\ : NOR3A - port map(A => \pirq_2_i_a2_1[15]\, B => status_new_err_0_1, - C => status_new_err_0_0, Y => \pirq_2_i_a2_6[15]\); - - \reg_wp.status_full_err_RNO_0[0]\ : NOR3A - port map(A => N_933_0, B => \status_full_err[0]\, C => - status_full_err_0(0), Y => N_139); - - \prdata_RNO_6[14]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[14]\, - C => \addr_data_f2_m_i[14]\, Y => \prdata_39_0_iv_3[14]\); - - \prdata_RNO_1[11]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[11]\, B => - \addr_matrix_f0_0_m_i[11]\, C => \addr_data_f3_m_i[11]\, - Y => \prdata_39_0_iv_4[11]\); - - \prdata_RNO_1[16]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[16]\, C - => \addr_data_f1_m_i[16]\, Y => \prdata_39_0_iv_2[16]\); - - \apbo.pirq[15]\ : DFN1C0 - port map(D => N_155_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => pirq_c(15)); - - \reg_wp.addr_data_f1[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[4]\); - - \prdata_RNO[19]\ : OR3C - port map(A => \prdata_39_0_iv_3[19]\, B => - \prdata_39_0_iv_2[19]\, C => \prdata_39_0_iv_4[19]\, Y - => \prdata_39[19]\); - - \reg_wp.data_shaping_BW\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_BW_c\); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_158, B => apbi_c_21, C => apbi_c_22, Y => - N_164); - - \prdata_RNO_17[1]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[1]\, - Y => \addr_matrix_f0_0_m_i[1]\); - - \reg_sp.addr_matrix_f2[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[0]\); - - \prdata_RNO_9[1]\ : AOI1B - port map(A => \nb_snapshot_param[1]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_5[1]\, Y => \prdata_39_0_iv_10[1]\); - - \prdata_RNO_1[0]\ : AOI1B - port map(A => \nb_snapshot_param[0]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_7[0]\, Y => \prdata_39_0_iv_12[0]\); - - \prdata_RNO_10[1]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[1]\, - Y => \addr_data_f2_m_i[1]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_a2_0\ : NOR3C - port map(A => N_159, B => N_928, C => N_930, Y => - addr_matrix_f0_0_1_sqmuxa_0); - - \reg_wp.addr_data_f1[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[13]\); - - \reg_wp.delta_snapshot[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[4]\); - - \reg_wp.addr_data_f1[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[10]\); - - \reg_wp.status_full_RNO_0[0]\ : NOR3A - port map(A => N_933_0, B => \status_full_0[0]\, C => - status_full(0), Y => N_135); - - \reg_sp.addr_matrix_f1[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[9]\); - - \reg_wp.delta_f2_f1[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[8]\); - - \reg_sp.addr_matrix_f0_1[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[10]\); - - \prdata_RNO_19[3]\ : OR2B - port map(A => \nb_burst_available[3]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[3]\); - - \prdata_RNO_2[5]\ : NOR3C - port map(A => \prdata_39_0_iv_5[5]\, B => - \prdata_39_0_iv_4[5]\, C => \nb_burst_available_m_i[5]\, - Y => \prdata_39_0_iv_12[5]\); - - \prdata_RNO_2[6]\ : NOR3C - port map(A => \prdata_39_0_iv_3[6]\, B => - \prdata_39_0_iv_2[6]\, C => \prdata_39_0_iv_8[6]\, Y => - \prdata_39_0_iv_11[6]\); - - prdata_8_sqmuxa_0_a2 : NOR2 - port map(A => N_163, B => N_157, Y => prdata_8_sqmuxa); - - \prdata_RNO_0[19]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[19]\, - C => \addr_data_f2_m_i[19]\, Y => \prdata_39_0_iv_3[19]\); - - \prdata[12]\ : DFN1C0 - port map(D => \prdata_39[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(12)); - - \reg_sp.addr_matrix_f0_1[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[13]\); - - \prdata_RNO_1[12]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[12]\, - Y => \delta_snapshot_m_i[12]\); - - \reg_sp.addr_matrix_f0_0[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[9]\); - - \reg_wp.addr_data_f1[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[11]\); - - prdata_0_sqmuxa_0_a2 : NOR2A - port map(A => N_161, B => N_169, Y => prdata_0_sqmuxa); - - \prdata_RNO_5[25]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[25]\, - Y => \addr_matrix_f0_1_m_i[25]\); - - \prdata[19]\ : DFN1C0 - port map(D => \prdata_39[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(19)); - - \prdata_RNO_11[4]\ : AOI1B - port map(A => \status_full_err[0]\, B => prdata_13_sqmuxa, - C => status_error_anticipating_empty_fifo_m_i, Y => - \prdata_39_0_iv_2[4]\); - - \reg_wp.delta_f2_f0[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[7]\); - - \prdata_RNO_11[11]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[11]\, Y => \addr_data_f2_m_i[11]\); - - \reg_sp.addr_matrix_f0_1[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[29]\); - - \reg_wp.status_full_RNO[1]\ : OA1B - port map(A => apbi_c_51, B => \status_full_5_i_o2[0]\, C - => N_136, Y => \status_full_RNO[1]\); - - \reg_wp.nb_burst_available[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[5]\); - - \prdata_RNO_7[30]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[30]\, C - => \addr_matrix_f2_m_i[30]\, Y => \prdata_39_0_iv_1[30]\); - - \reg_wp.addr_data_f3[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[8]\); - - \prdata_RNO_5[11]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[11]\, - Y => \addr_matrix_f0_0_m_i[11]\); - - \reg_wp.addr_data_f0[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[29]\); - - \prdata_RNO_5[16]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[16]\, Y => \addr_matrix_f0_1_m_i[16]\); - - \prdata_RNO_2[11]\ : NOR3C - port map(A => \addr_data_f0_m_i[11]\, B => - \status_new_err_m_i[3]\, C => \prdata_39_0_iv_3[11]\, Y - => \prdata_39_0_iv_6[11]\); - - \prdata_RNO_2[16]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[16]\, B => - \addr_matrix_f0_0_m_i[16]\, C => \prdata_39_0_iv_1[16]\, - Y => \prdata_39_0_iv_4[16]\); - - \prdata_RNO_13[10]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[10]\, - Y => \addr_matrix_f2_m_i[10]\); - - \reg_wp.nb_burst_available[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[8]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_930, B => N_168, C => apbi_c_20, Y => - addr_data_f2_1_sqmuxa); - - prdata_13_sqmuxa_0_a2 : NOR3A - port map(A => apbi_c_21, B => N_931, C => apbi_c_19, Y => - prdata_13_sqmuxa); - - \reg_wp.delta_f2_f0[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[0]\); - - \reg_sp.status_error_bad_component_error\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_error_bad_component_error); - - \prdata_RNO_12[10]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[10]\, - C => \addr_matrix_f2_m_i[10]\, Y => - \prdata_39_0_iv_1[10]\); - - \reg_wp.addr_data_f3[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[24]\); - - \reg_wp.nb_burst_available[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[4]\); - - prdata_10_sqmuxa_0_a2_0 : NOR3A - port map(A => apbi_c_19, B => apbi_c_21, C => N_931, Y => - prdata_10_sqmuxa_0); - - \reg_wp.addr_data_f1[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[25]\); - - \lpp_top_apbreg.reg_wp.status_full_5_i_o2_0[0]\ : OR3B - port map(A => apbi_c_21, B => N_930, C => N_931, Y => - N_933_0); - - \reg_wp.addr_data_f1[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[26]\); - - \prdata_RNO_0[30]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[30]\, C - => \addr_data_f2_m_i[30]\, Y => \prdata_39_0_iv_3[30]\); - - \reg_wp.addr_data_f1[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[1]\); - - \prdata_RNO_8[23]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[23]\, Y - => \addr_data_f1_m_i[23]\); - - \reg_sp.addr_matrix_f2[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[3]\); - - \reg_sp.addr_matrix_f2[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[19]\); - - \status_full_ack[0]\ : DFN1C0 - port map(D => \status_full_ack_8[0]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => status_full_ack(0)); - - \prdata[21]\ : DFN1C0 - port map(D => \prdata_39[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(21)); - - \prdata_RNO_3[8]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[8]\, - C => \addr_matrix_f0_1_m_i[8]\, Y => - \prdata_39_0_iv_0[8]\); - - \prdata_RNO_5[12]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[12]\, C => \addr_matrix_f0_1_m_i[12]\, - Y => \prdata_39_0_iv_0[12]\); - - \reg_wp.addr_data_f3[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[28]\); - - \reg_wp.addr_data_f2[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[23]\); - - \prdata_RNO_5[28]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[28]\, - Y => \addr_matrix_f0_1_m_i[28]\); - - \prdata_RNO_2[12]\ : NOR3C - port map(A => \prdata_39_0_iv_1[12]\, B => - \prdata_39_0_iv_0[12]\, C => \prdata_39_0_iv_3[12]\, Y - => \prdata_39_0_iv_6[12]\); - - \reg_wp.addr_data_f2[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[20]\); - - \prdata_RNO_1[20]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[20]\, C - => \addr_data_f1_m_i[20]\, Y => \prdata_39_0_iv_2[20]\); - - \prdata_RNO_10[0]\ : OR3A - port map(A => status_ready_matrix_f0_0, B => N_157, C => - N_169, Y => status_ready_matrix_f0_0_m_i); - - \reg_wp.data_shaping_SP0\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_SP0\); - - \prdata_RNO_6[13]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[13]\, - C => \addr_data_f2_m_i[13]\, Y => \prdata_39_0_iv_3[13]\); - - \prdata_RNO_3[25]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[25]\, Y - => \addr_data_f2_m_i[25]\); - - \reg_wp.addr_data_f0[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[19]\); - - \prdata_RNO_11[9]\ : OR2B - port map(A => \nb_burst_available[9]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[9]\); - - \prdata_RNO_17[9]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[9]\, Y - => \addr_data_f0_m_i[9]\); - - \reg_wp.data_shaping_R1_0\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_R1_0\); - - \prdata_RNO_8[5]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[5]\, C - => \addr_data_f2_m_i[5]\, Y => \prdata_39_0_iv_4[5]\); - - \prdata_RNO_6[3]\ : OR2B - port map(A => \nb_snapshot_param[3]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[3]\); - - \reg_sp.addr_matrix_f2[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[13]\); - - \prdata_RNO_17[6]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[6]\, Y - => \addr_data_f3_m_i[6]\); - - \prdata_RNO_7[19]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[19]\, C - => \addr_matrix_f2_m_i[19]\, Y => \prdata_39_0_iv_1[19]\); - - \prdata_RNO_9[14]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[14]\, Y - => \addr_data_f2_m_i[14]\); - - \prdata_RNO_7[24]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[24]\, C - => \addr_matrix_f2_m_i[24]\, Y => \prdata_39_0_iv_1[24]\); - - \prdata_RNO[21]\ : OR3C - port map(A => \prdata_39_0_iv_1[21]\, B => - \prdata_39_0_iv_0[21]\, C => \prdata_39_0_iv_5[21]\, Y - => \prdata_39[21]\); - - \prdata[1]\ : DFN1C0 - port map(D => \prdata_39[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(1)); - - \reg_wp.delta_snapshot[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[10]\); - - \reg_sp.addr_matrix_f2[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[29]\); - - \reg_wp.addr_data_f2[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[21]\); - - \reg_wp.addr_data_f3[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[7]\); - - \prdata_RNO_4[11]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[11]\, Y => \addr_matrix_f0_1_m_i[11]\); - - \prdata_RNO_4[16]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[16]\, - Y => \addr_data_f1_m_i[16]\); - - \prdata_RNO_1[7]\ : NOR3C - port map(A => \delta_f2_f0_m_i[7]\, B => - \addr_data_f3_m_i[7]\, C => \nb_snapshot_param_m_i[7]\, Y - => \prdata_39_0_iv_8[7]\); - - \prdata_RNO_7[9]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[9]\, Y - => \addr_data_f3_m_i[9]\); - - \prdata_RNO_6[29]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[29]\, - Y => \addr_matrix_f0_0_m_i[29]\); - - \prdata_RNO_19[2]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[2]\, Y - => \delta_f2_f0_m_i[2]\); - - \reg_wp.addr_data_f1[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[15]\); - - \prdata_RNO_16[2]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[2]\, - Y => \addr_matrix_f0_1_m_i[2]\); - - \reg_wp.status_full_err_RNO[0]\ : OA1B - port map(A => apbi_c_54, B => \status_full_5_i_o2[0]\, C - => N_139, Y => \status_full_err_RNO[0]\); - - \reg_wp.addr_data_f1[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[16]\); - - \prdata_RNO_5[9]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[9]\, B => - \addr_matrix_f0_0_m_i[9]\, C => \delta_f2_f1_m_i[9]\, Y - => \prdata_39_0_iv_5[9]\); - - \reg_sp.addr_matrix_f1[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[26]\); - - \reg_sp.addr_matrix_f2[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[2]\); - - \reg_sp.addr_matrix_f0_1[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[14]\); - - \reg_sp.addr_matrix_f0_1[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[15]\); - - \prdata_RNO[26]\ : OR3C - port map(A => \prdata_39_0_iv_3[26]\, B => - \prdata_39_0_iv_2[26]\, C => \prdata_39_0_iv_4[26]\, Y - => \prdata_39[26]\); - - \prdata_RNO_0[15]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[15]\, B => - \addr_matrix_f0_0_m_i[15]\, C => \prdata_39_0_iv_1[15]\, - Y => \prdata_39_0_iv_4[15]\); - - \prdata[31]\ : DFN1C0 - port map(D => \prdata_39[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(31)); - - \reg_wp.addr_data_f1_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_166, B => apbi_c_21, C => N_931, Y => - addr_data_f1_1_sqmuxa); - - \reg_wp.addr_data_f2[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[30]\); - - \reg_sp.addr_matrix_f0_1[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[7]\); - - \prdata_RNO_4[24]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[24]\, Y - => \addr_data_f1_m_i[24]\); - - \reg_sp.addr_matrix_f1[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[21]\); - - \reg_sp.addr_matrix_f2[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[23]\); - - \reg_wp.addr_data_f3[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[3]\); - - \prdata_RNO_3[28]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[28]\, Y - => \addr_data_f2_m_i[28]\); - - \reg_sp.addr_matrix_f1[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[20]\); - - \prdata[16]\ : DFN1C0 - port map(D => \prdata_39[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(16)); - - \prdata_RNO_4[0]\ : AOI1B - port map(A => prdata_0_sqmuxa, B => - config_active_interruption_onNewMatrix, C => - status_ready_matrix_f0_0_m_i, Y => \prdata_39_0_iv_2[0]\); - - \status_full_ack[2]\ : DFN1C0 - port map(D => \status_full_ack_8[2]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => status_full_ack(2)); - - \prdata_RNO_4[12]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[12]\, - C => \addr_matrix_f2_m_i[12]\, Y => - \prdata_39_0_iv_1[12]\); - - \prdata_RNO[0]\ : OR3C - port map(A => \prdata_39_0_iv_13[0]\, B => - \prdata_39_0_iv_12[0]\, C => \prdata_39_0_iv_14[0]\, Y - => \prdata_39[0]\); - - \reg_wp.addr_data_f1[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[22]\); - - \prdata_RNO_12[5]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[5]\, - Y => \addr_matrix_f0_1_m_i[5]\); - - \reg_wp.addr_data_f2[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[31]\); - - \reg_wp.nb_snapshot_param[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[3]\); - - \reg_sp.addr_matrix_f0_0[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[12]\); - - \prdata_RNO_0[24]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[24]\, - C => \addr_data_f2_m_i[24]\, Y => \prdata_39_0_iv_3[24]\); - - \reg_sp.status_error_anticipating_empty_fifo\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_error_anticipating_empty_fifo); - - \reg_sp.addr_matrix_f0_0[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[8]\); - - \status_full_ack_RNO[0]\ : NOR3A - port map(A => \status_full_0[0]\, B => apbi_c_50, C => - \status_full_5_i_o2[0]\, Y => \status_full_ack_8[0]\); - - \prdata_RNO_2[21]\ : NOR3C - port map(A => \addr_data_f3_m_i[21]\, B => - \addr_data_f2_m_i[21]\, C => \prdata_39_0_iv_2[21]\, Y - => \prdata_39_0_iv_5[21]\); - - \reg_sp.addr_matrix_f0_0[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[21]\); - - \prdata_RNO_2[26]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[26]\, B => - \addr_matrix_f0_0_m_i[26]\, C => \prdata_39_0_iv_1[26]\, - Y => \prdata_39_0_iv_4[26]\); - - \prdata_RNO_5[27]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[27]\, - Y => \addr_matrix_f0_1_m_i[27]\); - - \reg_wp.addr_data_f0[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[2]\); - - \reg_sp.addr_matrix_f0_0[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[0]\); - - \prdata_RNO_5[1]\ : OR3B - port map(A => N_161_0, B => \data_shaping_SP0\, C => N_163, - Y => data_shaping_SP0_m_i); - - \prdata_RNO_15[8]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[8]\, Y - => \delta_snapshot_m_i[8]\); - - \prdata_RNO_15[6]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[6]\, Y - => \addr_data_f0_m_i[6]\); - - \reg_wp.status_full[3]\ : DFN1C0 - port map(D => \status_full_RNO[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \status_full_0[3]\); - - \prdata_RNO_16[1]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[1]\, - Y => \addr_matrix_f0_1_m_i[1]\); - - \prdata[2]\ : DFN1C0 - port map(D => \prdata_39[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(2)); - - \reg_wp.delta_snapshot[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[2]\); - - \prdata_RNO_5[31]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[31]\, - Y => \addr_matrix_f0_1_m_i[31]\); - - prdata_9_sqmuxa_0_a2 : NOR3 - port map(A => apbi_c_21, B => N_931, C => apbi_c_19, Y => - prdata_9_sqmuxa); - - \prdata_RNO_5[2]\ : NOR3C - port map(A => \status_full_m_i[2]\, B => - \delta_f2_f1_m_i[2]\, C => \prdata_39_0_iv_4[2]\, Y => - \prdata_39_0_iv_9[2]\); - - \prdata_RNO_0[18]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[18]\, - C => \addr_matrix_f2_m_i[18]\, Y => - \prdata_39_0_iv_1[18]\); - - \reg_wp.nb_snapshot_param[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[6]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0_1\ : NOR3B - port map(A => N_930, B => N_168, C => apbi_c_20, Y => - addr_data_f2_1_sqmuxa_0); - - \reg_sp.addr_matrix_f2[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[18]\); - - \lpp_top_apbreg.reg_wp.status_full_5_i_o2[0]\ : OR3B - port map(A => apbi_c_21, B => N_930, C => N_931, Y => - \status_full_5_i_o2[0]\); - - \reg_wp.status_new_err_RNO_0[0]\ : NOR3A - port map(A => N_933_0, B => \status_new_err[0]\, C => - status_new_err_0_0, Y => N_147); - - \reg_wp.delta_f2_f1[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[6]\); - - \reg_sp.addr_matrix_f0_1[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[27]\); - - \reg_wp.status_full_err[0]\ : DFN1C0 - port map(D => \status_full_err_RNO[0]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_full_err[0]\); - - \prdata_RNO_18[3]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[3]\, - C => \addr_matrix_f2_m_i[3]\, Y => \prdata_39_0_iv_1[3]\); - - \reg_sp.addr_matrix_f1[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[4]\); - - \reg_sp.addr_matrix_f1[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[19]\); - - \reg_wp.addr_data_f2[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[25]\); - - \prdata_RNO_9[9]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[9]\, C - => \addr_data_f2_m_i[9]\, Y => \prdata_39_0_iv_3[9]\); - - \prdata_RNO_9[13]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[13]\, Y => \addr_data_f2_m_i[13]\); - - \prdata_RNO_3[5]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[5]\, C - => \addr_data_f1_m_i[5]\, Y => \prdata_39_0_iv_3[5]\); - - \prdata_RNO_0[4]\ : NOR3C - port map(A => \prdata_39_0_iv_3[4]\, B => burst_f0_m_i, C - => \prdata_39_0_iv_7[4]\, Y => \prdata_39_0_iv_11[4]\); - - \prdata_RNO_7[23]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[23]\, C - => \addr_data_f1_m_i[23]\, Y => \prdata_39_0_iv_2[23]\); - - \reg_wp.addr_data_f2[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[26]\); - - \prdata_RNO_2[22]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[22]\, B => - \addr_matrix_f0_0_m_i[22]\, C => \prdata_39_0_iv_1[22]\, - Y => \prdata_39_0_iv_4[22]\); - - \reg_sp.addr_matrix_f0_1[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[8]\); - - \reg_wp.delta_snapshot[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[7]\); - - \reg_sp.addr_matrix_f0_0[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[3]\); - - \prdata_RNO_18[6]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f2\, Y => - burst_f2_m_i); - - \reg_wp.burst_f1\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \burst_f1\); - - \prdata_RNO_7[15]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[15]\, - Y => \addr_data_f1_m_i[15]\); - - \reg_wp.addr_data_f1[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[12]\); - - \reg_sp.addr_matrix_f1[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[7]\); - - \reg_wp.status_full_RNO[2]\ : OA1B - port map(A => apbi_c_52, B => \status_full_5_i_o2[0]\, C - => N_137, Y => \status_full_RNO[2]\); - - \reg_wp.nb_burst_available[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[1]\); - - \prdata_RNO_8[20]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[20]\, Y - => \addr_matrix_f2_m_i[20]\); - - \prdata_RNO_0[5]\ : NOR3C - port map(A => \prdata_39_0_iv_3[5]\, B => burst_f1_m_i, C - => \prdata_39_0_iv_7[5]\, Y => \prdata_39_0_iv_11[5]\); - - \reg_wp.addr_data_f2[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[14]\); - - \reg_sp.addr_matrix_f0_0[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[28]\); - - \reg_wp.addr_data_f3[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[30]\); - - \prdata_RNO_3[27]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[27]\, Y - => \addr_data_f2_m_i[27]\); - - \reg_wp.addr_data_f0[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[1]\); - - \reg_sp.addr_matrix_f1[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[13]\); - - \prdata_RNO_6[25]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[25]\, - Y => \addr_matrix_f0_0_m_i[25]\); - - \reg_wp.addr_data_f3[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[29]\); - - \reg_sp.addr_matrix_f2[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[28]\); - - \prdata_RNO_12[8]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[8]\, - Y => \addr_matrix_f0_1_m_i[8]\); - - \prdata_RNO_4[23]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[23]\, - Y => \addr_matrix_f0_1_m_i[23]\); - - \prdata_RNO_1[19]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[19]\, C - => \addr_data_f1_m_i[19]\, Y => \prdata_39_0_iv_2[19]\); - - \prdata_RNO_8[31]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[31]\, Y - => \addr_matrix_f2_m_i[31]\); - - \prdata_RNO_7[2]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[2]\, B => - \addr_matrix_f0_0_m_i[2]\, C => \prdata_39_0_iv_1[2]\, Y - => \prdata_39_0_iv_6[2]\); - - \prdata_RNO_6[10]\ : AOI1B - port map(A => \status_new_err[2]\, B => prdata_13_sqmuxa, C - => \addr_data_f0_m_i[10]\, Y => \prdata_39_0_iv_2[10]\); - - \reg_sp.addr_matrix_f1[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[24]\); - - \prdata_RNO_7[6]\ : NOR3C - port map(A => \delta_f2_f0_m_i[6]\, B => - \addr_data_f3_m_i[6]\, C => burst_f2_m_i, Y => - \prdata_39_0_iv_8[6]\); - - \reg_wp.data_shaping_BW_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_930, B => apbi_c_20, C => N_163, Y => - data_shaping_BW_1_sqmuxa); - - \reg_wp.addr_data_f3[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[31]\); - - \reg_wp.addr_data_f2[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[18]\); - - \prdata_RNO[5]\ : OR3C - port map(A => \prdata_39_0_iv_11[5]\, B => - \prdata_39_0_iv_10[5]\, C => \prdata_39_0_iv_12[5]\, Y - => \prdata_39[5]\); - - \prdata_RNO_3[14]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[14]\, Y - => \addr_data_f1_m_i[14]\); - - \reg_wp.status_full[2]\ : DFN1C0 - port map(D => \status_full_RNO[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \status_full_0[2]\); - - \prdata_RNO_0[23]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[23]\, C - => \addr_matrix_f2_m_i[23]\, Y => \prdata_39_0_iv_1[23]\); - - \reg_wp.status_full_RNO[0]\ : OA1B - port map(A => apbi_c_50, B => \status_full_5_i_o2[0]\, C - => N_135, Y => \status_full_RNO[0]\); - - \prdata_RNO_7[18]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[18]\, C - => \addr_data_f1_m_i[18]\, Y => \prdata_39_0_iv_2[18]\); - - \prdata_RNO_13[9]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[9]\, - Y => \addr_matrix_f0_1_m_i[9]\); - - \reg_wp.addr_data_f1[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[2]\); - - \reg_sp.addr_matrix_f2[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[6]\); - - \prdata_RNO_0[17]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[17]\, - C => \addr_data_f2_m_i[17]\, Y => \prdata_39_0_iv_3[17]\); - - prdata_0_sqmuxa_0_a2_0_0 : NOR2 - port map(A => apbi_c_20, B => apbi_c_19, Y => N_161_0); - - \reg_wp.addr_data_f1[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[3]\); - - \prdata_RNO_0[9]\ : NOR3C - port map(A => \delta_snapshot_m_i[9]\, B => - \prdata_39_0_iv_1[9]\, C => \prdata_39_0_iv_5[9]\, Y => - \prdata_39_0_iv_9[9]\); - - \reg_sp.addr_matrix_f0_0[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[30]\); - - \prdata_RNO_6[28]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[28]\, - Y => \addr_matrix_f0_0_m_i[28]\); - - \reg_wp.addr_data_f2[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[3]\); - - \prdata_RNO[31]\ : OR3C - port map(A => \prdata_39_0_iv_3[31]\, B => - \prdata_39_0_iv_2[31]\, C => \prdata_39_0_iv_4[31]\, Y - => \prdata_39[31]\); - - \reg_sp.addr_matrix_f0_0[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[6]\); - - \prdata_RNO_17[5]\ : OR3A - port map(A => status_error_bad_component_error, B => N_157, - C => N_169, Y => status_error_bad_component_error_m_i); - - \prdata_RNO_10[7]\ : AOI1B - port map(A => \status_full_err[3]\, B => prdata_13_sqmuxa, - C => \addr_data_f0_m_i[7]\, Y => \prdata_39_0_iv_2[7]\); - - \prdata_RNO_13[4]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[4]\, - Y => \addr_matrix_f0_0_m_i[4]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_0\ : NOR3B - port map(A => N_930, B => N_172, C => apbi_c_20, Y => - addr_matrix_f1_1_sqmuxa_0); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_159, B => N_928, C => N_166, Y => - addr_matrix_f0_1_1_sqmuxa); - - \prdata_RNO_5[19]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[19]\, - Y => \addr_matrix_f0_1_m_i[19]\); - - \prdata_RNO_2[19]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[19]\, B => - \addr_matrix_f0_0_m_i[19]\, C => \prdata_39_0_iv_1[19]\, - Y => \prdata_39_0_iv_4[19]\); - - \prdata_RNO_3[2]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[2]\, C - => \addr_data_f2_m_i[2]\, Y => \prdata_39_0_iv_3[2]\); - - \prdata_RNO_0[7]\ : NOR3C - port map(A => \delta_snapshot_m_i[7]\, B => - \prdata_39_0_iv_1[7]\, C => \prdata_39_0_iv_5[7]\, Y => - \prdata_39_0_iv_9[7]\); - - \reg_wp.addr_data_f2[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[22]\); - - \reg_wp.delta_f2_f0[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[9]\); - - \prdata[17]\ : DFN1C0 - port map(D => \prdata_39[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(17)); - - \reg_wp.addr_data_f0[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[30]\); - - \prdata_RNO_7[31]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[31]\, C - => \addr_matrix_f2_m_i[31]\, Y => \prdata_39_0_iv_1[31]\); - - \prdata_RNO_8[2]\ : OR2B - port map(A => \nb_snapshot_param[2]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[2]\); - - \reg_wp.status_full_err[2]\ : DFN1C0 - port map(D => \status_full_err_RNO[2]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_full_err[2]\); - - \prdata_RNO_11[2]\ : OR3A - port map(A => status_ready_matrix_f1, B => N_157, C => - N_169, Y => status_ready_matrix_f1_m_i); - - \prdata_RNO_8[14]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[14]\, Y => \addr_matrix_f0_1_m_i[14]\); - - \reg_sp.addr_matrix_f2[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[31]\); - - \prdata_RNO_15[2]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f2\, Y => - enable_f2_m_i); - - \prdata[18]\ : DFN1C0 - port map(D => \prdata_39[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(18)); - - \reg_sp.addr_matrix_f2[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[30]\); - - \reg_wp.addr_data_f2[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[7]\); - - \prdata_RNO[13]\ : OR3C - port map(A => \prdata_39_0_iv_2[13]\, B => - \delta_snapshot_m_i[13]\, C => \prdata_39_0_iv_6[13]\, Y - => \prdata_39[13]\); - - \reg_wp.data_shaping_R0_0\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_R0_0\); - - \reg_sp.addr_matrix_f1[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[2]\); - - \reg_sp.addr_matrix_f1[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[18]\); - - \prdata_RNO_9[3]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[3]\, - Y => \addr_data_f2_m_i[3]\); - - \prdata_RNO_21[0]\ : OR3B - port map(A => N_161, B => \data_shaping_BW_c\, C => N_163, - Y => data_shaping_BW_m_i); - - \prdata_RNO_15[9]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[9]\, Y - => \delta_f2_f1_m_i[9]\); - - \prdata_RNO_0[31]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[31]\, C - => \addr_data_f2_m_i[31]\, Y => \prdata_39_0_iv_3[31]\); - - \prdata_RNO_0[3]\ : OR3B - port map(A => N_161_0, B => \data_shaping_R0_0\, C => N_163, - Y => data_shaping_R0_m_i); - - \prdata_RNO[3]\ : OR3C - port map(A => data_shaping_R0_m_i, B => - \prdata_39_0_iv_12[3]\, C => \prdata_39_0_iv_13[3]\, Y - => \prdata_39[3]\); - - \reg_wp.enable_f2\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \enable_f2\); - - \reg_wp.addr_data_f0[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[6]\); - - \reg_wp.addr_data_f0[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[31]\); - - \prdata_RNO[6]\ : OR3C - port map(A => \prdata_39_0_iv_10[6]\, B => - \prdata_39_0_iv_9[6]\, C => \prdata_39_0_iv_11[6]\, Y => - \prdata_39[6]\); - - \reg_wp.status_new_err_RNO_0[1]\ : NOR3A - port map(A => N_933_0, B => \status_new_err[1]\, C => - status_new_err_0_1, Y => N_149); - - \reg_wp.addr_data_f3[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[9]\); - - \reg_wp.status_new_err[1]\ : DFN1C0 - port map(D => \status_new_err_RNO[1]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_new_err[1]\); - - \prdata_RNO_10[5]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[5]\, Y - => \addr_data_f1_m_i[5]\); - - \prdata_RNO_16[7]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[7]\, - Y => \addr_data_f2_m_i[7]\); - - \prdata_RNO_1[1]\ : AOI1B - port map(A => \nb_burst_available[1]\, B => - prdata_17_sqmuxa, C => \prdata_39_0_iv_8[1]\, Y => - \prdata_39_0_iv_12[1]\); - - \reg_wp.status_full_RNO_0[1]\ : NOR3A - port map(A => N_933_0, B => \status_full_0[1]\, C => - status_full(1), Y => N_136); - - \prdata_RNO_14[6]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[6]\, - Y => \addr_data_f2_m_i[6]\); - - \prdata_RNO_1[21]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[21]\, C => \addr_matrix_f0_1_m_i[21]\, - Y => \prdata_39_0_iv_0[21]\); - - \prdata_RNO_1[26]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[26]\, C - => \addr_data_f1_m_i[26]\, Y => \prdata_39_0_iv_2[26]\); - - \prdata_RNO_1[15]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[15]\, - C => \addr_data_f2_m_i[15]\, Y => \prdata_39_0_iv_3[15]\); - - \prdata_RNO_14[2]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[2]\, C - => \delta_f2_f0_m_i[2]\, Y => \prdata_39_0_iv_4[2]\); - - \prdata_RNO_7[17]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[17]\, - C => \addr_matrix_f2_m_i[17]\, Y => - \prdata_39_0_iv_1[17]\); - - \prdata_RNO_13[1]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[1]\, - Y => \addr_matrix_f2_m_i[1]\); - - \reg_sp.addr_matrix_f0_1[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[26]\); - - \prdata_RNO_9[10]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[10]\, Y => \addr_matrix_f0_1_m_i[10]\); - - \prdata_RNO_3[13]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[13]\, - Y => \addr_data_f1_m_i[13]\); - - \prdata_RNO_7[20]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[20]\, C - => \addr_matrix_f2_m_i[20]\, Y => \prdata_39_0_iv_1[20]\); - - \status_full_ack_RNO[1]\ : NOR3A - port map(A => \status_full_0[1]\, B => apbi_c_51, C => - N_933_0, Y => \status_full_ack_8[1]\); - - \reg_wp.addr_data_f1[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[9]\); - - \reg_wp.addr_data_f0[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[27]\); - - \prdata_RNO_17[0]\ : OR2B - port map(A => \status_full_0[0]\, B => prdata_13_sqmuxa, Y - => \status_full_m_i[0]\); - - \reg_wp.delta_snapshot[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[3]\); - - \prdata_RNO_4[19]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[19]\, Y - => \addr_data_f1_m_i[19]\); - - \prdata_RNO[14]\ : OR3C - port map(A => \prdata_39_0_iv_2[14]\, B => - \delta_snapshot_m_i[14]\, C => \prdata_39_0_iv_6[14]\, Y - => \prdata_39[14]\); - - \reg_wp.status_full_err_RNO_0[3]\ : NOR3A - port map(A => N_933_0, B => \status_full_err[3]\, C => - status_full_err_0(3), Y => N_145); - - \prdata_RNO_2[30]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[30]\, B => - \addr_matrix_f0_0_m_i[30]\, C => \prdata_39_0_iv_1[30]\, - Y => \prdata_39_0_iv_4[30]\); - - \reg_sp.addr_matrix_f1[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[1]\); - - \prdata_RNO_6[27]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[27]\, - Y => \addr_matrix_f0_0_m_i[27]\); - - \prdata_RNO_3[30]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[30]\, Y - => \addr_data_f2_m_i[30]\); - - \prdata_RNO_6[7]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[7]\, Y - => \delta_f2_f0_m_i[7]\); - - \reg_sp.addr_matrix_f0_0[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[11]\); - - \reg_wp.addr_data_f3[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[14]\); - - \prdata_RNO_1[22]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[22]\, C - => \addr_data_f1_m_i[22]\, Y => \prdata_39_0_iv_2[22]\); - - \prdata_RNO[28]\ : OR3C - port map(A => \prdata_39_0_iv_3[28]\, B => - \prdata_39_0_iv_2[28]\, C => \prdata_39_0_iv_4[28]\, Y - => \prdata_39[28]\); - - \prdata_RNO_4[20]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[20]\, Y - => \addr_data_f1_m_i[20]\); - - \status_full_ack_RNO[3]\ : NOR3A - port map(A => \status_full_0[3]\, B => apbi_c_53, C => - \status_full_5_i_o2[0]\, Y => \status_full_ack_8[3]\); - - \reg_wp.nb_burst_available_1_sqmuxa_0_a2_1\ : NOR3A - port map(A => apbi_c_20, B => apbi_c_21, C => apbi_c_22, Y - => N_159); - - \reg_wp.addr_data_f2[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[8]\); - - \prdata_RNO_14[8]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[8]\, Y - => \addr_matrix_f1_m_i[8]\); - - \prdata_RNO_13[7]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[7]\, - Y => \addr_matrix_f0_1_m_i[7]\); - - \reg_wp.delta_f2_f1[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[5]\); - - \reg_wp.nb_snapshot_param[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[5]\); - - \reg_wp.addr_data_f2[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[19]\); - - \prdata_RNO_1[18]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[18]\, C => \addr_matrix_f0_1_m_i[18]\, - Y => \prdata_39_0_iv_0[18]\); - - \reg_wp.addr_data_f0[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[17]\); - - \prdata_RNO_14[4]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[4]\, - C => \addr_matrix_f2_m_i[4]\, Y => \prdata_39_0_iv_1[4]\); - - \prdata_RNO_5[15]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[15]\, - C => \addr_matrix_f2_m_i[15]\, Y => - \prdata_39_0_iv_1[15]\); - - \reg_wp.status_full_err_RNO_0[2]\ : NOR3A - port map(A => N_933_0, B => \status_full_err[2]\, C => - status_full_err_0(2), Y => N_143); - - \prdata_RNO_6[2]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[2]\, C - => enable_f2_m_i, Y => \prdata_39_0_iv_7[2]\); - - \prdata_RNO_2[15]\ : NOR3C - port map(A => \addr_data_f1_m_i[15]\, B => - \addr_data_f0_m_i[15]\, C => \delta_snapshot_m_i[15]\, Y - => \prdata_39_0_iv_5[15]\); - - \prdata_RNO_8[13]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[13]\, Y => \addr_matrix_f0_1_m_i[13]\); - - \reg_wp.addr_data_f3[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[18]\); - - prdata_5_sqmuxa_0_a2_0 : NOR2A - port map(A => N_172, B => N_157, Y => prdata_5_sqmuxa_0); - - \prdata_RNO_4[2]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[2]\, C - => status_ready_matrix_f1_m_i, Y => - \prdata_39_0_iv_2[2]\); - - \prdata_RNO_2[29]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[29]\, B => - \addr_matrix_f0_0_m_i[29]\, C => \prdata_39_0_iv_1[29]\, - Y => \prdata_39_0_iv_4[29]\); - - \prdata_RNO_0[20]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[20]\, - C => \addr_data_f2_m_i[20]\, Y => \prdata_39_0_iv_3[20]\); - - \reg_sp.addr_matrix_f2[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[16]\); - - \reg_wp.delta_f2_f1[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[0]\); - - \prdata_RNO_15[0]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[0]\, - Y => \addr_data_f2_m_i[0]\); - - \reg_wp.status_new_err_RNO[1]\ : OA1B - port map(A => apbi_c_59, B => \status_full_5_i_o2[0]\, C - => N_149, Y => \status_new_err_RNO[1]\); - - \prdata_RNO_1[6]\ : AOI1B - port map(A => \nb_snapshot_param[6]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_5[6]\, Y => \prdata_39_0_iv_9[6]\); - - \reg_sp.addr_matrix_f2[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[11]\); - - \reg_sp.addr_matrix_f2[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[10]\); - - \reg_sp.addr_matrix_f0_0[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[18]\); - - \prdata_RNO_20[3]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f3\, Y => - enable_f3_m_i); - - \reg_sp.addr_matrix_f0_0[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[29]\); - - \prdata_RNO_10[8]\ : AOI1B - port map(A => \status_new_err[0]\, B => prdata_13_sqmuxa, C - => \addr_data_f0_m_i[8]\, Y => \prdata_39_0_iv_2[8]\); - - \prdata_RNO_3[7]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[7]\, Y - => \delta_snapshot_m_i[7]\); - - \reg_wp.delta_f2_f1[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[4]\); - - \reg_sp.addr_matrix_f0_1[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[20]\); - - \prdata_RNO_4[30]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[30]\, Y - => \addr_data_f1_m_i[30]\); - - \reg_sp.addr_matrix_f2[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[26]\); - - \reg_sp.addr_matrix_f0_1[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[23]\); - - \prdata_RNO_5[18]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[18]\, Y - => \addr_data_f3_m_i[18]\); - - \reg_wp.delta_snapshot[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[15]\); - - \prdata_RNO_2[18]\ : NOR3C - port map(A => \addr_data_f3_m_i[18]\, B => - \addr_data_f2_m_i[18]\, C => \prdata_39_0_iv_2[18]\, Y - => \prdata_39_0_iv_5[18]\); - - \reg_wp.data_shaping_R1\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => data_shaping_R1); - - \prdata_RNO_12[6]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[6]\, - Y => \addr_matrix_f0_0_m_i[6]\); - - \reg_sp.addr_matrix_f0_1[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[12]\); - - \reg_wp.delta_snapshot[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[0]\); - - \reg_sp.addr_matrix_f2[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[21]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_159, B => N_928, C => N_930, Y => - addr_matrix_f0_0_1_sqmuxa); - - \prdata_RNO_0[0]\ : NOR3C - port map(A => \delta_snapshot_m_i[0]\, B => - \prdata_39_0_iv_2[0]\, C => \prdata_39_0_iv_9[0]\, Y => - \prdata_39_0_iv_13[0]\); - - \prdata_RNO_8[1]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[1]\, B => - \addr_matrix_f0_0_m_i[1]\, C => \status_full_m_i[1]\, Y - => \prdata_39_0_iv_6[1]\); - - \reg_wp.enable_f3\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \enable_f3\); - - \prdata[24]\ : DFN1C0 - port map(D => \prdata_39[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(24)); - - \prdata_RNO[22]\ : OR3C - port map(A => \prdata_39_0_iv_3[22]\, B => - \prdata_39_0_iv_2[22]\, C => \prdata_39_0_iv_4[22]\, Y - => \prdata_39[22]\); - - \reg_sp.addr_matrix_f2[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[20]\); - - \prdata_RNO_4[15]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[15]\, - Y => \addr_matrix_f0_0_m_i[15]\); - - \prdata_RNO_18[0]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[0]\, Y - => \delta_f2_f1_m_i[0]\); - - \prdata_RNO_13[2]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[2]\, Y - => \delta_f2_f1_m_i[2]\); - - \prdata_RNO_8[8]\ : OR2B - port map(A => \nb_snapshot_param[8]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[8]\); - - \prdata_RNO_8[21]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[21]\, Y - => \addr_data_f1_m_i[21]\); - - \prdata_RNO_8[26]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[26]\, Y - => \addr_matrix_f2_m_i[26]\); - - \prdata_RNO_1[17]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[17]\, C - => \addr_data_f1_m_i[17]\, Y => \prdata_39_0_iv_2[17]\); - - \prdata_RNO_14[9]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[9]\, - Y => \addr_matrix_f0_0_m_i[9]\); - - \prdata_RNO[20]\ : OR3C - port map(A => \prdata_39_0_iv_3[20]\, B => - \prdata_39_0_iv_2[20]\, C => \prdata_39_0_iv_4[20]\, Y - => \prdata_39[20]\); - - \prdata_RNO_15[5]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[5]\, Y - => \delta_f2_f1_m_i[5]\); - - \prdata_RNO_12[3]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[3]\, Y - => \addr_data_f3_m_i[3]\); - - \reg_sp.addr_matrix_f0_1[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[31]\); - - \prdata_RNO_5[24]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[24]\, - Y => \addr_matrix_f0_1_m_i[24]\); - - \reg_sp.addr_matrix_f1[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[5]\); - - prdata_15_sqmuxa_0_a2 : NOR2B - port map(A => N_164, B => N_161, Y => prdata_15_sqmuxa); - - \reg_wp.delta_snapshot[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[12]\); - - \prdata_RNO_19[1]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[1]\, C - => \delta_f2_f1_m_i[1]\, Y => \prdata_39_0_iv_5[1]\); - - \reg_wp.status_new_err_RNO_0[2]\ : NOR3A - port map(A => N_933_0, B => \status_new_err[2]\, C => - status_new_err_0_2, Y => N_151); - - \prdata_RNO_6[11]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[11]\, Y - => \addr_data_f3_m_i[11]\); - - \prdata_RNO_6[16]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[16]\, - Y => \addr_matrix_f0_0_m_i[16]\); - - \prdata_RNO_3[10]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[10]\, C => \addr_matrix_f0_1_m_i[10]\, - Y => \prdata_39_0_iv_0[10]\); - - \prdata_RNO_14[5]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[5]\, - C => \addr_matrix_f2_m_i[5]\, Y => \prdata_39_0_iv_1[5]\); - - \prdata_RNO_17[3]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[3]\, Y - => \delta_snapshot_m_i[3]\); - - \prdata_RNO_8[22]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[22]\, Y - => \addr_matrix_f2_m_i[22]\); - - prdata_17_sqmuxa_0_a2 : NOR3B - port map(A => N_158, B => N_159, C => apbi_c_19, Y => - prdata_17_sqmuxa); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2_0_0\ : NOR3C - port map(A => N_159, B => N_928, C => N_166, Y => - addr_matrix_f0_1_1_sqmuxa_0); - - \reg_wp.addr_data_f1[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[30]\); - - \prdata_RNO_2[25]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[25]\, B => - \addr_matrix_f0_0_m_i[25]\, C => \prdata_39_0_iv_1[25]\, - Y => \prdata_39_0_iv_4[25]\); - - \prdata_RNO_4[18]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[18]\, - Y => \addr_matrix_f0_1_m_i[18]\); - - \reg_wp.nb_burst_available[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[2]\); - - \prdata_RNO_8[6]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[6]\, - Y => \addr_matrix_f2_m_i[6]\); - - \prdata_RNO_3[3]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[3]\, C - => \addr_data_f2_m_i[3]\, Y => \prdata_39_0_iv_3[3]\); - - \reg_wp.delta_snapshot[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[14]\); - - \reg_wp.delta_f2_f1[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[9]\); - - \reg_sp.addr_matrix_f2[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[14]\); - - \prdata_RNO_6[12]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[12]\, - C => \addr_data_f2_m_i[12]\, Y => \prdata_39_0_iv_3[12]\); - - \prdata_RNO_9[5]\ : OR2B - port map(A => \nb_burst_available[5]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[5]\); - - \prdata_RNO_5[0]\ : AOI1B - port map(A => \nb_burst_available[0]\, B => - prdata_17_sqmuxa, C => enable_f0_m_i, Y => - \prdata_39_0_iv_9[0]\); - - \reg_wp.addr_data_f3[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[27]\); - - \prdata_RNO_5[17]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[17]\, - Y => \addr_matrix_f0_1_m_i[17]\); - - \prdata_RNO_17[7]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[7]\, Y - => \addr_data_f0_m_i[7]\); - - \prdata_RNO_2[17]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[17]\, B => - \addr_matrix_f0_0_m_i[17]\, C => \prdata_39_0_iv_1[17]\, - Y => \prdata_39_0_iv_4[17]\); - - \reg_wp.nb_snapshot_param[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[10]\); - - \reg_sp.addr_matrix_f1[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[16]\); - - \reg_wp.delta_snapshot[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[11]\); - - \reg_sp.config_active_interruption_onNewMatrix\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => config_active_interruption_onError_0_sqmuxa, Q => - config_active_interruption_onNewMatrix); - - \reg_wp.addr_data_f1[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[31]\); - - \reg_wp.status_full_RNO[3]\ : OA1B - port map(A => apbi_c_53, B => \status_full_5_i_o2[0]\, C - => N_138, Y => \status_full_RNO[3]\); - - \prdata_RNO_3[24]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[24]\, Y - => \addr_data_f2_m_i[24]\); - - \reg_wp.addr_data_f3[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[19]\); - - \prdata_RNO_2[8]\ : NOR3C - port map(A => \prdata_39_0_iv_3[8]\, B => - \prdata_39_0_iv_2[8]\, C => \nb_burst_available_m_i[8]\, - Y => \prdata_39_0_iv_10[8]\); - - \reg_sp.addr_matrix_f1[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[11]\); - - \status_full_ack_RNO[2]\ : NOR3A - port map(A => \status_full_0[2]\, B => apbi_c_52, C => - N_933_0, Y => \status_full_ack_8[2]\); - - \reg_sp.addr_matrix_f0_1[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[24]\); - - \reg_sp.addr_matrix_f0_1[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[3]\); - - \reg_sp.addr_matrix_f0_1[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[25]\); - - \prdata_RNO_8[10]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[10]\, - C => \prdata_39_0_iv_1[10]\, Y => \prdata_39_0_iv_5[10]\); - - \reg_sp.addr_matrix_f1[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[10]\); - - \reg_sp.status_error_anticipating_empty_fifo_1_sqmuxa_0_a2\ : - NOR3 - port map(A => N_157, B => un1_apbi_2, C => N_169, Y => - status_error_anticipating_empty_fifo_1_sqmuxa); - - prdata_3_sqmuxa_0_a2 : NOR3C - port map(A => N_159, B => N_928, C => apbi_c_19, Y => - prdata_3_sqmuxa); - - \prdata_RNO_3[0]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[0]\, Y - => \delta_snapshot_m_i[0]\); - - \prdata_RNO_2[2]\ : NOR3C - port map(A => \prdata_39_0_iv_6[2]\, B => - \nb_snapshot_param_m_i[2]\, C => data_shaping_SP1_m_i, Y - => \prdata_39_0_iv_13[2]\); - - \prdata_RNO_7[7]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[7]\, Y - => \addr_data_f3_m_i[7]\); - - \prdata_RNO_13[5]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[5]\, - Y => \addr_matrix_f0_0_m_i[5]\); - - \prdata_RNO_3[4]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[4]\, C - => \addr_data_f1_m_i[4]\, Y => \prdata_39_0_iv_3[4]\); - - \lpp_top_apbreg.un1_apbi_2\ : OR2B - port map(A => apbi_c_49, B => apbi_c_16, Y => un1_apbi_2); - - \reg_wp.status_full_err_RNO[3]\ : OA1B - port map(A => apbi_c_57, B => \status_full_5_i_o2[0]\, C - => N_145, Y => \status_full_err_RNO[3]\); - - \reg_sp.addr_matrix_f2[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[7]\); - - \reg_sp.addr_matrix_f2[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[24]\); - - \reg_wp.addr_data_f1[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[24]\); - - \prdata_RNO_5[6]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[6]\, C - => \addr_data_f2_m_i[6]\, Y => \prdata_39_0_iv_3[6]\); - - \prdata_RNO_2[28]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[28]\, B => - \addr_matrix_f0_0_m_i[28]\, C => \prdata_39_0_iv_1[28]\, - Y => \prdata_39_0_iv_4[28]\); - - \prdata_RNO_16[4]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[4]\, - Y => \addr_data_f2_m_i[4]\); - - \prdata_RNO[17]\ : OR3C - port map(A => \prdata_39_0_iv_3[17]\, B => - \prdata_39_0_iv_2[17]\, C => \prdata_39_0_iv_4[17]\, Y - => \prdata_39[17]\); - - \reg_wp.addr_data_f0[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[23]\); - - \prdata_RNO[25]\ : OR3C - port map(A => \prdata_39_0_iv_3[25]\, B => - \prdata_39_0_iv_2[25]\, C => \prdata_39_0_iv_4[25]\, Y - => \prdata_39[25]\); - - \prdata[20]\ : DFN1C0 - port map(D => \prdata_39[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(20)); - - \reg_wp.addr_data_f0[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[20]\); - - \prdata_RNO_1[4]\ : AOI1B - port map(A => \nb_snapshot_param[4]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_6[4]\, Y => \prdata_39_0_iv_10[4]\); - - \prdata_RNO_21[1]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[1]\, Y - => \delta_f2_f1_m_i[1]\); - - \reg_wp.addr_data_f3[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[1]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \prdata_RNO_8[3]\ : NOR3C - port map(A => \delta_snapshot_m_i[3]\, B => - \prdata_39_0_iv_1[3]\, C => \nb_burst_available_m_i[3]\, - Y => \prdata_39_0_iv_11[3]\); - - \reg_sp.addr_matrix_f0_0[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[27]\); - - \prdata_RNO_1[29]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[29]\, C - => \addr_data_f1_m_i[29]\, Y => \prdata_39_0_iv_2[29]\); - - \prdata_RNO_5[23]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[23]\, Y - => \addr_data_f3_m_i[23]\); - - \prdata_RNO_17[8]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[8]\, Y - => \addr_data_f0_m_i[8]\); - - \prdata_RNO_10[6]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[6]\, Y - => \delta_snapshot_m_i[6]\); - - \prdata_RNO_0[14]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[14]\, C - => \addr_data_f1_m_i[14]\, Y => \prdata_39_0_iv_2[14]\); - - prdata_14_sqmuxa_0_a2 : NOR3B - port map(A => apbi_c_21, B => apbi_c_19, C => N_931, Y => - prdata_14_sqmuxa); - - \reg_wp.addr_data_f1[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[28]\); - - \reg_wp.delta_snapshot[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[13]\); - - \prdata_RNO_8[7]\ : OR2B - port map(A => \nb_snapshot_param[7]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[7]\); - - \reg_wp.addr_data_f0[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[21]\); - - prdata_3_sqmuxa_0_a2_0 : NOR3C - port map(A => N_159, B => N_928, C => apbi_c_19, Y => - prdata_3_sqmuxa_0); - - \prdata[23]\ : DFN1C0 - port map(D => \prdata_39[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(23)); - - \prdata_RNO_4[17]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[17]\, - Y => \addr_data_f1_m_i[17]\); - - \reg_wp.delta_f2_f0[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[6]\); - - \prdata_RNO_9[11]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[11]\, - C => \addr_data_f2_m_i[11]\, Y => \prdata_39_0_iv_3[11]\); - - \prdata_RNO_7[21]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[21]\, C - => \addr_data_f1_m_i[21]\, Y => \prdata_39_0_iv_2[21]\); - - \prdata_RNO_7[26]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[26]\, C - => \addr_matrix_f2_m_i[26]\, Y => \prdata_39_0_iv_1[26]\); - - \prdata_RNO[9]\ : OR3C - port map(A => \prdata_39_0_iv_9[9]\, B => - \prdata_39_0_iv_8[9]\, C => \prdata_39_0_iv_10[9]\, Y => - \prdata_39[9]\); - - \reg_wp.addr_data_f0[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[13]\); - - \prdata_RNO_20[2]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[2]\, - Y => \addr_matrix_f2_m_i[2]\); - - \prdata_RNO_12[7]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[7]\, - Y => \addr_matrix_f2_m_i[7]\); - - \reg_wp.addr_data_f0[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[10]\); - - \prdata_RNO_2[31]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[31]\, B => - \addr_matrix_f0_0_m_i[31]\, C => \prdata_39_0_iv_1[31]\, - Y => \prdata_39_0_iv_4[31]\); - - \prdata_RNO_13[3]\ : AOI1B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[3]\, C - => enable_f3_m_i, Y => \prdata_39_0_iv_5[3]\); - - \prdata_RNO_14[3]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[3]\, - Y => \addr_matrix_f0_1_m_i[3]\); - - \prdata_RNO_3[31]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[31]\, Y - => \addr_data_f2_m_i[31]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0\ : NOR3C - port map(A => apbi_c_22, B => N_928, C => apbi_c_21, Y => - N_168); - - \prdata_RNO_5[5]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[5]\, C - => \prdata_39_0_iv_2[5]\, Y => \prdata_39_0_iv_7[5]\); - - \reg_wp.addr_data_f1[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[14]\); - - \reg_sp.addr_matrix_f2[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[1]\); - - \reg_wp.delta_snapshot[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[9]\); - - \prdata[30]\ : DFN1C0 - port map(D => \prdata_39[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(30)); - - \prdata_RNO_13[8]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[8]\, - Y => \addr_matrix_f2_m_i[8]\); - - \reg_wp.status_new_err[3]\ : DFN1C0 - port map(D => \status_new_err_RNO[3]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_new_err_0[3]\); - - \reg_wp.addr_data_f1[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[0]\); - - \prdata_RNO_12[2]\ : OR2B - port map(A => \status_full_0[2]\, B => prdata_13_sqmuxa, Y - => \status_full_m_i[2]\); - - \reg_wp.delta_f2_f0[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[4]\); - - \prdata_RNO_12[1]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f1\, Y => - enable_f1_m_i); - - \prdata[11]\ : DFN1C0 - port map(D => \prdata_39[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(11)); - - \reg_sp.addr_matrix_f0_0[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[19]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0_0\ : NOR3C - port map(A => apbi_c_22, B => N_928, C => apbi_c_21, Y => - N_168_0); - - \reg_wp.addr_data_f0[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[11]\); - - \prdata_RNO_4[21]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[21]\, - Y => \addr_matrix_f0_1_m_i[21]\); - - \prdata_RNO_4[26]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[26]\, Y - => \addr_data_f1_m_i[26]\); - - \prdata_RNO_9[12]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[12]\, Y => \addr_data_f2_m_i[12]\); - - \prdata_RNO_3[23]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[23]\, Y - => \addr_matrix_f2_m_i[23]\); - - \prdata_RNO_7[22]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[22]\, C - => \addr_matrix_f2_m_i[22]\, Y => \prdata_39_0_iv_1[22]\); - - \reg_sp.addr_matrix_f0_1[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[5]\); - - \reg_wp.addr_data_f1[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[18]\); - - \prdata_RNO_2[27]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[27]\, B => - \addr_matrix_f0_0_m_i[27]\, C => \prdata_39_0_iv_1[27]\, - Y => \prdata_39_0_iv_4[27]\); - - \prdata_RNO_9[0]\ : NOR3C - port map(A => \status_full_m_i[0]\, B => - \delta_f2_f1_m_i[0]\, C => \prdata_39_0_iv_5[0]\, Y => - \prdata_39_0_iv_11[0]\); - - \reg_sp.status_ready_matrix_f0_1\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f0_1); - - \reg_sp.addr_matrix_f1[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[14]\); - - \prdata_RNO_5[8]\ : NOR3C - port map(A => \addr_matrix_f2_m_i[8]\, B => - \addr_matrix_f1_m_i[8]\, C => \delta_snapshot_m_i[8]\, Y - => \prdata_39_0_iv_6[8]\); - - \prdata_RNO[30]\ : OR3C - port map(A => \prdata_39_0_iv_3[30]\, B => - \prdata_39_0_iv_2[30]\, C => \prdata_39_0_iv_4[30]\, Y - => \prdata_39[30]\); - - \apbo.pirq_RNO_2[15]\ : NOR3A - port map(A => \pirq_2_i_a2_5[15]\, B => status_full(1), C - => status_full(0), Y => \pirq_2_i_a2_8[15]\); - - \prdata_RNO_0[21]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[21]\, C - => \addr_matrix_f2_m_i[21]\, Y => \prdata_39_0_iv_1[21]\); - - \reg_sp.addr_matrix_f0_1[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[11]\); - - \prdata_RNO_7[14]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[14]\, - Y => \addr_matrix_f2_m_i[14]\); - - \prdata_RNO_11[0]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f0\, Y => - enable_f0_m_i); - - \prdata_RNO_0[26]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[26]\, - C => \addr_data_f2_m_i[26]\, Y => \prdata_39_0_iv_3[26]\); - - \prdata_RNO_4[8]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[8]\, Y - => \delta_f2_f1_m_i[8]\); - - \reg_sp.addr_matrix_f0_0[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[5]\); - - prdata_12_sqmuxa_0_a2 : NOR2A - port map(A => N_168, B => N_157, Y => prdata_12_sqmuxa); - - \prdata_RNO_21[3]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[3]\, - Y => \addr_matrix_f2_m_i[3]\); - - \prdata_RNO_4[22]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[22]\, Y - => \addr_data_f1_m_i[22]\); - - \reg_wp.addr_data_f0[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[9]\); - - prdata_5_sqmuxa_0_a2 : NOR2A - port map(A => N_172, B => N_157, Y => prdata_5_sqmuxa); - - \reg_wp.addr_data_f2[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[2]\); - - \prdata_RNO_6[30]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[30]\, - Y => \addr_matrix_f0_0_m_i[30]\); - - \prdata_RNO_6[24]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[24]\, - Y => \addr_matrix_f0_0_m_i[24]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_1\ : NOR3B - port map(A => apbi_c_21, B => N_928, C => apbi_c_22, Y => - N_172); - - \reg_wp.addr_data_f0[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[25]\); - - \reg_sp.addr_matrix_f0_0[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[7]\); - - \prdata_RNO_17[2]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[2]\, - Y => \addr_matrix_f0_0_m_i[2]\); - - \prdata_RNO_0[13]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[13]\, C - => \addr_data_f1_m_i[13]\, Y => \prdata_39_0_iv_2[13]\); - - \reg_wp.nb_snapshot_param[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[8]\); - - \reg_wp.addr_data_f0[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[26]\); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_172, B => N_157, C => un1_apbi_2, Y => - addr_matrix_f2_1_sqmuxa); - - \reg_wp.delta_snapshot_1_sqmuxa_0_a2\ : NOR3B - port map(A => apbi_c_21, B => N_166, C => N_931, Y => - delta_snapshot_1_sqmuxa); - - \reg_sp.addr_matrix_f0_1[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[6]\); - - \prdata_RNO_1[25]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[25]\, C - => \addr_data_f1_m_i[25]\, Y => \prdata_39_0_iv_2[25]\); - - \reg_wp.addr_data_f1_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_166, B => apbi_c_21, C => N_931, Y => - addr_data_f1_1_sqmuxa_0); - - \prdata_RNO_15[1]\ : AOI1B - port map(A => prdata_0_sqmuxa, B => - config_active_interruption_onError, C => - status_ready_matrix_f0_1_m_i, Y => \prdata_39_0_iv_2[1]\); - - \reg_wp.addr_data_f2[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[17]\); - - \prdata_RNO[11]\ : OR3C - port map(A => \prdata_39_0_iv_5[11]\, B => - \prdata_39_0_iv_4[11]\, C => \prdata_39_0_iv_6[11]\, Y - => \prdata_39[11]\); - - \prdata[25]\ : DFN1C0 - port map(D => \prdata_39[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(25)); - - \prdata_RNO_1[8]\ : NOR3C - port map(A => \delta_f2_f0_m_i[8]\, B => - \addr_data_f3_m_i[8]\, C => \nb_snapshot_param_m_i[8]\, Y - => \prdata_39_0_iv_8[8]\); - - \prdata_RNO_0[22]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[22]\, - C => \addr_data_f2_m_i[22]\, Y => \prdata_39_0_iv_3[22]\); - - \prdata_RNO_4[31]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[31]\, Y - => \addr_data_f1_m_i[31]\); - - \reg_wp.addr_data_f2[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[24]\); - - \reg_wp.status_full_err_RNO_0[1]\ : NOR3A - port map(A => N_933_0, B => \status_full_err[1]\, C => - status_full_err_0(1), Y => N_141); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_172, B => N_157, C => un1_apbi_2, Y => - addr_matrix_f2_1_sqmuxa_0); - - \reg_sp.addr_matrix_f2[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[8]\); - - \prdata_RNO_8[9]\ : OR2B - port map(A => \nb_snapshot_param[9]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[9]\); - - \status_full_ack[3]\ : DFN1C0 - port map(D => \status_full_ack_8[3]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => status_full_ack(3)); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_164, B => N_157, C => un1_apbi_2, Y => - delta_f2_f0_1_sqmuxa); - - \prdata_RNO[29]\ : OR3C - port map(A => \prdata_39_0_iv_3[29]\, B => - \prdata_39_0_iv_2[29]\, C => \prdata_39_0_iv_4[29]\, Y - => \prdata_39[29]\); - - \prdata_RNO_14[0]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[0]\, - C => \addr_matrix_f2_m_i[0]\, Y => \prdata_39_0_iv_1[0]\); - - \prdata_RNO_6[5]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[5]\, B => - \addr_matrix_f0_0_m_i[5]\, C => \prdata_39_0_iv_1[5]\, Y - => \prdata_39_0_iv_6[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \prdata_RNO_8[29]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[29]\, Y - => \addr_matrix_f2_m_i[29]\); - - \reg_wp.status_full[0]\ : DFN1C0 - port map(D => \status_full_RNO[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \status_full_0[0]\); - - \reg_sp.addr_matrix_f0_1[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[18]\); - - \prdata_RNO[16]\ : OR3C - port map(A => \prdata_39_0_iv_3[16]\, B => - \prdata_39_0_iv_2[16]\, C => \prdata_39_0_iv_4[16]\, Y - => \prdata_39[16]\); - - \prdata[0]\ : DFN1C0 - port map(D => \prdata_39[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(0)); - - \apbo.pirq_RNO_5[15]\ : NOR2 - port map(A => status_full(2), B => status_full(3), Y => - \pirq_2_i_a2_5[15]\); - - \reg_wp.addr_data_f0_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_930, B => apbi_c_21, C => N_931, Y => - addr_data_f0_1_sqmuxa_0); - - \reg_wp.addr_data_f0[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[15]\); - - prdata_9_sqmuxa_0_a2_0 : NOR3 - port map(A => apbi_c_21, B => N_931, C => apbi_c_19, Y => - prdata_9_sqmuxa_0); - - \reg_wp.addr_data_f3[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[6]\); - - \reg_wp.addr_data_f2[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[28]\); - - \reg_wp.addr_data_f0[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[16]\); - - \reg_wp.status_full_err[1]\ : DFN1C0 - port map(D => \status_full_err_RNO[1]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_full_err[1]\); - - \reg_wp.nb_burst_available[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[10]\); - - \reg_wp.nb_snapshot_param[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[1]\); - - \reg_wp.addr_data_f1[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[29]\); - - \reg_sp.addr_matrix_f0_0[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[26]\); - - \prdata_RNO_7[4]\ : OR2B - port map(A => \nb_burst_available[4]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[4]\); - - \prdata_RNO_5[20]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[20]\, - Y => \addr_matrix_f0_1_m_i[20]\); - - \prdata_RNO_6[19]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[19]\, - Y => \addr_matrix_f0_0_m_i[19]\); - - prdata_1_sqmuxa_0_a2_0 : OR2A - port map(A => apbi_c_19, B => apbi_c_20, Y => N_157); - - \reg_wp.delta_f2_f1_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_930, B => N_164, C => apbi_c_20, Y => - delta_f2_f1_1_sqmuxa); - - \reg_wp.addr_data_f2[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[5]\); - - \reg_sp.addr_matrix_f1[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[3]\); - - \prdata_RNO_1[28]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[28]\, C - => \addr_data_f1_m_i[28]\, Y => \prdata_39_0_iv_2[28]\); - - \reg_sp.addr_matrix_f1[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[25]\); - - \prdata_RNO_16[0]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[0]\, Y - => \addr_data_f1_m_i[0]\); - - \reg_wp.addr_data_f3[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[23]\); - - \reg_wp.addr_data_f3[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[20]\); - - \reg_wp.nb_burst_available[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[0]\); - - \prdata_RNO_3[11]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[11]\, - C => \addr_matrix_f2_m_i[11]\, Y => - \prdata_39_0_iv_1[11]\); - - \prdata_RNO_3[16]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[16]\, Y => \addr_data_f2_m_i[16]\); - - \reg_wp.addr_data_f3[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[4]\); - - \reg_sp.addr_matrix_f1[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[22]\); - - \prdata_RNO_4[4]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f0\, Y => - burst_f0_m_i); - - \prdata_RNO_7[13]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[13]\, - Y => \addr_matrix_f2_m_i[13]\); - - \prdata[9]\ : DFN1C0 - port map(D => \prdata_39[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(9)); - - \prdata[8]\ : DFN1C0 - port map(D => \prdata_39[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(8)); - - \prdata_RNO_10[3]\ : OR3A - port map(A => status_ready_matrix_f2, B => N_157, C => - N_169, Y => status_ready_matrix_f2_m_i); - - \reg_sp.addr_matrix_f1[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[27]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg_wp.addr_data_f3[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[21]\); - - \prdata_RNO_6[23]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[23]\, Y - => \addr_data_f2_m_i[23]\); - - \prdata_RNO_18[5]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[5]\, - Y => \addr_matrix_f2_m_i[5]\); - - \reg_wp.addr_data_f0[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[22]\); - - \prdata[22]\ : DFN1C0 - port map(D => \prdata_39[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(22)); - - \prdata_RNO_5[3]\ : NOR3C - port map(A => \delta_f2_f0_m_i[3]\, B => - \addr_data_f3_m_i[3]\, C => \prdata_39_0_iv_5[3]\, Y => - \prdata_39_0_iv_9[3]\); - - \prdata_RNO_11[5]\ : AOI1B - port map(A => \status_full_err[1]\, B => prdata_13_sqmuxa, - C => status_error_bad_component_error_m_i, Y => - \prdata_39_0_iv_2[5]\); - - \reg_sp.addr_matrix_f0_0[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[17]\); - - prdata_10_sqmuxa_0_a2 : NOR3A - port map(A => apbi_c_19, B => apbi_c_21, C => N_931, Y => - prdata_10_sqmuxa); - - \prdata[29]\ : DFN1C0 - port map(D => \prdata_39[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(29)); - - \prdata_RNO_4[6]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[6]\, B => - \addr_matrix_f0_0_m_i[6]\, C => \delta_f2_f1_m_i[6]\, Y - => \prdata_39_0_iv_5[6]\); - - \reg_wp.nb_snapshot_param[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[4]\); - - \reg_wp.nb_snapshot_param[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[7]\); - - \reg_wp.addr_data_f1[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[19]\); - - \prdata_RNO_3[20]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[20]\, Y - => \addr_data_f2_m_i[20]\); - - \prdata_RNO_3[12]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[12]\, - Y => \addr_data_f1_m_i[12]\); - - \reg_sp.addr_matrix_f2[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[5]\); - - \prdata_RNO_9[4]\ : OR3B - port map(A => N_161_0, B => \data_shaping_R1_0\, C => N_163, - Y => data_shaping_R1_m_i); - - \prdata_RNO[4]\ : OR3C - port map(A => \prdata_39_0_iv_11[4]\, B => - \prdata_39_0_iv_10[4]\, C => \prdata_39_0_iv_14[4]\, Y - => \prdata_39[4]\); - - \prdata_RNO_1[14]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[14]\, - Y => \delta_snapshot_m_i[14]\); - - \prdata_RNO_6[9]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[9]\, Y - => \delta_f2_f0_m_i[9]\); - - \reg_sp.addr_matrix_f1[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[31]\); - - \prdata_RNO_4[1]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[1]\, C - => \addr_data_f1_m_i[1]\, Y => \prdata_39_0_iv_3[1]\); - - \reg_wp.nb_burst_available[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[3]\); - - \reg_sp.addr_matrix_f1[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[30]\); - - \prdata_RNO_8[11]\ : OR2B - port map(A => \status_new_err_0[3]\, B => prdata_13_sqmuxa, - Y => \status_new_err_m_i[3]\); - - \prdata_RNO_8[16]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[16]\, - Y => \addr_matrix_f2_m_i[16]\); - - \reg_wp.nb_burst_available_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_158, B => N_159, C => N_930, Y => - nb_burst_available_1_sqmuxa); - - \reg_sp.status_ready_matrix_f0_0\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f0_0); - - \prdata_RNO_0[2]\ : NOR3C - port map(A => \prdata_39_0_iv_3[2]\, B => - \prdata_39_0_iv_2[2]\, C => \prdata_39_0_iv_9[2]\, Y => - \prdata_39_0_iv_12[2]\); - - \reg_wp.addr_data_f1[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[6]\); - - \prdata_RNO_10[10]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[10]\, Y => \addr_data_f2_m_i[10]\); - - \reg_wp.addr_data_f1[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[7]\); - - \reg_wp.addr_data_f0[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[12]\); - - \prdata_RNO_8[25]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[25]\, Y - => \addr_matrix_f2_m_i[25]\); - - \prdata_RNO_1[27]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[27]\, C - => \addr_data_f1_m_i[27]\, Y => \prdata_39_0_iv_2[27]\); - - \reg_sp.addr_matrix_f0_0[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[20]\); - - \prdata_RNO_18[4]\ : OR3A - port map(A => status_error_anticipating_empty_fifo, B => - N_157, C => N_169, Y => - status_error_anticipating_empty_fifo_m_i); - - \prdata_RNO_20[4]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[4]\, Y - => \delta_f2_f1_m_i[4]\); - - \prdata_RNO_0[10]\ : NOR3C - port map(A => \prdata_39_0_iv_0[10]\, B => - \addr_data_f3_m_i[10]\, C => \prdata_39_0_iv_3[10]\, Y - => \prdata_39_0_iv_7[10]\); - - \reg_wp.nb_snapshot_param_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_158, B => N_159, C => N_166, Y => - nb_snapshot_param_1_sqmuxa); - - \reg_wp.enable_f1\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \enable_f1\); - - \reg_sp.addr_matrix_f0_0[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[23]\); - - \prdata_RNO_4[9]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[9]\, - C => \addr_matrix_f2_m_i[9]\, Y => \prdata_39_0_iv_1[9]\); - - \prdata_RNO_10[15]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[15]\, - Y => \addr_matrix_f2_m_i[15]\); - - \prdata_RNO_8[12]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[12]\, Y => \addr_matrix_f0_1_m_i[12]\); - - \prdata[4]\ : DFN1C0 - port map(D => \prdata_39[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(4)); - - \prdata_RNO_6[15]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[15]\, Y => \addr_data_f2_m_i[15]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_2 is - - port( S_0_18 : in std_logic; - S_0_0 : in std_logic; - S_i : in std_logic_vector(1 to 1); - alu_sel_coeff_0 : in std_logic_vector(2 to 2); - S_25 : in std_logic; - S_7 : in std_logic; - S_6 : in std_logic; - S_15 : in std_logic; - S_20 : in std_logic; - S_11 : in std_logic; - S_17 : in std_logic; - S_10 : in std_logic; - S_9 : in std_logic; - S_13 : in std_logic; - S_26 : in std_logic; - S_16 : in std_logic; - S_19 : in std_logic; - S_0_d0 : in std_logic; - S_33 : in std_logic; - S_12 : in std_logic; - S_8 : in std_logic; - S_22 : in std_logic; - S_2 : in std_logic; - S_23 : in std_logic; - S_5 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 3); - alu_coef_s : out std_logic_vector(8 downto 0) - ); - -end MUXN_9_2; - -architecture DEF_ARCH of MUXN_9_2 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_43, N_19, N_47, N_25, N_48, N_28, N_49, N_50, N_56, - N_40, N_37, N_16, N_55, N_52, N_53, N_44, N_45, N_42, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \NB_STAGE_2.all_input.6.RES_8_1[6]\ : MX2 - port map(A => S_2, B => S_20, S => alu_sel_coeff(4), Y => - N_52); - - \NB_STAGE_2.all_input.7.RES_6_3[7]\ : MX2 - port map(A => N_55, B => N_37, S => alu_sel_coeff(3), Y => - alu_coef_s(7)); - - \NB_STAGE_2.all_input.7.RES_6_2[7]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_10, Y => N_37); - - \NB_STAGE_2.all_input.4.RES_12_1[4]\ : MX2C - port map(A => S_2, B => S_22, S => alu_sel_coeff(4), Y => - N_48); - - \NB_STAGE_2.all_input.0.RES_20_2[0]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_17, Y => N_16); - - \NB_STAGE_2.all_input.2.RES_16_2[2]\ : MX2C - port map(A => S_15, B => S_33, S => alu_sel_coeff(4), Y => - N_45); - - \NB_STAGE_2.all_input.1.RES_18_1[1]\ : MX2C - port map(A => S_7, B => S_25, S => alu_sel_coeff(4), Y => - N_43); - - GND_i_0 : GND - port map(Y => GND_0); - - \NB_STAGE_2.all_input.2.RES_16_3[2]\ : MX2 - port map(A => N_44, B => N_45, S => alu_sel_coeff(3), Y => - alu_coef_s(2)); - - \NB_STAGE_2.all_input.2.RES_16_1[2]\ : MX2 - port map(A => S_6, B => S_11, S => alu_sel_coeff(4), Y => - N_44); - - VCC_i : VCC - port map(Y => \VCC\); - - \NB_STAGE_2.all_input.6.RES_8_2[6]\ : MX2C - port map(A => S_11, B => S_33, S => alu_sel_coeff(4), Y => - N_53); - - \NB_STAGE_2.all_input.3.RES_14_1[3]\ : MX2C - port map(A => S_5, B => S_23, S => alu_sel_coeff(4), Y => - N_47); - - \NB_STAGE_2.all_input.3.RES_14_2[3]\ : OA1C - port map(A => S_26, B => alu_sel_coeff_0(2), C => - alu_sel_coeff(4), Y => N_25); - - GND_i : GND - port map(Y => \GND\); - - \NB_STAGE_2.all_input.3.RES_14_3[3]\ : MX2 - port map(A => N_47, B => N_25, S => alu_sel_coeff(3), Y => - alu_coef_s(3)); - - \NB_STAGE_2.all_input.8.RES_4_3[8]\ : MX2 - port map(A => N_56, B => N_40, S => alu_sel_coeff(3), Y => - alu_coef_s(8)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \NB_STAGE_2.all_input.1.RES_18_3[1]\ : MX2 - port map(A => N_43, B => N_19, S => alu_sel_coeff(3), Y => - alu_coef_s(1)); - - \NB_STAGE_2.all_input.6.RES_8_3[6]\ : MX2 - port map(A => N_52, B => N_53, S => alu_sel_coeff(3), Y => - alu_coef_s(6)); - - \NB_STAGE_2.all_input.8.RES_4_1[8]\ : MX2C - port map(A => S_0_d0, B => S_19, S => alu_sel_coeff(4), Y - => N_56); - - \NB_STAGE_2.all_input.4.RES_12_3[4]\ : MX2 - port map(A => N_48, B => N_28, S => alu_sel_coeff(3), Y => - alu_coef_s(4)); - - \NB_STAGE_2.all_input.4.RES_12_2[4]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_13, Y => N_28); - - \NB_STAGE_2.all_input.0.RES_20_3[0]\ : MX2 - port map(A => N_42, B => N_16, S => alu_sel_coeff(3), Y => - alu_coef_s(0)); - - \NB_STAGE_2.all_input.8.RES_4_2[8]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_9, Y => N_40); - - \NB_STAGE_2.all_input.7.RES_6_1[7]\ : MX2C - port map(A => S_i(1), B => S_19, S => alu_sel_coeff(4), Y - => N_55); - - \NB_STAGE_2.all_input.1.RES_18_2[1]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_16, Y => N_19); - - \NB_STAGE_2.all_input.5.RES_10_1[5]\ : MX2C - port map(A => S_5, B => S_8, S => alu_sel_coeff(4), Y => - N_49); - - \NB_STAGE_2.all_input.5.RES_10_2[5]\ : MX2C - port map(A => S_12, B => S_33, S => alu_sel_coeff(4), Y => - N_50); - - \NB_STAGE_2.all_input.5.RES_10_3[5]\ : MX2 - port map(A => N_49, B => N_50, S => alu_sel_coeff(3), Y => - alu_coef_s(5)); - - \NB_STAGE_2.all_input.0.RES_20_1[0]\ : MX2C - port map(A => S_0_0, B => S_0_18, S => alu_sel_coeff(4), Y - => N_42); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_3 is - - port( alu_coef_s : out std_logic_vector(8 downto 0); - S_0_0 : in std_logic; - S_0_18 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0) - ); - -end MUXN_9_3; - -architecture DEF_ARCH of MUXN_9_3 is - - component MUXN_9_2 - port( S_0_18 : in std_logic := 'U'; - S_0_0 : in std_logic := 'U'; - S_i : in std_logic_vector(1 to 1) := (others => 'U'); - alu_sel_coeff_0 : in std_logic_vector(2 to 2) := (others => 'U'); - S_25 : in std_logic := 'U'; - S_7 : in std_logic := 'U'; - S_6 : in std_logic := 'U'; - S_15 : in std_logic := 'U'; - S_20 : in std_logic := 'U'; - S_11 : in std_logic := 'U'; - S_17 : in std_logic := 'U'; - S_10 : in std_logic := 'U'; - S_9 : in std_logic := 'U'; - S_13 : in std_logic := 'U'; - S_26 : in std_logic := 'U'; - S_16 : in std_logic := 'U'; - S_19 : in std_logic := 'U'; - S_0_d0 : in std_logic := 'U'; - S_33 : in std_logic := 'U'; - S_12 : in std_logic := 'U'; - S_8 : in std_logic := 'U'; - S_22 : in std_logic := 'U'; - S_2 : in std_logic := 'U'; - S_23 : in std_logic := 'U'; - S_5 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 3) := (others => 'U'); - alu_coef_s : out std_logic_vector(8 downto 0) - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO14 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI4 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AO16 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO17 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \S[0]_net_1\, \S[9]_net_1\, \S[13]_net_1\, - \S[16]_net_1\, \S[22]_net_1\, \S[26]_net_1\, \S[33]\, - \S[23]_net_1\, \S_i[1]\, \S[5]\, \S[19]\, \S[12]_net_1\, - \S[2]_net_1\, \S[20]_net_1\, \S[17]_net_1\, \S[10]_net_1\, - \S[25]_net_1\, \S[15]_net_1\, \S[11]_net_1\, \S[8]_net_1\, - \S[7]_net_1\, \S[6]_net_1\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : MUXN_9_2 - Use entity work.MUXN_9_2(DEF_ARCH); -begin - - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_2 - port map(S_0_18 => \S[26]_net_1\, S_0_0 => \S[8]_net_1\, - S_i(1) => \S_i[1]\, alu_sel_coeff_0(2) => - alu_sel_coeff_0_2, S_25 => \S[25]_net_1\, S_7 => - \S[7]_net_1\, S_6 => \S[6]_net_1\, S_15 => \S[15]_net_1\, - S_20 => \S[20]_net_1\, S_11 => \S[11]_net_1\, S_17 => - \S[17]_net_1\, S_10 => \S[10]_net_1\, S_9 => \S[9]_net_1\, - S_13 => \S[13]_net_1\, S_26 => S_0_18, S_16 => - \S[16]_net_1\, S_19 => \S[19]\, S_0_d0 => \S[0]_net_1\, - S_33 => \S[33]\, S_12 => \S[12]_net_1\, S_8 => S_0_0, - S_22 => \S[22]_net_1\, S_2 => \S[2]_net_1\, S_23 => - \S[23]_net_1\, S_5 => \S[5]\, alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0)); - - \S[26]\ : AX1B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[26]_net_1\); - - \S[13]\ : XO1A - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[13]_net_1\); - - \S[3]\ : XA1 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[5]\); - - \S[9]\ : AO14 - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff(1), C - => alu_sel_coeff_0_0, Y => \S[9]_net_1\); - - \S[23]\ : XA1C - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_0, C - => alu_sel_coeff_0_2, Y => \S[23]_net_1\); - - \S[15]\ : AXOI5 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[15]_net_1\); - - \S[11]\ : XAI1 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[11]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \S[8]\ : AXO5 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), C - => alu_sel_coeff(2), Y => \S[8]_net_1\); - - \S[6]\ : AXOI4 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), C - => alu_sel_coeff(2), Y => \S[6]_net_1\); - - \S[25]\ : AXOI3 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[25]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \S[17]\ : AO16 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[17]_net_1\); - - \S[10]\ : AO17 - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(2), C - => alu_sel_coeff(1), Y => \S[10]_net_1\); - - \S[20]\ : OA1A - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(0), C - => alu_sel_coeff(1), Y => \S[20]_net_1\); - - \S[7]\ : AO16 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), C - => alu_sel_coeff(2), Y => \S[7]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \S[18]\ : XAI1A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[19]\); - - \S[0]\ : AXO5 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[0]_net_1\); - - \S[29]\ : OR3 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), C - => alu_sel_coeff_0_2, Y => \S[33]\); - - \S[1]\ : XNOR2 - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff_0_0, Y - => \S_i[1]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \S[12]\ : AO1A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), C - => alu_sel_coeff(2), Y => \S[12]_net_1\); - - \S[22]\ : AXO5 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[22]_net_1\); - - \S[2]\ : NOR3B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[2]_net_1\); - - \S[16]\ : MX2B - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff_0_0, S - => alu_sel_coeff(1), Y => \S[16]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_4 is - - port( alu_coef_s : out std_logic_vector(8 downto 0); - S_0 : out std_logic; - S_i_0 : out std_logic_vector(33 to 33); - alu_sel_coeff : in std_logic_vector(4 downto 0); - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff_0_0 : in std_logic - ); - -end MUXN_9_4; - -architecture DEF_ARCH of MUXN_9_4 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MUXN_9_3 - port( alu_coef_s : out std_logic_vector(8 downto 0); - S_0_0 : in std_logic := 'U'; - S_0_18 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U') - ); - end component; - - signal \S[26]\, \S[8]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : MUXN_9_3 - Use entity work.MUXN_9_3(DEF_ARCH); -begin - - S_0 <= \S[8]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \S[20]\ : OR2B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), Y - => \S[8]\); - - \S[18]\ : XOR2 - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(1), Y - => S_i_0(33)); - - VCC_i : VCC - port map(Y => \VCC\); - - \S[23]\ : NOR2A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), Y - => \S[26]\); - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_3 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), S_0_0 => - \S[8]\, S_0_18 => \S[26]\, alu_sel_coeff_0_0 => - alu_sel_coeff_0_0, alu_sel_coeff_0_2 => alu_sel_coeff_0_2, - alu_sel_coeff(4) => alu_sel_coeff(4), alu_sel_coeff(3) - => alu_sel_coeff(3), alu_sel_coeff(2) => - alu_sel_coeff(2), alu_sel_coeff(1) => alu_sel_coeff(1), - alu_sel_coeff(0) => alu_sel_coeff(0)); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_5 is - - port( alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0); - S_i_0 : out std_logic_vector(33 to 33); - S : out std_logic_vector(8 to 8); - alu_coef_s : out std_logic_vector(8 downto 0) - ); - -end MUXN_9_5; - -architecture DEF_ARCH of MUXN_9_5 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MUXN_9_4 - port( alu_coef_s : out std_logic_vector(8 downto 0); - S_0 : out std_logic; - S_i_0 : out std_logic_vector(33 to 33); - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : MUXN_9_4 - Use entity work.MUXN_9_4(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_4 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), S_0 => - S(8), S_i_0(33) => S_i_0(33), alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_sel_coeff(2) => alu_sel_coeff(2), alu_sel_coeff(1) - => alu_sel_coeff(1), alu_sel_coeff(0) => - alu_sel_coeff(0), alu_sel_coeff_0_2 => alu_sel_coeff_0_2, - alu_sel_coeff_0_0 => alu_sel_coeff_0_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_18 is - - port( alu_sample : in std_logic_vector(17 downto 0); - OP1_2C_D : out std_logic_vector(17 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end MAC_REG_18; - -architecture DEF_ARCH of MAC_REG_18 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[6]\ : DFN1C0 - port map(D => alu_sample(6), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(6)); - - \Q[13]\ : DFN1C0 - port map(D => alu_sample(13), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(13)); - - \Q[14]\ : DFN1C0 - port map(D => alu_sample(14), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(14)); - - \Q[15]\ : DFN1C0 - port map(D => alu_sample(15), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(15)); - - \Q[11]\ : DFN1C0 - port map(D => alu_sample(11), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(11)); - - GND_i_0 : GND - port map(Y => GND_0); - - \Q[2]\ : DFN1C0 - port map(D => alu_sample(2), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(2)); - - \Q[4]\ : DFN1C0 - port map(D => alu_sample(4), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(4)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[17]\ : DFN1C0 - port map(D => alu_sample(17), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(17)); - - \Q[10]\ : DFN1C0 - port map(D => alu_sample(10), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(10)); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[3]\ : DFN1C0 - port map(D => alu_sample(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(3)); - - \Q[7]\ : DFN1C0 - port map(D => alu_sample(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(7)); - - \Q[12]\ : DFN1C0 - port map(D => alu_sample(12), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(12)); - - \Q[8]\ : DFN1C0 - port map(D => alu_sample(8), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(8)); - - \Q[1]\ : DFN1C0 - port map(D => alu_sample(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(1)); - - \Q[0]\ : DFN1C0 - port map(D => alu_sample(0), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(0)); - - \Q[9]\ : DFN1C0 - port map(D => alu_sample(9), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(9)); - - \Q[5]\ : DFN1C0 - port map(D => alu_sample(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(5)); - - \Q[16]\ : DFN1C0 - port map(D => alu_sample(16), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(16)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_9 is - - port( alu_coef_s : in std_logic_vector(8 downto 0); - OP2_2C_D : out std_logic_vector(8 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end MAC_REG_9; - -architecture DEF_ARCH of MAC_REG_9 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[5]\ : DFN1C0 - port map(D => alu_coef_s(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(5)); - - \Q[3]\ : DFN1C0 - port map(D => alu_coef_s(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(3)); - - \Q[8]\ : DFN1C0 - port map(D => alu_coef_s(8), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(8)); - - \Q[7]\ : DFN1C0 - port map(D => alu_coef_s(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(7)); - - \Q[1]\ : DFN1C0 - port map(D => alu_coef_s(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(1)); - - \Q[2]\ : DFN1C0 - port map(D => alu_coef_s(2), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(2)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[6]\ : DFN1C0 - port map(D => alu_coef_s(6), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(6)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[0]\ : DFN1C0 - port map(D => alu_coef_s(0), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(0)); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \Q[4]\ : DFN1C0 - port map(D => alu_coef_s(4), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(4)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_4 is - - port( MACMUX2sel_D : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - MACMUX2sel_D_D : out std_logic - ); - -end MAC_REG_1_4; - -architecture DEF_ARCH of MAC_REG_1_4 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[0]\ : DFN1C0 - port map(D => MACMUX2sel_D, CLK => HCLK_c, CLR => HRESETn_c, - Q => MACMUX2sel_D_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_CONTROLER is - - port( alu_ctrl : in std_logic_vector(1 downto 0); - MACMUX2sel : out std_logic; - N_4 : out std_logic; - mult : out std_logic; - mult_0 : out std_logic - ); - -end MAC_CONTROLER; - -architecture DEF_ARCH of MAC_CONTROLER is - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_mult_i : NOR2B - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => N_4); - - GND_i_0 : GND - port map(Y => GND_0); - - un2_mult_i_x2 : XOR2 - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => mult); - - VCC_i : VCC - port map(Y => \VCC\); - - un2_mult_i_x2_0 : XOR2 - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => mult_0); - - un1_add_0_a2 : NOR2A - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => - MACMUX2sel); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_MUX is - - port( OP1_2C_D : in std_logic_vector(17 downto 0); - MULTout : in std_logic_vector(24 downto 0); - ADDERinB : out std_logic_vector(24 downto 0); - ADDERinA_i : out std_logic_vector(18 to 18); - OP2_2C_D : in std_logic_vector(8 downto 0); - ADDERout : in std_logic_vector(24 downto 0); - ADDERinA_17 : out std_logic; - ADDERinA_24 : out std_logic; - ADDERinA_23 : out std_logic; - ADDERinA_22 : out std_logic; - ADDERinA_21 : out std_logic; - ADDERinA_20 : out std_logic; - ADDERinA_19 : out std_logic; - ADDERinA_16 : out std_logic; - ADDERinA_15 : out std_logic; - ADDERinA_14 : out std_logic; - ADDERinA_13 : out std_logic; - ADDERinA_12 : out std_logic; - ADDERinA_11 : out std_logic; - ADDERinA_10 : out std_logic; - ADDERinA_9 : out std_logic; - ADDERinA_8 : out std_logic; - ADDERinA_7 : out std_logic; - ADDERinA_6 : out std_logic; - ADDERinA_5 : out std_logic; - ADDERinA_4 : out std_logic; - ADDERinA_3 : out std_logic; - ADDERinA_2 : out std_logic; - ADDERinA_1 : out std_logic; - ADDERinA_0 : out std_logic; - MACMUXsel_D : in std_logic; - MACMUXsel_D_1 : in std_logic; - MACMUXsel_D_0 : in std_logic - ); - -end MAC_MUX; - -architecture DEF_ARCH of MAC_MUX is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \OUTA[24]\ : MX2C - port map(A => ADDERout(24), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_24); - - \OUTB[3]\ : MX2 - port map(A => MULTout(3), B => OP1_2C_D(3), S => - MACMUXsel_D_1, Y => ADDERinB(3)); - - \OUTB[9]\ : MX2 - port map(A => MULTout(9), B => OP1_2C_D(9), S => - MACMUXsel_D_1, Y => ADDERinB(9)); - - \OUTA[0]\ : MX2 - port map(A => ADDERout(0), B => OP2_2C_D(0), S => - MACMUXsel_D_0, Y => ADDERinA_0); - - \OUTA[3]\ : MX2 - port map(A => ADDERout(3), B => OP2_2C_D(3), S => - MACMUXsel_D_0, Y => ADDERinA_3); - - \OUTB[11]\ : MX2 - port map(A => MULTout(11), B => OP1_2C_D(11), S => - MACMUXsel_D, Y => ADDERinB(11)); - - \OUTB[23]\ : MX2 - port map(A => MULTout(23), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(23)); - - \OUTB[12]\ : MX2 - port map(A => MULTout(12), B => OP1_2C_D(12), S => - MACMUXsel_D, Y => ADDERinB(12)); - - \OUTB[20]\ : MX2 - port map(A => MULTout(20), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(20)); - - \OUTB[19]\ : MX2 - port map(A => MULTout(19), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(19)); - - \OUTA[13]\ : MX2 - port map(A => ADDERout(13), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_13); - - \OUTB[8]\ : MX2 - port map(A => MULTout(8), B => OP1_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinB(8)); - - \OUTA[10]\ : MX2 - port map(A => ADDERout(10), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_10); - - VCC_i : VCC - port map(Y => \VCC\); - - \OUTB[6]\ : MX2 - port map(A => MULTout(6), B => OP1_2C_D(6), S => - MACMUXsel_D_1, Y => ADDERinB(6)); - - \OUTA[6]\ : MX2 - port map(A => ADDERout(6), B => OP2_2C_D(6), S => - MACMUXsel_D_0, Y => ADDERinA_6); - - \OUTB[24]\ : MX2 - port map(A => MULTout(24), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(24)); - - \OUTA[14]\ : MX2C - port map(A => ADDERout(14), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_14); - - \OUTB[2]\ : MX2 - port map(A => MULTout(2), B => OP1_2C_D(2), S => - MACMUXsel_D_1, Y => ADDERinB(2)); - - \OUTB[13]\ : MX2 - port map(A => MULTout(13), B => OP1_2C_D(13), S => - MACMUXsel_D, Y => ADDERinB(13)); - - \OUTB[10]\ : MX2 - port map(A => MULTout(10), B => OP1_2C_D(10), S => - MACMUXsel_D, Y => ADDERinB(10)); - - \OUTA[9]\ : MX2 - port map(A => ADDERout(9), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_9); - - \OUTA[15]\ : MX2C - port map(A => ADDERout(15), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_15); - - \OUTA[16]\ : MX2 - port map(A => ADDERout(16), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_16); - - \OUTA[7]\ : MX2 - port map(A => ADDERout(7), B => OP2_2C_D(7), S => - MACMUXsel_D_0, Y => ADDERinA_7); - - \OUTB[5]\ : MX2 - port map(A => MULTout(5), B => OP1_2C_D(5), S => - MACMUXsel_D_1, Y => ADDERinB(5)); - - \OUTB[14]\ : MX2 - port map(A => MULTout(14), B => OP1_2C_D(14), S => - MACMUXsel_D, Y => ADDERinB(14)); - - GND_i : GND - port map(Y => \GND\); - - \OUTA[18]\ : MX2C - port map(A => ADDERout(18), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_i(18)); - - \OUTB[4]\ : MX2 - port map(A => MULTout(4), B => OP1_2C_D(4), S => - MACMUXsel_D_1, Y => ADDERinB(4)); - - \OUTB[15]\ : MX2 - port map(A => MULTout(15), B => OP1_2C_D(15), S => - MACMUXsel_D, Y => ADDERinB(15)); - - \OUTB[16]\ : MX2 - port map(A => MULTout(16), B => OP1_2C_D(16), S => - MACMUXsel_D, Y => ADDERinB(16)); - - \OUTA[21]\ : MX2 - port map(A => ADDERout(21), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_21); - - \OUTA[22]\ : MX2C - port map(A => ADDERout(22), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_22); - - \OUTA[17]\ : MX2 - port map(A => ADDERout(17), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA_17); - - \OUTB[18]\ : MX2 - port map(A => MULTout(18), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(18)); - - \OUTA[4]\ : MX2 - port map(A => ADDERout(4), B => OP2_2C_D(4), S => - MACMUXsel_D_0, Y => ADDERinA_4); - - \OUTA[1]\ : MX2C - port map(A => ADDERout(1), B => OP2_2C_D(1), S => - MACMUXsel_D_0, Y => ADDERinA_1); - - \OUTB[7]\ : MX2 - port map(A => MULTout(7), B => OP1_2C_D(7), S => - MACMUXsel_D_1, Y => ADDERinB(7)); - - \OUTA[2]\ : MX2 - port map(A => ADDERout(2), B => OP2_2C_D(2), S => - MACMUXsel_D_0, Y => ADDERinA_2); - - \OUTA[23]\ : MX2 - port map(A => ADDERout(23), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_23); - - \OUTA[20]\ : MX2 - port map(A => ADDERout(20), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_20); - - \OUTB[17]\ : MX2 - port map(A => MULTout(17), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(17)); - - \OUTB[21]\ : MX2 - port map(A => MULTout(21), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(21)); - - \OUTA[8]\ : MX2 - port map(A => ADDERout(8), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_8); - - \OUTB[22]\ : MX2 - port map(A => MULTout(22), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(22)); - - \OUTB[0]\ : MX2 - port map(A => MULTout(0), B => OP1_2C_D(0), S => - MACMUXsel_D_1, Y => ADDERinB(0)); - - \OUTA[11]\ : MX2 - port map(A => ADDERout(11), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_11); - - \OUTB[1]\ : MX2 - port map(A => MULTout(1), B => OP1_2C_D(1), S => - MACMUXsel_D_1, Y => ADDERinB(1)); - - \OUTA[5]\ : MX2 - port map(A => ADDERout(5), B => OP2_2C_D(5), S => - MACMUXsel_D_0, Y => ADDERinA_5); - - \OUTA[12]\ : MX2 - port map(A => ADDERout(12), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \OUTA[19]\ : MX2 - port map(A => ADDERout(19), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_19); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_27 is - - port( MULTout : in std_logic_vector(24 downto 7); - MULTout_D : out std_logic_vector(24 downto 7); - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end MAC_REG_27; - -architecture DEF_ARCH of MAC_REG_27 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[24]\ : DFN1C0 - port map(D => MULTout(24), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(24)); - - \Q[21]\ : DFN1C0 - port map(D => MULTout(21), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(21)); - - \Q[13]\ : DFN1C0 - port map(D => MULTout(13), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(13)); - - \Q[14]\ : DFN1C0 - port map(D => MULTout(14), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(14)); - - \Q[15]\ : DFN1C0 - port map(D => MULTout(15), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(15)); - - \Q[11]\ : DFN1C0 - port map(D => MULTout(11), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(11)); - - GND_i_0 : GND - port map(Y => GND_0); - - \Q[20]\ : DFN1C0 - port map(D => MULTout(20), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(20)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[17]\ : DFN1C0 - port map(D => MULTout(17), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(17)); - - \Q[10]\ : DFN1C0 - port map(D => MULTout(10), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(10)); - - \Q[19]\ : DFN1C0 - port map(D => MULTout(19), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(19)); - - GND_i : GND - port map(Y => \GND\); - - \Q[18]\ : DFN1C0 - port map(D => MULTout(18), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(18)); - - \Q[22]\ : DFN1C0 - port map(D => MULTout(22), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(22)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[7]\ : DFN1C0 - port map(D => MULTout(7), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(7)); - - \Q[12]\ : DFN1C0 - port map(D => MULTout(12), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(12)); - - \Q[8]\ : DFN1C0 - port map(D => MULTout(8), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(8)); - - \Q[9]\ : DFN1C0 - port map(D => MULTout(9), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(9)); - - \Q[23]\ : DFN1C0 - port map(D => MULTout(23), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(23)); - - \Q[16]\ : DFN1C0 - port map(D => MULTout(16), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(16)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_1 is - - port( alu_ctrl : in std_logic_vector(0 to 0); - add_D : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - add_D_0 : out std_logic - ); - -end MAC_REG_1_1; - -architecture DEF_ARCH of MAC_REG_1_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_0[0]\ : DFN1C0 - port map(D => alu_ctrl(0), CLK => HCLK_c, CLR => HRESETn_c, - Q => add_D_0); - - \Q[0]\ : DFN1C0 - port map(D => alu_ctrl(0), CLK => HCLK_c, CLR => HRESETn_c, - Q => add_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_3 is - - port( MACMUX2sel : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - MACMUX2sel_D : out std_logic - ); - -end MAC_REG_1_3; - -architecture DEF_ARCH of MAC_REG_1_3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[0]\ : DFN1C0 - port map(D => MACMUX2sel, CLK => HCLK_c, CLR => HRESETn_c, - Q => MACMUX2sel_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1 is - - port( alu_ctrl : in std_logic_vector(2 to 2); - clr_MAC_D : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - clr_MAC_D_0 : out std_logic - ); - -end MAC_REG_1; - -architecture DEF_ARCH of MAC_REG_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_0[0]\ : DFN1C0 - port map(D => alu_ctrl(2), CLK => HCLK_c, CLR => HRESETn_c, - Q => clr_MAC_D_0); - - \Q[0]\ : DFN1C0 - port map(D => alu_ctrl(2), CLK => HCLK_c, CLR => HRESETn_c, - Q => clr_MAC_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Adder is - - port( ADDERout : out std_logic_vector(24 downto 0); - ADDERinA_i : in std_logic_vector(18 to 18); - ADDERinB : in std_logic_vector(24 downto 0); - ADDERinA_0 : in std_logic; - ADDERinA_1 : in std_logic; - ADDERinA_3 : in std_logic; - ADDERinA_5 : in std_logic; - ADDERinA_7 : in std_logic; - ADDERinA_8 : in std_logic; - ADDERinA_15 : in std_logic; - ADDERinA_16 : in std_logic; - ADDERinA_2 : in std_logic; - ADDERinA_14 : in std_logic; - ADDERinA_6 : in std_logic; - ADDERinA_10 : in std_logic; - ADDERinA_4 : in std_logic; - ADDERinA_12 : in std_logic; - ADDERinA_20 : in std_logic; - ADDERinA_11 : in std_logic; - ADDERinA_19 : in std_logic; - ADDERinA_9 : in std_logic; - ADDERinA_13 : in std_logic; - ADDERinA_21 : in std_logic; - ADDERinA_22 : in std_logic; - ADDERinA_24 : in std_logic; - ADDERinA_23 : in std_logic; - ADDERinA_17 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - clr_MAC_D : in std_logic; - add_D : in std_logic; - clr_MAC_D_0 : in std_logic; - MACMUX2sel_D : in std_logic; - add_D_0 : in std_logic - ); - -end Adder; - -architecture DEF_ARCH of Adder is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_clr_1_0\, ADD_27x27_fast_I247_Y_0_0, - ADD_27x27_fast_I253_Y_0_0, ADD_27x27_fast_I254_Y_0_0, - ADD_27x27_fast_I208_Y_3, N534, N519, - ADD_27x27_fast_I208_Y_2, N472, N465, - ADD_27x27_fast_I208_Y_1, N415, N412, - ADD_27x27_fast_I208_Y_0, N388, ADD_27x27_fast_I251_Y_0_0, - ADD_27x27_fast_I207_Y_3, N532, N517, - ADD_27x27_fast_I207_Y_2, N470, N463, - ADD_27x27_fast_I207_Y_1, N413, N410, - ADD_27x27_fast_I207_Y_0, N391, ADD_27x27_fast_I243_Y_0_0, - ADD_27x27_fast_I239_Y_0_0, ADD_27x27_fast_I249_Y_0_0, - ADD_27x27_fast_I196_Y_0_0, N496, N_73, N439, - ADD_27x27_fast_I241_Y_0_0, ADD_27x27_fast_I250_Y_0_0, - ADD_27x27_fast_I242_Y_0_0, ADD_27x27_fast_I252_Y_0_0, - ADD_27x27_fast_I212_Y_1, N542, N527, - ADD_27x27_fast_I212_Y_0, N480, N473, - ADD_27x27_fast_I164_Y_i_0, N_58, - ADD_27x27_fast_I248_Y_0_0, ADD_27x27_fast_I211_Y_1, N540, - N525, ADD_27x27_fast_I211_Y_0, N478, N471, - ADD_27x27_fast_I209_Y_2, N536, N521, - ADD_27x27_fast_I209_Y_1, N474, N467, - ADD_27x27_fast_I209_Y_0, N417, N414, - ADD_27x27_fast_I240_Y_0_0, ADD_27x27_fast_I213_Y_1, - ADD_27x27_fast_I213_un1_Y_0, N529, - ADD_27x27_fast_I213_Y_0, N475, N482, - ADD_27x27_fast_I236_Y_0_0, N499, N_47, N491, - ADD_27x27_fast_I99_Y_0, N364, ADD_27x27_fast_I91_Y_0, - N376, ADD_27x27_fast_I107_Y_0, N352, - ADD_27x27_fast_I115_Y_0, N340, - ADD_27x27_fast_I115_un1_Y_0, N_108, - ADD_27x27_fast_I116_Y_0, ADD_27x27_fast_I100_Y_0, N362, - I207_un1_Y, N533, N548, I209_un1_Y, N537, N552, - I211_un1_Y, N541, N502, N431, N428, N481, N488, N436, - N444, N497, I208_un1_Y, N535, N550, I212_un1_Y, N543, - N_48, N_33, \un1_clr_1\, \un2_resadd[24]\, - \un2_resadd[23]\, \un2_resadd[22]\, \un2_resadd[21]\, - ADD_27x27_fast_I210_Y_0_a2, \un2_resadd[20]\, - \un2_resadd[19]\, \un2_resadd[18]\, I185_un1_Y, - \un2_resadd[16]\, N648_i, \un2_resadd[15]\, N651, - \un2_resadd[14]\, N654_i, \un2_resadd[13]\, - ADD_27x27_fast_I192_Y_0_a2, N361, \un2_resadd[12]\, - I193_un1_Y, \un2_resadd[11]\, I194_un1_Y_i, - \un2_resadd[10]\, N544, I195_un1_Y_i, \un2_resadd[9]\, - N_78_i, \un2_resadd[8]\, \un2_resadd[7]\, \un2_resadd[6]\, - \un2_resadd[5]\, \un2_resadd[4]\, \un2_resadd[3]\, - \un2_resadd[2]\, \un2_resadd[1]\, N325, \un2_resadd[17]\, - N423, N_98_i, N420, N392, N355, N356, N379, N380, N385, - N386, N429, N437, N349, N441, N343, N445, N_52_i_0, N449, - N_72, N450, N418, N433, N430, N483, N434, N490, N438, - N442, N494, N498, N446, N487, N479, N495, I163_un1_Y, - N383, N350, N344, N341, N486, N346, N382, N367, N368, - N_105_1, N489, I190_un1_Y, N_59, N_50, N_9, N_11, N_16, - N_18, N_23, N_30, N_32, \REG_4[1]\, \REG_4[3]\, - \REG_4[8]\, \REG_4[10]\, \REG_4[15]\, \REG_4[22]\, - \REG_4[24]\, N_8, N_12, N_15, N_19, N_22, N_26, N_29, - \REG_4[0]\, \REG_4[4]\, \REG_4[7]\, \REG_4[11]\, - \REG_4[14]\, \REG_4[18]\, \REG_4[21]\, N_10, N_13, N_14, - N_17, N_20, N_21, N_24, N_27, N_28, N_31, \REG_4[2]\, - \REG_4[5]\, \REG_4[6]\, \REG_4[9]\, \REG_4[12]\, - \REG_4[13]\, \REG_4[16]\, \REG_4[19]\, \REG_4[20]\, - \REG_4[23]\, N_23_0, \REG_4[17]\, N_25, N374, N370, N373, - N371, N426, N422, N421, N425, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - un2_resadd_ADD_27x27_fast_I8_G0N : NOR2B - port map(A => ADDERinB(8), B => ADDERinA_8, Y => N349); - - un2_resadd_ADD_27x27_fast_I241_Y_0_0 : XOR2 - port map(A => ADDERinA_11, B => ADDERinB(11), Y => - ADD_27x27_fast_I241_Y_0_0); - - un2_resadd_ADD_27x27_fast_I134_Y : NOR2 - port map(A => N475, B => N467, Y => N521); - - un2_resadd_ADD_27x27_fast_I208_Y_1 : AOI1B - port map(A => N415, B => N412, C => ADD_27x27_fast_I208_Y_0, - Y => ADD_27x27_fast_I208_Y_1); - - un2_resadd_ADD_27x27_fast_I156_Y : NOR2A - port map(A => N497, B => N489, Y => N543); - - un2_resadd_ADD_27x27_fast_I19_P0N : OR2 - port map(A => ADDERinB(19), B => ADDERinA_19, Y => N383); - - un2_resadd_ADD_27x27_fast_I21_G0N : NOR2B - port map(A => ADDERinB(21), B => ADDERinA_21, Y => N388); - - \REG[14]\ : DFN1E0C0 - port map(D => \REG_4[14]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(14)); - - un2_resadd_ADD_27x27_fast_I214_Y_0_a2 : OR2A - port map(A => N651, B => N_23_0, Y => N_98_i); - - un2_resadd_ADD_27x27_fast_I12_G0N : OR2B - port map(A => ADDERinB(12), B => ADDERinA_12, Y => N361); - - un2_resadd_ADD_27x27_fast_I99_Y : AOI1 - port map(A => N431, B => N428, C => ADD_27x27_fast_I99_Y_0, - Y => N480); - - un2_resadd_ADD_27x27_fast_I149_Y : AO1A - port map(A => N483, B => N490, C => N482, Y => N536); - - un2_resadd_ADD_27x27_fast_I68_Y : OA1 - port map(A => ADDERinA_4, B => ADDERinB(4), C => N341, Y - => N446); - - un2_resadd_ADD_27x27_fast_I5_P0N : OR2 - port map(A => ADDERinB(5), B => ADDERinA_5, Y => N341); - - un2_resadd_ADD_27x27_fast_I11_G0N_0_o2 : OR2B - port map(A => ADDERinB(11), B => ADDERinA_11, Y => N_50); - - un2_resadd_ADD_27x27_fast_I209_Y_0 : AOI1 - port map(A => N417, B => N414, C => N413, Y => - ADD_27x27_fast_I209_Y_0); - - un2_resadd_ADD_27x27_fast_I132_Y : NOR2 - port map(A => N473, B => N465, Y => N519); - - un2_resadd_ADD_27x27_fast_I122_Y_i_o2 : MAJ3 - port map(A => ADDERinA_2, B => ADDERinB(2), C => N_47, Y - => N_48); - - un2_resadd_ADD_27x27_fast_I93_Y : AO1 - port map(A => N425, B => N422, C => N421, Y => N474); - - un2_resadd_ADD_27x27_fast_I52_Y : OA1 - port map(A => ADDERinA_13, B => ADDERinB(13), C => N362, Y - => N430); - - un2_resadd_ADD_27x27_fast_I254_Y_0 : AX1C - port map(A => I207_un1_Y, B => ADD_27x27_fast_I207_Y_3, C - => ADD_27x27_fast_I254_Y_0_0, Y => \un2_resadd[24]\); - - \REG_RNO[11]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_19, Y => \REG_4[11]\); - - \REG[22]\ : DFN1E0C0 - port map(D => \REG_4[22]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(22)); - - un2_resadd_ADD_27x27_fast_I51_Y : AO13 - port map(A => ADDERinB(13), B => ADDERinA_13, C => N361, Y - => N429); - - \REG_RNO[20]\ : NOR2 - port map(A => clr_MAC_D, B => N_28, Y => \REG_4[20]\); - - \REG_RNO[15]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_23, Y => \REG_4[15]\); - - \REG_RNO_0[17]\ : MX2C - port map(A => ADDERinB(17), B => \un2_resadd[17]\, S => - add_D, Y => N_25); - - un2_resadd_ADD_27x27_fast_I196_Y_0_a2 : OR3B - port map(A => N497, B => N_48, C => N_73, Y => N_78_i); - - un2_resadd_ADD_27x27_fast_I240_Y_0_0 : XOR2 - port map(A => ADDERinA_10, B => ADDERinB(10), Y => - ADD_27x27_fast_I240_Y_0_0); - - un2_resadd_ADD_27x27_fast_I6_G0N : NOR2B - port map(A => ADDERinB(6), B => ADDERinA_6, Y => N343); - - un2_resadd_ADD_27x27_fast_I163_Y : OR2 - port map(A => N498, B => I163_un1_Y, Y => N552); - - un2_resadd_ADD_27x27_fast_I90_Y : OR2B - port map(A => N422, B => N418, Y => N471); - - un2_resadd_ADD_27x27_fast_I35_Y : MAJ3 - port map(A => ADDERinA_21, B => ADDERinB(21), C => N385, Y - => N413); - - un2_resadd_ADD_27x27_fast_I48_Y : NOR2B - port map(A => N371, B => N368, Y => N426); - - \REG_RNO[9]\ : NOR2 - port map(A => clr_MAC_D, B => N_17, Y => \REG_4[9]\); - - \REG_RNO_0[8]\ : MX2C - port map(A => ADDERinB(8), B => \un2_resadd[8]\, S => - add_D_0, Y => N_16); - - \REG[11]\ : DFN1E0C0 - port map(D => \REG_4[11]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(11)); - - un2_resadd_ADD_27x27_fast_I99_Y_0 : AO18 - port map(A => N364, B => ADDERinB(14), C => ADDERinA_14, Y - => ADD_27x27_fast_I99_Y_0); - - un2_resadd_ADD_27x27_fast_I6_P0N : OR2 - port map(A => ADDERinB(6), B => ADDERinA_6, Y => N344); - - un2_resadd_ADD_27x27_fast_I15_G0N : NOR2A - port map(A => ADDERinB(15), B => ADDERinA_15, Y => N370); - - un2_resadd_ADD_27x27_fast_I207_Y_1 : AOI1B - port map(A => N413, B => N410, C => ADD_27x27_fast_I207_Y_0, - Y => ADD_27x27_fast_I207_Y_1); - - un2_resadd_ADD_27x27_fast_I207_Y_0 : MIN3 - port map(A => ADDERinA_23, B => ADDERinB(23), C => N391, Y - => ADD_27x27_fast_I207_Y_0); - - un2_resadd_ADD_27x27_fast_I116_Y : NOR2B - port map(A => ADD_27x27_fast_I116_Y_0, B => N444, Y => N497); - - un2_resadd_ADD_27x27_fast_I242_Y_0_0 : XOR2 - port map(A => ADDERinA_12, B => ADDERinB(12), Y => - ADD_27x27_fast_I242_Y_0_0); - - un2_resadd_ADD_27x27_fast_I163_un1_Y : NOR2B - port map(A => N_47, B => N499, Y => I163_un1_Y); - - un2_resadd_ADD_27x27_fast_I238_Y_0 : XOR3 - port map(A => ADDERinB(8), B => ADDERinA_8, C => N548, Y - => \un2_resadd[8]\); - - \REG_RNO[4]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_12, Y => \REG_4[4]\); - - \REG_RNO[12]\ : NOR2 - port map(A => clr_MAC_D, B => N_20, Y => \REG_4[12]\); - - un2_resadd_ADD_27x27_fast_I140_Y : NOR2 - port map(A => N481, B => N473, Y => N527); - - un2_resadd_ADD_27x27_fast_I248_Y_0 : AX1B - port map(A => I185_un1_Y, B => ADD_27x27_fast_I213_Y_1, C - => ADD_27x27_fast_I248_Y_0_0, Y => \un2_resadd[18]\); - - \REG_RNO_0[11]\ : MX2C - port map(A => ADDERinB(11), B => \un2_resadd[11]\, S => - add_D_0, Y => N_19); - - un2_resadd_ADD_27x27_fast_I66_Y : NOR2B - port map(A => N344, B => N341, Y => N444); - - un2_resadd_ADD_27x27_fast_I247_Y_0_0 : XOR2 - port map(A => ADDERinA_17, B => ADDERinB(17), Y => - ADD_27x27_fast_I247_Y_0_0); - - un2_resadd_ADD_27x27_fast_I162_Y : AO1 - port map(A => N_48, B => N497, C => N496, Y => N550); - - un2_resadd_ADD_27x27_fast_I36_Y : OA1 - port map(A => ADDERinA_21, B => ADDERinB(21), C => N386, Y - => N414); - - un2_resadd_ADD_27x27_fast_I209_Y_2 : AOI1B - port map(A => N536, B => N521, C => ADD_27x27_fast_I209_Y_1, - Y => ADD_27x27_fast_I209_Y_2); - - un2_resadd_ADD_27x27_fast_I236_Y_0_0 : XOR2 - port map(A => ADDERinA_6, B => ADDERinB(6), Y => - ADD_27x27_fast_I236_Y_0_0); - - un2_resadd_ADD_27x27_fast_I212_Y_1 : AO1 - port map(A => N542, B => N527, C => ADD_27x27_fast_I212_Y_0, - Y => ADD_27x27_fast_I212_Y_1); - - un2_resadd_ADD_27x27_fast_I19_G0N : NOR2B - port map(A => ADDERinB(19), B => ADDERinA_19, Y => N382); - - \REG_RNO_0[10]\ : MX2C - port map(A => ADDERinB(10), B => \un2_resadd[10]\, S => - add_D_0, Y => N_18); - - \REG[12]\ : DFN1E0C0 - port map(D => \REG_4[12]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(12)); - - un2_resadd_ADD_27x27_fast_I84_Y : OR2B - port map(A => N_105_1, B => N412, Y => N465); - - un2_resadd_ADD_27x27_fast_I107_Y_0 : MIN3 - port map(A => ADDERinA_10, B => ADDERinB(10), C => N352, Y - => ADD_27x27_fast_I107_Y_0); - - un2_resadd_ADD_27x27_fast_I185_un1_Y : NOR2B - port map(A => N544, B => N529, Y => I185_un1_Y); - - un2_resadd_ADD_27x27_fast_I115_un1_Y_0 : OA1B - port map(A => ADDERinA_4, B => ADDERinB(4), C => N_108, Y - => ADD_27x27_fast_I115_un1_Y_0); - - un2_resadd_ADD_27x27_fast_I207_Y_2 : OA1A - port map(A => N470, B => N463, C => ADD_27x27_fast_I207_Y_1, - Y => ADD_27x27_fast_I207_Y_2); - - un2_resadd_ADD_27x27_fast_I118_Y : NOR2B - port map(A => N450, B => N446, Y => N499); - - un2_resadd_ADD_27x27_fast_I207_Y_3 : AOI1B - port map(A => N532, B => N517, C => ADD_27x27_fast_I207_Y_2, - Y => ADD_27x27_fast_I207_Y_3); - - GND_i : GND - port map(Y => \GND\); - - \REG_RNO_0[21]\ : MX2C - port map(A => ADDERinB(21), B => \un2_resadd[21]\, S => - add_D, Y => N_29); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un2_resadd_ADD_27x27_fast_I63_Y : MAJ3 - port map(A => ADDERinA_7, B => ADDERinB(7), C => N343, Y - => N441); - - un2_resadd_ADD_27x27_fast_I236_Y_0 : XOR2 - port map(A => ADD_27x27_fast_I236_Y_0_0, B => N552, Y => - \un2_resadd[6]\); - - un2_resadd_ADD_27x27_fast_I45_Y_0_o2 : AO1 - port map(A => N374, B => N370, C => N373, Y => N423); - - un2_resadd_ADD_27x27_fast_I10_G0N : NOR2B - port map(A => ADDERinB(10), B => ADDERinA_10, Y => N355); - - un2_resadd_ADD_27x27_fast_I246_Y_0 : XNOR3 - port map(A => ADDERinB(16), B => ADDERinA_16, C => N648_i, - Y => \un2_resadd[16]\); - - \REG_RNO[14]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_22, Y => \REG_4[14]\); - - un2_resadd_ADD_27x27_fast_I92_Y : OR2A - port map(A => N420, B => N_23_0, Y => N473); - - un2_resadd_ADD_27x27_fast_I39_Y : MAJ3 - port map(A => ADDERinA_19, B => ADDERinB(19), C => N379, Y - => N417); - - un2_resadd_ADD_27x27_fast_I150_Y : NOR2 - port map(A => N491, B => N483, Y => N537); - - un2_resadd_ADD_27x27_fast_I235_Y_0 : XNOR3 - port map(A => ADDERinB(5), B => ADDERinA_5, C => N_33, Y - => \un2_resadd[5]\); - - un2_resadd_ADD_27x27_fast_I164_Y_i_0 : MAJ3 - port map(A => ADDERinA_4, B => ADDERinB(4), C => N_58, Y - => ADD_27x27_fast_I164_Y_i_0); - - un2_resadd_ADD_27x27_fast_I212_Y_0 : AO1D - port map(A => N480, B => N473, C => N472, Y => - ADD_27x27_fast_I212_Y_0); - - un2_resadd_ADD_27x27_fast_I196_Y_0_0 : OA1C - port map(A => N496, B => N_73, C => N439, Y => - ADD_27x27_fast_I196_Y_0_0); - - un2_resadd_ADD_27x27_fast_I245_Y_0 : XNOR3 - port map(A => ADDERinB(15), B => ADDERinA_15, C => N651, Y - => \un2_resadd[15]\); - - \REG[0]\ : DFN1E0C0 - port map(D => \REG_4[0]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(0)); - - \REG_RNO[7]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_15, Y => \REG_4[7]\); - - un2_resadd_ADD_27x27_fast_I9_G0N : NOR2B - port map(A => ADDERinB(9), B => ADDERinA_9, Y => N352); - - un2_resadd_ADD_27x27_fast_I91_Y : AO1 - port map(A => N423, B => N420, C => ADD_27x27_fast_I91_Y_0, - Y => N472); - - \REG_RNO_0[20]\ : MX2C - port map(A => ADDERinB(20), B => \un2_resadd[20]\, S => - add_D, Y => N_28); - - un2_resadd_ADD_27x27_fast_I212_un1_Y : NOR3C - port map(A => N543, B => N527, C => N_48, Y => I212_un1_Y); - - un2_resadd_ADD_27x27_fast_I106_Y : OR2B - port map(A => N438, B => N434, Y => N487); - - un2_resadd_ADD_27x27_fast_I3_G0N_i_o2 : NOR2B - port map(A => ADDERinB(3), B => ADDERinA_3, Y => N_59); - - un2_resadd_ADD_27x27_fast_I60_Y : OA1 - port map(A => ADDERinA_9, B => ADDERinB(9), C => N350, Y - => N438); - - \REG[23]\ : DFN1E0C0 - port map(D => \REG_4[23]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(23)); - - un2_resadd_ADD_27x27_fast_I208_Y_0 : AO18 - port map(A => N388, B => ADDERinA_22, C => ADDERinB(22), Y - => ADD_27x27_fast_I208_Y_0); - - \REG_RNO[1]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_9, Y => \REG_4[1]\); - - un2_resadd_ADD_27x27_fast_I43_Y : MAJ3 - port map(A => ADDERinA_17, B => ADDERinB(17), C => N373, Y - => N421); - - un2_resadd_ADD_27x27_fast_I190_un1_Y : NOR2B - port map(A => N550, B => N535, Y => I190_un1_Y); - - un2_resadd_ADD_27x27_fast_I20_P0N : OR2 - port map(A => ADDERinB(20), B => ADDERinA_20, Y => N386); - - un2_resadd_ADD_27x27_fast_I208_Y_2 : OA1A - port map(A => N472, B => N465, C => ADD_27x27_fast_I208_Y_1, - Y => ADD_27x27_fast_I208_Y_2); - - un2_resadd_ADD_27x27_fast_I101_Y : AO1 - port map(A => N433, B => N430, C => N429, Y => N482); - - \REG_RNO[21]\ : NOR2 - port map(A => clr_MAC_D, B => N_29, Y => \REG_4[21]\); - - un2_resadd_ADD_27x27_fast_I16_G0N : NOR2B - port map(A => ADDERinB(16), B => ADDERinA_16, Y => N373); - - VCC_i : VCC - port map(Y => \VCC\); - - un2_resadd_ADD_27x27_fast_I91_Y_0 : AO13 - port map(A => N376, B => ADDERinB(18), C => ADDERinA_i(18), - Y => ADD_27x27_fast_I91_Y_0); - - un2_resadd_ADD_27x27_fast_I211_Y_0 : OA1C - port map(A => N478, B => N471, C => N470, Y => - ADD_27x27_fast_I211_Y_0); - - un2_resadd_ADD_27x27_fast_I97_Y : AO1 - port map(A => N429, B => N426, C => N425, Y => N478); - - un2_resadd_ADD_27x27_fast_I40_Y : NOR2B - port map(A => N383, B => N380, Y => N418); - - un2_resadd_ADD_27x27_fast_I2_G0N_i_o2 : OR2B - port map(A => ADDERinB(2), B => ADDERinA_2, Y => N_72); - - \REG_RNO[13]\ : NOR2 - port map(A => clr_MAC_D, B => N_21, Y => \REG_4[13]\); - - un2_resadd_ADD_27x27_fast_I145_Y : AO1A - port map(A => N479, B => N486, C => N478, Y => N532); - - un2_resadd_ADD_27x27_fast_I108_Y : OR2A - port map(A => N436, B => N_73, Y => N489); - - \REG_RNO_0[19]\ : MX2C - port map(A => ADDERinB(19), B => \un2_resadd[19]\, S => - add_D, Y => N_27); - - un2_resadd_ADD_27x27_fast_I110_Y : OR2B - port map(A => N442, B => N438, Y => N491); - - \REG_RNO_0[6]\ : MX2C - port map(A => ADDERinB(6), B => \un2_resadd[6]\, S => add_D, - Y => N_14); - - un2_resadd_ADD_27x27_fast_I22_P0N : OR2A - port map(A => ADDERinA_22, B => ADDERinB(22), Y => N392); - - un2_resadd_ADD_27x27_fast_I213_Y_1 : AO1 - port map(A => ADD_27x27_fast_I213_un1_Y_0, B => N529, C => - ADD_27x27_fast_I213_Y_0, Y => ADD_27x27_fast_I213_Y_1); - - un2_resadd_ADD_27x27_fast_I72_Y : OA1 - port map(A => ADDERinA_2, B => ADDERinB(2), C => N_58, Y - => N450); - - un2_resadd_ADD_27x27_fast_I116_Y_0 : OA1 - port map(A => ADDERinA_4, B => ADDERinB(4), C => N_58, Y - => ADD_27x27_fast_I116_Y_0); - - un2_resadd_ADD_27x27_fast_I109_Y : AO1 - port map(A => N441, B => N438, C => N437, Y => N490); - - \REG[9]\ : DFN1E0C0 - port map(D => \REG_4[9]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(9)); - - un1_clr_1_0 : NOR3 - port map(A => add_D_0, B => MACMUX2sel_D, C => clr_MAC_D_0, - Y => \un1_clr_1_0\); - - un2_resadd_ADD_27x27_fast_I142_Y : NOR2 - port map(A => N483, B => N475, Y => N529); - - \REG_RNO_0[9]\ : MX2C - port map(A => ADDERinB(9), B => \un2_resadd[9]\, S => add_D, - Y => N_17); - - un2_resadd_ADD_27x27_fast_I71_Y : AO13 - port map(A => ADDERinB(3), B => ADDERinA_3, C => N_72, Y - => N449); - - \REG_RNO[22]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_30, Y => \REG_4[22]\); - - \REG[5]\ : DFN1E0C0 - port map(D => \REG_4[5]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(5)); - - un2_resadd_ADD_27x27_fast_I210_Y_0_a2 : OA1 - port map(A => I212_un1_Y, B => ADD_27x27_fast_I212_Y_1, C - => N_105_1, Y => ADD_27x27_fast_I210_Y_0_a2); - - \REG_RNO[2]\ : NOR2 - port map(A => clr_MAC_D, B => N_10, Y => \REG_4[2]\); - - \REG[13]\ : DFN1E0C0 - port map(D => \REG_4[13]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(13)); - - un2_resadd_ADD_27x27_fast_I153_Y : AO1A - port map(A => N487, B => N494, C => N486, Y => N540); - - un2_resadd_ADD_27x27_fast_I232_Y_0 : XOR3 - port map(A => ADDERinB(2), B => ADDERinA_2, C => N_47, Y - => \un2_resadd[2]\); - - un2_resadd_ADD_27x27_fast_I100_Y_0 : OA1 - port map(A => ADDERinA_11, B => ADDERinB(11), C => N362, Y - => ADD_27x27_fast_I100_Y_0); - - \REG[6]\ : DFN1E0C0 - port map(D => \REG_4[6]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(6)); - - \REG[18]\ : DFN1E0C0 - port map(D => \REG_4[18]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(18)); - - un2_resadd_ADD_27x27_fast_I8_P0N : OR2 - port map(A => ADDERinB(8), B => ADDERinA_8, Y => N350); - - un2_resadd_ADD_27x27_fast_I14_G0N : NOR2A - port map(A => ADDERinB(14), B => ADDERinA_14, Y => N367); - - un2_resadd_ADD_27x27_fast_I242_Y_0 : AX1D - port map(A => I193_un1_Y, B => N540, C => - ADD_27x27_fast_I242_Y_0_0, Y => \un2_resadd[12]\); - - un2_resadd_ADD_27x27_fast_I211_un1_Y : OR3C - port map(A => N525, B => N541, C => N502, Y => I211_un1_Y); - - un2_resadd_ADD_27x27_fast_I46_Y_i : OR2B - port map(A => N374, B => N371, Y => N_23_0); - - un2_resadd_ADD_27x27_fast_I239_Y_0_0 : XOR2 - port map(A => ADDERinA_9, B => ADDERinB(9), Y => - ADD_27x27_fast_I239_Y_0_0); - - un2_resadd_ADD_27x27_fast_I155_Y : AO1A - port map(A => N489, B => N496, C => N488, Y => N542); - - un2_resadd_ADD_27x27_fast_I191_Y : AOI1 - port map(A => N552, B => N537, C => N536, Y => N654_i); - - \REG_RNO_0[13]\ : MX2C - port map(A => ADDERinB(13), B => \un2_resadd[13]\, S => - add_D, Y => N_21); - - un2_resadd_ADD_27x27_fast_I249_Y_0_0 : XOR2 - port map(A => ADDERinA_19, B => ADDERinB(19), Y => - ADD_27x27_fast_I249_Y_0_0); - - \REG_RNO_0[18]\ : MX2C - port map(A => ADDERinB(18), B => \un2_resadd[18]\, S => - add_D, Y => N_26); - - \REG_RNO[18]\ : NOR2 - port map(A => clr_MAC_D, B => N_26, Y => \REG_4[18]\); - - \REG[19]\ : DFN1E0C0 - port map(D => \REG_4[19]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(19)); - - un2_resadd_ADD_27x27_fast_I32_Y : OA1 - port map(A => ADDERinA_23, B => ADDERinB(23), C => N392, Y - => N410); - - un2_resadd_ADD_27x27_fast_I53_Y_0 : AO1C - port map(A => N_50, B => N362, C => N361, Y => N431); - - un2_resadd_ADD_27x27_fast_I209_un1_Y : OR3C - port map(A => N537, B => N521, C => N552, Y => I209_un1_Y); - - un2_resadd_ADD_27x27_fast_I147_Y : AO1C - port map(A => N481, B => N488, C => N480, Y => N534); - - un2_resadd_ADD_27x27_fast_I253_Y_0_0 : XOR2 - port map(A => ADDERinA_23, B => ADDERinB(23), Y => - ADD_27x27_fast_I253_Y_0_0); - - un2_resadd_ADD_27x27_fast_I7_G0N : NOR2B - port map(A => ADDERinB(7), B => ADDERinA_7, Y => N346); - - un2_resadd_ADD_27x27_fast_I5_G0N : NOR2B - port map(A => ADDERinB(5), B => ADDERinA_5, Y => N340); - - un2_resadd_ADD_27x27_fast_I138_Y : NOR2 - port map(A => N479, B => N471, Y => N525); - - un2_resadd_ADD_27x27_fast_I154_Y : NOR2A - port map(A => N495, B => N487, Y => N541); - - un2_resadd_ADD_27x27_fast_I37_Y_0_o2 : AO1 - port map(A => N386, B => N382, C => N385, Y => N415); - - \REG_RNO[19]\ : NOR2 - port map(A => clr_MAC_D, B => N_27, Y => \REG_4[19]\); - - un2_resadd_ADD_27x27_fast_I58_Y : OA1 - port map(A => ADDERinA_9, B => ADDERinB(9), C => N356, Y - => N436); - - \REG_RNO_0[1]\ : MX2C - port map(A => ADDERinB(1), B => \un2_resadd[1]\, S => - add_D_0, Y => N_9); - - un2_resadd_ADD_27x27_fast_I94_Y : OR2B - port map(A => N426, B => N422, Y => N475); - - un2_resadd_ADD_27x27_fast_I42_Y : OA1 - port map(A => ADDERinA_17, B => ADDERinB(17), C => N380, Y - => N420); - - un2_resadd_ADD_27x27_fast_I86_Y : OR2B - port map(A => N418, B => N414, Y => N467); - - un2_resadd_ADD_27x27_fast_I75_Y_i_o2 : AO18 - port map(A => ADDERinA_1, B => ADDERinB(1), C => N325, Y - => N_47); - - un2_resadd_ADD_27x27_fast_I231_Y_0 : XOR3 - port map(A => ADDERinB(1), B => ADDERinA_1, C => N325, Y - => \un2_resadd[1]\); - - \REG[1]\ : DFN1E0C0 - port map(D => \REG_4[1]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(1)); - - un2_resadd_ADD_27x27_fast_I241_Y_0 : AX1A - port map(A => N542, B => I194_un1_Y_i, C => - ADD_27x27_fast_I241_Y_0_0, Y => \un2_resadd[11]\); - - un2_resadd_ADD_27x27_fast_I17_G0N : NOR2B - port map(A => ADDERinB(17), B => ADDERinA_17, Y => N376); - - un2_resadd_ADD_27x27_fast_I100_Y : OR2B - port map(A => ADD_27x27_fast_I100_Y_0, B => N428, Y => N481); - - \REG_RNO[24]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_32, Y => \REG_4[24]\); - - un2_resadd_ADD_27x27_fast_I55_Y : MAJ3 - port map(A => ADDERinA_11, B => ADDERinB(11), C => N355, Y - => N433); - - un2_resadd_ADD_27x27_fast_I193_un1_Y : NOR2B - port map(A => N541, B => N502, Y => I193_un1_Y); - - un2_resadd_ADD_27x27_fast_I164_Y_i : AO1C - port map(A => N_48, B => N_108, C => - ADD_27x27_fast_I164_Y_i_0, Y => N_33); - - \REG[20]\ : DFN1E0C0 - port map(D => \REG_4[20]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(20)); - - un2_resadd_ADD_27x27_fast_I252_Y_0 : AX1C - port map(A => I209_un1_Y, B => ADD_27x27_fast_I209_Y_2, C - => ADD_27x27_fast_I252_Y_0_0, Y => \un2_resadd[22]\); - - \REG_RNO[8]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_16, Y => \REG_4[8]\); - - \REG_RNO_0[7]\ : MX2C - port map(A => ADDERinB(7), B => \un2_resadd[7]\, S => - add_D_0, Y => N_15); - - un2_resadd_ADD_27x27_fast_I67_Y : MAJ3 - port map(A => ADDERinA_5, B => ADDERinB(5), C => N_52_i_0, - Y => N445); - - \REG_RNO_0[23]\ : MX2C - port map(A => ADDERinB(23), B => \un2_resadd[23]\, S => - add_D, Y => N_31); - - \REG[3]\ : DFN1E0C0 - port map(D => \REG_4[3]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(3)); - - un2_resadd_ADD_27x27_fast_I248_Y_0_0 : XOR2 - port map(A => ADDERinA_i(18), B => ADDERinB(18), Y => - ADD_27x27_fast_I248_Y_0_0); - - \REG_RNO[3]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_11, Y => \REG_4[3]\); - - un2_resadd_ADD_27x27_fast_I121_Y : AO1 - port map(A => N_47, B => N450, C => N449, Y => N502); - - un2_resadd_ADD_27x27_fast_I113_Y : AO1 - port map(A => N445, B => N442, C => N441, Y => N494); - - \REG[17]\ : DFN1E0C0 - port map(D => \REG_4[17]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(17)); - - un2_resadd_ADD_27x27_fast_I161_Y : AO1 - port map(A => N502, B => N495, C => N494, Y => N548); - - un2_resadd_ADD_27x27_fast_I22_G0N : NOR2A - port map(A => ADDERinB(22), B => ADDERinA_22, Y => N391); - - un2_resadd_ADD_27x27_fast_I157_Y : AO1A - port map(A => N491, B => N498, C => N490, Y => N544); - - GND_i_0 : GND - port map(Y => GND_0); - - un2_resadd_ADD_27x27_fast_I195_un1_Y : OR3B - port map(A => N499, B => N_47, C => N491, Y => I195_un1_Y_i); - - un2_resadd_ADD_27x27_fast_I115_Y : AO1B - port map(A => ADD_27x27_fast_I115_un1_Y_0, B => N444, C => - ADD_27x27_fast_I115_Y_0, Y => N496); - - un2_resadd_ADD_27x27_fast_I89_Y : AO1 - port map(A => N421, B => N418, C => N417, Y => N470); - - \REG_RNO_0[16]\ : MX2C - port map(A => ADDERinB(16), B => \un2_resadd[16]\, S => - add_D, Y => N_24); - - un2_resadd_ADD_27x27_fast_I213_Y_0 : AO1A - port map(A => N475, B => N482, C => N474, Y => - ADD_27x27_fast_I213_Y_0); - - un2_resadd_ADD_27x27_fast_I16_P0N : OR2 - port map(A => ADDERinB(16), B => ADDERinA_16, Y => N374); - - \REG_RNO[16]\ : NOR2 - port map(A => clr_MAC_D, B => N_24, Y => \REG_4[16]\); - - un2_resadd_ADD_27x27_fast_I115_Y_0 : MIN3 - port map(A => ADDERinA_6, B => ADDERinB(6), C => N340, Y - => ADD_27x27_fast_I115_Y_0); - - un2_resadd_ADD_27x27_fast_I47_Y : AO13 - port map(A => N367, B => ADDERinB(15), C => ADDERinA_15, Y - => N425); - - \REG_RNO_0[0]\ : AX1E - port map(A => ADDERinA_0, B => add_D_0, C => ADDERinB(0), Y - => N_8); - - un2_resadd_ADD_27x27_fast_I114_Y : NOR2B - port map(A => N446, B => N442, Y => N495); - - un2_resadd_ADD_27x27_fast_I251_Y_0 : AX1D - port map(A => N415, B => ADD_27x27_fast_I210_Y_0_a2, C => - ADD_27x27_fast_I251_Y_0_0, Y => \un2_resadd[21]\); - - \REG_RNO[6]\ : NOR2 - port map(A => clr_MAC_D, B => N_14, Y => \REG_4[6]\); - - \REG_RNO[5]\ : NOR2 - port map(A => clr_MAC_D, B => N_13, Y => \REG_4[5]\); - - un2_resadd_ADD_27x27_fast_I56_Y : OA1 - port map(A => ADDERinA_11, B => ADDERinB(11), C => N356, Y - => N434); - - \REG[2]\ : DFN1E0C0 - port map(D => \REG_4[2]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(2)); - - un2_resadd_ADD_27x27_fast_I254_Y_0_0 : XOR2 - port map(A => ADDERinA_24, B => ADDERinB(24), Y => - ADD_27x27_fast_I254_Y_0_0); - - un2_resadd_ADD_27x27_fast_I10_P0N : OR2 - port map(A => ADDERinB(10), B => ADDERinA_10, Y => N356); - - \REG_RNO[23]\ : NOR2 - port map(A => clr_MAC_D, B => N_31, Y => \REG_4[23]\); - - un2_resadd_ADD_27x27_fast_I130_Y : NOR2 - port map(A => N471, B => N463, Y => N517); - - un2_resadd_ADD_27x27_fast_I209_Y_1 : OA1A - port map(A => N474, B => N467, C => ADD_27x27_fast_I209_Y_0, - Y => ADD_27x27_fast_I209_Y_1); - - \REG[7]\ : DFN1E0C0 - port map(D => \REG_4[7]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(7)); - - un2_resadd_ADD_27x27_fast_I211_Y_1 : AOI1B - port map(A => N540, B => N525, C => ADD_27x27_fast_I211_Y_0, - Y => ADD_27x27_fast_I211_Y_1); - - un2_resadd_ADD_27x27_fast_I61_Y_0_o2 : AO1 - port map(A => N350, B => N346, C => N349, Y => N439); - - \REG_RNO[10]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_18, Y => \REG_4[10]\); - - \REG[4]\ : DFN1E0C0 - port map(D => \REG_4[4]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(4)); - - \REG[10]\ : DFN1E0C0 - port map(D => \REG_4[10]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(10)); - - un2_resadd_ADD_27x27_fast_I243_Y_0_0 : XOR2 - port map(A => ADDERinA_13, B => ADDERinB(13), Y => - ADD_27x27_fast_I243_Y_0_0); - - un2_resadd_ADD_27x27_fast_I208_Y_3 : AOI1B - port map(A => N534, B => N519, C => ADD_27x27_fast_I208_Y_2, - Y => ADD_27x27_fast_I208_Y_3); - - un2_resadd_ADD_27x27_fast_I192_Y_0_a2 : OA1 - port map(A => I193_un1_Y, B => N540, C => N362, Y => - ADD_27x27_fast_I192_Y_0_a2); - - un2_resadd_ADD_27x27_fast_I190_Y : OR2 - port map(A => N534, B => I190_un1_Y, Y => N651); - - un2_resadd_ADD_27x27_fast_I18_P0N : OR2A - port map(A => ADDERinA_i(18), B => ADDERinB(18), Y => N380); - - un2_resadd_ADD_27x27_fast_I207_un1_Y : OR3C - port map(A => N533, B => N517, C => N548, Y => I207_un1_Y); - - un2_resadd_ADD_27x27_fast_I59_Y : MAJ3 - port map(A => ADDERinA_9, B => ADDERinB(9), C => N349, Y - => N437); - - un2_resadd_ADD_27x27_fast_I251_Y_0_0 : XOR2 - port map(A => ADDERinA_21, B => ADDERinB(21), Y => - ADD_27x27_fast_I251_Y_0_0); - - un2_resadd_ADD_27x27_fast_I208_un1_Y : OR3C - port map(A => N519, B => N535, C => N550, Y => I208_un1_Y); - - \REG_RNO[17]\ : NOR2 - port map(A => clr_MAC_D, B => N_25, Y => \REG_4[17]\); - - un1_clr_1 : NOR3 - port map(A => add_D_0, B => MACMUX2sel_D, C => clr_MAC_D_0, - Y => \un1_clr_1\); - - un2_resadd_ADD_27x27_fast_I98_Y : OR2B - port map(A => N430, B => N426, Y => N479); - - un2_resadd_ADD_27x27_fast_I12_P0N : OR2 - port map(A => ADDERinB(12), B => ADDERinA_12, Y => N362); - - un2_resadd_ADD_27x27_fast_I117_Y : AO1 - port map(A => N449, B => N446, C => N445, Y => N498); - - un2_resadd_ADD_27x27_fast_I64_Y : OA1 - port map(A => ADDERinA_7, B => ADDERinB(7), C => N344, Y - => N442); - - \REG[8]\ : DFN1E0C0 - port map(D => \REG_4[8]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(8)); - - un2_resadd_ADD_27x27_fast_I240_Y_0 : AX1A - port map(A => N544, B => I195_un1_Y_i, C => - ADD_27x27_fast_I240_Y_0_0, Y => \un2_resadd[10]\); - - un2_resadd_ADD_27x27_fast_I0_CO1 : OR2B - port map(A => ADDERinB(0), B => ADDERinA_0, Y => N325); - - un2_resadd_ADD_27x27_fast_I34_Y : OA1 - port map(A => ADDERinA_21, B => ADDERinB(21), C => N392, Y - => N412); - - un2_resadd_ADD_27x27_fast_I105_Y : AO1 - port map(A => N437, B => N434, C => N433, Y => N486); - - \REG_RNO_0[3]\ : MX2C - port map(A => ADDERinB(3), B => \un2_resadd[3]\, S => - add_D_0, Y => N_11); - - un2_resadd_ADD_27x27_fast_I50_Y : OA1 - port map(A => ADDERinA_13, B => ADDERinB(13), C => N368, Y - => N428); - - un2_resadd_ADD_27x27_fast_I239_Y_0 : AX1E - port map(A => N_78_i, B => ADD_27x27_fast_I196_Y_0_0, C => - ADD_27x27_fast_I239_Y_0_0, Y => \un2_resadd[9]\); - - \REG[24]\ : DFN1E0C0 - port map(D => \REG_4[24]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(24)); - - un2_resadd_ADD_27x27_fast_I3_P0N_i_o2 : OR2 - port map(A => ADDERinB(3), B => ADDERinA_3, Y => N_58); - - un2_resadd_ADD_27x27_fast_I15_P0N : OR2A - port map(A => ADDERinA_15, B => ADDERinB(15), Y => N371); - - un2_resadd_ADD_27x27_fast_I249_Y_0 : AX1D - port map(A => I212_un1_Y, B => ADD_27x27_fast_I212_Y_1, C - => ADD_27x27_fast_I249_Y_0_0, Y => \un2_resadd[19]\); - - un2_resadd_ADD_27x27_fast_I189_Y : AOI1 - port map(A => N548, B => N533, C => N532, Y => N648_i); - - un2_resadd_ADD_27x27_fast_I4_G0N_i_o2 : NOR2B - port map(A => ADDERinB(4), B => ADDERinA_4, Y => N_52_i_0); - - un2_resadd_ADD_27x27_fast_I250_Y_0_0 : XOR2 - port map(A => ADDERinA_20, B => ADDERinB(20), Y => - ADD_27x27_fast_I250_Y_0_0); - - \REG_RNO_0[12]\ : MX2C - port map(A => ADDERinB(12), B => \un2_resadd[12]\, S => - add_D, Y => N_20); - - un2_resadd_ADD_27x27_fast_I44_Y : OA1 - port map(A => ADDERinA_17, B => ADDERinB(17), C => N374, Y - => N422); - - un2_resadd_ADD_27x27_fast_I233_Y_0 : XOR3 - port map(A => ADDERinB(3), B => ADDERinA_3, C => N_48, Y - => \un2_resadd[3]\); - - un2_resadd_ADD_27x27_fast_I194_un1_Y : OR2B - port map(A => N_48, B => N543, Y => I194_un1_Y_i); - - un2_resadd_ADD_27x27_fast_I14_P0N : OR2A - port map(A => ADDERinA_14, B => ADDERinB(14), Y => N368); - - un2_resadd_ADD_27x27_fast_I243_Y_0 : AX1A - port map(A => ADD_27x27_fast_I192_Y_0_a2, B => N361, C => - ADD_27x27_fast_I243_Y_0_0, Y => \un2_resadd[13]\); - - un2_resadd_ADD_27x27_fast_I146_Y : NOR2 - port map(A => N487, B => N479, Y => N533); - - \REG_RNO_0[14]\ : MX2C - port map(A => ADDERinB(14), B => \un2_resadd[14]\, S => - add_D_0, Y => N_22); - - \REG[16]\ : DFN1E0C0 - port map(D => \REG_4[16]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(16)); - - un2_resadd_ADD_27x27_fast_I62_Y_i_o2 : OAI1 - port map(A => ADDERinA_7, B => ADDERinB(7), C => N350, Y - => N_73); - - un2_resadd_ADD_27x27_fast_I210_Y_0_a2_1 : NOR2B - port map(A => N386, B => N383, Y => N_105_1); - - un2_resadd_ADD_27x27_fast_I102_Y : OR2B - port map(A => N434, B => N430, Y => N483); - - \REG_RNO_0[4]\ : MX2C - port map(A => ADDERinB(4), B => \un2_resadd[4]\, S => - add_D_0, Y => N_12); - - un2_resadd_ADD_27x27_fast_I20_G0N : NOR2B - port map(A => ADDERinB(20), B => ADDERinA_20, Y => N385); - - \REG_RNO_0[2]\ : MX2C - port map(A => ADDERinB(2), B => \un2_resadd[2]\, S => add_D, - Y => N_10); - - un2_resadd_ADD_27x27_fast_I82_Y : OR2B - port map(A => N414, B => N410, Y => N463); - - un2_resadd_ADD_27x27_fast_I234_Y_0 : XOR3 - port map(A => ADDERinB(4), B => ADDERinA_4, C => N502, Y - => \un2_resadd[4]\); - - un2_resadd_ADD_27x27_fast_I250_Y_0 : AX1E - port map(A => I211_un1_Y, B => ADD_27x27_fast_I211_Y_1, C - => ADD_27x27_fast_I250_Y_0_0, Y => \un2_resadd[20]\); - - un2_resadd_ADD_27x27_fast_I252_Y_0_0 : XOR2 - port map(A => ADDERinA_22, B => ADDERinB(22), Y => - ADD_27x27_fast_I252_Y_0_0); - - un2_resadd_ADD_27x27_fast_I244_Y_0 : XOR3 - port map(A => ADDERinB(14), B => ADDERinA_14, C => N654_i, - Y => \un2_resadd[14]\); - - un2_resadd_ADD_27x27_fast_I69_Y_i_a2 : NOR2 - port map(A => N_59, B => N_52_i_0, Y => N_108); - - un2_resadd_ADD_27x27_fast_I18_G0N : NOR2A - port map(A => ADDERinB(18), B => ADDERinA_i(18), Y => N379); - - un2_resadd_ADD_27x27_fast_I13_G0N : OR2B - port map(A => ADDERinB(13), B => ADDERinA_13, Y => N364); - - \REG_RNO_0[5]\ : MX2C - port map(A => ADDERinB(5), B => \un2_resadd[5]\, S => add_D, - Y => N_13); - - \REG[21]\ : DFN1E0C0 - port map(D => \REG_4[21]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(21)); - - un2_resadd_ADD_27x27_fast_I237_Y_0 : XOR3 - port map(A => ADDERinB(7), B => ADDERinA_7, C => N550, Y - => \un2_resadd[7]\); - - \REG_RNO_0[22]\ : MX2C - port map(A => ADDERinB(22), B => \un2_resadd[22]\, S => - add_D_0, Y => N_30); - - un2_resadd_ADD_27x27_fast_I107_Y : AO1B - port map(A => N439, B => N436, C => ADD_27x27_fast_I107_Y_0, - Y => N488); - - un2_resadd_ADD_27x27_fast_I247_Y_0 : AX1A - port map(A => N423, B => N_98_i, C => - ADD_27x27_fast_I247_Y_0_0, Y => \un2_resadd[17]\); - - \REG_RNO[0]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_8, Y => \REG_4[0]\); - - \REG_RNO_0[15]\ : MX2C - port map(A => ADDERinB(15), B => \un2_resadd[15]\, S => - add_D_0, Y => N_23); - - un2_resadd_ADD_27x27_fast_I148_Y : NOR2 - port map(A => N489, B => N481, Y => N535); - - \REG_RNO_0[24]\ : MX2C - port map(A => ADDERinB(24), B => \un2_resadd[24]\, S => - add_D_0, Y => N_32); - - un2_resadd_ADD_27x27_fast_I253_Y_0 : AX1E - port map(A => I208_un1_Y, B => ADD_27x27_fast_I208_Y_3, C - => ADD_27x27_fast_I253_Y_0_0, Y => \un2_resadd[23]\); - - un2_resadd_ADD_27x27_fast_I213_un1_Y_0 : NOR3B - port map(A => N499, B => N_47, C => N491, Y => - ADD_27x27_fast_I213_un1_Y_0); - - \REG[15]\ : DFN1E0C0 - port map(D => \REG_4[15]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(15)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_MUX2 is - - port( MULTout_D : in std_logic_vector(24 downto 7); - ADDERout : in std_logic_vector(24 downto 7); - sample_out_s : out std_logic_vector(17 downto 0); - MACMUX2sel_D_D : in std_logic - ); - -end MAC_MUX2; - -architecture DEF_ARCH of MAC_MUX2 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \RES[19]\ : MX2 - port map(A => ADDERout(19), B => MULTout_D(19), S => - MACMUX2sel_D_D, Y => sample_out_s(12)); - - \RES[9]\ : MX2 - port map(A => ADDERout(9), B => MULTout_D(9), S => - MACMUX2sel_D_D, Y => sample_out_s(2)); - - GND_i_0 : GND - port map(Y => GND_0); - - \RES[12]\ : MX2 - port map(A => ADDERout(12), B => MULTout_D(12), S => - MACMUX2sel_D_D, Y => sample_out_s(5)); - - VCC_i : VCC - port map(Y => \VCC\); - - \RES[17]\ : MX2 - port map(A => ADDERout(17), B => MULTout_D(17), S => - MACMUX2sel_D_D, Y => sample_out_s(10)); - - \RES[22]\ : MX2 - port map(A => ADDERout(22), B => MULTout_D(22), S => - MACMUX2sel_D_D, Y => sample_out_s(15)); - - \RES[11]\ : MX2 - port map(A => ADDERout(11), B => MULTout_D(11), S => - MACMUX2sel_D_D, Y => sample_out_s(4)); - - \RES[18]\ : MX2 - port map(A => ADDERout(18), B => MULTout_D(18), S => - MACMUX2sel_D_D, Y => sample_out_s(11)); - - \RES[21]\ : MX2 - port map(A => ADDERout(21), B => MULTout_D(21), S => - MACMUX2sel_D_D, Y => sample_out_s(14)); - - \RES[14]\ : MX2 - port map(A => ADDERout(14), B => MULTout_D(14), S => - MACMUX2sel_D_D, Y => sample_out_s(7)); - - GND_i : GND - port map(Y => \GND\); - - \RES[24]\ : MX2 - port map(A => ADDERout(24), B => MULTout_D(24), S => - MACMUX2sel_D_D, Y => sample_out_s(17)); - - \RES[10]\ : MX2 - port map(A => ADDERout(10), B => MULTout_D(10), S => - MACMUX2sel_D_D, Y => sample_out_s(3)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \RES[8]\ : MX2 - port map(A => ADDERout(8), B => MULTout_D(8), S => - MACMUX2sel_D_D, Y => sample_out_s(1)); - - \RES[16]\ : MX2 - port map(A => ADDERout(16), B => MULTout_D(16), S => - MACMUX2sel_D_D, Y => sample_out_s(9)); - - \RES[20]\ : MX2 - port map(A => ADDERout(20), B => MULTout_D(20), S => - MACMUX2sel_D_D, Y => sample_out_s(13)); - - \RES[13]\ : MX2 - port map(A => ADDERout(13), B => MULTout_D(13), S => - MACMUX2sel_D_D, Y => sample_out_s(6)); - - \RES[7]\ : MX2 - port map(A => ADDERout(7), B => MULTout_D(7), S => - MACMUX2sel_D_D, Y => sample_out_s(0)); - - \RES[23]\ : MX2 - port map(A => ADDERout(23), B => MULTout_D(23), S => - MACMUX2sel_D_D, Y => sample_out_s(16)); - - \RES[15]\ : MX2 - port map(A => ADDERout(15), B => MULTout_D(15), S => - MACMUX2sel_D_D, Y => sample_out_s(8)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_2 is - - port( MACMUXsel_D : out std_logic; - MACMUXsel_D_0 : out std_logic; - N_4 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - MACMUXsel_D_1 : out std_logic - ); - -end MAC_REG_1_2; - -architecture DEF_ARCH of MAC_REG_1_2 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_1[0]\ : DFN1C0 - port map(D => N_4, CLK => HCLK_c, CLR => HRESETn_c, Q => - MACMUXsel_D_1); - - \Q_0[0]\ : DFN1C0 - port map(D => N_4, CLK => HCLK_c, CLR => HRESETn_c, Q => - MACMUXsel_D_0); - - \Q[0]\ : DFN1C0 - port map(D => N_4, CLK => HCLK_c, CLR => HRESETn_c, Q => - MACMUXsel_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Multiplier is - - port( MULTout : out std_logic_vector(24 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - mult : in std_logic; - mult_0 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end Multiplier; - -architecture DEF_ARCH of Multiplier is - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N399, ADD_22x22_fast_I80_un1_Y, N354, I120_un1_Y, - N407, N400, ADD_22x22_fast_I154_Y_0, - ADD_22x22_fast_I208_Y_0_0, N_253, N_250, - ADD_22x22_fast_I209_Y_0_2, N_252, - ADD_22x22_fast_I209_Y_0_0, N_254, \a17_b_i[7]\, - ADD_22x22_fast_I207_Y_0_0, N_249, N_244, - ADD_22x22_fast_I171_Y_2, I70_un1_Y, - ADD_22x22_fast_I171_Y_0, I110_un1_Y, N321, - ADD_22x22_fast_I206_Y_0_0, N_243, N_236, - ADD_22x22_fast_I170_Y_2, N395, N388, - ADD_22x22_fast_I170_Y_1, N346, N343, - ADD_22x22_fast_I170_Y_0, N324, ADD_22x22_fast_I205_Y_0_0, - madd_301, madd_527_0, N_235, ADD_22x22_fast_I172_Y_2, - I112_un1_Y, ADD_22x22_fast_I172_Y_0, I148_un1_Y, N350, - N347, ADD_22x22_fast_I200_Y_0_0, N_167, N_152, - ADD_22x22_fast_I203_Y_0_0, madd_262, madd_462_0, N_213, - ADD_22x22_fast_I173_Y_2, ADD_22x22_fast_I114_un1_Y, - ADD_22x22_fast_I173_Y_0, I173_un1_Y_i, - ADD_22x22_fast_I74_un1_Y, ADD_22x22_fast_I32_un1_Y, N318, - ADD_22x22_fast_I199_Y_0_0, N_134, N_149, N_136, - ADD_22x22_fast_I201_Y_0_0, N_150, N_165, N_183, - ADD_22x22_fast_I152_Y_0, N403, N396, - ADD_22x22_fast_I202_Y_0_0, N_182, madd_458_0_0, N_184, - ADD_22x22_fast_I198_Y_0_0, N_118, N_133, N_120, - ADD_22x22_fast_I172_un1_Y_0, N408, N416, N378, - ADD_22x22_fast_I153_un1_Y_0, N361, N398, N365, - ADD_22x22_fast_I155_Y_0, I82_un1_Y, N356, I155_un1_Y_i, - ADD_22x22_fast_I196_Y_0_0, N_86, N_101, N_88, - ADD_22x22_fast_I173_un1_Y_0, N410, N418, N_12, - ADD_22x22_fast_I152_un1_Y_0, I132_un1_Y_i, N411, N404, - ADD_22x22_fast_I197_Y_0_0, N_104, N_119, - ADD_22x22_fast_I157_un1_Y_0, N373, N421, N369, - ADD_22x22_fast_I155_un1_Y_0, I135_un1_Y_i, N417, - ADD_22x22_fast_I195_Y_0_0, N_72, N_87, - ADD_22x22_fast_I194_Y_0_0, N_69, madd_124_m6, N_56, - ADD_22x22_fast_I192_Y_0_0, N_28, N_39, N_30, N_180, - madd_458_14_0, N_195, madd_548_0_0, N_222, N_233, - ADD_22x22_fast_I190_Y_0_0, N_11_i, CO2, N_19, - madd_416_0_0, N_177_i, N_164, madd_268_0_0, N_113_i, - N_115, madd_522_0_tz_0, N_192, N_194, N_219, - madd_198_0_tz_0, N_61_i, N_63, N_50, madd_235_0_tz_0, - N_64_i, N_79, N_66, madd_24_0_0, N_7_i, N_9, - madd_120_0_0_1, N_32_i, N_43, N_34, madd_457_m5_0, N_185, - N_187, madd_39_0_0, N_15_i, N_13, madd_24_4_0, \a1_b[3]\, - \a0_b[4]\, madd_88_8_0, N_33_i, N_31, madd_268_8_0, - N_105_i, N_109, madd_115_0_0_1, \a0_b[8]\, \a2_b[6]\, - \a1_b[7]\, madd_493_6_0, \a_i10_b[8]\, madd_39_2_0, - \a5_b[0]\, \a3_b[2]\, madd_231_2_0, \a11_b[0]\, \a9_b[2]\, - madd_268_2_0, \a12_b[0]\, \a10_b[2]\, madd_523_4_0, - \a14_b[5]\, \a12_b[7]\, madd_458_2_0, madd_24_2_0, - \a2_b[2]\, \a4_b[0]\, madd_268_7_0, \a6_b[6]\, \a5_b[7]\, - madd_88_4_0, \a2_b[5]\, \a4_b[3]\, I157_un1_Y, I130_un1_Y, - ADD_22x22_fast_I171_un1_Y_0, madd_235_0_tz, N_99, N_174, - N_191, N402, I172_un1_Y, N392, ADD_22x22_fast_I115_Y_0, - I152_un1_Y, I154_un1_Y, N461, N_246_i, N_251, N_248, - \a16_b[7]\, \a_i15_b[8]\, \a17_b_i[6]\, N_240_i, N_247, - N_242, N_245, \a_i14_b[8]\, N_238, \a16_b[6]\, \a15_b[7]\, - \a17_b_i[5]\, N_241, N_239_i, N_234, N_237, \a16_b[5]\, - \a15_b[6]\, \a17_b_i[4]\, \a_i13_b[8]\, \a14_b[7]\, N_228, - N_230_i, N_232, N_224, N_231, N_229_i, N_220, N_227_i, - \a16_b[4]\, \a15_b[5]\, \a17_b_i[3]\, \a13_b[7]\, - \a14_b[6]\, \a_i12_b[8]\, N_218, N_216, N_225, N_223, - N_221, N_212, N_215, \a16_b[3]\, \a15_b[4]\, \a17_b_i[2]\, - N_217, \a13_b[6]\, N_204, \a_i11_b[8]\, N_202, N_208, - N_210, madd_457_m6, N_209_i, N_211, N_201, \a16_b[2]\, - \a15_b[3]\, \a17_b_i[1]\, N_203_i, \a12_b[6]\, \a14_b[4]\, - \a13_b[5]\, N_207, N_188_i, N_190, N_205, N_196, N_169_i, - \a15_b[1]\, \a16_b[0]\, \a14_b[2]\, N_171, \a11_b[5]\, - \a13_b[3]\, \a12_b[4]\, N_173, \a9_b[7]\, \a10_b[6]\, - \a_i8_b[8]\, N_175_i_0, N_156, N_154_i, N_158, N_163, - N_161_i, N_148, N_153_i, \a13_b[2]\, \a15_b[0]\, - \a14_b[1]\, N_155, \a10_b[5]\, \a12_b[3]\, \a11_b[4]\, - N_157, \a8_b[7]\, \a9_b[6]\, \a_i7_b[8]\, N_159_i, N_142, - N_138_i, N_140, N_146, N_144, N_147, N_145_i, N_132, - N_137_i, \a12_b[2]\, \a14_b[0]\, \a13_b[1]\, N_139, - \a9_b[5]\, \a11_b[3]\, \a10_b[4]\, N_141, \a_i6_b[8]\, - \a8_b[6]\, \a7_b[7]\, N_143_i, N_126, N_122_i, N_124, - N_130, N_128, N_131, N_129_i, N_116, N_121_i, \a11_b[2]\, - \a13_b[0]\, \a12_b[1]\, N_123, \a8_b[5]\, \a10_b[3]\, - \a9_b[4]\, N_125, \a6_b[7]\, \a7_b[6]\, \a_i5_b[8]\, - N_127_i, N_108, N_106_i, N_110, N_114, N_112, \a11_b[1]\, - N_107, \a7_b[5]\, \a9_b[3]\, \a8_b[4]\, \a_i4_b[8]\, - N_111_i, N_92, N_90_i, N_94, N_98, N_96, N_97, N_84, - N_89_i, \a10_b[1]\, N_91, \a6_b[5]\, \a8_b[3]\, \a7_b[4]\, - N_93, \a4_b[7]\, \a5_b[6]\, \a_i3_b[8]\, N_95_i, N_76, - N_74_i, N_78, N_82, N_80, N_85, N_83, N_81, N_68, N_73_i, - \a8_b[2]\, \a10_b[0]\, \a9_b[1]\, N_75, \a5_b[5]\, - \a7_b[3]\, \a6_b[4]\, N_77, \a4_b[6]\, \a_i2_b[8]\, - \a3_b[7]\, N_60, N_58_i, N_62, madd_119_m6, N_65_i, N_67, - N_57, \a7_b[2]\, \a9_b[0]\, \a8_b[1]\, N_59_i, \a5_b[4]\, - \a6_b[3]\, \a4_b[5]\, \a3_b[6]\, \a2_b[7]\, \a_i1_b[8]\, - N_44, \a_i0_b[8]\, N_46, N_48, N_45, \a3_b[5]\, \a5_b[3]\, - \a4_b[4]\, \a6_b[2]\, \a8_b[0]\, \a7_b[1]\, \a5_b[2]\, - \a7_b[0]\, \a6_b[1]\, \a3_b[4]\, N_37, N_24, N_25, N_14, - \a0_b[6]\, N_16, N_27, N_21_i, N_23, N_18, \a3_b[3]\, - \a2_b[4]\, \a1_b[5]\, N_17, N_8, \a4_b[1]\, \a0_b[5]\, - \a2_b[3]\, \a1_b[4]\, N_6, \a3_b[1]\, N_4, N_5, N_3, - \a0_b[3]\, N_2, \a3_b[0]\, \a2_b[1]\, \a1_b[2]\, N_1_i, - \a0_b[2]\, \a2_b[0]\, \a1_b[1]\, \a13_b[4]\, \a15_b[2]\, - \a14_b[3]\, N_189_i, \a10_b[7]\, \a12_b[5]\, \a11_b[6]\, - N_170, \a_i9_b[8]\, N_172, N_178, N_176, \RESMULT[24]\, - ADD_22x22_fast_I170_Y_3, \RESMULT[23]\, - ADD_22x22_fast_I171_Y_3, \RESMULT[22]\, \RESMULT[21]\, - I150_un1_Y, \RESMULT[20]\, \RESMULT[18]\, \RESMULT[17]\, - I122_un1_Y, \RESMULT[16]\, N449, I156_un1_Y_i, - \RESMULT[15]\, N451, \RESMULT[14]\, I158_un1_Y, N453, - \RESMULT[13]\, N455, I159_un1_Y_i, \RESMULT[12]\, - \RESMULT[10]\, \RESMULT[9]\, \RESMULT[8]\, N_53, N_55, - N419, \RESMULT[7]\, \RESMULT[6]\, N_29, \RESMULT[5]\, - \RESMULT[11]\, N413, I133_un1_Y_i, \RESMULT[19]\, N_214, - N544, \a17_b_i[0]\, N_186_1, N_206, I118_un1_Y, N397, - I153_un1_Y, N390, ADD_22x22_fast_I171_Y_3_tz, - ADD_22x22_fast_I170_Y_3_tz, N319, N313, N353, N349, - madd_61_2_0, \a6_b[0]\, \a5_b[1]\, N316, \a4_b[2]\, N_35, - \a0_b[7]\, \a1_b[6]\, N_22, madd_88_0_0, N_26, N_38, - N_40_i, N_51, N_36, N_179, N_162, N_160, madd_457_N_4, - madd_457tt_m3, madd_119_N_4, madd_119tt_m3, madd_124_N_4, - madd_124tt_m3, ADD_22x22_fast_I170_un1_Y_0, madd_462_0_tz, - madd_522_0, madd_487_0, madd_198_0, madd_477_0, - madd_477_0_tz, N412, madd_271, N_10, N_70, madd_112, - N_100, N_102, madd_133, N_166, madd_298, CO1, \a0_b[1]\, - \a1_b[0]\, \RESMULT[1]\, \RESMULT[2]\, \RESMULT[3]\, - \RESMULT[4]\, N273, N274, N276, N277, N279, N280, N288, - N289, N291, N292, N294, N295, N297, N298, N300, N301, - N303, N304, N306, N307, N352, N309, N312, N310, N357, - N362, N363, N364, N368, N285, N286, N372, N283, N376, - N377, N360, I90_un1_Y, N409, I101_un1_Y, N415, N345, N325, - N405, N282, N370, N374, N351, N358, N359, I92_un1_Y, N366, - N371, N375, I124_un1_Y, I134_un1_Y, madd_240, I126_un1_Y, - \RESMULT[0]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - RESMULT_madd_120_0 : XNOR3 - port map(A => N_38, B => madd_120_0_0_1, C => N_40_i, Y => - N_53); - - RESMULT_madd_452 : MIN3 - port map(A => N_189_i, B => N_176, C => N_178, Y => N_196); - - \RESMULT_a9_b[1]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(1), Y => - \a9_b[1]\); - - RESMULT_madd_65 : AO13 - port map(A => N_18, B => N_21_i, C => N_23, Y => N_28); - - RESMULT_madd_420 : AO18 - port map(A => N_164, B => N_179, C => N_177_i, Y => N_182); - - RESMULT_madd_606_ADD_22x22_fast_I3_P0N : OR2 - port map(A => N_55, B => N_53, Y => N283); - - RESMULT_madd_523_0 : XOR3 - port map(A => N_223, B => N_221, C => N_212, Y => N_225); - - \RESMULT_a4_b[2]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(2), Y => - \a4_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I124_un1_Y : NOR2B - port map(A => N411, B => N404, Y => I124_un1_Y); - - RESMULT_madd_552 : MIN3 - port map(A => N_222, B => N_224, C => N_233, Y => N_236); - - \RESMULT_a9_b[4]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(4), Y => - \a9_b[4]\); - - RESMULT_madd_267 : MAJ3 - port map(A => N_111_i, B => N_96, C => N_98, Y => N_116); - - \RESMULT_a11_b[5]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(5), Y => - \a11_b[5]\); - - \RESMULT_a10_b[7]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(7), Y => - \a10_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I58_Y : AO1 - port map(A => N280, B => N276, C => N279, Y => N374); - - RESMULT_madd_606_ADD_22x22_fast_I55_Y : NOR2B - port map(A => N286, B => N283, Y => N371); - - RESMULT_madd_606_ADD_22x22_fast_I99_Y : NOR2B - port map(A => N377, B => N373, Y => N418); - - RESMULT_madd_606_ADD_22x22_fast_I156_un1_Y : OR3C - port map(A => N404, B => N412, C => N419, Y => I156_un1_Y_i); - - RESMULT_madd_146 : MAJ3 - port map(A => \a_i0_b[8]\, B => N_44, C => N_46, Y => - N_64_i); - - RESMULT_madd_61_2_0 : XOR2 - port map(A => \a6_b[0]\, B => \a5_b[1]\, Y => madd_61_2_0); - - RESMULT_madd_378 : MAJ3 - port map(A => N_159_i, B => N_144, C => N_146, Y => N_164); - - RESMULT_madd_231_0 : XNOR3 - port map(A => N_99, B => N_97, C => N_84, Y => N_101); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_0 : NOR3A - port map(A => ADD_22x22_fast_I74_un1_Y, B => - ADD_22x22_fast_I32_un1_Y, C => N318, Y => - ADD_22x22_fast_I173_Y_0); - - \RESMULT_a11_b[0]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(0), Y => - \a11_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I9_G0N : XA1A - port map(A => N_134, B => N_149, C => N_136, Y => N300); - - \RESMULT_a13_b[7]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(7), Y => - \a13_b[7]\); - - RESMULT_madd_457_m5 : XOR3 - port map(A => N_174, B => madd_457_m5_0, C => N_191, Y => - madd_458_14_0); - - RESMULT_madd_43 : AO13 - port map(A => N_8, B => N_15_i, C => N_13, Y => N_18); - - RESMULT_madd_141 : MAJ3 - port map(A => \a3_b[6]\, B => \a2_b[7]\, C => \a_i1_b[8]\, - Y => N_62); - - \RESMULT_a7_b[7]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(7), Y => - \a7_b[7]\); - - RESMULT_madd_235 : AO1 - port map(A => madd_235_0_tz, B => N_97, C => madd_133, Y - => N_102); - - RESMULT_madd_197 : NOR2A - port map(A => N_83, B => N_68, Y => madd_112); - - RESMULT_madd_606_ADD_22x22_fast_I200_Y_0_0 : XOR2 - port map(A => N_167, B => N_152, Y => - ADD_22x22_fast_I200_Y_0_0); - - RESMULT_madd_38 : MIN3 - port map(A => \a2_b[3]\, B => \a0_b[5]\, C => \a1_b[4]\, Y - => N_16); - - \REG[6]\ : DFN1E1C0 - port map(D => \RESMULT[6]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(6)); - - RESMULT_madd_200 : NOR2A - port map(A => N_85, B => N_70, Y => N_88); - - RESMULT_madd_104 : MAJ3 - port map(A => \a5_b[3]\, B => \a3_b[5]\, C => \a4_b[4]\, Y - => N_46); - - \RESMULT_a14_b[7]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(7), Y => - \a14_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I31_Y : AO1C - port map(A => N_243, B => N_236, C => N319, Y => N347); - - \RESMULT_a6_b[7]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(7), Y => - \a6_b[7]\); - - \RESMULT_a0_b[3]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(3), Y => - \a0_b[3]\); - - \RESMULT_a4_b[3]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(3), Y => - \a4_b[3]\); - - \RESMULT_a15_b[4]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(4), Y => - \a15_b[4]\); - - RESMULT_madd_247 : MAJ3 - port map(A => \a9_b[3]\, B => \a7_b[5]\, C => \a8_b[4]\, Y - => N_108); - - RESMULT_madd_606_ADD_22x22_fast_I172_un1_Y_0 : NOR3C - port map(A => N408, B => N416, C => N378, Y => - ADD_22x22_fast_I172_un1_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I122_un1_Y : OR2A - port map(A => N409, B => N402, Y => I122_un1_Y); - - RESMULT_madd_523_8 : XOR3 - port map(A => N_217, B => N_215, C => N_206, Y => N_221); - - \RESMULT_a16_b[7]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(7), Y => - \a16_b[7]\); - - RESMULT_madd_457_m5_0 : XOR2 - port map(A => N_185, B => N_187, Y => madd_457_m5_0); - - RESMULT_madd_235_0_tz : OR2 - port map(A => madd_235_0_tz_0, B => N_99, Y => - madd_235_0_tz); - - RESMULT_madd_61_0 : XOR3 - port map(A => N_21_i, B => N_23, C => N_18, Y => N_27); - - \RESMULT_a9_b[0]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(0), Y => - \a9_b[0]\); - - \RESMULT_a6_b[1]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(1), Y => - \a6_b[1]\); - - \RESMULT_a13_b[0]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(0), Y => - \a13_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I73_Y : OR2A - port map(A => N351, B => N347, Y => N392); - - RESMULT_madd_507 : MAJ3 - port map(A => \a14_b[5]\, B => \a12_b[7]\, C => \a13_b[6]\, - Y => N_218); - - RESMULT_madd_606_ADD_22x22_fast_I155_un1_Y : OR2A - port map(A => ADD_22x22_fast_I155_un1_Y_0, B => N402, Y => - I155_un1_Y_i); - - RESMULT_madd_252 : MAJ3 - port map(A => \a6_b[6]\, B => \a5_b[7]\, C => \a_i4_b[8]\, - Y => N_110); - - RESMULT_madd_472 : MAJ3 - port map(A => \a14_b[4]\, B => \a12_b[6]\, C => \a13_b[5]\, - Y => N_204); - - RESMULT_madd_67 : NOR3B - port map(A => N_17, B => N_25, C => N_10, Y => N_30); - - RESMULT_madd_95_0 : XNOR3 - port map(A => \a6_b[2]\, B => \a8_b[0]\, C => \a7_b[1]\, Y - => N_43); - - \REG[18]\ : DFN1E1C0 - port map(D => \RESMULT[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(18)); - - RESMULT_madd_568_4 : XOR3 - port map(A => \a_i13_b[8]\, B => \a14_b[7]\, C => N_228, Y - => N_239_i); - - \RESMULT_a1_b[6]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(6), Y => - \a1_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I197_Y_0 : AX1A - port map(A => N411, B => I132_un1_Y_i, C => - ADD_22x22_fast_I197_Y_0_0, Y => \RESMULT[12]\); - - RESMULT_madd_572 : AO18 - port map(A => N_234, B => N_241, C => N_239_i, Y => N_244); - - \RESMULT_a7_b[0]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(0), Y => - \a7_b[0]\); - - RESMULT_madd_88_4 : XOR2 - port map(A => madd_88_4_0, B => \a3_b[4]\, Y => N_33_i); - - RESMULT_madd_72 : MAJ3 - port map(A => \a7_b[0]\, B => \a5_b[2]\, C => \a6_b[1]\, Y - => N_32_i); - - RESMULT_madd_230 : MAJ3 - port map(A => N_95_i, B => N_80, C => N_82, Y => N_100); - - RESMULT_madd_88_8 : XOR2 - port map(A => madd_88_8_0, B => N_24, Y => N_37); - - RESMULT_madd_606_ADD_22x22_fast_I80_un1_Y : NOR3C - port map(A => N307, B => N310, C => N358, Y => - ADD_22x22_fast_I80_un1_Y); - - RESMULT_madd_458_0_0 : XNOR3 - port map(A => N_180, B => madd_458_14_0, C => N_195, Y => - madd_458_0_0); - - RESMULT_madd_66_0 : AX1 - port map(A => N_10, B => N_17, C => N_25, Y => N_29); - - RESMULT_madd_606_ADD_22x22_fast_I204_Y_0 : XOR3 - port map(A => N_225, B => N_214, C => N544, Y => - \RESMULT[19]\); - - RESMULT_madd_231_12 : XNOR3 - port map(A => N_82, B => N_95_i, C => N_80, Y => N_99); - - RESMULT_madd_194_4 : XNOR3 - port map(A => \a5_b[5]\, B => \a7_b[3]\, C => \a6_b[4]\, Y - => N_75); - - RESMULT_madd_458_2 : XOR2 - port map(A => madd_458_2_0, B => \a17_b_i[0]\, Y => N_185); - - \RESMULT_a_i13_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(13), Y => - \a_i13_b[8]\); - - \REG[19]\ : DFN1E1C0 - port map(D => \RESMULT[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(19)); - - \RESMULT_a6_b[0]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(0), Y => - \a6_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I34_Y : AO13 - port map(A => N312, B => N_225, C => N_214, Y => N350); - - RESMULT_madd_606_ADD_22x22_fast_I5_P0N : OR2 - port map(A => N_87, B => N_72, Y => N289); - - RESMULT_madd_606_ADD_22x22_fast_I197_Y_0_0 : XOR2 - port map(A => N_104, B => N_119, Y => - ADD_22x22_fast_I197_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I83_Y : OR2A - port map(A => N361, B => N357, Y => N402); - - RESMULT_madd_537 : MAJ3 - port map(A => \a14_b[6]\, B => \a13_b[7]\, C => - \a_i12_b[8]\, Y => N_230_i); - - RESMULT_madd_606_ADD_22x22_fast_I152_Y_0 : AO1 - port map(A => N403, B => N396, C => N395, Y => - ADD_22x22_fast_I152_Y_0); - - \RESMULT_a13_b[2]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(2), Y => - \a13_b[2]\); - - RESMULT_madd_416_4 : XNOR3 - port map(A => \a11_b[5]\, B => \a13_b[3]\, C => \a12_b[4]\, - Y => N_171); - - RESMULT_madd_606_ADD_22x22_fast_I42_Y : MAJ3 - port map(A => N_152, B => N_167, C => N300, Y => N358); - - RESMULT_madd_606_ADD_22x22_fast_I16_G0N : NOR2A - port map(A => N_243, B => N_236, Y => N321); - - \RESMULT_a_i0_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(0), Y => - \a_i0_b[8]\); - - RESMULT_madd_437 : MAJ3 - port map(A => \a12_b[5]\, B => \a10_b[7]\, C => \a11_b[6]\, - Y => N_190); - - RESMULT_madd_606_ADD_22x22_fast_I100_Y : AO1 - port map(A => N378, B => N375, C => N374, Y => N419); - - RESMULT_madd_606_ADD_22x22_fast_I199_Y_0_0 : XNOR3 - port map(A => N_134, B => N_149, C => N_136, Y => - ADD_22x22_fast_I199_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I98_Y : AO1 - port map(A => N376, B => N373, C => N372, Y => N417); - - \RESMULT_a4_b[7]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(7), Y => - \a4_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I9_P0N : XO1A - port map(A => N_134, B => N_149, C => N_136, Y => N301); - - RESMULT_madd_304 : MAJ3 - port map(A => N_127_i, B => N_112, C => N_114, Y => N_132); - - \RESMULT_a_i9_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(9), Y => - \a_i9_b[8]\); - - \REG[1]\ : DFN1E1C0 - port map(D => \RESMULT[1]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult_0, Q => MULTout(1)); - - \RESMULT_a5_b[1]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(1), Y => - \a5_b[1]\); - - \RESMULT_a1_b[7]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(7), Y => - \a1_b[7]\); - - \RESMULT_a1_b[4]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(4), Y => - \a1_b[4]\); - - RESMULT_madd_476 : NOR2B - port map(A => \a_i10_b[8]\, B => N_186_1, Y => madd_271); - - RESMULT_madd_39_2_0 : XOR2 - port map(A => \a5_b[0]\, B => \a3_b[2]\, Y => madd_39_2_0); - - RESMULT_madd_119_m6 : AO18 - port map(A => N_45, B => madd_115_0_0_1, C => madd_119_N_4, - Y => madd_119_m6); - - RESMULT_madd_606_ADD_22x22_fast_I133_un1_Y : OR3B - port map(A => N373, B => N421, C => N369, Y => I133_un1_Y_i); - - RESMULT_madd_583_0 : XOR3 - port map(A => N_240_i, B => N_247, C => N_242, Y => N_249); - - RESMULT_madd_18 : MAJ3 - port map(A => \a4_b[0]\, B => \a2_b[2]\, C => \a3_b[1]\, Y - => N_8); - - \RESMULT_a9_b[7]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(7), Y => - \a9_b[7]\); - - RESMULT_madd_492 : MAJ3 - port map(A => N_205, B => N_196, C => N_207, Y => N_212); - - \RESMULT_a0_b[5]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(5), Y => - \a0_b[5]\); - - \RESMULT_a2_b[4]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(4), Y => - \a2_b[4]\); - - RESMULT_madd_462_0 : NOR2B - port map(A => madd_462_0_tz, B => N_195, Y => madd_462_0); - - RESMULT_madd_272 : AO13 - port map(A => N_100, B => N_113_i, C => N_115, Y => N_118); - - \RESMULT_a9_b[5]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(5), Y => - \a9_b[5]\); - - RESMULT_madd_225 : AO18 - port map(A => N_93, B => N_89_i, C => N_91, Y => N_98); - - RESMULT_madd_606_ADD_22x22_fast_I194_Y_0 : AX1A - port map(A => N417, B => I135_un1_Y_i, C => - ADD_22x22_fast_I194_Y_0_0, Y => \RESMULT[9]\); - - RESMULT_madd_592 : MAJ3 - port map(A => \a_i15_b[8]\, B => \a16_b[7]\, C => - \a17_b_i[6]\, Y => N_252); - - RESMULT_madd_458_7 : XOR3 - port map(A => \a10_b[7]\, B => \a12_b[5]\, C => \a11_b[6]\, - Y => N_189_i); - - \RESMULT_a10_b[4]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(4), Y => - \a10_b[4]\); - - \RESMULT_a0_b[7]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(7), Y => - \a0_b[7]\); - - RESMULT_madd_588_0 : XNOR3 - port map(A => \a16_b[7]\, B => \a_i15_b[8]\, C => - \a17_b_i[6]\, Y => N_251); - - \RESMULT_a15_b[1]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(1), Y => - \a15_b[1]\); - - \RESMULT_a0_b[8]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(8), Y => - \a0_b[8]\); - - RESMULT_madd_24_4 : XNOR2 - port map(A => madd_24_4_0, B => N_4, Y => N_9); - - RESMULT_madd_606_ADD_22x22_fast_I198_Y_0 : AX1A - port map(A => N455, B => I159_un1_Y_i, C => - ADD_22x22_fast_I198_Y_0_0, Y => \RESMULT[13]\); - - \REG[15]\ : DFN1E1C0 - port map(D => \RESMULT[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(15)); - - RESMULT_madd_124_m2 : XOR2 - port map(A => N_37, B => N_35, Y => madd_88_0_0); - - \RESMULT_a_i5_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(5), Y => - \a_i5_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I134_Y : OR2 - port map(A => N415, B => I134_un1_Y, Y => N461); - - RESMULT_madd_606_ADD_22x22_fast_I8_P0N : XO1A - port map(A => N_118, B => N_133, C => N_120, Y => N298); - - \REG[3]\ : DFN1E1C0 - port map(D => \RESMULT[3]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(3)); - - RESMULT_madd_606_ADD_22x22_fast_I80_Y : OR2 - port map(A => ADD_22x22_fast_I80_un1_Y, B => N354, Y => - N399); - - RESMULT_madd_606_ADD_22x22_fast_I52_Y : MAJ3 - port map(A => N_72, B => N_87, C => N285, Y => N368); - - RESMULT_madd_606_ADD_22x22_fast_I27_Y : OA1 - port map(A => N_250, B => N_253, C => N325, Y => N343); - - \RESMULT_a_i12_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(12), Y => - \a_i12_b[8]\); - - RESMULT_madd_273_0 : XOR3 - port map(A => N_100, B => madd_268_0_0, C => N_102, Y => - N_119); - - \RESMULT_a10_b[6]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(6), Y => - \a10_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I71_Y : NOR2 - port map(A => N349, B => N345, Y => N390); - - RESMULT_madd_61_2 : XOR2 - port map(A => madd_61_2_0, B => \a4_b[2]\, Y => N_21_i); - - RESMULT_madd_606_ADD_22x22_fast_I199_Y_0 : AX1D - port map(A => I158_un1_Y, B => N453, C => - ADD_22x22_fast_I199_Y_0_0, Y => \RESMULT[14]\); - - \RESMULT_a6_b[5]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(5), Y => - \a6_b[5]\); - - RESMULT_madd_305_2 : XOR3 - port map(A => \a11_b[2]\, B => \a13_b[0]\, C => \a12_b[1]\, - Y => N_121_i); - - \RESMULT_a15_b[3]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(3), Y => - \a15_b[3]\); - - \RESMULT_a3_b[6]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(6), Y => - \a3_b[6]\); - - RESMULT_madd_342_2 : XOR3 - port map(A => \a12_b[2]\, B => \a14_b[0]\, C => \a13_b[1]\, - Y => N_137_i); - - \RESMULT_a5_b[6]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(6), Y => - \a5_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_2 : NOR3C - port map(A => I112_un1_Y, B => ADD_22x22_fast_I172_Y_0, C - => I148_un1_Y, Y => ADD_22x22_fast_I172_Y_2); - - RESMULT_madd_331 : MAJ3 - port map(A => N_122_i, B => N_124, C => N_126, Y => N_144); - - RESMULT_madd_606_ADD_22x22_fast_I5_G0N : NOR2B - port map(A => N_87, B => N_72, Y => N288); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_3 : OR3C - port map(A => N398, B => N390, C => - ADD_22x22_fast_I171_Y_3_tz, Y => ADD_22x22_fast_I171_Y_3); - - RESMULT_madd_606_ADD_22x22_fast_I155_Y_0 : NOR3C - port map(A => I82_un1_Y, B => N356, C => I155_un1_Y_i, Y - => ADD_22x22_fast_I155_Y_0); - - RESMULT_madd_410 : AO18 - port map(A => N_173, B => N_169_i, C => N_171, Y => N_178); - - RESMULT_madd_220 : MAJ3 - port map(A => N_74_i, B => N_76, C => N_78, Y => N_96); - - RESMULT_madd_24_0 : XNOR2 - port map(A => madd_24_0_0, B => N_6, Y => N_11_i); - - RESMULT_madd_606_ADD_22x22_fast_I6_G0N : XA1 - port map(A => N_86, B => N_101, C => N_88, Y => N291); - - RESMULT_madd_416_10 : XOR3 - port map(A => N_156, B => N_154_i, C => N_158, Y => - N_175_i_0); - - \RESMULT_a6_b[6]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(6), Y => - \a6_b[6]\); - - RESMULT_madd_363 : MAJ3 - port map(A => \a9_b[6]\, B => \a8_b[7]\, C => \a_i7_b[8]\, - Y => N_158); - - \RESMULT_a17_b_i[3]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(3), Y => - \a17_b_i[3]\); - - \RESMULT_a8_b[2]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(2), Y => - \a8_b[2]\); - - RESMULT_madd_268_2 : XOR2 - port map(A => madd_268_2_0, B => \a11_b[1]\, Y => N_105_i); - - RESMULT_madd_606_ADD_22x22_fast_I62_Y : AO1 - port map(A => N274, B => N_12, C => N273, Y => N378); - - \REG[10]\ : DFN1E1C0 - port map(D => \RESMULT[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(10)); - - RESMULT_madd_606_ADD_22x22_fast_I135_un1_Y : OR2B - port map(A => N418, B => N_12, Y => I135_un1_Y_i); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_3_tz : OR2 - port map(A => N449, B => ADD_22x22_fast_I170_un1_Y_0, Y => - ADD_22x22_fast_I170_Y_3_tz); - - RESMULT_madd_194_0 : XNOR3 - port map(A => N_83, B => N_81, C => N_68, Y => N_85); - - RESMULT_madd_606_ADD_22x22_fast_I81_Y : OR3C - port map(A => N307, B => N310, C => N359, Y => N400); - - \RESMULT_a11_b[6]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(6), Y => - \a11_b[6]\); - - \REG[12]\ : DFN1E1C0 - port map(D => \RESMULT[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(12)); - - \RESMULT_a11_b[3]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(3), Y => - \a11_b[3]\); - - RESMULT_madd_55 : MAJ3 - port map(A => \a3_b[3]\, B => \a1_b[5]\, C => \a2_b[4]\, Y - => N_24); - - \RESMULT_a_i4_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(4), Y => - \a_i4_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I6_P0N : XO1 - port map(A => N_86, B => N_101, C => N_88, Y => N292); - - RESMULT_madd_567 : AO13 - port map(A => N_232, B => N_230_i, C => N_237, Y => N_242); - - RESMULT_madd_421_0 : XOR3 - port map(A => N_179, B => madd_416_0_0, C => N_166, Y => - N_183); - - \RESMULT_a_i11_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(11), Y => - \a_i11_b[8]\); - - RESMULT_madd_342_12 : XNOR3 - port map(A => N_130, B => N_143_i, C => N_128, Y => N_147); - - RESMULT_madd_467 : MAJ3 - port map(A => \a15_b[3]\, B => \a16_b[2]\, C => - \a17_b_i[1]\, Y => N_202); - - RESMULT_madd_383 : AO13 - port map(A => N_148, B => N_161_i, C => N_163, Y => N_166); - - RESMULT_madd_606_ADD_22x22_fast_I170_un1_Y_0 : NOR3C - port map(A => N404, B => N412, C => N419, Y => - ADD_22x22_fast_I170_un1_Y_0); - - RESMULT_madd_379_0 : XOR3 - port map(A => N_163, B => N_161_i, C => N_148, Y => N_165); - - RESMULT_madd_606_ADD_22x22_fast_I46_Y : AO1 - port map(A => N298, B => N294, C => N297, Y => N362); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_1 : AOI1B - port map(A => N346, B => N343, C => ADD_22x22_fast_I170_Y_0, - Y => ADD_22x22_fast_I170_Y_1); - - RESMULT_madd_606_ADD_22x22_fast_I157_un1_Y_0 : NOR3B - port map(A => N373, B => N421, C => N369, Y => - ADD_22x22_fast_I157_un1_Y_0); - - \REG[11]\ : DFN1E1C0 - port map(D => \RESMULT[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(11)); - - RESMULT_madd_587 : AO18 - port map(A => N_242, B => N_247, C => N_240_i, Y => N_250); - - GND_i : GND - port map(Y => \GND\); - - \RESMULT_a7_b[3]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(3), Y => - \a7_b[3]\); - - \RESMULT_a8_b[6]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(6), Y => - \a8_b[6]\); - - \RESMULT_a3_b[3]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(3), Y => - \a3_b[3]\); - - RESMULT_madd_231_10 : XOR3 - port map(A => N_76, B => N_74_i, C => N_78, Y => N_95_i); - - RESMULT_madd_157_4 : XOR3 - port map(A => \a5_b[4]\, B => \a6_b[3]\, C => \a4_b[5]\, Y - => N_59_i); - - RESMULT_madd_487 : MAJ3 - port map(A => N_203_i, B => N_192, C => N_194, Y => N_210); - - RESMULT_madd_157_9 : XNOR3 - port map(A => N_44, B => \a_i0_b[8]\, C => N_46, Y => N_63); - - RESMULT_madd_606_ADD_22x22_fast_I206_Y_0_0 : XNOR2 - port map(A => N_243, B => N_236, Y => - ADD_22x22_fast_I206_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I126_un1_Y : NOR3B - port map(A => N361, B => N413, C => N365, Y => I126_un1_Y); - - RESMULT_madd_547 : AO13 - port map(A => N_220, B => N_229_i, C => N_231, Y => N_234); - - \RESMULT_a5_b[7]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(7), Y => - \a5_b[7]\); - - \REG[20]\ : DFN1E1C0 - port map(D => \RESMULT[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(20)); - - RESMULT_madd_606_ADD_22x22_fast_I70_un1_Y : AO1D - port map(A => N318, B => ADD_22x22_fast_I32_un1_Y, C => - N345, Y => I70_un1_Y); - - RESMULT_madd_60 : AO18 - port map(A => N_16, B => \a0_b[6]\, C => N_14, Y => N_26); - - \RESMULT_a10_b[0]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(0), Y => - \a10_b[0]\); - - \REG[22]\ : DFN1E1C0 - port map(D => \RESMULT[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult, Q => MULTout(22)); - - RESMULT_madd_447 : MIN3 - port map(A => N_187, B => N_174, C => N_185, Y => N_194); - - RESMULT_madd_502 : MIN3 - port map(A => \a15_b[4]\, B => \a16_b[3]\, C => - \a17_b_i[2]\, Y => N_216); - - \RESMULT_a17_b_i[0]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(0), Y => - \a17_b_i[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I92_Y : OR2 - port map(A => N366, B => I92_un1_Y, Y => N411); - - RESMULT_madd_606_ADD_22x22_fast_I205_Y_0_0 : AX1B - port map(A => madd_301, B => madd_527_0, C => N_235, Y => - ADD_22x22_fast_I205_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I84_Y : AO1 - port map(A => N362, B => N359, C => N358, Y => N403); - - RESMULT_madd_194_12 : XOR3 - port map(A => N_79, B => N_64_i, C => N_66, Y => N_83); - - \RESMULT_a15_b[0]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(0), Y => - \a15_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I190_Y_0 : XOR2 - port map(A => ADD_22x22_fast_I190_Y_0_0, B => N_12, Y => - \RESMULT[5]\); - - \RESMULT_a14_b[0]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(0), Y => - \a14_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I201_Y_0 : AX1A - port map(A => N449, B => I156_un1_Y_i, C => - ADD_22x22_fast_I201_Y_0_0, Y => \RESMULT[16]\); - - RESMULT_madd_606_ADD_22x22_fast_I155_un1_Y_0 : OA1A - port map(A => I135_un1_Y_i, B => N417, C => N410, Y => - ADD_22x22_fast_I155_un1_Y_0); - - \REG[8]\ : DFN1E1C0 - port map(D => \RESMULT[8]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(8)); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_0 : OA1C - port map(A => N350, B => N347, C => N346, Y => - ADD_22x22_fast_I172_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I11_G0N : NOR3B - port map(A => N_165, B => N_183, C => N_150, Y => N306); - - \RESMULT_a16_b[3]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(3), Y => - \a16_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I153_Y : NOR3 - port map(A => I118_un1_Y, B => N397, C => I153_un1_Y, Y => - N544); - - RESMULT_madd_606_ADD_22x22_fast_I191_Y_0 : XOR3 - port map(A => N_29, B => N_27, C => N378, Y => \RESMULT[6]\); - - \RESMULT_a5_b[3]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(3), Y => - \a5_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I38_Y : AO1 - port map(A => N310, B => N306, C => N309, Y => N354); - - RESMULT_madd_606_ADD_22x22_fast_I35_Y : NOR2B - port map(A => N316, B => N313, Y => N351); - - RESMULT_madd_274 : XA1 - port map(A => N_100, B => madd_268_0_0, C => N_102, Y => - N_120); - - RESMULT_madd_606_ADD_22x22_fast_I56_Y : MAJ3 - port map(A => N_53, B => N_55, C => N279, Y => N372); - - RESMULT_madd_279 : MAJ3 - port map(A => \a13_b[0]\, B => \a11_b[2]\, C => \a12_b[1]\, - Y => N_122_i); - - RESMULT_madd_606_ADD_22x22_fast_I10_G0N : NOR2B - port map(A => N_167, B => N_152, Y => N303); - - \REG[21]\ : DFN1E1C0 - port map(D => \RESMULT[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult, Q => MULTout(21)); - - RESMULT_madd_606_ADD_22x22_fast_I15_G0N : OA1 - port map(A => madd_301, B => madd_527_0, C => N_235, Y => - N318); - - RESMULT_madd_493_12 : XOR3 - port map(A => N_207, B => N_205, C => N_196, Y => N_211); - - RESMULT_madd_321 : MIN3 - port map(A => \a11_b[3]\, B => \a9_b[5]\, C => \a10_b[4]\, - Y => N_140); - - RESMULT_madd_342_7 : XNOR3 - port map(A => \a_i6_b[8]\, B => \a8_b[6]\, C => \a7_b[7]\, - Y => N_141); - - RESMULT_madd_432 : MAJ3 - port map(A => \a15_b[2]\, B => \a13_b[4]\, C => \a14_b[3]\, - Y => N_188_i); - - RESMULT_madd_268_7 : XNOR2 - port map(A => madd_268_7_0, B => \a_i4_b[8]\, Y => N_109); - - \REG[16]\ : DFN1E1C0 - port map(D => \RESMULT[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(16)); - - RESMULT_madd_23 : MAJ3 - port map(A => \a1_b[3]\, B => N_4, C => \a0_b[4]\, Y => - N_10); - - \RESMULT_a14_b[4]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(4), Y => - \a14_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I82_un1_Y : OR2 - port map(A => N360, B => N357, Y => I82_un1_Y); - - RESMULT_madd_532 : MIN3 - port map(A => \a15_b[5]\, B => \a16_b[4]\, C => - \a17_b_i[3]\, Y => N_228); - - RESMULT_madd_24_2 : XOR2 - port map(A => madd_24_2_0, B => \a3_b[1]\, Y => N_7_i); - - \RESMULT_a16_b[4]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(4), Y => - \a16_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I79_Y : NOR2 - port map(A => N357, B => N353, Y => N398); - - RESMULT_madd_606_ADD_22x22_fast_I17_P0N : OR2 - port map(A => N_249, B => N_244, Y => N325); - - RESMULT_madd_305_12 : XNOR3 - port map(A => N_114, B => N_127_i, C => N_112, Y => N_131); - - RESMULT_madd_543_4 : XOR3 - port map(A => \a13_b[7]\, B => \a14_b[6]\, C => - \a_i12_b[8]\, Y => N_229_i); - - \RESMULT_a14_b[3]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(3), Y => - \a14_b[3]\); - - \RESMULT_a_i6_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(6), Y => - \a_i6_b[8]\); - - \REG[4]\ : DFN1E1C0 - port map(D => \RESMULT[4]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(4)); - - \REG[13]\ : DFN1E1C0 - port map(D => \RESMULT[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(13)); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0 : AX1E - port map(A => ADD_22x22_fast_I170_Y_3, B => - ADD_22x22_fast_I170_Y_2, C => ADD_22x22_fast_I209_Y_0_2, - Y => \RESMULT[24]\); - - RESMULT_madd_336 : AO18 - port map(A => N_141, B => N_137_i, C => N_139, Y => N_146); - - RESMULT_madd_215 : MAJ3 - port map(A => \a5_b[6]\, B => \a4_b[7]\, C => \a_i3_b[8]\, - Y => N_94); - - RESMULT_madd_416_2 : XOR3 - port map(A => \a15_b[1]\, B => \a16_b[0]\, C => \a14_b[2]\, - Y => N_169_i); - - RESMULT_madd_606_ADD_22x22_fast_I32_un1_Y : NOR3B - port map(A => N_225, B => N319, C => N_214, Y => - ADD_22x22_fast_I32_un1_Y); - - RESMULT_madd_44_0 : XNOR2 - port map(A => N_17, B => N_10, Y => N_19); - - \RESMULT_a16_b[2]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(2), Y => - \a16_b[2]\); - - RESMULT_madd_341 : MAJ3 - port map(A => N_143_i, B => N_128, C => N_130, Y => N_148); - - \RESMULT_a17_b_i[5]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(5), Y => - \a17_b_i[5]\); - - RESMULT_madd_568_2 : XOR3 - port map(A => \a16_b[5]\, B => \a15_b[6]\, C => - \a17_b_i[4]\, Y => N_237); - - \RESMULT_a7_b[6]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(6), Y => - \a7_b[6]\); - - RESMULT_madd_305_7 : XNOR3 - port map(A => \a6_b[7]\, B => \a7_b[6]\, C => \a_i5_b[8]\, - Y => N_125); - - RESMULT_madd_606_ADD_22x22_fast_I0_P0N : AO1D - port map(A => CO2, B => N_11_i, C => N_19, Y => N274); - - RESMULT_madd_606_ADD_22x22_fast_I2_G0N : XA1A - port map(A => N_28, B => N_39, C => N_30, Y => N279); - - RESMULT_madd_606_ADD_22x22_fast_I89_Y : NOR3C - port map(A => N289, B => N292, C => N363, Y => N408); - - RESMULT_madd_493_6_0 : AX1C - port map(A => alu_coef_s(7), B => alu_sample(11), C => - \a_i10_b[8]\, Y => madd_493_6_0); - - RESMULT_madd_384_0 : XNOR2 - port map(A => N_165, B => N_150, Y => N_167); - - RESMULT_madd_305_0 : XOR3 - port map(A => N_131, B => N_129_i, C => N_116, Y => N_133); - - RESMULT_madd_294 : MAJ3 - port map(A => N_106_i, B => N_108, C => N_110, Y => N_128); - - RESMULT_madd_231_8 : XNOR3 - port map(A => N_91, B => N_89_i, C => N_93, Y => N_97); - - RESMULT_madd_268_2_0 : XOR2 - port map(A => \a12_b[0]\, B => \a10_b[2]\, Y => - madd_268_2_0); - - RESMULT_madd_299 : AO18 - port map(A => N_125, B => N_121_i, C => N_123, Y => N_130); - - RESMULT_madd_368 : AO18 - port map(A => N_142, B => N_138_i, C => N_140, Y => N_160); - - \RESMULT_a11_b[1]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(1), Y => - \a11_b[1]\); - - \REG[7]\ : DFN1E1C0 - port map(D => \RESMULT[7]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(7)); - - RESMULT_madd_24_4_0 : XOR2 - port map(A => \a1_b[3]\, B => \a0_b[4]\, Y => madd_24_4_0); - - RESMULT_madd_606_ADD_22x22_fast_I154_Y_0 : OR2 - port map(A => I120_un1_Y, B => N399, Y => - ADD_22x22_fast_I154_Y_0); - - \RESMULT_a5_b[2]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(2), Y => - \a5_b[2]\); - - RESMULT_madd_405 : MAJ3 - port map(A => N_154_i, B => N_156, C => N_158, Y => N_176); - - \RESMULT_a1_b[5]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(5), Y => - \a1_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_un1_Y : OR3A - port map(A => ADD_22x22_fast_I172_un1_Y_0, B => N392, C => - N400, Y => I172_un1_Y); - - \REG[23]\ : DFN1E1C0 - port map(D => \RESMULT[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult, Q => MULTout(23)); - - RESMULT_madd_606_ADD_22x22_fast_I10_P0N : OR2 - port map(A => N_167, B => N_152, Y => N304); - - RESMULT_madd_210 : MAJ3 - port map(A => \a8_b[3]\, B => \a6_b[5]\, C => \a7_b[4]\, Y - => N_92); - - RESMULT_madd_114 : AO13 - port map(A => N_34, B => N_32_i, C => N_43, Y => N_50); - - \RESMULT_a12_b[0]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(0), Y => - \a12_b[0]\); - - \RESMULT_a_i15_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(15), Y => - \a_i15_b[8]\); - - \RESMULT_a7_b[5]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(5), Y => - \a7_b[5]\); - - RESMULT_madd_379_10 : XOR3 - port map(A => N_142, B => N_138_i, C => N_140, Y => N_159_i); - - RESMULT_madd_39_4 : XOR3 - port map(A => \a0_b[5]\, B => \a2_b[3]\, C => \a1_b[4]\, Y - => N_15_i); - - \REG[0]\ : DFN1E1C0 - port map(D => \RESMULT[0]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult_0, Q => MULTout(0)); - - RESMULT_madd_606_ADD_22x22_fast_I153_un1_Y_0 : NOR3B - port map(A => N361, B => N398, C => N365, Y => - ADD_22x22_fast_I153_un1_Y_0); - - RESMULT_madd_458_9 : XNOR3 - port map(A => N_170, B => \a_i9_b[8]\, C => N_172, Y => - N_191); - - RESMULT_madd_606_ADD_22x22_fast_I101_Y : OR2 - port map(A => N376, B => I101_un1_Y, Y => N421); - - RESMULT_madd_157_11 : XNOR3 - port map(A => N_57, B => N_59_i, C => N_48, Y => N_65_i); - - \REG[5]\ : DFN1E1C0 - port map(D => \RESMULT[5]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(5)); - - RESMULT_madd_606_ADD_22x22_fast_I114_un1_Y_0 : OR2 - port map(A => N353, B => N349, Y => ADD_22x22_fast_I115_Y_0); - - RESMULT_madd_125_0 : AX1 - port map(A => N_28, B => N_39, C => N_51, Y => N_55); - - \RESMULT_a8_b[1]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(1), Y => - \a8_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I96_Y : AO1 - port map(A => N374, B => N371, C => N370, Y => N415); - - RESMULT_madd_124tt_m3 : AO13 - port map(A => N_16, B => N_14, C => \a0_b[6]\, Y => - madd_124tt_m3); - - RESMULT_madd_493_8 : XOR3 - port map(A => N_188_i, B => N_201, C => N_190, Y => N_207); - - \RESMULT_a12_b[6]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(6), Y => - \a12_b[6]\); - - RESMULT_madd_348 : NOR2A - port map(A => N_149, B => N_134, Y => N_152); - - RESMULT_madd_517 : MAJ3 - port map(A => N_215, B => N_206, C => N_217, Y => N_222); - - RESMULT_madd_606_ADD_22x22_fast_I207_Y_0_0 : XOR2 - port map(A => N_249, B => N_244, Y => - ADD_22x22_fast_I207_Y_0_0); - - \RESMULT_a12_b[7]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(7), Y => - \a12_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_2 : NOR3C - port map(A => ADD_22x22_fast_I114_un1_Y, B => - ADD_22x22_fast_I173_Y_0, C => I173_un1_Y_i, Y => - ADD_22x22_fast_I173_Y_2); - - \RESMULT_a12_b[3]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(3), Y => - \a12_b[3]\); - - RESMULT_madd_88_2 : XNOR3 - port map(A => \a5_b[2]\, B => \a7_b[0]\, C => \a6_b[1]\, Y - => N_31); - - RESMULT_madd_523_7 : XNOR3 - port map(A => N_204, B => \a_i11_b[8]\, C => N_202, Y => - N_219); - - RESMULT_madd_422 : XO1 - port map(A => N_179, B => madd_416_0_0, C => N_166, Y => - N_184); - - RESMULT_madd_606_ADD_22x22_fast_I198_Y_0_0 : XNOR3 - port map(A => N_118, B => N_133, C => N_120, Y => - ADD_22x22_fast_I198_Y_0_0); - - RESMULT_madd_523_4_0 : XOR2 - port map(A => \a14_b[5]\, B => \a12_b[7]\, Y => - madd_523_4_0); - - \RESMULT_a4_b[5]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(5), Y => - \a4_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I47_Y : NOR2B - port map(A => N298, B => N295, Y => N363); - - RESMULT_madd_606_ADD_22x22_fast_I110_un1_Y : OR2B - port map(A => N397, B => N390, Y => I110_un1_Y); - - RESMULT_madd_548_0_0 : XOR2 - port map(A => N_222, B => N_233, Y => madd_548_0_0); - - RESMULT_madd_157_0 : XOR3 - port map(A => madd_119_m6, B => N_65_i, C => N_67, Y => - N_69); - - RESMULT_madd_606_ADD_22x22_fast_I78_Y : OAI1 - port map(A => N353, B => N356, C => N352, Y => N397); - - RESMULT_madd_522 : OR2 - port map(A => madd_522_0, B => madd_298, Y => N_224); - - RESMULT_madd_305_8 : XOR3 - port map(A => N_125, B => N_121_i, C => N_123, Y => N_129_i); - - RESMULT_madd_562 : MAJ3 - port map(A => \a14_b[7]\, B => N_228, C => \a_i13_b[8]\, Y - => N_240_i); - - \REG[14]\ : DFN1E1C0 - port map(D => \RESMULT[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(14)); - - \RESMULT_a2_b[6]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(6), Y => - \a2_b[6]\); - - \RESMULT_a0_b[1]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(1), Y => - \a0_b[1]\); - - \RESMULT_a12_b[2]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(2), Y => - \a12_b[2]\); - - RESMULT_madd_157_7 : XOR3 - port map(A => \a3_b[6]\, B => \a2_b[7]\, C => \a_i1_b[8]\, - Y => N_61_i); - - RESMULT_madd_606_ADD_22x22_fast_I11_P0N : AO1A - port map(A => N_150, B => N_165, C => N_183, Y => N307); - - RESMULT_madd_1_605_SUM3_0 : XOR2 - port map(A => CO2, B => N_11_i, Y => \RESMULT[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I157_un1_Y : OR3B - port map(A => N361, B => ADD_22x22_fast_I157_un1_Y_0, C => - N365, Y => I157_un1_Y); - - RESMULT_madd_178 : MAJ3 - port map(A => \a4_b[6]\, B => \a3_b[7]\, C => \a_i2_b[8]\, - Y => N_78); - - RESMULT_madd_326 : MIN3 - port map(A => \a8_b[6]\, B => \a7_b[7]\, C => \a_i6_b[8]\, - Y => N_142); - - RESMULT_madd_482 : AO18 - port map(A => N_190, B => N_201, C => N_188_i, Y => N_208); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_3_tz : OR2B - port map(A => N451, B => ADD_22x22_fast_I171_un1_Y_0, Y => - ADD_22x22_fast_I171_Y_3_tz); - - RESMULT_madd_28 : AO18 - port map(A => N_6, B => N_9, C => N_7_i, Y => N_12); - - RESMULT_madd_606_ADD_22x22_fast_I150_un1_Y : OR3A - port map(A => N455, B => ADD_22x22_fast_I115_Y_0, C => N402, - Y => I150_un1_Y); - - RESMULT_madd_582 : AO13 - port map(A => N_238, B => \a_i14_b[8]\, C => N_245, Y => - N_248); - - RESMULT_madd_543_2 : XNOR3 - port map(A => \a16_b[4]\, B => \a15_b[5]\, C => - \a17_b_i[3]\, Y => N_227_i); - - RESMULT_madd_194_8 : XNOR3 - port map(A => N_77, B => N_73_i, C => N_75, Y => N_81); - - \RESMULT_a17_b_i[1]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(1), Y => - \a17_b_i[1]\); - - \RESMULT_a0_b[4]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(4), Y => - \a0_b[4]\); - - RESMULT_madd_0_s : XOR3 - port map(A => \a0_b[2]\, B => \a2_b[0]\, C => \a1_b[1]\, Y - => N_1_i); - - \RESMULT_a13_b[3]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(3), Y => - \a13_b[3]\); - - RESMULT_madd_442 : MAJ3 - port map(A => \a_i9_b[8]\, B => N_170, C => N_172, Y => - N_192); - - RESMULT_madd_606_ADD_22x22_fast_I90_un1_Y : NOR2A - port map(A => N368, B => N365, Y => I90_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I88_Y : AO1 - port map(A => N366, B => N363, C => N362, Y => N407); - - RESMULT_madd_606_ADD_22x22_fast_I85_Y : NOR2B - port map(A => N363, B => N359, Y => N404); - - RESMULT_madd_542 : MAJ3 - port map(A => N_227_i, B => N_216, C => N_218, Y => N_232); - - RESMULT_madd_522_0_tz_0 : OA1B - port map(A => N_192, B => N_194, C => N_219, Y => - madd_522_0_tz_0); - - RESMULT_madd_606_ADD_22x22_fast_I57_Y : NOR2B - port map(A => N283, B => N280, Y => N373); - - \RESMULT_a4_b[6]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(6), Y => - \a4_b[6]\); - - \RESMULT_a0_b[2]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(2), Y => - \a0_b[2]\); - - RESMULT_madd_157_12 : XOR3 - port map(A => N_63, B => N_61_i, C => N_50, Y => N_67); - - \REG[24]\ : DFN1E1C0 - port map(D => \RESMULT[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult, Q => MULTout(24)); - - RESMULT_madd_606_ADD_22x22_fast_I8_G0N : XA1A - port map(A => N_118, B => N_133, C => N_120, Y => N297); - - RESMULT_madd_199_0 : XNOR2 - port map(A => N_85, B => N_70, Y => N_87); - - RESMULT_madd_50 : MAJ3 - port map(A => \a6_b[0]\, B => \a4_b[2]\, C => \a5_b[1]\, Y - => N_22); - - RESMULT_madd_8 : MAJ3 - port map(A => \a3_b[0]\, B => \a1_b[2]\, C => \a2_b[1]\, Y - => N_4); - - RESMULT_madd_477_0 : NOR3C - port map(A => alu_coef_s(7), B => alu_sample(11), C => - madd_477_0_tz, Y => madd_477_0); - - RESMULT_madd_346 : AO13 - port map(A => N_132, B => N_145_i, C => N_147, Y => N_150); - - RESMULT_madd_262 : AO18 - port map(A => N_109, B => N_105_i, C => N_107, Y => N_114); - - RESMULT_madd_231_7 : XNOR3 - port map(A => \a4_b[7]\, B => \a5_b[6]\, C => \a_i3_b[8]\, - Y => N_93); - - RESMULT_madd_311 : NOR2A - port map(A => N_133, B => N_118, Y => N_136); - - \RESMULT_a3_b[7]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(7), Y => - \a3_b[7]\); - - \RESMULT_a8_b[3]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(3), Y => - \a8_b[3]\); - - RESMULT_madd_173 : MAJ3 - port map(A => \a7_b[3]\, B => \a5_b[5]\, C => \a6_b[4]\, Y - => N_76); - - \RESMULT_a14_b[6]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(6), Y => - \a14_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I4_P0N : XO1 - port map(A => N_69, B => madd_124_m6, C => N_56, Y => N286); - - RESMULT_madd_1_605_SUM2_0 : XOR2 - port map(A => CO1, B => N_5, Y => \RESMULT[3]\); - - RESMULT_madd_194_10 : XNOR3 - port map(A => N_60, B => N_58_i, C => N_62, Y => N_79); - - \RESMULT_a13_b[1]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(1), Y => - \a13_b[1]\); - - \RESMULT_a9_b[2]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(2), Y => - \a9_b[2]\); - - RESMULT_madd_198 : OR2 - port map(A => madd_198_0, B => madd_112, Y => N_86); - - RESMULT_madd_606_ADD_22x22_fast_I201_Y_0_0 : AX1 - port map(A => N_150, B => N_165, C => N_183, Y => - ADD_22x22_fast_I201_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I190_Y_0_0 : AX1B - port map(A => N_11_i, B => CO2, C => N_19, Y => - ADD_22x22_fast_I190_Y_0_0); - - RESMULT_madd_156 : AO13 - port map(A => N_50, B => N_61_i, C => N_63, Y => N_68); - - RESMULT_madd_268_7_0 : XOR2 - port map(A => \a6_b[6]\, B => \a5_b[7]\, Y => madd_268_7_0); - - \RESMULT_a3_b[1]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(1), Y => - \a3_b[1]\); - - RESMULT_madd_268_10 : XOR3 - port map(A => N_92, B => N_90_i, C => N_94, Y => N_111_i); - - RESMULT_madd_342_4 : XNOR3 - port map(A => \a9_b[5]\, B => \a11_b[3]\, C => \a10_b[4]\, - Y => N_139); - - RESMULT_madd_606_ADD_22x22_fast_I7_P0N : OR2 - port map(A => N_119, B => N_104, Y => N295); - - RESMULT_madd_151 : AO13 - port map(A => N_48, B => N_59_i, C => N_57, Y => N_66); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0_0 : AX1A - port map(A => alu_sample(16), B => alu_coef_s(8), C => - \a17_b_i[7]\, Y => ADD_22x22_fast_I209_Y_0_0); - - \RESMULT_a12_b[5]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(5), Y => - \a12_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I206_Y_0 : AX1E - port map(A => I150_un1_Y, B => ADD_22x22_fast_I173_Y_2, C - => ADD_22x22_fast_I206_Y_0_0, Y => \RESMULT[21]\); - - \RESMULT_a17_b_i[4]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(4), Y => - \a17_b_i[4]\); - - RESMULT_madd_234 : NOR2A - port map(A => N_99, B => N_84, Y => madd_133); - - RESMULT_madd_99 : MAJ3 - port map(A => \a8_b[0]\, B => \a6_b[2]\, C => \a7_b[1]\, Y - => N_44); - - RESMULT_madd_425 : NOR3C - port map(A => alu_coef_s(1), B => alu_sample(16), C => - alu_sample(17), Y => madd_240); - - \RESMULT_a16_b[6]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(6), Y => - \a16_b[6]\); - - RESMULT_madd_242 : MAJ3 - port map(A => \a12_b[0]\, B => \a10_b[2]\, C => \a11_b[1]\, - Y => N_106_i); - - \RESMULT_a1_b[3]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(3), Y => - \a1_b[3]\); - - RESMULT_madd_521 : NOR2A - port map(A => N_219, B => N_210, Y => madd_298); - - RESMULT_madd_606_ADD_22x22_fast_I13_G0N : OA1 - port map(A => madd_262, B => madd_462_0, C => N_213, Y => - N312); - - RESMULT_madd_568_6 : XOR3 - port map(A => N_237, B => N_230_i, C => N_232, Y => N_241); - - \RESMULT_a10_b[5]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(5), Y => - \a10_b[5]\); - - RESMULT_madd_124_m6 : MIN3 - port map(A => madd_120_0_0_1, B => madd_124_N_4, C => N_38, - Y => madd_124_m6); - - RESMULT_madd_606_ADD_22x22_fast_I205_Y_0 : AX1B - port map(A => I152_un1_Y, B => ADD_22x22_fast_I152_Y_0, C - => ADD_22x22_fast_I205_Y_0_0, Y => \RESMULT[20]\); - - RESMULT_madd_3 : MAJ3 - port map(A => \a2_b[0]\, B => \a0_b[2]\, C => \a1_b[1]\, Y - => N_2); - - RESMULT_madd_379_4 : XNOR3 - port map(A => \a10_b[5]\, B => \a12_b[3]\, C => \a11_b[4]\, - Y => N_155); - - RESMULT_madd_257 : MAJ3 - port map(A => N_90_i, B => N_92, C => N_94, Y => N_112); - - RESMULT_madd_231_4 : XNOR3 - port map(A => \a6_b[5]\, B => \a8_b[3]\, C => \a7_b[4]\, Y - => N_91); - - RESMULT_madd_115_2 : XNOR3 - port map(A => \a3_b[5]\, B => \a5_b[3]\, C => \a4_b[4]\, Y - => N_45); - - RESMULT_madd_606_ADD_22x22_fast_I14_P0N : OR2A - port map(A => N_214, B => N_225, Y => N316); - - RESMULT_madd_606_ADD_22x22_fast_I200_Y_0 : AX1E - port map(A => I157_un1_Y, B => N451, C => - ADD_22x22_fast_I200_Y_0_0, Y => \RESMULT[15]\); - - \RESMULT_a2_b[1]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(1), Y => - \a2_b[1]\); - - RESMULT_madd_88_7 : XNOR3 - port map(A => \a0_b[7]\, B => \a1_b[6]\, C => N_22, Y => - N_35); - - RESMULT_madd_606_ADD_22x22_fast_I29_Y : AO1C - port map(A => N_243, B => N_236, C => N325, Y => N345); - - RESMULT_madd_606_ADD_22x22_fast_I74_un1_Y : OR2 - port map(A => N352, B => N349, Y => - ADD_22x22_fast_I74_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I43_Y : NOR2B - port map(A => N304, B => N301, Y => N359); - - RESMULT_madd_606_ADD_22x22_fast_I203_Y_0_0 : AX1B - port map(A => madd_262, B => madd_462_0, C => N_213, Y => - ADD_22x22_fast_I203_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I173_un1_Y : OR3A - port map(A => ADD_22x22_fast_I173_un1_Y_0, B => - ADD_22x22_fast_I115_Y_0, C => N402, Y => I173_un1_Y_i); - - RESMULT_madd_523_4 : XNOR2 - port map(A => madd_523_4_0, B => \a13_b[6]\, Y => N_217); - - RESMULT_madd_56_0 : XNOR3 - port map(A => N_14, B => \a0_b[6]\, C => N_16, Y => N_25); - - RESMULT_madd_606_ADD_22x22_fast_I13_P0N : OR3 - port map(A => madd_262, B => N_213, C => madd_462_0, Y => - N313); - - RESMULT_madd_193 : AO13 - port map(A => N_66, B => N_64_i, C => N_79, Y => N_84); - - RESMULT_madd_87 : AO13 - port map(A => N_24, B => N_33_i, C => N_31, Y => N_38); - - \RESMULT_a8_b[5]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(5), Y => - \a8_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I36_Y : AOI1 - port map(A => N313, B => N309, C => N312, Y => N352); - - RESMULT_madd_606_ADD_22x22_fast_I193_Y_0 : XOR3 - port map(A => N_53, B => N_55, C => N419, Y => \RESMULT[8]\); - - RESMULT_madd_1_605_CO2 : OR2B - port map(A => CO1, B => N_5, Y => CO2); - - RESMULT_madd_606_ADD_22x22_fast_I97_Y : NOR2B - port map(A => N375, B => N371, Y => N416); - - \RESMULT_a_i3_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(3), Y => - \a_i3_b[8]\); - - RESMULT_madd_124_m3 : MIN3 - port map(A => N_35, B => madd_124tt_m3, C => N_37, Y => - madd_124_N_4); - - \RESMULT_a16_b[5]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(5), Y => - \a16_b[5]\); - - \RESMULT_a6_b[3]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(3), Y => - \a6_b[3]\); - - \RESMULT_a11_b[2]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(2), Y => - \a11_b[2]\); - - RESMULT_madd_462_0_tz : XO1A - port map(A => N_180, B => madd_458_14_0, C => N_182, Y => - madd_462_0_tz); - - RESMULT_madd_493_2 : XNOR3 - port map(A => \a16_b[2]\, B => \a15_b[3]\, C => - \a17_b_i[1]\, Y => N_201); - - RESMULT_madd_606_ADD_22x22_fast_I130_un1_Y : NOR3A - port map(A => N417, B => N369, C => N365, Y => I130_un1_Y); - - RESMULT_madd_268_0_0 : XOR2 - port map(A => N_113_i, B => N_115, Y => madd_268_0_0); - - \RESMULT_a3_b[5]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(5), Y => - \a3_b[5]\); - - \RESMULT_a2_b[5]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(5), Y => - \a2_b[5]\); - - \RESMULT_a16_b[0]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(0), Y => - \a16_b[0]\); - - RESMULT_madd_457tt_m3 : AO18 - port map(A => N_140, B => N_138_i, C => N_142, Y => - madd_457tt_m3); - - RESMULT_madd_194_2 : XOR3 - port map(A => \a8_b[2]\, B => \a10_b[0]\, C => \a9_b[1]\, Y - => N_73_i); - - RESMULT_madd_457_m6 : MX2C - port map(A => N_191, B => madd_457_N_4, S => madd_458_14_0, - Y => madd_457_m6); - - RESMULT_madd_305_10 : XOR3 - port map(A => N_108, B => N_106_i, C => N_110, Y => N_127_i); - - RESMULT_madd_9_0 : XOR3 - port map(A => N_3, B => \a0_b[3]\, C => N_2, Y => N_5); - - \REG[2]\ : DFN1E1C0 - port map(D => \RESMULT[2]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(2)); - - RESMULT_madd_606_ADD_22x22_fast_I148_un1_Y : OR3A - port map(A => N453, B => N392, C => N400, Y => I148_un1_Y); - - \REG[17]\ : DFN1E1C0 - port map(D => \RESMULT[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(17)); - - RESMULT_madd_606_ADD_22x22_fast_I53_Y : OR2B - port map(A => N289, B => N286, Y => N369); - - RESMULT_madd_268_4 : XNOR3 - port map(A => \a7_b[5]\, B => \a9_b[3]\, C => \a8_b[4]\, Y - => N_107); - - RESMULT_madd_231_2_0 : XOR2 - port map(A => \a11_b[0]\, B => \a9_b[2]\, Y => madd_231_2_0); - - RESMULT_madd_606_ADD_22x22_fast_I195_Y_0_0 : XOR2 - port map(A => N_72, B => N_87, Y => - ADD_22x22_fast_I195_Y_0_0); - - RESMULT_madd_512 : MAJ3 - port map(A => \a_i11_b[8]\, B => N_202, C => N_204, Y => - N_220); - - RESMULT_madd_198_0_tz_0 : AO18 - port map(A => N_61_i, B => N_63, C => N_50, Y => - madd_198_0_tz_0); - - RESMULT_madd_606_ADD_22x22_fast_I40_Y : AOI1 - port map(A => N307, B => N303, C => N306, Y => N356); - - RESMULT_madd_606_ADD_22x22_fast_I202_Y_0 : AX1E - port map(A => I122_un1_Y, B => ADD_22x22_fast_I155_Y_0, C - => ADD_22x22_fast_I202_Y_0_0, Y => \RESMULT[17]\); - - RESMULT_madd_120_0_0_1 : XNOR3 - port map(A => N_32_i, B => N_43, C => N_34, Y => - madd_120_0_0_1); - - RESMULT_madd_115_0 : XOR3 - port map(A => N_45, B => madd_115_0_0_1, C => N_36, Y => - N_51); - - RESMULT_madd_115_0_0_1 : XOR3 - port map(A => \a0_b[8]\, B => \a2_b[6]\, C => \a1_b[7]\, Y - => madd_115_0_0_1); - - RESMULT_madd_493_4 : XOR3 - port map(A => \a12_b[6]\, B => \a14_b[4]\, C => \a13_b[5]\, - Y => N_203_i); - - RESMULT_madd_342_0 : XOR3 - port map(A => N_147, B => N_145_i, C => N_132, Y => N_149); - - RESMULT_madd_416_7 : XNOR3 - port map(A => \a9_b[7]\, B => \a10_b[6]\, C => \a_i8_b[8]\, - Y => N_173); - - RESMULT_madd_458_4 : XNOR3 - port map(A => \a13_b[4]\, B => \a15_b[2]\, C => \a14_b[3]\, - Y => N_187); - - \RESMULT_a9_b[6]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(6), Y => - \a9_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I1_P0N : OR2 - port map(A => N_29, B => N_27, Y => N277); - - \RESMULT_a14_b[2]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(2), Y => - \a14_b[2]\); - - RESMULT_madd_119_m3 : MIN3 - port map(A => \a0_b[7]\, B => madd_119tt_m3, C => \a1_b[6]\, - Y => madd_119_N_4); - - RESMULT_madd_523_10 : XNOR3 - port map(A => N_219, B => N_208, C => N_210, Y => N_223); - - RESMULT_madd_316 : MAJ3 - port map(A => \a14_b[0]\, B => \a12_b[2]\, C => \a13_b[1]\, - Y => N_138_i); - - RESMULT_madd_606_ADD_22x22_fast_I192_Y_0_0 : XNOR3 - port map(A => N_28, B => N_39, C => N_30, Y => - ADD_22x22_fast_I192_Y_0_0); - - RESMULT_madd_88_8_0 : XOR2 - port map(A => N_33_i, B => N_31, Y => madd_88_8_0); - - \RESMULT_a14_b[1]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(1), Y => - \a14_b[1]\); - - \RESMULT_a15_b[6]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(6), Y => - \a15_b[6]\); - - RESMULT_madd_342_8 : XOR3 - port map(A => N_141, B => N_137_i, C => N_139, Y => N_145_i); - - \RESMULT_a13_b[4]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(4), Y => - \a13_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I4_G0N : XA1 - port map(A => N_69, B => madd_124_m6, C => N_56, Y => N285); - - \RESMULT_a_i2_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(2), Y => - \a_i2_b[8]\); - - RESMULT_madd_39_2 : XNOR2 - port map(A => madd_39_2_0, B => \a4_b[1]\, Y => N_13); - - \RESMULT_a6_b[2]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(2), Y => - \a6_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I41_Y : OR2B - port map(A => N307, B => N304, Y => N357); - - RESMULT_madd_606_ADD_22x22_fast_I50_Y : AO1 - port map(A => N292, B => N288, C => N291, Y => N366); - - RESMULT_madd_284 : MAJ3 - port map(A => \a10_b[3]\, B => \a8_b[5]\, C => \a9_b[4]\, Y - => N_124); - - RESMULT_madd_606_ADD_22x22_fast_I152_un1_Y_0 : OA1A - port map(A => I132_un1_Y_i, B => N411, C => N404, Y => - ADD_22x22_fast_I152_un1_Y_0); - - RESMULT_madd_289 : MAJ3 - port map(A => \a7_b[6]\, B => \a6_b[7]\, C => \a_i5_b[8]\, - Y => N_126); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0_2 : XOR3 - port map(A => N_252, B => ADD_22x22_fast_I209_Y_0_0, C => - N_254, Y => ADD_22x22_fast_I209_Y_0_2); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_0 : MIN3 - port map(A => N_250, B => N_253, C => N324, Y => - ADD_22x22_fast_I170_Y_0); - - \RESMULT_a3_b[0]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(0), Y => - \a3_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I171_un1_Y_0 : OR3B - port map(A => N361, B => ADD_22x22_fast_I157_un1_Y_0, C => - N365, Y => ADD_22x22_fast_I171_un1_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_2 : AOI1B - port map(A => N395, B => N388, C => ADD_22x22_fast_I170_Y_1, - Y => ADD_22x22_fast_I170_Y_2); - - \RESMULT_a7_b[1]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(1), Y => - \a7_b[1]\); - - RESMULT_madd_24_2_0 : XOR2 - port map(A => \a2_b[2]\, B => \a4_b[0]\, Y => madd_24_2_0); - - RESMULT_madd_606_ADD_22x22_fast_I92_un1_Y : NOR3C - port map(A => N289, B => N292, C => N370, Y => I92_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I114_un1_Y : AO1 - port map(A => N356, B => I82_un1_Y, C => - ADD_22x22_fast_I115_Y_0, Y => ADD_22x22_fast_I114_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_0 : MIN3 - port map(A => N_244, B => N_249, C => N321, Y => - ADD_22x22_fast_I171_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I124_Y : OR2 - port map(A => N403, B => I124_un1_Y, Y => N449); - - \RESMULT_a0_b[6]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(6), Y => - \a0_b[6]\); - - RESMULT_madd_523_2 : XOR3 - port map(A => \a16_b[3]\, B => \a15_b[4]\, C => - \a17_b_i[2]\, Y => N_215); - - RESMULT_madd_77 : MAJ3 - port map(A => \a4_b[3]\, B => \a2_b[5]\, C => \a3_b[4]\, Y - => N_34); - - RESMULT_madd_606_ADD_22x22_fast_I2_P0N : XO1A - port map(A => N_28, B => N_39, C => N_30, Y => N280); - - RESMULT_madd_157_2 : XNOR3 - port map(A => \a7_b[2]\, B => \a9_b[0]\, C => \a8_b[1]\, Y - => N_57); - - RESMULT_madd_606_ADD_22x22_fast_I120_un1_Y : NOR2A - port map(A => N407, B => N400, Y => I120_un1_Y); - - \RESMULT_a2_b[0]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(0), Y => - \a2_b[0]\); - - RESMULT_madd_379_7 : XNOR3 - port map(A => \a8_b[7]\, B => \a9_b[6]\, C => \a_i7_b[8]\, - Y => N_157); - - \RESMULT_a8_b[4]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(4), Y => - \a8_b[4]\); - - RESMULT_madd_461 : XA1A - port map(A => N_180, B => madd_458_14_0, C => N_182, Y => - madd_262); - - \RESMULT_a2_b[3]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(3), Y => - \a2_b[3]\); - - \RESMULT_a17_b_i[6]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(6), Y => - \a17_b_i[6]\); - - \RESMULT_a12_b[1]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(1), Y => - \a12_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I76_Y : AO1 - port map(A => N354, B => N351, C => N350, Y => N395); - - RESMULT_madd_309 : AO13 - port map(A => N_116, B => N_129_i, C => N_131, Y => N_134); - - RESMULT_madd_1_605_SUM0_0 : XOR2 - port map(A => \a1_b[0]\, B => \a0_b[1]\, Y => \RESMULT[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I60_Y : MAJ3 - port map(A => N_27, B => N_29, C => N273, Y => N376); - - RESMULT_madd_606_ADD_22x22_fast_I154_un1_Y : NOR3B - port map(A => N408, B => N461, C => N400, Y => I154_un1_Y); - - \RESMULT_a2_b[2]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(2), Y => - \a2_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I1_G0N : NOR2B - port map(A => N_29, B => N_27, Y => N276); - - RESMULT_madd_415 : MAJ3 - port map(A => N_175_i_0, B => N_160, C => N_162, Y => N_180); - - RESMULT_madd_606_ADD_22x22_fast_I93_Y : NOR3C - port map(A => N289, B => N292, C => N371, Y => N412); - - RESMULT_madd_543_0 : XOR3 - port map(A => N_231, B => N_229_i, C => N_220, Y => N_233); - - RESMULT_madd_119tt_m3 : MAJ3 - port map(A => \a6_b[0]\, B => \a4_b[2]\, C => \a5_b[1]\, Y - => madd_119tt_m3); - - \RESMULT_a3_b[2]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(2), Y => - \a3_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I118_un1_Y : NOR2B - port map(A => N405, B => N398, Y => I118_un1_Y); - - RESMULT_madd_493_11 : XOR3 - port map(A => N_192, B => N_203_i, C => N_194, Y => N_209_i); - - RESMULT_madd_606_ADD_22x22_fast_I44_Y : AOI1 - port map(A => N301, B => N297, C => N300, Y => N360); - - RESMULT_madd_88_4_0 : XOR2 - port map(A => \a2_b[5]\, B => \a4_b[3]\, Y => madd_88_4_0); - - RESMULT_madd_606_ADD_22x22_fast_I173_un1_Y_0 : NOR3C - port map(A => N410, B => N418, C => N_12, Y => - ADD_22x22_fast_I173_un1_Y_0); - - \RESMULT_a9_b[3]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(3), Y => - \a9_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_2 : NOR3C - port map(A => I70_un1_Y, B => ADD_22x22_fast_I171_Y_0, C - => I110_un1_Y, Y => ADD_22x22_fast_I171_Y_2); - - RESMULT_madd_606_ADD_22x22_fast_I112_un1_Y : AO1D - port map(A => N354, B => ADD_22x22_fast_I80_un1_Y, C => - N392, Y => I112_un1_Y); - - RESMULT_madd_548_0 : XOR2 - port map(A => madd_548_0_0, B => N_224, Y => N_235); - - RESMULT_madd_606_ADD_22x22_fast_I196_Y_0_0 : XOR3 - port map(A => N_86, B => N_101, C => N_88, Y => - ADD_22x22_fast_I196_Y_0_0); - - \RESMULT_a4_b[4]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(4), Y => - \a4_b[4]\); - - \RESMULT_a15_b[7]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(7), Y => - \a15_b[7]\); - - RESMULT_madd_353 : MAJ3 - port map(A => \a15_b[0]\, B => \a13_b[2]\, C => \a14_b[1]\, - Y => N_154_i); - - \RESMULT_a_i10_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(10), Y => - \a_i10_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I86_Y : AO1B - port map(A => N364, B => N361, C => N360, Y => N405); - - RESMULT_madd_268_12 : XNOR3 - port map(A => N_98, B => N_111_i, C => N_96, Y => N_115); - - RESMULT_madd_1_605_CO1 : NOR3B - port map(A => \a0_b[1]\, B => \a1_b[0]\, C => N_1_i, Y => - CO1); - - RESMULT_madd_4_0 : XNOR3 - port map(A => \a3_b[0]\, B => \a2_b[1]\, C => \a1_b[2]\, Y - => N_3); - - \RESMULT_a17_b_i[2]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(2), Y => - \a17_b_i[2]\); - - RESMULT_madd_379_12 : XNOR3 - port map(A => N_146, B => N_159_i, C => N_144, Y => N_163); - - RESMULT_madd_606_ADD_22x22_fast_I158_un1_Y : NOR3C - port map(A => N408, B => N416, C => N378, Y => I158_un1_Y); - - GND_i_0 : GND - port map(Y => GND_0); - - RESMULT_madd_606_ADD_22x22_fast_I37_Y : OR2B - port map(A => N313, B => N310, Y => N353); - - RESMULT_madd_557 : MIN3 - port map(A => \a15_b[6]\, B => \a16_b[5]\, C => - \a17_b_i[4]\, Y => N_238); - - RESMULT_madd_458_13 : XNOR3 - port map(A => N_178, B => N_189_i, C => N_176, Y => N_195); - - RESMULT_madd_606_ADD_22x22_fast_I101_un1_Y : NOR2B - port map(A => N377, B => N_12, Y => I101_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I159_un1_Y : OR3C - port map(A => N410, B => N418, C => N_12, Y => I159_un1_Y_i); - - RESMULT_madd_457_m3 : MIN3 - port map(A => N_162, B => madd_457tt_m3, C => N_175_i_0, Y - => madd_457_N_4); - - \RESMULT_a1_b[0]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(0), Y => - \a1_b[0]\); - - RESMULT_madd_24_0_0 : XOR2 - port map(A => N_7_i, B => N_9, Y => madd_24_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I152_un1_Y : NOR2B - port map(A => ADD_22x22_fast_I152_un1_Y_0, B => N396, Y => - I152_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I17_G0N : NOR2B - port map(A => N_249, B => N_244, Y => N324); - - RESMULT_madd_606_ADD_22x22_fast_I61_Y : NOR2B - port map(A => N277, B => N274, Y => N377); - - RESMULT_madd_88_0 : XNOR2 - port map(A => madd_88_0_0, B => N_26, Y => N_39); - - RESMULT_madd_606_ADD_22x22_fast_I130_Y : OR2 - port map(A => N409, B => I130_un1_Y, Y => N455); - - RESMULT_madd_522_0 : OA1A - port map(A => madd_522_0_tz_0, B => madd_487_0, C => N_208, - Y => madd_522_0); - - RESMULT_madd_487_0 : AOI1 - port map(A => N_194, B => N_192, C => N_203_i, Y => - madd_487_0); - - \RESMULT_a4_b[1]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(1), Y => - \a4_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I90_Y : OR2 - port map(A => N364, B => I90_un1_Y, Y => N409); - - \RESMULT_a13_b[6]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(6), Y => - \a13_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I54_Y : AO1 - port map(A => N286, B => N282, C => N285, Y => N370); - - \RESMULT_a2_b[7]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(7), Y => - \a2_b[7]\); - - RESMULT_madd_198_0 : OA1 - port map(A => N_83, B => madd_198_0_tz_0, C => N_81, Y => - madd_198_0); - - RESMULT_madd_168 : MAJ3 - port map(A => \a10_b[0]\, B => \a8_b[2]\, C => \a9_b[1]\, Y - => N_74_i); - - RESMULT_madd_606_ADD_22x22_fast_I196_Y_0 : AX1A - port map(A => N413, B => I133_un1_Y_i, C => - ADD_22x22_fast_I196_Y_0_0, Y => \RESMULT[11]\); - - RESMULT_madd_109 : MAJ3 - port map(A => \a2_b[6]\, B => \a0_b[8]\, C => \a1_b[7]\, Y - => N_48); - - \RESMULT_a10_b[2]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(2), Y => - \a10_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I126_Y : NOR2 - port map(A => N405, B => I126_un1_Y, Y => N451); - - \RESMULT_a17_b_i[7]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(7), Y => - \a17_b_i[7]\); - - RESMULT_madd_268_8_0 : XOR2 - port map(A => N_105_i, B => N_109, Y => madd_268_8_0); - - RESMULT_madd_573_0 : XNOR3 - port map(A => \a16_b[6]\, B => \a15_b[7]\, C => - \a17_b_i[5]\, Y => N_245); - - \RESMULT_a7_b[2]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(2), Y => - \a7_b[2]\); - - \RESMULT_a6_b[4]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(4), Y => - \a6_b[4]\); - - RESMULT_madd_92 : AO18 - port map(A => N_35, B => N_26, C => N_37, Y => N_40_i); - - RESMULT_madd_416_0_0 : XNOR2 - port map(A => N_177_i, B => N_164, Y => madd_416_0_0); - - RESMULT_madd_400 : MIN3 - port map(A => \a10_b[6]\, B => \a9_b[7]\, C => \a_i8_b[8]\, - Y => N_174); - - RESMULT_madd_390 : MAJ3 - port map(A => \a16_b[0]\, B => \a14_b[2]\, C => \a15_b[1]\, - Y => N_170); - - \RESMULT_a_i7_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(7), Y => - \a_i7_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I49_Y : OR2B - port map(A => N295, B => N292, Y => N365); - - RESMULT_madd_606_ADD_22x22_fast_I12_G0N : XA1B - port map(A => N_182, B => madd_458_0_0, C => N_184, Y => - N309); - - RESMULT_madd_458_2_0 : AX1E - port map(A => alu_coef_s(1), B => alu_sample(16), C => - alu_sample(17), Y => madd_458_2_0); - - RESMULT_madd_568_0 : XOR3 - port map(A => N_241, B => N_239_i, C => N_234, Y => N_243); - - RESMULT_madd_527_0 : OA1 - port map(A => N_212, B => N_223, C => N_221, Y => - madd_527_0); - - RESMULT_madd_526 : NOR2B - port map(A => N_223, B => N_212, Y => madd_301); - - RESMULT_madd_427_1 : OR2A - port map(A => \a17_b_i[0]\, B => madd_240, Y => N_186_1); - - RESMULT_madd_188 : AO18 - port map(A => N_77, B => N_73_i, C => N_75, Y => N_82); - - \RESMULT_a8_b[7]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(7), Y => - \a8_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I15_P0N : OR3 - port map(A => N_235, B => madd_301, C => madd_527_0, Y => - N319); - - RESMULT_madd_543_6 : XNOR3 - port map(A => N_218, B => N_227_i, C => N_216, Y => N_231); - - RESMULT_madd_136 : MAJ3 - port map(A => \a6_b[3]\, B => \a4_b[5]\, C => \a5_b[4]\, Y - => N_60); - - \RESMULT_a3_b[4]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(4), Y => - \a3_b[4]\); - - RESMULT_madd_373 : AO18 - port map(A => N_157, B => N_153_i, C => N_155, Y => N_162); - - RESMULT_madd_578_0 : XOR3 - port map(A => N_245, B => \a_i14_b[8]\, C => N_238, Y => - N_247); - - \RESMULT_a5_b[5]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(5), Y => - \a5_b[5]\); - - \RESMULT_a15_b[5]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(5), Y => - \a15_b[5]\); - - RESMULT_madd_231_2 : XOR2 - port map(A => madd_231_2_0, B => \a10_b[1]\, Y => N_89_i); - - \RESMULT_a5_b[0]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(0), Y => - \a5_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I91_Y : NOR2 - port map(A => N369, B => N365, Y => N410); - - RESMULT_madd_477_0_tz : OR2 - port map(A => \a_i10_b[8]\, B => N_186_1, Y => - madd_477_0_tz); - - RESMULT_madd_131 : MAJ3 - port map(A => \a9_b[0]\, B => \a7_b[2]\, C => \a8_b[1]\, Y - => N_58_i); - - RESMULT_madd_606_ADD_22x22_fast_I128_Y : AO1 - port map(A => N415, B => N408, C => N407, Y => N453); - - RESMULT_madd_577 : MAJ3 - port map(A => \a15_b[7]\, B => \a16_b[6]\, C => - \a17_b_i[5]\, Y => N_246_i); - - RESMULT_madd_305_4 : XNOR3 - port map(A => \a8_b[5]\, B => \a10_b[3]\, C => \a9_b[4]\, Y - => N_123); - - RESMULT_madd_61_4 : XNOR3 - port map(A => \a3_b[3]\, B => \a2_b[4]\, C => \a1_b[5]\, Y - => N_23); - - RESMULT_madd_477 : OR2 - port map(A => madd_477_0, B => madd_271, Y => N_206); - - RESMULT_madd_416_12 : XNOR3 - port map(A => N_162, B => N_175_i_0, C => N_160, Y => N_179); - - RESMULT_madd_606_ADD_22x22_fast_I192_Y_0 : XOR2 - port map(A => ADD_22x22_fast_I192_Y_0_0, B => N421, Y => - \RESMULT[7]\); - - RESMULT_madd_194_7 : XNOR3 - port map(A => \a4_b[6]\, B => \a_i2_b[8]\, C => \a3_b[7]\, - Y => N_77); - - RESMULT_madd_163 : NOR2B - port map(A => madd_124_m6, B => N_69, Y => N_72); - - \RESMULT_a13_b[5]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(5), Y => - \a13_b[5]\); - - \RESMULT_a1_b[1]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(1), Y => - \a1_b[1]\); - - RESMULT_madd_237 : NOR2B - port map(A => N_101, B => N_86, Y => N_104); - - RESMULT_madd_593_0 : XOR3 - port map(A => N_246_i, B => N_251, C => N_248, Y => N_253); - - RESMULT_madd_379_2 : XOR3 - port map(A => \a13_b[2]\, B => \a15_b[0]\, C => \a14_b[1]\, - Y => N_153_i); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - RESMULT_madd_606_ADD_22x22_fast_I3_G0N : NOR2B - port map(A => N_55, B => N_53, Y => N282); - - RESMULT_madd_606_ADD_22x22_fast_I134_un1_Y : NOR2B - port map(A => N416, B => N378, Y => I134_un1_Y); - - RESMULT_madd_493_0 : XOR3 - port map(A => madd_457_m6, B => N_209_i, C => N_211, Y => - N_213); - - RESMULT_madd_33 : MIN3 - port map(A => \a5_b[0]\, B => \a3_b[2]\, C => \a4_b[1]\, Y - => N_14); - - RESMULT_madd_606_ADD_22x22_fast_I59_Y : NOR2B - port map(A => N280, B => N277, Y => N375); - - \RESMULT_a8_b[0]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(0), Y => - \a8_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I202_Y_0_0 : XNOR3 - port map(A => N_182, B => madd_458_0_0, C => N_184, Y => - ADD_22x22_fast_I202_Y_0_0); - - RESMULT_madd_183 : MAJ3 - port map(A => N_58_i, B => N_60, C => N_62, Y => N_80); - - RESMULT_madd_606_ADD_22x22_fast_I0_G0N : NOR3A - port map(A => N_19, B => N_11_i, C => CO2, Y => N273); - - \RESMULT_a11_b[4]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(4), Y => - \a11_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_3 : OR3C - port map(A => N396, B => N388, C => - ADD_22x22_fast_I170_Y_3_tz, Y => ADD_22x22_fast_I170_Y_3); - - RESMULT_madd_606_ADD_22x22_fast_I94_Y : AO1A - port map(A => N369, B => N372, C => N368, Y => N413); - - RESMULT_madd_606_ADD_22x22_fast_I77_Y : NOR3C - port map(A => N307, B => N310, C => N351, Y => N396); - - \RESMULT_a0_b[0]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(0), Y => - \RESMULT[0]\); - - RESMULT_madd_39_0 : XOR2 - port map(A => madd_39_0_0, B => N_8, Y => N_17); - - RESMULT_madd_606_ADD_22x22_fast_I33_Y : OR2B - port map(A => N319, B => N316, Y => N349); - - RESMULT_madd_606_ADD_22x22_fast_I208_Y_0 : AX1E - port map(A => ADD_22x22_fast_I171_Y_3, B => - ADD_22x22_fast_I171_Y_2, C => ADD_22x22_fast_I208_Y_0_0, - Y => \RESMULT[23]\); - - \RESMULT_a_i1_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(1), Y => - \a_i1_b[8]\); - - RESMULT_madd_39_0_0 : XOR2 - port map(A => N_15_i, B => N_13, Y => madd_39_0_0); - - RESMULT_madd_342_10 : XOR3 - port map(A => N_126, B => N_122_i, C => N_124, Y => N_143_i); - - VCC_i : VCC - port map(Y => \VCC\); - - RESMULT_madd_597 : AO13 - port map(A => N_248, B => N_246_i, C => N_251, Y => N_254); - - \RESMULT_a7_b[4]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(4), Y => - \a7_b[4]\); - - RESMULT_madd_358 : MAJ3 - port map(A => \a12_b[3]\, B => \a10_b[5]\, C => \a11_b[4]\, - Y => N_156); - - RESMULT_madd_235_0_tz_0 : AO18 - port map(A => N_64_i, B => N_79, C => N_66, Y => - madd_235_0_tz_0); - - \RESMULT_a10_b[1]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(1), Y => - \a10_b[1]\); - - RESMULT_madd_497 : AO13 - port map(A => madd_457_m6, B => N_209_i, C => N_211, Y => - N_214); - - RESMULT_madd_395 : MAJ3 - port map(A => \a13_b[3]\, B => \a11_b[5]\, C => \a12_b[4]\, - Y => N_172); - - \RESMULT_a10_b[3]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(3), Y => - \a10_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I208_Y_0_0 : XOR2 - port map(A => N_253, B => N_250, Y => - ADD_22x22_fast_I208_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I69_Y : NOR2A - port map(A => N343, B => N347, Y => N388); - - RESMULT_madd_606_ADD_22x22_fast_I132_un1_Y : OR2B - port map(A => N419, B => N412, Y => I132_un1_Y_i); - - RESMULT_madd_268_8 : XOR2 - port map(A => madd_268_8_0, B => N_107, Y => N_113_i); - - RESMULT_madd_1_605_SUM1_0 : AX1E - port map(A => \a0_b[1]\, B => \a1_b[0]\, C => N_1_i, Y => - \RESMULT[2]\); - - \REG[9]\ : DFN1E1C0 - port map(D => \RESMULT[9]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(9)); - - RESMULT_madd_606_ADD_22x22_fast_I203_Y_0 : AX1B - port map(A => I154_un1_Y, B => ADD_22x22_fast_I154_Y_0, C - => ADD_22x22_fast_I203_Y_0_0, Y => \RESMULT[18]\); - - \RESMULT_a15_b[2]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(2), Y => - \a15_b[2]\); - - RESMULT_madd_379_8 : XOR3 - port map(A => N_155, B => N_153_i, C => N_157, Y => N_161_i); - - RESMULT_madd_82 : MAJ3 - port map(A => \a1_b[6]\, B => N_22, C => \a0_b[7]\, Y => - N_36); - - RESMULT_madd_606_ADD_22x22_fast_I48_Y : MAJ3 - port map(A => N_104, B => N_119, C => N291, Y => N364); - - RESMULT_madd_606_ADD_22x22_fast_I45_Y : NOR2B - port map(A => N301, B => N298, Y => N361); - - \RESMULT_a5_b[4]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(4), Y => - \a5_b[4]\); - - RESMULT_madd_416_8 : XOR3 - port map(A => N_171, B => N_169_i, C => N_173, Y => N_177_i); - - RESMULT_madd_606_ADD_22x22_fast_I12_P0N : XAI1A - port map(A => N_182, B => madd_458_0_0, C => N_184, Y => - N310); - - RESMULT_madd_606_ADD_22x22_fast_I195_Y_0 : XOR2 - port map(A => ADD_22x22_fast_I195_Y_0_0, B => N461, Y => - \RESMULT[10]\); - - \RESMULT_a1_b[2]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(2), Y => - \a1_b[2]\); - - RESMULT_madd_126 : NOR3B - port map(A => N_39, B => N_51, C => N_28, Y => N_56); - - \RESMULT_a_i14_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(14), Y => - \a_i14_b[8]\); - - RESMULT_madd_493_6 : XOR2 - port map(A => madd_493_6_0, B => N_186_1, Y => N_205); - - \RESMULT_a14_b[5]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(5), Y => - \a14_b[5]\); - - RESMULT_madd_161 : AO13 - port map(A => madd_119_m6, B => N_65_i, C => N_67, Y => - N_70); - - RESMULT_madd_606_ADD_22x22_fast_I194_Y_0_0 : XOR3 - port map(A => N_69, B => madd_124_m6, C => N_56, Y => - ADD_22x22_fast_I194_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I153_un1_Y : OA1A - port map(A => I133_un1_Y_i, B => N413, C => - ADD_22x22_fast_I153_un1_Y_0, Y => I153_un1_Y); - - \RESMULT_a4_b[0]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(0), Y => - \a4_b[0]\); - - \RESMULT_a12_b[4]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(4), Y => - \a12_b[4]\); - - RESMULT_madd_205 : MAJ3 - port map(A => \a11_b[0]\, B => \a9_b[2]\, C => \a10_b[1]\, - Y => N_90_i); - - RESMULT_madd_13 : AO13 - port map(A => N_2, B => \a0_b[3]\, C => N_3, Y => N_6); - - RESMULT_madd_606_ADD_22x22_fast_I207_Y_0 : AX1E - port map(A => I172_un1_Y, B => ADD_22x22_fast_I172_Y_2, C - => ADD_22x22_fast_I207_Y_0_0, Y => \RESMULT[22]\); - - RESMULT_madd_606_ADD_22x22_fast_I7_G0N : NOR2B - port map(A => N_119, B => N_104, Y => N294); - - RESMULT_madd_606_ADD_22x22_fast_I30_Y : AO13 - port map(A => N318, B => N_243, C => N_236, Y => N346); - - \RESMULT_a_i8_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(8), Y => - \a_i8_b[8]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC is - - port( sample_out_s : out std_logic_vector(17 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_ctrl : in std_logic_vector(2 downto 0); - HCLK_c : in std_logic; - HRESETn_c : in std_logic - ); - -end MAC; - -architecture DEF_ARCH of MAC is - - component MAC_REG_18 - port( alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - OP1_2C_D : out std_logic_vector(17 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MAC_REG_9 - port( alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - OP2_2C_D : out std_logic_vector(8 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MAC_REG_1_4 - port( MACMUX2sel_D : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - MACMUX2sel_D_D : out std_logic - ); - end component; - - component MAC_CONTROLER - port( alu_ctrl : in std_logic_vector(1 downto 0) := (others => 'U'); - MACMUX2sel : out std_logic; - N_4 : out std_logic; - mult : out std_logic; - mult_0 : out std_logic - ); - end component; - - component MAC_MUX - port( OP1_2C_D : in std_logic_vector(17 downto 0) := (others => 'U'); - MULTout : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinB : out std_logic_vector(24 downto 0); - ADDERinA_i : out std_logic_vector(18 to 18); - OP2_2C_D : in std_logic_vector(8 downto 0) := (others => 'U'); - ADDERout : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinA_17 : out std_logic; - ADDERinA_24 : out std_logic; - ADDERinA_23 : out std_logic; - ADDERinA_22 : out std_logic; - ADDERinA_21 : out std_logic; - ADDERinA_20 : out std_logic; - ADDERinA_19 : out std_logic; - ADDERinA_16 : out std_logic; - ADDERinA_15 : out std_logic; - ADDERinA_14 : out std_logic; - ADDERinA_13 : out std_logic; - ADDERinA_12 : out std_logic; - ADDERinA_11 : out std_logic; - ADDERinA_10 : out std_logic; - ADDERinA_9 : out std_logic; - ADDERinA_8 : out std_logic; - ADDERinA_7 : out std_logic; - ADDERinA_6 : out std_logic; - ADDERinA_5 : out std_logic; - ADDERinA_4 : out std_logic; - ADDERinA_3 : out std_logic; - ADDERinA_2 : out std_logic; - ADDERinA_1 : out std_logic; - ADDERinA_0 : out std_logic; - MACMUXsel_D : in std_logic := 'U'; - MACMUXsel_D_1 : in std_logic := 'U'; - MACMUXsel_D_0 : in std_logic := 'U' - ); - end component; - - component MAC_REG_27 - port( MULTout : in std_logic_vector(24 downto 7) := (others => 'U'); - MULTout_D : out std_logic_vector(24 downto 7); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component MAC_REG_1_1 - port( alu_ctrl : in std_logic_vector(0 to 0) := (others => 'U'); - add_D : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - add_D_0 : out std_logic - ); - end component; - - component MAC_REG_1_3 - port( MACMUX2sel : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - MACMUX2sel_D : out std_logic - ); - end component; - - component MAC_REG_1 - port( alu_ctrl : in std_logic_vector(2 to 2) := (others => 'U'); - clr_MAC_D : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - clr_MAC_D_0 : out std_logic - ); - end component; - - component Adder - port( ADDERout : out std_logic_vector(24 downto 0); - ADDERinA_i : in std_logic_vector(18 to 18) := (others => 'U'); - ADDERinB : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinA_0 : in std_logic := 'U'; - ADDERinA_1 : in std_logic := 'U'; - ADDERinA_3 : in std_logic := 'U'; - ADDERinA_5 : in std_logic := 'U'; - ADDERinA_7 : in std_logic := 'U'; - ADDERinA_8 : in std_logic := 'U'; - ADDERinA_15 : in std_logic := 'U'; - ADDERinA_16 : in std_logic := 'U'; - ADDERinA_2 : in std_logic := 'U'; - ADDERinA_14 : in std_logic := 'U'; - ADDERinA_6 : in std_logic := 'U'; - ADDERinA_10 : in std_logic := 'U'; - ADDERinA_4 : in std_logic := 'U'; - ADDERinA_12 : in std_logic := 'U'; - ADDERinA_20 : in std_logic := 'U'; - ADDERinA_11 : in std_logic := 'U'; - ADDERinA_19 : in std_logic := 'U'; - ADDERinA_9 : in std_logic := 'U'; - ADDERinA_13 : in std_logic := 'U'; - ADDERinA_21 : in std_logic := 'U'; - ADDERinA_22 : in std_logic := 'U'; - ADDERinA_24 : in std_logic := 'U'; - ADDERinA_23 : in std_logic := 'U'; - ADDERinA_17 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - clr_MAC_D : in std_logic := 'U'; - add_D : in std_logic := 'U'; - clr_MAC_D_0 : in std_logic := 'U'; - MACMUX2sel_D : in std_logic := 'U'; - add_D_0 : in std_logic := 'U' - ); - end component; - - component MAC_MUX2 - port( MULTout_D : in std_logic_vector(24 downto 7) := (others => 'U'); - ADDERout : in std_logic_vector(24 downto 7) := (others => 'U'); - sample_out_s : out std_logic_vector(17 downto 0); - MACMUX2sel_D_D : in std_logic := 'U' - ); - end component; - - component MAC_REG_1_2 - port( MACMUXsel_D : out std_logic; - MACMUXsel_D_0 : out std_logic; - N_4 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - MACMUXsel_D_1 : out std_logic - ); - end component; - - component Multiplier - port( MULTout : out std_logic_vector(24 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - mult : in std_logic := 'U'; - mult_0 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal MACMUX2sel, N_4, mult, mult_0, \MULTout[0]\, - \MULTout[1]\, \MULTout[2]\, \MULTout[3]\, \MULTout[4]\, - \MULTout[5]\, \MULTout[6]\, \MULTout[7]\, \MULTout[8]\, - \MULTout[9]\, \MULTout[10]\, \MULTout[11]\, \MULTout[12]\, - \MULTout[13]\, \MULTout[14]\, \MULTout[15]\, - \MULTout[16]\, \MULTout[17]\, \MULTout[18]\, - \MULTout[19]\, \MULTout[20]\, \MULTout[21]\, - \MULTout[22]\, \MULTout[23]\, \MULTout[24]\, - \ADDERout[0]\, \ADDERout[1]\, \ADDERout[2]\, - \ADDERout[3]\, \ADDERout[4]\, \ADDERout[5]\, - \ADDERout[6]\, \ADDERout[7]\, \ADDERout[8]\, - \ADDERout[9]\, \ADDERout[10]\, \ADDERout[11]\, - \ADDERout[12]\, \ADDERout[13]\, \ADDERout[14]\, - \ADDERout[15]\, \ADDERout[16]\, \ADDERout[17]\, - \ADDERout[18]\, \ADDERout[19]\, \ADDERout[20]\, - \ADDERout[21]\, \ADDERout[22]\, \ADDERout[23]\, - \ADDERout[24]\, \ADDERinA_i[18]\, \ADDERinB[0]\, - \ADDERinB[1]\, \ADDERinB[2]\, \ADDERinB[3]\, - \ADDERinB[4]\, \ADDERinB[5]\, \ADDERinB[6]\, - \ADDERinB[7]\, \ADDERinB[8]\, \ADDERinB[9]\, - \ADDERinB[10]\, \ADDERinB[11]\, \ADDERinB[12]\, - \ADDERinB[13]\, \ADDERinB[14]\, \ADDERinB[15]\, - \ADDERinB[16]\, \ADDERinB[17]\, \ADDERinB[18]\, - \ADDERinB[19]\, \ADDERinB[20]\, \ADDERinB[21]\, - \ADDERinB[22]\, \ADDERinB[23]\, \ADDERinB[24]\, - \ADDERinA[0]\, \ADDERinA[1]\, \ADDERinA[3]\, - \ADDERinA[5]\, \ADDERinA[7]\, \ADDERinA[8]\, - \ADDERinA[15]\, \ADDERinA[16]\, \ADDERinA[2]\, - \ADDERinA[14]\, \ADDERinA[6]\, \ADDERinA[10]\, - \ADDERinA[4]\, \ADDERinA[12]\, \ADDERinA[20]\, - \ADDERinA[11]\, \ADDERinA[19]\, \ADDERinA[9]\, - \ADDERinA[13]\, \ADDERinA[21]\, \ADDERinA[22]\, - \ADDERinA[24]\, \ADDERinA[23]\, \ADDERinA[17]\, clr_MAC_D, - add_D, clr_MAC_D_0, MACMUX2sel_D, add_D_0, \OP1_2C_D[0]\, - \OP1_2C_D[1]\, \OP1_2C_D[2]\, \OP1_2C_D[3]\, - \OP1_2C_D[4]\, \OP1_2C_D[5]\, \OP1_2C_D[6]\, - \OP1_2C_D[7]\, \OP1_2C_D[8]\, \OP1_2C_D[9]\, - \OP1_2C_D[10]\, \OP1_2C_D[11]\, \OP1_2C_D[12]\, - \OP1_2C_D[13]\, \OP1_2C_D[14]\, \OP1_2C_D[15]\, - \OP1_2C_D[16]\, \OP1_2C_D[17]\, \OP2_2C_D[0]\, - \OP2_2C_D[1]\, \OP2_2C_D[2]\, \OP2_2C_D[3]\, - \OP2_2C_D[4]\, \OP2_2C_D[5]\, \OP2_2C_D[6]\, - \OP2_2C_D[7]\, \OP2_2C_D[8]\, \MULTout_D[7]\, - \MULTout_D[8]\, \MULTout_D[9]\, \MULTout_D[10]\, - \MULTout_D[11]\, \MULTout_D[12]\, \MULTout_D[13]\, - \MULTout_D[14]\, \MULTout_D[15]\, \MULTout_D[16]\, - \MULTout_D[17]\, \MULTout_D[18]\, \MULTout_D[19]\, - \MULTout_D[20]\, \MULTout_D[21]\, \MULTout_D[22]\, - \MULTout_D[23]\, \MULTout_D[24]\, MACMUXsel_D, - MACMUXsel_D_0, MACMUXsel_D_1, MACMUX2sel_D_D, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : MAC_REG_18 - Use entity work.MAC_REG_18(DEF_ARCH); - for all : MAC_REG_9 - Use entity work.MAC_REG_9(DEF_ARCH); - for all : MAC_REG_1_4 - Use entity work.MAC_REG_1_4(DEF_ARCH); - for all : MAC_CONTROLER - Use entity work.MAC_CONTROLER(DEF_ARCH); - for all : MAC_MUX - Use entity work.MAC_MUX(DEF_ARCH); - for all : MAC_REG_27 - Use entity work.MAC_REG_27(DEF_ARCH); - for all : MAC_REG_1_1 - Use entity work.MAC_REG_1_1(DEF_ARCH); - for all : MAC_REG_1_3 - Use entity work.MAC_REG_1_3(DEF_ARCH); - for all : MAC_REG_1 - Use entity work.MAC_REG_1(DEF_ARCH); - for all : Adder - Use entity work.Adder(DEF_ARCH); - for all : MAC_MUX2 - Use entity work.MAC_MUX2(DEF_ARCH); - for all : MAC_REG_1_2 - Use entity work.MAC_REG_1_2(DEF_ARCH); - for all : Multiplier - Use entity work.Multiplier(DEF_ARCH); -begin - - - OP1REG : MAC_REG_18 - port map(alu_sample(17) => alu_sample(17), alu_sample(16) - => alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), - OP1_2C_D(17) => \OP1_2C_D[17]\, OP1_2C_D(16) => - \OP1_2C_D[16]\, OP1_2C_D(15) => \OP1_2C_D[15]\, - OP1_2C_D(14) => \OP1_2C_D[14]\, OP1_2C_D(13) => - \OP1_2C_D[13]\, OP1_2C_D(12) => \OP1_2C_D[12]\, - OP1_2C_D(11) => \OP1_2C_D[11]\, OP1_2C_D(10) => - \OP1_2C_D[10]\, OP1_2C_D(9) => \OP1_2C_D[9]\, OP1_2C_D(8) - => \OP1_2C_D[8]\, OP1_2C_D(7) => \OP1_2C_D[7]\, - OP1_2C_D(6) => \OP1_2C_D[6]\, OP1_2C_D(5) => - \OP1_2C_D[5]\, OP1_2C_D(4) => \OP1_2C_D[4]\, OP1_2C_D(3) - => \OP1_2C_D[3]\, OP1_2C_D(2) => \OP1_2C_D[2]\, - OP1_2C_D(1) => \OP1_2C_D[1]\, OP1_2C_D(0) => - \OP1_2C_D[0]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c); - - GND_i_0 : GND - port map(Y => GND_0); - - OP2REG : MAC_REG_9 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - OP2_2C_D(8) => \OP2_2C_D[8]\, OP2_2C_D(7) => - \OP2_2C_D[7]\, OP2_2C_D(6) => \OP2_2C_D[6]\, OP2_2C_D(5) - => \OP2_2C_D[5]\, OP2_2C_D(4) => \OP2_2C_D[4]\, - OP2_2C_D(3) => \OP2_2C_D[3]\, OP2_2C_D(2) => - \OP2_2C_D[2]\, OP2_2C_D(1) => \OP2_2C_D[1]\, OP2_2C_D(0) - => \OP2_2C_D[0]\, HRESETn_c => HRESETn_c, HCLK_c => - HCLK_c); - - VCC_i : VCC - port map(Y => \VCC\); - - MACMUX2selREG2 : MAC_REG_1_4 - port map(MACMUX2sel_D => MACMUX2sel_D, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, MACMUX2sel_D_D => - MACMUX2sel_D_D); - - MAC_CONTROLER1 : MAC_CONTROLER - port map(alu_ctrl(1) => alu_ctrl(1), alu_ctrl(0) => - alu_ctrl(0), MACMUX2sel => MACMUX2sel, N_4 => N_4, mult - => mult, mult_0 => mult_0); - - MACMUX_inst : MAC_MUX - port map(OP1_2C_D(17) => \OP1_2C_D[17]\, OP1_2C_D(16) => - \OP1_2C_D[16]\, OP1_2C_D(15) => \OP1_2C_D[15]\, - OP1_2C_D(14) => \OP1_2C_D[14]\, OP1_2C_D(13) => - \OP1_2C_D[13]\, OP1_2C_D(12) => \OP1_2C_D[12]\, - OP1_2C_D(11) => \OP1_2C_D[11]\, OP1_2C_D(10) => - \OP1_2C_D[10]\, OP1_2C_D(9) => \OP1_2C_D[9]\, OP1_2C_D(8) - => \OP1_2C_D[8]\, OP1_2C_D(7) => \OP1_2C_D[7]\, - OP1_2C_D(6) => \OP1_2C_D[6]\, OP1_2C_D(5) => - \OP1_2C_D[5]\, OP1_2C_D(4) => \OP1_2C_D[4]\, OP1_2C_D(3) - => \OP1_2C_D[3]\, OP1_2C_D(2) => \OP1_2C_D[2]\, - OP1_2C_D(1) => \OP1_2C_D[1]\, OP1_2C_D(0) => - \OP1_2C_D[0]\, MULTout(24) => \MULTout[24]\, MULTout(23) - => \MULTout[23]\, MULTout(22) => \MULTout[22]\, - MULTout(21) => \MULTout[21]\, MULTout(20) => - \MULTout[20]\, MULTout(19) => \MULTout[19]\, MULTout(18) - => \MULTout[18]\, MULTout(17) => \MULTout[17]\, - MULTout(16) => \MULTout[16]\, MULTout(15) => - \MULTout[15]\, MULTout(14) => \MULTout[14]\, MULTout(13) - => \MULTout[13]\, MULTout(12) => \MULTout[12]\, - MULTout(11) => \MULTout[11]\, MULTout(10) => - \MULTout[10]\, MULTout(9) => \MULTout[9]\, MULTout(8) => - \MULTout[8]\, MULTout(7) => \MULTout[7]\, MULTout(6) => - \MULTout[6]\, MULTout(5) => \MULTout[5]\, MULTout(4) => - \MULTout[4]\, MULTout(3) => \MULTout[3]\, MULTout(2) => - \MULTout[2]\, MULTout(1) => \MULTout[1]\, MULTout(0) => - \MULTout[0]\, ADDERinB(24) => \ADDERinB[24]\, - ADDERinB(23) => \ADDERinB[23]\, ADDERinB(22) => - \ADDERinB[22]\, ADDERinB(21) => \ADDERinB[21]\, - ADDERinB(20) => \ADDERinB[20]\, ADDERinB(19) => - \ADDERinB[19]\, ADDERinB(18) => \ADDERinB[18]\, - ADDERinB(17) => \ADDERinB[17]\, ADDERinB(16) => - \ADDERinB[16]\, ADDERinB(15) => \ADDERinB[15]\, - ADDERinB(14) => \ADDERinB[14]\, ADDERinB(13) => - \ADDERinB[13]\, ADDERinB(12) => \ADDERinB[12]\, - ADDERinB(11) => \ADDERinB[11]\, ADDERinB(10) => - \ADDERinB[10]\, ADDERinB(9) => \ADDERinB[9]\, ADDERinB(8) - => \ADDERinB[8]\, ADDERinB(7) => \ADDERinB[7]\, - ADDERinB(6) => \ADDERinB[6]\, ADDERinB(5) => - \ADDERinB[5]\, ADDERinB(4) => \ADDERinB[4]\, ADDERinB(3) - => \ADDERinB[3]\, ADDERinB(2) => \ADDERinB[2]\, - ADDERinB(1) => \ADDERinB[1]\, ADDERinB(0) => - \ADDERinB[0]\, ADDERinA_i(18) => \ADDERinA_i[18]\, - OP2_2C_D(8) => \OP2_2C_D[8]\, OP2_2C_D(7) => - \OP2_2C_D[7]\, OP2_2C_D(6) => \OP2_2C_D[6]\, OP2_2C_D(5) - => \OP2_2C_D[5]\, OP2_2C_D(4) => \OP2_2C_D[4]\, - OP2_2C_D(3) => \OP2_2C_D[3]\, OP2_2C_D(2) => - \OP2_2C_D[2]\, OP2_2C_D(1) => \OP2_2C_D[1]\, OP2_2C_D(0) - => \OP2_2C_D[0]\, ADDERout(24) => \ADDERout[24]\, - ADDERout(23) => \ADDERout[23]\, ADDERout(22) => - \ADDERout[22]\, ADDERout(21) => \ADDERout[21]\, - ADDERout(20) => \ADDERout[20]\, ADDERout(19) => - \ADDERout[19]\, ADDERout(18) => \ADDERout[18]\, - ADDERout(17) => \ADDERout[17]\, ADDERout(16) => - \ADDERout[16]\, ADDERout(15) => \ADDERout[15]\, - ADDERout(14) => \ADDERout[14]\, ADDERout(13) => - \ADDERout[13]\, ADDERout(12) => \ADDERout[12]\, - ADDERout(11) => \ADDERout[11]\, ADDERout(10) => - \ADDERout[10]\, ADDERout(9) => \ADDERout[9]\, ADDERout(8) - => \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, - ADDERout(6) => \ADDERout[6]\, ADDERout(5) => - \ADDERout[5]\, ADDERout(4) => \ADDERout[4]\, ADDERout(3) - => \ADDERout[3]\, ADDERout(2) => \ADDERout[2]\, - ADDERout(1) => \ADDERout[1]\, ADDERout(0) => - \ADDERout[0]\, ADDERinA_17 => \ADDERinA[17]\, ADDERinA_24 - => \ADDERinA[24]\, ADDERinA_23 => \ADDERinA[23]\, - ADDERinA_22 => \ADDERinA[22]\, ADDERinA_21 => - \ADDERinA[21]\, ADDERinA_20 => \ADDERinA[20]\, - ADDERinA_19 => \ADDERinA[19]\, ADDERinA_16 => - \ADDERinA[16]\, ADDERinA_15 => \ADDERinA[15]\, - ADDERinA_14 => \ADDERinA[14]\, ADDERinA_13 => - \ADDERinA[13]\, ADDERinA_12 => \ADDERinA[12]\, - ADDERinA_11 => \ADDERinA[11]\, ADDERinA_10 => - \ADDERinA[10]\, ADDERinA_9 => \ADDERinA[9]\, ADDERinA_8 - => \ADDERinA[8]\, ADDERinA_7 => \ADDERinA[7]\, - ADDERinA_6 => \ADDERinA[6]\, ADDERinA_5 => \ADDERinA[5]\, - ADDERinA_4 => \ADDERinA[4]\, ADDERinA_3 => \ADDERinA[3]\, - ADDERinA_2 => \ADDERinA[2]\, ADDERinA_1 => \ADDERinA[1]\, - ADDERinA_0 => \ADDERinA[0]\, MACMUXsel_D => MACMUXsel_D, - MACMUXsel_D_1 => MACMUXsel_D_1, MACMUXsel_D_0 => - MACMUXsel_D_0); - - MULToutREG : MAC_REG_27 - port map(MULTout(24) => \MULTout[24]\, MULTout(23) => - \MULTout[23]\, MULTout(22) => \MULTout[22]\, MULTout(21) - => \MULTout[21]\, MULTout(20) => \MULTout[20]\, - MULTout(19) => \MULTout[19]\, MULTout(18) => - \MULTout[18]\, MULTout(17) => \MULTout[17]\, MULTout(16) - => \MULTout[16]\, MULTout(15) => \MULTout[15]\, - MULTout(14) => \MULTout[14]\, MULTout(13) => - \MULTout[13]\, MULTout(12) => \MULTout[12]\, MULTout(11) - => \MULTout[11]\, MULTout(10) => \MULTout[10]\, - MULTout(9) => \MULTout[9]\, MULTout(8) => \MULTout[8]\, - MULTout(7) => \MULTout[7]\, MULTout_D(24) => - \MULTout_D[24]\, MULTout_D(23) => \MULTout_D[23]\, - MULTout_D(22) => \MULTout_D[22]\, MULTout_D(21) => - \MULTout_D[21]\, MULTout_D(20) => \MULTout_D[20]\, - MULTout_D(19) => \MULTout_D[19]\, MULTout_D(18) => - \MULTout_D[18]\, MULTout_D(17) => \MULTout_D[17]\, - MULTout_D(16) => \MULTout_D[16]\, MULTout_D(15) => - \MULTout_D[15]\, MULTout_D(14) => \MULTout_D[14]\, - MULTout_D(13) => \MULTout_D[13]\, MULTout_D(12) => - \MULTout_D[12]\, MULTout_D(11) => \MULTout_D[11]\, - MULTout_D(10) => \MULTout_D[10]\, MULTout_D(9) => - \MULTout_D[9]\, MULTout_D(8) => \MULTout_D[8]\, - MULTout_D(7) => \MULTout_D[7]\, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c); - - GND_i : GND - port map(Y => \GND\); - - addREG : MAC_REG_1_1 - port map(alu_ctrl(0) => alu_ctrl(0), add_D => add_D, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, add_D_0 => - add_D_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - MACMUX2selREG : MAC_REG_1_3 - port map(MACMUX2sel => MACMUX2sel, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, MACMUX2sel_D => MACMUX2sel_D); - - clr_MACREG1 : MAC_REG_1 - port map(alu_ctrl(2) => alu_ctrl(2), clr_MAC_D => clr_MAC_D, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, clr_MAC_D_0 => - clr_MAC_D_0); - - adder_inst : Adder - port map(ADDERout(24) => \ADDERout[24]\, ADDERout(23) => - \ADDERout[23]\, ADDERout(22) => \ADDERout[22]\, - ADDERout(21) => \ADDERout[21]\, ADDERout(20) => - \ADDERout[20]\, ADDERout(19) => \ADDERout[19]\, - ADDERout(18) => \ADDERout[18]\, ADDERout(17) => - \ADDERout[17]\, ADDERout(16) => \ADDERout[16]\, - ADDERout(15) => \ADDERout[15]\, ADDERout(14) => - \ADDERout[14]\, ADDERout(13) => \ADDERout[13]\, - ADDERout(12) => \ADDERout[12]\, ADDERout(11) => - \ADDERout[11]\, ADDERout(10) => \ADDERout[10]\, - ADDERout(9) => \ADDERout[9]\, ADDERout(8) => - \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, ADDERout(6) - => \ADDERout[6]\, ADDERout(5) => \ADDERout[5]\, - ADDERout(4) => \ADDERout[4]\, ADDERout(3) => - \ADDERout[3]\, ADDERout(2) => \ADDERout[2]\, ADDERout(1) - => \ADDERout[1]\, ADDERout(0) => \ADDERout[0]\, - ADDERinA_i(18) => \ADDERinA_i[18]\, ADDERinB(24) => - \ADDERinB[24]\, ADDERinB(23) => \ADDERinB[23]\, - ADDERinB(22) => \ADDERinB[22]\, ADDERinB(21) => - \ADDERinB[21]\, ADDERinB(20) => \ADDERinB[20]\, - ADDERinB(19) => \ADDERinB[19]\, ADDERinB(18) => - \ADDERinB[18]\, ADDERinB(17) => \ADDERinB[17]\, - ADDERinB(16) => \ADDERinB[16]\, ADDERinB(15) => - \ADDERinB[15]\, ADDERinB(14) => \ADDERinB[14]\, - ADDERinB(13) => \ADDERinB[13]\, ADDERinB(12) => - \ADDERinB[12]\, ADDERinB(11) => \ADDERinB[11]\, - ADDERinB(10) => \ADDERinB[10]\, ADDERinB(9) => - \ADDERinB[9]\, ADDERinB(8) => \ADDERinB[8]\, ADDERinB(7) - => \ADDERinB[7]\, ADDERinB(6) => \ADDERinB[6]\, - ADDERinB(5) => \ADDERinB[5]\, ADDERinB(4) => - \ADDERinB[4]\, ADDERinB(3) => \ADDERinB[3]\, ADDERinB(2) - => \ADDERinB[2]\, ADDERinB(1) => \ADDERinB[1]\, - ADDERinB(0) => \ADDERinB[0]\, ADDERinA_0 => \ADDERinA[0]\, - ADDERinA_1 => \ADDERinA[1]\, ADDERinA_3 => \ADDERinA[3]\, - ADDERinA_5 => \ADDERinA[5]\, ADDERinA_7 => \ADDERinA[7]\, - ADDERinA_8 => \ADDERinA[8]\, ADDERinA_15 => - \ADDERinA[15]\, ADDERinA_16 => \ADDERinA[16]\, ADDERinA_2 - => \ADDERinA[2]\, ADDERinA_14 => \ADDERinA[14]\, - ADDERinA_6 => \ADDERinA[6]\, ADDERinA_10 => - \ADDERinA[10]\, ADDERinA_4 => \ADDERinA[4]\, ADDERinA_12 - => \ADDERinA[12]\, ADDERinA_20 => \ADDERinA[20]\, - ADDERinA_11 => \ADDERinA[11]\, ADDERinA_19 => - \ADDERinA[19]\, ADDERinA_9 => \ADDERinA[9]\, ADDERinA_13 - => \ADDERinA[13]\, ADDERinA_21 => \ADDERinA[21]\, - ADDERinA_22 => \ADDERinA[22]\, ADDERinA_24 => - \ADDERinA[24]\, ADDERinA_23 => \ADDERinA[23]\, - ADDERinA_17 => \ADDERinA[17]\, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, clr_MAC_D => clr_MAC_D, add_D => add_D, - clr_MAC_D_0 => clr_MAC_D_0, MACMUX2sel_D => MACMUX2sel_D, - add_D_0 => add_D_0); - - MAC_MUX2_inst : MAC_MUX2 - port map(MULTout_D(24) => \MULTout_D[24]\, MULTout_D(23) - => \MULTout_D[23]\, MULTout_D(22) => \MULTout_D[22]\, - MULTout_D(21) => \MULTout_D[21]\, MULTout_D(20) => - \MULTout_D[20]\, MULTout_D(19) => \MULTout_D[19]\, - MULTout_D(18) => \MULTout_D[18]\, MULTout_D(17) => - \MULTout_D[17]\, MULTout_D(16) => \MULTout_D[16]\, - MULTout_D(15) => \MULTout_D[15]\, MULTout_D(14) => - \MULTout_D[14]\, MULTout_D(13) => \MULTout_D[13]\, - MULTout_D(12) => \MULTout_D[12]\, MULTout_D(11) => - \MULTout_D[11]\, MULTout_D(10) => \MULTout_D[10]\, - MULTout_D(9) => \MULTout_D[9]\, MULTout_D(8) => - \MULTout_D[8]\, MULTout_D(7) => \MULTout_D[7]\, - ADDERout(24) => \ADDERout[24]\, ADDERout(23) => - \ADDERout[23]\, ADDERout(22) => \ADDERout[22]\, - ADDERout(21) => \ADDERout[21]\, ADDERout(20) => - \ADDERout[20]\, ADDERout(19) => \ADDERout[19]\, - ADDERout(18) => \ADDERout[18]\, ADDERout(17) => - \ADDERout[17]\, ADDERout(16) => \ADDERout[16]\, - ADDERout(15) => \ADDERout[15]\, ADDERout(14) => - \ADDERout[14]\, ADDERout(13) => \ADDERout[13]\, - ADDERout(12) => \ADDERout[12]\, ADDERout(11) => - \ADDERout[11]\, ADDERout(10) => \ADDERout[10]\, - ADDERout(9) => \ADDERout[9]\, ADDERout(8) => - \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, - sample_out_s(17) => sample_out_s(17), sample_out_s(16) - => sample_out_s(16), sample_out_s(15) => - sample_out_s(15), sample_out_s(14) => sample_out_s(14), - sample_out_s(13) => sample_out_s(13), sample_out_s(12) - => sample_out_s(12), sample_out_s(11) => - sample_out_s(11), sample_out_s(10) => sample_out_s(10), - sample_out_s(9) => sample_out_s(9), sample_out_s(8) => - sample_out_s(8), sample_out_s(7) => sample_out_s(7), - sample_out_s(6) => sample_out_s(6), sample_out_s(5) => - sample_out_s(5), sample_out_s(4) => sample_out_s(4), - sample_out_s(3) => sample_out_s(3), sample_out_s(2) => - sample_out_s(2), sample_out_s(1) => sample_out_s(1), - sample_out_s(0) => sample_out_s(0), MACMUX2sel_D_D => - MACMUX2sel_D_D); - - MACMUXselREG : MAC_REG_1_2 - port map(MACMUXsel_D => MACMUXsel_D, MACMUXsel_D_0 => - MACMUXsel_D_0, N_4 => N_4, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c, MACMUXsel_D_1 => MACMUXsel_D_1); - - Multiplieri_nst : Multiplier - port map(MULTout(24) => \MULTout[24]\, MULTout(23) => - \MULTout[23]\, MULTout(22) => \MULTout[22]\, MULTout(21) - => \MULTout[21]\, MULTout(20) => \MULTout[20]\, - MULTout(19) => \MULTout[19]\, MULTout(18) => - \MULTout[18]\, MULTout(17) => \MULTout[17]\, MULTout(16) - => \MULTout[16]\, MULTout(15) => \MULTout[15]\, - MULTout(14) => \MULTout[14]\, MULTout(13) => - \MULTout[13]\, MULTout(12) => \MULTout[12]\, MULTout(11) - => \MULTout[11]\, MULTout(10) => \MULTout[10]\, - MULTout(9) => \MULTout[9]\, MULTout(8) => \MULTout[8]\, - MULTout(7) => \MULTout[7]\, MULTout(6) => \MULTout[6]\, - MULTout(5) => \MULTout[5]\, MULTout(4) => \MULTout[4]\, - MULTout(3) => \MULTout[3]\, MULTout(2) => \MULTout[2]\, - MULTout(1) => \MULTout[1]\, MULTout(0) => \MULTout[0]\, - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_sample(17) => alu_sample(17), alu_sample(16) => - alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), mult => - mult, mult_0 => mult_0, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ALU is - - port( alu_ctrl : in std_logic_vector(2 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - sample_out_s : out std_logic_vector(17 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end ALU; - -architecture DEF_ARCH of ALU is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MAC - port( sample_out_s : out std_logic_vector(17 downto 0); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - HCLK_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : MAC - Use entity work.MAC(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \arith.MACinst\ : MAC - port map(sample_out_s(17) => sample_out_s(17), - sample_out_s(16) => sample_out_s(16), sample_out_s(15) - => sample_out_s(15), sample_out_s(14) => - sample_out_s(14), sample_out_s(13) => sample_out_s(13), - sample_out_s(12) => sample_out_s(12), sample_out_s(11) - => sample_out_s(11), sample_out_s(10) => - sample_out_s(10), sample_out_s(9) => sample_out_s(9), - sample_out_s(8) => sample_out_s(8), sample_out_s(7) => - sample_out_s(7), sample_out_s(6) => sample_out_s(6), - sample_out_s(5) => sample_out_s(5), sample_out_s(4) => - sample_out_s(4), sample_out_s(3) => sample_out_s(3), - sample_out_s(2) => sample_out_s(2), sample_out_s(1) => - sample_out_s(1), sample_out_s(0) => sample_out_s(0), - alu_sample(17) => alu_sample(17), alu_sample(16) => - alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_ctrl(2) => alu_ctrl(2), alu_ctrl(1) => alu_ctrl(1), - alu_ctrl(0) => alu_ctrl(0), HCLK_c => HCLK_c, HRESETn_c - => HRESETn_c); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity generic_syncram_2p_8_18_0 is - - port( ram_input : in std_logic_vector(17 downto 0); - counter : in std_logic_vector(7 downto 0); - DIN_REG1_15 : out std_logic; - ram_output_16 : out std_logic; - ram_output_0 : out std_logic; - ram_output_17 : out std_logic; - ram_output_15 : out std_logic; - ram_output_14 : out std_logic; - ram_output_13 : out std_logic; - ram_output_12 : out std_logic; - ram_output_11 : out std_logic; - ram_output_10 : out std_logic; - ram_output_9 : out std_logic; - ram_output_8 : out std_logic; - ram_output_7 : out std_logic; - ram_output_6 : out std_logic; - ram_output_5 : out std_logic; - ram_output_4 : out std_logic; - ram_output_3 : out std_logic; - ram_output_1 : out std_logic; - reg_sample_in : in std_logic_vector(6 downto 5); - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15); - alu_sample_1 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_10 : out std_logic; - ram_write_i : in std_logic; - generic_syncram_2p_8_18_0_VCC : in std_logic; - generic_syncram_2p_8_18_0_GND : in std_logic; - ADD_8x8_medium_area_I30_Y_0 : in std_logic; - ADD_8x8_medium_area_I29_Y_0 : in std_logic; - ADD_8x8_medium_area_I28_Y_0 : in std_logic; - ADD_8x8_medium_area_I27_Y_0 : in std_logic; - ADD_8x8_medium_area_I26_Y_0 : in std_logic; - ADD_8x8_medium_area_I25_Y_0 : in std_logic; - ADD_8x8_medium_area_I24_Y_0 : in std_logic; - ADD_8x8_medium_area_I0_S_0 : in std_logic; - ram_write : in std_logic; - HCLK_c : in std_logic; - alu_sel_input : in std_logic; - I_1_RNI3I3E3 : out std_logic - ); - -end generic_syncram_2p_8_18_0; - -architecture DEF_ARCH of generic_syncram_2p_8_18_0 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component RAM512X18 - generic (MEMORYFILE:string := ""); - - port( RADDR8 : in std_logic := 'U'; - RADDR7 : in std_logic := 'U'; - RADDR6 : in std_logic := 'U'; - RADDR5 : in std_logic := 'U'; - RADDR4 : in std_logic := 'U'; - RADDR3 : in std_logic := 'U'; - RADDR2 : in std_logic := 'U'; - RADDR1 : in std_logic := 'U'; - RADDR0 : in std_logic := 'U'; - WADDR8 : in std_logic := 'U'; - WADDR7 : in std_logic := 'U'; - WADDR6 : in std_logic := 'U'; - WADDR5 : in std_logic := 'U'; - WADDR4 : in std_logic := 'U'; - WADDR3 : in std_logic := 'U'; - WADDR2 : in std_logic := 'U'; - WADDR1 : in std_logic := 'U'; - WADDR0 : in std_logic := 'U'; - WD17 : in std_logic := 'U'; - WD16 : in std_logic := 'U'; - WD15 : in std_logic := 'U'; - WD14 : in std_logic := 'U'; - WD13 : in std_logic := 'U'; - WD12 : in std_logic := 'U'; - WD11 : in std_logic := 'U'; - WD10 : in std_logic := 'U'; - WD9 : in std_logic := 'U'; - WD8 : in std_logic := 'U'; - WD7 : in std_logic := 'U'; - WD6 : in std_logic := 'U'; - WD5 : in std_logic := 'U'; - WD4 : in std_logic := 'U'; - WD3 : in std_logic := 'U'; - WD2 : in std_logic := 'U'; - WD1 : in std_logic := 'U'; - WD0 : in std_logic := 'U'; - RW0 : in std_logic := 'U'; - RW1 : in std_logic := 'U'; - WW0 : in std_logic := 'U'; - WW1 : in std_logic := 'U'; - PIPE : in std_logic := 'U'; - REN : in std_logic := 'U'; - WEN : in std_logic := 'U'; - RCLK : in std_logic := 'U'; - WCLK : in std_logic := 'U'; - RESET : in std_logic := 'U'; - RD17 : out std_logic; - RD16 : out std_logic; - RD15 : out std_logic; - RD14 : out std_logic; - RD13 : out std_logic; - RD12 : out std_logic; - RD11 : out std_logic; - RD10 : out std_logic; - RD9 : out std_logic; - RD8 : out std_logic; - RD7 : out std_logic; - RD6 : out std_logic; - RD5 : out std_logic; - RD4 : out std_logic; - RD3 : out std_logic; - RD2 : out std_logic; - RD1 : out std_logic; - RD0 : out std_logic - ); - end component; - - signal I_5_1, I_4_0_i_0, I_4_1_i_0, I_4_3, I_5_0, - \RADDR_REG1[2]\, \WADDR_REG1[2]\, N_5, I_5_2, I_5_5_0, - I_5_5_1, \RADDR_REG1[6]\, \WADDR_REG1[6]\, I_4_7_i_0, - \RADDR_REG1[4]\, \WADDR_REG1[4]\, I_4_5_i_0, N_7_i_0, - \DIN_REG1[2]\, \DOUT_TMP[2]\, \DOUT_TMP[15]\, - I_3_RNI91FA3, \DOUT_TMP[5]\, \DIN_REG1_RNIVQEG[5]\, - \DIN_REG1[5]\, \DOUT_TMP[6]\, \DIN_REG1_RNI13FG[6]\, - \DIN_REG1[6]\, \WADDR_REG1[0]\, \RADDR_REG1[0]\, - \WADDR_REG1[1]\, \RADDR_REG1[1]\, \WADDR_REG1[3]\, - \RADDR_REG1[3]\, \WADDR_REG1[5]\, \RADDR_REG1[5]\, - \WADDR_REG1[7]\, \RADDR_REG1[7]\, \DIN_REG1[1]\, - \DOUT_TMP[1]\, \DIN_REG1[3]\, \DOUT_TMP[3]\, - \DIN_REG1[4]\, \DOUT_TMP[4]\, \DIN_REG1[7]\, - \DOUT_TMP[7]\, \DIN_REG1[8]\, \DOUT_TMP[8]\, - \DIN_REG1[9]\, \DOUT_TMP[9]\, \DIN_REG1[10]\, - \DOUT_TMP[10]\, \DIN_REG1[11]\, \DOUT_TMP[11]\, - \DIN_REG1[12]\, \DOUT_TMP[12]\, \DIN_REG1[13]\, - \DOUT_TMP[13]\, \DIN_REG1[14]\, \DOUT_TMP[14]\, - \DIN_REG1[17]\, \DOUT_TMP[17]\, \DIN_REG1[0]\, - \DOUT_TMP[0]\, \DIN_REG1[16]\, \DOUT_TMP[16]\, - \DIN_REG1[15]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - DIN_REG1_15 <= \DIN_REG1[15]\; - - rfd_tile_I_1_RNIAE4E3 : MX2 - port map(A => \DIN_REG1[9]\, B => \DOUT_TMP[9]\, S => - N_7_i_0, Y => ram_output_9); - - rfd_tile_I_1_RNI038F3 : MX2 - port map(A => \DIN_REG1[12]\, B => \DOUT_TMP[12]\, S => - N_7_i_0, Y => ram_output_12); - - \rfd_tile_DIN_REG1_RNI13FG[6]\ : MX2 - port map(A => reg_sample_in(6), B => \DIN_REG1[6]\, S => - alu_sel_input, Y => \DIN_REG1_RNI13FG[6]\); - - \rfd_tile_DIN_REG1[9]\ : DFN1 - port map(D => ram_input(9), CLK => HCLK_c, Q => - \DIN_REG1[9]\); - - rfd_tile_I_1_RNI4M3E3 : MX2 - port map(A => \DIN_REG1[3]\, B => \DOUT_TMP[3]\, S => - N_7_i_0, Y => ram_output_3); - - \rfd_tile_RADDR_REG1[5]\ : DFN1 - port map(D => counter(5), CLK => HCLK_c, Q => - \RADDR_REG1[5]\); - - \rfd_tile_WADDR_REG1[6]\ : DFN1 - port map(D => ADD_8x8_medium_area_I29_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[6]\); - - rfd_tile_I_3 : DFN1 - port map(D => ram_write, CLK => HCLK_c, Q => N_5); - - rfd_tile_I_1_RNI2E3E3 : MX2 - port map(A => \DIN_REG1[1]\, B => \DOUT_TMP[1]\, S => - N_7_i_0, Y => ram_output_1); - - rfd_tile_I_1_RNI5Q3E3 : MX2 - port map(A => \DIN_REG1[4]\, B => \DOUT_TMP[4]\, S => - N_7_i_0, Y => ram_output_4); - - \rfd_tile_DIN_REG1[10]\ : DFN1 - port map(D => ram_input(10), CLK => HCLK_c, Q => - \DIN_REG1[10]\); - - \rfd_tile_WADDR_REG1[4]\ : DFN1 - port map(D => ADD_8x8_medium_area_I27_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[4]\); - - \rfd_tile_RADDR_REG1_RNIL9AC[1]\ : XNOR2 - port map(A => \WADDR_REG1[1]\, B => \RADDR_REG1[1]\, Y => - I_4_1_i_0); - - rfd_tile_I_1_RNI1A3E3 : MX2 - port map(A => \DIN_REG1[0]\, B => \DOUT_TMP[0]\, S => - N_7_i_0, Y => ram_output_0); - - rfd_tile_I_3_RNI91FA3 : OR2B - port map(A => alu_sel_input, B => N_7_i_0, Y => - I_3_RNI91FA3); - - VCC_i : VCC - port map(Y => \VCC\); - - \rfd_tile_DIN_REG1[0]\ : DFN1 - port map(D => ram_input(0), CLK => HCLK_c, Q => - \DIN_REG1[0]\); - - \rfd_tile_DIN_REG1[5]\ : DFN1 - port map(D => ram_input(5), CLK => HCLK_c, Q => - \DIN_REG1[5]\); - - \rfd_tile_DIN_REG1[4]\ : DFN1 - port map(D => ram_input(4), CLK => HCLK_c, Q => - \DIN_REG1[4]\); - - \rfd_tile_DIN_REG1[3]\ : DFN1 - port map(D => ram_input(3), CLK => HCLK_c, Q => - \DIN_REG1[3]\); - - \rfd_tile_DIN_REG1[2]\ : DFN1 - port map(D => ram_input(2), CLK => HCLK_c, Q => - \DIN_REG1[2]\); - - \rfd_tile_DIN_REG1[12]\ : DFN1 - port map(D => ram_input(12), CLK => HCLK_c, Q => - \DIN_REG1[12]\); - - \rfd_tile_WADDR_REG1[7]\ : DFN1 - port map(D => ADD_8x8_medium_area_I30_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[7]\); - - rfd_tile_I_3_RNIVS763 : OR2B - port map(A => I_5_2, B => I_5_1, Y => N_7_i_0); - - rfd_tile_I_3_RNI60RF : XA1A - port map(A => \RADDR_REG1[2]\, B => \WADDR_REG1[2]\, C => - N_5, Y => I_5_0); - - rfd_tile_I_1_RNI864E3 : MX2 - port map(A => \DIN_REG1[7]\, B => \DOUT_TMP[7]\, S => - N_7_i_0, Y => ram_output_7); - - \rfd_tile_RADDR_REG1_RNIOBMO[4]\ : XA1A - port map(A => \RADDR_REG1[4]\, B => \WADDR_REG1[4]\, C => - I_4_5_i_0, Y => I_5_5_0); - - rfd_tile_I_1_RNIV28F3 : MX2 - port map(A => \DIN_REG1[11]\, B => \DOUT_TMP[11]\, S => - N_7_i_0, Y => ram_output_11); - - \rfd_tile_DIN_REG1[15]\ : DFN1 - port map(D => ram_input(15), CLK => HCLK_c, Q => - \DIN_REG1[15]\); - - \rfd_tile_RADDR_REG1[0]\ : DFN1 - port map(D => counter(0), CLK => HCLK_c, Q => - \RADDR_REG1[0]\); - - \rfd_tile_WADDR_REG1[5]\ : DFN1 - port map(D => ADD_8x8_medium_area_I28_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[5]\); - - rfd_tile_I_1_RNINIEU3 : MX2 - port map(A => \DOUT_TMP[6]\, B => \DIN_REG1_RNI13FG[6]\, S - => I_3_RNI91FA3, Y => alu_sample_1); - - rfd_tile_I_1_RNI3I3E3 : MX2 - port map(A => \DIN_REG1[2]\, B => \DOUT_TMP[2]\, S => - N_7_i_0, Y => I_1_RNI3I3E3); - - \rfd_tile_RADDR_REG1[2]\ : DFN1 - port map(D => counter(2), CLK => HCLK_c, Q => - \RADDR_REG1[2]\); - - \rfd_tile_DIN_REG1[1]\ : DFN1 - port map(D => ram_input(1), CLK => HCLK_c, Q => - \DIN_REG1[1]\); - - rfd_tile_I_1_RNI5Q2Q3 : MX2 - port map(A => \DOUT_TMP[15]\, B => - reg_sample_in_RNIFA3C(15), S => I_3_RNI91FA3, Y => - alu_sample_10); - - \rfd_tile_RADDR_REG1[3]\ : DFN1 - port map(D => counter(3), CLK => HCLK_c, Q => - \RADDR_REG1[3]\); - - rfd_tile_I_3_RNIUN812 : NOR3C - port map(A => I_5_5_0, B => I_5_5_1, C => I_5_0, Y => I_5_2); - - GND_i : GND - port map(Y => \GND\); - - rfd_tile_I_1_RNI338F3 : MX2 - port map(A => \DIN_REG1[15]\, B => \DOUT_TMP[15]\, S => - N_7_i_0, Y => ram_output_15); - - \rfd_tile_RADDR_REG1_RNIT9BC[5]\ : XNOR2 - port map(A => \WADDR_REG1[5]\, B => \RADDR_REG1[5]\, Y => - I_4_5_i_0); - - \rfd_tile_RADDR_REG1[1]\ : DFN1 - port map(D => counter(1), CLK => HCLK_c, Q => - \RADDR_REG1[1]\); - - \rfd_tile_DIN_REG1_RNIVQEG[5]\ : MX2 - port map(A => reg_sample_in(5), B => \DIN_REG1[5]\, S => - alu_sel_input, Y => \DIN_REG1_RNIVQEG[5]\); - - rfd_tile_I_1_RNI9A4E3 : MX2 - port map(A => \DIN_REG1[8]\, B => \DOUT_TMP[8]\, S => - N_7_i_0, Y => ram_output_8); - - \rfd_tile_DIN_REG1[14]\ : DFN1 - port map(D => ram_input(14), CLK => HCLK_c, Q => - \DIN_REG1[14]\); - - \rfd_tile_RADDR_REG1_RNI15V41[0]\ : NOR3B - port map(A => I_4_0_i_0, B => I_4_1_i_0, C => I_4_3, Y => - I_5_1); - - \rfd_tile_RADDR_REG1_RNIJ1AC[0]\ : XNOR2 - port map(A => \WADDR_REG1[0]\, B => \RADDR_REG1[0]\, Y => - I_4_0_i_0); - - rfd_tile_I_1_RNIU28F3 : MX2 - port map(A => \DIN_REG1[10]\, B => \DOUT_TMP[10]\, S => - N_7_i_0, Y => ram_output_10); - - \rfd_tile_RADDR_REG1[6]\ : DFN1 - port map(D => counter(6), CLK => HCLK_c, Q => - \RADDR_REG1[6]\); - - rfd_tile_I_1_RNI724E3 : MX2C - port map(A => \DIN_REG1[6]\, B => \DOUT_TMP[6]\, S => - N_7_i_0, Y => ram_output_6); - - \rfd_tile_RADDR_REG1_RNI1QBC[7]\ : XNOR2 - port map(A => \WADDR_REG1[7]\, B => \RADDR_REG1[7]\, Y => - I_4_7_i_0); - - \rfd_tile_RADDR_REG1_RNIPPAC[3]\ : XOR2 - port map(A => \WADDR_REG1[3]\, B => \RADDR_REG1[3]\, Y => - I_4_3); - - \rfd_tile_DIN_REG1[8]\ : DFN1 - port map(D => ram_input(8), CLK => HCLK_c, Q => - \DIN_REG1[8]\); - - \rfd_tile_WADDR_REG1[0]\ : DFN1 - port map(D => ADD_8x8_medium_area_I0_S_0, CLK => HCLK_c, Q - => \WADDR_REG1[0]\); - - \rfd_tile_RADDR_REG1[4]\ : DFN1 - port map(D => counter(4), CLK => HCLK_c, Q => - \RADDR_REG1[4]\); - - rfd_tile_I_1_RNI138F3 : MX2 - port map(A => \DIN_REG1[13]\, B => \DOUT_TMP[13]\, S => - N_7_i_0, Y => ram_output_13); - - \rfd_tile_DIN_REG1[6]\ : DFN1 - port map(D => ram_input(6), CLK => HCLK_c, Q => - \DIN_REG1[6]\); - - \rfd_tile_WADDR_REG1[2]\ : DFN1 - port map(D => ADD_8x8_medium_area_I25_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[2]\); - - \rfd_tile_DIN_REG1[11]\ : DFN1 - port map(D => ram_input(11), CLK => HCLK_c, Q => - \DIN_REG1[11]\); - - rfd_tile_I_1_RNILAEU3 : MX2 - port map(A => \DOUT_TMP[5]\, B => \DIN_REG1_RNIVQEG[5]\, S - => I_3_RNI91FA3, Y => alu_sample_0); - - \rfd_tile_WADDR_REG1[3]\ : DFN1 - port map(D => ADD_8x8_medium_area_I26_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[3]\); - - rfd_tile_I_1_RNI438F3 : MX2 - port map(A => \DIN_REG1[16]\, B => \DOUT_TMP[16]\, S => - N_7_i_0, Y => ram_output_16); - - rfd_tile_I_1_RNI238F3 : MX2 - port map(A => \DIN_REG1[14]\, B => \DOUT_TMP[14]\, S => - N_7_i_0, Y => ram_output_14); - - \rfd_tile_DIN_REG1[13]\ : DFN1 - port map(D => ram_input(13), CLK => HCLK_c, Q => - \DIN_REG1[13]\); - - \rfd_tile_RADDR_REG1_RNI0CNO[6]\ : XA1A - port map(A => \RADDR_REG1[6]\, B => \WADDR_REG1[6]\, C => - I_4_7_i_0, Y => I_5_5_1); - - rfd_tile_I_1_RNI538F3 : MX2 - port map(A => \DIN_REG1[17]\, B => \DOUT_TMP[17]\, S => - N_7_i_0, Y => ram_output_17); - - rfd_tile_I_1 : RAM512X18 - port map(RADDR8 => generic_syncram_2p_8_18_0_GND, RADDR7 - => counter(7), RADDR6 => counter(6), RADDR5 => - counter(5), RADDR4 => counter(4), RADDR3 => counter(3), - RADDR2 => counter(2), RADDR1 => counter(1), RADDR0 => - counter(0), WADDR8 => generic_syncram_2p_8_18_0_GND, - WADDR7 => ADD_8x8_medium_area_I30_Y_0, WADDR6 => - ADD_8x8_medium_area_I29_Y_0, WADDR5 => - ADD_8x8_medium_area_I28_Y_0, WADDR4 => - ADD_8x8_medium_area_I27_Y_0, WADDR3 => - ADD_8x8_medium_area_I26_Y_0, WADDR2 => - ADD_8x8_medium_area_I25_Y_0, WADDR1 => - ADD_8x8_medium_area_I24_Y_0, WADDR0 => - ADD_8x8_medium_area_I0_S_0, WD17 => ram_input(17), WD16 - => ram_input(16), WD15 => ram_input(15), WD14 => - ram_input(14), WD13 => ram_input(13), WD12 => - ram_input(12), WD11 => ram_input(11), WD10 => - ram_input(10), WD9 => ram_input(9), WD8 => ram_input(8), - WD7 => ram_input(7), WD6 => ram_input(6), WD5 => - ram_input(5), WD4 => ram_input(4), WD3 => ram_input(3), - WD2 => ram_input(2), WD1 => ram_input(1), WD0 => - ram_input(0), RW0 => generic_syncram_2p_8_18_0_GND, RW1 - => generic_syncram_2p_8_18_0_VCC, WW0 => - generic_syncram_2p_8_18_0_GND, WW1 => - generic_syncram_2p_8_18_0_VCC, PIPE => - generic_syncram_2p_8_18_0_GND, REN => - generic_syncram_2p_8_18_0_GND, WEN => ram_write_i, RCLK - => HCLK_c, WCLK => HCLK_c, RESET => - generic_syncram_2p_8_18_0_VCC, RD17 => \DOUT_TMP[17]\, - RD16 => \DOUT_TMP[16]\, RD15 => \DOUT_TMP[15]\, RD14 => - \DOUT_TMP[14]\, RD13 => \DOUT_TMP[13]\, RD12 => - \DOUT_TMP[12]\, RD11 => \DOUT_TMP[11]\, RD10 => - \DOUT_TMP[10]\, RD9 => \DOUT_TMP[9]\, RD8 => - \DOUT_TMP[8]\, RD7 => \DOUT_TMP[7]\, RD6 => \DOUT_TMP[6]\, - RD5 => \DOUT_TMP[5]\, RD4 => \DOUT_TMP[4]\, RD3 => - \DOUT_TMP[3]\, RD2 => \DOUT_TMP[2]\, RD1 => \DOUT_TMP[1]\, - RD0 => \DOUT_TMP[0]\); - - \rfd_tile_RADDR_REG1[7]\ : DFN1 - port map(D => counter(7), CLK => HCLK_c, Q => - \RADDR_REG1[7]\); - - \rfd_tile_DIN_REG1[16]\ : DFN1 - port map(D => ram_input(16), CLK => HCLK_c, Q => - \DIN_REG1[16]\); - - \rfd_tile_WADDR_REG1[1]\ : DFN1 - port map(D => ADD_8x8_medium_area_I24_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[1]\); - - rfd_tile_I_1_RNI6U3E3 : MX2C - port map(A => \DIN_REG1[5]\, B => \DOUT_TMP[5]\, S => - N_7_i_0, Y => ram_output_5); - - \rfd_tile_DIN_REG1[17]\ : DFN1 - port map(D => ram_input(17), CLK => HCLK_c, Q => - \DIN_REG1[17]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \rfd_tile_DIN_REG1[7]\ : DFN1 - port map(D => ram_input(7), CLK => HCLK_c, Q => - \DIN_REG1[7]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ0 is - - port( alu_sample_10 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_1 : out std_logic; - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15); - reg_sample_in : in std_logic_vector(6 downto 5); - ram_output_1 : out std_logic; - ram_output_3 : out std_logic; - ram_output_4 : out std_logic; - ram_output_5 : out std_logic; - ram_output_6 : out std_logic; - ram_output_7 : out std_logic; - ram_output_8 : out std_logic; - ram_output_9 : out std_logic; - ram_output_10 : out std_logic; - ram_output_11 : out std_logic; - ram_output_12 : out std_logic; - ram_output_13 : out std_logic; - ram_output_14 : out std_logic; - ram_output_15 : out std_logic; - ram_output_17 : out std_logic; - ram_output_0 : out std_logic; - ram_output_16 : out std_logic; - DIN_REG1 : out std_logic_vector(15 to 15); - counter : in std_logic_vector(7 downto 0); - ram_input : in std_logic_vector(17 downto 0); - I_1_RNI3I3E3 : out std_logic; - alu_sel_input : in std_logic; - HCLK_c : in std_logic; - ram_write : in std_logic; - ADD_8x8_medium_area_I0_S_0 : in std_logic; - ADD_8x8_medium_area_I24_Y_0 : in std_logic; - ADD_8x8_medium_area_I25_Y_0 : in std_logic; - ADD_8x8_medium_area_I26_Y_0 : in std_logic; - ADD_8x8_medium_area_I27_Y_0 : in std_logic; - ADD_8x8_medium_area_I28_Y_0 : in std_logic; - ADD_8x8_medium_area_I29_Y_0 : in std_logic; - ADD_8x8_medium_area_I30_Y_0 : in std_logic; - syncram_2pZ0_GND : in std_logic; - syncram_2pZ0_VCC : in std_logic; - ram_write_i : in std_logic - ); - -end syncram_2pZ0; - -architecture DEF_ARCH of syncram_2pZ0 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component generic_syncram_2p_8_18_0 - port( ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - counter : in std_logic_vector(7 downto 0) := (others => 'U'); - DIN_REG1_15 : out std_logic; - ram_output_16 : out std_logic; - ram_output_0 : out std_logic; - ram_output_17 : out std_logic; - ram_output_15 : out std_logic; - ram_output_14 : out std_logic; - ram_output_13 : out std_logic; - ram_output_12 : out std_logic; - ram_output_11 : out std_logic; - ram_output_10 : out std_logic; - ram_output_9 : out std_logic; - ram_output_8 : out std_logic; - ram_output_7 : out std_logic; - ram_output_6 : out std_logic; - ram_output_5 : out std_logic; - ram_output_4 : out std_logic; - ram_output_3 : out std_logic; - ram_output_1 : out std_logic; - reg_sample_in : in std_logic_vector(6 downto 5) := (others => 'U'); - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15) := (others => 'U'); - alu_sample_1 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_10 : out std_logic; - ram_write_i : in std_logic := 'U'; - generic_syncram_2p_8_18_0_VCC : in std_logic := 'U'; - generic_syncram_2p_8_18_0_GND : in std_logic := 'U'; - ADD_8x8_medium_area_I30_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I29_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I28_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I27_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I26_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I25_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I24_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I0_S_0 : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - alu_sel_input : in std_logic := 'U'; - I_1_RNI3I3E3 : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : generic_syncram_2p_8_18_0 - Use entity work.generic_syncram_2p_8_18_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \inf.x0\ : generic_syncram_2p_8_18_0 - port map(ram_input(17) => ram_input(17), ram_input(16) => - ram_input(16), ram_input(15) => ram_input(15), - ram_input(14) => ram_input(14), ram_input(13) => - ram_input(13), ram_input(12) => ram_input(12), - ram_input(11) => ram_input(11), ram_input(10) => - ram_input(10), ram_input(9) => ram_input(9), ram_input(8) - => ram_input(8), ram_input(7) => ram_input(7), - ram_input(6) => ram_input(6), ram_input(5) => - ram_input(5), ram_input(4) => ram_input(4), ram_input(3) - => ram_input(3), ram_input(2) => ram_input(2), - ram_input(1) => ram_input(1), ram_input(0) => - ram_input(0), counter(7) => counter(7), counter(6) => - counter(6), counter(5) => counter(5), counter(4) => - counter(4), counter(3) => counter(3), counter(2) => - counter(2), counter(1) => counter(1), counter(0) => - counter(0), DIN_REG1_15 => DIN_REG1(15), ram_output_16 - => ram_output_16, ram_output_0 => ram_output_0, - ram_output_17 => ram_output_17, ram_output_15 => - ram_output_15, ram_output_14 => ram_output_14, - ram_output_13 => ram_output_13, ram_output_12 => - ram_output_12, ram_output_11 => ram_output_11, - ram_output_10 => ram_output_10, ram_output_9 => - ram_output_9, ram_output_8 => ram_output_8, ram_output_7 - => ram_output_7, ram_output_6 => ram_output_6, - ram_output_5 => ram_output_5, ram_output_4 => - ram_output_4, ram_output_3 => ram_output_3, ram_output_1 - => ram_output_1, reg_sample_in(6) => reg_sample_in(6), - reg_sample_in(5) => reg_sample_in(5), - reg_sample_in_RNIFA3C(15) => reg_sample_in_RNIFA3C(15), - alu_sample_1 => alu_sample_1, alu_sample_0 => - alu_sample_0, alu_sample_10 => alu_sample_10, ram_write_i - => ram_write_i, generic_syncram_2p_8_18_0_VCC => - syncram_2pZ0_VCC, generic_syncram_2p_8_18_0_GND => - syncram_2pZ0_GND, ADD_8x8_medium_area_I30_Y_0 => - ADD_8x8_medium_area_I30_Y_0, ADD_8x8_medium_area_I29_Y_0 - => ADD_8x8_medium_area_I29_Y_0, - ADD_8x8_medium_area_I28_Y_0 => - ADD_8x8_medium_area_I28_Y_0, ADD_8x8_medium_area_I27_Y_0 - => ADD_8x8_medium_area_I27_Y_0, - ADD_8x8_medium_area_I26_Y_0 => - ADD_8x8_medium_area_I26_Y_0, ADD_8x8_medium_area_I25_Y_0 - => ADD_8x8_medium_area_I25_Y_0, - ADD_8x8_medium_area_I24_Y_0 => - ADD_8x8_medium_area_I24_Y_0, ADD_8x8_medium_area_I0_S_0 - => ADD_8x8_medium_area_I0_S_0, ram_write => ram_write, - HCLK_c => HCLK_c, alu_sel_input => alu_sel_input, - I_1_RNI3I3E3 => I_1_RNI3I3E3); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity RAM_CTRLR_v2 is - - port( ram_input : in std_logic_vector(17 downto 0); - DIN_REG1 : out std_logic_vector(15 to 15); - ram_output_16 : out std_logic; - ram_output_0 : out std_logic; - ram_output_17 : out std_logic; - ram_output_15 : out std_logic; - ram_output_14 : out std_logic; - ram_output_13 : out std_logic; - ram_output_12 : out std_logic; - ram_output_11 : out std_logic; - ram_output_10 : out std_logic; - ram_output_9 : out std_logic; - ram_output_8 : out std_logic; - ram_output_7 : out std_logic; - ram_output_6 : out std_logic; - ram_output_5 : out std_logic; - ram_output_4 : out std_logic; - ram_output_3 : out std_logic; - ram_output_1 : out std_logic; - reg_sample_in : in std_logic_vector(6 downto 5); - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15); - alu_sample_1 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_10 : out std_logic; - waddr_previous : in std_logic_vector(1 downto 0); - ram_write_i : in std_logic; - RAM_CTRLR_v2_VCC : in std_logic; - RAM_CTRLR_v2_GND : in std_logic; - ram_write : in std_logic; - alu_sel_input : in std_logic; - I_1_RNI3I3E3 : out std_logic; - raddr_add1 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - raddr_rst : in std_logic - ); - -end RAM_CTRLR_v2; - -architecture DEF_ARCH of RAM_CTRLR_v2 is - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component syncram_2pZ0 - port( alu_sample_10 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_1 : out std_logic; - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15) := (others => 'U'); - reg_sample_in : in std_logic_vector(6 downto 5) := (others => 'U'); - ram_output_1 : out std_logic; - ram_output_3 : out std_logic; - ram_output_4 : out std_logic; - ram_output_5 : out std_logic; - ram_output_6 : out std_logic; - ram_output_7 : out std_logic; - ram_output_8 : out std_logic; - ram_output_9 : out std_logic; - ram_output_10 : out std_logic; - ram_output_11 : out std_logic; - ram_output_12 : out std_logic; - ram_output_13 : out std_logic; - ram_output_14 : out std_logic; - ram_output_15 : out std_logic; - ram_output_17 : out std_logic; - ram_output_0 : out std_logic; - ram_output_16 : out std_logic; - DIN_REG1 : out std_logic_vector(15 to 15); - counter : in std_logic_vector(7 downto 0) := (others => 'U'); - ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - I_1_RNI3I3E3 : out std_logic; - alu_sel_input : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - ADD_8x8_medium_area_I0_S_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I24_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I25_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I26_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I27_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I28_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I29_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I30_Y_0 : in std_logic := 'U'; - syncram_2pZ0_GND : in std_logic := 'U'; - syncram_2pZ0_VCC : in std_logic := 'U'; - ram_write_i : in std_logic := 'U' - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_TMP[0]\, \counter[1]_net_1\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, \counter[4]_net_1\, - \DWACT_ADD_CI_0_g_array_12[0]\, \counter[2]_net_1\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, \counter[6]_net_1\, - ADD_8x8_medium_area_I20_Y_0, \counter[5]_net_1\, N_5_i, - ADD_8x8_medium_area_I20_un1_Y_0, N125_i, - ADD_8x8_medium_area_I13_Y_0, \counter[3]_net_1\, - ADD_8x8_medium_area_I13_un1_Y_0, - ADD_8x8_medium_area_I30_Y_0, \counter[7]_net_1\, N149, - ADD_8x8_medium_area_I29_Y_0, N147, - ADD_8x8_medium_area_I27_Y_0, N145_i, N135_i, - ADD_8x8_medium_area_I24_Y_0, N116, - ADD_8x8_medium_area_I25_Y_0, ADD_8x8_medium_area_I28_Y_0, - N124, \counter[0]_net_1\, N120, - ADD_8x8_medium_area_I0_S_0, ADD_8x8_medium_area_I26_Y_0, - N121, \counter_3[7]\, I_34, \counter_3[6]\, I_30, - \counter_3[5]\, I_33, \counter_3[4]\, I_28, - \counter_3[3]\, I_31, \counter_3[2]\, I_32, - \counter_3[1]\, I_27, \counter_3[0]\, - \DWACT_ADD_CI_0_partial_sum[0]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : syncram_2pZ0 - Use entity work.syncram_2pZ0(DEF_ARCH); -begin - - - un1_counter_1_ADD_8x8_medium_area_I20_Y_0 : OA1 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - C => N_5_i, Y => ADD_8x8_medium_area_I20_Y_0); - - un1_counter_I_45 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => - \counter[6]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_2[0]\); - - un1_counter_I_31 : XOR2 - port map(A => \counter[3]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_31); - - un1_counter_I_36 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - un1_counter_1_ADD_8x8_medium_area_I12_Y : MX2B - port map(A => N116, B => N_5_i, S => \counter[1]_net_1\, Y - => N135_i); - - un1_counter_1_ADD_8x8_medium_area_I13_Y_0 : OAI1 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - C => N_5_i, Y => ADD_8x8_medium_area_I13_Y_0); - - un1_counter_I_44 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \counter[2]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12[0]\); - - \counter[2]\ : DFN1C0 - port map(D => \counter_3[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[2]_net_1\); - - \counter[7]\ : DFN1C0 - port map(D => \counter_3[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[7]_net_1\); - - un1_counter_1_ADD_8x8_medium_area_I29_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[6]_net_1\, C => N147, Y - => ADD_8x8_medium_area_I29_Y_0); - - un1_counter_I_48 : AND2 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - Y => \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - un1_counter_1_ADD_8x8_medium_area_I20_Y : OA1B - port map(A => N145_i, B => ADD_8x8_medium_area_I20_un1_Y_0, - C => ADD_8x8_medium_area_I20_Y_0, Y => N147); - - \counter_RNO[0]\ : NOR2A - port map(A => \DWACT_ADD_CI_0_partial_sum[0]\, B => - raddr_rst, Y => \counter_3[0]\); - - \counter[6]\ : DFN1C0 - port map(D => \counter_3[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[6]_net_1\); - - \counter_RNO[4]\ : NOR2A - port map(A => I_28, B => raddr_rst, Y => \counter_3[4]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \memRAM.SRAM\ : syncram_2pZ0 - port map(alu_sample_10 => alu_sample_10, alu_sample_0 => - alu_sample_0, alu_sample_1 => alu_sample_1, - reg_sample_in_RNIFA3C(15) => reg_sample_in_RNIFA3C(15), - reg_sample_in(6) => reg_sample_in(6), reg_sample_in(5) - => reg_sample_in(5), ram_output_1 => ram_output_1, - ram_output_3 => ram_output_3, ram_output_4 => - ram_output_4, ram_output_5 => ram_output_5, ram_output_6 - => ram_output_6, ram_output_7 => ram_output_7, - ram_output_8 => ram_output_8, ram_output_9 => - ram_output_9, ram_output_10 => ram_output_10, - ram_output_11 => ram_output_11, ram_output_12 => - ram_output_12, ram_output_13 => ram_output_13, - ram_output_14 => ram_output_14, ram_output_15 => - ram_output_15, ram_output_17 => ram_output_17, - ram_output_0 => ram_output_0, ram_output_16 => - ram_output_16, DIN_REG1(15) => DIN_REG1(15), counter(7) - => \counter[7]_net_1\, counter(6) => \counter[6]_net_1\, - counter(5) => \counter[5]_net_1\, counter(4) => - \counter[4]_net_1\, counter(3) => \counter[3]_net_1\, - counter(2) => \counter[2]_net_1\, counter(1) => - \counter[1]_net_1\, counter(0) => \counter[0]_net_1\, - ram_input(17) => ram_input(17), ram_input(16) => - ram_input(16), ram_input(15) => ram_input(15), - ram_input(14) => ram_input(14), ram_input(13) => - ram_input(13), ram_input(12) => ram_input(12), - ram_input(11) => ram_input(11), ram_input(10) => - ram_input(10), ram_input(9) => ram_input(9), ram_input(8) - => ram_input(8), ram_input(7) => ram_input(7), - ram_input(6) => ram_input(6), ram_input(5) => - ram_input(5), ram_input(4) => ram_input(4), ram_input(3) - => ram_input(3), ram_input(2) => ram_input(2), - ram_input(1) => ram_input(1), ram_input(0) => - ram_input(0), I_1_RNI3I3E3 => I_1_RNI3I3E3, alu_sel_input - => alu_sel_input, HCLK_c => HCLK_c, ram_write => - ram_write, ADD_8x8_medium_area_I0_S_0 => - ADD_8x8_medium_area_I0_S_0, ADD_8x8_medium_area_I24_Y_0 - => ADD_8x8_medium_area_I24_Y_0, - ADD_8x8_medium_area_I25_Y_0 => - ADD_8x8_medium_area_I25_Y_0, ADD_8x8_medium_area_I26_Y_0 - => ADD_8x8_medium_area_I26_Y_0, - ADD_8x8_medium_area_I27_Y_0 => - ADD_8x8_medium_area_I27_Y_0, ADD_8x8_medium_area_I28_Y_0 - => ADD_8x8_medium_area_I28_Y_0, - ADD_8x8_medium_area_I29_Y_0 => - ADD_8x8_medium_area_I29_Y_0, ADD_8x8_medium_area_I30_Y_0 - => ADD_8x8_medium_area_I30_Y_0, syncram_2pZ0_GND => - RAM_CTRLR_v2_GND, syncram_2pZ0_VCC => RAM_CTRLR_v2_VCC, - ram_write_i => ram_write_i); - - un1_counter_1_ADD_8x8_medium_area_I26_Y_0 : AX1E - port map(A => N120, B => N135_i, C => N121, Y => - ADD_8x8_medium_area_I26_Y_0); - - \counter_RNO[1]\ : NOR2A - port map(A => I_27, B => raddr_rst, Y => \counter_3[1]\); - - un1_counter_1_ADD_8x8_medium_area_I0_CO1 : OR3B - port map(A => waddr_previous(0), B => \counter[0]_net_1\, C - => waddr_previous(1), Y => N116); - - \un2_waddr_0_x2[6]\ : XOR2 - port map(A => waddr_previous(1), B => waddr_previous(0), Y - => N_5_i); - - un1_counter_1_ADD_8x8_medium_area_I4_CO1 : OR2B - port map(A => \counter[4]_net_1\, B => N_5_i, Y => N124); - - un1_counter_I_28 : XOR2 - port map(A => \counter[4]_net_1\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_28); - - un1_counter_1_ADD_8x8_medium_area_I3_S_0 : XOR2 - port map(A => \counter[3]_net_1\, B => N_5_i, Y => N121); - - un1_counter_1_ADD_8x8_medium_area_I25_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[2]_net_1\, C => N135_i, - Y => ADD_8x8_medium_area_I25_Y_0); - - un1_counter_I_42 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \counter[4]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_1[0]\); - - un1_counter_1_ADD_8x8_medium_area_I30_Y_0 : XOR3 - port map(A => N_5_i, B => \counter[7]_net_1\, C => N149, Y - => ADD_8x8_medium_area_I30_Y_0); - - un1_counter_I_35 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => - \counter[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1[0]\); - - \counter[4]\ : DFN1C0 - port map(D => \counter_3[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[4]_net_1\); - - un1_counter_1_ADD_8x8_medium_area_I20_un1_Y_0 : OR2 - port map(A => \counter[4]_net_1\, B => N125_i, Y => - ADD_8x8_medium_area_I20_un1_Y_0); - - \counter[5]\ : DFN1C0 - port map(D => \counter_3[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[5]_net_1\); - - un1_counter_I_34 : XOR2 - port map(A => \counter[7]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => I_34); - - un1_counter_1_ADD_8x8_medium_area_I21_Y : MX2A - port map(A => N147, B => N_5_i, S => \counter[6]_net_1\, Y - => N149); - - \counter_RNO[2]\ : NOR2A - port map(A => I_32, B => raddr_rst, Y => \counter_3[2]\); - - GND_i : GND - port map(Y => \GND\); - - un1_counter_I_30 : XOR2 - port map(A => \counter[6]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_30); - - \counter_RNO[5]\ : NOR2A - port map(A => I_33, B => raddr_rst, Y => \counter_3[5]\); - - \counter_RNO[3]\ : NOR2A - port map(A => I_31, B => raddr_rst, Y => \counter_3[3]\); - - un1_counter_1_ADD_8x8_medium_area_I13_un1_Y_0 : OR2 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - Y => ADD_8x8_medium_area_I13_un1_Y_0); - - \counter[1]\ : DFN1C0 - port map(D => \counter_3[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[1]_net_1\); - - \counter[3]\ : DFN1C0 - port map(D => \counter_3[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[3]_net_1\); - - un1_counter_I_39 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - un1_counter_1_ADD_8x8_medium_area_I0_S_0 : AX1 - port map(A => waddr_previous(1), B => waddr_previous(0), C - => \counter[0]_net_1\, Y => ADD_8x8_medium_area_I0_S_0); - - un1_counter_I_47 : AND2 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - Y => \DWACT_ADD_CI_0_pog_array_1[0]\); - - un1_counter_I_19 : XOR2 - port map(A => \counter[0]_net_1\, B => raddr_add1, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \counter_RNO[6]\ : NOR2A - port map(A => I_30, B => raddr_rst, Y => \counter_3[6]\); - - un1_counter_I_1 : AND2 - port map(A => \counter[0]_net_1\, B => raddr_add1, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - un1_counter_1_ADD_8x8_medium_area_I5_S_0 : XNOR2 - port map(A => \counter[5]_net_1\, B => N_5_i, Y => N125_i); - - un1_counter_1_ADD_8x8_medium_area_I13_Y : OA1 - port map(A => N135_i, B => ADD_8x8_medium_area_I13_un1_Y_0, - C => ADD_8x8_medium_area_I13_Y_0, Y => N145_i); - - un1_counter_I_33 : XOR2 - port map(A => \counter[5]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_33); - - un1_counter_I_32 : XOR2 - port map(A => \counter[2]_net_1\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_32); - - un1_counter_I_27 : XOR2 - port map(A => \counter[1]_net_1\, B => - \DWACT_ADD_CI_0_TMP[0]\, Y => I_27); - - un1_counter_1_ADD_8x8_medium_area_I27_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[4]_net_1\, C => N145_i, - Y => ADD_8x8_medium_area_I27_Y_0); - - un1_counter_1_ADD_8x8_medium_area_I28_Y_0 : AX1C - port map(A => N124, B => N145_i, C => N125_i, Y => - ADD_8x8_medium_area_I28_Y_0); - - un1_counter_1_ADD_8x8_medium_area_I24_Y_0 : XNOR3 - port map(A => N116, B => \counter[1]_net_1\, C => N_5_i, Y - => ADD_8x8_medium_area_I24_Y_0); - - \counter_RNO[7]\ : NOR2A - port map(A => I_34, B => raddr_rst, Y => \counter_3[7]\); - - un1_counter_1_ADD_8x8_medium_area_I2_CO1 : OR2B - port map(A => \counter[2]_net_1\, B => N_5_i, Y => N120); - - \counter[0]\ : DFN1C0 - port map(D => \counter_3[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[0]_net_1\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2_DATAFLOW is - - port( alu_ctrl : in std_logic_vector(2 downto 0); - S : out std_logic_vector(8 to 8); - S_i_0 : out std_logic_vector(33 to 33); - alu_sel_coeff : in std_logic_vector(4 downto 0); - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - waddr_previous : in std_logic_vector(1 downto 0); - sample_0 : in std_logic_vector(14 downto 0); - sample_in_buf : in std_logic_vector(143 downto 129); - ram_sel_Wdata : in std_logic_vector(1 downto 0); - sample_out_s_0 : out std_logic; - sample_out_s_1 : out std_logic; - sample_out_s_3 : out std_logic; - sample_out_s_2 : out std_logic; - sample_out_s_10 : out std_logic; - sample_out_s_15 : out std_logic; - sample_out_s_14 : out std_logic; - sample_out_s_13 : out std_logic; - sample_out_s_12 : out std_logic; - sample_out_s_11 : out std_logic; - sample_out_s_9 : out std_logic; - sample_out_s_8 : out std_logic; - sample_out_s_7 : out std_logic; - sample_out_s_6 : out std_logic; - sample_out_s_5 : out std_logic; - sample_out_s_4 : out std_logic; - sample_in_s_1 : in std_logic_vector(17 to 17); - in_sel_src : in std_logic_vector(1 downto 0); - raddr_rst : in std_logic; - raddr_add1 : in std_logic; - ram_write : in std_logic; - IIR_CEL_CTRLR_v2_DATAFLOW_GND : in std_logic; - IIR_CEL_CTRLR_v2_DATAFLOW_VCC : in std_logic; - ram_write_i : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_val_delay : in std_logic; - alu_sel_input : in std_logic - ); - -end IIR_CEL_CTRLR_v2_DATAFLOW; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2_DATAFLOW is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MUXN_9_5 - port( alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - S_i_0 : out std_logic_vector(33 to 33); - S : out std_logic_vector(8 to 8); - alu_coef_s : out std_logic_vector(8 downto 0) - ); - end component; - - component ALU - port( alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - sample_out_s : out std_logic_vector(17 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component RAM_CTRLR_v2 - port( ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - DIN_REG1 : out std_logic_vector(15 to 15); - ram_output_16 : out std_logic; - ram_output_0 : out std_logic; - ram_output_17 : out std_logic; - ram_output_15 : out std_logic; - ram_output_14 : out std_logic; - ram_output_13 : out std_logic; - ram_output_12 : out std_logic; - ram_output_11 : out std_logic; - ram_output_10 : out std_logic; - ram_output_9 : out std_logic; - ram_output_8 : out std_logic; - ram_output_7 : out std_logic; - ram_output_6 : out std_logic; - ram_output_5 : out std_logic; - ram_output_4 : out std_logic; - ram_output_3 : out std_logic; - ram_output_1 : out std_logic; - reg_sample_in : in std_logic_vector(6 downto 5) := (others => 'U'); - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15) := (others => 'U'); - alu_sample_1 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_10 : out std_logic; - waddr_previous : in std_logic_vector(1 downto 0) := (others => 'U'); - ram_write_i : in std_logic := 'U'; - RAM_CTRLR_v2_VCC : in std_logic := 'U'; - RAM_CTRLR_v2_GND : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - alu_sel_input : in std_logic := 'U'; - I_1_RNI3I3E3 : out std_logic; - raddr_add1 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - raddr_rst : in std_logic := 'U' - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \reg_sample_in_RNIFA3C[15]_net_1\, - \reg_sample_in[15]_net_1\, \DIN_REG1[15]\, - \reg_sample_in6\, N_318, \ram_output[4]\, - \sample_in_s_27[4]\, N_319, \ram_output[5]\, - \sample_in_s_25[5]\, N_320, \ram_output[6]\, - \sample_in_s_23[6]\, N_321, \ram_output[7]\, - \sample_in_s_21[7]\, N_322, \ram_output[8]\, - \sample_in_s_19[8]\, N_323, \ram_output[9]\, - \sample_in_s_17[9]\, N_324, \ram_output[10]\, - \sample_in_s_15[10]\, N_325, \ram_output[11]\, - \sample_in_s_13[11]\, N_326, \ram_output[12]\, - \sample_in_s_11[12]\, N_327, \ram_output[13]\, - \sample_in_s_9[13]\, N_328, \ram_output[14]\, - \sample_in_s_7[14]\, N_329, \ram_output[15]\, N_331, - \ram_output[17]\, \reg_sample_in_5[4]\, - reg_sample_in_5_sn_N_2_i, \reg_sample_in_5[5]\, - \reg_sample_in_5[6]\, \reg_sample_in_5[7]\, - \reg_sample_in_5[8]\, \reg_sample_in_5[9]\, - \reg_sample_in_5[11]\, \reg_sample_in_5[12]\, - \reg_sample_in_5[13]\, \reg_sample_in_5[14]\, - \reg_sample_in_5[15]\, \reg_sample_in_5[17]\, - \sample_out_s[17]\, N_358, \reg_sample_in[4]_net_1\, - \sample_out_s[4]\, N_359, \reg_sample_in[5]_net_1\, - \sample_out_s[5]\, N_360, \reg_sample_in[6]_net_1\, - \sample_out_s[6]\, N_361, \reg_sample_in[7]_net_1\, - \sample_out_s[7]\, N_362, \reg_sample_in[8]_net_1\, - \sample_out_s[8]\, N_363, \reg_sample_in[9]_net_1\, - \sample_out_s[9]\, N_364, \reg_sample_in[10]_net_1\, - N_365, \reg_sample_in[11]_net_1\, \sample_out_s[11]\, - N_366, \reg_sample_in[12]_net_1\, \sample_out_s[12]\, - N_367, \reg_sample_in[13]_net_1\, \sample_out_s[13]\, - N_368, \reg_sample_in[14]_net_1\, \sample_out_s[14]\, - N_369, \sample_out_s[15]\, N_371, - \reg_sample_in[17]_net_1\, \ram_input[4]\, \ram_input[5]\, - \ram_input[6]\, \ram_input[7]\, \ram_input[8]\, - \ram_input[9]\, \ram_input[10]\, \ram_input[11]\, - \ram_input[12]\, \ram_input[13]\, \ram_input[14]\, - \ram_input[15]\, \ram_input[17]\, \alu_sample[1]\, - \reg_sample_in[1]_net_1\, \ram_output[1]\, - \alu_sample[2]\, \reg_sample_in[2]_net_1\, I_1_RNI3I3E3, - \alu_sample[3]\, \reg_sample_in[3]_net_1\, - \ram_output[3]\, \alu_sample[4]\, \alu_sample[7]\, - \alu_sample[8]\, \alu_sample[9]\, \alu_sample[11]\, - \alu_sample[12]\, \alu_sample[13]\, \alu_sample[14]\, - \alu_sample[17]\, N_316, \sample_in_s_31[2]\, N_317, - \sample_in_s_29[3]\, \reg_sample_in_5[2]\, - \reg_sample_in_5[3]\, N_356, \sample_out_s[2]\, N_357, - \sample_out_s[3]\, \ram_input[2]\, \ram_input[3]\, N_315, - \sample_in_s_33[1]\, \reg_sample_in_5[1]\, N_355, - \sample_out_s[1]\, \ram_input[1]\, \alu_sample[10]\, - \reg_sample_in_5[10]\, \sample_out_s[10]\, - \sample_in_s_35[0]\, \ram_input[0]\, N_354, - \ram_output[0]\, \reg_sample_in[0]_net_1\, - \reg_sample_in_5[0]\, \sample_out_s[0]\, N_314, - \alu_sample[0]\, \alu_sample[16]\, - \reg_sample_in[16]_net_1\, \ram_output[16]\, - \ram_input[16]\, N_370, \sample_out_s[16]\, - \reg_sample_in_5[16]\, N_330, \alu_sample[6]\, - \alu_sample[5]\, \alu_sample[15]\, \alu_coef_s[0]\, - \alu_coef_s[1]\, \alu_coef_s[2]\, \alu_coef_s[3]\, - \alu_coef_s[4]\, \alu_coef_s[5]\, \alu_coef_s[6]\, - \alu_coef_s[7]\, \alu_coef_s[8]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : MUXN_9_5 - Use entity work.MUXN_9_5(DEF_ARCH); - for all : ALU - Use entity work.ALU(DEF_ARCH); - for all : RAM_CTRLR_v2 - Use entity work.RAM_CTRLR_v2(DEF_ARCH); -begin - - sample_out_s_0 <= \sample_out_s[0]\; - sample_out_s_1 <= \sample_out_s[1]\; - sample_out_s_3 <= \sample_out_s[3]\; - sample_out_s_2 <= \sample_out_s[2]\; - sample_out_s_10 <= \sample_out_s[10]\; - sample_out_s_15 <= \sample_out_s[15]\; - sample_out_s_14 <= \sample_out_s[14]\; - sample_out_s_13 <= \sample_out_s[13]\; - sample_out_s_12 <= \sample_out_s[12]\; - sample_out_s_11 <= \sample_out_s[11]\; - sample_out_s_9 <= \sample_out_s[9]\; - sample_out_s_8 <= \sample_out_s[8]\; - sample_out_s_7 <= \sample_out_s[7]\; - sample_out_s_6 <= \sample_out_s[6]\; - sample_out_s_5 <= \sample_out_s[5]\; - sample_out_s_4 <= \sample_out_s[4]\; - - \reg_sample_in_RNO_1[10]\ : MX2 - port map(A => sample_in_buf(133), B => sample_0(10), S => - sample_val_delay, Y => \sample_in_s_15[10]\); - - \reg_sample_in_RNO[2]\ : MX2 - port map(A => \sample_out_s[2]\, B => N_316, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[2]\); - - \reg_sample_in_RNIO8MA4[8]\ : MX2 - port map(A => N_362, B => \ram_output[8]\, S => - ram_sel_Wdata(1), Y => \ram_input[8]\); - - \reg_sample_in_RNO_1[1]\ : MX2 - port map(A => sample_in_buf(142), B => sample_0(1), S => - sample_val_delay, Y => \sample_in_s_33[1]\); - - \reg_sample_in_RNIUJBJ[12]\ : MX2 - port map(A => \reg_sample_in[12]_net_1\, B => - \sample_out_s[12]\, S => ram_sel_Wdata(0), Y => N_366); - - \reg_sample_in_RNIJLRL3[11]\ : MX2 - port map(A => \reg_sample_in[11]_net_1\, B => - \ram_output[11]\, S => alu_sel_input, Y => - \alu_sample[11]\); - - \reg_sample_in_RNO_0[7]\ : MX2 - port map(A => \ram_output[7]\, B => \sample_in_s_21[7]\, S - => in_sel_src(0), Y => N_321); - - \reg_sample_in_RNIPLRL3[14]\ : MX2 - port map(A => \reg_sample_in[14]_net_1\, B => - \ram_output[14]\, S => alu_sel_input, Y => - \alu_sample[14]\); - - \reg_sample_in_RNII1984[2]\ : MX2 - port map(A => N_356, B => I_1_RNI3I3E3, S => - ram_sel_Wdata(1), Y => \ram_input[2]\); - - \reg_sample_in[5]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[5]_net_1\); - - \reg_sample_in_RNI0HPO[5]\ : MX2C - port map(A => \reg_sample_in[5]_net_1\, B => - \sample_out_s[5]\, S => ram_sel_Wdata(0), Y => N_359); - - \reg_sample_in_RNISOMA4[9]\ : MX2 - port map(A => N_363, B => \ram_output[9]\, S => - ram_sel_Wdata(1), Y => \ram_input[9]\); - - \reg_sample_in_RNI1U5Q3[0]\ : MX2 - port map(A => \reg_sample_in[0]_net_1\, B => - \ram_output[0]\, S => alu_sel_input, Y => \alu_sample[0]\); - - \reg_sample_in_RNIJ68Q3[9]\ : MX2 - port map(A => \reg_sample_in[9]_net_1\, B => - \ram_output[9]\, S => alu_sel_input, Y => \alu_sample[9]\); - - \reg_sample_in_RNI4OJA4[3]\ : MX2 - port map(A => N_357, B => \ram_output[3]\, S => - ram_sel_Wdata(1), Y => \ram_input[3]\); - - \reg_sample_in_RNO_0[0]\ : MX2 - port map(A => \ram_output[0]\, B => \sample_in_s_35[0]\, S - => in_sel_src(0), Y => N_314); - - \reg_sample_in_RNO_0[1]\ : MX2 - port map(A => \ram_output[1]\, B => \sample_in_s_33[1]\, S - => in_sel_src(0), Y => N_315); - - \reg_sample_in_RNI3TPO[6]\ : MX2C - port map(A => \reg_sample_in[6]_net_1\, B => - \sample_out_s[6]\, S => ram_sel_Wdata(0), Y => N_360); - - \reg_sample_in_RNO_0[2]\ : MX2 - port map(A => I_1_RNI3I3E3, B => \sample_in_s_31[2]\, S => - in_sel_src(0), Y => N_316); - - \reg_sample_in_RNIT4PO[4]\ : MX2 - port map(A => \reg_sample_in[4]_net_1\, B => - \sample_out_s[4]\, S => ram_sel_Wdata(0), Y => N_358); - - \reg_sample_in_RNO[11]\ : MX2 - port map(A => \sample_out_s[11]\, B => N_325, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[11]\); - - \reg_sample_in_RNO_1[2]\ : MX2 - port map(A => sample_in_buf(141), B => sample_0(2), S => - sample_val_delay, Y => \sample_in_s_31[2]\); - - \reg_sample_in_RNO_0[11]\ : MX2 - port map(A => \ram_output[11]\, B => \sample_in_s_13[11]\, - S => in_sel_src(0), Y => N_325); - - \reg_sample_in_RNIU7964[15]\ : MX2 - port map(A => N_369, B => \ram_output[15]\, S => - ram_sel_Wdata(1), Y => \ram_input[15]\); - - reg_sample_in6 : NOR2 - port map(A => in_sel_src(1), B => in_sel_src(0), Y => - \reg_sample_in6\); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg_sample_in_RNO[13]\ : MX2 - port map(A => \sample_out_s[13]\, B => N_327, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[13]\); - - \reg_sample_in[3]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[3]_net_1\); - - \reg_sample_in_RNO_1[9]\ : MX2 - port map(A => sample_in_buf(134), B => sample_0(9), S => - sample_val_delay, Y => \sample_in_s_17[9]\); - - \reg_sample_in_RNO[4]\ : MX2 - port map(A => \sample_out_s[4]\, B => N_318, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[4]\); - - \reg_sample_in[7]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[7]_net_1\); - - \reg_sample_in[14]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[14]_net_1\); - - \reg_sample_in_RNILLRL3[12]\ : MX2 - port map(A => \reg_sample_in[12]_net_1\, B => - \ram_output[12]\, S => alu_sel_input, Y => - \alu_sample[12]\); - - \reg_sample_in_RNIEP884[1]\ : MX2 - port map(A => N_355, B => \ram_output[1]\, S => - ram_sel_Wdata(1), Y => \ram_input[1]\); - - \reg_sample_in_RNO[3]\ : MX2 - port map(A => \sample_out_s[3]\, B => N_317, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[3]\); - - \reg_sample_in_RNI5E6Q3[2]\ : MX2 - port map(A => \reg_sample_in[2]_net_1\, B => I_1_RNI3I3E3, - S => alu_sel_input, Y => \alu_sample[2]\); - - \reg_sample_in_RNO_1[11]\ : MX2 - port map(A => sample_in_buf(132), B => sample_0(11), S => - sample_val_delay, Y => \sample_in_s_13[11]\); - - \reg_sample_in_RNO[1]\ : MX2 - port map(A => \sample_out_s[1]\, B => N_315, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[1]\); - - \reg_sample_in_RNI9U6Q3[4]\ : MX2 - port map(A => \reg_sample_in[4]_net_1\, B => - \ram_output[4]\, S => alu_sel_input, Y => \alu_sample[4]\); - - \reg_sample_in[9]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[9]_net_1\); - - \reg_sample_in_RNO_0[15]\ : MX2 - port map(A => \ram_output[15]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_329); - - \reg_sample_in_RNO[8]\ : MX2 - port map(A => \sample_out_s[8]\, B => N_322, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[8]\); - - \reg_sample_in_RNO[12]\ : MX2 - port map(A => \sample_out_s[12]\, B => N_326, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[12]\); - - \reg_sample_in_RNI6O964[17]\ : MX2 - port map(A => N_371, B => \ram_output[17]\, S => - ram_sel_Wdata(1), Y => \ram_input[17]\); - - \reg_sample_in_RNIFB9J[13]\ : MX2 - port map(A => \reg_sample_in[13]_net_1\, B => - \sample_out_s[13]\, S => ram_sel_Wdata(0), Y => N_367); - - \reg_sample_in_RNIRBBJ[11]\ : MX2 - port map(A => \reg_sample_in[11]_net_1\, B => - \sample_out_s[11]\, S => ram_sel_Wdata(0), Y => N_365); - - \reg_sample_in_RNIQOOO[3]\ : MX2 - port map(A => \reg_sample_in[3]_net_1\, B => - \sample_out_s[3]\, S => ram_sel_Wdata(0), Y => N_357); - - \reg_sample_in_RNIFA3C[15]\ : MX2 - port map(A => \reg_sample_in[15]_net_1\, B => - \DIN_REG1[15]\, S => alu_sel_input, Y => - \reg_sample_in_RNIFA3C[15]_net_1\); - - \reg_sample_in_RNI0OA64[11]\ : MX2 - port map(A => N_365, B => \ram_output[11]\, S => - ram_sel_Wdata(1), Y => \ram_input[11]\); - - \reg_sample_in_RNO_0[16]\ : MX2 - port map(A => \ram_output[16]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_330); - - \reg_sample_in_RNIIJ9J[14]\ : MX2 - port map(A => \reg_sample_in[14]_net_1\, B => - \sample_out_s[14]\, S => ram_sel_Wdata(0), Y => N_368); - - \reg_sample_in[16]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[16]_net_1\); - - \reg_sample_in_RNO_1[5]\ : MX2C - port map(A => sample_in_buf(138), B => sample_0(5), S => - sample_val_delay, Y => \sample_in_s_25[5]\); - - \reg_sample_in_RNIVLRL3[17]\ : MX2 - port map(A => \reg_sample_in[17]_net_1\, B => - \ram_output[17]\, S => alu_sel_input, Y => - \alu_sample[17]\); - - \reg_sample_in_RNIFM7Q3[7]\ : MX2 - port map(A => \reg_sample_in[7]_net_1\, B => - \ram_output[7]\, S => alu_sel_input, Y => \alu_sample[7]\); - - Coeff_Mux : MUXN_9_5 - port map(alu_sel_coeff_0_0 => alu_sel_coeff_0_0, - alu_sel_coeff_0_2 => alu_sel_coeff_0_2, alu_sel_coeff(4) - => alu_sel_coeff(4), alu_sel_coeff(3) => - alu_sel_coeff(3), alu_sel_coeff(2) => alu_sel_coeff(2), - alu_sel_coeff(1) => alu_sel_coeff(1), alu_sel_coeff(0) - => alu_sel_coeff(0), S_i_0(33) => S_i_0(33), S(8) => - S(8), alu_coef_s(8) => \alu_coef_s[8]\, alu_coef_s(7) => - \alu_coef_s[7]\, alu_coef_s(6) => \alu_coef_s[6]\, - alu_coef_s(5) => \alu_coef_s[5]\, alu_coef_s(4) => - \alu_coef_s[4]\, alu_coef_s(3) => \alu_coef_s[3]\, - alu_coef_s(2) => \alu_coef_s[2]\, alu_coef_s(1) => - \alu_coef_s[1]\, alu_coef_s(0) => \alu_coef_s[0]\); - - ALU_1 : ALU - port map(alu_ctrl(2) => alu_ctrl(2), alu_ctrl(1) => - alu_ctrl(1), alu_ctrl(0) => alu_ctrl(0), alu_coef_s(8) - => \alu_coef_s[8]\, alu_coef_s(7) => \alu_coef_s[7]\, - alu_coef_s(6) => \alu_coef_s[6]\, alu_coef_s(5) => - \alu_coef_s[5]\, alu_coef_s(4) => \alu_coef_s[4]\, - alu_coef_s(3) => \alu_coef_s[3]\, alu_coef_s(2) => - \alu_coef_s[2]\, alu_coef_s(1) => \alu_coef_s[1]\, - alu_coef_s(0) => \alu_coef_s[0]\, alu_sample(17) => - \alu_sample[17]\, alu_sample(16) => \alu_sample[16]\, - alu_sample(15) => \alu_sample[15]\, alu_sample(14) => - \alu_sample[14]\, alu_sample(13) => \alu_sample[13]\, - alu_sample(12) => \alu_sample[12]\, alu_sample(11) => - \alu_sample[11]\, alu_sample(10) => \alu_sample[10]\, - alu_sample(9) => \alu_sample[9]\, alu_sample(8) => - \alu_sample[8]\, alu_sample(7) => \alu_sample[7]\, - alu_sample(6) => \alu_sample[6]\, alu_sample(5) => - \alu_sample[5]\, alu_sample(4) => \alu_sample[4]\, - alu_sample(3) => \alu_sample[3]\, alu_sample(2) => - \alu_sample[2]\, alu_sample(1) => \alu_sample[1]\, - alu_sample(0) => \alu_sample[0]\, sample_out_s(17) => - \sample_out_s[17]\, sample_out_s(16) => - \sample_out_s[16]\, sample_out_s(15) => - \sample_out_s[15]\, sample_out_s(14) => - \sample_out_s[14]\, sample_out_s(13) => - \sample_out_s[13]\, sample_out_s(12) => - \sample_out_s[12]\, sample_out_s(11) => - \sample_out_s[11]\, sample_out_s(10) => - \sample_out_s[10]\, sample_out_s(9) => \sample_out_s[9]\, - sample_out_s(8) => \sample_out_s[8]\, sample_out_s(7) => - \sample_out_s[7]\, sample_out_s(6) => \sample_out_s[6]\, - sample_out_s(5) => \sample_out_s[5]\, sample_out_s(4) => - \sample_out_s[4]\, sample_out_s(3) => \sample_out_s[3]\, - sample_out_s(2) => \sample_out_s[2]\, sample_out_s(1) => - \sample_out_s[1]\, sample_out_s(0) => \sample_out_s[0]\, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c); - - \reg_sample_in_RNI7M6Q3[3]\ : MX2 - port map(A => \reg_sample_in[3]_net_1\, B => - \ram_output[3]\, S => alu_sel_input, Y => \alu_sample[3]\); - - \reg_sample_in[8]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[8]_net_1\); - - \reg_sample_in[13]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[13]_net_1\); - - \reg_sample_in[12]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[12]_net_1\); - - \reg_sample_in_RNISFA64[10]\ : MX2 - port map(A => N_364, B => \ram_output[10]\, S => - ram_sel_Wdata(1), Y => \ram_input[10]\); - - \reg_sample_in_RNIHLRL3[10]\ : MX2 - port map(A => \reg_sample_in[10]_net_1\, B => - \ram_output[10]\, S => alu_sel_input, Y => - \alu_sample[10]\); - - \reg_sample_in_RNI88KA4[4]\ : MX2 - port map(A => N_358, B => \ram_output[4]\, S => - ram_sel_Wdata(1), Y => \ram_input[4]\); - - \reg_sample_in_RNI62EM[1]\ : MX2 - port map(A => \reg_sample_in[1]_net_1\, B => - \sample_out_s[1]\, S => ram_sel_Wdata(0), Y => N_355); - - \reg_sample_in[10]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[10]_net_1\); - - \reg_sample_in[6]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[6]_net_1\); - - \reg_sample_in[1]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[1]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \reg_sample_in_RNO[10]\ : MX2 - port map(A => \sample_out_s[10]\, B => N_324, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[10]\); - - \reg_sample_in_RNIC1RO[9]\ : MX2 - port map(A => \reg_sample_in[9]_net_1\, B => - \sample_out_s[9]\, S => ram_sel_Wdata(0), Y => N_363); - - \reg_sample_in_RNIQV864[14]\ : MX2 - port map(A => N_368, B => \ram_output[14]\, S => - ram_sel_Wdata(1), Y => \ram_input[14]\); - - \reg_sample_in_RNIO3AJ[16]\ : MX2 - port map(A => \reg_sample_in[16]_net_1\, B => - \sample_out_s[16]\, S => ram_sel_Wdata(0), Y => N_370); - - \reg_sample_in_RNO_0[5]\ : MX2C - port map(A => \ram_output[5]\, B => \sample_in_s_25[5]\, S - => in_sel_src(0), Y => N_319); - - \reg_sample_in_RNIAH884[0]\ : MX2 - port map(A => N_354, B => \ram_output[0]\, S => - ram_sel_Wdata(1), Y => \ram_input[0]\); - - \reg_sample_in[2]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[2]_net_1\); - - \reg_sample_in_RNO_1[4]\ : MX2 - port map(A => sample_in_buf(139), B => sample_0(4), S => - sample_val_delay, Y => \sample_in_s_27[4]\); - - \reg_sample_in_RNI40B64[12]\ : MX2 - port map(A => N_366, B => \ram_output[12]\, S => - ram_sel_Wdata(1), Y => \ram_input[12]\); - - \reg_sample_in_RNIO3BJ[10]\ : MX2 - port map(A => \reg_sample_in[10]_net_1\, B => - \sample_out_s[10]\, S => ram_sel_Wdata(0), Y => N_364); - - \reg_sample_in[17]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[17]_net_1\); - - \reg_sample_in_RNO[7]\ : MX2 - port map(A => \sample_out_s[7]\, B => N_321, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[7]\); - - \reg_sample_in_RNO[16]\ : MX2 - port map(A => \sample_out_s[16]\, B => N_330, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[16]\); - - \reg_sample_in_RNI9LQO[8]\ : MX2 - port map(A => \reg_sample_in[8]_net_1\, B => - \sample_out_s[8]\, S => ram_sel_Wdata(0), Y => N_362); - - \reg_sample_in[4]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[4]_net_1\); - - \reg_sample_in_RNO_1[7]\ : MX2 - port map(A => sample_in_buf(136), B => sample_0(7), S => - sample_val_delay, Y => \sample_in_s_21[7]\); - - \reg_sample_in_RNO_1[3]\ : MX2 - port map(A => sample_in_buf(140), B => sample_0(3), S => - sample_val_delay, Y => \sample_in_s_29[3]\); - - \reg_sample_in_RNO_0[12]\ : MX2 - port map(A => \ram_output[12]\, B => \sample_in_s_11[12]\, - S => in_sel_src(0), Y => N_326); - - \reg_sample_in_RNO[6]\ : MX2 - port map(A => \sample_out_s[6]\, B => N_320, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[6]\); - - \reg_sample_in[15]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[15]_net_1\); - - \reg_sample_in_RNO_0[4]\ : MX2 - port map(A => \ram_output[4]\, B => \sample_in_s_27[4]\, S - => in_sel_src(0), Y => N_318); - - \reg_sample_in_RNO_0[3]\ : MX2 - port map(A => \ram_output[3]\, B => \sample_in_s_29[3]\, S - => in_sel_src(0), Y => N_317); - - \reg_sample_in_RNO_0[17]\ : MX2 - port map(A => \ram_output[17]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_331); - - \reg_sample_in_RNO[17]\ : MX2 - port map(A => \sample_out_s[17]\, B => N_331, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[17]\); - - \reg_sample_in_RNO[14]\ : MX2 - port map(A => \sample_out_s[14]\, B => N_328, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[14]\); - - \reg_sample_in_RNIRBAJ[17]\ : MX2 - port map(A => \reg_sample_in[17]_net_1\, B => - \sample_out_s[17]\, S => ram_sel_Wdata(0), Y => N_371); - - \reg_sample_in_RNO_1[8]\ : MX2 - port map(A => sample_in_buf(135), B => sample_0(8), S => - sample_val_delay, Y => \sample_in_s_19[8]\); - - \reg_sample_in_RNI3UDM[0]\ : MX2 - port map(A => \reg_sample_in[0]_net_1\, B => - \sample_out_s[0]\, S => ram_sel_Wdata(0), Y => N_354); - - \reg_sample_in[11]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[11]_net_1\); - - \reg_sample_in_RNO[5]\ : MX2 - port map(A => \sample_out_s[5]\, B => N_319, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[5]\); - - \reg_sample_in_RNO_0[9]\ : MX2 - port map(A => \ram_output[9]\, B => \sample_in_s_17[9]\, S - => in_sel_src(0), Y => N_323); - - \reg_sample_in_RNO[9]\ : MX2 - port map(A => \sample_out_s[9]\, B => N_323, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[9]\); - - RAM_CTRLR_v2_1 : RAM_CTRLR_v2 - port map(ram_input(17) => \ram_input[17]\, ram_input(16) - => \ram_input[16]\, ram_input(15) => \ram_input[15]\, - ram_input(14) => \ram_input[14]\, ram_input(13) => - \ram_input[13]\, ram_input(12) => \ram_input[12]\, - ram_input(11) => \ram_input[11]\, ram_input(10) => - \ram_input[10]\, ram_input(9) => \ram_input[9]\, - ram_input(8) => \ram_input[8]\, ram_input(7) => - \ram_input[7]\, ram_input(6) => \ram_input[6]\, - ram_input(5) => \ram_input[5]\, ram_input(4) => - \ram_input[4]\, ram_input(3) => \ram_input[3]\, - ram_input(2) => \ram_input[2]\, ram_input(1) => - \ram_input[1]\, ram_input(0) => \ram_input[0]\, - DIN_REG1(15) => \DIN_REG1[15]\, ram_output_16 => - \ram_output[16]\, ram_output_0 => \ram_output[0]\, - ram_output_17 => \ram_output[17]\, ram_output_15 => - \ram_output[15]\, ram_output_14 => \ram_output[14]\, - ram_output_13 => \ram_output[13]\, ram_output_12 => - \ram_output[12]\, ram_output_11 => \ram_output[11]\, - ram_output_10 => \ram_output[10]\, ram_output_9 => - \ram_output[9]\, ram_output_8 => \ram_output[8]\, - ram_output_7 => \ram_output[7]\, ram_output_6 => - \ram_output[6]\, ram_output_5 => \ram_output[5]\, - ram_output_4 => \ram_output[4]\, ram_output_3 => - \ram_output[3]\, ram_output_1 => \ram_output[1]\, - reg_sample_in(6) => \reg_sample_in[6]_net_1\, - reg_sample_in(5) => \reg_sample_in[5]_net_1\, - reg_sample_in_RNIFA3C(15) => - \reg_sample_in_RNIFA3C[15]_net_1\, alu_sample_1 => - \alu_sample[6]\, alu_sample_0 => \alu_sample[5]\, - alu_sample_10 => \alu_sample[15]\, waddr_previous(1) => - waddr_previous(1), waddr_previous(0) => waddr_previous(0), - ram_write_i => ram_write_i, RAM_CTRLR_v2_VCC => - IIR_CEL_CTRLR_v2_DATAFLOW_VCC, RAM_CTRLR_v2_GND => - IIR_CEL_CTRLR_v2_DATAFLOW_GND, ram_write => ram_write, - alu_sel_input => alu_sel_input, I_1_RNI3I3E3 => - I_1_RNI3I3E3, raddr_add1 => raddr_add1, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, raddr_rst => raddr_rst); - - reg_sample_in_5_sn_m1 : OR2B - port map(A => in_sel_src(1), B => in_sel_src(0), Y => - reg_sample_in_5_sn_N_2_i); - - \reg_sample_in_RNO[15]\ : MX2 - port map(A => \sample_out_s[15]\, B => N_329, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[15]\); - - \reg_sample_in_RNO_0[14]\ : MX2 - port map(A => \ram_output[14]\, B => \sample_in_s_7[14]\, S - => in_sel_src(0), Y => N_328); - - \reg_sample_in_RNI96EM[2]\ : MX2 - port map(A => \reg_sample_in[2]_net_1\, B => - \sample_out_s[2]\, S => ram_sel_Wdata(0), Y => N_356); - - \reg_sample_in_RNO_1[12]\ : MX2 - port map(A => sample_in_buf(131), B => sample_0(12), S => - sample_val_delay, Y => \sample_in_s_11[12]\); - - \reg_sample_in_RNI366Q3[1]\ : MX2 - port map(A => \reg_sample_in[1]_net_1\, B => - \ram_output[1]\, S => alu_sel_input, Y => \alu_sample[1]\); - - \reg_sample_in_RNI69QO[7]\ : MX2 - port map(A => \reg_sample_in[7]_net_1\, B => - \sample_out_s[7]\, S => ram_sel_Wdata(0), Y => N_361); - - \reg_sample_in_RNIG8LA4[6]\ : MX2C - port map(A => N_360, B => \ram_output[6]\, S => - ram_sel_Wdata(1), Y => \ram_input[6]\); - - \reg_sample_in_RNO_0[8]\ : MX2 - port map(A => \ram_output[8]\, B => \sample_in_s_19[8]\, S - => in_sel_src(0), Y => N_322); - - \reg_sample_in_RNO_0[13]\ : MX2 - port map(A => \ram_output[13]\, B => \sample_in_s_9[13]\, S - => in_sel_src(0), Y => N_327); - - \reg_sample_in_RNO[0]\ : MX2 - port map(A => \sample_out_s[0]\, B => N_314, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[0]\); - - \reg_sample_in_RNITLRL3[16]\ : MX2 - port map(A => \reg_sample_in[16]_net_1\, B => - \ram_output[16]\, S => alu_sel_input, Y => - \alu_sample[16]\); - - \reg_sample_in_RNILR9J[15]\ : MX2 - port map(A => \reg_sample_in[15]_net_1\, B => - \sample_out_s[15]\, S => ram_sel_Wdata(0), Y => N_369); - - \reg_sample_in[0]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[0]_net_1\); - - \reg_sample_in_RNO_0[10]\ : MX2 - port map(A => \ram_output[10]\, B => \sample_in_s_15[10]\, - S => in_sel_src(0), Y => N_324); - - \reg_sample_in_RNIKOLA4[7]\ : MX2 - port map(A => N_361, B => \ram_output[7]\, S => - ram_sel_Wdata(1), Y => \ram_input[7]\); - - \reg_sample_in_RNI2G964[16]\ : MX2 - port map(A => N_370, B => \ram_output[16]\, S => - ram_sel_Wdata(1), Y => \ram_input[16]\); - - \reg_sample_in_RNINLRL3[13]\ : MX2 - port map(A => \reg_sample_in[13]_net_1\, B => - \ram_output[13]\, S => alu_sel_input, Y => - \alu_sample[13]\); - - \reg_sample_in_RNO_1[14]\ : MX2 - port map(A => sample_in_buf(129), B => sample_0(14), S => - sample_val_delay, Y => \sample_in_s_7[14]\); - - \reg_sample_in_RNO_1[6]\ : MX2C - port map(A => sample_in_buf(137), B => sample_0(6), S => - sample_val_delay, Y => \sample_in_s_23[6]\); - - \reg_sample_in_RNIHU7Q3[8]\ : MX2 - port map(A => \reg_sample_in[8]_net_1\, B => - \ram_output[8]\, S => alu_sel_input, Y => \alu_sample[8]\); - - \reg_sample_in_RNO_0[6]\ : MX2C - port map(A => \ram_output[6]\, B => \sample_in_s_23[6]\, S - => in_sel_src(0), Y => N_320); - - \reg_sample_in_RNO_1[13]\ : MX2 - port map(A => sample_in_buf(130), B => sample_0(13), S => - sample_val_delay, Y => \sample_in_s_9[13]\); - - \reg_sample_in_RNO_1[0]\ : MX2 - port map(A => sample_in_buf(143), B => sample_0(0), S => - sample_val_delay, Y => \sample_in_s_35[0]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \reg_sample_in_RNIMN864[13]\ : MX2 - port map(A => N_367, B => \ram_output[13]\, S => - ram_sel_Wdata(1), Y => \ram_input[13]\); - - \reg_sample_in_RNICOKA4[5]\ : MX2C - port map(A => N_359, B => \ram_output[5]\, S => - ram_sel_Wdata(1), Y => \ram_input[5]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2_CONTROL is - - port( alu_ctrl : out std_logic_vector(2 downto 0); - ram_sel_Wdata : out std_logic_vector(1 downto 0); - waddr_previous : out std_logic_vector(1 downto 0); - in_sel_src : out std_logic_vector(1 downto 0); - S_i_0 : in std_logic_vector(33 to 33); - S : in std_logic_vector(8 to 8); - alu_sel_coeff : out std_logic_vector(4 downto 0); - alu_sel_coeff_0_2 : out std_logic; - alu_sel_coeff_0_0 : out std_logic; - sample_out_rot_s : out std_logic; - sample_out_val_s : out std_logic; - raddr_rst : out std_logic; - alu_sel_input : out std_logic; - raddr_add1 : out std_logic; - sample_val_delay : in std_logic; - ram_write : out std_logic; - ram_write_i : out std_logic; - un1_sample_in_rotate : out std_logic; - sample_out_rot_s_0 : out std_logic; - sample_out_rot_s_1 : out std_logic; - sample_out_rot_s_2 : out std_logic; - sample_out_rot_s_3 : out std_logic; - sample_out_rot_s_4 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end IIR_CEL_CTRLR_v2_CONTROL; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2_CONTROL is - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \Chanel_ongoing_RNISG5D[13]_net_1\, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_7, N_270, - Chanel_ongoing_n20, \Chanel_ongoing[20]_net_1\, N_278, - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Chanel_ongoing_n21, - \Chanel_ongoing[21]_net_1\, N_279, Chanel_ongoing_n22, - \Chanel_ongoing[22]_net_1\, N_725, Chanel_ongoing_n28, - \Chanel_ongoing[28]_net_1\, N_293, - un1_alu_sel_input_0_sqmuxa_2_i_0, Chanel_ongoing_n29, - \Chanel_ongoing[29]_net_1\, N_295, Chanel_ongoing_n30, - \Chanel_ongoing[30]_net_1\, N_327, Chanel_ongoing_n31, - \Chanel_ongoing[31]_net_1\, N_335, N_250, - \Chanel_ongoing[0]_net_1\, \Chanel_ongoing[1]_net_1\, - \Chanel_ongoing[2]_net_1\, N_256, - \Chanel_ongoing[7]_net_1\, N_254, - \Chanel_ongoing[8]_net_1\, N_265, - \Chanel_ongoing[11]_net_1\, N_258, - \Chanel_ongoing[12]_net_1\, \Chanel_ongoing[13]_net_1\, - N_271, \Chanel_ongoing[14]_net_1\, N_272, - \Chanel_ongoing[15]_net_1\, N_273, - \Chanel_ongoing[16]_net_1\, N_275, - \Chanel_ongoing[17]_net_1\, N_276, - \Chanel_ongoing[18]_net_1\, \Chanel_ongoing[19]_net_1\, - N_288, \Chanel_ongoing[23]_net_1\, N_290, - \Chanel_ongoing[24]_net_1\, N_292, N_291, - \Chanel_ongoing[26]_net_1\, \Chanel_ongoing[27]_net_1\, - \Chanel_ongoing[9]_net_1\, \Chanel_ongoing[10]_net_1\, - \Chanel_ongoing[25]_net_1\, \Chanel_ongoing[5]_net_1\, - N_252, \Chanel_ongoing[6]_net_1\, - \Chanel_ongoing[3]_net_1\, \Chanel_ongoing[4]_net_1\, - N_75, \Cel_ongoing[29]_net_1\, \Cel_ongoing[30]_net_1\, - N_72, I129_un1_Y, \Cel_ongoing[13]_net_1\, N_28_0, - ADD_32x32_fast_I129_un1_Y_14, N_20_0, - \Cel_ongoing[3]_net_1\, N_18_0, \Cel_ongoing[4]_net_1\, - N_22_0, \Cel_ongoing[5]_net_1\, \Cel_ongoing[6]_net_1\, - N_24_0, \Cel_ongoing[7]_net_1\, \Cel_ongoing[8]_net_1\, - N_26_0, \Cel_ongoing[9]_net_1\, \Cel_ongoing[10]_net_1\, - \Cel_ongoing[11]_net_1\, \Cel_ongoing[12]_net_1\, N_44, - \Cel_ongoing[14]_net_1\, N_47, \Cel_ongoing[15]_net_1\, - \Cel_ongoing[16]_net_1\, N_48, N_51, - \Cel_ongoing[17]_net_1\, \Cel_ongoing[18]_net_1\, N_52, - N_55, \Cel_ongoing[19]_net_1\, \Cel_ongoing[20]_net_1\, - N_56, N_59, \Cel_ongoing[21]_net_1\, - \Cel_ongoing[22]_net_1\, N_60, N_63, - \Cel_ongoing[23]_net_1\, \Cel_ongoing[24]_net_1\, N_64, - N_66, \Cel_ongoing[25]_net_1\, N_68, - \Cel_ongoing[26]_net_1\, N_70, \Cel_ongoing[27]_net_1\, - \Cel_ongoing[28]_net_1\, \un1_IIR_CEL_STATE_17_i[17]\, - \Cel_ongoing_RNO[14]_net_1\, N_371_0, - \Cel_ongoing_RNO[15]_net_1\, N_435, N_436, N_437, N_438, - N_439, N_440, N_371, N_441, N_442, N_443, N_444, N_445, - N_446, N_447, N_448, N_449, N_450, - \Cel_ongoing[31]_net_1\, \Cel_ongoing[1]_net_1\, N_16_0, - \Cel_ongoing[2]_net_1\, \Cel_ongoing[0]_net_1\, N_566, - N_6, \IIR_CEL_STATE[4]_net_1\, \IIR_CEL_STATE_i[9]_net_1\, - \IIR_CEL_STATE[0]_net_1\, \IIR_CEL_STATE[1]_net_1\, - alu_selected_coeff_n0, alu_selected_coeffe, N_713, - N_567_i_0, \IIR_CEL_STATE[8]_net_1\, N_127_0, N_274, - un1_alu_sel_input_0_sqmuxa_2_i_0_s_0_0, N_452, N_248, - \sample_in_rot_RNI6EV7\, \IIR_CEL_STATE_i_i[9]\, - ADD_32x32_fast_I129_un1_Y_9, ADD_32x32_fast_I129_un1_Y_8, - ADD_32x32_fast_I129_un1_Y_13, ADD_32x32_fast_I129_un1_Y_5, - ADD_32x32_fast_I129_un1_Y_4, ADD_32x32_fast_I129_un1_Y_11, - ADD_32x32_fast_I129_un1_Y_7, ADD_32x32_fast_I129_un1_Y_3, - ADD_32x32_fast_I129_un1_Y_1, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_2, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_1, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_6, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_4, - Chanel_ongoing_n2_0_i_0_0, Chanel_ongoing_n7_0_i_0_0, - Chanel_ongoing_n6_0_i_0_0, Chanel_ongoing_n4_0_i_0_0, - Chanel_ongoing_n8_0_i_0_0, Chanel_ongoing_n5_0_i_0_0, - Chanel_ongoing_n1_0_i_0_0, alu_selected_coeff_n3_0_i_0, - N_717, N_733_1, N_294, N_453, alu_selected_coeff_n2_0_i_0, - \alu_sel_coeff_0[2]\, \Cel_ongoing_6_i_i_1[0]\, - \Cel_ongoing_6_i_i_a2_0_0[0]\, N_328, - \Cel_ongoing_6_i_i_0[0]\, - \un1_IIR_CEL_STATE_17_i_1_i_0[31]\, N_457, - un1_IIR_CEL_STATE_22_0_0, \IIR_CEL_STATE[5]_net_1\, - raddr_add1_2_i_a2_0_0, \IIR_CEL_STATE[3]_net_1\, - \in_sel_src_8_i_a2_0_a2_0_0[1]\, \IIR_CEL_STATE[6]_net_1\, - \IIR_CEL_STATE[7]_net_1\, Cel_ongoing_0_sqmuxa_0_a2_0_27, - Cel_ongoing_0_sqmuxa_0_a2_0_16, - Cel_ongoing_0_sqmuxa_0_a2_0_15, - Cel_ongoing_0_sqmuxa_0_a2_0_24, - Cel_ongoing_0_sqmuxa_0_a2_0_26, - Cel_ongoing_0_sqmuxa_0_a2_0_12, - Cel_ongoing_0_sqmuxa_0_a2_0_11, - Cel_ongoing_0_sqmuxa_0_a2_0_22, - Cel_ongoing_0_sqmuxa_0_a2_0_25, - Cel_ongoing_0_sqmuxa_0_a2_0_8, - Cel_ongoing_0_sqmuxa_0_a2_0_7, - Cel_ongoing_0_sqmuxa_0_a2_0_20, N_479, - Cel_ongoing_0_sqmuxa_0_a2_0_4, - Cel_ongoing_0_sqmuxa_0_a2_0_18, - Cel_ongoing_0_sqmuxa_0_a2_0_14, - Cel_ongoing_0_sqmuxa_0_a2_0_10, - Cel_ongoing_0_sqmuxa_0_a2_0_6, - Cel_ongoing_0_sqmuxa_0_a2_0_3, - Cel_ongoing_0_sqmuxa_0_a2_0_1, - \in_sel_src_8_i_a2_0_o2_0_27[1]\, - \in_sel_src_8_i_a2_0_o2_0_18[1]\, - \in_sel_src_8_i_a2_0_o2_0_17[1]\, - \in_sel_src_8_i_a2_0_o2_0_23[1]\, - \in_sel_src_8_i_a2_0_o2_0_26[1]\, - \in_sel_src_8_i_a2_0_o2_0_12[1]\, - \in_sel_src_8_i_a2_0_o2_0_11[1]\, - \in_sel_src_8_i_a2_0_o2_0_22[1]\, - \in_sel_src_8_i_a2_0_o2_0_25[1]\, - \in_sel_src_8_i_a2_0_o2_0_8[1]\, - \in_sel_src_8_i_a2_0_o2_0_7[1]\, - \in_sel_src_8_i_a2_0_o2_0_20[1]\, - \in_sel_src_8_i_a2_0_o2_0_2[1]\, - \in_sel_src_8_i_a2_0_o2_0_1[1]\, - \in_sel_src_8_i_a2_0_o2_0_15[1]\, - \in_sel_src_8_i_a2_0_o2_0_14[1]\, - \in_sel_src_8_i_a2_0_o2_0_10[1]\, - \in_sel_src_8_i_a2_0_o2_0_6[1]\, - \in_sel_src_8_i_a2_0_o2_0_4[1]\, ram_write_2_0_a2_0, N_18, - N_20, N_650, N_651, N_703, N_206, N_480, - un1_IIR_CEL_STATE_20, N_325_i, N_714, - un1_IIR_CEL_STATE_22, N_796_i, N_736, N_723_i_0, N_737, - N_735, N_289, N_11, N_22, N_216, N_216_tz, N_33_0, N_34_0, - N_35_0, N_36_0, N_38, N_40, N_42, Chanel_ongoing_n0, - \Cel_ongoing_RNO[3]_net_1\, \Cel_ongoing_RNO[4]_net_1\, - \Cel_ongoing_RNO[5]_net_1\, \Cel_ongoing_RNO[6]_net_1\, - \Cel_ongoing_RNO[7]_net_1\, \Cel_ongoing_RNO[8]_net_1\, - \Cel_ongoing_RNO[9]_net_1\, \Cel_ongoing_RNO[10]_net_1\, - \Cel_ongoing_RNO[11]_net_1\, \Cel_ongoing_RNO[12]_net_1\, - N_462, N_374_i, N_269, N_332, Chanel_ongoing_n17, - Chanel_ongoing_n18, Chanel_ongoing_n19, - Chanel_ongoing_n23, Chanel_ongoing_n24, - Chanel_ongoing_n26, Chanel_ongoing_n27, N_224, N_724, - N_229, N_232, sample_in_rotate, N_373_i, N_372_i, N_127, - N_461, N_460, \IIR_CEL_STATE_ns[8]\, N_336_i_i_0, N_221, - \Cel_ongoing_RNO[13]_net_1\, \Cel_ongoing_RNO[1]_net_1\, - N_31_0, N_32_0_i_0, N_715, N_15_i, \alu_sel_coeff[3]\, - N_353, N_712, \IIR_CEL_STATE[2]_net_1\, N_227, N_729, - N_523, N_568_i_0, ram_write_2, un1_IIR_CEL_STATE_27, - N_477, N_569, N_334, N_180, N_204, Chanel_ongoing_n25, - un1_IIR_CEL_STATE_25, N_268_i_0, alu_sel_input_1, - sample_in_rot_2, N_512_i_0, \alu_sel_coeff[0]\, - \alu_sel_coeff[2]\, \alu_sel_coeff[4]\, ram_write_net_1, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - alu_sel_coeff(4) <= \alu_sel_coeff[4]\; - alu_sel_coeff(3) <= \alu_sel_coeff[3]\; - alu_sel_coeff(2) <= \alu_sel_coeff[2]\; - alu_sel_coeff(0) <= \alu_sel_coeff[0]\; - alu_sel_coeff_0_2 <= \alu_sel_coeff_0[2]\; - ram_write <= ram_write_net_1; - - sample_in_rot_RNO : NOR2A - port map(A => \IIR_CEL_STATE[7]_net_1\, B => N_328, Y => - sample_in_rot_2); - - \Cel_ongoing_RNIP2TO[8]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_4[1]\, B => - \Cel_ongoing[8]_net_1\, C => \Cel_ongoing[7]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_17[1]\); - - un1_IIR_CEL_STATE_17_m17 : NOR3C - port map(A => \Cel_ongoing[1]_net_1\, B => N_16_0, C => - \Cel_ongoing[2]_net_1\, Y => N_18_0); - - \IIR_CEL_STATE_RNIU1T5[5]\ : OR2 - port map(A => \IIR_CEL_STATE[7]_net_1\, B => - \IIR_CEL_STATE[5]_net_1\, Y => N_289); - - \Cel_ongoing_RNO[9]\ : XA1 - port map(A => \Cel_ongoing[9]_net_1\, B => N_24_0, C => - N_371_0, Y => \Cel_ongoing_RNO[9]_net_1\); - - \in_sel_src[0]\ : DFN1E0C0 - port map(D => N_268_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => un1_IIR_CEL_STATE_27, Q => in_sel_src(0)); - - \Chanel_ongoing_RNIFMU9[17]\ : NOR2A - port map(A => \Chanel_ongoing[17]_net_1\, B => N_273, Y => - N_275); - - \Chanel_ongoing[1]\ : DFN1E1C0 - port map(D => N_18, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[1]_net_1\); - - \in_sel_src_RNO_0[1]\ : OR2 - port map(A => \IIR_CEL_STATE[6]_net_1\, B => - \IIR_CEL_STATE[7]_net_1\, Y => - \in_sel_src_8_i_a2_0_a2_0_0[1]\); - - \Chanel_ongoing_RNI3OA4[8]\ : NOR3C - port map(A => \Chanel_ongoing[7]_net_1\, B => N_254, C => - \Chanel_ongoing[8]_net_1\, Y => N_256); - - \Chanel_ongoing_RNIO3D1[2]\ : OR3C - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, C => \Chanel_ongoing[2]_net_1\, - Y => N_250); - - \Cel_ongoing[23]\ : DFN1C0 - port map(D => N_442, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[23]_net_1\); - - \Cel_ongoing[22]\ : DFN1C0 - port map(D => N_441, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[22]_net_1\); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_7 : NOR2B - port map(A => \Cel_ongoing[28]_net_1\, B => - \Cel_ongoing[29]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_7); - - \Chanel_ongoing_RNO_0[22]\ : OR2A - port map(A => \Chanel_ongoing[21]_net_1\, B => N_279, Y => - N_725); - - \Chanel_ongoing[29]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n29, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[29]_net_1\); - - \Cel_ongoing_RNO[17]\ : XA1 - port map(A => \Cel_ongoing[17]_net_1\, B => N_48, C => - N_371_0, Y => N_436); - - \Chanel_ongoing_RNIPNC7[13]\ : OR2A - port map(A => \Chanel_ongoing[13]_net_1\, B => N_265, Y => - N_270); - - \Chanel_ongoing_RNIIB91[29]\ : NOR2 - port map(A => \Chanel_ongoing[29]_net_1\, B => - \Chanel_ongoing[30]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_10); - - \IIR_CEL_STATE_i_RNILN7F[9]\ : AOI1B - port map(A => N_733_1, B => N_294, C => N_453, Y => - un1_alu_sel_input_0_sqmuxa_2_i_0_s_0_0); - - \Cel_ongoing[15]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[15]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[15]_net_1\); - - \Cel_ongoing_RNO[16]\ : NOR2A - port map(A => N_371_0, B => N_47, Y => N_435); - - \Chanel_ongoing_RNO[30]\ : XA1C - port map(A => \Chanel_ongoing[30]_net_1\, B => N_327, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n30); - - \Cel_ongoing_RNO[21]\ : XA1 - port map(A => \Cel_ongoing[21]_net_1\, B => N_56, C => - N_371, Y => N_440); - - \alu_selected_coeff[4]\ : DFN1E1C0 - port map(D => N_715, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => \alu_sel_coeff[4]\); - - \Cel_ongoing[2]\ : DFN1C0 - port map(D => N_227, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[2]_net_1\); - - \alu_selected_coeff_RNIH4TI5[0]\ : NOR2A - port map(A => N_371, B => \alu_sel_coeff[0]\, Y => - alu_selected_coeff_n0); - - \Cel_ongoing_RNIT33B[0]\ : NOR2A - port map(A => \Cel_ongoing[0]_net_1\, B => - \Cel_ongoing[14]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_7[1]\); - - \alu_selected_coeff_RNO[3]\ : NOR2A - port map(A => N_371_0, B => alu_selected_coeff_n3_0_i_0, Y - => N_714); - - \Chanel_ongoing_RNO_0[9]\ : XNOR2 - port map(A => N_256, B => \Chanel_ongoing[9]_net_1\, Y => - N_372_i); - - \IIR_CEL_STATE_RNO[2]\ : NOR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_523, Y => - N_477); - - \Chanel_ongoing_RNIQVNF[26]\ : OR2B - port map(A => N_291, B => \Chanel_ongoing[26]_net_1\, Y => - N_292); - - alu_sel_input_RNO : NOR2 - port map(A => \IIR_CEL_STATE[6]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => alu_sel_input_1); - - \Chanel_ongoing_RNO_0[3]\ : XNOR2 - port map(A => N_250, B => \Chanel_ongoing[3]_net_1\, Y => - N_336_i_i_0); - - \Cel_ongoing_RNO_1[0]\ : NOR2B - port map(A => \IIR_CEL_STATE[4]_net_1\, B => - \un1_IIR_CEL_STATE_17_i_1_i_0[31]\, Y => - \Cel_ongoing_6_i_i_a2_0_0[0]\); - - \Chanel_ongoing[30]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n30, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[30]_net_1\); - - \IIR_CEL_STATE_RNI5V1J5[2]\ : OR2B - port map(A => N_371, B => N_353, Y => alu_selected_coeffe); - - \Cel_ongoing_RNO[5]\ : NOR2A - port map(A => N_371_0, B => N_35_0, Y => - \Cel_ongoing_RNO[5]_net_1\); - - \Cel_ongoing_RNIDJOG[18]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_10[1]\, B => - \Cel_ongoing[18]_net_1\, C => \Cel_ongoing[17]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_20[1]\); - - \Cel_ongoing[24]\ : DFN1C0 - port map(D => N_443, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[24]_net_1\); - - un1_IIR_CEL_STATE_17_m54 : AX1E - port map(A => \Cel_ongoing[19]_net_1\, B => N_52, C => - \Cel_ongoing[20]_net_1\, Y => N_55); - - \Chanel_ongoing_RNIDQB2[4]\ : NOR3B - port map(A => \Chanel_ongoing[3]_net_1\, B => - \Chanel_ongoing[4]_net_1\, C => N_250, Y => N_252); - - \IIR_CEL_STATE_i[9]\ : DFN1 - port map(D => N_512_i_0, CLK => HCLK_c, Q => - \IIR_CEL_STATE_i[9]_net_1\); - - \Chanel_ongoing_RNI61B3[6]\ : NOR3C - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252, C => - \Chanel_ongoing[6]_net_1\, Y => N_254); - - \Chanel_ongoing[8]\ : DFN1E1C0 - port map(D => N_651, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[8]_net_1\); - - \Chanel_ongoing_RNO[13]\ : XA1C - port map(A => \Chanel_ongoing[13]_net_1\, B => N_265, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => N_224); - - \Chanel_ongoing_RNIKIU[2]\ : NOR2 - port map(A => \Chanel_ongoing[2]_net_1\, B => - \Chanel_ongoing[4]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_1); - - \Cel_ongoing_RNO[11]\ : XA1 - port map(A => \Cel_ongoing[11]_net_1\, B => N_26_0, C => - N_371_0, Y => \Cel_ongoing_RNO[11]_net_1\); - - \Cel_ongoing_RNIKMF11[22]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_12[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_11[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_22[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_26[1]\); - - \IIR_CEL_STATE_RNIRIR8[6]\ : OR3 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[6]_net_1\, C => \IIR_CEL_STATE[7]_net_1\, - Y => N_334); - - \alu_selected_coeff_RNO_0[4]\ : AX1A - port map(A => N_717, B => \alu_sel_coeff[3]\, C => - \alu_sel_coeff[4]\, Y => N_15_i); - - \Chanel_ongoing[3]\ : DFN1E1C0 - port map(D => N_221, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[3]_net_1\); - - \Chanel_ongoing_RNO_0[6]\ : AX1E - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252, C => - \Chanel_ongoing[6]_net_1\, Y => Chanel_ongoing_n6_0_i_0_0); - - ram_write_RNO : AO1B - port map(A => ram_write_2_0_a2_0, B => N_733_1, C => N_480, - Y => ram_write_2); - - \Cel_ongoing_RNICE615_0[2]\ : OR2A - port map(A => N_325_i, B => \Cel_ongoing[2]_net_1\, Y => - N_332); - - \Cel_ongoing[0]\ : DFN1C0 - port map(D => N_206, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[0]_net_1\); - - sample_out_rot_3 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_3); - - \IIR_CEL_STATE_RNISQ2Q5[2]\ : AO1 - port map(A => N_523, B => \IIR_CEL_STATE[4]_net_1\, C => - \IIR_CEL_STATE[2]_net_1\, Y => un1_IIR_CEL_STATE_27); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_13 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_5, B => - ADD_32x32_fast_I129_un1_Y_4, C => - ADD_32x32_fast_I129_un1_Y_11, Y => - ADD_32x32_fast_I129_un1_Y_13); - - \Chanel_ongoing_RNIE545[14]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_12, B => - Cel_ongoing_0_sqmuxa_0_a2_0_11, C => - Cel_ongoing_0_sqmuxa_0_a2_0_22, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_26); - - \IIR_CEL_STATE_RNI9V445[4]\ : OR2B - port map(A => N_328, B => \IIR_CEL_STATE[4]_net_1\, Y => - N_248); - - \IIR_CEL_STATE_i_RNILP76[9]\ : OR3 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay, C => \IIR_CEL_STATE[4]_net_1\, Y => - N_453); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \Cel_ongoing[22]_net_1\, B => - \Cel_ongoing[23]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_4); - - un1_IIR_CEL_STATE_17_m50 : AX1E - port map(A => \Cel_ongoing[17]_net_1\, B => N_48, C => - \Cel_ongoing[18]_net_1\, Y => N_51); - - \IIR_CEL_STATE_i_RNIEAL96[9]\ : OR2B - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_s_0_0, B => - N_452, Y => un1_alu_sel_input_0_sqmuxa_2_i_0_0); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y : NOR3C - port map(A => \Cel_ongoing[13]_net_1\, B => N_28_0, C => - ADD_32x32_fast_I129_un1_Y_14, Y => I129_un1_Y); - - \IIR_CEL_STATE[2]\ : DFN1E1 - port map(D => N_477, CLK => HCLK_c, E => HRESETn_c, Q => - \IIR_CEL_STATE[2]_net_1\); - - \Chanel_ongoing[13]\ : DFN1E1C0 - port map(D => N_224, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[13]_net_1\); - - \Chanel_ongoing[12]\ : DFN1E1C0 - port map(D => N_216, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[12]_net_1\); - - ram_write_RNO_0 : NOR2 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[7]_net_1\, Y => ram_write_2_0_a2_0); - - un1_IIR_CEL_STATE_17_m34 : XNOR2 - port map(A => N_20_0, B => \Cel_ongoing[5]_net_1\, Y => - N_35_0); - - \IIR_CEL_STATE_i_RNIEAL96_0[9]\ : OR2B - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_s_0_0, B => - N_452, Y => un1_alu_sel_input_0_sqmuxa_2_i_0); - - \Cel_ongoing_RNO_0[0]\ : AOI1B - port map(A => \Cel_ongoing_6_i_i_a2_0_0[0]\, B => N_328, C - => \Cel_ongoing_6_i_i_0[0]\, Y => - \Cel_ongoing_6_i_i_1[0]\); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \Cel_ongoing[15]_net_1\, B => - \Cel_ongoing[14]_net_1\, C => ADD_32x32_fast_I129_un1_Y_1, - Y => ADD_32x32_fast_I129_un1_Y_8); - - sample_out_rot_1 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_1); - - \Chanel_ongoing_RNI9OEE[24]\ : OR2A - port map(A => \Chanel_ongoing[24]_net_1\, B => N_288, Y => - N_290); - - \Cel_ongoing_RNO[31]\ : XA1 - port map(A => \Cel_ongoing[31]_net_1\, B => N_75, C => - N_371, Y => N_450); - - \Cel_ongoing_RNIRLC8[27]\ : NOR2 - port map(A => \Cel_ongoing[27]_net_1\, B => - \Cel_ongoing[28]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_14[1]\); - - \Chanel_ongoing_RNO[31]\ : XA1C - port map(A => \Chanel_ongoing[31]_net_1\, B => N_335, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n31); - - \Chanel_ongoing_RNIH791[25]\ : NOR2 - port map(A => \Chanel_ongoing[25]_net_1\, B => - \Chanel_ongoing[26]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_8); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_11 : NOR3C - port map(A => \Cel_ongoing[27]_net_1\, B => - \Cel_ongoing[26]_net_1\, C => ADD_32x32_fast_I129_un1_Y_7, - Y => ADD_32x32_fast_I129_un1_Y_11); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_14 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_9, B => - ADD_32x32_fast_I129_un1_Y_8, C => - ADD_32x32_fast_I129_un1_Y_13, Y => - ADD_32x32_fast_I129_un1_Y_14); - - \Chanel_ongoing[11]\ : DFN1E1C0 - port map(D => N_462, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[11]_net_1\); - - \IIR_CEL_STATE[4]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[3]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[4]_net_1\); - - \Chanel_ongoing_RNI3PO5[15]\ : NOR3C - port map(A => Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_2, B => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_1, C => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_6, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_7); - - un1_IIR_CEL_STATE_17_m21 : NOR3C - port map(A => \Cel_ongoing[5]_net_1\, B => N_20_0, C => - \Cel_ongoing[6]_net_1\, Y => N_22_0); - - \IIR_CEL_STATE_i_RNI16EG5[9]\ : OR2A - port map(A => N_371, B => N_274, Y => N_127_0); - - \alu_selected_coeff_RNO[1]\ : NOR2B - port map(A => S_i_0(33), B => N_371, Y => N_712); - - \IIR_CEL_STATE_RNI3D16[1]\ : NOR3A - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - \IIR_CEL_STATE[0]_net_1\, C => \IIR_CEL_STATE[1]_net_1\, - Y => N_6); - - \Cel_ongoing_RNIJEQD[6]\ : NOR2 - port map(A => \Cel_ongoing[5]_net_1\, B => - \Cel_ongoing[6]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_2[1]\); - - un1_IIR_CEL_STATE_17_m30 : XNOR2 - port map(A => N_16_0, B => \Cel_ongoing[1]_net_1\, Y => - N_31_0); - - \Chanel_ongoing_RNO[20]\ : XA1C - port map(A => \Chanel_ongoing[20]_net_1\, B => N_278, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n20); - - \Chanel_ongoing[20]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n20, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[20]_net_1\); - - \Chanel_ongoing_RNIUQV[7]\ : NOR2 - port map(A => \Chanel_ongoing[7]_net_1\, B => - \Chanel_ongoing[9]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_3); - - \Chanel_ongoing_RNIFUT[1]\ : NOR2 - port map(A => \Chanel_ongoing[1]_net_1\, B => - \Chanel_ongoing[0]_net_1\, Y => N_479); - - GND_i : GND - port map(Y => \GND\); - - \Chanel_ongoing[27]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n27, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[27]_net_1\); - - \Cel_ongoing_RNO[25]\ : XA1 - port map(A => \Cel_ongoing[25]_net_1\, B => N_64, C => - N_371, Y => N_444); - - \Chanel_ongoing_RNO_0[7]\ : XOR2 - port map(A => \Chanel_ongoing[7]_net_1\, B => N_254, Y => - Chanel_ongoing_n7_0_i_0_0); - - un1_IIR_CEL_STATE_17_m71 : NOR2B - port map(A => N_70, B => \Cel_ongoing[28]_net_1\, Y => N_72); - - \Chanel_ongoing_RNII4QD[23]\ : OR2A - port map(A => \Chanel_ongoing[23]_net_1\, B => - \Chanel_ongoing_RNISG5D[13]_net_1\, Y => N_288); - - \alu_selected_coeff_RNIR19H[2]\ : OR2A - port map(A => \alu_sel_coeff[2]\, B => S(8), Y => N_717); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - raddr_add1_RNO_0 : OR3 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay, C => \IIR_CEL_STATE[3]_net_1\, Y => - N_737); - - \Chanel_ongoing_RNO_0[12]\ : AX1E - port map(A => \Chanel_ongoing[11]_net_1\, B => N_258, C => - \Chanel_ongoing[12]_net_1\, Y => N_216_tz); - - \Chanel_ongoing_RNI9Q63[19]\ : NOR3C - port map(A => \Chanel_ongoing[20]_net_1\, B => - \Chanel_ongoing[19]_net_1\, C => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_4, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_6); - - sample_out_rot_0 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_0); - - \Chanel_ongoing_RNIF71H[28]\ : OR2A - port map(A => \Chanel_ongoing[28]_net_1\, B => N_293, Y => - N_295); - - \IIR_CEL_STATE[5]\ : DFN1E1 - port map(D => N_204, CLK => HCLK_c, E => HRESETn_c, Q => - \IIR_CEL_STATE[5]_net_1\); - - \Cel_ongoing[25]\ : DFN1C0 - port map(D => N_444, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[25]_net_1\); - - \IIR_CEL_STATE_RNO[5]\ : OR2A - port map(A => N_248, B => N_353, Y => N_204); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_5 : NOR2B - port map(A => \Cel_ongoing[24]_net_1\, B => - \Cel_ongoing[25]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_5); - - \Chanel_ongoing[18]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n18, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[18]_net_1\); - - \Chanel_ongoing[16]\ : DFN1E1C0 - port map(D => N_232, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[16]_net_1\); - - \alu_selected_coeff[3]\ : DFN1E1C0 - port map(D => N_714, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => \alu_sel_coeff[3]\); - - \Chanel_ongoing_RNITMT1[22]\ : NOR3C - port map(A => \Chanel_ongoing[14]_net_1\, B => - \Chanel_ongoing[22]_net_1\, C => - \Chanel_ongoing[21]_net_1\, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_4); - - \Cel_ongoing_RNO[15]\ : XA1 - port map(A => \Cel_ongoing[15]_net_1\, B => N_44, C => - N_371_0, Y => \Cel_ongoing_RNO[15]_net_1\); - - un1_IIR_CEL_STATE_17_m67 : NOR2B - port map(A => N_66, B => \Cel_ongoing[26]_net_1\, Y => N_68); - - \alu_ctrl[0]\ : DFN1E0C0 - port map(D => N_568_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(0)); - - raddr_add1_RNO_1 : OR3B - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => N_289, C => - \IIR_CEL_STATE[3]_net_1\, Y => N_735); - - \Chanel_ongoing_RNI7791[20]\ : NOR2 - port map(A => \Chanel_ongoing[20]_net_1\, B => - \Chanel_ongoing[21]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_14); - - \Cel_ongoing_RNIU5UA1[31]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_2[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_1[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_15[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_23[1]\); - - un1_IIR_CEL_STATE_17_m23 : NOR3C - port map(A => \Cel_ongoing[7]_net_1\, B => N_22_0, C => - \Cel_ongoing[8]_net_1\, Y => N_24_0); - - \Chanel_ongoing_RNI2NL8[15]\ : OR2A - port map(A => \Chanel_ongoing[15]_net_1\, B => N_271, Y => - N_272); - - \Chanel_ongoing[14]\ : DFN1E1C0 - port map(D => N_724, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[14]_net_1\); - - \IIR_CEL_STATE_i_RNIO893[9]\ : NOR2A - port map(A => sample_val_delay, B => - \IIR_CEL_STATE_i[9]_net_1\, Y => N_274); - - \alu_ctrl[2]\ : DFN1E0C0 - port map(D => \IIR_CEL_STATE_i_i[9]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \IIR_CEL_STATE[2]_net_1\, Q => - alu_ctrl(2)); - - \Chanel_ongoing_RNO[10]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0, B => - N_373_i, Y => N_461); - - \ram_sel_Wdata[1]\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_22, CLK => HCLK_c, CLR => - HRESETn_c, E => \IIR_CEL_STATE[8]_net_1\, Q => - ram_sel_Wdata(1)); - - \IIR_CEL_STATE_RNIN1T5[5]\ : NOR2 - port map(A => \IIR_CEL_STATE[0]_net_1\, B => - \IIR_CEL_STATE[5]_net_1\, Y => un1_IIR_CEL_STATE_22_0_0); - - \Chanel_ongoing_RNIBV81[15]\ : NOR2B - port map(A => \Chanel_ongoing[15]_net_1\, B => - \Chanel_ongoing[16]_net_1\, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_1); - - \Cel_ongoing_RNO[4]\ : NOR2A - port map(A => N_371_0, B => N_34_0, Y => - \Cel_ongoing_RNO[4]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \Chanel_ongoing_RNO_0[11]\ : XNOR2 - port map(A => N_258, B => \Chanel_ongoing[11]_net_1\, Y => - N_374_i); - - \Chanel_ongoing_RNID791[23]\ : NOR2 - port map(A => \Chanel_ongoing[23]_net_1\, B => - \Chanel_ongoing[24]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_7); - - \Cel_ongoing[4]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[4]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[4]_net_1\); - - \Chanel_ongoing_RNO[21]\ : XA1C - port map(A => \Chanel_ongoing[21]_net_1\, B => N_279, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n21); - - \Chanel_ongoing_RNI76JA[18]\ : OR2B - port map(A => N_275, B => \Chanel_ongoing[18]_net_1\, Y => - N_276); - - \Chanel_ongoing_RNO[29]\ : XA1C - port map(A => \Chanel_ongoing[29]_net_1\, B => N_295, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n29); - - \Chanel_ongoing_RNIJ9SB[20]\ : OR2A - port map(A => \Chanel_ongoing[20]_net_1\, B => N_278, Y => - N_279); - - \alu_ctrl[1]\ : DFN1E0C0 - port map(D => N_569, CLK => HCLK_c, CLR => HRESETn_c, E => - \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(1)); - - sample_out_val : DFN1E0C0 - port map(D => \IIR_CEL_STATE[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => N_353, Q => sample_out_val_s); - - raddr_add1_RNO_3 : OR2A - port map(A => \IIR_CEL_STATE[3]_net_1\, B => N_274, Y => - raddr_add1_2_i_a2_0_0); - - \Chanel_ongoing[31]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n31, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[31]_net_1\); - - un1_IIR_CEL_STATE_17_m29 : XNOR2 - port map(A => N_566, B => \Cel_ongoing[0]_net_1\, Y => - \un1_IIR_CEL_STATE_17_i_1_i_0[31]\); - - \IIR_CEL_STATE_RNI0UV8[4]\ : NOR2A - port map(A => N_6, B => \IIR_CEL_STATE[4]_net_1\, Y => - N_566); - - \Cel_ongoing_RNI679Q4[12]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_26[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_25[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_27[1]\, Y => N_325_i); - - sample_out_rot_2 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_2); - - \Chanel_ongoing_RNI53M8[6]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_16, B => - Cel_ongoing_0_sqmuxa_0_a2_0_15, C => - Cel_ongoing_0_sqmuxa_0_a2_0_24, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_27); - - \Chanel_ongoing_RNIO6I2[18]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_14, B => - \Chanel_ongoing[19]_net_1\, C => - \Chanel_ongoing[18]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_22); - - \Chanel_ongoing_RNI1C3F[25]\ : NOR2A - port map(A => \Chanel_ongoing[25]_net_1\, B => N_290, Y => - N_291); - - un1_IIR_CEL_STATE_17_m19 : NOR3C - port map(A => \Cel_ongoing[3]_net_1\, B => N_18_0, C => - \Cel_ongoing[4]_net_1\, Y => N_20_0); - - \IIR_CEL_STATE_RNI9T4D5[4]\ : OR2A - port map(A => N_248, B => N_566, Y => N_371_0); - - un1_IIR_CEL_STATE_17_m46 : AX1E - port map(A => \Cel_ongoing[15]_net_1\, B => N_44, C => - \Cel_ongoing[16]_net_1\, Y => N_47); - - \Chanel_ongoing_RNIKJCG[27]\ : OR2A - port map(A => \Chanel_ongoing[27]_net_1\, B => N_292, Y => - N_293); - - \Chanel_ongoing_RNI39F5[10]\ : NOR3C - port map(A => \Chanel_ongoing[9]_net_1\, B => N_256, C => - \Chanel_ongoing[10]_net_1\, Y => N_258); - - \waddr_previous[1]\ : DFN1E0C0 - port map(D => N_729, CLK => HCLK_c, CLR => HRESETn_c, E => - \IIR_CEL_STATE[8]_net_1\, Q => waddr_previous(1)); - - un1_IIR_CEL_STATE_17_m37 : AX1E - port map(A => \Cel_ongoing[7]_net_1\, B => N_22_0, C => - \Cel_ongoing[8]_net_1\, Y => N_38); - - un1_IIR_CEL_STATE_17_m25 : NOR3C - port map(A => \Cel_ongoing[9]_net_1\, B => N_24_0, C => - \Cel_ongoing[10]_net_1\, Y => N_26_0); - - \Cel_ongoing_RNIF5B8[22]\ : NOR2 - port map(A => \Cel_ongoing[21]_net_1\, B => - \Cel_ongoing[22]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_11[1]\); - - raddr_add1_RNO : NOR3C - port map(A => N_737, B => N_735, C => N_736, Y => N_723_i_0); - - un1_IIR_CEL_STATE_17_m15 : NOR2A - port map(A => \Cel_ongoing[0]_net_1\, B => N_566, Y => - N_16_0); - - \IIR_CEL_STATE_RNI1A4N5[4]\ : NOR2 - port map(A => N_796_i, B => N_480, Y => - \IIR_CEL_STATE_ns[8]\); - - \IIR_CEL_STATE[7]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[6]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[7]_net_1\); - - \IIR_CEL_STATE_RNIL1T5[1]\ : OR2 - port map(A => \IIR_CEL_STATE[2]_net_1\, B => - \IIR_CEL_STATE[1]_net_1\, Y => N_567_i_0); - - \Cel_ongoing[19]\ : DFN1C0 - port map(D => N_438, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[19]_net_1\); - - \Chanel_ongoing_RNO[11]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_0, B => - N_374_i, Y => N_462); - - \Chanel_ongoing_RNO[24]\ : XA1C - port map(A => \Chanel_ongoing[24]_net_1\, B => N_288, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n24); - - \Chanel_ongoing_RNO[19]\ : XA1C - port map(A => \Chanel_ongoing[19]_net_1\, B => N_276, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n19); - - \Chanel_ongoing_RNIN1V1[6]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_3, B => - \Chanel_ongoing[6]_net_1\, C => \Chanel_ongoing[5]_net_1\, - Y => Cel_ongoing_0_sqmuxa_0_a2_0_16); - - \Chanel_ongoing[15]\ : DFN1E1C0 - port map(D => N_229, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[15]_net_1\); - - \Cel_ongoing[31]\ : DFN1C0 - port map(D => N_450, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[31]_net_1\); - - \IIR_CEL_STATE_i_RNIPIDQ5[9]\ : OR2A - port map(A => \IIR_CEL_STATE_ns[8]\, B => N_274, Y => N_452); - - \Cel_ongoing_RNIJLB8[24]\ : NOR2 - port map(A => \Cel_ongoing[23]_net_1\, B => - \Cel_ongoing[24]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_12[1]\); - - \alu_selected_coeff_RNO[4]\ : NOR2A - port map(A => N_371, B => N_15_i, Y => N_715); - - \Cel_ongoing[30]\ : DFN1C0 - port map(D => N_449, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[30]_net_1\); - - \Chanel_ongoing_RNO_0[5]\ : XNOR2 - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252, Y => - Chanel_ongoing_n5_0_i_0_0); - - \Chanel_ongoing[6]\ : DFN1E1C0 - port map(D => N_22, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[6]_net_1\); - - \alu_selected_coeff_RNO_0[3]\ : XOR2 - port map(A => N_717, B => \alu_sel_coeff[3]\, Y => - alu_selected_coeff_n3_0_i_0); - - sample_out_rot : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s); - - \Chanel_ongoing[23]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n23, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[23]_net_1\); - - \Chanel_ongoing[22]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n22, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[22]_net_1\); - - sample_out_rot_4 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_4); - - \Cel_ongoing_RNO[7]\ : XA1 - port map(A => \Cel_ongoing[7]_net_1\, B => N_22_0, C => - N_371_0, Y => \Cel_ongoing_RNO[7]_net_1\); - - ram_write_RNI0IG : INV - port map(A => ram_write_net_1, Y => ram_write_i); - - \IIR_CEL_STATE_RNI012A5[5]\ : OR2B - port map(A => un1_IIR_CEL_STATE_22_0_0, B => N_480, Y => - un1_IIR_CEL_STATE_22); - - \in_sel_src_RNO[0]\ : MX2A - port map(A => N_334, B => N_332, S => - \IIR_CEL_STATE[5]_net_1\, Y => N_268_i_0); - - \waddr_previous[0]\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_25, CLK => HCLK_c, CLR => - HRESETn_c, E => \IIR_CEL_STATE[8]_net_1\, Q => - waddr_previous(0)); - - \Chanel_ongoing_RNI68O6[12]\ : OR3C - port map(A => \Chanel_ongoing[11]_net_1\, B => N_258, C => - \Chanel_ongoing[12]_net_1\, Y => N_265); - - \alu_selected_coeff_0[2]\ : DFN1E1C0 - port map(D => N_713, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => \alu_sel_coeff_0[2]\); - - \Chanel_ongoing[21]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n21, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[21]_net_1\); - - \alu_selected_coeff_0[0]\ : DFN1E1C0 - port map(D => alu_selected_coeff_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => alu_selected_coeffe, Q => - alu_sel_coeff_0_0); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_9 : NOR3C - port map(A => \Cel_ongoing[19]_net_1\, B => - \Cel_ongoing[18]_net_1\, C => ADD_32x32_fast_I129_un1_Y_3, - Y => ADD_32x32_fast_I129_un1_Y_9); - - \Cel_ongoing_RNO[22]\ : NOR2A - port map(A => N_371, B => N_59, Y => N_441); - - \Chanel_ongoing_RNIDPT1[8]\ : NOR3B - port map(A => \Chanel_ongoing[3]_net_1\, B => - Cel_ongoing_0_sqmuxa_0_a2_0_1, C => - \Chanel_ongoing[8]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_15); - - un1_IIR_CEL_STATE_17_m51 : NOR3C - port map(A => \Cel_ongoing[17]_net_1\, B => N_48, C => - \Cel_ongoing[18]_net_1\, Y => N_52); - - \Chanel_ongoing_RNO[14]\ : XA1C - port map(A => \Chanel_ongoing[14]_net_1\, B => N_270, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => N_724); - - \Cel_ongoing_RNISAMG[12]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_6[1]\, B => - \Cel_ongoing[12]_net_1\, C => \Cel_ongoing[11]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_18[1]\); - - \Cel_ongoing_RNIKTB8[20]\ : NOR2 - port map(A => \Cel_ongoing[19]_net_1\, B => - \Cel_ongoing[20]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_10[1]\); - - \raddr_rst\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_20, CLK => HCLK_c, CLR => - HRESETn_c, E => N_353, Q => raddr_rst); - - \Chanel_ongoing_RNIO6A9[16]\ : OR2A - port map(A => \Chanel_ongoing[16]_net_1\, B => N_272, Y => - N_273); - - \Cel_ongoing_RNO[3]\ : NOR2A - port map(A => N_371_0, B => N_33_0, Y => - \Cel_ongoing_RNO[3]_net_1\); - - \Chanel_ongoing_RNI18P4[1]\ : NOR3C - port map(A => N_479, B => Cel_ongoing_0_sqmuxa_0_a2_0_4, C - => Cel_ongoing_0_sqmuxa_0_a2_0_18, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_24); - - \IIR_CEL_STATE_i_RNO[9]\ : MX2B - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => N_180, S => - HRESETn_c, Y => N_512_i_0); - - \Chanel_ongoing_RNISG5D[13]\ : OR2A - port map(A => Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_7, B => - N_270, Y => \Chanel_ongoing_RNISG5D[13]_net_1\); - - un1_IIR_CEL_STATE_17_m47 : NOR3C - port map(A => \Cel_ongoing[15]_net_1\, B => N_44, C => - \Cel_ongoing[16]_net_1\, Y => N_48); - - \Chanel_ongoing_RNO[26]\ : XA1B - port map(A => \Chanel_ongoing[26]_net_1\, B => N_291, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n26); - - \Cel_ongoing[18]\ : DFN1C0 - port map(D => N_437, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[18]_net_1\); - - \alu_selected_coeff_0_RNIF4EQ5[2]\ : NOR2B - port map(A => alu_selected_coeff_n2_0_i_0, B => N_371_0, Y - => N_713); - - \Chanel_ongoing_RNIHAI2[31]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_6, B => - \Chanel_ongoing[12]_net_1\, C => - \Chanel_ongoing[31]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_18); - - \Cel_ongoing_RNO[12]\ : NOR2A - port map(A => N_371_0, B => N_42, Y => - \Cel_ongoing_RNO[12]_net_1\); - - \Cel_ongoing_RNI2K2B[10]\ : NOR2 - port map(A => \Cel_ongoing[9]_net_1\, B => - \Cel_ongoing[10]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_4[1]\); - - \alu_selected_coeff[0]\ : DFN1E1C0 - port map(D => alu_selected_coeff_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => alu_selected_coeffe, Q => - \alu_sel_coeff[0]\); - - \Chanel_ongoing[19]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n19, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[19]_net_1\); - - \Cel_ongoing_RNI4P5K5[2]\ : OR2A - port map(A => N_796_i, B => N_328, Y => N_523); - - \Cel_ongoing[16]\ : DFN1C0 - port map(D => N_435, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[16]_net_1\); - - un1_IIR_CEL_STATE_17_m63 : NOR3C - port map(A => \Cel_ongoing[23]_net_1\, B => N_60, C => - \Cel_ongoing[24]_net_1\, Y => N_64); - - \Chanel_ongoing_RNO[0]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_0, B => - \Chanel_ongoing[0]_net_1\, Y => Chanel_ongoing_n0); - - GND_i_0 : GND - port map(Y => GND_0); - - \Chanel_ongoing_RNO[25]\ : XA1C - port map(A => \Chanel_ongoing[25]_net_1\, B => N_290, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n25); - - \in_sel_src_RNO[1]\ : MX2 - port map(A => \in_sel_src_8_i_a2_0_a2_0_0[1]\, B => N_289, - S => N_332, Y => N_269); - - \Cel_ongoing_RNO[23]\ : XA1 - port map(A => \Cel_ongoing[23]_net_1\, B => N_60, C => - N_371, Y => N_442); - - \Chanel_ongoing[28]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n28, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[28]_net_1\); - - un1_IIR_CEL_STATE_17_m31 : AX1C - port map(A => \Cel_ongoing[1]_net_1\, B => N_16_0, C => - \Cel_ongoing[2]_net_1\, Y => N_32_0_i_0); - - \Chanel_ongoing[26]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n26, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[26]_net_1\); - - \Chanel_ongoing_RNO[4]\ : NOR2 - port map(A => Chanel_ongoing_n4_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_11); - - \Cel_ongoing_RNIF5B8[30]\ : NOR2 - port map(A => \Cel_ongoing[13]_net_1\, B => - \Cel_ongoing[30]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_6[1]\); - - \Chanel_ongoing[2]\ : DFN1E1C0 - port map(D => N_703, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[2]_net_1\); - - \Chanel_ongoing_RNI1V81[10]\ : NOR2 - port map(A => \Chanel_ongoing[10]_net_1\, B => - \Chanel_ongoing[11]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_4); - - \Chanel_ongoing_RNO[6]\ : NOR2 - port map(A => Chanel_ongoing_n6_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_22); - - \IIR_CEL_STATE[6]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[5]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[6]_net_1\); - - \Cel_ongoing[17]\ : DFN1C0 - port map(D => N_436, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[17]_net_1\); - - \Chanel_ongoing[24]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n24, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[24]_net_1\); - - \Cel_ongoing_RNO[2]\ : AO1 - port map(A => N_32_0_i_0, B => N_371, C => - \IIR_CEL_STATE_ns[8]\, Y => N_227); - - \Cel_ongoing_RNIS89F[31]\ : NOR3 - port map(A => \Cel_ongoing[1]_net_1\, B => - \Cel_ongoing[31]_net_1\, C => \Cel_ongoing[29]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_15[1]\); - - \Cel_ongoing[11]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[11]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[11]_net_1\); - - un1_IIR_CEL_STATE_17_m62 : AX1E - port map(A => \Cel_ongoing[23]_net_1\, B => N_60, C => - \Cel_ongoing[24]_net_1\, Y => N_63); - - \Chanel_ongoing_RNO[2]\ : NOR2A - port map(A => Chanel_ongoing_n2_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_703); - - \Cel_ongoing[10]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[10]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[10]_net_1\); - - \IIR_CEL_STATE_i_RNI16EG5_0[9]\ : OR2A - port map(A => N_371, B => N_274, Y => N_127); - - \Cel_ongoing_RNO[13]\ : XA1 - port map(A => \Cel_ongoing[13]_net_1\, B => N_28_0, C => - N_371, Y => \Cel_ongoing_RNO[13]_net_1\); - - \Cel_ongoing_RNO[24]\ : NOR2A - port map(A => N_371, B => N_63, Y => N_443); - - \Chanel_ongoing_RNO[16]\ : XA1C - port map(A => \Chanel_ongoing[16]_net_1\, B => N_272, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => N_232); - - \Chanel_ongoing_RNI0M7B[19]\ : OR2A - port map(A => \Chanel_ongoing[19]_net_1\, B => N_276, Y => - N_278); - - \Cel_ongoing_RNO[20]\ : NOR2A - port map(A => N_371_0, B => N_55, Y => N_439); - - \Cel_ongoing[5]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[5]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[5]_net_1\); - - \Cel_ongoing[29]\ : DFN1C0 - port map(D => N_448, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[29]_net_1\); - - \IIR_CEL_STATE_i_RNIBA69[9]\ : AO1D - port map(A => sample_val_delay, B => - \IIR_CEL_STATE_i[9]_net_1\, C => N_294, Y => - un1_IIR_CEL_STATE_20); - - \Chanel_ongoing_RNO_0[1]\ : XNOR2 - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, Y => Chanel_ongoing_n1_0_i_0_0); - - \Chanel_ongoing_RNO[27]\ : XA1C - port map(A => \Chanel_ongoing[27]_net_1\, B => N_292, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n27); - - \waddr_previous_RNO[0]\ : OR2A - port map(A => N_248, B => N_334, Y => un1_IIR_CEL_STATE_25); - - un1_IIR_CEL_STATE_17_m69 : NOR2B - port map(A => N_68, B => \Cel_ongoing[27]_net_1\, Y => N_70); - - \ram_sel_Wdata[0]\ : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => ram_sel_Wdata(0)); - - un1_IIR_CEL_STATE_17_m74 : NOR3C - port map(A => \Cel_ongoing[29]_net_1\, B => - \Cel_ongoing[30]_net_1\, C => N_72, Y => N_75); - - \Chanel_ongoing[4]\ : DFN1E1C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[4]_net_1\); - - \Cel_ongoing_RNO[0]\ : OAI1 - port map(A => N_480, B => un1_IIR_CEL_STATE_20, C => - \Cel_ongoing_6_i_i_1[0]\, Y => N_206); - - \IIR_CEL_STATE_RNI9V445_0[4]\ : OR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_328, Y => - N_480); - - \Chanel_ongoing_RNO_0[31]\ : OR2A - port map(A => \Chanel_ongoing[30]_net_1\, B => N_327, Y => - N_335); - - \Chanel_ongoing_RNI8391[13]\ : NOR2 - port map(A => \Chanel_ongoing[13]_net_1\, B => - \Chanel_ongoing[22]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_6); - - \Chanel_ongoing_RNO_0[10]\ : AX1E - port map(A => \Chanel_ongoing[9]_net_1\, B => N_256, C => - \Chanel_ongoing[10]_net_1\, Y => N_373_i); - - \Chanel_ongoing_RNO[8]\ : NOR2 - port map(A => Chanel_ongoing_n8_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_651); - - \IIR_CEL_STATE_RNIJ1T5[1]\ : OR2 - port map(A => \IIR_CEL_STATE[1]_net_1\, B => - \IIR_CEL_STATE[0]_net_1\, Y => N_294); - - \Chanel_ongoing_RNO[15]\ : XA1C - port map(A => \Chanel_ongoing[15]_net_1\, B => N_271, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => N_229); - - \Chanel_ongoing[7]\ : DFN1E1C0 - port map(D => N_650, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[7]_net_1\); - - \Cel_ongoing_RNO[8]\ : NOR2A - port map(A => N_371_0, B => N_38, Y => - \Cel_ongoing_RNO[8]_net_1\); - - \Cel_ongoing[13]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[13]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[13]_net_1\); - - \Cel_ongoing[12]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[12]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[12]_net_1\); - - \Chanel_ongoing_RNO[22]\ : XA1C - port map(A => \Chanel_ongoing[22]_net_1\, B => N_725, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n22); - - un1_IIR_CEL_STATE_17_m65 : NOR2B - port map(A => N_64, B => \Cel_ongoing[25]_net_1\, Y => N_66); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \Cel_ongoing[16]_net_1\, B => - \Cel_ongoing[17]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_1); - - \Chanel_ongoing_RNO[28]\ : XA1C - port map(A => \Chanel_ongoing[28]_net_1\, B => N_293, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n28); - - \Cel_ongoing_RNO[14]\ : NOR2A - port map(A => N_371_0, B => \un1_IIR_CEL_STATE_17_i[17]\, Y - => \Cel_ongoing_RNO[14]_net_1\); - - \Cel_ongoing_RNO[1]\ : NOR2A - port map(A => N_371, B => N_31_0, Y => - \Cel_ongoing_RNO[1]_net_1\); - - un1_IIR_CEL_STATE_17_m33 : AX1E - port map(A => \Cel_ongoing[3]_net_1\, B => N_18_0, C => - \Cel_ongoing[4]_net_1\, Y => N_34_0); - - \Cel_ongoing_RNO[10]\ : NOR2A - port map(A => N_371_0, B => N_40, Y => - \Cel_ongoing_RNO[10]_net_1\); - - \Cel_ongoing_RNICE615[2]\ : OR2B - port map(A => N_325_i, B => \Cel_ongoing[2]_net_1\, Y => - N_328); - - un1_IIR_CEL_STATE_17_m59 : NOR3C - port map(A => \Cel_ongoing[21]_net_1\, B => N_56, C => - \Cel_ongoing[22]_net_1\, Y => N_60); - - \Chanel_ongoing_RNI7JI2[27]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_10, B => - \Chanel_ongoing[28]_net_1\, C => - \Chanel_ongoing[27]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_20); - - \IIR_CEL_STATE_i_RNIDS23[9]\ : NOR2A - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => N_733_1); - - \Chanel_ongoing_RNI5255[23]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_8, B => - Cel_ongoing_0_sqmuxa_0_a2_0_7, C => - Cel_ongoing_0_sqmuxa_0_a2_0_20, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_25); - - \Cel_ongoing_RNIL5C8[16]\ : NOR2 - port map(A => \Cel_ongoing[15]_net_1\, B => - \Cel_ongoing[16]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_8[1]\); - - \Cel_ongoing[6]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[6]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[6]_net_1\); - - \IIR_CEL_STATE[3]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[7]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[3]_net_1\); - - \Cel_ongoing_RNO[29]\ : XA1 - port map(A => \Cel_ongoing[29]_net_1\, B => N_72, C => - N_371, Y => N_448); - - raddr_add1_RNO_2 : OR2A - port map(A => N_328, B => raddr_add1_2_i_a2_0_0, Y => N_736); - - \Chanel_ongoing_RNI9V81[14]\ : NOR2 - port map(A => \Chanel_ongoing[14]_net_1\, B => - \Chanel_ongoing[15]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_11); - - \Chanel_ongoing[0]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[0]_net_1\); - - \Cel_ongoing_RNO[6]\ : NOR2A - port map(A => N_371_0, B => N_36_0, Y => - \Cel_ongoing_RNO[6]_net_1\); - - \Cel_ongoing[14]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[14]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[14]_net_1\); - - \alu_selected_coeff_0_RNI679D[2]\ : XNOR2 - port map(A => S(8), B => \alu_sel_coeff_0[2]\, Y => - alu_selected_coeff_n2_0_i_0); - - un1_IIR_CEL_STATE_17_m55 : NOR3C - port map(A => \Cel_ongoing[19]_net_1\, B => N_52, C => - \Cel_ongoing[20]_net_1\, Y => N_56); - - \Cel_ongoing[9]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[9]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[9]_net_1\); - - sample_in_rot : DFN1E0C0 - port map(D => sample_in_rot_2, CLK => HCLK_c, CLR => - HRESETn_c, E => N_353, Q => sample_in_rotate); - - \Chanel_ongoing_RNO[17]\ : XA1C - port map(A => \Chanel_ongoing[17]_net_1\, B => N_273, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n17); - - \alu_selected_coeff[1]\ : DFN1E1C0 - port map(D => N_712, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => alu_sel_coeff(1)); - - \Cel_ongoing[8]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[8]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[8]_net_1\); - - un1_IIR_CEL_STATE_17_m32 : XNOR2 - port map(A => N_18_0, B => \Cel_ongoing[3]_net_1\, Y => - N_33_0); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I174_Y_0 : AX1E - port map(A => \Cel_ongoing[13]_net_1\, B => N_28_0, C => - \Cel_ongoing[14]_net_1\, Y => - \un1_IIR_CEL_STATE_17_i[17]\); - - \IIR_CEL_STATE[8]\ : DFN1E1 - port map(D => N_274, CLK => HCLK_c, E => HRESETn_c, Q => - \IIR_CEL_STATE[8]_net_1\); - - un1_IIR_CEL_STATE_17_m41 : AX1E - port map(A => \Cel_ongoing[11]_net_1\, B => N_26_0, C => - \Cel_ongoing[12]_net_1\, Y => N_42); - - \raddr_add1\ : DFN1C0 - port map(D => N_723_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => raddr_add1); - - \IIR_CEL_STATE[1]\ : DFN1E1 - port map(D => \IIR_CEL_STATE_ns[8]\, CLK => HCLK_c, E => - HRESETn_c, Q => \IIR_CEL_STATE[1]_net_1\); - - \alu_sel_input\ : DFN1E0C0 - port map(D => alu_sel_input_1, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_IIR_CEL_STATE_20, Q => alu_sel_input); - - un1_IIR_CEL_STATE_17_m58 : AX1E - port map(A => \Cel_ongoing[21]_net_1\, B => N_56, C => - \Cel_ongoing[22]_net_1\, Y => N_59); - - \ram_write\ : DFN1E0C0 - port map(D => ram_write_2, CLK => HCLK_c, CLR => HRESETn_c, - E => \IIR_CEL_STATE[8]_net_1\, Q => ram_write_net_1); - - \IIR_CEL_STATE_i_RNO_0[9]\ : AO1D - port map(A => sample_val_delay, B => - \IIR_CEL_STATE_i[9]_net_1\, C => \IIR_CEL_STATE[0]_net_1\, - Y => N_180); - - \Chanel_ongoing[10]\ : DFN1E1C0 - port map(D => N_461, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[10]_net_1\); - - \in_sel_src[1]\ : DFN1E0C0 - port map(D => N_269, CLK => HCLK_c, CLR => HRESETn_c, E => - un1_IIR_CEL_STATE_27, Q => in_sel_src(1)); - - \IIR_CEL_STATE_RNI9T4D5_0[4]\ : OR2A - port map(A => N_248, B => N_566, Y => N_371); - - \Chanel_ongoing[17]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n17, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[17]_net_1\); - - \Cel_ongoing[7]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[7]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[7]_net_1\); - - \Cel_ongoing_RNO[30]\ : XA1 - port map(A => \Cel_ongoing[30]_net_1\, B => I129_un1_Y, C - => N_371, Y => N_449); - - \Cel_ongoing[28]\ : DFN1C0 - port map(D => N_447, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[28]_net_1\); - - un1_IIR_CEL_STATE_17_m39 : AX1E - port map(A => \Cel_ongoing[9]_net_1\, B => N_24_0, C => - \Cel_ongoing[10]_net_1\, Y => N_40); - - \Chanel_ongoing_RNO[12]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_0, B => - N_216_tz, Y => N_216); - - \Chanel_ongoing[25]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n25, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[25]_net_1\); - - \Cel_ongoing_RNO[19]\ : XA1 - port map(A => \Cel_ongoing[19]_net_1\, B => N_52, C => - N_371_0, Y => N_438); - - \Chanel_ongoing_RNIOAVI[6]\ : OR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_26, B => - Cel_ongoing_0_sqmuxa_0_a2_0_25, C => - Cel_ongoing_0_sqmuxa_0_a2_0_27, Y => N_796_i); - - \Cel_ongoing_RNO[28]\ : XA1 - port map(A => \Cel_ongoing[28]_net_1\, B => N_70, C => - N_371, Y => N_447); - - \Chanel_ongoing_RNO[18]\ : XA1B - port map(A => \Chanel_ongoing[18]_net_1\, B => N_275, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n18); - - \Cel_ongoing_RNIFEQD[4]\ : NOR2 - port map(A => \Cel_ongoing[3]_net_1\, B => - \Cel_ongoing[4]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_1[1]\); - - \Cel_ongoing_RNIVS741[16]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_8[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_7[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_20[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_25[1]\); - - \Chanel_ongoing_RNO[1]\ : NOR2 - port map(A => Chanel_ongoing_n1_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_18); - - \Cel_ongoing[26]\ : DFN1C0 - port map(D => N_445, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[26]_net_1\); - - \Cel_ongoing_RNIIROG[25]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_14[1]\, B => - \Cel_ongoing[26]_net_1\, C => \Cel_ongoing[25]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_22[1]\); - - sample_in_rot_RNI6EV7_0 : CLKINT - port map(A => \sample_in_rot_RNI6EV7\, Y => - un1_sample_in_rotate); - - \Chanel_ongoing[9]\ : DFN1E1C0 - port map(D => N_460, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[9]_net_1\); - - un1_IIR_CEL_STATE_17_m35 : AX1E - port map(A => \Cel_ongoing[5]_net_1\, B => N_20_0, C => - \Cel_ongoing[6]_net_1\, Y => N_36_0); - - \IIR_CEL_STATE_RNIS1T5[2]\ : OR2 - port map(A => \IIR_CEL_STATE[8]_net_1\, B => - \IIR_CEL_STATE[2]_net_1\, Y => N_353); - - \Chanel_ongoing_RNO[3]\ : AO1A - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0, B => - N_336_i_i_0, C => \IIR_CEL_STATE_ns[8]\, Y => N_221); - - \Chanel_ongoing_RNO[5]\ : NOR2 - port map(A => Chanel_ongoing_n5_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_20); - - \Cel_ongoing_RNIJJHK2[12]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_18[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_17[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_23[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_27[1]\); - - \alu_ctrl_RNO[1]\ : OR2 - port map(A => \IIR_CEL_STATE[8]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => N_569); - - \Cel_ongoing[3]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[3]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[3]_net_1\); - - \Chanel_ongoing_RNO_0[2]\ : AX1C - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, C => \Chanel_ongoing[2]_net_1\, - Y => Chanel_ongoing_n2_0_i_0_0); - - \Chanel_ongoing_RNO[9]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0, B => - N_372_i, Y => N_460); - - \Cel_ongoing_RNO[18]\ : NOR2A - port map(A => N_371_0, B => N_51, Y => N_437); - - \IIR_CEL_STATE[0]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[1]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[0]_net_1\); - - \Cel_ongoing[27]\ : DFN1C0 - port map(D => N_446, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[27]_net_1\); - - \alu_selected_coeff[2]\ : DFN1E1C0 - port map(D => N_713, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => \alu_sel_coeff[2]\); - - \alu_ctrl_RNO[2]\ : INV - port map(A => \IIR_CEL_STATE_i[9]_net_1\, Y => - \IIR_CEL_STATE_i_i[9]\); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_3 : NOR2B - port map(A => \Cel_ongoing[20]_net_1\, B => - \Cel_ongoing[21]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_3); - - \Cel_ongoing[21]\ : DFN1C0 - port map(D => N_440, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[21]_net_1\); - - \Chanel_ongoing_RNIBRLH[29]\ : OR2A - port map(A => \Chanel_ongoing[29]_net_1\, B => N_295, Y => - N_327); - - sample_in_rot_RNI6EV7 : OR2 - port map(A => sample_val_delay, B => sample_in_rotate, Y - => \sample_in_rot_RNI6EV7\); - - \Cel_ongoing_RNO_2[0]\ : AOI1B - port map(A => \un1_IIR_CEL_STATE_17_i_1_i_0[31]\, B => N_6, - C => N_457, Y => \Cel_ongoing_6_i_i_0[0]\); - - \Cel_ongoing_RNO[27]\ : XA1 - port map(A => \Cel_ongoing[27]_net_1\, B => N_68, C => - N_371, Y => N_446); - - \Cel_ongoing[20]\ : DFN1C0 - port map(D => N_439, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[20]_net_1\); - - \Chanel_ongoing_RNID718[14]\ : OR2A - port map(A => \Chanel_ongoing[14]_net_1\, B => N_270, Y => - N_271); - - un1_IIR_CEL_STATE_17_m43 : NOR3C - port map(A => \Cel_ongoing[13]_net_1\, B => N_28_0, C => - \Cel_ongoing[14]_net_1\, Y => N_44); - - \Chanel_ongoing_RNO_0[8]\ : AX1E - port map(A => \Chanel_ongoing[7]_net_1\, B => N_254, C => - \Chanel_ongoing[8]_net_1\, Y => Chanel_ongoing_n8_0_i_0_0); - - \Cel_ongoing[1]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[1]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[1]_net_1\); - - \Chanel_ongoing_RNIDV81[16]\ : NOR2 - port map(A => \Chanel_ongoing[16]_net_1\, B => - \Chanel_ongoing[17]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_12); - - \Cel_ongoing_RNO[26]\ : XA1 - port map(A => \Cel_ongoing[26]_net_1\, B => N_66, C => - N_371, Y => N_445); - - \Chanel_ongoing_RNO_0[4]\ : AX1A - port map(A => N_250, B => \Chanel_ongoing[3]_net_1\, C => - \Chanel_ongoing[4]_net_1\, Y => Chanel_ongoing_n4_0_i_0_0); - - \Chanel_ongoing_RNO[7]\ : NOR2A - port map(A => Chanel_ongoing_n7_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_650); - - \waddr_previous_RNO[1]\ : OR2 - port map(A => un1_IIR_CEL_STATE_22, B => N_567_i_0, Y => - N_729); - - un1_IIR_CEL_STATE_17_m27 : NOR3C - port map(A => \Cel_ongoing[11]_net_1\, B => N_26_0, C => - \Cel_ongoing[12]_net_1\, Y => N_28_0); - - \Chanel_ongoing_RNIFV81[17]\ : NOR2B - port map(A => \Chanel_ongoing[17]_net_1\, B => - \Chanel_ongoing[18]_net_1\, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_2); - - \alu_ctrl_RNO[0]\ : OR3 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[6]_net_1\, C => N_289, Y => N_568_i_0); - - \Chanel_ongoing_RNO[23]\ : XA1C - port map(A => \Chanel_ongoing[23]_net_1\, B => - \Chanel_ongoing_RNISG5D[13]_net_1\, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n23); - - \Chanel_ongoing[5]\ : DFN1E1C0 - port map(D => N_20, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[5]_net_1\); - - \Cel_ongoing_RNO_3[0]\ : OR3A - port map(A => N_274, B => N_294, C => - \IIR_CEL_STATE[4]_net_1\, Y => N_457); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2 is - - port( sample_filter_v2_out_0 : out std_logic; - sample_filter_v2_out_1 : out std_logic; - sample_filter_v2_out_2 : out std_logic; - sample_filter_v2_out_3 : out std_logic; - sample_filter_v2_out_4 : out std_logic; - sample_filter_v2_out_5 : out std_logic; - sample_filter_v2_out_6 : out std_logic; - sample_filter_v2_out_7 : out std_logic; - sample_filter_v2_out_8 : out std_logic; - sample_filter_v2_out_9 : out std_logic; - sample_filter_v2_out_10 : out std_logic; - sample_filter_v2_out_11 : out std_logic; - sample_filter_v2_out_12 : out std_logic; - sample_filter_v2_out_13 : out std_logic; - sample_filter_v2_out_14 : out std_logic; - sample_filter_v2_out_15 : out std_logic; - sample_filter_v2_out_18 : out std_logic; - sample_filter_v2_out_19 : out std_logic; - sample_filter_v2_out_20 : out std_logic; - sample_filter_v2_out_21 : out std_logic; - sample_filter_v2_out_22 : out std_logic; - sample_filter_v2_out_23 : out std_logic; - sample_filter_v2_out_24 : out std_logic; - sample_filter_v2_out_25 : out std_logic; - sample_filter_v2_out_26 : out std_logic; - sample_filter_v2_out_27 : out std_logic; - sample_filter_v2_out_28 : out std_logic; - sample_filter_v2_out_29 : out std_logic; - sample_filter_v2_out_30 : out std_logic; - sample_filter_v2_out_31 : out std_logic; - sample_filter_v2_out_32 : out std_logic; - sample_filter_v2_out_33 : out std_logic; - sample_filter_v2_out_36 : out std_logic; - sample_filter_v2_out_37 : out std_logic; - sample_filter_v2_out_38 : out std_logic; - sample_filter_v2_out_39 : out std_logic; - sample_filter_v2_out_40 : out std_logic; - sample_filter_v2_out_41 : out std_logic; - sample_filter_v2_out_42 : out std_logic; - sample_filter_v2_out_43 : out std_logic; - sample_filter_v2_out_44 : out std_logic; - sample_filter_v2_out_45 : out std_logic; - sample_filter_v2_out_46 : out std_logic; - sample_filter_v2_out_47 : out std_logic; - sample_filter_v2_out_48 : out std_logic; - sample_filter_v2_out_49 : out std_logic; - sample_filter_v2_out_50 : out std_logic; - sample_filter_v2_out_51 : out std_logic; - sample_filter_v2_out_54 : out std_logic; - sample_filter_v2_out_55 : out std_logic; - sample_filter_v2_out_56 : out std_logic; - sample_filter_v2_out_57 : out std_logic; - sample_filter_v2_out_58 : out std_logic; - sample_filter_v2_out_59 : out std_logic; - sample_filter_v2_out_60 : out std_logic; - sample_filter_v2_out_61 : out std_logic; - sample_filter_v2_out_62 : out std_logic; - sample_filter_v2_out_63 : out std_logic; - sample_filter_v2_out_64 : out std_logic; - sample_filter_v2_out_65 : out std_logic; - sample_filter_v2_out_66 : out std_logic; - sample_filter_v2_out_67 : out std_logic; - sample_filter_v2_out_68 : out std_logic; - sample_filter_v2_out_69 : out std_logic; - sample_filter_v2_out_90 : out std_logic; - sample_filter_v2_out_91 : out std_logic; - sample_filter_v2_out_92 : out std_logic; - sample_filter_v2_out_93 : out std_logic; - sample_filter_v2_out_94 : out std_logic; - sample_filter_v2_out_95 : out std_logic; - sample_filter_v2_out_96 : out std_logic; - sample_filter_v2_out_97 : out std_logic; - sample_filter_v2_out_98 : out std_logic; - sample_filter_v2_out_99 : out std_logic; - sample_filter_v2_out_100 : out std_logic; - sample_filter_v2_out_101 : out std_logic; - sample_filter_v2_out_102 : out std_logic; - sample_filter_v2_out_103 : out std_logic; - sample_filter_v2_out_104 : out std_logic; - sample_filter_v2_out_105 : out std_logic; - sample_filter_v2_out_108 : out std_logic; - sample_filter_v2_out_126 : out std_logic; - sample_filter_v2_out_109 : out std_logic; - sample_filter_v2_out_127 : out std_logic; - sample_filter_v2_out_110 : out std_logic; - sample_filter_v2_out_128 : out std_logic; - sample_filter_v2_out_111 : out std_logic; - sample_filter_v2_out_129 : out std_logic; - sample_filter_v2_out_112 : out std_logic; - sample_filter_v2_out_130 : out std_logic; - sample_filter_v2_out_113 : out std_logic; - sample_filter_v2_out_131 : out std_logic; - sample_filter_v2_out_114 : out std_logic; - sample_filter_v2_out_132 : out std_logic; - sample_filter_v2_out_115 : out std_logic; - sample_filter_v2_out_133 : out std_logic; - sample_filter_v2_out_116 : out std_logic; - sample_filter_v2_out_134 : out std_logic; - sample_filter_v2_out_117 : out std_logic; - sample_filter_v2_out_135 : out std_logic; - sample_filter_v2_out_118 : out std_logic; - sample_filter_v2_out_136 : out std_logic; - sample_filter_v2_out_119 : out std_logic; - sample_filter_v2_out_137 : out std_logic; - sample_filter_v2_out_120 : out std_logic; - sample_filter_v2_out_138 : out std_logic; - sample_filter_v2_out_121 : out std_logic; - sample_filter_v2_out_139 : out std_logic; - sample_filter_v2_out_122 : out std_logic; - sample_filter_v2_out_140 : out std_logic; - sample_filter_v2_out_123 : out std_logic; - sample_filter_v2_out_141 : out std_logic; - sample_6 : in std_logic_vector(15 downto 0); - sample_5 : in std_logic_vector(15 downto 0); - sample_2 : in std_logic_vector(15 downto 0); - sample_0 : in std_logic_vector(15 downto 0); - sample_1 : in std_logic_vector(15 downto 0); - sample_3 : in std_logic_vector(15 downto 0); - sample_4 : in std_logic_vector(15 downto 0); - sample_7 : in std_logic_vector(15 downto 0); - IIR_CEL_CTRLR_v2_VCC : in std_logic; - IIR_CEL_CTRLR_v2_GND : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_filter_v2_out_val : out std_logic; - sample_val_delay : in std_logic - ); - -end IIR_CEL_CTRLR_v2; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2_DATAFLOW - port( alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - S : out std_logic_vector(8 to 8); - S_i_0 : out std_logic_vector(33 to 33); - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - waddr_previous : in std_logic_vector(1 downto 0) := (others => 'U'); - sample_0 : in std_logic_vector(14 downto 0) := (others => 'U'); - sample_in_buf : in std_logic_vector(143 downto 129) := (others => 'U'); - ram_sel_Wdata : in std_logic_vector(1 downto 0) := (others => 'U'); - sample_out_s_0 : out std_logic; - sample_out_s_1 : out std_logic; - sample_out_s_3 : out std_logic; - sample_out_s_2 : out std_logic; - sample_out_s_10 : out std_logic; - sample_out_s_15 : out std_logic; - sample_out_s_14 : out std_logic; - sample_out_s_13 : out std_logic; - sample_out_s_12 : out std_logic; - sample_out_s_11 : out std_logic; - sample_out_s_9 : out std_logic; - sample_out_s_8 : out std_logic; - sample_out_s_7 : out std_logic; - sample_out_s_6 : out std_logic; - sample_out_s_5 : out std_logic; - sample_out_s_4 : out std_logic; - sample_in_s_1 : in std_logic_vector(17 to 17) := (others => 'U'); - in_sel_src : in std_logic_vector(1 downto 0) := (others => 'U'); - raddr_rst : in std_logic := 'U'; - raddr_add1 : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_DATAFLOW_GND : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_DATAFLOW_VCC : in std_logic := 'U'; - ram_write_i : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_val_delay : in std_logic := 'U'; - alu_sel_input : in std_logic := 'U' - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2_CONTROL - port( alu_ctrl : out std_logic_vector(2 downto 0); - ram_sel_Wdata : out std_logic_vector(1 downto 0); - waddr_previous : out std_logic_vector(1 downto 0); - in_sel_src : out std_logic_vector(1 downto 0); - S_i_0 : in std_logic_vector(33 to 33) := (others => 'U'); - S : in std_logic_vector(8 to 8) := (others => 'U'); - alu_sel_coeff : out std_logic_vector(4 downto 0); - alu_sel_coeff_0_2 : out std_logic; - alu_sel_coeff_0_0 : out std_logic; - sample_out_rot_s : out std_logic; - sample_out_val_s : out std_logic; - raddr_rst : out std_logic; - alu_sel_input : out std_logic; - raddr_add1 : out std_logic; - sample_val_delay : in std_logic := 'U'; - ram_write : out std_logic; - ram_write_i : out std_logic; - un1_sample_in_rotate : out std_logic; - sample_out_rot_s_0 : out std_logic; - sample_out_rot_s_1 : out std_logic; - sample_out_rot_s_2 : out std_logic; - sample_out_rot_s_3 : out std_logic; - sample_out_rot_s_4 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal \sample_in_buf_581[9]\, \sample_in_buf[135]\, - \sample_in_buf_349[59]\, \sample_in_buf[41]\, - \sample_in_buf_669[64]\, \sample_in_buf[46]\, - \sample_in_buf_293[76]\, \sample_in_buf[58]\, - \sample_in_buf_501[115]\, \sample_in_buf[97]\, - \sample_in_buf_821[120]\, \sample_in_buf[102]\, - \sample_in_buf_637[135]\, \sample_in_buf[117]\, - \sample_in_buf_965[15]\, \sample_in_buf[141]\, - \sample_in_buf_29[54]\, \sample_in_buf[36]\, - \sample_in_buf_285[58]\, \sample_in_buf[40]\, - \sample_in_buf_813[102]\, \sample_in_buf[84]\, - \sample_in_buf_437[114]\, \sample_in_buf[96]\, - \sample_in_buf_1021[141]\, \sample_in_buf[123]\, - \sample_in_buf_645[10]\, \sample_in_buf[136]\, - \sample_in_buf_853[49]\, \sample_in_buf[31]\, - \sample_in_buf_1045[52]\, \sample_in_buf[34]\, - \sample_in_buf_805[84]\, \sample_in_buf[66]\, - \sample_in_buf_493[97]\, \sample_in_buf[79]\, - \sample_in_buf_701[136]\, \sample_in_buf[118]\, - \sample_in_buf_389[6]\, \sample_in_buf[132]\, - \sample_in_buf_341[41]\, \sample_in_buf[23]\, - \sample_in_buf_605[63]\, \sample_in_buf[45]\, - \sample_in_buf_1117[71]\, \sample_in_buf[53]\, - \sample_in_buf_757[119]\, \sample_in_buf[101]\, - \sample_in_buf_445[132]\, \sample_in_buf[114]\, - \sample_in_buf_277[40]\, \sample_in_buf[22]\, - \sample_in_buf_725[47]\, \sample_in_buf[29]\, - \sample_in_buf_421[78]\, \sample_in_buf[60]\, - \sample_in_buf_373[113]\, \sample_in_buf[95]\, - \sample_in_buf_1013[123]\, \sample_in_buf[105]\, - \sample_in_buf_261[4]\, \sample_in_buf[130]\, - \sample_in_buf_21[36]\, \sample_in_buf[18]\, - \sample_in_buf_221[57]\, \sample_in_buf[39]\, - \sample_in_buf_749[101]\, \sample_in_buf[83]\, - \sample_in_buf_1133[107]\, \sample_in_buf[89]\, - \sample_in_buf_317[130]\, \sample_in_buf[112]\, - \sample_in_buf_517[8]\, \sample_in_buf[134]\, - \sample_in_buf_773[12]\, \sample_in_buf[138]\, - \sample_in_buf_1101[35]\, \sample_in_buf[17]\, - \sample_in_buf_213[39]\, \sample_in_buf[21]\, - \sample_in_buf_477[61]\, \sample_in_buf[43]\, - \sample_in_buf_1069[106]\, \sample_in_buf[88]\, - \sample_in_buf_573[134]\, \sample_in_buf[116]\, - \sample_in_buf_829[138]\, \sample_in_buf[120]\, - \sample_in_buf_325[5]\, \sample_in_buf[131]\, - \sample_in_buf_845[31]\, \sample_in_buf[13]\, - \sample_in_buf_909[32]\, \sample_in_buf[14]\, - \sample_in_buf_981[51]\, \sample_in_buf[33]\, - \sample_in_buf_741[83]\, \sample_in_buf[65]\, - \sample_in_buf_933[86]\, \sample_in_buf[68]\, - \sample_in_buf_1125[89]\, \sample_in_buf[71]\, - \sample_in_buf_237[93]\, \sample_in_buf[75]\, - \sample_in_buf_245[111]\, \sample_in_buf[93]\, - \sample_in_buf_381[131]\, \sample_in_buf[113]\, - \sample_in_buf_781[30]\, \sample_in_buf[12]\, - \sample_in_buf_789[48]\, \sample_in_buf[30]\, - \sample_in_buf_917[50]\, \sample_in_buf[32]\, - \sample_in_buf_549[80]\, \sample_in_buf[62]\, - \sample_in_buf_613[81]\, \sample_in_buf[63]\, - \sample_in_buf_997[87]\, \sample_in_buf[69]\, - \sample_in_buf_365[95]\, \sample_in_buf[77]\, - \sample_in_buf_949[122]\, \sample_in_buf[104]\, - \sample_in_buf_837[13]\, \sample_in_buf[139]\, - \sample_in_buf_653[28]\, \sample_in_buf[10]\, - \sample_in_buf_469[43]\, \sample_in_buf[25]\, - \sample_in_buf_37[72]\, \sample_in_buf[54]\, - \sample_in_buf_877[103]\, \sample_in_buf[85]\, - \sample_in_buf_893[139]\, \sample_in_buf[121]\, - \sample_in_buf_589[27]\, \sample_in_buf[9]\, - \sample_in_buf_973[33]\, \sample_in_buf[15]\, - \sample_in_buf_533[44]\, \sample_in_buf[26]\, - \sample_in_buf_861[67]\, \sample_in_buf[49]\, - \sample_in_buf_989[69]\, \sample_in_buf[51]\, - \sample_in_buf_869[85]\, \sample_in_buf[67]\, - \sample_in_buf_45[90]\, \sample_in_buf[72]\, - \sample_in_buf_301[94]\, \sample_in_buf[76]\, - \sample_in_buf_941[104]\, \sample_in_buf[86]\, - \sample_in_buf_565[116]\, \sample_in_buf[98]\, - \sample_in_buf_197[3]\, \sample_in_buf[129]\, - \sample_in_buf_525[26]\, \sample_in_buf[8]\, - \sample_in_buf_405[42]\, \sample_in_buf[24]\, - \sample_in_buf_797[66]\, \sample_in_buf[48]\, - \sample_in_buf_677[82]\, \sample_in_buf[64]\, - \sample_in_buf_1141[125]\, \sample_in_buf[107]\, - \sample_in_buf_253[129]\, \sample_in_buf[111]\, - \sample_in_buf_901[14]\, \sample_in_buf[140]\, - \sample_in_buf_1029[16]\, \sample_in_buf[142]\, - \sample_in_buf_461[25]\, \sample_in_buf[7]\, - \sample_in_buf_1037[34]\, \sample_in_buf[16]\, - \sample_in_buf_429[96]\, \sample_in_buf[78]\, - \sample_in_buf_957[140]\, \sample_in_buf[122]\, - \sample_in_buf_1085[142]\, \sample_in_buf[124]\, - \sample_in_buf_709[11]\, \sample_in_buf[137]\, - \sample_in_buf_397[24]\, \sample_in_buf[6]\, - \sample_in_buf_733[65]\, \sample_in_buf[47]\, - \sample_in_buf_485[79]\, \sample_in_buf[61]\, - \sample_in_buf_1077[124]\, \sample_in_buf[106]\, - \sample_in_buf_765[137]\, \sample_in_buf[119]\, - \sample_in_buf_269[22]\, \sample_in_buf[4]\, - \sample_in_buf_333[23]\, \sample_in_buf[5]\, - \sample_in_buf_597[45]\, \sample_in_buf[27]\, - \sample_in_buf_541[62]\, \sample_in_buf[44]\, - \sample_in_buf_925[68]\, \sample_in_buf[50]\, - \sample_in_buf_1053[70]\, \sample_in_buf[52]\, - \sample_in_buf_1061[88]\, \sample_in_buf[70]\, - \sample_in_buf_557[98]\, \sample_in_buf[80]\, - \sample_in_buf_621[99]\, \sample_in_buf[81]\, - \sample_in_buf_309[112]\, \sample_in_buf[94]\, - \sample_in_buf_629[117]\, \sample_in_buf[99]\, - \sample_in_buf_693[118]\, \sample_in_buf[100]\, - \sample_in_buf_5[0]\, \sample_in_buf[128]\, - \sample_in_buf_205[21]\, \sample_in_buf[3]\, - \sample_in_buf_413[60]\, \sample_in_buf[42]\, - \sample_in_buf_1005[105]\, \sample_in_buf[87]\, - \sample_in_buf_61[126]\, \sample_in_buf[108]\, - \sample_in_s_1[17]\, \sample_in_buf_453[7]\, - \sample_in_buf[133]\, \sample_in_buf_13[18]\, - \sample_in_buf[0]\, \sample_in_buf_717[29]\, - \sample_in_buf[11]\, \sample_in_buf_661[46]\, - \sample_in_buf[28]\, \sample_in_buf_1109[53]\, - \sample_in_buf[35]\, \sample_in_buf_229[75]\, - \sample_in_buf[57]\, \sample_in_buf_357[77]\, - \sample_in_buf[59]\, \sample_in_buf_685[100]\, - \sample_in_buf[82]\, \sample_in_buf_53[108]\, - \sample_in_buf[90]\, \sample_in_buf_885[121]\, - \sample_in_buf[103]\, \sample_in_buf_509[133]\, - \sample_in_buf[115]\, \sample_in_buf_1149[143]\, - \sample_in_buf[125]\, \sample_in_buf_1093[17]\, - \sample_in_buf[143]\, \sample_out_val_s2\, - sample_out_val_s, sample_out_rot_s_0, sample_out_rot_s_1, - \sample_filter_v2_out[125]\, \sample_filter_v2_out[124]\, - \sample_filter_v2_out[123]\, \sample_filter_v2_out[122]\, - \sample_filter_v2_out[121]\, \sample_filter_v2_out[120]\, - \sample_filter_v2_out[119]\, sample_out_rot_s_2, - \sample_filter_v2_out[118]\, \sample_filter_v2_out[117]\, - \sample_filter_v2_out[116]\, \sample_filter_v2_out[115]\, - \sample_filter_v2_out[114]\, \sample_filter_v2_out[113]\, - \sample_filter_v2_out[112]\, \sample_filter_v2_out[111]\, - \sample_filter_v2_out[110]\, \sample_filter_v2_out[107]\, - \sample_filter_v2_out[89]\, \sample_filter_v2_out[106]\, - \sample_filter_v2_out[88]\, \sample_filter_v2_out[105]\, - \sample_filter_v2_out[87]\, \sample_filter_v2_out[104]\, - \sample_filter_v2_out[86]\, \sample_filter_v2_out[103]\, - \sample_filter_v2_out[85]\, \sample_filter_v2_out[102]\, - \sample_filter_v2_out[84]\, \sample_filter_v2_out[101]\, - \sample_filter_v2_out[83]\, \sample_filter_v2_out[100]\, - \sample_filter_v2_out[82]\, \sample_filter_v2_out[99]\, - \sample_filter_v2_out[81]\, \sample_filter_v2_out[98]\, - \sample_filter_v2_out[80]\, \sample_filter_v2_out[97]\, - \sample_filter_v2_out[79]\, \sample_filter_v2_out[96]\, - \sample_filter_v2_out[78]\, \sample_filter_v2_out[95]\, - \sample_filter_v2_out[77]\, \sample_filter_v2_out[94]\, - \sample_filter_v2_out[76]\, \sample_filter_v2_out[93]\, - \sample_filter_v2_out[75]\, \sample_filter_v2_out[92]\, - \sample_filter_v2_out[74]\, sample_out_rot_s_3, - \sample_filter_v2_out[71]\, \sample_filter_v2_out[70]\, - \sample_filter_v2_out[69]\, sample_out_rot_s_4, - \sample_filter_v2_out[68]\, \sample_filter_v2_out[67]\, - \sample_filter_v2_out[66]\, \sample_filter_v2_out[65]\, - \sample_filter_v2_out[64]\, \sample_filter_v2_out[63]\, - \sample_filter_v2_out[62]\, \sample_filter_v2_out[61]\, - \sample_filter_v2_out[60]\, \sample_filter_v2_out[59]\, - \sample_filter_v2_out[58]\, \sample_filter_v2_out[57]\, - \sample_filter_v2_out[56]\, \sample_filter_v2_out[53]\, - \sample_filter_v2_out[52]\, \sample_filter_v2_out[51]\, - \sample_filter_v2_out[50]\, \sample_filter_v2_out[49]\, - \sample_filter_v2_out[48]\, \sample_filter_v2_out[47]\, - \sample_filter_v2_out[46]\, \sample_filter_v2_out[45]\, - sample_out_rot_s, \sample_filter_v2_out[44]\, - \sample_filter_v2_out[43]\, \sample_filter_v2_out[42]\, - \sample_filter_v2_out[41]\, \sample_filter_v2_out[40]\, - \sample_filter_v2_out[39]\, \sample_filter_v2_out[38]\, - un1_sample_in_rotate, \sample_filter_v2_out[35]\, - \sample_filter_v2_out[34]\, \sample_filter_v2_out[33]\, - \sample_filter_v2_out[32]\, \sample_filter_v2_out[31]\, - \sample_filter_v2_out[30]\, \sample_filter_v2_out[29]\, - \sample_filter_v2_out[28]\, \sample_filter_v2_out[27]\, - \sample_filter_v2_out[26]\, \sample_filter_v2_out[25]\, - \sample_filter_v2_out[24]\, \sample_filter_v2_out[23]\, - \sample_filter_v2_out[22]\, \sample_filter_v2_out[21]\, - \sample_filter_v2_out[20]\, \sample_filter_v2_out[17]\, - \sample_out_s[0]\, \sample_filter_v2_out[16]\, - \sample_out_s[1]\, \sample_filter_v2_out[15]\, - \sample_out_s[2]\, \sample_filter_v2_out[14]\, - \sample_out_s[3]\, \sample_filter_v2_out[13]\, - \sample_out_s[4]\, \sample_filter_v2_out[12]\, - \sample_out_s[5]\, \sample_filter_v2_out[11]\, - \sample_out_s[6]\, \sample_filter_v2_out[10]\, - \sample_out_s[7]\, \sample_filter_v2_out[9]\, - \sample_out_s[8]\, \sample_filter_v2_out[8]\, - \sample_out_s[9]\, \sample_filter_v2_out[7]\, - \sample_out_s[10]\, \sample_filter_v2_out[6]\, - \sample_out_s[11]\, \sample_filter_v2_out[5]\, - \sample_out_s[12]\, \sample_filter_v2_out[4]\, - \sample_out_s[13]\, \sample_filter_v2_out[3]\, - \sample_out_s[14]\, \sample_filter_v2_out[2]\, - \sample_out_s[15]\, \alu_ctrl[0]\, \alu_ctrl[1]\, - \alu_ctrl[2]\, \S[8]\, \S_i_0[33]\, \alu_sel_coeff[0]\, - \alu_sel_coeff[1]\, \alu_sel_coeff[2]\, - \alu_sel_coeff[3]\, \alu_sel_coeff[4]\, - \alu_sel_coeff_0[2]\, \alu_sel_coeff_0[0]\, - \waddr_previous[0]\, \waddr_previous[1]\, - \ram_sel_Wdata[0]\, \ram_sel_Wdata[1]\, \in_sel_src[0]\, - \in_sel_src[1]\, raddr_rst, raddr_add1, ram_write, - ram_write_i, alu_sel_input, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : IIR_CEL_CTRLR_v2_DATAFLOW - Use entity work.IIR_CEL_CTRLR_v2_DATAFLOW(DEF_ARCH); - for all : IIR_CEL_CTRLR_v2_CONTROL - Use entity work.IIR_CEL_CTRLR_v2_CONTROL(DEF_ARCH); -begin - - sample_filter_v2_out_0 <= \sample_filter_v2_out[2]\; - sample_filter_v2_out_1 <= \sample_filter_v2_out[3]\; - sample_filter_v2_out_2 <= \sample_filter_v2_out[4]\; - sample_filter_v2_out_3 <= \sample_filter_v2_out[5]\; - sample_filter_v2_out_4 <= \sample_filter_v2_out[6]\; - sample_filter_v2_out_5 <= \sample_filter_v2_out[7]\; - sample_filter_v2_out_6 <= \sample_filter_v2_out[8]\; - sample_filter_v2_out_7 <= \sample_filter_v2_out[9]\; - sample_filter_v2_out_8 <= \sample_filter_v2_out[10]\; - sample_filter_v2_out_9 <= \sample_filter_v2_out[11]\; - sample_filter_v2_out_10 <= \sample_filter_v2_out[12]\; - sample_filter_v2_out_11 <= \sample_filter_v2_out[13]\; - sample_filter_v2_out_12 <= \sample_filter_v2_out[14]\; - sample_filter_v2_out_13 <= \sample_filter_v2_out[15]\; - sample_filter_v2_out_14 <= \sample_filter_v2_out[16]\; - sample_filter_v2_out_15 <= \sample_filter_v2_out[17]\; - sample_filter_v2_out_18 <= \sample_filter_v2_out[20]\; - sample_filter_v2_out_19 <= \sample_filter_v2_out[21]\; - sample_filter_v2_out_20 <= \sample_filter_v2_out[22]\; - sample_filter_v2_out_21 <= \sample_filter_v2_out[23]\; - sample_filter_v2_out_22 <= \sample_filter_v2_out[24]\; - sample_filter_v2_out_23 <= \sample_filter_v2_out[25]\; - sample_filter_v2_out_24 <= \sample_filter_v2_out[26]\; - sample_filter_v2_out_25 <= \sample_filter_v2_out[27]\; - sample_filter_v2_out_26 <= \sample_filter_v2_out[28]\; - sample_filter_v2_out_27 <= \sample_filter_v2_out[29]\; - sample_filter_v2_out_28 <= \sample_filter_v2_out[30]\; - sample_filter_v2_out_29 <= \sample_filter_v2_out[31]\; - sample_filter_v2_out_30 <= \sample_filter_v2_out[32]\; - sample_filter_v2_out_31 <= \sample_filter_v2_out[33]\; - sample_filter_v2_out_32 <= \sample_filter_v2_out[34]\; - sample_filter_v2_out_33 <= \sample_filter_v2_out[35]\; - sample_filter_v2_out_36 <= \sample_filter_v2_out[38]\; - sample_filter_v2_out_37 <= \sample_filter_v2_out[39]\; - sample_filter_v2_out_38 <= \sample_filter_v2_out[40]\; - sample_filter_v2_out_39 <= \sample_filter_v2_out[41]\; - sample_filter_v2_out_40 <= \sample_filter_v2_out[42]\; - sample_filter_v2_out_41 <= \sample_filter_v2_out[43]\; - sample_filter_v2_out_42 <= \sample_filter_v2_out[44]\; - sample_filter_v2_out_43 <= \sample_filter_v2_out[45]\; - sample_filter_v2_out_44 <= \sample_filter_v2_out[46]\; - sample_filter_v2_out_45 <= \sample_filter_v2_out[47]\; - sample_filter_v2_out_46 <= \sample_filter_v2_out[48]\; - sample_filter_v2_out_47 <= \sample_filter_v2_out[49]\; - sample_filter_v2_out_48 <= \sample_filter_v2_out[50]\; - sample_filter_v2_out_49 <= \sample_filter_v2_out[51]\; - sample_filter_v2_out_50 <= \sample_filter_v2_out[52]\; - sample_filter_v2_out_51 <= \sample_filter_v2_out[53]\; - sample_filter_v2_out_54 <= \sample_filter_v2_out[56]\; - sample_filter_v2_out_55 <= \sample_filter_v2_out[57]\; - sample_filter_v2_out_56 <= \sample_filter_v2_out[58]\; - sample_filter_v2_out_57 <= \sample_filter_v2_out[59]\; - sample_filter_v2_out_58 <= \sample_filter_v2_out[60]\; - sample_filter_v2_out_59 <= \sample_filter_v2_out[61]\; - sample_filter_v2_out_60 <= \sample_filter_v2_out[62]\; - sample_filter_v2_out_61 <= \sample_filter_v2_out[63]\; - sample_filter_v2_out_62 <= \sample_filter_v2_out[64]\; - sample_filter_v2_out_63 <= \sample_filter_v2_out[65]\; - sample_filter_v2_out_64 <= \sample_filter_v2_out[66]\; - sample_filter_v2_out_65 <= \sample_filter_v2_out[67]\; - sample_filter_v2_out_66 <= \sample_filter_v2_out[68]\; - sample_filter_v2_out_67 <= \sample_filter_v2_out[69]\; - sample_filter_v2_out_68 <= \sample_filter_v2_out[70]\; - sample_filter_v2_out_69 <= \sample_filter_v2_out[71]\; - sample_filter_v2_out_90 <= \sample_filter_v2_out[92]\; - sample_filter_v2_out_91 <= \sample_filter_v2_out[93]\; - sample_filter_v2_out_92 <= \sample_filter_v2_out[94]\; - sample_filter_v2_out_93 <= \sample_filter_v2_out[95]\; - sample_filter_v2_out_94 <= \sample_filter_v2_out[96]\; - sample_filter_v2_out_95 <= \sample_filter_v2_out[97]\; - sample_filter_v2_out_96 <= \sample_filter_v2_out[98]\; - sample_filter_v2_out_97 <= \sample_filter_v2_out[99]\; - sample_filter_v2_out_98 <= \sample_filter_v2_out[100]\; - sample_filter_v2_out_99 <= \sample_filter_v2_out[101]\; - sample_filter_v2_out_100 <= \sample_filter_v2_out[102]\; - sample_filter_v2_out_101 <= \sample_filter_v2_out[103]\; - sample_filter_v2_out_102 <= \sample_filter_v2_out[104]\; - sample_filter_v2_out_103 <= \sample_filter_v2_out[105]\; - sample_filter_v2_out_104 <= \sample_filter_v2_out[106]\; - sample_filter_v2_out_105 <= \sample_filter_v2_out[107]\; - sample_filter_v2_out_108 <= \sample_filter_v2_out[110]\; - sample_filter_v2_out_109 <= \sample_filter_v2_out[111]\; - sample_filter_v2_out_110 <= \sample_filter_v2_out[112]\; - sample_filter_v2_out_111 <= \sample_filter_v2_out[113]\; - sample_filter_v2_out_112 <= \sample_filter_v2_out[114]\; - sample_filter_v2_out_113 <= \sample_filter_v2_out[115]\; - sample_filter_v2_out_114 <= \sample_filter_v2_out[116]\; - sample_filter_v2_out_115 <= \sample_filter_v2_out[117]\; - sample_filter_v2_out_116 <= \sample_filter_v2_out[118]\; - sample_filter_v2_out_117 <= \sample_filter_v2_out[119]\; - sample_filter_v2_out_118 <= \sample_filter_v2_out[120]\; - sample_filter_v2_out_119 <= \sample_filter_v2_out[121]\; - sample_filter_v2_out_120 <= \sample_filter_v2_out[122]\; - sample_filter_v2_out_121 <= \sample_filter_v2_out[123]\; - sample_filter_v2_out_122 <= \sample_filter_v2_out[124]\; - sample_filter_v2_out_123 <= \sample_filter_v2_out[125]\; - - \loop_all_sample.2.loop_all_chanel.6.sample_in_buf[33]\ : - DFN1E1C0 - port map(D => \sample_in_buf_973[33]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[33]\); - - \loop_all_sample.13.loop_all_chanel.7.sample_in_buf[4]\ : - DFN1E1C0 - port map(D => \sample_in_buf_261[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[4]\); - - \loop_all_sample.9.loop_all_chanel.4.sample_in_buf_RNO[62]\ : - MX2 - port map(A => \sample_in_buf[44]\, B => sample_4(9), S => - sample_val_delay, Y => \sample_in_buf_541[62]\); - - \loop_all_sample.10.loop_all_chanel.2.sample_in_buf_RNO[97]\ : - MX2 - port map(A => \sample_in_buf[79]\, B => sample_2(10), S => - sample_val_delay, Y => \sample_in_buf_493[97]\); - - \chanel_more.all_chanel.2.all_bit.3.sample_out_s2[122]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[104]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[122]\); - - \loop_all_sample.5.loop_all_chanel.4.sample_in_buf_RNO[66]\ : - MX2 - port map(A => \sample_in_buf[48]\, B => sample_4(5), S => - sample_val_delay, Y => \sample_in_buf_797[66]\); - - \loop_all_sample.1.loop_all_chanel.6.sample_in_buf[34]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1037[34]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[34]\); - - \chanel_more.all_chanel.3.all_bit.1.sample_out_s2[106]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[88]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[106]\); - - \loop_all_sample.6.loop_all_chanel.1.sample_in_buf_RNO[119]\ : - MX2 - port map(A => \sample_in_buf[101]\, B => sample_1(6), S => - sample_val_delay, Y => \sample_in_buf_757[119]\); - - \loop_all_sample.12.loop_all_chanel.4.sample_in_buf_RNO[59]\ : - MX2 - port map(A => \sample_in_buf[41]\, B => sample_4(12), S => - sample_val_delay, Y => \sample_in_buf_349[59]\); - - \chanel_more.all_chanel.1.all_bit.6.sample_out_s2[137]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[119]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_135); - - \chanel_more.all_chanel.7.all_bit.3.sample_out_s2[32]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[14]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[32]\); - - \chanel_more.all_chanel.5.all_bit.10.sample_out_s2[61]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[43]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[61]\); - - \loop_all_sample.6.loop_all_chanel.0.sample_in_buf_RNO[137]\ : - MX2 - port map(A => \sample_in_buf[119]\, B => sample_0(6), S => - sample_val_delay, Y => \sample_in_buf_765[137]\); - - \chanel_more.all_chanel.6.all_bit.0.sample_out_s2[53]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[35]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[53]\); - - \chanel_more.all_chanel.4.all_bit.13.sample_out_s2[76]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[58]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[76]\); - - \loop_all_sample.9.loop_all_chanel.0.sample_in_buf_RNO[134]\ : - MX2 - port map(A => \sample_in_buf[116]\, B => sample_0(9), S => - sample_val_delay, Y => \sample_in_buf_573[134]\); - - \loop_all_sample.8.loop_all_chanel.2.sample_in_buf[99]\ : - DFN1E1C0 - port map(D => \sample_in_buf_621[99]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[99]\); - - \chanel_more.all_chanel.3.all_bit.11.sample_out_s2[96]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[78]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[96]\); - - \chanel_more.all_chanel.6.all_bit.2.sample_out_s2[51]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[33]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[51]\); - - \loop_all_sample.12.loop_all_chanel.5.sample_in_buf_RNO[41]\ : - MX2 - port map(A => \sample_in_buf[23]\, B => sample_5(12), S => - sample_val_delay, Y => \sample_in_buf_341[41]\); - - \loop_all_sample.1.loop_all_chanel.2.sample_in_buf[106]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1069[106]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[106]\); - - \loop_all_sample.17.loop_all_chanel.7.sample_in_buf_RNO[0]\ : - MX2 - port map(A => \sample_in_buf[128]\, B => sample_7(15), S - => sample_val_delay, Y => \sample_in_buf_5[0]\); - - \loop_all_sample.13.loop_all_chanel.5.sample_in_buf[40]\ : - DFN1E1C0 - port map(D => \sample_in_buf_277[40]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[40]\); - - \loop_all_sample.13.loop_all_chanel.0.sample_in_buf_RNO[130]\ : - MX2 - port map(A => \sample_in_buf[112]\, B => sample_0(13), S - => sample_val_delay, Y => \sample_in_buf_317[130]\); - - \loop_all_sample.3.loop_all_chanel.4.sample_in_buf_RNO[68]\ : - MX2 - port map(A => \sample_in_buf[50]\, B => sample_4(3), S => - sample_val_delay, Y => \sample_in_buf_925[68]\); - - \chanel_more.all_chanel.1.all_bit.3.sample_out_s2[140]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[122]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_138); - - \loop_all_sample.13.loop_all_chanel.2.sample_in_buf_RNO[94]\ : - MX2 - port map(A => \sample_in_buf[76]\, B => sample_2(13), S => - sample_val_delay, Y => \sample_in_buf_301[94]\); - - \loop_all_sample.11.loop_all_chanel.3.sample_in_buf_RNO[78]\ : - MX2 - port map(A => \sample_in_buf[60]\, B => sample_3(11), S => - sample_val_delay, Y => \sample_in_buf_421[78]\); - - \chanel_more.all_chanel.4.all_bit.1.sample_out_s2[88]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[70]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[88]\); - - \chanel_more.all_chanel.3.all_bit.4.sample_out_s2[103]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[85]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[103]\); - - \loop_all_sample.7.loop_all_chanel.4.sample_in_buf_RNO[64]\ : - MX2 - port map(A => \sample_in_buf[46]\, B => sample_4(7), S => - sample_val_delay, Y => \sample_in_buf_669[64]\); - - \loop_all_sample.5.loop_all_chanel.3.sample_in_buf[84]\ : - DFN1E1C0 - port map(D => \sample_in_buf_805[84]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[84]\); - - \chanel_more.all_chanel.6.all_bit.15.sample_out_s2[38]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[20]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[38]\); - - \loop_all_sample.12.loop_all_chanel.5.sample_in_buf[41]\ : - DFN1E1C0 - port map(D => \sample_in_buf_341[41]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[41]\); - - \chanel_more.all_chanel.5.all_bit.7.sample_out_s2[64]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[46]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[64]\); - - \chanel_more.all_chanel.5.all_bit.6.sample_out_s2[65]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[47]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[65]\); - - \chanel_more.all_chanel.7.all_bit.2.sample_out_s2[33]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[15]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[33]\); - - \loop_all_sample.9.loop_all_chanel.3.sample_in_buf_RNO[80]\ : - MX2 - port map(A => \sample_in_buf[62]\, B => sample_3(9), S => - sample_val_delay, Y => \sample_in_buf_549[80]\); - - \loop_all_sample.2.loop_all_chanel.4.sample_in_buf_RNO[69]\ : - MX2 - port map(A => \sample_in_buf[51]\, B => sample_4(2), S => - sample_val_delay, Y => \sample_in_buf_989[69]\); - - \loop_all_sample.14.loop_all_chanel.6.sample_in_buf[21]\ : - DFN1E1C0 - port map(D => \sample_in_buf_205[21]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[21]\); - - \loop_all_sample.9.loop_all_chanel.5.sample_in_buf[44]\ : - DFN1E1C0 - port map(D => \sample_in_buf_533[44]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[44]\); - - \loop_all_sample.11.loop_all_chanel.5.sample_in_buf[42]\ : - DFN1E1C0 - port map(D => \sample_in_buf_405[42]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[42]\); - - \loop_all_sample.9.loop_all_chanel.2.sample_in_buf_RNO[98]\ : - MX2 - port map(A => \sample_in_buf[80]\, B => sample_2(9), S => - sample_val_delay, Y => \sample_in_buf_557[98]\); - - \loop_all_sample.10.loop_all_chanel.4.sample_in_buf_RNO[61]\ : - MX2 - port map(A => \sample_in_buf[43]\, B => sample_4(10), S => - sample_val_delay, Y => \sample_in_buf_477[61]\); - - \chanel_more.all_chanel.1.all_bit.8.sample_out_s2[135]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[117]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_133); - - \loop_all_sample.9.loop_all_chanel.6.sample_in_buf[26]\ : - DFN1E1C0 - port map(D => \sample_in_buf_525[26]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[26]\); - - \chanel_more.all_chanel.1.all_bit.9.sample_out_s2[134]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[116]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_132); - - \loop_all_sample.11.loop_all_chanel.7.sample_in_buf_RNO[6]\ : - MX2 - port map(A => \sample_in_buf[132]\, B => sample_7(11), S - => sample_val_delay, Y => \sample_in_buf_389[6]\); - - \loop_all_sample.1.loop_all_chanel.6.sample_in_buf_RNO[34]\ : - MX2 - port map(A => \sample_in_buf[16]\, B => sample_6(1), S => - sample_val_delay, Y => \sample_in_buf_1037[34]\); - - \loop_all_sample.3.loop_all_chanel.3.sample_in_buf[86]\ : - DFN1E1C0 - port map(D => \sample_in_buf_933[86]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[86]\); - - \chanel_more.all_chanel.6.all_bit.1.sample_out_s2[52]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[34]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[52]\); - - \chanel_HIGH.6.sample_out_s2[11]\ : DFN1E1C0 - port map(D => \sample_out_s[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[11]\); - - \loop_all_sample.11.loop_all_chanel.2.sample_in_buf_RNO[96]\ : - MX2 - port map(A => \sample_in_buf[78]\, B => sample_2(11), S => - sample_val_delay, Y => \sample_in_buf_429[96]\); - - \chanel_more.all_chanel.1.all_bit.5.sample_out_s2[138]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[120]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_136); - - \loop_all_sample.2.loop_all_chanel.7.sample_in_buf_RNO[15]\ : - MX2 - port map(A => \sample_in_buf[141]\, B => sample_7(2), S => - sample_val_delay, Y => \sample_in_buf_965[15]\); - - \loop_all_sample.13.loop_all_chanel.2.sample_in_buf[94]\ : - DFN1E1C0 - port map(D => \sample_in_buf_301[94]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[94]\); - - \loop_all_sample.17.loop_all_chanel.1.sample_in_buf[108]\ : - DFN1E1C0 - port map(D => \sample_in_buf_53[108]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[108]\); - - \loop_all_sample.0.loop_all_chanel.6.sample_in_buf_RNO[35]\ : - MX2 - port map(A => \sample_in_buf[17]\, B => sample_6(0), S => - sample_val_delay, Y => \sample_in_buf_1101[35]\); - - \loop_all_sample.4.loop_all_chanel.0.sample_in_buf_RNO[139]\ : - MX2 - port map(A => \sample_in_buf[121]\, B => sample_0(4), S => - sample_val_delay, Y => \sample_in_buf_893[139]\); - - \loop_all_sample.0.loop_all_chanel.3.sample_in_buf[89]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1125[89]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[89]\); - - \chanel_more.all_chanel.5.all_bit.9.sample_out_s2[62]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[44]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[62]\); - - \loop_all_sample.11.loop_all_chanel.2.sample_in_buf[96]\ : - DFN1E1C0 - port map(D => \sample_in_buf_429[96]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[96]\); - - \loop_all_sample.1.loop_all_chanel.3.sample_in_buf[88]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1061[88]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[88]\); - - \chanel_more.all_chanel.4.all_bit.11.sample_out_s2[78]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[60]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[78]\); - - \chanel_HIGH.15.sample_out_s2[2]\ : DFN1E1C0 - port map(D => \sample_out_s[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[2]\); - - \loop_all_sample.0.loop_all_chanel.5.sample_in_buf_RNO[53]\ : - MX2 - port map(A => \sample_in_buf[35]\, B => sample_5(0), S => - sample_val_delay, Y => \sample_in_buf_1109[53]\); - - \loop_all_sample.6.loop_all_chanel.4.sample_in_buf[65]\ : - DFN1E1C0 - port map(D => \sample_in_buf_733[65]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[65]\); - - \loop_all_sample.7.loop_all_chanel.7.sample_in_buf_RNO[10]\ : - MX2 - port map(A => \sample_in_buf[136]\, B => sample_7(7), S => - sample_val_delay, Y => \sample_in_buf_645[10]\); - - \loop_all_sample.17.loop_all_chanel.4.sample_in_buf[54]\ : - DFN1E1C0 - port map(D => \sample_in_buf_29[54]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[54]\); - - \loop_all_sample.4.loop_all_chanel.1.sample_in_buf_RNO[121]\ : - MX2 - port map(A => \sample_in_buf[103]\, B => sample_1(4), S => - sample_val_delay, Y => \sample_in_buf_885[121]\); - - \loop_all_sample.13.loop_all_chanel.6.sample_in_buf[22]\ : - DFN1E1C0 - port map(D => \sample_in_buf_269[22]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[22]\); - - \loop_all_sample.17.loop_all_chanel.2.sample_in_buf_RNO[90]\ : - MX2 - port map(A => \sample_in_buf[72]\, B => sample_2(15), S => - sample_val_delay, Y => \sample_in_buf_45[90]\); - - \loop_all_sample.11.loop_all_chanel.6.sample_in_buf_RNO[24]\ : - MX2 - port map(A => \sample_in_buf[6]\, B => sample_6(11), S => - sample_val_delay, Y => \sample_in_buf_397[24]\); - - \loop_all_sample.1.loop_all_chanel.7.sample_in_buf_RNO[16]\ : - MX2 - port map(A => \sample_in_buf[142]\, B => sample_7(1), S => - sample_val_delay, Y => \sample_in_buf_1029[16]\); - - \loop_all_sample.6.loop_all_chanel.7.sample_in_buf[11]\ : - DFN1E1C0 - port map(D => \sample_in_buf_709[11]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[11]\); - - \chanel_more.all_chanel.6.all_bit.8.sample_out_s2[45]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[27]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[45]\); - - \loop_all_sample.7.loop_all_chanel.0.sample_in_buf_RNO[136]\ : - MX2 - port map(A => \sample_in_buf[118]\, B => sample_0(7), S => - sample_val_delay, Y => \sample_in_buf_701[136]\); - - \chanel_more.all_chanel.3.all_bit.10.sample_out_s2[97]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[79]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[97]\); - - \loop_all_sample.4.loop_all_chanel.5.sample_in_buf_RNO[49]\ : - MX2 - port map(A => \sample_in_buf[31]\, B => sample_5(4), S => - sample_val_delay, Y => \sample_in_buf_853[49]\); - - \chanel_more.all_chanel.1.all_bit.13.sample_out_s2[130]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[112]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_128); - - \loop_all_sample.13.loop_all_chanel.5.sample_in_buf_RNO[40]\ : - MX2 - port map(A => \sample_in_buf[22]\, B => sample_5(13), S => - sample_val_delay, Y => \sample_in_buf_277[40]\); - - \loop_all_sample.17.loop_all_chanel.3.sample_in_buf[72]\ : - DFN1E1C0 - port map(D => \sample_in_buf_37[72]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[72]\); - - \chanel_more.all_chanel.6.all_bit.12.sample_out_s2[41]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[23]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[41]\); - - \chanel_more.all_chanel.4.all_bit.4.sample_out_s2[85]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[67]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[85]\); - - \loop_all_sample.5.loop_all_chanel.1.sample_in_buf[120]\ : - DFN1E1C0 - port map(D => \sample_in_buf_821[120]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[120]\); - - \loop_all_sample.11.loop_all_chanel.4.sample_in_buf_RNO[60]\ : - MX2 - port map(A => \sample_in_buf[42]\, B => sample_4(11), S => - sample_val_delay, Y => \sample_in_buf_413[60]\); - - \loop_all_sample.0.loop_all_chanel.1.sample_in_buf_RNO[125]\ : - MX2 - port map(A => \sample_in_buf[107]\, B => sample_1(0), S => - sample_val_delay, Y => \sample_in_buf_1141[125]\); - - \loop_all_sample.7.loop_all_chanel.2.sample_in_buf[100]\ : - DFN1E1C0 - port map(D => \sample_in_buf_685[100]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[100]\); - - \loop_all_sample.9.loop_all_chanel.7.sample_in_buf[8]\ : - DFN1E1C0 - port map(D => \sample_in_buf_517[8]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[8]\); - - \chanel_more.all_chanel.2.all_bit.7.sample_out_s2[118]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[100]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[118]\); - - \chanel_HIGH.9.sample_out_s2[8]\ : DFN1E1C0 - port map(D => \sample_out_s[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[8]\); - - \loop_all_sample.6.loop_all_chanel.5.sample_in_buf[47]\ : - DFN1E1C0 - port map(D => \sample_in_buf_725[47]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[47]\); - - \loop_all_sample.13.loop_all_chanel.4.sample_in_buf[58]\ : - DFN1E1C0 - port map(D => \sample_in_buf_285[58]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[58]\); - - \chanel_more.all_chanel.4.all_bit.5.sample_out_s2[84]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[66]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[84]\); - - \loop_all_sample.4.loop_all_chanel.2.sample_in_buf[103]\ : - DFN1E1C0 - port map(D => \sample_in_buf_877[103]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[103]\); - - \loop_all_sample.1.loop_all_chanel.7.sample_in_buf[16]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1029[16]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[16]\); - - \chanel_HIGH.7.sample_out_s2[10]\ : DFN1E1C0 - port map(D => \sample_out_s[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[10]\); - - \loop_all_sample.13.loop_all_chanel.7.sample_in_buf_RNO[4]\ : - MX2 - port map(A => \sample_in_buf[130]\, B => sample_7(13), S - => sample_val_delay, Y => \sample_in_buf_261[4]\); - - \loop_all_sample.11.loop_all_chanel.7.sample_in_buf[6]\ : - DFN1E1C0 - port map(D => \sample_in_buf_389[6]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[6]\); - - GND_i : GND - port map(Y => \GND\); - - \loop_all_sample.1.loop_all_chanel.3.sample_in_buf_RNO[88]\ : - MX2 - port map(A => \sample_in_buf[70]\, B => sample_3(1), S => - sample_val_delay, Y => \sample_in_buf_1061[88]\); - - \loop_all_sample.13.loop_all_chanel.4.sample_in_buf_RNO[58]\ : - MX2 - port map(A => \sample_in_buf[40]\, B => sample_4(13), S => - sample_val_delay, Y => \sample_in_buf_285[58]\); - - \chanel_more.all_chanel.1.all_bit.4.sample_out_s2[139]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[121]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_137); - - \chanel_more.all_chanel.7.all_bit.6.sample_out_s2[29]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[11]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[29]\); - - \loop_all_sample.2.loop_all_chanel.2.sample_in_buf_RNO[105]\ : - MX2 - port map(A => \sample_in_buf[87]\, B => sample_2(2), S => - sample_val_delay, Y => \sample_in_buf_1005[105]\); - - \loop_all_sample.10.loop_all_chanel.2.sample_in_buf[97]\ : - DFN1E1C0 - port map(D => \sample_in_buf_493[97]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[97]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \loop_all_sample.2.loop_all_chanel.5.sample_in_buf_RNO[51]\ : - MX2 - port map(A => \sample_in_buf[33]\, B => sample_5(2), S => - sample_val_delay, Y => \sample_in_buf_981[51]\); - - \loop_all_sample.17.loop_all_chanel.5.sample_in_buf[36]\ : - DFN1E1C0 - port map(D => \sample_in_buf_21[36]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[36]\); - - \loop_all_sample.17.loop_all_chanel.3.sample_in_buf_RNO[72]\ : - MX2 - port map(A => \sample_in_buf[54]\, B => sample_3(15), S => - sample_val_delay, Y => \sample_in_buf_37[72]\); - - \chanel_more.all_chanel.2.all_bit.9.sample_out_s2[116]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[98]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[116]\); - - \loop_all_sample.7.loop_all_chanel.1.sample_in_buf_RNO[118]\ : - MX2 - port map(A => \sample_in_buf[100]\, B => sample_1(7), S => - sample_val_delay, Y => \sample_in_buf_693[118]\); - - \chanel_more.all_chanel.2.all_bit.10.sample_out_s2[115]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[97]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[115]\); - - \chanel_more.all_chanel.3.all_bit.6.sample_out_s2[101]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[83]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[101]\); - - \loop_all_sample.9.loop_all_chanel.4.sample_in_buf[62]\ : - DFN1E1C0 - port map(D => \sample_in_buf_541[62]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[62]\); - - \loop_all_sample.14.loop_all_chanel.0.sample_in_buf[129]\ : - DFN1E1C0 - port map(D => \sample_in_buf_253[129]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[129]\); - - \loop_all_sample.7.loop_all_chanel.0.sample_in_buf[136]\ : - DFN1E1C0 - port map(D => \sample_in_buf_701[136]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[136]\); - - \chanel_more.all_chanel.4.all_bit.0.sample_out_s2[89]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[71]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[89]\); - - \loop_all_sample.3.loop_all_chanel.2.sample_in_buf[104]\ : - DFN1E1C0 - port map(D => \sample_in_buf_941[104]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[104]\); - - \loop_all_sample.5.loop_all_chanel.2.sample_in_buf_RNO[102]\ : - MX2 - port map(A => \sample_in_buf[84]\, B => sample_2(5), S => - sample_val_delay, Y => \sample_in_buf_813[102]\); - - \loop_all_sample.4.loop_all_chanel.1.sample_in_buf[121]\ : - DFN1E1C0 - port map(D => \sample_in_buf_885[121]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[121]\); - - \chanel_more.all_chanel.6.all_bit.11.sample_out_s2[42]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[24]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[42]\); - - \loop_all_sample.10.loop_all_chanel.5.sample_in_buf[43]\ : - DFN1E1C0 - port map(D => \sample_in_buf_469[43]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[43]\); - - \chanel_more.all_chanel.5.all_bit.0.sample_out_s2[71]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[53]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[71]\); - - \loop_all_sample.11.loop_all_chanel.0.sample_in_buf_RNO[132]\ : - MX2 - port map(A => \sample_in_buf[114]\, B => sample_0(11), S - => sample_val_delay, Y => \sample_in_buf_445[132]\); - - \chanel_more.all_chanel.6.all_bit.6.sample_out_s2[47]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[29]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[47]\); - - \loop_all_sample.12.loop_all_chanel.2.sample_in_buf[95]\ : - DFN1E1C0 - port map(D => \sample_in_buf_365[95]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[95]\); - - \chanel_more.all_chanel.7.all_bit.1.sample_out_s2[34]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[16]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[34]\); - - \loop_all_sample.6.loop_all_chanel.2.sample_in_buf[101]\ : - DFN1E1C0 - port map(D => \sample_in_buf_749[101]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[101]\); - - \loop_all_sample.9.loop_all_chanel.1.sample_in_buf_RNO[116]\ : - MX2 - port map(A => \sample_in_buf[98]\, B => sample_1(9), S => - sample_val_delay, Y => \sample_in_buf_565[116]\); - - \loop_all_sample.4.loop_all_chanel.2.sample_in_buf_RNO[103]\ : - MX2 - port map(A => \sample_in_buf[85]\, B => sample_2(4), S => - sample_val_delay, Y => \sample_in_buf_877[103]\); - - \loop_all_sample.10.loop_all_chanel.1.sample_in_buf_RNO[115]\ : - MX2 - port map(A => \sample_in_buf[97]\, B => sample_1(10), S => - sample_val_delay, Y => \sample_in_buf_501[115]\); - - \loop_all_sample.5.loop_all_chanel.5.sample_in_buf_RNO[48]\ : - MX2 - port map(A => \sample_in_buf[30]\, B => sample_5(5), S => - sample_val_delay, Y => \sample_in_buf_789[48]\); - - \loop_all_sample.3.loop_all_chanel.2.sample_in_buf_RNO[104]\ : - MX2 - port map(A => \sample_in_buf[86]\, B => sample_2(3), S => - sample_val_delay, Y => \sample_in_buf_941[104]\); - - \chanel_more.all_chanel.7.all_bit.15.sample_out_s2[20]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[20]\); - - \loop_all_sample.2.loop_all_chanel.1.sample_in_buf[123]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1013[123]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[123]\); - - \chanel_HIGH.13.sample_out_s2[4]\ : DFN1E1C0 - port map(D => \sample_out_s[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[4]\); - - \loop_all_sample.10.loop_all_chanel.6.sample_in_buf[25]\ : - DFN1E1C0 - port map(D => \sample_in_buf_461[25]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[25]\); - - \chanel_more.all_chanel.3.all_bit.13.sample_out_s2[94]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[76]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[94]\); - - \loop_all_sample.3.loop_all_chanel.1.sample_in_buf_RNO[122]\ : - MX2 - port map(A => \sample_in_buf[104]\, B => sample_1(3), S => - sample_val_delay, Y => \sample_in_buf_949[122]\); - - \loop_all_sample.2.loop_all_chanel.1.sample_in_buf_RNO[123]\ : - MX2 - port map(A => \sample_in_buf[105]\, B => sample_1(2), S => - sample_val_delay, Y => \sample_in_buf_1013[123]\); - - \loop_all_sample.3.loop_all_chanel.0.sample_in_buf_RNO[140]\ : - MX2 - port map(A => \sample_in_buf[122]\, B => sample_0(3), S => - sample_val_delay, Y => \sample_in_buf_957[140]\); - - \loop_all_sample.7.loop_all_chanel.6.sample_in_buf_RNO[28]\ : - MX2 - port map(A => \sample_in_buf[10]\, B => sample_6(7), S => - sample_val_delay, Y => \sample_in_buf_653[28]\); - - \loop_all_sample.8.loop_all_chanel.3.sample_in_buf_RNO[81]\ : - MX2 - port map(A => \sample_in_buf[63]\, B => sample_3(8), S => - sample_val_delay, Y => \sample_in_buf_613[81]\); - - \loop_all_sample.14.loop_all_chanel.5.sample_in_buf_RNO[39]\ : - MX2 - port map(A => \sample_in_buf[21]\, B => sample_5(14), S => - sample_val_delay, Y => \sample_in_buf_213[39]\); - - \loop_all_sample.12.loop_all_chanel.7.sample_in_buf_RNO[5]\ : - MX2 - port map(A => \sample_in_buf[131]\, B => sample_7(12), S - => sample_val_delay, Y => \sample_in_buf_325[5]\); - - \loop_all_sample.0.loop_all_chanel.2.sample_in_buf_RNO[107]\ : - MX2 - port map(A => \sample_in_buf[89]\, B => sample_2(0), S => - sample_val_delay, Y => \sample_in_buf_1133[107]\); - - \chanel_more.all_chanel.1.all_bit.15.sample_out_s2[128]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[110]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_126); - - \loop_all_sample.8.loop_all_chanel.1.sample_in_buf[117]\ : - DFN1E1C0 - port map(D => \sample_in_buf_629[117]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[117]\); - - \loop_all_sample.11.loop_all_chanel.1.sample_in_buf_RNO[114]\ : - MX2 - port map(A => \sample_in_buf[96]\, B => sample_1(11), S => - sample_val_delay, Y => \sample_in_buf_437[114]\); - - \loop_all_sample.5.loop_all_chanel.3.sample_in_buf_RNO[84]\ : - MX2 - port map(A => \sample_in_buf[66]\, B => sample_3(5), S => - sample_val_delay, Y => \sample_in_buf_805[84]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \chanel_more.all_chanel.6.all_bit.3.sample_out_s2[50]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[32]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[50]\); - - \loop_all_sample.2.loop_all_chanel.5.sample_in_buf[51]\ : - DFN1E1C0 - port map(D => \sample_in_buf_981[51]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[51]\); - - \chanel_more.all_chanel.7.all_bit.7.sample_out_s2[28]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[10]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[28]\); - - \chanel_more.all_chanel.2.all_bit.15.sample_out_s2[110]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[92]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[110]\); - - \loop_all_sample.8.loop_all_chanel.5.sample_in_buf[45]\ : - DFN1E1C0 - port map(D => \sample_in_buf_597[45]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[45]\); - - \loop_all_sample.9.loop_all_chanel.7.sample_in_buf_RNO[8]\ : - MX2 - port map(A => \sample_in_buf[134]\, B => sample_7(9), S => - sample_val_delay, Y => \sample_in_buf_517[8]\); - - \loop_all_sample.4.loop_all_chanel.6.sample_in_buf_RNO[31]\ : - MX2 - port map(A => \sample_in_buf[13]\, B => sample_6(4), S => - sample_val_delay, Y => \sample_in_buf_845[31]\); - - \loop_all_sample.8.loop_all_chanel.5.sample_in_buf_RNO[45]\ : - MX2 - port map(A => \sample_in_buf[27]\, B => sample_5(8), S => - sample_val_delay, Y => \sample_in_buf_597[45]\); - - \loop_all_sample.11.loop_all_chanel.1.sample_in_buf[114]\ : - DFN1E1C0 - port map(D => \sample_in_buf_437[114]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[114]\); - - \loop_all_sample.2.loop_all_chanel.0.sample_in_buf[141]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1021[141]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[141]\); - - \loop_all_sample.14.loop_all_chanel.4.sample_in_buf[57]\ : - DFN1E1C0 - port map(D => \sample_in_buf_221[57]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[57]\); - - IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW - port map(alu_ctrl(2) => \alu_ctrl[2]\, alu_ctrl(1) => - \alu_ctrl[1]\, alu_ctrl(0) => \alu_ctrl[0]\, S(8) => - \S[8]\, S_i_0(33) => \S_i_0[33]\, alu_sel_coeff(4) => - \alu_sel_coeff[4]\, alu_sel_coeff(3) => - \alu_sel_coeff[3]\, alu_sel_coeff(2) => - \alu_sel_coeff[2]\, alu_sel_coeff(1) => - \alu_sel_coeff[1]\, alu_sel_coeff(0) => - \alu_sel_coeff[0]\, alu_sel_coeff_0_2 => - \alu_sel_coeff_0[2]\, alu_sel_coeff_0_0 => - \alu_sel_coeff_0[0]\, waddr_previous(1) => - \waddr_previous[1]\, waddr_previous(0) => - \waddr_previous[0]\, sample_0(14) => sample_0(14), - sample_0(13) => sample_0(13), sample_0(12) => - sample_0(12), sample_0(11) => sample_0(11), sample_0(10) - => sample_0(10), sample_0(9) => sample_0(9), sample_0(8) - => sample_0(8), sample_0(7) => sample_0(7), sample_0(6) - => sample_0(6), sample_0(5) => sample_0(5), sample_0(4) - => sample_0(4), sample_0(3) => sample_0(3), sample_0(2) - => sample_0(2), sample_0(1) => sample_0(1), sample_0(0) - => sample_0(0), sample_in_buf(143) => - \sample_in_buf[143]\, sample_in_buf(142) => - \sample_in_buf[142]\, sample_in_buf(141) => - \sample_in_buf[141]\, sample_in_buf(140) => - \sample_in_buf[140]\, sample_in_buf(139) => - \sample_in_buf[139]\, sample_in_buf(138) => - \sample_in_buf[138]\, sample_in_buf(137) => - \sample_in_buf[137]\, sample_in_buf(136) => - \sample_in_buf[136]\, sample_in_buf(135) => - \sample_in_buf[135]\, sample_in_buf(134) => - \sample_in_buf[134]\, sample_in_buf(133) => - \sample_in_buf[133]\, sample_in_buf(132) => - \sample_in_buf[132]\, sample_in_buf(131) => - \sample_in_buf[131]\, sample_in_buf(130) => - \sample_in_buf[130]\, sample_in_buf(129) => - \sample_in_buf[129]\, ram_sel_Wdata(1) => - \ram_sel_Wdata[1]\, ram_sel_Wdata(0) => - \ram_sel_Wdata[0]\, sample_out_s_0 => \sample_out_s[0]\, - sample_out_s_1 => \sample_out_s[1]\, sample_out_s_3 => - \sample_out_s[3]\, sample_out_s_2 => \sample_out_s[2]\, - sample_out_s_10 => \sample_out_s[10]\, sample_out_s_15 - => \sample_out_s[15]\, sample_out_s_14 => - \sample_out_s[14]\, sample_out_s_13 => \sample_out_s[13]\, - sample_out_s_12 => \sample_out_s[12]\, sample_out_s_11 - => \sample_out_s[11]\, sample_out_s_9 => - \sample_out_s[9]\, sample_out_s_8 => \sample_out_s[8]\, - sample_out_s_7 => \sample_out_s[7]\, sample_out_s_6 => - \sample_out_s[6]\, sample_out_s_5 => \sample_out_s[5]\, - sample_out_s_4 => \sample_out_s[4]\, sample_in_s_1(17) - => \sample_in_s_1[17]\, in_sel_src(1) => \in_sel_src[1]\, - in_sel_src(0) => \in_sel_src[0]\, raddr_rst => raddr_rst, - raddr_add1 => raddr_add1, ram_write => ram_write, - IIR_CEL_CTRLR_v2_DATAFLOW_GND => IIR_CEL_CTRLR_v2_GND, - IIR_CEL_CTRLR_v2_DATAFLOW_VCC => IIR_CEL_CTRLR_v2_VCC, - ram_write_i => ram_write_i, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, sample_val_delay => sample_val_delay, - alu_sel_input => alu_sel_input); - - sample_out_val : DFN1C0 - port map(D => \sample_out_val_s2\, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_filter_v2_out_val); - - \loop_all_sample.8.loop_all_chanel.3.sample_in_buf[81]\ : - DFN1E1C0 - port map(D => \sample_in_buf_613[81]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[81]\); - - \loop_all_sample.17.loop_all_chanel.4.sample_in_buf_RNO[54]\ : - MX2 - port map(A => \sample_in_buf[36]\, B => sample_4(15), S => - sample_val_delay, Y => \sample_in_buf_29[54]\); - - \loop_all_sample.4.loop_all_chanel.3.sample_in_buf[85]\ : - DFN1E1C0 - port map(D => \sample_in_buf_869[85]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[85]\); - - \loop_all_sample.3.loop_all_chanel.4.sample_in_buf[68]\ : - DFN1E1C0 - port map(D => \sample_in_buf_925[68]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[68]\); - - \loop_all_sample.10.loop_all_chanel.7.sample_in_buf_RNO[7]\ : - MX2 - port map(A => \sample_in_buf[133]\, B => sample_7(10), S - => sample_val_delay, Y => \sample_in_buf_453[7]\); - - \loop_all_sample.10.loop_all_chanel.4.sample_in_buf[61]\ : - DFN1E1C0 - port map(D => \sample_in_buf_477[61]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[61]\); - - \loop_all_sample.10.loop_all_chanel.3.sample_in_buf[79]\ : - DFN1E1C0 - port map(D => \sample_in_buf_485[79]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[79]\); - - \chanel_more.all_chanel.4.all_bit.15.sample_out_s2[74]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[56]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[74]\); - - \chanel_more.all_chanel.2.all_bit.5.sample_out_s2[120]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[102]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[120]\); - - \chanel_more.all_chanel.2.all_bit.14.sample_out_s2[111]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[93]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[111]\); - - \chanel_more.all_chanel.2.all_bit.6.sample_out_s2[119]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[101]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[119]\); - - \loop_all_sample.11.loop_all_chanel.0.sample_in_buf[132]\ : - DFN1E1C0 - port map(D => \sample_in_buf_445[132]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[132]\); - - \chanel_more.all_chanel.7.all_bit.13.sample_out_s2[22]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[22]\); - - \loop_all_sample.6.loop_all_chanel.5.sample_in_buf_RNO[47]\ : - MX2 - port map(A => \sample_in_buf[29]\, B => sample_5(6), S => - sample_val_delay, Y => \sample_in_buf_725[47]\); - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf_RNO[126]\ : - MX2 - port map(A => \sample_in_buf[108]\, B => sample_0(15), S - => sample_val_delay, Y => \sample_in_buf_61[126]\); - - \loop_all_sample.6.loop_all_chanel.6.sample_in_buf[29]\ : - DFN1E1C0 - port map(D => \sample_in_buf_717[29]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[29]\); - - \loop_all_sample.1.loop_all_chanel.2.sample_in_buf_RNO[106]\ : - MX2 - port map(A => \sample_in_buf[88]\, B => sample_2(1), S => - sample_val_delay, Y => \sample_in_buf_1069[106]\); - - \loop_all_sample.0.loop_all_chanel.6.sample_in_buf[35]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1101[35]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[35]\); - - \chanel_more.all_chanel.3.all_bit.0.sample_out_s2[107]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[89]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[107]\); - - \loop_all_sample.4.loop_all_chanel.6.sample_in_buf[31]\ : - DFN1E1C0 - port map(D => \sample_in_buf_845[31]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[31]\); - - \chanel_more.all_chanel.4.all_bit.8.sample_out_s2[81]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[63]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[81]\); - - \chanel_more.all_chanel.6.all_bit.14.sample_out_s2[39]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[21]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[39]\); - - \loop_all_sample.12.loop_all_chanel.3.sample_in_buf_RNO[77]\ : - MX2 - port map(A => \sample_in_buf[59]\, B => sample_3(12), S => - sample_val_delay, Y => \sample_in_buf_357[77]\); - - \loop_all_sample.1.loop_all_chanel.5.sample_in_buf_RNO[52]\ : - MX2 - port map(A => \sample_in_buf[34]\, B => sample_5(1), S => - sample_val_delay, Y => \sample_in_buf_1045[52]\); - - \chanel_more.all_chanel.7.all_bit.14.sample_out_s2[21]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[21]\); - - \loop_all_sample.2.loop_all_chanel.2.sample_in_buf[105]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1005[105]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[105]\); - - \loop_all_sample.10.loop_all_chanel.6.sample_in_buf_RNO[25]\ : - MX2 - port map(A => \sample_in_buf[7]\, B => sample_6(10), S => - sample_val_delay, Y => \sample_in_buf_461[25]\); - - \chanel_more.all_chanel.3.all_bit.14.sample_out_s2[93]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[75]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[93]\); - - \loop_all_sample.2.loop_all_chanel.0.sample_in_buf_RNO[141]\ : - MX2 - port map(A => \sample_in_buf[123]\, B => sample_0(2), S => - sample_val_delay, Y => \sample_in_buf_1021[141]\); - - \loop_all_sample.3.loop_all_chanel.1.sample_in_buf[122]\ : - DFN1E1C0 - port map(D => \sample_in_buf_949[122]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[122]\); - - \chanel_more.all_chanel.4.all_bit.9.sample_out_s2[80]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[62]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[80]\); - - \chanel_more.all_chanel.4.all_bit.6.sample_out_s2[83]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[65]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[83]\); - - \loop_all_sample.13.loop_all_chanel.6.sample_in_buf_RNO[22]\ : - MX2 - port map(A => \sample_in_buf[4]\, B => sample_6(13), S => - sample_val_delay, Y => \sample_in_buf_269[22]\); - - \loop_all_sample.8.loop_all_chanel.6.sample_in_buf[27]\ : - DFN1E1C0 - port map(D => \sample_in_buf_589[27]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[27]\); - - \loop_all_sample.2.loop_all_chanel.3.sample_in_buf[87]\ : - DFN1E1C0 - port map(D => \sample_in_buf_997[87]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[87]\); - - \chanel_more.all_chanel.3.all_bit.15.sample_out_s2[92]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[74]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[92]\); - - \loop_all_sample.3.loop_all_chanel.3.sample_in_buf_RNO[86]\ : - MX2 - port map(A => \sample_in_buf[68]\, B => sample_3(3), S => - sample_val_delay, Y => \sample_in_buf_933[86]\); - - \chanel_more.all_chanel.6.all_bit.10.sample_out_s2[43]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[25]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[43]\); - - \loop_all_sample.6.loop_all_chanel.4.sample_in_buf_RNO[65]\ : - MX2 - port map(A => \sample_in_buf[47]\, B => sample_4(6), S => - sample_val_delay, Y => \sample_in_buf_733[65]\); - - \loop_all_sample.0.loop_all_chanel.0.sample_in_buf[143]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1149[143]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[143]\); - - \loop_all_sample.3.loop_all_chanel.0.sample_in_buf[140]\ : - DFN1E1C0 - port map(D => \sample_in_buf_957[140]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[140]\); - - \loop_all_sample.1.loop_all_chanel.4.sample_in_buf[70]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1053[70]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[70]\); - - \loop_all_sample.14.loop_all_chanel.2.sample_in_buf[93]\ : - DFN1E1C0 - port map(D => \sample_in_buf_237[93]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[93]\); - - \chanel_HIGH.14.sample_out_s2[3]\ : DFN1E1C0 - port map(D => \sample_out_s[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[3]\); - - \loop_all_sample.9.loop_all_chanel.1.sample_in_buf[116]\ : - DFN1E1C0 - port map(D => \sample_in_buf_565[116]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[116]\); - - \loop_all_sample.17.loop_all_chanel.2.sample_in_buf[90]\ : - DFN1E1C0 - port map(D => \sample_in_buf_45[90]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[90]\); - - \loop_all_sample.0.loop_all_chanel.2.sample_in_buf[107]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1133[107]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[107]\); - - \loop_all_sample.4.loop_all_chanel.4.sample_in_buf_RNO[67]\ : - MX2 - port map(A => \sample_in_buf[49]\, B => sample_4(4), S => - sample_val_delay, Y => \sample_in_buf_861[67]\); - - \loop_all_sample.8.loop_all_chanel.0.sample_in_buf[135]\ : - DFN1E1C0 - port map(D => \sample_in_buf_637[135]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[135]\); - - \chanel_more.all_chanel.5.all_bit.13.sample_out_s2[58]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[40]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[58]\); - - \chanel_HIGH.2.sample_out_s2[15]\ : DFN1E1C0 - port map(D => \sample_out_s[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[15]\); - - \chanel_more.all_chanel.4.all_bit.10.sample_out_s2[79]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[61]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[79]\); - - \loop_all_sample.12.loop_all_chanel.2.sample_in_buf_RNO[95]\ : - MX2 - port map(A => \sample_in_buf[77]\, B => sample_2(12), S => - sample_val_delay, Y => \sample_in_buf_365[95]\); - - \loop_all_sample.5.loop_all_chanel.5.sample_in_buf[48]\ : - DFN1E1C0 - port map(D => \sample_in_buf_789[48]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[48]\); - - \loop_all_sample.14.loop_all_chanel.7.sample_in_buf[3]\ : - DFN1E1C0 - port map(D => \sample_in_buf_197[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[3]\); - - \chanel_more.all_chanel.7.all_bit.10.sample_out_s2[25]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[7]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[25]\); - - \loop_all_sample.12.loop_all_chanel.3.sample_in_buf[77]\ : - DFN1E1C0 - port map(D => \sample_in_buf_357[77]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[77]\); - - \chanel_more.all_chanel.3.all_bit.3.sample_out_s2[104]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[86]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[104]\); - - sample_out_val_s2 : DFN1C0 - port map(D => sample_out_val_s, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sample_out_val_s2\); - - \chanel_more.all_chanel.7.all_bit.9.sample_out_s2[26]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[8]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[26]\); - - \loop_all_sample.5.loop_all_chanel.6.sample_in_buf_RNO[30]\ : - MX2 - port map(A => \sample_in_buf[12]\, B => sample_6(5), S => - sample_val_delay, Y => \sample_in_buf_781[30]\); - - \loop_all_sample.14.loop_all_chanel.5.sample_in_buf[39]\ : - DFN1E1C0 - port map(D => \sample_in_buf_213[39]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[39]\); - - \chanel_more.all_chanel.2.all_bit.0.sample_out_s2[125]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[107]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[125]\); - - \chanel_more.all_chanel.2.all_bit.2.sample_out_s2[123]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[105]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[123]\); - - \chanel_more.all_chanel.3.all_bit.7.sample_out_s2[100]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[82]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[100]\); - - \loop_all_sample.4.loop_all_chanel.7.sample_in_buf_RNO[13]\ : - MX2 - port map(A => \sample_in_buf[139]\, B => sample_7(4), S => - sample_val_delay, Y => \sample_in_buf_837[13]\); - - \loop_all_sample.14.loop_all_chanel.6.sample_in_buf_RNO[21]\ : - MX2 - port map(A => \sample_in_buf[3]\, B => sample_6(14), S => - sample_val_delay, Y => \sample_in_buf_205[21]\); - - \chanel_more.all_chanel.2.all_bit.13.sample_out_s2[112]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[94]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[112]\); - - \loop_all_sample.9.loop_all_chanel.6.sample_in_buf_RNO[26]\ : - MX2 - port map(A => \sample_in_buf[8]\, B => sample_6(9), S => - sample_val_delay, Y => \sample_in_buf_525[26]\); - - \loop_all_sample.9.loop_all_chanel.3.sample_in_buf[80]\ : - DFN1E1C0 - port map(D => \sample_in_buf_549[80]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[80]\); - - \loop_all_sample.7.loop_all_chanel.7.sample_in_buf[10]\ : - DFN1E1C0 - port map(D => \sample_in_buf_645[10]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[10]\); - - \loop_all_sample.12.loop_all_chanel.1.sample_in_buf_RNO[113]\ : - MX2 - port map(A => \sample_in_buf[95]\, B => sample_1(12), S => - sample_val_delay, Y => \sample_in_buf_373[113]\); - - \chanel_HIGH.1.sample_out_s2[16]\ : DFN1E1C0 - port map(D => \sample_out_s[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[16]\); - - \loop_all_sample.8.loop_all_chanel.4.sample_in_buf_RNO[63]\ : - MX2 - port map(A => \sample_in_buf[45]\, B => sample_4(8), S => - sample_val_delay, Y => \sample_in_buf_605[63]\); - - \loop_all_sample.6.loop_all_chanel.7.sample_in_buf_RNO[11]\ : - MX2 - port map(A => \sample_in_buf[137]\, B => sample_7(6), S => - sample_val_delay, Y => \sample_in_buf_709[11]\); - - \loop_all_sample.14.loop_all_chanel.0.sample_in_buf_RNO[129]\ : - MX2 - port map(A => \sample_in_buf[111]\, B => sample_0(14), S - => sample_val_delay, Y => \sample_in_buf_253[129]\); - - \chanel_HIGH.12.sample_out_s2[5]\ : DFN1E1C0 - port map(D => \sample_out_s[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[5]\); - - \loop_all_sample.3.loop_all_chanel.6.sample_in_buf[32]\ : - DFN1E1C0 - port map(D => \sample_in_buf_909[32]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[32]\); - - \loop_all_sample.17.loop_all_chanel.5.sample_in_buf_RNO[36]\ : - MX2 - port map(A => \sample_in_buf[18]\, B => sample_5(15), S => - sample_val_delay, Y => \sample_in_buf_21[36]\); - - \chanel_more.all_chanel.5.all_bit.8.sample_out_s2[63]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[45]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[63]\); - - \loop_all_sample.8.loop_all_chanel.7.sample_in_buf_RNO[9]\ : - MX2 - port map(A => \sample_in_buf[135]\, B => sample_7(8), S => - sample_val_delay, Y => \sample_in_buf_581[9]\); - - \loop_all_sample.5.loop_all_chanel.7.sample_in_buf_RNO[12]\ : - MX2 - port map(A => \sample_in_buf[138]\, B => sample_7(5), S => - sample_val_delay, Y => \sample_in_buf_773[12]\); - - \loop_all_sample.1.loop_all_chanel.4.sample_in_buf_RNO[70]\ : - MX2 - port map(A => \sample_in_buf[52]\, B => sample_4(1), S => - sample_val_delay, Y => \sample_in_buf_1053[70]\); - - \loop_all_sample.7.loop_all_chanel.6.sample_in_buf[28]\ : - DFN1E1C0 - port map(D => \sample_in_buf_653[28]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[28]\); - - \loop_all_sample.13.loop_all_chanel.3.sample_in_buf[76]\ : - DFN1E1C0 - port map(D => \sample_in_buf_293[76]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[76]\); - - \loop_all_sample.17.loop_all_chanel.6.sample_in_buf[18]\ : - DFN1E1C0 - port map(D => \sample_in_buf_13[18]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[18]\); - - \loop_all_sample.0.loop_all_chanel.3.sample_in_buf_RNO[89]\ : - MX2 - port map(A => \sample_in_buf[71]\, B => sample_3(0), S => - sample_val_delay, Y => \sample_in_buf_1125[89]\); - - \chanel_more.all_chanel.2.all_bit.11.sample_out_s2[114]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[96]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[114]\); - - \loop_all_sample.12.loop_all_chanel.1.sample_in_buf[113]\ : - DFN1E1C0 - port map(D => \sample_in_buf_373[113]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[113]\); - - \loop_all_sample.0.loop_all_chanel.4.sample_in_buf_RNO[71]\ : - MX2 - port map(A => \sample_in_buf[53]\, B => sample_4(0), S => - sample_val_delay, Y => \sample_in_buf_1117[71]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \loop_all_sample.13.loop_all_chanel.1.sample_in_buf[112]\ : - DFN1E1C0 - port map(D => \sample_in_buf_309[112]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[112]\); - - \chanel_more.all_chanel.6.all_bit.9.sample_out_s2[44]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[26]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[44]\); - - \chanel_more.all_chanel.2.all_bit.1.sample_out_s2[124]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[106]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[124]\); - - \loop_all_sample.12.loop_all_chanel.4.sample_in_buf[59]\ : - DFN1E1C0 - port map(D => \sample_in_buf_349[59]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[59]\); - - \loop_all_sample.8.loop_all_chanel.7.sample_in_buf[9]\ : - DFN1E1C0 - port map(D => \sample_in_buf_581[9]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[9]\); - - \chanel_HIGH.5.sample_out_s2[12]\ : DFN1E1C0 - port map(D => \sample_out_s[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[12]\); - - \loop_all_sample.5.loop_all_chanel.0.sample_in_buf[138]\ : - DFN1E1C0 - port map(D => \sample_in_buf_829[138]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[138]\); - - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf_RNIF75G[126]\ : - MX2 - port map(A => \sample_in_buf[128]\, B => sample_0(15), S - => sample_val_delay, Y => \sample_in_s_1[17]\); - - \loop_all_sample.3.loop_all_chanel.5.sample_in_buf[50]\ : - DFN1E1C0 - port map(D => \sample_in_buf_917[50]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[50]\); - - \loop_all_sample.0.loop_all_chanel.1.sample_in_buf[125]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1141[125]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[125]\); - - \loop_all_sample.9.loop_all_chanel.2.sample_in_buf[98]\ : - DFN1E1C0 - port map(D => \sample_in_buf_557[98]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[98]\); - - \loop_all_sample.6.loop_all_chanel.0.sample_in_buf[137]\ : - DFN1E1C0 - port map(D => \sample_in_buf_765[137]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[137]\); - - \loop_all_sample.3.loop_all_chanel.5.sample_in_buf_RNO[50]\ : - MX2 - port map(A => \sample_in_buf[32]\, B => sample_5(3), S => - sample_val_delay, Y => \sample_in_buf_917[50]\); - - \loop_all_sample.1.loop_all_chanel.1.sample_in_buf[124]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1077[124]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[124]\); - - \loop_all_sample.14.loop_all_chanel.3.sample_in_buf_RNO[75]\ : - MX2 - port map(A => \sample_in_buf[57]\, B => sample_3(14), S => - sample_val_delay, Y => \sample_in_buf_229[75]\); - - \chanel_HIGH.4.sample_out_s2[13]\ : DFN1E1C0 - port map(D => \sample_out_s[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[13]\); - - \chanel_HIGH.0.sample_out_s2[17]\ : DFN1E1C0 - port map(D => \sample_out_s[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[17]\); - - \loop_all_sample.7.loop_all_chanel.4.sample_in_buf[64]\ : - DFN1E1C0 - port map(D => \sample_in_buf_669[64]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[64]\); - - \chanel_more.all_chanel.1.all_bit.1.sample_out_s2[142]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[124]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_140); - - \loop_all_sample.6.loop_all_chanel.6.sample_in_buf_RNO[29]\ : - MX2 - port map(A => \sample_in_buf[11]\, B => sample_6(6), S => - sample_val_delay, Y => \sample_in_buf_717[29]\); - - \loop_all_sample.14.loop_all_chanel.4.sample_in_buf_RNO[57]\ : - MX2 - port map(A => \sample_in_buf[39]\, B => sample_4(14), S => - sample_val_delay, Y => \sample_in_buf_221[57]\); - - \loop_all_sample.12.loop_all_chanel.6.sample_in_buf_RNO[23]\ : - MX2 - port map(A => \sample_in_buf[5]\, B => sample_6(12), S => - sample_val_delay, Y => \sample_in_buf_333[23]\); - - \chanel_more.all_chanel.5.all_bit.4.sample_out_s2[67]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[49]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[67]\); - - \chanel_more.all_chanel.3.all_bit.9.sample_out_s2[98]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[80]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[98]\); - - \loop_all_sample.7.loop_all_chanel.5.sample_in_buf[46]\ : - DFN1E1C0 - port map(D => \sample_in_buf_661[46]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[46]\); - - \loop_all_sample.9.loop_all_chanel.0.sample_in_buf[134]\ : - DFN1E1C0 - port map(D => \sample_in_buf_573[134]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[134]\); - - \chanel_more.all_chanel.4.all_bit.3.sample_out_s2[86]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[68]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[86]\); - - \loop_all_sample.5.loop_all_chanel.7.sample_in_buf[12]\ : - DFN1E1C0 - port map(D => \sample_in_buf_773[12]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[12]\); - - \loop_all_sample.4.loop_all_chanel.7.sample_in_buf[13]\ : - DFN1E1C0 - port map(D => \sample_in_buf_837[13]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[13]\); - - \loop_all_sample.2.loop_all_chanel.4.sample_in_buf[69]\ : - DFN1E1C0 - port map(D => \sample_in_buf_989[69]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[69]\); - - \loop_all_sample.12.loop_all_chanel.0.sample_in_buf[131]\ : - DFN1E1C0 - port map(D => \sample_in_buf_381[131]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[131]\); - - \loop_all_sample.4.loop_all_chanel.5.sample_in_buf[49]\ : - DFN1E1C0 - port map(D => \sample_in_buf_853[49]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[49]\); - - \loop_all_sample.11.loop_all_chanel.6.sample_in_buf[24]\ : - DFN1E1C0 - port map(D => \sample_in_buf_397[24]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[24]\); - - \loop_all_sample.3.loop_all_chanel.7.sample_in_buf_RNO[14]\ : - MX2 - port map(A => \sample_in_buf[140]\, B => sample_7(3), S => - sample_val_delay, Y => \sample_in_buf_901[14]\); - - \loop_all_sample.1.loop_all_chanel.0.sample_in_buf[142]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1085[142]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[142]\); - - \loop_all_sample.8.loop_all_chanel.4.sample_in_buf[63]\ : - DFN1E1C0 - port map(D => \sample_in_buf_605[63]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[63]\); - - \loop_all_sample.10.loop_all_chanel.1.sample_in_buf[115]\ : - DFN1E1C0 - port map(D => \sample_in_buf_501[115]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[115]\); - - \loop_all_sample.0.loop_all_chanel.4.sample_in_buf[71]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1117[71]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[71]\); - - \loop_all_sample.4.loop_all_chanel.3.sample_in_buf_RNO[85]\ : - MX2 - port map(A => \sample_in_buf[67]\, B => sample_3(4), S => - sample_val_delay, Y => \sample_in_buf_869[85]\); - - \loop_all_sample.13.loop_all_chanel.3.sample_in_buf_RNO[76]\ : - MX2 - port map(A => \sample_in_buf[58]\, B => sample_3(13), S => - sample_val_delay, Y => \sample_in_buf_293[76]\); - - \loop_all_sample.14.loop_all_chanel.1.sample_in_buf[111]\ : - DFN1E1C0 - port map(D => \sample_in_buf_245[111]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[111]\); - - \chanel_more.all_chanel.3.all_bit.5.sample_out_s2[102]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[84]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[102]\); - - \loop_all_sample.2.loop_all_chanel.7.sample_in_buf[15]\ : - DFN1E1C0 - port map(D => \sample_in_buf_965[15]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[15]\); - - \loop_all_sample.14.loop_all_chanel.7.sample_in_buf_RNO[3]\ : - MX2 - port map(A => \sample_in_buf[129]\, B => sample_7(14), S - => sample_val_delay, Y => \sample_in_buf_197[3]\); - - \chanel_more.all_chanel.7.all_bit.4.sample_out_s2[31]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[13]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[31]\); - - \loop_all_sample.7.loop_all_chanel.2.sample_in_buf_RNO[100]\ : - MX2 - port map(A => \sample_in_buf[82]\, B => sample_2(7), S => - sample_val_delay, Y => \sample_in_buf_685[100]\); - - \loop_all_sample.8.loop_all_chanel.0.sample_in_buf_RNO[135]\ : - MX2 - port map(A => \sample_in_buf[117]\, B => sample_0(8), S => - sample_val_delay, Y => \sample_in_buf_637[135]\); - - \loop_all_sample.7.loop_all_chanel.5.sample_in_buf_RNO[46]\ : - MX2 - port map(A => \sample_in_buf[28]\, B => sample_5(7), S => - sample_val_delay, Y => \sample_in_buf_661[46]\); - - \loop_all_sample.7.loop_all_chanel.1.sample_in_buf[118]\ : - DFN1E1C0 - port map(D => \sample_in_buf_693[118]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[118]\); - - \chanel_more.all_chanel.5.all_bit.3.sample_out_s2[68]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[50]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[68]\); - - \loop_all_sample.11.loop_all_chanel.5.sample_in_buf_RNO[42]\ : - MX2 - port map(A => \sample_in_buf[24]\, B => sample_5(11), S => - sample_val_delay, Y => \sample_in_buf_405[42]\); - - \chanel_more.all_chanel.3.all_bit.12.sample_out_s2[95]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[77]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[95]\); - - \loop_all_sample.1.loop_all_chanel.0.sample_in_buf_RNO[142]\ : - MX2 - port map(A => \sample_in_buf[124]\, B => sample_0(1), S => - sample_val_delay, Y => \sample_in_buf_1085[142]\); - - \loop_all_sample.12.loop_all_chanel.6.sample_in_buf[23]\ : - DFN1E1C0 - port map(D => \sample_in_buf_333[23]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[23]\); - - \chanel_more.all_chanel.5.all_bit.15.sample_out_s2[56]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[38]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[56]\); - - \loop_all_sample.4.loop_all_chanel.0.sample_in_buf[139]\ : - DFN1E1C0 - port map(D => \sample_in_buf_893[139]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[139]\); - - \chanel_more.all_chanel.6.all_bit.5.sample_out_s2[48]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[30]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[48]\); - - \loop_all_sample.4.loop_all_chanel.4.sample_in_buf[67]\ : - DFN1E1C0 - port map(D => \sample_in_buf_861[67]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[67]\); - - \loop_all_sample.12.loop_all_chanel.0.sample_in_buf_RNO[131]\ : - MX2 - port map(A => \sample_in_buf[113]\, B => sample_0(12), S - => sample_val_delay, Y => \sample_in_buf_381[131]\); - - \chanel_more.all_chanel.4.all_bit.2.sample_out_s2[87]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[69]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[87]\); - - \loop_all_sample.5.loop_all_chanel.0.sample_in_buf_RNO[138]\ : - MX2 - port map(A => \sample_in_buf[120]\, B => sample_0(5), S => - sample_val_delay, Y => \sample_in_buf_829[138]\); - - \chanel_more.all_chanel.7.all_bit.5.sample_out_s2[30]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[12]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[30]\); - - \chanel_more.all_chanel.5.all_bit.14.sample_out_s2[57]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[39]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[57]\); - - \loop_all_sample.9.loop_all_chanel.5.sample_in_buf_RNO[44]\ : - MX2 - port map(A => \sample_in_buf[26]\, B => sample_5(9), S => - sample_val_delay, Y => \sample_in_buf_533[44]\); - - \chanel_more.all_chanel.3.all_bit.2.sample_out_s2[105]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[87]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[105]\); - - \loop_all_sample.5.loop_all_chanel.2.sample_in_buf[102]\ : - DFN1E1C0 - port map(D => \sample_in_buf_813[102]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[102]\); - - \chanel_HIGH.10.sample_out_s2[7]\ : DFN1E1C0 - port map(D => \sample_out_s[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[7]\); - - \chanel_more.all_chanel.6.all_bit.13.sample_out_s2[40]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[22]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[40]\); - - \chanel_more.all_chanel.5.all_bit.12.sample_out_s2[59]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[41]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[59]\); - - \loop_all_sample.14.loop_all_chanel.3.sample_in_buf[75]\ : - DFN1E1C0 - port map(D => \sample_in_buf_229[75]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[75]\); - - \loop_all_sample.14.loop_all_chanel.2.sample_in_buf_RNO[93]\ : - MX2 - port map(A => \sample_in_buf[75]\, B => sample_2(14), S => - sample_val_delay, Y => \sample_in_buf_237[93]\); - - \loop_all_sample.10.loop_all_chanel.5.sample_in_buf_RNO[43]\ : - MX2 - port map(A => \sample_in_buf[25]\, B => sample_5(10), S => - sample_val_delay, Y => \sample_in_buf_469[43]\); - - \loop_all_sample.0.loop_all_chanel.7.sample_in_buf[17]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1093[17]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[17]\); - - \loop_all_sample.6.loop_all_chanel.3.sample_in_buf_RNO[83]\ : - MX2 - port map(A => \sample_in_buf[65]\, B => sample_3(6), S => - sample_val_delay, Y => \sample_in_buf_741[83]\); - - \loop_all_sample.5.loop_all_chanel.6.sample_in_buf[30]\ : - DFN1E1C0 - port map(D => \sample_in_buf_781[30]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[30]\); - - \loop_all_sample.13.loop_all_chanel.0.sample_in_buf[130]\ : - DFN1E1C0 - port map(D => \sample_in_buf_317[130]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[130]\); - - \loop_all_sample.10.loop_all_chanel.7.sample_in_buf[7]\ : - DFN1E1C0 - port map(D => \sample_in_buf_453[7]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[7]\); - - \loop_all_sample.0.loop_all_chanel.0.sample_in_buf_RNO[143]\ : - MX2 - port map(A => \sample_in_buf[125]\, B => sample_0(0), S => - sample_val_delay, Y => \sample_in_buf_1149[143]\); - - \chanel_more.all_chanel.4.all_bit.12.sample_out_s2[77]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[59]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[77]\); - - \loop_all_sample.2.loop_all_chanel.6.sample_in_buf_RNO[33]\ : - MX2 - port map(A => \sample_in_buf[15]\, B => sample_6(2), S => - sample_val_delay, Y => \sample_in_buf_973[33]\); - - \chanel_more.all_chanel.5.all_bit.5.sample_out_s2[66]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[48]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[66]\); - - \loop_all_sample.6.loop_all_chanel.1.sample_in_buf[119]\ : - DFN1E1C0 - port map(D => \sample_in_buf_757[119]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[119]\); - - \loop_all_sample.0.loop_all_chanel.5.sample_in_buf[53]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1109[53]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[53]\); - - \loop_all_sample.17.loop_all_chanel.6.sample_in_buf_RNO[18]\ : - MX2 - port map(A => \sample_in_buf[0]\, B => sample_6(15), S => - sample_val_delay, Y => \sample_in_buf_13[18]\); - - \chanel_more.all_chanel.6.all_bit.4.sample_out_s2[49]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[31]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[49]\); - - \chanel_more.all_chanel.5.all_bit.1.sample_out_s2[70]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[52]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[70]\); - - \loop_all_sample.17.loop_all_chanel.7.sample_in_buf[0]\ : - DFN1E1C0 - port map(D => \sample_in_buf_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[0]\); - - \chanel_more.all_chanel.1.all_bit.14.sample_out_s2[129]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[111]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_127); - - \loop_all_sample.5.loop_all_chanel.1.sample_in_buf_RNO[120]\ : - MX2 - port map(A => \sample_in_buf[102]\, B => sample_1(5), S => - sample_val_delay, Y => \sample_in_buf_821[120]\); - - \loop_all_sample.0.loop_all_chanel.7.sample_in_buf_RNO[17]\ : - MX2 - port map(A => \sample_in_buf[143]\, B => sample_7(0), S => - sample_val_delay, Y => \sample_in_buf_1093[17]\); - - \loop_all_sample.12.loop_all_chanel.7.sample_in_buf[5]\ : - DFN1E1C0 - port map(D => \sample_in_buf_325[5]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[5]\); - - \chanel_more.all_chanel.3.all_bit.8.sample_out_s2[99]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[81]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[99]\); - - \chanel_more.all_chanel.4.all_bit.7.sample_out_s2[82]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[64]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[82]\); - - \loop_all_sample.10.loop_all_chanel.0.sample_in_buf[133]\ : - DFN1E1C0 - port map(D => \sample_in_buf_509[133]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[133]\); - - \loop_all_sample.3.loop_all_chanel.7.sample_in_buf[14]\ : - DFN1E1C0 - port map(D => \sample_in_buf_901[14]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[14]\); - - \chanel_HIGH.8.sample_out_s2[9]\ : DFN1E1C0 - port map(D => \sample_out_s[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[9]\); - - \chanel_more.all_chanel.5.all_bit.2.sample_out_s2[69]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[51]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[69]\); - - \chanel_more.all_chanel.1.all_bit.0.sample_out_s2[143]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[125]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_141); - - \chanel_more.all_chanel.1.all_bit.12.sample_out_s2[131]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[113]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_129); - - \chanel_HIGH.3.sample_out_s2[14]\ : DFN1E1C0 - port map(D => \sample_out_s[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[14]\); - - \chanel_more.all_chanel.7.all_bit.12.sample_out_s2[23]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[5]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[23]\); - - \loop_all_sample.8.loop_all_chanel.1.sample_in_buf_RNO[117]\ : - MX2 - port map(A => \sample_in_buf[99]\, B => sample_1(8), S => - sample_val_delay, Y => \sample_in_buf_629[117]\); - - \loop_all_sample.10.loop_all_chanel.0.sample_in_buf_RNO[133]\ : - MX2 - port map(A => \sample_in_buf[115]\, B => sample_0(10), S - => sample_val_delay, Y => \sample_in_buf_509[133]\); - - \loop_all_sample.11.loop_all_chanel.3.sample_in_buf[78]\ : - DFN1E1C0 - port map(D => \sample_in_buf_421[78]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[78]\); - - \chanel_HIGH.11.sample_out_s2[6]\ : DFN1E1C0 - port map(D => \sample_out_s[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[6]\); - - \loop_all_sample.10.loop_all_chanel.3.sample_in_buf_RNO[79]\ : - MX2 - port map(A => \sample_in_buf[61]\, B => sample_3(10), S => - sample_val_delay, Y => \sample_in_buf_485[79]\); - - \chanel_more.all_chanel.1.all_bit.11.sample_out_s2[132]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[114]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_130); - - \chanel_more.all_chanel.1.all_bit.10.sample_out_s2[133]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[115]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_131); - - \loop_all_sample.13.loop_all_chanel.1.sample_in_buf_RNO[112]\ : - MX2 - port map(A => \sample_in_buf[94]\, B => sample_1(13), S => - sample_val_delay, Y => \sample_in_buf_309[112]\); - - \loop_all_sample.6.loop_all_chanel.3.sample_in_buf[83]\ : - DFN1E1C0 - port map(D => \sample_in_buf_741[83]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[83]\); - - \loop_all_sample.2.loop_all_chanel.3.sample_in_buf_RNO[87]\ : - MX2 - port map(A => \sample_in_buf[69]\, B => sample_3(2), S => - sample_val_delay, Y => \sample_in_buf_997[87]\); - - \loop_all_sample.1.loop_all_chanel.5.sample_in_buf[52]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1045[52]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[52]\); - - \chanel_more.all_chanel.7.all_bit.0.sample_out_s2[35]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[17]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[35]\); - - \chanel_more.all_chanel.4.all_bit.14.sample_out_s2[75]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[57]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[75]\); - - \chanel_more.all_chanel.2.all_bit.4.sample_out_s2[121]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[103]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[121]\); - - \chanel_more.all_chanel.2.all_bit.12.sample_out_s2[113]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[95]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[113]\); - - \chanel_more.all_chanel.1.all_bit.7.sample_out_s2[136]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[118]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_134); - - \chanel_more.all_chanel.1.all_bit.2.sample_out_s2[141]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[123]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_139); - - \loop_all_sample.6.loop_all_chanel.2.sample_in_buf_RNO[101]\ : - MX2 - port map(A => \sample_in_buf[83]\, B => sample_2(6), S => - sample_val_delay, Y => \sample_in_buf_749[101]\); - - \chanel_more.all_chanel.5.all_bit.11.sample_out_s2[60]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[42]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[60]\); - - \loop_all_sample.1.loop_all_chanel.1.sample_in_buf_RNO[124]\ : - MX2 - port map(A => \sample_in_buf[106]\, B => sample_1(1), S => - sample_val_delay, Y => \sample_in_buf_1077[124]\); - - IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL - port map(alu_ctrl(2) => \alu_ctrl[2]\, alu_ctrl(1) => - \alu_ctrl[1]\, alu_ctrl(0) => \alu_ctrl[0]\, - ram_sel_Wdata(1) => \ram_sel_Wdata[1]\, ram_sel_Wdata(0) - => \ram_sel_Wdata[0]\, waddr_previous(1) => - \waddr_previous[1]\, waddr_previous(0) => - \waddr_previous[0]\, in_sel_src(1) => \in_sel_src[1]\, - in_sel_src(0) => \in_sel_src[0]\, S_i_0(33) => - \S_i_0[33]\, S(8) => \S[8]\, alu_sel_coeff(4) => - \alu_sel_coeff[4]\, alu_sel_coeff(3) => - \alu_sel_coeff[3]\, alu_sel_coeff(2) => - \alu_sel_coeff[2]\, alu_sel_coeff(1) => - \alu_sel_coeff[1]\, alu_sel_coeff(0) => - \alu_sel_coeff[0]\, alu_sel_coeff_0_2 => - \alu_sel_coeff_0[2]\, alu_sel_coeff_0_0 => - \alu_sel_coeff_0[0]\, sample_out_rot_s => - sample_out_rot_s, sample_out_val_s => sample_out_val_s, - raddr_rst => raddr_rst, alu_sel_input => alu_sel_input, - raddr_add1 => raddr_add1, sample_val_delay => - sample_val_delay, ram_write => ram_write, ram_write_i => - ram_write_i, un1_sample_in_rotate => un1_sample_in_rotate, - sample_out_rot_s_0 => sample_out_rot_s_0, - sample_out_rot_s_1 => sample_out_rot_s_1, - sample_out_rot_s_2 => sample_out_rot_s_2, - sample_out_rot_s_3 => sample_out_rot_s_3, - sample_out_rot_s_4 => sample_out_rot_s_4, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \loop_all_sample.7.loop_all_chanel.3.sample_in_buf_RNO[82]\ : - MX2 - port map(A => \sample_in_buf[64]\, B => sample_3(7), S => - sample_val_delay, Y => \sample_in_buf_677[82]\); - - \chanel_more.all_chanel.7.all_bit.8.sample_out_s2[27]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[9]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[27]\); - - \chanel_more.all_chanel.6.all_bit.7.sample_out_s2[46]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[28]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[46]\); - - \loop_all_sample.7.loop_all_chanel.3.sample_in_buf[82]\ : - DFN1E1C0 - port map(D => \sample_in_buf_677[82]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[82]\); - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf[126]\ : - DFN1E1C0 - port map(D => \sample_in_buf_61[126]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[128]\); - - \loop_all_sample.11.loop_all_chanel.4.sample_in_buf[60]\ : - DFN1E1C0 - port map(D => \sample_in_buf_413[60]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[60]\); - - \loop_all_sample.3.loop_all_chanel.6.sample_in_buf_RNO[32]\ : - MX2 - port map(A => \sample_in_buf[14]\, B => sample_6(3), S => - sample_val_delay, Y => \sample_in_buf_909[32]\); - - \loop_all_sample.17.loop_all_chanel.1.sample_in_buf_RNO[108]\ : - MX2 - port map(A => \sample_in_buf[90]\, B => sample_1(15), S => - sample_val_delay, Y => \sample_in_buf_53[108]\); - - \loop_all_sample.8.loop_all_chanel.6.sample_in_buf_RNO[27]\ : - MX2 - port map(A => \sample_in_buf[9]\, B => sample_6(8), S => - sample_val_delay, Y => \sample_in_buf_589[27]\); - - \loop_all_sample.5.loop_all_chanel.4.sample_in_buf[66]\ : - DFN1E1C0 - port map(D => \sample_in_buf_797[66]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[66]\); - - \loop_all_sample.14.loop_all_chanel.1.sample_in_buf_RNO[111]\ : - MX2 - port map(A => \sample_in_buf[93]\, B => sample_1(14), S => - sample_val_delay, Y => \sample_in_buf_245[111]\); - - \chanel_more.all_chanel.2.all_bit.8.sample_out_s2[117]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[99]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[117]\); - - \chanel_more.all_chanel.7.all_bit.11.sample_out_s2[24]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[6]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[24]\); - - \loop_all_sample.8.loop_all_chanel.2.sample_in_buf_RNO[99]\ : - MX2 - port map(A => \sample_in_buf[81]\, B => sample_2(8), S => - sample_val_delay, Y => \sample_in_buf_621[99]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_6_16_256 is - - port( sample_f1 : in std_logic_vector(111 downto 80); - sample_f1_wdata_95 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_0 : in std_logic; - sample_f3_wdata : out std_logic_vector(95 downto 0); - sample_f1_val : in std_logic; - HCLK_c : in std_logic; - sample_f3_val : out std_logic; - HRESETn_c : in std_logic; - sample_f1_val_0 : in std_logic - ); - -end Downsampling_6_16_256; - -architecture DEF_ARCH of Downsampling_6_16_256 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un2_sample_in_val_0, un2_sample_in_val_23, - un2_sample_in_val_22, un2_sample_in_val_24, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1, - sample_out_0_sqmuxa_0, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un2_sample_in_val_15, - un2_sample_in_val_14, un2_sample_in_val_20, - un2_sample_in_val_9, un2_sample_in_val_8, - un2_sample_in_val_19, un2_sample_in_val_5, - un2_sample_in_val_4, un2_sample_in_val_17, - un2_sample_in_val_13, \counter[24]_net_1\, - un2_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un2_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un2_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un2_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un2_sample_in_val, - sample_out_0_sqmuxa, \counter_4[8]\, I_45_2, - \counter_4[9]\, I_52_2, \counter_4[10]\, I_56_2, - \counter_4[11]\, I_66_2, \counter_4[12]\, I_73_2, - \counter_4[13]\, I_77_2, \counter_4[14]\, I_84_2, - \counter_4[15]\, I_91_2, \counter_4[16]\, I_98_2, - \counter_4[17]\, I_105_2, \counter_4[18]\, I_115_2, - \counter_4[19]\, I_122_2, \counter_4[20]\, I_129_2, - \counter_4[21]\, I_136_2, \counter_4[22]\, I_143_2, - \counter_4[23]\, I_156_2, \counter_4[24]\, I_166_2, - \counter_4[25]\, I_173_2, \counter_4[26]\, I_186_2, - \counter_4[27]\, I_196_2, sample_out_val_4, I_4_2, I_5_2, - I_9_2, I_13_2, I_20_2, I_24_2, I_31_3, I_38_2, N_4, - \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[19]_net_1\); - - \counter_RNI8DTE[12]\ : NOR3C - port map(A => un2_sample_in_val_9, B => un2_sample_in_val_8, - C => un2_sample_in_val_19, Y => un2_sample_in_val_23); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f1_wdata_73, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(73)); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f1_wdata_75, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(75)); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f1_wdata_82, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(82)); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f1_wdata_94, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(94)); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f1_wdata_76, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(76)); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f1(93), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(34)); - - \sample_out[66]\ : DFN1E1 - port map(D => sample_f1(98), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(29)); - - \sample_out[73]\ : DFN1E1 - port map(D => sample_f1(105), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(22)); - - \sample_out[79]\ : DFN1E1 - port map(D => sample_f1(111), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(16)); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f1_wdata_57, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(57)); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f1_wdata_0, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(0)); - - \counter_RNO[11]\ : NOR2B - port map(A => I_66_2, B => un2_sample_in_val_0, Y => - \counter_4[11]\); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f1_wdata_61, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(61)); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_2); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_2); - - \counter_RNO[15]\ : NOR2B - port map(A => I_91_2, B => un2_sample_in_val_0, Y => - \counter_4[15]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f1(83), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(44)); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f1(88), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(39)); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f1_wdata_95, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(95)); - - \counter[6]\ : DFN1E1C0 - port map(D => I_31_3, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_2); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f1_wdata_14, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(14)); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f1_wdata_9, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(9)); - - \counter[3]\ : DFN1E1C0 - port map(D => I_13_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_2, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f1_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_2); - - \counter_RNO[8]\ : NOR2B - port map(A => I_45_2, B => un2_sample_in_val_0, Y => - \counter_4[8]\); - - \counter_RNO[13]\ : NOR2B - port map(A => I_77_2, B => un2_sample_in_val_0, Y => - \counter_4[13]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_2); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f1_wdata_83, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(83)); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f1_wdata_85, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(85)); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f1_wdata_50, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(50)); - - \counter_RNO[12]\ : NOR2B - port map(A => I_73_2, B => un2_sample_in_val_0, Y => - \counter_4[12]\); - - \sample_out[72]\ : DFN1E1 - port map(D => sample_f1(104), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(23)); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f1_wdata_62, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(62)); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f1_wdata_56, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(56)); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[17]_net_1\); - - \sample_out[70]\ : DFN1E1 - port map(D => sample_f1(102), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(25)); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => I_20_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_2); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f1_wdata_90, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(90)); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f1_wdata_48, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(48)); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \counter_RNIPKE[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un2_sample_in_val_5); - - \sample_out[65]\ : DFN1E1 - port map(D => sample_f1(97), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(30)); - - \counter_RNIBJN3[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un2_sample_in_val_3); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f1_wdata_74, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(74)); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f1_wdata_69, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(69)); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f1_wdata_93, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(93)); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[27]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[27]_net_1\); - - \counter_RNI2SB8[10]\ : NOR3C - port map(A => un2_sample_in_val_5, B => un2_sample_in_val_4, - C => un2_sample_in_val_17, Y => un2_sample_in_val_22); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \sample_out[67]\ : DFN1E1 - port map(D => sample_f1(99), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(28)); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f1_wdata_1, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(1)); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_2); - - \counter_RNO[17]\ : NOR2B - port map(A => I_105_2, B => un2_sample_in_val, Y => - \counter_4[17]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f1(87), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(40)); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \counter_RNIH507[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un2_sample_in_val_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_2); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f1_wdata_63, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(63)); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_2); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f1(89), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(38)); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f1_wdata_65, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(65)); - - \counter_RNO[14]\ : NOR2B - port map(A => I_84_2, B => un2_sample_in_val_0, Y => - \counter_4[14]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f1_wdata_10, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(10)); - - \counter_RNIO507[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un2_sample_in_val_8); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_2, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f1_val, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => I_186_2, B => un2_sample_in_val, Y => - \counter_4[26]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f1_wdata_91, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(91)); - - \counter_RNI0MBF1_2[10]\ : NOR3B - port map(A => sample_f1_val_0, B => HRESETn_c, C => - un2_sample_in_val_0, Y => sample_out_0_sqmuxa_1); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[25]_net_1\); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_4, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f3_val); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f1_wdata_8, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(8)); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_2); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_2); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f1(80), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(47)); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_2); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f1_wdata_2, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(2)); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f1_wdata_84, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(84)); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f1_wdata_79, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(79)); - - \counter[5]\ : DFN1E1C0 - port map(D => I_24_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f1_wdata_51, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(51)); - - \sample_out[71]\ : DFN1E1 - port map(D => sample_f1(103), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(24)); - - \sample_out[76]\ : DFN1E1 - port map(D => sample_f1(108), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(19)); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : NOR2B - port map(A => I_56_2, B => un2_sample_in_val_0, Y => - \counter_4[10]\); - - \counter_RNIRSE[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un2_sample_in_val_1); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_2); - - \counter_RNO[21]\ : NOR2B - port map(A => I_136_2, B => un2_sample_in_val, Y => - \counter_4[21]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_2); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[68]\ : DFN1E1 - port map(D => sample_f1(100), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(27)); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f1_wdata_70, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(70)); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_2); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => I_173_2, B => un2_sample_in_val, Y => - \counter_4[25]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - \sample_out[64]\ : DFN1E1 - port map(D => sample_f1(96), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(31)); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_3); - - \counter_RNIH1T[12]\ : NOR3A - port map(A => un2_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un2_sample_in_val_19); - - \counter_RNI0G54[20]\ : NOR3A - port map(A => un2_sample_in_val_3, B => \counter[23]_net_1\, - C => \counter[20]_net_1\, Y => un2_sample_in_val_15); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_2); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f1_wdata_68, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(68)); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - \counter_RNI6RM3[10]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un2_sample_in_val_4); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_2); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f1(90), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(37)); - - \counter_RNI7FN3[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un2_sample_in_val_7); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[26]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_2); - - \counter_RNO[23]\ : NOR2B - port map(A => I_156_2, B => un2_sample_in_val, Y => - \counter_4[23]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f1(86), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(41)); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f1_wdata_52, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(52)); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f1(81), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(46)); - - \counter_RNI0MBF1_0[10]\ : NOR3B - port map(A => sample_f1_val_0, B => HRESETn_c, C => - un2_sample_in_val_0, Y => sample_out_0_sqmuxa_0); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_2); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_2); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f1_wdata_3, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(3)); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_2); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f1_wdata_7, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(7)); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f1_wdata_5, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(5)); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_2); - - \counter_RNO[22]\ : NOR2B - port map(A => I_143_2, B => un2_sample_in_val, Y => - \counter_4[22]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f1_wdata_64, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(64)); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f1_wdata_59, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(59)); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f1_wdata_11, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(11)); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f1(95), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(32)); - - \sample_out[69]\ : DFN1E1 - port map(D => sample_f1(101), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(26)); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f1_wdata_80, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(80)); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_2); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[75]\ : DFN1E1 - port map(D => sample_f1(107), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(20)); - - \counter_RNIMGNA[24]\ : NOR3A - port map(A => un2_sample_in_val_13, B => \counter[1]_net_1\, - C => \counter[24]_net_1\, Y => un2_sample_in_val_20); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \counter_RNIKN371[10]\ : OR3C - port map(A => un2_sample_in_val_23, B => - un2_sample_in_val_22, C => un2_sample_in_val_24, Y => - un2_sample_in_val_0); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_2); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f1_wdata_78, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(78)); - - \counter_RNO[18]\ : NOR2B - port map(A => I_115_2, B => un2_sample_in_val, Y => - \counter_4[18]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[77]\ : DFN1E1 - port map(D => sample_f1(109), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(18)); - - \counter_RNI0MBF1[10]\ : NOR3B - port map(A => sample_f1_val_0, B => HRESETn_c, C => - un2_sample_in_val_0, Y => sample_out_0_sqmuxa); - - sample_out_val_RNO : NOR2A - port map(A => sample_f1_val_0, B => un2_sample_in_val, Y - => sample_out_val_4); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f1(85), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(42)); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f1_wdata_67, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(67)); - - \counter_RNO[27]\ : NOR2B - port map(A => I_196_2, B => un2_sample_in_val, Y => - \counter_4[27]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f1(91), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(36)); - - \counter_RNI0MBF1_1[10]\ : NOR3B - port map(A => sample_f1_val_0, B => HRESETn_c, C => - un2_sample_in_val_0, Y => sample_out_0_sqmuxa_2); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f1_wdata_71, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(71)); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f1_wdata_53, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(53)); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f1_wdata_55, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(55)); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f1_wdata_12, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(12)); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f1_wdata_6, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(6)); - - \counter_RNIV507[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un2_sample_in_val_9); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => I_166_2, B => un2_sample_in_val, Y => - \counter_4[24]\); - - \counter[7]\ : DFN1E1C0 - port map(D => I_38_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_2); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f1_wdata_89, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(89)); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f1(94), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(33)); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f1(92), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(35)); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f1_wdata_60, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(60)); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f1_wdata_4, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(4)); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - \counter_RNIAEQF[20]\ : NOR3C - port map(A => un2_sample_in_val_15, B => - un2_sample_in_val_14, C => un2_sample_in_val_20, Y => - un2_sample_in_val_24); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : NOR2B - port map(A => I_129_2, B => un2_sample_in_val, Y => - \counter_4[20]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f1_wdata_58, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(58)); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f1_wdata_72, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(72)); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f1(84), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(43)); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f1_wdata_66, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(66)); - - \counter_RNI3C64[22]\ : NOR3A - port map(A => un2_sample_in_val_7, B => \counter[22]_net_1\, - C => \counter[19]_net_1\, Y => un2_sample_in_val_17); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f1(82), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(45)); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f1_wdata_77, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(77)); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f1_wdata_86, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(86)); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f1_wdata_88, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(88)); - - \sample_out[78]\ : DFN1E1 - port map(D => sample_f1(110), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(17)); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f1_wdata_81, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(81)); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f1_wdata_13, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(13)); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[9]_net_1\); - - \sample_out[74]\ : DFN1E1 - port map(D => sample_f1(106), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(21)); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f1_wdata_15, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(15)); - - \counter_RNIKN371_0[10]\ : OR3C - port map(A => un2_sample_in_val_23, B => - un2_sample_in_val_22, C => un2_sample_in_val_24, Y => - un2_sample_in_val); - - \counter_RNO[19]\ : NOR2B - port map(A => I_122_2, B => un2_sample_in_val, Y => - \counter_4[19]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : NOR2B - port map(A => I_52_2, B => un2_sample_in_val_0, Y => - \counter_4[9]\); - - \counter_RNIQKE[21]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un2_sample_in_val_11); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_2); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_2); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[18]_net_1\); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f1_wdata_87, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(87)); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f1_wdata_54, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(54)); - - \counter_RNO[16]\ : NOR2B - port map(A => I_98_2, B => un2_sample_in_val_0, Y => - \counter_4[16]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_2, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f1_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f1_wdata_49, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(49)); - - \counter_RNIKDT[27]\ : NOR3A - port map(A => un2_sample_in_val_1, B => \counter[11]_net_1\, - C => \counter[27]_net_1\, Y => un2_sample_in_val_14); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f1_wdata_92, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(92)); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_6_16_96 is - - port( sample_f0 : in std_logic_vector(111 downto 80); - sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f2_wdata : out std_logic_vector(95 downto 0); - sample_f0_val : in std_logic; - sample_f0_val_1 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_f2_val : out std_logic; - sample_f0_val_0 : in std_logic; - sample_out_0_sqmuxa_1 : in std_logic - ); - -end Downsampling_6_16_96; - -architecture DEF_ARCH of Downsampling_6_16_96 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - signal un6_sample_in_val_24_0, un6_sample_in_val_15, - un6_sample_in_val_14, un6_sample_in_val_20, - un6_sample_in_val_25_0, un6_sample_in_val_17, - un6_sample_in_val_16, un6_sample_in_val_23, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1_0, - sample_out_0_sqmuxa_0, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un6_sample_in_val_25, - un6_sample_in_val_24, un6_sample_in_val_9, - un6_sample_in_val_8, un6_sample_in_val_19, - un6_sample_in_val_13, \counter[24]_net_1\, - un6_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un6_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un6_sample_in_val_5, \counter[10]_net_1\, - \counter[7]_net_1\, un6_sample_in_val_3, - \counter[23]_net_1\, \counter[20]_net_1\, - un6_sample_in_val_1, \counter[11]_net_1\, - \counter[27]_net_1\, \counter[18]_net_1\, - \counter[21]_net_1\, \counter[9]_net_1\, - \counter[4]_net_1\, \counter[6]_net_1\, - \counter[25]_net_1\, \counter[2]_net_1\, - \counter[13]_net_1\, \counter[16]_net_1\, - \counter[26]_net_1\, \counter[5]_net_1\, - \counter[14]_net_1\, \counter[17]_net_1\, - sample_out_val_9, \counter_4[5]\, I_24_1, \counter_4[7]\, - I_38_1, \counter_4[8]\, I_45_1, \counter_4[9]\, I_52_1, - \counter_4[10]\, I_56_1, \counter_4[11]\, I_66_1, - \counter_4[12]\, I_73_1, \counter_4[13]\, I_77_1, - \counter_4[14]\, I_84_1, \counter_4[15]\, I_91_1, - \counter_4[16]\, I_98_1, \counter_4[17]\, I_105_1, - \counter_4[18]\, I_115_1, \counter_4[19]\, I_122_1, - \counter_4[20]\, I_129_1, \counter_4[21]\, I_136_1, - \counter_4[22]\, I_143_1, \counter_4[23]\, I_156_1, - \counter_4[24]\, I_166_1, \counter_4[25]\, I_173_1, - \counter_4[26]\, I_186_1, \counter_4[27]\, I_196_1, - sample_out_0_sqmuxa, I_4_1, I_5_1, I_9_1, I_13_1, I_20_1, - I_31_2, N_4, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[19]_net_1\); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f0_wdata_73, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(73)); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f0_wdata_75, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(75)); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f0_wdata_82, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(82)); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f0_wdata_94, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(94)); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f0_wdata_76, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(76)); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f0(93), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(34)); - - \sample_out[66]\ : DFN1E1 - port map(D => sample_f0(98), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(29)); - - \sample_out[73]\ : DFN1E1 - port map(D => sample_f0(105), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(22)); - - \sample_out[79]\ : DFN1E1 - port map(D => sample_f0(111), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(16)); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f0_wdata_57, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(57)); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f0_wdata_0, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(0)); - - \counter_RNO[11]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_66_1, Y => \counter_4[11]\); - - \counter_RNISF54[20]\ : NOR3A - port map(A => un6_sample_in_val_3, B => \counter[23]_net_1\, - C => \counter[20]_net_1\, Y => un6_sample_in_val_15); - - \counter_RNID1T[12]\ : NOR3A - port map(A => un6_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un6_sample_in_val_19); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f0_wdata_61, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(61)); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_1); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_1); - - \counter_RNO[15]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_91_1, Y => \counter_4[15]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f0(83), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(44)); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f0(88), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(39)); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f0_wdata_95, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(95)); - - \counter_RNO[7]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_38_1, Y => \counter_4[7]\); - - \counter[6]\ : DFN1E1C0 - port map(D => I_31_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f0_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter_RNIPSE[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un6_sample_in_val_1); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_1); - - \counter_RNIF507[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un6_sample_in_val_13); - - \counter_RNI3LBF1_1[10]\ : NOR3C - port map(A => un6_sample_in_val_24_0, B => - un6_sample_in_val_25_0, C => sample_out_0_sqmuxa_1, Y => - sample_out_0_sqmuxa_2); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f0_wdata_14, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(14)); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f0_wdata_9, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(9)); - - \counter_RNIOKE[21]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un6_sample_in_val_11); - - \counter[3]\ : DFN1E1C0 - port map(D => I_13_1, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f0_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_1, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_1); - - \counter_RNO[8]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_45_1, Y => \counter_4[8]\); - - \counter_RNIUDQF[20]\ : NOR3C - port map(A => un6_sample_in_val_15, B => - un6_sample_in_val_14, C => un6_sample_in_val_20, Y => - un6_sample_in_val_24_0); - - \counter_RNO[13]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_77_1, Y => \counter_4[13]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_1); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f0_wdata_83, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(83)); - - \counter_RNIQ89N[10]\ : NOR3C - port map(A => un6_sample_in_val_17, B => - un6_sample_in_val_16, C => un6_sample_in_val_23, Y => - un6_sample_in_val_25_0); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f0_wdata_85, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(85)); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f0_wdata_50, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(50)); - - \counter_RNO[12]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_73_1, Y => \counter_4[12]\); - - \counter_RNIT507[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un6_sample_in_val_9); - - \sample_out[72]\ : DFN1E1 - port map(D => sample_f0(104), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(23)); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f0_wdata_62, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(62)); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f0_wdata_56, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(56)); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[17]_net_1\); - - \sample_out[70]\ : DFN1E1 - port map(D => sample_f0(102), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(25)); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => I_20_1, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f0_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_1); - - \counter_RNIGDT[27]\ : NOR3A - port map(A => un6_sample_in_val_1, B => \counter[11]_net_1\, - C => \counter[27]_net_1\, Y => un6_sample_in_val_14); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f0_wdata_90, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(90)); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f0_wdata_48, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(48)); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \sample_out[65]\ : DFN1E1 - port map(D => sample_f0(97), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(30)); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f0_wdata_74, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(74)); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f0_wdata_69, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(69)); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f0_wdata_93, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(93)); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[27]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[27]_net_1\); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \sample_out[67]\ : DFN1E1 - port map(D => sample_f0(99), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(28)); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f0_wdata_1, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(1)); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_1); - - \counter_RNO[17]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_105_1, Y => \counter_4[17]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f0(87), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(40)); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_1); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f0_wdata_63, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(63)); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_1); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f0(89), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(38)); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f0_wdata_65, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(65)); - - \counter_RNO[14]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_84_1, Y => \counter_4[14]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f0_wdata_10, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(10)); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_1, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_186_1, Y => \counter_4[26]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f0_wdata_91, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(91)); - - \counter_RNO[5]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_24_1, Y => \counter_4[5]\); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[25]_net_1\); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_9, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f2_val); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f0_wdata_8, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(8)); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_1); - - \counter_RNIUDQF_0[20]\ : NOR3C - port map(A => un6_sample_in_val_15, B => - un6_sample_in_val_14, C => un6_sample_in_val_20, Y => - un6_sample_in_val_24); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_1); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f0(80), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(47)); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_1); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f0_wdata_2, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(2)); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f0_wdata_84, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(84)); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f0_wdata_79, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(79)); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f0_wdata_51, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(51)); - - \sample_out[71]\ : DFN1E1 - port map(D => sample_f0(103), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(24)); - - \counter_RNI0DTE[12]\ : NOR3C - port map(A => un6_sample_in_val_9, B => un6_sample_in_val_8, - C => un6_sample_in_val_19, Y => un6_sample_in_val_23); - - \sample_out[76]\ : DFN1E1 - port map(D => sample_f0(108), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(19)); - - \counter_RNI3LBF1_0[10]\ : NOR3C - port map(A => un6_sample_in_val_24_0, B => - un6_sample_in_val_25_0, C => sample_out_0_sqmuxa_1, Y => - sample_out_0_sqmuxa_0); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_56_1, Y => \counter_4[10]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_1); - - \counter_RNO[21]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_136_1, Y => \counter_4[21]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_1); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[68]\ : DFN1E1 - port map(D => sample_f0(100), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(27)); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f0_wdata_70, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(70)); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_1); - - \counter_RNIM507[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un6_sample_in_val_8); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_173_1, Y => \counter_4[25]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - \sample_out[64]\ : DFN1E1 - port map(D => sample_f0(96), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(31)); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_2); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_1); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f0_wdata_68, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(68)); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNI3LBF1_2[10]\ : NOR3C - port map(A => un6_sample_in_val_24_0, B => - un6_sample_in_val_25_0, C => sample_out_0_sqmuxa_1, Y => - sample_out_0_sqmuxa_1_0); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_1); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - \counter_RNIRF54[10]\ : NOR3A - port map(A => un6_sample_in_val_5, B => \counter[10]_net_1\, - C => \counter[7]_net_1\, Y => un6_sample_in_val_16); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f0(90), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(37)); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[26]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_1); - - \counter_RNO[23]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_156_1, Y => \counter_4[23]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f0(86), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(41)); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f0_wdata_52, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(52)); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f0(81), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(46)); - - \counter_RNI3LBF1[10]\ : NOR3C - port map(A => un6_sample_in_val_24, B => - un6_sample_in_val_25, C => sample_out_0_sqmuxa_1, Y => - sample_out_0_sqmuxa); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_1); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_1); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f0_wdata_3, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(3)); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_1); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f0_wdata_7, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(7)); - - \counter_RNIVB64[22]\ : NOR3A - port map(A => un6_sample_in_val_7, B => \counter[22]_net_1\, - C => \counter[19]_net_1\, Y => un6_sample_in_val_17); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f0_wdata_5, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(5)); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_1); - - \counter_RNO[22]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_143_1, Y => \counter_4[22]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f0_wdata_64, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(64)); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f0_wdata_59, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(59)); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f0_wdata_11, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(11)); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f0(95), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(32)); - - \sample_out[69]\ : DFN1E1 - port map(D => sample_f0(101), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(26)); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f0_wdata_80, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(80)); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_1); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[75]\ : DFN1E1 - port map(D => sample_f0(107), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(20)); - - \counter_RNIIGNA[24]\ : NOR3A - port map(A => un6_sample_in_val_13, B => \counter[1]_net_1\, - C => \counter[24]_net_1\, Y => un6_sample_in_val_20); - - \counter_RNI9JN3[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un6_sample_in_val_3); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \counter_RNIQ89N_0[10]\ : NOR3C - port map(A => un6_sample_in_val_17, B => - un6_sample_in_val_16, C => un6_sample_in_val_23, Y => - un6_sample_in_val_25); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_1); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f0_wdata_78, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(78)); - - \counter_RNO[18]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_115_1, Y => \counter_4[18]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[77]\ : DFN1E1 - port map(D => sample_f0(109), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(18)); - - sample_out_val_RNO : NOR3C - port map(A => un6_sample_in_val_24_0, B => - un6_sample_in_val_25_0, C => sample_f0_val_0, Y => - sample_out_val_9); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f0(85), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(42)); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f0_wdata_67, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(67)); - - \counter_RNO[27]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_196_1, Y => \counter_4[27]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f0(91), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(36)); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f0_wdata_71, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(71)); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f0_wdata_53, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(53)); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f0_wdata_55, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(55)); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f0_wdata_12, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(12)); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f0_wdata_6, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(6)); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_166_1, Y => \counter_4[24]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_1); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f0_wdata_89, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(89)); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f0(94), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(33)); - - \counter_RNINKE[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un6_sample_in_val_5); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f0(92), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(35)); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f0_wdata_60, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(60)); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f0_wdata_4, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(4)); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_129_1, Y => \counter_4[20]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f0_wdata_58, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(58)); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f0_wdata_72, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(72)); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f0(84), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(43)); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f0_wdata_66, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(66)); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f0(82), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(45)); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f0_wdata_77, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(77)); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f0_wdata_86, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(86)); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f0_wdata_88, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(88)); - - \sample_out[78]\ : DFN1E1 - port map(D => sample_f0(110), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(17)); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f0_wdata_81, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(81)); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f0_wdata_13, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(13)); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[9]_net_1\); - - \sample_out[74]\ : DFN1E1 - port map(D => sample_f0(106), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(21)); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f0_wdata_15, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(15)); - - \counter_RNO[19]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_122_1, Y => \counter_4[19]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_52_1, Y => \counter_4[9]\); - - \counter_RNI5FN3[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un6_sample_in_val_7); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_1); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_1); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[18]_net_1\); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f0_wdata_87, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(87)); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f0_wdata_54, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(54)); - - \counter_RNO[16]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_98_1, Y => \counter_4[16]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_1, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val_1, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f0_wdata_49, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(49)); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f0_wdata_92, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(92)); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 is - - port( sample_f1_wdata_95 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_0 : in std_logic; - data_f1_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0); - sample_f1_37 : in std_logic; - sample_f1_5 : in std_logic; - sample_f1_38 : in std_logic; - sample_f1_6 : in std_logic; - sample_f1_39 : in std_logic; - sample_f1_7 : in std_logic; - sample_f1_40 : in std_logic; - sample_f1_8 : in std_logic; - sample_f1_41 : in std_logic; - sample_f1_9 : in std_logic; - sample_f1_42 : in std_logic; - sample_f1_10 : in std_logic; - sample_f1_43 : in std_logic; - sample_f1_11 : in std_logic; - sample_f1_61 : in std_logic; - sample_f1_62 : in std_logic; - sample_f1_63 : in std_logic; - sample_f1_32 : in std_logic; - sample_f1_0 : in std_logic; - sample_f1_33 : in std_logic; - sample_f1_1 : in std_logic; - sample_f1_34 : in std_logic; - sample_f1_2 : in std_logic; - sample_f1_35 : in std_logic; - sample_f1_3 : in std_logic; - sample_f1_36 : in std_logic; - sample_f1_4 : in std_logic; - sample_f1_48 : in std_logic; - sample_f1_49 : in std_logic; - sample_f1_50 : in std_logic; - sample_f1_51 : in std_logic; - sample_f1_52 : in std_logic; - sample_f1_53 : in std_logic; - sample_f1_54 : in std_logic; - sample_f1_55 : in std_logic; - sample_f1_56 : in std_logic; - sample_f1_57 : in std_logic; - sample_f1_58 : in std_logic; - sample_f1_59 : in std_logic; - sample_f1_60 : in std_logic; - sample_f1_44 : in std_logic; - sample_f1_12 : in std_logic; - sample_f1_45 : in std_logic; - sample_f1_13 : in std_logic; - sample_f1_46 : in std_logic; - sample_f1_14 : in std_logic; - sample_f1_47 : in std_logic; - sample_f1_15 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f1_out_valid : out std_logic; - N_4 : in std_logic; - I_38_4 : in std_logic; - I_24_4 : in std_logic; - I_20_12 : in std_logic; - I_13_20 : in std_logic; - I_45_4 : in std_logic; - I_9_20 : in std_logic; - I_5_20 : in std_logic; - I_52_4 : in std_logic; - data_shaping_R1 : in std_logic; - data_shaping_R1_0 : in std_logic; - I_56_4 : in std_logic; - I_31_5 : in std_logic; - enable_f1 : in std_logic; - burst_f1 : in std_logic; - sample_f1_val_0 : in std_logic; - start_snapshot_f1 : in std_logic - ); - -end lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1; - -architecture DEF_ARCH of - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_47_1, \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - N_59, N_47_0, counter_points_snapshot_0_sqmuxa_1_0, - ADD_32x32_fast_I308_Y_0_0, - \counter_points_snapshot[28]_net_1\, - ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I310_Y_0_0, - \counter_points_snapshot[30]_net_1\, - ADD_32x32_fast_I309_Y_0_0, - \counter_points_snapshot[29]_net_1\, - ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I253_Y_0_0, N481, N485, - ADD_32x32_fast_I250_Y_2, ADD_32x32_fast_I250_Y_1, N483, - N487, N467, N470, N479, ADD_32x32_fast_I295_Y_0_0, - \counter_points_snapshot[15]_net_1\, - ADD_32x32_fast_I251_Y_2, ADD_32x32_fast_I251_Y_1, N489, - N464, ADD_32x32_fast_I302_Y_0_0, - \counter_points_snapshot[22]_net_1\, - ADD_32x32_fast_I252_Y_1, N550, ADD_32x32_fast_I294_Y_0_0, - \counter_points_snapshot[14]_net_1\, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, - ADD_32x32_fast_I301_Y_0_0, - \counter_points_snapshot[21]_net_1\, - ADD_32x32_fast_I288_Y_0_0, - \un1_counter_points_snapshot[23]\, - ADD_32x32_fast_I293_Y_0_0, - \counter_points_snapshot[13]_net_1\, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I300_Y_0_0, - \counter_points_snapshot[20]_net_1\, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot[5]\, - ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I254_Y_0, N554, ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I255_Y_0, N556, ADD_32x32_fast_I256_Y_0, - I112_un1_Y, N495, ADD_32x32_fast_I263_Y_0, N580, N588, - N533, ADD_32x32_fast_I282_Y_0_0, - \un1_counter_points_snapshot[29]\, - ADD_32x32_fast_I134_Y_1, N401, ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[22]\, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot[26]\, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I126_Y_1, - \un1_counter_points_snapshot[20]\, N419, - ADD_32x32_fast_I126_Y_0, - \un1_counter_points_snapshot[21]\, - ADD_32x32_fast_I118_Y_1, N425, ADD_32x32_fast_I118_Y_0, - N422, data_out_valid_9_i_0, un1_data_in_validlt30_27, - un1_data_in_validlt30_18, un1_data_in_validlt30_17, - un1_data_in_validlt30_23, un1_data_in_validlt30_26, - un1_data_in_validlt30_12, un1_data_in_validlt30_11, - un1_data_in_validlt30_22, un1_data_in_validlt30_25, - un1_data_in_validlt30_8, un1_data_in_validlt30_7, - un1_data_in_validlt30_20, un1_data_in_validlt30_2, - un1_data_in_validlt30_1, un1_data_in_validlt30_15, - un1_data_in_validlt30_14, - \counter_points_snapshot[27]_net_1\, - \counter_points_snapshot[26]_net_1\, - un1_data_in_validlt30_10, - \counter_points_snapshot[19]_net_1\, - \counter_points_snapshot[18]_net_1\, - un1_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un1_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, N758, N638, N622_i, - N654, N748, N628, N786, - \un1_data_out_valid_0_sqmuxa_2[10]\, - \un1_data_out_valid_0_sqmuxa_2[6]\, N652, - \un1_data_out_valid_0_sqmuxa_2[9]\, N789, N750_i, N630, - N744, N752, N_49, N_52, N_60, un1_data_in_validlto30_i, - N_47, counter_points_snapshot_0_sqmuxa_1, N740, N774, - N620, N738, N771_i, N618, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, N380, N756, N636, N529, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_data_out_valid_0_sqmuxa_2[8]\, N650, - \un1_data_out_valid_0_sqmuxa_2[4]\, N592, - \un1_data_out_valid_0_sqmuxa_2[3]\, - \un1_counter_points_snapshot[28]\, N594, - \un1_data_out_valid_0_sqmuxa_2[5]\, N766, N646, N443, - N440, N497, \un1_data_out_valid_0_sqmuxa_2[7]\, - \un1_counter_points_snapshot[24]\, N754, N634, N572, - \un1_data_out_valid_0_sqmuxa_2[11]\, N783, N742, N777, - N762, N642, N626, N764, N746, N574, N515, N511, N566, - N582, N_90, counter_points_snapshot_2_sqmuxa, N_94, - \counter_points_snapshot_10[6]\, - \counter_points_snapshot_10[10]\, N_25, N_35, - \sample_f1_wdata[32]\, \sample_f1_wdata[33]\, - \sample_f1_wdata[34]\, \sample_f1_wdata[35]\, - \sample_f1_wdata[19]\, \sample_f1_wdata[20]\, - \sample_f1_wdata[21]\, \sample_f1_wdata[22]\, - \sample_f1_wdata[23]\, \sample_f1_wdata[24]\, - \sample_f1_wdata[25]\, \sample_f1_wdata[26]\, - \sample_f1_wdata[27]\, \sample_f1_wdata[28]\, - \sample_f1_wdata[29]\, \sample_f1_wdata[30]\, - \sample_f1_wdata[31]\, \sample_f1_wdata[43]\, - \sample_f1_wdata[44]\, \sample_f1_wdata[45]\, - \sample_f1_wdata[46]\, \sample_f1_wdata[47]\, - \sample_f1_wdata[16]\, \sample_f1_wdata[17]\, - \sample_f1_wdata[18]\, \sample_f1_wdata[36]\, - \sample_f1_wdata[37]\, \sample_f1_wdata[38]\, - \sample_f1_wdata[39]\, \sample_f1_wdata[40]\, - \sample_f1_wdata[41]\, \sample_f1_wdata[42]\, N_9, N_7, - N780, N503, N570, N_27, \counter_points_snapshot_10[9]\, - N_93, N446, N_39, \counter_points_snapshot_10[1]\, N_85, - N_45, N_43, N_13, N_11, \counter_points_snapshot_10[2]\, - N_86, N_92, \counter_points_snapshot_10[8]\, N590, N531, - N527, N386, N383, \un1_counter_points_snapshot[31]\, - \un1_data_out_valid_0_sqmuxa_2[0]\, N_84, - \counter_points_snapshot_10[0]\, N586, N523, N_87, N_88, - \counter_points_snapshot_10[3]\, - \counter_points_snapshot_10[4]\, N_17, - \counter_points_snapshot_10[5]\, N_89, N519, N_31, N_29, - \counter_points_snapshot_10[7]\, N_91, N_33, N_41, - \counter_points_snapshot_10[11]\, N_95, N_21, N768, N_15, - N_37, N_23, N760, N_19, N578, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => N_9, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[27]\, C => N592, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - \counter_points_snapshot_RNI7ND9[16]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un1_data_in_validlt30_8); - - \data_out[110]\ : DFN1C0 - port map(D => \sample_f1_wdata[46]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(110)); - - \counter_points_snapshot_RNI9G66[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un1_data_in_validlt30_4); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[10]\, B => - I_56_4, S => counter_points_snapshot_2_sqmuxa, Y => N_94); - - \counter_points_snapshot_RNO[27]\ : XA1C - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - N_52, Y => N_37); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => N_39, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[28]_net_1\); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762, B => ADD_32x32_fast_I299_Y_0_0, C => - N_52, Y => N_21); - - \data_out_RNO[96]\ : MX2 - port map(A => sample_f1_15, B => sample_f1_47, S => - data_shaping_R1_0, Y => \sample_f1_wdata[32]\); - - \data_out[91]\ : DFN1C0 - port map(D => \sample_f1_wdata[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(91)); - - \counter_points_snapshot_RNISSL51[23]\ : NOR3C - port map(A => un1_data_in_validlt30_12, B => - un1_data_in_validlt30_11, C => un1_data_in_validlt30_22, - Y => un1_data_in_validlt30_26); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f1_wdata_56, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1C - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - N_52, Y => N_31); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : OR3A - port map(A => ADD_32x32_fast_I254_Y_0, B => N626, C => N783, - Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : NOR2 - port map(A => N586, B => N578, Y => N642); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f1_wdata_66, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => \sample_f1_wdata[40]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : OR3B - port map(A => N443, B => N446, C => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => I_20_12, B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => N_60, Y => N_88); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[1]\, B => - I_5_20, S => counter_points_snapshot_2_sqmuxa, Y => N_85); - - \data_out[102]\ : DFN1C0 - port map(D => \sample_f1_wdata[38]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3B - port map(A => N622_i, B => ADD_32x32_fast_I252_Y_1, C => - N777, Y => N742); - - \counter_points_snapshot_RNIHVMR1[11]\ : MX2 - port map(A => N_4, B => \counter_points_snapshot[11]_net_1\, - S => counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[29]\, B => - N_47_0, Y => ADD_32x32_fast_I282_Y_0_0); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_91, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[29]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1C - port map(A => N780, B => ADD_32x32_fast_I292_Y_0_0, C => - N_52, Y => N_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : NOR2 - port map(A => N650, B => N634, Y => N771_i); - - \data_out[93]\ : DFN1C0 - port map(D => \sample_f1_wdata[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(93)); - - \counter_points_snapshot_RNIHME71[4]\ : MX2C - port map(A => I_20_12, B => - \counter_points_snapshot[4]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[27]\); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[4]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[21]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f1_wdata_95, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => \sample_f1_wdata[41]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(105)); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f1_wdata_77, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR3B - port map(A => N443, B => N446, C => N495, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2B - port map(A => N527, B => N523, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => \sample_f1_wdata[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(81)); - - \counter_points_snapshot_RNIU5411[2]\ : MX2C - port map(A => I_9_20, B => - \counter_points_snapshot[2]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[29]\); - - counter_points_snapshot_10_12_i_o2 : OR3B - port map(A => enable_f1, B => N_60, C => burst_f1, Y => - N_52); - - \data_out_RNO[99]\ : MX2 - port map(A => sample_f1_12, B => sample_f1_44, S => - data_shaping_R1_0, Y => \sample_f1_wdata[35]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[30]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I310_Y_0_0); - - \data_out_RNO[104]\ : MX2 - port map(A => sample_f1_7, B => sample_f1_39, S => - data_shaping_R1, Y => \sample_f1_wdata[40]\); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : OR3 - port map(A => I112_un1_Y, B => N495, C => N550, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - OR2A - port map(A => N771_i, B => N425, Y => N768); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f1_wdata_50, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : OR2 - port map(A => N578, B => N570, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : NOR3 - port map(A => N419, B => N422, C => N503, Y => N566); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => N_37, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f1_wdata_79, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(143)); - - \counter_points_snapshot_RNI319P[27]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : OR2 - port map(A => N590, B => N533, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3C - port map(A => N443, B => N440, C => N497, Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f1_wdata_48, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f1_wdata_60, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(124)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f1_wdata_70, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : AO1 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[25]\, C => N_47, Y => N523); - - \counter_points_snapshot_RNO[28]\ : XA1B - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - N_52, Y => N_39); - - \data_out[83]\ : DFN1C0 - port map(D => \sample_f1_wdata[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I250_Y_1, B => N483, C => N487, - Y => ADD_32x32_fast_I250_Y_2); - - \counter_points_snapshot_RNIMURI[26]\ : NOR3A - port map(A => un1_data_in_validlt30_14, B => - \counter_points_snapshot[27]_net_1\, C => - \counter_points_snapshot[26]_net_1\, Y => - un1_data_in_validlt30_22); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f1_wdata_58, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f1_wdata_51, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(115)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : OA1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[8]\, C => N_47, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : - OA1C - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_counter_points_snapshot[4]\, C => N_47, Y => N481); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AO1D - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_1, C => N422, Y => ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f1_wdata_68, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(132)); - - \counter_points_snapshot_RNIM3VT[1]\ : MX2C - port map(A => I_5_20, B => - \counter_points_snapshot[1]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[30]\); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => N_43, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[30]_net_1\); - - \data_out[96]\ : DFN1C0 - port map(D => \sample_f1_wdata[32]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(96)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : NOR3 - port map(A => N628, B => ADD_32x32_fast_I255_Y_0, C => N786, - Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[14]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f1_wdata_61, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(125)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f1_wdata_71, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(135)); - - \data_out_RNO[87]\ : NOR2B - port map(A => sample_f1_56, B => data_shaping_R1_0, Y => - \sample_f1_wdata[23]\); - - \data_out_RNO[108]\ : MX2 - port map(A => sample_f1_3, B => sample_f1_35, S => - data_shaping_R1, Y => \sample_f1_wdata[44]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_G0N : NOR3B - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N425); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : NOR2 - port map(A => ADD_32x32_fast_I253_Y_0_0, B => N752, Y => - N744); - - data_out_valid : DFN1C0 - port map(D => N_49, CLK => HCLK_c, CLR => HRESETn_c, Q => - data_f1_out_valid); - - \data_out_RNO[90]\ : NOR2B - port map(A => sample_f1_53, B => data_shaping_R1_0, Y => - \sample_f1_wdata[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : OR3 - port map(A => I112_un1_Y, B => N503, C => N570, Y => N626); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I29_G0N : OR3B - port map(A => \counter_points_snapshot[29]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N467); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f1_wdata_7, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f1_wdata_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => N_19, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : OR3B - port map(A => N638, B => N622_i, C => N654, Y => N758); - - \data_out_RNO[98]\ : MX2 - port map(A => sample_f1_13, B => sample_f1_45, S => - data_shaping_R1_0, Y => \sample_f1_wdata[34]\); - - \data_out[86]\ : DFN1C0 - port map(D => \sample_f1_wdata[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[23]\, B => - N_47_0, Y => ADD_32x32_fast_I288_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : OR3 - port map(A => I112_un1_Y, B => N503, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f1_wdata_86, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(150)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_0, Y => ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - N_47_0, Y => ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f1_wdata_84, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(148)); - - GND_i : GND - port map(Y => \GND\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_G0N : NOR3B - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N419); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[8]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : OR2A - port map(A => N566, B => N574, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR2B - port map(A => N523, B => N519, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f1_wdata_9, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_out[92]\ : DFN1C0 - port map(D => \sample_f1_wdata[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f1_wdata_3, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => \sample_f1_wdata[43]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I14_G0N : NOR3B - port map(A => \counter_points_snapshot[14]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N422); - - \counter_points_snapshot_RNISOQ14[6]\ : NOR3C - port map(A => un1_data_in_validlt30_26, B => - un1_data_in_validlt30_25, C => un1_data_in_validlt30_27, - Y => un1_data_in_validlto30_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OR3B - port map(A => N580, B => N588, C => N533, Y => - ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_90, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[21]\, C => N786, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => N_41, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[29]_net_1\); - - \data_out_RNO[94]\ : NOR2B - port map(A => sample_f1_49, B => data_shaping_R1_0, Y => - \sample_f1_wdata[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[20]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1C - port map(A => N750_i, B => ADD_32x32_fast_I305_Y_0_0, C => - N_52, Y => N_33); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => N_23, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[22]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I302_Y_0_0); - - \counter_points_snapshot_RNI2T8P[26]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot[5]\); - - \data_out_RNO[95]\ : NOR2B - port map(A => sample_f1_48, B => data_shaping_R1, Y => - \sample_f1_wdata[31]\); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => N_17, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : OR2 - port map(A => N590, B => N582, Y => N646); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : NOR2 - port map(A => N386, B => N383, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - N_47_0, Y => ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I28_G0N : OR3B - port map(A => \counter_points_snapshot[28]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N464); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : OR3B - port map(A => ADD_32x32_fast_I250_Y_2, B => N771_i, C => - N618, Y => N738); - - \data_out_RNO[93]\ : NOR2B - port map(A => sample_f1_50, B => data_shaping_R1_0, Y => - \sample_f1_wdata[29]\); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f1_wdata_90, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(154)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - OR2B - port map(A => N764, B => N497, Y => N760); - - \data_out[82]\ : DFN1C0 - port map(D => \sample_f1_wdata[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f1_wdata_53, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1C - port map(A => N760, B => ADD_32x32_fast_I300_Y_0_0, C => - N_52, Y => N_23); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : NOR3 - port map(A => N483, B => N487, C => N554, Y => - ADD_32x32_fast_I254_Y_0); - - \counter_points_snapshot_RNIICL51[14]\ : NOR3C - port map(A => un1_data_in_validlt30_8, B => - un1_data_in_validlt30_7, C => un1_data_in_validlt30_20, Y - => un1_data_in_validlt30_25); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f1_wdata_12, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(76)); - - \counter_points_snapshot_RNI1G66[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un1_data_in_validlt30_2); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f1_wdata_88, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(152)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_1 : AO1A - port map(A => N_47_1, B => - \un1_counter_points_snapshot[15]\, C => N425, Y => - ADD_32x32_fast_I118_Y_1); - - \counter_points_snapshot_RNIE0DC[6]\ : NOR3A - port map(A => un1_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un1_data_in_validlt30_17); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f1_wdata_85, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(149)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f1_wdata_63, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : OR2A - port map(A => N638, B => N654, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : NOR2 - port map(A => N652, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2A - port map(A => N588, B => N533, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f1_wdata_73, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I30_G0N : OR3B - port map(A => \counter_points_snapshot[30]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N470); - - \data_out_RNO[81]\ : NOR2B - port map(A => sample_f1_62, B => data_shaping_R1, Y => - \sample_f1_wdata[17]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : OR2B - port map(A => N531, B => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f1_wdata_91, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(155)); - - \counter_points_snapshot_RNI1T8P[16]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_89, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1C - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - N_52, Y => N_17); - - data_out_valid_RNO_0 : NOR2B - port map(A => enable_f1, B => sample_f1_val_0, Y => - data_out_valid_9_i_0); - - \data_out[90]\ : DFN1C0 - port map(D => \sample_f1_wdata[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_0 : AO1 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[21]\, C => N_47_1, Y => - ADD_32x32_fast_I126_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR3 - port map(A => N419, B => N422, C => N511, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR3B - port map(A => ADD_32x32_fast_I251_Y_2, B => N774, C => N620, - Y => N740); - - \counter_points_snapshot_RNO[14]\ : XA1C - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - N_52, Y => N_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_G0N : OR3B - port map(A => \counter_points_snapshot[20]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N440); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR2A - port map(A => N519, B => N515, Y => N578); - - \counter_points_snapshot_RNI385K1[8]\ : MX2 - port map(A => I_45_4, B => - \counter_points_snapshot[8]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[23]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I282_Y_0_0, B => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - \data_out_RNO[92]\ : NOR2B - port map(A => sample_f1_51, B => data_shaping_R1_0, Y => - \sample_f1_wdata[28]\); - - counter_points_snapshot_2_sqmuxa_0_a2 : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_60, Y => - counter_points_snapshot_2_sqmuxa); - - \data_out[99]\ : DFN1C0 - port map(D => \sample_f1_wdata[35]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(99)); - - \counter_points_snapshot_RNI359P[18]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - \counter_points_snapshot_RNI219P[17]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - \data_out_RNO[100]\ : MX2 - port map(A => sample_f1_11, B => sample_f1_43, S => - data_shaping_R1, Y => \sample_f1_wdata[36]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I76_Y : OA1C - port map(A => \un1_counter_points_snapshot[23]\, B => N_47, - C => N401, Y => N519); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : NOR3 - port map(A => N634, B => N618, C => N650, Y => N754); - - \data_out[106]\ : DFN1C0 - port map(D => \sample_f1_wdata[42]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1C - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - N_52, Y => N_25); - - \data_out_RNO[103]\ : MX2 - port map(A => sample_f1_8, B => sample_f1_40, S => - data_shaping_R1, Y => \sample_f1_wdata[39]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : OR2 - port map(A => N515, B => N511, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => \sample_f1_wdata[34]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(98)); - - \counter_points_snapshot_RNIEFFM1[6]\ : NOR3C - port map(A => un1_data_in_validlt30_18, B => - un1_data_in_validlt30_17, C => un1_data_in_validlt30_23, - Y => un1_data_in_validlt30_27); - - \counter_points_snapshot_RNI1NC9[23]\ : NOR2 - port map(A => \counter_points_snapshot[22]_net_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - un1_data_in_validlt30_11); - - \data_out[80]\ : DFN1C0 - port map(D => \sample_f1_wdata[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f1_wdata_8, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : NOR3 - port map(A => N630, B => ADD_32x32_fast_I256_Y_0, C => N789, - Y => N750_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_G0N : OR3B - port map(A => \counter_points_snapshot[22]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N446); - - \counter_points_snapshot_RNITF66[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un1_data_in_validlt30_1); - - \counter_points_snapshot_RNI7C941[3]\ : MX2C - port map(A => I_13_20, B => - \counter_points_snapshot[3]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[28]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AOI1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47, Y => - I112_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : AX1B - port map(A => N401, B => N650, C => - ADD_32x32_fast_I288_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - \data_out_RNO[107]\ : MX2 - port map(A => sample_f1_4, B => sample_f1_36, S => - data_shaping_R1, Y => \sample_f1_wdata[43]\); - - counter_points_snapshot_2_sqmuxa_0_a2_0 : OR2A - port map(A => start_snapshot_f1, B => sample_f1_val_0, Y - => N_60); - - \data_out[89]\ : DFN1C0 - port map(D => \sample_f1_wdata[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(89)); - - \counter_points_snapshot_RNIGRMR1[10]\ : MX2C - port map(A => I_56_4, B => - \counter_points_snapshot[10]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[21]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : NOR2 - port map(A => ADD_32x32_fast_I263_Y_0, B => N628, Y => N764); - - counter_points_snapshot_0_sqmuxa_1_0_a2 : OR3B - port map(A => start_snapshot_f1, B => sample_f1_val_0, C - => burst_f1, Y => counter_points_snapshot_0_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, C => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out_RNO[101]\ : MX2 - port map(A => sample_f1_10, B => sample_f1_42, S => - data_shaping_R1, Y => \sample_f1_wdata[37]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f1_wdata_52, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => N_21, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[2]\, B => - I_9_20, S => counter_points_snapshot_2_sqmuxa, Y => N_86); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - N_47_0, Y => ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : OR2 - port map(A => N594, B => N586, Y => N650); - - \counter_points_snapshot_RNI0L8P[24]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[26]\, C => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1C - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - N_52, Y => N_19); - - \data_out[88]\ : DFN1C0 - port map(D => \sample_f1_wdata[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XNOR2 - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f1_wdata_62, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => \sample_f1_wdata[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f1_wdata_76, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f1_wdata_72, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(136)); - - \counter_points_snapshot_RNI8HSA[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[30]_net_1\, Y => - un1_data_in_validlt30_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I293_Y_0_0); - - \un1_data_out_valid_0_sqmuxa_1_i_0[31]\ : AOI1B - port map(A => start_snapshot_f1, B => burst_f1, C => - sample_f1_val_0, Y => - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\); - - \counter_points_snapshot_RNI8EQI[18]\ : NOR3A - port map(A => un1_data_in_validlt30_10, B => - \counter_points_snapshot[19]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un1_data_in_validlt30_20); - - \counter_points_snapshot_RNII6BN1[9]\ : MX2C - port map(A => I_52_4, B => - \counter_points_snapshot[9]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[22]\); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => N_27, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[22]_net_1\); - - \counter_points_snapshot_RNI57D9[24]\ : NOR2 - port map(A => \counter_points_snapshot[24]_net_1\, B => - \counter_points_snapshot[25]_net_1\, Y => - un1_data_in_validlt30_12); - - \data_out_RNO[86]\ : NOR2B - port map(A => sample_f1_57, B => data_shaping_R1_0, Y => - \sample_f1_wdata[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2B - port map(A => N531, B => N380, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => N_47_0, - Y => ADD_32x32_fast_I304_Y_0_0); - - \data_out[101]\ : DFN1C0 - port map(D => \sample_f1_wdata[37]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(101)); - - \counter_points_snapshot_RNINKBE4[31]\ : OA1B - port map(A => \counter_points_snapshot[31]_net_1\, B => - un1_data_in_validlto30_i, C => start_snapshot_f1, Y => - N_59); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f1_wdata_93, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_88, Y => - \counter_points_snapshot_10[4]\); - - \counter_points_snapshot_RNI37D9[14]\ : NOR2 - port map(A => \counter_points_snapshot[14]_net_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - un1_data_in_validlt30_7); - - \counter_points_snapshot_RNO[30]\ : XA1C - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - N_52, Y => N_43); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : AO1 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => N_47, Y => N497); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR3 - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N572, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[25]\, C => N_47_1, Y => - ADD_32x32_fast_I134_Y_0); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f1_wdata_6, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => I_24_4, B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => N_60, Y => N_89); - - \data_out[84]\ : DFN1C0 - port map(D => \sample_f1_wdata[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => \sample_f1_wdata[39]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I7_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[24]\, B => N_47, - Y => N401); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : AO1 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[27]\, C => N_47, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - N_52, Y => N_35); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f1_wdata_15, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \counter_points_snapshot_RNITC8P[12]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f1_wdata_80, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(144)); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0 : OR3B - port map(A => start_snapshot_f1, B => sample_f1_val_0, C - => burst_f1, Y => counter_points_snapshot_0_sqmuxa_1_0); - - \data_out_RNO[89]\ : NOR2B - port map(A => sample_f1_54, B => data_shaping_R1_0, Y => - \sample_f1_wdata[25]\); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_92, Y => - \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => \sample_f1_wdata[47]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(111)); - - \counter_points_snapshot_RNID7E9[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un1_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2A - port map(A => \un1_counter_points_snapshot[31]\, B => - N_47_1, Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f1_wdata_78, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f1_wdata_14, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - N_52, Y => N_29); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : OR2A - port map(A => N580, B => N572, Y => N636); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_1 : AO1A - port map(A => N_47_0, B => - \un1_counter_points_snapshot[23]\, C => N401, Y => - ADD_32x32_fast_I134_Y_1); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => I_13_20, B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => N_60, Y => N_87); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => N_35, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => N_47_0, - Y => ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : NOR3 - port map(A => N479, B => N483, C => N550, Y => - ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I1_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[30]\, B => - N_47_1, Y => N383); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f1_wdata_57, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : AO1A - port map(A => N_47_1, B => - \un1_counter_points_snapshot[15]\, C => N425, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_84, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f1_wdata_67, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f1_wdata_49, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(113)); - - \counter_points_snapshot_RNIS4KA1[5]\ : MX2C - port map(A => I_24_4, B => - \counter_points_snapshot[5]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[26]\); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f1_wdata_81, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(145)); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f1_wdata_2, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[1]_net_1\); - - \counter_points_snapshot_RNO[31]\ : XA1B - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - N_52, Y => N_45); - - \data_out_RNO[109]\ : MX2 - port map(A => sample_f1_2, B => sample_f1_34, S => - data_shaping_R1, Y => \sample_f1_wdata[45]\); - - \counter_points_snapshot_RNO_0[0]\ : MX2B - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => N_60, Y => N_84); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N771_i, B => ADD_32x32_fast_I295_Y_0_0, C => - N_52, Y => N_13); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f1_wdata_59, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(123)); - - GND_i_0 : GND - port map(Y => GND_0); - - \counter_points_snapshot_RNILDVG1[7]\ : MX2C - port map(A => I_38_4, B => - \counter_points_snapshot[7]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[24]\); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f1_wdata_69, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : OR3B - port map(A => \counter_points_snapshot[21]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N443); - - \counter_points_snapshot_RNO[29]\ : XA1C - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - N_52, Y => N_41); - - \counter_points_snapshot_RNI5OT25_1[31]\ : OR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => N_45, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : AO1C - port map(A => N_47, B => \un1_counter_points_snapshot[4]\, - C => N464, Y => N479); - - \counter_points_snapshot_RNI1P8P[25]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - \data_out_RNO[97]\ : MX2 - port map(A => sample_f1_14, B => sample_f1_46, S => - data_shaping_R1_0, Y => \sample_f1_wdata[33]\); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f1_wdata_10, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(74)); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_94, Y => - \counter_points_snapshot_10[10]\); - - \data_out[108]\ : DFN1C0 - port map(D => \sample_f1_wdata[44]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[6]\, B => - I_31_5, S => counter_points_snapshot_2_sqmuxa, Y => N_90); - - \counter_points_snapshot_RNIF5QQ[0]\ : MX2A - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[31]\); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f1_wdata_92, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(156)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_Y : OR3B - port map(A => N580, B => N588, C => N533, Y => N786); - - \data_out_RNO[106]\ : MX2 - port map(A => sample_f1_5, B => sample_f1_37, S => - data_shaping_R1, Y => \sample_f1_wdata[42]\); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => I_45_4, B => - \un1_data_out_valid_0_sqmuxa_2[8]\, S => N_60, Y => N_92); - - \data_out_RNO[80]\ : NOR2B - port map(A => sample_f1_63, B => data_shaping_R1, Y => - \sample_f1_wdata[16]\); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_85, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_0, - Y => ADD_32x32_fast_I303_Y_0_0); - - \counter_points_snapshot_RNIT6C9[20]\ : NOR2 - port map(A => \counter_points_snapshot[20]_net_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - un1_data_in_validlt30_10); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : AOI1 - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[5]\, C => N_47, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - OR2 - port map(A => N756, B => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - N_52, Y => N_27); - - \data_out_RNO[88]\ : NOR2B - port map(A => sample_f1_55, B => data_shaping_R1_0, Y => - \sample_f1_wdata[24]\); - - \counter_points_snapshot_RNIQTOI[10]\ : NOR3A - port map(A => un1_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un1_data_in_validlt30_18); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I146_Y : NOR2 - port map(A => N533, B => N529, Y => N592); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => N_7, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => N_31, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[24]_net_1\); - - \counter_points_snapshot_RNI6H9N[0]\ : NOR3C - port map(A => un1_data_in_validlt30_2, B => - un1_data_in_validlt30_1, C => un1_data_in_validlt30_15, Y - => un1_data_in_validlt30_23); - - \data_out[95]\ : DFN1C0 - port map(D => \sample_f1_wdata[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(95)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR2B - port map(A => ADD_32x32_fast_I126_Y_1, B => - ADD_32x32_fast_I126_Y_0, Y => N572); - - \data_out_RNO[110]\ : MX2 - port map(A => sample_f1_1, B => sample_f1_33, S => - data_shaping_R1, Y => \sample_f1_wdata[46]\); - - \counter_points_snapshot_RNIVMC9[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un1_data_in_validlt30_6); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[9]\, B => - I_52_4, S => counter_points_snapshot_2_sqmuxa, Y => N_93); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : OA1C - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N419, Y => ADD_32x32_fast_I126_Y_1); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_87, Y => - \counter_points_snapshot_10[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[27]\, C => N_47_1, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f1_wdata_54, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(118)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR2A - port map(A => N380, B => N646, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[5]\, B => N_47_0, - Y => ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : NOR3B - port map(A => N467, B => N464, C => N481, Y => - ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2A - port map(A => N642, B => N594, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[24]\, C => N650, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[25]\, C => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - AO1C - port map(A => N_47, B => \un1_counter_points_snapshot[8]\, - C => N446, Y => N489); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[20]\, C => N783, Y => - \un1_data_out_valid_0_sqmuxa_2[11]\); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f1_wdata_64, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(128)); - - \counter_points_snapshot_RNO[11]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_95, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => \sample_f1_wdata[33]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f1_wdata_74, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(138)); - - \data_out_RNO[84]\ : NOR2B - port map(A => sample_f1_59, B => data_shaping_R1_0, Y => - \sample_f1_wdata[20]\); - - \data_out[85]\ : DFN1C0 - port map(D => \sample_f1_wdata[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[3]_net_1\); - - \data_out_RNO[85]\ : NOR2B - port map(A => sample_f1_58, B => data_shaping_R1_0, Y => - \sample_f1_wdata[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => \sample_f1_wdata[45]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(109)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : OA1C - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[20]\, C => N_47, Y => N511); - - \data_out_RNO[111]\ : MX2 - port map(A => sample_f1_0, B => sample_f1_32, S => - data_shaping_R1, Y => \sample_f1_wdata[47]\); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => N_29, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => N_25, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : OR3 - port map(A => N485, B => N489, C => N556, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f1_wdata_83, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(147)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f1_wdata_87, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(151)); - - \data_out_RNO[83]\ : NOR2B - port map(A => sample_f1_60, B => data_shaping_R1_0, Y => - \sample_f1_wdata[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - N_47_0, Y => ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[28]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => \sample_f1_wdata[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(87)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f1_wdata_89, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(153)); - - \counter_points_snapshot_RNI499P[19]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[28]\, C => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR3 - port map(A => N636, B => N620, C => N652, Y => N756); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AO1D - port map(A => \un1_counter_points_snapshot[28]\, B => N_47, - C => N386, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : NOR2 - port map(A => ADD_32x32_fast_I142_Y_0, B => N529, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => N_47_0, - Y => ADD_32x32_fast_I307_Y_0_0); - - \data_out_RNO[91]\ : NOR2B - port map(A => sample_f1_52, B => data_shaping_R1_0, Y => - \sample_f1_wdata[27]\); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f1_wdata_55, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : NOR3B - port map(A => N467, B => N470, C => N479, Y => - ADD_32x32_fast_I250_Y_1); - - \counter_points_snapshot_RNI5OT25[31]\ : OR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_1); - - \data_out_RNO[102]\ : MX2 - port map(A => sample_f1_9, B => sample_f1_41, S => - data_shaping_R1, Y => \sample_f1_wdata[38]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AOI1 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[21]\, C => N_47, Y => N515); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[7]\, B => - I_38_4, S => counter_points_snapshot_2_sqmuxa, Y => N_91); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_93, Y => - \counter_points_snapshot_10[9]\); - - \counter_points_snapshot_RNI5OT25_0[31]\ : OR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_0); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f1_wdata_5, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f1_wdata_65, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I251_Y_1, B => N485, C => N489, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f1_wdata_75, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => N_33, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[25]_net_1\); - - \data_out_RNO[82]\ : NOR2B - port map(A => sample_f1_61, B => data_shaping_R1, Y => - \sample_f1_wdata[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : NOR2 - port map(A => ADD_32x32_fast_I134_Y_1, B => - ADD_32x32_fast_I134_Y_0, Y => N580); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - OA1C - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N783, Y => N780); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : OR2A - port map(A => N380, B => N383, Y => N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : OA1C - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[7]\, C => N_47, Y => N485); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f1_wdata_11, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(75)); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f1_wdata_4, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(68)); - - \counter_points_snapshot_RNO_0[11]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[11]\, B => N_4, - S => counter_points_snapshot_2_sqmuxa, Y => N_95); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : OAI1 - port map(A => N_47, B => \un1_counter_points_snapshot[12]\, - C => N440, Y => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OR3 - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N556, Y => N620); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : NOR3A - port map(A => N380, B => N646, C => N630, Y => N766); - - \counter_points_snapshot_RNIVG8P[23]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - \counter_points_snapshot_RNO[16]\ : XA1C - port map(A => N768, B => ADD_32x32_fast_I296_Y_0_0, C => - N_52, Y => N_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : NOR3A - port map(A => N566, B => I112_un1_Y, C => N495, Y => N622_i); - - \counter_points_snapshot_RNI8NPD1[6]\ : MX2C - port map(A => I_31_5, B => - \counter_points_snapshot[6]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[25]\); - - data_out_valid_RNO : OA1A - port map(A => N_59, B => burst_f1, C => - data_out_valid_9_i_0, Y => N_49); - - \data_out[100]\ : DFN1C0 - port map(D => \sample_f1_wdata[36]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : OR3A - port map(A => N642, B => N594, C => N626, Y => N762); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : OR2 - port map(A => N481, B => N485, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f1_wdata_13, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f1_wdata_82, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_86, Y => - \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : NOR2 - port map(A => N582, B => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1B - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - N_52, Y => N_9); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f1_wdata_94, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(158)); - - \data_out_RNO[105]\ : MX2 - port map(A => sample_f1_6, B => sample_f1_38, S => - data_shaping_R1, Y => \sample_f1_wdata[41]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I2_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[29]\, B => N_47, - Y => N386); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f1_wdata_0, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(64)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_controler is - - port( delta_f2_f0 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - start_snapshot_f2 : out std_logic; - start_snapshot_f1 : out std_logic; - start_snapshot_f0 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_f0_val_0 : in std_logic; - sample_f2_val : in std_logic; - coarse_time_0_c : in std_logic - ); - -end lpp_waveform_snapshot_controler; - -architecture DEF_ARCH of lpp_waveform_snapshot_controler is - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AXOI2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_34, N_80, \counter_delta_f0[26]_net_1\, N_57_0, - N_265, \counter_delta_f0[19]_net_1\, N_105, - counter_delta_f0_n19, N_106, N_57, counter_delta_f0_n20, - \counter_delta_f0[20]_net_1\, N_89, - \counter_delta_f0[0]_net_1\, \counter_delta_f0[1]_net_1\, - \counter_delta_f0[2]_net_1\, N_99, N_67, - \counter_delta_f0[11]_net_1\, - \counter_delta_f0[12]_net_1\, N_101, - \counter_delta_f0[13]_net_1\, - \counter_delta_f0[14]_net_1\, N_103, - \counter_delta_f0[15]_net_1\, - \counter_delta_f0[16]_net_1\, - \counter_delta_f0[17]_net_1\, - \counter_delta_f0[18]_net_1\, N_276, N_58, - \counter_delta_f0[21]_net_1\, N_277, N_86_i, N_28, N_62, - \counter_delta_f0[23]_net_1\, N_30, N_98_i, N_32, N_66, - \counter_delta_f0[25]_net_1\, - \counter_delta_f0[22]_net_1\, - \counter_delta_f0[24]_net_1\, N_63, - \counter_delta_f0[9]_net_1\, \counter_delta_f0[10]_net_1\, - N_59, \counter_delta_f0[7]_net_1\, - \counter_delta_f0[8]_net_1\, N_55, - \counter_delta_f0[5]_net_1\, \counter_delta_f0[6]_net_1\, - \counter_delta_f0[3]_net_1\, \counter_delta_f0[4]_net_1\, - un2_coarse_time_0_0, \coarse_time_0_r\, N_504_0, - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, N_9_0, - N_9_tz, N_7, \start_snapshot_fothers_temp\, - counter_delta_snapshot_e27_0_0_o2_N_7_0, - \counter_delta_snapshot_e27_0_0_o2_m6_e_3\, - counter_delta_snapshot_e27_0_0_o2_m6_e_2, N_398, - start_snapshot_f22_0_a2_11_0_a2_3_i, - \counter_delta_snapshot[23]_net_1\, - \counter_delta_snapshot[22]_net_1\, - start_snapshot_f22_0_a2_11_0_a2_2_i, - \counter_delta_snapshot[19]_net_1\, - \counter_delta_snapshot[18]_net_1\, N_495, - \counter_delta_snapshot[12]_net_1\, - start_snapshot_f2_temp3_0_a2_0, start_snapshot_f22_11_i, - start_snapshot_f22_10, start_snapshot_f22_0_a2_1, - start_snapshot_f22_0_a2_0, - start_snapshot_f22_0_a2_11_0_a2_2_0, - un12_start_snapshot_fothers_temp_NE, - un12_start_snapshot_fothers_temp_NE_12, - un12_start_snapshot_fothers_temp_NE_13, N_493, - \counter_delta_snapshot_e12_i_0_a2_0\, - start_snapshot_f2_temp3, counter_delta_snapshot_e12_i_0_0, - counter_delta_snapshot_e25_0_0_0, - \counter_delta_snapshot[25]_net_1\, N_421, - counter_delta_snapshot_e25_0_0_a2_0, - counter_delta_snapshot_e23_0_0_0, N_189, - counter_delta_snapshot_e8_i_0, - counter_delta_snapshot_e8_i_a2_0, N_466, - counter_delta_snapshot_e2_i_0, - counter_delta_snapshot_e2_i_a2_0, N_436, - counter_delta_snapshot_e3_i_0, - \counter_delta_snapshot[3]_net_1\, N_440, - counter_delta_snapshot_e6_i_0, - \counter_delta_snapshot[6]_net_1\, N_455, - counter_delta_snapshot_e7_i_0, - \counter_delta_snapshot[7]_net_1\, N_460, - counter_delta_snapshot_e9_i_0, - counter_delta_snapshot_e9_i_a2_0, N_470, - counter_delta_snapshot_e15_i_0_0, - \counter_delta_snapshot[15]_net_1\, N_478, - counter_delta_snapshot_e14_i_0_0, - \counter_delta_snapshot[14]_net_1\, N_484, - counter_delta_snapshot_e13_i_0_0, - \counter_delta_snapshot[13]_net_1\, N_285, - counter_delta_snapshot_e4_i_0, - \counter_delta_snapshot[4]_net_1\, N_445, - counter_delta_snapshot_e5_i_0, - \counter_delta_snapshot_i[5]\, N_450, - counter_delta_snapshot_e11_i_0_0, - counter_delta_snapshot_e11_i_0_a2_0, N_294, - counter_delta_snapshot_e0_i_0, - \counter_delta_snapshot[0]_net_1\, - counter_delta_snapshot_e10_i_0, - \counter_delta_snapshot[10]_net_1\, N_474, - counter_delta_f0_n18_0_0_a2_0, - counter_delta_snapshot_e16_i_i_0, - \counter_delta_snapshot[16]_net_1\, N_168, - counter_delta_snapshot_e19_i_i_0, - counter_delta_snapshot_e19_i_i_a2_0, N_178, - counter_delta_snapshot_e21_0_0_0, - \counter_delta_snapshot[21]_net_1\, un2_coarse_time_0, - N_183, counter_delta_snapshot_e13_i_0_a2_2_0, N_393, - counter_delta_snapshot_e23_0_0_a2_0, - counter_delta_f0_n16_0_0_a2_0, - counter_delta_snapshot_e21_0_0_a2_0, - \counter_delta_snapshot_RNI0DDG1[7]_net_1\, - \counter_delta_snapshot[8]_net_1\, N_388, - \counter_delta_snapshot[2]_net_1\, N_382, - counter_delta_snapshot_e6_i_a2_0, N_386, - counter_delta_snapshot_e7_i_a2_0, N_387, - \counter_delta_snapshot[9]_net_1\, N_389, - counter_delta_snapshot_e15_i_0_a2_0, N_395, - counter_delta_snapshot_e14_i_0_a2_0, N_394, - counter_delta_snapshot_e13_i_0_a2_0, - counter_delta_snapshot_e16_i_i_a2_0, N_396, - counter_delta_snapshot_e4_i_a2_0, N_384, - counter_delta_snapshot_e5_i_a2_0, N_385, - \counter_delta_snapshot_i[11]\, N_391, - counter_delta_f0_n14_0_0_a2_0, - \counter_delta_snapshot_e27_0_0_o2_m6_e_1\, - start_snapshot_f22_0_a2_11_0_a2_1, - \counter_delta_snapshot[26]_net_1\, - \counter_delta_snapshot[24]_net_1\, - counter_delta_f0_n12_0_0_a2_0, counter_delta_f0_n10_0_i_0, - counter_delta_f0lde_i_a2_0_1_3, - counter_delta_f0lde_i_a2_0_1_2, counter_delta_f0_1_0_a2_7, - N_273, counter_delta_f0_1_0_a2_2_0, - start_snapshot_f12_0_a2_7, start_snapshot_f12_0_a2_1, - start_snapshot_f12_0_a2_0, start_snapshot_f12_0_a2_4, - start_snapshot_f12_0_a2_6, N_113_i_i_0, N_112_i_i_0, - start_snapshot_f12_0_a2_3, N_108_i_i_0, N_83_i_i_0, - N_111_i_i_0, N_82_i_i_0, \start_snapshot_f2_temp\, - counter_delta_snapshot_e12_i_0_o2_m6_e_6, - counter_delta_snapshot_e12_i_0_o2_m6_e_4, - counter_delta_snapshot_e12_i_0_o2_m6_e_5, - counter_delta_snapshot_e12_i_0_o2_m6_e_2, - un12_start_snapshot_fothers_temp_NE_5, - un12_start_snapshot_fothers_temp_NE_4, - un12_start_snapshot_fothers_temp_NE_11, - un12_start_snapshot_fothers_temp_NE_1, - un12_start_snapshot_fothers_temp_NE_0, - un12_start_snapshot_fothers_temp_NE_9, N_506_i, N_166_i_i, - un12_start_snapshot_fothers_temp_NE_7, N_133_i_i, - N_132_i_i, un12_start_snapshot_fothers_temp_NE_3, N_509_i, - N_164_i_i, N_510_i, N_135_i_i, - un12_start_snapshot_fothers_temp_NE_RNO_8, N_137_i_i, - counter_delta_f0_1_0_a2_12, counter_delta_f0_1_0_a2_1_0, - counter_delta_f0_1_0_a2_9, counter_delta_f0_1_0_a2_11, - counter_delta_f0_1_0_a2_6, counter_delta_f0_1_0_a2_5, - counter_delta_f0_1_0_a2_10, counter_delta_f0_1_0_a2_5_0, - counter_delta_f0_1_0_a2_0, N_272, - counter_delta_f0_1_0_a2_8_0, counter_delta_f0_1_0_a2_8_1, - counter_delta_f0_1_0_a2_3, counter_delta_f0_1_0_a2_2, - un1_start_snapshot_f22_i_a2_0_4, - un1_start_snapshot_f22_i_a2_0_3, - start_snapshot_f22_0_a2_11_0_a2_0, - \counter_delta_snapshot[17]_net_1\, start_snapshot_f12, - N_322, N_19, N_275, N_22_i_0, N_503, N_501, N_26, N_287, - N_288, N_6, N_486, N_488, N_8, N_480, N_482, - \counter_delta_snapshot_RNO[10]_net_1\, N_476, N_477, - \counter_delta_snapshot_RNO[9]_net_1\, N_471, N_472, - \counter_delta_snapshot_RNO[7]_net_1\, N_462, N_463, - \counter_delta_snapshot_RNO[6]_net_1\, N_457, N_458, - N_376_i_0, N_453, N_452, N_375_i_0, N_448, N_447, - \counter_delta_snapshot_RNO[3]_net_1\, N_442, N_443, N_54, - N_437, N_438, \counter_delta_snapshot_RNO[1]_net_1\, - N_433, counter_delta_snapshot_e1_i_0, N_435, N_263, N_259, - N_255, N_252, \counter_delta_snapshot_RNO[0]_net_1\, - N_505, counter_delta_snapshot_e24, N_192, N_193, N_194, - counter_delta_snapshot_e23, N_404, - counter_delta_snapshot_e22, N_186, N_187, N_188, - counter_delta_snapshot_e21, N_402, - \counter_delta_snapshot_RNO[20]_net_1\, N_180, N_181, - N_182, N_20, N_400, - \counter_delta_snapshot_RNO[17]_net_1\, N_171, N_172, - N_173, \counter_delta_snapshot_RNO[16]_net_1\, N_397, - N_390, N_504, N_383, \counter_delta_snapshot[1]_net_1\, - \counter_delta_snapshot[20]_net_1\, counter_delta_f0_1, - N_174, N_405, N_468, N_498, - \counter_delta_snapshot_RNO[18]_net_1\, N_175, N_176, - counter_delta_snapshot_e25, N_406, - \counter_delta_snapshot_RNO[8]_net_1\, N_467, - \counter_delta_snapshot_RNO[12]_net_1\, N_496, N_284, - counter_delta_snapshot_e26_0_0_0_tz, N_9, - counter_delta_snapshot_e26, N_425, N_21, N_23, N_107_i_i, - N_227, N_114_i_i, N_228, N_115_i_i, counter_delta_f0_n12, - counter_delta_f0_n13, counter_delta_f0_n14, - counter_delta_f0_n15, counter_delta_f0_n16, - counter_delta_f0_n17, counter_delta_f0_n18, N_11, - N_87_i_i, N_17, N_324_i, N_99_i_i, N_89_i_i, N_15, N_13, - N_117_i_i, N_116_i_i, N_230, N_229, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - - \counter_delta_snapshot_RNO_1[11]\ : AOI1B - port map(A => counter_delta_snapshot_e11_i_0_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_294, Y - => counter_delta_snapshot_e11_i_0_0); - - \counter_delta_snapshot_RNO[21]\ : OAI1 - port map(A => N_402, B => N_504_0, C => - counter_delta_snapshot_e21_0_0_0, Y => - counter_delta_snapshot_e21); - - \counter_delta_snapshot[19]\ : DFN1C0 - port map(D => N_20, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[19]_net_1\); - - start_snapshot_f0_RNO_1 : NOR3A - port map(A => counter_delta_f0_1_0_a2_5_0, B => - counter_delta_f0_1_0_a2_0, C => N_272, Y => - counter_delta_f0_1_0_a2_10); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_6\ : NOR3C - port map(A => N_133_i_i, B => N_132_i_i, C => - un12_start_snapshot_fothers_temp_NE_3, Y => - un12_start_snapshot_fothers_temp_NE_9); - - \counter_delta_f0_RNO[14]\ : AO1C - port map(A => N_101, B => N_57_0, C => N_255, Y => - counter_delta_f0_n14); - - \op_eq.start_snapshot_f2_temp3_0_a2_RNO\ : OR2 - port map(A => start_snapshot_f22_11_i, B => - start_snapshot_f22_10, Y => - start_snapshot_f2_temp3_0_a2_0); - - \counter_delta_snapshot_RNO_0[17]\ : OR3C - port map(A => N_397, B => - \counter_delta_snapshot[17]_net_1\, C => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_171); - - \counter_delta_snapshot_RNIP067[1]\ : NOR2 - port map(A => \counter_delta_snapshot[1]_net_1\, B => - \counter_delta_snapshot[0]_net_1\, Y => N_382); - - \counter_delta_f0_RNITCA8[6]\ : NOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => - \counter_delta_f0[6]_net_1\, Y => - counter_delta_f0_1_0_a2_7); - - \counter_delta_snapshot_RNO_5[13]\ : OR2 - port map(A => \counter_delta_snapshot[13]_net_1\, B => - N_393, Y => counter_delta_snapshot_e13_i_0_a2_0); - - \counter_delta_snapshot_RNIKDF23[19]\ : OR3 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot[19]_net_1\, Y => N_400); - - coarse_time_0_r_RNIGJTR4_0 : OR2B - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => un2_coarse_time_0, Y => N_504); - - \counter_delta_snapshot_RNIV4TS1[13]\ : NOR2A - port map(A => N_393, B => - \counter_delta_snapshot[13]_net_1\, Y => N_394); - - \counter_delta_snapshot_RNO[19]\ : OAI1 - port map(A => N_400, B => N_504_0, C => - counter_delta_snapshot_e19_i_i_0, Y => N_20); - - \counter_delta_snapshot_RNO_1[2]\ : AO1A - port map(A => counter_delta_snapshot_e2_i_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_436, Y - => counter_delta_snapshot_e2_i_0); - - \counter_delta_f0_RNO[11]\ : XA1A - port map(A => N_67, B => \counter_delta_f0[11]_net_1\, C - => N_57_0, Y => N_275); - - \counter_delta_f0_RNO_0[4]\ : AX1B - port map(A => N_89, B => \counter_delta_f0[3]_net_1\, C => - \counter_delta_f0[4]_net_1\, Y => N_116_i_i); - - \counter_delta_f0_RNILJOA[20]\ : NOR3 - port map(A => \counter_delta_f0[14]_net_1\, B => - \counter_delta_f0[15]_net_1\, C => - \counter_delta_f0[20]_net_1\, Y => - counter_delta_f0_1_0_a2_3); - - \counter_delta_snapshot_RNO_1[12]\ : OR2 - port map(A => N_493, B => N_495, Y => - counter_delta_snapshot_e12_i_0_0); - - \counter_delta_snapshot_RNIIDER3[23]\ : OR3 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => - \counter_delta_snapshot[23]_net_1\, Y => N_404); - - \counter_delta_f0_RNO[26]\ : XA1 - port map(A => N_80, B => \counter_delta_f0[26]_net_1\, C - => N_57_0, Y => N_34); - - \counter_delta_snapshot_RNO_1[19]\ : OA1 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot[19]_net_1\, Y => - counter_delta_snapshot_e19_i_i_a2_0); - - coarse_time_0_r_RNILJMD : NOR2A - port map(A => coarse_time_0_c, B => \coarse_time_0_r\, Y - => un2_coarse_time_0); - - \counter_delta_snapshot_RNO[5]\ : OR3C - port map(A => N_453, B => counter_delta_snapshot_e5_i_0, C - => N_452, Y => N_376_i_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_11\ : XNOR2 - port map(A => \counter_delta_snapshot[3]_net_1\, B => - delta_snapshot(3), Y => N_506_i); - - \counter_delta_snapshot[16]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[16]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[16]_net_1\); - - \counter_delta_snapshot_RNIRV6E4_0[23]\ : OR3B - port map(A => \counter_delta_snapshot_e27_0_0_o2_m6_e_3\, B - => counter_delta_snapshot_e27_0_0_o2_m6_e_2, C => N_398, - Y => counter_delta_snapshot_e27_0_0_o2_N_7_0); - - \counter_delta_snapshot_RNO_0[20]\ : OR3C - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_180); - - \counter_delta_snapshot_RNIS3OS[7]\ : NOR2A - port map(A => N_387, B => \counter_delta_snapshot[7]_net_1\, - Y => N_388); - - start_snapshot_f22_0_a2_RNO : OR2 - port map(A => start_snapshot_f22_0_a2_0, B => - start_snapshot_f22_11_i, Y => start_snapshot_f22_0_a2_1); - - \counter_delta_snapshot_RNO_1[16]\ : OR2B - port map(A => counter_delta_snapshot_e16_i_i_a2_0, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_168); - - \counter_delta_snapshot_RNO_0[10]\ : NOR2 - port map(A => N_505, B => delta_snapshot(10), Y => N_476); - - \counter_delta_snapshot[25]\ : DFN1C0 - port map(D => counter_delta_snapshot_e25, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[25]_net_1\); - - \counter_delta_f0_RNO[7]\ : MX2 - port map(A => delta_f2_f0(7), B => N_89_i_i, S => N_57, Y - => N_13); - - \counter_delta_snapshot_RNO_2[13]\ : NOR2A - port map(A => counter_delta_snapshot_e13_i_0_a2_2_0, B => - N_504_0, Y => N_288); - - \counter_delta_snapshot_RNO_3[5]\ : OR2B - port map(A => counter_delta_snapshot_e5_i_a2_0, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_450); - - counter_delta_snapshot_e12_i_0_a2 : NOR2A - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => \counter_delta_snapshot_e12_i_0_a2_0\, Y => N_493); - - \counter_delta_snapshot[14]\ : DFN1C0 - port map(D => N_6, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[14]_net_1\); - - \counter_delta_snapshot_RNO_1[17]\ : OR2A - port map(A => \counter_delta_snapshot[17]_net_1\, B => - un2_coarse_time_0, Y => N_172); - - \counter_delta_f0[14]\ : DFN1E0C0 - port map(D => counter_delta_f0_n14, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[14]_net_1\); - - \counter_delta_snapshot_RNO_0[2]\ : NOR2 - port map(A => N_505, B => delta_snapshot(2), Y => N_437); - - \counter_delta_f0_RNO[18]\ : AO1B - port map(A => N_105, B => N_57, C => N_263, Y => - counter_delta_f0_n18); - - \counter_delta_snapshot_RNO[26]\ : AO1B - port map(A => counter_delta_snapshot_e26_0_0_0_tz, B => - \counter_delta_snapshot[26]_net_1\, C => N_425, Y => - counter_delta_snapshot_e26); - - \counter_delta_snapshot_RNO[17]\ : OR3C - port map(A => N_171, B => N_172, C => N_173, Y => - \counter_delta_snapshot_RNO[17]_net_1\); - - \counter_delta_snapshot[2]\ : DFN1C0 - port map(D => N_54, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[2]_net_1\); - - \counter_delta_f0_RNITVJ91[3]\ : NOR3A - port map(A => counter_delta_f0lde_i_a2_0_1_2, B => N_89, C - => \counter_delta_f0[3]_net_1\, Y => - counter_delta_f0lde_i_a2_0_1_3); - - \counter_delta_f0_RNIIVPK[4]\ : OR3 - port map(A => N_89, B => \counter_delta_f0[3]_net_1\, C => - \counter_delta_f0[4]_net_1\, Y => N_55); - - \counter_delta_snapshot_RNO_2[15]\ : NOR3B - port map(A => N_395, B => - \counter_delta_snapshot[15]_net_1\, C => N_504_0, Y => - N_482); - - \counter_delta_snapshot_RNI5NLF2[16]\ : OR2 - port map(A => \counter_delta_snapshot[16]_net_1\, B => - N_396, Y => N_397); - - \counter_delta_f0_RNIU25H2[20]\ : OR2 - port map(A => \counter_delta_f0[20]_net_1\, B => N_106, Y - => N_58); - - \counter_delta_snapshot_RNI71PA[2]\ : OR2A - port map(A => N_382, B => \counter_delta_snapshot[2]_net_1\, - Y => N_383); - - \counter_delta_snapshot_RNO_2[14]\ : NOR3B - port map(A => N_394, B => - \counter_delta_snapshot[14]_net_1\, C => N_504_0, Y => - N_488); - - \counter_delta_f0_RNO[20]\ : XA1A - port map(A => \counter_delta_f0[20]_net_1\, B => N_106, C - => N_57, Y => counter_delta_f0_n20); - - \counter_delta_snapshot_RNO_3[7]\ : NOR2A - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => counter_delta_snapshot_e7_i_a2_0, Y => N_460); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_5\ : NOR3C - port map(A => N_506_i, B => N_166_i_i, C => - un12_start_snapshot_fothers_temp_NE_7, Y => - un12_start_snapshot_fothers_temp_NE_11); - - \counter_delta_snapshot[21]\ : DFN1C0 - port map(D => counter_delta_snapshot_e21, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[21]_net_1\); - - \counter_delta_f0_RNIPJ57[22]\ : OR2 - port map(A => \counter_delta_f0[23]_net_1\, B => - \counter_delta_f0[22]_net_1\, Y => - counter_delta_f0_1_0_a2_2); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_15\ : XNOR2 - port map(A => \counter_delta_snapshot[12]_net_1\, B => - delta_snapshot(12), Y => N_132_i_i); - - \counter_delta_f0[15]\ : DFN1E0C0 - port map(D => counter_delta_f0_n15, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[15]_net_1\); - - \counter_delta_snapshot_RNO_2[11]\ : OR2 - port map(A => N_505, B => delta_snapshot(11), Y => N_501); - - \counter_delta_f0_RNIBRBK1[12]\ : OR3 - port map(A => N_67, B => \counter_delta_f0[11]_net_1\, C - => \counter_delta_f0[12]_net_1\, Y => N_99); - - \counter_delta_f0_RNI4JID2[19]\ : OR2A - port map(A => N_105, B => \counter_delta_f0[19]_net_1\, Y - => N_106); - - \counter_delta_snapshot_RNO[20]\ : OR3C - port map(A => N_180, B => N_181, C => N_182, Y => - \counter_delta_snapshot_RNO[20]_net_1\); - - \counter_delta_snapshot_RNO_1[10]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[10]_net_1\, C => N_474, Y => - counter_delta_snapshot_e10_i_0); - - \counter_delta_snapshot_RNO[25]\ : OAI1 - port map(A => N_406, B => N_504, C => - counter_delta_snapshot_e25_0_0_0, Y => - counter_delta_snapshot_e25); - - \op_eq.start_snapshot_f2_temp3_0_a2\ : NOR2 - port map(A => un12_start_snapshot_fothers_temp_NE, B => - start_snapshot_f2_temp3_0_a2_0, Y => - start_snapshot_f2_temp3); - - \counter_delta_f0_RNIDC4T[6]\ : OR3 - port map(A => N_55, B => \counter_delta_f0[5]_net_1\, C => - \counter_delta_f0[6]_net_1\, Y => N_59); - - \counter_delta_f0_RNO_0[14]\ : OAI1 - port map(A => N_99, B => \counter_delta_f0[13]_net_1\, C - => counter_delta_f0_n14_0_0_a2_0, Y => N_255); - - \counter_delta_snapshot_RNO[4]\ : NOR3C - port map(A => N_448, B => counter_delta_snapshot_e4_i_0, C - => N_447, Y => N_375_i_0); - - \counter_delta_snapshot[23]\ : DFN1C0 - port map(D => counter_delta_snapshot_e23, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[23]_net_1\); - - \counter_delta_snapshot_RNO_4[8]\ : NOR2 - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[8]_net_1\, Y => N_466); - - \counter_delta_snapshot_RNO[23]\ : OAI1 - port map(A => N_404, B => N_504_0, C => - counter_delta_snapshot_e23_0_0_0, Y => - counter_delta_snapshot_e23); - - \counter_delta_snapshot[17]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[17]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[17]_net_1\); - - \counter_delta_f0[4]\ : DFN1E0C0 - port map(D => N_229, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[4]_net_1\); - - \counter_delta_f0_RNIVJ67[16]\ : NOR2 - port map(A => \counter_delta_f0[16]_net_1\, B => - \counter_delta_f0[17]_net_1\, Y => - counter_delta_f0_1_0_a2_8_0); - - counter_delta_snapshot_e27_0_0_o2_m6_e_3 : NOR2 - port map(A => \counter_delta_snapshot[23]_net_1\, B => - \counter_delta_snapshot[22]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_3_i); - - \counter_delta_f0[13]\ : DFN1E0C0 - port map(D => counter_delta_f0_n13, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[13]_net_1\); - - \counter_delta_snapshot_RNO_2[12]\ : NOR3A - port map(A => \counter_delta_snapshot[12]_net_1\, B => - \counter_delta_snapshot_RNI0DDG1[7]_net_1\, C => N_504, Y - => N_498); - - \counter_delta_f0_RNO_0[10]\ : AX1D - port map(A => N_63, B => \counter_delta_f0[9]_net_1\, C => - \counter_delta_f0[10]_net_1\, Y => - counter_delta_f0_n10_0_i_0); - - \counter_delta_snapshot_RNO_2[19]\ : OR2A - port map(A => \counter_delta_snapshot[19]_net_1\, B => - un2_coarse_time_0, Y => N_178); - - \counter_delta_f0_RNO_0[3]\ : XNOR2 - port map(A => \counter_delta_f0[3]_net_1\, B => N_89, Y => - N_115_i_i); - - \counter_delta_f0_RNI4NHR1[14]\ : OR3 - port map(A => N_99, B => \counter_delta_f0[13]_net_1\, C - => \counter_delta_f0[14]_net_1\, Y => N_101); - - \counter_delta_snapshot_RNO_2[16]\ : NOR2B - port map(A => \counter_delta_snapshot[16]_net_1\, B => - N_396, Y => counter_delta_snapshot_e16_i_i_a2_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_13\ : XA1A - port map(A => delta_snapshot(6), B => - \counter_delta_snapshot[6]_net_1\, C => N_509_i, Y => - un12_start_snapshot_fothers_temp_NE_7); - - start_snapshot_fothers_temp : DFN1E0C0 - port map(D => N_7, CLK => HCLK_c, CLR => HRESETn_c, E => - N_284, Q => \start_snapshot_fothers_temp\); - - \counter_delta_snapshot_RNO_1[5]\ : OA1A - port map(A => \counter_delta_snapshot_i[5]\, B => - un2_coarse_time_0_0, C => N_450, Y => - counter_delta_snapshot_e5_i_0); - - \counter_delta_snapshot_RNO_2[17]\ : OR2 - port map(A => N_504, B => N_398, Y => N_173); - - \counter_delta_snapshot_RNO[7]\ : NOR3 - port map(A => N_462, B => counter_delta_snapshot_e7_i_0, C - => N_463, Y => \counter_delta_snapshot_RNO[7]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \counter_delta_snapshot[10]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[10]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[10]_net_1\); - - \counter_delta_f0_RNICPE51[8]\ : OR3 - port map(A => N_59, B => \counter_delta_f0[7]_net_1\, C => - \counter_delta_f0[8]_net_1\, Y => N_63); - - start_snapshot_f1_RNO_6 : XNOR2 - port map(A => \counter_delta_f0[4]_net_1\, B => - delta_f2_f1(4), Y => N_112_i_i_0); - - counter_delta_snapshot_e27_0_0_o2_m6_e_1_RNI4AT3 : AND2 - port map(A => start_snapshot_f22_0_a2_11_0_a2_3_i, B => - start_snapshot_f22_0_a2_11_0_a2_2_i, Y => - start_snapshot_f22_0_a2_11_0_a2_2_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_7\ : XNOR2 - port map(A => \counter_delta_snapshot[7]_net_1\, B => - delta_snapshot(7), Y => N_164_i_i); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \counter_delta_snapshot_RNO_0[6]\ : NOR2 - port map(A => N_505, B => delta_snapshot(6), Y => N_457); - - \counter_delta_f0_RNI3477[18]\ : NOR2 - port map(A => \counter_delta_f0[18]_net_1\, B => - \counter_delta_f0[19]_net_1\, Y => - counter_delta_f0_1_0_a2_8_1); - - \counter_delta_f0_RNI1DA8[8]\ : NOR2 - port map(A => \counter_delta_f0[8]_net_1\, B => - \counter_delta_f0[9]_net_1\, Y => - counter_delta_f0_1_0_a2_2_0); - - \counter_delta_snapshot[3]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[3]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[3]_net_1\); - - \counter_delta_f0_RNO_0[7]\ : XNOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => N_59, Y => - N_89_i_i); - - \counter_delta_f0_RNIU767[26]\ : OR2 - port map(A => \counter_delta_f0[26]_net_1\, B => - \counter_delta_f0[24]_net_1\, Y => - counter_delta_f0_1_0_a2_0); - - \counter_delta_snapshot_RNI2DD92[15]\ : OR2A - port map(A => N_395, B => - \counter_delta_snapshot[15]_net_1\, Y => N_396); - - \start_snapshot_f0\ : DFN1C0 - port map(D => counter_delta_f0_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => start_snapshot_f0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_3\ : XA1A - port map(A => delta_snapshot(2), B => - \counter_delta_snapshot[2]_net_1\, C => N_510_i, Y => - un12_start_snapshot_fothers_temp_NE_4); - - \counter_delta_snapshot[12]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[12]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[12]_net_1\); - - start_snapshot_f0_RNO_0 : NOR3B - port map(A => counter_delta_f0_1_0_a2_7, B => - counter_delta_f0_1_0_a2_6, C => counter_delta_f0_1_0_a2_5, - Y => counter_delta_f0_1_0_a2_11); - - \counter_delta_snapshot_RNO_0[0]\ : AXOI2 - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => un2_coarse_time_0_0, C => - \counter_delta_snapshot[0]_net_1\, Y => - counter_delta_snapshot_e0_i_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE\ : NAND2 - port map(A => un12_start_snapshot_fothers_temp_NE_12, B => - un12_start_snapshot_fothers_temp_NE_13, Y => - un12_start_snapshot_fothers_temp_NE); - - \counter_delta_snapshot_RNO_2[10]\ : NOR3A - port map(A => \counter_delta_snapshot[10]_net_1\, B => - N_390, C => N_504_0, Y => N_477); - - \counter_delta_snapshot_RNI0DDG1[7]\ : OR3B - port map(A => counter_delta_snapshot_e12_i_0_o2_m6_e_6, B - => counter_delta_snapshot_e12_i_0_o2_m6_e_5, C => N_383, - Y => \counter_delta_snapshot_RNI0DDG1[7]_net_1\); - - \counter_delta_f0_RNO[25]\ : XA1A - port map(A => N_66, B => \counter_delta_f0[25]_net_1\, C - => N_57, Y => N_32); - - \counter_delta_snapshot_RNO[12]\ : NOR3 - port map(A => N_496, B => counter_delta_snapshot_e12_i_0_0, - C => N_498, Y => \counter_delta_snapshot_RNO[12]_net_1\); - - start_snapshot_f2_temp : DFN1C0 - port map(D => start_snapshot_f2_temp3, CLK => HCLK_c, CLR - => HRESETn_c, Q => \start_snapshot_f2_temp\); - - \counter_delta_f0[20]\ : DFN1E0C0 - port map(D => counter_delta_f0_n20, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[20]_net_1\); - - start_snapshot_f1_RNO_7 : XA1A - port map(A => delta_f2_f1(2), B => - \counter_delta_f0[2]_net_1\, C => N_83_i_i_0, Y => - start_snapshot_f12_0_a2_3); - - \counter_delta_snapshot_RNO_4[13]\ : NOR2B - port map(A => \counter_delta_snapshot[13]_net_1\, B => - N_393, Y => counter_delta_snapshot_e13_i_0_a2_2_0); - - \counter_delta_snapshot_RNO_0[1]\ : NOR2 - port map(A => N_505, B => delta_snapshot(1), Y => N_433); - - \counter_delta_f0[17]\ : DFN1E0C0 - port map(D => counter_delta_f0_n17, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[17]_net_1\); - - \counter_delta_f0_RNO_0[26]\ : NOR2 - port map(A => \counter_delta_f0[25]_net_1\, B => N_66, Y - => N_80); - - \counter_delta_snapshot_RNO_4[15]\ : OR2 - port map(A => \counter_delta_snapshot[15]_net_1\, B => - N_395, Y => counter_delta_snapshot_e15_i_0_a2_0); - - counter_delta_snapshot_e12_i_0_a2_0 : NOR2 - port map(A => \counter_delta_snapshot[12]_net_1\, B => - un2_coarse_time_0_0, Y => N_495); - - \counter_delta_f0[2]\ : DFN1E0C0 - port map(D => N_227, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[2]_net_1\); - - \counter_delta_snapshot_RNO[18]\ : OR3C - port map(A => N_174, B => N_175, C => N_176, Y => - \counter_delta_snapshot_RNO[18]_net_1\); - - \counter_delta_snapshot_RNINLU74[25]\ : OR2A - port map(A => N_405, B => - \counter_delta_snapshot[25]_net_1\, Y => N_406); - - counter_delta_snapshot_e12_i_0_a2_RNO : OR2A - port map(A => \counter_delta_snapshot_RNI0DDG1[7]_net_1\, B - => \counter_delta_snapshot[12]_net_1\, Y => - \counter_delta_snapshot_e12_i_0_a2_0\); - - \counter_delta_f0_RNIJBBE[25]\ : NOR3 - port map(A => \counter_delta_f0[21]_net_1\, B => - \counter_delta_f0[25]_net_1\, C => - counter_delta_f0_1_0_a2_2, Y => - counter_delta_f0_1_0_a2_5_0); - - start_snapshot_f1_RNO_2 : XA1A - port map(A => delta_f2_f1(1), B => - \counter_delta_f0[1]_net_1\, C => N_111_i_i_0, Y => - start_snapshot_f12_0_a2_1); - - \counter_delta_snapshot_RNO_4[14]\ : OR2 - port map(A => \counter_delta_snapshot[14]_net_1\, B => - N_394, Y => counter_delta_snapshot_e14_i_0_a2_0); - - \counter_delta_f0[21]\ : DFN1E0C0 - port map(D => N_276, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[21]_net_1\); - - \counter_delta_f0_RNO[1]\ : MX2 - port map(A => delta_f2_f0(1), B => N_107_i_i, S => N_57_0, - Y => N_23); - - \counter_delta_snapshot_RNI9IOI_0[26]\ : NOR3 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - \counter_delta_snapshot[26]_net_1\, C => - \counter_delta_snapshot[24]_net_1\, Y => - \counter_delta_snapshot_e27_0_0_o2_m6_e_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_delta_snapshot_RNO_1[9]\ : AO1A - port map(A => counter_delta_snapshot_e9_i_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_470, Y - => counter_delta_snapshot_e9_i_0); - - \counter_delta_snapshot_RNO_4[2]\ : NOR2 - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[2]_net_1\, Y => N_436); - - start_snapshot_f0_RNO_4 : NOR2A - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[3]_net_1\, Y => - counter_delta_f0_1_0_a2_1_0); - - \counter_delta_snapshot_RNO_1[3]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[3]_net_1\, C => N_440, Y => - counter_delta_snapshot_e3_i_0); - - \counter_delta_snapshot_RNO_0[3]\ : NOR2 - port map(A => N_505, B => delta_snapshot(3), Y => N_442); - - \counter_delta_snapshot_RNI7OGC[16]\ : NOR2 - port map(A => \counter_delta_snapshot[16]_net_1\, B => - \counter_delta_snapshot[17]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_0); - - \counter_delta_snapshot_RNO_4[11]\ : OR2A - port map(A => \counter_delta_snapshot_i[11]\, B => - un2_coarse_time_0, Y => N_294); - - \counter_delta_snapshot_RNO_1[23]\ : OAI1 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => - counter_delta_snapshot_e23_0_0_a2_0, Y => N_189); - - \counter_delta_f0_RNIMF6D1[10]\ : OR3 - port map(A => N_63, B => \counter_delta_f0[9]_net_1\, C => - \counter_delta_f0[10]_net_1\, Y => N_67); - - \counter_delta_snapshot_RNIKFM14[24]\ : NOR2 - port map(A => \counter_delta_snapshot[24]_net_1\, B => - N_404, Y => N_405); - - \counter_delta_f0_RNO[16]\ : AO1C - port map(A => N_103, B => N_57, C => N_259, Y => - counter_delta_f0_n16); - - \counter_delta_f0_RNIRALB3[3]\ : AO1B - port map(A => counter_delta_f0lde_i_a2_0_1_3, B => N_322, C - => sample_f0_val_0, Y => N_9_tz); - - \counter_delta_f0_RNO[8]\ : MX2 - port map(A => delta_f2_f0(8), B => N_99_i_i, S => N_57, Y - => N_15); - - \counter_delta_snapshot_RNO_1[25]\ : OR2 - port map(A => counter_delta_snapshot_e25_0_0_a2_0, B => - N_405, Y => N_421); - - start_snapshot_f1_RNO_8 : XNOR2 - port map(A => \counter_delta_f0[3]_net_1\, B => - delta_f2_f1(3), Y => N_111_i_i_0); - - \counter_delta_snapshot_RNO[2]\ : NOR3 - port map(A => N_437, B => counter_delta_snapshot_e2_i_0, C - => N_438, Y => N_54); - - \counter_delta_snapshot[26]\ : DFN1C0 - port map(D => counter_delta_snapshot_e26, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[26]_net_1\); - - \start_snapshot_f1\ : DFN1C0 - port map(D => start_snapshot_f12, CLK => HCLK_c, CLR => - HRESETn_c, Q => start_snapshot_f1); - - \counter_delta_snapshot_RNIM1CE[3]\ : OR2 - port map(A => \counter_delta_snapshot[3]_net_1\, B => N_383, - Y => N_384); - - \counter_delta_snapshot_RNO_1[7]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[7]_net_1\, C => N_460, Y => - counter_delta_snapshot_e7_i_0); - - \counter_delta_snapshot_RNIV6LM1[12]\ : NOR2 - port map(A => \counter_delta_snapshot_RNI0DDG1[7]_net_1\, B - => \counter_delta_snapshot[12]_net_1\, Y => N_393); - - \counter_delta_f0_RNO[5]\ : MX2 - port map(A => delta_f2_f0(5), B => N_117_i_i, S => N_57, Y - => N_230); - - \counter_delta_snapshot_RNO_1[24]\ : OR2A - port map(A => \counter_delta_snapshot[24]_net_1\, B => - un2_coarse_time_0, Y => N_193); - - \counter_delta_snapshot_RNO[6]\ : NOR3 - port map(A => N_457, B => counter_delta_snapshot_e6_i_0, C - => N_458, Y => \counter_delta_snapshot_RNO[6]_net_1\); - - \counter_delta_snapshot[24]\ : DFN1C0 - port map(D => counter_delta_snapshot_e24, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[24]_net_1\); - - \counter_delta_snapshot_RNO_3[13]\ : NOR2A - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => counter_delta_snapshot_e13_i_0_a2_0, Y => N_285); - - \counter_delta_f0_RNO[4]\ : MX2 - port map(A => delta_f2_f0(4), B => N_116_i_i, S => N_57, Y - => N_229); - - \counter_delta_snapshot_RNO_3[3]\ : NOR3B - port map(A => N_383, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, C => - \counter_delta_snapshot[3]_net_1\, Y => N_440); - - \counter_delta_snapshot_RNI55U31[9]\ : OR2A - port map(A => N_389, B => \counter_delta_snapshot[9]_net_1\, - Y => N_390); - - \counter_delta_snapshot_RNO_1[21]\ : OAI1 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - counter_delta_snapshot_e21_0_0_a2_0, Y => N_183); - - start_snapshot_f1_RNO_9 : XNOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => - delta_f2_f1(7), Y => N_82_i_i_0); - - \counter_delta_snapshot_RNIG4B01[8]\ : NOR2A - port map(A => N_388, B => \counter_delta_snapshot[8]_net_1\, - Y => N_389); - - \counter_delta_f0[12]\ : DFN1E0C0 - port map(D => counter_delta_f0_n12, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[12]_net_1\); - - \counter_delta_f0_RNO_1[16]\ : NOR2B - port map(A => \counter_delta_f0[16]_net_1\, B => N_57_0, Y - => counter_delta_f0_n16_0_0_a2_0); - - \counter_delta_snapshot_RNO_3[15]\ : NOR2A - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => counter_delta_snapshot_e15_i_0_a2_0, Y => N_478); - - \counter_delta_snapshot_RNO_1[6]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[6]_net_1\, C => N_455, Y => - counter_delta_snapshot_e6_i_0); - - \counter_delta_f0_RNO[10]\ : NOR2A - port map(A => N_57_0, B => counter_delta_f0_n10_0_i_0, Y - => N_19); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_12\ : XNOR2 - port map(A => \counter_delta_snapshot[9]_net_1\, B => - delta_snapshot(9), Y => N_166_i_i); - - \counter_delta_snapshot_RNO_2[8]\ : NOR3B - port map(A => N_388, B => \counter_delta_snapshot[8]_net_1\, - C => N_504, Y => N_468); - - \counter_delta_f0_RNILRIL[10]\ : NOR3B - port map(A => counter_delta_f0_1_0_a2_8_0, B => - counter_delta_f0_1_0_a2_8_1, C => - counter_delta_f0_1_0_a2_5, Y => - un1_start_snapshot_f22_i_a2_0_3); - - \counter_delta_snapshot_RNO_3[14]\ : NOR2A - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => counter_delta_snapshot_e14_i_0_a2_0, Y => N_484); - - counter_delta_snapshot_e26_0_0_a2_1 : VCC - port map(Y => N_425); - - \counter_delta_f0[3]\ : DFN1E0C0 - port map(D => N_228, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[3]_net_1\); - - \counter_delta_snapshot_RNO_0[8]\ : NOR2 - port map(A => N_505, B => delta_snapshot(8), Y => N_467); - - \counter_delta_f0_RNI2VU92[18]\ : NOR3 - port map(A => N_103, B => \counter_delta_f0[17]_net_1\, C - => \counter_delta_f0[18]_net_1\, Y => N_105); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_10\ : XNOR2 - port map(A => \counter_delta_snapshot[1]_net_1\, B => - delta_snapshot(1), Y => N_137_i_i); - - \counter_delta_snapshot_RNO_0[4]\ : OR3A - port map(A => \counter_delta_snapshot[4]_net_1\, B => N_384, - C => N_504, Y => N_448); - - \counter_delta_f0_RNO_0[8]\ : AX1B - port map(A => N_59, B => \counter_delta_f0[7]_net_1\, C => - \counter_delta_f0[8]_net_1\, Y => N_99_i_i); - - \counter_delta_f0[24]\ : DFN1E0C0 - port map(D => N_30, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[24]_net_1\); - - \counter_delta_snapshot_RNO_1[22]\ : OR2A - port map(A => \counter_delta_snapshot[22]_net_1\, B => - un2_coarse_time_0, Y => N_187); - - \counter_delta_f0_RNO[23]\ : XA1A - port map(A => N_62, B => \counter_delta_f0[23]_net_1\, C - => N_57, Y => N_28); - - \counter_delta_snapshot_RNO_3[11]\ : NOR2B - port map(A => \counter_delta_snapshot_i[11]\, B => N_391, Y - => counter_delta_snapshot_e11_i_0_a2_0); - - \counter_delta_snapshot_RNO_2[1]\ : NOR3A - port map(A => \counter_delta_snapshot[1]_net_1\, B => - \counter_delta_snapshot[0]_net_1\, C => N_504, Y => N_435); - - \counter_delta_f0_RNO_0[6]\ : AX1B - port map(A => N_55, B => \counter_delta_f0[5]_net_1\, C => - \counter_delta_f0[6]_net_1\, Y => N_87_i_i); - - \counter_delta_f0_RNIAF4P[20]\ : NOR3A - port map(A => counter_delta_f0_1_0_a2_3, B => - counter_delta_f0_1_0_a2_0, C => N_272, Y => - un1_start_snapshot_f22_i_a2_0_4); - - start_snapshot_f0_RNO_5 : NOR3C - port map(A => counter_delta_f0_1_0_a2_8_0, B => - counter_delta_f0_1_0_a2_8_1, C => - counter_delta_f0_1_0_a2_3, Y => counter_delta_f0_1_0_a2_9); - - \counter_delta_f0_RNO_0[2]\ : AX1B - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[1]_net_1\, C => - \counter_delta_f0[2]_net_1\, Y => N_114_i_i); - - \counter_delta_snapshot_RNO[22]\ : OR3C - port map(A => N_186, B => N_187, C => N_188, Y => - counter_delta_snapshot_e22); - - \counter_delta_snapshot_RNO[1]\ : NOR3 - port map(A => N_433, B => counter_delta_snapshot_e1_i_0, C - => N_435, Y => \counter_delta_snapshot_RNO[1]_net_1\); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_4\ : XA1A - port map(A => delta_snapshot(0), B => - \counter_delta_snapshot[0]_net_1\, C => N_137_i_i, Y => - un12_start_snapshot_fothers_temp_NE_0); - - \counter_delta_snapshot_RNO[14]\ : NOR3 - port map(A => N_486, B => counter_delta_snapshot_e14_i_0_0, - C => N_488, Y => N_6); - - start_snapshot_fothers_temp_RNI1HGO3 : NOR2B - port map(A => N_57_0, B => N_9_tz, Y => N_9_0); - - \counter_delta_snapshot_RNO_2[7]\ : NOR3B - port map(A => N_387, B => \counter_delta_snapshot[7]_net_1\, - C => N_504_0, Y => N_463); - - \counter_delta_f0_RNO[3]\ : MX2 - port map(A => delta_f2_f0(3), B => N_115_i_i, S => N_57_0, - Y => N_228); - - \counter_delta_snapshot_RNO_2[23]\ : NOR2B - port map(A => \counter_delta_snapshot[23]_net_1\, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, Y => - counter_delta_snapshot_e23_0_0_a2_0); - - \start_snapshot_f2\ : DFN1C0 - port map(D => N_7, CLK => HCLK_c, CLR => HRESETn_c, Q => - start_snapshot_f2); - - start_snapshot_fothers_temp_RNI66RC : OAI1 - port map(A => N_7, B => \start_snapshot_fothers_temp\, C - => sample_f2_val, Y => N_57_0); - - \counter_delta_snapshot_RNO_2[6]\ : NOR3A - port map(A => \counter_delta_snapshot[6]_net_1\, B => N_386, - C => N_504_0, Y => N_458); - - \counter_delta_f0_RNILEAO2[22]\ : OR3 - port map(A => N_58, B => \counter_delta_f0[21]_net_1\, C - => \counter_delta_f0[22]_net_1\, Y => N_62); - - \counter_delta_f0[25]\ : DFN1E0C0 - port map(D => N_32, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[25]_net_1\); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_1\ : XA1 - port map(A => delta_snapshot(5), B => - \counter_delta_snapshot_i[5]\, C => N_164_i_i, Y => - un12_start_snapshot_fothers_temp_NE_5); - - \counter_delta_snapshot_RNIRV6E4[23]\ : OR3B - port map(A => \counter_delta_snapshot_e27_0_0_o2_m6_e_3\, B - => counter_delta_snapshot_e27_0_0_o2_m6_e_2, C => N_398, - Y => \counter_delta_snapshot_RNIRV6E4[23]_net_1\); - - \counter_delta_snapshot_RNO_2[25]\ : OR2B - port map(A => \counter_delta_snapshot[25]_net_1\, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, Y => - counter_delta_snapshot_e25_0_0_a2_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_9\ : XNOR2 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - delta_snapshot(10), Y => N_510_i); - - \counter_delta_f0_RNO[9]\ : MX2 - port map(A => delta_f2_f0(9), B => N_324_i, S => N_57, Y - => N_17); - - \counter_delta_f0_RNINJ57[12]\ : OR2 - port map(A => \counter_delta_f0[13]_net_1\, B => - \counter_delta_f0[12]_net_1\, Y => N_272); - - \counter_delta_f0[16]\ : DFN1E0C0 - port map(D => counter_delta_f0_n16, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[16]_net_1\); - - \counter_delta_snapshot_RNO_2[24]\ : OR2A - port map(A => N_405, B => N_504, Y => N_194); - - \counter_delta_snapshot_RNIT7FC[21]\ : OR2 - port map(A => \counter_delta_snapshot[21]_net_1\, B => - \counter_delta_snapshot[20]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_1); - - start_snapshot_f0_RNO_3 : NOR3A - port map(A => N_273, B => \counter_delta_f0[2]_net_1\, C - => \counter_delta_f0[1]_net_1\, Y => - counter_delta_f0_1_0_a2_6); - - \counter_delta_snapshot_RNO_3[8]\ : OR2 - port map(A => \counter_delta_snapshot[8]_net_1\, B => N_388, - Y => counter_delta_snapshot_e8_i_a2_0); - - \counter_delta_snapshot_RNIN2IL[5]\ : OR2A - port map(A => \counter_delta_snapshot_i[5]\, B => N_385, Y - => N_386); - - \counter_delta_snapshot_RNO_3[9]\ : OR2 - port map(A => \counter_delta_snapshot[9]_net_1\, B => N_389, - Y => counter_delta_snapshot_e9_i_a2_0); - - \counter_delta_snapshot_RNO_2[3]\ : NOR3A - port map(A => \counter_delta_snapshot[3]_net_1\, B => N_383, - C => N_504, Y => N_443); - - \counter_delta_f0_RNO[19]\ : AO1C - port map(A => N_106, B => N_57, C => N_265, Y => - counter_delta_f0_n19); - - start_snapshot_f1_RNO_11 : XNOR2 - port map(A => \counter_delta_f0[8]_net_1\, B => - delta_f2_f1(8), Y => N_83_i_i_0); - - \counter_delta_f0_RNO_0[1]\ : XNOR2 - port map(A => \counter_delta_f0[1]_net_1\, B => - \counter_delta_f0[0]_net_1\, Y => N_107_i_i); - - \counter_delta_f0_RNIRIFC[2]\ : OR3 - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[1]_net_1\, C => - \counter_delta_f0[2]_net_1\, Y => N_89); - - \counter_delta_snapshot_RNO_2[21]\ : NOR2B - port map(A => \counter_delta_snapshot[21]_net_1\, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, Y => - counter_delta_snapshot_e21_0_0_a2_0); - - \counter_delta_snapshot[20]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[20]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[20]_net_1\); - - \counter_delta_f0_RNO_0[22]\ : AX1D - port map(A => N_58, B => \counter_delta_f0[21]_net_1\, C - => \counter_delta_f0[22]_net_1\, Y => N_86_i); - - \counter_delta_f0[0]\ : DFN1E0C0 - port map(D => N_21, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[0]_net_1\); - - \counter_delta_f0[23]\ : DFN1E0C0 - port map(D => N_28, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[23]_net_1\); - - \counter_delta_snapshot_RNI9KJK[7]\ : NOR3A - port map(A => counter_delta_snapshot_e12_i_0_o2_m6_e_4, B - => \counter_delta_snapshot[8]_net_1\, C => - \counter_delta_snapshot[7]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_6); - - \counter_delta_f0_RNO[22]\ : NOR2A - port map(A => N_57, B => N_86_i, Y => N_277); - - \counter_delta_f0[8]\ : DFN1E0C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[8]_net_1\); - - \counter_delta_snapshot_RNO_1[20]\ : OR2A - port map(A => \counter_delta_snapshot[20]_net_1\, B => - un2_coarse_time_0, Y => N_181); - - \counter_delta_snapshot_RNO_0[9]\ : NOR2 - port map(A => N_505, B => delta_snapshot(9), Y => N_471); - - \counter_delta_f0_RNO_1[18]\ : NOR2B - port map(A => \counter_delta_f0[18]_net_1\, B => N_57_0, Y - => counter_delta_f0_n18_0_0_a2_0); - - start_snapshot_f1_RNO : NOR3C - port map(A => start_snapshot_f12_0_a2_7, B => - start_snapshot_f12_0_a2_6, C => N_322, Y => - start_snapshot_f12); - - \counter_delta_f0_RNO[2]\ : MX2 - port map(A => delta_f2_f0(2), B => N_114_i_i, S => N_57_0, - Y => N_227); - - start_snapshot_f0_RNO_2 : NOR3C - port map(A => counter_delta_f0_1_0_a2_2_0, B => - counter_delta_f0_1_0_a2_1_0, C => - counter_delta_f0_1_0_a2_9, Y => - counter_delta_f0_1_0_a2_12); - - \counter_delta_snapshot_RNO_1[4]\ : OA1 - port map(A => \counter_delta_snapshot[4]_net_1\, B => - un2_coarse_time_0_0, C => N_445, Y => - counter_delta_snapshot_e4_i_0); - - \counter_delta_snapshot_RNIGN0H[11]\ : NOR3B - port map(A => \counter_delta_snapshot_i[11]\, B => - counter_delta_snapshot_e12_i_0_o2_m6_e_2, C => - \counter_delta_snapshot[3]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_5); - - \counter_delta_snapshot_RNIAA8V[23]\ : NOR3A - port map(A => \counter_delta_snapshot_e27_0_0_o2_m6_e_1\, B - => \counter_delta_snapshot[22]_net_1\, C => - \counter_delta_snapshot[23]_net_1\, Y => - \counter_delta_snapshot_e27_0_0_o2_m6_e_3\); - - coarse_time_0_r_RNIGJTR4 : OR2B - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => un2_coarse_time_0_0, Y => N_504_0); - - start_snapshot_f0_RNO : NOR3C - port map(A => counter_delta_f0_1_0_a2_11, B => - counter_delta_f0_1_0_a2_10, C => - counter_delta_f0_1_0_a2_12, Y => counter_delta_f0_1); - - \counter_delta_snapshot_RNO_2[22]\ : OR3 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => N_504, Y => - N_188); - - \counter_delta_snapshot_RNO[9]\ : NOR3 - port map(A => N_471, B => counter_delta_snapshot_e9_i_0, C - => N_472, Y => \counter_delta_snapshot_RNO[9]_net_1\); - - start_snapshot_f1_RNO_5 : XNOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => - delta_f2_f1(5), Y => N_113_i_i_0); - - \counter_delta_f0[1]\ : DFN1E0C0 - port map(D => N_23, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[1]_net_1\); - - \counter_delta_snapshot_RNI95UL2[17]\ : OR2 - port map(A => \counter_delta_snapshot[17]_net_1\, B => - N_397, Y => N_398); - - \counter_delta_snapshot[22]\ : DFN1C0 - port map(D => counter_delta_snapshot_e22, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[22]_net_1\); - - \counter_delta_f0_RNO[15]\ : XA1A - port map(A => \counter_delta_f0[15]_net_1\, B => N_101, C - => N_57_0, Y => counter_delta_f0_n15); - - \counter_delta_f0[19]\ : DFN1E0C0 - port map(D => counter_delta_f0_n19, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[19]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \counter_delta_snapshot_RNO_0[5]\ : OR3 - port map(A => N_385, B => \counter_delta_snapshot_i[5]\, C - => N_504_0, Y => N_453); - - \counter_delta_f0_RNO[24]\ : NOR2A - port map(A => N_57, B => N_98_i, Y => N_30); - - \counter_delta_snapshot_RNO[3]\ : NOR3 - port map(A => N_442, B => counter_delta_snapshot_e3_i_0, C - => N_443, Y => \counter_delta_snapshot_RNO[3]_net_1\); - - \counter_delta_f0_RNO_0[16]\ : OAI1 - port map(A => N_101, B => \counter_delta_f0[15]_net_1\, C - => counter_delta_f0_n16_0_0_a2_0, Y => N_259); - - \counter_delta_snapshot[6]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[6]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[6]_net_1\); - - \counter_delta_f0[18]\ : DFN1E0C0 - port map(D => counter_delta_f0_n18, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[18]_net_1\); - - \counter_delta_snapshot_RNO_3[10]\ : NOR3B - port map(A => N_390, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => - \counter_delta_snapshot[10]_net_1\, Y => N_474); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_8\ : XOR2 - port map(A => \counter_delta_snapshot_i[11]\, B => - delta_snapshot(11), Y => - un12_start_snapshot_fothers_temp_NE_RNO_8); - - start_snapshot_fothers_temp_RNI66RC_0 : OAI1 - port map(A => N_7, B => \start_snapshot_fothers_temp\, C - => sample_f2_val, Y => N_57); - - \counter_delta_f0[6]\ : DFN1E0C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[6]_net_1\); - - \counter_delta_snapshot[8]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[8]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[8]_net_1\); - - \counter_delta_snapshot_RNO_0[18]\ : OR3C - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_174); - - counter_delta_snapshot_e27_0_0_o2_m6_e_1_RNI8ATS : OR3B - port map(A => start_snapshot_f22_0_a2_11_0_a2_0, B => - start_snapshot_f22_0_a2_11_0_a2_2_0, C => - start_snapshot_f22_0_a2_11_0_a2_1, Y => - start_snapshot_f22_11_i); - - \counter_delta_snapshot_RNI2JDD[4]\ : NOR3 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - \counter_delta_snapshot[4]_net_1\, C => - \counter_delta_snapshot[9]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_4); - - start_snapshot_f1_RNO_0 : NOR3C - port map(A => start_snapshot_f12_0_a2_1, B => - start_snapshot_f12_0_a2_0, C => start_snapshot_f12_0_a2_4, - Y => start_snapshot_f12_0_a2_7); - - \counter_delta_f0_RNO[21]\ : XA1A - port map(A => N_58, B => \counter_delta_f0[21]_net_1\, C - => N_57, Y => N_276); - - \counter_delta_snapshot_RNO_4[7]\ : OR2 - port map(A => \counter_delta_snapshot[7]_net_1\, B => N_387, - Y => counter_delta_snapshot_e7_i_a2_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_17\ : XNOR2 - port map(A => \counter_delta_snapshot[8]_net_1\, B => - delta_snapshot(8), Y => N_509_i); - - \counter_delta_f0_RNIIM2T1[25]\ : NOR3C - port map(A => un1_start_snapshot_f22_i_a2_0_3, B => - counter_delta_f0_1_0_a2_5_0, C => - un1_start_snapshot_f22_i_a2_0_4, Y => N_322); - - \counter_delta_snapshot[4]\ : DFN1C0 - port map(D => N_375_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => \counter_delta_snapshot[4]_net_1\); - - \counter_delta_snapshot_RNI935P[6]\ : NOR2 - port map(A => \counter_delta_snapshot[6]_net_1\, B => N_386, - Y => N_387); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_0\ : NOR3C - port map(A => un12_start_snapshot_fothers_temp_NE_5, B => - un12_start_snapshot_fothers_temp_NE_4, C => - un12_start_snapshot_fothers_temp_NE_11, Y => - un12_start_snapshot_fothers_temp_NE_13); - - \counter_delta_snapshot_RNO[24]\ : OR3C - port map(A => N_192, B => N_193, C => N_194, Y => - counter_delta_snapshot_e24); - - \counter_delta_f0_RNO_1[12]\ : NOR2B - port map(A => \counter_delta_f0[12]_net_1\, B => N_57_0, Y - => counter_delta_f0_n12_0_0_a2_0); - - \counter_delta_f0_RNIJ357[10]\ : OR2 - port map(A => \counter_delta_f0[11]_net_1\, B => - \counter_delta_f0[10]_net_1\, Y => - counter_delta_f0_1_0_a2_5); - - \counter_delta_snapshot[15]\ : DFN1C0 - port map(D => N_8, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[15]_net_1\); - - \counter_delta_snapshot_RNO_1[1]\ : OA1C - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[0]_net_1\, C => - \counter_delta_snapshot[1]_net_1\, Y => - counter_delta_snapshot_e1_i_0); - - \counter_delta_snapshot_RNO_3[2]\ : OR2 - port map(A => \counter_delta_snapshot[2]_net_1\, B => N_382, - Y => counter_delta_snapshot_e2_i_a2_0); - - start_snapshot_fothers_temp_RNI1HGO3_0 : NOR2B - port map(A => N_57_0, B => N_9_tz, Y => N_9); - - \counter_delta_f0[9]\ : DFN1E0C0 - port map(D => N_17, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[9]_net_1\); - - \counter_delta_snapshot_RNO[0]\ : OA1B - port map(A => delta_snapshot(0), B => N_505, C => - counter_delta_snapshot_e0_i_0, Y => - \counter_delta_snapshot_RNO[0]_net_1\); - - start_snapshot_f1_RNO_10 : XNOR2 - port map(A => \counter_delta_f0[0]_net_1\, B => - delta_f2_f1(0), Y => N_108_i_i_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO\ : NOR3C - port map(A => un12_start_snapshot_fothers_temp_NE_1, B => - un12_start_snapshot_fothers_temp_NE_0, C => - un12_start_snapshot_fothers_temp_NE_9, Y => - un12_start_snapshot_fothers_temp_NE_12); - - \counter_delta_snapshot_RNO_2[20]\ : OR3 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => N_504, Y => - N_182); - - \counter_delta_snapshot_RNO_4[5]\ : NOR2B - port map(A => \counter_delta_snapshot_i[5]\, B => N_385, Y - => counter_delta_snapshot_e5_i_a2_0); - - \counter_delta_snapshot_RNO_1[18]\ : OR2A - port map(A => \counter_delta_snapshot[18]_net_1\, B => - un2_coarse_time_0, Y => N_175); - - \counter_delta_f0_RNO_0[9]\ : XNOR2 - port map(A => \counter_delta_f0[9]_net_1\, B => N_63, Y => - N_324_i); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_2\ : XA1A - port map(A => delta_snapshot(4), B => - \counter_delta_snapshot[4]_net_1\, C => - un12_start_snapshot_fothers_temp_NE_RNO_8, Y => - un12_start_snapshot_fothers_temp_NE_1); - - \counter_delta_snapshot_RNI62VH[4]\ : OR2 - port map(A => \counter_delta_snapshot[4]_net_1\, B => N_384, - Y => N_385); - - \counter_delta_snapshot[11]\ : DFN1P0 - port map(D => N_22_i_0, CLK => HCLK_c, PRE => HRESETn_c, Q - => \counter_delta_snapshot_i[11]\); - - \counter_delta_snapshot_RNO_4[9]\ : NOR2 - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[9]_net_1\, Y => N_470); - - \counter_delta_f0_RNO_0[5]\ : XNOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => N_55, Y => - N_117_i_i); - - \counter_delta_snapshot_RNI07532[14]\ : NOR2A - port map(A => N_394, B => - \counter_delta_snapshot[14]_net_1\, Y => N_395); - - \counter_delta_snapshot_RNO_1[8]\ : AO1A - port map(A => counter_delta_snapshot_e8_i_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_466, Y - => counter_delta_snapshot_e8_i_0); - - \counter_delta_snapshot_RNO_2[5]\ : OR2 - port map(A => N_505, B => delta_snapshot(5), Y => N_452); - - \counter_delta_snapshot_RNO[11]\ : OR3C - port map(A => N_503, B => counter_delta_snapshot_e11_i_0_0, - C => N_501, Y => N_22_i_0); - - \counter_delta_snapshot[18]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[18]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[18]_net_1\); - - \counter_delta_f0_RNO_0[19]\ : OR3B - port map(A => N_57_0, B => \counter_delta_f0[19]_net_1\, C - => N_105, Y => N_265); - - \counter_delta_f0_RNO_0[18]\ : OAI1 - port map(A => N_103, B => \counter_delta_f0[17]_net_1\, C - => counter_delta_f0_n18_0_0_a2_0, Y => N_263); - - \counter_delta_snapshot_RNO_2[2]\ : NOR3B - port map(A => N_382, B => \counter_delta_snapshot[2]_net_1\, - C => N_504, Y => N_438); - - \counter_delta_snapshot[13]\ : DFN1C0 - port map(D => N_26, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[13]_net_1\); - - \counter_delta_snapshot_RNO_2[4]\ : OR2 - port map(A => N_505, B => delta_snapshot(4), Y => N_447); - - \counter_delta_snapshot_RNI9IOI[26]\ : OR3 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - \counter_delta_snapshot[26]_net_1\, C => - \counter_delta_snapshot[24]_net_1\, Y => - start_snapshot_f22_10); - - \counter_delta_snapshot_RNI2N5A1[10]\ : OR2 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - N_390, Y => N_391); - - \counter_delta_f0_RNO[17]\ : XA1A - port map(A => \counter_delta_f0[17]_net_1\, B => N_103, C - => N_57, Y => counter_delta_f0_n17); - - \counter_delta_snapshot_RNI3167[5]\ : NOR2A - port map(A => \counter_delta_snapshot_i[5]\, B => - \counter_delta_snapshot[6]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_2); - - \counter_delta_snapshot_RNO_0[23]\ : OA1A - port map(A => \counter_delta_snapshot[23]_net_1\, B => - un2_coarse_time_0_0, C => N_189, Y => - counter_delta_snapshot_e23_0_0_0); - - \counter_delta_f0_RNO[13]\ : XA1A - port map(A => \counter_delta_f0[13]_net_1\, B => N_99, C - => N_57_0, Y => counter_delta_f0_n13); - - \counter_delta_snapshot_RNO_0[13]\ : NOR2 - port map(A => N_505, B => delta_snapshot(13), Y => N_287); - - \counter_delta_snapshot_RNO[8]\ : NOR3 - port map(A => N_467, B => counter_delta_snapshot_e8_i_0, C - => N_468, Y => \counter_delta_snapshot_RNO[8]_net_1\); - - \counter_delta_f0_RNO_0[24]\ : AX1D - port map(A => N_62, B => \counter_delta_f0[23]_net_1\, C - => \counter_delta_f0[24]_net_1\, Y => N_98_i); - - coarse_time_0_r_RNILJMD_0 : NOR2A - port map(A => coarse_time_0_c, B => \coarse_time_0_r\, Y - => un2_coarse_time_0_0); - - start_snapshot_f22_0_a2_RNO_0 : OR2 - port map(A => \start_snapshot_f2_temp\, B => - start_snapshot_f22_10, Y => start_snapshot_f22_0_a2_0); - - \counter_delta_f0_RNO[0]\ : MX2B - port map(A => delta_f2_f0(0), B => - \counter_delta_f0[0]_net_1\, S => N_57_0, Y => N_21); - - coarse_time_0_r_RNIGJTR4_1 : OR2A - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_505); - - \counter_delta_snapshot[1]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[1]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[1]_net_1\); - - \counter_delta_f0[22]\ : DFN1E0C0 - port map(D => N_277, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[22]_net_1\); - - \counter_delta_snapshot_RNO_0[25]\ : OA1A - port map(A => \counter_delta_snapshot[25]_net_1\, B => - un2_coarse_time_0_0, C => N_421, Y => - counter_delta_snapshot_e25_0_0_0); - - \counter_delta_f0_RNI13O22[16]\ : OR3 - port map(A => N_101, B => \counter_delta_f0[15]_net_1\, C - => \counter_delta_f0[16]_net_1\, Y => N_103); - - \counter_delta_snapshot_RNO_0[15]\ : NOR2 - port map(A => N_505, B => delta_snapshot(15), Y => N_480); - - \counter_delta_snapshot_RNO_0[24]\ : OR3C - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => \counter_delta_snapshot[24]_net_1\, C => N_404, Y - => N_192); - - \counter_delta_snapshot_RNO_0[14]\ : NOR2 - port map(A => N_505, B => delta_snapshot(14), Y => N_486); - - start_snapshot_fothers_temp_RNO : NOR3B - port map(A => N_322, B => counter_delta_f0lde_i_a2_0_1_3, C - => N_7, Y => N_284); - - \counter_delta_snapshot_RNIHLUE3[21]\ : OR3 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - \counter_delta_snapshot[21]_net_1\, Y => N_402); - - \counter_delta_snapshot_RNI8G0P[19]\ : NOR3 - port map(A => \counter_delta_snapshot[18]_net_1\, B => - \counter_delta_snapshot[19]_net_1\, C => - start_snapshot_f22_0_a2_11_0_a2_1, Y => - counter_delta_snapshot_e27_0_0_o2_m6_e_2); - - \counter_delta_snapshot_RNO[16]\ : OAI1 - port map(A => N_397, B => N_504_0, C => - counter_delta_snapshot_e16_i_i_0, Y => - \counter_delta_snapshot_RNO[16]_net_1\); - - \counter_delta_f0_RNIN6VO[4]\ : NOR3C - port map(A => counter_delta_f0_1_0_a2_7, B => N_273, C => - counter_delta_f0_1_0_a2_2_0, Y => - counter_delta_f0lde_i_a2_0_1_2); - - \counter_delta_f0[7]\ : DFN1E0C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[7]_net_1\); - - \counter_delta_snapshot_RNO_0[21]\ : OA1A - port map(A => \counter_delta_snapshot[21]_net_1\, B => - un2_coarse_time_0, C => N_183, Y => - counter_delta_snapshot_e21_0_0_0); - - \counter_delta_f0[5]\ : DFN1E0C0 - port map(D => N_230, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[5]_net_1\); - - coarse_time_0_r : DFN1C0 - port map(D => coarse_time_0_c, CLK => HCLK_c, CLR => - HRESETn_c, Q => \coarse_time_0_r\); - - \counter_delta_snapshot_RNO_4[4]\ : NOR2A - port map(A => N_384, B => \counter_delta_snapshot[4]_net_1\, - Y => counter_delta_snapshot_e4_i_a2_0); - - \counter_delta_snapshot_RNO_3[6]\ : NOR2A - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => counter_delta_snapshot_e6_i_a2_0, Y => N_455); - - counter_delta_snapshot_e27_0_0_o2_m6_e_1 : NOR2 - port map(A => \counter_delta_snapshot[19]_net_1\, B => - \counter_delta_snapshot[18]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_2_i); - - \counter_delta_f0[10]\ : DFN1E0C0 - port map(D => N_19, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[10]_net_1\); - - \counter_delta_snapshot_RNO_0[11]\ : OR3 - port map(A => N_391, B => \counter_delta_snapshot_i[11]\, C - => N_504_0, Y => N_503); - - \counter_delta_f0_RNO[6]\ : MX2 - port map(A => delta_f2_f0(6), B => N_87_i_i, S => N_57, Y - => N_11); - - start_snapshot_f22_0_a2 : NOR2 - port map(A => un12_start_snapshot_fothers_temp_NE, B => - start_snapshot_f22_0_a2_1, Y => N_7); - - \counter_delta_snapshot[5]\ : DFN1P0 - port map(D => N_376_i_0, CLK => HCLK_c, PRE => HRESETn_c, Q - => \counter_delta_snapshot_i[5]\); - - \counter_delta_f0_RNO_0[12]\ : OAI1 - port map(A => N_67, B => \counter_delta_f0[11]_net_1\, C - => counter_delta_f0_n12_0_0_a2_0, Y => N_252); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_14\ : XNOR2 - port map(A => \counter_delta_snapshot[13]_net_1\, B => - delta_snapshot(13), Y => N_133_i_i); - - \counter_delta_snapshot_RNO_3[4]\ : OR2B - port map(A => counter_delta_snapshot_e4_i_a2_0, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_445); - - \counter_delta_snapshot_RNO_2[18]\ : OR3 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => N_504, Y => - N_176); - - \counter_delta_snapshot[0]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[0]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[0]_net_1\); - - \counter_delta_snapshot[7]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[7]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[7]_net_1\); - - \counter_delta_snapshot_RNO_1[13]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[13]_net_1\, C => N_285, Y => - counter_delta_snapshot_e13_i_0_0); - - start_snapshot_f1_RNO_1 : NOR3C - port map(A => N_113_i_i_0, B => N_112_i_i_0, C => - start_snapshot_f12_0_a2_3, Y => start_snapshot_f12_0_a2_6); - - \counter_delta_f0_RNIGAGV2[24]\ : OR3 - port map(A => N_62, B => \counter_delta_f0[23]_net_1\, C - => \counter_delta_f0[24]_net_1\, Y => N_66); - - \counter_delta_snapshot_RNO_2[9]\ : NOR3B - port map(A => N_389, B => \counter_delta_snapshot[9]_net_1\, - C => N_504_0, Y => N_472); - - \counter_delta_f0_RNIPCA8[4]\ : NOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => - \counter_delta_f0[4]_net_1\, Y => N_273); - - \counter_delta_f0_RNO[12]\ : AO1C - port map(A => N_99, B => N_57_0, C => N_252, Y => - counter_delta_f0_n12); - - \counter_delta_snapshot[9]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[9]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[9]_net_1\); - - \counter_delta_snapshot_RNO_1[15]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[15]_net_1\, C => N_478, Y => - counter_delta_snapshot_e15_i_0_0); - - \counter_delta_snapshot_RNO[10]\ : NOR3 - port map(A => N_476, B => counter_delta_snapshot_e10_i_0, C - => N_477, Y => \counter_delta_snapshot_RNO[10]_net_1\); - - \counter_delta_f0[11]\ : DFN1E0C0 - port map(D => N_275, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[11]_net_1\); - - \counter_delta_snapshot_RNO_0[22]\ : OR3C - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => \counter_delta_snapshot[22]_net_1\, C => N_402, Y - => N_186); - - start_snapshot_f1_RNO_4 : XA1A - port map(A => delta_f2_f1(9), B => - \counter_delta_f0[9]_net_1\, C => N_108_i_i_0, Y => - start_snapshot_f12_0_a2_4); - - \counter_delta_snapshot_RNO_0[12]\ : NOR2 - port map(A => N_505, B => delta_snapshot(12), Y => N_496); - - \counter_delta_snapshot_RNO[15]\ : NOR3 - port map(A => N_480, B => counter_delta_snapshot_e15_i_0_0, - C => N_482, Y => N_8); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_18\ : XNOR2 - port map(A => \counter_delta_snapshot[15]_net_1\, B => - delta_snapshot(15), Y => N_135_i_i); - - \counter_delta_snapshot_RNO_1[14]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[14]_net_1\, C => N_484, Y => - counter_delta_snapshot_e14_i_0_0); - - \counter_delta_f0_RNO_1[14]\ : NOR2B - port map(A => \counter_delta_f0[14]_net_1\, B => N_57_0, Y - => counter_delta_f0_n14_0_0_a2_0); - - \counter_delta_snapshot_RNO_0[19]\ : AOI1B - port map(A => counter_delta_snapshot_e19_i_i_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_178, Y - => counter_delta_snapshot_e19_i_i_0); - - \counter_delta_f0[26]\ : DFN1E0C0 - port map(D => N_34, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[26]_net_1\); - - \counter_delta_snapshot_RNO_4[6]\ : OR2A - port map(A => N_386, B => \counter_delta_snapshot[6]_net_1\, - Y => counter_delta_snapshot_e6_i_a2_0); - - \counter_delta_snapshot_RNO[13]\ : NOR3 - port map(A => N_287, B => counter_delta_snapshot_e13_i_0_0, - C => N_288, Y => N_26); - - \counter_delta_snapshot_RNO_0[7]\ : NOR2 - port map(A => N_505, B => delta_snapshot(7), Y => N_462); - - \counter_delta_snapshot_RNO_0[26]\ : AO1B - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => N_406, C => un2_coarse_time_0, Y => - counter_delta_snapshot_e26_0_0_0_tz); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_16\ : XA1A - port map(A => delta_snapshot(14), B => - \counter_delta_snapshot[14]_net_1\, C => N_135_i_i, Y => - un12_start_snapshot_fothers_temp_NE_3); - - \counter_delta_snapshot_RNO_0[16]\ : OA1A - port map(A => \counter_delta_snapshot[16]_net_1\, B => - un2_coarse_time_0_0, C => N_168, Y => - counter_delta_snapshot_e16_i_i_0); - - start_snapshot_f1_RNO_3 : XA1A - port map(A => delta_f2_f1(6), B => - \counter_delta_f0[6]_net_1\, C => N_82_i_i_0, Y => - start_snapshot_f12_0_a2_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ is - - port( status_new_err : out std_logic_vector(3 to 3); - valid_ack : in std_logic_vector(3 to 3); - valid_out : out std_logic_vector(3 to 3); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f3_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1_i, N_6_i_i_0, \valid_out[3]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(3) <= \valid_out[3]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1_i, CLK => HCLK_c, CLR => - HRESETn_c, Q => status_new_err(3)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => \valid_out[3]\); - - error_RNO : NOR3B - port map(A => \valid_out[3]\, B => data_f3_out_valid, C => - valid_ack(3), Y => state_1_sqmuxa_1_i); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(3), B => \valid_out[3]\, C => - data_f3_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ is - - port( status_new_err : out std_logic_vector(1 to 1); - valid_out_i : out std_logic_vector(1 to 1); - valid_ack : in std_logic_vector(1 to 1); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f1_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out_i[1]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out_i(1) <= \valid_out_i[1]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => status_new_err(1)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1P0 - port map(D => N_6_i_i_0, CLK => HCLK_c, PRE => HRESETn_c, Q - => \valid_out_i[1]\); - - error_RNO : NOR3A - port map(A => data_f1_out_valid, B => valid_ack(1), C => - \valid_out_i[1]\, Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1D - port map(A => valid_ack(1), B => \valid_out_i[1]\, C => - data_f1_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_burst is - - port( sample_f3_wdata : in std_logic_vector(95 downto 0); - data_f3_out : out std_logic_vector(159 downto 64); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f3_out_valid : out std_logic; - enable_f3 : in std_logic; - sample_f3_val : in std_logic - ); - -end lpp_waveform_burst; - -architecture DEF_ARCH of lpp_waveform_burst is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal data_out_valid_3, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \data_out[91]\ : DFN1C0 - port map(D => sample_f3_wdata(27), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(91)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f3_wdata(60), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(124)); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f3_wdata(56), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(120)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f3_wdata(74), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(138)); - - \data_out[105]\ : DFN1C0 - port map(D => sample_f3_wdata(41), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(105)); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f3_wdata(62), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(126)); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f3_wdata(10), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(74)); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f3_wdata(90), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(154)); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f3_wdata(86), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(150)); - - \data_out[102]\ : DFN1C0 - port map(D => sample_f3_wdata(38), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(102)); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f3_wdata(92), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(156)); - - \data_out[93]\ : DFN1C0 - port map(D => sample_f3_wdata(29), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(93)); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f3_wdata(64), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(128)); - - data_out_valid : DFN1C0 - port map(D => data_out_valid_3, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out_valid); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f3_wdata(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(69)); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f3_wdata(77), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(141)); - - \data_out[99]\ : DFN1C0 - port map(D => sample_f3_wdata(35), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(99)); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f3_wdata(83), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(147)); - - \data_out[87]\ : DFN1C0 - port map(D => sample_f3_wdata(23), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(87)); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f3_wdata(85), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(149)); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_out[86]\ : DFN1C0 - port map(D => sample_f3_wdata(22), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(86)); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f3_wdata(94), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(158)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f3_wdata(49), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(113)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f3_wdata(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(65)); - - \data_out[95]\ : DFN1C0 - port map(D => sample_f3_wdata(31), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(95)); - - \data_out[92]\ : DFN1C0 - port map(D => sample_f3_wdata(28), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(92)); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f3_wdata(13), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(77)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f3_wdata(81), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(145)); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f3_wdata(67), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(131)); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f3_wdata(12), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(76)); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f3_wdata(73), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(137)); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f3_wdata(75), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(139)); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f3_wdata(50), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(114)); - - \data_out[80]\ : DFN1C0 - port map(D => sample_f3_wdata(16), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(80)); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f3_wdata(0), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(64)); - - \data_out[110]\ : DFN1C0 - port map(D => sample_f3_wdata(46), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(110)); - - \data_out[103]\ : DFN1C0 - port map(D => sample_f3_wdata(39), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(103)); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f3_wdata(78), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(142)); - - \data_out[94]\ : DFN1C0 - port map(D => sample_f3_wdata(30), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(94)); - - \data_out[88]\ : DFN1C0 - port map(D => sample_f3_wdata(24), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(88)); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f3_wdata(52), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(116)); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f3_wdata(57), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(121)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f3_wdata(63), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(127)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f3_wdata(65), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(129)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f3_wdata(71), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(135)); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f3_wdata(6), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(70)); - - data_out_valid_RNO : NOR2B - port map(A => sample_f3_val, B => enable_f3, Y => - data_out_valid_3); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f3_wdata(54), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(118)); - - \data_out[104]\ : DFN1C0 - port map(D => sample_f3_wdata(40), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(104)); - - \data_out[100]\ : DFN1C0 - port map(D => sample_f3_wdata(36), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(100)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f3_wdata(14), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(78)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f3_wdata(87), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(151)); - - GND_i : GND - port map(Y => \GND\); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f3_wdata(93), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(157)); - - \data_out[106]\ : DFN1C0 - port map(D => sample_f3_wdata(42), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(106)); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f3_wdata(95), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(159)); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f3_wdata(68), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(132)); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f3_wdata(61), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(125)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f3_wdata(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(67)); - - \data_out[81]\ : DFN1C0 - port map(D => sample_f3_wdata(17), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(81)); - - \data_out[97]\ : DFN1C0 - port map(D => sample_f3_wdata(33), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(97)); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f3_wdata(2), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(66)); - - \data_out[108]\ : DFN1C0 - port map(D => sample_f3_wdata(44), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(108)); - - \data_out[96]\ : DFN1C0 - port map(D => sample_f3_wdata(32), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(96)); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f3_wdata(79), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(143)); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f3_wdata(58), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(122)); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f3_wdata(91), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(155)); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f3_wdata(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(71)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f3_wdata(88), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(152)); - - \data_out[83]\ : DFN1C0 - port map(D => sample_f3_wdata(19), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(83)); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f3_wdata(80), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(144)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f3_wdata(76), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(140)); - - \data_out[111]\ : DFN1C0 - port map(D => sample_f3_wdata(47), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(111)); - - \data_out[90]\ : DFN1C0 - port map(D => sample_f3_wdata(26), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(90)); - - \data_out[89]\ : DFN1C0 - port map(D => sample_f3_wdata(25), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(89)); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f3_wdata(4), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(68)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f3_wdata(53), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(117)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f3_wdata(82), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(146)); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f3_wdata(69), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(133)); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f3_wdata(55), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(119)); - - \data_out[98]\ : DFN1C0 - port map(D => sample_f3_wdata(34), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(98)); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f3_wdata(9), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(73)); - - \data_out[85]\ : DFN1C0 - port map(D => sample_f3_wdata(21), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(85)); - - \data_out[82]\ : DFN1C0 - port map(D => sample_f3_wdata(18), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(82)); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f3_wdata(15), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(79)); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f3_wdata(84), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(148)); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f3_wdata(59), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(123)); - - \data_out[101]\ : DFN1C0 - port map(D => sample_f3_wdata(37), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(101)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f3_wdata(70), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(134)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f3_wdata(51), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(115)); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f3_wdata(66), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(130)); - - \data_out[107]\ : DFN1C0 - port map(D => sample_f3_wdata(43), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(107)); - - \data_out[109]\ : DFN1C0 - port map(D => sample_f3_wdata(45), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(109)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f3_wdata(72), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(136)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[84]\ : DFN1C0 - port map(D => sample_f3_wdata(20), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(84)); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f3_wdata(11), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(75)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f3_wdata(8), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(72)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f3_wdata(89), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(153)); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f3_wdata(48), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(112)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ is - - port( status_new_err : out std_logic_vector(2 to 2); - valid_ack : in std_logic_vector(2 to 2); - valid_out : out std_logic_vector(2 to 2); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f2_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out[2]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(2) <= \valid_out[2]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => status_new_err(2)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => \valid_out[2]\); - - error_RNO : NOR3B - port map(A => \valid_out[2]\, B => data_f2_out_valid, C => - valid_ack(2), Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(2), B => \valid_out[2]\, C => - data_f2_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ is - - port( status_new_err : out std_logic_vector(0 to 0); - valid_ack : in std_logic_vector(0 to 0); - valid_out : out std_logic_vector(0 to 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f0_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out[0]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(0) <= \valid_out[0]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => status_new_err(0)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => \valid_out[0]\); - - error_RNO : NOR3B - port map(A => \valid_out[0]\, B => data_f0_out_valid, C => - valid_ack(0), Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(0), B => \valid_out[0]\, C => - data_f0_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ1 is - - port( ready_i_0 : out std_logic_vector(1 to 1); - Raddr_vect_RNICA1PH : out std_logic_vector(1 to 1); - data_mem_wen_i_0 : inout std_logic_vector(2 downto 1) := (others => 'Z'); - Raddr_vect_RNIIMQ5I : out std_logic_vector(4 to 4); - Raddr_vect_RNIE6Q5I : out std_logic_vector(3 to 3); - Raddr_vect_RNIKA2PH : out std_logic_vector(2 to 2); - data_addr_r_iv_i_3 : in std_logic_vector(4 downto 0); - Raddr_vect_RNI4A0PH : out std_logic_vector(0 to 0); - data_addr_r_iv_i_a2_2 : in std_logic_vector(4 to 4); - data_wen : in std_logic_vector(1 to 1); - data_mem_ren_i_0 : inout std_logic_vector(1 downto 0) := (others => 'Z'); - data_ren : in std_logic_vector(1 to 1); - data_ren_1z : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_166 : out std_logic; - N_126 : out std_logic; - N_150 : out std_logic; - N_134 : out std_logic; - N_142 : out std_logic; - N_165 : in std_logic; - N_158 : out std_logic; - un20_time_write : in std_logic; - N_68 : in std_logic; - N_164 : in std_logic; - N_120_i : out std_logic; - N_44 : in std_logic; - N_52 : in std_logic; - N_60 : in std_logic; - N_76 : in std_logic; - N_86 : out std_logic; - N_75 : in std_logic; - N_59 : in std_logic; - N_51 : in std_logic; - N_43 : in std_logic; - N_67 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ1; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ1 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \data_mem_addr_w_1[1]\, \data_mem_addr_w_1[0]\, - N_4, \data_mem_addr_w_1[3]\, \DWACT_FINC_E[0]\, N_12_0, - \data_mem_addr_r_1[1]\, \data_mem_addr_r_1[0]\, N_4_0, - \data_mem_addr_r_1[3]\, \DWACT_FINC_E_0[0]\, - \un26_sfull_s\, \un26_sfull_s_tz\, \sFull\, un5_sfull_s_4, - \data_addr_r_iv_i_4[1]\, \data_addr_r_iv_i_4[4]\, - \data_mem_addr_r_1[4]\, \data_addr_r_iv_i_4[3]\, - \data_addr_r_iv_i_4[2]\, \data_mem_addr_r_1[2]\, - \data_addr_r_iv_i_4[0]\, \data_addr_r_iv_i_a2_3[4]\, - un7_sempty_s_4, un7_sempty_s_1, un7_sempty_s_0, - un7_sempty_s_2, \un10_raddr_vect_s[3]\, sEmpty_RNO_7_0, - \un10_raddr_vect_s[1]\, sEmpty_RNO_6_2, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \un8_waddr_vect_s[3]\, \un26_sfull_s_tz_RNO_7\, - un5_sfull_s_4_1, \un8_waddr_vect_s[1]\, - \un26_sfull_s_tz_RNO_4\, un5_sfull_s_4_0, - \un8_waddr_vect_s[0]\, ADD_5x5_fast_I11_Y_i_a2_0, - \data_mem_addr_w_1[2]\, N_109, ADD_5x5_fast_I11_Y_0, - N_89_i, N80, SUM2_0_0, ADD_5x5_fast_I11_un1_Y_0, N81, - N_85_i, N_105_1, ADD_7x7_fast_I19_Y_i_o4_1_0, N_87, - un1_waddr_vect_slto3_0, un2_raddr_vect_slto3_0, - un1_waddr_vect_slt4, \un60_ready1[4]\, CO1_tz, N_12_1, - N_17, N_18, I11_un1_Y, un7_sempty_s, Waddr_vect_n4, - \data_mem_addr_w_1[4]\, Waddr_vect_14_0, Waddr_vect_c2, - Waddr_vect_n2, un1_waddr_vect_s, Waddr_vect_n2_tz, - Waddr_vect_n3, N_9, N165, N_14_1, N_23, N_75_i_0, - \un75_ready1[4]\, ADD_5x5_fast_I8_un1_Y_0, - \un75_ready0_1[4]\, \un60_ready0[4]\, N_13, - \un75_ready0[4]\, un62_readylto4, un77_ready, un69_ready, - N_198, N107, N161, N_197, \un75_ready1[5]\, N_16_i_i_0, - N_196, N83, un2_raddr_vect_slto1, un2_raddr_vect_s, - Waddr_vect_e0, Waddr_vect_e1, Waddr_vect_n1_i, - Waddr_vect_e4, Waddr_vect_e2, I_20_9, I_9_17, - \un10_raddr_vect_s[4]\, \un10_raddr_vect_s[2]\, - Waddr_vect_e3, I_13_17, I_5_17, I_20_10, I_13_18, I_9_18, - I_5_18, sEmpty_RNO_11, un1_sempty_s, \sEmpty\, N_9_0, - N_13_0, N_12_2, N_11, N_8, N_10, N_9_1, N_7, N_4_1, N_5, - N_6, N_9_2, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - sFull : DFN1C0 - port map(D => \un26_sfull_s\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Raddr_vect_RNICA1PH[1]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[1]\, B => - data_addr_r_iv_i_3(1), C => N_68, Y => - Raddr_vect_RNICA1PH(1)); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => data_mem_wen_i_0(1), C - => \data_mem_addr_w_1[0]\, Y => Waddr_vect_e0); - - \Raddr_vect_RNIA2FB1[0]\ : MX2 - port map(A => \un60_ready1[4]\, B => \un60_ready0[4]\, S - => \data_mem_addr_r_1[0]\, Y => un62_readylto4); - - un75_ready_1_16_ADD_5x5_fast_I8_un1_Y : NOR3A - port map(A => N81, B => N_85_i, C => N_105_1, Y => - ADD_5x5_fast_I8_un1_Y_0); - - \Raddr_vect_RNI7873[3]\ : XNOR2 - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, Y => N_87); - - \Waddr_vect_RNIIOD6[0]\ : AO1B - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => un1_waddr_vect_slto3_0, Y - => un1_waddr_vect_slt4); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[0]\); - - sEmpty_RNIANF32 : NOR3A - port map(A => data_ren_1z, B => un20_time_write, C => - \sEmpty\, Y => data_mem_ren_i_0(1)); - - \Waddr_vect_RNO[3]\ : MX2A - port map(A => Waddr_vect_n3, B => \data_mem_addr_w_1[3]\, S - => data_mem_wen_i_0(1), Y => Waddr_vect_e3); - - un26_sfull_s_tz_RNO_5 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_1[0]\, - Y => \un8_waddr_vect_s[0]\); - - \Raddr_vect_RNI3O63[1]\ : NOR2A - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, Y => N_105_1); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_r_1[0]\, Y => N_12_0); - - un26_sfull_s_tz_RNO_3 : OR2B - port map(A => I_5_17, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - \ready_gen.un69_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_1[4]\, B => - \data_mem_addr_r_1[4]\, Y => N_11); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, Y => I_5_17); - - sEmpty_RNO_0 : NOR3B - port map(A => data_ren_1z, B => un7_sempty_s_4, C => - un20_time_write, Y => un7_sempty_s); - - \Waddr_vect_RNIE4CV[3]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[3]\, Y => N_134); - - un60_ready_1_1_0_SUM2_0 : AX1C - port map(A => N_87, B => CO1_tz, C => SUM2_0_0, Y => - \un60_ready1[4]\); - - \Raddr_vect_RNIU7FE[4]\ : NOR2B - port map(A => I_13_18, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un26_sfull_s_tz_RNO_6 : OR2B - port map(A => I_13_17, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Raddr_vect_RNI0G18[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_1[4]\, Y => - un2_raddr_vect_s); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, C => \data_mem_addr_r_1[2]\, Y - => N_9_0); - - \Raddr_vect_RNIB44A2[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_1[0]\, - Y => N_198); - - \ready_gen.un69_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, Y => N_5); - - \ready_gen.un69_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, C => N_4_1, Y => N_10); - - \Raddr_vect_RNIK66A4[1]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[1]\, C => N_67, Y => - \data_addr_r_iv_i_4[1]\); - - \Waddr_vect_RNO[4]\ : MX2A - port map(A => Waddr_vect_n4, B => \data_mem_addr_w_1[4]\, S - => data_mem_wen_i_0(1), Y => Waddr_vect_e4); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[1]\); - - un75_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : XOR2 - port map(A => N165, B => \un75_ready0_1[4]\, Y => - \un75_ready0[4]\); - - un60_ready_0_0_0_ADD_5x5_fast_I9_Y_i_o2 : AO13 - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => \data_mem_addr_r_1[1]\, Y - => N_9); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_2, B => \data_mem_addr_w_1[3]\, Y => - I_13_17); - - sFull_RNI8GOT : OR2B - port map(A => data_mem_wen_i_0(1), B => N_165, Y => N_166); - - GND_i : GND - port map(Y => \GND\); - - sEmpty_RNO_7 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_1[4]\, Y => sEmpty_RNO_7_0); - - sEmpty_RNIGNUI8 : NOR2B - port map(A => \data_addr_r_iv_i_a2_3[4]\, B => - data_addr_r_iv_i_a2_2(4), Y => N_86); - - \Raddr_vect_RNIT38B[4]\ : NOR2B - port map(A => I_5_18, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - un26_sfull_s_tz_RNO_0 : XA1 - port map(A => \data_mem_addr_r_1[1]\, B => - \un8_waddr_vect_s[1]\, C => \un26_sfull_s_tz_RNO_4\, Y - => un5_sfull_s_4_1); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => N_9_2); - - \Raddr_vect_RNI5073[2]\ : XNOR2 - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, Y => N_85_i); - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[2]\); - - un60_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0 : OR2A - port map(A => \data_mem_addr_r_1[3]\, B => - \data_mem_addr_w_1[3]\, Y => N_13); - - sEmpty_RNIJEV64 : NOR2 - port map(A => data_mem_ren_i_0(1), B => data_mem_ren_i_0(0), - Y => \data_addr_r_iv_i_a2_3[4]\); - - \ready_gen.un69_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_1[4]\, B => - \data_mem_addr_w_1[4]\, Y => N_7); - - un75_ready_1_16_ADD_5x5_fast_I1_P0N : OR2A - port map(A => \data_mem_addr_r_1[2]\, B => N_87, Y => N81); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_1 : OA1C - port map(A => N165, B => N_89_i, C => N_23, Y => N_14_1); - - un60_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3_0 : NOR2B - port map(A => N_9, B => \data_mem_addr_w_1[2]\, Y => N_18); - - \Waddr_vect_RNO_0[4]\ : AXO1 - port map(A => un1_waddr_vect_slt4, B => - \data_mem_addr_w_1[4]\, C => Waddr_vect_14_0, Y => - Waddr_vect_n4); - - sFull_RNIBVR9 : OR2 - port map(A => \sFull\, B => data_wen(1), Y => - data_mem_wen_i_0(1)); - - \Raddr_vect_RNIT3LC6[0]\ : AOI1 - port map(A => N_197, B => N_196, C => N_198, Y => - un77_ready); - - \Raddr_vect_RNI9G73_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_1[4]\, B => - \data_mem_addr_w_1[4]\, Y => N_75_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR2B - port map(A => N_14_1, B => N_75_i_0, Y => N161); - - un75_ready_1_16_ADD_5x5_fast_I2_G0N : OR2 - port map(A => N_109, B => N_89_i, Y => N83); - - sEmpty_RNO : OR2 - port map(A => un7_sempty_s, B => un1_sempty_s, Y => - sEmpty_RNO_11); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[3]\); - - un26_sfull_s : AND2 - port map(A => data_ren(1), B => \un26_sfull_s_tz\, Y => - \un26_sfull_s\); - - \Waddr_vect_RNIB473[3]\ : NOR2 - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_w_1[2]\, Y => un1_waddr_vect_slto3_0); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, Y => N_12); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_1[1]\, B => - \un10_raddr_vect_s[1]\, C => sEmpty_RNO_6_2, Y => - un7_sempty_s_1); - - un26_sfull_s_tz_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_17, C => - \data_mem_addr_r_1[2]\, Y => \un26_sfull_s_tz_RNO_4\); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4 : AO1B - port map(A => ADD_7x7_fast_I19_Y_i_o4_1_0, B => N_9, C => - N80, Y => N165); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_1[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[4]\); - - \ready_gen.un69_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, C => N_6, Y => N_8); - - \Raddr_vect_RNIOM6A4[3]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[3]\, C => N_51, Y => - \data_addr_r_iv_i_4[3]\); - - \Raddr_vect_RNIE6Q5I[3]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[3]\, B => - data_addr_r_iv_i_3(3), C => N_52, Y => - Raddr_vect_RNIE6Q5I(3)); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - \Raddr_vect_RNI003G[4]\ : NOR2B - port map(A => I_20_10, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXOI5 - port map(A => N_87, B => \data_mem_addr_r_1[2]\, C => - \data_mem_addr_w_1[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - \ready_gen.un69_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, C => N_7, Y => N_12_2); - - un26_sfull_s_tz : OR2 - port map(A => \sFull\, B => un5_sfull_s_4, Y => - \un26_sfull_s_tz\); - - un75_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_14_1, B => N83, C => N_75_i_0, Y => - N_16_i_i_0); - - \Waddr_vect_RNID0CV[2]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[2]\, Y => N_142); - - \Raddr_vect_RNIKA2PH[2]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[2]\, B => - data_addr_r_iv_i_3(2), C => N_60, Y => - Raddr_vect_RNIKA2PH(2)); - - \Raddr_vect_RNIUNK9[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_1[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[0]\); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_1[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Raddr_vect_RNI9G73[4]\ : XNOR2 - port map(A => \data_mem_addr_w_1[4]\, B => - \data_mem_addr_r_1[4]\, Y => N_89_i); - - \Waddr_vect_RNIF8CV[4]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[4]\, Y => N_126); - - \Raddr_vect_RNIIU5A4[0]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[0]\, C => N_75, Y => - \data_addr_r_iv_i_4[0]\); - - \Raddr_vect_RNION3L8[0]\ : MX2 - port map(A => un62_readylto4, B => un77_ready, S => - un69_ready, Y => ready_i_0(1)); - - un60_ready_1_1_0_SUM2_0_0 : XNOR2 - port map(A => N_109, B => N_89_i, Y => SUM2_0_0); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_1[2]\, Y => - I_9_18); - - \ready_gen.un69_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, Y => N_4_1); - - \Raddr_vect_RNITJ63[1]\ : OR2B - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_r_1[0]\, Y => un2_raddr_vect_slto1); - - un75_ready_0_0_0_ADD_7x7_fast_I32_Y_0_1 : XOR2 - port map(A => N_109, B => N_89_i, Y => \un75_ready0_1[4]\); - - un60_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2 : OR3 - port map(A => N_17, B => ADD_5x5_fast_I11_Y_i_a2_0, C => - N_18, Y => N_12_1); - - un75_ready_1_16_ADD_5x5_fast_I10_Y : OR3A - port map(A => N_75_i_0, B => I11_un1_Y, C => - ADD_5x5_fast_I11_Y_0, Y => N107); - - \Waddr_vect_RNICSBV[1]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[1]\, Y => N_150); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4 : NOR3B - port map(A => N_9, B => ADD_7x7_fast_I19_Y_i_o4_1_0, C => - N_109, Y => N_23); - - un26_sfull_s_tz_RNO : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, C => \data_mem_addr_r_1[2]\, Y - => \DWACT_FINC_E_0[0]\); - - \Raddr_vect_RNIN2UH1[0]\ : MX2C - port map(A => \un75_ready1[4]\, B => \un75_ready0[4]\, S - => \data_mem_addr_r_1[0]\, Y => N_196); - - \Waddr_vect_RNIC4Q4[0]\ : NOR3C - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => Waddr_vect_c2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_1[3]\, Y - => Waddr_vect_14_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \Waddr_vect_RNIPG18[4]\ : OR2B - port map(A => un1_waddr_vect_slt4, B => - \data_mem_addr_w_1[4]\, Y => un1_waddr_vect_s); - - un75_ready_1_16_ADD_5x5_fast_I11_un1_Y_0 : NOR3A - port map(A => N81, B => N_85_i, C => N_105_1, Y => - ADD_5x5_fast_I11_un1_Y_0); - - un26_sfull_s_tz_RNO_7 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_9, C => - \data_mem_addr_r_1[4]\, Y => \un26_sfull_s_tz_RNO_7\); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_1[4]\, Y => I_20_9); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[1]\); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_1[2]\, Y => sEmpty_RNO_6_2); - - \Raddr_vect_RNIQU6A4[4]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[4]\, C => N_43, Y => - \data_addr_r_iv_i_4[4]\); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9_0, B => \data_mem_addr_r_1[3]\, Y => - I_13_18); - - un26_sfull_s_tz_RNO_1 : XA1B - port map(A => \data_mem_addr_r_1[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(1), Y => - un5_sfull_s_4_0); - - \ready_gen.un69_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_1, Y => N_13_0); - - \ready_gen.un69_ready_0_I_11\ : OA1 - port map(A => N_13_0, B => N_12_2, C => N_11, Y => - un69_ready); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \data_mem_addr_w_1[2]\, S - => data_mem_wen_i_0(1), Y => Waddr_vect_e2); - - un60_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0_0 : AO1C - port map(A => \data_mem_addr_r_1[2]\, B => - \data_mem_addr_w_1[2]\, C => N_109, Y => - ADD_5x5_fast_I11_Y_i_a2_0); - - \Waddr_vect_RNIBOBV[0]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[0]\, Y => N_158); - - sEmpty_RNO_2 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - un60_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3 : NOR2A - port map(A => N_9, B => \data_mem_addr_r_1[2]\, Y => N_17); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_1[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(1), Y => - un7_sempty_s_0); - - un75_ready_1_16_ADD_5x5_fast_I11_un1_Y : AOI1B - port map(A => N_109, B => N_89_i, C => - ADD_5x5_fast_I11_un1_Y_0, Y => I11_un1_Y); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, Y => I_5_18); - - \Raddr_vect_RNITJRC[4]\ : NOR2B - port map(A => I_9_18, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \ready_gen.un69_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, C => N_5, Y => N_9_1); - - un26_sfull_s_tz_RNO_2 : XA1 - port map(A => \data_mem_addr_r_1[3]\, B => - \un8_waddr_vect_s[3]\, C => \un26_sfull_s_tz_RNO_7\, Y - => un5_sfull_s_4_2); - - un60_ready_1_1_0_CO1_tz : AO18 - port map(A => N_105_1, B => \data_mem_addr_w_1[2]\, C => - \data_mem_addr_r_1[2]\, Y => CO1_tz); - - \ready_gen.un69_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_w_1[0]\, Y => N_6); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_11, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Raddr_vect_RNIRSIG2[0]\ : MX2C - port map(A => \un75_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_1[0]\, Y => N_197); - - \Raddr_vect_RNI4A0PH[0]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[0]\, B => - data_addr_r_iv_i_3(0), C => N_76, Y => - Raddr_vect_RNI4A0PH(0)); - - un75_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1D - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75_i_0, Y => \un75_ready1[5]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \data_mem_addr_w_1[1]\, - S => data_mem_wen_i_0(1), Y => Waddr_vect_e1); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[2]\); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => \DWACT_FINC_E[0]\); - - \Raddr_vect_RNI7873_0[3]\ : OR2A - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, Y => N_109); - - \Raddr_vect_RNI1473[3]\ : NOR2 - port map(A => \data_mem_addr_r_1[3]\, B => - \data_mem_addr_r_1[2]\, Y => un2_raddr_vect_slto3_0); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[3]\); - - \Raddr_vect_RNIIMQ5I[4]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[4]\, B => - data_addr_r_iv_i_3(4), C => N_44, Y => - Raddr_vect_RNIIMQ5I(4)); - - sEmpty_RNO_5 : XA1A - port map(A => \data_mem_addr_w_1[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_7_0, Y => - un7_sempty_s_2); - - un75_ready_1_16_ADD_5x5_fast_I1_G0N : AO1C - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, C => N_87, Y => N80); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_1[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - un60_ready_0_0_0_ADD_5x5_fast_I18_Y_0 : AX1C - port map(A => N_12_1, B => N_13, C => N_89_i, Y => - \un60_ready0[4]\); - - un75_ready_1_16_ADD_5x5_fast_I15_Y_0 : AX1A - port map(A => ADD_5x5_fast_I8_un1_Y_0, B => N80, C => - \un75_ready0_1[4]\, Y => \un75_ready1[4]\); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[4]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_1[2]\, Y => - I_9_17); - - un75_ready_1_16_ADD_5x5_fast_I11_Y_0 : MIN3 - port map(A => N_89_i, B => N_109, C => N80, Y => - ADD_5x5_fast_I11_Y_0); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(1), Y => un1_sempty_s); - - sFull_RNICGOT : OR3B - port map(A => data_mem_wen_i_0(1), B => data_mem_wen_i_0(2), - C => N_164, Y => N_120_i); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => Waddr_vect_n2_tz); - - \Raddr_vect_RNIME6A4[2]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[2]\, C => N_59, Y => - \data_addr_r_iv_i_4[2]\); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_1[4]\, Y => - I_20_10); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ7 is - - port( time_mem_addr_w_3_i_0_1 : out std_logic; - data_addr_w_1_iv_i_a2_1_1_0 : in std_logic_vector(6 to 6); - data_addr_w_1_iv_i_s_0_0 : out std_logic_vector(6 to 6); - time_wen : in std_logic_vector(3 to 3); - time_ren : in std_logic_vector(3 to 3); - data_mem_ren_i_0 : in std_logic_vector(1 to 1); - time_mem_ren_i_0 : out std_logic_vector(3 to 3); - data_addr_r_1_iv_i_a9_1_1 : out std_logic_vector(6 to 6); - time_mem_addr_w_3 : out std_logic_vector(1 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_124 : out std_logic; - N_64 : out std_logic; - N_140 : out std_logic; - N_30_1 : out std_logic; - N_89 : out std_logic; - N_163 : in std_logic; - N_164 : out std_logic; - N_72 : out std_logic; - N_56 : out std_logic; - N_48 : out std_logic; - N_35 : out std_logic; - N_113 : in std_logic; - N_162 : in std_logic; - N_77 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ7; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ7 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_7, \time_mem_addr_r_3[1]\, \time_mem_addr_r_3[0]\, - N_7_0, un5_sfull_s_3, sFull_RNO_3_0, sFull_RNO_4_0, - un5_sfull_s_0, un5_sfull_s_2, \Raddr_vect[3]_net_1\, - \un8_waddr_vect_s[3]\, \un8_waddr_vect_s[0]\, - un7_sempty_s_3, sEmpty_RNO_3_2, sEmpty_RNO_4_2, - un7_sempty_s_0, un7_sempty_s_2, \Waddr_vect[3]_net_1\, - \un10_raddr_vect_s[3]\, \un10_raddr_vect_s[0]\, - \time_mem_addr_w_3[0]\, \data_addr_w_1_iv_i_s_0_tz[6]\, - un2_raddr_vect_slt3, \time_mem_addr_r_3_i_0[2]\, - un1_waddr_vect_slt3, \time_mem_addr_w_3[1]\, - \time_mem_addr_w_3_i_0[2]\, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, - \time_mem_addr_w_3_i_0[5]\, \time_mem_wen_i_0[3]\, - Raddr_vect_n2, un2_raddr_vect_s, Raddr_vect_n2_tz, - Waddr_vect_n2, un1_waddr_vect_s, Waddr_vect_n2_tz, I_13_3, - I_5_3, I_9_3, \time_mem_addr_r_3_i_0[5]\, - \time_mem_ren_i_0[3]\, \time_mem_addr_r_3_i_0[3]\, - Raddr_vect_n1_i, Raddr_vect_e2, Raddr_vect_e1, - Raddr_vect_e0, \N_89\, Waddr_vect_e2, Waddr_vect_e0, - Waddr_vect_e1, Waddr_vect_n1_i, I_13_4, I_5_4, I_9_4, - \sFull_RNO\, un8_sfull_s, \sEmpty_RNO\, un2_sempty_s, - \sFull\, \sEmpty\, N_4, N_4_0, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - time_mem_ren_i_0(3) <= \time_mem_ren_i_0[3]\; - time_mem_addr_w_3(1) <= \time_mem_addr_w_3[1]\; - time_mem_addr_w_3(0) <= \time_mem_addr_w_3[0]\; - N_89 <= \N_89\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_3[1]\, B => - \time_mem_addr_w_3[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => N_4); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_3[1]\, B => - \time_mem_addr_r_3[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - \Raddr_vect_RNICJ9L[2]\ : OR2A - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \time_mem_ren_i_0[3]\, Y => N_56); - - sFull_RNIR3CG : OR2B - port map(A => \time_mem_addr_w_3_i_0[5]\, B => \N_89\, Y - => N_124); - - sEmpty_RNIBEFO_1 : OR2 - port map(A => \time_mem_ren_i_0[3]\, B => - \time_mem_addr_r_3_i_0[5]\, Y => N_30_1); - - \Waddr_vect_RNI6PG9[1]\ : OR3 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => un1_waddr_vect_slt3); - - un43_mem_addr_ren_1_SUM1_0 : XNOR2 - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_3_i_0[3]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_3[1]\, B => - \time_mem_addr_w_3[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_3[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_wen_i_0[3]\, Q => - \Waddr_vect[3]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \time_mem_addr_r_3_i_0[2]\, Y => - I_9_4); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO\, CLK => HCLK_c, PRE => HRESETn_c, - Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[3]\, - C => \time_mem_addr_w_3[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_3_i_0[2]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_3[1]\, - S => \time_mem_wen_i_0[3]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, Y => I_5_3); - - \Raddr_vect_RNIMJMC[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - sEmpty_RNIFCRP3 : NOR3B - port map(A => N_77, B => \time_mem_ren_i_0[3]\, C => - data_mem_ren_i_0(1), Y => data_addr_r_1_iv_i_a9_1_1(6)); - - \Waddr_vect_RNIN86D[2]\ : OR2B - port map(A => \time_mem_addr_w_3_i_0[2]\, B => \N_89\, Y - => N_140); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_ren_i_0[3]\, Q => - \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(3), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4, B => \Waddr_vect[3]_net_1\, Y => I_13_3); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[3]\, - C => \time_mem_addr_r_3[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_3[1]\, - S => \time_mem_ren_i_0[3]\, Y => Raddr_vect_e1); - - sFull_RNIKH0A_0 : NOR2A - port map(A => N_163, B => \time_mem_wen_i_0[3]\, Y => - \N_89\); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_3, C => - \time_mem_addr_r_3[1]\, Y => sFull_RNO_4_0); - - sFull_RNO_6 : OR2B - port map(A => I_13_3, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_4, C => - \time_mem_addr_w_3_i_0[2]\, Y => sEmpty_RNO_3_2); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_3_i_0[2]\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_3[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_3[0]\, C => time_wen(3), Y => - un5_sfull_s_0); - - sFull_RNIQOVC1 : OA1 - port map(A => N_162, B => \data_addr_w_1_iv_i_s_0_tz[6]\, C - => N_113, Y => data_addr_w_1_iv_i_s_0_0(6)); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => - \time_mem_addr_w_3_i_0[2]\, S => \time_mem_wen_i_0[3]\, Y - => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_4, C => - \time_mem_addr_w_3[1]\, Y => sEmpty_RNO_4_2); - - un50_mem_addr_wen_1_SUM1_0 : XNOR2 - port map(A => \time_mem_addr_w_3_i_0[2]\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_3_i_0_1); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_3, C => - \time_mem_addr_r_3_i_0[2]\, Y => sFull_RNO_3_0); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_2, B => sEmpty_RNO_4_2, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => Waddr_vect_n2_tz); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => Raddr_vect_n2_tz); - - sEmpty_RNO_7 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_3[0]\, - Y => \un10_raddr_vect_s[0]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => - \time_mem_addr_r_3_i_0[2]\, S => \time_mem_ren_i_0[3]\, Y - => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_3[0]\); - - sEmpty_RNIBEFO_0 : OR2A - port map(A => \time_mem_addr_r_3_i_0[3]\, B => - \time_mem_ren_i_0[3]\, Y => N_48); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_3[1]\, B => - \time_mem_addr_r_3[0]\, Y => N_7); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \time_mem_addr_w_3_i_0[2]\, Y => - I_9_3); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_0, B => \Raddr_vect[3]_net_1\, Y => - I_13_4); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => N_4_0); - - sFull_RNIBLJS : MX2B - port map(A => \time_mem_addr_w_3_i_0[5]\, B => - data_addr_w_1_iv_i_a2_1_1_0(6), S => - \time_mem_wen_i_0[3]\, Y => - \data_addr_w_1_iv_i_s_0_tz[6]\); - - sFull_RNIG4G2 : OR2 - port map(A => time_wen(3), B => \sFull\, Y => - \time_mem_wen_i_0[3]\); - - \Raddr_vect_RNINOG9[1]\ : OR3 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => un2_raddr_vect_slt3); - - sEmpty_RNO_1 : XA1B - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, C => time_ren(3), Y => - un7_sempty_s_2); - - sFull_RNO_1 : XA1 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, C => time_ren(3), Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, Y => I_5_4); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => Waddr_vect_15_0); - - sFull_RNO_7 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_3[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNIBEFO : OR2A - port map(A => \time_mem_addr_r_3_i_0[5]\, B => - \time_mem_ren_i_0[3]\, Y => N_35); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => Raddr_vect_7_0); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => sFull_RNO_3_0, B => sFull_RNO_4_0, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2B - port map(A => I_13_4, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un43_mem_addr_ren_1_CO1 : NOR2B - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_3_i_0[5]\); - - sFull : DFN1C0 - port map(D => \sFull_RNO\, CLK => HCLK_c, CLR => HRESETn_c, - Q => \sFull\); - - \Waddr_vect_RNIAKMC[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - un50_mem_addr_wen_1_CO1 : NOR2B - port map(A => \time_mem_addr_w_3_i_0[2]\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_3_i_0[5]\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_3[1]\); - - sEmpty_RNIES3I : OR2 - port map(A => time_ren(3), B => \sEmpty\, Y => - \time_mem_ren_i_0[3]\); - - \Raddr_vect_RNIBF9L[1]\ : OR2 - port map(A => \time_mem_ren_i_0[3]\, B => - \time_mem_addr_r_3[1]\, Y => N_64); - - sFull_RNO_2 : NOR2B - port map(A => time_ren(3), B => \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_3[0]\, C => time_wen(3), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - \Raddr_vect_RNIAB9L[0]\ : OR2 - port map(A => \time_mem_ren_i_0[3]\, B => - \time_mem_addr_r_3[0]\, Y => N_72); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - sFull_RNIKH0A : OR2B - port map(A => \time_mem_wen_i_0[3]\, B => N_163, Y => N_164); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity generic_syncram_2p_7_32_0 is - - port( wdata : in std_logic_vector(31 downto 0); - Waddr_vect_RNILLSP5 : in std_logic_vector(4 to 4); - Waddr_vect_RNIJTNE5 : in std_logic_vector(3 to 3); - Waddr_vect_RNI394D5 : in std_logic_vector(2 to 2); - Waddr_vect_RNI0O455 : in std_logic_vector(1 to 1); - Waddr_vect_RNION355 : in std_logic_vector(0 to 0); - Raddr_vect_RNIIMQ5I : in std_logic_vector(4 to 4); - Raddr_vect_RNIE6Q5I : in std_logic_vector(3 to 3); - Raddr_vect_RNIKA2PH : in std_logic_vector(2 to 2); - Raddr_vect_RNICA1PH : in std_logic_vector(1 to 1); - Raddr_vect_RNI4A0PH : in std_logic_vector(0 to 0); - hwdata_c : out std_logic_vector(31 downto 0); - N_1_i_1_i : in std_logic; - generic_syncram_2p_7_32_0_VCC : in std_logic; - generic_syncram_2p_7_32_0_GND : in std_logic; - sFull_RNIU5GK1 : in std_logic; - sFull_RNIHL443 : in std_logic; - sEmpty_RNILSD08 : in std_logic; - sEmpty_RNIE7T87 : in std_logic; - N_1_i_1 : in std_logic; - HCLK_c : in std_logic - ); - -end generic_syncram_2p_7_32_0; - -architecture DEF_ARCH of generic_syncram_2p_7_32_0 is - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component RAM512X18 - generic (MEMORYFILE:string := ""); - - port( RADDR8 : in std_logic := 'U'; - RADDR7 : in std_logic := 'U'; - RADDR6 : in std_logic := 'U'; - RADDR5 : in std_logic := 'U'; - RADDR4 : in std_logic := 'U'; - RADDR3 : in std_logic := 'U'; - RADDR2 : in std_logic := 'U'; - RADDR1 : in std_logic := 'U'; - RADDR0 : in std_logic := 'U'; - WADDR8 : in std_logic := 'U'; - WADDR7 : in std_logic := 'U'; - WADDR6 : in std_logic := 'U'; - WADDR5 : in std_logic := 'U'; - WADDR4 : in std_logic := 'U'; - WADDR3 : in std_logic := 'U'; - WADDR2 : in std_logic := 'U'; - WADDR1 : in std_logic := 'U'; - WADDR0 : in std_logic := 'U'; - WD17 : in std_logic := 'U'; - WD16 : in std_logic := 'U'; - WD15 : in std_logic := 'U'; - WD14 : in std_logic := 'U'; - WD13 : in std_logic := 'U'; - WD12 : in std_logic := 'U'; - WD11 : in std_logic := 'U'; - WD10 : in std_logic := 'U'; - WD9 : in std_logic := 'U'; - WD8 : in std_logic := 'U'; - WD7 : in std_logic := 'U'; - WD6 : in std_logic := 'U'; - WD5 : in std_logic := 'U'; - WD4 : in std_logic := 'U'; - WD3 : in std_logic := 'U'; - WD2 : in std_logic := 'U'; - WD1 : in std_logic := 'U'; - WD0 : in std_logic := 'U'; - RW0 : in std_logic := 'U'; - RW1 : in std_logic := 'U'; - WW0 : in std_logic := 'U'; - WW1 : in std_logic := 'U'; - PIPE : in std_logic := 'U'; - REN : in std_logic := 'U'; - WEN : in std_logic := 'U'; - RCLK : in std_logic := 'U'; - WCLK : in std_logic := 'U'; - RESET : in std_logic := 'U'; - RD17 : out std_logic; - RD16 : out std_logic; - RD15 : out std_logic; - RD14 : out std_logic; - RD13 : out std_logic; - RD12 : out std_logic; - RD11 : out std_logic; - RD10 : out std_logic; - RD9 : out std_logic; - RD8 : out std_logic; - RD7 : out std_logic; - RD6 : out std_logic; - RD5 : out std_logic; - RD4 : out std_logic; - RD3 : out std_logic; - RD2 : out std_logic; - RD1 : out std_logic; - RD0 : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal N_7_0, I_5_1, I_5_0, I_5_5, I_4_5_i_0, I_4_4_i_0, - I_5_3, \RADDR_REG1[6]\, \WADDR_REG1[6]\, N_5, - \RADDR_REG1[2]\, \WADDR_REG1[2]\, I_4_3_i_0, - \RADDR_REG1[0]\, \WADDR_REG1[0]\, I_4_1_i_0, N_7, - \DOUT_TMP[13]\, \DIN_REG1[13]\, \DOUT_TMP[12]\, - \DIN_REG1[12]\, \DOUT_TMP[11]\, \DIN_REG1[11]\, - \DOUT_TMP[10]\, \DIN_REG1[10]\, \DOUT_TMP[9]\, - \DIN_REG1[9]\, \DOUT_TMP[8]\, \DIN_REG1[8]\, - \DOUT_TMP[7]\, \DIN_REG1[7]\, \DOUT_TMP[6]\, - \DIN_REG1[6]\, \DOUT_TMP[5]\, \DIN_REG1[5]\, - \DOUT_TMP[4]\, \DIN_REG1[4]\, \DOUT_TMP[3]\, - \DIN_REG1[3]\, \DOUT_TMP[2]\, \DIN_REG1[2]\, - \DOUT_TMP[1]\, \DIN_REG1[1]\, \DOUT_TMP[0]\, - \DIN_REG1[0]\, \DOUT_TMP[17]\, \DIN_REG1[17]\, - \DOUT_TMP[16]\, \DIN_REG1[16]\, \DOUT_TMP[15]\, - \DIN_REG1[15]\, \DOUT_TMP[14]\, \DIN_REG1[14]\, - \DOUT_TMP_0[13]\, \DIN_REG1_0[13]\, \DOUT_TMP_0[12]\, - \DIN_REG1_0[12]\, \DOUT_TMP_0[11]\, \DIN_REG1_0[11]\, - \DOUT_TMP_0[10]\, \DIN_REG1_0[10]\, \DOUT_TMP_0[9]\, - \DIN_REG1_0[9]\, \DOUT_TMP_0[8]\, \DIN_REG1_0[8]\, - \DOUT_TMP_0[7]\, \DIN_REG1_0[7]\, \DOUT_TMP_0[6]\, - \DIN_REG1_0[6]\, \DOUT_TMP_0[5]\, \DIN_REG1_0[5]\, - \DOUT_TMP_0[4]\, \DIN_REG1_0[4]\, \DOUT_TMP_0[3]\, - \DIN_REG1_0[3]\, \DOUT_TMP_0[2]\, \DIN_REG1_0[2]\, - \DOUT_TMP_0[1]\, \DIN_REG1_0[1]\, \DOUT_TMP_0[0]\, - \DIN_REG1_0[0]\, \WADDR_REG1[5]\, \RADDR_REG1[5]\, - \WADDR_REG1[4]\, \RADDR_REG1[4]\, \WADDR_REG1[3]\, - \RADDR_REG1[3]\, \WADDR_REG1[1]\, \RADDR_REG1[1]\, - \DOUT_TMP_0[14]\, \DOUT_TMP_0[15]\, \DOUT_TMP_0[16]\, - \DOUT_TMP_0[17]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \rfd_tile_RADDR_REG1_RNIG9I4[2]\ : XA1A - port map(A => \RADDR_REG1[2]\, B => \WADDR_REG1[2]\, C => - I_4_3_i_0, Y => I_5_1); - - \rfd_tile_DIN_REG1[9]\ : DFN1 - port map(D => wdata(9), CLK => HCLK_c, Q => \DIN_REG1_0[9]\); - - \rfd_tile_0_DIN_REG1[0]\ : DFN1 - port map(D => wdata(18), CLK => HCLK_c, Q => \DIN_REG1[0]\); - - \rfd_tile_RADDR_REG1[5]\ : DFN1 - port map(D => sEmpty_RNIE7T87, CLK => HCLK_c, Q => - \RADDR_REG1[5]\); - - \rfd_tile_0_DIN_REG1[12]\ : DFN1 - port map(D => wdata(30), CLK => HCLK_c, Q => \DIN_REG1[12]\); - - \rfd_tile_WADDR_REG1[6]\ : DFN1 - port map(D => sFull_RNIU5GK1, CLK => HCLK_c, Q => - \WADDR_REG1[6]\); - - rfd_tile_I_3 : DFN1 - port map(D => N_1_i_1, CLK => HCLK_c, Q => N_5); - - \rfd_tile_RADDR_REG1_RNI89H4[0]\ : XA1A - port map(A => \RADDR_REG1[0]\, B => \WADDR_REG1[0]\, C => - I_4_1_i_0, Y => I_5_0); - - rfd_tile_0_I_1_RNIK6BO : MX2 - port map(A => \DOUT_TMP[6]\, B => \DIN_REG1[6]\, S => N_7_0, - Y => hwdata_c(24)); - - rfd_tile_I_1_RNI83001 : MX2 - port map(A => \DOUT_TMP_0[13]\, B => \DIN_REG1_0[13]\, S - => N_7, Y => hwdata_c(13)); - - \rfd_tile_0_DIN_REG1[11]\ : DFN1 - port map(D => wdata(29), CLK => HCLK_c, Q => \DIN_REG1[11]\); - - \rfd_tile_DIN_REG1[10]\ : DFN1 - port map(D => wdata(10), CLK => HCLK_c, Q => - \DIN_REG1_0[10]\); - - rfd_tile_0_I_1_RNIGMAO : MX2 - port map(A => \DOUT_TMP[2]\, B => \DIN_REG1[2]\, S => N_7_0, - Y => hwdata_c(20)); - - rfd_tile_I_1_RNIA3001 : MX2 - port map(A => \DOUT_TMP[15]\, B => \DIN_REG1[15]\, S => N_7, - Y => hwdata_c(15)); - - \rfd_tile_DIN_REG1_RNIROBR[7]\ : MX2 - port map(A => \DOUT_TMP_0[7]\, B => \DIN_REG1_0[7]\, S => - N_7, Y => hwdata_c(7)); - - \rfd_tile_WADDR_REG1[4]\ : DFN1 - port map(D => Waddr_vect_RNILLSP5(4), CLK => HCLK_c, Q => - \WADDR_REG1[4]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \rfd_tile_DIN_REG1_RNIM4BR[2]\ : MX2 - port map(A => \DOUT_TMP_0[2]\, B => \DIN_REG1_0[2]\, S => - N_7, Y => hwdata_c(2)); - - \rfd_tile_DIN_REG1[0]\ : DFN1 - port map(D => wdata(0), CLK => HCLK_c, Q => \DIN_REG1_0[0]\); - - \rfd_tile_DIN_REG1[5]\ : DFN1 - port map(D => wdata(5), CLK => HCLK_c, Q => \DIN_REG1_0[5]\); - - \rfd_tile_0_DIN_REG1[6]\ : DFN1 - port map(D => wdata(24), CLK => HCLK_c, Q => \DIN_REG1[6]\); - - \rfd_tile_0_DIN_REG1[1]\ : DFN1 - port map(D => wdata(19), CLK => HCLK_c, Q => \DIN_REG1[1]\); - - \rfd_tile_RADDR_REG1_RNILO82[1]\ : XNOR2 - port map(A => \WADDR_REG1[1]\, B => \RADDR_REG1[1]\, Y => - I_4_1_i_0); - - \rfd_tile_DIN_REG1[4]\ : DFN1 - port map(D => wdata(4), CLK => HCLK_c, Q => \DIN_REG1_0[4]\); - - \rfd_tile_DIN_REG1[3]\ : DFN1 - port map(D => wdata(3), CLK => HCLK_c, Q => \DIN_REG1_0[3]\); - - \rfd_tile_DIN_REG1[2]\ : DFN1 - port map(D => wdata(2), CLK => HCLK_c, Q => \DIN_REG1_0[2]\); - - rfd_tile_0_I_1_RNIHQAO : MX2 - port map(A => \DOUT_TMP[3]\, B => \DIN_REG1[3]\, S => N_7_0, - Y => hwdata_c(21)); - - \rfd_tile_0_DIN_REG1[2]\ : DFN1 - port map(D => wdata(20), CLK => HCLK_c, Q => \DIN_REG1[2]\); - - rfd_tile_0_I_1 : RAM512X18 - port map(RADDR8 => generic_syncram_2p_7_32_0_GND, RADDR7 - => generic_syncram_2p_7_32_0_GND, RADDR6 => - sEmpty_RNILSD08, RADDR5 => sEmpty_RNIE7T87, RADDR4 => - Raddr_vect_RNIIMQ5I(4), RADDR3 => Raddr_vect_RNIE6Q5I(3), - RADDR2 => Raddr_vect_RNIKA2PH(2), RADDR1 => - Raddr_vect_RNICA1PH(1), RADDR0 => Raddr_vect_RNI4A0PH(0), - WADDR8 => generic_syncram_2p_7_32_0_GND, WADDR7 => - generic_syncram_2p_7_32_0_GND, WADDR6 => sFull_RNIU5GK1, - WADDR5 => sFull_RNIHL443, WADDR4 => - Waddr_vect_RNILLSP5(4), WADDR3 => Waddr_vect_RNIJTNE5(3), - WADDR2 => Waddr_vect_RNI394D5(2), WADDR1 => - Waddr_vect_RNI0O455(1), WADDR0 => Waddr_vect_RNION355(0), - WD17 => generic_syncram_2p_7_32_0_GND, WD16 => - generic_syncram_2p_7_32_0_GND, WD15 => - generic_syncram_2p_7_32_0_GND, WD14 => - generic_syncram_2p_7_32_0_GND, WD13 => wdata(31), WD12 - => wdata(30), WD11 => wdata(29), WD10 => wdata(28), WD9 - => wdata(27), WD8 => wdata(26), WD7 => wdata(25), WD6 - => wdata(24), WD5 => wdata(23), WD4 => wdata(22), WD3 - => wdata(21), WD2 => wdata(20), WD1 => wdata(19), WD0 - => wdata(18), RW0 => generic_syncram_2p_7_32_0_GND, RW1 - => generic_syncram_2p_7_32_0_VCC, WW0 => - generic_syncram_2p_7_32_0_GND, WW1 => - generic_syncram_2p_7_32_0_VCC, PIPE => - generic_syncram_2p_7_32_0_GND, REN => - generic_syncram_2p_7_32_0_GND, WEN => N_1_i_1_i, RCLK => - HCLK_c, WCLK => HCLK_c, RESET => - generic_syncram_2p_7_32_0_VCC, RD17 => \DOUT_TMP_0[17]\, - RD16 => \DOUT_TMP_0[16]\, RD15 => \DOUT_TMP_0[15]\, RD14 - => \DOUT_TMP_0[14]\, RD13 => \DOUT_TMP[13]\, RD12 => - \DOUT_TMP[12]\, RD11 => \DOUT_TMP[11]\, RD10 => - \DOUT_TMP[10]\, RD9 => \DOUT_TMP[9]\, RD8 => - \DOUT_TMP[8]\, RD7 => \DOUT_TMP[7]\, RD6 => \DOUT_TMP[6]\, - RD5 => \DOUT_TMP[5]\, RD4 => \DOUT_TMP[4]\, RD3 => - \DOUT_TMP[3]\, RD2 => \DOUT_TMP[2]\, RD1 => \DOUT_TMP[1]\, - RD0 => \DOUT_TMP[0]\); - - \rfd_tile_DIN_REG1[12]\ : DFN1 - port map(D => wdata(12), CLK => HCLK_c, Q => - \DIN_REG1_0[12]\); - - \rfd_tile_0_DIN_REG1[5]\ : DFN1 - port map(D => wdata(23), CLK => HCLK_c, Q => \DIN_REG1[5]\); - - rfd_tile_0_I_1_RNIMEBO : MX2 - port map(A => \DOUT_TMP[8]\, B => \DIN_REG1[8]\, S => N_7_0, - Y => hwdata_c(26)); - - \rfd_tile_0_DIN_REG1[3]\ : DFN1 - port map(D => wdata(21), CLK => HCLK_c, Q => \DIN_REG1[3]\); - - \rfd_tile_RADDR_REG1_RNIRG92[4]\ : XNOR2 - port map(A => \WADDR_REG1[4]\, B => \RADDR_REG1[4]\, Y => - I_4_4_i_0); - - rfd_tile_0_I_1_RNIIUAO : MX2 - port map(A => \DOUT_TMP[4]\, B => \DIN_REG1[4]\, S => N_7_0, - Y => hwdata_c(22)); - - \rfd_tile_DIN_REG1_RNIPGBR[5]\ : MX2 - port map(A => \DOUT_TMP_0[5]\, B => \DIN_REG1_0[5]\, S => - N_7, Y => hwdata_c(5)); - - rfd_tile_I_1_RNI53001 : MX2 - port map(A => \DOUT_TMP_0[10]\, B => \DIN_REG1_0[10]\, S - => N_7, Y => hwdata_c(10)); - - \rfd_tile_DIN_REG1[15]\ : DFN1 - port map(D => wdata(15), CLK => HCLK_c, Q => \DIN_REG1[15]\); - - rfd_tile_0_I_1_RNIB01O : MX2 - port map(A => \DOUT_TMP[12]\, B => \DIN_REG1[12]\, S => - N_7_0, Y => hwdata_c(30)); - - \rfd_tile_RADDR_REG1[0]\ : DFN1 - port map(D => Raddr_vect_RNI4A0PH(0), CLK => HCLK_c, Q => - \RADDR_REG1[0]\); - - \rfd_tile_WADDR_REG1[5]\ : DFN1 - port map(D => sFull_RNIHL443, CLK => HCLK_c, Q => - \WADDR_REG1[5]\); - - \rfd_tile_RADDR_REG1[2]\ : DFN1 - port map(D => Raddr_vect_RNIKA2PH(2), CLK => HCLK_c, Q => - \RADDR_REG1[2]\); - - rfd_tile_0_I_1_RNILABO : MX2 - port map(A => \DOUT_TMP[7]\, B => \DIN_REG1[7]\, S => N_7_0, - Y => hwdata_c(25)); - - rfd_tile_0_I_1_RNIFIAO : MX2 - port map(A => \DOUT_TMP[1]\, B => \DIN_REG1[1]\, S => N_7_0, - Y => hwdata_c(19)); - - \rfd_tile_0_DIN_REG1[9]\ : DFN1 - port map(D => wdata(27), CLK => HCLK_c, Q => \DIN_REG1[9]\); - - \rfd_tile_DIN_REG1[1]\ : DFN1 - port map(D => wdata(1), CLK => HCLK_c, Q => \DIN_REG1_0[1]\); - - \rfd_tile_RADDR_REG1_RNIP892[3]\ : XNOR2 - port map(A => \WADDR_REG1[3]\, B => \RADDR_REG1[3]\, Y => - I_4_3_i_0); - - rfd_tile_I_1_RNI63001 : MX2 - port map(A => \DOUT_TMP_0[11]\, B => \DIN_REG1_0[11]\, S - => N_7, Y => hwdata_c(11)); - - \rfd_tile_RADDR_REG1_RNIQS1L[0]\ : NOR3C - port map(A => I_5_1, B => I_5_0, C => I_5_5, Y => N_7_0); - - \rfd_tile_RADDR_REG1[3]\ : DFN1 - port map(D => Raddr_vect_RNIE6Q5I(3), CLK => HCLK_c, Q => - \RADDR_REG1[3]\); - - \rfd_tile_DIN_REG1_RNIQKBR[6]\ : MX2 - port map(A => \DOUT_TMP_0[6]\, B => \DIN_REG1_0[6]\, S => - N_7, Y => hwdata_c(6)); - - rfd_tile_0_I_1_RNIJ2BO : MX2 - port map(A => \DOUT_TMP[5]\, B => \DIN_REG1[5]\, S => N_7_0, - Y => hwdata_c(23)); - - \rfd_tile_RADDR_REG1_RNI2AUB[4]\ : NOR3C - port map(A => I_4_5_i_0, B => I_4_4_i_0, C => I_5_3, Y => - I_5_5); - - GND_i : GND - port map(Y => \GND\); - - \rfd_tile_RADDR_REG1_RNITO92[5]\ : XNOR2 - port map(A => \WADDR_REG1[5]\, B => \RADDR_REG1[5]\, Y => - I_4_5_i_0); - - \rfd_tile_RADDR_REG1[1]\ : DFN1 - port map(D => Raddr_vect_RNICA1PH(1), CLK => HCLK_c, Q => - \RADDR_REG1[1]\); - - \rfd_tile_RADDR_REG1_RNIA0B7[6]\ : XA1A - port map(A => \RADDR_REG1[6]\, B => \WADDR_REG1[6]\, C => - N_5, Y => I_5_3); - - rfd_tile_0_I_1_RNINIBO : MX2 - port map(A => \DOUT_TMP[9]\, B => \DIN_REG1[9]\, S => N_7_0, - Y => hwdata_c(27)); - - \rfd_tile_DIN_REG1[14]\ : DFN1 - port map(D => wdata(14), CLK => HCLK_c, Q => \DIN_REG1[14]\); - - \rfd_tile_0_DIN_REG1[10]\ : DFN1 - port map(D => wdata(28), CLK => HCLK_c, Q => \DIN_REG1[10]\); - - \rfd_tile_DIN_REG1_RNISSBR[8]\ : MX2 - port map(A => \DOUT_TMP_0[8]\, B => \DIN_REG1_0[8]\, S => - N_7, Y => hwdata_c(8)); - - \rfd_tile_RADDR_REG1[6]\ : DFN1 - port map(D => sEmpty_RNILSD08, CLK => HCLK_c, Q => - \RADDR_REG1[6]\); - - rfd_tile_0_I_1_RNIC01O : MX2 - port map(A => \DOUT_TMP[13]\, B => \DIN_REG1[13]\, S => - N_7_0, Y => hwdata_c(31)); - - rfd_tile_0_I_1_RNIA01O : MX2 - port map(A => \DOUT_TMP[11]\, B => \DIN_REG1[11]\, S => - N_7_0, Y => hwdata_c(29)); - - \rfd_tile_DIN_REG1_RNIKSAR[0]\ : MX2 - port map(A => \DOUT_TMP_0[0]\, B => \DIN_REG1_0[0]\, S => - N_7, Y => hwdata_c(0)); - - \rfd_tile_DIN_REG1_RNIOCBR[4]\ : MX2 - port map(A => \DOUT_TMP_0[4]\, B => \DIN_REG1_0[4]\, S => - N_7, Y => hwdata_c(4)); - - \rfd_tile_DIN_REG1_RNIT0CR[9]\ : MX2 - port map(A => \DOUT_TMP_0[9]\, B => \DIN_REG1_0[9]\, S => - N_7, Y => hwdata_c(9)); - - \rfd_tile_0_DIN_REG1[7]\ : DFN1 - port map(D => wdata(25), CLK => HCLK_c, Q => \DIN_REG1[7]\); - - \rfd_tile_0_DIN_REG1[13]\ : DFN1 - port map(D => wdata(31), CLK => HCLK_c, Q => \DIN_REG1[13]\); - - \rfd_tile_DIN_REG1[8]\ : DFN1 - port map(D => wdata(8), CLK => HCLK_c, Q => \DIN_REG1_0[8]\); - - rfd_tile_0_I_1_RNIEEAO : MX2 - port map(A => \DOUT_TMP[0]\, B => \DIN_REG1[0]\, S => N_7_0, - Y => hwdata_c(18)); - - \rfd_tile_WADDR_REG1[0]\ : DFN1 - port map(D => Waddr_vect_RNION355(0), CLK => HCLK_c, Q => - \WADDR_REG1[0]\); - - \rfd_tile_DIN_REG1_RNIN8BR[3]\ : MX2 - port map(A => \DOUT_TMP_0[3]\, B => \DIN_REG1_0[3]\, S => - N_7, Y => hwdata_c(3)); - - \rfd_tile_RADDR_REG1[4]\ : DFN1 - port map(D => Raddr_vect_RNIIMQ5I(4), CLK => HCLK_c, Q => - \RADDR_REG1[4]\); - - \rfd_tile_DIN_REG1[6]\ : DFN1 - port map(D => wdata(6), CLK => HCLK_c, Q => \DIN_REG1_0[6]\); - - \rfd_tile_0_DIN_REG1[8]\ : DFN1 - port map(D => wdata(26), CLK => HCLK_c, Q => \DIN_REG1[8]\); - - \rfd_tile_WADDR_REG1[2]\ : DFN1 - port map(D => Waddr_vect_RNI394D5(2), CLK => HCLK_c, Q => - \WADDR_REG1[2]\); - - \rfd_tile_DIN_REG1_RNIL0BR[1]\ : MX2 - port map(A => \DOUT_TMP_0[1]\, B => \DIN_REG1_0[1]\, S => - N_7, Y => hwdata_c(1)); - - \rfd_tile_DIN_REG1[11]\ : DFN1 - port map(D => wdata(11), CLK => HCLK_c, Q => - \DIN_REG1_0[11]\); - - rfd_tile_I_1_RNI93001 : MX2 - port map(A => \DOUT_TMP[14]\, B => \DIN_REG1[14]\, S => N_7, - Y => hwdata_c(14)); - - \rfd_tile_WADDR_REG1[3]\ : DFN1 - port map(D => Waddr_vect_RNIJTNE5(3), CLK => HCLK_c, Q => - \WADDR_REG1[3]\); - - \rfd_tile_DIN_REG1[13]\ : DFN1 - port map(D => wdata(13), CLK => HCLK_c, Q => - \DIN_REG1_0[13]\); - - rfd_tile_0_I_1_RNI901O : MX2 - port map(A => \DOUT_TMP[10]\, B => \DIN_REG1[10]\, S => - N_7_0, Y => hwdata_c(28)); - - rfd_tile_I_1 : RAM512X18 - port map(RADDR8 => generic_syncram_2p_7_32_0_GND, RADDR7 - => generic_syncram_2p_7_32_0_GND, RADDR6 => - sEmpty_RNILSD08, RADDR5 => sEmpty_RNIE7T87, RADDR4 => - Raddr_vect_RNIIMQ5I(4), RADDR3 => Raddr_vect_RNIE6Q5I(3), - RADDR2 => Raddr_vect_RNIKA2PH(2), RADDR1 => - Raddr_vect_RNICA1PH(1), RADDR0 => Raddr_vect_RNI4A0PH(0), - WADDR8 => generic_syncram_2p_7_32_0_GND, WADDR7 => - generic_syncram_2p_7_32_0_GND, WADDR6 => sFull_RNIU5GK1, - WADDR5 => sFull_RNIHL443, WADDR4 => - Waddr_vect_RNILLSP5(4), WADDR3 => Waddr_vect_RNIJTNE5(3), - WADDR2 => Waddr_vect_RNI394D5(2), WADDR1 => - Waddr_vect_RNI0O455(1), WADDR0 => Waddr_vect_RNION355(0), - WD17 => wdata(17), WD16 => wdata(16), WD15 => wdata(15), - WD14 => wdata(14), WD13 => wdata(13), WD12 => wdata(12), - WD11 => wdata(11), WD10 => wdata(10), WD9 => wdata(9), - WD8 => wdata(8), WD7 => wdata(7), WD6 => wdata(6), WD5 - => wdata(5), WD4 => wdata(4), WD3 => wdata(3), WD2 => - wdata(2), WD1 => wdata(1), WD0 => wdata(0), RW0 => - generic_syncram_2p_7_32_0_GND, RW1 => - generic_syncram_2p_7_32_0_VCC, WW0 => - generic_syncram_2p_7_32_0_GND, WW1 => - generic_syncram_2p_7_32_0_VCC, PIPE => - generic_syncram_2p_7_32_0_GND, REN => - generic_syncram_2p_7_32_0_GND, WEN => N_1_i_1_i, RCLK => - HCLK_c, WCLK => HCLK_c, RESET => - generic_syncram_2p_7_32_0_VCC, RD17 => \DOUT_TMP[17]\, - RD16 => \DOUT_TMP[16]\, RD15 => \DOUT_TMP[15]\, RD14 => - \DOUT_TMP[14]\, RD13 => \DOUT_TMP_0[13]\, RD12 => - \DOUT_TMP_0[12]\, RD11 => \DOUT_TMP_0[11]\, RD10 => - \DOUT_TMP_0[10]\, RD9 => \DOUT_TMP_0[9]\, RD8 => - \DOUT_TMP_0[8]\, RD7 => \DOUT_TMP_0[7]\, RD6 => - \DOUT_TMP_0[6]\, RD5 => \DOUT_TMP_0[5]\, RD4 => - \DOUT_TMP_0[4]\, RD3 => \DOUT_TMP_0[3]\, RD2 => - \DOUT_TMP_0[2]\, RD1 => \DOUT_TMP_0[1]\, RD0 => - \DOUT_TMP_0[0]\); - - rfd_tile_I_1_RNIB3001 : MX2 - port map(A => \DOUT_TMP[16]\, B => \DIN_REG1[16]\, S => - N_7_0, Y => hwdata_c(16)); - - \rfd_tile_DIN_REG1[16]\ : DFN1 - port map(D => wdata(16), CLK => HCLK_c, Q => \DIN_REG1[16]\); - - \rfd_tile_WADDR_REG1[1]\ : DFN1 - port map(D => Waddr_vect_RNI0O455(1), CLK => HCLK_c, Q => - \WADDR_REG1[1]\); - - rfd_tile_I_1_RNIC3001 : MX2 - port map(A => \DOUT_TMP[17]\, B => \DIN_REG1[17]\, S => - N_7_0, Y => hwdata_c(17)); - - \rfd_tile_RADDR_REG1_RNIQS1L_0[0]\ : NOR3C - port map(A => I_5_1, B => I_5_0, C => I_5_5, Y => N_7); - - \rfd_tile_DIN_REG1[17]\ : DFN1 - port map(D => wdata(17), CLK => HCLK_c, Q => \DIN_REG1[17]\); - - \rfd_tile_0_DIN_REG1[4]\ : DFN1 - port map(D => wdata(22), CLK => HCLK_c, Q => \DIN_REG1[4]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - rfd_tile_I_1_RNI73001 : MX2 - port map(A => \DOUT_TMP_0[12]\, B => \DIN_REG1_0[12]\, S - => N_7, Y => hwdata_c(12)); - - \rfd_tile_DIN_REG1[7]\ : DFN1 - port map(D => wdata(7), CLK => HCLK_c, Q => \DIN_REG1_0[7]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ1 is - - port( hwdata_c : out std_logic_vector(31 downto 0); - Raddr_vect_RNI4A0PH : in std_logic_vector(0 to 0); - Raddr_vect_RNICA1PH : in std_logic_vector(1 to 1); - Raddr_vect_RNIKA2PH : in std_logic_vector(2 to 2); - Raddr_vect_RNIE6Q5I : in std_logic_vector(3 to 3); - Raddr_vect_RNIIMQ5I : in std_logic_vector(4 to 4); - Waddr_vect_RNION355 : in std_logic_vector(0 to 0); - Waddr_vect_RNI0O455 : in std_logic_vector(1 to 1); - Waddr_vect_RNI394D5 : in std_logic_vector(2 to 2); - Waddr_vect_RNIJTNE5 : in std_logic_vector(3 to 3); - Waddr_vect_RNILLSP5 : in std_logic_vector(4 to 4); - wdata : in std_logic_vector(31 downto 0); - HCLK_c : in std_logic; - N_1_i_1 : in std_logic; - sEmpty_RNIE7T87 : in std_logic; - sEmpty_RNILSD08 : in std_logic; - sFull_RNIHL443 : in std_logic; - sFull_RNIU5GK1 : in std_logic; - syncram_2pZ1_GND : in std_logic; - syncram_2pZ1_VCC : in std_logic; - N_1_i_1_i : in std_logic - ); - -end syncram_2pZ1; - -architecture DEF_ARCH of syncram_2pZ1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component generic_syncram_2p_7_32_0 - port( wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - Waddr_vect_RNILLSP5 : in std_logic_vector(4 to 4) := (others => 'U'); - Waddr_vect_RNIJTNE5 : in std_logic_vector(3 to 3) := (others => 'U'); - Waddr_vect_RNI394D5 : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_RNI0O455 : in std_logic_vector(1 to 1) := (others => 'U'); - Waddr_vect_RNION355 : in std_logic_vector(0 to 0) := (others => 'U'); - Raddr_vect_RNIIMQ5I : in std_logic_vector(4 to 4) := (others => 'U'); - Raddr_vect_RNIE6Q5I : in std_logic_vector(3 to 3) := (others => 'U'); - Raddr_vect_RNIKA2PH : in std_logic_vector(2 to 2) := (others => 'U'); - Raddr_vect_RNICA1PH : in std_logic_vector(1 to 1) := (others => 'U'); - Raddr_vect_RNI4A0PH : in std_logic_vector(0 to 0) := (others => 'U'); - hwdata_c : out std_logic_vector(31 downto 0); - N_1_i_1_i : in std_logic := 'U'; - generic_syncram_2p_7_32_0_VCC : in std_logic := 'U'; - generic_syncram_2p_7_32_0_GND : in std_logic := 'U'; - sFull_RNIU5GK1 : in std_logic := 'U'; - sFull_RNIHL443 : in std_logic := 'U'; - sEmpty_RNILSD08 : in std_logic := 'U'; - sEmpty_RNIE7T87 : in std_logic := 'U'; - N_1_i_1 : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : generic_syncram_2p_7_32_0 - Use entity work.generic_syncram_2p_7_32_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \inf.x0\ : generic_syncram_2p_7_32_0 - port map(wdata(31) => wdata(31), wdata(30) => wdata(30), - wdata(29) => wdata(29), wdata(28) => wdata(28), wdata(27) - => wdata(27), wdata(26) => wdata(26), wdata(25) => - wdata(25), wdata(24) => wdata(24), wdata(23) => wdata(23), - wdata(22) => wdata(22), wdata(21) => wdata(21), wdata(20) - => wdata(20), wdata(19) => wdata(19), wdata(18) => - wdata(18), wdata(17) => wdata(17), wdata(16) => wdata(16), - wdata(15) => wdata(15), wdata(14) => wdata(14), wdata(13) - => wdata(13), wdata(12) => wdata(12), wdata(11) => - wdata(11), wdata(10) => wdata(10), wdata(9) => wdata(9), - wdata(8) => wdata(8), wdata(7) => wdata(7), wdata(6) => - wdata(6), wdata(5) => wdata(5), wdata(4) => wdata(4), - wdata(3) => wdata(3), wdata(2) => wdata(2), wdata(1) => - wdata(1), wdata(0) => wdata(0), Waddr_vect_RNILLSP5(4) - => Waddr_vect_RNILLSP5(4), Waddr_vect_RNIJTNE5(3) => - Waddr_vect_RNIJTNE5(3), Waddr_vect_RNI394D5(2) => - Waddr_vect_RNI394D5(2), Waddr_vect_RNI0O455(1) => - Waddr_vect_RNI0O455(1), Waddr_vect_RNION355(0) => - Waddr_vect_RNION355(0), Raddr_vect_RNIIMQ5I(4) => - Raddr_vect_RNIIMQ5I(4), Raddr_vect_RNIE6Q5I(3) => - Raddr_vect_RNIE6Q5I(3), Raddr_vect_RNIKA2PH(2) => - Raddr_vect_RNIKA2PH(2), Raddr_vect_RNICA1PH(1) => - Raddr_vect_RNICA1PH(1), Raddr_vect_RNI4A0PH(0) => - Raddr_vect_RNI4A0PH(0), hwdata_c(31) => hwdata_c(31), - hwdata_c(30) => hwdata_c(30), hwdata_c(29) => - hwdata_c(29), hwdata_c(28) => hwdata_c(28), hwdata_c(27) - => hwdata_c(27), hwdata_c(26) => hwdata_c(26), - hwdata_c(25) => hwdata_c(25), hwdata_c(24) => - hwdata_c(24), hwdata_c(23) => hwdata_c(23), hwdata_c(22) - => hwdata_c(22), hwdata_c(21) => hwdata_c(21), - hwdata_c(20) => hwdata_c(20), hwdata_c(19) => - hwdata_c(19), hwdata_c(18) => hwdata_c(18), hwdata_c(17) - => hwdata_c(17), hwdata_c(16) => hwdata_c(16), - hwdata_c(15) => hwdata_c(15), hwdata_c(14) => - hwdata_c(14), hwdata_c(13) => hwdata_c(13), hwdata_c(12) - => hwdata_c(12), hwdata_c(11) => hwdata_c(11), - hwdata_c(10) => hwdata_c(10), hwdata_c(9) => hwdata_c(9), - hwdata_c(8) => hwdata_c(8), hwdata_c(7) => hwdata_c(7), - hwdata_c(6) => hwdata_c(6), hwdata_c(5) => hwdata_c(5), - hwdata_c(4) => hwdata_c(4), hwdata_c(3) => hwdata_c(3), - hwdata_c(2) => hwdata_c(2), hwdata_c(1) => hwdata_c(1), - hwdata_c(0) => hwdata_c(0), N_1_i_1_i => N_1_i_1_i, - generic_syncram_2p_7_32_0_VCC => syncram_2pZ1_VCC, - generic_syncram_2p_7_32_0_GND => syncram_2pZ1_GND, - sFull_RNIU5GK1 => sFull_RNIU5GK1, sFull_RNIHL443 => - sFull_RNIHL443, sEmpty_RNILSD08 => sEmpty_RNILSD08, - sEmpty_RNIE7T87 => sEmpty_RNIE7T87, N_1_i_1 => N_1_i_1, - HCLK_c => HCLK_c); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ2 is - - port( ready_i_0 : out std_logic_vector(2 to 2); - data_mem_wen_i_0 : out std_logic_vector(2 to 2); - data_ren : in std_logic_vector(2 to 2); - Waddr_vect_RNI0O455 : out std_logic_vector(1 to 1); - Waddr_vect_RNILLSP5 : out std_logic_vector(4 to 4); - Waddr_vect_RNIJTNE5 : out std_logic_vector(3 to 3); - Waddr_vect_RNI394D5 : out std_logic_vector(2 to 2); - data_mem_ren_i_0_0 : in std_logic; - data_addr_r_0_iv_i_2 : in std_logic_vector(5 to 5); - data_addr_w_iv_i_4 : in std_logic_vector(4 downto 0); - Waddr_vect_RNION355 : out std_logic_vector(0 to 0); - data_wen : in std_logic_vector(2 to 2); - data_addr_r_iv_i_a2_0 : in std_logic_vector(4 to 4); - data_addr_r_iv_i_a2_2 : out std_logic_vector(4 to 4); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_67 : out std_logic; - N_166 : in std_logic; - N_75 : out std_logic; - N_59 : out std_logic; - N_51 : out std_logic; - N_43 : out std_logic; - N_152 : in std_logic; - N_128 : in std_logic; - N_136 : in std_logic; - N_144 : in std_logic; - sEmpty_RNIE7T87 : out std_logic; - N_160 : in std_logic; - N_77 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ2; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ2 is - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \data_mem_addr_w_2[1]\, \data_mem_addr_w_2[0]\, - N_4, \data_mem_addr_w_2[3]\, \DWACT_FINC_E[0]\, N_12_0, - \data_mem_addr_r_2[1]\, \data_mem_addr_r_2[0]\, N_4_0, - \data_mem_addr_r_2[3]\, \DWACT_FINC_E_0[0]\, - \data_mem_ren_i_0[2]\, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \sEmpty_RNO_6\, - \sEmpty_RNO_7\, \un10_raddr_vect_s[1]\, \sEmpty_RNO_5\, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \un8_waddr_vect_s[3]\, sFull_RNO_8_0, un5_sfull_s_4_1, - \un8_waddr_vect_s[1]\, sFull_RNO_5_2, un5_sfull_s_4_0, - \un8_waddr_vect_s[0]\, ADD_7x7_fast_I23_Y_0_o2_0, N165_1, - N_89_i, N_109, ADD_5x5_fast_I11_Y_i_a2_1, - ADD_5x5_fast_I11_Y_i_a2_0, N_17, \data_mem_addr_r_2[2]\, - \data_mem_addr_w_2[2]\, SUM2_0_0, ADD_5x5_fast_I11_Y_0, - N80, un1_waddr_vect_slto3_0, un2_raddr_vect_slto3_0, - N_159, N_143, N_135, N_127, N_151, \un117_ready1[4]\, - N_87, CO1_tz, N_12_1, N_18, I11_un1_Y, N81, N77, N98, - un5_sfull_s_4, Waddr_vect_n4, \data_mem_addr_w_2[4]\, - Waddr_vect_14_0, N_58_i_0, Waddr_vect_c2, Waddr_vect_n3, - sFull_RNO_9, \sFull\, ADD_7x7_fast_I19_Y_i_a2_0_206, - N_9_i, N_105_1, Waddr_vect_n2, Waddr_vect_c1_i_0, - \sEmpty\, un1_sempty_s, sEmpty_RNO_10, un2_raddr_vect_s, - I_5_16, \un10_raddr_vect_s[2]\, I_9_16, - \un10_raddr_vect_s[3]\, I_13_16, \un10_raddr_vect_s[4]\, - I_20_8, I_5_15, I_13_15, \data_mem_addr_r_2[4]\, - \data_mem_wen_i_0[2]\, Waddr_vect_e1, Waddr_vect_n1_i, - Waddr_vect_e4, I_20_7, I_9_15, Waddr_vect_e3, - Waddr_vect_e0, N_85_i, N_24, N_75_0, \un132_ready1[4]\, - I8_un1_Y, \un132_ready0_1[4]\, \un117_ready0[4]\, N_6, - \un132_ready0[4]\, un119_readylto4, un134_ready, - un126_ready, N_198, N107, N161, N_197, \un132_ready1[5]\, - N_16_i_i_0, N_196, N_13, un2_raddr_vect_slto1, - Waddr_vect_e2, N_9, N_13_0, N_12_2, N_11, N_8, N_10, - N_9_0, N_7, N_4_1, N_5, N_6_0, N_9_1, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - data_mem_wen_i_0(2) <= \data_mem_wen_i_0[2]\; - - un117_ready_1_1_0_CO1_tz : AO18 - port map(A => N_105_1, B => \data_mem_addr_w_2[2]\, C => - \data_mem_addr_r_2[2]\, Y => CO1_tz); - - sFull : DFN1C0 - port map(D => sFull_RNO_9, CLK => HCLK_c, CLR => HRESETn_c, - Q => \sFull\); - - un117_ready_1_1_0_SUM2_0 : AX1C - port map(A => N_87, B => CO1_tz, C => SUM2_0_0, Y => - \un117_ready1[4]\); - - \ready_gen.un126_ready_0_I_11\ : OA1 - port map(A => N_13_0, B => N_12_2, C => N_11, Y => - un126_ready); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => N_58_i_0, B => \data_mem_wen_i_0[2]\, C => - \data_mem_addr_w_2[0]\, Y => Waddr_vect_e0); - - sFull_RNO_8 : AX1E - port map(A => N_58_i_0, B => I_20_7, C => - \data_mem_addr_r_2[4]\, Y => sFull_RNO_8_0); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0_0 : AO1C - port map(A => \data_mem_addr_r_2[2]\, B => - \data_mem_addr_w_2[2]\, C => N_109, Y => - ADD_5x5_fast_I11_Y_i_a2_0); - - sFull_RNO_6 : OR2A - port map(A => N_58_i_0, B => \data_mem_addr_w_2[0]\, Y => - \un8_waddr_vect_s[0]\); - - \Raddr_vect_RNIVJ63[1]\ : OR2B - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_r_2[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[0]\); - - \Raddr_vect_RNI53FB1[0]\ : MX2 - port map(A => \un117_ready1[4]\, B => \un117_ready0[4]\, S - => \data_mem_addr_r_2[0]\, Y => un119_readylto4); - - un132_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO1 - port map(A => N80, B => N_109, C => N_89_i, Y => - ADD_5x5_fast_I11_Y_0); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AO1A - port map(A => N165_1, B => N_89_i, C => N_109, Y => - ADD_7x7_fast_I23_Y_0_o2_0); - - \Waddr_vect_RNO[3]\ : MX2B - port map(A => \data_mem_addr_w_2[3]\, B => Waddr_vect_n3, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e3); - - \Waddr_vect_RNI394D5[2]\ : NOR3C - port map(A => data_addr_w_iv_i_4(2), B => N_143, C => N_144, - Y => Waddr_vect_RNI394D5(2)); - - \Raddr_vect_RNI8ULN5[0]\ : AOI1 - port map(A => N_197, B => N_196, C => N_198, Y => - un134_ready); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_r_2[0]\, Y => N_12_0); - - \Waddr_vect_RNION355[0]\ : NOR3C - port map(A => data_addr_w_iv_i_4(0), B => N_159, C => N_160, - Y => Waddr_vect_RNION355(0)); - - \Waddr_vect_RNIPN791[0]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[0]\, Y => N_159); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, Y => I_5_15); - - un132_ready_1_16_ADD_5x5_fast_I8_un1_Y : NOR2B - port map(A => N81, B => N77, Y => I8_un1_Y); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - un132_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75_0, Y => N_16_i_i_0); - - \Raddr_vect_RNI5KRC[4]\ : NOR2B - port map(A => I_9_16, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \Waddr_vect_RNIT7891[4]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[4]\, Y => N_127); - - un117_ready_0_0_0_ADD_5x5_fast_I18_Y_0 : XNOR2 - port map(A => N_6, B => N_89_i, Y => \un117_ready0[4]\); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_r_2[2]\, Y - => N_9); - - un117_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3 : NOR2 - port map(A => N_9_i, B => \data_mem_addr_r_2[2]\, Y => N_17); - - \Raddr_vect_RNI7073[2]\ : XNOR2 - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => N_85_i); - - \ready_gen.un126_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_2[4]\, B => - \data_mem_addr_w_2[4]\, Y => N_7); - - \Waddr_vect_RNO[4]\ : MX2B - port map(A => \data_mem_addr_w_2[4]\, B => Waddr_vect_n4, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e4); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[1]\); - - sFull_RNO_7 : OR2B - port map(A => I_13_15, B => N_58_i_0, Y => - \un8_waddr_vect_s[3]\); - - \Raddr_vect_RNIB3352[1]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[1]\, Y => N_67); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_2[3]\, Y => - I_13_15); - - GND_i : GND - port map(Y => \GND\); - - sEmpty_RNO_7 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_2[4]\, Y => \sEmpty_RNO_7\); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i : OR2B - port map(A => N_13, B => N_12_1, Y => N_6); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Raddr_vect_RNI5O63[1]\ : NOR2A - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, Y => N_105_1); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, C => \data_mem_addr_w_2[2]\, Y - => N_9_1); - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, C => N_58_i_0, Y => - Waddr_vect_n1_i); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_1 : OR2 - port map(A => ADD_5x5_fast_I11_Y_i_a2_0, B => N_17, Y => - ADD_5x5_fast_I11_Y_i_a2_1); - - \Raddr_vect[2]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[2]\); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2 : OR2 - port map(A => ADD_5x5_fast_I11_Y_i_a2_1, B => N_18, Y => - N_12_1); - - un132_ready_1_16_ADD_5x5_fast_I1_G0N : AO1C - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, C => N_87, Y => N80); - - \Waddr_vect_RNIS3891[3]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[3]\, Y => N_135); - - \Raddr_vect_RNIGJ408[0]\ : MX2 - port map(A => un119_readylto4, B => un134_ready, S => - un126_ready, Y => ready_i_0(2)); - - \Raddr_vect_RNI9873_0[3]\ : OR2A - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, Y => N_109); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_2[4]\, B => Waddr_vect_14_0, - C => N_58_i_0, Y => Waddr_vect_n4); - - un132_ready_1_16_ADD_5x5_fast_I0_CO1 : NOR2 - port map(A => N_105_1, B => N_85_i, Y => N77); - - VCC_i : VCC - port map(Y => \VCC\); - - sEmpty_RNIT8VB4 : NOR3C - port map(A => N_77, B => data_addr_r_iv_i_a2_0(4), C => - \data_mem_ren_i_0[2]\, Y => data_addr_r_iv_i_a2_2(4)); - - sEmpty_RNO : AO1A - port map(A => data_ren(2), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_10); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[3]\); - - \Raddr_vect_RNIAV252[0]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[0]\, Y => N_75); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, Y => N_12); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_2[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(2), Y => - un7_sempty_s_0); - - \Waddr_vect_RNIUG18[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => - Waddr_vect_c1_i_0, C => \data_mem_addr_w_2[4]\, Y => - N_58_i_0); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_2[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - \Raddr_vect_RNI5G18[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_2[4]\, Y => - un2_raddr_vect_s); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[4]\); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(2), - Y => sFull_RNO_9); - - \Raddr_vect_RNIA03G[4]\ : NOR2B - port map(A => I_20_8, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \ready_gen.un126_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, C => N_7, Y => N_12_2); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_2[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(2), Y => - un5_sfull_s_4_0); - - \ready_gen.un126_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, C => N_4_1, Y => N_10); - - un132_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : AX1A - port map(A => N165_1, B => N80, C => \un132_ready0_1[4]\, Y - => \un132_ready0[4]\); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_2[2]\, B => - Waddr_vect_c1_i_0, C => N_58_i_0, Y => Waddr_vect_n2); - - \ready_gen.un126_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, C => N_6_0, Y => N_8); - - \ready_gen.un126_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_w_2[0]\, Y => N_6_0); - - un132_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75_0, Y => \un132_ready1[5]\); - - \Raddr_vect[0]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[0]\); - - sFull_RNIDVR9 : NOR2 - port map(A => \sFull\, B => data_wen(2), Y => - \data_mem_wen_i_0[2]\); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_2[3]\, B => Waddr_vect_c2, C - => N_58_i_0, Y => Waddr_vect_n3); - - \ready_gen.un126_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, C => N_5, Y => N_9_0); - - \Waddr_vect_RNI0O455[1]\ : NOR3C - port map(A => data_addr_w_iv_i_4(1), B => N_151, C => N_152, - Y => Waddr_vect_RNI0O455(1)); - - un132_ready_1_16_ADD_5x5_fast_I1_P0N : OR3A - port map(A => \data_mem_addr_r_2[2]\, B => - \data_mem_addr_w_2[2]\, C => N_87, Y => N81); - - sEmpty_RNIBNF32 : OR2 - port map(A => \sEmpty\, B => data_ren(2), Y => - \data_mem_ren_i_0[2]\); - - \Raddr_vect_RNI4OK9[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_2[0]\, - Y => \un10_raddr_vect_s[0]\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_2[2]\, Y => - I_9_16); - - \sEmpty_RNIE7T87\ : NOR3B - port map(A => \data_mem_ren_i_0[2]\, B => - data_addr_r_0_iv_i_2(5), C => data_mem_ren_i_0_0, Y => - sEmpty_RNIE7T87); - - \Raddr_vect_RNIBG73[4]\ : XNOR2 - port map(A => \data_mem_addr_w_2[4]\, B => - \data_mem_addr_r_2[4]\, Y => N_89_i); - - \Waddr_vect_RNIRV791[2]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[2]\, Y => N_143); - - \Waddr_vect_RNIQR791[1]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[1]\, Y => N_151); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_2[3]\, B => - \un8_waddr_vect_s[3]\, C => sFull_RNO_8_0, Y => - un5_sfull_s_4_2); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_r_2[2]\, Y - => \DWACT_FINC_E_0[0]\); - - \ready_gen.un126_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, Y => N_4_1); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_2[3]\, Y - => Waddr_vect_14_0); - - \Raddr_vect_RNIC7352[2]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[2]\, Y => N_59); - - GND_i_0 : GND - port map(Y => GND_0); - - \Raddr_vect_RNI9873[3]\ : XNOR2 - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, Y => N_87); - - \Raddr_vect_RNI3473[3]\ : NOR2 - port map(A => \data_mem_addr_r_2[3]\, B => - \data_mem_addr_r_2[2]\, Y => un2_raddr_vect_slto3_0); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR2A - port map(A => N_75_0, B => \un117_ready0[4]\, Y => N161); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_2[4]\, Y => I_20_7); - - \Raddr_vect[1]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[1]\); - - un132_ready_0_0_0_ADD_7x7_fast_I19_Y_i_a2_0_206 : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => - ADD_7x7_fast_I19_Y_i_a2_0_206); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[3]\, B => - \data_mem_addr_w_2[3]\, Y => \sEmpty_RNO_6\); - - \Raddr_vect_RNIBG73_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_2[4]\, B => - \data_mem_addr_w_2[4]\, Y => N_75_0); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_2[3]\, Y => - I_13_16); - - \ready_gen.un126_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_2[4]\, B => - \data_mem_addr_r_2[4]\, Y => N_11); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \data_mem_addr_w_2[2]\, B => Waddr_vect_n2, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e2); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_2[1]\, B => - \un10_raddr_vect_s[1]\, C => \sEmpty_RNO_5\, Y => - un7_sempty_s_1); - - \Raddr_vect_RNISJHJ1[0]\ : MX2C - port map(A => \un132_ready1[4]\, B => \un132_ready0[4]\, S - => \data_mem_addr_r_2[0]\, Y => N_196); - - sEmpty_RNO_4 : NOR2B - port map(A => \sEmpty_RNO_6\, B => \sEmpty_RNO_7\, Y => - un7_sempty_s_2); - - sFull_RNO_5 : AX1E - port map(A => N_58_i_0, B => I_9_15, C => - \data_mem_addr_r_2[2]\, Y => sFull_RNO_5_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, Y => I_5_16); - - \Waddr_vect_RNIJTNE5[3]\ : NOR3C - port map(A => data_addr_w_iv_i_4(3), B => N_135, C => N_136, - Y => Waddr_vect_RNIJTNE5(3)); - - un117_ready_1_1_0_SUM2_0_0 : XNOR2 - port map(A => N_109, B => N_89_i, Y => SUM2_0_0); - - \Waddr_vect_RNI9K63[0]\ : OR2B - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, Y => Waddr_vect_c1_i_0); - - un132_ready_1_16_ADD_5x5_fast_I15_Y_0 : AX1A - port map(A => I8_un1_Y, B => N80, C => \un132_ready0_1[4]\, - Y => \un132_ready1[4]\); - - \ready_gen.un126_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13_0); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_10, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \data_mem_addr_w_2[1]\, B => Waddr_vect_n1_i, - S => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e1); - - \Raddr_vect_RNI448B[4]\ : NOR2B - port map(A => I_5_16, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[2]\); - - un132_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1 : OA1B - port map(A => ADD_7x7_fast_I19_Y_i_a2_0_206, B => N_87, C - => N_9_i, Y => N165_1); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, C => \data_mem_addr_w_2[2]\, Y - => \DWACT_FINC_E[0]\); - - un117_ready_0_0_0_ADD_5x5_fast_I9_Y_i_o2 : AO18 - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_w_2[0]\, Y - => N_9_i); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : AO1A - port map(A => N165_1, B => N80, C => N_89_i, Y => N_24); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_2[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_2, Y => - un5_sfull_s_4_1); - - \Waddr_vect_RNILLSP5[4]\ : NOR3C - port map(A => data_addr_w_iv_i_4(4), B => N_127, C => N_128, - Y => Waddr_vect_RNILLSP5(4)); - - un132_ready_1_16_ADD_5x5_fast_I10_Y : OR2B - port map(A => I11_un1_Y, B => N_75_0, Y => N107); - - un132_ready_0_0_0_ADD_7x7_fast_I32_Y_0_1 : XOR2 - port map(A => N_109, B => N_89_i, Y => \un132_ready0_1[4]\); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[3]\); - - sFull_RNO_4 : OR2B - port map(A => I_5_15, B => N_58_i_0, Y => - \un8_waddr_vect_s[1]\); - - \Raddr_vect_RNI78FE[4]\ : NOR2B - port map(A => I_13_16, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_2[2]\, Y => \sEmpty_RNO_5\); - - \Waddr_vect_RNID473[3]\ : NOR2 - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_w_2[2]\, Y => un1_waddr_vect_slto3_0); - - un117_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3_0 : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => N_9_i, Y => N_18); - - un132_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - \ready_gen.un126_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => N_5); - - \Raddr_vect_RNI245L1[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_2[0]\, - Y => N_198); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_2[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - \Waddr_vect_RNIF4Q4[2]\ : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => - Waddr_vect_c1_i_0, Y => Waddr_vect_c2); - - \Raddr_vect_RNIA6VE2[0]\ : MX2C - port map(A => \un132_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_2[0]\, Y => N_197); - - \Raddr_vect[4]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[4]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_2[2]\, Y => - I_9_15); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0 : OR2A - port map(A => \data_mem_addr_r_2[3]\, B => - \data_mem_addr_w_2[3]\, Y => N_13); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(2), Y => un1_sempty_s); - - \Raddr_vect_RNIDB352[3]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[3]\, Y => N_51); - - \Raddr_vect_RNIEF352[4]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[4]\, Y => N_43); - - un132_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_109, B => N_89_i, Y => N98); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_2[4]\, Y => - I_20_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ5 is - - port( time_mem_wen_i_0_0 : in std_logic; - Waddr_vect_RNINV58 : out std_logic_vector(2 to 2); - Waddr_vect_RNILN58 : out std_logic_vector(0 to 0); - Raddr_vect_RNI8J9L : out std_logic_vector(2 to 2); - time_mem_ren_i_0 : out std_logic_vector(1 to 1); - time_wen : in std_logic_vector(1 to 1); - time_ren : in std_logic_vector(1 to 1); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_146 : out std_logic; - N_162 : out std_logic; - N_113 : out std_logic; - N_122 : out std_logic; - sFull_RNIPQBB_0 : out std_logic; - N_62 : out std_logic; - N_70 : out std_logic; - sEmpty_RNI5EFO_0 : out std_logic; - N_33 : out std_logic; - N_29 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ5; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ5 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \time_mem_addr_r_1[5]\, \Raddr_vect[2]_net_1\, - \Raddr_vect[3]_net_1\, \DWACT_FINC_E[0]\, - \time_mem_addr_w_1[5]\, \Waddr_vect[2]_net_1\, - \Waddr_vect[3]_net_1\, \DWACT_FINC_E_0[0]\, N_7, - \time_mem_addr_r_1[1]\, \time_mem_addr_r_1[0]\, N_7_0, - \time_mem_addr_w_1[1]\, \time_mem_addr_w_1[0]\, - un5_sfull_s_2, \un8_waddr_vect_s[3]\, un5_sfull_s_1, - \un8_waddr_vect_s[1]\, sFull_RNO_5_0, un5_sfull_s_0, - \un8_waddr_vect_s[0]\, un7_sempty_s_3, sEmpty_RNO_3_1, - sEmpty_RNO_4_1, un7_sempty_s_0, un7_sempty_s_2, - \un10_raddr_vect_s[3]\, \un10_raddr_vect_s[0]\, - un1_waddr_vect_slt3, un5_sfull_s, un2_raddr_vect_slt3, - Raddr_vect_n3, Raddr_vect_7_0, Waddr_vect_n3, - Waddr_vect_15_0, Raddr_vect_n2, un2_raddr_vect_s, - Raddr_vect_n2_tz, Waddr_vect_n2, un1_waddr_vect_s, - Waddr_vect_n2_tz, \time_mem_ren_i_0[1]\, - \time_mem_addr_r_1[3]\, N_167, I_9_10, Raddr_vect_n1_i, - Raddr_vect_e2, Raddr_vect_e1, Raddr_vect_e0, I_13_10, - I_9_9, I_5_10, Waddr_vect_n1_i, Waddr_vect_e2, - \time_mem_wen_i_0[1]\, Waddr_vect_e1, Waddr_vect_e0, - I_13_9, I_5_9, \sFull_RNO_2\, \sFull\, \sEmpty_RNO_2\, - un2_sempty_s, \sEmpty\, \time_mem_addr_w_1[3]\, N_4, - N_4_0, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - time_mem_ren_i_0(1) <= \time_mem_ren_i_0[1]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_1[1]\, B => - \time_mem_addr_w_1[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4); - - sFull_RNIPQBB_1 : NOR2 - port map(A => \time_mem_addr_w_1[5]\, B => N_167, Y => - N_122); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_1[1]\, B => - \time_mem_addr_r_1[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - sEmpty_RNI5EFO_1 : NOR2 - port map(A => \time_mem_ren_i_0[1]\, B => - \time_mem_addr_r_1[5]\, Y => N_33); - - un36_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_1[5]\); - - un36_mem_addr_wen_I_16 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => \DWACT_FINC_E_0[0]\); - - \Waddr_vect_RNI0PG9[1]\ : OR3 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_1[1]\, B => - \time_mem_addr_w_1[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_2\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_1[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_wen_i_0[1]\, Q => - \Waddr_vect[3]_net_1\); - - sEmpty_RNI5EFO : OR2A - port map(A => \DWACT_FINC_E[0]\, B => \time_mem_ren_i_0[1]\, - Y => N_29); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_10); - - \Raddr_vect_RNI7F9L[1]\ : OR2 - port map(A => \time_mem_ren_i_0[1]\, B => - \time_mem_addr_r_1[1]\, Y => N_62); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_2\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[1]\, - C => \time_mem_addr_w_1[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Waddr_vect[2]_net_1\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_1[1]\, - S => \time_mem_wen_i_0[1]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, Y => I_5_9); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - sFull_RNIM805_0 : OR2A - port map(A => time_mem_wen_i_0_0, B => - \time_mem_wen_i_0[1]\, Y => N_167); - - sFull_RNIPQBB : OR2A - port map(A => \DWACT_FINC_E_0[0]\, B => N_167, Y => N_113); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_ren_i_0[1]\, Q => - \Raddr_vect[3]_net_1\); - - \sFull_RNIPQBB_0\ : OR2 - port map(A => \time_mem_addr_w_1[3]\, B => N_167, Y => - sFull_RNIPQBB_0); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(1), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4, B => \Waddr_vect[3]_net_1\, Y => I_13_9); - - un31_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_1[3]\); - - sFull_RNO : AO1 - port map(A => time_ren(1), B => \sFull\, C => un5_sfull_s, - Y => \sFull_RNO_2\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[1]\, - C => \time_mem_addr_r_1[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_1[1]\, - S => \time_mem_ren_i_0[1]\, Y => Raddr_vect_e1); - - sFull_RNIM805 : OR2B - port map(A => \time_mem_wen_i_0[1]\, B => - time_mem_wen_i_0_0, Y => N_162); - - sFull_RNO_4 : OR2B - port map(A => I_5_9, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_1[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_10, C => - \Waddr_vect[2]_net_1\, Y => sEmpty_RNO_3_1); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Raddr_vect[2]_net_1\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_1[0]\); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_9, C => - \Raddr_vect[2]_net_1\, Y => sFull_RNO_5_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[1]\, Y => Waddr_vect_e2); - - un31_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_1[5]\); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_10, C => - \time_mem_addr_w_1[1]\, Y => sEmpty_RNO_4_1); - - sFull_RNO_3 : XA1 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, C => time_ren(1), Y => - un5_sfull_s_2); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_1, B => sEmpty_RNO_4_1, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un36_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_1[3]\); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - sEmpty_RNO_7 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_1[0]\, - Y => \un10_raddr_vect_s[0]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[1]\, Y => Raddr_vect_e2); - - \Raddr_vect_RNIEJMC[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_1[0]\); - - \sEmpty_RNI5EFO_0\ : OR2 - port map(A => \time_mem_ren_i_0[1]\, B => - \time_mem_addr_r_1[3]\, Y => sEmpty_RNI5EFO_0); - - \Raddr_vect_RNIHOG9[1]\ : OR3 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - \Waddr_vect_RNINV58[2]\ : OR2A - port map(A => \Waddr_vect[2]_net_1\, B => N_167, Y => - Waddr_vect_RNINV58(2)); - - \Raddr_vect_RNI8J9L[2]\ : OR2A - port map(A => \Raddr_vect[2]_net_1\, B => - \time_mem_ren_i_0[1]\, Y => Raddr_vect_RNI8J9L(2)); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_1[1]\, B => - \time_mem_addr_r_1[0]\, Y => N_7); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => I_9_9); - - sFull_RNIC4G2 : OR2 - port map(A => time_wen(1), B => \sFull\, Y => - \time_mem_wen_i_0[1]\); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_0, B => \Raddr_vect[3]_net_1\, Y => - I_13_10); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_0); - - sEmpty_RNO_1 : XA1B - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, C => time_ren(1), Y => - un7_sempty_s_2); - - sFull_RNO_1 : XA1 - port map(A => \un8_waddr_vect_s[1]\, B => - \time_mem_addr_r_1[1]\, C => sFull_RNO_5_0, Y => - un5_sfull_s_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, Y => I_5_10); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - sFull_RNO_7 : OR2B - port map(A => I_13_9, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - \Raddr_vect_RNI6B9L[0]\ : OR2 - port map(A => \time_mem_ren_i_0[1]\, B => - \time_mem_addr_r_1[0]\, Y => N_70); - - \Waddr_vect_RNIMR58[1]\ : OR2 - port map(A => \time_mem_addr_w_1[1]\, B => N_167, Y => - N_146); - - \Waddr_vect_RNILN58[0]\ : OR2 - port map(A => \time_mem_addr_w_1[0]\, B => N_167, Y => - Waddr_vect_RNILN58(0)); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - un31_mem_addr_ren_I_16 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_1, B => un5_sfull_s_0, C => - un5_sfull_s_2, Y => un5_sfull_s); - - sEmpty_RNO_6 : OR2B - port map(A => I_13_10, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - sFull : DFN1C0 - port map(D => \sFull_RNO_2\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Waddr_vect_RNI2KMC[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_1[1]\); - - sFull_RNO_2 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_1[0]\, C => time_wen(1), Y => - un5_sfull_s_0); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_1[0]\, C => time_wen(1), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - sEmpty_RNICS3I : OR2 - port map(A => time_ren(1), B => \sEmpty\, Y => - \time_mem_ren_i_0[1]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ3 is - - port( ready_i_0 : out std_logic_vector(3 to 3); - data_mem_wen_i_0_0 : in std_logic; - data_ren : in std_logic_vector(3 to 3); - data_wen : in std_logic_vector(3 to 3); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_128 : out std_logic; - N_152 : out std_logic; - N_136 : out std_logic; - N_68 : out std_logic; - N_144 : out std_logic; - N_166 : in std_logic; - N_160 : out std_logic; - N_76 : out std_logic; - N_60 : out std_logic; - N_52 : out std_logic; - N_86 : in std_logic; - N_44 : out std_logic; - N_1_i_1 : out std_logic; - N_1_i_1_i : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ3; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ3 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \data_mem_addr_w_3[1]\, \data_mem_addr_w_3[0]\, - N_4, \data_mem_addr_w_3[3]\, \DWACT_FINC_E[0]\, N_12_0, - \data_mem_addr_r_3[1]\, \data_mem_addr_r_3[0]\, N_4_0, - \data_mem_addr_r_3[3]\, \DWACT_FINC_E_0[0]\, - un7_sempty_s_4, un7_sempty_s_1, un7_sempty_s_0, - un7_sempty_s_2, \un10_raddr_vect_s[3]\, sEmpty_RNO_6_0, - \un10_raddr_vect_s[1]\, sEmpty_RNO_5_0, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \un8_waddr_vect_s[3]\, \sFull_RNO_8\, un5_sfull_s_4_1, - \un8_waddr_vect_s[1]\, sFull_RNO_5_1, un5_sfull_s_4_0, - \un8_waddr_vect_s[0]\, ADD_7x7_fast_I23_Y_0_o2_0, N165_1, - \un174_ready0_1[4]\, N_11, ADD_5x5_fast_I11_Y_0, N80, - ADD_5x5_fast_I11_Y_i_a2_0, \data_mem_addr_w_3[2]\, - \data_mem_addr_r_3[2]\, \un189_ready0_1[4]\, - ADD_7x7_fast_I19_Y_i_o4_1_0, N_87, un1_waddr_vect_slto3_0, - un2_raddr_vect_slto3_0, I11_un1_Y, N81, N77, N98, N_12_1, - N_17, N_18, \un174_ready1[4]\, CO1_tz, un5_sfull_s_4, N_9, - Waddr_vect_n4, \data_mem_addr_w_3[4]\, Waddr_vect_14_0, - un1_waddr_vect_s, Waddr_vect_c2, Waddr_vect_n2, - Waddr_vect_c1, Waddr_vect_n3, N_105, \sFull_RNO_6\, - \sFull\, un1_sempty_s, \sEmpty\, sEmpty_RNO_8, I_5_11, - I_13_11, un2_raddr_vect_s, un2_raddr_vect_slto1, - \data_mem_addr_r_3[4]\, \un10_raddr_vect_s[2]\, - \un10_raddr_vect_s[4]\, \N_1_i_1\, \data_mem_wen_i_0[3]\, - N_75, N_24, N165, Waddr_vect_e2, Waddr_vect_e3, - Waddr_vect_e4, N111, N107, \un189_ready1_i[5]\, N_13, - N161, N_16_i, un191_ready, N_197_i, N_196_i, N_198, - \un189_ready1[4]\, \un189_ready0[4]\, un176_readylto4_i_0, - \un174_ready0[4]\, un183_ready, Waddr_vect_e0, - Waddr_vect_e1, Waddr_vect_n1_i, I_20_3, I_9_11, I_20_4, - I_13_12, I_9_12, I_5_12, sREN, N_9_0, N_13_0, N_12_2, - N_11_0, N_8, N_10, N_9_1, N_7, N_4_1, N_5, N_6, N_9_2, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - N_1_i_1 <= \N_1_i_1\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, C => \data_mem_addr_w_3[2]\, Y - => N_9_2); - - un189_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR3A - port map(A => N_75, B => N_24, C => - ADD_7x7_fast_I23_Y_0_o2_0, Y => N161); - - \ready_gen.un183_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, C => N_7, Y => N_12_2); - - un189_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4 : OR2B - port map(A => N80, B => N165_1, Y => N165); - - \ready_gen.un183_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_w_3[0]\, Y => N_6); - - \Raddr_vect_RNIDKRC[4]\ : NOR2B - port map(A => I_9_12, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \Raddr_vect_RNI3FG82[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_3[0]\, - Y => N_198); - - un189_ready_1_16_ADD_5x5_fast_I11_Y_0 : MIN3 - port map(A => \un174_ready0_1[4]\, B => N_11, C => N80, Y - => ADD_5x5_fast_I11_Y_0); - - un189_ready_1_16_ADD_5x5_fast_I1_G0N : AO1C - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, C => N_87, Y => N80); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, C => \data_mem_addr_r_3[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, Y => N_12); - - sEmpty_RNO : AO1A - port map(A => data_ren(3), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_8); - - \Raddr_vect_RNIJBIK8[3]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[3]\, Y => N_52); - - \ready_gen.un183_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, Y => N_4_1); - - \Raddr_vect[1]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[3]\); - - un189_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : NOR2A - port map(A => N165, B => \un174_ready0_1[4]\, Y => N_24); - - \ready_gen.un183_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, Y => N_5); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_3[2]\, Y => - I_9_12); - - \Raddr_vect_RNIAG18[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_3[4]\, Y => - un2_raddr_vect_s); - - \Raddr_vect_RNISKHJ1[0]\ : MX2C - port map(A => \un189_ready1[4]\, B => \un189_ready0[4]\, S - => \data_mem_addr_r_3[0]\, Y => N_196_i); - - \Waddr_vect_RNO[4]\ : MX2A - port map(A => Waddr_vect_n4, B => \data_mem_addr_w_3[4]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e4); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_8, CLK => HCLK_c, PRE => HRESETn_c, - Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[3]\, - C => \data_mem_addr_w_3[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[2]\); - - \ready_gen.un183_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, C => N_5, Y => N_9_1); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \data_mem_addr_w_3[1]\, - S => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - un174_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0_0 : OA1A - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, C => N_11, Y => - ADD_5x5_fast_I11_Y_i_a2_0); - - \Raddr_vect_RNIK03G[4]\ : NOR2B - port map(A => I_20_4, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_3[2]\, B => Waddr_vect_c1, C - => un1_waddr_vect_s, Y => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, Y => I_5_11); - - \Raddr_vect_RNIGVHK8[0]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[0]\, Y => N_76); - - un174_ready_1_1_0_CO1_tz : AO18 - port map(A => N_105, B => \data_mem_addr_w_3[2]\, C => - \data_mem_addr_r_3[2]\, Y => CO1_tz); - - \Waddr_vect_RNIRR791[1]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[1]\, Y => N_152); - - \ready_gen.un183_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, C => N_4_1, Y => N_10); - - un189_ready_1_16_ADD_5x5_fast_I15_Y_0 : XOR2 - port map(A => N111, B => \un189_ready0_1[4]\, Y => - \un189_ready1[4]\); - - \Raddr_vect_RNIR7VE2[0]\ : MX2 - port map(A => \un189_ready1_i[5]\, B => N_16_i, S => - \data_mem_addr_r_3[0]\, Y => N_197_i); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[3]\); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_3[1]\, B => - \un10_raddr_vect_s[1]\, C => sEmpty_RNO_5_0, Y => - un7_sempty_s_1); - - \ready_gen.un183_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_3[4]\, B => - \data_mem_addr_w_3[4]\, Y => N_7); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_2, B => \data_mem_addr_w_3[3]\, Y => - I_13_11); - - un174_ready_1_1_0_SUM2_0_0 : XOR2 - port map(A => N_11, B => \un174_ready0_1[4]\, Y => - \un189_ready0_1[4]\); - - \Waddr_vect_RNIBK63[0]\ : OR2B - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, Y => Waddr_vect_c1); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(3), - Y => \sFull_RNO_6\); - - un189_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1B - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75, Y => N_16_i); - - un189_ready_1_16_ADD_5x5_fast_I11_un1_Y : NOR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - un189_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : XOR2 - port map(A => N165, B => \un189_ready0_1[4]\, Y => - \un189_ready0[4]\); - - \Raddr_vect_RNII7IK8[2]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[2]\, Y => N_60); - - sFull_RNO_4 : OR2B - port map(A => I_5_11, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_3[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_3[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(3), Y => - un7_sempty_s_0); - - \Raddr_vect[2]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[2]\); - - \Raddr_vect_RNIQB1B6[0]\ : AO1 - port map(A => N_197_i, B => N_196_i, C => N_198, Y => - un191_ready); - - un189_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1 : OR2B - port map(A => ADD_7x7_fast_I19_Y_i_o4_1_0, B => N_9, Y => - N165_1); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[0]\); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_3, C => - \data_mem_addr_r_3[4]\, Y => \sFull_RNO_8\); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_3[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - un174_ready_0_0_0_ADD_5x5_fast_I11_Y_i_o2 : OR2A - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, Y => N_11); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_11, C => - \data_mem_addr_r_3[2]\, Y => sFull_RNO_5_1); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \data_mem_addr_w_3[2]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e2); - - \Raddr_vect_RNI5473[3]\ : NOR2 - port map(A => \data_mem_addr_r_3[3]\, B => - \data_mem_addr_r_3[2]\, Y => un2_raddr_vect_slto3_0); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_3[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_6_0, Y => - un7_sempty_s_2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_3[3]\, Y - => Waddr_vect_14_0); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_3[3]\, B => - \un8_waddr_vect_s[3]\, C => \sFull_RNO_8\, Y => - un5_sfull_s_4_2); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - sEmpty_RNICNF32 : OR2 - port map(A => \sEmpty\, B => data_ren(3), Y => sREN); - - \ready_gen.un183_ready_0_I_11\ : OA1 - port map(A => N_13_0, B => N_12_2, C => N_11_0, Y => - un183_ready); - - \Raddr_vect_RNIAOK9[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_3[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Raddr_vect_RNIB48B[4]\ : NOR2B - port map(A => I_5_12, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNIDG73[4]\ : NOR2A - port map(A => \data_mem_addr_r_3[4]\, B => - \data_mem_addr_w_3[4]\, Y => N_75); - - \Raddr_vect_RNIF2GJ8[0]\ : MX2 - port map(A => un176_readylto4_i_0, B => un191_ready, S => - un183_ready, Y => ready_i_0(3)); - - un174_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3 : OR2A - port map(A => N_9, B => \data_mem_addr_r_3[2]\, Y => N_17); - - \Raddr_vect[0]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[0]\); - - un189_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_11, B => \un174_ready0_1[4]\, Y => N98); - - un174_ready_0_0_0_ADD_5x5_fast_I18_Y_0_1 : XNOR2 - port map(A => \data_mem_addr_w_3[4]\, B => - \data_mem_addr_r_3[4]\, Y => \un174_ready0_1[4]\); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_r_3[0]\, Y => N_12_0); - - un189_ready_1_16_ADD_5x5_fast_I8_Y : AO1B - port map(A => N81, B => N77, C => N80, Y => N111); - - un189_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1B - port map(A => \data_mem_addr_r_3[2]\, B => - \data_mem_addr_w_3[2]\, C => N_105, Y => N77); - - \Waddr_vect_RNI3H18[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => Waddr_vect_c1, C - => \data_mem_addr_w_3[4]\, Y => un1_waddr_vect_s); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_3[2]\, Y => - I_9_11); - - sFull_RNI4FGH1_0 : INV - port map(A => \N_1_i_1\, Y => N_1_i_1_i); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9_0, B => \data_mem_addr_r_3[3]\, Y => - I_13_12); - - un174_ready_0_0_0_ADD_5x5_fast_I18_Y_0 : AX1C - port map(A => N_12_1, B => N_13, C => \un174_ready0_1[4]\, - Y => \un174_ready0[4]\); - - \Raddr_vect_RNI04FB1[0]\ : MX2C - port map(A => \un174_ready1[4]\, B => \un174_ready0[4]\, S - => \data_mem_addr_r_3[0]\, Y => un176_readylto4_i_0); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, C => \data_mem_addr_r_3[2]\, Y - => N_9_0); - - un189_ready_1_16_ADD_5x5_fast_I10_Y : AO1B - port map(A => N111, B => N98, C => N_75, Y => N107); - - \ready_gen.un183_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_1, Y => N_13_0); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(3), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_3[4]\, Y => - I_20_4); - - \Raddr_vect_RNIB873[3]\ : XNOR2 - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, Y => N_87); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_3[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_1, Y => - un5_sfull_s_4_1); - - \Waddr_vect_RNIT3891[3]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[3]\, Y => N_136); - - \Waddr_vect_RNII4Q4[2]\ : NOR2A - port map(A => \data_mem_addr_w_3[2]\, B => Waddr_vect_c1, Y - => Waddr_vect_c2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, Y => I_5_12); - - un189_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AOI1 - port map(A => N165_1, B => \un174_ready0_1[4]\, C => N_11, - Y => ADD_7x7_fast_I23_Y_0_o2_0); - - un174_ready_0_0_0_ADD_5x5_fast_I9_Y_i_o2 : AO13 - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, C => \data_mem_addr_r_3[1]\, Y - => N_9); - - \Waddr_vect_RNIF473[3]\ : NOR2 - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_w_3[2]\, Y => un1_waddr_vect_slto3_0); - - un189_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1B - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75, Y => \un189_ready1_i[5]\); - - \Raddr_vect_RNI7O63[1]\ : NOR2A - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, Y => N_105); - - \Raddr_vect_RNI1K63[1]\ : OR2B - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_r_3[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_3[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[4]\); - - sFull_RNO_7 : OR2B - port map(A => I_13_11, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Waddr_vect_RNIU7891[4]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[4]\, Y => N_128); - - \Waddr_vect_RNIQN791[0]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[0]\, Y => N_160); - - un174_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3_0 : OR2B - port map(A => N_9, B => \data_mem_addr_w_3[2]\, Y => N_18); - - sFull_RNI4FGH1 : OR3A - port map(A => \data_mem_wen_i_0[3]\, B => N_166, C => - data_mem_wen_i_0_0, Y => \N_1_i_1\); - - \Waddr_vect_RNO[3]\ : MX2A - port map(A => Waddr_vect_n3, B => \data_mem_addr_w_3[3]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e3); - - un189_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXOI5 - port map(A => N_87, B => \data_mem_addr_r_3[2]\, C => - \data_mem_addr_w_3[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - un174_ready_1_1_0_SUM2_0 : AX1E - port map(A => N_87, B => CO1_tz, C => \un189_ready0_1[4]\, - Y => \un174_ready1[4]\); - - un174_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2 : OR3C - port map(A => N_17, B => ADD_5x5_fast_I11_Y_i_a2_0, C => - N_18, Y => N_12_1); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_3[4]\, Y => sEmpty_RNO_6_0); - - \Waddr_vect_RNISV791[2]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[2]\, Y => N_144); - - sFull : DFN1C0 - port map(D => \sFull_RNO_6\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Raddr_vect_RNIG8FE[4]\ : NOR2B - port map(A => I_13_12, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_3[4]\, Y => I_20_3); - - \ready_gen.un183_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_3[4]\, B => - \data_mem_addr_r_3[4]\, Y => N_11_0); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[1]\); - - \ready_gen.un183_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, C => N_6, Y => N_8); - - \Raddr_vect[4]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[4]\); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_3[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(3), Y => - un5_sfull_s_4_0); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_3[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - un174_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0 : OR2A - port map(A => \data_mem_addr_r_3[3]\, B => - \data_mem_addr_w_3[3]\, Y => N_13); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_3[2]\, Y => sEmpty_RNO_5_0); - - \Raddr_vect_RNIKFIK8[4]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[4]\, Y => N_44); - - \Raddr_vect_RNIH3IK8[1]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[1]\, Y => N_68); - - sFull_RNIFVR9 : OR2 - port map(A => \sFull\, B => data_wen(3), Y => - \data_mem_wen_i_0[3]\); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_3[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, C => \data_mem_addr_w_3[2]\, Y - => \DWACT_FINC_E[0]\); - - un189_ready_1_16_ADD_5x5_fast_I1_P0N : OR3A - port map(A => \data_mem_addr_r_3[2]\, B => - \data_mem_addr_w_3[2]\, C => N_87, Y => N81); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ0 is - - port( ready_i_0 : out std_logic_vector(0 to 0); - data_ren : in std_logic_vector(0 to 0); - data_addr_w_0_iv_i_1 : in std_logic_vector(5 to 5); - data_addr_r_1_iv_i_s_1 : in std_logic_vector(6 to 6); - data_addr_r_1_iv_i_a9_1_1 : in std_logic_vector(6 to 6); - data_mem_ren_i_0 : out std_logic_vector(0 to 0); - data_mem_wen_i_0_1 : in std_logic; - data_addr_w_1_iv_i_a2_1_1_0 : out std_logic_vector(6 to 6); - data_addr_w_iv_i_2 : in std_logic_vector(4 downto 0); - data_addr_w_iv_i_4 : out std_logic_vector(4 downto 0); - data_wen : in std_logic_vector(0 to 0); - data_addr_r_iv_i_0 : in std_logic_vector(4 downto 0); - data_addr_r_iv_i_1 : in std_logic_vector(4 downto 0); - data_addr_r_iv_i_3 : out std_logic_vector(4 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_165 : out std_logic; - N_120_i : in std_logic; - sFull_RNIHL443 : out std_logic; - sEmpty_RNILSD08 : out std_logic; - N_124 : in std_logic; - N_164 : in std_logic; - N_158 : in std_logic; - N_142 : in std_logic; - N_134 : in std_logic; - N_126 : in std_logic; - N_150 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ0; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ0 is - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \data_mem_addr_w_0[1]\, \data_mem_addr_w_0[0]\, - N_4, \data_mem_addr_w_0[3]\, \DWACT_FINC_E[0]\, N_12_0, - \data_mem_addr_r_0[1]\, \data_mem_addr_r_0[0]\, N_4_0, - \data_mem_addr_r_0[3]\, \DWACT_FINC_E_0[0]\, N_65, N_41, - N_49, N_57, N_73, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \un10_raddr_vect_s[3]\, - sEmpty_RNO_6_1, \un10_raddr_vect_s[1]\, sEmpty_RNO_5_1, - \un10_raddr_vect_s[0]\, N_149, N_125, N_133, N_141, N_157, - un5_sfull_s_4_2, \un8_waddr_vect_s[3]\, sFull_RNO_8_1, - un5_sfull_s_4_1, \un8_waddr_vect_s[1]\, sFull_RNO_5_3, - un5_sfull_s_4_0, \un8_waddr_vect_s[0]\, - \data_addr_w_0_iv_i_3[5]\, \data_mem_wen_i_0[0]\, - ADD_7x7_fast_I23_Y_0_o2_0, N165_1, N_89_i, N_109, - ADD_5x5_fast_I11_Y_0, N80, ADD_5x5_fast_I11_Y_i_a2_0, - \data_mem_addr_r_0[2]\, \data_mem_addr_w_0[2]\, SUM2_0_0, - ADD_7x7_fast_I19_Y_i_o4_1_0, N_87, un1_waddr_vect_slto3_0, - un2_raddr_vect_slto3_0, I11_un1_Y, N81, N77, N98, - \un3_ready1[4]\, CO1_tz, N_12_1, N_17, N_18, - un5_sfull_s_4, ADD_5x5_fast_I9_Y_i_o2_0, Waddr_vect_c1, - Waddr_vect_n4, \data_mem_addr_w_0[4]\, Waddr_vect_14_0, - un1_waddr_vect_s, Waddr_vect_c2, \sFull_RNO_7\, \sFull\, - Waddr_vect_n2, Waddr_vect_n3, N_84_1, - \data_mem_ren_i_0[0]\, \sEmpty\, un2_raddr_vect_s, I_5_14, - \un10_raddr_vect_s[2]\, I_9_14, I_13_14, - \un10_raddr_vect_s[4]\, I_20_6, un2_raddr_vect_slto1, - \data_mem_addr_r_0[4]\, I_9_13, ADD_5x5_fast_I8_un1_Y, - sEmpty_RNO_9, un1_sempty_s, N_75, Waddr_vect_e0, - Waddr_vect_e1, Waddr_vect_n1_i, Waddr_vect_e2, - Waddr_vect_e3, Waddr_vect_e4, \un18_ready1[4]\, - \un18_ready0_1[4]\, \un3_ready0[4]\, N_6, - \un18_ready0[4]\, un5_readylto4, un20_ready, un12_ready, - N_198, N107, N161, N_197, \un18_ready1[5]\, N_16_i_i_0, - N_196, N_24, N_13, I_20_5, I_13_13, I_5_13, N_9, N_13_0, - N_12_2, N_11, N_8, N_10, N_9_0, N_7, N_4_1, N_5, N_6_0, - N_9_1, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - data_mem_ren_i_0(0) <= \data_mem_ren_i_0[0]\; - - un3_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0_0 : AO1A - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N_109, Y => - ADD_5x5_fast_I11_Y_i_a2_0); - - sFull : DFN1C0 - port map(D => \sFull_RNO_7\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[0]\, - C => \data_mem_addr_w_0[0]\, Y => Waddr_vect_e0); - - un3_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0 : OR2A - port map(A => \data_mem_addr_r_0[3]\, B => - \data_mem_addr_w_0[3]\, Y => N_13); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_5, C => - \data_mem_addr_r_0[4]\, Y => sFull_RNO_8_1); - - \Waddr_vect_RNI11GL[2]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[2]\, Y => N_141); - - \Waddr_vect_RNIC9KQ2[2]\ : NOR3C - port map(A => N_141, B => data_addr_w_iv_i_2(2), C => N_142, - Y => data_addr_w_iv_i_4(2)); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_0[0]\, - Y => \un8_waddr_vect_s[0]\); - - \Raddr_vect_RNI73352[1]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[1]\, Y => N_65); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[0]\); - - \Waddr_vect_RNO[3]\ : MX2B - port map(A => \data_mem_addr_w_0[3]\, B => Waddr_vect_n3, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e3); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_r_0[0]\, Y => N_12_0); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : AO1D - port map(A => N80, B => N165_1, C => N_89_i, Y => N_24); - - \Waddr_vect_RNIKG18[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => Waddr_vect_c1, C - => \data_mem_addr_w_0[4]\, Y => un1_waddr_vect_s); - - \Raddr_vect_RNILJRC[4]\ : NOR2B - port map(A => I_9_14, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, Y => I_5_13); - - \ready_gen.un12_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13_0); - - \Raddr_vect_RNI5873[3]\ : XNOR2 - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, Y => N_87); - - \Raddr_vect_RNIV373[3]\ : NOR2 - port map(A => \data_mem_addr_r_0[3]\, B => - \data_mem_addr_r_0[2]\, Y => un2_raddr_vect_slto3_0); - - \sFull_RNIHL443\ : NOR3C - port map(A => data_addr_w_0_iv_i_1(5), B => N_120_i, C => - \data_addr_w_0_iv_i_3[5]\, Y => sFull_RNIHL443); - - \Raddr_vect_RNI87352[2]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[2]\, Y => N_57); - - un18_ready_1_16_ADD_5x5_fast_I10_Y : OR3A - port map(A => N_75, B => ADD_5x5_fast_I8_un1_Y, C => N80, Y - => N107); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - \ready_gen.un12_ready_0_I_11\ : OA1 - port map(A => N_13_0, B => N_12_2, C => N_11, Y => - un12_ready); - - un18_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXO5 - port map(A => N_87, B => \data_mem_addr_r_0[2]\, C => - \data_mem_addr_w_0[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AO1C - port map(A => N165_1, B => N_89_i, C => N_109, Y => - ADD_7x7_fast_I23_Y_0_o2_0); - - \Waddr_vect_RNI94Q4[2]\ : NOR2A - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_c1, Y - => Waddr_vect_c2); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, C => \data_mem_addr_r_0[2]\, Y - => N_9); - - un18_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO18 - port map(A => N80, B => N_89_i, C => N_109, Y => - ADD_5x5_fast_I11_Y_0); - - \Waddr_vect_RNO[4]\ : MX2B - port map(A => \data_mem_addr_w_0[4]\, B => Waddr_vect_n4, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e4); - - un3_ready_1_1_0_SUM2_0 : AX1C - port map(A => N_87, B => CO1_tz, C => SUM2_0_0, Y => - \un3_ready1[4]\); - - \Waddr_vect_RNI5K63[0]\ : OR2B - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, Y => Waddr_vect_c1); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[1]\); - - \ready_gen.un12_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, C => N_7, Y => N_12_2); - - sFull_RNO_7 : OR2B - port map(A => I_13_13, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_0[3]\, Y => - I_13_13); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \ready_gen.un12_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, Y => N_5); - - \Waddr_vect_RNI0TFL[1]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[1]\, Y => N_149); - - sFull_RNITGSJ : NOR2 - port map(A => \data_mem_wen_i_0[0]\, B => N_164, Y => N_165); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, C => \data_mem_addr_w_0[2]\, Y - => N_9_1); - - un18_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75, Y => \un18_ready1[5]\); - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - \Raddr_vect_RNIMV2G[4]\ : NOR2B - port map(A => I_20_6, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[2]\); - - \Raddr_vect_RNI48175[4]\ : NOR3C - port map(A => data_addr_r_iv_i_1(4), B => - data_addr_r_iv_i_0(4), C => N_41, Y => - data_addr_r_iv_i_3(4)); - - sFull_RNIKUNJ : NOR2A - port map(A => data_mem_wen_i_0_1, B => - \data_mem_wen_i_0[0]\, Y => - data_addr_w_1_iv_i_a2_1_1_0(6)); - - \Raddr_vect_RNI6V252[0]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[0]\, Y => N_73); - - sFull_RNI9VR9 : NOR2 - port map(A => \sFull\, B => data_wen(0), Y => - \data_mem_wen_i_0[0]\); - - un18_ready_1_16_ADD_5x5_fast_I1_G0N : OA1A - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N_87, Y => N80); - - \ready_gen.un12_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, C => N_4_1, Y => N_10); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_0[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i : VCC - port map(Y => \VCC\); - - un3_ready_0_0_0_ADD_5x5_fast_I11_Y_i : OR2B - port map(A => N_13, B => N_12_1, Y => N_6); - - un18_ready_1_16_ADD_5x5_fast_I2_P0N : OR2A - port map(A => N_89_i, B => N_109, Y => N98); - - sEmpty_RNO : AO1A - port map(A => data_ren(0), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_9); - - \Raddr_vect_RNIONK9[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_0[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Raddr_vect_RNI6QHR1[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_0[0]\, - Y => N_198); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[3]\); - - un3_ready_1_1_0_CO1_tz : AO18 - port map(A => N_84_1, B => \data_mem_addr_w_0[2]\, C => - \data_mem_addr_r_0[2]\, Y => CO1_tz); - - un3_ready_0_0_0_ADD_5x5_fast_I9_Y_i_o2_0 : AO1D - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, C => \data_mem_addr_r_0[1]\, Y - => ADD_5x5_fast_I9_Y_i_o2_0); - - un18_ready_1_16_ADD_5x5_fast_I8_un1_Y : NOR2B - port map(A => N81, B => N77, Y => ADD_5x5_fast_I8_un1_Y); - - un18_ready_1_16_ADD_5x5_fast_I15_Y_0 : AX1D - port map(A => ADD_5x5_fast_I8_un1_Y, B => N80, C => - \un18_ready0_1[4]\, Y => \un18_ready1[4]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, Y => N_12); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_0[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(0), Y => - un7_sempty_s_0); - - \sEmpty_RNILSD08\ : AO1C - port map(A => \data_mem_ren_i_0[0]\, B => - data_addr_r_1_iv_i_a9_1_1(6), C => - data_addr_r_1_iv_i_s_1(6), Y => sEmpty_RNILSD08); - - \Raddr_vect_RNIRF18[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_0[4]\, Y => - un2_raddr_vect_s); - - \Raddr_vect_RNIPBM76[0]\ : AOI1 - port map(A => N_197, B => N_196, C => N_198, Y => - un20_ready); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_0[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - \Waddr_vect_RNI39GL[4]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[4]\, Y => N_125); - - un3_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3_0 : AOI1B - port map(A => ADD_5x5_fast_I9_Y_i_o2_0, B => Waddr_vect_c1, - C => \data_mem_addr_w_0[2]\, Y => N_18); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[4]\); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(0), - Y => \sFull_RNO_7\); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_0[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(0), Y => - un5_sfull_s_4_0); - - un3_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2 : OR3 - port map(A => N_17, B => ADD_5x5_fast_I11_Y_i_a2_0, C => - N_18, Y => N_12_1); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_c1, C - => un1_waddr_vect_s, Y => Waddr_vect_n2); - - \Raddr_vect_RNIRJ63[1]\ : OR2B - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_r_0[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect_RNIQ5C73[4]\ : NOR3C - port map(A => N_125, B => data_addr_w_iv_i_2(4), C => N_126, - Y => data_addr_w_iv_i_4(4)); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[0]\); - - \Waddr_vect_RNIQL7S2[3]\ : NOR3C - port map(A => N_133, B => data_addr_w_iv_i_2(3), C => N_134, - Y => data_addr_w_iv_i_4(3)); - - \Raddr_vect_RNI16OM1[0]\ : MX2C - port map(A => \un18_ready1[4]\, B => \un18_ready0[4]\, S - => \data_mem_addr_r_0[0]\, Y => N_196); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_0[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Raddr_vect_RNIIBCL2[0]\ : MX2C - port map(A => \un18_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_0[0]\, Y => N_197); - - \Raddr_vect_RNIL7FE[4]\ : NOR2B - port map(A => I_13_14, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - \Raddr_vect_RNI5873_0[3]\ : NOR2A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, Y => N_109); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_0[2]\, Y => - I_9_14); - - un18_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75, Y => N_16_i_i_0); - - un18_ready_1_16_ADD_5x5_fast_I1_P0N : OR3A - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N_87, Y => N81); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_0[3]\, B => - \un8_waddr_vect_s[3]\, C => sFull_RNO_8_1, Y => - un5_sfull_s_4_2); - - sEmpty_RNI9NF32 : NOR2 - port map(A => \sEmpty\, B => data_ren(0), Y => - \data_mem_ren_i_0[0]\); - - \ready_gen.un12_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, C => N_5, Y => N_9_0); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, C => \data_mem_addr_r_0[2]\, Y - => \DWACT_FINC_E_0[0]\); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_0[3]\, Y - => Waddr_vect_14_0); - - GND_i_0 : GND - port map(Y => GND_0); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR2A - port map(A => N_75, B => \un3_ready0[4]\, Y => N161); - - \Raddr_vect_RNI34175[3]\ : NOR3C - port map(A => data_addr_r_iv_i_1(3), B => - data_addr_r_iv_i_0(3), C => N_49, Y => - data_addr_r_iv_i_3(3)); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_0[4]\, Y => I_20_5); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[1]\); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_0[4]\, Y => sEmpty_RNO_6_1); - - sFull_RNIOK841 : OA1A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => N_124, - Y => \data_addr_w_0_iv_i_3[5]\); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_0[3]\, Y => - I_13_14); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_n2, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e2); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - \Raddr_vect_RNIAF352[4]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[4]\, Y => N_41); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_0[1]\, B => - \un10_raddr_vect_s[1]\, C => sEmpty_RNO_5_1, Y => - un7_sempty_s_1); - - \Raddr_vect_RNIP9SH1[0]\ : MX2 - port map(A => \un3_ready1[4]\, B => \un3_ready0[4]\, S => - \data_mem_addr_r_0[0]\, Y => un5_readylto4); - - \Raddr_vect_RNI1O63[1]\ : NOR2A - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, Y => N_84_1); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_0[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_6_1, Y => - un7_sempty_s_2); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_13, C => - \data_mem_addr_r_0[2]\, Y => sFull_RNO_5_3); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, Y => I_5_14); - - un18_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1 : AOI1 - port map(A => ADD_5x5_fast_I9_Y_i_o2_0, B => Waddr_vect_c1, - C => ADD_7x7_fast_I19_Y_i_o4_1_0, Y => N165_1); - - \ready_gen.un12_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_0[4]\, B => - \data_mem_addr_r_0[4]\, Y => N_11); - - \Raddr_vect_RNIH6IM8[0]\ : MX2 - port map(A => un5_readylto4, B => un20_ready, S => - un12_ready, Y => ready_i_0(0)); - - \Waddr_vect_RNI25GL[3]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[3]\, Y => N_133); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_9, CLK => HCLK_c, PRE => HRESETn_c, - Q => \sEmpty\); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \data_mem_addr_w_0[1]\, B => Waddr_vect_n1_i, - S => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e1); - - un18_ready_0_0_0_ADD_7x7_fast_I32_Y_0_1 : XNOR2 - port map(A => N_109, B => N_89_i, Y => \un18_ready0_1[4]\); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[2]\); - - \Waddr_vect_RNI58KI2[0]\ : NOR3C - port map(A => N_157, B => data_addr_w_iv_i_2(0), C => N_158, - Y => data_addr_w_iv_i_4(0)); - - \Raddr_vect_RNI2C8Q4[0]\ : NOR3C - port map(A => data_addr_r_iv_i_1(0), B => - data_addr_r_iv_i_0(0), C => N_73, Y => - data_addr_r_iv_i_3(0)); - - un18_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : AX1D - port map(A => N165_1, B => N80, C => \un18_ready0_1[4]\, Y - => \un18_ready0[4]\); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, C => \data_mem_addr_w_0[2]\, Y - => \DWACT_FINC_E[0]\); - - un3_ready_0_0_0_ADD_5x5_fast_I18_Y_0 : XNOR2 - port map(A => N_6, B => N_89_i, Y => \un3_ready0[4]\); - - un18_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - \Waddr_vect_RNIVOFL[0]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[0]\, Y => N_157); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_0[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_3, Y => - un5_sfull_s_4_1); - - \ready_gen.un12_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_w_0[0]\, Y => N_6_0); - - \Waddr_vect_RNIB0LI2[1]\ : NOR3C - port map(A => N_149, B => data_addr_w_iv_i_2(1), C => N_150, - Y => data_addr_w_iv_i_4(1)); - - un18_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1B - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N_84_1, Y => N77); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[3]\); - - sFull_RNO_4 : OR2B - port map(A => I_5_13, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - \Raddr_vect_RNI7G73_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_0[4]\, B => - \data_mem_addr_w_0[4]\, Y => N_75); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_0[2]\, Y => sEmpty_RNO_5_1); - - \Raddr_vect_RNI9B352[3]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[3]\, Y => N_49); - - un3_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3 : AOI1 - port map(A => ADD_5x5_fast_I9_Y_i_o2_0, B => Waddr_vect_c1, - C => \data_mem_addr_r_0[2]\, Y => N_17); - - \Raddr_vect_RNI7G73[4]\ : XNOR2 - port map(A => \data_mem_addr_w_0[4]\, B => - \data_mem_addr_r_0[4]\, Y => N_89_i); - - \Raddr_vect_RNIM38B[4]\ : NOR2B - port map(A => I_5_14, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_0[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - un3_ready_1_1_0_SUM2_0_0 : XOR2 - port map(A => N_89_i, B => N_109, Y => SUM2_0_0); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[4]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_0[2]\, Y => - I_9_13); - - \ready_gen.un12_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, C => N_6_0, Y => N_8); - - \ready_gen.un12_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, Y => N_4_1); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(0), Y => un1_sempty_s); - - \Raddr_vect_RNICK9Q4[2]\ : NOR3C - port map(A => data_addr_r_iv_i_1(2), B => - data_addr_r_iv_i_0(2), C => N_57, Y => - data_addr_r_iv_i_3(2)); - - \Waddr_vect_RNI9473[3]\ : NOR2 - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_w_0[2]\, Y => un1_waddr_vect_slto3_0); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_0[4]\, Y => - I_20_6); - - \ready_gen.un12_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_0[4]\, B => - \data_mem_addr_w_0[4]\, Y => N_7); - - \Raddr_vect_RNI709Q4[1]\ : NOR3C - port map(A => data_addr_r_iv_i_1(1), B => - data_addr_r_iv_i_0(1), C => N_65, Y => - data_addr_r_iv_i_3(1)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ4 is - - port( time_mem_ren_i_0_1 : in std_logic; - time_wen : in std_logic_vector(0 to 0); - time_ren : in std_logic_vector(0 to 0); - data_addr_w_0_iv_i_1 : out std_logic_vector(5 to 5); - Waddr_vect_RNILN58 : in std_logic_vector(0 to 0); - Waddr_vect_RNINV58 : in std_logic_vector(2 to 2); - Waddr_vect_RNI64MA : in std_logic_vector(2 to 2); - data_addr_w_iv_i_2_0 : out std_logic; - data_addr_w_iv_i_2_2 : out std_logic; - time_mem_wen_i_0 : out std_logic_vector(0 to 0); - data_addr_r_0_iv_i_1 : in std_logic_vector(5 to 5); - data_addr_r_0_iv_i_2 : out std_logic_vector(5 to 5); - Raddr_vect_RNI8J9L : in std_logic_vector(2 to 2); - data_addr_r_iv_i_0 : out std_logic_vector(4 downto 0); - data_addr_w_iv_i_1_0 : out std_logic; - data_addr_w_iv_i_1_3 : out std_logic; - data_addr_w_iv_i_1_1 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_77 : out std_logic; - sFull_RNI9VRD : in std_logic; - N_140 : in std_logic; - sFull_RNIPQBB_0 : in std_logic; - N_122 : in std_logic; - N_124 : in std_logic; - sFull_RNI9VRD_0 : in std_logic; - N_146 : in std_logic; - N_70 : in std_logic; - sEmpty_RNI5EFO_0 : in std_logic; - N_33 : in std_logic; - N_62 : in std_logic; - N_155 : in std_logic; - sFull_RNI9VRD_1 : in std_logic; - N_147 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ4; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ4 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \time_mem_addr_r_0[4]\, \Raddr_vect[2]_net_1\, - \Raddr_vect[3]_net_1\, N_4, \time_mem_addr_w_0[4]\, - \Waddr_vect[2]_net_1\, \Waddr_vect[3]_net_1\, N_4_0, N_7, - \time_mem_addr_r_0[1]\, \time_mem_addr_r_0[0]\, N_7_0, - \time_mem_addr_w_0[1]\, \time_mem_addr_w_0[0]\, - \data_addr_w_iv_i_0[1]\, \data_addr_w_iv_i_0[3]\, - \data_addr_w_iv_i_0[0]\, \time_mem_ren_i_0[0]\, - \time_mem_addr_r_0[3]\, \sEmpty_RNI2EFO\, - \data_addr_w_iv_i_0[4]\, \time_mem_wen_i_0[0]\, - \time_mem_addr_w_0[3]\, \data_addr_w_iv_i_0[2]\, - \sFull_RNIBMR8\, un7_sempty_s_3, \sEmpty_RNO_3\, - \sEmpty_RNO_4\, un7_sempty_s_0, un7_sempty_s_2, - \un10_raddr_vect_s[3]\, \un10_raddr_vect_s[0]\, - un5_sfull_s_2, \un8_waddr_vect_s[3]\, un5_sfull_s_1, - \un8_waddr_vect_s[1]\, \sFull_RNO_5\, un5_sfull_s_0, - \un8_waddr_vect_s[0]\, un2_raddr_vect_slt3, - un1_waddr_vect_slt3, un5_sfull_s, Raddr_vect_n3, - Raddr_vect_7_0, Waddr_vect_n3, Waddr_vect_15_0, - Raddr_vect_n2, un2_raddr_vect_s, Raddr_vect_n2_tz, - Waddr_vect_n2, un1_waddr_vect_s, Waddr_vect_n2_tz, - \sEmpty\, un2_sempty_s, \sFull\, \sEmpty_RNO_0\, - \sFull_RNO_0\, I_13_6, I_5_5, I_13_5, I_5_6, I_9_6, I_9_5, - Raddr_vect_n1_i, Raddr_vect_e2, Raddr_vect_e1, - Raddr_vect_e0, Waddr_vect_n1_i, Waddr_vect_e2, - Waddr_vect_e1, Waddr_vect_e0, N_4_1, N_4_2, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - time_mem_wen_i_0(0) <= \time_mem_wen_i_0[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_addr_w_0[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4_1); - - sFull_RNI8KFI1 : NOR3C - port map(A => sFull_RNI9VRD_0, B => \data_addr_w_iv_i_0[4]\, - C => N_124, Y => data_addr_w_iv_i_2_2); - - \Waddr_vect_RNI4JHO[1]\ : AND2 - port map(A => N_147, B => \data_addr_w_iv_i_0[1]\, Y => - data_addr_w_iv_i_1_1); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_addr_r_0[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - sEmpty_RNI2EFO : OR2 - port map(A => \time_mem_ren_i_0[0]\, B => N_4, Y => - \sEmpty_RNI2EFO\); - - \Waddr_vect_RNITOG9[1]\ : OR3 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_addr_w_0[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_0\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_0[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_wen_i_0[0]\, Q => - \Waddr_vect[3]_net_1\); - - sFull_RNIBMR8 : OR2 - port map(A => \time_mem_wen_i_0[0]\, B => N_4_0, Y => - \sFull_RNIBMR8\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_6); - - \Raddr_vect_RNICUIA1[1]\ : OA1 - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_ren_i_0[0]\, C => N_62, Y => - data_addr_r_iv_i_0(1)); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_0\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[0]\, - C => \time_mem_addr_w_0[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Waddr_vect[2]_net_1\); - - sFull_RNIA4G2 : OR2 - port map(A => time_wen(0), B => \sFull\, Y => - \time_mem_wen_i_0[0]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_0[1]\, - S => \time_mem_wen_i_0[0]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, Y => I_5_5); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - sEmpty_RNINO741 : NOR2B - port map(A => time_mem_ren_i_0_1, B => - \time_mem_ren_i_0[0]\, Y => N_77); - - \Waddr_vect_RNIVIRD[1]\ : OA1 - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_wen_i_0[0]\, C => N_146, Y => - \data_addr_w_iv_i_0[1]\); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_ren_i_0[0]\, Q => - \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(0), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4_1, B => \Waddr_vect[3]_net_1\, Y => - I_13_5); - - sFull_RNO : AO1 - port map(A => time_ren(0), B => \sFull\, C => un5_sfull_s, - Y => \sFull_RNO_0\); - - sEmpty_RNIBS3I : OR2 - port map(A => time_ren(0), B => \sEmpty\, Y => - \time_mem_ren_i_0[0]\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[0]\, - C => \time_mem_addr_r_0[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_0[1]\, - S => \time_mem_ren_i_0[0]\, Y => Raddr_vect_e1); - - \Raddr_vect_RNIAMIA1[0]\ : OA1 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_ren_i_0[0]\, C => N_70, Y => - data_addr_r_iv_i_0(0)); - - sFull_RNO_4 : OR2B - port map(A => I_5_5, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_0[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_6, C => - \Waddr_vect[2]_net_1\, Y => \sEmpty_RNO_3\); - - sEmpty_RNI7SUG1_0 : OA1 - port map(A => \time_mem_addr_r_0[3]\, B => - \time_mem_ren_i_0[0]\, C => sEmpty_RNI5EFO_0, Y => - data_addr_r_iv_i_0(3)); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Raddr_vect[2]_net_1\); - - \Raddr_vect_RNIE6JA1[2]\ : OA1A - port map(A => \Raddr_vect[2]_net_1\, B => - \time_mem_ren_i_0[0]\, C => Raddr_vect_RNI8J9L(2), Y => - data_addr_r_iv_i_0(2)); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_0[0]\); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_5, C => - \Raddr_vect[2]_net_1\, Y => \sFull_RNO_5\); - - sFull_RNI4H7K : OA1B - port map(A => \time_mem_addr_w_0[4]\, B => - \time_mem_wen_i_0[0]\, C => N_122, Y => - \data_addr_w_iv_i_0[4]\); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[0]\, Y => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_6, C => - \time_mem_addr_w_0[1]\, Y => \sEmpty_RNO_4\); - - sFull_RNO_3 : XA1 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, C => time_ren(0), Y => - un5_sfull_s_2); - - sEmpty_RNO_0 : NOR3C - port map(A => \sEmpty_RNO_3\, B => \sEmpty_RNO_4\, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un25_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_0[4]\); - - sFull_RNIDG321 : NOR3B - port map(A => \sFull_RNIBMR8\, B => sFull_RNI9VRD, C => - N_122, Y => data_addr_w_0_iv_i_1(5)); - - \Waddr_vect_RNI1RRD[2]\ : OA1A - port map(A => \Waddr_vect[2]_net_1\, B => - \time_mem_wen_i_0[0]\, C => Waddr_vect_RNINV58(2), Y => - \data_addr_w_iv_i_0[2]\); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - un25_mem_addr_ren_I_12 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => N_4); - - sEmpty_RNO_7 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_0[0]\, - Y => \un10_raddr_vect_s[0]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[0]\, Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_0[0]\); - - sEmpty_RNI7SUG1 : OA1B - port map(A => \time_mem_addr_r_0[4]\, B => - \time_mem_ren_i_0[0]\, C => N_33, Y => - data_addr_r_iv_i_0(4)); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_addr_r_0[0]\, Y => N_7); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => I_9_5); - - \Waddr_vect_RNIU7O51[2]\ : NOR3C - port map(A => Waddr_vect_RNI64MA(2), B => - \data_addr_w_iv_i_0[2]\, C => N_140, Y => - data_addr_w_iv_i_2_0); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_2, B => \Raddr_vect[3]_net_1\, Y => - I_13_6); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_2); - - sFull_RNIDG321_0 : AND2 - port map(A => sFull_RNI9VRD_1, B => \data_addr_w_iv_i_0[3]\, - Y => data_addr_w_iv_i_1_3); - - sEmpty_RNO_1 : XA1B - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, C => time_ren(0), Y => - un7_sempty_s_2); - - sFull_RNO_1 : XA1 - port map(A => \un8_waddr_vect_s[1]\, B => - \time_mem_addr_r_0[1]\, C => \sFull_RNO_5\, Y => - un5_sfull_s_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, Y => I_5_6); - - \Raddr_vect_RNIEOG9[1]\ : OR3 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - sFull_RNO_7 : OR2B - port map(A => I_13_5, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Waddr_vect_RNIUJMC[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - sEmpty_RNIQOT13 : NOR3B - port map(A => \sEmpty_RNI2EFO\, B => - data_addr_r_0_iv_i_1(5), C => N_33, Y => - data_addr_r_0_iv_i_2(5)); - - un29_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_0[4]\); - - un25_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_0[3]\); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_1, B => un5_sfull_s_0, C => - un5_sfull_s_2, Y => un5_sfull_s); - - sEmpty_RNO_6 : OR2B - port map(A => I_13_6, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un29_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_0[3]\); - - sFull : DFN1C0 - port map(D => \sFull_RNO_0\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Waddr_vect_RNITARD[0]\ : OA1 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_wen_i_0[0]\, C => Waddr_vect_RNILN58(0), Y => - \data_addr_w_iv_i_0[0]\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_0[1]\); - - un29_mem_addr_wen_I_12 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => N_4_0); - - sFull_RNO_2 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_0[0]\, C => time_wen(0), Y => - un5_sfull_s_0); - - sFull_RNI4H7K_0 : OA1 - port map(A => \time_mem_addr_w_0[3]\, B => - \time_mem_wen_i_0[0]\, C => sFull_RNIPQBB_0, Y => - \data_addr_w_iv_i_0[3]\); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_0[0]\, C => time_wen(0), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - \Raddr_vect_RNIAJMC[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - \Waddr_vect_RNI17HO[0]\ : AND2 - port map(A => N_155, B => \data_addr_w_iv_i_0[0]\, Y => - data_addr_w_iv_i_1_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ6 is - - port( Waddr_vect_RNI64MA : out std_logic_vector(2 to 2); - data_addr_w_1_iv_i_s_0_0 : in std_logic_vector(6 to 6); - time_wen : in std_logic_vector(2 to 2); - data_addr_r_0_iv_i_1 : out std_logic_vector(5 to 5); - data_addr_r_1_iv_i_s_1 : out std_logic_vector(6 to 6); - time_mem_ren_i_0_1 : in std_logic; - data_addr_r_iv_i_a2_0 : out std_logic_vector(4 to 4); - data_addr_r_iv_i_1 : out std_logic_vector(4 downto 0); - time_ren : in std_logic_vector(2 to 2); - time_ren_1z : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sFull_RNI9VRD_0 : out std_logic; - N_147 : out std_logic; - sFull_RNI9VRD_1 : out std_logic; - sFull_RNI9VRD : out std_logic; - un13_time_write : in std_logic; - N_163 : out std_logic; - N_155 : out std_logic; - N_162 : in std_logic; - sFull_RNIU5GK1 : out std_logic; - N_29 : in std_logic; - N_30_1 : in std_logic; - N_72 : in std_logic; - N_56 : in std_logic; - N_48 : in std_logic; - N_35 : in std_logic; - N_64 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ6; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ6 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \time_mem_addr_r_2[4]\, \Raddr_vect[2]_net_1\, - \Raddr_vect[3]_net_1\, N_4, \time_mem_addr_w_2[4]\, - \Waddr_vect[2]_net_1\, \Waddr_vect[3]_net_1\, N_4_0, N_7, - \time_mem_addr_r_2[1]\, \time_mem_addr_r_2[0]\, N_7_0, - \time_mem_addr_w_2[1]\, \time_mem_addr_w_2[0]\, - \un2_sfull_s_3_0\, \un8_waddr_vect_s[3]\, - \un10_sempty_s_3_0\, \un10_raddr_vect_s[3]\, - un5_sfull_s_2, un7_sempty_s_2, \time_mem_ren_i_0[2]\, - \time_mem_addr_r_2[3]\, un5_sfull_s_3, \sFull_RNO_3\, - \sFull_RNO_4\, un5_sfull_s_0, \un8_waddr_vect_s[0]\, - un7_sempty_s_3, sEmpty_RNO_3_0, sEmpty_RNO_4_0, - un7_sempty_s_0, \un10_raddr_vect_s[0]\, - un2_raddr_vect_slt3, \time_mem_wen_i_0[2]\, - un1_waddr_vect_slt3, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, Raddr_vect_c1, - Raddr_vect_n2, un2_raddr_vect_s, Waddr_vect_n2, - un1_waddr_vect_s, Waddr_vect_n2_tz, I_13_7, I_9_7, I_5_7, - I_9_8, I_5_8, Raddr_vect_n1_i, N_50, Raddr_vect_e2, - Raddr_vect_e1, Raddr_vect_e0, I_13_8, \sFull_RNO_1\, - un8_sfull_s, \sEmpty_RNO_1\, un2_sempty_s, \sFull\, - \sEmpty\, Waddr_vect_n1_i, Waddr_vect_e2, Waddr_vect_e1, - Waddr_vect_e0, \time_mem_addr_w_2[3]\, N_4_1, N_4_2, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_2[1]\, B => - \time_mem_addr_w_2[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4_1); - - un37_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_2[4]\); - - sEmpty_RNITO232 : NOR3C - port map(A => N_30_1, B => \time_mem_ren_i_0[2]\, C => N_29, - Y => data_addr_r_1_iv_i_s_1(6)); - - \Raddr_vect_RNO_0[1]\ : AX1C - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_2[1]\, - C => N_50, Y => Raddr_vect_n1_i); - - \Waddr_vect_RNI4SLA[0]\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - \time_mem_addr_w_2[0]\, Y => N_155); - - \sFull_RNI9VRD_1\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - \time_mem_addr_w_2[3]\, Y => sFull_RNI9VRD_1); - - \sFull_RNI9VRD_0\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - \time_mem_addr_w_2[4]\, Y => sFull_RNI9VRD_0); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_2[1]\, B => - \time_mem_addr_w_2[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_1\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_2[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_wen_i_0[2]\, Q => - \Waddr_vect[3]_net_1\); - - \Raddr_vect_RNIKOG9[1]\ : OR3 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_8); - - un2_sfull_s_3_0_RNO : OR2B - port map(A => I_13_7, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_1\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[2]\, - C => \time_mem_addr_w_2[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Waddr_vect[2]_net_1\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_2[1]\, - S => \time_mem_wen_i_0[2]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, Y => I_5_7); - - \sFull_RNI9VRD\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => N_4_0, - Y => sFull_RNI9VRD); - - \Raddr_vect_RNO_0[2]\ : XAI1 - port map(A => \Raddr_vect[2]_net_1\, B => Raddr_vect_c1, C - => un2_raddr_vect_s, Y => Raddr_vect_n2); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_ren_i_0[2]\, Q => - \Raddr_vect[3]_net_1\); - - \Waddr_vect_RNI64MA[2]\ : OR3A - port map(A => \Waddr_vect[2]_net_1\, B => N_162, C => - \time_mem_wen_i_0[2]\, Y => Waddr_vect_RNI64MA(2)); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(2), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4_1, B => \Waddr_vect[3]_net_1\, Y => - I_13_7); - - un2_sfull_s_3_0 : XOR2 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, Y => \un2_sfull_s_3_0\); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO_1\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[2]\, - C => \time_mem_addr_r_2[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_2[1]\, - S => \time_mem_ren_i_0[2]\, Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_7, C => - \time_mem_addr_r_2[1]\, Y => \sFull_RNO_4\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_2[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_8, C => - \Waddr_vect[2]_net_1\, Y => sEmpty_RNO_3_0); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Raddr_vect[2]_net_1\); - - sEmpty_RNIJSUG1_0 : OA1 - port map(A => N_4, B => \time_mem_ren_i_0[2]\, C => N_35, Y - => data_addr_r_0_iv_i_1(5)); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_2[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_2[0]\, C => time_wen(2), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[2]\, Y => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_8, C => - \time_mem_addr_w_2[1]\, Y => sEmpty_RNO_4_0); - - \Raddr_vect_RNIN1B6[1]\ : NOR2B - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_addr_r_2[0]\, Y => Raddr_vect_c1); - - \Waddr_vect_RNI3PG9[1]\ : OR3 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - un10_sempty_s_3_0 : XOR2 - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, Y => \un10_sempty_s_3_0\); - - \Raddr_vect_RNIIMIA1[0]\ : OA1 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_ren_i_0[2]\, C => N_72, Y => - data_addr_r_iv_i_1(0)); - - un43_mem_addr_wen_I_12 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => N_4_0); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_7, C => - \Raddr_vect[2]_net_1\, Y => \sFull_RNO_3\); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_0, B => sEmpty_RNO_4_0, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un43_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_2[4]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[2]\, Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_2[0]\); - - \Waddr_vect_RNI50MA[1]\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - \time_mem_addr_w_2[1]\, Y => N_147); - - sEmpty_RNIRO741 : NOR2B - port map(A => time_mem_ren_i_0_1, B => - \time_mem_ren_i_0[2]\, Y => data_addr_r_iv_i_a2_0(4)); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_addr_r_2[0]\, Y => N_7); - - un10_sempty_s_3_0_RNO : OR2B - port map(A => I_13_8, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => I_9_7); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_2, B => \Raddr_vect[3]_net_1\, Y => - I_13_8); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_2); - - \Raddr_vect_RNIKUIA1[1]\ : OA1 - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_ren_i_0[2]\, C => N_64, Y => - data_addr_r_iv_i_1(1)); - - sEmpty_RNO_1 : NOR2A - port map(A => \un10_sempty_s_3_0\, B => time_ren(2), Y => - un7_sempty_s_2); - - \Raddr_vect_RNIM6JA1[2]\ : OA1A - port map(A => \Raddr_vect[2]_net_1\, B => - \time_mem_ren_i_0[2]\, C => N_56, Y => - data_addr_r_iv_i_1(2)); - - sEmpty_RNIDS3I : OR3A - port map(A => time_ren_1z, B => un13_time_write, C => - \sEmpty\, Y => \time_mem_ren_i_0[2]\); - - sFull_RNO_1 : AND2 - port map(A => time_ren(2), B => \un2_sfull_s_3_0\, Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, Y => I_5_8); - - un43_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_2[3]\); - - \Waddr_vect_RNI6KMC[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - un37_mem_addr_ren_I_12 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => N_4); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - \Raddr_vect_RNO_0[3]\ : OR2B - port map(A => Raddr_vect_c1, B => \Raddr_vect[2]_net_1\, Y - => Raddr_vect_7_0); - - \Raddr_vect_RNIIJMC[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNI4DG7 : NOR2A - port map(A => \time_mem_wen_i_0[2]\, B => N_162, Y => N_163); - - sFull_RNO_0 : NOR3C - port map(A => \sFull_RNO_3\, B => \sFull_RNO_4\, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_2[0]\, - Y => \un10_raddr_vect_s[0]\); - - un37_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_2[3]\); - - sEmpty_RNIJSUG1_1 : OA1 - port map(A => \time_mem_addr_r_2[4]\, B => - \time_mem_ren_i_0[2]\, C => N_35, Y => - data_addr_r_iv_i_1(4)); - - \Raddr_vect_RNO_1[1]\ : OR2B - port map(A => \time_mem_addr_r_2[0]\, B => un2_raddr_vect_s, - Y => N_50); - - sFull : DFN1C0 - port map(D => \sFull_RNO_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \sFull_RNIU5GK1\ : OAI1 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - data_addr_w_1_iv_i_s_0_0(6), Y => sFull_RNIU5GK1); - - sFull_RNIE4G2 : OR2 - port map(A => time_wen(2), B => \sFull\, Y => - \time_mem_wen_i_0[2]\); - - sEmpty_RNIJSUG1 : OA1 - port map(A => \time_mem_addr_r_2[3]\, B => - \time_mem_ren_i_0[2]\, C => N_48, Y => - data_addr_r_iv_i_1(3)); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_2[1]\); - - sFull_RNO_2 : OA1A - port map(A => time_ren_1z, B => un13_time_write, C => - \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_2[0]\, C => time_wen(2), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo is - - port( data_wen : in std_logic_vector(3 downto 0); - data_ren : in std_logic_vector(3 downto 0); - ready_i_0 : out std_logic_vector(3 downto 0); - time_ren : in std_logic_vector(3 downto 0); - time_wen : in std_logic_vector(3 downto 0); - wdata : in std_logic_vector(31 downto 0); - hwdata_c : out std_logic_vector(31 downto 0); - time_ren_1z : in std_logic; - data_ren_1z : in std_logic; - un20_time_write : in std_logic; - un13_time_write : in std_logic; - HRESETn_c : in std_logic; - lpp_waveform_fifo_VCC : in std_logic; - lpp_waveform_fifo_GND : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_waveform_fifo; - -architecture DEF_ARCH of lpp_waveform_fifo is - - component lpp_waveform_fifo_ctrlZ1 - port( ready_i_0 : out std_logic_vector(1 to 1); - Raddr_vect_RNICA1PH : out std_logic_vector(1 to 1); - data_mem_wen_i_0 : inout std_logic_vector(2 downto 1); - Raddr_vect_RNIIMQ5I : out std_logic_vector(4 to 4); - Raddr_vect_RNIE6Q5I : out std_logic_vector(3 to 3); - Raddr_vect_RNIKA2PH : out std_logic_vector(2 to 2); - data_addr_r_iv_i_3 : in std_logic_vector(4 downto 0) := (others => 'U'); - Raddr_vect_RNI4A0PH : out std_logic_vector(0 to 0); - data_addr_r_iv_i_a2_2 : in std_logic_vector(4 to 4) := (others => 'U'); - data_wen : in std_logic_vector(1 to 1) := (others => 'U'); - data_mem_ren_i_0 : inout std_logic_vector(1 downto 0); - data_ren : in std_logic_vector(1 to 1) := (others => 'U'); - data_ren_1z : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_166 : out std_logic; - N_126 : out std_logic; - N_150 : out std_logic; - N_134 : out std_logic; - N_142 : out std_logic; - N_165 : in std_logic := 'U'; - N_158 : out std_logic; - un20_time_write : in std_logic := 'U'; - N_68 : in std_logic := 'U'; - N_164 : in std_logic := 'U'; - N_120_i : out std_logic; - N_44 : in std_logic := 'U'; - N_52 : in std_logic := 'U'; - N_60 : in std_logic := 'U'; - N_76 : in std_logic := 'U'; - N_86 : out std_logic; - N_75 : in std_logic := 'U'; - N_59 : in std_logic := 'U'; - N_51 : in std_logic := 'U'; - N_43 : in std_logic := 'U'; - N_67 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ7 - port( time_mem_addr_w_3_i_0_1 : out std_logic; - data_addr_w_1_iv_i_a2_1_1_0 : in std_logic_vector(6 to 6) := (others => 'U'); - data_addr_w_1_iv_i_s_0_0 : out std_logic_vector(6 to 6); - time_wen : in std_logic_vector(3 to 3) := (others => 'U'); - time_ren : in std_logic_vector(3 to 3) := (others => 'U'); - data_mem_ren_i_0 : in std_logic_vector(1 to 1) := (others => 'U'); - time_mem_ren_i_0 : out std_logic_vector(3 to 3); - data_addr_r_1_iv_i_a9_1_1 : out std_logic_vector(6 to 6); - time_mem_addr_w_3 : out std_logic_vector(1 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_124 : out std_logic; - N_64 : out std_logic; - N_140 : out std_logic; - N_30_1 : out std_logic; - N_89 : out std_logic; - N_163 : in std_logic := 'U'; - N_164 : out std_logic; - N_72 : out std_logic; - N_56 : out std_logic; - N_48 : out std_logic; - N_35 : out std_logic; - N_113 : in std_logic := 'U'; - N_162 : in std_logic := 'U'; - N_77 : in std_logic := 'U' - ); - end component; - - component syncram_2pZ1 - port( hwdata_c : out std_logic_vector(31 downto 0); - Raddr_vect_RNI4A0PH : in std_logic_vector(0 to 0) := (others => 'U'); - Raddr_vect_RNICA1PH : in std_logic_vector(1 to 1) := (others => 'U'); - Raddr_vect_RNIKA2PH : in std_logic_vector(2 to 2) := (others => 'U'); - Raddr_vect_RNIE6Q5I : in std_logic_vector(3 to 3) := (others => 'U'); - Raddr_vect_RNIIMQ5I : in std_logic_vector(4 to 4) := (others => 'U'); - Waddr_vect_RNION355 : in std_logic_vector(0 to 0) := (others => 'U'); - Waddr_vect_RNI0O455 : in std_logic_vector(1 to 1) := (others => 'U'); - Waddr_vect_RNI394D5 : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_RNIJTNE5 : in std_logic_vector(3 to 3) := (others => 'U'); - Waddr_vect_RNILLSP5 : in std_logic_vector(4 to 4) := (others => 'U'); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - HCLK_c : in std_logic := 'U'; - N_1_i_1 : in std_logic := 'U'; - sEmpty_RNIE7T87 : in std_logic := 'U'; - sEmpty_RNILSD08 : in std_logic := 'U'; - sFull_RNIHL443 : in std_logic := 'U'; - sFull_RNIU5GK1 : in std_logic := 'U'; - syncram_2pZ1_GND : in std_logic := 'U'; - syncram_2pZ1_VCC : in std_logic := 'U'; - N_1_i_1_i : in std_logic := 'U' - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ2 - port( ready_i_0 : out std_logic_vector(2 to 2); - data_mem_wen_i_0 : out std_logic_vector(2 to 2); - data_ren : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_RNI0O455 : out std_logic_vector(1 to 1); - Waddr_vect_RNILLSP5 : out std_logic_vector(4 to 4); - Waddr_vect_RNIJTNE5 : out std_logic_vector(3 to 3); - Waddr_vect_RNI394D5 : out std_logic_vector(2 to 2); - data_mem_ren_i_0_0 : in std_logic := 'U'; - data_addr_r_0_iv_i_2 : in std_logic_vector(5 to 5) := (others => 'U'); - data_addr_w_iv_i_4 : in std_logic_vector(4 downto 0) := (others => 'U'); - Waddr_vect_RNION355 : out std_logic_vector(0 to 0); - data_wen : in std_logic_vector(2 to 2) := (others => 'U'); - data_addr_r_iv_i_a2_0 : in std_logic_vector(4 to 4) := (others => 'U'); - data_addr_r_iv_i_a2_2 : out std_logic_vector(4 to 4); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_67 : out std_logic; - N_166 : in std_logic := 'U'; - N_75 : out std_logic; - N_59 : out std_logic; - N_51 : out std_logic; - N_43 : out std_logic; - N_152 : in std_logic := 'U'; - N_128 : in std_logic := 'U'; - N_136 : in std_logic := 'U'; - N_144 : in std_logic := 'U'; - sEmpty_RNIE7T87 : out std_logic; - N_160 : in std_logic := 'U'; - N_77 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_ctrlZ5 - port( time_mem_wen_i_0_0 : in std_logic := 'U'; - Waddr_vect_RNINV58 : out std_logic_vector(2 to 2); - Waddr_vect_RNILN58 : out std_logic_vector(0 to 0); - Raddr_vect_RNI8J9L : out std_logic_vector(2 to 2); - time_mem_ren_i_0 : out std_logic_vector(1 to 1); - time_wen : in std_logic_vector(1 to 1) := (others => 'U'); - time_ren : in std_logic_vector(1 to 1) := (others => 'U'); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_146 : out std_logic; - N_162 : out std_logic; - N_113 : out std_logic; - N_122 : out std_logic; - sFull_RNIPQBB_0 : out std_logic; - N_62 : out std_logic; - N_70 : out std_logic; - sEmpty_RNI5EFO_0 : out std_logic; - N_33 : out std_logic; - N_29 : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ3 - port( ready_i_0 : out std_logic_vector(3 to 3); - data_mem_wen_i_0_0 : in std_logic := 'U'; - data_ren : in std_logic_vector(3 to 3) := (others => 'U'); - data_wen : in std_logic_vector(3 to 3) := (others => 'U'); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_128 : out std_logic; - N_152 : out std_logic; - N_136 : out std_logic; - N_68 : out std_logic; - N_144 : out std_logic; - N_166 : in std_logic := 'U'; - N_160 : out std_logic; - N_76 : out std_logic; - N_60 : out std_logic; - N_52 : out std_logic; - N_86 : in std_logic := 'U'; - N_44 : out std_logic; - N_1_i_1 : out std_logic; - N_1_i_1_i : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ0 - port( ready_i_0 : out std_logic_vector(0 to 0); - data_ren : in std_logic_vector(0 to 0) := (others => 'U'); - data_addr_w_0_iv_i_1 : in std_logic_vector(5 to 5) := (others => 'U'); - data_addr_r_1_iv_i_s_1 : in std_logic_vector(6 to 6) := (others => 'U'); - data_addr_r_1_iv_i_a9_1_1 : in std_logic_vector(6 to 6) := (others => 'U'); - data_mem_ren_i_0 : out std_logic_vector(0 to 0); - data_mem_wen_i_0_1 : in std_logic := 'U'; - data_addr_w_1_iv_i_a2_1_1_0 : out std_logic_vector(6 to 6); - data_addr_w_iv_i_2 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_addr_w_iv_i_4 : out std_logic_vector(4 downto 0); - data_wen : in std_logic_vector(0 to 0) := (others => 'U'); - data_addr_r_iv_i_0 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_addr_r_iv_i_1 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_addr_r_iv_i_3 : out std_logic_vector(4 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_165 : out std_logic; - N_120_i : in std_logic := 'U'; - sFull_RNIHL443 : out std_logic; - sEmpty_RNILSD08 : out std_logic; - N_124 : in std_logic := 'U'; - N_164 : in std_logic := 'U'; - N_158 : in std_logic := 'U'; - N_142 : in std_logic := 'U'; - N_134 : in std_logic := 'U'; - N_126 : in std_logic := 'U'; - N_150 : in std_logic := 'U' - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ4 - port( time_mem_ren_i_0_1 : in std_logic := 'U'; - time_wen : in std_logic_vector(0 to 0) := (others => 'U'); - time_ren : in std_logic_vector(0 to 0) := (others => 'U'); - data_addr_w_0_iv_i_1 : out std_logic_vector(5 to 5); - Waddr_vect_RNILN58 : in std_logic_vector(0 to 0) := (others => 'U'); - Waddr_vect_RNINV58 : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_RNI64MA : in std_logic_vector(2 to 2) := (others => 'U'); - data_addr_w_iv_i_2_0 : out std_logic; - data_addr_w_iv_i_2_2 : out std_logic; - time_mem_wen_i_0 : out std_logic_vector(0 to 0); - data_addr_r_0_iv_i_1 : in std_logic_vector(5 to 5) := (others => 'U'); - data_addr_r_0_iv_i_2 : out std_logic_vector(5 to 5); - Raddr_vect_RNI8J9L : in std_logic_vector(2 to 2) := (others => 'U'); - data_addr_r_iv_i_0 : out std_logic_vector(4 downto 0); - data_addr_w_iv_i_1_0 : out std_logic; - data_addr_w_iv_i_1_3 : out std_logic; - data_addr_w_iv_i_1_1 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_77 : out std_logic; - sFull_RNI9VRD : in std_logic := 'U'; - N_140 : in std_logic := 'U'; - sFull_RNIPQBB_0 : in std_logic := 'U'; - N_122 : in std_logic := 'U'; - N_124 : in std_logic := 'U'; - sFull_RNI9VRD_0 : in std_logic := 'U'; - N_146 : in std_logic := 'U'; - N_70 : in std_logic := 'U'; - sEmpty_RNI5EFO_0 : in std_logic := 'U'; - N_33 : in std_logic := 'U'; - N_62 : in std_logic := 'U'; - N_155 : in std_logic := 'U'; - sFull_RNI9VRD_1 : in std_logic := 'U'; - N_147 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_ctrlZ6 - port( Waddr_vect_RNI64MA : out std_logic_vector(2 to 2); - data_addr_w_1_iv_i_s_0_0 : in std_logic_vector(6 to 6) := (others => 'U'); - time_wen : in std_logic_vector(2 to 2) := (others => 'U'); - data_addr_r_0_iv_i_1 : out std_logic_vector(5 to 5); - data_addr_r_1_iv_i_s_1 : out std_logic_vector(6 to 6); - time_mem_ren_i_0_1 : in std_logic := 'U'; - data_addr_r_iv_i_a2_0 : out std_logic_vector(4 to 4); - data_addr_r_iv_i_1 : out std_logic_vector(4 downto 0); - time_ren : in std_logic_vector(2 to 2) := (others => 'U'); - time_ren_1z : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sFull_RNI9VRD_0 : out std_logic; - N_147 : out std_logic; - sFull_RNI9VRD_1 : out std_logic; - sFull_RNI9VRD : out std_logic; - un13_time_write : in std_logic := 'U'; - N_163 : out std_logic; - N_155 : out std_logic; - N_162 : in std_logic := 'U'; - sFull_RNIU5GK1 : out std_logic; - N_29 : in std_logic := 'U'; - N_30_1 : in std_logic := 'U'; - N_72 : in std_logic := 'U'; - N_56 : in std_logic := 'U'; - N_48 : in std_logic := 'U'; - N_35 : in std_logic := 'U'; - N_64 : in std_logic := 'U' - ); - end component; - - signal N_156, N_89, \time_mem_addr_w_3[0]\, N_132, - \time_mem_addr_w_3_i_0[3]\, N_148, \time_mem_addr_w_3[1]\, - \data_addr_w_iv_i_2[3]\, \data_addr_w_iv_i_1[3]\, - \data_addr_w_iv_i_2[0]\, \data_addr_w_iv_i_1[0]\, - \data_addr_w_iv_i_2[1]\, \data_addr_w_iv_i_1[1]\, - \Raddr_vect_RNI4A0PH[0]\, \Raddr_vect_RNICA1PH[1]\, - \Raddr_vect_RNIKA2PH[2]\, \Raddr_vect_RNIE6Q5I[3]\, - \Raddr_vect_RNIIMQ5I[4]\, \Waddr_vect_RNION355[0]\, - \Waddr_vect_RNI0O455[1]\, \Waddr_vect_RNI394D5[2]\, - \Waddr_vect_RNIJTNE5[3]\, \Waddr_vect_RNILLSP5[4]\, - N_1_i_1, sEmpty_RNIE7T87, sEmpty_RNILSD08, sFull_RNIHL443, - sFull_RNIU5GK1, N_1_i_1_i, - \data_addr_w_1_iv_i_a2_1_1_0[6]\, - \data_addr_w_1_iv_i_s_0_0[6]\, \data_mem_ren_i_0[1]\, - \time_mem_ren_i_0[3]\, \data_addr_r_1_iv_i_a9_1_1[6]\, - N_124, N_64, N_140, N_30_1, N_163, N_164, N_72, N_56, - N_48, N_35, N_113, N_162, N_77, \time_mem_ren_i_0[1]\, - \data_addr_w_0_iv_i_1[5]\, \Waddr_vect_RNILN58[0]\, - \Waddr_vect_RNINV58[2]\, \Waddr_vect_RNI64MA[2]\, - \data_addr_w_iv_i_2[2]\, \data_addr_w_iv_i_2[4]\, - \time_mem_wen_i_0[0]\, \data_addr_r_0_iv_i_1[5]\, - \data_addr_r_0_iv_i_2[5]\, \Raddr_vect_RNI8J9L[2]\, - \data_addr_r_iv_i_0[0]\, \data_addr_r_iv_i_0[1]\, - \data_addr_r_iv_i_0[2]\, \data_addr_r_iv_i_0[3]\, - \data_addr_r_iv_i_0[4]\, sFull_RNI9VRD, sFull_RNIPQBB_0, - N_122, sFull_RNI9VRD_0, N_146, N_70, sEmpty_RNI5EFO_0, - N_33, N_62, N_155, sFull_RNI9VRD_1, N_147, - \data_addr_r_1_iv_i_s_1[6]\, \data_addr_r_iv_i_a2_0[4]\, - \data_addr_r_iv_i_1[0]\, \data_addr_r_iv_i_1[1]\, - \data_addr_r_iv_i_1[2]\, \data_addr_r_iv_i_1[3]\, - \data_addr_r_iv_i_1[4]\, N_29, \data_mem_wen_i_0[2]\, - N_128, N_152, N_136, N_68, N_144, N_166, N_160, N_76, - N_60, N_52, N_86, N_44, \data_mem_ren_i_0[0]\, - \data_mem_wen_i_0[1]\, \data_addr_w_iv_i_4[0]\, - \data_addr_w_iv_i_4[1]\, \data_addr_w_iv_i_4[2]\, - \data_addr_w_iv_i_4[3]\, \data_addr_w_iv_i_4[4]\, - \data_addr_r_iv_i_3[0]\, \data_addr_r_iv_i_3[1]\, - \data_addr_r_iv_i_3[2]\, \data_addr_r_iv_i_3[3]\, - \data_addr_r_iv_i_3[4]\, N_165, N_120_i, N_158, N_142, - N_134, N_126, N_150, \data_addr_r_iv_i_a2_2[4]\, N_67, - N_75, N_59, N_51, N_43, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : lpp_waveform_fifo_ctrlZ1 - Use entity work.lpp_waveform_fifo_ctrlZ1(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ7 - Use entity work.lpp_waveform_fifo_ctrlZ7(DEF_ARCH); - for all : syncram_2pZ1 - Use entity work.syncram_2pZ1(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ2 - Use entity work.lpp_waveform_fifo_ctrlZ2(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ5 - Use entity work.lpp_waveform_fifo_ctrlZ5(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ3 - Use entity work.lpp_waveform_fifo_ctrlZ3(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ0 - Use entity work.lpp_waveform_fifo_ctrlZ0(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ4 - Use entity work.lpp_waveform_fifo_ctrlZ4(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ6 - Use entity work.lpp_waveform_fifo_ctrlZ6(DEF_ARCH); -begin - - - \gen_fifo_ctrl_data.1.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ1 - port map(ready_i_0(1) => ready_i_0(1), - Raddr_vect_RNICA1PH(1) => \Raddr_vect_RNICA1PH[1]\, - data_mem_wen_i_0(2) => \data_mem_wen_i_0[2]\, - data_mem_wen_i_0(1) => \data_mem_wen_i_0[1]\, - Raddr_vect_RNIIMQ5I(4) => \Raddr_vect_RNIIMQ5I[4]\, - Raddr_vect_RNIE6Q5I(3) => \Raddr_vect_RNIE6Q5I[3]\, - Raddr_vect_RNIKA2PH(2) => \Raddr_vect_RNIKA2PH[2]\, - data_addr_r_iv_i_3(4) => \data_addr_r_iv_i_3[4]\, - data_addr_r_iv_i_3(3) => \data_addr_r_iv_i_3[3]\, - data_addr_r_iv_i_3(2) => \data_addr_r_iv_i_3[2]\, - data_addr_r_iv_i_3(1) => \data_addr_r_iv_i_3[1]\, - data_addr_r_iv_i_3(0) => \data_addr_r_iv_i_3[0]\, - Raddr_vect_RNI4A0PH(0) => \Raddr_vect_RNI4A0PH[0]\, - data_addr_r_iv_i_a2_2(4) => \data_addr_r_iv_i_a2_2[4]\, - data_wen(1) => data_wen(1), data_mem_ren_i_0(1) => - \data_mem_ren_i_0[1]\, data_mem_ren_i_0(0) => - \data_mem_ren_i_0[0]\, data_ren(1) => data_ren(1), - data_ren_1z => data_ren_1z, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, N_166 => N_166, N_126 => N_126, N_150 - => N_150, N_134 => N_134, N_142 => N_142, N_165 => N_165, - N_158 => N_158, un20_time_write => un20_time_write, N_68 - => N_68, N_164 => N_164, N_120_i => N_120_i, N_44 => - N_44, N_52 => N_52, N_60 => N_60, N_76 => N_76, N_86 => - N_86, N_75 => N_75, N_59 => N_59, N_51 => N_51, N_43 => - N_43, N_67 => N_67); - - GND_i_0 : GND - port map(Y => GND_0); - - \gen_fifo_ctrl_time.3.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ7 - port map(time_mem_addr_w_3_i_0_1 => - \time_mem_addr_w_3_i_0[3]\, - data_addr_w_1_iv_i_a2_1_1_0(6) => - \data_addr_w_1_iv_i_a2_1_1_0[6]\, - data_addr_w_1_iv_i_s_0_0(6) => - \data_addr_w_1_iv_i_s_0_0[6]\, time_wen(3) => time_wen(3), - time_ren(3) => time_ren(3), data_mem_ren_i_0(1) => - \data_mem_ren_i_0[1]\, time_mem_ren_i_0(3) => - \time_mem_ren_i_0[3]\, data_addr_r_1_iv_i_a9_1_1(6) => - \data_addr_r_1_iv_i_a9_1_1[6]\, time_mem_addr_w_3(1) => - \time_mem_addr_w_3[1]\, time_mem_addr_w_3(0) => - \time_mem_addr_w_3[0]\, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c, N_124 => N_124, N_64 => N_64, N_140 => N_140, - N_30_1 => N_30_1, N_89 => N_89, N_163 => N_163, N_164 => - N_164, N_72 => N_72, N_56 => N_56, N_48 => N_48, N_35 => - N_35, N_113 => N_113, N_162 => N_162, N_77 => N_77); - - SRAM : syncram_2pZ1 - port map(hwdata_c(31) => hwdata_c(31), hwdata_c(30) => - hwdata_c(30), hwdata_c(29) => hwdata_c(29), hwdata_c(28) - => hwdata_c(28), hwdata_c(27) => hwdata_c(27), - hwdata_c(26) => hwdata_c(26), hwdata_c(25) => - hwdata_c(25), hwdata_c(24) => hwdata_c(24), hwdata_c(23) - => hwdata_c(23), hwdata_c(22) => hwdata_c(22), - hwdata_c(21) => hwdata_c(21), hwdata_c(20) => - hwdata_c(20), hwdata_c(19) => hwdata_c(19), hwdata_c(18) - => hwdata_c(18), hwdata_c(17) => hwdata_c(17), - hwdata_c(16) => hwdata_c(16), hwdata_c(15) => - hwdata_c(15), hwdata_c(14) => hwdata_c(14), hwdata_c(13) - => hwdata_c(13), hwdata_c(12) => hwdata_c(12), - hwdata_c(11) => hwdata_c(11), hwdata_c(10) => - hwdata_c(10), hwdata_c(9) => hwdata_c(9), hwdata_c(8) => - hwdata_c(8), hwdata_c(7) => hwdata_c(7), hwdata_c(6) => - hwdata_c(6), hwdata_c(5) => hwdata_c(5), hwdata_c(4) => - hwdata_c(4), hwdata_c(3) => hwdata_c(3), hwdata_c(2) => - hwdata_c(2), hwdata_c(1) => hwdata_c(1), hwdata_c(0) => - hwdata_c(0), Raddr_vect_RNI4A0PH(0) => - \Raddr_vect_RNI4A0PH[0]\, Raddr_vect_RNICA1PH(1) => - \Raddr_vect_RNICA1PH[1]\, Raddr_vect_RNIKA2PH(2) => - \Raddr_vect_RNIKA2PH[2]\, Raddr_vect_RNIE6Q5I(3) => - \Raddr_vect_RNIE6Q5I[3]\, Raddr_vect_RNIIMQ5I(4) => - \Raddr_vect_RNIIMQ5I[4]\, Waddr_vect_RNION355(0) => - \Waddr_vect_RNION355[0]\, Waddr_vect_RNI0O455(1) => - \Waddr_vect_RNI0O455[1]\, Waddr_vect_RNI394D5(2) => - \Waddr_vect_RNI394D5[2]\, Waddr_vect_RNIJTNE5(3) => - \Waddr_vect_RNIJTNE5[3]\, Waddr_vect_RNILLSP5(4) => - \Waddr_vect_RNILLSP5[4]\, wdata(31) => wdata(31), - wdata(30) => wdata(30), wdata(29) => wdata(29), wdata(28) - => wdata(28), wdata(27) => wdata(27), wdata(26) => - wdata(26), wdata(25) => wdata(25), wdata(24) => wdata(24), - wdata(23) => wdata(23), wdata(22) => wdata(22), wdata(21) - => wdata(21), wdata(20) => wdata(20), wdata(19) => - wdata(19), wdata(18) => wdata(18), wdata(17) => wdata(17), - wdata(16) => wdata(16), wdata(15) => wdata(15), wdata(14) - => wdata(14), wdata(13) => wdata(13), wdata(12) => - wdata(12), wdata(11) => wdata(11), wdata(10) => wdata(10), - wdata(9) => wdata(9), wdata(8) => wdata(8), wdata(7) => - wdata(7), wdata(6) => wdata(6), wdata(5) => wdata(5), - wdata(4) => wdata(4), wdata(3) => wdata(3), wdata(2) => - wdata(2), wdata(1) => wdata(1), wdata(0) => wdata(0), - HCLK_c => HCLK_c, N_1_i_1 => N_1_i_1, sEmpty_RNIE7T87 => - sEmpty_RNIE7T87, sEmpty_RNILSD08 => sEmpty_RNILSD08, - sFull_RNIHL443 => sFull_RNIHL443, sFull_RNIU5GK1 => - sFull_RNIU5GK1, syncram_2pZ1_GND => lpp_waveform_fifo_GND, - syncram_2pZ1_VCC => lpp_waveform_fifo_VCC, N_1_i_1_i => - N_1_i_1_i); - - \data_addr_w_iv_i_a2_2[0]\ : OR2A - port map(A => N_89, B => \time_mem_addr_w_3[0]\, Y => N_156); - - \data_addr_w_iv_i_a2_2_RNIRMOT[0]\ : AND2 - port map(A => \data_addr_w_iv_i_1[0]\, B => N_156, Y => - \data_addr_w_iv_i_2[0]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \gen_fifo_ctrl_data.2.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ2 - port map(ready_i_0(2) => ready_i_0(2), data_mem_wen_i_0(2) - => \data_mem_wen_i_0[2]\, data_ren(2) => data_ren(2), - Waddr_vect_RNI0O455(1) => \Waddr_vect_RNI0O455[1]\, - Waddr_vect_RNILLSP5(4) => \Waddr_vect_RNILLSP5[4]\, - Waddr_vect_RNIJTNE5(3) => \Waddr_vect_RNIJTNE5[3]\, - Waddr_vect_RNI394D5(2) => \Waddr_vect_RNI394D5[2]\, - data_mem_ren_i_0_0 => \data_mem_ren_i_0[0]\, - data_addr_r_0_iv_i_2(5) => \data_addr_r_0_iv_i_2[5]\, - data_addr_w_iv_i_4(4) => \data_addr_w_iv_i_4[4]\, - data_addr_w_iv_i_4(3) => \data_addr_w_iv_i_4[3]\, - data_addr_w_iv_i_4(2) => \data_addr_w_iv_i_4[2]\, - data_addr_w_iv_i_4(1) => \data_addr_w_iv_i_4[1]\, - data_addr_w_iv_i_4(0) => \data_addr_w_iv_i_4[0]\, - Waddr_vect_RNION355(0) => \Waddr_vect_RNION355[0]\, - data_wen(2) => data_wen(2), data_addr_r_iv_i_a2_0(4) => - \data_addr_r_iv_i_a2_0[4]\, data_addr_r_iv_i_a2_2(4) => - \data_addr_r_iv_i_a2_2[4]\, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, N_67 => N_67, N_166 => N_166, N_75 => - N_75, N_59 => N_59, N_51 => N_51, N_43 => N_43, N_152 => - N_152, N_128 => N_128, N_136 => N_136, N_144 => N_144, - sEmpty_RNIE7T87 => sEmpty_RNIE7T87, N_160 => N_160, N_77 - => N_77); - - GND_i : GND - port map(Y => \GND\); - - \gen_fifo_ctrl_time.1.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ5 - port map(time_mem_wen_i_0_0 => \time_mem_wen_i_0[0]\, - Waddr_vect_RNINV58(2) => \Waddr_vect_RNINV58[2]\, - Waddr_vect_RNILN58(0) => \Waddr_vect_RNILN58[0]\, - Raddr_vect_RNI8J9L(2) => \Raddr_vect_RNI8J9L[2]\, - time_mem_ren_i_0(1) => \time_mem_ren_i_0[1]\, time_wen(1) - => time_wen(1), time_ren(1) => time_ren(1), HRESETn_c - => HRESETn_c, HCLK_c => HCLK_c, N_146 => N_146, N_162 - => N_162, N_113 => N_113, N_122 => N_122, - sFull_RNIPQBB_0 => sFull_RNIPQBB_0, N_62 => N_62, N_70 - => N_70, sEmpty_RNI5EFO_0 => sEmpty_RNI5EFO_0, N_33 => - N_33, N_29 => N_29); - - \gen_fifo_ctrl_data.3.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ3 - port map(ready_i_0(3) => ready_i_0(3), data_mem_wen_i_0_0 - => \data_mem_wen_i_0[2]\, data_ren(3) => data_ren(3), - data_wen(3) => data_wen(3), HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, N_128 => N_128, N_152 => N_152, N_136 - => N_136, N_68 => N_68, N_144 => N_144, N_166 => N_166, - N_160 => N_160, N_76 => N_76, N_60 => N_60, N_52 => N_52, - N_86 => N_86, N_44 => N_44, N_1_i_1 => N_1_i_1, N_1_i_1_i - => N_1_i_1_i); - - \gen_fifo_ctrl_data.0.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ0 - port map(ready_i_0(0) => ready_i_0(0), data_ren(0) => - data_ren(0), data_addr_w_0_iv_i_1(5) => - \data_addr_w_0_iv_i_1[5]\, data_addr_r_1_iv_i_s_1(6) => - \data_addr_r_1_iv_i_s_1[6]\, data_addr_r_1_iv_i_a9_1_1(6) - => \data_addr_r_1_iv_i_a9_1_1[6]\, data_mem_ren_i_0(0) - => \data_mem_ren_i_0[0]\, data_mem_wen_i_0_1 => - \data_mem_wen_i_0[1]\, data_addr_w_1_iv_i_a2_1_1_0(6) => - \data_addr_w_1_iv_i_a2_1_1_0[6]\, data_addr_w_iv_i_2(4) - => \data_addr_w_iv_i_2[4]\, data_addr_w_iv_i_2(3) => - \data_addr_w_iv_i_2[3]\, data_addr_w_iv_i_2(2) => - \data_addr_w_iv_i_2[2]\, data_addr_w_iv_i_2(1) => - \data_addr_w_iv_i_2[1]\, data_addr_w_iv_i_2(0) => - \data_addr_w_iv_i_2[0]\, data_addr_w_iv_i_4(4) => - \data_addr_w_iv_i_4[4]\, data_addr_w_iv_i_4(3) => - \data_addr_w_iv_i_4[3]\, data_addr_w_iv_i_4(2) => - \data_addr_w_iv_i_4[2]\, data_addr_w_iv_i_4(1) => - \data_addr_w_iv_i_4[1]\, data_addr_w_iv_i_4(0) => - \data_addr_w_iv_i_4[0]\, data_wen(0) => data_wen(0), - data_addr_r_iv_i_0(4) => \data_addr_r_iv_i_0[4]\, - data_addr_r_iv_i_0(3) => \data_addr_r_iv_i_0[3]\, - data_addr_r_iv_i_0(2) => \data_addr_r_iv_i_0[2]\, - data_addr_r_iv_i_0(1) => \data_addr_r_iv_i_0[1]\, - data_addr_r_iv_i_0(0) => \data_addr_r_iv_i_0[0]\, - data_addr_r_iv_i_1(4) => \data_addr_r_iv_i_1[4]\, - data_addr_r_iv_i_1(3) => \data_addr_r_iv_i_1[3]\, - data_addr_r_iv_i_1(2) => \data_addr_r_iv_i_1[2]\, - data_addr_r_iv_i_1(1) => \data_addr_r_iv_i_1[1]\, - data_addr_r_iv_i_1(0) => \data_addr_r_iv_i_1[0]\, - data_addr_r_iv_i_3(4) => \data_addr_r_iv_i_3[4]\, - data_addr_r_iv_i_3(3) => \data_addr_r_iv_i_3[3]\, - data_addr_r_iv_i_3(2) => \data_addr_r_iv_i_3[2]\, - data_addr_r_iv_i_3(1) => \data_addr_r_iv_i_3[1]\, - data_addr_r_iv_i_3(0) => \data_addr_r_iv_i_3[0]\, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_165 => N_165, - N_120_i => N_120_i, sFull_RNIHL443 => sFull_RNIHL443, - sEmpty_RNILSD08 => sEmpty_RNILSD08, N_124 => N_124, N_164 - => N_164, N_158 => N_158, N_142 => N_142, N_134 => N_134, - N_126 => N_126, N_150 => N_150); - - \data_addr_w_iv_i_a2_2_RNIACB71[3]\ : AND2 - port map(A => N_132, B => \data_addr_w_iv_i_1[3]\, Y => - \data_addr_w_iv_i_2[3]\); - - \data_addr_w_iv_i_a2_2[3]\ : NAND2 - port map(A => N_89, B => \time_mem_addr_w_3_i_0[3]\, Y => - N_132); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \gen_fifo_ctrl_time.0.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ4 - port map(time_mem_ren_i_0_1 => \time_mem_ren_i_0[1]\, - time_wen(0) => time_wen(0), time_ren(0) => time_ren(0), - data_addr_w_0_iv_i_1(5) => \data_addr_w_0_iv_i_1[5]\, - Waddr_vect_RNILN58(0) => \Waddr_vect_RNILN58[0]\, - Waddr_vect_RNINV58(2) => \Waddr_vect_RNINV58[2]\, - Waddr_vect_RNI64MA(2) => \Waddr_vect_RNI64MA[2]\, - data_addr_w_iv_i_2_0 => \data_addr_w_iv_i_2[2]\, - data_addr_w_iv_i_2_2 => \data_addr_w_iv_i_2[4]\, - time_mem_wen_i_0(0) => \time_mem_wen_i_0[0]\, - data_addr_r_0_iv_i_1(5) => \data_addr_r_0_iv_i_1[5]\, - data_addr_r_0_iv_i_2(5) => \data_addr_r_0_iv_i_2[5]\, - Raddr_vect_RNI8J9L(2) => \Raddr_vect_RNI8J9L[2]\, - data_addr_r_iv_i_0(4) => \data_addr_r_iv_i_0[4]\, - data_addr_r_iv_i_0(3) => \data_addr_r_iv_i_0[3]\, - data_addr_r_iv_i_0(2) => \data_addr_r_iv_i_0[2]\, - data_addr_r_iv_i_0(1) => \data_addr_r_iv_i_0[1]\, - data_addr_r_iv_i_0(0) => \data_addr_r_iv_i_0[0]\, - data_addr_w_iv_i_1_0 => \data_addr_w_iv_i_1[0]\, - data_addr_w_iv_i_1_3 => \data_addr_w_iv_i_1[3]\, - data_addr_w_iv_i_1_1 => \data_addr_w_iv_i_1[1]\, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_77 => N_77, - sFull_RNI9VRD => sFull_RNI9VRD, N_140 => N_140, - sFull_RNIPQBB_0 => sFull_RNIPQBB_0, N_122 => N_122, N_124 - => N_124, sFull_RNI9VRD_0 => sFull_RNI9VRD_0, N_146 => - N_146, N_70 => N_70, sEmpty_RNI5EFO_0 => sEmpty_RNI5EFO_0, - N_33 => N_33, N_62 => N_62, N_155 => N_155, - sFull_RNI9VRD_1 => sFull_RNI9VRD_1, N_147 => N_147); - - \data_addr_w_iv_i_a2_2[1]\ : OR2A - port map(A => N_89, B => \time_mem_addr_w_3[1]\, Y => N_148); - - \gen_fifo_ctrl_time.2.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ6 - port map(Waddr_vect_RNI64MA(2) => \Waddr_vect_RNI64MA[2]\, - data_addr_w_1_iv_i_s_0_0(6) => - \data_addr_w_1_iv_i_s_0_0[6]\, time_wen(2) => time_wen(2), - data_addr_r_0_iv_i_1(5) => \data_addr_r_0_iv_i_1[5]\, - data_addr_r_1_iv_i_s_1(6) => \data_addr_r_1_iv_i_s_1[6]\, - time_mem_ren_i_0_1 => \time_mem_ren_i_0[3]\, - data_addr_r_iv_i_a2_0(4) => \data_addr_r_iv_i_a2_0[4]\, - data_addr_r_iv_i_1(4) => \data_addr_r_iv_i_1[4]\, - data_addr_r_iv_i_1(3) => \data_addr_r_iv_i_1[3]\, - data_addr_r_iv_i_1(2) => \data_addr_r_iv_i_1[2]\, - data_addr_r_iv_i_1(1) => \data_addr_r_iv_i_1[1]\, - data_addr_r_iv_i_1(0) => \data_addr_r_iv_i_1[0]\, - time_ren(2) => time_ren(2), time_ren_1z => time_ren_1z, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, sFull_RNI9VRD_0 - => sFull_RNI9VRD_0, N_147 => N_147, sFull_RNI9VRD_1 => - sFull_RNI9VRD_1, sFull_RNI9VRD => sFull_RNI9VRD, - un13_time_write => un13_time_write, N_163 => N_163, N_155 - => N_155, N_162 => N_162, sFull_RNIU5GK1 => - sFull_RNIU5GK1, N_29 => N_29, N_30_1 => N_30_1, N_72 => - N_72, N_56 => N_56, N_48 => N_48, N_35 => N_35, N_64 => - N_64); - - \data_addr_w_iv_i_a2_2_RNIV6PT[1]\ : AND2 - port map(A => \data_addr_w_iv_i_1[1]\, B => N_148, Y => - \data_addr_w_iv_i_2[1]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_11 is - - port( sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - data_f0_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(10 downto 0); - sample_f0_37 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_63 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_0 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_15 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f0_out_valid : out std_logic; - enable_f0 : in std_logic; - data_shaping_R0 : in std_logic; - data_shaping_R0_0 : in std_logic; - start_snapshot_f0 : in std_logic; - sample_f0_val_0 : in std_logic; - burst_f0 : in std_logic - ); - -end lpp_waveform_snapshot_160_11; - -architecture DEF_ARCH of lpp_waveform_snapshot_160_11 is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_data_out_valid_0_sqmuxa_1_1[31]\, - data_out_valid_0_sqmuxa_1, - \counter_points_snapshot_0_sqmuxa_1_0\, - \un1_data_out_valid_0_sqmuxa_1_0[31]\, - \data_out_valid_0_sqmuxa\, ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I310_Y_0_0, - \counter_points_snapshot[30]_net_1\, - ADD_32x32_fast_I250_Y_2, ADD_32x32_fast_I250_Y_1, N483, - N487, N467, N470, N479, ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I253_Y_0_0, I94_un1_Y, N485, - ADD_32x32_fast_I295_Y_0_0, - \un1_counter_points_snapshot[16]\, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I288_Y_0_0, - \un1_counter_points_snapshot[23]\, - ADD_32x32_fast_I251_Y_2, ADD_32x32_fast_I251_Y_1, N489, - N464, ADD_32x32_fast_I302_Y_0_0, - \un1_counter_points_snapshot[9]\, - ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, - ADD_32x32_fast_I294_Y_0_0, - \un1_counter_points_snapshot[17]\, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I309_Y_0_0, - \counter_points_snapshot[29]_net_1\, - ADD_32x32_fast_I300_Y_0_0, - \un1_counter_points_snapshot[11]\, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot[5]\, - ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I287_Y_0_0, - \un1_counter_points_snapshot[24]\, - ADD_32x32_fast_I291_Y_0_0, - \un1_counter_points_snapshot[20]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I301_Y_0_0, - \un1_counter_points_snapshot[10]\, - ADD_32x32_fast_I254_Y_0, N554, ADD_32x32_fast_I259_Y_0, - N636, N620, ADD_32x32_fast_I297_Y_0_0, - \counter_points_snapshot[17]_net_1\, - ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I252_Y_1, ADD_32x32_fast_I252_Y_0, N491, - ADD_32x32_fast_I289_Y_0_0, - \un1_counter_points_snapshot[22]\, - ADD_32x32_fast_I255_Y_0, N556, ADD_32x32_fast_I293_Y_0_0, - \un1_counter_points_snapshot[18]\, - ADD_32x32_fast_I256_Y_0, N558, ADD_32x32_fast_I284_Y_0_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I263_Y_0, N644, N628, - ADD_32x32_fast_I283_Y_0_0, - \un1_counter_points_snapshot[28]\, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot[26]\, - ADD_32x32_fast_I118_Y_0, ADD_32x32_fast_I110_Y_0, - ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I126_Y_1, - \un1_counter_points_snapshot[21]\, - data_out_valid_0_sqmuxa_1_1, un4_data_in_validlt30_27, - un4_data_in_validlt30_18, un4_data_in_validlt30_17, - un4_data_in_validlt30_23, un4_data_in_validlt30_26, - un4_data_in_validlt30_12, un4_data_in_validlt30_11, - un4_data_in_validlt30_22, un4_data_in_validlt30_25, - un4_data_in_validlt30_8, un4_data_in_validlt30_7, - un4_data_in_validlt30_20, un4_data_in_validlt30_2, - un4_data_in_validlt30_1, un4_data_in_validlt30_15, - un4_data_in_validlt30_14, - \counter_points_snapshot[27]_net_1\, - \counter_points_snapshot[26]_net_1\, - un4_data_in_validlt30_10, - \counter_points_snapshot[19]_net_1\, - \counter_points_snapshot[18]_net_1\, - un4_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un4_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[28]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[22]_net_1\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[20]_net_1\, - \counter_points_snapshot[21]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[14]_net_1\, - \counter_points_snapshot[15]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[13]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, - \un1_data_out_valid_0_sqmuxa_2[4]\, N533, N529, N754, - N634, N618, N650, un4_data_in_validlto30_i, N740, N774, - N764, N738, N771, N744, N752, - \un1_data_out_valid_0_sqmuxa_2[6]\, N652_i, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, N380, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_counter_points_snapshot[29]\, - \un1_data_out_valid_0_sqmuxa_2[5]\, N654, - \un1_data_out_valid_0_sqmuxa_2[8]\, N401, - \un1_data_out_valid_0_sqmuxa_2[10]\, N786, N750, N630, - N789, \un1_data_out_valid_0_sqmuxa_2[9]\, N756, N748, - N497, N766, N646, N746, N626, N783, N572, N419, I66_un1_Y, - N580, N407, N588, \un1_data_out_valid_0_sqmuxa_2[3]\, - N594, \un1_data_out_valid_0_sqmuxa_2[7]\, N762, N642, - N564, I60_un1_Y, N431, N758, N622, N638, N742, N777, - \sample_f0_wdata[32]\, \sample_f0_wdata[33]\, - \sample_f0_wdata[34]\, \sample_f0_wdata[35]\, - \sample_f0_wdata[19]\, \sample_f0_wdata[20]\, - \sample_f0_wdata[21]\, \sample_f0_wdata[22]\, - \sample_f0_wdata[23]\, \sample_f0_wdata[24]\, - \sample_f0_wdata[25]\, \sample_f0_wdata[26]\, - \sample_f0_wdata[27]\, \sample_f0_wdata[28]\, - \sample_f0_wdata[29]\, \sample_f0_wdata[30]\, - \sample_f0_wdata[31]\, \sample_f0_wdata[43]\, - \sample_f0_wdata[44]\, \sample_f0_wdata[45]\, - \sample_f0_wdata[46]\, \sample_f0_wdata[47]\, - \sample_f0_wdata[16]\, \sample_f0_wdata[17]\, - \sample_f0_wdata[18]\, \sample_f0_wdata[36]\, - \sample_f0_wdata[37]\, \sample_f0_wdata[38]\, - \sample_f0_wdata[39]\, \sample_f0_wdata[40]\, - \sample_f0_wdata[41]\, \sample_f0_wdata[42]\, - \counter_points_snapshot_10[4]\, N_90, - \counter_points_snapshot_2_sqmuxa\, - \counter_points_snapshot_10[23]\, - un1_counter_points_snapshot_0_sqmuxa_1_i, N461, - \counter_points_snapshot_3_sqmuxa\, - \un1_data_out_valid_0_sqmuxa_1[31]\, - counter_points_snapshot_0_sqmuxa_i, data_out_valid_19, - un1_enable_2, \counter_points_snapshot_10[30]\, - \counter_points_snapshot_0_sqmuxa_1\, - \counter_points_snapshot_10[31]\, - \counter_points_snapshot_10[22]\, - \counter_points_snapshot_10[24]\, - \counter_points_snapshot_10[28]\, N760, - \counter_points_snapshot_10[18]\, N590, N582, N_92, - \counter_points_snapshot_2_sqmuxa_2\, - \counter_points_snapshot_10[6]\, N507, N511, N578, N586, - I74_un1_Y, \un1_counter_points_snapshot[31]\, - \counter_points_snapshot_10[10]\, N_96, - \counter_points_snapshot_10[8]\, N_94, - \counter_points_snapshot_10[5]\, N_91, - \counter_points_snapshot_10[2]\, N_88, - \counter_points_snapshot_10[1]\, N_87, N562, - \counter_points_snapshot_10[25]\, N_95, - \counter_points_snapshot_10[9]\, - \counter_points_snapshot_10[27]\, - \counter_points_snapshot_10[26]\, - \counter_points_snapshot_10[17]\, - \counter_points_snapshot_10[14]\, - \counter_points_snapshot_10[15]\, - \counter_points_snapshot_10[11]\, N515, - \counter_points_snapshot_10[16]\, N768, N523, N531, N527, - \un1_data_out_valid_0_sqmuxa_2[0]\, N_86, - \counter_points_snapshot_10[0]\, - \counter_points_snapshot_10[19]\, - \counter_points_snapshot_10[7]\, N_93, - \counter_points_snapshot_10[3]\, N_89, - \counter_points_snapshot_10[20]\, N434, N780, - \counter_points_snapshot_10[12]\, - \counter_points_snapshot_10[29]\, - \counter_points_snapshot_10[21]\, - \counter_points_snapshot_10[13]\, N574, N566, N503, N495, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter_points_snapshot_RNIV49P[18]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - \counter_points_snapshot_RNIRF66[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un4_data_in_validlt30_1); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[13]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : AX1A - port map(A => N533, B => N529, C => - ADD_32x32_fast_I284_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - \data_out[110]\ : DFN1C0 - port map(D => \sample_f0_wdata[46]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(110)); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[10]\, B => - nb_snapshot_param(10), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_96); - - \counter_points_snapshot_RNO[27]\ : XA1C - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[27]\); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[28]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[28]_net_1\); - - \counter_points_snapshot_RNIVG9N[0]\ : NOR3C - port map(A => un4_data_in_validlt30_2, B => - un4_data_in_validlt30_1, C => un4_data_in_validlt30_15, Y - => un4_data_in_validlt30_23); - - \counter_points_snapshot_RNI37D9[24]\ : NOR2 - port map(A => \counter_points_snapshot[24]_net_1\, B => - \counter_points_snapshot[25]_net_1\, Y => - un4_data_in_validlt30_12); - - data_out_valid_0_sqmuxa : OR2B - port map(A => sample_f0_val_0, B => start_snapshot_f0, Y - => \data_out_valid_0_sqmuxa\); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762, B => ADD_32x32_fast_I299_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[19]\); - - \data_out_RNO[96]\ : MX2 - port map(A => sample_f0_15, B => sample_f0_47, S => - data_shaping_R0_0, Y => \sample_f0_wdata[32]\); - - \data_out[91]\ : DFN1C0 - port map(D => \sample_f0_wdata[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(91)); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f0_wdata_56, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1C - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : NOR3 - port map(A => N626, B => ADD_32x32_fast_I254_Y_0, C => N783, - Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : OR2 - port map(A => N586, B => N578, Y => N642); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f0_wdata_66, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => \sample_f0_wdata[40]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(104)); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => nb_snapshot_param(4), B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_90); - - \counter_points_snapshot_RNIRK8P[14]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[14]_net_1\, Y => - \un1_counter_points_snapshot[17]\); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[1]\, B => - nb_snapshot_param(1), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_87); - - \counter_points_snapshot_RNIHHQQ[3]\ : MX2 - port map(A => nb_snapshot_param(3), B => - \counter_points_snapshot[3]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[28]\); - - \data_out[102]\ : DFN1C0 - port map(D => \sample_f0_wdata[38]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I64_Y : AO1A - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_data_out_valid_0_sqmuxa_1[31]\, C => N419, Y => N507); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3B - port map(A => ADD_32x32_fast_I252_Y_1, B => N777, C => N622, - Y => N742); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_93, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[29]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1B - port map(A => N780, B => ADD_32x32_fast_I292_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[12]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : OR2 - port map(A => N650, B => N634, Y => N771); - - \data_out[93]\ : DFN1C0 - port map(D => \sample_f0_wdata[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(93)); - - \counter_points_snapshot_RNISO8P[15]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - \un1_counter_points_snapshot[16]\); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[4]_net_1\); - - counter_points_snapshot_2_sqmuxa : OR3B - port map(A => enable_f0, B => - \counter_points_snapshot_2_sqmuxa_2\, C => burst_f0, Y - => \counter_points_snapshot_2_sqmuxa\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f0_wdata_95, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => \sample_f0_wdata[41]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(105)); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[15]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f0_wdata_77, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR2 - port map(A => N495, B => N491, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2 - port map(A => N527, B => N523, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => \sample_f0_wdata[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(81)); - - \data_out_RNO[99]\ : MX2 - port map(A => sample_f0_12, B => sample_f0_44, S => - data_shaping_R0_0, Y => \sample_f0_wdata[35]\); - - \counter_points_snapshot_RNIB5QQ[0]\ : MX2 - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[30]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I310_Y_0_0); - - \data_out_RNO[104]\ : MX2 - port map(A => sample_f0_7, B => sample_f0_39, S => - data_shaping_R0, Y => \sample_f0_wdata[40]\); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : OR3 - port map(A => N487, B => N491, C => N558, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - NOR2 - port map(A => N771, B => I60_un1_Y, Y => N768); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f0_wdata_50, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(114)); - - \counter_points_snapshot_RNIR5RQ[8]\ : MX2C - port map(A => nb_snapshot_param(8), B => - \counter_points_snapshot[8]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[23]\); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : OR3 - port map(A => N507, B => N511, C => N578, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : OR2 - port map(A => N507, B => N503, Y => N566); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[27]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f0_wdata_79, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : OR2 - port map(A => N590, B => N380, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR2 - port map(A => ADD_32x32_fast_I110_Y_0, B => N497, Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f0_wdata_48, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(112)); - - \counter_points_snapshot_RNIP88P[21]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - \un1_counter_points_snapshot[10]\); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f0_wdata_60, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(124)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f0_wdata_70, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : OA1A - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_counter_points_snapshot[26]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N523); - - \counter_points_snapshot_RNO[28]\ : XA1C - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[28]\); - - \data_out[83]\ : DFN1C0 - port map(D => \sample_f0_wdata[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I250_Y_1, B => N483, C => N487, - Y => ADD_32x32_fast_I250_Y_2); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f0_wdata_58, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f0_wdata_51, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(115)); - - \counter_points_snapshot_RNID01S[10]\ : MX2C - port map(A => nb_snapshot_param(10), B => - \counter_points_snapshot[10]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[21]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : AOI1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : OA1 - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[5]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => I94_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[17]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f0_wdata_68, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(132)); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[30]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[30]_net_1\); - - \data_out[96]\ : DFN1C0 - port map(D => \sample_f0_wdata[32]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(96)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : NOR3 - port map(A => N628, B => ADD_32x32_fast_I255_Y_0, C => N786, - Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f0_wdata_61, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(125)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f0_wdata_71, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(135)); - - \data_out_RNO[87]\ : NOR2B - port map(A => sample_f0_56, B => data_shaping_R0_0, Y => - \sample_f0_wdata[23]\); - - \data_out_RNO[108]\ : MX2 - port map(A => sample_f0_3, B => sample_f0_35, S => - data_shaping_R0, Y => \sample_f0_wdata[44]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_G0N : NOR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[16]\, Y => I60_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : NOR2 - port map(A => ADD_32x32_fast_I253_Y_0_0, B => N752, Y => - N744); - - \counter_points_snapshot_RNID9QQ[1]\ : MX2C - port map(A => nb_snapshot_param(1), B => - \counter_points_snapshot[1]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[30]\); - - data_out_valid : DFN1C0 - port map(D => data_out_valid_19, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out_valid); - - \data_out_RNO[90]\ : NOR2B - port map(A => sample_f0_53, B => data_shaping_R0_0, Y => - \sample_f0_wdata[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : OR3 - port map(A => N507, B => N511, C => N562, Y => N626); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I29_G0N : OR3B - port map(A => \counter_points_snapshot[29]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1\, C => - data_out_valid_0_sqmuxa_1, Y => N467); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f0_wdata_7, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f0_wdata_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(65)); - - \counter_points_snapshot_RNIUS8P[26]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot[5]\); - - \counter_points_snapshot_RNIO88P[11]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[11]_net_1\, Y => - \un1_counter_points_snapshot[20]\); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[18]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : NOR3 - port map(A => N622, B => N638, C => N654, Y => N758); - - \data_out_RNO[98]\ : MX2 - port map(A => sample_f0_13, B => sample_f0_45, S => - data_shaping_R0_0, Y => \sample_f0_wdata[34]\); - - \data_out[86]\ : DFN1C0 - port map(D => \sample_f0_wdata[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[23]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I288_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : OR2 - port map(A => N562, B => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f0_wdata_86, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(150)); - - \counter_points_snapshot_RNIQC8P[22]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[22]_net_1\, Y => - \un1_counter_points_snapshot[9]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[17]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f0_wdata_84, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(148)); - - GND_i : GND - port map(Y => \GND\); - - \counter_points_snapshot_RNIPC8P[12]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - \counter_points_snapshot_RNIB7E9[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un4_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_G0N : NOR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[18]\, Y => N419); - - \counter_points_snapshot_RNIA0DC[6]\ : NOR3A - port map(A => un4_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un4_data_in_validlt30_17); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[8]_net_1\); - - counter_points_snapshot_2_sqmuxa_2 : NOR2A - port map(A => start_snapshot_f0, B => sample_f0_val_0, Y - => \counter_points_snapshot_2_sqmuxa_2\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : OR2 - port map(A => N574, B => N566, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR3 - port map(A => I74_un1_Y, B => N401, C => N523, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f0_wdata_9, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I283_Y_0_0); - - \data_out[92]\ : DFN1C0 - port map(D => \sample_f0_wdata[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f0_wdata_3, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => \sample_f0_wdata[43]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OR2 - port map(A => N644, B => N628, Y => ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_92, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[21]\, C => N786, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[29]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[29]_net_1\); - - \counter_points_snapshot_RNIDBS75_1[31]\ : OR2B - port map(A => data_out_valid_0_sqmuxa_1, B => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_data_out_valid_0_sqmuxa_1[31]\); - - \counter_points_snapshot_RNI28AJ4[31]\ : OR2 - port map(A => data_out_valid_0_sqmuxa_1_1, B => - un4_data_in_validlto30_i, Y => data_out_valid_0_sqmuxa_1); - - \data_out_RNO[94]\ : NOR2B - port map(A => sample_f0_49, B => data_shaping_R0_0, Y => - \sample_f0_wdata[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1B - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[25]\); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[20]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I302_Y_0_0); - - \counter_points_snapshot_RNIR6C9[20]\ : NOR2 - port map(A => \counter_points_snapshot[20]_net_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - un4_data_in_validlt30_10); - - \data_out_RNO[95]\ : NOR2B - port map(A => sample_f0_48, B => data_shaping_R0, Y => - \sample_f0_wdata[31]\); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[17]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : OR2 - port map(A => N590, B => N582, Y => N646); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : AOI1B - port map(A => \un1_counter_points_snapshot[30]\, B => - \un1_counter_points_snapshot[29]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I28_G0N : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[3]\, Y => N464); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : OR3A - port map(A => ADD_32x32_fast_I250_Y_2, B => N618, C => N771, - Y => N738); - - \data_out_RNO[93]\ : NOR2B - port map(A => sample_f0_50, B => data_shaping_R0_0, Y => - \sample_f0_wdata[29]\); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f0_wdata_90, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(154)); - - \counter_points_snapshot_RNITMC9[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un4_data_in_validlt30_6); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - OR2A - port map(A => N764, B => N497, Y => N760); - - \data_out[82]\ : DFN1C0 - port map(D => \sample_f0_wdata[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f0_wdata_53, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1C - port map(A => N760, B => ADD_32x32_fast_I300_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : OR3 - port map(A => N483, B => N487, C => N554, Y => - ADD_32x32_fast_I254_Y_0); - - \counter_points_snapshot_RNIT9RQ[9]\ : MX2C - port map(A => nb_snapshot_param(9), B => - \counter_points_snapshot[9]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[22]\); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f0_wdata_12, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f0_wdata_88, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(152)); - - \counter_points_snapshot_RNIVMC9[22]\ : NOR2 - port map(A => \counter_points_snapshot[22]_net_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - un4_data_in_validlt30_11); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f0_wdata_85, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(149)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f0_wdata_63, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : NOR2 - port map(A => N654, B => N638, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : OR2B - port map(A => N652_i, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : NOR2 - port map(A => N588, B => N533, Y => N652_i); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f0_wdata_73, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I30_G0N : OR3B - port map(A => \counter_points_snapshot[30]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - data_out_valid_0_sqmuxa_1, Y => N470); - - \data_out_RNO[81]\ : NOR2B - port map(A => sample_f0_62, B => data_shaping_R0, Y => - \sample_f0_wdata[17]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : OR2 - port map(A => N531, B => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f0_wdata_91, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(155)); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_91, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1B - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[17]\); - - \counter_points_snapshot_RNI099P[19]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - data_out_valid_RNO_0 : AO1B - port map(A => data_out_valid_0_sqmuxa_1, B => - \data_out_valid_0_sqmuxa\, C => enable_f0, Y => - un1_enable_2); - - \data_out[90]\ : DFN1C0 - port map(D => \sample_f0_wdata[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(90)); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR3B - port map(A => N620, B => ADD_32x32_fast_I251_Y_2, C => N774, - Y => N740); - - \counter_points_snapshot_RNO[14]\ : XA1C - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[14]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR3 - port map(A => I74_un1_Y, B => N401, C => N515, Y => N578); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[29]\, C => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - \data_out_RNO[92]\ : NOR2B - port map(A => sample_f0_51, B => data_shaping_R0_0, Y => - \sample_f0_wdata[28]\); - - \counter_points_snapshot_RNIO48P[20]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[20]_net_1\, Y => - \un1_counter_points_snapshot[11]\); - - \data_out[99]\ : DFN1C0 - port map(D => \sample_f0_wdata[35]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(99)); - - \data_out_RNO[100]\ : MX2 - port map(A => sample_f0_11, B => sample_f0_43, S => - data_shaping_R0, Y => \sample_f0_wdata[36]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : NOR3 - port map(A => N634, B => N618, C => N650, Y => N754); - - \counter_points_snapshot_RNISK8P[24]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - \data_out[106]\ : DFN1C0 - port map(D => \sample_f0_wdata[42]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1C - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[21]\); - - \counter_points_snapshot_RNITO8P[25]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - \counter_points_snapshot_RNITNQ14[6]\ : NOR3C - port map(A => un4_data_in_validlt30_26, B => - un4_data_in_validlt30_25, C => un4_data_in_validlt30_27, - Y => un4_data_in_validlto30_i); - - \data_out_RNO[103]\ : MX2 - port map(A => sample_f0_8, B => sample_f0_40, S => - data_shaping_R0, Y => \sample_f0_wdata[39]\); - - \counter_points_snapshot_RNIVEFM1[6]\ : NOR3C - port map(A => un4_data_in_validlt30_18, B => - un4_data_in_validlt30_17, C => un4_data_in_validlt30_23, - Y => un4_data_in_validlt30_27); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : OR2 - port map(A => N515, B => N511, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => \sample_f0_wdata[34]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(98)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y : NOR3 - port map(A => I60_un1_Y, B => N431, C => - ADD_32x32_fast_I118_Y_0, Y => N564); - - \counter_points_snapshot_RNIFDQQ[2]\ : MX2C - port map(A => nb_snapshot_param(2), B => - \counter_points_snapshot[2]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[29]\); - - \data_out[80]\ : DFN1C0 - port map(D => \sample_f0_wdata[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f0_wdata_8, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : NOR3 - port map(A => N630, B => ADD_32x32_fast_I256_Y_0, C => N789, - Y => N750); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : AX1B - port map(A => N401, B => N650, C => - ADD_32x32_fast_I288_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - \data_out_RNO[107]\ : MX2 - port map(A => sample_f0_4, B => sample_f0_36, S => - data_shaping_R0, Y => \sample_f0_wdata[43]\); - - \data_out[89]\ : DFN1C0 - port map(D => \sample_f0_wdata[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(89)); - - \counter_points_snapshot_RNI059P[28]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : NOR2 - port map(A => ADD_32x32_fast_I263_Y_0, B => N533, Y => N764); - - \counter_points_snapshot_RNIQG8P[13]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - \un1_counter_points_snapshot[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I289_Y_0_0, B => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out_RNO[101]\ : MX2 - port map(A => sample_f0_10, B => sample_f0_42, S => - data_shaping_R0, Y => \sample_f0_wdata[37]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f0_wdata_52, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[19]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[2]\, B => - nb_snapshot_param(2), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_88); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : OR2 - port map(A => N594, B => N586, Y => N650); - - \counter_points_snapshot_RNITS8P[16]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[26]\, C => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1C - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[18]\); - - \data_out[88]\ : DFN1C0 - port map(D => \sample_f0_wdata[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XOR2 - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[31]\, Y => - \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f0_wdata_62, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => \sample_f0_wdata[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f0_wdata_76, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f0_wdata_72, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(136)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I27_G0N : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[4]\, Y => N461); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[18]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I293_Y_0_0); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[22]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[22]_net_1\); - - \data_out_RNO[86]\ : NOR2B - port map(A => sample_f0_57, B => data_shaping_R0_0, Y => - \sample_f0_wdata[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2 - port map(A => N531, B => N380, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I304_Y_0_0); - - data_out_valid_RNO_1 : NOR2B - port map(A => enable_f0, B => burst_f0, Y => - counter_points_snapshot_0_sqmuxa_i); - - \data_out[101]\ : DFN1C0 - port map(D => \sample_f0_wdata[37]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(101)); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f0_wdata_93, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_90, Y => - \counter_points_snapshot_10[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y_0 : OA1A - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot[10]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I110_Y_0); - - \counter_points_snapshot_RNO[30]\ : XA1B - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[30]\); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : - AO1C - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_data_out_valid_0_sqmuxa_1[31]\, C => N434, Y => N497); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR2A - port map(A => N564, B => N572, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AO1B - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_counter_points_snapshot[23]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I134_Y_0); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f0_wdata_6, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[5]\, B => - nb_snapshot_param(5), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_91); - - \data_out[84]\ : DFN1C0 - port map(D => \sample_f0_wdata[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => \sample_f0_wdata[39]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I7_G0N : NOR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[24]\, Y => N401); - - \counter_points_snapshot_RNIRG8P[23]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : OA1 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[27]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I8_G0N : NOR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[23]\, Y => I74_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I289_Y_0_0); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f0_wdata_15, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f0_wdata_80, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(144)); - - \data_out_RNO[89]\ : NOR2B - port map(A => sample_f0_54, B => data_shaping_R0_0, Y => - \sample_f0_wdata[25]\); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_94, Y => - \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => \sample_f0_wdata[47]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : NOR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[31]\, Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f0_wdata_78, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f0_wdata_14, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[23]\); - - \counter_points_snapshot_RNIDBS75[31]\ : OR2B - port map(A => data_out_valid_0_sqmuxa_1, B => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_data_out_valid_0_sqmuxa_1_0[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : NOR2 - port map(A => N580, B => N572, Y => N636); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => nb_snapshot_param(3), B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_89); - - \counter_points_snapshot_RNI5HSA[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[30]_net_1\, Y => - un4_data_in_validlt30_15); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[26]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : NOR3A - port map(A => ADD_32x32_fast_I252_Y_0, B => N487, C => N491, - Y => ADD_32x32_fast_I252_Y_1); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f0_wdata_57, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : AO1A - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_data_out_valid_0_sqmuxa_1[31]\, C => I60_un1_Y, Y - => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_86, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f0_wdata_67, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f0_wdata_49, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(113)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f0_wdata_81, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(145)); - - \counter_points_snapshot_RNI5ND9[16]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un4_data_in_validlt30_8); - - \counter_points_snapshot_RNIIURI[26]\ : NOR3A - port map(A => un4_data_in_validlt30_14, B => - \counter_points_snapshot[27]_net_1\, C => - \counter_points_snapshot[26]_net_1\, Y => - un4_data_in_validlt30_22); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f0_wdata_2, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[1]_net_1\); - - \counter_points_snapshot_RNO[31]\ : XA1C - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[31]\); - - \data_out_RNO[109]\ : MX2 - port map(A => sample_f0_2, B => sample_f0_34, S => - data_shaping_R0, Y => \sample_f0_wdata[45]\); - - \counter_points_snapshot_RNO_0[0]\ : MX2C - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_86); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N771, B => ADD_32x32_fast_I295_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[15]\); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f0_wdata_59, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(123)); - - \counter_points_snapshot_RNIKSL51[22]\ : NOR3C - port map(A => un4_data_in_validlt30_12, B => - un4_data_in_validlt30_11, C => un4_data_in_validlt30_22, - Y => un4_data_in_validlt30_26); - - GND_i_0 : GND - port map(Y => GND_0); - - counter_points_snapshot_3_sqmuxa : OR2 - port map(A => start_snapshot_f0, B => burst_f0, Y => - \counter_points_snapshot_3_sqmuxa\); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f0_wdata_69, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(133)); - - \counter_points_snapshot_RNIACL51[14]\ : NOR3C - port map(A => un4_data_in_validlt30_8, B => - un4_data_in_validlt30_7, C => un4_data_in_validlt30_20, Y - => un4_data_in_validlt30_25); - - \counter_points_snapshot_RNO[29]\ : XA1B - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[29]\); - - \counter_points_snapshot_RNIVF66[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un4_data_in_validlt30_2); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[31]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : OR2B - port map(A => N464, B => N461, Y => N479); - - \data_out_RNO[97]\ : MX2 - port map(A => sample_f0_14, B => sample_f0_46, S => - data_shaping_R0_0, Y => \sample_f0_wdata[33]\); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f0_wdata_10, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(74)); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_96, Y => - \counter_points_snapshot_10[10]\); - - \data_out[108]\ : DFN1C0 - port map(D => \sample_f0_wdata[44]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[6]\, B => - nb_snapshot_param(6), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_92); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f0_wdata_92, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(156)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_Y : OR2 - port map(A => N644, B => N533, Y => N786); - - \data_out_RNO[106]\ : MX2 - port map(A => sample_f0_5, B => sample_f0_37, S => - data_shaping_R0, Y => \sample_f0_wdata[42]\); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[8]\, B => - nb_snapshot_param(8), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_94); - - \data_out_RNO[80]\ : NOR2B - port map(A => sample_f0_63, B => data_shaping_R0, Y => - \sample_f0_wdata[16]\); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_87, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : OA1A - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[5]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - OR2 - port map(A => N756, B => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[22]\); - - \data_out_RNO[88]\ : NOR2B - port map(A => sample_f0_55, B => data_shaping_R0_0, Y => - \sample_f0_wdata[24]\); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[12]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[24]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[24]_net_1\); - - \data_out[95]\ : DFN1C0 - port map(D => \sample_f0_wdata[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(95)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_0 : NOR2 - port map(A => N479, B => N483, Y => ADD_32x32_fast_I252_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR3A - port map(A => ADD_32x32_fast_I126_Y_1, B => N419, C => - I66_un1_Y, Y => N572); - - \data_out_RNO[110]\ : MX2 - port map(A => sample_f0_1, B => sample_f0_33, S => - data_shaping_R0, Y => \sample_f0_wdata[46]\); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => nb_snapshot_param(9), B => - \un1_data_out_valid_0_sqmuxa_2[9]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_95); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : AO1C - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_counter_points_snapshot[21]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I126_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I116_Y : OR3A - port map(A => N434, B => N431, C => N503, Y => N562); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_89, Y => - \counter_points_snapshot_10[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : OAI1 - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[26]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f0_wdata_54, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(118)); - - counter_points_snapshot_0_sqmuxa_1_0 : OR2 - port map(A => \data_out_valid_0_sqmuxa\, B => burst_f0, Y - => \counter_points_snapshot_0_sqmuxa_1_0\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR2 - port map(A => N646, B => N380, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : NOR3B - port map(A => N467, B => N464, C => I94_un1_Y, Y => - ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2 - port map(A => N642, B => N594, Y => N783); - - \counter_points_snapshot_RNIDBS75_0[31]\ : OR2B - port map(A => data_out_valid_0_sqmuxa_1, B => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_data_out_valid_0_sqmuxa_1_1[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I287_Y_0_0, B => N650, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[25]\, C => N652_i, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - \counter_points_snapshot_RNIV09P[27]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - AOI1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[9]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => N489); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f0_wdata_64, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(128)); - - \counter_points_snapshot_RNO[11]\ : XA1B - port map(A => N783, B => ADD_32x32_fast_I291_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => \sample_f0_wdata[33]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f0_wdata_74, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(138)); - - \data_out_RNO[84]\ : NOR2B - port map(A => sample_f0_59, B => data_shaping_R0_0, Y => - \sample_f0_wdata[20]\); - - \data_out[85]\ : DFN1C0 - port map(D => \sample_f0_wdata[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[3]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I18_G0N : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[13]\, Y => N434); - - \data_out_RNO[85]\ : NOR2B - port map(A => sample_f0_58, B => data_shaping_R0_0, Y => - \sample_f0_wdata[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => \sample_f0_wdata[45]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(109)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y_0 : NOR2B - port map(A => N636, B => N620, Y => ADD_32x32_fast_I259_Y_0); - - \counter_points_snapshot_RNI4EQI[18]\ : NOR3A - port map(A => un4_data_in_validlt30_10, B => - \counter_points_snapshot[19]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un4_data_in_validlt30_20); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : AO1 - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[20]\, C => I66_un1_Y, Y => - N511); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I192_Y : OR2 - port map(A => N588, B => N580, Y => N644); - - \data_out_RNO[111]\ : MX2 - port map(A => sample_f0_0, B => sample_f0_32, S => - data_shaping_R0, Y => \sample_f0_wdata[47]\); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[23]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[21]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[16]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : OR3 - port map(A => N485, B => N489, C => N556, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f0_wdata_83, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(147)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f0_wdata_87, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(151)); - - \data_out_RNO[83]\ : NOR2B - port map(A => sample_f0_60, B => data_shaping_R0_0, Y => - \sample_f0_wdata[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => \sample_f0_wdata[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(87)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f0_wdata_89, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(153)); - - \counter_points_snapshot_RNIP1RQ[7]\ : MX2 - port map(A => nb_snapshot_param(7), B => - \counter_points_snapshot[7]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I283_Y_0_0, B => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - \counter_points_snapshot_RNI17D9[14]\ : NOR2 - port map(A => \counter_points_snapshot[14]_net_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - un4_data_in_validlt30_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR2B - port map(A => ADD_32x32_fast_I259_Y_0, B => N652_i, Y => - N756); - - counter_points_snapshot_0_sqmuxa_1 : OR2 - port map(A => \data_out_valid_0_sqmuxa\, B => burst_f0, Y - => \counter_points_snapshot_0_sqmuxa_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AO1C - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[29]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : OR2B - port map(A => ADD_32x32_fast_I142_Y_0, B => N529, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I307_Y_0_0); - - \data_out_RNO[91]\ : NOR2B - port map(A => sample_f0_52, B => data_shaping_R0_0, Y => - \sample_f0_wdata[27]\); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f0_wdata_55, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : NOR3B - port map(A => N467, B => N470, C => N479, Y => - ADD_32x32_fast_I250_Y_1); - - \data_out_RNO[102]\ : MX2 - port map(A => sample_f0_9, B => sample_f0_41, S => - data_shaping_R0, Y => \sample_f0_wdata[38]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AO1A - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_data_out_valid_0_sqmuxa_1[31]\, C => N407, Y => N515); - - \counter_points_snapshot_RNILPQQ[5]\ : MX2 - port map(A => nb_snapshot_param(5), B => - \counter_points_snapshot[5]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[26]\); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => nb_snapshot_param(7), B => - \un1_data_out_valid_0_sqmuxa_2[7]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_93); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_95, Y => - \counter_points_snapshot_10[9]\); - - \counter_points_snapshot_RNI5GFH[31]\ : OR3A - port map(A => sample_f0_val_0, B => start_snapshot_f0, C - => \counter_points_snapshot[31]_net_1\, Y => - data_out_valid_0_sqmuxa_1_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I291_Y_0_0); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f0_wdata_5, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f0_wdata_65, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I112_Y : OR3A - port map(A => N434, B => N431, C => N495, Y => N558); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I251_Y_1, B => N485, C => N489, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f0_wdata_75, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[25]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[25]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I48_Y : OA1A - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_counter_points_snapshot[10]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => N491); - - \data_out_RNO[82]\ : NOR2B - port map(A => sample_f0_61, B => data_shaping_R0, Y => - \sample_f0_wdata[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : OR3A - port map(A => ADD_32x32_fast_I134_Y_0, B => N401, C => N407, - Y => N580); - - \counter_points_snapshot_RNIMTOI[10]\ : NOR3A - port map(A => un4_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un4_data_in_validlt30_18); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - AO1 - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[20]\, C => N783, Y => N780); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : AO1A - port map(A => \un1_counter_points_snapshot[30]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, C => N380, Y => - N533); - - \counter_points_snapshot_RNIJLQQ[4]\ : MX2 - port map(A => nb_snapshot_param(4), B => - \counter_points_snapshot[4]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[27]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : AOI1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[6]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N485); - - \counter_points_snapshot_RNI7G66[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un4_data_in_validlt30_4); - - un1_counter_points_snapshot_0_sqmuxa_1 : AO1B - port map(A => \counter_points_snapshot_3_sqmuxa\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => enable_f0, Y - => un1_counter_points_snapshot_0_sqmuxa_1_i); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f0_wdata_11, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(75)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I284_Y_0_0); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f0_wdata_4, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(68)); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[14]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I12_G0N : NOR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[19]\, Y => I66_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : AOI1B - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_counter_points_snapshot[11]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : NOR2A - port map(A => N564, B => N556, Y => N620); - - \counter_points_snapshot_RNINTQQ[6]\ : MX2C - port map(A => nb_snapshot_param(6), B => - \counter_points_snapshot[6]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[25]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : NOR3 - port map(A => N646, B => N380, C => N630, Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768, B => ADD_32x32_fast_I296_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[16]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : OR2 - port map(A => N566, B => N558, Y => N622); - - data_out_valid_RNO : MX2A - port map(A => un1_enable_2, B => sample_f0_val_0, S => - counter_points_snapshot_0_sqmuxa_i, Y => - data_out_valid_19); - - \data_out[100]\ : DFN1C0 - port map(D => \sample_f0_wdata[36]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I9_G0N : NOR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[22]\, Y => N407); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : NOR3 - port map(A => N642, B => N594, C => N626, Y => N762); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : OR2 - port map(A => I94_un1_Y, B => N485, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f0_wdata_13, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f0_wdata_82, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_88, Y => - \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : OR2 - port map(A => N582, B => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1C - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[13]\); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f0_wdata_94, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(158)); - - \data_out_RNO[105]\ : MX2 - port map(A => sample_f0_6, B => sample_f0_38, S => - data_shaping_R0, Y => \sample_f0_wdata[41]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I17_G0N : NOR3B - port map(A => \counter_points_snapshot[17]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1\, C => - data_out_valid_0_sqmuxa_1, Y => N431); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f0_wdata_0, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I287_Y_0_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 is - - port( sample_f2_wdata : in std_logic_vector(95 downto 0); - data_f2_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f2_out_valid : out std_logic; - I_13_20 : in std_logic; - I_9_20 : in std_logic; - I_5_20 : in std_logic; - I_38_4 : in std_logic; - I_31_5 : in std_logic; - N_4 : in std_logic; - I_45_4 : in std_logic; - I_56_4 : in std_logic; - I_52_4 : in std_logic; - I_24_4 : in std_logic; - I_20_12 : in std_logic; - enable_f2 : in std_logic; - burst_f2 : in std_logic; - start_snapshot_f2 : in std_logic; - sample_f2_val : in std_logic - ); - -end lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1; - -architecture DEF_ARCH of - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal counter_points_snapshot_0_sqmuxa_1_0, N_47_1, - un1_data_in_valid, - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, N_47_0, - ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I250_Y_3, ADD_32x32_fast_I250_Y_1, N618, - N546, I32_un1_Y, N470, N479, ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, - ADD_32x32_fast_I295_Y_0_0, - \counter_points_snapshot[15]_net_1\, - ADD_32x32_fast_I310_Y_0_0, - \counter_points_snapshot[30]_net_1\, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I253_Y_0_0, N461, N458, N485, - ADD_32x32_fast_I307_Y_0_0, - \counter_points_snapshot[27]_net_1\, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I309_Y_0_0, - \counter_points_snapshot[29]_net_1\, - ADD_32x32_fast_I300_Y_0_0, - \counter_points_snapshot[20]_net_1\, - ADD_32x32_fast_I287_Y_0_0, - \un1_counter_points_snapshot[24]\, - ADD_32x32_fast_I251_Y_2, ADD_32x32_fast_I251_Y_1, N489, - ADD_32x32_fast_I251_Y_0, ADD_32x32_fast_I305_Y_0_0, - \counter_points_snapshot[25]_net_1\, - ADD_32x32_fast_I302_Y_0_0, - \counter_points_snapshot[22]_net_1\, - ADD_32x32_fast_I294_Y_0_0, - \un1_counter_points_snapshot[17]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I306_Y_0_0, - \counter_points_snapshot[26]_net_1\, - ADD_32x32_fast_I254_Y_0, N554, ADD_32x32_fast_I301_Y_0_0, - \counter_points_snapshot[21]_net_1\, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I252_Y_1, N483, N550, - ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I293_Y_0_0, - \counter_points_snapshot[13]_net_1\, - ADD_32x32_fast_I256_Y_0, N495, N499, - ADD_32x32_fast_I255_Y_0, N556, ADD_32x32_fast_I284_Y_0_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I263_Y_0, N580, N588, N533, - ADD_32x32_fast_I283_Y_0_0, - \un1_counter_points_snapshot[28]\, - ADD_32x32_fast_I126_Y_1, - \un1_counter_points_snapshot[20]\, N419, - ADD_32x32_fast_I126_Y_0, - \un1_counter_points_snapshot[21]\, - ADD_32x32_fast_I134_Y_1, - \un1_counter_points_snapshot[22]\, N401, - ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[25]\, N404, - ADD_32x32_fast_I118_Y_1, N425, ADD_32x32_fast_I118_Y_0, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot_i[26]\, - \counter_points_snapshot_10_12_i_o2_0\, - un1_data_in_validlt30_28, un1_data_in_validlt30_20, - un1_data_in_validlt30_19, un1_data_in_validlt30_26, - un1_data_in_validlt30_27, un1_data_in_validlt30_16, - un1_data_in_validlt30_15, un1_data_in_validlt30_24, - un1_data_in_validlt30_12, un1_data_in_validlt30_11, - un1_data_in_validlt30_22, un1_data_in_validlt30_4, - un1_data_in_validlt30_3, un1_data_in_validlt30_18, - un1_data_in_validlt30_14, un1_data_in_validlt30_10, - \counter_points_snapshot[19]_net_1\, - \counter_points_snapshot[18]_net_1\, - un1_data_in_validlt30_8, - \counter_points_snapshot[14]_net_1\, - un1_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un1_data_in_validlt30_2, - \counter_points_snapshot[3]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[28]_net_1\, - \counter_points_snapshot_i_0[24]\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, N738, N771, N742, - N622, N777, \un1_data_out_valid_0_sqmuxa_2[10]\, N786, - \un1_data_out_valid_0_sqmuxa_2[9]\, N789_i, - \un1_data_out_valid_0_sqmuxa_2[5]\, N654_i, - \un1_data_out_valid_0_sqmuxa_2[4]\, N529, - \un1_data_out_valid_0_sqmuxa_2[8]\, - \un1_counter_points_snapshot[23]\, N648, - \un1_data_out_valid_0_sqmuxa_2[11]\, N783, N758, N638, - N740, N774, N620, N744, N752, N750, N630, N754, N634, - N650_i, N746, N626, N762_i, N594, N642, N764, N628, N748, - N766, N380, N646, N443, N440, N497, N_49, N_57, N_52, - N_60, counter_points_snapshot_0_sqmuxa_1, N_47, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_counter_points_snapshot_i[29]\, - \un1_data_out_valid_0_sqmuxa_2[6]\, N652, N756, N636, - N572, \un1_data_out_valid_0_sqmuxa_2[3]\, - \un1_data_out_valid_0_sqmuxa_2[7]\, N578, N515, N586, - N523, N527, N503, N570, N590, N531, N566, N582, N574, - N383, N768, N_20, counter_points_snapshot_2_sqmuxa_i, - N_21, N_25, N_26, \counter_points_snapshot_10[4]\, - counter_points_snapshot_2_sqmuxa_1, - \counter_points_snapshot_10[5]\, - \counter_points_snapshot_10[9]\, - \counter_points_snapshot_10[10]\, N_9, N_13, N_15, N_41, - N_45, \un1_counter_points_snapshot[31]\, - \counter_points_snapshot_10[0]\, N_16, - \un1_data_out_valid_0_sqmuxa_2[0]\, - \counter_points_snapshot_10[8]\, N_24, N_7, N780, - \counter_points_snapshot_10[11]\, N_27, N487, N_43, - \counter_points_snapshot_10[6]\, N_22, N422, N455, N_39, - N_37, N_33, N_29, \counter_points_snapshot_RNO[19]_net_1\, - N_35, \counter_points_snapshot_RNO[18]_net_1\, - \counter_points_snapshot_RNO[17]_net_1\, - \counter_points_snapshot_RNO[22]_net_1\, N446, N_11, N760, - \counter_points_snapshot_RNO[20]_net_1\, - \counter_points_snapshot_RNO[21]_net_1\, N_17, - \counter_points_snapshot_10[1]\, N386, - \counter_points_snapshot_10[2]\, N_18, N_31, N511, N_19, - \counter_points_snapshot_10[3]\, N_23, - \counter_points_snapshot_10[7]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - - \counter_points_snapshot_RNI58FP[1]\ : MX2 - port map(A => I_5_20, B => - \counter_points_snapshot[1]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[30]\); - - \counter_points_snapshot_RNIUTOI[10]\ : NOR3A - port map(A => un1_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un1_data_in_validlt30_18); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => N_9, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : AX1 - port map(A => N533, B => N529, C => - ADD_32x32_fast_I284_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I26_G0N : NOR3B - port map(A => \counter_points_snapshot[26]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N458); - - \data_out[110]\ : DFN1C0 - port map(D => sample_f2_wdata(46), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(110)); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => I_56_4, B => - \un1_data_out_valid_0_sqmuxa_2[10]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_26); - - \counter_points_snapshot_RNO[27]\ : XA1B - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - N_52, Y => N_37); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => N_39, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[28]_net_1\); - - \counter_points_snapshot_RNO[19]\ : XA1C - port map(A => N762_i, B => ADD_32x32_fast_I299_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[19]_net_1\); - - \counter_points_snapshot_RNI1NC9[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un1_data_in_validlt30_6); - - \data_out[91]\ : DFN1C0 - port map(D => sample_f2_wdata(27), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(91)); - - \counter_points_snapshot_RNIB9461[5]\ : MX2C - port map(A => I_24_4, B => - \counter_points_snapshot[5]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot_i[26]\); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f2_wdata(56), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(120)); - - \counter_points_snapshot_RNO[24]\ : XO1 - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - N_52, Y => N_31); - - \counter_points_snapshot_RNIU9BB2[14]\ : NOR3C - port map(A => un1_data_in_validlt30_20, B => - un1_data_in_validlt30_19, C => un1_data_in_validlt30_26, - Y => un1_data_in_validlt30_28); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : NOR3 - port map(A => N626, B => ADD_32x32_fast_I254_Y_0, C => N783, - Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : OR2 - port map(A => N586, B => N578, Y => N642); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f2_wdata(66), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => sample_f2_wdata(40), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : NOR3 - port map(A => N443, B => N446, C => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => I_20_12, B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_20); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => I_5_20, B => - \un1_data_out_valid_0_sqmuxa_2[1]\, S => N_60, Y => N_17); - - \counter_points_snapshot_RNIJDPK[19]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - \data_out[102]\ : DFN1C0 - port map(D => sample_f2_wdata(38), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3B - port map(A => N622, B => ADD_32x32_fast_I252_Y_1, C => N777, - Y => N742); - - \counter_points_snapshot_RNO[7]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_23, - Y => \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[29]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1C - port map(A => N780, B => ADD_32x32_fast_I292_Y_0_0, C => - N_52, Y => N_7); - - \counter_points_snapshot_RNIKTDU4_0[31]\ : AO1C - port map(A => start_snapshot_f2, B => un1_data_in_valid, C - => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, Y => - N_47_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : NOR2B - port map(A => N650_i, B => N634, Y => N771); - - \data_out[93]\ : DFN1C0 - port map(D => sample_f2_wdata(29), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(93)); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[4]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[21]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f2_wdata(95), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => sample_f2_wdata(41), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(105)); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f2_wdata(77), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR3 - port map(A => N443, B => N446, C => N495, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2A - port map(A => N523, B => N527, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => sample_f2_wdata(17), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(81)); - - counter_points_snapshot_10_12_i_o2 : OR2B - port map(A => \counter_points_snapshot_10_12_i_o2_0\, B => - N_60, Y => N_52); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[30]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I310_Y_0_0); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : NOR3A - port map(A => N550, B => N495, C => N499, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - OR2A - port map(A => N771, B => N425, Y => N768); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f2_wdata(50), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : NOR2 - port map(A => N578, B => N570, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : OR3 - port map(A => N419, B => N422, C => N503, Y => N566); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => N_37, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f2_wdata(79), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : NOR2B - port map(A => N590, B => N380, Y => N654_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3 - port map(A => N443, B => N440, C => N497, Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f2_wdata(48), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f2_wdata(60), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(124)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f2_wdata(70), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(134)); - - \counter_points_snapshot_RNIMGPV[3]\ : MX2 - port map(A => I_13_20, B => - \counter_points_snapshot[3]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[28]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : AO1 - port map(A => \un1_counter_points_snapshot_i[26]\, B => - \un1_counter_points_snapshot[25]\, C => N_47, Y => N523); - - \counter_points_snapshot_RNO[28]\ : XA1B - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - N_52, Y => N_39); - - \data_out[83]\ : DFN1C0 - port map(D => sample_f2_wdata(19), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(83)); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f2_wdata(58), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f2_wdata(51), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(115)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : OA1C - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => N_47, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AO1 - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[17]\, C => N_47_1, Y => - ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f2_wdata(68), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(132)); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => N_43, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[30]_net_1\); - - \data_out[96]\ : DFN1C0 - port map(D => sample_f2_wdata(32), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(96)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : NOR3 - port map(A => N628, B => ADD_32x32_fast_I255_Y_0, C => N786, - Y => N748); - - \counter_points_snapshot_RNI20DC[2]\ : NOR3A - port map(A => un1_data_in_validlt30_2, B => - \counter_points_snapshot[3]_net_1\, C => - \counter_points_snapshot[2]_net_1\, Y => - un1_data_in_validlt30_16); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - N_47_0, Y => ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f2_wdata(61), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(125)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f2_wdata(71), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(135)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_G0N : NOR3B - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N425); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : NOR2 - port map(A => ADD_32x32_fast_I253_Y_0_0, B => N752, Y => - N744); - - \counter_points_snapshot_RNICVG64[31]\ : AO1 - port map(A => un1_data_in_validlt30_28, B => - un1_data_in_validlt30_27, C => - \counter_points_snapshot[31]_net_1\, Y => - un1_data_in_valid); - - data_out_valid : DFN1C0 - port map(D => N_49, CLK => HCLK_c, CLR => HRESETn_c, Q => - data_f2_out_valid); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : OR3 - port map(A => N499, B => N503, C => N570, Y => N626); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I29_G0N : OR3B - port map(A => \counter_points_snapshot[29]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - I32_un1_Y); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f2_wdata(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f2_wdata(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[18]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : OR3C - port map(A => N638, B => N622, C => N654_i, Y => N758); - - \data_out[86]\ : DFN1C0 - port map(D => sample_f2_wdata(22), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : NOR3 - port map(A => N499, B => N503, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f2_wdata(86), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(150)); - - \counter_points_snapshot_RNINR991[6]\ : MX2C - port map(A => I_31_5, B => - \counter_points_snapshot[6]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[25]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_0, Y => ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - N_47_0, Y => ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f2_wdata(84), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(148)); - - GND_i : GND - port map(Y => \GND\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_G0N : NOR3B - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N419); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[8]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : OR2 - port map(A => N574, B => N566, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR3B - port map(A => N401, B => N523, C => N404, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f2_wdata(9), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[28]\, B => - N_47_0, Y => ADD_32x32_fast_I283_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_3 : NOR3B - port map(A => ADD_32x32_fast_I250_Y_1, B => N618, C => N546, - Y => ADD_32x32_fast_I250_Y_3); - - \data_out[92]\ : DFN1C0 - port map(D => sample_f2_wdata(28), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f2_wdata(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => sample_f2_wdata(43), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I14_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - N_47_1, Y => N422); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OR3 - port map(A => N580, B => N588, C => N533, Y => - ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_22, - Y => \counter_points_snapshot_10[6]\); - - \counter_points_snapshot_RNIQURI[26]\ : NOR3A - port map(A => un1_data_in_validlt30_14, B => - \counter_points_snapshot[27]_net_1\, C => - \counter_points_snapshot[26]_net_1\, Y => - un1_data_in_validlt30_22); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[21]\, C => N786, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => N_41, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[29]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[20]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1B - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - N_52, Y => N_33); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[20]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[22]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I302_Y_0_0); - - \counter_points_snapshot_RNIICLF1[8]\ : MX2C - port map(A => I_45_4, B => - \counter_points_snapshot[8]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[23]\); - - \counter_points_snapshot_RNIG1PK[16]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[17]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : OR2A - port map(A => N590, B => N582, Y => N646); - - \counter_points_snapshot_RNI9ND9[16]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un1_data_in_validlt30_8); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : OR2A - port map(A => N383, B => N386, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - N_47_0, Y => ADD_32x32_fast_I292_Y_0_0); - - \counter_points_snapshot_RNITFFM1[0]\ : NOR3C - port map(A => un1_data_in_validlt30_16, B => - un1_data_in_validlt30_15, C => un1_data_in_validlt30_24, - Y => un1_data_in_validlt30_27); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : OR2B - port map(A => ADD_32x32_fast_I250_Y_3, B => N771, Y => N738); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f2_wdata(90), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(154)); - - \counter_points_snapshot_RNI047N1[11]\ : MX2 - port map(A => N_4, B => \counter_points_snapshot[11]_net_1\, - S => counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - OR2 - port map(A => N764, B => N497, Y => N760); - - \data_out[82]\ : DFN1C0 - port map(D => sample_f2_wdata(18), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f2_wdata(53), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1C - port map(A => N760, B => ADD_32x32_fast_I300_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : OR2 - port map(A => N554, B => N546, Y => ADD_32x32_fast_I254_Y_0); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f2_wdata(12), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f2_wdata(88), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(152)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_1 : OA1B - port map(A => N_47_1, B => - \un1_counter_points_snapshot[14]\, C => N425, Y => - ADD_32x32_fast_I118_Y_1); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f2_wdata(85), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(149)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f2_wdata(63), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : OR2B - port map(A => N654_i, B => N638, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : NOR2 - port map(A => N652, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2 - port map(A => N588, B => N533, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f2_wdata(73), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I30_G0N : OR3B - port map(A => \counter_points_snapshot[30]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N470); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : NOR2 - port map(A => N531, B => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f2_wdata(91), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(155)); - - \counter_points_snapshot_RNIV6C9[20]\ : NOR2 - port map(A => \counter_points_snapshot[20]_net_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - un1_data_in_validlt30_10); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_21, - Y => \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1C - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[17]_net_1\); - - data_out_valid_RNO_0 : OR3A - port map(A => un1_data_in_valid, B => start_snapshot_f2, C - => burst_f2, Y => N_57); - - \data_out[90]\ : DFN1C0 - port map(D => sample_f2_wdata(26), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_0 : AO1 - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[19]\, C => N_47_1, Y => - ADD_32x32_fast_I126_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR3 - port map(A => N419, B => N422, C => N511, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR3B - port map(A => ADD_32x32_fast_I251_Y_2, B => N774, C => N620, - Y => N740); - - \counter_points_snapshot_RNO[14]\ : XA1C - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - N_52, Y => N_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_G0N : NOR3B - port map(A => \counter_points_snapshot[20]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N440); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR3A - port map(A => N401, B => N404, C => N515, Y => N578); - - \counter_points_snapshot_RNIF7E9[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un1_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[29]\, C => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - counter_points_snapshot_2_sqmuxa_0_a2 : OR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_60, - Y => counter_points_snapshot_2_sqmuxa_i); - - \data_out[99]\ : DFN1C0 - port map(D => sample_f2_wdata(35), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(99)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : OR3C - port map(A => N634, B => N618, C => N650_i, Y => N754); - - \data_out[106]\ : DFN1C0 - port map(D => sample_f2_wdata(42), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1C - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[21]_net_1\); - - \counter_points_snapshot_RNI77D9[24]\ : NOR2A - port map(A => \counter_points_snapshot_i_0[24]\, B => - \counter_points_snapshot[25]_net_1\, Y => - un1_data_in_validlt30_12); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : OR2 - port map(A => N515, B => N511, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => sample_f2_wdata(34), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(98)); - - \data_out[80]\ : DFN1C0 - port map(D => sample_f2_wdata(16), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f2_wdata(8), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : OR3B - port map(A => ADD_32x32_fast_I256_Y_0, B => N789_i, C => - N630, Y => N750); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_G0N : NOR3B - port map(A => \counter_points_snapshot[22]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N446); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AOI1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47, Y => N499); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[23]\, C => N648, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - counter_points_snapshot_2_sqmuxa_0_a2_0 : OR2A - port map(A => start_snapshot_f2, B => sample_f2_val, Y => - N_60); - - \data_out[89]\ : DFN1C0 - port map(D => sample_f2_wdata(25), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(89)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : OR2 - port map(A => ADD_32x32_fast_I263_Y_0, B => N628, Y => N764); - - counter_points_snapshot_0_sqmuxa_1_0_a2 : OR3B - port map(A => sample_f2_val, B => start_snapshot_f2, C => - burst_f2, Y => counter_points_snapshot_0_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, C => N789_i, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f2_wdata(52), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[19]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => I_9_20, B => - \un1_data_out_valid_0_sqmuxa_2[2]\, S => N_60, Y => N_18); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - N_47_0, Y => ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : NOR2 - port map(A => N594, B => N586, Y => N650_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[26]\, C => N654_i, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1B - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[18]_net_1\); - - \data_out[88]\ : DFN1C0 - port map(D => sample_f2_wdata(24), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XNOR2 - port map(A => \un1_counter_points_snapshot[31]\, B => - N_47_1, Y => \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f2_wdata(62), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => sample_f2_wdata(30), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f2_wdata(76), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f2_wdata(72), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(136)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I27_G0N : OR3B - port map(A => \counter_points_snapshot[27]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N461); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I293_Y_0_0); - - \un1_data_out_valid_0_sqmuxa_1_i_0[31]\ : AOI1B - port map(A => start_snapshot_f2, B => burst_f2, C => - sample_f2_val, Y => - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\); - - \counter_points_snapshot_RNIH5PK[17]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[22]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[22]_net_1\); - - \counter_points_snapshot_RNIEUQI[14]\ : NOR3A - port map(A => un1_data_in_validlt30_8, B => - \counter_points_snapshot[15]_net_1\, C => - \counter_points_snapshot[14]_net_1\, Y => - un1_data_in_validlt30_19); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2A - port map(A => N380, B => N531, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => N_47_0, - Y => ADD_32x32_fast_I304_Y_0_0); - - \data_out[101]\ : DFN1C0 - port map(D => sample_f2_wdata(37), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(101)); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f2_wdata(93), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_20, - Y => \counter_points_snapshot_10[4]\); - - \counter_points_snapshot_RNO[30]\ : XA1C - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - N_52, Y => N_43); - - \counter_points_snapshot_RNIEPOK[14]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[14]_net_1\, Y => - \un1_counter_points_snapshot[17]\); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : - AOI1 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => N_47, Y => N497); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR3B - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N572, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : OA1B - port map(A => N_47_1, B => - \un1_counter_points_snapshot[25]\, C => N404, Y => - ADD_32x32_fast_I134_Y_0); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f2_wdata(6), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => I_24_4, B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_21); - - \data_out[84]\ : DFN1C0 - port map(D => sample_f2_wdata(20), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => sample_f2_wdata(39), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I7_G0N : OR2A - port map(A => \un1_counter_points_snapshot[24]\, B => N_47, - Y => N401); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : OA1B - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[28]\, C => N_47, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1B - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - N_52, Y => N_35); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I8_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[23]\, B => - N_47_1, Y => N404); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f2_wdata(15), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f2_wdata(80), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(144)); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0 : OR3B - port map(A => sample_f2_val, B => start_snapshot_f2, C => - burst_f2, Y => counter_points_snapshot_0_sqmuxa_1_0); - - \counter_points_snapshot_RNI1BRI1[9]\ : MX2C - port map(A => I_52_4, B => - \counter_points_snapshot[9]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[22]\); - - \counter_points_snapshot_RNO[8]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_24, - Y => \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => sample_f2_wdata(47), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2A - port map(A => \un1_counter_points_snapshot[31]\, B => - N_47_1, Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f2_wdata(78), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f2_wdata(14), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - N_52, Y => N_29); - - \counter_points_snapshot_RNIKTDU4[31]\ : AO1C - port map(A => start_snapshot_f2, B => un1_data_in_valid, C - => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, Y => - N_47_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : OR2 - port map(A => N580, B => N572, Y => N636); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_1 : OA1 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, C => N401, Y => - ADD_32x32_fast_I134_Y_1); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => I_13_20, B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_19); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => N_35, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[25]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : NOR3B - port map(A => N483, B => N550, C => N479, Y => - ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I1_G0N : OR2A - port map(A => \un1_counter_points_snapshot[30]\, B => N_47, - Y => N383); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f2_wdata(57), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : AO1D - port map(A => \un1_counter_points_snapshot[15]\, B => N_47, - C => N425, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_16, - Y => \counter_points_snapshot_10[0]\); - - \counter_points_snapshot_RNI4IFC1[7]\ : MX2 - port map(A => I_38_4, B => - \counter_points_snapshot[7]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[24]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f2_wdata(67), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f2_wdata(49), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(113)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f2_wdata(81), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(145)); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f2_wdata(2), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[1]_net_1\); - - \counter_points_snapshot_RNO[31]\ : XA1B - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - N_52, Y => N_45); - - \counter_points_snapshot_RNO_0[0]\ : MX2B - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_16); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N771, B => ADD_32x32_fast_I295_Y_0_0, C => - N_52, Y => N_13); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f2_wdata(59), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(123)); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f2_wdata(69), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : NOR3B - port map(A => \counter_points_snapshot[21]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N443); - - \counter_points_snapshot_RNO[29]\ : XA1C - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - N_52, Y => N_41); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => N_45, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : AO1C - port map(A => N_47_1, B => \un1_counter_points_snapshot[3]\, - C => N461, Y => N479); - - \counter_points_snapshot_RNI0RU21[4]\ : MX2 - port map(A => I_20_12, B => - \counter_points_snapshot[4]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[27]\); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f2_wdata(10), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(74)); - - \counter_points_snapshot_RNO[10]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_26, - Y => \counter_points_snapshot_10[10]\); - - \counter_points_snapshot_RNI7G66[6]\ : NOR2 - port map(A => \counter_points_snapshot[6]_net_1\, B => - \counter_points_snapshot[7]_net_1\, Y => - un1_data_in_validlt30_3); - - \data_out[108]\ : DFN1C0 - port map(D => sample_f2_wdata(44), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => I_31_5, B => - \un1_data_out_valid_0_sqmuxa_2[6]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_22); - - \counter_points_snapshot_RNI3NC9[23]\ : NOR2 - port map(A => \counter_points_snapshot[22]_net_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - un1_data_in_validlt30_11); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f2_wdata(92), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(156)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_Y : OR3 - port map(A => N580, B => N588, C => N533, Y => N786); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => I_45_4, B => - \un1_data_out_valid_0_sqmuxa_2[8]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_24); - - \counter_points_snapshot_RNO[1]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_17, - Y => \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_0, - Y => ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I25_G0N : NOR3B - port map(A => \counter_points_snapshot[25]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N455); - - \counter_points_snapshot_RNIGU5V[6]\ : NOR3C - port map(A => un1_data_in_validlt30_4, B => - un1_data_in_validlt30_3, C => un1_data_in_validlt30_18, Y - => un1_data_in_validlt30_24); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : NOR2 - port map(A => N458, B => N455, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - OR2 - port map(A => N756, B => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[22]_net_1\); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => N_7, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1P0 - port map(D => N_31, CLK => HCLK_c, PRE => HRESETn_c, Q => - \counter_points_snapshot_i_0[24]\); - - \counter_points_snapshot_RNIKTDU4_1[31]\ : AO1C - port map(A => start_snapshot_f2, B => un1_data_in_valid, C - => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, Y => - N_47); - - \data_out[95]\ : DFN1C0 - port map(D => sample_f2_wdata(31), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(95)); - - \counter_points_snapshot_RNIJ9PK[28]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I196_Y_0_o2 : - OR2B - port map(A => N650_i, B => N401, Y => N648); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR2B - port map(A => ADD_32x32_fast_I126_Y_1, B => - ADD_32x32_fast_I126_Y_0, Y => N572); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => I_52_4, B => - \un1_data_out_valid_0_sqmuxa_2[9]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_25); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : OA1C - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N419, Y => ADD_32x32_fast_I126_Y_1); - - \counter_points_snapshot_RNO[3]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_19, - Y => \counter_points_snapshot_10[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot_i[26]\, C => N_47_1, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f2_wdata(54), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(118)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : NOR2A - port map(A => N380, B => N646, Y => N789_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[26]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I306_Y_0_0); - - \counter_points_snapshot_RNICEQI[18]\ : NOR3A - port map(A => un1_data_in_validlt30_10, B => - \counter_points_snapshot[19]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un1_data_in_validlt30_20); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : NOR3B - port map(A => N461, B => ADD_32x32_fast_I251_Y_0, C => N458, - Y => ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2 - port map(A => N642, B => N594, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I287_Y_0_0, B => N650_i, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[25]\, C => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - AO1D - port map(A => \un1_counter_points_snapshot[8]\, B => N_47, - C => N446, Y => N489); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[20]\, C => N783, Y => - \un1_data_out_valid_0_sqmuxa_2[11]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I100_Y : OR2A - port map(A => N483, B => N487, Y => N546); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f2_wdata(64), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(128)); - - \counter_points_snapshot_RNO[11]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_27, - Y => \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => sample_f2_wdata(33), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f2_wdata(74), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(138)); - - \counter_points_snapshot_RNII9PK[18]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - \counter_points_snapshot_RNIDAKS[2]\ : MX2C - port map(A => I_9_20, B => - \counter_points_snapshot[2]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot_i[29]\); - - \counter_points_snapshot_RNIU9AM[0]\ : MX2A - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[31]\); - - \data_out[85]\ : DFN1C0 - port map(D => sample_f2_wdata(21), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[3]_net_1\); - - \counter_points_snapshot_RNIVV6N1[10]\ : MX2C - port map(A => I_56_4, B => - \counter_points_snapshot[10]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => sample_f2_wdata(45), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(109)); - - \counter_points_snapshot_RNI4TL51[23]\ : NOR3C - port map(A => un1_data_in_validlt30_12, B => - un1_data_in_validlt30_11, C => un1_data_in_validlt30_22, - Y => un1_data_in_validlt30_26); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : OA1C - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[20]\, C => N_47, Y => N511); - - \counter_points_snapshot_RNIBHSA[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[30]_net_1\, Y => - un1_data_in_validlt30_15); - - \counter_points_snapshot_RNIBG66[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un1_data_in_validlt30_4); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => N_29, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[21]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : OR3 - port map(A => N485, B => N489, C => N556, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f2_wdata(83), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(147)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f2_wdata(87), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(151)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - N_47_0, Y => ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => N_47_0, - Y => ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => sample_f2_wdata(23), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(87)); - - counter_points_snapshot_10_12_i_o2_0 : NOR2A - port map(A => enable_f2, B => burst_f2, Y => - \counter_points_snapshot_10_12_i_o2_0\); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f2_wdata(89), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(153)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I283_Y_0_0, B => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR3 - port map(A => N636, B => N620, C => N652, Y => N756); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : OA1C - port map(A => \un1_counter_points_snapshot[28]\, B => N_47, - C => N386, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : OR2B - port map(A => ADD_32x32_fast_I142_Y_0, B => N529, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[27]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I307_Y_0_0); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f2_wdata(55), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : NOR3B - port map(A => I32_un1_Y, B => N470, C => N479, Y => - ADD_32x32_fast_I250_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AOI1 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[21]\, C => N_47, Y => N515); - - \counter_points_snapshot_RNIELOK[23]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => I_38_4, B => - \un1_data_out_valid_0_sqmuxa_2[7]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_23); - - \counter_points_snapshot_RNO[9]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_25, - Y => \counter_points_snapshot_10[9]\); - - \counter_points_snapshot_RNIFPOK[24]\ : NOR2A - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot_i_0[24]\, Y => - \un1_counter_points_snapshot[7]\); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f2_wdata(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f2_wdata(65), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I251_Y_1, B => N485, C => N489, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f2_wdata(75), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => N_33, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[25]_net_1\); - - counter_points_snapshot_2_sqmuxa_0_a2_1 : OR2A - port map(A => enable_f2, B => burst_f2, Y => - counter_points_snapshot_2_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : OR2B - port map(A => ADD_32x32_fast_I134_Y_1, B => - ADD_32x32_fast_I134_Y_0, Y => N580); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - OA1C - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N783, Y => N780); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : OR2B - port map(A => N383, B => N380, Y => N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : AO1A - port map(A => N_47, B => \un1_counter_points_snapshot[7]\, - C => N455, Y => N485); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f2_wdata(11), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(75)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => - N_47_0, Y => ADD_32x32_fast_I284_Y_0_0); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f2_wdata(4), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(68)); - - \counter_points_snapshot_RNICHOK[12]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - \counter_points_snapshot_RNI3G66[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un1_data_in_validlt30_2); - - \counter_points_snapshot_RNO_0[11]\ : MX2C - port map(A => N_4, B => \un1_data_out_valid_0_sqmuxa_2[11]\, - S => counter_points_snapshot_2_sqmuxa_i, Y => N_27); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_0 : OA1A - port map(A => \un1_counter_points_snapshot[3]\, B => N_47_0, - C => I32_un1_Y, Y => ADD_32x32_fast_I251_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : AO1D - port map(A => \un1_counter_points_snapshot[12]\, B => N_47, - C => N440, Y => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OR3B - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N556, Y => N620); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : NOR3A - port map(A => N380, B => N646, C => N630, Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768, B => ADD_32x32_fast_I296_Y_0_0, C => - N_52, Y => N_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : NOR3 - port map(A => N495, B => N499, C => N566, Y => N622); - - data_out_valid_RNO : NOR3C - port map(A => sample_f2_val, B => enable_f2, C => N_57, Y - => N_49); - - \data_out[100]\ : DFN1C0 - port map(D => sample_f2_wdata(36), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : NOR3 - port map(A => N626, B => N594, C => N642, Y => N762_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : - OR3A - port map(A => N461, B => N458, C => N485, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f2_wdata(13), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f2_wdata(82), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_18, - Y => \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : NOR2 - port map(A => N582, B => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1B - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - N_52, Y => N_9); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f2_wdata(94), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(158)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I2_G0N : NOR2 - port map(A => \un1_counter_points_snapshot_i[29]\, B => - N_47, Y => N386); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f2_wdata(0), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[24]\, B => - N_47_0, Y => ADD_32x32_fast_I287_Y_0_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(2 to 2); - status_full : out std_logic_vector(2 to 2); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - update_and_sel_3 : in std_logic_vector(5 downto 4); - addr_data_f2 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(2 to 2); - addr_data_vector_62 : out std_logic; - addr_data_vector_61 : out std_logic; - addr_data_vector_5 : in std_logic; - addr_data_vector_4 : in std_logic; - addr_data_vector_3 : in std_logic; - addr_data_vector_0 : in std_logic; - addr_data_vector_12 : in std_logic; - addr_data_vector_11 : in std_logic; - addr_data_vector_9 : in std_logic; - addr_data_vector_7 : in std_logic; - addr_data_vector_6 : in std_logic; - addr_data_vector_26 : in std_logic; - addr_data_vector_24 : in std_logic; - addr_data_vector_22 : in std_logic; - addr_data_vector_28 : in std_logic; - addr_data_vector_66 : out std_logic; - addr_data_vector_65 : out std_logic; - addr_data_vector_91 : out std_logic; - addr_data_vector_89 : out std_logic; - addr_data_vector_87 : out std_logic; - addr_data_vector_63 : out std_logic; - addr_data_vector_72 : out std_logic; - addr_data_vector_74 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_78 : out std_logic; - addr_data_vector_81 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_84 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_83 : out std_logic; - N_1329 : out std_logic; - N_1328 : out std_logic; - N_1327 : out std_logic; - N_1324 : out std_logic; - N_1322 : out std_logic; - N_1321 : out std_logic; - N_1319 : out std_logic; - N_1317 : out std_logic; - N_1316 : out std_logic; - N_1308 : out std_logic; - N_1306 : out std_logic; - N_1304 : out std_logic; - N_1296 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, m41_m6_0_a2_7, m41_m6_0_a2_2, - m41_m6_0_a2_1, m41_m6_0_a2_6, m41_m6_0_a2_4, - m26_m6_0_a2_6, \addr_data_vector[76]\, m26_m6_0_a2_4, - m26_m6_0_a2_5, \addr_data_vector[73]\, - \addr_data_vector[72]\, m26_m6_0_a2_2, - \addr_data_vector[71]\, \addr_data_vector[79]\, - \addr_data_vector[78]\, \addr_data_vector[74]\, - \un1_state_12_3_0[4]\, \update_r_i[0]\, - \update_r[1]_net_1\, \state_ns_i_0[3]\, N_131, - \un1_state_12[4]\, \un1_state_12_2[4]\, \un1_address[6]\, - address_0_sqmuxa, \addr_data_vector[70]\, N_5_0, N_116, - N_129, \state[1]_net_1\, \state_ns[0]\, N_125, N_124, - N_110, \state[3]_net_1\, \state[4]_net_1\, N_130, - \state[2]_net_1\, state7, un3_update_r, N_27_0_i_0, - N_13_0, N_15_0_i_0, N_16_0, N_17_0_i_0, N_19_0, - N_20_0_i_0, \addr_data_vector[75]\, N_22_0_i_0, N_23_0, - N_26_0_i_0, N_25_0, N_28_0_i_0, \addr_data_vector[80]\, - N_30_0_i_0, \addr_data_vector[81]\, N_31_0, - \un1_address[19]\, \addr_data_vector[82]\, - \addr_data_vector[83]\, N_34_0, \un1_address[20]\, - \addr_data_vector[84]\, N_37_0, \addr_data_vector[85]\, - \un1_address[23]\, \addr_data_vector[86]\, - \addr_data_vector[87]\, N_40_i_0, N_41, N_43, - \addr_data_vector[89]\, N_45, \addr_data_vector[91]\, - N_47, \addr_data_vector[93]\, N_49_i_0, - \addr_data_vector[95]\, N_50_i_0, \addr_data_vector[66]\, - \addr_data_vector[67]\, N_51_i_0, N_69, N_52_i_0, - \addr_data_vector[68]\, N_1_i_0, N_54_0_i_0, N_55_0_i_0, - \addr_data_vector[77]\, \un1_address[18]\, - \un1_address[21]\, \un1_address[22]\, \un1_address[24]\, - \addr_data_vector[88]\, \un1_address[25]\, - \un1_address[26]\, \addr_data_vector[90]\, - \un1_address[27]\, \un1_address[28]\, - \addr_data_vector[92]\, \un1_address[29]\, - \un1_address[30]\, \addr_data_vector[94]\, - \addr_data_vector[69]\, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[15]\, \address_7[16]\, - \address_7[17]\, \address_7[18]\, \address_7[19]\, - \state[0]_net_1\, \address_7[20]\, \address_7[21]\, - \address_7[22]\, \address_7[23]\, \address_7[24]\, - \address_7[25]\, \address_7[26]\, \address_7[27]\, - \address_7[28]\, \address_7[29]\, \address_7[30]\, - \address_7[31]\, N_56_0_i_0, un1_state_9, \nb_send_5[0]\, - \nb_send_5[1]\, \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, N_126, N_113, \state_ns[2]\, - un1_state_11, \address_7[14]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_66 <= \addr_data_vector[69]\; - addr_data_vector_65 <= \addr_data_vector[68]\; - addr_data_vector_91 <= \addr_data_vector[94]\; - addr_data_vector_89 <= \addr_data_vector[92]\; - addr_data_vector_87 <= \addr_data_vector[90]\; - addr_data_vector_63 <= \addr_data_vector[66]\; - addr_data_vector_72 <= \addr_data_vector[75]\; - addr_data_vector_74 <= \addr_data_vector[77]\; - addr_data_vector_79 <= \addr_data_vector[82]\; - addr_data_vector_78 <= \addr_data_vector[81]\; - addr_data_vector_81 <= \addr_data_vector[84]\; - addr_data_vector_80 <= \addr_data_vector[83]\; - addr_data_vector_84 <= \addr_data_vector[87]\; - addr_data_vector_85 <= \addr_data_vector[88]\; - addr_data_vector_77 <= \addr_data_vector[80]\; - addr_data_vector_82 <= \addr_data_vector[85]\; - addr_data_vector_83 <= \addr_data_vector[86]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[80]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[74]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[94]\); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f2(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : XOR2 - port map(A => N_43, B => \addr_data_vector[90]\, Y => - \un1_address[26]\); - - \address_RNILG94[25]\ : MX2C - port map(A => addr_data_vector_22, B => - \addr_data_vector[89]\, S => sel_data_1(1), Y => N_1304); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[90]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[84]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \address_RNI5894[10]\ : MX2C - port map(A => addr_data_vector_7, B => - \addr_data_vector[74]\, S => sel_data_1(1), Y => N_1317); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1C - port map(A => \addr_data_vector[68]\, B => N_69, C => - \addr_data_vector[69]\, Y => N_52_i_0); - - un1_address_m26_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[77]\, B => - \addr_data_vector[76]\, C => m26_m6_0_a2_4, Y => - m26_m6_0_a2_6); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[76]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - un1_address_m26_m6_0_a2 : OR3B - port map(A => m26_m6_0_a2_6, B => m26_m6_0_a2_5, C => - N_13_0, Y => N_27_0_i_0); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f2(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - un1_address_m41_m6_0_a2_7 : NOR3C - port map(A => m41_m6_0_a2_2, B => m41_m6_0_a2_1, C => - m41_m6_0_a2_6, Y => m41_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XNOR2 - port map(A => N_19_0, B => \addr_data_vector[75]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[86]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f2(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[66]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f2(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f2(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_110, Q => status_full_err(2)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : OR3B - port map(A => \addr_data_vector[73]\, B => - \addr_data_vector[74]\, C => N_16_0, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - \address_RNIPNMA[3]\ : MX2C - port map(A => addr_data_vector_0, B => - \addr_data_vector[67]\, S => sel_data_1(1), Y => N_1324); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f2(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[69]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[79]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[77]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[83]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[89]\); - - \address_RNIT9IB[7]\ : MX2C - port map(A => addr_data_vector_4, B => - \addr_data_vector[71]\, S => sel_data(1), Y => N_1328); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \state_RNIV5SU8[3]\ : OR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa); - - \address_RNIR1IB[6]\ : MX2C - port map(A => addr_data_vector_3, B => - \addr_data_vector[70]\, S => sel_data(1), Y => N_1327); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[87]\); - - un1_address_m26_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[73]\, B => - \addr_data_vector[72]\, C => m26_m6_0_a2_2, Y => - m26_m6_0_a2_5); - - \state_RNISHSP8_0[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => state7, Y => N_126); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[71]\, C => - \addr_data_vector[72]\, Y => N_15_0_i_0); - - un1_address_m29 : AX1 - port map(A => N_27_0_i_0, B => \addr_data_vector[80]\, C - => \addr_data_vector[81]\, Y => N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[93]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[82]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f2(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f2(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f2(0), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - addr_data_vector_61); - - \address_RNITG94[29]\ : MX2C - port map(A => addr_data_vector_26, B => - \addr_data_vector[93]\, S => sel_data_1(1), Y => N_1308); - - \state_RNIV5SU8_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - GND_i : GND - port map(Y => \GND\); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f2(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[68]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[92]\); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3B - port map(A => N_131, B => N_129, C => \state[3]_net_1\, Y - => N_125); - - \address_RNI9894[12]\ : MX2C - port map(A => addr_data_vector_9, B => - \addr_data_vector[76]\, S => sel_data_1(1), Y => N_1319); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR3 - port map(A => address_0_sqmuxa, B => \addr_data_vector[70]\, - C => N_5_0, Y => \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f2(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - un1_address_m24 : OR3B - port map(A => \addr_data_vector[77]\, B => - \addr_data_vector[78]\, C => N_23_0, Y => N_25_0); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[7]_net_1\); - - \update_r_RNIV5SU8[0]\ : NOR2 - port map(A => \un1_state_12_3_0[4]\, B => - \un1_state_12_2[4]\, Y => \un1_state_12[4]\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f2(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[78]\); - - \state_RNO[1]\ : OA1C - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f2(14), S => - \state[0]_net_1\, Y => \address_7[14]\); - - \address_RNIPG94[27]\ : MX2C - port map(A => addr_data_vector_24, B => - \addr_data_vector[91]\, S => sel_data_1(1), Y => N_1306); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[88]\); - - un1_address_m27 : XNOR2 - port map(A => N_27_0_i_0, B => \addr_data_vector[80]\, Y - => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : AX1 - port map(A => N_27_0_i_0, B => m41_m6_0_a2_7, C => - \addr_data_vector[89]\, Y => \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - un1_address_m30 : OR3B - port map(A => \addr_data_vector[80]\, B => - \addr_data_vector[81]\, C => N_27_0_i_0, Y => N_31_0); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[73]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3C - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[72]\); - - un1_address_m50 : XOR2 - port map(A => N_69, B => \addr_data_vector[68]\, Y => - N_51_i_0); - - un1_address_m39 : XOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[66]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : NOR2A - port map(A => update_and_sel_3(4), B => update_and_sel_3(5), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f2(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => status_full_ack(2), B => N_130, C => N_126, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f2(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f2(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1 - port map(A => N_37_0, B => \addr_data_vector[86]\, C => - \addr_data_vector[87]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa, C => - \addr_data_vector[70]\, Y => N_13_0); - - un1_address_m59 : XNOR2 - port map(A => N_41, B => \addr_data_vector[88]\, Y => - \un1_address[24]\); - - \update_r[0]\ : DFN1P0 - port map(D => update_and_sel_3(4), CLK => HCLK_c, PRE => - HRESETn_c, Q => \update_r_i[0]\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f2(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f2(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[71]\, B => - \addr_data_vector[72]\, C => N_13_0, Y => N_16_0); - - un1_address_m58 : XNOR2 - port map(A => N_37_0, B => \addr_data_vector[86]\, Y => - \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - \address_RNID894[14]\ : MX2C - port map(A => addr_data_vector_11, B => - \addr_data_vector[78]\, S => sel_data_1(1), Y => N_1321); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - un1_address_m41_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[86]\, B => - \addr_data_vector[85]\, C => m41_m6_0_a2_4, Y => - m41_m6_0_a2_6); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f2(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[67]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : AX1C - port map(A => \addr_data_vector[92]\, B => N_45, C => - \addr_data_vector[93]\, Y => \un1_address[29]\); - - \address_RNI58OA[9]\ : MX2C - port map(A => addr_data_vector_6, B => - \addr_data_vector[73]\, S => sel_data_1(1), Y => N_1316); - - un1_address_m34 : XNOR2 - port map(A => N_34_0, B => \addr_data_vector[84]\, Y => - \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f2(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - un1_address_m26_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[74]\, B => - \addr_data_vector[75]\, Y => m26_m6_0_a2_2); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(2), B => N_131, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : XNOR2 - port map(A => N_23_0, B => \addr_data_vector[77]\, Y => - N_55_0_i_0); - - un1_address_m22 : OR3B - port map(A => \addr_data_vector[75]\, B => - \addr_data_vector[76]\, C => N_19_0, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[71]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - \address_RNIF894[15]\ : MX2C - port map(A => addr_data_vector_12, B => - \addr_data_vector[79]\, S => sel_data_1(1), Y => N_1322); - - un1_address_m25 : XNOR2 - port map(A => N_25_0, B => \addr_data_vector[79]\, Y => - N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[3]_net_1\); - - \update_r_RNI3KV4[0]\ : OR2B - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => un3_update_r); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_3(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => \update_r[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - \update_r_RNI3KV4_0[0]\ : OR2 - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => \un1_state_12_3_0[4]\); - - un1_address_m40 : OR3B - port map(A => \addr_data_vector[86]\, B => - \addr_data_vector[87]\, C => N_37_0, Y => N_41); - - \address_RNIIO94[31]\ : MX2C - port map(A => addr_data_vector_28, B => - \addr_data_vector[95]\, S => sel_data_0(1), Y => N_1296); - - un1_address_m57 : AX1 - port map(A => N_34_0, B => \addr_data_vector[84]\, C => - \addr_data_vector[85]\, Y => \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f2(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1C - port map(A => \addr_data_vector[66]\, B => - \un1_state_12[4]\, C => \addr_data_vector[67]\, Y => - N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[73]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f2(18), S - => \state_0[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f2(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[94]\, B => N_47, C => - \addr_data_vector[95]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[70]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - status_full_err_RNO : OR3 - port map(A => \state[3]_net_1\, B => \state[4]_net_1\, C - => N_130, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f2(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un1_address_m36 : OR3B - port map(A => \addr_data_vector[84]\, B => - \addr_data_vector[85]\, C => N_34_0, Y => N_37_0); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[75]\); - - \state_RNIHABE[1]\ : NOR2A - port map(A => status_full_ack(2), B => N_131, Y => N_118); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[95]\); - - \state_RNISHSP8[3]\ : OR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : XNOR2 - port map(A => N_31_0, B => \addr_data_vector[82]\, Y => - \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f2(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - un1_address_m44 : NOR3C - port map(A => \addr_data_vector[90]\, B => N_43, C => - \addr_data_vector[91]\, Y => N_45); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f2(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f2(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[85]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - un1_address_m62 : AX1C - port map(A => \addr_data_vector[90]\, B => N_43, C => - \addr_data_vector[91]\, Y => \un1_address[27]\); - - un1_address_m32 : AX1 - port map(A => N_31_0, B => \addr_data_vector[82]\, C => - \addr_data_vector[83]\, Y => \un1_address[19]\); - - un1_address_m12_e : OR3C - port map(A => \addr_data_vector[68]\, B => N_69, C => - \addr_data_vector[69]\, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[81]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[94]\, Y => - \un1_address[30]\); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[71]\, Y => - N_1_i_0); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[91]\); - - \state_RNO[3]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : AX1 - port map(A => N_19_0, B => \addr_data_vector[75]\, C => - \addr_data_vector[76]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : AX1 - port map(A => N_23_0, B => \addr_data_vector[77]\, C => - \addr_data_vector[78]\, Y => N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f2(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : NOR3C - port map(A => \addr_data_vector[66]\, B => - \un1_state_12[4]\, C => \addr_data_vector[67]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f2(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : OR2 - port map(A => \state[2]_net_1\, B => N_126, Y => - un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f2(1), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - addr_data_vector_62); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_11, Q => status_full(2)); - - un1_address_m63 : XOR2 - port map(A => N_45, B => \addr_data_vector[92]\, Y => - \un1_address[28]\); - - un1_address_m33 : OR3B - port map(A => \addr_data_vector[82]\, B => - \addr_data_vector[83]\, C => N_31_0, Y => N_34_0); - - un1_address_m26_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[71]\, B => - \addr_data_vector[79]\, C => \addr_data_vector[78]\, Y - => m26_m6_0_a2_4); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un1_address_m41_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[83]\, B => - \addr_data_vector[84]\, Y => m41_m6_0_a2_2); - - un1_address_m41_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[81]\, B => - \addr_data_vector[82]\, Y => m41_m6_0_a2_1); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f2(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR3C - port map(A => \addr_data_vector[92]\, B => N_45, C => - \addr_data_vector[93]\, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : AX1 - port map(A => N_16_0, B => \addr_data_vector[73]\, C => - \addr_data_vector[74]\, Y => N_54_0_i_0); - - \state_RNIVJCD[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - un1_address_m41_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[80]\, B => - \addr_data_vector[88]\, C => \addr_data_vector[87]\, Y - => m41_m6_0_a2_4); - - \state_RNIH9F11[2]\ : NOR2B - port map(A => \state[2]_net_1\, B => N_129, Y => N_130); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[3]_net_1\, C - => \state[2]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f2(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - un1_address_m42 : NOR3B - port map(A => m41_m6_0_a2_7, B => \addr_data_vector[89]\, C - => N_27_0_i_0, Y => N_43); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - \address_RNIVHIB[8]\ : MX2C - port map(A => addr_data_vector_5, B => - \addr_data_vector[72]\, S => sel_data(1), Y => N_1329); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(0 to 0); - status_full : out std_logic_vector(0 to 0); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - update_and_sel_7 : in std_logic_vector(1 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(0 to 0); - addr_data_vector_69 : in std_logic; - addr_data_vector_68 : in std_logic; - addr_data_vector_66 : in std_logic; - addr_data_vector_77 : in std_logic; - addr_data_vector_75 : in std_logic; - addr_data_vector_86 : in std_logic; - addr_data_vector_85 : in std_logic; - addr_data_vector_84 : in std_logic; - addr_data_vector_83 : in std_logic; - addr_data_vector_82 : in std_logic; - addr_data_vector_81 : in std_logic; - addr_data_vector_80 : in std_logic; - addr_data_vector_92 : in std_logic; - addr_data_vector_90 : in std_logic; - addr_data_vector_88 : in std_logic; - addr_data_vector_87 : in std_logic; - addr_data_vector_94 : in std_logic; - addr_data_vector_65 : in std_logic; - addr_data_vector_64 : in std_logic; - addr_data_vector_3 : out std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_27 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_25 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_8 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_12 : out std_logic; - N_1326 : out std_logic; - N_1325 : out std_logic; - N_1323 : out std_logic; - N_1320 : out std_logic; - N_1318 : out std_logic; - N_1315 : out std_logic; - N_1314 : out std_logic; - N_1313 : out std_logic; - N_1312 : out std_logic; - N_1311 : out std_logic; - N_1310 : out std_logic; - N_1309 : out std_logic; - N_1307 : out std_logic; - N_1305 : out std_logic; - N_1303 : out std_logic; - N_1302 : out std_logic; - N_1295 : out std_logic; - N_1280 : out std_logic; - N_1279 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, \state_RNIBABE[1]_net_1\, N_38, - \nb_send[1]_net_1\, \nb_send[0]_net_1\, N_30, - \nb_send[3]_net_1\, \DWACT_FINC_E[0]\, N_7, - \nb_send[8]_net_1\, \DWACT_FINC_E[4]\, m40_m6_0_a2_7, - m40_m6_0_a2_6, m37_m6_0_a2_4_i, m40_m6_0_a2_3, - m40_m6_0_a2_2, m40_m6_0_a2_4, \addr_data_vector[13]\, - \addr_data_vector[23]\, m40_m6_0_a2_1, - \addr_data_vector[11]\, m23_m7_i_5, m23_m7_i_2, - m23_m7_i_1, m23_m7_i_3, \addr_data_vector[7]\, - \addr_data_vector[12]\, \addr_data_vector[10]\, - \addr_data_vector[8]\, \addr_data_vector[9]\, - ADD_32x32_fast_I164_Y_0_0, address_0_sqmuxa, - \un1_state_12_3_0[4]\, \update_r_i[0]\, - \update_r[1]_net_1\, address_0_sqmuxa_0, \state[3]_net_1\, - un3_update_r, un1_state_5_i_0, \state[4]_net_1\, - \state_ns_i_0[3]\, N_85, address_7_31_m6_e_3, - \addr_data_vector[30]\, address_7_31_m6_e_1, - address_7_31_m6_e_2, \addr_data_vector[28]\, - \addr_data_vector[26]\, m37_m6_0_a2_4_6, - \addr_data_vector[20]\, \addr_data_vector[19]\, - m37_m6_0_a2_4_4, m37_m6_0_a2_4_5, \addr_data_vector[16]\, - m37_m6_0_a2_4_2, \addr_data_vector[22]\, - \addr_data_vector[21]\, \addr_data_vector[17]\, - \addr_data_vector[18]\, \un1_address[6]\, N_5_0, - \state_RNO_0[1]_net_1\, N_83_i, \state[1]_net_1\, - \state_ns[0]\, N_79, N_78, \un1_state_12_2[4]\, N_64, - N_84, \state[2]_net_1\, state7, \address_RNO_2_0[31]\, - m23_m7_i, m23_N_10, m23_m7_i_a5, \addr_data_vector[6]\, - \address_7[31]\, \address_RNO_0_0[31]\, - \address_RNO_1_0[31]\, N_42, \addr_data_vector[31]\, N_2, - \addr_data_vector[2]\, N_4_0, \addr_data_vector[4]\, - N_15_0_i_0, N_13_0, N_16_0, N_17_0_i_0, N_19_0, - N_20_0_i_0, N_21_0, N_22_0_i_0, N_26_0_i_0, - \addr_data_vector[14]\, \addr_data_vector[15]\, N_27_0, - N_28_0_i_0, N_30_0_i_0, N_31_0, \un1_address[19]\, N_34_0, - \un1_address[20]\, N_36_0, \un1_address[23]\, N_40_i_0, - \addr_data_vector[24]\, N_44, \addr_data_vector[25]\, - N_46, \addr_data_vector[27]\, N_50_i_0, - \addr_data_vector[3]\, N_51_i_0, N_52_i_0, - \addr_data_vector[5]\, N_1_i_0, N_54_0_i_0, N_55_0_i_0, - \un1_address[18]\, \un1_address[21]\, \un1_address[22]\, - \un1_address[24]\, \un1_address[25]\, \un1_address[26]\, - \un1_address[27]\, \un1_address[28]\, \un1_address[29]\, - \addr_data_vector[29]\, \un1_address[30]\, \address_7[2]\, - \address_7[3]\, \address_7[4]\, \address_7[5]\, - \address_7[6]\, \address_7[7]\, \address_7[8]\, - \address_7[9]\, \address_7[10]\, \address_7[11]\, - \address_7[12]\, \address_7[13]\, \address_7[15]\, - \address_7[16]\, \address_7[17]\, \state[0]_net_1\, - \address_7[18]\, \address_7[19]\, \address_7[20]\, - \address_7[21]\, \address_7[22]\, \address_7[23]\, - \address_7[24]\, \address_7[25]\, \address_7[26]\, - \address_7[27]\, \address_7[28]\, \address_7[29]\, - \address_7[30]\, N_56_0_i_0, un1_state_9, \nb_send_5[0]\, - \nb_send_5[1]\, \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, N_80, \state_RNO_1[3]\, - \state_ns[2]\, un1_state_11, \address_7[14]\, - \addr_data_vector[0]\, \addr_data_vector[1]\, - \nb_send[2]_net_1\, \nb_send[4]_net_1\, - \nb_send[5]_net_1\, \nb_send[6]_net_1\, - \nb_send[7]_net_1\, \nb_send[9]_net_1\, - \nb_send[10]_net_1\, N_4, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[3]\, N_12, N_17, N_22, \DWACT_FINC_E[1]\, - N_27, N_35, \DWACT_COMP0_E[1]\, \DWACT_COMP0_E[2]\, - \DWACT_COMP0_E[0]\, \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_3 <= \addr_data_vector[3]\; - addr_data_vector_31 <= \addr_data_vector[31]\; - addr_data_vector_14 <= \addr_data_vector[14]\; - addr_data_vector_15 <= \addr_data_vector[15]\; - addr_data_vector_27 <= \addr_data_vector[27]\; - addr_data_vector_29 <= \addr_data_vector[29]\; - addr_data_vector_25 <= \addr_data_vector[25]\; - addr_data_vector_6 <= \addr_data_vector[6]\; - addr_data_vector_8 <= \addr_data_vector[8]\; - addr_data_vector_7 <= \addr_data_vector[7]\; - addr_data_vector_10 <= \addr_data_vector[10]\; - addr_data_vector_9 <= \addr_data_vector[9]\; - addr_data_vector_12 <= \addr_data_vector[12]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[16]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[10]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNIBABE[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[30]\); - - un1_address_m45 : NOR3C - port map(A => \addr_data_vector[27]\, B => N_44, C => - \addr_data_vector[28]\, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f0(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : AX1C - port map(A => \addr_data_vector[25]\, B => N_42, C => - \addr_data_vector[26]\, Y => \un1_address[26]\); - - \address_RNIN894[19]\ : MX2C - port map(A => \addr_data_vector[19]\, B => - addr_data_vector_83, S => sel_data_1(1), Y => N_1312); - - un1_address_m37_m6_0_a2_4_6 : NOR3C - port map(A => \addr_data_vector[20]\, B => - \addr_data_vector[19]\, C => m37_m6_0_a2_4_4, Y => - m37_m6_0_a2_4_6); - - un1_address_m37_m6_0_a2_4 : OR2B - port map(A => m37_m6_0_a2_4_6, B => m37_m6_0_a2_4_5, Y => - m37_m6_0_a2_4_i); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[26]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[20]\); - - \address_RNIK7MA[1]\ : MX2C - port map(A => \addr_data_vector[1]\, B => - addr_data_vector_65, S => sel_data_0(1), Y => N_1280); - - \state_RNI9QRU8_0[3]\ : OR2B - port map(A => address_0_sqmuxa_0, B => state7, Y => - address_0_sqmuxa); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \address_RNIPPHB[5]\ : MX2C - port map(A => \addr_data_vector[5]\, B => - addr_data_vector_69, S => sel_data(1), Y => N_1326); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : XOR2 - port map(A => N_4_0, B => \addr_data_vector[5]\, Y => - N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[12]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f0(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - \update_r_RNIVJV4[0]\ : OR2B - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => un3_update_r); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XNOR2 - port map(A => N_19_0, B => \addr_data_vector[11]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[22]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f0(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[2]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - un1_address_m43 : NOR3C - port map(A => \addr_data_vector[25]\, B => N_42, C => - \addr_data_vector[26]\, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f0(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f0(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_64, Q => status_full_err(0)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : OR3B - port map(A => \addr_data_vector[9]\, B => - \addr_data_vector[10]\, C => N_16_0, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \state_RNIF9F11[2]\ : NOR2A - port map(A => \state[2]_net_1\, B => N_83_i, Y => N_84); - - un1_address_ADD_32x32_fast_I164_Y_0_0 : XNOR2 - port map(A => \addr_data_vector[6]\, B => address_0_sqmuxa, - Y => ADD_32x32_fast_I164_Y_0_0); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f0(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[5]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[15]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[13]\); - - un1_address_m20 : NOR2A - port map(A => \addr_data_vector[11]\, B => N_19_0, Y => - N_21_0); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \address_RNIJ894[17]\ : MX2C - port map(A => \addr_data_vector[17]\, B => - addr_data_vector_81, S => sel_data_1(1), Y => N_1310); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[19]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[25]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[23]\); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[7]\, C => - \addr_data_vector[8]\, Y => N_15_0_i_0); - - un1_address_m29 : AX1 - port map(A => N_27_0, B => \addr_data_vector[16]\, C => - \addr_data_vector[17]\, Y => N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \address_RNO_2[31]\ : NOR3B - port map(A => address_7_31_m6_e_3, B => address_7_31_m6_e_2, - C => \state_0[0]_net_1\, Y => \address_RNO_2_0[31]\); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[29]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[18]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f0(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f0(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address_RNIH894[16]\ : MX2C - port map(A => \addr_data_vector[16]\, B => - addr_data_vector_80, S => sel_data_1(1), Y => N_1309); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f0(0), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - \addr_data_vector[0]\); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - \state_RNIRJCD[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_85); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : NOR3B - port map(A => m40_m6_0_a2_7, B => \addr_data_vector[24]\, C - => N_13_0, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f0(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[4]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[28]\); - - un1_address_m1 : NOR3A - port map(A => \addr_data_vector[2]\, B => - \un1_state_12_2[4]\, C => \un1_state_12_3_0[4]\, Y => N_2); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3A - port map(A => N_85, B => \state[3]_net_1\, C => N_83_i, Y - => N_79); - - \address_RNO_1[31]\ : XNOR2 - port map(A => N_42, B => \addr_data_vector[31]\, Y => - \address_RNO_1_0[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I164_Y_0_0, B => N_5_0, Y => - \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f0(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f0(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[14]\); - - un1_address_m23_m7_i_a5_0 : OR2B - port map(A => N_5_0, B => address_0_sqmuxa, Y => m23_N_10); - - \state_RNO[1]\ : OA1B - port map(A => N_83_i, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => \state_RNO_0[1]_net_1\); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - un1_address_m40_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[13]\, B => - \addr_data_vector[23]\, C => m40_m6_0_a2_1, Y => - m40_m6_0_a2_4); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f0(14), S => - \state[0]_net_1\, Y => \address_7[14]\); - - un1_address_m23_m7_i_a5 : AO1D - port map(A => N_5_0, B => address_0_sqmuxa, C => - \addr_data_vector[6]\, Y => m23_m7_i_a5); - - \state_RNIA6SP8[3]\ : OR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[24]\); - - un1_address_m27 : XNOR2 - port map(A => N_27_0, B => \addr_data_vector[16]\, Y => - N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \address_RNO_0[31]\ : MX2C - port map(A => \addr_data_vector[31]\, B => addr_data_f0(31), - S => \state_0[0]_net_1\, Y => \address_RNO_0_0[31]\); - - un1_address_m60 : XOR2 - port map(A => N_42, B => \addr_data_vector[25]\, Y => - \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - un1_address_m30 : OR3B - port map(A => \addr_data_vector[16]\, B => - \addr_data_vector[17]\, C => N_27_0, Y => N_31_0); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[9]\, Y => - N_17_0_i_0); - - un1_address_m37_m6_0_a2_4_2 : NOR2B - port map(A => \addr_data_vector[17]\, B => - \addr_data_vector[18]\, Y => m37_m6_0_a2_4_2); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - un1_address_m23_m7_i : OR3C - port map(A => m23_N_10, B => m23_m7_i_5, C => m23_m7_i_a5, - Y => m23_m7_i); - - \state_RNI9QRU8[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3C - port map(A => N_79, B => N_78, C => \un1_state_12_2[4]\, Y - => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[8]\); - - un1_address_m40_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[9]\, B => - \addr_data_vector[10]\, Y => m40_m6_0_a2_2); - - \address_RNIHG94[23]\ : MX2C - port map(A => \addr_data_vector[23]\, B => - addr_data_vector_87, S => sel_data_1(1), Y => N_1302); - - un1_address_m50 : AX1C - port map(A => \addr_data_vector[3]\, B => N_2, C => - \addr_data_vector[4]\, Y => N_51_i_0); - - un1_address_m39 : AX1B - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, C => \addr_data_vector[2]\, Y => - N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : OR2A - port map(A => update_and_sel_7(0), B => update_and_sel_7(1), - Y => N_83_i); - - un1_address_m23_m7_i_2 : NOR2B - port map(A => \addr_data_vector[10]\, B => - \addr_data_vector[11]\, Y => m23_m7_i_2); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f0(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => status_full_ack(0), B => N_84, C => N_80, Y - => \state_ns[2]\); - - \address_RNIBG94[20]\ : MX2C - port map(A => \addr_data_vector[20]\, B => - addr_data_vector_84, S => sel_data_1(1), Y => N_1313); - - \address_RNI7894[11]\ : MX2C - port map(A => \addr_data_vector[11]\, B => - addr_data_vector_75, S => sel_data_1(1), Y => N_1318); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f0(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f0(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - un1_address_m40_m6_0_a2_3 : NOR2B - port map(A => \addr_data_vector[11]\, B => - \addr_data_vector[12]\, Y => m40_m6_0_a2_3); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1B - port map(A => m23_m7_i, B => m37_m6_0_a2_4_i, C => - \addr_data_vector[23]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa, C => - \addr_data_vector[6]\, Y => N_13_0); - - un1_address_m59 : AX1 - port map(A => N_13_0, B => m40_m6_0_a2_7, C => - \addr_data_vector[24]\, Y => \un1_address[24]\); - - \update_r[0]\ : DFN1P0 - port map(D => update_and_sel_7(0), CLK => HCLK_c, PRE => - HRESETn_c, Q => \update_r_i[0]\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - \state_RNIBABE[1]\ : NOR2A - port map(A => status_full_ack(0), B => N_85, Y => - \state_RNIBABE[1]_net_1\); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => m40_m6_0_a2_3, B => m40_m6_0_a2_2, C => - m40_m6_0_a2_4, Y => m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f0(17), S => - \state[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f0(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[7]\, B => - \addr_data_vector[8]\, C => N_13_0, Y => N_16_0); - - un1_address_m58 : AX1C - port map(A => \addr_data_vector[21]\, B => N_36_0, C => - \addr_data_vector[22]\, Y => \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - un1_address_m26 : OR3B - port map(A => \addr_data_vector[14]\, B => - \addr_data_vector[15]\, C => m23_m7_i, Y => N_27_0); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f0(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address_RNO_4[31]\ : NOR2B - port map(A => \addr_data_vector[28]\, B => - \addr_data_vector[29]\, Y => address_7_31_m6_e_2); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[3]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XOR2 - port map(A => N_46, B => \addr_data_vector[29]\, Y => - \un1_address[29]\); - - un1_address_m34 : XNOR2 - port map(A => N_34_0, B => \addr_data_vector[20]\, Y => - \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f0(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(0), B => N_85, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[3]_net_1\); - - un1_address_m23_m7_i_1 : NOR2B - port map(A => \addr_data_vector[8]\, B => - \addr_data_vector[9]\, Y => m23_m7_i_1); - - \address_RNIIVLA[0]\ : MX2C - port map(A => \addr_data_vector[0]\, B => - addr_data_vector_64, S => sel_data_0(1), Y => N_1279); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : AX1C - port map(A => \addr_data_vector[12]\, B => N_21_0, C => - \addr_data_vector[13]\, Y => N_55_0_i_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[7]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[5]_net_1\); - - un1_address_m3 : NOR3C - port map(A => \addr_data_vector[3]\, B => N_2, C => - \addr_data_vector[4]\, Y => N_4_0); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - \address_RNIDG94[21]\ : MX2C - port map(A => \addr_data_vector[21]\, B => - addr_data_vector_85, S => sel_data_1(1), Y => N_1314); - - un1_address_m25 : AX1 - port map(A => m23_m7_i, B => \addr_data_vector[14]\, C => - \addr_data_vector[15]\, Y => N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_1[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - \address_RNIFG94[22]\ : MX2C - port map(A => \addr_data_vector[22]\, B => - addr_data_vector_86, S => sel_data_1(1), Y => N_1315); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_7(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => \update_r[1]_net_1\); - - un1_address_m40_m6_0_a2_7 : NOR2A - port map(A => m40_m6_0_a2_6, B => m37_m6_0_a2_4_i, Y => - m40_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - \address_RNINHHB[4]\ : MX2C - port map(A => \addr_data_vector[4]\, B => - addr_data_vector_68, S => sel_data(1), Y => N_1325); - - un1_address_m57 : XOR2 - port map(A => N_36_0, B => \addr_data_vector[21]\, Y => - \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - \address_RNING94[26]\ : MX2C - port map(A => \addr_data_vector[26]\, B => - addr_data_vector_90, S => sel_data_1(1), Y => N_1305); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f0(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : XOR2 - port map(A => N_2, B => \addr_data_vector[3]\, Y => - N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[9]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f0(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f0(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m23_m7_i_5 : NOR3C - port map(A => m23_m7_i_2, B => m23_m7_i_1, C => m23_m7_i_3, - Y => m23_m7_i_5); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - \address_RNIRG94[28]\ : MX2C - port map(A => \addr_data_vector[28]\, B => - addr_data_vector_92, S => sel_data_1(1), Y => N_1307); - - status_full_err_RNO : OR2 - port map(A => un1_state_5_i_0, B => N_84, Y => N_64); - - \state_0[0]\ : DFN1C0 - port map(D => \state_RNIBABE[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f0(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[11]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - \state_RNIU3MB[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => un3_update_r, Y => - address_0_sqmuxa_0); - - un1_address_m56 : XNOR2 - port map(A => N_31_0, B => \addr_data_vector[18]\, Y => - \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f0(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f0(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f0(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[21]\); - - un1_address_m23_m7_i_3 : NOR3C - port map(A => \addr_data_vector[7]\, B => - \addr_data_vector[13]\, C => \addr_data_vector[12]\, Y - => m23_m7_i_3); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - un1_address_m62 : XOR2 - port map(A => N_44, B => \addr_data_vector[27]\, Y => - \un1_address[27]\); - - \address_RNIB894[13]\ : MX2C - port map(A => \addr_data_vector[13]\, B => - addr_data_vector_77, S => sel_data_1(1), Y => N_1320); - - un1_address_m32 : AX1 - port map(A => N_31_0, B => \addr_data_vector[18]\, C => - \addr_data_vector[19]\, Y => \un1_address[19]\); - - un1_address_m12_e : OR2B - port map(A => N_4_0, B => \addr_data_vector[5]\, Y => N_5_0); - - \address_RNO_5[31]\ : NOR2B - port map(A => \addr_data_vector[26]\, B => - \addr_data_vector[27]\, Y => address_7_31_m6_e_1); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => \state_RNO_0[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[17]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : AX1C - port map(A => \addr_data_vector[29]\, B => N_46, C => - \addr_data_vector[30]\, Y => \un1_address[30]\); - - un1_address_m35 : NOR2A - port map(A => \addr_data_vector[20]\, B => N_34_0, Y => - N_36_0); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[7]\, Y => - N_1_i_0); - - \address_RNINFMA[2]\ : MX2C - port map(A => \addr_data_vector[2]\, B => - addr_data_vector_66, S => sel_data_1(1), Y => N_1323); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[27]\); - - \state_RNO[3]\ : NOR2B - port map(A => \state[4]_net_1\, B => N_83_i, Y => - \state_RNO_1[3]\); - - un1_address_m21 : XOR2 - port map(A => N_21_0, B => \addr_data_vector[12]\, Y => - N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - \address_RNIGO94[30]\ : MX2C - port map(A => \addr_data_vector[30]\, B => - addr_data_vector_94, S => sel_data_0(1), Y => N_1295); - - un1_address_m55 : XNOR2 - port map(A => m23_m7_i, B => \addr_data_vector[14]\, Y => - N_56_0_i_0); - - \address_RNO[31]\ : MX2C - port map(A => \address_RNO_0_0[31]\, B => - \address_RNO_1_0[31]\, S => \address_RNO_2_0[31]\, Y => - \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f0(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - \update_r_RNIVJV4_0[0]\ : OR2 - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => \un1_state_12_3_0[4]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : OR2 - port map(A => \state[2]_net_1\, B => N_80, Y => - un1_state_11); - - \address_RNIJG94[24]\ : MX2C - port map(A => \addr_data_vector[24]\, B => - addr_data_vector_88, S => sel_data_1(1), Y => N_1303); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f0(1), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - \addr_data_vector[1]\); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_11, Q => status_full(0)); - - un1_address_m63 : AX1C - port map(A => \addr_data_vector[27]\, B => N_44, C => - \addr_data_vector[28]\, Y => \un1_address[28]\); - - un1_address_m33 : OR3B - port map(A => \addr_data_vector[18]\, B => - \addr_data_vector[19]\, C => N_31_0, Y => N_34_0); - - \state_RNIA6SP8_0[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => state7, Y => N_80); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f0(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[8]_net_1\); - - \address_RNIL894[18]\ : MX2C - port map(A => \addr_data_vector[18]\, B => - addr_data_vector_82, S => sel_data_1(1), Y => N_1311); - - un1_address_m53 : AX1 - port map(A => N_16_0, B => \addr_data_vector[9]\, C => - \addr_data_vector[10]\, Y => N_54_0_i_0); - - un1_address_m40_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[7]\, B => - \addr_data_vector[8]\, Y => m40_m6_0_a2_1); - - \address_RNO_3[31]\ : NOR3C - port map(A => \addr_data_vector[25]\, B => - \addr_data_vector[30]\, C => address_7_31_m6_e_1, Y => - address_7_31_m6_e_3); - - un1_address_m37_m6_0_a2_4_4 : NOR3C - port map(A => \addr_data_vector[14]\, B => - \addr_data_vector[22]\, C => \addr_data_vector[21]\, Y - => m37_m6_0_a2_4_4); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[3]_net_1\, C - => \state[2]_net_1\, Y => N_78); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f0(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - un1_address_m37_m6_0_a2_4_5 : NOR3C - port map(A => \addr_data_vector[16]\, B => - \addr_data_vector[15]\, C => m37_m6_0_a2_4_2, Y => - m37_m6_0_a2_4_5); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_dma_send_16word is - - port( un7_dmain : out std_logic_vector(66 to 66); - data_address : in std_logic_vector(31 downto 0); - Store : out std_logic; - Fault : in std_logic; - un1_data_send_ok : out std_logic; - Request_0 : in std_logic; - N_1011 : out std_logic; - Lock_0 : in std_logic; - N_1013 : out std_logic; - N_957 : out std_logic; - N_956 : out std_logic; - N_955 : out std_logic; - N_954 : out std_logic; - N_953 : out std_logic; - N_952 : out std_logic; - N_951 : out std_logic; - N_964 : out std_logic; - N_963 : out std_logic; - N_962 : out std_logic; - N_961 : out std_logic; - N_960 : out std_logic; - time_select : in std_logic; - N_959 : out std_logic; - N_958 : out std_logic; - N_971 : out std_logic; - N_970 : out std_logic; - N_969 : out std_logic; - N_968 : out std_logic; - N_967 : out std_logic; - N_966 : out std_logic; - N_965 : out std_logic; - N_978 : out std_logic; - N_977 : out std_logic; - N_976 : out std_logic; - N_975 : out std_logic; - N_974 : out std_logic; - N_973 : out std_logic; - N_972 : out std_logic; - N_950 : out std_logic; - N_949 : out std_logic; - N_948 : out std_logic; - time_select_0 : in std_logic; - N_947 : out std_logic; - N_249 : out std_logic; - Grant : in std_logic; - Ready : in std_logic; - data_send : in std_logic; - OKAY : in std_logic; - N_200 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_dma_send_16word; - -architecture DEF_ARCH of lpp_dma_send_16word is - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[5]_net_1\, N_4, N_198_0, N_509, N_344, - N_154_0, N_241, N_235, N_242, N_202_0, m74_0, - \data_counter[30]_net_1\, \data_counter[29]_net_1\, - ADD_32x32_fast_I129_un1_Y_14, ADD_32x32_fast_I129_un1_Y_9, - ADD_32x32_fast_I129_un1_Y_8, ADD_32x32_fast_I129_un1_Y_13, - ADD_32x32_fast_I129_un1_Y_5, ADD_32x32_fast_I129_un1_Y_4, - ADD_32x32_fast_I129_un1_Y_11, \grant_counter[27]_net_1\, - \grant_counter[26]_net_1\, ADD_32x32_fast_I129_un1_Y_7, - \grant_counter[19]_net_1\, \grant_counter[18]_net_1\, - ADD_32x32_fast_I129_un1_Y_3, \grant_counter[15]_net_1\, - \grant_counter[14]_net_1\, ADD_32x32_fast_I129_un1_Y_1, - \grant_counter[28]_net_1\, \grant_counter[29]_net_1\, - \grant_counter[24]_net_1\, \grant_counter[25]_net_1\, - \grant_counter[22]_net_1\, \grant_counter[23]_net_1\, - \grant_counter[20]_net_1\, \grant_counter[21]_net_1\, - \grant_counter[16]_net_1\, \grant_counter[17]_net_1\, - m43_m6_0_a2_6, \grant_counter[13]_net_1\, - \grant_counter[12]_net_1\, m43_m6_0_a2_4, m43_m6_0_a2_5, - \grant_counter[9]_net_1\, \grant_counter[8]_net_1\, - m43_m6_0_a2_2, \grant_counter[7]_net_1\, - \grant_counter[6]_net_1\, \grant_counter[10]_net_1\, - \grant_counter[11]_net_1\, \data_counter_8_i_0[0]\, N_508, - N_338_1, N_337, \grant_counter_0_i_0[4]\, N_246, - un1_hresetn_inv_i_0, ADD_32x32_fast_I129_un1_Y_14_0, - ADD_32x32_fast_I129_un1_Y_9_0, - ADD_32x32_fast_I129_un1_Y_8_0, - ADD_32x32_fast_I129_un1_Y_13_0, - ADD_32x32_fast_I129_un1_Y_5_0, - ADD_32x32_fast_I129_un1_Y_4_0, - ADD_32x32_fast_I129_un1_Y_11_0, \data_counter[27]_net_1\, - \data_counter[26]_net_1\, ADD_32x32_fast_I129_un1_Y_7_0, - \data_counter[19]_net_1\, \data_counter[18]_net_1\, - ADD_32x32_fast_I129_un1_Y_3_0, \data_counter[15]_net_1\, - \data_counter[14]_net_1\, ADD_32x32_fast_I129_un1_Y_1_0, - \data_counter[28]_net_1\, \data_counter[24]_net_1\, - \data_counter[25]_net_1\, \data_counter[22]_net_1\, - \data_counter[23]_net_1\, \data_counter[20]_net_1\, - \data_counter[21]_net_1\, \data_counter[16]_net_1\, - \data_counter[17]_net_1\, m28_m6_5, \state[3]_net_1\, - m28_m6_4, m28_m6_1, m28_m6_0, m28_m6_2, - \data_counter[0]_net_1\, \state[0]_net_1\, - \data_counter[2]_net_1\, \data_counter[3]_net_1\, - \data_counter[13]_net_1\, \data_counter[1]_net_1\, - \grant_counter_0_0_0[0]\, \grant_counter[0]_net_1\, - un1_state_2_i_o2_0, \state[1]_net_1\, \state[2]_net_1\, - \state_ns_i_a2_i_0_0[0]\, un1_state_7_i_a4_0_1, N_518_1, - un1_state_5_i_o2_30, un1_state_5_i_o2_25, - un1_state_5_i_o2_24, un1_state_5_i_o2_29, - un1_state_5_i_o2_21, un1_state_5_i_o2_20, - un1_state_5_i_o2_27, un1_state_5_i_o2_13, - un1_state_5_i_o2_12, un1_state_5_i_o2_23, - un1_state_5_i_o2_5, un1_state_5_i_o2_4, - un1_state_5_i_o2_19, un1_state_5_i_o2_1, - un1_state_5_i_o2_0, un1_state_5_i_o2_17, - un1_state_5_i_o2_15, un1_state_5_i_o2_11, - un1_state_5_i_o2_9, un1_state_5_i_o2_7, - un1_state_5_i_o2_3, \data_counter[5]_net_1\, - \data_counter[4]_net_1\, \data_counter[10]_net_1\, - \data_counter[11]_net_1\, \data_counter[8]_net_1\, - \data_counter[9]_net_1\, \data_counter[6]_net_1\, - \data_counter[7]_net_1\, \data_counter[31]_net_1\, - \data_counter[12]_net_1\, \state_ns_i_a2_0_i_o2_29[3]\, - \state_ns_i_a2_0_i_o2_21[3]\, - \state_ns_i_a2_0_i_o2_20[3]\, - \state_ns_i_a2_0_i_o2_27[3]\, - \state_ns_i_a2_0_i_o2_22[3]\, - \state_ns_i_a2_0_i_o2_23[3]\, - \state_ns_i_a2_0_i_o2_25[3]\, \state_ns_i_a2_0_i_o2_5[3]\, - \state_ns_i_a2_0_i_o2_4[3]\, \state_ns_i_a2_0_i_o2_19[3]\, - \state_ns_i_a2_0_i_o2_24[3]\, \state_ns_i_a2_0_i_o2_3[3]\, - \state_ns_i_a2_0_i_o2_2[3]\, \state_ns_i_a2_0_i_o2_16[3]\, - \state_ns_i_a2_0_i_o2_15[3]\, - \state_ns_i_a2_0_i_o2_13[3]\, - \state_ns_i_a2_0_i_o2_11[3]\, \state_ns_i_a2_0_i_o2_9[3]\, - \state_ns_i_a2_0_i_o2_6[3]\, \state_ns_i_a2_0_i_o2_7[3]\, - \state_ns_i_a2_0_i_o2_1[3]\, \grant_counter[4]_net_1\, - \grant_counter[31]_net_1\, \grant_counter[2]_net_1\, - \grant_counter[3]_net_1\, \grant_counter[1]_net_1\, - \grant_counter[5]_net_1\, \grant_counter[30]_net_1\, - m27_m6_0_a2_4_5, m27_m6_0_a2_4_2, m27_m6_0_a2_4_4, - m27_m6_0_a2_4_3, N_75, N_72, I129_un1_Y, N623, - \grant_counter_RNO[0]_net_1\, N_89, N_19_0, N_346, N_243, - \state[4]_net_1\, N_194_i_0, N_522, Burst, N_526, N_339, - N_186, N_336, \un1_state_4_i_i[31]\, N_75_0, N_72_0, - m27_m6_0_a2_4, N_44, N_21_0, N623_0, N_28_0, N_19_0_0, - N_22_0, N_23_0, N_24_0, N_25_0, N_26_0, N_27_0, N_28_0_0, - \un1_hresetn_inv_2_i[26]\, \un1_hresetn_inv_2_i[15]\, - N_48, \un1_hresetn_inv_2_i[13]\, N_52, - \un1_hresetn_inv_2_i[11]\, N_56, \un1_hresetn_inv_2_i[9]\, - N_60, \un1_hresetn_inv_2_i[7]\, N_64, - \un1_hresetn_inv_2_i[5]\, N_68, \un1_hresetn_inv_2_i[3]\, - N_23_0_0, N_22_0_0, N_24_0_0, N_25_0_0, N_26_0_0, - N_27_0_0, N_45, N_46, N_48_0, N_50, N_52_0, N_54, N_56_0, - N_58, N_60_0, N_62, N_64_0, N_66, N_68_0, - \un1_state_4_i[17]\, \data_counter_8[7]\, - \data_counter_8[8]\, \data_counter_8[9]\, - \data_counter_8[10]\, \data_counter_8[11]\, - \data_counter_8[12]\, \data_counter_8[13]\, - \data_counter_8[14]\, \data_counter_8[15]\, - \data_counter_8[16]\, \data_counter_8[17]\, - \data_counter_8[18]\, \data_counter_8[19]\, - \data_counter_8[20]\, \data_counter_8[21]\, N_198, - \data_counter_8[22]\, \data_counter_8[23]\, - \data_counter_8[24]\, \data_counter_8[25]\, - \data_counter_8[26]\, N_13, N_15, N_17, N_19, N_21, N_23, - N_25, N_27, N_29, N_31, N_33, N_35, N_43, N_45_0, N_47, - N_49, N_51, N_53, N_55, \state[5]_net_1\, N_57, N_59, - N_61, N_63, N_65, N_67, N_69, N_71, N_73, N_75_1, N_77, - N_79, N_81, N_91, N_93, N_95, N_97, N_99, N_101, N_103, - N_105, N_107, N_109, N_111, N_113, N_115, N_117, N_119, - N_202, N_121, N_123, N_125, N_127, N_129, N_131, N_133, - N_135, N_137, N_139, N_141, N_143, \N_200\, \Address[0]\, - \Address[1]\, \Address[2]\, \Address[3]\, \Address[25]\, - \Address[26]\, \Address[27]\, \Address[28]\, - \Address[29]\, \Address[30]\, \Address[31]\, - \Address[18]\, \Address[19]\, \Address[20]\, - \Address[21]\, \Address[22]\, \Address[23]\, - \Address[24]\, \Address[11]\, \Address[12]\, - \Address[13]\, \Address[14]\, \Address[15]\, - \Address[16]\, \Address[17]\, \Address[4]\, \Address[5]\, - \Address[6]\, \Address[7]\, \Address[8]\, \Address[9]\, - \Address[10]\, Lock, Request, N_84, Request_5, N_32_0_i_0, - N_17_0, \grant_counter_RNO[2]_net_1\, N_513, N_146, N_516, - N_151, data_send_ok, data_send_ko, - \grant_counter_RNO[3]_net_1\, N_33_0_i_0, - \grant_counter_RNO[1]_net_1\, N_31_0_i_0, - \state_RNO_0[0]_net_1\, \state_RNO[0]_net_1\, - \state_RNO[3]_net_1\, N_154, N_192, \un1_state_4_i[28]\, - N_190, \un1_state_4_i[29]\, N_188, \un1_state_4_i[30]\, - N_156, N_348, \data_counter_8[31]\, \data_counter_8[30]\, - \un1_state_4_i[1]\, \data_counter_8[29]\, - \data_counter_8[28]\, N_70, \data_counter_8[27]\, - \data_counter_8[6]\, N_21_0_0, \data_counter_8[5]\, - N_20_0, \data_counter_8[4]\, N_510, N_18_0, N_16_0, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - N_200 <= \N_200\; - - un1_hresetn_inv_2_m66 : AX1E - port map(A => \grant_counter[25]_net_1\, B => N_64, C => - \grant_counter[26]_net_1\, Y => \un1_hresetn_inv_2_i[5]\); - - \state_RNIK8SG_1[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => OKAY, Y => N_249); - - \DMAIn.Address[7]\ : DFN1E1C0 - port map(D => N_27, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[7]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNO[0]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[0]_net_1\); - - un1_state_4_m28_m6_4 : NOR3C - port map(A => m28_m6_1, B => m28_m6_0, C => m28_m6_2, Y => - m28_m6_4); - - \data_counter_RNIMF78[4]\ : NOR3A - port map(A => un1_state_5_i_o2_3, B => - \data_counter[5]_net_1\, C => \data_counter[4]_net_1\, Y - => un1_state_5_i_o2_17); - - \data_counter_RNO[31]\ : XA1C - port map(A => \data_counter[31]_net_1\, B => N_75_0, C => - N_198, Y => \data_counter_8[31]\); - - un1_state_4_m51 : NOR2B - port map(A => N_50, B => \data_counter[18]_net_1\, Y => - N_52_0); - - \data_counter_RNO[2]\ : AOI1B - port map(A => \un1_state_4_i[29]\, B => N_344, C => N_509, - Y => N_190); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_3 : NOR2B - port map(A => \grant_counter[20]_net_1\, B => - \grant_counter[21]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_3); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y : NOR2B - port map(A => ADD_32x32_fast_I129_un1_Y_14, B => N623, Y - => I129_un1_Y); - - \data_counter_RNO[18]\ : XA1B - port map(A => \data_counter[18]_net_1\, B => N_50, C => - N_198_0, Y => \data_counter_8[18]\); - - un1_state_4_m17 : NOR3C - port map(A => \data_counter[1]_net_1\, B => N_16_0, C => - \data_counter[2]_net_1\, Y => N_18_0); - - \grant_counter_RNO[5]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[26]\, Y - => N_91); - - un1_state_4_m49 : NOR2B - port map(A => N_48_0, B => \data_counter[17]_net_1\, Y => - N_50); - - un1_state_4_m28_m6_2 : NOR2A - port map(A => \data_counter[0]_net_1\, B => - \state[0]_net_1\, Y => m28_m6_2); - - \DMAIn.Address_RNIJIRJ[25]\ : MX2 - port map(A => \Address[25]\, B => data_address(25), S => - time_select_0, Y => N_972); - - \DMAIn.Address_RNI54FJ[14]\ : MX2 - port map(A => \Address[14]\, B => data_address(14), S => - time_select, Y => N_961); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_5 : NOR2B - port map(A => \data_counter[24]_net_1\, B => - \data_counter[25]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_5_0); - - \grant_counter_RNO[26]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[5]\, Y => - N_133); - - \DMAIn.Address_RNO[20]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(20), Y - => N_59); - - \DMAIn.Address_RNIEF261[5]\ : MX2 - port map(A => \Address[5]\, B => data_address(5), S => - time_select, Y => N_952); - - \grant_counter[0]\ : DFN1 - port map(D => \grant_counter_RNO[0]_net_1\, CLK => HCLK_c, - Q => \grant_counter[0]_net_1\); - - \DMAIn.Address[6]\ : DFN1E1C0 - port map(D => N_25, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[6]\); - - \DMAIn.Address_RNI3IKI[13]\ : MX2 - port map(A => \Address[13]\, B => data_address(13), S => - time_select, Y => N_960); - - \DMAIn.Address_RNIL0M41[0]\ : MX2 - port map(A => \Address[0]\, B => data_address(0), S => - time_select_0, Y => N_947); - - un1_state_4_m53 : NOR2B - port map(A => N_52_0, B => \data_counter[19]_net_1\, Y => - N_54); - - \grant_counter[20]\ : DFN1 - port map(D => N_121, CLK => HCLK_c, Q => - \grant_counter[20]_net_1\); - - \DMAIn.Address_RNO[27]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(27), Y - => N_73); - - un1_state_4_m27_m6_0_a2_4_4 : NOR3C - port map(A => \data_counter[4]_net_1\, B => - \data_counter[12]_net_1\, C => \data_counter[11]_net_1\, - Y => m27_m6_0_a2_4_4); - - \data_counter_RNO[14]\ : NOR2 - port map(A => \un1_state_4_i[17]\, B => N_198_0, Y => - \data_counter_8[14]\); - - \data_counter_RNO[21]\ : XA1B - port map(A => \data_counter[21]_net_1\, B => N_56_0, C => - N_198, Y => \data_counter_8[21]\); - - \data_counter_RNIN6PF[31]\ : NOR2 - port map(A => \data_counter[31]_net_1\, B => - \data_counter[12]_net_1\, Y => un1_state_5_i_o2_0); - - \DMAIn.Address[2]\ : DFN1E1C0 - port map(D => N_17, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[2]\); - - \DMAIn.Address[28]\ : DFN1E1C0 - port map(D => N_75_1, CLK => HCLK_c, CLR => HRESETn_c, E - => N_154, Q => \Address[28]\); - - un1_state_4_m19 : NOR2B - port map(A => N_19_0_0, B => \data_counter[4]_net_1\, Y => - N_20_0); - - \grant_counter[26]\ : DFN1 - port map(D => N_133, CLK => HCLK_c, Q => - \grant_counter[26]_net_1\); - - \grant_counter[29]\ : DFN1 - port map(D => N_139, CLK => HCLK_c, Q => - \grant_counter[29]_net_1\); - - \grant_counter[1]\ : DFN1 - port map(D => \grant_counter_RNO[1]_net_1\, CLK => HCLK_c, - Q => \grant_counter[1]_net_1\); - - \data_counter[16]\ : DFN1C0 - port map(D => \data_counter_8[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[16]_net_1\); - - \data_counter[13]\ : DFN1C0 - port map(D => \data_counter_8[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[13]_net_1\); - - un1_state_4_m74 : OR2B - port map(A => m74_0, B => N_72_0, Y => N_75_0); - - un1_hresetn_inv_2_m21 : NOR2B - port map(A => N_21_0, B => \grant_counter[6]_net_1\, Y => - N_22_0); - - \state_0[5]\ : DFN1P0 - port map(D => N_4, CLK => HCLK_c, PRE => HRESETn_c, Q => - \state_0[5]_net_1\); - - \DMAIn.Address[29]\ : DFN1E1C0 - port map(D => N_77, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[29]\); - - \state_RNIV6P14[3]\ : OR2A - port map(A => N_526, B => N_242, Y => N_156); - - \grant_counter_RNO[3]\ : AO1 - port map(A => N_33_0_i_0, B => N_202, C => N_513, Y => - \grant_counter_RNO[3]_net_1\); - - \grant_counter_RNIP43F[6]\ : NOR2 - port map(A => \grant_counter[6]_net_1\, B => - \grant_counter[7]_net_1\, Y => - \state_ns_i_a2_0_i_o2_4[3]\); - - un1_hresetn_inv_2_m20 : NOR3C - port map(A => \grant_counter[4]_net_1\, B => N_19_0, C => - \grant_counter[5]_net_1\, Y => N_21_0); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_9 : NOR3C - port map(A => \data_counter[19]_net_1\, B => - \data_counter[18]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_3_0, Y => - ADD_32x32_fast_I129_un1_Y_9_0); - - \grant_counter_RNIC1Q[18]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_11[3]\, B => - \grant_counter[19]_net_1\, C => \grant_counter[18]_net_1\, - Y => \state_ns_i_a2_0_i_o2_21[3]\); - - \grant_counter_RNIBSC[10]\ : NOR2 - port map(A => \grant_counter[10]_net_1\, B => - \grant_counter[11]_net_1\, Y => - \state_ns_i_a2_0_i_o2_6[3]\); - - \grant_counter_RNO[16]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[15]\, Y - => N_113); - - un1_hresetn_inv_2_m23 : NOR2B - port map(A => N_23_0, B => \grant_counter[8]_net_1\, Y => - N_24_0); - - \data_counter[11]\ : DFN1C0 - port map(D => \data_counter_8[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[11]_net_1\); - - \data_counter_RNIMDJV[22]\ : NOR3A - port map(A => un1_state_5_i_o2_11, B => - \data_counter[23]_net_1\, C => \data_counter[22]_net_1\, - Y => un1_state_5_i_o2_21); - - \data_counter_RNI4TP71[4]\ : NOR3C - port map(A => un1_state_5_i_o2_1, B => un1_state_5_i_o2_0, - C => un1_state_5_i_o2_17, Y => un1_state_5_i_o2_24); - - \data_counter[8]\ : DFN1C0 - port map(D => \data_counter_8[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[8]_net_1\); - - \grant_counter_RNO[4]\ : XA1B - port map(A => \grant_counter[4]_net_1\, B => N_19_0, C => - \grant_counter_0_i_0[4]\, Y => N_89); - - \DMAIn.Address[1]\ : DFN1E1C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[1]\); - - \DMAIn.Address[13]\ : DFN1E1C0 - port map(D => N_45_0, CLK => HCLK_c, CLR => HRESETn_c, E - => N_154_0, Q => \Address[13]\); - - \state_RNIRGVK7[0]\ : OR2A - port map(A => N_348, B => N_235, Y => N_344); - - \state_RNI97HH[3]\ : MX2B - port map(A => \state[5]_net_1\, B => Fault, S => - \state[3]_net_1\, Y => N_242); - - \grant_counter_RNIH42F[3]\ : NOR2B - port map(A => \grant_counter[2]_net_1\, B => - \grant_counter[3]_net_1\, Y => - \state_ns_i_a2_0_i_o2_3[3]\); - - \DMAIn.Address[30]\ : DFN1E1C0 - port map(D => N_79, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[30]\); - - \DMAIn.Address_RNO[0]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(0), Y - => N_13); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[14]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_1, Y => - ADD_32x32_fast_I129_un1_Y_8); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_5 : NOR2B - port map(A => \grant_counter[24]_net_1\, B => - \grant_counter[25]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_5); - - un1_hresetn_inv_2_m26 : NOR2B - port map(A => N_26_0, B => \grant_counter[11]_net_1\, Y => - N_27_0); - - \DMAIn.Address_RNO[10]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(10), Y - => N_33); - - \DMAIn.Address_RNO[5]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(5), Y - => N_23); - - send_ok : DFN1E1C0 - port map(D => \state[0]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_146, Q => data_send_ok); - - \grant_counter_RNO[9]\ : XA1 - port map(A => \grant_counter[9]_net_1\, B => N_24_0, C => - N_202_0, Y => N_99); - - \data_counter_RNI5VQF[28]\ : NOR2 - port map(A => \data_counter[28]_net_1\, B => - \data_counter[29]_net_1\, Y => un1_state_5_i_o2_13); - - \DMAIn.Address[31]\ : DFN1E1C0 - port map(D => N_81, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[31]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_11 : NOR3C - port map(A => \grant_counter[27]_net_1\, B => - \grant_counter[26]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_7, Y => - ADD_32x32_fast_I129_un1_Y_11); - - \grant_counter_RNIC1GF[31]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_1[3]\, B => - \grant_counter[4]_net_1\, C => \grant_counter[31]_net_1\, - Y => \state_ns_i_a2_0_i_o2_16[3]\); - - \DMAIn.Address_RNIMP5I[11]\ : MX2 - port map(A => \Address[11]\, B => data_address(11), S => - time_select_0, Y => N_958); - - \grant_counter[25]\ : DFN1 - port map(D => N_131, CLK => HCLK_c, Q => - \grant_counter[25]_net_1\); - - \DMAIn.Address_RNO[17]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(17), Y - => N_53); - - un1_state_4_m18 : NOR2B - port map(A => N_18_0, B => \data_counter[3]_net_1\, Y => - N_19_0_0); - - un1_state_4_m55 : NOR2B - port map(A => N_54, B => \data_counter[20]_net_1\, Y => - N_56_0); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \data_counter[16]_net_1\, B => - \data_counter[17]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_1_0); - - un1_hresetn_inv_2_m71 : NOR3C - port map(A => \grant_counter[27]_net_1\, B => N_68, C => - \grant_counter[28]_net_1\, Y => N_72); - - \state[4]\ : DFN1C0 - port map(D => N_84, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[4]_net_1\); - - \grant_counter_RNO[6]\ : XA1 - port map(A => \grant_counter[6]_net_1\, B => N_21_0, C => - N_202_0, Y => N_93); - - \data_counter_RNO[22]\ : XA1B - port map(A => \data_counter[22]_net_1\, B => N_58, C => - N_198, Y => \data_counter_8[22]\); - - un1_hresetn_inv_2_m70 : AX1E - port map(A => \grant_counter[27]_net_1\, B => N_68, C => - \grant_counter[28]_net_1\, Y => \un1_hresetn_inv_2_i[3]\); - - \DMAIn.Address_RNO[28]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(28), Y - => N_75_1); - - \DMAIn.Address_RNI09N41[2]\ : MX2 - port map(A => \Address[2]\, B => data_address(2), S => - time_select_0, Y => N_949); - - \data_counter_RNITN34[6]\ : NOR2 - port map(A => \data_counter[6]_net_1\, B => - \data_counter[7]_net_1\, Y => un1_state_5_i_o2_3); - - \DMAIn.Address_RNIUHKI[12]\ : MX2 - port map(A => \Address[12]\, B => data_address(12), S => - time_select, Y => N_959); - - \data_counter_RNI1FQF[26]\ : NOR2 - port map(A => \data_counter[26]_net_1\, B => - \data_counter[27]_net_1\, Y => un1_state_5_i_o2_12); - - \grant_counter_RNO[20]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[11]\, Y => - N_121); - - un1_state_4_m21 : NOR2B - port map(A => N_21_0_0, B => \data_counter[6]_net_1\, Y => - N_22_0_0); - - \grant_counter_RNITK3F[8]\ : NOR2 - port map(A => \grant_counter[8]_net_1\, B => - \grant_counter[9]_net_1\, Y => - \state_ns_i_a2_0_i_o2_5[3]\); - - un1_hresetn_inv_2_m59 : NOR3C - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - \grant_counter[22]_net_1\, Y => N_60); - - \data_counter_RNIJJIB3[4]\ : NOR3B - port map(A => un1_state_5_i_o2_25, B => un1_state_5_i_o2_24, - C => OKAY, Y => un1_state_5_i_o2_30); - - \grant_counter_RNO[22]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[9]\, Y => - N_125); - - un1_state_4_m22 : NOR2B - port map(A => N_22_0_0, B => \data_counter[7]_net_1\, Y => - N_23_0_0); - - \state_RNI6D91[2]\ : OR2 - port map(A => \state[4]_net_1\, B => \state[2]_net_1\, Y - => N_518_1); - - \data_counter[3]\ : DFN1C0 - port map(D => N_192, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_counter[3]_net_1\); - - \DMAIn.Address_RNI9IRJ[23]\ : MX2 - port map(A => \Address[23]\, B => data_address(23), S => - time_select_0, Y => N_970); - - \state[5]\ : DFN1P0 - port map(D => N_4, CLK => HCLK_c, PRE => HRESETn_c, Q => - \state[5]_net_1\); - - \grant_counter_RNO[30]\ : XA1 - port map(A => \grant_counter[30]_net_1\, B => I129_un1_Y, C - => N_202, Y => N_141); - - \data_counter_RNO[8]\ : XA1B - port map(A => \data_counter[8]_net_1\, B => N_23_0_0, C => - N_198_0, Y => \data_counter_8[8]\); - - \data_counter[28]\ : DFN1C0 - port map(D => \data_counter_8[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[28]_net_1\); - - \state_RNI9EI2[0]\ : OR2 - port map(A => N_518_1, B => N_338_1, Y => N_516); - - \data_counter[10]\ : DFN1C0 - port map(D => \data_counter_8[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[10]_net_1\); - - \data_counter_RNO[13]\ : XA1C - port map(A => \data_counter[13]_net_1\, B => N_28_0, C => - N_198_0, Y => \data_counter_8[13]\); - - \data_counter[12]\ : DFN1C0 - port map(D => \data_counter_8[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[12]_net_1\); - - \data_counter[24]\ : DFN1C0 - port map(D => \data_counter_8[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[24]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \DMAIn.Address_RNO[26]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(26), Y - => N_71); - - un1_state_4_m23 : NOR2B - port map(A => N_23_0_0, B => \data_counter[8]_net_1\, Y => - N_24_0_0); - - un1_hresetn_inv_2_m47 : NOR3C - port map(A => \grant_counter[15]_net_1\, B => N_44, C => - \grant_counter[16]_net_1\, Y => N_48); - - \DMAIn.Address_RNO[23]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(23), Y - => N_65); - - \DMAIn.Address_RNIOUQJ[19]\ : MX2 - port map(A => \Address[19]\, B => data_address(19), S => - time_select_0, Y => N_966); - - \DMAIn.Address[12]\ : DFN1E1C0 - port map(D => N_43, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[12]\); - - \data_counter_RNIQ8473[22]\ : NOR3C - port map(A => un1_state_5_i_o2_21, B => un1_state_5_i_o2_20, - C => un1_state_5_i_o2_27, Y => un1_state_5_i_o2_29); - - \data_counter[27]\ : DFN1C0 - port map(D => \data_counter_8[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[27]_net_1\); - - \grant_counter_RNO[1]\ : AO1 - port map(A => N_31_0_i_0, B => N_202, C => N_513, Y => - \grant_counter_RNO[1]_net_1\); - - \DMAIn.Address[5]\ : DFN1E1C0 - port map(D => N_23, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_counter_RNO[10]\ : XA1B - port map(A => \data_counter[10]_net_1\, B => N_25_0_0, C - => N_198_0, Y => \data_counter_8[10]\); - - \data_counter_RNICTS71[2]\ : NOR3C - port map(A => un1_state_5_i_o2_13, B => un1_state_5_i_o2_12, - C => un1_state_5_i_o2_23, Y => un1_state_5_i_o2_27); - - \grant_counter_RNO[28]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[3]\, Y => - N_137); - - \grant_counter[17]\ : DFN1 - port map(D => N_115, CLK => HCLK_c, Q => - \grant_counter[17]_net_1\); - - \grant_counter_RNINSC[16]\ : NOR2 - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[17]_net_1\, Y => - \state_ns_i_a2_0_i_o2_9[3]\); - - \data_counter_RNO[27]\ : XA1B - port map(A => \data_counter[27]_net_1\, B => N_68_0, C => - N_198, Y => \data_counter_8[27]\); - - \grant_counter_RNO[24]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[7]\, Y => - N_129); - - \data_counter[1]\ : DFN1C0 - port map(D => N_188, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_counter[1]_net_1\); - - \grant_counter_RNO[10]\ : XA1 - port map(A => \grant_counter[10]_net_1\, B => N_25_0, C => - N_202_0, Y => N_101); - - \grant_counter[30]\ : DFN1 - port map(D => N_141, CLK => HCLK_c, Q => - \grant_counter[30]_net_1\); - - \grant_counter[9]\ : DFN1 - port map(D => N_99, CLK => HCLK_c, Q => - \grant_counter[9]_net_1\); - - \data_counter_RNO_1[0]\ : NOR3 - port map(A => N_235, B => \state[0]_net_1\, C => N_508, Y - => N_339); - - \data_counter_RNO[6]\ : XA1B - port map(A => \data_counter[6]_net_1\, B => N_21_0_0, C => - N_198, Y => \data_counter_8[6]\); - - \state_RNI1BT21[3]\ : OR2A - port map(A => N_348, B => \state[3]_net_1\, Y => N_509); - - \DMAIn.Address_RNO[30]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(30), Y - => N_79); - - \grant_counter_RNIFSC[12]\ : NOR2 - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[13]_net_1\, Y => - \state_ns_i_a2_0_i_o2_7[3]\); - - un1_state_4_m57 : NOR2B - port map(A => N_56_0, B => \data_counter[21]_net_1\, Y => - N_58); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_7 : NOR2B - port map(A => \grant_counter[28]_net_1\, B => - \grant_counter[29]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_7); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \grant_counter[22]_net_1\, B => - \grant_counter[23]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_4); - - \grant_counter_RNO[12]\ : XA1 - port map(A => \grant_counter[12]_net_1\, B => N_27_0, C => - N_202_0, Y => N_105); - - \DMAIn.Address_RNO[8]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(8), Y - => N_29); - - \DMAIn.Address[9]\ : DFN1E1C0 - port map(D => N_31, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[9]\); - - un1_state_4_m61 : NOR2B - port map(A => N_60_0, B => \data_counter[23]_net_1\, Y => - N_62); - - un1_state_4_m26 : OR2B - port map(A => N_26_0_0, B => \data_counter[11]_net_1\, Y - => N_27_0_0); - - \grant_counter[18]\ : DFN1 - port map(D => N_117, CLK => HCLK_c, Q => - \grant_counter[18]_net_1\); - - \data_counter_RNO[4]\ : XA1B - port map(A => \data_counter[4]_net_1\, B => N_19_0_0, C => - N_198, Y => \data_counter_8[4]\); - - \data_counter[29]\ : DFN1C0 - port map(D => \data_counter_8[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[29]_net_1\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[17]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_1); - - \DMAIn.Address_RNO[18]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(18), Y - => N_55); - - \DMAIn.Address[10]\ : DFN1E1C0 - port map(D => N_33, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[10]\); - - un1_state_4_m31 : AX1E - port map(A => \data_counter[1]_net_1\, B => N_16_0, C => - \data_counter[2]_net_1\, Y => \un1_state_4_i[29]\); - - \DMAIn.Address_RNO[29]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(29), Y - => N_77); - - \state_RNI1E9S2[3]\ : OAI1 - port map(A => N_246, B => un1_state_7_i_a4_0_1, C => N_516, - Y => N_146); - - un1_state_4_m32 : XNOR2 - port map(A => N_18_0, B => \data_counter[3]_net_1\, Y => - \un1_state_4_i[28]\); - - \DMAIn.Address_RNID6SJ[31]\ : MX2 - port map(A => \Address[31]\, B => data_address(31), S => - time_select_0, Y => N_978); - - \data_counter[2]\ : DFN1C0 - port map(D => N_190, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_counter[2]_net_1\); - - un1_hresetn_inv_2_m67 : NOR3C - port map(A => \grant_counter[25]_net_1\, B => N_64, C => - \grant_counter[26]_net_1\, Y => N_68); - - un1_hresetn_inv_2_m43_m6_0_a2_2 : NOR2B - port map(A => \grant_counter[10]_net_1\, B => - \grant_counter[11]_net_1\, Y => m43_m6_0_a2_2); - - \DMAIn.Address_RNI86SJ[30]\ : MX2 - port map(A => \Address[30]\, B => data_address(30), S => - time_select_0, Y => N_977); - - \DMAIn.Address[11]\ : DFN1E1C0 - port map(D => N_35, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[11]\); - - un1_hresetn_inv_2_m34 : AX1E - port map(A => \grant_counter[4]_net_1\, B => N_19_0, C => - \grant_counter[5]_net_1\, Y => \un1_hresetn_inv_2_i[26]\); - - \state_RNIR8B01[4]\ : OR2B - port map(A => \state[4]_net_1\, B => Grant, Y => \N_200\); - - \grant_counter[21]\ : DFN1 - port map(D => N_123, CLK => HCLK_c, Q => - \grant_counter[21]_net_1\); - - \DMAIn.Address_RNI6EA51[9]\ : MX2 - port map(A => \Address[9]\, B => data_address(9), S => - time_select, Y => N_956); - - \DMAIn.Address_RNI2JRJ[28]\ : MX2C - port map(A => \Address[28]\, B => data_address(28), S => - time_select_0, Y => N_975); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_7 : NOR2B - port map(A => \data_counter[28]_net_1\, B => - \data_counter[29]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_7_0); - - \grant_counter[22]\ : DFN1 - port map(D => N_125, CLK => HCLK_c, Q => - \grant_counter[22]_net_1\); - - \DMAIn.Address[14]\ : DFN1E1C0 - port map(D => N_47, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[14]\); - - \DMAIn.Burst_RNI9478\ : OR2A - port map(A => Burst, B => time_select, Y => un7_dmain(66)); - - un1_state_4_m63 : NOR2B - port map(A => N_62, B => \data_counter[24]_net_1\, Y => - N_64_0); - - un1_state_4_m44 : AX1E - port map(A => \data_counter[14]_net_1\, B => N623_0, C => - \data_counter[15]_net_1\, Y => N_45); - - \state_RNISRSN8[3]\ : OR2B - port map(A => N_509, B => N_344, Y => N_198); - - \DMAIn.Address_RNITB461[8]\ : MX2 - port map(A => \Address[8]\, B => data_address(8), S => - time_select, Y => N_955); - - \state_RNO_0[0]\ : NOR2A - port map(A => \state[0]_net_1\, B => Ready, Y => - \state_RNO_0[0]_net_1\); - - \grant_counter_RNO[18]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[13]\, Y - => N_117); - - \data_counter[0]\ : DFN1C0 - port map(D => N_186, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_counter[0]_net_1\); - - un1_hresetn_inv_2_m51 : NOR3C - port map(A => \grant_counter[17]_net_1\, B => N_48, C => - \grant_counter[18]_net_1\, Y => N_52); - - \grant_counter_RNO[27]\ : XA1 - port map(A => \grant_counter[27]_net_1\, B => N_68, C => - N_202, Y => N_135); - - \DMAIn.Address_RNO[16]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(16), Y - => N_51); - - \grant_counter_RNO[14]\ : XA1 - port map(A => \grant_counter[14]_net_1\, B => N623, C => - N_202_0, Y => N_109); - - un1_state_4_m59 : NOR2B - port map(A => N_58, B => \data_counter[22]_net_1\, Y => - N_60_0); - - \data_counter_RNI1O34[8]\ : NOR2 - port map(A => \data_counter[8]_net_1\, B => - \data_counter[9]_net_1\, Y => un1_state_5_i_o2_4); - - un1_hresetn_inv_2_m50 : AX1E - port map(A => \grant_counter[17]_net_1\, B => N_48, C => - \grant_counter[18]_net_1\, Y => \un1_hresetn_inv_2_i[13]\); - - \DMAIn.Address_RNO[13]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(13), Y - => N_45_0); - - un1_state_4_m25 : NOR2B - port map(A => N_25_0_0, B => \data_counter[10]_net_1\, Y - => N_26_0_0); - - \grant_counter_RNIU9Q[26]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_15[3]\, B => - \grant_counter[27]_net_1\, C => \grant_counter[26]_net_1\, - Y => \state_ns_i_a2_0_i_o2_23[3]\); - - \DMAIn.Address_RNIKHKI[10]\ : MX2 - port map(A => \Address[10]\, B => data_address(10), S => - time_select, Y => N_957); - - VCC_i : VCC - port map(Y => \VCC\); - - \state_RNIS4Q9[3]\ : OR3A - port map(A => Ready, B => \state[3]_net_1\, C => N_518_1, Y - => un1_state_7_i_a4_0_1); - - \DMAIn.Address_RNO[7]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(7), Y - => N_27); - - \data_counter_RNO_2[0]\ : NOR3B - port map(A => N_235, B => \state[3]_net_1\, C => - \un1_state_4_i_i[31]\, Y => N_336); - - \data_counter_RNO[16]\ : XA1B - port map(A => \data_counter[16]_net_1\, B => N_46, C => - N_198_0, Y => \data_counter_8[16]\); - - \data_counter_RNO[29]\ : XA1B - port map(A => \data_counter[29]_net_1\, B => N_72_0, C => - N_198, Y => \data_counter_8[29]\); - - un1_hresetn_inv_2_m16 : NOR3C - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => \grant_counter[1]_net_1\, Y => - N_17_0); - - \DMAIn.Address[8]\ : DFN1E1C0 - port map(D => N_29, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[8]\); - - \state_RNO[4]\ : AO1A - port map(A => Grant, B => \state[4]_net_1\, C => Request_5, - Y => N_84); - - \state_RNIK8SG_0[3]\ : OR2A - port map(A => \state[3]_net_1\, B => Fault, Y => N_522); - - un1_state_4_m27_m6_0_a2 : OR2B - port map(A => m27_m6_0_a2_4, B => N_19_0_0, Y => N_28_0); - - \grant_counter_RNIP4D[24]\ : NOR2 - port map(A => \grant_counter[24]_net_1\, B => - \grant_counter[25]_net_1\, Y => - \state_ns_i_a2_0_i_o2_13[3]\); - - \state_RNIAMD44[4]\ : NOR3A - port map(A => un1_hresetn_inv_i_0, B => N_246, C => - \state[4]_net_1\, Y => N_513); - - \DMAIn.Address_RNO[19]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(19), Y - => N_57); - - \DMAIn.Address[0]\ : DFN1E1C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[0]\); - - un1_hresetn_inv_2_m25 : NOR2B - port map(A => N_25_0, B => \grant_counter[10]_net_1\, Y => - N_26_0); - - un1_state_4_m27_m6_0_a2_4_5 : NOR3C - port map(A => \data_counter[6]_net_1\, B => - \data_counter[5]_net_1\, C => m27_m6_0_a2_4_2, Y => - m27_m6_0_a2_4_5); - - \state_RNO[2]\ : AO1C - port map(A => N_346, B => N_246, C => N_522, Y => N_151); - - \grant_counter_RNO[17]\ : XA1 - port map(A => \grant_counter[17]_net_1\, B => N_48, C => - N_202_0, Y => N_115); - - \grant_counter_RNIM2O7[30]\ : NOR2 - port map(A => \grant_counter[5]_net_1\, B => - \grant_counter[30]_net_1\, Y => - \state_ns_i_a2_0_i_o2_1[3]\); - - \state_RNIQIK31[4]\ : OR2A - port map(A => HRESETn_c, B => \N_200\, Y => N_202); - - un1_state_4_m71 : NOR2B - port map(A => N_70, B => \data_counter[28]_net_1\, Y => - N_72_0); - - \grant_counter[10]\ : DFN1 - port map(D => N_101, CLK => HCLK_c, Q => - \grant_counter[10]_net_1\); - - \data_counter_RNO[28]\ : XA1B - port map(A => \data_counter[28]_net_1\, B => N_70, C => - N_198, Y => \data_counter_8[28]\); - - \grant_counter[24]\ : DFN1 - port map(D => N_129, CLK => HCLK_c, Q => - \grant_counter[24]_net_1\); - - \data_counter_RNO[15]\ : NOR2 - port map(A => N_45, B => N_198_0, Y => \data_counter_8[15]\); - - \DMAIn.Lock_RNILJE7\ : MX2C - port map(A => Lock, B => Lock_0, S => time_select, Y => - N_1013); - - un1_state_4_m65 : NOR2B - port map(A => N_64_0, B => \data_counter[25]_net_1\, Y => - N_66); - - \DMAIn.Address_RNI4IRJ[22]\ : MX2 - port map(A => \Address[22]\, B => data_address(22), S => - time_select_0, Y => N_969); - - \grant_counter[16]\ : DFN1 - port map(D => N_113, CLK => HCLK_c, Q => - \grant_counter[16]_net_1\); - - \DMAIn.Address_RNION361[7]\ : MX2 - port map(A => \Address[7]\, B => data_address(7), S => - time_select, Y => N_954); - - \DMAIn.Address[15]\ : DFN1E1C0 - port map(D => N_49, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[15]\); - - un1_state_4_m20 : NOR2B - port map(A => N_20_0, B => \data_counter[5]_net_1\, Y => - N_21_0_0); - - \state_RNIAC4L7[3]\ : AO1D - port map(A => N_241, B => N_235, C => N_242, Y => N_154); - - \grant_counter[19]\ : DFN1 - port map(D => N_119, CLK => HCLK_c, Q => - \grant_counter[19]_net_1\); - - send_ok_RNIC0Q : NOR2 - port map(A => data_send_ok, B => data_send_ko, Y => - un1_data_send_ok); - - un1_hresetn_inv_2_m32 : AX1C - port map(A => \grant_counter[2]_net_1\, B => N_17_0, C => - \grant_counter[3]_net_1\, Y => N_33_0_i_0); - - un1_hresetn_inv_2_m27 : NOR2B - port map(A => N_27_0, B => \grant_counter[12]_net_1\, Y => - N_28_0_0); - - \data_counter[18]\ : DFN1C0 - port map(D => \data_counter_8[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[18]_net_1\); - - \DMAIn.Address_RNO[3]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(3), Y - => N_19); - - \data_counter_RNO[24]\ : XA1B - port map(A => \data_counter[24]_net_1\, B => N_62, C => - N_198, Y => \data_counter_8[24]\); - - \data_counter[14]\ : DFN1C0 - port map(D => \data_counter_8[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[14]_net_1\); - - \grant_counter_RNO[23]\ : XA1 - port map(A => \grant_counter[23]_net_1\, B => N_60, C => - N_202, Y => N_127); - - \DMAIn.Address_RNI5TN41[3]\ : MX2 - port map(A => \Address[3]\, B => data_address(3), S => - time_select_0, Y => N_950); - - un1_state_4_m28_m6_0 : NOR2B - port map(A => \data_counter[13]_net_1\, B => - \data_counter[1]_net_1\, Y => m28_m6_0); - - \state_RNIK8SG[3]\ : OR2B - port map(A => \state[3]_net_1\, B => Fault, Y => N_241); - - \DMAIn.Request_RNIJKMF\ : MX2 - port map(A => Request, B => Request_0, S => time_select, Y - => N_1011); - - \DMAIn.Address_RNO[21]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(21), Y - => N_61); - - \DMAIn.Address[23]\ : DFN1E1C0 - port map(D => N_65, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[23]\); - - \grant_counter[23]\ : DFN1 - port map(D => N_127, CLK => HCLK_c, Q => - \grant_counter[23]_net_1\); - - \data_counter[17]\ : DFN1C0 - port map(D => \data_counter_8[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[17]_net_1\); - - \state_RNIAC4L7_0[3]\ : AO1D - port map(A => N_241, B => N_235, C => N_242, Y => N_154_0); - - \state_RNI3191[1]\ : NOR2 - port map(A => \state[1]_net_1\, B => \state[2]_net_1\, Y - => un1_state_2_i_o2_0); - - \grant_counter_RNIH4D[20]\ : NOR2 - port map(A => \grant_counter[20]_net_1\, B => - \grant_counter[21]_net_1\, Y => - \state_ns_i_a2_0_i_o2_11[3]\); - - \DMAIn.Address_RNIQKM41[1]\ : MX2 - port map(A => \Address[1]\, B => data_address(1), S => - time_select_0, Y => N_948); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_14 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_9_0, B => - ADD_32x32_fast_I129_un1_Y_8_0, C => - ADD_32x32_fast_I129_un1_Y_13_0, Y => - ADD_32x32_fast_I129_un1_Y_14_0); - - \data_counter_RNIJN34[3]\ : NOR2B - port map(A => \data_counter[3]_net_1\, B => - \data_counter[0]_net_1\, Y => un1_state_5_i_o2_15); - - \data_counter[31]\ : DFN1C0 - port map(D => \data_counter_8[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[31]_net_1\); - - \data_counter_RNILUOF[20]\ : NOR2 - port map(A => \data_counter[20]_net_1\, B => - \data_counter[21]_net_1\, Y => un1_state_5_i_o2_9); - - un1_state_4_m29 : XNOR2 - port map(A => \data_counter[0]_net_1\, B => N_510, Y => - \un1_state_4_i_i[31]\); - - un1_hresetn_inv_2_m28 : NOR2B - port map(A => N_28_0_0, B => \grant_counter[13]_net_1\, Y - => N623); - - \data_counter_RNO_0[0]\ : AO1D - port map(A => N_508, B => N_338_1, C => N_337, Y => - \data_counter_8_i_0[0]\); - - \data_counter_RNIOTJV[18]\ : NOR3A - port map(A => un1_state_5_i_o2_9, B => - \data_counter[19]_net_1\, C => \data_counter[18]_net_1\, - Y => un1_state_5_i_o2_20); - - \grant_counter[31]\ : DFN1 - port map(D => N_143, CLK => HCLK_c, Q => - \grant_counter[31]_net_1\); - - \grant_counter[15]\ : DFN1 - port map(D => N_111, CLK => HCLK_c, Q => - \grant_counter[15]_net_1\); - - \DMAIn.Address_RNO[1]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(1), Y - => N_15); - - \grant_counter[6]\ : DFN1 - port map(D => N_93, CLK => HCLK_c, Q => - \grant_counter[6]_net_1\); - - \DMAIn.Address_RNO[22]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(22), Y - => N_63); - - \data_counter[19]\ : DFN1C0 - port map(D => \data_counter_8[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[19]_net_1\); - - \DMAIn.Address[16]\ : DFN1E1C0 - port map(D => N_51, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[16]\); - - \grant_counter_RNO_0[0]\ : XA1A - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => N_202_0, Y => - \grant_counter_0_0_0[0]\); - - \grant_counter[8]\ : DFN1 - port map(D => N_97, CLK => HCLK_c, Q => - \grant_counter[8]_net_1\); - - \data_counter_RNIN6PF[30]\ : NOR2 - port map(A => \data_counter[13]_net_1\, B => - \data_counter[30]_net_1\, Y => un1_state_5_i_o2_1); - - \state_RNI3191[0]\ : OR2 - port map(A => \state[3]_net_1\, B => \state[0]_net_1\, Y - => N_338_1); - - un1_state_4_m30 : XNOR2 - port map(A => N_16_0, B => \data_counter[1]_net_1\, Y => - \un1_state_4_i[30]\); - - \DMAIn.Address_RNO[24]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(24), Y - => N_67); - - \data_counter_RNO[3]\ : AOI1B - port map(A => \un1_state_4_i[28]\, B => N_344, C => N_509, - Y => N_192); - - un1_hresetn_inv_2_m43_m6_0_a2_5 : NOR3C - port map(A => \grant_counter[9]_net_1\, B => - \grant_counter[8]_net_1\, C => m43_m6_0_a2_2, Y => - m43_m6_0_a2_5); - - \DMAIn.Address_RNO[25]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(25), Y - => N_69); - - \data_counter_RNO[5]\ : XA1B - port map(A => \data_counter[5]_net_1\, B => N_20_0, C => - N_198, Y => \data_counter_8[5]\); - - \data_counter_RNITUPF[24]\ : NOR2 - port map(A => \data_counter[24]_net_1\, B => - \data_counter[25]_net_1\, Y => un1_state_5_i_o2_11); - - un1_state_4_m67 : NOR2B - port map(A => N_66, B => \data_counter[26]_net_1\, Y => - N_68_0); - - \grant_counter_RNO[13]\ : XA1 - port map(A => \grant_counter[13]_net_1\, B => N_28_0_0, C - => N_202_0, Y => N_107); - - \grant_counter_RNIDK1F[1]\ : NOR2B - port map(A => \grant_counter[0]_net_1\, B => - \grant_counter[1]_net_1\, Y => - \state_ns_i_a2_0_i_o2_2[3]\); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - \state_RNIJKJ6[1]\ : AO1A - port map(A => data_send, B => \state_0[5]_net_1\, C => - \state[1]_net_1\, Y => \state_ns_i_a2_i_0_0[0]\); - - \data_counter[7]\ : DFN1C0 - port map(D => \data_counter_8[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[7]_net_1\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_14 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_9, B => - ADD_32x32_fast_I129_un1_Y_8, C => - ADD_32x32_fast_I129_un1_Y_13, Y => - ADD_32x32_fast_I129_un1_Y_14); - - \grant_counter_RNO[21]\ : XA1 - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - N_202, Y => N_123); - - \data_counter[5]\ : DFN1C0 - port map(D => \data_counter_8[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[5]_net_1\); - - \DMAIn.Request\ : DFN1E1C0 - port map(D => Request_5, CLK => HCLK_c, CLR => HRESETn_c, E - => N_156, Q => Request); - - \DMAIn.Address_RNO[11]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(11), Y - => N_35); - - \grant_counter_RNO_0[4]\ : AO1C - port map(A => N_246, B => un1_hresetn_inv_i_0, C => N_202_0, - Y => \grant_counter_0_i_0[4]\); - - \DMAIn.Address_RNO[6]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(6), Y - => N_25); - - \DMAIn.Address[17]\ : DFN1E1C0 - port map(D => N_53, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[17]\); - - \data_counter_RNIVEQF[16]\ : NOR2 - port map(A => \data_counter[16]_net_1\, B => - \data_counter[17]_net_1\, Y => un1_state_5_i_o2_7); - - \grant_counter_RNO[31]\ : XA1 - port map(A => \grant_counter[31]_net_1\, B => N_75, C => - N_202, Y => N_143); - - \grant_counter_RNIGI0V[6]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_5[3]\, B => - \state_ns_i_a2_0_i_o2_4[3]\, C => - \state_ns_i_a2_0_i_o2_19[3]\, Y => - \state_ns_i_a2_0_i_o2_25[3]\); - - \state_RNIEK821[0]\ : NOR2 - port map(A => \state[0]_net_1\, B => N_243, Y => N_348); - - un1_state_4_m28_m6_5 : AOI1B - port map(A => \state[3]_net_1\, B => OKAY, C => m28_m6_4, Y - => m28_m6_5); - - \state_RNIF6GI1[0]\ : OR2A - port map(A => N_348, B => OKAY, Y => N_510); - - \DMAIn.Address[22]\ : DFN1E1C0 - port map(D => N_63, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[22]\); - - \data_counter_RNO[30]\ : NOR2 - port map(A => \un1_state_4_i[1]\, B => N_198, Y => - \data_counter_8[30]\); - - \data_counter[9]\ : DFN1C0 - port map(D => \data_counter_8[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[9]_net_1\); - - un1_state_4_m69 : NOR2B - port map(A => N_68_0, B => \data_counter[27]_net_1\, Y => - N_70); - - un1_hresetn_inv_2_m43_m6_0_a2_4 : NOR3C - port map(A => \grant_counter[7]_net_1\, B => - \grant_counter[6]_net_1\, C => \grant_counter[14]_net_1\, - Y => m43_m6_0_a2_4); - - un1_state_4_m27_m6_0_a2_4 : NOR3C - port map(A => m27_m6_0_a2_4_4, B => m27_m6_0_a2_4_3, C => - m27_m6_0_a2_4_5, Y => m27_m6_0_a2_4); - - \data_counter[30]\ : DFN1C0 - port map(D => \data_counter_8[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[30]_net_1\); - - un1_state_4_m28_m6_1 : NOR2B - port map(A => \data_counter[2]_net_1\, B => - \data_counter[3]_net_1\, Y => m28_m6_1); - - \data_counter_RNO[7]\ : XA1B - port map(A => \data_counter[7]_net_1\, B => N_22_0_0, C => - N_198_0, Y => \data_counter_8[7]\); - - \data_counter_RNO[11]\ : XA1B - port map(A => \data_counter[11]_net_1\, B => N_26_0_0, C - => N_198_0, Y => \data_counter_8[11]\); - - un1_hresetn_inv_2_m62 : AX1E - port map(A => \grant_counter[23]_net_1\, B => N_60, C => - \grant_counter[24]_net_1\, Y => \un1_hresetn_inv_2_i[7]\); - - \grant_counter_RNO[2]\ : AO1 - port map(A => N_32_0_i_0, B => N_202, C => N_513, Y => - \grant_counter_RNO[2]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_counter_RNO[23]\ : XA1B - port map(A => \data_counter[23]_net_1\, B => N_60_0, C => - N_198, Y => \data_counter_8[23]\); - - un1_hresetn_inv_2_m24 : NOR2B - port map(A => N_24_0, B => \grant_counter[9]_net_1\, Y => - N_25_0); - - \DMAIn.Address_RNO[12]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(12), Y - => N_43); - - un1_hresetn_inv_2_m55 : NOR3C - port map(A => \grant_counter[19]_net_1\, B => N_52, C => - \grant_counter[20]_net_1\, Y => N_56); - - \grant_counter_RNO[25]\ : XA1 - port map(A => \grant_counter[25]_net_1\, B => N_64, C => - N_202, Y => N_131); - - \DMAIn.Address_RNITIRJ[27]\ : MX2C - port map(A => \Address[27]\, B => data_address(27), S => - time_select_0, Y => N_974); - - \DMAIn.Address_RNO[14]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(14), Y - => N_47); - - \grant_counter_RNO[11]\ : XA1 - port map(A => \grant_counter[11]_net_1\, B => N_26_0, C => - N_202_0, Y => N_103); - - \grant_counter_RNI2E83[14]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_21[3]\, B => - \state_ns_i_a2_0_i_o2_20[3]\, C => - \state_ns_i_a2_0_i_o2_27[3]\, Y => - \state_ns_i_a2_0_i_o2_29[3]\); - - \DMAIn.Address[20]\ : DFN1E1C0 - port map(D => N_59, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[20]\); - - \DMAIn.Address_RNO[15]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(15), Y - => N_49); - - un1_state_4_m74_0 : NOR2B - port map(A => \data_counter[30]_net_1\, B => - \data_counter[29]_net_1\, Y => m74_0); - - \DMAIn.Address_RNIOIRJ[26]\ : MX2C - port map(A => \Address[26]\, B => data_address(26), S => - time_select_0, Y => N_973); - - \data_counter_RNO[20]\ : XA1B - port map(A => \data_counter[20]_net_1\, B => N_54, C => - N_198_0, Y => \data_counter_8[20]\); - - \state_RNI2R0V2[1]\ : AO1D - port map(A => N_346, B => N_246, C => - \state_ns_i_a2_i_0_0[0]\, Y => N_4); - - \DMAIn.Address_RNI7JRJ[29]\ : MX2 - port map(A => \Address[29]\, B => data_address(29), S => - time_select_0, Y => N_976); - - \DMAIn.Address[21]\ : DFN1E1C0 - port map(D => N_61, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[21]\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_13 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_5_0, B => - ADD_32x32_fast_I129_un1_Y_4_0, C => - ADD_32x32_fast_I129_un1_Y_11_0, Y => - ADD_32x32_fast_I129_un1_Y_13_0); - - \grant_counter[5]\ : DFN1 - port map(D => N_91, CLK => HCLK_c, Q => - \grant_counter[5]_net_1\); - - \DMAIn.Address_RNO[9]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(9), Y - => N_31); - - \DMAIn.Address[18]\ : DFN1E1C0 - port map(D => N_55, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[18]\); - - \data_counter[25]\ : DFN1C0 - port map(D => \data_counter_8[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[25]_net_1\); - - \grant_counter[4]\ : DFN1 - port map(D => N_89, CLK => HCLK_c, Q => - \grant_counter[4]_net_1\); - - \grant_counter[11]\ : DFN1 - port map(D => N_103, CLK => HCLK_c, Q => - \grant_counter[11]_net_1\); - - \DMAIn.Address[24]\ : DFN1E1C0 - port map(D => N_67, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[24]\); - - \grant_counter[12]\ : DFN1 - port map(D => N_105, CLK => HCLK_c, Q => - \grant_counter[12]_net_1\); - - \DMAIn.Burst_RNO\ : NOR3C - port map(A => N_522, B => Burst, C => N_526, Y => N_194_i_0); - - un1_hresetn_inv_2_m43_m6_0_a2 : NOR3C - port map(A => m43_m6_0_a2_6, B => m43_m6_0_a2_5, C => - N_21_0, Y => N_44); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_9 : NOR3C - port map(A => \grant_counter[19]_net_1\, B => - \grant_counter[18]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_3, Y => - ADD_32x32_fast_I129_un1_Y_9); - - \DMAIn.Address[19]\ : DFN1E1C0 - port map(D => N_57, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[19]\); - - \data_counter_RNO[1]\ : AOI1B - port map(A => \un1_state_4_i[30]\, B => N_344, C => N_509, - Y => N_188); - - \state_RNIMV7G3[3]\ : OR3B - port map(A => \state[3]_net_1\, B => Grant, C => N_246, Y - => N_526); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \data_counter[22]_net_1\, B => - \data_counter[23]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_4_0); - - \state_RNISRSN8_0[3]\ : OR2B - port map(A => N_509, B => N_344, Y => N_198_0); - - un1_hresetn_inv_2_m74 : NOR3C - port map(A => \grant_counter[29]_net_1\, B => - \grant_counter[30]_net_1\, C => N_72, Y => N_75); - - \grant_counter_RNI15D[28]\ : NOR2 - port map(A => \grant_counter[28]_net_1\, B => - \grant_counter[29]_net_1\, Y => - \state_ns_i_a2_0_i_o2_15[3]\); - - \data_counter[4]\ : DFN1C0 - port map(D => \data_counter_8[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[4]_net_1\); - - \DMAIn.Address_RNIVHRJ[21]\ : MX2 - port map(A => \Address[21]\, B => data_address(21), S => - time_select_0, Y => N_968); - - \grant_counter_RNO[15]\ : XA1 - port map(A => \grant_counter[15]_net_1\, B => N_44, C => - N_202_0, Y => N_111); - - un1_hresetn_inv_2_m43_m6_0_a2_6 : NOR3C - port map(A => \grant_counter[13]_net_1\, B => - \grant_counter[12]_net_1\, C => m43_m6_0_a2_4, Y => - m43_m6_0_a2_6); - - \grant_counter[7]\ : DFN1 - port map(D => N_95, CLK => HCLK_c, Q => - \grant_counter[7]_net_1\); - - \DMAIn.Address_RNO[31]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(31), Y - => N_81); - - \state[2]\ : DFN1C0 - port map(D => N_151, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[2]_net_1\); - - \data_counter_RNIE4HJ1[8]\ : NOR3C - port map(A => un1_state_5_i_o2_5, B => un1_state_5_i_o2_4, - C => un1_state_5_i_o2_19, Y => un1_state_5_i_o2_25); - - send_ko : DFN1E1C0 - port map(D => \state[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_146, Q => data_send_ko); - - \data_counter_RNO[12]\ : XA1C - port map(A => \data_counter[12]_net_1\, B => N_27_0_0, C - => N_198_0, Y => \data_counter_8[12]\); - - un1_state_4_ADD_32x32_fast_I190_Y_0 : AX1E - port map(A => N623_0, B => ADD_32x32_fast_I129_un1_Y_14_0, - C => \data_counter[30]_net_1\, Y => \un1_state_4_i[1]\); - - \DMAIn.Address_RNIMC0J[18]\ : MX2 - port map(A => \Address[18]\, B => data_address(18), S => - time_select_0, Y => N_965); - - un1_hresetn_inv_2_m31 : XOR2 - port map(A => N_17_0, B => \grant_counter[2]_net_1\, Y => - N_32_0_i_0); - - un1_state_4_m27_m6_0_a2_4_3 : NOR2B - port map(A => \data_counter[9]_net_1\, B => - \data_counter[10]_net_1\, Y => m27_m6_0_a2_4_3); - - \DMAIn.Store\ : DFN1E1C0 - port map(D => \state[5]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_156, Q => Store); - - \DMAIn.Address_RNI9R161[4]\ : MX2 - port map(A => \Address[4]\, B => data_address(4), S => - time_select, Y => N_951); - - un1_state_4_m27_m6_0_a2_4_2 : NOR2B - port map(A => \data_counter[7]_net_1\, B => - \data_counter[8]_net_1\, Y => m27_m6_0_a2_4_2); - - \grant_counter_RNO[29]\ : XA1 - port map(A => \grant_counter[29]_net_1\, B => N_72, C => - N_202, Y => N_139); - - \DMAIn.Address[3]\ : DFN1E1C0 - port map(D => N_19, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[3]\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_11 : NOR3C - port map(A => \data_counter[27]_net_1\, B => - \data_counter[26]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_7_0, Y => - ADD_32x32_fast_I129_un1_Y_11_0); - - \state[1]\ : DFN1C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - un1_hresetn_inv_2_m30 : AX1C - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => \grant_counter[1]_net_1\, Y => - N_31_0_i_0); - - \grant_counter_RNISQSF2[14]\ : OR3C - port map(A => \state_ns_i_a2_0_i_o2_25[3]\, B => - \state_ns_i_a2_0_i_o2_24[3]\, C => - \state_ns_i_a2_0_i_o2_29[3]\, Y => N_246); - - \DMAIn.Burst\ : DFN1P0 - port map(D => N_194_i_0, CLK => HCLK_c, PRE => HRESETn_c, Q - => Burst); - - un1_hresetn_inv_2_m18 : NOR3C - port map(A => \grant_counter[2]_net_1\, B => N_17_0, C => - \grant_counter[3]_net_1\, Y => N_19_0); - - un1_hresetn_inv_2_m58 : AX1E - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - \grant_counter[22]_net_1\, Y => \un1_hresetn_inv_2_i[9]\); - - \data_counter_RNO[9]\ : XA1B - port map(A => \data_counter[9]_net_1\, B => N_24_0_0, C => - N_198_0, Y => \data_counter_8[9]\); - - \DMAIn.Address_RNIK4FJ[17]\ : MX2 - port map(A => \Address[17]\, B => data_address(17), S => - time_select, Y => N_964); - - \data_counter_RNO[26]\ : XA1B - port map(A => \data_counter[26]_net_1\, B => N_66, C => - N_198, Y => \data_counter_8[26]\); - - un1_hresetn_inv_2_m22 : NOR2B - port map(A => N_22_0, B => \grant_counter[7]_net_1\, Y => - N_23_0); - - \state_RNO[3]\ : AO1C - port map(A => N_241, B => N_235, C => \N_200\, Y => - \state_RNO[3]_net_1\); - - \state_RNO[0]\ : AO1D - port map(A => N_241, B => N_235, C => - \state_RNO_0[0]_net_1\, Y => \state_RNO[0]_net_1\); - - \grant_counter[14]\ : DFN1 - port map(D => N_109, CLK => HCLK_c, Q => - \grant_counter[14]_net_1\); - - \grant_counter_RNICJK1[22]\ : NOR2B - port map(A => \state_ns_i_a2_0_i_o2_22[3]\, B => - \state_ns_i_a2_0_i_o2_23[3]\, Y => - \state_ns_i_a2_0_i_o2_27[3]\); - - \DMAIn.Address[4]\ : DFN1E1C0 - port map(D => N_21, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[4]\); - - \grant_counter[2]\ : DFN1 - port map(D => \grant_counter_RNO[2]_net_1\, CLK => HCLK_c, - Q => \grant_counter[2]_net_1\); - - \data_counter_RNIB4B41[0]\ : MX2A - port map(A => \state[5]_net_1\, B => - \data_counter[0]_net_1\, S => N_243, Y => N_508); - - \data_counter[26]\ : DFN1C0 - port map(D => \data_counter_8[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[26]_net_1\); - - \data_counter[23]\ : DFN1C0 - port map(D => \data_counter_8[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[23]_net_1\); - - \DMAIn.Address_RNIEIRJ[24]\ : MX2 - port map(A => \Address[24]\, B => data_address(24), S => - time_select_0, Y => N_971); - - \DMAIn.Address[25]\ : DFN1E1C0 - port map(D => N_69, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[25]\); - - un1_state_4_m45 : NOR3C - port map(A => \data_counter[14]_net_1\, B => N623_0, C => - \data_counter[15]_net_1\, Y => N_46); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \data_counter[15]_net_1\, B => - \data_counter[14]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_1_0, Y => - ADD_32x32_fast_I129_un1_Y_8_0); - - \grant_counter_RNO[19]\ : XA1 - port map(A => \grant_counter[19]_net_1\, B => N_52, C => - N_202, Y => N_119); - - \DMAIn.Address_RNO[2]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(2), Y - => N_17); - - \data_counter_RNO[17]\ : XA1B - port map(A => \data_counter[17]_net_1\, B => N_48_0, C => - N_198_0, Y => \data_counter_8[17]\); - - un1_state_4_m24 : NOR2B - port map(A => N_24_0_0, B => \data_counter[9]_net_1\, Y => - N_25_0_0); - - \data_counter_RNO[25]\ : XA1B - port map(A => \data_counter[25]_net_1\, B => N_64_0, C => - N_198, Y => \data_counter_8[25]\); - - \data_counter[21]\ : DFN1C0 - port map(D => \data_counter_8[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[21]_net_1\); - - \DMAIn.Address_RNO[4]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(4), Y - => N_21); - - \grant_counter_RNO[7]\ : XA1 - port map(A => \grant_counter[7]_net_1\, B => N_22_0, C => - N_202_0, Y => N_95); - - \data_counter_RNI6F78[2]\ : NOR3C - port map(A => \data_counter[2]_net_1\, B => - \data_counter[1]_net_1\, C => un1_state_5_i_o2_15, Y => - un1_state_5_i_o2_23); - - \DMAIn.Lock\ : DFN1E1C0 - port map(D => data_send, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[5]_net_1\, Q => Lock); - - \data_counter_RNO_3[0]\ : NOR2A - port map(A => \state[0]_net_1\, B => - \data_counter[0]_net_1\, Y => N_337); - - \state_RNIQIK31_0[4]\ : OR2A - port map(A => HRESETn_c, B => \N_200\, Y => N_202_0); - - \grant_counter[3]\ : DFN1 - port map(D => \grant_counter_RNO[3]_net_1\, CLK => HCLK_c, - Q => \grant_counter[3]_net_1\); - - \data_counter_RNIJUOF[10]\ : NOR2 - port map(A => \data_counter[10]_net_1\, B => - \data_counter[11]_net_1\, Y => un1_state_5_i_o2_5); - - \grant_counter[13]\ : DFN1 - port map(D => N_107, CLK => HCLK_c, Q => - \grant_counter[13]_net_1\); - - \grant_counter_RNIQOP[10]\ : NOR2B - port map(A => \state_ns_i_a2_0_i_o2_6[3]\, B => - \state_ns_i_a2_0_i_o2_7[3]\, Y => - \state_ns_i_a2_0_i_o2_19[3]\); - - \grant_counter[27]\ : DFN1 - port map(D => N_135, CLK => HCLK_c, Q => - \grant_counter[27]_net_1\); - - \state_RNI1FH3[5]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_send, Y => - Request_5); - - \DMAIn.Address_RNIF4FJ[16]\ : MX2 - port map(A => \Address[16]\, B => data_address(16), S => - time_select, Y => N_963); - - \DMAIn.Address_RNIA4FJ[15]\ : MX2 - port map(A => \Address[15]\, B => data_address(15), S => - time_select, Y => N_962); - - un1_state_4_m15 : AOI1B - port map(A => N_510, B => N_509, C => - \data_counter[0]_net_1\, Y => N_16_0); - - un1_hresetn_inv_2_m54 : AX1E - port map(A => \grant_counter[19]_net_1\, B => N_52, C => - \grant_counter[20]_net_1\, Y => \un1_hresetn_inv_2_i[11]\); - - \grant_counter_RNIAQJD1[31]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_3[3]\, B => - \state_ns_i_a2_0_i_o2_2[3]\, C => - \state_ns_i_a2_0_i_o2_16[3]\, Y => - \state_ns_i_a2_0_i_o2_24[3]\); - - \grant_counter[28]\ : DFN1 - port map(D => N_137, CLK => HCLK_c, Q => - \grant_counter[28]_net_1\); - - un1_state_4_ADD_32x32_fast_I174_Y_0 : XNOR2 - port map(A => N623_0, B => \data_counter[14]_net_1\, Y => - \un1_state_4_i[17]\); - - un1_hresetn_inv_2_m46 : AX1E - port map(A => \grant_counter[15]_net_1\, B => N_44, C => - \grant_counter[16]_net_1\, Y => \un1_hresetn_inv_2_i[15]\); - - \grant_counter_RNIE9Q[22]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_13[3]\, B => - \grant_counter[23]_net_1\, C => \grant_counter[22]_net_1\, - Y => \state_ns_i_a2_0_i_o2_22[3]\); - - \DMAIn.Address[26]\ : DFN1E1C0 - port map(D => N_71, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[26]\); - - \DMAIn.Address_RNIJ3361[6]\ : MX2 - port map(A => \Address[6]\, B => data_address(6), S => - time_select, Y => N_953); - - \data_counter_RNO[0]\ : NOR3 - port map(A => \data_counter_8_i_0[0]\, B => N_339, C => - N_336, Y => N_186); - - \state_RNIQ0SJ1[3]\ : NOR3B - port map(A => HRESETn_c, B => Grant, C => N_241, Y => - un1_hresetn_inv_i_0); - - \state_RNIJBG8[0]\ : OR2B - port map(A => \state[0]_net_1\, B => Ready, Y => N_346); - - \DMAIn.Address_RNIQHRJ[20]\ : MX2 - port map(A => \Address[20]\, B => data_address(20), S => - time_select_0, Y => N_967); - - \grant_counter_RNO[0]\ : AO1C - port map(A => N_246, B => un1_hresetn_inv_i_0, C => - \grant_counter_0_0_0[0]\, Y => - \grant_counter_RNO[0]_net_1\); - - \data_counter[6]\ : DFN1C0 - port map(D => \data_counter_8[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[6]_net_1\); - - \data_counter[15]\ : DFN1C0 - port map(D => \data_counter_8[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[15]_net_1\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_3 : NOR2B - port map(A => \data_counter[20]_net_1\, B => - \data_counter[21]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_3_0); - - un1_state_4_m47 : NOR2B - port map(A => N_46, B => \data_counter[16]_net_1\, Y => - N_48_0); - - \data_counter_RNIDSMI6[22]\ : OR2B - port map(A => un1_state_5_i_o2_30, B => un1_state_5_i_o2_29, - Y => N_235); - - un1_hresetn_inv_2_m63 : NOR3C - port map(A => \grant_counter[23]_net_1\, B => N_60, C => - \grant_counter[24]_net_1\, Y => N_64); - - \data_counter_RNO[19]\ : XA1B - port map(A => \data_counter[19]_net_1\, B => N_52_0, C => - N_198_0, Y => \data_counter_8[19]\); - - \grant_counter_RNO[8]\ : XA1 - port map(A => \grant_counter[8]_net_1\, B => N_23_0, C => - N_202_0, Y => N_97); - - \data_counter[20]\ : DFN1C0 - port map(D => \data_counter_8[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[20]_net_1\); - - un1_state_4_m28_m6 : NOR3B - port map(A => m28_m6_5, B => m27_m6_0_a2_4, C => N_243, Y - => N623_0); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_13 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_5, B => - ADD_32x32_fast_I129_un1_Y_4, C => - ADD_32x32_fast_I129_un1_Y_11, Y => - ADD_32x32_fast_I129_un1_Y_13); - - \data_counter[22]\ : DFN1C0 - port map(D => \data_counter_8[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[22]_net_1\); - - \data_counter_RNIQDKV[15]\ : NOR3A - port map(A => un1_state_5_i_o2_7, B => - \data_counter[15]_net_1\, C => \data_counter[14]_net_1\, - Y => un1_state_5_i_o2_19); - - \state_RNIU9K11[4]\ : AO1C - port map(A => Grant, B => \state[4]_net_1\, C => - un1_state_2_i_o2_0, Y => N_243); - - \grant_counter_RNIAPP[14]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_9[3]\, B => - \grant_counter[15]_net_1\, C => \grant_counter[14]_net_1\, - Y => \state_ns_i_a2_0_i_o2_20[3]\); - - \DMAIn.Address[27]\ : DFN1E1C0 - port map(D => N_73, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[27]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(1 to 1); - status_full : out std_logic_vector(1 to 1); - sel_data : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - update_and_sel_5 : in std_logic_vector(3 downto 2); - addr_data_f1 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(1 to 1); - addr_data_vector_94 : in std_logic; - addr_data_vector_91 : in std_logic; - addr_data_vector_89 : in std_logic; - addr_data_vector_87 : in std_logic; - addr_data_vector_86 : in std_logic; - addr_data_vector_85 : in std_logic; - addr_data_vector_84 : in std_logic; - addr_data_vector_83 : in std_logic; - addr_data_vector_67 : in std_logic; - addr_data_vector_66 : in std_logic; - addr_data_vector_65 : in std_logic; - addr_data_vector_64 : in std_logic; - addr_data_vector_75 : in std_logic; - addr_data_vector_73 : in std_logic; - addr_data_vector_81 : in std_logic; - addr_data_vector_79 : in std_logic; - addr_data_vector_77 : in std_logic; - addr_data_vector_24 : out std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_16 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_18 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_5 : out std_logic; - addr_data_vector_4 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_12 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_8 : out std_logic; - N_913 : out std_logic; - N_910 : out std_logic; - N_908 : out std_logic; - N_906 : out std_logic; - N_905 : out std_logic; - N_904 : out std_logic; - N_903 : out std_logic; - N_902 : out std_logic; - N_1300 : out std_logic; - N_1299 : out std_logic; - N_1298 : out std_logic; - N_1297 : out std_logic; - N_1294 : out std_logic; - N_1292 : out std_logic; - N_1286 : out std_logic; - N_1284 : out std_logic; - N_1282 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, m40_m6_0_a2_6, m40_m6_0_a2_1, - m40_m6_0_a2_0, m40_m6_0_a2_5, m40_m6_0_a2_3, - \addr_data_vector[41]\, \addr_data_vector[54]\, - \addr_data_vector[55]\, \addr_data_vector[43]\, - m20_m7_i_4, address_0_sqmuxa, m20_m7_i_3, m20_m7_i_0, - \addr_data_vector[42]\, m20_m7_i_1, - \addr_data_vector[40]\, \addr_data_vector[39]\, - m20_m3_e_0, \un1_state_12_3_0[4]\, \update_r_i[0]\, - \update_r[1]_net_1\, address_0_sqmuxa_0, \state[3]_net_1\, - un3_update_r, un1_state_5_i_0, \state[4]_net_1\, - \state_ns_i_0[3]\, N_131, address_7_31_m6_e_3, - \addr_data_vector[57]\, \addr_data_vector[62]\, - address_7_31_m6_e_1, address_7_31_m6_e_2, - \addr_data_vector[59]\, m36_m6_0_a2_4_6, - \addr_data_vector[51]\, m36_m6_0_a2_4_4, m36_m6_0_a2_4_5, - \addr_data_vector[47]\, m36_m6_0_a2_4_2, - \addr_data_vector[45]\, \addr_data_vector[53]\, - \addr_data_vector[52]\, \addr_data_vector[49]\, - \un1_address[6]\, \addr_data_vector[38]\, N_5_0, N_116, - N_129, \state[1]_net_1\, \state_ns[0]\, N_125, N_124, - \un1_state_12_2[4]\, N_110, \state[2]_net_1\, state7, - m36_m6_0_a2_4_i, \address_RNO_2[31]_net_1\, N_41, N_13_0, - m20_m3_e, N_69, m20_N_17_i_0, m20_m7_i_o5, - \address_7[31]\, \address_RNO_0[31]_net_1\, - \address_RNO_1[31]_net_1\, \addr_data_vector[63]\, N_37_0, - \addr_data_vector[44]\, N_2, \addr_data_vector[34]\, - N_15_0_i_0, N_16_0, N_17_0_i_0, N_18_0, N_20_0_i_0, - N_22_0_i_0, N_24_0, N_26_0_i_0, \addr_data_vector[46]\, - N_27_0, N_28_0_i_0, \addr_data_vector[48]\, N_30_0_i_0, - N_31_0, \un1_address[19]\, \addr_data_vector[50]\, N_34_0, - \un1_address[20]\, \un1_address[23]\, N_40_i_0, N_43, - \addr_data_vector[56]\, N_45, \addr_data_vector[58]\, - N_46, \addr_data_vector[60]\, N_50_i_0, - \addr_data_vector[35]\, N_51_i_0, \addr_data_vector[36]\, - N_52_i_0, \addr_data_vector[37]\, N_1_i_0, N_54_0_i_0, - N_55_0_i_0, \un1_address[18]\, \un1_address[21]\, - \un1_address[22]\, \un1_address[24]\, \un1_address[25]\, - \un1_address[26]\, \un1_address[27]\, \un1_address[28]\, - \un1_address[29]\, \addr_data_vector[61]\, - \un1_address[30]\, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[15]\, \address_7[16]\, - \address_7[17]\, \state[0]_net_1\, \address_7[18]\, - \address_7[19]\, \address_7[20]\, \address_7[21]\, - \address_7[22]\, \address_7[23]\, \address_7[24]\, - \address_7[25]\, \address_7[26]\, \address_7[27]\, - \address_7[28]\, \address_7[29]\, \address_7[30]\, - N_56_0_i_0, un1_state_9, \nb_send_5[0]\, \nb_send_5[1]\, - \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, N_127, N_113, \state_ns[2]\, - un1_state_11, \address_7[14]\, \addr_data_vector[32]\, - \addr_data_vector[33]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_24 <= \addr_data_vector[56]\; - addr_data_vector_31 <= \addr_data_vector[63]\; - addr_data_vector_16 <= \addr_data_vector[48]\; - addr_data_vector_14 <= \addr_data_vector[46]\; - addr_data_vector_18 <= \addr_data_vector[50]\; - addr_data_vector_26 <= \addr_data_vector[58]\; - addr_data_vector_29 <= \addr_data_vector[61]\; - addr_data_vector_28 <= \addr_data_vector[60]\; - addr_data_vector_5 <= \addr_data_vector[37]\; - addr_data_vector_4 <= \addr_data_vector[36]\; - addr_data_vector_6 <= \addr_data_vector[38]\; - addr_data_vector_12 <= \addr_data_vector[44]\; - addr_data_vector_10 <= \addr_data_vector[42]\; - addr_data_vector_7 <= \addr_data_vector[39]\; - addr_data_vector_8 <= \addr_data_vector[40]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[48]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[42]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[62]\); - - un1_address_m20_m7_i_0 : NOR2B - port map(A => \addr_data_vector[43]\, B => - \addr_data_vector[39]\, Y => m20_m7_i_0); - - un1_address_m45 : NOR2A - port map(A => \addr_data_vector[60]\, B => N_45, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f1(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : XNOR2 - port map(A => N_43, B => \addr_data_vector[58]\, Y => - \un1_address[26]\); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[58]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[52]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3B - port map(A => N_129, B => \state[2]_net_1\, C => - status_full_ack(1), Y => N_127); - - \state_RNI3CSP8[3]\ : OR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1C - port map(A => \addr_data_vector[36]\, B => N_69, C => - \addr_data_vector[37]\, Y => N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[44]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f1(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m36_m6_0_a2_4_4 : NOR3C - port map(A => \addr_data_vector[45]\, B => - \addr_data_vector[53]\, C => \addr_data_vector[52]\, Y - => m36_m6_0_a2_4_4); - - un1_address_m36_m6_0_a2_4 : OR2B - port map(A => m36_m6_0_a2_4_6, B => m36_m6_0_a2_4_5, Y => - m36_m6_0_a2_4_i); - - un1_address_m19 : AX1C - port map(A => \addr_data_vector[42]\, B => N_18_0, C => - \addr_data_vector[43]\, Y => N_20_0_i_0); - - \address_RNI68OA[9]\ : MX2C - port map(A => \addr_data_vector[41]\, B => - addr_data_vector_73, S => sel_data_0(1), Y => N_1292); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[54]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f1(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[34]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f1(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f1(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_110, Q => status_full_err(1)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f1(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[37]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[47]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[45]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[51]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[57]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[55]\); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[39]\, C => - \addr_data_vector[40]\, Y => N_15_0_i_0); - - un1_address_m29 : AX1C - port map(A => \addr_data_vector[48]\, B => N_27_0, C => - \addr_data_vector[49]\, Y => N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - un1_address_m36_m6_0_a2 : NOR3B - port map(A => \addr_data_vector[44]\, B => m20_N_17_i_0, C - => m36_m6_0_a2_4_i, Y => N_37_0); - - \address_RNO_2[31]\ : NOR3B - port map(A => address_7_31_m6_e_3, B => address_7_31_m6_e_2, - C => \state_0[0]_net_1\, Y => \address_RNO_2[31]_net_1\); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[61]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[50]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f1(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f1(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f1(0), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - \addr_data_vector[32]\); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m36_m6_0_a2_4_2 : NOR2B - port map(A => \addr_data_vector[48]\, B => - \addr_data_vector[49]\, Y => m36_m6_0_a2_4_2); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f1(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[36]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[60]\); - - un1_address_m1 : NOR3A - port map(A => \addr_data_vector[34]\, B => - \un1_state_12_2[4]\, C => \un1_state_12_3_0[4]\, Y => N_2); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - un1_address_m17 : NOR2A - port map(A => \addr_data_vector[41]\, B => N_16_0, Y => - N_18_0); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3B - port map(A => N_131, B => N_129, C => \state[3]_net_1\, Y - => N_125); - - \address_RNO_1[31]\ : AX1E - port map(A => \addr_data_vector[56]\, B => N_41, C => - \addr_data_vector[63]\, Y => \address_RNO_1[31]_net_1\); - - un1_address_m20_m7_i_4 : OA1A - port map(A => address_0_sqmuxa, B => \addr_data_vector[38]\, - C => m20_m7_i_3, Y => m20_m7_i_4); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR3 - port map(A => address_0_sqmuxa, B => \addr_data_vector[38]\, - C => N_5_0, Y => \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f1(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[7]_net_1\); - - un1_address_m40_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[40]\, B => - \addr_data_vector[39]\, C => m40_m6_0_a2_3, Y => - m40_m6_0_a2_5); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f1(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address_RNIFA45[30]\ : MX2C - port map(A => \addr_data_vector[62]\, B => - addr_data_vector_94, S => sel_data(1), Y => N_913); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[46]\); - - \state_RNO[1]\ : OA1C - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - \address_RNIJ245[25]\ : MX2C - port map(A => \addr_data_vector[57]\, B => - addr_data_vector_89, S => sel_data(1), Y => N_908); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f1(14), S => - \state[0]_net_1\, Y => \address_7[14]\); - - un1_address_m20_m3_e_0 : NOR2B - port map(A => \addr_data_vector[36]\, B => - \addr_data_vector[37]\, Y => m20_m3_e_0); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[56]\); - - un1_address_m27 : XOR2 - port map(A => N_27_0, B => \addr_data_vector[48]\, Y => - N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \address_RNO_0[31]\ : MX2C - port map(A => \addr_data_vector[63]\, B => addr_data_f1(31), - S => \state_0[0]_net_1\, Y => \address_RNO_0[31]_net_1\); - - \address_RNILQ35[19]\ : MX2C - port map(A => \addr_data_vector[51]\, B => - addr_data_vector_83, S => sel_data(1), Y => N_902); - - un1_address_m60 : AX1C - port map(A => \addr_data_vector[56]\, B => N_41, C => - \addr_data_vector[57]\, Y => \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - un1_address_m36_m6_0_a2_4_5 : NOR3C - port map(A => \addr_data_vector[47]\, B => - \addr_data_vector[46]\, C => m36_m6_0_a2_4_2, Y => - m36_m6_0_a2_4_5); - - un1_address_m30 : NOR3C - port map(A => \addr_data_vector[48]\, B => N_27_0, C => - \addr_data_vector[49]\, Y => N_31_0); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[41]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3C - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[40]\); - - un1_address_m50 : XOR2 - port map(A => N_69, B => \addr_data_vector[36]\, Y => - N_51_i_0); - - un1_address_m39 : AX1B - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, C => \addr_data_vector[34]\, Y => - N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : NOR2A - port map(A => update_and_sel_5(2), B => update_and_sel_5(3), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f1(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f1(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f1(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - un1_address_m40_m6_0_a2_3 : NOR2B - port map(A => \addr_data_vector[41]\, B => - \addr_data_vector[42]\, Y => m40_m6_0_a2_3); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1C - port map(A => \addr_data_vector[54]\, B => N_37_0, C => - \addr_data_vector[55]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa, C => - \addr_data_vector[38]\, Y => N_13_0); - - un1_address_m59 : XOR2 - port map(A => N_41, B => \addr_data_vector[56]\, Y => - \un1_address[24]\); - - \address_RNIB245[21]\ : MX2C - port map(A => \addr_data_vector[53]\, B => - addr_data_vector_85, S => sel_data(1), Y => N_904); - - \update_r[0]\ : DFN1P0 - port map(D => update_and_sel_5(2), CLK => HCLK_c, PRE => - HRESETn_c, Q => \update_r_i[0]\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => m40_m6_0_a2_1, B => m40_m6_0_a2_0, C => - m40_m6_0_a2_5, Y => m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f1(17), S => - \state[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f1(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[39]\, B => - \addr_data_vector[40]\, C => N_13_0, Y => N_16_0); - - un1_address_m58 : XOR2 - port map(A => N_37_0, B => \addr_data_vector[54]\, Y => - \un1_address[22]\); - - \state_RNI40SU8[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - un1_address_m26 : NOR3C - port map(A => \addr_data_vector[46]\, B => N_24_0, C => - \addr_data_vector[47]\, Y => N_27_0); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f1(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address_RNO_4[31]\ : NOR2B - port map(A => \addr_data_vector[60]\, B => - \addr_data_vector[61]\, Y => address_7_31_m6_e_2); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[35]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XOR2 - port map(A => N_46, B => \addr_data_vector[61]\, Y => - \un1_address[29]\); - - un1_address_m34 : XOR2 - port map(A => N_34_0, B => \addr_data_vector[52]\, Y => - \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f1(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \address_RNI9245[20]\ : MX2C - port map(A => \addr_data_vector[52]\, B => - addr_data_vector_84, S => sel_data(1), Y => N_903); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(1), B => N_131, Y => - \state_ns_i_0[3]\); - - \state_RNITJCD[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : AX1C - port map(A => \addr_data_vector[44]\, B => m20_N_17_i_0, C - => \addr_data_vector[45]\, Y => N_55_0_i_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[39]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - un1_address_m25 : AX1C - port map(A => \addr_data_vector[46]\, B => N_24_0, C => - \addr_data_vector[47]\, Y => N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[3]_net_1\); - - \address_RNIG894[15]\ : MX2C - port map(A => \addr_data_vector[47]\, B => - addr_data_vector_79, S => sel_data_0(1), Y => N_1284); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_5(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => \update_r[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - \update_r_RNI1KV4_0[0]\ : OR2 - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => \un1_state_12_3_0[4]\); - - un1_address_m57 : AX1C - port map(A => \addr_data_vector[52]\, B => N_34_0, C => - \addr_data_vector[53]\, Y => \un1_address[21]\); - - un1_address_m20_m7_i_1 : NOR2B - port map(A => \addr_data_vector[40]\, B => - \addr_data_vector[41]\, Y => m20_m7_i_1); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - un1_address_m40_m6_0_a2 : NOR3A - port map(A => m40_m6_0_a2_6, B => m36_m6_0_a2_4_i, C => - N_13_0, Y => N_41); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f1(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : XOR2 - port map(A => N_2, B => \addr_data_vector[35]\, Y => - N_50_i_0); - - \address_RNIQNMA[3]\ : MX2C - port map(A => \addr_data_vector[35]\, B => - addr_data_vector_67, S => sel_data_0(1), Y => N_1300); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[41]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f1(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - \address_RNIKVLA[0]\ : MX2C - port map(A => \addr_data_vector[32]\, B => - addr_data_vector_64, S => sel_data_0(1), Y => N_1297); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNI8894[11]\ : MX2C - port map(A => \addr_data_vector[43]\, B => - addr_data_vector_75, S => sel_data_0(1), Y => N_1294); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f1(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[38]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - un1_address_m23 : NOR3C - port map(A => \addr_data_vector[44]\, B => m20_N_17_i_0, C - => \addr_data_vector[45]\, Y => N_24_0); - - status_full_err_RNO : AO1 - port map(A => \state[2]_net_1\, B => N_129, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f1(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address_RNIC894[13]\ : MX2C - port map(A => \addr_data_vector[45]\, B => - addr_data_vector_77, S => sel_data_0(1), Y => N_1282); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[43]\); - - un1_address_m20_m3_e : OR2B - port map(A => m20_m3_e_0, B => N_69, Y => m20_m3_e); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[63]\); - - un1_address_m36_m6_0_a2_4_6 : NOR3C - port map(A => \addr_data_vector[51]\, B => - \addr_data_vector[50]\, C => m36_m6_0_a2_4_4, Y => - m36_m6_0_a2_4_6); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : XOR2 - port map(A => N_31_0, B => \addr_data_vector[50]\, Y => - \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f1(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - un1_address_m44 : OR3B - port map(A => \addr_data_vector[58]\, B => - \addr_data_vector[59]\, C => N_43, Y => N_45); - - \address_RNIOFMA[2]\ : MX2C - port map(A => \addr_data_vector[34]\, B => - addr_data_vector_66, S => sel_data_0(1), Y => N_1299); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f1(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f1(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[53]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - un1_address_m62 : AX1 - port map(A => N_43, B => \addr_data_vector[58]\, C => - \addr_data_vector[59]\, Y => \un1_address[27]\); - - un1_address_m32 : AX1C - port map(A => \addr_data_vector[50]\, B => N_31_0, C => - \addr_data_vector[51]\, Y => \un1_address[19]\); - - un1_address_m12_e : OR3C - port map(A => \addr_data_vector[36]\, B => N_69, C => - \addr_data_vector[37]\, Y => N_5_0); - - \address_RNO_5[31]\ : NOR2B - port map(A => \addr_data_vector[58]\, B => - \addr_data_vector[59]\, Y => address_7_31_m6_e_1); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[1]_net_1\); - - \address_RNIF245[23]\ : MX2C - port map(A => \addr_data_vector[55]\, B => - addr_data_vector_87, S => sel_data(1), Y => N_906); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[49]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - \state_RNI40SU8_0[3]\ : OR2B - port map(A => address_0_sqmuxa_0, B => state7, Y => - address_0_sqmuxa); - - un1_address_m65 : AX1C - port map(A => \addr_data_vector[61]\, B => N_46, C => - \addr_data_vector[62]\, Y => \un1_address[30]\); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[39]\, Y => - N_1_i_0); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[59]\); - - \state_RNO[3]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : XOR2 - port map(A => m20_N_17_i_0, B => \addr_data_vector[44]\, Y - => N_22_0_i_0); - - un1_address_m20_m7_i_3 : NOR3C - port map(A => m20_m7_i_0, B => \addr_data_vector[42]\, C - => m20_m7_i_1, Y => m20_m7_i_3); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : XOR2 - port map(A => N_24_0, B => \addr_data_vector[46]\, Y => - N_56_0_i_0); - - \address_RNO[31]\ : MX2C - port map(A => \address_RNO_0[31]_net_1\, B => - \address_RNO_1[31]_net_1\, S => \address_RNO_2[31]_net_1\, - Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m20_m7_i_o5 : OR2A - port map(A => \addr_data_vector[38]\, B => address_0_sqmuxa, - Y => m20_m7_i_o5); - - un1_address_m10_e : NOR2B - port map(A => N_2, B => \addr_data_vector[35]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f1(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - \address_RNIK894[17]\ : MX2C - port map(A => \addr_data_vector[49]\, B => - addr_data_vector_81, S => sel_data_0(1), Y => N_1286); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \state_RNIEABE[1]\ : NOR2A - port map(A => status_full_ack(1), B => N_131, Y => N_118); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f1(1), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - \addr_data_vector[33]\); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_11, Q => status_full(1)); - - \update_r_RNI1KV4[0]\ : OR2B - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => un3_update_r); - - un1_address_m63 : XNOR2 - port map(A => N_45, B => \addr_data_vector[60]\, Y => - \un1_address[28]\); - - un1_address_m33 : NOR3C - port map(A => \addr_data_vector[50]\, B => N_31_0, C => - \addr_data_vector[51]\, Y => N_34_0); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNID245[22]\ : MX2C - port map(A => \addr_data_vector[54]\, B => - addr_data_vector_86, S => sel_data(1), Y => N_905); - - \address_RNIM7MA[1]\ : MX2C - port map(A => \addr_data_vector[33]\, B => - addr_data_vector_65, S => sel_data_0(1), Y => N_1298); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f1(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : XOR2 - port map(A => N_18_0, B => \addr_data_vector[42]\, Y => - N_54_0_i_0); - - un1_address_m40_m6_0_a2_0 : NOR2B - port map(A => \addr_data_vector[55]\, B => - \addr_data_vector[43]\, Y => m40_m6_0_a2_0); - - un1_address_m40_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[44]\, B => - \addr_data_vector[54]\, Y => m40_m6_0_a2_1); - - \address_RNO_3[31]\ : NOR3C - port map(A => \addr_data_vector[57]\, B => - \addr_data_vector[62]\, C => address_7_31_m6_e_1, Y => - address_7_31_m6_e_3); - - \state_RNI14MB[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => un3_update_r, Y => - address_0_sqmuxa_0); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[3]_net_1\, C - => \state[2]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f1(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un1_address_m20_m7_i : AOI1B - port map(A => m20_m7_i_o5, B => m20_m3_e, C => m20_m7_i_4, - Y => m20_N_17_i_0); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - un1_address_m42 : OR3C - port map(A => \addr_data_vector[56]\, B => N_41, C => - \addr_data_vector[57]\, Y => N_43); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - \address_RNIN245[27]\ : MX2C - port map(A => \addr_data_vector[59]\, B => - addr_data_vector_91, S => sel_data(1), Y => N_910); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_dma_send_1word is - - port( Lock : out std_logic; - Request : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - un1_time_send_ok : out std_logic; - time_select : in std_logic; - Store : in std_logic; - N_1012 : out std_logic; - Ready : in std_logic; - Fault : in std_logic; - time_send : in std_logic; - Grant : in std_logic - ); - -end lpp_dma_send_1word; - -architecture DEF_ARCH of lpp_dma_send_1word is - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un1_state_4_i_0, \state[1]_net_1\, \state[3]_net_1\, - \state_ns_i_a4_0[0]\, \state[0]_net_1\, \state[2]_net_1\, - un1_state_2, N_69, \state[4]_net_1\, N_66, N_58, N_60, - \state_ns[1]\, Request_4, N_61, Store_0, \state_ns[2]\, - \state_RNO[4]_net_1\, time_send_ok, time_send_ko, - \state_ns[3]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \state_RNI4AM7[1]\ : OR2 - port map(A => \state[1]_net_1\, B => \state[3]_net_1\, Y - => un1_state_4_i_0); - - \state[1]\ : DFN1C0 - port map(D => \state_ns[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - \state_RNIFCT8[4]\ : NOR2B - port map(A => time_send, B => \state[4]_net_1\, Y => - Request_4); - - GND_i_0 : GND - port map(Y => GND_0); - - \state_RNIAJH31[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => Grant, Y => N_66); - - \state_RNI6OUR[2]\ : NOR2A - port map(A => \state[2]_net_1\, B => N_61, Y => N_69); - - un1_state_2_0_o3 : NOR2A - port map(A => Fault, B => Ready, Y => N_61); - - \state[4]\ : DFN1P0 - port map(D => \state_RNO[4]_net_1\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \DMAIn.Request\ : DFN1E1C0 - port map(D => Request_4, CLK => HCLK_c, CLR => HRESETn_c, E - => un1_state_2, Q => Request); - - VCC_i : VCC - port map(Y => \VCC\); - - \state_RNO[4]\ : OA1C - port map(A => time_send, B => \state_ns_i_a4_0[0]\, C => - N_58, Y => \state_RNO[4]_net_1\); - - \state_RNIKGB32[4]\ : OR3 - port map(A => N_69, B => \state[4]_net_1\, C => N_66, Y => - un1_state_2); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - send_ok : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_58, Q => time_send_ok); - - \state_RNO[1]\ : NOR2A - port map(A => \state[2]_net_1\, B => Fault, Y => - \state_ns[3]\); - - GND_i : GND - port map(Y => \GND\); - - \DMAIn.Store_RNIVI9A\ : MX2 - port map(A => Store, B => Store_0, S => time_select, Y => - N_1012); - - \state_RNO_0[4]\ : OR2 - port map(A => \state[0]_net_1\, B => \state[2]_net_1\, Y - => \state_ns_i_a4_0[0]\); - - \DMAIn.Store\ : DFN1E1C0 - port map(D => \state[4]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_2, Q => Store_0); - - \DMAIn.Lock\ : DFN1E1C0 - port map(D => time_send, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[4]_net_1\, Q => Lock); - - \state_RNO[2]\ : AO1 - port map(A => \state[2]_net_1\, B => N_61, C => N_66, Y => - \state_ns[2]\); - - \state_ns_i_o3[0]\ : NOR2B - port map(A => Ready, B => Fault, Y => N_60); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO[3]\ : AO1A - port map(A => Grant, B => \state[3]_net_1\, C => Request_4, - Y => \state_ns[1]\); - - send_ko_RNI8BV9 : OR2 - port map(A => time_send_ok, B => time_send_ko, Y => - un1_time_send_ok); - - send_ko : DFN1E0C0 - port map(D => \state[0]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_58, Q => time_send_ko); - - \state[0]\ : DFN1C0 - port map(D => \state[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[0]_net_1\); - - \state_RNIA2L31[2]\ : AO1A - port map(A => N_60, B => \state[2]_net_1\, C => - un1_state_4_i_0, Y => N_58); - - \state[3]\ : DFN1C0 - port map(D => \state_ns[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(3 to 3); - status_full : out std_logic_vector(3 to 3); - sel_data : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - update_and_sel_1 : in std_logic_vector(7 downto 6); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(3 to 3); - addr_data_vector_61 : out std_logic; - addr_data_vector_60 : out std_logic; - addr_data_vector_27 : in std_logic; - addr_data_vector_25 : in std_logic; - addr_data_vector_24 : in std_logic; - addr_data_vector_22 : in std_logic; - addr_data_vector_20 : in std_logic; - addr_data_vector_0 : in std_logic; - addr_data_vector_6 : in std_logic; - addr_data_vector_4 : in std_logic; - addr_data_vector_3 : in std_logic; - addr_data_vector_2 : in std_logic; - addr_data_vector_1 : in std_logic; - addr_data_vector_14 : in std_logic; - addr_data_vector_12 : in std_logic; - addr_data_vector_10 : in std_logic; - addr_data_vector_8 : in std_logic; - addr_data_vector_63 : out std_logic; - addr_data_vector_90 : out std_logic; - addr_data_vector_87 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_62 : out std_logic; - addr_data_vector_69 : out std_logic; - addr_data_vector_73 : out std_logic; - addr_data_vector_71 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_83 : out std_logic; - addr_data_vector_75 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_81 : out std_logic; - N_914 : out std_logic; - N_912 : out std_logic; - N_911 : out std_logic; - N_909 : out std_logic; - N_907 : out std_logic; - N_1301 : out std_logic; - N_1293 : out std_logic; - N_1291 : out std_logic; - N_1290 : out std_logic; - N_1289 : out std_logic; - N_1288 : out std_logic; - N_1287 : out std_logic; - N_1285 : out std_logic; - N_1283 : out std_logic; - N_1281 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, \state_RNIKABE[1]_net_1\, N_38, - \nb_send[1]_net_1\, \nb_send[0]_net_1\, N_30, - \nb_send[3]_net_1\, \DWACT_FINC_E[0]\, N_7, - \nb_send[8]_net_1\, \DWACT_FINC_E[4]\, m40_m6_0_a2_7, - m40_m6_0_a2_2, m40_m6_0_a2_1, m40_m6_0_a2_6, - m40_m6_0_a2_4, \addr_data_vector[114]\, - \addr_data_vector[112]\, m24_m5_0_a2_5, - \addr_data_vector[106]\, m24_m5_0_a2_3, m24_m5_0_a2_4, - \addr_data_vector[103]\, \addr_data_vector[110]\, - m24_m5_0_a2_1, \addr_data_vector[108]\, - \addr_data_vector[104]\, \un1_state_12_3_0[4]\, - \update_r_i[0]\, \update_r[1]_net_1\, un1_state_5_i_0, - \state[4]_net_1\, \state[3]_net_1\, \state_ns_i_0[3]\, - N_131, \un1_state_12[4]\, \un1_state_12_2[4]\, - \un1_address[6]\, address_0_sqmuxa, - \addr_data_vector[102]\, N_5_0, \state_RNO[1]_net_1\, - N_129, \state[1]_net_1\, \state_ns[0]\, N_125, N_124, - N_110, \state[2]_net_1\, state7, un3_update_r, N_25_0_i_0, - N_13_0, N_15_0_i_0, N_16_0, N_17_0_i_0, - \addr_data_vector[105]\, N_19_0, N_20_0_i_0, - \addr_data_vector[107]\, N_22_0_i_0, N_23_0, N_26_0_i_0, - \addr_data_vector[111]\, N_28_0_i_0, N_29_0, N_30_0_i_0, - \addr_data_vector[113]\, N_32_0, N_33_0, - \addr_data_vector[115]\, N_35_0, \addr_data_vector[116]\, - N_36_0, N_37_0, \addr_data_vector[117]\, N_39, - \addr_data_vector[118]\, \addr_data_vector[119]\, - N_40_i_0, N_42, \addr_data_vector[120]\, N_44, - \addr_data_vector[122]\, N_46, \addr_data_vector[124]\, - N_47, \addr_data_vector[125]\, N_49_i_0, - \addr_data_vector[127]\, N_50_i_0, \addr_data_vector[98]\, - N_51_i_0, N_69, \addr_data_vector[100]\, N_52_i_0, - \addr_data_vector[101]\, N_1_i_0, N_54_0_i_0, N_55_0_i_0, - \addr_data_vector[109]\, N_57_0, N_58_0, N_59_0, N_60_0, - N_61_0, \addr_data_vector[121]\, N_62, N_63_0, - \addr_data_vector[123]\, N_64_0, N_65_0, N_66_0, - \addr_data_vector[126]\, \addr_data_vector[99]\, - \address_7[2]\, \address_7[3]\, \address_7[4]\, - \address_7[5]\, \address_7[6]\, \address_7[7]\, - \address_7[8]\, \address_7[9]\, \address_7[10]\, - \address_7[11]\, \address_7[12]\, \address_7[13]\, - \address_7[15]\, \address_7[16]\, \address_7[17]\, - \address_7[18]\, \address_7[19]\, \state[0]_net_1\, - \address_7[20]\, \address_7[21]\, \address_7[22]\, - \address_7[23]\, \address_7[24]\, \address_7[25]\, - \address_7[26]\, \address_7[27]\, \address_7[28]\, - \address_7[29]\, \address_7[30]\, \address_7[31]\, - N_56_0_i_0, un1_state_9, \nb_send_5[0]\, \nb_send_5[1]\, - I_5_19, \nb_send_5[2]\, I_9_19, \nb_send_5[3]\, I_13_19, - \nb_send_5[4]\, I_20_11, \nb_send_5[5]\, I_24_3, - \nb_send_5[6]\, I_31_4, \nb_send_5[7]\, I_38_3, - \nb_send_5[8]\, I_45_3, \nb_send_5[9]\, I_52_3, - \nb_send_5[10]\, I_56_3, N_127, \state_RNO_0[3]\, - \state_ns[2]\, un1_state_11, \address_7[14]\, - \nb_send[2]_net_1\, \nb_send[4]_net_1\, - \nb_send[5]_net_1\, \nb_send[6]_net_1\, - \nb_send[7]_net_1\, \nb_send[9]_net_1\, - \nb_send[10]_net_1\, N_4, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[3]\, N_12, N_17, N_22, \DWACT_FINC_E[1]\, - N_27, N_35, \DWACT_COMP0_E[1]\, \DWACT_COMP0_E[2]\, - \DWACT_COMP0_E[0]\, \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_1, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_63 <= \addr_data_vector[99]\; - addr_data_vector_90 <= \addr_data_vector[126]\; - addr_data_vector_87 <= \addr_data_vector[123]\; - addr_data_vector_85 <= \addr_data_vector[121]\; - addr_data_vector_62 <= \addr_data_vector[98]\; - addr_data_vector_69 <= \addr_data_vector[105]\; - addr_data_vector_73 <= \addr_data_vector[109]\; - addr_data_vector_71 <= \addr_data_vector[107]\; - addr_data_vector_77 <= \addr_data_vector[113]\; - addr_data_vector_79 <= \addr_data_vector[115]\; - addr_data_vector_82 <= \addr_data_vector[118]\; - addr_data_vector_83 <= \addr_data_vector[119]\; - addr_data_vector_75 <= \addr_data_vector[111]\; - addr_data_vector_80 <= \addr_data_vector[116]\; - addr_data_vector_81 <= \addr_data_vector[117]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[112]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[106]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNIKABE[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[126]\); - - un1_address_m45 : OR3B - port map(A => \addr_data_vector[123]\, B => - \addr_data_vector[124]\, C => N_44, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => N_62, B => addr_data_f3(26), S => - \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => I_52_3, B => nb_burst_available(9), C => N_31, - Y => N_36); - - un1_address_m61 : AX1 - port map(A => N_42, B => \addr_data_vector[121]\, C => - \addr_data_vector[122]\, Y => N_62); - - un1_address_m31 : OR3B - port map(A => \addr_data_vector[113]\, B => - \addr_data_vector[114]\, C => N_29_0, Y => N_32_0); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[122]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[116]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => I_20_11, B => nb_burst_available(4), C => - I_24_3, Y => \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3B - port map(A => N_129, B => \state[2]_net_1\, C => - status_full_ack(3), Y => N_127); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1C - port map(A => \addr_data_vector[100]\, B => N_69, C => - \addr_data_vector[101]\, Y => N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[108]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => I_52_3, B => nb_burst_available(9), C => N_29, - Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => N_65_0, B => addr_data_f3(29), S => - \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XOR2 - port map(A => N_19_0, B => \addr_data_vector[107]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[118]\); - - \address_RNO[23]\ : MX2 - port map(A => N_39, B => addr_data_f3(23), S => - \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[98]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => I_13_19); - - un1_address_m43 : OR3B - port map(A => \addr_data_vector[121]\, B => - \addr_data_vector[122]\, C => N_42, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => N_60_0, B => addr_data_f3(24), S => - \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f3(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_110, Q => status_full_err(3)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : NOR3C - port map(A => \addr_data_vector[105]\, B => N_16_0, C => - \addr_data_vector[106]\, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => I_5_19, B => state7, Y => \nb_send_5[1]\); - - \address_RNIA894[12]\ : MX2C - port map(A => addr_data_vector_8, B => - \addr_data_vector[108]\, S => sel_data_0(1), Y => N_1281); - - \address_RNI40OA[8]\ : MX2C - port map(A => addr_data_vector_4, B => - \addr_data_vector[104]\, S => sel_data_0(1), Y => N_1291); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => I_31_4); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f3(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[101]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => I_38_3, B => nb_burst_available(7), Y => - \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[111]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[109]\); - - \update_r_RNI5KV4[0]\ : OR2B - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => un3_update_r); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => I_52_3, B => state7, Y => \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[115]\); - - \address_RNII894[16]\ : MX2C - port map(A => addr_data_vector_12, B => - \addr_data_vector[112]\, S => sel_data_0(1), Y => N_1285); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[121]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address_RNIL245[26]\ : MX2C - port map(A => addr_data_vector_22, B => - \addr_data_vector[122]\, S => sel_data(1), Y => N_909); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[119]\); - - un1_address_m14 : AX1C - port map(A => \addr_data_vector[103]\, B => N_13_0, C => - \addr_data_vector[104]\, Y => N_15_0_i_0); - - un1_address_m29 : XNOR2 - port map(A => N_29_0, B => \addr_data_vector[113]\, Y => - N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => I_31_4, Y => - N_30_0); - - \address_RNIH245[24]\ : MX2C - port map(A => addr_data_vector_20, B => - \addr_data_vector[120]\, S => sel_data(1), Y => N_907); - - \state_RNIKABE[1]\ : NOR2A - port map(A => status_full_ack(3), B => N_131, Y => - \state_RNIKABE[1]_net_1\); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[125]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[114]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => I_31_4, B => state7, Y => \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => N_58_0, B => addr_data_f3(21), S => - \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f3(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f3(0), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - addr_data_vector_60); - - un1_address_m28 : OR3B - port map(A => \addr_data_vector[111]\, B => - \addr_data_vector[112]\, C => N_25_0_i_0, Y => N_29_0); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : OR3B - port map(A => m40_m6_0_a2_7, B => \addr_data_vector[120]\, - C => N_25_0_i_0, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => N_63_0, B => addr_data_f3(27), S => - \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[100]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[124]\); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \nb_send_RNO[2]\ : NOR2B - port map(A => I_9_19, B => state7, Y => \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3B - port map(A => N_131, B => N_129, C => \state[3]_net_1\, Y - => N_125); - - \address_RNI6894[10]\ : MX2C - port map(A => addr_data_vector_6, B => - \addr_data_vector[106]\, S => sel_data_0(1), Y => N_1293); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => I_9_19, B => nb_burst_available(2), Y => - \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => I_38_3, B => state7, Y => \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => I_24_3); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XNOR3 - port map(A => address_0_sqmuxa, B => - \addr_data_vector[102]\, C => N_5_0, Y => - \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => N_33_0, B => addr_data_f3(19), S => - \state[0]_net_1\, Y => \address_7[19]\); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f3(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[110]\); - - \state_RNO[1]\ : OA1C - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => \state_RNO[1]_net_1\); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[0]_net_1\); - - \state_RNILNSP8[3]\ : OR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => I_5_19, Y => - \ACT_LT4_E[2]\); - - un1_address_m40_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[111]\, B => - \addr_data_vector[119]\, C => \addr_data_vector[118]\, Y - => m40_m6_0_a2_4); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => I_13_19, Y => - \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f3(14), S => - \state[0]_net_1\, Y => \address_7[14]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => I_13_19, B => state7, Y => \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_1, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[120]\); - - un1_address_m27 : AX1 - port map(A => N_25_0_i_0, B => \addr_data_vector[111]\, C - => \addr_data_vector[112]\, Y => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[121]\, Y => - N_61_0); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XOR2 - port map(A => N_16_0, B => \addr_data_vector[105]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => I_45_3); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => I_45_3, B => state7, Y => \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => I_24_3, Y => - \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3C - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => I_52_3, B => nb_burst_available(9), Y => - \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[104]\); - - un1_address_m40_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[114]\, B => - \addr_data_vector[115]\, Y => m40_m6_0_a2_2); - - un1_address_m50 : XOR2 - port map(A => N_69, B => \addr_data_vector[100]\, Y => - N_51_i_0); - - un1_address_m39 : XOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[98]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => I_56_3, B => nb_burst_available(10), Y => - N_35_1); - - \state_ns_i_a2[1]\ : NOR2A - port map(A => update_and_sel_1(6), B => update_and_sel_1(7), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f3(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \update_r_RNIQBSU8[0]\ : NOR2 - port map(A => \un1_state_12_3_0[4]\, B => - \un1_state_12_2[4]\, Y => \un1_state_12[4]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => N_64_0, B => addr_data_f3(28), S => - \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f3(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => I_38_3, C => - N_30_0, Y => N_32); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => I_24_3, B => nb_burst_available(5), Y => - \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => I_31_4, B => nb_burst_available(6), Y => - \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1C - port map(A => \addr_data_vector[118]\, B => N_37_0, C => - \addr_data_vector[119]\, Y => N_39); - - un1_address_m12 : AO13 - port map(A => address_0_sqmuxa, B => - \addr_data_vector[102]\, C => N_5_0, Y => N_13_0); - - un1_address_m59 : AX1 - port map(A => N_25_0_i_0, B => m40_m6_0_a2_7, C => - \addr_data_vector[120]\, Y => N_60_0); - - \update_r[0]\ : DFN1P0 - port map(D => update_and_sel_1(6), CLK => HCLK_c, PRE => - HRESETn_c, Q => \update_r_i[0]\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => I_5_19); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[117]\, B => - \addr_data_vector[116]\, C => m40_m6_0_a2_4, Y => - m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f3(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f3(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : NOR3C - port map(A => \addr_data_vector[103]\, B => N_13_0, C => - \addr_data_vector[104]\, Y => N_16_0); - - un1_address_m58 : XOR2 - port map(A => N_37_0, B => \addr_data_vector[118]\, Y => - N_59_0); - - \address_RNIU7NA[5]\ : MX2C - port map(A => addr_data_vector_1, B => - \addr_data_vector[101]\, S => sel_data_0(1), Y => N_1288); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => I_56_3); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f3(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[99]\); - - \address_RNIR245[29]\ : MX2C - port map(A => addr_data_vector_25, B => - \addr_data_vector[125]\, S => sel_data(1), Y => N_912); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XNOR2 - port map(A => N_46, B => \addr_data_vector[125]\, Y => - N_65_0); - - un1_address_m34 : AX1 - port map(A => N_32_0, B => \addr_data_vector[115]\, C => - \addr_data_vector[116]\, Y => N_35_0); - - \address_RNO[30]\ : MX2 - port map(A => N_66_0, B => addr_data_f3(30), S => - \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(3), B => N_131, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[3]_net_1\); - - \state_RNIQBSU8_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => I_56_3, Y => - N_31); - - un1_address_m54 : XOR2 - port map(A => N_23_0, B => \addr_data_vector[109]\, Y => - N_55_0_i_0); - - un1_address_m22 : NOR3C - port map(A => \addr_data_vector[107]\, B => N_19_0, C => - \addr_data_vector[108]\, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[103]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => I_38_3); - - un1_address_m24_m5_0_a2_1 : NOR2B - port map(A => \addr_data_vector[104]\, B => - \addr_data_vector[105]\, Y => m24_m5_0_a2_1); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => I_24_3, B => state7, Y => \nb_send_5[5]\); - - un1_address_m25 : XNOR2 - port map(A => N_25_0_i_0, B => \addr_data_vector[111]\, Y - => N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_0[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_1(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => \update_r[1]_net_1\); - - un1_address_m40_m6_0_a2_7 : NOR3C - port map(A => m40_m6_0_a2_2, B => m40_m6_0_a2_1, C => - m40_m6_0_a2_6, Y => m40_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => I_38_3, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => I_20_11, B => nb_burst_available(4), C => - nb_burst_available(5), Y => \ACT_LT2_E[2]\); - - un1_address_m57 : XNOR2 - port map(A => N_36_0, B => \addr_data_vector[117]\, Y => - N_58_0); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => I_45_3, B => nb_burst_available(8), C => N_28, - Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNI0GNA[6]\ : MX2C - port map(A => addr_data_vector_2, B => - \addr_data_vector[102]\, S => sel_data_0(1), Y => N_1289); - - \address_RNO[22]\ : MX2 - port map(A => N_59_0, B => addr_data_f3(22), S => - \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1C - port map(A => \addr_data_vector[98]\, B => - \un1_state_12[4]\, C => \addr_data_vector[99]\, Y => - N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[105]\); - - \address_RNO[18]\ : MX2 - port map(A => N_57_0, B => addr_data_f3(18), S => - \state_0[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f3(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[126]\, B => N_47, C => - \addr_data_vector[127]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[102]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => I_13_19, B => nb_burst_available(3), Y => - \ACT_LT4_E[8]\); - - \address_RNISVMA[4]\ : MX2C - port map(A => addr_data_vector_0, B => - \addr_data_vector[100]\, S => sel_data_0(1), Y => N_1301); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => I_56_3, B => nb_burst_available(10), Y => - \DWACT_BL_EQUAL_0_E[4]\); - - status_full_err_RNO : AO1 - port map(A => \state[2]_net_1\, B => N_129, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => \state_RNIKABE[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f3(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - \state_RNIQBSU8[3]\ : NOR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa); - - un1_address_m36 : NOR2A - port map(A => \addr_data_vector[117]\, B => N_36_0, Y => - N_37_0); - - \state_RNI1KCD[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - \address_RNIP245[28]\ : MX2C - port map(A => addr_data_vector_24, B => - \addr_data_vector[124]\, S => sel_data(1), Y => N_911); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => I_52_3); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[107]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[127]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => I_9_19, Y => - \ACT_LT4_E[4]\); - - un1_address_m56 : AX1 - port map(A => N_29_0, B => \addr_data_vector[113]\, C => - \addr_data_vector[114]\, Y => N_57_0); - - \address_RNIE894[14]\ : MX2C - port map(A => addr_data_vector_10, B => - \addr_data_vector[110]\, S => sel_data_0(1), Y => N_1283); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f3(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f3(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => N_61_0, B => addr_data_f3(25), S => - \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[117]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - un1_address_m62 : XNOR2 - port map(A => N_44, B => \addr_data_vector[123]\, Y => - N_63_0); - - un1_address_m32 : XNOR2 - port map(A => N_32_0, B => \addr_data_vector[115]\, Y => - N_33_0); - - un1_address_m12_e : OR3C - port map(A => \addr_data_vector[100]\, B => N_69, C => - \addr_data_vector[101]\, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => I_9_19); - - \state[1]\ : DFN1C0 - port map(D => \state_RNO[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - un1_address_m24_m5_0_a2 : OR3C - port map(A => m24_m5_0_a2_5, B => m24_m5_0_a2_4, C => - N_13_0, Y => N_25_0_i_0); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[113]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => I_5_19, Y => - \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[126]\, Y => - N_66_0); - - un1_address_m35 : OR3B - port map(A => \addr_data_vector[115]\, B => - \addr_data_vector[116]\, C => N_32_0, Y => N_36_0); - - un1_address_m52 : XOR2 - port map(A => N_13_0, B => \addr_data_vector[103]\, Y => - N_1_i_0); - - un1_address_m24_m5_0_a2_5 : NOR3C - port map(A => \addr_data_vector[107]\, B => - \addr_data_vector[106]\, C => m24_m5_0_a2_3, Y => - m24_m5_0_a2_5); - - \address_RNIM894[18]\ : MX2C - port map(A => addr_data_vector_14, B => - \addr_data_vector[114]\, S => sel_data_0(1), Y => N_1287); - - un1_address_m24_m5_0_a2_3 : NOR2B - port map(A => \addr_data_vector[108]\, B => - \addr_data_vector[109]\, Y => m24_m5_0_a2_3); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[123]\); - - \state_RNO[3]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_129, Y => - \state_RNO_0[3]\); - - un1_address_m21 : AX1C - port map(A => \addr_data_vector[107]\, B => N_19_0, C => - \addr_data_vector[108]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => I_20_11, B => state7, Y => \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => I_56_3, B => state7, Y => \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => I_45_3, B => nb_burst_available(8), Y => N_29); - - un1_address_m55 : AX1C - port map(A => \addr_data_vector[109]\, B => N_23_0, C => - \addr_data_vector[110]\, Y => N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f3(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \address_RNI2ONA[7]\ : MX2C - port map(A => addr_data_vector_3, B => - \addr_data_vector[103]\, S => sel_data_0(1), Y => N_1290); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : NOR3C - port map(A => \addr_data_vector[98]\, B => - \un1_state_12[4]\, C => \addr_data_vector[99]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => I_20_11, B => nb_burst_available(4), Y => - \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f3(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - \update_r_RNI5KV4_0[0]\ : OR2 - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => \un1_state_12_3_0[4]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => I_45_3, B => nb_burst_available(8), Y => - \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address_RNIHA45[31]\ : MX2C - port map(A => addr_data_vector_27, B => - \addr_data_vector[127]\, S => sel_data(1), Y => N_914); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f3(1), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - addr_data_vector_61); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_11, Q => status_full(3)); - - un1_address_m63 : AX1 - port map(A => N_44, B => \addr_data_vector[123]\, C => - \addr_data_vector[124]\, Y => N_64_0); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => N_35_0, B => addr_data_f3(20), S => - \state[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR2A - port map(A => \addr_data_vector[125]\, B => N_46, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : AX1C - port map(A => \addr_data_vector[105]\, B => N_16_0, C => - \addr_data_vector[106]\, Y => N_54_0_i_0); - - un1_address_m40_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[112]\, B => - \addr_data_vector[113]\, Y => m40_m6_0_a2_1); - - un1_address_m24_m5_0_a2_4 : NOR3C - port map(A => \addr_data_vector[103]\, B => - \addr_data_vector[110]\, C => m24_m5_0_a2_1, Y => - m24_m5_0_a2_4); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[3]_net_1\, C - => \state[2]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f3(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => I_20_11); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity DMA2AHB is - - port( hburst_c : out std_logic_vector(2 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - un7_dmain : in std_logic_vector(66 to 66); - hsize_c : out std_logic_vector(1 downto 0); - AHB_Master_In_c_5 : in std_logic; - AHB_Master_In_c_4 : in std_logic; - AHB_Master_In_c_0 : in std_logic; - AHB_Master_In_c_3 : in std_logic; - haddr_c : out std_logic_vector(31 downto 0); - hwrite_c : out std_logic; - Ready : out std_logic; - N_1012 : in std_logic; - Grant : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - OKAY : out std_logic; - Fault : out std_logic; - N_1011 : in std_logic; - N_1013 : in std_logic; - N_43 : out std_logic; - time_select_0 : in std_logic; - N_960 : in std_logic; - N_959 : in std_logic; - N_958 : in std_logic; - N_957 : in std_logic; - N_964 : in std_logic; - N_963 : in std_logic; - N_962 : in std_logic; - N_961 : in std_logic; - N_955 : in std_logic; - N_954 : in std_logic; - N_953 : in std_logic; - N_952 : in std_logic; - N_951 : in std_logic; - N_950 : in std_logic; - N_949 : in std_logic; - N_948 : in std_logic; - N_947 : in std_logic; - N_956 : in std_logic; - N_965 : in std_logic; - N_966 : in std_logic; - N_967 : in std_logic; - N_968 : in std_logic; - N_969 : in std_logic; - N_970 : in std_logic; - N_971 : in std_logic; - N_972 : in std_logic; - N_973 : in std_logic; - N_974 : in std_logic; - N_975 : in std_logic; - N_976 : in std_logic; - N_977 : in std_logic; - HRESETn_c : in std_logic; - N_978 : in std_logic; - HCLK_c : in std_logic - ); - -end DMA2AHB; - -architecture DEF_ARCH of DMA2AHB is - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \htrans_12_i_o2_2_5[0]\, \htrans_12_i_o2_2_2[0]\, - \htrans_12_i_o2_2_4[0]\, \htrans_12_i_o2_2_0[0]\, N_183, - N_556_i_0, N_58_0, \Address_0_i_1[29]\, N_181, - \un1_AddressSave_0_sqmuxa_1_i_i[29]\, \Address_0_i_1[28]\, - N_179, N_37, \Address_0_i_1[26]\, N_177, N_35, - \Address_0_i_1[25]\, N_175, N_33_0, \Address_0_i_1[24]\, - N_173, N_55_0, \Address_0_i_1[23]\, N_128, N_556_i, - N_56_0, \Address_0_i_1[27]\, N_30, - \un1_AddressSave_0_sqmuxa_1_i_i[32]\, \Address_0_i_1[31]\, - N_28, N_42, \Address_0_i_1[30]\, N_13_0, N_580, N_15_0, - N_18_0, N_22_0, N_26_0, N_29_0, N_32_0, \haddr_c[24]\, - N_36, \haddr_c[25]\, N_39, \haddr_c[26]\, N_41, - \haddr_c[22]\, \haddr_c[23]\, \haddr_c[27]\, - \haddr_c[28]\, \haddr_c[29]\, \haddr_c[30]\, N_566, - \AddressPhase\, \AddressPhase_0\, N_191, hsize_0_sqmuxa_0, - N_756, N_754_0, \ReDataPhase\, N_553, N_753_0, N_555, - N_557, \Address_0_i_0[31]\, \AddressSave[31]_net_1\, - \Address_0_i_0[30]\, \AddressSave[30]_net_1\, - \Address_0_i_0[29]\, \AddressSave[29]_net_1\, - \Address_0_i_0[28]\, \AddressSave[28]_net_1\, - \Address_0_i_0[27]\, \AddressSave[27]_net_1\, - \Address_0_i_0[26]\, \AddressSave[26]_net_1\, - \Address_0_i_0[25]\, \AddressSave[25]_net_1\, - \Address_0_i_0[24]\, \AddressSave[24]_net_1\, - \Address_0_i_0[23]\, \AddressSave[23]_net_1\, - \Address_0_i_1[22]\, \Address_0_i_0[22]\, - \AddressSave[22]_net_1\, \Address_0_i_1[21]\, - \Address_0_i_0[21]\, \AddressSave[21]_net_1\, - \Address_0_i_1[20]\, \Address_0_i_0[20]\, - \AddressSave[20]_net_1\, \Address_0_i_1[19]\, - \Address_0_i_0[19]\, \AddressSave[19]_net_1\, - \Address_0_i_1[18]\, \Address_0_i_0[18]\, - \AddressSave[18]_net_1\, \Address_0_i_1[9]\, - \Address_0_i_0[9]\, \AddressSave[9]_net_1\, - \Address_0_i_1[0]\, \Address_0_i_0[0]\, - \AddressSave[0]_net_1\, \Address_0_i_1[1]\, N_753, - \Address_0_i_0[1]\, \AddressSave[1]_net_1\, N_754, - \Address_0_i_1[2]\, \Address_0_i_0[2]\, - \AddressSave[2]_net_1\, \Address_0_i_1[3]\, - \Address_0_i_0[3]\, \AddressSave[3]_net_1\, - \Address_0_i_1[4]\, \Address_0_i_0[4]\, - \AddressSave[4]_net_1\, \Address_0_i_1[5]\, - \Address_0_i_0[5]\, \AddressSave[5]_net_1\, - \Address_0_i_1[6]\, \Address_0_i_0[6]\, - \AddressSave[6]_net_1\, \Address_0_i_1[7]\, - \Address_0_i_0[7]\, \AddressSave[7]_net_1\, - \Address_0_i_1[8]\, \Address_0_i_0[8]\, - \AddressSave[8]_net_1\, \Address_0_i_1[14]\, - \Address_0_i_0[14]\, \AddressSave[14]_net_1\, - \Address_0_i_1[15]\, \Address_0_i_0[15]\, - \AddressSave[15]_net_1\, \Address_0_i_1[16]\, - \Address_0_i_0[16]\, \AddressSave[16]_net_1\, - \Address_0_i_1[17]\, \Address_0_i_0[17]\, - \AddressSave[17]_net_1\, \Address_0_i_1[10]\, - \Address_0_i_0[10]\, \AddressSave[10]_net_1\, - \Address_0_i_1[11]\, \Address_0_i_0[11]\, - \AddressSave[11]_net_1\, \Address_0_i_1[12]\, - \Address_0_i_0[12]\, \AddressSave[12]_net_1\, - \Address_0_i_1[13]\, \Address_0_i_0[13]\, - \AddressSave[13]_net_1\, \hsize_1_i_0[0]\, - BoundaryPhase_2_i_1, N_686, N_684, \hsize_1_i_0[1]\, - \htrans_12_i_2[0]\, \htrans_12_i_0[0]\, N_678, N_675, - \hsize_1_i_a5_0[1]\, \hsize_c[1]\, un1_ahbin_3_0_0, N_561, - \hburst_11_i_a2_i_a5_1[1]\, \ReAddrPhase\, - \hburst_11_0_a2_i_2[0]\, \hburst_11_0_a2_i_0[0]\, N_643, - N_563, \SingleAcc\, N_559, \un1_dmain_20_i_0\, - ActivePhase_1_sqmuxa_i_a5_0, \DataPhase\, DataPhase_2_i_0, - N_576, Fault_0_a5_0, \Address_RNO[13]_net_1\, - \un1_AddressSave_0_sqmuxa_1_i_i[14]\, - \Address_RNO[12]_net_1\, - \un1_AddressSave_0_sqmuxa_1_i_i[13]\, - \Address_RNO[11]_net_1\, - \un1_AddressSave_0_sqmuxa_1_i_i[12]\, - \Address_RNO[10]_net_1\, - \un1_AddressSave_0_sqmuxa_1_i_i[11]\, N_171, - \un1_AddressSave_0_sqmuxa_1_i_i[23]\, N_169, - \un1_AddressSave_0_sqmuxa_1_i_i[22]\, N_167, - \un1_AddressSave_0_sqmuxa_1_i_i[21]\, N_165, - \un1_AddressSave_0_sqmuxa_1_i_i[20]\, N_163, - \un1_AddressSave_0_sqmuxa_1_i_i[19]\, N_161, - \un1_AddressSave_0_sqmuxa_1_i_i[18]\, N_159, - \un1_AddressSave_0_sqmuxa_1_i_i[17]\, N_157, - \un1_AddressSave_0_sqmuxa_1_i_i[16]\, N_155, - \un1_AddressSave_0_sqmuxa_1_i_i[15]\, N_153, - \un1_AddressSave_0_sqmuxa_1_i_i[9]\, N_151, N_569, N_126, - \un1_AddressSave_0_sqmuxa_1_i_i[8]\, N_124, - \un1_AddressSave_0_sqmuxa_1_i_i[7]\, N_122, - \un1_AddressSave_0_sqmuxa_1_i_i[6]\, N_120, - \un1_AddressSave_0_sqmuxa_1_i_i[5]\, N_118, - \un1_AddressSave_0_sqmuxa_1_i_i[4]\, N_116, - \un1_AddressSave_0_sqmuxa_1_i_i[3]\, N_114, N_112, N_26, - \un1_AddressSave_0_sqmuxa_1_i_i[10]\, N_137_i_0, - \htrans_RNO_1[0]\, N_676, N_20, hwrite_2_sqmuxa, N_560, - hwrite_2_sqmuxa_1, N_758, N_149, N_147_i_0, - \BoundaryPhase_RNO_1\, N_685, N_635, \IdlePhase\, N_829, - N_567, N_760, N_682, N_554, N_189, N_737, N_196, N_193, - N_614, N_738, N_139, N_680, N_679, un1_ahbin_3, N_568, - N_639, N_56_i_0, N_330, N_592, N_331, N_593, N_332, N_594, - N_333, N_595, N_334, N_586, N_335, N_587, N_336, N_588, - N_337, N_589, N_338, N_613, N_339, N_590, N_340, N_615, - N_341, N_616, N_342, N_617, N_343, N_618, N_344, N_596, - N_345, N_597, N_346, N_598, hsize_0_sqmuxa, N_347, N_599, - N_348, N_600, N_349, N_601, N_350, N_602, N_351, N_603, - N_352, N_604, N_353, N_605, N_354, N_606, N_355, N_607, - N_356, N_608, N_357, N_609, N_358, N_610, N_359, N_611, - N_360, N_612, N_361, N_591, \haddr_c[2]\, N_5_0, - \haddr_c[3]\, \haddr_c[4]\, N_3_0, N_7_0, \haddr_c[5]\, - \haddr_c[6]\, N_9_0, \haddr_c[7]\, \haddr_c[8]\, - \haddr_c[10]\, \haddr_c[14]\, \haddr_c[16]\, - \haddr_c[17]\, \haddr_c[18]\, \haddr_c[19]\, - \haddr_c[20]\, \haddr_c[21]\, \haddr_c[9]\, \haddr_c[11]\, - \haddr_c[12]\, \haddr_c[13]\, \haddr_c[15]\, N_213, N_215, - N_217, N_219, N_221, N_225, N_259, N_261, N_263, N_279, - N_281, N_283, N_285, N_287, N_289, N_291, N_293, N_295, - \AddressSave_RNO[2]_net_1\, \AddressSave_RNO[3]_net_1\, - N_512, N_514, N_516, N_518, N_520, N_522, N_524, N_526, - N_528, N_530, N_532, N_534, \haddr_c[31]\, \haddr_c[0]\, - \haddr_c[1]\, \EarlyPhase\, N_562, N_325, N_53, N_48, - \BoundaryPhase\, Retry, N_761, N_102, SingleAcc_2_sqmuxa, - N_104, N_322, N_326, N_329, N_22, N_100, N_558, - \ActivePhase\, \WriteAcc\, N_582, N_130, N_24, N_327, - N_108, N_320, N_106, N_321, \hsize_c[0]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - hsize_c(1) <= \hsize_c[1]\; - hsize_c(0) <= \hsize_c[0]\; - haddr_c(31) <= \haddr_c[31]\; - haddr_c(30) <= \haddr_c[30]\; - haddr_c(29) <= \haddr_c[29]\; - haddr_c(28) <= \haddr_c[28]\; - haddr_c(27) <= \haddr_c[27]\; - haddr_c(26) <= \haddr_c[26]\; - haddr_c(25) <= \haddr_c[25]\; - haddr_c(24) <= \haddr_c[24]\; - haddr_c(23) <= \haddr_c[23]\; - haddr_c(22) <= \haddr_c[22]\; - haddr_c(21) <= \haddr_c[21]\; - haddr_c(20) <= \haddr_c[20]\; - haddr_c(19) <= \haddr_c[19]\; - haddr_c(18) <= \haddr_c[18]\; - haddr_c(17) <= \haddr_c[17]\; - haddr_c(16) <= \haddr_c[16]\; - haddr_c(15) <= \haddr_c[15]\; - haddr_c(14) <= \haddr_c[14]\; - haddr_c(13) <= \haddr_c[13]\; - haddr_c(12) <= \haddr_c[12]\; - haddr_c(11) <= \haddr_c[11]\; - haddr_c(10) <= \haddr_c[10]\; - haddr_c(9) <= \haddr_c[9]\; - haddr_c(8) <= \haddr_c[8]\; - haddr_c(7) <= \haddr_c[7]\; - haddr_c(6) <= \haddr_c[6]\; - haddr_c(5) <= \haddr_c[5]\; - haddr_c(4) <= \haddr_c[4]\; - haddr_c(3) <= \haddr_c[3]\; - haddr_c(2) <= \haddr_c[2]\; - haddr_c(1) <= \haddr_c[1]\; - haddr_c(0) <= \haddr_c[0]\; - - \AHBOut.hwrite_RNO_0\ : OR2 - port map(A => \WriteAcc\, B => N_561, Y => N_680); - - \Address[16]\ : DFN1 - port map(D => N_159, CLK => HCLK_c, Q => \haddr_c[16]\); - - \Address[10]\ : DFN1 - port map(D => \Address_RNO[10]_net_1\, CLK => HCLK_c, Q => - \haddr_c[10]\); - - \Address_RNO_1[3]\ : OAI1 - port map(A => \AddressSave[3]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[3]\); - - \Address[30]\ : DFN1 - port map(D => N_28, CLK => HCLK_c, Q => \haddr_c[30]\); - - \AddressSave_RNO_0[30]\ : MX2 - port map(A => \AddressSave[30]_net_1\, B => N_612, S => - hsize_0_sqmuxa, Y => N_360); - - \AddressSave[8]\ : DFN1 - port map(D => N_283, CLK => HCLK_c, Q => - \AddressSave[8]_net_1\); - - \Address_RNO_1[0]\ : OAI1 - port map(A => \AddressSave[0]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[0]\); - - ReAddrPhase_RNIEV7K1 : NOR3B - port map(A => N_829, B => \hburst_11_i_a2_i_a5_1[1]\, C => - N_554, Y => N_682); - - \DMAOut.Fault_0_a5_0\ : NOR2A - port map(A => AHB_Master_In_c_4, B => AHB_Master_In_c_5, Y - => Fault_0_a5_0); - - \AHBOut.hsize_RNO[1]\ : OA1B - port map(A => N_569, B => \hsize_1_i_a5_0[1]\, C => - \hsize_1_i_0[1]\, Y => N_151); - - \Address_RNO[26]\ : OA1B - port map(A => N_556_i_0, B => N_37, C => - \Address_0_i_1[26]\, Y => N_179); - - \AddressSave_RNO_0[12]\ : MX2 - port map(A => \AddressSave[12]_net_1\, B => N_617, S => - hsize_0_sqmuxa_0, Y => N_342); - - \AddressSave_RNO_1[1]\ : MX2 - port map(A => N_948, B => \haddr_c[1]\, S => - \AddressPhase_0\, Y => N_593); - - un1_AddressSave_0_sqmuxa_1_m55 : AX1C - port map(A => \haddr_c[26]\, B => N_36, C => \haddr_c[27]\, - Y => N_56_0); - - EarlyPhase_RNIP1701 : NOR3B - port map(A => N_561, B => AHB_Master_In_c_3, C => N_1011, Y - => N_738); - - \Address_RNO[1]\ : OA1B - port map(A => \haddr_c[1]\, B => N_556_i, C => - \Address_0_i_1[1]\, Y => N_114); - - \AddressSave_RNO_0[10]\ : MX2 - port map(A => \AddressSave[10]_net_1\, B => N_615, S => - hsize_0_sqmuxa_0, Y => N_340); - - \AddressSave_RNO_0[27]\ : MX2 - port map(A => \AddressSave[27]_net_1\, B => N_609, S => - hsize_0_sqmuxa, Y => N_357); - - \AddressSave[15]\ : DFN1 - port map(D => N_287, CLK => HCLK_c, Q => - \AddressSave[15]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m50 : XOR2 - port map(A => N_13_0, B => \haddr_c[12]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[13]\); - - \Address[26]\ : DFN1 - port map(D => N_179, CLK => HCLK_c, Q => \haddr_c[26]\); - - \Address[20]\ : DFN1 - port map(D => N_167, CLK => HCLK_c, Q => \haddr_c[20]\); - - \AddressSave[12]\ : DFN1 - port map(D => N_285, CLK => HCLK_c, Q => - \AddressSave[12]_net_1\); - - \AddressSave_RNO_1[16]\ : MX2 - port map(A => N_963, B => \haddr_c[16]\, S => - \AddressPhase_0\, Y => N_598); - - \Address_RNO_1[8]\ : OAI1 - port map(A => \AddressSave[8]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[8]\); - - BoundaryPhase_RNO : NOR3C - port map(A => BoundaryPhase_2_i_1, B => - \BoundaryPhase_RNO_1\, C => N_685, Y => N_147_i_0); - - un1_AddressSave_0_sqmuxa_1_m31 : NOR3C - port map(A => \haddr_c[22]\, B => N_29_0, C => - \haddr_c[23]\, Y => N_32_0); - - IdlePhase_RNO : NOR2B - port map(A => N_326, B => HRESETn_c, Y => N_100); - - un1_AddressSave_0_sqmuxa_1_m47 : XNOR2 - port map(A => N_9_0, B => \haddr_c[9]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[10]\); - - \AHBOut.hsize[1]\ : DFN1 - port map(D => N_151, CLK => HCLK_c, Q => \hsize_c[1]\); - - ActivePhase_RNO_2 : OR2 - port map(A => \DataPhase\, B => \AddressPhase_0\, Y => - ActivePhase_1_sqmuxa_i_a5_0); - - \AHBOut.hburst_RNO_1[0]\ : AOI1B - port map(A => \SingleAcc\, B => N_559, C => - AHB_Master_In_c_0, Y => \hburst_11_0_a2_i_0[0]\); - - \Address_RNO_0[11]\ : AO1D - port map(A => N_958, B => N_753, C => \Address_0_i_0[11]\, - Y => \Address_0_i_1[11]\); - - \Address_RNO_0[8]\ : AO1D - port map(A => N_955, B => N_753, C => \Address_0_i_0[8]\, Y - => \Address_0_i_1[8]\); - - \Address_RNO_1[21]\ : OAI1 - port map(A => \AddressSave[21]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[21]\); - - \AHBOut.hwrite\ : DFN1E1 - port map(D => N_139, CLK => HCLK_c, E => N_130, Q => - hwrite_c); - - \Address[12]\ : DFN1 - port map(D => \Address_RNO[12]_net_1\, CLK => HCLK_c, Q => - \haddr_c[12]\); - - \AddressSave[23]\ : DFN1 - port map(D => N_526, CLK => HCLK_c, Q => - \AddressSave[23]_net_1\); - - \AddressSave_RNO_0[8]\ : MX2 - port map(A => \AddressSave[8]_net_1\, B => N_613, S => - hsize_0_sqmuxa_0, Y => N_338); - - \AddressSave_RNO_1[31]\ : MX2 - port map(A => N_978, B => \haddr_c[31]\, S => - \AddressPhase_0\, Y => N_591); - - \AddressSave_RNO[5]\ : NOR2B - port map(A => N_335, B => HRESETn_c, Y => N_281); - - \Address_RNO_1[11]\ : OAI1 - port map(A => \AddressSave[11]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[11]\); - - \AddressSave_RNO[18]\ : NOR2B - port map(A => N_348, B => HRESETn_c, Y => N_524); - - un1_AddressSave_0_sqmuxa_1_m41 : XOR2 - port map(A => N_41, B => \haddr_c[30]\, Y => N_42); - - \Address_RNO[29]\ : OA1B - port map(A => N_556_i_0, B => N_58_0, C => - \Address_0_i_1[29]\, Y => N_183); - - \AddressSave_RNO_1[28]\ : MX2A - port map(A => N_975, B => \haddr_c[28]\, S => - \AddressPhase\, Y => N_610); - - WriteAcc_RNO : NOR2B - port map(A => N_321, B => HRESETn_c, Y => N_106); - - \AddressSave_RNO[11]\ : NOR2B - port map(A => N_341, B => HRESETn_c, Y => N_518); - - SingleAcc_RNO : NOR2B - port map(A => N_322, B => HRESETn_c, Y => N_104); - - ReAddrPhase_RNO_1 : OA1B - port map(A => \AddressPhase\, B => \ReAddrPhase\, C => - AHB_Master_In_c_3, Y => N_53); - - \Address[22]\ : DFN1 - port map(D => N_171, CLK => HCLK_c, Q => \haddr_c[22]\); - - \Address_RNO[23]\ : OA1B - port map(A => N_556_i_0, B => N_55_0, C => - \Address_0_i_1[23]\, Y => N_173); - - \Address[2]\ : DFN1 - port map(D => N_116, CLK => HCLK_c, Q => \haddr_c[2]\); - - \Address_RNO_1[7]\ : OAI1 - port map(A => \AddressSave[7]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[7]\); - - \Address_RNO[24]\ : OA1B - port map(A => N_556_i_0, B => N_33_0, C => - \Address_0_i_1[24]\, Y => N_175); - - \Address_RNO[10]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[11]\, C => - \Address_0_i_1[10]\, Y => \Address_RNO[10]_net_1\); - - \AddressSave[20]\ : DFN1 - port map(D => N_225, CLK => HCLK_c, Q => - \AddressSave[20]_net_1\); - - \Address_RNO_1[30]\ : OAI1 - port map(A => \AddressSave[30]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[30]\); - - \AddressSave_RNO_1[3]\ : MX2 - port map(A => N_950, B => \haddr_c[3]\, S => - \AddressPhase_0\, Y => N_595); - - \AddressSave_RNO_1[19]\ : MX2 - port map(A => N_966, B => \haddr_c[19]\, S => - \AddressPhase_0\, Y => N_601); - - AddressPhase_RNI6S87 : OR2B - port map(A => \AddressPhase\, B => AHB_Master_In_c_3, Y => - N_566); - - ActivePhase_RNIS2FG1 : AO1 - port map(A => N_582, B => AHB_Master_In_c_3, C => N_563, Y - => N_130); - - EarlyPhase_RNO_1 : AO1C - port map(A => AHB_Master_In_c_0, B => N_568, C => - un1_ahbin_3_0_0, Y => un1_ahbin_3); - - \AddressSave_RNO_1[24]\ : MX2 - port map(A => N_971, B => \haddr_c[24]\, S => - \AddressPhase\, Y => N_606); - - \DMAOut.Ready_RNO\ : NOR3C - port map(A => HRESETn_c, B => AHB_Master_In_c_3, C => - \DataPhase\, Y => N_196); - - BoundaryPhase_RNO_2 : OR2A - port map(A => N_555, B => N_553, Y => N_685); - - \AddressSave_RNO[25]\ : NOR2B - port map(A => N_355, B => HRESETn_c, Y => N_530); - - \AddressSave_RNO_1[23]\ : MX2 - port map(A => N_970, B => \haddr_c[23]\, S => - \AddressPhase\, Y => N_605); - - \AHBOut.hbusreq_i_0_a2\ : NOR2A - port map(A => un7_dmain(66), B => N_1011, Y => N_761); - - \Address_RNO[9]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[10]\, C => - \Address_0_i_1[9]\, Y => N_26); - - \Address[5]\ : DFN1 - port map(D => N_122, CLK => HCLK_c, Q => \haddr_c[5]\); - - \AddressSave[30]\ : DFN1 - port map(D => N_532, CLK => HCLK_c, Q => - \AddressSave[30]_net_1\); - - \Address[15]\ : DFN1 - port map(D => N_157, CLK => HCLK_c, Q => \haddr_c[15]\); - - \AHBOut.hburst[2]\ : DFN1E1 - port map(D => N_682, CLK => HCLK_c, E => N_130, Q => - hburst_c(2)); - - \Address_RNO_0[9]\ : AO1D - port map(A => N_956, B => N_753_0, C => \Address_0_i_0[9]\, - Y => \Address_0_i_1[9]\); - - \Address[13]\ : DFN1 - port map(D => \Address_RNO[13]_net_1\, CLK => HCLK_c, Q => - \haddr_c[13]\); - - \AddressSave_RNO_1[15]\ : MX2 - port map(A => N_962, B => \haddr_c[15]\, S => - \AddressPhase_0\, Y => N_597); - - \AddressSave_RNO_1[11]\ : MX2 - port map(A => N_958, B => \haddr_c[11]\, S => - \AddressPhase\, Y => N_616); - - \AddressSave_RNO_0[18]\ : MX2 - port map(A => \AddressSave[18]_net_1\, B => N_600, S => - hsize_0_sqmuxa, Y => N_348); - - \AddressSave[6]\ : DFN1 - port map(D => N_215, CLK => HCLK_c, Q => - \AddressSave[6]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m24 : AX1C - port map(A => \haddr_c[18]\, B => N_22_0, C => - \haddr_c[19]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[20]\); - - \AHBOut.hsize_RNO_1[1]\ : OR2 - port map(A => \hsize_c[1]\, B => \AddressPhase_0\, Y => - \hsize_1_i_a5_0[1]\); - - \Address_RNO_1[4]\ : OAI1 - port map(A => \AddressSave[4]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[4]\); - - ReDataPhase_RNIORDS : OA1B - port map(A => N_555, B => \ReDataPhase\, C => N_553, Y => - N_556_i); - - \Address[19]\ : DFN1 - port map(D => N_165, CLK => HCLK_c, Q => \haddr_c[19]\); - - ActivePhase_RNII8GG : OR2A - port map(A => N_1011, B => \ActivePhase\, Y => N_554); - - BoundaryPhase_RNO_0 : NOR3C - port map(A => N_686, B => HRESETn_c, C => N_684, Y => - BoundaryPhase_2_i_1); - - \Address[25]\ : DFN1 - port map(D => N_177, CLK => HCLK_c, Q => \haddr_c[25]\); - - un1_AddressSave_0_sqmuxa_1_m12 : NOR3C - port map(A => \haddr_c[10]\, B => N_580, C => \haddr_c[11]\, - Y => N_13_0); - - \Address_RNO_0[27]\ : AO1A - port map(A => N_753_0, B => N_974, C => \Address_0_i_0[27]\, - Y => \Address_0_i_1[27]\); - - \AddressSave_RNO[7]\ : NOR2B - port map(A => N_337, B => HRESETn_c, Y => N_217); - - ActivePhase_RNIHBAN : OR2 - port map(A => N_554, B => N_553, Y => N_756); - - \Address[23]\ : DFN1 - port map(D => N_173, CLK => HCLK_c, Q => \haddr_c[23]\); - - \AddressSave_RNO_1[7]\ : MX2 - port map(A => N_954, B => \haddr_c[7]\, S => - \AddressPhase_0\, Y => N_589); - - \AHBOut.htrans[1]\ : DFN1E1 - port map(D => N_193, CLK => HCLK_c, E => N_189, Q => - htrans_c(1)); - - DataPhase_RNI0SGJ_0 : AO1C - port map(A => N_760, B => N_558, C => HRESETn_c, Y => N_563); - - AddressPhase_RNIDRDU1 : NOR3 - port map(A => N_563, B => N_614, C => N_738, Y => N_191); - - WriteAcc_RNO_0 : MX2 - port map(A => \WriteAcc\, B => N_1012, S => hwrite_2_sqmuxa, - Y => N_321); - - \AddressSave_RNO[29]\ : NOR2B - port map(A => N_359, B => HRESETn_c, Y => N_295); - - \AddressSave_RNO_0[14]\ : MX2 - port map(A => \AddressSave[14]_net_1\, B => N_596, S => - hsize_0_sqmuxa_0, Y => N_344); - - \Address[29]\ : DFN1 - port map(D => N_183, CLK => HCLK_c, Q => \haddr_c[29]\); - - \Address_RNIQTTQ[4]\ : NOR3C - port map(A => \haddr_c[4]\, B => \haddr_c[3]\, C => - \htrans_12_i_o2_2_0[0]\, Y => \htrans_12_i_o2_2_4[0]\); - - \Address[18]\ : DFN1 - port map(D => N_163, CLK => HCLK_c, Q => \haddr_c[18]\); - - \AddressSave_RNO[10]\ : NOR2B - port map(A => N_340, B => HRESETn_c, Y => N_516); - - \AddressSave[16]\ : DFN1 - port map(D => N_520, CLK => HCLK_c, Q => - \AddressSave[16]_net_1\); - - \AddressSave_RNO_1[26]\ : MX2A - port map(A => N_973, B => \haddr_c[26]\, S => - \AddressPhase\, Y => N_608); - - \AddressSave_RNO_0[13]\ : MX2 - port map(A => \AddressSave[13]_net_1\, B => N_618, S => - hsize_0_sqmuxa_0, Y => N_343); - - ActivePhase_RNO : NOR2B - port map(A => N_320, B => HRESETn_c, Y => N_108); - - \Address_RNO[21]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[22]\, C => - \Address_0_i_1[21]\, Y => N_169); - - \Address_RNO[16]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[17]\, C => - \Address_0_i_1[16]\, Y => N_159); - - SingleAcc_RNO_1 : NOR3C - port map(A => AHB_Master_In_c_0, B => N_561, C => - un7_dmain(66), Y => SingleAcc_2_sqmuxa); - - \Address_RNO_0[30]\ : AO1D - port map(A => N_977, B => N_753_0, C => \Address_0_i_0[30]\, - Y => \Address_0_i_1[30]\); - - \Address_RNO_0[24]\ : AO1D - port map(A => N_971, B => N_753_0, C => \Address_0_i_0[24]\, - Y => \Address_0_i_1[24]\); - - un1_AddressSave_0_sqmuxa_1_m2 : OR2A - port map(A => \haddr_c[2]\, B => N_566, Y => N_3_0); - - \Address_RNO_0[25]\ : AO1D - port map(A => N_972, B => N_753_0, C => \Address_0_i_0[25]\, - Y => \Address_0_i_1[25]\); - - \Address[0]\ : DFN1 - port map(D => N_112, CLK => HCLK_c, Q => \haddr_c[0]\); - - ReDataPhase_RNIHO18 : OR2A - port map(A => \ReDataPhase\, B => N_553, Y => N_754); - - \AddressSave_RNO[22]\ : NOR2B - port map(A => N_352, B => HRESETn_c, Y => N_291); - - DataPhase_RNIFGQC : NOR2A - port map(A => AHB_Master_In_c_5, B => N_760, Y => Retry); - - BoundaryPhase_RNO_1 : OR2 - port map(A => N_580, B => \BoundaryPhase\, Y => - \BoundaryPhase_RNO_1\); - - GND_i : GND - port map(Y => \GND\); - - \AddressSave_RNO_0[6]\ : MX2 - port map(A => \AddressSave[6]_net_1\, B => N_588, S => - hsize_0_sqmuxa_0, Y => N_336); - - \AHBOut.hsize_RNO_2[1]\ : OAI1 - port map(A => AHB_Master_In_c_3, B => \hsize_c[1]\, C => - HRESETn_c, Y => \hsize_1_i_0[1]\); - - \AHBOut.hburst_RNO_0[0]\ : NOR3B - port map(A => \hburst_11_0_a2_i_0[0]\, B => N_643, C => - N_563, Y => \hburst_11_0_a2_i_2[0]\); - - \AddressSave_RNO[16]\ : NOR2B - port map(A => N_346, B => HRESETn_c, Y => N_520); - - \Address_RNO[27]\ : OA1B - port map(A => N_556_i, B => N_56_0, C => - \Address_0_i_1[27]\, Y => N_128); - - \Address[4]\ : DFN1 - port map(D => N_120, CLK => HCLK_c, Q => \haddr_c[4]\); - - \Address[28]\ : DFN1 - port map(D => N_181, CLK => HCLK_c, Q => \haddr_c[28]\); - - \AHBOut.htrans_RNO_5[0]\ : OAI1 - port map(A => \ReAddrPhase\, B => N_1011, C => - \BoundaryPhase\, Y => N_675); - - \AddressSave_RNO[23]\ : NOR2B - port map(A => N_353, B => HRESETn_c, Y => N_526); - - un1_AddressSave_0_sqmuxa_1_m49 : AX1C - port map(A => \haddr_c[10]\, B => N_580, C => \haddr_c[11]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[12]\); - - un1_AddressSave_0_sqmuxa_1_m35 : NOR3C - port map(A => \haddr_c[24]\, B => N_32_0, C => - \haddr_c[25]\, Y => N_36); - - \Address_RNO_0[3]\ : AO1D - port map(A => N_950, B => N_753, C => \Address_0_i_0[3]\, Y - => \Address_0_i_1[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_AddressSave_0_sqmuxa_1_m52 : AX1C - port map(A => \haddr_c[14]\, B => N_15_0, C => - \haddr_c[15]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[16]\); - - EarlyPhase : DFN1 - port map(D => N_24, CLK => HCLK_c, Q => \EarlyPhase\); - - \Address_RNO_1[31]\ : OAI1 - port map(A => \AddressSave[31]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[31]\); - - \AddressSave_RNO[4]\ : NOR2B - port map(A => N_334, B => HRESETn_c, Y => N_512); - - un1_AddressSave_0_sqmuxa_1_m18 : XOR2 - port map(A => N_18_0, B => \haddr_c[16]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[17]\); - - \Address_RNO_0[4]\ : AO1D - port map(A => N_951, B => N_753, C => \Address_0_i_0[4]\, Y - => \Address_0_i_1[4]\); - - \Address_RNO_0[5]\ : AO1D - port map(A => N_952, B => N_753, C => \Address_0_i_0[5]\, Y - => \Address_0_i_1[5]\); - - \AHBOut.hsize[0]\ : DFN1 - port map(D => N_149, CLK => HCLK_c, Q => \hsize_c[0]\); - - \Address_RNO_0[17]\ : AO1D - port map(A => N_964, B => N_753, C => \Address_0_i_0[17]\, - Y => \Address_0_i_1[17]\); - - \AddressSave_RNO_1[2]\ : MX2 - port map(A => N_949, B => \haddr_c[2]\, S => - \AddressPhase_0\, Y => N_594); - - ReAddrPhase_RNO : NOR2B - port map(A => N_325, B => HRESETn_c, Y => N_102); - - \AddressSave_RNO_1[17]\ : MX2 - port map(A => N_964, B => \haddr_c[17]\, S => - \AddressPhase_0\, Y => N_599); - - \Address_RNO_1[27]\ : OAI1 - port map(A => \AddressSave[27]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[27]\); - - \AHBMaster.AHBOut.hwrite_8_iv_i_o5\ : OR2B - port map(A => AHB_Master_In_c_3, B => AHB_Master_In_c_0, Y - => N_553); - - un1_AddressSave_0_sqmuxa_1_m45 : AX1 - port map(A => N_5_0, B => \haddr_c[5]\, C => \haddr_c[6]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[7]\); - - \Address_RNI2UUQ[8]\ : NOR3C - port map(A => \haddr_c[8]\, B => \haddr_c[7]\, C => - \htrans_12_i_o2_2_2[0]\, Y => \htrans_12_i_o2_2_5[0]\); - - \Address_RNO[19]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[20]\, C => - \Address_0_i_1[19]\, Y => N_165); - - \AddressSave_RNO_0[16]\ : MX2 - port map(A => \AddressSave[16]_net_1\, B => N_598, S => - hsize_0_sqmuxa, Y => N_346); - - \Address_RNO_1[17]\ : OAI1 - port map(A => \AddressSave[17]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[17]\); - - \AHBOut.hburst[0]\ : DFN1E1 - port map(D => N_56_i_0, CLK => HCLK_c, E => N_130, Q => - hburst_c(0)); - - \AddressSave[9]\ : DFN1 - port map(D => N_514, CLK => HCLK_c, Q => - \AddressSave[9]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m40 : NOR3C - port map(A => \haddr_c[28]\, B => N_39, C => \haddr_c[29]\, - Y => N_41); - - IdlePhase_0_sqmuxa_0_o2 : OR2 - port map(A => AHB_Master_In_c_5, B => AHB_Master_In_c_4, Y - => N_558); - - \AddressSave_RNO_1[29]\ : MX2 - port map(A => N_976, B => \haddr_c[29]\, S => - \AddressPhase\, Y => N_611); - - \AddressSave_RNO[2]\ : NOR2B - port map(A => N_332, B => HRESETn_c, Y => - \AddressSave_RNO[2]_net_1\); - - \Address_RNO[13]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[14]\, C => - \Address_0_i_1[13]\, Y => \Address_RNO[13]_net_1\); - - \Address_RNO_0[14]\ : AO1D - port map(A => N_961, B => N_753, C => \Address_0_i_0[14]\, - Y => \Address_0_i_1[14]\); - - \Address[14]\ : DFN1 - port map(D => N_155, CLK => HCLK_c, Q => \haddr_c[14]\); - - \AddressSave[29]\ : DFN1 - port map(D => N_295, CLK => HCLK_c, Q => - \AddressSave[29]_net_1\); - - \Address_RNO_0[15]\ : AO1D - port map(A => N_962, B => N_753, C => \Address_0_i_0[15]\, - Y => \Address_0_i_1[15]\); - - \Address_RNO_1[24]\ : OAI1 - port map(A => \AddressSave[24]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[24]\); - - \AddressSave_RNO_0[1]\ : MX2 - port map(A => \AddressSave[1]_net_1\, B => N_593, S => - hsize_0_sqmuxa_0, Y => N_331); - - \IdlePhase_RNI03G71\ : OA1C - port map(A => N_761, B => N_559, C => \IdlePhase\, Y => - IdlePhase_RNI03G71); - - \Address_RNO_1[25]\ : OAI1 - port map(A => \AddressSave[25]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[25]\); - - \Address_RNO[14]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[15]\, C => - \Address_0_i_1[14]\, Y => N_155); - - \Address_RNO_1[14]\ : OAI1 - port map(A => \AddressSave[14]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[14]\); - - \Address_RNIV6FD[6]\ : NOR2B - port map(A => \haddr_c[5]\, B => \haddr_c[6]\, Y => - \htrans_12_i_o2_2_2[0]\); - - DataPhase_RNIGGQC : OR2B - port map(A => N_558, B => \DataPhase\, Y => N_737); - - \Address_RNO_1[15]\ : OAI1 - port map(A => \AddressSave[15]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[15]\); - - \AddressSave[11]\ : DFN1 - port map(D => N_518, CLK => HCLK_c, Q => - \AddressSave[11]_net_1\); - - \AddressSave_RNO_1[25]\ : MX2 - port map(A => N_972, B => \haddr_c[25]\, S => - \AddressPhase\, Y => N_607); - - \AddressSave_RNO_1[21]\ : MX2 - port map(A => N_968, B => \haddr_c[21]\, S => - \AddressPhase_0\, Y => N_603); - - \Address[24]\ : DFN1 - port map(D => N_175, CLK => HCLK_c, Q => \haddr_c[24]\); - - \Address_RNO_0[22]\ : AO1D - port map(A => N_969, B => N_753_0, C => \Address_0_i_0[22]\, - Y => \Address_0_i_1[22]\); - - \AddressSave[1]\ : DFN1 - port map(D => N_279, CLK => HCLK_c, Q => - \AddressSave[1]_net_1\); - - \AHBOut.hwrite_RNO\ : NOR3C - port map(A => N_193, B => N_680, C => N_679, Y => N_139); - - VCC_i : VCC - port map(Y => \VCC\); - - \Address_RNO_0[31]\ : AO1D - port map(A => N_978, B => N_753_0, C => \Address_0_i_0[31]\, - Y => \Address_0_i_1[31]\); - - \AddressSave[25]\ : DFN1 - port map(D => N_530, CLK => HCLK_c, Q => - \AddressSave[25]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m27 : AX1C - port map(A => \haddr_c[20]\, B => N_26_0, C => - \haddr_c[21]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[22]\); - - \AddressSave[22]\ : DFN1 - port map(D => N_291, CLK => HCLK_c, Q => - \AddressSave[22]_net_1\); - - \AddressSave_RNO_0[19]\ : MX2 - port map(A => \AddressSave[19]_net_1\, B => N_601, S => - hsize_0_sqmuxa, Y => N_349); - - ReDataPhase_RNIORDS_0 : OA1B - port map(A => N_555, B => \ReDataPhase\, C => N_553, Y => - N_556_i_0); - - \AddressSave_RNO_0[31]\ : MX2 - port map(A => \AddressSave[31]_net_1\, B => N_591, S => - hsize_0_sqmuxa, Y => N_361); - - \AddressSave_RNO[1]\ : NOR2B - port map(A => N_331, B => HRESETn_c, Y => N_279); - - \Address[8]\ : DFN1 - port map(D => N_153, CLK => HCLK_c, Q => \haddr_c[8]\); - - \Address_RNO_0[1]\ : AO1D - port map(A => N_948, B => N_753, C => \Address_0_i_0[1]\, Y - => \Address_0_i_1[1]\); - - un1_AddressSave_0_sqmuxa_1_m21 : NOR3C - port map(A => \haddr_c[16]\, B => N_18_0, C => - \haddr_c[17]\, Y => N_22_0); - - BoundaryPhase : DFN1 - port map(D => N_147_i_0, CLK => HCLK_c, Q => - \BoundaryPhase\); - - \AddressSave_RNO_0[7]\ : MX2 - port map(A => \AddressSave[7]_net_1\, B => N_589, S => - hsize_0_sqmuxa_0, Y => N_337); - - ReAddrPhase_RNO_2 : AO1A - port map(A => N_557, B => \ReAddrPhase\, C => Retry, Y => - N_48); - - EarlyPhase_RNILB3D : NOR2 - port map(A => N_559, B => \EarlyPhase\, Y => N_561); - - \AddressSave_RNO[24]\ : NOR2B - port map(A => N_354, B => HRESETn_c, Y => N_528); - - \AHBOut.htrans_RNO_0[0]\ : NOR3C - port map(A => \htrans_12_i_0[0]\, B => N_678, C => N_675, Y - => \htrans_12_i_2[0]\); - - \AddressSave_RNO_1[9]\ : MX2 - port map(A => N_956, B => \haddr_c[9]\, S => - \AddressPhase_0\, Y => N_590); - - \AHBOut.hburst_RNO_2[0]\ : OR2B - port map(A => un7_dmain(66), B => N_561, Y => N_643); - - \Address_RNO[6]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[7]\, C => - \Address_0_i_1[6]\, Y => N_124); - - IdlePhase : DFN1 - port map(D => N_100, CLK => HCLK_c, Q => \IdlePhase\); - - \AddressSave_RNO_0[15]\ : MX2 - port map(A => \AddressSave[15]_net_1\, B => N_597, S => - hsize_0_sqmuxa_0, Y => N_345); - - \AddressSave_RNO_0[11]\ : MX2 - port map(A => \AddressSave[11]_net_1\, B => N_616, S => - hsize_0_sqmuxa_0, Y => N_341); - - ReAddrPhase : DFN1 - port map(D => N_102, CLK => HCLK_c, Q => \ReAddrPhase\); - - \Address_RNO[28]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[29]\, C => - \Address_0_i_1[28]\, Y => N_181); - - \Address_RNO[11]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[12]\, C => - \Address_0_i_1[11]\, Y => \Address_RNO[11]_net_1\); - - \Address_RNO_0[12]\ : AO1D - port map(A => N_959, B => N_753, C => \Address_0_i_0[12]\, - Y => \Address_0_i_1[12]\); - - \AddressSave_RNO_1[5]\ : MX2 - port map(A => N_952, B => \haddr_c[5]\, S => - \AddressPhase_0\, Y => N_587); - - DataPhase_RNO_0 : OAI1 - port map(A => AHB_Master_In_c_3, B => N_576, C => HRESETn_c, - Y => DataPhase_2_i_0); - - \Address_RNO_1[22]\ : OAI1 - port map(A => \AddressSave[22]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[22]\); - - \Address_RNO[17]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[18]\, C => - \Address_0_i_1[17]\, Y => N_161); - - \AddressSave_RNO_0[0]\ : MX2 - port map(A => \AddressSave[0]_net_1\, B => N_592, S => - hsize_0_sqmuxa_0, Y => N_330); - - \AddressSave_RNO[31]\ : NOR2B - port map(A => N_361, B => HRESETn_c, Y => N_534); - - IdlePhase_RNI9HPU : NOR3 - port map(A => N_635, B => \IdlePhase\, C => N_1013, Y => - N_43); - - \Address_RNO[5]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[6]\, C => - \Address_0_i_1[5]\, Y => N_122); - - \AddressSave[17]\ : DFN1 - port map(D => N_522, CLK => HCLK_c, Q => - \AddressSave[17]_net_1\); - - \Address_RNO_1[12]\ : OAI1 - port map(A => \AddressSave[12]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[12]\); - - \AddressSave_RNO_1[27]\ : MX2A - port map(A => N_974, B => \haddr_c[27]\, S => - \AddressPhase\, Y => N_609); - - \AddressSave_RNO[15]\ : NOR2B - port map(A => N_345, B => HRESETn_c, Y => N_287); - - \AddressSave[4]\ : DFN1 - port map(D => N_512, CLK => HCLK_c, Q => - \AddressSave[4]_net_1\); - - \AddressSave[14]\ : DFN1 - port map(D => N_221, CLK => HCLK_c, Q => - \AddressSave[14]_net_1\); - - \Address_RNO[0]\ : OA1B - port map(A => \haddr_c[0]\, B => N_556_i, C => - \Address_0_i_1[0]\, Y => N_112); - - ActivePhase : DFN1 - port map(D => N_108, CLK => HCLK_c, Q => \ActivePhase\); - - ReAddrPhase_RNO_0 : MX2 - port map(A => \ReAddrPhase\, B => N_53, S => N_48, Y => - N_325); - - \AddressSave[7]\ : DFN1 - port map(D => N_217, CLK => HCLK_c, Q => - \AddressSave[7]_net_1\); - - DataPhase_RNI0SGJ : OR3B - port map(A => HRESETn_c, B => N_737, C => AHB_Master_In_c_3, - Y => N_189); - - \Address_RNO_0[2]\ : AO1D - port map(A => N_949, B => N_753, C => \Address_0_i_0[2]\, Y - => \Address_0_i_1[2]\); - - \AddressSave_RNO_0[22]\ : MX2 - port map(A => \AddressSave[22]_net_1\, B => N_604, S => - hsize_0_sqmuxa, Y => N_352); - - un1_AddressSave_0_sqmuxa_1_m14 : NOR3C - port map(A => \haddr_c[12]\, B => N_13_0, C => - \haddr_c[13]\, Y => N_15_0); - - \Address_RNO[3]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[4]\, C => - \Address_0_i_1[3]\, Y => N_118); - - \Address[3]\ : DFN1 - port map(D => N_118, CLK => HCLK_c, Q => \haddr_c[3]\); - - \AddressSave_RNO_1[6]\ : MX2 - port map(A => N_953, B => \haddr_c[6]\, S => - \AddressPhase_0\, Y => N_588); - - ActivePhase_RNO_1 : NOR3A - port map(A => un7_dmain(66), B => - ActivePhase_1_sqmuxa_i_a5_0, C => N_559, Y => N_639); - - un1_AddressSave_0_sqmuxa_1_m32 : XOR2 - port map(A => N_32_0, B => \haddr_c[24]\, Y => N_33_0); - - ReDataPhase_RNILM59 : OR2 - port map(A => \ReDataPhase\, B => \ReAddrPhase\, Y => N_559); - - \AddressSave_RNO_0[20]\ : MX2 - port map(A => \AddressSave[20]_net_1\, B => N_602, S => - hsize_0_sqmuxa, Y => N_350); - - \AddressSave_RNO[0]\ : NOR2B - port map(A => N_330, B => HRESETn_c, Y => N_213); - - \Address_RNO_1[2]\ : OAI1 - port map(A => \AddressSave[2]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[2]\); - - DataPhase_RNISED9 : OR2A - port map(A => \DataPhase\, B => AHB_Master_In_c_3, Y => - N_760); - - \Address_RNO[30]\ : OA1B - port map(A => N_556_i, B => N_42, C => \Address_0_i_1[30]\, - Y => N_28); - - \AddressSave[0]\ : DFN1 - port map(D => N_213, CLK => HCLK_c, Q => - \AddressSave[0]_net_1\); - - AddressPhase : DFN1 - port map(D => N_191, CLK => HCLK_c, Q => \AddressPhase\); - - BoundaryPhase_RNO_5 : MX2A - port map(A => \ReAddrPhase\, B => \ActivePhase\, S => - \AddressPhase\, Y => N_567); - - \AHBOut.htrans_RNO_6[0]\ : AOI1 - port map(A => N_1011, B => \AddressPhase\, C => - \ReAddrPhase\, Y => N_562); - - \AddressSave_RNO_0[5]\ : MX2 - port map(A => \AddressSave[5]_net_1\, B => N_587, S => - hsize_0_sqmuxa_0, Y => N_335); - - \AddressSave_RNO[3]\ : NOR2B - port map(A => N_333, B => HRESETn_c, Y => - \AddressSave_RNO[3]_net_1\); - - DataPhase_RNI1I7G : OR2B - port map(A => N_576, B => AHB_Master_In_c_3, Y => OKAY); - - ReAddrPhase_RNIMLKN : OR2A - port map(A => N_1011, B => \ReAddrPhase\, Y => - hwrite_2_sqmuxa_1); - - \AddressSave_RNO[19]\ : NOR2B - port map(A => N_349, B => HRESETn_c, Y => N_289); - - un1_AddressSave_0_sqmuxa_1_m42 : XNOR2 - port map(A => N_3_0, B => \haddr_c[3]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[4]\); - - \Address_RNO_0[6]\ : AO1D - port map(A => N_953, B => N_753, C => \Address_0_i_0[6]\, Y - => \Address_0_i_1[6]\); - - AddressPhase_RNIN7JU_0 : OR2B - port map(A => N_756, B => N_566, Y => hsize_0_sqmuxa); - - un1_AddressSave_0_sqmuxa_1_m6 : OR3B - port map(A => \haddr_c[5]\, B => \haddr_c[6]\, C => N_5_0, - Y => N_7_0); - - \AddressSave_RNO_0[17]\ : MX2 - port map(A => \AddressSave[17]_net_1\, B => N_599, S => - hsize_0_sqmuxa, Y => N_347); - - \Address[7]\ : DFN1 - port map(D => N_126, CLK => HCLK_c, Q => \haddr_c[7]\); - - un1_AddressSave_0_sqmuxa_1_m1 : XNOR2 - port map(A => N_566, B => \haddr_c[2]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[3]\); - - \Address_RNO_0[28]\ : AO1A - port map(A => N_753_0, B => N_975, C => \Address_0_i_0[28]\, - Y => \Address_0_i_1[28]\); - - AddressPhase_RNIORDS_0 : OR2A - port map(A => N_555, B => N_557, Y => N_753_0); - - \AddressSave_RNO[27]\ : NOR2B - port map(A => N_357, B => HRESETn_c, Y => N_261); - - \AddressSave_RNO[12]\ : NOR2B - port map(A => N_342, B => HRESETn_c, Y => N_285); - - \AddressSave[26]\ : DFN1 - port map(D => N_293, CLK => HCLK_c, Q => - \AddressSave[26]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m54 : AX1C - port map(A => \haddr_c[22]\, B => N_29_0, C => - \haddr_c[23]\, Y => N_55_0); - - un1_AddressSave_0_sqmuxa_1_m53 : XOR2 - port map(A => N_26_0, B => \haddr_c[20]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[21]\); - - AddressPhase_RNIORDS : OR2A - port map(A => N_555, B => N_557, Y => N_753); - - \DMAOut.Ready\ : DFN1 - port map(D => N_196, CLK => HCLK_c, Q => Ready); - - \AddressSave[18]\ : DFN1 - port map(D => N_524, CLK => HCLK_c, Q => - \AddressSave[18]_net_1\); - - \AddressSave_RNO[30]\ : NOR2B - port map(A => N_360, B => HRESETn_c, Y => N_532); - - \AddressSave_RNO[13]\ : NOR2B - port map(A => N_343, B => HRESETn_c, Y => N_219); - - un1_AddressSave_0_sqmuxa_1_m29 : XOR2 - port map(A => N_29_0, B => \haddr_c[22]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[23]\); - - un1_AddressSave_0_sqmuxa_1_m38 : NOR3C - port map(A => \haddr_c[26]\, B => N_36, C => \haddr_c[27]\, - Y => N_39); - - \AHBOut.hsize_RNO_0[1]\ : NOR2A - port map(A => AHB_Master_In_c_0, B => N_554, Y => N_569); - - \Address_RNO_0[26]\ : AO1A - port map(A => N_753_0, B => N_973, C => \Address_0_i_0[26]\, - Y => \Address_0_i_1[26]\); - - WriteAcc : DFN1 - port map(D => N_106, CLK => HCLK_c, Q => \WriteAcc\); - - \AHBOut.hsize_RNO_0[0]\ : NOR2B - port map(A => HRESETn_c, B => \hsize_c[0]\, Y => - \hsize_1_i_0[0]\); - - EarlyPhase_RNO_0 : MX2A - port map(A => AHB_Master_In_c_0, B => \EarlyPhase\, S => - un1_ahbin_3, Y => N_327); - - \AddressSave_RNO_0[3]\ : MX2 - port map(A => \AddressSave[3]_net_1\, B => N_595, S => - hsize_0_sqmuxa_0, Y => N_333); - - ActivePhase_RNI8O09 : OR2A - port map(A => \ActivePhase\, B => un7_dmain(66), Y => N_560); - - \Address_RNO_0[29]\ : AO1D - port map(A => N_976, B => N_753_0, C => \Address_0_i_0[29]\, - Y => \Address_0_i_1[29]\); - - un1_AddressSave_0_sqmuxa_1_m56 : XOR2 - port map(A => N_39, B => \haddr_c[28]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[29]\); - - un1_AddressSave_0_sqmuxa_1_m25 : NOR3C - port map(A => \haddr_c[18]\, B => N_22_0, C => - \haddr_c[19]\, Y => N_26_0); - - un1_AddressSave_0_sqmuxa_1_m48 : XNOR2 - port map(A => N_7_0, B => \haddr_c[7]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[8]\); - - un1_AddressSave_0_sqmuxa_1_m20 : AX1C - port map(A => \haddr_c[16]\, B => N_18_0, C => - \haddr_c[17]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[18]\); - - EarlyPhase_RNO_2 : OR2A - port map(A => \ActivePhase\, B => N_761, Y => N_568); - - \AHBOut.htrans_RNO_1[0]\ : OR3B - port map(A => \htrans_12_i_o2_2_4[0]\, B => - \htrans_12_i_o2_2_5[0]\, C => N_562, Y => - \htrans_RNO_1[0]\); - - \Address_RNO[22]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[23]\, C => - \Address_0_i_1[22]\, Y => N_171); - - \Address[9]\ : DFN1 - port map(D => N_26, CLK => HCLK_c, Q => \haddr_c[9]\); - - DataPhase_RNO : OA1C - port map(A => AHB_Master_In_c_3, B => \AddressPhase_0\, C - => DataPhase_2_i_0, Y => N_20); - - \Address_RNO[18]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[19]\, C => - \Address_0_i_1[18]\, Y => N_163); - - \Address_RNO_0[18]\ : AO1D - port map(A => N_965, B => N_753_0, C => \Address_0_i_0[18]\, - Y => \Address_0_i_1[18]\); - - \AddressSave_RNO_0[28]\ : MX2 - port map(A => \AddressSave[28]_net_1\, B => N_610, S => - hsize_0_sqmuxa, Y => N_358); - - GND_i_0 : GND - port map(Y => GND_0); - - \Address_RNO[7]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[8]\, C => - \Address_0_i_1[7]\, Y => N_126); - - \Address_RNO_1[28]\ : OAI1 - port map(A => \AddressSave[28]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[28]\); - - \Address_RNO_0[7]\ : AO1D - port map(A => N_954, B => N_753, C => \Address_0_i_0[7]\, Y - => \Address_0_i_1[7]\); - - SingleAcc : DFN1 - port map(D => N_104, CLK => HCLK_c, Q => \SingleAcc\); - - \AddressSave_RNO_0[4]\ : MX2 - port map(A => \AddressSave[4]_net_1\, B => N_586, S => - hsize_0_sqmuxa_0, Y => N_334); - - \Address_RNO_1[18]\ : OAI1 - port map(A => \AddressSave[18]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[18]\); - - \Address[6]\ : DFN1 - port map(D => N_124, CLK => HCLK_c, Q => \haddr_c[6]\); - - \AddressSave_RNO_1[30]\ : MX2 - port map(A => N_977, B => \haddr_c[30]\, S => - \AddressPhase\, Y => N_612); - - \AddressSave_RNO[9]\ : NOR2B - port map(A => N_339, B => HRESETn_c, Y => N_514); - - EarlyPhase_RNO_3 : AOI1B - port map(A => N_561, B => AHB_Master_In_c_0, C => - AHB_Master_In_c_3, Y => un1_ahbin_3_0_0); - - \Address_RNO_0[16]\ : AO1D - port map(A => N_963, B => N_753, C => \Address_0_i_0[16]\, - Y => \Address_0_i_1[16]\); - - \AddressSave_RNO_1[0]\ : MX2 - port map(A => N_947, B => \haddr_c[0]\, S => - \AddressPhase_0\, Y => N_592); - - \Address_RNO[8]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[9]\, C => - \Address_0_i_1[8]\, Y => N_153); - - \AddressSave_RNO_0[24]\ : MX2 - port map(A => \AddressSave[24]_net_1\, B => N_606, S => - hsize_0_sqmuxa, Y => N_354); - - \AddressSave[21]\ : DFN1 - port map(D => N_259, CLK => HCLK_c, Q => - \AddressSave[21]_net_1\); - - \Address_RNO_1[26]\ : OAI1 - port map(A => \AddressSave[26]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[26]\); - - \AddressSave_RNO_0[9]\ : MX2 - port map(A => \AddressSave[9]_net_1\, B => N_590, S => - hsize_0_sqmuxa_0, Y => N_339); - - un1_AddressSave_0_sqmuxa_1_m17 : NOR3C - port map(A => \haddr_c[14]\, B => N_15_0, C => - \haddr_c[15]\, Y => N_18_0); - - \AHBOut.htrans_RNO_2[0]\ : AO1D - port map(A => N_560, B => \EarlyPhase\, C => \ReAddrPhase\, - Y => N_676); - - \AddressSave_RNO_0[23]\ : MX2 - port map(A => \AddressSave[23]_net_1\, B => N_605, S => - hsize_0_sqmuxa, Y => N_353); - - SingleAcc_RNO_0 : MX2 - port map(A => \SingleAcc\, B => SingleAcc_2_sqmuxa, S => - hwrite_2_sqmuxa, Y => N_322); - - ReAddrPhase_RNI7EMV : NOR2 - port map(A => N_557, B => hwrite_2_sqmuxa_1, Y => Grant); - - \Address_RNO_1[16]\ : OAI1 - port map(A => \AddressSave[16]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[16]\); - - \Address_RNO_0[19]\ : AO1D - port map(A => N_966, B => N_753_0, C => \Address_0_i_0[19]\, - Y => \Address_0_i_1[19]\); - - \Address[11]\ : DFN1 - port map(D => \Address_RNO[11]_net_1\, CLK => HCLK_c, Q => - \haddr_c[11]\); - - \AddressSave[31]\ : DFN1 - port map(D => N_534, CLK => HCLK_c, Q => - \AddressSave[31]_net_1\); - - \Address[31]\ : DFN1 - port map(D => N_30, CLK => HCLK_c, Q => \haddr_c[31]\); - - \Address_RNO_1[29]\ : OAI1 - port map(A => \AddressSave[29]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[29]\); - - \AddressSave_RNO_0[2]\ : MX2 - port map(A => \AddressSave[2]_net_1\, B => N_594, S => - hsize_0_sqmuxa_0, Y => N_332); - - \AddressSave[13]\ : DFN1 - port map(D => N_219, CLK => HCLK_c, Q => - \AddressSave[13]_net_1\); - - AddressPhase_RNI73CK : NOR2 - port map(A => N_554, B => \AddressPhase\, Y => N_555); - - DataPhase_RNI1I7G_0 : OR2A - port map(A => Fault_0_a5_0, B => N_760, Y => Fault); - - \Address_RNO_1[19]\ : OAI1 - port map(A => \AddressSave[19]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[19]\); - - \AHBOut.hwrite_RNO_1\ : AO1B - port map(A => N_1012, B => N_560, C => N_561, Y => N_679); - - \Address_RNO[2]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[3]\, C => - \Address_0_i_1[2]\, Y => N_116); - - EarlyPhase_RNI6DT61 : OA1C - port map(A => N_561, B => N_1011, C => \un1_dmain_20_i_0\, - Y => N_193); - - \Address_RNO_1[5]\ : OAI1 - port map(A => \AddressSave[5]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[5]\); - - \Address_RNO[4]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[5]\, C => - \Address_0_i_1[4]\, Y => N_120); - - \AddressSave_RNO[14]\ : NOR2B - port map(A => N_344, B => HRESETn_c, Y => N_221); - - EarlyPhase_RNO : NOR2B - port map(A => N_327, B => HRESETn_c, Y => N_24); - - EarlyPhase_RNIHDVB : OR2 - port map(A => N_557, B => \EarlyPhase\, Y => N_758); - - \Address_RNO[25]\ : OA1B - port map(A => N_556_i_0, B => N_35, C => - \Address_0_i_1[25]\, Y => N_177); - - \Address[21]\ : DFN1 - port map(D => N_169, CLK => HCLK_c, Q => \haddr_c[21]\); - - \AddressSave_RNO[28]\ : NOR2B - port map(A => N_358, B => HRESETn_c, Y => N_263); - - \AddressSave_RNO_1[12]\ : MX2 - port map(A => N_959, B => \haddr_c[12]\, S => - \AddressPhase\, Y => N_617); - - \AddressSave_RNO_1[10]\ : MX2 - port map(A => N_957, B => \haddr_c[10]\, S => - \AddressPhase\, Y => N_615); - - ReDataPhase_RNO : NOR2B - port map(A => N_329, B => HRESETn_c, Y => N_22); - - \AHBOut.hsize_RNO[0]\ : NOR2A - port map(A => \hsize_1_i_0[0]\, B => hsize_0_sqmuxa_0, Y - => N_149); - - \AddressSave_RNO[21]\ : NOR2B - port map(A => N_351, B => HRESETn_c, Y => N_259); - - IdlePhase_RNO_0 : MX2B - port map(A => \IdlePhase\, B => N_760, S => N_189, Y => - N_326); - - un1_AddressSave_0_sqmuxa_1_m57 : AX1C - port map(A => \haddr_c[28]\, B => N_39, C => \haddr_c[29]\, - Y => N_58_0); - - \Address[17]\ : DFN1 - port map(D => N_161, CLK => HCLK_c, Q => \haddr_c[17]\); - - \AddressSave[10]\ : DFN1 - port map(D => N_516, CLK => HCLK_c, Q => - \AddressSave[10]_net_1\); - - \AddressSave_RNO_0[26]\ : MX2 - port map(A => \AddressSave[26]_net_1\, B => N_608, S => - hsize_0_sqmuxa, Y => N_356); - - \Address_RNO_1[1]\ : OAI1 - port map(A => \AddressSave[1]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[1]\); - - \Address_RNO_1[6]\ : OAI1 - port map(A => \AddressSave[6]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[6]\); - - un1_AddressSave_0_sqmuxa_1_m51 : AX1C - port map(A => \haddr_c[12]\, B => N_13_0, C => - \haddr_c[13]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[14]\); - - un1_AddressSave_0_sqmuxa_1_m34 : AX1C - port map(A => \haddr_c[24]\, B => N_32_0, C => - \haddr_c[25]\, Y => N_35); - - \Address_RNIV6FD[9]\ : NOR2B - port map(A => \haddr_c[9]\, B => \haddr_c[2]\, Y => - \htrans_12_i_o2_2_0[0]\); - - \Address[27]\ : DFN1 - port map(D => N_128, CLK => HCLK_c, Q => \haddr_c[27]\); - - \AddressSave[3]\ : DFN1 - port map(D => \AddressSave_RNO[3]_net_1\, CLK => HCLK_c, Q - => \AddressSave[3]_net_1\); - - DataPhase : DFN1 - port map(D => N_20, CLK => HCLK_c, Q => \DataPhase\); - - \AddressSave[2]\ : DFN1 - port map(D => \AddressSave_RNO[2]_net_1\, CLK => HCLK_c, Q - => \AddressSave[2]_net_1\); - - \AddressSave[27]\ : DFN1 - port map(D => N_261, CLK => HCLK_c, Q => - \AddressSave[27]_net_1\); - - AddressPhase_0 : DFN1 - port map(D => N_191, CLK => HCLK_c, Q => \AddressPhase_0\); - - \Address_RNO_0[20]\ : AO1D - port map(A => N_967, B => N_753_0, C => \Address_0_i_0[20]\, - Y => \Address_0_i_1[20]\); - - \AddressSave_RNO[8]\ : NOR2B - port map(A => N_338, B => HRESETn_c, Y => N_283); - - \AddressSave[5]\ : DFN1 - port map(D => N_281, CLK => HCLK_c, Q => - \AddressSave[5]_net_1\); - - \AddressSave[24]\ : DFN1 - port map(D => N_528, CLK => HCLK_c, Q => - \AddressSave[24]_net_1\); - - \AddressSave_RNO_1[8]\ : MX2 - port map(A => N_955, B => \haddr_c[8]\, S => \AddressPhase\, - Y => N_613); - - \Address_RNO[31]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[32]\, C => - \Address_0_i_1[31]\, Y => N_30); - - \AHBOut.htrans_RNO_4[0]\ : OR2A - port map(A => \ReAddrPhase\, B => \AddressPhase\, Y => - N_678); - - \AHBOut.htrans_RNO[0]\ : NOR3C - port map(A => \htrans_12_i_2[0]\, B => \htrans_RNO_1[0]\, C - => N_676, Y => N_137_i_0); - - un1_AddressSave_0_sqmuxa_1_m44 : XNOR2 - port map(A => N_5_0, B => \haddr_c[5]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[6]\); - - un1_AddressSave_0_sqmuxa_1_m43 : AX1 - port map(A => N_3_0, B => \haddr_c[3]\, C => \haddr_c[4]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[5]\); - - \Address_RNO[12]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[13]\, C => - \Address_0_i_1[12]\, Y => \Address_RNO[12]_net_1\); - - DataPhase_RNIGGQC_0 : NOR2A - port map(A => \DataPhase\, B => N_558, Y => N_576); - - un1_AddressSave_0_sqmuxa_1_m36 : XOR2 - port map(A => N_36, B => \haddr_c[26]\, Y => N_37); - - \Address_RNO_0[23]\ : AO1D - port map(A => N_970, B => N_753_0, C => \Address_0_i_0[23]\, - Y => \Address_0_i_1[23]\); - - un1_AddressSave_0_sqmuxa_1_m22 : XOR2 - port map(A => N_22_0, B => \haddr_c[18]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[19]\); - - \AddressSave_RNO[6]\ : NOR2B - port map(A => N_336, B => HRESETn_c, Y => N_215); - - \AddressSave_RNO_0[29]\ : MX2 - port map(A => \AddressSave[29]_net_1\, B => N_611, S => - hsize_0_sqmuxa, Y => N_359); - - \Address[1]\ : DFN1 - port map(D => N_114, CLK => HCLK_c, Q => \haddr_c[1]\); - - \AddressSave_RNO[20]\ : NOR2B - port map(A => N_350, B => HRESETn_c, Y => N_225); - - \AddressSave_RNO[17]\ : NOR2B - port map(A => N_347, B => HRESETn_c, Y => N_522); - - un1_AddressSave_0_sqmuxa_1_m46 : AX1 - port map(A => N_7_0, B => \haddr_c[7]\, C => \haddr_c[8]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[9]\); - - \AHBOut.hburst[1]\ : DFN1E1 - port map(D => N_682, CLK => HCLK_c, E => N_130, Q => - hburst_c(1)); - - ReDataPhase_RNIHO18_0 : OR2A - port map(A => \ReDataPhase\, B => N_553, Y => N_754_0); - - un1_dmain_20_i_0 : OR2A - port map(A => HRESETn_c, B => N_553, Y => - \un1_dmain_20_i_0\); - - un1_AddressSave_0_sqmuxa_1_m4 : OR3B - port map(A => \haddr_c[3]\, B => \haddr_c[4]\, C => N_3_0, - Y => N_5_0); - - ReAddrPhase_RNI25HF : NOR3A - port map(A => HRESETn_c, B => \ReAddrPhase\, C => - time_select_0, Y => \hburst_11_i_a2_i_a5_1[1]\); - - AddressPhase_RNIN7JU : OR2B - port map(A => N_756, B => N_566, Y => hsize_0_sqmuxa_0); - - BoundaryPhase_RNO_4 : OR3C - port map(A => N_829, B => N_567, C => N_1011, Y => N_684); - - \AddressSave_RNO_1[18]\ : MX2 - port map(A => N_965, B => \haddr_c[18]\, S => - \AddressPhase_0\, Y => N_600); - - \AddressSave_RNO_0[25]\ : MX2 - port map(A => \AddressSave[25]_net_1\, B => N_607, S => - hsize_0_sqmuxa, Y => N_355); - - AddressPhase_RNIKTLA : MX2C - port map(A => \AddressPhase\, B => AHB_Master_In_c_0, S => - AHB_Master_In_c_3, Y => N_614); - - \AddressSave_RNO_0[21]\ : MX2 - port map(A => \AddressSave[21]_net_1\, B => N_603, S => - hsize_0_sqmuxa, Y => N_351); - - \Address_RNO_0[10]\ : AO1D - port map(A => N_957, B => N_753, C => \Address_0_i_0[10]\, - Y => \Address_0_i_1[10]\); - - \Address_RNO[20]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[21]\, C => - \Address_0_i_1[20]\, Y => N_167); - - ActivePhase_RNO_0 : AO1A - port map(A => N_639, B => \ActivePhase\, C => - hwrite_2_sqmuxa, Y => N_320); - - \AddressSave_RNO[26]\ : NOR2B - port map(A => N_356, B => HRESETn_c, Y => N_293); - - \Address_RNO_1[20]\ : OAI1 - port map(A => \AddressSave[20]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[20]\); - - \AHBOut.htrans_RNO_3[0]\ : NOR2A - port map(A => HRESETn_c, B => N_557, Y => - \htrans_12_i_0[0]\); - - \AddressSave[28]\ : DFN1 - port map(D => N_263, CLK => HCLK_c, Q => - \AddressSave[28]_net_1\); - - ReDataPhase_RNIHO18_1 : OR2 - port map(A => \ReDataPhase\, B => N_553, Y => N_557); - - \AddressSave_RNO_1[4]\ : MX2 - port map(A => N_951, B => \haddr_c[4]\, S => - \AddressPhase_0\, Y => N_586); - - EarlyPhase_RNIFRKC1 : NOR3A - port map(A => N_560, B => hwrite_2_sqmuxa_1, C => N_758, Y - => hwrite_2_sqmuxa); - - \Address_RNO_1[10]\ : OAI1 - port map(A => \AddressSave[10]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[10]\); - - \AddressSave_RNO_1[22]\ : MX2 - port map(A => N_969, B => \haddr_c[22]\, S => - \AddressPhase_0\, Y => N_604); - - \Address_RNI2O5T1[4]\ : NOR3B - port map(A => \htrans_12_i_o2_2_4[0]\, B => - \htrans_12_i_o2_2_5[0]\, C => N_566, Y => N_580); - - ReDataPhase : DFN1 - port map(D => N_22, CLK => HCLK_c, Q => \ReDataPhase\); - - \AHBOut.htrans[0]\ : DFN1E1 - port map(D => N_137_i_0, CLK => HCLK_c, E => N_189, Q => - htrans_c(0)); - - EarlyPhase_RNIQH6K : NOR2 - port map(A => un7_dmain(66), B => N_758, Y => N_829); - - BoundaryPhase_RNO_3 : OR3B - port map(A => \ReAddrPhase\, B => \AddressPhase\, C => - N_557, Y => N_686); - - un1_AddressSave_0_sqmuxa_1_m15 : XOR2 - port map(A => N_15_0, B => \haddr_c[14]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[15]\); - - ReDataPhase_RNO_0 : AO1 - port map(A => \ReDataPhase\, B => N_553, C => Retry, Y => - N_329); - - \AddressSave_RNO_1[20]\ : MX2 - port map(A => N_967, B => \haddr_c[20]\, S => - \AddressPhase_0\, Y => N_602); - - \AddressSave_RNO_1[14]\ : MX2 - port map(A => N_961, B => \haddr_c[14]\, S => - \AddressPhase_0\, Y => N_596); - - un1_AddressSave_0_sqmuxa_1_m8 : OR3B - port map(A => \haddr_c[7]\, B => \haddr_c[8]\, C => N_7_0, - Y => N_9_0); - - un1_AddressSave_0_sqmuxa_1_m28 : NOR3C - port map(A => \haddr_c[20]\, B => N_26_0, C => - \haddr_c[21]\, Y => N_29_0); - - \Address_RNO_0[13]\ : AO1D - port map(A => N_960, B => N_753, C => \Address_0_i_0[13]\, - Y => \Address_0_i_1[13]\); - - \Address_RNO[15]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[16]\, C => - \Address_0_i_1[15]\, Y => N_157); - - ActivePhase_RNIB5HP : OR3B - port map(A => AHB_Master_In_c_0, B => N_561, C => N_560, Y - => N_582); - - un1_AddressSave_0_sqmuxa_1_m10 : XOR2 - port map(A => N_580, B => \haddr_c[10]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[11]\); - - \AHBOut.hburst_RNO[0]\ : OA1A - port map(A => N_561, B => N_1011, C => - \hburst_11_0_a2_i_2[0]\, Y => N_56_i_0); - - \AddressSave_RNO_1[13]\ : MX2 - port map(A => N_960, B => \haddr_c[13]\, S => - \AddressPhase\, Y => N_618); - - \Address_RNO_1[23]\ : OAI1 - port map(A => \AddressSave[23]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[23]\); - - \Address_RNO_0[21]\ : AO1D - port map(A => N_968, B => N_753_0, C => \Address_0_i_0[21]\, - Y => \Address_0_i_1[21]\); - - \AddressSave[19]\ : DFN1 - port map(D => N_289, CLK => HCLK_c, Q => - \AddressSave[19]_net_1\); - - ReDataPhase_RNI5AUG : NOR2 - port map(A => N_1011, B => \ReDataPhase\, Y => N_635); - - \Address_RNO_1[13]\ : OAI1 - port map(A => \AddressSave[13]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[13]\); - - un1_AddressSave_0_sqmuxa_1_m59 : AX1C - port map(A => \haddr_c[30]\, B => N_41, C => \haddr_c[31]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[32]\); - - \Address_RNO_1[9]\ : OAI1 - port map(A => \AddressSave[9]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[9]\); - - \Address_RNO_0[0]\ : AO1D - port map(A => N_947, B => N_753_0, C => \Address_0_i_0[0]\, - Y => \Address_0_i_1[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_dma is - - port( addr_data_f0 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - haddr_c : out std_logic_vector(31 downto 0); - AHB_Master_In_c_3 : in std_logic; - AHB_Master_In_c_0 : in std_logic; - AHB_Master_In_c_4 : in std_logic; - AHB_Master_In_c_5 : in std_logic; - hsize_c : out std_logic_vector(1 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0); - ready_i_0 : in std_logic_vector(3 downto 0); - data_ren : out std_logic_vector(3 downto 0); - time_ren : out std_logic_vector(3 downto 0); - time_ren_1z : out std_logic; - data_ren_1z : out std_logic; - N_43 : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - hwrite_c : out std_logic; - un20_time_write : out std_logic; - un13_time_write : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_waveform_dma; - -architecture DEF_ARCH of lpp_waveform_dma is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(2 to 2); - status_full : out std_logic_vector(2 to 2); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_3 : in std_logic_vector(5 downto 4) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(2 to 2) := (others => 'U'); - addr_data_vector_62 : out std_logic; - addr_data_vector_61 : out std_logic; - addr_data_vector_5 : in std_logic := 'U'; - addr_data_vector_4 : in std_logic := 'U'; - addr_data_vector_3 : in std_logic := 'U'; - addr_data_vector_0 : in std_logic := 'U'; - addr_data_vector_12 : in std_logic := 'U'; - addr_data_vector_11 : in std_logic := 'U'; - addr_data_vector_9 : in std_logic := 'U'; - addr_data_vector_7 : in std_logic := 'U'; - addr_data_vector_6 : in std_logic := 'U'; - addr_data_vector_26 : in std_logic := 'U'; - addr_data_vector_24 : in std_logic := 'U'; - addr_data_vector_22 : in std_logic := 'U'; - addr_data_vector_28 : in std_logic := 'U'; - addr_data_vector_66 : out std_logic; - addr_data_vector_65 : out std_logic; - addr_data_vector_91 : out std_logic; - addr_data_vector_89 : out std_logic; - addr_data_vector_87 : out std_logic; - addr_data_vector_63 : out std_logic; - addr_data_vector_72 : out std_logic; - addr_data_vector_74 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_78 : out std_logic; - addr_data_vector_81 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_84 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_83 : out std_logic; - N_1329 : out std_logic; - N_1328 : out std_logic; - N_1327 : out std_logic; - N_1324 : out std_logic; - N_1322 : out std_logic; - N_1321 : out std_logic; - N_1319 : out std_logic; - N_1317 : out std_logic; - N_1316 : out std_logic; - N_1308 : out std_logic; - N_1306 : out std_logic; - N_1304 : out std_logic; - N_1296 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(0 to 0); - status_full : out std_logic_vector(0 to 0); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_7 : in std_logic_vector(1 downto 0) := (others => 'U'); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(0 to 0) := (others => 'U'); - addr_data_vector_69 : in std_logic := 'U'; - addr_data_vector_68 : in std_logic := 'U'; - addr_data_vector_66 : in std_logic := 'U'; - addr_data_vector_77 : in std_logic := 'U'; - addr_data_vector_75 : in std_logic := 'U'; - addr_data_vector_86 : in std_logic := 'U'; - addr_data_vector_85 : in std_logic := 'U'; - addr_data_vector_84 : in std_logic := 'U'; - addr_data_vector_83 : in std_logic := 'U'; - addr_data_vector_82 : in std_logic := 'U'; - addr_data_vector_81 : in std_logic := 'U'; - addr_data_vector_80 : in std_logic := 'U'; - addr_data_vector_92 : in std_logic := 'U'; - addr_data_vector_90 : in std_logic := 'U'; - addr_data_vector_88 : in std_logic := 'U'; - addr_data_vector_87 : in std_logic := 'U'; - addr_data_vector_94 : in std_logic := 'U'; - addr_data_vector_65 : in std_logic := 'U'; - addr_data_vector_64 : in std_logic := 'U'; - addr_data_vector_3 : out std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_27 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_25 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_8 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_12 : out std_logic; - N_1326 : out std_logic; - N_1325 : out std_logic; - N_1323 : out std_logic; - N_1320 : out std_logic; - N_1318 : out std_logic; - N_1315 : out std_logic; - N_1314 : out std_logic; - N_1313 : out std_logic; - N_1312 : out std_logic; - N_1311 : out std_logic; - N_1310 : out std_logic; - N_1309 : out std_logic; - N_1307 : out std_logic; - N_1305 : out std_logic; - N_1303 : out std_logic; - N_1302 : out std_logic; - N_1295 : out std_logic; - N_1280 : out std_logic; - N_1279 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_dma_send_16word - port( un7_dmain : out std_logic_vector(66 to 66); - data_address : in std_logic_vector(31 downto 0) := (others => 'U'); - Store : out std_logic; - Fault : in std_logic := 'U'; - un1_data_send_ok : out std_logic; - Request_0 : in std_logic := 'U'; - N_1011 : out std_logic; - Lock_0 : in std_logic := 'U'; - N_1013 : out std_logic; - N_957 : out std_logic; - N_956 : out std_logic; - N_955 : out std_logic; - N_954 : out std_logic; - N_953 : out std_logic; - N_952 : out std_logic; - N_951 : out std_logic; - N_964 : out std_logic; - N_963 : out std_logic; - N_962 : out std_logic; - N_961 : out std_logic; - N_960 : out std_logic; - time_select : in std_logic := 'U'; - N_959 : out std_logic; - N_958 : out std_logic; - N_971 : out std_logic; - N_970 : out std_logic; - N_969 : out std_logic; - N_968 : out std_logic; - N_967 : out std_logic; - N_966 : out std_logic; - N_965 : out std_logic; - N_978 : out std_logic; - N_977 : out std_logic; - N_976 : out std_logic; - N_975 : out std_logic; - N_974 : out std_logic; - N_973 : out std_logic; - N_972 : out std_logic; - N_950 : out std_logic; - N_949 : out std_logic; - N_948 : out std_logic; - time_select_0 : in std_logic := 'U'; - N_947 : out std_logic; - N_249 : out std_logic; - Grant : in std_logic := 'U'; - Ready : in std_logic := 'U'; - data_send : in std_logic := 'U'; - OKAY : in std_logic := 'U'; - N_200 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(1 to 1); - status_full : out std_logic_vector(1 to 1); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_5 : in std_logic_vector(3 downto 2) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_vector_94 : in std_logic := 'U'; - addr_data_vector_91 : in std_logic := 'U'; - addr_data_vector_89 : in std_logic := 'U'; - addr_data_vector_87 : in std_logic := 'U'; - addr_data_vector_86 : in std_logic := 'U'; - addr_data_vector_85 : in std_logic := 'U'; - addr_data_vector_84 : in std_logic := 'U'; - addr_data_vector_83 : in std_logic := 'U'; - addr_data_vector_67 : in std_logic := 'U'; - addr_data_vector_66 : in std_logic := 'U'; - addr_data_vector_65 : in std_logic := 'U'; - addr_data_vector_64 : in std_logic := 'U'; - addr_data_vector_75 : in std_logic := 'U'; - addr_data_vector_73 : in std_logic := 'U'; - addr_data_vector_81 : in std_logic := 'U'; - addr_data_vector_79 : in std_logic := 'U'; - addr_data_vector_77 : in std_logic := 'U'; - addr_data_vector_24 : out std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_16 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_18 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_5 : out std_logic; - addr_data_vector_4 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_12 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_8 : out std_logic; - N_913 : out std_logic; - N_910 : out std_logic; - N_908 : out std_logic; - N_906 : out std_logic; - N_905 : out std_logic; - N_904 : out std_logic; - N_903 : out std_logic; - N_902 : out std_logic; - N_1300 : out std_logic; - N_1299 : out std_logic; - N_1298 : out std_logic; - N_1297 : out std_logic; - N_1294 : out std_logic; - N_1292 : out std_logic; - N_1286 : out std_logic; - N_1284 : out std_logic; - N_1282 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component lpp_dma_send_1word - port( Lock : out std_logic; - Request : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - un1_time_send_ok : out std_logic; - time_select : in std_logic := 'U'; - Store : in std_logic := 'U'; - N_1012 : out std_logic; - Ready : in std_logic := 'U'; - Fault : in std_logic := 'U'; - time_send : in std_logic := 'U'; - Grant : in std_logic := 'U' - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(3 to 3); - status_full : out std_logic_vector(3 to 3); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_1 : in std_logic_vector(7 downto 6) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(3 to 3) := (others => 'U'); - addr_data_vector_61 : out std_logic; - addr_data_vector_60 : out std_logic; - addr_data_vector_27 : in std_logic := 'U'; - addr_data_vector_25 : in std_logic := 'U'; - addr_data_vector_24 : in std_logic := 'U'; - addr_data_vector_22 : in std_logic := 'U'; - addr_data_vector_20 : in std_logic := 'U'; - addr_data_vector_0 : in std_logic := 'U'; - addr_data_vector_6 : in std_logic := 'U'; - addr_data_vector_4 : in std_logic := 'U'; - addr_data_vector_3 : in std_logic := 'U'; - addr_data_vector_2 : in std_logic := 'U'; - addr_data_vector_1 : in std_logic := 'U'; - addr_data_vector_14 : in std_logic := 'U'; - addr_data_vector_12 : in std_logic := 'U'; - addr_data_vector_10 : in std_logic := 'U'; - addr_data_vector_8 : in std_logic := 'U'; - addr_data_vector_63 : out std_logic; - addr_data_vector_90 : out std_logic; - addr_data_vector_87 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_62 : out std_logic; - addr_data_vector_69 : out std_logic; - addr_data_vector_73 : out std_logic; - addr_data_vector_71 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_83 : out std_logic; - addr_data_vector_75 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_81 : out std_logic; - N_914 : out std_logic; - N_912 : out std_logic; - N_911 : out std_logic; - N_909 : out std_logic; - N_907 : out std_logic; - N_1301 : out std_logic; - N_1293 : out std_logic; - N_1291 : out std_logic; - N_1290 : out std_logic; - N_1289 : out std_logic; - N_1288 : out std_logic; - N_1287 : out std_logic; - N_1285 : out std_logic; - N_1283 : out std_logic; - N_1281 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component DMA2AHB - port( hburst_c : out std_logic_vector(2 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - un7_dmain : in std_logic_vector(66 to 66) := (others => 'U'); - hsize_c : out std_logic_vector(1 downto 0); - AHB_Master_In_c_5 : in std_logic := 'U'; - AHB_Master_In_c_4 : in std_logic := 'U'; - AHB_Master_In_c_0 : in std_logic := 'U'; - AHB_Master_In_c_3 : in std_logic := 'U'; - haddr_c : out std_logic_vector(31 downto 0); - hwrite_c : out std_logic; - Ready : out std_logic; - N_1012 : in std_logic := 'U'; - Grant : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - OKAY : out std_logic; - Fault : out std_logic; - N_1011 : in std_logic := 'U'; - N_1013 : in std_logic := 'U'; - N_43 : out std_logic; - time_select_0 : in std_logic := 'U'; - N_960 : in std_logic := 'U'; - N_959 : in std_logic := 'U'; - N_958 : in std_logic := 'U'; - N_957 : in std_logic := 'U'; - N_964 : in std_logic := 'U'; - N_963 : in std_logic := 'U'; - N_962 : in std_logic := 'U'; - N_961 : in std_logic := 'U'; - N_955 : in std_logic := 'U'; - N_954 : in std_logic := 'U'; - N_953 : in std_logic := 'U'; - N_952 : in std_logic := 'U'; - N_951 : in std_logic := 'U'; - N_950 : in std_logic := 'U'; - N_949 : in std_logic := 'U'; - N_948 : in std_logic := 'U'; - N_947 : in std_logic := 'U'; - N_956 : in std_logic := 'U'; - N_965 : in std_logic := 'U'; - N_966 : in std_logic := 'U'; - N_967 : in std_logic := 'U'; - N_968 : in std_logic := 'U'; - N_969 : in std_logic := 'U'; - N_970 : in std_logic := 'U'; - N_971 : in std_logic := 'U'; - N_972 : in std_logic := 'U'; - N_973 : in std_logic := 'U'; - N_974 : in std_logic := 'U'; - N_975 : in std_logic := 'U'; - N_976 : in std_logic := 'U'; - N_977 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - N_978 : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal count_send_time_e18_0_0, \count_send_time[18]_net_1\, - N_1220, N_1099, \count_send_time_RNO[17]_net_1\, N_1091, - N_1096, N_1137, \count_send_time_RNO[28]_net_1\, N_1156, - \count_send_time[28]_net_1\, - \count_send_time_RNO[29]_net_1\, N_1160, - \count_send_time[29]_net_1\, count_send_time_e31, N_1191, - N_1193, N_1194, count_send_time_e30, N_1126, - count_send_time_e30_0_0, N_1128, N_1146, - \count_send_time[27]_net_1\, count_send_time_e30_0_a2_2_1, - count_send_time_e25, N_1178, N_1177, N_1180, - count_send_time_e24, N_1173, N_1172, N_1175, N_1161, - \count_send_time[31]_net_1\, \state[2]_net_1\, N_1162, - N_1145_0, \count_send_time[25]_net_1\, - count_send_time_e25_0_o3_N_7_i_0, - \count_send_time[23]_net_1\, N_1069, - count_send_time_e24_0_a2_1_0, - count_send_time_e24_0_a2_0_0, count_send_time_e23, N_1121, - N_1122, N_1123, count_send_time_e22, N_1117, N_1118, - N_1119, count_send_time_e21, N_1112, N_1113, N_1114, - count_send_time_e20, N_1107, N_1108, N_1109, - count_send_time_e19, N_1103, N_1102, N_1104, - count_send_time_e18, count_send_time_e30_0_a2_0_0, - \count_send_time[21]_net_1\, N_1066, - count_send_time_e22_0_a2_1_0, count_send_time_e22_0_a2_0, - N_1145, N_1063, \count_send_time[19]_net_1\, - count_send_time_e20_0_a2_1_0, count_send_time_e20_0_a2_0, - \count_send_time[17]_net_1\, N_1061, - count_send_time_e18_0_a2_0_0, N_1059, - \count_send_time[15]_net_1\, - count_send_time_e25_0_o3_m6_0_a2_7, N_1057, - \count_send_time[11]_net_1\, \count_send_time[12]_net_1\, - N_1159, \count_send_time[13]_net_1\, - \count_send_time[14]_net_1\, \count_send_time[16]_net_1\, - \count_send_time[20]_net_1\, \count_send_time[22]_net_1\, - \count_send_time_RNO[26]_net_1\, N_1163, - \count_send_time[26]_net_1\, - \count_send_time_RNO[27]_net_1\, N_1164, - \count_send_time[9]_net_1\, \count_send_time[10]_net_1\, - N_1225, N_1217, \count_send_time[0]_net_1\, - \count_send_time[1]_net_1\, \count_send_time[2]_net_1\, - N_1219, \count_send_time[3]_net_1\, - \count_send_time[4]_net_1\, N_1223, - \count_send_time[5]_net_1\, \count_send_time[6]_net_1\, - \count_send_time[7]_net_1\, \count_send_time[8]_net_1\, - \sel_data_0[0]_net_1\, N_1016_i_0, \state[7]_net_1\, - \sel_data_1[1]_net_1\, N_1015, \sel_data_0[1]_net_1\, - \state_0[2]_net_1\, \state_ns_i_a2_0[5]_net_1\, - \time_select_0\, time_fifo_ren_1, N_816, - time_fifo_ren_1_i, N_1049, N_1026, \state[4]_net_1\, - \state_ns_i_a2_0_1[5]\, N_1048, \state_ns_i_a2_0_0[5]\, - \count_send_time[24]_net_1\, \count_send_time[30]_net_1\, - N_1125, N_1075, count_send_time_e16_i_0, N_1077, - \state_ns_i_a2_0_a4_0_19_i[5]\, N_1050, - count_send_time_e25_0_o3_m6_0_a2_2, - count_send_time_e25_0_o3_m6_0_a2_1, - count_send_time_e25_0_o3_m6_0_a2_6, - count_send_time_e25_0_o3_m6_0_a2_4, - count_send_time_e14_i_0, - \count_send_time_RNO_1[14]_net_1\, state_tr2_i_0, - \send_16_3_time[0]_net_1\, - \state_ns_i_a2_0_a3_0[5]_net_1\, - \send_16_3_time_1_sqmuxa_i_o3_0\, - count_send_time_e12_0_a2_0_0, - count_send_time_e12_0_a2_1_0, count_send_time_e10_0_a2_0, - count_send_time_e10_0_a2_1_0, count_send_time_e8_0_a2_0, - count_send_time_e8_0_a2_1_0, count_send_time_e2_0_a2_1_0, - state_tr13_0_a2_15, state_tr13_0_a2_9_0, - state_tr13_0_a2_8, state_tr13_0_a2_12, state_tr13_0_a2_14, - state_tr13_0_a2_10, state_tr13_0_a2_9, state_tr13_0_a2_7, - state_tr13_0_a2_17_0, state_tr13_0_a2_17_1, - state_tr13_0_a2_6, state_tr13_0_a2_4, state_tr13_0_a2_2, - \state_ns_i_a2_0_a4_0_19_15[5]\, N_1047_25, - \state_ns_i_a2_0_a4_0_19_12[5]\, - \state_ns_i_a2_0_a4_0_19_11[5]\, N_1047_5, - \state_ns_i_a2_0_a4_0_25_4[5]\, - \state_ns_i_a2_0_a4_0_25_2[5]\, - \state_ns_i_a2_0_a4_0_25_1[5]\, - \state_ns_i_a2_0_a4_0_25_0[5]\, - count_send_time_e2_0_a2_0_0, un1_state_13_0_a4_0_0, - \state[1]_net_1\, \state[3]_net_1\, - \state_ns_i_a2_0_a4_0_19_9_0[5]\, - \count_send_time_RNO[14]_net_1\, - \count_send_time_RNO[15]_net_1\, N_1092, - \count_send_time_RNO[16]_net_1\, - \count_send_time_RNO[6]_net_1\, N_1253, N_1230, - \count_send_time_RNO[7]_net_1\, \state_ns[6]\, - count_send_time_e10, N_1270, N_1272, N_1273, - count_send_time_e9, N_1265, N_1267, N_1268, - count_send_time_e8, N_1260, N_1262, N_1263, - count_send_time_e3, N_1249, N_1247, N_1246, - count_send_time_e2, N_1244, N_1242, N_1241, - count_send_time_e1, N_1239, N_1237, N_1236, - count_send_time_e11, N_1167, N_1169, N_1170, - count_send_time_e13, N_1086, N_1085, N_1087, - count_send_time_e12, N_1081, N_1080, N_1082, - \state_RNO[6]_net_1\, N_1027, N_1036, N_812, - \state[0]_net_1\, N_1037, un5_time_write, - \sel_data[1]_net_1\, \un13_time_write\, \un20_time_write\, - un27_time_write, un7_time_write, \time_write\, - un15_time_write, un22_time_write, un29_time_write, - un2_status_full_ack, un7_status_full_ack, - un12_status_full_ack, un17_status_full_ack, \data_ren\, - N_200, N_249, \time_select\, \time_ren\, - \update_and_sel_1[6]\, \update[0]_net_1\, - \update_and_sel_1[7]\, \update[1]_net_1\, - \update_and_sel_3[4]\, \update_and_sel_3[5]\, - \update_and_sel_5[2]\, \update_and_sel_5[3]\, - \update_and_sel_7[0]\, \update_and_sel_7[1]\, - \data_address[0]\, N_1279, N_1297, \data_address[1]\, - N_1280, N_1298, \data_address[2]\, N_1323, N_1299, - \data_address[3]\, N_1324, N_1300, \data_address[4]\, - N_1325, N_1301, \data_address[5]\, N_1326, N_1288, - \data_address[6]\, N_1327, N_1289, \data_address[7]\, - N_1328, N_1290, \data_address[8]\, N_1329, N_1291, - \data_address[9]\, N_1316, N_1292, \data_address[10]\, - N_1317, N_1293, \data_address[11]\, N_1318, N_1294, - \data_address[12]\, N_1319, N_1281, \data_address[13]\, - N_1320, N_1282, \data_address[14]\, N_1321, N_1283, - \sel_data[0]_net_1\, \data_address[15]\, N_1322, N_1284, - \data_address[16]\, N_1309, N_1285, \data_address[17]\, - N_1310, N_1286, \data_address[18]\, N_1311, N_1287, - \data_address[19]\, N_1312, N_902, \data_address[20]\, - N_1313, N_903, \data_address[21]\, N_1314, N_904, - \data_address[22]\, N_1315, N_905, \data_address[23]\, - N_1302, N_906, \data_address[24]\, N_1303, N_907, - \data_address[25]\, N_1304, N_908, \data_address[26]\, - N_1305, N_909, \data_address[27]\, N_1306, N_910, - \data_address[28]\, N_1307, N_911, \data_address[29]\, - N_1308, N_912, \data_address[30]\, N_1295, N_913, - \data_address[31]\, N_1296, N_914, N_1024, - \time_already_send[3]\, \time_already_send[2]\, N_1025, - \time_already_send[1]\, \count_send_time_RNO_1[6]_net_1\, - count_send_time_e0, \count_send_time_RNO[4]_net_1\, - N_1227, \count_send_time_RNO[5]_net_1\, N_1228, - \state_RNO_1[0]\, un1_data_send_ok, N_815, N_1040, N_1014, - \state_RNO[7]_net_1\, \time_fifo_ren\, N_1030, - un1_state_12, \state[6]_net_1\, \time_already_send[0]\, - \state_RNO_2[3]\, N_1033, \state_RNO_0[4]_net_1\, N_1044, - \state_RNO[5]_net_1\, N_1042, un1_state_13, - un1_time_send_ok, \state[5]_net_1\, time_send_0_sqmuxa, - update_0_sqmuxa, \time_send\, \data_send\, - \send_16_3_time[2]_net_1\, \send_16_3_time[1]_net_1\, - \un7_dmain[66]\, Ready, N_1012, Grant, OKAY, Fault, - N_1011, N_1013, N_960, N_959, N_958, N_957, N_964, N_963, - N_962, N_961, N_955, N_954, N_953, N_952, N_951, N_950, - N_949, N_948, N_947, N_956, N_965, N_966, N_967, N_968, - N_969, N_970, N_971, N_972, N_973, N_974, N_975, N_976, - N_977, N_978, Lock, Request, Store, - \addr_data_vector[97]\, \addr_data_vector[96]\, - \addr_data_vector[63]\, \addr_data_vector[61]\, - \addr_data_vector[60]\, \addr_data_vector[58]\, - \addr_data_vector[56]\, \addr_data_vector[36]\, - \addr_data_vector[42]\, \addr_data_vector[40]\, - \addr_data_vector[39]\, \addr_data_vector[38]\, - \addr_data_vector[37]\, \addr_data_vector[50]\, - \addr_data_vector[48]\, \addr_data_vector[46]\, - \addr_data_vector[44]\, \addr_data_vector[99]\, - \addr_data_vector[126]\, \addr_data_vector[123]\, - \addr_data_vector[121]\, \addr_data_vector[98]\, - \addr_data_vector[105]\, \addr_data_vector[109]\, - \addr_data_vector[107]\, \addr_data_vector[113]\, - \addr_data_vector[115]\, \addr_data_vector[118]\, - \addr_data_vector[119]\, \addr_data_vector[111]\, - \addr_data_vector[116]\, \addr_data_vector[117]\, - \addr_data_vector[65]\, \addr_data_vector[64]\, - \addr_data_vector[8]\, \addr_data_vector[7]\, - \addr_data_vector[6]\, \addr_data_vector[3]\, - \addr_data_vector[15]\, \addr_data_vector[14]\, - \addr_data_vector[12]\, \addr_data_vector[10]\, - \addr_data_vector[9]\, \addr_data_vector[29]\, - \addr_data_vector[27]\, \addr_data_vector[25]\, - \addr_data_vector[31]\, \addr_data_vector[69]\, - \addr_data_vector[68]\, \addr_data_vector[94]\, - \addr_data_vector[92]\, \addr_data_vector[90]\, - \addr_data_vector[66]\, \addr_data_vector[75]\, - \addr_data_vector[77]\, \addr_data_vector[82]\, - \addr_data_vector[81]\, \addr_data_vector[84]\, - \addr_data_vector[83]\, \addr_data_vector[87]\, - \addr_data_vector[88]\, \addr_data_vector[80]\, - \addr_data_vector[85]\, \addr_data_vector[86]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\(DEF_ARCH); - for all : lpp_dma_send_16word - Use entity work.lpp_dma_send_16word(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\(DEF_ARCH); - for all : lpp_dma_send_1word - Use entity work.lpp_dma_send_1word(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\(DEF_ARCH); - for all : DMA2AHB - Use entity work.DMA2AHB(DEF_ARCH); -begin - - time_ren_1z <= \time_ren\; - data_ren_1z <= \data_ren\; - un20_time_write <= \un20_time_write\; - un13_time_write <= \un13_time_write\; - - \state[0]\ : DFN1C0 - port map(D => \state_RNO_1[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[0]_net_1\); - - \count_send_time_RNO_0[9]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[9]_net_1\, C => N_1225, Y => N_1265); - - \count_send_time_RNO_4[30]\ : OR3C - port map(A => N_1075, B => \count_send_time[30]_net_1\, C - => N_1091, Y => N_1125); - - \sel_data[0]\ : DFN1E1C0 - port map(D => N_1016_i_0, CLK => HCLK_c, CLR => HRESETn_c, - E => \state[7]_net_1\, Q => \sel_data[0]_net_1\); - - \gen_select_address.2.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(2) => status_full_err(2), status_full(2) - => status_full(2), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, sel_data_0(1) => - \sel_data_0[1]_net_1\, update_and_sel_3(5) => - \update_and_sel_3[5]\, update_and_sel_3(4) => - \update_and_sel_3[4]\, addr_data_f2(31) => - addr_data_f2(31), addr_data_f2(30) => addr_data_f2(30), - addr_data_f2(29) => addr_data_f2(29), addr_data_f2(28) - => addr_data_f2(28), addr_data_f2(27) => - addr_data_f2(27), addr_data_f2(26) => addr_data_f2(26), - addr_data_f2(25) => addr_data_f2(25), addr_data_f2(24) - => addr_data_f2(24), addr_data_f2(23) => - addr_data_f2(23), addr_data_f2(22) => addr_data_f2(22), - addr_data_f2(21) => addr_data_f2(21), addr_data_f2(20) - => addr_data_f2(20), addr_data_f2(19) => - addr_data_f2(19), addr_data_f2(18) => addr_data_f2(18), - addr_data_f2(17) => addr_data_f2(17), addr_data_f2(16) - => addr_data_f2(16), addr_data_f2(15) => - addr_data_f2(15), addr_data_f2(14) => addr_data_f2(14), - addr_data_f2(13) => addr_data_f2(13), addr_data_f2(12) - => addr_data_f2(12), addr_data_f2(11) => - addr_data_f2(11), addr_data_f2(10) => addr_data_f2(10), - addr_data_f2(9) => addr_data_f2(9), addr_data_f2(8) => - addr_data_f2(8), addr_data_f2(7) => addr_data_f2(7), - addr_data_f2(6) => addr_data_f2(6), addr_data_f2(5) => - addr_data_f2(5), addr_data_f2(4) => addr_data_f2(4), - addr_data_f2(3) => addr_data_f2(3), addr_data_f2(2) => - addr_data_f2(2), addr_data_f2(1) => addr_data_f2(1), - addr_data_f2(0) => addr_data_f2(0), status_full_ack(2) - => status_full_ack(2), addr_data_vector_62 => - \addr_data_vector[65]\, addr_data_vector_61 => - \addr_data_vector[64]\, addr_data_vector_5 => - \addr_data_vector[8]\, addr_data_vector_4 => - \addr_data_vector[7]\, addr_data_vector_3 => - \addr_data_vector[6]\, addr_data_vector_0 => - \addr_data_vector[3]\, addr_data_vector_12 => - \addr_data_vector[15]\, addr_data_vector_11 => - \addr_data_vector[14]\, addr_data_vector_9 => - \addr_data_vector[12]\, addr_data_vector_7 => - \addr_data_vector[10]\, addr_data_vector_6 => - \addr_data_vector[9]\, addr_data_vector_26 => - \addr_data_vector[29]\, addr_data_vector_24 => - \addr_data_vector[27]\, addr_data_vector_22 => - \addr_data_vector[25]\, addr_data_vector_28 => - \addr_data_vector[31]\, addr_data_vector_66 => - \addr_data_vector[69]\, addr_data_vector_65 => - \addr_data_vector[68]\, addr_data_vector_91 => - \addr_data_vector[94]\, addr_data_vector_89 => - \addr_data_vector[92]\, addr_data_vector_87 => - \addr_data_vector[90]\, addr_data_vector_63 => - \addr_data_vector[66]\, addr_data_vector_72 => - \addr_data_vector[75]\, addr_data_vector_74 => - \addr_data_vector[77]\, addr_data_vector_79 => - \addr_data_vector[82]\, addr_data_vector_78 => - \addr_data_vector[81]\, addr_data_vector_81 => - \addr_data_vector[84]\, addr_data_vector_80 => - \addr_data_vector[83]\, addr_data_vector_84 => - \addr_data_vector[87]\, addr_data_vector_85 => - \addr_data_vector[88]\, addr_data_vector_77 => - \addr_data_vector[80]\, addr_data_vector_82 => - \addr_data_vector[85]\, addr_data_vector_83 => - \addr_data_vector[86]\, N_1329 => N_1329, N_1328 => - N_1328, N_1327 => N_1327, N_1324 => N_1324, N_1322 => - N_1322, N_1321 => N_1321, N_1319 => N_1319, N_1317 => - N_1317, N_1316 => N_1316, N_1308 => N_1308, N_1306 => - N_1306, N_1304 => N_1304, N_1296 => N_1296, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \count_send_time_RNIRUBI[20]\ : NOR3C - port map(A => count_send_time_e25_0_o3_m6_0_a2_2, B => - count_send_time_e25_0_o3_m6_0_a2_1, C => - count_send_time_e25_0_o3_m6_0_a2_6, Y => - count_send_time_e25_0_o3_m6_0_a2_7); - - \count_send_time_RNO_0[16]\ : OAI1 - port map(A => N_1077, B => \count_send_time[16]_net_1\, C - => N_1091, Y => count_send_time_e16_i_0); - - \count_send_time_RNO_2[1]\ : OR2B - port map(A => \count_send_time[1]_net_1\, B => N_1220, Y - => N_1236); - - \count_send_time_RNO[4]\ : XA1A - port map(A => N_1227, B => \count_send_time[4]_net_1\, C - => N_1091, Y => \count_send_time_RNO[4]_net_1\); - - \count_send_time_RNINOP61[10]\ : OR3B - port map(A => \count_send_time[9]_net_1\, B => - \count_send_time[10]_net_1\, C => N_1225, Y => N_1159); - - \gen_select_address.0.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(0) => status_full_err(0), status_full(0) - => status_full(0), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, sel_data_0(1) => - \sel_data_0[1]_net_1\, update_and_sel_7(1) => - \update_and_sel_7[1]\, update_and_sel_7(0) => - \update_and_sel_7[0]\, addr_data_f0(31) => - addr_data_f0(31), addr_data_f0(30) => addr_data_f0(30), - addr_data_f0(29) => addr_data_f0(29), addr_data_f0(28) - => addr_data_f0(28), addr_data_f0(27) => - addr_data_f0(27), addr_data_f0(26) => addr_data_f0(26), - addr_data_f0(25) => addr_data_f0(25), addr_data_f0(24) - => addr_data_f0(24), addr_data_f0(23) => - addr_data_f0(23), addr_data_f0(22) => addr_data_f0(22), - addr_data_f0(21) => addr_data_f0(21), addr_data_f0(20) - => addr_data_f0(20), addr_data_f0(19) => - addr_data_f0(19), addr_data_f0(18) => addr_data_f0(18), - addr_data_f0(17) => addr_data_f0(17), addr_data_f0(16) - => addr_data_f0(16), addr_data_f0(15) => - addr_data_f0(15), addr_data_f0(14) => addr_data_f0(14), - addr_data_f0(13) => addr_data_f0(13), addr_data_f0(12) - => addr_data_f0(12), addr_data_f0(11) => - addr_data_f0(11), addr_data_f0(10) => addr_data_f0(10), - addr_data_f0(9) => addr_data_f0(9), addr_data_f0(8) => - addr_data_f0(8), addr_data_f0(7) => addr_data_f0(7), - addr_data_f0(6) => addr_data_f0(6), addr_data_f0(5) => - addr_data_f0(5), addr_data_f0(4) => addr_data_f0(4), - addr_data_f0(3) => addr_data_f0(3), addr_data_f0(2) => - addr_data_f0(2), addr_data_f0(1) => addr_data_f0(1), - addr_data_f0(0) => addr_data_f0(0), status_full_ack(0) - => status_full_ack(0), addr_data_vector_69 => - \addr_data_vector[69]\, addr_data_vector_68 => - \addr_data_vector[68]\, addr_data_vector_66 => - \addr_data_vector[66]\, addr_data_vector_77 => - \addr_data_vector[77]\, addr_data_vector_75 => - \addr_data_vector[75]\, addr_data_vector_86 => - \addr_data_vector[86]\, addr_data_vector_85 => - \addr_data_vector[85]\, addr_data_vector_84 => - \addr_data_vector[84]\, addr_data_vector_83 => - \addr_data_vector[83]\, addr_data_vector_82 => - \addr_data_vector[82]\, addr_data_vector_81 => - \addr_data_vector[81]\, addr_data_vector_80 => - \addr_data_vector[80]\, addr_data_vector_92 => - \addr_data_vector[92]\, addr_data_vector_90 => - \addr_data_vector[90]\, addr_data_vector_88 => - \addr_data_vector[88]\, addr_data_vector_87 => - \addr_data_vector[87]\, addr_data_vector_94 => - \addr_data_vector[94]\, addr_data_vector_65 => - \addr_data_vector[65]\, addr_data_vector_64 => - \addr_data_vector[64]\, addr_data_vector_3 => - \addr_data_vector[3]\, addr_data_vector_31 => - \addr_data_vector[31]\, addr_data_vector_14 => - \addr_data_vector[14]\, addr_data_vector_15 => - \addr_data_vector[15]\, addr_data_vector_27 => - \addr_data_vector[27]\, addr_data_vector_29 => - \addr_data_vector[29]\, addr_data_vector_25 => - \addr_data_vector[25]\, addr_data_vector_6 => - \addr_data_vector[6]\, addr_data_vector_8 => - \addr_data_vector[8]\, addr_data_vector_7 => - \addr_data_vector[7]\, addr_data_vector_10 => - \addr_data_vector[10]\, addr_data_vector_9 => - \addr_data_vector[9]\, addr_data_vector_12 => - \addr_data_vector[12]\, N_1326 => N_1326, N_1325 => - N_1325, N_1323 => N_1323, N_1320 => N_1320, N_1318 => - N_1318, N_1315 => N_1315, N_1314 => N_1314, N_1313 => - N_1313, N_1312 => N_1312, N_1311 => N_1311, N_1310 => - N_1310, N_1309 => N_1309, N_1307 => N_1307, N_1305 => - N_1305, N_1303 => N_1303, N_1302 => N_1302, N_1295 => - N_1295, N_1280 => N_1280, N_1279 => N_1279, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \count_send_time_RNIFF6R1[20]\ : OR3C - port map(A => N_1063, B => \count_send_time[19]_net_1\, C - => \count_send_time[20]_net_1\, Y => N_1066); - - \sel_data_0_RNI0MA8[0]\ : OR2B - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => un5_time_write); - - \count_send_time_RNO[26]\ : XA1A - port map(A => N_1163, B => \count_send_time[26]_net_1\, C - => N_1091, Y => \count_send_time_RNO[26]_net_1\); - - \count_send_time_RNINK24[24]\ : NOR2B - port map(A => \count_send_time[24]_net_1\, B => - \count_send_time[18]_net_1\, Y => - count_send_time_e25_0_o3_m6_0_a2_1); - - \sel_data_RNIM70E[0]\ : MX2C - port map(A => N_1308, B => N_912, S => \sel_data[0]_net_1\, - Y => \data_address[29]\); - - \all_time_write.0.time_already_send_RNI944DP[0]\ : MX2 - port map(A => N_1025, B => \time_already_send[0]\, S => - ready_i_0(0), Y => N_1026); - - \count_send_time[0]\ : DFN1 - port map(D => count_send_time_e0, CLK => HCLK_c, Q => - \count_send_time[0]_net_1\); - - \count_send_time_RNO_3[2]\ : OR3B - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => - \count_send_time[2]_net_1\, Y => - count_send_time_e2_0_a2_1_0); - - \count_send_time_RNO_0[10]\ : AO1C - port map(A => N_1225, B => \count_send_time[9]_net_1\, C - => count_send_time_e10_0_a2_0, Y => N_1270); - - \count_send_time_RNO[2]\ : OR3C - port map(A => N_1244, B => N_1242, C => N_1241, Y => - count_send_time_e2); - - time_fifo_ren_RNO : INV - port map(A => time_fifo_ren_1, Y => time_fifo_ren_1_i); - - lpp_dma_send_16word_1 : lpp_dma_send_16word - port map(un7_dmain(66) => \un7_dmain[66]\, data_address(31) - => \data_address[31]\, data_address(30) => - \data_address[30]\, data_address(29) => - \data_address[29]\, data_address(28) => - \data_address[28]\, data_address(27) => - \data_address[27]\, data_address(26) => - \data_address[26]\, data_address(25) => - \data_address[25]\, data_address(24) => - \data_address[24]\, data_address(23) => - \data_address[23]\, data_address(22) => - \data_address[22]\, data_address(21) => - \data_address[21]\, data_address(20) => - \data_address[20]\, data_address(19) => - \data_address[19]\, data_address(18) => - \data_address[18]\, data_address(17) => - \data_address[17]\, data_address(16) => - \data_address[16]\, data_address(15) => - \data_address[15]\, data_address(14) => - \data_address[14]\, data_address(13) => - \data_address[13]\, data_address(12) => - \data_address[12]\, data_address(11) => - \data_address[11]\, data_address(10) => - \data_address[10]\, data_address(9) => \data_address[9]\, - data_address(8) => \data_address[8]\, data_address(7) => - \data_address[7]\, data_address(6) => \data_address[6]\, - data_address(5) => \data_address[5]\, data_address(4) => - \data_address[4]\, data_address(3) => \data_address[3]\, - data_address(2) => \data_address[2]\, data_address(1) => - \data_address[1]\, data_address(0) => \data_address[0]\, - Store => Store, Fault => Fault, un1_data_send_ok => - un1_data_send_ok, Request_0 => Request, N_1011 => N_1011, - Lock_0 => Lock, N_1013 => N_1013, N_957 => N_957, N_956 - => N_956, N_955 => N_955, N_954 => N_954, N_953 => N_953, - N_952 => N_952, N_951 => N_951, N_964 => N_964, N_963 => - N_963, N_962 => N_962, N_961 => N_961, N_960 => N_960, - time_select => \time_select\, N_959 => N_959, N_958 => - N_958, N_971 => N_971, N_970 => N_970, N_969 => N_969, - N_968 => N_968, N_967 => N_967, N_966 => N_966, N_965 => - N_965, N_978 => N_978, N_977 => N_977, N_976 => N_976, - N_975 => N_975, N_974 => N_974, N_973 => N_973, N_972 => - N_972, N_950 => N_950, N_949 => N_949, N_948 => N_948, - time_select_0 => \time_select_0\, N_947 => N_947, N_249 - => N_249, Grant => Grant, Ready => Ready, data_send => - \data_send\, OKAY => OKAY, N_200 => N_200, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \count_send_time_RNO_1[6]\ : NOR3B - port map(A => N_1219, B => \count_send_time[5]_net_1\, C - => N_1145, Y => \count_send_time_RNO_1[6]_net_1\); - - \count_send_time_RNO_0[27]\ : OR2A - port map(A => N_1146, B => N_1145, Y => N_1164); - - \count_send_time_RNO_1[19]\ : OR2B - port map(A => \count_send_time[19]_net_1\, B => N_1220, Y - => N_1102); - - \count_send_time_RNIRQ3N1[17]\ : NOR3C - port map(A => N_1061, B => \count_send_time[17]_net_1\, C - => \count_send_time[18]_net_1\, Y => N_1063); - - \count_send_time[14]\ : DFN1 - port map(D => \count_send_time_RNO[14]_net_1\, CLK => - HCLK_c, Q => \count_send_time[14]_net_1\); - - \state[6]\ : DFN1C0 - port map(D => \state_RNO[6]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[6]_net_1\); - - \count_send_time_RNO_2[18]\ : NOR2B - port map(A => \count_send_time[18]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e18_0_a2_0_0); - - \count_send_time[21]\ : DFN1 - port map(D => count_send_time_e21, CLK => HCLK_c, Q => - \count_send_time[21]_net_1\); - - \count_send_time_RNO[14]\ : OA1C - port map(A => N_1059, B => N_1145_0, C => - count_send_time_e14_i_0, Y => - \count_send_time_RNO[14]_net_1\); - - \count_send_time[31]\ : DFN1 - port map(D => count_send_time_e31, CLK => HCLK_c, Q => - \count_send_time[31]_net_1\); - - \update_RNIPECD_0[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un20_time_write\, Y - => \update_and_sel_5[3]\); - - \sel_data_RNIP45D[0]\ : MX2C - port map(A => N_1321, B => N_1283, S => \sel_data[0]_net_1\, - Y => \data_address[14]\); - - \count_send_time_RNI8KVA[2]\ : OR3C - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => - \count_send_time[2]_net_1\, Y => N_1217); - - \count_send_time_RNO[22]\ : OR3C - port map(A => N_1117, B => N_1118, C => N_1119, Y => - count_send_time_e22); - - time_write_RNO : AO1D - port map(A => un1_state_13_0_a4_0_0, B => \state[7]_net_1\, - C => N_1033, Y => un1_state_13); - - \count_send_time[17]\ : DFN1 - port map(D => \count_send_time_RNO[17]_net_1\, CLK => - HCLK_c, Q => \count_send_time[17]_net_1\); - - \state_RNIKSS3_0[2]\ : OAI1 - port map(A => \state[2]_net_1\, B => \state[7]_net_1\, C - => HRESETn_c, Y => N_1220); - - \count_send_time_RNO_0[3]\ : OR3 - port map(A => N_1217, B => \count_send_time[3]_net_1\, C - => N_1145_0, Y => N_1249); - - \all_data_ren.2.data_time_ren_3[2]\ : OR2A - port map(A => \time_ren\, B => \un13_time_write\, Y => - time_ren(2)); - - \all_data_ren.1.data_data_ren_5[1]\ : OR2A - port map(A => \data_ren\, B => \un20_time_write\, Y => - data_ren(1)); - - \count_send_time_RNO_2[8]\ : OR3B - port map(A => N_1223, B => \count_send_time[7]_net_1\, C - => count_send_time_e8_0_a2_1_0, Y => N_1263); - - \count_send_time_RNIN9B7[4]\ : NOR2 - port map(A => \count_send_time[4]_net_1\, B => - \count_send_time[5]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_0[5]\); - - \update_RNIOECD_1[0]\ : OR2A - port map(A => \update[0]_net_1\, B => \un13_time_write\, Y - => \update_and_sel_3[4]\); - - \state_ns_i_a2_0_a3_0[5]\ : NAND2 - port map(A => N_1026, B => \state[4]_net_1\, Y => N_1049); - - \sel_data_0_RNIKH5P[0]\ : MX2C - port map(A => N_1324, B => N_1300, S => - \sel_data_0[0]_net_1\, Y => \data_address[3]\); - - \count_send_time_RNO[7]\ : XA1 - port map(A => N_1230, B => \count_send_time[7]_net_1\, C - => N_1091, Y => \count_send_time_RNO[7]_net_1\); - - \count_send_time_RNO_2[9]\ : OR3 - port map(A => N_1145_0, B => \count_send_time[9]_net_1\, C - => N_1225, Y => N_1268); - - \sel_data_0_RNIKIAC[0]\ : MX2C - port map(A => N_1319, B => N_1281, S => - \sel_data_0[0]_net_1\, Y => \data_address[12]\); - - \count_send_time[25]\ : DFN1 - port map(D => count_send_time_e25, CLK => HCLK_c, Q => - \count_send_time[25]_net_1\); - - \update_RNIPECD[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => un5_time_write, Y => - \update_and_sel_1[7]\); - - \count_send_time[5]\ : DFN1 - port map(D => \count_send_time_RNO[5]_net_1\, CLK => HCLK_c, - Q => \count_send_time[5]_net_1\); - - \update[1]\ : DFN1E0C0 - port map(D => \state[0]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_12, Q => \update[1]_net_1\); - - time_select : DFN1E1C0 - port map(D => time_fifo_ren_1, CLK => HCLK_c, CLR => - HRESETn_c, E => N_816, Q => \time_select\); - - \count_send_time_RNO_0[2]\ : OR2 - port map(A => count_send_time_e2_0_a2_1_0, B => N_1145_0, Y - => N_1244); - - \count_send_time_RNO[27]\ : XA1A - port map(A => N_1164, B => \count_send_time[27]_net_1\, C - => N_1091, Y => \count_send_time_RNO[27]_net_1\); - - \update_RNIOECD_0[0]\ : OR2A - port map(A => \update[0]_net_1\, B => \un20_time_write\, Y - => \update_and_sel_5[2]\); - - \state_RNIHU8A[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => un1_time_send_ok, Y - => N_1033); - - \sel_data_RNIU60E[0]\ : MX2C - port map(A => N_1302, B => N_906, S => \sel_data[0]_net_1\, - Y => \data_address[23]\); - - \count_send_time_RNO_1[10]\ : OR2B - port map(A => \count_send_time[10]_net_1\, B => N_1220, Y - => N_1272); - - \count_send_time_RNO[0]\ : MX2A - port map(A => N_1145, B => N_1220, S => - \count_send_time[0]_net_1\, Y => count_send_time_e0); - - \count_send_time_RNO[10]\ : OR3C - port map(A => N_1270, B => N_1272, C => N_1273, Y => - count_send_time_e10); - - \all_time_write.3.time_already_send[3]\ : DFN1E1C0 - port map(D => un7_time_write, CLK => HCLK_c, CLR => - HRESETn_c, E => un2_status_full_ack, Q => - \time_already_send[3]\); - - \sel_data_0[1]\ : DFN1E1C0 - port map(D => N_1015, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[7]_net_1\, Q => \sel_data_0[1]_net_1\); - - \count_send_time_RNO_4[12]\ : OR2 - port map(A => \count_send_time[12]_net_1\, B => N_1145_0, Y - => count_send_time_e12_0_a2_1_0); - - \count_send_time_RNI4A1J1[16]\ : NOR3C - port map(A => N_1059, B => \count_send_time[15]_net_1\, C - => \count_send_time[16]_net_1\, Y => N_1061); - - \state[4]\ : DFN1C0 - port map(D => \state_RNO_0[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state[4]_net_1\); - - time_write : DFN1E0C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_13, Q => \time_write\); - - data_send_RNO : NOR3 - port map(A => \state[0]_net_1\, B => \state[1]_net_1\, C - => \state[7]_net_1\, Y => N_812); - - \sel_data_1[1]\ : DFN1E1C0 - port map(D => N_1015, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[7]_net_1\, Q => \sel_data_1[1]_net_1\); - - \sel_data_0_RNIBH4P[0]\ : MX2C - port map(A => N_1280, B => N_1298, S => - \sel_data_0[0]_net_1\, Y => \data_address[1]\); - - \count_send_time[28]\ : DFN1 - port map(D => \count_send_time_RNO[28]_net_1\, CLK => - HCLK_c, Q => \count_send_time[28]_net_1\); - - \update_RNIOECD[0]\ : OR2A - port map(A => \update[0]_net_1\, B => un5_time_write, Y => - \update_and_sel_1[6]\); - - \sel_data_RNIANVD[0]\ : MX2C - port map(A => N_1312, B => N_902, S => \sel_data[0]_net_1\, - Y => \data_address[19]\); - - \count_send_time_RNIGL6A[22]\ : NOR3C - port map(A => \count_send_time[22]_net_1\, B => - \count_send_time[21]_net_1\, C => - count_send_time_e25_0_o3_m6_0_a2_4, Y => - count_send_time_e25_0_o3_m6_0_a2_6); - - \count_send_time[8]\ : DFN1 - port map(D => count_send_time_e8, CLK => HCLK_c, Q => - \count_send_time[8]_net_1\); - - \sel_data_0_RNIO31Q[0]\ : MX2C - port map(A => N_1326, B => N_1288, S => - \sel_data_0[0]_net_1\, Y => \data_address[5]\); - - \count_send_time_RNO[13]\ : OR3C - port map(A => N_1086, B => N_1085, C => N_1087, Y => - count_send_time_e13); - - \state[7]\ : DFN1P0 - port map(D => \state_RNO[7]_net_1\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[7]_net_1\); - - \count_send_time_RNIT09T[6]\ : NOR2A - port map(A => N_1223, B => N_1145, Y => N_1230); - - \count_send_time_RNO[3]\ : OR3C - port map(A => N_1249, B => N_1247, C => N_1246, Y => - count_send_time_e3); - - \count_send_time[10]\ : DFN1 - port map(D => count_send_time_e10, CLK => HCLK_c, Q => - \count_send_time[10]_net_1\); - - time_write_RNI6IL9_2 : NOR2A - port map(A => \time_write\, B => un27_time_write, Y => - un29_time_write); - - \count_send_time_RNO_2[30]\ : OR3B - port map(A => N_1146, B => \count_send_time[27]_net_1\, C - => count_send_time_e30_0_a2_2_1, Y => N_1128); - - \state[5]\ : DFN1C0 - port map(D => \state_RNO[5]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[5]_net_1\); - - data_send : DFN1E0C0 - port map(D => \state[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_812, Q => \data_send\); - - \count_send_time_RNI9946[30]\ : OR2A - port map(A => \count_send_time[30]_net_1\, B => N_1075, Y - => N_1161); - - \DMAWriteFSM_p.sel_data_3_i_a4[0]\ : OR2A - port map(A => ready_i_0(2), B => ready_i_0(1), Y => N_1037); - - \sel_data_0_RNIG15P[0]\ : MX2C - port map(A => N_1323, B => N_1299, S => - \sel_data_0[0]_net_1\, Y => \data_address[2]\); - - \update_RNIPECD_2[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => un27_time_write, Y - => \update_and_sel_7[1]\); - - \count_send_time_RNO_1[2]\ : OR2B - port map(A => count_send_time_e2_0_a2_0_0, B => - \state_0[2]_net_1\, Y => N_1242); - - \state_RNIMMJ[4]\ : NOR2 - port map(A => \state[6]_net_1\, B => \state[4]_net_1\, Y - => N_1030); - - GND_i : GND - port map(Y => \GND\); - - time_send_RNO : NOR2 - port map(A => N_1030, B => N_1026, Y => time_send_0_sqmuxa); - - \sel_data_0_RNI0MA8_1[0]\ : OR2A - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => \un13_time_write\); - - \count_send_time_RNO_3[24]\ : NOR2B - port map(A => \count_send_time[24]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e24_0_a2_0_0); - - \count_send_time_RNO_0[25]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[25]_net_1\, C => - count_send_time_e25_0_o3_N_7_i_0, Y => N_1178); - - \count_send_time_RNO_3[12]\ : NOR2B - port map(A => \count_send_time[12]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e12_0_a2_0_0); - - \count_send_time_RNIRPB7[6]\ : NOR2 - port map(A => \count_send_time[6]_net_1\, B => - \count_send_time[7]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_1[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \DMAWriteFSM_p.sel_data_3_i[0]\ : NOR3B - port map(A => N_1037, B => N_1027, C => ready_i_0(0), Y => - N_1016_i_0); - - \state_RNO_0[5]\ : OR2A - port map(A => \state[5]_net_1\, B => un1_time_send_ok, Y - => N_1042); - - \state_RNO_0[4]\ : OR2B - port map(A => \state[5]_net_1\, B => un1_time_send_ok, Y - => N_1044); - - \sel_data_RNITM0E[0]\ : MX2C - port map(A => N_1295, B => N_913, S => \sel_data[0]_net_1\, - Y => \data_address[30]\); - - \count_send_time_RNO_3[31]\ : OR3B - port map(A => N_1146, B => \count_send_time[27]_net_1\, C - => N_1161, Y => N_1162); - - \sel_data_RNII70E[0]\ : MX2C - port map(A => N_1307, B => N_911, S => \sel_data[0]_net_1\, - Y => \data_address[28]\); - - \count_send_time_RNO_1[25]\ : OR2B - port map(A => \count_send_time[25]_net_1\, B => N_1220, Y - => N_1177); - - \count_send_time_RNO_2[25]\ : OR3 - port map(A => N_1145_0, B => \count_send_time[25]_net_1\, C - => count_send_time_e25_0_o3_N_7_i_0, Y => N_1180); - - \count_send_time_RNINO24[24]\ : OR2 - port map(A => \count_send_time[24]_net_1\, B => - \count_send_time[25]_net_1\, Y => state_tr13_0_a2_17_1); - - \DMAWriteFSM_p.sel_data_3_i_o3[0]\ : OR2A - port map(A => ready_i_0(3), B => ready_i_0(1), Y => N_1027); - - \state_RNO_0[7]\ : OR3B - port map(A => \send_16_3_time_1_sqmuxa_i_o3_0\, B => - \state[7]_net_1\, C => N_1027, Y => N_1040); - - \count_send_time[7]\ : DFN1 - port map(D => \count_send_time_RNO[7]_net_1\, CLK => HCLK_c, - Q => \count_send_time[7]_net_1\); - - \count_send_time_RNO[25]\ : OR3C - port map(A => N_1178, B => N_1177, C => N_1180, Y => - count_send_time_e25); - - \count_send_time_RNO_1[9]\ : OR2B - port map(A => \count_send_time[9]_net_1\, B => N_1220, Y - => N_1267); - - \count_send_time_RNIVS36[16]\ : NOR3C - port map(A => \count_send_time[17]_net_1\, B => - \count_send_time[16]_net_1\, C => - \count_send_time[23]_net_1\, Y => - count_send_time_e25_0_o3_m6_0_a2_4); - - \count_send_time_RNO[31]\ : OR3C - port map(A => N_1191, B => N_1193, C => N_1194, Y => - count_send_time_e31); - - \state_ns_i_a2_0_RNO_2[5]\ : NOR2A - port map(A => \state[7]_net_1\, B => - \send_16_3_time[0]_net_1\, Y => - \state_ns_i_a2_0_a3_0[5]_net_1\); - - \count_send_time_RNIM7MP[6]\ : NOR3C - port map(A => N_1219, B => \count_send_time[5]_net_1\, C - => \count_send_time[6]_net_1\, Y => N_1223); - - \state_RNO[1]\ : NOR3C - port map(A => state_tr13_0_a2_14, B => N_1047_25, C => - state_tr13_0_a2_15, Y => \state_ns[6]\); - - \state_RNIKSS3[2]\ : OR3B - port map(A => \state[7]_net_1\, B => HRESETn_c, C => - \state[2]_net_1\, Y => N_1091); - - \count_send_time_RNO_3[22]\ : NOR2B - port map(A => \count_send_time[22]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e22_0_a2_0); - - \count_send_time_RNI6158[16]\ : OR3A - port map(A => \state_ns_i_a2_0_a4_0_19_9_0[5]\, B => - \count_send_time[17]_net_1\, C => - \count_send_time[16]_net_1\, Y => state_tr13_0_a2_9); - - \count_send_time_RNO_0[13]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[13]_net_1\, C => N_1057, Y => N_1086); - - time_write_RNI6IL9 : NOR2A - port map(A => \time_write\, B => un5_time_write, Y => - un7_time_write); - - \sel_data_0[0]\ : DFN1E1C0 - port map(D => N_1016_i_0, CLK => HCLK_c, CLR => HRESETn_c, - E => \state[7]_net_1\, Q => \sel_data_0[0]_net_1\); - - \count_send_time_RNO_0[14]\ : OAI1 - port map(A => \count_send_time_RNO_1[14]_net_1\, B => - \count_send_time[14]_net_1\, C => N_1091, Y => - count_send_time_e14_i_0); - - \sel_data_0_RNIGHOH_0[0]\ : OR2A - port map(A => \time_ren\, B => un5_time_write, Y => - time_ren(3)); - - \count_send_time_RNO[8]\ : OR3C - port map(A => N_1260, B => N_1262, C => N_1263, Y => - count_send_time_e8); - - \count_send_time[26]\ : DFN1 - port map(D => \count_send_time_RNO[26]_net_1\, CLK => - HCLK_c, Q => \count_send_time[26]_net_1\); - - \state_RNIQLS[5]\ : NOR3 - port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C - => \state[0]_net_1\, Y => N_816); - - \state_RNILNKV11[7]\ : AO1C - port map(A => N_1027, B => \send_16_3_time_1_sqmuxa_i_o3_0\, - C => \state[7]_net_1\, Y => N_1014); - - \count_send_time_RNIU2FB[29]\ : NOR3 - port map(A => \count_send_time[29]_net_1\, B => - \count_send_time[28]_net_1\, C => N_1047_5, Y => - state_tr13_0_a2_7); - - VCC_i : VCC - port map(Y => \VCC\); - - \count_send_time_RNI5L58[22]\ : NOR3A - port map(A => state_tr13_0_a2_6, B => - \count_send_time[22]_net_1\, C => - \count_send_time[21]_net_1\, Y => state_tr13_0_a2_10); - - \sel_data[1]\ : DFN1E1C0 - port map(D => N_1015, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[7]_net_1\, Q => \sel_data[1]_net_1\); - - \count_send_time_RNIV9C7[8]\ : OR2 - port map(A => \count_send_time[9]_net_1\, B => - \count_send_time[8]_net_1\, Y => N_1047_5); - - \all_time_write.0.time_already_send[0]\ : DFN1E1C0 - port map(D => un29_time_write, CLK => HCLK_c, CLR => - HRESETn_c, E => un17_status_full_ack, Q => - \time_already_send[0]\); - - \sel_data_0_RNI4K2Q[0]\ : MX2C - port map(A => N_1329, B => N_1291, S => - \sel_data_0[0]_net_1\, Y => \data_address[8]\); - - \count_send_time_RNIKS24[30]\ : NOR2 - port map(A => \count_send_time[23]_net_1\, B => - \count_send_time[30]_net_1\, Y => state_tr13_0_a2_6); - - \count_send_time_RNI29SA1[12]\ : OR3B - port map(A => \count_send_time[11]_net_1\, B => - \count_send_time[12]_net_1\, C => N_1159, Y => N_1057); - - \sel_data_0_RNIIPAU1_0[0]\ : OR2A - port map(A => \data_ren\, B => un5_time_write, Y => - data_ren(3)); - - \count_send_time[29]\ : DFN1 - port map(D => \count_send_time_RNO[29]_net_1\, CLK => - HCLK_c, Q => \count_send_time[29]_net_1\); - - \send_16_3_time[1]\ : DFN1E0C0 - port map(D => \send_16_3_time[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => N_1014, Q => - \send_16_3_time[1]_net_1\); - - \sel_data_RNI670E[0]\ : MX2C - port map(A => N_1304, B => N_908, S => \sel_data[0]_net_1\, - Y => \data_address[25]\); - - \state_RNO[4]\ : AO1B - port map(A => \state[6]_net_1\, B => N_1026, C => N_1044, Y - => \state_RNO_0[4]_net_1\); - - \count_send_time_RNO[19]\ : OR3C - port map(A => N_1103, B => N_1102, C => N_1104, Y => - count_send_time_e19); - - send_16_3_time_1_sqmuxa_i_o3_0 : NOR2 - port map(A => ready_i_0(2), B => ready_i_0(0), Y => - \send_16_3_time_1_sqmuxa_i_o3_0\); - - \all_time_write.3.time_already_send_RNO[3]\ : OR2 - port map(A => status_full_ack(3), B => un7_time_write, Y - => un2_status_full_ack); - - \state_ns_i_a2_0_RNO_3[5]\ : OR3C - port map(A => \state_ns_i_a2_0_a4_0_19_12[5]\, B => - \state_ns_i_a2_0_a4_0_19_11[5]\, C => - \state_ns_i_a2_0_a4_0_19_15[5]\, Y => - \state_ns_i_a2_0_a4_0_19_i[5]\); - - \sel_data_RNIA70E[0]\ : MX2C - port map(A => N_1305, B => N_909, S => \sel_data[0]_net_1\, - Y => \data_address[26]\); - - \count_send_time_RNO_1[30]\ : AOI1B - port map(A => \count_send_time[30]_net_1\, B => N_1220, C - => N_1125, Y => count_send_time_e30_0_0); - - \count_send_time[13]\ : DFN1 - port map(D => count_send_time_e13, CLK => HCLK_c, Q => - \count_send_time[13]_net_1\); - - \count_send_time[12]\ : DFN1 - port map(D => count_send_time_e12, CLK => HCLK_c, Q => - \count_send_time[12]_net_1\); - - \sel_data_0_RNI0MA8_0[0]\ : OR2A - port map(A => \sel_data_0[0]_net_1\, B => - \sel_data[1]_net_1\, Y => \un20_time_write\); - - \DMAWriteFSM_p.sel_data_3_i[1]\ : NOR3 - port map(A => N_1036, B => ready_i_0(0), C => ready_i_0(1), - Y => N_1015); - - \count_send_time_RNO_0[12]\ : AO1C - port map(A => N_1159, B => \count_send_time[11]_net_1\, C - => count_send_time_e12_0_a2_0_0, Y => N_1081); - - \count_send_time_RNO[24]\ : OR3C - port map(A => N_1173, B => N_1172, C => N_1175, Y => - count_send_time_e24); - - \count_send_time_RNO_2[3]\ : OR2B - port map(A => \count_send_time[3]_net_1\, B => N_1220, Y - => N_1246); - - \sel_data_0_RNIGIAC[0]\ : MX2C - port map(A => N_1318, B => N_1294, S => - \sel_data_0[0]_net_1\, Y => \data_address[11]\); - - \count_send_time_RNI23LE[0]\ : NOR3B - port map(A => \count_send_time[1]_net_1\, B => - \state_ns_i_a2_0_a4_0_25_2[5]\, C => - \count_send_time[0]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_4[5]\); - - time_fifo_ren_RNIGRD9 : NOR2A - port map(A => \time_select\, B => \time_fifo_ren\, Y => - \time_ren\); - - \count_send_time_RNO_0[30]\ : AO1B - port map(A => \count_send_time[27]_net_1\, B => N_1146, C - => count_send_time_e30_0_a2_0_0, Y => N_1126); - - \count_send_time_RNO_1[13]\ : OR2B - port map(A => \count_send_time[13]_net_1\, B => N_1220, Y - => N_1085); - - \count_send_time_RNO_2[19]\ : OR3A - port map(A => N_1063, B => N_1145, C => - \count_send_time[19]_net_1\, Y => N_1104); - - \count_send_time_RNO_1[14]\ : NOR3A - port map(A => \count_send_time[13]_net_1\, B => N_1057, C - => N_1145, Y => \count_send_time_RNO_1[14]_net_1\); - - \count_send_time_RNO_0[6]\ : NOR2 - port map(A => \count_send_time[6]_net_1\, B => - \count_send_time_RNO_1[6]_net_1\, Y => N_1253); - - \count_send_time_RNO_0[11]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[11]_net_1\, C => N_1159, Y => N_1167); - - \count_send_time_RNO_4[8]\ : OR2 - port map(A => \count_send_time[8]_net_1\, B => N_1145_0, Y - => count_send_time_e8_0_a2_1_0); - - \all_time_write.2.time_already_send[2]\ : DFN1E1C0 - port map(D => un15_time_write, CLK => HCLK_c, CLR => - HRESETn_c, E => un7_status_full_ack, Q => - \time_already_send[2]\); - - \count_send_time[4]\ : DFN1 - port map(D => \count_send_time_RNO[4]_net_1\, CLK => HCLK_c, - Q => \count_send_time[4]_net_1\); - - \state_RNO[6]\ : OA1C - port map(A => \send_16_3_time_1_sqmuxa_i_o3_0\, B => N_1027, - C => state_tr2_i_0, Y => \state_RNO[6]_net_1\); - - \sel_data_0_RNISJ1Q[0]\ : MX2C - port map(A => N_1327, B => N_1289, S => - \sel_data_0[0]_net_1\, Y => \data_address[6]\); - - \state_RNIU5T[2]\ : OR2A - port map(A => N_1030, B => \state[2]_net_1\, Y => - time_fifo_ren_1); - - \count_send_time[3]\ : DFN1 - port map(D => count_send_time_e3, CLK => HCLK_c, Q => - \count_send_time[3]_net_1\); - - \count_send_time_RNIKK24_0[20]\ : NOR2 - port map(A => \count_send_time[19]_net_1\, B => - \count_send_time[20]_net_1\, Y => state_tr13_0_a2_4); - - \sel_data_0_RNIOIAC[0]\ : MX2C - port map(A => N_1320, B => N_1282, S => - \sel_data_0[0]_net_1\, Y => \data_address[13]\); - - \count_send_time_RNO_0[29]\ : NOR2A - port map(A => \count_send_time[28]_net_1\, B => N_1156, Y - => N_1160); - - \count_send_time_RNO[1]\ : OR3C - port map(A => N_1239, B => N_1237, C => N_1236, Y => - count_send_time_e1); - - \count_send_time_RNO_1[3]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[3]_net_1\, C => N_1217, Y => N_1247); - - \count_send_time_RNIJPA7[2]\ : NOR2A - port map(A => \count_send_time[3]_net_1\, B => - \count_send_time[2]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_2[5]\); - - \count_send_time_RNO_4[20]\ : OR2 - port map(A => \count_send_time[20]_net_1\, B => N_1145_0, Y - => count_send_time_e20_0_a2_1_0); - - \count_send_time_RNO[20]\ : OR3C - port map(A => N_1107, B => N_1108, C => N_1109, Y => - count_send_time_e20); - - \state_RNO[7]\ : AO1C - port map(A => un1_data_send_ok, B => \state[0]_net_1\, C - => N_1040, Y => \state_RNO[7]_net_1\); - - \count_send_time[2]\ : DFN1 - port map(D => count_send_time_e2, CLK => HCLK_c, Q => - \count_send_time[2]_net_1\); - - \sel_data_RNI955D[0]\ : MX2C - port map(A => N_1311, B => N_1287, S => \sel_data[0]_net_1\, - Y => \data_address[18]\); - - \sel_data_0_RNI0MA8_2[0]\ : OR2 - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => un27_time_write); - - \count_send_time_RNIKK24[20]\ : NOR2B - port map(A => \count_send_time[19]_net_1\, B => - \count_send_time[20]_net_1\, Y => - count_send_time_e25_0_o3_m6_0_a2_2); - - \state_RNI7PI3[2]\ : OR2B - port map(A => \state[2]_net_1\, B => HRESETn_c, Y => N_1145); - - \count_send_time_RNO_2[10]\ : OR3A - port map(A => \count_send_time[9]_net_1\, B => N_1225, C - => count_send_time_e10_0_a2_1_0, Y => N_1273); - - \count_send_time_RNO_0[26]\ : OR3A - port map(A => \count_send_time[25]_net_1\, B => - count_send_time_e25_0_o3_N_7_i_0, C => N_1145, Y => - N_1163); - - \count_send_time_RNO[18]\ : AO1C - port map(A => \count_send_time[18]_net_1\, B => N_1137, C - => count_send_time_e18_0_0, Y => count_send_time_e18); - - \state_RNO_0[1]\ : NOR3B - port map(A => \state_0[2]_net_1\, B => state_tr13_0_a2_10, - C => state_tr13_0_a2_9, Y => state_tr13_0_a2_14); - - \state_RNO_2[1]\ : NOR3A - port map(A => state_tr13_0_a2_7, B => state_tr13_0_a2_17_0, - C => state_tr13_0_a2_17_1, Y => state_tr13_0_a2_12); - - \count_send_time_RNI3V2D2[27]\ : OR3B - port map(A => N_1146, B => \count_send_time[27]_net_1\, C - => N_1145, Y => N_1156); - - \sel_data_0_RNI714P[0]\ : MX2C - port map(A => N_1279, B => N_1297, S => - \sel_data_0[0]_net_1\, Y => \data_address[0]\); - - \count_send_time_RNO[6]\ : NOR3A - port map(A => N_1091, B => N_1253, C => N_1230, Y => - \count_send_time_RNO[6]_net_1\); - - time_write_RNI6IL9_1 : NOR2A - port map(A => \time_write\, B => \un20_time_write\, Y => - un22_time_write); - - \gen_select_address.1.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(1) => status_full_err(1), status_full(1) - => status_full(1), sel_data(1) => \sel_data[1]_net_1\, - sel_data_0(1) => \sel_data_0[1]_net_1\, - update_and_sel_5(3) => \update_and_sel_5[3]\, - update_and_sel_5(2) => \update_and_sel_5[2]\, - addr_data_f1(31) => addr_data_f1(31), addr_data_f1(30) - => addr_data_f1(30), addr_data_f1(29) => - addr_data_f1(29), addr_data_f1(28) => addr_data_f1(28), - addr_data_f1(27) => addr_data_f1(27), addr_data_f1(26) - => addr_data_f1(26), addr_data_f1(25) => - addr_data_f1(25), addr_data_f1(24) => addr_data_f1(24), - addr_data_f1(23) => addr_data_f1(23), addr_data_f1(22) - => addr_data_f1(22), addr_data_f1(21) => - addr_data_f1(21), addr_data_f1(20) => addr_data_f1(20), - addr_data_f1(19) => addr_data_f1(19), addr_data_f1(18) - => addr_data_f1(18), addr_data_f1(17) => - addr_data_f1(17), addr_data_f1(16) => addr_data_f1(16), - addr_data_f1(15) => addr_data_f1(15), addr_data_f1(14) - => addr_data_f1(14), addr_data_f1(13) => - addr_data_f1(13), addr_data_f1(12) => addr_data_f1(12), - addr_data_f1(11) => addr_data_f1(11), addr_data_f1(10) - => addr_data_f1(10), addr_data_f1(9) => addr_data_f1(9), - addr_data_f1(8) => addr_data_f1(8), addr_data_f1(7) => - addr_data_f1(7), addr_data_f1(6) => addr_data_f1(6), - addr_data_f1(5) => addr_data_f1(5), addr_data_f1(4) => - addr_data_f1(4), addr_data_f1(3) => addr_data_f1(3), - addr_data_f1(2) => addr_data_f1(2), addr_data_f1(1) => - addr_data_f1(1), addr_data_f1(0) => addr_data_f1(0), - status_full_ack(1) => status_full_ack(1), - addr_data_vector_94 => \addr_data_vector[126]\, - addr_data_vector_91 => \addr_data_vector[123]\, - addr_data_vector_89 => \addr_data_vector[121]\, - addr_data_vector_87 => \addr_data_vector[119]\, - addr_data_vector_86 => \addr_data_vector[118]\, - addr_data_vector_85 => \addr_data_vector[117]\, - addr_data_vector_84 => \addr_data_vector[116]\, - addr_data_vector_83 => \addr_data_vector[115]\, - addr_data_vector_67 => \addr_data_vector[99]\, - addr_data_vector_66 => \addr_data_vector[98]\, - addr_data_vector_65 => \addr_data_vector[97]\, - addr_data_vector_64 => \addr_data_vector[96]\, - addr_data_vector_75 => \addr_data_vector[107]\, - addr_data_vector_73 => \addr_data_vector[105]\, - addr_data_vector_81 => \addr_data_vector[113]\, - addr_data_vector_79 => \addr_data_vector[111]\, - addr_data_vector_77 => \addr_data_vector[109]\, - addr_data_vector_24 => \addr_data_vector[56]\, - addr_data_vector_31 => \addr_data_vector[63]\, - addr_data_vector_16 => \addr_data_vector[48]\, - addr_data_vector_14 => \addr_data_vector[46]\, - addr_data_vector_18 => \addr_data_vector[50]\, - addr_data_vector_26 => \addr_data_vector[58]\, - addr_data_vector_29 => \addr_data_vector[61]\, - addr_data_vector_28 => \addr_data_vector[60]\, - addr_data_vector_5 => \addr_data_vector[37]\, - addr_data_vector_4 => \addr_data_vector[36]\, - addr_data_vector_6 => \addr_data_vector[38]\, - addr_data_vector_12 => \addr_data_vector[44]\, - addr_data_vector_10 => \addr_data_vector[42]\, - addr_data_vector_7 => \addr_data_vector[39]\, - addr_data_vector_8 => \addr_data_vector[40]\, N_913 => - N_913, N_910 => N_910, N_908 => N_908, N_906 => N_906, - N_905 => N_905, N_904 => N_904, N_903 => N_903, N_902 => - N_902, N_1300 => N_1300, N_1299 => N_1299, N_1298 => - N_1298, N_1297 => N_1297, N_1294 => N_1294, N_1292 => - N_1292, N_1286 => N_1286, N_1284 => N_1284, N_1282 => - N_1282, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c); - - \count_send_time[24]\ : DFN1 - port map(D => count_send_time_e24, CLK => HCLK_c, Q => - \count_send_time[24]_net_1\); - - \count_send_time_RNO_1[12]\ : OR2B - port map(A => \count_send_time[12]_net_1\, B => N_1220, Y - => N_1080); - - \update_RNO[0]\ : OA1 - port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C - => un1_time_send_ok, Y => update_0_sqmuxa); - - \count_send_time_RNO_0[20]\ : AO1B - port map(A => \count_send_time[19]_net_1\, B => N_1063, C - => count_send_time_e20_0_a2_0, Y => N_1107); - - \sel_data_0_RNICIAC[0]\ : MX2C - port map(A => N_1317, B => N_1293, S => - \sel_data_0[0]_net_1\, Y => \data_address[10]\); - - \count_send_time_RNI1RIK1[15]\ : NOR3B - port map(A => N_1059, B => \count_send_time[15]_net_1\, C - => N_1145, Y => N_1077); - - \count_send_time_RNO[23]\ : OR3C - port map(A => N_1121, B => N_1122, C => N_1123, Y => - count_send_time_e23); - - \sel_data_RNI155D[0]\ : MX2C - port map(A => N_1309, B => N_1285, S => \sel_data[0]_net_1\, - Y => \data_address[16]\); - - \count_send_time_RNO_1[11]\ : OR2B - port map(A => \count_send_time[11]_net_1\, B => N_1220, Y - => N_1169); - - \count_send_time_RNO[11]\ : OR3C - port map(A => N_1167, B => N_1169, C => N_1170, Y => - count_send_time_e11); - - \count_send_time[27]\ : DFN1 - port map(D => \count_send_time_RNO[27]_net_1\, CLK => - HCLK_c, Q => \count_send_time[27]_net_1\); - - \count_send_time_RNO_1[20]\ : OR2B - port map(A => \count_send_time[20]_net_1\, B => N_1220, Y - => N_1108); - - \count_send_time_RNO_4[2]\ : AOI1B - port map(A => \count_send_time[1]_net_1\, B => - \count_send_time[0]_net_1\, C => - \count_send_time[2]_net_1\, Y => - count_send_time_e2_0_a2_0_0); - - \count_send_time_RNO_2[20]\ : OR3B - port map(A => N_1063, B => \count_send_time[19]_net_1\, C - => count_send_time_e20_0_a2_1_0, Y => N_1109); - - \count_send_time_RNO_0[17]\ : OA1C - port map(A => N_1061, B => N_1145, C => - \count_send_time[17]_net_1\, Y => N_1096); - - time_select_RNII30M1 : OA1C - port map(A => N_200, B => N_249, C => \time_select\, Y => - \data_ren\); - - \sel_data_0_RNIIPAU1[0]\ : OR2A - port map(A => \data_ren\, B => un27_time_write, Y => - data_ren(0)); - - time_write_RNI6IL9_0 : NOR2A - port map(A => \time_write\, B => \un13_time_write\, Y => - un15_time_write); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_2[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - time_fifo_ren : DFN1E0P0 - port map(D => time_fifo_ren_1_i, CLK => HCLK_c, PRE => - HRESETn_c, E => \state[0]_net_1\, Q => \time_fifo_ren\); - - \count_send_time_RNIK6CT[0]\ : NOR3C - port map(A => \state_ns_i_a2_0_a4_0_25_1[5]\, B => - \state_ns_i_a2_0_a4_0_25_0[5]\, C => - \state_ns_i_a2_0_a4_0_25_4[5]\, Y => N_1047_25); - - time_write_RNO_0 : OR2 - port map(A => \state[1]_net_1\, B => \state[3]_net_1\, Y - => un1_state_13_0_a4_0_0); - - \count_send_time_RNO_1[1]\ : OR3B - port map(A => \count_send_time[1]_net_1\, B => - \state[2]_net_1\, C => \count_send_time[0]_net_1\, Y => - N_1237); - - time_select_0 : DFN1E1C0 - port map(D => time_fifo_ren_1, CLK => HCLK_c, CLR => - HRESETn_c, E => N_816, Q => \time_select_0\); - - \sel_data_RNI555D[0]\ : MX2C - port map(A => N_1310, B => N_1286, S => \sel_data[0]_net_1\, - Y => \data_address[17]\); - - \count_send_time_RNIJ9211[7]\ : OR3C - port map(A => N_1223, B => \count_send_time[7]_net_1\, C - => \count_send_time[8]_net_1\, Y => N_1225); - - \count_send_time_RNO_0[18]\ : AOI1B - port map(A => \count_send_time[18]_net_1\, B => N_1220, C - => N_1099, Y => count_send_time_e18_0_0); - - lpp_dma_send_1word_1 : lpp_dma_send_1word - port map(Lock => Lock, Request => Request, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, un1_time_send_ok => - un1_time_send_ok, time_select => \time_select\, Store => - Store, N_1012 => N_1012, Ready => Ready, Fault => Fault, - time_send => \time_send\, Grant => Grant); - - \all_time_write.0.time_already_send_RNO[0]\ : OR2 - port map(A => status_full_ack(0), B => un29_time_write, Y - => un17_status_full_ack); - - \count_send_time_RNIMBLO1[17]\ : NOR3B - port map(A => N_1061, B => \count_send_time[17]_net_1\, C - => N_1145, Y => N_1137); - - \count_send_time_RNO_2[31]\ : OR3 - port map(A => N_1161, B => \count_send_time[31]_net_1\, C - => N_1156, Y => N_1194); - - \count_send_time[11]\ : DFN1 - port map(D => count_send_time_e11, CLK => HCLK_c, Q => - \count_send_time[11]_net_1\); - - \sel_data_RNIQ60E[0]\ : MX2C - port map(A => N_1315, B => N_905, S => \sel_data[0]_net_1\, - Y => \data_address[22]\); - - \count_send_time[1]\ : DFN1 - port map(D => count_send_time_e1, CLK => HCLK_c, Q => - \count_send_time[1]_net_1\); - - \count_send_time[9]\ : DFN1 - port map(D => count_send_time_e9, CLK => HCLK_c, Q => - \count_send_time[9]_net_1\); - - \sel_data_0_RNI042Q[0]\ : MX2C - port map(A => N_1328, B => N_1290, S => - \sel_data_0[0]_net_1\, Y => \data_address[7]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \count_send_time_RNO_1[8]\ : OR2B - port map(A => \count_send_time[8]_net_1\, B => N_1220, Y - => N_1262); - - \sel_data_RNIE70E[0]\ : MX2C - port map(A => N_1306, B => N_910, S => \sel_data[0]_net_1\, - Y => \data_address[27]\); - - \sel_data_RNIM60E[0]\ : MX2C - port map(A => N_1314, B => N_904, S => \sel_data[0]_net_1\, - Y => \data_address[21]\); - - \count_send_time[20]\ : DFN1 - port map(D => count_send_time_e20, CLK => HCLK_c, Q => - \count_send_time[20]_net_1\); - - \state_ns_i_a2_0_RNO_5[5]\ : NOR2B - port map(A => state_tr13_0_a2_7, B => state_tr13_0_a2_8, Y - => \state_ns_i_a2_0_a4_0_19_12[5]\); - - \count_send_time[30]\ : DFN1 - port map(D => count_send_time_e30, CLK => HCLK_c, Q => - \count_send_time[30]_net_1\); - - \count_send_time[15]\ : DFN1 - port map(D => \count_send_time_RNO[15]_net_1\, CLK => - HCLK_c, Q => \count_send_time[15]_net_1\); - - \count_send_time_RNO[16]\ : OA1C - port map(A => N_1061, B => N_1145_0, C => - count_send_time_e16_i_0, Y => - \count_send_time_RNO[16]_net_1\); - - \DMAWriteFSM_p.sel_data_3_i_a4[1]\ : NOR2A - port map(A => ready_i_0(3), B => ready_i_0(2), Y => N_1036); - - \all_time_write.2.time_already_send_RNISCP08[2]\ : MX2 - port map(A => \time_already_send[3]\, B => - \time_already_send[2]\, S => ready_i_0(2), Y => N_1024); - - \state_RNO[5]\ : AO1C - port map(A => N_1026, B => \state[6]_net_1\, C => N_1042, Y - => \state_RNO[5]_net_1\); - - \count_send_time_RNITLAI[4]\ : NOR3B - port map(A => \count_send_time[3]_net_1\, B => - \count_send_time[4]_net_1\, C => N_1217, Y => N_1219); - - \count_send_time_RNI7558[13]\ : NOR3A - port map(A => state_tr13_0_a2_4, B => - \count_send_time[18]_net_1\, C => - \count_send_time[13]_net_1\, Y => state_tr13_0_a2_9_0); - - \count_send_time_RNO_1[18]\ : AO1B - port map(A => \count_send_time[17]_net_1\, B => N_1061, C - => count_send_time_e18_0_a2_0_0, Y => N_1099); - - \count_send_time_RNIHG24[14]\ : NOR2 - port map(A => \count_send_time[14]_net_1\, B => - \count_send_time[15]_net_1\, Y => - \state_ns_i_a2_0_a4_0_19_9_0[5]\); - - \sel_data_RNI1N0E[0]\ : MX2C - port map(A => N_1296, B => N_914, S => \sel_data[0]_net_1\, - Y => \data_address[31]\); - - \count_send_time[18]\ : DFN1 - port map(D => count_send_time_e18, CLK => HCLK_c, Q => - \count_send_time[18]_net_1\); - - \count_send_time_RNO_0[15]\ : OA1C - port map(A => N_1059, B => N_1145, C => - \count_send_time[15]_net_1\, Y => N_1092); - - \count_send_time_RNO[12]\ : OR3C - port map(A => N_1081, B => N_1080, C => N_1082, Y => - count_send_time_e12); - - \state[2]\ : DFN1C0 - port map(D => \state_ns_i_a2_0[5]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \state[2]_net_1\); - - \count_send_time_RNO_5[30]\ : OR3 - port map(A => N_1075, B => \count_send_time[30]_net_1\, C - => N_1145_0, Y => count_send_time_e30_0_a2_2_1); - - \send_16_3_time[0]\ : DFN1E0P0 - port map(D => \send_16_3_time[2]_net_1\, CLK => HCLK_c, PRE - => HRESETn_c, E => N_1014, Q => - \send_16_3_time[0]_net_1\); - - \count_send_time_RNO_3[8]\ : NOR2B - port map(A => \count_send_time[8]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e8_0_a2_0); - - \count_send_time_RNO_0[8]\ : AO1B - port map(A => \count_send_time[7]_net_1\, B => N_1223, C - => count_send_time_e8_0_a2_0, Y => N_1260); - - \count_send_time_RNO[29]\ : XA1 - port map(A => N_1160, B => \count_send_time[29]_net_1\, C - => N_1091, Y => \count_send_time_RNO[29]_net_1\); - - \count_send_time[6]\ : DFN1 - port map(D => \count_send_time_RNO[6]_net_1\, CLK => HCLK_c, - Q => \count_send_time[6]_net_1\); - - \send_16_3_time[2]\ : DFN1E0C0 - port map(D => \send_16_3_time[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => N_1014, Q => - \send_16_3_time[2]_net_1\); - - \state_0[2]\ : DFN1C0 - port map(D => \state_ns_i_a2_0[5]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \state_0[2]_net_1\); - - \count_send_time_RNIQ858[31]\ : NOR3A - port map(A => state_tr13_0_a2_2, B => - \count_send_time[10]_net_1\, C => - \count_send_time[31]_net_1\, Y => state_tr13_0_a2_8); - - \count_send_time_RNI089V1[22]\ : OR3B - port map(A => \count_send_time[21]_net_1\, B => - \count_send_time[22]_net_1\, C => N_1066, Y => N_1069); - - \state[1]\ : DFN1C0 - port map(D => \state_ns[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - \count_send_time_RNO_4[10]\ : OR2 - port map(A => \count_send_time[10]_net_1\, B => N_1145_0, Y - => count_send_time_e10_0_a2_1_0); - - \count_send_time_RNIRO24[26]\ : OR2 - port map(A => \count_send_time[26]_net_1\, B => - \count_send_time[27]_net_1\, Y => state_tr13_0_a2_17_0); - - \count_send_time_RNO[17]\ : NOR3A - port map(A => N_1091, B => N_1096, C => N_1137, Y => - \count_send_time_RNO[17]_net_1\); - - time_send_RNO_0 : NOR2 - port map(A => \state[2]_net_1\, B => \state[0]_net_1\, Y - => N_815); - - \all_time_write.1.time_already_send_RNI7H7MG[1]\ : MX2 - port map(A => N_1024, B => \time_already_send[1]\, S => - ready_i_0(1), Y => N_1025); - - \sel_data_RNIT45D[0]\ : MX2C - port map(A => N_1322, B => N_1284, S => \sel_data[0]_net_1\, - Y => \data_address[15]\); - - \count_send_time_RNIEPE72[26]\ : NOR3B - port map(A => \count_send_time[25]_net_1\, B => - \count_send_time[26]_net_1\, C => - count_send_time_e25_0_o3_N_7_i_0, Y => N_1146); - - \state_ns_i_a2_0_RNO_1[5]\ : AOI1B - port map(A => \state_ns_i_a2_0_a4_0_19_i[5]\, B => - \state_0[2]_net_1\, C => N_1050, Y => - \state_ns_i_a2_0_0[5]\); - - \state_RNO_0[6]\ : OR2B - port map(A => \send_16_3_time[0]_net_1\, B => - \state[7]_net_1\, Y => state_tr2_i_0); - - \state_ns_i_a2_0[5]\ : NAND2 - port map(A => N_1049, B => \state_ns_i_a2_0_1[5]\, Y => - \state_ns_i_a2_0[5]_net_1\); - - \count_send_time_RNO_2[2]\ : OR2B - port map(A => \count_send_time[2]_net_1\, B => N_1220, Y - => N_1241); - - \count_send_time_RNO_4[24]\ : OR2 - port map(A => \count_send_time[24]_net_1\, B => N_1145_0, Y - => count_send_time_e24_0_a2_1_0); - - \all_time_write.1.time_already_send_RNO[1]\ : OR2 - port map(A => status_full_ack(1), B => un22_time_write, Y - => un12_status_full_ack); - - \state_RNO[3]\ : AO1A - port map(A => N_1026, B => \state[4]_net_1\, C => N_1033, Y - => \state_RNO_2[3]\); - - \state_RNO[0]\ : AO1 - port map(A => \state[0]_net_1\, B => un1_data_send_ok, C - => \state[1]_net_1\, Y => \state_RNO_1[0]\); - - \state_ns_i_a2_0_RNO[5]\ : AND2 - port map(A => N_1048, B => \state_ns_i_a2_0_0[5]\, Y => - \state_ns_i_a2_0_1[5]\); - - \sel_data_0_RNIKJ0Q[0]\ : MX2C - port map(A => N_1325, B => N_1301, S => - \sel_data_0[0]_net_1\, Y => \data_address[4]\); - - \count_send_time_RNO_2[13]\ : OR3 - port map(A => N_1145, B => \count_send_time[13]_net_1\, C - => N_1057, Y => N_1087); - - \state_RNO_1[1]\ : NOR3C - port map(A => state_tr13_0_a2_9_0, B => state_tr13_0_a2_8, - C => state_tr13_0_a2_12, Y => state_tr13_0_a2_15); - - \state_ns_i_a2_0_RNO_4[5]\ : OR2B - port map(A => \state[3]_net_1\, B => un1_time_send_ok, Y - => N_1050); - - \count_send_time_RNO_0[4]\ : OR3A - port map(A => \count_send_time[3]_net_1\, B => N_1217, C - => N_1145, Y => N_1227); - - \count_send_time_RNIL0C32[15]\ : OR3C - port map(A => N_1059, B => \count_send_time[15]_net_1\, C - => count_send_time_e25_0_o3_m6_0_a2_7, Y => - count_send_time_e25_0_o3_N_7_i_0); - - \sel_data_RNI270E[0]\ : MX2C - port map(A => N_1303, B => N_907, S => \sel_data[0]_net_1\, - Y => \data_address[24]\); - - \count_send_time_RNO_1[31]\ : OR2B - port map(A => \count_send_time[31]_net_1\, B => N_1220, Y - => N_1193); - - time_fifo_ren_RNIGHOH : OR2A - port map(A => \time_ren\, B => \un20_time_write\, Y => - time_ren(1)); - - \count_send_time_RNO_0[5]\ : OR2A - port map(A => N_1219, B => N_1145, Y => N_1228); - - \count_send_time_RNO_3[30]\ : NOR2B - port map(A => \count_send_time[30]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e30_0_a2_0_0); - - \count_send_time_RNO_0[23]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[23]_net_1\, C => N_1069, Y => N_1121); - - \count_send_time_RNO_0[24]\ : AO1C - port map(A => N_1069, B => \count_send_time[23]_net_1\, C - => count_send_time_e24_0_a2_0_0, Y => N_1173); - - time_send : DFN1E1C0 - port map(D => time_send_0_sqmuxa, CLK => HCLK_c, CLR => - HRESETn_c, E => N_815, Q => \time_send\); - - \count_send_time_RNO_0[31]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[31]_net_1\, C => N_1162, Y => N_1191); - - time_select_RNIIPAU1 : OR2A - port map(A => \data_ren\, B => \un13_time_write\, Y => - data_ren(2)); - - \count_send_time_RNO_3[10]\ : NOR2B - port map(A => \count_send_time[10]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e10_0_a2_0); - - \count_send_time_RNO_0[1]\ : OR3A - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => N_1145_0, Y => N_1239); - - \update[0]\ : DFN1E0C0 - port map(D => update_0_sqmuxa, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_12, Q => \update[0]_net_1\); - - \count_send_time_RNO_1[23]\ : OR2B - port map(A => \count_send_time[23]_net_1\, B => N_1220, Y - => N_1122); - - \count_send_time_RNO[28]\ : XA1A - port map(A => N_1156, B => \count_send_time[28]_net_1\, C - => N_1091, Y => \count_send_time_RNO[28]_net_1\); - - \count_send_time_RNO_2[23]\ : OR3 - port map(A => N_1145_0, B => \count_send_time[23]_net_1\, C - => N_1069, Y => N_1123); - - \count_send_time_RNO_1[24]\ : OR2B - port map(A => \count_send_time[24]_net_1\, B => N_1220, Y - => N_1172); - - \count_send_time_RNIBG24[12]\ : NOR2 - port map(A => \count_send_time[11]_net_1\, B => - \count_send_time[12]_net_1\, Y => state_tr13_0_a2_2); - - \count_send_time_RNO_2[24]\ : OR3A - port map(A => \count_send_time[23]_net_1\, B => N_1069, C - => count_send_time_e24_0_a2_1_0, Y => N_1175); - - \count_send_time[23]\ : DFN1 - port map(D => count_send_time_e23, CLK => HCLK_c, Q => - \count_send_time[23]_net_1\); - - \count_send_time[22]\ : DFN1 - port map(D => count_send_time_e22, CLK => HCLK_c, Q => - \count_send_time[22]_net_1\); - - \state_ns_i_a2_0_RNO_6[5]\ : NOR3 - port map(A => state_tr13_0_a2_17_0, B => - state_tr13_0_a2_17_1, C => state_tr13_0_a2_9, Y => - \state_ns_i_a2_0_a4_0_19_11[5]\); - - \sel_data_RNII60E[0]\ : MX2C - port map(A => N_1313, B => N_903, S => \sel_data[0]_net_1\, - Y => \data_address[20]\); - - \update_RNIOECD_2[0]\ : OR2A - port map(A => \update[0]_net_1\, B => un27_time_write, Y - => \update_and_sel_7[0]\); - - \count_send_time_RNO_4[22]\ : OR2 - port map(A => \count_send_time[22]_net_1\, B => N_1145_0, Y - => count_send_time_e22_0_a2_1_0); - - \count_send_time[16]\ : DFN1 - port map(D => \count_send_time_RNO[16]_net_1\, CLK => - HCLK_c, Q => \count_send_time[16]_net_1\); - - \count_send_time_RNIHPUE1[14]\ : NOR3B - port map(A => \count_send_time[13]_net_1\, B => - \count_send_time[14]_net_1\, C => N_1057, Y => N_1059); - - \count_send_time_RNO[30]\ : OR3C - port map(A => N_1126, B => count_send_time_e30_0_0, C => - N_1128, Y => count_send_time_e30); - - \count_send_time_RNO[21]\ : OR3C - port map(A => N_1112, B => N_1113, C => N_1114, Y => - count_send_time_e21); - - \sel_data_0_RNIGHOH[0]\ : OR2A - port map(A => \time_ren\, B => un27_time_write, Y => - time_ren(0)); - - \count_send_time_RNO_2[12]\ : OR3A - port map(A => \count_send_time[11]_net_1\, B => N_1159, C - => count_send_time_e12_0_a2_1_0, Y => N_1082); - - \all_time_write.2.time_already_send_RNO[2]\ : OR2 - port map(A => status_full_ack(2), B => un15_time_write, Y - => un7_status_full_ack); - - \all_time_write.1.time_already_send[1]\ : DFN1E1C0 - port map(D => un22_time_write, CLK => HCLK_c, CLR => - HRESETn_c, E => un12_status_full_ack, Q => - \time_already_send[1]\); - - \gen_select_address.3.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(3) => status_full_err(3), status_full(3) - => status_full(3), sel_data(1) => \sel_data[1]_net_1\, - sel_data_0(1) => \sel_data_0[1]_net_1\, - update_and_sel_1(7) => \update_and_sel_1[7]\, - update_and_sel_1(6) => \update_and_sel_1[6]\, - addr_data_f3(31) => addr_data_f3(31), addr_data_f3(30) - => addr_data_f3(30), addr_data_f3(29) => - addr_data_f3(29), addr_data_f3(28) => addr_data_f3(28), - addr_data_f3(27) => addr_data_f3(27), addr_data_f3(26) - => addr_data_f3(26), addr_data_f3(25) => - addr_data_f3(25), addr_data_f3(24) => addr_data_f3(24), - addr_data_f3(23) => addr_data_f3(23), addr_data_f3(22) - => addr_data_f3(22), addr_data_f3(21) => - addr_data_f3(21), addr_data_f3(20) => addr_data_f3(20), - addr_data_f3(19) => addr_data_f3(19), addr_data_f3(18) - => addr_data_f3(18), addr_data_f3(17) => - addr_data_f3(17), addr_data_f3(16) => addr_data_f3(16), - addr_data_f3(15) => addr_data_f3(15), addr_data_f3(14) - => addr_data_f3(14), addr_data_f3(13) => - addr_data_f3(13), addr_data_f3(12) => addr_data_f3(12), - addr_data_f3(11) => addr_data_f3(11), addr_data_f3(10) - => addr_data_f3(10), addr_data_f3(9) => addr_data_f3(9), - addr_data_f3(8) => addr_data_f3(8), addr_data_f3(7) => - addr_data_f3(7), addr_data_f3(6) => addr_data_f3(6), - addr_data_f3(5) => addr_data_f3(5), addr_data_f3(4) => - addr_data_f3(4), addr_data_f3(3) => addr_data_f3(3), - addr_data_f3(2) => addr_data_f3(2), addr_data_f3(1) => - addr_data_f3(1), addr_data_f3(0) => addr_data_f3(0), - status_full_ack(3) => status_full_ack(3), - addr_data_vector_61 => \addr_data_vector[97]\, - addr_data_vector_60 => \addr_data_vector[96]\, - addr_data_vector_27 => \addr_data_vector[63]\, - addr_data_vector_25 => \addr_data_vector[61]\, - addr_data_vector_24 => \addr_data_vector[60]\, - addr_data_vector_22 => \addr_data_vector[58]\, - addr_data_vector_20 => \addr_data_vector[56]\, - addr_data_vector_0 => \addr_data_vector[36]\, - addr_data_vector_6 => \addr_data_vector[42]\, - addr_data_vector_4 => \addr_data_vector[40]\, - addr_data_vector_3 => \addr_data_vector[39]\, - addr_data_vector_2 => \addr_data_vector[38]\, - addr_data_vector_1 => \addr_data_vector[37]\, - addr_data_vector_14 => \addr_data_vector[50]\, - addr_data_vector_12 => \addr_data_vector[48]\, - addr_data_vector_10 => \addr_data_vector[46]\, - addr_data_vector_8 => \addr_data_vector[44]\, - addr_data_vector_63 => \addr_data_vector[99]\, - addr_data_vector_90 => \addr_data_vector[126]\, - addr_data_vector_87 => \addr_data_vector[123]\, - addr_data_vector_85 => \addr_data_vector[121]\, - addr_data_vector_62 => \addr_data_vector[98]\, - addr_data_vector_69 => \addr_data_vector[105]\, - addr_data_vector_73 => \addr_data_vector[109]\, - addr_data_vector_71 => \addr_data_vector[107]\, - addr_data_vector_77 => \addr_data_vector[113]\, - addr_data_vector_79 => \addr_data_vector[115]\, - addr_data_vector_82 => \addr_data_vector[118]\, - addr_data_vector_83 => \addr_data_vector[119]\, - addr_data_vector_75 => \addr_data_vector[111]\, - addr_data_vector_80 => \addr_data_vector[116]\, - addr_data_vector_81 => \addr_data_vector[117]\, N_914 => - N_914, N_912 => N_912, N_911 => N_911, N_909 => N_909, - N_907 => N_907, N_1301 => N_1301, N_1293 => N_1293, - N_1291 => N_1291, N_1290 => N_1290, N_1289 => N_1289, - N_1288 => N_1288, N_1287 => N_1287, N_1285 => N_1285, - N_1283 => N_1283, N_1281 => N_1281, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \state_ns_i_a2_0_RNO_7[5]\ : NOR3C - port map(A => state_tr13_0_a2_10, B => state_tr13_0_a2_9_0, - C => N_1047_25, Y => \state_ns_i_a2_0_a4_0_19_15[5]\); - - \count_send_time_RNO_2[11]\ : OR3 - port map(A => N_1145_0, B => \count_send_time[11]_net_1\, C - => N_1159, Y => N_1170); - - \count_send_time_RNO[5]\ : XA1A - port map(A => N_1228, B => \count_send_time[5]_net_1\, C - => N_1091, Y => \count_send_time_RNO[5]_net_1\); - - \count_send_time[19]\ : DFN1 - port map(D => count_send_time_e19, CLK => HCLK_c, Q => - \count_send_time[19]_net_1\); - - \count_send_time_RNO_3[20]\ : NOR2B - port map(A => \count_send_time[20]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e20_0_a2_0); - - \sel_data_0_RNICI8P[0]\ : MX2C - port map(A => N_1316, B => N_1292, S => - \sel_data_0[0]_net_1\, Y => \data_address[9]\); - - \count_send_time_RNO_0[22]\ : AO1C - port map(A => N_1066, B => \count_send_time[21]_net_1\, C - => count_send_time_e22_0_a2_0, Y => N_1117); - - \count_send_time_RNO[15]\ : NOR3A - port map(A => N_1091, B => N_1092, C => N_1077, Y => - \count_send_time_RNO[15]_net_1\); - - \count_send_time_RNO_0[21]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[21]_net_1\, C => N_1066, Y => N_1112); - - \count_send_time_RNO_1[22]\ : OR2B - port map(A => \count_send_time[22]_net_1\, B => N_1220, Y - => N_1118); - - \update_RNIPECD_1[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un13_time_write\, Y - => \update_and_sel_3[5]\); - - \count_send_time_RNO_2[22]\ : OR3A - port map(A => \count_send_time[21]_net_1\, B => N_1066, C - => count_send_time_e22_0_a2_1_0, Y => N_1119); - - \state_0_RNIAU89[2]\ : OR2B - port map(A => \state_0[2]_net_1\, B => HRESETn_c, Y => - N_1145_0); - - \state_RNI8UM1[0]\ : AO1B - port map(A => \state[0]_net_1\, B => un1_data_send_ok, C - => N_1030, Y => un1_state_12); - - DMA2AHB_1 : DMA2AHB - port map(hburst_c(2) => hburst_c(2), hburst_c(1) => - hburst_c(1), hburst_c(0) => hburst_c(0), htrans_c(1) => - htrans_c(1), htrans_c(0) => htrans_c(0), un7_dmain(66) - => \un7_dmain[66]\, hsize_c(1) => hsize_c(1), hsize_c(0) - => hsize_c(0), AHB_Master_In_c_5 => AHB_Master_In_c_5, - AHB_Master_In_c_4 => AHB_Master_In_c_4, AHB_Master_In_c_0 - => AHB_Master_In_c_0, AHB_Master_In_c_3 => - AHB_Master_In_c_3, haddr_c(31) => haddr_c(31), - haddr_c(30) => haddr_c(30), haddr_c(29) => haddr_c(29), - haddr_c(28) => haddr_c(28), haddr_c(27) => haddr_c(27), - haddr_c(26) => haddr_c(26), haddr_c(25) => haddr_c(25), - haddr_c(24) => haddr_c(24), haddr_c(23) => haddr_c(23), - haddr_c(22) => haddr_c(22), haddr_c(21) => haddr_c(21), - haddr_c(20) => haddr_c(20), haddr_c(19) => haddr_c(19), - haddr_c(18) => haddr_c(18), haddr_c(17) => haddr_c(17), - haddr_c(16) => haddr_c(16), haddr_c(15) => haddr_c(15), - haddr_c(14) => haddr_c(14), haddr_c(13) => haddr_c(13), - haddr_c(12) => haddr_c(12), haddr_c(11) => haddr_c(11), - haddr_c(10) => haddr_c(10), haddr_c(9) => haddr_c(9), - haddr_c(8) => haddr_c(8), haddr_c(7) => haddr_c(7), - haddr_c(6) => haddr_c(6), haddr_c(5) => haddr_c(5), - haddr_c(4) => haddr_c(4), haddr_c(3) => haddr_c(3), - haddr_c(2) => haddr_c(2), haddr_c(1) => haddr_c(1), - haddr_c(0) => haddr_c(0), hwrite_c => hwrite_c, Ready => - Ready, N_1012 => N_1012, Grant => Grant, - IdlePhase_RNI03G71 => IdlePhase_RNI03G71, OKAY => OKAY, - Fault => Fault, N_1011 => N_1011, N_1013 => N_1013, N_43 - => N_43, time_select_0 => \time_select_0\, N_960 => - N_960, N_959 => N_959, N_958 => N_958, N_957 => N_957, - N_964 => N_964, N_963 => N_963, N_962 => N_962, N_961 => - N_961, N_955 => N_955, N_954 => N_954, N_953 => N_953, - N_952 => N_952, N_951 => N_951, N_950 => N_950, N_949 => - N_949, N_948 => N_948, N_947 => N_947, N_956 => N_956, - N_965 => N_965, N_966 => N_966, N_967 => N_967, N_968 => - N_968, N_969 => N_969, N_970 => N_970, N_971 => N_971, - N_972 => N_972, N_973 => N_973, N_974 => N_974, N_975 => - N_975, N_976 => N_976, N_977 => N_977, HRESETn_c => - HRESETn_c, N_978 => N_978, HCLK_c => HCLK_c); - - \count_send_time_RNO_1[21]\ : OR2B - port map(A => \count_send_time[21]_net_1\, B => N_1220, Y - => N_1113); - - \count_send_time_RNO_0[19]\ : OR3B - port map(A => \state[2]_net_1\, B => - \count_send_time[19]_net_1\, C => N_1063, Y => N_1103); - - \count_send_time_RNIVO24[29]\ : OR2B - port map(A => \count_send_time[29]_net_1\, B => - \count_send_time[28]_net_1\, Y => N_1075); - - \count_send_time_RNO_2[21]\ : OR3 - port map(A => N_1145, B => \count_send_time[21]_net_1\, C - => N_1066, Y => N_1114); - - \count_send_time_RNO[9]\ : OR3C - port map(A => N_1265, B => N_1267, C => N_1268, Y => - count_send_time_e9); - - \state_ns_i_a2_0_RNO_0[5]\ : AO1C - port map(A => N_1027, B => \send_16_3_time_1_sqmuxa_i_o3_0\, - C => \state_ns_i_a2_0_a3_0[5]_net_1\, Y => N_1048); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_arbiter is - - port( wdata : out std_logic_vector(31 downto 0); - data_wen : out std_logic_vector(3 downto 0); - valid_ack : out std_logic_vector(3 downto 0); - time_wen : out std_logic_vector(3 downto 0); - data_f3_out : in std_logic_vector(159 downto 64); - data_f2_out : in std_logic_vector(159 downto 64); - data_f1_out : in std_logic_vector(159 downto 64); - data_f0_out : in std_logic_vector(159 downto 64); - valid_out_i : in std_logic_vector(1 to 1); - ready_i_0 : in std_logic_vector(3 downto 0); - valid_out_3 : in std_logic; - valid_out_2 : in std_logic; - valid_out_0 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_waveform_fifo_arbiter; - -architecture DEF_ARCH of lpp_waveform_fifo_arbiter is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \data_valid_and_ready_3[0]_net_1\, - \data_valid_and_ready_2[0]_net_1\, - \data_valid_and_ready_1[0]_net_1\, - \data_valid_and_ready_0[0]_net_1\, - \data_valid_and_ready_3[2]_net_1\, - \data_valid_and_ready_2[2]_net_1\, - \data_valid_and_ready_1[2]_net_1\, - \data_valid_and_ready_0[2]_net_1\, N_863_2, - \state[4]_net_1\, \data_temp_5_i_a2_0_0[32]_net_1\, - N_1580_0, N_863_1, N_863_0, N_1580_3, - \data_valid_and_ready[1]_net_1\, N_1580_2, N_1580_1, - \state_0[4]\, N_860_i, N_860, \time_wen_3_i[0]\, - \time_wen_3[0]\, N_859_i, N_859, N_857_i, N_857, - state_0_sqmuxa_i_i, state_0_sqmuxa_i, - \data_temp_5_i_0[32]\, N_912_i, N_769, N_864, - \data_temp_5_i_0[33]\, N_770, N_867, - \data_temp_5_i_0[34]\, N_848, N_870, - \data_temp_5_i_0[35]\, N_849, N_873, - \data_temp_5_i_0[36]\, N_850, N_1650, - \data_temp_5_i_0[37]\, N_851, N_1653, - \data_temp_5_i_0[38]\, N_852, N_1656, - \data_temp_5_i_0[39]\, N_853, N_1659, - \data_temp_5_i_0[40]\, N_854, N_1662, - \data_temp_5_i_0[41]\, N_841, N_1665, - \data_temp_5_i_0[42]\, N_842, N_1668, - \data_temp_5_i_0[43]\, N_843, N_897, - \data_temp_5_i_0[92]\, N_794, N_900, - \data_temp_5_i_0[93]\, N_795, N_902, - \data_temp_5_i_0[124]\, N_1681, N_904, - \data_temp_5_i_0[125]\, N_1682, N_906, - \data_temp_5_i_0[91]\, N_793, N_908, - \data_temp_5_i_0[123]\, N_1680, N_910, - \time_wen_3_i_a2_0[3]_net_1\, - \data_valid_and_ready[3]_net_1\, \state_ns_i_i_a2_1[0]\, - \state[2]_net_1\, \state[1]_net_1\, \state[3]_net_1\, - N_239, N_898, N_237, N_1669, N_235, N_1666, N_233, N_1663, - N_231, N_1660, N_229, N_1657, N_227, N_1654, N_225, - N_1651, N_223, N_874, N_221, N_871, N_219, N_868, N_215, - N_865, N_251, N_913, N_249, N_247, N_914, N_245, N_915, - N_243, N_241, N_863, N_861, N_1306, \state[0]_net_1\, - N_917, N_858, \data_temp[64]_net_1\, N_1685, - \data_temp[65]_net_1\, N_1686, \data_temp[66]_net_1\, - N_1687, \data_temp[67]_net_1\, N_1688, - \data_temp[68]_net_1\, N_1689, \data_temp[69]_net_1\, - N_762, \data_temp[70]_net_1\, N_763, - \data_temp[71]_net_1\, N_764, \data_temp[72]_net_1\, - N_765, \data_temp[73]_net_1\, N_766, - \data_temp[74]_net_1\, N_767, \data_temp[75]_net_1\, - N_768, N_1731, N_1718, N_1693, N_1694, N_1730, N_1692, - \data_temp[123]_net_1\, \data_temp[125]_net_1\, - \data_temp[124]_net_1\, N_916, N_1580, N_1675, N_1676, - N_1677, N_1678, N_1679, N_1683, N_1684, N_1690, N_1691, - N_1695, N_1696, N_1697, N_1698, N_1699, N_1700, N_1701, - N_1702, N_1703, N_1704, N_1705, N_1706, N_1707, N_1708, - N_1709, N_1710, N_1711, N_1712, N_1713, N_1714, N_1715, - N_1716, N_1717, N_1719, N_1720, N_1721, N_1722, N_1723, - N_1724, N_1725, N_1726, N_1727, N_1728, N_1729, N_1732, - N_1733, N_1734, N_1735, N_1736, N_1737, N_1738, N_1739, - N_1740, N_729, N_730, N_731, N_732, N_733, N_734, N_735, - N_736, N_737, N_738, N_739, N_740, N_741, N_742, N_743, - N_744, N_745, N_746, N_747, N_748, N_749, N_750, N_751, - N_752, \data_valid_and_ready[2]_net_1\, N_753, N_754, - N_755, N_756, N_757, N_758, N_759, N_760, N_761, N_771, - N_772, N_773, N_774, N_775, N_776, N_777, N_778, N_779, - N_780, N_781, N_782, N_783, N_784, N_785, N_786, N_787, - N_788, N_789, N_790, N_791, N_792, N_796, N_797, N_798, - N_799, N_800, N_801, N_802, N_803, N_804, N_805, N_806, - N_807, N_808, N_809, N_810, N_811, N_812, N_813, N_814, - N_815, N_816, N_817, N_818, N_819, N_820, N_821, N_822, - N_823, N_824, N_825, N_826, N_827, N_828, N_829, N_830, - N_831, N_832, N_833, N_834, N_835, N_836, - \data_valid_and_ready[0]_net_1\, N_837, N_838, N_839, - N_840, N_844, N_845, N_846, N_847, \data_wen_3[0]\, - \time_en_temp[0]_net_1\, \data_wen_3[2]\, - \time_en_temp[2]_net_1\, \data_wen_3[3]\, - \time_en_temp[3]_net_1\, \data_selected[127]\, - \data_selected[159]\, N_696, \data_temp[127]_net_1\, - N_728, \data_temp_5[95]\, \data_temp_5[127]\, - \data_temp_5[14]\, \data_temp[46]_net_1\, - \data_temp_5[13]\, \data_temp[45]_net_1\, - \data_temp_5[12]\, \data_temp[44]_net_1\, - \data_temp_5[11]\, \data_temp[43]_net_1\, - \data_temp_5[10]\, \data_temp[42]_net_1\, - \data_temp_5[9]\, \data_temp[41]_net_1\, \data_temp_5[8]\, - \data_temp[40]_net_1\, \data_temp_5[7]\, - \data_temp[39]_net_1\, \data_temp_5[6]\, - \data_temp[38]_net_1\, \data_temp_5[5]\, - \data_temp[37]_net_1\, \data_temp_5[4]\, - \data_temp[36]_net_1\, \data_temp_5[3]\, - \data_temp[35]_net_1\, \data_temp_5[2]\, - \data_temp[34]_net_1\, \data_temp_5[1]\, - \data_temp[33]_net_1\, \data_temp_5[0]\, - \data_temp[32]_net_1\, \data_5[31]\, - \data_temp[31]_net_1\, \data_5[30]\, - \data_temp[30]_net_1\, \data_5[29]\, - \data_temp[29]_net_1\, \data_5[28]\, - \data_temp[28]_net_1\, \data_5[27]\, - \data_temp[27]_net_1\, \data_5[26]\, - \data_temp[26]_net_1\, \data_5[25]\, - \data_temp[25]_net_1\, \data_5[24]\, - \data_temp[24]_net_1\, \data_5[23]\, - \data_temp[23]_net_1\, \data_5[22]\, - \data_temp[22]_net_1\, \data_5[21]\, - \data_temp[21]_net_1\, \data_5[20]\, - \data_temp[20]_net_1\, \data_5[19]\, - \data_temp[19]_net_1\, \data_5[18]\, - \data_temp[18]_net_1\, \data_5[17]\, - \data_temp[17]_net_1\, \data_5[16]\, - \data_temp[16]_net_1\, \data_5[15]\, - \data_temp[15]_net_1\, \data_5[14]\, - \data_temp[14]_net_1\, \data_5[13]\, - \data_temp[13]_net_1\, \data_5[12]\, - \data_temp[12]_net_1\, \data_5[11]\, - \data_temp[11]_net_1\, \data_5[10]\, - \data_temp[10]_net_1\, \data_5[9]\, \data_temp[9]_net_1\, - \data_5[8]\, \data_temp[8]_net_1\, \data_5[7]\, - \data_temp[7]_net_1\, \data_5[6]\, \data_temp[6]_net_1\, - \data_selected[76]\, \data_selected[77]\, - \data_selected[78]\, \data_selected[79]\, - \data_selected[126]\, \data_selected[158]\, N_645, - \data_temp[76]_net_1\, N_646, \data_temp[77]_net_1\, - N_647, \data_temp[78]_net_1\, N_648, - \data_temp[79]_net_1\, N_695, \data_temp[126]_net_1\, - N_727, \data_temp_5[44]\, \data_temp_5[45]\, - \data_temp_5[46]\, \data_temp_5[47]\, \data_temp_5[94]\, - \data_temp_5[126]\, \data_temp_5[31]\, - \data_temp[63]_net_1\, \data_temp_5[30]\, - \data_temp[62]_net_1\, \data_temp_5[29]\, - \data_temp[61]_net_1\, \data_temp_5[28]\, - \data_temp[60]_net_1\, \data_temp_5[27]\, - \data_temp[59]_net_1\, \data_temp_5[26]\, - \data_temp[58]_net_1\, \data_temp_5[25]\, - \data_temp[57]_net_1\, \data_temp_5[24]\, - \data_temp[56]_net_1\, \data_temp_5[23]\, - \data_temp[55]_net_1\, \data_temp_5[22]\, - \data_temp[54]_net_1\, \data_temp_5[21]\, - \data_temp[53]_net_1\, \data_temp_5[20]\, - \data_temp[52]_net_1\, \data_temp_5[19]\, - \data_temp[51]_net_1\, \data_temp_5[18]\, - \data_temp[50]_net_1\, \data_temp_5[17]\, - \data_temp[49]_net_1\, \data_temp_5[16]\, - \data_temp[48]_net_1\, \data_temp_5[15]\, - \data_temp[47]_net_1\, N_928, N_929, \data_selected[80]\, - \data_selected[81]\, \data_selected[82]\, - \data_selected[83]\, \data_selected[84]\, - \data_selected[85]\, \data_selected[86]\, - \data_selected[87]\, \data_selected[88]\, - \data_selected[89]\, \data_selected[90]\, - \data_selected[91]\, \data_selected[92]\, - \data_selected[93]\, \data_selected[94]\, - \data_selected[95]\, \data_selected[112]\, - \data_selected[144]\, N_649, \data_temp[80]_net_1\, N_650, - \data_temp[81]_net_1\, N_651, \data_temp[82]_net_1\, - N_652, \data_temp[83]_net_1\, N_653, - \data_temp[84]_net_1\, N_654, \data_temp[85]_net_1\, - N_655, \data_temp[86]_net_1\, N_656, - \data_temp[87]_net_1\, N_657, \data_temp[88]_net_1\, - N_658, \data_temp[89]_net_1\, N_659, - \data_temp[90]_net_1\, N_660, \data_temp[91]_net_1\, - N_661, \data_temp[92]_net_1\, N_662, - \data_temp[93]_net_1\, N_663, \data_temp[94]_net_1\, - N_664, \data_temp[95]_net_1\, N_681, - \data_temp[112]_net_1\, N_713, \data_temp_5[48]\, - \data_temp_5[49]\, \data_temp_5[50]\, \data_temp_5[51]\, - \data_temp_5[52]\, \data_temp_5[53]\, \data_temp_5[54]\, - \data_temp_5[55]\, \data_temp_5[56]\, \data_temp_5[57]\, - \data_temp_5[58]\, \data_temp_5[59]\, \data_temp_5[60]\, - \data_temp_5[61]\, \data_temp_5[62]\, \data_temp_5[63]\, - \data_temp_5[80]\, \data_temp_5[112]\, \data_5[5]\, - \data_temp[5]_net_1\, \data_5[4]\, \data_temp[4]_net_1\, - \data_5[3]\, \data_temp[3]_net_1\, \data_5[2]\, - \data_temp[2]_net_1\, \data_5[1]\, \data_temp[1]_net_1\, - \data_5[0]\, \data_temp[0]_net_1\, \data_selected[108]\, - \data_selected[110]\, \data_selected[140]\, - \data_selected[142]\, N_677, \data_temp[108]_net_1\, - N_679, \data_temp[110]_net_1\, N_709, N_711, - \data_temp_5[76]\, \data_temp_5[78]\, \data_temp_5[108]\, - \data_temp_5[110]\, \data_selected[107]\, - \data_selected[111]\, \data_selected[139]\, - \data_selected[143]\, N_676, \data_temp[107]_net_1\, - N_680, \data_temp[111]_net_1\, N_708, N_712, - \data_temp_5[75]\, \data_temp_5[79]\, \data_temp_5[107]\, - \data_temp_5[111]\, \data_selected[106]\, - \data_selected[113]\, \data_selected[138]\, - \data_selected[145]\, N_675, \data_temp[106]_net_1\, - N_682, \data_temp[113]_net_1\, N_707, N_714, - \data_temp_5[74]\, \data_temp_5[81]\, \data_temp_5[106]\, - \data_temp_5[113]\, \data_selected[105]\, - \data_selected[114]\, \data_selected[137]\, - \data_selected[146]\, N_674, \data_temp[105]_net_1\, - N_683, \data_temp[114]_net_1\, N_706, N_715, - \data_temp_5[73]\, \data_temp_5[82]\, \data_temp_5[105]\, - \data_temp_5[114]\, \data_selected[104]\, - \data_selected[115]\, \data_selected[136]\, - \data_selected[147]\, N_673, \data_temp[104]_net_1\, - N_684, \data_temp[115]_net_1\, N_705, N_716, - \data_temp_5[72]\, \data_temp_5[83]\, \data_temp_5[104]\, - \data_temp_5[115]\, \data_selected[103]\, - \data_selected[116]\, \data_selected[135]\, - \data_selected[148]\, N_672, \data_temp[103]_net_1\, - N_685, \data_temp[116]_net_1\, N_704, N_717, - \data_temp_5[71]\, \data_temp_5[84]\, \data_temp_5[103]\, - \data_temp_5[116]\, \data_selected[102]\, - \data_selected[117]\, \data_selected[134]\, - \data_selected[149]\, N_671, \data_temp[102]_net_1\, - N_686, \data_temp[117]_net_1\, N_703, N_718, - \data_temp_5[70]\, \data_temp_5[85]\, \data_temp_5[102]\, - \data_temp_5[117]\, \data_selected[101]\, - \data_selected[118]\, \data_selected[133]\, - \data_selected[150]\, N_670, \data_temp[101]_net_1\, - N_687, \data_temp[118]_net_1\, N_702, N_719, - \data_temp_5[69]\, \data_temp_5[86]\, \data_temp_5[101]\, - \data_temp_5[118]\, \data_selected[100]\, - \data_selected[119]\, \data_selected[132]\, - \data_selected[151]\, N_669, \data_temp[100]_net_1\, - N_688, \data_temp[119]_net_1\, N_701, N_720, - \data_temp_5[68]\, \data_temp_5[87]\, \data_temp_5[100]\, - \data_temp_5[119]\, \data_selected[99]\, - \data_selected[120]\, \data_selected[131]\, - \data_selected[152]\, N_668, \data_temp[99]_net_1\, N_689, - \data_temp[120]_net_1\, N_700, N_721, \data_temp_5[67]\, - \data_temp_5[88]\, \data_temp_5[99]\, \data_temp_5[120]\, - \data_selected[98]\, \data_selected[121]\, - \data_selected[130]\, \data_selected[153]\, N_667, - \data_temp[98]_net_1\, N_690, \data_temp[121]_net_1\, - N_699, N_722, \data_temp_5[66]\, \data_temp_5[89]\, - \data_temp_5[98]\, \data_temp_5[121]\, - \data_selected[97]\, \data_selected[122]\, - \data_selected[129]\, \data_selected[154]\, N_666, - \data_temp[97]_net_1\, N_691, \data_temp[122]_net_1\, - N_698, N_723, \data_temp_5[65]\, \data_temp_5[90]\, - \data_temp_5[97]\, \data_temp_5[122]\, - \data_selected[96]\, \data_selected[109]\, - \data_selected[128]\, \data_selected[141]\, N_665, - \data_temp[96]_net_1\, N_678, \data_temp[109]_net_1\, - N_697, N_710, \data_temp_5[64]\, \data_temp_5[77]\, - \data_temp_5[96]\, \data_temp_5[109]\, \data_wen_3[1]\, - \time_en_temp[1]_net_1\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \data_temp_RNO_2[65]\ : MX2C - port map(A => data_f2_out(97), B => data_f3_out(97), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_734); - - \data_temp[124]\ : DFN1C0 - port map(D => N_245, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[124]_net_1\); - - \data_temp_RNO_4[42]\ : MX2 - port map(A => data_f2_out(74), B => data_f3_out(74), S => - \data_valid_and_ready[2]_net_1\, Y => N_767); - - \data_temp[99]\ : DFN1C0 - port map(D => \data_temp_5[99]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[99]_net_1\); - - \data_temp_RNO_1[76]\ : MX2C - port map(A => N_731, B => N_806, S => N_1580_2, Y => - \data_selected[108]\); - - \data_temp_RNO_0[42]\ : AO1D - port map(A => N_912_i, B => N_842, C => N_1668, Y => - \data_temp_5_i_0[42]\); - - \data[3]\ : DFN1C0 - port map(D => \data_5[3]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(3)); - - \data_temp_RNO_2[32]\ : MX2 - port map(A => data_f0_out(64), B => data_f1_out(64), S => - \data_valid_and_ready_0[0]_net_1\, Y => N_769); - - \data_temp_RNO_2[64]\ : MX2C - port map(A => data_f2_out(96), B => data_f3_out(96), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_747); - - \time_en_temp[1]\ : DFN1E0C0 - port map(D => N_917, CLK => HCLK_c, CLR => HRESETn_c, E => - state_0_sqmuxa_i, Q => \time_en_temp[1]_net_1\); - - \data_temp[127]\ : DFN1C0 - port map(D => \data_temp_5[127]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[127]_net_1\); - - \time_wen_RNO[1]\ : INV - port map(A => N_857, Y => N_857_i); - - \data_RNO[13]\ : NOR2A - port map(A => \data_temp[13]_net_1\, B => \state[4]_net_1\, - Y => \data_5[13]\); - - \state_RNIQTIC[2]\ : NOR2 - port map(A => \state[4]_net_1\, B => \state[2]_net_1\, Y - => N_928); - - \data_temp_RNO_1[86]\ : MX2C - port map(A => N_1725, B => N_802, S => N_1580_3, Y => - \data_selected[118]\); - - \data_temp_RNO_1[73]\ : MX2C - port map(A => N_1740, B => N_817, S => N_1580_2, Y => - \data_selected[105]\); - - \data_temp_RNO_0[103]\ : MX2C - port map(A => \data_temp[103]_net_1\, B => - \data_selected[135]\, S => \state[4]_net_1\, Y => N_704); - - \data_temp_RNO_1[101]\ : MX2C - port map(A => N_1712, B => N_789, S => N_1580_3, Y => - \data_selected[133]\); - - \data_temp_RNO_2[124]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1693, - Y => N_904); - - \data_temp_RNO_1[96]\ : MX2C - port map(A => N_1721, B => N_798, S => N_1580, Y => - \data_selected[128]\); - - \data_temp_RNO_1[83]\ : MX2C - port map(A => N_1736, B => N_799, S => N_1580_3, Y => - \data_selected[115]\); - - \data_temp[26]\ : DFN1C0 - port map(D => \data_temp_5[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[26]_net_1\); - - \data_RNO[17]\ : NOR2A - port map(A => \data_temp[17]_net_1\, B => \state[4]_net_1\, - Y => \data_5[17]\); - - \data_valid_ack[3]\ : DFN1E0C0 - port map(D => N_860_i, CLK => HCLK_c, CLR => HRESETn_c, E - => N_929, Q => valid_ack(3)); - - \data_temp_RNO_1[39]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_764, - Y => N_1660); - - \data_temp_RNO_1[93]\ : MX2 - port map(A => data_f0_out(125), B => data_f1_out(125), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_795); - - \data_temp[13]\ : DFN1C0 - port map(D => \data_temp_5[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[13]_net_1\); - - \data_temp[56]\ : DFN1C0 - port map(D => \data_temp_5[56]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[56]_net_1\); - - \data_temp_RNO_2[127]\ : MX2C - port map(A => data_f2_out(159), B => data_f3_out(159), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1696); - - \data_temp[125]\ : DFN1C0 - port map(D => N_247, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[125]_net_1\); - - \data_temp_RNO[65]\ : NOR2A - port map(A => N_863, B => N_666, Y => \data_temp_5[65]\); - - \data_temp_RNO[98]\ : NOR2A - port map(A => N_863, B => N_699, Y => \data_temp_5[98]\); - - \data_RNO[5]\ : NOR2A - port map(A => \data_temp[5]_net_1\, B => \state[4]_net_1\, - Y => \data_5[5]\); - - \data_temp_RNO_2[119]\ : MX2C - port map(A => data_f2_out(151), B => data_f3_out(151), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1702); - - \data_wen[3]\ : DFN1E0P0 - port map(D => \data_wen_3[3]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => data_wen(3)); - - \data_temp[70]\ : DFN1C0 - port map(D => \data_temp_5[70]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[70]_net_1\); - - \data_temp_RNO[39]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[39]\, C => - N_1660, Y => N_231); - - \data_temp_RNO[77]\ : NOR2A - port map(A => N_863, B => N_678, Y => \data_temp_5[77]\); - - \data[13]\ : DFN1C0 - port map(D => \data_5[13]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(13)); - - \data_temp_RNO_2[57]\ : MX2C - port map(A => data_f2_out(89), B => data_f3_out(89), S => - \data_valid_and_ready[2]_net_1\, Y => N_754); - - \data_temp[64]\ : DFN1C0 - port map(D => \data_temp_5[64]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[64]_net_1\); - - \data_temp_RNO[93]\ : NOR3B - port map(A => N_863_0, B => N_914, C => - \data_temp_5_i_0[93]\, Y => N_243); - - \state_RNO_0[4]\ : OR3 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, C - => \state[3]_net_1\, Y => \state_ns_i_i_a2_1[0]\); - - \data_temp_RNO_1[50]\ : MX2C - port map(A => N_761, B => N_836, S => N_1580_1, Y => - \data_selected[82]\); - - \data_temp[6]\ : DFN1C0 - port map(D => \data_temp_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[6]_net_1\); - - \data[31]\ : DFN1C0 - port map(D => \data_5[31]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(31)); - - \data_temp[112]\ : DFN1C0 - port map(D => \data_temp_5[112]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[112]_net_1\); - - \data_temp_RNO[112]\ : NOR2A - port map(A => N_863_1, B => N_713, Y => \data_temp_5[112]\); - - \data_temp[100]\ : DFN1C0 - port map(D => \data_temp_5[100]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[100]_net_1\); - - \data_temp_RNO_2[70]\ : MX2C - port map(A => data_f2_out(102), B => data_f3_out(102), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_739); - - \data_temp_RNO_3[56]\ : MX2C - port map(A => data_f0_out(88), B => data_f1_out(88), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_828); - - \data_temp_RNO_0[37]\ : AO1D - port map(A => N_912_i, B => N_851, C => N_1653, Y => - \data_temp_5_i_0[37]\); - - \data_temp_RNO[36]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[36]\, C => - N_1651, Y => N_225); - - \data_temp_RNO_0[59]\ : MX2C - port map(A => \data_temp[91]_net_1\, B => - \data_selected[91]\, S => \state[4]_net_1\, Y => N_660); - - \data_temp_RNO_0[51]\ : MX2C - port map(A => \data_temp[83]_net_1\, B => - \data_selected[83]\, S => \state[4]_net_1\, Y => N_652); - - \data_temp_RNO_3[66]\ : MX2C - port map(A => data_f0_out(98), B => data_f1_out(98), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_824); - - \data_temp_RNO_3[86]\ : MX2C - port map(A => data_f0_out(118), B => data_f1_out(118), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_802); - - \data_temp_RNO_3[49]\ : MX2C - port map(A => data_f0_out(81), B => data_f1_out(81), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_835); - - \data_temp_RNO_3[41]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[73]_net_1\, - Y => N_1665); - - \data_temp_RNO_2[40]\ : MX2 - port map(A => data_f0_out(72), B => data_f1_out(72), S => - \data_valid_and_ready[0]_net_1\, Y => N_854); - - \data_temp_RNO_0[116]\ : MX2C - port map(A => \data_temp[116]_net_1\, B => - \data_selected[148]\, S => \state[4]_net_1\, Y => N_717); - - \data_temp_RNO_1[35]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1688, - Y => N_874); - - \data_temp_RNO_3[53]\ : MX2C - port map(A => data_f0_out(85), B => data_f1_out(85), S => - \data_valid_and_ready[0]_net_1\, Y => N_839); - - \data_temp_RNO[49]\ : NOR2A - port map(A => N_863_1, B => N_650, Y => \data_temp_5[49]\); - - \data_temp_RNO_3[63]\ : MX2C - port map(A => data_f0_out(95), B => data_f1_out(95), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_821); - - \data_temp_RNO_3[83]\ : MX2C - port map(A => data_f0_out(115), B => data_f1_out(115), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_799); - - \data_temp_RNO_2[120]\ : MX2C - port map(A => data_f2_out(152), B => data_f3_out(152), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1703); - - \data_temp_RNO_1[52]\ : MX2C - port map(A => N_749, B => N_838, S => N_1580_1, Y => - \data_selected[84]\); - - \data_temp_RNO_1[34]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1687, - Y => N_871); - - \state[2]\ : DFN1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - \data_temp[36]\ : DFN1C0 - port map(D => N_225, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[36]_net_1\); - - un5_data_selected_i_i_a2 : OR2B - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_917); - - \data_wen_RNO[0]\ : OR2 - port map(A => \time_en_temp[0]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[0]\); - - \data_temp_RNO_2[72]\ : MX2C - port map(A => data_f2_out(104), B => data_f3_out(104), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1739); - - \data_temp_RNO_1[110]\ : MX2C - port map(A => N_1707, B => N_784, S => N_1580_2, Y => - \data_selected[142]\); - - \data_temp[82]\ : DFN1C0 - port map(D => \data_temp_5[82]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[82]_net_1\); - - \data_temp_RNO[46]\ : NOR2A - port map(A => N_863_0, B => N_647, Y => \data_temp_5[46]\); - - \data_temp[0]\ : DFN1C0 - port map(D => \data_temp_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[0]_net_1\); - - data_selected_sn_m2_0_o2_2 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_2); - - \data_temp_RNO_2[42]\ : MX2 - port map(A => data_f0_out(74), B => data_f1_out(74), S => - \data_valid_and_ready[0]_net_1\, Y => N_842); - - \data_temp_RNO_1[49]\ : MX2C - port map(A => N_760, B => N_835, S => N_1580_1, Y => - \data_selected[81]\); - - \data_temp_RNO_1[41]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_766, - Y => N_1666); - - \data_RNO[2]\ : NOR2A - port map(A => \data_temp[2]_net_1\, B => \state[4]_net_1\, - Y => \data_5[2]\); - - \data_temp_RNO_2[86]\ : MX2C - port map(A => data_f2_out(118), B => data_f3_out(118), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1725); - - \data_temp[10]\ : DFN1C0 - port map(D => \data_temp_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[10]_net_1\); - - \data_temp[111]\ : DFN1C0 - port map(D => \data_temp_5[111]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[111]_net_1\); - - \data_temp_RNO_3[36]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[68]_net_1\, - Y => N_1650); - - \data_temp_RNO_0[55]\ : MX2C - port map(A => \data_temp[87]_net_1\, B => - \data_selected[87]\, S => \state[4]_net_1\, Y => N_656); - - \time_wen[1]\ : DFN1E0P0 - port map(D => N_857_i, CLK => HCLK_c, PRE => HRESETn_c, E - => N_928, Q => time_wen(1)); - - \data_temp_RNO_1[127]\ : MX2C - port map(A => N_1696, B => N_1684, S => N_1580_1, Y => - \data_selected[159]\); - - \data_temp_RNO[10]\ : NOR2A - port map(A => \data_temp[42]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[10]\); - - \data_temp_RNO_3[45]\ : MX2C - port map(A => data_f0_out(77), B => data_f1_out(77), S => - \data_valid_and_ready[0]_net_1\, Y => N_845); - - \data_temp_RNO_3[108]\ : MX2C - port map(A => data_f0_out(140), B => data_f1_out(140), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_782); - - \data_temp[24]\ : DFN1C0 - port map(D => \data_temp_5[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[24]_net_1\); - - \data_temp_RNO_0[115]\ : MX2C - port map(A => \data_temp[115]_net_1\, B => - \data_selected[147]\, S => \state[4]_net_1\, Y => N_716); - - \data_temp_RNO_2[83]\ : MX2C - port map(A => data_f2_out(115), B => data_f3_out(115), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1736); - - \data_temp_RNO_0[54]\ : MX2C - port map(A => \data_temp[86]_net_1\, B => - \data_selected[86]\, S => \state[4]_net_1\, Y => N_655); - - \data_temp_RNO[4]\ : NOR2A - port map(A => \data_temp[36]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[4]\); - - \data_temp[119]\ : DFN1C0 - port map(D => \data_temp_5[119]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[119]_net_1\); - - \data_temp_RNO_3[33]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[65]_net_1\, - Y => N_867); - - \data_temp_RNO_2[66]\ : MX2C - port map(A => data_f2_out(98), B => data_f3_out(98), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_735); - - \data_temp[54]\ : DFN1C0 - port map(D => \data_temp_5[54]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[54]_net_1\); - - \data_temp_RNO_3[44]\ : MX2C - port map(A => data_f0_out(76), B => data_f1_out(76), S => - \data_valid_and_ready[0]_net_1\, Y => N_844); - - \data_temp_RNO[75]\ : NOR2A - port map(A => N_863_2, B => N_676, Y => \data_temp_5[75]\); - - \data_temp[81]\ : DFN1C0 - port map(D => \data_temp_5[81]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[81]_net_1\); - - \data_RNO[11]\ : NOR2A - port map(A => \data_temp[11]_net_1\, B => \state[4]_net_1\, - Y => \data_5[11]\); - - \data_temp_RNO_3[99]\ : MX2C - port map(A => data_f0_out(131), B => data_f1_out(131), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_787); - - \data_temp_RNO_3[91]\ : MX2 - port map(A => data_f2_out(123), B => data_f3_out(123), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1730); - - \data_temp_RNO[37]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[37]\, C => - N_1654, Y => N_227); - - \data_temp_RNO_2[63]\ : MX2C - port map(A => data_f2_out(95), B => data_f3_out(95), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_746); - - \data_RNO[12]\ : NOR2A - port map(A => \data_temp[12]_net_1\, B => \state[4]_net_1\, - Y => \data_5[12]\); - - \data_valid_ack_RNO[0]\ : INV - port map(A => \time_wen_3[0]\, Y => \time_wen_3_i[0]\); - - \data_temp_RNO_3[127]\ : MX2C - port map(A => data_f0_out(159), B => data_f1_out(159), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1684); - - \data_temp_RNO[2]\ : NOR2A - port map(A => \data_temp[34]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[2]\); - - \data_temp_RNO_1[68]\ : MX2C - port map(A => N_737, B => N_826, S => N_1580_3, Y => - \data_selected[100]\); - - \data_temp_RNO_0[120]\ : MX2C - port map(A => \data_temp[120]_net_1\, B => - \data_selected[152]\, S => \state[4]_net_1\, Y => N_721); - - \data_temp_RNO_1[45]\ : MX2C - port map(A => N_756, B => N_845, S => N_1580_1, Y => - \data_selected[77]\); - - \data_temp_RNO_0[98]\ : MX2C - port map(A => \data_temp[98]_net_1\, B => - \data_selected[130]\, S => \state[4]_net_1\, Y => N_699); - - \data_temp_RNO[91]\ : NOR3B - port map(A => N_863_0, B => N_913, C => - \data_temp_5_i_0[91]\, Y => N_249); - - \data_temp_RNO[115]\ : NOR2A - port map(A => N_863_2, B => N_716, Y => \data_temp_5[115]\); - - \data_temp[76]\ : DFN1C0 - port map(D => \data_temp_5[76]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[76]_net_1\); - - \data_temp_RNO_1[44]\ : MX2C - port map(A => N_755, B => N_844, S => N_1580_1, Y => - \data_selected[76]\); - - \data_RNO[28]\ : NOR2A - port map(A => \data_temp[28]_net_1\, B => \state[4]_net_1\, - Y => \data_5[28]\); - - \data_temp_RNO[68]\ : NOR2A - port map(A => N_863, B => N_669, Y => \data_temp_5[68]\); - - \data_temp_RNO_0[117]\ : MX2C - port map(A => \data_temp[117]_net_1\, B => - \data_selected[149]\, S => \state[4]_net_1\, Y => N_718); - - \data_temp_RNO[92]\ : NOR3B - port map(A => N_863_0, B => N_915, C => - \data_temp_5_i_0[92]\, Y => N_241); - - \time_en_temp_RNO[2]\ : OR2 - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - N_1580_0, Y => N_858); - - \data_temp_RNO_3[122]\ : MX2C - port map(A => data_f0_out(154), B => data_f1_out(154), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1679); - - \data_temp_RNO_2[50]\ : MX2C - port map(A => data_f2_out(82), B => data_f3_out(82), S => - \data_valid_and_ready[2]_net_1\, Y => N_761); - - \data_temp[88]\ : DFN1C0 - port map(D => \data_temp_5[88]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[88]_net_1\); - - \data[28]\ : DFN1C0 - port map(D => \data_5[28]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(28)); - - \data_temp_RNO[20]\ : NOR2A - port map(A => \data_temp[52]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[20]\); - - \data_temp_RNO[63]\ : NOR2A - port map(A => N_863_1, B => N_664, Y => \data_temp_5[63]\); - - \data_temp_RNO[47]\ : NOR2A - port map(A => N_863_0, B => N_648, Y => \data_temp_5[47]\); - - \data_temp_RNO[117]\ : NOR2A - port map(A => N_863_2, B => N_718, Y => \data_temp_5[117]\); - - \data_wen_RNO[1]\ : OR2 - port map(A => \time_en_temp[1]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[1]\); - - \data_temp[93]\ : DFN1C0 - port map(D => N_243, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[93]_net_1\); - - \data_temp[49]\ : DFN1C0 - port map(D => \data_temp_5[49]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[49]_net_1\); - - \data_temp_RNO_3[95]\ : MX2C - port map(A => data_f0_out(127), B => data_f1_out(127), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_797); - - \data_temp_RNO_2[109]\ : MX2C - port map(A => data_f2_out(141), B => data_f3_out(141), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1706); - - \data[5]\ : DFN1C0 - port map(D => \data_5[5]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(5)); - - \data_temp_RNO_4[41]\ : MX2 - port map(A => data_f2_out(73), B => data_f3_out(73), S => - \data_valid_and_ready[2]_net_1\, Y => N_766); - - \data_temp[34]\ : DFN1C0 - port map(D => N_221, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[34]_net_1\); - - \data[16]\ : DFN1C0 - port map(D => \data_5[16]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(16)); - - \data_temp_RNO_3[78]\ : MX2C - port map(A => data_f0_out(110), B => data_f1_out(110), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_808); - - \data_temp_RNO_0[49]\ : MX2C - port map(A => \data_temp[81]_net_1\, B => - \data_selected[81]\, S => \state[4]_net_1\, Y => N_650); - - \data_temp_RNO_0[41]\ : AO1D - port map(A => N_912_i, B => N_841, C => N_1665, Y => - \data_temp_5_i_0[41]\); - - \data_temp[62]\ : DFN1C0 - port map(D => \data_temp_5[62]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[62]_net_1\); - - \data_temp_RNO[94]\ : NOR2A - port map(A => N_863_1, B => N_695, Y => \data_temp_5[94]\); - - \data[7]\ : DFN1C0 - port map(D => \data_5[7]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(7)); - - \data_temp_RNO_3[114]\ : MX2C - port map(A => data_f0_out(146), B => data_f1_out(146), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_774); - - \data_temp_RNO_2[39]\ : MX2 - port map(A => data_f0_out(71), B => data_f1_out(71), S => - \data_valid_and_ready[0]_net_1\, Y => N_853); - - \data_temp_RNO[122]\ : NOR2A - port map(A => N_863, B => N_723, Y => \data_temp_5[122]\); - - \data_RNO[31]\ : NOR2A - port map(A => \data_temp[31]_net_1\, B => \state[4]_net_1\, - Y => \data_5[31]\); - - \data_temp_RNO_3[94]\ : MX2C - port map(A => data_f0_out(126), B => data_f1_out(126), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_796); - - \data_temp[87]\ : DFN1C0 - port map(D => \data_temp_5[87]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[87]_net_1\); - - \data_temp_RNO_3[126]\ : MX2C - port map(A => data_f0_out(158), B => data_f1_out(158), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1683); - - \data_temp_RNO_0[78]\ : MX2C - port map(A => \data_temp[110]_net_1\, B => - \data_selected[110]\, S => \state[4]_net_1\, Y => N_679); - - \data_temp_RNO_2[52]\ : MX2C - port map(A => data_f2_out(84), B => data_f3_out(84), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_749); - - \data_temp[108]\ : DFN1C0 - port map(D => \data_temp_5[108]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[108]_net_1\); - - \data_temp_RNO_1[112]\ : MX2C - port map(A => N_1709, B => N_772, S => N_1580_2, Y => - \data_selected[144]\); - - \data_temp_RNO_0[106]\ : MX2C - port map(A => \data_temp[106]_net_1\, B => - \data_selected[138]\, S => \state[4]_net_1\, Y => N_707); - - \data_temp_RNO[59]\ : NOR2A - port map(A => N_863_1, B => N_660, Y => \data_temp_5[59]\); - - \data_temp_RNO_0[32]\ : AO1D - port map(A => N_912_i, B => N_769, C => N_864, Y => - \data_temp_5_i_0[32]\); - - \data_temp[61]\ : DFN1C0 - port map(D => \data_temp_5[61]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[61]_net_1\); - - \data_temp_RNO_4[38]\ : MX2 - port map(A => data_f2_out(70), B => data_f3_out(70), S => - \data_valid_and_ready[2]_net_1\, Y => N_763); - - \data_temp[16]\ : DFN1C0 - port map(D => \data_temp_5[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[16]_net_1\); - - \data[21]\ : DFN1C0 - port map(D => \data_5[21]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(21)); - - \data_temp_RNO_1[36]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1689, - Y => N_1651); - - \data_temp_RNO[89]\ : NOR2A - port map(A => N_863, B => N_690, Y => \data_temp_5[89]\); - - \data_temp_RNO[35]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[35]\, C => - N_874, Y => N_223); - - \data_temp_RNO[102]\ : NOR2A - port map(A => N_863_2, B => N_703, Y => \data_temp_5[102]\); - - \data_temp_RNO_1[123]\ : MX2 - port map(A => data_f0_out(155), B => data_f1_out(155), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1680); - - \data_temp_RNO_3[110]\ : MX2C - port map(A => data_f0_out(142), B => data_f1_out(142), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_784); - - \data_temp_RNO_2[122]\ : MX2C - port map(A => data_f2_out(154), B => data_f3_out(154), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1691); - - \data_temp_RNO_0[45]\ : MX2C - port map(A => \data_temp[77]_net_1\, B => - \data_selected[77]\, S => \state[4]_net_1\, Y => N_646); - - \data_temp_RNO_2[125]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1694, - Y => N_906); - - \data[0]\ : DFN1C0 - port map(D => \data_5[0]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(0)); - - \data_temp_RNO[56]\ : NOR2A - port map(A => N_863_1, B => N_657, Y => \data_temp_5[56]\); - - \data_temp_RNO_2[35]\ : MX2 - port map(A => data_f0_out(67), B => data_f1_out(67), S => - \data_valid_and_ready[0]_net_1\, Y => N_849); - - \data_valid_ack[0]\ : DFN1E0C0 - port map(D => \time_wen_3_i[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_929, Q => valid_ack(0)); - - \data_temp_RNO_1[33]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1686, - Y => N_868); - - \data_temp_RNO[86]\ : NOR2A - port map(A => N_863, B => N_687, Y => \data_temp_5[86]\); - - \data_temp_RNO_1[119]\ : MX2C - port map(A => N_1702, B => N_1676, S => N_1580, Y => - \data_selected[151]\); - - \data_temp_RNO_1[100]\ : MX2C - port map(A => N_1711, B => N_788, S => N_1580, Y => - \data_selected[132]\); - - \data_temp_RNO_1[118]\ : MX2C - port map(A => N_1701, B => N_1675, S => N_1580_3, Y => - \data_selected[150]\); - - GND_i : GND - port map(Y => \GND\); - - \data_temp_RNO_0[44]\ : MX2C - port map(A => \data_temp[76]_net_1\, B => - \data_selected[76]\, S => \state[4]_net_1\, Y => N_645); - - \data_temp_RNO_2[34]\ : MX2 - port map(A => data_f0_out(66), B => data_f1_out(66), S => - \data_valid_and_ready[0]_net_1\, Y => N_848); - - \data_RNO[16]\ : NOR2A - port map(A => \data_temp[16]_net_1\, B => \state[4]_net_1\, - Y => \data_5[16]\); - - \data_temp[74]\ : DFN1C0 - port map(D => \data_temp_5[74]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[74]_net_1\); - - \data_temp[90]\ : DFN1C0 - port map(D => \data_temp_5[90]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[90]_net_1\); - - \data_temp[22]\ : DFN1C0 - port map(D => \data_temp_5[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[22]_net_1\); - - \time_wen_3_i_a2_0[3]\ : NOR2B - port map(A => \data_valid_and_ready[3]_net_1\, B => - \data_valid_and_ready_0[2]_net_1\, Y => - \time_wen_3_i_a2_0[3]_net_1\); - - \state_RNIUI96[4]\ : CLKINT - port map(A => \state_0[4]\, Y => \state[4]_net_1\); - - \data_temp_RNO_0[56]\ : MX2C - port map(A => \data_temp[88]_net_1\, B => - \data_selected[88]\, S => \state[4]_net_1\, Y => N_657); - - \data_temp_RNO_0[88]\ : MX2C - port map(A => \data_temp[120]_net_1\, B => - \data_selected[120]\, S => \state[4]_net_1\, Y => N_689); - - \data_temp_RNO[78]\ : NOR2A - port map(A => N_863_1, B => N_679, Y => \data_temp_5[78]\); - - \data_temp_RNO_1[67]\ : MX2C - port map(A => N_736, B => N_825, S => N_1580, Y => - \data_selected[99]\); - - \data_temp_RNO[45]\ : NOR2A - port map(A => N_863_0, B => N_646, Y => \data_temp_5[45]\); - - \data_temp_RNO_3[46]\ : MX2C - port map(A => data_f0_out(78), B => data_f1_out(78), S => - \data_valid_and_ready[0]_net_1\, Y => N_846); - - \data_temp_RNO_0[112]\ : MX2C - port map(A => \data_temp[112]_net_1\, B => - \data_selected[144]\, S => \state[4]_net_1\, Y => N_713); - - \data_temp[68]\ : DFN1C0 - port map(D => \data_temp_5[68]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[68]_net_1\); - - \time_en_temp[2]\ : DFN1E0C0 - port map(D => N_858, CLK => HCLK_c, CLR => HRESETn_c, E => - state_0_sqmuxa_i, Q => \time_en_temp[2]_net_1\); - - \data_temp_RNO_2[98]\ : MX2C - port map(A => data_f2_out(130), B => data_f3_out(130), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1723); - - \data_temp_RNO_0[105]\ : MX2C - port map(A => \data_temp[105]_net_1\, B => - \data_selected[137]\, S => \state[4]_net_1\, Y => N_706); - - \data_temp_RNIDNBC[124]\ : OR2 - port map(A => \state[4]_net_1\, B => \data_temp[124]_net_1\, - Y => N_915); - - \data_temp[52]\ : DFN1C0 - port map(D => \data_temp_5[52]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[52]_net_1\); - - \data_temp_RNO_0[97]\ : MX2C - port map(A => \data_temp[97]_net_1\, B => - \data_selected[129]\, S => \state[4]_net_1\, Y => N_698); - - \data_temp_RNO_0[119]\ : MX2C - port map(A => \data_temp[119]_net_1\, B => - \data_selected[151]\, S => \state[4]_net_1\, Y => N_720); - - \data[2]\ : DFN1C0 - port map(D => \data_5[2]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(2)); - - \data_temp_RNO[73]\ : NOR2A - port map(A => N_863_2, B => N_674, Y => \data_temp_5[73]\); - - \data_temp[85]\ : DFN1C0 - port map(D => \data_temp_5[85]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[85]_net_1\); - - \data_temp_5_i_a2_0_0[32]\ : NOR2A - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - \data_valid_and_ready[3]_net_1\, Y => - \data_temp_5_i_a2_0_0[32]_net_1\); - - \data_valid_and_ready_1[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready_1[2]_net_1\); - - \data_temp_RNO_0[53]\ : MX2C - port map(A => \data_temp[85]_net_1\, B => - \data_selected[85]\, S => \state[4]_net_1\, Y => N_654); - - \data_temp_RNO_3[43]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[75]_net_1\, - Y => N_897); - - \data[22]\ : DFN1C0 - port map(D => \data_5[22]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(22)); - - \data_temp_RNO_2[126]\ : MX2C - port map(A => data_f2_out(158), B => data_f3_out(158), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1695); - - \data_temp_RNO[61]\ : NOR2A - port map(A => N_863_1, B => N_662, Y => \data_temp_5[61]\); - - \data_temp_RNO_0[68]\ : MX2C - port map(A => \data_temp[100]_net_1\, B => - \data_selected[100]\, S => \state[4]_net_1\, Y => N_669); - - \data_temp[67]\ : DFN1C0 - port map(D => \data_temp_5[67]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[67]_net_1\); - - \data_temp[21]\ : DFN1C0 - port map(D => \data_temp_5[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[21]_net_1\); - - \data_wen[2]\ : DFN1E0P0 - port map(D => \data_wen_3[2]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => data_wen(2)); - - \data_temp[9]\ : DFN1C0 - port map(D => \data_temp_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[9]_net_1\); - - \data_temp_RNO[62]\ : NOR2A - port map(A => N_863_1, B => N_663, Y => \data_temp_5[62]\); - - \data_temp_RNO[125]\ : NOR3B - port map(A => N_863_0, B => N_914, C => - \data_temp_5_i_0[125]\, Y => N_247); - - \data_temp_RNO_1[59]\ : MX2C - port map(A => N_742, B => N_831, S => N_1580_2, Y => - \data_selected[91]\); - - \data_temp_RNO_1[51]\ : MX2C - port map(A => N_748, B => N_837, S => N_1580_1, Y => - \data_selected[83]\); - - \data_temp_RNO_1[46]\ : MX2C - port map(A => N_757, B => N_846, S => N_1580_1, Y => - \data_selected[78]\); - - \data_temp[51]\ : DFN1C0 - port map(D => \data_temp_5[51]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[51]_net_1\); - - data_selected_sn_m2_0_o2_3 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_3); - - \data_temp_RNO_2[79]\ : MX2C - port map(A => data_f2_out(111), B => data_f3_out(111), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1732); - - \data_temp_RNO_2[71]\ : MX2C - port map(A => data_f2_out(103), B => data_f3_out(103), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_740); - - \data_temp_RNO_3[77]\ : MX2C - port map(A => data_f0_out(109), B => data_f1_out(109), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_807); - - \data_temp[120]\ : DFN1C0 - port map(D => \data_temp_5[120]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[120]_net_1\); - - \state_RNIKK3V21_3[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \time_wen_3_i_a2_0[3]_net_1\, C => N_1580_0, Y => N_860); - - \data_temp[106]\ : DFN1C0 - port map(D => \data_temp_5[106]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[106]_net_1\); - - \time_wen[3]\ : DFN1E0P0 - port map(D => N_860, CLK => HCLK_c, PRE => HRESETn_c, E => - N_928, Q => time_wen(3)); - - \data_temp_RNO_2[49]\ : MX2C - port map(A => data_f2_out(81), B => data_f3_out(81), S => - \data_valid_and_ready[2]_net_1\, Y => N_760); - - \data_temp_RNO_2[41]\ : MX2 - port map(A => data_f0_out(73), B => data_f1_out(73), S => - \data_valid_and_ready[0]_net_1\, Y => N_841); - - \data_temp_RNO[127]\ : NOR2A - port map(A => N_863_0, B => N_728, Y => \data_temp_5[127]\); - - \data_temp_RNO_0[107]\ : MX2C - port map(A => \data_temp[107]_net_1\, B => - \data_selected[139]\, S => \state[4]_net_1\, Y => N_708); - - \data_temp_RNO_0[77]\ : MX2C - port map(A => \data_temp[109]_net_1\, B => - \data_selected[109]\, S => \state[4]_net_1\, Y => N_678); - - \data_temp_RNO_1[43]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_768, - Y => N_898); - - \data_temp_RNO[57]\ : NOR2A - port map(A => N_863_1, B => N_658, Y => \data_temp_5[57]\); - - \data_temp_RNO[64]\ : NOR2A - port map(A => N_863, B => N_665, Y => \data_temp_5[64]\); - - \data_temp[14]\ : DFN1C0 - port map(D => \data_temp_5[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[14]_net_1\); - - \data_temp_RNO[87]\ : NOR2A - port map(A => N_863, B => N_688, Y => \data_temp_5[87]\); - - \data_temp[114]\ : DFN1C0 - port map(D => \data_temp_5[114]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[114]_net_1\); - - \data_temp_RNO_0[124]\ : AO1D - port map(A => N_1681, B => N_912_i, C => N_904, Y => - \data_temp_5_i_0[124]\); - - \data_temp_RNO[110]\ : NOR2A - port map(A => N_863_1, B => N_711, Y => \data_temp_5[110]\); - - \data_temp_RNO_3[111]\ : MX2C - port map(A => data_f0_out(143), B => data_f1_out(143), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_771); - - \data_temp_RNO_0[121]\ : MX2C - port map(A => \data_temp[121]_net_1\, B => - \data_selected[153]\, S => \state[4]_net_1\, Y => N_722); - - \data_temp_RNO[105]\ : NOR2A - port map(A => N_863_2, B => N_706, Y => \data_temp_5[105]\); - - \data[29]\ : DFN1C0 - port map(D => \data_5[29]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(29)); - - \data_temp_RNO_1[78]\ : MX2C - port map(A => N_733, B => N_808, S => N_1580_2, Y => - \data_selected[110]\); - - \data_temp[32]\ : DFN1C0 - port map(D => N_215, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[32]_net_1\); - - \data_temp_RNO_0[118]\ : MX2C - port map(A => \data_temp[118]_net_1\, B => - \data_selected[150]\, S => \state[4]_net_1\, Y => N_719); - - \data_temp[28]\ : DFN1C0 - port map(D => \data_temp_5[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[28]_net_1\); - - \data_temp_RNO_3[96]\ : MX2C - port map(A => data_f0_out(128), B => data_f1_out(128), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_798); - - \data_temp[117]\ : DFN1C0 - port map(D => \data_temp_5[117]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[117]_net_1\); - - \data_RNO[19]\ : NOR2A - port map(A => \data_temp[19]_net_1\, B => \state[4]_net_1\, - Y => \data_5[19]\); - - \data_temp_RNO_4[37]\ : MX2 - port map(A => data_f2_out(69), B => data_f3_out(69), S => - \data_valid_and_ready[2]_net_1\, Y => N_762); - - data_selected_sn_m2_0_o2 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580); - - \data_temp[58]\ : DFN1C0 - port map(D => \data_temp_5[58]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[58]_net_1\); - - \data_temp_RNO_1[55]\ : MX2C - port map(A => N_752, B => N_827, S => N_1580_1, Y => - \data_selected[87]\); - - \data_temp_RNO_3[104]\ : MX2C - port map(A => data_f0_out(136), B => data_f1_out(136), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_778); - - \data_temp_RNO_1[88]\ : MX2C - port map(A => N_1727, B => N_804, S => N_1580, Y => - \data_selected[120]\); - - \data_temp_RNO[107]\ : NOR2A - port map(A => N_863_2, B => N_708, Y => \data_temp_5[107]\); - - \state_RNIKK3V21_1[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \data_temp_5_i_a2_0_0[32]_net_1\, C => N_1580_0, Y => - N_863_2); - - \data[25]\ : DFN1C0 - port map(D => \data_5[25]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(25)); - - \data_temp_RNO_3[93]\ : MX2 - port map(A => data_f2_out(125), B => data_f3_out(125), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1718); - - \data_temp_RNO_2[75]\ : MX2C - port map(A => data_f2_out(107), B => data_f3_out(107), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_730); - - \data_valid_and_ready_0[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready_0[2]_net_1\); - - \data_temp_RNO_1[115]\ : MX2C - port map(A => N_1698, B => N_775, S => N_1580_3, Y => - \data_selected[147]\); - - \data_temp[27]\ : DFN1C0 - port map(D => \data_temp_5[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[27]_net_1\); - - \data_temp_RNO_1[54]\ : MX2C - port map(A => N_751, B => N_840, S => N_1580_1, Y => - \data_selected[86]\); - - \data_temp_RNO[38]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[38]\, C => - N_1657, Y => N_229); - - \data_temp_RNO_2[45]\ : MX2C - port map(A => data_f2_out(77), B => data_f3_out(77), S => - \data_valid_and_ready[2]_net_1\, Y => N_756); - - \data_temp_RNO_1[98]\ : MX2C - port map(A => N_1723, B => N_786, S => N_1580, Y => - \data_selected[130]\); - - \data_temp[31]\ : DFN1C0 - port map(D => \data_temp_5[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[31]_net_1\); - - \data_temp_RNO_1[102]\ : MX2C - port map(A => N_1713, B => N_790, S => N_1580_3, Y => - \data_selected[134]\); - - \data_temp[3]\ : DFN1C0 - port map(D => \data_temp_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[3]_net_1\); - - \data_temp_RNO_2[74]\ : MX2C - port map(A => data_f2_out(106), B => data_f3_out(106), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_729); - - \data_temp[65]\ : DFN1C0 - port map(D => \data_temp_5[65]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[65]_net_1\); - - \data_temp[57]\ : DFN1C0 - port map(D => \data_temp_5[57]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[57]_net_1\); - - \state_RNIHQ76Q[4]\ : OR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => - \data_valid_and_ready_0[2]_net_1\, Y => N_859); - - \data_temp_RNO_3[115]\ : MX2C - port map(A => data_f0_out(147), B => data_f1_out(147), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_775); - - \state_RNO[3]\ : INV - port map(A => state_0_sqmuxa_i, Y => state_0_sqmuxa_i_i); - - \data_temp[7]\ : DFN1C0 - port map(D => \data_temp_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[7]_net_1\); - - \data_temp_RNO[33]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[33]\, C => - N_868, Y => N_219); - - \data_temp_RNO_2[44]\ : MX2C - port map(A => data_f2_out(76), B => data_f3_out(76), S => - \data_valid_and_ready[2]_net_1\, Y => N_755); - - \data_temp_RNO_2[118]\ : MX2C - port map(A => data_f2_out(150), B => data_f3_out(150), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1701); - - \data_temp_RNO_1[116]\ : MX2C - port map(A => N_1699, B => N_776, S => N_1580_3, Y => - \data_selected[148]\); - - \data_temp[96]\ : DFN1C0 - port map(D => \data_temp_5[96]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[96]_net_1\); - - \data_temp_RNO_0[87]\ : MX2C - port map(A => \data_temp[119]_net_1\, B => - \data_selected[119]\, S => \state[4]_net_1\, Y => N_688); - - \data_temp[115]\ : DFN1C0 - port map(D => \data_temp_5[115]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[115]_net_1\); - - \data_temp_RNO_3[100]\ : MX2C - port map(A => data_f0_out(132), B => data_f1_out(132), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_788); - - \data[14]\ : DFN1C0 - port map(D => \data_5[14]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(14)); - - \data_temp_RNO_2[97]\ : MX2C - port map(A => data_f2_out(129), B => data_f3_out(129), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1722); - - \data_temp_RNO_0[123]\ : AO1D - port map(A => N_1680, B => N_912_i, C => N_910, Y => - \data_temp_5_i_0[123]\); - - \data_temp_RNO[71]\ : NOR2A - port map(A => N_863_2, B => N_672, Y => \data_temp_5[71]\); - - \data_temp[43]\ : DFN1C0 - port map(D => N_239, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[43]_net_1\); - - \data_temp_RNO_0[46]\ : MX2C - port map(A => \data_temp[78]_net_1\, B => - \data_selected[78]\, S => \state[4]_net_1\, Y => N_647); - - \data_temp_RNO_1[60]\ : MX2C - port map(A => N_743, B => N_832, S => N_1580_2, Y => - \data_selected[92]\); - - \data_temp_RNO_1[121]\ : MX2C - port map(A => N_1690, B => N_1678, S => N_1580, Y => - \data_selected[153]\); - - \data_temp_RNO_2[36]\ : MX2 - port map(A => data_f0_out(68), B => data_f1_out(68), S => - \data_valid_and_ready[0]_net_1\, Y => N_850); - - \data_temp_RNO[72]\ : NOR2A - port map(A => N_863_2, B => N_673, Y => \data_temp_5[72]\); - - \data_temp_RNO[116]\ : NOR2A - port map(A => N_863_2, B => N_717, Y => \data_temp_5[116]\); - - \data_temp_RNO_0[90]\ : MX2C - port map(A => \data_temp[122]_net_1\, B => - \data_selected[122]\, S => \state[4]_net_1\, Y => N_691); - - \data_RNO[24]\ : NOR2A - port map(A => \data_temp[24]_net_1\, B => \state[4]_net_1\, - Y => \data_5[24]\); - - \data_temp_RNO_1[109]\ : MX2C - port map(A => N_1706, B => N_783, S => N_1580, Y => - \data_selected[141]\); - - \data_temp_RNO[90]\ : NOR2A - port map(A => N_863, B => N_691, Y => \data_temp_5[90]\); - - \data_temp_RNO[48]\ : NOR2A - port map(A => N_863_1, B => N_649, Y => \data_temp_5[48]\); - - \data_temp_RNO_1[108]\ : MX2C - port map(A => N_1705, B => N_782, S => N_1580_2, Y => - \data_selected[140]\); - - \data_temp[72]\ : DFN1C0 - port map(D => \data_temp_5[72]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[72]_net_1\); - - \data_temp_RNO_2[111]\ : MX2C - port map(A => data_f2_out(143), B => data_f3_out(143), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1708); - - \data_temp_RNO[5]\ : NOR2A - port map(A => \data_temp[37]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[5]\); - - \data_temp_RNO_4[43]\ : MX2 - port map(A => data_f2_out(75), B => data_f3_out(75), S => - \data_valid_and_ready[2]_net_1\, Y => N_768); - - \data_temp_RNO[55]\ : NOR2A - port map(A => N_863_1, B => N_656, Y => \data_temp_5[55]\); - - \data_temp_RNO_0[67]\ : MX2C - port map(A => \data_temp[99]_net_1\, B => - \data_selected[99]\, S => \state[4]_net_1\, Y => N_668); - - \data_temp_RNO_0[43]\ : AO1D - port map(A => N_912_i, B => N_843, C => N_897, Y => - \data_temp_5_i_0[43]\); - - \data_temp[38]\ : DFN1C0 - port map(D => N_229, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[38]_net_1\); - - \data_RNO[20]\ : NOR2A - port map(A => \data_temp[20]_net_1\, B => \state[4]_net_1\, - Y => \data_5[20]\); - - \data_temp_RNO[85]\ : NOR2A - port map(A => N_863_2, B => N_686, Y => \data_temp_5[85]\); - - \data_temp_RNO[7]\ : NOR2A - port map(A => \data_temp[39]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[7]\); - - \data_temp_RNO[43]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[43]\, C => - N_898, Y => N_239); - - \data_temp[103]\ : DFN1C0 - port map(D => \data_temp_5[103]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[103]_net_1\); - - \data[10]\ : DFN1C0 - port map(D => \data_5[10]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(10)); - - \data_temp_RNO_2[33]\ : MX2 - port map(A => data_f0_out(65), B => data_f1_out(65), S => - \data_valid_and_ready_0[0]_net_1\, Y => N_770); - - \data_temp_RNO_3[58]\ : MX2C - port map(A => data_f0_out(90), B => data_f1_out(90), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_830); - - \data_temp_RNO_3[68]\ : MX2C - port map(A => data_f0_out(100), B => data_f1_out(100), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_826); - - \data_temp_RNO_0[102]\ : MX2C - port map(A => \data_temp[102]_net_1\, B => - \data_selected[134]\, S => \state[4]_net_1\, Y => N_703); - - \state[4]\ : DFN1P0 - port map(D => N_861, CLK => HCLK_c, PRE => HRESETn_c, Q => - \state_0[4]\); - - \data_temp_RNO_3[88]\ : MX2C - port map(A => data_f0_out(120), B => data_f1_out(120), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_804); - - \data_temp_RNO[74]\ : NOR2A - port map(A => N_863_2, B => N_675, Y => \data_temp_5[74]\); - - \data_temp_RNO_2[59]\ : MX2C - port map(A => data_f2_out(91), B => data_f3_out(91), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_742); - - \data_temp_RNO_2[51]\ : MX2C - port map(A => data_f2_out(83), B => data_f3_out(83), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_748); - - \data_temp_RNO_0[109]\ : MX2C - port map(A => \data_temp[109]_net_1\, B => - \data_selected[141]\, S => \state[4]_net_1\, Y => N_710); - - \data_temp_RNO_3[113]\ : MX2C - port map(A => data_f0_out(145), B => data_f1_out(145), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_773); - - \data_temp_RNO_1[62]\ : MX2C - port map(A => N_745, B => N_820, S => N_1580_2, Y => - \data_selected[94]\); - - \data_temp_RNO_1[114]\ : MX2C - port map(A => N_1697, B => N_774, S => N_1580_3, Y => - \data_selected[146]\); - - \data_temp_RNO_0[92]\ : AO1D - port map(A => N_912_i, B => N_794, C => N_900, Y => - \data_temp_5_i_0[92]\); - - \data_valid_and_ready[3]\ : NOR2B - port map(A => valid_out_3, B => ready_i_0(3), Y => - \data_valid_and_ready[3]_net_1\); - - \data_temp[37]\ : DFN1C0 - port map(D => N_227, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[37]_net_1\); - - \data_temp[71]\ : DFN1C0 - port map(D => \data_temp_5[71]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[71]_net_1\); - - \data_temp_RNO_3[70]\ : MX2C - port map(A => data_f0_out(102), B => data_f1_out(102), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_814); - - \data_temp_RNO_0[39]\ : AO1D - port map(A => N_912_i, B => N_853, C => N_1659, Y => - \data_temp_5_i_0[39]\); - - \state_RNIR1JC[3]\ : NOR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => N_929); - - \data_temp[25]\ : DFN1C0 - port map(D => \data_temp_5[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[25]_net_1\); - - \data_temp_RNO[9]\ : NOR2A - port map(A => \data_temp[41]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[9]\); - - \data_RNO[25]\ : NOR2A - port map(A => \data_temp[25]_net_1\, B => \state[4]_net_1\, - Y => \data_5[25]\); - - \data_temp_RNO_0[70]\ : MX2C - port map(A => \data_temp[102]_net_1\, B => - \data_selected[102]\, S => \state[4]_net_1\, Y => N_671); - - \data_temp[55]\ : DFN1C0 - port map(D => \data_temp_5[55]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[55]_net_1\); - - \data_temp_RNO_1[77]\ : MX2C - port map(A => N_732, B => N_807, S => N_1580, Y => - \data_selected[109]\); - - \data_temp_RNO_2[88]\ : MX2C - port map(A => data_f2_out(120), B => data_f3_out(120), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1727); - - \data_temp_RNO_2[113]\ : MX2C - port map(A => data_f2_out(145), B => data_f3_out(145), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1710); - - \data_temp_RNO_3[38]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[70]_net_1\, - Y => N_1656); - - \data_temp[40]\ : DFN1C0 - port map(D => N_233, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[40]_net_1\); - - \data_temp_RNO[120]\ : NOR2A - port map(A => N_863, B => N_721, Y => \data_temp_5[120]\); - - \data_temp_RNO_1[87]\ : MX2C - port map(A => N_1726, B => N_803, S => N_1580_3, Y => - \data_selected[119]\); - - \data_temp[12]\ : DFN1C0 - port map(D => \data_temp_5[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[12]_net_1\); - - \data_temp_RNO_2[55]\ : MX2C - port map(A => data_f2_out(87), B => data_f3_out(87), S => - \data_valid_and_ready[2]_net_1\, Y => N_752); - - \data_temp_RNO_3[72]\ : MX2C - port map(A => data_f0_out(104), B => data_f1_out(104), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_816); - - \data_wen[1]\ : DFN1E0P0 - port map(D => \data_wen_3[1]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => data_wen(1)); - - \data_temp_RNO[19]\ : NOR2A - port map(A => \data_temp[51]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[19]\); - - \data_temp[94]\ : DFN1C0 - port map(D => \data_temp_5[94]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[94]_net_1\); - - \data_temp[78]\ : DFN1C0 - port map(D => \data_temp_5[78]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[78]_net_1\); - - \data_temp_RNO_2[68]\ : MX2C - port map(A => data_f2_out(100), B => data_f3_out(100), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_737); - - \data_temp_RNO_3[101]\ : MX2C - port map(A => data_f0_out(133), B => data_f1_out(133), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_789); - - \data_temp_RNO_2[54]\ : MX2C - port map(A => data_f2_out(86), B => data_f3_out(86), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_751); - - \data_temp_RNO_1[97]\ : MX2C - port map(A => N_1722, B => N_785, S => N_1580, Y => - \data_selected[129]\); - - \data_temp_RNO_0[72]\ : MX2C - port map(A => \data_temp[104]_net_1\, B => - \data_selected[104]\, S => \state[4]_net_1\, Y => N_673); - - \data_temp_RNO_0[35]\ : AO1D - port map(A => N_912_i, B => N_849, C => N_873, Y => - \data_temp_5_i_0[35]\); - - \data_RNO[7]\ : NOR2A - port map(A => \data_temp[7]_net_1\, B => \state[4]_net_1\, - Y => \data_5[7]\); - - \data_temp_RNO[31]\ : NOR2A - port map(A => \data_temp[63]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[31]\); - - \data_temp_RNO_0[108]\ : MX2C - port map(A => \data_temp[108]_net_1\, B => - \data_selected[140]\, S => \state[4]_net_1\, Y => N_709); - - \data[27]\ : DFN1C0 - port map(D => \data_5[27]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(27)); - - \data_temp_RNICJBC[123]\ : OR2 - port map(A => \state[4]_net_1\, B => \data_temp[123]_net_1\, - Y => N_913); - - \data_temp[5]\ : DFN1C0 - port map(D => \data_temp_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[5]_net_1\); - - \data_temp_RNO[32]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[32]\, C => - N_865, Y => N_215); - - \data_temp_RNO[16]\ : NOR2A - port map(A => \data_temp[48]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[16]\); - - \data_temp_RNO_0[34]\ : AO1D - port map(A => N_912_i, B => N_848, C => N_870, Y => - \data_temp_5_i_0[34]\); - - \data_temp_RNO[100]\ : NOR2A - port map(A => N_863, B => N_701, Y => \data_temp_5[100]\); - - \state[1]\ : DFN1C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - \data_temp[102]\ : DFN1C0 - port map(D => \data_temp_5[102]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[102]_net_1\); - - \data_temp_RNO_1[56]\ : MX2C - port map(A => N_753, B => N_828, S => N_1580_1, Y => - \data_selected[88]\); - - \data_temp[77]\ : DFN1C0 - port map(D => \data_temp_5[77]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[77]_net_1\); - - \data_temp[11]\ : DFN1C0 - port map(D => \data_temp_5[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[11]_net_1\); - - \data_temp[89]\ : DFN1C0 - port map(D => \data_temp_5[89]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[89]_net_1\); - - \data_RNO[0]\ : NOR2A - port map(A => \data_temp[0]_net_1\, B => \state[4]_net_1\, - Y => \data_5[0]\); - - \data_temp_RNO_4[32]\ : MX2 - port map(A => data_f2_out(64), B => data_f3_out(64), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1685); - - \data_temp_RNO[118]\ : NOR2A - port map(A => N_863, B => N_719, Y => \data_temp_5[118]\); - - \data_temp_RNO_2[76]\ : MX2C - port map(A => data_f2_out(108), B => data_f3_out(108), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_731); - - \data_temp_RNO_0[80]\ : MX2C - port map(A => \data_temp[112]_net_1\, B => - \data_selected[112]\, S => \state[4]_net_1\, Y => N_681); - - \data_temp_RNO_1[105]\ : MX2C - port map(A => N_1716, B => N_779, S => N_1580_3, Y => - \data_selected[137]\); - - \data_temp[35]\ : DFN1C0 - port map(D => N_223, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[35]_net_1\); - - \data_temp_RNO_2[90]\ : MX2C - port map(A => data_f2_out(122), B => data_f3_out(122), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1729); - - \data_temp_RNO_2[114]\ : MX2C - port map(A => data_f2_out(146), B => data_f3_out(146), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1697); - - data_selected_sn_m2_0_o2_1 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_1); - - \data_temp_RNO_2[46]\ : MX2C - port map(A => data_f2_out(78), B => data_f3_out(78), S => - \data_valid_and_ready[2]_net_1\, Y => N_757); - - \data_valid_and_ready_2[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready_2[0]_net_1\); - - \data_temp_RNO_1[53]\ : MX2C - port map(A => N_750, B => N_839, S => N_1580_1, Y => - \data_selected[85]\); - - \data_temp_RNO[34]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[34]\, C => - N_871, Y => N_221); - - \data_temp_RNO[0]\ : NOR2A - port map(A => \data_temp[32]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[0]\); - - \data_temp_RNO[41]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[41]\, C => - N_1666, Y => N_235); - - \data_temp_RNO_3[105]\ : MX2C - port map(A => data_f0_out(137), B => data_f1_out(137), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_779); - - \data[8]\ : DFN1C0 - port map(D => \data_5[8]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(8)); - - \data_temp_RNO_2[73]\ : MX2C - port map(A => data_f2_out(105), B => data_f3_out(105), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1740); - - state_0_sqmuxa_i_0_o2_0_a2 : NOR2 - port map(A => \data_valid_and_ready[3]_net_1\, B => N_916, - Y => N_1306); - - \data_temp_RNO_2[108]\ : MX2C - port map(A => data_f2_out(140), B => data_f3_out(140), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1705); - - \data_temp_RNO[60]\ : NOR2A - port map(A => N_863_1, B => N_661, Y => \data_temp_5[60]\); - - \data_temp_RNO_1[106]\ : MX2C - port map(A => N_1717, B => N_780, S => N_1580_2, Y => - \data_selected[138]\); - - \data_temp_RNO[42]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[42]\, C => - N_1669, Y => N_237); - - \data_temp_RNO_2[43]\ : MX2 - port map(A => data_f0_out(75), B => data_f1_out(75), S => - \data_valid_and_ready[0]_net_1\, Y => N_843); - - \data_RNO[4]\ : NOR2A - port map(A => \data_temp[4]_net_1\, B => \state[4]_net_1\, - Y => \data_5[4]\); - - \data_temp_RNO_3[57]\ : MX2C - port map(A => data_f0_out(89), B => data_f1_out(89), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_829); - - \data_temp_RNO[126]\ : NOR2A - port map(A => N_863_1, B => N_727, Y => \data_temp_5[126]\); - - \data_temp_RNO_0[60]\ : MX2C - port map(A => \data_temp[92]_net_1\, B => - \data_selected[92]\, S => \state[4]_net_1\, Y => N_661); - - \data_temp_RNO_3[67]\ : MX2C - port map(A => data_f0_out(99), B => data_f1_out(99), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_825); - - \data_temp_RNO_2[117]\ : MX2C - port map(A => data_f2_out(149), B => data_f3_out(149), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1700); - - \data_temp_RNO_3[87]\ : MX2C - port map(A => data_f0_out(119), B => data_f1_out(119), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_803); - - \data_temp_RNO[58]\ : NOR2A - port map(A => N_863_1, B => N_659, Y => \data_temp_5[58]\); - - \data_temp[2]\ : DFN1C0 - port map(D => \data_temp_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[2]_net_1\); - - \data_temp_RNO[29]\ : NOR2A - port map(A => \data_temp[61]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[29]\); - - \data_temp[18]\ : DFN1C0 - port map(D => \data_temp_5[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[18]_net_1\); - - \data_temp_RNO_0[82]\ : MX2C - port map(A => \data_temp[114]_net_1\, B => - \data_selected[114]\, S => \state[4]_net_1\, Y => N_683); - - \data_temp_RNO[88]\ : NOR2A - port map(A => N_863, B => N_689, Y => \data_temp_5[88]\); - - \data_temp_RNO_2[92]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1731, - Y => N_900); - - \data_temp_RNO[8]\ : NOR2A - port map(A => \data_temp[40]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[8]\); - - \data_temp[101]\ : DFN1C0 - port map(D => \data_temp_5[101]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[101]_net_1\); - - \data_temp_RNO_2[101]\ : MX2C - port map(A => data_f2_out(133), B => data_f3_out(133), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1712); - - \data_temp_RNO[53]\ : NOR2A - port map(A => N_863_1, B => N_654, Y => \data_temp_5[53]\); - - \data_temp_RNO[44]\ : NOR2A - port map(A => N_863_0, B => N_645, Y => \data_temp_5[44]\); - - \data_temp_RNO[83]\ : NOR2A - port map(A => N_863_2, B => N_684, Y => \data_temp_5[83]\); - - \time_en_temp[0]\ : DFN1E0C0 - port map(D => \data_valid_and_ready[0]_net_1\, CLK => - HCLK_c, CLR => HRESETn_c, E => state_0_sqmuxa_i, Q => - \time_en_temp[0]_net_1\); - - \data_temp_RNO[26]\ : NOR2A - port map(A => \data_temp[58]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[26]\); - - \data_temp[126]\ : DFN1C0 - port map(D => \data_temp_5[126]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[126]_net_1\); - - \data_temp_RNO[106]\ : NOR2A - port map(A => N_863_2, B => N_707, Y => \data_temp_5[106]\); - - \data_temp[17]\ : DFN1C0 - port map(D => \data_temp_5[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[17]_net_1\); - - \data_temp[109]\ : DFN1C0 - port map(D => \data_temp_5[109]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[109]_net_1\); - - \data_temp_RNO_0[62]\ : MX2C - port map(A => \data_temp[94]_net_1\, B => - \data_selected[94]\, S => \state[4]_net_1\, Y => N_663); - - \data_RNO[23]\ : NOR2A - port map(A => \data_temp[23]_net_1\, B => \state[4]_net_1\, - Y => \data_5[23]\); - - \data[6]\ : DFN1C0 - port map(D => \data_5[6]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(6)); - - \data_temp_RNO[17]\ : NOR2A - port map(A => \data_temp[49]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[17]\); - - un23_data_selected_i_a2 : OR2A - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - N_1580_1, Y => N_916); - - \data_temp_RNO_2[87]\ : MX2C - port map(A => data_f2_out(119), B => data_f3_out(119), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1726); - - \data_temp_RNO[114]\ : NOR2A - port map(A => N_863_2, B => N_715, Y => \data_temp_5[114]\); - - \data_temp_RNO_3[103]\ : MX2C - port map(A => data_f0_out(135), B => data_f1_out(135), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_791); - - \data_temp_RNO_1[70]\ : MX2C - port map(A => N_739, B => N_814, S => N_1580_3, Y => - \data_selected[102]\); - - \data_temp[75]\ : DFN1C0 - port map(D => \data_temp_5[75]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[75]_net_1\); - - \data_temp_RNO_3[37]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[69]_net_1\, - Y => N_1653); - - \data_temp_RNO_1[38]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_763, - Y => N_1657); - - \data_temp_RNO_1[104]\ : MX2C - port map(A => N_1715, B => N_778, S => N_1580_3, Y => - \data_selected[136]\); - - \state_RNIKK3V21_0[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \data_temp_5_i_a2_0_0[32]_net_1\, C => N_1580_0, Y => - N_863_1); - - \data_temp[46]\ : DFN1C0 - port map(D => \data_temp_5[46]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[46]_net_1\); - - \data_temp_RNO[111]\ : NOR2A - port map(A => N_863_2, B => N_712, Y => \data_temp_5[111]\); - - \data_temp_RNO_2[110]\ : MX2C - port map(A => data_f2_out(142), B => data_f3_out(142), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1707); - - \data_temp[69]\ : DFN1C0 - port map(D => \data_temp_5[69]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[69]_net_1\); - - \data_temp_RNO_1[80]\ : MX2C - port map(A => N_1733, B => N_810, S => N_1580_2, Y => - \data_selected[112]\); - - \data_temp_RNO_2[67]\ : MX2C - port map(A => data_f2_out(99), B => data_f3_out(99), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_736); - - \data_RNO[27]\ : NOR2A - port map(A => \data_temp[27]_net_1\, B => \state[4]_net_1\, - Y => \data_5[27]\); - - \data_temp_RNO[6]\ : NOR2A - port map(A => \data_temp[38]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[6]\); - - \data_temp_RNO_0[126]\ : MX2C - port map(A => \data_temp[126]_net_1\, B => - \data_selected[158]\, S => \state[4]_net_1\, Y => N_727); - - \data_temp_RNO_1[90]\ : MX2C - port map(A => N_1729, B => N_792, S => N_1580, Y => - \data_selected[122]\); - - \data[23]\ : DFN1C0 - port map(D => \data_5[23]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(23)); - - \data_temp_RNO_2[103]\ : MX2C - port map(A => data_f2_out(135), B => data_f3_out(135), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1714); - - \state_RNIKK3V21[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \data_temp_5_i_a2_0_0[32]_net_1\, C => N_1580_0, Y => - N_863_0); - - \data_temp_RNO_1[72]\ : MX2C - port map(A => N_1739, B => N_816, S => N_1580_3, Y => - \data_selected[104]\); - - \data_temp_RNO_0[58]\ : MX2C - port map(A => \data_temp[90]_net_1\, B => - \data_selected[90]\, S => \state[4]_net_1\, Y => N_659); - - \data_temp_RNO_1[117]\ : MX2C - port map(A => N_1700, B => N_777, S => N_1580_3, Y => - \data_selected[149]\); - - \data_temp[4]\ : DFN1C0 - port map(D => \data_temp_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[4]_net_1\); - - \data_wen_RNO[2]\ : OR2 - port map(A => \time_en_temp[2]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[2]\); - - \data_temp_RNO_3[48]\ : MX2C - port map(A => data_f0_out(80), B => data_f1_out(80), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_834); - - \data_temp[92]\ : DFN1C0 - port map(D => N_241, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[92]_net_1\); - - \data_temp_RNO_2[56]\ : MX2C - port map(A => data_f2_out(88), B => data_f3_out(88), S => - \data_valid_and_ready[2]_net_1\, Y => N_753); - - \state_RNIKK3V21_2[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \data_temp_5_i_a2_0_0[32]_net_1\, C => N_1580_0, Y => - N_863); - - \data_temp_RNO[70]\ : NOR2A - port map(A => N_863_2, B => N_671, Y => \data_temp_5[70]\); - - \data_temp_RNO_1[82]\ : MX2C - port map(A => N_1735, B => N_812, S => N_1580_3, Y => - \data_selected[114]\); - - \data_RNO[18]\ : NOR2A - port map(A => \data_temp[18]_net_1\, B => \state[4]_net_1\, - Y => \data_5[18]\); - - \time_wen[0]\ : DFN1E0P0 - port map(D => \time_wen_3[0]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => time_wen(0)); - - \data_temp_RNO_1[120]\ : MX2C - port map(A => N_1703, B => N_1677, S => N_1580, Y => - \data_selected[152]\); - - \data_temp_RNO_0[36]\ : AO1D - port map(A => N_912_i, B => N_850, C => N_1650, Y => - \data_temp_5_i_0[36]\); - - \data_temp_RNO_2[53]\ : MX2C - port map(A => data_f2_out(85), B => data_f3_out(85), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_750); - - \data_temp_RNO_1[69]\ : MX2C - port map(A => N_738, B => N_813, S => N_1580_3, Y => - \data_selected[101]\); - - \data_temp_RNO_1[61]\ : MX2C - port map(A => N_744, B => N_833, S => N_1580_2, Y => - \data_selected[93]\); - - \state[0]\ : DFN1C0 - port map(D => \state[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[0]_net_1\); - - \data_temp_RNO[27]\ : NOR2A - port map(A => \data_temp[59]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[27]\); - - \data_temp_RNO_1[92]\ : MX2 - port map(A => data_f0_out(124), B => data_f1_out(124), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_794); - - \data_temp_RNO_0[99]\ : MX2C - port map(A => \data_temp[99]_net_1\, B => - \data_selected[131]\, S => \state[4]_net_1\, Y => N_700); - - \data_temp_RNO_0[91]\ : AO1D - port map(A => N_912_i, B => N_793, C => N_908, Y => - \data_temp_5_i_0[91]\); - - \data_temp[15]\ : DFN1C0 - port map(D => \data_temp_5[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[15]_net_1\); - - \data_temp_RNO[119]\ : NOR2A - port map(A => N_863, B => N_720, Y => \data_temp_5[119]\); - - \data_RNO[1]\ : NOR2A - port map(A => \data_temp[1]_net_1\, B => \state[4]_net_1\, - Y => \data_5[1]\); - - \data_temp_RNO_3[117]\ : MX2C - port map(A => data_f0_out(149), B => data_f1_out(149), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_777); - - \data_temp_RNO_0[33]\ : AO1D - port map(A => N_912_i, B => N_770, C => N_867, Y => - \data_temp_5_i_0[33]\); - - \data_temp[91]\ : DFN1C0 - port map(D => N_249, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[91]_net_1\); - - \data_temp_RNO_0[125]\ : AO1D - port map(A => N_1682, B => N_912_i, C => N_906, Y => - \data_temp_5_i_0[125]\); - - \data_temp_RNO_0[110]\ : MX2C - port map(A => \data_temp[110]_net_1\, B => - \data_selected[142]\, S => \state[4]_net_1\, Y => N_711); - - \data_temp_RNO_1[48]\ : MX2C - port map(A => N_759, B => N_834, S => N_1580_1, Y => - \data_selected[80]\); - - \data_temp_RNO[15]\ : NOR2A - port map(A => \data_temp[47]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[15]\); - - \data[18]\ : DFN1C0 - port map(D => \data_5[18]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(18)); - - \data_temp[29]\ : DFN1C0 - port map(D => \data_temp_5[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[29]_net_1\); - - \data_temp_RNO_3[50]\ : MX2C - port map(A => data_f0_out(82), B => data_f1_out(82), S => - \data_valid_and_ready[0]_net_1\, Y => N_836); - - \data_temp[110]\ : DFN1C0 - port map(D => \data_temp_5[110]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[110]_net_1\); - - data_selected_sn_m2_0_o2_0 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_0); - - \data_temp_RNO[51]\ : NOR2A - port map(A => N_863_1, B => N_652, Y => \data_temp_5[51]\); - - \data_temp_RNO[113]\ : NOR2A - port map(A => N_863_2, B => N_714, Y => \data_temp_5[113]\); - - \data_temp_RNO_3[60]\ : MX2C - port map(A => data_f0_out(92), B => data_f1_out(92), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_832); - - \data_temp[123]\ : DFN1C0 - port map(D => N_251, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[123]_net_1\); - - \data_temp_RNO_3[80]\ : MX2C - port map(A => data_f0_out(112), B => data_f1_out(112), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_810); - - \data_temp_RNO_2[104]\ : MX2C - port map(A => data_f2_out(136), B => data_f3_out(136), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1715); - - \data_temp_RNO[81]\ : NOR2A - port map(A => N_863_2, B => N_682, Y => \data_temp_5[81]\); - - \data_temp_RNO[1]\ : NOR2A - port map(A => \data_temp[33]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[1]\); - - \data_temp[59]\ : DFN1C0 - port map(D => \data_temp_5[59]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[59]_net_1\); - - \data_temp_RNO[52]\ : NOR2A - port map(A => N_863_1, B => N_653, Y => \data_temp_5[52]\); - - \data_temp_RNO[82]\ : NOR2A - port map(A => N_863_2, B => N_683, Y => \data_temp_5[82]\); - - \data_temp_RNO[108]\ : NOR2A - port map(A => N_863_1, B => N_709, Y => \data_temp_5[108]\); - - \data_temp_RNO_3[112]\ : MX2C - port map(A => data_f0_out(144), B => data_f1_out(144), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_772); - - \data_temp_RNO_3[79]\ : MX2C - port map(A => data_f0_out(111), B => data_f1_out(111), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_809); - - \data_temp_RNO_3[71]\ : MX2C - port map(A => data_f0_out(103), B => data_f1_out(103), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_815); - - \data_temp[44]\ : DFN1C0 - port map(D => \data_temp_5[44]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[44]_net_1\); - - \data_temp_RNO_1[65]\ : MX2C - port map(A => N_734, B => N_823, S => N_1580, Y => - \data_selected[97]\); - - \data_temp_RNO_2[107]\ : MX2C - port map(A => data_f2_out(139), B => data_f3_out(139), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1704); - - \data_temp_RNO_3[98]\ : MX2C - port map(A => data_f0_out(130), B => data_f1_out(130), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_786); - - \data_temp_RNO_0[95]\ : MX2C - port map(A => \data_temp[127]_net_1\, B => - \data_selected[127]\, S => \state[4]_net_1\, Y => N_696); - - \data_temp_RNO_0[79]\ : MX2C - port map(A => \data_temp[111]_net_1\, B => - \data_selected[111]\, S => \state[4]_net_1\, Y => N_680); - - \data_temp_RNO_0[71]\ : MX2C - port map(A => \data_temp[103]_net_1\, B => - \data_selected[103]\, S => \state[4]_net_1\, Y => N_672); - - \data_valid_ack_RNO[3]\ : INV - port map(A => N_860, Y => N_860_i); - - \data_temp_RNO_3[52]\ : MX2C - port map(A => data_f0_out(84), B => data_f1_out(84), S => - \data_valid_and_ready[0]_net_1\, Y => N_838); - - \data_temp[98]\ : DFN1C0 - port map(D => \data_temp_5[98]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[98]_net_1\); - - \data_temp_RNO[54]\ : NOR2A - port map(A => N_863_1, B => N_655, Y => \data_temp_5[54]\); - - \data_valid_and_ready_1[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready_1[0]_net_1\); - - \data_temp_RNO_3[62]\ : MX2C - port map(A => data_f0_out(94), B => data_f1_out(94), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_820); - - \data_temp_RNO_1[37]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_762, - Y => N_1654); - - \data_temp_RNO_3[82]\ : MX2C - port map(A => data_f0_out(114), B => data_f1_out(114), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_812); - - \data_temp_RNO_1[64]\ : MX2C - port map(A => N_747, B => N_822, S => N_1580, Y => - \data_selected[96]\); - - \data_temp_RNO[84]\ : NOR2A - port map(A => N_863_2, B => N_685, Y => \data_temp_5[84]\); - - \data_temp_RNO_2[80]\ : MX2C - port map(A => data_f2_out(112), B => data_f3_out(112), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1733); - - \data_temp_RNO_0[94]\ : MX2C - port map(A => \data_temp[126]_net_1\, B => - \data_selected[126]\, S => \state[4]_net_1\, Y => N_695); - - \data_temp_RNO_0[127]\ : MX2C - port map(A => \data_temp[127]_net_1\, B => - \data_selected[159]\, S => \state[4]_net_1\, Y => N_728); - - \data_temp[83]\ : DFN1C0 - port map(D => \data_temp_5[83]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[83]_net_1\); - - \data_temp_RNO_3[116]\ : MX2C - port map(A => data_f0_out(148), B => data_f1_out(148), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_776); - - \data[4]\ : DFN1C0 - port map(D => \data_5[4]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(4)); - - \data[11]\ : DFN1C0 - port map(D => \data_5[11]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(11)); - - \data_temp_RNO[124]\ : NOR3B - port map(A => N_863_0, B => N_915, C => - \data_temp_5_i_0[124]\, Y => N_245); - - \data_valid_and_ready_3[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready_3[0]_net_1\); - - \data_RNO[21]\ : NOR2A - port map(A => \data_temp[21]_net_1\, B => \state[4]_net_1\, - Y => \data_5[21]\); - - \data_temp_RNO_4[39]\ : MX2 - port map(A => data_f2_out(71), B => data_f3_out(71), S => - \data_valid_and_ready[2]_net_1\, Y => N_764); - - \data_temp[97]\ : DFN1C0 - port map(D => \data_temp_5[97]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[97]_net_1\); - - \state_RNIKK3V21_4[4]\ : OR2A - port map(A => \state[4]_net_1\, B => N_1306, Y => - state_0_sqmuxa_i); - - \data_RNO[22]\ : NOR2A - port map(A => \data_temp[22]_net_1\, B => \state[4]_net_1\, - Y => \data_5[22]\); - - \data_temp_RNO_2[60]\ : MX2C - port map(A => data_f2_out(92), B => data_f3_out(92), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_743); - - \data_temp_RNO[30]\ : NOR2A - port map(A => \data_temp[62]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[30]\); - - \data_temp_RNO[25]\ : NOR2A - port map(A => \data_temp[57]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[25]\); - - \data_temp_RNO[121]\ : NOR2A - port map(A => N_863, B => N_722, Y => \data_temp_5[121]\); - - \time_en_temp[3]\ : DFN1E0C0 - port map(D => N_916, CLK => HCLK_c, CLR => HRESETn_c, E => - state_0_sqmuxa_i, Q => \time_en_temp[3]_net_1\); - - \data_temp_RNO_3[75]\ : MX2C - port map(A => data_f0_out(107), B => data_f1_out(107), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_819); - - \data_temp_RNO_3[124]\ : MX2 - port map(A => data_f2_out(156), B => data_f3_out(156), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1693); - - \data_temp_RNO_0[57]\ : MX2C - port map(A => \data_temp[89]_net_1\, B => - \data_selected[89]\, S => \state[4]_net_1\, Y => N_658); - - \data_temp[39]\ : DFN1C0 - port map(D => N_231, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[39]_net_1\); - - \data_temp_RNO_3[47]\ : MX2C - port map(A => data_f0_out(79), B => data_f1_out(79), S => - \data_valid_and_ready[0]_net_1\, Y => N_847); - - \data_temp_RNO_1[113]\ : MX2C - port map(A => N_1710, B => N_773, S => N_1580_2, Y => - \data_selected[145]\); - - \data_temp_RNO_2[82]\ : MX2C - port map(A => data_f2_out(114), B => data_f3_out(114), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1735); - - \data_temp_RNO_0[75]\ : MX2C - port map(A => \data_temp[107]_net_1\, B => - \data_selected[107]\, S => \state[4]_net_1\, Y => N_676); - - \data_temp_RNO_3[32]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[64]_net_1\, - Y => N_864); - - \data_temp_RNO_3[74]\ : MX2C - port map(A => data_f0_out(106), B => data_f1_out(106), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_818); - - \data_temp_RNO_2[100]\ : MX2C - port map(A => data_f2_out(132), B => data_f3_out(132), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1711); - - \data_temp_RNO_2[112]\ : MX2C - port map(A => data_f2_out(144), B => data_f3_out(144), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1709); - - \data_temp_RNO_0[48]\ : MX2C - port map(A => \data_temp[80]_net_1\, B => - \data_selected[80]\, S => \state[4]_net_1\, Y => N_649); - - \data_temp_RNO_2[115]\ : MX2C - port map(A => data_f2_out(147), B => data_f3_out(147), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1698); - - \data_temp_RNO[104]\ : NOR2A - port map(A => N_863_2, B => N_705, Y => \data_temp_5[104]\); - - \data_temp_RNO_2[38]\ : MX2 - port map(A => data_f0_out(70), B => data_f1_out(70), S => - \data_valid_and_ready[0]_net_1\, Y => N_852); - - \data_temp[122]\ : DFN1C0 - port map(D => \data_temp_5[122]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[122]_net_1\); - - \data_temp[8]\ : DFN1C0 - port map(D => \data_temp_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[8]_net_1\); - - \data[26]\ : DFN1C0 - port map(D => \data_5[26]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(26)); - - \data_temp_RNO_0[74]\ : MX2C - port map(A => \data_temp[106]_net_1\, B => - \data_selected[106]\, S => \state[4]_net_1\, Y => N_675); - - \data_temp_RNO_1[122]\ : MX2C - port map(A => N_1691, B => N_1679, S => N_1580, Y => - \data_selected[154]\); - - \data_temp_RNO_0[89]\ : MX2C - port map(A => \data_temp[121]_net_1\, B => - \data_selected[121]\, S => \state[4]_net_1\, Y => N_690); - - \data_temp_RNO_0[81]\ : MX2C - port map(A => \data_temp[113]_net_1\, B => - \data_selected[113]\, S => \state[4]_net_1\, Y => N_682); - - \data_temp_RNO[101]\ : NOR2A - port map(A => N_863, B => N_702, Y => \data_temp_5[101]\); - - \data_temp_RNO_2[99]\ : MX2C - port map(A => data_f2_out(131), B => data_f3_out(131), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1724); - - \data_temp_RNO_2[91]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1730, - Y => N_908); - - \data_temp_RNO_2[62]\ : MX2C - port map(A => data_f2_out(94), B => data_f3_out(94), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_745); - - \data_temp_RNO_3[119]\ : MX2C - port map(A => data_f0_out(151), B => data_f1_out(151), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1676); - - \data_temp_RNO[40]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[40]\, C => - N_1663, Y => N_233); - - \data_temp_RNO[99]\ : NOR2A - port map(A => N_863, B => N_700, Y => \data_temp_5[99]\); - - \data_temp_RNO_4[35]\ : MX2 - port map(A => data_f2_out(67), B => data_f3_out(67), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1688); - - \data[12]\ : DFN1C0 - port map(D => \data_5[12]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(12)); - - \data_temp_RNO_1[107]\ : MX2C - port map(A => N_1704, B => N_781, S => N_1580_2, Y => - \data_selected[139]\); - - \data_temp[104]\ : DFN1C0 - port map(D => \data_temp_5[104]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[104]_net_1\); - - \data_temp_RNO_3[120]\ : MX2C - port map(A => data_f0_out(152), B => data_f1_out(152), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1677); - - \data_temp_RNO_1[47]\ : MX2C - port map(A => N_758, B => N_847, S => N_1580_1, Y => - \data_selected[79]\); - - \data_temp_RNO_4[34]\ : MX2 - port map(A => data_f2_out(66), B => data_f3_out(66), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1687); - - \data_temp_RNO_0[69]\ : MX2C - port map(A => \data_temp[101]_net_1\, B => - \data_selected[101]\, S => \state[4]_net_1\, Y => N_670); - - \data_temp_RNO_0[61]\ : MX2C - port map(A => \data_temp[93]_net_1\, B => - \data_selected[93]\, S => \state[4]_net_1\, Y => N_662); - - \data_temp_RNO[96]\ : NOR2A - port map(A => N_863, B => N_697, Y => \data_temp_5[96]\); - - \data_temp[107]\ : DFN1C0 - port map(D => \data_temp_5[107]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[107]_net_1\); - - \data_temp[80]\ : DFN1C0 - port map(D => \data_temp_5[80]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[80]_net_1\); - - \data_temp_RNO_2[116]\ : MX2C - port map(A => data_f2_out(148), B => data_f3_out(148), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1699); - - \data_temp_RNO[18]\ : NOR2A - port map(A => \data_temp[50]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[18]\); - - \data_temp[95]\ : DFN1C0 - port map(D => \data_temp_5[95]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[95]_net_1\); - - \data_temp[63]\ : DFN1C0 - port map(D => \data_temp_5[63]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[63]_net_1\); - - \state_RNI8220I[4]\ : OR2B - port map(A => \state[4]_net_1\, B => N_1580_1, Y => N_912_i); - - \data_temp_RNO[123]\ : NOR3B - port map(A => N_863_0, B => N_913, C => - \data_temp_5_i_0[123]\, Y => N_251); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_temp_RNO_0[85]\ : MX2C - port map(A => \data_temp[117]_net_1\, B => - \data_selected[117]\, S => \state[4]_net_1\, Y => N_686); - - \data_temp[121]\ : DFN1C0 - port map(D => \data_temp_5[121]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[121]_net_1\); - - \data_temp[79]\ : DFN1C0 - port map(D => \data_temp_5[79]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[79]_net_1\); - - \data_temp_RNO_3[107]\ : MX2C - port map(A => data_f0_out(139), B => data_f1_out(139), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_781); - - \data[30]\ : DFN1C0 - port map(D => \data_5[30]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(30)); - - \data_temp_RNO_0[122]\ : MX2C - port map(A => \data_temp[122]_net_1\, B => - \data_selected[154]\, S => \state[4]_net_1\, Y => N_723); - - \data_temp_RNO_2[95]\ : MX2C - port map(A => data_f2_out(127), B => data_f3_out(127), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1720); - - \data_temp_RNO_0[100]\ : MX2C - port map(A => \data_temp[100]_net_1\, B => - \data_selected[132]\, S => \state[4]_net_1\, Y => N_701); - - \data_temp_RNO[13]\ : NOR2A - port map(A => \data_temp[45]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[13]\); - - \data_valid_and_ready[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready[0]_net_1\); - - \data_temp_RNO_3[97]\ : MX2C - port map(A => data_f0_out(129), B => data_f1_out(129), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_785); - - \data[19]\ : DFN1C0 - port map(D => \data_5[19]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(19)); - - \data_temp_RNO_0[84]\ : MX2C - port map(A => \data_temp[116]_net_1\, B => - \data_selected[116]\, S => \state[4]_net_1\, Y => N_685); - - \time_wen[2]\ : DFN1E0P0 - port map(D => N_859, CLK => HCLK_c, PRE => HRESETn_c, E => - N_928, Q => time_wen(2)); - - \data_temp[118]\ : DFN1C0 - port map(D => \data_temp_5[118]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[118]_net_1\); - - \data_temp_RNO[109]\ : NOR2A - port map(A => N_863, B => N_710, Y => \data_temp_5[109]\); - - \data_temp_RNO_2[94]\ : MX2C - port map(A => data_f2_out(126), B => data_f3_out(126), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1719); - - \data_temp_RNO_1[79]\ : MX2C - port map(A => N_1732, B => N_809, S => N_1580_2, Y => - \data_selected[111]\); - - \data_temp_RNO_1[71]\ : MX2C - port map(A => N_740, B => N_815, S => N_1580_3, Y => - \data_selected[103]\); - - \data_temp[105]\ : DFN1C0 - port map(D => \data_temp_5[105]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[105]_net_1\); - - \data_temp[42]\ : DFN1C0 - port map(D => N_237, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[42]_net_1\); - - \data_temp_RNO_0[65]\ : MX2C - port map(A => \data_temp[97]_net_1\, B => - \data_selected[97]\, S => \state[4]_net_1\, Y => N_666); - - \data_temp_RNO[103]\ : NOR2A - port map(A => N_863_2, B => N_704, Y => \data_temp_5[103]\); - - \data_temp_RNO_3[102]\ : MX2C - port map(A => data_f0_out(134), B => data_f1_out(134), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_790); - - \data_temp_RNO_0[114]\ : MX2C - port map(A => \data_temp[114]_net_1\, B => - \data_selected[146]\, S => \state[4]_net_1\, Y => N_715); - - \data[15]\ : DFN1C0 - port map(D => \data_5[15]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(15)); - - \data_temp_RNO_0[111]\ : MX2C - port map(A => \data_temp[111]_net_1\, B => - \data_selected[143]\, S => \state[4]_net_1\, Y => N_712); - - \data_RNO[26]\ : NOR2A - port map(A => \data_temp[26]_net_1\, B => \state[4]_net_1\, - Y => \data_5[26]\); - - \data_temp[1]\ : DFN1C0 - port map(D => \data_temp_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[1]_net_1\); - - \data_temp_RNO_1[66]\ : MX2C - port map(A => N_735, B => N_824, S => N_1580, Y => - \data_selected[98]\); - - \data_temp_RNO_1[89]\ : MX2C - port map(A => N_1728, B => N_805, S => N_1580, Y => - \data_selected[121]\); - - \data_temp_RNO_1[81]\ : MX2C - port map(A => N_1734, B => N_811, S => N_1580_2, Y => - \data_selected[113]\); - - \data_temp_RNO_0[64]\ : MX2C - port map(A => \data_temp[96]_net_1\, B => - \data_selected[96]\, S => \state[4]_net_1\, Y => N_665); - - \data_temp_RNO_0[96]\ : MX2C - port map(A => \data_temp[96]_net_1\, B => - \data_selected[128]\, S => \state[4]_net_1\, Y => N_697); - - \data_temp_RNO_1[58]\ : MX2C - port map(A => N_741, B => N_830, S => N_1580_2, Y => - \data_selected[90]\); - - \data_temp_RNO_1[99]\ : MX2C - port map(A => N_1724, B => N_787, S => N_1580, Y => - \data_selected[131]\); - - \data_temp_RNO_1[91]\ : MX2 - port map(A => data_f0_out(123), B => data_f1_out(123), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_793); - - \data_temp_RNO_1[63]\ : MX2C - port map(A => N_746, B => N_821, S => N_1580_2, Y => - \data_selected[95]\); - - \data_temp_RNO_3[106]\ : MX2C - port map(A => data_f0_out(138), B => data_f1_out(138), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_780); - - \data_temp_RNO[28]\ : NOR2A - port map(A => \data_temp[60]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[28]\); - - \data_temp_RNO_1[32]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1685, - Y => N_865); - - \data_temp[41]\ : DFN1C0 - port map(D => N_235, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[41]_net_1\); - - \data_temp_RNO_2[78]\ : MX2C - port map(A => data_f2_out(110), B => data_f3_out(110), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_733); - - \data_temp_RNO_0[93]\ : AO1D - port map(A => N_912_i, B => N_795, C => N_902, Y => - \data_temp_5_i_0[93]\); - - \data_temp_RNO_0[50]\ : MX2C - port map(A => \data_temp[82]_net_1\, B => - \data_selected[82]\, S => \state[4]_net_1\, Y => N_651); - - \data_temp_RNO[97]\ : NOR2A - port map(A => N_863, B => N_698, Y => \data_temp_5[97]\); - - \data_temp_RNO_0[47]\ : MX2C - port map(A => \data_temp[79]_net_1\, B => - \data_selected[79]\, S => \state[4]_net_1\, Y => N_648); - - \data_RNO[14]\ : NOR2A - port map(A => \data_temp[14]_net_1\, B => \state[4]_net_1\, - Y => \data_5[14]\); - - \data_temp_RNO_3[40]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[72]_net_1\, - Y => N_1662); - - \data_temp[23]\ : DFN1C0 - port map(D => \data_temp_5[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[23]_net_1\); - - \data_temp_RNO_3[121]\ : MX2C - port map(A => data_f0_out(153), B => data_f1_out(153), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1678); - - \data_temp_RNO_2[37]\ : MX2 - port map(A => data_f0_out(69), B => data_f1_out(69), S => - \data_valid_and_ready[0]_net_1\, Y => N_851); - - \data_temp[19]\ : DFN1C0 - port map(D => \data_temp_5[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[19]_net_1\); - - \data_temp_RNO_2[48]\ : MX2C - port map(A => data_f2_out(80), B => data_f3_out(80), S => - \data_valid_and_ready[2]_net_1\, Y => N_759); - - \data_temp_RNO_1[75]\ : MX2C - port map(A => N_730, B => N_819, S => N_1580_2, Y => - \data_selected[107]\); - - \data_valid_and_ready_0[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready_0[0]_net_1\); - - \data_temp_RNO[23]\ : NOR2A - port map(A => \data_temp[55]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[23]\); - - \data_RNO[10]\ : NOR2A - port map(A => \data_temp[10]_net_1\, B => \state[4]_net_1\, - Y => \data_5[10]\); - - \data_temp[60]\ : DFN1C0 - port map(D => \data_temp_5[60]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[60]_net_1\); - - \data_temp[53]\ : DFN1C0 - port map(D => \data_temp_5[53]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[53]_net_1\); - - \data_valid_and_ready_3[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready_3[2]_net_1\); - - \data_temp_RNO_3[76]\ : MX2C - port map(A => data_f0_out(108), B => data_f1_out(108), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_806); - - \data_temp_RNO_1[74]\ : MX2C - port map(A => N_729, B => N_818, S => N_1580_2, Y => - \data_selected[106]\); - - \data_temp_RNO_1[85]\ : MX2C - port map(A => N_1738, B => N_801, S => N_1580_3, Y => - \data_selected[117]\); - - \data_wen_RNO[3]\ : OR2 - port map(A => \time_en_temp[3]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[3]\); - - \data_temp_RNO_1[103]\ : MX2C - port map(A => N_1714, B => N_791, S => N_1580_3, Y => - \data_selected[135]\); - - \data_RNO[8]\ : NOR2A - port map(A => \data_temp[8]_net_1\, B => \state[4]_net_1\, - Y => \data_5[8]\); - - \data_temp_RNO_0[113]\ : MX2C - port map(A => \data_temp[113]_net_1\, B => - \data_selected[145]\, S => \state[4]_net_1\, Y => N_714); - - \data_temp_RNO_0[76]\ : MX2C - port map(A => \data_temp[108]_net_1\, B => - \data_selected[108]\, S => \state[4]_net_1\, Y => N_677); - - \data_temp_RNO[69]\ : NOR2A - port map(A => N_863, B => N_670, Y => \data_temp_5[69]\); - - \data_temp_RNO_2[102]\ : MX2C - port map(A => data_f2_out(134), B => data_f3_out(134), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1713); - - \data_temp_RNO_0[52]\ : MX2C - port map(A => \data_temp[84]_net_1\, B => - \data_selected[84]\, S => \state[4]_net_1\, Y => N_653); - - \data_temp_RNO_1[125]\ : MX2 - port map(A => data_f0_out(157), B => data_f1_out(157), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1682); - - \data_RNO[9]\ : NOR2A - port map(A => \data_temp[9]_net_1\, B => \state[4]_net_1\, - Y => \data_5[9]\); - - \data_temp_RNO_2[105]\ : MX2C - port map(A => data_f2_out(137), B => data_f3_out(137), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1716); - - \data_temp_RNO_3[42]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[74]_net_1\, - Y => N_1668); - - \data_temp_RNO_1[111]\ : MX2C - port map(A => N_1708, B => N_771, S => N_1580_2, Y => - \data_selected[143]\); - - \data_valid_ack[1]\ : DFN1E0C0 - port map(D => N_857, CLK => HCLK_c, CLR => HRESETn_c, E => - N_929, Q => valid_ack(1)); - - \data_temp_RNO_3[73]\ : MX2C - port map(A => data_f0_out(105), B => data_f1_out(105), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_817); - - \data_temp_RNO_1[84]\ : MX2C - port map(A => N_1737, B => N_800, S => N_1580_3, Y => - \data_selected[116]\); - - \data_temp_RNO_1[95]\ : MX2C - port map(A => N_1720, B => N_797, S => N_1580_1, Y => - \data_selected[127]\); - - \data_temp_RNO_1[40]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_765, - Y => N_1663); - - \data_temp[48]\ : DFN1C0 - port map(D => \data_temp_5[48]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[48]_net_1\); - - \data_temp_RNO[50]\ : NOR2A - port map(A => N_863_1, B => N_651, Y => \data_temp_5[50]\); - - \data_temp[86]\ : DFN1C0 - port map(D => \data_temp_5[86]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[86]_net_1\); - - \state_RNI8220I_0[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_917, Y => N_857); - - \data_temp_RNO[3]\ : NOR2A - port map(A => \data_temp[35]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[3]\); - - \data_temp_RNO_3[59]\ : MX2C - port map(A => data_f0_out(91), B => data_f1_out(91), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_831); - - \data_temp_RNO_3[51]\ : MX2C - port map(A => data_f0_out(83), B => data_f1_out(83), S => - \data_valid_and_ready[0]_net_1\, Y => N_837); - - \data_temp_RNO[80]\ : NOR2A - port map(A => N_863_1, B => N_681, Y => \data_temp_5[80]\); - - \data_temp_RNO_3[125]\ : MX2 - port map(A => data_f2_out(157), B => data_f3_out(157), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1694); - - \data_temp_RNO_3[69]\ : MX2C - port map(A => data_f0_out(101), B => data_f1_out(101), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_813); - - \data_temp_RNO_3[61]\ : MX2C - port map(A => data_f0_out(93), B => data_f1_out(93), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_833); - - \data_temp_RNO_0[73]\ : MX2C - port map(A => \data_temp[105]_net_1\, B => - \data_selected[105]\, S => \state[4]_net_1\, Y => N_674); - - \data_RNO[15]\ : NOR2A - port map(A => \data_temp[15]_net_1\, B => \state[4]_net_1\, - Y => \data_5[15]\); - - \data_temp_RNO_3[89]\ : MX2C - port map(A => data_f0_out(121), B => data_f1_out(121), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_805); - - \data_temp_RNO_3[81]\ : MX2C - port map(A => data_f0_out(113), B => data_f1_out(113), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_811); - - \data_temp_RNO[66]\ : NOR2A - port map(A => N_863, B => N_667, Y => \data_temp_5[66]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_temp_RNO_3[109]\ : MX2C - port map(A => data_f0_out(141), B => data_f1_out(141), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_783); - - \data_temp[116]\ : DFN1C0 - port map(D => \data_temp_5[116]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[116]_net_1\); - - \data_temp_RNO_1[94]\ : MX2C - port map(A => N_1719, B => N_796, S => N_1580_1, Y => - \data_selected[126]\); - - \data_temp_RNO[11]\ : NOR2A - port map(A => \data_temp[43]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[11]\); - - \data_temp_RNO_1[126]\ : MX2C - port map(A => N_1695, B => N_1683, S => N_1580_1, Y => - \data_selected[158]\); - - \data_temp_RNO_4[36]\ : MX2 - port map(A => data_f2_out(68), B => data_f3_out(68), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1689); - - \data_RNO[29]\ : NOR2A - port map(A => \data_temp[29]_net_1\, B => \state[4]_net_1\, - Y => \data_5[29]\); - - \state[3]\ : DFN1C0 - port map(D => state_0_sqmuxa_i_i, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - \data_temp_RNO[12]\ : NOR2A - port map(A => \data_temp[44]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[12]\); - - \data_temp[47]\ : DFN1C0 - port map(D => \data_temp_5[47]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[47]_net_1\); - - \data_valid_ack_RNO[2]\ : INV - port map(A => N_859, Y => N_859_i); - - \data_RNO[30]\ : NOR2A - port map(A => \data_temp[30]_net_1\, B => \state[4]_net_1\, - Y => \data_5[30]\); - - \data_temp_RNO_4[33]\ : MX2 - port map(A => data_f2_out(65), B => data_f3_out(65), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1686); - - \data_temp_RNO_3[90]\ : MX2C - port map(A => data_f0_out(122), B => data_f1_out(122), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_792); - - \data_temp_RNO_1[42]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_767, - Y => N_1669); - - \data_temp_RNO_2[121]\ : MX2C - port map(A => data_f2_out(153), B => data_f3_out(153), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1690); - - \data_temp[33]\ : DFN1C0 - port map(D => N_219, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[33]_net_1\); - - \data_temp[20]\ : DFN1C0 - port map(D => \data_temp_5[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[20]_net_1\); - - \data_temp_RNO_2[106]\ : MX2C - port map(A => data_f2_out(138), B => data_f3_out(138), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1717); - - \data_temp_RNIERBC[125]\ : OR2 - port map(A => \state[4]_net_1\, B => \data_temp[125]_net_1\, - Y => N_914); - - \data[24]\ : DFN1C0 - port map(D => \data_5[24]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(24)); - - \data_temp_RNO[95]\ : NOR2A - port map(A => N_863_0, B => N_696, Y => \data_temp_5[95]\); - - \data_temp_RNO[14]\ : NOR2A - port map(A => \data_temp[46]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[14]\); - - \data_temp_RNO_2[89]\ : MX2C - port map(A => data_f2_out(121), B => data_f3_out(121), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1728); - - \data_temp_RNO_2[81]\ : MX2C - port map(A => data_f2_out(113), B => data_f3_out(113), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1734); - - \data_temp_RNO_3[39]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[71]_net_1\, - Y => N_1659); - - \data_temp[50]\ : DFN1C0 - port map(D => \data_temp_5[50]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[50]_net_1\); - - \data_temp_RNO_3[55]\ : MX2C - port map(A => data_f0_out(87), B => data_f1_out(87), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_827); - - \data_temp_RNO_0[86]\ : MX2C - port map(A => \data_temp[118]_net_1\, B => - \data_selected[118]\, S => \state[4]_net_1\, Y => N_687); - - \data[1]\ : DFN1C0 - port map(D => \data_5[1]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(1)); - - \data_valid_and_ready_2[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready_2[2]_net_1\); - - \data_temp_RNO_3[65]\ : MX2C - port map(A => data_f0_out(97), B => data_f1_out(97), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_823); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_valid_and_ready[1]\ : NOR2 - port map(A => valid_out_i(1), B => ready_i_0(1), Y => - \data_valid_and_ready[1]_net_1\); - - \data_temp_RNO_3[85]\ : MX2C - port map(A => data_f0_out(117), B => data_f1_out(117), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_801); - - \state_RNO[4]\ : OA1B - port map(A => N_1306, B => \state[0]_net_1\, C => - \state_ns_i_i_a2_1[0]\, Y => N_861); - - \data_temp_RNO_2[96]\ : MX2C - port map(A => data_f2_out(128), B => data_f3_out(128), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1721); - - \data[9]\ : DFN1C0 - port map(D => \data_5[9]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(9)); - - \data_temp_RNO_3[123]\ : MX2 - port map(A => data_f2_out(155), B => data_f3_out(155), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1692); - - \data_valid_and_ready[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready[2]_net_1\); - - \data_temp_RNO_3[54]\ : MX2C - port map(A => data_f0_out(86), B => data_f1_out(86), S => - \data_valid_and_ready[0]_net_1\, Y => N_840); - - \data_temp_RNO_1[124]\ : MX2 - port map(A => data_f0_out(156), B => data_f1_out(156), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1681); - - \data_temp_RNO_3[92]\ : MX2 - port map(A => data_f2_out(124), B => data_f3_out(124), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1731); - - \data_temp_RNO_3[64]\ : MX2C - port map(A => data_f0_out(96), B => data_f1_out(96), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_822); - - \data_temp_RNO_1[57]\ : MX2C - port map(A => N_754, B => N_829, S => N_1580_1, Y => - \data_selected[89]\); - - \data_temp_RNO_2[69]\ : MX2C - port map(A => data_f2_out(101), B => data_f3_out(101), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_738); - - \data_temp_RNO_2[61]\ : MX2C - port map(A => data_f2_out(93), B => data_f3_out(93), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_744); - - \data[17]\ : DFN1C0 - port map(D => \data_5[17]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(17)); - - \data_temp_RNO_3[84]\ : MX2C - port map(A => data_f0_out(116), B => data_f1_out(116), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_800); - - \data_temp_RNO_0[83]\ : MX2C - port map(A => \data_temp[115]_net_1\, B => - \data_selected[115]\, S => \state[4]_net_1\, Y => N_684); - - \data_temp_RNO_2[58]\ : MX2C - port map(A => data_f2_out(90), B => data_f3_out(90), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_741); - - \data[20]\ : DFN1C0 - port map(D => \data_5[20]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(20)); - - \data_temp_RNO_2[93]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1718, - Y => N_902); - - \data_RNO[6]\ : NOR2A - port map(A => \data_temp[6]_net_1\, B => \state[4]_net_1\, - Y => \data_5[6]\); - - \data_RNO[3]\ : NOR2A - port map(A => \data_temp[3]_net_1\, B => \state[4]_net_1\, - Y => \data_5[3]\); - - \data_temp_RNO_2[77]\ : MX2C - port map(A => data_f2_out(109), B => data_f3_out(109), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_732); - - \data_temp_RNO_0[66]\ : MX2C - port map(A => \data_temp[98]_net_1\, B => - \data_selected[98]\, S => \state[4]_net_1\, Y => N_667); - - \data_temp_RNO[21]\ : NOR2A - port map(A => \data_temp[53]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[21]\); - - \data_wen[0]\ : DFN1E0P0 - port map(D => \data_wen_3[0]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => data_wen(0)); - - \data_temp_RNO_0[104]\ : MX2C - port map(A => \data_temp[104]_net_1\, B => - \data_selected[136]\, S => \state[4]_net_1\, Y => N_705); - - \data_temp_RNO_4[40]\ : MX2 - port map(A => data_f2_out(72), B => data_f3_out(72), S => - \data_valid_and_ready[2]_net_1\, Y => N_765); - - \data_temp_RNO_2[47]\ : MX2C - port map(A => data_f2_out(79), B => data_f3_out(79), S => - \data_valid_and_ready[2]_net_1\, Y => N_758); - - \data_temp_RNO_0[101]\ : MX2C - port map(A => \data_temp[101]_net_1\, B => - \data_selected[133]\, S => \state[4]_net_1\, Y => N_702); - - \data_temp_RNO_0[40]\ : AO1D - port map(A => N_912_i, B => N_854, C => N_1662, Y => - \data_temp_5_i_0[40]\); - - \data_temp_RNO_0[38]\ : AO1D - port map(A => N_912_i, B => N_852, C => N_1656, Y => - \data_temp_5_i_0[38]\); - - \state_RNIIO749[4]\ : OR2A - port map(A => \state[4]_net_1\, B => - \data_valid_and_ready_0[0]_net_1\, Y => \time_wen_3[0]\); - - \data_temp_RNO[67]\ : NOR2A - port map(A => N_863, B => N_668, Y => \data_temp_5[67]\); - - \data_temp_RNO[22]\ : NOR2A - port map(A => \data_temp[54]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[22]\); - - \data_temp_RNO[79]\ : NOR2A - port map(A => N_863_2, B => N_680, Y => \data_temp_5[79]\); - - \data_temp[66]\ : DFN1C0 - port map(D => \data_temp_5[66]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[66]_net_1\); - - \data_temp_RNO_2[85]\ : MX2C - port map(A => data_f2_out(117), B => data_f3_out(117), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1738); - - \data_temp_RNO_2[123]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_1, C => N_1692, - Y => N_910); - - \data_temp_RNO_0[63]\ : MX2C - port map(A => \data_temp[95]_net_1\, B => - \data_selected[95]\, S => \state[4]_net_1\, Y => N_664); - - \data_temp_RNO_3[35]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[67]_net_1\, - Y => N_873); - - \data_temp[84]\ : DFN1C0 - port map(D => \data_temp_5[84]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[84]_net_1\); - - \data_temp[45]\ : DFN1C0 - port map(D => \data_temp_5[45]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[45]_net_1\); - - \data_valid_ack[2]\ : DFN1E0C0 - port map(D => N_859_i, CLK => HCLK_c, CLR => HRESETn_c, E - => N_929, Q => valid_ack(2)); - - \data_temp[73]\ : DFN1C0 - port map(D => \data_temp_5[73]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[73]_net_1\); - - \data_temp_RNO_3[118]\ : MX2C - port map(A => data_f0_out(150), B => data_f1_out(150), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1675); - - \data_temp_RNO_2[84]\ : MX2C - port map(A => data_f2_out(116), B => data_f3_out(116), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1737); - - \data_temp_RNO[76]\ : NOR2A - port map(A => N_863_1, B => N_677, Y => \data_temp_5[76]\); - - \data_temp_RNO_3[34]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[66]_net_1\, - Y => N_870); - - \data_temp[113]\ : DFN1C0 - port map(D => \data_temp_5[113]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[113]_net_1\); - - \data_temp_RNO[24]\ : NOR2A - port map(A => \data_temp[56]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[24]\); - - \data_temp[30]\ : DFN1C0 - port map(D => \data_temp_5[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[30]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform is - - port( status_full_ack : in std_logic_vector(3 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hsize_c : out std_logic_vector(1 downto 0); - AHB_Master_In_c_5 : in std_logic; - AHB_Master_In_c_4 : in std_logic; - AHB_Master_In_c_0 : in std_logic; - AHB_Master_In_c_3 : in std_logic; - haddr_c : out std_logic_vector(31 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - status_full : out std_logic_vector(3 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - hwdata_c : out std_logic_vector(31 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - sample_f3_wdata : in std_logic_vector(95 downto 0); - sample_f2_wdata : in std_logic_vector(95 downto 0); - sample_f1_15 : in std_logic; - sample_f1_47 : in std_logic; - sample_f1_14 : in std_logic; - sample_f1_46 : in std_logic; - sample_f1_13 : in std_logic; - sample_f1_45 : in std_logic; - sample_f1_12 : in std_logic; - sample_f1_44 : in std_logic; - sample_f1_60 : in std_logic; - sample_f1_59 : in std_logic; - sample_f1_58 : in std_logic; - sample_f1_57 : in std_logic; - sample_f1_56 : in std_logic; - sample_f1_55 : in std_logic; - sample_f1_54 : in std_logic; - sample_f1_53 : in std_logic; - sample_f1_52 : in std_logic; - sample_f1_51 : in std_logic; - sample_f1_50 : in std_logic; - sample_f1_49 : in std_logic; - sample_f1_48 : in std_logic; - sample_f1_4 : in std_logic; - sample_f1_36 : in std_logic; - sample_f1_3 : in std_logic; - sample_f1_35 : in std_logic; - sample_f1_2 : in std_logic; - sample_f1_34 : in std_logic; - sample_f1_1 : in std_logic; - sample_f1_33 : in std_logic; - sample_f1_0 : in std_logic; - sample_f1_32 : in std_logic; - sample_f1_63 : in std_logic; - sample_f1_62 : in std_logic; - sample_f1_61 : in std_logic; - sample_f1_11 : in std_logic; - sample_f1_43 : in std_logic; - sample_f1_10 : in std_logic; - sample_f1_42 : in std_logic; - sample_f1_9 : in std_logic; - sample_f1_41 : in std_logic; - sample_f1_8 : in std_logic; - sample_f1_40 : in std_logic; - sample_f1_7 : in std_logic; - sample_f1_39 : in std_logic; - sample_f1_6 : in std_logic; - sample_f1_38 : in std_logic; - sample_f1_5 : in std_logic; - sample_f1_37 : in std_logic; - sample_f1_wdata_0 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_95 : in std_logic; - sample_f0_15 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_0 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_63 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_37 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_95 : in std_logic; - delta_f2_f1 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - nb_snapshot_param : in std_logic_vector(10 downto 0); - hwrite_c : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - N_43 : out std_logic; - lpp_waveform_GND : in std_logic; - lpp_waveform_VCC : in std_logic; - sample_f3_val : in std_logic; - enable_f3 : in std_logic; - burst_f2 : in std_logic; - enable_f2 : in std_logic; - sample_f1_val_0 : in std_logic; - burst_f1 : in std_logic; - enable_f1 : in std_logic; - data_shaping_R1_0 : in std_logic; - data_shaping_R1 : in std_logic; - burst_f0 : in std_logic; - data_shaping_R0_0 : in std_logic; - data_shaping_R0 : in std_logic; - enable_f0 : in std_logic; - coarse_time_0_c : in std_logic; - sample_f2_val : in std_logic; - sample_f0_val_0 : in std_logic; - HCLK_c : in std_logic; - HRESETn_c : in std_logic - ); - -end lpp_waveform; - -architecture DEF_ARCH of lpp_waveform is - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 - port( sample_f1_wdata_95 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - data_f1_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0) := (others => 'U'); - sample_f1_37 : in std_logic := 'U'; - sample_f1_5 : in std_logic := 'U'; - sample_f1_38 : in std_logic := 'U'; - sample_f1_6 : in std_logic := 'U'; - sample_f1_39 : in std_logic := 'U'; - sample_f1_7 : in std_logic := 'U'; - sample_f1_40 : in std_logic := 'U'; - sample_f1_8 : in std_logic := 'U'; - sample_f1_41 : in std_logic := 'U'; - sample_f1_9 : in std_logic := 'U'; - sample_f1_42 : in std_logic := 'U'; - sample_f1_10 : in std_logic := 'U'; - sample_f1_43 : in std_logic := 'U'; - sample_f1_11 : in std_logic := 'U'; - sample_f1_61 : in std_logic := 'U'; - sample_f1_62 : in std_logic := 'U'; - sample_f1_63 : in std_logic := 'U'; - sample_f1_32 : in std_logic := 'U'; - sample_f1_0 : in std_logic := 'U'; - sample_f1_33 : in std_logic := 'U'; - sample_f1_1 : in std_logic := 'U'; - sample_f1_34 : in std_logic := 'U'; - sample_f1_2 : in std_logic := 'U'; - sample_f1_35 : in std_logic := 'U'; - sample_f1_3 : in std_logic := 'U'; - sample_f1_36 : in std_logic := 'U'; - sample_f1_4 : in std_logic := 'U'; - sample_f1_48 : in std_logic := 'U'; - sample_f1_49 : in std_logic := 'U'; - sample_f1_50 : in std_logic := 'U'; - sample_f1_51 : in std_logic := 'U'; - sample_f1_52 : in std_logic := 'U'; - sample_f1_53 : in std_logic := 'U'; - sample_f1_54 : in std_logic := 'U'; - sample_f1_55 : in std_logic := 'U'; - sample_f1_56 : in std_logic := 'U'; - sample_f1_57 : in std_logic := 'U'; - sample_f1_58 : in std_logic := 'U'; - sample_f1_59 : in std_logic := 'U'; - sample_f1_60 : in std_logic := 'U'; - sample_f1_44 : in std_logic := 'U'; - sample_f1_12 : in std_logic := 'U'; - sample_f1_45 : in std_logic := 'U'; - sample_f1_13 : in std_logic := 'U'; - sample_f1_46 : in std_logic := 'U'; - sample_f1_14 : in std_logic := 'U'; - sample_f1_47 : in std_logic := 'U'; - sample_f1_15 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f1_out_valid : out std_logic; - N_4 : in std_logic := 'U'; - I_38_4 : in std_logic := 'U'; - I_24_4 : in std_logic := 'U'; - I_20_12 : in std_logic := 'U'; - I_13_20 : in std_logic := 'U'; - I_45_4 : in std_logic := 'U'; - I_9_20 : in std_logic := 'U'; - I_5_20 : in std_logic := 'U'; - I_52_4 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - I_56_4 : in std_logic := 'U'; - I_31_5 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U'; - start_snapshot_f1 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_controler - port( delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - start_snapshot_f2 : out std_logic; - start_snapshot_f1 : out std_logic; - start_snapshot_f0 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U'; - coarse_time_0_c : in std_logic := 'U' - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - port( status_new_err : out std_logic_vector(3 to 3); - valid_ack : in std_logic_vector(3 to 3) := (others => 'U'); - valid_out : out std_logic_vector(3 to 3); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f3_out_valid : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - port( status_new_err : out std_logic_vector(1 to 1); - valid_out_i : out std_logic_vector(1 to 1); - valid_ack : in std_logic_vector(1 to 1) := (others => 'U'); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f1_out_valid : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_waveform_burst - port( sample_f3_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - data_f3_out : out std_logic_vector(159 downto 64); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f3_out_valid : out std_logic; - enable_f3 : in std_logic := 'U'; - sample_f3_val : in std_logic := 'U' - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - port( status_new_err : out std_logic_vector(2 to 2); - valid_ack : in std_logic_vector(2 to 2) := (others => 'U'); - valid_out : out std_logic_vector(2 to 2); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f2_out_valid : in std_logic := 'U' - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - port( status_new_err : out std_logic_vector(0 to 0); - valid_ack : in std_logic_vector(0 to 0) := (others => 'U'); - valid_out : out std_logic_vector(0 to 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f0_out_valid : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo - port( data_wen : in std_logic_vector(3 downto 0) := (others => 'U'); - data_ren : in std_logic_vector(3 downto 0) := (others => 'U'); - ready_i_0 : out std_logic_vector(3 downto 0); - time_ren : in std_logic_vector(3 downto 0) := (others => 'U'); - time_wen : in std_logic_vector(3 downto 0) := (others => 'U'); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata_c : out std_logic_vector(31 downto 0); - time_ren_1z : in std_logic := 'U'; - data_ren_1z : in std_logic := 'U'; - un20_time_write : in std_logic := 'U'; - un13_time_write : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - lpp_waveform_fifo_VCC : in std_logic := 'U'; - lpp_waveform_fifo_GND : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_160_11 - port( sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - data_f0_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - sample_f0_37 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_0 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f0_out_valid : out std_logic; - enable_f0 : in std_logic := 'U'; - data_shaping_R0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - start_snapshot_f0 : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U' - ); - end component; - - component - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 - port( sample_f2_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - data_f2_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0) := (others => 'U'); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f2_out_valid : out std_logic; - I_13_20 : in std_logic := 'U'; - I_9_20 : in std_logic := 'U'; - I_5_20 : in std_logic := 'U'; - I_38_4 : in std_logic := 'U'; - I_31_5 : in std_logic := 'U'; - N_4 : in std_logic := 'U'; - I_45_4 : in std_logic := 'U'; - I_56_4 : in std_logic := 'U'; - I_52_4 : in std_logic := 'U'; - I_24_4 : in std_logic := 'U'; - I_20_12 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - start_snapshot_f2 : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U' - ); - end component; - - component lpp_waveform_dma - port( addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - haddr_c : out std_logic_vector(31 downto 0); - AHB_Master_In_c_3 : in std_logic := 'U'; - AHB_Master_In_c_0 : in std_logic := 'U'; - AHB_Master_In_c_4 : in std_logic := 'U'; - AHB_Master_In_c_5 : in std_logic := 'U'; - hsize_c : out std_logic_vector(1 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - ready_i_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - data_ren : out std_logic_vector(3 downto 0); - time_ren : out std_logic_vector(3 downto 0); - time_ren_1z : out std_logic; - data_ren_1z : out std_logic; - N_43 : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - hwrite_c : out std_logic; - un20_time_write : out std_logic; - un13_time_write : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_arbiter - port( wdata : out std_logic_vector(31 downto 0); - data_wen : out std_logic_vector(3 downto 0); - valid_ack : out std_logic_vector(3 downto 0); - time_wen : out std_logic_vector(3 downto 0); - data_f3_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f2_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f1_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f0_out : in std_logic_vector(159 downto 64) := (others => 'U'); - valid_out_i : in std_logic_vector(1 to 1) := (others => 'U'); - ready_i_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - valid_out_3 : in std_logic := 'U'; - valid_out_2 : in std_logic := 'U'; - valid_out_0 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal N_45, N_37, \DWACT_FINC_E[0]\, N_14, - \DWACT_FINC_E[4]\, N_4, \DWACT_FINC_E[6]\, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[5]\, I_56_4, N_11, - I_52_4, \DWACT_FINC_E[3]\, I_45_4, N_19, I_38_4, N_24, - I_31_5, N_29, \DWACT_FINC_E[1]\, I_24_4, N_34, I_20_12, - I_13_20, N_42, I_9_20, I_5_20, start_snapshot_f2, - start_snapshot_f1, start_snapshot_f0, \data_f0_out[64]\, - \data_f0_out[65]\, \data_f0_out[66]\, \data_f0_out[67]\, - \data_f0_out[68]\, \data_f0_out[69]\, \data_f0_out[70]\, - \data_f0_out[71]\, \data_f0_out[72]\, \data_f0_out[73]\, - \data_f0_out[74]\, \data_f0_out[75]\, \data_f0_out[76]\, - \data_f0_out[77]\, \data_f0_out[78]\, \data_f0_out[79]\, - \data_f0_out[80]\, \data_f0_out[81]\, \data_f0_out[82]\, - \data_f0_out[83]\, \data_f0_out[84]\, \data_f0_out[85]\, - \data_f0_out[86]\, \data_f0_out[87]\, \data_f0_out[88]\, - \data_f0_out[89]\, \data_f0_out[90]\, \data_f0_out[91]\, - \data_f0_out[92]\, \data_f0_out[93]\, \data_f0_out[94]\, - \data_f0_out[95]\, \data_f0_out[96]\, \data_f0_out[97]\, - \data_f0_out[98]\, \data_f0_out[99]\, \data_f0_out[100]\, - \data_f0_out[101]\, \data_f0_out[102]\, - \data_f0_out[103]\, \data_f0_out[104]\, - \data_f0_out[105]\, \data_f0_out[106]\, - \data_f0_out[107]\, \data_f0_out[108]\, - \data_f0_out[109]\, \data_f0_out[110]\, - \data_f0_out[111]\, \data_f0_out[112]\, - \data_f0_out[113]\, \data_f0_out[114]\, - \data_f0_out[115]\, \data_f0_out[116]\, - \data_f0_out[117]\, \data_f0_out[118]\, - \data_f0_out[119]\, \data_f0_out[120]\, - \data_f0_out[121]\, \data_f0_out[122]\, - \data_f0_out[123]\, \data_f0_out[124]\, - \data_f0_out[125]\, \data_f0_out[126]\, - \data_f0_out[127]\, \data_f0_out[128]\, - \data_f0_out[129]\, \data_f0_out[130]\, - \data_f0_out[131]\, \data_f0_out[132]\, - \data_f0_out[133]\, \data_f0_out[134]\, - \data_f0_out[135]\, \data_f0_out[136]\, - \data_f0_out[137]\, \data_f0_out[138]\, - \data_f0_out[139]\, \data_f0_out[140]\, - \data_f0_out[141]\, \data_f0_out[142]\, - \data_f0_out[143]\, \data_f0_out[144]\, - \data_f0_out[145]\, \data_f0_out[146]\, - \data_f0_out[147]\, \data_f0_out[148]\, - \data_f0_out[149]\, \data_f0_out[150]\, - \data_f0_out[151]\, \data_f0_out[152]\, - \data_f0_out[153]\, \data_f0_out[154]\, - \data_f0_out[155]\, \data_f0_out[156]\, - \data_f0_out[157]\, \data_f0_out[158]\, - \data_f0_out[159]\, data_f0_out_valid, \data_f1_out[64]\, - \data_f1_out[65]\, \data_f1_out[66]\, \data_f1_out[67]\, - \data_f1_out[68]\, \data_f1_out[69]\, \data_f1_out[70]\, - \data_f1_out[71]\, \data_f1_out[72]\, \data_f1_out[73]\, - \data_f1_out[74]\, \data_f1_out[75]\, \data_f1_out[76]\, - \data_f1_out[77]\, \data_f1_out[78]\, \data_f1_out[79]\, - \data_f1_out[80]\, \data_f1_out[81]\, \data_f1_out[82]\, - \data_f1_out[83]\, \data_f1_out[84]\, \data_f1_out[85]\, - \data_f1_out[86]\, \data_f1_out[87]\, \data_f1_out[88]\, - \data_f1_out[89]\, \data_f1_out[90]\, \data_f1_out[91]\, - \data_f1_out[92]\, \data_f1_out[93]\, \data_f1_out[94]\, - \data_f1_out[95]\, \data_f1_out[96]\, \data_f1_out[97]\, - \data_f1_out[98]\, \data_f1_out[99]\, \data_f1_out[100]\, - \data_f1_out[101]\, \data_f1_out[102]\, - \data_f1_out[103]\, \data_f1_out[104]\, - \data_f1_out[105]\, \data_f1_out[106]\, - \data_f1_out[107]\, \data_f1_out[108]\, - \data_f1_out[109]\, \data_f1_out[110]\, - \data_f1_out[111]\, \data_f1_out[112]\, - \data_f1_out[113]\, \data_f1_out[114]\, - \data_f1_out[115]\, \data_f1_out[116]\, - \data_f1_out[117]\, \data_f1_out[118]\, - \data_f1_out[119]\, \data_f1_out[120]\, - \data_f1_out[121]\, \data_f1_out[122]\, - \data_f1_out[123]\, \data_f1_out[124]\, - \data_f1_out[125]\, \data_f1_out[126]\, - \data_f1_out[127]\, \data_f1_out[128]\, - \data_f1_out[129]\, \data_f1_out[130]\, - \data_f1_out[131]\, \data_f1_out[132]\, - \data_f1_out[133]\, \data_f1_out[134]\, - \data_f1_out[135]\, \data_f1_out[136]\, - \data_f1_out[137]\, \data_f1_out[138]\, - \data_f1_out[139]\, \data_f1_out[140]\, - \data_f1_out[141]\, \data_f1_out[142]\, - \data_f1_out[143]\, \data_f1_out[144]\, - \data_f1_out[145]\, \data_f1_out[146]\, - \data_f1_out[147]\, \data_f1_out[148]\, - \data_f1_out[149]\, \data_f1_out[150]\, - \data_f1_out[151]\, \data_f1_out[152]\, - \data_f1_out[153]\, \data_f1_out[154]\, - \data_f1_out[155]\, \data_f1_out[156]\, - \data_f1_out[157]\, \data_f1_out[158]\, - \data_f1_out[159]\, data_f1_out_valid, \data_f2_out[64]\, - \data_f2_out[65]\, \data_f2_out[66]\, \data_f2_out[67]\, - \data_f2_out[68]\, \data_f2_out[69]\, \data_f2_out[70]\, - \data_f2_out[71]\, \data_f2_out[72]\, \data_f2_out[73]\, - \data_f2_out[74]\, \data_f2_out[75]\, \data_f2_out[76]\, - \data_f2_out[77]\, \data_f2_out[78]\, \data_f2_out[79]\, - \data_f2_out[80]\, \data_f2_out[81]\, \data_f2_out[82]\, - \data_f2_out[83]\, \data_f2_out[84]\, \data_f2_out[85]\, - \data_f2_out[86]\, \data_f2_out[87]\, \data_f2_out[88]\, - \data_f2_out[89]\, \data_f2_out[90]\, \data_f2_out[91]\, - \data_f2_out[92]\, \data_f2_out[93]\, \data_f2_out[94]\, - \data_f2_out[95]\, \data_f2_out[96]\, \data_f2_out[97]\, - \data_f2_out[98]\, \data_f2_out[99]\, \data_f2_out[100]\, - \data_f2_out[101]\, \data_f2_out[102]\, - \data_f2_out[103]\, \data_f2_out[104]\, - \data_f2_out[105]\, \data_f2_out[106]\, - \data_f2_out[107]\, \data_f2_out[108]\, - \data_f2_out[109]\, \data_f2_out[110]\, - \data_f2_out[111]\, \data_f2_out[112]\, - \data_f2_out[113]\, \data_f2_out[114]\, - \data_f2_out[115]\, \data_f2_out[116]\, - \data_f2_out[117]\, \data_f2_out[118]\, - \data_f2_out[119]\, \data_f2_out[120]\, - \data_f2_out[121]\, \data_f2_out[122]\, - \data_f2_out[123]\, \data_f2_out[124]\, - \data_f2_out[125]\, \data_f2_out[126]\, - \data_f2_out[127]\, \data_f2_out[128]\, - \data_f2_out[129]\, \data_f2_out[130]\, - \data_f2_out[131]\, \data_f2_out[132]\, - \data_f2_out[133]\, \data_f2_out[134]\, - \data_f2_out[135]\, \data_f2_out[136]\, - \data_f2_out[137]\, \data_f2_out[138]\, - \data_f2_out[139]\, \data_f2_out[140]\, - \data_f2_out[141]\, \data_f2_out[142]\, - \data_f2_out[143]\, \data_f2_out[144]\, - \data_f2_out[145]\, \data_f2_out[146]\, - \data_f2_out[147]\, \data_f2_out[148]\, - \data_f2_out[149]\, \data_f2_out[150]\, - \data_f2_out[151]\, \data_f2_out[152]\, - \data_f2_out[153]\, \data_f2_out[154]\, - \data_f2_out[155]\, \data_f2_out[156]\, - \data_f2_out[157]\, \data_f2_out[158]\, - \data_f2_out[159]\, data_f2_out_valid, \data_f3_out[64]\, - \data_f3_out[65]\, \data_f3_out[66]\, \data_f3_out[67]\, - \data_f3_out[68]\, \data_f3_out[69]\, \data_f3_out[70]\, - \data_f3_out[71]\, \data_f3_out[72]\, \data_f3_out[73]\, - \data_f3_out[74]\, \data_f3_out[75]\, \data_f3_out[76]\, - \data_f3_out[77]\, \data_f3_out[78]\, \data_f3_out[79]\, - \data_f3_out[80]\, \data_f3_out[81]\, \data_f3_out[82]\, - \data_f3_out[83]\, \data_f3_out[84]\, \data_f3_out[85]\, - \data_f3_out[86]\, \data_f3_out[87]\, \data_f3_out[88]\, - \data_f3_out[89]\, \data_f3_out[90]\, \data_f3_out[91]\, - \data_f3_out[92]\, \data_f3_out[93]\, \data_f3_out[94]\, - \data_f3_out[95]\, \data_f3_out[96]\, \data_f3_out[97]\, - \data_f3_out[98]\, \data_f3_out[99]\, \data_f3_out[100]\, - \data_f3_out[101]\, \data_f3_out[102]\, - \data_f3_out[103]\, \data_f3_out[104]\, - \data_f3_out[105]\, \data_f3_out[106]\, - \data_f3_out[107]\, \data_f3_out[108]\, - \data_f3_out[109]\, \data_f3_out[110]\, - \data_f3_out[111]\, \data_f3_out[112]\, - \data_f3_out[113]\, \data_f3_out[114]\, - \data_f3_out[115]\, \data_f3_out[116]\, - \data_f3_out[117]\, \data_f3_out[118]\, - \data_f3_out[119]\, \data_f3_out[120]\, - \data_f3_out[121]\, \data_f3_out[122]\, - \data_f3_out[123]\, \data_f3_out[124]\, - \data_f3_out[125]\, \data_f3_out[126]\, - \data_f3_out[127]\, \data_f3_out[128]\, - \data_f3_out[129]\, \data_f3_out[130]\, - \data_f3_out[131]\, \data_f3_out[132]\, - \data_f3_out[133]\, \data_f3_out[134]\, - \data_f3_out[135]\, \data_f3_out[136]\, - \data_f3_out[137]\, \data_f3_out[138]\, - \data_f3_out[139]\, \data_f3_out[140]\, - \data_f3_out[141]\, \data_f3_out[142]\, - \data_f3_out[143]\, \data_f3_out[144]\, - \data_f3_out[145]\, \data_f3_out[146]\, - \data_f3_out[147]\, \data_f3_out[148]\, - \data_f3_out[149]\, \data_f3_out[150]\, - \data_f3_out[151]\, \data_f3_out[152]\, - \data_f3_out[153]\, \data_f3_out[154]\, - \data_f3_out[155]\, \data_f3_out[156]\, - \data_f3_out[157]\, \data_f3_out[158]\, - \data_f3_out[159]\, data_f3_out_valid, \valid_ack[3]\, - \valid_out[3]\, \valid_ack[0]\, \valid_out[0]\, - \valid_out_i[1]\, \valid_ack[1]\, \valid_ack[2]\, - \valid_out[2]\, \wdata[0]\, \wdata[1]\, \wdata[2]\, - \wdata[3]\, \wdata[4]\, \wdata[5]\, \wdata[6]\, - \wdata[7]\, \wdata[8]\, \wdata[9]\, \wdata[10]\, - \wdata[11]\, \wdata[12]\, \wdata[13]\, \wdata[14]\, - \wdata[15]\, \wdata[16]\, \wdata[17]\, \wdata[18]\, - \wdata[19]\, \wdata[20]\, \wdata[21]\, \wdata[22]\, - \wdata[23]\, \wdata[24]\, \wdata[25]\, \wdata[26]\, - \wdata[27]\, \wdata[28]\, \wdata[29]\, \wdata[30]\, - \wdata[31]\, \data_wen[0]\, \data_wen[1]\, \data_wen[2]\, - \data_wen[3]\, \time_wen[0]\, \time_wen[1]\, - \time_wen[2]\, \time_wen[3]\, \ready_i_0[0]\, - \ready_i_0[1]\, \ready_i_0[2]\, \ready_i_0[3]\, - \data_ren[0]\, \data_ren[1]\, \data_ren[2]\, - \data_ren[3]\, \time_ren[0]\, \time_ren[1]\, - \time_ren[2]\, \time_ren[3]\, time_ren, data_ren, - un20_time_write, un13_time_write, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 - Use entity work. - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1(DEF_ARCH); - for all : lpp_waveform_snapshot_controler - Use entity work.lpp_waveform_snapshot_controler(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\(DEF_ARCH); - for all : lpp_waveform_burst - Use entity work.lpp_waveform_burst(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\(DEF_ARCH); - for all : lpp_waveform_fifo - Use entity work.lpp_waveform_fifo(DEF_ARCH); - for all : lpp_waveform_snapshot_160_11 - Use entity work.lpp_waveform_snapshot_160_11(DEF_ARCH); - for all : lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 - Use entity work. - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1(DEF_ARCH); - for all : lpp_waveform_dma - Use entity work.lpp_waveform_dma(DEF_ARCH); - for all : lpp_waveform_fifo_arbiter - Use entity work.lpp_waveform_fifo_arbiter(DEF_ARCH); -begin - - - un7_nb_snapshot_param_more_one_I_45 : XOR2 - port map(A => N_19, B => nb_snapshot_param(8), Y => I_45_4); - - un7_nb_snapshot_param_more_one_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => nb_snapshot_param(6), Y => N_24); - - un7_nb_snapshot_param_more_one_I_16 : AND3 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), C => nb_snapshot_param(2), Y => - \DWACT_FINC_E[0]\); - - lpp_waveform_snapshot_f1 : - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 - port map(sample_f1_wdata_95 => sample_f1_wdata_95, - sample_f1_wdata_94 => sample_f1_wdata_94, - sample_f1_wdata_93 => sample_f1_wdata_93, - sample_f1_wdata_92 => sample_f1_wdata_92, - sample_f1_wdata_91 => sample_f1_wdata_91, - sample_f1_wdata_90 => sample_f1_wdata_90, - sample_f1_wdata_89 => sample_f1_wdata_89, - sample_f1_wdata_88 => sample_f1_wdata_88, - sample_f1_wdata_87 => sample_f1_wdata_87, - sample_f1_wdata_86 => sample_f1_wdata_86, - sample_f1_wdata_85 => sample_f1_wdata_85, - sample_f1_wdata_84 => sample_f1_wdata_84, - sample_f1_wdata_83 => sample_f1_wdata_83, - sample_f1_wdata_82 => sample_f1_wdata_82, - sample_f1_wdata_81 => sample_f1_wdata_81, - sample_f1_wdata_80 => sample_f1_wdata_80, - sample_f1_wdata_79 => sample_f1_wdata_79, - sample_f1_wdata_78 => sample_f1_wdata_78, - sample_f1_wdata_77 => sample_f1_wdata_77, - sample_f1_wdata_76 => sample_f1_wdata_76, - sample_f1_wdata_75 => sample_f1_wdata_75, - sample_f1_wdata_74 => sample_f1_wdata_74, - sample_f1_wdata_73 => sample_f1_wdata_73, - sample_f1_wdata_72 => sample_f1_wdata_72, - sample_f1_wdata_71 => sample_f1_wdata_71, - sample_f1_wdata_70 => sample_f1_wdata_70, - sample_f1_wdata_69 => sample_f1_wdata_69, - sample_f1_wdata_68 => sample_f1_wdata_68, - sample_f1_wdata_67 => sample_f1_wdata_67, - sample_f1_wdata_66 => sample_f1_wdata_66, - sample_f1_wdata_65 => sample_f1_wdata_65, - sample_f1_wdata_64 => sample_f1_wdata_64, - sample_f1_wdata_63 => sample_f1_wdata_63, - sample_f1_wdata_62 => sample_f1_wdata_62, - sample_f1_wdata_61 => sample_f1_wdata_61, - sample_f1_wdata_60 => sample_f1_wdata_60, - sample_f1_wdata_59 => sample_f1_wdata_59, - sample_f1_wdata_58 => sample_f1_wdata_58, - sample_f1_wdata_57 => sample_f1_wdata_57, - sample_f1_wdata_56 => sample_f1_wdata_56, - sample_f1_wdata_55 => sample_f1_wdata_55, - sample_f1_wdata_54 => sample_f1_wdata_54, - sample_f1_wdata_53 => sample_f1_wdata_53, - sample_f1_wdata_52 => sample_f1_wdata_52, - sample_f1_wdata_51 => sample_f1_wdata_51, - sample_f1_wdata_50 => sample_f1_wdata_50, - sample_f1_wdata_49 => sample_f1_wdata_49, - sample_f1_wdata_48 => sample_f1_wdata_48, - sample_f1_wdata_15 => sample_f1_wdata_15, - sample_f1_wdata_14 => sample_f1_wdata_14, - sample_f1_wdata_13 => sample_f1_wdata_13, - sample_f1_wdata_12 => sample_f1_wdata_12, - sample_f1_wdata_11 => sample_f1_wdata_11, - sample_f1_wdata_10 => sample_f1_wdata_10, - sample_f1_wdata_9 => sample_f1_wdata_9, sample_f1_wdata_8 - => sample_f1_wdata_8, sample_f1_wdata_7 => - sample_f1_wdata_7, sample_f1_wdata_6 => sample_f1_wdata_6, - sample_f1_wdata_5 => sample_f1_wdata_5, sample_f1_wdata_4 - => sample_f1_wdata_4, sample_f1_wdata_3 => - sample_f1_wdata_3, sample_f1_wdata_2 => sample_f1_wdata_2, - sample_f1_wdata_1 => sample_f1_wdata_1, sample_f1_wdata_0 - => sample_f1_wdata_0, data_f1_out(159) => - \data_f1_out[159]\, data_f1_out(158) => - \data_f1_out[158]\, data_f1_out(157) => - \data_f1_out[157]\, data_f1_out(156) => - \data_f1_out[156]\, data_f1_out(155) => - \data_f1_out[155]\, data_f1_out(154) => - \data_f1_out[154]\, data_f1_out(153) => - \data_f1_out[153]\, data_f1_out(152) => - \data_f1_out[152]\, data_f1_out(151) => - \data_f1_out[151]\, data_f1_out(150) => - \data_f1_out[150]\, data_f1_out(149) => - \data_f1_out[149]\, data_f1_out(148) => - \data_f1_out[148]\, data_f1_out(147) => - \data_f1_out[147]\, data_f1_out(146) => - \data_f1_out[146]\, data_f1_out(145) => - \data_f1_out[145]\, data_f1_out(144) => - \data_f1_out[144]\, data_f1_out(143) => - \data_f1_out[143]\, data_f1_out(142) => - \data_f1_out[142]\, data_f1_out(141) => - \data_f1_out[141]\, data_f1_out(140) => - \data_f1_out[140]\, data_f1_out(139) => - \data_f1_out[139]\, data_f1_out(138) => - \data_f1_out[138]\, data_f1_out(137) => - \data_f1_out[137]\, data_f1_out(136) => - \data_f1_out[136]\, data_f1_out(135) => - \data_f1_out[135]\, data_f1_out(134) => - \data_f1_out[134]\, data_f1_out(133) => - \data_f1_out[133]\, data_f1_out(132) => - \data_f1_out[132]\, data_f1_out(131) => - \data_f1_out[131]\, data_f1_out(130) => - \data_f1_out[130]\, data_f1_out(129) => - \data_f1_out[129]\, data_f1_out(128) => - \data_f1_out[128]\, data_f1_out(127) => - \data_f1_out[127]\, data_f1_out(126) => - \data_f1_out[126]\, data_f1_out(125) => - \data_f1_out[125]\, data_f1_out(124) => - \data_f1_out[124]\, data_f1_out(123) => - \data_f1_out[123]\, data_f1_out(122) => - \data_f1_out[122]\, data_f1_out(121) => - \data_f1_out[121]\, data_f1_out(120) => - \data_f1_out[120]\, data_f1_out(119) => - \data_f1_out[119]\, data_f1_out(118) => - \data_f1_out[118]\, data_f1_out(117) => - \data_f1_out[117]\, data_f1_out(116) => - \data_f1_out[116]\, data_f1_out(115) => - \data_f1_out[115]\, data_f1_out(114) => - \data_f1_out[114]\, data_f1_out(113) => - \data_f1_out[113]\, data_f1_out(112) => - \data_f1_out[112]\, data_f1_out(111) => - \data_f1_out[111]\, data_f1_out(110) => - \data_f1_out[110]\, data_f1_out(109) => - \data_f1_out[109]\, data_f1_out(108) => - \data_f1_out[108]\, data_f1_out(107) => - \data_f1_out[107]\, data_f1_out(106) => - \data_f1_out[106]\, data_f1_out(105) => - \data_f1_out[105]\, data_f1_out(104) => - \data_f1_out[104]\, data_f1_out(103) => - \data_f1_out[103]\, data_f1_out(102) => - \data_f1_out[102]\, data_f1_out(101) => - \data_f1_out[101]\, data_f1_out(100) => - \data_f1_out[100]\, data_f1_out(99) => \data_f1_out[99]\, - data_f1_out(98) => \data_f1_out[98]\, data_f1_out(97) => - \data_f1_out[97]\, data_f1_out(96) => \data_f1_out[96]\, - data_f1_out(95) => \data_f1_out[95]\, data_f1_out(94) => - \data_f1_out[94]\, data_f1_out(93) => \data_f1_out[93]\, - data_f1_out(92) => \data_f1_out[92]\, data_f1_out(91) => - \data_f1_out[91]\, data_f1_out(90) => \data_f1_out[90]\, - data_f1_out(89) => \data_f1_out[89]\, data_f1_out(88) => - \data_f1_out[88]\, data_f1_out(87) => \data_f1_out[87]\, - data_f1_out(86) => \data_f1_out[86]\, data_f1_out(85) => - \data_f1_out[85]\, data_f1_out(84) => \data_f1_out[84]\, - data_f1_out(83) => \data_f1_out[83]\, data_f1_out(82) => - \data_f1_out[82]\, data_f1_out(81) => \data_f1_out[81]\, - data_f1_out(80) => \data_f1_out[80]\, data_f1_out(79) => - \data_f1_out[79]\, data_f1_out(78) => \data_f1_out[78]\, - data_f1_out(77) => \data_f1_out[77]\, data_f1_out(76) => - \data_f1_out[76]\, data_f1_out(75) => \data_f1_out[75]\, - data_f1_out(74) => \data_f1_out[74]\, data_f1_out(73) => - \data_f1_out[73]\, data_f1_out(72) => \data_f1_out[72]\, - data_f1_out(71) => \data_f1_out[71]\, data_f1_out(70) => - \data_f1_out[70]\, data_f1_out(69) => \data_f1_out[69]\, - data_f1_out(68) => \data_f1_out[68]\, data_f1_out(67) => - \data_f1_out[67]\, data_f1_out(66) => \data_f1_out[66]\, - data_f1_out(65) => \data_f1_out[65]\, data_f1_out(64) => - \data_f1_out[64]\, nb_snapshot_param(0) => - nb_snapshot_param(0), sample_f1_37 => sample_f1_37, - sample_f1_5 => sample_f1_5, sample_f1_38 => sample_f1_38, - sample_f1_6 => sample_f1_6, sample_f1_39 => sample_f1_39, - sample_f1_7 => sample_f1_7, sample_f1_40 => sample_f1_40, - sample_f1_8 => sample_f1_8, sample_f1_41 => sample_f1_41, - sample_f1_9 => sample_f1_9, sample_f1_42 => sample_f1_42, - sample_f1_10 => sample_f1_10, sample_f1_43 => - sample_f1_43, sample_f1_11 => sample_f1_11, sample_f1_61 - => sample_f1_61, sample_f1_62 => sample_f1_62, - sample_f1_63 => sample_f1_63, sample_f1_32 => - sample_f1_32, sample_f1_0 => sample_f1_0, sample_f1_33 - => sample_f1_33, sample_f1_1 => sample_f1_1, - sample_f1_34 => sample_f1_34, sample_f1_2 => sample_f1_2, - sample_f1_35 => sample_f1_35, sample_f1_3 => sample_f1_3, - sample_f1_36 => sample_f1_36, sample_f1_4 => sample_f1_4, - sample_f1_48 => sample_f1_48, sample_f1_49 => - sample_f1_49, sample_f1_50 => sample_f1_50, sample_f1_51 - => sample_f1_51, sample_f1_52 => sample_f1_52, - sample_f1_53 => sample_f1_53, sample_f1_54 => - sample_f1_54, sample_f1_55 => sample_f1_55, sample_f1_56 - => sample_f1_56, sample_f1_57 => sample_f1_57, - sample_f1_58 => sample_f1_58, sample_f1_59 => - sample_f1_59, sample_f1_60 => sample_f1_60, sample_f1_44 - => sample_f1_44, sample_f1_12 => sample_f1_12, - sample_f1_45 => sample_f1_45, sample_f1_13 => - sample_f1_13, sample_f1_46 => sample_f1_46, sample_f1_14 - => sample_f1_14, sample_f1_47 => sample_f1_47, - sample_f1_15 => sample_f1_15, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, data_f1_out_valid => data_f1_out_valid, - N_4 => N_4, I_38_4 => I_38_4, I_24_4 => I_24_4, I_20_12 - => I_20_12, I_13_20 => I_13_20, I_45_4 => I_45_4, I_9_20 - => I_9_20, I_5_20 => I_5_20, I_52_4 => I_52_4, - data_shaping_R1 => data_shaping_R1, data_shaping_R1_0 => - data_shaping_R1_0, I_56_4 => I_56_4, I_31_5 => I_31_5, - enable_f1 => enable_f1, burst_f1 => burst_f1, - sample_f1_val_0 => sample_f1_val_0, start_snapshot_f1 => - start_snapshot_f1); - - lpp_waveform_snapshot_controler_1 : - lpp_waveform_snapshot_controler - port map(delta_f2_f0(9) => delta_f2_f0(9), delta_f2_f0(8) - => delta_f2_f0(8), delta_f2_f0(7) => delta_f2_f0(7), - delta_f2_f0(6) => delta_f2_f0(6), delta_f2_f0(5) => - delta_f2_f0(5), delta_f2_f0(4) => delta_f2_f0(4), - delta_f2_f0(3) => delta_f2_f0(3), delta_f2_f0(2) => - delta_f2_f0(2), delta_f2_f0(1) => delta_f2_f0(1), - delta_f2_f0(0) => delta_f2_f0(0), delta_snapshot(15) => - delta_snapshot(15), delta_snapshot(14) => - delta_snapshot(14), delta_snapshot(13) => - delta_snapshot(13), delta_snapshot(12) => - delta_snapshot(12), delta_snapshot(11) => - delta_snapshot(11), delta_snapshot(10) => - delta_snapshot(10), delta_snapshot(9) => - delta_snapshot(9), delta_snapshot(8) => delta_snapshot(8), - delta_snapshot(7) => delta_snapshot(7), delta_snapshot(6) - => delta_snapshot(6), delta_snapshot(5) => - delta_snapshot(5), delta_snapshot(4) => delta_snapshot(4), - delta_snapshot(3) => delta_snapshot(3), delta_snapshot(2) - => delta_snapshot(2), delta_snapshot(1) => - delta_snapshot(1), delta_snapshot(0) => delta_snapshot(0), - delta_f2_f1(9) => delta_f2_f1(9), delta_f2_f1(8) => - delta_f2_f1(8), delta_f2_f1(7) => delta_f2_f1(7), - delta_f2_f1(6) => delta_f2_f1(6), delta_f2_f1(5) => - delta_f2_f1(5), delta_f2_f1(4) => delta_f2_f1(4), - delta_f2_f1(3) => delta_f2_f1(3), delta_f2_f1(2) => - delta_f2_f1(2), delta_f2_f1(1) => delta_f2_f1(1), - delta_f2_f1(0) => delta_f2_f1(0), start_snapshot_f2 => - start_snapshot_f2, start_snapshot_f1 => start_snapshot_f1, - start_snapshot_f0 => start_snapshot_f0, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, sample_f0_val_0 => - sample_f0_val_0, sample_f2_val => sample_f2_val, - coarse_time_0_c => coarse_time_0_c); - - un7_nb_snapshot_param_more_one_I_20 : XOR2 - port map(A => N_37, B => nb_snapshot_param(4), Y => I_20_12); - - \all_input_valid.3.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - port map(status_new_err(3) => status_new_err(3), - valid_ack(3) => \valid_ack[3]\, valid_out(3) => - \valid_out[3]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - data_f3_out_valid => data_f3_out_valid); - - un7_nb_snapshot_param_more_one_I_52 : XOR2 - port map(A => N_14, B => nb_snapshot_param(9), Y => I_52_4); - - VCC_i : VCC - port map(Y => \VCC\); - - un7_nb_snapshot_param_more_one_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - un7_nb_snapshot_param_more_one_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => nb_snapshot_param(3), - C => nb_snapshot_param(4), Y => N_34); - - un7_nb_snapshot_param_more_one_I_56 : XOR2 - port map(A => N_11, B => nb_snapshot_param(10), Y => I_56_4); - - un7_nb_snapshot_param_more_one_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un7_nb_snapshot_param_more_one_I_19 : NOR2B - port map(A => nb_snapshot_param(3), B => \DWACT_FINC_E[0]\, - Y => N_37); - - un7_nb_snapshot_param_more_one_I_24 : XOR2 - port map(A => N_34, B => nb_snapshot_param(5), Y => I_24_4); - - un7_nb_snapshot_param_more_one_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_19); - - \all_input_valid.1.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - port map(status_new_err(1) => status_new_err(1), - valid_out_i(1) => \valid_out_i[1]\, valid_ack(1) => - \valid_ack[1]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - data_f1_out_valid => data_f1_out_valid); - - un7_nb_snapshot_param_more_one_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => nb_snapshot_param(8), - C => nb_snapshot_param(9), Y => N_11); - - un7_nb_snapshot_param_more_one_I_13 : XOR2 - port map(A => N_42, B => nb_snapshot_param(3), Y => I_13_20); - - un7_nb_snapshot_param_more_one_I_9 : XOR2 - port map(A => N_45, B => nb_snapshot_param(2), Y => I_9_20); - - un7_nb_snapshot_param_more_one_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => nb_snapshot_param(9), - C => nb_snapshot_param(10), Y => N_4); - - un7_nb_snapshot_param_more_one_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => nb_snapshot_param(5), Y => N_29); - - GND_i : GND - port map(Y => \GND\); - - un7_nb_snapshot_param_more_one_I_59 : AND3 - port map(A => nb_snapshot_param(6), B => - nb_snapshot_param(7), C => nb_snapshot_param(8), Y => - \DWACT_FINC_E[5]\); - - lpp_waveform_burst_f3 : lpp_waveform_burst - port map(sample_f3_wdata(95) => sample_f3_wdata(95), - sample_f3_wdata(94) => sample_f3_wdata(94), - sample_f3_wdata(93) => sample_f3_wdata(93), - sample_f3_wdata(92) => sample_f3_wdata(92), - sample_f3_wdata(91) => sample_f3_wdata(91), - sample_f3_wdata(90) => sample_f3_wdata(90), - sample_f3_wdata(89) => sample_f3_wdata(89), - sample_f3_wdata(88) => sample_f3_wdata(88), - sample_f3_wdata(87) => sample_f3_wdata(87), - sample_f3_wdata(86) => sample_f3_wdata(86), - sample_f3_wdata(85) => sample_f3_wdata(85), - sample_f3_wdata(84) => sample_f3_wdata(84), - sample_f3_wdata(83) => sample_f3_wdata(83), - sample_f3_wdata(82) => sample_f3_wdata(82), - sample_f3_wdata(81) => sample_f3_wdata(81), - sample_f3_wdata(80) => sample_f3_wdata(80), - sample_f3_wdata(79) => sample_f3_wdata(79), - sample_f3_wdata(78) => sample_f3_wdata(78), - sample_f3_wdata(77) => sample_f3_wdata(77), - sample_f3_wdata(76) => sample_f3_wdata(76), - sample_f3_wdata(75) => sample_f3_wdata(75), - sample_f3_wdata(74) => sample_f3_wdata(74), - sample_f3_wdata(73) => sample_f3_wdata(73), - sample_f3_wdata(72) => sample_f3_wdata(72), - sample_f3_wdata(71) => sample_f3_wdata(71), - sample_f3_wdata(70) => sample_f3_wdata(70), - sample_f3_wdata(69) => sample_f3_wdata(69), - sample_f3_wdata(68) => sample_f3_wdata(68), - sample_f3_wdata(67) => sample_f3_wdata(67), - sample_f3_wdata(66) => sample_f3_wdata(66), - sample_f3_wdata(65) => sample_f3_wdata(65), - sample_f3_wdata(64) => sample_f3_wdata(64), - sample_f3_wdata(63) => sample_f3_wdata(63), - sample_f3_wdata(62) => sample_f3_wdata(62), - sample_f3_wdata(61) => sample_f3_wdata(61), - sample_f3_wdata(60) => sample_f3_wdata(60), - sample_f3_wdata(59) => sample_f3_wdata(59), - sample_f3_wdata(58) => sample_f3_wdata(58), - sample_f3_wdata(57) => sample_f3_wdata(57), - sample_f3_wdata(56) => sample_f3_wdata(56), - sample_f3_wdata(55) => sample_f3_wdata(55), - sample_f3_wdata(54) => sample_f3_wdata(54), - sample_f3_wdata(53) => sample_f3_wdata(53), - sample_f3_wdata(52) => sample_f3_wdata(52), - sample_f3_wdata(51) => sample_f3_wdata(51), - sample_f3_wdata(50) => sample_f3_wdata(50), - sample_f3_wdata(49) => sample_f3_wdata(49), - sample_f3_wdata(48) => sample_f3_wdata(48), - sample_f3_wdata(47) => sample_f3_wdata(47), - sample_f3_wdata(46) => sample_f3_wdata(46), - sample_f3_wdata(45) => sample_f3_wdata(45), - sample_f3_wdata(44) => sample_f3_wdata(44), - sample_f3_wdata(43) => sample_f3_wdata(43), - sample_f3_wdata(42) => sample_f3_wdata(42), - sample_f3_wdata(41) => sample_f3_wdata(41), - sample_f3_wdata(40) => sample_f3_wdata(40), - sample_f3_wdata(39) => sample_f3_wdata(39), - sample_f3_wdata(38) => sample_f3_wdata(38), - sample_f3_wdata(37) => sample_f3_wdata(37), - sample_f3_wdata(36) => sample_f3_wdata(36), - sample_f3_wdata(35) => sample_f3_wdata(35), - sample_f3_wdata(34) => sample_f3_wdata(34), - sample_f3_wdata(33) => sample_f3_wdata(33), - sample_f3_wdata(32) => sample_f3_wdata(32), - sample_f3_wdata(31) => sample_f3_wdata(31), - sample_f3_wdata(30) => sample_f3_wdata(30), - sample_f3_wdata(29) => sample_f3_wdata(29), - sample_f3_wdata(28) => sample_f3_wdata(28), - sample_f3_wdata(27) => sample_f3_wdata(27), - sample_f3_wdata(26) => sample_f3_wdata(26), - sample_f3_wdata(25) => sample_f3_wdata(25), - sample_f3_wdata(24) => sample_f3_wdata(24), - sample_f3_wdata(23) => sample_f3_wdata(23), - sample_f3_wdata(22) => sample_f3_wdata(22), - sample_f3_wdata(21) => sample_f3_wdata(21), - sample_f3_wdata(20) => sample_f3_wdata(20), - sample_f3_wdata(19) => sample_f3_wdata(19), - sample_f3_wdata(18) => sample_f3_wdata(18), - sample_f3_wdata(17) => sample_f3_wdata(17), - sample_f3_wdata(16) => sample_f3_wdata(16), - sample_f3_wdata(15) => sample_f3_wdata(15), - sample_f3_wdata(14) => sample_f3_wdata(14), - sample_f3_wdata(13) => sample_f3_wdata(13), - sample_f3_wdata(12) => sample_f3_wdata(12), - sample_f3_wdata(11) => sample_f3_wdata(11), - sample_f3_wdata(10) => sample_f3_wdata(10), - sample_f3_wdata(9) => sample_f3_wdata(9), - sample_f3_wdata(8) => sample_f3_wdata(8), - sample_f3_wdata(7) => sample_f3_wdata(7), - sample_f3_wdata(6) => sample_f3_wdata(6), - sample_f3_wdata(5) => sample_f3_wdata(5), - sample_f3_wdata(4) => sample_f3_wdata(4), - sample_f3_wdata(3) => sample_f3_wdata(3), - sample_f3_wdata(2) => sample_f3_wdata(2), - sample_f3_wdata(1) => sample_f3_wdata(1), - sample_f3_wdata(0) => sample_f3_wdata(0), - data_f3_out(159) => \data_f3_out[159]\, data_f3_out(158) - => \data_f3_out[158]\, data_f3_out(157) => - \data_f3_out[157]\, data_f3_out(156) => - \data_f3_out[156]\, data_f3_out(155) => - \data_f3_out[155]\, data_f3_out(154) => - \data_f3_out[154]\, data_f3_out(153) => - \data_f3_out[153]\, data_f3_out(152) => - \data_f3_out[152]\, data_f3_out(151) => - \data_f3_out[151]\, data_f3_out(150) => - \data_f3_out[150]\, data_f3_out(149) => - \data_f3_out[149]\, data_f3_out(148) => - \data_f3_out[148]\, data_f3_out(147) => - \data_f3_out[147]\, data_f3_out(146) => - \data_f3_out[146]\, data_f3_out(145) => - \data_f3_out[145]\, data_f3_out(144) => - \data_f3_out[144]\, data_f3_out(143) => - \data_f3_out[143]\, data_f3_out(142) => - \data_f3_out[142]\, data_f3_out(141) => - \data_f3_out[141]\, data_f3_out(140) => - \data_f3_out[140]\, data_f3_out(139) => - \data_f3_out[139]\, data_f3_out(138) => - \data_f3_out[138]\, data_f3_out(137) => - \data_f3_out[137]\, data_f3_out(136) => - \data_f3_out[136]\, data_f3_out(135) => - \data_f3_out[135]\, data_f3_out(134) => - \data_f3_out[134]\, data_f3_out(133) => - \data_f3_out[133]\, data_f3_out(132) => - \data_f3_out[132]\, data_f3_out(131) => - \data_f3_out[131]\, data_f3_out(130) => - \data_f3_out[130]\, data_f3_out(129) => - \data_f3_out[129]\, data_f3_out(128) => - \data_f3_out[128]\, data_f3_out(127) => - \data_f3_out[127]\, data_f3_out(126) => - \data_f3_out[126]\, data_f3_out(125) => - \data_f3_out[125]\, data_f3_out(124) => - \data_f3_out[124]\, data_f3_out(123) => - \data_f3_out[123]\, data_f3_out(122) => - \data_f3_out[122]\, data_f3_out(121) => - \data_f3_out[121]\, data_f3_out(120) => - \data_f3_out[120]\, data_f3_out(119) => - \data_f3_out[119]\, data_f3_out(118) => - \data_f3_out[118]\, data_f3_out(117) => - \data_f3_out[117]\, data_f3_out(116) => - \data_f3_out[116]\, data_f3_out(115) => - \data_f3_out[115]\, data_f3_out(114) => - \data_f3_out[114]\, data_f3_out(113) => - \data_f3_out[113]\, data_f3_out(112) => - \data_f3_out[112]\, data_f3_out(111) => - \data_f3_out[111]\, data_f3_out(110) => - \data_f3_out[110]\, data_f3_out(109) => - \data_f3_out[109]\, data_f3_out(108) => - \data_f3_out[108]\, data_f3_out(107) => - \data_f3_out[107]\, data_f3_out(106) => - \data_f3_out[106]\, data_f3_out(105) => - \data_f3_out[105]\, data_f3_out(104) => - \data_f3_out[104]\, data_f3_out(103) => - \data_f3_out[103]\, data_f3_out(102) => - \data_f3_out[102]\, data_f3_out(101) => - \data_f3_out[101]\, data_f3_out(100) => - \data_f3_out[100]\, data_f3_out(99) => \data_f3_out[99]\, - data_f3_out(98) => \data_f3_out[98]\, data_f3_out(97) => - \data_f3_out[97]\, data_f3_out(96) => \data_f3_out[96]\, - data_f3_out(95) => \data_f3_out[95]\, data_f3_out(94) => - \data_f3_out[94]\, data_f3_out(93) => \data_f3_out[93]\, - data_f3_out(92) => \data_f3_out[92]\, data_f3_out(91) => - \data_f3_out[91]\, data_f3_out(90) => \data_f3_out[90]\, - data_f3_out(89) => \data_f3_out[89]\, data_f3_out(88) => - \data_f3_out[88]\, data_f3_out(87) => \data_f3_out[87]\, - data_f3_out(86) => \data_f3_out[86]\, data_f3_out(85) => - \data_f3_out[85]\, data_f3_out(84) => \data_f3_out[84]\, - data_f3_out(83) => \data_f3_out[83]\, data_f3_out(82) => - \data_f3_out[82]\, data_f3_out(81) => \data_f3_out[81]\, - data_f3_out(80) => \data_f3_out[80]\, data_f3_out(79) => - \data_f3_out[79]\, data_f3_out(78) => \data_f3_out[78]\, - data_f3_out(77) => \data_f3_out[77]\, data_f3_out(76) => - \data_f3_out[76]\, data_f3_out(75) => \data_f3_out[75]\, - data_f3_out(74) => \data_f3_out[74]\, data_f3_out(73) => - \data_f3_out[73]\, data_f3_out(72) => \data_f3_out[72]\, - data_f3_out(71) => \data_f3_out[71]\, data_f3_out(70) => - \data_f3_out[70]\, data_f3_out(69) => \data_f3_out[69]\, - data_f3_out(68) => \data_f3_out[68]\, data_f3_out(67) => - \data_f3_out[67]\, data_f3_out(66) => \data_f3_out[66]\, - data_f3_out(65) => \data_f3_out[65]\, data_f3_out(64) => - \data_f3_out[64]\, HRESETn_c => HRESETn_c, HCLK_c => - HCLK_c, data_f3_out_valid => data_f3_out_valid, enable_f3 - => enable_f3, sample_f3_val => sample_f3_val); - - \all_input_valid.2.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - port map(status_new_err(2) => status_new_err(2), - valid_ack(2) => \valid_ack[2]\, valid_out(2) => - \valid_out[2]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - data_f2_out_valid => data_f2_out_valid); - - un7_nb_snapshot_param_more_one_I_41 : AND2 - port map(A => nb_snapshot_param(6), B => - nb_snapshot_param(7), Y => \DWACT_FINC_E[3]\); - - un7_nb_snapshot_param_more_one_I_38 : XOR2 - port map(A => N_24, B => nb_snapshot_param(7), Y => I_38_4); - - \all_input_valid.0.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - port map(status_new_err(0) => status_new_err(0), - valid_ack(0) => \valid_ack[0]\, valid_out(0) => - \valid_out[0]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - data_f0_out_valid => data_f0_out_valid); - - un7_nb_snapshot_param_more_one_I_27 : AND2 - port map(A => nb_snapshot_param(3), B => - nb_snapshot_param(4), Y => \DWACT_FINC_E[1]\); - - un7_nb_snapshot_param_more_one_I_34 : AND3 - port map(A => nb_snapshot_param(3), B => - nb_snapshot_param(4), C => nb_snapshot_param(5), Y => - \DWACT_FINC_E[2]\); - - un7_nb_snapshot_param_more_one_I_8 : NOR2B - port map(A => nb_snapshot_param(1), B => - nb_snapshot_param(0), Y => N_45); - - lpp_waveform_fifo_1 : lpp_waveform_fifo - port map(data_wen(3) => \data_wen[3]\, data_wen(2) => - \data_wen[2]\, data_wen(1) => \data_wen[1]\, data_wen(0) - => \data_wen[0]\, data_ren(3) => \data_ren[3]\, - data_ren(2) => \data_ren[2]\, data_ren(1) => - \data_ren[1]\, data_ren(0) => \data_ren[0]\, ready_i_0(3) - => \ready_i_0[3]\, ready_i_0(2) => \ready_i_0[2]\, - ready_i_0(1) => \ready_i_0[1]\, ready_i_0(0) => - \ready_i_0[0]\, time_ren(3) => \time_ren[3]\, time_ren(2) - => \time_ren[2]\, time_ren(1) => \time_ren[1]\, - time_ren(0) => \time_ren[0]\, time_wen(3) => - \time_wen[3]\, time_wen(2) => \time_wen[2]\, time_wen(1) - => \time_wen[1]\, time_wen(0) => \time_wen[0]\, - wdata(31) => \wdata[31]\, wdata(30) => \wdata[30]\, - wdata(29) => \wdata[29]\, wdata(28) => \wdata[28]\, - wdata(27) => \wdata[27]\, wdata(26) => \wdata[26]\, - wdata(25) => \wdata[25]\, wdata(24) => \wdata[24]\, - wdata(23) => \wdata[23]\, wdata(22) => \wdata[22]\, - wdata(21) => \wdata[21]\, wdata(20) => \wdata[20]\, - wdata(19) => \wdata[19]\, wdata(18) => \wdata[18]\, - wdata(17) => \wdata[17]\, wdata(16) => \wdata[16]\, - wdata(15) => \wdata[15]\, wdata(14) => \wdata[14]\, - wdata(13) => \wdata[13]\, wdata(12) => \wdata[12]\, - wdata(11) => \wdata[11]\, wdata(10) => \wdata[10]\, - wdata(9) => \wdata[9]\, wdata(8) => \wdata[8]\, wdata(7) - => \wdata[7]\, wdata(6) => \wdata[6]\, wdata(5) => - \wdata[5]\, wdata(4) => \wdata[4]\, wdata(3) => - \wdata[3]\, wdata(2) => \wdata[2]\, wdata(1) => - \wdata[1]\, wdata(0) => \wdata[0]\, hwdata_c(31) => - hwdata_c(31), hwdata_c(30) => hwdata_c(30), hwdata_c(29) - => hwdata_c(29), hwdata_c(28) => hwdata_c(28), - hwdata_c(27) => hwdata_c(27), hwdata_c(26) => - hwdata_c(26), hwdata_c(25) => hwdata_c(25), hwdata_c(24) - => hwdata_c(24), hwdata_c(23) => hwdata_c(23), - hwdata_c(22) => hwdata_c(22), hwdata_c(21) => - hwdata_c(21), hwdata_c(20) => hwdata_c(20), hwdata_c(19) - => hwdata_c(19), hwdata_c(18) => hwdata_c(18), - hwdata_c(17) => hwdata_c(17), hwdata_c(16) => - hwdata_c(16), hwdata_c(15) => hwdata_c(15), hwdata_c(14) - => hwdata_c(14), hwdata_c(13) => hwdata_c(13), - hwdata_c(12) => hwdata_c(12), hwdata_c(11) => - hwdata_c(11), hwdata_c(10) => hwdata_c(10), hwdata_c(9) - => hwdata_c(9), hwdata_c(8) => hwdata_c(8), hwdata_c(7) - => hwdata_c(7), hwdata_c(6) => hwdata_c(6), hwdata_c(5) - => hwdata_c(5), hwdata_c(4) => hwdata_c(4), hwdata_c(3) - => hwdata_c(3), hwdata_c(2) => hwdata_c(2), hwdata_c(1) - => hwdata_c(1), hwdata_c(0) => hwdata_c(0), time_ren_1z - => time_ren, data_ren_1z => data_ren, un20_time_write - => un20_time_write, un13_time_write => un13_time_write, - HRESETn_c => HRESETn_c, lpp_waveform_fifo_VCC => - lpp_waveform_VCC, lpp_waveform_fifo_GND => - lpp_waveform_GND, HCLK_c => HCLK_c); - - lpp_waveform_snapshot_f0 : lpp_waveform_snapshot_160_11 - port map(sample_f0_wdata_95 => sample_f0_wdata_95, - sample_f0_wdata_94 => sample_f0_wdata_94, - sample_f0_wdata_93 => sample_f0_wdata_93, - sample_f0_wdata_92 => sample_f0_wdata_92, - sample_f0_wdata_91 => sample_f0_wdata_91, - sample_f0_wdata_90 => sample_f0_wdata_90, - sample_f0_wdata_89 => sample_f0_wdata_89, - sample_f0_wdata_88 => sample_f0_wdata_88, - sample_f0_wdata_87 => sample_f0_wdata_87, - sample_f0_wdata_86 => sample_f0_wdata_86, - sample_f0_wdata_85 => sample_f0_wdata_85, - sample_f0_wdata_84 => sample_f0_wdata_84, - sample_f0_wdata_83 => sample_f0_wdata_83, - sample_f0_wdata_82 => sample_f0_wdata_82, - sample_f0_wdata_81 => sample_f0_wdata_81, - sample_f0_wdata_80 => sample_f0_wdata_80, - sample_f0_wdata_79 => sample_f0_wdata_79, - sample_f0_wdata_78 => sample_f0_wdata_78, - sample_f0_wdata_77 => sample_f0_wdata_77, - sample_f0_wdata_76 => sample_f0_wdata_76, - sample_f0_wdata_75 => sample_f0_wdata_75, - sample_f0_wdata_74 => sample_f0_wdata_74, - sample_f0_wdata_73 => sample_f0_wdata_73, - sample_f0_wdata_72 => sample_f0_wdata_72, - sample_f0_wdata_71 => sample_f0_wdata_71, - sample_f0_wdata_70 => sample_f0_wdata_70, - sample_f0_wdata_69 => sample_f0_wdata_69, - sample_f0_wdata_68 => sample_f0_wdata_68, - sample_f0_wdata_67 => sample_f0_wdata_67, - sample_f0_wdata_66 => sample_f0_wdata_66, - sample_f0_wdata_65 => sample_f0_wdata_65, - sample_f0_wdata_64 => sample_f0_wdata_64, - sample_f0_wdata_63 => sample_f0_wdata_63, - sample_f0_wdata_62 => sample_f0_wdata_62, - sample_f0_wdata_61 => sample_f0_wdata_61, - sample_f0_wdata_60 => sample_f0_wdata_60, - sample_f0_wdata_59 => sample_f0_wdata_59, - sample_f0_wdata_58 => sample_f0_wdata_58, - sample_f0_wdata_57 => sample_f0_wdata_57, - sample_f0_wdata_56 => sample_f0_wdata_56, - sample_f0_wdata_55 => sample_f0_wdata_55, - sample_f0_wdata_54 => sample_f0_wdata_54, - sample_f0_wdata_53 => sample_f0_wdata_53, - sample_f0_wdata_52 => sample_f0_wdata_52, - sample_f0_wdata_51 => sample_f0_wdata_51, - sample_f0_wdata_50 => sample_f0_wdata_50, - sample_f0_wdata_49 => sample_f0_wdata_49, - sample_f0_wdata_48 => sample_f0_wdata_48, - sample_f0_wdata_15 => sample_f0_wdata_15, - sample_f0_wdata_14 => sample_f0_wdata_14, - sample_f0_wdata_13 => sample_f0_wdata_13, - sample_f0_wdata_12 => sample_f0_wdata_12, - sample_f0_wdata_11 => sample_f0_wdata_11, - sample_f0_wdata_10 => sample_f0_wdata_10, - sample_f0_wdata_9 => sample_f0_wdata_9, sample_f0_wdata_8 - => sample_f0_wdata_8, sample_f0_wdata_7 => - sample_f0_wdata_7, sample_f0_wdata_6 => sample_f0_wdata_6, - sample_f0_wdata_5 => sample_f0_wdata_5, sample_f0_wdata_4 - => sample_f0_wdata_4, sample_f0_wdata_3 => - sample_f0_wdata_3, sample_f0_wdata_2 => sample_f0_wdata_2, - sample_f0_wdata_1 => sample_f0_wdata_1, sample_f0_wdata_0 - => sample_f0_wdata_0, data_f0_out(159) => - \data_f0_out[159]\, data_f0_out(158) => - \data_f0_out[158]\, data_f0_out(157) => - \data_f0_out[157]\, data_f0_out(156) => - \data_f0_out[156]\, data_f0_out(155) => - \data_f0_out[155]\, data_f0_out(154) => - \data_f0_out[154]\, data_f0_out(153) => - \data_f0_out[153]\, data_f0_out(152) => - \data_f0_out[152]\, data_f0_out(151) => - \data_f0_out[151]\, data_f0_out(150) => - \data_f0_out[150]\, data_f0_out(149) => - \data_f0_out[149]\, data_f0_out(148) => - \data_f0_out[148]\, data_f0_out(147) => - \data_f0_out[147]\, data_f0_out(146) => - \data_f0_out[146]\, data_f0_out(145) => - \data_f0_out[145]\, data_f0_out(144) => - \data_f0_out[144]\, data_f0_out(143) => - \data_f0_out[143]\, data_f0_out(142) => - \data_f0_out[142]\, data_f0_out(141) => - \data_f0_out[141]\, data_f0_out(140) => - \data_f0_out[140]\, data_f0_out(139) => - \data_f0_out[139]\, data_f0_out(138) => - \data_f0_out[138]\, data_f0_out(137) => - \data_f0_out[137]\, data_f0_out(136) => - \data_f0_out[136]\, data_f0_out(135) => - \data_f0_out[135]\, data_f0_out(134) => - \data_f0_out[134]\, data_f0_out(133) => - \data_f0_out[133]\, data_f0_out(132) => - \data_f0_out[132]\, data_f0_out(131) => - \data_f0_out[131]\, data_f0_out(130) => - \data_f0_out[130]\, data_f0_out(129) => - \data_f0_out[129]\, data_f0_out(128) => - \data_f0_out[128]\, data_f0_out(127) => - \data_f0_out[127]\, data_f0_out(126) => - \data_f0_out[126]\, data_f0_out(125) => - \data_f0_out[125]\, data_f0_out(124) => - \data_f0_out[124]\, data_f0_out(123) => - \data_f0_out[123]\, data_f0_out(122) => - \data_f0_out[122]\, data_f0_out(121) => - \data_f0_out[121]\, data_f0_out(120) => - \data_f0_out[120]\, data_f0_out(119) => - \data_f0_out[119]\, data_f0_out(118) => - \data_f0_out[118]\, data_f0_out(117) => - \data_f0_out[117]\, data_f0_out(116) => - \data_f0_out[116]\, data_f0_out(115) => - \data_f0_out[115]\, data_f0_out(114) => - \data_f0_out[114]\, data_f0_out(113) => - \data_f0_out[113]\, data_f0_out(112) => - \data_f0_out[112]\, data_f0_out(111) => - \data_f0_out[111]\, data_f0_out(110) => - \data_f0_out[110]\, data_f0_out(109) => - \data_f0_out[109]\, data_f0_out(108) => - \data_f0_out[108]\, data_f0_out(107) => - \data_f0_out[107]\, data_f0_out(106) => - \data_f0_out[106]\, data_f0_out(105) => - \data_f0_out[105]\, data_f0_out(104) => - \data_f0_out[104]\, data_f0_out(103) => - \data_f0_out[103]\, data_f0_out(102) => - \data_f0_out[102]\, data_f0_out(101) => - \data_f0_out[101]\, data_f0_out(100) => - \data_f0_out[100]\, data_f0_out(99) => \data_f0_out[99]\, - data_f0_out(98) => \data_f0_out[98]\, data_f0_out(97) => - \data_f0_out[97]\, data_f0_out(96) => \data_f0_out[96]\, - data_f0_out(95) => \data_f0_out[95]\, data_f0_out(94) => - \data_f0_out[94]\, data_f0_out(93) => \data_f0_out[93]\, - data_f0_out(92) => \data_f0_out[92]\, data_f0_out(91) => - \data_f0_out[91]\, data_f0_out(90) => \data_f0_out[90]\, - data_f0_out(89) => \data_f0_out[89]\, data_f0_out(88) => - \data_f0_out[88]\, data_f0_out(87) => \data_f0_out[87]\, - data_f0_out(86) => \data_f0_out[86]\, data_f0_out(85) => - \data_f0_out[85]\, data_f0_out(84) => \data_f0_out[84]\, - data_f0_out(83) => \data_f0_out[83]\, data_f0_out(82) => - \data_f0_out[82]\, data_f0_out(81) => \data_f0_out[81]\, - data_f0_out(80) => \data_f0_out[80]\, data_f0_out(79) => - \data_f0_out[79]\, data_f0_out(78) => \data_f0_out[78]\, - data_f0_out(77) => \data_f0_out[77]\, data_f0_out(76) => - \data_f0_out[76]\, data_f0_out(75) => \data_f0_out[75]\, - data_f0_out(74) => \data_f0_out[74]\, data_f0_out(73) => - \data_f0_out[73]\, data_f0_out(72) => \data_f0_out[72]\, - data_f0_out(71) => \data_f0_out[71]\, data_f0_out(70) => - \data_f0_out[70]\, data_f0_out(69) => \data_f0_out[69]\, - data_f0_out(68) => \data_f0_out[68]\, data_f0_out(67) => - \data_f0_out[67]\, data_f0_out(66) => \data_f0_out[66]\, - data_f0_out(65) => \data_f0_out[65]\, data_f0_out(64) => - \data_f0_out[64]\, nb_snapshot_param(10) => - nb_snapshot_param(10), nb_snapshot_param(9) => - nb_snapshot_param(9), nb_snapshot_param(8) => - nb_snapshot_param(8), nb_snapshot_param(7) => - nb_snapshot_param(7), nb_snapshot_param(6) => - nb_snapshot_param(6), nb_snapshot_param(5) => - nb_snapshot_param(5), nb_snapshot_param(4) => - nb_snapshot_param(4), nb_snapshot_param(3) => - nb_snapshot_param(3), nb_snapshot_param(2) => - nb_snapshot_param(2), nb_snapshot_param(1) => - nb_snapshot_param(1), nb_snapshot_param(0) => - nb_snapshot_param(0), sample_f0_37 => sample_f0_37, - sample_f0_5 => sample_f0_5, sample_f0_38 => sample_f0_38, - sample_f0_6 => sample_f0_6, sample_f0_39 => sample_f0_39, - sample_f0_7 => sample_f0_7, sample_f0_40 => sample_f0_40, - sample_f0_8 => sample_f0_8, sample_f0_41 => sample_f0_41, - sample_f0_9 => sample_f0_9, sample_f0_42 => sample_f0_42, - sample_f0_10 => sample_f0_10, sample_f0_43 => - sample_f0_43, sample_f0_11 => sample_f0_11, sample_f0_61 - => sample_f0_61, sample_f0_62 => sample_f0_62, - sample_f0_63 => sample_f0_63, sample_f0_32 => - sample_f0_32, sample_f0_0 => sample_f0_0, sample_f0_33 - => sample_f0_33, sample_f0_1 => sample_f0_1, - sample_f0_34 => sample_f0_34, sample_f0_2 => sample_f0_2, - sample_f0_35 => sample_f0_35, sample_f0_3 => sample_f0_3, - sample_f0_36 => sample_f0_36, sample_f0_4 => sample_f0_4, - sample_f0_48 => sample_f0_48, sample_f0_49 => - sample_f0_49, sample_f0_50 => sample_f0_50, sample_f0_51 - => sample_f0_51, sample_f0_52 => sample_f0_52, - sample_f0_53 => sample_f0_53, sample_f0_54 => - sample_f0_54, sample_f0_55 => sample_f0_55, sample_f0_56 - => sample_f0_56, sample_f0_57 => sample_f0_57, - sample_f0_58 => sample_f0_58, sample_f0_59 => - sample_f0_59, sample_f0_60 => sample_f0_60, sample_f0_44 - => sample_f0_44, sample_f0_12 => sample_f0_12, - sample_f0_45 => sample_f0_45, sample_f0_13 => - sample_f0_13, sample_f0_46 => sample_f0_46, sample_f0_14 - => sample_f0_14, sample_f0_47 => sample_f0_47, - sample_f0_15 => sample_f0_15, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, data_f0_out_valid => data_f0_out_valid, - enable_f0 => enable_f0, data_shaping_R0 => - data_shaping_R0, data_shaping_R0_0 => data_shaping_R0_0, - start_snapshot_f0 => start_snapshot_f0, sample_f0_val_0 - => sample_f0_val_0, burst_f0 => burst_f0); - - un7_nb_snapshot_param_more_one_I_31 : XOR2 - port map(A => N_29, B => nb_snapshot_param(6), Y => I_31_5); - - lpp_waveform_snapshot_f2 : - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 - port map(sample_f2_wdata(95) => sample_f2_wdata(95), - sample_f2_wdata(94) => sample_f2_wdata(94), - sample_f2_wdata(93) => sample_f2_wdata(93), - sample_f2_wdata(92) => sample_f2_wdata(92), - sample_f2_wdata(91) => sample_f2_wdata(91), - sample_f2_wdata(90) => sample_f2_wdata(90), - sample_f2_wdata(89) => sample_f2_wdata(89), - sample_f2_wdata(88) => sample_f2_wdata(88), - sample_f2_wdata(87) => sample_f2_wdata(87), - sample_f2_wdata(86) => sample_f2_wdata(86), - sample_f2_wdata(85) => sample_f2_wdata(85), - sample_f2_wdata(84) => sample_f2_wdata(84), - sample_f2_wdata(83) => sample_f2_wdata(83), - sample_f2_wdata(82) => sample_f2_wdata(82), - sample_f2_wdata(81) => sample_f2_wdata(81), - sample_f2_wdata(80) => sample_f2_wdata(80), - sample_f2_wdata(79) => sample_f2_wdata(79), - sample_f2_wdata(78) => sample_f2_wdata(78), - sample_f2_wdata(77) => sample_f2_wdata(77), - sample_f2_wdata(76) => sample_f2_wdata(76), - sample_f2_wdata(75) => sample_f2_wdata(75), - sample_f2_wdata(74) => sample_f2_wdata(74), - sample_f2_wdata(73) => sample_f2_wdata(73), - sample_f2_wdata(72) => sample_f2_wdata(72), - sample_f2_wdata(71) => sample_f2_wdata(71), - sample_f2_wdata(70) => sample_f2_wdata(70), - sample_f2_wdata(69) => sample_f2_wdata(69), - sample_f2_wdata(68) => sample_f2_wdata(68), - sample_f2_wdata(67) => sample_f2_wdata(67), - sample_f2_wdata(66) => sample_f2_wdata(66), - sample_f2_wdata(65) => sample_f2_wdata(65), - sample_f2_wdata(64) => sample_f2_wdata(64), - sample_f2_wdata(63) => sample_f2_wdata(63), - sample_f2_wdata(62) => sample_f2_wdata(62), - sample_f2_wdata(61) => sample_f2_wdata(61), - sample_f2_wdata(60) => sample_f2_wdata(60), - sample_f2_wdata(59) => sample_f2_wdata(59), - sample_f2_wdata(58) => sample_f2_wdata(58), - sample_f2_wdata(57) => sample_f2_wdata(57), - sample_f2_wdata(56) => sample_f2_wdata(56), - sample_f2_wdata(55) => sample_f2_wdata(55), - sample_f2_wdata(54) => sample_f2_wdata(54), - sample_f2_wdata(53) => sample_f2_wdata(53), - sample_f2_wdata(52) => sample_f2_wdata(52), - sample_f2_wdata(51) => sample_f2_wdata(51), - sample_f2_wdata(50) => sample_f2_wdata(50), - sample_f2_wdata(49) => sample_f2_wdata(49), - sample_f2_wdata(48) => sample_f2_wdata(48), - sample_f2_wdata(47) => sample_f2_wdata(47), - sample_f2_wdata(46) => sample_f2_wdata(46), - sample_f2_wdata(45) => sample_f2_wdata(45), - sample_f2_wdata(44) => sample_f2_wdata(44), - sample_f2_wdata(43) => sample_f2_wdata(43), - sample_f2_wdata(42) => sample_f2_wdata(42), - sample_f2_wdata(41) => sample_f2_wdata(41), - sample_f2_wdata(40) => sample_f2_wdata(40), - sample_f2_wdata(39) => sample_f2_wdata(39), - sample_f2_wdata(38) => sample_f2_wdata(38), - sample_f2_wdata(37) => sample_f2_wdata(37), - sample_f2_wdata(36) => sample_f2_wdata(36), - sample_f2_wdata(35) => sample_f2_wdata(35), - sample_f2_wdata(34) => sample_f2_wdata(34), - sample_f2_wdata(33) => sample_f2_wdata(33), - sample_f2_wdata(32) => sample_f2_wdata(32), - sample_f2_wdata(31) => sample_f2_wdata(31), - sample_f2_wdata(30) => sample_f2_wdata(30), - sample_f2_wdata(29) => sample_f2_wdata(29), - sample_f2_wdata(28) => sample_f2_wdata(28), - sample_f2_wdata(27) => sample_f2_wdata(27), - sample_f2_wdata(26) => sample_f2_wdata(26), - sample_f2_wdata(25) => sample_f2_wdata(25), - sample_f2_wdata(24) => sample_f2_wdata(24), - sample_f2_wdata(23) => sample_f2_wdata(23), - sample_f2_wdata(22) => sample_f2_wdata(22), - sample_f2_wdata(21) => sample_f2_wdata(21), - sample_f2_wdata(20) => sample_f2_wdata(20), - sample_f2_wdata(19) => sample_f2_wdata(19), - sample_f2_wdata(18) => sample_f2_wdata(18), - sample_f2_wdata(17) => sample_f2_wdata(17), - sample_f2_wdata(16) => sample_f2_wdata(16), - sample_f2_wdata(15) => sample_f2_wdata(15), - sample_f2_wdata(14) => sample_f2_wdata(14), - sample_f2_wdata(13) => sample_f2_wdata(13), - sample_f2_wdata(12) => sample_f2_wdata(12), - sample_f2_wdata(11) => sample_f2_wdata(11), - sample_f2_wdata(10) => sample_f2_wdata(10), - sample_f2_wdata(9) => sample_f2_wdata(9), - sample_f2_wdata(8) => sample_f2_wdata(8), - sample_f2_wdata(7) => sample_f2_wdata(7), - sample_f2_wdata(6) => sample_f2_wdata(6), - sample_f2_wdata(5) => sample_f2_wdata(5), - sample_f2_wdata(4) => sample_f2_wdata(4), - sample_f2_wdata(3) => sample_f2_wdata(3), - sample_f2_wdata(2) => sample_f2_wdata(2), - sample_f2_wdata(1) => sample_f2_wdata(1), - sample_f2_wdata(0) => sample_f2_wdata(0), - data_f2_out(159) => \data_f2_out[159]\, data_f2_out(158) - => \data_f2_out[158]\, data_f2_out(157) => - \data_f2_out[157]\, data_f2_out(156) => - \data_f2_out[156]\, data_f2_out(155) => - \data_f2_out[155]\, data_f2_out(154) => - \data_f2_out[154]\, data_f2_out(153) => - \data_f2_out[153]\, data_f2_out(152) => - \data_f2_out[152]\, data_f2_out(151) => - \data_f2_out[151]\, data_f2_out(150) => - \data_f2_out[150]\, data_f2_out(149) => - \data_f2_out[149]\, data_f2_out(148) => - \data_f2_out[148]\, data_f2_out(147) => - \data_f2_out[147]\, data_f2_out(146) => - \data_f2_out[146]\, data_f2_out(145) => - \data_f2_out[145]\, data_f2_out(144) => - \data_f2_out[144]\, data_f2_out(143) => - \data_f2_out[143]\, data_f2_out(142) => - \data_f2_out[142]\, data_f2_out(141) => - \data_f2_out[141]\, data_f2_out(140) => - \data_f2_out[140]\, data_f2_out(139) => - \data_f2_out[139]\, data_f2_out(138) => - \data_f2_out[138]\, data_f2_out(137) => - \data_f2_out[137]\, data_f2_out(136) => - \data_f2_out[136]\, data_f2_out(135) => - \data_f2_out[135]\, data_f2_out(134) => - \data_f2_out[134]\, data_f2_out(133) => - \data_f2_out[133]\, data_f2_out(132) => - \data_f2_out[132]\, data_f2_out(131) => - \data_f2_out[131]\, data_f2_out(130) => - \data_f2_out[130]\, data_f2_out(129) => - \data_f2_out[129]\, data_f2_out(128) => - \data_f2_out[128]\, data_f2_out(127) => - \data_f2_out[127]\, data_f2_out(126) => - \data_f2_out[126]\, data_f2_out(125) => - \data_f2_out[125]\, data_f2_out(124) => - \data_f2_out[124]\, data_f2_out(123) => - \data_f2_out[123]\, data_f2_out(122) => - \data_f2_out[122]\, data_f2_out(121) => - \data_f2_out[121]\, data_f2_out(120) => - \data_f2_out[120]\, data_f2_out(119) => - \data_f2_out[119]\, data_f2_out(118) => - \data_f2_out[118]\, data_f2_out(117) => - \data_f2_out[117]\, data_f2_out(116) => - \data_f2_out[116]\, data_f2_out(115) => - \data_f2_out[115]\, data_f2_out(114) => - \data_f2_out[114]\, data_f2_out(113) => - \data_f2_out[113]\, data_f2_out(112) => - \data_f2_out[112]\, data_f2_out(111) => - \data_f2_out[111]\, data_f2_out(110) => - \data_f2_out[110]\, data_f2_out(109) => - \data_f2_out[109]\, data_f2_out(108) => - \data_f2_out[108]\, data_f2_out(107) => - \data_f2_out[107]\, data_f2_out(106) => - \data_f2_out[106]\, data_f2_out(105) => - \data_f2_out[105]\, data_f2_out(104) => - \data_f2_out[104]\, data_f2_out(103) => - \data_f2_out[103]\, data_f2_out(102) => - \data_f2_out[102]\, data_f2_out(101) => - \data_f2_out[101]\, data_f2_out(100) => - \data_f2_out[100]\, data_f2_out(99) => \data_f2_out[99]\, - data_f2_out(98) => \data_f2_out[98]\, data_f2_out(97) => - \data_f2_out[97]\, data_f2_out(96) => \data_f2_out[96]\, - data_f2_out(95) => \data_f2_out[95]\, data_f2_out(94) => - \data_f2_out[94]\, data_f2_out(93) => \data_f2_out[93]\, - data_f2_out(92) => \data_f2_out[92]\, data_f2_out(91) => - \data_f2_out[91]\, data_f2_out(90) => \data_f2_out[90]\, - data_f2_out(89) => \data_f2_out[89]\, data_f2_out(88) => - \data_f2_out[88]\, data_f2_out(87) => \data_f2_out[87]\, - data_f2_out(86) => \data_f2_out[86]\, data_f2_out(85) => - \data_f2_out[85]\, data_f2_out(84) => \data_f2_out[84]\, - data_f2_out(83) => \data_f2_out[83]\, data_f2_out(82) => - \data_f2_out[82]\, data_f2_out(81) => \data_f2_out[81]\, - data_f2_out(80) => \data_f2_out[80]\, data_f2_out(79) => - \data_f2_out[79]\, data_f2_out(78) => \data_f2_out[78]\, - data_f2_out(77) => \data_f2_out[77]\, data_f2_out(76) => - \data_f2_out[76]\, data_f2_out(75) => \data_f2_out[75]\, - data_f2_out(74) => \data_f2_out[74]\, data_f2_out(73) => - \data_f2_out[73]\, data_f2_out(72) => \data_f2_out[72]\, - data_f2_out(71) => \data_f2_out[71]\, data_f2_out(70) => - \data_f2_out[70]\, data_f2_out(69) => \data_f2_out[69]\, - data_f2_out(68) => \data_f2_out[68]\, data_f2_out(67) => - \data_f2_out[67]\, data_f2_out(66) => \data_f2_out[66]\, - data_f2_out(65) => \data_f2_out[65]\, data_f2_out(64) => - \data_f2_out[64]\, nb_snapshot_param(0) => - nb_snapshot_param(0), HRESETn_c => HRESETn_c, HCLK_c => - HCLK_c, data_f2_out_valid => data_f2_out_valid, I_13_20 - => I_13_20, I_9_20 => I_9_20, I_5_20 => I_5_20, I_38_4 - => I_38_4, I_31_5 => I_31_5, N_4 => N_4, I_45_4 => - I_45_4, I_56_4 => I_56_4, I_52_4 => I_52_4, I_24_4 => - I_24_4, I_20_12 => I_20_12, enable_f2 => enable_f2, - burst_f2 => burst_f2, start_snapshot_f2 => - start_snapshot_f2, sample_f2_val => sample_f2_val); - - un7_nb_snapshot_param_more_one_I_12 : AND3 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), C => nb_snapshot_param(2), Y => - N_42); - - un7_nb_snapshot_param_more_one_I_5 : XOR2 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), Y => I_5_20); - - un7_nb_snapshot_param_more_one_I_51 : NOR2B - port map(A => nb_snapshot_param(8), B => \DWACT_FINC_E[4]\, - Y => N_14); - - pp_waveform_dma_1 : lpp_waveform_dma - port map(addr_data_f0(31) => addr_data_f0(31), - addr_data_f0(30) => addr_data_f0(30), addr_data_f0(29) - => addr_data_f0(29), addr_data_f0(28) => - addr_data_f0(28), addr_data_f0(27) => addr_data_f0(27), - addr_data_f0(26) => addr_data_f0(26), addr_data_f0(25) - => addr_data_f0(25), addr_data_f0(24) => - addr_data_f0(24), addr_data_f0(23) => addr_data_f0(23), - addr_data_f0(22) => addr_data_f0(22), addr_data_f0(21) - => addr_data_f0(21), addr_data_f0(20) => - addr_data_f0(20), addr_data_f0(19) => addr_data_f0(19), - addr_data_f0(18) => addr_data_f0(18), addr_data_f0(17) - => addr_data_f0(17), addr_data_f0(16) => - addr_data_f0(16), addr_data_f0(15) => addr_data_f0(15), - addr_data_f0(14) => addr_data_f0(14), addr_data_f0(13) - => addr_data_f0(13), addr_data_f0(12) => - addr_data_f0(12), addr_data_f0(11) => addr_data_f0(11), - addr_data_f0(10) => addr_data_f0(10), addr_data_f0(9) => - addr_data_f0(9), addr_data_f0(8) => addr_data_f0(8), - addr_data_f0(7) => addr_data_f0(7), addr_data_f0(6) => - addr_data_f0(6), addr_data_f0(5) => addr_data_f0(5), - addr_data_f0(4) => addr_data_f0(4), addr_data_f0(3) => - addr_data_f0(3), addr_data_f0(2) => addr_data_f0(2), - addr_data_f0(1) => addr_data_f0(1), addr_data_f0(0) => - addr_data_f0(0), addr_data_f1(31) => addr_data_f1(31), - addr_data_f1(30) => addr_data_f1(30), addr_data_f1(29) - => addr_data_f1(29), addr_data_f1(28) => - addr_data_f1(28), addr_data_f1(27) => addr_data_f1(27), - addr_data_f1(26) => addr_data_f1(26), addr_data_f1(25) - => addr_data_f1(25), addr_data_f1(24) => - addr_data_f1(24), addr_data_f1(23) => addr_data_f1(23), - addr_data_f1(22) => addr_data_f1(22), addr_data_f1(21) - => addr_data_f1(21), addr_data_f1(20) => - addr_data_f1(20), addr_data_f1(19) => addr_data_f1(19), - addr_data_f1(18) => addr_data_f1(18), addr_data_f1(17) - => addr_data_f1(17), addr_data_f1(16) => - addr_data_f1(16), addr_data_f1(15) => addr_data_f1(15), - addr_data_f1(14) => addr_data_f1(14), addr_data_f1(13) - => addr_data_f1(13), addr_data_f1(12) => - addr_data_f1(12), addr_data_f1(11) => addr_data_f1(11), - addr_data_f1(10) => addr_data_f1(10), addr_data_f1(9) => - addr_data_f1(9), addr_data_f1(8) => addr_data_f1(8), - addr_data_f1(7) => addr_data_f1(7), addr_data_f1(6) => - addr_data_f1(6), addr_data_f1(5) => addr_data_f1(5), - addr_data_f1(4) => addr_data_f1(4), addr_data_f1(3) => - addr_data_f1(3), addr_data_f1(2) => addr_data_f1(2), - addr_data_f1(1) => addr_data_f1(1), addr_data_f1(0) => - addr_data_f1(0), addr_data_f2(31) => addr_data_f2(31), - addr_data_f2(30) => addr_data_f2(30), addr_data_f2(29) - => addr_data_f2(29), addr_data_f2(28) => - addr_data_f2(28), addr_data_f2(27) => addr_data_f2(27), - addr_data_f2(26) => addr_data_f2(26), addr_data_f2(25) - => addr_data_f2(25), addr_data_f2(24) => - addr_data_f2(24), addr_data_f2(23) => addr_data_f2(23), - addr_data_f2(22) => addr_data_f2(22), addr_data_f2(21) - => addr_data_f2(21), addr_data_f2(20) => - addr_data_f2(20), addr_data_f2(19) => addr_data_f2(19), - addr_data_f2(18) => addr_data_f2(18), addr_data_f2(17) - => addr_data_f2(17), addr_data_f2(16) => - addr_data_f2(16), addr_data_f2(15) => addr_data_f2(15), - addr_data_f2(14) => addr_data_f2(14), addr_data_f2(13) - => addr_data_f2(13), addr_data_f2(12) => - addr_data_f2(12), addr_data_f2(11) => addr_data_f2(11), - addr_data_f2(10) => addr_data_f2(10), addr_data_f2(9) => - addr_data_f2(9), addr_data_f2(8) => addr_data_f2(8), - addr_data_f2(7) => addr_data_f2(7), addr_data_f2(6) => - addr_data_f2(6), addr_data_f2(5) => addr_data_f2(5), - addr_data_f2(4) => addr_data_f2(4), addr_data_f2(3) => - addr_data_f2(3), addr_data_f2(2) => addr_data_f2(2), - addr_data_f2(1) => addr_data_f2(1), addr_data_f2(0) => - addr_data_f2(0), addr_data_f3(31) => addr_data_f3(31), - addr_data_f3(30) => addr_data_f3(30), addr_data_f3(29) - => addr_data_f3(29), addr_data_f3(28) => - addr_data_f3(28), addr_data_f3(27) => addr_data_f3(27), - addr_data_f3(26) => addr_data_f3(26), addr_data_f3(25) - => addr_data_f3(25), addr_data_f3(24) => - addr_data_f3(24), addr_data_f3(23) => addr_data_f3(23), - addr_data_f3(22) => addr_data_f3(22), addr_data_f3(21) - => addr_data_f3(21), addr_data_f3(20) => - addr_data_f3(20), addr_data_f3(19) => addr_data_f3(19), - addr_data_f3(18) => addr_data_f3(18), addr_data_f3(17) - => addr_data_f3(17), addr_data_f3(16) => - addr_data_f3(16), addr_data_f3(15) => addr_data_f3(15), - addr_data_f3(14) => addr_data_f3(14), addr_data_f3(13) - => addr_data_f3(13), addr_data_f3(12) => - addr_data_f3(12), addr_data_f3(11) => addr_data_f3(11), - addr_data_f3(10) => addr_data_f3(10), addr_data_f3(9) => - addr_data_f3(9), addr_data_f3(8) => addr_data_f3(8), - addr_data_f3(7) => addr_data_f3(7), addr_data_f3(6) => - addr_data_f3(6), addr_data_f3(5) => addr_data_f3(5), - addr_data_f3(4) => addr_data_f3(4), addr_data_f3(3) => - addr_data_f3(3), addr_data_f3(2) => addr_data_f3(2), - addr_data_f3(1) => addr_data_f3(1), addr_data_f3(0) => - addr_data_f3(0), status_full(3) => status_full(3), - status_full(2) => status_full(2), status_full(1) => - status_full(1), status_full(0) => status_full(0), - status_full_err(3) => status_full_err(3), - status_full_err(2) => status_full_err(2), - status_full_err(1) => status_full_err(1), - status_full_err(0) => status_full_err(0), - nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - haddr_c(31) => haddr_c(31), haddr_c(30) => haddr_c(30), - haddr_c(29) => haddr_c(29), haddr_c(28) => haddr_c(28), - haddr_c(27) => haddr_c(27), haddr_c(26) => haddr_c(26), - haddr_c(25) => haddr_c(25), haddr_c(24) => haddr_c(24), - haddr_c(23) => haddr_c(23), haddr_c(22) => haddr_c(22), - haddr_c(21) => haddr_c(21), haddr_c(20) => haddr_c(20), - haddr_c(19) => haddr_c(19), haddr_c(18) => haddr_c(18), - haddr_c(17) => haddr_c(17), haddr_c(16) => haddr_c(16), - haddr_c(15) => haddr_c(15), haddr_c(14) => haddr_c(14), - haddr_c(13) => haddr_c(13), haddr_c(12) => haddr_c(12), - haddr_c(11) => haddr_c(11), haddr_c(10) => haddr_c(10), - haddr_c(9) => haddr_c(9), haddr_c(8) => haddr_c(8), - haddr_c(7) => haddr_c(7), haddr_c(6) => haddr_c(6), - haddr_c(5) => haddr_c(5), haddr_c(4) => haddr_c(4), - haddr_c(3) => haddr_c(3), haddr_c(2) => haddr_c(2), - haddr_c(1) => haddr_c(1), haddr_c(0) => haddr_c(0), - AHB_Master_In_c_3 => AHB_Master_In_c_3, AHB_Master_In_c_0 - => AHB_Master_In_c_0, AHB_Master_In_c_4 => - AHB_Master_In_c_4, AHB_Master_In_c_5 => AHB_Master_In_c_5, - hsize_c(1) => hsize_c(1), hsize_c(0) => hsize_c(0), - htrans_c(1) => htrans_c(1), htrans_c(0) => htrans_c(0), - hburst_c(2) => hburst_c(2), hburst_c(1) => hburst_c(1), - hburst_c(0) => hburst_c(0), status_full_ack(3) => - status_full_ack(3), status_full_ack(2) => - status_full_ack(2), status_full_ack(1) => - status_full_ack(1), status_full_ack(0) => - status_full_ack(0), ready_i_0(3) => \ready_i_0[3]\, - ready_i_0(2) => \ready_i_0[2]\, ready_i_0(1) => - \ready_i_0[1]\, ready_i_0(0) => \ready_i_0[0]\, - data_ren(3) => \data_ren[3]\, data_ren(2) => - \data_ren[2]\, data_ren(1) => \data_ren[1]\, data_ren(0) - => \data_ren[0]\, time_ren(3) => \time_ren[3]\, - time_ren(2) => \time_ren[2]\, time_ren(1) => - \time_ren[1]\, time_ren(0) => \time_ren[0]\, time_ren_1z - => time_ren, data_ren_1z => data_ren, N_43 => N_43, - IdlePhase_RNI03G71 => IdlePhase_RNI03G71, hwrite_c => - hwrite_c, un20_time_write => un20_time_write, - un13_time_write => un13_time_write, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter - port map(wdata(31) => \wdata[31]\, wdata(30) => \wdata[30]\, - wdata(29) => \wdata[29]\, wdata(28) => \wdata[28]\, - wdata(27) => \wdata[27]\, wdata(26) => \wdata[26]\, - wdata(25) => \wdata[25]\, wdata(24) => \wdata[24]\, - wdata(23) => \wdata[23]\, wdata(22) => \wdata[22]\, - wdata(21) => \wdata[21]\, wdata(20) => \wdata[20]\, - wdata(19) => \wdata[19]\, wdata(18) => \wdata[18]\, - wdata(17) => \wdata[17]\, wdata(16) => \wdata[16]\, - wdata(15) => \wdata[15]\, wdata(14) => \wdata[14]\, - wdata(13) => \wdata[13]\, wdata(12) => \wdata[12]\, - wdata(11) => \wdata[11]\, wdata(10) => \wdata[10]\, - wdata(9) => \wdata[9]\, wdata(8) => \wdata[8]\, wdata(7) - => \wdata[7]\, wdata(6) => \wdata[6]\, wdata(5) => - \wdata[5]\, wdata(4) => \wdata[4]\, wdata(3) => - \wdata[3]\, wdata(2) => \wdata[2]\, wdata(1) => - \wdata[1]\, wdata(0) => \wdata[0]\, data_wen(3) => - \data_wen[3]\, data_wen(2) => \data_wen[2]\, data_wen(1) - => \data_wen[1]\, data_wen(0) => \data_wen[0]\, - valid_ack(3) => \valid_ack[3]\, valid_ack(2) => - \valid_ack[2]\, valid_ack(1) => \valid_ack[1]\, - valid_ack(0) => \valid_ack[0]\, time_wen(3) => - \time_wen[3]\, time_wen(2) => \time_wen[2]\, time_wen(1) - => \time_wen[1]\, time_wen(0) => \time_wen[0]\, - data_f3_out(159) => \data_f3_out[159]\, data_f3_out(158) - => \data_f3_out[158]\, data_f3_out(157) => - \data_f3_out[157]\, data_f3_out(156) => - \data_f3_out[156]\, data_f3_out(155) => - \data_f3_out[155]\, data_f3_out(154) => - \data_f3_out[154]\, data_f3_out(153) => - \data_f3_out[153]\, data_f3_out(152) => - \data_f3_out[152]\, data_f3_out(151) => - \data_f3_out[151]\, data_f3_out(150) => - \data_f3_out[150]\, data_f3_out(149) => - \data_f3_out[149]\, data_f3_out(148) => - \data_f3_out[148]\, data_f3_out(147) => - \data_f3_out[147]\, data_f3_out(146) => - \data_f3_out[146]\, data_f3_out(145) => - \data_f3_out[145]\, data_f3_out(144) => - \data_f3_out[144]\, data_f3_out(143) => - \data_f3_out[143]\, data_f3_out(142) => - \data_f3_out[142]\, data_f3_out(141) => - \data_f3_out[141]\, data_f3_out(140) => - \data_f3_out[140]\, data_f3_out(139) => - \data_f3_out[139]\, data_f3_out(138) => - \data_f3_out[138]\, data_f3_out(137) => - \data_f3_out[137]\, data_f3_out(136) => - \data_f3_out[136]\, data_f3_out(135) => - \data_f3_out[135]\, data_f3_out(134) => - \data_f3_out[134]\, data_f3_out(133) => - \data_f3_out[133]\, data_f3_out(132) => - \data_f3_out[132]\, data_f3_out(131) => - \data_f3_out[131]\, data_f3_out(130) => - \data_f3_out[130]\, data_f3_out(129) => - \data_f3_out[129]\, data_f3_out(128) => - \data_f3_out[128]\, data_f3_out(127) => - \data_f3_out[127]\, data_f3_out(126) => - \data_f3_out[126]\, data_f3_out(125) => - \data_f3_out[125]\, data_f3_out(124) => - \data_f3_out[124]\, data_f3_out(123) => - \data_f3_out[123]\, data_f3_out(122) => - \data_f3_out[122]\, data_f3_out(121) => - \data_f3_out[121]\, data_f3_out(120) => - \data_f3_out[120]\, data_f3_out(119) => - \data_f3_out[119]\, data_f3_out(118) => - \data_f3_out[118]\, data_f3_out(117) => - \data_f3_out[117]\, data_f3_out(116) => - \data_f3_out[116]\, data_f3_out(115) => - \data_f3_out[115]\, data_f3_out(114) => - \data_f3_out[114]\, data_f3_out(113) => - \data_f3_out[113]\, data_f3_out(112) => - \data_f3_out[112]\, data_f3_out(111) => - \data_f3_out[111]\, data_f3_out(110) => - \data_f3_out[110]\, data_f3_out(109) => - \data_f3_out[109]\, data_f3_out(108) => - \data_f3_out[108]\, data_f3_out(107) => - \data_f3_out[107]\, data_f3_out(106) => - \data_f3_out[106]\, data_f3_out(105) => - \data_f3_out[105]\, data_f3_out(104) => - \data_f3_out[104]\, data_f3_out(103) => - \data_f3_out[103]\, data_f3_out(102) => - \data_f3_out[102]\, data_f3_out(101) => - \data_f3_out[101]\, data_f3_out(100) => - \data_f3_out[100]\, data_f3_out(99) => \data_f3_out[99]\, - data_f3_out(98) => \data_f3_out[98]\, data_f3_out(97) => - \data_f3_out[97]\, data_f3_out(96) => \data_f3_out[96]\, - data_f3_out(95) => \data_f3_out[95]\, data_f3_out(94) => - \data_f3_out[94]\, data_f3_out(93) => \data_f3_out[93]\, - data_f3_out(92) => \data_f3_out[92]\, data_f3_out(91) => - \data_f3_out[91]\, data_f3_out(90) => \data_f3_out[90]\, - data_f3_out(89) => \data_f3_out[89]\, data_f3_out(88) => - \data_f3_out[88]\, data_f3_out(87) => \data_f3_out[87]\, - data_f3_out(86) => \data_f3_out[86]\, data_f3_out(85) => - \data_f3_out[85]\, data_f3_out(84) => \data_f3_out[84]\, - data_f3_out(83) => \data_f3_out[83]\, data_f3_out(82) => - \data_f3_out[82]\, data_f3_out(81) => \data_f3_out[81]\, - data_f3_out(80) => \data_f3_out[80]\, data_f3_out(79) => - \data_f3_out[79]\, data_f3_out(78) => \data_f3_out[78]\, - data_f3_out(77) => \data_f3_out[77]\, data_f3_out(76) => - \data_f3_out[76]\, data_f3_out(75) => \data_f3_out[75]\, - data_f3_out(74) => \data_f3_out[74]\, data_f3_out(73) => - \data_f3_out[73]\, data_f3_out(72) => \data_f3_out[72]\, - data_f3_out(71) => \data_f3_out[71]\, data_f3_out(70) => - \data_f3_out[70]\, data_f3_out(69) => \data_f3_out[69]\, - data_f3_out(68) => \data_f3_out[68]\, data_f3_out(67) => - \data_f3_out[67]\, data_f3_out(66) => \data_f3_out[66]\, - data_f3_out(65) => \data_f3_out[65]\, data_f3_out(64) => - \data_f3_out[64]\, data_f2_out(159) => \data_f2_out[159]\, - data_f2_out(158) => \data_f2_out[158]\, data_f2_out(157) - => \data_f2_out[157]\, data_f2_out(156) => - \data_f2_out[156]\, data_f2_out(155) => - \data_f2_out[155]\, data_f2_out(154) => - \data_f2_out[154]\, data_f2_out(153) => - \data_f2_out[153]\, data_f2_out(152) => - \data_f2_out[152]\, data_f2_out(151) => - \data_f2_out[151]\, data_f2_out(150) => - \data_f2_out[150]\, data_f2_out(149) => - \data_f2_out[149]\, data_f2_out(148) => - \data_f2_out[148]\, data_f2_out(147) => - \data_f2_out[147]\, data_f2_out(146) => - \data_f2_out[146]\, data_f2_out(145) => - \data_f2_out[145]\, data_f2_out(144) => - \data_f2_out[144]\, data_f2_out(143) => - \data_f2_out[143]\, data_f2_out(142) => - \data_f2_out[142]\, data_f2_out(141) => - \data_f2_out[141]\, data_f2_out(140) => - \data_f2_out[140]\, data_f2_out(139) => - \data_f2_out[139]\, data_f2_out(138) => - \data_f2_out[138]\, data_f2_out(137) => - \data_f2_out[137]\, data_f2_out(136) => - \data_f2_out[136]\, data_f2_out(135) => - \data_f2_out[135]\, data_f2_out(134) => - \data_f2_out[134]\, data_f2_out(133) => - \data_f2_out[133]\, data_f2_out(132) => - \data_f2_out[132]\, data_f2_out(131) => - \data_f2_out[131]\, data_f2_out(130) => - \data_f2_out[130]\, data_f2_out(129) => - \data_f2_out[129]\, data_f2_out(128) => - \data_f2_out[128]\, data_f2_out(127) => - \data_f2_out[127]\, data_f2_out(126) => - \data_f2_out[126]\, data_f2_out(125) => - \data_f2_out[125]\, data_f2_out(124) => - \data_f2_out[124]\, data_f2_out(123) => - \data_f2_out[123]\, data_f2_out(122) => - \data_f2_out[122]\, data_f2_out(121) => - \data_f2_out[121]\, data_f2_out(120) => - \data_f2_out[120]\, data_f2_out(119) => - \data_f2_out[119]\, data_f2_out(118) => - \data_f2_out[118]\, data_f2_out(117) => - \data_f2_out[117]\, data_f2_out(116) => - \data_f2_out[116]\, data_f2_out(115) => - \data_f2_out[115]\, data_f2_out(114) => - \data_f2_out[114]\, data_f2_out(113) => - \data_f2_out[113]\, data_f2_out(112) => - \data_f2_out[112]\, data_f2_out(111) => - \data_f2_out[111]\, data_f2_out(110) => - \data_f2_out[110]\, data_f2_out(109) => - \data_f2_out[109]\, data_f2_out(108) => - \data_f2_out[108]\, data_f2_out(107) => - \data_f2_out[107]\, data_f2_out(106) => - \data_f2_out[106]\, data_f2_out(105) => - \data_f2_out[105]\, data_f2_out(104) => - \data_f2_out[104]\, data_f2_out(103) => - \data_f2_out[103]\, data_f2_out(102) => - \data_f2_out[102]\, data_f2_out(101) => - \data_f2_out[101]\, data_f2_out(100) => - \data_f2_out[100]\, data_f2_out(99) => \data_f2_out[99]\, - data_f2_out(98) => \data_f2_out[98]\, data_f2_out(97) => - \data_f2_out[97]\, data_f2_out(96) => \data_f2_out[96]\, - data_f2_out(95) => \data_f2_out[95]\, data_f2_out(94) => - \data_f2_out[94]\, data_f2_out(93) => \data_f2_out[93]\, - data_f2_out(92) => \data_f2_out[92]\, data_f2_out(91) => - \data_f2_out[91]\, data_f2_out(90) => \data_f2_out[90]\, - data_f2_out(89) => \data_f2_out[89]\, data_f2_out(88) => - \data_f2_out[88]\, data_f2_out(87) => \data_f2_out[87]\, - data_f2_out(86) => \data_f2_out[86]\, data_f2_out(85) => - \data_f2_out[85]\, data_f2_out(84) => \data_f2_out[84]\, - data_f2_out(83) => \data_f2_out[83]\, data_f2_out(82) => - \data_f2_out[82]\, data_f2_out(81) => \data_f2_out[81]\, - data_f2_out(80) => \data_f2_out[80]\, data_f2_out(79) => - \data_f2_out[79]\, data_f2_out(78) => \data_f2_out[78]\, - data_f2_out(77) => \data_f2_out[77]\, data_f2_out(76) => - \data_f2_out[76]\, data_f2_out(75) => \data_f2_out[75]\, - data_f2_out(74) => \data_f2_out[74]\, data_f2_out(73) => - \data_f2_out[73]\, data_f2_out(72) => \data_f2_out[72]\, - data_f2_out(71) => \data_f2_out[71]\, data_f2_out(70) => - \data_f2_out[70]\, data_f2_out(69) => \data_f2_out[69]\, - data_f2_out(68) => \data_f2_out[68]\, data_f2_out(67) => - \data_f2_out[67]\, data_f2_out(66) => \data_f2_out[66]\, - data_f2_out(65) => \data_f2_out[65]\, data_f2_out(64) => - \data_f2_out[64]\, data_f1_out(159) => \data_f1_out[159]\, - data_f1_out(158) => \data_f1_out[158]\, data_f1_out(157) - => \data_f1_out[157]\, data_f1_out(156) => - \data_f1_out[156]\, data_f1_out(155) => - \data_f1_out[155]\, data_f1_out(154) => - \data_f1_out[154]\, data_f1_out(153) => - \data_f1_out[153]\, data_f1_out(152) => - \data_f1_out[152]\, data_f1_out(151) => - \data_f1_out[151]\, data_f1_out(150) => - \data_f1_out[150]\, data_f1_out(149) => - \data_f1_out[149]\, data_f1_out(148) => - \data_f1_out[148]\, data_f1_out(147) => - \data_f1_out[147]\, data_f1_out(146) => - \data_f1_out[146]\, data_f1_out(145) => - \data_f1_out[145]\, data_f1_out(144) => - \data_f1_out[144]\, data_f1_out(143) => - \data_f1_out[143]\, data_f1_out(142) => - \data_f1_out[142]\, data_f1_out(141) => - \data_f1_out[141]\, data_f1_out(140) => - \data_f1_out[140]\, data_f1_out(139) => - \data_f1_out[139]\, data_f1_out(138) => - \data_f1_out[138]\, data_f1_out(137) => - \data_f1_out[137]\, data_f1_out(136) => - \data_f1_out[136]\, data_f1_out(135) => - \data_f1_out[135]\, data_f1_out(134) => - \data_f1_out[134]\, data_f1_out(133) => - \data_f1_out[133]\, data_f1_out(132) => - \data_f1_out[132]\, data_f1_out(131) => - \data_f1_out[131]\, data_f1_out(130) => - \data_f1_out[130]\, data_f1_out(129) => - \data_f1_out[129]\, data_f1_out(128) => - \data_f1_out[128]\, data_f1_out(127) => - \data_f1_out[127]\, data_f1_out(126) => - \data_f1_out[126]\, data_f1_out(125) => - \data_f1_out[125]\, data_f1_out(124) => - \data_f1_out[124]\, data_f1_out(123) => - \data_f1_out[123]\, data_f1_out(122) => - \data_f1_out[122]\, data_f1_out(121) => - \data_f1_out[121]\, data_f1_out(120) => - \data_f1_out[120]\, data_f1_out(119) => - \data_f1_out[119]\, data_f1_out(118) => - \data_f1_out[118]\, data_f1_out(117) => - \data_f1_out[117]\, data_f1_out(116) => - \data_f1_out[116]\, data_f1_out(115) => - \data_f1_out[115]\, data_f1_out(114) => - \data_f1_out[114]\, data_f1_out(113) => - \data_f1_out[113]\, data_f1_out(112) => - \data_f1_out[112]\, data_f1_out(111) => - \data_f1_out[111]\, data_f1_out(110) => - \data_f1_out[110]\, data_f1_out(109) => - \data_f1_out[109]\, data_f1_out(108) => - \data_f1_out[108]\, data_f1_out(107) => - \data_f1_out[107]\, data_f1_out(106) => - \data_f1_out[106]\, data_f1_out(105) => - \data_f1_out[105]\, data_f1_out(104) => - \data_f1_out[104]\, data_f1_out(103) => - \data_f1_out[103]\, data_f1_out(102) => - \data_f1_out[102]\, data_f1_out(101) => - \data_f1_out[101]\, data_f1_out(100) => - \data_f1_out[100]\, data_f1_out(99) => \data_f1_out[99]\, - data_f1_out(98) => \data_f1_out[98]\, data_f1_out(97) => - \data_f1_out[97]\, data_f1_out(96) => \data_f1_out[96]\, - data_f1_out(95) => \data_f1_out[95]\, data_f1_out(94) => - \data_f1_out[94]\, data_f1_out(93) => \data_f1_out[93]\, - data_f1_out(92) => \data_f1_out[92]\, data_f1_out(91) => - \data_f1_out[91]\, data_f1_out(90) => \data_f1_out[90]\, - data_f1_out(89) => \data_f1_out[89]\, data_f1_out(88) => - \data_f1_out[88]\, data_f1_out(87) => \data_f1_out[87]\, - data_f1_out(86) => \data_f1_out[86]\, data_f1_out(85) => - \data_f1_out[85]\, data_f1_out(84) => \data_f1_out[84]\, - data_f1_out(83) => \data_f1_out[83]\, data_f1_out(82) => - \data_f1_out[82]\, data_f1_out(81) => \data_f1_out[81]\, - data_f1_out(80) => \data_f1_out[80]\, data_f1_out(79) => - \data_f1_out[79]\, data_f1_out(78) => \data_f1_out[78]\, - data_f1_out(77) => \data_f1_out[77]\, data_f1_out(76) => - \data_f1_out[76]\, data_f1_out(75) => \data_f1_out[75]\, - data_f1_out(74) => \data_f1_out[74]\, data_f1_out(73) => - \data_f1_out[73]\, data_f1_out(72) => \data_f1_out[72]\, - data_f1_out(71) => \data_f1_out[71]\, data_f1_out(70) => - \data_f1_out[70]\, data_f1_out(69) => \data_f1_out[69]\, - data_f1_out(68) => \data_f1_out[68]\, data_f1_out(67) => - \data_f1_out[67]\, data_f1_out(66) => \data_f1_out[66]\, - data_f1_out(65) => \data_f1_out[65]\, data_f1_out(64) => - \data_f1_out[64]\, data_f0_out(159) => \data_f0_out[159]\, - data_f0_out(158) => \data_f0_out[158]\, data_f0_out(157) - => \data_f0_out[157]\, data_f0_out(156) => - \data_f0_out[156]\, data_f0_out(155) => - \data_f0_out[155]\, data_f0_out(154) => - \data_f0_out[154]\, data_f0_out(153) => - \data_f0_out[153]\, data_f0_out(152) => - \data_f0_out[152]\, data_f0_out(151) => - \data_f0_out[151]\, data_f0_out(150) => - \data_f0_out[150]\, data_f0_out(149) => - \data_f0_out[149]\, data_f0_out(148) => - \data_f0_out[148]\, data_f0_out(147) => - \data_f0_out[147]\, data_f0_out(146) => - \data_f0_out[146]\, data_f0_out(145) => - \data_f0_out[145]\, data_f0_out(144) => - \data_f0_out[144]\, data_f0_out(143) => - \data_f0_out[143]\, data_f0_out(142) => - \data_f0_out[142]\, data_f0_out(141) => - \data_f0_out[141]\, data_f0_out(140) => - \data_f0_out[140]\, data_f0_out(139) => - \data_f0_out[139]\, data_f0_out(138) => - \data_f0_out[138]\, data_f0_out(137) => - \data_f0_out[137]\, data_f0_out(136) => - \data_f0_out[136]\, data_f0_out(135) => - \data_f0_out[135]\, data_f0_out(134) => - \data_f0_out[134]\, data_f0_out(133) => - \data_f0_out[133]\, data_f0_out(132) => - \data_f0_out[132]\, data_f0_out(131) => - \data_f0_out[131]\, data_f0_out(130) => - \data_f0_out[130]\, data_f0_out(129) => - \data_f0_out[129]\, data_f0_out(128) => - \data_f0_out[128]\, data_f0_out(127) => - \data_f0_out[127]\, data_f0_out(126) => - \data_f0_out[126]\, data_f0_out(125) => - \data_f0_out[125]\, data_f0_out(124) => - \data_f0_out[124]\, data_f0_out(123) => - \data_f0_out[123]\, data_f0_out(122) => - \data_f0_out[122]\, data_f0_out(121) => - \data_f0_out[121]\, data_f0_out(120) => - \data_f0_out[120]\, data_f0_out(119) => - \data_f0_out[119]\, data_f0_out(118) => - \data_f0_out[118]\, data_f0_out(117) => - \data_f0_out[117]\, data_f0_out(116) => - \data_f0_out[116]\, data_f0_out(115) => - \data_f0_out[115]\, data_f0_out(114) => - \data_f0_out[114]\, data_f0_out(113) => - \data_f0_out[113]\, data_f0_out(112) => - \data_f0_out[112]\, data_f0_out(111) => - \data_f0_out[111]\, data_f0_out(110) => - \data_f0_out[110]\, data_f0_out(109) => - \data_f0_out[109]\, data_f0_out(108) => - \data_f0_out[108]\, data_f0_out(107) => - \data_f0_out[107]\, data_f0_out(106) => - \data_f0_out[106]\, data_f0_out(105) => - \data_f0_out[105]\, data_f0_out(104) => - \data_f0_out[104]\, data_f0_out(103) => - \data_f0_out[103]\, data_f0_out(102) => - \data_f0_out[102]\, data_f0_out(101) => - \data_f0_out[101]\, data_f0_out(100) => - \data_f0_out[100]\, data_f0_out(99) => \data_f0_out[99]\, - data_f0_out(98) => \data_f0_out[98]\, data_f0_out(97) => - \data_f0_out[97]\, data_f0_out(96) => \data_f0_out[96]\, - data_f0_out(95) => \data_f0_out[95]\, data_f0_out(94) => - \data_f0_out[94]\, data_f0_out(93) => \data_f0_out[93]\, - data_f0_out(92) => \data_f0_out[92]\, data_f0_out(91) => - \data_f0_out[91]\, data_f0_out(90) => \data_f0_out[90]\, - data_f0_out(89) => \data_f0_out[89]\, data_f0_out(88) => - \data_f0_out[88]\, data_f0_out(87) => \data_f0_out[87]\, - data_f0_out(86) => \data_f0_out[86]\, data_f0_out(85) => - \data_f0_out[85]\, data_f0_out(84) => \data_f0_out[84]\, - data_f0_out(83) => \data_f0_out[83]\, data_f0_out(82) => - \data_f0_out[82]\, data_f0_out(81) => \data_f0_out[81]\, - data_f0_out(80) => \data_f0_out[80]\, data_f0_out(79) => - \data_f0_out[79]\, data_f0_out(78) => \data_f0_out[78]\, - data_f0_out(77) => \data_f0_out[77]\, data_f0_out(76) => - \data_f0_out[76]\, data_f0_out(75) => \data_f0_out[75]\, - data_f0_out(74) => \data_f0_out[74]\, data_f0_out(73) => - \data_f0_out[73]\, data_f0_out(72) => \data_f0_out[72]\, - data_f0_out(71) => \data_f0_out[71]\, data_f0_out(70) => - \data_f0_out[70]\, data_f0_out(69) => \data_f0_out[69]\, - data_f0_out(68) => \data_f0_out[68]\, data_f0_out(67) => - \data_f0_out[67]\, data_f0_out(66) => \data_f0_out[66]\, - data_f0_out(65) => \data_f0_out[65]\, data_f0_out(64) => - \data_f0_out[64]\, valid_out_i(1) => \valid_out_i[1]\, - ready_i_0(3) => \ready_i_0[3]\, ready_i_0(2) => - \ready_i_0[2]\, ready_i_0(1) => \ready_i_0[1]\, - ready_i_0(0) => \ready_i_0[0]\, valid_out_3 => - \valid_out[3]\, valid_out_2 => \valid_out[2]\, - valid_out_0 => \valid_out[0]\, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_8_16_4 is - - port( sample_f0_0 : out std_logic; - sample_f0_1 : out std_logic; - sample_f0_2 : out std_logic; - sample_f0_3 : out std_logic; - sample_f0_4 : out std_logic; - sample_f0_5 : out std_logic; - sample_f0_6 : out std_logic; - sample_f0_7 : out std_logic; - sample_f0_8 : out std_logic; - sample_f0_9 : out std_logic; - sample_f0_10 : out std_logic; - sample_f0_11 : out std_logic; - sample_f0_12 : out std_logic; - sample_f0_13 : out std_logic; - sample_f0_14 : out std_logic; - sample_f0_15 : out std_logic; - sample_f0_32 : out std_logic; - sample_f0_33 : out std_logic; - sample_f0_34 : out std_logic; - sample_f0_35 : out std_logic; - sample_f0_36 : out std_logic; - sample_f0_37 : out std_logic; - sample_f0_38 : out std_logic; - sample_f0_39 : out std_logic; - sample_f0_40 : out std_logic; - sample_f0_41 : out std_logic; - sample_f0_42 : out std_logic; - sample_f0_43 : out std_logic; - sample_f0_44 : out std_logic; - sample_f0_45 : out std_logic; - sample_f0_46 : out std_logic; - sample_f0_47 : out std_logic; - sample_f0_48 : out std_logic; - sample_f0_49 : out std_logic; - sample_f0_50 : out std_logic; - sample_f0_51 : out std_logic; - sample_f0_52 : out std_logic; - sample_f0_53 : out std_logic; - sample_f0_54 : out std_logic; - sample_f0_55 : out std_logic; - sample_f0_56 : out std_logic; - sample_f0_57 : out std_logic; - sample_f0_58 : out std_logic; - sample_f0_59 : out std_logic; - sample_f0_60 : out std_logic; - sample_f0_61 : out std_logic; - sample_f0_62 : out std_logic; - sample_f0_63 : out std_logic; - sample_data_shaping_out_0 : in std_logic; - sample_data_shaping_out_1 : in std_logic; - sample_data_shaping_out_2 : in std_logic; - sample_data_shaping_out_3 : in std_logic; - sample_data_shaping_out_4 : in std_logic; - sample_data_shaping_out_5 : in std_logic; - sample_data_shaping_out_6 : in std_logic; - sample_data_shaping_out_7 : in std_logic; - sample_data_shaping_out_8 : in std_logic; - sample_data_shaping_out_9 : in std_logic; - sample_data_shaping_out_10 : in std_logic; - sample_data_shaping_out_11 : in std_logic; - sample_data_shaping_out_12 : in std_logic; - sample_data_shaping_out_13 : in std_logic; - sample_data_shaping_out_14 : in std_logic; - sample_data_shaping_out_15 : in std_logic; - sample_data_shaping_out_18 : in std_logic; - sample_data_shaping_out_19 : in std_logic; - sample_data_shaping_out_20 : in std_logic; - sample_data_shaping_out_21 : in std_logic; - sample_data_shaping_out_22 : in std_logic; - sample_data_shaping_out_23 : in std_logic; - sample_data_shaping_out_24 : in std_logic; - sample_data_shaping_out_25 : in std_logic; - sample_data_shaping_out_26 : in std_logic; - sample_data_shaping_out_27 : in std_logic; - sample_data_shaping_out_28 : in std_logic; - sample_data_shaping_out_29 : in std_logic; - sample_data_shaping_out_30 : in std_logic; - sample_data_shaping_out_31 : in std_logic; - sample_data_shaping_out_32 : in std_logic; - sample_data_shaping_out_33 : in std_logic; - sample_data_shaping_out_36 : in std_logic; - sample_data_shaping_out_37 : in std_logic; - sample_data_shaping_out_38 : in std_logic; - sample_data_shaping_out_39 : in std_logic; - sample_data_shaping_out_40 : in std_logic; - sample_data_shaping_out_41 : in std_logic; - sample_data_shaping_out_42 : in std_logic; - sample_data_shaping_out_43 : in std_logic; - sample_data_shaping_out_44 : in std_logic; - sample_data_shaping_out_45 : in std_logic; - sample_data_shaping_out_46 : in std_logic; - sample_data_shaping_out_47 : in std_logic; - sample_data_shaping_out_48 : in std_logic; - sample_data_shaping_out_49 : in std_logic; - sample_data_shaping_out_50 : in std_logic; - sample_data_shaping_out_51 : in std_logic; - sample_data_shaping_out_54 : in std_logic; - sample_data_shaping_out_55 : in std_logic; - sample_data_shaping_out_56 : in std_logic; - sample_data_shaping_out_57 : in std_logic; - sample_data_shaping_out_58 : in std_logic; - sample_data_shaping_out_59 : in std_logic; - sample_data_shaping_out_60 : in std_logic; - sample_data_shaping_out_61 : in std_logic; - sample_data_shaping_out_62 : in std_logic; - sample_data_shaping_out_63 : in std_logic; - sample_data_shaping_out_64 : in std_logic; - sample_data_shaping_out_65 : in std_logic; - sample_data_shaping_out_66 : in std_logic; - sample_data_shaping_out_67 : in std_logic; - sample_data_shaping_out_68 : in std_logic; - sample_data_shaping_out_69 : in std_logic; - sample_data_shaping_out_90 : in std_logic; - sample_data_shaping_out_91 : in std_logic; - sample_data_shaping_out_92 : in std_logic; - sample_data_shaping_out_93 : in std_logic; - sample_data_shaping_out_94 : in std_logic; - sample_data_shaping_out_95 : in std_logic; - sample_data_shaping_out_96 : in std_logic; - sample_data_shaping_out_97 : in std_logic; - sample_data_shaping_out_98 : in std_logic; - sample_data_shaping_out_99 : in std_logic; - sample_data_shaping_out_100 : in std_logic; - sample_data_shaping_out_101 : in std_logic; - sample_data_shaping_out_102 : in std_logic; - sample_data_shaping_out_103 : in std_logic; - sample_data_shaping_out_104 : in std_logic; - sample_data_shaping_out_105 : in std_logic; - sample_data_shaping_out_108 : in std_logic; - sample_data_shaping_out_109 : in std_logic; - sample_data_shaping_out_110 : in std_logic; - sample_data_shaping_out_111 : in std_logic; - sample_data_shaping_out_112 : in std_logic; - sample_data_shaping_out_113 : in std_logic; - sample_data_shaping_out_114 : in std_logic; - sample_data_shaping_out_115 : in std_logic; - sample_data_shaping_out_116 : in std_logic; - sample_data_shaping_out_117 : in std_logic; - sample_data_shaping_out_118 : in std_logic; - sample_data_shaping_out_119 : in std_logic; - sample_data_shaping_out_120 : in std_logic; - sample_data_shaping_out_121 : in std_logic; - sample_data_shaping_out_122 : in std_logic; - sample_data_shaping_out_123 : in std_logic; - sample_data_shaping_out_126 : in std_logic; - sample_data_shaping_out_127 : in std_logic; - sample_data_shaping_out_128 : in std_logic; - sample_data_shaping_out_129 : in std_logic; - sample_data_shaping_out_130 : in std_logic; - sample_data_shaping_out_131 : in std_logic; - sample_data_shaping_out_132 : in std_logic; - sample_data_shaping_out_133 : in std_logic; - sample_data_shaping_out_134 : in std_logic; - sample_data_shaping_out_135 : in std_logic; - sample_data_shaping_out_136 : in std_logic; - sample_data_shaping_out_137 : in std_logic; - sample_data_shaping_out_138 : in std_logic; - sample_data_shaping_out_139 : in std_logic; - sample_data_shaping_out_140 : in std_logic; - sample_data_shaping_out_141 : in std_logic; - sample_f0_wdata_95 : out std_logic; - sample_f0_wdata_94 : out std_logic; - sample_f0_wdata_93 : out std_logic; - sample_f0_wdata_92 : out std_logic; - sample_f0_wdata_91 : out std_logic; - sample_f0_wdata_90 : out std_logic; - sample_f0_wdata_89 : out std_logic; - sample_f0_wdata_88 : out std_logic; - sample_f0_wdata_87 : out std_logic; - sample_f0_wdata_86 : out std_logic; - sample_f0_wdata_85 : out std_logic; - sample_f0_wdata_84 : out std_logic; - sample_f0_wdata_83 : out std_logic; - sample_f0_wdata_82 : out std_logic; - sample_f0_wdata_81 : out std_logic; - sample_f0_wdata_80 : out std_logic; - sample_f0_wdata_79 : out std_logic; - sample_f0_wdata_78 : out std_logic; - sample_f0_wdata_77 : out std_logic; - sample_f0_wdata_76 : out std_logic; - sample_f0_wdata_75 : out std_logic; - sample_f0_wdata_74 : out std_logic; - sample_f0_wdata_73 : out std_logic; - sample_f0_wdata_72 : out std_logic; - sample_f0_wdata_71 : out std_logic; - sample_f0_wdata_70 : out std_logic; - sample_f0_wdata_69 : out std_logic; - sample_f0_wdata_68 : out std_logic; - sample_f0_wdata_67 : out std_logic; - sample_f0_wdata_66 : out std_logic; - sample_f0_wdata_65 : out std_logic; - sample_f0_wdata_64 : out std_logic; - sample_f0_wdata_63 : out std_logic; - sample_f0_wdata_62 : out std_logic; - sample_f0_wdata_61 : out std_logic; - sample_f0_wdata_60 : out std_logic; - sample_f0_wdata_59 : out std_logic; - sample_f0_wdata_58 : out std_logic; - sample_f0_wdata_57 : out std_logic; - sample_f0_wdata_56 : out std_logic; - sample_f0_wdata_55 : out std_logic; - sample_f0_wdata_54 : out std_logic; - sample_f0_wdata_53 : out std_logic; - sample_f0_wdata_52 : out std_logic; - sample_f0_wdata_51 : out std_logic; - sample_f0_wdata_50 : out std_logic; - sample_f0_wdata_49 : out std_logic; - sample_f0_wdata_48 : out std_logic; - sample_f0_wdata_15 : out std_logic; - sample_f0_wdata_14 : out std_logic; - sample_f0_wdata_13 : out std_logic; - sample_f0_wdata_12 : out std_logic; - sample_f0_wdata_11 : out std_logic; - sample_f0_wdata_10 : out std_logic; - sample_f0_wdata_9 : out std_logic; - sample_f0_wdata_8 : out std_logic; - sample_f0_wdata_7 : out std_logic; - sample_f0_wdata_6 : out std_logic; - sample_f0_wdata_5 : out std_logic; - sample_f0_wdata_4 : out std_logic; - sample_f0_wdata_3 : out std_logic; - sample_f0_wdata_2 : out std_logic; - sample_f0_wdata_1 : out std_logic; - sample_f0_wdata_0 : out std_logic; - sample_data_shaping_out_val : in std_logic; - sample_f0_val : out std_logic; - sample_data_shaping_out_val_0 : in std_logic; - sample_f0_val_0 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_f0_val_1 : out std_logic - ); - -end Downsampling_8_16_4; - -architecture DEF_ARCH of Downsampling_8_16_4 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - signal sample_out_val_19, sample_out_0_sqmuxa_3, - un14_sample_in_val_0, sample_out_0_sqmuxa_2, - sample_out_0_sqmuxa_1, sample_out_0_sqmuxa_0, - un14_sample_in_val_23, un14_sample_in_val_22, - un14_sample_in_val_24, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un14_sample_in_val_15, - un14_sample_in_val_14, un14_sample_in_val_20, - un14_sample_in_val_9, un14_sample_in_val_8, - un14_sample_in_val_19, un14_sample_in_val_5, - un14_sample_in_val_4, un14_sample_in_val_17, - un14_sample_in_val_13, \counter[24]_net_1\, - un14_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un14_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un14_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un14_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un14_sample_in_val, - sample_out_0_sqmuxa, \counter_4[2]\, I_9, \counter_4[3]\, - I_13, \counter_4[4]\, I_20, \counter_4[5]\, I_24, - \counter_4[6]\, I_31_0, \counter_4[7]\, I_38, - \counter_4[8]\, I_45, \counter_4[9]\, I_52, - \counter_4[10]\, I_56, \counter_4[11]\, I_66, - \counter_4[12]\, I_73, \counter_4[13]\, I_77, - \counter_4[14]\, I_84, \counter_4[15]\, I_91, - \counter_4[16]\, I_98, \counter_4[17]\, I_105, - \counter_4[18]\, I_115, \counter_4[19]\, I_122, - \counter_4[20]\, I_129, \counter_4[21]\, I_136, - \counter_4[22]\, I_143, \counter_4[23]\, I_156, - \counter_4[24]\, I_166, \counter_4[25]\, I_173, - \counter_4[26]\, I_186, \counter_4[27]\, I_196, I_4, I_5, - N_4, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[19]_net_1\); - - \sample_out[125]\ : DFN1E1 - port map(D => sample_data_shaping_out_139, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_2); - - \sample_out[102]\ : DFN1E1 - port map(D => sample_data_shaping_out_114, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_54); - - \sample_out[122]\ : DFN1E1 - port map(D => sample_data_shaping_out_136, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_5); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_data_shaping_out_24, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_73); - - \sample_out[101]\ : DFN1E1 - port map(D => sample_data_shaping_out_113, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_53); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_data_shaping_out_22, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_75); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_data_shaping_out_13, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_82); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_data_shaping_out_1, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_94); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_data_shaping_out_21, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_76); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_data_shaping_out_67, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_13); - - \sample_out[121]\ : DFN1E1 - port map(D => sample_data_shaping_out_135, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_6); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_data_shaping_out_42, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_57); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_data_shaping_out_105, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_47); - - \counter_RNO[11]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_66, Y => - \counter_4[11]\); - - \counter_RNIHDLE1[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa_1); - - \sample_out[104]\ : DFN1E1 - port map(D => sample_data_shaping_out_116, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_56); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_data_shaping_out_38, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_61); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4); - - \sample_out[124]\ : DFN1E1 - port map(D => sample_data_shaping_out_138, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_3); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \counter_RNI0L371[10]\ : OR3C - port map(A => un14_sample_in_val_23, B => - un14_sample_in_val_22, C => un14_sample_in_val_24, Y => - un14_sample_in_val_0); - - \sample_out[97]\ : DFN1E1 - port map(D => sample_data_shaping_out_109, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_49); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186); - - \sample_out[108]\ : DFN1E1 - port map(D => sample_data_shaping_out_120, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_60); - - \counter_RNO[15]\ : NOR2B - port map(A => un14_sample_in_val, B => I_91, Y => - \counter_4[15]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_data_shaping_out_57, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_3); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_data_shaping_out_62, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_8); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_data_shaping_out_0, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_95); - - \counter_RNO[7]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_38, Y => - \counter_4[7]\); - - \counter[6]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_data_shaping_out_91, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_33); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_data_shaping_out_96, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_38); - - \counter[3]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73); - - \counter_RNO[8]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_45, Y => - \counter_4[8]\); - - \counter_RNO[13]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_77, Y => - \counter_4[13]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52); - - \counter_RNIKF54[20]\ : NOR3A - port map(A => un14_sample_in_val_3, B => - \counter[23]_net_1\, C => \counter[20]_net_1\, Y => - un14_sample_in_val_15); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_data_shaping_out_12, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_83); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_data_shaping_out_10, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_85); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_data_shaping_out_49, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_50); - - \counter_RNO[12]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_73, Y => - \counter_4[12]\); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_data_shaping_out_37, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_62); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_data_shaping_out_43, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_56); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[17]_net_1\); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_data_shaping_out_5, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_90); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_data_shaping_out_51, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_48); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \counter_RNILSE[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un14_sample_in_val_1); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - \sample_out[115]\ : DFN1E1 - port map(D => sample_data_shaping_out_129, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_data_shaping_out_23, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_74); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_data_shaping_out_28, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_69); - - \counter_RNIB507[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un14_sample_in_val_13); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_data_shaping_out_2, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_93); - - \sample_out[98]\ : DFN1E1 - port map(D => sample_data_shaping_out_110, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_50); - - \sample_out[112]\ : DFN1E1 - port map(D => sample_data_shaping_out_126, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_15); - - \counter_RNIHDLE1_1[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa_0); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[27]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[27]_net_1\); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_data_shaping_out_104, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_46); - - \sample_out[111]\ : DFN1E1 - port map(D => sample_data_shaping_out_123, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_63); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166); - - \counter_RNO[17]\ : NOR2B - port map(A => un14_sample_in_val, B => I_105, Y => - \counter_4[17]\); - - \counter_RNII3CB1[10]\ : NOR2A - port map(A => sample_data_shaping_out_val_0, B => - un14_sample_in_val_0, Y => sample_out_val_19); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[23]_net_1\); - - \counter_RNIGCTE[12]\ : NOR3C - port map(A => un14_sample_in_val_9, B => - un14_sample_in_val_8, C => un14_sample_in_val_19, Y => - un14_sample_in_val_23); - - \counter_RNI8DT[27]\ : NOR3A - port map(A => un14_sample_in_val_1, B => - \counter[11]_net_1\, C => \counter[27]_net_1\, Y => - un14_sample_in_val_14); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_data_shaping_out_61, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_7); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \sample_out[114]\ : DFN1E1 - port map(D => sample_data_shaping_out_128, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196); - - \counter_RNIHDLE1_0[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa_2); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_data_shaping_out_36, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_63); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122); - - \sample_out[118]\ : DFN1E1 - port map(D => sample_data_shaping_out_132, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_9); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_data_shaping_out_63, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_9); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_data_shaping_out_32, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_65); - - \counter_RNO[14]\ : NOR2B - port map(A => un14_sample_in_val, B => I_84, Y => - \counter_4[14]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_data_shaping_out_95, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_37); - - \counter_RNI51T[12]\ : NOR3A - port map(A => un14_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un14_sample_in_val_19); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_data_shaping_out_val, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => un14_sample_in_val, B => I_186, Y => - \counter_4[26]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_data_shaping_out_4, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_91); - - \counter_RNO[5]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_24, Y => - \counter_4[5]\); - - \sample_out[103]\ : DFN1E1 - port map(D => sample_data_shaping_out_115, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_55); - - \sample_out[100]\ : DFN1E1 - port map(D => sample_data_shaping_out_112, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_52); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[25]_net_1\); - - \sample_out[123]\ : DFN1E1 - port map(D => sample_data_shaping_out_137, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_4); - - \sample_out[120]\ : DFN1E1 - port map(D => sample_data_shaping_out_134, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_7); - - \counter_RNI0RM3[10]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un14_sample_in_val_4); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_19, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f0_val); - - \counter_RNO[3]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_13, Y => - \counter_4[3]\); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_data_shaping_out_97, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_39); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_data_shaping_out_54, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_0); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_data_shaping_out_103, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_45); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_data_shaping_out_11, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_84); - - \sample_out[99]\ : DFN1E1 - port map(D => sample_data_shaping_out_111, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_51); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_data_shaping_out_18, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_79); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[5]_net_1\); - - \counter_RNIAGNA[24]\ : NOR3A - port map(A => un14_sample_in_val_13, B => - \counter[1]_net_1\, C => \counter[24]_net_1\, Y => - un14_sample_in_val_20); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_data_shaping_out_48, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_51); - - \counter_RNIP507[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un14_sample_in_val_9); - - \counter_RNIJKE[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un14_sample_in_val_5); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNINB64[22]\ : NOR3A - port map(A => un14_sample_in_val_7, B => - \counter[22]_net_1\, C => \counter[19]_net_1\, Y => - un14_sample_in_val_17); - - \counter_RNO[10]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_56, Y => - \counter_4[10]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9); - - \counter_RNO[21]\ : NOR2B - port map(A => un14_sample_in_val, B => I_136, Y => - \counter_4[21]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_data_shaping_out_27, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_70); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => un14_sample_in_val, B => I_173, Y => - \counter_4[25]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_0); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98); - - \counter_RNIHDLE1_3[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_data_shaping_out_29, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_68); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNO[6]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_31_0, Y => - \counter_4[6]\); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - \counter_RNI6DQF[20]\ : NOR3C - port map(A => un14_sample_in_val_15, B => - un14_sample_in_val_14, C => un14_sample_in_val_20, Y => - un14_sample_in_val_24); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_data_shaping_out_64, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_10); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[26]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66); - - \counter_RNO[23]\ : NOR2B - port map(A => un14_sample_in_val, B => I_156, Y => - \counter_4[23]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_data_shaping_out_60, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_6); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_data_shaping_out_47, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_52); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_data_shaping_out_55, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_1); - - sample_out_val_0 : DFN1C0 - port map(D => sample_out_val_19, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f0_val_0); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_data_shaping_out_102, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_44); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_data_shaping_out_98, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_40); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_data_shaping_out_100, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_42); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91); - - \counter_RNO[22]\ : NOR2B - port map(A => un14_sample_in_val, B => I_143, Y => - \counter_4[22]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_data_shaping_out_33, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_64); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_data_shaping_out_40, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_59); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_data_shaping_out_94, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_36); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_data_shaping_out_69, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_15); - - \counter_RNI5JN3[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un14_sample_in_val_3); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_data_shaping_out_15, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_80); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[113]\ : DFN1E1 - port map(D => sample_data_shaping_out_127, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_14); - - \sample_out[110]\ : DFN1E1 - port map(D => sample_data_shaping_out_122, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_62); - - \counter_RNO[4]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_20, Y => - \counter_4[4]\); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \sample_out[106]\ : DFN1E1 - port map(D => sample_data_shaping_out_118, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_58); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_data_shaping_out_19, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_78); - - \sample_out[107]\ : DFN1E1 - port map(D => sample_data_shaping_out_119, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_59); - - \counter_RNO[18]\ : NOR2B - port map(A => un14_sample_in_val, B => I_115, Y => - \counter_4[18]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[126]\ : DFN1E1 - port map(D => sample_data_shaping_out_140, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_1); - - \sample_out[127]\ : DFN1E1 - port map(D => sample_data_shaping_out_141, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_0); - - \counter_RNIKKE[21]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un14_sample_in_val_11); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_data_shaping_out_59, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_5); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_data_shaping_out_30, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_67); - - \counter_RNO[27]\ : NOR2B - port map(A => un14_sample_in_val, B => I_196, Y => - \counter_4[27]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_data_shaping_out_65, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_11); - - \sample_out[109]\ : DFN1E1 - port map(D => sample_data_shaping_out_121, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_61); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_data_shaping_out_26, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_71); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_data_shaping_out_46, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_53); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_data_shaping_out_44, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_55); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_data_shaping_out_93, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_35); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_data_shaping_out_99, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_41); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => un14_sample_in_val, B => I_166, Y => - \counter_4[24]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_data_shaping_out_6, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_89); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_data_shaping_out_68, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_14); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_data_shaping_out_66, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_12); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_data_shaping_out_39, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_60); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_data_shaping_out_101, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_43); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - \sample_out[96]\ : DFN1E1 - port map(D => sample_data_shaping_out_108, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_48); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - \counter_RNII507[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un14_sample_in_val_8); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNI1FN3[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un14_sample_in_val_7); - - sample_out_val_1 : DFN1C0 - port map(D => sample_out_val_19, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f0_val_1); - - \counter_RNO[20]\ : NOR2B - port map(A => un14_sample_in_val, B => I_129, Y => - \counter_4[20]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_data_shaping_out_41, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_58); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_data_shaping_out_25, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_72); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_data_shaping_out_58, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_4); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_data_shaping_out_31, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_66); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_data_shaping_out_56, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_2); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_data_shaping_out_20, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_77); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_data_shaping_out_9, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_wdata_86); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_data_shaping_out_7, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_88); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_data_shaping_out_14, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_81); - - \counter_RNIHDLE1_2[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa_3); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_data_shaping_out_92, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_34); - - \counter_RNO[2]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_9, Y => - \counter_4[2]\); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[9]_net_1\); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_data_shaping_out_90, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_32); - - \counter_RNO[19]\ : NOR2B - port map(A => un14_sample_in_val, B => I_122, Y => - \counter_4[19]\); - - \counter_RNIARB8[10]\ : NOR3C - port map(A => un14_sample_in_val_5, B => - un14_sample_in_val_4, C => un14_sample_in_val_17, Y => - un14_sample_in_val_22); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_52, Y => - \counter_4[9]\); - - \counter_RNI0L371_0[10]\ : OR3C - port map(A => un14_sample_in_val_23, B => - un14_sample_in_val_22, C => un14_sample_in_val_24, Y => - un14_sample_in_val); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143); - - \sample_out[116]\ : DFN1E1 - port map(D => sample_data_shaping_out_130, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_11); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[18]_net_1\); - - \sample_out[117]\ : DFN1E1 - port map(D => sample_data_shaping_out_131, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_10); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_data_shaping_out_8, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_wdata_87); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_data_shaping_out_45, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_54); - - \counter_RNO[16]\ : NOR2B - port map(A => un14_sample_in_val, B => I_98, Y => - \counter_4[16]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_data_shaping_out_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_data_shaping_out_50, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_49); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_data_shaping_out_3, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_92); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - \sample_out[105]\ : DFN1E1 - port map(D => sample_data_shaping_out_117, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_57); - - \sample_out[119]\ : DFN1E1 - port map(D => sample_data_shaping_out_133, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_8_16_6 is - - port( sample_f0_0 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_15 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_37 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_63 : in std_logic; - sample_f1_0 : out std_logic; - sample_f1_1 : out std_logic; - sample_f1_2 : out std_logic; - sample_f1_3 : out std_logic; - sample_f1_4 : out std_logic; - sample_f1_5 : out std_logic; - sample_f1_6 : out std_logic; - sample_f1_7 : out std_logic; - sample_f1_8 : out std_logic; - sample_f1_9 : out std_logic; - sample_f1_10 : out std_logic; - sample_f1_11 : out std_logic; - sample_f1_12 : out std_logic; - sample_f1_13 : out std_logic; - sample_f1_14 : out std_logic; - sample_f1_15 : out std_logic; - sample_f1_32 : out std_logic; - sample_f1_33 : out std_logic; - sample_f1_34 : out std_logic; - sample_f1_35 : out std_logic; - sample_f1_36 : out std_logic; - sample_f1_37 : out std_logic; - sample_f1_38 : out std_logic; - sample_f1_39 : out std_logic; - sample_f1_40 : out std_logic; - sample_f1_41 : out std_logic; - sample_f1_42 : out std_logic; - sample_f1_43 : out std_logic; - sample_f1_44 : out std_logic; - sample_f1_45 : out std_logic; - sample_f1_46 : out std_logic; - sample_f1_47 : out std_logic; - sample_f1_48 : out std_logic; - sample_f1_49 : out std_logic; - sample_f1_50 : out std_logic; - sample_f1_51 : out std_logic; - sample_f1_52 : out std_logic; - sample_f1_53 : out std_logic; - sample_f1_54 : out std_logic; - sample_f1_55 : out std_logic; - sample_f1_56 : out std_logic; - sample_f1_57 : out std_logic; - sample_f1_58 : out std_logic; - sample_f1_59 : out std_logic; - sample_f1_60 : out std_logic; - sample_f1_61 : out std_logic; - sample_f1_62 : out std_logic; - sample_f1_63 : out std_logic; - sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f1_wdata_95 : out std_logic; - sample_f1_wdata_94 : out std_logic; - sample_f1_wdata_93 : out std_logic; - sample_f1_wdata_92 : out std_logic; - sample_f1_wdata_91 : out std_logic; - sample_f1_wdata_90 : out std_logic; - sample_f1_wdata_89 : out std_logic; - sample_f1_wdata_88 : out std_logic; - sample_f1_wdata_87 : out std_logic; - sample_f1_wdata_86 : out std_logic; - sample_f1_wdata_85 : out std_logic; - sample_f1_wdata_84 : out std_logic; - sample_f1_wdata_83 : out std_logic; - sample_f1_wdata_82 : out std_logic; - sample_f1_wdata_81 : out std_logic; - sample_f1_wdata_80 : out std_logic; - sample_f1_wdata_79 : out std_logic; - sample_f1_wdata_78 : out std_logic; - sample_f1_wdata_77 : out std_logic; - sample_f1_wdata_76 : out std_logic; - sample_f1_wdata_75 : out std_logic; - sample_f1_wdata_74 : out std_logic; - sample_f1_wdata_73 : out std_logic; - sample_f1_wdata_72 : out std_logic; - sample_f1_wdata_71 : out std_logic; - sample_f1_wdata_70 : out std_logic; - sample_f1_wdata_69 : out std_logic; - sample_f1_wdata_68 : out std_logic; - sample_f1_wdata_67 : out std_logic; - sample_f1_wdata_66 : out std_logic; - sample_f1_wdata_65 : out std_logic; - sample_f1_wdata_64 : out std_logic; - sample_f1_wdata_63 : out std_logic; - sample_f1_wdata_62 : out std_logic; - sample_f1_wdata_61 : out std_logic; - sample_f1_wdata_60 : out std_logic; - sample_f1_wdata_59 : out std_logic; - sample_f1_wdata_58 : out std_logic; - sample_f1_wdata_57 : out std_logic; - sample_f1_wdata_56 : out std_logic; - sample_f1_wdata_55 : out std_logic; - sample_f1_wdata_54 : out std_logic; - sample_f1_wdata_53 : out std_logic; - sample_f1_wdata_52 : out std_logic; - sample_f1_wdata_51 : out std_logic; - sample_f1_wdata_50 : out std_logic; - sample_f1_wdata_49 : out std_logic; - sample_f1_wdata_48 : out std_logic; - sample_f1_wdata_15 : out std_logic; - sample_f1_wdata_14 : out std_logic; - sample_f1_wdata_13 : out std_logic; - sample_f1_wdata_12 : out std_logic; - sample_f1_wdata_11 : out std_logic; - sample_f1_wdata_10 : out std_logic; - sample_f1_wdata_9 : out std_logic; - sample_f1_wdata_8 : out std_logic; - sample_f1_wdata_7 : out std_logic; - sample_f1_wdata_6 : out std_logic; - sample_f1_wdata_5 : out std_logic; - sample_f1_wdata_4 : out std_logic; - sample_f1_wdata_3 : out std_logic; - sample_f1_wdata_2 : out std_logic; - sample_f1_wdata_1 : out std_logic; - sample_f1_wdata_0 : out std_logic; - sample_f0_val_1 : in std_logic; - sample_f1_val : out std_logic; - sample_f0_val_0 : in std_logic; - sample_out_0_sqmuxa_1 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_f1_val_0 : out std_logic - ); - -end Downsampling_8_16_6; - -architecture DEF_ARCH of Downsampling_8_16_6 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal sample_out_val_14, sample_out_0_sqmuxa_3, - un10_sample_in_val_24, un10_sample_in_val_25, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1_net_1, - sample_out_0_sqmuxa_1_0, sample_out_0_sqmuxa_0, - un10_sample_in_val_24_0, un10_sample_in_val_15, - un10_sample_in_val_14, un10_sample_in_val_20, - un10_sample_in_val_25_0, un10_sample_in_val_17, - un10_sample_in_val_16, un10_sample_in_val_23, N_137, - \counter[1]_net_1\, \counter[0]_net_1\, N_129, - \counter[3]_net_1\, \DWACT_FDEC_E[0]\, N_106, - \counter[8]_net_1\, \DWACT_FDEC_E[4]\, N_91, - \DWACT_FDEC_E[7]\, \DWACT_FDEC_E[6]\, - un10_sample_in_val_9, un10_sample_in_val_8, - un10_sample_in_val_19, un10_sample_in_val_13, - \counter[24]_net_1\, un10_sample_in_val_11, - \counter[15]_net_1\, \counter[12]_net_1\, - un10_sample_in_val_7, \counter[22]_net_1\, - \counter[19]_net_1\, un10_sample_in_val_5, - \counter[10]_net_1\, \counter[7]_net_1\, - un10_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un10_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, \counter_4[1]\, I_5_0, - \counter_4[3]\, I_13_0, \counter_4[4]\, I_20_0, - \counter_4[5]\, I_24_0, \counter_4[6]\, I_31_1, - \counter_4[7]\, I_38_0, \counter_4[8]\, I_45_0, - \counter_4[9]\, I_52_0, \counter_4[10]\, I_56_0, - \counter_4[11]\, I_66_0, \counter_4[12]\, I_73_0, - \counter_4[13]\, I_77_0, \counter_4[14]\, I_84_0, - \counter_4[15]\, I_91_0, \counter_4[16]\, I_98_0, - \counter_4[17]\, I_105_0, \counter_4[18]\, I_115_0, - \counter_4[19]\, I_122_0, \counter_4[20]\, I_129_0, - \counter_4[21]\, I_136_0, \counter_4[22]\, I_143_0, - \counter_4[23]\, I_156_0, \counter_4[24]\, I_166_0, - \counter_4[25]\, I_173_0, \counter_4[26]\, I_186_0, - \counter_4[27]\, I_196_0, sample_out_0_sqmuxa, I_4_0, - I_9_0, N_4, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - sample_out_0_sqmuxa_1 <= sample_out_0_sqmuxa_1_net_1; - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[19]_net_1\); - - \sample_out[125]\ : DFN1E1 - port map(D => sample_f0_wdata_2, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_2); - - \sample_out[102]\ : DFN1E1 - port map(D => sample_f0_54, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_54); - - \sample_out[122]\ : DFN1E1 - port map(D => sample_f0_wdata_5, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_5); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f0_wdata_73, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_73); - - \sample_out[101]\ : DFN1E1 - port map(D => sample_f0_53, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_53); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f0_wdata_75, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_75); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f0_wdata_82, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_82); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f0_wdata_94, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_94); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f0_wdata_76, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_76); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f0_13, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_13); - - \sample_out[121]\ : DFN1E1 - port map(D => sample_f0_wdata_6, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_6); - - \counter_RNIA89N_0[10]\ : NOR3C - port map(A => un10_sample_in_val_17, B => - un10_sample_in_val_16, C => un10_sample_in_val_23, Y => - un10_sample_in_val_25_0); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f0_wdata_57, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_57); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f0_47, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_47); - - \counter_RNO[11]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_66_0, Y => - \counter_4[11]\); - - \sample_out[104]\ : DFN1E1 - port map(D => sample_f0_56, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_56); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f0_wdata_61, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_61); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_0); - - \sample_out[124]\ : DFN1E1 - port map(D => sample_f0_wdata_3, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_3); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \sample_out[97]\ : DFN1E1 - port map(D => sample_f0_49, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_49); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_0); - - \sample_out[108]\ : DFN1E1 - port map(D => sample_f0_60, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_60); - - \counter_RNO[15]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_91_0, Y => \counter_4[15]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f0_3, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_3); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f0_8, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_8); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f0_wdata_95, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_95); - - \counter_RNO[7]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_38_0, Y => \counter_4[7]\); - - \counter[6]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_0); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f0_33, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_33); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f0_38, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_38); - - \counter[3]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_0, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val_1, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_0); - - \counter_RNO[8]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_45_0, Y => \counter_4[8]\); - - \counter_RNO[13]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_77_0, Y => - \counter_4[13]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_0); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f0_wdata_83, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_83); - - \counter_RNINF54[10]\ : NOR3A - port map(A => un10_sample_in_val_5, B => - \counter[10]_net_1\, C => \counter[7]_net_1\, Y => - un10_sample_in_val_16); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f0_wdata_85, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_85); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f0_wdata_50, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_50); - - \counter_RNO[12]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_73_0, Y => - \counter_4[12]\); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f0_wdata_62, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_62); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f0_wdata_56, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_56); - - \counter_RNO[1]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_5_0, Y => \counter_4[1]\); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[17]_net_1\); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter_RNIRB64[22]\ : NOR3A - port map(A => un10_sample_in_val_7, B => - \counter[22]_net_1\, C => \counter[19]_net_1\, Y => - un10_sample_in_val_17); - - \counter[4]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_0); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f0_wdata_90, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_90); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f0_wdata_48, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_48); - - \counter_RNI91T[12]\ : NOR3A - port map(A => un10_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un10_sample_in_val_19); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - \sample_out[115]\ : DFN1E1 - port map(D => sample_f0_wdata_12, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f0_wdata_74, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_74); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f0_wdata_69, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_69); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f0_wdata_93, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_93); - - \sample_out[98]\ : DFN1E1 - port map(D => sample_f0_50, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_50); - - \sample_out[112]\ : DFN1E1 - port map(D => sample_f0_wdata_15, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_15); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[27]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[27]_net_1\); - - \counter_RNIIDQF[20]\ : NOR3C - port map(A => un10_sample_in_val_15, B => - un10_sample_in_val_14, C => un10_sample_in_val_20, Y => - un10_sample_in_val_24); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f0_46, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_46); - - \sample_out[111]\ : DFN1E1 - port map(D => sample_f0_63, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_63); - - \counter_RNIMKE[21]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un10_sample_in_val_11); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_0); - - \counter_RNO[17]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_105_0, Y => \counter_4[17]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f0_7, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_7); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \sample_out[114]\ : DFN1E1 - port map(D => sample_f0_wdata_13, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_0); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f0_wdata_63, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_63); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_0); - - \counter_RNILKE[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un10_sample_in_val_5); - - \sample_out[118]\ : DFN1E1 - port map(D => sample_f0_wdata_9, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_9); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f0_9, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_9); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f0_wdata_65, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_65); - - \counter_RNO[14]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_84_0, Y => - \counter_4[14]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f0_37, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_37); - - \counter[1]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_186_0, Y => \counter_4[26]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f0_wdata_91, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_91); - - \counter_RNO[5]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_24_0, Y => \counter_4[5]\); - - \sample_out[103]\ : DFN1E1 - port map(D => sample_f0_55, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_55); - - \sample_out[100]\ : DFN1E1 - port map(D => sample_f0_52, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_52); - - \counter_RNI7KBF1_0[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa_2); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[25]_net_1\); - - \sample_out[123]\ : DFN1E1 - port map(D => sample_f0_wdata_4, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_4); - - \sample_out[120]\ : DFN1E1 - port map(D => sample_f0_wdata_7, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_7); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_14, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f1_val); - - \counter_RNO[3]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_13_0, Y => \counter_4[3]\); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f0_39, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_39); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_0); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_0); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f0_0, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_0); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_0); - - \counter_RNID507[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un10_sample_in_val_13); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f0_45, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_45); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f0_wdata_84, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_84); - - \sample_out[99]\ : DFN1E1 - port map(D => sample_f0_51, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_51); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f0_wdata_79, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_79); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f0_wdata_51, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_51); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_56_0, Y => - \counter_4[10]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_0); - - \counter_RNO[21]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_136_0, Y => \counter_4[21]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_0); - - \counter_RNIK507[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un10_sample_in_val_8); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f0_wdata_70, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_70); - - \counter_RNI7KBF1_3[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_0); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_173_0, Y => \counter_4[25]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_1); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_0); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f0_wdata_68, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_68); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNO[6]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_31_1, Y => \counter_4[6]\); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_0); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f0_10, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_10); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[26]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_0); - - \counter_RNO[23]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_156_0, Y => \counter_4[23]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f0_6, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_6); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f0_wdata_52, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_52); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f0_1, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_1); - - sample_out_val_0 : DFN1C0 - port map(D => sample_out_val_14, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f1_val_0); - - \counter_RNI3FN3[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un10_sample_in_val_7); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_0); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_0); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f0_44, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_44); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_0); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f0_40, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_40); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f0_42, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_42); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_0); - - \counter_RNO[22]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_143_0, Y => \counter_4[22]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f0_wdata_64, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_64); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f0_wdata_59, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_59); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out_0_sqmuxa_1\ : NOR2B - port map(A => sample_f0_val_0, B => HRESETn_c, Y => - sample_out_0_sqmuxa_1_net_1); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f0_36, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_36); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f0_15, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_15); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f0_wdata_80, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_80); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_0); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[113]\ : DFN1E1 - port map(D => sample_f0_wdata_14, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_14); - - \sample_out[110]\ : DFN1E1 - port map(D => sample_f0_62, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_62); - - \counter_RNO[4]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_20_0, Y => \counter_4[4]\); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \counter_RNI7KBF1_1[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa_0); - - \counter_RNINSE[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un10_sample_in_val_1); - - \sample_out[106]\ : DFN1E1 - port map(D => sample_f0_58, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_58); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_0); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f0_wdata_78, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_78); - - \sample_out[107]\ : DFN1E1 - port map(D => sample_f0_59, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_59); - - \counter_RNO[18]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_115_0, Y => \counter_4[18]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[126]\ : DFN1E1 - port map(D => sample_f0_wdata_1, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_1); - - \sample_out[127]\ : DFN1E1 - port map(D => sample_f0_wdata_0, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_0); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f0_5, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_5); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f0_wdata_67, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_67); - - \counter_RNO[27]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_196_0, Y => \counter_4[27]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f0_11, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_11); - - \counter_RNI7KBF1_2[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa_3); - - \sample_out[109]\ : DFN1E1 - port map(D => sample_f0_61, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_61); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f0_wdata_71, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_71); - - \counter_RNIOF54[20]\ : NOR3A - port map(A => un10_sample_in_val_3, B => - \counter[23]_net_1\, C => \counter[20]_net_1\, Y => - un10_sample_in_val_15); - - \counter_RNIOCTE[12]\ : NOR3C - port map(A => un10_sample_in_val_9, B => - un10_sample_in_val_8, C => un10_sample_in_val_19, Y => - un10_sample_in_val_23); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f0_wdata_53, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_53); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f0_wdata_55, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_55); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f0_35, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_35); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f0_41, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_41); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_166_0, Y => \counter_4[24]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_0); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f0_wdata_89, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_89); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f0_14, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_14); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f0_12, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_12); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \counter_RNI7JN3[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un10_sample_in_val_3); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f0_wdata_60, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_60); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f0_43, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_43); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - \sample_out[96]\ : DFN1E1 - port map(D => sample_f0_48, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_48); - - \counter_RNICDT[27]\ : NOR3A - port map(A => un10_sample_in_val_1, B => - \counter[11]_net_1\, C => \counter[27]_net_1\, Y => - un10_sample_in_val_14); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - \counter_RNI8A2C1[10]\ : NOR3C - port map(A => un10_sample_in_val_24_0, B => - un10_sample_in_val_25_0, C => sample_f0_val_0, Y => - sample_out_val_14); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_129_0, Y => \counter_4[20]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f0_wdata_58, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_58); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f0_wdata_72, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_72); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f0_4, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_4); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f0_wdata_66, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_66); - - \counter_RNIEGNA[24]\ : NOR3A - port map(A => un10_sample_in_val_13, B => - \counter[1]_net_1\, C => \counter[24]_net_1\, Y => - un10_sample_in_val_20); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f0_2, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_2); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f0_wdata_77, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_77); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f0_wdata_86, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_wdata_86); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f0_wdata_88, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_88); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f0_wdata_81, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_81); - - \counter_RNI7KBF1[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa_1_0); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f0_34, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_34); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[9]_net_1\); - - \counter_RNIA89N[10]\ : NOR3C - port map(A => un10_sample_in_val_17, B => - un10_sample_in_val_16, C => un10_sample_in_val_23, Y => - un10_sample_in_val_25); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f0_32, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_32); - - \counter_RNO[19]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_122_0, Y => \counter_4[19]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_52_0, Y => \counter_4[9]\); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_0); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_0); - - \counter_RNIR507[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un10_sample_in_val_9); - - \sample_out[116]\ : DFN1E1 - port map(D => sample_f0_wdata_11, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_11); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[18]_net_1\); - - \sample_out[117]\ : DFN1E1 - port map(D => sample_f0_wdata_10, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_10); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \counter_RNIIDQF_0[20]\ : NOR3C - port map(A => un10_sample_in_val_15, B => - un10_sample_in_val_14, C => un10_sample_in_val_20, Y => - un10_sample_in_val_24_0); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f0_wdata_87, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_wdata_87); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f0_wdata_54, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_54); - - \counter_RNO[16]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_98_0, Y => \counter_4[16]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_0, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f0_wdata_49, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_49); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f0_wdata_92, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_92); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - \sample_out[105]\ : DFN1E1 - port map(D => sample_f0_57, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_57); - - \sample_out[119]\ : DFN1E1 - port map(D => sample_f0_wdata_8, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity SYNC_FF_1 is - - port( cnv_run_c : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - cnv_run_sync : out std_logic - ); - -end SYNC_FF_1; - -architecture DEF_ARCH of SYNC_FF_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \A_temp[1]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sync_loop.0.A_temp[0]\ : DFN1C0 - port map(D => \A_temp[1]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => cnv_run_sync); - - GND_i_0 : GND - port map(Y => GND_0); - - \sync_loop.1.A_temp[1]\ : DFN1C0 - port map(D => cnv_run_c, CLK => HCLK_c, CLR => HRESETn_c, Q - => \A_temp[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity SYNC_FF is - - port( cnv_c : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - cnv_sync : out std_logic; - cnv_sync_i : out std_logic - ); - -end SYNC_FF; - -architecture DEF_ARCH of SYNC_FF is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \cnv_sync\, \A_temp[1]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - cnv_sync <= \cnv_sync\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sync_loop.0.A_temp[0]\ : DFN1C0 - port map(D => \A_temp[1]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => \cnv_sync\); - - GND_i_0 : GND - port map(Y => GND_0); - - \sync_loop.1.A_temp[1]\ : DFN1C0 - port map(D => cnv_c, CLK => HCLK_c, CLR => HRESETn_c, Q => - \A_temp[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sync_loop.0.A_temp_RNIEBA5[0]\ : INV - port map(A => \cnv_sync\, Y => cnv_sync_i); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity AD7688_drvr is - - port( sample_7 : out std_logic_vector(15 downto 0); - sample_0 : out std_logic_vector(15 downto 0); - sample_1 : out std_logic_vector(15 downto 0); - sample_2 : out std_logic_vector(15 downto 0); - sample_3 : out std_logic_vector(15 downto 0); - sample_4 : out std_logic_vector(15 downto 0); - sample_5 : out std_logic_vector(15 downto 0); - sdo_c : in std_logic_vector(7 downto 0); - sample_6 : out std_logic_vector(15 downto 0); - cnv_rstn_c : in std_logic; - cnv_clk_c : in std_logic; - cnv_c : out std_logic; - sample_val : out std_logic; - sck_c : out std_logic; - cnv_run_c : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end AD7688_drvr; - -architecture DEF_ARCH of AD7688_drvr is - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component SYNC_FF_1 - port( cnv_run_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - cnv_run_sync : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component SYNC_FF - port( cnv_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - cnv_sync : out std_logic; - cnv_sync_i : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \sample_bit_counter_4[0]_net_1\, - sample_bit_counter_n0, N_6, - \sample_bit_counter_3[0]_net_1\, - \sample_bit_counter_2[0]_net_1\, - \sample_bit_counter_1[0]_net_1\, - \sample_bit_counter_0[0]_net_1\, sample_0_0_sqmuxa, - \sample_bit_counter_RNIVMI9[5]_net_1\, - \sample_bit_counter_i[0]\, sample_bit_counterlde_i_a3_0_1, - \sample_bit_counter[3]_net_1\, - \sample_bit_counter[2]_net_1\, - \sample_bit_counter[4]_net_1\, un3_cnv_runlto8_0, - \cnv_cycle_counter[8]_net_1\, - \cnv_cycle_counter[7]_net_1\, un3_cnv_runlto5_0, - \cnv_cycle_counter[4]_net_1\, - \cnv_cycle_counter[5]_net_1\, un2_cnv_runlto8_2, - \cnv_cycle_counter[2]_net_1\, - \cnv_cycle_counter[3]_net_1\, un2_cnv_runlto8_1, - \cnv_cycle_counter[6]_net_1\, un2_cnv_runlto8_0, N_30, - N_38, N_36, N_17, N_22, N_15, N_21, N_13, N_20, N_11, - un3_cnv_runlt6, cnv_cycle_counter_c2, un3_cnv_run, - un2_cnv_run, cnv_cycle_counter_n8, cnv_cycle_counter_33_0, - cnv_s_0_sqmuxa, cnv_cycle_counter_n7, - cnv_cycle_counter_c6, cnv_cycle_counter_n6, - cnv_cycle_counter_c5, cnv_cycle_counter_n5, - cnv_cycle_counter_c4, cnv_cycle_counter_n4, - cnv_cycle_counter_n4_tz_i, cnv_cycle_counter_n3, - cnv_cycle_counter_n3_tz_i, cnv_cycle_counter_n2, - cnv_cycle_counter_n2_tz_i, \cnv_cycle_counter[0]_net_1\, - \cnv_cycle_counter[1]_net_1\, N_23, - \sample_bit_counter[1]_net_1\, N_19, cnv_done_i, - cnv_run_sync, \sample_bit_counter[5]_net_1\, - \sample_bit_counter_RNI0D96[5]_net_1\, - cnv_cycle_counter_n1, cnv_cycle_counter_n0, \cnv_s_RNO\, - cnv_done_1, cnv_sync_r_i_0, cnv_sync, cnv_sync_i, - \sample_bit_counter[0]_net_1\, \shift_reg_6[0]_net_1\, - \shift_reg_6[1]_net_1\, \shift_reg_6[2]_net_1\, - \shift_reg_6[3]_net_1\, \shift_reg_6[4]_net_1\, - \shift_reg_6[5]_net_1\, \shift_reg_6[6]_net_1\, - \shift_reg_6[7]_net_1\, \shift_reg_6[8]_net_1\, - \shift_reg_6[9]_net_1\, \shift_reg_6[10]_net_1\, - \shift_reg_6[11]_net_1\, \shift_reg_6[12]_net_1\, - \shift_reg_6[13]_net_1\, \shift_reg_6[14]_net_1\, - \shift_reg_5[0]_net_1\, \shift_reg_5[1]_net_1\, - \shift_reg_5[2]_net_1\, \shift_reg_5[3]_net_1\, - \shift_reg_5[4]_net_1\, \shift_reg_5[5]_net_1\, - \shift_reg_5[6]_net_1\, \shift_reg_5[7]_net_1\, - \shift_reg_5[8]_net_1\, \shift_reg_5[9]_net_1\, - \shift_reg_5[10]_net_1\, \shift_reg_5[11]_net_1\, - \shift_reg_5[12]_net_1\, \shift_reg_5[13]_net_1\, - \shift_reg_5[14]_net_1\, \shift_reg_4[0]_net_1\, - \shift_reg_4[1]_net_1\, \shift_reg_4[2]_net_1\, - \shift_reg_4[3]_net_1\, \shift_reg_4[4]_net_1\, - \shift_reg_4[5]_net_1\, \shift_reg_4[6]_net_1\, - \shift_reg_4[7]_net_1\, \shift_reg_4[8]_net_1\, - \shift_reg_4[9]_net_1\, \shift_reg_4[10]_net_1\, - \shift_reg_4[11]_net_1\, \shift_reg_4[12]_net_1\, - \shift_reg_4[13]_net_1\, \shift_reg_4[14]_net_1\, - \shift_reg_3[0]_net_1\, \shift_reg_3[1]_net_1\, - \shift_reg_3[2]_net_1\, \shift_reg_3[3]_net_1\, - \shift_reg_3[4]_net_1\, \shift_reg_3[5]_net_1\, - \shift_reg_3[6]_net_1\, \shift_reg_3[7]_net_1\, - \shift_reg_3[8]_net_1\, \shift_reg_3[9]_net_1\, - \shift_reg_3[10]_net_1\, \shift_reg_3[11]_net_1\, - \shift_reg_3[12]_net_1\, \shift_reg_3[13]_net_1\, - \shift_reg_3[14]_net_1\, \shift_reg_2[0]_net_1\, - \shift_reg_2[1]_net_1\, \shift_reg_2[2]_net_1\, - \shift_reg_2[3]_net_1\, \shift_reg_2[4]_net_1\, - \shift_reg_2[5]_net_1\, \shift_reg_2[6]_net_1\, - \shift_reg_2[7]_net_1\, \shift_reg_2[8]_net_1\, - \shift_reg_2[9]_net_1\, \shift_reg_2[10]_net_1\, - \shift_reg_2[11]_net_1\, \shift_reg_2[12]_net_1\, - \shift_reg_2[13]_net_1\, \shift_reg_2[14]_net_1\, - \shift_reg_1[0]_net_1\, \shift_reg_1[1]_net_1\, - \shift_reg_1[2]_net_1\, \shift_reg_1[3]_net_1\, - \shift_reg_1[4]_net_1\, \shift_reg_1[5]_net_1\, - \shift_reg_1[6]_net_1\, \shift_reg_1[7]_net_1\, - \shift_reg_1[8]_net_1\, \shift_reg_1[9]_net_1\, - \shift_reg_1[10]_net_1\, \shift_reg_1[11]_net_1\, - \shift_reg_1[12]_net_1\, \shift_reg_1[13]_net_1\, - \shift_reg_1[14]_net_1\, \shift_reg_0[0]_net_1\, - \shift_reg_0[1]_net_1\, \shift_reg_0[2]_net_1\, - \shift_reg_0[3]_net_1\, \shift_reg_0[4]_net_1\, - \shift_reg_0[5]_net_1\, \shift_reg_0[6]_net_1\, - \shift_reg_0[7]_net_1\, \shift_reg_0[8]_net_1\, - \shift_reg_0[9]_net_1\, \shift_reg_0[10]_net_1\, - \shift_reg_0[11]_net_1\, \shift_reg_0[12]_net_1\, - \shift_reg_0[13]_net_1\, \shift_reg_0[14]_net_1\, - \shift_reg_7[0]_net_1\, \shift_reg_7[1]_net_1\, - \shift_reg_7[2]_net_1\, \shift_reg_7[3]_net_1\, - \shift_reg_7[4]_net_1\, \shift_reg_7[5]_net_1\, - \shift_reg_7[6]_net_1\, \shift_reg_7[7]_net_1\, - \shift_reg_7[8]_net_1\, \shift_reg_7[9]_net_1\, - \shift_reg_7[10]_net_1\, \shift_reg_7[11]_net_1\, - \shift_reg_7[12]_net_1\, \shift_reg_7[13]_net_1\, - \shift_reg_7[14]_net_1\, \cnv_c\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : SYNC_FF_1 - Use entity work.SYNC_FF_1(DEF_ARCH); - for all : SYNC_FF - Use entity work.SYNC_FF(DEF_ARCH); -begin - - cnv_c <= \cnv_c\; - - \sample_bit_counter[2]\ : DFN1E0C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[2]_net_1\); - - \shift_reg_0[1]\ : DFN1E1C0 - port map(D => \shift_reg_0[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[1]_net_1\); - - \cnv_cycle_counter_RNO_0[2]\ : AX1E - port map(A => \cnv_cycle_counter[0]_net_1\, B => - \cnv_cycle_counter[1]_net_1\, C => - \cnv_cycle_counter[2]_net_1\, Y => - cnv_cycle_counter_n2_tz_i); - - \shift_reg_7[14]\ : DFN1E1C0 - port map(D => \shift_reg_7[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[14]_net_1\); - - \sample_6[13]\ : DFN1E1 - port map(D => \shift_reg_6[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(13)); - - \sample_7[11]\ : DFN1E1 - port map(D => \shift_reg_7[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(11)); - - \sample_0[3]\ : DFN1E1 - port map(D => \shift_reg_0[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(3)); - - \shift_reg_6[12]\ : DFN1E1C0 - port map(D => \shift_reg_6[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[12]_net_1\); - - \sample_1[0]\ : DFN1E1 - port map(D => sdo_c(1), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(0)); - - \sample_0[12]\ : DFN1E1 - port map(D => \shift_reg_0[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(12)); - - \shift_reg_6[9]\ : DFN1E1C0 - port map(D => \shift_reg_6[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[9]_net_1\); - - \shift_reg_2[0]\ : DFN1E1C0 - port map(D => sdo_c(2), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[0]_net_1\); - - \shift_reg_5[11]\ : DFN1E1C0 - port map(D => \shift_reg_5[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_5[11]_net_1\); - - cnv_s : DFN1C0 - port map(D => \cnv_s_RNO\, CLK => cnv_clk_c, CLR => - cnv_rstn_c, Q => \cnv_c\); - - \sample_6[11]\ : DFN1E1 - port map(D => \shift_reg_6[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(11)); - - \sample_3[9]\ : DFN1E1 - port map(D => \shift_reg_3[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(9)); - - \shift_reg_0[10]\ : DFN1E1C0 - port map(D => \shift_reg_0[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[10]_net_1\); - - \shift_reg_7[6]\ : DFN1E1C0 - port map(D => \shift_reg_7[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[6]_net_1\); - - \shift_reg_7[2]\ : DFN1E1C0 - port map(D => \shift_reg_7[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[2]_net_1\); - - \sample_2[6]\ : DFN1E1 - port map(D => \shift_reg_2[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(6)); - - \cnv_cycle_counter[4]\ : DFN1C0 - port map(D => cnv_cycle_counter_n4, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[4]_net_1\); - - \cnv_cycle_counter_RNO[2]\ : NOR2 - port map(A => cnv_s_0_sqmuxa, B => - cnv_cycle_counter_n2_tz_i, Y => cnv_cycle_counter_n2); - - \sample_6[2]\ : DFN1E1 - port map(D => \shift_reg_6[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(2)); - - \sample_7[5]\ : DFN1E1 - port map(D => \shift_reg_7[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(5)); - - \shift_reg_5[6]\ : DFN1E1C0 - port map(D => \shift_reg_5[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[6]_net_1\); - - \shift_reg_0[14]\ : DFN1E1C0 - port map(D => \shift_reg_0[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[14]_net_1\); - - \shift_reg_1[7]\ : DFN1E1C0 - port map(D => \shift_reg_1[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[7]_net_1\); - - \sample_0[15]\ : DFN1E1 - port map(D => \shift_reg_0[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(15)); - - \sample_2[4]\ : DFN1E1 - port map(D => \shift_reg_2[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(4)); - - \sample_bit_counter_RNO[3]\ : XA1B - port map(A => N_21, B => \sample_bit_counter[3]_net_1\, C - => N_36, Y => N_15); - - \sample_1[6]\ : DFN1E1 - port map(D => \shift_reg_1[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(6)); - - \cnv_cycle_counter_RNO[8]\ : XA1C - port map(A => \cnv_cycle_counter[8]_net_1\, B => - cnv_cycle_counter_33_0, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n8); - - \sample_2[14]\ : DFN1E1 - port map(D => \shift_reg_2[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(14)); - - \sample_5[10]\ : DFN1E1 - port map(D => \shift_reg_5[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(10)); - - \sample_2[0]\ : DFN1E1 - port map(D => sdo_c(2), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(0)); - - \sample_5[1]\ : DFN1E1 - port map(D => \shift_reg_5[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(1)); - - \shift_reg_4[13]\ : DFN1E1C0 - port map(D => \shift_reg_4[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[13]_net_1\); - - \cnv_cycle_counter_RNO[1]\ : XA1B - port map(A => \cnv_cycle_counter[1]_net_1\, B => - \cnv_cycle_counter[0]_net_1\, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n1); - - \shift_reg_7[5]\ : DFN1E1C0 - port map(D => \shift_reg_7[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[5]_net_1\); - - \sample_0[7]\ : DFN1E1 - port map(D => \shift_reg_0[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(7)); - - \sample_0[13]\ : DFN1E1 - port map(D => \shift_reg_0[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(13)); - - \shift_reg_1[10]\ : DFN1E1C0 - port map(D => \shift_reg_1[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_1[10]_net_1\); - - \sample_6[3]\ : DFN1E1 - port map(D => \shift_reg_6[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(3)); - - \shift_reg_1[5]\ : DFN1E1C0 - port map(D => \shift_reg_1[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[5]_net_1\); - - \shift_reg_5[1]\ : DFN1E1C0 - port map(D => \shift_reg_5[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[1]_net_1\); - - \shift_reg_1[14]\ : DFN1E1C0 - port map(D => \shift_reg_1[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[14]_net_1\); - - cnv_done_RNO : OR2 - port map(A => cnv_sync_r_i_0, B => cnv_sync, Y => - cnv_done_1); - - \shift_reg_6[2]\ : DFN1E1C0 - port map(D => \shift_reg_6[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[2]_net_1\); - - \shift_reg_3[5]\ : DFN1E1C0 - port map(D => \shift_reg_3[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[5]_net_1\); - - cnv_done_RNI4H78 : AOI1B - port map(A => \sample_bit_counter_0[0]_net_1\, B => - cnv_done_i, C => cnv_run_sync, Y => sample_bit_counter_n0); - - \sample_7[6]\ : DFN1E1 - port map(D => \shift_reg_7[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(6)); - - \sample_7[10]\ : DFN1E1 - port map(D => \shift_reg_7[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(10)); - - \sample_6[6]\ : DFN1E1 - port map(D => \shift_reg_6[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(6)); - - \sample_0[11]\ : DFN1E1 - port map(D => \shift_reg_0[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(11)); - - \shift_reg_0[0]\ : DFN1E1C0 - port map(D => sdo_c(0), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[0]_net_1\); - - \sample_0[0]\ : DFN1E1 - port map(D => sdo_c(0), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(0)); - - \sample_5[4]\ : DFN1E1 - port map(D => \shift_reg_5[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(4)); - - \sample_7[9]\ : DFN1E1 - port map(D => \shift_reg_7[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(9)); - - \sample_4[9]\ : DFN1E1 - port map(D => \shift_reg_4[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(9)); - - \cnv_cycle_counter[6]\ : DFN1C0 - port map(D => cnv_cycle_counter_n6, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[6]_net_1\); - - \shift_reg_2[12]\ : DFN1E1C0 - port map(D => \shift_reg_2[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[12]_net_1\); - - \sample_bit_counter_1[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_1[0]_net_1\); - - \sample_5[9]\ : DFN1E1 - port map(D => \shift_reg_5[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(9)); - - \shift_reg_7[0]\ : DFN1E1C0 - port map(D => sdo_c(7), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[0]_net_1\); - - SYNC_FF_run : SYNC_FF_1 - port map(cnv_run_c => cnv_run_c, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, cnv_run_sync => cnv_run_sync); - - \shift_reg_1[1]\ : DFN1E1C0 - port map(D => \shift_reg_1[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[1]_net_1\); - - \shift_reg_3[9]\ : DFN1E1C0 - port map(D => \shift_reg_3[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_3[9]_net_1\); - - \sample_5[7]\ : DFN1E1 - port map(D => \shift_reg_5[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(7)); - - \sample_bit_counter[5]\ : DFN1E0C0 - port map(D => N_19, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[5]_net_1\); - - \sample_6[10]\ : DFN1E1 - port map(D => \shift_reg_6[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(10)); - - \sample_3[12]\ : DFN1E1 - port map(D => \shift_reg_3[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(12)); - - \shift_reg_3[6]\ : DFN1E1C0 - port map(D => \shift_reg_3[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[6]_net_1\); - - \sample_5[0]\ : DFN1E1 - port map(D => sdo_c(5), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(0)); - - \sample_4[7]\ : DFN1E1 - port map(D => \shift_reg_4[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(7)); - - \shift_reg_0[5]\ : DFN1E1C0 - port map(D => \shift_reg_0[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[5]_net_1\); - - \sample_bit_counter[4]\ : DFN1E0C0 - port map(D => N_17, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[4]_net_1\); - - \sample_4[12]\ : DFN1E1 - port map(D => \shift_reg_4[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(12)); - - \sample_2[7]\ : DFN1E1 - port map(D => \shift_reg_2[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(7)); - - \shift_reg_7[8]\ : DFN1E1C0 - port map(D => \shift_reg_7[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[8]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \sample_bit_counter_RNID104[3]\ : NOR2B - port map(A => \sample_bit_counter[3]_net_1\, B => N_21, Y - => N_22); - - \shift_reg_0[3]\ : DFN1E1C0 - port map(D => \shift_reg_0[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[3]_net_1\); - - \sample_bit_counter_RNILHR2[2]\ : NOR2B - port map(A => \sample_bit_counter[2]_net_1\, B => N_20, Y - => N_21); - - \sample_bit_counter_RNIOIIL[5]\ : AO1A - port map(A => N_36, B => \sample_bit_counter[5]_net_1\, C - => N_30, Y => N_6); - - \shift_reg_6[11]\ : DFN1E1C0 - port map(D => \shift_reg_6[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[11]_net_1\); - - \sample_3[15]\ : DFN1E1 - port map(D => \shift_reg_3[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(15)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \shift_reg_3[8]\ : DFN1E1C0 - port map(D => \shift_reg_3[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[8]_net_1\); - - \shift_reg_4[10]\ : DFN1E1C0 - port map(D => \shift_reg_4[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[10]_net_1\); - - \sample_4[15]\ : DFN1E1 - port map(D => \shift_reg_4[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(15)); - - \shift_reg_5[13]\ : DFN1E1C0 - port map(D => \shift_reg_5[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_5[13]_net_1\); - - \shift_reg_3[7]\ : DFN1E1C0 - port map(D => \shift_reg_3[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[7]_net_1\); - - \sample_0[2]\ : DFN1E1 - port map(D => \shift_reg_0[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(2)); - - \cnv_cycle_counter_RNITOET[2]\ : OR2B - port map(A => un2_cnv_run, B => cnv_run_c, Y => - cnv_s_0_sqmuxa); - - \shift_reg_4[14]\ : DFN1E1C0 - port map(D => \shift_reg_4[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[14]_net_1\); - - \sample_bit_counter_RNI8FD3[2]\ : NOR3 - port map(A => \sample_bit_counter[3]_net_1\, B => - \sample_bit_counter[2]_net_1\, C => - \sample_bit_counter[4]_net_1\, Y => - sample_bit_counterlde_i_a3_0_1); - - \sample_0[5]\ : DFN1E1 - port map(D => \shift_reg_0[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(5)); - - \sample_3[13]\ : DFN1E1 - port map(D => \shift_reg_3[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(13)); - - \sample_bit_counter_RNIVMI9_0[5]\ : CLKINT - port map(A => \sample_bit_counter_RNIVMI9[5]_net_1\, Y => - sample_0_0_sqmuxa); - - \sample_2[5]\ : DFN1E1 - port map(D => \shift_reg_2[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(5)); - - \shift_reg_2[5]\ : DFN1E1C0 - port map(D => \shift_reg_2[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[5]_net_1\); - - \sample_4[13]\ : DFN1E1 - port map(D => \shift_reg_4[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(13)); - - \sample_3[1]\ : DFN1E1 - port map(D => \shift_reg_3[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(1)); - - \sample_0[1]\ : DFN1E1 - port map(D => \shift_reg_0[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(1)); - - \sample_0[10]\ : DFN1E1 - port map(D => \shift_reg_0[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(10)); - - \shift_reg_0[2]\ : DFN1E1C0 - port map(D => \shift_reg_0[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[2]_net_1\); - - \sample_2[12]\ : DFN1E1 - port map(D => \shift_reg_2[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(12)); - - \sample_6[0]\ : DFN1E1 - port map(D => sdo_c(6), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(0)); - - \shift_reg_3[12]\ : DFN1E1C0 - port map(D => \shift_reg_3[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[12]_net_1\); - - \sample_val\ : DFN1C0 - port map(D => \sample_bit_counter_RNI0D96[5]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => sample_val); - - \cnv_cycle_counter_RNO[3]\ : NOR2 - port map(A => cnv_s_0_sqmuxa, B => - cnv_cycle_counter_n3_tz_i, Y => cnv_cycle_counter_n3); - - \sample_3[11]\ : DFN1E1 - port map(D => \shift_reg_3[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(11)); - - \sample_0[9]\ : DFN1E1 - port map(D => \shift_reg_0[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(9)); - - \shift_reg_5[8]\ : DFN1E1C0 - port map(D => \shift_reg_5[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[8]_net_1\); - - \sample_bit_counter_RNO[4]\ : XA1B - port map(A => N_22, B => \sample_bit_counter[4]_net_1\, C - => N_36, Y => N_17); - - \cnv_cycle_counter[3]\ : DFN1C0 - port map(D => cnv_cycle_counter_n3, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[3]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_4[11]\ : DFN1E1 - port map(D => \shift_reg_4[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(11)); - - \shift_reg_7[12]\ : DFN1E1C0 - port map(D => \shift_reg_7[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[12]_net_1\); - - \sample_6[7]\ : DFN1E1 - port map(D => \shift_reg_6[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(7)); - - \sample_2[9]\ : DFN1E1 - port map(D => \shift_reg_2[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(9)); - - \cnv_cycle_counter_RNO_0[8]\ : OR2B - port map(A => cnv_cycle_counter_c6, B => - \cnv_cycle_counter[7]_net_1\, Y => cnv_cycle_counter_33_0); - - \shift_reg_6[1]\ : DFN1E1C0 - port map(D => \shift_reg_6[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[1]_net_1\); - - \shift_reg_7[7]\ : DFN1E1C0 - port map(D => \shift_reg_7[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[7]_net_1\); - - \sample_2[15]\ : DFN1E1 - port map(D => \shift_reg_2[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(15)); - - \sample_bit_counter_0[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_0[0]_net_1\); - - \shift_reg_6[3]\ : DFN1E1C0 - port map(D => \shift_reg_6[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[3]_net_1\); - - \sample_6[4]\ : DFN1E1 - port map(D => \shift_reg_6[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(4)); - - \sample_4[3]\ : DFN1E1 - port map(D => \shift_reg_4[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(3)); - - \sample_1[9]\ : DFN1E1 - port map(D => \shift_reg_1[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(9)); - - \cnv_cycle_counter_RNO_0[4]\ : AX1E - port map(A => \cnv_cycle_counter[3]_net_1\, B => - cnv_cycle_counter_c2, C => \cnv_cycle_counter[4]_net_1\, - Y => cnv_cycle_counter_n4_tz_i); - - \shift_reg_5[5]\ : DFN1E1C0 - port map(D => \shift_reg_5[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[5]_net_1\); - - \cnv_cycle_counter[7]\ : DFN1C0 - port map(D => cnv_cycle_counter_n7, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[7]_net_1\); - - \sample_1[14]\ : DFN1E1 - port map(D => \shift_reg_1[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(14)); - - \shift_reg_2[11]\ : DFN1E1C0 - port map(D => \shift_reg_2[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[11]_net_1\); - - \shift_reg_7[3]\ : DFN1E1C0 - port map(D => \shift_reg_7[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[3]_net_1\); - - \shift_reg_5[10]\ : DFN1E1C0 - port map(D => \shift_reg_5[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_5[10]_net_1\); - - \shift_reg_3[4]\ : DFN1E1C0 - port map(D => \shift_reg_3[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[4]_net_1\); - - \sample_2[13]\ : DFN1E1 - port map(D => \shift_reg_2[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(13)); - - \sample_bit_counter_RNI0D96[5]\ : NOR2 - port map(A => \sample_bit_counter[5]_net_1\, B => N_23, Y - => \sample_bit_counter_RNI0D96[5]_net_1\); - - \sample_3[0]\ : DFN1E1 - port map(D => sdo_c(3), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(0)); - - \shift_reg_0[12]\ : DFN1E1C0 - port map(D => \shift_reg_0[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[12]_net_1\); - - \sample_4[2]\ : DFN1E1 - port map(D => \shift_reg_4[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(2)); - - \sample_bit_counter[1]\ : DFN1E0C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[1]_net_1\); - - \shift_reg_5[14]\ : DFN1E1C0 - port map(D => \shift_reg_5[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[14]_net_1\); - - \sample_7[0]\ : DFN1E1 - port map(D => sdo_c(7), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(0)); - - \sample_bit_counter_RNI28PC[2]\ : NOR3B - port map(A => sample_bit_counterlde_i_a3_0_1, B => N_38, C - => N_36, Y => N_30); - - \sample_2[3]\ : DFN1E1 - port map(D => \shift_reg_2[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(3)); - - \sample_3[7]\ : DFN1E1 - port map(D => \shift_reg_3[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(7)); - - \sample_7[1]\ : DFN1E1 - port map(D => \shift_reg_7[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(1)); - - \sample_2[11]\ : DFN1E1 - port map(D => \shift_reg_2[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(11)); - - cnv_sync_r : DFN1P0 - port map(D => cnv_sync_i, CLK => HCLK_c, PRE => HRESETn_c, - Q => cnv_sync_r_i_0); - - \cnv_cycle_counter_RNI6D3R[6]\ : NOR2A - port map(A => \cnv_cycle_counter[6]_net_1\, B => - cnv_cycle_counter_c5, Y => cnv_cycle_counter_c6); - - \shift_reg_1[9]\ : DFN1E1C0 - port map(D => \shift_reg_1[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[9]_net_1\); - - \shift_reg_6[13]\ : DFN1E1C0 - port map(D => \shift_reg_6[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[13]_net_1\); - - \sample_6[1]\ : DFN1E1 - port map(D => \shift_reg_6[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(1)); - - \shift_reg_0[8]\ : DFN1E1C0 - port map(D => \shift_reg_0[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[8]_net_1\); - - \sample_3[10]\ : DFN1E1 - port map(D => \shift_reg_3[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(10)); - - \shift_reg_4[0]\ : DFN1E1C0 - port map(D => sdo_c(4), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[0]_net_1\); - - SYNC_FF_cnv : SYNC_FF - port map(cnv_c => \cnv_c\, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c, cnv_sync => cnv_sync, cnv_sync_i => - cnv_sync_i); - - \shift_reg_2[2]\ : DFN1E1C0 - port map(D => \shift_reg_2[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[2]_net_1\); - - \sample_bit_counter_RNIU5N1_0[1]\ : NOR2 - port map(A => \sample_bit_counter[1]_net_1\, B => - \sample_bit_counter_0[0]_net_1\, Y => N_38); - - \shift_reg_1[3]\ : DFN1E1C0 - port map(D => \shift_reg_1[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[3]_net_1\); - - \shift_reg_1[12]\ : DFN1E1C0 - port map(D => \shift_reg_1[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[12]_net_1\); - - \sample_7[2]\ : DFN1E1 - port map(D => \shift_reg_7[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(2)); - - \sample_4[10]\ : DFN1E1 - port map(D => \shift_reg_4[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(10)); - - \sample_bit_counter_RNIU5N1[1]\ : NOR2B - port map(A => \sample_bit_counter[1]_net_1\, B => - \sample_bit_counter_0[0]_net_1\, Y => N_20); - - \sample_3[8]\ : DFN1E1 - port map(D => \shift_reg_3[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(8)); - - \shift_reg_3[3]\ : DFN1E1C0 - port map(D => \shift_reg_3[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[3]_net_1\); - - \shift_reg_1[8]\ : DFN1E1C0 - port map(D => \shift_reg_1[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[8]_net_1\); - - \sample_bit_counter_3[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_3[0]_net_1\); - - \cnv_cycle_counter[8]\ : DFN1C0 - port map(D => cnv_cycle_counter_n8, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[8]_net_1\); - - \sample_bit_counter[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter[0]_net_1\); - - \sample_1[1]\ : DFN1E1 - port map(D => \shift_reg_1[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(1)); - - \shift_reg_4[1]\ : DFN1E1C0 - port map(D => \shift_reg_4[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[1]_net_1\); - - \cnv_cycle_counter_RNO[0]\ : NOR2 - port map(A => \cnv_cycle_counter[0]_net_1\, B => - cnv_s_0_sqmuxa, Y => cnv_cycle_counter_n0); - - \sample_5[14]\ : DFN1E1 - port map(D => \shift_reg_5[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(14)); - - \cnv_cycle_counter_RNIQQN7[8]\ : NOR2B - port map(A => \cnv_cycle_counter[8]_net_1\, B => - \cnv_cycle_counter[4]_net_1\, Y => un2_cnv_runlto8_0); - - \shift_reg_3[1]\ : DFN1E1C0 - port map(D => \shift_reg_3[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[1]_net_1\); - - \shift_reg_2[8]\ : DFN1E1C0 - port map(D => \shift_reg_2[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[8]_net_1\); - - \sample_2[8]\ : DFN1E1 - port map(D => \shift_reg_2[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(8)); - - \shift_reg_3[11]\ : DFN1E1C0 - port map(D => \shift_reg_3[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[11]_net_1\); - - \shift_reg_0[4]\ : DFN1E1C0 - port map(D => \shift_reg_0[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[4]_net_1\); - - \sample_4[5]\ : DFN1E1 - port map(D => \shift_reg_4[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(5)); - - \sample_0[4]\ : DFN1E1 - port map(D => \shift_reg_0[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(4)); - - \shift_reg_7[11]\ : DFN1E1C0 - port map(D => \shift_reg_7[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[11]_net_1\); - - \shift_reg_3[0]\ : DFN1E1C0 - port map(D => sdo_c(3), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[0]_net_1\); - - \sample_3[4]\ : DFN1E1 - port map(D => \shift_reg_3[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(4)); - - \sample_5[5]\ : DFN1E1 - port map(D => \shift_reg_5[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(5)); - - \shift_reg_1[0]\ : DFN1E1C0 - port map(D => sdo_c(1), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_1[0]_net_1\); - - \shift_reg_4[9]\ : DFN1E1C0 - port map(D => \shift_reg_4[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[9]_net_1\); - - \shift_reg_1[6]\ : DFN1E1C0 - port map(D => \shift_reg_1[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[6]_net_1\); - - \sample_4[1]\ : DFN1E1 - port map(D => \shift_reg_4[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(1)); - - \shift_reg_2[9]\ : DFN1E1C0 - port map(D => \shift_reg_2[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[9]_net_1\); - - cnv_done_RNISIK7 : OR2B - port map(A => cnv_run_sync, B => cnv_done_i, Y => N_36); - - \shift_reg_4[2]\ : DFN1E1C0 - port map(D => \shift_reg_4[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[2]_net_1\); - - \sample_7[8]\ : DFN1E1 - port map(D => \shift_reg_7[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(8)); - - \sample_7[14]\ : DFN1E1 - port map(D => \shift_reg_7[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(14)); - - \sample_2[10]\ : DFN1E1 - port map(D => \shift_reg_2[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(10)); - - \shift_reg_6[10]\ : DFN1E1C0 - port map(D => \shift_reg_6[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[10]_net_1\); - - \shift_reg_3[2]\ : DFN1E1C0 - port map(D => \shift_reg_3[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[2]_net_1\); - - \shift_reg_4[12]\ : DFN1E1C0 - port map(D => \shift_reg_4[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[12]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \shift_reg_7[4]\ : DFN1E1C0 - port map(D => \shift_reg_7[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[4]_net_1\); - - \shift_reg_2[13]\ : DFN1E1C0 - port map(D => \shift_reg_2[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[13]_net_1\); - - \sample_6[5]\ : DFN1E1 - port map(D => \shift_reg_6[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(5)); - - \shift_reg_6[14]\ : DFN1E1C0 - port map(D => \shift_reg_6[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[14]_net_1\); - - \cnv_cycle_counter_RNO[6]\ : XA1C - port map(A => \cnv_cycle_counter[6]_net_1\, B => - cnv_cycle_counter_c5, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n6); - - \sample_bit_counter_2[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_2[0]_net_1\); - - \sample_5[2]\ : DFN1E1 - port map(D => \shift_reg_5[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(2)); - - \sample_5[8]\ : DFN1E1 - port map(D => \shift_reg_5[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(8)); - - \sample_1[12]\ : DFN1E1 - port map(D => \shift_reg_1[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(12)); - - \shift_reg_2[6]\ : DFN1E1C0 - port map(D => \shift_reg_2[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[6]_net_1\); - - \shift_reg_0[11]\ : DFN1E1C0 - port map(D => \shift_reg_0[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[11]_net_1\); - - \sample_6[14]\ : DFN1E1 - port map(D => \shift_reg_6[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(14)); - - cnv_s_RNO_0 : OA1C - port map(A => \cnv_cycle_counter[6]_net_1\, B => - un3_cnv_runlt6, C => un3_cnv_runlto8_0, Y => un3_cnv_run); - - \shift_reg_4[8]\ : DFN1E1C0 - port map(D => \shift_reg_4[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[8]_net_1\); - - cnv_s_RNO_1 : AOI1 - port map(A => cnv_cycle_counter_c2, B => - \cnv_cycle_counter[3]_net_1\, C => un3_cnv_runlto5_0, Y - => un3_cnv_runlt6); - - \cnv_cycle_counter[2]\ : DFN1C0 - port map(D => cnv_cycle_counter_n2, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[2]_net_1\); - - \sample_7[7]\ : DFN1E1 - port map(D => \shift_reg_7[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(7)); - - \sample_3[5]\ : DFN1E1 - port map(D => \shift_reg_3[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(5)); - - \shift_reg_7[1]\ : DFN1E1C0 - port map(D => \shift_reg_7[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[1]_net_1\); - - \sample_7[3]\ : DFN1E1 - port map(D => \shift_reg_7[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(3)); - - \sample_3[6]\ : DFN1E1 - port map(D => \shift_reg_3[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(6)); - - \cnv_cycle_counter_RNO[5]\ : XA1B - port map(A => \cnv_cycle_counter[5]_net_1\, B => - cnv_cycle_counter_c4, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n5); - - \shift_reg_5[9]\ : DFN1E1C0 - port map(D => \shift_reg_5[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[9]_net_1\); - - \shift_reg_4[6]\ : DFN1E1C0 - port map(D => \shift_reg_4[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[6]_net_1\); - - \shift_reg_1[4]\ : DFN1E1C0 - port map(D => \shift_reg_1[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[4]_net_1\); - - \cnv_cycle_counter_RNIPQN7[5]\ : NOR2B - port map(A => \cnv_cycle_counter[5]_net_1\, B => - \cnv_cycle_counter[6]_net_1\, Y => un2_cnv_runlto8_1); - - \shift_reg_4[5]\ : DFN1E1C0 - port map(D => \shift_reg_4[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[5]_net_1\); - - \sample_2[1]\ : DFN1E1 - port map(D => \shift_reg_2[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(1)); - - \sample_1[15]\ : DFN1E1 - port map(D => \shift_reg_1[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(15)); - - sck : DFN1P0 - port map(D => \sample_bit_counter_i[0]\, CLK => HCLK_c, PRE - => HRESETn_c, Q => sck_c); - - \shift_reg_6[8]\ : DFN1E1C0 - port map(D => \shift_reg_6[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[8]_net_1\); - - \shift_reg_5[4]\ : DFN1E1C0 - port map(D => \shift_reg_5[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[4]_net_1\); - - \cnv_cycle_counter_RNO[4]\ : NOR2 - port map(A => cnv_s_0_sqmuxa, B => - cnv_cycle_counter_n4_tz_i, Y => cnv_cycle_counter_n4); - - \sample_bit_counter_RNO[2]\ : XA1B - port map(A => N_20, B => \sample_bit_counter[2]_net_1\, C - => N_36, Y => N_13); - - \sample_5[6]\ : DFN1E1 - port map(D => \shift_reg_5[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(6)); - - \sample_bit_counter_4[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_4[0]_net_1\); - - \shift_reg_0[6]\ : DFN1E1C0 - port map(D => \shift_reg_0[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[6]_net_1\); - - \sample_1[3]\ : DFN1E1 - port map(D => \shift_reg_1[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(3)); - - \cnv_cycle_counter_RNIONJB[1]\ : NOR3C - port map(A => \cnv_cycle_counter[0]_net_1\, B => - \cnv_cycle_counter[1]_net_1\, C => - \cnv_cycle_counter[2]_net_1\, Y => cnv_cycle_counter_c2); - - \shift_reg_5[3]\ : DFN1E1C0 - port map(D => \shift_reg_5[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[3]_net_1\); - - \sample_3[2]\ : DFN1E1 - port map(D => \shift_reg_3[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(2)); - - \sample_5[3]\ : DFN1E1 - port map(D => \shift_reg_5[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(3)); - - \shift_reg_1[11]\ : DFN1E1C0 - port map(D => \shift_reg_1[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[11]_net_1\); - - \sample_bit_counter_RNO[5]\ : NOR2 - port map(A => N_36, B => N_23, Y => N_19); - - \cnv_cycle_counter[5]\ : DFN1C0 - port map(D => cnv_cycle_counter_n5, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[5]_net_1\); - - \sample_1[7]\ : DFN1E1 - port map(D => \shift_reg_1[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(7)); - - \sample_1[13]\ : DFN1E1 - port map(D => \shift_reg_1[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(13)); - - sck_RNO : INV - port map(A => \sample_bit_counter_0[0]_net_1\, Y => - \sample_bit_counter_i[0]\); - - \shift_reg_5[2]\ : DFN1E1C0 - port map(D => \shift_reg_5[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[2]_net_1\); - - \sample_bit_counter_RNO[1]\ : NOR3 - port map(A => N_38, B => N_36, C => N_20, Y => N_11); - - \sample_6[8]\ : DFN1E1 - port map(D => \shift_reg_6[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(8)); - - \sample_1[2]\ : DFN1E1 - port map(D => \shift_reg_1[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(2)); - - \sample_bit_counter_RNI6L45[4]\ : OR2B - port map(A => \sample_bit_counter[4]_net_1\, B => N_22, Y - => N_23); - - \cnv_cycle_counter_RNIKD3R[2]\ : OR3C - port map(A => un2_cnv_runlto8_1, B => un2_cnv_runlto8_0, C - => un2_cnv_runlto8_2, Y => un2_cnv_run); - - \sample_0[8]\ : DFN1E1 - port map(D => \shift_reg_0[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(8)); - - \sample_0[14]\ : DFN1E1 - port map(D => \shift_reg_0[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(14)); - - \sample_5[12]\ : DFN1E1 - port map(D => \shift_reg_5[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(12)); - - \shift_reg_0[9]\ : DFN1E1C0 - port map(D => \shift_reg_0[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[9]_net_1\); - - \sample_bit_counter_RNIVMI9[5]\ : NOR2B - port map(A => \sample_bit_counter_RNI0D96[5]_net_1\, B => - HRESETn_c, Y => \sample_bit_counter_RNIVMI9[5]_net_1\); - - \sample_1[11]\ : DFN1E1 - port map(D => \shift_reg_1[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(11)); - - \shift_reg_5[7]\ : DFN1E1C0 - port map(D => \shift_reg_5[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[7]_net_1\); - - \sample_0[6]\ : DFN1E1 - port map(D => \shift_reg_0[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(6)); - - \shift_reg_2[10]\ : DFN1E1C0 - port map(D => \shift_reg_2[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[10]_net_1\); - - \shift_reg_5[12]\ : DFN1E1C0 - port map(D => \shift_reg_5[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_5[12]_net_1\); - - \shift_reg_3[13]\ : DFN1E1C0 - port map(D => \shift_reg_3[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[13]_net_1\); - - cnv_done : DFN1P0 - port map(D => cnv_done_1, CLK => HCLK_c, PRE => HRESETn_c, - Q => cnv_done_i); - - \shift_reg_2[1]\ : DFN1E1C0 - port map(D => \shift_reg_2[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[1]_net_1\); - - \sample_7[4]\ : DFN1E1 - port map(D => \shift_reg_7[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(4)); - - \sample_4[6]\ : DFN1E1 - port map(D => \shift_reg_4[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(6)); - - \shift_reg_1[2]\ : DFN1E1C0 - port map(D => \shift_reg_1[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[2]_net_1\); - - cnv_s_RNO_3 : OR2 - port map(A => \cnv_cycle_counter[4]_net_1\, B => - \cnv_cycle_counter[5]_net_1\, Y => un3_cnv_runlto5_0); - - \shift_reg_7[13]\ : DFN1E1C0 - port map(D => \shift_reg_7[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[13]_net_1\); - - \shift_reg_2[14]\ : DFN1E1C0 - port map(D => \shift_reg_2[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[14]_net_1\); - - \cnv_cycle_counter_RNIDIBJ[4]\ : NOR3C - port map(A => \cnv_cycle_counter[3]_net_1\, B => - cnv_cycle_counter_c2, C => \cnv_cycle_counter[4]_net_1\, - Y => cnv_cycle_counter_c4); - - \shift_reg_6[5]\ : DFN1E1C0 - port map(D => \shift_reg_6[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[5]_net_1\); - - \sample_4[8]\ : DFN1E1 - port map(D => \shift_reg_4[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(8)); - - \sample_5[15]\ : DFN1E1 - port map(D => \shift_reg_5[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(15)); - - \shift_reg_2[3]\ : DFN1E1C0 - port map(D => \shift_reg_2[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[3]_net_1\); - - cnv_s_RNO : OA1A - port map(A => un2_cnv_run, B => un3_cnv_run, C => cnv_run_c, - Y => \cnv_s_RNO\); - - \shift_reg_6[0]\ : DFN1E1C0 - port map(D => sdo_c(6), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[0]_net_1\); - - \cnv_cycle_counter[0]\ : DFN1C0 - port map(D => cnv_cycle_counter_n0, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[0]_net_1\); - - \shift_reg_2[7]\ : DFN1E1C0 - port map(D => \shift_reg_2[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[7]_net_1\); - - \shift_reg_6[4]\ : DFN1E1C0 - port map(D => \shift_reg_6[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[4]_net_1\); - - \shift_reg_2[4]\ : DFN1E1C0 - port map(D => \shift_reg_2[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[4]_net_1\); - - \sample_6[9]\ : DFN1E1 - port map(D => \shift_reg_6[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(9)); - - \shift_reg_4[4]\ : DFN1E1C0 - port map(D => \shift_reg_4[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[4]_net_1\); - - \sample_7[12]\ : DFN1E1 - port map(D => \shift_reg_7[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(12)); - - \cnv_cycle_counter_RNIPF7N[5]\ : OR2B - port map(A => cnv_cycle_counter_c4, B => - \cnv_cycle_counter[5]_net_1\, Y => cnv_cycle_counter_c5); - - \shift_reg_4[3]\ : DFN1E1C0 - port map(D => \shift_reg_4[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[3]_net_1\); - - \shift_reg_4[11]\ : DFN1E1C0 - port map(D => \shift_reg_4[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[11]_net_1\); - - \sample_bit_counter[3]\ : DFN1E0C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[3]_net_1\); - - \cnv_cycle_counter_RNI1OJB[2]\ : OA1 - port map(A => \cnv_cycle_counter[2]_net_1\, B => - \cnv_cycle_counter[3]_net_1\, C => - \cnv_cycle_counter[7]_net_1\, Y => un2_cnv_runlto8_2); - - \sample_5[13]\ : DFN1E1 - port map(D => \shift_reg_5[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(13)); - - \shift_reg_0[7]\ : DFN1E1C0 - port map(D => \shift_reg_0[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[7]_net_1\); - - cnv_s_RNO_2 : OR2 - port map(A => \cnv_cycle_counter[8]_net_1\, B => - \cnv_cycle_counter[7]_net_1\, Y => un3_cnv_runlto8_0); - - \shift_reg_0[13]\ : DFN1E1C0 - port map(D => \shift_reg_0[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[13]_net_1\); - - \sample_2[2]\ : DFN1E1 - port map(D => \shift_reg_2[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(2)); - - \sample_1[8]\ : DFN1E1 - port map(D => \shift_reg_1[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(8)); - - \sample_1[5]\ : DFN1E1 - port map(D => \shift_reg_1[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(5)); - - \sample_6[12]\ : DFN1E1 - port map(D => \shift_reg_6[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(12)); - - \cnv_cycle_counter_RNO[7]\ : XA1B - port map(A => \cnv_cycle_counter[7]_net_1\, B => - cnv_cycle_counter_c6, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n7); - - \sample_7[15]\ : DFN1E1 - port map(D => \shift_reg_7[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(15)); - - \sample_4[0]\ : DFN1E1 - port map(D => sdo_c(4), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(0)); - - \shift_reg_5[0]\ : DFN1E1C0 - port map(D => sdo_c(5), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[0]_net_1\); - - \sample_3[3]\ : DFN1E1 - port map(D => \shift_reg_3[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(3)); - - \sample_5[11]\ : DFN1E1 - port map(D => \shift_reg_5[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(11)); - - \shift_reg_4[7]\ : DFN1E1C0 - port map(D => \shift_reg_4[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[7]_net_1\); - - \shift_reg_6[6]\ : DFN1E1C0 - port map(D => \shift_reg_6[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[6]_net_1\); - - \sample_4[4]\ : DFN1E1 - port map(D => \shift_reg_4[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(4)); - - \sample_6[15]\ : DFN1E1 - port map(D => \shift_reg_6[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(15)); - - \shift_reg_3[10]\ : DFN1E1C0 - port map(D => \shift_reg_3[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[10]_net_1\); - - \sample_1[10]\ : DFN1E1 - port map(D => \shift_reg_1[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(10)); - - \sample_3[14]\ : DFN1E1 - port map(D => \shift_reg_3[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(14)); - - \sample_7[13]\ : DFN1E1 - port map(D => \shift_reg_7[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(13)); - - \shift_reg_7[9]\ : DFN1E1C0 - port map(D => \shift_reg_7[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[9]_net_1\); - - \sample_1[4]\ : DFN1E1 - port map(D => \shift_reg_1[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(4)); - - \cnv_cycle_counter_RNO_0[3]\ : XNOR2 - port map(A => cnv_cycle_counter_c2, B => - \cnv_cycle_counter[3]_net_1\, Y => - cnv_cycle_counter_n3_tz_i); - - \cnv_cycle_counter[1]\ : DFN1C0 - port map(D => cnv_cycle_counter_n1, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[1]_net_1\); - - \shift_reg_7[10]\ : DFN1E1C0 - port map(D => \shift_reg_7[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[10]_net_1\); - - \sample_4[14]\ : DFN1E1 - port map(D => \shift_reg_4[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(14)); - - \shift_reg_6[7]\ : DFN1E1C0 - port map(D => \shift_reg_6[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[7]_net_1\); - - \shift_reg_3[14]\ : DFN1E1C0 - port map(D => \shift_reg_3[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[14]_net_1\); - - \shift_reg_1[13]\ : DFN1E1C0 - port map(D => \shift_reg_1[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[13]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_lfr_wf_picker_ip is - - port( nb_snapshot_param : in std_logic_vector(10 downto 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - hwdata_c : out std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - haddr_c : out std_logic_vector(31 downto 0); - AHB_Master_In_c_3 : in std_logic; - AHB_Master_In_c_0 : in std_logic; - AHB_Master_In_c_4 : in std_logic; - AHB_Master_In_c_5 : in std_logic; - hsize_c : out std_logic_vector(1 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0); - sdo_c : in std_logic_vector(7 downto 0); - coarse_time_0_c : in std_logic; - enable_f0 : in std_logic; - data_shaping_R0 : in std_logic; - data_shaping_R0_0 : in std_logic; - burst_f0 : in std_logic; - data_shaping_R1 : in std_logic; - data_shaping_R1_0 : in std_logic; - enable_f1 : in std_logic; - burst_f1 : in std_logic; - enable_f2 : in std_logic; - burst_f2 : in std_logic; - enable_f3 : in std_logic; - N_43 : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - hwrite_c : out std_logic; - lpp_top_lfr_wf_picker_ip_GND : in std_logic; - lpp_top_lfr_wf_picker_ip_VCC : in std_logic; - cnv_run_c : in std_logic; - sck_c : out std_logic; - cnv_c : out std_logic; - cnv_clk_c : in std_logic; - cnv_rstn_c : in std_logic; - data_shaping_SP0 : in std_logic; - data_shaping_SP1 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_top_lfr_wf_picker_ip; - -architecture DEF_ARCH of lpp_top_lfr_wf_picker_ip is - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2 - port( sample_filter_v2_out_0 : out std_logic; - sample_filter_v2_out_1 : out std_logic; - sample_filter_v2_out_2 : out std_logic; - sample_filter_v2_out_3 : out std_logic; - sample_filter_v2_out_4 : out std_logic; - sample_filter_v2_out_5 : out std_logic; - sample_filter_v2_out_6 : out std_logic; - sample_filter_v2_out_7 : out std_logic; - sample_filter_v2_out_8 : out std_logic; - sample_filter_v2_out_9 : out std_logic; - sample_filter_v2_out_10 : out std_logic; - sample_filter_v2_out_11 : out std_logic; - sample_filter_v2_out_12 : out std_logic; - sample_filter_v2_out_13 : out std_logic; - sample_filter_v2_out_14 : out std_logic; - sample_filter_v2_out_15 : out std_logic; - sample_filter_v2_out_18 : out std_logic; - sample_filter_v2_out_19 : out std_logic; - sample_filter_v2_out_20 : out std_logic; - sample_filter_v2_out_21 : out std_logic; - sample_filter_v2_out_22 : out std_logic; - sample_filter_v2_out_23 : out std_logic; - sample_filter_v2_out_24 : out std_logic; - sample_filter_v2_out_25 : out std_logic; - sample_filter_v2_out_26 : out std_logic; - sample_filter_v2_out_27 : out std_logic; - sample_filter_v2_out_28 : out std_logic; - sample_filter_v2_out_29 : out std_logic; - sample_filter_v2_out_30 : out std_logic; - sample_filter_v2_out_31 : out std_logic; - sample_filter_v2_out_32 : out std_logic; - sample_filter_v2_out_33 : out std_logic; - sample_filter_v2_out_36 : out std_logic; - sample_filter_v2_out_37 : out std_logic; - sample_filter_v2_out_38 : out std_logic; - sample_filter_v2_out_39 : out std_logic; - sample_filter_v2_out_40 : out std_logic; - sample_filter_v2_out_41 : out std_logic; - sample_filter_v2_out_42 : out std_logic; - sample_filter_v2_out_43 : out std_logic; - sample_filter_v2_out_44 : out std_logic; - sample_filter_v2_out_45 : out std_logic; - sample_filter_v2_out_46 : out std_logic; - sample_filter_v2_out_47 : out std_logic; - sample_filter_v2_out_48 : out std_logic; - sample_filter_v2_out_49 : out std_logic; - sample_filter_v2_out_50 : out std_logic; - sample_filter_v2_out_51 : out std_logic; - sample_filter_v2_out_54 : out std_logic; - sample_filter_v2_out_55 : out std_logic; - sample_filter_v2_out_56 : out std_logic; - sample_filter_v2_out_57 : out std_logic; - sample_filter_v2_out_58 : out std_logic; - sample_filter_v2_out_59 : out std_logic; - sample_filter_v2_out_60 : out std_logic; - sample_filter_v2_out_61 : out std_logic; - sample_filter_v2_out_62 : out std_logic; - sample_filter_v2_out_63 : out std_logic; - sample_filter_v2_out_64 : out std_logic; - sample_filter_v2_out_65 : out std_logic; - sample_filter_v2_out_66 : out std_logic; - sample_filter_v2_out_67 : out std_logic; - sample_filter_v2_out_68 : out std_logic; - sample_filter_v2_out_69 : out std_logic; - sample_filter_v2_out_90 : out std_logic; - sample_filter_v2_out_91 : out std_logic; - sample_filter_v2_out_92 : out std_logic; - sample_filter_v2_out_93 : out std_logic; - sample_filter_v2_out_94 : out std_logic; - sample_filter_v2_out_95 : out std_logic; - sample_filter_v2_out_96 : out std_logic; - sample_filter_v2_out_97 : out std_logic; - sample_filter_v2_out_98 : out std_logic; - sample_filter_v2_out_99 : out std_logic; - sample_filter_v2_out_100 : out std_logic; - sample_filter_v2_out_101 : out std_logic; - sample_filter_v2_out_102 : out std_logic; - sample_filter_v2_out_103 : out std_logic; - sample_filter_v2_out_104 : out std_logic; - sample_filter_v2_out_105 : out std_logic; - sample_filter_v2_out_108 : out std_logic; - sample_filter_v2_out_126 : out std_logic; - sample_filter_v2_out_109 : out std_logic; - sample_filter_v2_out_127 : out std_logic; - sample_filter_v2_out_110 : out std_logic; - sample_filter_v2_out_128 : out std_logic; - sample_filter_v2_out_111 : out std_logic; - sample_filter_v2_out_129 : out std_logic; - sample_filter_v2_out_112 : out std_logic; - sample_filter_v2_out_130 : out std_logic; - sample_filter_v2_out_113 : out std_logic; - sample_filter_v2_out_131 : out std_logic; - sample_filter_v2_out_114 : out std_logic; - sample_filter_v2_out_132 : out std_logic; - sample_filter_v2_out_115 : out std_logic; - sample_filter_v2_out_133 : out std_logic; - sample_filter_v2_out_116 : out std_logic; - sample_filter_v2_out_134 : out std_logic; - sample_filter_v2_out_117 : out std_logic; - sample_filter_v2_out_135 : out std_logic; - sample_filter_v2_out_118 : out std_logic; - sample_filter_v2_out_136 : out std_logic; - sample_filter_v2_out_119 : out std_logic; - sample_filter_v2_out_137 : out std_logic; - sample_filter_v2_out_120 : out std_logic; - sample_filter_v2_out_138 : out std_logic; - sample_filter_v2_out_121 : out std_logic; - sample_filter_v2_out_139 : out std_logic; - sample_filter_v2_out_122 : out std_logic; - sample_filter_v2_out_140 : out std_logic; - sample_filter_v2_out_123 : out std_logic; - sample_filter_v2_out_141 : out std_logic; - sample_6 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_5 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_2 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_1 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_3 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_4 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_7 : in std_logic_vector(15 downto 0) := (others => 'U'); - IIR_CEL_CTRLR_v2_VCC : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_GND : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_filter_v2_out_val : out std_logic; - sample_val_delay : in std_logic := 'U' - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component Downsampling_6_16_256 - port( sample_f1 : in std_logic_vector(111 downto 80) := (others => 'U'); - sample_f1_wdata_95 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - sample_f3_wdata : out std_logic_vector(95 downto 0); - sample_f1_val : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f3_val : out std_logic; - HRESETn_c : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component Downsampling_6_16_96 - port( sample_f0 : in std_logic_vector(111 downto 80) := (others => 'U'); - sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f2_wdata : out std_logic_vector(95 downto 0); - sample_f0_val : in std_logic := 'U'; - sample_f0_val_1 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f2_val : out std_logic; - sample_f0_val_0 : in std_logic := 'U'; - sample_out_0_sqmuxa_1 : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform - port( status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - hburst_c : out std_logic_vector(2 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hsize_c : out std_logic_vector(1 downto 0); - AHB_Master_In_c_5 : in std_logic := 'U'; - AHB_Master_In_c_4 : in std_logic := 'U'; - AHB_Master_In_c_0 : in std_logic := 'U'; - AHB_Master_In_c_3 : in std_logic := 'U'; - haddr_c : out std_logic_vector(31 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(3 downto 0); - status_full : out std_logic_vector(3 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata_c : out std_logic_vector(31 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - sample_f3_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - sample_f2_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - sample_f1_15 : in std_logic := 'U'; - sample_f1_47 : in std_logic := 'U'; - sample_f1_14 : in std_logic := 'U'; - sample_f1_46 : in std_logic := 'U'; - sample_f1_13 : in std_logic := 'U'; - sample_f1_45 : in std_logic := 'U'; - sample_f1_12 : in std_logic := 'U'; - sample_f1_44 : in std_logic := 'U'; - sample_f1_60 : in std_logic := 'U'; - sample_f1_59 : in std_logic := 'U'; - sample_f1_58 : in std_logic := 'U'; - sample_f1_57 : in std_logic := 'U'; - sample_f1_56 : in std_logic := 'U'; - sample_f1_55 : in std_logic := 'U'; - sample_f1_54 : in std_logic := 'U'; - sample_f1_53 : in std_logic := 'U'; - sample_f1_52 : in std_logic := 'U'; - sample_f1_51 : in std_logic := 'U'; - sample_f1_50 : in std_logic := 'U'; - sample_f1_49 : in std_logic := 'U'; - sample_f1_48 : in std_logic := 'U'; - sample_f1_4 : in std_logic := 'U'; - sample_f1_36 : in std_logic := 'U'; - sample_f1_3 : in std_logic := 'U'; - sample_f1_35 : in std_logic := 'U'; - sample_f1_2 : in std_logic := 'U'; - sample_f1_34 : in std_logic := 'U'; - sample_f1_1 : in std_logic := 'U'; - sample_f1_33 : in std_logic := 'U'; - sample_f1_0 : in std_logic := 'U'; - sample_f1_32 : in std_logic := 'U'; - sample_f1_63 : in std_logic := 'U'; - sample_f1_62 : in std_logic := 'U'; - sample_f1_61 : in std_logic := 'U'; - sample_f1_11 : in std_logic := 'U'; - sample_f1_43 : in std_logic := 'U'; - sample_f1_10 : in std_logic := 'U'; - sample_f1_42 : in std_logic := 'U'; - sample_f1_9 : in std_logic := 'U'; - sample_f1_41 : in std_logic := 'U'; - sample_f1_8 : in std_logic := 'U'; - sample_f1_40 : in std_logic := 'U'; - sample_f1_7 : in std_logic := 'U'; - sample_f1_39 : in std_logic := 'U'; - sample_f1_6 : in std_logic := 'U'; - sample_f1_38 : in std_logic := 'U'; - sample_f1_5 : in std_logic := 'U'; - sample_f1_37 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_95 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_0 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_37 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_95 : in std_logic := 'U'; - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - hwrite_c : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - N_43 : out std_logic; - lpp_waveform_GND : in std_logic := 'U'; - lpp_waveform_VCC : in std_logic := 'U'; - sample_f3_val : in std_logic := 'U'; - enable_f3 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - data_shaping_R0 : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - coarse_time_0_c : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U' - ); - end component; - - component Downsampling_8_16_4 - port( sample_f0_0 : out std_logic; - sample_f0_1 : out std_logic; - sample_f0_2 : out std_logic; - sample_f0_3 : out std_logic; - sample_f0_4 : out std_logic; - sample_f0_5 : out std_logic; - sample_f0_6 : out std_logic; - sample_f0_7 : out std_logic; - sample_f0_8 : out std_logic; - sample_f0_9 : out std_logic; - sample_f0_10 : out std_logic; - sample_f0_11 : out std_logic; - sample_f0_12 : out std_logic; - sample_f0_13 : out std_logic; - sample_f0_14 : out std_logic; - sample_f0_15 : out std_logic; - sample_f0_32 : out std_logic; - sample_f0_33 : out std_logic; - sample_f0_34 : out std_logic; - sample_f0_35 : out std_logic; - sample_f0_36 : out std_logic; - sample_f0_37 : out std_logic; - sample_f0_38 : out std_logic; - sample_f0_39 : out std_logic; - sample_f0_40 : out std_logic; - sample_f0_41 : out std_logic; - sample_f0_42 : out std_logic; - sample_f0_43 : out std_logic; - sample_f0_44 : out std_logic; - sample_f0_45 : out std_logic; - sample_f0_46 : out std_logic; - sample_f0_47 : out std_logic; - sample_f0_48 : out std_logic; - sample_f0_49 : out std_logic; - sample_f0_50 : out std_logic; - sample_f0_51 : out std_logic; - sample_f0_52 : out std_logic; - sample_f0_53 : out std_logic; - sample_f0_54 : out std_logic; - sample_f0_55 : out std_logic; - sample_f0_56 : out std_logic; - sample_f0_57 : out std_logic; - sample_f0_58 : out std_logic; - sample_f0_59 : out std_logic; - sample_f0_60 : out std_logic; - sample_f0_61 : out std_logic; - sample_f0_62 : out std_logic; - sample_f0_63 : out std_logic; - sample_data_shaping_out_0 : in std_logic := 'U'; - sample_data_shaping_out_1 : in std_logic := 'U'; - sample_data_shaping_out_2 : in std_logic := 'U'; - sample_data_shaping_out_3 : in std_logic := 'U'; - sample_data_shaping_out_4 : in std_logic := 'U'; - sample_data_shaping_out_5 : in std_logic := 'U'; - sample_data_shaping_out_6 : in std_logic := 'U'; - sample_data_shaping_out_7 : in std_logic := 'U'; - sample_data_shaping_out_8 : in std_logic := 'U'; - sample_data_shaping_out_9 : in std_logic := 'U'; - sample_data_shaping_out_10 : in std_logic := 'U'; - sample_data_shaping_out_11 : in std_logic := 'U'; - sample_data_shaping_out_12 : in std_logic := 'U'; - sample_data_shaping_out_13 : in std_logic := 'U'; - sample_data_shaping_out_14 : in std_logic := 'U'; - sample_data_shaping_out_15 : in std_logic := 'U'; - sample_data_shaping_out_18 : in std_logic := 'U'; - sample_data_shaping_out_19 : in std_logic := 'U'; - sample_data_shaping_out_20 : in std_logic := 'U'; - sample_data_shaping_out_21 : in std_logic := 'U'; - sample_data_shaping_out_22 : in std_logic := 'U'; - sample_data_shaping_out_23 : in std_logic := 'U'; - sample_data_shaping_out_24 : in std_logic := 'U'; - sample_data_shaping_out_25 : in std_logic := 'U'; - sample_data_shaping_out_26 : in std_logic := 'U'; - sample_data_shaping_out_27 : in std_logic := 'U'; - sample_data_shaping_out_28 : in std_logic := 'U'; - sample_data_shaping_out_29 : in std_logic := 'U'; - sample_data_shaping_out_30 : in std_logic := 'U'; - sample_data_shaping_out_31 : in std_logic := 'U'; - sample_data_shaping_out_32 : in std_logic := 'U'; - sample_data_shaping_out_33 : in std_logic := 'U'; - sample_data_shaping_out_36 : in std_logic := 'U'; - sample_data_shaping_out_37 : in std_logic := 'U'; - sample_data_shaping_out_38 : in std_logic := 'U'; - sample_data_shaping_out_39 : in std_logic := 'U'; - sample_data_shaping_out_40 : in std_logic := 'U'; - sample_data_shaping_out_41 : in std_logic := 'U'; - sample_data_shaping_out_42 : in std_logic := 'U'; - sample_data_shaping_out_43 : in std_logic := 'U'; - sample_data_shaping_out_44 : in std_logic := 'U'; - sample_data_shaping_out_45 : in std_logic := 'U'; - sample_data_shaping_out_46 : in std_logic := 'U'; - sample_data_shaping_out_47 : in std_logic := 'U'; - sample_data_shaping_out_48 : in std_logic := 'U'; - sample_data_shaping_out_49 : in std_logic := 'U'; - sample_data_shaping_out_50 : in std_logic := 'U'; - sample_data_shaping_out_51 : in std_logic := 'U'; - sample_data_shaping_out_54 : in std_logic := 'U'; - sample_data_shaping_out_55 : in std_logic := 'U'; - sample_data_shaping_out_56 : in std_logic := 'U'; - sample_data_shaping_out_57 : in std_logic := 'U'; - sample_data_shaping_out_58 : in std_logic := 'U'; - sample_data_shaping_out_59 : in std_logic := 'U'; - sample_data_shaping_out_60 : in std_logic := 'U'; - sample_data_shaping_out_61 : in std_logic := 'U'; - sample_data_shaping_out_62 : in std_logic := 'U'; - sample_data_shaping_out_63 : in std_logic := 'U'; - sample_data_shaping_out_64 : in std_logic := 'U'; - sample_data_shaping_out_65 : in std_logic := 'U'; - sample_data_shaping_out_66 : in std_logic := 'U'; - sample_data_shaping_out_67 : in std_logic := 'U'; - sample_data_shaping_out_68 : in std_logic := 'U'; - sample_data_shaping_out_69 : in std_logic := 'U'; - sample_data_shaping_out_90 : in std_logic := 'U'; - sample_data_shaping_out_91 : in std_logic := 'U'; - sample_data_shaping_out_92 : in std_logic := 'U'; - sample_data_shaping_out_93 : in std_logic := 'U'; - sample_data_shaping_out_94 : in std_logic := 'U'; - sample_data_shaping_out_95 : in std_logic := 'U'; - sample_data_shaping_out_96 : in std_logic := 'U'; - sample_data_shaping_out_97 : in std_logic := 'U'; - sample_data_shaping_out_98 : in std_logic := 'U'; - sample_data_shaping_out_99 : in std_logic := 'U'; - sample_data_shaping_out_100 : in std_logic := 'U'; - sample_data_shaping_out_101 : in std_logic := 'U'; - sample_data_shaping_out_102 : in std_logic := 'U'; - sample_data_shaping_out_103 : in std_logic := 'U'; - sample_data_shaping_out_104 : in std_logic := 'U'; - sample_data_shaping_out_105 : in std_logic := 'U'; - sample_data_shaping_out_108 : in std_logic := 'U'; - sample_data_shaping_out_109 : in std_logic := 'U'; - sample_data_shaping_out_110 : in std_logic := 'U'; - sample_data_shaping_out_111 : in std_logic := 'U'; - sample_data_shaping_out_112 : in std_logic := 'U'; - sample_data_shaping_out_113 : in std_logic := 'U'; - sample_data_shaping_out_114 : in std_logic := 'U'; - sample_data_shaping_out_115 : in std_logic := 'U'; - sample_data_shaping_out_116 : in std_logic := 'U'; - sample_data_shaping_out_117 : in std_logic := 'U'; - sample_data_shaping_out_118 : in std_logic := 'U'; - sample_data_shaping_out_119 : in std_logic := 'U'; - sample_data_shaping_out_120 : in std_logic := 'U'; - sample_data_shaping_out_121 : in std_logic := 'U'; - sample_data_shaping_out_122 : in std_logic := 'U'; - sample_data_shaping_out_123 : in std_logic := 'U'; - sample_data_shaping_out_126 : in std_logic := 'U'; - sample_data_shaping_out_127 : in std_logic := 'U'; - sample_data_shaping_out_128 : in std_logic := 'U'; - sample_data_shaping_out_129 : in std_logic := 'U'; - sample_data_shaping_out_130 : in std_logic := 'U'; - sample_data_shaping_out_131 : in std_logic := 'U'; - sample_data_shaping_out_132 : in std_logic := 'U'; - sample_data_shaping_out_133 : in std_logic := 'U'; - sample_data_shaping_out_134 : in std_logic := 'U'; - sample_data_shaping_out_135 : in std_logic := 'U'; - sample_data_shaping_out_136 : in std_logic := 'U'; - sample_data_shaping_out_137 : in std_logic := 'U'; - sample_data_shaping_out_138 : in std_logic := 'U'; - sample_data_shaping_out_139 : in std_logic := 'U'; - sample_data_shaping_out_140 : in std_logic := 'U'; - sample_data_shaping_out_141 : in std_logic := 'U'; - sample_f0_wdata_95 : out std_logic; - sample_f0_wdata_94 : out std_logic; - sample_f0_wdata_93 : out std_logic; - sample_f0_wdata_92 : out std_logic; - sample_f0_wdata_91 : out std_logic; - sample_f0_wdata_90 : out std_logic; - sample_f0_wdata_89 : out std_logic; - sample_f0_wdata_88 : out std_logic; - sample_f0_wdata_87 : out std_logic; - sample_f0_wdata_86 : out std_logic; - sample_f0_wdata_85 : out std_logic; - sample_f0_wdata_84 : out std_logic; - sample_f0_wdata_83 : out std_logic; - sample_f0_wdata_82 : out std_logic; - sample_f0_wdata_81 : out std_logic; - sample_f0_wdata_80 : out std_logic; - sample_f0_wdata_79 : out std_logic; - sample_f0_wdata_78 : out std_logic; - sample_f0_wdata_77 : out std_logic; - sample_f0_wdata_76 : out std_logic; - sample_f0_wdata_75 : out std_logic; - sample_f0_wdata_74 : out std_logic; - sample_f0_wdata_73 : out std_logic; - sample_f0_wdata_72 : out std_logic; - sample_f0_wdata_71 : out std_logic; - sample_f0_wdata_70 : out std_logic; - sample_f0_wdata_69 : out std_logic; - sample_f0_wdata_68 : out std_logic; - sample_f0_wdata_67 : out std_logic; - sample_f0_wdata_66 : out std_logic; - sample_f0_wdata_65 : out std_logic; - sample_f0_wdata_64 : out std_logic; - sample_f0_wdata_63 : out std_logic; - sample_f0_wdata_62 : out std_logic; - sample_f0_wdata_61 : out std_logic; - sample_f0_wdata_60 : out std_logic; - sample_f0_wdata_59 : out std_logic; - sample_f0_wdata_58 : out std_logic; - sample_f0_wdata_57 : out std_logic; - sample_f0_wdata_56 : out std_logic; - sample_f0_wdata_55 : out std_logic; - sample_f0_wdata_54 : out std_logic; - sample_f0_wdata_53 : out std_logic; - sample_f0_wdata_52 : out std_logic; - sample_f0_wdata_51 : out std_logic; - sample_f0_wdata_50 : out std_logic; - sample_f0_wdata_49 : out std_logic; - sample_f0_wdata_48 : out std_logic; - sample_f0_wdata_15 : out std_logic; - sample_f0_wdata_14 : out std_logic; - sample_f0_wdata_13 : out std_logic; - sample_f0_wdata_12 : out std_logic; - sample_f0_wdata_11 : out std_logic; - sample_f0_wdata_10 : out std_logic; - sample_f0_wdata_9 : out std_logic; - sample_f0_wdata_8 : out std_logic; - sample_f0_wdata_7 : out std_logic; - sample_f0_wdata_6 : out std_logic; - sample_f0_wdata_5 : out std_logic; - sample_f0_wdata_4 : out std_logic; - sample_f0_wdata_3 : out std_logic; - sample_f0_wdata_2 : out std_logic; - sample_f0_wdata_1 : out std_logic; - sample_f0_wdata_0 : out std_logic; - sample_data_shaping_out_val : in std_logic := 'U'; - sample_f0_val : out std_logic; - sample_data_shaping_out_val_0 : in std_logic := 'U'; - sample_f0_val_0 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f0_val_1 : out std_logic - ); - end component; - - component Downsampling_8_16_6 - port( sample_f0_0 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_37 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f1_0 : out std_logic; - sample_f1_1 : out std_logic; - sample_f1_2 : out std_logic; - sample_f1_3 : out std_logic; - sample_f1_4 : out std_logic; - sample_f1_5 : out std_logic; - sample_f1_6 : out std_logic; - sample_f1_7 : out std_logic; - sample_f1_8 : out std_logic; - sample_f1_9 : out std_logic; - sample_f1_10 : out std_logic; - sample_f1_11 : out std_logic; - sample_f1_12 : out std_logic; - sample_f1_13 : out std_logic; - sample_f1_14 : out std_logic; - sample_f1_15 : out std_logic; - sample_f1_32 : out std_logic; - sample_f1_33 : out std_logic; - sample_f1_34 : out std_logic; - sample_f1_35 : out std_logic; - sample_f1_36 : out std_logic; - sample_f1_37 : out std_logic; - sample_f1_38 : out std_logic; - sample_f1_39 : out std_logic; - sample_f1_40 : out std_logic; - sample_f1_41 : out std_logic; - sample_f1_42 : out std_logic; - sample_f1_43 : out std_logic; - sample_f1_44 : out std_logic; - sample_f1_45 : out std_logic; - sample_f1_46 : out std_logic; - sample_f1_47 : out std_logic; - sample_f1_48 : out std_logic; - sample_f1_49 : out std_logic; - sample_f1_50 : out std_logic; - sample_f1_51 : out std_logic; - sample_f1_52 : out std_logic; - sample_f1_53 : out std_logic; - sample_f1_54 : out std_logic; - sample_f1_55 : out std_logic; - sample_f1_56 : out std_logic; - sample_f1_57 : out std_logic; - sample_f1_58 : out std_logic; - sample_f1_59 : out std_logic; - sample_f1_60 : out std_logic; - sample_f1_61 : out std_logic; - sample_f1_62 : out std_logic; - sample_f1_63 : out std_logic; - sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f1_wdata_95 : out std_logic; - sample_f1_wdata_94 : out std_logic; - sample_f1_wdata_93 : out std_logic; - sample_f1_wdata_92 : out std_logic; - sample_f1_wdata_91 : out std_logic; - sample_f1_wdata_90 : out std_logic; - sample_f1_wdata_89 : out std_logic; - sample_f1_wdata_88 : out std_logic; - sample_f1_wdata_87 : out std_logic; - sample_f1_wdata_86 : out std_logic; - sample_f1_wdata_85 : out std_logic; - sample_f1_wdata_84 : out std_logic; - sample_f1_wdata_83 : out std_logic; - sample_f1_wdata_82 : out std_logic; - sample_f1_wdata_81 : out std_logic; - sample_f1_wdata_80 : out std_logic; - sample_f1_wdata_79 : out std_logic; - sample_f1_wdata_78 : out std_logic; - sample_f1_wdata_77 : out std_logic; - sample_f1_wdata_76 : out std_logic; - sample_f1_wdata_75 : out std_logic; - sample_f1_wdata_74 : out std_logic; - sample_f1_wdata_73 : out std_logic; - sample_f1_wdata_72 : out std_logic; - sample_f1_wdata_71 : out std_logic; - sample_f1_wdata_70 : out std_logic; - sample_f1_wdata_69 : out std_logic; - sample_f1_wdata_68 : out std_logic; - sample_f1_wdata_67 : out std_logic; - sample_f1_wdata_66 : out std_logic; - sample_f1_wdata_65 : out std_logic; - sample_f1_wdata_64 : out std_logic; - sample_f1_wdata_63 : out std_logic; - sample_f1_wdata_62 : out std_logic; - sample_f1_wdata_61 : out std_logic; - sample_f1_wdata_60 : out std_logic; - sample_f1_wdata_59 : out std_logic; - sample_f1_wdata_58 : out std_logic; - sample_f1_wdata_57 : out std_logic; - sample_f1_wdata_56 : out std_logic; - sample_f1_wdata_55 : out std_logic; - sample_f1_wdata_54 : out std_logic; - sample_f1_wdata_53 : out std_logic; - sample_f1_wdata_52 : out std_logic; - sample_f1_wdata_51 : out std_logic; - sample_f1_wdata_50 : out std_logic; - sample_f1_wdata_49 : out std_logic; - sample_f1_wdata_48 : out std_logic; - sample_f1_wdata_15 : out std_logic; - sample_f1_wdata_14 : out std_logic; - sample_f1_wdata_13 : out std_logic; - sample_f1_wdata_12 : out std_logic; - sample_f1_wdata_11 : out std_logic; - sample_f1_wdata_10 : out std_logic; - sample_f1_wdata_9 : out std_logic; - sample_f1_wdata_8 : out std_logic; - sample_f1_wdata_7 : out std_logic; - sample_f1_wdata_6 : out std_logic; - sample_f1_wdata_5 : out std_logic; - sample_f1_wdata_4 : out std_logic; - sample_f1_wdata_3 : out std_logic; - sample_f1_wdata_2 : out std_logic; - sample_f1_wdata_1 : out std_logic; - sample_f1_wdata_0 : out std_logic; - sample_f0_val_1 : in std_logic := 'U'; - sample_f1_val : out std_logic; - sample_f0_val_0 : in std_logic := 'U'; - sample_out_0_sqmuxa_1 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f1_val_0 : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AD7688_drvr - port( sample_7 : out std_logic_vector(15 downto 0); - sample_0 : out std_logic_vector(15 downto 0); - sample_1 : out std_logic_vector(15 downto 0); - sample_2 : out std_logic_vector(15 downto 0); - sample_3 : out std_logic_vector(15 downto 0); - sample_4 : out std_logic_vector(15 downto 0); - sample_5 : out std_logic_vector(15 downto 0); - sdo_c : in std_logic_vector(7 downto 0) := (others => 'U'); - sample_6 : out std_logic_vector(15 downto 0); - cnv_rstn_c : in std_logic := 'U'; - cnv_clk_c : in std_logic := 'U'; - cnv_c : out std_logic; - sample_val : out std_logic; - sck_c : out std_logic; - cnv_run_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \sample_data_shaping_out_val_0\, - sample_filter_v2_out_val, \sample_val_delay\, - sample_val_delay_0, SUB_16x16_medium_area_I57_Y_2, N244, - N229, SUB_16x16_medium_area_I57_Y_1, N254, N212, - SUB_16x16_medium_area_I57_Y_0, N206, - \sample_filter_v2_out[111]\, \sample_filter_v2_out[93]\, - SUB_16x16_medium_area_I57_Y_2_0, N244_0, N229_0, - SUB_16x16_medium_area_I57_Y_1_0, N212_0, N254_0, - SUB_16x16_medium_area_I57_Y_0_0, N206_0, - \sample_filter_v2_out[129]\, - SUB_16x16_medium_area_I57_un1_Y_0, N245, - SUB_16x16_medium_area_I57_un1_Y_0_0, N245_0, - SUB_16x16_medium_area_I56_Y_1, N274, N220, - SUB_16x16_medium_area_I56_Y_0, N190, - \sample_filter_v2_out[119]\, \sample_filter_v2_out[101]\, - SUB_16x16_medium_area_I56_Y_1_0, N274_0, N220_0, - SUB_16x16_medium_area_I56_Y_0_0, N190_0, - \sample_filter_v2_out[137]\, - SUB_16x16_medium_area_I56_un1_Y_0, N275, - SUB_16x16_medium_area_I49_Y_0, N198, - \sample_filter_v2_out[115]\, \sample_filter_v2_out[97]\, - SUB_16x16_medium_area_I49_Y_0_0, N198_0, - \sample_filter_v2_out[133]\, - SUB_16x16_medium_area_I53_Y_0, N182, - \sample_filter_v2_out[123]\, \sample_filter_v2_out[105]\, - SUB_16x16_medium_area_I53_Y_0_0, N182_0, - \sample_filter_v2_out[141]\, - SUB_16x16_medium_area_I53_un1_Y_0, N225, N264, N216, N240, - N268, I53_un1_Y, N225_0, N183, N181, N278, N264_0, N216_0, - N240_0, N268_0, I56_un1_Y, N275_0, N278_0, - \sample_data_shaping_f2_f1_s[15]\, - \sample_filter_v2_out[110]\, \sample_filter_v2_out[92]\, - \sample_data_shaping_f1_f0_s[15]\, - \sample_filter_v2_out[128]\, N181_0, N194, - \sample_filter_v2_out[118]\, \sample_filter_v2_out[136]\, - \sample_filter_v2_out[116]\, \sample_filter_v2_out[134]\, - N202, \sample_filter_v2_out[114]\, - \sample_filter_v2_out[132]\, \sample_filter_v2_out[112]\, - \sample_filter_v2_out[130]\, N205, - \sample_filter_v2_out[131]\, \sample_filter_v2_out[113]\, - N255, N201, N197, N265, N195, N258, N260, N270, N282_i, - N284_i, N286_i, \sample_data_shaping_f1_f0_s[7]\, - \sample_data_shaping_f1_f0_s[9]\, - \sample_data_shaping_f1_f0_s[10]\, - \sample_data_shaping_f1_f0_s[11]\, - \sample_data_shaping_f1_f0_s[12]\, - \sample_data_shaping_f1_f0_s[13]\, - \sample_data_shaping_f1_f0_s_i[14]\, N186, - \sample_filter_v2_out[122]\, \sample_filter_v2_out[140]\, - \sample_filter_v2_out[120]\, \sample_filter_v2_out[138]\, - N191, N189, \sample_filter_v2_out[121]\, - \sample_filter_v2_out[139]\, N187, N185, I85_un1_Y, - I90_un1_Y, SUB_16x16_medium_area_I91_un1_Y, - \sample_data_shaping_f1_f0_s[3]\, - \sample_data_shaping_f1_f0_s[4]\, - \sample_data_shaping_f1_f0_s[5]\, - \sample_data_shaping_f1_f0_s[6]\, N194_0, - \sample_filter_v2_out[100]\, \sample_filter_v2_out[98]\, - N202_0, \sample_filter_v2_out[96]\, - \sample_filter_v2_out[94]\, N207, N205_0, - \sample_filter_v2_out[95]\, N255_0, N203, N201_0, N199, - N197_0, \sample_filter_v2_out[99]\, - \sample_filter_v2_out[117]\, N265_0, N195_0, N193, - I64_un1_Y, I71_un1_Y, I78_un1_Y, I86_un1_Y, - SUB_16x16_medium_area_I87_un1_Y, I88_un1_Y, - SUB_16x16_medium_area_I89_un1_Y, - \sample_data_shaping_f2_f1_s[7]\, - \sample_data_shaping_f2_f1_s[8]\, - \sample_data_shaping_f2_f1_s[9]\, - \sample_data_shaping_f2_f1_s[10]\, - \sample_data_shaping_f2_f1_s[11]\, - \sample_data_shaping_f2_f1_s[12]\, - \sample_data_shaping_f2_f1_s[13]\, - \sample_data_shaping_f2_f1_s[14]\, N186_0, - \sample_filter_v2_out[104]\, \sample_filter_v2_out[102]\, - N189_0, \sample_filter_v2_out[103]\, N187_0, N280, N290_i, - SUB_16x16_medium_area_I91_un1_Y_0, - \sample_data_shaping_f2_f1_s[3]\, - \sample_data_shaping_f2_f1_s[4]\, - \sample_data_shaping_f2_f1_s[5]\, - \sample_data_shaping_f2_f1_s[6]\, - \sample_data_shaping_out_377[92]\, - \sample_data_shaping_out_353[93]\, - \sample_data_shaping_out_329[94]\, - \sample_data_shaping_out_305[95]\, - \sample_data_shaping_out_281[96]\, - \sample_data_shaping_out_257[97]\, - \sample_data_shaping_out_233[98]\, - \sample_data_shaping_out_209[99]\, - \sample_data_shaping_out_185[100]\, - \sample_data_shaping_out_161[101]\, - \sample_data_shaping_out_137[102]\, - \sample_data_shaping_out_113[103]\, - \sample_data_shaping_out_89[104]\, - \sample_data_shaping_out_373[110]\, - \sample_data_shaping_out_349[111]\, - \sample_data_shaping_out_325[112]\, - \sample_data_shaping_out_301[113]\, - \sample_data_shaping_out_277[114]\, - \sample_data_shaping_out_253[115]\, - \sample_data_shaping_out_229[116]\, - \sample_data_shaping_out_181[118]\, - \sample_data_shaping_out_157[119]\, - \sample_data_shaping_out_133[120]\, - \sample_data_shaping_out_109[121]\, - \sample_data_shaping_out_85[122]\, - \sample_filter_v2_out[143]\, \sample_filter_v2_out[125]\, - \sample_filter_v2_out[107]\, - \sample_data_shaping_out_17[107]\, - \sample_data_shaping_out_13[125]\, - \sample_data_shaping_out_37[124]\, - \sample_filter_v2_out[124]\, - \sample_data_shaping_f1_f0_s[1]\, - \sample_data_shaping_out_61[123]\, - \sample_data_shaping_f1_f0_s[2]\, - \sample_data_shaping_out_205[117]\, - \sample_data_shaping_f1_f0_s[8]\, - \sample_data_shaping_out_41[106]\, - \sample_filter_v2_out[106]\, - \sample_data_shaping_f2_f1_s[1]\, - \sample_data_shaping_out_65[105]\, - \sample_data_shaping_f2_f1_s[2]\, N294_i, I92_un1_Y, - \sample_filter_v2_out[142]\, \sample_filter_v2_out[135]\, - N288_i, sample_val, \sample_data_shaping_out_val\, - \sample_data_shaping_out[20]\, \sample_filter_v2_out[20]\, - \sample_data_shaping_out[21]\, \sample_filter_v2_out[21]\, - \sample_data_shaping_out[22]\, \sample_filter_v2_out[22]\, - \sample_data_shaping_out[23]\, \sample_filter_v2_out[23]\, - \sample_data_shaping_out[24]\, \sample_filter_v2_out[24]\, - \sample_data_shaping_out[25]\, \sample_filter_v2_out[25]\, - \sample_data_shaping_out[26]\, \sample_filter_v2_out[26]\, - \sample_data_shaping_out[27]\, \sample_filter_v2_out[27]\, - \sample_data_shaping_out[28]\, \sample_filter_v2_out[28]\, - \sample_data_shaping_out[29]\, \sample_filter_v2_out[29]\, - \sample_data_shaping_out[30]\, \sample_filter_v2_out[30]\, - \sample_data_shaping_out[31]\, \sample_filter_v2_out[31]\, - \sample_data_shaping_out[32]\, \sample_filter_v2_out[32]\, - \sample_data_shaping_out[33]\, \sample_filter_v2_out[33]\, - \sample_data_shaping_out[34]\, \sample_filter_v2_out[34]\, - \sample_data_shaping_out[35]\, \sample_filter_v2_out[35]\, - \sample_data_shaping_out[38]\, \sample_filter_v2_out[38]\, - \sample_data_shaping_out[39]\, \sample_filter_v2_out[39]\, - \sample_data_shaping_out[40]\, \sample_filter_v2_out[40]\, - \sample_data_shaping_out[41]\, \sample_filter_v2_out[41]\, - \sample_data_shaping_out[42]\, \sample_filter_v2_out[42]\, - \sample_data_shaping_out[43]\, \sample_filter_v2_out[43]\, - \sample_data_shaping_out[44]\, \sample_filter_v2_out[44]\, - \sample_data_shaping_out[45]\, \sample_filter_v2_out[45]\, - \sample_data_shaping_out[46]\, \sample_filter_v2_out[46]\, - \sample_data_shaping_out[47]\, \sample_filter_v2_out[47]\, - \sample_data_shaping_out[48]\, \sample_filter_v2_out[48]\, - \sample_data_shaping_out[49]\, \sample_filter_v2_out[49]\, - \sample_data_shaping_out[50]\, \sample_filter_v2_out[50]\, - \sample_data_shaping_out[51]\, \sample_filter_v2_out[51]\, - \sample_data_shaping_out[52]\, \sample_filter_v2_out[52]\, - \sample_data_shaping_out[53]\, \sample_filter_v2_out[53]\, - \sample_data_shaping_out[56]\, \sample_filter_v2_out[56]\, - \sample_data_shaping_out[57]\, \sample_filter_v2_out[57]\, - \sample_data_shaping_out[58]\, \sample_filter_v2_out[58]\, - \sample_data_shaping_out[59]\, \sample_filter_v2_out[59]\, - \sample_data_shaping_out[60]\, \sample_filter_v2_out[60]\, - \sample_data_shaping_out[61]\, \sample_filter_v2_out[61]\, - \sample_data_shaping_out[62]\, \sample_filter_v2_out[62]\, - \sample_data_shaping_out[63]\, \sample_filter_v2_out[63]\, - \sample_data_shaping_out[64]\, \sample_filter_v2_out[64]\, - \sample_data_shaping_out[65]\, \sample_filter_v2_out[65]\, - \sample_data_shaping_out[66]\, \sample_filter_v2_out[66]\, - \sample_data_shaping_out[67]\, \sample_filter_v2_out[67]\, - \sample_data_shaping_out[68]\, \sample_filter_v2_out[68]\, - \sample_data_shaping_out[69]\, \sample_filter_v2_out[69]\, - \sample_data_shaping_out[70]\, \sample_filter_v2_out[70]\, - \sample_data_shaping_out[71]\, \sample_filter_v2_out[71]\, - \sample_data_shaping_out[128]\, - \sample_data_shaping_out[129]\, - \sample_data_shaping_out[130]\, - \sample_data_shaping_out[131]\, - \sample_data_shaping_out[132]\, - \sample_data_shaping_out[133]\, - \sample_data_shaping_out[134]\, - \sample_data_shaping_out[135]\, - \sample_data_shaping_out[136]\, - \sample_data_shaping_out[137]\, - \sample_data_shaping_out[138]\, - \sample_data_shaping_out[139]\, - \sample_data_shaping_out[140]\, - \sample_data_shaping_out[141]\, - \sample_data_shaping_out[142]\, - \sample_data_shaping_out[143]\, - \sample_data_shaping_out[2]\, \sample_filter_v2_out[2]\, - \sample_data_shaping_out[3]\, \sample_filter_v2_out[3]\, - \sample_data_shaping_out[4]\, \sample_filter_v2_out[4]\, - \sample_data_shaping_out[5]\, \sample_filter_v2_out[5]\, - \sample_data_shaping_out[6]\, \sample_filter_v2_out[6]\, - \sample_data_shaping_out[7]\, \sample_filter_v2_out[7]\, - \sample_data_shaping_out[8]\, \sample_filter_v2_out[8]\, - \sample_data_shaping_out[9]\, \sample_filter_v2_out[9]\, - \sample_data_shaping_out[10]\, \sample_filter_v2_out[10]\, - \sample_data_shaping_out[11]\, \sample_filter_v2_out[11]\, - \sample_data_shaping_out[12]\, \sample_filter_v2_out[12]\, - \sample_data_shaping_out[13]\, \sample_filter_v2_out[13]\, - \sample_data_shaping_out[14]\, \sample_filter_v2_out[14]\, - \sample_data_shaping_out[15]\, \sample_filter_v2_out[15]\, - \sample_data_shaping_out[16]\, \sample_filter_v2_out[16]\, - \sample_data_shaping_out[17]\, \sample_filter_v2_out[17]\, - \sample_data_shaping_out[92]\, - \sample_data_shaping_out[93]\, - \sample_data_shaping_out[94]\, - \sample_data_shaping_out[95]\, - \sample_data_shaping_out[96]\, - \sample_data_shaping_out[97]\, - \sample_data_shaping_out[98]\, - \sample_data_shaping_out[99]\, - \sample_data_shaping_out[100]\, - \sample_data_shaping_out[101]\, - \sample_data_shaping_out[102]\, - \sample_data_shaping_out[103]\, - \sample_data_shaping_out[104]\, - \sample_data_shaping_out[105]\, - \sample_data_shaping_out[106]\, - \sample_data_shaping_out[107]\, - \sample_data_shaping_out[110]\, - \sample_data_shaping_out[111]\, - \sample_data_shaping_out[112]\, - \sample_data_shaping_out[113]\, - \sample_data_shaping_out[114]\, - \sample_data_shaping_out[115]\, - \sample_data_shaping_out[116]\, - \sample_data_shaping_out[117]\, - \sample_data_shaping_out[118]\, - \sample_data_shaping_out[119]\, - \sample_data_shaping_out[120]\, - \sample_data_shaping_out[121]\, - \sample_data_shaping_out[122]\, - \sample_data_shaping_out[123]\, - \sample_data_shaping_out[124]\, - \sample_data_shaping_out[125]\, \sample_7[0]\, - \sample_7[1]\, \sample_7[2]\, \sample_7[3]\, - \sample_7[4]\, \sample_7[5]\, \sample_7[6]\, - \sample_7[7]\, \sample_7[8]\, \sample_7[9]\, - \sample_7[10]\, \sample_7[11]\, \sample_7[12]\, - \sample_7[13]\, \sample_7[14]\, \sample_7[15]\, - \sample_0[0]\, \sample_0[1]\, \sample_0[2]\, - \sample_0[3]\, \sample_0[4]\, \sample_0[5]\, - \sample_0[6]\, \sample_0[7]\, \sample_0[8]\, - \sample_0[9]\, \sample_0[10]\, \sample_0[11]\, - \sample_0[12]\, \sample_0[13]\, \sample_0[14]\, - \sample_0[15]\, \sample_1[0]\, \sample_1[1]\, - \sample_1[2]\, \sample_1[3]\, \sample_1[4]\, - \sample_1[5]\, \sample_1[6]\, \sample_1[7]\, - \sample_1[8]\, \sample_1[9]\, \sample_1[10]\, - \sample_1[11]\, \sample_1[12]\, \sample_1[13]\, - \sample_1[14]\, \sample_1[15]\, \sample_2[0]\, - \sample_2[1]\, \sample_2[2]\, \sample_2[3]\, - \sample_2[4]\, \sample_2[5]\, \sample_2[6]\, - \sample_2[7]\, \sample_2[8]\, \sample_2[9]\, - \sample_2[10]\, \sample_2[11]\, \sample_2[12]\, - \sample_2[13]\, \sample_2[14]\, \sample_2[15]\, - \sample_3[0]\, \sample_3[1]\, \sample_3[2]\, - \sample_3[3]\, \sample_3[4]\, \sample_3[5]\, - \sample_3[6]\, \sample_3[7]\, \sample_3[8]\, - \sample_3[9]\, \sample_3[10]\, \sample_3[11]\, - \sample_3[12]\, \sample_3[13]\, \sample_3[14]\, - \sample_3[15]\, \sample_4[0]\, \sample_4[1]\, - \sample_4[2]\, \sample_4[3]\, \sample_4[4]\, - \sample_4[5]\, \sample_4[6]\, \sample_4[7]\, - \sample_4[8]\, \sample_4[9]\, \sample_4[10]\, - \sample_4[11]\, \sample_4[12]\, \sample_4[13]\, - \sample_4[14]\, \sample_4[15]\, \sample_5[0]\, - \sample_5[1]\, \sample_5[2]\, \sample_5[3]\, - \sample_5[4]\, \sample_5[5]\, \sample_5[6]\, - \sample_5[7]\, \sample_5[8]\, \sample_5[9]\, - \sample_5[10]\, \sample_5[11]\, \sample_5[12]\, - \sample_5[13]\, \sample_5[14]\, \sample_5[15]\, - \sample_6[0]\, \sample_6[1]\, \sample_6[2]\, - \sample_6[3]\, \sample_6[4]\, \sample_6[5]\, - \sample_6[6]\, \sample_6[7]\, \sample_6[8]\, - \sample_6[9]\, \sample_6[10]\, \sample_6[11]\, - \sample_6[12]\, \sample_6[13]\, \sample_6[14]\, - \sample_6[15]\, \sample_f0[48]\, \sample_f0[49]\, - \sample_f0[50]\, \sample_f0[51]\, \sample_f0[52]\, - \sample_f0[53]\, \sample_f0[54]\, \sample_f0[55]\, - \sample_f0[56]\, \sample_f0[57]\, \sample_f0[58]\, - \sample_f0[59]\, \sample_f0[60]\, \sample_f0[61]\, - \sample_f0[62]\, \sample_f0[63]\, \sample_f0[80]\, - \sample_f0[81]\, \sample_f0[82]\, \sample_f0[83]\, - \sample_f0[84]\, \sample_f0[85]\, \sample_f0[86]\, - \sample_f0[87]\, \sample_f0[88]\, \sample_f0[89]\, - \sample_f0[90]\, \sample_f0[91]\, \sample_f0[92]\, - \sample_f0[93]\, \sample_f0[94]\, \sample_f0[95]\, - \sample_f0[96]\, \sample_f0[97]\, \sample_f0[98]\, - \sample_f0[99]\, \sample_f0[100]\, \sample_f0[101]\, - \sample_f0[102]\, \sample_f0[103]\, \sample_f0[104]\, - \sample_f0[105]\, \sample_f0[106]\, \sample_f0[107]\, - \sample_f0[108]\, \sample_f0[109]\, \sample_f0[110]\, - \sample_f0[111]\, \sample_f0_wdata[95]\, - \sample_f0_wdata[94]\, \sample_f0_wdata[93]\, - \sample_f0_wdata[92]\, \sample_f0_wdata[91]\, - \sample_f0_wdata[90]\, \sample_f0_wdata[89]\, - \sample_f0_wdata[88]\, \sample_f0_wdata[87]\, - \sample_f0_wdata[86]\, \sample_f0_wdata[85]\, - \sample_f0_wdata[84]\, \sample_f0_wdata[83]\, - \sample_f0_wdata[82]\, \sample_f0_wdata[81]\, - \sample_f0_wdata[80]\, \sample_f0_wdata[79]\, - \sample_f0_wdata[78]\, \sample_f0_wdata[77]\, - \sample_f0_wdata[76]\, \sample_f0_wdata[75]\, - \sample_f0_wdata[74]\, \sample_f0_wdata[73]\, - \sample_f0_wdata[72]\, \sample_f0_wdata[71]\, - \sample_f0_wdata[70]\, \sample_f0_wdata[69]\, - \sample_f0_wdata[68]\, \sample_f0_wdata[67]\, - \sample_f0_wdata[66]\, \sample_f0_wdata[65]\, - \sample_f0_wdata[64]\, \sample_f0_wdata[63]\, - \sample_f0_wdata[62]\, \sample_f0_wdata[61]\, - \sample_f0_wdata[60]\, \sample_f0_wdata[59]\, - \sample_f0_wdata[58]\, \sample_f0_wdata[57]\, - \sample_f0_wdata[56]\, \sample_f0_wdata[55]\, - \sample_f0_wdata[54]\, \sample_f0_wdata[53]\, - \sample_f0_wdata[52]\, \sample_f0_wdata[51]\, - \sample_f0_wdata[50]\, \sample_f0_wdata[49]\, - \sample_f0_wdata[48]\, \sample_f0_wdata[15]\, - \sample_f0_wdata[14]\, \sample_f0_wdata[13]\, - \sample_f0_wdata[12]\, \sample_f0_wdata[11]\, - \sample_f0_wdata[10]\, \sample_f0_wdata[9]\, - \sample_f0_wdata[8]\, \sample_f0_wdata[7]\, - \sample_f0_wdata[6]\, \sample_f0_wdata[5]\, - \sample_f0_wdata[4]\, \sample_f0_wdata[3]\, - \sample_f0_wdata[2]\, \sample_f0_wdata[1]\, - \sample_f0_wdata[0]\, sample_f0_val, sample_f0_val_0, - sample_f0_val_1, \sample_f1[48]\, \sample_f1[49]\, - \sample_f1[50]\, \sample_f1[51]\, \sample_f1[52]\, - \sample_f1[53]\, \sample_f1[54]\, \sample_f1[55]\, - \sample_f1[56]\, \sample_f1[57]\, \sample_f1[58]\, - \sample_f1[59]\, \sample_f1[60]\, \sample_f1[61]\, - \sample_f1[62]\, \sample_f1[63]\, \sample_f1[80]\, - \sample_f1[81]\, \sample_f1[82]\, \sample_f1[83]\, - \sample_f1[84]\, \sample_f1[85]\, \sample_f1[86]\, - \sample_f1[87]\, \sample_f1[88]\, \sample_f1[89]\, - \sample_f1[90]\, \sample_f1[91]\, \sample_f1[92]\, - \sample_f1[93]\, \sample_f1[94]\, \sample_f1[95]\, - \sample_f1[96]\, \sample_f1[97]\, \sample_f1[98]\, - \sample_f1[99]\, \sample_f1[100]\, \sample_f1[101]\, - \sample_f1[102]\, \sample_f1[103]\, \sample_f1[104]\, - \sample_f1[105]\, \sample_f1[106]\, \sample_f1[107]\, - \sample_f1[108]\, \sample_f1[109]\, \sample_f1[110]\, - \sample_f1[111]\, \sample_f1_wdata[95]\, - \sample_f1_wdata[94]\, \sample_f1_wdata[93]\, - \sample_f1_wdata[92]\, \sample_f1_wdata[91]\, - \sample_f1_wdata[90]\, \sample_f1_wdata[89]\, - \sample_f1_wdata[88]\, \sample_f1_wdata[87]\, - \sample_f1_wdata[86]\, \sample_f1_wdata[85]\, - \sample_f1_wdata[84]\, \sample_f1_wdata[83]\, - \sample_f1_wdata[82]\, \sample_f1_wdata[81]\, - \sample_f1_wdata[80]\, \sample_f1_wdata[79]\, - \sample_f1_wdata[78]\, \sample_f1_wdata[77]\, - \sample_f1_wdata[76]\, \sample_f1_wdata[75]\, - \sample_f1_wdata[74]\, \sample_f1_wdata[73]\, - \sample_f1_wdata[72]\, \sample_f1_wdata[71]\, - \sample_f1_wdata[70]\, \sample_f1_wdata[69]\, - \sample_f1_wdata[68]\, \sample_f1_wdata[67]\, - \sample_f1_wdata[66]\, \sample_f1_wdata[65]\, - \sample_f1_wdata[64]\, \sample_f1_wdata[63]\, - \sample_f1_wdata[62]\, \sample_f1_wdata[61]\, - \sample_f1_wdata[60]\, \sample_f1_wdata[59]\, - \sample_f1_wdata[58]\, \sample_f1_wdata[57]\, - \sample_f1_wdata[56]\, \sample_f1_wdata[55]\, - \sample_f1_wdata[54]\, \sample_f1_wdata[53]\, - \sample_f1_wdata[52]\, \sample_f1_wdata[51]\, - \sample_f1_wdata[50]\, \sample_f1_wdata[49]\, - \sample_f1_wdata[48]\, \sample_f1_wdata[15]\, - \sample_f1_wdata[14]\, \sample_f1_wdata[13]\, - \sample_f1_wdata[12]\, \sample_f1_wdata[11]\, - \sample_f1_wdata[10]\, \sample_f1_wdata[9]\, - \sample_f1_wdata[8]\, \sample_f1_wdata[7]\, - \sample_f1_wdata[6]\, \sample_f1_wdata[5]\, - \sample_f1_wdata[4]\, \sample_f1_wdata[3]\, - \sample_f1_wdata[2]\, \sample_f1_wdata[1]\, - \sample_f1_wdata[0]\, sample_f1_val, - sample_out_0_sqmuxa_1, sample_f1_val_0, - \sample_f2_wdata[0]\, \sample_f2_wdata[1]\, - \sample_f2_wdata[2]\, \sample_f2_wdata[3]\, - \sample_f2_wdata[4]\, \sample_f2_wdata[5]\, - \sample_f2_wdata[6]\, \sample_f2_wdata[7]\, - \sample_f2_wdata[8]\, \sample_f2_wdata[9]\, - \sample_f2_wdata[10]\, \sample_f2_wdata[11]\, - \sample_f2_wdata[12]\, \sample_f2_wdata[13]\, - \sample_f2_wdata[14]\, \sample_f2_wdata[15]\, - \sample_f2_wdata[16]\, \sample_f2_wdata[17]\, - \sample_f2_wdata[18]\, \sample_f2_wdata[19]\, - \sample_f2_wdata[20]\, \sample_f2_wdata[21]\, - \sample_f2_wdata[22]\, \sample_f2_wdata[23]\, - \sample_f2_wdata[24]\, \sample_f2_wdata[25]\, - \sample_f2_wdata[26]\, \sample_f2_wdata[27]\, - \sample_f2_wdata[28]\, \sample_f2_wdata[29]\, - \sample_f2_wdata[30]\, \sample_f2_wdata[31]\, - \sample_f2_wdata[32]\, \sample_f2_wdata[33]\, - \sample_f2_wdata[34]\, \sample_f2_wdata[35]\, - \sample_f2_wdata[36]\, \sample_f2_wdata[37]\, - \sample_f2_wdata[38]\, \sample_f2_wdata[39]\, - \sample_f2_wdata[40]\, \sample_f2_wdata[41]\, - \sample_f2_wdata[42]\, \sample_f2_wdata[43]\, - \sample_f2_wdata[44]\, \sample_f2_wdata[45]\, - \sample_f2_wdata[46]\, \sample_f2_wdata[47]\, - \sample_f2_wdata[48]\, \sample_f2_wdata[49]\, - \sample_f2_wdata[50]\, \sample_f2_wdata[51]\, - \sample_f2_wdata[52]\, \sample_f2_wdata[53]\, - \sample_f2_wdata[54]\, \sample_f2_wdata[55]\, - \sample_f2_wdata[56]\, \sample_f2_wdata[57]\, - \sample_f2_wdata[58]\, \sample_f2_wdata[59]\, - \sample_f2_wdata[60]\, \sample_f2_wdata[61]\, - \sample_f2_wdata[62]\, \sample_f2_wdata[63]\, - \sample_f2_wdata[64]\, \sample_f2_wdata[65]\, - \sample_f2_wdata[66]\, \sample_f2_wdata[67]\, - \sample_f2_wdata[68]\, \sample_f2_wdata[69]\, - \sample_f2_wdata[70]\, \sample_f2_wdata[71]\, - \sample_f2_wdata[72]\, \sample_f2_wdata[73]\, - \sample_f2_wdata[74]\, \sample_f2_wdata[75]\, - \sample_f2_wdata[76]\, \sample_f2_wdata[77]\, - \sample_f2_wdata[78]\, \sample_f2_wdata[79]\, - \sample_f2_wdata[80]\, \sample_f2_wdata[81]\, - \sample_f2_wdata[82]\, \sample_f2_wdata[83]\, - \sample_f2_wdata[84]\, \sample_f2_wdata[85]\, - \sample_f2_wdata[86]\, \sample_f2_wdata[87]\, - \sample_f2_wdata[88]\, \sample_f2_wdata[89]\, - \sample_f2_wdata[90]\, \sample_f2_wdata[91]\, - \sample_f2_wdata[92]\, \sample_f2_wdata[93]\, - \sample_f2_wdata[94]\, \sample_f2_wdata[95]\, - sample_f2_val, \sample_f3_wdata[0]\, \sample_f3_wdata[1]\, - \sample_f3_wdata[2]\, \sample_f3_wdata[3]\, - \sample_f3_wdata[4]\, \sample_f3_wdata[5]\, - \sample_f3_wdata[6]\, \sample_f3_wdata[7]\, - \sample_f3_wdata[8]\, \sample_f3_wdata[9]\, - \sample_f3_wdata[10]\, \sample_f3_wdata[11]\, - \sample_f3_wdata[12]\, \sample_f3_wdata[13]\, - \sample_f3_wdata[14]\, \sample_f3_wdata[15]\, - \sample_f3_wdata[16]\, \sample_f3_wdata[17]\, - \sample_f3_wdata[18]\, \sample_f3_wdata[19]\, - \sample_f3_wdata[20]\, \sample_f3_wdata[21]\, - \sample_f3_wdata[22]\, \sample_f3_wdata[23]\, - \sample_f3_wdata[24]\, \sample_f3_wdata[25]\, - \sample_f3_wdata[26]\, \sample_f3_wdata[27]\, - \sample_f3_wdata[28]\, \sample_f3_wdata[29]\, - \sample_f3_wdata[30]\, \sample_f3_wdata[31]\, - \sample_f3_wdata[32]\, \sample_f3_wdata[33]\, - \sample_f3_wdata[34]\, \sample_f3_wdata[35]\, - \sample_f3_wdata[36]\, \sample_f3_wdata[37]\, - \sample_f3_wdata[38]\, \sample_f3_wdata[39]\, - \sample_f3_wdata[40]\, \sample_f3_wdata[41]\, - \sample_f3_wdata[42]\, \sample_f3_wdata[43]\, - \sample_f3_wdata[44]\, \sample_f3_wdata[45]\, - \sample_f3_wdata[46]\, \sample_f3_wdata[47]\, - \sample_f3_wdata[48]\, \sample_f3_wdata[49]\, - \sample_f3_wdata[50]\, \sample_f3_wdata[51]\, - \sample_f3_wdata[52]\, \sample_f3_wdata[53]\, - \sample_f3_wdata[54]\, \sample_f3_wdata[55]\, - \sample_f3_wdata[56]\, \sample_f3_wdata[57]\, - \sample_f3_wdata[58]\, \sample_f3_wdata[59]\, - \sample_f3_wdata[60]\, \sample_f3_wdata[61]\, - \sample_f3_wdata[62]\, \sample_f3_wdata[63]\, - \sample_f3_wdata[64]\, \sample_f3_wdata[65]\, - \sample_f3_wdata[66]\, \sample_f3_wdata[67]\, - \sample_f3_wdata[68]\, \sample_f3_wdata[69]\, - \sample_f3_wdata[70]\, \sample_f3_wdata[71]\, - \sample_f3_wdata[72]\, \sample_f3_wdata[73]\, - \sample_f3_wdata[74]\, \sample_f3_wdata[75]\, - \sample_f3_wdata[76]\, \sample_f3_wdata[77]\, - \sample_f3_wdata[78]\, \sample_f3_wdata[79]\, - \sample_f3_wdata[80]\, \sample_f3_wdata[81]\, - \sample_f3_wdata[82]\, \sample_f3_wdata[83]\, - \sample_f3_wdata[84]\, \sample_f3_wdata[85]\, - \sample_f3_wdata[86]\, \sample_f3_wdata[87]\, - \sample_f3_wdata[88]\, \sample_f3_wdata[89]\, - \sample_f3_wdata[90]\, \sample_f3_wdata[91]\, - \sample_f3_wdata[92]\, \sample_f3_wdata[93]\, - \sample_f3_wdata[94]\, \sample_f3_wdata[95]\, - sample_f3_val, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : IIR_CEL_CTRLR_v2 - Use entity work.IIR_CEL_CTRLR_v2(DEF_ARCH); - for all : Downsampling_6_16_256 - Use entity work.Downsampling_6_16_256(DEF_ARCH); - for all : Downsampling_6_16_96 - Use entity work.Downsampling_6_16_96(DEF_ARCH); - for all : lpp_waveform - Use entity work.lpp_waveform(DEF_ARCH); - for all : Downsampling_8_16_4 - Use entity work.Downsampling_8_16_4(DEF_ARCH); - for all : Downsampling_8_16_6 - Use entity work.Downsampling_8_16_6(DEF_ARCH); - for all : AD7688_drvr - Use entity work.AD7688_drvr(DEF_ARCH); -begin - - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I91_un1_Y : - XA1A - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, C => N278_0, Y => - SUB_16x16_medium_area_I91_un1_Y_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I27_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[96]\, B => - \sample_filter_v2_out[114]\, Y => N202_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[29]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[29]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[29]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[97]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_257[97]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[97]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out_RNO[120]\ : - MX2 - port map(A => \sample_filter_v2_out[120]\, B => - \sample_data_shaping_f1_f0_s[5]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_133[120]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[138]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[138]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[138]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I86_Y : - AO18 - port map(A => N260, B => \sample_filter_v2_out[130]\, C => - \sample_filter_v2_out[112]\, Y => N282_i); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[117]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_205[117]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[117]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[23]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[23]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[23]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out_RNO[103]\ : - MX2 - port map(A => \sample_filter_v2_out[103]\, B => - \sample_data_shaping_f2_f1_s[4]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_113[103]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I106_Y_0 : - AX1D - port map(A => I71_un1_Y, B => N254, C => N205_0, Y => - \sample_data_shaping_f2_f1_s[13]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I100_Y_0 : - XOR2 - port map(A => N268_0, B => N193, Y => - \sample_data_shaping_f2_f1_s[7]\); - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - port map(sample_filter_v2_out_0 => - \sample_filter_v2_out[2]\, sample_filter_v2_out_1 => - \sample_filter_v2_out[3]\, sample_filter_v2_out_2 => - \sample_filter_v2_out[4]\, sample_filter_v2_out_3 => - \sample_filter_v2_out[5]\, sample_filter_v2_out_4 => - \sample_filter_v2_out[6]\, sample_filter_v2_out_5 => - \sample_filter_v2_out[7]\, sample_filter_v2_out_6 => - \sample_filter_v2_out[8]\, sample_filter_v2_out_7 => - \sample_filter_v2_out[9]\, sample_filter_v2_out_8 => - \sample_filter_v2_out[10]\, sample_filter_v2_out_9 => - \sample_filter_v2_out[11]\, sample_filter_v2_out_10 => - \sample_filter_v2_out[12]\, sample_filter_v2_out_11 => - \sample_filter_v2_out[13]\, sample_filter_v2_out_12 => - \sample_filter_v2_out[14]\, sample_filter_v2_out_13 => - \sample_filter_v2_out[15]\, sample_filter_v2_out_14 => - \sample_filter_v2_out[16]\, sample_filter_v2_out_15 => - \sample_filter_v2_out[17]\, sample_filter_v2_out_18 => - \sample_filter_v2_out[20]\, sample_filter_v2_out_19 => - \sample_filter_v2_out[21]\, sample_filter_v2_out_20 => - \sample_filter_v2_out[22]\, sample_filter_v2_out_21 => - \sample_filter_v2_out[23]\, sample_filter_v2_out_22 => - \sample_filter_v2_out[24]\, sample_filter_v2_out_23 => - \sample_filter_v2_out[25]\, sample_filter_v2_out_24 => - \sample_filter_v2_out[26]\, sample_filter_v2_out_25 => - \sample_filter_v2_out[27]\, sample_filter_v2_out_26 => - \sample_filter_v2_out[28]\, sample_filter_v2_out_27 => - \sample_filter_v2_out[29]\, sample_filter_v2_out_28 => - \sample_filter_v2_out[30]\, sample_filter_v2_out_29 => - \sample_filter_v2_out[31]\, sample_filter_v2_out_30 => - \sample_filter_v2_out[32]\, sample_filter_v2_out_31 => - \sample_filter_v2_out[33]\, sample_filter_v2_out_32 => - \sample_filter_v2_out[34]\, sample_filter_v2_out_33 => - \sample_filter_v2_out[35]\, sample_filter_v2_out_36 => - \sample_filter_v2_out[38]\, sample_filter_v2_out_37 => - \sample_filter_v2_out[39]\, sample_filter_v2_out_38 => - \sample_filter_v2_out[40]\, sample_filter_v2_out_39 => - \sample_filter_v2_out[41]\, sample_filter_v2_out_40 => - \sample_filter_v2_out[42]\, sample_filter_v2_out_41 => - \sample_filter_v2_out[43]\, sample_filter_v2_out_42 => - \sample_filter_v2_out[44]\, sample_filter_v2_out_43 => - \sample_filter_v2_out[45]\, sample_filter_v2_out_44 => - \sample_filter_v2_out[46]\, sample_filter_v2_out_45 => - \sample_filter_v2_out[47]\, sample_filter_v2_out_46 => - \sample_filter_v2_out[48]\, sample_filter_v2_out_47 => - \sample_filter_v2_out[49]\, sample_filter_v2_out_48 => - \sample_filter_v2_out[50]\, sample_filter_v2_out_49 => - \sample_filter_v2_out[51]\, sample_filter_v2_out_50 => - \sample_filter_v2_out[52]\, sample_filter_v2_out_51 => - \sample_filter_v2_out[53]\, sample_filter_v2_out_54 => - \sample_filter_v2_out[56]\, sample_filter_v2_out_55 => - \sample_filter_v2_out[57]\, sample_filter_v2_out_56 => - \sample_filter_v2_out[58]\, sample_filter_v2_out_57 => - \sample_filter_v2_out[59]\, sample_filter_v2_out_58 => - \sample_filter_v2_out[60]\, sample_filter_v2_out_59 => - \sample_filter_v2_out[61]\, sample_filter_v2_out_60 => - \sample_filter_v2_out[62]\, sample_filter_v2_out_61 => - \sample_filter_v2_out[63]\, sample_filter_v2_out_62 => - \sample_filter_v2_out[64]\, sample_filter_v2_out_63 => - \sample_filter_v2_out[65]\, sample_filter_v2_out_64 => - \sample_filter_v2_out[66]\, sample_filter_v2_out_65 => - \sample_filter_v2_out[67]\, sample_filter_v2_out_66 => - \sample_filter_v2_out[68]\, sample_filter_v2_out_67 => - \sample_filter_v2_out[69]\, sample_filter_v2_out_68 => - \sample_filter_v2_out[70]\, sample_filter_v2_out_69 => - \sample_filter_v2_out[71]\, sample_filter_v2_out_90 => - \sample_filter_v2_out[92]\, sample_filter_v2_out_91 => - \sample_filter_v2_out[93]\, sample_filter_v2_out_92 => - \sample_filter_v2_out[94]\, sample_filter_v2_out_93 => - \sample_filter_v2_out[95]\, sample_filter_v2_out_94 => - \sample_filter_v2_out[96]\, sample_filter_v2_out_95 => - \sample_filter_v2_out[97]\, sample_filter_v2_out_96 => - \sample_filter_v2_out[98]\, sample_filter_v2_out_97 => - \sample_filter_v2_out[99]\, sample_filter_v2_out_98 => - \sample_filter_v2_out[100]\, sample_filter_v2_out_99 => - \sample_filter_v2_out[101]\, sample_filter_v2_out_100 => - \sample_filter_v2_out[102]\, sample_filter_v2_out_101 => - \sample_filter_v2_out[103]\, sample_filter_v2_out_102 => - \sample_filter_v2_out[104]\, sample_filter_v2_out_103 => - \sample_filter_v2_out[105]\, sample_filter_v2_out_104 => - \sample_filter_v2_out[106]\, sample_filter_v2_out_105 => - \sample_filter_v2_out[107]\, sample_filter_v2_out_108 => - \sample_filter_v2_out[110]\, sample_filter_v2_out_126 => - \sample_filter_v2_out[128]\, sample_filter_v2_out_109 => - \sample_filter_v2_out[111]\, sample_filter_v2_out_127 => - \sample_filter_v2_out[129]\, sample_filter_v2_out_110 => - \sample_filter_v2_out[112]\, sample_filter_v2_out_128 => - \sample_filter_v2_out[130]\, sample_filter_v2_out_111 => - \sample_filter_v2_out[113]\, sample_filter_v2_out_129 => - \sample_filter_v2_out[131]\, sample_filter_v2_out_112 => - \sample_filter_v2_out[114]\, sample_filter_v2_out_130 => - \sample_filter_v2_out[132]\, sample_filter_v2_out_113 => - \sample_filter_v2_out[115]\, sample_filter_v2_out_131 => - \sample_filter_v2_out[133]\, sample_filter_v2_out_114 => - \sample_filter_v2_out[116]\, sample_filter_v2_out_132 => - \sample_filter_v2_out[134]\, sample_filter_v2_out_115 => - \sample_filter_v2_out[117]\, sample_filter_v2_out_133 => - \sample_filter_v2_out[135]\, sample_filter_v2_out_116 => - \sample_filter_v2_out[118]\, sample_filter_v2_out_134 => - \sample_filter_v2_out[136]\, sample_filter_v2_out_117 => - \sample_filter_v2_out[119]\, sample_filter_v2_out_135 => - \sample_filter_v2_out[137]\, sample_filter_v2_out_118 => - \sample_filter_v2_out[120]\, sample_filter_v2_out_136 => - \sample_filter_v2_out[138]\, sample_filter_v2_out_119 => - \sample_filter_v2_out[121]\, sample_filter_v2_out_137 => - \sample_filter_v2_out[139]\, sample_filter_v2_out_120 => - \sample_filter_v2_out[122]\, sample_filter_v2_out_138 => - \sample_filter_v2_out[140]\, sample_filter_v2_out_121 => - \sample_filter_v2_out[123]\, sample_filter_v2_out_139 => - \sample_filter_v2_out[141]\, sample_filter_v2_out_122 => - \sample_filter_v2_out[124]\, sample_filter_v2_out_140 => - \sample_filter_v2_out[142]\, sample_filter_v2_out_123 => - \sample_filter_v2_out[125]\, sample_filter_v2_out_141 => - \sample_filter_v2_out[143]\, sample_6(15) => - \sample_6[15]\, sample_6(14) => \sample_6[14]\, - sample_6(13) => \sample_6[13]\, sample_6(12) => - \sample_6[12]\, sample_6(11) => \sample_6[11]\, - sample_6(10) => \sample_6[10]\, sample_6(9) => - \sample_6[9]\, sample_6(8) => \sample_6[8]\, sample_6(7) - => \sample_6[7]\, sample_6(6) => \sample_6[6]\, - sample_6(5) => \sample_6[5]\, sample_6(4) => - \sample_6[4]\, sample_6(3) => \sample_6[3]\, sample_6(2) - => \sample_6[2]\, sample_6(1) => \sample_6[1]\, - sample_6(0) => \sample_6[0]\, sample_5(15) => - \sample_5[15]\, sample_5(14) => \sample_5[14]\, - sample_5(13) => \sample_5[13]\, sample_5(12) => - \sample_5[12]\, sample_5(11) => \sample_5[11]\, - sample_5(10) => \sample_5[10]\, sample_5(9) => - \sample_5[9]\, sample_5(8) => \sample_5[8]\, sample_5(7) - => \sample_5[7]\, sample_5(6) => \sample_5[6]\, - sample_5(5) => \sample_5[5]\, sample_5(4) => - \sample_5[4]\, sample_5(3) => \sample_5[3]\, sample_5(2) - => \sample_5[2]\, sample_5(1) => \sample_5[1]\, - sample_5(0) => \sample_5[0]\, sample_2(15) => - \sample_2[15]\, sample_2(14) => \sample_2[14]\, - sample_2(13) => \sample_2[13]\, sample_2(12) => - \sample_2[12]\, sample_2(11) => \sample_2[11]\, - sample_2(10) => \sample_2[10]\, sample_2(9) => - \sample_2[9]\, sample_2(8) => \sample_2[8]\, sample_2(7) - => \sample_2[7]\, sample_2(6) => \sample_2[6]\, - sample_2(5) => \sample_2[5]\, sample_2(4) => - \sample_2[4]\, sample_2(3) => \sample_2[3]\, sample_2(2) - => \sample_2[2]\, sample_2(1) => \sample_2[1]\, - sample_2(0) => \sample_2[0]\, sample_0(15) => - \sample_0[15]\, sample_0(14) => \sample_0[14]\, - sample_0(13) => \sample_0[13]\, sample_0(12) => - \sample_0[12]\, sample_0(11) => \sample_0[11]\, - sample_0(10) => \sample_0[10]\, sample_0(9) => - \sample_0[9]\, sample_0(8) => \sample_0[8]\, sample_0(7) - => \sample_0[7]\, sample_0(6) => \sample_0[6]\, - sample_0(5) => \sample_0[5]\, sample_0(4) => - \sample_0[4]\, sample_0(3) => \sample_0[3]\, sample_0(2) - => \sample_0[2]\, sample_0(1) => \sample_0[1]\, - sample_0(0) => \sample_0[0]\, sample_1(15) => - \sample_1[15]\, sample_1(14) => \sample_1[14]\, - sample_1(13) => \sample_1[13]\, sample_1(12) => - \sample_1[12]\, sample_1(11) => \sample_1[11]\, - sample_1(10) => \sample_1[10]\, sample_1(9) => - \sample_1[9]\, sample_1(8) => \sample_1[8]\, sample_1(7) - => \sample_1[7]\, sample_1(6) => \sample_1[6]\, - sample_1(5) => \sample_1[5]\, sample_1(4) => - \sample_1[4]\, sample_1(3) => \sample_1[3]\, sample_1(2) - => \sample_1[2]\, sample_1(1) => \sample_1[1]\, - sample_1(0) => \sample_1[0]\, sample_3(15) => - \sample_3[15]\, sample_3(14) => \sample_3[14]\, - sample_3(13) => \sample_3[13]\, sample_3(12) => - \sample_3[12]\, sample_3(11) => \sample_3[11]\, - sample_3(10) => \sample_3[10]\, sample_3(9) => - \sample_3[9]\, sample_3(8) => \sample_3[8]\, sample_3(7) - => \sample_3[7]\, sample_3(6) => \sample_3[6]\, - sample_3(5) => \sample_3[5]\, sample_3(4) => - \sample_3[4]\, sample_3(3) => \sample_3[3]\, sample_3(2) - => \sample_3[2]\, sample_3(1) => \sample_3[1]\, - sample_3(0) => \sample_3[0]\, sample_4(15) => - \sample_4[15]\, sample_4(14) => \sample_4[14]\, - sample_4(13) => \sample_4[13]\, sample_4(12) => - \sample_4[12]\, sample_4(11) => \sample_4[11]\, - sample_4(10) => \sample_4[10]\, sample_4(9) => - \sample_4[9]\, sample_4(8) => \sample_4[8]\, sample_4(7) - => \sample_4[7]\, sample_4(6) => \sample_4[6]\, - sample_4(5) => \sample_4[5]\, sample_4(4) => - \sample_4[4]\, sample_4(3) => \sample_4[3]\, sample_4(2) - => \sample_4[2]\, sample_4(1) => \sample_4[1]\, - sample_4(0) => \sample_4[0]\, sample_7(15) => - \sample_7[15]\, sample_7(14) => \sample_7[14]\, - sample_7(13) => \sample_7[13]\, sample_7(12) => - \sample_7[12]\, sample_7(11) => \sample_7[11]\, - sample_7(10) => \sample_7[10]\, sample_7(9) => - \sample_7[9]\, sample_7(8) => \sample_7[8]\, sample_7(7) - => \sample_7[7]\, sample_7(6) => \sample_7[6]\, - sample_7(5) => \sample_7[5]\, sample_7(4) => - \sample_7[4]\, sample_7(3) => \sample_7[3]\, sample_7(2) - => \sample_7[2]\, sample_7(1) => \sample_7[1]\, - sample_7(0) => \sample_7[0]\, IIR_CEL_CTRLR_v2_VCC => - lpp_top_lfr_wf_picker_ip_VCC, IIR_CEL_CTRLR_v2_GND => - lpp_top_lfr_wf_picker_ip_GND, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, sample_filter_v2_out_val => - sample_filter_v2_out_val, sample_val_delay => - \sample_val_delay\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I101_Y_0 : - XNOR2 - port map(A => N288_i, B => N195, Y => - \sample_data_shaping_f1_f0_s[8]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[103]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_113[103]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[103]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I22_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[137]\, B => - \sample_filter_v2_out[119]\, Y => N191); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[135]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[135]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[135]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I98_Y_0 : - AX1D - port map(A => I85_un1_Y, B => N274_0, C => N189, Y => - \sample_data_shaping_f1_f0_s[5]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I24_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[135]\, B => - \sample_filter_v2_out[117]\, Y => N195); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[28]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[28]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[28]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out_RNO[110]\ : - MX2 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_data_shaping_f1_f0_s[15]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_373[110]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I108_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_filter_v2_out[128]\, C => N240, Y => - \sample_data_shaping_f1_f0_s[15]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I78_Y : - AO1 - port map(A => N268, B => N265, C => N264, Y => N270); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I71_Y : - AO1C - port map(A => N255, B => N258, C => N254_0, Y => N260); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I49_Y_0 : - AO18 - port map(A => N198_0, B => \sample_filter_v2_out[133]\, C - => \sample_filter_v2_out[115]\, Y => - SUB_16x16_medium_area_I49_Y_0_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I17_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[124]\, B => - \sample_filter_v2_out[106]\, Y => N181_0); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[30]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[30]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[30]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I33_Y : - XAI1A - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[129]\, C => N205, Y => N212_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I17_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[124]\, B => - \sample_filter_v2_out[142]\, Y => N182_0); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I104_Y_0 : - XOR2 - port map(A => N258, B => N201, Y => - \sample_data_shaping_f1_f0_s[11]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[119]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_157[119]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[119]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I49_Y_0 : - AO18 - port map(A => N198, B => \sample_filter_v2_out[115]\, C => - \sample_filter_v2_out[97]\, Y => - SUB_16x16_medium_area_I49_Y_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out_RNO[101]\ : - MX2 - port map(A => \sample_filter_v2_out[101]\, B => - \sample_data_shaping_f2_f1_s[6]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_161[101]\); - - sample_val_delay_RNI8T43 : CLKINT - port map(A => sample_val_delay_0, Y => \sample_val_delay\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I29_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[94]\, B => - \sample_filter_v2_out[112]\, Y => N206); - - \SampleLoop_data_shaping.14.sample_data_shaping_out_RNO[93]\ : - MX2 - port map(A => \sample_filter_v2_out[93]\, B => - \sample_data_shaping_f2_f1_s[14]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_353[93]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[47]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[47]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[47]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[120]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_133[120]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[120]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[13]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[13]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[13]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[32]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[32]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[32]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I21_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[102]\, B => - \sample_filter_v2_out[120]\, Y => N190); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[15]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[15]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[15]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out_RNO[95]\ : - MX2 - port map(A => \sample_filter_v2_out[95]\, B => - \sample_data_shaping_f2_f1_s[12]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_305[95]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[113]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_301[113]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[113]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y_1 : - AOI1B - port map(A => N274_0, B => N220_0, C => - SUB_16x16_medium_area_I56_Y_0_0, Y => - SUB_16x16_medium_area_I56_Y_1_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I20_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[121]\, B => - \sample_filter_v2_out[103]\, Y => N187_0); - - \SampleLoop_data_shaping.2.sample_data_shaping_out_RNO[123]\ : - MX2 - port map(A => \sample_filter_v2_out[123]\, B => - \sample_data_shaping_f1_f0_s[2]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_61[123]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[67]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[67]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[67]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I87_un1_Y : - OA1A - port map(A => I64_un1_Y, B => N244, C => N201_0, Y => - SUB_16x16_medium_area_I87_un1_Y); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I71_un1_Y : - OA1A - port map(A => I64_un1_Y, B => N244, C => N255_0, Y => - I71_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I37_Y : - NOR2B - port map(A => N199, B => N197_0, Y => N216_0); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[104]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_89[104]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[104]\); - - sample_val_delay : DFN1C0 - port map(D => sample_val, CLK => HCLK_c, CLR => HRESETn_c, - Q => sample_val_delay_0); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[35]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[35]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[35]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I48_Y : - NOR2B - port map(A => N255_0, B => N212, Y => N229); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_un1_Y_0 : - NOR2B - port map(A => N229, B => N245, Y => - SUB_16x16_medium_area_I57_un1_Y_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[129]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[129]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[129]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I94_Y_0 : - XOR2 - port map(A => N225_0, B => N181, Y => - \sample_data_shaping_f1_f0_s[1]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[107]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_17[107]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[107]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I28_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[95]\, Y => N203); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I107_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[129]\, C => N282_i, Y => - \sample_data_shaping_f1_f0_s_i[14]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I19_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[140]\, B => - \sample_filter_v2_out[122]\, Y => N185); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[137]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[137]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[137]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[11]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[11]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[11]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[46]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[46]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[46]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[110]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_373[110]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[110]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[61]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[61]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[61]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I102_Y_0 : - XOR2 - port map(A => N270, B => N197, Y => - \sample_data_shaping_f1_f0_s[9]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[68]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[68]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[68]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I42_Y : - AO13 - port map(A => N186_0, B => \sample_filter_v2_out[103]\, C - => \sample_filter_v2_out[121]\, Y => N274); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[57]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[57]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[57]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I107_Y_0 : - AX1D - port map(A => I86_un1_Y, B => N206, C => N207, Y => - \sample_data_shaping_f2_f1_s[14]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_un1_Y_0 : - XA1A - port map(A => \sample_filter_v2_out[105]\, B => - \sample_filter_v2_out[123]\, C => N225, Y => - SUB_16x16_medium_area_I53_un1_Y_0); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[49]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[49]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[49]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out_RNO[104]\ : - MX2 - port map(A => \sample_filter_v2_out[104]\, B => - \sample_data_shaping_f2_f1_s[3]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_89[104]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[17]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[17]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[17]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I92_Y : - AO18 - port map(A => N225, B => \sample_filter_v2_out[124]\, C => - \sample_filter_v2_out[106]\, Y => N294_i); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I105_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[131]\, C => N284_i, Y => - \sample_data_shaping_f1_f0_s[12]\); - - \SampleLoop_data_shaping.9.sample_data_shaping_out_RNO[116]\ : - MX2 - port map(A => \sample_filter_v2_out[116]\, B => - \sample_data_shaping_f1_f0_s[9]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_229[116]\); - - Downsampling_f3 : Downsampling_6_16_256 - port map(sample_f1(111) => \sample_f1[111]\, sample_f1(110) - => \sample_f1[110]\, sample_f1(109) => \sample_f1[109]\, - sample_f1(108) => \sample_f1[108]\, sample_f1(107) => - \sample_f1[107]\, sample_f1(106) => \sample_f1[106]\, - sample_f1(105) => \sample_f1[105]\, sample_f1(104) => - \sample_f1[104]\, sample_f1(103) => \sample_f1[103]\, - sample_f1(102) => \sample_f1[102]\, sample_f1(101) => - \sample_f1[101]\, sample_f1(100) => \sample_f1[100]\, - sample_f1(99) => \sample_f1[99]\, sample_f1(98) => - \sample_f1[98]\, sample_f1(97) => \sample_f1[97]\, - sample_f1(96) => \sample_f1[96]\, sample_f1(95) => - \sample_f1[95]\, sample_f1(94) => \sample_f1[94]\, - sample_f1(93) => \sample_f1[93]\, sample_f1(92) => - \sample_f1[92]\, sample_f1(91) => \sample_f1[91]\, - sample_f1(90) => \sample_f1[90]\, sample_f1(89) => - \sample_f1[89]\, sample_f1(88) => \sample_f1[88]\, - sample_f1(87) => \sample_f1[87]\, sample_f1(86) => - \sample_f1[86]\, sample_f1(85) => \sample_f1[85]\, - sample_f1(84) => \sample_f1[84]\, sample_f1(83) => - \sample_f1[83]\, sample_f1(82) => \sample_f1[82]\, - sample_f1(81) => \sample_f1[81]\, sample_f1(80) => - \sample_f1[80]\, sample_f1_wdata_95 => - \sample_f1_wdata[95]\, sample_f1_wdata_94 => - \sample_f1_wdata[94]\, sample_f1_wdata_93 => - \sample_f1_wdata[93]\, sample_f1_wdata_92 => - \sample_f1_wdata[92]\, sample_f1_wdata_91 => - \sample_f1_wdata[91]\, sample_f1_wdata_90 => - \sample_f1_wdata[90]\, sample_f1_wdata_89 => - \sample_f1_wdata[89]\, sample_f1_wdata_88 => - \sample_f1_wdata[88]\, sample_f1_wdata_87 => - \sample_f1_wdata[87]\, sample_f1_wdata_86 => - \sample_f1_wdata[86]\, sample_f1_wdata_85 => - \sample_f1_wdata[85]\, sample_f1_wdata_84 => - \sample_f1_wdata[84]\, sample_f1_wdata_83 => - \sample_f1_wdata[83]\, sample_f1_wdata_82 => - \sample_f1_wdata[82]\, sample_f1_wdata_81 => - \sample_f1_wdata[81]\, sample_f1_wdata_80 => - \sample_f1_wdata[80]\, sample_f1_wdata_79 => - \sample_f1_wdata[79]\, sample_f1_wdata_78 => - \sample_f1_wdata[78]\, sample_f1_wdata_77 => - \sample_f1_wdata[77]\, sample_f1_wdata_76 => - \sample_f1_wdata[76]\, sample_f1_wdata_75 => - \sample_f1_wdata[75]\, sample_f1_wdata_74 => - \sample_f1_wdata[74]\, sample_f1_wdata_73 => - \sample_f1_wdata[73]\, sample_f1_wdata_72 => - \sample_f1_wdata[72]\, sample_f1_wdata_71 => - \sample_f1_wdata[71]\, sample_f1_wdata_70 => - \sample_f1_wdata[70]\, sample_f1_wdata_69 => - \sample_f1_wdata[69]\, sample_f1_wdata_68 => - \sample_f1_wdata[68]\, sample_f1_wdata_67 => - \sample_f1_wdata[67]\, sample_f1_wdata_66 => - \sample_f1_wdata[66]\, sample_f1_wdata_65 => - \sample_f1_wdata[65]\, sample_f1_wdata_64 => - \sample_f1_wdata[64]\, sample_f1_wdata_63 => - \sample_f1_wdata[63]\, sample_f1_wdata_62 => - \sample_f1_wdata[62]\, sample_f1_wdata_61 => - \sample_f1_wdata[61]\, sample_f1_wdata_60 => - \sample_f1_wdata[60]\, sample_f1_wdata_59 => - \sample_f1_wdata[59]\, sample_f1_wdata_58 => - \sample_f1_wdata[58]\, sample_f1_wdata_57 => - \sample_f1_wdata[57]\, sample_f1_wdata_56 => - \sample_f1_wdata[56]\, sample_f1_wdata_55 => - \sample_f1_wdata[55]\, sample_f1_wdata_54 => - \sample_f1_wdata[54]\, sample_f1_wdata_53 => - \sample_f1_wdata[53]\, sample_f1_wdata_52 => - \sample_f1_wdata[52]\, sample_f1_wdata_51 => - \sample_f1_wdata[51]\, sample_f1_wdata_50 => - \sample_f1_wdata[50]\, sample_f1_wdata_49 => - \sample_f1_wdata[49]\, sample_f1_wdata_48 => - \sample_f1_wdata[48]\, sample_f1_wdata_15 => - \sample_f1_wdata[15]\, sample_f1_wdata_14 => - \sample_f1_wdata[14]\, sample_f1_wdata_13 => - \sample_f1_wdata[13]\, sample_f1_wdata_12 => - \sample_f1_wdata[12]\, sample_f1_wdata_11 => - \sample_f1_wdata[11]\, sample_f1_wdata_10 => - \sample_f1_wdata[10]\, sample_f1_wdata_9 => - \sample_f1_wdata[9]\, sample_f1_wdata_8 => - \sample_f1_wdata[8]\, sample_f1_wdata_7 => - \sample_f1_wdata[7]\, sample_f1_wdata_6 => - \sample_f1_wdata[6]\, sample_f1_wdata_5 => - \sample_f1_wdata[5]\, sample_f1_wdata_4 => - \sample_f1_wdata[4]\, sample_f1_wdata_3 => - \sample_f1_wdata[3]\, sample_f1_wdata_2 => - \sample_f1_wdata[2]\, sample_f1_wdata_1 => - \sample_f1_wdata[1]\, sample_f1_wdata_0 => - \sample_f1_wdata[0]\, sample_f3_wdata(95) => - \sample_f3_wdata[95]\, sample_f3_wdata(94) => - \sample_f3_wdata[94]\, sample_f3_wdata(93) => - \sample_f3_wdata[93]\, sample_f3_wdata(92) => - \sample_f3_wdata[92]\, sample_f3_wdata(91) => - \sample_f3_wdata[91]\, sample_f3_wdata(90) => - \sample_f3_wdata[90]\, sample_f3_wdata(89) => - \sample_f3_wdata[89]\, sample_f3_wdata(88) => - \sample_f3_wdata[88]\, sample_f3_wdata(87) => - \sample_f3_wdata[87]\, sample_f3_wdata(86) => - \sample_f3_wdata[86]\, sample_f3_wdata(85) => - \sample_f3_wdata[85]\, sample_f3_wdata(84) => - \sample_f3_wdata[84]\, sample_f3_wdata(83) => - \sample_f3_wdata[83]\, sample_f3_wdata(82) => - \sample_f3_wdata[82]\, sample_f3_wdata(81) => - \sample_f3_wdata[81]\, sample_f3_wdata(80) => - \sample_f3_wdata[80]\, sample_f3_wdata(79) => - \sample_f3_wdata[79]\, sample_f3_wdata(78) => - \sample_f3_wdata[78]\, sample_f3_wdata(77) => - \sample_f3_wdata[77]\, sample_f3_wdata(76) => - \sample_f3_wdata[76]\, sample_f3_wdata(75) => - \sample_f3_wdata[75]\, sample_f3_wdata(74) => - \sample_f3_wdata[74]\, sample_f3_wdata(73) => - \sample_f3_wdata[73]\, sample_f3_wdata(72) => - \sample_f3_wdata[72]\, sample_f3_wdata(71) => - \sample_f3_wdata[71]\, sample_f3_wdata(70) => - \sample_f3_wdata[70]\, sample_f3_wdata(69) => - \sample_f3_wdata[69]\, sample_f3_wdata(68) => - \sample_f3_wdata[68]\, sample_f3_wdata(67) => - \sample_f3_wdata[67]\, sample_f3_wdata(66) => - \sample_f3_wdata[66]\, sample_f3_wdata(65) => - \sample_f3_wdata[65]\, sample_f3_wdata(64) => - \sample_f3_wdata[64]\, sample_f3_wdata(63) => - \sample_f3_wdata[63]\, sample_f3_wdata(62) => - \sample_f3_wdata[62]\, sample_f3_wdata(61) => - \sample_f3_wdata[61]\, sample_f3_wdata(60) => - \sample_f3_wdata[60]\, sample_f3_wdata(59) => - \sample_f3_wdata[59]\, sample_f3_wdata(58) => - \sample_f3_wdata[58]\, sample_f3_wdata(57) => - \sample_f3_wdata[57]\, sample_f3_wdata(56) => - \sample_f3_wdata[56]\, sample_f3_wdata(55) => - \sample_f3_wdata[55]\, sample_f3_wdata(54) => - \sample_f3_wdata[54]\, sample_f3_wdata(53) => - \sample_f3_wdata[53]\, sample_f3_wdata(52) => - \sample_f3_wdata[52]\, sample_f3_wdata(51) => - \sample_f3_wdata[51]\, sample_f3_wdata(50) => - \sample_f3_wdata[50]\, sample_f3_wdata(49) => - \sample_f3_wdata[49]\, sample_f3_wdata(48) => - \sample_f3_wdata[48]\, sample_f3_wdata(47) => - \sample_f3_wdata[47]\, sample_f3_wdata(46) => - \sample_f3_wdata[46]\, sample_f3_wdata(45) => - \sample_f3_wdata[45]\, sample_f3_wdata(44) => - \sample_f3_wdata[44]\, sample_f3_wdata(43) => - \sample_f3_wdata[43]\, sample_f3_wdata(42) => - \sample_f3_wdata[42]\, sample_f3_wdata(41) => - \sample_f3_wdata[41]\, sample_f3_wdata(40) => - \sample_f3_wdata[40]\, sample_f3_wdata(39) => - \sample_f3_wdata[39]\, sample_f3_wdata(38) => - \sample_f3_wdata[38]\, sample_f3_wdata(37) => - \sample_f3_wdata[37]\, sample_f3_wdata(36) => - \sample_f3_wdata[36]\, sample_f3_wdata(35) => - \sample_f3_wdata[35]\, sample_f3_wdata(34) => - \sample_f3_wdata[34]\, sample_f3_wdata(33) => - \sample_f3_wdata[33]\, sample_f3_wdata(32) => - \sample_f3_wdata[32]\, sample_f3_wdata(31) => - \sample_f3_wdata[31]\, sample_f3_wdata(30) => - \sample_f3_wdata[30]\, sample_f3_wdata(29) => - \sample_f3_wdata[29]\, sample_f3_wdata(28) => - \sample_f3_wdata[28]\, sample_f3_wdata(27) => - \sample_f3_wdata[27]\, sample_f3_wdata(26) => - \sample_f3_wdata[26]\, sample_f3_wdata(25) => - \sample_f3_wdata[25]\, sample_f3_wdata(24) => - \sample_f3_wdata[24]\, sample_f3_wdata(23) => - \sample_f3_wdata[23]\, sample_f3_wdata(22) => - \sample_f3_wdata[22]\, sample_f3_wdata(21) => - \sample_f3_wdata[21]\, sample_f3_wdata(20) => - \sample_f3_wdata[20]\, sample_f3_wdata(19) => - \sample_f3_wdata[19]\, sample_f3_wdata(18) => - \sample_f3_wdata[18]\, sample_f3_wdata(17) => - \sample_f3_wdata[17]\, sample_f3_wdata(16) => - \sample_f3_wdata[16]\, sample_f3_wdata(15) => - \sample_f3_wdata[15]\, sample_f3_wdata(14) => - \sample_f3_wdata[14]\, sample_f3_wdata(13) => - \sample_f3_wdata[13]\, sample_f3_wdata(12) => - \sample_f3_wdata[12]\, sample_f3_wdata(11) => - \sample_f3_wdata[11]\, sample_f3_wdata(10) => - \sample_f3_wdata[10]\, sample_f3_wdata(9) => - \sample_f3_wdata[9]\, sample_f3_wdata(8) => - \sample_f3_wdata[8]\, sample_f3_wdata(7) => - \sample_f3_wdata[7]\, sample_f3_wdata(6) => - \sample_f3_wdata[6]\, sample_f3_wdata(5) => - \sample_f3_wdata[5]\, sample_f3_wdata(4) => - \sample_f3_wdata[4]\, sample_f3_wdata(3) => - \sample_f3_wdata[3]\, sample_f3_wdata(2) => - \sample_f3_wdata[2]\, sample_f3_wdata(1) => - \sample_f3_wdata[1]\, sample_f3_wdata(0) => - \sample_f3_wdata[0]\, sample_f1_val => sample_f1_val, - HCLK_c => HCLK_c, sample_f3_val => sample_f3_val, - HRESETn_c => HRESETn_c, sample_f1_val_0 => - sample_f1_val_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I34_Y : - AO18 - port map(A => N202, B => \sample_filter_v2_out[131]\, C => - \sample_filter_v2_out[113]\, Y => N254_0); - - \SampleLoop_data_shaping.10.sample_data_shaping_out_RNO[115]\ : - MX2 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_data_shaping_f1_f0_s[10]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_253[115]\); - - GND_i : GND - port map(Y => \GND\); - - Downsampling_f2 : Downsampling_6_16_96 - port map(sample_f0(111) => \sample_f0[111]\, sample_f0(110) - => \sample_f0[110]\, sample_f0(109) => \sample_f0[109]\, - sample_f0(108) => \sample_f0[108]\, sample_f0(107) => - \sample_f0[107]\, sample_f0(106) => \sample_f0[106]\, - sample_f0(105) => \sample_f0[105]\, sample_f0(104) => - \sample_f0[104]\, sample_f0(103) => \sample_f0[103]\, - sample_f0(102) => \sample_f0[102]\, sample_f0(101) => - \sample_f0[101]\, sample_f0(100) => \sample_f0[100]\, - sample_f0(99) => \sample_f0[99]\, sample_f0(98) => - \sample_f0[98]\, sample_f0(97) => \sample_f0[97]\, - sample_f0(96) => \sample_f0[96]\, sample_f0(95) => - \sample_f0[95]\, sample_f0(94) => \sample_f0[94]\, - sample_f0(93) => \sample_f0[93]\, sample_f0(92) => - \sample_f0[92]\, sample_f0(91) => \sample_f0[91]\, - sample_f0(90) => \sample_f0[90]\, sample_f0(89) => - \sample_f0[89]\, sample_f0(88) => \sample_f0[88]\, - sample_f0(87) => \sample_f0[87]\, sample_f0(86) => - \sample_f0[86]\, sample_f0(85) => \sample_f0[85]\, - sample_f0(84) => \sample_f0[84]\, sample_f0(83) => - \sample_f0[83]\, sample_f0(82) => \sample_f0[82]\, - sample_f0(81) => \sample_f0[81]\, sample_f0(80) => - \sample_f0[80]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_f2_wdata(95) => - \sample_f2_wdata[95]\, sample_f2_wdata(94) => - \sample_f2_wdata[94]\, sample_f2_wdata(93) => - \sample_f2_wdata[93]\, sample_f2_wdata(92) => - \sample_f2_wdata[92]\, sample_f2_wdata(91) => - \sample_f2_wdata[91]\, sample_f2_wdata(90) => - \sample_f2_wdata[90]\, sample_f2_wdata(89) => - \sample_f2_wdata[89]\, sample_f2_wdata(88) => - \sample_f2_wdata[88]\, sample_f2_wdata(87) => - \sample_f2_wdata[87]\, sample_f2_wdata(86) => - \sample_f2_wdata[86]\, sample_f2_wdata(85) => - \sample_f2_wdata[85]\, sample_f2_wdata(84) => - \sample_f2_wdata[84]\, sample_f2_wdata(83) => - \sample_f2_wdata[83]\, sample_f2_wdata(82) => - \sample_f2_wdata[82]\, sample_f2_wdata(81) => - \sample_f2_wdata[81]\, sample_f2_wdata(80) => - \sample_f2_wdata[80]\, sample_f2_wdata(79) => - \sample_f2_wdata[79]\, sample_f2_wdata(78) => - \sample_f2_wdata[78]\, sample_f2_wdata(77) => - \sample_f2_wdata[77]\, sample_f2_wdata(76) => - \sample_f2_wdata[76]\, sample_f2_wdata(75) => - \sample_f2_wdata[75]\, sample_f2_wdata(74) => - \sample_f2_wdata[74]\, sample_f2_wdata(73) => - \sample_f2_wdata[73]\, sample_f2_wdata(72) => - \sample_f2_wdata[72]\, sample_f2_wdata(71) => - \sample_f2_wdata[71]\, sample_f2_wdata(70) => - \sample_f2_wdata[70]\, sample_f2_wdata(69) => - \sample_f2_wdata[69]\, sample_f2_wdata(68) => - \sample_f2_wdata[68]\, sample_f2_wdata(67) => - \sample_f2_wdata[67]\, sample_f2_wdata(66) => - \sample_f2_wdata[66]\, sample_f2_wdata(65) => - \sample_f2_wdata[65]\, sample_f2_wdata(64) => - \sample_f2_wdata[64]\, sample_f2_wdata(63) => - \sample_f2_wdata[63]\, sample_f2_wdata(62) => - \sample_f2_wdata[62]\, sample_f2_wdata(61) => - \sample_f2_wdata[61]\, sample_f2_wdata(60) => - \sample_f2_wdata[60]\, sample_f2_wdata(59) => - \sample_f2_wdata[59]\, sample_f2_wdata(58) => - \sample_f2_wdata[58]\, sample_f2_wdata(57) => - \sample_f2_wdata[57]\, sample_f2_wdata(56) => - \sample_f2_wdata[56]\, sample_f2_wdata(55) => - \sample_f2_wdata[55]\, sample_f2_wdata(54) => - \sample_f2_wdata[54]\, sample_f2_wdata(53) => - \sample_f2_wdata[53]\, sample_f2_wdata(52) => - \sample_f2_wdata[52]\, sample_f2_wdata(51) => - \sample_f2_wdata[51]\, sample_f2_wdata(50) => - \sample_f2_wdata[50]\, sample_f2_wdata(49) => - \sample_f2_wdata[49]\, sample_f2_wdata(48) => - \sample_f2_wdata[48]\, sample_f2_wdata(47) => - \sample_f2_wdata[47]\, sample_f2_wdata(46) => - \sample_f2_wdata[46]\, sample_f2_wdata(45) => - \sample_f2_wdata[45]\, sample_f2_wdata(44) => - \sample_f2_wdata[44]\, sample_f2_wdata(43) => - \sample_f2_wdata[43]\, sample_f2_wdata(42) => - \sample_f2_wdata[42]\, sample_f2_wdata(41) => - \sample_f2_wdata[41]\, sample_f2_wdata(40) => - \sample_f2_wdata[40]\, sample_f2_wdata(39) => - \sample_f2_wdata[39]\, sample_f2_wdata(38) => - \sample_f2_wdata[38]\, sample_f2_wdata(37) => - \sample_f2_wdata[37]\, sample_f2_wdata(36) => - \sample_f2_wdata[36]\, sample_f2_wdata(35) => - \sample_f2_wdata[35]\, sample_f2_wdata(34) => - \sample_f2_wdata[34]\, sample_f2_wdata(33) => - \sample_f2_wdata[33]\, sample_f2_wdata(32) => - \sample_f2_wdata[32]\, sample_f2_wdata(31) => - \sample_f2_wdata[31]\, sample_f2_wdata(30) => - \sample_f2_wdata[30]\, sample_f2_wdata(29) => - \sample_f2_wdata[29]\, sample_f2_wdata(28) => - \sample_f2_wdata[28]\, sample_f2_wdata(27) => - \sample_f2_wdata[27]\, sample_f2_wdata(26) => - \sample_f2_wdata[26]\, sample_f2_wdata(25) => - \sample_f2_wdata[25]\, sample_f2_wdata(24) => - \sample_f2_wdata[24]\, sample_f2_wdata(23) => - \sample_f2_wdata[23]\, sample_f2_wdata(22) => - \sample_f2_wdata[22]\, sample_f2_wdata(21) => - \sample_f2_wdata[21]\, sample_f2_wdata(20) => - \sample_f2_wdata[20]\, sample_f2_wdata(19) => - \sample_f2_wdata[19]\, sample_f2_wdata(18) => - \sample_f2_wdata[18]\, sample_f2_wdata(17) => - \sample_f2_wdata[17]\, sample_f2_wdata(16) => - \sample_f2_wdata[16]\, sample_f2_wdata(15) => - \sample_f2_wdata[15]\, sample_f2_wdata(14) => - \sample_f2_wdata[14]\, sample_f2_wdata(13) => - \sample_f2_wdata[13]\, sample_f2_wdata(12) => - \sample_f2_wdata[12]\, sample_f2_wdata(11) => - \sample_f2_wdata[11]\, sample_f2_wdata(10) => - \sample_f2_wdata[10]\, sample_f2_wdata(9) => - \sample_f2_wdata[9]\, sample_f2_wdata(8) => - \sample_f2_wdata[8]\, sample_f2_wdata(7) => - \sample_f2_wdata[7]\, sample_f2_wdata(6) => - \sample_f2_wdata[6]\, sample_f2_wdata(5) => - \sample_f2_wdata[5]\, sample_f2_wdata(4) => - \sample_f2_wdata[4]\, sample_f2_wdata(3) => - \sample_f2_wdata[3]\, sample_f2_wdata(2) => - \sample_f2_wdata[2]\, sample_f2_wdata(1) => - \sample_f2_wdata[1]\, sample_f2_wdata(0) => - \sample_f2_wdata[0]\, sample_f0_val => sample_f0_val, - sample_f0_val_1 => sample_f0_val_1, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, sample_f2_val => - sample_f2_val, sample_f0_val_0 => sample_f0_val_0, - sample_out_0_sqmuxa_1 => sample_out_0_sqmuxa_1); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I38_Y : - AO13 - port map(A => N194_0, B => \sample_filter_v2_out[99]\, C - => \sample_filter_v2_out[117]\, Y => N264_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I95_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[105]\, B => - \sample_filter_v2_out[123]\, C => N294_i, Y => - \sample_data_shaping_f2_f1_s[2]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[33]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[33]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[33]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_Y : - OR2B - port map(A => SUB_16x16_medium_area_I53_Y_0_0, B => - I53_un1_Y, Y => N278); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y : - AO1B - port map(A => SUB_16x16_medium_area_I56_un1_Y_0, B => N278, - C => SUB_16x16_medium_area_I56_Y_1_0, Y => N268); - - \SampleLoop_data_shaping.14.sample_data_shaping_out_RNO[111]\ : - MX2B - port map(A => \sample_filter_v2_out[111]\, B => - \sample_data_shaping_f1_f0_s_i[14]\, S => - data_shaping_SP0, Y => \sample_data_shaping_out_349[111]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I89_Y : - AO18 - port map(A => N268, B => \sample_filter_v2_out[136]\, C => - \sample_filter_v2_out[118]\, Y => N288_i); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[122]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_85[122]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[122]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[20]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[20]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[20]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_Y : - AO1B - port map(A => SUB_16x16_medium_area_I53_un1_Y_0, B => - N181_0, C => SUB_16x16_medium_area_I53_Y_0, Y => N278_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I87_Y : - AO18 - port map(A => N258, B => \sample_filter_v2_out[132]\, C => - \sample_filter_v2_out[114]\, Y => N284_i); - - \SampleLoop_data_shaping.11.sample_data_shaping_out_RNO[96]\ : - MX2 - port map(A => \sample_filter_v2_out[96]\, B => - \sample_data_shaping_f2_f1_s[11]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_281[96]\); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[3]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[3]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[3]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_un1_Y_0 : - NOR2B - port map(A => N229_0, B => N245_0, Y => - SUB_16x16_medium_area_I57_un1_Y_0_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I43_Y : - NOR2B - port map(A => N187, B => N185, Y => N275); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[58]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[58]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[58]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I46_Y : - OR2A - port map(A => \sample_filter_v2_out[143]\, B => - \sample_filter_v2_out[125]\, Y => N225_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[26]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[26]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[26]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[56]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[56]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[56]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I102_Y_0 : - AX1D - port map(A => I78_un1_Y, B => N264_0, C => N197_0, Y => - \sample_data_shaping_f2_f1_s[9]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I21_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[138]\, B => - \sample_filter_v2_out[120]\, Y => N189); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[143]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[143]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[143]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I26_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[97]\, Y => N199); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I88_un1_Y : - OA1 - port map(A => I78_un1_Y, B => N264_0, C => N197_0, Y => - I88_un1_Y); - - \SampleLoop_data_shaping.0.sample_data_shaping_out_RNO[107]\ : - AX1C - port map(A => \sample_filter_v2_out[125]\, B => - data_shaping_SP1, C => \sample_filter_v2_out[107]\, Y => - \sample_data_shaping_out_17[107]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I85_Y : - AO1 - port map(A => N278_0, B => N275_0, C => N274, Y => N280); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[27]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[27]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[27]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I85_un1_Y : - NOR2B - port map(A => N278, B => N275, Y => I85_un1_Y); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[136]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[136]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[136]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I39_Y : - XA1A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N195, Y => N265); - - lpp_waveform_1 : lpp_waveform - port map(status_full_ack(3) => status_full_ack(3), - status_full_ack(2) => status_full_ack(2), - status_full_ack(1) => status_full_ack(1), - status_full_ack(0) => status_full_ack(0), hburst_c(2) => - hburst_c(2), hburst_c(1) => hburst_c(1), hburst_c(0) => - hburst_c(0), htrans_c(1) => htrans_c(1), htrans_c(0) => - htrans_c(0), hsize_c(1) => hsize_c(1), hsize_c(0) => - hsize_c(0), AHB_Master_In_c_5 => AHB_Master_In_c_5, - AHB_Master_In_c_4 => AHB_Master_In_c_4, AHB_Master_In_c_0 - => AHB_Master_In_c_0, AHB_Master_In_c_3 => - AHB_Master_In_c_3, haddr_c(31) => haddr_c(31), - haddr_c(30) => haddr_c(30), haddr_c(29) => haddr_c(29), - haddr_c(28) => haddr_c(28), haddr_c(27) => haddr_c(27), - haddr_c(26) => haddr_c(26), haddr_c(25) => haddr_c(25), - haddr_c(24) => haddr_c(24), haddr_c(23) => haddr_c(23), - haddr_c(22) => haddr_c(22), haddr_c(21) => haddr_c(21), - haddr_c(20) => haddr_c(20), haddr_c(19) => haddr_c(19), - haddr_c(18) => haddr_c(18), haddr_c(17) => haddr_c(17), - haddr_c(16) => haddr_c(16), haddr_c(15) => haddr_c(15), - haddr_c(14) => haddr_c(14), haddr_c(13) => haddr_c(13), - haddr_c(12) => haddr_c(12), haddr_c(11) => haddr_c(11), - haddr_c(10) => haddr_c(10), haddr_c(9) => haddr_c(9), - haddr_c(8) => haddr_c(8), haddr_c(7) => haddr_c(7), - haddr_c(6) => haddr_c(6), haddr_c(5) => haddr_c(5), - haddr_c(4) => haddr_c(4), haddr_c(3) => haddr_c(3), - haddr_c(2) => haddr_c(2), haddr_c(1) => haddr_c(1), - haddr_c(0) => haddr_c(0), nb_burst_available(10) => - nb_burst_available(10), nb_burst_available(9) => - nb_burst_available(9), nb_burst_available(8) => - nb_burst_available(8), nb_burst_available(7) => - nb_burst_available(7), nb_burst_available(6) => - nb_burst_available(6), nb_burst_available(5) => - nb_burst_available(5), nb_burst_available(4) => - nb_burst_available(4), nb_burst_available(3) => - nb_burst_available(3), nb_burst_available(2) => - nb_burst_available(2), nb_burst_available(1) => - nb_burst_available(1), nb_burst_available(0) => - nb_burst_available(0), status_full_err(3) => - status_full_err(3), status_full_err(2) => - status_full_err(2), status_full_err(1) => - status_full_err(1), status_full_err(0) => - status_full_err(0), status_full(3) => status_full(3), - status_full(2) => status_full(2), status_full(1) => - status_full(1), status_full(0) => status_full(0), - addr_data_f3(31) => addr_data_f3(31), addr_data_f3(30) - => addr_data_f3(30), addr_data_f3(29) => - addr_data_f3(29), addr_data_f3(28) => addr_data_f3(28), - addr_data_f3(27) => addr_data_f3(27), addr_data_f3(26) - => addr_data_f3(26), addr_data_f3(25) => - addr_data_f3(25), addr_data_f3(24) => addr_data_f3(24), - addr_data_f3(23) => addr_data_f3(23), addr_data_f3(22) - => addr_data_f3(22), addr_data_f3(21) => - addr_data_f3(21), addr_data_f3(20) => addr_data_f3(20), - addr_data_f3(19) => addr_data_f3(19), addr_data_f3(18) - => addr_data_f3(18), addr_data_f3(17) => - addr_data_f3(17), addr_data_f3(16) => addr_data_f3(16), - addr_data_f3(15) => addr_data_f3(15), addr_data_f3(14) - => addr_data_f3(14), addr_data_f3(13) => - addr_data_f3(13), addr_data_f3(12) => addr_data_f3(12), - addr_data_f3(11) => addr_data_f3(11), addr_data_f3(10) - => addr_data_f3(10), addr_data_f3(9) => addr_data_f3(9), - addr_data_f3(8) => addr_data_f3(8), addr_data_f3(7) => - addr_data_f3(7), addr_data_f3(6) => addr_data_f3(6), - addr_data_f3(5) => addr_data_f3(5), addr_data_f3(4) => - addr_data_f3(4), addr_data_f3(3) => addr_data_f3(3), - addr_data_f3(2) => addr_data_f3(2), addr_data_f3(1) => - addr_data_f3(1), addr_data_f3(0) => addr_data_f3(0), - addr_data_f2(31) => addr_data_f2(31), addr_data_f2(30) - => addr_data_f2(30), addr_data_f2(29) => - addr_data_f2(29), addr_data_f2(28) => addr_data_f2(28), - addr_data_f2(27) => addr_data_f2(27), addr_data_f2(26) - => addr_data_f2(26), addr_data_f2(25) => - addr_data_f2(25), addr_data_f2(24) => addr_data_f2(24), - addr_data_f2(23) => addr_data_f2(23), addr_data_f2(22) - => addr_data_f2(22), addr_data_f2(21) => - addr_data_f2(21), addr_data_f2(20) => addr_data_f2(20), - addr_data_f2(19) => addr_data_f2(19), addr_data_f2(18) - => addr_data_f2(18), addr_data_f2(17) => - addr_data_f2(17), addr_data_f2(16) => addr_data_f2(16), - addr_data_f2(15) => addr_data_f2(15), addr_data_f2(14) - => addr_data_f2(14), addr_data_f2(13) => - addr_data_f2(13), addr_data_f2(12) => addr_data_f2(12), - addr_data_f2(11) => addr_data_f2(11), addr_data_f2(10) - => addr_data_f2(10), addr_data_f2(9) => addr_data_f2(9), - addr_data_f2(8) => addr_data_f2(8), addr_data_f2(7) => - addr_data_f2(7), addr_data_f2(6) => addr_data_f2(6), - addr_data_f2(5) => addr_data_f2(5), addr_data_f2(4) => - addr_data_f2(4), addr_data_f2(3) => addr_data_f2(3), - addr_data_f2(2) => addr_data_f2(2), addr_data_f2(1) => - addr_data_f2(1), addr_data_f2(0) => addr_data_f2(0), - addr_data_f1(31) => addr_data_f1(31), addr_data_f1(30) - => addr_data_f1(30), addr_data_f1(29) => - addr_data_f1(29), addr_data_f1(28) => addr_data_f1(28), - addr_data_f1(27) => addr_data_f1(27), addr_data_f1(26) - => addr_data_f1(26), addr_data_f1(25) => - addr_data_f1(25), addr_data_f1(24) => addr_data_f1(24), - addr_data_f1(23) => addr_data_f1(23), addr_data_f1(22) - => addr_data_f1(22), addr_data_f1(21) => - addr_data_f1(21), addr_data_f1(20) => addr_data_f1(20), - addr_data_f1(19) => addr_data_f1(19), addr_data_f1(18) - => addr_data_f1(18), addr_data_f1(17) => - addr_data_f1(17), addr_data_f1(16) => addr_data_f1(16), - addr_data_f1(15) => addr_data_f1(15), addr_data_f1(14) - => addr_data_f1(14), addr_data_f1(13) => - addr_data_f1(13), addr_data_f1(12) => addr_data_f1(12), - addr_data_f1(11) => addr_data_f1(11), addr_data_f1(10) - => addr_data_f1(10), addr_data_f1(9) => addr_data_f1(9), - addr_data_f1(8) => addr_data_f1(8), addr_data_f1(7) => - addr_data_f1(7), addr_data_f1(6) => addr_data_f1(6), - addr_data_f1(5) => addr_data_f1(5), addr_data_f1(4) => - addr_data_f1(4), addr_data_f1(3) => addr_data_f1(3), - addr_data_f1(2) => addr_data_f1(2), addr_data_f1(1) => - addr_data_f1(1), addr_data_f1(0) => addr_data_f1(0), - addr_data_f0(31) => addr_data_f0(31), addr_data_f0(30) - => addr_data_f0(30), addr_data_f0(29) => - addr_data_f0(29), addr_data_f0(28) => addr_data_f0(28), - addr_data_f0(27) => addr_data_f0(27), addr_data_f0(26) - => addr_data_f0(26), addr_data_f0(25) => - addr_data_f0(25), addr_data_f0(24) => addr_data_f0(24), - addr_data_f0(23) => addr_data_f0(23), addr_data_f0(22) - => addr_data_f0(22), addr_data_f0(21) => - addr_data_f0(21), addr_data_f0(20) => addr_data_f0(20), - addr_data_f0(19) => addr_data_f0(19), addr_data_f0(18) - => addr_data_f0(18), addr_data_f0(17) => - addr_data_f0(17), addr_data_f0(16) => addr_data_f0(16), - addr_data_f0(15) => addr_data_f0(15), addr_data_f0(14) - => addr_data_f0(14), addr_data_f0(13) => - addr_data_f0(13), addr_data_f0(12) => addr_data_f0(12), - addr_data_f0(11) => addr_data_f0(11), addr_data_f0(10) - => addr_data_f0(10), addr_data_f0(9) => addr_data_f0(9), - addr_data_f0(8) => addr_data_f0(8), addr_data_f0(7) => - addr_data_f0(7), addr_data_f0(6) => addr_data_f0(6), - addr_data_f0(5) => addr_data_f0(5), addr_data_f0(4) => - addr_data_f0(4), addr_data_f0(3) => addr_data_f0(3), - addr_data_f0(2) => addr_data_f0(2), addr_data_f0(1) => - addr_data_f0(1), addr_data_f0(0) => addr_data_f0(0), - hwdata_c(31) => hwdata_c(31), hwdata_c(30) => - hwdata_c(30), hwdata_c(29) => hwdata_c(29), hwdata_c(28) - => hwdata_c(28), hwdata_c(27) => hwdata_c(27), - hwdata_c(26) => hwdata_c(26), hwdata_c(25) => - hwdata_c(25), hwdata_c(24) => hwdata_c(24), hwdata_c(23) - => hwdata_c(23), hwdata_c(22) => hwdata_c(22), - hwdata_c(21) => hwdata_c(21), hwdata_c(20) => - hwdata_c(20), hwdata_c(19) => hwdata_c(19), hwdata_c(18) - => hwdata_c(18), hwdata_c(17) => hwdata_c(17), - hwdata_c(16) => hwdata_c(16), hwdata_c(15) => - hwdata_c(15), hwdata_c(14) => hwdata_c(14), hwdata_c(13) - => hwdata_c(13), hwdata_c(12) => hwdata_c(12), - hwdata_c(11) => hwdata_c(11), hwdata_c(10) => - hwdata_c(10), hwdata_c(9) => hwdata_c(9), hwdata_c(8) => - hwdata_c(8), hwdata_c(7) => hwdata_c(7), hwdata_c(6) => - hwdata_c(6), hwdata_c(5) => hwdata_c(5), hwdata_c(4) => - hwdata_c(4), hwdata_c(3) => hwdata_c(3), hwdata_c(2) => - hwdata_c(2), hwdata_c(1) => hwdata_c(1), hwdata_c(0) => - hwdata_c(0), status_new_err(3) => status_new_err(3), - status_new_err(2) => status_new_err(2), status_new_err(1) - => status_new_err(1), status_new_err(0) => - status_new_err(0), sample_f3_wdata(95) => - \sample_f3_wdata[95]\, sample_f3_wdata(94) => - \sample_f3_wdata[94]\, sample_f3_wdata(93) => - \sample_f3_wdata[93]\, sample_f3_wdata(92) => - \sample_f3_wdata[92]\, sample_f3_wdata(91) => - \sample_f3_wdata[91]\, sample_f3_wdata(90) => - \sample_f3_wdata[90]\, sample_f3_wdata(89) => - \sample_f3_wdata[89]\, sample_f3_wdata(88) => - \sample_f3_wdata[88]\, sample_f3_wdata(87) => - \sample_f3_wdata[87]\, sample_f3_wdata(86) => - \sample_f3_wdata[86]\, sample_f3_wdata(85) => - \sample_f3_wdata[85]\, sample_f3_wdata(84) => - \sample_f3_wdata[84]\, sample_f3_wdata(83) => - \sample_f3_wdata[83]\, sample_f3_wdata(82) => - \sample_f3_wdata[82]\, sample_f3_wdata(81) => - \sample_f3_wdata[81]\, sample_f3_wdata(80) => - \sample_f3_wdata[80]\, sample_f3_wdata(79) => - \sample_f3_wdata[79]\, sample_f3_wdata(78) => - \sample_f3_wdata[78]\, sample_f3_wdata(77) => - \sample_f3_wdata[77]\, sample_f3_wdata(76) => - \sample_f3_wdata[76]\, sample_f3_wdata(75) => - \sample_f3_wdata[75]\, sample_f3_wdata(74) => - \sample_f3_wdata[74]\, sample_f3_wdata(73) => - \sample_f3_wdata[73]\, sample_f3_wdata(72) => - \sample_f3_wdata[72]\, sample_f3_wdata(71) => - \sample_f3_wdata[71]\, sample_f3_wdata(70) => - \sample_f3_wdata[70]\, sample_f3_wdata(69) => - \sample_f3_wdata[69]\, sample_f3_wdata(68) => - \sample_f3_wdata[68]\, sample_f3_wdata(67) => - \sample_f3_wdata[67]\, sample_f3_wdata(66) => - \sample_f3_wdata[66]\, sample_f3_wdata(65) => - \sample_f3_wdata[65]\, sample_f3_wdata(64) => - \sample_f3_wdata[64]\, sample_f3_wdata(63) => - \sample_f3_wdata[63]\, sample_f3_wdata(62) => - \sample_f3_wdata[62]\, sample_f3_wdata(61) => - \sample_f3_wdata[61]\, sample_f3_wdata(60) => - \sample_f3_wdata[60]\, sample_f3_wdata(59) => - \sample_f3_wdata[59]\, sample_f3_wdata(58) => - \sample_f3_wdata[58]\, sample_f3_wdata(57) => - \sample_f3_wdata[57]\, sample_f3_wdata(56) => - \sample_f3_wdata[56]\, sample_f3_wdata(55) => - \sample_f3_wdata[55]\, sample_f3_wdata(54) => - \sample_f3_wdata[54]\, sample_f3_wdata(53) => - \sample_f3_wdata[53]\, sample_f3_wdata(52) => - \sample_f3_wdata[52]\, sample_f3_wdata(51) => - \sample_f3_wdata[51]\, sample_f3_wdata(50) => - \sample_f3_wdata[50]\, sample_f3_wdata(49) => - \sample_f3_wdata[49]\, sample_f3_wdata(48) => - \sample_f3_wdata[48]\, sample_f3_wdata(47) => - \sample_f3_wdata[47]\, sample_f3_wdata(46) => - \sample_f3_wdata[46]\, sample_f3_wdata(45) => - \sample_f3_wdata[45]\, sample_f3_wdata(44) => - \sample_f3_wdata[44]\, sample_f3_wdata(43) => - \sample_f3_wdata[43]\, sample_f3_wdata(42) => - \sample_f3_wdata[42]\, sample_f3_wdata(41) => - \sample_f3_wdata[41]\, sample_f3_wdata(40) => - \sample_f3_wdata[40]\, sample_f3_wdata(39) => - \sample_f3_wdata[39]\, sample_f3_wdata(38) => - \sample_f3_wdata[38]\, sample_f3_wdata(37) => - \sample_f3_wdata[37]\, sample_f3_wdata(36) => - \sample_f3_wdata[36]\, sample_f3_wdata(35) => - \sample_f3_wdata[35]\, sample_f3_wdata(34) => - \sample_f3_wdata[34]\, sample_f3_wdata(33) => - \sample_f3_wdata[33]\, sample_f3_wdata(32) => - \sample_f3_wdata[32]\, sample_f3_wdata(31) => - \sample_f3_wdata[31]\, sample_f3_wdata(30) => - \sample_f3_wdata[30]\, sample_f3_wdata(29) => - \sample_f3_wdata[29]\, sample_f3_wdata(28) => - \sample_f3_wdata[28]\, sample_f3_wdata(27) => - \sample_f3_wdata[27]\, sample_f3_wdata(26) => - \sample_f3_wdata[26]\, sample_f3_wdata(25) => - \sample_f3_wdata[25]\, sample_f3_wdata(24) => - \sample_f3_wdata[24]\, sample_f3_wdata(23) => - \sample_f3_wdata[23]\, sample_f3_wdata(22) => - \sample_f3_wdata[22]\, sample_f3_wdata(21) => - \sample_f3_wdata[21]\, sample_f3_wdata(20) => - \sample_f3_wdata[20]\, sample_f3_wdata(19) => - \sample_f3_wdata[19]\, sample_f3_wdata(18) => - \sample_f3_wdata[18]\, sample_f3_wdata(17) => - \sample_f3_wdata[17]\, sample_f3_wdata(16) => - \sample_f3_wdata[16]\, sample_f3_wdata(15) => - \sample_f3_wdata[15]\, sample_f3_wdata(14) => - \sample_f3_wdata[14]\, sample_f3_wdata(13) => - \sample_f3_wdata[13]\, sample_f3_wdata(12) => - \sample_f3_wdata[12]\, sample_f3_wdata(11) => - \sample_f3_wdata[11]\, sample_f3_wdata(10) => - \sample_f3_wdata[10]\, sample_f3_wdata(9) => - \sample_f3_wdata[9]\, sample_f3_wdata(8) => - \sample_f3_wdata[8]\, sample_f3_wdata(7) => - \sample_f3_wdata[7]\, sample_f3_wdata(6) => - \sample_f3_wdata[6]\, sample_f3_wdata(5) => - \sample_f3_wdata[5]\, sample_f3_wdata(4) => - \sample_f3_wdata[4]\, sample_f3_wdata(3) => - \sample_f3_wdata[3]\, sample_f3_wdata(2) => - \sample_f3_wdata[2]\, sample_f3_wdata(1) => - \sample_f3_wdata[1]\, sample_f3_wdata(0) => - \sample_f3_wdata[0]\, sample_f2_wdata(95) => - \sample_f2_wdata[95]\, sample_f2_wdata(94) => - \sample_f2_wdata[94]\, sample_f2_wdata(93) => - \sample_f2_wdata[93]\, sample_f2_wdata(92) => - \sample_f2_wdata[92]\, sample_f2_wdata(91) => - \sample_f2_wdata[91]\, sample_f2_wdata(90) => - \sample_f2_wdata[90]\, sample_f2_wdata(89) => - \sample_f2_wdata[89]\, sample_f2_wdata(88) => - \sample_f2_wdata[88]\, sample_f2_wdata(87) => - \sample_f2_wdata[87]\, sample_f2_wdata(86) => - \sample_f2_wdata[86]\, sample_f2_wdata(85) => - \sample_f2_wdata[85]\, sample_f2_wdata(84) => - \sample_f2_wdata[84]\, sample_f2_wdata(83) => - \sample_f2_wdata[83]\, sample_f2_wdata(82) => - \sample_f2_wdata[82]\, sample_f2_wdata(81) => - \sample_f2_wdata[81]\, sample_f2_wdata(80) => - \sample_f2_wdata[80]\, sample_f2_wdata(79) => - \sample_f2_wdata[79]\, sample_f2_wdata(78) => - \sample_f2_wdata[78]\, sample_f2_wdata(77) => - \sample_f2_wdata[77]\, sample_f2_wdata(76) => - \sample_f2_wdata[76]\, sample_f2_wdata(75) => - \sample_f2_wdata[75]\, sample_f2_wdata(74) => - \sample_f2_wdata[74]\, sample_f2_wdata(73) => - \sample_f2_wdata[73]\, sample_f2_wdata(72) => - \sample_f2_wdata[72]\, sample_f2_wdata(71) => - \sample_f2_wdata[71]\, sample_f2_wdata(70) => - \sample_f2_wdata[70]\, sample_f2_wdata(69) => - \sample_f2_wdata[69]\, sample_f2_wdata(68) => - \sample_f2_wdata[68]\, sample_f2_wdata(67) => - \sample_f2_wdata[67]\, sample_f2_wdata(66) => - \sample_f2_wdata[66]\, sample_f2_wdata(65) => - \sample_f2_wdata[65]\, sample_f2_wdata(64) => - \sample_f2_wdata[64]\, sample_f2_wdata(63) => - \sample_f2_wdata[63]\, sample_f2_wdata(62) => - \sample_f2_wdata[62]\, sample_f2_wdata(61) => - \sample_f2_wdata[61]\, sample_f2_wdata(60) => - \sample_f2_wdata[60]\, sample_f2_wdata(59) => - \sample_f2_wdata[59]\, sample_f2_wdata(58) => - \sample_f2_wdata[58]\, sample_f2_wdata(57) => - \sample_f2_wdata[57]\, sample_f2_wdata(56) => - \sample_f2_wdata[56]\, sample_f2_wdata(55) => - \sample_f2_wdata[55]\, sample_f2_wdata(54) => - \sample_f2_wdata[54]\, sample_f2_wdata(53) => - \sample_f2_wdata[53]\, sample_f2_wdata(52) => - \sample_f2_wdata[52]\, sample_f2_wdata(51) => - \sample_f2_wdata[51]\, sample_f2_wdata(50) => - \sample_f2_wdata[50]\, sample_f2_wdata(49) => - \sample_f2_wdata[49]\, sample_f2_wdata(48) => - \sample_f2_wdata[48]\, sample_f2_wdata(47) => - \sample_f2_wdata[47]\, sample_f2_wdata(46) => - \sample_f2_wdata[46]\, sample_f2_wdata(45) => - \sample_f2_wdata[45]\, sample_f2_wdata(44) => - \sample_f2_wdata[44]\, sample_f2_wdata(43) => - \sample_f2_wdata[43]\, sample_f2_wdata(42) => - \sample_f2_wdata[42]\, sample_f2_wdata(41) => - \sample_f2_wdata[41]\, sample_f2_wdata(40) => - \sample_f2_wdata[40]\, sample_f2_wdata(39) => - \sample_f2_wdata[39]\, sample_f2_wdata(38) => - \sample_f2_wdata[38]\, sample_f2_wdata(37) => - \sample_f2_wdata[37]\, sample_f2_wdata(36) => - \sample_f2_wdata[36]\, sample_f2_wdata(35) => - \sample_f2_wdata[35]\, sample_f2_wdata(34) => - \sample_f2_wdata[34]\, sample_f2_wdata(33) => - \sample_f2_wdata[33]\, sample_f2_wdata(32) => - \sample_f2_wdata[32]\, sample_f2_wdata(31) => - \sample_f2_wdata[31]\, sample_f2_wdata(30) => - \sample_f2_wdata[30]\, sample_f2_wdata(29) => - \sample_f2_wdata[29]\, sample_f2_wdata(28) => - \sample_f2_wdata[28]\, sample_f2_wdata(27) => - \sample_f2_wdata[27]\, sample_f2_wdata(26) => - \sample_f2_wdata[26]\, sample_f2_wdata(25) => - \sample_f2_wdata[25]\, sample_f2_wdata(24) => - \sample_f2_wdata[24]\, sample_f2_wdata(23) => - \sample_f2_wdata[23]\, sample_f2_wdata(22) => - \sample_f2_wdata[22]\, sample_f2_wdata(21) => - \sample_f2_wdata[21]\, sample_f2_wdata(20) => - \sample_f2_wdata[20]\, sample_f2_wdata(19) => - \sample_f2_wdata[19]\, sample_f2_wdata(18) => - \sample_f2_wdata[18]\, sample_f2_wdata(17) => - \sample_f2_wdata[17]\, sample_f2_wdata(16) => - \sample_f2_wdata[16]\, sample_f2_wdata(15) => - \sample_f2_wdata[15]\, sample_f2_wdata(14) => - \sample_f2_wdata[14]\, sample_f2_wdata(13) => - \sample_f2_wdata[13]\, sample_f2_wdata(12) => - \sample_f2_wdata[12]\, sample_f2_wdata(11) => - \sample_f2_wdata[11]\, sample_f2_wdata(10) => - \sample_f2_wdata[10]\, sample_f2_wdata(9) => - \sample_f2_wdata[9]\, sample_f2_wdata(8) => - \sample_f2_wdata[8]\, sample_f2_wdata(7) => - \sample_f2_wdata[7]\, sample_f2_wdata(6) => - \sample_f2_wdata[6]\, sample_f2_wdata(5) => - \sample_f2_wdata[5]\, sample_f2_wdata(4) => - \sample_f2_wdata[4]\, sample_f2_wdata(3) => - \sample_f2_wdata[3]\, sample_f2_wdata(2) => - \sample_f2_wdata[2]\, sample_f2_wdata(1) => - \sample_f2_wdata[1]\, sample_f2_wdata(0) => - \sample_f2_wdata[0]\, sample_f1_15 => \sample_f1[63]\, - sample_f1_47 => \sample_f1[95]\, sample_f1_14 => - \sample_f1[62]\, sample_f1_46 => \sample_f1[94]\, - sample_f1_13 => \sample_f1[61]\, sample_f1_45 => - \sample_f1[93]\, sample_f1_12 => \sample_f1[60]\, - sample_f1_44 => \sample_f1[92]\, sample_f1_60 => - \sample_f1[108]\, sample_f1_59 => \sample_f1[107]\, - sample_f1_58 => \sample_f1[106]\, sample_f1_57 => - \sample_f1[105]\, sample_f1_56 => \sample_f1[104]\, - sample_f1_55 => \sample_f1[103]\, sample_f1_54 => - \sample_f1[102]\, sample_f1_53 => \sample_f1[101]\, - sample_f1_52 => \sample_f1[100]\, sample_f1_51 => - \sample_f1[99]\, sample_f1_50 => \sample_f1[98]\, - sample_f1_49 => \sample_f1[97]\, sample_f1_48 => - \sample_f1[96]\, sample_f1_4 => \sample_f1[52]\, - sample_f1_36 => \sample_f1[84]\, sample_f1_3 => - \sample_f1[51]\, sample_f1_35 => \sample_f1[83]\, - sample_f1_2 => \sample_f1[50]\, sample_f1_34 => - \sample_f1[82]\, sample_f1_1 => \sample_f1[49]\, - sample_f1_33 => \sample_f1[81]\, sample_f1_0 => - \sample_f1[48]\, sample_f1_32 => \sample_f1[80]\, - sample_f1_63 => \sample_f1[111]\, sample_f1_62 => - \sample_f1[110]\, sample_f1_61 => \sample_f1[109]\, - sample_f1_11 => \sample_f1[59]\, sample_f1_43 => - \sample_f1[91]\, sample_f1_10 => \sample_f1[58]\, - sample_f1_42 => \sample_f1[90]\, sample_f1_9 => - \sample_f1[57]\, sample_f1_41 => \sample_f1[89]\, - sample_f1_8 => \sample_f1[56]\, sample_f1_40 => - \sample_f1[88]\, sample_f1_7 => \sample_f1[55]\, - sample_f1_39 => \sample_f1[87]\, sample_f1_6 => - \sample_f1[54]\, sample_f1_38 => \sample_f1[86]\, - sample_f1_5 => \sample_f1[53]\, sample_f1_37 => - \sample_f1[85]\, sample_f1_wdata_0 => - \sample_f1_wdata[0]\, sample_f1_wdata_1 => - \sample_f1_wdata[1]\, sample_f1_wdata_2 => - \sample_f1_wdata[2]\, sample_f1_wdata_3 => - \sample_f1_wdata[3]\, sample_f1_wdata_4 => - \sample_f1_wdata[4]\, sample_f1_wdata_5 => - \sample_f1_wdata[5]\, sample_f1_wdata_6 => - \sample_f1_wdata[6]\, sample_f1_wdata_7 => - \sample_f1_wdata[7]\, sample_f1_wdata_8 => - \sample_f1_wdata[8]\, sample_f1_wdata_9 => - \sample_f1_wdata[9]\, sample_f1_wdata_10 => - \sample_f1_wdata[10]\, sample_f1_wdata_11 => - \sample_f1_wdata[11]\, sample_f1_wdata_12 => - \sample_f1_wdata[12]\, sample_f1_wdata_13 => - \sample_f1_wdata[13]\, sample_f1_wdata_14 => - \sample_f1_wdata[14]\, sample_f1_wdata_15 => - \sample_f1_wdata[15]\, sample_f1_wdata_48 => - \sample_f1_wdata[48]\, sample_f1_wdata_49 => - \sample_f1_wdata[49]\, sample_f1_wdata_50 => - \sample_f1_wdata[50]\, sample_f1_wdata_51 => - \sample_f1_wdata[51]\, sample_f1_wdata_52 => - \sample_f1_wdata[52]\, sample_f1_wdata_53 => - \sample_f1_wdata[53]\, sample_f1_wdata_54 => - \sample_f1_wdata[54]\, sample_f1_wdata_55 => - \sample_f1_wdata[55]\, sample_f1_wdata_56 => - \sample_f1_wdata[56]\, sample_f1_wdata_57 => - \sample_f1_wdata[57]\, sample_f1_wdata_58 => - \sample_f1_wdata[58]\, sample_f1_wdata_59 => - \sample_f1_wdata[59]\, sample_f1_wdata_60 => - \sample_f1_wdata[60]\, sample_f1_wdata_61 => - \sample_f1_wdata[61]\, sample_f1_wdata_62 => - \sample_f1_wdata[62]\, sample_f1_wdata_63 => - \sample_f1_wdata[63]\, sample_f1_wdata_64 => - \sample_f1_wdata[64]\, sample_f1_wdata_65 => - \sample_f1_wdata[65]\, sample_f1_wdata_66 => - \sample_f1_wdata[66]\, sample_f1_wdata_67 => - \sample_f1_wdata[67]\, sample_f1_wdata_68 => - \sample_f1_wdata[68]\, sample_f1_wdata_69 => - \sample_f1_wdata[69]\, sample_f1_wdata_70 => - \sample_f1_wdata[70]\, sample_f1_wdata_71 => - \sample_f1_wdata[71]\, sample_f1_wdata_72 => - \sample_f1_wdata[72]\, sample_f1_wdata_73 => - \sample_f1_wdata[73]\, sample_f1_wdata_74 => - \sample_f1_wdata[74]\, sample_f1_wdata_75 => - \sample_f1_wdata[75]\, sample_f1_wdata_76 => - \sample_f1_wdata[76]\, sample_f1_wdata_77 => - \sample_f1_wdata[77]\, sample_f1_wdata_78 => - \sample_f1_wdata[78]\, sample_f1_wdata_79 => - \sample_f1_wdata[79]\, sample_f1_wdata_80 => - \sample_f1_wdata[80]\, sample_f1_wdata_81 => - \sample_f1_wdata[81]\, sample_f1_wdata_82 => - \sample_f1_wdata[82]\, sample_f1_wdata_83 => - \sample_f1_wdata[83]\, sample_f1_wdata_84 => - \sample_f1_wdata[84]\, sample_f1_wdata_85 => - \sample_f1_wdata[85]\, sample_f1_wdata_86 => - \sample_f1_wdata[86]\, sample_f1_wdata_87 => - \sample_f1_wdata[87]\, sample_f1_wdata_88 => - \sample_f1_wdata[88]\, sample_f1_wdata_89 => - \sample_f1_wdata[89]\, sample_f1_wdata_90 => - \sample_f1_wdata[90]\, sample_f1_wdata_91 => - \sample_f1_wdata[91]\, sample_f1_wdata_92 => - \sample_f1_wdata[92]\, sample_f1_wdata_93 => - \sample_f1_wdata[93]\, sample_f1_wdata_94 => - \sample_f1_wdata[94]\, sample_f1_wdata_95 => - \sample_f1_wdata[95]\, sample_f0_15 => \sample_f0[63]\, - sample_f0_47 => \sample_f0[95]\, sample_f0_14 => - \sample_f0[62]\, sample_f0_46 => \sample_f0[94]\, - sample_f0_13 => \sample_f0[61]\, sample_f0_45 => - \sample_f0[93]\, sample_f0_12 => \sample_f0[60]\, - sample_f0_44 => \sample_f0[92]\, sample_f0_60 => - \sample_f0[108]\, sample_f0_59 => \sample_f0[107]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_57 => - \sample_f0[105]\, sample_f0_56 => \sample_f0[104]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_54 => - \sample_f0[102]\, sample_f0_53 => \sample_f0[101]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_51 => - \sample_f0[99]\, sample_f0_50 => \sample_f0[98]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_48 => - \sample_f0[96]\, sample_f0_4 => \sample_f0[52]\, - sample_f0_36 => \sample_f0[84]\, sample_f0_3 => - \sample_f0[51]\, sample_f0_35 => \sample_f0[83]\, - sample_f0_2 => \sample_f0[50]\, sample_f0_34 => - \sample_f0[82]\, sample_f0_1 => \sample_f0[49]\, - sample_f0_33 => \sample_f0[81]\, sample_f0_0 => - \sample_f0[48]\, sample_f0_32 => \sample_f0[80]\, - sample_f0_63 => \sample_f0[111]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_61 => \sample_f0[109]\, - sample_f0_11 => \sample_f0[59]\, sample_f0_43 => - \sample_f0[91]\, sample_f0_10 => \sample_f0[58]\, - sample_f0_42 => \sample_f0[90]\, sample_f0_9 => - \sample_f0[57]\, sample_f0_41 => \sample_f0[89]\, - sample_f0_8 => \sample_f0[56]\, sample_f0_40 => - \sample_f0[88]\, sample_f0_7 => \sample_f0[55]\, - sample_f0_39 => \sample_f0[87]\, sample_f0_6 => - \sample_f0[54]\, sample_f0_38 => \sample_f0[86]\, - sample_f0_5 => \sample_f0[53]\, sample_f0_37 => - \sample_f0[85]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, delta_f2_f1(9) => delta_f2_f1(9), - delta_f2_f1(8) => delta_f2_f1(8), delta_f2_f1(7) => - delta_f2_f1(7), delta_f2_f1(6) => delta_f2_f1(6), - delta_f2_f1(5) => delta_f2_f1(5), delta_f2_f1(4) => - delta_f2_f1(4), delta_f2_f1(3) => delta_f2_f1(3), - delta_f2_f1(2) => delta_f2_f1(2), delta_f2_f1(1) => - delta_f2_f1(1), delta_f2_f1(0) => delta_f2_f1(0), - delta_snapshot(15) => delta_snapshot(15), - delta_snapshot(14) => delta_snapshot(14), - delta_snapshot(13) => delta_snapshot(13), - delta_snapshot(12) => delta_snapshot(12), - delta_snapshot(11) => delta_snapshot(11), - delta_snapshot(10) => delta_snapshot(10), - delta_snapshot(9) => delta_snapshot(9), delta_snapshot(8) - => delta_snapshot(8), delta_snapshot(7) => - delta_snapshot(7), delta_snapshot(6) => delta_snapshot(6), - delta_snapshot(5) => delta_snapshot(5), delta_snapshot(4) - => delta_snapshot(4), delta_snapshot(3) => - delta_snapshot(3), delta_snapshot(2) => delta_snapshot(2), - delta_snapshot(1) => delta_snapshot(1), delta_snapshot(0) - => delta_snapshot(0), delta_f2_f0(9) => delta_f2_f0(9), - delta_f2_f0(8) => delta_f2_f0(8), delta_f2_f0(7) => - delta_f2_f0(7), delta_f2_f0(6) => delta_f2_f0(6), - delta_f2_f0(5) => delta_f2_f0(5), delta_f2_f0(4) => - delta_f2_f0(4), delta_f2_f0(3) => delta_f2_f0(3), - delta_f2_f0(2) => delta_f2_f0(2), delta_f2_f0(1) => - delta_f2_f0(1), delta_f2_f0(0) => delta_f2_f0(0), - nb_snapshot_param(10) => nb_snapshot_param(10), - nb_snapshot_param(9) => nb_snapshot_param(9), - nb_snapshot_param(8) => nb_snapshot_param(8), - nb_snapshot_param(7) => nb_snapshot_param(7), - nb_snapshot_param(6) => nb_snapshot_param(6), - nb_snapshot_param(5) => nb_snapshot_param(5), - nb_snapshot_param(4) => nb_snapshot_param(4), - nb_snapshot_param(3) => nb_snapshot_param(3), - nb_snapshot_param(2) => nb_snapshot_param(2), - nb_snapshot_param(1) => nb_snapshot_param(1), - nb_snapshot_param(0) => nb_snapshot_param(0), hwrite_c - => hwrite_c, IdlePhase_RNI03G71 => IdlePhase_RNI03G71, - N_43 => N_43, lpp_waveform_GND => - lpp_top_lfr_wf_picker_ip_GND, lpp_waveform_VCC => - lpp_top_lfr_wf_picker_ip_VCC, sample_f3_val => - sample_f3_val, enable_f3 => enable_f3, burst_f2 => - burst_f2, enable_f2 => enable_f2, sample_f1_val_0 => - sample_f1_val_0, burst_f1 => burst_f1, enable_f1 => - enable_f1, data_shaping_R1_0 => data_shaping_R1_0, - data_shaping_R1 => data_shaping_R1, burst_f0 => burst_f0, - data_shaping_R0_0 => data_shaping_R0_0, data_shaping_R0 - => data_shaping_R0, enable_f0 => enable_f0, - coarse_time_0_c => coarse_time_0_c, sample_f2_val => - sample_f2_val, sample_f0_val_0 => sample_f0_val_0, HCLK_c - => HCLK_c, HRESETn_c => HRESETn_c); - - Downsampling_f0 : Downsampling_8_16_4 - port map(sample_f0_0 => \sample_f0[48]\, sample_f0_1 => - \sample_f0[49]\, sample_f0_2 => \sample_f0[50]\, - sample_f0_3 => \sample_f0[51]\, sample_f0_4 => - \sample_f0[52]\, sample_f0_5 => \sample_f0[53]\, - sample_f0_6 => \sample_f0[54]\, sample_f0_7 => - \sample_f0[55]\, sample_f0_8 => \sample_f0[56]\, - sample_f0_9 => \sample_f0[57]\, sample_f0_10 => - \sample_f0[58]\, sample_f0_11 => \sample_f0[59]\, - sample_f0_12 => \sample_f0[60]\, sample_f0_13 => - \sample_f0[61]\, sample_f0_14 => \sample_f0[62]\, - sample_f0_15 => \sample_f0[63]\, sample_f0_32 => - \sample_f0[80]\, sample_f0_33 => \sample_f0[81]\, - sample_f0_34 => \sample_f0[82]\, sample_f0_35 => - \sample_f0[83]\, sample_f0_36 => \sample_f0[84]\, - sample_f0_37 => \sample_f0[85]\, sample_f0_38 => - \sample_f0[86]\, sample_f0_39 => \sample_f0[87]\, - sample_f0_40 => \sample_f0[88]\, sample_f0_41 => - \sample_f0[89]\, sample_f0_42 => \sample_f0[90]\, - sample_f0_43 => \sample_f0[91]\, sample_f0_44 => - \sample_f0[92]\, sample_f0_45 => \sample_f0[93]\, - sample_f0_46 => \sample_f0[94]\, sample_f0_47 => - \sample_f0[95]\, sample_f0_48 => \sample_f0[96]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_50 => - \sample_f0[98]\, sample_f0_51 => \sample_f0[99]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_53 => - \sample_f0[101]\, sample_f0_54 => \sample_f0[102]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_56 => - \sample_f0[104]\, sample_f0_57 => \sample_f0[105]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_59 => - \sample_f0[107]\, sample_f0_60 => \sample_f0[108]\, - sample_f0_61 => \sample_f0[109]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_63 => \sample_f0[111]\, - sample_data_shaping_out_0 => \sample_data_shaping_out[2]\, - sample_data_shaping_out_1 => \sample_data_shaping_out[3]\, - sample_data_shaping_out_2 => \sample_data_shaping_out[4]\, - sample_data_shaping_out_3 => \sample_data_shaping_out[5]\, - sample_data_shaping_out_4 => \sample_data_shaping_out[6]\, - sample_data_shaping_out_5 => \sample_data_shaping_out[7]\, - sample_data_shaping_out_6 => \sample_data_shaping_out[8]\, - sample_data_shaping_out_7 => \sample_data_shaping_out[9]\, - sample_data_shaping_out_8 => - \sample_data_shaping_out[10]\, sample_data_shaping_out_9 - => \sample_data_shaping_out[11]\, - sample_data_shaping_out_10 => - \sample_data_shaping_out[12]\, sample_data_shaping_out_11 - => \sample_data_shaping_out[13]\, - sample_data_shaping_out_12 => - \sample_data_shaping_out[14]\, sample_data_shaping_out_13 - => \sample_data_shaping_out[15]\, - sample_data_shaping_out_14 => - \sample_data_shaping_out[16]\, sample_data_shaping_out_15 - => \sample_data_shaping_out[17]\, - sample_data_shaping_out_18 => - \sample_data_shaping_out[20]\, sample_data_shaping_out_19 - => \sample_data_shaping_out[21]\, - sample_data_shaping_out_20 => - \sample_data_shaping_out[22]\, sample_data_shaping_out_21 - => \sample_data_shaping_out[23]\, - sample_data_shaping_out_22 => - \sample_data_shaping_out[24]\, sample_data_shaping_out_23 - => \sample_data_shaping_out[25]\, - sample_data_shaping_out_24 => - \sample_data_shaping_out[26]\, sample_data_shaping_out_25 - => \sample_data_shaping_out[27]\, - sample_data_shaping_out_26 => - \sample_data_shaping_out[28]\, sample_data_shaping_out_27 - => \sample_data_shaping_out[29]\, - sample_data_shaping_out_28 => - \sample_data_shaping_out[30]\, sample_data_shaping_out_29 - => \sample_data_shaping_out[31]\, - sample_data_shaping_out_30 => - \sample_data_shaping_out[32]\, sample_data_shaping_out_31 - => \sample_data_shaping_out[33]\, - sample_data_shaping_out_32 => - \sample_data_shaping_out[34]\, sample_data_shaping_out_33 - => \sample_data_shaping_out[35]\, - sample_data_shaping_out_36 => - \sample_data_shaping_out[38]\, sample_data_shaping_out_37 - => \sample_data_shaping_out[39]\, - sample_data_shaping_out_38 => - \sample_data_shaping_out[40]\, sample_data_shaping_out_39 - => \sample_data_shaping_out[41]\, - sample_data_shaping_out_40 => - \sample_data_shaping_out[42]\, sample_data_shaping_out_41 - => \sample_data_shaping_out[43]\, - sample_data_shaping_out_42 => - \sample_data_shaping_out[44]\, sample_data_shaping_out_43 - => \sample_data_shaping_out[45]\, - sample_data_shaping_out_44 => - \sample_data_shaping_out[46]\, sample_data_shaping_out_45 - => \sample_data_shaping_out[47]\, - sample_data_shaping_out_46 => - \sample_data_shaping_out[48]\, sample_data_shaping_out_47 - => \sample_data_shaping_out[49]\, - sample_data_shaping_out_48 => - \sample_data_shaping_out[50]\, sample_data_shaping_out_49 - => \sample_data_shaping_out[51]\, - sample_data_shaping_out_50 => - \sample_data_shaping_out[52]\, sample_data_shaping_out_51 - => \sample_data_shaping_out[53]\, - sample_data_shaping_out_54 => - \sample_data_shaping_out[56]\, sample_data_shaping_out_55 - => \sample_data_shaping_out[57]\, - sample_data_shaping_out_56 => - \sample_data_shaping_out[58]\, sample_data_shaping_out_57 - => \sample_data_shaping_out[59]\, - sample_data_shaping_out_58 => - \sample_data_shaping_out[60]\, sample_data_shaping_out_59 - => \sample_data_shaping_out[61]\, - sample_data_shaping_out_60 => - \sample_data_shaping_out[62]\, sample_data_shaping_out_61 - => \sample_data_shaping_out[63]\, - sample_data_shaping_out_62 => - \sample_data_shaping_out[64]\, sample_data_shaping_out_63 - => \sample_data_shaping_out[65]\, - sample_data_shaping_out_64 => - \sample_data_shaping_out[66]\, sample_data_shaping_out_65 - => \sample_data_shaping_out[67]\, - sample_data_shaping_out_66 => - \sample_data_shaping_out[68]\, sample_data_shaping_out_67 - => \sample_data_shaping_out[69]\, - sample_data_shaping_out_68 => - \sample_data_shaping_out[70]\, sample_data_shaping_out_69 - => \sample_data_shaping_out[71]\, - sample_data_shaping_out_90 => - \sample_data_shaping_out[92]\, sample_data_shaping_out_91 - => \sample_data_shaping_out[93]\, - sample_data_shaping_out_92 => - \sample_data_shaping_out[94]\, sample_data_shaping_out_93 - => \sample_data_shaping_out[95]\, - sample_data_shaping_out_94 => - \sample_data_shaping_out[96]\, sample_data_shaping_out_95 - => \sample_data_shaping_out[97]\, - sample_data_shaping_out_96 => - \sample_data_shaping_out[98]\, sample_data_shaping_out_97 - => \sample_data_shaping_out[99]\, - sample_data_shaping_out_98 => - \sample_data_shaping_out[100]\, - sample_data_shaping_out_99 => - \sample_data_shaping_out[101]\, - sample_data_shaping_out_100 => - \sample_data_shaping_out[102]\, - sample_data_shaping_out_101 => - \sample_data_shaping_out[103]\, - sample_data_shaping_out_102 => - \sample_data_shaping_out[104]\, - sample_data_shaping_out_103 => - \sample_data_shaping_out[105]\, - sample_data_shaping_out_104 => - \sample_data_shaping_out[106]\, - sample_data_shaping_out_105 => - \sample_data_shaping_out[107]\, - sample_data_shaping_out_108 => - \sample_data_shaping_out[110]\, - sample_data_shaping_out_109 => - \sample_data_shaping_out[111]\, - sample_data_shaping_out_110 => - \sample_data_shaping_out[112]\, - sample_data_shaping_out_111 => - \sample_data_shaping_out[113]\, - sample_data_shaping_out_112 => - \sample_data_shaping_out[114]\, - sample_data_shaping_out_113 => - \sample_data_shaping_out[115]\, - sample_data_shaping_out_114 => - \sample_data_shaping_out[116]\, - sample_data_shaping_out_115 => - \sample_data_shaping_out[117]\, - sample_data_shaping_out_116 => - \sample_data_shaping_out[118]\, - sample_data_shaping_out_117 => - \sample_data_shaping_out[119]\, - sample_data_shaping_out_118 => - \sample_data_shaping_out[120]\, - sample_data_shaping_out_119 => - \sample_data_shaping_out[121]\, - sample_data_shaping_out_120 => - \sample_data_shaping_out[122]\, - sample_data_shaping_out_121 => - \sample_data_shaping_out[123]\, - sample_data_shaping_out_122 => - \sample_data_shaping_out[124]\, - sample_data_shaping_out_123 => - \sample_data_shaping_out[125]\, - sample_data_shaping_out_126 => - \sample_data_shaping_out[128]\, - sample_data_shaping_out_127 => - \sample_data_shaping_out[129]\, - sample_data_shaping_out_128 => - \sample_data_shaping_out[130]\, - sample_data_shaping_out_129 => - \sample_data_shaping_out[131]\, - sample_data_shaping_out_130 => - \sample_data_shaping_out[132]\, - sample_data_shaping_out_131 => - \sample_data_shaping_out[133]\, - sample_data_shaping_out_132 => - \sample_data_shaping_out[134]\, - sample_data_shaping_out_133 => - \sample_data_shaping_out[135]\, - sample_data_shaping_out_134 => - \sample_data_shaping_out[136]\, - sample_data_shaping_out_135 => - \sample_data_shaping_out[137]\, - sample_data_shaping_out_136 => - \sample_data_shaping_out[138]\, - sample_data_shaping_out_137 => - \sample_data_shaping_out[139]\, - sample_data_shaping_out_138 => - \sample_data_shaping_out[140]\, - sample_data_shaping_out_139 => - \sample_data_shaping_out[141]\, - sample_data_shaping_out_140 => - \sample_data_shaping_out[142]\, - sample_data_shaping_out_141 => - \sample_data_shaping_out[143]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_data_shaping_out_val => - \sample_data_shaping_out_val\, sample_f0_val => - sample_f0_val, sample_data_shaping_out_val_0 => - \sample_data_shaping_out_val_0\, sample_f0_val_0 => - sample_f0_val_0, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - sample_f0_val_1 => sample_f0_val_1); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[51]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[51]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[51]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[141]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[141]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[141]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I95_Y_0 : - AX1D - port map(A => I92_un1_Y, B => N182_0, C => N183, Y => - \sample_data_shaping_f1_f0_s[2]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I37_Y : - XA1A - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[133]\, C => N197, Y => N216); - - \SampleLoop_data_shaping.1.sample_data_shaping_out_RNO[106]\ : - MX2 - port map(A => \sample_filter_v2_out[106]\, B => - \sample_data_shaping_f2_f1_s[1]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_41[106]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I49_Y : - AO1B - port map(A => N264_0, B => N216_0, C => - SUB_16x16_medium_area_I49_Y_0, Y => N244); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_0 : - AO18 - port map(A => N206_0, B => \sample_filter_v2_out[129]\, C - => \sample_filter_v2_out[111]\, Y => - SUB_16x16_medium_area_I57_Y_0_0); - - sample_data_shaping_out_val : DFN1C0 - port map(D => sample_filter_v2_out_val, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out_val\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out_RNO[125]\ : - AX1C - port map(A => \sample_filter_v2_out[143]\, B => - data_shaping_SP0, C => \sample_filter_v2_out[125]\, Y => - \sample_data_shaping_out_13[125]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I103_Y_0 : - AX1D - port map(A => I88_un1_Y, B => N198, C => N199, Y => - \sample_data_shaping_f2_f1_s[10]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I23_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, Y => N194); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[106]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_41[106]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[106]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[118]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_181[118]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[118]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I99_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[101]\, B => - \sample_filter_v2_out[119]\, C => N290_i, Y => - \sample_data_shaping_f2_f1_s[6]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[102]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_137[102]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[102]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I90_un1_Y : - OA1 - port map(A => I85_un1_Y, B => N274_0, C => N189, Y => - I90_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I46_Y : - OR2A - port map(A => \sample_filter_v2_out[125]\, B => - \sample_filter_v2_out[107]\, Y => N225); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[4]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[4]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[4]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[125]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_13[125]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[125]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I99_Y_0 : - AX1D - port map(A => I90_un1_Y, B => N190_0, C => N191, Y => - \sample_data_shaping_f1_f0_s[6]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I29_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[130]\, B => - \sample_filter_v2_out[112]\, Y => N205); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[6]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[6]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[6]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[69]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[69]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[69]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[25]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[25]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[25]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[121]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_109[121]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[121]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I90_Y : - AO18 - port map(A => N280, B => \sample_filter_v2_out[120]\, C => - \sample_filter_v2_out[102]\, Y => N290_i); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[94]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_329[94]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[94]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_1 : - OA1 - port map(A => N212_0, B => N254_0, C => - SUB_16x16_medium_area_I57_Y_0_0, Y => - SUB_16x16_medium_area_I57_Y_1_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I39_Y : - NOR2B - port map(A => N195_0, B => N193, Y => N265_0); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[53]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[53]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[53]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_0 : - AO18 - port map(A => N206, B => \sample_filter_v2_out[111]\, C => - \sample_filter_v2_out[93]\, Y => - SUB_16x16_medium_area_I57_Y_0); - - \SampleLoop_data_shaping.1.sample_data_shaping_out_RNO[124]\ : - MX2 - port map(A => \sample_filter_v2_out[124]\, B => - \sample_data_shaping_f1_f0_s[1]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_37[124]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I108_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_filter_v2_out[92]\, C => N240_0, Y => - \sample_data_shaping_f2_f1_s[15]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I94_Y_0 : - XOR2 - port map(A => N225, B => N181_0, Y => - \sample_data_shaping_f2_f1_s[1]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I29_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[112]\, B => - \sample_filter_v2_out[130]\, Y => N206_0); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[99]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_209[99]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[99]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I88_Y : - AO18 - port map(A => N270, B => \sample_filter_v2_out[134]\, C => - \sample_filter_v2_out[116]\, Y => N286_i); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[116]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_229[116]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[116]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I50_Y : - NOR2B - port map(A => N265, B => N216, Y => N245_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I24_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[117]\, B => - \sample_filter_v2_out[99]\, Y => N195_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I18_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[141]\, B => - \sample_filter_v2_out[123]\, Y => N183); - - \SampleLoop_data_shaping.6.sample_data_shaping_out_RNO[119]\ : - MX2 - port map(A => \sample_filter_v2_out[119]\, B => - \sample_data_shaping_f1_f0_s[6]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_157[119]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[139]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[139]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[139]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[70]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[70]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[70]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I27_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[114]\, B => - \sample_filter_v2_out[96]\, Y => N201_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[8]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[8]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[8]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[112]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_325[112]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[112]\); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[98]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_233[98]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[98]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[128]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[128]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[128]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y_0 : - AO18 - port map(A => N190, B => \sample_filter_v2_out[119]\, C => - \sample_filter_v2_out[101]\, Y => - SUB_16x16_medium_area_I56_Y_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[134]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[134]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[134]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I25_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[116]\, B => - \sample_filter_v2_out[98]\, Y => N197_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I29_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[112]\, B => - \sample_filter_v2_out[94]\, Y => N205_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I64_Y : - AO1 - port map(A => N268, B => N245_0, C => N244_0, Y => N258); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y : - AO1B - port map(A => SUB_16x16_medium_area_I57_un1_Y_0_0, B => - N268, C => SUB_16x16_medium_area_I57_Y_2_0, Y => N240); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[59]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[59]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[59]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I34_Y : - AO13 - port map(A => N202_0, B => \sample_filter_v2_out[95]\, C - => \sample_filter_v2_out[113]\, Y => N254); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[10]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[10]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[10]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I96_Y_0 : - XOR2 - port map(A => N278, B => N185, Y => - \sample_data_shaping_f1_f0_s[3]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I21_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[120]\, B => - \sample_filter_v2_out[138]\, Y => N190_0); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[40]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[40]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[40]\); - - Downsampling_f1 : Downsampling_8_16_6 - port map(sample_f0_0 => \sample_f0[48]\, sample_f0_1 => - \sample_f0[49]\, sample_f0_2 => \sample_f0[50]\, - sample_f0_3 => \sample_f0[51]\, sample_f0_4 => - \sample_f0[52]\, sample_f0_5 => \sample_f0[53]\, - sample_f0_6 => \sample_f0[54]\, sample_f0_7 => - \sample_f0[55]\, sample_f0_8 => \sample_f0[56]\, - sample_f0_9 => \sample_f0[57]\, sample_f0_10 => - \sample_f0[58]\, sample_f0_11 => \sample_f0[59]\, - sample_f0_12 => \sample_f0[60]\, sample_f0_13 => - \sample_f0[61]\, sample_f0_14 => \sample_f0[62]\, - sample_f0_15 => \sample_f0[63]\, sample_f0_32 => - \sample_f0[80]\, sample_f0_33 => \sample_f0[81]\, - sample_f0_34 => \sample_f0[82]\, sample_f0_35 => - \sample_f0[83]\, sample_f0_36 => \sample_f0[84]\, - sample_f0_37 => \sample_f0[85]\, sample_f0_38 => - \sample_f0[86]\, sample_f0_39 => \sample_f0[87]\, - sample_f0_40 => \sample_f0[88]\, sample_f0_41 => - \sample_f0[89]\, sample_f0_42 => \sample_f0[90]\, - sample_f0_43 => \sample_f0[91]\, sample_f0_44 => - \sample_f0[92]\, sample_f0_45 => \sample_f0[93]\, - sample_f0_46 => \sample_f0[94]\, sample_f0_47 => - \sample_f0[95]\, sample_f0_48 => \sample_f0[96]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_50 => - \sample_f0[98]\, sample_f0_51 => \sample_f0[99]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_53 => - \sample_f0[101]\, sample_f0_54 => \sample_f0[102]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_56 => - \sample_f0[104]\, sample_f0_57 => \sample_f0[105]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_59 => - \sample_f0[107]\, sample_f0_60 => \sample_f0[108]\, - sample_f0_61 => \sample_f0[109]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_63 => \sample_f0[111]\, - sample_f1_0 => \sample_f1[48]\, sample_f1_1 => - \sample_f1[49]\, sample_f1_2 => \sample_f1[50]\, - sample_f1_3 => \sample_f1[51]\, sample_f1_4 => - \sample_f1[52]\, sample_f1_5 => \sample_f1[53]\, - sample_f1_6 => \sample_f1[54]\, sample_f1_7 => - \sample_f1[55]\, sample_f1_8 => \sample_f1[56]\, - sample_f1_9 => \sample_f1[57]\, sample_f1_10 => - \sample_f1[58]\, sample_f1_11 => \sample_f1[59]\, - sample_f1_12 => \sample_f1[60]\, sample_f1_13 => - \sample_f1[61]\, sample_f1_14 => \sample_f1[62]\, - sample_f1_15 => \sample_f1[63]\, sample_f1_32 => - \sample_f1[80]\, sample_f1_33 => \sample_f1[81]\, - sample_f1_34 => \sample_f1[82]\, sample_f1_35 => - \sample_f1[83]\, sample_f1_36 => \sample_f1[84]\, - sample_f1_37 => \sample_f1[85]\, sample_f1_38 => - \sample_f1[86]\, sample_f1_39 => \sample_f1[87]\, - sample_f1_40 => \sample_f1[88]\, sample_f1_41 => - \sample_f1[89]\, sample_f1_42 => \sample_f1[90]\, - sample_f1_43 => \sample_f1[91]\, sample_f1_44 => - \sample_f1[92]\, sample_f1_45 => \sample_f1[93]\, - sample_f1_46 => \sample_f1[94]\, sample_f1_47 => - \sample_f1[95]\, sample_f1_48 => \sample_f1[96]\, - sample_f1_49 => \sample_f1[97]\, sample_f1_50 => - \sample_f1[98]\, sample_f1_51 => \sample_f1[99]\, - sample_f1_52 => \sample_f1[100]\, sample_f1_53 => - \sample_f1[101]\, sample_f1_54 => \sample_f1[102]\, - sample_f1_55 => \sample_f1[103]\, sample_f1_56 => - \sample_f1[104]\, sample_f1_57 => \sample_f1[105]\, - sample_f1_58 => \sample_f1[106]\, sample_f1_59 => - \sample_f1[107]\, sample_f1_60 => \sample_f1[108]\, - sample_f1_61 => \sample_f1[109]\, sample_f1_62 => - \sample_f1[110]\, sample_f1_63 => \sample_f1[111]\, - sample_f0_wdata_95 => \sample_f0_wdata[95]\, - sample_f0_wdata_94 => \sample_f0_wdata[94]\, - sample_f0_wdata_93 => \sample_f0_wdata[93]\, - sample_f0_wdata_92 => \sample_f0_wdata[92]\, - sample_f0_wdata_91 => \sample_f0_wdata[91]\, - sample_f0_wdata_90 => \sample_f0_wdata[90]\, - sample_f0_wdata_89 => \sample_f0_wdata[89]\, - sample_f0_wdata_88 => \sample_f0_wdata[88]\, - sample_f0_wdata_87 => \sample_f0_wdata[87]\, - sample_f0_wdata_86 => \sample_f0_wdata[86]\, - sample_f0_wdata_85 => \sample_f0_wdata[85]\, - sample_f0_wdata_84 => \sample_f0_wdata[84]\, - sample_f0_wdata_83 => \sample_f0_wdata[83]\, - sample_f0_wdata_82 => \sample_f0_wdata[82]\, - sample_f0_wdata_81 => \sample_f0_wdata[81]\, - sample_f0_wdata_80 => \sample_f0_wdata[80]\, - sample_f0_wdata_79 => \sample_f0_wdata[79]\, - sample_f0_wdata_78 => \sample_f0_wdata[78]\, - sample_f0_wdata_77 => \sample_f0_wdata[77]\, - sample_f0_wdata_76 => \sample_f0_wdata[76]\, - sample_f0_wdata_75 => \sample_f0_wdata[75]\, - sample_f0_wdata_74 => \sample_f0_wdata[74]\, - sample_f0_wdata_73 => \sample_f0_wdata[73]\, - sample_f0_wdata_72 => \sample_f0_wdata[72]\, - sample_f0_wdata_71 => \sample_f0_wdata[71]\, - sample_f0_wdata_70 => \sample_f0_wdata[70]\, - sample_f0_wdata_69 => \sample_f0_wdata[69]\, - sample_f0_wdata_68 => \sample_f0_wdata[68]\, - sample_f0_wdata_67 => \sample_f0_wdata[67]\, - sample_f0_wdata_66 => \sample_f0_wdata[66]\, - sample_f0_wdata_65 => \sample_f0_wdata[65]\, - sample_f0_wdata_64 => \sample_f0_wdata[64]\, - sample_f0_wdata_63 => \sample_f0_wdata[63]\, - sample_f0_wdata_62 => \sample_f0_wdata[62]\, - sample_f0_wdata_61 => \sample_f0_wdata[61]\, - sample_f0_wdata_60 => \sample_f0_wdata[60]\, - sample_f0_wdata_59 => \sample_f0_wdata[59]\, - sample_f0_wdata_58 => \sample_f0_wdata[58]\, - sample_f0_wdata_57 => \sample_f0_wdata[57]\, - sample_f0_wdata_56 => \sample_f0_wdata[56]\, - sample_f0_wdata_55 => \sample_f0_wdata[55]\, - sample_f0_wdata_54 => \sample_f0_wdata[54]\, - sample_f0_wdata_53 => \sample_f0_wdata[53]\, - sample_f0_wdata_52 => \sample_f0_wdata[52]\, - sample_f0_wdata_51 => \sample_f0_wdata[51]\, - sample_f0_wdata_50 => \sample_f0_wdata[50]\, - sample_f0_wdata_49 => \sample_f0_wdata[49]\, - sample_f0_wdata_48 => \sample_f0_wdata[48]\, - sample_f0_wdata_15 => \sample_f0_wdata[15]\, - sample_f0_wdata_14 => \sample_f0_wdata[14]\, - sample_f0_wdata_13 => \sample_f0_wdata[13]\, - sample_f0_wdata_12 => \sample_f0_wdata[12]\, - sample_f0_wdata_11 => \sample_f0_wdata[11]\, - sample_f0_wdata_10 => \sample_f0_wdata[10]\, - sample_f0_wdata_9 => \sample_f0_wdata[9]\, - sample_f0_wdata_8 => \sample_f0_wdata[8]\, - sample_f0_wdata_7 => \sample_f0_wdata[7]\, - sample_f0_wdata_6 => \sample_f0_wdata[6]\, - sample_f0_wdata_5 => \sample_f0_wdata[5]\, - sample_f0_wdata_4 => \sample_f0_wdata[4]\, - sample_f0_wdata_3 => \sample_f0_wdata[3]\, - sample_f0_wdata_2 => \sample_f0_wdata[2]\, - sample_f0_wdata_1 => \sample_f0_wdata[1]\, - sample_f0_wdata_0 => \sample_f0_wdata[0]\, - sample_f1_wdata_95 => \sample_f1_wdata[95]\, - sample_f1_wdata_94 => \sample_f1_wdata[94]\, - sample_f1_wdata_93 => \sample_f1_wdata[93]\, - sample_f1_wdata_92 => \sample_f1_wdata[92]\, - sample_f1_wdata_91 => \sample_f1_wdata[91]\, - sample_f1_wdata_90 => \sample_f1_wdata[90]\, - sample_f1_wdata_89 => \sample_f1_wdata[89]\, - sample_f1_wdata_88 => \sample_f1_wdata[88]\, - sample_f1_wdata_87 => \sample_f1_wdata[87]\, - sample_f1_wdata_86 => \sample_f1_wdata[86]\, - sample_f1_wdata_85 => \sample_f1_wdata[85]\, - sample_f1_wdata_84 => \sample_f1_wdata[84]\, - sample_f1_wdata_83 => \sample_f1_wdata[83]\, - sample_f1_wdata_82 => \sample_f1_wdata[82]\, - sample_f1_wdata_81 => \sample_f1_wdata[81]\, - sample_f1_wdata_80 => \sample_f1_wdata[80]\, - sample_f1_wdata_79 => \sample_f1_wdata[79]\, - sample_f1_wdata_78 => \sample_f1_wdata[78]\, - sample_f1_wdata_77 => \sample_f1_wdata[77]\, - sample_f1_wdata_76 => \sample_f1_wdata[76]\, - sample_f1_wdata_75 => \sample_f1_wdata[75]\, - sample_f1_wdata_74 => \sample_f1_wdata[74]\, - sample_f1_wdata_73 => \sample_f1_wdata[73]\, - sample_f1_wdata_72 => \sample_f1_wdata[72]\, - sample_f1_wdata_71 => \sample_f1_wdata[71]\, - sample_f1_wdata_70 => \sample_f1_wdata[70]\, - sample_f1_wdata_69 => \sample_f1_wdata[69]\, - sample_f1_wdata_68 => \sample_f1_wdata[68]\, - sample_f1_wdata_67 => \sample_f1_wdata[67]\, - sample_f1_wdata_66 => \sample_f1_wdata[66]\, - sample_f1_wdata_65 => \sample_f1_wdata[65]\, - sample_f1_wdata_64 => \sample_f1_wdata[64]\, - sample_f1_wdata_63 => \sample_f1_wdata[63]\, - sample_f1_wdata_62 => \sample_f1_wdata[62]\, - sample_f1_wdata_61 => \sample_f1_wdata[61]\, - sample_f1_wdata_60 => \sample_f1_wdata[60]\, - sample_f1_wdata_59 => \sample_f1_wdata[59]\, - sample_f1_wdata_58 => \sample_f1_wdata[58]\, - sample_f1_wdata_57 => \sample_f1_wdata[57]\, - sample_f1_wdata_56 => \sample_f1_wdata[56]\, - sample_f1_wdata_55 => \sample_f1_wdata[55]\, - sample_f1_wdata_54 => \sample_f1_wdata[54]\, - sample_f1_wdata_53 => \sample_f1_wdata[53]\, - sample_f1_wdata_52 => \sample_f1_wdata[52]\, - sample_f1_wdata_51 => \sample_f1_wdata[51]\, - sample_f1_wdata_50 => \sample_f1_wdata[50]\, - sample_f1_wdata_49 => \sample_f1_wdata[49]\, - sample_f1_wdata_48 => \sample_f1_wdata[48]\, - sample_f1_wdata_15 => \sample_f1_wdata[15]\, - sample_f1_wdata_14 => \sample_f1_wdata[14]\, - sample_f1_wdata_13 => \sample_f1_wdata[13]\, - sample_f1_wdata_12 => \sample_f1_wdata[12]\, - sample_f1_wdata_11 => \sample_f1_wdata[11]\, - sample_f1_wdata_10 => \sample_f1_wdata[10]\, - sample_f1_wdata_9 => \sample_f1_wdata[9]\, - sample_f1_wdata_8 => \sample_f1_wdata[8]\, - sample_f1_wdata_7 => \sample_f1_wdata[7]\, - sample_f1_wdata_6 => \sample_f1_wdata[6]\, - sample_f1_wdata_5 => \sample_f1_wdata[5]\, - sample_f1_wdata_4 => \sample_f1_wdata[4]\, - sample_f1_wdata_3 => \sample_f1_wdata[3]\, - sample_f1_wdata_2 => \sample_f1_wdata[2]\, - sample_f1_wdata_1 => \sample_f1_wdata[1]\, - sample_f1_wdata_0 => \sample_f1_wdata[0]\, - sample_f0_val_1 => sample_f0_val_1, sample_f1_val => - sample_f1_val, sample_f0_val_0 => sample_f0_val_0, - sample_out_0_sqmuxa_1 => sample_out_0_sqmuxa_1, HRESETn_c - => HRESETn_c, HCLK_c => HCLK_c, sample_f1_val_0 => - sample_f1_val_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out_RNO[100]\ : - MX2 - port map(A => \sample_filter_v2_out[100]\, B => - \sample_data_shaping_f2_f1_s[7]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_185[100]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I49_Y : - AO1B - port map(A => N264, B => N216, C => - SUB_16x16_medium_area_I49_Y_0_0, Y => N244_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I23_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[100]\, Y => N193); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I41_Y : - XA1A - port map(A => \sample_filter_v2_out[101]\, B => - \sample_filter_v2_out[119]\, C => N189_0, Y => N220); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y : - AO1B - port map(A => SUB_16x16_medium_area_I57_un1_Y_0, B => - N268_0, C => SUB_16x16_medium_area_I57_Y_2, Y => N240_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I17_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[142]\, B => - \sample_filter_v2_out[124]\, Y => N181); - - \SampleLoop_data_shaping.9.sample_data_shaping_out_RNO[98]\ : - MX2 - port map(A => \sample_filter_v2_out[98]\, B => - \sample_data_shaping_f2_f1_s[9]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_233[98]\); - - sample_data_shaping_out_val_0 : DFN1C0 - port map(D => sample_filter_v2_out_val, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out_val_0\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I38_Y : - AO13 - port map(A => N194, B => \sample_filter_v2_out[117]\, C => - \sample_filter_v2_out[135]\, Y => N264); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[41]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[41]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[41]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[140]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[140]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[140]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out_RNO[105]\ : - MX2 - port map(A => \sample_filter_v2_out[105]\, B => - \sample_data_shaping_f2_f1_s[2]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_65[105]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_1 : - AOI1B - port map(A => N254, B => N212, C => - SUB_16x16_medium_area_I57_Y_0, Y => - SUB_16x16_medium_area_I57_Y_1); - - \SampleLoop_data_shaping.5.sample_data_shaping_out_RNO[102]\ : - MX2 - port map(A => \sample_filter_v2_out[102]\, B => - \sample_data_shaping_f2_f1_s[5]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_137[102]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_2 : - AOI1B - port map(A => N244_0, B => N229_0, C => - SUB_16x16_medium_area_I57_Y_1_0, Y => - SUB_16x16_medium_area_I57_Y_2_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[39]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[39]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[39]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[130]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[130]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[130]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I97_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I91_un1_Y_0, B => - N186_0, C => N187_0, Y => - \sample_data_shaping_f2_f1_s[4]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I21_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[120]\, B => - \sample_filter_v2_out[102]\, Y => N189_0); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[63]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[63]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[63]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[101]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_161[101]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[101]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I106_Y_0 : - XOR2 - port map(A => N260, B => N205, Y => - \sample_data_shaping_f1_f0_s[13]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[45]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[45]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[45]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[123]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_61[123]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[123]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[24]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[24]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[24]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out_RNO[122]\ : - MX2 - port map(A => \sample_filter_v2_out[122]\, B => - \sample_data_shaping_f1_f0_s[3]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_85[122]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[115]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_253[115]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[115]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[43]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[43]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[43]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I78_un1_Y : - NOR2B - port map(A => N268_0, B => N265_0, Y => I78_un1_Y); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[60]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[60]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[60]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I42_Y : - AO13 - port map(A => N186, B => \sample_filter_v2_out[121]\, C => - \sample_filter_v2_out[139]\, Y => N274_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[64]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[64]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[64]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[133]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[133]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[133]\); - - GND_i_0 : GND - port map(Y => GND_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_2 : - AOI1B - port map(A => N244, B => N229, C => - SUB_16x16_medium_area_I57_Y_1, Y => - SUB_16x16_medium_area_I57_Y_2); - - \SampleLoop_data_shaping.4.sample_data_shaping_out_RNO[121]\ : - MX2 - port map(A => \sample_filter_v2_out[121]\, B => - \sample_data_shaping_f1_f0_s[4]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_109[121]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[142]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[142]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[142]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I96_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, C => N278_0, Y => - \sample_data_shaping_f2_f1_s[3]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_un1_Y : - OR3C - port map(A => N225_0, B => N183, C => N181, Y => I53_un1_Y); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[14]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[14]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[14]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out_RNO[99]\ : - MX2 - port map(A => \sample_filter_v2_out[99]\, B => - \sample_data_shaping_f2_f1_s[8]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_209[99]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I101_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I89_un1_Y, B => N194_0, - C => N195_0, Y => \sample_data_shaping_f2_f1_s[8]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out_RNO[118]\ : - MX2 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_data_shaping_f1_f0_s[7]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_181[118]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I103_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[133]\, C => N286_i, Y => - \sample_data_shaping_f1_f0_s[10]\); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[93]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_353[93]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[93]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I92_un1_Y : - NOR2B - port map(A => N225_0, B => N181, Y => I92_un1_Y); - - \SampleLoop_data_shaping.8.sample_data_shaping_out_RNO[117]\ : - MX2 - port map(A => \sample_filter_v2_out[117]\, B => - \sample_data_shaping_f1_f0_s[8]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_205[117]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out_RNO[112]\ : - MX2 - port map(A => \sample_filter_v2_out[112]\, B => - \sample_data_shaping_f1_f0_s[13]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_325[112]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_Y_0 : - AO18 - port map(A => N182, B => \sample_filter_v2_out[123]\, C => - \sample_filter_v2_out[105]\, Y => - SUB_16x16_medium_area_I53_Y_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[114]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_277[114]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[114]\); - - DIGITAL_acquisition : AD7688_drvr - port map(sample_7(15) => \sample_7[15]\, sample_7(14) => - \sample_7[14]\, sample_7(13) => \sample_7[13]\, - sample_7(12) => \sample_7[12]\, sample_7(11) => - \sample_7[11]\, sample_7(10) => \sample_7[10]\, - sample_7(9) => \sample_7[9]\, sample_7(8) => - \sample_7[8]\, sample_7(7) => \sample_7[7]\, sample_7(6) - => \sample_7[6]\, sample_7(5) => \sample_7[5]\, - sample_7(4) => \sample_7[4]\, sample_7(3) => - \sample_7[3]\, sample_7(2) => \sample_7[2]\, sample_7(1) - => \sample_7[1]\, sample_7(0) => \sample_7[0]\, - sample_0(15) => \sample_0[15]\, sample_0(14) => - \sample_0[14]\, sample_0(13) => \sample_0[13]\, - sample_0(12) => \sample_0[12]\, sample_0(11) => - \sample_0[11]\, sample_0(10) => \sample_0[10]\, - sample_0(9) => \sample_0[9]\, sample_0(8) => - \sample_0[8]\, sample_0(7) => \sample_0[7]\, sample_0(6) - => \sample_0[6]\, sample_0(5) => \sample_0[5]\, - sample_0(4) => \sample_0[4]\, sample_0(3) => - \sample_0[3]\, sample_0(2) => \sample_0[2]\, sample_0(1) - => \sample_0[1]\, sample_0(0) => \sample_0[0]\, - sample_1(15) => \sample_1[15]\, sample_1(14) => - \sample_1[14]\, sample_1(13) => \sample_1[13]\, - sample_1(12) => \sample_1[12]\, sample_1(11) => - \sample_1[11]\, sample_1(10) => \sample_1[10]\, - sample_1(9) => \sample_1[9]\, sample_1(8) => - \sample_1[8]\, sample_1(7) => \sample_1[7]\, sample_1(6) - => \sample_1[6]\, sample_1(5) => \sample_1[5]\, - sample_1(4) => \sample_1[4]\, sample_1(3) => - \sample_1[3]\, sample_1(2) => \sample_1[2]\, sample_1(1) - => \sample_1[1]\, sample_1(0) => \sample_1[0]\, - sample_2(15) => \sample_2[15]\, sample_2(14) => - \sample_2[14]\, sample_2(13) => \sample_2[13]\, - sample_2(12) => \sample_2[12]\, sample_2(11) => - \sample_2[11]\, sample_2(10) => \sample_2[10]\, - sample_2(9) => \sample_2[9]\, sample_2(8) => - \sample_2[8]\, sample_2(7) => \sample_2[7]\, sample_2(6) - => \sample_2[6]\, sample_2(5) => \sample_2[5]\, - sample_2(4) => \sample_2[4]\, sample_2(3) => - \sample_2[3]\, sample_2(2) => \sample_2[2]\, sample_2(1) - => \sample_2[1]\, sample_2(0) => \sample_2[0]\, - sample_3(15) => \sample_3[15]\, sample_3(14) => - \sample_3[14]\, sample_3(13) => \sample_3[13]\, - sample_3(12) => \sample_3[12]\, sample_3(11) => - \sample_3[11]\, sample_3(10) => \sample_3[10]\, - sample_3(9) => \sample_3[9]\, sample_3(8) => - \sample_3[8]\, sample_3(7) => \sample_3[7]\, sample_3(6) - => \sample_3[6]\, sample_3(5) => \sample_3[5]\, - sample_3(4) => \sample_3[4]\, sample_3(3) => - \sample_3[3]\, sample_3(2) => \sample_3[2]\, sample_3(1) - => \sample_3[1]\, sample_3(0) => \sample_3[0]\, - sample_4(15) => \sample_4[15]\, sample_4(14) => - \sample_4[14]\, sample_4(13) => \sample_4[13]\, - sample_4(12) => \sample_4[12]\, sample_4(11) => - \sample_4[11]\, sample_4(10) => \sample_4[10]\, - sample_4(9) => \sample_4[9]\, sample_4(8) => - \sample_4[8]\, sample_4(7) => \sample_4[7]\, sample_4(6) - => \sample_4[6]\, sample_4(5) => \sample_4[5]\, - sample_4(4) => \sample_4[4]\, sample_4(3) => - \sample_4[3]\, sample_4(2) => \sample_4[2]\, sample_4(1) - => \sample_4[1]\, sample_4(0) => \sample_4[0]\, - sample_5(15) => \sample_5[15]\, sample_5(14) => - \sample_5[14]\, sample_5(13) => \sample_5[13]\, - sample_5(12) => \sample_5[12]\, sample_5(11) => - \sample_5[11]\, sample_5(10) => \sample_5[10]\, - sample_5(9) => \sample_5[9]\, sample_5(8) => - \sample_5[8]\, sample_5(7) => \sample_5[7]\, sample_5(6) - => \sample_5[6]\, sample_5(5) => \sample_5[5]\, - sample_5(4) => \sample_5[4]\, sample_5(3) => - \sample_5[3]\, sample_5(2) => \sample_5[2]\, sample_5(1) - => \sample_5[1]\, sample_5(0) => \sample_5[0]\, sdo_c(7) - => sdo_c(7), sdo_c(6) => sdo_c(6), sdo_c(5) => sdo_c(5), - sdo_c(4) => sdo_c(4), sdo_c(3) => sdo_c(3), sdo_c(2) => - sdo_c(2), sdo_c(1) => sdo_c(1), sdo_c(0) => sdo_c(0), - sample_6(15) => \sample_6[15]\, sample_6(14) => - \sample_6[14]\, sample_6(13) => \sample_6[13]\, - sample_6(12) => \sample_6[12]\, sample_6(11) => - \sample_6[11]\, sample_6(10) => \sample_6[10]\, - sample_6(9) => \sample_6[9]\, sample_6(8) => - \sample_6[8]\, sample_6(7) => \sample_6[7]\, sample_6(6) - => \sample_6[6]\, sample_6(5) => \sample_6[5]\, - sample_6(4) => \sample_6[4]\, sample_6(3) => - \sample_6[3]\, sample_6(2) => \sample_6[2]\, sample_6(1) - => \sample_6[1]\, sample_6(0) => \sample_6[0]\, - cnv_rstn_c => cnv_rstn_c, cnv_clk_c => cnv_clk_c, cnv_c - => cnv_c, sample_val => sample_val, sck_c => sck_c, - cnv_run_c => cnv_run_c, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c); - - \SampleLoop_data_shaping.10.sample_data_shaping_out_RNO[97]\ : - MX2 - port map(A => \sample_filter_v2_out[97]\, B => - \sample_data_shaping_f2_f1_s[10]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_257[97]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[96]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_281[96]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[96]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I20_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[139]\, B => - \sample_filter_v2_out[121]\, Y => N187); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I19_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[122]\, B => - \sample_filter_v2_out[140]\, Y => N186); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[62]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[62]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[62]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I43_Y : - XA1A - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, C => N187_0, Y => N275_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I48_Y : - NOR2 - port map(A => N255, B => N212_0, Y => N229_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I35_Y : - XAI1A - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[131]\, C => N201, Y => N255); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I41_Y : - NOR2B - port map(A => N191, B => N189, Y => N220_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[42]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[42]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[42]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[71]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[71]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[71]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I27_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[132]\, B => - \sample_filter_v2_out[114]\, Y => N201); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I17_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[106]\, B => - \sample_filter_v2_out[124]\, Y => N182); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[52]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[52]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[52]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I30_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[93]\, Y => N207); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[34]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[34]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[34]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_un1_Y : - OR3C - port map(A => N275_0, B => N220, C => N278_0, Y => - I56_un1_Y); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I64_un1_Y : - OR2B - port map(A => N268_0, B => N245, Y => I64_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I25_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[98]\, B => - \sample_filter_v2_out[116]\, Y => N198); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I25_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[116]\, B => - \sample_filter_v2_out[134]\, Y => N198_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I27_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[114]\, B => - \sample_filter_v2_out[132]\, Y => N202); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[111]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_349[111]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[111]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[9]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[9]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[9]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I105_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I87_un1_Y, B => N202_0, - C => N203, Y => \sample_data_shaping_f2_f1_s[12]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[7]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[7]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[7]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[48]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[48]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[48]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[132]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[132]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[132]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[31]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[31]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[31]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[16]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[16]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[16]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I33_Y : - NOR2B - port map(A => N207, B => N205_0, Y => N212); - - \SampleLoop_data_shaping.11.sample_data_shaping_out_RNO[114]\ : - MX2 - port map(A => \sample_filter_v2_out[114]\, B => - \sample_data_shaping_f1_f0_s[11]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_277[114]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I86_un1_Y : - OA1 - port map(A => I71_un1_Y, B => N254, C => N205_0, Y => - I86_un1_Y); - - \SampleLoop_data_shaping.12.sample_data_shaping_out_RNO[113]\ : - MX2 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_data_shaping_f1_f0_s[12]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_301[113]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[50]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[50]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[50]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out_RNO[94]\ : - MX2 - port map(A => \sample_filter_v2_out[94]\, B => - \sample_data_shaping_f2_f1_s[13]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_329[94]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[2]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[2]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[2]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[66]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[66]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[66]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[124]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_37[124]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[124]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I19_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, Y => N186_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I25_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[134]\, B => - \sample_filter_v2_out[116]\, Y => N197); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y : - OR2B - port map(A => SUB_16x16_medium_area_I56_Y_1, B => I56_un1_Y, - Y => N268_0); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[5]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[5]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[5]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[105]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_65[105]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[105]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I104_Y_0 : - AX1A - port map(A => N244, B => I64_un1_Y, C => N201_0, Y => - \sample_data_shaping_f2_f1_s[11]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[92]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_377[92]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[92]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I89_un1_Y : - NOR2B - port map(A => N268_0, B => N193, Y => - SUB_16x16_medium_area_I89_un1_Y); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[44]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[44]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[44]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y_0 : - AO18 - port map(A => N190_0, B => \sample_filter_v2_out[137]\, C - => \sample_filter_v2_out[119]\, Y => - SUB_16x16_medium_area_I56_Y_0_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[21]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[21]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[21]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I35_Y : - NOR2B - port map(A => N203, B => N201_0, Y => N255_0); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[38]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[38]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[38]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y_1 : - AOI1B - port map(A => N274, B => N220, C => - SUB_16x16_medium_area_I56_Y_0, Y => - SUB_16x16_medium_area_I56_Y_1); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I50_Y : - NOR2B - port map(A => N265_0, B => N216_0, Y => N245); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_un1_Y_0 : - NOR2B - port map(A => N220_0, B => N275, Y => - SUB_16x16_medium_area_I56_un1_Y_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[100]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_185[100]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[100]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I98_Y_0 : - XOR2 - port map(A => N280, B => N189_0, Y => - \sample_data_shaping_f2_f1_s[5]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[95]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_305[95]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[95]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[65]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[65]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[65]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out_RNO[92]\ : - MX2 - port map(A => \sample_filter_v2_out[92]\, B => - \sample_data_shaping_f2_f1_s[15]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_377[92]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[131]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[131]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[131]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[22]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[22]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[22]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I91_un1_Y : - NOR2B - port map(A => N278, B => N185, Y => - SUB_16x16_medium_area_I91_un1_Y); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_Y_0 : - AO18 - port map(A => N182_0, B => \sample_filter_v2_out[141]\, C - => \sample_filter_v2_out[123]\, Y => - SUB_16x16_medium_area_I53_Y_0_0); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[12]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[12]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[12]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I23_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, Y => N194_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I97_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I91_un1_Y, B => N186, C - => N187, Y => \sample_data_shaping_f1_f0_s[4]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I100_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N268, Y => - \sample_data_shaping_f1_f0_s[7]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_lfr_wf_picker is - - port( cnv_run : in std_logic; - cnv : out std_logic; - sck : out std_logic; - sdo : in std_logic_vector(7 downto 0); - cnv_clk : in std_logic; - cnv_rstn : in std_logic; - HCLK : in std_logic; - HRESETn : in std_logic; - apbi : in std_logic_vector(121 downto 0); - apbo : out std_logic_vector(131 downto 0); - AHB_Master_In : in std_logic_vector(90 downto 0); - AHB_Master_Out : out std_logic_vector(370 downto 0); - coarse_time_0 : in std_logic; - data_shaping_BW : out std_logic - ); - -end lpp_top_lfr_wf_picker; - -architecture DEF_ARCH of lpp_top_lfr_wf_picker is - - component OUTBUF - port( D : in std_logic := 'U'; - PAD : out std_logic - ); - end component; - - component INBUF - port( PAD : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component lpp_top_apbreg - port( status_full_ack : out std_logic_vector(3 downto 0); - prdata_c : out std_logic_vector(31 downto 0); - pirq_c : out std_logic_vector(15 to 15); - addr_data_f2 : out std_logic_vector(31 downto 0); - status_new_err_3 : in std_logic := 'U'; - status_new_err_0_2 : in std_logic := 'U'; - status_new_err_0_0 : in std_logic := 'U'; - status_new_err_0_1 : in std_logic := 'U'; - status_full_err_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - status_full : in std_logic_vector(3 downto 0) := (others => 'U'); - addr_data_f3 : out std_logic_vector(31 downto 0); - nb_burst_available : out std_logic_vector(10 downto 0); - addr_data_f1 : out std_logic_vector(31 downto 0); - delta_f2_f1 : out std_logic_vector(9 downto 0); - addr_data_f0 : out std_logic_vector(31 downto 0); - delta_f2_f0 : out std_logic_vector(9 downto 0); - delta_snapshot : out std_logic_vector(15 downto 0); - nb_snapshot_param : out std_logic_vector(10 downto 0); - apbi_c_81 : in std_logic := 'U'; - apbi_c_80 : in std_logic := 'U'; - apbi_c_79 : in std_logic := 'U'; - apbi_c_78 : in std_logic := 'U'; - apbi_c_77 : in std_logic := 'U'; - apbi_c_76 : in std_logic := 'U'; - apbi_c_75 : in std_logic := 'U'; - apbi_c_74 : in std_logic := 'U'; - apbi_c_73 : in std_logic := 'U'; - apbi_c_72 : in std_logic := 'U'; - apbi_c_71 : in std_logic := 'U'; - apbi_c_70 : in std_logic := 'U'; - apbi_c_69 : in std_logic := 'U'; - apbi_c_68 : in std_logic := 'U'; - apbi_c_67 : in std_logic := 'U'; - apbi_c_66 : in std_logic := 'U'; - apbi_c_65 : in std_logic := 'U'; - apbi_c_64 : in std_logic := 'U'; - apbi_c_63 : in std_logic := 'U'; - apbi_c_62 : in std_logic := 'U'; - apbi_c_61 : in std_logic := 'U'; - apbi_c_60 : in std_logic := 'U'; - apbi_c_59 : in std_logic := 'U'; - apbi_c_58 : in std_logic := 'U'; - apbi_c_57 : in std_logic := 'U'; - apbi_c_56 : in std_logic := 'U'; - apbi_c_55 : in std_logic := 'U'; - apbi_c_24 : in std_logic := 'U'; - apbi_c_23 : in std_logic := 'U'; - apbi_c_0 : in std_logic := 'U'; - apbi_c_50 : in std_logic := 'U'; - apbi_c_51 : in std_logic := 'U'; - apbi_c_52 : in std_logic := 'U'; - apbi_c_16 : in std_logic := 'U'; - apbi_c_49 : in std_logic := 'U'; - apbi_c_22 : in std_logic := 'U'; - apbi_c_20 : in std_logic := 'U'; - apbi_c_19 : in std_logic := 'U'; - apbi_c_21 : in std_logic := 'U'; - apbi_c_54 : in std_logic := 'U'; - apbi_c_53 : in std_logic := 'U'; - data_shaping_R0 : out std_logic; - data_shaping_R1 : out std_logic; - enable_f0 : out std_logic; - data_shaping_BW_c : out std_logic; - burst_f2 : out std_logic; - burst_f1 : out std_logic; - burst_f0 : out std_logic; - enable_f3 : out std_logic; - enable_f2 : out std_logic; - data_shaping_SP1 : out std_logic; - enable_f1 : out std_logic; - data_shaping_SP0 : out std_logic; - data_shaping_R1_0 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_shaping_R0_0 : out std_logic - ); - end component; - - component lpp_top_lfr_wf_picker_ip - port( nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - status_new_err : out std_logic_vector(3 downto 0); - hwdata_c : out std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - haddr_c : out std_logic_vector(31 downto 0); - AHB_Master_In_c_3 : in std_logic := 'U'; - AHB_Master_In_c_0 : in std_logic := 'U'; - AHB_Master_In_c_4 : in std_logic := 'U'; - AHB_Master_In_c_5 : in std_logic := 'U'; - hsize_c : out std_logic_vector(1 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - sdo_c : in std_logic_vector(7 downto 0) := (others => 'U'); - coarse_time_0_c : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - data_shaping_R0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - enable_f3 : in std_logic := 'U'; - N_43 : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - hwrite_c : out std_logic; - lpp_top_lfr_wf_picker_ip_GND : in std_logic := 'U'; - lpp_top_lfr_wf_picker_ip_VCC : in std_logic := 'U'; - cnv_run_c : in std_logic := 'U'; - sck_c : out std_logic; - cnv_c : out std_logic; - cnv_clk_c : in std_logic := 'U'; - cnv_rstn_c : in std_logic := 'U'; - data_shaping_SP0 : in std_logic := 'U'; - data_shaping_SP1 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component CLKBUF - port( PAD : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \status_full[0]\, \status_full[1]\, \status_full[2]\, - \status_full[3]\, \status_full_ack[0]\, - \status_full_ack[1]\, \status_full_ack[2]\, - \status_full_ack[3]\, \status_full_err[0]\, - \status_full_err[1]\, \status_full_err[2]\, - \status_full_err[3]\, \status_new_err[0]\, - \status_new_err[1]\, \status_new_err[2]\, - \status_new_err[3]\, data_shaping_SP0, data_shaping_SP1, - data_shaping_R0, data_shaping_R1, \delta_snapshot[0]\, - \delta_snapshot[1]\, \delta_snapshot[2]\, - \delta_snapshot[3]\, \delta_snapshot[4]\, - \delta_snapshot[5]\, \delta_snapshot[6]\, - \delta_snapshot[7]\, \delta_snapshot[8]\, - \delta_snapshot[9]\, \delta_snapshot[10]\, - \delta_snapshot[11]\, \delta_snapshot[12]\, - \delta_snapshot[13]\, \delta_snapshot[14]\, - \delta_snapshot[15]\, \delta_f2_f1[0]\, \delta_f2_f1[1]\, - \delta_f2_f1[2]\, \delta_f2_f1[3]\, \delta_f2_f1[4]\, - \delta_f2_f1[5]\, \delta_f2_f1[6]\, \delta_f2_f1[7]\, - \delta_f2_f1[8]\, \delta_f2_f1[9]\, \delta_f2_f0[0]\, - \delta_f2_f0[1]\, \delta_f2_f0[2]\, \delta_f2_f0[3]\, - \delta_f2_f0[4]\, \delta_f2_f0[5]\, \delta_f2_f0[6]\, - \delta_f2_f0[7]\, \delta_f2_f0[8]\, \delta_f2_f0[9]\, - \nb_burst_available[0]\, \nb_burst_available[1]\, - \nb_burst_available[2]\, \nb_burst_available[3]\, - \nb_burst_available[4]\, \nb_burst_available[5]\, - \nb_burst_available[6]\, \nb_burst_available[7]\, - \nb_burst_available[8]\, \nb_burst_available[9]\, - \nb_burst_available[10]\, \nb_snapshot_param[0]\, - \nb_snapshot_param[1]\, \nb_snapshot_param[2]\, - \nb_snapshot_param[3]\, \nb_snapshot_param[4]\, - \nb_snapshot_param[5]\, \nb_snapshot_param[6]\, - \nb_snapshot_param[7]\, \nb_snapshot_param[8]\, - \nb_snapshot_param[9]\, \nb_snapshot_param[10]\, - enable_f0, enable_f1, enable_f2, enable_f3, burst_f0, - burst_f1, burst_f2, \addr_data_f0[0]\, \addr_data_f0[1]\, - \addr_data_f0[2]\, \addr_data_f0[3]\, \addr_data_f0[4]\, - \addr_data_f0[5]\, \addr_data_f0[6]\, \addr_data_f0[7]\, - \addr_data_f0[8]\, \addr_data_f0[9]\, \addr_data_f0[10]\, - \addr_data_f0[11]\, \addr_data_f0[12]\, - \addr_data_f0[13]\, \addr_data_f0[14]\, - \addr_data_f0[15]\, \addr_data_f0[16]\, - \addr_data_f0[17]\, \addr_data_f0[18]\, - \addr_data_f0[19]\, \addr_data_f0[20]\, - \addr_data_f0[21]\, \addr_data_f0[22]\, - \addr_data_f0[23]\, \addr_data_f0[24]\, - \addr_data_f0[25]\, \addr_data_f0[26]\, - \addr_data_f0[27]\, \addr_data_f0[28]\, - \addr_data_f0[29]\, \addr_data_f0[30]\, - \addr_data_f0[31]\, \addr_data_f1[0]\, \addr_data_f1[1]\, - \addr_data_f1[2]\, \addr_data_f1[3]\, \addr_data_f1[4]\, - \addr_data_f1[5]\, \addr_data_f1[6]\, \addr_data_f1[7]\, - \addr_data_f1[8]\, \addr_data_f1[9]\, \addr_data_f1[10]\, - \addr_data_f1[11]\, \addr_data_f1[12]\, - \addr_data_f1[13]\, \addr_data_f1[14]\, - \addr_data_f1[15]\, \addr_data_f1[16]\, - \addr_data_f1[17]\, \addr_data_f1[18]\, - \addr_data_f1[19]\, \addr_data_f1[20]\, - \addr_data_f1[21]\, \addr_data_f1[22]\, - \addr_data_f1[23]\, \addr_data_f1[24]\, - \addr_data_f1[25]\, \addr_data_f1[26]\, - \addr_data_f1[27]\, \addr_data_f1[28]\, - \addr_data_f1[29]\, \addr_data_f1[30]\, - \addr_data_f1[31]\, \addr_data_f2[0]\, \addr_data_f2[1]\, - \addr_data_f2[2]\, \addr_data_f2[3]\, \addr_data_f2[4]\, - \addr_data_f2[5]\, \addr_data_f2[6]\, \addr_data_f2[7]\, - \addr_data_f2[8]\, \addr_data_f2[9]\, \addr_data_f2[10]\, - \addr_data_f2[11]\, \addr_data_f2[12]\, - \addr_data_f2[13]\, \addr_data_f2[14]\, - \addr_data_f2[15]\, \addr_data_f2[16]\, - \addr_data_f2[17]\, \addr_data_f2[18]\, - \addr_data_f2[19]\, \addr_data_f2[20]\, - \addr_data_f2[21]\, \addr_data_f2[22]\, - \addr_data_f2[23]\, \addr_data_f2[24]\, - \addr_data_f2[25]\, \addr_data_f2[26]\, - \addr_data_f2[27]\, \addr_data_f2[28]\, - \addr_data_f2[29]\, \addr_data_f2[30]\, - \addr_data_f2[31]\, \addr_data_f3[0]\, \addr_data_f3[1]\, - \addr_data_f3[2]\, \addr_data_f3[3]\, \addr_data_f3[4]\, - \addr_data_f3[5]\, \addr_data_f3[6]\, \addr_data_f3[7]\, - \addr_data_f3[8]\, \addr_data_f3[9]\, \addr_data_f3[10]\, - \addr_data_f3[11]\, \addr_data_f3[12]\, - \addr_data_f3[13]\, \addr_data_f3[14]\, - \addr_data_f3[15]\, \addr_data_f3[16]\, - \addr_data_f3[17]\, \addr_data_f3[18]\, - \addr_data_f3[19]\, \addr_data_f3[20]\, - \addr_data_f3[21]\, \addr_data_f3[22]\, - \addr_data_f3[23]\, \addr_data_f3[24]\, - \addr_data_f3[25]\, \addr_data_f3[26]\, - \addr_data_f3[27]\, \addr_data_f3[28]\, - \addr_data_f3[29]\, \addr_data_f3[30]\, - \addr_data_f3[31]\, IdlePhase_RNI03G71, - \lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.N_43\, - cnv_run_c, cnv_c, sck_c, \sdo_c[0]\, \sdo_c[1]\, - \sdo_c[2]\, \sdo_c[3]\, \sdo_c[4]\, \sdo_c[5]\, - \sdo_c[6]\, \sdo_c[7]\, cnv_clk_c, cnv_rstn_c, HCLK_c, - HRESETn_c, \apbi_c[0]\, \apbi_c[16]\, \apbi_c[19]\, - \apbi_c[20]\, \apbi_c[21]\, \apbi_c[22]\, \apbi_c[23]\, - \apbi_c[24]\, \apbi_c[49]\, \apbi_c[50]\, \apbi_c[51]\, - \apbi_c[52]\, \apbi_c[53]\, \apbi_c[54]\, \apbi_c[55]\, - \apbi_c[56]\, \apbi_c[57]\, \apbi_c[58]\, \apbi_c[59]\, - \apbi_c[60]\, \apbi_c[61]\, \apbi_c[62]\, \apbi_c[63]\, - \apbi_c[64]\, \apbi_c[65]\, \apbi_c[66]\, \apbi_c[67]\, - \apbi_c[68]\, \apbi_c[69]\, \apbi_c[70]\, \apbi_c[71]\, - \apbi_c[72]\, \apbi_c[73]\, \apbi_c[74]\, \apbi_c[75]\, - \apbi_c[76]\, \apbi_c[77]\, \apbi_c[78]\, \apbi_c[79]\, - \apbi_c[80]\, \apbi_c[81]\, \apbo.prdata_c[0]\, - \apbo.prdata_c[1]\, \apbo.prdata_c[2]\, - \apbo.prdata_c[3]\, \apbo.prdata_c[4]\, - \apbo.prdata_c[5]\, \apbo.prdata_c[6]\, - \apbo.prdata_c[7]\, \apbo.prdata_c[8]\, - \apbo.prdata_c[9]\, \apbo.prdata_c[10]\, - \apbo.prdata_c[11]\, \apbo.prdata_c[12]\, - \apbo.prdata_c[13]\, \apbo.prdata_c[14]\, - \apbo.prdata_c[15]\, \apbo.prdata_c[16]\, - \apbo.prdata_c[17]\, \apbo.prdata_c[18]\, - \apbo.prdata_c[19]\, \apbo.prdata_c[20]\, - \apbo.prdata_c[21]\, \apbo.prdata_c[22]\, - \apbo.prdata_c[23]\, \apbo.prdata_c[24]\, - \apbo.prdata_c[25]\, \apbo.prdata_c[26]\, - \apbo.prdata_c[27]\, \apbo.prdata_c[28]\, - \apbo.prdata_c[29]\, \apbo.prdata_c[30]\, - \apbo.prdata_c[31]\, \apbo.pirq_c[15]\, - \AHB_Master_In_c[13]\, \AHB_Master_In_c[16]\, - \AHB_Master_In_c[17]\, \AHB_Master_In_c[18]\, - \AHB_Master_Out.htrans_c[0]\, - \AHB_Master_Out.htrans_c[1]\, \AHB_Master_Out.haddr_c[0]\, - \AHB_Master_Out.haddr_c[1]\, \AHB_Master_Out.haddr_c[2]\, - \AHB_Master_Out.haddr_c[3]\, \AHB_Master_Out.haddr_c[4]\, - \AHB_Master_Out.haddr_c[5]\, \AHB_Master_Out.haddr_c[6]\, - \AHB_Master_Out.haddr_c[7]\, \AHB_Master_Out.haddr_c[8]\, - \AHB_Master_Out.haddr_c[9]\, \AHB_Master_Out.haddr_c[10]\, - \AHB_Master_Out.haddr_c[11]\, - \AHB_Master_Out.haddr_c[12]\, - \AHB_Master_Out.haddr_c[13]\, - \AHB_Master_Out.haddr_c[14]\, - \AHB_Master_Out.haddr_c[15]\, - \AHB_Master_Out.haddr_c[16]\, - \AHB_Master_Out.haddr_c[17]\, - \AHB_Master_Out.haddr_c[18]\, - \AHB_Master_Out.haddr_c[19]\, - \AHB_Master_Out.haddr_c[20]\, - \AHB_Master_Out.haddr_c[21]\, - \AHB_Master_Out.haddr_c[22]\, - \AHB_Master_Out.haddr_c[23]\, - \AHB_Master_Out.haddr_c[24]\, - \AHB_Master_Out.haddr_c[25]\, - \AHB_Master_Out.haddr_c[26]\, - \AHB_Master_Out.haddr_c[27]\, - \AHB_Master_Out.haddr_c[28]\, - \AHB_Master_Out.haddr_c[29]\, - \AHB_Master_Out.haddr_c[30]\, - \AHB_Master_Out.haddr_c[31]\, \AHB_Master_Out.hwrite_c\, - \AHB_Master_Out.hsize_c[0]\, \AHB_Master_Out.hsize_c[1]\, - \AHB_Master_Out.hburst_c[0]\, - \AHB_Master_Out.hburst_c[1]\, - \AHB_Master_Out.hburst_c[2]\, - \AHB_Master_Out.hwdata_c[0]\, - \AHB_Master_Out.hwdata_c[1]\, - \AHB_Master_Out.hwdata_c[2]\, - \AHB_Master_Out.hwdata_c[3]\, - \AHB_Master_Out.hwdata_c[4]\, - \AHB_Master_Out.hwdata_c[5]\, - \AHB_Master_Out.hwdata_c[6]\, - \AHB_Master_Out.hwdata_c[7]\, - \AHB_Master_Out.hwdata_c[8]\, - \AHB_Master_Out.hwdata_c[9]\, - \AHB_Master_Out.hwdata_c[10]\, - \AHB_Master_Out.hwdata_c[11]\, - \AHB_Master_Out.hwdata_c[12]\, - \AHB_Master_Out.hwdata_c[13]\, - \AHB_Master_Out.hwdata_c[14]\, - \AHB_Master_Out.hwdata_c[15]\, - \AHB_Master_Out.hwdata_c[16]\, - \AHB_Master_Out.hwdata_c[17]\, - \AHB_Master_Out.hwdata_c[18]\, - \AHB_Master_Out.hwdata_c[19]\, - \AHB_Master_Out.hwdata_c[20]\, - \AHB_Master_Out.hwdata_c[21]\, - \AHB_Master_Out.hwdata_c[22]\, - \AHB_Master_Out.hwdata_c[23]\, - \AHB_Master_Out.hwdata_c[24]\, - \AHB_Master_Out.hwdata_c[25]\, - \AHB_Master_Out.hwdata_c[26]\, - \AHB_Master_Out.hwdata_c[27]\, - \AHB_Master_Out.hwdata_c[28]\, - \AHB_Master_Out.hwdata_c[29]\, - \AHB_Master_Out.hwdata_c[30]\, - \AHB_Master_Out.hwdata_c[31]\, \VCC\, \GND\, - coarse_time_0_c, data_shaping_BW_c, data_shaping_R1_0, - data_shaping_R0_0, GND_0, VCC_0 : std_logic; - - for all : lpp_top_apbreg - Use entity work.lpp_top_apbreg(DEF_ARCH); - for all : lpp_top_lfr_wf_picker_ip - Use entity work.lpp_top_lfr_wf_picker_ip(DEF_ARCH); -begin - - - \apbo_pad[90]\ : OUTBUF - port map(D => \GND\, PAD => apbo(90)); - - \apbi_pad[78]\ : INBUF - port map(PAD => apbi(78), Y => \apbi_c[78]\); - - \apbo_pad[113]\ : OUTBUF - port map(D => \GND\, PAD => apbo(113)); - - \AHB_Master_Out_pad[189]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(189)); - - \AHB_Master_Out_pad[170]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(170)); - - \apbo_pad[106]\ : OUTBUF - port map(D => \GND\, PAD => apbo(106)); - - \apbi_pad[23]\ : INBUF - port map(PAD => apbi(23), Y => \apbi_c[23]\); - - \apbo_pad[18]\ : OUTBUF - port map(D => \apbo.prdata_c[18]\, PAD => apbo(18)); - - \AHB_Master_Out_pad[15]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[11]\, PAD => - AHB_Master_Out(15)); - - \AHB_Master_Out_pad[6]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[2]\, PAD => - AHB_Master_Out(6)); - - \AHB_Master_Out_pad[4]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[0]\, PAD => - AHB_Master_Out(4)); - - \AHB_Master_Out_pad[40]\ : OUTBUF - port map(D => \AHB_Master_Out.hburst_c[0]\, PAD => - AHB_Master_Out(40)); - - \AHB_Master_Out_pad[176]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(176)); - - \AHB_Master_Out_pad[132]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(132)); - - \AHB_Master_Out_pad[51]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[4]\, PAD => - AHB_Master_Out(51)); - - \apbo_pad[102]\ : OUTBUF - port map(D => \GND\, PAD => apbo(102)); - - \AHB_Master_Out_pad[257]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(257)); - - \apbo_pad[124]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(124)); - - \AHB_Master_Out_pad[318]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(318)); - - \apbo_pad[91]\ : OUTBUF - port map(D => \GND\, PAD => apbo(91)); - - \AHB_Master_Out_pad[328]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(328)); - - \AHB_Master_In_pad[17]\ : INBUF - port map(PAD => AHB_Master_In(17), Y => - \AHB_Master_In_c[17]\); - - \apbo_pad[95]\ : OUTBUF - port map(D => \GND\, PAD => apbo(95)); - - \AHB_Master_Out_pad[348]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(348)); - - \AHB_Master_Out_pad[259]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(259)); - - \AHB_Master_Out_pad[332]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(332)); - - \AHB_Master_Out_pad[12]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[8]\, PAD => - AHB_Master_Out(12)); - - \AHB_Master_Out_pad[1]\ : OUTBUF - port map(D => - \lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.N_43\, - PAD => AHB_Master_Out(1)); - - \sdo_pad[4]\ : INBUF - port map(PAD => sdo(4), Y => \sdo_c[4]\); - - \AHB_Master_Out_pad[46]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(46)); - - \apbo_pad[48]\ : OUTBUF - port map(D => \GND\, PAD => apbo(48)); - - \AHB_Master_Out_pad[214]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(214)); - - \apbo_pad[6]\ : OUTBUF - port map(D => \apbo.prdata_c[6]\, PAD => apbo(6)); - - \AHB_Master_Out_pad[224]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(224)); - - \AHB_Master_Out_pad[244]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(244)); - - \AHB_Master_Out_pad[150]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(150)); - - \AHB_Master_Out_pad[368]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(368)); - - \AHB_Master_Out_pad[339]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(339)); - - \AHB_Master_Out_pad[297]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(297)); - - \AHB_Master_Out_pad[201]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(201)); - - \AHB_Master_Out_pad[47]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[0]\, PAD => - AHB_Master_Out(47)); - - \AHB_Master_Out_pad[307]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(307)); - - \AHB_Master_Out_pad[213]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(213)); - - \apbo_pad[57]\ : OUTBUF - port map(D => \GND\, PAD => apbo(57)); - - \AHB_Master_Out_pad[223]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(223)); - - \AHB_Master_Out_pad[156]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(156)); - - \AHB_Master_Out_pad[111]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(111)); - - \apbi_pad[76]\ : INBUF - port map(PAD => apbi(76), Y => \apbi_c[76]\); - - \AHB_Master_Out_pad[243]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(243)); - - \AHB_Master_Out_pad[121]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(121)); - - \apbo_pad[89]\ : OUTBUF - port map(D => \GND\, PAD => apbo(89)); - - \AHB_Master_Out_pad[299]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(299)); - - \AHB_Master_Out_pad[141]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(141)); - - \AHB_Master_Out_pad[49]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[2]\, PAD => - AHB_Master_Out(49)); - - \AHB_Master_Out_pad[182]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(182)); - - \apbo_pad[16]\ : OUTBUF - port map(D => \apbo.prdata_c[16]\, PAD => apbo(16)); - - \AHB_Master_Out_pad[264]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(264)); - - \AHB_Master_Out_pad[301]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(301)); - - \apbo_pad[53]\ : OUTBUF - port map(D => \GND\, PAD => apbo(53)); - - \AHB_Master_Out_pad[190]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(190)); - - \AHB_Master_Out_pad[232]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(232)); - - \AHB_Master_In_pad[16]\ : INBUF - port map(PAD => AHB_Master_In(16), Y => - \AHB_Master_In_c[16]\); - - \AHB_Master_Out_pad[263]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(263)); - - \AHB_Master_Out_pad[25]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[21]\, PAD => - AHB_Master_Out(25)); - - \AHB_Master_Out_pad[161]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(161)); - - \AHB_Master_Out_pad[196]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(196)); - - \AHB_Master_Out_pad[134]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(134)); - - \AHB_Master_Out_pad[0]\ : OUTBUF - port map(D => IdlePhase_RNI03G71, PAD => AHB_Master_Out(0)); - - \AHB_Master_In_pad[13]\ : INBUF - port map(PAD => AHB_Master_In(13), Y => - \AHB_Master_In_c[13]\); - - sck_pad : OUTBUF - port map(D => sck_c, PAD => sck); - - \apbi_pad[68]\ : INBUF - port map(PAD => apbi(68), Y => \apbi_c[68]\); - - \AHB_Master_Out_pad[200]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(200)); - - \AHB_Master_Out_pad[61]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[14]\, PAD => - AHB_Master_Out(61)); - - \AHB_Master_Out_pad[105]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(105)); - - \AHB_Master_Out_pad[117]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(117)); - - \AHB_Master_Out_pad[127]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(127)); - - \AHB_Master_Out_pad[147]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(147)); - - \apbo_pad[46]\ : OUTBUF - port map(D => \GND\, PAD => apbo(46)); - - \AHB_Master_Out_pad[335]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(335)); - - \apbi_pad[74]\ : INBUF - port map(PAD => apbi(74), Y => \apbi_c[74]\); - - \AHB_Master_Out_pad[22]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[18]\, PAD => - AHB_Master_Out(22)); - - \apbo_pad[131]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(131)); - - \apbo_pad[7]\ : OUTBUF - port map(D => \apbo.prdata_c[7]\, PAD => apbo(7)); - - \AHB_Master_Out_pad[206]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(206)); - - coarse_time_0_pad : INBUF - port map(PAD => coarse_time_0, Y => coarse_time_0_c); - - \apbo_pad[127]\ : OUTBUF - port map(D => \GND\, PAD => apbo(127)); - - \apbo_pad[14]\ : OUTBUF - port map(D => \apbo.prdata_c[14]\, PAD => apbo(14)); - - \AHB_Master_Out_pad[108]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(108)); - - \apbo_pad[119]\ : OUTBUF - port map(D => \GND\, PAD => apbo(119)); - - \AHB_Master_Out_pad[167]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(167)); - - \AHB_Master_Out_pad[14]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[10]\, PAD => - AHB_Master_Out(14)); - - \AHB_Master_Out_pad[31]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[27]\, PAD => - AHB_Master_Out(31)); - - \AHB_Master_Out_pad[282]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(282)); - - \AHB_Master_Out_pad[184]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(184)); - - \AHB_Master_Out_pad[133]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(133)); - - \apbo_pad[98]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(98)); - - \AHB_Master_Out_pad[303]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(303)); - - \apbo_pad[44]\ : OUTBUF - port map(D => \GND\, PAD => apbo(44)); - - \apbi_pad[66]\ : INBUF - port map(PAD => apbi(66), Y => \apbi_c[66]\); - - \AHB_Master_Out_pad[274]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(274)); - - \apbo_pad[79]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(79)); - - \AHB_Master_Out_pad[211]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(211)); - - \apbo_pad[32]\ : OUTBUF - port map(D => \GND\, PAD => apbo(32)); - - \AHB_Master_Out_pad[317]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(317)); - - \AHB_Master_Out_pad[221]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(221)); - - \AHB_Master_Out_pad[327]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(327)); - - \AHB_Master_Out_pad[241]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(241)); - - \apbi_pad[52]\ : INBUF - port map(PAD => apbi(52), Y => \apbi_c[52]\); - - \AHB_Master_Out_pad[347]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(347)); - - \apbo_pad[22]\ : OUTBUF - port map(D => \apbo.prdata_c[22]\, PAD => apbo(22)); - - \AHB_Master_Out_pad[7]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[3]\, PAD => - AHB_Master_Out(7)); - - \AHB_Master_Out_pad[336]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(336)); - - \AHB_Master_Out_pad[273]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(273)); - - \apbo_pad[116]\ : OUTBUF - port map(D => \GND\, PAD => apbo(116)); - - \AHB_Master_Out_pad[171]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(171)); - - \apbo_pad[108]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(108)); - - \sdo_pad[1]\ : INBUF - port map(PAD => sdo(1), Y => \sdo_c[1]\); - - \AHB_Master_Out_pad[98]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(98)); - - \AHB_Master_Out_pad[13]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[9]\, PAD => - AHB_Master_Out(13)); - - \AHB_Master_Out_pad[358]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(358)); - - \AHB_Master_Out_pad[311]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(311)); - - \apbo_pad[30]\ : OUTBUF - port map(D => \apbo.prdata_c[30]\, PAD => apbo(30)); - - \AHB_Master_Out_pad[321]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(321)); - - \AHB_Master_Out_pad[208]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(208)); - - \apbo_pad[62]\ : OUTBUF - port map(D => \GND\, PAD => apbo(62)); - - \apbo_pad[112]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(112)); - - \AHB_Master_Out_pad[341]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(341)); - - \apbi_pad[50]\ : INBUF - port map(PAD => apbi(50), Y => \apbi_c[50]\); - - \apbo_pad[20]\ : OUTBUF - port map(D => \apbo.prdata_c[20]\, PAD => apbo(20)); - - \AHB_Master_Out_pad[261]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(261)); - - \AHB_Master_Out_pad[367]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(367)); - - \AHB_Master_Out_pad[90]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(90)); - - \AHB_Master_Out_pad[183]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(183)); - - \AHB_Master_Out_pad[109]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(109)); - - GND_i : GND - port map(Y => \GND\); - - \AHB_Master_Out_pad[45]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(45)); - - \AHB_Master_Out_pad[254]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(254)); - - \AHB_Master_Out_pad[210]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(210)); - - \AHB_Master_Out_pad[220]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(220)); - - \AHB_Master_Out_pad[115]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(115)); - - \apbo_pad[60]\ : OUTBUF - port map(D => \GND\, PAD => apbo(60)); - - \apbi_pad[77]\ : INBUF - port map(PAD => apbi(77), Y => \apbi_c[77]\); - - \apbi_pad[64]\ : INBUF - port map(PAD => apbi(64), Y => \apbi_c[64]\); - - \AHB_Master_Out_pad[240]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(240)); - - \AHB_Master_Out_pad[125]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(125)); - - \apbo_pad[96]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(96)); - - \AHB_Master_Out_pad[145]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(145)); - - \apbo_pad[31]\ : OUTBUF - port map(D => \apbo.prdata_c[31]\, PAD => apbo(31)); - - \AHB_Master_Out_pad[361]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(361)); - - \AHB_Master_Out_pad[334]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(334)); - - \AHB_Master_Out_pad[24]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[20]\, PAD => - AHB_Master_Out(24)); - - \AHB_Master_In_pad[18]\ : INBUF - port map(PAD => AHB_Master_In(18), Y => - \AHB_Master_In_c[18]\); - - \apbo_pad[35]\ : OUTBUF - port map(D => \GND\, PAD => apbo(35)); - - \apbi_pad[51]\ : INBUF - port map(PAD => apbi(51), Y => \apbi_c[51]\); - - \AHB_Master_Out_pad[253]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(253)); - - \AHB_Master_Out_pad[177]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(177)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \apbo_pad[21]\ : OUTBUF - port map(D => \apbo.prdata_c[21]\, PAD => apbo(21)); - - \apbi_pad[55]\ : INBUF - port map(PAD => apbi(55), Y => \apbi_c[55]\); - - \AHB_Master_Out_pad[151]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(151)); - - \apbo_pad[25]\ : OUTBUF - port map(D => \apbo.prdata_c[25]\, PAD => apbo(25)); - - \apbo_pad[17]\ : OUTBUF - port map(D => \apbo.prdata_c[17]\, PAD => apbo(17)); - - \apbo_pad[120]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(120)); - - \AHB_Master_Out_pad[300]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(300)); - - data_shaping_BW_pad : OUTBUF - port map(D => data_shaping_BW_c, PAD => data_shaping_BW); - - \apbi_pad[73]\ : INBUF - port map(PAD => apbi(73), Y => \apbi_c[73]\); - - \AHB_Master_Out_pad[96]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(96)); - - \AHB_Master_Out_pad[216]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(216)); - - \apbo_pad[4]\ : OUTBUF - port map(D => \apbo.prdata_c[4]\, PAD => apbo(4)); - - \AHB_Master_Out_pad[226]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(226)); - - \AHB_Master_Out_pad[42]\ : OUTBUF - port map(D => \AHB_Master_Out.hburst_c[2]\, PAD => - AHB_Master_Out(42)); - - \AHB_Master_Out_pad[246]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(246)); - - \AHB_Master_Out_pad[260]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(260)); - - \AHB_Master_Out_pad[118]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(118)); - - \apbo_pad[61]\ : OUTBUF - port map(D => \GND\, PAD => apbo(61)); - - \AHB_Master_Out_pad[294]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(294)); - - \AHB_Master_Out_pad[165]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(165)); - - \AHB_Master_Out_pad[128]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(128)); - - \apbo_pad[65]\ : OUTBUF - port map(D => \GND\, PAD => apbo(65)); - - \AHB_Master_Out_pad[148]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(148)); - - \apbo_pad[13]\ : OUTBUF - port map(D => \apbo.prdata_c[13]\, PAD => apbo(13)); - - \AHB_Master_Out_pad[97]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(97)); - - \apbi_pad[80]\ : INBUF - port map(PAD => apbi(80), Y => \apbi_c[80]\); - - \AHB_Master_Out_pad[235]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(235)); - - \apbo_pad[101]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(101)); - - \AHB_Master_Out_pad[293]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(293)); - - \AHB_Master_Out_pad[191]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(191)); - - \AHB_Master_Out_pad[99]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(99)); - - \apbo_pad[59]\ : OUTBUF - port map(D => \GND\, PAD => apbo(59)); - - \apbo_pad[47]\ : OUTBUF - port map(D => \apbo.pirq_c[15]\, PAD => apbo(47)); - - \AHB_Master_Out_pad[266]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(266)); - - \AHB_Master_Out_pad[23]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[19]\, PAD => - AHB_Master_Out(23)); - - \apbo_pad[94]\ : OUTBUF - port map(D => \GND\, PAD => apbo(94)); - - \apbo_pad[105]\ : OUTBUF - port map(D => \GND\, PAD => apbo(105)); - - \AHB_Master_Out_pad[157]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(157)); - - \AHB_Master_Out_pad[313]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(313)); - - \AHB_Master_Out_pad[168]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(168)); - - \AHB_Master_Out_pad[323]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(323)); - - \AHB_Master_Out_pad[102]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(102)); - - \AHB_Master_Out_pad[343]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(343)); - - \apbo_pad[5]\ : OUTBUF - port map(D => \apbo.prdata_c[5]\, PAD => apbo(5)); - - \apbi_pad[81]\ : INBUF - port map(PAD => apbi(81), Y => \apbi_c[81]\); - - \apbo_pad[43]\ : OUTBUF - port map(D => \GND\, PAD => apbo(43)); - - lpp_top_apbreg_1 : lpp_top_apbreg - port map(status_full_ack(3) => \status_full_ack[3]\, - status_full_ack(2) => \status_full_ack[2]\, - status_full_ack(1) => \status_full_ack[1]\, - status_full_ack(0) => \status_full_ack[0]\, prdata_c(31) - => \apbo.prdata_c[31]\, prdata_c(30) => - \apbo.prdata_c[30]\, prdata_c(29) => \apbo.prdata_c[29]\, - prdata_c(28) => \apbo.prdata_c[28]\, prdata_c(27) => - \apbo.prdata_c[27]\, prdata_c(26) => \apbo.prdata_c[26]\, - prdata_c(25) => \apbo.prdata_c[25]\, prdata_c(24) => - \apbo.prdata_c[24]\, prdata_c(23) => \apbo.prdata_c[23]\, - prdata_c(22) => \apbo.prdata_c[22]\, prdata_c(21) => - \apbo.prdata_c[21]\, prdata_c(20) => \apbo.prdata_c[20]\, - prdata_c(19) => \apbo.prdata_c[19]\, prdata_c(18) => - \apbo.prdata_c[18]\, prdata_c(17) => \apbo.prdata_c[17]\, - prdata_c(16) => \apbo.prdata_c[16]\, prdata_c(15) => - \apbo.prdata_c[15]\, prdata_c(14) => \apbo.prdata_c[14]\, - prdata_c(13) => \apbo.prdata_c[13]\, prdata_c(12) => - \apbo.prdata_c[12]\, prdata_c(11) => \apbo.prdata_c[11]\, - prdata_c(10) => \apbo.prdata_c[10]\, prdata_c(9) => - \apbo.prdata_c[9]\, prdata_c(8) => \apbo.prdata_c[8]\, - prdata_c(7) => \apbo.prdata_c[7]\, prdata_c(6) => - \apbo.prdata_c[6]\, prdata_c(5) => \apbo.prdata_c[5]\, - prdata_c(4) => \apbo.prdata_c[4]\, prdata_c(3) => - \apbo.prdata_c[3]\, prdata_c(2) => \apbo.prdata_c[2]\, - prdata_c(1) => \apbo.prdata_c[1]\, prdata_c(0) => - \apbo.prdata_c[0]\, pirq_c(15) => \apbo.pirq_c[15]\, - addr_data_f2(31) => \addr_data_f2[31]\, addr_data_f2(30) - => \addr_data_f2[30]\, addr_data_f2(29) => - \addr_data_f2[29]\, addr_data_f2(28) => - \addr_data_f2[28]\, addr_data_f2(27) => - \addr_data_f2[27]\, addr_data_f2(26) => - \addr_data_f2[26]\, addr_data_f2(25) => - \addr_data_f2[25]\, addr_data_f2(24) => - \addr_data_f2[24]\, addr_data_f2(23) => - \addr_data_f2[23]\, addr_data_f2(22) => - \addr_data_f2[22]\, addr_data_f2(21) => - \addr_data_f2[21]\, addr_data_f2(20) => - \addr_data_f2[20]\, addr_data_f2(19) => - \addr_data_f2[19]\, addr_data_f2(18) => - \addr_data_f2[18]\, addr_data_f2(17) => - \addr_data_f2[17]\, addr_data_f2(16) => - \addr_data_f2[16]\, addr_data_f2(15) => - \addr_data_f2[15]\, addr_data_f2(14) => - \addr_data_f2[14]\, addr_data_f2(13) => - \addr_data_f2[13]\, addr_data_f2(12) => - \addr_data_f2[12]\, addr_data_f2(11) => - \addr_data_f2[11]\, addr_data_f2(10) => - \addr_data_f2[10]\, addr_data_f2(9) => \addr_data_f2[9]\, - addr_data_f2(8) => \addr_data_f2[8]\, addr_data_f2(7) => - \addr_data_f2[7]\, addr_data_f2(6) => \addr_data_f2[6]\, - addr_data_f2(5) => \addr_data_f2[5]\, addr_data_f2(4) => - \addr_data_f2[4]\, addr_data_f2(3) => \addr_data_f2[3]\, - addr_data_f2(2) => \addr_data_f2[2]\, addr_data_f2(1) => - \addr_data_f2[1]\, addr_data_f2(0) => \addr_data_f2[0]\, - status_new_err_3 => \status_new_err[3]\, - status_new_err_0_2 => \status_new_err[2]\, - status_new_err_0_0 => \status_new_err[0]\, - status_new_err_0_1 => \status_new_err[1]\, - status_full_err_0(3) => \status_full_err[3]\, - status_full_err_0(2) => \status_full_err[2]\, - status_full_err_0(1) => \status_full_err[1]\, - status_full_err_0(0) => \status_full_err[0]\, - status_full(3) => \status_full[3]\, status_full(2) => - \status_full[2]\, status_full(1) => \status_full[1]\, - status_full(0) => \status_full[0]\, addr_data_f3(31) => - \addr_data_f3[31]\, addr_data_f3(30) => - \addr_data_f3[30]\, addr_data_f3(29) => - \addr_data_f3[29]\, addr_data_f3(28) => - \addr_data_f3[28]\, addr_data_f3(27) => - \addr_data_f3[27]\, addr_data_f3(26) => - \addr_data_f3[26]\, addr_data_f3(25) => - \addr_data_f3[25]\, addr_data_f3(24) => - \addr_data_f3[24]\, addr_data_f3(23) => - \addr_data_f3[23]\, addr_data_f3(22) => - \addr_data_f3[22]\, addr_data_f3(21) => - \addr_data_f3[21]\, addr_data_f3(20) => - \addr_data_f3[20]\, addr_data_f3(19) => - \addr_data_f3[19]\, addr_data_f3(18) => - \addr_data_f3[18]\, addr_data_f3(17) => - \addr_data_f3[17]\, addr_data_f3(16) => - \addr_data_f3[16]\, addr_data_f3(15) => - \addr_data_f3[15]\, addr_data_f3(14) => - \addr_data_f3[14]\, addr_data_f3(13) => - \addr_data_f3[13]\, addr_data_f3(12) => - \addr_data_f3[12]\, addr_data_f3(11) => - \addr_data_f3[11]\, addr_data_f3(10) => - \addr_data_f3[10]\, addr_data_f3(9) => \addr_data_f3[9]\, - addr_data_f3(8) => \addr_data_f3[8]\, addr_data_f3(7) => - \addr_data_f3[7]\, addr_data_f3(6) => \addr_data_f3[6]\, - addr_data_f3(5) => \addr_data_f3[5]\, addr_data_f3(4) => - \addr_data_f3[4]\, addr_data_f3(3) => \addr_data_f3[3]\, - addr_data_f3(2) => \addr_data_f3[2]\, addr_data_f3(1) => - \addr_data_f3[1]\, addr_data_f3(0) => \addr_data_f3[0]\, - nb_burst_available(10) => \nb_burst_available[10]\, - nb_burst_available(9) => \nb_burst_available[9]\, - nb_burst_available(8) => \nb_burst_available[8]\, - nb_burst_available(7) => \nb_burst_available[7]\, - nb_burst_available(6) => \nb_burst_available[6]\, - nb_burst_available(5) => \nb_burst_available[5]\, - nb_burst_available(4) => \nb_burst_available[4]\, - nb_burst_available(3) => \nb_burst_available[3]\, - nb_burst_available(2) => \nb_burst_available[2]\, - nb_burst_available(1) => \nb_burst_available[1]\, - nb_burst_available(0) => \nb_burst_available[0]\, - addr_data_f1(31) => \addr_data_f1[31]\, addr_data_f1(30) - => \addr_data_f1[30]\, addr_data_f1(29) => - \addr_data_f1[29]\, addr_data_f1(28) => - \addr_data_f1[28]\, addr_data_f1(27) => - \addr_data_f1[27]\, addr_data_f1(26) => - \addr_data_f1[26]\, addr_data_f1(25) => - \addr_data_f1[25]\, addr_data_f1(24) => - \addr_data_f1[24]\, addr_data_f1(23) => - \addr_data_f1[23]\, addr_data_f1(22) => - \addr_data_f1[22]\, addr_data_f1(21) => - \addr_data_f1[21]\, addr_data_f1(20) => - \addr_data_f1[20]\, addr_data_f1(19) => - \addr_data_f1[19]\, addr_data_f1(18) => - \addr_data_f1[18]\, addr_data_f1(17) => - \addr_data_f1[17]\, addr_data_f1(16) => - \addr_data_f1[16]\, addr_data_f1(15) => - \addr_data_f1[15]\, addr_data_f1(14) => - \addr_data_f1[14]\, addr_data_f1(13) => - \addr_data_f1[13]\, addr_data_f1(12) => - \addr_data_f1[12]\, addr_data_f1(11) => - \addr_data_f1[11]\, addr_data_f1(10) => - \addr_data_f1[10]\, addr_data_f1(9) => \addr_data_f1[9]\, - addr_data_f1(8) => \addr_data_f1[8]\, addr_data_f1(7) => - \addr_data_f1[7]\, addr_data_f1(6) => \addr_data_f1[6]\, - addr_data_f1(5) => \addr_data_f1[5]\, addr_data_f1(4) => - \addr_data_f1[4]\, addr_data_f1(3) => \addr_data_f1[3]\, - addr_data_f1(2) => \addr_data_f1[2]\, addr_data_f1(1) => - \addr_data_f1[1]\, addr_data_f1(0) => \addr_data_f1[0]\, - delta_f2_f1(9) => \delta_f2_f1[9]\, delta_f2_f1(8) => - \delta_f2_f1[8]\, delta_f2_f1(7) => \delta_f2_f1[7]\, - delta_f2_f1(6) => \delta_f2_f1[6]\, delta_f2_f1(5) => - \delta_f2_f1[5]\, delta_f2_f1(4) => \delta_f2_f1[4]\, - delta_f2_f1(3) => \delta_f2_f1[3]\, delta_f2_f1(2) => - \delta_f2_f1[2]\, delta_f2_f1(1) => \delta_f2_f1[1]\, - delta_f2_f1(0) => \delta_f2_f1[0]\, addr_data_f0(31) => - \addr_data_f0[31]\, addr_data_f0(30) => - \addr_data_f0[30]\, addr_data_f0(29) => - \addr_data_f0[29]\, addr_data_f0(28) => - \addr_data_f0[28]\, addr_data_f0(27) => - \addr_data_f0[27]\, addr_data_f0(26) => - \addr_data_f0[26]\, addr_data_f0(25) => - \addr_data_f0[25]\, addr_data_f0(24) => - \addr_data_f0[24]\, addr_data_f0(23) => - \addr_data_f0[23]\, addr_data_f0(22) => - \addr_data_f0[22]\, addr_data_f0(21) => - \addr_data_f0[21]\, addr_data_f0(20) => - \addr_data_f0[20]\, addr_data_f0(19) => - \addr_data_f0[19]\, addr_data_f0(18) => - \addr_data_f0[18]\, addr_data_f0(17) => - \addr_data_f0[17]\, addr_data_f0(16) => - \addr_data_f0[16]\, addr_data_f0(15) => - \addr_data_f0[15]\, addr_data_f0(14) => - \addr_data_f0[14]\, addr_data_f0(13) => - \addr_data_f0[13]\, addr_data_f0(12) => - \addr_data_f0[12]\, addr_data_f0(11) => - \addr_data_f0[11]\, addr_data_f0(10) => - \addr_data_f0[10]\, addr_data_f0(9) => \addr_data_f0[9]\, - addr_data_f0(8) => \addr_data_f0[8]\, addr_data_f0(7) => - \addr_data_f0[7]\, addr_data_f0(6) => \addr_data_f0[6]\, - addr_data_f0(5) => \addr_data_f0[5]\, addr_data_f0(4) => - \addr_data_f0[4]\, addr_data_f0(3) => \addr_data_f0[3]\, - addr_data_f0(2) => \addr_data_f0[2]\, addr_data_f0(1) => - \addr_data_f0[1]\, addr_data_f0(0) => \addr_data_f0[0]\, - delta_f2_f0(9) => \delta_f2_f0[9]\, delta_f2_f0(8) => - \delta_f2_f0[8]\, delta_f2_f0(7) => \delta_f2_f0[7]\, - delta_f2_f0(6) => \delta_f2_f0[6]\, delta_f2_f0(5) => - \delta_f2_f0[5]\, delta_f2_f0(4) => \delta_f2_f0[4]\, - delta_f2_f0(3) => \delta_f2_f0[3]\, delta_f2_f0(2) => - \delta_f2_f0[2]\, delta_f2_f0(1) => \delta_f2_f0[1]\, - delta_f2_f0(0) => \delta_f2_f0[0]\, delta_snapshot(15) - => \delta_snapshot[15]\, delta_snapshot(14) => - \delta_snapshot[14]\, delta_snapshot(13) => - \delta_snapshot[13]\, delta_snapshot(12) => - \delta_snapshot[12]\, delta_snapshot(11) => - \delta_snapshot[11]\, delta_snapshot(10) => - \delta_snapshot[10]\, delta_snapshot(9) => - \delta_snapshot[9]\, delta_snapshot(8) => - \delta_snapshot[8]\, delta_snapshot(7) => - \delta_snapshot[7]\, delta_snapshot(6) => - \delta_snapshot[6]\, delta_snapshot(5) => - \delta_snapshot[5]\, delta_snapshot(4) => - \delta_snapshot[4]\, delta_snapshot(3) => - \delta_snapshot[3]\, delta_snapshot(2) => - \delta_snapshot[2]\, delta_snapshot(1) => - \delta_snapshot[1]\, delta_snapshot(0) => - \delta_snapshot[0]\, nb_snapshot_param(10) => - \nb_snapshot_param[10]\, nb_snapshot_param(9) => - \nb_snapshot_param[9]\, nb_snapshot_param(8) => - \nb_snapshot_param[8]\, nb_snapshot_param(7) => - \nb_snapshot_param[7]\, nb_snapshot_param(6) => - \nb_snapshot_param[6]\, nb_snapshot_param(5) => - \nb_snapshot_param[5]\, nb_snapshot_param(4) => - \nb_snapshot_param[4]\, nb_snapshot_param(3) => - \nb_snapshot_param[3]\, nb_snapshot_param(2) => - \nb_snapshot_param[2]\, nb_snapshot_param(1) => - \nb_snapshot_param[1]\, nb_snapshot_param(0) => - \nb_snapshot_param[0]\, apbi_c_81 => \apbi_c[81]\, - apbi_c_80 => \apbi_c[80]\, apbi_c_79 => \apbi_c[79]\, - apbi_c_78 => \apbi_c[78]\, apbi_c_77 => \apbi_c[77]\, - apbi_c_76 => \apbi_c[76]\, apbi_c_75 => \apbi_c[75]\, - apbi_c_74 => \apbi_c[74]\, apbi_c_73 => \apbi_c[73]\, - apbi_c_72 => \apbi_c[72]\, apbi_c_71 => \apbi_c[71]\, - apbi_c_70 => \apbi_c[70]\, apbi_c_69 => \apbi_c[69]\, - apbi_c_68 => \apbi_c[68]\, apbi_c_67 => \apbi_c[67]\, - apbi_c_66 => \apbi_c[66]\, apbi_c_65 => \apbi_c[65]\, - apbi_c_64 => \apbi_c[64]\, apbi_c_63 => \apbi_c[63]\, - apbi_c_62 => \apbi_c[62]\, apbi_c_61 => \apbi_c[61]\, - apbi_c_60 => \apbi_c[60]\, apbi_c_59 => \apbi_c[59]\, - apbi_c_58 => \apbi_c[58]\, apbi_c_57 => \apbi_c[57]\, - apbi_c_56 => \apbi_c[56]\, apbi_c_55 => \apbi_c[55]\, - apbi_c_24 => \apbi_c[24]\, apbi_c_23 => \apbi_c[23]\, - apbi_c_0 => \apbi_c[0]\, apbi_c_50 => \apbi_c[50]\, - apbi_c_51 => \apbi_c[51]\, apbi_c_52 => \apbi_c[52]\, - apbi_c_16 => \apbi_c[16]\, apbi_c_49 => \apbi_c[49]\, - apbi_c_22 => \apbi_c[22]\, apbi_c_20 => \apbi_c[20]\, - apbi_c_19 => \apbi_c[19]\, apbi_c_21 => \apbi_c[21]\, - apbi_c_54 => \apbi_c[54]\, apbi_c_53 => \apbi_c[53]\, - data_shaping_R0 => data_shaping_R0, data_shaping_R1 => - data_shaping_R1, enable_f0 => enable_f0, - data_shaping_BW_c => data_shaping_BW_c, burst_f2 => - burst_f2, burst_f1 => burst_f1, burst_f0 => burst_f0, - enable_f3 => enable_f3, enable_f2 => enable_f2, - data_shaping_SP1 => data_shaping_SP1, enable_f1 => - enable_f1, data_shaping_SP0 => data_shaping_SP0, - data_shaping_R1_0 => data_shaping_R1_0, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, data_shaping_R0_0 => - data_shaping_R0_0); - - \AHB_Master_Out_pad[78]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[31]\, PAD => - AHB_Master_Out(78)); - - \AHB_Master_Out_pad[271]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(271)); - - cnv_pad : OUTBUF - port map(D => cnv_c, PAD => cnv); - - \AHB_Master_Out_pad[302]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(302)); - - \AHB_Master_Out_pad[88]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(88)); - - \AHB_Master_Out_pad[363]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(363)); - - \AHB_Master_Out_pad[218]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(218)); - - \AHB_Master_Out_pad[197]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(197)); - - \apbo_pad[104]\ : OUTBUF - port map(D => \GND\, PAD => apbo(104)); - - \AHB_Master_Out_pad[70]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[23]\, PAD => - AHB_Master_Out(70)); - - \AHB_Master_Out_pad[228]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(228)); - - \AHB_Master_Out_pad[248]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(248)); - - \AHB_Master_Out_pad[285]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(285)); - - \sdo_pad[3]\ : INBUF - port map(PAD => sdo(3), Y => \sdo_c[3]\); - - \AHB_Master_Out_pad[80]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(80)); - - \AHB_Master_Out_pad[309]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(309)); - - VCC_i : VCC - port map(Y => \VCC\); - - \apbo_pad[82]\ : OUTBUF - port map(D => \GND\, PAD => apbo(82)); - - \apbi_pad[67]\ : INBUF - port map(PAD => apbi(67), Y => \apbi_c[67]\); - - \AHB_Master_Out_pad[119]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(119)); - - \apbo_pad[0]\ : OUTBUF - port map(D => \apbo.prdata_c[0]\, PAD => apbo(0)); - - \AHB_Master_Out_pad[129]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(129)); - - \AHB_Master_Out_pad[149]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(149)); - - \AHB_Master_Out_pad[58]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[11]\, PAD => - AHB_Master_Out(58)); - - \AHB_Master_Out_pad[270]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(270)); - - \AHB_Master_Out_pad[268]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(268)); - - \AHB_Master_Out_pad[251]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(251)); - - \AHB_Master_Out_pad[237]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(237)); - - \AHB_Master_Out_pad[175]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(175)); - - \AHB_Master_Out_pad[11]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[7]\, PAD => - AHB_Master_Out(11)); - - \apbi_pad[63]\ : INBUF - port map(PAD => apbi(63), Y => \apbi_c[63]\); - - \AHB_Master_Out_pad[76]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[29]\, PAD => - AHB_Master_Out(76)); - - \AHB_Master_Out_pad[357]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(357)); - - \apbo_pad[80]\ : OUTBUF - port map(D => \GND\, PAD => apbo(80)); - - \AHB_Master_Out_pad[44]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(44)); - - \AHB_Master_Out_pad[310]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(310)); - - \AHB_Master_Out_pad[86]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(86)); - - \AHB_Master_Out_pad[50]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[3]\, PAD => - AHB_Master_Out(50)); - - \AHB_Master_Out_pad[320]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(320)); - - \AHB_Master_Out_pad[239]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(239)); - - \AHB_Master_Out_pad[202]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(202)); - - \sdo_pad[5]\ : INBUF - port map(PAD => sdo(5), Y => \sdo_c[5]\); - - lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip - port map(nb_snapshot_param(10) => \nb_snapshot_param[10]\, - nb_snapshot_param(9) => \nb_snapshot_param[9]\, - nb_snapshot_param(8) => \nb_snapshot_param[8]\, - nb_snapshot_param(7) => \nb_snapshot_param[7]\, - nb_snapshot_param(6) => \nb_snapshot_param[6]\, - nb_snapshot_param(5) => \nb_snapshot_param[5]\, - nb_snapshot_param(4) => \nb_snapshot_param[4]\, - nb_snapshot_param(3) => \nb_snapshot_param[3]\, - nb_snapshot_param(2) => \nb_snapshot_param[2]\, - nb_snapshot_param(1) => \nb_snapshot_param[1]\, - nb_snapshot_param(0) => \nb_snapshot_param[0]\, - delta_f2_f0(9) => \delta_f2_f0[9]\, delta_f2_f0(8) => - \delta_f2_f0[8]\, delta_f2_f0(7) => \delta_f2_f0[7]\, - delta_f2_f0(6) => \delta_f2_f0[6]\, delta_f2_f0(5) => - \delta_f2_f0[5]\, delta_f2_f0(4) => \delta_f2_f0[4]\, - delta_f2_f0(3) => \delta_f2_f0[3]\, delta_f2_f0(2) => - \delta_f2_f0[2]\, delta_f2_f0(1) => \delta_f2_f0[1]\, - delta_f2_f0(0) => \delta_f2_f0[0]\, delta_snapshot(15) - => \delta_snapshot[15]\, delta_snapshot(14) => - \delta_snapshot[14]\, delta_snapshot(13) => - \delta_snapshot[13]\, delta_snapshot(12) => - \delta_snapshot[12]\, delta_snapshot(11) => - \delta_snapshot[11]\, delta_snapshot(10) => - \delta_snapshot[10]\, delta_snapshot(9) => - \delta_snapshot[9]\, delta_snapshot(8) => - \delta_snapshot[8]\, delta_snapshot(7) => - \delta_snapshot[7]\, delta_snapshot(6) => - \delta_snapshot[6]\, delta_snapshot(5) => - \delta_snapshot[5]\, delta_snapshot(4) => - \delta_snapshot[4]\, delta_snapshot(3) => - \delta_snapshot[3]\, delta_snapshot(2) => - \delta_snapshot[2]\, delta_snapshot(1) => - \delta_snapshot[1]\, delta_snapshot(0) => - \delta_snapshot[0]\, delta_f2_f1(9) => \delta_f2_f1[9]\, - delta_f2_f1(8) => \delta_f2_f1[8]\, delta_f2_f1(7) => - \delta_f2_f1[7]\, delta_f2_f1(6) => \delta_f2_f1[6]\, - delta_f2_f1(5) => \delta_f2_f1[5]\, delta_f2_f1(4) => - \delta_f2_f1[4]\, delta_f2_f1(3) => \delta_f2_f1[3]\, - delta_f2_f1(2) => \delta_f2_f1[2]\, delta_f2_f1(1) => - \delta_f2_f1[1]\, delta_f2_f1(0) => \delta_f2_f1[0]\, - status_new_err(3) => \status_new_err[3]\, - status_new_err(2) => \status_new_err[2]\, - status_new_err(1) => \status_new_err[1]\, - status_new_err(0) => \status_new_err[0]\, hwdata_c(31) - => \AHB_Master_Out.hwdata_c[31]\, hwdata_c(30) => - \AHB_Master_Out.hwdata_c[30]\, hwdata_c(29) => - \AHB_Master_Out.hwdata_c[29]\, hwdata_c(28) => - \AHB_Master_Out.hwdata_c[28]\, hwdata_c(27) => - \AHB_Master_Out.hwdata_c[27]\, hwdata_c(26) => - \AHB_Master_Out.hwdata_c[26]\, hwdata_c(25) => - \AHB_Master_Out.hwdata_c[25]\, hwdata_c(24) => - \AHB_Master_Out.hwdata_c[24]\, hwdata_c(23) => - \AHB_Master_Out.hwdata_c[23]\, hwdata_c(22) => - \AHB_Master_Out.hwdata_c[22]\, hwdata_c(21) => - \AHB_Master_Out.hwdata_c[21]\, hwdata_c(20) => - \AHB_Master_Out.hwdata_c[20]\, hwdata_c(19) => - \AHB_Master_Out.hwdata_c[19]\, hwdata_c(18) => - \AHB_Master_Out.hwdata_c[18]\, hwdata_c(17) => - \AHB_Master_Out.hwdata_c[17]\, hwdata_c(16) => - \AHB_Master_Out.hwdata_c[16]\, hwdata_c(15) => - \AHB_Master_Out.hwdata_c[15]\, hwdata_c(14) => - \AHB_Master_Out.hwdata_c[14]\, hwdata_c(13) => - \AHB_Master_Out.hwdata_c[13]\, hwdata_c(12) => - \AHB_Master_Out.hwdata_c[12]\, hwdata_c(11) => - \AHB_Master_Out.hwdata_c[11]\, hwdata_c(10) => - \AHB_Master_Out.hwdata_c[10]\, hwdata_c(9) => - \AHB_Master_Out.hwdata_c[9]\, hwdata_c(8) => - \AHB_Master_Out.hwdata_c[8]\, hwdata_c(7) => - \AHB_Master_Out.hwdata_c[7]\, hwdata_c(6) => - \AHB_Master_Out.hwdata_c[6]\, hwdata_c(5) => - \AHB_Master_Out.hwdata_c[5]\, hwdata_c(4) => - \AHB_Master_Out.hwdata_c[4]\, hwdata_c(3) => - \AHB_Master_Out.hwdata_c[3]\, hwdata_c(2) => - \AHB_Master_Out.hwdata_c[2]\, hwdata_c(1) => - \AHB_Master_Out.hwdata_c[1]\, hwdata_c(0) => - \AHB_Master_Out.hwdata_c[0]\, addr_data_f0(31) => - \addr_data_f0[31]\, addr_data_f0(30) => - \addr_data_f0[30]\, addr_data_f0(29) => - \addr_data_f0[29]\, addr_data_f0(28) => - \addr_data_f0[28]\, addr_data_f0(27) => - \addr_data_f0[27]\, addr_data_f0(26) => - \addr_data_f0[26]\, addr_data_f0(25) => - \addr_data_f0[25]\, addr_data_f0(24) => - \addr_data_f0[24]\, addr_data_f0(23) => - \addr_data_f0[23]\, addr_data_f0(22) => - \addr_data_f0[22]\, addr_data_f0(21) => - \addr_data_f0[21]\, addr_data_f0(20) => - \addr_data_f0[20]\, addr_data_f0(19) => - \addr_data_f0[19]\, addr_data_f0(18) => - \addr_data_f0[18]\, addr_data_f0(17) => - \addr_data_f0[17]\, addr_data_f0(16) => - \addr_data_f0[16]\, addr_data_f0(15) => - \addr_data_f0[15]\, addr_data_f0(14) => - \addr_data_f0[14]\, addr_data_f0(13) => - \addr_data_f0[13]\, addr_data_f0(12) => - \addr_data_f0[12]\, addr_data_f0(11) => - \addr_data_f0[11]\, addr_data_f0(10) => - \addr_data_f0[10]\, addr_data_f0(9) => \addr_data_f0[9]\, - addr_data_f0(8) => \addr_data_f0[8]\, addr_data_f0(7) => - \addr_data_f0[7]\, addr_data_f0(6) => \addr_data_f0[6]\, - addr_data_f0(5) => \addr_data_f0[5]\, addr_data_f0(4) => - \addr_data_f0[4]\, addr_data_f0(3) => \addr_data_f0[3]\, - addr_data_f0(2) => \addr_data_f0[2]\, addr_data_f0(1) => - \addr_data_f0[1]\, addr_data_f0(0) => \addr_data_f0[0]\, - addr_data_f1(31) => \addr_data_f1[31]\, addr_data_f1(30) - => \addr_data_f1[30]\, addr_data_f1(29) => - \addr_data_f1[29]\, addr_data_f1(28) => - \addr_data_f1[28]\, addr_data_f1(27) => - \addr_data_f1[27]\, addr_data_f1(26) => - \addr_data_f1[26]\, addr_data_f1(25) => - \addr_data_f1[25]\, addr_data_f1(24) => - \addr_data_f1[24]\, addr_data_f1(23) => - \addr_data_f1[23]\, addr_data_f1(22) => - \addr_data_f1[22]\, addr_data_f1(21) => - \addr_data_f1[21]\, addr_data_f1(20) => - \addr_data_f1[20]\, addr_data_f1(19) => - \addr_data_f1[19]\, addr_data_f1(18) => - \addr_data_f1[18]\, addr_data_f1(17) => - \addr_data_f1[17]\, addr_data_f1(16) => - \addr_data_f1[16]\, addr_data_f1(15) => - \addr_data_f1[15]\, addr_data_f1(14) => - \addr_data_f1[14]\, addr_data_f1(13) => - \addr_data_f1[13]\, addr_data_f1(12) => - \addr_data_f1[12]\, addr_data_f1(11) => - \addr_data_f1[11]\, addr_data_f1(10) => - \addr_data_f1[10]\, addr_data_f1(9) => \addr_data_f1[9]\, - addr_data_f1(8) => \addr_data_f1[8]\, addr_data_f1(7) => - \addr_data_f1[7]\, addr_data_f1(6) => \addr_data_f1[6]\, - addr_data_f1(5) => \addr_data_f1[5]\, addr_data_f1(4) => - \addr_data_f1[4]\, addr_data_f1(3) => \addr_data_f1[3]\, - addr_data_f1(2) => \addr_data_f1[2]\, addr_data_f1(1) => - \addr_data_f1[1]\, addr_data_f1(0) => \addr_data_f1[0]\, - addr_data_f2(31) => \addr_data_f2[31]\, addr_data_f2(30) - => \addr_data_f2[30]\, addr_data_f2(29) => - \addr_data_f2[29]\, addr_data_f2(28) => - \addr_data_f2[28]\, addr_data_f2(27) => - \addr_data_f2[27]\, addr_data_f2(26) => - \addr_data_f2[26]\, addr_data_f2(25) => - \addr_data_f2[25]\, addr_data_f2(24) => - \addr_data_f2[24]\, addr_data_f2(23) => - \addr_data_f2[23]\, addr_data_f2(22) => - \addr_data_f2[22]\, addr_data_f2(21) => - \addr_data_f2[21]\, addr_data_f2(20) => - \addr_data_f2[20]\, addr_data_f2(19) => - \addr_data_f2[19]\, addr_data_f2(18) => - \addr_data_f2[18]\, addr_data_f2(17) => - \addr_data_f2[17]\, addr_data_f2(16) => - \addr_data_f2[16]\, addr_data_f2(15) => - \addr_data_f2[15]\, addr_data_f2(14) => - \addr_data_f2[14]\, addr_data_f2(13) => - \addr_data_f2[13]\, addr_data_f2(12) => - \addr_data_f2[12]\, addr_data_f2(11) => - \addr_data_f2[11]\, addr_data_f2(10) => - \addr_data_f2[10]\, addr_data_f2(9) => \addr_data_f2[9]\, - addr_data_f2(8) => \addr_data_f2[8]\, addr_data_f2(7) => - \addr_data_f2[7]\, addr_data_f2(6) => \addr_data_f2[6]\, - addr_data_f2(5) => \addr_data_f2[5]\, addr_data_f2(4) => - \addr_data_f2[4]\, addr_data_f2(3) => \addr_data_f2[3]\, - addr_data_f2(2) => \addr_data_f2[2]\, addr_data_f2(1) => - \addr_data_f2[1]\, addr_data_f2(0) => \addr_data_f2[0]\, - addr_data_f3(31) => \addr_data_f3[31]\, addr_data_f3(30) - => \addr_data_f3[30]\, addr_data_f3(29) => - \addr_data_f3[29]\, addr_data_f3(28) => - \addr_data_f3[28]\, addr_data_f3(27) => - \addr_data_f3[27]\, addr_data_f3(26) => - \addr_data_f3[26]\, addr_data_f3(25) => - \addr_data_f3[25]\, addr_data_f3(24) => - \addr_data_f3[24]\, addr_data_f3(23) => - \addr_data_f3[23]\, addr_data_f3(22) => - \addr_data_f3[22]\, addr_data_f3(21) => - \addr_data_f3[21]\, addr_data_f3(20) => - \addr_data_f3[20]\, addr_data_f3(19) => - \addr_data_f3[19]\, addr_data_f3(18) => - \addr_data_f3[18]\, addr_data_f3(17) => - \addr_data_f3[17]\, addr_data_f3(16) => - \addr_data_f3[16]\, addr_data_f3(15) => - \addr_data_f3[15]\, addr_data_f3(14) => - \addr_data_f3[14]\, addr_data_f3(13) => - \addr_data_f3[13]\, addr_data_f3(12) => - \addr_data_f3[12]\, addr_data_f3(11) => - \addr_data_f3[11]\, addr_data_f3(10) => - \addr_data_f3[10]\, addr_data_f3(9) => \addr_data_f3[9]\, - addr_data_f3(8) => \addr_data_f3[8]\, addr_data_f3(7) => - \addr_data_f3[7]\, addr_data_f3(6) => \addr_data_f3[6]\, - addr_data_f3(5) => \addr_data_f3[5]\, addr_data_f3(4) => - \addr_data_f3[4]\, addr_data_f3(3) => \addr_data_f3[3]\, - addr_data_f3(2) => \addr_data_f3[2]\, addr_data_f3(1) => - \addr_data_f3[1]\, addr_data_f3(0) => \addr_data_f3[0]\, - status_full(3) => \status_full[3]\, status_full(2) => - \status_full[2]\, status_full(1) => \status_full[1]\, - status_full(0) => \status_full[0]\, status_full_err(3) - => \status_full_err[3]\, status_full_err(2) => - \status_full_err[2]\, status_full_err(1) => - \status_full_err[1]\, status_full_err(0) => - \status_full_err[0]\, nb_burst_available(10) => - \nb_burst_available[10]\, nb_burst_available(9) => - \nb_burst_available[9]\, nb_burst_available(8) => - \nb_burst_available[8]\, nb_burst_available(7) => - \nb_burst_available[7]\, nb_burst_available(6) => - \nb_burst_available[6]\, nb_burst_available(5) => - \nb_burst_available[5]\, nb_burst_available(4) => - \nb_burst_available[4]\, nb_burst_available(3) => - \nb_burst_available[3]\, nb_burst_available(2) => - \nb_burst_available[2]\, nb_burst_available(1) => - \nb_burst_available[1]\, nb_burst_available(0) => - \nb_burst_available[0]\, haddr_c(31) => - \AHB_Master_Out.haddr_c[31]\, haddr_c(30) => - \AHB_Master_Out.haddr_c[30]\, haddr_c(29) => - \AHB_Master_Out.haddr_c[29]\, haddr_c(28) => - \AHB_Master_Out.haddr_c[28]\, haddr_c(27) => - \AHB_Master_Out.haddr_c[27]\, haddr_c(26) => - \AHB_Master_Out.haddr_c[26]\, haddr_c(25) => - \AHB_Master_Out.haddr_c[25]\, haddr_c(24) => - \AHB_Master_Out.haddr_c[24]\, haddr_c(23) => - \AHB_Master_Out.haddr_c[23]\, haddr_c(22) => - \AHB_Master_Out.haddr_c[22]\, haddr_c(21) => - \AHB_Master_Out.haddr_c[21]\, haddr_c(20) => - \AHB_Master_Out.haddr_c[20]\, haddr_c(19) => - \AHB_Master_Out.haddr_c[19]\, haddr_c(18) => - \AHB_Master_Out.haddr_c[18]\, haddr_c(17) => - \AHB_Master_Out.haddr_c[17]\, haddr_c(16) => - \AHB_Master_Out.haddr_c[16]\, haddr_c(15) => - \AHB_Master_Out.haddr_c[15]\, haddr_c(14) => - \AHB_Master_Out.haddr_c[14]\, haddr_c(13) => - \AHB_Master_Out.haddr_c[13]\, haddr_c(12) => - \AHB_Master_Out.haddr_c[12]\, haddr_c(11) => - \AHB_Master_Out.haddr_c[11]\, haddr_c(10) => - \AHB_Master_Out.haddr_c[10]\, haddr_c(9) => - \AHB_Master_Out.haddr_c[9]\, haddr_c(8) => - \AHB_Master_Out.haddr_c[8]\, haddr_c(7) => - \AHB_Master_Out.haddr_c[7]\, haddr_c(6) => - \AHB_Master_Out.haddr_c[6]\, haddr_c(5) => - \AHB_Master_Out.haddr_c[5]\, haddr_c(4) => - \AHB_Master_Out.haddr_c[4]\, haddr_c(3) => - \AHB_Master_Out.haddr_c[3]\, haddr_c(2) => - \AHB_Master_Out.haddr_c[2]\, haddr_c(1) => - \AHB_Master_Out.haddr_c[1]\, haddr_c(0) => - \AHB_Master_Out.haddr_c[0]\, AHB_Master_In_c_3 => - \AHB_Master_In_c[16]\, AHB_Master_In_c_0 => - \AHB_Master_In_c[13]\, AHB_Master_In_c_4 => - \AHB_Master_In_c[17]\, AHB_Master_In_c_5 => - \AHB_Master_In_c[18]\, hsize_c(1) => - \AHB_Master_Out.hsize_c[1]\, hsize_c(0) => - \AHB_Master_Out.hsize_c[0]\, htrans_c(1) => - \AHB_Master_Out.htrans_c[1]\, htrans_c(0) => - \AHB_Master_Out.htrans_c[0]\, hburst_c(2) => - \AHB_Master_Out.hburst_c[2]\, hburst_c(1) => - \AHB_Master_Out.hburst_c[1]\, hburst_c(0) => - \AHB_Master_Out.hburst_c[0]\, status_full_ack(3) => - \status_full_ack[3]\, status_full_ack(2) => - \status_full_ack[2]\, status_full_ack(1) => - \status_full_ack[1]\, status_full_ack(0) => - \status_full_ack[0]\, sdo_c(7) => \sdo_c[7]\, sdo_c(6) - => \sdo_c[6]\, sdo_c(5) => \sdo_c[5]\, sdo_c(4) => - \sdo_c[4]\, sdo_c(3) => \sdo_c[3]\, sdo_c(2) => - \sdo_c[2]\, sdo_c(1) => \sdo_c[1]\, sdo_c(0) => - \sdo_c[0]\, coarse_time_0_c => coarse_time_0_c, enable_f0 - => enable_f0, data_shaping_R0 => data_shaping_R0, - data_shaping_R0_0 => data_shaping_R0_0, burst_f0 => - burst_f0, data_shaping_R1 => data_shaping_R1, - data_shaping_R1_0 => data_shaping_R1_0, enable_f1 => - enable_f1, burst_f1 => burst_f1, enable_f2 => enable_f2, - burst_f2 => burst_f2, enable_f3 => enable_f3, N_43 => - \lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.N_43\, - IdlePhase_RNI03G71 => IdlePhase_RNI03G71, hwrite_c => - \AHB_Master_Out.hwrite_c\, lpp_top_lfr_wf_picker_ip_GND - => \GND\, lpp_top_lfr_wf_picker_ip_VCC => \VCC\, - cnv_run_c => cnv_run_c, sck_c => sck_c, cnv_c => cnv_c, - cnv_clk_c => cnv_clk_c, cnv_rstn_c => cnv_rstn_c, - data_shaping_SP0 => data_shaping_SP0, data_shaping_SP1 - => data_shaping_SP1, HRESETn_c => HRESETn_c, HCLK_c => - HCLK_c); - - \apbo_pad[38]\ : OUTBUF - port map(D => \GND\, PAD => apbo(38)); - - \AHB_Master_Out_pad[340]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(340)); - - \AHB_Master_Out_pad[169]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(169)); - - \apbi_pad[58]\ : INBUF - port map(PAD => apbi(58), Y => \apbi_c[58]\); - - \AHB_Master_Out_pad[77]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[30]\, PAD => - AHB_Master_Out(77)); - - \apbo_pad[28]\ : OUTBUF - port map(D => \apbo.prdata_c[28]\, PAD => apbo(28)); - - \AHB_Master_Out_pad[104]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(104)); - - \AHB_Master_Out_pad[351]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(351)); - - \AHB_Master_Out_pad[276]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(276)); - - \apbo_pad[118]\ : OUTBUF - port map(D => \GND\, PAD => apbo(118)); - - \AHB_Master_Out_pad[87]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(87)); - - \AHB_Master_Out_pad[79]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(79)); - - \AHB_Master_Out_pad[178]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(178)); - - \AHB_Master_Out_pad[130]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(130)); - - \apbo_pad[81]\ : OUTBUF - port map(D => \GND\, PAD => apbo(81)); - - \AHB_Master_Out_pad[291]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(291)); - - \apbo_pad[85]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(85)); - - \apbo_pad[97]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(97)); - - \apbo_pad[68]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(68)); - - \AHB_Master_Out_pad[89]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(89)); - - \AHB_Master_Out_pad[360]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(360)); - - \AHB_Master_Out_pad[305]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(305)); - - \AHB_Master_Out_pad[136]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(136)); - - \AHB_Master_Out_pad[56]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[9]\, PAD => - AHB_Master_Out(56)); - - \apbo_pad[130]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(130)); - - \AHB_Master_Out_pad[250]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(250)); - - \apbo_pad[1]\ : OUTBUF - port map(D => \apbo.prdata_c[1]\, PAD => apbo(1)); - - \AHB_Master_Out_pad[155]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(155)); - - \apbo_pad[8]\ : OUTBUF - port map(D => \apbo.prdata_c[8]\, PAD => apbo(8)); - - \AHB_Master_Out_pad[112]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(112)); - - \AHB_Master_Out_pad[43]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(43)); - - \AHB_Master_Out_pad[122]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(122)); - - \apbo_pad[93]\ : OUTBUF - port map(D => \GND\, PAD => apbo(93)); - - \AHB_Master_Out_pad[57]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[10]\, PAD => - AHB_Master_Out(57)); - - \AHB_Master_Out_pad[287]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(287)); - - \AHB_Master_Out_pad[142]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(142)); - - \apbo_pad[123]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(123)); - - \AHB_Master_Out_pad[59]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[12]\, PAD => - AHB_Master_Out(59)); - - \AHB_Master_Out_pad[289]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(289)); - - \AHB_Master_Out_pad[256]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(256)); - - \AHB_Master_Out_pad[95]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(95)); - - \AHB_Master_Out_pad[312]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(312)); - - \apbo_pad[107]\ : OUTBUF - port map(D => \GND\, PAD => apbo(107)); - - \AHB_Master_Out_pad[322]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(322)); - - \AHB_Master_Out_pad[158]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(158)); - - \AHB_Master_Out_pad[342]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(342)); - - \AHB_Master_Out_pad[290]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(290)); - - \AHB_Master_Out_pad[103]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(103)); - - \apbo_pad[36]\ : OUTBUF - port map(D => \GND\, PAD => apbo(36)); - - \apbi_pad[16]\ : INBUF - port map(PAD => apbi(16), Y => \apbi_c[16]\); - - \AHB_Master_Out_pad[68]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[21]\, PAD => - AHB_Master_Out(68)); - - \AHB_Master_Out_pad[195]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(195)); - - \AHB_Master_Out_pad[21]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[17]\, PAD => - AHB_Master_Out(21)); - - \apbi_pad[56]\ : INBUF - port map(PAD => apbi(56), Y => \apbi_c[56]\); - - \AHB_Master_Out_pad[162]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(162)); - - \apbo_pad[72]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(72)); - - \apbo_pad[26]\ : OUTBUF - port map(D => \apbo.prdata_c[26]\, PAD => apbo(26)); - - \apbi_pad[79]\ : INBUF - port map(PAD => apbi(79), Y => \apbi_c[79]\); - - \AHB_Master_Out_pad[180]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(180)); - - \AHB_Master_Out_pad[278]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(278)); - - \AHB_Master_Out_pad[319]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(319)); - - \AHB_Master_Out_pad[329]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(329)); - - \apbo_pad[111]\ : OUTBUF - port map(D => \GND\, PAD => apbo(111)); - - \AHB_Master_Out_pad[60]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[13]\, PAD => - AHB_Master_Out(60)); - - \AHB_Master_Out_pad[349]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(349)); - - \AHB_Master_Out_pad[186]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(186)); - - \apbo_pad[19]\ : OUTBUF - port map(D => \apbo.prdata_c[19]\, PAD => apbo(19)); - - \AHB_Master_Out_pad[92]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(92)); - - \AHB_Master_Out_pad[296]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(296)); - - \apbo_pad[66]\ : OUTBUF - port map(D => \GND\, PAD => apbo(66)); - - \AHB_Master_Out_pad[362]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(362)); - - \AHB_Master_Out_pad[353]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(353)); - - \AHB_Master_Out_pad[306]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(306)); - - \AHB_Master_Out_pad[179]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(179)); - - \apbo_pad[70]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(70)); - - \apbi_pad[22]\ : INBUF - port map(PAD => apbi(22), Y => \apbi_c[22]\); - - \AHB_Master_Out_pad[198]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(198)); - - \apbo_pad[115]\ : OUTBUF - port map(D => \GND\, PAD => apbo(115)); - - \AHB_Master_Out_pad[38]\ : OUTBUF - port map(D => \AHB_Master_Out.hsize_c[1]\, PAD => - AHB_Master_Out(38)); - - \AHB_Master_Out_pad[369]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(369)); - - \AHB_Master_Out_pad[212]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(212)); - - \AHB_Master_Out_pad[222]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(222)); - - \AHB_Master_Out_pad[66]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[19]\, PAD => - AHB_Master_Out(66)); - - \AHB_Master_Out_pad[242]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(242)); - - \apbi_pad[20]\ : INBUF - port map(PAD => apbi(20), Y => \apbi_c[20]\); - - \AHB_Master_Out_pad[370]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(370)); - - \apbo_pad[34]\ : OUTBUF - port map(D => \GND\, PAD => apbo(34)); - - \AHB_Master_Out_pad[114]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(114)); - - \apbo_pad[49]\ : OUTBUF - port map(D => \GND\, PAD => apbo(49)); - - \AHB_Master_Out_pad[124]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(124)); - - \apbo_pad[71]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(71)); - - \apbi_pad[54]\ : INBUF - port map(PAD => apbi(54), Y => \apbi_c[54]\); - - \AHB_Master_Out_pad[30]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[26]\, PAD => - AHB_Master_Out(30)); - - \AHB_Master_Out_pad[258]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(258)); - - \AHB_Master_Out_pad[144]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(144)); - - \apbo_pad[75]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(75)); - - \apbo_pad[24]\ : OUTBUF - port map(D => \apbo.prdata_c[24]\, PAD => apbo(24)); - - \AHB_Master_Out_pad[67]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[20]\, PAD => - AHB_Master_Out(67)); - - \apbo_pad[114]\ : OUTBUF - port map(D => \GND\, PAD => apbo(114)); - - \AHB_Master_Out_pad[304]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(304)); - - \apbo_pad[3]\ : OUTBUF - port map(D => \apbo.prdata_c[3]\, PAD => apbo(3)); - - \AHB_Master_Out_pad[315]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(315)); - - \AHB_Master_Out_pad[159]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(159)); - - \AHB_Master_Out_pad[69]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[22]\, PAD => - AHB_Master_Out(69)); - - \AHB_Master_Out_pad[325]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(325)); - - \AHB_Master_Out_pad[262]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(262)); - - \apbo_pad[64]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(64)); - - \AHB_Master_Out_pad[345]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(345)); - - \apbi_pad[21]\ : INBUF - port map(PAD => apbi(21), Y => \apbi_c[21]\); - - \apbo_pad[88]\ : OUTBUF - port map(D => \GND\, PAD => apbo(88)); - - \AHB_Master_Out_pad[164]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(164)); - - \apbo_pad[2]\ : OUTBUF - port map(D => \apbo.prdata_c[2]\, PAD => apbo(2)); - - \AHB_Master_Out_pad[36]\ : OUTBUF - port map(D => \AHB_Master_Out.hwrite_c\, PAD => - AHB_Master_Out(36)); - - \AHB_Master_Out_pad[338]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(338)); - - \AHB_Master_Out_pad[298]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(298)); - - \AHB_Master_Out_pad[75]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[28]\, PAD => - AHB_Master_Out(75)); - - \AHB_Master_Out_pad[172]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(172)); - - \AHB_Master_Out_pad[350]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(350)); - - \apbo_pad[100]\ : OUTBUF - port map(D => \GND\, PAD => apbo(100)); - - \AHB_Master_Out_pad[85]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(85)); - - \AHB_Master_Out_pad[205]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(205)); - - \sdo_pad[7]\ : INBUF - port map(PAD => sdo(7), Y => \sdo_c[7]\); - - \apbo_pad[52]\ : OUTBUF - port map(D => \GND\, PAD => apbo(52)); - - \AHB_Master_Out_pad[37]\ : OUTBUF - port map(D => \AHB_Master_Out.hsize_c[0]\, PAD => - AHB_Master_Out(37)); - - \AHB_Master_Out_pad[365]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(365)); - - \AHB_Master_Out_pad[199]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(199)); - - \apbi_pad[69]\ : INBUF - port map(PAD => apbi(69), Y => \apbi_c[69]\); - - \AHB_Master_Out_pad[113]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(113)); - - \AHB_Master_Out_pad[234]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(234)); - - \AHB_Master_Out_pad[123]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(123)); - - \apbo_pad[129]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(129)); - - \AHB_Master_Out_pad[39]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(39)); - - \AHB_Master_Out_pad[143]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(143)); - - HRESETn_pad : CLKBUF - port map(PAD => HRESETn, Y => HRESETn_c); - - \AHB_Master_Out_pad[94]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(94)); - - \AHB_Master_Out_pad[72]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[25]\, PAD => - AHB_Master_Out(72)); - - \AHB_Master_Out_pad[41]\ : OUTBUF - port map(D => \AHB_Master_Out.hburst_c[1]\, PAD => - AHB_Master_Out(41)); - - \apbo_pad[50]\ : OUTBUF - port map(D => \GND\, PAD => apbo(50)); - - \AHB_Master_Out_pad[233]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(233)); - - \AHB_Master_Out_pad[131]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(131)); - - \AHB_Master_Out_pad[8]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[4]\, PAD => - AHB_Master_Out(8)); - - \AHB_Master_Out_pad[82]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(82)); - - \AHB_Master_Out_pad[55]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[8]\, PAD => - AHB_Master_Out(55)); - - \AHB_Master_Out_pad[316]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(316)); - - \AHB_Master_Out_pad[326]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(326)); - - \AHB_Master_Out_pad[163]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(163)); - - \AHB_Master_Out_pad[152]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(152)); - - \AHB_Master_Out_pad[346]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(346)); - - GND_i_0 : GND - port map(Y => GND_0); - - \apbo_pad[86]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(86)); - - \sdo_pad[0]\ : INBUF - port map(PAD => sdo(0), Y => \sdo_c[0]\); - - \apbo_pad[51]\ : OUTBUF - port map(D => \GND\, PAD => apbo(51)); - - \apbo_pad[37]\ : OUTBUF - port map(D => \GND\, PAD => apbo(37)); - - \apbo_pad[55]\ : OUTBUF - port map(D => \GND\, PAD => apbo(55)); - - \apbi_pad[57]\ : INBUF - port map(PAD => apbi(57), Y => \apbi_c[57]\); - - \apbo_pad[27]\ : OUTBUF - port map(D => \apbo.prdata_c[27]\, PAD => apbo(27)); - - \AHB_Master_Out_pad[52]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[5]\, PAD => - AHB_Master_Out(52)); - - \AHB_Master_Out_pad[352]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(352)); - - \apbo_pad[99]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(99)); - - \apbo_pad[126]\ : OUTBUF - port map(D => \GND\, PAD => apbo(126)); - - \AHB_Master_Out_pad[272]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(272)); - - \AHB_Master_Out_pad[93]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(93)); - - \AHB_Master_Out_pad[366]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(366)); - - \AHB_Master_Out_pad[284]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(284)); - - \apbo_pad[117]\ : OUTBUF - port map(D => \GND\, PAD => apbo(117)); - - \AHB_Master_Out_pad[137]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(137)); - - \apbo_pad[33]\ : OUTBUF - port map(D => \GND\, PAD => apbo(33)); - - \AHB_Master_Out_pad[192]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(192)); - - \AHB_Master_Out_pad[174]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(174)); - - \apbo_pad[122]\ : OUTBUF - port map(D => \GND\, PAD => apbo(122)); - - \apbo_pad[67]\ : OUTBUF - port map(D => \GND\, PAD => apbo(67)); - - \apbi_pad[53]\ : INBUF - port map(PAD => apbi(53), Y => \apbi_c[53]\); - - \apbo_pad[23]\ : OUTBUF - port map(D => \apbo.prdata_c[23]\, PAD => apbo(23)); - - \AHB_Master_Out_pad[359]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(359)); - - \AHB_Master_Out_pad[314]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(314)); - - \AHB_Master_Out_pad[324]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(324)); - - \AHB_Master_Out_pad[283]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(283)); - - \AHB_Master_Out_pad[207]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(207)); - - \apbo_pad[78]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(78)); - - \AHB_Master_Out_pad[344]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(344)); - - \AHB_Master_Out_pad[181]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(181)); - - \AHB_Master_Out_pad[209]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(209)); - - \apbo_pad[63]\ : OUTBUF - port map(D => \GND\, PAD => apbo(63)); - - \apbo_pad[84]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(84)); - - \AHB_Master_Out_pad[364]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(364)); - - \AHB_Master_Out_pad[252]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(252)); - - \AHB_Master_Out_pad[100]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(100)); - - \AHB_Master_Out_pad[215]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(215)); - - \AHB_Master_Out_pad[225]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(225)); - - \AHB_Master_Out_pad[65]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[18]\, PAD => - AHB_Master_Out(65)); - - \AHB_Master_Out_pad[245]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(245)); - - \apbi_pad[0]\ : INBUF - port map(PAD => apbi(0), Y => \apbi_c[0]\); - - \AHB_Master_Out_pad[154]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(154)); - - \AHB_Master_Out_pad[74]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[27]\, PAD => - AHB_Master_Out(74)); - - \AHB_Master_Out_pad[106]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(106)); - - \AHB_Master_Out_pad[187]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(187)); - - \AHB_Master_Out_pad[84]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(84)); - - \AHB_Master_Out_pad[173]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(173)); - - \AHB_Master_Out_pad[18]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[14]\, PAD => - AHB_Master_Out(18)); - - \AHB_Master_Out_pad[231]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(231)); - - \AHB_Master_Out_pad[337]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(337)); - - \AHB_Master_Out_pad[355]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(355)); - - \AHB_Master_Out_pad[292]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(292)); - - \AHB_Master_Out_pad[265]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(265)); - - \AHB_Master_Out_pad[62]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[15]\, PAD => - AHB_Master_Out(62)); - - \apbo_pad[76]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(76)); - - \AHB_Master_Out_pad[10]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[6]\, PAD => - AHB_Master_Out(10)); - - \AHB_Master_Out_pad[9]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[5]\, PAD => - AHB_Master_Out(9)); - - \AHB_Master_Out_pad[194]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(194)); - - \AHB_Master_Out_pad[35]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[31]\, PAD => - AHB_Master_Out(35)); - - \AHB_Master_Out_pad[331]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(331)); - - \apbi_pad[72]\ : INBUF - port map(PAD => apbi(72), Y => \apbi_c[72]\); - - cnv_rstn_pad : INBUF - port map(PAD => cnv_rstn, Y => cnv_rstn_c); - - \AHB_Master_Out_pad[54]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[7]\, PAD => - AHB_Master_Out(54)); - - \apbo_pad[103]\ : OUTBUF - port map(D => \GND\, PAD => apbo(103)); - - \AHB_Master_Out_pad[73]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[26]\, PAD => - AHB_Master_Out(73)); - - \apbo_pad[9]\ : OUTBUF - port map(D => \apbo.prdata_c[9]\, PAD => apbo(9)); - - \apbo_pad[12]\ : OUTBUF - port map(D => \apbo.prdata_c[12]\, PAD => apbo(12)); - - \apbo_pad[110]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(110)); - - \AHB_Master_Out_pad[153]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(153)); - - \AHB_Master_Out_pad[83]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(83)); - - \AHB_Master_Out_pad[5]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[1]\, PAD => - AHB_Master_Out(5)); - - \AHB_Master_Out_pad[230]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(230)); - - \apbo_pad[58]\ : OUTBUF - port map(D => \GND\, PAD => apbo(58)); - - \apbi_pad[70]\ : INBUF - port map(PAD => apbi(70), Y => \apbi_c[70]\); - - \AHB_Master_Out_pad[16]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[12]\, PAD => - AHB_Master_Out(16)); - - \AHB_Master_Out_pad[135]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(135)); - - \AHB_Master_Out_pad[32]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[28]\, PAD => - AHB_Master_Out(32)); - - \AHB_Master_Out_pad[281]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(281)); - - \apbo_pad[10]\ : OUTBUF - port map(D => \apbo.prdata_c[10]\, PAD => apbo(10)); - - \AHB_Master_Out_pad[217]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(217)); - - \AHB_Master_Out_pad[227]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(227)); - - \AHB_Master_Out_pad[17]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[13]\, PAD => - AHB_Master_Out(17)); - - \AHB_Master_Out_pad[247]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(247)); - - \apbo_pad[87]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(87)); - - \apbo_pad[74]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(74)); - - \AHB_Master_Out_pad[236]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(236)); - - \AHB_Master_Out_pad[356]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(356)); - - \AHB_Master_Out_pad[219]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(219)); - - \apbo_pad[42]\ : OUTBUF - port map(D => \GND\, PAD => apbo(42)); - - \AHB_Master_Out_pad[229]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(229)); - - \AHB_Master_Out_pad[19]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[15]\, PAD => - AHB_Master_Out(19)); - - \apbi_pad[71]\ : INBUF - port map(PAD => apbi(71), Y => \apbi_c[71]\); - - \AHB_Master_Out_pad[53]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[6]\, PAD => - AHB_Master_Out(53)); - - \AHB_Master_Out_pad[249]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(249)); - - \AHB_Master_Out_pad[193]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(193)); - - \AHB_Master_Out_pad[138]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(138)); - - \apbi_pad[75]\ : INBUF - port map(PAD => apbi(75), Y => \apbi_c[75]\); - - \AHB_Master_Out_pad[28]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[24]\, PAD => - AHB_Master_Out(28)); - - \AHB_Master_Out_pad[91]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(91)); - - \apbo_pad[83]\ : OUTBUF - port map(D => \GND\, PAD => apbo(83)); - - \sdo_pad[6]\ : INBUF - port map(PAD => sdo(6), Y => \sdo_c[6]\); - - \apbo_pad[11]\ : OUTBUF - port map(D => \apbo.prdata_c[11]\, PAD => apbo(11)); - - \AHB_Master_Out_pad[110]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(110)); - - \apbo_pad[15]\ : OUTBUF - port map(D => \apbo.prdata_c[15]\, PAD => apbo(15)); - - \apbi_pad[24]\ : INBUF - port map(PAD => apbi(24), Y => \apbi_c[24]\); - - \AHB_Master_Out_pad[267]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(267)); - - \AHB_Master_Out_pad[120]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(120)); - - \AHB_Master_Out_pad[140]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(140)); - - \apbo_pad[40]\ : OUTBUF - port map(D => \GND\, PAD => apbo(40)); - - \AHB_Master_Out_pad[20]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[16]\, PAD => - AHB_Master_Out(20)); - - \AHB_Master_Out_pad[275]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(275)); - - \AHB_Master_Out_pad[116]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(116)); - - cnv_run_pad : INBUF - port map(PAD => cnv_run, Y => cnv_run_c); - - \AHB_Master_Out_pad[280]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(280)); - - \AHB_Master_Out_pad[269]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(269)); - - \AHB_Master_Out_pad[126]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(126)); - - \AHB_Master_Out_pad[185]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(185)); - - \AHB_Master_Out_pad[146]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(146)); - - \apbo_pad[128]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(128)); - - \AHB_Master_Out_pad[333]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(333)); - - \apbo_pad[56]\ : OUTBUF - port map(D => \GND\, PAD => apbo(56)); - - \apbi_pad[49]\ : INBUF - port map(PAD => apbi(49), Y => \apbi_c[49]\); - - \AHB_Master_Out_pad[64]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[17]\, PAD => - AHB_Master_Out(64)); - - \AHB_Master_Out_pad[354]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(354)); - - \AHB_Master_Out_pad[308]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(308)); - - cnv_clk_pad : INBUF - port map(PAD => cnv_clk, Y => cnv_clk_c); - - \AHB_Master_Out_pad[160]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(160)); - - \apbo_pad[41]\ : OUTBUF - port map(D => \GND\, PAD => apbo(41)); - - \apbo_pad[39]\ : OUTBUF - port map(D => \GND\, PAD => apbo(39)); - - \apbi_pad[19]\ : INBUF - port map(PAD => apbi(19), Y => \apbi_c[19]\); - - \AHB_Master_Out_pad[2]\ : OUTBUF - port map(D => \AHB_Master_Out.htrans_c[0]\, PAD => - AHB_Master_Out(2)); - - \apbo_pad[45]\ : OUTBUF - port map(D => \GND\, PAD => apbo(45)); - - \apbi_pad[62]\ : INBUF - port map(PAD => apbi(62), Y => \apbi_c[62]\); - - \AHB_Master_Out_pad[286]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(286)); - - \apbi_pad[59]\ : INBUF - port map(PAD => apbi(59), Y => \apbi_c[59]\); - - \AHB_Master_Out_pad[26]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[22]\, PAD => - AHB_Master_Out(26)); - - \apbo_pad[29]\ : OUTBUF - port map(D => \apbo.prdata_c[29]\, PAD => apbo(29)); - - \AHB_Master_Out_pad[166]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(166)); - - \AHB_Master_Out_pad[188]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(188)); - - \AHB_Master_Out_pad[238]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(238)); - - HCLK_pad : CLKBUF - port map(PAD => HCLK, Y => HCLK_c); - - \AHB_Master_Out_pad[204]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(204)); - - \AHB_Master_Out_pad[3]\ : OUTBUF - port map(D => \AHB_Master_Out.htrans_c[1]\, PAD => - AHB_Master_Out(3)); - - \AHB_Master_Out_pad[27]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[23]\, PAD => - AHB_Master_Out(27)); - - \AHB_Master_Out_pad[255]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(255)); - - \apbo_pad[69]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(69)); - - \apbi_pad[60]\ : INBUF - port map(PAD => apbi(60), Y => \apbi_c[60]\); - - \sdo_pad[2]\ : INBUF - port map(PAD => sdo(2), Y => \sdo_c[2]\); - - \AHB_Master_Out_pad[34]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[30]\, PAD => - AHB_Master_Out(34)); - - \AHB_Master_Out_pad[203]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(203)); - - \AHB_Master_Out_pad[139]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(139)); - - \AHB_Master_Out_pad[29]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[25]\, PAD => - AHB_Master_Out(29)); - - \AHB_Master_Out_pad[101]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(101)); - - \AHB_Master_Out_pad[63]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[16]\, PAD => - AHB_Master_Out(63)); - - \apbo_pad[109]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(109)); - - \apbo_pad[54]\ : OUTBUF - port map(D => \GND\, PAD => apbo(54)); - - \apbo_pad[77]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(77)); - - \apbi_pad[61]\ : INBUF - port map(PAD => apbi(61), Y => \apbi_c[61]\); - - \AHB_Master_Out_pad[330]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(330)); - - \apbo_pad[121]\ : OUTBUF - port map(D => \GND\, PAD => apbo(121)); - - \apbi_pad[65]\ : INBUF - port map(PAD => apbi(65), Y => \apbi_c[65]\); - - \AHB_Master_Out_pad[295]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(295)); - - \apbo_pad[92]\ : OUTBUF - port map(D => \GND\, PAD => apbo(92)); - - \AHB_Master_Out_pad[277]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(277)); - - \AHB_Master_Out_pad[71]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[24]\, PAD => - AHB_Master_Out(71)); - - \apbo_pad[73]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(73)); - - \AHB_Master_Out_pad[81]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(81)); - - \AHB_Master_Out_pad[279]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(279)); - - \apbo_pad[125]\ : OUTBUF - port map(D => \GND\, PAD => apbo(125)); - - \AHB_Master_Out_pad[288]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(288)); - - \AHB_Master_Out_pad[107]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(107)); - - \AHB_Master_Out_pad[48]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[1]\, PAD => - AHB_Master_Out(48)); - - \AHB_Master_Out_pad[33]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[29]\, PAD => - AHB_Master_Out(33)); - - -end DEF_ARCH; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp.vhd +++ /dev/null @@ -1,739 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2010, Aeroflex Gaisler AB - all rights reserved. --- --- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN --- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED --- IN ADVANCE IN WRITING. ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE GRLIB.DMA2AHB_Package.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; ---USE gaisler.pci.ALL; -USE gaisler.net.ALL; -USE gaisler.jtag.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; ---USE esa.pcicomp.ALL; -USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_bootloader_pkg.ALL; -use lpp.lpp_lfr_time_management.all; -- PLE -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - resetn : IN STD_ULOGIC; - clk : IN STD_ULOGIC; - pllref : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - dsutx : OUT STD_ULOGIC; -- DSU tx data - dsurx : IN STD_ULOGIC; -- DSU rx data - dsuen : IN STD_ULOGIC; - dsubre : IN STD_ULOGIC; - dsuact : OUT STD_ULOGIC; - txd1 : OUT STD_ULOGIC; -- UART1 tx data - rxd1 : IN STD_ULOGIC; -- UART1 rx data - txd2 : OUT STD_ULOGIC; -- UART2 tx data - rxd2 : IN STD_ULOGIC; -- UART2 rx data - ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - oen : OUT STD_ULOGIC; - writen : OUT STD_ULOGIC; - read : OUT STD_ULOGIC; - iosn : OUT STD_ULOGIC; - romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - emddis : OUT STD_LOGIC; - epwrdwn : OUT STD_ULOGIC; - ereset : OUT STD_ULOGIC; - esleep : OUT STD_ULOGIC; - epause : OUT STD_ULOGIC; - - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC; - pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - spw_clk : IN STD_ULOGIC; - spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - ramclk : OUT STD_LOGIC; - - nBWa : OUT STD_LOGIC; - nBWb : OUT STD_LOGIC; - nBWc : OUT STD_LOGIC; - nBWd : OUT STD_LOGIC; - nBWE : OUT STD_LOGIC; - nADSC : OUT STD_LOGIC; - nADSP : OUT STD_LOGIC; - nADV : OUT STD_LOGIC; - nGW : OUT STD_LOGIC; - nCE1 : OUT STD_LOGIC; - CE2 : OUT STD_LOGIC; - nCE3 : OUT STD_LOGIC; - nOE : OUT STD_LOGIC; - MODE : OUT STD_LOGIC; - SSRAM_CLK : OUT STD_LOGIC; - ZZ : OUT STD_LOGIC; - - tck, tms, tdi : IN STD_ULOGIC; - tdo : OUT STD_ULOGIC; - - -- waveform picker------ - clk49_152MHz : in std_ulogic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic - - - ); -END; - -ARCHITECTURE rtl OF leon3mp IS - - CONSTANT blength : INTEGER := 12; - - CONSTANT maxahbmsp : INTEGER := NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI); - CONSTANT maxahbm : INTEGER := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp + 2; -- +LPP_DMA - - - - SIGNAL vcc, gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdi : sdctrl_in_type; - SIGNAL sdo : sdram_out_type; - SIGNAL sdo2, sdo3 : sdctrl_out_type; - - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - - SIGNAL clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; - SIGNAL u1i, u2i, dui : uart_in_type; - SIGNAL u1o, u2o, duo : uart_out_type; - - SIGNAL irqi : irq_in_vector(0 TO NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO NCPU-1); - - SIGNAL dbgi : l3_debug_in_vector(0 TO NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO NCPU-1); - - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - - -- SIGNAL pcii : pci_in_type; --- SIGNAL pcio : pci_out_type; - - SIGNAL ethi, ethi1, ethi2 : eth_in_type; - SIGNAL etho, etho1, etho2 : eth_out_type; - - SIGNAL gpti : gptimer_in_type; - - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - - - SIGNAL lclk, pci_lclk : STD_ULOGIC := '0'; - SIGNAL pci_arb_req_n, pci_arb_gnt_n : STD_LOGIC_VECTOR(0 TO 3); - - SIGNAL spwi : grspw_in_type_vector(0 TO 2); - SIGNAL spwo : grspw_out_type_vector(0 TO 2); - SIGNAL spw_rx_clk : STD_ULOGIC; - - ATTRIBUTE sync_set_reset : STRING; - ATTRIBUTE sync_set_reset OF rstn : SIGNAL IS "true"; - - CONSTANT BOARD_FREQ : INTEGER := 40000; -- Board frequency in KHz - CONSTANT CPU_FREQ : INTEGER := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; - CONSTANT IOAEN : INTEGER := CFG_SDCTRL; - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - - CONSTANT sysfreq : INTEGER := (CFG_CLKMUL/CFG_CLKDIV)*40000; - - ----------------------------------------------------------------------------- - - SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fifo_empty : STD_LOGIC; - SIGNAL fifo_ren : STD_LOGIC; - SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL dma_empty : STD_LOGIC; - SIGNAL dma_ren : STD_LOGIC; - SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL header_val : STD_LOGIC; - SIGNAL header_ack : STD_LOGIC; - - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - - CONSTANT boardfreq : INTEGER := 50000; - - signal coarse_time : std_logic_vector(31 downto 0); - signal fine_time : std_logic_vector(31 downto 0); - -BEGIN - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); - gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; - cgi.pllrst <= rstraw; - - pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref); - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x); - - PROCESS(lclk2x) - BEGIN - IF lclk2x'EVENT AND lclk2x = '1' THEN - lclk <= NOT lclk; - END IF; - END PROCESS; - - pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk, lclk, clkm, OPEN, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; - - rst0 : rstgen -- reset generator - PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw); - ----------------------------------------------------------------------- ---- AHB CONTROLLER -------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- LEON3 processor and DSU ----------------------------------------- ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : odpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsuen_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsuen, dsui.enable); - dsubre_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsubre, dsui.break); - dsuact_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsuact, dsuo.active); - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart -- Debug UART - GENERIC MAP (hindex => NCPU, pindex => 7, paddr => 7) - PORT MAP (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsurx, dui.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsutx, duo.txd); - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(7) <= apb_none; END GENERATE; - - ahbjtaggen0 : IF CFG_AHB_JTAG = 1 GENERATE - ahbjtag0 : ahbjtag GENERIC MAP(tech => fabtech, hindex => NCPU+CFG_AHB_UART) - PORT MAP(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), - OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, gnd(0)); - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers ---------------------------------------------- ----------------------------------------------------------------------- --- LEON2 memory controller - sr1 : mctrl - GENERIC MAP ( - hindex => 0, - pindex => 0, - romaddr => 16#000#, - rommask => 16#E00#, - ioaddr => 16#200#, - iomask => 16#E00#, - ramaddr => 16#400#, - rammask => 16#C00#, - paddr => 0, - pmask => 16#fff#, - wprot => 0, - invclk => 0, - fast => 0, - romasel => 28, - sdrasel => 29, - srbanks => 4, - ram8 => 0, - ram16 => 0, - sden => 0, - sepbus => 0, - sdbits => 32, - sdlsb => 2, -- set to 12 for the GE-HPE board - oepol => 0, - syncrst => 0, - pageburst => 0, - scantest => 0, - mobile => 0 - ) - PORT MAP ( - rst => rstn, - clk => clkm, - memi => memi, - memo => memo, - ahbsi => ahbsi, - ahbso => ahbso(0), - apbi => apbi, - apbo => apbo(0), - wpo => wpo, - sdo => sdo - ); - - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads - addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0)); - rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0)); - roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0)); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (oen, memo.oen); - rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn); - roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0)); - wri_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (writen, memo.writen); - read_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (read, memo.read); - iosn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (iosn, memo.iosn); - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP (data(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - END GENERATE; - - SSRAM_0 : ssram_plugin - GENERIC MAP (tech => padtech) - PORT MAP (lclk2x, memo, SSRAM_CLK, - nBWa, nBWb, nBWc, nBWd, nBWE, nADSC, nADSP, nADV, nGW, nCE1, CE2, nCE3, nOE, MODE, ZZ); - - - ----------------------------------------------------------------------- ---- APB Bridge and various periherals ------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), u1i, u1o); - u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - - ua2 : IF CFG_UART2_ENABLE /= 0 GENERATE - uart2 : apbuart -- UART 2 - GENERIC MAP (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(9), u2i, u2o); - u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd; - END GENERATE; - noua1 : IF CFG_UART2_ENABLE = 0 GENERATE apbo(9) <= apb_none; END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, OPEN); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - gpio0 : IF CFG_GRGPIO_ENABLE /= 0 GENERATE -- GR GPIO unit - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, - nbits => CFG_GRGPIO_WIDTH) - PORT MAP(rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : FOR i IN 0 TO CFG_GRGPIO_WIDTH-1 GENERATE - pio_pad : iopad GENERIC MAP (tech => padtech) - PORT MAP (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - END GENERATE; - END GENERATE; - ------------------------------------------------------------------------ ---- PCI ------------------------------------------------------------ ------------------------------------------------------------------------ - - --pp : IF CFG_PCI /= 0 GENERATE - - -- pci_gr0 : IF CFG_PCI = 1 GENERATE -- simple target-only - -- pci0 : pci_target GENERIC MAP (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- device_id => CFG_PCIDID, vendor_id => CFG_PCIVID) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG)); - -- END GENERATE; - - -- pci_mtf0 : IF CFG_PCI = 2 GENERATE -- master/target with fifo - -- pci0 : pci_mtf GENERIC MAP (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - -- hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, - -- ioaddr => 16#400#, nsync => 2, hostrst => 1) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4), - -- ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - -- END GENERATE; - - -- pci_mtf1 : IF CFG_PCI = 3 GENERATE -- master/target with fifo and DMA - -- dma : pcidma GENERIC MAP (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1, - -- dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - -- slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, - -- nsync => 2, hostrst => 1) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1), - -- apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - -- END GENERATE; - - -- pci_trc0 : IF CFG_PCITBUFEN /= 0 GENERATE -- PCI trace buffer - -- pt0 : pcitrace GENERIC MAP (depth => (6 + log2(CFG_PCITBUF/256)), - -- memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#) - -- PORT MAP (rstn, clkm, pciclk, pcii, apbi, apbo(8)); - -- END GENERATE; - - -- pcia0 : IF CFG_PCI_ARB = 1 GENERATE -- PCI arbiter - -- pciarb0 : pciarb GENERIC MAP (pindex => 10, paddr => 10, - -- apb_en => CFG_PCI_ARBAPB) - -- PORT MAP (clk => pciclk, rst_n => pcii.rst, - -- req_n => pci_arb_req_n, frame_n => pcii.frame, - -- gnt_n => pci_arb_gnt_n, pclk => clkm, - -- prst_n => rstn, apbi => apbi, apbo => apbo(10) - -- ); - -- pgnt_pad : outpadv GENERIC MAP (tech => padtech, width => 4) - -- PORT MAP (pci_arb_gnt, pci_arb_gnt_n); - -- preq_pad : inpadv GENERIC MAP (tech => padtech, width => 4) - -- PORT MAP (pci_arb_req, pci_arb_req_n); - -- END GENERATE; - - -- pcipads0 : pcipads GENERIC MAP (padtech => padtech) -- PCI pads - -- PORT MAP (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - -- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, - -- pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio); - - --END GENERATE; - --- nop1 : IF CFG_PCI <= 1 GENERATE apbo(4) <= apb_none; END GENERATE; --- nop2 : IF CFG_PCI <= 2 GENERATE apbo(5) <= apb_none; END GENERATE; - nop3 : IF CFG_PCI <= 1 GENERATE ahbso(4) <= ahbs_none; END GENERATE; - notrc : IF CFG_PCITBUFEN = 0 GENERATE apbo(8) <= apb_none; END GENERATE; - noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE; - pci_rst <= '0'; - pci_lock <= '0'; - pci_ad <= (OTHERS => '0'); - pci_cbe <= (OTHERS => '0'); - pci_frame <= '0'; - pci_irdy <= '0'; - pci_trdy <= '0'; - pci_devsel <= '0'; - pci_stop <= '0'; - pci_perr <= '0'; - pci_par <= '0'; - pci_req <= '0'; - pci_serr <= '0'; - pci_arb_gnt <= (OTHERS => '0'); - - --- ahbso(6) <= ahbs_none; - ------------------------------------------------------------------------ ---- AHB RAM ---------------------------------------------------------- ------------------------------------------------------------------------ - - ocram : IF CFG_AHBRAMEN = 1 GENERATE - ahbram0 : ahbram GENERIC MAP (hindex => 7, haddr => CFG_AHBRADDR, - tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) - PORT MAP (rstn, clkm, ahbsi, ahbso(7)); - END GENERATE; - nram : IF CFG_AHBRAMEN = 0 GENERATE ahbso(7) <= ahbs_none; END GENERATE; - ------------------------------------------------------------------------ ---- SPACEWIRE ------------------------------------------------------- ------------------------------------------------------------------------ - --This template does NOT currently support grspw2 so only use grspw1 - spw : IF CFG_SPW_EN > 0 GENERATE - spw_rx_clk <= '0'; - spw_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (spw_clk, spw_lclk); - swloop : FOR i IN 0 TO CFG_SPW_NUM-1 GENERATE - sw0 : grspwm GENERIC MAP(tech => memtech, netlist => CFG_SPW_NETLIST, - hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i, - sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1, - fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO, - rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW) - PORT MAP(resetn, clkm, spw_rx_clk, spw_rx_clk, spw_lclk, spw_lclk, - ahbmi, ahbmo(maxahbmsp+i), - apbi, apbo(12+i), spwi(i), spwo(i)); - spwi(i).tickin <= '0'; spwi(i).rmapen <= '1'; - spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8); - spw_rxd_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxd(i), spw_rxdn(i), spwi(i).d(0)); - spw_rxs_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxs(i), spw_rxsn(i), spwi(i).s(0)); - spw_txd_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0)); - spw_txs_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0)); - END GENERATE; - END GENERATE; - no_spw: IF CFG_SPW_EN = 0 GENERATE - spw_txd <= (OTHERS => '0'); - spw_txdn <= (OTHERS => '0'); - spw_txs <= (OTHERS => '0'); - spw_txsn <= (OTHERS => '0'); - END GENERATE no_spw; - - - -------------------------------------------------------------------------------- --- BOOT MEMORY AND REGISTER -------------------------------------------------------------------------------- - - lpp_bootloader_1 : lpp_bootloader - GENERIC MAP ( - pindex => 13, - paddr => 13, - pmask => 16#fff#, - - hindex => 6, - haddr => 16#900#, - hmask => 16#F00#) - PORT MAP ( - HCLK => clkm, - HRESETn => resetn, - apbi => apbi, - apbo => apbo(13), - ahbsi => ahbsi, - ahbso => ahbso(6)); - - -------------------------------------------------------------------------------- --- AHB DMA -------------------------------------------------------------------------------- - - --lpp_dma_1 : lpp_dma - -- GENERIC MAP ( - -- tech => fabtech, - -- hindex => 2, - -- pindex => 14, - -- paddr => 14, - -- pmask => 16#fff#, - -- pirq => 0) - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- apbi => apbi, - -- apbo => apbo(14), - -- AHB_Master_In => ahbmi, - -- AHB_Master_Out => ahbmo(2), - -- fifo_data => fifo_data, --dma_data, - -- fifo_empty => fifo_empty, --dma_empty, - -- fifo_ren => fifo_ren, --dma_ren, - -- header => header, - -- header_val => header_val, - -- header_ack => header_ack); - - --fifo_test_dma_1 : fifo_test_dma - -- GENERIC MAP ( - -- tech => fabtech, - -- pindex => 15, - -- paddr => 15, - -- pmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- apbi => apbi, - -- apbo => apbo(15), - -- fifo_data => fifo_data, - -- fifo_empty => fifo_empty, - -- fifo_ren => fifo_ren, - -- header => header, - -- header_val => header_val, - -- header_ack => header_ack); - --------------------------- --- APB_LFR_TIME_MANAGEMENT --------------------------- - lfrtimemanagement_0 : apb_lfr_time_management - generic map( - pindex => 15, - paddr => 15, - pmask => 16#fff#, - masterclk => 25000000, - timeclk => 49152000, - finetimeclk => 65536, - pirq => 12) -- the IP uses 2 consecutive IRQ lines - port map( - clkm, - clk49_152MHz, - rstn, - '0', - apbi, - apbo(15), - coarse_time, - fine_time); - ------------------- --- WAVEFORM PICKER ------------------- - waveform_picker0 : lpp_top_lfr_wf_picker - GENERIC MAP( - hindex => 3, - pindex => 14, - paddr => 14, - pmask => 16#fff#, - pirq => 15, - tech => CFG_FABTECH, - nb_burst_available_size => 11, -- size of the register holding the nb of burst - nb_snapshot_param_size => 11, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 10, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 10 -- nb f0 ticks before starting the f1 snapshot - ) - PORT MAP( - -- ADS7886 - cnv_run => '1', -- stop the sampling request - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(14), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(3), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => Bias_Fails - ); - ------------------------------------------------------------------------ ---- Boot message ---------------------------------------------------- ------------------------------------------------------------------------ - --- pragma translate_off - x : report_version - GENERIC MAP ( - msg1 => "LEON3 MP Demonstration design", - msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION MOD 1000)/100) - & "." & tost(LIBVHDL_VERSION MOD 100) & ", build " & tost(LIBVHDL_BUILD), - msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech), - mdel => 1 - ); --- pragma translate_on -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp_post.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp_post.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp_post.vhd +++ /dev/null @@ -1,758 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2010, Aeroflex Gaisler AB - all rights reserved. --- --- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN --- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED --- IN ADVANCE IN WRITING. ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE GRLIB.DMA2AHB_Package.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; ---USE gaisler.pci.ALL; -USE gaisler.net.ALL; -USE gaisler.jtag.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; ---USE esa.pcicomp.ALL; -USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_bootloader_pkg.ALL; -use lpp.lpp_lfr_time_management.all; -- PLE -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_memory.ALL; ---USE lpp.lpp_top_lfr_pkg.ALL; - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - resetn : IN STD_ULOGIC; - clk : IN STD_ULOGIC; - pllref : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - dsutx : OUT STD_ULOGIC; -- DSU tx data - dsurx : IN STD_ULOGIC; -- DSU rx data - dsuen : IN STD_ULOGIC; - dsubre : IN STD_ULOGIC; - dsuact : OUT STD_ULOGIC; - txd1 : OUT STD_ULOGIC; -- UART1 tx data - rxd1 : IN STD_ULOGIC; -- UART1 rx data - txd2 : OUT STD_ULOGIC; -- UART2 tx data - rxd2 : IN STD_ULOGIC; -- UART2 rx data - ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - oen : OUT STD_ULOGIC; - writen : OUT STD_ULOGIC; - read : OUT STD_ULOGIC; - iosn : OUT STD_ULOGIC; - romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - emddis : OUT STD_LOGIC; - epwrdwn : OUT STD_ULOGIC; - ereset : OUT STD_ULOGIC; - esleep : OUT STD_ULOGIC; - epause : OUT STD_ULOGIC; - - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC; - pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - spw_clk : IN STD_ULOGIC; - spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - ramclk : OUT STD_LOGIC; - - nBWa : OUT STD_LOGIC; - nBWb : OUT STD_LOGIC; - nBWc : OUT STD_LOGIC; - nBWd : OUT STD_LOGIC; - nBWE : OUT STD_LOGIC; - nADSC : OUT STD_LOGIC; - nADSP : OUT STD_LOGIC; - nADV : OUT STD_LOGIC; - nGW : OUT STD_LOGIC; - nCE1 : OUT STD_LOGIC; - CE2 : OUT STD_LOGIC; - nCE3 : OUT STD_LOGIC; - nOE : OUT STD_LOGIC; - MODE : OUT STD_LOGIC; - SSRAM_CLK : OUT STD_LOGIC; - ZZ : OUT STD_LOGIC; - - tck, tms, tdi : IN STD_ULOGIC; - tdo : OUT STD_ULOGIC; - - -- waveform picker------ - clk49_152MHz : in std_ulogic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic - - - ); -END; - -ARCHITECTURE rtl OF leon3mp IS - - CONSTANT blength : INTEGER := 12; - - CONSTANT maxahbmsp : INTEGER := NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI); - CONSTANT maxahbm : INTEGER := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp + 2; -- +LPP_DMA - - - - SIGNAL vcc, gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdi : sdctrl_in_type; - SIGNAL sdo : sdram_out_type; - SIGNAL sdo2, sdo3 : sdctrl_out_type; - - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - - SIGNAL clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; - SIGNAL u1i, u2i, dui : uart_in_type; - SIGNAL u1o, u2o, duo : uart_out_type; - - SIGNAL irqi : irq_in_vector(0 TO NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO NCPU-1); - - SIGNAL dbgi : l3_debug_in_vector(0 TO NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO NCPU-1); - - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - - -- SIGNAL pcii : pci_in_type; --- SIGNAL pcio : pci_out_type; - - SIGNAL ethi, ethi1, ethi2 : eth_in_type; - SIGNAL etho, etho1, etho2 : eth_out_type; - - SIGNAL gpti : gptimer_in_type; - - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - - - SIGNAL lclk, pci_lclk : STD_ULOGIC := '0'; - SIGNAL pci_arb_req_n, pci_arb_gnt_n : STD_LOGIC_VECTOR(0 TO 3); - - SIGNAL spwi : grspw_in_type_vector(0 TO 2); - SIGNAL spwo : grspw_out_type_vector(0 TO 2); - SIGNAL spw_rx_clk : STD_ULOGIC; - - ATTRIBUTE sync_set_reset : STRING; - ATTRIBUTE sync_set_reset OF rstn : SIGNAL IS "true"; - - CONSTANT BOARD_FREQ : INTEGER := 40000; -- Board frequency in KHz - CONSTANT CPU_FREQ : INTEGER := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; - CONSTANT IOAEN : INTEGER := CFG_SDCTRL; - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - - CONSTANT sysfreq : INTEGER := (CFG_CLKMUL/CFG_CLKDIV)*40000; - - ----------------------------------------------------------------------------- - - SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fifo_empty : STD_LOGIC; - SIGNAL fifo_ren : STD_LOGIC; - SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL dma_empty : STD_LOGIC; - SIGNAL dma_ren : STD_LOGIC; - SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL header_val : STD_LOGIC; - SIGNAL header_ack : STD_LOGIC; - - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - - CONSTANT boardfreq : INTEGER := 50000; - - signal coarse_time : std_logic_vector(31 downto 0); - signal fine_time : std_logic_vector(31 downto 0); - - COMPONENT lpp_top_lfr_wf_picker - PORT ( - cnv_run : in std_logic; - cnv : out std_logic; - sck : out std_logic; - sdo : in std_logic_vector(7 downto 0); - cnv_clk : in std_logic; - cnv_rstn : in std_logic; - HCLK : in std_logic; - HRESETn : in std_logic; - apbi : in std_logic_vector(121 downto 0); - apbo : out std_logic_vector(131 downto 0); - AHB_Master_In : in std_logic_vector(90 downto 0); - AHB_Master_Out : out std_logic_vector(370 downto 0); - coarse_time_0 : in std_logic; - data_shaping_BW : out std_logic); - END COMPONENT; - -BEGIN - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); - gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; - cgi.pllrst <= rstraw; - - pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref); - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x); - - PROCESS(lclk2x) - BEGIN - IF lclk2x'EVENT AND lclk2x = '1' THEN - lclk <= NOT lclk; - END IF; - END PROCESS; - - pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk, lclk, clkm, OPEN, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; - - rst0 : rstgen -- reset generator - PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw); - ----------------------------------------------------------------------- ---- AHB CONTROLLER -------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- LEON3 processor and DSU ----------------------------------------- ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : odpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsuen_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsuen, dsui.enable); - dsubre_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsubre, dsui.break); - dsuact_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsuact, dsuo.active); - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart -- Debug UART - GENERIC MAP (hindex => NCPU, pindex => 7, paddr => 7) - PORT MAP (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsurx, dui.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsutx, duo.txd); - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(7) <= apb_none; END GENERATE; - - ahbjtaggen0 : IF CFG_AHB_JTAG = 1 GENERATE - ahbjtag0 : ahbjtag GENERIC MAP(tech => fabtech, hindex => NCPU+CFG_AHB_UART) - PORT MAP(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), - OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, gnd(0)); - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers ---------------------------------------------- ----------------------------------------------------------------------- --- LEON2 memory controller - sr1 : mctrl - GENERIC MAP ( - hindex => 0, - pindex => 0, - romaddr => 16#000#, - rommask => 16#E00#, - ioaddr => 16#200#, - iomask => 16#E00#, - ramaddr => 16#400#, - rammask => 16#C00#, - paddr => 0, - pmask => 16#fff#, - wprot => 0, - invclk => 0, - fast => 0, - romasel => 28, - sdrasel => 29, - srbanks => 4, - ram8 => 0, - ram16 => 0, - sden => 0, - sepbus => 0, - sdbits => 32, - sdlsb => 2, -- set to 12 for the GE-HPE board - oepol => 0, - syncrst => 0, - pageburst => 0, - scantest => 0, - mobile => 0 - ) - PORT MAP ( - rst => rstn, - clk => clkm, - memi => memi, - memo => memo, - ahbsi => ahbsi, - ahbso => ahbso(0), - apbi => apbi, - apbo => apbo(0), - wpo => wpo, - sdo => sdo - ); - - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads - addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0)); - rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0)); - roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0)); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (oen, memo.oen); - rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn); - roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0)); - wri_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (writen, memo.writen); - read_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (read, memo.read); - iosn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (iosn, memo.iosn); - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP (data(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - END GENERATE; - - SSRAM_0 : ssram_plugin - GENERIC MAP (tech => padtech) - PORT MAP (lclk2x, memo, SSRAM_CLK, - nBWa, nBWb, nBWc, nBWd, nBWE, nADSC, nADSP, nADV, nGW, nCE1, CE2, nCE3, nOE, MODE, ZZ); - - - ----------------------------------------------------------------------- ---- APB Bridge and various periherals ------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), u1i, u1o); - u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - - ua2 : IF CFG_UART2_ENABLE /= 0 GENERATE - uart2 : apbuart -- UART 2 - GENERIC MAP (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(9), u2i, u2o); - u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd; - END GENERATE; - noua1 : IF CFG_UART2_ENABLE = 0 GENERATE apbo(9) <= apb_none; END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, OPEN); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - gpio0 : IF CFG_GRGPIO_ENABLE /= 0 GENERATE -- GR GPIO unit - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, - nbits => CFG_GRGPIO_WIDTH) - PORT MAP(rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : FOR i IN 0 TO CFG_GRGPIO_WIDTH-1 GENERATE - pio_pad : iopad GENERIC MAP (tech => padtech) - PORT MAP (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - END GENERATE; - END GENERATE; - ------------------------------------------------------------------------ ---- PCI ------------------------------------------------------------ ------------------------------------------------------------------------ - - --pp : IF CFG_PCI /= 0 GENERATE - - -- pci_gr0 : IF CFG_PCI = 1 GENERATE -- simple target-only - -- pci0 : pci_target GENERIC MAP (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- device_id => CFG_PCIDID, vendor_id => CFG_PCIVID) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG)); - -- END GENERATE; - - -- pci_mtf0 : IF CFG_PCI = 2 GENERATE -- master/target with fifo - -- pci0 : pci_mtf GENERIC MAP (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - -- hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, - -- ioaddr => 16#400#, nsync => 2, hostrst => 1) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4), - -- ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - -- END GENERATE; - - -- pci_mtf1 : IF CFG_PCI = 3 GENERATE -- master/target with fifo and DMA - -- dma : pcidma GENERIC MAP (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1, - -- dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - -- slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, - -- nsync => 2, hostrst => 1) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1), - -- apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - -- END GENERATE; - - -- pci_trc0 : IF CFG_PCITBUFEN /= 0 GENERATE -- PCI trace buffer - -- pt0 : pcitrace GENERIC MAP (depth => (6 + log2(CFG_PCITBUF/256)), - -- memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#) - -- PORT MAP (rstn, clkm, pciclk, pcii, apbi, apbo(8)); - -- END GENERATE; - - -- pcia0 : IF CFG_PCI_ARB = 1 GENERATE -- PCI arbiter - -- pciarb0 : pciarb GENERIC MAP (pindex => 10, paddr => 10, - -- apb_en => CFG_PCI_ARBAPB) - -- PORT MAP (clk => pciclk, rst_n => pcii.rst, - -- req_n => pci_arb_req_n, frame_n => pcii.frame, - -- gnt_n => pci_arb_gnt_n, pclk => clkm, - -- prst_n => rstn, apbi => apbi, apbo => apbo(10) - -- ); - -- pgnt_pad : outpadv GENERIC MAP (tech => padtech, width => 4) - -- PORT MAP (pci_arb_gnt, pci_arb_gnt_n); - -- preq_pad : inpadv GENERIC MAP (tech => padtech, width => 4) - -- PORT MAP (pci_arb_req, pci_arb_req_n); - -- END GENERATE; - - -- pcipads0 : pcipads GENERIC MAP (padtech => padtech) -- PCI pads - -- PORT MAP (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - -- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, - -- pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio); - - --END GENERATE; - --- nop1 : IF CFG_PCI <= 1 GENERATE apbo(4) <= apb_none; END GENERATE; --- nop2 : IF CFG_PCI <= 2 GENERATE apbo(5) <= apb_none; END GENERATE; - nop3 : IF CFG_PCI <= 1 GENERATE ahbso(4) <= ahbs_none; END GENERATE; - notrc : IF CFG_PCITBUFEN = 0 GENERATE apbo(8) <= apb_none; END GENERATE; - noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE; - pci_rst <= '0'; - pci_lock <= '0'; - pci_ad <= (OTHERS => '0'); - pci_cbe <= (OTHERS => '0'); - pci_frame <= '0'; - pci_irdy <= '0'; - pci_trdy <= '0'; - pci_devsel <= '0'; - pci_stop <= '0'; - pci_perr <= '0'; - pci_par <= '0'; - pci_req <= '0'; - pci_serr <= '0'; - pci_arb_gnt <= (OTHERS => '0'); - - --- ahbso(6) <= ahbs_none; - ------------------------------------------------------------------------ ---- AHB RAM ---------------------------------------------------------- ------------------------------------------------------------------------ - - ocram : IF CFG_AHBRAMEN = 1 GENERATE - ahbram0 : ahbram GENERIC MAP (hindex => 7, haddr => CFG_AHBRADDR, - tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) - PORT MAP (rstn, clkm, ahbsi, ahbso(7)); - END GENERATE; - nram : IF CFG_AHBRAMEN = 0 GENERATE ahbso(7) <= ahbs_none; END GENERATE; - ------------------------------------------------------------------------ ---- SPACEWIRE ------------------------------------------------------- ------------------------------------------------------------------------ - --This template does NOT currently support grspw2 so only use grspw1 - spw : IF CFG_SPW_EN > 0 GENERATE - spw_rx_clk <= '0'; - spw_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (spw_clk, spw_lclk); - swloop : FOR i IN 0 TO CFG_SPW_NUM-1 GENERATE - sw0 : grspwm GENERIC MAP(tech => memtech, netlist => CFG_SPW_NETLIST, - hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i, - sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1, - fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO, - rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW) - PORT MAP(resetn, clkm, spw_rx_clk, spw_rx_clk, spw_lclk, spw_lclk, - ahbmi, ahbmo(maxahbmsp+i), - apbi, apbo(12+i), spwi(i), spwo(i)); - spwi(i).tickin <= '0'; spwi(i).rmapen <= '1'; - spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8); - spw_rxd_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxd(i), spw_rxdn(i), spwi(i).d(0)); - spw_rxs_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxs(i), spw_rxsn(i), spwi(i).s(0)); - spw_txd_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0)); - spw_txs_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0)); - END GENERATE; - END GENERATE; - no_spw: IF CFG_SPW_EN = 0 GENERATE - spw_txd <= (OTHERS => '0'); - spw_txdn <= (OTHERS => '0'); - spw_txs <= (OTHERS => '0'); - spw_txsn <= (OTHERS => '0'); - END GENERATE no_spw; - - - -------------------------------------------------------------------------------- --- BOOT MEMORY AND REGISTER -------------------------------------------------------------------------------- - - lpp_bootloader_1 : lpp_bootloader - GENERIC MAP ( - pindex => 13, - paddr => 13, - pmask => 16#fff#, - - hindex => 6, - haddr => 16#900#, - hmask => 16#F00#) - PORT MAP ( - HCLK => clkm, - HRESETn => resetn, - apbi => apbi, - apbo => apbo(13), - ahbsi => ahbsi, - ahbso => ahbso(6)); - - -------------------------------------------------------------------------------- --- AHB DMA -------------------------------------------------------------------------------- - - --lpp_dma_1 : lpp_dma - -- GENERIC MAP ( - -- tech => fabtech, - -- hindex => 2, - -- pindex => 14, - -- paddr => 14, - -- pmask => 16#fff#, - -- pirq => 0) - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- apbi => apbi, - -- apbo => apbo(14), - -- AHB_Master_In => ahbmi, - -- AHB_Master_Out => ahbmo(2), - -- fifo_data => fifo_data, --dma_data, - -- fifo_empty => fifo_empty, --dma_empty, - -- fifo_ren => fifo_ren, --dma_ren, - -- header => header, - -- header_val => header_val, - -- header_ack => header_ack); - - --fifo_test_dma_1 : fifo_test_dma - -- GENERIC MAP ( - -- tech => fabtech, - -- pindex => 15, - -- paddr => 15, - -- pmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- apbi => apbi, - -- apbo => apbo(15), - -- fifo_data => fifo_data, - -- fifo_empty => fifo_empty, - -- fifo_ren => fifo_ren, - -- header => header, - -- header_val => header_val, - -- header_ack => header_ack); - --------------------------- --- APB_LFR_TIME_MANAGEMENT --------------------------- - lfrtimemanagement_0 : apb_lfr_time_management - generic map( - pindex => 15, - paddr => 15, - pmask => 16#fff#, - masterclk => 25000000, - otherclk => 49152000, - finetimeclk => 65536, - pirq => 12) -- the IP uses 2 consecutive IRQ lines - port map( - clkm, - clk49_152MHz, - rstn, - '0', - apbi, - apbo(15), - coarse_time, - fine_time); - ------------------- --- WAVEFORM PICKER ------------------- --- waveform_picker0 : lpp_top_lfr_wf_picker --- GENERIC MAP( --- hindex => 3, --- pindex => 14, --- paddr => 14, --- pmask => 16#fff#, --- pirq => 15, - -- tech => CFG_FABTECH, --- nb_burst_available_size => 11, -- size of the register holding the nb of burst --- nb_snapshot_param_size => 11, -- size of the register holding the snapshots size --- delta_snapshot_size => 16, -- snapshots period --- delta_f2_f0_size => 10, -- initialize the counter when the f2 snapshot starts --- delta_f2_f1_size => 10 -- nb f0 ticks before starting the f1 snapshot --- ) - waveform_picker0 : lpp_top_lfr_wf_picker - PORT MAP( - -- ADS7886 - cnv_run => '1', -- stop the sampling request - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(14), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(3), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => Bias_Fails - ); - ------------------------------------------------------------------------ ---- Boot message ---------------------------------------------------- ------------------------------------------------------------------------ - --- pragma translate_off - x : report_version - GENERIC MAP ( - msg1 => "LEON3 MP Demonstration design", - msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION MOD 1000)/100) - & "." & tost(LIBVHDL_VERSION MOD 100) & ", build " & tost(LIBVHDL_BUILD), - msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech), - mdel => 1 - ); --- pragma translate_on -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp_wfp_post.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp_wfp_post.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/leon3mp_wfp_post.vhd +++ /dev/null @@ -1,192155 +0,0 @@ --- Version: 9.1 SP5 9.1.5.1 - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity gptimer is - - port( scaler_4 : out std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_0 : in std_logic; - pwdata_1_2 : in std_logic; - paddr : in std_logic_vector(6 downto 2); - value_6 : out std_logic; - value_0 : out std_logic; - paddr_2 : in std_logic_vector(2 to 2); - pirq : out std_logic_vector(9 downto 8); - readdata_9_5 : out std_logic; - readdata_9_0 : out std_logic; - readdata_9_27 : out std_logic; - readdata_9_4 : out std_logic; - paddr_1 : in std_logic_vector(2 to 2); - reload_RNIRDRG : out std_logic_vector(1 to 1); - value_RNIBAHH : out std_logic_vector(1 to 1); - reload_RNI6SNI : out std_logic_vector(1 to 1); - scaler_i_m : out std_logic_vector(1 to 1); - reload_m_0_2 : out std_logic; - reload_m_0_3 : out std_logic; - reload_m_0_0 : out std_logic; - scaler_m_5 : out std_logic; - scaler_m_7 : out std_logic; - scaler_m_6 : out std_logic; - scaler_m_0 : out std_logic; - pwdata_0_d0 : in std_logic; - pwdata_14 : in std_logic; - pwdata_25 : in std_logic; - pwdata_12 : in std_logic; - pwdata_24 : in std_logic; - pwdata_23 : in std_logic; - pwdata_22 : in std_logic; - pwdata_21 : in std_logic; - pwdata_20 : in std_logic; - pwdata_19 : in std_logic; - pwdata_18 : in std_logic; - pwdata_17 : in std_logic; - pwdata_16 : in std_logic; - pwdata_15 : in std_logic; - pwdata_13 : in std_logic; - pwdata_11 : in std_logic; - pwdata_10 : in std_logic; - reload_28 : out std_logic; - reload_12 : out std_logic; - reload_11 : out std_logic; - reload_10 : out std_logic; - reload_8 : out std_logic; - reload_7 : out std_logic; - reload_6 : out std_logic; - reload_5 : out std_logic; - reload_0_7 : out std_logic; - reload_0_6 : out std_logic; - reload_0_4 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 0); - prdata_17 : out std_logic; - prdata_0 : out std_logic; - prdata_2 : out std_logic; - prdata_4 : out std_logic; - prdata_16 : out std_logic; - prdata_3 : out std_logic; - prdata_5 : out std_logic; - prdata_11 : out std_logic; - prdata_15 : out std_logic; - prdata_9 : out std_logic; - readdata_9_i_m : out std_logic_vector(1 to 1); - readdata_1_iv_0_0 : out std_logic; - readdata_1_iv_0_2 : out std_logic; - readdata_1_iv_0_11 : out std_logic; - readdata_1_iv_0_13 : out std_logic; - readdata_1_iv_0_9 : out std_logic; - readdata_iv_3 : out std_logic_vector(3 downto 2); - reload_m_20 : out std_logic; - reload_m_5 : out std_logic; - reload_m_9 : out std_logic; - reload_m_21 : out std_logic; - reload_m_0_d0 : out std_logic; - reload_m_27 : out std_logic; - reload_m_4 : out std_logic; - value_m_1 : out std_logic; - value_m_9 : out std_logic; - value_m_5 : out std_logic; - value_m_23 : out std_logic; - value_m_17 : out std_logic; - value_m_11 : out std_logic; - value_m_3 : out std_logic; - value_m_20 : out std_logic; - value_m_6 : out std_logic; - value_m_4 : out std_logic; - value_m_7 : out std_logic; - value_m_0 : out std_logic; - value_m_24 : out std_logic; - value_m_22 : out std_logic; - value_m_18 : out std_logic; - value_m_8 : out std_logic; - value_m_16 : out std_logic; - paddr_0 : in std_logic_vector(3 downto 2); - N_228 : out std_logic; - readdata51_1 : out std_logic; - N_6455 : in std_logic; - chain_m : out std_logic; - rdata60_1 : out std_logic; - rdata60_4 : in std_logic; - enable_m : out std_logic; - rdata59_4 : in std_logic; - N_217 : out std_logic; - N_229 : out std_logic; - N_215 : out std_logic; - rdata61_2 : in std_logic; - readdata55_3 : out std_logic; - N_218 : out std_logic; - N_216 : out std_logic; - N_214 : out std_logic; - irqpen_m : out std_logic; - N_219 : out std_logic; - N_236 : out std_logic; - N_220 : out std_logic; - rstn : in std_logic; - restart_RNIIKBB : out std_logic; - N_240 : out std_logic; - readdata55 : out std_logic; - dishlt : out std_logic; - penable : in std_logic; - pwrite : in std_logic; - N_773 : in std_logic; - N_769 : in std_logic; - readdata57 : out std_logic; - un1_apbi_0 : out std_logic; - N_78 : in std_logic; - un1_apbi_7_3 : in std_logic; - un1_apbi_2 : out std_logic; - readdata56 : out std_logic; - N_232_0 : in std_logic; - N_240_0 : out std_logic; - readdata_1_sqmuxa_1_0 : out std_logic; - N_232 : in std_logic; - value_0_sqmuxa_0 : out std_logic; - N_6455_0 : in std_logic; - lclk_c : in std_logic - ); - -end gptimer; - -architecture DEF_ARCH of gptimer is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \tsel_0[0]\, \tsel_RNIG6TH[0]\, reload_1_sqmuxa_0, - readdata30, un1_apbi, value_2_sqmuxa_0, irq_0_sqmuxa, - load, value_1_sqmuxa_0, value_2_sqmuxa_0_0, - irq_0_sqmuxa_0, load_0, value_1_sqmuxa_0_0, - reload_1_sqmuxa_0_0, \readdata_1_sqmuxa_1\, readdata51, - \value_0_sqmuxa_0\, value_1_sn_N_9_i_0, restart, un19_res, - value_1_sn_N_9_i_0_0, restart_0, N_157, - \value_RNI534J[1]\, \value_RNI3R3J[0]\, N_149, - \value_RNI9J4J[3]\, \DWACT_FDEC_E[0]\, N_126, - \value_RNIJR5J[8]\, \DWACT_FDEC_E[4]\, N_111, - \DWACT_FDEC_E[7]\, \DWACT_FDEC_E[6]\, N_30, \scaler[1]\, - \scaler[0]\, N_22, \scaler[3]\, \DWACT_FDEC_E_0[0]\, - \value[20]\, \reload[4]\, \reload[27]\, - readdata_1_sqmuxa_1_0_net_1, irqpen_0_sqmuxa_0, irqen, - \tsel[1]\, irqpen_0_sqmuxa_1, un4_i, irqen_0, - \reload_m[2]\, \readdata_iv_0[2]\, \readdata_iv_2[2]\, - \value[2]\, \scaler_m[2]\, \readdata_2_sqmuxa\, - \readdata_9[2]\, \reload_m[3]\, \readdata_iv_0[3]\, - \readdata_iv_2[3]\, \value[3]\, \scaler_m[3]\, - \readdata_9[3]\, \readdata_1_iv_0[31]\, \N_240_0\, N_239, - \reload_m[31]\, \readdata_1_iv_0[14]\, N_222, - \reload_m[14]\, \readdata_1_iv_0[16]\, \reload[16]\, - \readdata_9[16]\, N_230, \reload_m[22]\, N_234, - \reload_m[26]\, \readdata_1_iv_0[19]\, N_227, - \reload_m[19]\, N_232_1, \reload_m[24]\, N_223, - \reload_m[15]\, N_221, \reload_m[13]\, - \readdata_9_i_m_0[1]\, un1_apbi_0_0, \readdata_9[1]\, - value_1_sqmuxa, \reload_m[23]\, \readdata_9[23]\, - \value_m[23]\, \reload_m[29]\, \readdata_9[29]\, - \value_m[29]\, \reload_m[25]\, \readdata_9[25]\, - \value_m[25]\, \value[19]\, \reload_m[17]\, - \readdata_9[17]\, \value_m[17]\, \reload_m[30]\, - \readdata_9[30]\, \value_m[30]\, \reload_m[18]\, - \readdata_9[18]\, \value_m[18]\, \value[16]\, - reload_1_sqmuxa, load_RNO, load_1_sqmuxa, \value[14]\, - irqpen_0_sqmuxa_1_0, un34_i, value_2_sqmuxa, - value_2_sqmuxa_1, \value[31]\, \un1_apbi_0\, N_620, - load_1_sqmuxa_1, N_631, dishlt_1_sqmuxa, N_553, - \reload[0]\, N_554, \reload[1]\, N_555, \reload[2]\, - N_556, \reload[3]\, N_557, N_558, N_559, N_560, N_561, - N_562, \reload[9]\, N_563, N_564, N_565, N_566, - \reload[13]\, N_568, \reload[15]\, N_569, N_570, - \reload[17]\, reload_1_sqmuxa_1, N_572, \reload[19]\, - N_574, \reload[21]\, N_575, \reload[22]\, N_576, - \reload[23]\, N_577, \reload[24]\, N_578, \reload[25]\, - N_579, \reload[26]\, N_580, N_581, N_582, \reload[29]\, - N_583, \reload[30]\, N_623, \reload_0[0]\, - reload_1_sqmuxa_2, N_624, \reload_0[1]\, N_625, - \reload_0[2]\, N_626, \reload_0[3]\, N_627, N_628, - \reload_0[5]\, N_629, N_630, N_208, \un1_timer0[8]\, - \reload_1[0]\, \readdata56\, N_201, N_209, \readdata55\, - \value[1]\, N_324, I_44, N_325, I_5_6, N_326, I_9_6, - \scaler_1[0]\, scaler_0_sqmuxa, \scaler_1[1]\, - \scaler_1[2]\, N_343, I_5_5, \reload_1[1]\, N_344, I_9_5, - \reload_1[2]\, \value_1[1]\, \value_1[2]\, N_431, I_143_1, - \value_1[22]\, N_198, \scaler_RNO[0]\, \scaler_RNO[1]\, - \scaler_RNO[2]\, \un1_timer0[20]\, \reload_0[12]\, N_224, - \un1_timer0[24]\, \reload_0[16]\, N_226, \un1_timer0[26]\, - \reload[18]\, \un1_timer0[30]\, \reload_0[22]\, - \un1_timer0[34]\, \reload_0[26]\, \un1_timer0[36]\, - \reload_0[28]\, N_238, \un1_timer0[38]\, \reload_0[30]\, - \value[12]\, \value[18]\, \reload_0[18]\, \value[22]\, - \value[26]\, \value[28]\, \value[30]\, N_342, N_345, - I_13_9, \reload_1[3]\, \value_1[0]\, \value_1[3]\, N_409, - N_411, N_412, \value_1_0[0]\, \value_1_0[2]\, - \value_1_0[3]\, \N_240\, N_212, \un1_timer0[12]\, - \reload_1[4]\, \un1_timer0[19]\, \reload_0[11]\, N_225, - \un1_timer0[25]\, \reload_0[17]\, \un1_timer0[27]\, - \reload_0[19]\, N_233, \un1_timer0[33]\, \reload_0[25]\, - N_237, \un1_timer0[37]\, \reload_0[29]\, N_204, - \value[4]\, value_0_sqmuxa, irqpen, \value[11]\, - \value[17]\, \value[25]\, \value[29]\, N_346, I_20_5, - N_368, I_186_1, \value_1[4]\, \value_1[26]\, N_413, - \reload_0[4]\, N_435, \value_1_0[4]\, \value_1_0[26]\, - irqpen_0, N_347, I_24_6, \reload_1[5]\, N_349, I_38_2, - \reload_1[7]\, N_351, I_52_2, \reload_0[9]\, N_355, - I_77_1, \reload_0[13]\, N_366, I_166_1, \reload_0[24]\, - N_367, I_173_1, \value_1[5]\, \value_1[7]\, \value_1[9]\, - \value_1[13]\, \value_1[24]\, \value_1[25]\, N_414, - \reload[5]\, N_416, \reload[7]\, N_418, N_422, - \value_1_0[5]\, \value_1_0[7]\, \value_1_0[9]\, - \value_1_0[13]\, \un1_timer0[14]\, \reload_1[6]\, - \un1_timer0[16]\, \reload_0[8]\, \scaler[6]\, \value[8]\, - N_330, I_31_5, \reload_0[6]\, \scaler_1[6]\, N_348, - I_31_4, N_353, I_66_2, \value_1[6]\, \value_1[11]\, N_415, - \reload[6]\, N_420, \reload[11]\, N_433, N_434, - \value_1_0[6]\, \value_1_0[11]\, \value_1_0[24]\, - \value_1_0[25]\, \scaler_RNO[6]\, N_350, I_45_2, N_352, - I_56_2, \reload_0[10]\, N_354, I_73_1, value_1_sn_N_9_i, - N_358, I_98_1, N_359, I_105_1, N_360, I_115_1, N_361, - I_122_1, N_363, I_136_1, \reload_0[21]\, N_365, I_156_1, - \reload_0[23]\, N_369, I_196_1, \reload_0[27]\, N_370, - I_203_1, N_372, I_217, \value_1[8]\, \value_1[10]\, - \value_1[12]\, \value_1[16]\, \value_1[17]\, - \value_1[18]\, \value_1[19]\, \value_1[21]\, - \value_1[23]\, \value_1[27]\, \value_1[28]\, - \value_1[30]\, N_417, \reload[8]\, N_419, \reload[10]\, - N_421, \reload[12]\, value_1_sn_N_9_i_1, N_423, I_84_1, - \reload[14]\, N_425, N_426, N_427, N_428, N_430, N_432, - N_436, N_437, \reload[28]\, N_439, \value_1_0[8]\, - \value_1_0[10]\, \value_1_0[12]\, value_1_sqmuxa_1, - \value_1[14]\, \value_1_0[16]\, \value_1_0[17]\, - \value_1_0[18]\, \value_1_0[19]\, \value_1_0[21]\, - \value_1_0[23]\, \value_1_0[27]\, \value_1_0[28]\, - \value_1_0[30]\, \un1_timer0[18]\, \value[10]\, N_364, - N_371, I_210_1, \value_1_0[22]\, N_424, I_91_1, N_438, - \value_1[15]\, \value_1[29]\, \readdata57\, - \un1_timer0[5]\, \un1_timer0[32]\, \value[24]\, irqpen_1, - irqpen_4, irqpen_1_0, load_1_sqmuxa_0, irqpen_4_0, - \un1_timer0[15]\, \un1_timer0[23]\, \reload_0[15]\, - \un1_timer0[29]\, N_235, \un1_timer0[35]\, \scaler[7]\, - \value[7]\, \value[15]\, \value[21]\, \value[27]\, N_328, - I_20_6, \scaler_1[4]\, irqpen_RNO, irqpen_RNO_0, - \scaler_RNO[4]\, N_327, I_13_10, N_329, I_24_7, N_331, - I_38_3, \reload_0[7]\, \scaler_1[3]\, \scaler_1[5]\, - \scaler_1[7]\, \scaler_RNO[3]\, \scaler_RNO[5]\, - \scaler_RNO[7]\, \un1_timer0[17]\, \un1_timer0[21]\, - \value[9]\, \value[13]\, dishlt_RNO, irqen_RNO, - \reload_RNO[16]\, \reload_RNO[17]\, \reload_RNO[19]\, - \reload_RNO[21]\, \reload_RNO[22]\, \reload_RNO[23]\, - \reload_RNO[24]\, \reload_RNO[25]\, \reload_RNO[26]\, - \reload_RNO[27]\, \reload_RNO[28]\, \reload_RNO[29]\, - \reload_RNO[30]\, \tsel_RNO[1]\, \reload_RNO[0]\, - \reload_RNO[1]\, \reload_RNO[2]\, \reload_RNO[3]\, - \reload_RNO[4]\, \reload_RNO[5]\, \reload_RNO[6]\, - \reload_RNO[7]\, \reload_RNO[8]\, \reload_RNO[9]\, - \reload_RNO[10]\, \reload_RNO[11]\, \reload_RNO[12]\, - \reload_RNO[13]\, \reload_RNO[15]\, \reload_RNO_0[0]\, - \reload_RNO_0[1]\, \reload_RNO_0[2]\, \reload_RNO_0[3]\, - \reload_RNO_0[4]\, \reload_RNO_0[5]\, \reload_RNO_0[6]\, - \reload_RNO_0[7]\, N_231, \un1_timer0[31]\, \value[23]\, - \un1_timer0[6]\, \un1_timer0[22]\, \reload_0[14]\, N_203, - N_211, \un1_timer0[9]\, \value_RNI7B4J[2]\, - \un1_timer0[10]\, \un1_timer0[11]\, \value_RNIBR4J[4]\, - \value_RNID35J[5]\, \value[5]\, \un1_timer0[13]\, - \value_RNIFB5J[6]\, \value_RNIHJ5J[7]\, - \value_RNIL36J[9]\, \value_RNI73QI[10]\, - \value_RNI93QI[11]\, \value_RNIB3QI[12]\, - \value_RNID3QI[13]\, \value_RNIF3QI[14]\, - \value_RNIH3QI[15]\, \value_RNIJ3QI[16]\, - \value_RNIVLUG[17]\, \tsel[0]\, \value_RNI3MUG[19]\, - \value_RNIPTUG[21]\, \value_RNIRTUG[22]\, - \value_RNITTUG[23]\, \value_RNIVTUG[24]\, - \value_RNI1UUG[25]\, \value_RNI3UUG[26]\, - \value_RNI5UUG[27]\, \value_RNI7UUG[28]\, - \value_RNI9UUG[29]\, \value_RNIT5VG[30]\, N_200, enable, - enable_0, chain, \scaler[2]\, tsel_1_sqmuxa, - \un1_timer0[7]\, N_205, enable_RNO, N_544, chain_0, - \scaler[5]\, N_213, enable_1_sqmuxa, load_RNIC53BJ, - enable_1, N_202, N_210, \rdata60_1\, \un1_apbi_2\, - \readdata51_1\, \readdata55_3\, \value_RNI1MUG[18]\, - \reload_RNO[14]\, N_567, \reload_RNO[18]\, N_571, - \value_1_0[29]\, \value_1_0[14]\, N_356, irq_2, N_543, - enable_1_0, enable_1_sqmuxa_0, N_617, N_619, irq_RNO, - chain_RNO, irqen_RNO_0, enable_RNO_0, I_224, - \value_RNIV5VG[31]\, \reload_RNO[31]\, N_584, restart_RNO, - N_618, \un1_timer0[39]\, \reload[31]\, \reload_0[31]\, - load_RNO_0, \value_1[31]\, N_440, \value_1_0[31]\, N_373, - \value_RNINTUG[20]\, \un1_timer0[28]\, \reload_RNO[20]\, - N_573, \value_1_0[15]\, N_357, \value_1[20]\, N_429, - I_129_1, \reload[20]\, \value_1_0[20]\, N_362, - \reload_0[20]\, \value_1_0[1]\, N_410, \dishlt\, - \value[0]\, \value[6]\, \DWACT_FDEC_E[3]\, - \DWACT_FDEC_E[2]\, N_9, \scaler[4]\, N_14, - \DWACT_FDEC_E[1]\, N_19, N_27, N_4, \DWACT_FDEC_E[24]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[27]\, - \DWACT_FDEC_E[26]\, N_9_0, N_14_0, \DWACT_FDEC_E[25]\, - N_19_0, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, N_24, - \DWACT_FDEC_E[15]\, \DWACT_FDEC_E[17]\, - \DWACT_FDEC_E[22]\, N_31, \DWACT_FDEC_E[21]\, - \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, \DWACT_FDEC_E[20]\, - N_40, \DWACT_FDEC_E[13]\, \DWACT_FDEC_E[19]\, N_45, - \DWACT_FDEC_E[18]\, N_52, \DWACT_FDEC_E[33]\, - \DWACT_FDEC_E[34]\, \DWACT_FDEC_E_0[2]\, - \DWACT_FDEC_E[5]\, N_61, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_66, N_71, \DWACT_FDEC_E[14]\, N_76, - N_81, \DWACT_FDEC_E[10]\, N_88, \DWACT_FDEC_E[11]\, N_93, - N_98, N_103, \DWACT_FDEC_E[8]\, N_108, N_116, N_123, - \DWACT_FDEC_E_0[3]\, N_131, N_136, N_141, - \DWACT_FDEC_E_0[1]\, N_146, N_154, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - scaler_4 <= \scaler[4]\; - value_6 <= \value[6]\; - value_0 <= \value[0]\; - reload_28 <= \reload[28]\; - reload_12 <= \reload[12]\; - reload_11 <= \reload[11]\; - reload_10 <= \reload[10]\; - reload_8 <= \reload[8]\; - reload_7 <= \reload[7]\; - reload_6 <= \reload[6]\; - reload_5 <= \reload[5]\; - reload_0_7 <= \reload_0[7]\; - reload_0_6 <= \reload_0[6]\; - reload_0_4 <= \reload_0[4]\; - readdata51_1 <= \readdata51_1\; - rdata60_1 <= \rdata60_1\; - readdata55_3 <= \readdata55_3\; - N_240 <= \N_240\; - readdata55 <= \readdata55\; - dishlt <= \dishlt\; - readdata57 <= \readdata57\; - un1_apbi_0 <= \un1_apbi_0\; - un1_apbi_2 <= \un1_apbi_2\; - readdata56 <= \readdata56\; - N_240_0 <= \N_240_0\; - readdata_1_sqmuxa_1_0 <= readdata_1_sqmuxa_1_0_net_1; - value_0_sqmuxa_0 <= \value_0_sqmuxa_0\; - - \r.timers_1.value_RNI3MUG[19]\ : MX2 - port map(A => \value[19]\, B => \un1_timer0[27]\, S => - \tsel[0]\, Y => \value_RNI3MUG[19]\); - - un12_res_I_108 : OR3 - port map(A => \value_RNIH3QI[15]\, B => \value_RNIJ3QI[16]\, - C => \value_RNIVLUG[17]\, Y => \DWACT_FDEC_E[12]\); - - \r.timers_2.value_RNO[5]\ : MX2A - port map(A => N_414, B => pwdata_0(5), S => - value_1_sqmuxa_0_0, Y => \value_1_0[5]\); - - un12_res_I_52 : XNOR2 - port map(A => N_126, B => \value_RNIL36J[9]\, Y => I_52_2); - - \r.timers_1.restart_RNIC90KI\ : AO1 - port map(A => restart_0, B => un19_res, C => load, Y => - value_1_sn_N_9_i); - - un12_res_I_224 : XNOR2 - port map(A => N_4, B => \value_RNIV5VG[31]\, Y => I_224); - - \r.timers_2.reload[13]\ : DFN1 - port map(D => \reload_RNO[13]\, CLK => lclk_c, Q => - \reload[13]\); - - \r.timers_1.reload[8]\ : DFN1E1 - port map(D => pwdata_0(8), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[8]\); - - \r.scaler_RNO[1]\ : OR2B - port map(A => rstn, B => \scaler_1[1]\, Y => - \scaler_RNO[1]\); - - \comb.readdata57\ : OR2 - port map(A => rdata60_4, B => paddr(6), Y => \readdata57\); - - \r.timers_2.reload[9]\ : DFN1 - port map(D => \reload_RNO[9]\, CLK => lclk_c, Q => - \reload[9]\); - - \r.timers_1.irqen\ : DFN1 - port map(D => irqen_RNO, CLK => lclk_c, Q => irqen_0); - - \r.scaler[2]\ : DFN1 - port map(D => \scaler_RNO[2]\, CLK => lclk_c, Q => - \scaler[2]\); - - \r.timers_2.reload_RNO[27]\ : NOR2B - port map(A => rstn, B => N_580, Y => \reload_RNO[27]\); - - \r.timers_2.load_RNO\ : AO1B - port map(A => load_1_sqmuxa_0, B => pwdata_0(2), C => rstn, - Y => load_RNO_0); - - \r.timers_2.restart\ : DFN1 - port map(D => restart_RNO, CLK => lclk_c, Q => restart); - - \r.timers_2.value[16]\ : DFN1E0 - port map(D => \value_1_0[16]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[16]\); - - \r.timers_1.value_RNIV2CL[23]\ : OR2B - port map(A => \N_240\, B => N_231, Y => \readdata_9[23]\); - - \r.timers_1.value_RNI1UUG[25]\ : MX2 - port map(A => \value[25]\, B => \un1_timer0[33]\, S => - \tsel[0]\, Y => \value_RNI1UUG[25]\); - - \r.dishlt_RNO_0\ : MX2 - port map(A => \dishlt\, B => pwdata_0(9), S => - dishlt_1_sqmuxa, Y => N_631); - - \r.timers_2.reload[6]\ : DFN1 - port map(D => \reload_RNO[6]\, CLK => lclk_c, Q => - \reload[6]\); - - \r.timers_1.value_RNO_0[19]\ : MX2C - port map(A => I_122_1, B => \reload_0[19]\, S => - value_1_sn_N_9_i, Y => N_361); - - un12_res_I_77 : XNOR2 - port map(A => N_108, B => \value_RNID3QI[13]\, Y => I_77_1); - - \r.timers_2.irqen\ : DFN1 - port map(D => irqen_RNO_0, CLK => lclk_c, Q => irqen); - - un12_res_I_31 : XNOR2 - port map(A => N_141, B => \value_RNIFB5J[6]\, Y => I_31_4); - - \r.timers_2.value[4]\ : DFN1E0 - port map(D => \value_1_0[4]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[4]\); - - \r.timers_1.value_RNO_0[6]\ : MX2C - port map(A => I_31_4, B => \reload_1[6]\, S => - value_1_sn_N_9_i_0_0, Y => N_348); - - \r.timers_1.value_RNO[3]\ : MX2A - port map(A => N_345, B => pwdata_0(3), S => - value_1_sqmuxa_0, Y => \value_1[3]\); - - \r.timers_1.value_RNIH3QI[15]\ : MX2 - port map(A => \value[15]\, B => \un1_timer0[23]\, S => - \tsel_0[0]\, Y => \value_RNIH3QI[15]\); - - \r.tsel_RNO[1]\ : NOR2B - port map(A => rstn, B => \tsel_0[0]\, Y => \tsel_RNO[1]\); - - \r.timers_1.enable_RNO\ : NOR2B - port map(A => rstn, B => N_544, Y => enable_RNO); - - \r.timers_1.value_RNIAQJC[26]\ : MX2 - port map(A => \un1_timer0[34]\, B => \reload_0[26]\, S => - paddr_1(2), Y => N_234); - - \r.scaler_RNO[4]\ : OR2B - port map(A => rstn, B => \scaler_1[4]\, Y => - \scaler_RNO[4]\); - - \r.timers_2.reload_RNILNBI[29]\ : OR2A - port map(A => \reload[29]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[29]\); - - \r.timers_2.value_RNO_0[29]\ : MX2C - port map(A => I_210_1, B => \reload[29]\, S => - value_1_sn_N_9_i_1, Y => N_438); - - un12_res_I_91 : XNOR2 - port map(A => N_98, B => \value_RNIH3QI[15]\, Y => I_91_1); - - \r.reload[1]\ : DFN1 - port map(D => \reload_RNO_0[1]\, CLK => lclk_c, Q => - \reload_0[1]\); - - un6_scaler_I_13 : XNOR2 - port map(A => N_27, B => \scaler[3]\, Y => I_13_10); - - un12_res_I_80 : OR2 - port map(A => \value_RNIB3QI[12]\, B => \value_RNID3QI[13]\, - Y => \DWACT_FDEC_E[8]\); - - un12_res_I_13 : XNOR2 - port map(A => N_154, B => \value_RNI9J4J[3]\, Y => I_13_9); - - \r.timers_1.value_RNO_0[23]\ : MX2C - port map(A => I_156_1, B => \reload_0[23]\, S => - value_1_sn_N_9_i, Y => N_365); - - \r.timers_2.value_RNIS2KN1[14]\ : AO1C - port map(A => \value_0_sqmuxa_0\, B => \value[14]\, C => - \readdata_1_iv_0[14]\, Y => prdata_0); - - \r.timers_2.value_RNIBAHH[1]\ : OR2 - port map(A => \value_0_sqmuxa_0\, B => \value[1]\, Y => - value_RNIBAHH(1)); - - \r.timers_1.value_RNI2FCL[17]\ : OR2B - port map(A => \N_240\, B => N_225, Y => \readdata_9[17]\); - - \comb.1.un1_apbi_2\ : OR2B - port map(A => paddr(3), B => paddr(2), Y => \un1_apbi_2\); - - un12_res_I_8 : OR2 - port map(A => \value_RNI534J[1]\, B => \value_RNI3R3J[0]\, - Y => N_157); - - un12_res_I_19 : OR2 - port map(A => \value_RNI9J4J[3]\, B => \DWACT_FDEC_E[0]\, Y - => N_149); - - \r.timers_1.reload[22]\ : DFN1E1 - port map(D => pwdata_16, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[22]\); - - \r.timers_2.value_RNI6O211[3]\ : OA1A - port map(A => \value[3]\, B => \value_0_sqmuxa_0\, C => - \scaler_m[3]\, Y => \readdata_iv_2[3]\); - - \r.reload_RNO[1]\ : OR2A - port map(A => rstn, B => N_624, Y => \reload_RNO_0[1]\); - - \r.timers_1.reload_RNIN27C[0]\ : MX2 - port map(A => \un1_timer0[8]\, B => \reload_1[0]\, S => - paddr_0(2), Y => N_208); - - \r.timers_1.value_RNO_0[1]\ : MX2C - port map(A => I_5_5, B => \reload_1[1]\, S => - value_1_sn_N_9_i_0_0, Y => N_343); - - \r.timers_2.value_RNO_0[11]\ : MX2C - port map(A => I_66_2, B => \reload[11]\, S => - value_1_sn_N_9_i_0, Y => N_420); - - \r.timers_2.value_RNI9HCH[29]\ : OR2A - port map(A => \value[29]\, B => value_0_sqmuxa, Y => - \value_m[29]\); - - \r.timers_1.value_RNI6JCL[27]\ : OR2B - port map(A => \N_240\, B => N_235, Y => readdata_9_27); - - \r.scaler[0]\ : DFN1 - port map(D => \scaler_RNO[0]\, CLK => lclk_c, Q => - \scaler[0]\); - - \r.timers_1.reload_RNIP9761[22]\ : AOI1B - port map(A => \N_240_0\, B => N_230, C => \reload_m[22]\, Y - => readdata_1_iv_0_9); - - \r.timers_2.value_RNITCCH[10]\ : OR2A - port map(A => \value[10]\, B => value_0_sqmuxa, Y => - value_m_6); - - \r.timers_1.reload[10]\ : DFN1E1 - port map(D => pwdata_0(10), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[10]\); - - \r.scaler[6]\ : DFN1 - port map(D => \scaler_RNO[6]\, CLK => lclk_c, Q => - \scaler[6]\); - - \r.timers_2.reload_RNO_0[12]\ : MX2 - port map(A => \reload[12]\, B => pwdata_0(12), S => - reload_1_sqmuxa_0_0, Y => N_565); - - un12_res_I_105 : XNOR2 - port map(A => N_88, B => \value_RNIVLUG[17]\, Y => I_105_1); - - \r.timers_1.load_RNO\ : NOR3A - port map(A => pwdata_0(2), B => load_1_sqmuxa, C => - un1_apbi, Y => load_RNO); - - \r.timers_1.reload[5]\ : DFN1E1 - port map(D => pwdata_0(5), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[5]\); - - un12_res_I_122 : XNOR2 - port map(A => N_76, B => \value_RNI3MUG[19]\, Y => I_122_1); - - \r.timers_2.reload_RNIGMN71[16]\ : OA1A - port map(A => \reload[16]\, B => - readdata_1_sqmuxa_1_0_net_1, C => \readdata_9[16]\, Y => - \readdata_1_iv_0[16]\); - - \r.timers_2.value_RNI8HCH[28]\ : OR2A - port map(A => \value[28]\, B => \value_0_sqmuxa_0\, Y => - value_m_24); - - \r.timers_2.value[22]\ : DFN1E0 - port map(D => \value_1[22]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[22]\); - - \r.timers_1.load_RNIN4901\ : MX2C - port map(A => N_202, B => N_210, S => \N_240\, Y => - \readdata_9[2]\); - - \r.timers_1.value_RNI5MJC[16]\ : MX2 - port map(A => \un1_timer0[24]\, B => \reload_0[16]\, S => - paddr_0(2), Y => N_224); - - \r.timers_1.value_RNIVP761[24]\ : AOI1B - port map(A => \N_240_0\, B => N_232_1, C => \reload_m[24]\, - Y => readdata_1_iv_0_11); - - \r.timers_1.value[28]\ : DFN1E0 - port map(D => \value_1[28]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[36]\); - - \r.timers_2.reload[10]\ : DFN1 - port map(D => \reload_RNO[10]\, CLK => lclk_c, Q => - \reload[10]\); - - \r.timers_2.value_RNI5HCH[25]\ : OR2A - port map(A => \value[25]\, B => value_0_sqmuxa, Y => - \value_m[25]\); - - \r.timers_2.value[11]\ : DFN1E0 - port map(D => \value_1_0[11]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[11]\); - - \r.timers_2.reload_RNIH7BI[25]\ : OR2A - port map(A => \reload[25]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[25]\); - - \r.timers_2.chain\ : DFN1 - port map(D => chain_RNO, CLK => lclk_c, Q => chain_0); - - \r.timers_1.value[4]\ : DFN1E0 - port map(D => \value_1[4]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[12]\); - - \r.timers_1.reload[13]\ : DFN1E1 - port map(D => pwdata_0(13), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[13]\); - - \r.timers_2.value_RNO[15]\ : MX2A - port map(A => N_424, B => pwdata_0(15), S => - value_1_sqmuxa_1, Y => \value_1[15]\); - - un12_res_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \value_RNIVTUG[24]\, Y => \DWACT_FDEC_E[19]\); - - \r.timers_2.value_RNO_0[0]\ : MX2B - port map(A => \value_RNI3R3J[0]\, B => \reload[0]\, S => - value_1_sn_N_9_i_0, Y => N_409); - - \r.timers_1.value_RNIOD761[13]\ : AOI1B - port map(A => \N_240_0\, B => N_221, C => \reload_m[13]\, Y - => readdata_1_iv_0_0); - - \r.timers_1.reload_RNIVR451[0]\ : MX2C - port map(A => N_200, B => N_208, S => \N_240\, Y => - readdata_9_0); - - \r.reload[2]\ : DFN1 - port map(D => \reload_RNO_0[2]\, CLK => lclk_c, Q => - \reload_0[2]\); - - un12_res_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[1]\, - C => \value_RNID35J[5]\, Y => N_141); - - \r.timers_1.value_RNO[17]\ : MX2A - port map(A => N_359, B => pwdata_11, S => value_1_sqmuxa, Y - => \value_1[17]\); - - un6_scaler_I_9 : XNOR2 - port map(A => N_30, B => \scaler[2]\, Y => I_9_6); - - \r.timers_1.value_RNO_0[24]\ : MX2C - port map(A => I_166_1, B => \reload_0[24]\, S => - value_1_sn_N_9_i_0_0, Y => N_366); - - un12_res_I_27 : OR2 - port map(A => \value_RNI9J4J[3]\, B => \value_RNIBR4J[4]\, - Y => \DWACT_FDEC_E_0[1]\); - - \r.timers_1.value_RNO[14]\ : MX2A - port map(A => N_356, B => pwdata_0(14), S => value_1_sqmuxa, - Y => \value_1_0[14]\); - - \r.reload_RNO_0[0]\ : MX2 - port map(A => \reload_0[0]\, B => pwdata_0(0), S => - reload_1_sqmuxa_2, Y => N_623); - - \r.timers_1.value_RNO_0[28]\ : MX2C - port map(A => I_203_1, B => \reload_0[28]\, S => - value_1_sn_N_9_i, Y => N_370); - - \r.timers_1.value[12]\ : DFN1E0 - port map(D => \value_1[12]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[20]\); - - \r.timers_2.value_RNO_0[17]\ : MX2C - port map(A => I_105_1, B => \reload[17]\, S => - value_1_sn_N_9_i_1, Y => N_426); - - un12_res_I_59 : OR3 - port map(A => \value_RNIFB5J[6]\, B => \value_RNIHJ5J[7]\, - C => \value_RNIJR5J[8]\, Y => \DWACT_FDEC_E[5]\); - - un12_res_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_98); - - \r.timers_1.irq_RNIAUTI\ : OA1A - port map(A => chain_0, B => \un1_timer0[6]\, C => enable_0, - Y => un34_i); - - un12_res_I_66 : XNOR2 - port map(A => N_116, B => \value_RNI93QI[11]\, Y => I_66_2); - - un12_res_I_213 : OR3 - port map(A => \value_RNI5UUG[27]\, B => \value_RNI7UUG[28]\, - C => \value_RNI9UUG[29]\, Y => \DWACT_FDEC_E[26]\); - - \r.timers_1.value_RNIHHNII[31]\ : NOR2A - port map(A => I_224, B => \value_RNIV5VG[31]\, Y => - un19_res); - - \v.timers_2.reload_1_sqmuxa_0\ : NOR2 - port map(A => \readdata_1_sqmuxa_1\, B => un1_apbi, Y => - reload_1_sqmuxa_0_0); - - \r.timers_1.value_RNO[0]\ : MX2A - port map(A => N_342, B => pwdata_0(0), S => - value_1_sqmuxa_0, Y => \value_1[0]\); - - un12_res_I_176 : OR2 - port map(A => \value_RNIVTUG[24]\, B => \value_RNI1UUG[25]\, - Y => \DWACT_FDEC_E[20]\); - - \r.timers_2.reload[12]\ : DFN1 - port map(D => \reload_RNO[12]\, CLK => lclk_c, Q => - \reload[12]\); - - \r.timers_1.reload[9]\ : DFN1E1 - port map(D => pwdata_0(9), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[9]\); - - un12_res_I_9 : XNOR2 - port map(A => N_157, B => \value_RNI7B4J[2]\, Y => I_9_5); - - \r.timers_2.value_RNO[4]\ : MX2A - port map(A => N_413, B => pwdata_0(4), S => - value_1_sqmuxa_0_0, Y => \value_1_0[4]\); - - \r.timers_2.value[31]\ : DFN1E0 - port map(D => \value_1[31]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[31]\); - - \r.timers_1.reload_RNI2AJC[22]\ : MX2 - port map(A => \un1_timer0[30]\, B => \reload_0[22]\, S => - paddr_1(2), Y => N_230); - - \r.timers_2.reload_RNO_0[10]\ : MX2 - port map(A => \reload[10]\, B => pwdata_0(10), S => - reload_1_sqmuxa_0_0, Y => N_563); - - \r.timers_1.value_RNO[27]\ : MX2A - port map(A => N_369, B => pwdata_21, S => value_1_sqmuxa, Y - => \value_1[27]\); - - \r.timers_1.reload[6]\ : DFN1E1 - port map(D => pwdata_0_d0, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[6]\); - - \r.timers_2.reload_RNO_0[13]\ : MX2 - port map(A => \reload[13]\, B => pwdata_0(13), S => - reload_1_sqmuxa_0_0, Y => N_566); - - \r.timers_1.value_RNO[24]\ : MX2A - port map(A => N_366, B => pwdata_18, S => value_1_sqmuxa_0, - Y => \value_1[24]\); - - \r.timers_2.reload[7]\ : DFN1 - port map(D => \reload_RNO[7]\, CLK => lclk_c, Q => - \reload[7]\); - - \r.scaler_RNO_1[2]\ : MX2 - port map(A => I_9_6, B => \reload_0[2]\, S => I_44, Y => - N_326); - - \r.timers_2.value_RNIJ34P1[16]\ : AO1C - port map(A => \value_0_sqmuxa_0\, B => \value[16]\, C => - \readdata_1_iv_0[16]\, Y => prdata_2); - - \r.timers_1.value[8]\ : DFN1E0 - port map(D => \value_1[8]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[16]\); - - \r.timers_2.value_RNO_0[6]\ : MX2C - port map(A => I_31_4, B => \reload[6]\, S => - value_1_sn_N_9_i_0, Y => N_415); - - \r.timers_1.value_RNI9J4J[3]\ : MX2 - port map(A => \value[3]\, B => \un1_timer0[11]\, S => - \tsel_0[0]\, Y => \value_RNI9J4J[3]\); - - \comb.1.readdata_9_sn_m1\ : OR2A - port map(A => readdata30, B => paddr(2), Y => N_198); - - \r.scaler_RNO[0]\ : OR2B - port map(A => rstn, B => \scaler_1[0]\, Y => - \scaler_RNO[0]\); - - \r.timers_1.reload_RNI4R7C[6]\ : MX2 - port map(A => \un1_timer0[14]\, B => \reload_1[6]\, S => - paddr_1(2), Y => N_214); - - \r.timers_1.enable_RNO_2\ : NOR2 - port map(A => load_1_sqmuxa_1, B => load_RNIC53BJ, Y => - enable_1_sqmuxa); - - \r.timers_2.value_RNIEMHH[4]\ : OR2A - port map(A => \value[4]\, B => value_0_sqmuxa, Y => - value_m_0); - - \r.timers_1.value_RNO[30]\ : MX2A - port map(A => N_372, B => pwdata_24, S => value_1_sqmuxa, Y - => \value_1[30]\); - - \r.timers_2.value_RNO_0[4]\ : MX2C - port map(A => I_20_5, B => \reload_0[4]\, S => - value_1_sn_N_9_i_0, Y => N_413); - - \r.timers_1.reload[25]\ : DFN1E1 - port map(D => pwdata_19, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[25]\); - - \r.timers_2.reload_RNO[22]\ : NOR2B - port map(A => rstn, B => N_575, Y => \reload_RNO[22]\); - - \r.timers_1.irqen_RNO_0\ : MX2 - port map(A => irqen_0, B => pwdata_0(3), S => - load_1_sqmuxa_1, Y => N_620); - - \r.timers_1.irqen_RNO\ : NOR2B - port map(A => rstn, B => N_620, Y => irqen_RNO); - - un12_res_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_31); - - \r.scaler_RNO_1[3]\ : MX2 - port map(A => I_13_10, B => \reload_0[3]\, S => I_44, Y => - N_327); - - \r.timers_2.value_RNO[20]\ : MX2A - port map(A => N_429, B => pwdata_14, S => value_1_sqmuxa_1, - Y => \value_1[20]\); - - \r.timers_1.restart_RNISC09\ : NOR2A - port map(A => restart_0, B => N_198, Y => N_201); - - \r.timers_1.irqen_RNI6SEC\ : NOR2A - port map(A => irqen_0, B => N_198, Y => N_203); - - \r.timers_2.load_RNIMIAC1\ : OA1A - port map(A => load_0, B => \readdata_2_sqmuxa\, C => - \readdata_9[2]\, Y => \readdata_iv_0[2]\); - - \r.dishlt_RNO_1\ : NOR2 - port map(A => un1_apbi, B => \readdata57\, Y => - dishlt_1_sqmuxa); - - \r.timers_1.value_RNIVTUG[24]\ : MX2 - port map(A => \value[24]\, B => \un1_timer0[32]\, S => - \tsel[0]\, Y => \value_RNIVTUG[24]\); - - \r.timers_1.value[9]\ : DFN1E0 - port map(D => \value_1[9]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[17]\); - - \r.timers_2.value_RNIFB3P1[31]\ : AO1C - port map(A => \value_0_sqmuxa_0\, B => \value[31]\, C => - \readdata_1_iv_0[31]\, Y => prdata_17); - - \r.timers_2.value[29]\ : DFN1E0 - port map(D => \value_1[29]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[29]\); - - \r.timers_1.value_RNI3UUG[26]\ : MX2 - port map(A => \value[26]\, B => \un1_timer0[34]\, S => - \tsel[0]\, Y => \value_RNI3UUG[26]\); - - \r.timers_2.value_RNO_0[5]\ : MX2C - port map(A => I_24_6, B => \reload[5]\, S => - value_1_sn_N_9_i_0, Y => N_414); - - \r.timers_1.reload_RNI26JC[30]\ : MX2 - port map(A => \un1_timer0[38]\, B => \reload_0[30]\, S => - paddr_1(2), Y => N_238); - - \r.timers_1.value_RNO[31]\ : MX2A - port map(A => N_373, B => pwdata_25, S => value_1_sqmuxa, Y - => \value_1_0[31]\); - - \r.timers_1.value_RNICUJC[27]\ : MX2 - port map(A => \un1_timer0[35]\, B => \reload_0[27]\, S => - paddr_1(2), Y => N_235); - - \r.timers_1.load_RNI0B3K3_0\ : NOR3 - port map(A => irq_0_sqmuxa, B => load, C => - value_1_sqmuxa_0, Y => value_2_sqmuxa_0); - - un12_res_I_220 : OR2 - port map(A => \DWACT_FDEC_E[26]\, B => \value_RNIT5VG[30]\, - Y => \DWACT_FDEC_E[27]\); - - \r.timers_1.value_RNO_0[26]\ : MX2C - port map(A => I_186_1, B => \reload_0[26]\, S => - value_1_sn_N_9_i_0_0, Y => N_368); - - \r.timers_2.reload_RNO_0[28]\ : MX2 - port map(A => \reload[28]\, B => pwdata_22, S => - reload_1_sqmuxa_1, Y => N_581); - - \r.scaler_RNO_0[3]\ : MX2C - port map(A => pwdata_0(3), B => N_327, S => scaler_0_sqmuxa, - Y => \scaler_1[3]\); - - \r.timers_1.reload_RNII7ND[5]\ : MX2 - port map(A => \un1_timer0[13]\, B => \reload_1[5]\, S => - paddr(2), Y => N_213); - - un12_res_I_132 : OR3 - port map(A => \value_RNI1MUG[18]\, B => \value_RNI3MUG[19]\, - C => \value_RNINTUG[20]\, Y => \DWACT_FDEC_E[15]\); - - \r.timers_2.value_RNO[21]\ : MX2A - port map(A => N_430, B => pwdata_15, S => value_1_sqmuxa_1, - Y => \value_1_0[21]\); - - un12_res_I_41 : OR2 - port map(A => \value_RNIFB5J[6]\, B => \value_RNIHJ5J[7]\, - Y => \DWACT_FDEC_E_0[3]\); - - \r.timers_1.irqpen_RNO_1\ : AO1 - port map(A => irqpen_0_sqmuxa_1, B => irq_2, C => irqpen_0, - Y => irqpen_4); - - \r.timers_2.value_RNIOB4P1[17]\ : OR3C - port map(A => \reload_m[17]\, B => \readdata_9[17]\, C => - \value_m[17]\, Y => prdata_3); - - \r.timers_1.reload[17]\ : DFN1E1 - port map(D => pwdata_11, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[17]\); - - \r.reload_RNO_0[3]\ : MX2 - port map(A => \reload_0[3]\, B => pwdata_0(3), S => - reload_1_sqmuxa_2, Y => N_626); - - un12_res_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \r.timers_2.reload_RNO[31]\ : NOR2B - port map(A => rstn, B => N_584, Y => \reload_RNO[31]\); - - \r.timers_2.value[20]\ : DFN1E0 - port map(D => \value_1[20]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[20]\); - - \r.timers_2.value[15]\ : DFN1E0 - port map(D => \value_1[15]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[15]\); - - \r.timers_1.value_RNI534J[1]\ : MX2 - port map(A => \value[1]\, B => \un1_timer0[9]\, S => - \tsel_0[0]\, Y => \value_RNI534J[1]\); - - un12_res_I_38 : XNOR2 - port map(A => N_136, B => \value_RNIHJ5J[7]\, Y => I_38_2); - - un12_res_I_203 : XNOR2 - port map(A => N_19_0, B => \value_RNI7UUG[28]\, Y => - I_203_1); - - \r.timers_2.value_RNO[26]\ : MX2A - port map(A => N_435, B => pwdata_20, S => - value_1_sqmuxa_0_0, Y => \value_1_0[26]\); - - \r.timers_2.reload[23]\ : DFN1 - port map(D => \reload_RNO[23]\, CLK => lclk_c, Q => - \reload[23]\); - - \r.timers_1.value[19]\ : DFN1E0 - port map(D => \value_1[19]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[27]\); - - \r.scaler_RNO_1[0]\ : MX2A - port map(A => \scaler[0]\, B => \reload_0[0]\, S => I_44, Y - => N_324); - - \r.timers_1.irqpen_RNO_2\ : NOR3C - port map(A => un4_i, B => irqen_0, C => \tsel_0[0]\, Y => - irqpen_0_sqmuxa_1); - - un12_res_I_98 : XNOR2 - port map(A => N_93, B => \value_RNIJ3QI[16]\, Y => I_98_1); - - un12_res_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \value_RNIJR5J[8]\, C - => \value_RNIL36J[9]\, Y => N_123); - - \comb.un1_apbi_0\ : OR2B - port map(A => pwrite, B => penable, Y => \un1_apbi_0\); - - un6_scaler_I_37 : OR3 - port map(A => \DWACT_FDEC_E_0[0]\, B => \DWACT_FDEC_E[2]\, - C => \scaler[6]\, Y => N_9); - - \r.timers_2.reload_RNO_0[19]\ : MX2 - port map(A => \reload[19]\, B => pwdata_13, S => - reload_1_sqmuxa_1, Y => N_572); - - \r.timers_1.value_RNI7B4J[2]\ : MX2 - port map(A => \value[2]\, B => \un1_timer0[10]\, S => - \tsel_0[0]\, Y => \value_RNI7B4J[2]\); - - un12_res_I_129 : XNOR2 - port map(A => N_71, B => \value_RNINTUG[20]\, Y => I_129_1); - - \r.timers_1.chain_RNIQO9C\ : NOR2A - port map(A => chain, B => N_198, Y => N_205); - - \r.timers_1.value_RNO[9]\ : MX2A - port map(A => N_351, B => pwdata_0(9), S => - value_1_sqmuxa_0, Y => \value_1[9]\); - - \r.timers_1.reload_RNIKQ2E[31]\ : MX2 - port map(A => \un1_timer0[39]\, B => \reload_0[31]\, S => - paddr(2), Y => N_239); - - un12_res_I_84 : XNOR2 - port map(A => N_103, B => \value_RNIF3QI[14]\, Y => I_84_1); - - \r.timers_1.value_RNO_0[13]\ : MX2C - port map(A => I_77_1, B => \reload_0[13]\, S => - value_1_sn_N_9_i_0_0, Y => N_355); - - \r.timers_1.irqpen_RNO_0\ : AO1B - port map(A => load_1_sqmuxa_1, B => pwdata_0(4), C => - irqpen_4, Y => irqpen_1); - - \r.scaler_RNO_0[0]\ : MX2C - port map(A => pwdata_0(0), B => N_324, S => scaler_0_sqmuxa, - Y => \scaler_1[0]\); - - \r.timers_2.value_RNO_0[30]\ : MX2C - port map(A => I_217, B => \reload[30]\, S => - value_1_sn_N_9_i_1, Y => N_439); - - \r.timers_2.value_RNI4DCH[17]\ : OR2A - port map(A => \value[17]\, B => value_0_sqmuxa, Y => - \value_m[17]\); - - \r.timers_2.reload_RNO[2]\ : OR2A - port map(A => rstn, B => N_555, Y => \reload_RNO[2]\); - - \r.timers_1.value[10]\ : DFN1E0 - port map(D => \value_1[10]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[18]\); - - \r.timers_2.value_RNO[7]\ : MX2A - port map(A => N_416, B => pwdata_0(7), S => - value_1_sqmuxa_0_0, Y => \value_1_0[7]\); - - \r.timers_2.value_RNO_0[23]\ : MX2C - port map(A => I_156_1, B => \reload[23]\, S => - value_1_sn_N_9_i_1, Y => N_432); - - \v.scaler_0_sqmuxa\ : OR2A - port map(A => un1_apbi_7_3, B => un1_apbi, Y => - scaler_0_sqmuxa); - - \r.timers_2.value[14]\ : DFN1E0 - port map(D => \value_1[14]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[14]\); - - \r.timers_2.reload_RNO_0[0]\ : MX2 - port map(A => \reload[0]\, B => pwdata_0(0), S => - reload_1_sqmuxa_0_0, Y => N_553); - - \r.timers_2.value_RNO[17]\ : MX2A - port map(A => N_426, B => pwdata_11, S => value_1_sqmuxa_1, - Y => \value_1_0[17]\); - - un12_res_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \r.timers_2.value_RNO[14]\ : MX2A - port map(A => N_423, B => pwdata_0(14), S => - value_1_sqmuxa_1, Y => \value_1[14]\); - - \r.timers_2.reload_RNIKNBI[19]\ : OR2A - port map(A => \reload[19]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[19]\); - - \r.tick_RNIGFUB\ : AO1D - port map(A => \un1_timer0[7]\, B => \tsel[0]\, C => - \tsel[1]\, Y => tsel_1_sqmuxa); - - \r.timers_2.value_RNIJAIH[9]\ : OR2A - port map(A => \value[9]\, B => value_0_sqmuxa, Y => - value_m_5); - - \r.timers_1.value_RNO[12]\ : MX2A - port map(A => N_354, B => pwdata_0(12), S => value_1_sqmuxa, - Y => \value_1[12]\); - - \readdata_1_sqmuxa_1_0\ : OR2A - port map(A => readdata51, B => N_6455_0, Y => - readdata_1_sqmuxa_1_0_net_1); - - \r.reload_RNI98OI[4]\ : OR2A - port map(A => \reload[4]\, B => \readdata56\, Y => - reload_m_4); - - \r.timers_1.load_RNIHKP9\ : NOR2A - port map(A => load, B => N_198, Y => N_202); - - GND_i : GND - port map(Y => \GND\); - - \r.timers_1.value_RNIBR4J[4]\ : MX2 - port map(A => \value[4]\, B => \un1_timer0[12]\, S => - \tsel_0[0]\, Y => \value_RNIBR4J[4]\); - - \r.reload_RNO[7]\ : OR2A - port map(A => rstn, B => N_630, Y => \reload_RNO_0[7]\); - - \r.timers_1.value_RNO[2]\ : MX2A - port map(A => N_344, B => pwdata_0(2), S => - value_1_sqmuxa_0, Y => \value_1[2]\); - - \r.timers_2.value_RNI5DCH[18]\ : OR2A - port map(A => \value[18]\, B => \value_0_sqmuxa_0\, Y => - \value_m[18]\); - - un12_res_I_20 : XNOR2 - port map(A => N_149, B => \value_RNIBR4J[4]\, Y => I_20_5); - - un12_res_I_216 : OR3 - port map(A => \DWACT_FDEC_E[24]\, B => \DWACT_FDEC_E[23]\, - C => \DWACT_FDEC_E[26]\, Y => N_9_0); - - \r.timers_2.enable_RNO_1\ : MX2 - port map(A => restart, B => pwdata_0(0), S => - load_1_sqmuxa_0, Y => enable_1_0); - - \r.timers_1.value[27]\ : DFN1E0 - port map(D => \value_1[27]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[35]\); - - \r.timers_1.restart_RNIM16U1\ : OR3C - port map(A => \readdata_9[1]\, B => \readdata_9_i_m_0[1]\, - C => \readdata57\, Y => readdata_9_i_m(1)); - - \r.timers_2.value_RNI4G211[2]\ : OA1A - port map(A => \value[2]\, B => \value_0_sqmuxa_0\, C => - \scaler_m[2]\, Y => \readdata_iv_2[2]\); - - \r.timers_1.reload[7]\ : DFN1E1 - port map(D => pwdata_0(7), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[7]\); - - \r.timers_2.value[9]\ : DFN1E0 - port map(D => \value_1_0[9]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[9]\); - - \r.timers_1.value_RNO[18]\ : MX2A - port map(A => N_360, B => pwdata_12, S => value_1_sqmuxa, Y - => \value_1[18]\); - - \r.reload[3]\ : DFN1 - port map(D => \reload_RNO_0[3]\, CLK => lclk_c, Q => - \reload_0[3]\); - - \r.timers_1.value_RNO[7]\ : MX2A - port map(A => N_349, B => pwdata_0(7), S => - value_1_sqmuxa_0, Y => \value_1[7]\); - - \r.timers_1.value_RNO_0[7]\ : MX2C - port map(A => I_38_2, B => \reload_1[7]\, S => - value_1_sn_N_9_i_0_0, Y => N_349); - - \r.timers_1.reload[20]\ : DFN1E1 - port map(D => pwdata_14, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[20]\); - - \r.timers_1.reload_RNIVE7C[3]\ : MX2 - port map(A => \un1_timer0[11]\, B => \reload_1[3]\, S => - paddr_2(2), Y => N_211); - - \v.timers_2.value_1_sqmuxa_0\ : NOR2 - port map(A => \value_0_sqmuxa_0\, B => un1_apbi, Y => - value_1_sqmuxa_0_0); - - \r.timers_1.value_RNO[22]\ : MX2A - port map(A => N_364, B => pwdata_16, S => value_1_sqmuxa, Y - => \value_1_0[22]\); - - \r.timers_2.reload_RNO[23]\ : NOR2B - port map(A => rstn, B => N_576, Y => \reload_RNO[23]\); - - un6_scaler_I_31 : XNOR2 - port map(A => N_14, B => \scaler[6]\, Y => I_31_5); - - un12_res_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \value_RNI1MUG[18]\, Y => N_76); - - \r.timers_2.restart_RNIIKBB\ : OR2 - port map(A => \readdata_2_sqmuxa\, B => restart, Y => - restart_RNIIKBB); - - \r.timers_2.value_RNO_0[9]\ : MX2C - port map(A => I_52_2, B => \reload[9]\, S => - value_1_sn_N_9_i_0, Y => N_418); - - \r.timers_2.enable\ : DFN1 - port map(D => enable_RNO_0, CLK => lclk_c, Q => enable_0); - - \r.timers_1.irqpen_RNIMRIG\ : NOR2A - port map(A => irqpen_0, B => N_198, Y => N_204); - - \r.scaler[7]\ : DFN1 - port map(D => \scaler_RNO[7]\, CLK => lclk_c, Q => - \scaler[7]\); - - \r.timers_2.reload_RNIERAI[22]\ : OR2A - port map(A => \reload[22]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => \reload_m[22]\); - - \v.timers_2.reload_1_sqmuxa\ : NOR2 - port map(A => \readdata_1_sqmuxa_1\, B => un1_apbi, Y => - reload_1_sqmuxa_1); - - \r.timers_1.value_RNI2BCL[25]\ : OR2B - port map(A => \N_240\, B => N_233, Y => \readdata_9[25]\); - - \r.scaler_RNO_0[7]\ : MX2C - port map(A => pwdata_0(7), B => N_331, S => scaler_0_sqmuxa, - Y => \scaler_1[7]\); - - un12_res_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \r.timers_2.reload_RNO_0[16]\ : MX2 - port map(A => \reload[16]\, B => pwdata_10, S => - reload_1_sqmuxa_0_0, Y => N_569); - - \r.timers_2.reload[20]\ : DFN1 - port map(D => \reload_RNO[20]\, CLK => lclk_c, Q => - \reload[20]\); - - \r.timers_2.enable_RNO_0\ : MX2 - port map(A => enable_1_0, B => enable_0, S => - enable_1_sqmuxa_0, Y => N_543); - - \r.timers_2.reload_RNO[11]\ : OR2A - port map(A => rstn, B => N_564, Y => \reload_RNO[11]\); - - \r.timers_2.reload_RNO_0[4]\ : MX2 - port map(A => \reload_0[4]\, B => pwdata_0(4), S => - reload_1_sqmuxa_0_0, Y => N_557); - - \r.timers_2.reload[31]\ : DFN1 - port map(D => \reload_RNO[31]\, CLK => lclk_c, Q => - \reload[31]\); - - \r.scaler_RNIMPGF[0]\ : OR2B - port map(A => \scaler[0]\, B => \readdata55\, Y => - scaler_m_0); - - \r.timers_2.value_RNI2DCH[15]\ : OR2A - port map(A => \value[15]\, B => value_0_sqmuxa, Y => - value_m_11); - - \r.timers_1.value_RNO_0[14]\ : MX2C - port map(A => I_84_1, B => \reload_0[14]\, S => - value_1_sn_N_9_i, Y => N_356); - - \r.timers_1.value_RNO[28]\ : MX2A - port map(A => N_370, B => pwdata_22, S => value_1_sqmuxa, Y - => \value_1[28]\); - - un12_res_I_34 : OR3 - port map(A => \value_RNI9J4J[3]\, B => \value_RNIBR4J[4]\, - C => \value_RNID35J[5]\, Y => \DWACT_FDEC_E_0[2]\); - - \r.timers_1.value_RNO_0[18]\ : MX2C - port map(A => I_115_1, B => \reload[18]\, S => - value_1_sn_N_9_i, Y => N_360); - - \r.timers_1.reload[23]\ : DFN1E1 - port map(D => pwdata_17, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[23]\); - - \r.timers_1.reload_RNIG3J51[4]\ : MX2C - port map(A => N_204, B => N_212, S => \N_240\, Y => - readdata_9_4); - - un6_scaler_I_12 : OR3 - port map(A => \scaler[0]\, B => \scaler[1]\, C => - \scaler[2]\, Y => N_27); - - \r.timers_2.value_RNO_0[19]\ : MX2C - port map(A => I_122_1, B => \reload[19]\, S => - value_1_sn_N_9_i_1, Y => N_428); - - \r.timers_2.value[13]\ : DFN1E0 - port map(D => \value_1_0[13]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[13]\); - - \r.timers_1.value_RNIPTUG[21]\ : MX2 - port map(A => \value[21]\, B => \un1_timer0[29]\, S => - \tsel[0]\, Y => \value_RNIPTUG[21]\); - - \r.timers_1.value_RNIFB5J[6]\ : MX2 - port map(A => \value[6]\, B => \un1_timer0[14]\, S => - \tsel_0[0]\, Y => \value_RNIFB5J[6]\); - - un12_res_I_173 : XNOR2 - port map(A => N_40, B => \value_RNI1UUG[25]\, Y => I_173_1); - - \r.timers_1.value[0]\ : DFN1E0 - port map(D => \value_1[0]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[8]\); - - \r.timers_2.reload_RNO[20]\ : NOR2B - port map(A => rstn, B => N_573, Y => \reload_RNO[20]\); - - un12_res_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \r.timers_2.value_RNO_0[24]\ : MX2C - port map(A => I_166_1, B => \reload[24]\, S => - value_1_sn_N_9_i_0, Y => N_433); - - un6_scaler_I_16 : OR3 - port map(A => \scaler[0]\, B => \scaler[1]\, C => - \scaler[2]\, Y => \DWACT_FDEC_E_0[0]\); - - \v.timers_1.reload_1_sqmuxa_0\ : NOR3A - port map(A => readdata30, B => N_6455_0, C => un1_apbi, Y - => reload_1_sqmuxa_0); - - \r.timers_2.value_RNO_0[28]\ : MX2C - port map(A => I_203_1, B => \reload[28]\, S => - value_1_sn_N_9_i_1, Y => N_437); - - \r.scaler_RNO_1[1]\ : MX2 - port map(A => I_5_6, B => \reload_0[1]\, S => I_44, Y => - N_325); - - \r.timers_2.value_RNO[30]\ : MX2A - port map(A => N_439, B => pwdata_24, S => value_1_sqmuxa_1, - Y => \value_1_0[30]\); - - \r.timers_2.value_RNO[8]\ : MX2A - port map(A => N_417, B => pwdata_0(8), S => - value_1_sqmuxa_0_0, Y => \value_1_0[8]\); - - \comb.2.readdata51_1\ : OR2A - port map(A => paddr(5), B => paddr(6), Y => \readdata51_1\); - - \r.timers_1.value_RNID35J[5]\ : MX2 - port map(A => \value[5]\, B => \un1_timer0[13]\, S => - \tsel_0[0]\, Y => \value_RNID35J[5]\); - - \r.timers_1.value_RNI3EJC[14]\ : MX2 - port map(A => \un1_timer0[22]\, B => \reload_0[14]\, S => - paddr_2(2), Y => N_222); - - \r.timers_2.reload_RNO_0[27]\ : MX2 - port map(A => \reload[27]\, B => pwdata_21, S => - reload_1_sqmuxa_1, Y => N_580); - - \r.timers_2.value_RNI0DCH[13]\ : OR2A - port map(A => \value[13]\, B => value_0_sqmuxa, Y => - value_m_9); - - un12_res_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \value_RNIPTUG[21]\, - Y => \DWACT_FDEC_E[16]\); - - \r.timers_2.reload_RNO_0[9]\ : MX2 - port map(A => \reload[9]\, B => pwdata_0(9), S => - reload_1_sqmuxa_0_0, Y => N_562); - - \r.timers_1.value[5]\ : DFN1E0 - port map(D => \value_1[5]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[13]\); - - \r.timers_2.reload[22]\ : DFN1 - port map(D => \reload_RNO[22]\, CLK => lclk_c, Q => - \reload[22]\); - - \r.timers_2.reload_RNO_0[1]\ : MX2 - port map(A => \reload[1]\, B => pwdata_0(1), S => - reload_1_sqmuxa_0_0, Y => N_554); - - \r.timers_2.reload_RNO_0[21]\ : MX2 - port map(A => \reload[21]\, B => pwdata_15, S => - reload_1_sqmuxa_1, Y => N_574); - - \r.timers_2.reload_RNO[16]\ : NOR2B - port map(A => rstn, B => N_569, Y => \reload_RNO[16]\); - - \r.timers_2.value_RNO[31]\ : MX2A - port map(A => N_440, B => pwdata_25, S => value_1_sqmuxa_1, - Y => \value_1[31]\); - - un6_scaler_I_23 : OR3 - port map(A => \DWACT_FDEC_E_0[0]\, B => \scaler[3]\, C => - \scaler[4]\, Y => N_19); - - \r.timers_2.value[26]\ : DFN1E0 - port map(D => \value_1_0[26]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[26]\); - - un12_res_I_199 : OR2 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - Y => \DWACT_FDEC_E[24]\); - - \r.timers_1.value_RNI6IJC[24]\ : MX2 - port map(A => \un1_timer0[32]\, B => \reload_0[24]\, S => - paddr_1(2), Y => N_232_1); - - un12_res_I_206 : OR2 - port map(A => \value_RNI5UUG[27]\, B => \value_RNI7UUG[28]\, - Y => \DWACT_FDEC_E[25]\); - - \r.timers_1.chain\ : DFN1E1 - port map(D => pwdata_0(5), CLK => lclk_c, E => - load_1_sqmuxa_1, Q => chain); - - \r.timers_2.reload_RNO[5]\ : OR2A - port map(A => rstn, B => N_558, Y => \reload_RNO[5]\); - - \r.timers_2.chain_RNO\ : NOR2B - port map(A => rstn, B => N_619, Y => chain_RNO); - - \v.timers_1.value_1_sqmuxa_0\ : NOR3A - port map(A => readdata30, B => N_232_0, C => un1_apbi, Y - => value_1_sqmuxa_0); - - \r.timers_2.value_RNO[23]\ : MX2A - port map(A => N_432, B => pwdata_17, S => value_1_sqmuxa_1, - Y => \value_1_0[23]\); - - \r.timers_1.value_RNO[19]\ : MX2A - port map(A => N_361, B => pwdata_13, S => value_1_sqmuxa, Y - => \value_1[19]\); - - \r.timers_2.value_RNO_0[31]\ : MX2C - port map(A => I_224, B => \reload[31]\, S => - value_1_sn_N_9_i_1, Y => N_440); - - \r.timers_2.value_RNI0HCH[20]\ : OR2A - port map(A => \value[20]\, B => \value_0_sqmuxa_0\, Y => - value_m_16); - - \r.timers_1.reload_RNICRMD[2]\ : MX2 - port map(A => \un1_timer0[10]\, B => \reload_1[2]\, S => - paddr(2), Y => N_210); - - un6_scaler_I_44 : NOR3 - port map(A => \DWACT_FDEC_E[3]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E_0[0]\, Y => I_44); - - \r.timers_1.value_RNO_0[2]\ : MX2C - port map(A => I_9_5, B => \reload_1[2]\, S => - value_1_sn_N_9_i_0_0, Y => N_344); - - \r.timers_2.reload_RNO[28]\ : NOR2B - port map(A => rstn, B => N_581, Y => \reload_RNO[28]\); - - \r.timers_2.value[5]\ : DFN1E0 - port map(D => \value_1_0[5]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[5]\); - - un12_res_I_69 : OR3 - port map(A => \value_RNIL36J[9]\, B => \value_RNI73QI[10]\, - C => \value_RNI93QI[11]\, Y => \DWACT_FDEC_E[7]\); - - un12_res_I_186 : XNOR2 - port map(A => N_31, B => \value_RNI3UUG[26]\, Y => I_186_1); - - \r.scaler_RNO[5]\ : OR2B - port map(A => rstn, B => \scaler_1[5]\, Y => - \scaler_RNO[5]\); - - \r.timers_2.irqpen_RNIM1UI\ : OR2A - port map(A => irqpen, B => \readdata_2_sqmuxa\, Y => - irqpen_m); - - \r.timers_1.irqpen\ : DFN1 - port map(D => irqpen_RNO_0, CLK => lclk_c, Q => irqpen_0); - - \r.timers_2.value_RNO[9]\ : MX2A - port map(A => N_418, B => pwdata_0(9), S => - value_1_sqmuxa_0_0, Y => \value_1_0[9]\); - - \r.reload_RNI84OI[3]\ : OR2A - port map(A => \reload_0[3]\, B => \readdata56\, Y => - reload_m_0_3); - - \r.timers_1.value_RNO_0[16]\ : MX2C - port map(A => I_98_1, B => \reload_0[16]\, S => - value_1_sn_N_9_i, Y => N_358); - - \r.timers_1.value_RNIB3QI[12]\ : MX2 - port map(A => \value[12]\, B => \un1_timer0[20]\, S => - \tsel_0[0]\, Y => \value_RNIB3QI[12]\); - - \r.timers_1.irq\ : DFN1 - port map(D => load_RNIC53BJ, CLK => lclk_c, Q => - \un1_timer0[6]\); - - \comb.un1_apbi_0_0\ : NOR2 - port map(A => N_78, B => \un1_apbi_0\, Y => un1_apbi_0_0); - - \r.timers_1.value[16]\ : DFN1E0 - port map(D => \value_1[16]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[24]\); - - \r.timers_1.restart_RNI0PFV\ : MX2C - port map(A => N_201, B => N_209, S => \N_240\, Y => - \readdata_9[1]\); - - un12_res_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E_0[3]\, Y => \DWACT_FDEC_E[4]\); - - un12_res_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_45); - - \r.timers_2.reload_RNO[29]\ : NOR2B - port map(A => rstn, B => N_582, Y => \reload_RNO[29]\); - - \r.timers_1.value_RNO_0[25]\ : MX2C - port map(A => I_173_1, B => \reload_0[25]\, S => - value_1_sn_N_9_i_0_0, Y => N_367); - - \r.timers_2.value_RNO_0[26]\ : MX2C - port map(A => I_186_1, B => \reload[26]\, S => - value_1_sn_N_9_i_0, Y => N_435); - - \r.timers_2.value_RNO[12]\ : MX2A - port map(A => N_421, B => pwdata_0(12), S => - value_1_sqmuxa_1, Y => \value_1_0[12]\); - - \r.scaler_RNIO1HF[2]\ : OR2B - port map(A => \scaler[2]\, B => \readdata55\, Y => - \scaler_m[2]\); - - \r.reload_RNI6SNI[1]\ : OR2 - port map(A => \reload_0[1]\, B => \readdata56\, Y => - reload_RNI6SNI(1)); - - \r.timers_1.value_RNI7UUG[28]\ : MX2 - port map(A => \value[28]\, B => \un1_timer0[36]\, S => - \tsel[0]\, Y => \value_RNI7UUG[28]\); - - \r.timers_2.reload[14]\ : DFN1 - port map(D => \reload_RNO[14]\, CLK => lclk_c, Q => - \reload[14]\); - - \r.timers_1.value_RNO[29]\ : MX2A - port map(A => N_371, B => pwdata_23, S => value_1_sqmuxa, Y - => \value_1_0[29]\); - - \r.timers_1.reload[18]\ : DFN1E1 - port map(D => pwdata_12, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload[18]\); - - \r.timers_1.irqpen_RNO\ : NOR2A - port map(A => rstn, B => irqpen_1, Y => irqpen_RNO_0); - - \r.scaler_RNO_1[4]\ : MX2 - port map(A => I_20_6, B => \reload[4]\, S => I_44, Y => - N_328); - - \r.timers_1.value[22]\ : DFN1E0 - port map(D => \value_1_0[22]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[30]\); - - \r.timers_1.reload[31]\ : DFN1E1 - port map(D => pwdata_25, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[31]\); - - \r.reload_RNO[2]\ : OR2A - port map(A => rstn, B => N_625, Y => \reload_RNO_0[2]\); - - \r.timers_2.restart_RNO\ : NOR2B - port map(A => rstn, B => N_618, Y => restart_RNO); - - \r.timers_2.reload_RNO_0[6]\ : MX2 - port map(A => \reload[6]\, B => pwdata_0(6), S => - reload_1_sqmuxa_0_0, Y => N_559); - - \r.timers_2.reload[11]\ : DFN1 - port map(D => \reload_RNO[11]\, CLK => lclk_c, Q => - \reload[11]\); - - \r.timers_2.value_RNO[18]\ : MX2A - port map(A => N_427, B => pwdata_12, S => value_1_sqmuxa_1, - Y => \value_1_0[18]\); - - \r.timers_1.reload[27]\ : DFN1E1 - port map(D => pwdata_21, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[27]\); - - un12_res_I_209 : OR3 - port map(A => \DWACT_FDEC_E[24]\, B => \DWACT_FDEC_E[23]\, - C => \DWACT_FDEC_E[25]\, Y => N_14_0); - - \r.timers_2.reload_RNIFVAI[23]\ : OR2A - port map(A => \reload[23]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[23]\); - - \r.timers_1.reload[19]\ : DFN1E1 - port map(D => pwdata_13, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[19]\); - - \r.timers_2.reload[1]\ : DFN1 - port map(D => \reload_RNO[1]\, CLK => lclk_c, Q => - \reload[1]\); - - \r.timers_2.value_RNISJ4P1[18]\ : OR3C - port map(A => \reload_m[18]\, B => \readdata_9[18]\, C => - \value_m[18]\, Y => prdata_4); - - \r.timers_2.value[21]\ : DFN1E0 - port map(D => \value_1_0[21]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[21]\); - - \r.reload[5]\ : DFN1 - port map(D => \reload_RNO_0[5]\, CLK => lclk_c, Q => - \reload_0[5]\); - - \r.timers_2.value[3]\ : DFN1E0 - port map(D => \value_1_0[3]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[3]\); - - \r.scaler_RNO_0[1]\ : MX2C - port map(A => pwdata_0(1), B => N_325, S => scaler_0_sqmuxa, - Y => \scaler_1[1]\); - - \r.timers_2.reload[4]\ : DFN1 - port map(D => \reload_RNO[4]\, CLK => lclk_c, Q => - \reload_0[4]\); - - \r.tsel_RNIG6TH[0]\ : XA1A - port map(A => \tsel[0]\, B => tsel_1_sqmuxa, C => rstn, Y - => \tsel_RNIG6TH[0]\); - - \r.reload_RNO[4]\ : OR2A - port map(A => rstn, B => N_627, Y => \reload_RNO_0[4]\); - - \r.tsel_RNI3KAN[0]\ : NOR2B - port map(A => \tsel[0]\, B => un4_i, Y => irq_0_sqmuxa); - - \r.timers_1.value_RNIVLUG[17]\ : MX2 - port map(A => \value[17]\, B => \un1_timer0[25]\, S => - \tsel[0]\, Y => \value_RNIVLUG[17]\); - - \r.timers_2.reload_RNO[15]\ : OR2A - port map(A => rstn, B => N_568, Y => \reload_RNO[15]\); - - \r.timers_1.reload[16]\ : DFN1E1 - port map(D => pwdata_10, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[16]\); - - un12_res_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_71); - - \r.timers_2.reload_RNO[4]\ : OR2A - port map(A => rstn, B => N_557, Y => \reload_RNO[4]\); - - \r.tsel_RNIHTGN[1]\ : OR2B - port map(A => \tsel[1]\, B => un34_i, Y => irq_0_sqmuxa_0); - - \r.timers_1.reload_RNI6V7C[7]\ : MX2 - port map(A => \un1_timer0[15]\, B => \reload_1[7]\, S => - paddr_1(2), Y => N_215); - - \r.reload_RNO_0[5]\ : MX2 - port map(A => \reload_0[5]\, B => pwdata_0(5), S => - reload_1_sqmuxa_2, Y => N_628); - - \r.timers_1.value_RNO_0[22]\ : MX2C - port map(A => I_143_1, B => \reload_0[22]\, S => - value_1_sn_N_9_i, Y => N_364); - - \r.timers_1.value_RNITTUG[23]\ : MX2 - port map(A => \value[23]\, B => \un1_timer0[31]\, S => - \tsel[0]\, Y => \value_RNITTUG[23]\); - - \r.timers_2.value[18]\ : DFN1E0 - port map(D => \value_1_0[18]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[18]\); - - un12_res_I_159 : OR3 - port map(A => \value_RNIPTUG[21]\, B => \value_RNIRTUG[22]\, - C => \value_RNITTUG[23]\, Y => \DWACT_FDEC_E[17]\); - - \r.timers_2.irqpen_RNO\ : NOR2A - port map(A => rstn, B => irqpen_1_0, Y => irqpen_RNO); - - \r.timers_1.value_RNINTUG[20]\ : MX2 - port map(A => \value[20]\, B => \un1_timer0[28]\, S => - \tsel[0]\, Y => \value_RNINTUG[20]\); - - \r.timers_2.load\ : DFN1 - port map(D => load_RNO_0, CLK => lclk_c, Q => load_0); - - \r.timers_1.value_RNO_0[20]\ : MX2C - port map(A => I_129_1, B => \reload_0[20]\, S => - value_1_sn_N_9_i, Y => N_362); - - \r.timers_1.chain_RNI6LP21\ : MX2C - port map(A => N_205, B => N_213, S => \N_240\, Y => - readdata_9_5); - - \r.timers_1.value[11]\ : DFN1E0 - port map(D => \value_1[11]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[19]\); - - un6_scaler_I_24 : XNOR2 - port map(A => N_19, B => \scaler[5]\, Y => I_24_7); - - un12_res_I_24 : XNOR2 - port map(A => N_146, B => \value_RNID35J[5]\, Y => I_24_6); - - \r.timers_2.reload_RNIDNAI[21]\ : OR2A - port map(A => \reload[21]\, B => \readdata_1_sqmuxa_1\, Y - => reload_m_21); - - \r.timers_1.value_RNI1AJC[13]\ : MX2 - port map(A => \un1_timer0[21]\, B => \reload_0[13]\, S => - paddr_2(2), Y => N_221); - - \r.timers_2.value_RNO_0[3]\ : MX2C - port map(A => I_13_9, B => \reload[3]\, S => - value_1_sn_N_9_i_0, Y => N_412); - - \r.timers_2.value_RNI2HCH[22]\ : OR2A - port map(A => \value[22]\, B => \value_0_sqmuxa_0\, Y => - value_m_18); - - \r.timers_2.value_RNO[25]\ : MX2A - port map(A => N_434, B => pwdata_19, S => - value_1_sqmuxa_0_0, Y => \value_1_0[25]\); - - un12_res_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \value_RNIL36J[9]\, C - => \value_RNI73QI[10]\, Y => N_116); - - \r.timers_1.value[3]\ : DFN1E0 - port map(D => \value_1[3]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[11]\); - - un12_res_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \value_RNIPTUG[21]\, - C => \value_RNIRTUG[22]\, Y => \DWACT_FDEC_E[33]\); - - \r.timers_2.value_RNIH2IH[7]\ : OR2A - port map(A => \value[7]\, B => value_0_sqmuxa, Y => - value_m_3); - - \r.timers_2.load_RNIP9AN3\ : NOR3A - port map(A => irq_0_sqmuxa_0, B => load_0, C => - value_1_sqmuxa_0_0, Y => value_2_sqmuxa); - - un12_res_I_51 : OR2 - port map(A => \value_RNIJR5J[8]\, B => \DWACT_FDEC_E[4]\, Y - => N_126); - - \r.timers_1.value_RNI4IJC[15]\ : MX2 - port map(A => \un1_timer0[23]\, B => \reload_0[15]\, S => - paddr_1(2), Y => N_223); - - \r.reload_RNO[3]\ : OR2A - port map(A => rstn, B => N_626, Y => \reload_RNO_0[3]\); - - \v.timers_2.value_1_sqmuxa\ : NOR2 - port map(A => value_0_sqmuxa, B => un1_apbi, Y => - value_1_sqmuxa_1); - - un12_res_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E_0[3]\, Y => N_131); - - un12_res_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \value_RNIB3QI[12]\, Y => N_108); - - \r.timers_2.reload_RNO_0[25]\ : MX2 - port map(A => \reload[25]\, B => pwdata_19, S => - reload_1_sqmuxa_1, Y => N_578); - - \r.timers_2.reload[15]\ : DFN1 - port map(D => \reload_RNO[15]\, CLK => lclk_c, Q => - \reload[15]\); - - \r.timers_2.reload_RNO[14]\ : OR2A - port map(A => rstn, B => N_567, Y => \reload_RNO[14]\); - - \r.timers_2.reload_RNO[1]\ : OR2A - port map(A => rstn, B => N_554, Y => \reload_RNO[1]\); - - \r.timers_2.reload[17]\ : DFN1 - port map(D => \reload_RNO[17]\, CLK => lclk_c, Q => - \reload[17]\); - - \r.timers_2.value_RNIHJ3P1[23]\ : OR3C - port map(A => \reload_m[23]\, B => \readdata_9[23]\, C => - \value_m[23]\, Y => prdata_9); - - \r.timers_1.value_RNI8MJC[25]\ : MX2 - port map(A => \un1_timer0[33]\, B => \reload_0[25]\, S => - paddr_1(2), Y => N_233); - - \r.timers_1.value[29]\ : DFN1E0 - port map(D => \value_1_0[29]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[37]\); - - \r.timers_2.irqpen\ : DFN1 - port map(D => irqpen_RNO, CLK => lclk_c, Q => irqpen); - - un12_res_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_40); - - \r.timers_2.value_RNIFBLN1[19]\ : AO1C - port map(A => \value_0_sqmuxa_0\, B => \value[19]\, C => - \readdata_1_iv_0[19]\, Y => prdata_5); - - \comb.1.readdata_9_sn_m3_0\ : NOR2A - port map(A => readdata30, B => paddr_0(3), Y => \N_240_0\); - - \comb.1.readdata_9_i_m_0[1]\ : AOI1 - port map(A => readdata51, B => \un1_apbi_2\, C => - un1_apbi_7_3, Y => \readdata_9_i_m_0[1]\); - - \r.timers_2.value_RNO[19]\ : MX2A - port map(A => N_428, B => pwdata_13, S => value_1_sqmuxa_1, - Y => \value_1_0[19]\); - - \r.reload_RNO[6]\ : OR2A - port map(A => rstn, B => N_629, Y => \reload_RNO_0[6]\); - - \r.reload_RNO[0]\ : OR2A - port map(A => rstn, B => N_623, Y => \reload_RNO_0[0]\); - - \r.timers_1.value_RNIRTUG[22]\ : MX2 - port map(A => \value[22]\, B => \un1_timer0[30]\, S => - \tsel[0]\, Y => \value_RNIRTUG[22]\); - - \r.timers_1.value_RNIF3QI[14]\ : MX2 - port map(A => \value[14]\, B => \un1_timer0[22]\, S => - \tsel_0[0]\, Y => \value_RNIF3QI[14]\); - - \r.timers_1.enable\ : DFN1 - port map(D => enable_RNO, CLK => lclk_c, Q => enable); - - \r.timers_1.value_RNO_0[5]\ : MX2C - port map(A => I_24_6, B => \reload_1[5]\, S => - value_1_sn_N_9_i_0_0, Y => N_347); - - \r.timers_1.reload[11]\ : DFN1E1 - port map(D => pwdata_0(11), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[11]\); - - un12_res_I_125 : OR2 - port map(A => \value_RNI1MUG[18]\, B => \value_RNI3MUG[19]\, - Y => \DWACT_FDEC_E[14]\); - - \r.timers_1.value_RNITT761[15]\ : AOI1B - port map(A => \N_240_0\, B => N_223, C => \reload_m[15]\, Y - => readdata_1_iv_0_2); - - \r.timers_2.value[0]\ : DFN1E0 - port map(D => \value_1_0[0]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[0]\); - - \r.timers_2.value_RNO_0[13]\ : MX2C - port map(A => I_77_1, B => \reload[13]\, S => - value_1_sn_N_9_i_0, Y => N_422); - - un6_scaler_I_20 : XNOR2 - port map(A => N_22, B => \scaler[4]\, Y => I_20_6); - - \r.timers_1.value[20]\ : DFN1E0 - port map(D => \value_1_0[20]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[28]\); - - \r.scaler_RNO_0[5]\ : MX2C - port map(A => pwdata_0(5), B => N_329, S => scaler_0_sqmuxa, - Y => \scaler_1[5]\); - - \r.timers_1.restart\ : DFN1E1 - port map(D => pwdata_1_0, CLK => lclk_c, E => - load_1_sqmuxa_1, Q => restart_0); - - \r.timers_1.irq_RNIBSFB\ : NOR2B - port map(A => \un1_timer0[6]\, B => irqen_0, Y => pirq(8)); - - \r.scaler_RNIRDHF[5]\ : OR2B - port map(A => \scaler[5]\, B => \readdata55\, Y => - scaler_m_5); - - \r.timers_1.value_RNIRL761[14]\ : AOI1B - port map(A => \N_240_0\, B => N_222, C => \reload_m[14]\, Y - => \readdata_1_iv_0[14]\); - - \r.scaler_RNO_1[6]\ : MX2 - port map(A => I_31_5, B => \reload_0[6]\, S => I_44, Y => - N_330); - - \r.timers_1.value_RNO_0[0]\ : MX2B - port map(A => \value_RNI3R3J[0]\, B => \reload_1[0]\, S => - value_1_sn_N_9_i_0_0, Y => N_342); - - \r.timers_1.reload_RNISQBL[30]\ : OR2B - port map(A => \N_240\, B => N_238, Y => \readdata_9[30]\); - - \r.timers_2.value[25]\ : DFN1E0 - port map(D => \value_1_0[25]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[25]\); - - \comb.readdata56\ : OR2A - port map(A => rdata59_4, B => paddr(6), Y => \readdata56\); - - \r.timers_2.irqen_RNO_0\ : MX2 - port map(A => irqen, B => pwdata_1_2, S => load_1_sqmuxa_0, - Y => N_617); - - \r.timers_1.reload[1]\ : DFN1E1 - port map(D => pwdata_1_0, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_1[1]\); - - \r.timers_2.load_RNIP9AN3_0\ : NOR3A - port map(A => irq_0_sqmuxa_0, B => load_0, C => - value_1_sqmuxa_0_0, Y => value_2_sqmuxa_0_0); - - \r.timers_1.reload[14]\ : DFN1E1 - port map(D => pwdata_0(14), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[14]\); - - \r.timers_2.reload[18]\ : DFN1 - port map(D => \reload_RNO[18]\, CLK => lclk_c, Q => - \reload_0[18]\); - - \r.timers_1.reload[4]\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[4]\); - - \r.reload_RNI70OI[2]\ : OR2A - port map(A => \reload_0[2]\, B => \readdata56\, Y => - reload_m_0_2); - - \r.timers_1.value_RNIL36J[9]\ : MX2 - port map(A => \value[9]\, B => \un1_timer0[17]\, S => - \tsel_0[0]\, Y => \value_RNIL36J[9]\); - - \r.timers_2.reload_RNO_0[31]\ : MX2 - port map(A => \reload[31]\, B => pwdata_25, S => - reload_1_sqmuxa_1, Y => N_584); - - \r.timers_1.value_RNO_0[30]\ : MX2C - port map(A => I_217, B => \reload_0[30]\, S => - value_1_sn_N_9_i, Y => N_372); - - \r.tsel[0]\ : DFN1 - port map(D => \tsel_RNIG6TH[0]\, CLK => lclk_c, Q => - \tsel[0]\); - - \r.timers_2.reload_RNO[17]\ : NOR2B - port map(A => rstn, B => N_570, Y => \reload_RNO[17]\); - - \r.timers_1.value[2]\ : DFN1E0 - port map(D => \value_1[2]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[10]\); - - \r.timers_2.irqen_RNO\ : OR2A - port map(A => rstn, B => N_617, Y => irqen_RNO_0); - - \r.timers_2.reload[16]\ : DFN1 - port map(D => \reload_RNO[16]\, CLK => lclk_c, Q => - \reload[16]\); - - \r.timers_2.reload_RNO_0[18]\ : MX2 - port map(A => \reload_0[18]\, B => pwdata_12, S => - reload_1_sqmuxa_1, Y => N_571); - - \r.timers_1.value[15]\ : DFN1E0 - port map(D => \value_1_0[15]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[23]\); - - \r.timers_2.irq_RNIF1IB\ : OR2B - port map(A => \un1_timer0[5]\, B => irqen, Y => pirq(9)); - - \r.timers_1.irqen_RNIVVE11\ : MX2C - port map(A => N_203, B => N_211, S => \N_240\, Y => - \readdata_9[3]\); - - \r.timers_2.reload_RNO_0[24]\ : MX2 - port map(A => \reload[24]\, B => pwdata_18, S => - reload_1_sqmuxa_1, Y => N_577); - - \r.reload_RNIACOI[5]\ : OR2A - port map(A => \reload_0[5]\, B => \readdata56\, Y => - reload_m_5); - - \r.timers_1.value_RNO_0[4]\ : MX2C - port map(A => I_20_5, B => \reload_1[4]\, S => - value_1_sn_N_9_i_0_0, Y => N_346); - - \r.timers_2.enable_RNIEAGI\ : OR2A - port map(A => enable_0, B => \readdata_2_sqmuxa\, Y => - enable_m); - - un12_res_I_5 : XNOR2 - port map(A => \value_RNI3R3J[0]\, B => \value_RNI534J[1]\, - Y => I_5_5); - - \r.timers_2.value[24]\ : DFN1E0 - port map(D => \value_1_0[24]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[24]\); - - \r.timers_2.enable_RNO_2\ : OA1C - port map(A => \tsel[1]\, B => irqpen_0_sqmuxa_1_0, C => - load_1_sqmuxa_0, Y => enable_1_sqmuxa_0); - - \r.timers_1.value_RNO_0[15]\ : MX2C - port map(A => I_91_1, B => \reload_0[15]\, S => - value_1_sn_N_9_i, Y => N_357); - - \r.timers_1.value_RNO_0[21]\ : MX2C - port map(A => I_136_1, B => \reload_0[21]\, S => - value_1_sn_N_9_i, Y => N_363); - - un12_res_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_103); - - un12_res_I_166 : XNOR2 - port map(A => N_45, B => \value_RNIVTUG[24]\, Y => I_166_1); - - \r.timers_1.value_RNIVACL[16]\ : OR2B - port map(A => \N_240\, B => N_224, Y => \readdata_9[16]\); - - \r.timers_2.value_RNO_0[25]\ : MX2C - port map(A => I_173_1, B => \reload[25]\, S => - value_1_sn_N_9_i_0, Y => N_434); - - \r.timers_2.value_RNO_0[14]\ : MX2C - port map(A => I_84_1, B => \reload[14]\, S => - value_1_sn_N_9_i_1, Y => N_423); - - \r.timers_2.reload_RNIDJAI[30]\ : OR2A - port map(A => \reload[30]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => \reload_m[30]\); - - \r.timers_2.value_RNO_0[18]\ : MX2C - port map(A => I_115_1, B => \reload_0[18]\, S => - value_1_sn_N_9_i_1, Y => N_427); - - \r.timers_1.value[30]\ : DFN1E0 - port map(D => \value_1[30]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[38]\); - - \r.timers_1.value_RNIHJ5J[7]\ : MX2 - port map(A => \value[7]\, B => \un1_timer0[15]\, S => - \tsel_0[0]\, Y => \value_RNIHJ5J[7]\); - - \r.timers_2.value_RNO[3]\ : MX2A - port map(A => N_412, B => pwdata_0(3), S => - value_1_sqmuxa_0_0, Y => \value_1_0[3]\); - - \r.timers_2.reload[24]\ : DFN1 - port map(D => \reload_RNO[24]\, CLK => lclk_c, Q => - \reload[24]\); - - \r.timers_1.reload[28]\ : DFN1E1 - port map(D => pwdata_22, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[28]\); - - \r.scaler_RNO_1[7]\ : MX2 - port map(A => I_38_3, B => \reload_0[7]\, S => I_44, Y => - N_331); - - \r.timers_2.restart_RNI607KI_0\ : AO1 - port map(A => restart, B => un19_res, C => load_0, Y => - value_1_sn_N_9_i_0); - - \r.timers_2.value_RNO[1]\ : MX2A - port map(A => N_410, B => pwdata_1_0, S => value_1_sqmuxa_1, - Y => \value_1_0[1]\); - - \r.timers_1.load_RNI0B3K3\ : NOR3 - port map(A => irq_0_sqmuxa, B => load, C => - value_1_sqmuxa_0, Y => value_2_sqmuxa_1); - - un12_res_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_111); - - \r.timers_1.value_RNI93QI[11]\ : MX2 - port map(A => \value[11]\, B => \un1_timer0[19]\, S => - \tsel_0[0]\, Y => \value_RNI93QI[11]\); - - \r.timers_2.value_RNIVCCH[12]\ : OR2A - port map(A => \value[12]\, B => \value_0_sqmuxa_0\, Y => - value_m_8); - - \r.timers_1.value[14]\ : DFN1E0 - port map(D => \value_1_0[14]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[22]\); - - \r.reload_RNO_0[4]\ : MX2 - port map(A => \reload[4]\, B => pwdata_0(4), S => - reload_1_sqmuxa_2, Y => N_627); - - un6_scaler_I_19 : OR2 - port map(A => \scaler[3]\, B => \DWACT_FDEC_E_0[0]\, Y => - N_22); - - \r.timers_2.load_RNIMG8U2\ : NOR3C - port map(A => \reload_m[2]\, B => \readdata_iv_0[2]\, C => - \readdata_iv_2[2]\, Y => readdata_iv_3(2)); - - \r.timers_2.value_RNO[27]\ : MX2A - port map(A => N_436, B => pwdata_21, S => value_1_sqmuxa_1, - Y => \value_1_0[27]\); - - \r.timers_2.reload[21]\ : DFN1 - port map(D => \reload_RNO[21]\, CLK => lclk_c, Q => - \reload[21]\); - - \r.timers_2.value_RNO[24]\ : MX2A - port map(A => N_433, B => pwdata_18, S => - value_1_sqmuxa_0_0, Y => \value_1_0[24]\); - - \r.timers_2.value[17]\ : DFN1E0 - port map(D => \value_1_0[17]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[17]\); - - \r.scaler[1]\ : DFN1 - port map(D => \scaler_RNO[1]\, CLK => lclk_c, Q => - \scaler[1]\); - - un12_res_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_66); - - \r.timers_1.reload[29]\ : DFN1E1 - port map(D => pwdata_23, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[29]\); - - \r.timers_2.value_RNI7HCH[27]\ : OR2A - port map(A => \value[27]\, B => value_0_sqmuxa, Y => - value_m_23); - - \r.timers_1.value_RNO_0[12]\ : MX2C - port map(A => I_73_1, B => \reload_0[12]\, S => - value_1_sn_N_9_i, Y => N_354); - - \r.timers_1.value_RNIT5VG[30]\ : MX2 - port map(A => \value[30]\, B => \un1_timer0[38]\, S => - \tsel[0]\, Y => \value_RNIT5VG[30]\); - - un12_res_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_24); - - \r.timers_1.chain_RNITONI\ : OA1A - port map(A => chain, B => \un1_timer0[5]\, C => enable, Y - => un4_i); - - \r.timers_2.value_RNI6HCH[26]\ : OR2A - port map(A => \value[26]\, B => \value_0_sqmuxa_0\, Y => - value_m_22); - - \r.timers_2.value[23]\ : DFN1E0 - port map(D => \value_1_0[23]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[23]\); - - \r.timers_1.value_RNO_0[10]\ : MX2C - port map(A => I_56_2, B => \reload_0[10]\, S => - value_1_sn_N_9_i_0_0, Y => N_352); - - \r.timers_1.value_RNO_0[27]\ : MX2C - port map(A => I_196_1, B => \reload_0[27]\, S => - value_1_sn_N_9_i, Y => N_369); - - \r.timers_1.value_RNIC2KC[19]\ : MX2 - port map(A => \un1_timer0[27]\, B => \reload_0[19]\, S => - paddr_1(2), Y => N_227); - - un12_res_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \r.timers_1.value_RNI5A861[26]\ : AOI1B - port map(A => \N_240_0\, B => N_234, C => \reload_m[26]\, Y - => readdata_1_iv_0_13); - - \r.timers_2.enable_RNO\ : OR2A - port map(A => rstn, B => N_543, Y => enable_RNO_0); - - \r.timers_1.reload[26]\ : DFN1E1 - port map(D => pwdata_20, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[26]\); - - \r.timers_2.value_RNO_0[22]\ : MX2C - port map(A => I_143_1, B => \reload[22]\, S => - value_1_sn_N_9_i_0, Y => N_431); - - \r.timers_2.reload[0]\ : DFN1 - port map(D => \reload_RNO[0]\, CLK => lclk_c, Q => - \reload[0]\); - - un6_scaler_I_5 : XNOR2 - port map(A => \scaler[0]\, B => \scaler[1]\, Y => I_5_6); - - un12_res_I_223 : OR3 - port map(A => \DWACT_FDEC_E[24]\, B => \DWACT_FDEC_E[23]\, - C => \DWACT_FDEC_E[27]\, Y => N_4); - - un12_res_I_143 : XNOR2 - port map(A => N_61, B => \value_RNIRTUG[22]\, Y => I_143_1); - - \r.timers_2.value_RNO_0[20]\ : MX2C - port map(A => I_129_1, B => \reload[20]\, S => - value_1_sn_N_9_i_1, Y => N_429); - - \r.reload_RNO[5]\ : OR2A - port map(A => rstn, B => N_628, Y => \reload_RNO_0[5]\); - - \r.timers_1.reload_RNIQTIC[10]\ : MX2 - port map(A => \un1_timer0[18]\, B => \reload_0[10]\, S => - paddr_1(2), Y => N_218); - - \r.timers_2.reload_RNO[7]\ : OR2A - port map(A => rstn, B => N_560, Y => \reload_RNO[7]\); - - un12_res_I_210 : XNOR2 - port map(A => N_14_0, B => \value_RNI9UUG[29]\, Y => - I_210_1); - - \r.timers_1.value[26]\ : DFN1E0 - port map(D => \value_1[26]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[34]\); - - \r.timers_1.value_RNO[10]\ : MX2A - port map(A => N_352, B => pwdata_0(10), S => - value_1_sqmuxa_0, Y => \value_1[10]\); - - \r.timers_2.value_RNO_0[16]\ : MX2C - port map(A => I_98_1, B => \reload[16]\, S => - value_1_sn_N_9_i_1, Y => N_425); - - \r.timers_1.value_RNO[5]\ : MX2A - port map(A => N_347, B => pwdata_0(5), S => - value_1_sqmuxa_0, Y => \value_1[5]\); - - \r.timers_2.reload[19]\ : DFN1 - port map(D => \reload_RNO[19]\, CLK => lclk_c, Q => - \reload[19]\); - - \r.timers_1.value[13]\ : DFN1E0 - port map(D => \value_1[13]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[21]\); - - un6_scaler_I_8 : OR2 - port map(A => \scaler[1]\, B => \scaler[0]\, Y => N_30); - - \v.reload_1_sqmuxa\ : NOR2 - port map(A => un1_apbi, B => \readdata56\, Y => - reload_1_sqmuxa_2); - - \r.tsel[1]\ : DFN1 - port map(D => \tsel_RNO[1]\, CLK => lclk_c, Q => \tsel[1]\); - - \r.timers_1.value_RNO_0[31]\ : MX2C - port map(A => I_224, B => \reload_0[31]\, S => - value_1_sn_N_9_i, Y => N_373); - - \r.timers_1.value_RNO[11]\ : MX2A - port map(A => N_353, B => pwdata_0(11), S => - value_1_sqmuxa_0, Y => \value_1[11]\); - - \r.timers_2.reload_RNIENAI[31]\ : OR2A - port map(A => \reload[31]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[31]\); - - \r.timers_2.value_RNO_0[2]\ : MX2C - port map(A => I_9_5, B => \reload[2]\, S => - value_1_sn_N_9_i_0, Y => N_411); - - \r.timers_1.value_RNO_0[9]\ : MX2C - port map(A => I_52_2, B => \reload_0[9]\, S => - value_1_sn_N_9_i_0_0, Y => N_351); - - \r.timers_1.value[6]\ : DFN1E0 - port map(D => \value_1[6]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[14]\); - - \r.timers_2.reload_RNO_0[22]\ : MX2 - port map(A => \reload[22]\, B => pwdata_16, S => - reload_1_sqmuxa_1, Y => N_575); - - \r.timers_1.value_RNO[20]\ : MX2A - port map(A => N_362, B => pwdata_14, S => value_1_sqmuxa, Y - => \value_1_0[20]\); - - \r.timers_1.value_RNIV5VG[31]\ : MX2 - port map(A => \value[31]\, B => \un1_timer0[39]\, S => - \tsel[0]\, Y => \value_RNIV5VG[31]\); - - \v.timers_1.load_1_sqmuxa\ : OR2A - port map(A => readdata30, B => \rdata60_1\, Y => - load_1_sqmuxa); - - \r.timers_2.reload[25]\ : DFN1 - port map(D => \reload_RNO[25]\, CLK => lclk_c, Q => - \reload[25]\); - - un12_res_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_81); - - \r.timers_2.value_RNO_0[1]\ : MX2C - port map(A => I_5_5, B => \reload[1]\, S => - value_1_sn_N_9_i_1, Y => N_410); - - \r.timers_2.value[1]\ : DFN1E0 - port map(D => \value_1_0[1]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[1]\); - - \r.timers_2.reload[27]\ : DFN1 - port map(D => \reload_RNO[27]\, CLK => lclk_c, Q => - \reload[27]\); - - \r.timers_1.reload_RNIBMM71[31]\ : AOI1B - port map(A => \N_240_0\, B => N_239, C => \reload_m[31]\, Y - => \readdata_1_iv_0[31]\); - - \r.timers_2.reload_RNO[3]\ : OR2A - port map(A => rstn, B => N_556, Y => \reload_RNO[3]\); - - \r.timers_1.value_RNO[16]\ : MX2A - port map(A => N_358, B => pwdata_10, S => value_1_sqmuxa, Y - => \value_1[16]\); - - \r.timers_1.reload_RNIANMD[1]\ : MX2 - port map(A => \un1_timer0[9]\, B => \reload_1[1]\, S => - paddr(2), Y => N_209); - - \comb.readdata55_3\ : OR2 - port map(A => rdata61_2, B => N_232_0, Y => \readdata55_3\); - - \r.scaler_RNO[7]\ : OR2B - port map(A => rstn, B => \scaler_1[7]\, Y => - \scaler_RNO[7]\); - - \r.timers_2.reload_RNO_0[17]\ : MX2 - port map(A => \reload[17]\, B => pwdata_11, S => - reload_1_sqmuxa_1, Y => N_570); - - \r.timers_2.reload_RNO_0[3]\ : MX2 - port map(A => \reload[3]\, B => pwdata_0(3), S => - reload_1_sqmuxa_0_0, Y => N_556); - - \r.timers_2.restart_RNI607KI\ : AO1 - port map(A => restart, B => un19_res, C => load_0, Y => - value_1_sn_N_9_i_1); - - \r.timers_1.value[1]\ : DFN1E0 - port map(D => \value_1[1]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[9]\); - - \r.timers_1.value_RNO[21]\ : MX2A - port map(A => N_363, B => pwdata_15, S => value_1_sqmuxa, Y - => \value_1[21]\); - - \r.scaler_RNO[2]\ : OR2B - port map(A => rstn, B => \scaler_1[2]\, Y => - \scaler_RNO[2]\); - - \r.timers_2.reload_RNO[12]\ : OR2A - port map(A => rstn, B => N_565, Y => \reload_RNO[12]\); - - \r.timers_2.irq_RNO\ : NOR3B - port map(A => \tsel[1]\, B => rstn, C => - irqpen_0_sqmuxa_1_0, Y => irq_RNO); - - un12_res_I_73 : XNOR2 - port map(A => N_111, B => \value_RNIB3QI[12]\, Y => I_73_1); - - \r.timers_2.reload_RNO_0[11]\ : MX2 - port map(A => \reload[11]\, B => pwdata_0(11), S => - reload_1_sqmuxa_0_0, Y => N_564); - - \r.timers_1.reload[21]\ : DFN1E1 - port map(D => pwdata_15, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[21]\); - - \r.timers_2.reload_RNIJJBI[18]\ : OR2A - port map(A => \reload_0[18]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => \reload_m[18]\); - - \r.timers_2.value_RNIC33P1[30]\ : OR3C - port map(A => \reload_m[30]\, B => \readdata_9[30]\, C => - \value_m[30]\, Y => prdata_16); - - \r.timers_1.value_RNI5UUG[27]\ : MX2 - port map(A => \value[27]\, B => \un1_timer0[35]\, S => - \tsel[0]\, Y => \value_RNI5UUG[27]\); - - \r.timers_2.chain_RNO_0\ : MX2 - port map(A => chain_0, B => pwdata_0(5), S => - load_1_sqmuxa_0, Y => N_619); - - \r.timers_2.value_RNO[0]\ : MX2A - port map(A => N_409, B => pwdata_0(0), S => - value_1_sqmuxa_0_0, Y => \value_1_0[0]\); - - \r.scaler_RNO_0[2]\ : MX2C - port map(A => pwdata_0(2), B => N_326, S => scaler_0_sqmuxa, - Y => \scaler_1[2]\); - - un12_res_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_52); - - \r.scaler[4]\ : DFN1 - port map(D => \scaler_RNO[4]\, CLK => lclk_c, Q => - \scaler[4]\); - - \r.tick\ : DFN1 - port map(D => I_44, CLK => lclk_c, Q => \un1_timer0[7]\); - - \r.timers_1.value_RNO[26]\ : MX2A - port map(A => N_368, B => pwdata_20, S => value_1_sqmuxa_0, - Y => \value_1[26]\); - - \r.timers_1.value[21]\ : DFN1E0 - port map(D => \value_1[21]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[29]\); - - \r.timers_2.reload_RNI3ERG[9]\ : OR2A - port map(A => \reload[9]\, B => \readdata_1_sqmuxa_1\, Y - => reload_m_9); - - un12_res_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \r.reload_RNO_0[6]\ : MX2 - port map(A => \reload_0[6]\, B => pwdata_0(6), S => - reload_1_sqmuxa_2, Y => N_629); - - \r.timers_2.reload_RNIIFBI[17]\ : OR2A - port map(A => \reload[17]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[17]\); - - \r.reload_RNO_0[2]\ : MX2 - port map(A => \reload_0[2]\, B => pwdata_0(2), S => - reload_1_sqmuxa_2, Y => N_625); - - \r.timers_2.reload_RNIRDRG[1]\ : OR2 - port map(A => readdata_1_sqmuxa_1_0_net_1, B => \reload[1]\, - Y => reload_RNIRDRG(1)); - - \r.timers_2.irqpen_RNO_1\ : AO1D - port map(A => irqpen_0_sqmuxa_0, B => irqpen_0_sqmuxa_1_0, - C => irqpen, Y => irqpen_4_0); - - \r.timers_1.value_RNI5EJC[23]\ : MX2 - port map(A => \un1_timer0[31]\, B => \reload_0[23]\, S => - paddr_2(2), Y => N_231); - - \r.timers_2.reload_RNO[21]\ : NOR2B - port map(A => rstn, B => N_574, Y => \reload_RNO[21]\); - - \r.timers_2.load_RNIS3O6J\ : OR3B - port map(A => un34_i, B => un19_res, C => load_0, Y => - irqpen_0_sqmuxa_1_0); - - \r.timers_1.reload[24]\ : DFN1E1 - port map(D => pwdata_18, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[24]\); - - \r.timers_1.load_RNI9HOJI\ : NOR2A - port map(A => un19_res, B => load, Y => irq_2); - - \r.timers_1.reload_RNIB78C[9]\ : MX2 - port map(A => \un1_timer0[17]\, B => \reload_0[9]\, S => - paddr_2(2), Y => N_217); - - \r.timers_2.value[12]\ : DFN1E0 - port map(D => \value_1_0[12]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[12]\); - - \r.timers_2.reload[28]\ : DFN1 - port map(D => \reload_RNO[28]\, CLK => lclk_c, Q => - \reload[28]\); - - \r.timers_2.value[6]\ : DFN1E0 - port map(D => \value_1_0[6]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[6]\); - - \r.timers_2.reload_RNIQDRG[0]\ : OR2A - port map(A => \reload[0]\, B => readdata_1_sqmuxa_1_0_net_1, - Y => reload_m_0_0); - - \r.timers_1.value_RNI8QJC[17]\ : MX2 - port map(A => \un1_timer0[25]\, B => \reload_0[17]\, S => - paddr_1(2), Y => N_225); - - \r.timers_2.value_RNO[22]\ : MX2A - port map(A => N_431, B => pwdata_16, S => - value_1_sqmuxa_0_0, Y => \value_1[22]\); - - \r.timers_2.value[2]\ : DFN1E0 - port map(D => \value_1_0[2]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[2]\); - - un12_res_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \r.timers_2.reload_RNO_0[20]\ : MX2 - port map(A => \reload[20]\, B => pwdata_14, S => - reload_1_sqmuxa_1, Y => N_573); - - \r.timers_2.reload_RNO_0[23]\ : MX2 - port map(A => \reload[23]\, B => pwdata_17, S => - reload_1_sqmuxa_1, Y => N_576); - - \r.timers_2.reload_RNO[30]\ : NOR2B - port map(A => rstn, B => N_583, Y => \reload_RNO[30]\); - - \r.timers_2.irqpen_RNO_2\ : OR2B - port map(A => irqen, B => \tsel[1]\, Y => irqpen_0_sqmuxa_0); - - \r.timers_2.reload[2]\ : DFN1 - port map(D => \reload_RNO[2]\, CLK => lclk_c, Q => - \reload[2]\); - - \r.timers_1.reload[0]\ : DFN1E1 - port map(D => pwdata_0(0), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_1[0]\); - - \r.timers_1.value_RNO_0[11]\ : MX2C - port map(A => I_66_2, B => \reload_0[11]\, S => - value_1_sn_N_9_i_0_0, Y => N_353); - - \r.timers_2.value[28]\ : DFN1E0 - port map(D => \value_1_0[28]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[28]\); - - \r.timers_1.value_RNIT5JC[12]\ : MX2 - port map(A => \un1_timer0[20]\, B => \reload_0[12]\, S => - paddr_0(2), Y => N_220); - - \r.timers_2.reload_RNIG3BI[24]\ : OR2A - port map(A => \reload[24]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[24]\); - - \r.timers_2.reload[26]\ : DFN1 - port map(D => \reload_RNO[26]\, CLK => lclk_c, Q => - \reload[26]\); - - \r.timers_2.irqen_RNI8S323\ : NOR3C - port map(A => \reload_m[3]\, B => \readdata_iv_0[3]\, C => - \readdata_iv_2[3]\, Y => readdata_iv_3(3)); - - \r.timers_1.restart_RNIC90KI_0\ : AO1 - port map(A => restart_0, B => un19_res, C => load, Y => - value_1_sn_N_9_i_0_0); - - \r.timers_2.value_RNI1HCH[21]\ : OR2A - port map(A => \value[21]\, B => value_0_sqmuxa, Y => - value_m_17); - - \r.timers_1.reload_RNIS1JC[11]\ : MX2 - port map(A => \un1_timer0[19]\, B => \reload_0[11]\, S => - paddr_1(2), Y => N_219); - - \comb.un1_apbi\ : OR3C - port map(A => N_769, B => N_773, C => un1_apbi_0_0, Y => - un1_apbi); - - \r.timers_2.value_RNO[28]\ : MX2A - port map(A => N_437, B => pwdata_22, S => value_1_sqmuxa_1, - Y => \value_1_0[28]\); - - \r.timers_2.value_RNO_0[21]\ : MX2C - port map(A => I_136_1, B => \reload[21]\, S => - value_1_sn_N_9_i_1, Y => N_430); - - \r.timers_1.value_RNO_0[3]\ : MX2C - port map(A => I_13_9, B => \reload_1[3]\, S => - value_1_sn_N_9_i_0_0, Y => N_345); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.timers_2.irqpen_RNO_0\ : AO1B - port map(A => load_1_sqmuxa_0, B => pwdata_0(4), C => - irqpen_4_0, Y => irqpen_1_0); - - \r.timers_1.value_RNIAUJC[18]\ : MX2 - port map(A => \un1_timer0[26]\, B => \reload[18]\, S => - paddr_1(2), Y => N_226); - - \r.scaler_RNO_1[5]\ : MX2 - port map(A => I_24_7, B => \reload_0[5]\, S => I_44, Y => - N_329); - - un12_res_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_88); - - \r.timers_2.value_RNI4HCH[24]\ : OR2A - port map(A => \value[24]\, B => value_0_sqmuxa, Y => - value_m_20); - - \r.timers_2.reload_RNO[6]\ : OR2A - port map(A => rstn, B => N_559, Y => \reload_RNO[6]\); - - \r.timers_1.value[7]\ : DFN1E0 - port map(D => \value_1[7]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[15]\); - - \r.timers_1.value_RNO[1]\ : MX2A - port map(A => N_343, B => pwdata_0(1), S => - value_1_sqmuxa_0, Y => \value_1[1]\); - - un12_res_I_217 : XNOR2 - port map(A => N_9_0, B => \value_RNIT5VG[30]\, Y => I_217); - - \r.timers_2.reload_RNO[26]\ : NOR2B - port map(A => rstn, B => N_579, Y => \reload_RNO[26]\); - - \r.timers_1.value_RNO[6]\ : MX2A - port map(A => N_348, B => pwdata_0(6), S => - value_1_sqmuxa_0, Y => \value_1[6]\); - - \r.dishlt_RNO\ : NOR2B - port map(A => rstn, B => N_631, Y => dishlt_RNO); - - \r.timers_2.value_RNO[10]\ : MX2A - port map(A => N_419, B => pwdata_0(10), S => - value_1_sqmuxa_0_0, Y => \value_1_0[10]\); - - un12_res_I_16 : OR3 - port map(A => \value_RNI3R3J[0]\, B => \value_RNI534J[1]\, - C => \value_RNI7B4J[2]\, Y => \DWACT_FDEC_E[0]\); - - \v.timers_2.value_0_sqmuxa\ : OR2A - port map(A => readdata51, B => N_232, Y => value_0_sqmuxa); - - \r.timers_2.reload_RNO_0[5]\ : MX2 - port map(A => \reload[5]\, B => pwdata_0(5), S => - reload_1_sqmuxa_0_0, Y => N_558); - - un6_scaler_I_41 : OR2 - port map(A => \scaler[6]\, B => \scaler[7]\, Y => - \DWACT_FDEC_E[3]\); - - \r.timers_2.reload_RNITDRG[3]\ : OR2A - port map(A => \reload[3]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[3]\); - - \r.timers_2.value_RNO[6]\ : MX2A - port map(A => N_415, B => pwdata_0(6), S => - value_1_sqmuxa_0_0, Y => \value_1_0[6]\); - - \r.timers_1.value[18]\ : DFN1E0 - port map(D => \value_1[18]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[26]\); - - \r.timers_1.enable_RNIE45G\ : NOR2A - port map(A => enable, B => N_198, Y => N_200); - - \r.timers_1.value_RNI1MUG[18]\ : MX2 - port map(A => \value[18]\, B => \un1_timer0[26]\, S => - \tsel[0]\, Y => \value_RNI1MUG[18]\); - - \r.timers_2.reload_RNO[9]\ : OR2A - port map(A => rstn, B => N_562, Y => \reload_RNO[9]\); - - \r.reload[7]\ : DFN1 - port map(D => \reload_RNO_0[7]\, CLK => lclk_c, Q => - \reload_0[7]\); - - \v.timers_2.value_0_sqmuxa_0\ : OR2A - port map(A => readdata51, B => N_232, Y => - \value_0_sqmuxa_0\); - - un12_res_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \value_RNI9J4J[3]\, C - => \value_RNIBR4J[4]\, Y => N_146); - - \r.timers_1.value[31]\ : DFN1E0 - port map(D => \value_1_0[31]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[39]\); - - \r.timers_2.reload_RNICJAI[20]\ : OR2A - port map(A => \reload[20]\, B => \readdata_1_sqmuxa_1\, Y - => reload_m_20); - - \r.timers_2.reload[3]\ : DFN1 - port map(D => \reload_RNO[3]\, CLK => lclk_c, Q => - \reload[3]\); - - \comb.readdata55\ : NOR2 - port map(A => \readdata55_3\, B => paddr(6), Y => - \readdata55\); - - \r.timers_2.value_RNO[11]\ : MX2A - port map(A => N_420, B => pwdata_0(11), S => - value_1_sqmuxa_0_0, Y => \value_1_0[11]\); - - \r.scaler_RNISHHF[6]\ : OR2B - port map(A => \scaler[6]\, B => \readdata55\, Y => - scaler_m_6); - - un12_res_I_136 : XNOR2 - port map(A => N_66, B => \value_RNIPTUG[21]\, Y => I_136_1); - - \r.timers_2.reload_RNIF3BI[14]\ : OR2A - port map(A => \reload[14]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[14]\); - - \r.timers_1.value_RNIG6KC[29]\ : MX2 - port map(A => \un1_timer0[37]\, B => \reload_0[29]\, S => - paddr_1(2), Y => N_237); - - \r.timers_2.reload_RNISDRG[2]\ : OR2A - port map(A => \reload[2]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[2]\); - - readdata_1_sqmuxa_1 : OR2A - port map(A => readdata51, B => N_6455, Y => - \readdata_1_sqmuxa_1\); - - \r.timers_1.value_RNO_0[17]\ : MX2C - port map(A => I_105_1, B => \reload_0[17]\, S => - value_1_sn_N_9_i, Y => N_359); - - readdata_2_sqmuxa : OR2A - port map(A => readdata51, B => \rdata60_1\, Y => - \readdata_2_sqmuxa\); - - un6_scaler_I_27 : OR2 - port map(A => \scaler[3]\, B => \scaler[4]\, Y => - \DWACT_FDEC_E[1]\); - - \r.timers_2.value_RNI845P1[29]\ : OR3C - port map(A => \reload_m[29]\, B => \readdata_9[29]\, C => - \value_m[29]\, Y => prdata_15); - - \r.timers_1.value_RNO_0[29]\ : MX2C - port map(A => I_210_1, B => \reload_0[29]\, S => - value_1_sn_N_9_i, Y => N_371); - - \r.scaler[3]\ : DFN1 - port map(D => \scaler_RNO[3]\, CLK => lclk_c, Q => - \scaler[3]\); - - \r.timers_2.value_RNO_0[8]\ : MX2C - port map(A => I_45_2, B => \reload[8]\, S => - value_1_sn_N_9_i_0, Y => N_417); - - \r.timers_2.reload_RNO[13]\ : OR2A - port map(A => rstn, B => N_566, Y => \reload_RNO[13]\); - - un12_res_I_196 : XNOR2 - port map(A => N_24, B => \value_RNI5UUG[27]\, Y => I_196_1); - - un12_res_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_61); - - \r.timers_1.value_RNI9U861[19]\ : AOI1B - port map(A => \N_240_0\, B => N_227, C => \reload_m[19]\, Y - => \readdata_1_iv_0[19]\); - - \r.timers_1.value_RNI73QI[10]\ : MX2 - port map(A => \value[10]\, B => \un1_timer0[18]\, S => - \tsel_0[0]\, Y => \value_RNI73QI[10]\); - - \r.timers_1.reload_RNI06JC[21]\ : MX2 - port map(A => \un1_timer0[29]\, B => \reload_0[21]\, S => - paddr_1(2), Y => N_229); - - \r.timers_2.value_RNO[16]\ : MX2A - port map(A => N_425, B => pwdata_10, S => value_1_sqmuxa_1, - Y => \value_1_0[16]\); - - \r.timers_2.value_RNO_0[27]\ : MX2C - port map(A => I_196_1, B => \reload[27]\, S => - value_1_sn_N_9_i_1, Y => N_436); - - \comb.1.readdata_9_sn_m3\ : NOR2A - port map(A => readdata30, B => paddr(3), Y => \N_240\); - - \r.timers_2.reload_RNO_0[7]\ : MX2 - port map(A => \reload[7]\, B => pwdata_0(7), S => - reload_1_sqmuxa_0_0, Y => N_560); - - \v.timers_1.load_1_sqmuxa_1\ : NOR2 - port map(A => load_1_sqmuxa, B => un1_apbi, Y => - load_1_sqmuxa_1); - - un12_res_I_202 : OR3 - port map(A => \DWACT_FDEC_E[24]\, B => \DWACT_FDEC_E[23]\, - C => \value_RNI5UUG[27]\, Y => N_19_0); - - \r.timers_1.reload[12]\ : DFN1E1 - port map(D => pwdata_0(12), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[12]\); - - \r.timers_2.reload_RNO_0[29]\ : MX2 - port map(A => \reload[29]\, B => pwdata_23, S => - reload_1_sqmuxa_1, Y => N_582); - - \r.timers_1.value[25]\ : DFN1E0 - port map(D => \value_1[25]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[33]\); - - \r.timers_2.value[19]\ : DFN1E0 - port map(D => \value_1_0[19]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[19]\); - - un6_scaler_I_34 : OR3 - port map(A => \scaler[3]\, B => \scaler[4]\, C => - \scaler[5]\, Y => \DWACT_FDEC_E[2]\); - - \r.timers_1.enable_RNO_1\ : MX2 - port map(A => restart_0, B => pwdata_0(0), S => - load_1_sqmuxa_1, Y => enable_1); - - un12_res_I_101 : OR2 - port map(A => \value_RNIH3QI[15]\, B => \value_RNIJ3QI[16]\, - Y => \DWACT_FDEC_E[11]\); - - \r.timers_2.reload_RNO[8]\ : OR2A - port map(A => rstn, B => N_561, Y => \reload_RNO[8]\); - - \r.timers_2.irq\ : DFN1 - port map(D => irq_RNO, CLK => lclk_c, Q => \un1_timer0[5]\); - - \r.timers_1.value_RNO[13]\ : MX2A - port map(A => N_355, B => pwdata_0(13), S => - value_1_sqmuxa_0, Y => \value_1[13]\); - - \r.timers_1.reload_RNI838C[8]\ : MX2 - port map(A => \un1_timer0[16]\, B => \reload_0[8]\, S => - paddr_1(2), Y => N_216); - - \r.timers_2.reload_RNO_0[15]\ : MX2 - port map(A => \reload[15]\, B => pwdata_0(15), S => - reload_1_sqmuxa_0_0, Y => N_568); - - \r.timers_2.reload_RNO[10]\ : OR2A - port map(A => rstn, B => N_563, Y => \reload_RNO[10]\); - - \r.scaler[5]\ : DFN1 - port map(D => \scaler_RNO[5]\, CLK => lclk_c, Q => - \scaler[5]\); - - \r.timers_2.value_RNO_0[15]\ : MX2C - port map(A => I_91_1, B => \reload[15]\, S => - value_1_sn_N_9_i_1, Y => N_424); - - \r.timers_2.value_RNIFQHH[5]\ : OR2A - port map(A => \value[5]\, B => value_0_sqmuxa, Y => - value_m_1); - - \r.timers_2.value_RNO[29]\ : MX2A - port map(A => N_438, B => pwdata_23, S => value_1_sqmuxa_1, - Y => \value_1[29]\); - - \r.scaler_RNITLHF[7]\ : OR2B - port map(A => \scaler[7]\, B => \readdata55\, Y => - scaler_m_7); - - \r.timers_2.value[7]\ : DFN1E0 - port map(D => \value_1_0[7]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[7]\); - - un12_res_I_56 : XNOR2 - port map(A => N_123, B => \value_RNI73QI[10]\, Y => I_56_2); - - \r.timers_2.value[10]\ : DFN1E0 - port map(D => \value_1_0[10]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[10]\); - - \r.timers_1.value_RNO[4]\ : MX2A - port map(A => N_346, B => pwdata_0(4), S => - value_1_sqmuxa_0, Y => \value_1[4]\); - - \r.timers_1.value_RNI3R3J[0]\ : MX2 - port map(A => \value[0]\, B => \un1_timer0[8]\, S => - \tsel_0[0]\, Y => \value_RNI3R3J[0]\); - - \r.reload_RNI5ONI[0]\ : OR2A - port map(A => \reload_0[0]\, B => \readdata56\, Y => - reload_m_0_d0); - - \r.timers_2.reload[8]\ : DFN1 - port map(D => \reload_RNO[8]\, CLK => lclk_c, Q => - \reload[8]\); - - \r.timers_1.value_RNI9UUG[29]\ : MX2 - port map(A => \value[29]\, B => \un1_timer0[37]\, S => - \tsel[0]\, Y => \value_RNI9UUG[29]\); - - \r.timers_1.value_RNO[23]\ : MX2A - port map(A => N_365, B => pwdata_17, S => value_1_sqmuxa, Y - => \value_1[23]\); - - \r.timers_2.reload_RNO[25]\ : NOR2B - port map(A => rstn, B => N_578, Y => \reload_RNO[25]\); - - un12_res_I_189 : OR3 - port map(A => \value_RNIVTUG[24]\, B => \value_RNI1UUG[25]\, - C => \value_RNI3UUG[26]\, Y => \DWACT_FDEC_E[22]\); - - \r.timers_2.reload[29]\ : DFN1 - port map(D => \reload_RNO[29]\, CLK => lclk_c, Q => - \reload[29]\); - - \r.timers_1.enable_RNO_0\ : MX2 - port map(A => enable_1, B => enable, S => enable_1_sqmuxa, - Y => N_544); - - \r.timers_2.reload_RNIEVAI[13]\ : OR2A - port map(A => \reload[13]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[13]\); - - un12_res_I_87 : OR3 - port map(A => \value_RNIB3QI[12]\, B => \value_RNID3QI[13]\, - C => \value_RNIF3QI[14]\, Y => \DWACT_FDEC_E[9]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.timers_1.value[24]\ : DFN1E0 - port map(D => \value_1[24]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[32]\); - - \r.timers_1.reload[2]\ : DFN1E1 - port map(D => pwdata_0(2), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[2]\); - - \comb.2.readdata51\ : NOR2 - port map(A => \readdata51_1\, B => paddr(4), Y => - readdata51); - - \r.timers_1.value_RNID3QI[13]\ : MX2 - port map(A => \value[13]\, B => \un1_timer0[21]\, S => - \tsel_0[0]\, Y => \value_RNID3QI[13]\); - - \r.timers_1.reload_RNI0J7C[4]\ : MX2 - port map(A => \un1_timer0[12]\, B => \reload_1[4]\, S => - paddr_1(2), Y => N_212); - - \r.timers_2.value_RNII6IH[8]\ : OR2A - port map(A => \value[8]\, B => value_0_sqmuxa, Y => - value_m_4); - - \r.timers_2.chain_RNIQIHE\ : OR2A - port map(A => chain_0, B => \readdata_2_sqmuxa\, Y => - chain_m); - - \r.timers_1.value_RNIJR5J[8]\ : MX2 - port map(A => \value[8]\, B => \un1_timer0[16]\, S => - \tsel_0[0]\, Y => \value_RNIJR5J[8]\); - - \r.reload[6]\ : DFN1 - port map(D => \reload_RNO_0[6]\, CLK => lclk_c, Q => - \reload_0[6]\); - - \r.timers_1.load_RNIC53BJ\ : NOR2B - port map(A => irq_0_sqmuxa, B => irq_2, Y => load_RNIC53BJ); - - \r.timers_2.reload_RNIJFBI[27]\ : OR2A - port map(A => \reload[27]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => reload_m_27); - - \r.timers_1.value_RNIE2KC[28]\ : MX2 - port map(A => \un1_timer0[36]\, B => \reload_0[28]\, S => - paddr_1(2), Y => N_236); - - \r.timers_2.reload_RNO_0[8]\ : MX2 - port map(A => \reload[8]\, B => pwdata_0(8), S => - reload_1_sqmuxa_0_0, Y => N_561); - - un12_res_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \v.timers_1.value_1_sqmuxa\ : NOR3A - port map(A => readdata30, B => N_232_0, C => un1_apbi, Y - => value_1_sqmuxa); - - un6_scaler_I_30 : OR3 - port map(A => \DWACT_FDEC_E_0[0]\, B => \DWACT_FDEC_E[1]\, - C => \scaler[5]\, Y => N_14); - - \r.timers_2.reload_RNO[18]\ : NOR2B - port map(A => rstn, B => N_571, Y => \reload_RNO[18]\); - - \r.timers_1.load\ : DFN1 - port map(D => load_RNO, CLK => lclk_c, Q => load); - - \r.timers_1.value_RNI4JCL[18]\ : OR2B - port map(A => \N_240\, B => N_226, Y => \readdata_9[18]\); - - \r.timers_2.value_RNO_0[12]\ : MX2C - port map(A => I_73_1, B => \reload[12]\, S => - value_1_sn_N_9_i_1, Y => N_421); - - \r.timers_2.reload_RNO_0[26]\ : MX2 - port map(A => \reload[26]\, B => pwdata_20, S => - reload_1_sqmuxa_1, Y => N_579); - - \r.scaler_RNIP5HF[3]\ : OR2B - port map(A => \scaler[3]\, B => \readdata55\, Y => - \scaler_m[3]\); - - \r.timers_2.value_RNI3HCH[23]\ : OR2A - port map(A => \value[23]\, B => value_0_sqmuxa, Y => - \value_m[23]\); - - \r.timers_2.value[8]\ : DFN1E0 - port map(D => \value_1_0[8]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[8]\); - - \r.timers_2.value[30]\ : DFN1E0 - port map(D => \value_1_0[30]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[30]\); - - \r.timers_2.value_RNO_0[10]\ : MX2C - port map(A => I_56_2, B => \reload[10]\, S => - value_1_sn_N_9_i_0, Y => N_419); - - un12_res_I_12 : OR3 - port map(A => \value_RNI3R3J[0]\, B => \value_RNI534J[1]\, - C => \value_RNI7B4J[2]\, Y => N_154); - - \r.reload[0]\ : DFN1 - port map(D => \reload_RNO_0[0]\, CLK => lclk_c, Q => - \reload_0[0]\); - - \comb.1.readdata26\ : OR2A - port map(A => paddr(3), B => paddr(2), Y => \rdata60_1\); - - \r.reload_RNO_0[1]\ : MX2 - port map(A => \reload_0[1]\, B => pwdata_0(1), S => - reload_1_sqmuxa_2, Y => N_624); - - un12_res_I_156 : XNOR2 - port map(A => N_52, B => \value_RNITTUG[23]\, Y => I_156_1); - - \r.reload_RNO_0[7]\ : MX2 - port map(A => \reload_0[7]\, B => pwdata_0(7), S => - reload_1_sqmuxa_2, Y => N_630); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.timers_2.value_RNI3LCH[30]\ : OR2A - port map(A => \value[30]\, B => \value_0_sqmuxa_0\, Y => - \value_m[30]\); - - \r.timers_2.reload_RNO[19]\ : NOR2B - port map(A => rstn, B => N_572, Y => \reload_RNO[19]\); - - \r.timers_2.reload_RNIG7BI[15]\ : OR2A - port map(A => \reload[15]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[15]\); - - \comb.1.readdata30\ : NOR3A - port map(A => paddr(4), B => paddr(6), C => paddr(5), Y => - readdata30); - - \r.timers_1.reload[3]\ : DFN1E1 - port map(D => pwdata_1_2, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[3]\); - - \r.scaler_RNO_0[6]\ : MX2C - port map(A => pwdata_0(6), B => N_330, S => scaler_0_sqmuxa, - Y => \scaler_1[6]\); - - \r.scaler_RNO[3]\ : OR2B - port map(A => rstn, B => \scaler_1[3]\, Y => - \scaler_RNO[3]\); - - \r.timers_2.value_RNIUCCH[11]\ : OR2A - port map(A => \value[11]\, B => value_0_sqmuxa, Y => - value_m_7); - - \r.timers_2.reload_RNO[24]\ : NOR2B - port map(A => rstn, B => N_577, Y => \reload_RNO[24]\); - - \v.timers_2.load_1_sqmuxa\ : NOR2 - port map(A => \readdata_2_sqmuxa\, B => un1_apbi, Y => - load_1_sqmuxa_0); - - \r.timers_1.value_RNO[8]\ : MX2A - port map(A => N_350, B => pwdata_0(8), S => - value_1_sqmuxa_0, Y => \value_1[8]\); - - \r.timers_2.value_RNIO34P1[25]\ : OR3C - port map(A => \reload_m[25]\, B => \readdata_9[25]\, C => - \value_m[25]\, Y => prdata_11); - - un12_res_I_45 : XNOR2 - port map(A => N_131, B => \value_RNIJR5J[8]\, Y => I_45_2); - - \r.timers_2.reload_RNIIBBI[26]\ : OR2A - port map(A => \reload[26]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => \reload_m[26]\); - - \r.timers_1.value_RNIARCL[29]\ : OR2B - port map(A => \N_240\, B => N_237, Y => \readdata_9[29]\); - - \r.timers_2.reload_RNO_0[14]\ : MX2 - port map(A => \reload[14]\, B => pwdata_0(14), S => - reload_1_sqmuxa_1, Y => N_567); - - \r.scaler_RNO[6]\ : OR2B - port map(A => rstn, B => \scaler_1[6]\, Y => - \scaler_RNO[6]\); - - \r.timers_2.value[27]\ : DFN1E0 - port map(D => \value_1_0[27]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[27]\); - - \r.timers_1.reload_RNIEI2E[20]\ : MX2 - port map(A => \un1_timer0[28]\, B => \reload_0[20]\, S => - paddr(2), Y => N_228); - - \r.timers_2.reload[5]\ : DFN1 - port map(D => \reload_RNO[5]\, CLK => lclk_c, Q => - \reload[5]\); - - \r.timers_2.value_RNO[2]\ : MX2A - port map(A => N_411, B => pwdata_0(2), S => - value_1_sqmuxa_0_0, Y => \value_1_0[2]\); - - un12_res_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \r.timers_1.value_RNO_0[8]\ : MX2C - port map(A => I_45_2, B => \reload_0[8]\, S => - value_1_sn_N_9_i_0_0, Y => N_350); - - \r.reload[4]\ : DFN1 - port map(D => \reload_RNO_0[4]\, CLK => lclk_c, Q => - \reload[4]\); - - \r.timers_1.value[23]\ : DFN1E0 - port map(D => \value_1[23]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[31]\); - - \r.timers_1.reload[15]\ : DFN1E1 - port map(D => pwdata_0(15), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[15]\); - - \r.tsel_0_0[0]\ : DFN1 - port map(D => \tsel_RNIG6TH[0]\, CLK => lclk_c, Q => - \tsel_0[0]\); - - \r.timers_1.reload[30]\ : DFN1E1 - port map(D => pwdata_24, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[30]\); - - \r.timers_2.restart_RNO_0\ : MX2 - port map(A => restart, B => pwdata_1_0, S => - load_1_sqmuxa_0, Y => N_618); - - \r.timers_2.reload_RNO[0]\ : OR2A - port map(A => rstn, B => N_553, Y => \reload_RNO[0]\); - - \r.timers_1.value_RNO[15]\ : MX2A - port map(A => N_357, B => pwdata_0(15), S => value_1_sqmuxa, - Y => \value_1_0[15]\); - - \v.timers_1.reload_1_sqmuxa\ : NOR3A - port map(A => readdata30, B => N_6455_0, C => un1_apbi, Y - => reload_1_sqmuxa); - - \r.timers_1.value_RNIJ3QI[16]\ : MX2 - port map(A => \value[16]\, B => \un1_timer0[24]\, S => - \tsel_0[0]\, Y => \value_RNIJ3QI[16]\); - - un12_res_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \value_RNIFB5J[6]\, Y => N_136); - - \r.scaler_RNO_0[4]\ : MX2C - port map(A => pwdata_0(4), B => N_328, S => scaler_0_sqmuxa, - Y => \scaler_1[4]\); - - \r.timers_2.value_RNO_0[7]\ : MX2C - port map(A => I_38_2, B => \reload[7]\, S => - value_1_sn_N_9_i_0, Y => N_416); - - un6_scaler_I_38 : XNOR2 - port map(A => N_9, B => \scaler[7]\, Y => I_38_3); - - \r.timers_2.reload_RNO_0[30]\ : MX2 - port map(A => \reload[30]\, B => pwdata_24, S => - reload_1_sqmuxa_1, Y => N_583); - - \r.dishlt\ : DFN1 - port map(D => dishlt_RNO, CLK => lclk_c, Q => \dishlt\); - - un12_res_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \value_RNIH3QI[15]\, Y => N_93); - - \r.timers_2.reload[30]\ : DFN1 - port map(D => \reload_RNO[30]\, CLK => lclk_c, Q => - \reload[30]\); - - \r.timers_2.irqen_RNI5M5G1\ : OA1A - port map(A => irqen, B => \readdata_2_sqmuxa\, C => - \readdata_9[3]\, Y => \readdata_iv_0[3]\); - - un12_res_I_149 : OR3 - port map(A => \value_RNI3R3J[0]\, B => \value_RNI534J[1]\, - C => \value_RNI7B4J[2]\, Y => \DWACT_FDEC_E[34]\); - - un12_res_I_115 : XNOR2 - port map(A => N_81, B => \value_RNI1MUG[18]\, Y => I_115_1); - - \r.timers_1.value[17]\ : DFN1E0 - port map(D => \value_1[17]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[25]\); - - \r.scaler_RNINTGF[1]\ : OR2A - port map(A => \readdata55\, B => \scaler[1]\, Y => - scaler_i_m(1)); - - \r.timers_2.value_RNO[13]\ : MX2A - port map(A => N_422, B => pwdata_0(13), S => - value_1_sqmuxa_0_0, Y => \value_1_0[13]\); - - \r.timers_2.reload_RNO_0[2]\ : MX2 - port map(A => \reload[2]\, B => pwdata_0(2), S => - reload_1_sqmuxa_0_0, Y => N_555); - - \r.timers_1.value_RNO[25]\ : MX2A - port map(A => N_367, B => pwdata_19, S => value_1_sqmuxa_0, - Y => \value_1[25]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ssram_plugin is - - port( state_RNIFS55 : out std_logic_vector(4 to 4); - ramsn_c : in std_logic_vector(0 to 0); - rwen_c : in std_logic_vector(3 downto 0); - address_c : in std_logic_vector(27 downto 20); - address : in std_logic_vector(31 downto 28); - state_i : out std_logic_vector(3 to 3); - ssram_plugin_GND : in std_logic; - clk_c : in std_logic; - writen_c : in std_logic; - nBWE_c : out std_logic; - nBWd_c : out std_logic; - nBWc_c : out std_logic; - nBWb_c : out std_logic; - nBWa_c : out std_logic; - nCE1_c : out std_logic; - nCE3_c : out std_logic; - CE2_c : out std_logic - ); - -end ssram_plugin; - -architecture DEF_ARCH of ssram_plugin is - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1P1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state[3]_net_1\, nCE1int_2, \nCE3int_0\, \CE2int_0\, - \state_ns[1]\, \state[2]_net_1\, \state[1]_net_1\, - \state[4]_net_1\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - nBWbint : OR2 - port map(A => rwen_c(2), B => ramsn_c(0), Y => nBWb_c); - - \state_RNIE94H[3]\ : NOR3B - port map(A => \state[3]_net_1\, B => address(30), C => - address(28), Y => nCE1int_2); - - nCE3int_0 : OR2 - port map(A => address_c(20), B => address_c(21), Y => - \nCE3int_0\); - - \state[1]\ : DFN1C1 - port map(D => \state[2]_net_1\, CLK => clk_c, CLR => - ramsn_c(0), Q => \state[1]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \state[4]\ : DFN1P1 - port map(D => ssram_plugin_GND, CLK => clk_c, PRE => - ramsn_c(0), Q => \state[4]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \state_RNINMLV[3]\ : OR3A - port map(A => nCE1int_2, B => address(31), C => address(29), - Y => nCE1_c); - - nCE3int : OR3 - port map(A => address_c(23), B => address_c(22), C => - \nCE3int_0\, Y => nCE3_c); - - nBWdint : OR2 - port map(A => rwen_c(0), B => ramsn_c(0), Y => nBWd_c); - - CE2int : NOR3 - port map(A => address_c(27), B => address_c(26), C => - \CE2int_0\, Y => CE2_c); - - \state[2]\ : DFN1C1 - port map(D => \state[3]_net_1\, CLK => clk_c, CLR => - ramsn_c(0), Q => \state[2]_net_1\); - - nBWaint : OR2 - port map(A => rwen_c(3), B => ramsn_c(0), Y => nBWa_c); - - CE2int_0 : OR2 - port map(A => address_c(24), B => address_c(25), Y => - \CE2int_0\); - - \state_RNIFS55[4]\ : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => state_RNIFS55(4)); - - GND_i : GND - port map(Y => \GND\); - - nBWEint : OR2 - port map(A => writen_c, B => ramsn_c(0), Y => nBWE_c); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO[3]\ : NOR3 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, C - => \state[3]_net_1\, Y => \state_ns[1]\); - - nBWcint : OR2 - port map(A => rwen_c(1), B => ramsn_c(0), Y => nBWc_c); - - \state_RNI7SI2[3]\ : INV - port map(A => \state[3]_net_1\, Y => state_i(3)); - - \state[3]\ : DFN1C1 - port map(D => \state_ns[1]\, CLK => clk_c, CLR => - ramsn_c(0), Q => \state[3]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_work_leon3mp_wfp_rtl_1 is - - port( clk : in std_logic; - address : in std_logic_vector(9 downto 0); - datain : in std_logic_vector(31 downto 0); - dataout : out std_logic_vector(31 downto 0); - enable : in std_logic; - write : in std_logic - ); - -end proasic3_syncram_work_leon3mp_wfp_rtl_1; - -architecture DEF_ARCH of proasic3_syncram_work_leon3mp_wfp_rtl_1 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ1_1 is - - port( dstate_RNI1G47MJ : in std_logic_vector(1 to 1); - dataout_0 : out std_logic_vector(31 downto 28); - dataout : out std_logic_vector(27 downto 0); - xaddress_RNIJI2O22 : in std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : in std_logic_vector(1 to 1); - xaddress_RNIK99NK1 : in std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : in std_logic_vector(0 to 0); - xaddress_RNILK99L1 : in std_logic_vector(1 to 1); - xaddress_RNILHOK61 : in std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : in std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : in std_logic_vector(1 to 1); - dstate_RNIFS6E51 : in std_logic_vector(1 to 1); - dstate_RNIFPT581 : in std_logic_vector(1 to 1); - dstate_RNIC3QA81 : in std_logic_vector(1 to 1); - faddr_RNI7MK691 : in std_logic_vector(6 to 6); - xaddress_RNID252J1 : in std_logic_vector(10 to 10); - faddr_RNIB0UOO : in std_logic_vector(2 to 2); - faddr_RNIEHR0O : in std_logic_vector(1 to 1); - faddr_RNI7879K : in std_logic_vector(0 to 0); - xaddress_RNITFTTE : in std_logic_vector(3 to 3); - xaddress_RNIFP43F : in std_logic_vector(2 to 2); - syncramZ1_1_VCC : in std_logic; - read_RNIEEGDD1 : in std_logic; - read_RNI75LJ31 : in std_logic; - read_RNIC9O9B1 : in std_logic; - read_RNIC70OF1 : in std_logic; - read_RNICKHE91 : in std_logic; - read_RNISLPNU : in std_logic; - read_RNIQMJI41 : in std_logic; - read_RNICAQK41 : in std_logic; - read_RNIQH64D1 : in std_logic; - read_RNIL633F1 : in std_logic; - read_RNIMJHQT : in std_logic; - read_RNIEKS231 : in std_logic; - read_RNI7G7G41 : in std_logic; - read_RNI76N8R : in std_logic; - read_RNIAQJ831 : in std_logic; - read_RNI8DFM31 : in std_logic; - read_RNIQPCQ11 : in std_logic; - read_RNIFPFT31 : in std_logic; - read_RNIQFOD21 : in std_logic; - read_RNIRO4K31 : in std_logic; - read_RNI0IQ7R : in std_logic; - N_26 : in std_logic; - N_24 : in std_logic; - N_10 : in std_logic; - lclk_c : in std_logic - ); - -end syncramZ1_1; - -architecture DEF_ARCH of syncramZ1_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_1 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(9 downto 0) := (others => 'U'); - datain : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout : out std_logic_vector(31 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_1 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_1(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_1 - port map(clk => lclk_c, address(9) => faddr_RNI7MK691(6), - address(8) => xaddress_RNID252J1(10), address(7) => N_26, - address(6) => N_24, address(5) => faddr_RNIB0UOO(2), - address(4) => faddr_RNIEHR0O(1), address(3) => - faddr_RNI7879K(0), address(2) => N_10, address(1) => - xaddress_RNITFTTE(3), address(0) => xaddress_RNIFP43F(2), - datain(31) => xaddress_RNIJI2O22(1), datain(30) => - xaddress_RNIP2BVK1(1), datain(29) => - xaddress_RNIK99NK1(1), datain(28) => - xaddress_RNI1I3MQ1(0), datain(27) => - xaddress_RNILK99L1(1), datain(26) => - xaddress_RNILHOK61(1), datain(25) => - xaddress_RNIEHIUT1(1), datain(24) => - xaddress_RNI1Q9ST1(1), datain(23) => read_RNIEEGDD1, - datain(22) => read_RNI75LJ31, datain(21) => - read_RNIC9O9B1, datain(20) => read_RNIC70OF1, datain(19) - => read_RNICKHE91, datain(18) => read_RNISLPNU, - datain(17) => read_RNIQMJI41, datain(16) => - read_RNICAQK41, datain(15) => read_RNIQH64D1, datain(14) - => read_RNIL633F1, datain(13) => read_RNIMJHQT, - datain(12) => read_RNIEKS231, datain(11) => - read_RNI7G7G41, datain(10) => read_RNI76N8R, datain(9) - => read_RNIAQJ831, datain(8) => read_RNI8DFM31, - datain(7) => read_RNIQPCQ11, datain(6) => - dstate_RNIFS6E51(1), datain(5) => read_RNIFPFT31, - datain(4) => read_RNIQFOD21, datain(3) => read_RNIRO4K31, - datain(2) => read_RNI0IQ7R, datain(1) => - dstate_RNIFPT581(1), datain(0) => dstate_RNIC3QA81(1), - dataout(31) => dataout_0(31), dataout(30) => - dataout_0(30), dataout(29) => dataout_0(29), dataout(28) - => dataout_0(28), dataout(27) => dataout(27), - dataout(26) => dataout(26), dataout(25) => dataout(25), - dataout(24) => dataout(24), dataout(23) => dataout(23), - dataout(22) => dataout(22), dataout(21) => dataout(21), - dataout(20) => dataout(20), dataout(19) => dataout(19), - dataout(18) => dataout(18), dataout(17) => dataout(17), - dataout(16) => dataout(16), dataout(15) => dataout(15), - dataout(14) => dataout(14), dataout(13) => dataout(13), - dataout(12) => dataout(12), dataout(11) => dataout(11), - dataout(10) => dataout(10), dataout(9) => dataout(9), - dataout(8) => dataout(8), dataout(7) => dataout(7), - dataout(6) => dataout(6), dataout(5) => dataout(5), - dataout(4) => dataout(4), dataout(3) => dataout(3), - dataout(2) => dataout(2), dataout(1) => dataout(1), - dataout(0) => dataout(0), enable => syncramZ1_1_VCC, - write => dstate_RNI1G47MJ(1)); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_work_leon3mp_wfp_rtl_2 is - - port( clk : in std_logic; - address : in std_logic_vector(6 downto 0); - datain : in std_logic_vector(35 downto 0); - dataout : out std_logic_vector(35 downto 0); - enable : in std_logic; - write : in std_logic - ); - -end proasic3_syncram_work_leon3mp_wfp_rtl_2; - -architecture DEF_ARCH of proasic3_syncram_work_leon3mp_wfp_rtl_2 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ2_1 is - - port( dataout : out std_logic_vector(35 downto 28); - dataout_0 : out std_logic_vector(27 downto 0); - ctx : in std_logic_vector(7 downto 0); - vdtdatain_0_1_5 : in std_logic; - xaddress_RNI9MB27S2 : in std_logic_vector(23 to 23); - xaddress_RNIC5A27S2 : in std_logic_vector(21 to 21); - xaddress_RNI1D927S2 : in std_logic_vector(20 to 20); - xaddress_RNI0GI17S2 : in std_logic_vector(17 to 17); - xaddress_RNIID927S2 : in std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : in std_logic_vector(15 to 15); - xaddress_RNIN7J17S2 : in std_logic_vector(14 to 14); - xaddress_RNICFI17S2 : in std_logic_vector(13 to 13); - xaddress_RNITMH17S2 : in std_logic_vector(12 to 12); - dstate_i_RNI29QQ7J3 : in std_logic_vector(8 to 8); - dstate_i_0_RNIH0PPES : in std_logic_vector(8 to 8); - dstate_i_0_RNIL7FGFS : in std_logic_vector(8 to 8); - faddr_RNI7MK691 : in std_logic_vector(6 to 6); - xaddress_RNID252J1 : in std_logic_vector(10 to 10); - faddr_RNIB0UOO : in std_logic_vector(2 to 2); - faddr_RNIEHR0O : in std_logic_vector(1 to 1); - faddr_RNI7879K : in std_logic_vector(0 to 0); - newtag_1_0 : in std_logic_vector(27 downto 24); - dci_m_3 : in std_logic; - dci_m_2 : in std_logic; - dci_m_1 : in std_logic; - dci_m_0 : in std_logic; - dci_m_6 : in std_logic; - maddress : in std_logic_vector(28 to 28); - addr : in std_logic_vector(30 to 30); - un1_p0_2_0 : in std_logic_vector(498 to 498); - edata2_iv_i_0 : in std_logic_vector(31 to 31); - flush_RNIGBB873 : in std_logic; - syncramZ2_1_VCC : in std_logic; - flush_0_1_RNIPTA27S2 : in std_logic; - flush_0_1_RNIOMB27S2 : in std_logic; - flush_0_1_RNIBUA27S2 : in std_logic; - N_3239_i_0 : in std_logic; - N_16_i_0 : in std_logic; - flush_RNIGUM2OH3 : in std_logic; - flush_RNIJEN4SI3 : in std_logic; - N_12_i_0 : in std_logic; - N_26 : in std_logic; - N_24 : in std_logic; - lclk_c : in std_logic; - N_269 : in std_logic; - N_270 : in std_logic; - N_3846 : in std_logic; - N_144 : in std_logic; - N_329 : in std_logic; - N_267 : in std_logic; - N_330 : in std_logic; - N_3254_0 : in std_logic - ); - -end syncramZ2_1; - -architecture DEF_ARCH of syncramZ2_1 is - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_2 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(6 downto 0) := (others => 'U'); - datain : in std_logic_vector(35 downto 0) := (others => 'U'); - dataout : out std_logic_vector(35 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - signal \vdtdatain_0_1_1[27]\, \vdtdatain_0_1_0[26]\, - \vdtdatain_0_1_0[24]\, \vdtdatain_0_1[24]\, - \vdtdatain_0_1[26]\, \vdtdatain_0_1[27]\, - \vdtdatain_0_1[20]\, \vdtdatain_0_1[21]\, - \vdtdatain_0_1[22]\, \vdtdatain_0_1[23]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_2 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_2(DEF_ARCH); -begin - - - \proa3.x0_RNO_8\ : OA1C - port map(A => edata2_iv_i_0(31), B => N_3254_0, C => - un1_p0_2_0(498), Y => \vdtdatain_0_1_1[27]\); - - \proa3.x0_RNO_5\ : OR3C - port map(A => N_270, B => N_269, C => \vdtdatain_0_1_1[27]\, - Y => \vdtdatain_0_1[27]\); - - \proa3.x0_RNO_4\ : OR3B - port map(A => dci_m_6, B => \vdtdatain_0_1_0[26]\, C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[26]\); - - \proa3.x0_RNO_2\ : OA1B - port map(A => dci_m_3, B => newtag_1_0(27), C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[23]\); - - \proa3.x0_RNO\ : OA1B - port map(A => dci_m_0, B => newtag_1_0(24), C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[20]\); - - \proa3.x0_RNO_1\ : OA1B - port map(A => dci_m_2, B => newtag_1_0(26), C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[22]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO_7\ : AOI1B - port map(A => addr(30), B => N_330, C => N_267, Y => - \vdtdatain_0_1_0[26]\); - - \proa3.x0_RNO_3\ : OR3B - port map(A => N_3846, B => \vdtdatain_0_1_0[24]\, C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[24]\); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \proa3.x0_RNO_6\ : AOI1B - port map(A => maddress(28), B => N_329, C => N_144, Y => - \vdtdatain_0_1_0[24]\); - - \proa3.x0_RNO_0\ : OA1B - port map(A => dci_m_1, B => newtag_1_0(25), C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[21]\); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_2 - port map(clk => lclk_c, address(6) => faddr_RNI7MK691(6), - address(5) => xaddress_RNID252J1(10), address(4) => N_26, - address(3) => N_24, address(2) => faddr_RNIB0UOO(2), - address(1) => faddr_RNIEHR0O(1), address(0) => - faddr_RNI7879K(0), datain(35) => ctx(7), datain(34) => - ctx(6), datain(33) => ctx(5), datain(32) => ctx(4), - datain(31) => ctx(3), datain(30) => ctx(2), datain(29) - => ctx(1), datain(28) => ctx(0), datain(27) => - \vdtdatain_0_1[27]\, datain(26) => \vdtdatain_0_1[26]\, - datain(25) => vdtdatain_0_1_5, datain(24) => - \vdtdatain_0_1[24]\, datain(23) => \vdtdatain_0_1[23]\, - datain(22) => \vdtdatain_0_1[22]\, datain(21) => - \vdtdatain_0_1[21]\, datain(20) => \vdtdatain_0_1[20]\, - datain(19) => xaddress_RNI9MB27S2(23), datain(18) => - flush_0_1_RNIPTA27S2, datain(17) => - xaddress_RNIC5A27S2(21), datain(16) => - xaddress_RNI1D927S2(20), datain(15) => - flush_0_1_RNIOMB27S2, datain(14) => flush_0_1_RNIBUA27S2, - datain(13) => xaddress_RNI0GI17S2(17), datain(12) => - xaddress_RNIID927S2(16), datain(11) => - xaddress_RNI2MB27S2(15), datain(10) => - xaddress_RNIN7J17S2(14), datain(9) => - xaddress_RNICFI17S2(13), datain(8) => - xaddress_RNITMH17S2(12), datain(7) => N_3239_i_0, - datain(6) => dstate_i_RNI29QQ7J3(8), datain(5) => - N_16_i_0, datain(4) => flush_RNIGUM2OH3, datain(3) => - dstate_i_0_RNIH0PPES(8), datain(2) => flush_RNIJEN4SI3, - datain(1) => N_12_i_0, datain(0) => - dstate_i_0_RNIL7FGFS(8), dataout(35) => dataout(35), - dataout(34) => dataout(34), dataout(33) => dataout(33), - dataout(32) => dataout(32), dataout(31) => dataout(31), - dataout(30) => dataout(30), dataout(29) => dataout(29), - dataout(28) => dataout(28), dataout(27) => dataout_0(27), - dataout(26) => dataout_0(26), dataout(25) => - dataout_0(25), dataout(24) => dataout_0(24), dataout(23) - => dataout_0(23), dataout(22) => dataout_0(22), - dataout(21) => dataout_0(21), dataout(20) => - dataout_0(20), dataout(19) => dataout_0(19), dataout(18) - => dataout_0(18), dataout(17) => dataout_0(17), - dataout(16) => dataout_0(16), dataout(15) => - dataout_0(15), dataout(14) => dataout_0(14), dataout(13) - => dataout_0(13), dataout(12) => dataout_0(12), - dataout(11) => dataout_0(11), dataout(10) => - dataout_0(10), dataout(9) => dataout_0(9), dataout(8) => - dataout_0(8), dataout(7) => dataout_0(7), dataout(6) => - dataout_0(6), dataout(5) => dataout_0(5), dataout(4) => - dataout_0(4), dataout(3) => dataout_0(3), dataout(2) => - dataout_0(2), dataout(1) => dataout_0(1), dataout(0) => - dataout_0(0), enable => syncramZ2_1_VCC, write => - flush_RNIGBB873); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ1 is - - port( istate_RNIJCMP6 : in std_logic_vector(0 to 0); - dataout_2 : out std_logic_vector(31 downto 28); - dataout_1 : out std_logic_vector(27 downto 0); - istate_RNIENB3M : in std_logic_vector(0 to 0); - istate_RNIS4VK8 : in std_logic_vector(0 to 0); - istate_RNIRASC8 : in std_logic_vector(0 to 0); - istate_RNIJSOBE : in std_logic_vector(0 to 0); - istate_RNIR2JU8 : in std_logic_vector(0 to 0); - istate_RNIOJJE1 : in std_logic_vector(0 to 0); - istate_RNIAP6PI : in std_logic_vector(0 to 0); - istate_RNIH0NBI : in std_logic_vector(0 to 0); - istate_RNI5V68H : in std_logic_vector(0 to 0); - istate_RNIM2DE7 : in std_logic_vector(0 to 0); - istate_RNIAJH4F : in std_logic_vector(0 to 0); - istate_RNIVTQIJ : in std_logic_vector(0 to 0); - istate_RNI2MM6D : in std_logic_vector(0 to 0); - istate_RNI8BL1A : in std_logic_vector(0 to 0); - istate_RNILTAC8 : in std_logic_vector(0 to 0); - istate_RNIK9NF8 : in std_logic_vector(0 to 0); - istate_RNIA8N5H : in std_logic_vector(0 to 0); - istate_RNIOVC5J : in std_logic_vector(0 to 0); - istate_RNI6PSS1 : in std_logic_vector(0 to 0); - istate_RNIN6957 : in std_logic_vector(0 to 0); - istate_RNIKJBN8 : in std_logic_vector(0 to 0); - istate_RNI6LOO6 : in std_logic_vector(0 to 0); - istate_RNIGUTA8 : in std_logic_vector(0 to 0); - istate_RNIMRTH8 : in std_logic_vector(0 to 0); - istate_RNIV33V9 : in std_logic_vector(0 to 0); - istate_RNI7BUID : in std_logic_vector(0 to 0); - istate_RNIEC82C : in std_logic_vector(0 to 0); - istate_RNIG7IIA : in std_logic_vector(0 to 0); - istate_RNI57KLB : in std_logic_vector(0 to 0); - istate_RNI6HPAI : in std_logic_vector(0 to 0); - istate_RNIPSU8G : in std_logic_vector(0 to 0); - istate_RNIUCOFG : in std_logic_vector(0 to 0); - faddr_RNIDN2CUE : in std_logic_vector(6 to 6); - faddr_RNI7UFASD : in std_logic_vector(5 to 5); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4); - faddr_RNIUT72LB : in std_logic_vector(3 to 3); - faddr_RNISJSHQA : in std_logic_vector(2 to 2); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0); - vaddress_RNIJG6QR7 : in std_logic_vector(4 to 4); - vaddress_RNIFCB8U6 : in std_logic_vector(3 to 3); - vaddress_RNI8EVQ36 : in std_logic_vector(2 to 2); - syncramZ1_VCC : in std_logic; - lclk_c : in std_logic - ); - -end syncramZ1; - -architecture DEF_ARCH of syncramZ1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_1 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(9 downto 0) := (others => 'U'); - datain : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout : out std_logic_vector(31 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_1 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_1(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_1 - port map(clk => lclk_c, address(9) => faddr_RNIDN2CUE(6), - address(8) => faddr_RNI7UFASD(5), address(7) => - faddr_RNI0FOJNE(4), address(6) => faddr_RNIUT72LB(3), - address(5) => faddr_RNISJSHQA(2), address(4) => - faddr_RNIKVTLT9(1), address(3) => faddr_RNI7H6KT8(0), - address(2) => vaddress_RNIJG6QR7(4), address(1) => - vaddress_RNIFCB8U6(3), address(0) => - vaddress_RNI8EVQ36(2), datain(31) => istate_RNIENB3M(0), - datain(30) => istate_RNIS4VK8(0), datain(29) => - istate_RNIRASC8(0), datain(28) => istate_RNIJSOBE(0), - datain(27) => istate_RNIR2JU8(0), datain(26) => - istate_RNIOJJE1(0), datain(25) => istate_RNIAP6PI(0), - datain(24) => istate_RNIH0NBI(0), datain(23) => - istate_RNI5V68H(0), datain(22) => istate_RNIM2DE7(0), - datain(21) => istate_RNIAJH4F(0), datain(20) => - istate_RNIVTQIJ(0), datain(19) => istate_RNI2MM6D(0), - datain(18) => istate_RNI8BL1A(0), datain(17) => - istate_RNILTAC8(0), datain(16) => istate_RNIK9NF8(0), - datain(15) => istate_RNIA8N5H(0), datain(14) => - istate_RNIOVC5J(0), datain(13) => istate_RNI6PSS1(0), - datain(12) => istate_RNIN6957(0), datain(11) => - istate_RNIKJBN8(0), datain(10) => istate_RNI6LOO6(0), - datain(9) => istate_RNIGUTA8(0), datain(8) => - istate_RNIMRTH8(0), datain(7) => istate_RNIV33V9(0), - datain(6) => istate_RNI7BUID(0), datain(5) => - istate_RNIEC82C(0), datain(4) => istate_RNIG7IIA(0), - datain(3) => istate_RNI57KLB(0), datain(2) => - istate_RNI6HPAI(0), datain(1) => istate_RNIPSU8G(0), - datain(0) => istate_RNIUCOFG(0), dataout(31) => - dataout_2(31), dataout(30) => dataout_2(30), dataout(29) - => dataout_2(29), dataout(28) => dataout_2(28), - dataout(27) => dataout_1(27), dataout(26) => - dataout_1(26), dataout(25) => dataout_1(25), dataout(24) - => dataout_1(24), dataout(23) => dataout_1(23), - dataout(22) => dataout_1(22), dataout(21) => - dataout_1(21), dataout(20) => dataout_1(20), dataout(19) - => dataout_1(19), dataout(18) => dataout_1(18), - dataout(17) => dataout_1(17), dataout(16) => - dataout_1(16), dataout(15) => dataout_1(15), dataout(14) - => dataout_1(14), dataout(13) => dataout_1(13), - dataout(12) => dataout_1(12), dataout(11) => - dataout_1(11), dataout(10) => dataout_1(10), dataout(9) - => dataout_1(9), dataout(8) => dataout_1(8), dataout(7) - => dataout_1(7), dataout(6) => dataout_1(6), dataout(5) - => dataout_1(5), dataout(4) => dataout_1(4), dataout(3) - => dataout_1(3), dataout(2) => dataout_1(2), dataout(1) - => dataout_1(1), dataout(0) => dataout_1(0), enable => - syncramZ1_VCC, write => istate_RNIJCMP6(0)); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ2 is - - port( dataout_0 : out std_logic_vector(35 downto 32); - dataout_1 : out std_logic_vector(31 downto 28); - dataout_2 : out std_logic_vector(27 downto 0); - ctx : in std_logic_vector(7 downto 0); - vaddress_RNI0OAKMI : in std_logic_vector(23 to 23); - vaddress_RNIUNAKMI : in std_logic_vector(22 to 22); - vaddress_RNISNAKMI : in std_logic_vector(21 to 21); - vaddress_RNIQNAKMI : in std_logic_vector(20 to 20); - vaddress_RNI6GAKMI : in std_logic_vector(19 to 19); - vaddress_RNI4GAKMI : in std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : in std_logic_vector(17 to 17); - vaddress_RNI0GAKMI : in std_logic_vector(16 to 16); - vaddress_RNIUFAKMI : in std_logic_vector(15 to 15); - vaddress_RNISFAKMI : in std_logic_vector(14 to 14); - vaddress_RNIQFAKMI : in std_logic_vector(13 to 13); - vaddress_RNIOFAKMI : in std_logic_vector(12 to 12); - un1_p0_2_i_4 : in std_logic; - un1_p0_2_i_0 : in std_logic; - faddr_RNIDN2CUE : in std_logic_vector(6 to 6); - faddr_RNI7UFASD : in std_logic_vector(5 to 5); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4); - faddr_RNIUT72LB : in std_logic_vector(3 to 3); - faddr_RNISJSHQA : in std_logic_vector(2 to 2); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0); - un1_p0_2_0 : in std_logic_vector(148 to 148); - vitdatain_0_1_0 : in std_logic_vector(22 to 22); - flush2_RNI5I3N7 : in std_logic; - syncramZ2_VCC : in std_logic; - flush2_0_0_RNI7G6O2 : in std_logic; - flush2_RNIFMGM2 : in std_logic; - flush2_0_0_RNI146O2 : in std_logic; - flush2_0_0_RNIVV5O2 : in std_logic; - flush2_0_0_RNITR5O2 : in std_logic; - flush2_0_0_RNIPJ5O2 : in std_logic; - lclk_c : in std_logic; - N_984 : in std_logic; - N_987 : in std_logic; - flush2 : in std_logic; - N_986 : in std_logic; - N_985 : in std_logic; - un1_ici : in std_logic; - N_982 : in std_logic; - N_983 : in std_logic; - N_981 : in std_logic; - N_980 : in std_logic - ); - -end syncramZ2; - -architecture DEF_ARCH of syncramZ2 is - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_2 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(6 downto 0) := (others => 'U'); - datain : in std_logic_vector(35 downto 0) := (others => 'U'); - dataout : out std_logic_vector(35 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - signal \vitdatain_0_1[20]\, \vitdatain_0_1[21]\, - \vitdatain_0_1[23]\, \vitdatain_0_1[22]\, - \vitdatain_0_1[25]\, \vitdatain_0_1[26]\, - \vitdatain_0_1[27]\, \vitdatain_0_1[24]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_2 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_2(DEF_ARCH); -begin - - - \proa3.x0_RNO_5\ : AO1A - port map(A => un1_ici, B => N_986, C => flush2, Y => - \vitdatain_0_1[26]\); - - \proa3.x0_RNO_4\ : AO1A - port map(A => un1_ici, B => N_985, C => un1_p0_2_0(148), Y - => \vitdatain_0_1[25]\); - - \proa3.x0_RNO_2\ : NOR2 - port map(A => N_983, B => vitdatain_0_1_0(22), Y => - \vitdatain_0_1[23]\); - - \proa3.x0_RNO\ : NOR2 - port map(A => N_980, B => vitdatain_0_1_0(22), Y => - \vitdatain_0_1[20]\); - - \proa3.x0_RNO_1\ : NOR2 - port map(A => N_982, B => vitdatain_0_1_0(22), Y => - \vitdatain_0_1[22]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO_3\ : AO1A - port map(A => un1_ici, B => N_984, C => flush2, Y => - \vitdatain_0_1[24]\); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \proa3.x0_RNO_6\ : AO1A - port map(A => un1_ici, B => N_987, C => flush2, Y => - \vitdatain_0_1[27]\); - - \proa3.x0_RNO_0\ : NOR2 - port map(A => N_981, B => vitdatain_0_1_0(22), Y => - \vitdatain_0_1[21]\); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_2 - port map(clk => lclk_c, address(6) => faddr_RNIDN2CUE(6), - address(5) => faddr_RNI7UFASD(5), address(4) => - faddr_RNI0FOJNE(4), address(3) => faddr_RNIUT72LB(3), - address(2) => faddr_RNISJSHQA(2), address(1) => - faddr_RNIKVTLT9(1), address(0) => faddr_RNI7H6KT8(0), - datain(35) => ctx(7), datain(34) => ctx(6), datain(33) - => ctx(5), datain(32) => ctx(4), datain(31) => ctx(3), - datain(30) => ctx(2), datain(29) => ctx(1), datain(28) - => ctx(0), datain(27) => \vitdatain_0_1[27]\, datain(26) - => \vitdatain_0_1[26]\, datain(25) => - \vitdatain_0_1[25]\, datain(24) => \vitdatain_0_1[24]\, - datain(23) => \vitdatain_0_1[23]\, datain(22) => - \vitdatain_0_1[22]\, datain(21) => \vitdatain_0_1[21]\, - datain(20) => \vitdatain_0_1[20]\, datain(19) => - vaddress_RNI0OAKMI(23), datain(18) => - vaddress_RNIUNAKMI(22), datain(17) => - vaddress_RNISNAKMI(21), datain(16) => - vaddress_RNIQNAKMI(20), datain(15) => - vaddress_RNI6GAKMI(19), datain(14) => - vaddress_RNI4GAKMI(18), datain(13) => - vaddress_RNI2GAKMI(17), datain(12) => - vaddress_RNI0GAKMI(16), datain(11) => - vaddress_RNIUFAKMI(15), datain(10) => - vaddress_RNISFAKMI(14), datain(9) => - vaddress_RNIQFAKMI(13), datain(8) => - vaddress_RNIOFAKMI(12), datain(7) => flush2_0_0_RNI7G6O2, - datain(6) => flush2_RNIFMGM2, datain(5) => un1_p0_2_i_4, - datain(4) => flush2_0_0_RNI146O2, datain(3) => - flush2_0_0_RNIVV5O2, datain(2) => flush2_0_0_RNITR5O2, - datain(1) => un1_p0_2_i_0, datain(0) => - flush2_0_0_RNIPJ5O2, dataout(35) => dataout_0(35), - dataout(34) => dataout_0(34), dataout(33) => - dataout_0(33), dataout(32) => dataout_0(32), dataout(31) - => dataout_1(31), dataout(30) => dataout_1(30), - dataout(29) => dataout_1(29), dataout(28) => - dataout_1(28), dataout(27) => dataout_2(27), dataout(26) - => dataout_2(26), dataout(25) => dataout_2(25), - dataout(24) => dataout_2(24), dataout(23) => - dataout_2(23), dataout(22) => dataout_2(22), dataout(21) - => dataout_2(21), dataout(20) => dataout_2(20), - dataout(19) => dataout_2(19), dataout(18) => - dataout_2(18), dataout(17) => dataout_2(17), dataout(16) - => dataout_2(16), dataout(15) => dataout_2(15), - dataout(14) => dataout_2(14), dataout(13) => - dataout_2(13), dataout(12) => dataout_2(12), dataout(11) - => dataout_2(11), dataout(10) => dataout_2(10), - dataout(9) => dataout_2(9), dataout(8) => dataout_2(8), - dataout(7) => dataout_2(7), dataout(6) => dataout_2(6), - dataout(5) => dataout_2(5), dataout(4) => dataout_2(4), - dataout(3) => dataout_2(3), dataout(2) => dataout_2(2), - dataout(1) => dataout_2(1), dataout(0) => dataout_2(0), - enable => syncramZ2_VCC, write => flush2_RNI5I3N7); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity cachemem is - - port( xaddress_RNIFP43F : in std_logic_vector(2 to 2); - xaddress_RNITFTTE : in std_logic_vector(3 to 3); - dstate_RNIC3QA81 : in std_logic_vector(1 to 1); - dstate_RNIFPT581 : in std_logic_vector(1 to 1); - dstate_RNIFS6E51 : in std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : in std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : in std_logic_vector(1 to 1); - xaddress_RNILHOK61 : in std_logic_vector(1 to 1); - xaddress_RNILK99L1 : in std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : in std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : in std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : in std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : in std_logic_vector(1 to 1); - dstate_RNI1G47MJ : in std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 to 31); - addr : in std_logic_vector(30 to 30); - maddress : in std_logic_vector(28 to 28); - newtag_1_0 : in std_logic_vector(27 downto 24); - faddr_RNI7879K : in std_logic_vector(0 to 0); - faddr_RNIEHR0O : in std_logic_vector(1 to 1); - faddr_RNIB0UOO : in std_logic_vector(2 to 2); - xaddress_RNID252J1 : in std_logic_vector(10 to 10); - faddr_RNI7MK691 : in std_logic_vector(6 to 6); - dstate_i_0_RNIL7FGFS : in std_logic_vector(8 to 8); - dstate_i_0_RNIH0PPES : in std_logic_vector(8 to 8); - dstate_i_RNI29QQ7J3 : in std_logic_vector(8 to 8); - xaddress_RNITMH17S2 : in std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : in std_logic_vector(13 to 13); - xaddress_RNIN7J17S2 : in std_logic_vector(14 to 14); - xaddress_RNI2MB27S2 : in std_logic_vector(15 to 15); - xaddress_RNIID927S2 : in std_logic_vector(16 to 16); - xaddress_RNI0GI17S2 : in std_logic_vector(17 to 17); - xaddress_RNI1D927S2 : in std_logic_vector(20 to 20); - xaddress_RNIC5A27S2 : in std_logic_vector(21 to 21); - xaddress_RNI9MB27S2 : in std_logic_vector(23 to 23); - dataout : out std_logic_vector(35 downto 0); - vaddress_RNI8EVQ36 : in std_logic_vector(2 to 2); - vaddress_RNIFCB8U6 : in std_logic_vector(3 to 3); - vaddress_RNIJG6QR7 : in std_logic_vector(4 to 4); - istate_RNIUCOFG : in std_logic_vector(0 to 0); - istate_RNIPSU8G : in std_logic_vector(0 to 0); - istate_RNI6HPAI : in std_logic_vector(0 to 0); - istate_RNI57KLB : in std_logic_vector(0 to 0); - istate_RNIG7IIA : in std_logic_vector(0 to 0); - istate_RNIEC82C : in std_logic_vector(0 to 0); - istate_RNI7BUID : in std_logic_vector(0 to 0); - istate_RNIV33V9 : in std_logic_vector(0 to 0); - istate_RNIMRTH8 : in std_logic_vector(0 to 0); - istate_RNIGUTA8 : in std_logic_vector(0 to 0); - istate_RNI6LOO6 : in std_logic_vector(0 to 0); - istate_RNIKJBN8 : in std_logic_vector(0 to 0); - istate_RNIN6957 : in std_logic_vector(0 to 0); - istate_RNI6PSS1 : in std_logic_vector(0 to 0); - istate_RNIOVC5J : in std_logic_vector(0 to 0); - istate_RNIA8N5H : in std_logic_vector(0 to 0); - istate_RNIK9NF8 : in std_logic_vector(0 to 0); - istate_RNILTAC8 : in std_logic_vector(0 to 0); - istate_RNI8BL1A : in std_logic_vector(0 to 0); - istate_RNI2MM6D : in std_logic_vector(0 to 0); - istate_RNIVTQIJ : in std_logic_vector(0 to 0); - istate_RNIAJH4F : in std_logic_vector(0 to 0); - istate_RNIM2DE7 : in std_logic_vector(0 to 0); - istate_RNI5V68H : in std_logic_vector(0 to 0); - istate_RNIH0NBI : in std_logic_vector(0 to 0); - istate_RNIAP6PI : in std_logic_vector(0 to 0); - istate_RNIOJJE1 : in std_logic_vector(0 to 0); - istate_RNIR2JU8 : in std_logic_vector(0 to 0); - istate_RNIJSOBE : in std_logic_vector(0 to 0); - istate_RNIRASC8 : in std_logic_vector(0 to 0); - istate_RNIS4VK8 : in std_logic_vector(0 to 0); - istate_RNIENB3M : in std_logic_vector(0 to 0); - istate_RNIJCMP6 : in std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1); - faddr_RNISJSHQA : in std_logic_vector(2 to 2); - faddr_RNIUT72LB : in std_logic_vector(3 to 3); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4); - faddr_RNI7UFASD : in std_logic_vector(5 to 5); - faddr_RNIDN2CUE : in std_logic_vector(6 to 6); - un1_p0_2_i_0 : in std_logic; - un1_p0_2_i_4 : in std_logic; - vaddress_RNIOFAKMI : in std_logic_vector(12 to 12); - vaddress_RNIQFAKMI : in std_logic_vector(13 to 13); - vaddress_RNISFAKMI : in std_logic_vector(14 to 14); - vaddress_RNIUFAKMI : in std_logic_vector(15 to 15); - vaddress_RNI0GAKMI : in std_logic_vector(16 to 16); - vaddress_RNI2GAKMI : in std_logic_vector(17 to 17); - vaddress_RNI4GAKMI : in std_logic_vector(18 to 18); - vaddress_RNI6GAKMI : in std_logic_vector(19 to 19); - vaddress_RNIQNAKMI : in std_logic_vector(20 to 20); - vaddress_RNISNAKMI : in std_logic_vector(21 to 21); - vaddress_RNIUNAKMI : in std_logic_vector(22 to 22); - vaddress_RNI0OAKMI : in std_logic_vector(23 to 23); - ctx : in std_logic_vector(7 downto 0); - dataout_2 : out std_logic_vector(31 downto 0); - dataout_1 : out std_logic_vector(31 downto 0); - dataout_0 : out std_logic_vector(35 downto 0); - vitdatain_0_1_0 : out std_logic_vector(22 to 22); - un1_p0_2_0_0 : in std_logic; - un1_p0_2_0_350 : in std_logic; - dci_m_6 : in std_logic; - dci_m_0 : in std_logic; - dci_m_1 : in std_logic; - dci_m_2 : in std_logic; - dci_m_3 : in std_logic; - dci_m_5 : in std_logic; - N_10 : in std_logic; - read_RNI0IQ7R : in std_logic; - read_RNIRO4K31 : in std_logic; - read_RNIQFOD21 : in std_logic; - read_RNIFPFT31 : in std_logic; - read_RNIQPCQ11 : in std_logic; - read_RNI8DFM31 : in std_logic; - read_RNIAQJ831 : in std_logic; - read_RNI76N8R : in std_logic; - read_RNI7G7G41 : in std_logic; - read_RNIEKS231 : in std_logic; - read_RNIMJHQT : in std_logic; - read_RNIL633F1 : in std_logic; - read_RNIQH64D1 : in std_logic; - read_RNICAQK41 : in std_logic; - read_RNIQMJI41 : in std_logic; - read_RNISLPNU : in std_logic; - read_RNICKHE91 : in std_logic; - read_RNIC70OF1 : in std_logic; - read_RNIC9O9B1 : in std_logic; - read_RNI75LJ31 : in std_logic; - read_RNIEEGDD1 : in std_logic; - N_3254_0 : in std_logic; - N_330 : in std_logic; - N_267 : in std_logic; - N_329 : in std_logic; - N_144 : in std_logic; - N_3846 : in std_logic; - N_270 : in std_logic; - N_269 : in std_logic; - N_24 : in std_logic; - N_26 : in std_logic; - N_12_i_0 : in std_logic; - flush_RNIJEN4SI3 : in std_logic; - flush_RNIGUM2OH3 : in std_logic; - N_16_i_0 : in std_logic; - N_3239_i_0 : in std_logic; - flush_0_1_RNIBUA27S2 : in std_logic; - flush_0_1_RNIOMB27S2 : in std_logic; - flush_0_1_RNIPTA27S2 : in std_logic; - flush_RNIGBB873 : in std_logic; - N_980 : in std_logic; - N_981 : in std_logic; - N_983 : in std_logic; - N_982 : in std_logic; - N_985 : in std_logic; - N_986 : in std_logic; - flush2 : in std_logic; - N_987 : in std_logic; - N_984 : in std_logic; - lclk_c : in std_logic; - flush2_0_0_RNIPJ5O2 : in std_logic; - flush2_0_0_RNITR5O2 : in std_logic; - flush2_0_0_RNIVV5O2 : in std_logic; - flush2_0_0_RNI146O2 : in std_logic; - flush2_RNIFMGM2 : in std_logic; - flush2_0_0_RNI7G6O2 : in std_logic; - cachemem_VCC : in std_logic; - flush2_RNI5I3N7 : in std_logic; - un1_ici : in std_logic; - N_258 : in std_logic; - N_259 : in std_logic - ); - -end cachemem; - -architecture DEF_ARCH of cachemem is - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ1_1 - port( dstate_RNI1G47MJ : in std_logic_vector(1 to 1) := (others => 'U'); - dataout_0 : out std_logic_vector(31 downto 28); - dataout : out std_logic_vector(27 downto 0); - xaddress_RNIJI2O22 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIP2BVK1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIK99NK1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNI1I3MQ1 : in std_logic_vector(0 to 0) := (others => 'U'); - xaddress_RNILK99L1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNILHOK61 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIEHIUT1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNI1Q9ST1 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIFS6E51 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIFPT581 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIC3QA81 : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7MK691 : in std_logic_vector(6 to 6) := (others => 'U'); - xaddress_RNID252J1 : in std_logic_vector(10 to 10) := (others => 'U'); - faddr_RNIB0UOO : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIEHR0O : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7879K : in std_logic_vector(0 to 0) := (others => 'U'); - xaddress_RNITFTTE : in std_logic_vector(3 to 3) := (others => 'U'); - xaddress_RNIFP43F : in std_logic_vector(2 to 2) := (others => 'U'); - syncramZ1_1_VCC : in std_logic := 'U'; - read_RNIEEGDD1 : in std_logic := 'U'; - read_RNI75LJ31 : in std_logic := 'U'; - read_RNIC9O9B1 : in std_logic := 'U'; - read_RNIC70OF1 : in std_logic := 'U'; - read_RNICKHE91 : in std_logic := 'U'; - read_RNISLPNU : in std_logic := 'U'; - read_RNIQMJI41 : in std_logic := 'U'; - read_RNICAQK41 : in std_logic := 'U'; - read_RNIQH64D1 : in std_logic := 'U'; - read_RNIL633F1 : in std_logic := 'U'; - read_RNIMJHQT : in std_logic := 'U'; - read_RNIEKS231 : in std_logic := 'U'; - read_RNI7G7G41 : in std_logic := 'U'; - read_RNI76N8R : in std_logic := 'U'; - read_RNIAQJ831 : in std_logic := 'U'; - read_RNI8DFM31 : in std_logic := 'U'; - read_RNIQPCQ11 : in std_logic := 'U'; - read_RNIFPFT31 : in std_logic := 'U'; - read_RNIQFOD21 : in std_logic := 'U'; - read_RNIRO4K31 : in std_logic := 'U'; - read_RNI0IQ7R : in std_logic := 'U'; - N_26 : in std_logic := 'U'; - N_24 : in std_logic := 'U'; - N_10 : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component syncramZ2_1 - port( dataout : out std_logic_vector(35 downto 28); - dataout_0 : out std_logic_vector(27 downto 0); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - vdtdatain_0_1_5 : in std_logic := 'U'; - xaddress_RNI9MB27S2 : in std_logic_vector(23 to 23) := (others => 'U'); - xaddress_RNIC5A27S2 : in std_logic_vector(21 to 21) := (others => 'U'); - xaddress_RNI1D927S2 : in std_logic_vector(20 to 20) := (others => 'U'); - xaddress_RNI0GI17S2 : in std_logic_vector(17 to 17) := (others => 'U'); - xaddress_RNIID927S2 : in std_logic_vector(16 to 16) := (others => 'U'); - xaddress_RNI2MB27S2 : in std_logic_vector(15 to 15) := (others => 'U'); - xaddress_RNIN7J17S2 : in std_logic_vector(14 to 14) := (others => 'U'); - xaddress_RNICFI17S2 : in std_logic_vector(13 to 13) := (others => 'U'); - xaddress_RNITMH17S2 : in std_logic_vector(12 to 12) := (others => 'U'); - dstate_i_RNI29QQ7J3 : in std_logic_vector(8 to 8) := (others => 'U'); - dstate_i_0_RNIH0PPES : in std_logic_vector(8 to 8) := (others => 'U'); - dstate_i_0_RNIL7FGFS : in std_logic_vector(8 to 8) := (others => 'U'); - faddr_RNI7MK691 : in std_logic_vector(6 to 6) := (others => 'U'); - xaddress_RNID252J1 : in std_logic_vector(10 to 10) := (others => 'U'); - faddr_RNIB0UOO : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIEHR0O : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7879K : in std_logic_vector(0 to 0) := (others => 'U'); - newtag_1_0 : in std_logic_vector(27 downto 24) := (others => 'U'); - dci_m_3 : in std_logic := 'U'; - dci_m_2 : in std_logic := 'U'; - dci_m_1 : in std_logic := 'U'; - dci_m_0 : in std_logic := 'U'; - dci_m_6 : in std_logic := 'U'; - maddress : in std_logic_vector(28 to 28) := (others => 'U'); - addr : in std_logic_vector(30 to 30) := (others => 'U'); - un1_p0_2_0 : in std_logic_vector(498 to 498) := (others => 'U'); - edata2_iv_i_0 : in std_logic_vector(31 to 31) := (others => 'U'); - flush_RNIGBB873 : in std_logic := 'U'; - syncramZ2_1_VCC : in std_logic := 'U'; - flush_0_1_RNIPTA27S2 : in std_logic := 'U'; - flush_0_1_RNIOMB27S2 : in std_logic := 'U'; - flush_0_1_RNIBUA27S2 : in std_logic := 'U'; - N_3239_i_0 : in std_logic := 'U'; - N_16_i_0 : in std_logic := 'U'; - flush_RNIGUM2OH3 : in std_logic := 'U'; - flush_RNIJEN4SI3 : in std_logic := 'U'; - N_12_i_0 : in std_logic := 'U'; - N_26 : in std_logic := 'U'; - N_24 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_269 : in std_logic := 'U'; - N_270 : in std_logic := 'U'; - N_3846 : in std_logic := 'U'; - N_144 : in std_logic := 'U'; - N_329 : in std_logic := 'U'; - N_267 : in std_logic := 'U'; - N_330 : in std_logic := 'U'; - N_3254_0 : in std_logic := 'U' - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ1 - port( istate_RNIJCMP6 : in std_logic_vector(0 to 0) := (others => 'U'); - dataout_2 : out std_logic_vector(31 downto 28); - dataout_1 : out std_logic_vector(27 downto 0); - istate_RNIENB3M : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIS4VK8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIRASC8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIJSOBE : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIR2JU8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIOJJE1 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIAP6PI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIH0NBI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI5V68H : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIM2DE7 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIAJH4F : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIVTQIJ : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI2MM6D : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI8BL1A : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNILTAC8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIK9NF8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIA8N5H : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIOVC5J : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6PSS1 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIN6957 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIKJBN8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6LOO6 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIGUTA8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIMRTH8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIV33V9 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI7BUID : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIEC82C : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIG7IIA : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI57KLB : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6HPAI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIPSU8G : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIUCOFG : in std_logic_vector(0 to 0) := (others => 'U'); - faddr_RNIDN2CUE : in std_logic_vector(6 to 6) := (others => 'U'); - faddr_RNI7UFASD : in std_logic_vector(5 to 5) := (others => 'U'); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4) := (others => 'U'); - faddr_RNIUT72LB : in std_logic_vector(3 to 3) := (others => 'U'); - faddr_RNISJSHQA : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0) := (others => 'U'); - vaddress_RNIJG6QR7 : in std_logic_vector(4 to 4) := (others => 'U'); - vaddress_RNIFCB8U6 : in std_logic_vector(3 to 3) := (others => 'U'); - vaddress_RNI8EVQ36 : in std_logic_vector(2 to 2) := (others => 'U'); - syncramZ1_VCC : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component syncramZ2 - port( dataout_0 : out std_logic_vector(35 downto 32); - dataout_1 : out std_logic_vector(31 downto 28); - dataout_2 : out std_logic_vector(27 downto 0); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - vaddress_RNI0OAKMI : in std_logic_vector(23 to 23) := (others => 'U'); - vaddress_RNIUNAKMI : in std_logic_vector(22 to 22) := (others => 'U'); - vaddress_RNISNAKMI : in std_logic_vector(21 to 21) := (others => 'U'); - vaddress_RNIQNAKMI : in std_logic_vector(20 to 20) := (others => 'U'); - vaddress_RNI6GAKMI : in std_logic_vector(19 to 19) := (others => 'U'); - vaddress_RNI4GAKMI : in std_logic_vector(18 to 18) := (others => 'U'); - vaddress_RNI2GAKMI : in std_logic_vector(17 to 17) := (others => 'U'); - vaddress_RNI0GAKMI : in std_logic_vector(16 to 16) := (others => 'U'); - vaddress_RNIUFAKMI : in std_logic_vector(15 to 15) := (others => 'U'); - vaddress_RNISFAKMI : in std_logic_vector(14 to 14) := (others => 'U'); - vaddress_RNIQFAKMI : in std_logic_vector(13 to 13) := (others => 'U'); - vaddress_RNIOFAKMI : in std_logic_vector(12 to 12) := (others => 'U'); - un1_p0_2_i_4 : in std_logic := 'U'; - un1_p0_2_i_0 : in std_logic := 'U'; - faddr_RNIDN2CUE : in std_logic_vector(6 to 6) := (others => 'U'); - faddr_RNI7UFASD : in std_logic_vector(5 to 5) := (others => 'U'); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4) := (others => 'U'); - faddr_RNIUT72LB : in std_logic_vector(3 to 3) := (others => 'U'); - faddr_RNISJSHQA : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0) := (others => 'U'); - un1_p0_2_0 : in std_logic_vector(148 to 148) := (others => 'U'); - vitdatain_0_1_0 : in std_logic_vector(22 to 22) := (others => 'U'); - flush2_RNI5I3N7 : in std_logic := 'U'; - syncramZ2_VCC : in std_logic := 'U'; - flush2_0_0_RNI7G6O2 : in std_logic := 'U'; - flush2_RNIFMGM2 : in std_logic := 'U'; - flush2_0_0_RNI146O2 : in std_logic := 'U'; - flush2_0_0_RNIVV5O2 : in std_logic := 'U'; - flush2_0_0_RNITR5O2 : in std_logic := 'U'; - flush2_0_0_RNIPJ5O2 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_984 : in std_logic := 'U'; - N_987 : in std_logic := 'U'; - flush2 : in std_logic := 'U'; - N_986 : in std_logic := 'U'; - N_985 : in std_logic := 'U'; - un1_ici : in std_logic := 'U'; - N_982 : in std_logic := 'U'; - N_983 : in std_logic := 'U'; - N_981 : in std_logic := 'U'; - N_980 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \vdtdatain_0_1[25]\, \vdtdatain_0_1_0[25]\, - \vdtdatain_0_1_1[25]\, \vitdatain_0_1_0[22]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : syncramZ1_1 - Use entity work.syncramZ1_1(DEF_ARCH); - for all : syncramZ2_1 - Use entity work.syncramZ2_1(DEF_ARCH); - for all : syncramZ1 - Use entity work.syncramZ1(DEF_ARCH); - for all : syncramZ2 - Use entity work.syncramZ2(DEF_ARCH); -begin - - vitdatain_0_1_0(22) <= \vitdatain_0_1_0[22]\; - - \itinsel.vdtdatain_0_1[25]\ : NAND2 - port map(A => \vdtdatain_0_1_0[25]\, B => - \vdtdatain_0_1_1[25]\, Y => \vdtdatain_0_1[25]\); - - \itinsel.vitdatain_0_1_0[20]\ : OR2 - port map(A => un1_p0_2_0_0, B => un1_ici, Y => - \vitdatain_0_1_0[22]\); - - \itinsel.vdtdatain_0_1_RNO[25]\ : AND2 - port map(A => N_259, B => N_258, Y => \vdtdatain_0_1_0[25]\); - - \dme.dd0.0.ddata0\ : syncramZ1_1 - port map(dstate_RNI1G47MJ(1) => dstate_RNI1G47MJ(1), - dataout_0(31) => dataout_0(31), dataout_0(30) => - dataout_0(30), dataout_0(29) => dataout_0(29), - dataout_0(28) => dataout_0(28), dataout(27) => - dataout(27), dataout(26) => dataout(26), dataout(25) => - dataout(25), dataout(24) => dataout(24), dataout(23) => - dataout(23), dataout(22) => dataout(22), dataout(21) => - dataout(21), dataout(20) => dataout(20), dataout(19) => - dataout(19), dataout(18) => dataout(18), dataout(17) => - dataout(17), dataout(16) => dataout(16), dataout(15) => - dataout(15), dataout(14) => dataout(14), dataout(13) => - dataout(13), dataout(12) => dataout(12), dataout(11) => - dataout(11), dataout(10) => dataout(10), dataout(9) => - dataout(9), dataout(8) => dataout(8), dataout(7) => - dataout(7), dataout(6) => dataout(6), dataout(5) => - dataout(5), dataout(4) => dataout(4), dataout(3) => - dataout(3), dataout(2) => dataout(2), dataout(1) => - dataout(1), dataout(0) => dataout(0), - xaddress_RNIJI2O22(1) => xaddress_RNIJI2O22(1), - xaddress_RNIP2BVK1(1) => xaddress_RNIP2BVK1(1), - xaddress_RNIK99NK1(1) => xaddress_RNIK99NK1(1), - xaddress_RNI1I3MQ1(0) => xaddress_RNI1I3MQ1(0), - xaddress_RNILK99L1(1) => xaddress_RNILK99L1(1), - xaddress_RNILHOK61(1) => xaddress_RNILHOK61(1), - xaddress_RNIEHIUT1(1) => xaddress_RNIEHIUT1(1), - xaddress_RNI1Q9ST1(1) => xaddress_RNI1Q9ST1(1), - dstate_RNIFS6E51(1) => dstate_RNIFS6E51(1), - dstate_RNIFPT581(1) => dstate_RNIFPT581(1), - dstate_RNIC3QA81(1) => dstate_RNIC3QA81(1), - faddr_RNI7MK691(6) => faddr_RNI7MK691(6), - xaddress_RNID252J1(10) => xaddress_RNID252J1(10), - faddr_RNIB0UOO(2) => faddr_RNIB0UOO(2), faddr_RNIEHR0O(1) - => faddr_RNIEHR0O(1), faddr_RNI7879K(0) => - faddr_RNI7879K(0), xaddress_RNITFTTE(3) => - xaddress_RNITFTTE(3), xaddress_RNIFP43F(2) => - xaddress_RNIFP43F(2), syncramZ1_1_VCC => cachemem_VCC, - read_RNIEEGDD1 => read_RNIEEGDD1, read_RNI75LJ31 => - read_RNI75LJ31, read_RNIC9O9B1 => read_RNIC9O9B1, - read_RNIC70OF1 => read_RNIC70OF1, read_RNICKHE91 => - read_RNICKHE91, read_RNISLPNU => read_RNISLPNU, - read_RNIQMJI41 => read_RNIQMJI41, read_RNICAQK41 => - read_RNICAQK41, read_RNIQH64D1 => read_RNIQH64D1, - read_RNIL633F1 => read_RNIL633F1, read_RNIMJHQT => - read_RNIMJHQT, read_RNIEKS231 => read_RNIEKS231, - read_RNI7G7G41 => read_RNI7G7G41, read_RNI76N8R => - read_RNI76N8R, read_RNIAQJ831 => read_RNIAQJ831, - read_RNI8DFM31 => read_RNI8DFM31, read_RNIQPCQ11 => - read_RNIQPCQ11, read_RNIFPFT31 => read_RNIFPFT31, - read_RNIQFOD21 => read_RNIQFOD21, read_RNIRO4K31 => - read_RNIRO4K31, read_RNI0IQ7R => read_RNI0IQ7R, N_26 => - N_26, N_24 => N_24, N_10 => N_10, lclk_c => lclk_c); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \dme.dtags0.dt0.0.dtags0\ : syncramZ2_1 - port map(dataout(35) => dataout(35), dataout(34) => - dataout(34), dataout(33) => dataout(33), dataout(32) => - dataout(32), dataout(31) => dataout(31), dataout(30) => - dataout(30), dataout(29) => dataout(29), dataout(28) => - dataout(28), dataout_0(27) => dataout_0(27), - dataout_0(26) => dataout_0(26), dataout_0(25) => - dataout_0(25), dataout_0(24) => dataout_0(24), - dataout_0(23) => dataout_0(23), dataout_0(22) => - dataout_0(22), dataout_0(21) => dataout_0(21), - dataout_0(20) => dataout_0(20), dataout_0(19) => - dataout_0(19), dataout_0(18) => dataout_0(18), - dataout_0(17) => dataout_0(17), dataout_0(16) => - dataout_0(16), dataout_0(15) => dataout_0(15), - dataout_0(14) => dataout_0(14), dataout_0(13) => - dataout_0(13), dataout_0(12) => dataout_0(12), - dataout_0(11) => dataout_0(11), dataout_0(10) => - dataout_0(10), dataout_0(9) => dataout_0(9), dataout_0(8) - => dataout_0(8), dataout_0(7) => dataout_0(7), - dataout_0(6) => dataout_0(6), dataout_0(5) => - dataout_0(5), dataout_0(4) => dataout_0(4), dataout_0(3) - => dataout_0(3), dataout_0(2) => dataout_0(2), - dataout_0(1) => dataout_0(1), dataout_0(0) => - dataout_0(0), ctx(7) => ctx(7), ctx(6) => ctx(6), ctx(5) - => ctx(5), ctx(4) => ctx(4), ctx(3) => ctx(3), ctx(2) - => ctx(2), ctx(1) => ctx(1), ctx(0) => ctx(0), - vdtdatain_0_1_5 => \vdtdatain_0_1[25]\, - xaddress_RNI9MB27S2(23) => xaddress_RNI9MB27S2(23), - xaddress_RNIC5A27S2(21) => xaddress_RNIC5A27S2(21), - xaddress_RNI1D927S2(20) => xaddress_RNI1D927S2(20), - xaddress_RNI0GI17S2(17) => xaddress_RNI0GI17S2(17), - xaddress_RNIID927S2(16) => xaddress_RNIID927S2(16), - xaddress_RNI2MB27S2(15) => xaddress_RNI2MB27S2(15), - xaddress_RNIN7J17S2(14) => xaddress_RNIN7J17S2(14), - xaddress_RNICFI17S2(13) => xaddress_RNICFI17S2(13), - xaddress_RNITMH17S2(12) => xaddress_RNITMH17S2(12), - dstate_i_RNI29QQ7J3(8) => dstate_i_RNI29QQ7J3(8), - dstate_i_0_RNIH0PPES(8) => dstate_i_0_RNIH0PPES(8), - dstate_i_0_RNIL7FGFS(8) => dstate_i_0_RNIL7FGFS(8), - faddr_RNI7MK691(6) => faddr_RNI7MK691(6), - xaddress_RNID252J1(10) => xaddress_RNID252J1(10), - faddr_RNIB0UOO(2) => faddr_RNIB0UOO(2), faddr_RNIEHR0O(1) - => faddr_RNIEHR0O(1), faddr_RNI7879K(0) => - faddr_RNI7879K(0), newtag_1_0(27) => newtag_1_0(27), - newtag_1_0(26) => newtag_1_0(26), newtag_1_0(25) => - newtag_1_0(25), newtag_1_0(24) => newtag_1_0(24), dci_m_3 - => dci_m_3, dci_m_2 => dci_m_2, dci_m_1 => dci_m_1, - dci_m_0 => dci_m_0, dci_m_6 => dci_m_6, maddress(28) => - maddress(28), addr(30) => addr(30), un1_p0_2_0(498) => - un1_p0_2_0_350, edata2_iv_i_0(31) => edata2_iv_i_0(31), - flush_RNIGBB873 => flush_RNIGBB873, syncramZ2_1_VCC => - cachemem_VCC, flush_0_1_RNIPTA27S2 => - flush_0_1_RNIPTA27S2, flush_0_1_RNIOMB27S2 => - flush_0_1_RNIOMB27S2, flush_0_1_RNIBUA27S2 => - flush_0_1_RNIBUA27S2, N_3239_i_0 => N_3239_i_0, N_16_i_0 - => N_16_i_0, flush_RNIGUM2OH3 => flush_RNIGUM2OH3, - flush_RNIJEN4SI3 => flush_RNIJEN4SI3, N_12_i_0 => - N_12_i_0, N_26 => N_26, N_24 => N_24, lclk_c => lclk_c, - N_269 => N_269, N_270 => N_270, N_3846 => N_3846, N_144 - => N_144, N_329 => N_329, N_267 => N_267, N_330 => N_330, - N_3254_0 => N_3254_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \itinsel.vdtdatain_0_1_RNO_0[25]\ : NOR2A - port map(A => dci_m_5, B => un1_p0_2_0_350, Y => - \vdtdatain_0_1_1[25]\); - - \ime.im0.0.idata0\ : syncramZ1 - port map(istate_RNIJCMP6(0) => istate_RNIJCMP6(0), - dataout_2(31) => dataout_2(31), dataout_2(30) => - dataout_2(30), dataout_2(29) => dataout_2(29), - dataout_2(28) => dataout_2(28), dataout_1(27) => - dataout_1(27), dataout_1(26) => dataout_1(26), - dataout_1(25) => dataout_1(25), dataout_1(24) => - dataout_1(24), dataout_1(23) => dataout_1(23), - dataout_1(22) => dataout_1(22), dataout_1(21) => - dataout_1(21), dataout_1(20) => dataout_1(20), - dataout_1(19) => dataout_1(19), dataout_1(18) => - dataout_1(18), dataout_1(17) => dataout_1(17), - dataout_1(16) => dataout_1(16), dataout_1(15) => - dataout_1(15), dataout_1(14) => dataout_1(14), - dataout_1(13) => dataout_1(13), dataout_1(12) => - dataout_1(12), dataout_1(11) => dataout_1(11), - dataout_1(10) => dataout_1(10), dataout_1(9) => - dataout_1(9), dataout_1(8) => dataout_1(8), dataout_1(7) - => dataout_1(7), dataout_1(6) => dataout_1(6), - dataout_1(5) => dataout_1(5), dataout_1(4) => - dataout_1(4), dataout_1(3) => dataout_1(3), dataout_1(2) - => dataout_1(2), dataout_1(1) => dataout_1(1), - dataout_1(0) => dataout_1(0), istate_RNIENB3M(0) => - istate_RNIENB3M(0), istate_RNIS4VK8(0) => - istate_RNIS4VK8(0), istate_RNIRASC8(0) => - istate_RNIRASC8(0), istate_RNIJSOBE(0) => - istate_RNIJSOBE(0), istate_RNIR2JU8(0) => - istate_RNIR2JU8(0), istate_RNIOJJE1(0) => - istate_RNIOJJE1(0), istate_RNIAP6PI(0) => - istate_RNIAP6PI(0), istate_RNIH0NBI(0) => - istate_RNIH0NBI(0), istate_RNI5V68H(0) => - istate_RNI5V68H(0), istate_RNIM2DE7(0) => - istate_RNIM2DE7(0), istate_RNIAJH4F(0) => - istate_RNIAJH4F(0), istate_RNIVTQIJ(0) => - istate_RNIVTQIJ(0), istate_RNI2MM6D(0) => - istate_RNI2MM6D(0), istate_RNI8BL1A(0) => - istate_RNI8BL1A(0), istate_RNILTAC8(0) => - istate_RNILTAC8(0), istate_RNIK9NF8(0) => - istate_RNIK9NF8(0), istate_RNIA8N5H(0) => - istate_RNIA8N5H(0), istate_RNIOVC5J(0) => - istate_RNIOVC5J(0), istate_RNI6PSS1(0) => - istate_RNI6PSS1(0), istate_RNIN6957(0) => - istate_RNIN6957(0), istate_RNIKJBN8(0) => - istate_RNIKJBN8(0), istate_RNI6LOO6(0) => - istate_RNI6LOO6(0), istate_RNIGUTA8(0) => - istate_RNIGUTA8(0), istate_RNIMRTH8(0) => - istate_RNIMRTH8(0), istate_RNIV33V9(0) => - istate_RNIV33V9(0), istate_RNI7BUID(0) => - istate_RNI7BUID(0), istate_RNIEC82C(0) => - istate_RNIEC82C(0), istate_RNIG7IIA(0) => - istate_RNIG7IIA(0), istate_RNI57KLB(0) => - istate_RNI57KLB(0), istate_RNI6HPAI(0) => - istate_RNI6HPAI(0), istate_RNIPSU8G(0) => - istate_RNIPSU8G(0), istate_RNIUCOFG(0) => - istate_RNIUCOFG(0), faddr_RNIDN2CUE(6) => - faddr_RNIDN2CUE(6), faddr_RNI7UFASD(5) => - faddr_RNI7UFASD(5), faddr_RNI0FOJNE(4) => - faddr_RNI0FOJNE(4), faddr_RNIUT72LB(3) => - faddr_RNIUT72LB(3), faddr_RNISJSHQA(2) => - faddr_RNISJSHQA(2), faddr_RNIKVTLT9(1) => - faddr_RNIKVTLT9(1), faddr_RNI7H6KT8(0) => - faddr_RNI7H6KT8(0), vaddress_RNIJG6QR7(4) => - vaddress_RNIJG6QR7(4), vaddress_RNIFCB8U6(3) => - vaddress_RNIFCB8U6(3), vaddress_RNI8EVQ36(2) => - vaddress_RNI8EVQ36(2), syncramZ1_VCC => cachemem_VCC, - lclk_c => lclk_c); - - \ime.im0.0.itags0\ : syncramZ2 - port map(dataout_0(35) => dataout_0(35), dataout_0(34) => - dataout_0(34), dataout_0(33) => dataout_0(33), - dataout_0(32) => dataout_0(32), dataout_1(31) => - dataout_1(31), dataout_1(30) => dataout_1(30), - dataout_1(29) => dataout_1(29), dataout_1(28) => - dataout_1(28), dataout_2(27) => dataout_2(27), - dataout_2(26) => dataout_2(26), dataout_2(25) => - dataout_2(25), dataout_2(24) => dataout_2(24), - dataout_2(23) => dataout_2(23), dataout_2(22) => - dataout_2(22), dataout_2(21) => dataout_2(21), - dataout_2(20) => dataout_2(20), dataout_2(19) => - dataout_2(19), dataout_2(18) => dataout_2(18), - dataout_2(17) => dataout_2(17), dataout_2(16) => - dataout_2(16), dataout_2(15) => dataout_2(15), - dataout_2(14) => dataout_2(14), dataout_2(13) => - dataout_2(13), dataout_2(12) => dataout_2(12), - dataout_2(11) => dataout_2(11), dataout_2(10) => - dataout_2(10), dataout_2(9) => dataout_2(9), dataout_2(8) - => dataout_2(8), dataout_2(7) => dataout_2(7), - dataout_2(6) => dataout_2(6), dataout_2(5) => - dataout_2(5), dataout_2(4) => dataout_2(4), dataout_2(3) - => dataout_2(3), dataout_2(2) => dataout_2(2), - dataout_2(1) => dataout_2(1), dataout_2(0) => - dataout_2(0), ctx(7) => ctx(7), ctx(6) => ctx(6), ctx(5) - => ctx(5), ctx(4) => ctx(4), ctx(3) => ctx(3), ctx(2) - => ctx(2), ctx(1) => ctx(1), ctx(0) => ctx(0), - vaddress_RNI0OAKMI(23) => vaddress_RNI0OAKMI(23), - vaddress_RNIUNAKMI(22) => vaddress_RNIUNAKMI(22), - vaddress_RNISNAKMI(21) => vaddress_RNISNAKMI(21), - vaddress_RNIQNAKMI(20) => vaddress_RNIQNAKMI(20), - vaddress_RNI6GAKMI(19) => vaddress_RNI6GAKMI(19), - vaddress_RNI4GAKMI(18) => vaddress_RNI4GAKMI(18), - vaddress_RNI2GAKMI(17) => vaddress_RNI2GAKMI(17), - vaddress_RNI0GAKMI(16) => vaddress_RNI0GAKMI(16), - vaddress_RNIUFAKMI(15) => vaddress_RNIUFAKMI(15), - vaddress_RNISFAKMI(14) => vaddress_RNISFAKMI(14), - vaddress_RNIQFAKMI(13) => vaddress_RNIQFAKMI(13), - vaddress_RNIOFAKMI(12) => vaddress_RNIOFAKMI(12), - un1_p0_2_i_4 => un1_p0_2_i_4, un1_p0_2_i_0 => - un1_p0_2_i_0, faddr_RNIDN2CUE(6) => faddr_RNIDN2CUE(6), - faddr_RNI7UFASD(5) => faddr_RNI7UFASD(5), - faddr_RNI0FOJNE(4) => faddr_RNI0FOJNE(4), - faddr_RNIUT72LB(3) => faddr_RNIUT72LB(3), - faddr_RNISJSHQA(2) => faddr_RNISJSHQA(2), - faddr_RNIKVTLT9(1) => faddr_RNIKVTLT9(1), - faddr_RNI7H6KT8(0) => faddr_RNI7H6KT8(0), un1_p0_2_0(148) - => un1_p0_2_0_0, vitdatain_0_1_0(22) => - \vitdatain_0_1_0[22]\, flush2_RNI5I3N7 => flush2_RNI5I3N7, - syncramZ2_VCC => cachemem_VCC, flush2_0_0_RNI7G6O2 => - flush2_0_0_RNI7G6O2, flush2_RNIFMGM2 => flush2_RNIFMGM2, - flush2_0_0_RNI146O2 => flush2_0_0_RNI146O2, - flush2_0_0_RNIVV5O2 => flush2_0_0_RNIVV5O2, - flush2_0_0_RNITR5O2 => flush2_0_0_RNITR5O2, - flush2_0_0_RNIPJ5O2 => flush2_0_0_RNIPJ5O2, lclk_c => - lclk_c, N_984 => N_984, N_987 => N_987, flush2 => flush2, - N_986 => N_986, N_985 => N_985, un1_ici => un1_ici, N_982 - => N_982, N_983 => N_983, N_981 => N_981, N_980 => N_980); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity iu3 is - - port( asi_0 : out std_logic_vector(4 downto 0); - wdata : out std_logic_vector(31 downto 0); - size_0_1 : out std_logic; - size_1_0 : out std_logic; - rdatav_0_1_1_iv_7 : in std_logic_vector(6 to 6); - rdatav_0_1_0_iv_7 : in std_logic_vector(2 to 2); - rdatav_0_1_0_iv_0_2 : in std_logic_vector(10 to 10); - rdatav_0_1_0_iv_5_4 : in std_logic; - rdatav_0_1_0_iv_5_1 : in std_logic; - rdatav_0_1_0_iv_5_0 : in std_logic; - rdatav_0_1_0_iv_5_6 : in std_logic; - waddr : out std_logic_vector(7 downto 0); - rfa2 : out std_logic_vector(7 downto 0); - raddr2 : out std_logic_vector(7 downto 0); - rfa1 : out std_logic_vector(7 downto 0); - raddr1 : out std_logic_vector(7 downto 0); - data_0_2_13 : in std_logic; - data_0_2_14 : in std_logic; - data_0_2_17 : in std_logic; - data_0_2_16 : in std_logic; - data_0_2_8 : in std_logic; - data_0_2_24 : in std_logic; - data_0_2_31 : in std_logic; - data_0_2_30 : in std_logic; - data_0_2_29 : in std_logic; - data_0_2_28 : in std_logic; - data_0_2_27 : in std_logic; - data_0_2_26 : in std_logic; - data_0_2_25 : in std_logic; - data_0_2_21 : in std_logic; - data_0_2_4 : in std_logic; - data_0_2_0 : in std_logic; - edata2_iv_i_0 : out std_logic_vector(31 downto 24); - rpc_6 : out std_logic; - rpc_8 : out std_logic; - rpc_5 : out std_logic; - rpc_7 : out std_logic; - rpc_2 : out std_logic; - rpc_0 : out std_logic; - rpc_1 : out std_logic; - rpc_3 : out std_logic; - irl_0 : in std_logic_vector(3 downto 0); - irl : out std_logic_vector(3 downto 0); - data2 : in std_logic_vector(31 downto 0); - mcdo_m_0_27 : in std_logic; - mcdo_m_0_29 : in std_logic; - mcdo_m_0_4 : in std_logic; - mcdo_m_0_20 : in std_logic; - mcdo_m_0_17 : in std_logic; - mcdo_m_0_0 : in std_logic; - mcdo_m_0_16 : in std_logic; - mcdo_m_0_7 : in std_logic; - mcdo_m_0_22 : in std_logic; - mcdo_m_0_21 : in std_logic; - rdatav_0_1_0_iv_4_20 : in std_logic; - rdatav_0_1_0_iv_4_22 : in std_logic; - rdatav_0_1_0_iv_4_0 : in std_logic; - rdatav_0_1_0_iv_4_14 : in std_logic; - maddress : out std_logic_vector(31 downto 0); - data1 : in std_logic_vector(31 downto 0); - un1_p0_6_0 : out std_logic; - edata2_0_iv : out std_logic_vector(23 downto 0); - fpc : out std_logic_vector(31 downto 2); - data_0_0_15 : in std_logic; - data_0_0_20 : in std_logic; - data_0_0_11 : in std_logic; - data_0_0_6 : in std_logic; - data_0_0_23 : in std_logic; - data_0_0_19 : in std_logic; - data_0_0_17 : in std_logic; - data_0_0_16 : in std_logic; - data_0_0_14 : in std_logic; - data_0_0_13 : in std_logic; - data_0_0_12 : in std_logic; - data_0_0_10 : in std_logic; - data_0_0_9 : in std_logic; - data_0_0_7 : in std_logic; - data_0_0_5 : in std_logic; - data_0_0_3 : in std_logic; - data_0_0_2 : in std_logic; - data_0_0_1 : in std_logic; - data_0_0_0 : in std_logic; - data_0_0_4 : in std_logic; - data_0_0_26 : in std_logic; - data_0_0_8 : in std_logic; - data_0_0_28 : in std_logic; - data_0_0_27 : in std_logic; - data_0_0_30 : in std_logic; - data_0_0_25 : in std_logic; - data_0_0_24 : in std_logic; - data_0_0_21 : in std_logic; - eaddress_4 : out std_logic; - eaddress_2 : out std_logic; - eaddress_12 : out std_logic; - eaddress_24 : out std_logic; - eaddress_5 : out std_logic; - eaddress_11 : out std_logic; - eaddress_30 : out std_logic; - eaddress_6 : out std_logic; - eaddress_3 : out std_logic; - eaddress_27 : out std_logic; - eaddress_31 : out std_logic; - eaddress_15 : out std_logic; - eaddress_17 : out std_logic; - eaddress_20 : out std_logic; - eaddress_18 : out std_logic; - eaddress_26 : out std_logic; - eaddress_14 : out std_logic; - eaddress_21 : out std_logic; - eaddress_25 : out std_logic; - eaddress_29 : out std_logic; - eaddress_19 : out std_logic; - eaddress_23 : out std_logic; - eaddress_22 : out std_logic; - eaddress_9 : out std_logic; - eaddress_10 : out std_logic; - eaddress_7 : out std_logic; - eaddress_8 : out std_logic; - data_0_22 : in std_logic; - data_0_20 : in std_logic; - data_0_18 : in std_logic; - data_0_15 : in std_logic; - data_0_11 : in std_logic; - data_0_7 : in std_logic; - data_0_12 : in std_logic; - data_0_31 : in std_logic; - data_0_29 : in std_logic; - dco_i_2 : in std_logic_vector(132 to 132); - maddress_0_2 : out std_logic; - maddress_0_0 : out std_logic; - msu : out std_logic; - error_i_2 : out std_logic; - read_1 : out std_logic; - write_0 : out std_logic; - mexc_2 : in std_logic; - enaddr : out std_logic; - eenaddr : out std_logic; - N_26 : out std_logic; - lock : out std_logic; - N_28 : out std_logic; - su_0 : out std_logic; - rfe2 : out std_logic; - ren2 : out std_logic; - mexc : in std_logic; - N_3305_0 : in std_logic; - intack_2 : out std_logic; - wren : out std_logic; - rfe1 : out std_logic; - ren1 : out std_logic; - werr_2 : in std_logic; - rstate_1188n : in std_logic; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : in std_logic; - ldlock_3_0 : out std_logic; - rst_RNIINI1H : in std_logic; - rbranch : out std_logic; - r_N_6 : out std_logic; - un1_addout_12 : out std_logic; - flush_i_0 : out std_logic; - N_3389_i_0 : in std_logic; - N_3227_i_0 : in std_logic; - N_3387_i_0 : in std_logic; - nullify : out std_logic; - ldlock_2 : out std_logic; - fbranch : out std_logic; - d_m5_0_a3_2 : out std_logic; - hold_pc_7 : out std_logic; - nullify2_0_sqmuxa : out std_logic; - me_nullify2_1_2 : out std_logic; - un9_icc_check_bp : out std_logic; - inull : out std_logic; - de_hold_pc_1 : out std_logic; - rst : in std_logic; - un17_casaen_0_0 : out std_logic; - xc_exception_1_0 : out std_logic; - mds : in std_logic; - ra_bpmiss_1_0 : out std_logic; - read_0 : out std_logic; - holdn : in std_logic; - lclk_c : in std_logic - ); - -end iu3; - -architecture DEF_ARCH of iu3 is - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO16 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI4 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_p0_6_0[51]\, \inst_0_0_0_RNI7TVIO2[12]\, - \un1_p0_6_0[60]\, \inst_0_0_0_RNIQ98I03[21]\, \eres2[1]\, - \eres2[3]\, read, wy_0, wy, \npc_0[0]\, \npc_1[0]\, - \npc_1[1]\, \npc_1_0[1]\, \npc_0[1]\, \rsel2_1[0]\, - N_3944, \rsel2_0[0]\, \aluop_0[0]\, \aluop[0]\, - \aluop_2[1]\, \aluop[1]\, \aluop_1[1]\, \aluop_0[1]\, - \aluop_0[2]\, \aluop[2]\, \rsel1_0[2]\, rs1, ldbp2_2, - ldbp2, ldbp2_1, ldbp2_0, invop2_1, N_6680, invop2_0, - mulstep_0, mulstep, ld_0, ld, ldbp1_4, ldbp, ldbp1_3, - ldbp1_2, ldbp1_1, ldbp1_0, y08_0, wy_1, d27_0, d28_0_0, - wy_1_0, wy_2, y14_0, shleft_1, N_208, shleft_0, - edata_3_sqmuxa_0, un1_logicout21, un17_casaen_0, - ex_bpmiss_1_0, ex_bpmiss_1_0_1, ex_bpmiss_1_0_2, - ra_bpmiss_1_1, branch, jump_0, jump_1_sqmuxa_1_i_0, - jump_0_sqmuxa_1_i_0, annul, de_hold_pc_1_0, - un2_rstn_5_0_i, un18_hold_pc, un2_rstn_3_0, - un12_de_hold_pc, un2_rstn_4_0_0, un2_rstn_4_0, - un2_rstn_5_2, un2_rstn_5_0, \un2_rstn_5_0_0\, - mexc_1_sqmuxa_1_0, un14_casaen_s0_0_1, d26, - un17_casaen_0_2, \rstate_0[0]\, N_6322s, s_3_sqmuxa_0, - \rstate_d[2]\, xc_wreg9, rstate_6314_d_0, \rstate[1]\, - N_481_0, y_1_sqmuxa_1, y_1_sqmuxa_0, d25_0, d26_0, - un14_casaen_s1_0_1, d31_0, \rsel2[2]\, \rsel2[1]\, - aluresult_7_sqmuxa_0_0, aluresult_7_sqmuxa_0, - logicout21_1, ld_0_0, mexc_1_sqmuxa_0, - aluresult_10_sqmuxa_0, miscout69, logicout20, - aluresult_9_sqmuxa_1, aluresult_12_sqmuxa_0_0, - aluresult_12_sqmuxa_0, aluresult_12_sqmuxa_4, - aluresult_12_sqmuxa_5, aluresult_1_sqmuxa_0, jmpl, - aluresult_1_sqmuxa_0_0, \ex_shcnt_1[0]\, ex_sari_1_1_0_0, - sari, ex_sari_1, aluresult_2_sqmuxa_0, jmpl_0, - miscout_11_sqmuxa, aluresult_0_sqmuxa_0, aluresult12, - aluresult_3_sqmuxa_0, \alusel[1]\, \alusel[0]\, d14_0, - \rsel1[0]\, \rsel1[1]\, bpdata6_0_0, bpdata6_8, bpdata6_7, - bpdata6_9, d13_0, N_484, un14_casaen_s1_0_0, N_494, - un14_casaen_s0_0_0, d11_0, d11_0_a5_0, N_227_0, N_226, - N_203, N_204, un1_aop2_1_sqmuxa_0, N_457, N_456, N_458, - N_484_0, call_hold5_0, \inst_0[31]\, \inst_0[30]\, casa, - N_3355_1, un17_casaen_0_1, \ex_shcnt_1_i_0[1]\, - \shcnt[1]\, N_3305, \ex_shcnt_1_i_0[2]\, \shcnt[2]\, - N_3306, \ex_shcnt_1_i_0[3]\, \shcnt[3]\, N_3307, - \ex_shcnt_1_i_0[4]\, \shcnt[4]\, N_3308, bpmiss_1_i_0_0, - \ra_bpmiss_1_0\, N_6763_i_0, N_6922_i_0, wy_RNILF1N3, - N_6866_i_0, N_6697_i_0_0, N_451, \aop2_i_o2_2[0]\, N_452, - wy_1_0_0, d29_0_0, \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_TMP[0]\, \ncwp[1]\, - \DWACT_ADD_CI_0_g_array_1_0[0]\, - \DWACT_ADD_CI_0_TMP_0[0]\, \cwp[1]\, - \DWACT_ADD_CI_0_g_array_1_1[0]\, - \DWACT_ADD_CI_0_TMP_1[0]\, - \DWACT_ADD_CI_0_g_array_1_2[0]\, - \DWACT_ADD_CI_0_TMP_2[0]\, N_147, \fe_pc[3]\, \fe_pc[2]\, - N_139, \fe_pc[5]\, \DWACT_FINC_E[0]\, N_116, \fe_pc[10]\, - \DWACT_FINC_E[4]\, N_101, \DWACT_FINC_E[7]\, - \DWACT_FINC_E[6]\, \un6_ex_add_res_s2_1[26]\, - \data_0[25]\, \un1_iu0_6[25]\, \un6_ex_add_res_s2[26]\, - N776, \un6_ex_add_res_s0[26]\, N776_0, N814, I249_un1_Y_i, - N668, \dco_m_0[125]\, rdata_5_sqmuxa, I157_un1_Y_i, - N561_i, N568, \un6_ex_add_res_s0[31]\, N766, - \un6_ex_add_res_s2_1[31]\, \un6_ex_add_res_s2[31]\, - N766_0, \data_0[30]\, \un1_iu0_6[30]\, N495, N_50, N485_i, - \op2[29]\, \un1_iu0_6[29]\, N482, \un1_iu0_6[28]\, - \data_0[28]\, \data_0_1_2[17]\, \rdata_5_m_9[8]\, - \rdata_13_m_9[8]\, \un6_ex_add_res_s2_1[30]\, - \data_0_0[29]\, N485_i_0, N484, N479, \un1_iu0_6[27]\, - \data_0[27]\, N488, rd_0_i_0, \rd[0]\, \rd_0[0]\, N527, - N434, N437, \annul_current_3_sqmuxa_1\, un5_exbpmiss_i_0, - call_hold7_i, \un6_ex_add_res_s2[25]\, N778, - \un6_ex_add_res_s2_1[25]\, \un6_ex_add_res_s0[25]\, - N778_0, \dco_m_0[127]\, \tmp_m[22]\, \tmp[22]\, - \un6_ex_add_res_m_1[9]\, \un6_ex_add_res_s2_1[27]\, - \data_0[26]\, \un1_iu0_6[26]\, N476, \op2[26]\, N_74_i, - N782, N_15_i, N506, N467, N464, I33_un1_Y, \data_0[24]\, - \un1_iu0_6[24]\, N470, \op2[24]\, N566_i, I103_un1_Y_i, - N500, N506_0, N_74, N493, N497, N495_0, N811, - I248_un1_Y_i, N666, N473, \op2[25]\, - \un6_ex_add_res_s0[28]\, N772, \un6_ex_add_res_s2_1[28]\, - \un6_ex_add_res_s2[28]\, N772_0, I33_un1_Y_0, N484_0, - N488_0, \op2[30]\, \un6_ex_add_res_s2[15]\, N799, - \un6_ex_add_res_s2_1[15]\, \data_0[14]\, \un1_iu0_6[14]\, - I244_un1_Y, N658, \un6_ex_add_res_s0[22]\, N784, - \un6_ex_add_res_s2_1[22]\, \un6_ex_add_res_s2[22]\, - N784_0, \data_0[21]\, \un1_iu0_6[21]\, - \un6_ex_add_res_s0[9]\, N817, \un6_ex_add_res_s2_1[9]\, - \un6_ex_add_res_s2[9]\, N817_0, \data_0[8]\, - \un1_iu0_6[8]\, N418, N_62, N418_0, - ADD_33x33_fast_I250_Y_0_a3_0, \un6_ex_add_res_s2_1[11]\, - \data_0[10]\, \un1_iu0_6[10]\, N524, I65_un1_Y, N439, - N436, N440, \un6_ex_add_res_s0[24]\, N780, - \un6_ex_add_res_s2_1[24]\, \un6_ex_add_res_s2[24]\, - N780_0, \data_0[23]\, \un1_iu0_6[23]\, N413, \data_0[5]\, - \un1_iu0_6[5]\, I231_un1_Y_i, N645, N660, N413_0, - \dco_m_i[117]\, N_3455, miscout140, miscout140_1, - \un6_ex_add_res_s2[30]\, N768, \un6_ex_add_res_s2[27]\, - N774, \un6_ex_add_res_s2[11]\, N811_0, N_74_1, N464_0, - N467_0, \un6_ex_add_res_s0[30]\, N768_0, - \un6_ex_add_res_s0[27]\, N774_0, \un6_ex_add_res_s0[11]\, - \shiftin_17_m[15]\, \shiftin_17[15]\, \tmp_m[29]\, - \tmp[29]\, \shiftin_17_m[7]\, \shiftin_17[7]\, - \bpdata_m_2[0]\, aluresult_4_sqmuxa, \bpdata[0]\, - \bpdata_m_1[3]\, N_3957_1, \bpdata[3]\, \bpdata_m[19]\, - aluresult_6_sqmuxa, \bpdata[19]\, \tba_m[7]\, \tba[7]\, - \tmp_m[19]\, \tmp[19]\, \tmp_m[23]\, \tmp[23]\, N501, - N525, N437_0, N_72, N463, N817_i, N418_1, - ADD_33x33_fast_I250_Y_0_a3, N506_1, N466, N416, - \un1_iu0_6[6]\, \data_0[6]\, I248_un1_Y, N666_0, N541, - CO0, \cwp[0]\, \rstate_RNIRDFU5[1]\, rdata199, - \me_size_1[0]\, \me_size_1[1]\, \tmp_m[4]\, \tmp[4]\, - \ex_op1_i_m[26]\, \bpdata_i_m[2]\, N_3687, \bpdata[2]\, - \shiftin_17_m[21]\, \shiftin_17[21]\, \tmp_m[16]\, - \tmp[16]\, N505, \op2[13]\, \un1_iu0_6[13]\, \op2[14]\, - \op2[22]\, \un1_iu0_6[22]\, \op2[23]\, N527_0, N434_0, - I105_un1_Y, N502, I165_un1_Y, N569, N576, N503, N493_0, - \dco_m_i[108]\, rdata_2_sqmuxa, \data_0_m_i[4]\, - \data_0[4]\, \dco_m_0_i[120]\, \aluresult_m_i[29]\, - \aluresult[29]\, N401, \data_0[1]\, \un1_iu0_6[1]\, - N644_i, N578, I175_un1_Y, N416_0, I163_un1_Y, N567, N574, - N541_0, \op2[12]\, \un1_iu0_6[12]\, I45_un1_Y, \pc_m[8]\, - \wovf_exc_0_sqmuxa_1\, un7_op, \wovf_exc_0_sqmuxa\, - \wovf_exc_1_sqmuxa\, trap, un1_annul, trap_0, icc_check5, - N_145, ticc_exception_1, un6_xc_exception, - \xc_exception_1_0\, \tmp_m[25]\, \tmp[25]\, \tmp_m[8]\, - \tmp[8]\, N428, \inst_0_1[25]\, \dpc[25]\, N377, - \inst_0[6]\, \dpc[8]\, N376_i, N586_i, I160_un1_Y_i, N526, - \tmp_m[15]\, \tmp[15]\, N_6619, \tmp[14]\, \tmp_m[5]\, - \tmp[5]\, \tmp_m[28]\, \tmp[28]\, \tmp_m[10]\, \tmp[10]\, - \tmp_m[12]\, \tmp[12]\, \tmp_m[17]\, \tmp[17]\, - \un2_rstn_5\, \tmp_m[31]\, \tmp[31]\, \tmp_m[13]\, - \tmp[13]\, \tmp_m[20]\, \tmp[20]\, N_39, \tmp[6]\, - \tmp_m[30]\, \tmp[30]\, \tmp_m[26]\, \tmp[26]\, N_6620, - \tmp[11]\, \tmp_m[27]\, \tmp[27]\, N492, N374, - ADD_30x30_fast_I40_Y_0_a3, N424, \dpc[24]\, - \inst_0_0_0_RNI9O79[21]\, N431, \inst_0_1[26]\, \dpc[26]\, - N456, \tmp[2]\, \dpc[2]\, \inst_0_RNI0FUM[0]\, un8_op, - un25_op, \tmp_m[21]\, \tmp[21]\, \tmp_m[3]\, \tmp[3]\, - \un6_fe_npc_m[1]\, I_5, \op1_RNI3RNF[26]\, - \un17_casaen_0_0\, \op1[26]\, \tmp_m[2]\, \op1_i_m[17]\, - \op1[17]\, \bpdata_i_m[17]\, edata_2_sqmuxa, \bpdata[17]\, - \tmp_m[7]\, \tmp[7]\, N_142, wy_1_0_a3_1_0, N373, - \dpc[7]\, \inst_0[5]\, I74_un1_Y_i, N491, N776_1, - I265_un1_Y_i, ADD_33x33_fast_I265_Y_1, I265_un1_Y_i_0, - ADD_33x33_fast_I265_Y_1_0, \un6_ex_add_res_s1_i[26]\, - ADD_33x33_fast_I316_Y_0_0, I260_un1_Y_i, - ADD_33x33_fast_I260_Y_3, I260_un1_Y_i_0, - ADD_33x33_fast_I260_Y_3_0, I263_un1_Y, - ADD_33x33_fast_I263_Y_1, I229_un1_Y, - ADD_33x33_fast_I268_Y_0, ADD_33x33_fast_I260_un1_Y_0, - I269_un1_Y_i, ADD_33x33_fast_I269_Y_0, - aluresult_11_sqmuxa_5_0, \un6_ex_add_res_s1[10]\, - ADD_33x33_fast_I300_Y_0_0, \data_0_1[16]\, - \data_0_1_1_iv_1[16]\, \data_0_1[31]\, - \data_0_1_1_iv_1[31]\, N593, ADD_33x33_fast_I130_Y_0, - enaddr_1_sqmuxa_1, enaddr_1_sqmuxa_1_1, N712_i, - ADD_30x30_fast_I280_Y_0_0, I265_un1_Y_i_1, - ADD_33x33_fast_I265_Y_1_1, ADD_33x33_fast_I265_un1_Y_0, - \edata2_0_iv_0[2]\, N698, ADD_30x30_fast_I287_Y_0_0, N710, - ADD_30x30_fast_I281_Y_0_0, N718_i, - ADD_30x30_fast_I277_Y_0_0, N726_i, - ADD_30x30_fast_I274_Y_0_0, N501_0, - ADD_30x30_fast_I262_Y_0_0, \un6_ex_add_res_s1_i[30]\, - N768_1, ADD_33x33_fast_I320_Y_0_0, \d_1[29]\, - \d_1_iv_4[29]\, \data_0_1[19]\, \data_0_1_1_iv_1[19]\, - \un6_ex_add_res_s1[9]\, ADD_33x33_fast_I299_Y_0_0, - \un6_ex_add_res_s1_i[24]\, N780_1, - ADD_33x33_fast_I314_Y_0_0, I267_un1_Y, - ADD_33x33_fast_I267_Y_0, I267_un1_Y_0, - ADD_33x33_fast_I267_Y_0_0, N_57_i, - ADD_33x33_fast_I206_Y_0_a3_1_0, I263_un1_Y_0, - ADD_33x33_fast_I263_Y_1_0, I261_un1_Y, - ADD_33x33_fast_I261_Y_2, I264_un1_Y, - ADD_33x33_fast_I264_un1_Y_0, ADD_33x33_fast_I264_Y_1, - I261_un1_Y_0, ADD_33x33_fast_I261_Y_2_0, I261_un1_Y_1, - ADD_33x33_fast_I261_Y_2_1, I269_un1_Y, - ADD_33x33_fast_I269_Y_0_0, I264_un1_Y_0, - ADD_33x33_fast_I264_un1_Y_0_0, ADD_33x33_fast_I264_Y_1_0, - I267_un1_Y_1, ADD_33x33_fast_I267_Y_0_1, N706, - ADD_30x30_fast_I283_Y_0_0, N614, - ADD_30x30_fast_I265_Y_0_0, N556_i, - ADD_30x30_fast_I264_Y_0_0, N358, - ADD_30x30_fast_I261_Y_0_0, N729, - ADD_30x30_fast_I273_Y_0_0, N732_i, - ADD_30x30_fast_I272_Y_0_0, N558, - ADD_30x30_fast_I263_Y_0_0, N700, - ADD_30x30_fast_I286_Y_0_0, un1_icc_check5, - un1_icc_check5_2, ldchkra, ldchkra_0, N612, - ADD_30x30_fast_I266_Y_0_0, N_6528, SUM1_0_0, N694, - ADD_30x30_fast_I289_Y_0_0, N696, - ADD_30x30_fast_I288_Y_0_0, N702_i, - ADD_30x30_fast_I285_Y_0_0, N704, - ADD_30x30_fast_I284_Y_0_0, N714, - ADD_30x30_fast_I279_Y_0_0, N716, - ADD_30x30_fast_I278_Y_0_0, N723, - ADD_30x30_fast_I275_Y_0_0, N735, - ADD_30x30_fast_I271_Y_0_0, N738, - ADD_30x30_fast_I270_Y_0_0, N741, - ADD_30x30_fast_I269_Y_0_0, N608_i, - ADD_30x30_fast_I268_Y_0_0, I242_un1_Y, - ADD_30x30_fast_I242_un1_Y_0, \pc_1[3]\, \pc_1_iv_2[3]\, - \xc_trap_address_m[2]\, \xc_trap_address_m_0[2]\, - \xc_trap_address_m[3]\, \xc_trap_address_m_0[3]\, - \npc_iv_1[8]\, N398, alucin, bpdata6_1, bpdata6_0, wreg, - annul_0, \inst[19]\, \edata2_iv_0[26]\, et_RNI1BRF2, - \cwp_0[1]\, N431_0, N428_0, un1_icc_check5_1, imm9, - \edata2_0_iv_0[17]\, N651, N635, \un1_iu0_6[9]\, \op2[9]\, - N651_0, N635_0, N653, N637, G_6_1, G_6_0, - annul_current_2_sqmuxa_1, annul_1, - ADD_33x33_fast_I264_Y_0, N627, N643, \ex_op1_i_m[2]\, - \op1_i_m[2]\, \op2[8]\, ADD_33x33_fast_I263_Y_0, - ADD_30x30_fast_I242_Y_0, \aluresult_1_iv_8[6]\, - \aluresult_1_iv_7[6]\, \aluresult_1_iv_6[6]\, - \bpdata_m[6]\, ldlock2_1, ldlock2_0, wreg_0, ld_1, - \aluresult_1_iv_5[8]\, \aluresult_1_iv_3[8]\, \tt_m[4]\, - \aluresult_1_iv_1[8]\, \aluresult_1_iv_5[24]\, - \aluresult_1_iv_3[24]\, \aluresult_1_iv_1[24]\, - \tba_m[12]\, \aluresult_1_iv_8[20]\, - \aluresult_1_iv_7[20]\, \aluresult_1_iv_6[20]\, - \logicout_m_0[20]\, \aluresult_1_iv_8[14]\, - \aluresult_1_iv_7[14]\, \aluresult_1_iv_6[14]\, - \logicout_m_0[14]\, \aluresult_1_iv_5[19]\, - \aluresult_1_iv_4[19]\, \aluresult_1_iv_3[19]\, - \aluresult_1_iv_2[19]\, \data_0_1_0_iv_0[8]\, - \data_0_m_i[8]\, \data_0_1_1[16]\, \data_0_1_1_iv_0[31]\, - \data_0_1_1_iv_0[16]\, \data_0_1_1_iv_0[19]\, - rdata_2_sqmuxa_1, rdata_2_sqmuxa_0, \me_laddr_2[1]\, - \me_laddr_2[0]\, rdata_1_sqmuxa_1, rdata_1_sqmuxa_0, - enaddr_1_sqmuxa_1_0, \cnt[1]\, \op1_m_i[29]\, - \d_1_iv_3[29]\, \data_0_1_0_iv_0[13]\, \data_0_m[13]\, - \data_0_1_0_iv_0[15]\, \data_0_m[15]\, - \data_0_1_1_iv_2[5]\, \data_0_1_1_iv_1[5]\, - \data_0_1_1_iv_0[5]\, \dco_m_i[125]\, - \data_0_1_1_iv_0[4]\, \pc_1_iv_1[3]\, \pc_1_iv_1[4]\, - \pc_4_m[4]\, \xc_trap_address_m[4]\, - \un6_ex_add_res_m_1[5]\, \pc_1_iv_1[7]\, \pc_1_iv_0[7]\, - \pc_4[7]\, \xc_trap_address_m[7]\, \pc_1_iv_1[10]\, - \pc_1_iv_0[10]\, \pc_4[10]\, \xc_trap_address_m[10]\, - \pc_1_iv_2[5]\, \un6_ex_add_res_m_1[6]\, \pc_1_iv_0[5]\, - \pc_4[5]\, \xc_trap_address_m[5]\, \pc_1_iv_1[8]\, - \eaddress[8]\, \pc_1_iv_0[8]\, \pc_4[8]\, - \xc_trap_address_m[8]\, \pc_1_iv_2[2]\, - \un6_ex_add_res_m[3]\, \pc_1_iv_0[2]\, \pc_4_m[2]\, - \pc_1_iv_1[9]\, \pc_1_iv_0[9]\, \xc_trap_address_m[9]\, - \pc_4_m[9]\, \pc_4_m[3]\, \un6_ex_add_res_m_1[4]\, - \pc_1_iv_1[22]\, \pc_1_iv_0[22]\, \pc_4[22]\, - \xc_trap_address_m[22]\, \pc_1_iv_1[24]\, \pc_4_m[24]\, - \xc_trap_address_m[24]\, \un6_ex_add_res_m_1[25]\, - \pc_1_iv_1[23]\, \pc_1_iv_0[23]\, \pc_4[23]\, - \xc_trap_address_m[23]\, \pc_1_iv_1[19]\, \pc_1_iv_0[19]\, - \pc_4[19]\, \xc_trap_address_m[19]\, \pc_1_iv_1[16]\, - \eaddress[16]\, \pc_1_iv_0[16]\, \pc_4[16]\, - \xc_trap_address_m[16]\, \pc_1_iv_1[29]\, \pc_1_iv_0[29]\, - \pc_4[29]\, \xc_trap_address_m[29]\, \pc_1_iv_1[25]\, - \pc_1_iv_0[25]\, \pc_4[25]\, \xc_trap_address_m[25]\, - \pc_1_iv_1[28]\, \eaddress[28]\, \pc_1_iv_0[28]\, - \pc_4[28]\, \xc_trap_address_m[28]\, \pc_1_iv_1[21]\, - \pc_1_iv_0[21]\, \pc_4[21]\, \xc_trap_address_m[21]\, - m7_1, m7_0, \pc_4[14]\, \xc_trap_address_m[14]\, - \pc_1_iv_2[27]\, \un6_ex_add_res_m_1[28]\, - \pc_1_iv_0[27]\, \pc_4[27]\, \xc_trap_address_m[27]\, - m14_2, N_9, m14_0, N_31, \pc_4[11]\, - \xc_trap_address_m[11]\, \pc_1_iv_1[26]\, \pc_1_iv_0[26]\, - \pc_4[26]\, \xc_trap_address_m[26]\, \pc_1_iv_1[30]\, - \pc_4_m[30]\, \xc_trap_address_m[30]\, - \un6_ex_add_res_m_1[31]\, \pc_1_iv_1[18]\, - \pc_1_iv_0[18]\, \pc_4[18]\, \xc_trap_address_m[18]\, - \pc_1_iv_2[12]\, \un6_ex_add_res_m_1[13]\, - \pc_1_iv_0[12]\, \pc_4[12]\, \xc_trap_address_m[12]\, - \pc_1_iv_1[13]\, \eaddress[13]\, \pc_1_iv_0[13]\, - \pc_4[13]\, \xc_trap_address_m[13]\, \pc_1_iv_1[20]\, - annul_RNI5L7FE1, \pc_1_iv_0[20]\, \pc_4[20]\, - \xc_trap_address_m[20]\, \pc_1_iv_1[17]\, \pc_1_iv_0[17]\, - \pc_4[17]\, \xc_trap_address_m[17]\, \pc_1_iv_1[15]\, - \pc_1_iv_0[15]\, \pc_4[15]\, \xc_trap_address_m[15]\, - \pc_1_iv_1[31]\, \pc_1_iv_0[31]\, \de_hold_pc_1\, - \pc_4[31]\, \xc_trap_address_m[31]\, m21_2, - ldbp2_2_RNIFB78T1, m21_0, \pc_4[6]\, - \xc_trap_address_m[6]\, cnt_3_sqmuxa_0, ldlock, - hold_pc_2_sqmuxa, cnt_2_sqmuxa_0, hold_pc_0_sqmuxa_1, - pv_3, un6_rabpmiss_2, N_4240, pv_2, N_4241_i_0, pv_0, - N_4242, un23_exbpmiss_i_0, un9_rabpmiss, - un1_annul_next_1_sqmuxa_3_3, annul_next_1_sqmuxa_1_6, - un1_annul_next_1_sqmuxa_3_2, un1_annul_next_1_sqmuxa_3_0, - un25_exbpmiss, annul_next_2_sqmuxa_1_8, un13_exbpmiss_0, - annul_next_2_sqmuxa_1_6, annul_next_2_sqmuxa_1_5, - annul_next_2_sqmuxa_1_3, annul_next_2_sqmuxa_1_2, N_108, - un19_inst, annul_next_2_sqmuxa_1_0, \data_0_1_0_iv_0[9]\, - \data_0_m[9]\, \data_0_1_0_iv_0[14]\, \data_0_m[14]\, - \data_0_1_0_iv_0[11]\, \data_0_m[11]\, - \data_0_1_0_iv_0[12]\, \data_0_m[12]\, branch_0, - un6_rabpmiss_0, pv, \inst[29]\, \dco_m_i[109]\, - \data_0_1_1_iv_1[7]\, \dco_m_i[111]\, \data_0_m_i[7]\, - \dco_m_i[127]\, \data_0_1_1_iv_2[0]\, - \data_0_1_1_iv_0[0]\, \dco_m_i[120]\, \dco_m_i[112]\, - \data_0_m_i[0]\, \data_0_1_1_iv_2[1]\, - \data_0_1_1_iv_0[1]\, \dco_m_i[121]\, \dco_m_i[113]\, - \dco_m_i[105]\, \data_0_1_1_iv_1[2]\, rdata_0_sqmuxa, - \data_0_1_1_iv_0[2]\, \data_0[2]\, \dco_m_i[106]\, - \data_0_1_1_iv_2[3]\, \data_0_1_1_iv_0[3]\, - \dco_m_i[123]\, \dco_m_i[115]\, \data_0[3]\, - \dco_m_i[107]\, \data_0_1_1_iv_2[4]\, \dco_m_i[124]\, - \dco_m_i[116]\, \data_0_1_1_iv_1[6]\, \dco_m_i[110]\, - \data_0_m_i[6]\, \dco_m_i[126]\, \data_0_1_0_iv_1[8]\, - \rdata_13_m[8]\, \rdata_17_m[8]\, \data_0_1_0_iv_1[10]\, - \data_0_1_0_iv_0[10]\, \data_0_m_i[10]\, annul_2, - \data_0_0[31]\, \dco_m_1[127]\, \data_0[16]\, - \dco_m_0[112]\, \data_0_1_1_iv_1[17]\, \dco_m_0[113]\, - \data_0_m[17]\, \data_0[19]\, \dco_m_0[115]\, cin_iv_i_2, - alucin_RNO_2, N_350, cin_iv_i_0, \inst[30]\, \inst[31]\, - bp_1_0, not_valid, \data_0_1_1_iv_1[24]\, - \data_0_m_i[24]\, \dco_m_1_i[120]\, cin_iv_i_a5_0, - \inst[22]\, ctrl_annul_i_0_a2_0, inhibit_current, - annul_current_0, annul_current_4, \icc_12_iv_0[1]\, - \icc_7_m_2[1]\, \icc_7[1]\, \icc_2_m[1]\, pv_12_i_a6_0_2, - pv_12_i_a6_0_1, \cnt_0[1]\, annul_next_1_sqmuxa_1_4, - hold_pc_1_sqmuxa, annul_next_1_sqmuxa_1_1, - annul_next_1_sqmuxa_1_0, annul_next_1_sqmuxa_1_2, - \inst_0[28]\, \inst_0[29]\, \inst_0[25]\, \inst_0[27]\, - \inull\, \inst_0[26]\, me_nullify2_1_0, \d_iv_2[31]\, - \d_iv_1[31]\, \result_m_0[31]\, \cpi_m_0[383]\, - \result_m_0_0[31]\, \d_1_iv_3[31]\, \d_1_iv_1[31]\, - \d_1_iv_0[31]\, \rfo_m_i[63]\, \cpi_m_i[383]\, - \result[31]\, \imm_m_i[31]\, \icc_8_m_1[1]\, \inst[24]\, - un3_notag, \icc_7_m_0[1]\, \icc_8_m_5[1]\, - \rdata_9_m_0[8]\, me_signed_1, \d_1_iv_3[16]\, - \d_1_iv_1[16]\, \d_1_iv_0[16]\, \rfo_m_i[48]\, - \cpi_m_i[368]\, \result[16]\, \imm_m_i[16]\, \d_iv_2[16]\, - \d_iv_0[16]\, \result_m_0[16]\, \rfo_m[16]\, - \un1_p0_6[368]\, \result_m_0_0[16]\, \d_1_iv_3[28]\, - \d_1_iv_1[28]\, \d_1_iv_0[28]\, \rfo_m_i[60]\, - \cpi_m_i[380]\, \result[28]\, \imm_m_i[28]\, \d_iv_3[28]\, - \rfo_m[28]\, \d_iv_1[28]\, \op1_m_0[28]\, - \result_m_0[28]\, \cpi_m_0[380]\, \result_m_0_0[28]\, - \d_1_iv_3[15]\, \d_1_iv_1[15]\, \d_1_iv_0[15]\, - \rfo_m_i[47]\, \cpi_m_i[367]\, \result[15]\, - \imm_m_i[15]\, \d_iv_2[15]\, \d_iv_0[15]\, - \result_m_0[15]\, \rfo_m[15]\, \un1_p0_6[367]\, - \result_m_0_0[15]\, enaddr_2_sqmuxa_3, N_3749_3, - enaddr_2_sqmuxa_0, enaddr_2_sqmuxa_1, N_3749_2, N_3356_3, - \cnt[0]\, \aluresult_1_iv_8[31]\, \shiftin_17[32]\, - \aluresult_1_iv_7[31]\, \logicout[31]\, - \aluresult_1_iv_6[31]\, \bpdata_m_2[7]\, - \aluresult_1_iv_3[31]\, \aluresult_1_iv_4[31]\, - \aluop_RNIK0RF4[1]\, \aluresult_1_iv_0[31]\, - \bpdata_m_0[15]\, \tba[19]\, \aluresult_1_iv_1[31]\, - \pc[31]\, \aluresult_6[31]\, \y[31]\, \ex_op2_m[31]\, - \d_1_iv_4[23]\, \rfo_m_i[55]\, \d_1_iv_2[23]\, - \op1_m_i[23]\, \result_m_i[23]\, \imm_m_i[23]\, - \d_1_iv_1[23]\, \result_m_i_0[23]\, \cpi_m_i[375]\, - \d_iv_2[23]\, \d_iv_0[23]\, \result_m_0[23]\, \rfo_m[23]\, - \un1_p0_6[375]\, \result_m_0_0[23]\, \d_1_iv_3[8]\, - \d_1_iv_1[8]\, \d_1_iv_0[8]\, \rfo_m_i[40]\, - \cpi_m_i[360]\, \imm_m_i[8]\, \result_m_i[8]\, - \d_iv_2[8]\, \d_iv_0[8]\, \result_m_0[8]\, \rfo_m[8]\, - \un1_p0_6[360]\, \result_m_0_0[8]\, \dpc[30]\, - \inst_0_1[30]\, \d_1_iv_3[27]\, \d_1_iv_1[27]\, - \d_1_iv_0[27]\, \rfo_m_i[59]\, \cpi_m_i[379]\, - \result[27]\, \imm_m_i[27]\, \d_iv_2[27]\, \d_iv_0[27]\, - \result_m_0[27]\, \rfo_m[27]\, \un1_p0_6[379]\, - \result_m_0_0[27]\, \d_1_iv_3[24]\, \d_1_iv_1[24]\, - \d_1_iv_0[24]\, \rfo_m_i[56]\, \result_m_i[24]\, - \cpi_m_i[376]\, \result[24]\, \imm_m_i[24]\, \d_iv_3[24]\, - \rfo_m[24]\, \d_iv_1[24]\, \op1_m_0[24]\, - \result_m_0[24]\, \cpi_m_0[376]\, \result_m_0_0[24]\, - \d_1_iv_3[30]\, \d_1_iv_1[30]\, \d_1_iv_0[30]\, - \rfo_m_i[62]\, \cpi_m_i[382]\, \result[30]\, - \imm_m_i[30]\, \d_iv_2[30]\, \d_iv_0[30]\, - \result_m_0[30]\, \rfo_m[30]\, \un1_p0_6[382]\, - \result_m_0_0[30]\, \aluresult_1_iv_7[16]\, - \aluresult_1_iv_5[16]\, \logicout_m_0[16]\, - \shiftin_17_m[17]\, \aluresult_1_iv_3[16]\, - \aluresult_1_iv_2[16]\, \bpdata_m_1[0]\, \bpdata[16]\, - \tba_m[4]\, \ex_op2_m[16]\, aluresult_8_sqmuxa_i, - \aluresult_1_iv_1[16]\, \y[16]\, \cpi_m[161]\, - \d_1_iv_3[12]\, \d_1_iv_2[12]\, \result_m_i[12]\, - \imm_m_i[12]\, \d_1_iv_1[12]\, \result_m_i_0[12]\, - \cpi_m_i[364]\, \d_iv_2[12]\, \d_iv_0[12]\, - \result_m_0[12]\, \rfo_m[12]\, \un1_p0_6[364]\, - \result_m_0_0[12]\, \d_1_iv_1[29]\, \d_1_iv_0[29]\, - \rfo_m_i[61]\, \cpi_m_i[381]\, \result[29]\, - \imm_m_i[29]\, \d_iv_3[29]\, \rfo_m[29]\, \d_iv_1[29]\, - \op1_m_0[29]\, \result_m_0[29]\, \cpi_m_0[381]\, - \result_m_0_0[29]\, \d_iv_2[20]\, \d_iv_0[20]\, - \result_m_0[20]\, \rfo_m[20]\, \un1_p0_6[372]\, - \result_m_0_0[20]\, \d_1_iv_3[20]\, \d_1_iv_2[20]\, - \result_m_i[20]\, \imm_m_i[20]\, \d_1_iv_1[20]\, - \cpi_m_i[372]\, \aluresult_1_iv_9[28]\, - \shiftin_17_m[29]\, \aluresult_1_iv_7[28]\, - \shiftin_17_m_0[28]\, \logicout[28]\, - \aluresult_1_iv_6[28]\, \bpdata_m_2[4]\, - \aluresult_1_iv_3[28]\, \aluresult_1_iv_4[28]\, - \aluop_RNI2TEB4[1]\, \aluresult_1_iv_0[28]\, - \aluop_RNIPR2R4[2]\, \tba[16]\, \aluresult_1_iv_1[28]\, - \cpi_m[173]\, \y[28]\, \ex_op2_m[28]\, - ADD_30x30_fast_I233_Y_0_0, \dpc[29]\, - \inst_0_RNI8AJ4[27]\, N436_0, ldlock_2_0, - de_fins_hold_1_2, N_3832, un5_ldlock, \d_1_iv_3[7]\, - \d_1_iv_1[7]\, \d_1_iv_0[7]\, \rfo_m_i[39]\, - \cpi_m_i[359]\, \result[7]\, \imm_m_i[7]\, \d_iv_2[7]\, - \d_iv_0[7]\, \result_m_0[7]\, \rfo_m[7]\, \un1_p0_6[359]\, - \result_m_0_0[7]\, un1_addout_12_0, un12_ex_add_res, - \d_1_iv_3[26]\, \d_1_iv_1[26]\, \d_1_iv_0[26]\, - \rfo_m_i[58]\, \cpi_m_i[378]\, \imm_m_i[26]\, - \result_m_i[26]\, \d_iv_2[26]\, \d_iv_0[26]\, - \result_m_0[26]\, \rfo_m[26]\, \un1_p0_6[378]\, - \result_m_0_0[26]\, \d_1_iv_3[25]\, \d_1_iv_1[25]\, - \d_1_iv_0[25]\, \rfo_m_i[57]\, \cpi_m_i[377]\, - \result[25]\, \imm_m_i[25]\, \d_iv_2[25]\, \d_iv_0[25]\, - \result_m_0[25]\, \rfo_m[25]\, \un1_p0_6[377]\, - \result_m_0_0[25]\, \osel_i_a3_0[0]\, un1_rs1, N_3948, - rfe_2, rfe_0, wreg_1, ldcheck2, imm, - ADD_30x30_fast_I276_Y_0_0, \dpc[18]\, \inst_0[16]\, - \d_1_iv_3[11]\, \d_1_iv_1[11]\, \d_1_iv_0[11]\, - \rfo_m_i[43]\, \cpi_m_i[363]\, \result[11]\, - \imm_m_i[11]\, \d_iv_2[11]\, \d_iv_0[11]\, - \result_m_0[11]\, \rfo_m[11]\, \un1_p0_6[363]\, - \result_m_0_0[11]\, \aluresult_1_iv_7[15]\, - \shiftin_17[16]\, \aluresult_1_iv_6[15]\, \logicout[15]\, - \aluresult_1_iv_5[15]\, \aluresult_1_iv_2[15]\, - \tba_m[3]\, \aluresult_1_iv_4[15]\, \bpdata_m[15]\, - \cpi_m[160]\, \y_m_1[15]\, \aluresult_1_iv_0[15]\, - \un1_iu0_5[81]\, \d_1_iv_3[22]\, \d_1_iv_1[22]\, - \d_1_iv_0[22]\, \rfo_m_i[54]\, \cpi_m_i[374]\, - \result[22]\, \imm_m_i[22]\, \d_iv_2[22]\, \d_iv_0[22]\, - \result_m_0[22]\, \rfo_m[22]\, \un1_p0_6[374]\, - \result_m_0_0[22]\, \d_1_iv_4[21]\, \op1[21]\, - \d_1_iv_3[21]\, \d_1_iv_1[21]\, \d_1_iv_0[21]\, - \rfo_m_i[53]\, \cpi_m_i[373]\, \result[21]\, - \imm_m_i[21]\, \d_iv_3[21]\, \rfo_m[21]\, \d_iv_1[21]\, - \op1_m_0[21]\, \result_m_0[21]\, \cpi_m_0[373]\, - \result_m_0_0[21]\, tt_2_sqmuxa_1_0, un1_trap_1_sqmuxa, - annul_3, \d_1_iv_3[14]\, \d_1_iv_1[14]\, \d_1_iv_0[14]\, - \rfo_m_i[46]\, \cpi_m_i[366]\, \result[14]\, - \imm_m_i[14]\, \d_iv_2[14]\, \d_iv_0[14]\, - \result_m_0[14]\, \rfo_m[14]\, \un1_p0_6[366]\, - \result_m_0_0[14]\, \aluresult_1_iv_9[23]\, - \shiftin_17[23]\, \aluresult_1_iv_8[23]\, - \aluresult_1_iv_6[23]\, \aluop_RNII15D6[0]\, - \shiftin_17_m[24]\, \aluresult_1_iv_4[23]\, - \aluresult_1_iv_3[23]\, \bpdata_m_1[7]\, \tba[11]\, - \aluresult_1_iv_2[23]\, \bpdata[23]\, - \aluresult_1_iv_1[23]\, \aluresult_1_iv_0[23]\, - \icc_m[3]\, \y[23]\, \cpi_m[168]\, \un1_iu0_5[89]\, - \d_1_iv_3[19]\, \d_1_iv_1[19]\, \d_1_iv_0[19]\, - \rfo_m_i[51]\, \cpi_m_i[371]\, \result[19]\, - \imm_m_i[19]\, \d_iv_2[19]\, \d_iv_0[19]\, - \result_m_0[19]\, \rfo_m[19]\, \un1_p0_6[371]\, - \result_m_0_0[19]\, \aluresult_1_iv_9[8]\, - \shiftin_17_m[9]\, \aluresult_1_iv_7[8]\, - \shiftin_17_m_0[8]\, \aluresult_1_iv_4[8]\, - \logicout_m_0[8]\, \pil_m[0]\, \aluresult_1_iv_0[8]\, - \bpdata_m[8]\, \y[8]\, \cpi_m[153]\, \un1_iu0_5[74]\, - \d_1_iv_3[17]\, \d_1_iv_1[17]\, \d_1_iv_0[17]\, - \rfo_m_i[49]\, d27, \cpi_m_i[369]\, \result[17]\, - \imm_m_i[17]\, \d_iv_2[17]\, \d_iv_0[17]\, - \result_m_0[17]\, \rfo_m[17]\, \un1_p0_6[369]\, - \result_m_0_0[17]\, \d_iv_2[18]\, \d_iv_0[18]\, - \result_m_0[18]\, \rfo_m[18]\, \un1_p0_6[370]\, d14, - \result_m_0_0[18]\, \d_1_iv_3[18]\, \d_1_iv_1[18]\, - \d_1_iv_0[18]\, \rfo_m_i[50]\, \cpi_m_i[370]\, - \result[18]\, d31, \imm_m_i[18]\, \dpc[31]\, - \inst_0_1[31]\, \d_1_iv_4[4]\, \op1[4]\, \d_1_iv_3[4]\, - \d_1_iv_2[4]\, \result_m_i[4]\, \imm_m_i[4]\, - \d_1_iv_1[4]\, \cpi_m_i[356]\, \d_iv_3[4]\, \rfo_m[4]\, - \d_iv_1[4]\, \op1_m_0[4]\, \result_m_0[4]\, - \cpi_m_0[356]\, \result_m_0_0[4]\, \d_1_iv_4[13]\, - \op1[13]\, \d_1_iv_3[13]\, \d_1_iv_2[13]\, \cpi_m_i[365]\, - \result_m_i[13]\, \d_1_iv_0[13]\, \result[13]\, - \imm_m_i[13]\, \d_iv_2[13]\, \d_iv_0[13]\, - \result_m_0[13]\, \rfo_m[13]\, \un1_p0_6[365]\, - \result_m_0_0[13]\, \aluresult_0_iv_9[27]\, - \shiftin_17[27]\, \aluresult_0_iv_8[27]\, - \aluresult_0_iv_6[27]\, \logicout_m_0[27]\, - \shiftin_17_m[28]\, \aluop_RNIEPDN4[2]\, - \aluresult_0_iv_2[27]\, \aluresult_0_iv_5[27]\, - \tba_m[15]\, \aluop_RNI5N3F4[1]\, \bpdata_m_2[3]\, - \ex_op2_m[27]\, \aluresult_0_iv_1[27]\, \pc[27]\, - \y_m_1[27]\, \aluresult_1_iv_8[24]\, - \aluresult_1_iv_6[24]\, \shiftin_17_m[25]\, N_198, - \aluresult_1_iv_4[24]\, \bpdata[8]\, aluresult_5_sqmuxa, - \aluresult_1_iv_2[24]\, \aluresult_1_iv_0[24]\, - \aluop_RNIN0RF4[1]\, \cpi_m[169]\, \y[24]\, - \ex_op2_m[24]\, \aluresult_1_iv_8[30]\, \shiftin_17[31]\, - \aluresult_1_iv_7[30]\, \aluresult_1_iv_5[30]\, - \aluresult_1_iv_4[30]\, \logicout_m_0[30]\, - \aluresult_1_iv_1[30]\, \tba_m[18]\, \bpdata_m_2[6]\, - \aluop_RNIC8EB4[1]\, \aluresult_1_iv_0[30]\, - \aluop_RNI143R4[2]\, \cpi_m[175]\, \y[30]\, - \ex_op2_m[30]\, \dpc[22]\, \inst_0[20]\, \dpc[14]\, - \aluresult_1_iv_7[12]\, \shiftin_17[13]\, - \aluresult_1_iv_6[12]\, \aluresult_1_iv_4[12]\, - \aluresult_1_iv_3[12]\, \logicout_m_0[12]\, N_3974, - \bpdata[12]\, \aluresult_1_iv_1[12]\, - \aluresult_1_iv_0[12]\, \tba_m[0]\, \y[12]\, \cpi_m[157]\, - \un1_iu0_5[78]\, \dpc[28]\, \inst_0_1[28]\, \d_iv_2[10]\, - \d_iv_0[10]\, \result_m_0[10]\, \rfo_m[10]\, - \un1_p0_6[362]\, \result_m_0_0[10]\, \d_1_iv_4[10]\, - \rfo_m_i[42]\, \d_1_iv_2[10]\, \op1_m_i[10]\, - \result_m_i[10]\, \imm_m_i[10]\, \d_1_iv_1[10]\, - \cpi_m_i[362]\, \aluresult_1_iv_8[29]\, - \aluresult_1_iv_6[29]\, \logicout_m_0[29]\, - \shiftin_17_m[30]\, \bpdata_m_2[5]\, - \aluresult_1_iv_3[29]\, \aluresult_1_iv_4[29]\, - \bpdata[13]\, \aluresult_1_iv_2[29]\, \tba[17]\, - \aluresult_1_iv_1[29]\, \bpdata[29]\, - \aluresult_1_iv_0[29]\, \cpi_m[174]\, \y[29]\, - \ex_op2_m[29]\, \d_1_iv_4[9]\, \rfo_m_i[41]\, - \d_1_iv_2[9]\, \op1_m_i[9]\, \result_m_i[9]\, - \imm_m_i[9]\, \d_1_iv_1[9]\, \result_m_i_0[9]\, - \cpi_m_i[361]\, \d_iv_2[9]\, \d_iv_1[9]\, \d_iv_0[9]\, - \cpi_m_0[361]\, \result_m_0[9]\, \dpc[17]\, \inst_0[15]\, - \aluresult_1_iv_4[20]\, \aluresult_1_iv_3[20]\, - \bpdata_m_1[4]\, \icc_m[0]\, \aluresult_1_iv_0[20]\, - \tba_m[8]\, \cpi_m[165]\, \y_m_1[20]\, \bpdata_m[20]\, - \un1_iu0_5[86]\, \dpc[27]\, \inst_0_1[27]\, - ADD_30x30_fast_I234_Y_1, N518, N511, - ADD_30x30_fast_I234_Y_0, N455, N452, N451, - ADD_30x30_fast_I232_Y_2, I86_un1_Y, - ADD_30x30_fast_I232_Y_0, I140_un1_Y_i, - ADD_30x30_fast_I30_un1_Y, \dpc[10]\, \inst_0[8]\, - ADD_30x30_fast_I282_Y_0_0, un6_annul_4, un3_irl, - un6_annul_2, annul_RNIPFOQ, irqen, irqen2, un6_annul_1, - et, pv_1, wreg_1_6, un1_de_ren1_4_i_0, wreg_1_4, - un1_de_ren1_5_i_0, wreg_1_2, wreg_1_1, \rd_RNIQP6H1[7]\, - \rd[3]\, \inst_0_RNI3RUM[3]\, wreg_1_0, \rd[1]\, - \inst_0_RNI1JUM[1]\, un1_de_ren1_2_0_i_0, wreg_2, - \dpc[16]\, \inst_0[14]\, \d_1_iv_3[6]\, \d_1_iv_1[6]\, - \d_1_iv_0[6]\, \rfo_m_i[38]\, \cpi_m_i[358]\, \result[6]\, - \imm_m_i[6]\, \d_iv_2[6]\, \d_iv_0[6]\, \result_m_0[6]\, - \rfo_m[6]\, \un1_p0_6[358]\, \result_m_0_0[6]\, irqen_1, - trap27, trap63, \aluresult_1_iv_8[7]\, \shiftin_17[8]\, - \aluresult_1_iv_7[7]\, \bpdata[7]\, N_3957, - \aluresult_1_iv_6[7]\, \aluresult_1_iv_4[7]\, - \aluresult_1_iv_3[7]\, \logicout_m_0[7]\, - \aluresult_1_iv_2[7]\, esu, aluresult_11_sqmuxa, - \aluresult_1_iv_1[7]\, \y[7]\, \cpi_m[152]\, - \un1_iu0_5[73]\, \aluresult_1_iv_0[7]\, \wim_m[7]\, - \aluresult_1_iv_9[26]\, \shiftin_17_m[27]\, - \aluresult_1_iv_7[26]\, \shiftin_17_m_0[26]\, - \aluresult_1_iv_5[26]\, \aluresult_1_iv_4[26]\, - \logicout_m_0[26]\, \aluresult_1_iv_3[26]\, - \bpdata_m_2[2]\, \bpdata[10]\, \aluresult_1_iv_2[26]\, - \tba[14]\, \aluresult_1_iv_1[26]\, \bpdata[26]\, - \aluresult_1_iv_0[26]\, \pc[26]\, \aluresult_4[1]\, - \un1_iu0_5[92]\, \y_m_1[26]\, ADD_30x30_fast_I235_Y_2, - N588, N573, ADD_30x30_fast_I235_Y_1, N520, N513, - ADD_30x30_fast_I235_Y_0, I36_un1_Y_i, I92_un1_Y, N433, - \aluresult_1_iv_9[25]\, \shiftin_17_m[26]\, - \aluresult_1_iv_7[25]\, \shiftin_17_m_0[25]\, - \aluresult_1_iv_5[25]\, \aluresult_1_iv_4[25]\, - \logicout_m_0[25]\, \aluresult_1_iv_3[25]\, - \bpdata_m_2[1]\, \aluresult_1_iv_2[25]\, \bpdata_m_0[9]\, - \tba[13]\, \aluresult_1_iv_1[25]\, \y_m_1[25]\, - \ex_op2_m[25]\, \aluop_RNIQ4RF4[1]\, \pc[25]\, - \d_1_iv_3[3]\, \d_1_iv_1[3]\, \d_1_iv_0[3]\, - \rfo_m_i[35]\, \result_m_i[3]\, \cpi_m_i[355]\, - \result[3]\, \imm_m_i[3]\, \d_iv_2[3]\, \d_iv_0[3]\, - \result_m_0[3]\, \rfo_m[3]\, \un1_p0_6[355]\, - \result_m_0_0[3]\, ADD_30x30_fast_I238_Y_0, N519, - \d_1_iv_3[5]\, \d_1_iv_1[5]\, \d_1_iv_0[5]\, - \rfo_m_i[37]\, \cpi_m_i[357]\, \result[5]\, \imm_m_i[5]\, - \d_iv_0_2[5]\, \d_iv_0_0[5]\, N_406, - \rsel1_0_RNITC8M2[2]\, \un1_p0_6[357]\, N_403, \dpc[20]\, - \inst_0[18]\, \aluresult_1_iv_8[11]\, \shiftin_17[12]\, - \aluresult_1_iv_7[11]\, \logicout[11]\, - \aluresult_1_iv_6[11]\, \aluresult_1_iv_3[11]\, - \aluresult_1_iv_4[11]\, \bpdata[11]\, - \aluresult_1_iv_2[11]\, \cpi_m[156]\, \y_m_1[11]\, - \tt_m[7]\, \pil[3]\, \aluresult_1_iv_0[11]\, - \un1_iu0_5[77]\, ADD_30x30_fast_I236_Y_1, N590, N575, - ADD_30x30_fast_I236_Y_0, N522, N515, N514, \dpc[19]\, - \inst_0[17]\, \dpc[21]\, \inst_0[19]\, wreg_5, wreg_3, - \rd_RNI2Q6H1[7]\, un1_de_ren1_1_4_i_0, wreg_0_0, - un1_de_ren1_1_3_i_0, wreg_1_7, un1_de_ren1_1_1_i_0, - un1_de_ren1_1_2_i_0, \rd_1[0]\, wreg_4, un1_de_ren1_NE_5, - un1_de_ren1_4_i, un1_de_ren1_NE_3, un1_de_ren1_5_i, - un1_de_ren1_NE_1, un1_de_ren1_NE_0, \rd_RNIMP6H1[7]\, - \rd[2]\, \inst_0_RNI2NUM[2]\, un1_de_ren1_3_i, \rd_2[0]\, - un1_de_ren1_1_i, \aluresult_1_iv_8[22]\, - \aluresult_1_iv_7[22]\, \logicout[22]\, - \aluresult_1_iv_6[22]\, \aluresult_1_iv_4[22]\, - \aluresult_1_iv_3[22]\, \bpdata_m_1[6]\, \tba[10]\, - \aluresult_1_iv_2[22]\, \bpdata[22]\, - \aluresult_1_iv_1[22]\, \aluresult_1_iv_0[22]\, - \icc_m[2]\, \y[22]\, \cpi_m[167]\, \un1_iu0_5[88]\, - \aluresult_1_iv_8[21]\, \shiftin_17[22]\, - \aluresult_1_iv_7[21]\, \aluresult_1_iv_5[21]\, - \bpdata_m_1[5]\, \logicout_m_0[21]\, - \aluresult_1_iv_2[21]\, \tba_m[9]\, - \aluresult_1_iv_3[21]\, \cpi_m[166]\, \y_m_1[21]\, - \bpdata_m[21]\, \ex_op2_m[21]\, \icc_m[1]\, - ADD_30x30_fast_I239_Y_1, I154_un1_Y, I204_un1_Y, - \dpc[23]\, \dpc[15]\, \inst_0[13]\, \dpc[13]\, - \inst_0[11]\, \aluresult_1_iv_3[14]\, \tba_m[2]\, - \aluresult_1_iv_5[14]\, \bpdata[14]\, - \aluresult_1_iv_1[14]\, \aluresult_1_iv_2[14]\, - \y_m_1[14]\, \cpi_m[159]\, \aluresult_1_iv_0[14]\, - \ex_op2_m[14]\, dwt, aluresult_9_sqmuxa, - \aluresult_1_iv_7[19]\, \shiftin_17[20]\, - \aluresult_1_iv_6[19]\, \logicout[19]\, \ex_op2_m[19]\, - \aluresult_1_iv_1[19]\, \pc[19]\, \y_m_1[19]\, - \aluresult_1_iv_8[17]\, \shiftin_17_m[18]\, - \aluresult_1_iv_6[17]\, \shiftin_17_m_0[17]\, - \aluresult_1_iv_4[17]\, \bpdata_m_1[1]\, - \logicout_m_0[17]\, \aluresult_1_iv_1[17]\, - \aluresult_1_iv_0[17]\, \aluresult_1_iv_3[17]\, - \tba_m[5]\, \y[17]\, \cpi_m[162]\, \un1_iu0_5[83]\, - ADD_30x30_fast_I267_Y_0_0, \dpc[9]\, \inst_0[7]\, - \aluresult_1_iv_7[18]\, \shiftin_17[19]\, - \aluresult_1_iv_6[18]\, \logicout[18]\, - \aluresult_1_iv_5[18]\, \bpdata_m_1[2]\, - \aluresult_1_iv_4[18]\, \aluresult_1_iv_1[18]\, - \aluresult_1_iv_0[18]\, \aluresult_1_iv_3[18]\, - \bpdata[18]\, \tba_m[6]\, \y_m_1[18]\, \cpi_m[163]\, - \un1_iu0_5[84]\, \dpc[12]\, \inst_0[10]\, - \aluresult_1_iv_7[4]\, \shiftin_17[5]\, - \aluresult_1_iv_6[4]\, \bpdata[4]\, \aluresult_1_iv_5[4]\, - \logicout[4]\, \aluresult_1_iv_4[4]\, - \aluresult_1_iv_3[4]\, \aluresult_1_iv_0[4]\, - \ex_op2_m[4]\, \aluresult_1_iv_2[4]\, \pc[4]\, \y_m_1[4]\, - \wim[4]\, aluresult_13_sqmuxa, - ADD_30x30_fast_I235_un1_Y_0, N589, \dpc[11]\, \inst_0[9]\, - ADD_30x30_fast_I236_un1_Y_0, N591, \aluresult_1_iv_7[13]\, - \shiftin_17[14]\, \aluresult_1_iv_6[13]\, \logicout[13]\, - \aluresult_1_iv_5[13]\, \aluresult_1_iv_2[13]\, - \tba_m[1]\, \aluresult_1_iv_4[13]\, \ex_op2_m[13]\, - \aluresult_1_iv_1[13]\, \y[13]\, \cpi_m[158]\, - \d_1_iv_3[2]\, \d_1_iv_1[2]\, \d_1_iv_0[2]\, - \rfo_m_i[34]\, \cpi_m_i[354]\, \result[2]\, \imm_m_i[2]\, - \d_iv_2[2]\, \d_iv_0[2]\, \result_m_0[2]\, \rfo_m[2]\, - \un1_p0_6[354]\, \result_m_0_0[2]\, - ADD_33x33_fast_I322_Y_0_0, \op2[31]\, \un1_iu0_6[31]\, - \aluresult_1_iv_8[10]\, \shiftin_17[11]\, - \aluresult_1_iv_7[10]\, \logicout[10]\, - \aluresult_1_iv_6[10]\, \aluresult_1_iv_3[10]\, - \aluresult_1_iv_4[10]\, \aluresult_1_iv_2[10]\, - \cpi_m[155]\, \y_m_1[10]\, \tt_m[6]\, \pil[2]\, - \aluresult_1_iv_0[10]\, \un1_iu0_5[76]\, - \aluresult_1_iv_8[9]\, \aluresult_1_iv_6[9]\, - \logicout_m_0[9]\, \shiftin_17_m[10]\, - \aluresult_1_iv_4[9]\, \aluresult_1_iv_5[9]\, \tt_m[5]\, - \aluresult_1_iv_1[9]\, \pil_m[1]\, \aluresult_1_iv_0[9]\, - \bpdata_m[9]\, \pc[9]\, \y_m_1[9]\, \un1_iu0_5[75]\, - \dpc[6]\, \inst_0_RNI4VUM[4]\, ADD_33x33_fast_I259_Y_3, - I155_un1_Y, ADD_33x33_fast_I259_Y_1, I211_un1_Y, - I33_un1_Y_1, N487, I95_un1_Y, ADD_33x33_fast_I259_Y_3_0, - I155_un1_Y_0, ADD_33x33_fast_I259_Y_1_0, I211_un1_Y_0, - N487_0, I95_un1_Y_0, ADD_33x33_fast_I319_Y_0_0, \op2[28]\, - \aluresult_1_iv_5[6]\, \logicout_m_0[6]\, - \aluresult_1_iv_1[6]\, ps_m_0, \aluresult_1_iv_4[6]\, - \aluresult_1_iv_2[6]\, \pc[6]\, \y_m_1[6]\, - \un1_iu0_5[72]\, \aluresult_1_iv_0[6]\, \wim_m[6]\, - iflush_1_0, \inst_0[24]\, \inst[21]\, trap_0_sqmuxa_1_1_i, - ADD_33x33_fast_I259_Y_3_1, N625, N640, - ADD_33x33_fast_I259_Y_2, I95_un1_Y_1, - ADD_33x33_fast_I259_Y_0, I155_un1_Y_1, \d_1_iv_4[1]\, - \op1[1]\, \d_1_iv_3[1]\, \d_1_iv_1[1]\, \d_1_iv_0[1]\, - \rfo_m_i[33]\, \result_m_i[1]\, \cpi_m_i[353]\, - \result[1]\, \imm_m_i[1]\, \d_iv_2[1]\, \d_iv_0[1]\, - \result_m_0[1]\, \rfo_m[1]\, \un1_p0_6[353]\, - \result_m_0_0[1]\, \aluresult_1_iv_7[3]\, - \shiftin_17_m_0[3]\, \aluresult_1_iv_6[3]\, - \aluresult_1_iv_5[3]\, \shiftin_17_m[4]\, \bpdata_m[3]\, - \aluresult_1_iv_4[3]\, \aluresult_1_iv_3[3]\, - \logicout_m_0[3]\, \cpi_m[148]\, \y_m_1[3]\, - \aluresult_1_iv_1[3]\, \un1_iu0_5[69]\, - \aluresult_1_iv_0[3]\, \wim_m[3]\, \d_iv_2[0]\, - \d_iv_0[0]\, \result_m_0[0]\, \rfo_m[0]\, \un1_p0_6[352]\, - \result_m_0_0[0]\, \d_1_iv_4[0]\, \rfo_m_i[32]\, - \d_1_iv_2[0]\, \op1_m_i[0]\, \result_m_i[0]\, - \imm_m_i[0]\, \d_1_iv_1[0]\, \cpi_m_i[352]\, - \aluresult_1_iv_9[5]\, \shiftin_17_m[6]\, - \aluresult_1_iv_7[5]\, \shiftin_17_m_0[5]\, \bpdata[5]\, - \aluresult_1_iv_6[5]\, \aluresult_1_iv_4[5]\, - \aluresult_1_iv_3[5]\, \logicout_m_0[5]\, - \aluresult_1_iv_2[5]\, et_0, \aluresult_1_iv_1[5]\, - \pc[5]\, \y_m_1[5]\, \un1_iu0_5[71]\, - \aluresult_1_iv_0[5]\, \wim_m[5]\, - ADD_33x33_fast_I262_Y_0_0, N_52, N478, - ADD_33x33_fast_I39_Y_0_a3, ADD_33x33_fast_I262_Y_0_0_0, - N502_0, N_50_0, N498_i, N551, N587, N543, \dpc[4]\, - \dpc[5]\, me_nullify2_1_2_1, un5_trap, trap_0_sqmuxa_7, - me_nullify2_1_2_0, nullify_0_sqmuxa_0, - ADD_33x33_fast_I262_Y_0_0_1, N502_1, N_50_1, N498, - \aluresult_2_iv_7[2]\, \shiftin_17[3]\, - aluresult_1_sqmuxa, \aluresult_2_iv_6[2]\, - \aluresult_2_iv_5[2]\, \aluresult_2_iv_3[2]\, - \aluresult_2_iv_2[2]\, \logicout_m_0[2]\, \cpi_m[147]\, - \y_m_1[2]\, \cwp_m[2]\, \ex_op2_m[2]\, \wim_m[2]\, - ADD_30x30_fast_I244_un1_Y_0, ADD_33x33_fast_I262_Y_0_a3_0, - N503_0, ADD_33x33_fast_I321_Y_0_0, \tt_0[1]\, \tt_0[2]\, - N_4036, ADD_33x33_fast_I318_Y_0_0, \op2[27]\, I227_un1_Y, - N640_0, N656, N641, N640_1, - ADD_33x33_fast_I262_Y_0_a3_0_0, N503_1, - ADD_30x30_fast_I132_Y_0, N370, ADD_33x33_fast_I303_Y_0_0, - ADD_33x33_fast_I311_Y_0_0, \op2[20]\, \un1_iu0_6[20]\, - N_454, \inst_RNIJ02L[19]\, \aop2_i_o2_0[0]\, N_219, - \tt_9_0_a3_0_1[5]\, ticc, trap_1, \tt_4[3]\, trap_4_1_0, - N656_0, N641_0, N648, N633, N648_0, N633_0, - ADD_33x33_fast_I263_Y_0_0, N574_0, N567_0, N566, N642, - N627_0, ADD_33x33_fast_I260_Y_2, N568_0, N561, - ADD_33x33_fast_I260_Y_1, ADD_33x33_fast_I260_Y_0, - ADD_33x33_fast_I97_un1_Y, N481, \aluresult_2_iv_7[1]\, - \shiftin_17[2]\, \shiftin_17_m_0[1]\, - \aluresult_2_iv_6[1]\, \eaddress[1]\, - \aluresult_2_iv_5[1]\, \logicout_m_0[1]\, - \aluresult_2_iv_3[1]\, \bpdata_m[1]\, \cwp_m[1]\, - \aluresult_2_iv_0[1]\, \aluresult_2_iv_1[1]\, \y[1]\, - \wim_m[1]\, \ex_op2_m[1]\, ADD_33x33_fast_I260_Y_3_1, - N642_0, N627_1, ADD_33x33_fast_I260_Y_2_0, I97_un1_Y, - ADD_33x33_fast_I260_Y_0_0, N481_0, \aluresult_2_iv_7[0]\, - \shiftin_17[0]\, \aluresult_2_iv_6[0]\, \logicout_m_0[0]\, - \aluresult_2_iv_4[0]\, \bpdata_m[0]\, - \aluresult_2_iv_1[0]\, \cwp_m[0]\, \aluresult_2_iv_2[0]\, - \aluresult_2_iv_0[0]\, \op2_RNI59C6[0]\, - aluresult_7_sqmuxa, \y_m_0[0]\, \wim[0]\, - \un6_ex_add_res_m[1]\, tba_610_e_5, tba_610_e_3, - tba_610_e_2, annul_1_0, \inst_1[19]\, y15, \inst_0[22]\, - \inst[23]\, \inst[20]\, \inst_0[21]\, I157_un1_Y_i_0, - ADD_33x33_fast_I260_Y_1_0, I213_un1_Y_i, - ADD_33x33_fast_I260_Y_0_1, N481_1, - ADD_33x33_fast_I317_Y_0_0, ldbp2_0_a5_0, N629, N644, - ADD_33x33_fast_I261_Y_1, I99_un1_Y, I159_un1_Y, N496, - I159_un1_Y_0, ADD_33x33_fast_I261_Y_0, I215_un1_Y, N497_0, - N496_0, ADD_33x33_fast_I263_Y_1_1, I163_un1_Y_i, - I219_un1_Y_i, N566_0, I159_un1_Y_1, - ADD_33x33_fast_I261_Y_0_0, I215_un1_Y_0, N500_0, N496_1, - ADD_33x33_fast_I312_Y_0_0, \op2[21]\, icc_0_sqmuxa_1_29, - icc_0_sqmuxa_1_18, icc_0_sqmuxa_1_17, icc_0_sqmuxa_1_26, - icc_0_sqmuxa_1_28, icc_0_sqmuxa_1_14, icc_0_sqmuxa_1_13, - icc_0_sqmuxa_1_24, icc_0_sqmuxa_1_27, icc_0_sqmuxa_1_10, - icc_0_sqmuxa_1_9, icc_0_sqmuxa_1_22, icc_0_sqmuxa_1_8, - icc_0_sqmuxa_1_7, icc_0_sqmuxa_1_19, icc_0_sqmuxa_1_16, - \logicout[21]\, icc_0_sqmuxa_1_0, icc_0_sqmuxa_1_12, - \logicout[30]\, icc_0_sqmuxa_1_5, \logicout[16]\, - icc_0_sqmuxa_1_3, \logicout[12]\, icc_0_sqmuxa_1_2, - \logicout[6]\, \logicout[5]\, \logicout[23]\, - \logicout[1]\, \logicout[20]\, \logicout[0]\, - \logicout[2]\, \logicout[3]\, \logicout[29]\, - \logicout[26]\, \logicout[27]\, \logicout[25]\, - \logicout[17]\, \logicout[14]\, \logicout[9]\, - \logicout[7]\, \logicout[8]\, ADD_33x33_fast_I310_Y_0_0, - \op2[19]\, \op1_RNID1VH[19]\, ADD_33x33_fast_I308_Y_0_0, - \op2[17]\, \un1_iu0_6[17]\, I165_un1_Y_0, I221_un1_Y, - N568_1, ADD_33x33_fast_I264_Y_1_1, N650, N635_1, - \tt_3[3]\, \tt_1[3]\, cp_disabled_4, fp_disabled_4, - \dpc[3]\, N650_0, ADD_33x33_fast_I264_Y_0_0, N576_0, - N569_0, N652, N637_0, ADD_33x33_fast_I265_Y_0, N578_0, - N571, N570, N652_0, ADD_33x33_fast_I265_Y_0_0, N578_1, - N571_0, N570_0, I167_un1_Y_i, I223_un1_Y_i, N570_1, - \edata2_0_iv_0[0]\, \op1[0]\, \ex_op1_i_m[0]\, - \edata2_0_iv_0[7]\, \op1[7]\, \ex_op1_i_m[7]\, - \edata2_0_iv_0[5]\, \op1[5]\, \ex_op1_i_m[5]\, - \edata2_0_iv_0[3]\, \op1[3]\, \ex_op1_i_m[3]\, - \edata2_0_iv_0[4]\, \un1_iu0_6[4]\, \op1_i_m[4]\, - ADD_33x33_fast_I261_un1_Y_0, N629_0, un1_rs1_2, un1_rs1_0, - un1_rs1_1, ADD_33x33_fast_I268_Y_0_0, N658_0, N643_0, - ADD_33x33_fast_I268_Y_0_1, N658_1, N643_1, - ADD_33x33_fast_I261_un1_Y_0_0, N629_1, N645_0, - de_inull_0_2004_0, rett_1, de_inull_0_a3_1_0, jmpl_1, - ADD_33x33_fast_I269_Y_0_1, N660_0, N645_1, branch_1_m7_3, - branch_1_m7_1, N660_1, N644_0, ADD_33x33_fast_I271_Y_0, - N664, N649, ADD_33x33_fast_I271_Y_0_0, I235_un1_Y_i, - I179_un1_Y, N582, SUM2_0_0, \cwp[2]\, tt_9_0_1862_0, - N_16684_tz_tz, trap_4_1, ADD_33x33_fast_I271_Y_0_1, - N664_0, N649_0, ADD_33x33_fast_I268_un1_Y_0, N674, N642_1, - ADD_33x33_fast_I273_Y_0, ADD_33x33_fast_I273_un1_Y_0, - N653_0, N652_1, ADD_33x33_fast_I273_Y_0_0, - ADD_33x33_fast_I273_un1_Y_0_0, d_m5_0_a3_0, \y_iv_2[31]\, - \y_m[31]\, \y_m_0[31]\, \y_iv_0[31]\, ex_ymsb_1_m, - ADD_33x33_fast_I265_un1_Y_0_0, N653_1, - ADD_33x33_fast_I265_un1_Y_0_1, N637_1, - ADD_33x33_fast_I273_Y_0_1, ADD_33x33_fast_I273_un1_Y_0_1, - un9_rabpmiss_1, un9_rabpmiss_0, \y_iv_1[22]\, \y_0[22]\, - \y_m[22]\, \y_iv_0[22]\, \y_m[23]\, \y_iv_2[21]\, - \y_m[21]\, \y_m_0[21]\, \y_iv_0[21]\, \y[21]\, - \y_m_0[22]\, \y_iv_1[23]\, \y_0[23]\, \y_m_0[23]\, - \y_iv_0[23]\, \y_m[24]\, \y_iv_1[20]\, \y[20]\, \y_m[20]\, - \y_iv_0[20]\, \y_0[20]\, \y_m_2[21]\, \y_iv_0_1[1]\, - \y_0[1]\, N_378, \y_iv_0_0[1]\, N_381, \y_iv_0_o5_1[0]\, - \y[0]\, N_465, \y_iv_0_o5_0[0]\, \y_0[0]\, N_468, - trap_0_sqmuxa_7_1, trap_2, werr_1, - ADD_33x33_fast_I268_un1_Y_0_0, N659, \y_iv_2[3]\, - \y_m[4]\, \y_m_0[3]\, \y_iv_1[3]\, \y[3]\, \y_m[3]\, - \y_iv_1[2]\, \y[2]\, \y_m[2]\, \y_iv_0[2]\, \y_0[2]\, - \y_m_2[3]\, \y_iv_2[4]\, \y_m_0[4]\, \y_m_2[4]\, - \y_iv_0[4]\, \y[4]\, \y_m[5]\, \tt_9_0_a3_0[5]\, - \y_iv_0_1[14]\, \y[14]\, N_387, \y_iv_0_0[14]\, \y_0[14]\, - N_389, \y_iv_0_2[29]\, N_419, N_416, \y_iv_0_1[29]\, - \y_0[29]\, N_417, \y_iv_1[11]\, \y[11]\, \y_m[11]\, - \y_iv_0[11]\, \y_0[11]\, \y_m[12]\, \y_iv_2[5]\, \y_m[6]\, - \y_m_0[5]\, \y_iv_1[5]\, \y[5]\, \y_m_2[5]\, \y_iv_2[9]\, - \y_m[10]\, \y_m_0[9]\, \y_iv_1[9]\, \y[9]\, \y_m[9]\, - \y_iv_1[10]\, \y[10]\, \y_m_0[10]\, \y_iv_0[10]\, - \y_0[10]\, \y_m_0[11]\, \y_iv_1[19]\, \y[19]\, \y_m[19]\, - \y_iv_0[19]\, \y_0[19]\, \y_m_0[20]\, \y_iv_0_2[18]\, - N_397, N_394, \y_iv_0_1[18]\, \y[18]\, N_395, - \y_iv_0_1[27]\, \y[27]\, N_422, \y_iv_0_0[27]\, \y_0[27]\, - N_424, \y_iv_2[26]\, \y_m[27]\, \y_m_0[26]\, \y_iv_1[26]\, - wy_RNIMKUI, \y[26]\, \y_m[26]\, \y_iv_1[12]\, \y_0[12]\, - \y_m_0[12]\, \y_iv_0[12]\, \y_m[13]\, \y_iv_2[28]\, - \y_m[29]\, \y_m_0[28]\, \y_iv_1[28]\, \y_0[28]\, - \y_m[28]\, \y_iv_2[17]\, \y_m[18]\, \y_m_0[17]\, - \y_iv_1[17]\, \y_0[17]\, \y_m[17]\, \y_iv_2[15]\, - \y_m[15]\, \y_m_0[15]\, \y_iv_0[15]\, \y[15]\, \y_m[16]\, - \y_iv_1[8]\, \y_0[8]\, \y_m[8]\, \y_iv_0[8]\, y08, - \y_m_2[9]\, \y_iv_1[13]\, \y_0[13]\, \y_m_0[13]\, - \y_iv_0[13]\, \y_m[14]\, \y_iv_1[16]\, \y_0[16]\, - \y_m_0[16]\, \y_iv_0[16]\, \y_m_1[17]\, \y_iv_1[6]\, - \y[6]\, \y_m_0[6]\, \y_iv_0[6]\, \y_0[6]\, \y_m[7]\, - \y_iv_2[7]\, \y_m_0[8]\, \y_m_0[7]\, \y_iv_1[7]\, - \y_0[7]\, \y_m_1[7]\, \y_iv_2[25]\, \y_m_2[26]\, - \y_m_0[25]\, \y_iv_1[25]\, \y[25]\, \y_m[25]\, - \y_iv_2[30]\, \y_m_1[31]\, \y_m_0[30]\, \y_iv_1[30]\, - \y_0[30]\, \y_m[30]\, ADD_33x33_fast_I268_un1_Y_0_1, - N593_0, N601, ADD_33x33_fast_I271_un1_Y_0, N665, N614_0, - ADD_33x33_fast_I269_un1_Y_0, N595, N603_i, - un23_exbpmiss_0, wreg_1_6_0, wreg_1_0_0, un2_rs1_2_0_i_0, - wreg_1_3, wreg_1_5, un2_rs1_2_7_i_0, un2_rs1_2_5_i_0, - wreg_1_2_0, \un3_de_ren1[94]\, \rd_0[3]\, un2_rs1_2_6_i_0, - \un3_de_ren1[92]\, \rd_0[1]\, un2_rs1_2_2_i_0, - \un3_de_ren1[95]\, \rd[4]\, N552, N669, N552_0, N669_0, - illegal_inst_7_iv_7, N_603, illegal_inst_7_iv_8_tz, - illegal_inst_7_iv_5, illegal_inst_7_iv_6_0, \cpi_m[121]\, - illegal_inst_7_iv_3, \inst_RNI3RNK9[19]\, - illegal_inst_7_iv_6_tz, illegal_inst_7_iv_2_0_a5_1_0, - N_474, illegal_inst_7_iv_0, N_444, illegal_inst_7_iv_1, - illegal_inst_4_m_0, illegal_inst33, - cp_disabled_3_sqmuxa_2, illegal_inst_1_sqmuxa_i_2, N_434, - \cpi_m_i[133]\, wreg_2_5, un2_rs1_1_7_i_0, - un2_rs1_1_5_i_0, wreg_2_2, wreg_2_4, \rs1_iv_i_0[0]\, - wreg_2_0, wreg_2_3, un2_rs1_1_6_i_0, un2_rs1_1_2_i_0, - \rd_0[4]\, un2_rs1_NE_5, un2_rs1_0_i, un2_rs1_6_i, - un2_rs1_NE_2, un2_rs1_NE_4, un2_rs1_5_i, un2_rs1_4_i, - un2_rs1_NE_1, \un3_de_ren1[93]\, un2_rs1_3_i, - \un3_de_ren1[98]\, \rd[7]\, un2_rs1_1_i, N659_0, N552_1, - N611, \edata2_0_iv_0[8]\, \op1[8]\, \ex_op1_i_m[8]\, - \edata2_0_iv_0[9]\, \op1[9]\, \ex_op1_i_m[9]\, - \edata2_0_iv_0[10]\, \op1_i_m[10]\, \edata2_0_iv_1[15]\, - \ex_op1_i_m[15]\, \op1_i_m[15]\, \bpdata_i_m_2[7]\, - \y_iv_0_2[24]\, N_374, N_371, \y_iv_0_1[24]\, \y_0[24]\, - N_372, \edata2_0_iv_1[21]\, \edata2_0_iv_0[21]\, - \bpdata[21]\, \op1_i_m[21]\, \edata2_0_iv_0[19]\, - \op1_i_m[19]\, \edata2_0_iv_0[16]\, \op1_i_m[16]\, - \edata2_0_iv_0[18]\, \op1_i_m[18]\, \edata2_0_iv_0[22]\, - \op1_i_m[22]\, \edata2_0_iv_1[23]\, \bpdata_i_m[23]\, - \op1_i_m[23]\, \ex_op1_i_m[23]\, \edata2_0_iv_1[20]\, - \edata2_0_iv_0[20]\, \bpdata[20]\, \op1_i_m[20]\, - \edata2_0_iv_0[11]\, \op1[11]\, \ex_op1_i_m[11]\, - \edata2_0_iv_1[13]\, \ex_op1_i_m[13]\, \op1_i_m[13]\, - \bpdata_i_m[13]\, \edata2_0_iv_0[12]\, \op1[12]\, - \ex_op1_i_m[12]\, \edata2_0_iv_1[14]\, \bpdata_i_m[14]\, - \edata2_0_iv_0[14]\, \op1_i_m[14]\, \edata2_iv_2[27]\, - edata_1_sqmuxa, \bpdata_i_m_2[3]\, \edata2_iv_1[27]\, - \ex_op1_i_m[27]\, \op1_RNI4VNF[27]\, \bpdata_i_m[27]\, - \edata2_iv_1[29]\, \ex_op1_i_m[29]\, \op1_RNI67OF[29]\, - \bpdata_i_m[29]\, \edata2_iv_2[25]\, \bpdata[9]\, - \bpdata_i_m_2[1]\, \edata2_iv_1[25]\, \bpdata[25]\, - \edata2_iv_0[25]\, \op1_RNI2NNF[25]\, \edata2_iv_2[24]\, - \aluop_RNI6QSC4[2]\, \bpdata_i_m_2[0]\, \edata2_iv_1[24]\, - \ex_op1_i_m[24]\, \op1_RNI1JNF[24]\, \bpdata_i_m[24]\, - \edata2_iv_2[30]\, \bpdata_i_m_0[14]\, \bpdata_i_m_2[6]\, - \edata2_iv_1[30]\, \bpdata[30]\, \edata2_iv_0[30]\, - \op1_RNIU2NF[30]\, \edata2_iv_2[28]\, \bpdata_i_m_2[4]\, - \edata2_iv_0[28]\, \op1[28]\, \ex_op1_i_m[28]\, - \edata2_iv_2[26]\, \bpdata_i_m_2[2]\, \edata2_iv_1[31]\, - un4_icc_m, \op1_i_m[31]\, \bpdata_i_m[31]\, rs1_2, - \rs1[4]\, \alusel_i_0_2[0]\, \alusel_i_0_1[0]\, N_351, - N_352, N_602, \alusel_i_0_1[1]\, N_341, \alusel_i_0_0[1]\, - N_212, \alusel_i_0_a5_0_0[1]\, N_339, - ADD_33x33_fast_I293_Y_0_0, \op2[2]\, \un1_iu0_6[2]\, - illegal_inst_7_iv_2_0_a5_0_1, \inst_2[19]\, - illegal_inst35_4, illegal_inst_7_iv_2_0_a5_0_0, N_487, - \inst_1[24]\, ADD_33x33_fast_I121_Y_0, \data_0[17]\, N445, - ADD_33x33_fast_I129_Y_0, N433_0, - ADD_33x33_fast_I121_Y_0_0, N445_0, \icc_1_iv_0[1]\, - icc_2_sqmuxa, \result_0[21]\, \icc_m_0[1]\, - \icc_1_iv_0[0]\, \result[20]\, \icc_m_0[0]\, - \icc_1_iv_0[3]\, \result[23]\, \icc_m_0[3]\, - \icc_1_iv_0[2]\, \result_0[22]\, \icc_m_0[2]\, - ADD_33x33_fast_I145_Y_0, \op2[5]\, N409, - ADD_33x33_fast_I145_Y_0_0, N409_0, - ADD_33x33_fast_I137_Y_0, N421, \data_0[9]\, N_271, N_209, - ADD_33x33_fast_I129_Y_0_0, N433_1, \data_0[13]\, - ADD_33x33_fast_I121_Y_0_1, N445_1, - ADD_33x33_fast_I137_Y_0_0, N421_0, - ADD_33x33_fast_I145_Y_0_1, N409_1, - ADD_33x33_fast_I137_Y_0_1, N421_1, un1_ld_1_sqmuxa_1_0, - un3_op2, write_reg_4_sqmuxa, ADD_33x33_fast_I113_Y_0, - N457, ADD_33x33_fast_I113_Y_0_0, N457_0, - ticc_exception_0_a3_1, un1_inst, un1_icc_check5_1_0, - icc_check9, \alusel_i_0_o5_0[1]\, \alusel_i_0_a2_1_0[1]\, - N_476, \tt_9_i_a4_0[2]\, wunf, wovf, bp, wim_1_sqmuxa_1, - wim_1_sqmuxa_0, un1_illegal_inst33_2, - un1_illegal_inst33_0, privileged_inst_0_sqmuxa, N_202, - illegal_inst37_4, illegal_inst38, G_9_0, N_6337, - ADD_33x33_fast_I130_Y_0_0, \op2[10]\, N431_1, - ADD_33x33_fast_I138_Y_0, N419, \inst_1[20]\, \inst_1[22]\, - \inst_0[23]\, ADD_33x33_fast_I138_Y_0_0, N419_0, - ADD_33x33_fast_I122_Y_0, N443, icc_check6_0, un7_op_3, - un1_icc_check5_0, icc_check10, - ADD_33x33_fast_I206_Y_0_o3_1_0, N397, \npc_cnst_m_0[0]\, - pv_4, pv_5, \npc_cnst_m_0[1]\, - ADD_33x33_fast_I206_Y_0_o3_1_0_0, \op2[1]\, N397_0, - ADD_33x33_fast_I206_Y_0_o3_1_0_1, N397_1, write_reg7_0, - N_89, N_122_1, inst_0, ADD_33x33_fast_I146_Y_0, N404, - N407, ADD_33x33_fast_I130_Y_0_1, N431_2, aluop_2_1_0_2, - aluadd_16_sqmuxa_0_a5_1, N_205, N_359, aluop_2_1_0_1, - N_360, \cnt_RNILD6A1[0]\, N_345, aluop_0_1_0_2, - aluop_0_1_0_a5_3_0, N_363, aluop_0_1_0_1, N_365, - \inst_RNILL631[19]\, N_362, de_inst_0_sqmuxa_0, un19_rd_1, - N_17, N_122_2, N_79, dwt_1_sqmuxa_3, dwt_1_sqmuxa_2, - \inst[27]\, \inst[26]\, \inst_1[29]\, \inst[25]\, - \inst[28]\, icc_2_sqmuxa_2, icc_2_sqmuxa_1, wicc, - \logicout_5_0_i_a5_0_0[24]\, illegal_inst34_3, - illegal_inst34_1, illegal_inst34_0, inst_5, inst_11_1, - inst_9_3, inst_22, inst_32_1, inst_32_0, inst_21, - ADD_33x33_fast_I206_Y_0_a3_1_0_0, N398_0, - aluresult_13_sqmuxa_3_0, aluresult_13_sqmuxa_1, - aluresult_13_sqmuxa_0_0, aluresult_13_sqmuxa_3, - \inst_1[21]\, \inst_0_m_0[26]\, un14_op_1, un14_op_2, - aluop_1_1_0_2, aluop_1_1_0_a5_0_0, aluop_1_1_0_0, N_262, - aluop_1_1_0_a5_0, N_344, invop2_0_1_i_0, N_58, - fp_disabled_4_0_1_1, cp_disabled_10_sqmuxa_1, N_260, - cp_disabled_5_sqmuxa, cp_disabled_4_0_1_1, - cp_disabled_11_sqmuxa, cp_disabled_4_0_1_0, - cp_disabled_2_sqmuxa_0, N_216, cp_disabled_8_sqmuxa_1, - bpdata6_2, rd_7_i_0, rd_4_i_0, rd_3_i_0, bpdata6_4, - \rd[5]\, \rd_0[5]\, rd_6_i_0, \rd_1[1]\, rd_2_i_0, - rstate_4_2, y6, y10, rstate_4_1, error_1_sqmuxa, - trap_1_sqmuxa_1, \cnt_1[1]\, \cnt_0[0]\, rstate_7_0, - ex_bpmiss_1_0_a5_0_0, N_261, ex_bpmiss_1_0_0, - ex_bpmiss_1_0_a5_0, N_328, N_427, cwp_2_sqmuxa_4, - cwp_2_sqmuxa_1, cwp_2_sqmuxa_2, icc_0_sqmuxa_1, - illegal_inst_7_iv_2_0_a5_5_0, et_1, \inst_2[21]\, - aluresult_11_sqmuxa_0, aluresult_11_sqmuxa_6, \inst[13]\, - \inst_1[25]\, \inst_2[20]\, N_201, bicc_hold_3, - bicc_hold_1, N_3736_2, rstate_9_0, un1_trap_0_sqmuxa_1_0, - trap55_i, \maddress[0]\, trap_0_sqmuxa_3, - \un6_ex_add_res_s0_0_0[1]\, \data_0[0]\, wicc_1_0_tz_0, - wicc_1_0_a3_1_1_0, N_152, wicc_1_0_a3_0, - cp_disabled_3_sqmuxa_2_0, un1_aop2_1_sqmuxa_0_a2_0_0, - ldcheck1_2, ldcheck1_5_i_a6_2_2, N_3737_1, N_3736, - ldcheck1_1, ldcheck1_5_i_a6_0_0, ldcheck1_0, - ADD_30x30_fast_I100_Y_0, N418_2, aluop_2_1_0_a2_1, - aluop_2_1_0_a2_0, \inst_1[23]\, illegal_inst_1_sqmuxa_i_0, - N_433, alusel24_2, \cpi_m_1[133]\, y_0_sqmuxa_3, - y_0_sqmuxa_1, \inst_0_0[24]\, de_fins_hold_1_1, bp_0, - \size_1[1]\, ex_sari_1_1_0, ADD_30x30_fast_I116_Y_0, N394, - ex_bpmiss_1_0_2_tz_0, ex_bpmiss_1_0_a5_2_1_0, N_248, - ex_bpmiss_1_0_a5_4_1, wy_1_0_a3_0_7_2, N_3525_3, - wy_1_0_a3_0_7_1, icc_check_bp_1, tmp, aluop_0_1_0_a5_0, - N_225, \inst_1[26]\, \inst_1[27]\, ex_bpmiss_1_0_a5_1_1, - N_482, illegal_inst12_0, N_492, \cnt_2[1]\, - ldcheck2_2_sqmuxa_1_1, \inst_0_0[22]\, ldchkex_0, - \size_0[0]\, N_3758, miscout_11_sqmuxa_0, y_0_sqmuxa_2, - jump_1_sqmuxa_1_1, un1_trap_0_sqmuxa_0, trap_0_sqmuxa_2, - trap_0_sqmuxa_1, d29_0, illegal_inst35_4_0, \cnt_1[0]\, - icc_check_3_0_a3_1, \inst_0_0[23]\, un54_casaen, - \alusel_i_0_a5_0_0[0]\, N_3518_1, aluresult_8_sqmuxa_1, - inst_11_0, jump_0_sqmuxa_1_2, jump_0_sqmuxa_1_0, N_3749_1, - ADD_30x30_fast_I109_Y_0, N404_0, un3_op_2, un3_op_1, - aluresult_11_sqmuxa_4, inst_22_0, inst_21_1, - trap_0_sqmuxa_3_1, \inst_3[19]\, trap_0_sqmuxa_3_2, - ADD_30x30_fast_I117_Y_0, N392, trap54_1517_0, - \inst_3[20]\, ldcheck1_5_i_a6_1_1, un11_op, fins_0_a3_0, - SIGNED_2_1, ex_bpmiss_1_0_1630_tz_0, \inst_2[25]\, - ex_bpmiss_1_0_a5_3_0, ADD_30x30_fast_I125_Y_0, N380, - ldcheck1_5_i_a6_2_1, y6_0_0, read_1_sqmuxa_0, - y_0_sqmuxa_1_1, y11_0, un4_op_0, intack_1, \tt[6]\, - \tt[7]\, intack_0, \tt[4]\, \tt[5]\, aluop_2_1_0_a5_1_0, - icc_check8_1, N_3515_1, un1_icc_2_sqmuxa_1, icc_check7_2, - \icc[1]\, \icc[3]\, aluop_0_1_0_a5_1_0_0, - write_3_0_a3_0_2_0, force_a2_1, force_a2_0, - trap_0_sqmuxa_2_1, trap_0_sqmuxa_2_0, \inst_2[23]\, - trap27_0, trap_0_sqmuxa_1_0, nalign, inst_4_2, - \inst_2[22]\, inst_4_1, y10_3_0, inst_3_2_1, inst_3_2_0, - tt_2, \tt_0[4]\, \tt_0[5]\, tt_1, \tt[2]\, \tt[3]\, tt_0, - \tt[0]\, \tt[1]\, un29_casaen_5, \inst[8]\, un29_casaen_3, - \inst[5]\, un29_casaen_4, un29_casaen_1, \inst[11]\, - \inst[10]\, \inst[7]\, \inst[9]\, \inst[6]\, \inst[12]\, - wy_1_0_1, un5_irl_1, un5_irl_0, rett_1_0, rett, rett_0, - rett_0_0, rett_2, rett_3, \npc_iv_2[8]\, - \un6_fe_npc_m[6]\, \npc_iv_0[8]\, \npc_iv_2[10]\, - \un6_fe_npc_m[8]\, \npc_iv_1[10]\, \eaddress[10]\, - \pc_m[10]\, \npc_iv_0[10]\, \npc_iv_2[7]\, - \un6_fe_npc_m[5]\, \npc_iv_1[7]\, \eaddress[7]\, - \pc_m[7]\, \npc_iv_0[7]\, \npc_iv_2[9]\, - \un6_fe_npc_m[7]\, \npc_iv_1[9]\, \eaddress[9]\, - \pc_m[9]\, \npc_iv_0[9]\, \tmp_m[9]\, \npc_iv_2[4]\, - \un6_fe_npc_m[2]\, \npc_iv_1[4]\, \npc_iv_0[4]\, - \npc_iv_3[2]\, \npc_iv_1[2]\, \fpc[2]\, \npc_iv_2[3]\, - \npc_iv_1[3]\, \fpc[3]\, \npc_iv_0[3]\, \npc_iv_2[5]\, - I_13, \npc_iv_1[5]\, \npc_iv_0[5]\, - illegal_inst_7_iv_2_0_a5_4_2, N_472, N_229, N_523, N528, - I52_un1_Y, N409_2, I108_un1_Y, N529, N407_0, N410, N537, - N478_0, N544, I68_un1_Y, N385, I124_un1_Y, N545, N486, - N552_2, N497_1, N494, I243_un1_Y, N605, I212_un1_Y, - I232_un1_Y, N567_1, N583, I190_un1_Y, I210_un1_Y, - I244_un1_Y_0, N607, N_41, N_39_0, N454, - ADD_30x30_fast_I233_Y_0_a3_0, trap_0_sqmuxa_2_2, - trap_0_sqmuxa_1_2_i, \y_0[4]\, \pc_1[9]\, \y_1[20]\, - \logicout_m[20]\, N_351_1, \y_1[30]\, \y_0[25]\, - \y_1[23]\, \y_RNO_2[23]\, \aluop_RNIESJP4[2]\, N_259, - N_515, cwp_2_sqmuxa_i, tba_1_sqmuxa_3, \y_1[2]\, - \logicout_m[2]\, \bpdata_i_m[12]\, \y_1[7]\, \y_1[6]\, - \logicout_m[6]\, wim_1_sqmuxa, y_0_sqmuxa_1_2, - xc_wreg_0_sqmuxa, cwp_1_sqmuxa, \bpdata_i_m[26]\, - \bpdata_i_m_1[4]\, \bpdata_i_m[15]\, \bpdata_i_m[28]\, - \pc_1[2]\, \un6_fe_npc_m[0]\, N_241, illegal_inst_7_i_0, - \bpdata_i_m_1[7]\, \y_1[16]\, \logicout_m[16]\, - \ex_op1_i_m[22]\, \bpdata_i_m_1[6]\, N_22, N_6618, - \bpdata_i_m_2[5]\, \ex_op1_i_m[17]\, \bpdata_i_m_1[1]\, - \pc_1[31]\, \un6_fe_npc_m[29]\, \y_1[13]\, - \logicout_m[13]\, \pc_1[15]\, \un6_fe_npc_m[13]\, - \pc_1[17]\, \un6_fe_npc_m[15]\, \pc_1[20]\, - \un6_fe_npc_m[18]\, \pc_1[13]\, \un6_fe_npc_m[11]\, - \pc_1[12]\, I_56, \pc_1[18]\, \tmp_m[18]\, - \un6_fe_npc_m[16]\, \bpdata_i_m[10]\, y6_0, \y_0[3]\, - \y_1[8]\, \logicout_m[8]\, \y_0[15]\, \y_1[17]\, - \y_0[21]\, \y_1[22]\, \logicout_m[22]\, \y_0[31]\, - \y_1[28]\, \y_1[12]\, \logicout_m[12]\, \y_0[26]\, - \y_1[0]\, N_463, \pc_1[30]\, \un6_fe_npc_m[28]\, N_481, - \pc_1[26]\, \un6_fe_npc_m[24]\, N_15, \pc_1[27]\, I_173, - \y_1[27]\, N_420, \y_1[1]\, N_377, \y_1[24]\, N_230, - N_473_i, N_256_i_0, N_6696, N_519, N_232, N_172, N_410, - N_409, N_411, N_163, N_399, N_398, N_400, N_158, N_391, - N_390, N_392, N_6686, N_368, N_367, N_369, N_470, N_207, - N_469, y_1_sqmuxa, inst_14, N_3738, un1_ldcheck1_1, - un1_illegal_inst34, \bpdata_i_m[3]\, \icc_1[2]\, - icc_1_sqmuxa, \icc[2]\, N_127, N_126, N_128, - un1_de_ren1_NE_i_0, \rd[6]\, \un3_de_ren1[105]\, - \tmp[18]\, N403, ADD_30x30_fast_I216_Y_0_a3, - un2_rs1_NE_i_0, \inst[18]\, \inst[14]\, \inst[17]\, - N_8_0_i_0, N_29, N536, N481_2, annul_RNIVCQHS1, - \pc_1[21]\, \un6_fe_npc_m[19]\, \pc_1[28]\, - \un6_fe_npc_m[26]\, trap_1_sqmuxa, trap_0_sqmuxa_4, y11, - \maddress[2]\, result_1, dwt_1_sqmuxa, N_3721, ldcheck1, - \inst_0_RNIMRAH[23]\, rfe_1, rfe_1_1, rfe_1_2, bp_1, - ctrl_annul_i, \pc_1[8]\, \y_0[18]\, \y_1[19]\, - \logicout_m[19]\, inst_1, iflush_1, ticc_exception, - branch_1, ra_bpmiss_1, rd_0_sqmuxa, N_67, un52_casaen, - un19_rd, \rd_3[0]\, \inst_RNIHVSN2[24]\, wreg_1_8, - \rd_0[6]\, wreg_2_1, ldcheck2_2_sqmuxa_1_i, N_3834_2, - un4_op3, de_inst_0_sqmuxa_i_0, N_6697_i_0, - illegal_inst37_2, SIGNED_2, N_3742_i, un17_casaen, - tt_2_sqmuxa_1, un6_annul, icc_0_sqmuxa_1_i, werr_RNO, - irqen_0, trap_2_0, un1_trap_0_sqmuxa_5, icc_check8, - icc_check7_i, un13_op3, un8_op3, un12_op3, - un1_ld_1_sqmuxa_1, write_reg_2_sqmuxa, - annul_next_2_sqmuxa_1, un2_exbpmiss, - un1_annul_next_1_sqmuxa_3, N_149, ra_bpannul_1, - \un1_p0_6[0]\, N_117, N_96, N_150, annul_current, pv_6, - pv_4_0, pv_RNO_6, N_4239, \inst_2[29]\, un2_exbpmiss_0, - \icc_1[3]\, \icc_0[3]\, \icc_1[0]\, \icc[0]\, - icc_0_sqmuxa, cnt_2_sqmuxa, annul_4, cnt_3_sqmuxa, N465, - N462, hold_pc_2_m, I239_un1_Y, N581, N597, \tmp[9]\, N610, - \pc_1[25]\, \un6_fe_npc_m[23]\, I202_un1_Y_i, I238_un1_Y, - N579, N595_0, cp_disabled_6_sqmuxa, cp_disabled_1_sqmuxa, - trap_4, N_4033_i, N_211, ex_bpmiss_1, N_6695_i, - \icc_0[2]\, branch_1_sqmuxa_i, \y_1[10]\, - \logicout_m[10]\, \y_0[9]\, \d_1[0]\, \aluresult_m_i[0]\, - N802, N584, N522_0, N519_0, N585, N443_0, N440_0, N592, - I67_un1_Y, N436_1, I129_un1_Y, N600, N538, N535, N601_0, - N608, N546, N543_0, I272_un1_Y, N667, N616, N790, - I237_un1_Y, N802_0, I51_un1_Y, N460, I113_un1_Y, N585_0, - N519_1, N592_0, N530, N419_1, N416_1, N535_0, - I264_un1_Y_1, N651_1, N811_1, N782_0, N674_0, - I272_un1_Y_0, N667_0, N616_0, N790_0, I237_un1_Y_0, - N802_1, N676, N585_1, N443_1, N440_1, N519_2, N593_1, - N527_1, N600_0, N538_0, N535_1, N608_0, N546_0, N543_1, - N609, N407_1, N404_1, I272_un1_Y_i, N667_1, N616_1, - N790_1, I237_un1_Y_1, N650_1, N657, N672, N_57, N398_1, - N401_0, I234_un1_Y, N571_1, I194_un1_Y, I240_un1_Y, N599, - I206_un1_Y, N582_0, I214_un1_Y, rdata_3_sqmuxa, - rdata_3_sqmuxa_2, un1_de_ren1_1_5_i_0, - un1_de_ren1_1_6_i_0, rfe, un1_de_ren1_2, \pc_1[5]\, - \aluresult[5]\, \un6_ex_add_res_m[6]\, \y_0[5]\, - \d_i[19]\, \op1_m_0[19]\, \aluresult_m_0[19]\, \d[4]\, - \aluresult[4]\, \d[3]\, \op1_m_0[3]\, \aluresult_m_0[3]\, - \aluresult[20]\, \shiftin_17_m_0[20]\, - \un6_ex_add_res_m[21]\, \d_i[27]\, \op1_m_0[27]\, - \aluresult_m_0[27]\, \d_i[22]\, \op1_m_0[22]\, - \aluresult_m_0[22]\, \d_i[21]\, \aluresult[21]\, - \d_i[17]\, \op1_m_0[17]\, \aluresult_m_0[17]\, \d_i[7]\, - \op1_m_0[7]\, \aluresult_m_0[7]\, \shiftin_17_m_0[29]\, - \un6_ex_add_res_m[30]\, \aluresult[24]\, - \shiftin_17_m_0[24]\, \un6_ex_add_res_m[25]\, - \aluresult[25]\, \un6_ex_add_res_m[26]\, \d_i[26]\, - \op1_m_0[26]\, \aluresult_m_0[26]\, \d_i[25]\, - \op1_m_0[25]\, \aluresult_m_0[25]\, \d_i[24]\, \d_i[23]\, - \op1_m_0[23]\, \aluresult_m_0[23]\, \aluresult[0]\, - \shiftin_17_m[1]\, \d_i[30]\, \op1_m_0[30]\, - \aluresult_m_0[30]\, \d_i[16]\, \op1_m_0[16]\, - \aluresult_m_0[16]\, \d_i[6]\, \op1_m_0[6]\, - \aluresult_m_0[6]\, \d_i[29]\, \d_i[28]\, \aluresult[28]\, - \d[2]\, \op1_m_0[2]\, \aluresult_m_0[2]\, \bpdata_i_m[9]\, - \bpdata_i_m_0[13]\, \ex_op1_i_m[18]\, \bpdata_i_m_1[2]\, - \ex_op1_i_m[16]\, \bpdata_i_m_1[0]\, \bpdata_i_m[8]\, - \aluresult[17]\, \un6_ex_add_res_m[18]\, - \shiftin_17_m_0[21]\, \un6_ex_add_res_m[22]\, - \aluresult[7]\, \shiftin_17_m_0[7]\, ldbp2_0_RNIKEHUF, - \d[1]\, \op1_m_0[1]\, \aluresult_m_0[1]\, - un1_illegal_inst33, \aluresult[31]\, \shiftin_17_m_0[31]\, - \un6_ex_add_res_m[32]\, \bpdata_i_m[11]\, \d_i[8]\, - \op1_m_0[8]\, \aluresult_m_0[8]\, \d_i[9]\, \op1_m_0[9]\, - \aluresult_m_0[9]\, \d_i[15]\, \op1_m_0[15]\, - \aluresult_m_0[15]\, \aluresult[27]\, \d_i[14]\, - \op1_m_0[14]\, \aluresult_m_0[14]\, \ex_op1_i_m[19]\, - \bpdata_i_m_1[3]\, \aluresult[10]\, \shiftin_17_m_0[10]\, - \un6_ex_add_res_m[11]\, \aluresult[11]\, - \shiftin_17_m_0[11]\, \un6_ex_add_res_m[12]\, - \aluresult[18]\, \shiftin_17_m_0[18]\, - \un6_ex_add_res_m[19]\, \aluresult[12]\, - \shiftin_17_m_0[12]\, \un6_ex_add_res_m[13]\, - \aluresult[3]\, ldbp2_2_RNI7G0C6, \aluresult[8]\, - \pc_1[10]\, intack, \aluresult[14]\, \shiftin_17_m_0[14]\, - \un6_ex_add_res_m[15]\, \pc_1[29]\, \un6_fe_npc_m[27]\, - \pc_1[16]\, \un6_fe_npc_m[14]\, \aluresult[23]\, - \un6_ex_add_res_m[24]\, \d_i[12]\, \op1_m_0[12]\, - \aluresult_m_0[12]\, \d_i[11]\, \op1_m_0[11]\, - \aluresult_m_0[11]\, \d_i[13]\, \op1_m_0[13]\, - \aluresult_m_0[13]\, \aluresult[6]\, \shiftin_17_m_0[6]\, - ldbp2_2_RNI5355F, \aluresult[26]\, \un6_ex_add_res_m[27]\, - \y_1[11]\, \logicout_m[11]\, \aluresult[22]\, - \shiftin_17_m_0[22]\, \un6_ex_add_res_m[23]\, \d[0]\, - \op1_m_0[0]\, \aluresult_m_0[0]\, un1_aop2_1_sqmuxa, - \aluresult[19]\, \shiftin_17_m_0[19]\, - \un6_ex_add_res_m[20]\, tt_i, N_3749, N_3748, - \aluresult[15]\, \shiftin_17_m_0[15]\, - \un6_ex_add_res_m[16]\, \pc_1[19]\, \un6_fe_npc_m[17]\, - \pc_1[23]\, \un6_fe_npc_m[21]\, \un6_ex_add_res_m[29]\, - aluresult_10_sqmuxa, aluresult_12_sqmuxa, \y_1[29]\, - \d_i_0[5]\, N_407, N_408, \y_1[14]\, N_385, N_6684_i_0, - N_348, N_236, N_346, N_3840, N_500, N_6829, - \un1_iu0_6[3]\, N_6838, N_6841, N_6853, \un1_iu0_5[96]\, - N_6856, \un1_iu0_5[91]\, N_6862, N_6865, \un1_iu0_6[0]\, - N_6868, N_6871, \un1_iu0_6[7]\, N_6874, \un1_iu0_5[94]\, - N_6877, N_6883, \un1_iu0_6[15]\, N_6886, \un1_iu0_6[16]\, - \un1_iu0_5[82]\, N_6889, \op2_RNI1LHG[1]\, N_6895, - \un1_iu0_6[18]\, N_6898, \un1_iu0_5[79]\, N_6901, - \un1_iu0_5[80]\, N_6904_i, \un1_iu0_5[87]\, N_6907, - \un1_iu0_5[68]\, N_6910, \un1_iu0_6[11]\, N_6913, - \un1_iu0_5[85]\, N_6916, \un1_iu0_5[97]\, N_6919, N_174, - N_413, N_412, N_414, N_153, N_383, N_382, N_384, N_220, - \ex_op1_i_m[1]\, \op1_i_m[1]\, \bpdata_i_m[1]\, - \bpdata_i_m[5]\, \ex_op1_i_m[6]\, \op1_i_m[6]\, - \bpdata_i_m[6]\, \bpdata_i_m[7]\, ps_1, s_m, ps_m, - \result_m[6]\, \bpdata_i_m[0]\, rdata200, rdata_4_sqmuxa, - N_6529, ANC1, CO1_0, \un6_ex_add_res_s1_i[27]\, - \un6_ex_add_res_s1_i[19]\, \op2[18]\, - \un6_ex_add_res_s1_i[17]\, \op2[16]\, N794_i, - \un6_ex_add_res_s1_i[13]\, N430, - ADD_33x33_fast_I246_Y_0_a3_0, \un6_ex_add_res_s1_i[11]\, - \un6_ex_add_res_s1[8]\, \op2[7]\, N672_0, \d_1[31]\, - \op1_m_i[31]\, \aluresult_m_i[31]\, \d_1[30]\, - \op1_m_i[30]\, \aluresult_m_i[30]\, \d_1[28]\, - \op1_m_i[28]\, \aluresult_m_i[28]\, \d_1[27]\, - \op1_m_i[27]\, \aluresult_m_i[27]\, \d_1[26]\, - \op1_m_i[26]\, \aluresult_m_i[26]\, \d_1[25]\, - \op1_m_i[25]\, \aluresult_m_i[25]\, \d_1[24]\, - \op1_m_i[24]\, \aluresult_m_i[24]\, \d_1[23]\, \d_1[22]\, - \op1_m_i[22]\, \aluresult_m_i[22]\, \d_1[21]\, \d_1[20]\, - \op1_m_i[20]\, \aluresult_m_i[20]\, \d_1[19]\, - \op1_m_i[19]\, \aluresult_m_i[19]\, \d_1[18]\, - \op1_m_i[18]\, \aluresult_m_i[18]\, \d_1[17]\, - \op1_m_i[17]\, \aluresult_m_i[17]\, \d_1[16]\, - \op1_m_i[16]\, \aluresult_m_i[16]\, \d_1[15]\, - \op1_m_i[15]\, \aluresult_m_i[15]\, \d_1[14]\, - \op1_m_i[14]\, \aluresult_m_i[14]\, \d_1[13]\, - \aluresult[13]\, \d_1[12]\, \op1_m_i[12]\, - \aluresult_m_i[12]\, \d_1[11]\, \op1_m_i[11]\, - \aluresult_m_i[11]\, \d_1[10]\, \d_1[9]\, \aluresult[9]\, - \d_1[8]\, \op1_m_i[8]\, \aluresult_m_i[8]\, \d_1[7]\, - \op1_m_i[7]\, \aluresult_m_i[7]\, \d_1[6]\, \op1_m_i[6]\, - \aluresult_m_i[6]\, \d_1[5]\, \op1_m_i[5]\, - \aluresult_m_i[5]\, \d_1[4]\, \d_1[3]\, \op1_m_i[3]\, - \aluresult_m_i[3]\, \d_1[2]\, \op1_m_i[2]\, - \aluresult_m_i[2]\, \d_1[1]\, \aluresult_m_i[1]\, - \data_0_1[26]\, \dco_m_1[122]\, \data_0_m[26]\, - \data_0_1_4[18]\, \data_0_1[25]\, \dco_m_1[121]\, - \data_0_m[25]\, \data_0_1[17]\, \data_0_1[12]\, - \dco_m_0[108]\, \data_0_1_4[9]\, \data_0_1[10]\, - \dco_m_0_i[106]\, \data_0_1_1[12]\, \data_0_1[8]\, - \dco_m_0_i[104]\, \data_0_1[6]\, \dco_m_i[118]\, - \dco_m_i[102]\, \data_0_1[4]\, N_3456, \data_0_1[3]\, - \data_0_1[2]\, \dco_m_i[114]\, \dco_m_i[98]\, - \data_0_1[1]\, \data_0_1[0]\, \data_0_1[21]\, - \dco_m_0[117]\, \data_0_m[21]\, \un6_ex_add_res_s1_i[3]\, - \shiftin_17_m_0[13]\, \un6_ex_add_res_m[14]\, - \aluresult[1]\, \data_0_1[7]\, \dco_m_i[119]\, - \dco_m_i[103]\, \d_i[10]\, \op1_m_0[10]\, - \aluresult_m_0[10]\, \data_0_1[11]\, \dco_m_0[107]\, - N_6844, N_57_i_0, N401_1, N609_0, N543_2, N608_1, - I145_un1_Y, N584_0, N522_1, \un6_ex_add_res_s1_i[18]\, - I239_un1_Y_0, \un6_ex_add_res_s1_i[23]\, N657_0, N641_1, - N657_1, N672_1, \data_0_1[5]\, N661, N676_0, N_6640_i, - \un6_ex_add_res_s1_i[28]\, I263_un1_Y_i, N_6892, - \un1_iu0_5[93]\, N808, N649_1, N633_1, N808_0, I259_un1_Y, - N796, N808_1, \un6_ex_add_res_s1_i[15]\, N799_0, N799_1, - \un6_ex_add_res_s1[32]\, I259_un1_Y_0, N625_0, N796_0, - I259_un1_Y_1, N625_1, N796_1, \un6_ex_add_res_s1_i[22]\, - I269_un1_Y_0, N661_0, N676_1, s_2_sqmuxa, logicout22_1, - \aluresult[2]\, \shiftin_17_m_0[2]\, jmpl_RNIR18H6, N_334, - N_3838_i_0, \data_0_1[18]\, \dco_m_0[114]\, - \data_0_m[18]\, \aluresult[16]\, \shiftin_17_m_0[16]\, - \un6_ex_add_res_m[17]\, \aluresult[30]\, - \shiftin_17_m_0[30]\, \un6_ex_add_res_m[31]\, s_1_iv, - ps_i_m, s_i_m, \result_i_m[7]\, \icc_8_1[1]\, \icc_2[1]\, - N_6859, \data_0_1[22]\, \dco_m_0[118]\, \data_0_m[22]\, - \data_0_1[24]\, \un6_ex_add_res_s1_i[21]\, N786_i, N_6835, - \un6_ex_add_res_s1[4]\, \op2[3]\, \data_0_1[23]\, - \dco_m_0[119]\, \data_0_m[23]\, \un6_ex_add_res_s1[7]\, - \op2[6]\, N782_1, N674_1, N514_0, N511_0, \data_0_1[20]\, - \dco_m_0[116]\, \data_0_m[20]\, N_6847, \d_i[20]\, - \op1_m_0[20]\, \aluresult_m_0[20]\, \data_0_1[28]\, - \dco_m_1[124]\, \data_0_m[28]\, rdata_6_sqmuxa, - \data_0_1[29]\, \dco_m_1[125]\, \data_0_m[29]\, - \data_0_1[30]\, \dco_m_1[126]\, \data_0_m[30]\, N_6850, - \un1_iu0_5[95]\, bpdata6, N_3946, N_3950, N_3946_1, d11, - \icc_8[1]\, \size[1]\, N_3755, jump_0_sqmuxa, - read_1_sqmuxa_i, un3_op_i, \size[0]\, N_3757, I271_un1_Y, - N665_0, N614_1, I271_un1_Y_i, I271_un1_Y_i_0, N665_1, - N614_2, \un6_ex_add_res_s1_i[20]\, - \un6_ex_add_res_s1_i[12]\, \op2[11]\, N609_1, N407_2, - N404_2, enaddr_2_sqmuxa, iflush_4, - \un6_ex_add_res_s1_i[6]\, \pc_1[7]\, - \un6_ex_add_res_s1_i[25]\, N778_1, \tmp[24]\, \pc_1[24]\, - \tmp_m[24]\, \un6_fe_npc_m[22]\, \icc_8_m_i[1]\, - \icc_1[1]\, \icc_0[1]\, \d_i[31]\, \op1_m_0[31]\, - \aluresult_m_0[31]\, \data_0_1[15]\, \dco_m_0[111]\, - \data_0_1[14]\, \dco_m_0[110]\, N592_1, N530_0, - \pc_1[22]\, \un6_fe_npc_m[20]\, \un6_ex_add_res_s1_i[16]\, - \op2[15]\, N814_0, I249_un1_Y, N668_0, - \un6_ex_add_res_s1_i[1]\, \op2[0]\, - \un6_ex_add_res_s1[14]\, \d_i[18]\, \op1_m_0[18]\, - \aluresult_m_0[18]\, N_4042, privileged_inst_5, N_4039, - \tt_0[3]\, \tt_9_1[0]\, \tt_1[2]\, N_4043_i, \tt_1[1]\, - N_16735_tz, \bpdata_i_m_1[5]\, \data_0_1[27]\, - \dco_m_1[123]\, \data_0_m[27]\, \data_0_1[13]\, - \dco_m_0[109]\, \rdata_9_m[8]\, N_51_i, N_51_i_0, - \un6_ex_add_res_s1_i[5]\, \op2[4]\, N678_i, - \un6_ex_add_res_s1[29]\, N_51_i_1, \shiftin_17_m_0[4]\, - \un6_ex_add_res_m[5]\, \pc_1[4]\, I260_un1_Y, - \data_0_1[9]\, \dco_m_0[105]\, \un6_ex_add_res_s1_i[31]\, - \shiftin_17_m_0[9]\, \un6_ex_add_res_m[10]\, N600_1, - N538_1, \un6_ex_add_res_s1_i[2]\, N_448, \un1_iu0_5[90]\, - \logicout_5_0_i_0[24]\, N_447, N_6880_i, N_6832, - \un1_iu0_5[70]\, inst_3_2, \me_nullify2_1_2\, - nullify_1_sqmuxa, wy_1_0_a3_0_4, illegal_inst12, - illegal_inst12_tz_tz, \inst_RNI884O1[22]\, inst_2_0, - \tt_RNO_0[0]\, annul_1tt_N_7, annul_5, branch_RNIA8KSK, - branch_RNIMJA92, N437_1, N440_2, rstate_8_0, d28_0, - un5_op3, logicout19_0, wy_1_0_a3_1, aluresult_2_sqmuxa, - mcasa, d25, N_478, cwp_1_sqmuxa_0, N_3739, N_6681_1, - write, write_3_tz, N_263, ex_bpmiss_1_0_1630_0, N_475, - ex_bpmiss_1_0_a5_6_0, wicc_1, wicc_1_0_a3_0_0, N_143, - \un1_addout_12\, annul_RNIVI35T, \fbranch\, annul_1tt_N_5, - CO1_0_tz, \logicout_5_0_i_0_tz[24]\, un1_illegal_inst11_0, - un1_illegal_inst11_2_0_a5_0, illegal_inst11_0_a5_0, - nobp_RNO_0, N_16827_tz, N_85, inull_RNIFV6VG2_0, - ld_1_sqmuxa, \inst_0_RNIPQUJ[21]\, wy_1_1, N_97, N_3718, - annul_RNIETIP, jmpl_2, \icc_0[0]\, inst_0_2, un1_addout, - \eaddress[31]\, de_inull, nobp_1, un1_reg, N_6322, N_6323, - \rstate_ns[1]\, N_6323s, N_4600, \inst_0[0]\, N_4601, - \inst_0[1]\, N_4602, \inst_0[2]\, N_4603, \inst_0[3]\, - N_4604, \inst_0[4]\, N_4605, N_4607, N_4609, N_4610, - N_4611, N_4612, N_4613, N_4614, N_4615, N_4616, N_4617, - N_4618, N_4619, N_4620, N_4621, N_4623, N_4625, N_4626, - N_4627, N_4628, N_4629, N_4630, N_4631, N361, N362, N364, - N365, N367, N371, N383, N386, N434_1, N498_0, N473_0, - N379, N_44, I170_un1_Y, N596, N604, I184_un1_Y, - ADD_30x30_fast_I218_un1_Y, N443_2, N542, N487_1, N484_1, - N483, I130_un1_Y, N495_1, N550, N476_0, N480, N527_2, - I176_un1_Y, N397_2, N398_2, N400, N422, N419_2, N388, - N391, N467_1, N416_2, N412, N415, N421_2, N425, N427, - N459, N460_0, N463_0, N464_1, I118_un1_Y_i, N538_2, - N479_0, N539, N546_1, N488_1, N547, I134_un1_Y, N499, - N496_2, N554, N555, N523, N530_1, N531, I172_un1_Y, N598, - N606, N471, N472, I110_un1_Y, N475, I114_un1_Y, N534, - \inst_1[31]\, \inst_1[30]\, wreg_6, \rd_1[3]\, N_3764, - \y_2[0]\, \result[0]\, N_4064, \eaddress[21]\, I_20, - N_4049, I_122, N_3768, \y_1[4]\, \result[4]\, N_3769, - \y_1[5]\, \result_0[5]\, \y_2[5]\, \y_2[4]\, \pc_4[3]\, - N_3886, \fe_pc[9]\, \pc_0[9]\, N_4046, N_4052, \fpc[9]\, - \pc_4[9]\, I_38, \inst_0_RNO[31]\, N_3784, \y_2[20]\, y14, - N_3897, \fe_pc[20]\, \pc[20]\, \xc_trap_address[20]\, - \fpc[20]\, \tba[8]\, \aluop_RNIGM3N1[2]\, N_3794, - \y_2[30]\, \result_0[30]\, N_3907, \fe_pc[30]\, \pc[30]\, - N_3789, \y_1[25]\, \result_0[25]\, \y_2[25]\, N_3787, - \y_2[23]\, N_3889, \fe_pc[12]\, \pc[12]\, \bpdata[31]\, - \un3_de_ren1[103]\, \DWACT_ADD_CI_0_partial_sum[0]\, - \un3_de_ren1[104]\, I_13_1, I_14_0, \rd_1[5]\, \rd_2[5]\, - \rd_0[7]\, \rd_1[7]\, \rd_2[7]\, \rd_0[2]\, - \de_raddr1_2[5]\, I_13_2, un26_rs1opt, \de_raddr1_2[6]\, - I_14_1, \de_raddr1_1[5]\, I_13_3, \un3_de_ren1[96]\, - rs1mod, \de_raddr1_1[6]\, I_14_2, \un3_de_ren1[97]\, - error_RNO, error, \rd_1[4]\, \rd_1[6]\, \icc_2[2]\, - N_6357, \de_raddr1_2[4]\, - \DWACT_ADD_CI_0_partial_sum_0[0]\, \de_raddr1_1[4]\, - \DWACT_ADD_CI_0_partial_sum_1[0]\, rett_i, su, s, ps, - \asi[0]\, \inst_1[5]\, \y_1[3]\, \y_2[2]\, \y_2[10]\, - N_3766, \result_0[2]\, N_3771, \y_2[7]\, \result_0[7]\, - N_3770, \y_2[6]\, \result_0[6]\, N_3724, N_3722, N_3723, - \ncwp_3[1]\, N_3726, \wim_1[2]\, \wim_1[6]\, \ncwp_3[2]\, - N_3727, N_3725, \cwp_0[0]\, N_3871, \result_0[1]\, - \cwp_1[1]\, \wim[2]\, \bpdata[15]\, N_3879, \pc[2]\, - \bpdata[28]\, \inst_0_RNIFKEG[25]\, N_4182, - \inst_0_RNO[30]\, illegal_inst35, bp_1_1, wicc_1_0, - wicc_0, un1_ldcheck1, \inst_0_0[21]\, icc_check9_2, - call_hold5, N_33, \DWACT_ADD_CI_0_partial_sum_2[0]\, - un3_reg, N_35, I_13_0, N_37, I_14, nerror_1, - \inst_0_RNO[28]\, \un3_de_ren1[128]\, \un3_de_ren1[129]\, - \un3_de_ren1[130]\, \un3_de_ren1[131]\, - \un3_de_ren1[132]\, \un3_de_ren1[133]\, - \un3_de_ren1[135]\, \un3_de_ren1[136]\, - \un3_de_ren1[137]\, \un3_de_ren1[138]\, - \un3_de_ren1[139]\, \un3_de_ren1[141]\, - \un3_de_ren1[142]\, \un3_de_ren1[143]\, - \un3_de_ren1[144]\, \inst_0[12]\, \un3_de_ren1[145]\, - \un3_de_ren1[146]\, \un3_de_ren1[147]\, - \un3_de_ren1[148]\, \un3_de_ren1[149]\, - \un3_de_ren1[119]\, \un3_de_ren1[120]\, - \un3_de_ren1[121]\, \un3_de_ren1[123]\, - \un3_de_ren1[125]\, \un3_de_ren1[127]\, \cnt_2[0]\, - \rd_2[1]\, \inst_0_RNO[26]\, \inst_0_RNO[27]\, N_4045, - ldbp2_1_RNIL7Q55, \pc_4[2]\, \inst_0_RNO[29]\, - \inst_0_RNO[0]\, \inst_0_RNO[1]\, \inst_0_RNO[2]\, - \inst_0_RNO[3]\, \inst_0_RNO[4]\, \inst_0_RNO[5]\, - \inst_0_RNO[7]\, \inst_0_RNO[9]\, \inst_0_RNO[10]\, - \inst_0_RNO[11]\, \inst_0_RNO[13]\, \inst_0_RNO[14]\, - \inst_0_RNO[15]\, \inst_0_RNO[16]\, \inst_0_RNO[17]\, - \inst_0_RNO[18]\, \inst_0_RNO[19]\, \inst_0_RNO[20]\, - \inst_0_RNO[23]\, \inst_0_RNO[25]\, N_3339, N_375, - \inst_2[27]\, \inst_1[28]\, N_3340, branch_3, branch_7, - N_3341, \inst_2[26]\, N_3343, branch_4, branch_8, - branch_2, branch_6, N_3883, \fe_pc[6]\, \pc_0[6]\, - \xc_trap_address[6]\, N_3885, \fpc[8]\, \fe_pc[8]\, - \pc[8]\, N_3780, \y_2[16]\, \result_0[16]\, \op1[22]\, - \bpdata[6]\, N_3703_i, \pc_RNI8CM4[6]\, \fpc[6]\, N_3908, - \fe_pc[31]\, \pc_0[31]\, \xc_trap_address[31]\, \fpc[31]\, - N_3903, \fe_pc[26]\, \pc_0[26]\, \bpdata[24]\, - \xc_vectt_1[2]\, \bpdata[1]\, N_3894, \fe_pc[17]\, - \pc[17]\, N_4061, \eaddress[18]\, I_98, - \xc_trap_address[17]\, \fpc[17]\, \tba[5]\, N_3898, - \fpc[21]\, \fe_pc[21]\, \pc[21]\, \xc_trap_address[13]\, - \tba[1]\, N_3895, \fpc[18]\, \fe_pc[18]\, \pc[18]\, - \xc_trap_address[12]\, \fpc[12]\, \tba[0]\, N_3906, - \fe_pc[29]\, \pc[29]\, N_3890, \fpc[13]\, N_4074, I_210, - N_4051, I_31, N_4053, I_45, N_3777, \y_2[13]\, - \result_0[13]\, \fe_pc[13]\, \pc[13]\, N_4058, - \eaddress[15]\, I_77, N_4060, \eaddress[17]\, I_91, - N_4056, N_4063, \eaddress[20]\, I_66, I_115, N_4055, - xc_exception_1, \xc_trap_address[18]\, - \xc_trap_address[8]\, \xc_trap_address[15]\, \y_1[9]\, - \y_1[18]\, \y_1[26]\, N_4069, \fpc[26]\, \eaddress[26]\, - I_166, bpmiss_1_i_0, rett_1_1, N_3767, \y_2[3]\, - \result_0[3]\, mulstep_1, N_3772, \y_2[8]\, \result[8]\, - N_3775, \y_2[11]\, \result_0[11]\, N_3779, \y_1[15]\, - \result_0[15]\, \y_2[15]\, N_3781, \y_2[17]\, - \result_0[17]\, wy_3, \y_1[21]\, \y_2[21]\, N_3786, - \y_2[22]\, ex_ymsb_1, \y_1[31]\, \y_2[31]\, N_3776, - \y_2[12]\, \result[12]\, N_3792, \y_2[28]\, - \result_0[28]\, N_3790, \y_2[26]\, \result[26]\, - \result_0[24]\, \y_2[24]\, \y_2[1]\, \result_0[14]\, - \result_0[18]\, \y_2[18]\, \result_0[27]\, \y_2[27]\, - N_483, N_3880, N_3888, \tba[6]\, N_4073, \fpc[30]\, - \pc_4[30]\, I_203, \xc_trap_address[30]\, \fe_pc[11]\, - \pc[11]\, \xc_vectt_1[4]\, \xc_trap_address[11]\, N_3892, - \fpc[15]\, \fe_pc[15]\, \pc[15]\, \tba[3]\, \pc[3]\, - N_3882, \fpc[5]\, \pc_0[5]\, \xc_trap_address[21]\, - \tba[9]\, I_52, N_4054, N_3904, \fe_pc[27]\, \pc_0[27]\, - N_4070, \fpc[27]\, \eaddress[27]\, jump, - \xc_trap_address[27]\, \tba[15]\, \xc_trap_address[26]\, - \tba[18]\, rstate_6314_d, N_6763_i, \pc_RNO[2]\, - \pc_RNO[3]\, \pc_RNO[5]\, \pc_RNO[6]\, \pc_RNO[8]\, - \pc_RNO[9]\, \pc_RNO[10]\, \fpc[10]\, \pc_RNO[11]\, - \fpc[11]\, \pc_RNO[12]\, \pc_RNO[13]\, \pc_RNO[15]\, - \pc_RNO[17]\, \pc_RNO[18]\, \pc_RNO[20]\, \pc_RNO[21]\, - \pc_RNO[26]\, \pc_RNO[27]\, \pc_RNO[29]\, \fpc[29]\, - \pc_RNO[30]\, N_6922_i, inst_5_1, \pc_RNO[14]\, - \xc_trap_address[14]\, \fpc[14]\, \tba[2]\, \fe_pc[14]\, - \pc[14]\, N_3891, I_73, N_4057, \eaddress[14]\, - I62_un1_Y_i, I137_un1_Y_i, I221_un1_Y_0, I183_un1_Y_i, - N468, N_14, N_59, N_11, \pc_RNO[28]\, - \xc_trap_address[28]\, \fpc[28]\, I_186, N_4071, - \fe_pc[28]\, \pc[28]\, N_3905, inst, N_318, N_170, werr, - werr_0, wicc_2, \icco[2]\, N_4187, N_4177, wicc_3, - \icc_16[2]\, \un9_icc_check_bp\, nobp, N_4021, - \un3_de_ren1[122]\, un1_wcwp, \y_2[19]\, N_3783, - \result_0[19]\, \inst_RNIVASI1[30]\, \asi[3]\, - \inst_1[8]\, \asi[1]\, \inst_1[6]\, \un3_de_ren1[126]\, - \ncwp[0]\, \ncwp[2]\, \cwp_0[2]\, N_3344, N_3342, N_3361, - \inst_2[24]\, un10_op, wreg_1_9, wreg_7, N_6350, - xc_wreg_1, N_4624, \rsel1_RNO_0[0]\, \rd_1[2]\, - annul_RNILQG71, ld_2, write_reg_0_sqmuxa_1, - \inst_0_RNO[24]\, \osel[0]\, ldcheck2_0_sqmuxa_1, - ldcheck2_0_sqmuxa, ldcheck1_1_sqmuxa_1, N_518, - \inst_2[31]\, \inst_2[30]\, trap2, trap_0_sqmuxa, - \maddress_0[3]\, \maddress[4]\, trap_0_sqmuxa_6, - tt_0_sqmuxa, tt_1_sqmuxa_1, \tt2[5]\, N_4209, N_4210_i_0, - \tt_1[5]\, \nullify2_0_sqmuxa\, \tt2[3]\, N_4201_i_0, - N_4207, \tt_2[3]\, un6_op, N_6825_i, \inst_0_RNO[22]\, - N_4622, un3_op, rett_1_2, jmpl_3, wreg_1_10, wreg_1_11, - write_reg, un1_ld_1_sqmuxa, annul_next_14, un1_exbpmiss, - wicc_1_1, annul_1_1, \un3_de_ren1[118]\, \pc_RNO[7]\, - I_24, N_4050, hold_pc_0_sqmuxa, \ldlock_3_0\, \ldlock_2\, - ctrl_pv, N_3014, \icc_16[0]\, \icc_3_i_0[0]\, aluadd, - \icc_16[1]\, N_4175, N_4176, N_4185, N_4180, N_4186, - N_4181, \icco[0]\, \icco[1]\, wicc_1_2, icc_0_sqmuxa_0, - pil_0_sqmuxa, \icc_2[0]\, \icc_3[1]\, \icc_2[3]\, - \cnt_RNO[1]\, N_3899, \fe_pc[22]\, \pc[22]\, I_129, - N_4065, \fpc[22]\, \eaddress[22]\, \pc_RNO[22]\, N_3034, - \hold_pc_7\, annul_2_0, N_3033_1_i, \inst_0_RNO[8]\, - N_4608, \xc_trap_address[9]\, \xc_vectt_1[5]\, - \pc_RNO[25]\, \xc_trap_address[25]\, \fpc[25]\, - \fe_pc[25]\, \pc_0[25]\, N_3902, I_156, \inst_0_RNO[6]\, - N_4606, \un3_de_ren1[124]\, \un3_de_ren1[134]\, N_4068, - \eaddress[25]\, N594, I168_un1_Y_i, trap_3, un2_irl, - \rd_3[1]\, \rd_2[2]\, \inst_RNIJ0JA[25]\, \inst_2[28]\, - branch_4_i, branch_8_i, branch_7_i, branch_3_i, - branch_6_i, branch_2_i, N_3348, N_3351, N_3349, N_3350, - N_3346, N_3347, I_9, \pc_4[4]\, N_4047, N_3774, - \result[10]\, \y_2[9]\, et_2_sqmuxa, et_0_sqmuxa, y6_2, - et_1_0, N_3029, et_m, \imm[0]\, intack_3, \inst_3[31]\, - \inst_3[30]\, N_3473, \data_0_2[12]\, \rdata_5[8]\, ld_3, - \maddress_0[1]\, \imm[1]\, \op1[2]\, \imm[2]\, \imm[3]\, - \un1_p0_6[356]\, \imm[4]\, \result_0[4]\, \imm[5]\, - \op1[6]\, \imm[6]\, \imm[7]\, \imm[8]\, \result_0[8]\, - \maddress[9]\, \un1_p0_6[361]\, \imm[9]\, \result[9]\, - \op1[10]\, \imm[10]\, \result_0[10]\, \imm[11]\, - \imm[12]\, \result_0[12]\, \imm[13]\, un14_casaen_s0, - \op1[14]\, \imm[14]\, \op1[15]\, \imm[15]\, \op1[16]\, - \imm[16]\, un14_casaen_s1, \imm[17]\, \op1[18]\, - \imm[18]\, \op1[19]\, \imm[19]\, \op1[20]\, \imm[20]\, - \result_0[20]\, \un1_p0_6[373]\, \imm[21]\, \rsel2[0]\, - \imm[22]\, \op1[23]\, \imm[23]\, \result_0[23]\, - \op1[24]\, \un1_p0_6[376]\, \imm[24]\, \op1[25]\, - \imm[25]\, \imm[26]\, \result_0[26]\, \op1[27]\, - \imm[27]\, \un1_p0_6[380]\, \imm[28]\, \op1[29]\, - \un1_p0_6[381]\, \imm[29]\, \op1[30]\, \imm[30]\, - \op1[31]\, \un1_p0_6[383]\, \imm[31]\, N_4943, N_5246, - mexc_0, N410_0, N536_0, N563, N473_1, N476_1, N516, - N513_0, N512, N579_0, N517, N586, N524_0, N521, N520_0, - N594_0, N532, N529_0, N528_0, N595_1, N533, N602, N540, - N537_0, N603, N571_2, N587_0, I183_un1_Y, N488_2, N415_0, - N478_1, N479_1, N442, N422_0, N439_0, \data_0_2[20]\, - N461, N425_0, N530_2, N577, N448, N449, N454_0, N455_0, - \data_0_0[18]\, I111_un1_Y_i, N464_2, N575_0, N582_1, - N583_0, N446, N424_0, N412_0, N598_0, N599_0, N606_0, - N544_0, ADD_33x33_fast_I246_Y_0_a3, N427_0, N430_0, - N403_0, N406, N451_0, N400_0, N406_0, N410_1, N504, N469, - N528_1, N544_1, N548, N500_1, N497_2, N509, N516_0, - N513_1, N512_0, N594_1, N532_0, N529_1, N595_2, N533_0, - N602_0, N403_1, N415_1, N479_2, N482_0, N537_1, N446_0, - N461_0, N425_1, N458, N514_1, N577_0, N666_1, N413_1, - N451_1, N452_0, N448_0, N574_1, N508, N575_1, N520_1, - N517_0, N583_1, N590_0, N591_0, N598_1, N599_1, N664_1, - N606_1, N607_0, I203_un1_Y, I243_un1_Y_0, N472_0, - I81_un1_Y, N412_1, N540_0, N541_1, N567_2, N536_1, N427_1, - N546_2, N442_0, N_30, N400_1, N410_2, N528_2, N430_1, - N544_2, N406_1, N549, N586_0, N521_0, N524_1, N520_2, - N587_1, N525_0, N594_2, N532_1, N529_2, N533_1, N602_1, - N540_1, N537_2, N536_2, N610_0, N548_0, N545_0, - I151_un1_Y, I205_un1_Y, I245_un1_Y, N415_2, N442_1, - N436_2, N437_2, N425_2, I121_un1_Y, N_53_i, I113_un1_Y_i, - N569_1, N577_1, I197_un1_Y, I204_un1_Y_0, N448_1, N449_0, - N454_1, N455_1, N516_1, N517_1, N452_1, N582_2, N583_2, - N591_1, N599_2, N606_2, N598_2, I203_un1_Y_0, - I243_un1_Y_1, N446_1, N424_1, N412_2, N590_1, - ADD_33x33_fast_I246_Y_0_a3_1, ADD_33x33_fast_I274_Y_0_a3, - N403_2, N507, N_6527, N_4204, \tt_0[0]\, \tt2[0]\, - N_4200_i_0, \laddr[1]\, \size_2[0]\, \size_2[1]\, - \logicout_3[3]\, \logicout_4[3]\, N_3319, N_3562, N_3530, - N_3626, N_3881, \fpc[4]\, \fe_pc[4]\, \pc_0[4]\, - \eaddress[6]\, \xc_trap_address[4]\, \xc_vectt_1[0]\, - \logicout_3[5]\, \logicout_3[6]\, \logicout_4[6]\, N_3324, - N_3532, N_3533, N_3565, N_3629, \wim[5]\, N_4048, - \eaddress[5]\, \eaddress[3]\, \logicout_3[9]\, - \logicout_4[9]\, N_3220, \pc_2[9]\, N_3250, \pc_3[9]\, - \xc_result[9]\, N_3400, N_3536, N_3568, N_3632, N_3773, - \result_0[9]\, \pc_0[20]\, \maddress[19]\, \aop1[2]\, - \aop1[3]\, \aop1[19]\, \eres2[4]\, \eres2[19]\, sari_0, - \maddress[7]\, \maddress[17]\, \maddress[21]\, - \maddress[22]\, \maddress[27]\, \aop1[0]\, \aop1[1]\, - \aop1[5]\, \aop1[6]\, \aop1[7]\, \aop1[15]\, \aop1[16]\, - \aop1[17]\, \aop1[18]\, \aop1[20]\, \aop1[21]\, - \aop1[22]\, \aop1[25]\, \aop1[26]\, N_227, \aop1[27]\, - \aop1[28]\, \aop1[29]\, \aop1[30]\, \eres2[22]\, - \eres2[27]\, \logicout_3[30]\, \logicout_4[30]\, N_3225, - \pc_0[14]\, \pc_1[14]\, N_3255, \pc_2[14]\, - \xc_result[14]\, N_3405, N_3556, N_3557, N_3589, N_3653, - \pc_0[29]\, \eaddress[29]\, \shiftin_17[30]\, - \shiftin_17[29]\, N_4277, \logicout_3[25]\, - \logicout_4[25]\, \logicout_4[26]\, N_3552, N_3553, - N_3584, N_3585, \logicout_3[26]\, N_3648, N_3649, - \pc[24]\, \shiftin_17[25]\, \shiftin_17[24]\, \tba[12]\, - \shiftin_17[26]\, \maddress[25]\, \maddress[26]\, - \aop1[24]\, \eres2[25]\, \eres2[26]\, \shiftin_8[41]\, - \shiftin_5[57]\, \shiftin_5[41]\, \logicout_3[22]\, - \logicout_4[22]\, N_3235, \pc_0[24]\, N_3265, \pc_2[24]\, - \pc_3[24]\, \xc_result[24]\, N_3415, N_3549, N_3581, - N_3645, N_3901, \fe_pc[24]\, N_4269_i, \maddress[23]\, - \maddress[24]\, \aop1[23]\, \eres2[23]\, \eres2[24]\, - \shiftin_5[53]\, \data_0_0[22]\, \logicout_3[0]\, - \logicout_4[0]\, N_3527, N_3559, N_3623, \eaddress[0]\, - \shiftin_17[1]\, aluresult_3_sqmuxa, \cwp_1[0]\, - \shiftin_14[2]\, \shiftin_14[0]\, \shiftin_11[4]\, - \shiftin_11[0]\, \shiftin_8[8]\, \shiftin_8[0]\, - \shiftin_5[16]\, \shiftin_5[0]\, N_3872, \maddress[28]\, - \maddress[30]\, N_4220, wcwp, N_4229, \cwp_1[2]\, - \cwp_1_0[2]\, N_6358, \rd_2[4]\, \rd_2[6]\, - \logicout_3[8]\, \logicout_4[8]\, N_3535, N_3567, N_3631, - et_0_sqmuxa_i, su2, N_4255, N_3221, \pc[10]\, \pc_0[10]\, - N_3251, \pc_2[10]\, \pc_3[10]\, \xc_result[10]\, N_3401, - d13, \maddress[16]\, un14_casaen_s0_0, \maddress[6]\, - \rsel1[2]\, \logicout_3[7]\, \logicout_4[7]\, N_3534, - N_3566, N_3630, \logicout_3[28]\, \logicout_4[28]\, - N_3555, N_3587, N_3651, \maddress[29]\, un14_casaen_s1_0, - \logicout_3[17]\, \logicout_4[17]\, N_3544, N_3576, - N_3640, \wim_1[1]\, \wim_1[5]\, \wim_1[3]\, \wim_1[7]\, - \wim_1[0]\, \wim_1[4]\, N_3870, \cwp_1_0[0]\, \wim[1]\, - \wim[3]\, \wim[6]\, \wim[7]\, \shiftin_17[18]\, - \shiftin_17[17]\, N_4278, \eres2[30]\, \eres2[31]\, - edata_3_sqmuxa, \ex_shcnt_1_i[2]\, N_3218, \pc[7]\, - \pc_0[7]\, N_3248, \pc_2[7]\, \pc_3[7]\, \xc_result[7]\, - N_3398, \eres2[8]\, \eres2[9]\, N_4257, \eres2[15]\, - \eres2[16]\, N_3213, \pc_0[2]\, \pc_2[2]\, N_3243, - \pc_3[2]\, \xc_result[2]\, N_3393, N_4263, \pc_0[17]\, - \eres2[17]\, \eres2[18]\, \pc_0[21]\, \eres2[7]\, - \eres2[0]\, \eres2[5]\, N_3884, \fpc[7]\, \fe_pc[7]\, - N_4276_i, \eres2[13]\, \eres2[14]\, \eres2[29]\, N_3223, - \pc_0[12]\, \pc_2[12]\, N_3253, \pc_3[12]\, - \xc_result[12]\, N_3403, \eres2[28]\, \pc[16]\, - \eres2[6]\, \eres2[11]\, \eres2[12]\, \eres2[21]\, - \data_0_2[7]\, \shiftin_17[6]\, \shiftin_17[9]\, N_6632, - \logicout_3[15]\, \logicout_4[15]\, N_3542, N_3574, - N_3638, \shiftin_11[6]\, \shiftin_11[2]\, \shiftin_8[10]\, - \shiftin_8[2]\, \shiftin_11[10]\, \shiftin_8[18]\, - \shiftin_5[18]\, \shiftin_5[2]\, jmpl_4, N_4254, N_6576, - \shiftin_8[15]\, \shiftin_5[31]\, \shiftin_5[15]\, N_6630, - \un6_ex_add_res_s2[13]\, \un6_ex_add_res_s0[13]\, N_6563, - \un6_ex_add_res_s2[17]\, \un6_ex_add_res_s0[17]\, N_6638, - \un6_ex_add_res_s2[19]\, \un6_ex_add_res_s0[19]\, N_6554, - \un6_ex_add_res_s2[8]\, \un6_ex_add_res_s0[8]\, N_4266, - N_3233, \pc_0[22]\, \pc_2[22]\, N_3263, \pc_3[22]\, - \xc_result[22]\, N_3413, N_4253, \ex_shcnt_1_i[3]\, - N_6658, \shiftin_14[3]\, \shiftin_14[1]\, \shiftin_14[5]\, - \shiftin_17[4]\, \shiftin_14[6]\, \shiftin_14[4]\, - \shiftin_14[7]\, \shiftin_14[8]\, \shiftin_14[9]\, - \shiftin_14[10]\, \shiftin_14[11]\, \shiftin_17[10]\, - \shiftin_14[12]\, \shiftin_14[13]\, \shiftin_14[14]\, - \shiftin_14[15]\, \shiftin_14[16]\, \shiftin_14[17]\, - \shiftin_14[18]\, \shiftin_14[19]\, \shiftin_14[20]\, - \ex_shcnt_1_i[1]\, \shiftin_14[21]\, \shiftin_14[22]\, - \shiftin_14[23]\, \shiftin_14[24]\, \shiftin_14[25]\, - \shiftin_14[26]\, \shiftin_14[27]\, \shiftin_14[28]\, - \shiftin_14[29]\, \shiftin_17[28]\, \shiftin_14[30]\, - \shiftin_14[31]\, \shiftin_14[32]\, \shiftin_11[5]\, - \shiftin_11[1]\, \shiftin_11[7]\, \shiftin_11[3]\, - \shiftin_11[9]\, \shiftin_11[11]\, \shiftin_11[12]\, - \shiftin_11[8]\, \shiftin_11[13]\, \shiftin_11[14]\, - \shiftin_11[15]\, \shiftin_11[16]\, \shiftin_11[17]\, - \shiftin_11[18]\, \shiftin_11[19]\, \shiftin_11[20]\, - \shiftin_11[21]\, \shiftin_11[22]\, \shiftin_11[23]\, - \shiftin_11[24]\, \shiftin_11[25]\, \shiftin_11[26]\, - \shiftin_11[27]\, \shiftin_11[28]\, \shiftin_11[29]\, - \shiftin_11[30]\, \shiftin_11[31]\, \shiftin_11[32]\, - \shiftin_11[33]\, \shiftin_11[34]\, \shiftin_8[9]\, - \shiftin_8[1]\, \shiftin_8[11]\, \shiftin_8[3]\, - \shiftin_8[7]\, \shiftin_8[17]\, \shiftin_8[19]\, - \shiftin_8[23]\, \shiftin_8[25]\, \shiftin_8[27]\, - \shiftin_8[31]\, \shiftin_8[33]\, \shiftin_5[19]\, - \shiftin_5[3]\, \shiftin_5[35]\, \shiftin_8[26]\, - \shiftin_8[35]\, \shiftin_5[17]\, shleft_0_RNIU2BG, - \shiftin_5[23]\, shleft_0_RNIBRBG, \shiftin_5[33]\, - \shiftin_5[39]\, s_RNO, mexc_RNO, \pc_4[24]\, - privileged_inst_1_sqmuxa, un1_privileged_inst_1_sqmuxa, - su_1, \maddress[8]\, \shiftin_14[34]\, \shiftin_11[38]\, - \shiftin_8[38]\, \shiftin_5[54]\, \shiftin_5[38]\, - \xc_trap_address[29]\, \shiftin_5[51]\, \shiftin_8[14]\, - \shiftin_8[6]\, \shiftin_5[22]\, \shiftin_5[6]\, - \shiftin_8[22]\, N_3217, \pc_1[6]\, N_3247, \pc_2[6]\, - \xc_result[6]\, N_3397, N_3219, \pc_0[8]\, \pc_2[8]\, - \xc_result[8]\, N_3249, N_3399, \aop1[8]\, - \shiftin_5[26]\, shleft_0_RNIJ8HP, N_3226, \pc_0[15]\, - \pc_2[15]\, N_3256, \pc_3[15]\, \xc_result[15]\, N_3406, - \maddress[15]\, \aop1[14]\, \logicout_3[16]\, - \logicout_4[16]\, N_3543, \aluop_1[2]\, N_3575, N_3639, - \xc_trap_address[16]\, \tba[4]\, \shiftin_5[47]\, N_4264, - \shiftin_14[33]\, \shiftin_11[37]\, \shiftin_8[45]\, - \shiftin_8[37]\, \shiftin_5[61]\, \shiftin_5[45]\, N_3268, - \pc_2[27]\, \bpdata[27]\, \aop1[10]\, \aop1[11]\, N_3242, - \pc_2[31]\, N_3272, \pc_3[31]\, \xc_result[31]\, N_3422, - \shiftin_8[46]\, \shiftin_5[62]\, \shiftin_5[46]\, - \maddress[14]\, \aop1[12]\, \aop1[13]\, N_3234, \pc[23]\, - \pc_0[23]\, N_3237, \pc_2[26]\, N_3264, \pc_2[23]\, - \pc_3[23]\, N_3267, \pc_3[26]\, \xc_result[23]\, - \xc_result[26]\, N_3414, s_3_sqmuxa, N_3417, - \shiftin_8[12]\, \shiftin_8[4]\, \shiftin_8[13]\, - \shiftin_8[5]\, \shiftin_8[16]\, \shiftin_8[20]\, - \shiftin_8[21]\, \shiftin_8[28]\, \shiftin_8[29]\, - \shiftin_8[30]\, \shiftin_8[34]\, \shiftin_8[36]\, - \shiftin_8[42]\, \shiftin_11[36]\, \shiftin_8[44]\, - \shiftin_5[20]\, shleft_1_RNI5FBG, \shiftin_5[21]\, - shleft_1_RNI9JBG, \shiftin_5[28]\, shleft_1_RNINGHP, - \shiftin_5[34]\, \shiftin_5[36]\, \shiftin_5[37]\, - \shiftin_5[42]\, \shiftin_5[44]\, \shiftin_5[50]\, - \ex_shcnt_1_i[4]\, \shiftin_5[52]\, \shiftin_5[58]\, - \shiftin_5[60]\, ex_sari_1_1, \shiftin_8[24]\, - \shiftin_8[40]\, \shiftin_8[32]\, \shiftin_5[24]\, - shleft_1_RNIDVBG, \shiftin_5[32]\, \shiftin_5[40]\, - \shiftin_5[30]\, \shiftin_5[49]\, \shiftin_5[56]\, shleft, - \pc_0[18]\, \logicout_3[1]\, \logicout_4[1]\, N_3528, - N_3560, N_3624, \aluop_1[0]\, aluresult_0_sqmuxa, N_3224, - \pc_0[13]\, \pc_2[13]\, N_3254, \pc_3[13]\, - \xc_result[13]\, N_3404, \rstate[0]\, N_4260, N_3228, - \pc_2[17]\, N_3258, \pc_3[17]\, \xc_result[17]\, \npc[0]\, - N_3408, N_3230, \pc_0[19]\, N_3260, \pc_2[19]\, - \pc_3[19]\, \xc_result[19]\, N_3410, N_3232, \pc_2[21]\, - N_3262, \pc_3[21]\, \xc_result[21]\, N_3412, N_3785, - \eaddress[12]\, N_3554, N_3586, \logicout_3[27]\, N_4259, - N_3240, \pc_2[29]\, N_3270, \pc_3[29]\, \xc_result[29]\, - N_3420, N_3900, \fe_pc[23]\, \pc_0[3]\, \logicout_3[18]\, - \logicout_4[18]\, N_3545, N_3577, N_3641, N_3215, - \pc_2[4]\, N_3245, \pc_3[4]\, \xc_result[4]\, N_3395, - edata_0_sqmuxa, \pil[0]\, \eaddress[23]\, I_84, - \logicout_3[13]\, \logicout_4[13]\, N_3540, N_3572, - N_3636, I_196, N_4072, N_3893, \fpc[16]\, \fe_pc[16]\, - \pc_0[16]\, N_4066, \fpc[23]\, \logicout_3[14]\, - \logicout_4[14]\, N_3541, N_3573, N_3637, - \logicout_3[21]\, \logicout_4[21]\, N_3548, N_3580, - N_3644, \maddress[11]\, \maddress[12]\, N_4059, - \maddress[13]\, \xc_trap_address[7]\, - \xc_trap_address[10]\, \result_0[0]\, \maddress[1]\, - \logicout_3[2]\, \logicout_4[2]\, N_3529, N_3561, N_3625, - \asi[2]\, \inst_1[7]\, \asi[4]\, \inst_1[9]\, - \logicout_3[31]\, \logicout_4[31]\, N_3558, N_3590, - \aluop_3[1]\, lock_0, annul_all, \logicout_3[11]\, - \logicout_4[11]\, N_3538, N_3570, N_3634, - \logicout_3[19]\, \logicout_4[19]\, N_3546, N_3578, - N_3642, ymsb, N_3795, \result_0[31]\, N_3654, \y_2[14]\, - \maddress[5]\, \result_0[29]\, \y_2[29]\, N_167, - N_266_i_i_0, N_268_i_i_0, N_269_i_i_0, N_270_i_i_0, N_284, - N_285, N_286, N_287, N_288, N_289, N_290, N_291, N_292, - N_293, N_294, N_295, N_296, N_297, N_298, N_299, N_300, - N_301, N_302, N_303, N_304, N_305, N_306, N_307, N_308, - N_309, N_310, N_311, N_312, N_313, N_314, N_315, - xc_vectt14, \eaddress[19]\, lock_1, \xc_vectt_1[3]\, - \eaddress[30]\, N_3322, \xc_vectt_1[6]\, N_3887, N_3227, - \pc_2[16]\, N_3257, \pc_3[16]\, \npc[1]\, \xc_result[16]\, - N_3407, I_105, N_3214, \pc_2[3]\, N_3244, \pc_3[3]\, - \xc_result[3]\, N_3394, N_3896, \fe_pc[19]\, N_3246, - \pc_2[5]\, \eaddress[11]\, \xc_trap_address[23]\, N_3321, - N_3323, I_136, N_4062, \fpc[19]\, \xc_trap_address[19]\, - \logicout_3[12]\, \logicout_4[12]\, N_3239, \pc_0[28]\, - \pc_2[28]\, N_3269, \pc_3[28]\, \xc_result[28]\, N_3419, - N_3539, N_3571, N_3635, N_3236, \pc_2[25]\, N_3266, - \pc_3[25]\, \xc_result[25]\, N_3416, N_6699, N_6747, - \tt_RNO[0]\, \irl[0]\, \pc_RNO[4]\, \pc_RNO[16]\, - \pc_RNO[19]\, \pc_RNO[23]\, N_6866_i, - \un6_ex_add_res_s0_1[17]\, \un6_ex_add_res_s0_1[13]\, - ld_4, N_4268_i, N460_1, \un6_ex_add_res_s0[3]\, - \un6_ex_add_res_s2_1[3]\, \un6_ex_add_res_s2[3]\, N_6642, - \cwp_2[1]\, \un6_ex_add_res_s2_1[8]\, \shiftin_5[55]\, - \shiftin_8[39]\, \aop1[9]\, \maddress[10]\, N_6555, - \eres2[10]\, N575_2, N579_1, N_3402, \xc_result[11]\, - \pc_0[11]\, N_3222, N_3252, \pc_1[11]\, \pc_2[11]\, - N_4258, \data_0_2[11]\, N603_0, N_3633, \logicout_4[10]\, - \shiftin_5_i[14]\, \shiftin_5[13]\, \shiftin_5[29]\, - N_3569, N_3537, \logicout_3[10]\, N427_2, - \un6_ex_add_res_s2_1[16]\, \data_0_2[15]\, N_4262, N_53, - N449_1, N521_1, I183_un1_Y_i_0, N586_1, N579_2, - \un6_ex_add_res_s0[18]\, I239_un1_Y_1, - \un6_ex_add_res_s2_1[18]\, \un6_ex_add_res_s2[18]\, - I239_un1_Y_i, \shiftin_5[48]\, N_6637, N668_1, - I249_un1_Y_0, \un6_ex_add_res_s0[23]\, - \un6_ex_add_res_s2_1[23]\, N_71, N_30_0, - \un6_ex_add_res_s2[23]\, \shiftin_11[35]\, - \shiftin_5[59]\, \shiftin_5[43]\, \shiftin_8[43]\, - \shiftin_5[27]\, N_6570, N_6569, \shiftin_5_i[11]\, - N656_1, N_4252, I245_un1_Y_0, N610_1, I205_un1_Y_0, - N545_1, N549_0, I197_un1_Y_i, I189_un1_Y_i, - \shiftin_5[25]\, \shiftin_5_i[9]\, N_4272, N563_0, N473_2, - N472_1, N472_2, N_3650, \logicout_4[27]\, N_4274, N_3418, - \xc_result[27]\, \pc_3[27]\, N_3238, N_6574, N_4275, - N475_0, N482_1, N485, \un6_ex_add_res_s0[15]\, N_6634, - I173_un1_Y_i, \un6_ex_add_res_s0[32]\, - \un6_ex_add_res_s2_1[32]\, \un6_ex_add_res_s2[32]\, - N_6659, N559, N_6568, \laddr[0]\, \eres2[2]\, \cwp_2[2]\, - N_4261, N_267_i_i_0, N_4265, \pc_0[30]\, N451_2, ps_RNO, - N_4993, \un6_ex_add_res_s0[4]\, \un6_ex_add_res_s2_1[4]\, - \un6_ex_add_res_s2[4]\, \un6_ex_add_res_s2_1[20]\, N_6643, - I247_un1_Y, \eaddress[2]\, \cwp_1_1[0]\, N_4227, N_4218, - N_4273, N476_2, N475_1, N463_1, N466_0, N505_0, - I103_un1_Y, N504_0, N513_2, N509_0, N512_1, N508_0, - N470_0, N469_0, N_4271, invop2, N505_1, N504_1, N470_1, - N469_1, N467_2, N466_1, \un6_ex_add_res_s0[10]\, - \un6_ex_add_res_s2_1[10]\, ADD_33x33_fast_I274_Y_0_a3_0, - \un6_ex_add_res_s2[10]\, N_6629, \un6_ex_add_res_s0[21]\, - \un6_ex_add_res_s2_1[21]\, \un6_ex_add_res_s2[21]\, N786, - N_3628, \logicout_4[5]\, N_6567, N_3564, N455_2, N454_2, - N545_2, N611_0, N610_2, N549_1, \un6_ex_add_res_s0[7]\, - \un6_ex_add_res_s2_1[7]\, N_15_0, \un6_ex_add_res_s2[7]\, - N_4270, N_6646, N463_2, N508_1, N461_1, N458_0, N460_2, - N_71_1, N514_2, N_4267, ldbp2_3, N_3643, \logicout_4[20]\, - \eres2[20]\, \maddress[20]\, N_3579, N_3547, - \logicout_3[20]\, N_3411, \xc_result[20]\, \pc_2[20]\, - N_3231, N_3261, \pc_3[20]\, ldbp1, \rdata_13[8]\, N_3480, - N_3652, \logicout_4[29]\, N_3588, \logicout_3[29]\, - N478_2, \rd_2[3]\, N_6352, \cwp_1_0[1]\, N_4228, N_4219, - \rd_3[2]\, N_3421, \xc_result[30]\, \pc_2[30]\, N_3241, - N_3271, \pc_3[30]\, mexc_1_sqmuxa, SIGNED, SIGNED_0, - \tt2[1]\, N_4205, \tt2[2]\, N_4206, \tt_2[2]\, \tt_2[1]\, - I107_un1_Y_i, N_6654, \un6_ex_add_res_s2[20]\, - \un6_ex_add_res_s0[20]\, N_6631, \un6_ex_add_res_s2[12]\, - \un6_ex_add_res_s0[12]\, \un6_ex_add_res_s2_1[12]\, - N607_1, N_3304, \shcnt[0]\, ADD_33x33_fast_I206_Y_0_a3, - N591_2, N525_1, N590_2, I171_un1_Y_i, N548_1, N400_2, - rett_1_3, N_4, N_6645, \un6_ex_add_res_s2[6]\, - \un6_ex_add_res_s0[6]\, N_6571, \eaddress[24]\, - \pc_RNO[24]\, \fpc[24]\, I_143, N_4067, - \xc_trap_address[24]\, wcwp_0, N_4178, N_4183, N_4188, - \icco[3]\, \maddress[31]\, \aop1_1_i[31]\, \aop1[31]\, - \un1_p0_6[349]\, trap_5, I181_un1_Y_i, - \xc_trap_address[22]\, N_6635, \un6_ex_add_res_s2[16]\, - \un6_ex_add_res_s0[16]\, N_6657, \maddress[18]\, - \un6_ex_add_res_s0[14]\, \un6_ex_add_res_s2[14]\, N_3409, - \xc_result[18]\, \pc_2[18]\, N_3229, N_3259, \pc_3[18]\, - N_6633, \tt_RNO[1]\, \xc_vectt_1[1]\, \irl[1]\, - \xc_trap_address[5]\, N_3320, \pc_3[8]\, \tt_1[0]\, - \tt_2[5]\, \tt2[4]\, N_6625, \un6_ex_add_res_s2[29]\, - \un6_ex_add_res_s0[29]\, \un6_ex_add_res_s2_1[29]\, - \un6_ex_add_res_s0[5]\, \un6_ex_add_res_s2_1[5]\, - \un6_ex_add_res_s2[5]\, ADD_33x33_fast_I206_Y_0_a3_0, - \eaddress[4]\, N_6644, N424_2, \pil[1]\, N_6577, N_4256, - ADD_33x33_fast_I244_un1_Y, \un6_ex_add_res_s0[2]\, - \un6_ex_add_res_s2_1[2]\, \un6_ex_add_res_s2[2]\, N_3646, - \logicout_4[23]\, N_3627, \logicout_4[4]\, N_3396, - \xc_result[5]\, \pc_3[5]\, N_3216, N_246, N_6641, N_3582, - N_3550, \logicout_3[23]\, et_2, N_3563, N_3531, - \logicout_3[4]\, \rfe2\, \rfe1\, \eenaddr\, \rbranch\, - mexc_1, \tt_3[5]\, \su_0\, ld_5, \inst_3[25]\, - \inst_3[26]\, \inst_3[27]\, \inst_3[28]\, \inst_3[29]\, - \tt_2[0]\, \tt_3[1]\, \tt_3[2]\, \tt_5[3]\, \cwp_2[0]\, - \cwp_3[1]\, \cwp_3[2]\, \inst_1[14]\, \inst_1[17]\, - \inst_1[18]\, \wdata[0]\, \wdata[1]\, \wdata[2]\, - \wdata[3]\, \wdata[4]\, \wdata[5]\, \wdata[6]\, - \wdata[7]\, \wdata[8]\, \wdata[9]\, \wdata[10]\, - \wdata[11]\, \wdata[12]\, \wdata[13]\, \wdata[14]\, - \wdata[15]\, \wdata[16]\, \wdata[17]\, \wdata[18]\, - \wdata[19]\, \wdata[20]\, \wdata[21]\, \wdata[22]\, - \wdata[23]\, \wdata[24]\, \wdata[25]\, \wdata[26]\, - \wdata[27]\, \wdata[28]\, \wdata[29]\, \wdata[30]\, - \wdata[31]\, \irl[2]\, \irl[3]\, \size_1[0]\, \size_0[1]\, - \maddress[3]\, \rfa2[0]\, \rfa2[1]\, \rfa2[2]\, \rfa2[3]\, - \rfa2[4]\, \rfa2[5]\, \rfa2[6]\, \rfa2[7]\, \raddr2[7]\, - \rfa1[0]\, \rfa1[1]\, \rfa1[2]\, \rfa1[3]\, \rfa1[4]\, - \rfa1[5]\, \rfa1[6]\, \rfa1[7]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \DWACT_ADD_CI_0_g_array_1_3[0]\, - \DWACT_ADD_CI_0_pog_array_0[0]\, - \DWACT_ADD_CI_0_g_array_0_1[0]\, - \DWACT_ADD_CI_0_partial_sum[2]\, - \DWACT_ADD_CI_0_partial_sum[1]\, N_4_0, - \DWACT_FINC_E[24]\, \DWACT_FINC_E[23]\, - \DWACT_FINC_E[25]\, N_9_0, \DWACT_FINC_E[29]\, - \DWACT_FINC_E[30]\, N_14_0, \DWACT_FINC_E[15]\, - \DWACT_FINC_E[17]\, \DWACT_FINC_E[22]\, N_21, - \DWACT_FINC_E[21]\, \DWACT_FINC_E[9]\, \DWACT_FINC_E[12]\, - \DWACT_FINC_E[20]\, N_30_1, \DWACT_FINC_E[13]\, - \DWACT_FINC_E[19]\, N_35_0, \DWACT_FINC_E[18]\, N_42, - \DWACT_FINC_E[33]\, \DWACT_FINC_E[34]\, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[5]\, N_51, \DWACT_FINC_E[28]\, - \DWACT_FINC_E[16]\, N_56, N_61, \DWACT_FINC_E[14]\, N_66, - N_71_0, \DWACT_FINC_E[10]\, N_78, \DWACT_FINC_E[11]\, - N_83, N_88, N_93, \DWACT_FINC_E[8]\, N_98, N_106, N_113, - \DWACT_FINC_E[3]\, N_121, N_126_0, N_131, - \DWACT_FINC_E[1]\, N_136, N_144, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - wdata(31) <= \wdata[31]\; - wdata(30) <= \wdata[30]\; - wdata(29) <= \wdata[29]\; - wdata(28) <= \wdata[28]\; - wdata(27) <= \wdata[27]\; - wdata(26) <= \wdata[26]\; - wdata(25) <= \wdata[25]\; - wdata(24) <= \wdata[24]\; - wdata(23) <= \wdata[23]\; - wdata(22) <= \wdata[22]\; - wdata(21) <= \wdata[21]\; - wdata(20) <= \wdata[20]\; - wdata(19) <= \wdata[19]\; - wdata(18) <= \wdata[18]\; - wdata(17) <= \wdata[17]\; - wdata(16) <= \wdata[16]\; - wdata(15) <= \wdata[15]\; - wdata(14) <= \wdata[14]\; - wdata(13) <= \wdata[13]\; - wdata(12) <= \wdata[12]\; - wdata(11) <= \wdata[11]\; - wdata(10) <= \wdata[10]\; - wdata(9) <= \wdata[9]\; - wdata(8) <= \wdata[8]\; - wdata(7) <= \wdata[7]\; - wdata(6) <= \wdata[6]\; - wdata(5) <= \wdata[5]\; - wdata(4) <= \wdata[4]\; - wdata(3) <= \wdata[3]\; - wdata(2) <= \wdata[2]\; - wdata(1) <= \wdata[1]\; - wdata(0) <= \wdata[0]\; - size_0_1 <= \size_0[1]\; - size_1_0 <= \size_1[0]\; - rfa2(7) <= \rfa2[7]\; - rfa2(6) <= \rfa2[6]\; - rfa2(5) <= \rfa2[5]\; - rfa2(4) <= \rfa2[4]\; - rfa2(3) <= \rfa2[3]\; - rfa2(2) <= \rfa2[2]\; - rfa2(1) <= \rfa2[1]\; - rfa2(0) <= \rfa2[0]\; - raddr2(7) <= \raddr2[7]\; - rfa1(7) <= \rfa1[7]\; - rfa1(6) <= \rfa1[6]\; - rfa1(5) <= \rfa1[5]\; - rfa1(4) <= \rfa1[4]\; - rfa1(3) <= \rfa1[3]\; - rfa1(2) <= \rfa1[2]\; - rfa1(1) <= \rfa1[1]\; - rfa1(0) <= \rfa1[0]\; - irl(3) <= \irl[3]\; - irl(2) <= \irl[2]\; - irl(1) <= \irl[1]\; - irl(0) <= \irl[0]\; - maddress(31) <= \maddress[31]\; - maddress(30) <= \maddress[30]\; - maddress(29) <= \maddress[29]\; - maddress(28) <= \maddress[28]\; - maddress(27) <= \maddress[27]\; - maddress(26) <= \maddress[26]\; - maddress(25) <= \maddress[25]\; - maddress(24) <= \maddress[24]\; - maddress(23) <= \maddress[23]\; - maddress(22) <= \maddress[22]\; - maddress(21) <= \maddress[21]\; - maddress(20) <= \maddress[20]\; - maddress(19) <= \maddress[19]\; - maddress(18) <= \maddress[18]\; - maddress(17) <= \maddress[17]\; - maddress(16) <= \maddress[16]\; - maddress(15) <= \maddress[15]\; - maddress(14) <= \maddress[14]\; - maddress(13) <= \maddress[13]\; - maddress(12) <= \maddress[12]\; - maddress(11) <= \maddress[11]\; - maddress(10) <= \maddress[10]\; - maddress(9) <= \maddress[9]\; - maddress(8) <= \maddress[8]\; - maddress(7) <= \maddress[7]\; - maddress(6) <= \maddress[6]\; - maddress(5) <= \maddress[5]\; - maddress(4) <= \maddress[4]\; - maddress(3) <= \maddress[3]\; - maddress(2) <= \maddress[2]\; - maddress(1) <= \maddress[1]\; - maddress(0) <= \maddress[0]\; - un1_p0_6_0 <= \un1_p0_6[0]\; - fpc(31) <= \fpc[31]\; - fpc(30) <= \fpc[30]\; - fpc(29) <= \fpc[29]\; - fpc(28) <= \fpc[28]\; - fpc(27) <= \fpc[27]\; - fpc(26) <= \fpc[26]\; - fpc(25) <= \fpc[25]\; - fpc(24) <= \fpc[24]\; - fpc(23) <= \fpc[23]\; - fpc(22) <= \fpc[22]\; - fpc(21) <= \fpc[21]\; - fpc(20) <= \fpc[20]\; - fpc(19) <= \fpc[19]\; - fpc(18) <= \fpc[18]\; - fpc(17) <= \fpc[17]\; - fpc(16) <= \fpc[16]\; - fpc(15) <= \fpc[15]\; - fpc(14) <= \fpc[14]\; - fpc(13) <= \fpc[13]\; - fpc(12) <= \fpc[12]\; - fpc(11) <= \fpc[11]\; - fpc(10) <= \fpc[10]\; - fpc(9) <= \fpc[9]\; - fpc(8) <= \fpc[8]\; - fpc(7) <= \fpc[7]\; - fpc(6) <= \fpc[6]\; - fpc(5) <= \fpc[5]\; - fpc(4) <= \fpc[4]\; - fpc(3) <= \fpc[3]\; - fpc(2) <= \fpc[2]\; - eaddress_4 <= \eaddress[4]\; - eaddress_2 <= \eaddress[2]\; - eaddress_12 <= \eaddress[12]\; - eaddress_24 <= \eaddress[24]\; - eaddress_5 <= \eaddress[5]\; - eaddress_11 <= \eaddress[11]\; - eaddress_30 <= \eaddress[30]\; - eaddress_6 <= \eaddress[6]\; - eaddress_3 <= \eaddress[3]\; - eaddress_27 <= \eaddress[27]\; - eaddress_31 <= \eaddress[31]\; - eaddress_15 <= \eaddress[15]\; - eaddress_17 <= \eaddress[17]\; - eaddress_20 <= \eaddress[20]\; - eaddress_18 <= \eaddress[18]\; - eaddress_26 <= \eaddress[26]\; - eaddress_14 <= \eaddress[14]\; - eaddress_21 <= \eaddress[21]\; - eaddress_25 <= \eaddress[25]\; - eaddress_29 <= \eaddress[29]\; - eaddress_19 <= \eaddress[19]\; - eaddress_23 <= \eaddress[23]\; - eaddress_22 <= \eaddress[22]\; - eaddress_9 <= \eaddress[9]\; - eaddress_10 <= \eaddress[10]\; - eaddress_7 <= \eaddress[7]\; - eaddress_8 <= \eaddress[8]\; - maddress_0_2 <= \maddress_0[3]\; - maddress_0_0 <= \maddress_0[1]\; - eenaddr <= \eenaddr\; - su_0 <= \su_0\; - rfe2 <= \rfe2\; - rfe1 <= \rfe1\; - ldlock_3_0 <= \ldlock_3_0\; - rbranch <= \rbranch\; - un1_addout_12 <= \un1_addout_12\; - ldlock_2 <= \ldlock_2\; - fbranch <= \fbranch\; - hold_pc_7 <= \hold_pc_7\; - nullify2_0_sqmuxa <= \nullify2_0_sqmuxa\; - me_nullify2_1_2 <= \me_nullify2_1_2\; - un9_icc_check_bp <= \un9_icc_check_bp\; - inull <= \inull\; - de_hold_pc_1 <= \de_hold_pc_1\; - un17_casaen_0_0 <= \un17_casaen_0_0\; - xc_exception_1_0 <= \xc_exception_1_0\; - ra_bpmiss_1_0 <= \ra_bpmiss_1_0\; - - \r.e.ctrl.inst[7]\ : DFN1E0 - port map(D => \inst[7]\, CLK => lclk_c, E => holdn, Q => - \inst_1[7]\); - - \r.a.rsel1_0_RNIH7LJ2[2]\ : OR2B - port map(A => data1(27), B => d11_0, Y => \rfo_m[27]\); - - \r.w.s.tba_RNIF5JUN[2]\ : AND2 - port map(A => \aluresult_1_iv_6[14]\, B => - \logicout_m_0[14]\, Y => \aluresult_1_iv_7[14]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I56_Y_i : AO1C - port map(A => \un1_iu0_6[18]\, B => \data_0_0[18]\, C => - N455_0, Y => N_30_0); - - \r.e.op2_RNO_6[10]\ : OR3B - port map(A => d29_0_0, B => \imm[10]\, C => \rsel2_1[0]\, Y - => \imm_m_i[10]\); - - \r.e.ctrl.pc_RNIH8UN2[28]\ : NOR2A - port map(A => \cpi_m[173]\, B => \aluresult_6[31]\, Y => - \aluresult_1_iv_1[28]\); - - \r.e.ctrl.pc[16]\ : DFN1E0 - port map(D => \pc_0[16]\, CLK => lclk_c, E => holdn, Q => - \pc[16]\); - - \r.x.ctrl.pc_RNI9GI61[17]\ : MX2C - port map(A => \un1_p0_6[369]\, B => \pc_2[17]\, S => - s_3_sqmuxa, Y => N_3408); - - \r.m.result_RNIOA753[18]\ : NOR3C - port map(A => \d_iv_0[18]\, B => \result_m_0[18]\, C => - \rfo_m[18]\, Y => \d_iv_2[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I299_Y_0_1 : XOR2 - port map(A => \data_0[8]\, B => \un1_iu0_6[8]\, Y => - \un6_ex_add_res_s2_1[9]\); - - \r.e.op2[21]\ : DFN1E0 - port map(D => N_305, CLK => lclk_c, E => holdn, Q => - \op2[21]\); - - \r.e.ldbp2_RNIQMSNU2\ : OR2A - port map(A => \eaddress[19]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[20]\); - - \r.a.ctrl.inst_RNI013H1[20]\ : OR3A - port map(A => aluop_0_1_0_a5_0, B => N_201, C => inst_9_3, - Y => N_362); - - un6_fe_npc_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_121); - - \r.e.ctrl.rd_RNI3QO53[1]\ : NOR3C - port map(A => un2_rs1_1_7_i_0, B => un2_rs1_1_5_i_0, C => - wreg_2_2, Y => wreg_2_5); - - \r.w.result_RNIMJD4[24]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[24]\, - Y => \result_m_0[24]\); - - \r.e.alucin_RNO_1\ : XAI1 - port map(A => N_220, B => \inst_2[21]\, C => cin_iv_i_a5_0, - Y => N_348); - - \r.x.data_0_RNO_3[8]\ : OR2A - port map(A => data_0_0_24, B => rdata_5_sqmuxa, Y => - \dco_m_0_i[120]\); - - \r.e.op2_RNO[13]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[13]\, Y => N_297); - - \comb.branch_address.tmp_ADD_30x30_fast_I21_G0N\ : NOR2B - port map(A => \un1_p0_6_0[60]\, B => \dpc[23]\, Y => N421_2); - - \r.e.aluop_0_RNIR9EM3[0]\ : MX2C - port map(A => N_3562, B => N_3626, S => \aluop_0[0]\, Y => - \logicout[3]\); - - \r.e.op2_RNO_6[28]\ : OR2B - port map(A => data2(28), B => d25, Y => \rfo_m_i[60]\); - - \r.d.inull_RNIIH9QT\ : OR2 - port map(A => de_hold_pc_1_0, B => holdn, Y => N_6763_i_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I130_Y\ : OR2 - port map(A => N491, B => I130_un1_Y, Y => N550); - - \r.d.pc_RNO[18]\ : MX2 - port map(A => \fpc[18]\, B => \dpc[18]\, S => N_6763_i_0, Y - => \pc_RNO[18]\); - - \r.m.result_RNO[12]\ : MX2 - port map(A => \aluresult[12]\, B => \op1[12]\, S => - un17_casaen_0_2, Y => \eres2[12]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I310_Y_0 : AX1C - port map(A => I271_un1_Y_i, B => ADD_33x33_fast_I271_Y_0_0, - C => ADD_33x33_fast_I310_Y_0_0, Y => - \un6_ex_add_res_s1_i[20]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I273_Y_0 : AO1 - port map(A => ADD_33x33_fast_I273_un1_Y_0_0, B => N653, C - => N652_0, Y => ADD_33x33_fast_I273_Y_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I44_Y : NOR2A - port map(A => N473_1, B => N470_1, Y => N503_0); - - \r.m.y_RNO_2[15]\ : OR2B - port map(A => wy_RNIMKUI, B => \y_2[15]\, Y => \y_m_0[15]\); - - \r.a.rsel1_RNI62UN02[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[3]\, Y - => \aluresult_m_0[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I81_Y : AO13 - port map(A => N412_0, B => \un1_iu0_6[6]\, C => \data_0[6]\, - Y => N540); - - \r.e.shcnt_RNIT5TM5[3]\ : MX2 - port map(A => \shiftin_8[29]\, B => \shiftin_8[21]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[21]\); - - \r.a.ctrl.inst_RNIMS131[31]\ : OR3A - port map(A => N_6681_1, B => \inst[30]\, C => \inst[31]\, Y - => cp_disabled_1_sqmuxa); - - \r.a.bp_RNO\ : NOR2 - port map(A => bp_1_0, B => ctrl_annul_i, Y => bp_1); - - \r.e.op2_RNICBH32[23]\ : AOI1B - port map(A => \un1_iu0_5[89]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[23]\); - - \r.e.jmpl_RNIN50TT\ : OR2B - port map(A => \shiftin_17[26]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[26]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I146_Y_0 : NOR2B - port map(A => N404, B => N407, Y => ADD_33x33_fast_I146_Y_0); - - \r.e.op2_RNO_5[16]\ : AOI1B - port map(A => \result[16]\, B => d31_0, C => \imm_m_i[16]\, - Y => \d_1_iv_0[16]\); - - un6_fe_npc_I_189 : AND3 - port map(A => \fe_pc[26]\, B => \fe_pc[27]\, C => - \fe_pc[28]\, Y => \DWACT_FINC_E[22]\); - - \r.a.imm[1]\ : DFN1E0 - port map(D => \un3_de_ren1[119]\, CLK => lclk_c, E => holdn, - Q => \imm[1]\); - - \r.e.shcnt_RNI98SF5[3]\ : MX2 - port map(A => \shiftin_8[25]\, B => \shiftin_8[17]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[17]\); - - \r.e.op1_RNIGF98B6[22]\ : NOR3C - port map(A => \op1_m_0[22]\, B => \d_iv_2[22]\, C => - \aluresult_m_0[22]\, Y => \d_i[22]\); - - \r.m.y_RNO_4[23]\ : OR2B - port map(A => \y[24]\, B => mulstep_0, Y => \y_m[24]\); - - \r.w.result_RNIQM3C[2]\ : AOI1B - port map(A => \result[2]\, B => d31, C => \imm_m_i[2]\, Y - => \d_1_iv_0[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I6_P0N : OR2A - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, Y => N413_0); - - \r.m.y_RNIGQT25[0]\ : OR3C - port map(A => \y_iv_0_o5_1[0]\, B => \y_iv_0_o5_0[0]\, C - => N_463, Y => \y_1[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I269_un1_Y : OR3C - port map(A => N645, B => N661, C => N676_0, Y => - I269_un1_Y_i); - - \r.e.shcnt_RNIKHVJE[2]\ : MX2 - port map(A => \shiftin_11[35]\, B => \shiftin_11[31]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[31]\); - - \r.e.jmpl_RNISQNAQ\ : OR2B - port map(A => \shiftin_17[18]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[18]\); - - \r.a.ctrl.inst_RNI7C0E[31]\ : OR2B - port map(A => \inst[31]\, B => \inst[30]\, Y => N_212); - - \r.e.invop2_0\ : DFN1E0 - port map(D => N_6680, CLK => lclk_c, E => holdn, Q => - invop2_0); - - \r.e.aluop_0_RNIJ59C6[0]\ : OR2B - port map(A => \logicout[16]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[16]\); - - \r.e.ctrl.pc_RNITIEE6[4]\ : NOR3C - port map(A => \aluresult_1_iv_0[4]\, B => \ex_op2_m[4]\, C - => \aluresult_1_iv_2[4]\, Y => \aluresult_1_iv_3[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I245_un1_Y : NOR2B - port map(A => N676_0, B => N661, Y => I245_un1_Y_0); - - \r.m.ctrl.trap_RNI92KDJ\ : OR3C - port map(A => trap_2_0, B => un1_trap_0_sqmuxa_5, C => - un6_annul_4, Y => un6_annul); - - \r.a.ctrl.pc[28]\ : DFN1E0 - port map(D => \dpc[28]\, CLK => lclk_c, E => holdn, Q => - \pc[28]\); - - \r.w.s.tt_RNIEJP81[4]\ : OR2B - port map(A => \tt[4]\, B => aluresult_12_sqmuxa, Y => - \tt_m[4]\); - - \r.e.ctrl.pc_RNIICUN2[29]\ : NOR2A - port map(A => \cpi_m[174]\, B => \aluresult_6[31]\, Y => - \aluresult_1_iv_1[29]\); - - \r.e.op2_RNO_6[9]\ : OR3B - port map(A => d29_0_0, B => \imm[9]\, C => \rsel2_1[0]\, Y - => \imm_m_i[9]\); - - \r.e.aluop_1_RNI6H393[1]\ : MX2C - port map(A => \logicout_4[19]\, B => N_6913, S => N_6866_i, - Y => N_3642); - - \r.f.pc_RNO_1[10]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[10]\, C => - \xc_trap_address_m[10]\, Y => \pc_1_iv_0[10]\); - - un6_fe_npc_I_149 : AND3 - port map(A => \fe_pc[2]\, B => \fe_pc[3]\, C => \fe_pc[4]\, - Y => \DWACT_FINC_E[34]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I219_un1_Y : OAI1 - port map(A => I179_un1_Y, B => N582, C => N633_1, Y => - I219_un1_Y_i); - - \r.d.inst_0_RNO_0[7]\ : MX2 - port map(A => data_0_0_7, B => \inst_0[7]\, S => - mexc_1_sqmuxa_1_0, Y => N_4607); - - \comb.branch_address.tmp_ADD_30x30_fast_I264_Y_0\ : XNOR2 - port map(A => N556_i, B => ADD_30x30_fast_I264_Y_0_0, Y => - \tmp[6]\); - - \r.m.result_RNIEJD4[26]\ : OR2B - port map(A => d13_0, B => \maddress[26]\, Y => - \result_m_0[26]\); - - \r.e.ctrl.inst_RNIROQF[25]\ : AO1B - port map(A => \inst_1[26]\, B => \inst_2[25]\, C => - \icc_0[2]\, Y => N_248); - - \r.f.pc_RNO_1[8]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[8]\, C => - \xc_trap_address_m[8]\, Y => \pc_1_iv_0[8]\); - - \r.a.ctrl.inst_RNIU43A1[23]\ : OR3A - port map(A => inst_22_0, B => N_271, C => N_241, Y => - inst_22); - - \r.f.pc_RNO_3[28]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[28]\, C => - \xc_trap_address_m[28]\, Y => \pc_1_iv_0[28]\); - - \r.m.result_RNIKO4D3[17]\ : NOR3C - port map(A => \d_iv_0[17]\, B => \result_m_0[17]\, C => - \rfo_m[17]\, Y => \d_iv_2[17]\); - - \r.e.shleft_0_RNI5BBG\ : OR2A - port map(A => \un1_iu0_6[3]\, B => shleft_0, Y => - \shiftin_5[3]\); - - \r.e.op2_RNI1PHG[2]\ : MX2 - port map(A => \op2[2]\, B => N_3306, S => ldbp2_0, Y => - \un1_iu0_5[68]\); - - \r.x.ctrl.trap\ : DFN1E0 - port map(D => trap2, CLK => lclk_c, E => holdn, Q => trap_5); - - \r.m.ctrl.pc[26]\ : DFN1E0 - port map(D => \pc[26]\, CLK => lclk_c, E => holdn, Q => - \pc_3[26]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I148_Y : NOR2B - port map(A => N549_1, B => N545_2, Y => N611_0); - - \r.w.s.dwt_RNI3GVA\ : OR2A - port map(A => werr, B => dwt, Y => werr_1); - - \r.d.inst_0_RNO_0[10]\ : MX2 - port map(A => data_0_0_10, B => \inst_0[10]\, S => - mexc_1_sqmuxa_1_0, Y => N_4610); - - \r.w.s.y[31]\ : DFN1E0 - port map(D => N_3795, CLK => lclk_c, E => N_6922_i, Q => - \y_2[31]\); - - un2_rstn_5 : NOR2 - port map(A => un2_rstn_5_2, B => \un2_rstn_5_0_0\, Y => - \un2_rstn_5\); - - \r.e.ctrl.wicc_RNIOBKQ6G\ : MX2 - port map(A => N_4186, B => N_4176, S => wicc_2, Y => - \icco[1]\); - - \r.a.ctrl.rett_RNO\ : NOR2A - port map(A => N_152, B => N_150, Y => rett_1_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I47_Y_0_a3 : AND2 - port map(A => N463, B => N467_0, Y => N_72); - - un6_ex_add_res_d0_ADD_33x33_fast_I197_Y : OR2A - port map(A => I197_un1_Y_i, B => N600, Y => N666); - - un6_ex_add_res_d1_ADD_33x33_fast_I37_Y : MAJ3 - port map(A => \op2[28]\, B => \un1_iu0_6[28]\, C => N478, Y - => N496); - - un6_ex_add_res_d2_ADD_33x33_fast_I246_Y_0_a3 : NOR2B - port map(A => N808, B => N431_2, Y => - ADD_33x33_fast_I246_Y_0_a3_1); - - \r.m.result_0_RNI05AB4[3]\ : AOI1 - port map(A => un1_trap_0_sqmuxa_0, B => trap_0_sqmuxa, C - => trap63, Y => trap_0_sqmuxa_6); - - un6_ex_add_res_d2_ADD_33x33_fast_I264_un1_Y_0 : AND2 - port map(A => N651, B => N635, Y => - ADD_33x33_fast_I264_un1_Y_0_0); - - \r.w.s.tba_RNI64CA1[5]\ : OR2B - port map(A => \tba[5]\, B => aluresult_12_sqmuxa, Y => - \tba_m[5]\); - - \r.x.data_0_RNO_0[1]\ : NOR3C - port map(A => \data_0_1_1_iv_0[1]\, B => \dco_m_i[121]\, C - => \dco_m_i[113]\, Y => \data_0_1_1_iv_2[1]\); - - \r.e.ctrl.rd_RNINR0HO[6]\ : NOR2 - port map(A => wreg_1, B => wreg_1_8, Y => N_3948); - - \r.w.s.tt[4]\ : DFN1E0 - port map(D => \xc_vectt_1[4]\, CLK => lclk_c, E => N_6747, - Q => \tt[4]\); - - \r.e.op2_RNI5OOH1[24]\ : OR2B - port map(A => \un1_iu0_5[90]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[24]\); - - un6_fe_npc_I_209 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[25]\, Y => N_4_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I171_Y : AOI1 - port map(A => N582, B => N575_1, C => N574_1, Y => N640); - - \r.a.ctrl.inst_RNIFG1L[22]\ : NOR2B - port map(A => \inst[22]\, B => aluop_2_1_0_a2_0, Y => - aluop_2_1_0_a2_1); - - \comb.op_mux.d_1_iv[29]\ : NAND2 - port map(A => \aluresult_m_i[29]\, B => \d_1_iv_4[29]\, Y - => \d_1[29]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I259_un1_Y : OR3C - port map(A => N641_1, B => N625_1, C => N796_1, Y => - I259_un1_Y_1); - - \r.e.invop2_1_RNI3LVB11\ : MX2C - port map(A => \un6_ex_add_res_s2[15]\, B => - \un6_ex_add_res_s0[15]\, S => invop2_1, Y => N_6634); - - \r.a.ctrl.wreg_RNO_1\ : NOR3 - port map(A => un19_rd, B => un1_ld_1_sqmuxa_1_0, C => - write_reg_2_sqmuxa, Y => un1_ld_1_sqmuxa_1); - - \r.w.s.tba_RNIBM524[17]\ : AOI1B - port map(A => \tba[17]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[29]\, Y => \aluresult_1_iv_3[29]\); - - \r.x.ctrl.inst_RNI7O0H2[30]\ : OR2A - port map(A => rst, B => s_2_sqmuxa, Y => et_2_sqmuxa); - - \r.a.ctrl.inst_RNIFVJ8L[23]\ : OA1 - port map(A => N_603, B => illegal_inst_7_iv_8_tz, C => - illegal_inst_7_iv_5, Y => illegal_inst_7_iv_7); - - un6_fe_npc_I_114 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[12]\, Y => N_71_0); - - \r.a.ctrl.rd_RNI1CCC2[5]\ : XNOR2 - port map(A => \un3_de_ren1[104]\, B => \rd_1[5]\, Y => - un1_de_ren1_5_i); - - \r.d.inst_0_RNO[13]\ : NOR2B - port map(A => rst, B => N_4613, Y => \inst_0_RNO[13]\); - - \r.e.op1_RNIE6VM1[11]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[11]\, Y => - \ex_op1_i_m[11]\); - - \r.x.data_0_RNO_3[15]\ : NOR2A - port map(A => \data_0_2[15]\, B => ld_3, Y => - \data_0_m[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I93_Y : AO13 - port map(A => alucin, B => \un1_iu0_6[0]\, C => \data_0[0]\, - Y => N552); - - un6_ex_add_res_d0_ADD_33x33_fast_I6_G0N : NOR3A - port map(A => \op1[5]\, B => ldbp1_3, C => \data_0[5]\, Y - => N412_0); - - \r.e.ctrl.pc_RNI75K11[12]\ : OR2B - port map(A => \pc_2[12]\, B => jmpl_4, Y => \cpi_m[157]\); - - \r.m.dci.lock_RNO_0\ : OR3 - port map(A => N_3749_2, B => N_3749_1, C => N_3749_3, Y => - N_3749); - - \r.d.inst_0_RNO[9]\ : NOR2B - port map(A => rst, B => N_4609, Y => \inst_0_RNO[9]\); - - \r.f.branch_RNIRIA332\ : MX2C - port map(A => rst_RNIINI1H, B => annul_RNIVI35T, S => - branch_RNIA8KSK, Y => \rbranch\); - - un6_ex_add_res_d2_ADD_33x33_fast_I272_Y : OR3B - port map(A => I272_un1_Y_i, B => I237_un1_Y_1, C => N650_1, - Y => N790_1); - - \r.f.pc_RNO_6[28]\ : MX2 - port map(A => \fpc[28]\, B => \eaddress[28]\, S => jump, Y - => N_4071); - - \r.a.rfa2_RNI099O2[5]\ : MX2 - port map(A => \un3_de_ren1[104]\, B => \rfa2[5]\, S => - holdn, Y => raddr2(5)); - - \r.m.y_RNO_4[12]\ : OR2B - port map(A => \y[13]\, B => mulstep_1, Y => \y_m[13]\); - - \r.m.y_RNO_0[8]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[8]\, C => \y_m[8]\, Y - => \y_iv_1[8]\); - - \r.e.op1_RNI2DUH[14]\ : MX2 - port map(A => \op1[14]\, B => \data_0[14]\, S => ldbp1_1, Y - => \un1_iu0_6[14]\); - - \r.d.annul_RNIV849\ : NOR3A - port map(A => un19_inst, B => annul_1, C => call_hold5_0, Y - => branch_1_sqmuxa_i); - - \r.a.ctrl.inst_RNIFG1L[24]\ : OR2A - port map(A => \inst_1[24]\, B => N_202, Y => N_259); - - \comb.branch_address.tmp_ADD_30x30_fast_I0_S_0\ : XOR2 - port map(A => \dpc[2]\, B => \inst_0_RNI0FUM[0]\, Y => - \tmp[2]\); - - un2_rstn_5_0_0_RNI5QOIQ4 : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[8]\, C => - \tmp_m[8]\, Y => \npc_iv_0[8]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I160_un1_Y\ : OR2B - port map(A => N534, B => N527_2, Y => I160_un1_Y_i); - - \r.w.s.pil_RNIJHGH8[0]\ : NOR3C - port map(A => \pil_m[0]\, B => \aluresult_1_iv_0[8]\, C => - \bpdata_m[8]\, Y => \aluresult_1_iv_4[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I79_Y_0 : AO1 - port map(A => N419_1, B => N415_1, C => N418_1, Y => N538_1); - - \r.x.ctrl.wy_RNILI9I\ : OR2 - port map(A => wy_2, B => annul_1_0, Y => y_1_sqmuxa_0); - - \r.d.inst_0_0_0[12]\ : DFN1 - port map(D => \inst_0_0_0_RNI7TVIO2[12]\, CLK => lclk_c, Q - => \un1_p0_6_0[51]\); - - \r.d.pc_RNO[24]\ : MX2 - port map(A => \fpc[24]\, B => \dpc[24]\, S => N_6763_i, Y - => \pc_RNO[24]\); - - \r.a.ctrl.pc_RNIP8M0C[8]\ : MX2 - port map(A => \pc[8]\, B => N_3885, S => ex_bpmiss_1_0, Y - => \fe_pc[8]\); - - \r.e.ldbp2_1_RNIMHAS57\ : OR2B - port map(A => \aluresult_1_iv_9[26]\, B => - \un6_ex_add_res_m[27]\, Y => \aluresult[26]\); - - \r.m.ctrl.inst_RNI211E[22]\ : OR2B - port map(A => \inst_2[22]\, B => \inst_0[24]\, Y => - inst_3_2_1); - - \r.m.y_RNINHBPL[17]\ : NOR3C - port map(A => \aluresult_1_iv_4[17]\, B => \bpdata_m_1[1]\, - C => \logicout_m_0[17]\, Y => \aluresult_1_iv_6[17]\); - - \r.e.aluop_RNIDBCS3[0]\ : MX2C - port map(A => N_3560, B => N_3624, S => \aluop_1[0]\, Y => - \logicout[1]\); - - \r.m.result_RNIVVO1[15]\ : OR2B - port map(A => d13, B => \maddress[15]\, Y => - \result_m_0[15]\); - - \r.w.s.ps\ : DFN1 - port map(D => ps_RNO, CLK => lclk_c, Q => ps); - - \r.x.ctrl.pc_RNIEIA71[28]\ : MX2C - port map(A => \un1_p0_6[380]\, B => \pc_0[28]\, S => - s_3_sqmuxa, Y => N_3419); - - \r.f.pc_RNO_3[14]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[14]\, C => - \xc_trap_address_m[14]\, Y => m7_0); - - \r.e.ctrl.rd_RNI6PSA2[0]\ : XA1A - port map(A => \rd[0]\, B => \rs1_iv_i_0[0]\, C => wreg_2_0, - Y => wreg_2_4); - - \r.a.rsel1_RNIKDB0O2[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[9]\, Y => - \aluresult_m_0[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I218_un1_Y\ : NOR2B - port map(A => N612, B => N597, Y => - ADD_30x30_fast_I218_un1_Y); - - \r.x.ctrl.tt_RNO[4]\ : MX2B - port map(A => \tt_2[3]\, B => un6_annul, S => tt_1_sqmuxa_1, - Y => \tt2[4]\); - - \r.m.y_RNO_0[24]\ : NOR3C - port map(A => N_374, B => N_371, C => \y_iv_0_1[24]\, Y => - \y_iv_0_2[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I1_G0N : NOR3A - port map(A => \op1[0]\, B => ldbp1_0, C => \data_0[0]\, Y - => N397); - - \r.e.ctrl.inst_RNIN01L[20]\ : NOR3B - port map(A => \inst_1[20]\, B => \inst_1[22]\, C => - \inst_0[23]\, Y => aluresult_12_sqmuxa_0); - - \r.e.op2_RNO_3[27]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[27]\, Y => - \aluresult_m_i[27]\); - - \r.e.shleft_1_RNIJEFP1\ : MX2A - port map(A => \shiftin_5[28]\, B => shleft_1_RNINGHP, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[12]\); - - \r.f.pc_RNI3AI9ME[11]\ : AO1A - port map(A => rst, B => \fpc[11]\, C => N_15, Y => N_26); - - \r.a.ctrl.inst_RNI013H1[21]\ : OR3A - port map(A => inst_5_1, B => N_201, C => inst_9_3, Y => - N_360); - - \r.m.y_RNO_0[2]\ : AOI1B - port map(A => wy_1_0, B => \y[2]\, C => \y_m[2]\, Y => - \y_iv_1[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I21_P0N : OR2 - port map(A => \un1_iu0_6[20]\, B => \op2[20]\, Y => N458); - - un6_ex_add_res_d1_ADD_33x33_fast_I180_Y : NOR2A - port map(A => N583_1, B => N591_0, Y => N649_1); - - \r.m.icc_RNI96A3[0]\ : XNOR2 - port map(A => \inst_0[28]\, B => \icc_0[0]\, Y => - branch_6_i); - - \r.e.aluop_RNIJ10O6[0]\ : MX2C - port map(A => N_3571, B => N_3635, S => \aluop_1[0]\, Y => - \logicout[12]\); - - \r.e.aluop_0_RNIJR2T2[1]\ : MX2C - port map(A => \logicout_4[18]\, B => N_6895, S => - N_6866_i_0, Y => N_3641); - - \comb.branch_address.tmp_ADD_30x30_fast_I280_Y_0_0\ : XOR2 - port map(A => \dpc[22]\, B => \inst_0[20]\, Y => - ADD_30x30_fast_I280_Y_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I74_Y\ : NAND2 - port map(A => I74_un1_Y_i, B => N376_i, Y => N491); - - \comb.branch_address.tmp_ADD_30x30_fast_I15_P0N\ : OR2 - port map(A => \inst_0[15]\, B => \dpc[17]\, Y => N404_0); - - \r.e.ctrl.inst_RNI31DJ[26]\ : OR3C - port map(A => N_229, B => \inst_1[26]\, C => N_523, Y => - ex_bpmiss_1_0_a5_4_1); - - \r.d.pc_RNO[11]\ : MX2 - port map(A => \fpc[11]\, B => \dpc[11]\, S => N_6763_i_0, Y - => \pc_RNO[11]\); - - \r.e.op1_RNIBA0C6[15]\ : OR3 - port map(A => \ex_op1_i_m[15]\, B => \op1_i_m[15]\, C => - \bpdata_i_m_2[7]\, Y => \edata2_0_iv_1[15]\); - - \r.a.ctrl.pc[6]\ : DFN1E0 - port map(D => \dpc[6]\, CLK => lclk_c, E => holdn, Q => - \pc_0[6]\); - - \r.m.result_RNI53K83[20]\ : NOR3C - port map(A => \d_iv_0[20]\, B => \result_m_0[20]\, C => - \rfo_m[20]\, Y => \d_iv_2[20]\); - - \r.d.inst_0_RNO_0[19]\ : MX2 - port map(A => data_0_0_19, B => \inst_0[19]\, S => - inull_RNIFV6VG2_0, Y => N_4619); - - un6_ex_add_res_d0_ADD_33x33_fast_I29_P0N : OR3A - port map(A => \data_0[28]\, B => \op1[28]\, C => ldbp1_3, Y - => N482_1); - - \r.e.ldbp2_0_RNIBFPFQ4\ : OR2A - port map(A => \eaddress[29]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[30]\); - - \r.e.jmpl_RNIDN24Q\ : OR2B - port map(A => \shiftin_17[17]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[17]\); - - \r.m.ctrl.pc_RNI62IF[27]\ : MX2 - port map(A => \pc_2[27]\, B => \pc_0[27]\, S => \npc_1[1]\, - Y => N_3268); - - \r.x.ctrl.rd[6]\ : DFN1E0 - port map(D => \rd_1[6]\, CLK => lclk_c, E => holdn, Q => - \rd_2[6]\); - - \r.x.ctrl.pc[8]\ : DFN1E0 - port map(D => \pc_3[8]\, CLK => lclk_c, E => holdn, Q => - \pc_0[8]\); - - \r.m.ctrl.pc[9]\ : DFN1E0 - port map(D => \pc[9]\, CLK => lclk_c, E => holdn, Q => - \pc_3[9]\); - - \r.e.ctrl.pc[15]\ : DFN1E0 - port map(D => \pc[15]\, CLK => lclk_c, E => holdn, Q => - \pc_2[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I160_Y : NOR3A - port map(A => N571_0, B => N497_2, C => N501, Y => N629); - - \r.a.ctrl.inst_RNIFK1L[21]\ : NOR2A - port map(A => \inst_2[21]\, B => N_472, Y => inst_5_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I165_Y\ : NOR2A - port map(A => N531, B => N539, Y => N591); - - \r.d.inst_0_RNO[22]\ : NOR2B - port map(A => rst, B => N_4622, Y => \inst_0_RNO[22]\); - - \r.x.result_RNITEIU5[0]\ : OR2B - port map(A => \bpdata[0]\, B => N_3957, Y => \bpdata_m[0]\); - - \r.a.rsel1_RNI1RFA_2[0]\ : NOR2A - port map(A => N_494, B => un17_casaen_0, Y => - un14_casaen_s0_0_0); - - wovf_exc_0_sqmuxa_RNO : MX2C - port map(A => N_3724, B => N_3727, S => \cwp_0[0]\, Y => - un25_op); - - \r.d.inst_0_RNIDGAF[20]\ : AOI1B - port map(A => ticc_exception_1, B => N_145, C => icc_check9, - Y => un1_icc_check5_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I309_Y_0 : XNOR3 - port map(A => \un1_iu0_6[18]\, B => \op2[18]\, C => N790_0, - Y => \un6_ex_add_res_s1_i[19]\); - - \r.w.s.y_RNO[22]\ : MX2 - port map(A => \y_2[22]\, B => \result_0[22]\, S => N_481_0, - Y => N_3786); - - un6_ex_add_res_d1_ADD_33x33_fast_I4_G0N : NOR2B - port map(A => \un1_iu0_6[3]\, B => \op2[3]\, Y => N406_0); - - \r.w.s.tba[17]\ : DFN1E1 - port map(D => \result_0[29]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[17]\); - - \r.e.op2[6]\ : DFN1E0 - port map(D => N_290, CLK => lclk_c, E => holdn, Q => - \op2[6]\); - - \r.m.icc_RNO_15[2]\ : NOR3A - port map(A => icc_0_sqmuxa_1_2, B => \logicout[6]\, C => - \logicout[5]\, Y => icc_0_sqmuxa_1_17); - - \r.d.inst_0_RNI0FUM[0]\ : NOR2B - port map(A => \inst_0[0]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI0FUM[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_Y_0 : AO1 - port map(A => N576_0, B => N569_0, C => N568_0, Y => - ADD_33x33_fast_I264_Y_0_0); - - \r.f.pc_RNIM5HB4[20]\ : MX2 - port map(A => \dpc[20]\, B => \fpc[20]\, S => - \ra_bpmiss_1_0\, Y => N_3897); - - un6_ex_add_res_d2_ADD_33x33_fast_I130_Y : NOR2A - port map(A => N527_1, B => ADD_33x33_fast_I130_Y_0_1, Y => - N593_1); - - \r.f.pc_RNO_1[29]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[29]\, C => - \pc_1_iv_0[29]\, Y => \pc_1_iv_1[29]\); - - \r.x.result_RNI1RIU5[1]\ : OR2B - port map(A => \bpdata[1]\, B => N_3957, Y => \bpdata_m[1]\); - - \r.f.pc_RNO[24]\ : OR3C - port map(A => \tmp_m[24]\, B => \pc_1_iv_1[24]\, C => - \un6_fe_npc_m[22]\, Y => \pc_1[24]\); - - \r.e.op1_RNIBP2B2[10]\ : AO1A - port map(A => \un1_iu0_6[10]\, B => edata_3_sqmuxa_0, C => - \op1_i_m[10]\, Y => \edata2_0_iv_0[10]\); - - \r.d.inst_0_RNI2423[13]\ : OR2B - port map(A => \inst_0[31]\, B => \inst_0[13]\, Y => N_126); - - un6_ex_add_res_d2_ADD_33x33_fast_I113_un1_Y : OR3B - port map(A => N458_0, B => N461_1, C => N514_2, Y => - I113_un1_Y_i); - - \r.e.shleft_0_RNIL7CQ1\ : MX2C - port map(A => \shiftin_5[19]\, B => \shiftin_5[3]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[3]\); - - \r.x.data_0_RNO_1[6]\ : NOR3C - port map(A => \dco_m_i[110]\, B => \data_0_m_i[6]\, C => - \dco_m_i[126]\, Y => \data_0_1_1_iv_1[6]\); - - \r.x.ctrl.tt_RNI9PVQ[2]\ : MX2 - port map(A => \result_0[2]\, B => \tt[2]\, S => tt_i, Y => - N_3321); - - \r.f.pc_RNO_1[16]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[16]\, C => - \pc_1_iv_0[16]\, Y => \pc_1_iv_1[16]\); - - \r.x.data_0_RNO_0[24]\ : NOR3B - port map(A => \data_0_m_i[24]\, B => \dco_m_1_i[120]\, C - => \rdata_5_m_9[8]\, Y => \data_0_1_1_iv_1[24]\); - - \r.w.s.ps_RNIJK089\ : NOR3C - port map(A => \aluresult_1_iv_1[6]\, B => ps_m_0, C => - \aluresult_1_iv_4[6]\, Y => \aluresult_1_iv_5[6]\); - - \r.m.y_RNO_2[20]\ : OR2A - port map(A => \logicout[20]\, B => y14, Y => - \logicout_m[20]\); - - \r.f.pc_RNO_6[13]\ : MX2 - port map(A => \fpc[13]\, B => \eaddress[13]\, S => jump_0, - Y => N_4056); - - \r.m.result_RNO[15]\ : MX2 - port map(A => \aluresult[15]\, B => \op1[15]\, S => - un17_casaen_0_1, Y => \eres2[15]\); - - \r.m.irqen2_RNISH4E3\ : NOR3B - port map(A => un3_irl, B => un6_annul_2, C => annul_RNIPFOQ, - Y => un6_annul_4); - - \r.e.op2_RNO_7[18]\ : OR3C - port map(A => d28_0, B => \rsel2_1[0]\, C => - \un1_p0_6[370]\, Y => \cpi_m_i[370]\); - - \r.m.y_RNO[26]\ : AO1C - port map(A => y14_0, B => \logicout[26]\, C => \y_iv_2[26]\, - Y => \y_0[26]\); - - \r.x.data_0_RNO[30]\ : OR3 - port map(A => \dco_m_1[126]\, B => \data_0_m[30]\, C => - \data_0_1_4[18]\, Y => \data_0_1[30]\); - - \r.m.icc_RNILOP8[1]\ : NOR2B - port map(A => \icc[1]\, B => \inst_0[24]\, Y => - trap_0_sqmuxa_2_1); - - \comb.lock_gen.ldchkra_RNITJNF\ : AND2 - port map(A => ldchkra, B => ldlock2_0, Y => ldlock2_1); - - \r.m.y_RNIT52T5[12]\ : NOR3C - port map(A => \aluresult_1_iv_1[12]\, B => - \aluresult_1_iv_0[12]\, C => \tba_m[0]\, Y => - \aluresult_1_iv_3[12]\); - - \r.f.pc_RNO_1[5]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[5]\, C => - \xc_trap_address_m[5]\, Y => \pc_1_iv_0[5]\); - - \r.x.result_RNINC6E[15]\ : MX2 - port map(A => \result_0[15]\, B => \data_0_2[15]\, S => - ld_4, Y => \un1_p0_6[367]\); - - \r.x.data_0_RNO_0[23]\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_14, B => mcdo_m_0_21, C => - rdata_6_sqmuxa, Y => \dco_m_0[119]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I205_Y : AO1 - port map(A => N611_0, B => N552_0, C => N610_2, Y => N676_1); - - \r.m.dci.lock_RNI09G7\ : NOR2A - port map(A => lock_0, B => annul_5, Y => lock); - - \r.e.jmpl_RNID6FUG1\ : AOI1B - port map(A => \shiftin_17[19]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[18]\, Y => \aluresult_1_iv_7[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I111_Y : AO1 - port map(A => N512_1, B => N509_0, C => N508_0, Y => N574_0); - - \r.d.pc_RNO[26]\ : MX2 - port map(A => \fpc[26]\, B => \dpc[26]\, S => N_6763_i, Y - => \pc_RNO[26]\); - - \r.x.data_0_RNO_0[18]\ : AOI1B - port map(A => rdatav_0_1_0_iv_5_0, B => mcdo_m_0_16, C => - rdata_6_sqmuxa, Y => \dco_m_0[114]\); - - \r.e.op2_RNO_2[31]\ : NOR3C - port map(A => \d_1_iv_1[31]\, B => \d_1_iv_0[31]\, C => - \rfo_m_i[63]\, Y => \d_1_iv_3[31]\); - - \comb.un6_xc_exception_RNI1M3D\ : NAND2 - port map(A => un6_xc_exception, B => - \xc_trap_address_m_0[2]\, Y => \xc_trap_address_m[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I322_Y_0 : AX1E - port map(A => I259_un1_Y_0, B => ADD_33x33_fast_I259_Y_3_0, - C => \un6_ex_add_res_s2_1[32]\, Y => - \un6_ex_add_res_s2[32]\); - - \r.m.y_RNI5QAV2[28]\ : AOI1B - port map(A => \y[28]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[28]\, Y => \aluresult_1_iv_0[28]\); - - \r.w.result_RNI6MDI[14]\ : AOI1B - port map(A => \un1_p0_6[366]\, B => d14_0, C => - \result_m_0_0[14]\, Y => \d_iv_0[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I106_Y\ : AO1 - port map(A => N471, B => N468, C => N467_1, Y => N526); - - \r.e.ctrl.pc_RNINMOI4[19]\ : NOR3C - port map(A => \ex_op2_m[19]\, B => aluresult_8_sqmuxa_i, C - => \aluresult_1_iv_1[19]\, Y => \aluresult_1_iv_2[19]\); - - \r.d.pc_RNO[20]\ : MX2 - port map(A => \fpc[20]\, B => \dpc[20]\, S => N_6763_i_0, Y - => \pc_RNO[20]\); - - \r.e.shleft_RNIPG831\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[2]\, S => shleft, - Y => \shiftin_5[33]\); - - \r.f.pc[13]\ : DFN1E0 - port map(D => \pc_1[13]\, CLK => lclk_c, E => holdn, Q => - \fpc[13]\); - - \r.a.imm[20]\ : DFN1E0 - port map(D => \un3_de_ren1[138]\, CLK => lclk_c, E => holdn, - Q => \imm[20]\); - - \r.w.s.y_RNO[30]\ : MX2 - port map(A => \y_2[30]\, B => \result_0[30]\, S => N_481_0, - Y => N_3794); - - \comb.v.x.data_0_1_1_iv_RNO[19]\ : OR2 - port map(A => \data_0_1_1[16]\, B => \data_0_1_1_iv_0[19]\, - Y => \data_0_1_1_iv_1[19]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I7_G0N\ : NOR2B - port map(A => \inst_0[7]\, B => \dpc[9]\, Y => N379); - - \r.e.shleft_0_RNI455I1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[30]\, S => - shleft_0, Y => \shiftin_5[61]\); - - \r.e.ctrl.inst[6]\ : DFN1E0 - port map(D => \inst[6]\, CLK => lclk_c, E => holdn, Q => - \inst_1[6]\); - - \r.a.imm_RNO[23]\ : MX2 - port map(A => \inst_0[13]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[141]\); - - \r.d.cwp[0]\ : DFN1E0 - port map(D => \cwp_1_1[0]\, CLK => lclk_c, E => holdn, Q - => \cwp_0[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I19_G0N : NOR2B - port map(A => \un1_iu0_6[18]\, B => \op2[18]\, Y => N451_1); - - \r.x.data_0[27]\ : DFN1E0 - port map(D => \data_0_1[27]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[27]\); - - \r.f.pc_RNO_1[30]\ : NOR3C - port map(A => \pc_4_m[30]\, B => \xc_trap_address_m[30]\, C - => \un6_ex_add_res_m_1[31]\, Y => \pc_1_iv_1[30]\); - - \r.m.y_RNO_4[24]\ : OR3A - port map(A => \y_2[24]\, B => wy_3, C => wy_1_0_1, Y => - N_372); - - \r.e.invop2_RNIOFG59\ : MX2 - port map(A => \un6_ex_add_res_s2[7]\, B => - \un6_ex_add_res_s0[7]\, S => invop2, Y => N_6646); - - un6_ex_add_res_d0_ADD_33x33_fast_I267_Y : NAND2 - port map(A => I267_un1_Y_0, B => ADD_33x33_fast_I267_Y_0_0, - Y => N780); - - \r.d.inst_0[27]\ : DFN1 - port map(D => \inst_0_RNO[27]\, CLK => lclk_c, Q => - \inst_0[27]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I106_Y : NOR2A - port map(A => N503_0, B => N_15_0, Y => N569_0); - - \r.a.ctrl.inst[24]\ : DFN1E0 - port map(D => \inst_0_0[24]\, CLK => lclk_c, E => holdn, Q - => \inst_1[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I182_Y : NOR2B - port map(A => N593, B => N585, Y => N651_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I54_Y : OA1A - port map(A => \data_0_2[20]\, B => \un1_iu0_6[20]\, C => - N455_0, Y => N513_0); - - \r.e.ctrl.annul_RNIDR5HD1\ : OR2A - port map(A => un12_de_hold_pc, B => \de_hold_pc_1\, Y => - un2_rstn_5_2); - - \r.x.result_RNIJ22O3[16]\ : MX2 - port map(A => \un1_iu0_6[16]\, B => \un1_p0_6[368]\, S => - bpdata6_0_0, Y => \bpdata[16]\); - - \r.e.aluop_RNIUDI14[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[3]\, Y => - \bpdata_i_m_2[3]\); - - \r.x.y[11]\ : DFN1E0 - port map(D => \y_0[11]\, CLK => lclk_c, E => holdn, Q => - \y_2[11]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I111_un1_Y : OR3C - port map(A => N461, B => N464_2, C => N512, Y => - I111_un1_Y_i); - - \r.m.ctrl.pc[25]\ : DFN1E0 - port map(D => \pc[25]\, CLK => lclk_c, E => holdn, Q => - \pc_3[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0\ : OR3C - port map(A => N_41, B => ADD_30x30_fast_I233_Y_0_0, C => - N_39_0, Y => N696); - - \r.m.ctrl.inst[22]\ : DFN1E0 - port map(D => \inst_1[22]\, CLK => lclk_c, E => holdn, Q - => \inst_2[22]\); - - \r.e.shcnt_RNIFVKOC[2]\ : MX2C - port map(A => \shiftin_11[23]\, B => \shiftin_11[19]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[19]\); - - \r.e.aluop_RNIOBIJ1[2]\ : XA1 - port map(A => \un1_iu0_5[97]\, B => \aluop_1[2]\, C => - \un1_iu0_6[31]\, Y => N_3558); - - \comb.branch_address.tmp_ADD_30x30_fast_I218_Y\ : NOR2 - port map(A => N596, B => ADD_30x30_fast_I218_un1_Y, Y => - N726_i); - - \r.x.rstate_RNIK4IR1[0]\ : MX2C - port map(A => N_3394, B => \xc_result[3]\, S => \rstate[0]\, - Y => \wdata[3]\); - - \r.e.op1_RNIR6CR1[23]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[23]\, Y => - \ex_op1_i_m[23]\); - - \r.f.pc_RNO_5[29]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[29]\, Y => \xc_trap_address_m[29]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I188_Y : NOR2 - port map(A => N599_0, B => N591_2, Y => N657_1); - - \r.x.ctrl.pc_RNIQRH61[12]\ : MX2C - port map(A => \un1_p0_6[364]\, B => \pc_0[12]\, S => - s_3_sqmuxa_0, Y => N_3403); - - \comb.branch_address.tmp_ADD_30x30_fast_I103_Y\ : NOR2B - port map(A => N468, B => N464_1, Y => N523); - - \r.f.pc_RNO_7[24]\ : MX2 - port map(A => \fpc[24]\, B => \tba[12]\, S => rstate_6314_d, - Y => \xc_trap_address[24]\); - - \r.f.pc_RNO_3[21]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[21]\, C => - \xc_trap_address_m[21]\, Y => \pc_1_iv_0[21]\); - - \r.e.alucin_RNO_0\ : NOR3C - port map(A => alucin_RNO_2, B => N_350, C => cin_iv_i_0, Y - => cin_iv_i_2); - - \r.x.data_0_RNO_1[2]\ : OA1A - port map(A => data_0_0_26, B => rdata_0_sqmuxa, C => - \data_0_1_1_iv_0[2]\, Y => \data_0_1_1_iv_1[2]\); - - \r.e.op2_RNO_7[25]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[377]\, - Y => \cpi_m_i[377]\); - - \r.x.result[0]\ : DFN1E0 - port map(D => \maddress[0]\, CLK => lclk_c, E => holdn, Q - => \result[0]\); - - \r.x.dci.size_RNIFJHJI[1]\ : NOR2B - port map(A => ld_3, B => \me_size_1[1]\, Y => - rdata_6_sqmuxa); - - \r.x.result_RNIRKP65[0]\ : OR2B - port map(A => \bpdata[0]\, B => N_3957_1, Y => - \bpdata_m_1[0]\); - - \r.e.op2_RNIVFMB1_0[22]\ : OR2 - port map(A => \un1_iu0_6[22]\, B => \un1_iu0_5[88]\, Y => - \logicout_3[22]\); - - \r.m.result_RNICFD4[17]\ : OR2B - port map(A => d13_0, B => \maddress[17]\, Y => - \result_m_0[17]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I279_Y_0\ : XOR2 - port map(A => N714, B => ADD_30x30_fast_I279_Y_0_0, Y => - \tmp[21]\); - - \r.x.result_RNIHN5B[4]\ : OR2B - port map(A => \un1_p0_6[356]\, B => d14, Y => - \cpi_m_0[356]\); - - \r.w.s.icc_RNO_1[1]\ : OR2B - port map(A => icc_0_sqmuxa, B => \icc_3[1]\, Y => - \icc_m_0[1]\); - - \r.e.ctrl.rd_RNISJ8T9[4]\ : NOR3C - port map(A => un1_de_ren1_4_i_0, B => wreg_1_4, C => - un1_de_ren1_5_i_0, Y => wreg_1_6); - - \r.w.s.y[22]\ : DFN1E0 - port map(D => N_3786, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[22]\); - - \comb.v.x.data_0_1_1_iv[16]\ : OR2 - port map(A => \data_0_1_2[17]\, B => \data_0_1_1_iv_1[16]\, - Y => \data_0_1[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I168_Y : NOR2B - port map(A => N579_0, B => N571_2, Y => N637_1); - - \r.x.ctrl.inst_RNI0MFG[24]\ : OR2A - port map(A => \inst_2[24]\, B => \rstate_d[2]\, Y => - tba_1_sqmuxa_3); - - \r.e.op2_RNI7C9P[1]\ : OR2A - port map(A => \op2_RNI1LHG[1]\, B => \un1_iu0_6[1]\, Y => - \logicout_4[1]\); - - \r.e.aluop_RNIKJC91[2]\ : XA1 - port map(A => \un1_iu0_5[86]\, B => \aluop_1[2]\, C => - \un1_iu0_6[20]\, Y => N_3547); - - \r.d.pv_RNI36O874\ : OR3C - port map(A => un2_exbpmiss, B => - un1_annul_next_1_sqmuxa_3_3, C => annul_next_2_sqmuxa_1_8, - Y => un1_annul_next_1_sqmuxa_3); - - wovf_exc_0_sqmuxa_RNO_3 : MX2 - port map(A => \wim_1[3]\, B => \wim_1[7]\, S => \ncwp_3[2]\, - Y => N_3723); - - un6_ex_add_res_d1_ADD_33x33_fast_I239_un1_Y : NOR2B - port map(A => N668, B => N653, Y => I239_un1_Y_0); - - \r.e.op2_RNIM3HN1[13]\ : OR2B - port map(A => \un1_iu0_5[79]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[13]\); - - \r.e.ldbp2_1_RNI7QDSS2\ : OR2A - port map(A => \eaddress[18]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[19]\); - - \r.e.op1_RNINQ8G[12]\ : OR2B - port map(A => \op1[12]\, B => un14_casaen_s1_0, Y => - \op1_m_0[12]\); - - \r.m.result[28]\ : DFN1E0 - port map(D => \eres2[28]\, CLK => lclk_c, E => holdn, Q => - \maddress[28]\); - - \comb.cwp_ctrl.ncwp_3_I_14\ : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[2]\, B => - \DWACT_ADD_CI_0_g_array_1_3[0]\, Y => \ncwp_3[2]\); - - \r.e.shcnt_RNIL4ER8[2]\ : MX2C - port map(A => \shiftin_11[4]\, B => \shiftin_11[0]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[0]\); - - \r.e.op2_RNO_1[17]\ : OR2B - port map(A => \op1[17]\, B => un14_casaen_s1, Y => - \op1_m_i[17]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I71_Y_0 : AO1 - port map(A => N431_0, B => N427_0, C => N430_0, Y => N530_2); - - \r.w.s.icc_RNO_0[0]\ : AOI1B - port map(A => icc_2_sqmuxa, B => \result[20]\, C => - \icc_m_0[0]\, Y => \icc_1_iv_0[0]\); - - \r.e.shcnt_RNO[1]\ : XOR2 - port map(A => \d_1[1]\, B => N_208, Y => N_267_i_i_0); - - un9_ra_I_14 : XOR2 - port map(A => \cwp_0[2]\, B => - \DWACT_ADD_CI_0_g_array_1_2[0]\, Y => I_14_2); - - \r.x.data_0[1]\ : DFN1E0 - port map(D => \data_0_1[1]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[1]\); - - \r.d.inst_0_RNO_0[31]\ : MX2 - port map(A => data_0_2_31, B => \inst_0[31]\, S => - inull_RNIFV6VG2_0, Y => N_4631); - - un6_ex_add_res_d2_ADD_33x33_fast_I24_G0N : NOR2B - port map(A => \un1_iu0_6[23]\, B => \data_0[23]\, Y => - N466_0); - - \r.x.result_RNIQMED[14]\ : MX2 - port map(A => \result_0[14]\, B => \data_0[14]\, S => ld_0, - Y => \un1_p0_6[366]\); - - \r.w.s.y_RNO[29]\ : NOR3 - port map(A => N_413, B => N_412, C => N_414, Y => N_174); - - \r.a.ctrl.inst[27]\ : DFN1E0 - port map(D => \inst_0[27]\, CLK => lclk_c, E => holdn, Q - => \inst_2[27]\); - - \r.f.branch\ : DFN1E0 - port map(D => \rbranch\, CLK => lclk_c, E => holdn, Q => - \fbranch\); - - \r.x.mexc_RNIQ5MM\ : NOR2 - port map(A => mexc_0, B => tt_i, Y => xc_vectt14); - - \comb.branch_address.tmp_ADD_30x30_fast_I161_Y\ : NOR3C - port map(A => N476_0, B => N480, C => N527_2, Y => N587); - - \comb.branch_address.tmp_ADD_30x30_fast_I117_Y\ : OR2B - port map(A => ADD_30x30_fast_I117_Y_0, B => N478_0, Y => - N537); - - un6_ex_add_res_d1_ADD_33x33_fast_I293_Y_0 : XNOR2 - port map(A => ADD_33x33_fast_I293_Y_0_0, B => N616_0, Y => - \un6_ex_add_res_s1_i[3]\); - - \r.e.aluop_2_RNI84413[1]\ : MX2C - port map(A => N_3548, B => \logicout_3[21]\, S => - \aluop_2[1]\, Y => N_3580); - - \r.e.op1_RNIGBO8[6]\ : MX2 - port map(A => \op1[6]\, B => \data_0[6]\, S => ldbp1_1, Y - => \un1_iu0_6[6]\); - - \r.x.rstate_0_RNIOG082[0]\ : MX2C - port map(A => N_3397, B => \xc_result[6]\, S => - \rstate_0[0]\, Y => \wdata[6]\); - - \r.d.annul_RNICD012\ : AOI1 - port map(A => bicc_hold_3, B => N_3718, C => annul_RNIETIP, - Y => \ldlock_3_0\); - - \r.e.op2_RNO_6[7]\ : OR2B - port map(A => data2(7), B => d25_0, Y => \rfo_m_i[39]\); - - \r.e.op2_RNIH5402[8]\ : AOI1B - port map(A => \un1_iu0_5[74]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[8]\); - - \r.a.ctrl.inst_RNIFG1L[23]\ : OR2A - port map(A => \inst_1[23]\, B => inst_9_3, Y => N_515); - - \r.m.y_RNITHO71[25]\ : OR2B - port map(A => \y_2[25]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[25]\); - - \r.f.pc_RNO_6[21]\ : MX2 - port map(A => \fpc[21]\, B => \eaddress[21]\, S => jump_0, - Y => N_4064); - - \r.w.s.y_RNO_0[29]\ : NOR2A - port map(A => N_481, B => \result_0[29]\, Y => N_413); - - \r.e.op1_RNIP29G[14]\ : OR2B - port map(A => \op1[14]\, B => un14_casaen_s1_0, Y => - \op1_m_0[14]\); - - un2_rstn_5_RNI87L95 : NAND2 - port map(A => \tmp[6]\, B => \un2_rstn_5\, Y => N_39); - - \r.e.shcnt_RNO[0]\ : XOR2 - port map(A => \d_1[0]\, B => N_208, Y => N_266_i_i_0); - - \r.x.result_RNI08LA[8]\ : MX2 - port map(A => \result[8]\, B => \data_0[8]\, S => ld_0, Y - => \un1_p0_6[360]\); - - \r.w.s.tba_RNII1TPG[10]\ : NOR3C - port map(A => \aluresult_1_iv_4[22]\, B => - \aluresult_1_iv_3[22]\, C => \bpdata_m_1[6]\, Y => - \aluresult_1_iv_6[22]\); - - \r.m.ctrl.pc[30]\ : DFN1E0 - port map(D => \pc_0[30]\, CLK => lclk_c, E => holdn, Q => - \pc_3[30]\); - - \r.e.shcnt_RNI5072V[1]\ : MX2 - port map(A => \shiftin_14[33]\, B => \shiftin_14[31]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[31]\); - - \r.x.data_0_RNO_2[17]\ : NOR2A - port map(A => \data_0[17]\, B => ld_0_0, Y => - \data_0_m[17]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I54_Y\ : MAJ3 - port map(A => \dpc[18]\, B => \inst_0[16]\, C => N403, Y - => N471); - - un6_ex_add_res_d1_ADD_33x33_fast_I73_Y : MAJ3 - port map(A => \op2[10]\, B => \un1_iu0_6[10]\, C => N424_2, - Y => N532_0); - - \r.a.rsel1_RNIPFH[2]\ : NOR2A - port map(A => N_484, B => \rsel1[2]\, Y => d13); - - un6_fe_npc_I_12 : AND3 - port map(A => \fe_pc[2]\, B => \fe_pc[3]\, C => \fe_pc[4]\, - Y => N_144); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_Y_0 : AOI1 - port map(A => N578_0, B => N571, C => N570, Y => - ADD_33x33_fast_I265_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I249_un1_Y : NOR2B - port map(A => N669, B => N552, Y => I249_un1_Y_0); - - \r.e.op1_RNI9LUH[16]\ : MX2 - port map(A => \op1[16]\, B => \data_0[16]\, S => ldbp1_4, Y - => \un1_iu0_6[16]\); - - \r.x.data_0_RNO_1[27]\ : NOR2A - port map(A => \data_0[27]\, B => ld_3, Y => \data_0_m[27]\); - - \r.m.y_RNO[9]\ : AO1C - port map(A => y14_0, B => \logicout[9]\, C => \y_iv_2[9]\, - Y => \y_0[9]\); - - \r.a.ctrl.inst_RNI293H1[24]\ : OR3A - port map(A => N_472, B => N_212, C => N_259, Y => - cp_disabled_5_sqmuxa); - - \r.a.rsel1_RNIQQVRB5[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[19]\, Y - => \aluresult_m_0[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I68_Y : AND2 - port map(A => N434_0, B => N437_0, Y => N527_0); - - \r.a.ctrl.inst_RNI5H3O1[23]\ : OR3 - port map(A => N_202, B => illegal_inst37_4, C => N_201, Y - => N_346); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_a3_1_0 : NOR2B - port map(A => alucin, B => N398_0, Y => - ADD_33x33_fast_I206_Y_0_a3_1_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I322_Y_0 : AX1C - port map(A => I259_un1_Y_1, B => ADD_33x33_fast_I259_Y_3, C - => \un6_ex_add_res_s2_1[32]\, Y => - \un6_ex_add_res_s0[32]\); - - \r.w.result_RNICD4P3[1]\ : NOR3C - port map(A => \d_1_iv_1[1]\, B => \d_1_iv_0[1]\, C => - \rfo_m_i[33]\, Y => \d_1_iv_3[1]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I243_un1_Y\ : NOR3C - port map(A => N605, B => N589, C => N501_0, Y => I243_un1_Y); - - \r.a.rfa1_RNIS1041[7]\ : MX2 - port map(A => \un3_de_ren1[98]\, B => \rfa1[7]\, S => holdn, - Y => raddr1(7)); - - un6_ex_add_res_d0_ADD_33x33_fast_I237_un1_Y : NOR2B - port map(A => N666, B => N651_0, Y => I237_un1_Y); - - \r.m.y_RNO_3[9]\ : AOI1B - port map(A => wy_1_0, B => \y[9]\, C => \y_m[9]\, Y => - \y_iv_1[9]\); - - \r.m.result_RNI522A3[0]\ : NOR3C - port map(A => \d_iv_0[0]\, B => \result_m_0[0]\, C => - \rfo_m[0]\, Y => \d_iv_2[0]\); - - \r.e.ctrl.pc_RNIE3E92[19]\ : AOI1B - port map(A => \pc[19]\, B => jmpl_0, C => \y_m_1[19]\, Y - => \aluresult_1_iv_1[19]\); - - \r.w.s.wim[4]\ : DFN1E0 - port map(D => \wim_1[4]\, CLK => lclk_c, E => holdn, Q => - \wim[4]\); - - un2_rstn_5_RNI9UJNL9 : OR2B - port map(A => m21_2, B => N_6618, Y => N_22); - - \r.e.op2_RNO_2[26]\ : NOR3C - port map(A => \d_1_iv_1[26]\, B => \d_1_iv_0[26]\, C => - \rfo_m_i[58]\, Y => \d_1_iv_3[26]\); - - \r.a.ctrl.inst_RNI6L3O1[22]\ : NOR3B - port map(A => illegal_inst_1_sqmuxa_i_0, B => N_433, C => - N_201, Y => illegal_inst_1_sqmuxa_i_2); - - \r.x.nerror_RNO\ : NOR2B - port map(A => rst, B => error, Y => nerror_1); - - \r.e.ldbp2\ : DFN1E0 - port map(D => ldbp2, CLK => lclk_c, E => holdn, Q => - ldbp2_3); - - un6_ex_add_res_d2_ADD_33x33_fast_I116_Y : NOR2A - port map(A => N513_2, B => N517_1, Y => N579_1); - - \r.m.ctrl.inst[31]\ : DFN1E0 - port map(D => \inst_2[31]\, CLK => lclk_c, E => holdn, Q - => \inst_1[31]\); - - \r.m.werr_RNIA2H4\ : OR2 - port map(A => werr_0, B => werr_2, Y => werr); - - \r.f.pc_RNO_5[16]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[16]\, Y => \xc_trap_address_m[16]\); - - \r.e.alusel_RNIRC5C_1[0]\ : NOR3A - port map(A => \alusel[1]\, B => \alusel[0]\, C => jmpl, Y - => aluresult_3_sqmuxa_0); - - \r.e.ldbp1_1\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_1); - - \r.e.jmpl_RNO\ : NOR2A - port map(A => jmpl_2, B => trap_1, Y => N_4); - - \r.m.werr\ : DFN1 - port map(D => werr_RNO, CLK => lclk_c, Q => werr_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_un1_Y_0 : NOR2B - port map(A => N629_0, B => N645, Y => - ADD_33x33_fast_I261_un1_Y_0); - - \r.d.pc_RNIMTGB4[13]\ : MX2 - port map(A => \dpc[13]\, B => \fpc[13]\, S => ra_bpmiss_1, - Y => N_3890); - - \r.x.data_0_RNO_3[4]\ : OR2B - port map(A => N_3455, B => data_0_0_20, Y => \dco_m_i[116]\); - - \r.f.pc_RNO_3[12]\ : NAND2 - port map(A => \tmp[12]\, B => un2_rstn_5_0, Y => - \tmp_m[12]\); - - \r.e.op1[18]\ : DFN1E0 - port map(D => \aop1[18]\, CLK => lclk_c, E => holdn, Q => - \op1[18]\); - - \r.a.imm_RNICUT01[4]\ : NOR3C - port map(A => \result_m_i[4]\, B => \imm_m_i[4]\, C => - \d_1_iv_1[4]\, Y => \d_1_iv_2[4]\); - - \r.d.inull\ : DFN1E0 - port map(D => de_inull, CLK => lclk_c, E => holdn, Q => - \inull\); - - \r.m.result_RNI3D5D3[27]\ : NOR3C - port map(A => \d_iv_0[27]\, B => \result_m_0[27]\, C => - \rfo_m[27]\, Y => \d_iv_2[27]\); - - \r.e.op2_RNIU6OP[31]\ : MX2 - port map(A => \op2[31]\, B => N_4278, S => ldbp2_1, Y => - \un1_iu0_5[97]\); - - \r.e.shcnt_RNI56DTT[1]\ : MX2C - port map(A => \shiftin_14[30]\, B => \shiftin_14[28]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[28]\); - - \r.e.aluop_RNI5N3F4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[27]\, Y => - \aluop_RNI5N3F4[1]\); - - GND_i : GND - port map(Y => \GND\); - - wovf_exc_0_sqmuxa_RNO_2 : MX2 - port map(A => \wim_1[1]\, B => \wim_1[5]\, S => \ncwp_3[2]\, - Y => N_3722); - - \r.d.annul_RNILQG71\ : AO1 - port map(A => ldcheck2_0_sqmuxa_1, B => ldcheck2_0_sqmuxa, - C => annul_1, Y => annul_RNILQG71); - - \comb.branch_address.tmp_ADD_30x30_fast_I271_Y_0_0\ : XOR2 - port map(A => \dpc[13]\, B => \inst_0[11]\, Y => - ADD_30x30_fast_I271_Y_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I19_P0N : AO1A - port map(A => ldbp1_3, B => \op1[18]\, C => \data_0_0[18]\, - Y => N452_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_Y : NAND2 - port map(A => I261_un1_Y, B => ADD_33x33_fast_I261_Y_2, Y - => N768_0); - - \r.e.op1_RNIPACR1[15]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[15]\, Y => - \ex_op1_i_m[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I313_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[23]\, B => N782_1, Y => - \un6_ex_add_res_s0[23]\); - - \r.x.ctrl.annul_RNI7RVD3\ : OR2 - port map(A => y6_2, B => annul_1_0, Y => et_0_sqmuxa_i); - - \comb.cwp_ctrl.un7_op_0_a3\ : NAND2 - port map(A => N_142, B => wy_1_0_a3_1_0, Y => un7_op); - - \r.x.result_RNI5L6E[29]\ : MX2 - port map(A => \result_0[29]\, B => \data_0_0[29]\, S => - ld_4, Y => \un1_p0_6[381]\); - - \r.x.npc_RNIUABL[0]\ : MX2C - port map(A => N_3241, B => N_3271, S => \npc[0]\, Y => - \xc_result[30]\); - - \r.d.inst_0_RNO_0[24]\ : MX2 - port map(A => data_0_2_24, B => \inst_0_0[24]\, S => - inull_RNIFV6VG2_0, Y => N_4624); - - \comb.op_mux.d_1_iv_RNO_3[29]\ : OA1A - port map(A => \maddress[29]\, B => d27_0, C => - \cpi_m_i[381]\, Y => \d_1_iv_1[29]\); - - \r.a.rsel1_RNI4RCNJ5[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[20]\, Y => - \aluresult_m_0[20]\); - - \r.a.imm[0]\ : DFN1E0 - port map(D => \un3_de_ren1[118]\, CLK => lclk_c, E => holdn, - Q => \imm[0]\); - - \r.e.shleft_1_RNIHHIM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[27]\, S => - shleft_1, Y => \shiftin_5[58]\); - - \r.a.ctrl.inst_RNIERBU3[20]\ : NOR3C - port map(A => N_365, B => \inst_RNILL631[19]\, C => N_362, - Y => aluop_0_1_0_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I199_Y : OAI1 - port map(A => N603_i, B => N610_0, C => N602_1, Y => N668_0); - - \r.e.op2_RNO_6[17]\ : OR2B - port map(A => data2(17), B => d25, Y => \rfo_m_i[49]\); - - \r.e.ctrl.inst_RNIPS1E[26]\ : NOR2B - port map(A => \inst_1[26]\, B => \inst_1[27]\, Y => - ex_bpmiss_1_0_a5_0_0); - - \r.d.inst_0_0_0_RNIQKFJ[21]\ : NOR3A - port map(A => not_valid, B => \un1_p0_6_0[60]\, C => - annul_1, Y => bicc_hold_1); - - \r.d.annul_RNIIHK0F_0\ : AO1 - port map(A => branch_0, B => bpmiss_1_i_0_0, C => - un2_rstn_5_0_i, Y => un2_rstn_4_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I11_G0N\ : NOR2B - port map(A => \inst_0[11]\, B => \dpc[13]\, Y => N391); - - \r.a.rfa2[5]\ : DFN1E0 - port map(D => \un3_de_ren1[104]\, CLK => lclk_c, E => holdn, - Q => \rfa2[5]\); - - \r.e.aluop_1_RNI20193[1]\ : MX2C - port map(A => \logicout_4[14]\, B => N_6901, S => N_6866_i, - Y => N_3637); - - un6_fe_npc_I_97 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \fe_pc[17]\, Y => N_83); - - \r.f.pc_RNO_2[19]\ : OR2B - port map(A => I_105, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[17]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I239_un1_Y : OR2B - port map(A => N668_0, B => N653_1, Y => I239_un1_Y_i); - - \r.a.ctrl.wreg_RNO_5\ : NOR3 - port map(A => N_89, B => \inst_0_0[22]\, C => un1_inst, Y - => write_reg_4_sqmuxa); - - \r.e.shleft_0_RNITKLK1\ : MX2C - port map(A => \shiftin_5[18]\, B => \shiftin_5[2]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[2]\); - - \r.d.annul_RNIU4C2O1\ : OA1A - port map(A => annul_next_1_sqmuxa_1_6, B => ldlock, C => - un1_annul_next_1_sqmuxa_3_2, Y => - un1_annul_next_1_sqmuxa_3_3); - - \r.a.ctrl.inst_RNILL631[19]\ : OR2 - port map(A => aluop_1_1_0_a5_0, B => N_472, Y => - \inst_RNILL631[19]\); - - \r.f.pc[8]\ : DFN1E0 - port map(D => \pc_1[8]\, CLK => lclk_c, E => holdn, Q => - \fpc[8]\); - - \r.d.pv_RNO_4\ : OR3 - port map(A => ex_bpmiss_1_0, B => annul_2, C => - \de_hold_pc_1\, Y => N_4242); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_Y_1 : AOI1B - port map(A => N498, B => N495_0, C => - ADD_33x33_fast_I260_Y_0_1, Y => ADD_33x33_fast_I260_Y_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I313_Y_0 : XNOR3 - port map(A => \un1_iu0_6[22]\, B => \op2[22]\, C => N782_0, - Y => \un6_ex_add_res_s1_i[23]\); - - \r.a.rsel2_0_RNI7V53_2[0]\ : NOR2A - port map(A => d26_0, B => \rsel2_0[0]\, Y => d25); - - \r.a.rsel1_RNIPFH[0]\ : NOR3B - port map(A => \rsel1[0]\, B => \rsel1[1]\, C => \rsel1[2]\, - Y => d14); - - un6_fe_npc_I_80 : AND2 - port map(A => \fe_pc[14]\, B => \fe_pc[15]\, Y => - \DWACT_FINC_E[8]\); - - \r.f.pc_RNO_0[2]\ : NOR3C - port map(A => \un6_ex_add_res_m[3]\, B => \pc_1_iv_0[2]\, C - => \tmp_m[2]\, Y => \pc_1_iv_2[2]\); - - \r.a.ctrl.rd_RNO[5]\ : NOR2A - port map(A => I_13_0, B => un3_reg, Y => N_35); - - \r.m.y_RNIM65F7[25]\ : NOR3C - port map(A => \y_m_1[25]\, B => \ex_op2_m[25]\, C => - \aluop_RNIQ4RF4[1]\, Y => \aluresult_1_iv_2[25]\); - - \r.m.y_RNO_0[25]\ : NOR3C - port map(A => \y_m_2[26]\, B => \y_m_0[25]\, C => - \y_iv_1[25]\, Y => \y_iv_2[25]\); - - \r.e.ctrl.rett\ : DFN1E0 - port map(D => rett_1, CLK => lclk_c, E => holdn, Q => - rett_3); - - \r.d.inst_0_RNIRAPD[23]\ : AO1C - port map(A => tmp, B => icc_check_3_0_a3_1, C => N_3721, Y - => N_3718); - - \r.x.ctrl.tt[0]\ : DFN1E0 - port map(D => \tt2[0]\, CLK => lclk_c, E => holdn, Q => - \tt[0]\); - - \r.x.data_0_RNI796I1[7]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[7]\, Y => - \ex_op1_i_m[7]\); - - \r.a.ctrl.pc_RNI0GE2C[23]\ : MX2 - port map(A => \pc_3[23]\, B => N_3900, S => ex_bpmiss_1, Y - => \fe_pc[23]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I60_Y : NOR2B - port map(A => N449, B => N446, Y => N519_0); - - \r.x.result[11]\ : DFN1E0 - port map(D => \maddress[11]\, CLK => lclk_c, E => holdn, Q - => \result_0[11]\); - - \r.e.op1[27]\ : DFN1E0 - port map(D => \aop1[27]\, CLK => lclk_c, E => holdn, Q => - \op1[27]\); - - \r.a.ctrl.pc_RNI1GE2C[31]\ : MX2 - port map(A => \pc_0[31]\, B => N_3908, S => ex_bpmiss_1_0, - Y => \fe_pc[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I23_G0N : OA1 - port map(A => \op1[22]\, B => ldbp1_3, C => \data_0_0[22]\, - Y => N463_1); - - \r.e.op1_RNIK8N34[0]\ : NOR3C - port map(A => \rfo_m_i[32]\, B => \d_1_iv_2[0]\, C => - \op1_m_i[0]\, Y => \d_1_iv_4[0]\); - - \r.w.s.y_RNO[9]\ : MX2 - port map(A => \y_2[9]\, B => \result_0[9]\, S => N_481, Y - => N_3773); - - \r.e.ctrl.rd_RNID7P71[6]\ : XNOR2 - port map(A => \rd_0[6]\, B => \un3_de_ren1[97]\, Y => - un2_rs1_1_6_i_0); - - \r.w.s.y[6]\ : DFN1E0 - port map(D => N_3770, CLK => lclk_c, E => N_6922_i, Q => - \y[6]\); - - \r.x.result_RNI47MJ3[29]\ : MX2C - port map(A => \un1_iu0_6[29]\, B => \un1_p0_6[381]\, S => - bpdata6_0_0, Y => \bpdata[29]\); - - \r.e.op2_RNO_0[20]\ : OR3C - port map(A => \op1_m_i[20]\, B => \d_1_iv_3[20]\, C => - \aluresult_m_i[20]\, Y => \d_1[20]\); - - \r.a.rsel2_0[0]\ : DFN1E0 - port map(D => N_3944, CLK => lclk_c, E => holdn, Q => - \rsel2_0[0]\); - - \r.e.aluop_1_RNIHDBS1[1]\ : MX2C - port map(A => N_3530, B => \logicout_3[3]\, S => - \aluop_1[1]\, Y => N_3562); - - \r.x.data_0[22]\ : DFN1E0 - port map(D => \data_0_1[22]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_0[22]\); - - \r.e.aluop_0_RNIFL2Q5[0]\ : MX2C - port map(A => N_3574, B => N_3638, S => \aluop_0[0]\, Y => - \logicout[15]\); - - \r.e.op2_RNI40IN1[29]\ : OR2B - port map(A => \un1_iu0_5[95]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[29]\); - - \r.x.result_RNIKCOE[31]\ : OR2B - port map(A => \un1_p0_6[383]\, B => d14, Y => - \cpi_m_0[383]\); - - \r.a.ctrl.inst[25]\ : DFN1E0 - port map(D => \inst_0[25]\, CLK => lclk_c, E => holdn, Q - => \inst_1[25]\); - - \r.e.op2_RNI0OG11_0[20]\ : OR2 - port map(A => \un1_iu0_6[20]\, B => \un1_iu0_5[86]\, Y => - \logicout_3[20]\); - - \r.e.op1_RNIUI9G[28]\ : OR2B - port map(A => \op1[28]\, B => un14_casaen_s1_0, Y => - \op1_m_0[28]\); - - \r.a.ctrl.inst_RNI3HLO[27]\ : MX2C - port map(A => branch_2, B => branch_6, S => \inst_2[27]\, Y - => N_3342); - - \comb.branch_address.tmp_ADD_30x30_fast_I37_Y\ : OA1A - port map(A => \inst_0_1[26]\, B => \dpc[26]\, C => N434_1, - Y => N454); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_Y_1\ : AOI1B - port map(A => N520, B => N513, C => ADD_30x30_fast_I235_Y_0, - Y => ADD_30x30_fast_I235_Y_1); - - \r.m.y_RNO_3[13]\ : OR3A - port map(A => \y_2[13]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[13]\); - - \r.e.op2_RNINUNP[11]\ : MX2 - port map(A => \op2[11]\, B => N_4258, S => ldbp2_1, Y => - \un1_iu0_5[77]\); - - \r.e.op2_RNO_8[24]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[376]\, - Y => \cpi_m_i[376]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I103_un1_Y : OR3C - port map(A => N473_1, B => N476_1, C => N504_1, Y => - I103_un1_Y_i); - - \r.e.jmpl_RNIDN24Q_0\ : OR2B - port map(A => \shiftin_17[17]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[17]\); - - \r.e.jmpl_RNIMI00K1\ : NOR3C - port map(A => \aluresult_1_iv_6[23]\, B => - \aluop_RNII15D6[0]\, C => \shiftin_17_m[24]\, Y => - \aluresult_1_iv_8[23]\); - - \r.e.aluop[2]\ : DFN1E0 - port map(D => \aluop[2]\, CLK => lclk_c, E => holdn, Q => - \aluop_1[2]\); - - un9_ra_I_13 : XOR2 - port map(A => \cwp[1]\, B => \DWACT_ADD_CI_0_TMP_2[0]\, Y - => I_13_3); - - \r.d.pc[10]\ : DFN1 - port map(D => \pc_RNO[10]\, CLK => lclk_c, Q => \dpc[10]\); - - \r.e.aluop_RNIFR794[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[28]\, Y => - \bpdata_i_m[28]\); - - \r.a.imm_RNO[11]\ : MX2 - port map(A => \inst_0_RNI1JUM[1]\, B => \inst_0[11]\, S => - call_hold5_0, Y => \un3_de_ren1[129]\); - - \r.e.op2_RNO[30]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[30]\, Y => N_314); - - \r.e.op2_RNI2NOP[17]\ : MX2 - port map(A => \op2[17]\, B => N_4264, S => ldbp2_1, Y => - \un1_iu0_5[83]\); - - \r.e.op1_RNI6C23A6[23]\ : NOR3C - port map(A => \op1_m_0[23]\, B => \d_iv_2[23]\, C => - \aluresult_m_0[23]\, Y => \d_i[23]\); - - \r.w.result_RNI50P1[11]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[11]\, Y - => \result_m_0_0[11]\); - - \r.e.ctrl.trap\ : DFN1E0 - port map(D => trap_3, CLK => lclk_c, E => holdn, Q => - trap_0); - - \r.d.cnt_RNI666I[1]\ : AO1D - port map(A => ldcheck1_1_sqmuxa_1, B => un54_casaen, C => - call_hold7_i, Y => ldcheck2_0_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I79_Y\ : OA1 - port map(A => \dpc[5]\, B => \inst_0_RNI3RUM[3]\, C => N371, - Y => N496_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I183_un1_Y : NOR2B - port map(A => N594_0, B => N587_0, Y => I183_un1_Y); - - \r.x.npc_RNIE6KU[0]\ : MX2C - port map(A => N_3215, B => N_3245, S => \npc[0]\, Y => - \xc_result[4]\); - - \r.f.pc[17]\ : DFN1E0 - port map(D => \pc_1[17]\, CLK => lclk_c, E => holdn, Q => - \fpc[17]\); - - \r.a.ctrl.inst_RNI7NUN[31]\ : OA1A - port map(A => \inst[30]\, B => N_219, C => \inst[31]\, Y - => \aop2_i_o2_0[0]\); - - \r.f.pc[31]\ : DFN1E0 - port map(D => \pc_1[31]\, CLK => lclk_c, E => holdn, Q => - \fpc[31]\); - - \r.e.aluop_RNI4J3F4[1]\ : NAND2 - port map(A => aluresult_6_sqmuxa, B => \bpdata[19]\, Y => - \bpdata_m[19]\); - - \r.e.invop2_RNIB98T6\ : MX2C - port map(A => \un6_ex_add_res_s2[6]\, B => - \un6_ex_add_res_s0[6]\, S => invop2, Y => N_6645); - - un6_ex_add_res_d2_ADD_33x33_fast_I197_Y : OR2A - port map(A => I197_un1_Y, B => N600_0, Y => N666_0); - - \r.f.pc_RNO_0[31]\ : NAND2 - port map(A => \tmp[31]\, B => \un2_rstn_5\, Y => - \tmp_m[31]\); - - \r.f.pc_RNO_7[22]\ : MX2 - port map(A => \fpc[22]\, B => \tba[10]\, S => rstate_6314_d, - Y => \xc_trap_address[22]\); - - \r.e.ldbp2_RNIT8TAA2\ : OR2B - port map(A => \aluresult_1_iv_9[5]\, B => - \un6_ex_add_res_m[6]\, Y => \aluresult[5]\); - - \r.m.ctrl.inst_RNIO92L[19]\ : NOR3A - port map(A => \inst_2[22]\, B => \inst_3[19]\, C => - \inst_0[24]\, Y => inst_4_2); - - \r.a.ctrl.rd_RNI6FAVB[6]\ : XA1A - port map(A => \rd[6]\, B => \un3_de_ren1[105]\, C => - un1_de_ren1_NE_5, Y => un1_de_ren1_NE_i_0); - - \r.e.aluop_RNIDO0N[2]\ : XA1 - port map(A => \un1_iu0_5[70]\, B => \aluop_1[2]\, C => - \un1_iu0_6[4]\, Y => N_3531); - - \r.e.op1_RNI1JNF[24]\ : OR2A - port map(A => un17_casaen_0_2, B => \op1[24]\, Y => - \op1_RNI1JNF[24]\); - - \r.a.ctrl.inst_RNIMC2S[19]\ : AXO5 - port map(A => N_232, B => \inst_2[19]\, C => \inst_2[20]\, - Y => N_262); - - \r.e.alusel_RNO[0]\ : NOR3C - port map(A => N_500, B => \alusel_i_0_o5_0[1]\, C => - \alusel_i_0_2[0]\, Y => N_3838_i_0); - - \r.d.pc_RNI2CCA4[8]\ : MX2 - port map(A => \dpc[8]\, B => \fpc[8]\, S => \ra_bpmiss_1_0\, - Y => N_3885); - - \r.w.s.tba_RNINQF44[14]\ : AOI1B - port map(A => \tba[14]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[26]\, Y => \aluresult_1_iv_3[26]\); - - \r.e.shleft_RNIOULD2\ : MX2B - port map(A => \shiftin_5[46]\, B => \shiftin_5[30]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[30]\); - - \r.w.result[21]\ : DFN1E0 - port map(D => \wdata[21]\, CLK => lclk_c, E => holdn, Q => - \result[21]\); - - \r.e.invop2_0_RNIA1FAP1\ : MX2C - port map(A => \un6_ex_add_res_s2[19]\, B => - \un6_ex_add_res_s0[19]\, S => invop2_0, Y => N_6638); - - \r.m.ctrl.pc_RNIV9HF[24]\ : MX2 - port map(A => \pc_2[24]\, B => \pc_3[24]\, S => \npc_0[1]\, - Y => N_3265); - - \r.e.op2_RNO_8[18]\ : OR3B - port map(A => d29_0, B => \imm[18]\, C => \rsel2_1[0]\, Y - => \imm_m_i[18]\); - - \r.x.result_RNI79BV5[3]\ : OR2B - port map(A => \bpdata[3]\, B => N_3957, Y => \bpdata_m[3]\); - - \r.e.aluop_0_RNI34A66[0]\ : OR2B - port map(A => \logicout[26]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[26]\); - - \r.f.pc_RNO_7[14]\ : MX2 - port map(A => \fpc[14]\, B => \tba[2]\, S => rstate_6314_d, - Y => \xc_trap_address[14]\); - - \r.e.jmpl_RNI66TM71\ : AOI1B - port map(A => \shiftin_17[2]\, B => aluresult_1_sqmuxa, C - => \shiftin_17_m_0[1]\, Y => \aluresult_2_iv_7[1]\); - - \r.a.imm[22]\ : DFN1E0 - port map(D => \inst_0[12]\, CLK => lclk_c, E => holdn, Q - => \imm[22]\); - - \r.a.rsel1_0_RNIVK8M2[2]\ : OR2B - port map(A => data1(7), B => d11_0, Y => \rfo_m[7]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I311_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[21]\, B => N786, Y => - \un6_ex_add_res_s2[21]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I82_Y : NOR2B - port map(A => N416_1, B => N413_1, Y => N541_1); - - \r.e.ldbp2_RNIB8SLL4\ : MX2 - port map(A => \un6_ex_add_res_s1[29]\, B => N_6625, S => - ldbp2_3, Y => \eaddress[28]\); - - \r.e.op2_RNO_6[20]\ : OR3B - port map(A => d29_0, B => \imm[20]\, C => \rsel2_1[0]\, Y - => \imm_m_i[20]\); - - \r.e.aluop_1_RNI0PFT2[1]\ : MX2C - port map(A => \logicout_4[23]\, B => N_6880_i, S => - N_6866_i, Y => N_3646); - - \r.a.ctrl.pc_RNIJVD2C[11]\ : MX2 - port map(A => \pc[11]\, B => N_3888, S => ex_bpmiss_1, Y - => \fe_pc[11]\); - - \r.e.shcnt_RNIAR1C[4]\ : MX2C - port map(A => \shcnt[4]\, B => N_3308, S => ldbp2_3, Y => - \ex_shcnt_1_i[4]\); - - \r.e.op2_RNI6ROP[18]\ : MX2 - port map(A => \op2[18]\, B => N_4265, S => ldbp2_2, Y => - \un1_iu0_5[84]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I42_Y : NAND2 - port map(A => N473, B => N476, Y => N501); - - \r.x.data_0_RNO_0[22]\ : AOI1B - port map(A => rdatav_0_1_0_iv_5_4, B => mcdo_m_0_20, C => - rdata_6_sqmuxa, Y => \dco_m_0[118]\); - - \r.m.y_RNO_4[25]\ : OR3A - port map(A => \y_1[25]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[25]\); - - \r.a.rsel1_RNIJAKCP1[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[0]\, Y => - \aluresult_m_0[0]\); - - \r.f.pc_RNIF2C62[7]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[7]\, Y => \xc_trap_address_m[7]\); - - \r.a.ctrl.pc_RNIB0F2C[19]\ : MX2 - port map(A => \pc_3[19]\, B => N_3896, S => ex_bpmiss_1, Y - => \fe_pc[19]\); - - \r.a.ctrl.inst_RNIDG1E_0[21]\ : OR2B - port map(A => \inst_2[21]\, B => \inst_2[19]\, Y => N_241); - - \r.f.pc_RNIEJ56[3]\ : NOR2A - port map(A => \fpc[3]\, B => rstate_6314_d_0, Y => - \xc_trap_address_m_0[3]\); - - \r.e.op1_RNI5S1CE2[5]\ : NOR3C - port map(A => N_407, B => \d_iv_0_2[5]\, C => N_408, Y => - \d_i_0[5]\); - - \r.e.op2_RNO_3[19]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[19]\, Y => - \aluresult_m_i[19]\); - - \r.d.pv_RNI0OB48\ : OR3A - port map(A => un23_exbpmiss_0, B => un52_casaen, C => - ra_bpannul_1, Y => un23_exbpmiss_i_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I308_Y_0_0 : XOR2 - port map(A => \op2[17]\, B => \un1_iu0_6[17]\, Y => - ADD_33x33_fast_I308_Y_0_0); - - \r.e.shleft_RNIEH9D2\ : MX2B - port map(A => \shiftin_5[39]\, B => \shiftin_5[23]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I80_Y\ : AO13 - port map(A => \inst_0_RNI3RUM[3]\, B => \dpc[5]\, C => N364, - Y => N497_1); - - \r.e.op1_RNI7O0M7[0]\ : OR2B - port map(A => \edata2_0_iv_0[0]\, B => \bpdata_i_m[0]\, Y - => edata2_0_iv(0)); - - \r.a.ctrl.pc_RNIVFE2C[15]\ : MX2 - port map(A => \pc[15]\, B => N_3892, S => ex_bpmiss_1, Y - => \fe_pc[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I147_Y : AO1 - port map(A => N548_1, B => N545_1, C => N544_0, Y => N610_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I305_Y_0_1 : XOR2 - port map(A => \data_0[14]\, B => \un1_iu0_6[14]\, Y => - \un6_ex_add_res_s2_1[15]\); - - \r.m.ctrl.ld\ : DFN1E0 - port map(D => ld_5, CLK => lclk_c, E => holdn, Q => ld); - - \r.d.inst_0[26]\ : DFN1 - port map(D => \inst_0_RNO[26]\, CLK => lclk_c, Q => - \inst_0[26]\); - - \r.x.result_RNIT3AB3[6]\ : MX2 - port map(A => \un1_iu0_6[6]\, B => \un1_p0_6[358]\, S => - bpdata6_0_0, Y => \bpdata[6]\); - - \r.d.cnt_RNI703B[1]\ : OR3A - port map(A => ldcheck2_2_sqmuxa_1_1, B => N_89, C => - call_hold7_i, Y => ldcheck2_2_sqmuxa_1_i); - - \r.x.npc_0[1]\ : DFN1E0 - port map(D => \npc_1_0[1]\, CLK => lclk_c, E => holdn, Q - => \npc_0[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I113_Y_0 : MIN3 - port map(A => \data_0[21]\, B => \un1_iu0_6[21]\, C => - N457_0, Y => ADD_33x33_fast_I113_Y_0_0); - - \r.x.ctrl.wreg_RNIHAGI1\ : MX2C - port map(A => N_6350, B => wreg, S => xc_wreg_0_sqmuxa, Y - => xc_wreg_1); - - \r.a.ctrl.inst_RNI0Q593[20]\ : OA1A - port map(A => illegal_inst38, B => N_212, C => - cp_disabled_11_sqmuxa, Y => cp_disabled_4_0_1_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I73_Y : AO13 - port map(A => N424_0, B => \un1_iu0_6[10]\, C => - \data_0[10]\, Y => N532); - - un6_ex_add_res_d0_ADD_33x33_fast_I144_Y : OR2B - port map(A => N545_1, B => N541_0, Y => N607_1); - - \r.m.y_RNIOTN71[20]\ : OR2B - port map(A => \y_0[20]\, B => aluresult_10_sqmuxa_0, Y => - \y_m_1[20]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I262_Y_0_0 : NOR3A - port map(A => N_52, B => N478, C => - ADD_33x33_fast_I39_Y_0_a3, Y => ADD_33x33_fast_I262_Y_0_0); - - \r.e.op2_RNO_0[6]\ : OR3C - port map(A => \op1_m_i[6]\, B => \d_1_iv_3[6]\, C => - \aluresult_m_i[6]\, Y => \d_1[6]\); - - \r.e.op2_RNI2EQ2JA[0]\ : AOI1B - port map(A => \icc_7_m_2[1]\, B => \icc_7[1]\, C => - \icc_2_m[1]\, Y => \icc_12_iv_0[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I25_G0N : NOR2B - port map(A => \un1_iu0_6[24]\, B => \op2[24]\, Y => N469); - - un6_ex_add_res_d1_ADD_33x33_fast_I196_Y : NOR2A - port map(A => N607_0, B => N599_1, Y => N665); - - \r.e.invop2_RNIAAN583\ : MX2C - port map(A => \un6_ex_add_res_s2[31]\, B => - \un6_ex_add_res_s0[31]\, S => invop2, Y => N_6577); - - \r.d.pc_RNIQTGB4[15]\ : MX2 - port map(A => \dpc[15]\, B => \fpc[15]\, S => ra_bpmiss_1, - Y => N_3892); - - \r.a.ctrl.inst_RNIC8Q8[28]\ : XOR2 - port map(A => \inst_1[28]\, B => \icc_0[0]\, Y => branch_6); - - un6_ex_add_res_d0_ADD_33x33_fast_I62_Y : NOR2B - port map(A => N446, B => N443_0, Y => N521); - - \r.a.rsel1_RNI0N5AB3[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[12]\, Y => - \aluresult_m_0[12]\); - - \r.x.data_0_RNO_0[11]\ : NOR2B - port map(A => N_3473, B => data_0_0_11, Y => \dco_m_0[107]\); - - \r.x.ctrl.pc_RNIJ2IF[17]\ : MX2 - port map(A => \pc_2[17]\, B => \pc_0[17]\, S => \npc_1[1]\, - Y => N_3228); - - \r.e.shcnt_RNINQM94[3]\ : MX2 - port map(A => \shiftin_8[17]\, B => \shiftin_8[9]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I286_Y_0_0\ : XOR2 - port map(A => \dpc[28]\, B => \inst_0_1[28]\, Y => - ADD_30x30_fast_I286_Y_0_0); - - \r.f.pc_RNO_2[23]\ : OR2B - port map(A => I_136, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[21]\); - - \r.e.op2_RNIUSAP_0[7]\ : OR2 - port map(A => \un1_iu0_6[7]\, B => \un1_iu0_5[73]\, Y => - \logicout_3[7]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I269_Y_0\ : XOR2 - port map(A => N741, B => ADD_30x30_fast_I269_Y_0_0, Y => - \tmp[11]\); - - \r.e.op2_RNO_6[30]\ : OR2B - port map(A => data2(30), B => d25, Y => \rfo_m_i[62]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I14_G0N\ : NOR2B - port map(A => \inst_0[14]\, B => \dpc[16]\, Y => N400); - - \r.a.jmpl_RNO\ : NOR2 - port map(A => un7_op_3, B => N_150, Y => jmpl_3); - - \r.e.et\ : DFN1E0 - port map(D => et_1, CLK => lclk_c, E => holdn, Q => et_0); - - \r.w.result_RNIMFD4[17]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[17]\, - Y => \result_m_0_0[17]\); - - \r.e.op2_RNO_0[14]\ : OR3C - port map(A => \op1_m_i[14]\, B => \d_1_iv_3[14]\, C => - \aluresult_m_i[14]\, Y => \d_1[14]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I174_Y : NOR2B - port map(A => N585, B => N577, Y => N643_1); - - \r.w.s.et_RNIVNF2\ : OR2B - port map(A => \rstate_0[0]\, B => et, Y => N_6337); - - \r.m.y_RNO_0[31]\ : NOR3C - port map(A => \y_m[31]\, B => \y_m_0[31]\, C => - \y_iv_0[31]\, Y => \y_iv_2[31]\); - - \r.a.ctrl.rd_RNIMP6H1[7]\ : XOR2 - port map(A => \rd[7]\, B => un1_reg, Y => \rd_RNIMP6H1[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I248_un1_Y : OR2B - port map(A => N667, B => N616, Y => I248_un1_Y_i); - - \r.m.result_RNIT3P1[20]\ : OR2B - port map(A => d13, B => \maddress[20]\, Y => - \result_m_0[20]\); - - \r.x.data_0_RNICF9E[16]\ : XOR2 - port map(A => \data_0[16]\, B => invop2_0, Y => N_4263); - - \r.w.s.tt[2]\ : DFN1E0 - port map(D => \xc_vectt_1[2]\, CLK => lclk_c, E => N_6747, - Q => \irl[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I134_Y\ : OR2 - port map(A => N495_1, B => I134_un1_Y, Y => N554); - - un6_ex_add_res_d2_ADD_33x33_fast_I100_Y : NOR3C - port map(A => N473_2, B => N476_2, C => N497, Y => N563_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I268_Y_0_0\ : XOR2 - port map(A => \dpc[10]\, B => \inst_0[8]\, Y => - ADD_30x30_fast_I268_Y_0_0); - - \r.a.ctrl.inst_RNIH5562[21]\ : AOI1 - port map(A => un1_illegal_inst11_2_0_a5_0, B => - illegal_inst11_0_a5_0, C => N_216, Y => - un1_illegal_inst11_0); - - \r.a.ctrl.inst_RNIA01E[22]\ : OR2A - port map(A => \inst[22]\, B => \inst_1[24]\, Y => N_232); - - \r.x.ctrl.inst_RNIP51E[24]\ : NOR2B - port map(A => \inst_2[24]\, B => \inst[23]\, Y => y6_0); - - \r.m.y_RNIA0LA2[8]\ : AOI1B - port map(A => \y[8]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[153]\, Y => \aluresult_1_iv_1[8]\); - - \r.d.pv_RNO_1\ : OA1A - port map(A => un6_rabpmiss_2, B => \de_hold_pc_1\, C => - N_4240, Y => pv_3); - - \r.x.result_RNIDQD25[6]\ : NOR2 - port map(A => \bpdata[6]\, B => N_3703_i, Y => - \bpdata_i_m_1[6]\); - - \r.d.pc_RNI04CA4[7]\ : MX2 - port map(A => \dpc[7]\, B => \fpc[7]\, S => ra_bpmiss_1, Y - => N_3884); - - \r.e.op2_RNO_3[16]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[16]\, Y => - \aluresult_m_i[16]\); - - \r.e.aluop_0_RNIPL6R[2]\ : XA1 - port map(A => \un1_iu0_5[73]\, B => \aluop_0[2]\, C => - \un1_iu0_6[7]\, Y => N_3534); - - \r.a.ctrl.pc[16]\ : DFN1E0 - port map(D => \dpc[16]\, CLK => lclk_c, E => holdn, Q => - \pc_0[16]\); - - \r.m.icc_RNIJ2R41[1]\ : OR3B - port map(A => trap_0_sqmuxa_2_0, B => trap_0_sqmuxa_2_1, C - => trap_0_sqmuxa_2_2, Y => trap_0_sqmuxa_2); - - \r.e.ctrl.pc[12]\ : DFN1E0 - port map(D => \pc[12]\, CLK => lclk_c, E => holdn, Q => - \pc_2[12]\); - - \r.d.cwp_RNISTPR[1]\ : MX2 - port map(A => \cwp[1]\, B => \ncwp_3[1]\, S => un8_op, Y - => \ncwp[1]\); - - \r.a.rsel2[0]\ : DFN1E0 - port map(D => N_3944, CLK => lclk_c, E => holdn, Q => - \rsel2[0]\); - - \r.m.y_RNIO6C97[24]\ : NOR2B - port map(A => \aluresult_1_iv_0[24]\, B => - \aluop_RNIN0RF4[1]\, Y => \aluresult_1_iv_2[24]\); - - \r.x.npc_RNIERDL[0]\ : MX2C - port map(A => N_3236, B => N_3266, S => \npc[0]\, Y => - \xc_result[25]\); - - \r.m.result[0]\ : DFN1E0 - port map(D => \eres2[0]\, CLK => lclk_c, E => holdn, Q => - \maddress[0]\); - - \r.e.op2_RNI40NB1[15]\ : OR2A - port map(A => \un1_iu0_5[81]\, B => \un1_iu0_6[15]\, Y => - \logicout_4[15]\); - - \r.e.jmpl_RNIDNUP91\ : AOI1B - port map(A => \shiftin_17[8]\, B => aluresult_1_sqmuxa_0, C - => \aluresult_1_iv_7[7]\, Y => \aluresult_1_iv_8[7]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I71_Y_0 : AO1 - port map(A => N431_1, B => N427_1, C => N430, Y => N530); - - un23_ra_I_15 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP_1[0]\, B => \cwp[1]\, Y - => \DWACT_ADD_CI_0_g_array_1_1[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I168_un1_Y\ : OR3C - port map(A => N476_0, B => N480, C => N542, Y => - I168_un1_Y_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I274_Y_0_a3 : NOR2B - port map(A => N796_1, B => N443_0, Y => - ADD_33x33_fast_I274_Y_0_a3_0); - - \r.x.result_RNIBED25[5]\ : NOR2 - port map(A => \bpdata[5]\, B => N_3703_i, Y => - \bpdata_i_m_1[5]\); - - \r.a.ctrl.inst_RNIIK1S[13]\ : OA1B - port map(A => \inst[13]\, B => \inst_1[25]\, C => N_212, Y - => illegal_inst_4_m_0); - - \r.d.cnt_RNIFET3[0]\ : OR2A - port map(A => \cnt_2[0]\, B => \cnt_0[1]\, Y => un52_casaen); - - \r.w.s.tba_RNIN17A1[15]\ : OR2B - port map(A => \tba[15]\, B => aluresult_12_sqmuxa, Y => - \tba_m[15]\); - - \r.e.ctrl.inst_RNIOS1E[24]\ : NOR2A - port map(A => \inst[24]\, B => \inst[19]\, Y => - \icc_7_m_0[1]\); - - \r.w.s.y_RNO_0[24]\ : NOR2A - port map(A => N_481, B => \result_0[24]\, Y => N_368); - - \r.w.s.tba[16]\ : DFN1E1 - port map(D => \result_0[28]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[16]\); - - \r.e.ctrl.inst[29]\ : DFN1E0 - port map(D => \inst[29]\, CLK => lclk_c, E => holdn, Q => - \inst_2[29]\); - - \r.a.ctrl.pc_RNIGGL0C[5]\ : MX2 - port map(A => \pc_0[5]\, B => N_3882, S => ex_bpmiss_1, Y - => \fe_pc[5]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I108_Y\ : OR3C - port map(A => I52_un1_Y, B => N409_2, C => I108_un1_Y, Y - => N528); - - un6_ex_add_res_d1_ADD_33x33_fast_I23_P0N : OR2 - port map(A => \op2[22]\, B => \un1_iu0_6[22]\, Y => N464_0); - - \r.e.op1_RNISA9G[26]\ : OR2B - port map(A => \op1[26]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[26]\); - - \r.e.jmpl_RNICCUBQ1\ : NOR3C - port map(A => \aluresult_1_iv_6[29]\, B => - \logicout_m_0[29]\, C => \shiftin_17_m[30]\, Y => - \aluresult_1_iv_8[29]\); - - \r.m.ctrl.pc[3]\ : DFN1E0 - port map(D => \pc_0[3]\, CLK => lclk_c, E => holdn, Q => - \pc_3[3]\); - - \r.w.s.tba_RNI14CA1[0]\ : OR2B - port map(A => \tba[0]\, B => aluresult_12_sqmuxa, Y => - \tba_m[0]\); - - \r.e.op1_RNO[23]\ : MX2C - port map(A => \d_i[23]\, B => \d_i[24]\, S => N_227, Y => - \aop1[23]\); - - \r.d.inst_0_RNI3AJ4[23]\ : OR3A - port map(A => \inst_0_0[23]\, B => \inst_0[20]\, C => - \inst_0[30]\, Y => N_3738); - - un6_ex_add_res_d2_ADD_33x33_fast_I298_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[7]\, B => \data_0_2[7]\, Y => - \un6_ex_add_res_s2_1[8]\); - - \r.w.s.tba_RNIDE5KG[11]\ : NOR3C - port map(A => \aluresult_1_iv_4[23]\, B => - \aluresult_1_iv_3[23]\, C => \bpdata_m_1[7]\, Y => - \aluresult_1_iv_6[23]\); - - \r.x.data_0_RNO_2[8]\ : AND2 - port map(A => \dco_m_0_i[120]\, B => \data_0_m_i[8]\, Y => - \data_0_1_0_iv_0[8]\); - - \r.m.result_RNO[5]\ : MX2 - port map(A => \aluresult[5]\, B => \op1[5]\, S => - un17_casaen_0_2, Y => \eres2[5]\); - - \r.e.aluop_RNIH8S04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[7]\, Y => - \bpdata_i_m_2[7]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I19_G0N\ : NOR2B - port map(A => \inst_0[19]\, B => \dpc[21]\, Y => N415); - - \comb.branch_address.tmp_ADD_30x30_fast_I122_Y\ : AO1 - port map(A => N487_1, B => N484_1, C => N483, Y => N542); - - un6_ex_add_res_d1_ADD_33x33_fast_I1_G0N : NOR2B - port map(A => \un1_iu0_6[0]\, B => \op2[0]\, Y => N397_0); - - \r.e.aluop_0_RNIQ8ID1[2]\ : XA1 - port map(A => \un1_iu0_5[88]\, B => \aluop_0[2]\, C => - \un1_iu0_6[22]\, Y => N_3549); - - \r.x.result_RNI3TAN3[27]\ : MX2C - port map(A => \un1_iu0_6[27]\, B => \un1_p0_6[379]\, S => - bpdata6, Y => \bpdata[27]\); - - \r.e.jmpl_RNIJRHU44\ : OR3C - port map(A => \aluresult_1_iv_7[16]\, B => - \shiftin_17_m_0[16]\, C => \un6_ex_add_res_m[17]\, Y => - \aluresult[16]\); - - \r.m.y_RNO[20]\ : OR3C - port map(A => \y_iv_1[20]\, B => \y_iv_0[20]\, C => - \logicout_m[20]\, Y => \y_1[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I59_Y\ : OA1 - port map(A => \dpc[16]\, B => \inst_0[14]\, C => N398_2, Y - => N476_0); - - \r.d.inst_0_RNIAAJ4[29]\ : MX2C - port map(A => \inst_0_0[21]\, B => \inst_0[29]\, S => - \inst_0[30]\, Y => \inst_0_1[31]\); - - \r.e.jmpl_RNIH6LEL1\ : NOR3C - port map(A => \aluresult_1_iv_6[24]\, B => - \aluresult_1_iv_5[24]\, C => \shiftin_17_m[25]\, Y => - \aluresult_1_iv_8[24]\); - - un37_ra_I_13 : XOR2 - port map(A => \cwp[1]\, B => \DWACT_ADD_CI_0_TMP_0[0]\, Y - => I_13_1); - - \r.e.ldbp2_2_RNI57ED02\ : OR2B - port map(A => \aluresult_1_iv_7[3]\, B => ldbp2_2_RNI7G0C6, - Y => \aluresult[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I129_un1_Y : NOR3C - port map(A => N434, B => N437, C => N530_2, Y => I129_un1_Y); - - \r.x.ctrl.pc_RNID3431[4]\ : MX2C - port map(A => \un1_p0_6[356]\, B => \pc_2[4]\, S => - s_3_sqmuxa, Y => N_3395); - - \r.m.y_RNO_3[14]\ : OR3A - port map(A => \y_2[14]\, B => wy_3, C => wy_1_0_1, Y => - N_387); - - \r.a.imm_RNI1645[0]\ : OR3B - port map(A => d29_0_0, B => \imm[0]\, C => \rsel2_0[0]\, Y - => \imm_m_i[0]\); - - \r.e.shcnt_RNIEJ7HD[2]\ : MX2C - port map(A => \shiftin_11[27]\, B => \shiftin_11[23]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[23]\); - - \r.a.ctrl.inst_RNIS0331[30]\ : AO1A - port map(A => N_209, B => N_472, C => \inst[30]\, Y => - N_451); - - \r.e.ctrl.rd_RNIRMGKE[0]\ : AOI1B - port map(A => wreg_1_6_0, B => wreg_1_5, C => wreg_2_1, Y - => rfe_1_1); - - \r.e.ctrl.rd_RNIHC1L[2]\ : XNOR2 - port map(A => \rd_1[2]\, B => \un3_de_ren1[93]\, Y => - un2_rs1_1_2_i_0); - - \r.e.aluop_0_RNIVQ1T2[1]\ : MX2C - port map(A => \logicout_4[16]\, B => N_6886, S => - N_6866_i_0, Y => N_3639); - - \r.d.pc_RNO[23]\ : MX2 - port map(A => \fpc[23]\, B => \dpc[23]\, S => N_6763_i, Y - => \pc_RNO[23]\); - - \r.w.s.icc_RNO_0[3]\ : AOI1B - port map(A => icc_2_sqmuxa, B => \result[23]\, C => - \icc_m_0[3]\, Y => \icc_1_iv_0[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I271_un1_Y : OR2B - port map(A => ADD_33x33_fast_I271_un1_Y_0, B => N649_1, Y - => I271_un1_Y_i); - - un2_rstn_5_0_0_RNITV7K4 : NAND2 - port map(A => \tmp[5]\, B => un2_rstn_5_0, Y => \tmp_m[5]\); - - \r.d.inst_0_RNIM3TA[29]\ : OR2B - port map(A => I_14_2, B => N_3525_3, Y => \de_raddr1_1[6]\); - - \r.m.ctrl.wy_RNI8E1D\ : NOR2A - port map(A => wy_1, B => wy_3, Y => y08); - - \r.d.inst_0_RNO[29]\ : NOR2B - port map(A => rst, B => N_4629, Y => \inst_0_RNO[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I116_Y\ : AO1B - port map(A => N481_2, B => N478_0, C => - ADD_30x30_fast_I116_Y_0, Y => N536); - - \r.e.op2_RNIR6OP[13]\ : MX2 - port map(A => \op2[13]\, B => N_4260, S => ldbp2_1, Y => - \un1_iu0_5[79]\); - - \r.e.ldbp2_RNIS1OF04\ : OR2A - port map(A => \eaddress[24]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[25]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I10_G0N : NOR2B - port map(A => \un1_iu0_6[9]\, B => \op2[9]\, Y => N424_2); - - \r.e.op2_RNO_7[23]\ : NOR2B - port map(A => \result_m_i_0[23]\, B => \cpi_m_i[375]\, Y - => \d_1_iv_1[23]\); - - \r.e.shleft_1_RNI5THM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[13]\, S => - shleft_1, Y => \shiftin_5[44]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I247_Y : OR2 - port map(A => N664, B => I247_un1_Y, Y => N808); - - \r.e.op1_RNI8TPD1[9]\ : NOR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[9]\, Y => - \ex_op1_i_m[9]\); - - \r.m.result_RNIFFJ83[15]\ : NOR3C - port map(A => \d_iv_0[15]\, B => \result_m_0[15]\, C => - \rfo_m[15]\, Y => \d_iv_2[15]\); - - \r.m.y_RNO_0[10]\ : AOI1B - port map(A => wy_1_0, B => \y[10]\, C => \y_m_0[10]\, Y => - \y_iv_1[10]\); - - \r.x.ctrl.rd_RNI5SGO[1]\ : AO1A - port map(A => N_6352, B => \rd_1[1]\, C => \rstate[0]\, Y - => waddr(1)); - - \r.e.op2_RNIP7HN1[14]\ : OR2B - port map(A => \un1_iu0_5[80]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[14]\); - - wovf_exc_0_sqmuxa_RNO_1 : MX2C - port map(A => N_3725, B => N_3726, S => \ncwp_3[1]\, Y => - N_3727); - - \r.e.aluop_0_RNIIRTVP[0]\ : AOI1B - port map(A => \logicout[28]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[28]\, Y => \aluresult_1_iv_7[28]\); - - \r.a.ctrl.pc_RNI5OE2C[17]\ : MX2 - port map(A => \pc[17]\, B => N_3894, S => ex_bpmiss_1_0, Y - => \fe_pc[17]\); - - \r.w.result[18]\ : DFN1E0 - port map(D => \wdata[18]\, CLK => lclk_c, E => holdn, Q => - \result[18]\); - - \r.e.shcnt_RNIFFO7E[2]\ : MX2C - port map(A => \shiftin_11[32]\, B => \shiftin_11[28]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[28]\); - - \r.e.op1_RNIOU8G[13]\ : OR2B - port map(A => \op1[13]\, B => un14_casaen_s1_0, Y => - \op1_m_0[13]\); - - \r.e.shleft_1_RNIQNBN2\ : MX2B - port map(A => \shiftin_5[36]\, B => \shiftin_5[20]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[20]\); - - \r.m.ctrl.pc[22]\ : DFN1E0 - port map(D => \pc_2[22]\, CLK => lclk_c, E => holdn, Q => - \pc_3[22]\); - - \r.e.ctrl.inst[21]\ : DFN1E0 - port map(D => \inst_2[21]\, CLK => lclk_c, E => holdn, Q - => \inst_1[21]\); - - \r.d.pv_RNO_0\ : NOR3C - port map(A => N_4241_i_0, B => pv_0, C => N_4242, Y => pv_2); - - \r.e.ctrl.inst_RNI2P1S[22]\ : NOR3A - port map(A => aluresult_12_sqmuxa_4, B => \inst_1[22]\, C - => \inst_0[23]\, Y => un1_icc_2_sqmuxa_1); - - \r.e.op1_RNIFU3U1[4]\ : OA1A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[4]\, C => - \op1_i_m[4]\, Y => \edata2_0_iv_0[4]\); - - \r.e.ldbp2_1_RNICD8GS2\ : MX2C - port map(A => \un6_ex_add_res_s1_i[19]\, B => N_6638, S => - ldbp2_1, Y => \eaddress[18]\); - - \r.m.ctrl.tt[1]\ : DFN1E0 - port map(D => \tt_3[1]\, CLK => lclk_c, E => holdn, Q => - \tt_2[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I157_un1_Y : NAND2 - port map(A => N561_i, B => N568, Y => I157_un1_Y_i); - - \r.m.y[31]\ : DFN1E0 - port map(D => \y_0[31]\, CLK => lclk_c, E => holdn, Q => - \y[31]\); - - \r.x.npc_RNI65VI[0]\ : MX2C - port map(A => N_3216, B => N_3246, S => \npc[0]\, Y => - \xc_result[5]\); - - \r.e.aluop_RNIN0RF4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[24]\, Y => - \aluop_RNIN0RF4[1]\); - - \r.w.result[10]\ : DFN1E0 - port map(D => \wdata[10]\, CLK => lclk_c, E => holdn, Q => - \result_0[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I195_Y : AO1A - port map(A => N599_1, B => N606_1, C => N598_1, Y => N664_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I319_Y_0_0 : XOR2 - port map(A => \op2[28]\, B => \un1_iu0_6[28]\, Y => - ADD_33x33_fast_I319_Y_0_0); - - \r.e.jmpl_RNI5K9661\ : AOI1B - port map(A => \shiftin_17[5]\, B => aluresult_1_sqmuxa_0, C - => \aluresult_1_iv_6[4]\, Y => \aluresult_1_iv_7[4]\); - - \r.e.op2_RNO_3[7]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[7]\, Y - => \aluresult_m_i[7]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_10\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I107_un1_Y : OR2B - port map(A => N508_1, B => N505_1, Y => I107_un1_Y_i); - - \r.e.op2_RNO_1[31]\ : OR2B - port map(A => \op1[31]\, B => un14_casaen_s1, Y => - \op1_m_i[31]\); - - \r.e.jmpl_RNIN2MUS_0\ : OR2B - port map(A => \shiftin_17[24]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[24]\); - - \r.d.inst_0_RNIOSIB[21]\ : OR3B - port map(A => un4_op3, B => un54_casaen, C => call_hold7_i, - Y => hold_pc_0_sqmuxa_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I109_Y\ : NOR3C - port map(A => N407_0, B => N410, C => - ADD_30x30_fast_I109_Y_0, Y => N529); - - un6_fe_npc_I_69 : AND3 - port map(A => \fe_pc[11]\, B => \fe_pc[12]\, C => - \fe_pc[13]\, Y => \DWACT_FINC_E[7]\); - - \r.x.ctrl.pc_RNI4AGF[10]\ : MX2 - port map(A => \pc[10]\, B => \pc_0[10]\, S => \npc_0[1]\, Y - => N_3221); - - \r.e.op2_RNO_7[10]\ : OA1A - port map(A => \maddress[10]\, B => d27, C => \cpi_m_i[362]\, - Y => \d_1_iv_1[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I301_Y_0 : XNOR3 - port map(A => \un1_iu0_6[10]\, B => \op2[10]\, C => N811_1, - Y => \un6_ex_add_res_s1_i[11]\); - - \r.x.result_RNIGR0QJ[2]\ : AOI1B - port map(A => \bpdata[2]\, B => N_3957, C => - \aluresult_2_iv_5[2]\, Y => \aluresult_2_iv_6[2]\); - - \r.m.y_RNO_1[22]\ : AOI1B - port map(A => \y[22]\, B => y08_0, C => \y_m[23]\, Y => - \y_iv_0[22]\); - - \r.m.ctrl.pc[16]\ : DFN1E0 - port map(D => \pc[16]\, CLK => lclk_c, E => holdn, Q => - \pc_3[16]\); - - \r.d.inst_0_0_0_RNI7IM7[21]\ : OR2A - port map(A => \un1_p0_6_0[60]\, B => \inst_0_0[22]\, Y => - un4_op_0); - - \r.d.annul_RNIN67I\ : NOR3C - port map(A => un19_inst, B => annul_next_1_sqmuxa_1_4, C - => hold_pc_1_sqmuxa, Y => annul_next_1_sqmuxa_1_6); - - \comb.branch_address.tmp_ADD_30x30_fast_I127_Y\ : OR2B - port map(A => N492, B => N488_1, Y => N547); - - \r.a.rfe1_RNI917BR\ : MX2 - port map(A => rfe_1, B => \rfe1\, S => holdn, Y => ren1); - - \r.x.data_0_RNO_0[25]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_25, Y => - \dco_m_1[121]\); - - \r.e.aluop_RNIVELC2[1]\ : OR2A - port map(A => N_3703_i, B => edata_2_sqmuxa, Y => N_3687); - - un6_ex_add_res_d2_ADD_33x33_fast_I197_un1_Y : OR3C - port map(A => N535_1, B => ADD_33x33_fast_I138_Y_0_0, C => - N608_0, Y => I197_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I305_Y_0 : XNOR3 - port map(A => \un1_iu0_6[14]\, B => \op2[14]\, C => N799_0, - Y => \un6_ex_add_res_s1_i[15]\); - - \r.d.inst_0_RNIF88C[21]\ : OR3C - port map(A => un8_op3, B => N_89, C => un12_op3, Y => - un13_op3); - - \r.x.data_0_RNI3FS8[2]\ : XOR2 - port map(A => \data_0[2]\, B => invop2_0, Y => N_3306); - - \r.w.s.y_RNO_0[27]\ : NOR2A - port map(A => N_481, B => \result_0[27]\, Y => N_410); - - \r.m.casa_RNI8BU9_0\ : NOR2A - port map(A => casa, B => N_3355_1, Y => un17_casaen_0); - - \r.e.op1_RNI0JNF[14]\ : NOR2A - port map(A => un17_casaen_0_2, B => \op1[14]\, Y => - \op1_i_m[14]\); - - \r.m.y_RNO[25]\ : AO1C - port map(A => y14_0, B => \logicout[25]\, C => \y_iv_2[25]\, - Y => \y_0[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I43_Y : MAJ3 - port map(A => \data_0[25]\, B => \un1_iu0_6[25]\, C => - N469_0, Y => N502_1); - - \r.f.pc_RNO_0[29]\ : NAND2 - port map(A => \tmp[29]\, B => un2_rstn_5_0, Y => - \tmp_m[29]\); - - \r.x.result[22]\ : DFN1E0 - port map(D => \maddress[22]\, CLK => lclk_c, E => holdn, Q - => \result_0[22]\); - - \r.e.op2_RNO_2[7]\ : NOR3C - port map(A => \d_1_iv_1[7]\, B => \d_1_iv_0[7]\, C => - \rfo_m_i[39]\, Y => \d_1_iv_3[7]\); - - \r.e.op1_RNID1VH[19]\ : MX2 - port map(A => \op1[19]\, B => \data_0[19]\, S => ldbp1_2, Y - => \op1_RNID1VH[19]\); - - \r.e.aluop_RNI2JHJ1[2]\ : XA1 - port map(A => \un1_iu0_5[76]\, B => \aluop_1[2]\, C => - \un1_iu0_6[10]\, Y => N_3537); - - \r.d.inull_RNIPRHA_0\ : NOR3B - port map(A => un19_inst, B => annul_next_2_sqmuxa_1_0, C - => call_hold5_0, Y => annul_next_2_sqmuxa_1_2); - - un6_fe_npc_I_104 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \DWACT_FINC_E[11]\, Y => N_78); - - \r.m.dci.write_RNO_1\ : NOR2A - port map(A => \inst_1[21]\, B => \inst_1[22]\, Y => - write_3_0_a3_0_2_0); - - \r.w.s.tt_RNIF7EJ3[1]\ : AOI1B - port map(A => aluresult_12_sqmuxa_0_0, B => \irl[1]\, C => - \aluresult_1_iv_2[5]\, Y => \aluresult_1_iv_4[5]\); - - \r.a.ctrl.inst_RNIB8549[30]\ : NOR3C - port map(A => N_451, B => \aop2_i_o2_2[0]\, C => N_452, Y - => N_6697_i_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I28_P0N : OR3A - port map(A => \data_0[27]\, B => \op1[27]\, C => ldbp1_0, Y - => N479_1); - - \r.e.op2_RNO_5[28]\ : AOI1B - port map(A => \result[28]\, B => d31_0, C => \imm_m_i[28]\, - Y => \d_1_iv_0[28]\); - - \r.e.op2_RNIBDIG[7]\ : MX2 - port map(A => \op2[7]\, B => N_4254, S => ldbp2_0, Y => - \un1_iu0_5[73]\); - - \r.a.ctrl.cnt_RNI7NUN[0]\ : OR2A - port map(A => N_219, B => N_212, Y => N_456); - - \r.a.ctrl.wreg_RNIGHAIA\ : AOI1 - port map(A => wreg_6, B => un2_rs1_NE_i_0, C => rs1, Y => - rfe_1_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I239_un1_Y\ : NOR3C - port map(A => N581, B => N597, C => N612, Y => I239_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I165_un1_Y : NOR2 - port map(A => N569, B => N576, Y => I165_un1_Y); - - \r.e.op2_RNO_0[11]\ : OR3C - port map(A => \op1_m_i[11]\, B => \d_1_iv_3[11]\, C => - \aluresult_m_i[11]\, Y => \d_1[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I4_G0N\ : NOR2B - port map(A => \inst_0_RNI4VUM[4]\, B => \dpc[6]\, Y => N370); - - \r.e.ctrl.rd_RNI5CCC2[5]\ : XNOR2 - port map(A => \un3_de_ren1[104]\, B => \rd[5]\, Y => - un1_de_ren1_5_i_0); - - \r.m.wcwp_RNO\ : NOR2 - port map(A => annul, B => un3_op_i, Y => wcwp_0); - - \r.a.ctrl.inst_RNII02L_0[24]\ : OR2 - port map(A => \inst_1[24]\, B => N_207, Y => N_433); - - \r.f.pc_RNO_7[12]\ : MX2 - port map(A => \fpc[12]\, B => \tba[0]\, S => - rstate_6314_d_0, Y => \xc_trap_address[12]\); - - \r.e.op1[10]\ : DFN1E0 - port map(D => \aop1[10]\, CLK => lclk_c, E => holdn, Q => - \op1[10]\); - - \r.m.y_RNO_4[13]\ : OR2B - port map(A => \y_0[14]\, B => mulstep_0, Y => \y_m[14]\); - - \r.e.aluop_RNIMPHR1[1]\ : OR2 - port map(A => aluresult_5_sqmuxa, B => aluresult_4_sqmuxa, - Y => N_3957_1); - - un6_fe_npc_I_66 : XOR2 - port map(A => N_106, B => \fe_pc[13]\, Y => I_66); - - \r.e.ldbp2_RNIV9NBU2\ : MX2C - port map(A => \un6_ex_add_res_s1_i[20]\, B => N_6654, S => - ldbp2_3, Y => \eaddress[19]\); - - \r.d.inst_0_RNI0QP8[29]\ : OR2B - port map(A => I_13_3, B => N_3525_3, Y => \de_raddr1_1[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I128_Y : NOR2A - port map(A => N529_2, B => N525_0, Y => N591_1); - - \r.e.shleft_1_RNIDVBG\ : NOR2A - port map(A => \un1_iu0_6[8]\, B => shleft_1, Y => - shleft_1_RNIDVBG); - - \r.d.inst_0_RNIQE58[27]\ : MX2C - port map(A => branch_2_i, B => branch_6_i, S => - \inst_0[27]\, Y => N_3349); - - \r.d.pc_RNI46HB4[27]\ : MX2 - port map(A => \dpc[27]\, B => \fpc[27]\, S => ra_bpmiss_1, - Y => N_3904); - - \r.e.shleft_RNIEIRJ\ : OR2A - port map(A => \un1_iu0_6[24]\, B => shleft, Y => - \shiftin_5[24]\); - - \r.d.inst_0_RNIDEJ4[29]\ : NOR2B - port map(A => \inst_0[29]\, B => N_85, Y => N_79); - - \r.a.rsel1_RNIHM4G85[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[18]\, Y => - \aluresult_m_0[18]\); - - \r.f.pc_RNIO5OJ62[9]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[9]\, C => - \pc_m[9]\, Y => \npc_iv_1[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I154_un1_Y\ : NOR3C - port map(A => N462, B => N_14, C => N528, Y => I154_un1_Y); - - \r.e.aluop_0_RNIG5791[1]\ : XOR3 - port map(A => \un1_iu0_6[28]\, B => \aluop_0[1]\, C => - \un1_iu0_5[94]\, Y => N_6874); - - \r.e.shleft_RNIEQEC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[12]\, S => - shleft, Y => \shiftin_5[43]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I272_Y_0_0\ : XOR2 - port map(A => \dpc[14]\, B => \un1_p0_6_0[51]\, Y => - ADD_30x30_fast_I272_Y_0_0); - - un6_fe_npc_I_83 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[8]\, Y => N_93); - - \r.d.inull_RNO_3\ : NOR2A - port map(A => jmpl, B => annul, Y => jmpl_1); - - un6_fe_npc_I_195 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[23]\, Y => N_14_0); - - \r.m.werr_RNO\ : NOR3B - port map(A => rst, B => trap_0_sqmuxa_7, C => werr_1, Y => - werr_RNO); - - \r.e.aluop_0_RNI5D6R[1]\ : MX2C - port map(A => \logicout_4[9]\, B => N_6841, S => N_6866_i_0, - Y => N_3632); - - \r.d.pc_RNI86HB4[29]\ : MX2 - port map(A => \dpc[29]\, B => \fpc[29]\, S => ra_bpmiss_1, - Y => N_3906); - - \comb.branch_address.tmp_ADD_30x30_fast_I232_un1_Y\ : OR3C - port map(A => N567_1, B => N583, C => N729, Y => I232_un1_Y); - - \r.x.ctrl.pc[9]\ : DFN1E0 - port map(D => \pc_3[9]\, CLK => lclk_c, E => holdn, Q => - \pc_2[9]\); - - \r.w.s.y[5]\ : DFN1E0 - port map(D => N_3769, CLK => lclk_c, E => N_6922_i, Q => - \y[5]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I28_G0N : NOR2A - port map(A => \un1_iu0_6[27]\, B => \data_0[27]\, Y => - N478_1); - - \r.m.icc_RNITN961[1]\ : OR2A - port map(A => \icc[1]\, B => aluresult_11_sqmuxa, Y => - \icc_m[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I63_Y_0_a3 : NOR3C - port map(A => \op2[14]\, B => \un1_iu0_6[14]\, C => N443, Y - => N_53); - - un6_ex_add_res_d0_ADD_33x33_fast_I22_G0N : NOR3A - port map(A => \op1[21]\, B => ldbp1_2, C => \data_0[21]\, Y - => N460_1); - - \r.x.result_RNIVKAN3[18]\ : MX2 - port map(A => \un1_iu0_6[18]\, B => \un1_p0_6[370]\, S => - bpdata6, Y => \bpdata[18]\); - - \r.x.ctrl.pc[17]\ : DFN1E0 - port map(D => \pc_3[17]\, CLK => lclk_c, E => holdn, Q => - \pc_2[17]\); - - \r.w.result[16]\ : DFN1E0 - port map(D => \wdata[16]\, CLK => lclk_c, E => holdn, Q => - \result[16]\); - - \r.a.ctrl.pc[15]\ : DFN1E0 - port map(D => \dpc[15]\, CLK => lclk_c, E => holdn, Q => - \pc[15]\); - - \r.w.result_RNIO7QL[25]\ : AOI1B - port map(A => \un1_p0_6[377]\, B => d14_0, C => - \result_m_0_0[25]\, Y => \d_iv_0[25]\); - - \r.f.pc_RNO_3[17]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[17]\, C => - \xc_trap_address_m[17]\, Y => \pc_1_iv_0[17]\); - - \r.a.ctrl.inst_RNIJ02S[21]\ : OR3A - port map(A => N_256_i_0, B => \inst_2[20]\, C => - \inst_2[21]\, Y => illegal_inst11_0_a5_0); - - \r.e.op2_RNO_4[12]\ : NOR3C - port map(A => \result_m_i[12]\, B => \imm_m_i[12]\, C => - \d_1_iv_1[12]\, Y => \d_1_iv_2[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I87_Y\ : NOR3A - port map(A => N452, B => N440_2, C => N443_2, Y => N507); - - \r.w.s.y_RNO[17]\ : MX2 - port map(A => \y_2[17]\, B => \result_0[17]\, S => N_481_0, - Y => N_3781); - - \r.e.op1_RNIC8HP7[13]\ : OR3 - port map(A => \ex_op1_i_m[13]\, B => \op1_i_m[13]\, C => - \bpdata_i_m[13]\, Y => \edata2_0_iv_1[13]\); - - \r.d.pc[9]\ : DFN1 - port map(D => \pc_RNO[9]\, CLK => lclk_c, Q => \dpc[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I112_Y : NOR3C - port map(A => N461, B => N464_2, C => N513_0, Y => N575_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I155_un1_Y : OR3B - port map(A => N493_0, B => N566_0, C => N497_2, Y => - I155_un1_Y_1); - - \r.w.s.tba_RNI94CA1[8]\ : OR2B - port map(A => \tba[8]\, B => aluresult_12_sqmuxa_0_0, Y => - \tba_m[8]\); - - \r.d.inst_0_RNIMO2O8[23]\ : OR2B - port map(A => un2_rs1_NE_i_0, B => ldcheck1, Y => - un1_ldcheck1); - - \r.w.s.tt_RNIIBEJ3[2]\ : AOI1B - port map(A => aluresult_12_sqmuxa_0_0, B => \irl[2]\, C => - \aluresult_1_iv_2[6]\, Y => \aluresult_1_iv_4[6]\); - - \r.m.icc_RNO_17[2]\ : NOR2A - port map(A => \logicout[23]\, B => \logicout[31]\, Y => - icc_0_sqmuxa_1_16); - - \r.e.aluop_0_RNILHN3[1]\ : OR2A - port map(A => \aluop_0[2]\, B => \aluop_0[1]\, Y => - N_6866_i_0); - - \r.e.ldbp2_RNI1LI304\ : MX2C - port map(A => \un6_ex_add_res_s1_i[25]\, B => N_6571, S => - ldbp2_3, Y => \eaddress[24]\); - - \r.e.ctrl.pc_RNI6PFM7[9]\ : NOR3C - port map(A => \tt_m[5]\, B => \aluresult_1_iv_1[9]\, C => - \bpdata_m_2[1]\, Y => \aluresult_1_iv_5[9]\); - - \r.e.aluop_RNI5O511[2]\ : XA1 - port map(A => \un1_iu0_5[69]\, B => \aluop_1[2]\, C => - \un1_iu0_6[3]\, Y => N_3530); - - \r.a.ctrl.inst_RNIMGCC[28]\ : AX1A - port map(A => \icc_0[2]\, B => N_211, C => \inst_1[28]\, Y - => branch_3); - - \r.x.result_RNII6E25[7]\ : NOR2 - port map(A => \bpdata[7]\, B => N_3703_i, Y => - \bpdata_i_m_1[7]\); - - \r.e.aluop_0_RNIOO306[0]\ : MX2C - port map(A => N_3575, B => N_3639, S => \aluop_0[0]\, Y => - \logicout[16]\); - - \r.x.result_RNIO9S65[7]\ : OR2B - port map(A => \bpdata[7]\, B => N_3957_1, Y => - \bpdata_m_1[7]\); - - \r.w.result_RNI60P1[12]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[12]\, - Y => \result_m_0_0[12]\); - - \r.e.jmpl_RNICH3L22\ : OR3C - port map(A => \aluresult_2_iv_7[2]\, B => - \shiftin_17_m_0[2]\, C => jmpl_RNIR18H6, Y => - \aluresult[2]\); - - \r.a.rsel1_0_RNI73LJ2[2]\ : OR2B - port map(A => data1(10), B => d11, Y => \rfo_m[10]\); - - \r.a.ctrl.rd[2]\ : DFN1E0 - port map(D => \rd_2[2]\, CLK => lclk_c, E => holdn, Q => - \rd[2]\); - - \r.a.ctrl.inst[10]\ : DFN1E0 - port map(D => \inst_0[10]\, CLK => lclk_c, E => holdn, Q - => \inst[10]\); - - \r.m.y_RNO_1[10]\ : AOI1B - port map(A => \y_0[10]\, B => y08_0, C => \y_m_0[11]\, Y - => \y_iv_0[10]\); - - \r.e.jmpl_RNICI5ES1\ : AOI1B - port map(A => \shiftin_17[32]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[31]\, Y => \aluresult_1_iv_8[31]\); - - \r.x.data_0_RNIDVN8[3]\ : MX2 - port map(A => \op1[3]\, B => \data_0[3]\, S => ldbp1_4, Y - => \un1_iu0_6[3]\); - - un6_fe_npc_I_165 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[18]\, Y => N_35_0); - - \r.x.data_0_RNO_2[24]\ : AO1B - port map(A => rdatav_0_1_0_iv_5_6, B => mcdo_m_0_22, C => - rdata_6_sqmuxa, Y => \dco_m_1_i[120]\); - - \r.e.aluop_0_RNIR3AK2[1]\ : MX2C - port map(A => \logicout_4[28]\, B => N_6874, S => - N_6866_i_0, Y => N_3651); - - \r.e.op2_RNO_3[25]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[25]\, Y => - \aluresult_m_i[25]\); - - \r.x.data_0_RNO_0[14]\ : NOR2B - port map(A => N_3473, B => data_0_2_14, Y => \dco_m_0[110]\); - - \r.a.rsel1_RNI1RFA_0[0]\ : NOR2B - port map(A => un17_casaen_0, B => N_494, Y => - un14_casaen_s1_0); - - \r.a.ctrl.inst_RNIFO1E[23]\ : NOR2B - port map(A => \inst_1[23]\, B => \inst_2[19]\, Y => - inst_32_0); - - \r.e.op2_RNIH11O85[0]\ : OR3C - port map(A => \op2_RNI1LHG[1]\, B => \op2_RNI59C6[0]\, C - => \icc_8_1[1]\, Y => \icc_8[1]\); - - \r.x.result[14]\ : DFN1E0 - port map(D => \maddress[14]\, CLK => lclk_c, E => holdn, Q - => \result_0[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I180_Y\ : AO1A - port map(A => N547, B => N554, C => N546_1, Y => N606); - - \r.x.data_0_RNO[10]\ : OR3B - port map(A => \data_0_1_0_iv_1[10]\, B => \dco_m_0_i[106]\, - C => \data_0_1_1[12]\, Y => \data_0_1[10]\); - - \r.e.op1[29]\ : DFN1E0 - port map(D => \aop1[29]\, CLK => lclk_c, E => holdn, Q => - \op1[29]\); - - \r.a.rsel2_RNI9LB_3[1]\ : NOR2 - port map(A => \rsel2[2]\, B => \rsel2[1]\, Y => d26_0); - - \r.a.rsel1_0_RNIE7LJ2[2]\ : OR2B - port map(A => data1(24), B => d11_0, Y => \rfo_m[24]\); - - \r.a.et\ : DFN1E0 - port map(D => et_2, CLK => lclk_c, E => holdn, Q => et_1); - - \r.e.ctrl.tt_RNO_1[2]\ : OR3 - port map(A => ticc, B => wunf, C => wovf, Y => - \tt_9_i_a4_0[2]\); - - \r.d.inst_0_RNO[5]\ : NOR2B - port map(A => rst, B => N_4605, Y => \inst_0_RNO[5]\); - - \r.d.cnt[0]\ : DFN1E1 - port map(D => cnt_2_sqmuxa, CLK => lclk_c, E => N_6825_i, Q - => \cnt_2[0]\); - - \comb.ld_align.rdata199_RNI46JTI_0\ : NOR2A - port map(A => rdata_2_sqmuxa_0, B => rdata199, Y => - rdata_2_sqmuxa_1); - - \r.m.ctrl.inst_RNIDP678[30]\ : OR2 - port map(A => \inst_RNIVASI1[30]\, B => trap_1_sqmuxa, Y - => un1_trap_1_sqmuxa); - - \r.d.inst_0_RNIKC392[4]\ : NOR2B - port map(A => I_13_1, B => un1_reg, Y => \un3_de_ren1[104]\); - - \r.x.data_0_RNO_0[13]\ : NOR2B - port map(A => N_3473, B => data_0_2_13, Y => \dco_m_0[109]\); - - \r.e.op2_RNI1PJF75_0[31]\ : AO16 - port map(A => \un1_iu0_6[31]\, B => \un1_iu0_5[97]\, C => - \eaddress[31]\, Y => \icc_2[1]\); - - \r.f.pc_RNO[21]\ : OR3C - port map(A => \tmp_m[21]\, B => \pc_1_iv_1[21]\, C => - \un6_fe_npc_m[19]\, Y => \pc_1[21]\); - - \r.a.ctrl.inst_RNI013H1_0[21]\ : OR3 - port map(A => inst_9_3, B => N_241, C => N_204, Y => N_359); - - \r.e.op1_RNIC3O8[4]\ : MX2 - port map(A => \op1[4]\, B => \data_0[4]\, S => ldbp1_1, Y - => \un1_iu0_6[4]\); - - \r.a.bp_RNIKBBRB\ : NOR2B - port map(A => ra_bpmiss_1, B => ex_bpmiss_1, Y => - bpmiss_1_i_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I24_P0N : OR3A - port map(A => \data_0[23]\, B => \op1[23]\, C => ldbp1, Y - => N467_2); - - \r.e.aluop_0[1]\ : DFN1E0 - port map(D => \aluop[1]\, CLK => lclk_c, E => holdn, Q => - \aluop_0[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I246_Y_0_a3 : NOR2B - port map(A => N808_0, B => N431_1, Y => - ADD_33x33_fast_I246_Y_0_a3_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I189_un1_Y : OR2B - port map(A => N600, B => N593, Y => I189_un1_Y_i); - - \r.m.result_RNIOIRC3[8]\ : NOR3C - port map(A => \d_iv_0[8]\, B => \result_m_0[8]\, C => - \rfo_m[8]\, Y => \d_iv_2[8]\); - - \r.d.pc_RNO[19]\ : MX2 - port map(A => \fpc[19]\, B => \dpc[19]\, S => N_6763_i, Y - => \pc_RNO[19]\); - - \r.w.s.icc_RNO[3]\ : AO1B - port map(A => icc_1_sqmuxa, B => \icc_0[3]\, C => - \icc_1_iv_0[3]\, Y => \icc_1[3]\); - - \r.e.op2_RNO_1[24]\ : OR2B - port map(A => \op1[24]\, B => un14_casaen_s1, Y => - \op1_m_i[24]\); - - \r.x.result[6]\ : DFN1E0 - port map(D => \maddress[6]\, CLK => lclk_c, E => holdn, Q - => \result_0[6]\); - - \r.w.s.wim_RNI75RD2[1]\ : OR2B - port map(A => \wim[1]\, B => aluresult_13_sqmuxa, Y => - \wim_m[1]\); - - \r.a.ctrl.inst_RNI7K0E[21]\ : OR2 - port map(A => \inst[22]\, B => \inst_2[21]\, Y => N_492); - - \r.e.op2_RNI33A92[15]\ : AOI1B - port map(A => \un1_iu0_5[81]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[15]\); - - \r.e.shcnt_RNIGTEB5[3]\ : MX2 - port map(A => \shiftin_8[18]\, B => \shiftin_8[10]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I96_Y : NOR3B - port map(A => N485, B => N488_2, C => N497_0, Y => N559); - - \r.m.y_RNO_2[18]\ : OR2B - port map(A => \y_1[18]\, B => y08, Y => N_394); - - \r.e.op2_RNO_0[27]\ : OR3C - port map(A => \op1_m_i[27]\, B => \d_1_iv_3[27]\, C => - \aluresult_m_i[27]\, Y => \d_1[27]\); - - \r.x.ctrl.pc_RNIB2HF[13]\ : MX2 - port map(A => \pc_0[13]\, B => \pc_2[13]\, S => \npc_1[1]\, - Y => N_3224); - - \r.e.op1_RNIVANF[22]\ : NOR2A - port map(A => \un17_casaen_0_0\, B => \op1[22]\, Y => - \op1_i_m[22]\); - - \r.e.aluop_0_RNIP8ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[22]\, B => \aluop_0[1]\, C => - \un1_iu0_5[88]\, Y => N_6862); - - \r.a.ctrl.inst_RNIFK1L[20]\ : NOR2B - port map(A => \inst_2[20]\, B => N_225, Y => - aluop_0_1_0_a5_0); - - \r.x.data_0[7]\ : DFN1E0 - port map(D => \data_0_1[7]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0_2[7]\); - - \r.w.s.wim_RNIB4JO5[0]\ : NOR2A - port map(A => \aluresult_2_iv_0[0]\, B => \aluresult_4[1]\, - Y => \aluresult_2_iv_2[0]\); - - \r.a.imm[27]\ : DFN1E0 - port map(D => \un3_de_ren1[145]\, CLK => lclk_c, E => holdn, - Q => \imm[27]\); - - \r.e.ctrl.pc_RNIMR011[2]\ : OR2B - port map(A => \pc_2[2]\, B => jmpl_4, Y => \cpi_m[147]\); - - \r.m.y_RNO_3[22]\ : OR3A - port map(A => \y_2[22]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[22]\); - - \r.e.aluop_RNIK26I6[0]\ : MX2C - port map(A => N_3586, B => N_3650, S => \aluop_1[0]\, Y => - \logicout[27]\); - - \r.f.pc_RNO_1[23]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[23]\, C => - \pc_1_iv_0[23]\, Y => \pc_1_iv_1[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I125_Y_0\ : OA1 - port map(A => \dpc[8]\, B => \inst_0[6]\, C => N380, Y => - ADD_30x30_fast_I125_Y_0); - - \r.d.inst_0[8]\ : DFN1 - port map(D => \inst_0_RNO[8]\, CLK => lclk_c, Q => - \inst_0[8]\); - - \r.x.mexc_RNIGSPT\ : OR2 - port map(A => mexc_0, B => N_3322, Y => \xc_vectt_1[3]\); - - \r.a.ctrl.rd_RNIRU2V[0]\ : XNOR2 - port map(A => \rs1_iv_i_0[0]\, B => \rd_2[0]\, Y => - un2_rs1_0_i); - - \r.x.ctrl.pc_RNI04I61[14]\ : MX2C - port map(A => \un1_p0_6[366]\, B => \pc_0[14]\, S => - s_3_sqmuxa_0, Y => N_3405); - - \r.w.s.tba[6]\ : DFN1E1 - port map(D => \result_0[18]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[6]\); - - \r.e.op1_RNI6CMO6[20]\ : AO1A - port map(A => \un1_iu0_6[20]\, B => edata_3_sqmuxa_0, C => - \edata2_0_iv_0[20]\, Y => \edata2_0_iv_1[20]\); - - \r.e.jmpl_RNIUM1833\ : OR3C - port map(A => \aluresult_1_iv_8[10]\, B => - \shiftin_17_m_0[10]\, C => \un6_ex_add_res_m[11]\, Y => - \aluresult[10]\); - - un6_fe_npc_I_51 : NOR2B - port map(A => \fe_pc[10]\, B => \DWACT_FINC_E[4]\, Y => - N_116); - - \r.m.ctrl.pc[15]\ : DFN1E0 - port map(D => \pc_2[15]\, CLK => lclk_c, E => holdn, Q => - \pc_3[15]\); - - \r.e.op2_RNO[8]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[8]\, Y => N_292); - - un6_ex_add_res_d2_ADD_33x33_fast_I179_Y : AO1 - port map(A => N590_1, B => N583_2, C => N582_2, Y => N648_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_o3_1_0 : AO18 - port map(A => N397, B => \data_0[1]\, C => \un1_iu0_6[1]\, - Y => ADD_33x33_fast_I206_Y_0_o3_1_0); - - \r.a.ctrl.pc_RNIJOL0C[6]\ : MX2 - port map(A => \pc_0[6]\, B => N_3883, S => ex_bpmiss_1_0, Y - => \fe_pc[6]\); - - \r.e.alusel_RNO_0[0]\ : OA1A - port map(A => N_226, B => N_204, C => \alusel_i_0_1[0]\, Y - => \alusel_i_0_2[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I110_un1_Y\ : NOR2B - port map(A => N475, B => N472, Y => I110_un1_Y); - - \comb.v.x.data_0_1_1_iv_2[19]\ : OR2 - port map(A => \rdata_5_m_9[8]\, B => \rdata_13_m_9[8]\, Y - => \data_0_1_2[17]\); - - \r.e.aluop_RNI4VJD4[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[24]\, Y => - \bpdata_i_m[24]\); - - \r.e.jmpl_RNI221OS\ : OR2B - port map(A => \shiftin_17[25]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[25]\); - - \r.d.inst_0_RNO_0[30]\ : MX2 - port map(A => data_0_2_30, B => \inst_0[30]\, S => - inull_RNIFV6VG2_0, Y => N_4630); - - \r.e.op1_RNI5HUH[15]\ : MX2 - port map(A => \op1[15]\, B => \data_0_2[15]\, S => ldbp1_2, - Y => \un1_iu0_6[15]\); - - \r.f.pc_RNO_7[27]\ : MX2 - port map(A => \fpc[27]\, B => \tba[15]\, S => - rstate_6314_d_0, Y => \xc_trap_address[27]\); - - un6_fe_npc_I_27 : AND2 - port map(A => \fe_pc[5]\, B => \fe_pc[6]\, Y => - \DWACT_FINC_E[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I17_G0N : NOR3A - port map(A => \op1[16]\, B => ldbp1_4, C => \data_0[16]\, Y - => N445_0); - - \r.e.shcnt_RNITNFBC[2]\ : MX2C - port map(A => \shiftin_11[22]\, B => \shiftin_11[18]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[18]\); - - \r.w.s.tba[3]\ : DFN1E1 - port map(D => \result_0[15]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[3]\); - - \r.x.rstate_0_RNI40DE1[0]\ : OA1A - port map(A => rstate_1188n, B => holdn, C => N_6322, Y => - N_6322s); - - \r.e.op2_RNO_4[28]\ : OA1A - port map(A => \maddress[28]\, B => d27_0, C => - \cpi_m_i[380]\, Y => \d_1_iv_1[28]\); - - \r.e.ctrl.pc[14]\ : DFN1E0 - port map(D => \pc[14]\, CLK => lclk_c, E => holdn, Q => - \pc_1[14]\); - - \r.a.ctrl.pc_RNIUBE2C[30]\ : MX2 - port map(A => \pc[30]\, B => N_3907, S => ex_bpmiss_1_0, Y - => \fe_pc[30]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I271_un1_Y : OR3C - port map(A => N649, B => N665_1, C => N614_2, Y => - I271_un1_Y_i_0); - - \r.e.ctrl.tt_RNO[1]\ : OA1B - port map(A => N_16735_tz, B => N_4033_i, C => \tt_0[1]\, Y - => \tt_1[1]\); - - \r.m.icc_RNI68I3[0]\ : OR2 - port map(A => \icc_0[2]\, B => \icc_0[0]\, Y => N_375); - - \r.e.shleft_RNI7ERJ\ : NOR2A - port map(A => \un1_iu0_6[14]\, B => shleft, Y => - \shiftin_5_i[14]\); - - \r.d.pv_RNO_8\ : OR3B - port map(A => annul_2, B => \de_hold_pc_1\, C => - \inst_2[29]\, Y => N_4239); - - \r.x.ctrl.wicc\ : DFN1E0 - port map(D => wicc_1_2, CLK => lclk_c, E => holdn, Q => - wicc); - - \r.d.cnt_RNIIB6B[1]\ : NOR2A - port map(A => un5_op3, B => \cnt_0[1]\, Y => - ldcheck1_1_sqmuxa_1); - - \r.a.rsel1_RNIEQG766[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[23]\, Y - => \aluresult_m_0[23]\); - - \r.e.op2_RNO_9[9]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[361]\, Y => \cpi_m_i[361]\); - - \r.x.ctrl.tt[2]\ : DFN1E0 - port map(D => \tt2[2]\, CLK => lclk_c, E => holdn, Q => - \tt[2]\); - - \r.e.op1_RNIK04F[2]\ : OR2B - port map(A => \op1[2]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[2]\); - - \r.e.cwp_RNIFT8H3[2]\ : NOR3C - port map(A => \cpi_m[147]\, B => \y_m_1[2]\, C => - \cwp_m[2]\, Y => \aluresult_2_iv_3[2]\); - - \r.e.op1_RNIN2TR3[4]\ : NOR3C - port map(A => \rfo_m[4]\, B => \d_iv_1[4]\, C => - \op1_m_0[4]\, Y => \d_iv_3[4]\); - - \r.e.op2_RNIIGNB1[26]\ : OR2A - port map(A => \un1_iu0_5[92]\, B => \un1_iu0_6[26]\, Y => - \logicout_4[26]\); - - \r.x.y[4]\ : DFN1E0 - port map(D => \y[4]\, CLK => lclk_c, E => holdn, Q => - \y_1[4]\); - - \r.x.data_0_RNIIVG8[20]\ : XOR2 - port map(A => \data_0_2[20]\, B => invop2, Y => N_4267); - - \r.e.op2_RNO_6[27]\ : OR2B - port map(A => data2(27), B => d25, Y => \rfo_m_i[59]\); - - \r.d.pc_RNO[2]\ : MX2 - port map(A => \fpc[2]\, B => \dpc[2]\, S => N_6763_i_0, Y - => \pc_RNO[2]\); - - \r.e.invop2_1_RNI67J0N2\ : MX2C - port map(A => \un6_ex_add_res_s2[28]\, B => - \un6_ex_add_res_s0[28]\, S => invop2_1, Y => N_6574); - - \r.e.aluop_RNIBO773[1]\ : MX2C - port map(A => N_3546, B => \logicout_3[19]\, S => - \aluop_3[1]\, Y => N_3578); - - \r.d.inst_0_RNI9446[21]\ : NOR3C - port map(A => \inst_0[19]\, B => \inst_0_0[21]\, C => - icc_check9_2, Y => inst_0_2); - - \r.e.aluop_RNI575F1[2]\ : XA1 - port map(A => \un1_iu0_5[77]\, B => \aluop_1[2]\, C => - \un1_iu0_6[11]\, Y => N_3538); - - \r.a.ctrl.inst_RNI6G0E[22]\ : OR2B - port map(A => \inst[22]\, B => \inst_2[20]\, Y => N_271); - - \comb.branch_address.tmp_ADD_30x30_fast_I287_Y_0_0\ : XOR2 - port map(A => \dpc[29]\, B => \inst_0_RNI8AJ4[27]\, Y => - ADD_30x30_fast_I287_Y_0_0); - - \r.x.y[1]\ : DFN1E0 - port map(D => \y[1]\, CLK => lclk_c, E => holdn, Q => - \y_2[1]\); - - un6_fe_npc_I_76 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \fe_pc[14]\, Y => N_98); - - un6_ex_add_res_d0_ADD_33x33_fast_I314_Y_0 : XNOR2 - port map(A => N780, B => \un6_ex_add_res_s2_1[24]\, Y => - \un6_ex_add_res_s0[24]\); - - \r.e.aluop_2_RNI05613[1]\ : MX2C - port map(A => N_3543, B => \logicout_3[16]\, S => - \aluop_2[1]\, Y => N_3575); - - \r.x.data_0_RNO_1[10]\ : AO1B - port map(A => rdatav_0_1_0_iv_0_2(10), B => N_3305_0, C => - N_3473, Y => \dco_m_0_i[106]\); - - \r.x.ctrl.wy_RNILF1N3_1\ : NOR2 - port map(A => y_1_sqmuxa_1, B => y_1_sqmuxa_0, Y => N_481_0); - - \r.m.y_RNO_4[14]\ : OR2B - port map(A => \y[15]\, B => mulstep_1, Y => N_389); - - \r.f.pc_RNO_5[23]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[23]\, Y => \xc_trap_address_m[23]\); - - un6_fe_npc_I_192 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[22]\, Y => \DWACT_FINC_E[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I151_Y : AO1 - port map(A => N552_0, B => N549_1, C => N548, Y => N614_0); - - \dci.enaddr_1_sqmuxa_1_RNI3PQ961\ : MX2C - port map(A => enaddr_1_sqmuxa_1, B => \inst_1[21]\, S => - enaddr_2_sqmuxa, Y => \eenaddr\); - - \r.e.jmpl_RNIJIRLN2\ : OR3C - port map(A => \aluresult_1_iv_8[9]\, B => - \shiftin_17_m_0[9]\, C => \un6_ex_add_res_m[10]\, Y => - \aluresult[9]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I158_Y : NOR3A - port map(A => N495, B => N_50, C => N569, Y => N627_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I6_P0N\ : OR2 - port map(A => \inst_0[6]\, B => \dpc[8]\, Y => N377); - - \r.x.result[20]\ : DFN1E0 - port map(D => \maddress[20]\, CLK => lclk_c, E => holdn, Q - => \result[20]\); - - \r.f.pc_RNO_3[24]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[24]\, Y => - \pc_4_m[24]\); - - \r.m.y_RNO_3[15]\ : AOI1B - port map(A => \y[15]\, B => y08_0, C => \y_m[16]\, Y => - \y_iv_0[15]\); - - \r.a.ctrl.pc_RNIF4F2C[28]\ : MX2 - port map(A => \pc[28]\, B => N_3905, S => ex_bpmiss_1, Y - => \fe_pc[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I131_Y : AO1 - port map(A => N532_0, B => N529_1, C => N528_1, Y => N594_1); - - \r.m.ctrl.annul\ : DFN1E0 - port map(D => annul_1_1, CLK => lclk_c, E => holdn, Q => - annul_5); - - un6_ex_add_res_d1_ADD_33x33_fast_I138_Y : NOR3C - port map(A => N419_1, B => N416_1, C => N535_0, Y => N601); - - \r.x.result[19]\ : DFN1E0 - port map(D => \maddress[19]\, CLK => lclk_c, E => holdn, Q - => \result_0[19]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I147_Y : AOI1 - port map(A => N548_0, B => N545_0, C => N544_2, Y => N610_0); - - \r.f.pc_RNO_2[30]\ : OR2B - port map(A => I_203, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[28]\); - - \r.e.aluop_0_RNIK8ROQ[0]\ : NOR3C - port map(A => \aluresult_1_iv_5[26]\, B => - \aluresult_1_iv_4[26]\, C => \logicout_m_0[26]\, Y => - \aluresult_1_iv_7[26]\); - - \r.e.op2_RNO_1[15]\ : OR2B - port map(A => \op1[15]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[15]\); - - \r.e.jmpl_RNI60MO28\ : OR3C - port map(A => \aluresult_1_iv_8[31]\, B => - \shiftin_17_m_0[31]\, C => \un6_ex_add_res_m[32]\, Y => - \aluresult[31]\); - - \r.x.ctrl.inst_RNIVU2L[25]\ : NOR3 - port map(A => \inst[26]\, B => \inst[25]\, C => - \inst_1[29]\, Y => y_0_sqmuxa_2); - - un9_ra_I_9 : XOR2 - port map(A => \cwp_0[0]\, B => \inst_0[29]\, Y => - \DWACT_ADD_CI_0_partial_sum_1[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I271_un1_Y : OR3C - port map(A => N649_0, B => N665_0, C => N614_1, Y => - I271_un1_Y); - - \r.x.data_0[31]\ : DFN1E0 - port map(D => \data_0_1[31]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0_0[31]\); - - \r.e.aluop_2_RNIJBDM1[1]\ : MX2C - port map(A => N_3534, B => \logicout_3[7]\, S => - \aluop_2[1]\, Y => N_3566); - - \r.x.mexc_RNIAGPT\ : NOR2 - port map(A => mexc_0, B => N_3319, Y => \xc_vectt_1[0]\); - - \r.a.cwp[2]\ : DFN1E0 - port map(D => \cwp_0[2]\, CLK => lclk_c, E => holdn, Q => - \cwp_3[2]\); - - \r.x.data_0[17]\ : DFN1E0 - port map(D => \data_0_1[17]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[17]\); - - \r.m.ctrl.trap_RNIPFG4B\ : NOR2A - port map(A => un1_trap_1_sqmuxa, B => annul_3, Y => - tt_2_sqmuxa_1_0); - - \r.e.ctrl.trap_RNO_0\ : NOR3A - port map(A => trap_4_1_0, B => trap_4_1, C => N_4033_i, Y - => trap_4); - - un6_ex_add_res_d2_ADD_33x33_fast_I18_P0N : AO1A - port map(A => ldbp1_1, B => \op1[17]\, C => \data_0[17]\, Y - => N449_0); - - \r.e.shleft_1_RNI55IP\ : OR2A - port map(A => \un1_iu0_6[26]\, B => shleft_1, Y => - \shiftin_5[26]\); - - un6_fe_npc_I_136 : XOR2 - port map(A => N_56, B => \fe_pc[23]\, Y => I_136); - - \r.f.pc_RNO_4[18]\ : MX2 - port map(A => I_98, B => N_4061, S => bpmiss_1_i_0_0, Y => - \pc_4[18]\); - - \r.f.pc_RNIEG981[4]\ : MX2B - port map(A => \fpc[4]\, B => \xc_vectt_1[0]\, S => - rstate_6314_d, Y => \xc_trap_address[4]\); - - \r.e.op2_RNIMCB71[28]\ : OR2A - port map(A => \un1_iu0_5[94]\, B => \un1_iu0_6[28]\, Y => - \logicout_4[28]\); - - \r.e.jmpl_RNITT19R\ : OR2B - port map(A => \shiftin_17[20]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[20]\); - - \r.a.ctrl.wicc_RNO_4\ : AOI1 - port map(A => \un1_p0_6_0[60]\, B => un7_op_3, C => un3_op2, - Y => wicc_1_0_a3_0); - - \r.d.pc[26]\ : DFN1 - port map(D => \pc_RNO[26]\, CLK => lclk_c, Q => \dpc[26]\); - - \r.x.data_0_RNO[21]\ : OR3 - port map(A => \dco_m_0[117]\, B => \data_0_m[21]\, C => - \data_0_1_4[18]\, Y => \data_0_1[21]\); - - \r.e.jmpl_RNIRFSGR\ : NAND2 - port map(A => aluresult_1_sqmuxa_0, B => \shiftin_17[21]\, - Y => \shiftin_17_m[21]\); - - \r.e.mulstep_RNI8VGC_1\ : NOR2B - port map(A => mulstep, B => wy_0, Y => mulstep_0); - - \r.d.inst_0_RNIAM6B2[4]\ : NOR2B - port map(A => I_14_0, B => un1_reg, Y => \un3_de_ren1[105]\); - - \r.a.ctrl.annul_RNI7R7R8\ : OR3A - port map(A => ra_bpannul_1, B => annul_2, C => - \un1_p0_6[0]\, Y => N_149); - - \r.e.op2_RNO_0[30]\ : OR3C - port map(A => \op1_m_i[30]\, B => \d_1_iv_3[30]\, C => - \aluresult_m_i[30]\, Y => \d_1[30]\); - - \r.a.rfe2\ : DFN1E0 - port map(D => rfe, CLK => lclk_c, E => holdn, Q => \rfe2\); - - \r.m.ctrl.pc[24]\ : DFN1E0 - port map(D => \pc[24]\, CLK => lclk_c, E => holdn, Q => - \pc_2[24]\); - - un6_fe_npc_I_162 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - Y => \DWACT_FINC_E[18]\); - - \r.d.cnt_RNIRCME[0]\ : NOR2A - port map(A => un10_op, B => call_hold7_i, Y => rs1mod); - - \r.m.result_RNIRVO1[11]\ : OR2B - port map(A => d13, B => \maddress[11]\, Y => - \result_m_0[11]\); - - \r.m.icc_RNO_6[2]\ : NOR3C - port map(A => icc_0_sqmuxa_1_10, B => icc_0_sqmuxa_1_9, C - => icc_0_sqmuxa_1_22, Y => icc_0_sqmuxa_1_27); - - \r.e.shleft_0_RNISKHP\ : OR2A - port map(A => \un1_iu0_6[22]\, B => shleft_0, Y => - \shiftin_5[22]\); - - \r.e.op2_RNO_5[14]\ : AOI1B - port map(A => \result[14]\, B => d31_0, C => \imm_m_i[14]\, - Y => \d_1_iv_0[14]\); - - \r.e.aluop_RNIGM3N1[2]\ : OR2 - port map(A => edata_2_sqmuxa, B => edata_1_sqmuxa, Y => - \aluop_RNIGM3N1[2]\); - - \r.e.jmpl_RNII70061\ : NOR2B - port map(A => \aluresult_1_iv_5[3]\, B => \shiftin_17_m[4]\, - Y => \aluresult_1_iv_6[3]\); - - \r.e.ctrl.inst_RNI2H1S[30]\ : NOR2A - port map(A => un3_notag, B => N_3749_2, Y => un3_op_2); - - \r.e.ctrl.pc[13]\ : DFN1E0 - port map(D => \pc[13]\, CLK => lclk_c, E => holdn, Q => - \pc_2[13]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I313_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[22]\, B => \data_0_0[22]\, Y => - \un6_ex_add_res_s2_1[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I14_G0N : AND2 - port map(A => \op2[13]\, B => \un1_iu0_6[13]\, Y => N436); - - \r.x.ctrl.wy_RNI4SI14_0\ : OR2 - port map(A => wy_RNILF1N3, B => holdn, Y => N_6922_i_0); - - \r.x.ctrl.pc_RNIVT971[23]\ : MX2C - port map(A => \un1_p0_6[375]\, B => \pc[23]\, S => - s_3_sqmuxa, Y => N_3414); - - \r.a.ctrl.cnt_RNI6P4J3[0]\ : NOR3C - port map(A => N_457, B => N_456, C => N_458, Y => - un1_aop2_1_sqmuxa); - - un6_ex_add_res_d0_ADD_33x33_fast_I307_Y_0 : AX1D - port map(A => N442, B => ADD_33x33_fast_I274_Y_0_a3_0, C - => \un6_ex_add_res_s0_1[17]\, Y => - \un6_ex_add_res_s0[17]\); - - \r.f.pc_RNO_6[24]\ : MX2 - port map(A => I_143, B => N_4067, S => bpmiss_1_i_0, Y => - \pc_4[24]\); - - \r.a.ctrl.pc_RNID8L0C[4]\ : MX2 - port map(A => \pc_0[4]\, B => N_3881, S => ex_bpmiss_1, Y - => \fe_pc[4]\); - - \r.x.dci.size_RNIUK8C9[1]\ : MX2 - port map(A => \size_0[1]\, B => \size_2[1]\, S => - dco_i_2(132), Y => \me_size_1[1]\); - - \r.w.s.y_RNI5H6G1[0]\ : AOI1B - port map(A => wy_1_0, B => \y[0]\, C => N_465, Y => - \y_iv_0_o5_1[0]\); - - \r.m.ctrl.inst_RNI5S3O1[20]\ : AOI1 - port map(A => inst_4_2, B => inst_4_1, C => inst, Y => - trap55_i); - - \r.e.ctrl.pc_RNI6VEPF[9]\ : NOR2B - port map(A => \aluresult_1_iv_4[9]\, B => - \aluresult_1_iv_5[9]\, Y => \aluresult_1_iv_6[9]\); - - \r.e.op1[11]\ : DFN1E0 - port map(D => \aop1[11]\, CLK => lclk_c, E => holdn, Q => - \op1[11]\); - - \comb.v.x.data_0_1_1_iv_RNO_0[16]\ : AO1A - port map(A => ld_0_0, B => \data_0[16]\, C => - \dco_m_0[112]\, Y => \data_0_1_1_iv_0[16]\); - - \r.d.inst_0_RNI513S[17]\ : MX2C - port map(A => \de_raddr1_2[4]\, B => \de_raddr1_1[4]\, S - => rs1mod, Y => \un3_de_ren1[95]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I18_G0N : OA1 - port map(A => \op1[17]\, B => ldbp1_1, C => \data_0[17]\, Y - => N448_1); - - \r.e.op2_RNO_8[10]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[362]\, Y => \cpi_m_i[362]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I12_G0N : OAI1 - port map(A => \op1[11]\, B => ldbp1, C => \data_0_2[11]\, Y - => N430_1); - - \r.e.ldbp2_RNI7TP6N1\ : OR2A - port map(A => \eaddress[15]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[16]\); - - \r.e.op2_RNO_1[21]\ : AOI1B - port map(A => \op1[21]\, B => un14_casaen_s1_0_1, C => - \d_1_iv_3[21]\, Y => \d_1_iv_4[21]\); - - \r.m.ctrl.pc_RNI2PL9[20]\ : MX2 - port map(A => \pc_3[20]\, B => \pc[20]\, S => \npc[1]\, Y - => N_3261); - - \r.e.aluop_0_RNIID791[2]\ : XA1 - port map(A => \un1_iu0_5[95]\, B => \aluop_0[2]\, C => - \un1_iu0_6[29]\, Y => N_3556); - - \r.d.inull_RNIE9S2\ : NOR2 - port map(A => \inull\, B => annul_1, Y => - annul_next_2_sqmuxa_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_Y : NAND2 - port map(A => I265_un1_Y_i, B => ADD_33x33_fast_I265_Y_1, Y - => N776_1); - - \r.e.ctrl.tt_RNO_2[0]\ : AO1A - port map(A => wunf, B => ticc, C => wovf, Y => - N_16684_tz_tz); - - un6_fe_npc_I_98 : XOR2 - port map(A => N_83, B => \fe_pc[18]\, Y => I_98); - - un6_ex_add_res_d1_ADD_33x33_fast_I55_Y_0_o3 : AO1 - port map(A => N455_2, B => N451_1, C => N454_2, Y => N514_1); - - \r.d.pc[7]\ : DFN1 - port map(D => \pc_RNO[7]\, CLK => lclk_c, Q => \dpc[7]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I145_un1_Y : NOR2B - port map(A => N546_2, B => N543_2, Y => I145_un1_Y); - - \r.m.icc_RNIL8JA[3]\ : NOR3B - port map(A => \icc[1]\, B => \icc[3]\, C => \inst_1[27]\, Y - => ex_bpmiss_1_0_a5_2_1_0); - - \r.e.jmpl\ : DFN1E0 - port map(D => N_4, CLK => lclk_c, E => holdn, Q => jmpl); - - \r.d.inst_0_RNO_0[0]\ : MX2 - port map(A => data_0_2_0, B => \inst_0[0]\, S => - mexc_1_sqmuxa_1_0, Y => N_4600); - - un6_ex_add_res_d1_ADD_33x33_fast_I146_Y : NOR2B - port map(A => ADD_33x33_fast_I146_Y_0, B => N543_2, Y => - N609_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I15_P0N : OR3A - port map(A => \data_0[14]\, B => \op1[14]\, C => ldbp1_0, Y - => N440_0); - - \r.d.annul_RNIMNQL44\ : OR2B - port map(A => I_24, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[5]\); - - \r.a.imm[16]\ : DFN1E0 - port map(D => \un3_de_ren1[134]\, CLK => lclk_c, E => holdn, - Q => \imm[16]\); - - \r.e.shleft_0_RNIB1IM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[23]\, S => - shleft_0, Y => \shiftin_5[54]\); - - \r.d.pc[2]\ : DFN1 - port map(D => \pc_RNO[2]\, CLK => lclk_c, Q => \dpc[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I215_un1_Y : OAI1 - port map(A => I175_un1_Y, B => N578, C => N629_0, Y => - I215_un1_Y); - - \r.e.aluop_2_RNIG4513[1]\ : MX2C - port map(A => N_3541, B => \logicout_3[14]\, S => - \aluop_2[1]\, Y => N_3573); - - \r.m.icc_RNO_20[2]\ : NOR2 - port map(A => \logicout[9]\, B => \logicout[10]\, Y => - icc_0_sqmuxa_1_3); - - \r.w.result_RNI8TA4[1]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[1]\, Y - => \result_m_0_0[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I89_Y : AO13 - port map(A => \un1_iu0_6[2]\, B => \data_0[2]\, C => N400_1, - Y => N548_0); - - \r.e.op1_RNIRTKP72[4]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[4]\, C - => \d_1_iv_4[4]\, Y => \d_1[4]\); - - \r.e.aluop_RNI2ECS1[1]\ : MX2C - port map(A => N_3532, B => \logicout_3[5]\, S => - \aluop_3[1]\, Y => N_3564); - - \r.m.y_RNO_3[5]\ : AOI1B - port map(A => wy_1_0, B => \y[5]\, C => \y_m_2[5]\, Y => - \y_iv_1[5]\); - - \r.m.ctrl.inst_RNI8FKRJ[30]\ : NOR2 - port map(A => un5_trap, B => un6_annul, Y => - \nullify2_0_sqmuxa\); - - \r.m.ctrl.pc_RNI8MF8[5]\ : MX2 - port map(A => \pc_2[5]\, B => \pc_0[5]\, S => \npc[1]\, Y - => N_3246); - - \r.e.ctrl.pc[6]\ : DFN1E0 - port map(D => \pc_0[6]\, CLK => lclk_c, E => holdn, Q => - \pc[6]\); - - \r.d.inst_0_RNI2KBFU8[29]\ : OR2B - port map(A => pv_4_0, B => annul_next_14, Y => annul_4); - - \r.m.ctrl.rd_RNIDCCC2[5]\ : XNOR2 - port map(A => \un3_de_ren1[104]\, B => \rd_2[5]\, Y => - un1_de_ren1_1_5_i_0); - - \r.m.y_RNI84K91[2]\ : OR2B - port map(A => \y_0[2]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[2]\); - - \r.d.pc_RNIUDHB4[31]\ : MX2 - port map(A => \dpc[31]\, B => \fpc[31]\, S => - \ra_bpmiss_1_0\, Y => N_3908); - - un6_fe_npc_I_94 : AND2 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, Y - => \DWACT_FINC_E[10]\); - - \comb.fpstdata.edata2_0_iv_RNO[2]\ : OR2A - port map(A => N_3687, B => \bpdata[2]\, Y => - \bpdata_i_m[2]\); - - \r.w.s.y_RNO[16]\ : MX2 - port map(A => \y_2[16]\, B => \result_0[16]\, S => N_481_0, - Y => N_3780); - - \r.e.op2_RNIVQ992[22]\ : AOI1B - port map(A => \un1_iu0_5[88]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I176_Y : NOR3C - port map(A => N521_1, B => N525, C => N579_2, Y => N645_1); - - \r.e.op2[24]\ : DFN1E0 - port map(D => N_308, CLK => lclk_c, E => holdn, Q => - \op2[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I166_Y : NOR2B - port map(A => N577, B => N569_0, Y => N635_0); - - \r.f.pc_RNO_4[28]\ : MX2 - port map(A => I_186, B => N_4071, S => bpmiss_1_i_0, Y => - \pc_4[28]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I98_Y\ : AO1 - port map(A => N463_0, B => N460_0, C => N459, Y => N518); - - \r.e.op2[8]\ : DFN1E0 - port map(D => N_292, CLK => lclk_c, E => holdn, Q => - \op2[8]\); - - \r.x.data_0_RNO_1[1]\ : OA1A - port map(A => \data_0[1]\, B => ld_0_0, C => \dco_m_i[105]\, - Y => \data_0_1_1_iv_0[1]\); - - \r.m.result_RNIUQB33[0]\ : AO1A - port map(A => trap55_i, B => \maddress[0]\, C => - trap_0_sqmuxa_3, Y => un1_trap_0_sqmuxa_1_0); - - \r.a.rsel1_0_RNIB3LJ2[2]\ : OR2B - port map(A => data1(14), B => d11, Y => \rfo_m[14]\); - - \r.a.rsel2_0_RNIFA4D[0]\ : NOR2B - port map(A => un17_casaen_0_2, B => d26, Y => - un14_casaen_s1); - - \r.a.rsel1_RNI1RFA[0]\ : NOR2B - port map(A => un17_casaen_0, B => N_494, Y => - un14_casaen_s1_0_0); - - \r.w.s.wim[2]\ : DFN1E0 - port map(D => \wim_1[2]\, CLK => lclk_c, E => holdn, Q => - \wim[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I275_Y_0\ : XOR2 - port map(A => N723, B => ADD_30x30_fast_I275_Y_0_0, Y => - \tmp[17]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I308_Y_0 : AX1E - port map(A => I239_un1_Y_i, B => ADD_33x33_fast_I273_Y_0_1, - C => \un6_ex_add_res_s2_1[18]\, Y => - \un6_ex_add_res_s2[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I85_Y : MAJ3 - port map(A => \data_0[4]\, B => \un1_iu0_6[4]\, C => N406_1, - Y => N544_2); - - \r.m.y[6]\ : DFN1E0 - port map(D => \y_1[6]\, CLK => lclk_c, E => holdn, Q => - \y_0[6]\); - - \r.m.icc_RNO_19[2]\ : NOR2 - port map(A => \logicout[2]\, B => \logicout[3]\, Y => - icc_0_sqmuxa_1_12); - - \r.e.jmpl_RNIUUEBP\ : NAND2 - port map(A => aluresult_1_sqmuxa_0, B => \shiftin_17[15]\, - Y => \shiftin_17_m[15]\); - - \r.x.rstate_RNIHR5I2[0]\ : MX2C - port map(A => N_3404, B => \xc_result[13]\, S => - \rstate[0]\, Y => \wdata[13]\); - - \r.e.op2_RNO_2[18]\ : NOR3C - port map(A => \d_1_iv_1[18]\, B => \d_1_iv_0[18]\, C => - \rfo_m_i[50]\, Y => \d_1_iv_3[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I46_Y\ : MAJ3 - port map(A => \dpc[22]\, B => \inst_0[20]\, C => N415, Y - => N463_0); - - \r.f.pc_RNO_1[19]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[19]\, C => - \pc_1_iv_0[19]\, Y => \pc_1_iv_1[19]\); - - \r.w.s.tba_RNI83558[12]\ : AND2 - port map(A => \bpdata_m_2[0]\, B => \aluresult_1_iv_3[24]\, - Y => \aluresult_1_iv_5[24]\); - - \r.a.rsel1_RNIKEBD73[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[11]\, Y => - \aluresult_m_0[11]\); - - \r.a.ctrl.inst_RNIU03A1[31]\ : OR3A - port map(A => \inst[31]\, B => N_207, C => N_260, Y => - N_470); - - \r.a.ctrl.inst_RNI5I693[20]\ : OA1A - port map(A => aluadd_16_sqmuxa_0_a5_1, B => N_205, C => - N_359, Y => aluop_2_1_0_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I307_Y_0 : XOR3 - port map(A => \un1_iu0_6[16]\, B => \op2[16]\, C => N794_i, - Y => \un6_ex_add_res_s1_i[17]\); - - \r.m.ctrl.pc[23]\ : DFN1E0 - port map(D => \pc_0[23]\, CLK => lclk_c, E => holdn, Q => - \pc_2[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I118_Y\ : OR2A - port map(A => I118_un1_Y_i, B => N479_0, Y => N538_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I14_P0N : OA1C - port map(A => \op1[13]\, B => ldbp1_1, C => \data_0[13]\, Y - => N437_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I76_Y : OA1 - port map(A => \op2[8]\, B => \un1_iu0_6[8]\, C => N425_1, Y - => N535_0); - - \r.x.data_0_RNO_5[6]\ : OR2A - port map(A => data_0_0_30, B => rdata_0_sqmuxa, Y => - \dco_m_i[126]\); - - \r.w.s.wim_RNID5RD2[7]\ : OR2B - port map(A => \wim[7]\, B => aluresult_13_sqmuxa, Y => - \wim_m[7]\); - - \r.f.pc_RNI46M784[9]\ : MX2 - port map(A => I_38, B => N_4052, S => bpmiss_1_i_0_0, Y => - \pc_4[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I8_G0N : NOR3A - port map(A => \op1[7]\, B => ldbp1_2, C => \data_0_2[7]\, Y - => N418_0); - - \r.d.cnt_RNIFET3_1[0]\ : NOR2 - port map(A => \cnt_0[1]\, B => \cnt_2[0]\, Y => un54_casaen); - - \r.x.data_0_RNIAJ33[0]\ : XOR2 - port map(A => \data_0[0]\, B => invop2, Y => N_3304); - - \r.a.ctrl.inst_RNI9U6G3[20]\ : AOI1B - port map(A => aluop_1_1_0_a5_0_0, B => N_209, C => N_345, Y - => aluop_1_1_0_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I126_Y\ : AO1 - port map(A => N491, B => N488_1, C => N487_1, Y => N546_1); - - \r.f.pc_RNIC2JOI4[8]\ : NOR2B - port map(A => \un6_fe_npc_m[6]\, B => - \xc_trap_address_m[8]\, Y => \npc_iv_2[8]\); - - \r.e.op2_RNO_6[15]\ : OR2B - port map(A => data2(15), B => d25_0, Y => \rfo_m_i[47]\); - - \r.e.aluop_0_RNIB4D85[0]\ : MX2C - port map(A => N_3589, B => N_3653, S => \aluop_0[0]\, Y => - \logicout[30]\); - - \r.e.op2_RNIM7MB1[12]\ : OR2A - port map(A => \un1_iu0_5[78]\, B => \un1_iu0_6[12]\, Y => - \logicout_4[12]\); - - \r.m.result_RNIEFD4[19]\ : OR2B - port map(A => d13_0, B => \maddress[19]\, Y => - \result_m_0[19]\); - - \r.e.op2[5]\ : DFN1E0 - port map(D => N_289, CLK => lclk_c, E => holdn, Q => - \op2[5]\); - - \r.m.casa_RNIB08P582\ : OR2B - port map(A => \un17_casaen_0_0\, B => un1_addout, Y => - un17_casaen); - - \r.e.ctrl.inst[23]\ : DFN1E0 - port map(D => \inst_1[23]\, CLK => lclk_c, E => holdn, Q - => \inst_0[23]\); - - \r.e.op2_RNO_2[6]\ : NOR3C - port map(A => \d_1_iv_1[6]\, B => \d_1_iv_0[6]\, C => - \rfo_m_i[38]\, Y => \d_1_iv_3[6]\); - - \r.e.op1_RNO[2]\ : MX2 - port map(A => \d[2]\, B => \d[3]\, S => N_227_0, Y => - \aop1[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I281_Y_0\ : XOR2 - port map(A => N710, B => ADD_30x30_fast_I281_Y_0_0, Y => - \tmp[23]\); - - \r.m.y_RNO_4[4]\ : OR2B - port map(A => \y_2[5]\, B => mulstep_0, Y => \y_m[5]\); - - \r.a.rsel1_RNIJC5DK3[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[13]\, Y => - \aluresult_m_0[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I81_Y : OR2 - port map(A => N415_1, B => I81_un1_Y, Y => N540_0); - - \r.x.ctrl.rd[5]\ : DFN1E0 - port map(D => \rd_2[5]\, CLK => lclk_c, E => holdn, Q => - \rd_0[5]\); - - \r.e.shcnt_RNIGI26F[2]\ : MX2 - port map(A => \shiftin_11[36]\, B => \shiftin_11[32]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[32]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I143_Y : AO1 - port map(A => N544_0, B => N541_0, C => N540, Y => N606_0); - - \r.d.pc[19]\ : DFN1 - port map(D => \pc_RNO[19]\, CLK => lclk_c, Q => \dpc[19]\); - - \r.f.pc_RNO_2[13]\ : OR2B - port map(A => I_66, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[11]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I271_un1_Y_0 : NOR2B - port map(A => N665, B => N614_0, Y => - ADD_33x33_fast_I271_un1_Y_0); - - \r.e.aluop_0_RNIL8ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[13]\, B => \aluop_0[1]\, C => - \un1_iu0_5[79]\, Y => N_6898); - - un6_ex_add_res_d0_ADD_33x33_fast_I199_Y : AO1 - port map(A => N610_1, B => N603, C => N602, Y => N668_1); - - \r.e.op1_RNIK2CR1[13]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[13]\, Y => - \ex_op1_i_m[13]\); - - \r.a.ctrl.inst_RNIE8Q8[28]\ : XOR2 - port map(A => \inst_1[28]\, B => \icc_0[2]\, Y => branch_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I123_Y\ : OR2B - port map(A => N488_1, B => N484_1, Y => N543); - - \r.m.result[20]\ : DFN1E0 - port map(D => \eres2[20]\, CLK => lclk_c, E => holdn, Q => - \maddress[20]\); - - \r.e.op1_RNIU4UH[12]\ : MX2 - port map(A => \op1[12]\, B => \data_0_2[12]\, S => ldbp1_1, - Y => \un1_iu0_6[12]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I41_Y : MAJ3 - port map(A => \op2[26]\, B => \un1_iu0_6[26]\, C => N472_0, - Y => N500_1); - - \r.w.s.y[11]\ : DFN1E0 - port map(D => N_3775, CLK => lclk_c, E => N_6922_i_0, Q => - \y[11]\); - - \r.d.inst_0_RNO_0[9]\ : MX2 - port map(A => data_0_0_9, B => \inst_0[9]\, S => - mexc_1_sqmuxa_1_0, Y => N_4609); - - \r.e.op1_RNI0FNF[23]\ : NOR2A - port map(A => un17_casaen_0, B => \op1[23]\, Y => - \op1_i_m[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I17_G0N\ : OR2B - port map(A => \inst_0[17]\, B => \dpc[19]\, Y => N409_2); - - \r.e.op2_RNO_7[17]\ : OR3C - port map(A => d28_0, B => \rsel2_1[0]\, C => - \un1_p0_6[369]\, Y => \cpi_m_i[369]\); - - \r.e.op1_RNI4MBT4[16]\ : AO1A - port map(A => \bpdata[16]\, B => edata_2_sqmuxa, C => - \op1_i_m[16]\, Y => \edata2_0_iv_0[16]\); - - \r.d.cwp_RNO_0[1]\ : MX2 - port map(A => \ncwp[1]\, B => N_4219, S => un1_wcwp, Y => - N_4228); - - \r.e.invop2_0_RNI5B8AV2\ : MX2C - port map(A => \un6_ex_add_res_s2[30]\, B => - \un6_ex_add_res_s0[30]\, S => invop2_0, Y => N_6576); - - \r.e.ctrl.pc[11]\ : DFN1E0 - port map(D => \pc[11]\, CLK => lclk_c, E => holdn, Q => - \pc_2[11]\); - - \r.a.ctrl.pv_RNO\ : NOR2A - port map(A => pv, B => annul_current, Y => ctrl_pv); - - \r.d.annul_RNI8949\ : OR3 - port map(A => tmp, B => annul_1, C => call_hold5_0, Y => - icc_check_bp_1); - - \r.a.ctrl.inst[29]\ : DFN1E0 - port map(D => \inst_0[29]\, CLK => lclk_c, E => holdn, Q - => \inst[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I26_P0N\ : OR2 - port map(A => \inst_0_1[28]\, B => \dpc[28]\, Y => N437_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I58_Y : OR2B - port map(A => N452_1, B => N449_0, Y => N517_1); - - \r.e.ldbp2_2_RNIT8T365\ : MX2 - port map(A => \un6_ex_add_res_s1[32]\, B => N_6659, S => - ldbp2_2, Y => \eaddress[31]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I173_Y : AO1 - port map(A => N584, B => N577, C => N576_0, Y => N642); - - \r.e.ldbp2_1_RNIL7Q55\ : MX2C - port map(A => \un6_ex_add_res_s1_i[3]\, B => N_6642, S => - ldbp2_1, Y => ldbp2_1_RNIL7Q55); - - un6_ex_add_res_d1_ADD_33x33_fast_I312_Y_0_0 : XOR2 - port map(A => \op2[21]\, B => \un1_iu0_6[21]\, Y => - ADD_33x33_fast_I312_Y_0_0); - - \r.x.ctrl.pc_RNI1QN9[28]\ : MX2 - port map(A => \pc_0[28]\, B => \pc_2[28]\, S => \npc[1]\, Y - => N_3239); - - un6_ex_add_res_d2_ADD_33x33_fast_I205_un1_Y : OR2A - port map(A => N552_1, B => N611, Y => I205_un1_Y); - - \r.f.pc_RNO[9]\ : OR3C - port map(A => \tmp_m[9]\, B => \pc_1_iv_1[9]\, C => - \un6_fe_npc_m[7]\, Y => \pc_1[9]\); - - \r.e.shleft_RNIP6FC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[24]\, S => - shleft, Y => \shiftin_5[55]\); - - \r.a.ctrl.inst_RNIDG1E_1[21]\ : OR2 - port map(A => \inst_2[21]\, B => \inst_2[19]\, Y => N_225); - - un6_ex_add_res_d2_ADD_33x33_fast_I87_Y_0 : AO1 - port map(A => N407_1, B => N403_2, C => N406_1, Y => N546_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I245_Y : OR2 - port map(A => N660_1, B => I245_un1_Y, Y => N802_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I27_P0N : OR3A - port map(A => \data_0[26]\, B => \op1[26]\, C => ldbp1_3, Y - => N476_1); - - \r.m.result_RNIS9JM[9]\ : AOI1B - port map(A => d13_0, B => \maddress[9]\, C => \d_iv_0[9]\, - Y => \d_iv_1[9]\); - - \r.w.s.dwt_RNO_3\ : NOR3B - port map(A => \inst_1[29]\, B => \inst[25]\, C => - \inst[28]\, Y => dwt_1_sqmuxa_2); - - \r.w.s.wim_RNIEF4N2[4]\ : MX2 - port map(A => \wim[4]\, B => \result[4]\, S => wim_1_sqmuxa, - Y => \wim_1[4]\); - - \r.a.ctrl.inst_RNICP4O1[23]\ : OR3B - port map(A => illegal_inst37_4, B => aluop_2_1_0_a2_0, C - => N_472, Y => illegal_inst_7_iv_2_0_a5_4_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I10_P0N : OR3A - port map(A => \data_0[9]\, B => \op1[9]\, C => ldbp1, Y => - N425_0); - - \r.w.s.y[14]\ : DFN1E0 - port map(D => N_153, CLK => lclk_c, E => holdn, Q => - \y[14]\); - - \r.e.ctrl.inst[31]\ : DFN1E0 - port map(D => \inst[31]\, CLK => lclk_c, E => holdn, Q => - \inst_2[31]\); - - \r.a.rsel1_0_RNIQ08M2[2]\ : OR2B - port map(A => data1(2), B => d11_0, Y => \rfo_m[2]\); - - \r.e.op1_RNIE0J494[16]\ : NOR3C - port map(A => \op1_m_0[16]\, B => \d_iv_2[16]\, C => - \aluresult_m_0[16]\, Y => \d_i[16]\); - - \r.e.op1_RNI3S43N6[24]\ : AOI1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[24]\, C - => \d_iv_3[24]\, Y => \d_i[24]\); - - \r.m.ctrl.rd_RNI4MFE2[6]\ : XNOR2 - port map(A => \un3_de_ren1[105]\, B => \rd_1[6]\, Y => - un1_de_ren1_1_6_i_0); - - \r.a.ctrl.inst_RNIKHI77[20]\ : OR3C - port map(A => aluop_1_1_0_0, B => N_346, C => aluop_1_1_0_2, - Y => \aluop[1]\); - - \r.m.irqen_RNO\ : OR3C - port map(A => trap_2_0, B => un1_trap_0_sqmuxa_5, C => - irqen_1, Y => irqen_0); - - \r.w.result_RNIFPB4[8]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[8]\, Y - => \result_m_0_0[8]\); - - \r.e.op2_RNO[7]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[7]\, Y => N_291); - - \r.e.aluop_0_RNIVOID1[2]\ : XA1 - port map(A => \un1_iu0_5[81]\, B => \aluop_0[2]\, C => - \un1_iu0_6[15]\, Y => N_3542); - - \r.e.shleft_0_RNIBK9C2\ : MX2B - port map(A => \shiftin_5[31]\, B => \shiftin_5[15]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[15]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I119_Y\ : OR2B - port map(A => N484_1, B => N480, Y => N539); - - un6_ex_add_res_d0_ADD_33x33_fast_I61_Y : AO13 - port map(A => N442, B => \un1_iu0_6[16]\, C => \data_0[16]\, - Y => N520_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I13_G0N : NOR2B - port map(A => \un1_iu0_6[12]\, B => \op2[12]\, Y => N433_0); - - \r.x.dci.SIGNED\ : DFN1E0 - port map(D => SIGNED, CLK => lclk_c, E => holdn, Q => - SIGNED_0); - - \r.m.dci.size_RNO_0[0]\ : OR2 - port map(A => N_3356_3, B => N_3758, Y => \size_0[0]\); - - \r.a.su_RNIPLKAI\ : OR2A - port map(A => un1_privileged_inst_1_sqmuxa, B => su_1, Y - => privileged_inst_5); - - \r.d.inst_0_RNIQQ3D[25]\ : OA1C - port map(A => \inst_0[30]\, B => rd_0_sqmuxa, C => - \inst_0[25]\, Y => N_3361); - - \r.d.inst_0_RNIB1HFI[13]\ : NOR3B - port map(A => rfe_0, B => wreg_1, C => un1_rs1, Y => rfe_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_Y\ : AO1B - port map(A => ADD_30x30_fast_I235_un1_Y_0, B => N738, C => - ADD_30x30_fast_I235_Y_2, Y => N700); - - un6_ex_add_res_d0_ADD_33x33_fast_I115_Y : AO1 - port map(A => N516, B => N513_0, C => N512, Y => N578); - - \r.e.op2_RNO_5[11]\ : AOI1B - port map(A => \result[11]\, B => d31_0, C => \imm_m_i[11]\, - Y => \d_1_iv_0[11]\); - - \r.e.jmpl_RNIQBA4F1\ : AOI1B - port map(A => \shiftin_17[13]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[12]\, Y => \aluresult_1_iv_7[12]\); - - \r.x.data_0_RNO_0[12]\ : NOR2B - port map(A => N_3473, B => data_0_12, Y => \dco_m_0[108]\); - - \r.x.ctrl.wy_RNIMKUI_0\ : NOR3 - port map(A => wy_1, B => wy_2, C => wy_0, Y => wy_1_0); - - \r.f.pc_RNO_7[17]\ : MX2 - port map(A => \fpc[17]\, B => \tba[5]\, S => - rstate_6314_d_0, Y => \xc_trap_address[17]\); - - \r.f.pc_RNO_0[18]\ : OR3A - port map(A => \tmp[18]\, B => un2_rstn_5_2, C => - \un2_rstn_5_0_0\, Y => \tmp_m[18]\); - - \r.a.ctrl.rd_RNIOC217[0]\ : NOR2B - port map(A => un2_rs1_NE_5, B => un2_rs1_NE_4, Y => - un2_rs1_NE_i_0); - - \r.a.ctrl.pc[9]\ : DFN1E0 - port map(D => \dpc[9]\, CLK => lclk_c, E => holdn, Q => - \pc_0[9]\); - - \r.x.ctrl.pc_RNIGOI61[27]\ : MX2C - port map(A => \un1_p0_6[379]\, B => \pc_3[27]\, S => - s_3_sqmuxa, Y => N_3418); - - \r.e.op2[23]\ : DFN1E0 - port map(D => N_307, CLK => lclk_c, E => holdn, Q => - \op2[23]\); - - \r.e.op1_RNI9RN8[2]\ : MX2 - port map(A => \op1[2]\, B => \data_0[2]\, S => ldbp1_2, Y - => \un1_iu0_6[2]\); - - \r.e.op1_RNIB9KOA[9]\ : NOR3 - port map(A => \bpdata_i_m_2[1]\, B => \edata2_0_iv_0[9]\, C - => \bpdata_i_m[9]\, Y => edata2_0_iv(9)); - - \r.e.ctrl.wicc\ : DFN1E0 - port map(D => wicc_1_0, CLK => lclk_c, E => holdn, Q => - wicc_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I145_Y : OR2 - port map(A => ADD_33x33_fast_I145_Y_0, B => I145_un1_Y, Y - => N608_1); - - \r.e.op1_RNO[7]\ : MX2C - port map(A => \d_i[7]\, B => \d_i[8]\, S => N_227_0, Y => - \aop1[7]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I294_Y_0 : XOR3 - port map(A => \un1_iu0_6[3]\, B => \op2[3]\, C => N614_0, Y - => \un6_ex_add_res_s1[4]\); - - \r.d.inst_0_RNI8446[19]\ : NOR3C - port map(A => \inst_0[19]\, B => \inst_0_0[22]\, C => - N_3515_1, Y => icc_check8_1); - - \r.e.aluop[1]\ : DFN1E0 - port map(D => \aluop[1]\, CLK => lclk_c, E => holdn, Q => - \aluop_3[1]\); - - \r.x.y[23]\ : DFN1E0 - port map(D => \y[23]\, CLK => lclk_c, E => holdn, Q => - \y_2[23]\); - - \r.e.jmpl_RNI3A18F1\ : AOI1B - port map(A => \shiftin_17[12]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[11]\, Y => \aluresult_1_iv_8[11]\); - - \r.x.ctrl.inst_RNI2TRS1[22]\ : NOR3B - port map(A => tba_610_e_3, B => tba_610_e_2, C => annul_1_0, - Y => tba_610_e_5); - - \r.e.ctrl.tt_RNO_1[0]\ : NOR2A - port map(A => N_16684_tz_tz, B => trap_4_1, Y => - tt_9_0_1862_0); - - \r.w.result[15]\ : DFN1E0 - port map(D => \wdata[15]\, CLK => lclk_c, E => holdn, Q => - \result[15]\); - - \r.e.ctrl.annul_RNIDKHT5\ : NOR3B - port map(A => rst, B => \hold_pc_7\, C => jump_0, Y => - branch_1_m7_1); - - \r.a.imm_RNO[5]\ : NOR2B - port map(A => \inst_0[5]\, B => call_hold5, Y => - \un3_de_ren1[123]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I3_P0N : OR3A - port map(A => \data_0[2]\, B => \op1[2]\, C => ldbp1_2, Y - => N404_2); - - \r.e.aluop_RNI143R4[2]\ : OR2A - port map(A => aluresult_5_sqmuxa, B => \bpdata[14]\, Y => - \aluop_RNI143R4[2]\); - - \r.d.inst_0_RNI5DOH[17]\ : MX2 - port map(A => \inst_0[17]\, B => \inst_0[28]\, S => rs1mod, - Y => \un3_de_ren1[94]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I97_un1_Y : OR3B - port map(A => N482_1, B => N485, C => N498_i, Y => - ADD_33x33_fast_I97_un1_Y); - - \r.e.aluop_RNI7NNF[1]\ : OR2B - port map(A => \aluop_1[2]\, B => \aluop_3[1]\, Y => - miscout140_1); - - \r.e.op1_RNIQ1BT4[22]\ : AO1A - port map(A => \bpdata[22]\, B => edata_2_sqmuxa, C => - \op1_i_m[22]\, Y => \edata2_0_iv_0[22]\); - - \r.e.shleft_0_RNI5DIP\ : OR2A - port map(A => \op1_RNID1VH[19]\, B => shleft_0, Y => - \shiftin_5[19]\); - - \r.m.result_RNINV3I[0]\ : OA1A - port map(A => \maddress[0]\, B => d27, C => \cpi_m_i[352]\, - Y => \d_1_iv_1[0]\); - - \r.e.shcnt_RNIV330Q[1]\ : MX2C - port map(A => \shiftin_14[21]\, B => \shiftin_14[19]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[19]\); - - \r.e.op2_RNIE8NB1_0[25]\ : OR2 - port map(A => \un1_iu0_6[25]\, B => \un1_iu0_5[91]\, Y => - \logicout_3[25]\); - - \r.a.ctrl.inst_RNIB41E[23]\ : OR2B - port map(A => \inst_1[24]\, B => \inst_1[23]\, Y => N_216); - - \r.a.ctrl.inst[21]\ : DFN1E0 - port map(D => \inst_0_0[21]\, CLK => lclk_c, E => holdn, Q - => \inst_2[21]\); - - \r.x.ctrl.inst[30]\ : DFN1E0 - port map(D => \inst_1[30]\, CLK => lclk_c, E => holdn, Q - => \inst_3[30]\); - - \r.e.shleft_0_RNIPL9A3\ : MX2 - port map(A => \shiftin_5[54]\, B => \shiftin_5[38]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[38]\); - - \r.e.aluop_0_RNI91JD1[2]\ : XA1 - port map(A => \un1_iu0_5[91]\, B => \aluop_0[2]\, C => - \un1_iu0_6[25]\, Y => N_3552); - - \r.f.pc_RNO_3[22]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[22]\, C => - \xc_trap_address_m[22]\, Y => \pc_1_iv_0[22]\); - - \r.e.shleft_1_RNIPBVI2\ : MX2B - port map(A => \shiftin_5[37]\, B => \shiftin_5[21]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[21]\); - - \r.d.inst_0_RNI3RUM[3]\ : NOR2B - port map(A => \inst_0[3]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI3RUM[3]\); - - \r.x.data_0[12]\ : DFN1E0 - port map(D => \data_0_1[12]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_2[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I3_G0N\ : OR2B - port map(A => \inst_0_RNI3RUM[3]\, B => \dpc[5]\, Y => N367); - - \r.w.result_RNIMOV6[4]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => - \result_0[4]\, Y => \result_m_0[4]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I175_Y : AOI1 - port map(A => N586_1, B => N579_2, C => N578_1, Y => N644); - - un6_ex_add_res_d2_ADD_33x33_fast_I311_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[20]\, B => \data_0_2[20]\, Y => - \un6_ex_add_res_s2_1[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I84_Y : OA1A - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N410_0, - Y => N543_0); - - \r.m.result_RNO[18]\ : MX2 - port map(A => \aluresult[18]\, B => \op1[18]\, S => - un17_casaen_0_2, Y => \eres2[18]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I113_un1_Y : NOR3C - port map(A => N458, B => N461_0, C => N514_1, Y => - I113_un1_Y); - - \comb.v.f.pc_1_iv_RNO_0[3]\ : AND2 - port map(A => \tmp_m[3]\, B => \pc_1_iv_1[3]\, Y => - \pc_1_iv_2[3]\); - - \r.x.result_RNIAELJ3[30]\ : MX2C - port map(A => \un1_iu0_6[30]\, B => \un1_p0_6[382]\, S => - bpdata6, Y => \bpdata[30]\); - - \r.f.pc_RNIMGQQE3[5]\ : AOI1B - port map(A => I_13, B => un2_rstn_4_0_0, C => - \xc_trap_address_m[5]\, Y => \npc_iv_2[5]\); - - \r.e.aluop_1_RNIL7KO1[1]\ : OR2B - port map(A => aluresult_9_sqmuxa, B => aluresult_8_sqmuxa_i, - Y => \aluresult_4[1]\); - - \r.x.y[20]\ : DFN1E0 - port map(D => \y_0[20]\, CLK => lclk_c, E => holdn, Q => - \y_2[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I63_Y_0_a3 : OR3C - port map(A => \data_0[14]\, B => \un1_iu0_6[14]\, C => - N443_1, Y => N_53_i); - - \r.m.ctrl.pc[21]\ : DFN1E0 - port map(D => \pc_0[21]\, CLK => lclk_c, E => holdn, Q => - \pc_3[21]\); - - \r.m.result[6]\ : DFN1E0 - port map(D => \eres2[6]\, CLK => lclk_c, E => holdn, Q => - \maddress[6]\); - - \r.a.bp\ : DFN1E0 - port map(D => bp_1, CLK => lclk_c, E => holdn, Q => bp); - - \r.x.data_0_RNO_0[9]\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_0, B => mcdo_m_0_7, C => - N_3473, Y => \dco_m_0[105]\); - - \r.e.op2_RNO[4]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[4]\, Y => N_288); - - un6_ex_add_res_d0_ADD_33x33_fast_I49_Y : AO13 - port map(A => N460_1, B => \un1_iu0_6[22]\, C => - \data_0_0[22]\, Y => N508_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I38_Y\ : AO13 - port map(A => N427, B => \dpc[26]\, C => \inst_0_1[26]\, Y - => N455); - - \r.m.result[15]\ : DFN1E0 - port map(D => \eres2[15]\, CLK => lclk_c, E => holdn, Q => - \maddress[15]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I134_un1_Y\ : NOR2B - port map(A => N499, B => N496_2, Y => I134_un1_Y); - - \r.e.op2_RNIE8NB1[25]\ : OR2A - port map(A => \un1_iu0_5[91]\, B => \un1_iu0_6[25]\, Y => - \logicout_4[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I62_Y\ : OR2A - port map(A => I62_un1_Y_i, B => N394, Y => N479_0); - - \r.m.y_RNO[12]\ : OR3C - port map(A => \y_iv_1[12]\, B => \y_iv_0[12]\, C => - \logicout_m[12]\, Y => \y_1[12]\); - - \r.a.imm_RNO[4]\ : NOR2B - port map(A => \inst_0_RNI4VUM[4]\, B => call_hold5, Y => - \un3_de_ren1[122]\); - - \r.f.pc_RNO_6[15]\ : MX2 - port map(A => \fpc[15]\, B => \eaddress[15]\, S => jump_0, - Y => N_4058); - - \r.f.pc_RNIE0J51[10]\ : MX2 - port map(A => \fpc[10]\, B => \xc_vectt_1[6]\, S => - rstate_6314_d, Y => \xc_trap_address[10]\); - - \r.a.ctrl.rd_RNIND3G3[4]\ : NOR3C - port map(A => un2_rs1_5_i, B => un2_rs1_4_i, C => - un2_rs1_NE_1, Y => un2_rs1_NE_4); - - \r.a.ctrl.pc_RNIGRD2C[10]\ : MX2 - port map(A => \pc_3[10]\, B => N_3887, S => ex_bpmiss_1, Y - => \fe_pc[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I65_un1_Y : AND2 - port map(A => N436, B => N440, Y => I65_un1_Y); - - \r.e.op1[3]\ : DFN1E0 - port map(D => \aop1[3]\, CLK => lclk_c, E => holdn, Q => - \op1[3]\); - - \r.e.op2_RNIS7MB1_0[21]\ : NOR2 - port map(A => \un1_iu0_6[21]\, B => \un1_iu0_5[87]\, Y => - \logicout_4[21]\); - - \r.a.ctrl.pc[12]\ : DFN1E0 - port map(D => \dpc[12]\, CLK => lclk_c, E => holdn, Q => - \pc[12]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I12_P0N : OR3A - port map(A => \data_0_2[11]\, B => \op1[11]\, C => ldbp1, Y - => N431_0); - - \r.m.ctrl.inst_RNI1T0E[23]\ : OR2B - port map(A => \inst_2[23]\, B => \inst_2[22]\, Y => - trap_0_sqmuxa_1_1_i); - - \r.e.ctrl.rd[0]\ : DFN1E0 - port map(D => \rd_2[0]\, CLK => lclk_c, E => holdn, Q => - \rd[0]\); - - \r.x.data_0_RNO_3[7]\ : OR2B - port map(A => rdata_2_sqmuxa, B => data_0_0_15, Y => - \dco_m_i[111]\); - - \r.d.inst_0_RNIV2072[4]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum[0]\, B => un1_reg, - Y => \un3_de_ren1[103]\); - - \r.e.op2_RNO_3[23]\ : NOR3C - port map(A => \result_m_i[23]\, B => \imm_m_i[23]\, C => - \d_1_iv_1[23]\, Y => \d_1_iv_2[23]\); - - \r.e.ctrl.rd_RNIF29A2[4]\ : XNOR2 - port map(A => \un3_de_ren1[103]\, B => \rd_0[4]\, Y => - un1_de_ren1_4_i_0); - - \r.e.shcnt_RNIHNTNM[1]\ : MX2C - port map(A => \shiftin_14[13]\, B => \shiftin_14[11]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[11]\); - - \r.e.ctrl.trap_RNIIHVT1\ : OR2A - port map(A => jump_0_sqmuxa_1_2, B => jump_0_sqmuxa, Y => - jump_0_sqmuxa_1_i_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I1_P0N : OR3A - port map(A => \data_0[0]\, B => \op1[0]\, C => ldbp1_0, Y - => N398); - - \r.f.pc_RNO_6[22]\ : MX2 - port map(A => \fpc[22]\, B => \eaddress[22]\, S => jump, Y - => N_4065); - - \r.e.shcnt_RNIBFEG[4]\ : MX2C - port map(A => \shcnt[4]\, B => N_3308, S => ldbp2_0, Y => - \ex_shcnt_1_i_0[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I45_Y : AO18 - port map(A => N466_1, B => \un1_iu0_6[24]\, C => - \data_0[24]\, Y => N504_1); - - \r.x.data_0_RNI4JS8[3]\ : XOR2 - port map(A => \data_0[3]\, B => invop2_0, Y => N_3307); - - \r.m.y_RNO_4[15]\ : OR2B - port map(A => \y[16]\, B => mulstep_0, Y => \y_m[16]\); - - \r.m.y_RNO_2[17]\ : OR2B - port map(A => \y[17]\, B => y08, Y => \y_m_0[17]\); - - \r.f.pc_RNO_5[19]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[19]\, Y => \xc_trap_address_m[19]\); - - \r.a.ctrl.rd_RNIH0CV[4]\ : XNOR2 - port map(A => \rd_1[4]\, B => \un3_de_ren1[95]\, Y => - un2_rs1_4_i); - - \r.f.pc_RNO_4[21]\ : MX2 - port map(A => I_122, B => N_4064, S => bpmiss_1_i_0_0, Y - => \pc_4[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I130_Y_0 : AND2 - port map(A => N431_0, B => N428_0, Y => - ADD_33x33_fast_I130_Y_0); - - \r.m.icc_RNO_1[2]\ : MX2C - port map(A => \logicout[22]\, B => \icc_16[2]\, S => - un3_op_i, Y => N_4177); - - \r.e.aluop_RNI7GQF4[1]\ : OR2B - port map(A => \bpdata[20]\, B => aluresult_6_sqmuxa, Y => - \bpdata_m[20]\); - - \r.a.ctrl.inst_RNIODC7I[31]\ : AO1C - port map(A => N_212, B => un1_illegal_inst33, C => - privileged_inst_1_sqmuxa, Y => - un1_privileged_inst_1_sqmuxa); - - \r.e.op2_RNO_5[20]\ : OR2B - port map(A => \result_0[20]\, B => d31, Y => - \result_m_i[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I191_Y : AO1 - port map(A => N602, B => N595_1, C => N594_0, Y => N660); - - \r.m.y_RNO_4[30]\ : OR3A - port map(A => \y_2[30]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[30]\); - - \r.x.result[18]\ : DFN1E0 - port map(D => \maddress[18]\, CLK => lclk_c, E => holdn, Q - => \result_0[18]\); - - \r.w.s.wim[3]\ : DFN1E0 - port map(D => \wim_1[3]\, CLK => lclk_c, E => holdn, Q => - \wim[3]\); - - \r.m.y_RNIBINI4[16]\ : NOR3C - port map(A => \ex_op2_m[16]\, B => aluresult_8_sqmuxa_i, C - => \aluresult_1_iv_1[16]\, Y => \aluresult_1_iv_2[16]\); - - \r.e.aluop_RNI6F7OM[0]\ : AOI1B - port map(A => \logicout[19]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_5[19]\, Y => \aluresult_1_iv_6[19]\); - - \r.d.inst_0_RNIPQUJ[21]\ : AO1 - port map(A => wy_1_0_a3_1_0, B => N_142, C => inst_0_2, Y - => \inst_0_RNIPQUJ[21]\); - - \r.x.result[8]\ : DFN1E0 - port map(D => \maddress[8]\, CLK => lclk_c, E => holdn, Q - => \result[8]\); - - \r.x.npc_0_RNIS6KU[0]\ : MX2C - port map(A => N_3219, B => N_3249, S => \npc_0[0]\, Y => - \xc_result[8]\); - - \r.a.imm[13]\ : DFN1E0 - port map(D => \un3_de_ren1[131]\, CLK => lclk_c, E => holdn, - Q => \imm[13]\); - - \r.m.result_RNO[11]\ : MX2 - port map(A => \aluresult[11]\, B => \op1[11]\, S => - un17_casaen_0_2, Y => \eres2[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I242_un1_Y\ : NAND2 - port map(A => N558, B => ADD_30x30_fast_I242_un1_Y_0, Y => - I242_un1_Y); - - \r.w.s.ps_RNO_0\ : MX2 - port map(A => ps_1, B => ps, S => holdn, Y => N_4993); - - un6_ex_add_res_d1_ADD_33x33_fast_I261_Y_2 : OA1A - port map(A => N629, B => N644, C => ADD_33x33_fast_I261_Y_1, - Y => ADD_33x33_fast_I261_Y_2_0); - - \r.e.op1_RNI9PUH[17]\ : MX2 - port map(A => \op1[17]\, B => \data_0[17]\, S => ldbp1_2, Y - => \un1_iu0_6[17]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I197_Y : AO1 - port map(A => N608_1, B => N601, C => N600_1, Y => N666_1); - - \r.e.ctrl.inst_RNIQSQF[25]\ : NOR3B - port map(A => \inst_2[25]\, B => \inst_1[27]\, C => - \icc_0[0]\, Y => ex_bpmiss_1_0_a5_6_0); - - \r.a.ctrl.ld\ : DFN1E0 - port map(D => ld_2, CLK => lclk_c, E => holdn, Q => ld_1); - - \r.w.s.tba[7]\ : DFN1E1 - port map(D => \result_0[19]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[7]\); - - \r.a.ctrl.inst_RNI293H1[22]\ : OR3B - port map(A => N_472, B => N_6681_1, C => N_212, Y => - cp_disabled_8_sqmuxa_1); - - \r.d.inst_0_RNIF423_0[29]\ : NOR2B - port map(A => \inst_0[28]\, B => \inst_0[29]\, Y => - annul_next_1_sqmuxa_1_2); - - \r.x.data_0_RNO_1[29]\ : NOR2A - port map(A => \data_0_0[29]\, B => ld_3, Y => - \data_0_m[29]\); - - \r.x.icc_RNI9SID[0]\ : MX2 - port map(A => \icc[0]\, B => \icc_2[0]\, S => wicc, Y => - N_4180); - - \r.m.y_RNO_0[28]\ : NOR3C - port map(A => \y_m[29]\, B => \y_m_0[28]\, C => - \y_iv_1[28]\, Y => \y_iv_2[28]\); - - \r.a.imm[30]\ : DFN1E0 - port map(D => \un3_de_ren1[148]\, CLK => lclk_c, E => holdn, - Q => \imm[30]\); - - \r.w.s.y_RNO_2[18]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[18]\, Y - => N_392); - - \r.f.pc_RNO[16]\ : OR3C - port map(A => \tmp_m[16]\, B => \pc_1_iv_1[16]\, C => - \un6_fe_npc_m[14]\, Y => \pc_1[16]\); - - \r.e.op2_RNO_4[31]\ : OA1A - port map(A => \maddress[31]\, B => d27_0, C => - \cpi_m_i[383]\, Y => \d_1_iv_1[31]\); - - \r.a.ctrl.rd_RNIQGFK1[2]\ : XA1A - port map(A => \rd[2]\, B => \inst_0_RNI2NUM[2]\, C => - un1_de_ren1_3_i, Y => un1_de_ren1_NE_1); - - \r.e.op1_RNI09UH[13]\ : MX2 - port map(A => \op1[13]\, B => \data_0[13]\, S => ldbp1_1, Y - => \un1_iu0_6[13]\); - - \r.x.ctrl.rd_RNIC2NU[5]\ : MX2 - port map(A => \cwp_0[1]\, B => \rd_0[5]\, S => N_6357, Y - => waddr(5)); - - \comb.branch_address.tmp_ADD_30x30_fast_I232_Y_2\ : NOR3C - port map(A => I86_un1_Y, B => ADD_30x30_fast_I232_Y_0, C - => I140_un1_Y_i, Y => ADD_30x30_fast_I232_Y_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I292_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[1]\, B => \data_0[1]\, Y => - \un6_ex_add_res_s2_1[2]\); - - \r.e.aluop_1_RNIAG093[1]\ : MX2C - port map(A => \logicout_4[31]\, B => N_6916, S => N_6866_i, - Y => N_3654); - - \r.x.ctrl.inst_RNI893A1[21]\ : NOR3B - port map(A => y6_0, B => y10_3_0, C => y11_0, Y => y11); - - \r.m.y_RNI5B6P6[20]\ : NOR3C - port map(A => \cpi_m[165]\, B => \y_m_1[20]\, C => - \bpdata_m[20]\, Y => \aluresult_1_iv_3[20]\); - - \r.e.ldbp2_2_RNIAMVOE\ : MX2C - port map(A => \un6_ex_add_res_s1[7]\, B => N_6646, S => - ldbp2_2, Y => \eaddress[6]\); - - \r.x.ctrl.pc_RNIUT971[15]\ : MX2C - port map(A => \un1_p0_6[367]\, B => \pc_0[15]\, S => - s_3_sqmuxa_0, Y => N_3406); - - \r.x.data_0_RNI97T8[8]\ : XOR2 - port map(A => \data_0[8]\, B => invop2_0, Y => N_4255); - - \r.m.y_RNINF7P6[23]\ : AOI1B - port map(A => \bpdata[23]\, B => aluresult_6_sqmuxa, C => - \aluresult_1_iv_1[23]\, Y => \aluresult_1_iv_3[23]\); - - \r.a.ctrl.inst_RNIDS0S[22]\ : NOR3 - port map(A => \inst_2[20]\, B => \inst[22]\, C => N_201, Y - => cp_disabled_10_sqmuxa_1); - - \r.m.casa_RNIKPD91_0\ : NOR2 - port map(A => un1_logicout21, B => un17_casaen_0, Y => - edata_3_sqmuxa_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I76_Y : NOR2B - port map(A => N425_0, B => N422_0, Y => N535); - - \r.x.ctrl.pc[27]\ : DFN1E0 - port map(D => \pc_2[27]\, CLK => lclk_c, E => holdn, Q => - \pc_3[27]\); - - \r.e.aluop_0_RNI59JD1[1]\ : XOR3 - port map(A => \un1_iu0_6[17]\, B => \aluop_0[1]\, C => - \un1_iu0_5[83]\, Y => N_6877); - - \r.d.pc_RNIGTGB4[10]\ : MX2 - port map(A => \dpc[10]\, B => \fpc[10]\, S => ra_bpmiss_1, - Y => N_3887); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.m.y_RNO[7]\ : AO1C - port map(A => y14_0, B => \logicout[7]\, C => \y_iv_2[7]\, - Y => \y_1[7]\); - - \r.e.op2_RNO_2[24]\ : NOR3C - port map(A => \d_1_iv_1[24]\, B => \d_1_iv_0[24]\, C => - \rfo_m_i[56]\, Y => \d_1_iv_3[24]\); - - \r.m.y_RNO[2]\ : OR3C - port map(A => \y_iv_1[2]\, B => \y_iv_0[2]\, C => - \logicout_m[2]\, Y => \y_1[2]\); - - \r.e.ctrl.pc_RNIRR011[7]\ : OR2B - port map(A => \pc_0[7]\, B => jmpl_4, Y => \cpi_m[152]\); - - \r.a.imm_RNO[31]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[149]\); - - \r.a.et_RNO\ : OR2A - port map(A => su2, B => et_1_0, Y => et_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I278_Y_0\ : XOR2 - port map(A => N716, B => ADD_30x30_fast_I278_Y_0_0, Y => - \tmp[20]\); - - \r.x.icc[2]\ : DFN1E0 - port map(D => \icc_0[2]\, CLK => lclk_c, E => holdn, Q => - \icc_2[2]\); - - \r.x.data_0_RNO[12]\ : OR3 - port map(A => \dco_m_0[108]\, B => \data_0_1_0_iv_0[12]\, C - => \data_0_1_4[9]\, Y => \data_0_1[12]\); - - \r.f.pc_RNI29U6A[3]\ : MX2B - port map(A => \fpc[3]\, B => \eaddress[3]\, S => jump_0, Y - => N_4046); - - \r.x.result_RNI990C3[2]\ : MX2 - port map(A => \un1_iu0_6[2]\, B => \un1_p0_6[354]\, S => - bpdata6_0_0, Y => \bpdata[2]\); - - \r.e.aluop_RNIUIL06[0]\ : MX2C - port map(A => N_3588, B => N_3652, S => \aluop_1[0]\, Y => - \logicout[29]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I90_Y : OA1A - port map(A => \data_0[1]\, B => \un1_iu0_6[1]\, C => N404_2, - Y => N549_0); - - \r.e.op1_RNIHP3M7[6]\ : OR3C - port map(A => \ex_op1_i_m[6]\, B => \op1_i_m[6]\, C => - \bpdata_i_m[6]\, Y => edata2_0_iv(6)); - - \r.m.result_RNIEVPK[4]\ : OA1A - port map(A => \maddress[4]\, B => d27, C => \cpi_m_i[356]\, - Y => \d_1_iv_1[4]\); - - \r.a.imm_RNO[29]\ : MX2 - port map(A => \inst_0[19]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[147]\); - - \r.m.ctrl.wy_RNI3TDC\ : NOR2A - port map(A => wy_1, B => wy_0, Y => y08_0); - - \r.a.ctrl.inst[30]\ : DFN1E0 - port map(D => \inst_0[30]\, CLK => lclk_c, E => holdn, Q - => \inst[30]\); - - \r.w.s.y[0]\ : DFN1E0 - port map(D => N_3764, CLK => lclk_c, E => N_6922_i_0, Q => - \y[0]\); - - \r.m.ctrl.pc[12]\ : DFN1E0 - port map(D => \pc_2[12]\, CLK => lclk_c, E => holdn, Q => - \pc_3[12]\); - - \r.e.ctrl.rd_RNI0KI31[5]\ : XNOR2 - port map(A => \rd[5]\, B => \un3_de_ren1[96]\, Y => - un2_rs1_1_5_i_0); - - \r.e.op2_RNI88NB1[16]\ : OR2A - port map(A => \un1_iu0_5[82]\, B => \un1_iu0_6[16]\, Y => - \logicout_4[16]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I298_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[8]\, B => N672, Y => - \un6_ex_add_res_s2[8]\); - - \comb.lock_gen.un1_icc_check5\ : NAND2 - port map(A => icc_check5, B => un1_icc_check5_2, Y => - un1_icc_check5); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_Y_3 : NOR3C - port map(A => I157_un1_Y_i_0, B => - ADD_33x33_fast_I260_Y_1_0, C => I213_un1_Y_i, Y => - ADD_33x33_fast_I260_Y_3_0); - - \r.e.ctrl.pc[27]\ : DFN1E0 - port map(D => \pc_0[27]\, CLK => lclk_c, E => holdn, Q => - \pc[27]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I39_Y_0_o3 : AOI1 - port map(A => N479_1, B => N475_0, C => N478_1, Y => N498_i); - - \r.w.result_RNI77PF[18]\ : AOI1B - port map(A => \un1_p0_6[370]\, B => d14, C => - \result_m_0_0[18]\, Y => \d_iv_0[18]\); - - \r.m.ctrl.trap_RNIJ6H22\ : NOR2A - port map(A => trap_0_sqmuxa_7, B => trap_2, Y => trap_2_0); - - \r.x.ctrl.wy_RNILF1N3\ : OR2B - port map(A => rstate_9_0, B => y_1_sqmuxa, Y => wy_RNILF1N3); - - \r.e.ctrl.rd[5]\ : DFN1E0 - port map(D => \rd_1[5]\, CLK => lclk_c, E => holdn, Q => - \rd[5]\); - - \r.x.icc_RNIFSID[3]\ : MX2C - port map(A => \icc_0[3]\, B => \icc_2[3]\, S => wicc, Y => - N_4183); - - un6_ex_add_res_d2_ADD_33x33_fast_I78_Y : OA1 - port map(A => \data_0[8]\, B => \un1_iu0_6[8]\, C => N419_0, - Y => N537_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I295_Y_0 : XOR3 - port map(A => \un1_iu0_6[4]\, B => \op2[4]\, C => N678_i, Y - => \un6_ex_add_res_s1_i[5]\); - - \r.m.y_RNO_1[23]\ : AOI1B - port map(A => \y[23]\, B => y08_0, C => \y_m[24]\, Y => - \y_iv_0[23]\); - - \r.d.cwp[2]\ : DFN1E0 - port map(D => \cwp_1[2]\, CLK => lclk_c, E => holdn, Q => - \cwp_0[2]\); - - \r.a.ctrl.pc_RNI6OE2C[25]\ : MX2 - port map(A => \pc_0[25]\, B => N_3902, S => ex_bpmiss_1, Y - => \fe_pc[25]\); - - \r.e.op2_RNIS7MB1[21]\ : NOR2A - port map(A => \un1_iu0_5[87]\, B => \un1_iu0_6[21]\, Y => - \logicout_3[21]\); - - \r.w.s.dwt\ : DFN1E0 - port map(D => N_170, CLK => lclk_c, E => holdn, Q => dwt); - - \comb.branch_address.tmp_ADD_30x30_fast_I274_Y_0_0\ : XOR2 - port map(A => \dpc[16]\, B => \inst_0[14]\, Y => - ADD_30x30_fast_I274_Y_0_0); - - \r.x.data_0_RNO_0[15]\ : NOR2B - port map(A => N_3473, B => data_0_0_15, Y => \dco_m_0[111]\); - - \r.d.inst_0_RNO[7]\ : NOR2B - port map(A => rst, B => N_4607, Y => \inst_0_RNO[7]\); - - \r.x.dci.size_RNISC8C9[0]\ : MX2C - port map(A => \size_1[0]\, B => \size_2[0]\, S => - dco_i_2(132), Y => \me_size_1[0]\); - - \r.e.op2_RNO_4[7]\ : OA1A - port map(A => \maddress[7]\, B => d27_0, C => - \cpi_m_i[359]\, Y => \d_1_iv_1[7]\); - - \r.e.ldbp2_RNIDJSF18\ : OR3C - port map(A => \aluresult_1_iv_8[30]\, B => - \shiftin_17_m_0[30]\, C => \un6_ex_add_res_m[31]\, Y => - \aluresult[30]\); - - \r.x.data_0_RNO_0[26]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_26, Y => - \dco_m_1[122]\); - - \r.e.shleft_RNIVDEF\ : NOR2A - port map(A => \un1_iu0_6[11]\, B => shleft, Y => - \shiftin_5_i[11]\); - - \r.e.ldbp2_RNIPVFHB5\ : OR3C - port map(A => \aluresult_1_iv_7[19]\, B => - \shiftin_17_m_0[19]\, C => \un6_ex_add_res_m[20]\, Y => - \aluresult[19]\); - - \r.a.ctrl.wreg_RNO_4\ : AOI1 - port map(A => write_reg7_0, B => un3_op, C => un1_inst, Y - => write_reg_2_sqmuxa); - - \r.x.result_RNI978B3[1]\ : MX2 - port map(A => \un1_iu0_6[1]\, B => \un1_p0_6[353]\, S => - bpdata6, Y => \bpdata[1]\); - - \r.d.inst_0_RNO[11]\ : NOR2B - port map(A => rst, B => N_4611, Y => \inst_0_RNO[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I52_un1_Y\ : OR3C - port map(A => \dpc[18]\, B => \inst_0[16]\, C => N410, Y - => I52_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I120_Y : NOR2B - port map(A => N521_1, B => N517_0, Y => N583_1); - - \r.x.result_RNIRN9B3[5]\ : MX2 - port map(A => \un1_iu0_6[5]\, B => \un1_p0_6[357]\, S => - bpdata6_0_0, Y => \bpdata[5]\); - - \r.m.result_RNI3R5A3[6]\ : NOR3C - port map(A => \d_iv_0[6]\, B => \result_m_0[6]\, C => - \rfo_m[6]\, Y => \d_iv_2[6]\); - - \r.d.inst_0[21]\ : DFN1 - port map(D => \inst_0_0_0_RNIQ98I03[21]\, CLK => lclk_c, Q - => \inst_0_0[21]\); - - \r.e.op2_RNIKONB1[27]\ : OR2A - port map(A => \un1_iu0_5[93]\, B => \un1_iu0_6[27]\, Y => - \logicout_4[27]\); - - \r.d.pc_RNO[28]\ : MX2 - port map(A => \fpc[28]\, B => \dpc[28]\, S => N_6763_i, Y - => \pc_RNO[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I108_Y : NOR2B - port map(A => N509, B => N505, Y => N571_0); - - \r.e.shcnt_RNI2HUGE[2]\ : MX2C - port map(A => \shiftin_11[33]\, B => \shiftin_11[29]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[29]\); - - \r.w.s.y_RNO[0]\ : MX2 - port map(A => \y_2[0]\, B => \result[0]\, S => N_481_0, Y - => N_3764); - - \r.x.result_RNIS4OE[28]\ : OR2B - port map(A => \un1_p0_6[380]\, B => d14, Y => - \cpi_m_0[380]\); - - \r.w.result[0]\ : DFN1E0 - port map(D => \wdata[0]\, CLK => lclk_c, E => holdn, Q => - \result_0[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I265_Y_0\ : XOR2 - port map(A => N614, B => ADD_30x30_fast_I265_Y_0_0, Y => - \tmp[7]\); - - \r.m.ctrl.trap_RNI2I4IU\ : OR2B - port map(A => tt_2_sqmuxa_1_0, B => un6_annul, Y => - tt_2_sqmuxa_1); - - \r.e.aluop_0_RNI81JD1[1]\ : XOR3 - port map(A => \un1_iu0_6[25]\, B => \aluop_0[1]\, C => - \un1_iu0_5[91]\, Y => N_6856); - - \r.a.ctrl.inst_RNIKK131[20]\ : NOR2 - port map(A => N_216, B => N_204, Y => N_6696); - - un6_ex_add_res_d2_ADD_33x33_fast_I17_P0N : AO1A - port map(A => ldbp1_4, B => \op1[16]\, C => \data_0[16]\, Y - => N446_1); - - \r.d.pc[22]\ : DFN1 - port map(D => \pc_RNO[22]\, CLK => lclk_c, Q => \dpc[22]\); - - \r.d.inst_0_RNO_0[1]\ : MX2 - port map(A => data_0_0_1, B => \inst_0[1]\, S => - mexc_1_sqmuxa_1_0, Y => N_4601); - - \r.m.result_RNI5PB4[8]\ : OR2B - port map(A => d13, B => \maddress[8]\, Y => \result_m_0[8]\); - - \r.e.op2_RNO_1[13]\ : AOI1B - port map(A => \op1[13]\, B => un14_casaen_s1_0_1, C => - \d_1_iv_3[13]\, Y => \d_1_iv_4[13]\); - - \r.d.inst_0_RNI7QTD1[4]\ : OR2 - port map(A => \inst_0_RNI4VUM[4]\, B => \inst_0_RNI3RUM[3]\, - Y => un1_reg); - - \r.m.y_RNO_4[28]\ : OR3A - port map(A => \y_2[28]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[28]\); - - \r.a.rsel1_0_RNIS88M2[2]\ : OR2B - port map(A => data1(4), B => d11_0, Y => \rfo_m[4]\); - - \r.a.imm_RNO[13]\ : MX2 - port map(A => \inst_0_RNI3RUM[3]\, B => \un1_p0_6_0[51]\, S - => call_hold5_0, Y => \un3_de_ren1[131]\); - - \r.e.op1_RNII04F[0]\ : OR2B - port map(A => \op1[0]\, B => un14_casaen_s1, Y => - \op1_m_i[0]\); - - \r.a.imm[18]\ : DFN1E0 - port map(D => \un3_de_ren1[136]\, CLK => lclk_c, E => holdn, - Q => \imm[18]\); - - \r.e.op2_RNIPS4F[4]\ : OR2A - port map(A => \un1_iu0_5[70]\, B => \un1_iu0_6[4]\, Y => - \logicout_4[4]\); - - \r.d.pc[31]\ : DFN1E0 - port map(D => \fpc[31]\, CLK => lclk_c, E => N_6763_i, Q - => \dpc[31]\); - - \r.a.ctrl.wicc_RNO_1\ : AO1 - port map(A => wicc_1_0_a3_1_1_0, B => N_152, C => - wicc_1_0_a3_0, Y => wicc_1_0_tz_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I22_G0N\ : NOR2B - port map(A => \dpc[24]\, B => \inst_0_0_0_RNI9O79[21]\, Y - => N424); - - \r.m.result_RNIAM2A3[1]\ : NOR3C - port map(A => \d_iv_0[1]\, B => \result_m_0[1]\, C => - \rfo_m[1]\, Y => \d_iv_2[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I180_Y : NOR2B - port map(A => N591_1, B => N583_2, Y => N649); - - un6_ex_add_res_d2_ADD_33x33_fast_I27_G0N : NOR2B - port map(A => \un1_iu0_6[26]\, B => \data_0[26]\, Y => - N475_1); - - \r.e.op1_RNI43OF[18]\ : NOR2A - port map(A => un17_casaen_0_1, B => \op1[18]\, Y => - \op1_i_m[18]\); - - \r.e.shcnt_RNIAIVC8[2]\ : MX2C - port map(A => \shiftin_11[5]\, B => \shiftin_11[1]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[1]\); - - \r.e.op2_RNO_5[5]\ : AOI1B - port map(A => \result[5]\, B => d31, C => \imm_m_i[5]\, Y - => \d_1_iv_0[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I307_Y_0 : AX1B - port map(A => N442_1, B => ADD_33x33_fast_I274_Y_0_a3, C - => \un6_ex_add_res_s0_1[17]\, Y => - \un6_ex_add_res_s2[17]\); - - \r.x.mexc_1_sqmuxa_0\ : NOR2A - port map(A => holdn, B => dco_i_2(132), Y => - mexc_1_sqmuxa_0); - - \r.e.sari_RNO\ : NOR3A - port map(A => aluadd_16_sqmuxa_0_a5_1, B => N_205, C => - \d_i[31]\, Y => sari_0); - - \r.e.jmpl_RNIINJV66\ : OR3C - port map(A => \aluresult_1_iv_8[22]\, B => - \shiftin_17_m_0[22]\, C => \un6_ex_add_res_m[23]\, Y => - \aluresult[22]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I118_un1_Y\ : OR2B - port map(A => N483, B => N480, Y => I118_un1_Y_i); - - \r.d.inst_0_RNO_0[6]\ : MX2 - port map(A => data_0_0_6, B => \inst_0[6]\, S => - inull_RNIFV6VG2_0, Y => N_4606); - - \r.a.ctrl.pc_RNIA0L0C[3]\ : MX2 - port map(A => \pc[3]\, B => N_3880, S => ex_bpmiss_1, Y => - \fe_pc[3]\); - - un6_fe_npc_I_173 : XOR2 - port map(A => N_30_1, B => \fe_pc[27]\, Y => I_173); - - \r.m.y_RNO_2[22]\ : OR2A - port map(A => \logicout[22]\, B => y14, Y => - \logicout_m[22]\); - - \r.m.dci.asi_RNO_0[0]\ : MX2 - port map(A => s, B => ps, S => rett_i, Y => su); - - un6_ex_add_res_d2_ADD_33x33_fast_I160_Y : NOR2B - port map(A => N571, B => N563_0, Y => N629_1); - - \r.m.result_RNI9JD4[21]\ : OR2B - port map(A => d13_0, B => \maddress[21]\, Y => - \result_m_0_0[21]\); - - \r.a.rsel1_RNI7R5338[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[31]\, Y => - \aluresult_m_0[31]\); - - un6_fe_npc_I_128 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[14]\, Y => N_61); - - \r.f.pc_RNIIODR76[11]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[11]\, C => - \xc_trap_address_m[11]\, Y => m14_0); - - \r.a.imm_RNO[28]\ : MX2 - port map(A => \inst_0[18]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[146]\); - - \r.m.result_RNI9MI7[1]\ : OR2 - port map(A => \maddress[1]\, B => \maddress[0]\, Y => - result_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I184_Y\ : OR2 - port map(A => N552_2, B => I184_un1_Y, Y => N612); - - \r.e.ctrl.inst_RNIS08H[21]\ : OR2 - port map(A => \inst_1[21]\, B => force_a2_0, Y => - force_a2_1); - - \r.x.ctrl.pc_RNIR1N9[25]\ : MX2 - port map(A => \pc_2[25]\, B => \pc[25]\, S => \npc[1]\, Y - => N_3236); - - \r.a.ctrl.inst_RNIEK1E[22]\ : NOR2B - port map(A => \inst[22]\, B => \inst_2[19]\, Y => N_256_i_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I5_G0N : NOR3A - port map(A => \op1[4]\, B => ldbp1, C => \data_0[4]\, Y => - N409_0); - - \r.e.op2_RNIIONB1[18]\ : OR2A - port map(A => \un1_iu0_5[84]\, B => \un1_iu0_6[18]\, Y => - \logicout_4[18]\); - - \r.f.pc_RNIB83E01[10]\ : MX2 - port map(A => \fpc[10]\, B => \eaddress[10]\, S => jump_0, - Y => N_4053); - - un6_ex_add_res_d2_ADD_33x33_fast_I4_P0N : AO1A - port map(A => ldbp1_4, B => \op1[3]\, C => \data_0[3]\, Y - => N407_1); - - \r.e.shleft_1_RNID40G3\ : MX2 - port map(A => \shiftin_5[50]\, B => \shiftin_5[34]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[34]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I306_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[16]\, B => N796_0, Y => - \un6_ex_add_res_s2[16]\); - - \r.e.shcnt_RNIUNLOQ[1]\ : MX2C - port map(A => \shiftin_14[23]\, B => \shiftin_14[21]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[21]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I232_Y\ : OR3C - port map(A => ADD_30x30_fast_I232_Y_2, B => I190_un1_Y, C - => I232_un1_Y, Y => N694); - - \r.a.ctrl.wy_RNO\ : OA1B - port map(A => wy_1_0_a3_0_4, B => wy_1_0_a3_1, C => N_143, - Y => wy_1_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I121_Y_0 : MAJ3 - port map(A => \data_0[17]\, B => \un1_iu0_6[17]\, C => N445, - Y => ADD_33x33_fast_I121_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I301_Y_0 : XNOR2 - port map(A => N811, B => \un6_ex_add_res_s2_1[11]\, Y => - \un6_ex_add_res_s0[11]\); - - \r.e.op2_RNO_4[20]\ : NOR3C - port map(A => \result_m_i[20]\, B => \imm_m_i[20]\, C => - \d_1_iv_1[20]\, Y => \d_1_iv_2[20]\); - - \r.f.pc_RNO_0[23]\ : NAND2 - port map(A => \tmp[23]\, B => un2_rstn_5_0, Y => - \tmp_m[23]\); - - \r.e.aluop_0_RNI0544G1[0]\ : NOR3C - port map(A => \aluresult_1_iv_5[16]\, B => - \logicout_m_0[16]\, C => \shiftin_17_m[17]\, Y => - \aluresult_1_iv_7[16]\); - - \r.e.op2_RNO_4[6]\ : OA1A - port map(A => \maddress[6]\, B => d27, C => \cpi_m_i[358]\, - Y => \d_1_iv_1[6]\); - - \r.e.shcnt_RNIQG5R3[3]\ : MX2 - port map(A => \shiftin_8[8]\, B => \shiftin_8[0]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[0]\); - - \r.x.result_RNIEGQL8[0]\ : MX2C - port map(A => \result[0]\, B => N_6527, S => cwp_1_sqmuxa_0, - Y => N_3870); - - \r.e.op2_RNO_8[17]\ : OR3B - port map(A => d29_0, B => \imm[17]\, C => \rsel2_1[0]\, Y - => \imm_m_i[17]\); - - \r.f.pc[20]\ : DFN1E0 - port map(D => \pc_1[20]\, CLK => lclk_c, E => holdn, Q => - \fpc[20]\); - - \r.e.op2[17]\ : DFN1E0 - port map(D => N_301, CLK => lclk_c, E => holdn, Q => - \op2[17]\); - - \r.d.inst_0_RNO[14]\ : NOR2B - port map(A => rst, B => N_4614, Y => \inst_0_RNO[14]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I2_P0N : OR2 - port map(A => \un1_iu0_6[1]\, B => \op2[1]\, Y => N401_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I137_Y : AO1 - port map(A => N538, B => N535, C => ADD_33x33_fast_I137_Y_0, - Y => N600); - - \r.m.y[5]\ : DFN1E0 - port map(D => \y_0[5]\, CLK => lclk_c, E => holdn, Q => - \y_2[5]\); - - \r.m.dci.asi[0]\ : DFN1E0 - port map(D => \asi[0]\, CLK => lclk_c, E => holdn, Q => - asi_0(0)); - - \r.e.shleft_RNIQ7CF1\ : MX2A - port map(A => \shiftin_5[27]\, B => \shiftin_5_i[11]\, S - => \ex_shcnt_1_i[4]\, Y => \shiftin_8[11]\); - - \r.e.shcnt_RNITO1A4[3]\ : MX2 - port map(A => \shiftin_8[12]\, B => \shiftin_8[4]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[4]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I280_Y_0\ : XNOR2 - port map(A => N712_i, B => ADD_30x30_fast_I280_Y_0_0, Y => - \tmp[22]\); - - \comb.v.x.data_0_1_1_iv_RNO[16]\ : OR2 - port map(A => \data_0_1_1[16]\, B => \data_0_1_1_iv_0[16]\, - Y => \data_0_1_1_iv_1[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I122_Y : NOR3C - port map(A => N443_0, B => N440_0, C => N519_0, Y => N585); - - \r.e.op1_RNIE81M7[1]\ : OR3C - port map(A => \ex_op1_i_m[1]\, B => \op1_i_m[1]\, C => - \bpdata_i_m[1]\, Y => edata2_0_iv(1)); - - \r.x.data_0_RNO[23]\ : OR3 - port map(A => \dco_m_0[119]\, B => \data_0_m[23]\, C => - \data_0_1_4[18]\, Y => \data_0_1[23]\); - - \r.m.result_0_RNIENIJ1[3]\ : OAI1 - port map(A => \maddress_0[3]\, B => \maddress[4]\, C => - trap27, Y => trap_0_sqmuxa); - - \r.e.ldbp2_RNI1UFSV7\ : NOR3 - port map(A => \eaddress[28]\, B => un1_addout_12_0, C => - \eaddress[16]\, Y => \un1_addout_12\); - - \r.e.jmpl_RNI31UJV_0\ : OR2B - port map(A => \shiftin_17[30]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[30]\); - - \r.x.ctrl.inst[24]\ : DFN1E0 - port map(D => \inst_0[24]\, CLK => lclk_c, E => holdn, Q - => \inst_2[24]\); - - \r.e.aluop_2_RNIJ26R2[1]\ : MX2C - port map(A => N_3552, B => \logicout_3[25]\, S => - \aluop_2[1]\, Y => N_3584); - - un6_fe_npc_I_31 : XOR2 - port map(A => N_131, B => \fe_pc[8]\, Y => I_31); - - \r.x.ctrl.wy_RNIRE1D\ : OR2A - port map(A => wy_2, B => wy_1, Y => wy_1_0_0); - - \r.d.inull_RNICHGG\ : AO1 - port map(A => \inull\, B => hold_pc_0_sqmuxa, C => - hold_pc_2_m, Y => N_3034); - - \r.w.s.pil_RNIF8C79[2]\ : AOI1B - port map(A => \bpdata[10]\, B => N_3974, C => - \aluresult_1_iv_2[10]\, Y => \aluresult_1_iv_4[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I128_Y : OR2B - port map(A => N529_0, B => N525_1, Y => N591_2); - - \r.e.aluop_0_RNIK9N4D[0]\ : NOR2B - port map(A => \aluresult_1_iv_5[6]\, B => \logicout_m_0[6]\, - Y => \aluresult_1_iv_6[6]\); - - \r.m.dci.lock_RNO_1\ : OR3A - port map(A => \inst[19]\, B => \inst[24]\, C => N_3749_3, Y - => N_3748); - - \r.e.op2_RNIVFMB1[22]\ : OR2A - port map(A => \un1_iu0_5[88]\, B => \un1_iu0_6[22]\, Y => - \logicout_4[22]\); - - \r.e.op1_RNICRPRB[10]\ : NOR3 - port map(A => \bpdata_i_m_2[2]\, B => \edata2_0_iv_0[10]\, - C => \bpdata_i_m[10]\, Y => edata2_0_iv(10)); - - un6_ex_add_res_d1_ADD_33x33_fast_I261_un1_Y : OR3C - port map(A => N645_1, B => N629, C => N802_0, Y => - I261_un1_Y_0); - - \r.m.ctrl.rd_RNIEFCA7[4]\ : NOR3C - port map(A => wreg_3, B => \rd_RNI2Q6H1[7]\, C => - un1_de_ren1_1_4_i_0, Y => wreg_5); - - \r.e.shleft_RNIIM661\ : MX2A - port map(A => \shiftin_5[25]\, B => \shiftin_5_i[9]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[9]\); - - \r.e.shcnt_RNIQN6B7[3]\ : MX2 - port map(A => \shiftin_8[41]\, B => \shiftin_8[33]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[33]\); - - \r.m.result_RNO[0]\ : MX2 - port map(A => \aluresult[0]\, B => \op1[0]\, S => - un17_casaen_0_2, Y => \eres2[0]\); - - \r.f.pc_RNO_6[30]\ : MX2 - port map(A => I_203, B => N_4073, S => bpmiss_1_i_0, Y => - \pc_4[30]\); - - \r.e.shleft_0\ : DFN1E0 - port map(D => N_208, CLK => lclk_c, E => holdn, Q => - shleft_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I11_P0N : OR3A - port map(A => \data_0[10]\, B => \op1[10]\, C => ldbp1_2, Y - => N428_0); - - \r.x.laddr_RNI21NB9[0]\ : MX2 - port map(A => \maddress[0]\, B => \laddr[0]\, S => - dco_i_2(132), Y => \me_laddr_2[0]\); - - \r.a.ctrl.ld_RNO\ : MX2C - port map(A => \inst_0_0[21]\, B => write_reg_0_sqmuxa_1, S - => ld_1_sqmuxa, Y => ld_2); - - \r.e.op1_RNI596JF[26]\ : NOR3C - port map(A => \edata2_iv_0[26]\, B => \bpdata_i_m[26]\, C - => \edata2_iv_2[26]\, Y => edata2_iv_i_0(26)); - - \r.m.wcwp\ : DFN1E0 - port map(D => wcwp_0, CLK => lclk_c, E => holdn, Q => wcwp); - - \r.a.imm_RNO[25]\ : MX2 - port map(A => \inst_0[15]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[143]\); - - \r.e.aluop_RNICSR04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[6]\, Y => - \bpdata_i_m_2[6]\); - - \r.x.dci.SIGNED_RNIIUIRU9\ : OR3 - port map(A => \rdata_13_m[8]\, B => \rdata_17_m[8]\, C => - \data_0_1_1[12]\, Y => \data_0_1_4[9]\); - - \r.e.op1_RNIJKHP7[14]\ : OR2 - port map(A => \bpdata_i_m[14]\, B => \edata2_0_iv_0[14]\, Y - => \edata2_0_iv_1[14]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_Y_2 : NOR3C - port map(A => I159_un1_Y_1, B => ADD_33x33_fast_I261_Y_0_0, - C => I215_un1_Y_0, Y => ADD_33x33_fast_I261_Y_2_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I157_un1_Y : OR3B - port map(A => N495_0, B => N568_1, C => N_50_1, Y => - I157_un1_Y_i_0); - - \r.x.rstate_RNO[1]\ : OA1A - port map(A => rstate_1188n, B => holdn, C => N_6323, Y => - N_6323s); - - \r.e.aluop_RNIGM3N1[1]\ : NOR2 - port map(A => edata_1_sqmuxa, B => edata_0_sqmuxa, Y => - N_3703_i); - - \r.m.y_RNO_2[11]\ : OR2A - port map(A => \logicout[11]\, B => y14, Y => - \logicout_m[11]\); - - \r.f.pc_RNO[18]\ : OR3C - port map(A => \tmp_m[18]\, B => \pc_1_iv_1[18]\, C => - \un6_fe_npc_m[16]\, Y => \pc_1[18]\); - - \r.e.op2_RNO_2[21]\ : NOR3C - port map(A => \d_1_iv_1[21]\, B => \d_1_iv_0[21]\, C => - \rfo_m_i[53]\, Y => \d_1_iv_3[21]\); - - \r.e.op1_RNI7HFC[3]\ : OR2B - port map(A => \op1[3]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I46_Y : NOR2B - port map(A => N470_0, B => N467, Y => N505_0); - - \r.e.ctrl.wicc_RNO\ : NOR3B - port map(A => ra_bpannul_1, B => wicc_0, C => \un1_p0_6[0]\, - Y => wicc_1_0); - - \r.e.ctrl.inst_RNI5I3O1[22]\ : OR2B - port map(A => un3_op_2, B => un3_op_1, Y => un3_op_i); - - \r.m.ctrl.rd_RNIFP2A1[1]\ : XA1A - port map(A => \un3_de_ren1[92]\, B => \rd_0[1]\, C => - un2_rs1_2_2_i_0, Y => wreg_1_2_0); - - \r.f.pc_RNO_4[31]\ : MX2 - port map(A => I_210, B => N_4074, S => bpmiss_1_i_0_0, Y - => \pc_4[31]\); - - \r.e.op1_RNIFKSFN7[29]\ : AOI1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[29]\, C - => \d_iv_3[29]\, Y => \d_i[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I2_G0N : NOR2B - port map(A => \un1_iu0_6[1]\, B => \op2[1]\, Y => N400_0); - - \r.w.s.wim_RNIB5RD2[5]\ : OR2B - port map(A => \wim[5]\, B => aluresult_13_sqmuxa, Y => - \wim_m[5]\); - - \r.m.result_RNI6CJN[28]\ : NOR3C - port map(A => \result_m_0[28]\, B => \cpi_m_0[380]\, C => - \result_m_0_0[28]\, Y => \d_iv_1[28]\); - - \r.e.op2_RNO_6[13]\ : AOI1B - port map(A => \result[13]\, B => d31, C => \imm_m_i[13]\, Y - => \d_1_iv_0[13]\); - - \r.x.ctrl.inst[27]\ : DFN1E0 - port map(D => \inst_3[27]\, CLK => lclk_c, E => holdn, Q - => \inst[27]\); - - \r.a.rsel2_0_RNI58AN3[0]\ : AOI1B - port map(A => data2(4), B => d25_0, C => \d_1_iv_2[4]\, Y - => \d_1_iv_3[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I25_P0N : AO1A - port map(A => ldbp1_4, B => \op1[24]\, C => \data_0[24]\, Y - => N470_0); - - \r.e.aluop_RNIVGC66[0]\ : MX2C - port map(A => N_3570, B => N_3634, S => \aluop_1[0]\, Y => - \logicout[11]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I259_Y_1 : NOR3C - port map(A => I33_un1_Y_1, B => N487, C => I95_un1_Y, Y => - ADD_33x33_fast_I259_Y_1); - - \r.a.ctrl.pc[26]\ : DFN1E0 - port map(D => \dpc[26]\, CLK => lclk_c, E => holdn, Q => - \pc_0[26]\); - - \r.m.y_RNO_3[23]\ : OR3A - port map(A => \y_2[23]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[23]\); - - \r.m.y_RNI96NI4[15]\ : NOR3C - port map(A => \cpi_m[160]\, B => \y_m_1[15]\, C => - \aluresult_1_iv_0[15]\, Y => \aluresult_1_iv_2[15]\); - - \r.d.pc_RNO[21]\ : MX2 - port map(A => \fpc[21]\, B => \dpc[21]\, S => N_6763_i_0, Y - => \pc_RNO[21]\); - - \r.e.op2_RNO_5[8]\ : NOR2B - port map(A => \imm_m_i[8]\, B => \result_m_i[8]\, Y => - \d_1_iv_0[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I54_Y : NOR2B - port map(A => N458, B => N455_2, Y => N513_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I239_un1_Y : NOR2B - port map(A => N668_1, B => N653_0, Y => I239_un1_Y_1); - - \r.e.aluop_RNI7UIK4[0]\ : OR2B - port map(A => \logicout[2]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[2]\); - - \r.e.jmpl_RNI85S3N\ : OR2B - port map(A => \shiftin_17[10]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[10]\); - - \r.a.rsel1_0[2]\ : DFN1E0 - port map(D => rs1, CLK => lclk_c, E => holdn, Q => - \rsel1_0[2]\); - - \r.e.aluop_RNI9EAU2[1]\ : MX2C - port map(A => N_3538, B => \logicout_3[11]\, S => - \aluop_3[1]\, Y => N_3570); - - \r.x.mexc_1_sqmuxa\ : NOR2A - port map(A => holdn, B => dco_i_2(132), Y => mexc_1_sqmuxa); - - \r.e.aluop_RNIAUMP8[2]\ : AOI1 - port map(A => edata_1_sqmuxa, B => \bpdata[12]\, C => - \bpdata_i_m_2[4]\, Y => \edata2_iv_2[28]\); - - \r.e.aluop_0_RNIBR1T2[1]\ : MX2C - port map(A => \logicout_4[25]\, B => N_6856, S => - N_6866_i_0, Y => N_3648); - - \r.e.op1_RNO[14]\ : MX2C - port map(A => \d_i[14]\, B => \d_i[15]\, S => N_227, Y => - \aop1[14]\); - - \r.a.imm[2]\ : DFN1E0 - port map(D => \un3_de_ren1[120]\, CLK => lclk_c, E => holdn, - Q => \imm[2]\); - - \r.m.dci.asi[2]\ : DFN1E0 - port map(D => \asi[2]\, CLK => lclk_c, E => holdn, Q => - asi_0(2)); - - \r.e.ctrl.inst_RNIJ41E[24]\ : OR2B - port map(A => \inst_0[23]\, B => \inst[24]\, Y => N_3749_2); - - \r.x.result_RNIQPKJ3[11]\ : MX2C - port map(A => \un1_iu0_6[11]\, B => \un1_p0_6[363]\, S => - bpdata6, Y => \bpdata[11]\); - - \r.f.pc_RNIT1222[8]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[8]\, Y => \xc_trap_address_m[8]\); - - \r.x.rstate_RNIOP1U[1]\ : OR2A - port map(A => rst, B => xc_exception_1, Y => \un1_p0_6[0]\); - - \r.e.op2_RNISM992[12]\ : AOI1B - port map(A => \un1_iu0_5[78]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[12]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I250_Y_0_a3 : NOR2B - port map(A => N672_0, B => N419_1, Y => - ADD_33x33_fast_I250_Y_0_a3); - - \r.a.ctrl.pc[14]\ : DFN1E0 - port map(D => \dpc[14]\, CLK => lclk_c, E => holdn, Q => - \pc[14]\); - - wovf_exc_0_sqmuxa_1 : NOR2 - port map(A => un7_op, B => \wovf_exc_0_sqmuxa\, Y => - \wovf_exc_0_sqmuxa_1\); - - \r.m.y_RNO_2[8]\ : OR2A - port map(A => \logicout[8]\, B => y14, Y => \logicout_m[8]\); - - \r.e.ctrl.cnt_RNIBT47[0]\ : OR2A - port map(A => \cnt[1]\, B => \cnt[0]\, Y => N_3355_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I31_G0N : OR2B - port map(A => \un1_iu0_6[30]\, B => \data_0[30]\, Y => - N487_0); - - \r.x.icc[1]\ : DFN1E0 - port map(D => \icc[1]\, CLK => lclk_c, E => holdn, Q => - \icc_3[1]\); - - \r.w.result[14]\ : DFN1E0 - port map(D => \wdata[14]\, CLK => lclk_c, E => holdn, Q => - \result[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I16_P0N\ : OR2 - port map(A => \inst_0[16]\, B => \dpc[18]\, Y => N407_0); - - \r.f.pc_RNI5DT811[2]\ : MX2A - port map(A => \fe_pc[2]\, B => N_4045, S => bpmiss_1_i_0_0, - Y => \pc_4[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I70_Y : OA1 - port map(A => \op2[12]\, B => \un1_iu0_6[12]\, C => N431_1, - Y => N529_1); - - \r.m.y_RNO_1[24]\ : OR2B - port map(A => \y_2[25]\, B => mulstep_1, Y => N_374); - - \r.m.dci.size_RNO_1[0]\ : OA1A - port map(A => \inst[19]\, B => \inst_1[21]\, C => - \inst[24]\, Y => N_3757); - - \r.e.jmpl_RNITN6O_1\ : NOR3 - port map(A => jmpl, B => aluresult_1_sqmuxa_0_0, C => - \ex_shcnt_1[0]\, Y => aluresult_1_sqmuxa); - - \r.m.result[26]\ : DFN1E0 - port map(D => \eres2[26]\, CLK => lclk_c, E => holdn, Q => - \maddress[26]\); - - un6_fe_npc_I_24 : XOR2 - port map(A => N_136, B => \fe_pc[7]\, Y => I_24); - - un2_rstn_5_RNIROLH1 : NAND2 - port map(A => \tmp[3]\, B => \un2_rstn_5\, Y => \tmp_m[3]\); - - \r.m.ctrl.trap_RNI90MMC\ : OR2B - port map(A => me_nullify2_1_2_1, B => nullify_1_sqmuxa, Y - => \me_nullify2_1_2\); - - \r.e.ctrl.inst_RNI2H1S[24]\ : NOR2A - port map(A => N_3749_2, B => N_3356_3, Y => - enaddr_2_sqmuxa_1); - - \r.e.jmpl_RNISAER71\ : AOI1B - port map(A => \shiftin_17[3]\, B => aluresult_1_sqmuxa, C - => \aluresult_2_iv_6[2]\, Y => \aluresult_2_iv_7[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I282_Y_0\ : AX1D - port map(A => I239_un1_Y, B => ADD_30x30_fast_I239_Y_1, C - => ADD_30x30_fast_I282_Y_0_0, Y => \tmp[24]\); - - \r.m.result[12]\ : DFN1E0 - port map(D => \eres2[12]\, CLK => lclk_c, E => holdn, Q => - \maddress[12]\); - - \r.e.op2_RNO_0[25]\ : OR3C - port map(A => \op1_m_i[25]\, B => \d_1_iv_3[25]\, C => - \aluresult_m_i[25]\, Y => \d_1[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I195_Y : AO1 - port map(A => N606_2, B => N599_2, C => N598_2, Y => N664); - - \r.w.s.y_RNO_2[29]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[29]\, Y - => N_414); - - \r.e.aluop_RNI77PI2[1]\ : MX2C - port map(A => N_3547, B => \logicout_3[20]\, S => - \aluop_3[1]\, Y => N_3579); - - \r.a.ctrl.inst_RNI628V1[19]\ : OA1 - port map(A => N_262, B => aluop_1_1_0_a5_0, C => N_344, Y - => aluop_1_1_0_0); - - \r.e.op1_RNIST53T1[0]\ : OR3C - port map(A => \op1_m_0[0]\, B => \d_iv_2[0]\, C => - \aluresult_m_0[0]\, Y => \d[0]\); - - \r.m.icc_RNO_10[2]\ : NOR3A - port map(A => icc_0_sqmuxa_1_16, B => \logicout[22]\, C => - \logicout[21]\, Y => icc_0_sqmuxa_1_24); - - \r.e.ctrl.pc[10]\ : DFN1E0 - port map(D => \pc_3[10]\, CLK => lclk_c, E => holdn, Q => - \pc_0[10]\); - - \r.m.ctrl.inst_RNITC0E[20]\ : NOR2A - port map(A => \inst_3[20]\, B => \inst[21]\, Y => inst_4_1); - - \r.d.annul_RNIFM901\ : AOI1 - port map(A => hold_pc_2_sqmuxa, B => hold_pc_0_sqmuxa_1, C - => annul_1, Y => annul_2_0); - - \r.m.y[9]\ : DFN1E0 - port map(D => \y_0[9]\, CLK => lclk_c, E => holdn, Q => - \y_1[9]\); - - \r.w.result[17]\ : DFN1E0 - port map(D => \wdata[17]\, CLK => lclk_c, E => holdn, Q => - \result[17]\); - - \r.a.rsel2_0_RNI7V53_0[0]\ : OR2A - port map(A => d28_0_0, B => \rsel2_0[0]\, Y => d27); - - \r.e.shcnt_RNIKJ4TL[1]\ : MX2C - port map(A => \shiftin_14[10]\, B => \shiftin_14[8]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[8]\); - - \r.a.ctrl.inst_RNIKJV9I1[13]\ : NOR2B - port map(A => illegal_inst_7_iv_7, B => - illegal_inst_7_iv_6_0, Y => illegal_inst_7_i_0); - - \r.e.jmpl_RNIRSOT\ : OR2A - port map(A => miscout_11_sqmuxa, B => jmpl, Y => jmpl_4); - - \r.e.op2_RNO_3[14]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[14]\, Y => - \aluresult_m_i[14]\); - - \r.d.inst_0[15]\ : DFN1 - port map(D => \inst_0_RNO[15]\, CLK => lclk_c, Q => - \inst_0[15]\); - - \r.d.inst_0_RNI0423[20]\ : NOR2 - port map(A => \inst_0[20]\, B => \inst_0_0[22]\, Y => - fins_0_a3_0); - - \r.x.data_0_RNO_1[7]\ : NOR3C - port map(A => \dco_m_i[111]\, B => \data_0_m_i[7]\, C => - \dco_m_i[127]\, Y => \data_0_1_1_iv_1[7]\); - - \r.w.s.icc_RNO[0]\ : AO1B - port map(A => icc_1_sqmuxa, B => \icc[0]\, C => - \icc_1_iv_0[0]\, Y => \icc_1[0]\); - - \r.m.ctrl.inst_RNIHFAI01[30]\ : NOR2 - port map(A => \me_nullify2_1_2\, B => \nullify2_0_sqmuxa\, - Y => me_nullify2_1_0); - - \r.a.ctrl.rd_RNIAI7Q[1]\ : XNOR2 - port map(A => \inst_0_RNI1JUM[1]\, B => \rd_2[1]\, Y => - un1_de_ren1_1_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I267_Y_0 : NOR2A - port map(A => I227_un1_Y, B => N640_0, Y => - ADD_33x33_fast_I267_Y_0_0); - - \r.e.op2_RNO_2[10]\ : OR2B - port map(A => data2(10), B => d25_0, Y => \rfo_m_i[42]\); - - \r.e.ctrl.inst_RNIHI8M1[20]\ : NOR3B - port map(A => aluresult_13_sqmuxa_1, B => - aluresult_13_sqmuxa_0_0, C => aluresult_9_sqmuxa_1, Y => - aluresult_13_sqmuxa_3_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I285_Y_0_0\ : XOR2 - port map(A => \dpc[27]\, B => \inst_0_1[27]\, Y => - ADD_30x30_fast_I285_Y_0_0); - - \r.d.inst_0_0_0_RNI7IM7_0[21]\ : NOR2B - port map(A => \inst_0_0[22]\, B => \un1_p0_6_0[60]\, Y => - ldcheck1_5_i_a6_2_1); - - \r.a.rsel1_0_RNIJ7LJ2[2]\ : OR2B - port map(A => data1(29), B => d11, Y => \rfo_m[29]\); - - \r.a.ctrl.wy_RNO_3\ : NOR2 - port map(A => N_3525_3, B => N_122_1, Y => wy_1_0_a3_0_7_2); - - \comb.dcache_gen.un1_r.e.ctrl.trap\ : NOR2 - port map(A => un1_annul, B => trap_0, Y => trap); - - un6_ex_add_res_d1_ADD_33x33_fast_I26_G0N : NOR2B - port map(A => \un1_iu0_6[25]\, B => \op2[25]\, Y => N472_0); - - \r.m.ctrl.pc_RNIS6AE[4]\ : MX2 - port map(A => \pc_3[4]\, B => \pc_0[4]\, S => \npc_1[1]\, Y - => N_3245); - - \r.a.rfe1\ : DFN1E0 - port map(D => rfe_1, CLK => lclk_c, E => holdn, Q => \rfe1\); - - \r.w.s.wim_RNIJSJV2[4]\ : AOI1B - port map(A => \wim[4]\, B => aluresult_13_sqmuxa, C => - aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[4]\); - - \r.e.shleft_RNIL6FC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[15]\, S => - shleft, Y => \shiftin_5[46]\); - - \r.d.inst_0_RNO_0[22]\ : MX2 - port map(A => data_0_22, B => \inst_0_0[22]\, S => - inull_RNIFV6VG2_0, Y => N_4622); - - un6_ex_add_res_d2_ADD_33x33_fast_I270_Y_0_a3_1 : NOR2B - port map(A => N455_1, B => N452_1, Y => N_71_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I116_Y : NOR2B - port map(A => N517, B => N513_0, Y => N579_0); - - \r.a.rsel1_0_RNIA3LJ2[2]\ : OR2B - port map(A => data1(13), B => d11, Y => \rfo_m[13]\); - - \r.a.ctrl.inst[23]\ : DFN1E0 - port map(D => \inst_0_0[23]\, CLK => lclk_c, E => holdn, Q - => \inst_1[23]\); - - \r.f.pc_RNO_2[25]\ : OR2B - port map(A => I_156, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[23]\); - - \r.a.ctrl.inst_RNI7C0E_1[31]\ : OR2A - port map(A => \inst[30]\, B => \inst[31]\, Y => N_344); - - \r.e.jmpl_RNIVRLVA3\ : OR3C - port map(A => \aluresult_1_iv_7[12]\, B => - \shiftin_17_m_0[12]\, C => \un6_ex_add_res_m[13]\, Y => - \aluresult[12]\); - - \comb.v.x.data_0_1_1_iv_RNO[31]\ : OR2 - port map(A => \data_0_1_1[16]\, B => \data_0_1_1_iv_0[31]\, - Y => \data_0_1_1_iv_1[31]\); - - \r.f.pc_RNIOH32M1[4]\ : OA1A - port map(A => \fpc[4]\, B => rst, C => - \un6_ex_add_res_m_1[5]\, Y => \npc_iv_1[4]\); - - \r.e.op2_RNO[26]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[26]\, Y => N_310); - - \r.e.op1_RNIMP3B2[14]\ : AO1A - port map(A => \un1_iu0_6[14]\, B => edata_3_sqmuxa_0, C => - \op1_i_m[14]\, Y => \edata2_0_iv_0[14]\); - - \r.m.result_RNIABJN[21]\ : NOR3C - port map(A => \result_m_0[21]\, B => \cpi_m_0[373]\, C => - \result_m_0_0[21]\, Y => \d_iv_1[21]\); - - \r.m.icc_RNO_24[2]\ : NOR3A - port map(A => icc_0_sqmuxa_1_5, B => \logicout[16]\, C => - \logicout[15]\, Y => icc_0_sqmuxa_1_19); - - \comb.op_mux.d_1_iv_RNO_2[29]\ : NOR3C - port map(A => \d_1_iv_1[29]\, B => \d_1_iv_0[29]\, C => - \rfo_m_i[61]\, Y => \d_1_iv_3[29]\); - - \r.x.data_0_RNO_4[4]\ : NAND2 - port map(A => data_0_12, B => rdata_2_sqmuxa, Y => - \dco_m_i[108]\); - - \r.x.data_0[30]\ : DFN1E0 - port map(D => \data_0_1[30]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[30]\); - - \r.f.pc_RNO_3[27]\ : NAND2 - port map(A => \tmp[27]\, B => \un2_rstn_5\, Y => - \tmp_m[27]\); - - \r.a.rsel2_RNI9LB_1[1]\ : NOR2A - port map(A => \rsel2[2]\, B => \rsel2[1]\, Y => d29_0_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_Y_1 : AOI1B - port map(A => N652_0, B => N637, C => - ADD_33x33_fast_I265_Y_0_0, Y => ADD_33x33_fast_I265_Y_1); - - \r.e.shcnt_RNI8D0R7[3]\ : MX2 - port map(A => \shiftin_8[44]\, B => \shiftin_8[36]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[36]\); - - \r.a.rsel1_RNIDCJV22[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[2]\, Y => - \aluresult_m_0[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I183_un1_Y\ : OR2B - port map(A => N558, B => N551, Y => I183_un1_Y_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I306_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[16]\, B => N796_1, Y => - \un6_ex_add_res_s0[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I179_Y : AO1 - port map(A => N590_2, B => N583_0, C => N582_1, Y => N648); - - \r.m.result_0_RNI5ER8[1]\ : OR2A - port map(A => \maddress_0[1]\, B => d27, Y => - \result_m_i[1]\); - - \r.d.inst_0_RNO[3]\ : NOR2B - port map(A => rst, B => N_4603, Y => \inst_0_RNO[3]\); - - \r.x.laddr_RNI66ENI[0]\ : OR2A - port map(A => \me_laddr_2[0]\, B => \me_laddr_2[1]\, Y => - rdata_1_sqmuxa_0); - - un54_ra_I_15 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => \ncwp[1]\, Y - => \DWACT_ADD_CI_0_g_array_1[0]\); - - \r.x.result[26]\ : DFN1E0 - port map(D => \maddress[26]\, CLK => lclk_c, E => holdn, Q - => \result[26]\); - - \r.e.op2_RNO_6[25]\ : OR2B - port map(A => data2(25), B => d25, Y => \rfo_m_i[57]\); - - \r.a.ctrl.pc[13]\ : DFN1E0 - port map(D => \dpc[13]\, CLK => lclk_c, E => holdn, Q => - \pc[13]\); - - \r.x.ctrl.inst_RNIE0331[20]\ : NOR3B - port map(A => y6_0, B => y10_3_0, C => \inst[20]\, Y => y10); - - \r.w.s.y_RNO[11]\ : MX2 - port map(A => \y_2[11]\, B => \result_0[11]\, S => N_481_0, - Y => N_3775); - - \r.a.ctrl.wreg_RNO_7\ : OR2B - port map(A => \inst_0[19]\, B => N_145, Y => un3_op); - - \r.x.ctrl.annul_RNI0THC\ : NOR2 - port map(A => annul_0, B => \rstate_d[2]\, Y => rstate_8_0); - - \r.m.result[8]\ : DFN1E0 - port map(D => \eres2[8]\, CLK => lclk_c, E => holdn, Q => - \maddress[8]\); - - \r.e.op2_RNO_1[7]\ : OR2B - port map(A => \op1[7]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[7]\); - - \r.f.pc_RNI9IB62[5]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[5]\, Y => \xc_trap_address_m[5]\); - - \r.e.aluop_RNIFC5U6[0]\ : OR2B - port map(A => \logicout[21]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[21]\); - - \r.f.pc_RNO_7[31]\ : MX2 - port map(A => \fpc[31]\, B => \tba[19]\, S => - rstate_6314_d_0, Y => \xc_trap_address[31]\); - - \r.e.op2_RNO_7[8]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[360]\, Y => \cpi_m_i[360]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I20_P0N : AO1A - port map(A => ldbp1_1, B => \op1[19]\, C => \data_0[19]\, Y - => N455_1); - - \r.w.s.y[21]\ : DFN1E0 - port map(D => N_3785, CLK => lclk_c, E => N_6922_i_0, Q => - \y_2[21]\); - - \r.f.pc_RNI4MT6S[9]\ : MX2 - port map(A => \fpc[9]\, B => \eaddress[9]\, S => jump_0, Y - => N_4052); - - un6_fe_npc_I_41 : AND2 - port map(A => \fe_pc[8]\, B => \fe_pc[9]\, Y => - \DWACT_FINC_E[3]\); - - \r.x.dci.SIGNED_RNIETQQB1\ : NOR2B - port map(A => me_signed_1, B => data_0_0_15, Y => - \rdata_13[8]\); - - \r.e.jmpl_RNIKTFSN\ : OR2B - port map(A => \shiftin_17[12]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I268_Y_0\ : XNOR2 - port map(A => N608_i, B => ADD_30x30_fast_I268_Y_0_0, Y => - \tmp[10]\); - - \r.m.ctrl.pc[20]\ : DFN1E0 - port map(D => \pc_0[20]\, CLK => lclk_c, E => holdn, Q => - \pc_3[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I170_Y\ : OR2 - port map(A => N536, B => I170_un1_Y, Y => N596); - - \r.d.pc_RNO[12]\ : MX2 - port map(A => \fpc[12]\, B => \dpc[12]\, S => N_6763_i_0, Y - => \pc_RNO[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I28_P0N\ : NOR2 - port map(A => \inst_0_1[30]\, B => \dpc[30]\, Y => N443_2); - - \r.m.y[23]\ : DFN1E0 - port map(D => \y_1[23]\, CLK => lclk_c, E => holdn, Q => - \y[23]\); - - \r.m.ctrl.pc[14]\ : DFN1E0 - port map(D => \pc_1[14]\, CLK => lclk_c, E => holdn, Q => - \pc_2[14]\); - - \r.e.op1_RNI3P2M7[4]\ : AO1C - port map(A => \bpdata[4]\, B => N_3687, C => - \edata2_0_iv_0[4]\, Y => edata2_0_iv(4)); - - \r.m.y[0]\ : DFN1E0 - port map(D => \y_1[0]\, CLK => lclk_c, E => holdn, Q => - \y_0[0]\); - - \r.e.op2_RNO_7[26]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[378]\, - Y => \cpi_m_i[378]\); - - \r.e.ctrl.annul_RNIAMD1G\ : OR3C - port map(A => jump_0, B => ex_bpmiss_1_0, C => - \ra_bpmiss_1_0\, Y => un12_de_hold_pc); - - \r.a.ctrl.inst_RNIFG1L[25]\ : NOR3B - port map(A => \inst_1[25]\, B => \inst_2[20]\, C => - \inst_1[24]\, Y => \cpi_m_1[133]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I29_G0N : NOR2A - port map(A => \un1_iu0_6[28]\, B => \data_0[28]\, Y => N481); - - \r.x.ctrl.rd[2]\ : DFN1E0 - port map(D => \rd_0[2]\, CLK => lclk_c, E => holdn, Q => - \rd_3[2]\); - - \r.w.s.y_RNO[8]\ : MX2 - port map(A => \y_2[8]\, B => \result[8]\, S => N_481_0, Y - => N_3772); - - un9_ra_I_1 : AND2 - port map(A => \cwp_0[0]\, B => \inst_0[29]\, Y => - \DWACT_ADD_CI_0_TMP_2[0]\); - - \r.e.ldbp2_2_RNI5355F\ : OR2 - port map(A => aluresult_0_sqmuxa, B => \eaddress[6]\, Y => - ldbp2_2_RNI5355F); - - \r.x.laddr[0]\ : DFN1E0 - port map(D => \maddress[0]\, CLK => lclk_c, E => holdn, Q - => \laddr[0]\); - - \r.d.pc_RNI0UGB4[18]\ : MX2 - port map(A => \dpc[18]\, B => \fpc[18]\, S => - \ra_bpmiss_1_0\, Y => N_3895); - - \r.e.aluop_0_RNI91C3J[0]\ : AND2 - port map(A => \aluresult_1_iv_6[6]\, B => \bpdata_m[6]\, Y - => \aluresult_1_iv_7[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I265_un1_Y_0 : NOR2B - port map(A => N637_1, B => N653_0, Y => - ADD_33x33_fast_I265_un1_Y_0_1); - - \r.m.y_RNIONRFG[20]\ : NOR3C - port map(A => \aluresult_1_iv_4[20]\, B => - \aluresult_1_iv_3[20]\, C => \bpdata_m_1[4]\, Y => - \aluresult_1_iv_6[20]\); - - \r.e.ctrl.pv\ : DFN1E0 - port map(D => pv_4, CLK => lclk_c, E => holdn, Q => pv_5); - - \r.w.s.y[24]\ : DFN1E0 - port map(D => N_6686, CLK => lclk_c, E => holdn, Q => - \y_0[24]\); - - \r.a.ctrl.inst_RNIS96K2[21]\ : OA1A - port map(A => inst_11_1, B => inst_9_3, C => inst_22, Y => - illegal_inst34_1); - - \r.f.pc_RNO_6[27]\ : MX2 - port map(A => \fpc[27]\, B => \eaddress[27]\, S => jump, Y - => N_4070); - - \r.a.rsel2_0_RNIMTBM2[0]\ : OR2B - port map(A => data2(1), B => d25_0, Y => \rfo_m_i[33]\); - - \r.e.aluop_0_RNICHJD1[1]\ : XOR3 - port map(A => \un1_iu0_6[18]\, B => \aluop_0[1]\, C => - \un1_iu0_5[84]\, Y => N_6895); - - \r.e.ldbp2_2_RNI35VBO\ : OR2A - port map(A => \eaddress[9]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[10]\); - - \r.x.result_RNI2GAB3[7]\ : MX2 - port map(A => \un1_iu0_6[7]\, B => \un1_p0_6[359]\, S => - bpdata6_0_0, Y => \bpdata[7]\); - - \r.a.ctrl.rd_RNIAC1L[1]\ : XNOR2 - port map(A => \rd_2[1]\, B => \un3_de_ren1[92]\, Y => - un2_rs1_1_i); - - \r.m.y[20]\ : DFN1E0 - port map(D => \y_1[20]\, CLK => lclk_c, E => holdn, Q => - \y_0[20]\); - - \r.e.shcnt_RNIFEVV3[3]\ : MX2 - port map(A => \shiftin_8[11]\, B => \shiftin_8[3]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[3]\); - - \r.e.aluop_0[0]\ : DFN1E0 - port map(D => \aluop[0]\, CLK => lclk_c, E => holdn, Q => - \aluop_0[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I305_Y_0 : XOR2 - port map(A => N799, B => \un6_ex_add_res_s2_1[15]\, Y => - \un6_ex_add_res_s2[15]\); - - \r.m.y_RNO_0[27]\ : AOI1B - port map(A => wy_1_0, B => \y[27]\, C => N_422, Y => - \y_iv_0_1[27]\); - - \r.e.alucin_RNO_5\ : MX2C - port map(A => \icc_0[0]\, B => \icco[0]\, S => wicc_2, Y - => N_220); - - un6_ex_add_res_d1_ADD_33x33_fast_I268_un1_Y_0 : NOR3C - port map(A => N593_0, B => N601, C => N643_0, Y => - ADD_33x33_fast_I268_un1_Y_0_1); - - \r.m.y_RNO_1[1]\ : AOI1B - port map(A => \y[1]\, B => y08_0, C => N_381, Y => - \y_iv_0_0[1]\); - - \r.e.op1_RNITACR1[24]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[24]\, Y => - \ex_op1_i_m[24]\); - - \r.x.ctrl.inst[25]\ : DFN1E0 - port map(D => \inst_3[25]\, CLK => lclk_c, E => holdn, Q - => \inst[25]\); - - \r.e.op2_RNO_5[27]\ : AOI1B - port map(A => \result[27]\, B => d31_0, C => \imm_m_i[27]\, - Y => \d_1_iv_0[27]\); - - \r.e.ctrl.pv_RNIKLVC\ : NOR2 - port map(A => pv_5, B => pv_1, Y => \npc_cnst_m_0[1]\); - - \r.x.ctrl.pc_RNIJJ431[6]\ : MX2C - port map(A => \un1_p0_6[358]\, B => \pc_1[6]\, S => - s_3_sqmuxa_0, Y => N_3397); - - \r.w.result_RNIA4P1[23]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[23]\, - Y => \result_m_0_0[23]\); - - \r.e.ldbp2_0_RNIKEHUF\ : OR2 - port map(A => aluresult_0_sqmuxa_0, B => \eaddress[7]\, Y - => ldbp2_0_RNIKEHUF); - - \r.a.ctrl.rd_RNIEQ7Q[3]\ : XNOR2 - port map(A => \inst_0_RNI3RUM[3]\, B => \rd_1[3]\, Y => - un1_de_ren1_3_i); - - aluresult_11_sqmuxa_5_RNO : OR2A - port map(A => \inst[19]\, B => aluresult_9_sqmuxa_1, Y => - aluresult_11_sqmuxa_5_0); - - \r.x.ctrl.inst_RNIFU0L[23]\ : NOR3B - port map(A => \inst_0[21]\, B => \inst[23]\, C => - \inst[20]\, Y => cwp_2_sqmuxa_2); - - \r.x.data_0_RNI96HK[31]\ : NOR2A - port map(A => \data_0_0[31]\, B => ex_sari_1_1_0, Y => - ex_sari_1); - - \r.f.pc_RNO_7[20]\ : MX2 - port map(A => \fpc[20]\, B => \tba[8]\, S => - rstate_6314_d_0, Y => \xc_trap_address[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I19_P0N\ : OR2 - port map(A => \inst_0[19]\, B => \dpc[21]\, Y => N416_2); - - \r.x.ctrl.pc[18]\ : DFN1E0 - port map(D => \pc_3[18]\, CLK => lclk_c, E => holdn, Q => - \pc_2[18]\); - - \r.e.shleft_1\ : DFN1E0 - port map(D => N_208, CLK => lclk_c, E => holdn, Q => - shleft_1); - - \r.e.ctrl.rd[6]\ : DFN1E0 - port map(D => \rd[6]\, CLK => lclk_c, E => holdn, Q => - \rd_0[6]\); - - \r.m.dci.lock_RNO\ : AOI1 - port map(A => N_3749, B => N_3748, C => N_3356_3, Y => - lock_1); - - \r.m.ctrl.trap_RNICM9T2\ : OR2A - port map(A => trap_2_0, B => annul_RNIPFOQ, Y => annul_3); - - \r.f.pc_RNO_0[8]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[8]\, C => - \pc_1_iv_0[8]\, Y => \pc_1_iv_1[8]\); - - \r.x.result_RNISNKA[6]\ : MX2 - port map(A => \result_0[6]\, B => \data_0[6]\, S => ld_0, Y - => \un1_p0_6[358]\); - - \r.w.s.tt_RNIHVP81[7]\ : OR2B - port map(A => \tt[7]\, B => aluresult_12_sqmuxa, Y => - \tt_m[7]\); - - \r.e.op1_RNI15UH[21]\ : MX2 - port map(A => \op1[21]\, B => \data_0[21]\, S => ldbp1_2, Y - => \un1_iu0_6[21]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_3\ : AND2A - port map(A => irl_0(1), B => \pil[1]\, Y => \ACT_LT4_E[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I121_un1_Y : OA1A - port map(A => N_53_i, B => N442_1, C => N519_2, Y => - I121_un1_Y); - - \r.a.rsel1_0_RNIF3LJ2[2]\ : OR2B - port map(A => data1(18), B => d11, Y => \rfo_m[18]\); - - \r.x.laddr_RNIH68NE1[0]\ : OR3A - port map(A => rdata_3_sqmuxa_2, B => \me_laddr_2[1]\, C => - \me_laddr_2[0]\, Y => rdata_0_sqmuxa); - - \r.d.inst_0_RNO_0[14]\ : MX2 - port map(A => data_0_0_14, B => \inst_0[14]\, S => - mexc_1_sqmuxa_1_0, Y => N_4614); - - \r.f.pc_RNO_3[16]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[16]\, C => - \xc_trap_address_m[16]\, Y => \pc_1_iv_0[16]\); - - \r.e.op2_RNO_5[6]\ : AOI1B - port map(A => \result[6]\, B => d31, C => \imm_m_i[6]\, Y - => \d_1_iv_0[6]\); - - \r.a.ctrl.pc[25]\ : DFN1E0 - port map(D => \dpc[25]\, CLK => lclk_c, E => holdn, Q => - \pc_0[25]\); - - \r.w.s.wim[0]\ : DFN1E0 - port map(D => \wim_1[0]\, CLK => lclk_c, E => holdn, Q => - \wim[0]\); - - \r.e.aluop_RNIE2SO4[2]\ : OR2B - port map(A => edata_1_sqmuxa, B => \bpdata[14]\, Y => - \bpdata_i_m_0[14]\); - - \r.m.result_RNIAMTD3[30]\ : NOR3C - port map(A => \d_iv_0[30]\, B => \result_m_0[30]\, C => - \rfo_m[30]\, Y => \d_iv_2[30]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I77_Y : MAJ3 - port map(A => \op2[8]\, B => \un1_iu0_6[8]\, C => N418_1, Y - => N536_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I116_Y_0\ : MIN3 - port map(A => \dpc[15]\, B => \inst_0[13]\, C => N394, Y - => ADD_30x30_fast_I116_Y_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I34_Y : NOR2A - port map(A => N488, B => N485_i_0, Y => N493); - - \r.e.op2_RNO_3[9]\ : NOR3C - port map(A => \result_m_i[9]\, B => \imm_m_i[9]\, C => - \d_1_iv_1[9]\, Y => \d_1_iv_2[9]\); - - \r.a.ctrl.inst_RNI9T3V1[31]\ : OR2A - port map(A => illegal_inst12, B => N_201, Y => N_345); - - \r.x.y[3]\ : DFN1E0 - port map(D => \y_1[3]\, CLK => lclk_c, E => holdn, Q => - \y_2[3]\); - - \r.e.op2_RNO_8[22]\ : OR3B - port map(A => d29_0, B => \imm[22]\, C => \rsel2[0]\, Y => - \imm_m_i[22]\); - - \r.e.ldbp2_RNITF9UK\ : OA1A - port map(A => \eaddress[1]\, B => aluresult_0_sqmuxa_0, C - => \aluresult_2_iv_5[1]\, Y => \aluresult_2_iv_6[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I69_Y : AO18 - port map(A => \un1_iu0_6[12]\, B => N430_1, C => - \data_0_2[12]\, Y => N528_2); - - \r.m.ctrl.trap_RNIBN4L1\ : OA1C - port map(A => nullify_0_sqmuxa_0, B => un5_trap, C => - annul_RNIPFOQ, Y => me_nullify2_1_2_0); - - \r.m.ctrl.rett\ : DFN1E0 - port map(D => rett_1_3, CLK => lclk_c, E => holdn, Q => - rett); - - \r.e.aluop_RNI27PHA8[0]\ : MX2A - port map(A => \logicout[23]\, B => \aluresult[31]\, S => - un3_op_i, Y => N_4178); - - un6_ex_add_res_d2_ADD_33x33_fast_I22_P0N : AO1A - port map(A => ldbp1_4, B => \op1[21]\, C => \data_0[21]\, Y - => N461_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I249_Y : OR2A - port map(A => I249_un1_Y_i, B => N668, Y => N814); - - \r.m.y_RNO_3[24]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[24]\, C => N_372, Y => - \y_iv_0_1[24]\); - - \r.e.aluop_RNIKVO31[2]\ : NOR3 - port map(A => logicout22_1, B => \aluop_1[2]\, C => - aluresult_9_sqmuxa_1, Y => aluresult_5_sqmuxa); - - \r.m.y_RNO_2[19]\ : OR2A - port map(A => \logicout[19]\, B => y14, Y => - \logicout_m[19]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I210_un1_Y\ : OAI1 - port map(A => I176_un1_Y, B => N542, C => N587, Y => - I210_un1_Y); - - \r.e.aluop_0_RNIM51E[2]\ : OR2 - port map(A => \aluop_0[2]\, B => aluresult_9_sqmuxa_1, Y - => aluresult_7_sqmuxa_0); - - \r.e.shleft\ : DFN1E0 - port map(D => N_208, CLK => lclk_c, E => holdn, Q => shleft); - - \r.d.inst_0_RNIN0IBM[13]\ : AO1B - port map(A => un1_de_ren1_NE_i_0, B => ldcheck2, C => - un1_ldcheck1, Y => un1_ldcheck1_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_un1_Y : OR2B - port map(A => ADD_33x33_fast_I261_un1_Y_0_0, B => N802_1, Y - => I261_un1_Y_1); - - \r.e.op1_RNI1RCR1[19]\ : NOR2A - port map(A => edata_3_sqmuxa_0, B => \op1_RNID1VH[19]\, Y - => \ex_op1_i_m[19]\); - - \r.m.dci.write\ : DFN1E0 - port map(D => write, CLK => lclk_c, E => holdn, Q => - write_0); - - \r.m.ctrl.pc[13]\ : DFN1E0 - port map(D => \pc_2[13]\, CLK => lclk_c, E => holdn, Q => - \pc_3[13]\); - - \r.e.shleft_RNI5ARJ\ : OR2A - port map(A => \un1_iu0_6[13]\, B => shleft, Y => - \shiftin_5[13]\); - - \r.a.ctrl.wy_RNO_2\ : NOR3 - port map(A => N_122_2, B => \inst_0[25]\, C => N_89, Y => - wy_1_0_a3_0_7_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I312_Y_0 : AX1C - port map(A => I269_un1_Y_0, B => ADD_33x33_fast_I269_Y_0_1, - C => ADD_33x33_fast_I312_Y_0_0, Y => - \un6_ex_add_res_s1_i[22]\); - - \r.f.pc_RNI8CM4[6]\ : NOR2A - port map(A => \fpc[6]\, B => rst, Y => \pc_RNI8CM4[6]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I143_Y : AO1 - port map(A => N544_2, B => N541, C => N540_1, Y => N606_2); - - \r.e.op1_RNIF0O9F[29]\ : NOR3B - port map(A => \bpdata_i_m_0[13]\, B => \edata2_iv_1[29]\, C - => \bpdata_i_m_2[5]\, Y => edata2_iv_i_0(29)); - - \r.e.cwp_RNIHTJ61[2]\ : OR2A - port map(A => \cwp_2[2]\, B => aluresult_11_sqmuxa, Y => - \cwp_m[2]\); - - \r.m.icc_RNO_9[2]\ : NOR2 - port map(A => \logicout[4]\, B => \logicout[0]\, Y => - icc_0_sqmuxa_1_13); - - un6_ex_add_res_d2_ADD_33x33_fast_I310_Y_0 : AX1E - port map(A => I271_un1_Y_i_0, B => ADD_33x33_fast_I271_Y_0, - C => \un6_ex_add_res_s2_1[20]\, Y => - \un6_ex_add_res_s2[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I302_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[12]\, B => N808, Y => - \un6_ex_add_res_s2[12]\); - - \r.e.op1_RNI2B0N1[29]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[29]\, Y => - \ex_op1_i_m[29]\); - - \r.d.pv_RNO_5\ : OR3B - port map(A => pv, B => N_4239, C => ex_bpmiss_1_0, Y => - N_4240); - - \r.a.ctrl.pv_RNI6GFJ\ : OA1C - port map(A => pv_4, B => pv_5, C => pv_1, Y => - \npc_cnst_m_0[0]\); - - \r.m.y_RNI8BD92[16]\ : AOI1B - port map(A => \y[16]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[161]\, Y => \aluresult_1_iv_1[16]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I65_Y : MIN3 - port map(A => \data_0[14]\, B => \un1_iu0_6[14]\, C => - N436_2, Y => N524_1); - - \r.m.y_RNO_1[31]\ : OR3A - port map(A => \y_1[31]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[31]\); - - \r.e.jmpl_RNIATCQK2\ : NOR3C - port map(A => \shiftin_17_m[26]\, B => - \aluresult_1_iv_7[25]\, C => \shiftin_17_m_0[25]\, Y => - \aluresult_1_iv_9[25]\); - - \r.e.op2_RNO_3[11]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[11]\, Y - => \aluresult_m_i[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I135_Y\ : NOR3C - port map(A => N362, B => N365, C => N496_2, Y => N555); - - \r.e.aluop_RNII95R8[2]\ : OA1C - port map(A => edata_1_sqmuxa, B => \bpdata[10]\, C => - \bpdata_i_m_2[2]\, Y => \edata2_iv_2[26]\); - - \r.w.s.y_RNO[5]\ : MX2 - port map(A => \y_1[5]\, B => \result_0[5]\, S => N_481_0, Y - => N_3769); - - \r.w.result_RNIOFD4[19]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[19]\, - Y => \result_m_0_0[19]\); - - \r.m.ctrl.inst[30]\ : DFN1E0 - port map(D => \inst_2[30]\, CLK => lclk_c, E => holdn, Q - => \inst_1[30]\); - - \r.m.y[13]\ : DFN1E0 - port map(D => \y_1[13]\, CLK => lclk_c, E => holdn, Q => - \y[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I314_Y_0 : XNOR2 - port map(A => N780_1, B => ADD_33x33_fast_I314_Y_0_0, Y => - \un6_ex_add_res_s1_i[24]\); - - \r.f.pc_RNIA9TC9[2]\ : MX2 - port map(A => \fpc[2]\, B => ldbp2_1_RNIL7Q55, S => jump_0, - Y => N_4045); - - \comb.branch_address.tmp_ADD_30x30_fast_I137_un1_Y\ : OR3C - port map(A => N362, B => N365, C => N358, Y => I137_un1_Y_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I147_Y : AO1 - port map(A => N548, B => N545_2, C => N544_1, Y => N610_2); - - \r.a.ctrl.pc[11]\ : DFN1E0 - port map(D => \dpc[11]\, CLK => lclk_c, E => holdn, Q => - \pc[11]\); - - \r.w.result_RNI062L[19]\ : AOI1B - port map(A => \un1_p0_6[371]\, B => d14_0, C => - \result_m_0_0[19]\, Y => \d_iv_0[19]\); - - \r.m.y_RNIRDO71[14]\ : OR2B - port map(A => \y_0[14]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[14]\); - - \r.a.rsel2_0_RNIV6QD[0]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[356]\, Y => \cpi_m_i[356]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I173_Y : OR3C - port map(A => I113_un1_Y_i, B => ADD_33x33_fast_I113_Y_0_0, - C => I173_un1_Y_i, Y => N642_1); - - \r.d.pc_RNIQ5HB4[22]\ : MX2 - port map(A => \dpc[22]\, B => \fpc[22]\, S => ra_bpmiss_1, - Y => N_3899); - - un6_ex_add_res_d0_ADD_33x33_fast_I171_Y : OR2A - port map(A => I171_un1_Y_i, B => N574, Y => N640_0); - - \r.w.s.dwt_RNO\ : NOR2A - port map(A => rst, B => N_318, Y => N_170); - - \r.e.op2_RNO[16]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0, S => - \d_1[16]\, Y => N_300); - - \r.a.ctrl.inst_RNIJ42L_0[19]\ : NOR2 - port map(A => \inst_2[19]\, B => N_202, Y => N_226); - - \r.e.ldbp1_2\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_2); - - \r.a.imm_RNO[1]\ : NOR2B - port map(A => \inst_0_RNI1JUM[1]\, B => call_hold5, Y => - \un3_de_ren1[119]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I139_Y : AOI1 - port map(A => N540_1, B => N537_2, C => N536_2, Y => N602_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_o3_1_0 : MIN3 - port map(A => \op2[1]\, B => \un1_iu0_6[1]\, C => N397_0, Y - => ADD_33x33_fast_I206_Y_0_o3_1_0_0); - - \r.m.y_RNO_4[27]\ : OR2B - port map(A => \y[28]\, B => mulstep_1, Y => N_424); - - un6_ex_add_res_d0_ADD_33x33_fast_I294_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[4]\, B => N614_1, Y => - \un6_ex_add_res_s0[4]\); - - \r.e.ctrl.pc_RNIJ4A7J[27]\ : NOR3C - port map(A => \aluop_RNIEPDN4[2]\, B => - \aluresult_0_iv_2[27]\, C => \aluresult_0_iv_5[27]\, Y - => \aluresult_0_iv_6[27]\); - - \r.d.inst_0_0_0_RNIL4JE03[21]\ : MX2 - port map(A => data_0_2_21, B => \un1_p0_6_0[60]\, S => - inull_RNIFV6VG2_0, Y => N_4621); - - \r.a.rfa1_RNID98B1[4]\ : MX2 - port map(A => \un3_de_ren1[95]\, B => \rfa1[4]\, S => holdn, - Y => raddr1(4)); - - \r.x.ctrl.tt_RNI32K6[0]\ : NOR2B - port map(A => \tt[0]\, B => \tt[1]\, Y => tt_0); - - \r.e.ctrl.tt[0]\ : DFN1E0 - port map(D => \tt_1[0]\, CLK => lclk_c, E => holdn, Q => - \tt_2[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I268_un1_Y_0 : NOR2B - port map(A => N659, B => N643_1, Y => - ADD_33x33_fast_I268_un1_Y_0_0); - - \r.f.pc_RNO_1[13]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[13]\, C => - \pc_1_iv_0[13]\, Y => \pc_1_iv_1[13]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_un1_Y : OR2B - port map(A => ADD_33x33_fast_I261_un1_Y_0, B => N802, Y => - I261_un1_Y); - - \r.x.data_0_RNO[7]\ : OR3C - port map(A => \dco_m_i[119]\, B => \data_0_1_1_iv_1[7]\, C - => \dco_m_i[103]\, Y => \data_0_1[7]\); - - \r.m.y[10]\ : DFN1E0 - port map(D => \y_1[10]\, CLK => lclk_c, E => holdn, Q => - \y_0[10]\); - - \r.d.inull_RNIOT29\ : NOR3C - port map(A => annul_next_1_sqmuxa_1_1, B => - annul_next_1_sqmuxa_1_0, C => annul_next_1_sqmuxa_1_2, Y - => annul_next_1_sqmuxa_1_4); - - \r.e.shleft_RNIA62L1\ : MX2A - port map(A => \shiftin_5[30]\, B => \shiftin_5_i[14]\, S - => \ex_shcnt_1_i[4]\, Y => \shiftin_8[14]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I70_Y : NOR2B - port map(A => N434, B => N431_0, Y => N529_0); - - \r.m.ctrl.pc_RNIN6AE[2]\ : MX2 - port map(A => \pc_3[2]\, B => \pc[2]\, S => \npc_0[1]\, Y - => N_3243); - - \r.x.result_RNIE4OE[21]\ : OR2B - port map(A => \un1_p0_6[373]\, B => d14, Y => - \cpi_m_0[373]\); - - \r.f.pc[23]\ : DFN1E0 - port map(D => \pc_1[23]\, CLK => lclk_c, E => holdn, Q => - \fpc[23]\); - - \r.x.result_RNILIDE5[12]\ : NOR2B - port map(A => \bpdata[12]\, B => \aluop_RNIGM3N1[2]\, Y => - \bpdata_i_m[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I70_Y\ : MAJ3 - port map(A => \dpc[10]\, B => \inst_0[8]\, C => N379, Y => - N487_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I200_Y : NOR2A - port map(A => N611_0, B => N603_0, Y => N669_0); - - \r.e.aluop_0_RNIRSOT[2]\ : NOR2 - port map(A => aluresult_7_sqmuxa_0, B => logicout21_1, Y - => aluresult_7_sqmuxa); - - \r.d.annul_RNIVCQHS1\ : NOR2 - port map(A => un2_rstn_4_0, B => un2_rstn_5_2, Y => - annul_RNIVCQHS1); - - \r.x.result_RNIJTR65[6]\ : OR2B - port map(A => \bpdata[6]\, B => N_3957_1, Y => - \bpdata_m_1[6]\); - - \r.e.aluop_RNI83T5C[2]\ : OA1A - port map(A => aluresult_5_sqmuxa, B => \bpdata[13]\, C => - \aluresult_1_iv_2[29]\, Y => \aluresult_1_iv_4[29]\); - - \r.a.ctrl.inst_RNIB41E_0[23]\ : NOR2A - port map(A => \inst_1[24]\, B => \inst_1[23]\, Y => - aluop_2_1_0_a2_0); - - \r.x.ctrl.wicc_RNISFUM2_0\ : NOR2B - port map(A => icc_2_sqmuxa_2, B => cwp_1_sqmuxa, Y => - icc_2_sqmuxa); - - \r.x.ctrl.tt_RNO_0[5]\ : OR2B - port map(A => tt_0_sqmuxa, B => \tt_1[5]\, Y => N_4209); - - \comb.branch_address.tmp_ADD_30x30_fast_I12_G0N\ : NOR2B - port map(A => \inst_0[12]\, B => \dpc[14]\, Y => N394); - - \r.a.ctrl.inst_RNIICJA[28]\ : XNOR2 - port map(A => \inst_1[28]\, B => N_211, Y => branch_4); - - \r.x.result_RNI5M1O3[20]\ : MX2 - port map(A => \un1_iu0_6[20]\, B => \un1_p0_6[372]\, S => - bpdata6, Y => \bpdata[20]\); - - \r.m.ctrl.pc_RNIC9N9[16]\ : MX2 - port map(A => \pc_3[16]\, B => \pc_0[16]\, S => \npc[1]\, Y - => N_3257); - - \r.e.op2_RNO[27]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[27]\, Y => N_311); - - \r.d.annul_RNIRK1K4\ : NOR3A - port map(A => un6_rabpmiss_0, B => annul_1, C => - \ra_bpmiss_1_0\, Y => un6_rabpmiss_2); - - \r.w.s.wim_RNILSJV2[6]\ : NOR2B - port map(A => aluresult_8_sqmuxa_i, B => \wim_m[6]\, Y => - \aluresult_1_iv_0[6]\); - - \r.e.jmpl_RNI1EKJ51\ : AOI1B - port map(A => \shiftin_17[0]\, B => aluresult_2_sqmuxa_0, C - => \aluresult_2_iv_6[0]\, Y => \aluresult_2_iv_7[0]\); - - \r.m.ctrl.pc_RNIS1HF[13]\ : MX2 - port map(A => \pc_3[13]\, B => \pc[13]\, S => \npc_1[1]\, Y - => N_3254); - - \r.e.shleft_1_RNIQCHP\ : OR2A - port map(A => \un1_iu0_6[20]\, B => shleft_1, Y => - \shiftin_5[20]\); - - \r.w.s.y[2]\ : DFN1E0 - port map(D => N_3766, CLK => lclk_c, E => N_6922_i, Q => - \y[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.e.shleft_1_RNI5GVF3\ : MX2 - port map(A => \shiftin_5[52]\, B => \shiftin_5[36]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[36]\); - - \r.e.ctrl.inst_RNIJ0JA[25]\ : MX2 - port map(A => \icc[3]\, B => \icc[1]\, S => \inst_2[25]\, Y - => \inst_RNIJ0JA[25]\); - - \r.m.y_RNO_3[18]\ : AOI1B - port map(A => wy_1_0, B => \y[18]\, C => N_395, Y => - \y_iv_0_1[18]\); - - \r.m.dci.write_RNO_0\ : AXO5 - port map(A => write_3_0_a3_0_2_0, B => \cnt[0]\, C => - \cnt[1]\, Y => write_3_tz); - - \r.e.op2_RNO_7[15]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[367]\, Y => \cpi_m_i[367]\); - - \r.a.rsel1_0_RNI93LJ2[2]\ : OR2B - port map(A => data1(12), B => d11, Y => \rfo_m[12]\); - - \r.f.pc_RNO_7[26]\ : MX2 - port map(A => \fpc[26]\, B => \tba[14]\, S => rstate_6314_d, - Y => \xc_trap_address[26]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I144_Y : NOR2B - port map(A => N545_2, B => N541_1, Y => N607_0); - - \r.x.ctrl.tt_RNO_0[3]\ : OA1C - port map(A => iflush_4, B => trap_0_sqmuxa_2, C => - un1_trap_0_sqmuxa_5, Y => N_4201_i_0); - - \r.a.rfa2[3]\ : DFN1E0 - port map(D => \inst_0_RNI3RUM[3]\, CLK => lclk_c, E => - holdn, Q => \rfa2[3]\); - - \r.e.ldbp2_0_RNIM5MI31\ : MX2C - port map(A => \un6_ex_add_res_s1_i[13]\, B => N_6632, S => - ldbp2_0, Y => \eaddress[12]\); - - \r.e.jmpl_RNI30TCJ5\ : OR3C - port map(A => \aluresult_1_iv_8[20]\, B => - \shiftin_17_m_0[20]\, C => \un6_ex_add_res_m[21]\, Y => - \aluresult[20]\); - - \r.x.ctrl.rd_RNINVH6[6]\ : XNOR2 - port map(A => \rd_2[6]\, B => \rd_0[6]\, Y => rd_6_i_0); - - \r.e.op2_RNO_0[12]\ : OR3C - port map(A => \op1_m_i[12]\, B => \d_1_iv_3[12]\, C => - \aluresult_m_i[12]\, Y => \d_1[12]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I314_Y_0 : XOR2 - port map(A => N780_0, B => \un6_ex_add_res_s2_1[24]\, Y => - \un6_ex_add_res_s2[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I21_P0N\ : OR2 - port map(A => \un1_p0_6_0[60]\, B => \dpc[23]\, Y => N422); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_Y_1 : AO1 - port map(A => N650_0, B => N635_0, C => - ADD_33x33_fast_I264_Y_0_0, Y => ADD_33x33_fast_I264_Y_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I34_Y : NOR2A - port map(A => N488_0, B => N485_i, Y => N493_0); - - \r.w.s.ps_RNIHGNV8\ : NOR3 - port map(A => ps_i_m, B => s_i_m, C => \result_i_m[7]\, Y - => s_1_iv); - - \comb.ld_align.rdata199_RNINGRP32\ : NOR3B - port map(A => ld_0_0, B => \rdata_9_m_0[8]\, C => - rdata_1_sqmuxa_1, Y => \rdata_9_m[8]\); - - \r.e.op2[19]\ : DFN1E0 - port map(D => N_303, CLK => lclk_c, E => holdn, Q => - \op2[19]\); - - \r.m.ctrl.rd_RNILISE3[0]\ : NOR3C - port map(A => wreg_0_0, B => un1_de_ren1_1_3_i_0, C => - wreg_1_7, Y => wreg_3); - - \r.x.npc_0[0]\ : DFN1E0 - port map(D => \npc_1[0]\, CLK => lclk_c, E => holdn, Q => - \npc_0[0]\); - - \r.a.ctrl.inst_RNICO0S[31]\ : AO1C - port map(A => \inst[30]\, B => N_58, C => \inst[31]\, Y => - invop2_0_1_i_0); - - \r.m.ctrl.ld_RNI4LM47\ : OA1C - port map(A => N_227_0, B => \y_1[0]\, C => ldbp2_0_a5_0, Y - => ldbp2); - - \r.m.y_RNIF4K91[9]\ : OR2B - port map(A => \y_1[9]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[9]\); - - \r.e.ctrl.tt_RNO_0[5]\ : OR3A - port map(A => \tt_9_0_a3_0_1[5]\, B => fp_disabled_4, C => - N_4033_i, Y => N_4043_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I174_Y : NOR2B - port map(A => N585_0, B => N577_0, Y => N643_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I40_Y_i_o3 : OR2B - port map(A => N479_1, B => N476_1, Y => N_50_0); - - \r.m.y_RNO_1[25]\ : OR2B - port map(A => \y_1[26]\, B => mulstep_0, Y => \y_m_2[26]\); - - \r.e.op2_RNI0OG11[20]\ : OR2A - port map(A => \un1_iu0_5[86]\, B => \un1_iu0_6[20]\, Y => - \logicout_4[20]\); - - \r.m.result[31]\ : DFN1E0 - port map(D => \eres2[31]\, CLK => lclk_c, E => holdn, Q => - \maddress[31]\); - - \r.a.ctrl.inst_RNID81L[20]\ : OR2 - port map(A => \inst_2[20]\, B => N_216, Y => N_434); - - \comb.branch_address.tmp_ADD_30x30_fast_I286_Y_0\ : XOR2 - port map(A => N700, B => ADD_30x30_fast_I286_Y_0_0, Y => - \tmp[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I107_Y : OR2A - port map(A => I107_un1_Y_i, B => N504_1, Y => N570_1); - - \r.e.ctrl.pc[8]\ : DFN1E0 - port map(D => \pc[8]\, CLK => lclk_c, E => holdn, Q => - \pc_2[8]\); - - \r.e.op2_RNO_4[27]\ : OA1A - port map(A => \maddress[27]\, B => d27_0, C => - \cpi_m_i[379]\, Y => \d_1_iv_1[27]\); - - \r.e.op1[1]\ : DFN1E0 - port map(D => \aop1[1]\, CLK => lclk_c, E => holdn, Q => - \op1[1]\); - - \r.d.pc_RNO[17]\ : MX2 - port map(A => \fpc[17]\, B => \dpc[17]\, S => N_6763_i_0, Y - => \pc_RNO[17]\); - - \r.e.op1_RNI456I1[6]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[6]\, Y => - \ex_op1_i_m[6]\); - - \r.m.result_RNIBND4[30]\ : OR2B - port map(A => d13_0, B => \maddress[30]\, Y => - \result_m_0[30]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I137_Y : AO1B - port map(A => N538_0, B => N535_1, C => - ADD_33x33_fast_I137_Y_0_1, Y => N600_0); - - un23_ra_I_14 : XOR2 - port map(A => \cwp_0[2]\, B => - \DWACT_ADD_CI_0_g_array_1_1[0]\, Y => I_14_1); - - \r.e.op1_RNIOQ8G[22]\ : OR2B - port map(A => \op1[22]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[22]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I104_Y : NOR3C - port map(A => N473_1, B => N476_1, C => N505_1, Y => N567); - - \r.e.op2[9]\ : DFN1E0 - port map(D => N_293, CLK => lclk_c, E => holdn, Q => - \op2[9]\); - - \r.a.imm[24]\ : DFN1E0 - port map(D => \un3_de_ren1[142]\, CLK => lclk_c, E => holdn, - Q => \imm[24]\); - - \r.m.ctrl.pc[11]\ : DFN1E0 - port map(D => \pc_2[11]\, CLK => lclk_c, E => holdn, Q => - \pc_1[11]\); - - \r.f.pc_RNI17ATA5[10]\ : NOR2B - port map(A => \un6_fe_npc_m[8]\, B => - \xc_trap_address_m[10]\, Y => \npc_iv_2[10]\); - - \r.m.icc[0]\ : DFN1E0 - port map(D => \icco[0]\, CLK => lclk_c, E => holdn, Q => - \icc_0[0]\); - - \r.e.ctrl.inst_RNI312S[22]\ : NOR3A - port map(A => \inst[19]\, B => \inst_1[22]\, C => - aluresult_11_sqmuxa_4, Y => un3_op_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I302_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[12]\, B => N808_1, Y => - \un6_ex_add_res_s0[12]\); - - \r.a.rsel1[2]\ : DFN1E0 - port map(D => rs1, CLK => lclk_c, E => holdn, Q => - \rsel1[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I40_Y_i_o3 : OAI1 - port map(A => \data_0[27]\, B => \un1_iu0_6[27]\, C => - N476_2, Y => N_50_1); - - \r.e.op1_RNIH494A7[26]\ : NOR3C - port map(A => \op1_m_0[26]\, B => \d_iv_2[26]\, C => - \aluresult_m_0[26]\, Y => \d_i[26]\); - - \comb.cwp_ctrl.ncwp_3_I_15\ : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0[0]\, B => - \cwp_0[0]\, C => \DWACT_ADD_CI_0_g_array_0_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_3[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I131_Y\ : NOR2B - port map(A => N496_2, B => N492, Y => N551); - - \r.x.npc_0_RNIADT61[0]\ : MX2C - port map(A => N_3226, B => N_3256, S => \npc_0[0]\, Y => - \xc_result[15]\); - - \r.e.op1_RNIJO8M02[1]\ : OR3C - port map(A => \op1_m_0[1]\, B => \d_iv_2[1]\, C => - \aluresult_m_0[1]\, Y => \d[1]\); - - \r.e.aluop_0_RNI4LVG[2]\ : XA1 - port map(A => \op2_RNI59C6[0]\, B => \aluop_0[2]\, C => - \un1_iu0_6[0]\, Y => N_3527); - - \r.m.y_RNO_2[16]\ : OR2A - port map(A => \logicout[16]\, B => y14, Y => - \logicout_m[16]\); - - \r.f.pc_RNO_4[14]\ : MX2 - port map(A => I_73, B => N_4057, S => bpmiss_1_i_0, Y => - \pc_4[14]\); - - \r.d.cnt_RNI338J[0]\ : OR3A - port map(A => un13_op3, B => call_hold7_i, C => un52_casaen, - Y => hold_pc_2_sqmuxa); - - \r.x.result_RNIL3RV[0]\ : NOR2B - port map(A => \un1_p0_6[352]\, B => N_6357, Y => \wdata[0]\); - - \r.x.ctrl.inst_RNIF32S[19]\ : NOR3B - port map(A => \inst[20]\, B => wim_1_sqmuxa_0, C => - \inst_1[19]\, Y => wim_1_sqmuxa_1); - - \r.e.ldbp2_RNI6L12M4\ : OR2A - port map(A => \eaddress[28]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[29]\); - - \r.d.inst_0_RNI5C23[31]\ : OR2B - port map(A => \inst_0[31]\, B => \inst_0[30]\, Y => - call_hold7_i); - - \r.w.s.y_RNO_2[24]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[24]\, Y - => N_369); - - \r.m.icc_RNIA6A3[1]\ : XNOR2 - port map(A => \inst_0[28]\, B => \icc[1]\, Y => branch_8_i); - - \r.a.ctrl.inst[5]\ : DFN1E0 - port map(D => \inst_0[5]\, CLK => lclk_c, E => holdn, Q => - \inst[5]\); - - \r.d.annul_RNI8MUI42\ : OR3A - port map(A => \tmp[9]\, B => un2_rstn_5_2, C => - \un2_rstn_5_0_0\, Y => \tmp_m[9]\); - - \r.x.result_RNIFL0C3[3]\ : MX2 - port map(A => \un1_iu0_6[3]\, B => \un1_p0_6[355]\, S => - bpdata6, Y => \bpdata[3]\); - - \r.e.op2_RNO_7[7]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[359]\, Y => \cpi_m_i[359]\); - - \r.d.inst_0_RNO[10]\ : NOR2B - port map(A => rst, B => N_4610, Y => \inst_0_RNO[10]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I181_un1_Y : OR2B - port map(A => N592_1, B => N585_1, Y => I181_un1_Y_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I33_un1_Y : OR3B - port map(A => \un1_iu0_6[29]\, B => N488_2, C => - \data_0_0[29]\, Y => I33_un1_Y_1); - - \r.e.invop2_RNI18F2G2\ : MX2C - port map(A => \un6_ex_add_res_s2[26]\, B => - \un6_ex_add_res_s0[26]\, S => invop2, Y => N_6657); - - \r.d.inst_0_RNIAO79[23]\ : NOR3 - port map(A => \inst_0[30]\, B => \inst_0_0[23]\, C => - \un1_p0_6_0[60]\, Y => ldcheck1_5_i_a6_1_1); - - \comb.un6_xc_exception_RNI2Q3D\ : NAND2 - port map(A => un6_xc_exception, B => - \xc_trap_address_m_0[3]\, Y => \xc_trap_address_m[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I19_G0N : OA1 - port map(A => \op1[18]\, B => ldbp1_3, C => \data_0_0[18]\, - Y => N451_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I15_G0N : NOR3A - port map(A => \op1[14]\, B => ldbp1_0, C => \data_0[14]\, Y - => N439_0); - - \r.x.result_RNIHHR65[5]\ : OR2B - port map(A => \bpdata[5]\, B => N_3957_1, Y => - \bpdata_m_1[5]\); - - \r.m.result_RNIJ85P[4]\ : NOR3C - port map(A => \result_m_0[4]\, B => \cpi_m_0[356]\, C => - \result_m_0_0[4]\, Y => \d_iv_1[4]\); - - \r.e.shcnt_RNI7AMS6[3]\ : MX2 - port map(A => \shiftin_8[36]\, B => \shiftin_8[28]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[28]\); - - \r.a.rfa1[6]\ : DFN1E0 - port map(D => \un3_de_ren1[97]\, CLK => lclk_c, E => holdn, - Q => \rfa1[6]\); - - \r.d.inst_0_RNIANSA[17]\ : OR2B - port map(A => I_14_1, B => un26_rs1opt, Y => - \de_raddr1_2[6]\); - - \r.e.op1[6]\ : DFN1E0 - port map(D => \aop1[6]\, CLK => lclk_c, E => holdn, Q => - \op1[6]\); - - \r.a.ctrl.inst_RNIGS1E[19]\ : NOR2A - port map(A => \inst_1[24]\, B => \inst_2[19]\, Y => - illegal_inst37_2); - - \r.m.y_RNI08OJF[16]\ : NOR3C - port map(A => \aluresult_1_iv_3[16]\, B => - \aluresult_1_iv_2[16]\, C => \bpdata_m_1[0]\, Y => - \aluresult_1_iv_5[16]\); - - \r.m.y_RNO_0[12]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[12]\, C => \y_m_0[12]\, - Y => \y_iv_1[12]\); - - \r.e.op2_RNO_8[5]\ : OR3B - port map(A => d29_0_0, B => \imm[5]\, C => \rsel2_0[0]\, Y - => \imm_m_i[5]\); - - \r.e.aluop_1_RNIQVV83[1]\ : MX2C - port map(A => \logicout_4[21]\, B => N_6904_i, S => - N_6866_i, Y => N_3644); - - \r.x.data_0_RNIHJ9E[27]\ : XOR2 - port map(A => \data_0[27]\, B => invop2_1, Y => N_4274); - - \r.x.data_0_RNIFF9E[19]\ : XOR2 - port map(A => \data_0[19]\, B => invop2_0, Y => N_4266); - - \r.x.rstate_RNI5S7L[1]\ : OR2 - port map(A => annul_1_0, B => \rstate_d[2]\, Y => - rstate_7_0); - - \r.e.ctrl.rd_RNI85J65[1]\ : NOR3C - port map(A => wreg_1_2, B => wreg_1_1, C => - \rd_RNIQP6H1[7]\, Y => wreg_1_4); - - \r.m.ctrl.tt[3]\ : DFN1E0 - port map(D => \tt_5[3]\, CLK => lclk_c, E => holdn, Q => - \tt_2[3]\); - - \r.e.op1[25]\ : DFN1E0 - port map(D => \aop1[25]\, CLK => lclk_c, E => holdn, Q => - \op1[25]\); - - \r.w.s.tba_RNIKCQJF[3]\ : NOR3C - port map(A => \aluresult_1_iv_2[15]\, B => \tba_m[3]\, C - => \aluresult_1_iv_4[15]\, Y => \aluresult_1_iv_5[15]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I295_Y_0 : AX1D - port map(A => N406_1, B => ADD_33x33_fast_I206_Y_0_a3_0, C - => \un6_ex_add_res_s2_1[5]\, Y => \un6_ex_add_res_s2[5]\); - - \r.e.op1_RNIU6NF[21]\ : NOR2A - port map(A => un17_casaen_0, B => \op1[21]\, Y => - \op1_i_m[21]\); - - \r.m.y_RNO_0[21]\ : NOR3C - port map(A => \y_m[21]\, B => \y_m_0[21]\, C => - \y_iv_0[21]\, Y => \y_iv_2[21]\); - - \r.w.s.ps_RNIF5EF2\ : NOR2 - port map(A => s_2_sqmuxa, B => ps, Y => ps_i_m); - - \r.x.result_RNIRS6E[31]\ : MX2 - port map(A => \result_0[31]\, B => \data_0_0[31]\, S => - ld_4, Y => \un1_p0_6[383]\); - - \r.e.aluop_RNIGHSC4[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[26]\, Y => - \bpdata_i_m[26]\); - - \r.d.inst_0_RNIA7PNP9[29]\ : OA1C - port map(A => ldlock, B => annul_4, C => holdn, Y => - N_6825_i); - - \r.x.data_0_RNIBJ9E[22]\ : XNOR2 - port map(A => \data_0_0[22]\, B => invop2_0, Y => N_4269_i); - - \r.e.aluop_0_RNIUE2QL[0]\ : AOI1B - port map(A => \logicout[15]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_5[15]\, Y => \aluresult_1_iv_6[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I156_Y : NOR3A - port map(A => N493_0, B => N497_2, C => N567_2, Y => N625); - - \un1_r.w.s.cwp_1_SUM0_0\ : XNOR2 - port map(A => \rstate_RNIRDFU5[1]\, B => \cwp[0]\, Y => - N_6527); - - \r.f.pc_RNO_1[25]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[25]\, C => - \pc_1_iv_0[25]\, Y => \pc_1_iv_1[25]\); - - \r.a.ctrl.inst_RNI2H3H1[23]\ : NOR2 - port map(A => illegal_inst12_0, B => illegal_inst12_tz_tz, - Y => illegal_inst12); - - \r.w.s.cwp[2]\ : DFN1E0 - port map(D => \cwp_1_0[2]\, CLK => lclk_c, E => holdn, Q - => \cwp[2]\); - - \r.d.inst_0_RNI1HLVD2[21]\ : OR2A - port map(A => N_145, B => N_143, Y => N_150); - - \r.e.ldbp2_2_RNI64M357\ : AO1C - port map(A => aluresult_0_sqmuxa_0, B => \eaddress[27]\, C - => \aluresult_0_iv_9[27]\, Y => \aluresult[27]\); - - \r.d.pc_RNO[30]\ : MX2 - port map(A => \fpc[30]\, B => \dpc[30]\, S => N_6763_i, Y - => \pc_RNO[30]\); - - \r.a.imm_RNO[6]\ : NOR2B - port map(A => \inst_0[6]\, B => call_hold5, Y => - \un3_de_ren1[124]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I136_Y : OR2B - port map(A => N537_1, B => N533_0, Y => N599_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I242_Y\ : OR2B - port map(A => ADD_30x30_fast_I242_Y_0, B => I210_un1_Y, Y - => N714); - - \r.d.inull_RNIVKU2\ : NOR2 - port map(A => \inull\, B => \inst_0[26]\, Y => - annul_next_1_sqmuxa_1_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I266_Y_0_0\ : XOR2 - port map(A => \dpc[8]\, B => \inst_0[6]\, Y => - ADD_30x30_fast_I266_Y_0_0); - - \r.m.y_RNO_3[4]\ : AOI1B - port map(A => \y[4]\, B => y08_0, C => \y_m[5]\, Y => - \y_iv_0[4]\); - - \r.e.op2_RNIQCAP[5]\ : OR2A - port map(A => \un1_iu0_5[71]\, B => \un1_iu0_6[5]\, Y => - \logicout_4[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I48_Y_i : NOR2B - port map(A => N467, B => N464, Y => N_15_i); - - \comb.branch_address.tmp_ADD_30x30_fast_I283_Y_0_0\ : XOR2 - port map(A => \dpc[25]\, B => \inst_0_1[25]\, Y => - ADD_30x30_fast_I283_Y_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I77_Y : AO13 - port map(A => N418_0, B => \un1_iu0_6[8]\, C => \data_0[8]\, - Y => N536_0); - - \r.w.s.s_RNO\ : OR2A - port map(A => rst, B => N_4943, Y => s_RNO); - - \r.a.ctrl.inst_RNIQO231[23]\ : OR2A - port map(A => inst_21_1, B => N_225, Y => inst_21); - - \r.e.op1_RNO[11]\ : MX2C - port map(A => \d_i[11]\, B => \d_i[12]\, S => N_227, Y => - \aop1[11]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I312_Y_0_1 : XOR2 - port map(A => \data_0[21]\, B => \un1_iu0_6[21]\, Y => - \un6_ex_add_res_s2_1[22]\); - - \r.x.ctrl.rd_RNI4SGO[0]\ : OA1B - port map(A => N_6352, B => \rd_0[0]\, C => \rstate[0]\, Y - => waddr(0)); - - \r.f.pc_RNO_5[13]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[13]\, Y => \xc_trap_address_m[13]\); - - \r.e.op2_RNO[17]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[17]\, Y => N_301); - - \r.e.op1_RNIOM8G[31]\ : OR2B - port map(A => \op1[31]\, B => un14_casaen_s1_0, Y => - \op1_m_0[31]\); - - \r.x.data_0[26]\ : DFN1E0 - port map(D => \data_0_1[26]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[26]\); - - \r.f.pc_RNO_4[24]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[24]\, Y => \xc_trap_address_m[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I50_Y\ : AO13 - port map(A => \inst_0[18]\, B => \dpc[20]\, C => N409_2, Y - => N467_1); - - \r.f.pc_RNO_0[5]\ : NOR3C - port map(A => \un6_ex_add_res_m_1[6]\, B => \pc_1_iv_0[5]\, - C => \tmp_m[5]\, Y => \pc_1_iv_2[5]\); - - un6_fe_npc_I_196 : XOR2 - port map(A => N_14_0, B => \fe_pc[29]\, Y => I_196); - - \r.f.pc_RNO_0[9]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[9]\, C => - \pc_1_iv_0[9]\, Y => \pc_1_iv_1[9]\); - - \r.a.ctrl.rett\ : DFN1E0 - port map(D => rett_1_2, CLK => lclk_c, E => holdn, Q => - rett_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I13_P0N : OR3A - port map(A => \data_0_2[12]\, B => \op1[12]\, C => ldbp1_0, - Y => N434); - - un6_ex_add_res_d2_ADD_33x33_fast_I21_P0N : AO1A - port map(A => ldbp1, B => \op1[20]\, C => \data_0_2[20]\, Y - => N458_0); - - \r.x.result_RNI1VVN5[7]\ : OR2A - port map(A => N_3687, B => \bpdata[7]\, Y => - \bpdata_i_m[7]\); - - \comb.lock_gen.un1_icc_check5_RNO_0\ : OA1A - port map(A => icc_check6_0, B => un7_op_3, C => - un1_icc_check5_0, Y => un1_icc_check5_1); - - \r.e.op2_RNO_0[23]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[23]\, C - => \d_1_iv_4[23]\, Y => \d_1[23]\); - - \r.w.s.y_RNO_2[27]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[27]\, Y - => N_411); - - \r.e.op1_RNO[31]\ : MX2C - port map(A => \d_i[31]\, B => \aop1_1_i[31]\, S => N_227, Y - => \aop1[31]\); - - \r.e.ctrl.inst_RNI1L1S[20]\ : NOR3A - port map(A => \inst_1[20]\, B => \inst_0[23]\, C => - aluresult_13_sqmuxa_3, Y => aluresult_13_sqmuxa_1); - - \r.d.inst_0_RNI4023[20]\ : OR2B - port map(A => \inst_0[20]\, B => \inst_0[19]\, Y => N_67); - - \r.x.rstate_RNI7VQQ1[0]\ : MX2C - port map(A => N_3396, B => \xc_result[5]\, S => \rstate[0]\, - Y => \wdata[5]\); - - \r.w.result[6]\ : DFN1E0 - port map(D => \wdata[6]\, CLK => lclk_c, E => holdn, Q => - \result[6]\); - - \r.w.s.wim[1]\ : DFN1E0 - port map(D => \wim_1[1]\, CLK => lclk_c, E => holdn, Q => - \wim[1]\); - - \r.x.data_0[3]\ : DFN1E0 - port map(D => \data_0_1[3]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I273_Y_0\ : XOR2 - port map(A => N729, B => ADD_30x30_fast_I273_Y_0_0, Y => - \tmp[15]\); - - \r.x.npc_RNIU4VI[0]\ : MX2C - port map(A => N_3214, B => N_3244, S => \npc[0]\, Y => - \xc_result[3]\); - - \r.d.inst_0_RNI4423[24]\ : NOR2B - port map(A => \inst_0_0[24]\, B => \inst_0_0[22]\, Y => - N_3736_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I322_Y_0_0 : XOR2 - port map(A => \op2[31]\, B => \un1_iu0_6[31]\, Y => - ADD_33x33_fast_I322_Y_0_0); - - \r.e.shleft_RNIHEFF\ : OR2A - port map(A => \un1_iu0_6[28]\, B => shleft, Y => - \shiftin_5[28]\); - - \r.x.rstate_0[0]\ : DFN1 - port map(D => N_6322s, CLK => lclk_c, Q => \rstate_0[0]\); - - \r.m.ctrl.inst[24]\ : DFN1E0 - port map(D => \inst[24]\, CLK => lclk_c, E => holdn, Q => - \inst_0[24]\); - - \r.f.pc_RNO_5[25]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[25]\, Y => \xc_trap_address_m[25]\); - - \r.e.aluop_RNIB3P34[1]\ : OR2B - port map(A => \bpdata[2]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[2]\); - - \comb.cwp_ctrl.ncwp_3_I_11\ : XNOR2 - port map(A => \inst_0[19]\, B => \cwp_0[2]\, Y => - \DWACT_ADD_CI_0_partial_sum[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I6_G0N : NOR2B - port map(A => \un1_iu0_6[5]\, B => \op2[5]\, Y => N412_1); - - \r.f.pc[9]\ : DFN1E0 - port map(D => \pc_1[9]\, CLK => lclk_c, E => holdn, Q => - \fpc[9]\); - - \r.e.aluop_RNIR7511[2]\ : XA1 - port map(A => \op2_RNI1LHG[1]\, B => \aluop_1[2]\, C => - \un1_iu0_6[1]\, Y => N_3528); - - \r.e.ldbp2_0_RNIHIRU31\ : OR2A - port map(A => \eaddress[12]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[13]\); - - \r.a.ctrl.rd[4]\ : DFN1E0 - port map(D => N_33, CLK => lclk_c, E => holdn, Q => - \rd_1[4]\); - - \r.a.rsel1[0]\ : DFN1E0 - port map(D => \osel[0]\, CLK => lclk_c, E => holdn, Q => - \rsel1[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I172_Y : NOR2B - port map(A => N583_2, B => N575_2, Y => N641); - - \r.d.inst_0_RNILEV6[19]\ : NOR3B - port map(A => \inst_0[19]\, B => un11_op, C => - \inst_0_0[22]\, Y => un14_op_1); - - \r.e.aluop_RNIKVVH6[0]\ : MX2 - port map(A => N_3580, B => N_3644, S => \aluop_1[0]\, Y => - \logicout[21]\); - - un6_fe_npc_I_166 : XOR2 - port map(A => N_35_0, B => \fe_pc[26]\, Y => I_166); - - un6_ex_add_res_d1_ADD_33x33_fast_I199_Y : AO1A - port map(A => N603_0, B => N610_2, C => N602_0, Y => N668); - - \r.e.aluop_2_RNI9AV11[1]\ : MX2C - port map(A => N_3527, B => \logicout_3[0]\, S => - \aluop_2[1]\, Y => N_3559); - - \r.w.s.y_RNO_0[18]\ : NOR2A - port map(A => N_481, B => \result_0[18]\, Y => N_391); - - \r.e.aluop_1_RNIUUU83[1]\ : MX2C - port map(A => \logicout_4[10]\, B => N_6844, S => N_6866_i, - Y => N_3633); - - \r.w.s.y[17]\ : DFN1E0 - port map(D => N_3781, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[17]\); - - un2_rstn_5_RNIL50VA : NAND2 - port map(A => \tmp[11]\, B => \un2_rstn_5\, Y => N_6620); - - \r.m.ctrl.inst_RNI4D1E_0[19]\ : NOR2B - port map(A => \inst_3[20]\, B => \inst_3[19]\, Y => - iflush_1); - - \r.e.op2_RNO_2[17]\ : NOR3C - port map(A => \d_1_iv_1[17]\, B => \d_1_iv_0[17]\, C => - \rfo_m_i[49]\, Y => \d_1_iv_3[17]\); - - \r.e.jmpl_RNIS1V9M\ : OR2B - port map(A => \shiftin_17[9]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[9]\); - - \r.m.y_RNO_4[21]\ : OR2B - port map(A => \y[22]\, B => mulstep_0, Y => \y_m_0[22]\); - - \r.x.result_RNI606K6[5]\ : OA1C - port map(A => \result_0[5]\, B => cwp_1_sqmuxa_0, C => et_m, - Y => N_3029); - - \comb.branch_address.tmp_ADD_30x30_fast_I176_un1_Y\ : NOR2A - port map(A => N550, B => N543, Y => I176_un1_Y); - - \r.e.su_RNI28U5D\ : NOR3C - port map(A => \aluresult_1_iv_4[7]\, B => - \aluresult_1_iv_3[7]\, C => \logicout_m_0[7]\, Y => - \aluresult_1_iv_6[7]\); - - \r.f.pc_RNIIOQV1[11]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[11]\, Y => \xc_trap_address_m[11]\); - - \r.e.aluop_1_RNIN0ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[21]\, B => \aluop_1[1]\, C => - \un1_iu0_5[87]\, Y => N_6904_i); - - \r.m.y_RNO_3[25]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y[25]\, C => \y_m[25]\, Y - => \y_iv_1[25]\); - - \r.e.jmpl_RNI4HD5L\ : OR2B - port map(A => \shiftin_17[4]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[4]\); - - \comb.ld_align.rdata199_RNI46JTI\ : OR2 - port map(A => rdata_1_sqmuxa_0, B => rdata199, Y => - rdata_1_sqmuxa_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I61_Y\ : OA1 - port map(A => \dpc[14]\, B => \inst_0[12]\, C => N398_2, Y - => N478_0); - - \r.d.inst_0_RNI9AJ4[28]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[28]\, S => - \inst_0[30]\, Y => \inst_0_1[30]\); - - \r.e.op1_RNO[18]\ : MX2C - port map(A => \d_i[18]\, B => \d_i[19]\, S => N_227_0, Y - => \aop1[18]\); - - \r.x.rstate_RNIC27D2[0]\ : MX2C - port map(A => N_3420, B => \xc_result[29]\, S => - \rstate[0]\, Y => \wdata[29]\); - - \r.e.shleft_0_RNIV7VF3\ : MX2 - port map(A => \shiftin_5[51]\, B => \shiftin_5[35]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[35]\); - - \r.e.aluop_RNIPG1E1[1]\ : MX2C - port map(A => N_3531, B => \logicout_3[4]\, S => - \aluop_3[1]\, Y => N_3563); - - \r.a.rsel1_RNI5LB_0[0]\ : NOR2A - port map(A => \rsel1[1]\, B => \rsel1[0]\, Y => N_484); - - un6_ex_add_res_d2_ADD_33x33_fast_I145_Y : AO1B - port map(A => N546_0, B => N543_1, C => - ADD_33x33_fast_I145_Y_0_1, Y => N608_0); - - \r.e.aluop_0_RNI68HG3[0]\ : MX2C - port map(A => N_3565, B => N_3629, S => \aluop_0[0]\, Y => - \logicout[6]\); - - \r.a.ctrl.pc_RNII8F2C[29]\ : MX2 - port map(A => \pc[29]\, B => N_3906, S => ex_bpmiss_1_0, Y - => \fe_pc[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I260_Y_2 : NOR3C - port map(A => I97_un1_Y, B => ADD_33x33_fast_I260_Y_0_0, C - => I157_un1_Y_i, Y => ADD_33x33_fast_I260_Y_2_0); - - \r.e.aluop_0_RNIH37O1[1]\ : MX2C - port map(A => \logicout_4[3]\, B => N_6829, S => N_6866_i_0, - Y => N_3626); - - \r.e.aluop_0_RNIEMIQG[0]\ : NOR2B - port map(A => \bpdata_m[3]\, B => \aluresult_1_iv_4[3]\, Y - => \aluresult_1_iv_5[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I45_Y\ : NOR2B - port map(A => N422, B => N419_2, Y => N462); - - \r.a.ctrl.pc_RNIQ7E2C[21]\ : MX2 - port map(A => \pc[21]\, B => N_3898, S => ex_bpmiss_1_0, Y - => \fe_pc[21]\); - - \r.d.pc[20]\ : DFN1 - port map(D => \pc_RNO[20]\, CLK => lclk_c, Q => \dpc[20]\); - - \r.e.op2_RNIUAOP[14]\ : MX2 - port map(A => \op2[14]\, B => N_4261, S => ldbp2_2, Y => - \un1_iu0_5[80]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I77_Y\ : OA1 - port map(A => \dpc[7]\, B => \inst_0[5]\, C => N371, Y => - N494); - - \r.e.ldbp2_RNI3BS185\ : OR2A - port map(A => \eaddress[30]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[31]\); - - \r.m.y_RNO_1[12]\ : AOI1B - port map(A => \y[12]\, B => y08_0, C => \y_m[13]\, Y => - \y_iv_0[12]\); - - \r.m.ctrl.inst[27]\ : DFN1E0 - port map(D => \inst_1[27]\, CLK => lclk_c, E => holdn, Q - => \inst_3[27]\); - - \r.e.cwp_RNIFULQD[2]\ : NOR3C - port map(A => \aluresult_2_iv_3[2]\, B => - \aluresult_2_iv_2[2]\, C => \logicout_m_0[2]\, Y => - \aluresult_2_iv_5[2]\); - - \r.e.ldbp2_2\ : DFN1E0 - port map(D => ldbp2, CLK => lclk_c, E => holdn, Q => - ldbp2_2); - - \r.e.op2_RNO_6[23]\ : OR3B - port map(A => d29_0, B => \imm[23]\, C => \rsel2[0]\, Y => - \imm_m_i[23]\); - - \r.m.ctrl.wicc_RNILN9L\ : MX2C - port map(A => N_4180, B => \icc_0[0]\, S => wicc_3, Y => - N_4185); - - \r.f.pc[27]\ : DFN1E0 - port map(D => \pc_1[27]\, CLK => lclk_c, E => holdn, Q => - \fpc[27]\); - - \r.e.invop2_0_RNILIU7M\ : MX2C - port map(A => \un6_ex_add_res_s2[13]\, B => - \un6_ex_add_res_s0[13]\, S => invop2_0, Y => N_6632); - - un6_ex_add_res_d2_ADD_33x33_fast_I321_Y_0_1 : XOR2 - port map(A => \data_0[30]\, B => \un1_iu0_6[30]\, Y => - \un6_ex_add_res_s2_1[31]\); - - un6_fe_npc_I_143 : XOR2 - port map(A => N_51, B => \fe_pc[24]\, Y => I_143); - - \r.m.y_RNI1EMI4[13]\ : NOR3C - port map(A => \ex_op2_m[13]\, B => aluresult_8_sqmuxa_i, C - => \aluresult_1_iv_1[13]\, Y => \aluresult_1_iv_2[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I66_Y : AND2 - port map(A => N437_0, B => N440, Y => N525); - - \r.m.y_RNO_2[23]\ : OR2 - port map(A => y14, B => \logicout[23]\, Y => \y_RNO_2[23]\); - - \r.d.inst_0_RNO[28]\ : NOR2B - port map(A => rst, B => N_4628, Y => \inst_0_RNO[28]\); - - \r.x.y[28]\ : DFN1E0 - port map(D => \y[28]\, CLK => lclk_c, E => holdn, Q => - \y_2[28]\); - - \r.m.result[27]\ : DFN1E0 - port map(D => \eres2[27]\, CLK => lclk_c, E => holdn, Q => - \maddress[27]\); - - \r.x.data_0_RNO_0[27]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_27, Y => - \dco_m_1[123]\); - - \r.x.laddr_RNIF5HB51_0[1]\ : NOR3C - port map(A => \me_laddr_2[1]\, B => rdata200, C => ld_0_0, - Y => rdata_4_sqmuxa); - - \r.e.ctrl.tt[3]\ : DFN1E0 - port map(D => \tt_0[3]\, CLK => lclk_c, E => holdn, Q => - \tt_5[3]\); - - \r.x.data_0_RNO_2[10]\ : OA1A - port map(A => data_0_0_26, B => rdata_5_sqmuxa, C => - \data_0_m_i[10]\, Y => \data_0_1_0_iv_0[10]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I175_Y : AO1 - port map(A => N586_0, B => N579_1, C => N578_0, Y => N644_0); - - \r.e.op1[30]\ : DFN1E0 - port map(D => \aop1[30]\, CLK => lclk_c, E => holdn, Q => - \op1[30]\); - - \r.w.s.ps_RNI76J61\ : OR2A - port map(A => ps, B => aluresult_11_sqmuxa, Y => ps_m_0); - - \r.e.ldbp2_1_RNI1B7RI2\ : AO1C - port map(A => aluresult_0_sqmuxa_0, B => \eaddress[8]\, C - => \aluresult_1_iv_9[8]\, Y => \aluresult[8]\); - - \r.a.ctrl.wicc_RNO\ : OA1B - port map(A => wicc_1_0_a3_0_0, B => wicc_1_0_tz_0, C => - N_143, Y => wicc_1); - - \r.x.ctrl.inst_RNISL1E[22]\ : NOR2B - port map(A => \inst_0[22]\, B => \inst_1[19]\, Y => y10_3_0); - - \r.w.s.tba_RNIA4CA1[9]\ : OR2B - port map(A => \tba[9]\, B => aluresult_12_sqmuxa, Y => - \tba_m[9]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I33_un1_Y : NAND2 - port map(A => N484_0, B => N488_0, Y => I33_un1_Y_0); - - \r.x.y[31]\ : DFN1E0 - port map(D => \y[31]\, CLK => lclk_c, E => holdn, Q => - \y_1[31]\); - - \r.m.y_RNO_2[30]\ : OR2B - port map(A => \y[30]\, B => y08, Y => \y_m_0[30]\); - - \r.x.result_RNISIVN5[6]\ : OR2A - port map(A => N_3687, B => \bpdata[6]\, Y => - \bpdata_i_m[6]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I266_Y_0_o3 : OR2A - port map(A => N_74_i, B => N506, Y => N778); - - \r.x.data_0_RNO_1[20]\ : NOR2A - port map(A => \data_0_2[20]\, B => ld_3, Y => - \data_0_m[20]\); - - \r.a.ctrl.wy_RNO_0\ : NOR3B - port map(A => wy_1_0_a3_0_7_1, B => wy_1_0_a3_0_7_2, C => - un7_op_3, Y => wy_1_0_a3_0_4); - - \r.a.ctrl.inst_RNIDG1E[21]\ : XNOR2 - port map(A => \inst_2[19]\, B => \inst_2[21]\, Y => N_209); - - \r.f.pc_RNO_0[14]\ : OR2B - port map(A => I_73, B => annul_RNIVCQHS1, Y => N_29); - - \r.m.result_RNI20P1[18]\ : OR2B - port map(A => d13, B => \maddress[18]\, Y => - \result_m_0[18]\); - - \r.e.ctrl.pc_RNIBCTN2[31]\ : AOI1 - port map(A => \pc[31]\, B => jmpl_0, C => \aluresult_6[31]\, - Y => \aluresult_1_iv_1[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I135_Y : AO1 - port map(A => N536_1, B => N533_0, C => N532_0, Y => N598_1); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.a.bp_RNIKBBRB_0\ : NOR2B - port map(A => \ra_bpmiss_1_0\, B => ex_bpmiss_1_0, Y => - bpmiss_1_i_0_0); - - \r.f.pc_RNO_7[16]\ : MX2 - port map(A => \fpc[16]\, B => \tba[4]\, S => rstate_6314_d, - Y => \xc_trap_address[16]\); - - \r.e.ctrl.inst[20]\ : DFN1E0 - port map(D => \inst_2[20]\, CLK => lclk_c, E => holdn, Q - => \inst_1[20]\); - - \r.e.op1[14]\ : DFN1E0 - port map(D => \aop1[14]\, CLK => lclk_c, E => holdn, Q => - \op1[14]\); - - \r.a.ctrl.cnt_RNILD6A1[0]\ : OR3 - port map(A => aluop_2_1_0_a5_1_0, B => N_519, C => N_232, Y - => \cnt_RNILD6A1[0]\); - - \r.m.result_RNIT6SC3[9]\ : AOI1B - port map(A => data1(9), B => d11_0, C => \d_iv_1[9]\, Y => - \d_iv_2[9]\); - - \r.m.result_RNO[31]\ : MX2 - port map(A => \aluresult[31]\, B => \op1[31]\, S => - un17_casaen_0_1, Y => \eres2[31]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I197_un1_Y : OR2B - port map(A => N608, B => N601_0, Y => I197_un1_Y_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I53_Y : MAJ3 - port map(A => \data_0_2[20]\, B => \un1_iu0_6[20]\, C => - N454_1, Y => N512_1); - - \r.e.op2_RNI4GMB1_0[31]\ : OR2 - port map(A => \un1_iu0_6[31]\, B => \un1_iu0_5[97]\, Y => - \logicout_3[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I130_Y_0 : OAI1 - port map(A => \data_0[10]\, B => \un1_iu0_6[10]\, C => - N431_2, Y => ADD_33x33_fast_I130_Y_0_1); - - \r.e.ldbp2_1\ : DFN1E0 - port map(D => ldbp2, CLK => lclk_c, E => holdn, Q => - ldbp2_1); - - \r.e.ctrl.cnt_RNI6U9K1[0]\ : NOR3C - port map(A => N_3749_3, B => enaddr_2_sqmuxa_0, C => - enaddr_2_sqmuxa_1, Y => enaddr_2_sqmuxa_3); - - \r.a.imm[7]\ : DFN1E0 - port map(D => \un3_de_ren1[125]\, CLK => lclk_c, E => holdn, - Q => \imm[7]\); - - \r.a.ctrl.inst_RNICT362[31]\ : OR2B - port map(A => N_473_i, B => N_344, Y => N_230); - - \r.w.s.tba_RNI24CA1[1]\ : OR2B - port map(A => \tba[1]\, B => aluresult_12_sqmuxa, Y => - \tba_m[1]\); - - \r.e.op1_RNIQ2CR1[31]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[31]\, Y => - un4_icc_m); - - \r.e.aluop_RNICHD84[0]\ : MX2C - port map(A => N_3561, B => N_3625, S => \aluop_1[0]\, Y => - \logicout[2]\); - - \r.e.aluop_2_RNIVH5R2[1]\ : MX2C - port map(A => N_3542, B => \logicout_3[15]\, S => - \aluop_2[1]\, Y => N_3574); - - \r.d.pc[18]\ : DFN1 - port map(D => \pc_RNO[18]\, CLK => lclk_c, Q => \dpc[18]\); - - \r.e.alusel_RNO_0[1]\ : OR2 - port map(A => N_341, B => \alusel_i_0_0[1]\, Y => - \alusel_i_0_1[1]\); - - \r.e.op2_RNO_1[22]\ : OR2B - port map(A => \op1[22]\, B => un14_casaen_s1, Y => - \op1_m_i[22]\); - - \r.e.op1_RNI90CQB[12]\ : NOR3 - port map(A => \edata2_0_iv_0[12]\, B => \bpdata_i_m[12]\, C - => \bpdata_i_m_2[4]\, Y => edata2_0_iv(12)); - - un6_ex_add_res_d0_ADD_33x33_fast_I20_G0N : NOR3A - port map(A => \op1[19]\, B => ldbp1_0, C => \data_0[19]\, Y - => N454_0); - - \r.e.op1_RNI7RKB97[27]\ : NOR3C - port map(A => \op1_m_0[27]\, B => \d_iv_2[27]\, C => - \aluresult_m_0[27]\, Y => \d_i[27]\); - - \r.a.ctrl.pc_RNIC0F2C[27]\ : MX2 - port map(A => \pc_0[27]\, B => N_3904, S => ex_bpmiss_1, Y - => \fe_pc[27]\); - - \r.d.inst_0_RNO[0]\ : NOR2B - port map(A => rst, B => N_4600, Y => \inst_0_RNO[0]\); - - un6_fe_npc_I_203 : XOR2 - port map(A => N_9_0, B => \fe_pc[30]\, Y => I_203); - - \r.w.s.y_RNO[15]\ : MX2 - port map(A => \y_1[15]\, B => \result_0[15]\, S => N_481_0, - Y => N_3779); - - un6_ex_add_res_d1_ADD_33x33_fast_I192_Y : NOR2 - port map(A => N603_0, B => N595_2, Y => N661_0); - - \r.m.y_RNO_4[18]\ : OR3A - port map(A => \y_2[18]\, B => wy_3, C => wy_1_0_1, Y => - N_395); - - un6_fe_npc_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \fe_pc[7]\, Y => N_131); - - un6_ex_add_res_d1_ADD_33x33_fast_I267_un1_Y : OR3C - port map(A => N641_0, B => N657_0, C => N672_0, Y => - I267_un1_Y); - - \r.w.s.y_RNO[18]\ : NOR3 - port map(A => N_391, B => N_390, C => N_392, Y => N_158); - - \r.a.rsel2_0_RNIOKHE[0]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[355]\, Y => \cpi_m_i[355]\); - - \r.x.icc_RNIBSID[1]\ : MX2C - port map(A => \icc_0[1]\, B => \icc_3[1]\, S => wicc, Y => - N_4181); - - \r.m.y_RNIF26I3[11]\ : NOR3C - port map(A => \cpi_m[156]\, B => \y_m_1[11]\, C => - \tt_m[7]\, Y => \aluresult_1_iv_3[11]\); - - \r.f.pc_RNO_4[12]\ : MX2 - port map(A => I_56, B => N_4055, S => bpmiss_1_i_0_0, Y => - \pc_4[12]\); - - \r.e.op1_RNISAE6F[24]\ : NOR2B - port map(A => \edata2_iv_2[24]\, B => \edata2_iv_1[24]\, Y - => edata2_iv_i_0(24)); - - un6_ex_add_res_d0_ADD_33x33_fast_I113_Y_0 : AO18 - port map(A => N457, B => \data_0[21]\, C => \un1_iu0_6[21]\, - Y => ADD_33x33_fast_I113_Y_0); - - \r.d.inst_0_RNI2423[23]\ : NOR2B - port map(A => \inst_0_0[23]\, B => \inst_0_0[21]\, Y => - N_3834_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I17_G0N : NOR2B - port map(A => \un1_iu0_6[16]\, B => \op2[16]\, Y => N445_1); - - \r.x.data_0_RNO_0[4]\ : NOR3C - port map(A => \data_0_1_1_iv_0[4]\, B => \dco_m_i[124]\, C - => \dco_m_i[116]\, Y => \data_0_1_1_iv_2[4]\); - - \r.e.aluop_RNIFOHL[1]\ : NOR3B - port map(A => logicout19_0, B => \aluop_3[1]\, C => - un17_casaen_0, Y => edata_0_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_Y_2\ : AOI1B - port map(A => N588, B => N573, C => ADD_30x30_fast_I235_Y_1, - Y => ADD_30x30_fast_I235_Y_2); - - aluresult_11_sqmuxa_5_RNIQJG41_1 : OR2B - port map(A => aluresult_11_sqmuxa_0, B => - aluresult_12_sqmuxa_5, Y => aluresult_11_sqmuxa); - - un6_ex_add_res_d2_ADD_33x33_fast_I159_un1_Y : OR2B - port map(A => N570, B => N563_0, Y => I159_un1_Y_1); - - \r.w.s.tt_RNIGRP81[6]\ : OR2B - port map(A => \tt[6]\, B => aluresult_12_sqmuxa, Y => - \tt_m[6]\); - - aluresult_11_sqmuxa_5_RNI3B9M1 : OR2B - port map(A => aluresult_11_sqmuxa, B => - aluresult_8_sqmuxa_i, Y => \aluresult_6[31]\); - - \r.e.shcnt_RNIBDLBM[1]\ : MX2C - port map(A => \shiftin_14[12]\, B => \shiftin_14[10]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[10]\); - - \r.e.op2_RNO_8[15]\ : OR3B - port map(A => d29_0_0, B => \imm[15]\, C => \rsel2_1[0]\, Y - => \imm_m_i[15]\); - - \r.e.aluop_0_RNI155R[1]\ : XOR3 - port map(A => \un1_iu0_6[1]\, B => \aluop_0[1]\, C => - \op2_RNI1LHG[1]\, Y => N_6889); - - \r.d.inst_0_RNIL0GL[23]\ : OR2B - port map(A => icc_check8, B => icc_check7_i, Y => imm9); - - \r.m.casa_RNI99E608\ : OR2A - port map(A => \un17_casaen_0_0\, B => \un1_addout_12\, Y - => r_N_6); - - \r.e.ldbp2_2_RNI7V5E57\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[27]\, Y - => \aluresult_m_0[27]\); - - \comb.v.x.data_0_1_1_iv_RNO_1[31]\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_22, B => mcdo_m_0_29, C => - rdata_6_sqmuxa, Y => \dco_m_1[127]\); - - \r.m.casa\ : DFN1E0 - port map(D => mcasa, CLK => lclk_c, E => holdn, Q => casa); - - \r.m.dci.SIGNED_RNO_1\ : XOR2 - port map(A => \inst_1[20]\, B => \inst[19]\, Y => N_3742_i); - - \r.e.shcnt_RNITOC27[3]\ : MX2 - port map(A => \shiftin_8[34]\, B => \shiftin_8[26]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[26]\); - - \r.a.ctrl.pc[22]\ : DFN1E0 - port map(D => \dpc[22]\, CLK => lclk_c, E => holdn, Q => - \pc[22]\); - - \r.m.icc_RNO_14[2]\ : NOR3A - port map(A => icc_0_sqmuxa_1_3, B => \logicout[12]\, C => - \logicout[11]\, Y => icc_0_sqmuxa_1_18); - - \r.e.ctrl.inst_RNIHQGF1[26]\ : AO1D - port map(A => ex_bpmiss_1_0_1630_tz_0, B => - ex_bpmiss_1_0_a5_6_0, C => \inst_1[26]\, Y => - ex_bpmiss_1_0_1630_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I268_Y_0 : AO1 - port map(A => N658_1, B => N643_1, C => N642, Y => - ADD_33x33_fast_I268_Y_0_1); - - \r.x.ctrl.inst_RNI2JBD2[19]\ : NOR3C - port map(A => y_0_sqmuxa_1_2, B => wim_1_sqmuxa_1, C => - xc_wreg_0_sqmuxa, Y => wim_1_sqmuxa); - - \r.d.inst_0_RNIHM3M4[13]\ : OR2 - port map(A => un1_rs1, B => imm, Y => N_3946_1); - - \r.m.y_RNO_0[29]\ : NOR3C - port map(A => N_419, B => N_416, C => \y_iv_0_1[29]\, Y => - \y_iv_0_2[29]\); - - \r.a.ctrl.inst_RNICC1E_1[19]\ : OR2 - port map(A => \inst_2[20]\, B => \inst_2[19]\, Y => N_207); - - \r.w.s.tba_RNIEN558[13]\ : NOR2B - port map(A => \aluresult_1_iv_3[25]\, B => \bpdata_m_2[1]\, - Y => \aluresult_1_iv_5[25]\); - - \comb.misc_op.un1_r.x.ctrl.rd_0_0\ : XNOR2 - port map(A => \rd[0]\, B => \rd_0[0]\, Y => rd_0_i_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I162_Y\ : AO1 - port map(A => N536, B => N529, C => N528, Y => N588); - - \r.x.rstate_RNO_0[1]\ : MX2 - port map(A => \rstate_ns[1]\, B => \rstate[1]\, S => holdn, - Y => N_6323); - - \r.e.bp\ : DFN1E0 - port map(D => bp_1_1, CLK => lclk_c, E => holdn, Q => bp_0); - - \r.d.pv_RNI565951\ : OR3A - port map(A => un2_exbpmiss_0, B => ex_bpmiss_1_0, C => - \de_hold_pc_1\, Y => un2_exbpmiss); - - \r.f.pc_RNO_2[15]\ : OR2B - port map(A => I_77, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[13]\); - - \r.d.inst_0_RNIVIU9[27]\ : MX2C - port map(A => branch_4_i, B => branch_8_i, S => - \inst_0[27]\, Y => N_3350); - - \r.e.shcnt_RNIJN0OF[2]\ : MX2A - port map(A => \shiftin_11[37]\, B => \shiftin_11[33]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[33]\); - - \r.m.dci.enaddr\ : DFN1E0 - port map(D => \eenaddr\, CLK => lclk_c, E => holdn, Q => - enaddr); - - \r.e.jmpl_RNI0468A2\ : NOR3C - port map(A => \shiftin_17_m[18]\, B => - \aluresult_1_iv_6[17]\, C => \shiftin_17_m_0[17]\, Y => - \aluresult_1_iv_8[17]\); - - \r.w.result_RNIOB5J[11]\ : AOI1B - port map(A => \un1_p0_6[363]\, B => d14_0, C => - \result_m_0_0[11]\, Y => \d_iv_0[11]\); - - \r.x.result[25]\ : DFN1E0 - port map(D => \maddress[25]\, CLK => lclk_c, E => holdn, Q - => \result_0[25]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I129_Y_0 : MAJ3 - port map(A => \op2[13]\, B => \un1_iu0_6[13]\, C => N433_0, - Y => ADD_33x33_fast_I129_Y_0); - - \r.w.s.y_RNO[27]\ : NOR3 - port map(A => N_410, B => N_409, C => N_411, Y => N_172); - - \r.e.aluop_RNIAJG84[0]\ : MX2C - port map(A => N_3564, B => N_3628, S => \aluop_1[0]\, Y => - \logicout[5]\); - - \r.d.inst_0_0_0[21]\ : DFN1 - port map(D => \inst_0_0_0_RNIQ98I03[21]\, CLK => lclk_c, Q - => \un1_p0_6_0[60]\); - - \r.w.s.tba[0]\ : DFN1E1 - port map(D => \result[12]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[0]\); - - \r.e.aluop_0_RNI6ALC[2]\ : XA1 - port map(A => \un1_iu0_5[75]\, B => \aluop_0[2]\, C => - \un1_iu0_6[9]\, Y => N_3536); - - un6_ex_add_res_d1_ADD_33x33_fast_I244_Y : OR2 - port map(A => N658_0, B => ADD_33x33_fast_I244_un1_Y, Y => - N799_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I181_Y : AOI1 - port map(A => N592_0, B => N585_0, C => N584_0, Y => N650); - - \r.e.aluop_0_RNI1LMS3[0]\ : OR2B - port map(A => \logicout[6]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[6]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I188_Y : NOR2 - port map(A => N599_1, B => N591_0, Y => N657_0); - - \r.x.npc_1[1]\ : DFN1E0 - port map(D => \npc_1_0[1]\, CLK => lclk_c, E => holdn, Q - => \npc_1[1]\); - - \r.x.y[0]\ : DFN1E0 - port map(D => \y_0[0]\, CLK => lclk_c, E => holdn, Q => - \y_2[0]\); - - \r.e.aluop_RNIVC7U6[0]\ : OR2B - port map(A => \logicout[14]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[14]\); - - \r.e.aluop_0_RNIEAJ5[1]\ : NOR3A - port map(A => \aluop_0[2]\, B => \aluop_0[0]\, C => - \aluop_0[1]\, Y => aluresult_8_sqmuxa_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I234_Y\ : OR3C - port map(A => I194_un1_Y, B => ADD_30x30_fast_I234_Y_1, C - => I234_un1_Y, Y => N698); - - \r.x.mexc_RNO_0\ : MX2 - port map(A => mexc, B => mexc_0, S => mexc_1_sqmuxa_0, Y - => N_5246); - - \r.e.aluop_RNI1UH11[2]\ : NOR3 - port map(A => logicout22_1, B => \aluop_1[2]\, C => - un17_casaen_0, Y => edata_1_sqmuxa); - - \r.a.ctrl.pc[10]\ : DFN1E0 - port map(D => \dpc[10]\, CLK => lclk_c, E => holdn, Q => - \pc_3[10]\); - - \r.w.s.wim_RNIA74N2[2]\ : MX2 - port map(A => \wim[2]\, B => \result_0[2]\, S => - wim_1_sqmuxa, Y => \wim_1[2]\); - - \r.a.ctrl.inst_RNI8LEQ[27]\ : MX2C - port map(A => branch_4, B => branch_8, S => \inst_2[27]\, Y - => N_3343); - - \r.f.pc_RNIQF6641[11]\ : MX2B - port map(A => \fpc[11]\, B => \eaddress[11]\, S => jump, Y - => N_4054); - - un6_ex_add_res_d1_ADD_33x33_fast_I168_Y : NOR2B - port map(A => N579_2, B => N571_0, Y => N637); - - \r.x.result_RNI1PAN3[26]\ : MX2C - port map(A => \un1_iu0_6[26]\, B => \un1_p0_6[378]\, S => - bpdata6_0_0, Y => \bpdata[26]\); - - \r.f.pc_RNO_4[22]\ : MX2 - port map(A => I_129, B => N_4065, S => bpmiss_1_i_0, Y => - \pc_4[22]\); - - \r.w.s.pil_RNI8MFA1[1]\ : OR2A - port map(A => \pil[1]\, B => aluresult_11_sqmuxa, Y => - \pil_m[1]\); - - \r.e.invop2_1_RNIJC7882\ : MX2C - port map(A => \un6_ex_add_res_s2[24]\, B => - \un6_ex_add_res_s0[24]\, S => invop2_1, Y => N_6570); - - \r.m.y_RNO_3[17]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[17]\, C => \y_m[17]\, Y - => \y_iv_1[17]\); - - \r.e.op1[13]\ : DFN1E0 - port map(D => \aop1[13]\, CLK => lclk_c, E => holdn, Q => - \op1[13]\); - - \r.e.aluop_RNIPVQC6[0]\ : OR2B - port map(A => \logicout[29]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[29]\); - - \r.m.result_RNI0V3G3[2]\ : NOR3C - port map(A => \d_iv_0[2]\, B => \result_m_0[2]\, C => - \rfo_m[2]\, Y => \d_iv_2[2]\); - - \r.e.aluop_RNI6SJJ1[2]\ : XA1 - port map(A => \un1_iu0_5[85]\, B => \aluop_1[2]\, C => - \op1_RNID1VH[19]\, Y => N_3546); - - \r.e.shleft_RNI559D2\ : MX2B - port map(A => \shiftin_5[33]\, B => \shiftin_5[17]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[17]\); - - \r.e.op1[26]\ : DFN1E0 - port map(D => \aop1[26]\, CLK => lclk_c, E => holdn, Q => - \op1[26]\); - - \r.e.shleft_RNIS6QU1\ : MX2B - port map(A => \shiftin_5[40]\, B => \shiftin_5[24]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[24]\); - - \r.e.op1_RNO[6]\ : MX2C - port map(A => \d_i[6]\, B => \d_i[7]\, S => N_227_0, Y => - \aop1[6]\); - - \r.a.rsel1_RNIJI3A76[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[22]\, Y - => \aluresult_m_0[22]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I243_Y\ : OR3 - port map(A => I243_un1_Y, B => N588, C => I212_un1_Y, Y => - N716); - - \r.x.ctrl.pc_RNICKI61[18]\ : MX2C - port map(A => \un1_p0_6[370]\, B => \pc_2[18]\, S => - s_3_sqmuxa, Y => N_3409); - - \r.m.icc_RNO_18[2]\ : NOR3A - port map(A => \alusel[1]\, B => \alusel[0]\, C => N_198, Y - => icc_0_sqmuxa_1_0); - - \r.e.shcnt_RNIQAF6S[1]\ : MX2C - port map(A => \shiftin_14[26]\, B => \shiftin_14[24]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[24]\); - - \r.e.aluop_1_RNIL56R[1]\ : XOR3 - port map(A => \un1_iu0_6[5]\, B => \aluop_1[1]\, C => - \un1_iu0_5[71]\, Y => N_6835); - - \r.x.ctrl.pc_RNICBI21[30]\ : MX2C - port map(A => \un1_p0_6[382]\, B => \pc_2[30]\, S => N_6352, - Y => N_3421); - - \r.m.ctrl.inst[25]\ : DFN1E0 - port map(D => \inst_2[25]\, CLK => lclk_c, E => holdn, Q - => \inst_3[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I214_un1_Y\ : NOR2B - port map(A => N606, B => N591, Y => I214_un1_Y); - - \r.x.result[1]\ : DFN1E0 - port map(D => \maddress[1]\, CLK => lclk_c, E => holdn, Q - => \result_0[1]\); - - \r.x.ctrl.pc[28]\ : DFN1E0 - port map(D => \pc_3[28]\, CLK => lclk_c, E => holdn, Q => - \pc_0[28]\); - - \r.a.ctrl.inst_RNIBOET5[20]\ : NOR3C - port map(A => illegal_inst34_1, B => illegal_inst34_0, C - => inst_5, Y => illegal_inst34_3); - - \r.e.op2_RNO_3[26]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[26]\, Y => - \aluresult_m_i[26]\); - - \r.f.pc[12]\ : DFN1E0 - port map(D => \pc_1[12]\, CLK => lclk_c, E => holdn, Q => - \fpc[12]\); - - \r.d.pc_RNO[29]\ : MX2 - port map(A => \fpc[29]\, B => \dpc[29]\, S => N_6763_i, Y - => \pc_RNO[29]\); - - \r.e.aluop_1_RNIRGC31[1]\ : XOR3 - port map(A => \un1_iu0_6[20]\, B => \aluop_1[1]\, C => - \un1_iu0_5[86]\, Y => N_6847); - - un6_ex_add_res_d0_ADD_33x33_fast_I305_Y_0 : XNOR3 - port map(A => \data_0[14]\, B => \un1_iu0_6[14]\, C => - N799_1, Y => \un6_ex_add_res_s0[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I318_Y_0 : XNOR2 - port map(A => N772, B => \un6_ex_add_res_s2_1[28]\, Y => - \un6_ex_add_res_s0[28]\); - - \r.e.shleft_1_RNIJ56I1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[29]\, S => - shleft_1, Y => \shiftin_5[60]\); - - \r.w.s.tba_RNI8JFP5[6]\ : AOI1B - port map(A => \bpdata[18]\, B => aluresult_6_sqmuxa, C => - \tba_m[6]\, Y => \aluresult_1_iv_3[18]\); - - \r.f.pc[7]\ : DFN1E0 - port map(D => \pc_1[7]\, CLK => lclk_c, E => holdn, Q => - \fpc[7]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I250_Y_0_o3 : OR2 - port map(A => N418, B => N_62, Y => N817_0); - - \r.e.op2_RNISHAE1[1]\ : OR2B - port map(A => \op2_RNI1LHG[1]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[1]\); - - \r.a.ctrl.inst_RNI7C0E_0[31]\ : OR2A - port map(A => \inst[31]\, B => \inst[30]\, Y => N_201); - - \r.f.pc[2]\ : DFN1E0 - port map(D => \pc_1[2]\, CLK => lclk_c, E => holdn, Q => - \fpc[2]\); - - \r.e.op2_RNIENLB1[10]\ : OR2A - port map(A => \un1_iu0_5[76]\, B => \un1_iu0_6[10]\, Y => - \logicout_4[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I15_P0N : OR2 - port map(A => \un1_iu0_6[14]\, B => \op2[14]\, Y => N440); - - \r.x.y[29]\ : DFN1E0 - port map(D => \y[29]\, CLK => lclk_c, E => holdn, Q => - \y_2[29]\); - - \r.a.imm[11]\ : DFN1E0 - port map(D => \un3_de_ren1[129]\, CLK => lclk_c, E => holdn, - Q => \imm[11]\); - - \r.d.pv_RNI4IIHE\ : NOR3C - port map(A => un5_exbpmiss_i_0, B => - annul_next_2_sqmuxa_1_3, C => un9_rabpmiss, Y => - annul_next_2_sqmuxa_1_5); - - \comb.branch_address.tmp_ADD_30x30_fast_I11_P0N\ : OR2 - port map(A => \inst_0[11]\, B => \dpc[13]\, Y => N392); - - \r.e.op2_RNO_7[13]\ : OR3B - port map(A => d29_0_0, B => \imm[13]\, C => \rsel2_1[0]\, Y - => \imm_m_i[13]\); - - \r.e.shleft_1_RNI6D5I1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[14]\, S => - shleft_1, Y => \shiftin_5[45]\); - - \r.e.shleft_0_RNI64JB3\ : MX2 - port map(A => \shiftin_5[53]\, B => \shiftin_5[37]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[37]\); - - \r.m.y_RNO_4[29]\ : OR3A - port map(A => \y_2[29]\, B => wy_3, C => wy_1_0_1, Y => - N_417); - - \r.m.result_RNO[24]\ : MX2 - port map(A => \aluresult[24]\, B => \op1[24]\, S => - un17_casaen_0_1, Y => \eres2[24]\); - - \r.e.ctrl.pc[28]\ : DFN1E0 - port map(D => \pc[28]\, CLK => lclk_c, E => holdn, Q => - \pc_2[28]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I145_Y\ : NOR2B - port map(A => N519, B => N511, Y => N571_1); - - \r.m.y_RNO_2[24]\ : OR2B - port map(A => \y[24]\, B => y08, Y => N_371); - - \r.e.op2_RNO_5[12]\ : OR2B - port map(A => \result_0[12]\, B => d31, Y => - \result_m_i[12]\); - - \r.e.op1[5]\ : DFN1E0 - port map(D => \aop1[5]\, CLK => lclk_c, E => holdn, Q => - \op1[5]\); - - \r.w.s.tba_RNI6U424[19]\ : AOI1B - port map(A => \tba[19]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[31]\, Y => \aluresult_1_iv_3[31]\); - - \r.m.ctrl.ld_RNIF9L9\ : OR2A - port map(A => ld, B => d27, Y => ldbp2_0_a5_0); - - \r.e.op2_RNIRJ971_0[30]\ : OR2 - port map(A => \un1_iu0_6[30]\, B => \un1_iu0_5[96]\, Y => - \logicout_3[30]\); - - \r.e.ctrl.inst_RNI8T131[23]\ : NOR2A - port map(A => aluresult_11_sqmuxa_6, B => \inst_0[23]\, Y - => aluresult_11_sqmuxa_0); - - \r.e.ctrl.pc_RNI89K11[13]\ : OR2B - port map(A => \pc_2[13]\, B => jmpl_4, Y => \cpi_m[158]\); - - \r.f.pc_RNIO9TUV1[8]\ : AND2 - port map(A => \un6_ex_add_res_m_1[9]\, B => \pc_m[8]\, Y - => \npc_iv_1[8]\); - - \r.e.ldbp2_1_RNI90VAH\ : MX2 - port map(A => \un6_ex_add_res_s1[9]\, B => N_6555, S => - ldbp2_1, Y => \eaddress[8]\); - - \r.d.cwp_RNO[1]\ : MX2 - port map(A => N_4228, B => \cwp_1[1]\, S => N_6358, Y => - \cwp_1_0[1]\); - - \r.e.op1_RNI67OF[29]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[29]\, Y => - \op1_RNI67OF[29]\); - - \r.e.shleft_RNIHURJ\ : OR2A - port map(A => \un1_iu0_6[18]\, B => shleft, Y => - \shiftin_5[18]\); - - \r.e.op2_RNO_4[18]\ : OA1A - port map(A => \maddress[18]\, B => d27, C => \cpi_m_i[370]\, - Y => \d_1_iv_1[18]\); - - un37_ra_I_15 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP_0[0]\, B => \cwp[1]\, Y - => \DWACT_ADD_CI_0_g_array_1_0[0]\); - - \r.d.inst_0_RNO_0[2]\ : MX2 - port map(A => data_0_0_2, B => \inst_0[2]\, S => - mexc_1_sqmuxa_1_0, Y => N_4602); - - \r.m.dci.SIGNED_RNO\ : NOR3B - port map(A => SIGNED_2_1, B => N_3742_i, C => N_3356_3, Y - => SIGNED_2); - - \r.a.rsel2_0_RNIPEPD[0]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[353]\, Y => \cpi_m_i[353]\); - - \r.a.ctrl.inst_RNIG9IL7[21]\ : NOR3B - port map(A => inst_14, B => illegal_inst34_3, C => N_212, Y - => N_474); - - un6_ex_add_res_d2_ADD_33x33_fast_I107_Y : AO1 - port map(A => N508_0, B => N505_0, C => N504_0, Y => N570); - - \r.m.result_RNO[19]\ : MX2 - port map(A => \aluresult[19]\, B => \op1[19]\, S => - un17_casaen_0_1, Y => \eres2[19]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I289_Y_0_0\ : XOR2 - port map(A => \dpc[31]\, B => \inst_0_1[31]\, Y => - ADD_30x30_fast_I289_Y_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I190_un1_Y\ : OR2A - port map(A => N567_1, B => N582_0, Y => I190_un1_Y); - - \r.x.ctrl.pc_RNI0U971[31]\ : MX2C - port map(A => \un1_p0_6[383]\, B => \pc_2[31]\, S => - s_3_sqmuxa_0, Y => N_3422); - - \comb.op_mux.d_1_iv_RNO_1[29]\ : OR2B - port map(A => \op1[29]\, B => un14_casaen_s1, Y => - \op1_m_i[29]\); - - \r.e.mulstep_RNI8VGC_0\ : OR2A - port map(A => wy_0, B => mulstep, Y => y14_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I190_Y : NOR2B - port map(A => N601_0, B => N593, Y => N659); - - \r.e.op1_RNINM8G[21]\ : OR2B - port map(A => \op1[21]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[21]\); - - \r.m.y_RNIBO006[14]\ : NOR2B - port map(A => \aluresult_1_iv_1[14]\, B => - \aluresult_1_iv_2[14]\, Y => \aluresult_1_iv_3[14]\); - - \r.e.aluop_RNI9A7HM[0]\ : AOI1B - port map(A => \logicout[13]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_5[13]\, Y => \aluresult_1_iv_6[13]\); - - \r.f.pc_RNID32PM6[3]\ : OR3C - port map(A => \npc_iv_1[3]\, B => \npc_iv_0[3]\, C => - \npc_iv_2[3]\, Y => rpc_1); - - \r.e.op2_RNO[1]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[1]\, Y => N_285); - - \r.e.aluop_0_RNIRSOT_0[2]\ : NOR2 - port map(A => aluresult_7_sqmuxa_0, B => logicout21_1, Y - => aluresult_7_sqmuxa_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_Y : NAND2 - port map(A => I261_un1_Y_1, B => ADD_33x33_fast_I261_Y_2_1, - Y => N768); - - \r.e.aluop_0_RNI36M72[0]\ : MX2C - port map(A => N_3559, B => N_3623, S => \aluop_0[0]\, Y => - \logicout[0]\); - - \r.e.ctrl.pc_RNI3E8CA[19]\ : AND2 - port map(A => \aluresult_1_iv_3[19]\, B => - \aluresult_1_iv_2[19]\, Y => \aluresult_1_iv_4[19]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I301_Y_0_1 : XOR2 - port map(A => \data_0[10]\, B => \un1_iu0_6[10]\, Y => - \un6_ex_add_res_s2_1[11]\); - - \r.e.cwp_RNI0C0D9[0]\ : NOR3C - port map(A => \aluresult_2_iv_1[0]\, B => \cwp_m[0]\, C => - \aluresult_2_iv_2[0]\, Y => \aluresult_2_iv_4[0]\); - - \r.e.ctrl.inst_RNIB1LO[25]\ : AO1D - port map(A => \inst_1[27]\, B => \inst_2[25]\, C => - ex_bpmiss_1_0_a5_3_0, Y => ex_bpmiss_1_0_1630_tz_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I319_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[28]\, B => \data_0[28]\, Y => - \un6_ex_add_res_s2_1[29]\); - - \r.e.op2_RNO_1[19]\ : OR2B - port map(A => \op1[19]\, B => un14_casaen_s1, Y => - \op1_m_i[19]\); - - \r.d.inst_0_RNIRO4K1[13]\ : MX2C - port map(A => \inst_0[13]\, B => ldcheck2_2_sqmuxa_1_i, S - => annul_RNILQG71, Y => ldcheck2); - - \r.w.s.tba[4]\ : DFN1E1 - port map(D => \result_0[16]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[4]\); - - \r.m.ctrl.pc[10]\ : DFN1E0 - port map(D => \pc_0[10]\, CLK => lclk_c, E => holdn, Q => - \pc_2[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I263_Y_0\ : XOR2 - port map(A => N558, B => ADD_30x30_fast_I263_Y_0_0, Y => - \tmp[5]\); - - \r.a.ctrl.rd_RNIEPQG9[4]\ : NOR3C - port map(A => un1_de_ren1_4_i, B => un1_de_ren1_NE_3, C => - un1_de_ren1_5_i, Y => un1_de_ren1_NE_5); - - \r.m.y_RNO_0[26]\ : NOR3C - port map(A => \y_m[27]\, B => \y_m_0[26]\, C => - \y_iv_1[26]\, Y => \y_iv_2[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I73_Y : AO13 - port map(A => \un1_iu0_6[10]\, B => \data_0[10]\, C => - N424_1, Y => N532_1); - - \r.e.aluop_RNIG3IJ1[2]\ : XAI1A - port map(A => \un1_iu0_5[87]\, B => \aluop_1[2]\, C => - \un1_iu0_6[21]\, Y => N_3548); - - un6_ex_add_res_d1_ADD_33x33_fast_I84_Y : NOR2B - port map(A => N413_1, B => N410_1, Y => N543_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I26_P0N : OR2 - port map(A => \un1_iu0_6[25]\, B => \op2[25]\, Y => N473); - - un6_ex_add_res_d1_ADD_33x33_fast_I260_Y_3 : AOI1B - port map(A => N642_0, B => N627_1, C => - ADD_33x33_fast_I260_Y_2_0, Y => ADD_33x33_fast_I260_Y_3_1); - - \r.e.shcnt_RNIHOGO9[2]\ : MX2C - port map(A => \shiftin_11[13]\, B => \shiftin_11[9]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[9]\); - - \r.e.op1_RNIKT53I2[6]\ : NOR3C - port map(A => \op1_m_0[6]\, B => \d_iv_2[6]\, C => - \aluresult_m_0[6]\, Y => \d_i[6]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I267_Y_0_0\ : XOR2 - port map(A => \dpc[9]\, B => \inst_0[7]\, Y => - ADD_30x30_fast_I267_Y_0_0); - - \r.f.pc_RNO_0[12]\ : NOR3C - port map(A => \un6_ex_add_res_m_1[13]\, B => - \pc_1_iv_0[12]\, C => \tmp_m[12]\, Y => \pc_1_iv_2[12]\); - - \r.a.ctrl.cnt_RNI0BU9[0]\ : OA1C - port map(A => \cnt_2[1]\, B => casa, C => \cnt_1[0]\, Y => - \alusel_i_0_a2_1_0[1]\); - - \r.e.ctrl.inst_RNIFSP8[25]\ : OR2A - port map(A => \icc_0[2]\, B => \inst_2[25]\, Y => N_229); - - \r.a.rsel2_0_RNIKHIQ02[0]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[3]\, Y - => \aluresult_m_i[3]\); - - \r.e.shleft_1_RNI38921\ : MX2 - port map(A => \un1_iu0_6[31]\, B => \un1_iu0_6[0]\, S => - shleft_1, Y => \shiftin_5[31]\); - - \r.e.shcnt_RNI8DOVD[2]\ : MX2C - port map(A => \shiftin_11[31]\, B => \shiftin_11[27]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[27]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I44_Y : AND2 - port map(A => N470, B => N473, Y => N503); - - \r.e.op1[31]\ : DFN1E0 - port map(D => \aop1[31]\, CLK => lclk_c, E => holdn, Q => - \op1[31]\); - - \r.x.data_0[29]\ : DFN1E0 - port map(D => \data_0_1[29]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0_0[29]\); - - \r.m.ctrl.inst_RNIG51L[24]\ : NOR2 - port map(A => \inst_0[24]\, B => trap_0_sqmuxa_3_2, Y => - inst); - - \r.x.data_0_RNO[20]\ : OR3 - port map(A => \dco_m_0[116]\, B => \data_0_m[20]\, C => - \data_0_1_4[18]\, Y => \data_0_1[20]\); - - \r.f.pc_RNO_5[31]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[31]\, Y => \xc_trap_address_m[31]\); - - \r.a.rsel1_RNIPFH_0[0]\ : NOR3A - port map(A => \rsel1[0]\, B => \rsel1[2]\, C => \rsel1[1]\, - Y => N_494); - - un6_ex_add_res_d0_ADD_33x33_fast_I250_Y_0_o3 : OR2 - port map(A => N418_0, B => ADD_33x33_fast_I250_Y_0_a3_0, Y - => N817); - - \r.e.op2_RNIMVGN1[30]\ : OR2B - port map(A => \un1_iu0_5[96]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[30]\); - - \r.d.inst_0_RNO_0[26]\ : MX2 - port map(A => data_0_2_26, B => \inst_0[26]\, S => - inull_RNIFV6VG2_0, Y => N_4626); - - un6_ex_add_res_d2_ADD_33x33_fast_I10_G0N : OAI1 - port map(A => \op1[9]\, B => ldbp1, C => \data_0[9]\, Y => - N424_1); - - \r.w.s.tba[10]\ : DFN1E1 - port map(D => \result_0[22]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[10]\); - - \r.w.s.s_RNIAI3V3\ : AOI1 - port map(A => rstate_8_0, B => et_0_sqmuxa_i, C => s, Y => - s_i_m); - - \r.e.op2_RNO_4[9]\ : OR2B - port map(A => \op1[9]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[9]\); - - \r.e.op2_RNO_7[30]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[382]\, - Y => \cpi_m_i[382]\); - - \r.a.imm_RNO[24]\ : MX2 - port map(A => \inst_0[14]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[142]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I106_Y : OR2B - port map(A => N_74_1, B => N503, Y => N569); - - \r.w.s.et_RNIVNF2_0\ : NOR2A - port map(A => \rstate_0[0]\, B => et, Y => error_1_sqmuxa); - - \r.a.rsel2_0_RNIN1CM2[0]\ : OR2B - port map(A => data2(2), B => d25_0, Y => \rfo_m_i[34]\); - - \r.a.ctrl.inst_RNIEP7S[27]\ : MX2C - port map(A => branch_3, B => branch_7, S => \inst_2[27]\, Y - => N_3340); - - \r.f.pc_RNO[8]\ : OR3C - port map(A => \tmp_m[8]\, B => \pc_1_iv_1[8]\, C => - \un6_fe_npc_m[6]\, Y => \pc_1[8]\); - - \r.e.aluop_RNI44R04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[4]\, Y => - \bpdata_i_m_2[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I310_Y_0 : AX1C - port map(A => I271_un1_Y, B => ADD_33x33_fast_I271_Y_0_1, C - => \un6_ex_add_res_s2_1[20]\, Y => - \un6_ex_add_res_s0[20]\); - - \r.e.ctrl.pc[9]\ : DFN1E0 - port map(D => \pc_0[9]\, CLK => lclk_c, E => holdn, Q => - \pc[9]\); - - \r.e.op1_RNIMM3RB[16]\ : NOR3 - port map(A => \edata2_0_iv_0[16]\, B => \ex_op1_i_m[16]\, C - => \bpdata_i_m_1[0]\, Y => edata2_0_iv(16)); - - \r.x.data_0_RNO_3[1]\ : OR2B - port map(A => N_3455, B => data_0_2_17, Y => \dco_m_i[113]\); - - \r.x.y[6]\ : DFN1E0 - port map(D => \y_0[6]\, CLK => lclk_c, E => holdn, Q => - \y_2[6]\); - - \r.e.op1_RNI3E3U1[0]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[0]\, C => - \ex_op1_i_m[0]\, Y => \edata2_0_iv_0[0]\); - - \r.x.nerror\ : DFN1E0 - port map(D => nerror_1, CLK => lclk_c, E => holdn, Q => - error_i_2); - - \r.e.op2_RNO_8[6]\ : OR3B - port map(A => d29_0_0, B => \imm[6]\, C => \rsel2_0[0]\, Y - => \imm_m_i[6]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I268_un1_Y_0 : OR2 - port map(A => N659_0, B => N643, Y => - ADD_33x33_fast_I268_un1_Y_0); - - \r.e.op2_RNIHS9P[3]\ : OR2A - port map(A => \un1_iu0_5[69]\, B => \un1_iu0_6[3]\, Y => - \logicout_4[3]\); - - \r.e.aluop_1_RNICGR61_0[1]\ : NOR3B - port map(A => miscout69, B => logicout20, C => - aluresult_9_sqmuxa_1, Y => aluresult_10_sqmuxa); - - \r.e.shcnt_RNIK99MI[1]\ : MX2C - port map(A => \shiftin_14[3]\, B => \shiftin_14[1]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[1]\); - - \r.e.op2_RNO_1[16]\ : OR2B - port map(A => \op1[16]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[16]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I10_P0N : OR2 - port map(A => \un1_iu0_6[9]\, B => \op2[9]\, Y => N425_1); - - \r.m.result[18]\ : DFN1E0 - port map(D => \eres2[18]\, CLK => lclk_c, E => holdn, Q => - \maddress[18]\); - - \r.e.op1_RNI69UH[31]\ : MX2 - port map(A => \op1[31]\, B => \data_0_0[31]\, S => ldbp1_3, - Y => \un1_iu0_6[31]\); - - \r.x.ctrl.inst[29]\ : DFN1E0 - port map(D => \inst_3[29]\, CLK => lclk_c, E => holdn, Q - => \inst_1[29]\); - - \r.x.npc_0_RNI9NE41[0]\ : MX2C - port map(A => N_3217, B => N_3247, S => \npc_0[0]\, Y => - \xc_result[6]\); - - \r.f.pc_RNISTGB4[16]\ : MX2 - port map(A => \dpc[16]\, B => \fpc[16]\, S => ra_bpmiss_1, - Y => N_3893); - - un6_ex_add_res_d0_ADD_33x33_fast_I296_Y_0 : XNOR3 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N676_0, - Y => \un6_ex_add_res_s0[6]\); - - \r.x.data_0_RNO_4[3]\ : OR2B - port map(A => rdata_2_sqmuxa, B => data_0_0_11, Y => - \dco_m_i[107]\); - - \r.e.op2_RNO_5[25]\ : AOI1B - port map(A => \result[25]\, B => d31_0, C => \imm_m_i[25]\, - Y => \d_1_iv_0[25]\); - - \r.e.aluop_RNI9KQF4[1]\ : OR2B - port map(A => \bpdata[21]\, B => aluresult_6_sqmuxa, Y => - \bpdata_m[21]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I141_Y\ : NOR2B - port map(A => N515, B => N507, Y => N567_1); - - \r.x.ctrl.pc_RNI22A71[24]\ : MX2C - port map(A => \un1_p0_6[376]\, B => \pc_0[24]\, S => - s_3_sqmuxa_0, Y => N_3415); - - \r.a.ctrl.rd_RNIB29A2[4]\ : XNOR2 - port map(A => \un3_de_ren1[103]\, B => \rd_1[4]\, Y => - un1_de_ren1_4_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I25_G0N : NOR2B - port map(A => \un1_iu0_6[24]\, B => \data_0[24]\, Y => - N469_0); - - \r.m.result_RNICJD4[24]\ : OR2B - port map(A => d13_0, B => \maddress[24]\, Y => - \result_m_0_0[24]\); - - \r.x.y[24]\ : DFN1E0 - port map(D => \y[24]\, CLK => lclk_c, E => holdn, Q => - \y_2[24]\); - - \r.d.pc[6]\ : DFN1 - port map(D => \pc_RNO[6]\, CLK => lclk_c, Q => \dpc[6]\); - - \r.m.y_RNO_3[1]\ : OR3A - port map(A => \y_2[1]\, B => wy_3, C => wy_1_0_1, Y => - N_378); - - \r.e.ctrl.cnt[0]\ : DFN1E0 - port map(D => \cnt_1[0]\, CLK => lclk_c, E => holdn, Q => - \cnt[0]\); - - \r.e.aluop_1_RNIARCM1[1]\ : MX2C - port map(A => N_3533, B => \logicout_3[6]\, S => - \aluop_1[1]\, Y => N_3565); - - \r.a.ctrl.pc_RNITBE2C[22]\ : MX2 - port map(A => \pc[22]\, B => N_3899, S => ex_bpmiss_1, Y - => \fe_pc[22]\); - - \r.e.ldbp2_0\ : DFN1E0 - port map(D => ldbp2, CLK => lclk_c, E => holdn, Q => - ldbp2_0); - - \r.d.pc_RNISDHB4[30]\ : MX2 - port map(A => \dpc[30]\, B => \fpc[30]\, S => - \ra_bpmiss_1_0\, Y => N_3907); - - \r.x.npc_0_RNIMQ1A1[1]\ : MX2 - port map(A => \npc_0[1]\, B => \npc_cnst_m_0[1]\, S => - s_3_sqmuxa_0, Y => \npc_1_0[1]\); - - \r.f.pc_RNO_3[20]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[20]\, C => - \xc_trap_address_m[20]\, Y => \pc_1_iv_0[20]\); - - \r.e.op2_RNO_6[8]\ : OR2B - port map(A => data2(8), B => d25_0, Y => \rfo_m_i[40]\); - - \r.w.s.tba[15]\ : DFN1E1 - port map(D => \result_0[27]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I40_Y_i_o3 : OAI1 - port map(A => \op2[26]\, B => \un1_iu0_6[26]\, C => N479_2, - Y => N_50); - - \r.w.result[8]\ : DFN1E0 - port map(D => \wdata[8]\, CLK => lclk_c, E => holdn, Q => - \result_0[8]\); - - \r.e.op1_RNIK64RB[21]\ : NOR2 - port map(A => \edata2_0_iv_1[21]\, B => \bpdata_i_m_1[5]\, - Y => edata2_0_iv(21)); - - \r.a.rsel1_0_RNID3LJ2[2]\ : OR2B - port map(A => data1(16), B => d11, Y => \rfo_m[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I216_Y_0_a3\ : NOR2B - port map(A => N723, B => N404_0, Y => - ADD_30x30_fast_I216_Y_0_a3); - - \r.x.y[26]\ : DFN1E0 - port map(D => \y_1[26]\, CLK => lclk_c, E => holdn, Q => - \y_2[26]\); - - \r.m.y_RNO_4[26]\ : OR3A - port map(A => \y_2[26]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[26]\); - - \r.a.rsel1_0_RNIUG8M2[2]\ : OR2B - port map(A => data1(6), B => d11, Y => \rfo_m[6]\); - - \r.w.result_RNIPOV6[4]\ : OR2B - port map(A => \result_0[4]\, B => d31, Y => \result_m_i[4]\); - - \r.e.ldbp2_RNIC795BE\ : NOR3C - port map(A => N_9, B => m14_0, C => N_31, Y => m14_2); - - \r.e.op1_RNI416I1[5]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[5]\, Y => - \ex_op1_i_m[5]\); - - \r.x.npc_0_RNI1TR61[0]\ : MX2C - port map(A => N_3233, B => N_3263, S => \npc_0[0]\, Y => - \xc_result[22]\); - - \r.e.op2_RNIRJ971[30]\ : OR2A - port map(A => \un1_iu0_5[96]\, B => \un1_iu0_6[30]\, Y => - \logicout_4[30]\); - - \r.e.op1_RNO[26]\ : MX2C - port map(A => \d_i[26]\, B => \d_i[27]\, S => N_227, Y => - \aop1[26]\); - - \r.e.aluop_RNI1VJD4[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[31]\, Y => - \bpdata_i_m[31]\); - - \r.d.inst_0_RNI1JUM[1]\ : NOR2B - port map(A => \inst_0[1]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI1JUM[1]\); - - \r.a.ctrl.inst_RNIS96K2[22]\ : OA1B - port map(A => N_202, B => illegal_inst37_4, C => - illegal_inst38, Y => un1_illegal_inst33_0); - - \r.m.ctrl.trap_RNIMI3D31\ : OR3C - port map(A => trap_2_0, B => un1_trap_0_sqmuxa_5, C => - un6_annul, Y => trap2); - - \r.m.ctrl.pc_RNIU1HF[23]\ : MX2 - port map(A => \pc_2[23]\, B => \pc_3[23]\, S => \npc_1[1]\, - Y => N_3264); - - \r.m.ctrl.pc_RNIV6AE[6]\ : MX2 - port map(A => \pc_2[6]\, B => \pc_0[6]\, S => \npc_0[1]\, Y - => N_3247); - - \r.f.pc_RNIMEJIR1[4]\ : MX2 - port map(A => I_9, B => N_4047, S => bpmiss_1_i_0, Y => - \pc_4[4]\); - - \r.x.result_RNIPV335[2]\ : NOR2 - port map(A => \bpdata[2]\, B => N_3703_i, Y => - \bpdata_i_m_1[2]\); - - un6_fe_npc_I_206 : AND2 - port map(A => \fe_pc[29]\, B => \fe_pc[30]\, Y => - \DWACT_FINC_E[25]\); - - \r.m.dci.SIGNED\ : DFN1E0 - port map(D => SIGNED_2, CLK => lclk_c, E => holdn, Q => - SIGNED); - - un6_ex_add_res_d0_ADD_33x33_fast_I89_Y : AO13 - port map(A => N400_2, B => \un1_iu0_6[2]\, C => \data_0[2]\, - Y => N548_1); - - \r.d.inst_0_RNO[23]\ : NOR2B - port map(A => rst, B => N_4623, Y => \inst_0_RNO[23]\); - - \r.e.op2_RNO_6[19]\ : OR2B - port map(A => data2(19), B => d25, Y => \rfo_m_i[51]\); - - \r.x.ctrl.inst[21]\ : DFN1E0 - port map(D => \inst[21]\, CLK => lclk_c, E => holdn, Q => - \inst_0[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I103_Y : NOR2A - port map(A => I103_un1_Y_i, B => N500, Y => N566_i); - - \r.x.ctrl.ld\ : DFN1E0 - port map(D => ld, CLK => lclk_c, E => holdn, Q => ld_4); - - un6_ex_add_res_d1_ADD_33x33_fast_I99_un1_Y : OR2A - port map(A => N500_1, B => N497_2, Y => I99_un1_Y); - - \r.x.dci.SIGNED_RNIQD0LV4\ : AO1A - port map(A => rdata_0_sqmuxa, B => \rdata_5[8]\, C => - \rdata_9_m[8]\, Y => \data_0_1_1[12]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I143_Y : AO1 - port map(A => N544_1, B => N541_1, C => N540_0, Y => N606_1); - - \r.a.ctrl.inst_RNINQ7L2[5]\ : AO1B - port map(A => un29_casaen_5, B => un29_casaen_4, C => - illegal_inst35, Y => privileged_inst_0_sqmuxa); - - \r.e.aluop_1_RNI47603[1]\ : MX2C - port map(A => \logicout_4[11]\, B => N_6910, S => N_6866_i, - Y => N_3634); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_un1_Y : NAND2 - port map(A => N799, B => ADD_33x33_fast_I260_un1_Y_0, Y => - I260_un1_Y_i_0); - - \r.a.rsel1_RNI4V53[0]\ : NOR3B - port map(A => \rsel1[0]\, B => \rsel1[1]\, C => - \rsel1_0[2]\, Y => d14_0); - - \r.w.s.y_RNO[26]\ : MX2 - port map(A => \y_2[26]\, B => \result[26]\, S => N_481, Y - => N_3790); - - \r.d.cnt_RNIATF3[1]\ : NOR2B - port map(A => \cnt_0[1]\, B => \inst_0[30]\, Y => N_3737_1); - - \comb.v.x.data_0_1_1_iv_RNO_1[16]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_2_16, Y => - \dco_m_0[112]\); - - un6_fe_npc_I_210 : XOR2 - port map(A => N_4_0, B => \fe_pc[31]\, Y => I_210); - - un6_ex_add_res_d0_ADD_33x33_fast_I24_G0N : OR2A - port map(A => \un1_iu0_6[23]\, B => \data_0[23]\, Y => - N466_1); - - \r.d.pc_RNIITGB4[11]\ : MX2 - port map(A => \dpc[11]\, B => \fpc[11]\, S => ra_bpmiss_1, - Y => N_3888); - - un6_ex_add_res_d2_ADD_33x33_fast_I250_Y_0_a3 : NOR2B - port map(A => N672, B => N419_0, Y => N_62); - - un6_ex_add_res_d1_ADD_33x33_fast_I12_P0N : OR2 - port map(A => \un1_iu0_6[11]\, B => \op2[11]\, Y => N431_1); - - \r.d.inst_0_RNI3DOH[16]\ : MX2 - port map(A => \inst_0[16]\, B => \inst_0[27]\, S => rs1mod, - Y => \un3_de_ren1[93]\); - - \r.a.ctrl.pc_RNI9SE2C[26]\ : MX2 - port map(A => \pc_0[26]\, B => N_3903, S => ex_bpmiss_1_0, - Y => \fe_pc[26]\); - - \r.x.rstate_RNICOF62[0]\ : MX2C - port map(A => N_3395, B => \xc_result[4]\, S => \rstate[0]\, - Y => \wdata[4]\); - - \r.m.y_RNO_3[11]\ : OR3A - port map(A => \y_2[11]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[11]\); - - \r.x.data_0_RNO[29]\ : OR3 - port map(A => \dco_m_1[125]\, B => \data_0_m[29]\, C => - \data_0_1_4[18]\, Y => \data_0_1[29]\); - - \r.e.op1_RNI3VNF[17]\ : NOR2A - port map(A => \un17_casaen_0_0\, B => \op1[17]\, Y => - \op1_i_m[17]\); - - \r.w.s.y_RNO[4]\ : MX2 - port map(A => \y_1[4]\, B => \result[4]\, S => N_481_0, Y - => N_3768); - - \r.f.pc_RNO_6[20]\ : MX2 - port map(A => \fpc[20]\, B => \eaddress[20]\, S => jump_0, - Y => N_4063); - - \r.a.et_RNILF8A\ : NOR2A - port map(A => et_1, B => \inst_2[21]\, Y => - illegal_inst_7_iv_2_0_a5_5_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I23_P0N : AO1A - port map(A => ldbp1_3, B => \op1[22]\, C => \data_0_0[22]\, - Y => N464); - - un6_ex_add_res_d0_ADD_33x33_fast_I85_Y : AO13 - port map(A => N406, B => \un1_iu0_6[4]\, C => \data_0[4]\, - Y => N544_0); - - \r.e.op1_RNO[9]\ : MX2C - port map(A => \d_i[9]\, B => \d_i[10]\, S => N_227, Y => - \aop1[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I7_G0N : NOR3A - port map(A => \op1[6]\, B => ldbp1_0, C => \data_0[6]\, Y - => N415_0); - - \r.e.alucin\ : DFN1E0 - port map(D => N_6684_i_0, CLK => lclk_c, E => holdn, Q => - alucin); - - un6_ex_add_res_d1_ADD_33x33_fast_I173_Y : AO1B - port map(A => N584_0, B => N577_0, C => N576, Y => N642_0); - - \r.a.ctrl.pc[24]\ : DFN1E0 - port map(D => \dpc[24]\, CLK => lclk_c, E => holdn, Q => - \pc_3[24]\); - - \r.x.y[22]\ : DFN1E0 - port map(D => \y[22]\, CLK => lclk_c, E => holdn, Q => - \y_2[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I205_Y : OR2B - port map(A => N610_0, B => I205_un1_Y, Y => N676); - - \r.w.s.icc_RNO[1]\ : AO1B - port map(A => icc_1_sqmuxa, B => \icc_0[1]\, C => - \icc_1_iv_0[1]\, Y => \icc_1[1]\); - - \r.d.inst_0_RNIVB391[25]\ : MX2C - port map(A => N_3348, B => N_3351, S => \inst_0[25]\, Y => - branch_1); - - \r.f.pc_RNO[13]\ : OR3C - port map(A => \tmp_m[13]\, B => \pc_1_iv_1[13]\, C => - \un6_fe_npc_m[11]\, Y => \pc_1[13]\); - - \r.e.shcnt_RNI6SQUK[1]\ : MX2C - port map(A => \shiftin_14[9]\, B => \shiftin_14[7]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[7]\); - - \r.e.op1_RNIU2NF[30]\ : OR2A - port map(A => un17_casaen_0, B => \op1[30]\, Y => - \op1_RNIU2NF[30]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I95_Y\ : NOR2B - port map(A => N460_0, B => N456, Y => N515); - - \r.e.cwp[2]\ : DFN1E0 - port map(D => \cwp_3[2]\, CLK => lclk_c, E => holdn, Q => - \cwp_2[2]\); - - \r.m.ctrl.rd_RNIMI7Q[1]\ : XNOR2 - port map(A => \inst_0_RNI1JUM[1]\, B => \rd_0[1]\, Y => - un1_de_ren1_1_1_i_0); - - \r.a.rsel1_RNI5LB[0]\ : OR2 - port map(A => \rsel1[0]\, B => \rsel1[1]\, Y => d11_0_a5_0); - - \r.e.op2_RNIVEOP[15]\ : MX2 - port map(A => \op2[15]\, B => N_4262, S => ldbp2_1, Y => - \un1_iu0_5[81]\); - - \r.e.aluop_RNIB31O6[0]\ : MX2C - port map(A => N_3590, B => N_3654, S => \aluop_1[0]\, Y => - \logicout[31]\); - - \r.e.aluop_0_RNIUOID1[1]\ : XOR3 - port map(A => \un1_iu0_6[15]\, B => \aluop_0[1]\, C => - \un1_iu0_5[81]\, Y => N_6883); - - \r.f.pc_RNIU2F8F[5]\ : MX2 - port map(A => \fpc[5]\, B => \eaddress[5]\, S => jump, Y - => N_4048); - - \r.e.aluop_RNI0IA98[2]\ : OA1C - port map(A => edata_1_sqmuxa, B => \bpdata[9]\, C => - \bpdata_i_m_2[1]\, Y => \edata2_iv_2[25]\); - - \r.e.ldbp2_RNIHA2632\ : OR3C - port map(A => \aluresult_1_iv_7[4]\, B => - \shiftin_17_m_0[4]\, C => \un6_ex_add_res_m[5]\, Y => - \aluresult[4]\); - - \r.d.cwp_RNO_0[0]\ : MX2 - port map(A => \ncwp[0]\, B => N_4218, S => un1_wcwp, Y => - N_4227); - - \r.e.invop2_0_RNI74UFN2\ : MX2C - port map(A => \un6_ex_add_res_s2[27]\, B => - \un6_ex_add_res_s0[27]\, S => invop2_0, Y => N_6658); - - \r.f.pc_RNO_0[25]\ : NAND2 - port map(A => \tmp[25]\, B => un2_rstn_5_0, Y => - \tmp_m[25]\); - - \r.a.ctrl.inst_RNI9S0E[23]\ : OR2 - port map(A => \inst_1[23]\, B => \inst[22]\, Y => N_202); - - \comb.branch_address.tmp_ADD_30x30_fast_I48_Y_0_o3\ : AO1 - port map(A => N416_2, B => N412, C => N415, Y => N465); - - \r.e.jmpl_RNITN6O_2\ : NOR3 - port map(A => jmpl, B => aluresult_1_sqmuxa_0_0, C => - \ex_shcnt_1[0]\, Y => aluresult_1_sqmuxa_0); - - \r.a.ctrl.pc[4]\ : DFN1E0 - port map(D => \dpc[4]\, CLK => lclk_c, E => holdn, Q => - \pc_0[4]\); - - \r.f.pc_RNIMOOJK1[3]\ : OA1C - port map(A => \fpc[3]\, B => rst, C => - \un6_ex_add_res_m_1[4]\, Y => \npc_iv_1[3]\); - - \r.a.ctrl.pc_RNIP7E2C[13]\ : MX2 - port map(A => \pc[13]\, B => N_3890, S => ex_bpmiss_1, Y - => \fe_pc[13]\); - - \r.e.op1_RNIO2CR1[22]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[22]\, Y => - \ex_op1_i_m[22]\); - - un37_ra_I_1 : AND2 - port map(A => \cwp_0[0]\, B => \inst_0_RNI4VUM[4]\, Y => - \DWACT_ADD_CI_0_TMP_0[0]\); - - \r.e.op2_RNO_6[16]\ : OR2B - port map(A => data2(16), B => d25, Y => \rfo_m_i[48]\); - - \r.e.aluop_0_RNI63A66[0]\ : OR2B - port map(A => \logicout[17]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[17]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I105_Y : OR2 - port map(A => I105_un1_Y, B => N502, Y => N568); - - \r.e.shcnt_RNITM6M[1]\ : MX2C - port map(A => \shcnt[1]\, B => N_3305, S => ldbp2_0, Y => - \ex_shcnt_1_i_0[1]\); - - \r.e.op2_RNO_6[5]\ : OR2B - port map(A => data2(5), B => d25_0, Y => \rfo_m_i[37]\); - - \r.w.s.y[9]\ : DFN1E0 - port map(D => N_3773, CLK => lclk_c, E => N_6922_i, Q => - \y[9]\); - - \r.e.op2_RNI8ROP[27]\ : MX2 - port map(A => \op2[27]\, B => N_4274, S => ldbp2_2, Y => - \un1_iu0_5[93]\); - - \r.e.invop2_0_RNI9V5MH\ : MX2C - port map(A => \un6_ex_add_res_s2[11]\, B => - \un6_ex_add_res_s0[11]\, S => invop2_0, Y => N_6630); - - \r.w.s.wim_RNIKR4N2[7]\ : MX2 - port map(A => \wim[7]\, B => \result_0[7]\, S => - wim_1_sqmuxa, Y => \wim_1[7]\); - - \r.f.pc_RNO[10]\ : OR3C - port map(A => \tmp_m[10]\, B => \pc_1_iv_1[10]\, C => - \un6_fe_npc_m[8]\, Y => \pc_1[10]\); - - \r.m.y_RNO_4[17]\ : OR3A - port map(A => \y_2[17]\, B => wy_3, C => wy_1_0_0, Y => - \y_m[17]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I139_Y : AO1 - port map(A => N540, B => N537_0, C => N536_0, Y => N602); - - \comb.branch_address.tmp_ADD_30x30_fast_I234_Y_1\ : AOI1B - port map(A => N518, B => N511, C => ADD_30x30_fast_I234_Y_0, - Y => ADD_30x30_fast_I234_Y_1); - - wovf_exc_0_sqmuxa_RNO_0 : MX2C - port map(A => N_3722, B => N_3723, S => \ncwp_3[1]\, Y => - N_3724); - - \r.e.su_RNIR2OL5\ : OA1A - port map(A => esu, B => aluresult_11_sqmuxa, C => - \aluresult_1_iv_1[7]\, Y => \aluresult_1_iv_3[7]\); - - \r.a.imm_RNO[19]\ : MX2 - port map(A => \inst_0[9]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[137]\); - - \r.e.ctrl.inst[26]\ : DFN1E0 - port map(D => \inst_2[26]\, CLK => lclk_c, E => holdn, Q - => \inst_1[26]\); - - \r.x.ctrl.tt_RNID10R[4]\ : MX2C - port map(A => \result[4]\, B => \tt_0[4]\, S => tt_i, Y => - N_3323); - - \r.x.ctrl.rd[7]\ : DFN1E0 - port map(D => \rd_0[7]\, CLK => lclk_c, E => holdn, Q => - \rd_2[7]\); - - \r.m.y_RNO[18]\ : AO1C - port map(A => y14_0, B => \logicout[18]\, C => - \y_iv_0_2[18]\, Y => \y_0[18]\); - - \r.e.shcnt_RNI178JO[1]\ : MX2C - port map(A => \shiftin_14[17]\, B => \shiftin_14[15]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[15]\); - - \r.x.result_RNIOO5H2[7]\ : NOR2 - port map(A => cwp_1_sqmuxa_0, B => \result_0[7]\, Y => - \result_i_m[7]\); - - \r.e.op1_RNO[10]\ : MX2C - port map(A => \d_i[10]\, B => \d_i[11]\, S => N_227, Y => - \aop1[10]\); - - \r.e.invop2_RNIDSAME2\ : MX2C - port map(A => \un6_ex_add_res_s2[25]\, B => - \un6_ex_add_res_s0[25]\, S => invop2, Y => N_6571); - - un6_ex_add_res_d2_ADD_33x33_fast_I203_un1_Y : NOR3C - port map(A => N541, B => N545_0, C => N614_2, Y => - I203_un1_Y_0); - - \r.x.annul_all_RNILS0QF\ : MX2 - port map(A => ps_1, B => s_1_iv, S => su2, Y => \su_0\); - - \r.e.op2_RNI4JOP[25]\ : MX2 - port map(A => \op2[25]\, B => N_4272, S => ldbp2_2, Y => - \un1_iu0_5[91]\); - - \r.e.op1_RNO[4]\ : MX2B - port map(A => \d[4]\, B => \d_i_0[5]\, S => N_227, Y => - N_167); - - un6_ex_add_res_d2_ADD_33x33_fast_I272_un1_Y : OR3C - port map(A => N667_1, B => N616_1, C => N651, Y => - I272_un1_Y_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I245_Y : OR2 - port map(A => N660, B => I245_un1_Y_0, Y => N802); - - \r.e.aluop_2_RNI6K413[1]\ : MX2C - port map(A => N_3540, B => \logicout_3[13]\, S => - \aluop_2[1]\, Y => N_3572); - - \r.e.shleft_1_RNIILIM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \op1_RNID1VH[19]\, S - => shleft_1, Y => \shiftin_5[50]\); - - \r.e.op1_RNITUPM7[3]\ : OR2B - port map(A => \edata2_0_iv_0[3]\, B => \bpdata_i_m[3]\, Y - => edata2_0_iv(3)); - - \r.m.y[28]\ : DFN1E0 - port map(D => \y_1[28]\, CLK => lclk_c, E => holdn, Q => - \y[28]\); - - \r.m.result_RNIKDAI[29]\ : NOR3C - port map(A => \result_m_0[29]\, B => \cpi_m_0[381]\, C => - \result_m_0_0[29]\, Y => \d_iv_1[29]\); - - \r.e.invop2\ : DFN1E0 - port map(D => N_6680, CLK => lclk_c, E => holdn, Q => - invop2); - - \r.m.y_RNISHO71[15]\ : OR2B - port map(A => \y[15]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I60_Y : NOR2B - port map(A => N449_1, B => N446_0, Y => N519_1); - - \r.e.op2_RNO_5[7]\ : AOI1B - port map(A => \result[7]\, B => d31_0, C => \imm_m_i[7]\, Y - => \d_1_iv_0[7]\); - - \r.e.op1_RNIBE3RB[20]\ : NOR2 - port map(A => \edata2_0_iv_1[20]\, B => \bpdata_i_m_1[4]\, - Y => edata2_0_iv(20)); - - \r.x.ctrl.pc_RNIH1M9[11]\ : MX2 - port map(A => \pc_0[11]\, B => \pc_2[11]\, S => \npc[1]\, Y - => N_3222); - - \r.x.data_0_RNO_3[0]\ : OR2B - port map(A => N_3455, B => data_0_2_16, Y => \dco_m_i[112]\); - - \r.w.s.y[27]\ : DFN1E0 - port map(D => N_172, CLK => lclk_c, E => holdn, Q => - \y[27]\); - - \r.e.aluop_0_RNI5B2T2[1]\ : MX2C - port map(A => \logicout_4[17]\, B => N_6877, S => - N_6866_i_0, Y => N_3640); - - \r.x.result_RNIVB435[3]\ : NOR2 - port map(A => \bpdata[3]\, B => N_3703_i, Y => - \bpdata_i_m_1[3]\); - - \r.x.ctrl.inst_RNITM3O1[30]\ : NOR2B - port map(A => y15, B => y6, Y => cwp_1_sqmuxa); - - \r.e.ctrl.pc_RNISR011[8]\ : OR2B - port map(A => \pc_2[8]\, B => jmpl_4, Y => \cpi_m[153]\); - - \r.d.inst_0_RNO[6]\ : NOR2B - port map(A => rst, B => N_4606, Y => \inst_0_RNO[6]\); - - \r.x.result_RNI0NED[17]\ : MX2 - port map(A => \result_0[17]\, B => \data_0[17]\, S => ld_0, - Y => \un1_p0_6[369]\); - - \r.w.result_RNIBTIF[9]\ : NOR2B - port map(A => \cpi_m_0[361]\, B => \result_m_0[9]\, Y => - \d_iv_0[9]\); - - \r.a.rsel1_0_RNIC7LJ2[2]\ : OR2B - port map(A => data1(22), B => d11_0, Y => \rfo_m[22]\); - - \r.f.pc_RNO_3[26]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[26]\, C => - \xc_trap_address_m[26]\, Y => \pc_1_iv_0[26]\); - - \r.e.aluop_RNIQ4RF4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[25]\, Y => - \aluop_RNIQ4RF4[1]\); - - \r.d.inst_0_RNI2423_0[23]\ : NOR2 - port map(A => \inst_0_0[23]\, B => \inst_0_0[21]\, Y => - N_3518_1); - - \r.e.op2_RNO_3[5]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[5]\, Y - => \aluresult_m_i[5]\); - - \r.e.aluop_0_RNI9NOH[1]\ : OR2A - port map(A => aluresult_8_sqmuxa_1, B => - aluresult_9_sqmuxa_1, Y => aluresult_8_sqmuxa_i); - - \r.x.data_0_RNO_3[2]\ : OA1A - port map(A => \data_0[2]\, B => ld_0_0, C => \dco_m_i[106]\, - Y => \data_0_1_1_iv_0[2]\); - - \r.e.shleft_RNIKOJ03\ : MX2 - port map(A => \shiftin_5[59]\, B => \shiftin_5[43]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[43]\); - - \r.f.pc_RNO_4[17]\ : MX2 - port map(A => I_91, B => N_4060, S => bpmiss_1_i_0_0, Y => - \pc_4[17]\); - - \r.e.aluop_RNITMRR[1]\ : OR2B - port map(A => \un1_iu0_5[90]\, B => \aluop_3[1]\, Y => - N_246); - - \r.e.op1_RNO[30]\ : MX2C - port map(A => \d_i[30]\, B => \d_i[31]\, S => N_227, Y => - \aop1[30]\); - - \r.a.ctrl.pc[23]\ : DFN1E0 - port map(D => \dpc[23]\, CLK => lclk_c, E => holdn, Q => - \pc_3[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I95_un1_Y : OR2B - port map(A => N496, B => N493_0, Y => I95_un1_Y_1); - - \r.m.y_RNO_0[13]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[13]\, C => \y_m_0[13]\, - Y => \y_iv_1[13]\); - - \r.e.shleft_0_RNIBRBG\ : NOR2A - port map(A => \un1_iu0_6[7]\, B => shleft_0, Y => - shleft_0_RNIBRBG); - - \r.e.op2_RNO_4[25]\ : OA1A - port map(A => \maddress[25]\, B => d27_0, C => - \cpi_m_i[377]\, Y => \d_1_iv_1[25]\); - - \r.a.rsel2_RNICN4B[0]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[352]\, - Y => \cpi_m_i[352]\); - - \r.m.y_RNO_2[25]\ : OR2B - port map(A => \y_2[25]\, B => y08, Y => \y_m_0[25]\); - - \r.e.ctrl.inst[30]\ : DFN1E0 - port map(D => \inst[30]\, CLK => lclk_c, E => holdn, Q => - \inst_2[30]\); - - \r.d.inst_0_RNI6846[21]\ : NOR2A - port map(A => N_142, B => \inst_0_0[21]\, Y => N_145); - - \r.a.rfa1[5]\ : DFN1E0 - port map(D => \un3_de_ren1[96]\, CLK => lclk_c, E => holdn, - Q => \rfa1[5]\); - - \r.x.data_0[2]\ : DFN1E0 - port map(D => \data_0_1[2]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[2]\); - - \r.e.aluop_RNIFV0I6[0]\ : MX2C - port map(A => N_3572, B => N_3636, S => \aluop_1[0]\, Y => - \logicout[13]\); - - \r.x.ctrl.pc_RNISP971[22]\ : MX2C - port map(A => \un1_p0_6[374]\, B => \pc_0[22]\, S => - s_3_sqmuxa_0, Y => N_3413); - - \r.e.op2_RNI6NOP[26]\ : MX2 - port map(A => \op2[26]\, B => N_4273, S => ldbp2_2, Y => - \un1_iu0_5[92]\); - - \r.f.pc_RNO[15]\ : OR3C - port map(A => \tmp_m[15]\, B => \pc_1_iv_1[15]\, C => - \un6_fe_npc_m[13]\, Y => \pc_1[15]\); - - \r.e.op1_RNI3IC972[2]\ : OR3C - port map(A => \op1_m_i[2]\, B => \d_1_iv_3[2]\, C => - \aluresult_m_i[2]\, Y => \d_1[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I239_Y_1\ : OR3 - port map(A => I154_un1_Y, B => N520, C => I204_un1_Y, Y => - ADD_30x30_fast_I239_Y_1); - - \r.a.ctrl.inst[9]\ : DFN1E0 - port map(D => \inst_0[9]\, CLK => lclk_c, E => holdn, Q => - \inst[9]\); - - \r.w.s.wim_RNIP2QK5[2]\ : NOR3B - port map(A => \ex_op2_m[2]\, B => \wim_m[2]\, C => - \aluresult_4[1]\, Y => \aluresult_2_iv_2[2]\); - - \r.f.pc_RNO[31]\ : OR3C - port map(A => \tmp_m[31]\, B => \pc_1_iv_1[31]\, C => - \un6_fe_npc_m[29]\, Y => \pc_1[31]\); - - \r.x.data_0_RNO[6]\ : OR3C - port map(A => \dco_m_i[118]\, B => \data_0_1_1_iv_1[6]\, C - => \dco_m_i[102]\, Y => \data_0_1[6]\); - - \r.e.op2_RNIR2OP[21]\ : MX2A - port map(A => \op2[21]\, B => N_4268_i, S => ldbp2_1, Y => - \un1_iu0_5[87]\); - - \r.m.ctrl.cnt[1]\ : DFN1E0 - port map(D => \cnt[1]\, CLK => lclk_c, E => holdn, Q => - \cnt_1[1]\); - - \comb.v.x.data_0_1_1_iv_RNO_0[19]\ : AO1A - port map(A => ld_0_0, B => \data_0[19]\, C => - \dco_m_0[115]\, Y => \data_0_1_1_iv_0[19]\); - - \r.e.op1[22]\ : DFN1E0 - port map(D => \aop1[22]\, CLK => lclk_c, E => holdn, Q => - \op1[22]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I87_Y_0 : AO1 - port map(A => N407_2, B => N403_0, C => N406, Y => N546); - - un6_ex_add_res_d0_ADD_33x33_fast_I163_un1_Y : NAND2 - port map(A => N567, B => N574, Y => I163_un1_Y); - - \r.a.ctrl.inst_RNI5H3O1_0[19]\ : NOR3A - port map(A => N_226, B => N_203, C => N_204, Y => N_227_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I306_Y_0 : XNOR3 - port map(A => \un1_iu0_6[15]\, B => \op2[15]\, C => N796, Y - => \un6_ex_add_res_s1_i[16]\); - - \r.x.dci.size[0]\ : DFN1E0 - port map(D => \size_1[0]\, CLK => lclk_c, E => holdn, Q => - \size_2[0]\); - - \r.e.shcnt_RNO[2]\ : XOR2 - port map(A => \d_1[2]\, B => N_208, Y => N_268_i_i_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I319_Y_0 : AX1E - port map(A => N_51_i_1, B => ADD_33x33_fast_I262_Y_0_0, C - => ADD_33x33_fast_I319_Y_0_0, Y => - \un6_ex_add_res_s1[29]\); - - \r.e.op2_RNIRFMB1[13]\ : OR2A - port map(A => \un1_iu0_5[79]\, B => \un1_iu0_6[13]\, Y => - \logicout_4[13]\); - - \r.m.ctrl.inst_RNI2Q1S[22]\ : NOR2 - port map(A => inst_3_2_1, B => inst_3_2_0, Y => inst_3_2); - - \r.e.shleft_0_RNIGNBD1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[4]\, S => - shleft_0, Y => \shiftin_5[35]\); - - \r.e.aluop_1_RNIH0ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[12]\, B => \aluop_1[1]\, C => - \un1_iu0_5[78]\, Y => N_6919); - - \r.m.icc_RNO_8[2]\ : NOR2 - port map(A => \logicout[1]\, B => \logicout[20]\, Y => - icc_0_sqmuxa_1_14); - - \r.e.op2_RNO_2[22]\ : NOR3C - port map(A => \d_1_iv_1[22]\, B => \d_1_iv_0[22]\, C => - \rfo_m_i[54]\, Y => \d_1_iv_3[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I273_un1_Y_0 : NOR2B - port map(A => N552_0, B => N669_0, Y => - ADD_33x33_fast_I273_un1_Y_0_0); - - \r.e.op2_RNO_3[8]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[8]\, Y - => \aluresult_m_i[8]\); - - \r.m.irqen2_RNIF63C\ : NOR3C - port map(A => irqen, B => irqen2, C => un6_annul_1, Y => - un6_annul_2); - - \r.e.aluop_2[1]\ : DFN1E0 - port map(D => \aluop[1]\, CLK => lclk_c, E => holdn, Q => - \aluop_2[1]\); - - \r.m.y_RNO[13]\ : OR3C - port map(A => \y_iv_1[13]\, B => \y_iv_0[13]\, C => - \logicout_m[13]\, Y => \y_1[13]\); - - \r.e.ldbp2_RNIJDFUV3\ : OR3C - port map(A => \aluresult_1_iv_7[15]\, B => - \shiftin_17_m_0[15]\, C => \un6_ex_add_res_m[16]\, Y => - \aluresult[15]\); - - \r.w.s.icc[3]\ : DFN1E0 - port map(D => \icc_1[3]\, CLK => lclk_c, E => holdn, Q => - \icc_0[3]\); - - \r.m.result[1]\ : DFN1E0 - port map(D => \eres2[1]\, CLK => lclk_c, E => holdn, Q => - \maddress[1]\); - - \r.d.inst_0_0_0_RNI35KP[21]\ : NOR3B - port map(A => bicc_hold_1, B => N_3736_2, C => un1_inst, Y - => bicc_hold_3); - - \comb.branch_address.tmp_ADD_30x30_fast_I185_Y\ : AO1 - port map(A => N555, B => N358, C => N554, Y => N614); - - \comb.irq_trap.un5_irl_1\ : NOR2B - port map(A => irl_0(2), B => irl_0(3), Y => un5_irl_1); - - \r.f.pc_RNO_6[26]\ : MX2 - port map(A => \fpc[26]\, B => \eaddress[26]\, S => jump_0, - Y => N_4069); - - \r.e.op2_RNIQ2VD4[6]\ : AOI1B - port map(A => \un1_iu0_5[72]\, B => aluresult_7_sqmuxa_0_0, - C => \aluresult_1_iv_0[6]\, Y => \aluresult_1_iv_1[6]\); - - \r.a.imm_RNO[18]\ : MX2 - port map(A => \inst_0[8]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[136]\); - - \r.e.shleft_0_RNIL1PK3\ : MX2 - port map(A => \shiftin_5[61]\, B => \shiftin_5[45]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[45]\); - - \r.a.ctrl.inst[18]\ : DFN1E0 - port map(D => \inst_0[18]\, CLK => lclk_c, E => holdn, Q - => \inst_1[18]\); - - \r.e.ldbp1_4\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_4); - - \r.w.result[11]\ : DFN1E0 - port map(D => \wdata[11]\, CLK => lclk_c, E => holdn, Q => - \result[11]\); - - \r.e.op1_RNIV3P873[10]\ : NOR3C - port map(A => \op1_m_0[10]\, B => \d_iv_2[10]\, C => - \aluresult_m_0[10]\, Y => \d_i[10]\); - - \r.e.op1_RNIQ94M7[7]\ : OR2B - port map(A => \edata2_0_iv_0[7]\, B => \bpdata_i_m[7]\, Y - => edata2_0_iv(7)); - - \r.m.y_RNO[17]\ : AO1C - port map(A => y14_0, B => \logicout[17]\, C => \y_iv_2[17]\, - Y => \y_1[17]\); - - \r.f.pc_RNO_3[19]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[19]\, C => - \xc_trap_address_m[19]\, Y => \pc_1_iv_0[19]\); - - \r.e.shcnt_RNIQQVS4[3]\ : MX2 - port map(A => \shiftin_8[19]\, B => \shiftin_8[11]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[11]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I98_Y : NOR2A - port map(A => N495, B => N_50, Y => N561_i); - - \r.a.ctrl.inst[20]\ : DFN1E0 - port map(D => \inst_0[20]\, CLK => lclk_c, E => holdn, Q - => \inst_2[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I23_G0N : NOR3A - port map(A => \op1[22]\, B => ldbp1_4, C => \data_0_0[22]\, - Y => N463_2); - - \r.e.ldbp2_RNIFKJUB1\ : MX2 - port map(A => \un6_ex_add_res_s1[14]\, B => N_6633, S => - ldbp2_3, Y => \eaddress[13]\); - - \r.e.op1_RNO[27]\ : MX2C - port map(A => \d_i[27]\, B => \d_i[28]\, S => N_227, Y => - \aop1[27]\); - - \r.e.bp_RNI77CD_0\ : NOR3A - port map(A => bp_0, B => annul, C => \inst_2[28]\, Y => - N_475); - - \r.x.laddr_RNIH68NE1_0[0]\ : NOR3C - port map(A => \me_laddr_2[1]\, B => \me_laddr_2[0]\, C => - rdata_3_sqmuxa_2, Y => rdata_3_sqmuxa); - - \r.m.result_RNO[16]\ : MX2 - port map(A => \aluresult[16]\, B => \op1[16]\, S => - un17_casaen_0_1, Y => \eres2[16]\); - - \r.e.ctrl.pc[7]\ : DFN1E0 - port map(D => \pc_3[7]\, CLK => lclk_c, E => holdn, Q => - \pc_0[7]\); - - \r.x.result_RNITK6E[25]\ : MX2 - port map(A => \result_0[25]\, B => \data_0[25]\, S => ld_4, - Y => \un1_p0_6[377]\); - - \r.e.op2_RNO_4[8]\ : OA1A - port map(A => \maddress[8]\, B => d27_0, C => - \cpi_m_i[360]\, Y => \d_1_iv_1[8]\); - - \r.x.rstate_RNIJEP02[0]\ : MX2C - port map(A => N_3409, B => \xc_result[18]\, S => - \rstate[0]\, Y => \wdata[18]\); - - \r.w.s.y_RNO_1[14]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y[14]\, Y => N_382); - - \r.a.ctrl.inst_RNICC1E[19]\ : OR2B - port map(A => \inst_2[20]\, B => \inst_2[19]\, Y => N_487); - - un6_ex_add_res_d1_ADD_33x33_fast_I172_Y : NOR2B - port map(A => N583_1, B => N575_1, Y => N641_0); - - \r.e.op1_RNIF1UB[4]\ : OR2A - port map(A => un17_casaen_0, B => \op1[4]\, Y => - \op1_i_m[4]\); - - \r.a.ctrl.inst_RNIE1HC6[5]\ : NOR3B - port map(A => un1_illegal_inst33_0, B => - privileged_inst_0_sqmuxa, C => illegal_inst33, Y => - un1_illegal_inst33_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I316_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[25]\, B => \op2[25]\, Y => - ADD_33x33_fast_I316_Y_0_0); - - \r.d.inst_0_RNINSV2[31]\ : NOR2A - port map(A => \inst_0[31]\, B => annul_1, Y => ldcheck1_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I120_Y : NOR2 - port map(A => N521_0, B => N517_1, Y => N583_2); - - \r.w.s.y_RNO[7]\ : MX2 - port map(A => \y_2[7]\, B => \result_0[7]\, S => N_481_0, Y - => N_3771); - - \r.f.pc_RNO_4[27]\ : MX2 - port map(A => I_173, B => N_4070, S => bpmiss_1_i_0, Y => - \pc_4[27]\); - - \r.e.op2_RNO[5]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[5]\, Y => N_289); - - \r.e.aluop_RNIOVP04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[1]\, Y => - \bpdata_i_m_2[1]\); - - \r.d.inst_0_RNI12TD1[0]\ : NOR2 - port map(A => \inst_0_RNI0FUM[0]\, B => \inst_0_RNI1JUM[1]\, - Y => un1_rs1_0); - - \r.a.rsel1_0_RNI83LJ2[2]\ : OR2B - port map(A => data1(11), B => d11, Y => \rfo_m[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I35_Y\ : NOR2B - port map(A => N437_1, B => N434_1, Y => N452); - - \r.m.ctrl.rd_RNIVH85C[5]\ : OR3C - port map(A => un1_de_ren1_1_5_i_0, B => wreg_5, C => - un1_de_ren1_1_6_i_0, Y => wreg_1); - - \r.e.ctrl.rd_RNI1KQS1[3]\ : XA1A - port map(A => \un3_de_ren1[94]\, B => \rd[3]\, C => - un2_rs1_1_6_i_0, Y => wreg_2_3); - - \r.m.y[18]\ : DFN1E0 - port map(D => \y_0[18]\, CLK => lclk_c, E => holdn, Q => - \y_1[18]\); - - \r.e.shcnt_RNIO57AL[1]\ : MX2C - port map(A => \shiftin_14[8]\, B => \shiftin_14[6]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[6]\); - - \r.e.op2_RNO_7[24]\ : OR2A - port map(A => \maddress[24]\, B => d27, Y => - \result_m_i[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I151_Y : AO1 - port map(A => N552, B => N549_0, C => N548_1, Y => N614_1); - - \r.f.pc_RNO_0[30]\ : NAND2 - port map(A => \tmp[30]\, B => \un2_rstn_5\, Y => - \tmp_m[30]\); - - \r.e.ctrl.rd_RNIUA09B1[6]\ : NOR3A - port map(A => rfe_2, B => wreg_1_8, C => un1_de_ren1_2, Y - => rfe); - - \comb.branch_address.tmp_ADD_30x30_fast_I163_Y\ : NOR2A - port map(A => N529, B => N537, Y => N589); - - \r.e.ctrl.inst_RNILDSK2[26]\ : AO1 - port map(A => ex_bpmiss_1_0_a5_0, B => N_328, C => N_427, Y - => ex_bpmiss_1_0_0); - - \r.x.npc_RNIUS311[0]\ : MX2C - port map(A => N_3228, B => N_3258, S => \npc[0]\, Y => - \xc_result[17]\); - - \r.e.ctrl.pc_RNIAHK11[15]\ : OR2B - port map(A => \pc_2[15]\, B => jmpl_4, Y => \cpi_m[160]\); - - \r.a.ctrl.inst_RNIVB1K1[30]\ : AO1A - port map(A => N_219, B => \inst[30]\, C => N_478, Y => - N_236); - - un6_ex_add_res_d0_ADD_33x33_fast_I131_Y : AO1 - port map(A => N532, B => N529_0, C => N528_0, Y => N594_0); - - \comb.cwp_ctrl.ncwp_3_I_5\ : NOR2A - port map(A => \cwp[1]\, B => \inst_0[19]\, Y => - \DWACT_ADD_CI_0_g_array_0_1[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I62_Y : NOR2B - port map(A => N446_0, B => N443, Y => N521_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I303_Y_0_1 : XNOR2 - port map(A => \un1_iu0_6[12]\, B => \data_0_2[12]\, Y => - \un6_ex_add_res_s0_1[13]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0_a3_0_0\ : - NOR2A - port map(A => N437_1, B => N440_2, Y => - ADD_30x30_fast_I233_Y_0_a3_0); - - \r.e.ctrl.pc[4]\ : DFN1E0 - port map(D => \pc_0[4]\, CLK => lclk_c, E => holdn, Q => - \pc[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I165_un1_Y : AO1B - port map(A => ADD_33x33_fast_I113_Y_0_0, B => I113_un1_Y_i, - C => N569_1, Y => I165_un1_Y_0); - - \r.e.aluop_RNI5NNF[1]\ : OR2B - port map(A => \aluop_3[1]\, B => \aluop_1[0]\, Y => - logicout22_1); - - \r.m.icc_RNIVN961[3]\ : OR2A - port map(A => \icc[3]\, B => aluresult_11_sqmuxa, Y => - \icc_m[3]\); - - \r.a.imm_RNO[15]\ : MX2 - port map(A => \inst_0[5]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[133]\); - - \r.x.ctrl.pc_RNIP3531[8]\ : MX2C - port map(A => \un1_p0_6[360]\, B => \pc_0[8]\, S => - s_3_sqmuxa_0, Y => N_3399); - - \r.e.shleft_1_RNIKBV81\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[6]\, S => - shleft_1, Y => \shiftin_5[37]\); - - \r.w.result_RNIIJQL[30]\ : AOI1B - port map(A => \un1_p0_6[382]\, B => d14_0, C => - \result_m_0_0[30]\, Y => \d_iv_0[30]\); - - \r.m.result[23]\ : DFN1E0 - port map(D => \eres2[23]\, CLK => lclk_c, E => holdn, Q => - \maddress[23]\); - - \r.m.ctrl.pc_RNIC1N9[25]\ : MX2 - port map(A => \pc_3[25]\, B => \pc_0[25]\, S => \npc[1]\, Y - => N_3266); - - \r.m.y_RNIVPO71[27]\ : OR2B - port map(A => \y_0[27]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[27]\); - - \r.m.ctrl.pc_RNI4PL9[30]\ : MX2 - port map(A => \pc_3[30]\, B => \pc[30]\, S => \npc[1]\, Y - => N_3271); - - un6_ex_add_res_d1_ADD_33x33_fast_I137_Y : AO1B - port map(A => N538_1, B => N535_0, C => - ADD_33x33_fast_I137_Y_0_0, Y => N600_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I132_Y_0\ : MAJ3 - port map(A => \dpc[7]\, B => \inst_0[5]\, C => N370, Y => - ADD_30x30_fast_I132_Y_0); - - \r.m.result_0_RNI7MR8[3]\ : OR2A - port map(A => \maddress_0[3]\, B => d27, Y => - \result_m_i[3]\); - - \r.e.shcnt_RNI7P6DK[1]\ : MX2C - port map(A => \shiftin_14[6]\, B => \shiftin_14[4]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[4]\); - - \r.e.aluop_0_RNI6HIK5[0]\ : OR2B - port map(A => \logicout[30]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I187_Y : AO1A - port map(A => N591_2, B => N598_0, C => N590_2, Y => N656_1); - - \r.e.ldbp2_0_RNIG2K3Q4\ : MX2C - port map(A => \un6_ex_add_res_s1_i[30]\, B => N_6576, S => - ldbp2_0, Y => \eaddress[29]\); - - \r.d.inst_0_0_0_RNI2OAFO2[12]\ : MX2 - port map(A => data_0_0_12, B => \un1_p0_6_0[51]\, S => - mexc_1_sqmuxa_1_0, Y => N_4612); - - \r.x.data_0_RNIIJ9E[28]\ : XOR2 - port map(A => \data_0[28]\, B => invop2_1, Y => N_4275); - - \r.x.ctrl.annul_RNI2ROB_0\ : OR2 - port map(A => annul_0, B => \un1_p0_6[349]\, Y => xc_wreg9); - - \r.m.result_RNIK2TD3[25]\ : NOR3C - port map(A => \d_iv_0[25]\, B => \result_m_0[25]\, C => - \rfo_m[25]\, Y => \d_iv_2[25]\); - - \r.a.rfa2[7]\ : DFN1 - port map(D => \raddr2[7]\, CLK => lclk_c, Q => \rfa2[7]\); - - \r.f.pc_RNO[26]\ : OR3C - port map(A => \tmp_m[26]\, B => \pc_1_iv_1[26]\, C => - \un6_fe_npc_m[24]\, Y => \pc_1[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I14_G0N : OA1 - port map(A => \op1[13]\, B => ldbp1_1, C => \data_0[13]\, Y - => N436_2); - - \r.d.inst_0_RNO_0[23]\ : MX2 - port map(A => data_0_0_23, B => \inst_0_0[23]\, S => - inull_RNIFV6VG2_0, Y => N_4623); - - un6_ex_add_res_d0_ADD_33x33_fast_I184_Y : NOR2B - port map(A => N595_1, B => N587_0, Y => N653_0); - - \r.e.aluop_0_RNI3LVG[1]\ : XOR3 - port map(A => \un1_iu0_6[0]\, B => \aluop_0[1]\, C => - \op2_RNI59C6[0]\, Y => N_6865); - - \r.a.ctrl.pc[21]\ : DFN1E0 - port map(D => \dpc[21]\, CLK => lclk_c, E => holdn, Q => - \pc[21]\); - - \r.m.y_RNO_3[19]\ : OR3A - port map(A => \y_2[19]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[19]\); - - \r.d.inull_RNII4QJ1\ : MX2C - port map(A => annul_2_0, B => N_3034, S => N_3033_1_i, Y - => \hold_pc_7\); - - \r.e.jmpl_RNICLDQ81\ : AND2 - port map(A => \shiftin_17_m[7]\, B => \aluresult_1_iv_7[6]\, - Y => \aluresult_1_iv_8[6]\); - - \r.d.inst_0_RNO_0[25]\ : MX2 - port map(A => data_0_2_25, B => \inst_0[25]\, S => - inull_RNIFV6VG2_0, Y => N_4625); - - un6_ex_add_res_d2_ADD_33x33_fast_I174_Y : OR2B - port map(A => N585_1, B => N577_1, Y => N643); - - \r.m.ctrl.cnt_RNIEEAK6[0]\ : OA1B - port map(A => trap_0_sqmuxa_4, B => un1_trap_0_sqmuxa_1_0, - C => trap_1_sqmuxa_1, Y => trap_1_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I284_Y_0\ : XNOR2 - port map(A => N704, B => ADD_30x30_fast_I284_Y_0_0, Y => - \tmp[26]\); - - \r.d.pc[29]\ : DFN1 - port map(D => \pc_RNO[29]\, CLK => lclk_c, Q => \dpc[29]\); - - \r.d.inst_0_RNI66J4[23]\ : OR3A - port map(A => \inst_0_0[24]\, B => \inst_0_0[22]\, C => - \inst_0_0[23]\, Y => un3_op2); - - \r.e.shleft_0_RNIL3CQ1\ : MX2A - port map(A => \shiftin_5[23]\, B => shleft_0_RNIBRBG, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[7]\); - - \r.a.rsel2_0_RNIFA4D_2[0]\ : NOR2A - port map(A => d26, B => un17_casaen_0_2, Y => - un14_casaen_s0_0_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I244_Y\ : NOR3 - port map(A => I244_un1_Y_0, B => N590, C => I214_un1_Y, Y - => N718_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I41_Y : MAJ3 - port map(A => \data_0[26]\, B => \un1_iu0_6[26]\, C => - N472_1, Y => N500_0); - - \r.w.s.tba_RNIVT0JF[1]\ : NOR3C - port map(A => \aluresult_1_iv_2[13]\, B => \tba_m[1]\, C - => \aluresult_1_iv_4[13]\, Y => \aluresult_1_iv_5[13]\); - - \r.e.ldbp2_RNIDO5E7\ : MX2C - port map(A => \un6_ex_add_res_s1_i[5]\, B => N_6644, S => - ldbp2_3, Y => \eaddress[4]\); - - \r.e.alusel_RNO_1[1]\ : NOR2A - port map(A => \inst[22]\, B => N_602, Y => N_341); - - \r.m.y_RNO_1[13]\ : AOI1B - port map(A => \y[13]\, B => y08, C => \y_m[14]\, Y => - \y_iv_0[13]\); - - \r.e.aluop_2_RNIUCAS1[1]\ : MX2C - port map(A => N_3528, B => \logicout_3[1]\, S => - \aluop_2[1]\, Y => N_3560); - - \comb.branch_address.tmp_ADD_30x30_fast_I9_P0N\ : OR2 - port map(A => \inst_0[9]\, B => \dpc[11]\, Y => N386); - - \r.f.pc_RNO[4]\ : OR3C - port map(A => \tmp_m[4]\, B => \pc_1_iv_1[4]\, C => - \un6_fe_npc_m[2]\, Y => \pc_1[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I164_Y : NOR2B - port map(A => N575_0, B => N567, Y => N633); - - \r.x.ctrl.pc_RNINMF8[5]\ : MX2 - port map(A => \pc_3[5]\, B => \pc[5]\, S => \npc[1]\, Y => - N_3216); - - \r.e.shcnt_RNIKVP67[3]\ : MX2 - port map(A => \shiftin_8[43]\, B => \shiftin_8[35]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[35]\); - - \r.a.ctrl.inst_RNIFO1E_0[23]\ : NOR2A - port map(A => \inst_1[23]\, B => \inst_2[19]\, Y => - inst_11_0); - - un6_fe_npc_I_139 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \fe_pc[23]\, Y => - \DWACT_FINC_E[16]\); - - \r.f.pc_RNI5Q6S64[7]\ : NOR2B - port map(A => \un6_fe_npc_m[5]\, B => - \xc_trap_address_m[7]\, Y => \npc_iv_2[7]\); - - \r.w.s.wim[6]\ : DFN1E0 - port map(D => \wim_1[6]\, CLK => lclk_c, E => holdn, Q => - \wim[6]\); - - \r.x.data_0_RNO_0[17]\ : OR3 - port map(A => \dco_m_0[113]\, B => \data_0_m[17]\, C => - \data_0_1_1[16]\, Y => \data_0_1_1_iv_1[17]\); - - \r.e.op1_RNIL04F[3]\ : OR2B - port map(A => \op1[3]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[3]\); - - \r.m.icc_RNISEJF3[1]\ : NOR3C - port map(A => \ex_op2_m[21]\, B => aluresult_8_sqmuxa_i, C - => \icc_m[1]\, Y => \aluresult_1_iv_2[21]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I155_un1_Y : OR3C - port map(A => N493, B => N497, C => N566, Y => I155_un1_Y_0); - - \r.m.y_RNI4JC92[23]\ : AOI1B - port map(A => \y[23]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[168]\, Y => \aluresult_1_iv_1[23]\); - - \r.m.y[29]\ : DFN1E0 - port map(D => \y_1[29]\, CLK => lclk_c, E => holdn, Q => - \y[29]\); - - \r.e.op2_RNO_2[15]\ : NOR3C - port map(A => \d_1_iv_1[15]\, B => \d_1_iv_0[15]\, C => - \rfo_m_i[47]\, Y => \d_1_iv_3[15]\); - - un6_fe_npc_I_91 : XOR2 - port map(A => N_88, B => \fe_pc[17]\, Y => I_91); - - \r.m.result_RNI3HB4[6]\ : OR2B - port map(A => d13, B => \maddress[6]\, Y => \result_m_0[6]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I181_Y\ : NOR2A - port map(A => N555, B => N547, Y => N607); - - \r.x.data_0[16]\ : DFN1E0 - port map(D => \data_0_1[16]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[16]\); - - \r.x.ctrl.trap_RNI5VL8\ : NOR2 - port map(A => mexc_0, B => trap_5, Y => \un1_p0_6[349]\); - - \r.m.y_RNO_1[28]\ : OR2B - port map(A => \y[29]\, B => mulstep_1, Y => \y_m[29]\); - - \r.e.ctrl.rd_RNIQP6H1[7]\ : XOR2 - port map(A => \rd_1[7]\, B => un1_reg, Y => - \rd_RNIQP6H1[7]\); - - \r.e.ldbp2_1_RNIHE5NT4\ : OR2B - port map(A => \aluresult_1_iv_8[17]\, B => - \un6_ex_add_res_m[18]\, Y => \aluresult[17]\); - - \r.e.aluop_RNIHA56M[0]\ : AOI1B - port map(A => \logicout[18]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_5[18]\, Y => \aluresult_1_iv_6[18]\); - - \r.f.pc_RNO_7[29]\ : MX2 - port map(A => \fpc[29]\, B => \tba[17]\, S => rstate_6314_d, - Y => \xc_trap_address[29]\); - - \r.f.pc[14]\ : DFN1E0 - port map(D => N_8_0_i_0, CLK => lclk_c, E => holdn, Q => - \fpc[14]\); - - \r.a.imm_RNO[20]\ : MX2 - port map(A => \inst_0[10]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[138]\); - - \r.e.op2_RNO_8[8]\ : OR3B - port map(A => d29_0_0, B => \imm[8]\, C => \rsel2_0[0]\, Y - => \imm_m_i[8]\); - - \r.x.result[3]\ : DFN1E0 - port map(D => \maddress[3]\, CLK => lclk_c, E => holdn, Q - => \result_0[3]\); - - \r.d.annul_RNIEC3SK5\ : OR2B - port map(A => I_52, B => annul_RNIVCQHS1, Y => N_31); - - \r.x.rstate_RNIMCA72[0]\ : MX2C - port map(A => N_3407, B => \xc_result[16]\, S => - \rstate[0]\, Y => \wdata[16]\); - - \r.x.rstate[1]\ : DFN1 - port map(D => N_6323s, CLK => lclk_c, Q => \rstate[1]\); - - \r.a.rsel2_RNO_0[1]\ : NOR2A - port map(A => wreg_1, B => wreg_1_8, Y => N_3950); - - \r.e.ctrl.rd_RNIO9OBC[6]\ : XA1A - port map(A => \rd_0[6]\, B => \un3_de_ren1[105]\, C => - wreg_1_6, Y => wreg_1_8); - - \r.a.ticc_RNO_0\ : NOR3A - port map(A => ticc_exception_1, B => annul_1, C => un1_inst, - Y => ticc_exception_0_a3_1); - - \r.x.ctrl.rd[4]\ : DFN1E0 - port map(D => \rd[4]\, CLK => lclk_c, E => holdn, Q => - \rd_2[4]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I86_un1_Y\ : OR3A - port map(A => N451, B => N440_2, C => N443_2, Y => - I86_un1_Y); - - un6_ex_add_res_d0_ADD_33x33_fast_I309_Y_0 : XNOR3 - port map(A => \data_0_0[18]\, B => \un1_iu0_6[18]\, C => - N790, Y => \un6_ex_add_res_s0[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I87_Y_0 : AO1 - port map(A => N407, B => N403_1, C => N406_0, Y => N546_2); - - \r.x.ctrl.rd_RNI6SGO[2]\ : NOR2B - port map(A => \rd_3[2]\, B => N_6357, Y => waddr(2)); - - un6_ex_add_res_d2_ADD_33x33_fast_I137_Y_0 : MIN3 - port map(A => \data_0[9]\, B => \un1_iu0_6[9]\, C => N421_1, - Y => ADD_33x33_fast_I137_Y_0_1); - - \comb.irq_trap.un5_irl_0\ : NOR2B - port map(A => irl_0(0), B => irl_0(1), Y => un5_irl_0); - - \r.e.shcnt_RNI5AQVR[1]\ : MX2C - port map(A => \shiftin_14[27]\, B => \shiftin_14[25]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[25]\); - - \r.a.ctrl.inst_RNISS231[30]\ : NOR3B - port map(A => \inst_1[24]\, B => N_205, C => \inst[30]\, Y - => N_478); - - \r.x.rstate_0_RNIHG622[0]\ : MX2C - port map(A => N_3399, B => \xc_result[8]\, S => - \rstate_0[0]\, Y => \wdata[8]\); - - \r.f.pc_RNO_0[17]\ : NAND2 - port map(A => \tmp[17]\, B => \un2_rstn_5\, Y => - \tmp_m[17]\); - - \r.w.s.y_RNO[6]\ : MX2 - port map(A => \y_2[6]\, B => \result_0[6]\, S => N_481_0, Y - => N_3770); - - \r.w.result_RNIOI3C[1]\ : AOI1B - port map(A => \result[1]\, B => d31, C => \imm_m_i[1]\, Y - => \d_1_iv_0[1]\); - - \r.m.result_RNIFPR73[14]\ : NOR3C - port map(A => \d_iv_0[14]\, B => \result_m_0[14]\, C => - \rfo_m[14]\, Y => \d_iv_2[14]\); - - \r.m.y_RNO_4[11]\ : OR2B - port map(A => \y[12]\, B => mulstep_1, Y => \y_m[12]\); - - \r.m.y_RNO_2[9]\ : OR2B - port map(A => \y_1[9]\, B => y08, Y => \y_m_0[9]\); - - \r.x.data_0_RNO_4[6]\ : OR2A - port map(A => \data_0[6]\, B => ld_0_0, Y => - \data_0_m_i[6]\); - - \r.d.pc[5]\ : DFN1 - port map(D => \pc_RNO[5]\, CLK => lclk_c, Q => \dpc[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I111_Y : AO1 - port map(A => N512_0, B => N509, C => N508, Y => N574_1); - - \r.m.y_RNO_0[14]\ : AOI1B - port map(A => wy_1_0, B => \y[14]\, C => N_387, Y => - \y_iv_0_1[14]\); - - \r.e.op1_RNIKJO8[8]\ : MX2 - port map(A => \op1[8]\, B => \data_0[8]\, S => ldbp1_1, Y - => \un1_iu0_6[8]\); - - \r.e.shleft_0_RNIQCT43\ : MX2 - port map(A => \shiftin_5[47]\, B => \shiftin_5[31]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[31]\); - - \r.x.result[27]\ : DFN1E0 - port map(D => \maddress[27]\, CLK => lclk_c, E => holdn, Q - => \result_0[27]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I140_Y : NOR2B - port map(A => N541_0, B => N537_0, Y => N603); - - \comb.branch_address.tmp_ADD_30x30_fast_I100_Y\ : AO1B - port map(A => N465, B => N462, C => ADD_30x30_fast_I100_Y_0, - Y => N520); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_Y_0 : AOI1 - port map(A => N500_0, B => N497, C => N496_1, Y => - ADD_33x33_fast_I261_Y_0_0); - - \r.x.result_RNI4NED[19]\ : MX2 - port map(A => \result_0[19]\, B => \data_0[19]\, S => ld_0, - Y => \un1_p0_6[371]\); - - \r.d.pc[14]\ : DFN1 - port map(D => \pc_RNO[14]\, CLK => lclk_c, Q => \dpc[14]\); - - \r.m.ctrl.rd_RNICD3O[7]\ : XNOR2 - port map(A => \rd_0[7]\, B => \un3_de_ren1[98]\, Y => - un2_rs1_2_7_i_0); - - \r.e.op1_RNO_0[31]\ : XNOR2 - port map(A => \icco[3]\, B => \icco[1]\, Y => - \aop1_1_i[31]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I223_un1_Y : OR2B - port map(A => N652_1, B => N637_1, Y => I223_un1_Y_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I138_Y_0 : OA1 - port map(A => \data_0[6]\, B => \un1_iu0_6[6]\, C => N419_0, - Y => ADD_33x33_fast_I138_Y_0_0); - - \r.f.pc[11]\ : DFN1E0 - port map(D => N_15, CLK => lclk_c, E => holdn, Q => - \fpc[11]\); - - \r.e.aluop_2_RNIK5713[1]\ : MX2C - port map(A => N_3545, B => \logicout_3[18]\, S => - \aluop_2[1]\, Y => N_3577); - - \r.f.pc_RNI1T85[10]\ : OR2A - port map(A => \fpc[10]\, B => rst, Y => \pc_m[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I265_Y_1 : NOR3B - port map(A => I167_un1_Y_i, B => I223_un1_Y_i, C => N570_1, - Y => ADD_33x33_fast_I265_Y_1_1); - - \r.w.s.y_RNO[14]\ : NOR3 - port map(A => N_383, B => N_382, C => N_384, Y => N_153); - - \r.e.op2_RNO_4[10]\ : OR2B - port map(A => \op1[10]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[10]\); - - \r.x.ctrl.tt_RNO[5]\ : MX2B - port map(A => un1_trap_0_sqmuxa_5, B => N_4209, S => - N_4210_i_0, Y => \tt2[5]\); - - \r.e.jmpl_RNI221OS_0\ : OR2B - port map(A => \shiftin_17[25]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[25]\); - - \r.x.data_0_RNI7RS8[5]\ : XOR2 - port map(A => \data_0[5]\, B => invop2_1, Y => N_4252); - - \r.d.inst_0_RNIU3LJ[26]\ : MX2C - port map(A => N_3349, B => N_3350, S => \inst_0[26]\, Y => - N_3351); - - \r.m.ctrl.pc_RNIPPGF[12]\ : MX2 - port map(A => \pc_3[12]\, B => \pc[12]\, S => \npc_0[1]\, Y - => N_3253); - - \r.m.y_RNO_3[30]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[30]\, C => \y_m[30]\, Y - => \y_iv_1[30]\); - - \r.a.rfa1_RNI5OLJ1[6]\ : MX2 - port map(A => \un3_de_ren1[97]\, B => \rfa1[6]\, S => holdn, - Y => raddr1(6)); - - \r.a.ctrl.inst_RNI3D3H1[21]\ : OR3 - port map(A => N_201, B => alusel24_2, C => N_205, Y => - N_458); - - \r.e.aluop_0_RNIOL6R[1]\ : XOR3 - port map(A => \un1_iu0_6[7]\, B => \aluop_0[1]\, C => - \un1_iu0_5[73]\, Y => N_6871); - - \r.m.y_RNO_1[5]\ : OR2B - port map(A => \y_0[6]\, B => mulstep_1, Y => \y_m[6]\); - - \r.e.op2_RNO_5[23]\ : OR2B - port map(A => \result_0[23]\, B => d31, Y => - \result_m_i[23]\); - - \r.e.op2_RNO_7[21]\ : OR3B - port map(A => d29_0, B => \imm[21]\, C => \rsel2[0]\, Y => - \imm_m_i[21]\); - - \r.d.pv\ : DFN1E0 - port map(D => pv_6, CLK => lclk_c, E => holdn, Q => pv); - - \r.m.y_RNO[3]\ : AO1C - port map(A => y14_0, B => \logicout[3]\, C => \y_iv_2[3]\, - Y => \y_0[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I322_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[31]\, B => \data_0_0[31]\, Y => - \un6_ex_add_res_s2_1[32]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I320_Y_0 : XNOR2 - port map(A => N768_1, B => ADD_33x33_fast_I320_Y_0_0, Y => - \un6_ex_add_res_s1_i[30]\); - - \r.m.nalign\ : DFN1E0 - port map(D => un12_ex_add_res, CLK => lclk_c, E => holdn, Q - => nalign); - - \r.m.ctrl.pc_RNI8IIF[19]\ : MX2 - port map(A => \pc_2[19]\, B => \pc_3[19]\, S => \npc_1[1]\, - Y => N_3260); - - \comb.branch_address.tmp_ADD_30x30_fast_I78_Y\ : AO13 - port map(A => \inst_0_RNI4VUM[4]\, B => \dpc[6]\, C => N367, - Y => N495_1); - - \r.e.shcnt_RNI7PA7A[2]\ : MX2C - port map(A => \shiftin_11[10]\, B => \shiftin_11[6]\, S => - \ex_shcnt_1_i[2]\, Y => \shiftin_14[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I167_un1_Y : OR2B - port map(A => N578, B => N571_2, Y => I167_un1_Y_i); - - \r.x.data_0_RNO[0]\ : AO1B - port map(A => N_3456, B => data_0_0_0, C => - \data_0_1_1_iv_2[0]\, Y => \data_0_1[0]\); - - \r.m.ctrl.tt[0]\ : DFN1E0 - port map(D => \tt_2[0]\, CLK => lclk_c, E => holdn, Q => - \tt_0[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I267_Y : NAND2 - port map(A => I267_un1_Y_1, B => ADD_33x33_fast_I267_Y_0_1, - Y => N780_0); - - \r.m.y[19]\ : DFN1E0 - port map(D => \y_1[19]\, CLK => lclk_c, E => holdn, Q => - \y_0[19]\); - - \r.e.shcnt_RNISCPM3[3]\ : MX2 - port map(A => \shiftin_8[9]\, B => \shiftin_8[1]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[1]\); - - \r.e.cwp[0]\ : DFN1E0 - port map(D => \cwp_2[0]\, CLK => lclk_c, E => holdn, Q => - \cwp_1[0]\); - - \r.m.ctrl.rd[1]\ : DFN1E0 - port map(D => \rd[1]\, CLK => lclk_c, E => holdn, Q => - \rd_0[1]\); - - \r.e.op1_RNI1NNF[15]\ : NOR2A - port map(A => un17_casaen_0_2, B => \op1[15]\, Y => - \op1_i_m[15]\); - - \r.e.op2_RNO_8[31]\ : OR3B - port map(A => d29_0, B => \imm[31]\, C => \rsel2[0]\, Y => - \imm_m_i[31]\); - - \r.w.s.y_RNO[10]\ : MX2 - port map(A => \y_2[10]\, B => \result[10]\, S => N_481, Y - => N_3774); - - \r.w.s.y[4]\ : DFN1E0 - port map(D => N_3768, CLK => lclk_c, E => N_6922_i, Q => - \y_2[4]\); - - \r.f.pc_RNO_1[15]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[15]\, C => - \pc_1_iv_0[15]\, Y => \pc_1_iv_1[15]\); - - \r.x.result[12]\ : DFN1E0 - port map(D => \maddress[12]\, CLK => lclk_c, E => holdn, Q - => \result[12]\); - - \r.m.dci.SIGNED_RNO_0\ : NOR3A - port map(A => \inst_1[22]\, B => \inst[24]\, C => - \inst_1[21]\, Y => SIGNED_2_1); - - \r.x.data_0[23]\ : DFN1E0 - port map(D => \data_0_1[23]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[23]\); - - \r.x.data_0_RNO[22]\ : OR3 - port map(A => \dco_m_0[118]\, B => \data_0_m[22]\, C => - \data_0_1_4[18]\, Y => \data_0_1[22]\); - - \r.x.ctrl.inst_RNI2JBD2[30]\ : OR3C - port map(A => y11, B => y15, C => xc_wreg_0_sqmuxa, Y => - s_2_sqmuxa); - - \r.a.su\ : DFN1E0 - port map(D => \su_0\, CLK => lclk_c, E => holdn, Q => su_1); - - \r.e.op2_RNIIGNB1_0[26]\ : OR2 - port map(A => \un1_iu0_6[26]\, B => \un1_iu0_5[92]\, Y => - \logicout_3[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I13_G0N : OAI1 - port map(A => \op1[12]\, B => ldbp1_1, C => \data_0_2[12]\, - Y => N433_1); - - \r.e.op2_RNO_3[12]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[12]\, Y - => \aluresult_m_i[12]\); - - \r.m.y_RNO_3[16]\ : OR3A - port map(A => \y_2[16]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[16]\); - - \r.e.op1_RNI8HFC[4]\ : OR2B - port map(A => \op1[4]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[4]\); - - \r.d.pv_RNICUFKC\ : OR2B - port map(A => un25_exbpmiss, B => un9_rabpmiss, Y => - inhibit_current); - - \r.x.ctrl.inst[23]\ : DFN1E0 - port map(D => \inst_2[23]\, CLK => lclk_c, E => holdn, Q - => \inst[23]\); - - \r.e.jmpl_RNI4I9RO1\ : NOR3C - port map(A => \aluresult_0_iv_6[27]\, B => - \logicout_m_0[27]\, C => \shiftin_17_m[28]\, Y => - \aluresult_0_iv_8[27]\); - - \r.d.pc_RNO[6]\ : MX2 - port map(A => \fpc[6]\, B => \dpc[6]\, S => N_6763_i_0, Y - => \pc_RNO[6]\); - - \r.x.ctrl.inst_RNIJD0E[21]\ : OR2 - port map(A => \inst_0[21]\, B => \inst[20]\, Y => y11_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I42_Y\ : MAJ3 - port map(A => \dpc[24]\, B => \inst_0_0_0_RNI9O79[21]\, C - => N421_2, Y => N459); - - \r.f.pc[16]\ : DFN1E0 - port map(D => \pc_1[16]\, CLK => lclk_c, E => holdn, Q => - \fpc[16]\); - - \r.e.op2_RNO_3[30]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[30]\, Y => - \aluresult_m_i[30]\); - - \r.m.icc_RNO_21[2]\ : NOR2 - port map(A => \logicout[7]\, B => \logicout[8]\, Y => - icc_0_sqmuxa_1_2); - - \r.m.y_RNIB4K91[5]\ : OR2B - port map(A => \y_2[5]\, B => aluresult_10_sqmuxa_0, Y => - \y_m_1[5]\); - - \r.m.y[24]\ : DFN1E0 - port map(D => \y_1[24]\, CLK => lclk_c, E => holdn, Q => - \y[24]\); - - \r.e.op2_RNIVFHN1[25]\ : OR2B - port map(A => \un1_iu0_5[91]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[25]\); - - \r.e.jmpl_RNILTD2M_0\ : OR2B - port map(A => \shiftin_17[6]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[6]\); - - \r.a.rsel1_RNIKM1954[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[16]\, Y - => \aluresult_m_0[16]\); - - \r.f.pc_RNO_6[18]\ : MX2 - port map(A => \fpc[18]\, B => \eaddress[18]\, S => jump_0, - Y => N_4061); - - \r.e.jmpl_RNIHBBLM\ : OR2B - port map(A => \shiftin_17[8]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[8]\); - - \r.x.data_0[9]\ : DFN1E0 - port map(D => \data_0_1[9]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[9]\); - - \r.m.ctrl.rd_RNIE9FK1[1]\ : NOR2B - port map(A => un1_de_ren1_1_1_i_0, B => un1_de_ren1_1_2_i_0, - Y => wreg_1_7); - - \r.f.pc_RNO[17]\ : OR3C - port map(A => \tmp_m[17]\, B => \pc_1_iv_1[17]\, C => - \un6_fe_npc_m[15]\, Y => \pc_1[17]\); - - \r.w.s.icc_RNO_1[2]\ : OR2B - port map(A => icc_0_sqmuxa, B => \icc_2[2]\, Y => - \icc_m_0[2]\); - - \r.d.inull_RNIOQ1F\ : AO1A - port map(A => N_85, B => \inull\, C => hold_pc_2_m, Y => - N_3014); - - un6_ex_add_res_d2_ADD_33x33_fast_I206_Y_0_o3_1 : OR2B - port map(A => ADD_33x33_fast_I206_Y_0_o3_1_0_1, B => N_57, - Y => N616_1); - - \r.w.result_RNIDHB4[6]\ : OR3C - port map(A => N_484_0, B => \rsel1[2]\, C => \result[6]\, Y - => \result_m_0_0[6]\); - - \r.e.ldbp2_RNIJJR273\ : OR3C - port map(A => \aluresult_1_iv_8[11]\, B => - \shiftin_17_m_0[11]\, C => \un6_ex_add_res_m[12]\, Y => - \aluresult[11]\); - - \r.e.jmpl_RNIBKNAF1\ : AOI1B - port map(A => \shiftin_17[14]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[13]\, Y => \aluresult_1_iv_7[13]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I58_Y : OA1A - port map(A => \data_0_0[18]\, B => \un1_iu0_6[18]\, C => - N449, Y => N517); - - \r.x.rstate_RNIOP1U_0[1]\ : OR2A - port map(A => rst, B => \xc_exception_1_0\, Y => - un2_rstn_5_0_i); - - \r.e.ctrl.trap_RNO_1\ : NOR3 - port map(A => trap_1, B => ticc, C => \tt_4[3]\, Y => - trap_4_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I264_Y_1 : AO1D - port map(A => N650, B => N635_1, C => - ADD_33x33_fast_I264_Y_0, Y => ADD_33x33_fast_I264_Y_1_1); - - \r.x.laddr[1]\ : DFN1E0 - port map(D => \maddress[1]\, CLK => lclk_c, E => holdn, Q - => \laddr[1]\); - - \r.w.result_RNI7O5J[23]\ : AOI1B - port map(A => \un1_p0_6[375]\, B => d14_0, C => - \result_m_0_0[23]\, Y => \d_iv_0[23]\); - - \r.m.y_RNO[8]\ : OR3C - port map(A => \y_iv_1[8]\, B => \y_iv_0[8]\, C => - \logicout_m[8]\, Y => \y_1[8]\); - - \r.m.y[26]\ : DFN1E0 - port map(D => \y_0[26]\, CLK => lclk_c, E => holdn, Q => - \y_1[26]\); - - \r.f.pc_RNO[28]\ : OR3C - port map(A => \tmp_m[28]\, B => \pc_1_iv_1[28]\, C => - \un6_fe_npc_m[26]\, Y => \pc_1[28]\); - - \r.x.rstate_0_RNI0CHE2[0]\ : MX2C - port map(A => N_3401, B => \xc_result[10]\, S => - \rstate_0[0]\, Y => \wdata[10]\); - - \r.m.y[4]\ : DFN1E0 - port map(D => \y_0[4]\, CLK => lclk_c, E => holdn, Q => - \y[4]\); - - \r.m.ctrl.trap_RNIMABN\ : NOR3A - port map(A => pv_1, B => trap_2, C => werr_1, Y => - trap_0_sqmuxa_7_1); - - un6_fe_npc_I_59 : AND3 - port map(A => \fe_pc[8]\, B => \fe_pc[9]\, C => \fe_pc[10]\, - Y => \DWACT_FINC_E[5]\); - - un54_ra_I_14 : XOR2 - port map(A => \ncwp[2]\, B => \DWACT_ADD_CI_0_g_array_1[0]\, - Y => I_14); - - \r.e.ldbp2_1_RNIEL6QV1\ : NAND2 - port map(A => \eaddress[8]\, B => un2_rstn_3_0, Y => - \un6_ex_add_res_m_1[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I4_G0N : OA1 - port map(A => \op1[3]\, B => ldbp1_4, C => \data_0[3]\, Y - => N406_1); - - \r.x.ctrl.pc_RNIVHN9[27]\ : MX2 - port map(A => \pc_3[27]\, B => \pc[27]\, S => \npc[1]\, Y - => N_3238); - - un6_ex_add_res_d2_ADD_33x33_fast_I132_Y : OR2B - port map(A => N533_1, B => N529_2, Y => N595); - - \r.a.ctrl.inst_RNI1D4C3[21]\ : NOR3 - port map(A => invop2_0_1_i_0, B => N_334, C => N_236, Y => - N_6680); - - \r.m.ctrl.pc[4]\ : DFN1E0 - port map(D => \pc[4]\, CLK => lclk_c, E => holdn, Q => - \pc_3[4]\); - - \r.m.y_RNO_3[28]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[28]\, C => \y_m[28]\, Y - => \y_iv_1[28]\); - - \r.m.result_RNO[22]\ : MX2 - port map(A => \aluresult[22]\, B => \op1[22]\, S => - un17_casaen_0_1, Y => \eres2[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I270_Y_0_o3 : AO1B - port map(A => N_71_1, B => N790_1, C => N514_2, Y => N786); - - \r.m.y_RNO_1[14]\ : AOI1B - port map(A => \y_0[14]\, B => y08_0, C => N_389, Y => - \y_iv_0_0[14]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I45_un1_Y : AND2 - port map(A => N466, B => N470, Y => I45_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I243_Y : OR2 - port map(A => N656_0, B => I243_un1_Y_0, Y => N796); - - \r.e.shleft_RNIEMRJ\ : OR2A - port map(A => \un1_iu0_6[16]\, B => shleft, Y => - \shiftin_5[16]\); - - \r.e.ldbp2_RNI3M6LS1\ : OR2B - port map(A => \aluresult_2_iv_7[1]\, B => - \aluresult_2_iv_6[1]\, Y => \aluresult[1]\); - - \r.e.op2_RNIQFHN1[16]\ : OR2B - port map(A => \un1_iu0_5[82]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I175_un1_Y : NOR2B - port map(A => N586, B => N579_0, Y => I175_un1_Y); - - \r.x.data_0_RNI8F9E[12]\ : XOR2 - port map(A => \data_0_2[12]\, B => invop2_0, Y => N_4259); - - \r.d.annul_RNIP2H4\ : NOR2 - port map(A => annul_1, B => call_hold5, Y => - hold_pc_1_sqmuxa); - - \r.a.rsel2_0_RNIVADN[0]\ : NOR2B - port map(A => \result_m_i[3]\, B => \cpi_m_i[355]\, Y => - \d_1_iv_1[3]\); - - \r.e.op1_RNIQ69G[15]\ : OR2B - port map(A => \op1[15]\, B => un14_casaen_s1_0, Y => - \op1_m_0[15]\); - - \r.e.op1_RNI2RNF[16]\ : NOR2A - port map(A => un17_casaen_0_1, B => \op1[16]\, Y => - \op1_i_m[16]\); - - \r.d.inull_RNI7S342\ : NOR2A - port map(A => annul_next_2_sqmuxa_1_2, B => N_108, Y => - annul_next_2_sqmuxa_1_3); - - \r.e.op1_RNIPA4U1[7]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[7]\, C => - \ex_op1_i_m[7]\, Y => \edata2_0_iv_0[7]\); - - \r.m.ctrl.pc_RNIL9GF[10]\ : MX2 - port map(A => \pc_2[10]\, B => \pc_3[10]\, S => \npc_0[1]\, - Y => N_3251); - - \r.m.ctrl.inst[29]\ : DFN1E0 - port map(D => \inst_2[29]\, CLK => lclk_c, E => holdn, Q - => \inst_3[29]\); - - \r.e.op1_RNIBHFC[7]\ : OR2B - port map(A => \op1[7]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[7]\); - - \r.w.result[29]\ : DFN1E0 - port map(D => \wdata[29]\, CLK => lclk_c, E => holdn, Q => - \result[29]\); - - \r.x.data_0_RNO_0[6]\ : AO1B - port map(A => rdatav_0_1_0_iv_5_4, B => mcdo_m_0_20, C => - N_3455, Y => \dco_m_i[118]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I2_G0N : NOR3A - port map(A => \op1[1]\, B => ldbp1, C => \data_0[1]\, Y => - N400_2); - - \r.m.y_RNO_3[7]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[7]\, C => \y_m_1[7]\, Y - => \y_iv_1[7]\); - - \r.e.shcnt_RNI2B1C[0]\ : MX2C - port map(A => \shcnt[0]\, B => N_3304, S => ldbp2_3, Y => - \ex_shcnt_1[0]\); - - \r.e.ctrl.pc[19]\ : DFN1E0 - port map(D => \pc_3[19]\, CLK => lclk_c, E => holdn, Q => - \pc[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I29_P0N : OR2 - port map(A => \un1_iu0_6[28]\, B => \op2[28]\, Y => N482_0); - - \r.e.op1_RNIJB1JB[11]\ : NOR3 - port map(A => \edata2_0_iv_0[11]\, B => \bpdata_i_m[11]\, C - => \bpdata_i_m_2[3]\, Y => edata2_0_iv(11)); - - \r.m.y_RNIV8FM7[8]\ : AND2 - port map(A => \bpdata_m_2[0]\, B => \aluresult_1_iv_3[8]\, - Y => \aluresult_1_iv_5[8]\); - - \r.m.y_RNIID7CA[17]\ : NOR3C - port map(A => \aluresult_1_iv_1[17]\, B => - \aluresult_1_iv_0[17]\, C => \aluresult_1_iv_3[17]\, Y - => \aluresult_1_iv_4[17]\); - - un6_fe_npc_I_56 : XOR2 - port map(A => N_113, B => \fe_pc[12]\, Y => I_56); - - \r.a.rsel2_RNI9LB_0[1]\ : NOR2A - port map(A => \rsel2[1]\, B => \rsel2[2]\, Y => d28_0); - - \r.e.op2[15]\ : DFN1E0 - port map(D => N_299, CLK => lclk_c, E => holdn, Q => - \op2[15]\); - - \r.x.ctrl.pc_RNIPIIF[29]\ : MX2 - port map(A => \pc_2[29]\, B => \pc_0[29]\, S => \npc_1[1]\, - Y => N_3240); - - \comb.branch_address.tmp_ADD_30x30_fast_I217_Y\ : AO1 - port map(A => N610, B => N595_0, C => N594, Y => N723); - - \r.a.rsel2_1[0]\ : DFN1E0 - port map(D => N_3944, CLK => lclk_c, E => holdn, Q => - \rsel2_1[0]\); - - \r.m.y[22]\ : DFN1E0 - port map(D => \y_1[22]\, CLK => lclk_c, E => holdn, Q => - \y[22]\); - - \r.e.aluop_0_RNID9JD1[2]\ : XA1 - port map(A => \un1_iu0_5[92]\, B => \aluop_0[2]\, C => - \un1_iu0_6[26]\, Y => N_3553); - - \r.m.result_RNO[9]\ : MX2 - port map(A => \aluresult[9]\, B => \op1[9]\, S => - un17_casaen_0_1, Y => \eres2[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I204_un1_Y : NOR2B - port map(A => N616_1, B => N609, Y => I204_un1_Y_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I3_G0N : NOR2B - port map(A => \un1_iu0_6[2]\, B => \op2[2]\, Y => N403_1); - - \r.m.y_RNI0BC92[12]\ : AOI1B - port map(A => \y[12]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[157]\, Y => \aluresult_1_iv_1[12]\); - - \r.m.result[29]\ : DFN1E0 - port map(D => \eres2[29]\, CLK => lclk_c, E => holdn, Q => - \maddress[29]\); - - \r.w.s.tba_RNI1E424[12]\ : AND2 - port map(A => \aluresult_1_iv_1[24]\, B => \tba_m[12]\, Y - => \aluresult_1_iv_3[24]\); - - \r.e.shcnt_RNIKP4RT[1]\ : MX2B - port map(A => \shiftin_14[31]\, B => \shiftin_14[29]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[29]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I294_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[4]\, B => N614_2, Y => - \un6_ex_add_res_s2[4]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I5_P0N : OR2 - port map(A => \un1_iu0_6[4]\, B => \op2[4]\, Y => N410_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I16_G0N : NOR3A - port map(A => \op1[15]\, B => ldbp1_3, C => \data_0_2[15]\, - Y => N442); - - \r.a.rfa2[1]\ : DFN1E0 - port map(D => \inst_0_RNI1JUM[1]\, CLK => lclk_c, E => - holdn, Q => \rfa2[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I135_Y : AO1 - port map(A => N536_2, B => N533_1, C => N532_1, Y => N598_2); - - \r.a.ctrl.pc[31]\ : DFN1E0 - port map(D => \dpc[31]\, CLK => lclk_c, E => holdn, Q => - \pc_0[31]\); - - \r.x.result_RNIJK6E[20]\ : MX2 - port map(A => \result[20]\, B => \data_0_2[20]\, S => ld_4, - Y => \un1_p0_6[372]\); - - \r.e.aluop_RNIRJNA4[2]\ : OR2B - port map(A => \bpdata[9]\, B => aluresult_5_sqmuxa, Y => - \bpdata_m_0[9]\); - - \r.d.inst_0_RNI7DOH[29]\ : MX2C - port map(A => \inst_0[18]\, B => \inst_0[29]\, S => rs1mod, - Y => \rs1[4]\); - - \r.e.shleft_0_RNI15IP\ : OR2A - port map(A => \un1_iu0_6[17]\, B => shleft_0, Y => - \shiftin_5[17]\); - - \r.e.op2_RNO[3]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[3]\, Y => N_287); - - \r.e.ldbp2_RNIOFQ534\ : MX2C - port map(A => \un6_ex_add_res_s1_i[26]\, B => N_6657, S => - ldbp2_3, Y => \eaddress[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I182_Y_0_o3\ : AOI1 - port map(A => N610, B => N380, C => N379, Y => N608_i); - - \r.e.op1_RNILI8G[10]\ : OR2B - port map(A => \op1[10]\, B => un14_casaen_s1_0, Y => - \op1_m_0[10]\); - - \r.a.bp_RNO_0\ : OR2A - port map(A => not_valid, B => \un9_icc_check_bp\, Y => - bp_1_0); - - \r.d.cwp_RNO_1[2]\ : MX2 - port map(A => \cwp_0[2]\, B => \maddress[2]\, S => wcwp, Y - => N_4220); - - \r.m.y[14]\ : DFN1E0 - port map(D => \y_1[14]\, CLK => lclk_c, E => holdn, Q => - \y_0[14]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I269_Y_0 : AOI1B - port map(A => N660_0, B => N645_1, C => N644, Y => - ADD_33x33_fast_I269_Y_0_1); - - \r.e.op2_RNO_0[26]\ : OR3C - port map(A => \op1_m_i[26]\, B => \d_1_iv_3[26]\, C => - \aluresult_m_i[26]\, Y => \d_1[26]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I63_Y\ : OA1 - port map(A => \dpc[14]\, B => \inst_0[12]\, C => N392, Y - => N480); - - \r.m.ctrl.inst[21]\ : DFN1E0 - port map(D => \inst_1[21]\, CLK => lclk_c, E => holdn, Q - => \inst[21]\); - - \r.e.op2_RNI3OHN1[27]\ : OR2B - port map(A => \un1_iu0_5[93]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I265_Y_0_0\ : XOR2 - port map(A => \dpc[7]\, B => \inst_0[5]\, Y => - ADD_30x30_fast_I265_Y_0_0); - - \r.e.ctrl.pc_RNI1T8Q2[26]\ : AOI1 - port map(A => \pc[26]\, B => jmpl_0, C => \aluresult_4[1]\, - Y => \aluresult_1_iv_1[26]\); - - \r.a.imm_RNO[0]\ : NOR2B - port map(A => \inst_0_RNI0FUM[0]\, B => call_hold5, Y => - \un3_de_ren1[118]\); - - \r.w.s.icc_RNO[2]\ : AO1B - port map(A => icc_1_sqmuxa, B => \icc[2]\, C => - \icc_1_iv_0[2]\, Y => \icc_1[2]\); - - \r.a.imm[5]\ : DFN1E0 - port map(D => \un3_de_ren1[123]\, CLK => lclk_c, E => holdn, - Q => \imm[5]\); - - \r.w.result_RNIQJD4[28]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[28]\, - Y => \result_m_0[28]\); - - \r.m.y_RNO_4[19]\ : OR2B - port map(A => \y_0[20]\, B => mulstep_1, Y => \y_m_0[20]\); - - \r.e.op2_RNO_4[23]\ : OR2B - port map(A => \op1[23]\, B => un14_casaen_s1, Y => - \op1_m_i[23]\); - - \r.d.inst_0_RNI4VUM[4]\ : NOR2B - port map(A => \inst_0[4]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI4VUM[4]\); - - \r.m.y[16]\ : DFN1E0 - port map(D => \y_1[16]\, CLK => lclk_c, E => holdn, Q => - \y[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I58_Y\ : MAJ3 - port map(A => \dpc[16]\, B => \inst_0[14]\, C => N397_2, Y - => N475); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y_2 : AOI1B - port map(A => N568_0, B => N561, C => - ADD_33x33_fast_I260_Y_1, Y => ADD_33x33_fast_I260_Y_2); - - \r.f.pc_RNO_7[19]\ : MX2 - port map(A => \fpc[19]\, B => \tba[7]\, S => rstate_6314_d, - Y => \xc_trap_address[19]\); - - \r.a.ctrl.inst_RNIG5R8[7]\ : NOR2 - port map(A => \inst[7]\, B => \inst[9]\, Y => un29_casaen_3); - - \r.x.rstate_RNIRDFU5[1]\ : AOI1 - port map(A => rstate_4_2, B => rstate_6314_d_0, C => - et_RNI1BRF2, Y => \rstate_RNIRDFU5[1]\); - - \r.a.rsel1_RNIUKSMO6[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[25]\, Y - => \aluresult_m_0[25]\); - - \r.e.op2_RNI5SHN1[28]\ : OR2B - port map(A => \un1_iu0_5[94]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[28]\); - - \r.e.aluop_0_RNINA1T2[1]\ : MX2C - port map(A => \logicout_4[15]\, B => N_6883, S => - N_6866_i_0, Y => N_3638); - - \r.f.pc_RNI6QK32[10]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[10]\, Y => \xc_trap_address_m[10]\); - - \r.x.result_RNI52D25[4]\ : NOR2 - port map(A => \bpdata[4]\, B => N_3703_i, Y => - \bpdata_i_m_1[4]\); - - \r.x.ctrl.wicc_RNIVOQU_0\ : NOR2A - port map(A => icc_0_sqmuxa_1, B => \rstate_d[2]\, Y => - icc_0_sqmuxa); - - \r.x.ctrl.tt_RNO_0[2]\ : MX2C - port map(A => irl_0(2), B => \tt_2[2]\, S => tt_0_sqmuxa, Y - => N_4206); - - \r.m.ctrl.pc[29]\ : DFN1E0 - port map(D => \pc_0[29]\, CLK => lclk_c, E => holdn, Q => - \pc_3[29]\); - - \r.a.ctrl.inst_RNI9T2M3[25]\ : MX2C - port map(A => N_3341, B => N_3344, S => \inst_1[25]\, Y => - branch); - - \r.x.ctrl.inst_RNI2JBD2_0[30]\ : OR2B - port map(A => xc_wreg_0_sqmuxa, B => cwp_1_sqmuxa, Y => - cwp_1_sqmuxa_0); - - \r.e.jmpl_RNITN6O\ : NOR3A - port map(A => \ex_shcnt_1[0]\, B => jmpl, C => - aluresult_1_sqmuxa_0_0, Y => aluresult_2_sqmuxa); - - \r.x.result_RNITK5F5[15]\ : NOR2A - port map(A => \aluop_RNIGM3N1[2]\, B => \bpdata[15]\, Y => - \bpdata_i_m[15]\); - - \r.e.op1_RNO[15]\ : MX2C - port map(A => \d_i[15]\, B => \d_i[16]\, S => N_227_0, Y - => \aop1[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I159_un1_Y : OR2B - port map(A => N570_1, B => N563, Y => I159_un1_Y_0); - - \comb.irq_trap.op_gt.un2_irl_0_I_9\ : OR2A - port map(A => \pil[3]\, B => irl_0(3), Y => \ACT_LT4_E[8]\); - - \r.e.aluop_RNI50KR2[1]\ : MX2C - port map(A => N_3550, B => \logicout_3[23]\, S => - \aluop_3[1]\, Y => N_3582); - - \r.d.inst_0_RNO[16]\ : NOR2B - port map(A => rst, B => N_4616, Y => \inst_0_RNO[16]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I189_Y : AO1 - port map(A => N600_0, B => N593_1, C => N592_1, Y => N658); - - \r.m.ctrl.rett_RNITNQB\ : OR2 - port map(A => rett, B => rett_0, Y => rett_1_0); - - \r.e.op2_RNO_5[30]\ : AOI1B - port map(A => \result[30]\, B => d31_0, C => \imm_m_i[30]\, - Y => \d_1_iv_0[30]\); - - \r.d.annul_RNI0LULC\ : OR2 - port map(A => annul_1, B => inhibit_current, Y => - ctrl_annul_i_0_a2_0); - - \r.e.aluop_0_RNIDA0T2[1]\ : MX2C - port map(A => \logicout_4[22]\, B => N_6862, S => - N_6866_i_0, Y => N_3645); - - \comb.branch_address.tmp_ADD_30x30_fast_I281_Y_0_0\ : XOR2 - port map(A => \dpc[23]\, B => \un1_p0_6_0[60]\, Y => - ADD_30x30_fast_I281_Y_0_0); - - \r.f.pc_RNO_5[15]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[15]\, Y => \xc_trap_address_m[15]\); - - \r.x.ctrl.tt_RNO_0[0]\ : NOR2B - port map(A => tt_2_sqmuxa_1, B => trap_0_sqmuxa_7, Y => - N_4200_i_0); - - \r.m.y_RNO_2[3]\ : OR2B - port map(A => \y_1[3]\, B => y08, Y => \y_m_0[3]\); - - \r.a.nobp_RNIP6STQ\ : AO1A - port map(A => \ldlock_3_0\, B => \un9_icc_check_bp\, C => - \ldlock_2\, Y => ldlock); - - \r.e.op1[0]\ : DFN1E0 - port map(D => \aop1[0]\, CLK => lclk_c, E => holdn, Q => - \op1[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I211_un1_Y : OR2B - port map(A => N640_1, B => N625_0, Y => I211_un1_Y_0); - - \comb.op_mux.d_1_iv_RNO_4[29]\ : AOI1B - port map(A => \result[29]\, B => d31_0, C => \imm_m_i[29]\, - Y => \d_1_iv_0[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I242_Y_0\ : AND2 - port map(A => I242_un1_Y, B => N586_i, Y => - ADD_30x30_fast_I242_Y_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I221_Y\ : OR3 - port map(A => I176_un1_Y, B => N542, C => I221_un1_Y_0, Y - => N735); - - \r.e.jmpl_RNI772QP1\ : AOI1B - port map(A => \shiftin_17[31]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[30]\, Y => \aluresult_1_iv_8[30]\); - - \r.m.dci.asi[4]\ : DFN1E0 - port map(D => \asi[4]\, CLK => lclk_c, E => holdn, Q => - asi_0(4)); - - \r.w.s.y_RNO[21]\ : MX2 - port map(A => \y_1[21]\, B => \result_0[21]\, S => N_481, Y - => N_3785); - - \r.e.shcnt_RNIE5275[3]\ : MX2 - port map(A => \shiftin_8[20]\, B => \shiftin_8[12]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[12]\); - - \r.a.ctrl.inst[26]\ : DFN1E0 - port map(D => \inst_0[26]\, CLK => lclk_c, E => holdn, Q - => \inst_2[26]\); - - \r.e.ctrl.inst_RNI2P2L[14]\ : OR3B - port map(A => \inst[18]\, B => \inst[14]\, C => \inst[17]\, - Y => miscout69); - - \r.e.aluop_RNI6QSC4[2]\ : OR2A - port map(A => edata_1_sqmuxa, B => \bpdata[8]\, Y => - \aluop_RNI6QSC4[2]\); - - \r.m.y_RNO_1[4]\ : OR3A - port map(A => \y_1[4]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[4]\); - - \r.e.ctrl.inst_RNIFC0E_0[30]\ : NOR2A - port map(A => \inst_2[31]\, B => \inst_2[30]\, Y => - un3_notag); - - \comb.branch_address.tmp_ADD_30x30_fast_I168_Y\ : OR2A - port map(A => I168_un1_Y_i, B => N534, Y => N594); - - \un1_r.w.s.cwp_1_CO1_0_tz\ : AO1A - port map(A => \rstate_RNIRDFU5[1]\, B => \cwp[0]\, C => - \cwp_0[1]\, Y => CO1_0_tz); - - \r.d.pc_RNO[22]\ : MX2 - port map(A => \fpc[22]\, B => \dpc[22]\, S => N_6763_i, Y - => \pc_RNO[22]\); - - \r.x.data_0_RNO_0[29]\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_20, B => mcdo_m_0_27, C => - rdata_6_sqmuxa, Y => \dco_m_1[125]\); - - \r.e.op1_RNIMOCQB[13]\ : NOR2 - port map(A => \edata2_0_iv_1[13]\, B => \bpdata_i_m_2[5]\, - Y => edata2_0_iv(13)); - - \r.d.inst_0_RNIR8HPD2[31]\ : OR2 - port map(A => un1_inst, B => ctrl_annul_i, Y => N_143); - - \r.e.op2_RNINE992[10]\ : AOI1B - port map(A => \un1_iu0_5[76]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[10]\); - - \r.e.op2_RNO_6[26]\ : OR2B - port map(A => data2(26), B => d25, Y => \rfo_m_i[58]\); - - \r.d.inst_0_RNI42J4_0[21]\ : OR2A - port map(A => \inst_0_0[21]\, B => N_67, Y => un8_op3); - - \r.m.y_RNO_2[1]\ : OR2A - port map(A => \logicout[1]\, B => y14, Y => N_377); - - \r.m.result_0[3]\ : DFN1E0 - port map(D => \eres2[3]\, CLK => lclk_c, E => holdn, Q => - \maddress_0[3]\); - - \r.e.op2_RNI0OMB1[14]\ : OR2A - port map(A => \un1_iu0_5[80]\, B => \un1_iu0_6[14]\, Y => - \logicout_4[14]\); - - \comb.misc_op.un1_r.x.ctrl.rd_0_0_RNIQ42F\ : AND2 - port map(A => rd_0_i_0, B => bpdata6_0, Y => bpdata6_1); - - \r.m.y[12]\ : DFN1E0 - port map(D => \y_1[12]\, CLK => lclk_c, E => holdn, Q => - \y[12]\); - - \r.e.ctrl.inst[18]\ : DFN1E0 - port map(D => \inst_1[18]\, CLK => lclk_c, E => holdn, Q - => \inst[18]\); - - \r.e.aluop_1_RNIC4591[1]\ : XOR3 - port map(A => \un1_iu0_6[11]\, B => \aluop_1[1]\, C => - \un1_iu0_5[77]\, Y => N_6910); - - \r.a.rsel2_0_RNI1Q8FP1[0]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[0]\, Y - => \aluresult_m_i[0]\); - - \r.e.jmpl_RNI9VDQM2\ : AOI1B - port map(A => \shiftin_17[27]\, B => aluresult_2_sqmuxa_0, - C => \aluresult_0_iv_8[27]\, Y => \aluresult_0_iv_9[27]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I269_Y_0 : AOI1 - port map(A => N660_1, B => N645_0, C => N644_0, Y => - ADD_33x33_fast_I269_Y_0_0); - - \r.e.su_RNISBJ4J\ : AOI1B - port map(A => \bpdata[7]\, B => N_3957, C => - \aluresult_1_iv_6[7]\, Y => \aluresult_1_iv_7[7]\); - - \r.a.imm[6]\ : DFN1E0 - port map(D => \un3_de_ren1[124]\, CLK => lclk_c, E => holdn, - Q => \imm[6]\); - - \r.x.data_0_RNIFF9E[18]\ : XOR2 - port map(A => \data_0_0[18]\, B => invop2_1, Y => N_4265); - - \r.m.y_RNO_5[31]\ : MX2 - port map(A => ymsb, B => \data_0[0]\, S => ldbp2_1, Y => - ex_ymsb_1); - - \r.d.inst_0_RNIBIL7[23]\ : OR2 - port map(A => un3_op2, B => call_hold5_0, Y => N_128); - - \comb.fpstdata.edata2_0_iv_RNO_0[2]\ : AND2 - port map(A => \ex_op1_i_m[2]\, B => \op1_i_m[2]\, Y => - \edata2_0_iv_0[2]\); - - \r.a.ctrl.cnt[1]\ : DFN1E0 - port map(D => \cnt_0[1]\, CLK => lclk_c, E => holdn, Q => - \cnt_2[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I302_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[11]\, B => \data_0_2[11]\, Y => - \un6_ex_add_res_s2_1[12]\); - - \r.e.ctrl.annul_RNI5L7FE1\ : NOR3 - port map(A => un2_rstn_5_0_i, B => un12_de_hold_pc, C => - \de_hold_pc_1\, Y => annul_RNI5L7FE1); - - \r.e.aluop_1_RNIATP71[1]\ : XNOR3 - port map(A => \un1_iu0_6[23]\, B => \aluop_1[1]\, C => - \un1_iu0_5[89]\, Y => N_6880_i); - - \r.m.y_RNO_0[15]\ : NOR3C - port map(A => \y_m[15]\, B => \y_m_0[15]\, C => - \y_iv_0[15]\, Y => \y_iv_2[15]\); - - \r.e.jmpl_RNIG24IP\ : OR2B - port map(A => \shiftin_17[16]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[16]\); - - \r.x.ctrl.tt_RNI7LVQ[1]\ : MX2 - port map(A => \result_0[1]\, B => \tt[1]\, S => tt_i, Y => - N_3320); - - \r.e.op2_RNI5VOP[19]\ : MX2 - port map(A => \op2[19]\, B => N_4266, S => ldbp2_0, Y => - \un1_iu0_5[85]\); - - \r.e.aluop_RNI8KJJ1[2]\ : XA1 - port map(A => \un1_iu0_5[93]\, B => \aluop_1[2]\, C => - \un1_iu0_6[27]\, Y => N_3554); - - \r.x.result[10]\ : DFN1E0 - port map(D => \maddress[10]\, CLK => lclk_c, E => holdn, Q - => \result[10]\); - - \r.x.intack_RNO_1\ : NOR2A - port map(A => \tt[4]\, B => \tt[5]\, Y => intack_0); - - \r.m.y_RNI2BC92[22]\ : AOI1B - port map(A => \y[22]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[167]\, Y => \aluresult_1_iv_1[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I103_Y : OR2 - port map(A => N500_0, B => I103_un1_Y, Y => N566); - - \r.x.ctrl.pc[6]\ : DFN1E0 - port map(D => \pc_2[6]\, CLK => lclk_c, E => holdn, Q => - \pc_1[6]\); - - \r.x.ctrl.inst_RNIH32S[22]\ : NOR3B - port map(A => \inst_1[19]\, B => y15, C => \inst_0[22]\, Y - => tba_610_e_3); - - \r.m.ctrl.rd_RNIPC1L[2]\ : XNOR2 - port map(A => \rd_0[2]\, B => \un3_de_ren1[93]\, Y => - un2_rs1_2_2_i_0); - - \r.e.shleft_RNI49931\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[8]\, S => shleft, - Y => \shiftin_5[39]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_a3_1_0 : AND2 - port map(A => N398, B => alucin, Y => - ADD_33x33_fast_I206_Y_0_a3_1_0); - - \r.x.rstate[0]\ : DFN1 - port map(D => N_6322s, CLK => lclk_c, Q => \rstate[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I211_un1_Y : OR2B - port map(A => N640_0, B => N625_1, Y => I211_un1_Y); - - \r.x.y[5]\ : DFN1E0 - port map(D => \y_2[5]\, CLK => lclk_c, E => holdn, Q => - \y_1[5]\); - - \r.d.pv_RNIEN8IS\ : NOR3C - port map(A => un1_annul_next_1_sqmuxa_3_0, B => - un23_exbpmiss_i_0, C => un9_rabpmiss, Y => - un1_annul_next_1_sqmuxa_3_2); - - un6_fe_npc_I_121 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \fe_pc[20]\, Y => N_66); - - \r.e.op2[27]\ : DFN1E0 - port map(D => N_311, CLK => lclk_c, E => holdn, Q => - \op2[27]\); - - \r.a.rsel1_0_RNIOO7M2[2]\ : OR2B - port map(A => data1(0), B => d11, Y => \rfo_m[0]\); - - \r.e.op2_RNI6BA92[17]\ : AOI1B - port map(A => \un1_iu0_5[83]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[17]\); - - \comb.cwp_ctrl.ncwp_3_I_10\ : XNOR2 - port map(A => \inst_0[19]\, B => \cwp[1]\, Y => - \DWACT_ADD_CI_0_partial_sum[1]\); - - \r.w.s.tba[12]\ : DFN1E1 - port map(D => \result_0[24]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[12]\); - - \r.x.mexc_RNICKPT\ : OR2A - port map(A => N_3320, B => mexc_0, Y => \xc_vectt_1[1]\); - - \r.m.result_RNO[25]\ : MX2 - port map(A => \aluresult[25]\, B => \op1[25]\, S => - un17_casaen_0_1, Y => \eres2[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I76_Y : OA1 - port map(A => \data_0[8]\, B => \un1_iu0_6[8]\, C => N425_2, - Y => N535_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I107_Y : AO1 - port map(A => N508, B => N505, C => N504, Y => N570_0); - - \r.m.ctrl.inst_RNIHADL4[21]\ : OR3C - port map(A => iflush_1_0, B => iflush_1, C => iflush_4, Y - => flush_i_0); - - \r.f.branch_RNI6I584\ : NOR2 - port map(A => \fbranch\, B => jump_0, Y => d_m5_0_a3_0); - - \r.x.data_0[19]\ : DFN1E0 - port map(D => \data_0_1[19]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[19]\); - - \r.x.ctrl.pc_RNIHPL9[20]\ : MX2 - port map(A => \pc_2[20]\, B => \pc_0[20]\, S => \npc[1]\, Y - => N_3231); - - \r.e.op1_RNO[12]\ : MX2C - port map(A => \d_i[12]\, B => \d_i[13]\, S => N_227, Y => - \aop1[12]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I243_Y : AO1 - port map(A => N672_1, B => N657_1, C => N656_1, Y => N796_1); - - \r.m.result[3]\ : DFN1E0 - port map(D => \eres2[3]\, CLK => lclk_c, E => holdn, Q => - \maddress[3]\); - - \r.e.cwp_RNIF0258[1]\ : NOR3C - port map(A => \cwp_m[1]\, B => \aluresult_2_iv_0[1]\, C => - \aluresult_2_iv_1[1]\, Y => \aluresult_2_iv_3[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I263_Y_1 : AOI1B - port map(A => N648, B => N633, C => ADD_33x33_fast_I263_Y_0, - Y => ADD_33x33_fast_I263_Y_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I187_Y : AO1 - port map(A => N598_2, B => N591_1, C => N590_1, Y => N656); - - \r.m.ctrl.rd_RNIHKQS1[3]\ : XA1A - port map(A => \un3_de_ren1[94]\, B => \rd_0[3]\, C => - un2_rs1_2_6_i_0, Y => wreg_1_3); - - \r.e.ctrl.cnt_RNILO7A_1[0]\ : NOR3 - port map(A => \cnt[0]\, B => \cnt[1]\, C => annul, Y => - read_1_sqmuxa_0); - - \r.m.y_RNIO1O71[11]\ : OR2B - port map(A => \y_0[11]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[11]\); - - \r.m.result_RNO[17]\ : MX2 - port map(A => \aluresult[17]\, B => \op1[17]\, S => - un17_casaen_0_2, Y => \eres2[17]\); - - \r.a.ctrl.inst_RNIIUL69[13]\ : OR3B - port map(A => \inst[13]\, B => un1_illegal_inst34, C => - N_212, Y => \cpi_m[121]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I6_G0N : OAI1 - port map(A => \op1[5]\, B => ldbp1_3, C => \data_0[5]\, Y - => N412_2); - - \r.x.result_RNIMMED[12]\ : MX2 - port map(A => \result[12]\, B => \data_0_2[12]\, S => ld_0, - Y => \un1_p0_6[364]\); - - \r.d.inst_0_0_0_RNI7TVIO2[12]\ : NOR2B - port map(A => rst, B => N_4612, Y => - \inst_0_0_0_RNI7TVIO2[12]\); - - \r.m.ctrl.pc[7]\ : DFN1E0 - port map(D => \pc_0[7]\, CLK => lclk_c, E => holdn, Q => - \pc_2[7]\); - - \r.w.s.y_RNO[13]\ : MX2 - port map(A => \y_2[13]\, B => \result_0[13]\, S => N_481_0, - Y => N_3777); - - \r.d.pc_RNO[9]\ : MX2 - port map(A => \fpc[9]\, B => \dpc[9]\, S => N_6763_i_0, Y - => \pc_RNO[9]\); - - \r.m.y_RNO_1[27]\ : AOI1B - port map(A => \y_0[27]\, B => y08_0, C => N_424, Y => - \y_iv_0_0[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I169_Y\ : NOR3B - port map(A => N476_0, B => N480, C => N543, Y => N595_0); - - \r.x.data_0[0]\ : DFN1E0 - port map(D => \data_0_1[0]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[0]\); - - \r.m.y_RNI2JC92[13]\ : AOI1B - port map(A => \y[13]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[158]\, Y => \aluresult_1_iv_1[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I15_G0N : NOR2B - port map(A => \op2[14]\, B => \un1_iu0_6[14]\, Y => N439); - - \r.e.aluop_RNIILSC4[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[27]\, Y => - \bpdata_i_m[27]\); - - \r.e.op2_RNIDPC6[4]\ : MX2 - port map(A => \op2[4]\, B => N_3308, S => ldbp2_3, Y => - \un1_iu0_5[70]\); - - \r.a.ctrl.pc[20]\ : DFN1E0 - port map(D => \dpc[20]\, CLK => lclk_c, E => holdn, Q => - \pc[20]\); - - \r.m.dci.asi_RNO[2]\ : NOR2B - port map(A => \inst_0[23]\, B => \inst_1[7]\, Y => \asi[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I311_Y_0 : XOR2 - port map(A => ADD_33x33_fast_I311_Y_0_0, B => N786_i, Y => - \un6_ex_add_res_s1_i[21]\); - - \r.m.ctrl.pc_RNIGPN9[18]\ : MX2 - port map(A => \pc_3[18]\, B => \pc[18]\, S => \npc[1]\, Y - => N_3259); - - \r.e.ctrl.pc_RNINR011[3]\ : OR2B - port map(A => \pc_0[3]\, B => jmpl_4, Y => \cpi_m[148]\); - - \r.a.ctrl.wy\ : DFN1E0 - port map(D => wy_1_1, CLK => lclk_c, E => holdn, Q => wy); - - \r.x.rstate_0_RNIVGIE2[0]\ : MX2C - port map(A => N_3422, B => \xc_result[31]\, S => - \rstate_0[0]\, Y => \wdata[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I315_Y_0 : XNOR3 - port map(A => \un1_iu0_6[24]\, B => \op2[24]\, C => N778_1, - Y => \un6_ex_add_res_s1_i[25]\); - - \r.x.rstate_RNIK02D2[0]\ : MX2C - port map(A => N_3412, B => \xc_result[21]\, S => - \rstate[0]\, Y => \wdata[21]\); - - \r.w.s.pil_RNI59PJ3[3]\ : OA1A - port map(A => \pil[3]\, B => aluresult_11_sqmuxa, C => - \aluresult_1_iv_0[11]\, Y => \aluresult_1_iv_2[11]\); - - \r.d.pc[17]\ : DFN1 - port map(D => \pc_RNO[17]\, CLK => lclk_c, Q => \dpc[17]\); - - \r.a.rsel1_0_RNIG7LJ2[2]\ : OR2B - port map(A => data1(26), B => d11_0, Y => \rfo_m[26]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I277_Y_0\ : XNOR2 - port map(A => N718_i, B => ADD_30x30_fast_I277_Y_0_0, Y => - \tmp[19]\); - - \r.e.aluop_0[2]\ : DFN1E0 - port map(D => \aluop[2]\, CLK => lclk_c, E => holdn, Q => - \aluop_0[2]\); - - \r.e.ctrl.wy_0\ : DFN1E0 - port map(D => wy, CLK => lclk_c, E => holdn, Q => wy_0); - - \r.d.inst_0_RNI3846[21]\ : OR2B - port map(A => un14_op_2, B => icc_check9_2, Y => icc_check9); - - \r.d.annul_RNIMSEMD2\ : OR2 - port map(A => ctrl_annul_i_0_a2_0, B => annul_current, Y - => ctrl_annul_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I68_Y : OA1B - port map(A => \data_0_2[12]\, B => \un1_iu0_6[12]\, C => - N437_2, Y => N527_1); - - \r.m.y_RNO_4[16]\ : OR2B - port map(A => \y[17]\, B => mulstep_0, Y => \y_m_1[17]\); - - \r.e.op2_RNO_2[13]\ : AOI1B - port map(A => data2(13), B => d25_0, C => \d_1_iv_2[13]\, Y - => \d_1_iv_3[13]\); - - \r.e.op2_RNI7C9P_0[1]\ : OR2 - port map(A => \un1_iu0_6[1]\, B => \op2_RNI1LHG[1]\, Y => - \logicout_3[1]\); - - \r.d.inst_0_RNIJCK6[27]\ : AX1C - port map(A => N_375, B => \inst_0[27]\, C => \inst_0[28]\, - Y => N_3346); - - \comb.ld_align.rdata199_RNI4ADG12\ : AO1C - port map(A => rdata_1_sqmuxa_1, B => ld_3, C => - rdata_5_sqmuxa, Y => N_3455); - - \r.x.y[13]\ : DFN1E0 - port map(D => \y[13]\, CLK => lclk_c, E => holdn, Q => - \y_2[13]\); - - \r.a.ctrl.rd_RNISJI31[5]\ : XNOR2 - port map(A => \rd_1[5]\, B => \un3_de_ren1[96]\, Y => - un2_rs1_5_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I104_Y : OR2A - port map(A => N505, B => N501, Y => N567_2); - - \r.m.y_RNO_3[3]\ : AOI1B - port map(A => wy_1_0, B => \y[3]\, C => \y_m[3]\, Y => - \y_iv_1[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I236_Y\ : AOI1 - port map(A => ADD_30x30_fast_I236_un1_Y_0, B => N741, C => - ADD_30x30_fast_I236_Y_1, Y => N702_i); - - \r.x.result_RNIB5R65[4]\ : OR2B - port map(A => \bpdata[4]\, B => N_3957_1, Y => - \bpdata_m_1[4]\); - - \r.e.aluop_RNIK0RF4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[31]\, Y => - \aluop_RNIK0RF4[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I11_G0N : NOR3A - port map(A => \op1[10]\, B => ldbp1_2, C => \data_0[10]\, Y - => N427_0); - - \r.e.op2_RNO_9[23]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[375]\, - Y => \cpi_m_i[375]\); - - \r.e.aluop_0_RNIN8IG3[0]\ : MX2C - port map(A => N_3566, B => N_3630, S => \aluop_0[0]\, Y => - \logicout[7]\); - - \r.e.ctrl.ld\ : DFN1E0 - port map(D => ld_1, CLK => lclk_c, E => holdn, Q => ld_5); - - \r.e.ctrl.inst_RNIFC0E[30]\ : OR2B - port map(A => \inst_2[31]\, B => \inst_2[30]\, Y => - N_3356_3); - - \r.x.y[25]\ : DFN1E0 - port map(D => \y_2[25]\, CLK => lclk_c, E => holdn, Q => - \y_1[25]\); - - \r.m.y_RNO[14]\ : OR3C - port map(A => \y_iv_0_1[14]\, B => \y_iv_0_0[14]\, C => - N_385, Y => \y_1[14]\); - - \r.e.aluop_0_RNI39JG3[0]\ : MX2C - port map(A => N_3567, B => N_3631, S => \aluop_0[0]\, Y => - \logicout[8]\); - - \r.e.shleft_0_RNISUAG\ : OR2A - port map(A => \un1_iu0_6[0]\, B => shleft_0, Y => - \shiftin_5[0]\); - - \r.e.op2_RNO_7[19]\ : OR3C - port map(A => d28_0, B => \rsel2_1[0]\, C => - \un1_p0_6[371]\, Y => \cpi_m_i[371]\); - - \r.x.data_0[4]\ : DFN1E0 - port map(D => \data_0_1[4]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[4]\); - - \r.x.ctrl.inst_RNIHVSN2[24]\ : NOR3A - port map(A => tba_610_e_5, B => tba_1_sqmuxa_3, C => holdn, - Y => \inst_RNIHVSN2[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I249_Y : OR2 - port map(A => N668_1, B => I249_un1_Y_0, Y => N814_0); - - \r.e.shcnt_RNIGAVV3[3]\ : MX2 - port map(A => \shiftin_8[13]\, B => \shiftin_8[5]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[5]\); - - \r.e.op2_RNIHS9P_0[3]\ : OR2 - port map(A => \un1_iu0_6[3]\, B => \un1_iu0_5[69]\, Y => - \logicout_3[3]\); - - \r.e.ctrl.pc_RNI60LA2[6]\ : AOI1B - port map(A => \pc[6]\, B => jmpl_0, C => \y_m_1[6]\, Y => - \aluresult_1_iv_2[6]\); - - \r.x.y[10]\ : DFN1E0 - port map(D => \y_0[10]\, CLK => lclk_c, E => holdn, Q => - \y_2[10]\); - - \r.a.rsel2[2]\ : DFN1E0 - port map(D => N_3946_1, CLK => lclk_c, E => holdn, Q => - \rsel2[2]\); - - wovf_exc_0_sqmuxa_RNO_5 : MX2 - port map(A => \wim_1[2]\, B => \wim_1[6]\, S => \ncwp_3[2]\, - Y => N_3726); - - \r.a.ctrl.inst_RNIU43A1_0[21]\ : OR2A - port map(A => inst_5_1, B => N_515, Y => inst_5); - - \r.x.ctrl.pc[16]\ : DFN1E0 - port map(D => \pc_3[16]\, CLK => lclk_c, E => holdn, Q => - \pc_2[16]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I166_Y : OR2A - port map(A => N577_0, B => N569, Y => N635_1); - - \r.f.pc_RNO[5]\ : AO1B - port map(A => I_13, B => un2_rstn_4_0_0, C => - \pc_1_iv_2[5]\, Y => \pc_1[5]\); - - \r.e.ldbp2_2_RNI620KL1\ : OR2A - port map(A => \eaddress[14]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[15]\); - - \r.e.ctrl.pc_RNIC0LA2[9]\ : AOI1B - port map(A => \pc[9]\, B => jmpl_0, C => \y_m_1[9]\, Y => - \aluresult_1_iv_1[9]\); - - \r.x.npc_0_RNI3DR61[0]\ : MX2C - port map(A => N_3242, B => N_3272, S => \npc_0[0]\, Y => - \xc_result[31]\); - - \r.m.ctrl.rd[0]\ : DFN1E0 - port map(D => \rd[0]\, CLK => lclk_c, E => holdn, Q => - \rd_1[0]\); - - \r.e.op2_RNO_2[5]\ : NOR3C - port map(A => \d_1_iv_1[5]\, B => \d_1_iv_0[5]\, C => - \rfo_m_i[37]\, Y => \d_1_iv_3[5]\); - - \r.e.aluop_2_RNIDI6R2[1]\ : MX2C - port map(A => N_3544, B => \logicout_3[17]\, S => - \aluop_2[1]\, Y => N_3576); - - un6_ex_add_res_d1_ADD_33x33_fast_I13_P0N : OR2 - port map(A => \op2[12]\, B => \un1_iu0_6[12]\, Y => N434_0); - - \r.e.ctrl.inst_RNIHS0E[24]\ : NOR2A - port map(A => \inst[24]\, B => \inst_1[21]\, Y => - aluresult_12_sqmuxa_4); - - \r.w.s.tba_RNI074BK[16]\ : NOR3C - port map(A => \bpdata_m_2[4]\, B => \aluresult_1_iv_3[28]\, - C => \aluresult_1_iv_4[28]\, Y => \aluresult_1_iv_6[28]\); - - \r.x.data_0_RNO_3[10]\ : OR2A - port map(A => \data_0[10]\, B => ld_0_0, Y => - \data_0_m_i[10]\); - - \r.f.pc_RNI7BEN55[9]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[9]\, Y => - \pc_4_m[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I248_Y : OR2A - port map(A => I248_un1_Y_i, B => N666, Y => N811); - - \r.e.ldbp2_RNICGKQM1\ : MX2C - port map(A => \un6_ex_add_res_s1_i[16]\, B => N_6635, S => - ldbp2_3, Y => \eaddress[15]\); - - \r.x.result_RNI8MTN5[1]\ : OR2A - port map(A => N_3687, B => \bpdata[1]\, Y => - \bpdata_i_m[1]\); - - \r.x.data_0_RNIMVG8[24]\ : XOR2 - port map(A => \data_0[24]\, B => invop2, Y => N_4271); - - \r.m.y_RNO_1[15]\ : OR3A - port map(A => \y_1[15]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[15]\); - - \r.e.op2_RNIUSAP[7]\ : OR2A - port map(A => \un1_iu0_5[73]\, B => \un1_iu0_6[7]\, Y => - \logicout_4[7]\); - - \r.e.op2_RNO_8[28]\ : OR3B - port map(A => d29_0, B => \imm[28]\, C => \rsel2[0]\, Y => - \imm_m_i[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I297_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[7]\, B => N674_1, Y => - \un6_ex_add_res_s0[7]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I5_G0N\ : AND2 - port map(A => \dpc[7]\, B => \inst_0[5]\, Y => N373); - - \r.m.ctrl.tt[5]\ : DFN1E0 - port map(D => \tt_3[5]\, CLK => lclk_c, E => holdn, Q => - \tt_1[5]\); - - \r.e.shcnt_RNIR4JM7[3]\ : MX2C - port map(A => \shiftin_8[45]\, B => \shiftin_8[37]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[37]\); - - \r.e.op2[30]\ : DFN1E0 - port map(D => N_314, CLK => lclk_c, E => holdn, Q => - \op2[30]\); - - \r.e.op1_RNIVENF[13]\ : NOR2A - port map(A => \un17_casaen_0_0\, B => \op1[13]\, Y => - \op1_i_m[13]\); - - \r.e.alusel_RNIJDA9[0]\ : OR2A - port map(A => \alusel[0]\, B => \alusel[1]\, Y => - aluresult_1_sqmuxa_0_0); - - \r.e.op1_RNIFNIO58[30]\ : NOR3C - port map(A => \op1_m_0[30]\, B => \d_iv_2[30]\, C => - \aluresult_m_0[30]\, Y => \d_i[30]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I289_Y_0\ : XNOR2 - port map(A => N694, B => ADD_30x30_fast_I289_Y_0_0, Y => - \tmp[31]\); - - \r.w.s.et_RNI1BRF2\ : OR2B - port map(A => cwp_2_sqmuxa_i, B => N_6337, Y => et_RNI1BRF2); - - \r.e.op2_RNO_3[24]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[24]\, Y => - \aluresult_m_i[24]\); - - \r.x.result_RNIHLBB[3]\ : MX2 - port map(A => \result_0[3]\, B => \data_0[3]\, S => ld_4, Y - => \un1_p0_6[355]\); - - \r.a.ctrl.inst_RNISAEP[10]\ : NOR3A - port map(A => un29_casaen_1, B => \inst[11]\, C => - \inst[10]\, Y => un29_casaen_4); - - \r.m.ctrl.pv\ : DFN1E0 - port map(D => pv_5, CLK => lclk_c, E => holdn, Q => pv_1); - - \r.e.op2_RNO_4[17]\ : OA1A - port map(A => \maddress[17]\, B => d27, C => \cpi_m_i[369]\, - Y => \d_1_iv_1[17]\); - - \r.a.rsel1_0_RNI4V53_0[2]\ : NOR2 - port map(A => d11_0_a5_0, B => \rsel1_0[2]\, Y => d11_0); - - \r.x.rstate_RNI1BC12[0]\ : MX2C - port map(A => N_3411, B => \xc_result[20]\, S => - \rstate[0]\, Y => \wdata[20]\); - - \r.e.ldbp2_2_RNI2UDR53\ : MX2C - port map(A => \un6_ex_add_res_s1_i[21]\, B => N_6567, S => - ldbp2_2, Y => \eaddress[20]\); - - \r.a.ctrl.pv\ : DFN1E0 - port map(D => ctrl_pv, CLK => lclk_c, E => holdn, Q => pv_4); - - \comb.branch_address.tmp_ADD_30x30_fast_I110_Y\ : OR2 - port map(A => N471, B => I110_un1_Y, Y => N530_1); - - \r.x.mexc_RNII0QT\ : NOR2 - port map(A => mexc_0, B => N_3323, Y => \xc_vectt_1[4]\); - - \r.e.op2[16]\ : DFN1E0 - port map(D => N_300, CLK => lclk_c, E => holdn, Q => - \op2[16]\); - - \r.e.aluop_RNIMFFR5[0]\ : OR2B - port map(A => \logicout[20]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[20]\); - - un2_rstn_5_0_0_RNIQT8C2 : NAND2 - port map(A => \tmp[4]\, B => un2_rstn_5_0, Y => \tmp_m[4]\); - - \r.e.shleft_0_RNITSHP\ : OR2A - port map(A => \un1_iu0_6[15]\, B => shleft_0, Y => - \shiftin_5[15]\); - - \r.m.result[10]\ : DFN1E0 - port map(D => \eres2[10]\, CLK => lclk_c, E => holdn, Q => - \maddress[10]\); - - \r.m.icc_RNI88I3_0[3]\ : NOR2 - port map(A => \icc[3]\, B => \icc[1]\, Y => N_523); - - \r.e.op2_RNO_7[16]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[368]\, Y => \cpi_m_i[368]\); - - \r.w.result_RNIJJD4[21]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[21]\, - Y => \result_m_0[21]\); - - \r.e.ctrl.tt_RNO_0[2]\ : NOR2 - port map(A => \tt_9_i_a4_0[2]\, B => trap_4_1, Y => N_4039); - - \r.e.ctrl.rd[7]\ : DFN1E0 - port map(D => \rd[7]\, CLK => lclk_c, E => holdn, Q => - \rd_1[7]\); - - \r.e.shcnt_RNIUQP9D[2]\ : MX2C - port map(A => \shiftin_11[26]\, B => \shiftin_11[22]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[22]\); - - \r.f.pc_RNO_2[28]\ : OR2B - port map(A => I_186, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I293_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[2]\, B => \data_0[2]\, Y => - \un6_ex_add_res_s2_1[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I183_Y : OR2 - port map(A => N586, B => I183_un1_Y, Y => N652_1); - - \r.e.mulstep_RNI8VGC_2\ : NOR2B - port map(A => mulstep, B => wy_0, Y => mulstep_1); - - \r.e.ctrl.inst_RNIN8Q71[26]\ : AOI1B - port map(A => N_229, B => N_211, C => ex_bpmiss_1_0_a5_1_1, - Y => N_427); - - \r.d.pc_RNO[27]\ : MX2 - port map(A => \fpc[27]\, B => \dpc[27]\, S => N_6763_i, Y - => \pc_RNO[27]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I6_P0N : OR2 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, Y => N413); - - \r.a.ctrl.cnt_RNI515E[0]\ : OR3A - port map(A => \cnt_2[1]\, B => \cnt_1[0]\, C => - \inst_2[20]\, Y => aluop_2_1_0_a5_1_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I114_Y : NOR2A - port map(A => N511_0, B => N_30_0, Y => N577); - - \r.x.laddr_RNI4ADG12[1]\ : OR2 - port map(A => rdata_4_sqmuxa, B => rdata_2_sqmuxa, Y => - N_3480); - - \r.x.result_RNI905F5[10]\ : NOR2A - port map(A => \aluop_RNIGM3N1[2]\, B => \bpdata[10]\, Y => - \bpdata_i_m[10]\); - - \r.w.s.pil_RNILSV29[3]\ : OA1A - port map(A => N_3974, B => \bpdata[11]\, C => - \aluresult_1_iv_2[11]\, Y => \aluresult_1_iv_4[11]\); - - \r.m.nalign_RNI0UR41\ : NOR3 - port map(A => trap_0_sqmuxa_1_1_i, B => trap_0_sqmuxa_1_0, - C => trap_0_sqmuxa_1_2_i, Y => trap_0_sqmuxa_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_un1_Y : OAI1 - port map(A => I249_un1_Y, B => N668_0, C => - ADD_33x33_fast_I265_un1_Y_0_0, Y => I265_un1_Y_i_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I61_Y : MAJ3 - port map(A => \op2[16]\, B => \un1_iu0_6[16]\, C => N442_0, - Y => N520_1); - - \r.m.irqen_RNO_0\ : NOR3A - port map(A => trap27, B => trap63, C => annul_RNIPFOQ, Y - => irqen_1); - - \r.f.pc_RNIVNV31[6]\ : MX2 - port map(A => \fpc[6]\, B => \xc_vectt_1[2]\, S => - rstate_6314_d_0, Y => \xc_trap_address[6]\); - - \r.e.alusel_RNO_2[0]\ : OR2B - port map(A => N_351_1, B => N_203, Y => N_351); - - \r.m.y_RNIAJD92[17]\ : AOI1B - port map(A => \y[17]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[162]\, Y => \aluresult_1_iv_1[17]\); - - \r.m.ctrl.wreg\ : DFN1E0 - port map(D => wreg_1_9, CLK => lclk_c, E => holdn, Q => - wreg_4); - - \r.e.ctrl.inst_RNIGF49A5[24]\ : OR3B - port map(A => \icc_8_m_1[1]\, B => \icc_8[1]\, C => - \icc_8_m_5[1]\, Y => \icc_8_m_i[1]\); - - \r.x.ctrl.pc_RNI67AE[2]\ : MX2 - port map(A => \pc_0[2]\, B => \pc_2[2]\, S => \npc_0[1]\, Y - => N_3213); - - \r.e.et_RNI9QNL5\ : OA1A - port map(A => et_0, B => aluresult_11_sqmuxa, C => - \aluresult_1_iv_1[5]\, Y => \aluresult_1_iv_3[5]\); - - \r.x.data_0_RNO[5]\ : AO1B - port map(A => N_3456, B => N_3389_i_0, C => - \data_0_1_1_iv_2[5]\, Y => \data_0_1[5]\); - - \r.e.su\ : DFN1E0 - port map(D => su_1, CLK => lclk_c, E => holdn, Q => esu); - - \r.e.shcnt_RNISL246[3]\ : MX2 - port map(A => \shiftin_8[26]\, B => \shiftin_8[18]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[18]\); - - \r.d.inst_0_RNIKG46[29]\ : NOR2A - port map(A => N_85, B => N_3525_3, Y => un3_reg); - - \r.a.ctrl.wreg_RNO_8\ : OR3B - port map(A => \inst_0[20]\, B => N_142, C => - \un1_p0_6_0[60]\, Y => inst_0); - - \r.e.shcnt_RNI0NSS4[3]\ : MX2 - port map(A => \shiftin_8[15]\, B => \shiftin_8[7]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_o3_1 : OR2B - port map(A => ADD_33x33_fast_I206_Y_0_o3_1_0, B => N_57_i, - Y => N616); - - \r.w.s.y[13]\ : DFN1E0 - port map(D => N_3777, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[13]\); - - \r.m.result[21]\ : DFN1E0 - port map(D => \eres2[21]\, CLK => lclk_c, E => holdn, Q => - \maddress[21]\); - - \r.m.dci.asi_RNO_1[0]\ : NOR2A - port map(A => rett_0, B => annul_0, Y => rett_i); - - \r.e.op1_RNI221HH7[28]\ : AOI1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[28]\, C - => \d_iv_3[28]\, Y => \d_i[28]\); - - \r.e.ldbp2_2_RNI2O2TD4\ : MX2C - port map(A => \un6_ex_add_res_s1_i[28]\, B => N_6574, S => - ldbp2_2, Y => \eaddress[27]\); - - \r.m.y_RNO_3[27]\ : OR3A - port map(A => \y_2[27]\, B => wy_3, C => wy_1_0_1, Y => - N_422); - - \r.e.shleft_RNI7BQR2\ : MX2 - port map(A => \shiftin_5[55]\, B => \shiftin_5[39]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[39]\); - - \r.m.result_RNO[10]\ : MX2 - port map(A => \aluresult[10]\, B => \op1[10]\, S => - un17_casaen_0, Y => \eres2[10]\); - - \r.e.ldbp2_0_RNI874SQ1\ : MX2C - port map(A => \un6_ex_add_res_s1_i[17]\, B => N_6563, S => - ldbp2_0, Y => \eaddress[16]\); - - \r.a.rfa2[4]\ : DFN1E0 - port map(D => \un3_de_ren1[103]\, CLK => lclk_c, E => holdn, - Q => \rfa2[4]\); - - \r.e.ctrl.pc_RNIDTK11[18]\ : OR2B - port map(A => \pc_0[18]\, B => jmpl_4, Y => \cpi_m[163]\); - - \r.x.data_0_RNO_0[2]\ : AO1B - port map(A => rdatav_0_1_0_iv_5_0, B => mcdo_m_0_16, C => - N_3455, Y => \dco_m_i[114]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I7_P0N : OR2 - port map(A => \un1_iu0_6[6]\, B => \op2[6]\, Y => N416_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I231_un1_Y : NAND2 - port map(A => N645, B => N660, Y => I231_un1_Y_i); - - \r.e.jmpl_RNID42AH1\ : AND2 - port map(A => \shiftin_17_m[15]\, B => - \aluresult_1_iv_7[14]\, Y => \aluresult_1_iv_8[14]\); - - \r.x.rstate_RNIEO45[1]\ : OR2A - port map(A => \rstate[1]\, B => \rstate_0[0]\, Y => - rstate_6314_d_0); - - \r.m.y_RNIUT7CA[18]\ : NOR3C - port map(A => \aluresult_1_iv_1[18]\, B => - \aluresult_1_iv_0[18]\, C => \aluresult_1_iv_3[18]\, Y - => \aluresult_1_iv_4[18]\); - - \r.a.ctrl.rett_RNIS5SE\ : NOR3A - port map(A => rett_2, B => trap_1, C => annul_2, Y => - rett_1); - - \r.a.jmpl\ : DFN1E0 - port map(D => jmpl_3, CLK => lclk_c, E => holdn, Q => - jmpl_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I3_P0N : OR2 - port map(A => \un1_iu0_6[2]\, B => \op2[2]\, Y => N404); - - \r.e.ctrl.tt_RNO[5]\ : AOI1 - port map(A => N_4043_i, B => N_4042, C => annul_2, Y => - \tt_2[5]\); - - \r.a.ctrl.inst_RNID8Q8[28]\ : XOR2 - port map(A => \inst_1[28]\, B => \icc[1]\, Y => branch_8); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_Y : NAND2 - port map(A => I265_un1_Y_i_0, B => - ADD_33x33_fast_I265_Y_1_0, Y => N776); - - \r.e.jmpl_RNI2UJLU_0\ : OR2B - port map(A => \shiftin_17[28]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[28]\); - - \r.e.op2_RNO_2[30]\ : NOR3C - port map(A => \d_1_iv_1[30]\, B => \d_1_iv_0[30]\, C => - \rfo_m_i[62]\, Y => \d_1_iv_3[30]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_4\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \r.e.aluop_RNIE7BBM[0]\ : AND2 - port map(A => \aluresult_1_iv_6[20]\, B => - \logicout_m_0[20]\, Y => \aluresult_1_iv_7[20]\); - - \r.a.imm_RNO[9]\ : NOR2B - port map(A => \inst_0[9]\, B => call_hold5, Y => - \un3_de_ren1[127]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I30_un1_Y\ : OR3B - port map(A => \dpc[29]\, B => \inst_0_RNI8AJ4[27]\, C => - N443_2, Y => ADD_30x30_fast_I30_un1_Y); - - \r.x.y[7]\ : DFN1E0 - port map(D => \y[7]\, CLK => lclk_c, E => holdn, Q => - \y_2[7]\); - - \r.x.npc_RNIAS011[0]\ : MX2C - port map(A => N_3232, B => N_3262, S => \npc[0]\, Y => - \xc_result[21]\); - - \r.e.ldbp2_RNIIDDTL1\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[4]\, Y => - \un6_ex_add_res_m_1[5]\); - - \r.w.s.tba_RNI34CA1[2]\ : OR2B - port map(A => \tba[2]\, B => aluresult_12_sqmuxa, Y => - \tba_m[2]\); - - \r.f.pc_RNO_3[13]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[13]\, C => - \xc_trap_address_m[13]\, Y => \pc_1_iv_0[13]\); - - \r.x.data_0_RNO_4[1]\ : AO1B - port map(A => rdatav_0_1_0_iv_4_0, B => mcdo_m_0_7, C => - rdata_2_sqmuxa, Y => \dco_m_i[105]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I227_un1_Y : OR2B - port map(A => N656_1, B => N641_1, Y => I227_un1_Y); - - \r.e.op2_RNO_0[18]\ : OR3C - port map(A => \op1_m_i[18]\, B => \d_1_iv_3[18]\, C => - \aluresult_m_i[18]\, Y => \d_1[18]\); - - \r.x.data_0_RNO_2[0]\ : AO1 - port map(A => rdatav_0_1_0_iv_5_6, B => mcdo_m_0_22, C => - rdata_0_sqmuxa, Y => \dco_m_i[120]\); - - \r.m.y_RNO_4[9]\ : OR3A - port map(A => \y_2[9]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[9]\); - - \r.e.jmpl_RNIGBJ9J1\ : AOI1B - port map(A => \shiftin_17[23]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[22]\, Y => \aluresult_1_iv_8[22]\); - - \r.a.rsel2_0_RNIMCHE[0]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[354]\, Y => \cpi_m_i[354]\); - - \r.e.aluop_0_RNIT26O1[1]\ : MX2C - port map(A => \logicout_4[1]\, B => N_6889, S => N_6866_i_0, - Y => N_3624); - - \comb.branch_address.tmp_ADD_30x30_fast_I263_Y_0_0\ : XOR2 - port map(A => \dpc[5]\, B => \inst_0_RNI3RUM[3]\, Y => - ADD_30x30_fast_I263_Y_0_0); - - \r.e.op1_RNIIUBR1[12]\ : NOR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[12]\, Y => - \ex_op1_i_m[12]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I321_Y_0 : XOR2 - port map(A => N766_0, B => \un6_ex_add_res_s2_1[31]\, Y => - \un6_ex_add_res_s2[31]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I18_G0N\ : NOR2B - port map(A => \inst_0[18]\, B => \dpc[20]\, Y => N412); - - \r.x.result_RNIQGAN3[17]\ : MX2 - port map(A => \un1_iu0_6[17]\, B => \un1_p0_6[369]\, S => - bpdata6, Y => \bpdata[17]\); - - \r.x.ctrl.rett\ : DFN1E0 - port map(D => rett_1_1, CLK => lclk_c, E => holdn, Q => - rett_0); - - \r.f.pc_RNIQUO11[11]\ : MX2 - port map(A => \fpc[11]\, B => xc_vectt14, S => - rstate_6314_d, Y => \xc_trap_address[11]\); - - \r.d.inst_0_RNO[4]\ : NOR2B - port map(A => rst, B => N_4604, Y => \inst_0_RNO[4]\); - - \r.x.ctrl.wy_RNIGJP13\ : AO1A - port map(A => y_0_sqmuxa_1, B => y_0_sqmuxa_3, C => wy_2, Y - => y_1_sqmuxa); - - un6_fe_npc_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - \r.x.result_RNINK6E[22]\ : MX2 - port map(A => \result_0[22]\, B => \data_0_0[22]\, S => - ld_4, Y => \un1_p0_6[374]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I50_Y : NOR2B - port map(A => N464, B => N461_1, Y => N509_0); - - \r.d.cwp[1]\ : DFN1E0 - port map(D => \cwp_1_0[1]\, CLK => lclk_c, E => holdn, Q - => \cwp[1]\); - - \r.a.et_RNIGQT5A\ : NOR3C - port map(A => illegal_inst_7_iv_0, B => N_444, C => - illegal_inst_7_iv_1, Y => illegal_inst_7_iv_3); - - un6_ex_add_res_d1_ADD_33x33_fast_I56_Y_i : OR2B - port map(A => N455_2, B => N452_0, Y => N_30); - - \r.e.op1_RNI4VNF[27]\ : OR2A - port map(A => un17_casaen_0, B => \op1[27]\, Y => - \op1_RNI4VNF[27]\); - - \r.a.ctrl.inst_RNITH523[22]\ : OA1A - port map(A => cp_disabled_10_sqmuxa_1, B => N_260, C => - cp_disabled_5_sqmuxa, Y => fp_disabled_4_0_1_1); - - \r.w.result_RNIG4P1[29]\ : OR3C - port map(A => N_484_0, B => \rsel1[2]\, C => \result[29]\, - Y => \result_m_0[29]\); - - \comb.lock_gen.ldchkra\ : OR2A - port map(A => ldchkra_0, B => call_hold7_i, Y => ldchkra); - - \r.m.y_RNO_1[21]\ : OR3A - port map(A => \y_1[21]\, B => wy_3, C => wy_1_0_0, Y => - \y_m[21]\); - - \r.x.data_0_RNO[1]\ : AO1B - port map(A => N_3456, B => N_3227_i_0, C => - \data_0_1_1_iv_2[1]\, Y => \data_0_1[1]\); - - \r.e.op2_RNO_1[14]\ : OR2B - port map(A => \op1[14]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[14]\); - - \r.d.inst_0_0_0_RNIAG79[21]\ : NOR3A - port map(A => \un1_p0_6_0[60]\, B => \inst_0[19]\, C => - \inst_0[20]\, Y => wy_1_0_a3_1_0); - - \r.a.ctrl.inst_RNIK15D2[30]\ : OA1A - port map(A => aluop_0_1_0_a5_3_0, B => N_205, C => N_363, Y - => aluop_0_1_0_2); - - \r.w.s.tba[8]\ : DFN1E1 - port map(D => \result[20]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[8]\); - - \r.w.result_RNISDSI[2]\ : AOI1B - port map(A => \un1_p0_6[354]\, B => d14, C => - \result_m_0_0[2]\, Y => \d_iv_0[2]\); - - \r.e.aluop_1[1]\ : DFN1E0 - port map(D => \aluop[1]\, CLK => lclk_c, E => holdn, Q => - \aluop_1[1]\); - - \r.a.bp_RNIQD984\ : OR2B - port map(A => ra_bpmiss_1_1, B => branch, Y => - \ra_bpmiss_1_0\); - - \r.a.ctrl.rd_RNITO2A1[2]\ : XA1A - port map(A => \un3_de_ren1[93]\, B => \rd[2]\, C => - un2_rs1_3_i, Y => un2_rs1_NE_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I278_Y_0_0\ : XOR2 - port map(A => \dpc[20]\, B => \inst_0[18]\, Y => - ADD_30x30_fast_I278_Y_0_0); - - \r.x.result_RNIF7GQ[6]\ : NOR2B - port map(A => \result_0[6]\, B => xc_vectt14, Y => - \xc_vectt_1[6]\); - - \r.e.op2_RNI1PJF75[31]\ : AO18 - port map(A => \un1_iu0_6[31]\, B => \eaddress[31]\, C => - \un1_iu0_5[97]\, Y => \icc_3_i_0[0]\); - - \r.e.op1_RNICHFC[8]\ : OR2B - port map(A => \op1[8]\, B => un14_casaen_s1_0, Y => - \op1_m_0[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I105_Y : AO1 - port map(A => N506, B => N503_1, C => N502_1, Y => N568_1); - - \r.w.result[1]\ : DFN1E0 - port map(D => \wdata[1]\, CLK => lclk_c, E => holdn, Q => - \result[1]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I237_Y_0_a3\ : AO1D - port map(A => ADD_30x30_fast_I239_Y_1, B => I239_un1_Y, C - => N_11, Y => N_59); - - \r.e.invop2_1_RNIBPPN3\ : MX2 - port map(A => \un6_ex_add_res_s2[4]\, B => - \un6_ex_add_res_s0[4]\, S => invop2_1, Y => N_6643); - - \r.a.ctrl.cnt_RNI041R1[0]\ : OA1A - port map(A => \alusel_i_0_a2_1_0[1]\, B => N_212, C => - N_476, Y => \alusel_i_0_o5_0[1]\); - - \r.f.pc_RNO[7]\ : OR3C - port map(A => \tmp_m[7]\, B => \pc_1_iv_1[7]\, C => - \un6_fe_npc_m[5]\, Y => \pc_1[7]\); - - \r.a.ctrl.inst_RNIE15O1[19]\ : AO1D - port map(A => \inst_2[19]\, B => illegal_inst35_4, C => - illegal_inst_7_iv_2_0_a5_0_0, Y => - illegal_inst_7_iv_2_0_a5_0_1); - - \r.x.ctrl.pc[15]\ : DFN1E0 - port map(D => \pc_3[15]\, CLK => lclk_c, E => holdn, Q => - \pc_0[15]\); - - \r.m.ctrl.rd_RNIN29A2[4]\ : XNOR2 - port map(A => \un3_de_ren1[103]\, B => \rd[4]\, Y => - un1_de_ren1_1_4_i_0); - - un6_fe_npc_I_90 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[9]\, Y => N_88); - - \r.a.ctrl.inst_RNIEC1L_0[23]\ : OR2 - port map(A => \inst_1[23]\, B => alusel24_2, Y => - illegal_inst12_0); - - \r.m.y_RNIULO71[26]\ : OR2B - port map(A => \y_1[26]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[26]\); - - un6_fe_npc_I_77 : XOR2 - port map(A => N_98, B => \fe_pc[15]\, Y => I_77); - - \r.x.result_RNINA2U4[9]\ : NOR2A - port map(A => \aluop_RNIGM3N1[2]\, B => \bpdata[9]\, Y => - \bpdata_i_m[9]\); - - \r.a.rsel2_0_RNIFA4D_0[0]\ : NOR2B - port map(A => un17_casaen_0_2, B => d26, Y => - un14_casaen_s1_0_1); - - \r.d.inst_0_RNI1DOH[15]\ : MX2 - port map(A => \inst_0[15]\, B => \inst_0[26]\, S => rs1mod, - Y => \un3_de_ren1[92]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I259_Y_3 : NOR3C - port map(A => I155_un1_Y_0, B => ADD_33x33_fast_I259_Y_1_0, - C => I211_un1_Y_0, Y => ADD_33x33_fast_I259_Y_3_0); - - \r.m.ctrl.inst[23]\ : DFN1E0 - port map(D => \inst_0[23]\, CLK => lclk_c, E => holdn, Q - => \inst_2[23]\); - - \r.e.op2_RNO_3[21]\ : OA1A - port map(A => \maddress[21]\, B => d27_0, C => - \cpi_m_i[373]\, Y => \d_1_iv_1[21]\); - - \r.a.ctrl.pc[30]\ : DFN1E0 - port map(D => \dpc[30]\, CLK => lclk_c, E => holdn, Q => - \pc[30]\); - - \r.e.op2_RNIMVGN1[21]\ : OR2A - port map(A => aluresult_7_sqmuxa, B => \un1_iu0_5[87]\, Y - => \ex_op2_m[21]\); - - \r.m.icc_RNO_11[2]\ : NOR2 - port map(A => \logicout[28]\, B => \logicout[29]\, Y => - icc_0_sqmuxa_1_10); - - \comb.branch_address.tmp_ADD_30x30_fast_I68_un1_Y\ : NOR3C - port map(A => \dpc[10]\, B => \inst_0[8]\, C => N386, Y => - I68_un1_Y); - - un6_ex_add_res_d2_ADD_33x33_fast_I229_un1_Y : NOR2A - port map(A => N658, B => N643, Y => I229_un1_Y); - - \r.m.y_RNO_1[6]\ : AOI1B - port map(A => \y_0[6]\, B => y08, C => \y_m[7]\, Y => - \y_iv_0[6]\); - - \r.f.pc_RNITQQB85[11]\ : MX2 - port map(A => I_52, B => N_4054, S => bpmiss_1_i_0, Y => - \pc_4[11]\); - - \comb.cwp_ctrl.ncwp_3_I_13\ : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[1]\, B => - \cwp_0[0]\, Y => \ncwp_3[1]\); - - \r.f.pc_RNITOA81[9]\ : MX2 - port map(A => \fpc[9]\, B => \xc_vectt_1[5]\, S => - rstate_6314_d, Y => \xc_trap_address[9]\); - - \r.x.result_RNI7Q1O3[21]\ : MX2 - port map(A => \un1_iu0_6[21]\, B => \un1_p0_6[373]\, S => - bpdata6, Y => \bpdata[21]\); - - \r.m.ctrl.inst_RNI211E_0[22]\ : NOR2 - port map(A => \inst_0[24]\, B => \inst_2[22]\, Y => - inst_2_0); - - \r.m.y_RNIT0QJF[18]\ : NOR2B - port map(A => \bpdata_m_1[2]\, B => \aluresult_1_iv_4[18]\, - Y => \aluresult_1_iv_5[18]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I308_Y_0 : AX1B - port map(A => I239_un1_Y_0, B => ADD_33x33_fast_I273_Y_0_0, - C => ADD_33x33_fast_I308_Y_0_0, Y => - \un6_ex_add_res_s1_i[18]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I139_Y : AO1 - port map(A => N540_0, B => N537_1, C => N536_1, Y => N602_0); - - \r.m.y_RNO_2[7]\ : OR2B - port map(A => \y[7]\, B => y08, Y => \y_m_0[7]\); - - \r.f.pc_RNO_8[30]\ : MX2 - port map(A => \fpc[30]\, B => \eaddress[30]\, S => jump_0, - Y => N_4073); - - \r.d.inull_RNO_2\ : NOR2A - port map(A => jmpl_2, B => trap_1, Y => de_inull_0_a3_1_0); - - \r.e.op2_RNIAK9P_0[2]\ : OR2 - port map(A => \un1_iu0_6[2]\, B => \un1_iu0_5[68]\, Y => - \logicout_3[2]\); - - \r.a.ctrl.inst_RNIJ42L[21]\ : NOR3A - port map(A => \inst_2[21]\, B => \inst_2[19]\, C => - \inst_1[24]\, Y => un1_aop2_1_sqmuxa_0_a2_0_0); - - \r.m.y_RNI04GU[0]\ : AOI1B - port map(A => \y_0[0]\, B => y08_0, C => N_468, Y => - \y_iv_0_o5_0[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I282_Y_0_0\ : XOR2 - port map(A => \dpc[24]\, B => \inst_0_0_0_RNI9O79[21]\, Y - => ADD_30x30_fast_I282_Y_0_0); - - un6_fe_npc_I_125 : AND2 - port map(A => \fe_pc[20]\, B => \fe_pc[21]\, Y => - \DWACT_FINC_E[14]\); - - \r.e.jmpl_RNIRSOT_0\ : OR2A - port map(A => miscout_11_sqmuxa, B => jmpl, Y => jmpl_0); - - \comb.op_mux.d_1_iv_RNO_0[29]\ : AND2 - port map(A => \op1_m_i[29]\, B => \d_1_iv_3[29]\, Y => - \d_1_iv_4[29]\); - - \r.a.ctrl.pc_RNI8SE2C[18]\ : MX2 - port map(A => \pc[18]\, B => N_3895, S => ex_bpmiss_1_0, Y - => \fe_pc[18]\); - - \r.e.op1_RNISTJ352[3]\ : OR3C - port map(A => \op1_m_i[3]\, B => \d_1_iv_3[3]\, C => - \aluresult_m_i[3]\, Y => \d_1[3]\); - - \r.d.inst_0_RNI4023_1[20]\ : NOR2A - port map(A => \inst_0[20]\, B => \inst_0[19]\, Y => - ticc_exception_1); - - \r.e.op1_RNIULHR3[24]\ : NOR3C - port map(A => \rfo_m[24]\, B => \d_iv_1[24]\, C => - \op1_m_0[24]\, Y => \d_iv_3[24]\); - - \r.f.pc_RNO_4[20]\ : MX2 - port map(A => I_115, B => N_4063, S => bpmiss_1_i_0_0, Y - => \pc_4[20]\); - - \r.a.ctrl.inst_RNI5C0E[21]\ : NOR2B - port map(A => \inst_2[21]\, B => \inst_2[20]\, Y => N_58); - - un6_ex_add_res_d0_ADD_33x33_fast_I4_G0N : NOR3A - port map(A => \op1[3]\, B => ldbp1_4, C => \data_0[3]\, Y - => N406); - - \un1_r.w.s.cwp_1_ANB0\ : NOR2A - port map(A => \cwp[0]\, B => \rstate_RNIRDFU5[1]\, Y => CO0); - - un6_ex_add_res_d1_ADD_33x33_fast_I121_Y : AO1B - port map(A => N522_1, B => N519_1, C => - ADD_33x33_fast_I121_Y_0_1, Y => N584_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I128_Y : OR2B - port map(A => N529_1, B => N525, Y => N591_0); - - \r.e.ctrl.pc_RNI99K11[23]\ : OR2B - port map(A => \pc_0[23]\, B => jmpl_4, Y => \cpi_m[168]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I317_Y_0 : XNOR2 - port map(A => N774_0, B => \un6_ex_add_res_s2_1[27]\, Y => - \un6_ex_add_res_s0[27]\); - - \r.e.op1_RNIQ29G[24]\ : OR2B - port map(A => \op1[24]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[24]\); - - \comb.lock_gen.un1_icc_check5_RNO_1\ : NOR2B - port map(A => N_3518_1, B => N_3736_2, Y => icc_check6_0); - - \r.e.op1_RNIU3N9F[28]\ : NOR3C - port map(A => \edata2_iv_0[28]\, B => \bpdata_i_m[28]\, C - => \edata2_iv_2[28]\, Y => edata2_iv_i_0(28)); - - \r.m.y_RNO_2[28]\ : OR2B - port map(A => \y[28]\, B => y08, Y => \y_m_0[28]\); - - \r.a.rfa2_RNILU3T1[7]\ : MX2A - port map(A => un1_reg, B => \rfa2[7]\, S => holdn, Y => - \raddr2[7]\); - - un6_fe_npc_I_172 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[19]\, Y => N_30_1); - - \r.f.pc_RNIKTGB4[12]\ : MX2 - port map(A => \dpc[12]\, B => \fpc[12]\, S => - \ra_bpmiss_1_0\, Y => N_3889); - - \r.e.shleft_1_RNILRBD1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[5]\, S => - shleft_1, Y => \shiftin_5[36]\); - - \r.a.imm_RNO[2]\ : NOR2B - port map(A => \inst_0_RNI2NUM[2]\, B => call_hold5, Y => - \un3_de_ren1[120]\); - - un2_rstn_5_RNI97F2T5 : NOR3C - port map(A => ldbp2_2_RNIFB78T1, B => m21_0, C => N_39, Y - => m21_2); - - \r.e.shcnt_RNI378QA[2]\ : MX2C - port map(A => \shiftin_11[14]\, B => \shiftin_11[10]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[10]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I26_G0N : NOR2B - port map(A => \un1_iu0_6[25]\, B => \data_0[25]\, Y => - N472_1); - - \r.m.dci.size[0]\ : DFN1E0 - port map(D => \size[0]\, CLK => lclk_c, E => holdn, Q => - \size_1[0]\); - - \r.f.pc_RNO_7[23]\ : MX2 - port map(A => \fpc[23]\, B => \tba[11]\, S => rstate_6314_d, - Y => \xc_trap_address[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I117_Y_0\ : OA1 - port map(A => \dpc[12]\, B => \inst_0[10]\, C => N392, Y - => ADD_30x30_fast_I117_Y_0); - - \r.f.pc_RNO_2[21]\ : OR2B - port map(A => I_122, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[19]\); - - \r.f.pc_RNIB8UPIA[7]\ : OR3C - port map(A => \npc_iv_1[7]\, B => \npc_iv_0[7]\, C => - \npc_iv_2[7]\, Y => rpc_5); - - \r.x.mexc_RNIK4QT\ : NOR2 - port map(A => mexc_0, B => N_3324, Y => \xc_vectt_1[5]\); - - \r.f.pc_RNO_3[29]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[29]\, C => - \xc_trap_address_m[29]\, Y => \pc_1_iv_0[29]\); - - \r.e.ctrl.tt_RNO_3[5]\ : NOR2A - port map(A => cp_disabled_4, B => trap_1, Y => - \tt_9_0_a3_0[5]\); - - \r.x.ctrl.pc_RNISB531[9]\ : MX2C - port map(A => \un1_p0_6[361]\, B => \pc_2[9]\, S => - s_3_sqmuxa_0, Y => N_3400); - - \r.m.result_RNIKL0O3[2]\ : NOR3C - port map(A => \d_1_iv_1[2]\, B => \d_1_iv_0[2]\, C => - \rfo_m_i[34]\, Y => \d_1_iv_3[2]\); - - \r.e.invop2_1_RNIGRG83\ : MX2C - port map(A => \un6_ex_add_res_s2[3]\, B => - \un6_ex_add_res_s0[3]\, S => invop2_1, Y => N_6642); - - \r.a.rfa2[0]\ : DFN1E0 - port map(D => \inst_0_RNI0FUM[0]\, CLK => lclk_c, E => - holdn, Q => \rfa2[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I69_Y\ : NOR2B - port map(A => N386, B => N383, Y => N486); - - \r.e.op1_RNIU5NPR2[9]\ : NOR3C - port map(A => \op1_m_0[9]\, B => \d_iv_2[9]\, C => - \aluresult_m_0[9]\, Y => \d_i[9]\); - - \r.d.inst_0_RNI703B[23]\ : AOI1B - port map(A => ldcheck1_5_i_a6_0_0, B => N_3737_1, C => - ldcheck1_0, Y => ldcheck1_1); - - \r.a.ctrl.rd_RNIAP4D1[7]\ : XA1A - port map(A => \un3_de_ren1[98]\, B => \rd[7]\, C => - un2_rs1_1_i, Y => un2_rs1_NE_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I248_Y : OR2 - port map(A => I248_un1_Y, B => N666_0, Y => N811_0); - - \r.x.dci.SIGNED_RNIG9LI9C\ : OR3 - port map(A => \rdata_5_m_9[8]\, B => \rdata_13_m_9[8]\, C - => \data_0_1_1[16]\, Y => \data_0_1_4[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I267_Y_0\ : XOR2 - port map(A => ADD_30x30_fast_I267_Y_0_0, B => N610, Y => - \tmp[9]\); - - \r.a.ctrl.inst[12]\ : DFN1E0 - port map(D => \inst_0[12]\, CLK => lclk_c, E => holdn, Q - => \inst[12]\); - - \r.e.op1_RNO[1]\ : MX2 - port map(A => \d[1]\, B => \d[2]\, S => N_227_0, Y => - \aop1[1]\); - - \r.x.rstate_0_RNI75KE2[0]\ : MX2C - port map(A => N_3415, B => \xc_result[24]\, S => - \rstate_0[0]\, Y => \wdata[24]\); - - \r.m.ctrl.inst_RNIB3AB3[30]\ : NOR2 - port map(A => annul_3, B => trap63, Y => iflush_4); - - \r.a.nobp_RNIM7G012\ : AO1C - port map(A => inhibit_current, B => ldlock, C => - annul_current_0, Y => annul_current); - - \r.e.op1[28]\ : DFN1E0 - port map(D => \aop1[28]\, CLK => lclk_c, E => holdn, Q => - \op1[28]\); - - \r.x.data_0_RNO_1[18]\ : NOR2A - port map(A => \data_0_0[18]\, B => ld_3, Y => - \data_0_m[18]\); - - \r.d.inst_0[18]\ : DFN1 - port map(D => \inst_0_RNO[18]\, CLK => lclk_c, Q => - \inst_0[18]\); - - \r.e.shcnt_RNIS2JO4[3]\ : MX2 - port map(A => \shiftin_8[21]\, B => \shiftin_8[13]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[13]\); - - un6_fe_npc_I_13 : XOR2 - port map(A => N_144, B => \fe_pc[5]\, Y => I_13); - - \r.f.pc_RNO_4[16]\ : MX2 - port map(A => I_84, B => N_4059, S => bpmiss_1_i_0, Y => - \pc_4[16]\); - - \r.e.shleft_0_RNIGDIM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[26]\, S => - shleft_0, Y => \shiftin_5[57]\); - - \r.e.shleft_0_RNI8NBG\ : OR2A - port map(A => \un1_iu0_6[6]\, B => shleft_0, Y => - \shiftin_5[6]\); - - \r.e.op2[29]\ : DFN1E0 - port map(D => N_313, CLK => lclk_c, E => holdn, Q => - \op2[29]\); - - \r.x.ctrl.wicc_RNIVOQU\ : NOR2A - port map(A => icc_2_sqmuxa_1, B => \rstate_d[2]\, Y => - icc_2_sqmuxa_2); - - \r.w.result_RNINJD4[25]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[25]\, - Y => \result_m_0_0[25]\); - - \r.e.op2[31]\ : DFN1E0 - port map(D => N_315, CLK => lclk_c, E => holdn, Q => - \op2[31]\); - - \r.e.ctrl.rd_RNIU7L61[0]\ : XA1C - port map(A => \rd[0]\, B => \inst_0_RNI0FUM[0]\, C => - wreg_2, Y => wreg_1_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_un1_Y : AND2 - port map(A => N811, B => ADD_33x33_fast_I264_un1_Y_0, Y => - I264_un1_Y); - - \r.m.y_RNO_0[30]\ : NOR3C - port map(A => \y_m_1[31]\, B => \y_m_0[30]\, C => - \y_iv_1[30]\, Y => \y_iv_2[30]\); - - \r.e.op2_RNO_8[19]\ : OR3B - port map(A => d29_0, B => \imm[19]\, C => \rsel2_1[0]\, Y - => \imm_m_i[19]\); - - \r.e.ctrl.rd_RNIG2T02[3]\ : XA1A - port map(A => \rd[3]\, B => \inst_0_RNI3RUM[3]\, C => - wreg_1_0, Y => wreg_1_2); - - \r.e.op2_RNO_6[14]\ : OR2B - port map(A => data2(14), B => d25_0, Y => \rfo_m_i[46]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I318_Y_0 : XOR2 - port map(A => N772_0, B => \un6_ex_add_res_s2_1[28]\, Y => - \un6_ex_add_res_s2[28]\); - - \r.e.shcnt_RNI0HEE4[3]\ : MX2 - port map(A => \shiftin_8[10]\, B => \shiftin_8[2]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0_a3\ : OR3C - port map(A => N454, B => ADD_30x30_fast_I233_Y_0_a3_0, C - => N704, Y => N_39_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I74_Y : OA1 - port map(A => \op2[10]\, B => \un1_iu0_6[10]\, C => N425_1, - Y => N533_0); - - \r.e.op2_RNO[24]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[24]\, Y => N_308); - - \r.d.inst_0[0]\ : DFN1 - port map(D => \inst_0_RNO[0]\, CLK => lclk_c, Q => - \inst_0[0]\); - - \r.e.op1[7]\ : DFN1E0 - port map(D => \aop1[7]\, CLK => lclk_c, E => holdn, Q => - \op1[7]\); - - \r.x.ctrl.inst_RNI893A1[19]\ : NOR3C - port map(A => y6_0, B => y6_0_0, C => wim_1_sqmuxa_0, Y => - y6); - - \r.f.pc_RNO_6[29]\ : MX2 - port map(A => \fpc[29]\, B => \eaddress[29]\, S => jump, Y - => N_4072); - - un6_ex_add_res_d1_ADD_33x33_fast_I262_Y_0_a3_0 : OR2A - port map(A => N502, B => N_50, Y => N_52); - - \r.m.dci.lock\ : DFN1E0 - port map(D => lock_1, CLK => lclk_c, E => holdn, Q => - lock_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I317_Y_0 : AX1B - port map(A => I264_un1_Y_1, B => ADD_33x33_fast_I264_Y_1_1, - C => ADD_33x33_fast_I317_Y_0_0, Y => - \un6_ex_add_res_s1_i[27]\); - - \r.x.result_RNIPTB25[1]\ : NOR2 - port map(A => \bpdata[1]\, B => N_3703_i, Y => - \bpdata_i_m_1[1]\); - - \r.x.rstate_RNI31F9_0[1]\ : OR2 - port map(A => \rstate[1]\, B => \rstate[0]\, Y => - \rstate_d[2]\); - - \r.e.shleft_0_RNID9IM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[16]\, S => - shleft_0, Y => \shiftin_5[47]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I57_Y : MIN3 - port map(A => \data_0_0[18]\, B => \un1_iu0_6[18]\, C => - N448_1, Y => N516_1); - - \r.x.rstate_RNITMC12[0]\ : MX2C - port map(A => N_3402, B => \xc_result[11]\, S => - \rstate[0]\, Y => \wdata[11]\); - - \r.f.pc_RNI969ADB[8]\ : OR3C - port map(A => \npc_iv_1[8]\, B => \npc_iv_0[8]\, C => - \npc_iv_2[8]\, Y => rpc_6); - - \r.d.inst_0_RNI1423[21]\ : OR2 - port map(A => \inst_0_0[22]\, B => \inst_0_0[21]\, Y => - N_122_1); - - \r.a.rfa1_RNIO0FF1[5]\ : MX2 - port map(A => \un3_de_ren1[96]\, B => \rfa1[5]\, S => holdn, - Y => raddr1(5)); - - \r.e.aluop_0_RNIRK0Q5[0]\ : MX2C - port map(A => N_3581, B => N_3645, S => \aluop_0[0]\, Y => - \logicout[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I132_Y : OR2B - port map(A => N533_0, B => N529_1, Y => N595_2); - - \r.e.jmpl_RNIEH6CF1\ : AOI1B - port map(A => \shiftin_17[16]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[15]\, Y => \aluresult_1_iv_7[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I204_Y : AO1 - port map(A => N616_0, B => N609_0, C => N608_1, Y => N674_0); - - \r.w.result_RNIKGV6[2]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[2]\, - Y => \result_m_0_0[2]\); - - \r.w.s.y_RNO[25]\ : MX2 - port map(A => \y_1[25]\, B => \result_0[25]\, S => N_481_0, - Y => N_3789); - - \r.e.jmpl_RNIRC5C_0\ : OR2 - port map(A => jmpl, B => aluresult12, Y => - aluresult_0_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I155_Y\ : NOR3C - port map(A => N462, B => N_14, C => N529, Y => N581); - - \r.x.data_0_RNO_0[5]\ : AND2 - port map(A => \dco_m_i[117]\, B => \data_0_1_1_iv_1[5]\, Y - => \data_0_1_1_iv_2[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I8_G0N : NOR2B - port map(A => \un1_iu0_6[7]\, B => \op2[7]\, Y => N418_1); - - \r.w.result_RNIQ52L[17]\ : AOI1B - port map(A => \un1_p0_6[369]\, B => d14_0, C => - \result_m_0_0[17]\, Y => \d_iv_0[17]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I28_P0N : OR2 - port map(A => \un1_iu0_6[27]\, B => \op2[27]\, Y => N479_2); - - \r.d.inst_0_RNIAJPI3[3]\ : NOR2B - port map(A => un1_rs1_2, B => un1_rs1_1, Y => un1_rs1); - - \r.m.ctrl.inst_RNI4D1E[19]\ : OR2 - port map(A => \inst_3[19]\, B => \inst_3[20]\, Y => - trap54_1517_0); - - \r.w.s.y_RNO[28]\ : MX2 - port map(A => \y_2[28]\, B => \result_0[28]\, S => N_481, Y - => N_3792); - - \r.d.pc_RNI06HB4[25]\ : MX2 - port map(A => \dpc[25]\, B => \fpc[25]\, S => ra_bpmiss_1, - Y => N_3902); - - \r.x.data_0_RNO_0[0]\ : NOR3C - port map(A => \data_0_1_1_iv_0[0]\, B => \dco_m_i[120]\, C - => \dco_m_i[112]\, Y => \data_0_1_1_iv_2[0]\); - - \r.e.ldbp2_2_RNIBLQ7L1\ : MX2C - port map(A => \un6_ex_add_res_s1_i[15]\, B => N_6634, S => - ldbp2_2, Y => \eaddress[14]\); - - \r.d.cnt[1]\ : DFN1 - port map(D => \cnt_RNO[1]\, CLK => lclk_c, Q => \cnt_0[1]\); - - \r.x.result_RNILNKU5[6]\ : OR2B - port map(A => \bpdata[6]\, B => N_3957, Y => \bpdata_m[6]\); - - \r.e.op1_RNI9OMO6[21]\ : AO1A - port map(A => \un1_iu0_6[21]\, B => edata_3_sqmuxa_0, C => - \edata2_0_iv_0[21]\, Y => \edata2_0_iv_1[21]\); - - \r.e.invop2_1_RNI58E2J1\ : MX2C - port map(A => \un6_ex_add_res_s2[18]\, B => - \un6_ex_add_res_s0[18]\, S => invop2_1, Y => N_6637); - - \r.e.op2_RNIM7MB1_0[12]\ : OR2 - port map(A => \un1_iu0_6[12]\, B => \un1_iu0_5[78]\, Y => - \logicout_3[12]\); - - \r.a.ctrl.wreg_RNO\ : NOR2 - port map(A => write_reg, B => ctrl_annul_i, Y => wreg_1_11); - - \r.e.aluop_1_RNI0DNN[1]\ : AXOI4 - port map(A => \aluop_0[2]\, B => \un1_iu0_5[90]\, C => - \aluop_1[1]\, Y => \logicout_5_0_i_0_tz[24]\); - - \r.m.y_RNO_3[21]\ : AOI1B - port map(A => \y[21]\, B => y08_0, C => \y_m_0[22]\, Y => - \y_iv_0[21]\); - - \r.e.op2_RNO_1[11]\ : OR2B - port map(A => \op1[11]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[11]\); - - \r.a.imm_RNO[14]\ : MX2 - port map(A => \inst_0_RNI4VUM[4]\, B => \un1_p0_6_0[51]\, S - => call_hold5_0, Y => \un3_de_ren1[132]\); - - \r.e.op1_RNO[19]\ : MX2C - port map(A => \d_i[19]\, B => \d_i[20]\, S => N_227_0, Y - => \aop1[19]\); - - \r.x.result_RNIDC6E[10]\ : MX2 - port map(A => \result[10]\, B => \data_0[10]\, S => ld_4, Y - => \un1_p0_6[362]\); - - \r.x.data_0_RNO_2[5]\ : AND2 - port map(A => \data_0_1_1_iv_0[5]\, B => \dco_m_i[125]\, Y - => \data_0_1_1_iv_1[5]\); - - \r.f.pc_RNO_0[10]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[10]\, C => - \pc_1_iv_0[10]\, Y => \pc_1_iv_1[10]\); - - \r.e.invop2_1\ : DFN1E0 - port map(D => N_6680, CLK => lclk_c, E => holdn, Q => - invop2_1); - - un6_fe_npc_I_72 : NOR2B - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y - => N_101); - - un6_ex_add_res_d1_ADD_33x33_fast_I268_Y_0 : AOI1 - port map(A => N658_0, B => N643_0, C => N642_0, Y => - ADD_33x33_fast_I268_Y_0_0); - - \r.e.et_RNIT1STD\ : NOR3C - port map(A => \aluresult_1_iv_4[5]\, B => - \aluresult_1_iv_3[5]\, C => \logicout_m_0[5]\, Y => - \aluresult_1_iv_6[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I93_Y : MAJ3 - port map(A => \data_0[0]\, B => \un1_iu0_6[0]\, C => alucin, - Y => N552_1); - - \r.w.s.y_RNO_0[1]\ : NOR2A - port map(A => N_481, B => \result_0[1]\, Y => N_399); - - \r.e.shcnt_RNI0710C[2]\ : MX2C - port map(A => \shiftin_11[19]\, B => \shiftin_11[15]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[15]\); - - \r.e.ctrl.inst_RNIJ3DK[26]\ : NOR2A - port map(A => N_482, B => \inst_1[26]\, Y => - ex_bpmiss_1_0_a5_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I171_Y\ : NOR2 - port map(A => N545, B => N537, Y => N597); - - un6_ex_add_res_d1_ADD_33x33_fast_I89_Y : MAJ3 - port map(A => \op2[2]\, B => \un1_iu0_6[2]\, C => N400_0, Y - => N548); - - aluresult_11_sqmuxa_5_RNIQJG41_0 : NOR3C - port map(A => aluresult_12_sqmuxa_0, B => - aluresult_12_sqmuxa_4, C => aluresult_12_sqmuxa_5, Y => - aluresult_12_sqmuxa_0_0); - - \r.e.shcnt_RNIID7HC[2]\ : MX2C - port map(A => \shiftin_11[25]\, B => \shiftin_11[21]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[21]\); - - \r.x.rstate_0_RNIVO082[0]\ : MX2C - port map(A => N_3398, B => \xc_result[7]\, S => - \rstate_0[0]\, Y => \wdata[7]\); - - \r.a.rsel1_RNI4HMVS1[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[1]\, Y => - \aluresult_m_0[1]\); - - \r.x.ctrl.wreg_RNI1S09\ : NOR2A - port map(A => wreg, B => annul_0, Y => bpdata6_0); - - \r.w.result[23]\ : DFN1E0 - port map(D => \wdata[23]\, CLK => lclk_c, E => holdn, Q => - \result_0[23]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I245_un1_Y : NOR3A - port map(A => N676, B => N595, C => N603_i, Y => I245_un1_Y); - - \r.e.op2_RNO_8[16]\ : OR3B - port map(A => d29_0, B => \imm[16]\, C => \rsel2_1[0]\, Y - => \imm_m_i[16]\); - - \r.a.ctrl.pc[19]\ : DFN1E0 - port map(D => \dpc[19]\, CLK => lclk_c, E => holdn, Q => - \pc_3[19]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I294_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[3]\, B => \data_0[3]\, Y => - \un6_ex_add_res_s2_1[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I103_un1_Y : NOR3C - port map(A => N473_2, B => N476_2, C => N504_0, Y => - I103_un1_Y); - - \r.e.shcnt_RNIV9OHL[1]\ : MX2C - port map(A => \shiftin_14[11]\, B => \shiftin_14[9]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[9]\); - - \r.f.pc_RNO_4[26]\ : MX2 - port map(A => I_166, B => N_4069, S => bpmiss_1_i_0, Y => - \pc_4[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I1_P0N : AO1A - port map(A => ldbp1_0, B => \op1[0]\, C => \data_0[0]\, Y - => N398_1); - - un2_rstn_5_0_0_RNIN7DHU5 : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[10]\, C => - \tmp_m[10]\, Y => \npc_iv_0[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I49_Y : MAJ3 - port map(A => \op2[22]\, B => \un1_iu0_6[22]\, C => N460, Y - => N508); - - \r.f.pc_RNIJNFPJ[7]\ : MX2B - port map(A => \fpc[7]\, B => \eaddress[7]\, S => jump, Y - => N_4050); - - un6_ex_add_res_d1_ADD_33x33_fast_I28_G0N : NOR2B - port map(A => \un1_iu0_6[27]\, B => \op2[27]\, Y => N478); - - \r.w.s.tba_RNIGB5BK[17]\ : NOR3C - port map(A => \bpdata_m_2[5]\, B => \aluresult_1_iv_3[29]\, - C => \aluresult_1_iv_4[29]\, Y => \aluresult_1_iv_6[29]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I70_Y : OA1 - port map(A => \data_0_2[12]\, B => \un1_iu0_6[12]\, C => - N431_2, Y => N529_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I22_G0N : NOR2B - port map(A => \un1_iu0_6[21]\, B => \op2[21]\, Y => N460); - - \r.f.pc_RNIHAASL9[6]\ : OR2 - port map(A => \pc_RNI8CM4[6]\, B => N_22, Y => N_28); - - \r.f.pc_RNO_1[28]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[28]\, C => - \pc_1_iv_0[28]\, Y => \pc_1_iv_1[28]\); - - \r.d.inst_0[25]\ : DFN1 - port map(D => \inst_0_RNO[25]\, CLK => lclk_c, Q => - \inst_0[25]\); - - un6_fe_npc_I_8 : NOR2B - port map(A => \fe_pc[3]\, B => \fe_pc[2]\, Y => N_147); - - \r.w.s.dwt_RNO_1\ : NOR3B - port map(A => dwt_1_sqmuxa_3, B => xc_wreg_0_sqmuxa, C => - y_0_sqmuxa_1, Y => dwt_1_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I93_Y : MAJ3 - port map(A => \op2[0]\, B => \un1_iu0_6[0]\, C => alucin, Y - => N552_0); - - \r.w.result_RNIOJD4[26]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => - \result_0[26]\, Y => \result_m_0_0[26]\); - - \r.m.dci.size_RNO[0]\ : NOR3 - port map(A => \size_0[0]\, B => N_3757, C => N_3755, Y => - \size[0]\); - - \r.x.npc_0_RNIDNE41[0]\ : MX2C - port map(A => N_3218, B => N_3248, S => \npc_0[0]\, Y => - \xc_result[7]\); - - \r.e.ctrl.pc_RNI85K11[22]\ : OR2B - port map(A => \pc_2[22]\, B => jmpl_4, Y => \cpi_m[167]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I119_Y : OAI1 - port map(A => N517_1, B => N520_2, C => N516_1, Y => N582_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I85_Y : MAJ3 - port map(A => \op2[4]\, B => \un1_iu0_6[4]\, C => N406_0, Y - => N544_1); - - \r.a.imm[4]\ : DFN1E0 - port map(D => \un3_de_ren1[122]\, CLK => lclk_c, E => holdn, - Q => \imm[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I27_G0N : NOR2A - port map(A => \un1_iu0_6[26]\, B => \data_0[26]\, Y => - N475_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I264_Y_1 : NOR3B - port map(A => I165_un1_Y_0, B => I221_un1_Y, C => N568_1, Y - => ADD_33x33_fast_I264_Y_1_0); - - \r.m.y_RNIVTO71[18]\ : OR2B - port map(A => \y_1[18]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[18]\); - - un6_fe_npc_I_118 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[13]\); - - \r.a.rfa1_RNI69T01[1]\ : MX2 - port map(A => \un3_de_ren1[92]\, B => \rfa1[1]\, S => holdn, - Y => raddr1(1)); - - \r.a.imm[19]\ : DFN1E0 - port map(D => \un3_de_ren1[137]\, CLK => lclk_c, E => holdn, - Q => \imm[19]\); - - un6_fe_npc_I_122 : XOR2 - port map(A => N_66, B => \fe_pc[21]\, Y => I_122); - - \r.e.aluop_RNIEE547[0]\ : OR2B - port map(A => \logicout[12]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[12]\); - - \r.a.ctrl.rd_RNI2B5Q4[0]\ : NOR3C - port map(A => un1_de_ren1_NE_1, B => un1_de_ren1_NE_0, C - => \rd_RNIMP6H1[7]\, Y => un1_de_ren1_NE_3); - - \r.x.y[2]\ : DFN1E0 - port map(D => \y_0[2]\, CLK => lclk_c, E => holdn, Q => - \y_2[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I45_Y : OR2 - port map(A => N469, B => I45_un1_Y, Y => N504); - - \r.e.op2[12]\ : DFN1E0 - port map(D => N_296, CLK => lclk_c, E => holdn, Q => - \op2[12]\); - - \r.e.ctrl.inst[9]\ : DFN1E0 - port map(D => \inst[9]\, CLK => lclk_c, E => holdn, Q => - \inst_1[9]\); - - \r.m.y_RNO_1[29]\ : OR2B - port map(A => \y[30]\, B => mulstep_1, Y => N_419); - - \r.m.ctrl.annul_RNI69JJ\ : OR3A - port map(A => xc_wreg9, B => annul_5, C => \rstate[1]\, Y - => annul_1tt_N_7); - - \r.a.rsel1_0_RNIPS7M2[2]\ : OR2B - port map(A => data1(1), B => d11, Y => \rfo_m[1]\); - - \r.x.result_RNI4VED[26]\ : MX2 - port map(A => \result[26]\, B => \data_0[26]\, S => ld_0, Y - => \un1_p0_6[378]\); - - \r.e.aluop_0_RNIKHN3[0]\ : NOR2 - port map(A => \aluop_0[2]\, B => \aluop_0[0]\, Y => - logicout19_0); - - \r.a.ctrl.inst_RNIJ02S_1[21]\ : OR2A - port map(A => N_207, B => N_492, Y => - un1_illegal_inst11_2_0_a5_0); - - \r.a.ctrl.inst_RNIIK1S[30]\ : OR3B - port map(A => \inst_1[24]\, B => N_202, C => \inst[30]\, Y - => N_454); - - un6_ex_add_res_d0_ADD_33x33_fast_I69_Y : AO13 - port map(A => N430_0, B => \un1_iu0_6[12]\, C => - \data_0_2[12]\, Y => N528_0); - - \r.e.ctrl.tt_RNO_0[0]\ : OR2B - port map(A => tt_9_0_1862_0, B => illegal_inst_7_i_0, Y => - \tt_RNO_0[0]\); - - \r.m.icc_RNIJ2RD1[3]\ : AOI1B - port map(A => ex_bpmiss_1_0_a5_2_1_0, B => N_248, C => - ex_bpmiss_1_0_a5_4_1, Y => ex_bpmiss_1_0_2_tz_0); - - \r.x.data_0[13]\ : DFN1E0 - port map(D => \data_0_1[13]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[13]\); - - \r.x.ctrl.pc_RNIK7AE[9]\ : MX2 - port map(A => \pc_2[9]\, B => \pc[9]\, S => \npc_0[1]\, Y - => N_3220); - - \r.e.op1_RNIRH0G6[29]\ : NOR3C - port map(A => \ex_op1_i_m[29]\, B => \op1_RNI67OF[29]\, C - => \bpdata_i_m[29]\, Y => \edata2_iv_1[29]\); - - \r.a.ctrl.inst_RNIEC1L[23]\ : OR2A - port map(A => \inst_1[23]\, B => N_203, Y => N_260); - - \r.x.npc[1]\ : DFN1E0 - port map(D => \npc_1_0[1]\, CLK => lclk_c, E => holdn, Q - => \npc[1]\); - - \r.m.ctrl.pc_RNI57AE[9]\ : MX2 - port map(A => \pc_3[9]\, B => \pc_0[9]\, S => \npc_0[1]\, Y - => N_3250); - - \r.e.op2_RNO_1[28]\ : OR2B - port map(A => \op1[28]\, B => un14_casaen_s1, Y => - \op1_m_i[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_a3_1 : NAND2 - port map(A => N401, B => ADD_33x33_fast_I206_Y_0_a3_1_0, Y - => N_57_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I43_Y : AO13 - port map(A => N469_1, B => \un1_iu0_6[25]\, C => - \data_0[25]\, Y => N502_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I26_G0N\ : NOR2B - port map(A => \inst_0_1[28]\, B => \dpc[28]\, Y => N436_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I3_G0N : OA1 - port map(A => \op1[2]\, B => ldbp1_2, C => \data_0[2]\, Y - => N403_2); - - \r.m.ctrl.inst_RNI0P0E[20]\ : OR2A - port map(A => \inst_0[24]\, B => \inst_3[20]\, Y => - trap_0_sqmuxa_1_2_i); - - \r.e.jmpl_RNILGINV3\ : OR3C - port map(A => \aluresult_1_iv_8[14]\, B => - \shiftin_17_m_0[14]\, C => \un6_ex_add_res_m[15]\, Y => - \aluresult[14]\); - - \r.f.pc[6]\ : DFN1E0 - port map(D => N_22, CLK => lclk_c, E => holdn, Q => - \fpc[6]\); - - \r.x.result_RNI5SAB3[8]\ : MX2 - port map(A => \un1_iu0_6[8]\, B => \un1_p0_6[360]\, S => - bpdata6_0_0, Y => \bpdata[8]\); - - un2_rstn_5_RNIV6DND4 : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[7]\, C => - \tmp_m[7]\, Y => \npc_iv_0[7]\); - - \r.e.op2_RNINKB71[29]\ : OR2A - port map(A => \un1_iu0_5[95]\, B => \un1_iu0_6[29]\, Y => - \logicout_4[29]\); - - \comb.op_mux.d_1_iv_RNO_6[29]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[381]\, - Y => \cpi_m_i[381]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I67_un1_Y : NOR3B - port map(A => \un1_iu0_6[12]\, B => N437, C => - \data_0_2[12]\, Y => I67_un1_Y); - - \r.x.data_0_RNO_1[3]\ : OA1A - port map(A => \data_0[3]\, B => ld_0_0, C => \dco_m_i[107]\, - Y => \data_0_1_1_iv_0[3]\); - - \r.x.data_0_RNO_1[0]\ : AOI1B - port map(A => rdata_2_sqmuxa, B => data_0_0_8, C => - \data_0_m_i[0]\, Y => \data_0_1_1_iv_0[0]\); - - \r.d.inst_0[12]\ : DFN1 - port map(D => \inst_0_0_0_RNI7TVIO2[12]\, CLK => lclk_c, Q - => \inst_0[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I232_Y_0\ : AOI1B - port map(A => \inst_0_1[30]\, B => \dpc[30]\, C => - ADD_30x30_fast_I30_un1_Y, Y => ADD_30x30_fast_I232_Y_0); - - \r.e.op2_RNIENLB1_0[10]\ : OR2 - port map(A => \un1_iu0_6[10]\, B => \un1_iu0_5[76]\, Y => - \logicout_3[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I24_P0N : OR2 - port map(A => \un1_iu0_6[23]\, B => \op2[23]\, Y => N467_0); - - \r.x.ctrl.rd_RNIFVH6[2]\ : XNOR2 - port map(A => \rd_3[2]\, B => \rd_1[2]\, Y => rd_2_i_0); - - \r.a.rfa2_RNIB7461[2]\ : MX2 - port map(A => \inst_0_RNI2NUM[2]\, B => \rfa2[2]\, S => - holdn, Y => raddr2(2)); - - \r.x.ctrl.pc_RNIVPN9[18]\ : MX2 - port map(A => \pc_2[18]\, B => \pc_0[18]\, S => \npc[1]\, Y - => N_3229); - - un6_ex_add_res_d1_ADD_33x33_fast_I237_un1_Y : NOR2B - port map(A => N666_1, B => N651_1, Y => I237_un1_Y_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I314_Y_0_1 : XOR2 - port map(A => \data_0[23]\, B => \un1_iu0_6[23]\, Y => - \un6_ex_add_res_s2_1[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I65_Y : AO13 - port map(A => N436_1, B => \un1_iu0_6[14]\, C => - \data_0[14]\, Y => N524_0); - - \r.w.s.wim_RNIISJV2[3]\ : NOR2B - port map(A => aluresult_8_sqmuxa_i, B => \wim_m[3]\, Y => - \aluresult_1_iv_0[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_un1_Y : NAND2 - port map(A => N814, B => ADD_33x33_fast_I265_un1_Y_0, Y => - I265_un1_Y_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I7_G0N : NOR2B - port map(A => \un1_iu0_6[6]\, B => \op2[6]\, Y => N415_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_un1_Y_0\ : NOR2B - port map(A => N589, B => N573, Y => - ADD_30x30_fast_I235_un1_Y_0); - - \r.x.y_RNI0QAM[0]\ : OR3A - port map(A => \y_2[0]\, B => wy_3, C => wy_1_0_1, Y => - N_465); - - \r.x.rstate_RNIORDC2[0]\ : MX2C - port map(A => N_3408, B => \xc_result[17]\, S => - \rstate[0]\, Y => \wdata[17]\); - - \r.m.y[25]\ : DFN1E0 - port map(D => \y_0[25]\, CLK => lclk_c, E => holdn, Q => - \y_2[25]\); - - \r.e.shleft_0_RNI5LHM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[20]\, S => - shleft_0, Y => \shiftin_5[51]\); - - \r.e.jmpl_RNI2ODQV\ : OR2B - port map(A => \shiftin_17[31]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[31]\); - - \r.f.pc_RNO_5[28]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[28]\, Y => \xc_trap_address_m[28]\); - - \r.e.jmpl_RNIRFSGR_0\ : OR2B - port map(A => \shiftin_17[21]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[21]\); - - \rp.error_RNO\ : OA1 - port map(A => error, B => error_1_sqmuxa, C => rst, Y => - error_RNO); - - \r.w.s.tba_RNI3K758[18]\ : NOR3C - port map(A => \aluresult_1_iv_1[30]\, B => \tba_m[18]\, C - => \bpdata_m_2[6]\, Y => \aluresult_1_iv_5[30]\); - - \r.f.pc_RNIDF56[2]\ : NOR2A - port map(A => \fpc[2]\, B => rstate_6314_d_0, Y => - \xc_trap_address_m_0[2]\); - - \r.e.alusel_RNIRC5C[0]\ : OR3B - port map(A => \alusel[0]\, B => \alusel[1]\, C => jmpl, Y - => aluresult_9_sqmuxa_1); - - \r.d.pv_RNI83B6\ : NOR2B - port map(A => pv, B => annul_2, Y => un2_exbpmiss_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0_a3_1\ : AO1C - port map(A => N433, B => I36_un1_Y_i, C => - ADD_30x30_fast_I233_Y_0_a3_0, Y => N_41); - - \r.e.shleft_1_RNIQDPK3\ : MX2 - port map(A => \shiftin_5[58]\, B => \shiftin_5[42]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[42]\); - - \r.m.y[30]\ : DFN1E0 - port map(D => \y_1[30]\, CLK => lclk_c, E => holdn, Q => - \y[30]\); - - \r.e.op2_RNO[14]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[14]\, Y => N_298); - - un6_ex_add_res_d1_ADD_33x33_fast_I122_Y_0 : OA1 - port map(A => \op2[14]\, B => \un1_iu0_6[14]\, C => N443, Y - => ADD_33x33_fast_I122_Y_0); - - \r.x.data_0_RNO_0[3]\ : NOR3C - port map(A => \data_0_1_1_iv_0[3]\, B => \dco_m_i[123]\, C - => \dco_m_i[115]\, Y => \data_0_1_1_iv_2[3]\); - - \r.e.aluop_0_RNI21JD1[1]\ : XOR3 - port map(A => \un1_iu0_6[16]\, B => \aluop_0[1]\, C => - \un1_iu0_5[82]\, Y => N_6886); - - un6_ex_add_res_d2_ADD_33x33_fast_I21_G0N : OA1 - port map(A => \op1[20]\, B => ldbp1_4, C => \data_0_2[20]\, - Y => N457_0); - - \r.m.result_RNO[13]\ : MX2 - port map(A => \aluresult[13]\, B => \op1[13]\, S => - un17_casaen_0_2, Y => \eres2[13]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I267_un1_Y : OR3C - port map(A => N641, B => N657, C => N672, Y => I267_un1_Y_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_o3 : AOI1 - port map(A => N614_0, B => N407, C => N406_0, Y => N678_i); - - \r.m.ctrl.trap_RNIF2S741\ : NOR2A - port map(A => trap2, B => annul_RNIPFOQ, Y => un1_annul); - - \r.e.aluop_0_RNIH5791[2]\ : XA1 - port map(A => \un1_iu0_5[94]\, B => \aluop_0[2]\, C => - \un1_iu0_6[28]\, Y => N_3555); - - \r.a.ctrl.inst_RNIF2TK1[26]\ : MX2C - port map(A => N_3339, B => N_3340, S => \inst_2[26]\, Y => - N_3341); - - \r.e.op2_RNO_6[11]\ : OR2B - port map(A => data2(11), B => d25_0, Y => \rfo_m_i[43]\); - - \r.d.annul_RNIVCQHS1_0\ : NOR2 - port map(A => un2_rstn_4_0, B => un2_rstn_5_2, Y => - un2_rstn_4_0_0); - - \r.m.ctrl.pc[19]\ : DFN1E0 - port map(D => \pc[19]\, CLK => lclk_c, E => holdn, Q => - \pc_2[19]\); - - \r.e.jmpl_RNI85S3N_0\ : OR2B - port map(A => \shiftin_17[10]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I264_un1_Y : NOR3B - port map(A => N651_1, B => N811_1, C => N635_1, Y => - I264_un1_Y_1); - - \r.e.op2_RNIPS4F_0[4]\ : OR2 - port map(A => \un1_iu0_6[4]\, B => \un1_iu0_5[70]\, Y => - \logicout_3[4]\); - - \r.e.op1_RNINI8G[30]\ : OR2B - port map(A => \op1[30]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[30]\); - - \r.w.result_RNIB8P1[31]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[31]\, Y - => \result_m_0[31]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I269_Y_0_0\ : XOR2 - port map(A => \dpc[11]\, B => \inst_0[9]\, Y => - ADD_30x30_fast_I269_Y_0_0); - - \r.e.ctrl.inst_RNIIULP85[22]\ : AO1B - port map(A => un1_icc_2_sqmuxa_1, B => un3_notag, C => - \icc_2[1]\, Y => \icc_2_m[1]\); - - \r.m.result[16]\ : DFN1E0 - port map(D => \eres2[16]\, CLK => lclk_c, E => holdn, Q => - \maddress[16]\); - - \r.e.op1_RNIK24U1[5]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[5]\, C => - \ex_op1_i_m[5]\, Y => \edata2_0_iv_0[5]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I16_P0N : OR3A - port map(A => \data_0_2[15]\, B => \op1[15]\, C => ldbp1_3, - Y => N443_0); - - \r.x.dci.SIGNED_RNI32NV72\ : NOR2B - port map(A => \rdata_13[8]\, B => rdata_2_sqmuxa, Y => - \rdata_13_m[8]\); - - \r.d.inst_0_RNO_0[16]\ : MX2 - port map(A => data_0_0_16, B => \inst_0[16]\, S => - mexc_1_sqmuxa_1_0, Y => N_4616); - - un6_ex_add_res_d0_ADD_33x33_fast_I4_P0N : OR3A - port map(A => \data_0[3]\, B => \op1[3]\, C => ldbp1_4, Y - => N407_2); - - \r.f.pc_RNO_0[16]\ : NAND2 - port map(A => \tmp[16]\, B => un2_rstn_5_0, Y => - \tmp_m[16]\); - - \r.m.result_RNI9T3I3[7]\ : NOR3C - port map(A => \d_iv_0[7]\, B => \result_m_0[7]\, C => - \rfo_m[7]\, Y => \d_iv_2[7]\); - - \r.e.invop2_1_RNIUM5NA\ : MX2 - port map(A => \un6_ex_add_res_s2[9]\, B => - \un6_ex_add_res_s0[9]\, S => invop2_1, Y => N_6555); - - \r.m.result_RNO[6]\ : MX2 - port map(A => \aluresult[6]\, B => \op1[6]\, S => - un17_casaen_0_2, Y => \eres2[6]\); - - \r.x.data_0_RNO_2[9]\ : NOR2A - port map(A => \data_0[9]\, B => ld_3, Y => \data_0_m[9]\); - - \r.f.pc_RNO_4[30]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[30]\, Y => \xc_trap_address_m[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I130_Y : AND2 - port map(A => N527, B => ADD_33x33_fast_I130_Y_0, Y => N593); - - \r.m.result_RNIVU7B3[16]\ : NOR3C - port map(A => \d_iv_0[16]\, B => \result_m_0[16]\, C => - \rfo_m[16]\, Y => \d_iv_2[16]\); - - \r.e.op1_RNI064B2[25]\ : OA1A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[25]\, C => - \op1_RNI2NNF[25]\, Y => \edata2_iv_0[25]\); - - \r.e.invop2_1_RNIHGG322\ : MX2C - port map(A => \un6_ex_add_res_s2[22]\, B => - \un6_ex_add_res_s0[22]\, S => invop2_1, Y => N_6568); - - un6_fe_npc_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \fe_pc[11]\, C => - \fe_pc[12]\, Y => N_106); - - un54_ra_I_1 : AND2 - port map(A => \ncwp[0]\, B => N_79, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - \r.m.dci.read\ : DFN1E0 - port map(D => read, CLK => lclk_c, E => holdn, Q => read_1); - - \r.d.pc_RNISJBA4[5]\ : MX2 - port map(A => \dpc[5]\, B => \fpc[5]\, S => ra_bpmiss_1, Y - => N_3882); - - \r.x.dci.SIGNED_RNII78BD3\ : NOR2B - port map(A => \rdata_13[8]\, B => N_3480, Y => - \rdata_13_m_9[8]\); - - \r.a.ctrl.inst_RNIJG131[20]\ : NOR3A - port map(A => \inst_2[20]\, B => N_201, C => inst_9_3, Y - => aluop_1_1_0_a5_0_0); - - \r.e.op2_RNINKB71_0[29]\ : OR2 - port map(A => \un1_iu0_6[29]\, B => \un1_iu0_5[95]\, Y => - \logicout_3[29]\); - - \r.m.y_RNI3J9F[1]\ : OR2B - port map(A => \y[1]\, B => mulstep_1, Y => N_468); - - \r.e.ctrl.wicc_RNI2M0DB8\ : MX2 - port map(A => N_4188, B => N_4178, S => wicc_2, Y => - \icco[3]\); - - \r.e.ctrl.pc_RNI5TJ11[10]\ : OR2B - port map(A => \pc_0[10]\, B => jmpl_4, Y => \cpi_m[155]\); - - \r.w.s.tba_RNID84T9[15]\ : NOR3C - port map(A => \tba_m[15]\, B => \aluop_RNI5N3F4[1]\, C => - \bpdata_m_2[3]\, Y => \aluresult_0_iv_5[27]\); - - \r.f.pc_RNI58041[8]\ : MX2 - port map(A => \fpc[8]\, B => \xc_vectt_1[4]\, S => - rstate_6314_d_0, Y => \xc_trap_address[8]\); - - \r.e.op2_RNO_2[9]\ : OR2B - port map(A => data2(9), B => d25_0, Y => \rfo_m_i[41]\); - - \r.m.ctrl.trap_RNI1LRM8\ : OR2B - port map(A => trap_1_sqmuxa, B => trap_2_0, Y => - nullify_1_sqmuxa); - - \r.d.pc[28]\ : DFN1 - port map(D => \pc_RNO[28]\, CLK => lclk_c, Q => \dpc[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I198_Y : NOR3C - port map(A => N535_1, B => ADD_33x33_fast_I138_Y_0_0, C => - N609, Y => N667_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I25_P0N : NOR3A - port map(A => \data_0[24]\, B => \op1[24]\, C => ldbp1_4, Y - => N470_1); - - \r.e.op2_RNO[0]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[0]\, Y => N_284); - - \r.e.op1_RNIG93B2[12]\ : AO1A - port map(A => \op1[12]\, B => \un17_casaen_0_0\, C => - \ex_op1_i_m[12]\, Y => \edata2_0_iv_0[12]\); - - \r.x.result[31]\ : DFN1E0 - port map(D => \maddress[31]\, CLK => lclk_c, E => holdn, Q - => \result_0[31]\); - - \r.a.rsel2_0_RNI7V53_1[0]\ : NOR2B - port map(A => \rsel2_0[0]\, B => d26_0, Y => d26); - - \comb.misc_op.miscout140\ : OR2 - port map(A => miscout140_1, B => \aluop_0[0]\, Y => - miscout140); - - \r.d.inst_0_RNO_0[4]\ : MX2 - port map(A => data_0_2_4, B => \inst_0[4]\, S => - mexc_1_sqmuxa_1_0, Y => N_4604); - - \r.e.op1_RNI0JCR1[26]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[26]\, Y => - \ex_op1_i_m[26]\); - - un6_fe_npc_I_199 : AND2 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - Y => \DWACT_FINC_E[24]\); - - \r.f.pc_RNO_7[13]\ : MX2 - port map(A => \fpc[13]\, B => \tba[1]\, S => - rstate_6314_d_0, Y => \xc_trap_address[13]\); - - \r.d.pv_RNO_3\ : NOR2B - port map(A => un23_exbpmiss_i_0, B => un9_rabpmiss, Y => - pv_0); - - \r.x.result_RNIPK6E[23]\ : MX2 - port map(A => \result[23]\, B => \data_0[23]\, S => ld_4, Y - => \un1_p0_6[375]\); - - \r.w.s.y_RNO[3]\ : MX2 - port map(A => \y_2[3]\, B => \result_0[3]\, S => N_481_0, Y - => N_3767); - - \r.d.pc[11]\ : DFN1 - port map(D => \pc_RNO[11]\, CLK => lclk_c, Q => \dpc[11]\); - - \r.d.pc_RNO[3]\ : MX2 - port map(A => \fpc[3]\, B => \dpc[3]\, S => N_6763_i_0, Y - => \pc_RNO[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I310_Y_0_1 : XOR2 - port map(A => \op1_RNID1VH[19]\, B => \data_0[19]\, Y => - \un6_ex_add_res_s2_1[20]\); - - \r.m.result_RNI5PR73[12]\ : NOR3C - port map(A => \d_iv_0[12]\, B => \result_m_0[12]\, C => - \rfo_m[12]\, Y => \d_iv_2[12]\); - - \r.a.ctrl.inst_RNIQG231[24]\ : OR3 - port map(A => N_241, B => \inst_1[24]\, C => N_212, Y => - N_469); - - \r.x.ctrl.inst_RNI023H1[22]\ : NOR3C - port map(A => y15, B => cwp_2_sqmuxa_1, C => cwp_2_sqmuxa_2, - Y => cwp_2_sqmuxa_4); - - \r.m.y_RNO[22]\ : OR3C - port map(A => \y_iv_1[22]\, B => \y_iv_0[22]\, C => - \logicout_m[22]\, Y => \y_1[22]\); - - \r.e.shcnt_RNI9K75G[2]\ : MX2 - port map(A => \shiftin_11[38]\, B => \shiftin_11[34]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[34]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I77_Y : MAJ3 - port map(A => \data_0[8]\, B => \un1_iu0_6[8]\, C => N418, - Y => N536_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I30_P0N : OR2A - port map(A => \data_0_0[29]\, B => \un1_iu0_6[29]\, Y => - N485); - - \r.w.s.wim[5]\ : DFN1E0 - port map(D => \wim_1[5]\, CLK => lclk_c, E => holdn, Q => - \wim[5]\); - - \r.x.ctrl.pc[26]\ : DFN1E0 - port map(D => \pc_3[26]\, CLK => lclk_c, E => holdn, Q => - \pc_2[26]\); - - \r.x.ctrl.wicc_RNISFUM2\ : OA1 - port map(A => icc_0_sqmuxa_0, B => rstate_7_0, C => rst, Y - => icc_1_sqmuxa); - - \r.e.aluop_0_RNIILNS3[0]\ : OR2B - port map(A => \logicout[7]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[7]\); - - \r.w.result_RNILND4[30]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[30]\, - Y => \result_m_0_0[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I74_Y : NOR2B - port map(A => N428_0, B => N425_0, Y => N533); - - \r.e.op2_RNO_8[20]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[372]\, - Y => \cpi_m_i[372]\); - - \r.e.ldbp2_1_RNIKNA7L3\ : MX2C - port map(A => \un6_ex_add_res_s1_i[24]\, B => N_6570, S => - ldbp2_1, Y => \eaddress[23]\); - - \r.e.ctrl.pc[31]\ : DFN1E0 - port map(D => \pc_0[31]\, CLK => lclk_c, E => holdn, Q => - \pc[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I116_Y : NOR2B - port map(A => N517_0, B => N513_1, Y => N579_2); - - \r.m.y_RNI94K91[3]\ : OR2B - port map(A => \y_1[3]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[3]\); - - \r.m.y_RNI02P71[19]\ : OR2B - port map(A => \y_0[19]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[19]\); - - \r.a.imm_RNO[8]\ : NOR2B - port map(A => \inst_0[8]\, B => call_hold5, Y => - \un3_de_ren1[126]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I137_Y_0 : AO13 - port map(A => N421, B => \un1_iu0_6[9]\, C => \data_0[9]\, - Y => ADD_33x33_fast_I137_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I189_Y : OR2A - port map(A => I189_un1_Y_i, B => N592, Y => N658_1); - - \r.w.s.tba_RNI84CA1[7]\ : NAND2 - port map(A => aluresult_12_sqmuxa_0_0, B => \tba[7]\, Y => - \tba_m[7]\); - - \r.m.ctrl.ld_RNIHU879_0\ : OR2 - port map(A => ld, B => dco_i_2(132), Y => ld_0_0); - - \r.e.aluop_RNI1UQR4[2]\ : OR2B - port map(A => \bpdata[15]\, B => aluresult_5_sqmuxa, Y => - \bpdata_m_0[15]\); - - \r.e.aluop_0_RNIRDEVH[0]\ : NOR3C - port map(A => \logicout_m_0[0]\, B => \aluresult_2_iv_4[0]\, - C => \bpdata_m[0]\, Y => \aluresult_2_iv_6[0]\); - - \r.x.result[16]\ : DFN1E0 - port map(D => \maddress[16]\, CLK => lclk_c, E => holdn, Q - => \result_0[16]\); - - \r.w.s.ps_RNO\ : OR2A - port map(A => rst, B => N_4993, Y => ps_RNO); - - \r.m.y[15]\ : DFN1E0 - port map(D => \y_0[15]\, CLK => lclk_c, E => holdn, Q => - \y[15]\); - - \r.e.op2_RNIHMUD4[3]\ : AOI1B - port map(A => \un1_iu0_5[69]\, B => aluresult_7_sqmuxa_0_0, - C => \aluresult_1_iv_0[3]\, Y => \aluresult_1_iv_1[3]\); - - \r.d.inull_RNO_0\ : AO1D - port map(A => rett_1, B => de_inull_0_a3_1_0, C => jmpl_1, - Y => de_inull_0_2004_0); - - \r.d.inst_0_RNID24008[29]\ : MX2C - port map(A => un1_annul_next_1_sqmuxa_3, B => \inst_0[29]\, - S => annul_next_2_sqmuxa_1, Y => annul_next_14); - - un6_fe_npc_I_169 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \fe_pc[26]\, Y => \DWACT_FINC_E[19]\); - - \r.m.y_RNO_1[26]\ : OR2B - port map(A => \y_0[27]\, B => mulstep_0, Y => \y_m[27]\); - - \r.e.ctrl.pc[26]\ : DFN1E0 - port map(D => \pc_0[26]\, CLK => lclk_c, E => holdn, Q => - \pc[26]\); - - \r.e.op2_RNO_5[18]\ : AOI1B - port map(A => \result[18]\, B => d31, C => \imm_m_i[18]\, Y - => \d_1_iv_0[18]\); - - \r.d.pc_RNIS5HB4[23]\ : MX2 - port map(A => \dpc[23]\, B => \fpc[23]\, S => ra_bpmiss_1, - Y => N_3900); - - un6_fe_npc_I_155 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[33]\, Y => N_42); - - \r.e.shcnt_RNI98VRI[1]\ : MX2C - port map(A => \shiftin_14[2]\, B => \shiftin_14[0]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[0]\); - - \r.a.ctrl.pc_RNISBE2C[14]\ : MX2 - port map(A => \pc[14]\, B => N_3891, S => ex_bpmiss_1, Y - => \fe_pc[14]\); - - \r.a.ctrl.inst_RNI7K0E_0[21]\ : NOR2B - port map(A => \inst_2[21]\, B => \inst[22]\, Y => - illegal_inst35_4_0); - - \r.x.ctrl.inst_RNILL0E[21]\ : NOR2 - port map(A => \inst_0[22]\, B => \inst_0[21]\, Y => - wim_1_sqmuxa_0); - - \r.e.ctrl.pc_RNIA8TN2[30]\ : NOR2A - port map(A => \cpi_m[175]\, B => \aluresult_6[31]\, Y => - \aluresult_1_iv_1[30]\); - - \r.f.pc_RNO_1[21]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[21]\, C => - \pc_1_iv_0[21]\, Y => \pc_1_iv_1[21]\); - - \r.a.bp_RNIFI8U\ : OR3C - port map(A => \inst[29]\, B => bp, C => un8_op, Y => - un5_ldlock); - - \r.m.y_RNO_3[29]\ : AOI1B - port map(A => wy_1_0, B => \y_0[29]\, C => N_417, Y => - \y_iv_0_1[29]\); - - \r.e.aluop_2_RNIPRDM1[1]\ : MX2C - port map(A => N_3535, B => \logicout_3[8]\, S => - \aluop_2[1]\, Y => N_3567); - - \comb.branch_address.tmp_ADD_30x30_fast_I132_Y\ : AO1 - port map(A => N497_1, B => N494, C => - ADD_30x30_fast_I132_Y_0, Y => N552_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I103_Y : AO1A - port map(A => N501, B => N504, C => N500_1, Y => N566_0); - - un2_rstn_5_RNISAMP : NAND2 - port map(A => \tmp[2]\, B => \un2_rstn_5\, Y => \tmp_m[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I220_Y_0_o3\ : AOI1 - port map(A => N735, B => N392, C => N391, Y => N732_i); - - \r.w.s.tba[14]\ : DFN1E1 - port map(D => \result[26]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[14]\); - - \r.f.pc_RNO_6[14]\ : MX2 - port map(A => \fpc[14]\, B => \eaddress[14]\, S => jump, Y - => N_4057); - - \r.e.shcnt_RNID7Q6E[2]\ : MX2C - port map(A => \shiftin_11[30]\, B => \shiftin_11[26]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[26]\); - - \r.a.imm[15]\ : DFN1E0 - port map(D => \un3_de_ren1[133]\, CLK => lclk_c, E => holdn, - Q => \imm[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I298_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[8]\, B => N672_1, Y => - \un6_ex_add_res_s0[8]\); - - \r.a.ctrl.inst_RNI9S0E[21]\ : OR2B - port map(A => \inst_1[24]\, B => \inst_2[21]\, Y => N_203); - - \r.x.npc_RNIQQBL[0]\ : MX2C - port map(A => N_3222, B => N_3252, S => \npc[0]\, Y => - \xc_result[11]\); - - \r.e.alucin_RNO_6\ : NOR2A - port map(A => \inst[22]\, B => \inst[30]\, Y => - cin_iv_i_a5_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I179_un1_Y : NOR2B - port map(A => N590_0, B => N583_1, Y => I179_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I267_Y_0 : AOI1B - port map(A => N656_0, B => N641_0, C => N640, Y => - ADD_33x33_fast_I267_Y_0); - - \r.m.result_RNO[7]\ : MX2 - port map(A => \aluresult[7]\, B => \op1[7]\, S => - un17_casaen_0_2, Y => \eres2[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I155_un1_Y : AO1C - port map(A => N500, B => I103_un1_Y_i, C => N559, Y => - I155_un1_Y); - - \r.m.ctrl.pc_RNI4QHF[26]\ : MX2 - port map(A => \pc_3[26]\, B => \pc_0[26]\, S => \npc_1[1]\, - Y => N_3267); - - \r.e.aluop_RNIIRTL9[1]\ : OA1A - port map(A => N_3974, B => \bpdata[12]\, C => - \bpdata_m_2[4]\, Y => \aluresult_1_iv_4[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I82_Y\ : MAJ3 - port map(A => \dpc[4]\, B => \inst_0_RNI2NUM[2]\, C => N361, - Y => N499); - - \r.w.s.tba_RNIF87ON[9]\ : NOR3C - port map(A => \aluresult_1_iv_5[21]\, B => \bpdata_m_1[5]\, - C => \logicout_m_0[21]\, Y => \aluresult_1_iv_7[21]\); - - \r.f.pc_RNIRJ9HO4[10]\ : MX2 - port map(A => I_45, B => N_4053, S => bpmiss_1_i_0_0, Y => - \pc_4[10]\); - - \r.w.s.tba[9]\ : DFN1E1 - port map(D => \result_0[21]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[9]\); - - \r.e.shcnt_RNISH246[3]\ : MX2 - port map(A => \shiftin_8[28]\, B => \shiftin_8[20]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[20]\); - - \r.x.data_0[21]\ : DFN1E0 - port map(D => \data_0_1[21]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[21]\); - - \r.m.result[24]\ : DFN1E0 - port map(D => \eres2[24]\, CLK => lclk_c, E => holdn, Q => - \maddress[24]\); - - \r.e.shleft_1_RNIPS4L\ : OR2A - port map(A => \un1_iu0_6[30]\, B => shleft_1, Y => - \shiftin_5[30]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I238_Y\ : OR3C - port map(A => I202_un1_Y_i, B => ADD_30x30_fast_I238_Y_0, C - => I238_un1_Y, Y => N706); - - \r.e.ctrl.annul\ : DFN1E0 - port map(D => N_149, CLK => lclk_c, E => holdn, Q => annul); - - \r.e.aluop_RNI7L034[1]\ : NAND2 - port map(A => aluresult_4_sqmuxa, B => \bpdata[0]\, Y => - \bpdata_m_2[0]\); - - \r.d.inst_0_RNO[24]\ : NOR2B - port map(A => rst, B => N_4624, Y => \inst_0_RNO[24]\); - - \r.m.ctrl.wicc_RNO\ : NOR2A - port map(A => wicc_2, B => \un1_p0_6[0]\, Y => wicc_1_1); - - un2_rstn_5_0_0 : NOR2 - port map(A => un2_rstn_5_2, B => \un2_rstn_5_0_0\, Y => - un2_rstn_5_0); - - \r.e.op2_RNO_5[26]\ : NOR2B - port map(A => \imm_m_i[26]\, B => \result_m_i[26]\, Y => - \d_1_iv_0[26]\); - - \rp.error\ : DFN1 - port map(D => error_RNO, CLK => lclk_c, Q => error); - - \r.d.inst_0_RNI4TR42[3]\ : NOR2A - port map(A => un1_rs1_0, B => \inst_0_RNI3RUM[3]\, Y => - un1_rs1_2); - - \r.x.ctrl.rd_RNI7SGO[3]\ : NOR2B - port map(A => \rd_2[3]\, B => N_6357, Y => waddr(3)); - - \r.w.s.y[23]\ : DFN1E0 - port map(D => N_3787, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[23]\); - - \r.f.pc_RNO_2[18]\ : OR2B - port map(A => I_98, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[16]\); - - \r.x.result_RNI7KU63[9]\ : MX2 - port map(A => \un1_iu0_6[9]\, B => \un1_p0_6[361]\, S => - bpdata6_0_0, Y => \bpdata[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I191_Y : AO1D - port map(A => N602_1, B => N595, C => N594_2, Y => N660_1); - - \r.e.aluop_RNI0RJD4[1]\ : NOR2A - port map(A => edata_2_sqmuxa, B => \bpdata[23]\, Y => - \bpdata_i_m[23]\); - - \r.d.inst_0_RNI8AJ4[27]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[27]\, S => - \inst_0[30]\, Y => \inst_0_RNI8AJ4[27]\); - - \r.e.op2_RNO_1[30]\ : OR2B - port map(A => \op1[30]\, B => un14_casaen_s1, Y => - \op1_m_i[30]\); - - \r.x.ctrl.tt_RNO_1[0]\ : MX2C - port map(A => \tt_0[0]\, B => irl_0(0), S => tt_1_sqmuxa_1, - Y => N_4204); - - \r.f.pc_RNO_7[30]\ : MX2 - port map(A => \fpc[30]\, B => \tba[18]\, S => - rstate_6314_d_0, Y => \xc_trap_address[30]\); - - \r.x.laddr_RNIFVAM63[0]\ : OR3 - port map(A => rdata_3_sqmuxa, B => rdata_4_sqmuxa, C => - rdata_6_sqmuxa, Y => N_3456); - - \r.x.result_RNIPKPCK[2]\ : MX2C - port map(A => \result_0[2]\, B => N_6529, S => - cwp_1_sqmuxa_0, Y => N_3872); - - \r.e.ctrl.inst[8]\ : DFN1E0 - port map(D => \inst[8]\, CLK => lclk_c, E => holdn, Q => - \inst_1[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I17_G0N : OA1 - port map(A => \op1[16]\, B => ldbp1_4, C => \data_0[16]\, Y - => N445); - - \r.e.op1_RNIFN41T1[1]\ : MX2 - port map(A => \aluresult[1]\, B => \op1[1]\, S => - un17_casaen_0, Y => \eres2[1]\); - - \r.e.shcnt[2]\ : DFN1E0 - port map(D => N_268_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[2]\); - - \r.e.op1_RNICTUH[18]\ : MX2 - port map(A => \op1[18]\, B => \data_0_0[18]\, S => ldbp1_3, - Y => \un1_iu0_6[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I238_un1_Y\ : OR3C - port map(A => N579, B => N595_0, C => N610, Y => I238_un1_Y); - - \r.x.ctrl.pc[12]\ : DFN1E0 - port map(D => \pc_3[12]\, CLK => lclk_c, E => holdn, Q => - \pc_0[12]\); - - \r.f.pc[22]\ : DFN1E0 - port map(D => \pc_1[22]\, CLK => lclk_c, E => holdn, Q => - \fpc[22]\); - - \r.w.result_RNIP407[7]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[7]\, - Y => \result_m_0_0[7]\); - - \r.e.op2_RNIHB971[11]\ : OR2A - port map(A => \un1_iu0_5[77]\, B => \un1_iu0_6[11]\, Y => - \logicout_4[11]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I20_P0N : OR3A - port map(A => \data_0[19]\, B => \op1[19]\, C => ldbp1_0, Y - => N455_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I113_Y : AO1B - port map(A => N514_0, B => N511_0, C => - ADD_33x33_fast_I113_Y_0, Y => N576_0); - - \r.a.ctrl.inst_RNIU43A1[22]\ : NOR3 - port map(A => N_472, B => \inst[22]\, C => N_260, Y => - illegal_inst38); - - \r.x.result[4]\ : DFN1E0 - port map(D => \maddress[4]\, CLK => lclk_c, E => holdn, Q - => \result[4]\); - - \r.m.y_RNO_2[27]\ : OR2A - port map(A => \logicout[27]\, B => y14, Y => N_420); - - \comb.branch_address.tmp_ADD_30x30_fast_I114_Y\ : OR2 - port map(A => N475, B => I114_un1_Y, Y => N534); - - \r.x.data_0_RNO_0[20]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_20, Y => - \dco_m_0[116]\); - - \r.m.y_RNO_4[7]\ : OR3A - port map(A => \y_2[7]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_1[7]\); - - \r.x.ctrl.tt_RNO_0[1]\ : MX2C - port map(A => irl_0(1), B => \tt_2[1]\, S => tt_0_sqmuxa, Y - => N_4205); - - \r.f.pc_RNO_5[21]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[21]\, Y => \xc_trap_address_m[21]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I317_Y_0 : XOR2 - port map(A => N774, B => \un6_ex_add_res_s2_1[27]\, Y => - \un6_ex_add_res_s2[27]\); - - \r.x.data_0_RNO_1[11]\ : AO1A - port map(A => rdata_5_sqmuxa, B => data_0_0_27, C => - \data_0_m[11]\, Y => \data_0_1_0_iv_0[11]\); - - \r.e.ctrl.pc[3]\ : DFN1E0 - port map(D => \pc[3]\, CLK => lclk_c, E => holdn, Q => - \pc_0[3]\); - - \r.e.ymsb\ : DFN1E0 - port map(D => \d[0]\, CLK => lclk_c, E => holdn, Q => ymsb); - - \comb.branch_address.tmp_ADD_30x30_fast_I137_Y\ : OR2A - port map(A => I137_un1_Y_i, B => N499, Y => N558); - - un6_ex_add_res_d0_ADD_33x33_fast_I53_Y : AO13 - port map(A => N454_0, B => \un1_iu0_6[20]\, C => - \data_0_2[20]\, Y => N512); - - annul_current_3_sqmuxa_1 : OR2A - port map(A => un5_exbpmiss_i_0, B => call_hold7_i, Y => - \annul_current_3_sqmuxa_1\); - - \r.m.result_RNI18P1[31]\ : OR2B - port map(A => d13, B => \maddress[31]\, Y => - \result_m_0_0[31]\); - - \r.e.ctrl.pc_RNICJD92[27]\ : AOI1B - port map(A => \pc[27]\, B => jmpl_0, C => \y_m_1[27]\, Y - => \aluresult_0_iv_1[27]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I311_Y_0_0 : XOR2 - port map(A => \op2[20]\, B => \un1_iu0_6[20]\, Y => - ADD_33x33_fast_I311_Y_0_0); - - \r.e.op2[1]\ : DFN1E0 - port map(D => N_285, CLK => lclk_c, E => holdn, Q => - \op2[1]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_11\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => un2_irl); - - \r.e.aluadd_RNIMCA2F5\ : MX2C - port map(A => \logicout[20]\, B => \icc_16[0]\, S => - un3_op_i, Y => N_4175); - - \r.e.op2_RNO_0[10]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[10]\, C - => \d_1_iv_4[10]\, Y => \d_1[10]\); - - \r.x.ctrl.inst[20]\ : DFN1E0 - port map(D => \inst_3[20]\, CLK => lclk_c, E => holdn, Q - => \inst[20]\); - - \r.w.s.pil[3]\ : DFN1E0 - port map(D => \result_0[11]\, CLK => lclk_c, E => N_6699, Q - => \pil[3]\); - - \r.f.pc_RNIHO981[5]\ : MX2B - port map(A => \fpc[5]\, B => \xc_vectt_1[1]\, S => - rstate_6314_d, Y => \xc_trap_address[5]\); - - \r.e.op1[20]\ : DFN1E0 - port map(D => \aop1[20]\, CLK => lclk_c, E => holdn, Q => - \op1[20]\); - - \r.e.invop2_0_RNISJIJ\ : XNOR3 - port map(A => invop2_0, B => \un6_ex_add_res_s0_0_0[1]\, C - => \un1_iu0_6[0]\, Y => N_6640_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I266_Y_0_o3 : AO1 - port map(A => N_74_1, B => N782_0, C => N506_1, Y => N778_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I316_Y_0 : XOR2 - port map(A => N776, B => \un6_ex_add_res_s2_1[26]\, Y => - \un6_ex_add_res_s2[26]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I205_Y : OR2 - port map(A => N610_1, B => I205_un1_Y_0, Y => N676_0); - - \r.w.s.pil_RNI06V28[1]\ : NOR3C - port map(A => \pil_m[1]\, B => \aluresult_1_iv_0[9]\, C => - \bpdata_m[9]\, Y => \aluresult_1_iv_4[9]\); - - \r.x.dci.SIGNED_RNII2M614\ : AOI1B - port map(A => rdata_5_sqmuxa, B => rdata_0_sqmuxa, C => - \rdata_5[8]\, Y => \rdata_5_m_9[8]\); - - \r.x.data_0_RNIDN9E[31]\ : XOR2 - port map(A => \data_0_0[31]\, B => invop2_0, Y => N_4278); - - \r.e.aluop_RNI2SUL9[1]\ : OA1A - port map(A => N_3974, B => \bpdata[14]\, C => - \bpdata_m_2[6]\, Y => \aluresult_1_iv_5[14]\); - - \r.e.shcnt_RNIQ376K[1]\ : MX2C - port map(A => \shiftin_14[7]\, B => \shiftin_14[5]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[5]\); - - \r.m.y_RNIG37P6[22]\ : AOI1B - port map(A => \bpdata[22]\, B => aluresult_6_sqmuxa, C => - \aluresult_1_iv_1[22]\, Y => \aluresult_1_iv_3[22]\); - - \r.f.pc_RNO[23]\ : OR3C - port map(A => \tmp_m[23]\, B => \pc_1_iv_1[23]\, C => - \un6_fe_npc_m[21]\, Y => \pc_1[23]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I311_Y_0 : AX1B - port map(A => N514_0, B => N_71, C => - \un6_ex_add_res_s2_1[21]\, Y => \un6_ex_add_res_s0[21]\); - - \r.a.rfa1_RNI9DT01[2]\ : MX2 - port map(A => \un3_de_ren1[93]\, B => \rfa1[2]\, S => holdn, - Y => raddr1(2)); - - un6_ex_add_res_d2_ADD_33x33_fast_I7_P0N : OR2 - port map(A => \un1_iu0_6[6]\, B => \data_0[6]\, Y => N416); - - \r.e.op2_RNIDHIG[8]\ : MX2 - port map(A => \op2[8]\, B => N_4255, S => ldbp2_0, Y => - \un1_iu0_5[74]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I23_P0N\ : OR2 - port map(A => \inst_0_1[25]\, B => \dpc[25]\, Y => N428); - - \r.e.op2_RNIVIOP[16]\ : MX2 - port map(A => \op2[16]\, B => N_4263, S => ldbp2_0, Y => - \un1_iu0_5[82]\); - - \r.w.result[3]\ : DFN1E0 - port map(D => \wdata[3]\, CLK => lclk_c, E => holdn, Q => - \result[3]\); - - \r.e.ctrl.tt_RNO_1[1]\ : OR2 - port map(A => \tt_0[2]\, B => N_4036, Y => \tt_0[1]\); - - \r.a.ctrl.inst_RNIDG9A[29]\ : NOR2B - port map(A => \inst[29]\, B => pv, Y => un9_rabpmiss_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I212_un1_Y\ : NOR2B - port map(A => N604, B => N589, Y => I212_un1_Y); - - \r.d.pc_RNIURBA4[6]\ : MX2 - port map(A => \dpc[6]\, B => \fpc[6]\, S => \ra_bpmiss_1_0\, - Y => N_3883); - - un6_fe_npc_I_20 : XOR2 - port map(A => N_139, B => \fe_pc[6]\, Y => I_20); - - un6_ex_add_res_d2_ADD_33x33_fast_I206_Y_0_a3_1 : OR3C - port map(A => N398_1, B => alucin, C => N401_0, Y => N_57); - - \r.e.op1_RNISE9G[17]\ : OR2B - port map(A => \op1[17]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[17]\); - - \r.w.s.wim_RNIGJ4N2[5]\ : MX2 - port map(A => \wim[5]\, B => \result_0[5]\, S => - wim_1_sqmuxa, Y => \wim_1[5]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_5\ : OR2A - port map(A => irl_0(2), B => \pil[2]\, Y => \ACT_LT4_E[4]\); - - \r.x.ctrl.tt_RNO[3]\ : MX2C - port map(A => N_4201_i_0, B => N_4207, S => N_4210_i_0, Y - => \tt2[3]\); - - \r.e.shcnt_RNIN594N[1]\ : MX2C - port map(A => \shiftin_14[14]\, B => \shiftin_14[12]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[12]\); - - \r.e.ctrl.inst[28]\ : DFN1E0 - port map(D => \inst_1[28]\, CLK => lclk_c, E => holdn, Q - => \inst_2[28]\); - - un6_fe_npc_I_185 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[21]\, Y => N_21); - - un6_ex_add_res_d2_ADD_33x33_fast_I243_Y : OR2 - port map(A => N656, B => I243_un1_Y_1, Y => N796_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I183_Y : AO1 - port map(A => N594_2, B => N587_1, C => N586_0, Y => N652); - - un6_ex_add_res_d1_ADD_33x33_fast_I115_Y : AO1 - port map(A => N516_0, B => N513_1, C => N512_0, Y => N578_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I181_Y : AO1 - port map(A => N592, B => N585, C => N584, Y => N650_0); - - \r.w.result_RNIPJD4[27]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[27]\, - Y => \result_m_0_0[27]\); - - \r.a.rfa2_RNINMCQ2[6]\ : MX2 - port map(A => \un3_de_ren1[105]\, B => \rfa2[6]\, S => - holdn, Y => raddr2(6)); - - \r.e.op2_RNIQKAP_0[6]\ : OR2 - port map(A => \un1_iu0_6[6]\, B => \un1_iu0_5[72]\, Y => - \logicout_3[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_un1_Y : OR3C - port map(A => N643_1, B => N627_0, C => N799_1, Y => - I260_un1_Y_i); - - \r.w.s.tba_RNI2U888[14]\ : NOR2B - port map(A => \aluresult_1_iv_3[26]\, B => \bpdata_m_2[2]\, - Y => \aluresult_1_iv_5[26]\); - - \r.f.pc_RNO[20]\ : OR3C - port map(A => \tmp_m[20]\, B => \pc_1_iv_1[20]\, C => - \un6_fe_npc_m[18]\, Y => \pc_1[20]\); - - \r.e.ctrl.rd_RNI4D3O[7]\ : XNOR2 - port map(A => \rd_1[7]\, B => \un3_de_ren1[98]\, Y => - un2_rs1_1_7_i_0); - - \r.e.shcnt_RNI8H0R7[3]\ : MX2 - port map(A => \shiftin_8[42]\, B => \shiftin_8[34]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[34]\); - - \r.e.shcnt_RNI376H5[3]\ : MX2 - port map(A => \shiftin_8[30]\, B => \shiftin_8[22]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[22]\); - - \comb.op_mux.d_1_iv_RNO_5[29]\ : OR2B - port map(A => data2(29), B => d25, Y => \rfo_m_i[61]\); - - \r.a.ctrl.pc[2]\ : DFN1E0 - port map(D => \dpc[2]\, CLK => lclk_c, E => holdn, Q => - \pc[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I22_P0N : OR3A - port map(A => \data_0[21]\, B => \op1[21]\, C => ldbp1_2, Y - => N461); - - \r.e.aluop_1_RNIRGID1[1]\ : XOR3 - port map(A => \un1_iu0_6[14]\, B => \aluop_1[1]\, C => - \un1_iu0_5[80]\, Y => N_6901); - - \r.e.shcnt_RNIKLLCA[2]\ : MX2C - port map(A => \shiftin_11[12]\, B => \shiftin_11[8]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[8]\); - - \r.e.op2_RNO_7[22]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[374]\, - Y => \cpi_m_i[374]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I248_un1_Y : NOR2B - port map(A => N667_1, B => N616_1, Y => I248_un1_Y); - - \r.a.ctrl.wicc_RNO_2\ : NOR2B - port map(A => \inst_0_0[22]\, B => un7_op_3, Y => N_97); - - \r.x.result_RNIV0Q65[1]\ : OR2B - port map(A => \bpdata[1]\, B => N_3957_1, Y => - \bpdata_m_1[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I267_Y_0 : AOI1 - port map(A => N656, B => N641, C => N640_1, Y => - ADD_33x33_fast_I267_Y_0_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I187_Y : AO1A - port map(A => N591_0, B => N598_1, C => N590_0, Y => N656_0); - - \r.x.result_RNIIFJA[1]\ : MX2 - port map(A => \result_0[1]\, B => \data_0[1]\, S => ld_0, Y - => \un1_p0_6[353]\); - - \r.x.ctrl.pc[25]\ : DFN1E0 - port map(D => \pc_3[25]\, CLK => lclk_c, E => holdn, Q => - \pc_2[25]\); - - \r.a.imm_RNO[10]\ : MX2 - port map(A => \inst_0_RNI0FUM[0]\, B => \inst_0[10]\, S => - call_hold5_0, Y => \un3_de_ren1[128]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I44_Y : NOR2B - port map(A => N473_2, B => N470_0, Y => N503_1); - - \r.e.op2_RNO_3[6]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[6]\, Y - => \aluresult_m_i[6]\); - - \r.e.op2_RNO[21]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[21]\, Y => N_305); - - un6_ex_add_res_d0_ADD_33x33_fast_I127_Y : AO1 - port map(A => N528_0, B => N525_1, C => N524_0, Y => N590_2); - - \r.e.ctrl.pc_RNIADK11[24]\ : OR2B - port map(A => \pc[24]\, B => jmpl_0, Y => \cpi_m[169]\); - - \r.d.inst_0_RNI1GIQ[24]\ : AOI1B - port map(A => ldcheck1_5_i_a6_2_2, B => N_3737_1, C => - N_3736, Y => ldcheck1_2); - - \r.d.inst_0[7]\ : DFN1 - port map(D => \inst_0_RNO[7]\, CLK => lclk_c, Q => - \inst_0[7]\); - - \r.x.ctrl.tt_RNIB2K6[4]\ : NOR2B - port map(A => \tt_0[4]\, B => \tt_0[5]\, Y => tt_2); - - \r.m.y_RNO[6]\ : OR3C - port map(A => \y_iv_1[6]\, B => \y_iv_0[6]\, C => - \logicout_m[6]\, Y => \y_1[6]\); - - \r.e.shcnt_RNI4KQGC[2]\ : MX2C - port map(A => \shiftin_11[24]\, B => \shiftin_11[20]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[20]\); - - \r.e.aluop_RNI36373[1]\ : MX2C - port map(A => N_3537, B => \logicout_3[10]\, S => - \aluop_3[1]\, Y => N_3569); - - un6_ex_add_res_d0_ADD_33x33_fast_I269_Y_0 : AND2 - port map(A => I231_un1_Y_i, B => N644_i, Y => - ADD_33x33_fast_I269_Y_0); - - \r.x.data_0_RNIGJ9E[26]\ : XOR2 - port map(A => \data_0[26]\, B => invop2_1, Y => N_4273); - - \comb.branch_address.tmp_ADD_30x30_fast_I7_P0N\ : OR2 - port map(A => \inst_0[7]\, B => \dpc[9]\, Y => N380); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_Y_0 : OA1C - port map(A => N500, B => N497_0, C => N496_0, Y => - ADD_33x33_fast_I261_Y_0); - - \r.m.y_RNO_3[26]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y[26]\, C => \y_m[26]\, Y - => \y_iv_1[26]\); - - \r.e.op1_RNIDN5RB[23]\ : NOR2 - port map(A => \edata2_0_iv_1[23]\, B => \bpdata_i_m_1[7]\, - Y => edata2_0_iv(23)); - - \r.a.imm_RNO[26]\ : MX2 - port map(A => \inst_0[16]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[144]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I124_Y : NOR2B - port map(A => N525_1, B => N521, Y => N587_0); - - \r.e.op2_RNO_4[15]\ : OA1A - port map(A => \maddress[15]\, B => d27_0, C => - \cpi_m_i[367]\, Y => \d_1_iv_1[15]\); - - \r.x.result_RNITDG25[9]\ : OR2B - port map(A => \bpdata[9]\, B => N_3974, Y => \bpdata_m[9]\); - - \r.e.shleft_1_RNINGHP\ : NOR2A - port map(A => \un1_iu0_6[12]\, B => shleft_1, Y => - shleft_1_RNINGHP); - - \r.e.op2_RNO_5[9]\ : OR2B - port map(A => \result[9]\, B => d31, Y => \result_m_i[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I236_Y_0\ : AO1 - port map(A => N522, B => N515, C => N514, Y => - ADD_30x30_fast_I236_Y_0); - - \r.a.ctrl.inst_RNI8O0E[20]\ : NOR2 - port map(A => \inst_2[20]\, B => \inst_1[24]\, Y => - inst_32_1); - - un6_fe_npc_I_152 : AND3 - port map(A => \DWACT_FINC_E[34]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I27_P0N : OR2 - port map(A => \un1_iu0_6[26]\, B => \op2[26]\, Y => N476); - - \r.m.y_RNO_0[18]\ : NOR3C - port map(A => N_397, B => N_394, C => \y_iv_0_1[18]\, Y => - \y_iv_0_2[18]\); - - \r.d.inst_0[2]\ : DFN1 - port map(D => \inst_0_RNO[2]\, CLK => lclk_c, Q => - \inst_0[2]\); - - \r.e.aluop_0_RNI8N4Q5[0]\ : MX2C - port map(A => N_3585, B => N_3649, S => \aluop_0[0]\, Y => - \logicout[26]\); - - \r.e.shleft_RNI35931\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[7]\, S => shleft, - Y => \shiftin_5[38]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I15_P0N : AO1A - port map(A => ldbp1_1, B => \op1[14]\, C => \data_0[14]\, Y - => N440_1); - - \r.x.rstate_RNO_1[1]\ : OR2A - port map(A => rstate_6314_d_0, B => error_1_sqmuxa, Y => - \rstate_ns[1]\); - - \r.w.s.s_RNI8MPP\ : OR2B - port map(A => s_3_sqmuxa_0, B => s, Y => s_m); - - \r.e.ctrl.pc[25]\ : DFN1E0 - port map(D => \pc_0[25]\, CLK => lclk_c, E => holdn, Q => - \pc[25]\); - - \r.e.op2_RNI4THG[3]\ : MX2 - port map(A => \op2[3]\, B => N_3307, S => ldbp2_1, Y => - \un1_iu0_5[69]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I30_G0N : NOR2B - port map(A => \un1_iu0_6[29]\, B => \op2[29]\, Y => N484_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I263_Y_1 : NOR3B - port map(A => I163_un1_Y_i, B => I219_un1_Y_i, C => N566_0, - Y => ADD_33x33_fast_I263_Y_1_1); - - \r.e.op1_RNIC8KS4[17]\ : OR2 - port map(A => \bpdata_i_m[17]\, B => \op1_i_m[17]\, Y => - \edata2_0_iv_0[17]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I247_un1_Y : NOR2B - port map(A => N665_1, B => N614_2, Y => I247_un1_Y); - - \r.x.mexc_RNO\ : NOR2B - port map(A => rst, B => N_5246, Y => mexc_RNO); - - \r.m.y_RNI16HP2[24]\ : AOI1B - port map(A => \y[24]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[24]\, Y => \aluresult_1_iv_0[24]\); - - \r.e.op1_RNI6NN8[1]\ : MX2 - port map(A => \op1[1]\, B => \data_0[1]\, S => ldbp1_1, Y - => \un1_iu0_6[1]\); - - \r.d.inst_0[19]\ : DFN1 - port map(D => \inst_0_RNO[19]\, CLK => lclk_c, Q => - \inst_0[19]\); - - \r.e.op1_RNO[5]\ : MX2C - port map(A => \d_i_0[5]\, B => \d_i[6]\, S => N_227_0, Y - => \aop1[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I244_un1_Y : NOR3C - port map(A => N593_0, B => N601, C => N674_0, Y => - ADD_33x33_fast_I244_un1_Y); - - \r.e.shcnt_RNIBUE9R[1]\ : MX2C - port map(A => \shiftin_14[24]\, B => \shiftin_14[22]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[22]\); - - \r.x.mexc_RNIEOPT\ : NOR2A - port map(A => N_3321, B => mexc_0, Y => \xc_vectt_1[2]\); - - \r.a.ctrl.inst_RNI914O1[25]\ : OR3A - port map(A => \cpi_m_1[133]\, B => N_212, C => N_205, Y => - \cpi_m_i[133]\); - - \r.x.data_0_RNO_0[30]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_30, Y => - \dco_m_1[126]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I196_Y : NOR3C - port map(A => N541, B => N545_0, C => N599_2, Y => N665_1); - - \r.x.data_0[28]\ : DFN1E0 - port map(D => \data_0_1[28]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[28]\); - - \comb.lock_gen.ldchkra_RNIR29CO\ : AO1B - port map(A => ldlock2_1, B => un1_ldcheck1_1, C => - ldlock_2_0, Y => \ldlock_2\); - - un6_ex_add_res_d1_ADD_33x33_fast_I8_P0N : OR2 - port map(A => \un1_iu0_6[7]\, B => \op2[7]\, Y => N419_1); - - \r.f.pc_RNO[25]\ : OR3C - port map(A => \tmp_m[25]\, B => \pc_1_iv_1[25]\, C => - \un6_fe_npc_m[23]\, Y => \pc_1[25]\); - - \r.a.imm[26]\ : DFN1E0 - port map(D => \un3_de_ren1[144]\, CLK => lclk_c, E => holdn, - Q => \imm[26]\); - - \r.w.s.y[3]\ : DFN1E0 - port map(D => N_3767, CLK => lclk_c, E => N_6922_i, Q => - \y[3]\); - - \r.e.op2_RNO_0[24]\ : OR3C - port map(A => \op1_m_i[24]\, B => \d_1_iv_3[24]\, C => - \aluresult_m_i[24]\, Y => \d_1[24]\); - - \r.w.s.tba_RNIQD7A1[18]\ : OR2B - port map(A => \tba[18]\, B => aluresult_12_sqmuxa, Y => - \tba_m[18]\); - - \r.f.pc_RNIN8A81[7]\ : MX2 - port map(A => \fpc[7]\, B => \xc_vectt_1[3]\, S => - rstate_6314_d, Y => \xc_trap_address[7]\); - - \r.w.result[30]\ : DFN1E0 - port map(D => \wdata[30]\, CLK => lclk_c, E => holdn, Q => - \result[30]\); - - \r.x.data_0_RNIJN43[9]\ : XOR2 - port map(A => \data_0[9]\, B => invop2, Y => N_4256); - - \r.m.casa_RNIKPD91\ : NOR2 - port map(A => un1_logicout21, B => un17_casaen_0, Y => - edata_3_sqmuxa); - - \r.e.ctrl.wicc_RNIDRHTF5\ : MX2C - port map(A => N_4185, B => N_4175, S => wicc_2, Y => - \icco[0]\); - - \r.m.ctrl.inst_RNIUG0E[20]\ : OR2A - port map(A => \inst_3[20]\, B => \inst_2[22]\, Y => - trap_0_sqmuxa_3_2); - - \r.e.aluop_0_RNIHLB5Q[0]\ : NOR3C - port map(A => \aluresult_1_iv_5[25]\, B => - \aluresult_1_iv_4[25]\, C => \logicout_m_0[25]\, Y => - \aluresult_1_iv_7[25]\); - - \dci.enaddr_1_sqmuxa_1_RNO\ : NOR2A - port map(A => enaddr_1_sqmuxa_1_0, B => \cnt[1]\, Y => - enaddr_1_sqmuxa_1_1); - - \r.x.npc_0_RNI7LHG1[0]\ : MX2 - port map(A => \npc_0[0]\, B => \npc_cnst_m_0[0]\, S => - s_3_sqmuxa_0, Y => \npc_1[0]\); - - \r.w.result_RNILFD4[16]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[16]\, - Y => \result_m_0_0[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I2_P0N\ : OR2 - port map(A => \inst_0_RNI2NUM[2]\, B => \dpc[4]\, Y => N365); - - un6_ex_add_res_d1_ADD_33x33_fast_I203_un1_Y : NOR2B - port map(A => N614_0, B => N607_0, Y => I203_un1_Y); - - \r.e.invop2_RNINRBQE\ : MX2 - port map(A => \un6_ex_add_res_s2[10]\, B => - \un6_ex_add_res_s0[10]\, S => invop2, Y => N_6629); - - \r.e.ctrl.wy\ : DFN1E0 - port map(D => wy, CLK => lclk_c, E => holdn, Q => wy_3); - - un6_ex_add_res_d1_ADD_33x33_fast_I184_Y : NOR3B - port map(A => N521_1, B => N525, C => N595_2, Y => N653); - - \r.f.pc[5]\ : DFN1E0 - port map(D => \pc_1[5]\, CLK => lclk_c, E => holdn, Q => - \fpc[5]\); - - \r.d.pv_RNITOEF91\ : NOR2A - port map(A => annul_next_2_sqmuxa_1_5, B => ldlock, Y => - annul_next_2_sqmuxa_1_6); - - un6_ex_add_res_d1_ADD_33x33_fast_I6_P0N : OR2 - port map(A => \un1_iu0_6[5]\, B => \op2[5]\, Y => N413_1); - - \r.e.op2_RNO_4[26]\ : OA1A - port map(A => \maddress[26]\, B => d27_0, C => - \cpi_m_i[378]\, Y => \d_1_iv_1[26]\); - - \r.e.ctrl.rd[4]\ : DFN1E0 - port map(D => \rd_1[4]\, CLK => lclk_c, E => holdn, Q => - \rd_0[4]\); - - \r.e.aluop_RNIC8EB4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[30]\, Y => - \aluop_RNIC8EB4[1]\); - - un2_rstn_5_0_0_RNI05FAD3 : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[5]\, C => - \tmp_m[5]\, Y => \npc_iv_0[5]\); - - \r.x.y[27]\ : DFN1E0 - port map(D => \y_0[27]\, CLK => lclk_c, E => holdn, Q => - \y_2[27]\); - - \r.x.result[23]\ : DFN1E0 - port map(D => \maddress[23]\, CLK => lclk_c, E => holdn, Q - => \result[23]\); - - \r.d.inst_0_RNI5C23_3[31]\ : OR2 - port map(A => \inst_0[31]\, B => \inst_0[30]\, Y => - call_hold5_0); - - \r.e.shcnt_RNO[3]\ : XOR2 - port map(A => \d_1[3]\, B => N_208, Y => N_269_i_i_0); - - \r.e.op2_RNO_9[8]\ : OR2B - port map(A => \result_0[8]\, B => d31, Y => \result_m_i[8]\); - - \r.m.y_RNIC4K91[6]\ : OR2B - port map(A => \y_0[6]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[6]\); - - \r.d.pv_RNO_6\ : MX2 - port map(A => un4_op3, B => un13_op3, S => \cnt_2[0]\, Y - => pv_RNO_6); - - \r.x.result_RNIPC6E[16]\ : MX2 - port map(A => \result_0[16]\, B => \data_0[16]\, S => ld_4, - Y => \un1_p0_6[368]\); - - \r.e.op2_RNO_0[8]\ : OR3C - port map(A => \op1_m_i[8]\, B => \d_1_iv_3[8]\, C => - \aluresult_m_i[8]\, Y => \d_1[8]\); - - \r.d.inst_0[30]\ : DFN1 - port map(D => \inst_0_RNO[30]\, CLK => lclk_c, Q => - \inst_0[30]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I164_Y : NOR2A - port map(A => N575_1, B => N567_2, Y => N633_1); - - \r.a.nobp_RNO_0\ : OR2A - port map(A => N_16827_tz, B => ctrl_annul_i, Y => - nobp_RNO_0); - - \r.e.op2_RNO[28]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[28]\, Y => N_312); - - un6_ex_add_res_d2_ADD_33x33_fast_I104_Y : NOR3C - port map(A => N473_2, B => N476_2, C => N505_0, Y => N567_0); - - \r.f.pc_RNI8P4IL3[8]\ : MX2 - port map(A => I_31, B => N_4051, S => bpmiss_1_i_0_0, Y => - \pc_4[8]\); - - \r.w.s.wim_RNIIN4N2[6]\ : MX2 - port map(A => \wim[6]\, B => \result_0[6]\, S => - wim_1_sqmuxa, Y => \wim_1[6]\); - - \r.m.result_RNIQVO1[10]\ : OR2B - port map(A => d13, B => \maddress[10]\, Y => - \result_m_0[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I284_Y_0_0\ : XOR2 - port map(A => \dpc[26]\, B => \inst_0_1[26]\, Y => - ADD_30x30_fast_I284_Y_0_0); - - \r.d.pc_RNIO5HB4[21]\ : MX2 - port map(A => \dpc[21]\, B => \fpc[21]\, S => - \ra_bpmiss_1_0\, Y => N_3898); - - \r.f.pc_RNIBOM4[9]\ : OR2A - port map(A => \fpc[9]\, B => rst, Y => \pc_m[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I309_Y_0 : XOR3 - port map(A => \data_0_0[18]\, B => \un1_iu0_6[18]\, C => - N790_1, Y => \un6_ex_add_res_s2[19]\); - - \r.a.ctrl.cnt_RNI0BU9_0[0]\ : NOR3B - port map(A => \cnt_2[1]\, B => casa, C => \cnt_1[0]\, Y => - N_219); - - \r.m.ctrl.wy\ : DFN1E0 - port map(D => wy_3, CLK => lclk_c, E => holdn, Q => wy_1); - - \r.m.y_RNO_2[5]\ : OR2B - port map(A => \y_2[5]\, B => y08, Y => \y_m_0[5]\); - - \r.d.inst_0_RNO_0[13]\ : MX2 - port map(A => data_0_0_13, B => \inst_0[13]\, S => - mexc_1_sqmuxa_1_0, Y => N_4613); - - \r.x.ctrl.pc_RNIID971[11]\ : MX2C - port map(A => \un1_p0_6[363]\, B => \pc_0[11]\, S => - s_3_sqmuxa, Y => N_3402); - - \r.e.ctrl.inst_RNI0L256[21]\ : OA1B - port map(A => N_3356_3, B => force_a2_1, C => - ldbp2_1_RNIL7Q55, Y => \eaddress[2]\); - - \r.w.s.y_RNO_1[1]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y_0[1]\, Y => N_398); - - \comb.v.x.data_0_1_1_iv_RNO_1[19]\ : AOI1B - port map(A => rdatav_0_1_0_iv_5_1, B => mcdo_m_0_17, C => - rdata_6_sqmuxa, Y => \dco_m_0[115]\); - - \r.e.aluop_0_RNIKBTV81[0]\ : NOR3C - port map(A => \aluresult_1_iv_6[9]\, B => \logicout_m_0[9]\, - C => \shiftin_17_m[10]\, Y => \aluresult_1_iv_8[9]\); - - \r.w.s.y[18]\ : DFN1E0 - port map(D => N_158, CLK => lclk_c, E => holdn, Q => - \y[18]\); - - \r.m.ctrl.pc[6]\ : DFN1E0 - port map(D => \pc[6]\, CLK => lclk_c, E => holdn, Q => - \pc_2[6]\); - - \r.d.inst_0_RNO_0[15]\ : MX2 - port map(A => data_0_15, B => \inst_0[15]\, S => - mexc_1_sqmuxa_1_0, Y => N_4615); - - \r.f.pc_RNO_6[12]\ : MX2 - port map(A => \fpc[12]\, B => \eaddress[12]\, S => jump, Y - => N_4055); - - \r.e.et_RNIGDGSJ\ : AOI1B - port map(A => \bpdata[5]\, B => N_3957, C => - \aluresult_1_iv_6[5]\, Y => \aluresult_1_iv_7[5]\); - - \r.d.inst_0_RNIF423[29]\ : OR2 - port map(A => \inst_0[29]\, B => \inst_0[28]\, Y => - N_3525_3); - - \r.w.s.tt[0]\ : DFN1 - port map(D => \tt_RNO[0]\, CLK => lclk_c, Q => \irl[0]\); - - \r.a.ctrl.pc_RNIM0M0C[7]\ : MX2 - port map(A => \pc_3[7]\, B => N_3884, S => ex_bpmiss_1, Y - => \fe_pc[7]\); - - \r.w.s.tt_RNO[0]\ : MX2A - port map(A => \xc_vectt_1[0]\, B => \irl[0]\, S => N_6747, - Y => \tt_RNO[0]\); - - \r.a.ctrl.wicc_RNO_0\ : NOR3A - port map(A => \inst_0_0[23]\, B => \inst_0_0[24]\, C => - N_97, Y => wicc_1_0_a3_0_0); - - \r.a.ctrl.inst_RNID81L[23]\ : NOR3B - port map(A => \inst_2[20]\, B => \inst_1[23]\, C => - \inst_1[24]\, Y => inst_21_1); - - \r.e.jmpl_RNIIF42P1\ : OR2B - port map(A => \aluresult_2_iv_7[0]\, B => \shiftin_17_m[1]\, - Y => \aluresult[0]\); - - \r.a.ctrl.inst_RNICC292[30]\ : NOR3C - port map(A => N_454, B => \inst_RNIJ02L[19]\, C => - \aop2_i_o2_0[0]\, Y => \aop2_i_o2_2[0]\); - - \r.e.op2_RNIR1VL1[9]\ : AOI1B - port map(A => \un1_iu0_5[75]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[9]\); - - \r.e.op2_RNO_6[24]\ : OR2B - port map(A => data2(24), B => d25, Y => \rfo_m_i[56]\); - - \r.x.y[18]\ : DFN1E0 - port map(D => \y_1[18]\, CLK => lclk_c, E => holdn, Q => - \y_2[18]\); - - \r.e.ctrl.pc_RNIETK11[28]\ : OR2B - port map(A => \pc_2[28]\, B => jmpl_4, Y => \cpi_m[173]\); - - \r.m.y_RNO[19]\ : OR3C - port map(A => \y_iv_1[19]\, B => \y_iv_0[19]\, C => - \logicout_m[19]\, Y => \y_1[19]\); - - \r.a.ctrl.pc_RNI3KE2C[24]\ : MX2 - port map(A => \pc_3[24]\, B => N_3901, S => ex_bpmiss_1, Y - => \fe_pc[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I285_Y_0\ : XNOR2 - port map(A => N702_i, B => ADD_30x30_fast_I285_Y_0_0, Y => - \tmp[27]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I303_Y_0 : AX1 - port map(A => ADD_33x33_fast_I246_Y_0_a3_1, B => N430_1, C - => \un6_ex_add_res_s0_1[13]\, Y => - \un6_ex_add_res_s2[13]\); - - \r.e.ctrl.rd_RNIU8FK1[1]\ : XA1A - port map(A => \rd[1]\, B => \inst_0_RNI1JUM[1]\, C => - un1_de_ren1_2_0_i_0, Y => wreg_1_1); - - \r.a.rsel1_0_RNIE3LJ2[2]\ : OR2B - port map(A => data1(17), B => d11_0, Y => \rfo_m[17]\); - - \r.e.shcnt_RNI970Q5[3]\ : MX2 - port map(A => \shiftin_8[27]\, B => \shiftin_8[19]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[19]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I316_Y_0 : XNOR2 - port map(A => N776_0, B => \un6_ex_add_res_s2_1[26]\, Y => - \un6_ex_add_res_s0[26]\); - - \r.x.ctrl.wy_RNILF1N3_0\ : NOR2 - port map(A => y_1_sqmuxa_1, B => y_1_sqmuxa_0, Y => N_481); - - \r.e.op2_RNIS6VD4[7]\ : AOI1B - port map(A => \un1_iu0_5[73]\, B => aluresult_7_sqmuxa_0_0, - C => \aluresult_1_iv_0[7]\, Y => \aluresult_1_iv_1[7]\); - - \r.e.aluop_0_RNIRHPC4[0]\ : NOR3 - port map(A => \logicout_5_0_i_0[24]\, B => N_448, C => - N_447, Y => N_198); - - \r.a.imm_RNI2645[1]\ : OR3B - port map(A => d29_0_0, B => \imm[1]\, C => \rsel2_0[0]\, Y - => \imm_m_i[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I31_P0N : OR2A - port map(A => \data_0[30]\, B => \un1_iu0_6[30]\, Y => - N488_2); - - \r.w.s.tba_RNIKL6A1[12]\ : OR2B - port map(A => \tba[12]\, B => aluresult_12_sqmuxa_0_0, Y - => \tba_m[12]\); - - \r.x.ctrl.inst_RNI0TN43[27]\ : OR3A - port map(A => y_0_sqmuxa_3, B => y_0_sqmuxa_1, C => - \rstate_d[2]\, Y => y_1_sqmuxa_1); - - \r.d.cnt_RNI9TF3[0]\ : OR2B - port map(A => \cnt_2[0]\, B => \inst_0[30]\, Y => N_3739); - - un6_ex_add_res_d2_ADD_33x33_fast_I151_un1_Y : NOR2B - port map(A => N552_1, B => N549, Y => I151_un1_Y); - - aluresult_11_sqmuxa_5_RNIQJG41 : NOR3C - port map(A => aluresult_12_sqmuxa_0, B => - aluresult_12_sqmuxa_4, C => aluresult_12_sqmuxa_5, Y => - aluresult_12_sqmuxa); - - un6_fe_npc_I_182 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[30]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I10_P0N : AO1A - port map(A => ldbp1, B => \op1[9]\, C => \data_0[9]\, Y => - N425_2); - - \r.d.inst_0[13]\ : DFN1 - port map(D => \inst_0_RNO[13]\, CLK => lclk_c, Q => - \inst_0[13]\); - - \r.e.op2[0]\ : DFN1E0 - port map(D => N_284, CLK => lclk_c, E => holdn, Q => - \op2[0]\); - - \r.f.branch_RNIJ4KLC\ : NOR3B - port map(A => d_m5_0_a3_0, B => ex_bpmiss_1_0, C => - \xc_exception_1_0\, Y => d_m5_0_a3_2); - - \r.e.ldbp2_2_RNITAJ763\ : OR2A - port map(A => \eaddress[20]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[21]\); - - \r.e.op2_RNO_2[19]\ : NOR3C - port map(A => \d_1_iv_1[19]\, B => \d_1_iv_0[19]\, C => - \rfo_m_i[51]\, Y => \d_1_iv_3[19]\); - - \r.e.op2_RNO[11]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[11]\, Y => N_295); - - \r.m.y_RNO_2[21]\ : OR2B - port map(A => wy_RNIMKUI, B => \y_2[21]\, Y => \y_m_0[21]\); - - \r.e.cwp_RNIFTJ61[0]\ : OR2A - port map(A => \cwp_1[0]\, B => aluresult_11_sqmuxa, Y => - \cwp_m[0]\); - - \r.x.ctrl.pc_RNINIIF[19]\ : MX2 - port map(A => \pc_0[19]\, B => \pc[19]\, S => \npc_1[1]\, Y - => N_3230); - - \r.d.cwp_RNO_1[0]\ : MX2 - port map(A => \cwp_0[0]\, B => \maddress[0]\, S => wcwp, Y - => N_4218); - - \r.a.rsel2_0_RNILPBM2[0]\ : OR2B - port map(A => data2(0), B => d25, Y => \rfo_m_i[32]\); - - \r.e.op1_RNIFQ3U1[3]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[3]\, C => - \ex_op1_i_m[3]\, Y => \edata2_0_iv_0[3]\); - - \r.e.ldbp2_2_RNIV858N3\ : MX2C - port map(A => \un6_ex_add_res_s1_i[23]\, B => N_6569, S => - ldbp2_2, Y => \eaddress[22]\); - - \r.m.y_RNO_1[18]\ : OR2B - port map(A => \y_0[19]\, B => mulstep_1, Y => N_397); - - un6_ex_add_res_d0_ADD_33x33_fast_I38_Y : OR2B - port map(A => N482_1, B => N479_1, Y => N497_0); - - \r.x.result[7]\ : DFN1E0 - port map(D => \maddress[7]\, CLK => lclk_c, E => holdn, Q - => \result_0[7]\); - - \r.x.ctrl.pc_RNIG7AE[7]\ : MX2 - port map(A => \pc[7]\, B => \pc_0[7]\, S => \npc_0[1]\, Y - => N_3218); - - \r.e.ctrl.inst_RNIB1LO[27]\ : AO1B - port map(A => \inst_1[27]\, B => \icc_0[0]\, C => N_6695_i, - Y => N_328); - - \r.e.shcnt_RNIAUGF6[3]\ : MX2 - port map(A => \shiftin_8[37]\, B => \shiftin_8[29]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[29]\); - - \r.e.ctrl.cnt_RNILO7A_0[0]\ : NOR3A - port map(A => \cnt[0]\, B => \cnt[1]\, C => annul, Y => - enaddr_2_sqmuxa_0); - - \r.e.op2_RNO_2[28]\ : NOR3C - port map(A => \d_1_iv_1[28]\, B => \d_1_iv_0[28]\, C => - \rfo_m_i[60]\, Y => \d_1_iv_3[28]\); - - \r.d.inst_0[14]\ : DFN1 - port map(D => \inst_0_RNO[14]\, CLK => lclk_c, Q => - \inst_0[14]\); - - \r.a.imm[10]\ : DFN1E0 - port map(D => \un3_de_ren1[128]\, CLK => lclk_c, E => holdn, - Q => \imm[10]\); - - \r.a.bp_RNIHG6I\ : NOR3A - port map(A => bp, B => annul_2, C => not_valid, Y => - ra_bpmiss_1_1); - - \r.e.op2_RNIJQNP[10]\ : MX2 - port map(A => \op2[10]\, B => N_4257, S => ldbp2_0, Y => - \un1_iu0_5[76]\); - - un6_fe_npc_I_142 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[16]\, Y => N_51); - - \r.a.ctrl.inst_RNII02L[24]\ : OR2A - port map(A => N_487, B => \inst_1[24]\, Y => - illegal_inst_7_iv_2_0_a5_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I91_Y\ : NOR2B - port map(A => N456, B => N452, Y => N511); - - un6_ex_add_res_d1_ADD_33x33_fast_I314_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[23]\, B => \op2[23]\, Y => - ADD_33x33_fast_I314_Y_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I100_Y : NOR3B - port map(A => N473_1, B => N476_1, C => N497_0, Y => N563); - - \r.x.data_0_RNO_1[14]\ : AO1A - port map(A => rdata_5_sqmuxa, B => data_0_0_30, C => - \data_0_m[14]\, Y => \data_0_1_0_iv_0[14]\); - - \r.m.result_RNIBJD4[23]\ : OR2B - port map(A => d13_0, B => \maddress[23]\, Y => - \result_m_0[23]\); - - \r.e.shleft_1_RNI6PHM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[21]\, S => - shleft_1, Y => \shiftin_5[52]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_Y_2 : NOR3C - port map(A => I159_un1_Y_0, B => ADD_33x33_fast_I261_Y_0, C - => I215_un1_Y, Y => ADD_33x33_fast_I261_Y_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I271_Y_0 : AOI1 - port map(A => N664, B => N649, C => N648_0, Y => - ADD_33x33_fast_I271_Y_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I22_P0N\ : OR2 - port map(A => \inst_0_0_0_RNI9O79[21]\, B => \dpc[24]\, Y - => N425); - - \r.e.shcnt_RNI8LCF4[3]\ : MX2 - port map(A => \shiftin_8[16]\, B => \shiftin_8[8]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I315_Y_0 : XOR2 - port map(A => N778, B => \un6_ex_add_res_s2_1[25]\, Y => - \un6_ex_add_res_s2[25]\); - - \r.d.cnt_RNO[1]\ : MX2B - port map(A => \cnt_0[1]\, B => cnt_3_sqmuxa, S => N_6825_i, - Y => \cnt_RNO[1]\); - - \r.x.data_0_RNO_2[1]\ : OR2A - port map(A => data_0_0_25, B => rdata_0_sqmuxa, Y => - \dco_m_i[121]\); - - \r.m.result_RNO[30]\ : MX2 - port map(A => \aluresult[30]\, B => \op1[30]\, S => - un17_casaen_0_1, Y => \eres2[30]\); - - \r.d.inst_0_RNI5C23_2[31]\ : OR2 - port map(A => \inst_0[31]\, B => \inst_0[30]\, Y => - call_hold5); - - \r.e.aluop_0_RNII3966[0]\ : OR2B - port map(A => \logicout[25]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[25]\); - - \r.e.aluop_0_RNIBM4Q5[0]\ : MX2C - port map(A => N_3576, B => N_3640, S => \aluop_0[0]\, Y => - \logicout[17]\); - - \r.x.data_0_RNO_1[13]\ : OR2 - port map(A => \dco_m_0[125]\, B => \data_0_m[13]\, Y => - \data_0_1_0_iv_0[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I248_Y : AO1 - port map(A => N667_0, B => N616_0, C => N666_1, Y => N811_1); - - \r.e.op1_RNIMOKS4[19]\ : AO1A - port map(A => \bpdata[19]\, B => edata_2_sqmuxa, C => - \op1_i_m[19]\, Y => \edata2_0_iv_0[19]\); - - \r.d.pc_RNIU5HB4[24]\ : MX2 - port map(A => \dpc[24]\, B => \fpc[24]\, S => ra_bpmiss_1, - Y => N_3901); - - \r.e.invop2_RNICR63K\ : MX2C - port map(A => \un6_ex_add_res_s2[12]\, B => - \un6_ex_add_res_s0[12]\, S => invop2, Y => N_6631); - - \r.m.result_RNO[28]\ : MX2 - port map(A => \aluresult[28]\, B => \op1[28]\, S => - un17_casaen_0_2, Y => \eres2[28]\); - - \r.x.rstate_RNI4GF12[0]\ : MX2C - port map(A => N_3416, B => \xc_result[25]\, S => - \rstate[0]\, Y => \wdata[25]\); - - \r.e.op1[21]\ : DFN1E0 - port map(D => \aop1[21]\, CLK => lclk_c, E => holdn, Q => - \op1[21]\); - - \r.f.branch_RNIA8KSK\ : NOR3C - port map(A => branch_RNIMJA92, B => branch_1_m7_3, C => - \ra_bpmiss_1_0\, Y => branch_RNIA8KSK); - - \r.e.op1[17]\ : DFN1E0 - port map(D => \aop1[17]\, CLK => lclk_c, E => holdn, Q => - \op1[17]\); - - \r.e.aluop_0_RNIL56R[2]\ : XA1 - port map(A => \un1_iu0_5[71]\, B => \aluop_0[2]\, C => - \un1_iu0_6[5]\, Y => N_3532); - - \r.f.pc_RNO_0[28]\ : NAND2 - port map(A => \tmp[28]\, B => un2_rstn_5_0, Y => - \tmp_m[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I182_Y : NOR2B - port map(A => N593_1, B => N585_1, Y => N651); - - \r.e.op2_RNO_1[20]\ : OR2B - port map(A => \op1[20]\, B => un14_casaen_s1, Y => - \op1_m_i[20]\); - - \r.a.ctrl.pc[3]\ : DFN1E0 - port map(D => \dpc[3]\, CLK => lclk_c, E => holdn, Q => - \pc[3]\); - - \r.f.pc_RNI8ILOU1[2]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[2]\, Y => - \pc_4_m[2]\); - - \r.e.op2_RNO_0[21]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[21]\, C - => \d_1_iv_4[21]\, Y => \d_1[21]\); - - \r.a.nobp\ : DFN1E0 - port map(D => nobp_1, CLK => lclk_c, E => holdn, Q => nobp); - - \r.e.shleft_RNIBIEC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[10]\, S => - shleft, Y => \shiftin_5[41]\); - - \r.e.op2_RNO_2[16]\ : NOR3C - port map(A => \d_1_iv_1[16]\, B => \d_1_iv_0[16]\, C => - \rfo_m_i[48]\, Y => \d_1_iv_3[16]\); - - \r.x.ctrl.pc[14]\ : DFN1E0 - port map(D => \pc_2[14]\, CLK => lclk_c, E => holdn, Q => - \pc_0[14]\); - - \r.x.ctrl.pc_RNIE7AE[6]\ : MX2 - port map(A => \pc_1[6]\, B => \pc[6]\, S => \npc_0[1]\, Y - => N_3217); - - \r.e.ctrl.inst_RNIQT1J7_0[26]\ : NOR2 - port map(A => ex_bpmiss_1_0_1, B => ex_bpmiss_1_0_2, Y => - ex_bpmiss_1); - - \r.x.npc_0_RNIJTT61[0]\ : MX2C - port map(A => N_3237, B => N_3267, S => \npc_0[0]\, Y => - \xc_result[26]\); - - \r.x.result[5]\ : DFN1E0 - port map(D => \maddress[5]\, CLK => lclk_c, E => holdn, Q - => \result_0[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I12_P0N : AO1A - port map(A => ldbp1, B => \op1[11]\, C => \data_0_2[11]\, Y - => N431_2); - - \r.e.ldbp2_RNITPCCO6\ : OR2B - port map(A => \aluresult_1_iv_9[25]\, B => - \un6_ex_add_res_m[26]\, Y => \aluresult[25]\); - - \r.e.aluop_RNI2QON[1]\ : NOR3B - port map(A => logicout19_0, B => \aluop_3[1]\, C => - aluresult_9_sqmuxa_1, Y => aluresult_4_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I9_G0N : NOR2B - port map(A => \un1_iu0_6[8]\, B => \op2[8]\, Y => N421_0); - - \r.a.rsel1_RNI1RFA_1[0]\ : NOR2A - port map(A => N_494, B => un17_casaen_0, Y => - un14_casaen_s0_0); - - \r.e.op1_RNICTUH[27]\ : MX2 - port map(A => \op1[27]\, B => \data_0[27]\, S => ldbp1_1, Y - => \un1_iu0_6[27]\); - - \comb.fpstdata.edata2_0_iv_RNO_2[2]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[2]\, Y => - \op1_i_m[2]\); - - \r.e.op2_RNO_9[26]\ : OR2B - port map(A => \result_0[26]\, B => d31, Y => - \result_m_i[26]\); - - \r.e.op2_RNO[18]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[18]\, Y => N_302); - - \r.e.op2_RNINDD6[9]\ : MX2 - port map(A => \op2[9]\, B => N_4256, S => ldbp2_3, Y => - \un1_iu0_5[75]\); - - \r.e.ctrl.pc_RNI7TJ11[30]\ : OR2B - port map(A => \pc_0[30]\, B => jmpl_4, Y => \cpi_m[175]\); - - \r.a.ctrl.pc[8]\ : DFN1E0 - port map(D => \dpc[8]\, CLK => lclk_c, E => holdn, Q => - \pc[8]\); - - \r.e.jmpl_RNI2VIHF1\ : AOI1B - port map(A => \shiftin_17[11]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[10]\, Y => \aluresult_1_iv_8[10]\); - - \r.e.aluop_0_RNI3K8O1[1]\ : MX2C - port map(A => \logicout_4[6]\, B => N_6838, S => N_6866_i_0, - Y => N_3629); - - \comb.branch_address.tmp_ADD_30x30_fast_I108_un1_Y\ : OR3C - port map(A => N407_0, B => N410, C => N473_0, Y => - I108_un1_Y); - - \r.f.pc_RNO_3[23]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[23]\, C => - \xc_trap_address_m[23]\, Y => \pc_1_iv_0[23]\); - - \r.f.pc_RNO_2[24]\ : OR2B - port map(A => I_143, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[22]\); - - \r.e.op2_RNO_8[27]\ : OR3B - port map(A => d29_0, B => \imm[27]\, C => \rsel2[0]\, Y => - \imm_m_i[27]\); - - \r.d.inst_0_0_0_RNIQ98I03[21]\ : NOR2B - port map(A => rst, B => N_4621, Y => - \inst_0_0_0_RNIQ98I03[21]\); - - \r.x.data_0_RNO_1[30]\ : NOR2A - port map(A => \data_0[30]\, B => ld_3, Y => \data_0_m[30]\); - - \r.a.ctrl.inst_RNI5H3O1_1[19]\ : NOR3 - port map(A => N_203, B => N_204, C => N_205, Y => N_208); - - un6_ex_add_res_d2_ADD_33x33_fast_I26_P0N : AO1A - port map(A => ldbp1_3, B => \op1[25]\, C => \data_0[25]\, Y - => N473_2); - - \r.e.aluop_RNI5NNF_0[1]\ : OR2A - port map(A => \aluop_1[0]\, B => \aluop_3[1]\, Y => - logicout21_1); - - \r.x.result_RNI4ATN5[0]\ : OR2A - port map(A => N_3687, B => \bpdata[0]\, Y => - \bpdata_i_m[0]\); - - \r.e.ctrl.cnt_RNILO7A[0]\ : OR3A - port map(A => \cnt[0]\, B => \cnt[1]\, C => annul, Y => - force_a2_0); - - \r.x.data_0_RNIJFO8[7]\ : MX2 - port map(A => \op1[7]\, B => \data_0_2[7]\, S => ldbp1_2, Y - => \un1_iu0_6[7]\); - - \r.a.ctrl.pc_RNIN3E2C[20]\ : MX2 - port map(A => \pc[20]\, B => N_3897, S => ex_bpmiss_1_0, Y - => \fe_pc[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I1_P0N\ : OR2 - port map(A => \inst_0_RNI1JUM[1]\, B => \dpc[3]\, Y => N362); - - \r.m.casa_RNI8BU9_2\ : NOR2A - port map(A => casa, B => N_3355_1, Y => un17_casaen_0_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I236_Y_1\ : AO1 - port map(A => N590, B => N575, C => ADD_30x30_fast_I236_Y_0, - Y => ADD_30x30_fast_I236_Y_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I263_Y_0 : AND2 - port map(A => I163_un1_Y, B => N566_i, Y => - ADD_33x33_fast_I263_Y_0); - - \r.x.npc_0_RNILNE41[0]\ : MX2C - port map(A => N_3220, B => N_3250, S => \npc_0[0]\, Y => - \xc_result[9]\); - - \r.w.result_RNI70P1[13]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[13]\, Y - => \result_m_0_0[13]\); - - \r.m.icc_RNO_4[2]\ : OR3C - port map(A => icc_0_sqmuxa_1_28, B => icc_0_sqmuxa_1_27, C - => icc_0_sqmuxa_1_29, Y => icc_0_sqmuxa_1_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I312_Y_0 : XOR2 - port map(A => N784_0, B => \un6_ex_add_res_s2_1[22]\, Y => - \un6_ex_add_res_s2[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I16_G0N : NOR2B - port map(A => \un1_iu0_6[15]\, B => \op2[15]\, Y => N442_0); - - \r.x.rstate_0_RNISNTD2[0]\ : MX2C - port map(A => N_3417, B => \xc_result[26]\, S => - \rstate_0[0]\, Y => \wdata[26]\); - - \r.m.y_RNO[11]\ : OR3C - port map(A => \y_iv_1[11]\, B => \y_iv_0[11]\, C => - \logicout_m[11]\, Y => \y_1[11]\); - - \r.m.ctrl.rd_RNIEK714[0]\ : NOR3C - port map(A => wreg_1_0_0, B => un2_rs1_2_0_i_0, C => - wreg_1_3, Y => wreg_1_6_0); - - \r.e.ldbp2_RNI8UML75\ : MX2C - port map(A => \un6_ex_add_res_s1_i[31]\, B => N_6577, S => - ldbp2_3, Y => \eaddress[30]\); - - \r.e.ctrl.pc[30]\ : DFN1E0 - port map(D => \pc[30]\, CLK => lclk_c, E => holdn, Q => - \pc_0[30]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I9_G0N\ : NOR2B - port map(A => \inst_0[9]\, B => \dpc[11]\, Y => N385); - - \r.x.data_0_RNO_2[6]\ : AO1B - port map(A => rdatav_0_1_1_iv_7(6), B => mcdo_m_0_4, C => - N_3456, Y => \dco_m_i[102]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I170_un1_Y\ : NOR2A - port map(A => N544, B => N537, Y => I170_un1_Y); - - \r.m.result[17]\ : DFN1E0 - port map(D => \eres2[17]\, CLK => lclk_c, E => holdn, Q => - \maddress[17]\); - - \r.d.inst_0_RNI4023_0[20]\ : OR2 - port map(A => \inst_0[20]\, B => \inst_0[19]\, Y => - un7_op_3); - - un6_ex_add_res_d2_ADD_33x33_fast_I148_Y : OR2B - port map(A => N549, B => N545_0, Y => N611); - - un6_ex_add_res_d0_ADD_33x33_fast_I9_P0N : OR3A - port map(A => \data_0[8]\, B => \op1[8]\, C => ldbp1_0, Y - => N422_0); - - \r.x.rstate_RNIKDGG[1]\ : NOR2 - port map(A => \rstate[1]\, B => xc_wreg9, Y => N_6352); - - \r.e.ctrl.inst_RNIB4OA3[26]\ : AOI1B - port map(A => ex_bpmiss_1_0_2_tz_0, B => - ex_bpmiss_1_0_1630_0, C => N_475, Y => ex_bpmiss_1_0_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I58_Y : NOR2B - port map(A => N452_0, B => N449_1, Y => N517_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I5_G0N : NOR2B - port map(A => \un1_iu0_6[4]\, B => \op2[4]\, Y => N409); - - \r.x.result_RNID4AN3[14]\ : MX2C - port map(A => \un1_iu0_6[14]\, B => \un1_p0_6[366]\, S => - bpdata6_0_0, Y => \bpdata[14]\); - - \r.x.data_0_RNO_4[8]\ : OR2A - port map(A => \data_0[8]\, B => ld_0_0, Y => - \data_0_m_i[8]\); - - \r.f.pc_RNI7DJ3E1[3]\ : MX2 - port map(A => I_5, B => N_4046, S => bpmiss_1_i_0_0, Y => - \pc_4[3]\); - - \r.f.pc[15]\ : DFN1E0 - port map(D => \pc_1[15]\, CLK => lclk_c, E => holdn, Q => - \fpc[15]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I55_Y_0_o3 : AOI1 - port map(A => N455_1, B => N451_2, C => N454_1, Y => N514_2); - - \r.w.result[22]\ : DFN1E0 - port map(D => \wdata[22]\, CLK => lclk_c, E => holdn, Q => - \result[22]\); - - \r.e.shleft_1_RNIGT5I1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[18]\, S => - shleft_1, Y => \shiftin_5[49]\); - - \r.f.pc_RNO[12]\ : AO1B - port map(A => I_56, B => un2_rstn_4_0_0, C => - \pc_1_iv_2[12]\, Y => \pc_1[12]\); - - \r.e.ctrl.inst_RNIVD3H1[24]\ : NOR3B - port map(A => un3_notag, B => \icc_7_m_0[1]\, C => - \icc_8_m_5[1]\, Y => \icc_7_m_2[1]\); - - \r.m.result[4]\ : DFN1E0 - port map(D => \eres2[4]\, CLK => lclk_c, E => holdn, Q => - \maddress[4]\); - - \r.a.ctrl.inst_RNIL82S[21]\ : OR2B - port map(A => illegal_inst37_2, B => N_58, Y => - illegal_inst37_4); - - \r.e.shcnt_RNIGVRBP[1]\ : MX2C - port map(A => \shiftin_14[19]\, B => \shiftin_14[17]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[17]\); - - \r.w.s.y_RNO[24]\ : NOR3 - port map(A => N_368, B => N_367, C => N_369, Y => N_6686); - - \r.a.imm_RNI5645[4]\ : OR3B - port map(A => d29_0_0, B => \imm[4]\, C => \rsel2_0[0]\, Y - => \imm_m_i[4]\); - - \r.x.dci.SIGNED_RNILER6N2\ : NOR3C - port map(A => me_signed_1, B => data_0_7, C => - rdata_3_sqmuxa, Y => \rdata_17_m[8]\); - - \r.x.data_0_RNO_4[5]\ : AO1 - port map(A => rdatav_0_1_0_iv_4_20, B => mcdo_m_0_27, C => - rdata_0_sqmuxa, Y => \dco_m_i[125]\); - - \r.m.result_RNO[21]\ : MX2 - port map(A => \aluresult[21]\, B => \op1[21]\, S => - un17_casaen_0_2, Y => \eres2[21]\); - - \r.a.ctrl.wreg_RNO_2\ : NOR2 - port map(A => ld_1_sqmuxa, B => un19_rd, Y => - un1_ld_1_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I247_Y : AO1 - port map(A => N665, B => N614_0, C => N664_1, Y => N808_0); - - \r.e.op1_RNI9HFC[5]\ : OR2B - port map(A => \op1[5]\, B => un14_casaen_s1_0, Y => N_407); - - \r.w.s.tba_RNIGOB0H[2]\ : NOR3C - port map(A => \aluresult_1_iv_3[14]\, B => \tba_m[2]\, C - => \aluresult_1_iv_5[14]\, Y => \aluresult_1_iv_6[14]\); - - \r.e.op2_RNIR6OP[22]\ : MX2B - port map(A => \op2[22]\, B => N_4269_i, S => ldbp2_0, Y => - \un1_iu0_5[88]\); - - \r.m.y_RNO_4[2]\ : OR2B - port map(A => \y_1[3]\, B => mulstep_0, Y => \y_m_2[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I86_Y : NOR2B - port map(A => N410_2, B => N407_1, Y => N545_0); - - \r.x.intack_RNI3VGC\ : OR2A - port map(A => intack_3, B => holdn, Y => intack_2); - - \r.e.shleft_0_RNI3TH32\ : MX2A - port map(A => \shiftin_5[26]\, B => shleft_0_RNIJ8HP, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[10]\); - - \r.e.aluop_1_RNIM9842[1]\ : MX2C - port map(A => \logicout_4[5]\, B => N_6835, S => N_6866_i, - Y => N_3628); - - \r.f.pc_RNIOTGB4[14]\ : MX2 - port map(A => \dpc[14]\, B => \fpc[14]\, S => ra_bpmiss_1, - Y => N_3891); - - \r.e.op2_RNO_6[21]\ : OR3C - port map(A => d28_0, B => \rsel2_1[0]\, C => - \un1_p0_6[373]\, Y => \cpi_m_i[373]\); - - \r.e.jmpl_RNINUSPJ1\ : AOI1B - port map(A => \shiftin_17[22]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[21]\, Y => \aluresult_1_iv_8[21]\); - - \r.e.ctrl.tt_RNO_0[3]\ : NOR3A - port map(A => \tt_1[3]\, B => cp_disabled_4, C => - fp_disabled_4, Y => \tt_3[3]\); - - \r.d.inst_0_RNIUB0N1[23]\ : NOR3C - port map(A => \inst_0_RNIMRAH[23]\, B => ldcheck1_1, C => - ldcheck1_2, Y => ldcheck1); - - \r.d.inst_0_RNIKMSG[20]\ : OAI1 - port map(A => wy_1_0_a3_1_0, B => N_152, C => N_142, Y => - un6_op); - - \r.x.data_0[24]\ : DFN1E0 - port map(D => \data_0_1[24]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[24]\); - - \r.a.imm[23]\ : DFN1E0 - port map(D => \un3_de_ren1[141]\, CLK => lclk_c, E => holdn, - Q => \imm[23]\); - - \r.x.result_RNI90AN3[13]\ : MX2C - port map(A => \un1_iu0_6[13]\, B => \un1_p0_6[365]\, S => - bpdata6, Y => \bpdata[13]\); - - \r.x.npc_RNIQBFL[0]\ : MX2C - port map(A => N_3239, B => N_3269, S => \npc[0]\, Y => - \xc_result[28]\); - - \r.m.ctrl.rd_RNIL7P71[6]\ : XNOR2 - port map(A => \rd_1[6]\, B => \un3_de_ren1[97]\, Y => - un2_rs1_2_6_i_0); - - \r.e.op1_RNIBUD2V5[21]\ : AOI1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[21]\, C - => \d_iv_3[21]\, Y => \d_i[21]\); - - \r.e.aluop_0_RNI7D7RA[0]\ : NOR2B - port map(A => \aluresult_1_iv_3[3]\, B => \logicout_m_0[3]\, - Y => \aluresult_1_iv_4[3]\); - - \r.e.aluop_2_RNIO5713[1]\ : MX2C - port map(A => N_3554, B => \logicout_3[27]\, S => - \aluop_2[1]\, Y => N_3586); - - \r.f.pc_RNO_6[23]\ : MX2 - port map(A => \fpc[23]\, B => \eaddress[23]\, S => jump, Y - => N_4066); - - \r.e.shcnt_RNIUM6M[1]\ : MX2C - port map(A => \shcnt[1]\, B => N_3305, S => ldbp2_1, Y => - \ex_shcnt_1_i[1]\); - - \r.a.rfe2_RNIVNBMB1\ : MX2 - port map(A => rfe, B => \rfe2\, S => holdn, Y => ren2); - - \r.a.nobp_RNIIMIG\ : OR3A - port map(A => un19_inst, B => icc_check_bp_1, C => nobp, Y - => \un9_icc_check_bp\); - - \r.e.op2_RNI9S3F_0[0]\ : OR2 - port map(A => \un1_iu0_6[0]\, B => \op2_RNI59C6[0]\, Y => - \logicout_3[0]\); - - \r.d.inst_0_RNI8K79[24]\ : NOR3B - port map(A => \inst_0[20]\, B => \inst_0_0[24]\, C => - \un1_p0_6_0[60]\, Y => icc_check7_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I136_Y\ : AOI1 - port map(A => N501_0, B => N498_0, C => N497_1, Y => N556_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I95_un1_Y : OR2B - port map(A => N496_1, B => N493, Y => I95_un1_Y_0); - - \r.x.y[19]\ : DFN1E0 - port map(D => \y_0[19]\, CLK => lclk_c, E => holdn, Q => - \y_2[19]\); - - \r.x.ctrl.pc[13]\ : DFN1E0 - port map(D => \pc_3[13]\, CLK => lclk_c, E => holdn, Q => - \pc_0[13]\); - - \r.w.s.tt[6]\ : DFN1E0 - port map(D => \xc_vectt_1[6]\, CLK => lclk_c, E => N_6747, - Q => \tt[6]\); - - \r.e.shcnt_RNIBF6RA[2]\ : MX2C - port map(A => \shiftin_11[16]\, B => \shiftin_11[12]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[12]\); - - \r.x.ctrl.tt[4]\ : DFN1E0 - port map(D => \tt2[4]\, CLK => lclk_c, E => holdn, Q => - \tt_0[4]\); - - \r.e.shleft_0_RNIAJFJ3\ : MX2 - port map(A => \shiftin_5[62]\, B => \shiftin_5[46]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[46]\); - - \r.e.op2_RNO_7[14]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[366]\, Y => \cpi_m_i[366]\); - - \r.e.op1_RNIM6IR3[28]\ : NOR3C - port map(A => \rfo_m[28]\, B => \d_iv_1[28]\, C => - \op1_m_0[28]\, Y => \d_iv_3[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I203_Y : OR2 - port map(A => N606_1, B => I203_un1_Y, Y => N672_0); - - un6_fe_npc_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \fe_pc[5]\, C => - \fe_pc[6]\, Y => N_136); - - \r.x.ctrl.pc_RNICAHF[14]\ : MX2 - port map(A => \pc_0[14]\, B => \pc_1[14]\, S => \npc_0[1]\, - Y => N_3225); - - \r.x.result_RNIPMDE5[13]\ : NOR2B - port map(A => \bpdata[13]\, B => \aluop_RNIGM3N1[2]\, Y => - \bpdata_i_m[13]\); - - \r.w.s.y_RNO[20]\ : MX2 - port map(A => \y_2[20]\, B => \result[20]\, S => N_481_0, Y - => N_3784); - - \r.e.jmpl_RNI3K1NL_0\ : OR2B - port map(A => \shiftin_17[7]\, B => aluresult_2_sqmuxa_0, Y - => \shiftin_17_m_0[7]\); - - un6_fe_npc_I_108 : AND3 - port map(A => \fe_pc[17]\, B => \fe_pc[18]\, C => - \fe_pc[19]\, Y => \DWACT_FINC_E[12]\); - - \r.m.icc_RNO_23[2]\ : NOR2 - port map(A => \logicout[17]\, B => \logicout[18]\, Y => - icc_0_sqmuxa_1_7); - - \r.e.op1_RNIHEJA12[1]\ : OR2B - port map(A => \d_1_iv_4[1]\, B => \aluresult_m_i[1]\, Y => - \d_1[1]\); - - \r.e.aluop_RNIKJIJ1[2]\ : XA1 - port map(A => \un1_iu0_5[80]\, B => \aluop_1[2]\, C => - \un1_iu0_6[14]\, Y => N_3541); - - \comb.branch_address.tmp_ADD_30x30_fast_I75_Y\ : AND2 - port map(A => N374, B => N377, Y => N492); - - \r.e.op1_RNIQ8NO6[31]\ : NOR3C - port map(A => un4_icc_m, B => \op1_i_m[31]\, C => - \bpdata_i_m[31]\, Y => \edata2_iv_1[31]\); - - \r.d.inst_0_RNI7S13[17]\ : OR2 - port map(A => \inst_0[18]\, B => \inst_0[17]\, Y => - un26_rs1opt); - - \r.x.ctrl.ld_0_RNISHEJ\ : NOR3C - port map(A => N_3355_1, B => rd_7_i_0, C => ld_0, Y => - bpdata6_8); - - \r.d.inst_0_RNO[20]\ : NOR2B - port map(A => rst, B => N_4620, Y => \inst_0_RNO[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I129_Y : AO1B - port map(A => N530_0, B => N527_1, C => - ADD_33x33_fast_I129_Y_0_0, Y => N592_1); - - \r.e.alusel[1]\ : DFN1E0 - port map(D => N_3840, CLK => lclk_c, E => holdn, Q => - \alusel[1]\); - - \r.e.aluop_1_RNIA1393[1]\ : MX2C - port map(A => \logicout_4[27]\, B => N_6892, S => N_6866_i, - Y => N_3650); - - \r.d.pv_RNO_9\ : NOR2A - port map(A => \inst_0[30]\, B => annul_1, Y => - pv_12_i_a6_0_1); - - \r.m.y_RNO_0[1]\ : AOI1B - port map(A => wy_1_0, B => \y_0[1]\, C => N_378, Y => - \y_iv_0_1[1]\); - - \r.e.aluop_RNIA3IJ1[2]\ : XA1 - port map(A => \un1_iu0_5[78]\, B => \aluop_1[2]\, C => - \un1_iu0_6[12]\, Y => N_3539); - - \r.f.pc_RNIOTOUQ2[6]\ : MX2 - port map(A => I_20, B => N_4049, S => bpmiss_1_i_0_0, Y => - \pc_4[6]\); - - \comb.irq_trap.un3_irl\ : AO1 - port map(A => un5_irl_1, B => un5_irl_0, C => un2_irl, Y - => un3_irl); - - un6_fe_npc_I_87 : AND3 - port map(A => \fe_pc[14]\, B => \fe_pc[15]\, C => - \fe_pc[16]\, Y => \DWACT_FINC_E[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I124_Y\ : OR3 - port map(A => I68_un1_Y, B => N385, C => I124_un1_Y, Y => - N544); - - \r.x.data_0_RNO_5[4]\ : OR2A - port map(A => \data_0[4]\, B => ld_0_0, Y => - \data_0_m_i[4]\); - - \r.e.ctrl.pc_RNI9DK11[14]\ : OR2B - port map(A => \pc_1[14]\, B => jmpl_4, Y => \cpi_m[159]\); - - \r.m.y_RNIS9Q5C[30]\ : NOR3C - port map(A => \aluop_RNIC8EB4[1]\, B => - \aluresult_1_iv_0[30]\, C => \aluop_RNI143R4[2]\, Y => - \aluresult_1_iv_4[30]\); - - \comb.fpstdata.edata2_0_iv_RNO_1[2]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[2]\, Y => - \ex_op1_i_m[2]\); - - \r.f.pc_RNO[27]\ : AO1B - port map(A => I_173, B => un2_rstn_4_0_0, C => - \pc_1_iv_2[27]\, Y => \pc_1[27]\); - - \r.e.aluop_1_RNIID791[1]\ : XOR3 - port map(A => \un1_iu0_6[29]\, B => \aluop_1[1]\, C => - \un1_iu0_5[95]\, Y => N_6850); - - \r.x.ctrl.wy_RNIMKUI\ : NOR3 - port map(A => wy_1, B => wy_2, C => wy_0, Y => wy_RNIMKUI); - - \r.e.op1_RNIQG5I1[1]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[1]\, Y => - \ex_op1_i_m[1]\); - - \r.e.op1_RNIJS6S62[2]\ : OR3C - port map(A => \op1_m_0[2]\, B => \d_iv_2[2]\, C => - \aluresult_m_0[2]\, Y => \d[2]\); - - \r.d.inst_0_RNO[17]\ : NOR2B - port map(A => rst, B => N_4617, Y => \inst_0_RNO[17]\); - - \r.e.op2_RNIQKAP[6]\ : OR2A - port map(A => \un1_iu0_5[72]\, B => \un1_iu0_6[6]\, Y => - \logicout_4[6]\); - - wovf_exc_1_sqmuxa : NOR2A - port map(A => un7_op, B => \wovf_exc_0_sqmuxa\, Y => - \wovf_exc_1_sqmuxa\); - - \r.e.op2_RNO_6[31]\ : OR2B - port map(A => data2(31), B => d25, Y => \rfo_m_i[63]\); - - \r.d.pv_RNI83B6_0\ : NOR2 - port map(A => pv, B => annul_2, Y => un23_exbpmiss_0); - - \r.x.data_0_RNO_2[3]\ : OR2A - port map(A => data_0_0_27, B => rdata_0_sqmuxa, Y => - \dco_m_i[123]\); - - \r.x.data_0_RNI8F9E[11]\ : XOR2 - port map(A => \data_0_2[11]\, B => invop2_1, Y => N_4258); - - \r.e.aluop_RNIFFBU6[0]\ : OR2B - port map(A => \logicout[27]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[27]\); - - \r.e.jmpl_RNI3K1NL\ : NAND2 - port map(A => aluresult_1_sqmuxa_0, B => \shiftin_17[7]\, Y - => \shiftin_17_m[7]\); - - \r.m.ctrl.inst_RNIM8PR2[21]\ : OA1 - port map(A => \inst_RNI884O1[22]\, B => inst_1, C => - result_1, Y => trap_0_sqmuxa_4); - - \r.f.pc_RNO_3[31]\ : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[31]\, C => - \xc_trap_address_m[31]\, Y => \pc_1_iv_0[31]\); - - \r.a.ctrl.inst_RNIRS231[23]\ : NOR2 - port map(A => N_515, B => N_487, Y => illegal_inst33); - - \r.x.ctrl.inst[26]\ : DFN1E0 - port map(D => \inst_3[26]\, CLK => lclk_c, E => holdn, Q - => \inst[26]\); - - \r.m.result_RNIFJD4[27]\ : OR2B - port map(A => d13_0, B => \maddress[27]\, Y => - \result_m_0[27]\); - - \r.e.op2_RNO_0[17]\ : OR3C - port map(A => \op1_m_i[17]\, B => \d_1_iv_3[17]\, C => - \aluresult_m_i[17]\, Y => \d_1[17]\); - - \r.d.inst_0_RNO_0[8]\ : MX2 - port map(A => data_0_2_8, B => \inst_0[8]\, S => - inull_RNIFV6VG2_0, Y => N_4608); - - \r.d.pc[3]\ : DFN1 - port map(D => \pc_RNO[3]\, CLK => lclk_c, Q => \dpc[3]\); - - \r.e.op2_RNO_5[10]\ : OR2B - port map(A => \result_0[10]\, B => d31, Y => - \result_m_i[10]\); - - \r.e.ldbp1_0\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_0); - - \r.a.cwp[0]\ : DFN1E0 - port map(D => \cwp_0[0]\, CLK => lclk_c, E => holdn, Q => - \cwp_2[0]\); - - \r.x.ctrl.rd_RNICV3D[5]\ : XA1A - port map(A => \rd[5]\, B => \rd_0[5]\, C => rd_6_i_0, Y => - bpdata6_4); - - \r.a.ctrl.inst_RNINU2KD[21]\ : OR3C - port map(A => inst_14, B => illegal_inst34_3, C => - un1_illegal_inst33_2, Y => un1_illegal_inst33); - - \comb.branch_address.tmp_ADD_30x30_fast_I13_P0N\ : OR2 - port map(A => \inst_0[13]\, B => \dpc[15]\, Y => N398_2); - - \r.x.npc_RNIQABL[0]\ : MX2C - port map(A => N_3231, B => N_3261, S => \npc[0]\, Y => - \xc_result[20]\); - - \r.e.ctrl.inst_RNIJ8JA[27]\ : AOI1 - port map(A => \inst_1[27]\, B => \icc_0[0]\, C => - \icc_0[2]\, Y => ex_bpmiss_1_0_a5_3_0); - - \r.x.ctrl.wy\ : DFN1E0 - port map(D => wy_1, CLK => lclk_c, E => holdn, Q => wy_2); - - \r.x.ctrl.inst_RNISL1E_0[22]\ : NOR2A - port map(A => \inst_0[22]\, B => \inst_1[19]\, Y => - cwp_2_sqmuxa_1); - - \r.x.result[15]\ : DFN1E0 - port map(D => \maddress[15]\, CLK => lclk_c, E => holdn, Q - => \result_0[15]\); - - \r.x.result_RNIH22O3[23]\ : MX2 - port map(A => \un1_iu0_6[23]\, B => \un1_p0_6[375]\, S => - bpdata6, Y => \bpdata[23]\); - - \r.e.jmpl_RNI31UJV\ : OR2B - port map(A => \shiftin_17[30]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[30]\); - - \r.a.ctrl.inst_RNI3RNK9[19]\ : OR2 - port map(A => illegal_inst_7_iv_2_0_a5_0_1, B => N_603, Y - => \inst_RNI3RNK9[19]\); - - \r.e.mulstep\ : DFN1E0 - port map(D => N_227, CLK => lclk_c, E => holdn, Q => - mulstep); - - \r.w.s.tt[1]\ : DFN1 - port map(D => \tt_RNO[1]\, CLK => lclk_c, Q => \irl[1]\); - - \r.e.op1_RNO[24]\ : MX2C - port map(A => \d_i[24]\, B => \d_i[25]\, S => N_227, Y => - \aop1[24]\); - - \r.d.inst_0_RNO[15]\ : NOR2B - port map(A => rst, B => N_4615, Y => \inst_0_RNO[15]\); - - \r.a.ctrl.inst_RNILPIS7[23]\ : OR2B - port map(A => \inst_1[23]\, B => N_474, Y => N_603); - - \comb.branch_address.tmp_ADD_30x30_fast_I270_Y_0_0\ : XOR2 - port map(A => \dpc[12]\, B => \inst_0[10]\, Y => - ADD_30x30_fast_I270_Y_0_0); - - \r.e.op2_RNO_8[7]\ : OR3B - port map(A => d29_0_0, B => \imm[7]\, C => \rsel2_0[0]\, Y - => \imm_m_i[7]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_un1_Y_0 : NOR2B - port map(A => N629_1, B => N645_0, Y => - ADD_33x33_fast_I261_un1_Y_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I312_Y_0 : XNOR2 - port map(A => N784, B => \un6_ex_add_res_s2_1[22]\, Y => - \un6_ex_add_res_s0[22]\); - - \r.x.ctrl.tt_RNO[1]\ : OR2B - port map(A => N_4210_i_0, B => N_4205, Y => \tt2[1]\); - - \r.e.aluop_RNIOJAJ2[1]\ : OR2 - port map(A => aluresult_6_sqmuxa, B => N_3957_1, Y => - N_3957); - - \r.m.y_RNO_2[29]\ : OR2B - port map(A => \y[29]\, B => y08, Y => N_416); - - \comb.branch_address.tmp_ADD_30x30_fast_I288_Y_0\ : XOR2 - port map(A => N696, B => ADD_30x30_fast_I288_Y_0_0, Y => - \tmp[30]\); - - \r.w.s.tba[5]\ : DFN1E1 - port map(D => \result_0[17]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[5]\); - - \r.e.op1_RNIB8EM42[3]\ : OR3C - port map(A => \op1_m_0[3]\, B => \d_iv_2[3]\, C => - \aluresult_m_0[3]\, Y => \d[3]\); - - \r.a.ctrl.pc_RNISGM0C[9]\ : MX2 - port map(A => \pc_0[9]\, B => N_3886, S => ex_bpmiss_1_0, Y - => \fe_pc[9]\); - - \r.e.ctrl.inst_RNI792S[24]\ : NOR3C - port map(A => \inst[19]\, B => \inst[24]\, C => un3_notag, - Y => \icc_8_m_1[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I3_G0N : NOR3A - port map(A => \op1[2]\, B => ldbp1_2, C => \data_0[2]\, Y - => N403_0); - - \r.e.shcnt_RNIUQ6M[2]\ : MX2C - port map(A => \shcnt[2]\, B => N_3306, S => ldbp2_0, Y => - \ex_shcnt_1_i_0[2]\); - - \r.a.rsel1_RNI5L1QF2[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[7]\, Y - => \aluresult_m_0[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I119_Y : AO1 - port map(A => N520_0, B => N517, C => N516, Y => N582_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I171_Y : AO1 - port map(A => N582_2, B => N575_2, C => N574_0, Y => N640_1); - - \r.e.shcnt_RNIQDP4T[1]\ : MX2C - port map(A => \shiftin_14[28]\, B => \shiftin_14[26]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[26]\); - - \r.e.jmpl_RNIH1GEJ\ : OR2B - port map(A => \shiftin_17[1]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[1]\); - - \r.f.pc[18]\ : DFN1E0 - port map(D => \pc_1[18]\, CLK => lclk_c, E => holdn, Q => - \fpc[18]\); - - \r.e.aluop_RNIR2AF5[0]\ : MX2C - port map(A => N_3579, B => N_3643, S => \aluop_1[0]\, Y => - \logicout[20]\); - - \r.f.pc[24]\ : DFN1E0 - port map(D => \pc_1[24]\, CLK => lclk_c, E => holdn, Q => - \fpc[24]\); - - \r.f.pc_RNI9GM4[7]\ : OR2A - port map(A => \fpc[7]\, B => rst, Y => \pc_m[7]\); - - \r.f.pc_RNI4Q2IL[8]\ : MX2 - port map(A => \fpc[8]\, B => \eaddress[8]\, S => jump_0, Y - => N_4051); - - \r.m.y_RNO_0[17]\ : NOR3C - port map(A => \y_m[18]\, B => \y_m_0[17]\, C => - \y_iv_1[17]\, Y => \y_iv_2[17]\); - - \r.f.pc_RNO_0[21]\ : NAND2 - port map(A => \tmp[21]\, B => \un2_rstn_5\, Y => - \tmp_m[21]\); - - \comb.lock_gen.un1_icc_check5_RNIRTRJ\ : AO1 - port map(A => un1_icc_check5_1_0, B => un1_icc_check5, C - => un1_inst, Y => ldcheck2_0_sqmuxa_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I219_Y\ : AO1 - port map(A => N614, B => N599, C => N598, Y => N729); - - \comb.branch_address.tmp_ADD_30x30_fast_I114_un1_Y\ : NOR2B - port map(A => N479_0, B => N476_0, Y => I114_un1_Y); - - \r.e.aluop_RNI2QON_0[1]\ : NOR3A - port map(A => logicout19_0, B => \aluop_3[1]\, C => - aluresult_9_sqmuxa_1, Y => aluresult_6_sqmuxa); - - \r.a.imm[28]\ : DFN1E0 - port map(D => \un3_de_ren1[146]\, CLK => lclk_c, E => holdn, - Q => \imm[28]\); - - \r.f.pc_RNI00F6B2[5]\ : MX2 - port map(A => I_13, B => N_4048, S => bpmiss_1_i_0, Y => - \pc_4[5]\); - - \r.e.ctrl.inst_RNIQT1J7[26]\ : NOR2 - port map(A => ex_bpmiss_1_0_1, B => ex_bpmiss_1_0_2, Y => - ex_bpmiss_1_0); - - \r.e.ctrl.pc_RNIDOTN2[24]\ : NOR2A - port map(A => \cpi_m[169]\, B => \aluresult_6[31]\, Y => - \aluresult_1_iv_1[24]\); - - \r.e.aluop_RNI357O6[0]\ : MX2C - port map(A => N_3578, B => N_3642, S => \aluop_1[0]\, Y => - \logicout[19]\); - - un37_ra_I_14 : XOR2 - port map(A => \cwp_0[2]\, B => - \DWACT_ADD_CI_0_g_array_1_0[0]\, Y => I_14_0); - - \r.a.wovf\ : DFN1E0 - port map(D => \wovf_exc_0_sqmuxa_1\, CLK => lclk_c, E => - holdn, Q => wovf); - - \r.d.inst_0_RNO[31]\ : NOR2B - port map(A => rst, B => N_4631, Y => \inst_0_RNO[31]\); - - \r.d.pc_RNO[8]\ : MX2 - port map(A => \fpc[8]\, B => \dpc[8]\, S => N_6763_i_0, Y - => \pc_RNO[8]\); - - \r.d.inst_0_RNIFA35[28]\ : XOR2 - port map(A => \inst_0[28]\, B => N_211, Y => branch_4_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I127_Y : OAI1 - port map(A => N525_0, B => N528_2, C => N524_1, Y => N590_1); - - \r.e.op2_RNO_3[18]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[18]\, Y => - \aluresult_m_i[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I147_Y\ : NOR3C - port map(A => N462, B => N_14, C => N513, Y => N573); - - \r.e.shcnt_RNINTG101[1]\ : MX2 - port map(A => \shiftin_14[34]\, B => \shiftin_14[32]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[32]\); - - \r.f.pc[30]\ : DFN1E0 - port map(D => \pc_1[30]\, CLK => lclk_c, E => holdn, Q => - \fpc[30]\); - - \r.e.jmpl_RNITT2412\ : NOR3C - port map(A => \shiftin_17_m[9]\, B => \aluresult_1_iv_7[8]\, - C => \shiftin_17_m_0[8]\, Y => \aluresult_1_iv_9[8]\); - - \r.e.alusel_RNO_4[1]\ : NOR2 - port map(A => N_259, B => N_201, Y => N_339); - - \r.x.ctrl.tt_RNI5HVQ[0]\ : MX2 - port map(A => \result[0]\, B => \tt[0]\, S => tt_i, Y => - N_3319); - - \r.d.inst_0[5]\ : DFN1 - port map(D => \inst_0_RNO[5]\, CLK => lclk_c, Q => - \inst_0[5]\); - - \r.e.op2_RNO_4[13]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[365]\, Y => \cpi_m_i[365]\); - - \r.x.intack\ : DFN1E0 - port map(D => intack, CLK => lclk_c, E => holdn, Q => - intack_3); - - \comb.irq_trap.op_gt.un2_irl_0_I_1\ : NOR2A - port map(A => irl_0(0), B => \pil[0]\, Y => \ACT_LT4_E[0]\); - - \r.x.ctrl.pc[11]\ : DFN1E0 - port map(D => \pc_1[11]\, CLK => lclk_c, E => holdn, Q => - \pc_0[11]\); - - \r.e.aluop_RNIFN473[1]\ : MX2C - port map(A => N_3558, B => \logicout_3[31]\, S => - \aluop_3[1]\, Y => N_3590); - - \r.d.inst_0_RNO[1]\ : NOR2B - port map(A => rst, B => N_4601, Y => \inst_0_RNO[1]\); - - \r.x.ctrl.pc[22]\ : DFN1E0 - port map(D => \pc_3[22]\, CLK => lclk_c, E => holdn, Q => - \pc_0[22]\); - - \r.e.aluop_0_RNI5ALC[1]\ : XOR3 - port map(A => \un1_iu0_6[9]\, B => \aluop_0[1]\, C => - \un1_iu0_5[75]\, Y => N_6841); - - \r.e.op1_RNICDID[28]\ : MX2 - port map(A => \op1[28]\, B => \data_0[28]\, S => ldbp1, Y - => \un1_iu0_6[28]\); - - \r.x.y[14]\ : DFN1E0 - port map(D => \y_0[14]\, CLK => lclk_c, E => holdn, Q => - \y_2[14]\); - - \r.d.pc[24]\ : DFN1 - port map(D => \pc_RNO[24]\, CLK => lclk_c, Q => \dpc[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I64_Y_0\ : AO1 - port map(A => N392, B => N388, C => N391, Y => N481_2); - - \r.e.ctrl.pc[17]\ : DFN1E0 - port map(D => \pc[17]\, CLK => lclk_c, E => holdn, Q => - \pc_0[17]\); - - \r.e.ldbp2_0_RNIKIIIS\ : OR2A - port map(A => \eaddress[10]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[11]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I38_Y : AND2 - port map(A => N479, B => N482, Y => N497); - - \r.e.op2_RNIARVJ[24]\ : MX2 - port map(A => \op2[24]\, B => N_4271, S => ldbp2_2, Y => - \un1_iu0_5[90]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I300_Y_0 : XOR2 - port map(A => N814, B => ADD_33x33_fast_I300_Y_0_0, Y => - \un6_ex_add_res_s1[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I273_un1_Y_0 : NOR2B - port map(A => N552, B => N669, Y => - ADD_33x33_fast_I273_un1_Y_0); - - \r.e.op2_RNO[6]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[6]\, Y => N_290); - - \r.a.imm[12]\ : DFN1E0 - port map(D => \un3_de_ren1[130]\, CLK => lclk_c, E => holdn, - Q => \imm[12]\); - - \r.m.y_RNIP1O71[21]\ : OR2B - port map(A => \y[21]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[21]\); - - \r.f.pc_RNO_3[15]\ : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[15]\, C => - \xc_trap_address_m[15]\, Y => \pc_1_iv_0[15]\); - - \r.d.inst_0[1]\ : DFN1 - port map(D => \inst_0_RNO[1]\, CLK => lclk_c, Q => - \inst_0[1]\); - - \r.x.npc_0_RNI5TS61[0]\ : MX2C - port map(A => N_3225, B => N_3255, S => \npc_0[0]\, Y => - \xc_result[14]\); - - \r.f.pc_RNO_4[19]\ : MX2 - port map(A => I_105, B => N_4062, S => bpmiss_1_i_0, Y => - \pc_4[19]\); - - \r.f.pc[21]\ : DFN1E0 - port map(D => \pc_1[21]\, CLK => lclk_c, E => holdn, Q => - \fpc[21]\); - - \r.a.ctrl.wreg_RNO_0\ : MX2A - port map(A => un1_ld_1_sqmuxa_1, B => \inst_0_0[21]\, S => - un1_ld_1_sqmuxa, Y => write_reg); - - un6_ex_add_res_d0_ADD_33x33_fast_I46_Y : NOR2A - port map(A => N467_2, B => N470_1, Y => N505_1); - - \r.m.result_RNIVI8B3[23]\ : NOR3C - port map(A => \d_iv_0[23]\, B => \result_m_0[23]\, C => - \rfo_m[23]\, Y => \d_iv_2[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I11_G0N : NOR2B - port map(A => \un1_iu0_6[10]\, B => \op2[10]\, Y => N427_1); - - \r.x.y[16]\ : DFN1E0 - port map(D => \y[16]\, CLK => lclk_c, E => holdn, Q => - \y_2[16]\); - - \r.e.shcnt_RNI04UKN[1]\ : MX2C - port map(A => \shiftin_14[15]\, B => \shiftin_14[13]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[13]\); - - \r.e.ctrl.pc[22]\ : DFN1E0 - port map(D => \pc[22]\, CLK => lclk_c, E => holdn, Q => - \pc_2[22]\); - - \r.e.ctrl.rd_RNIA7GD7[0]\ : OR3C - port map(A => wreg_2_4, B => wreg_2_3, C => wreg_2_5, Y => - wreg_2_1); - - \r.e.alusel_RNO_4[0]\ : NOR2A - port map(A => \inst[31]\, B => \cnt_2[1]\, Y => - \alusel_i_0_a5_0_0[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0_0\ : MIN3 - port map(A => \dpc[29]\, B => \inst_0_RNI8AJ4[27]\, C => - N436_0, Y => ADD_30x30_fast_I233_Y_0_0); - - \r.m.ctrl.inst[20]\ : DFN1E0 - port map(D => \inst_1[20]\, CLK => lclk_c, E => holdn, Q - => \inst_3[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I244_Y : OR2 - port map(A => I244_un1_Y, B => N658, Y => N799); - - \r.e.shcnt_RNI69NRU[1]\ : MX2B - port map(A => \shiftin_14[32]\, B => \shiftin_14[30]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[30]\); - - \r.m.ctrl.inst_RNI2Q1S[21]\ : NOR3A - port map(A => \inst_0[24]\, B => \inst[21]\, C => - trap_0_sqmuxa_1_1_i, Y => iflush_1_0); - - \r.f.pc_RNO[19]\ : OR3C - port map(A => \tmp_m[19]\, B => \pc_1_iv_1[19]\, C => - \un6_fe_npc_m[17]\, Y => \pc_1[19]\); - - \r.w.result_RNI74P1[20]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[20]\, - Y => \result_m_0_0[20]\); - - \r.e.op2_RNO_7[11]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[363]\, Y => \cpi_m_i[363]\); - - \r.e.op1_RNIR69G[25]\ : OR2B - port map(A => \op1[25]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[25]\); - - \r.a.ctrl.inst[28]\ : DFN1E0 - port map(D => \inst_0[28]\, CLK => lclk_c, E => holdn, Q - => \inst_1[28]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I261_Y_0_0\ : XOR2 - port map(A => \dpc[3]\, B => \inst_0_RNI1JUM[1]\, Y => - ADD_30x30_fast_I261_Y_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I5_P0N : AO1A - port map(A => ldbp1_1, B => \op1[4]\, C => \data_0[4]\, Y - => N410_2); - - \r.e.shcnt_RNI1V6M[3]\ : MX2C - port map(A => \shcnt[3]\, B => N_3307, S => ldbp2_1, Y => - \ex_shcnt_1_i[3]\); - - \r.d.inull_RNIP82GO\ : AOI1 - port map(A => N_3014, B => G_6_1, C => un1_exbpmiss, Y => - annul_current_4); - - \r.f.pc_RNO_2[22]\ : OR2B - port map(A => I_129, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I192_Y : NOR2B - port map(A => N603, B => N595_1, Y => N661); - - \r.x.result_RNIG7JA[0]\ : MX2 - port map(A => \result[0]\, B => \data_0[0]\, S => ld_0, Y - => \un1_p0_6[352]\); - - \r.m.y_RNO_2[10]\ : OR2A - port map(A => \logicout[10]\, B => y14, Y => - \logicout_m[10]\); - - \r.e.op2_RNO_4[30]\ : OA1A - port map(A => \maddress[30]\, B => d27_0, C => - \cpi_m_i[382]\, Y => \d_1_iv_1[30]\); - - \r.e.op2_RNIHB971_0[11]\ : OR2 - port map(A => \un1_iu0_6[11]\, B => \un1_iu0_5[77]\, Y => - \logicout_3[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I55_Y\ : NOR2B - port map(A => N407_0, B => N404_0, Y => N472); - - \r.e.alusel_RNIJTTQ[0]\ : OR2 - port map(A => miscout_11_sqmuxa_0, B => logicout22_1, Y => - miscout_11_sqmuxa); - - \r.w.s.ps_RNIC1HI2\ : AO1B - port map(A => rstate_8_0, B => pil_0_sqmuxa, C => ps, Y => - ps_m); - - \r.a.ctrl.wreg_RNILGCE\ : OA1A - port map(A => ldchkra_0, B => call_hold7_i, C => wreg_0, Y - => wreg_6); - - \r.x.npc_0_RNI7DS61[0]\ : MX2C - port map(A => N_3234, B => N_3264, S => \npc_0[0]\, Y => - \xc_result[23]\); - - \r.d.inst_0_RNI7AJ4[26]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[26]\, S => - \inst_0[30]\, Y => \inst_0_1[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I198_Y : NOR2B - port map(A => N609_1, B => N601_0, Y => N667); - - \r.w.s.wim_RNI6V3N2[0]\ : MX2 - port map(A => \wim[0]\, B => \result[0]\, S => wim_1_sqmuxa, - Y => \wim_1[0]\); - - \r.e.op2_RNO_1[5]\ : OR2B - port map(A => \op1[5]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[5]\); - - \r.m.y_RNO_3[8]\ : OR3A - port map(A => \y_2[8]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[8]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I205_un1_Y : NOR3C - port map(A => N545_1, B => N549_0, C => N552, Y => - I205_un1_Y_0); - - \r.m.ctrl.inst_RNIVC0E_0[30]\ : OR2A - port map(A => \inst_1[31]\, B => \inst_1[30]\, Y => trap63); - - \comb.branch_address.tmp_ADD_30x30_fast_I23_G0N\ : NOR2B - port map(A => \inst_0_1[25]\, B => \dpc[25]\, Y => N427); - - un6_ex_add_res_d1_ADD_33x33_fast_I51_un1_Y : NOR3C - port map(A => \op2[20]\, B => \un1_iu0_6[20]\, C => N461_0, - Y => I51_un1_Y); - - un6_ex_add_res_d0_ADD_33x33_fast_I203_Y : AO1A - port map(A => N607_1, B => N614_1, C => N606_0, Y => N672_1); - - \r.m.icc_RNO_5[2]\ : NOR3C - port map(A => icc_0_sqmuxa_1_14, B => icc_0_sqmuxa_1_13, C - => icc_0_sqmuxa_1_24, Y => icc_0_sqmuxa_1_28); - - \r.e.op1_RNI7DUH[23]\ : MX2 - port map(A => \op1[23]\, B => \data_0[23]\, S => ldbp1_4, Y - => \un1_iu0_6[23]\); - - \r.e.aluop_RNI7NNF_0[1]\ : OR2A - port map(A => \aluop_1[2]\, B => \aluop_3[1]\, Y => - N_6866_i); - - \r.d.inst_0_RNI2NUM[2]\ : NOR2B - port map(A => \inst_0[2]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI2NUM[2]\); - - \r.a.ctrl.inst_RNISK2A1[21]\ : OR2A - port map(A => un1_aop2_1_sqmuxa_0_a2_0_0, B => N_204, Y => - N_457); - - \r.w.s.dwt_RNO_2\ : NOR3A - port map(A => dwt_1_sqmuxa_2, B => \inst[27]\, C => - \inst[26]\, Y => dwt_1_sqmuxa_3); - - \r.e.aluop_RNIVLQ53[0]\ : MX2C - port map(A => N_3563, B => N_3627, S => \aluop_1[0]\, Y => - \logicout[4]\); - - \r.e.aluop_0_RNI8330N[0]\ : AOI1B - port map(A => \logicout[22]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[22]\, Y => \aluresult_1_iv_7[22]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I244_Y : AO1 - port map(A => N674_1, B => N659, C => N658_1, Y => N799_1); - - \r.m.icc_RNISN961[0]\ : OR2A - port map(A => \icc_0[0]\, B => aluresult_11_sqmuxa, Y => - \icc_m[0]\); - - \r.a.ctrl.inst_RNI5KB1T[13]\ : NOR3C - port map(A => \cpi_m[121]\, B => illegal_inst_7_iv_3, C => - \inst_RNI3RNK9[19]\, Y => illegal_inst_7_iv_6_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I146_Y : NOR3C - port map(A => N407_1, B => N404_1, C => N543_1, Y => N609); - - \r.w.result_RNIUN5J[20]\ : AOI1B - port map(A => \un1_p0_6[372]\, B => d14_0, C => - \result_m_0_0[20]\, Y => \d_iv_0[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I109_Y_0\ : OA1 - port map(A => \dpc[16]\, B => \inst_0[14]\, C => N404_0, Y - => ADD_30x30_fast_I109_Y_0); - - \r.m.y[8]\ : DFN1E0 - port map(D => \y_1[8]\, CLK => lclk_c, E => holdn, Q => - \y[8]\); - - \r.x.y[12]\ : DFN1E0 - port map(D => \y[12]\, CLK => lclk_c, E => holdn, Q => - \y_2[12]\); - - \r.x.data_0[6]\ : DFN1E0 - port map(D => \data_0_1[6]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[6]\); - - \r.x.data_0[20]\ : DFN1E0 - port map(D => \data_0_1[20]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_2[20]\); - - \r.m.result[7]\ : DFN1E0 - port map(D => \eres2[7]\, CLK => lclk_c, E => holdn, Q => - \maddress[7]\); - - \r.f.pc_RNO_6[17]\ : MX2 - port map(A => \fpc[17]\, B => \eaddress[17]\, S => jump_0, - Y => N_4060); - - \r.x.data_0_RNO_1[12]\ : AO1A - port map(A => rdata_5_sqmuxa, B => data_0_0_28, C => - \data_0_m[12]\, Y => \data_0_1_0_iv_0[12]\); - - \r.w.result_RNI0MDI[12]\ : AOI1B - port map(A => \un1_p0_6[364]\, B => d14_0, C => - \result_m_0_0[12]\, Y => \d_iv_0[12]\); - - \r.m.ctrl.pc[27]\ : DFN1E0 - port map(D => \pc[27]\, CLK => lclk_c, E => holdn, Q => - \pc_2[27]\); - - \r.f.pc[26]\ : DFN1E0 - port map(D => \pc_1[26]\, CLK => lclk_c, E => holdn, Q => - \fpc[26]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I29_G0N : NOR2B - port map(A => \un1_iu0_6[28]\, B => \op2[28]\, Y => N481_0); - - \r.w.s.pil[2]\ : DFN1E0 - port map(D => \result[10]\, CLK => lclk_c, E => N_6699, Q - => \pil[2]\); - - \r.m.y[27]\ : DFN1E0 - port map(D => \y_1[27]\, CLK => lclk_c, E => holdn, Q => - \y_0[27]\); - - \r.e.aluop_RNIO1I14[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[2]\, Y => - \bpdata_i_m_2[2]\); - - \r.a.rsel1_0_RNIDBLJ2[2]\ : OR2B - port map(A => data1(30), B => d11, Y => \rfo_m[30]\); - - un6_fe_npc_I_176 : AND2 - port map(A => \fe_pc[26]\, B => \fe_pc[27]\, Y => - \DWACT_FINC_E[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I111_Y : OR2A - port map(A => I111_un1_Y_i, B => N508_1, Y => N574); - - \r.f.pc_RNO_4[29]\ : MX2 - port map(A => I_196, B => N_4072, S => bpmiss_1_i_0, Y => - \pc_4[29]\); - - \r.m.y_RNO_2[26]\ : OR2B - port map(A => \y_1[26]\, B => y08, Y => \y_m_0[26]\); - - \r.f.pc_RNIIKIGQ3[6]\ : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[6]\, C => - \xc_trap_address_m[6]\, Y => m21_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I176_Y : NOR2B - port map(A => N587_1, B => N579_1, Y => N645_0); - - \r.x.npc_0_RNITSR61[0]\ : MX2C - port map(A => N_3223, B => N_3253, S => \npc_0[0]\, Y => - \xc_result[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I184_un1_Y\ : NOR3C - port map(A => N494, B => N498_0, C => N501_0, Y => - I184_un1_Y); - - \r.e.shleft_0_RNIJ8HP\ : NOR2A - port map(A => \un1_iu0_6[10]\, B => shleft_0, Y => - shleft_0_RNIJ8HP); - - \r.m.y_RNO_1[17]\ : OR2B - port map(A => \y_1[18]\, B => mulstep_0, Y => \y_m[18]\); - - \r.d.cwp_RNIID231[2]\ : MX2 - port map(A => \cwp_0[2]\, B => \ncwp_3[2]\, S => un8_op, Y - => \ncwp[2]\); - - \r.m.ctrl.trap_RNIU6LS1\ : OR3A - port map(A => trap_0_sqmuxa_7_1, B => annul_RNIPFOQ, C => - holdn, Y => trap_0_sqmuxa_7); - - \r.e.alusel_RNIE66B[0]\ : OR3C - port map(A => \alusel[0]\, B => \alusel[1]\, C => - \aluop_0[2]\, Y => miscout_11_sqmuxa_0); - - \r.a.rsel1_RNO_0[0]\ : NOR3C - port map(A => wreg_1_5, B => wreg_1_6_0, C => wreg_2_1, Y - => \rsel1_RNO_0[0]\); - - \r.m.y_RNI84VAC[31]\ : NOR3C - port map(A => \aluop_RNIK0RF4[1]\, B => - \aluresult_1_iv_0[31]\, C => \bpdata_m_0[15]\, Y => - \aluresult_1_iv_4[31]\); - - \r.e.aluop_RNI2TDE7[1]\ : OA1A - port map(A => aluresult_6_sqmuxa, B => \bpdata[26]\, C => - \aluresult_1_iv_0[26]\, Y => \aluresult_1_iv_2[26]\); - - \r.e.op2_RNO_1[8]\ : OR2B - port map(A => \op1[8]\, B => un14_casaen_s1, Y => - \op1_m_i[8]\); - - un6_fe_npc_I_19 : NOR2B - port map(A => \fe_pc[5]\, B => \DWACT_FINC_E[0]\, Y => - N_139); - - \r.f.pc_RNO_1[18]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[18]\, C => - \pc_1_iv_0[18]\, Y => \pc_1_iv_1[18]\); - - \r.e.op1_RNITI9G[18]\ : OR2B - port map(A => \op1[18]\, B => un14_casaen_s1_0, Y => - \op1_m_0[18]\); - - \r.x.data_0_RNO_0[10]\ : NOR3A - port map(A => \data_0_1_0_iv_0[10]\, B => \rdata_13_m[8]\, - C => \rdata_17_m[8]\, Y => \data_0_1_0_iv_1[10]\); - - un6_fe_npc_I_202 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \fe_pc[29]\, Y => N_9_0); - - \r.f.pc_RNO_1[24]\ : NOR3C - port map(A => \pc_4_m[24]\, B => \xc_trap_address_m[24]\, C - => \un6_ex_add_res_m_1[25]\, Y => \pc_1_iv_1[24]\); - - \r.a.ctrl.pc[29]\ : DFN1E0 - port map(D => \dpc[29]\, CLK => lclk_c, E => holdn, Q => - \pc[29]\); - - \r.e.op2_RNO[20]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[20]\, Y => N_304); - - \r.x.npc_RNICC9R[0]\ : MX2C - port map(A => N_3238, B => N_3268, S => \npc[0]\, Y => - \xc_result[27]\); - - \r.e.shcnt_RNIVETT4[3]\ : MX2 - port map(A => \shiftin_8[24]\, B => \shiftin_8[16]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[16]\); - - \r.e.op2[18]\ : DFN1E0 - port map(D => N_302, CLK => lclk_c, E => holdn, Q => - \op2[18]\); - - \r.e.ldbp2_0_RNI3K98R1\ : OR2A - port map(A => \eaddress[16]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[17]\); - - \r.e.op1_RNI5K76B3[11]\ : NOR3C - port map(A => \op1_m_0[11]\, B => \d_iv_2[11]\, C => - \aluresult_m_0[11]\, Y => \d_i[11]\); - - \r.e.op2_RNO_3[22]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[22]\, Y => - \aluresult_m_i[22]\); - - \r.e.op2_RNI15BP[8]\ : OR2A - port map(A => \un1_iu0_5[74]\, B => \un1_iu0_6[8]\, Y => - \logicout_4[8]\); - - \r.e.op1_RNIALUH[25]\ : MX2 - port map(A => \op1[25]\, B => \data_0[25]\, S => ldbp1_3, Y - => \un1_iu0_6[25]\); - - \r.m.y_RNO[16]\ : OR3C - port map(A => \y_iv_1[16]\, B => \y_iv_0[16]\, C => - \logicout_m[16]\, Y => \y_1[16]\); - - \r.e.jmpl_RNISQNAQ_0\ : OR2B - port map(A => \shiftin_17[18]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[18]\); - - \r.a.rsel1_RNIVHHI33[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[10]\, Y => - \aluresult_m_0[10]\); - - \r.m.y_RNO_2[2]\ : OR2A - port map(A => \logicout[2]\, B => y14, Y => \logicout_m[2]\); - - \r.x.data_0_RNO[17]\ : OR3 - port map(A => \rdata_5_m_9[8]\, B => \rdata_13_m_9[8]\, C - => \data_0_1_1_iv_1[17]\, Y => \data_0_1[17]\); - - \r.d.inst_0_RNI5C23_1[31]\ : OR2A - port map(A => \inst_0[31]\, B => \inst_0[30]\, Y => - un1_inst); - - un6_ex_add_res_d0_ADD_33x33_fast_I123_Y : AO1 - port map(A => N524_0, B => N521, C => N520_0, Y => N586); - - \r.a.ctrl.wy_RNO_1\ : NOR2A - port map(A => wy_1_0_a3_1_0, B => un3_op2, Y => wy_1_0_a3_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I38_Y : OR2B - port map(A => N482_0, B => N479_2, Y => N497_2); - - \r.x.ctrl.tt_RNIF50R[5]\ : MX2C - port map(A => \result_0[5]\, B => \tt_0[5]\, S => tt_i, Y - => N_3324); - - \r.a.ctrl.inst_RNIN8T1C[22]\ : AO1B - port map(A => illegal_inst_7_iv_6_tz, B => - illegal_inst_7_iv_2_0_a5_1_0, C => N_474, Y => - illegal_inst_7_iv_5); - - \r.f.pc_RNO_7[25]\ : MX2 - port map(A => \fpc[25]\, B => \tba[13]\, S => rstate_6314_d, - Y => \xc_trap_address[25]\); - - \r.e.jmpl_RNI9N7SH1\ : AND2 - port map(A => \shiftin_17_m[21]\, B => - \aluresult_1_iv_7[20]\, Y => \aluresult_1_iv_8[20]\); - - \r.m.y_RNO_1[2]\ : AOI1B - port map(A => \y_0[2]\, B => y08_0, C => \y_m_2[3]\, Y => - \y_iv_0[2]\); - - \comb.ld_align.rdata199_RNIL4S4S\ : NOR2B - port map(A => rdata_2_sqmuxa_1, B => ld_0_0, Y => - rdata_2_sqmuxa); - - \r.f.pc_RNI2M3CJ3[2]\ : NOR3C - port map(A => \pc_4_m[2]\, B => \tmp_m[2]\, C => - \npc_iv_1[2]\, Y => \npc_iv_3[2]\); - - \r.e.ldbp2_RNI4B3TI6\ : OR3C - port map(A => \aluresult_1_iv_8[24]\, B => - \shiftin_17_m_0[24]\, C => \un6_ex_add_res_m[25]\, Y => - \aluresult[24]\); - - \r.m.result[5]\ : DFN1E0 - port map(D => \eres2[5]\, CLK => lclk_c, E => holdn, Q => - \maddress[5]\); - - \r.m.dci.size_RNO_2[0]\ : NOR2B - port map(A => \inst_1[22]\, B => \inst[19]\, Y => N_3758); - - \r.e.ctrl.pc_RNIBLK11[16]\ : OR2B - port map(A => \pc[16]\, B => jmpl_0, Y => \cpi_m[161]\); - - \r.w.s.y[30]\ : DFN1E0 - port map(D => N_3794, CLK => lclk_c, E => N_6922_i, Q => - \y_0[30]\); - - \r.m.ctrl.pc_RNIEMF8[8]\ : MX2 - port map(A => \pc_3[8]\, B => \pc[8]\, S => \npc[1]\, Y => - N_3249); - - \r.m.ctrl.inst_RNIVK0E[23]\ : NOR2A - port map(A => \inst_3[20]\, B => \inst_2[23]\, Y => - trap_0_sqmuxa_2_0); - - \r.d.inst_0_RNO_0[28]\ : MX2 - port map(A => data_0_2_28, B => \inst_0[28]\, S => - inull_RNIFV6VG2_0, Y => N_4628); - - un6_ex_add_res_d1_ADD_33x33_fast_I293_Y_0_0 : XOR2 - port map(A => \op2[2]\, B => \un1_iu0_6[2]\, Y => - ADD_33x33_fast_I293_Y_0_0); - - \r.x.ctrl.tt[5]\ : DFN1E0 - port map(D => \tt2[5]\, CLK => lclk_c, E => holdn, Q => - \tt_0[5]\); - - \r.a.ctrl.wreg_RNO_6\ : OA1 - port map(A => N_89, B => N_122_1, C => inst_0, Y => - write_reg7_0); - - \r.d.annul_RNIETIP\ : NOR3B - port map(A => un19_inst, B => not_valid, C => - icc_check_bp_1, Y => annul_RNIETIP); - - \r.x.data_0_RNO_2[4]\ : OR2A - port map(A => data_0_0_28, B => rdata_0_sqmuxa, Y => - \dco_m_i[124]\); - - \r.w.s.y_RNO[23]\ : MX2 - port map(A => \y_2[23]\, B => \result[23]\, S => N_481_0, Y - => N_3787); - - \r.f.pc_RNO_5[30]\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[30]\, Y => - \un6_ex_add_res_m_1[31]\); - - \r.x.ctrl.inst_RNIF32S_0[19]\ : NOR3A - port map(A => wim_1_sqmuxa_0, B => \inst[20]\, C => - \inst_1[19]\, Y => y_0_sqmuxa_1_1); - - \r.x.ctrl.rd_RNISU3D[1]\ : XA1A - port map(A => \rd[1]\, B => \rd_1[1]\, C => rd_2_i_0, Y => - bpdata6_2); - - \r.a.rsel2[1]\ : DFN1E0 - port map(D => N_3946, CLK => lclk_c, E => holdn, Q => - \rsel2[1]\); - - un6_fe_npc_I_16 : AND3 - port map(A => \fe_pc[2]\, B => \fe_pc[3]\, C => \fe_pc[4]\, - Y => \DWACT_FINC_E[0]\); - - \r.x.ctrl.pc_RNI9IGF[21]\ : MX2 - port map(A => \pc_2[21]\, B => \pc_0[21]\, S => \npc_1[1]\, - Y => N_3232); - - \r.e.jmpl_RNIH1GEJ_0\ : OR2B - port map(A => \shiftin_17[1]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[1]\); - - \r.m.ctrl.rd[4]\ : DFN1E0 - port map(D => \rd_0[4]\, CLK => lclk_c, E => holdn, Q => - \rd[4]\); - - \r.e.op1[19]\ : DFN1E0 - port map(D => \aop1[19]\, CLK => lclk_c, E => holdn, Q => - \op1[19]\); - - \r.e.invop2_RNI4EL7S2\ : MX2 - port map(A => \un6_ex_add_res_s2[29]\, B => - \un6_ex_add_res_s0[29]\, S => invop2, Y => N_6625); - - \r.a.ctrl.inst_RNIU43A1[21]\ : OR3A - port map(A => \inst_2[21]\, B => N_207, C => N_515, Y => - inst_14); - - \r.m.ctrl.pc_RNIRPGF[22]\ : MX2 - port map(A => \pc_3[22]\, B => \pc[22]\, S => \npc_0[1]\, Y - => N_3263); - - \r.e.op2_RNIVMIF[20]\ : MX2 - port map(A => \op2[20]\, B => N_4267, S => ldbp2_3, Y => - \un1_iu0_5[86]\); - - \r.e.ctrl.inst_RNI963Q7[29]\ : OR2A - port map(A => \inst_2[29]\, B => ex_bpmiss_1, Y => - ra_bpannul_1); - - \r.e.jmpl_RNI4HD5L_0\ : OR2B - port map(A => \shiftin_17[4]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[4]\); - - \r.x.result[2]\ : DFN1E0 - port map(D => \maddress[2]\, CLK => lclk_c, E => holdn, Q - => \result_0[2]\); - - un54_ra_I_13 : XOR2 - port map(A => \ncwp[1]\, B => \DWACT_ADD_CI_0_TMP[0]\, Y - => I_13_0); - - \r.w.s.y[28]\ : DFN1E0 - port map(D => N_3792, CLK => lclk_c, E => N_6922_i, Q => - \y_0[28]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I172_un1_Y\ : NOR2A - port map(A => N546_1, B => N539, Y => I172_un1_Y); - - \r.e.op1_RNIUM9G[19]\ : OR2B - port map(A => \op1[19]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[19]\); - - \r.a.rfa2_RNI7N361[0]\ : MX2 - port map(A => \inst_0_RNI0FUM[0]\, B => \rfa2[0]\, S => - holdn, Y => raddr2(0)); - - un6_ex_add_res_d1_ADD_33x33_fast_I114_Y : NOR3B - port map(A => N458, B => N461_0, C => N_30, Y => N577_0); - - \r.e.op2_RNO_8[14]\ : OR3B - port map(A => d29_0_0, B => \imm[14]\, C => \rsel2_1[0]\, Y - => \imm_m_i[14]\); - - \r.x.data_0[11]\ : DFN1E0 - port map(D => \data_0_1[11]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_2[11]\); - - \r.f.pc_RNO_5[24]\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[24]\, Y => - \un6_ex_add_res_m_1[25]\); - - \r.d.inull_RNIH24EP\ : NOR2A - port map(A => annul_current_4, B => \un1_p0_6[0]\, Y => - annul_current_0); - - un54_ra_I_9 : XOR2 - port map(A => \ncwp[0]\, B => N_79, Y => - \DWACT_ADD_CI_0_partial_sum_2[0]\); - - \r.e.shleft_0_RNIL4LK1\ : MX2C - port map(A => \shiftin_5[16]\, B => \shiftin_5[0]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I240_Y\ : OR3C - port map(A => I206_un1_Y, B => N582_0, C => I240_un1_Y, Y - => N710); - - \r.e.shcnt_RNIJATPO[1]\ : MX2C - port map(A => \shiftin_14[18]\, B => \shiftin_14[16]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[16]\); - - \r.e.shcnt_RNI8RII6[3]\ : MX2 - port map(A => \shiftin_8[35]\, B => \shiftin_8[27]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[27]\); - - \r.m.y[17]\ : DFN1E0 - port map(D => \y_1[17]\, CLK => lclk_c, E => holdn, Q => - \y[17]\); - - \r.e.op2_RNO_1[27]\ : OR2B - port map(A => \op1[27]\, B => un14_casaen_s1, Y => - \op1_m_i[27]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I215_un1_Y : OR2B - port map(A => N644_0, B => N629_1, Y => I215_un1_Y_0); - - \r.e.ldbp2_RNI7DGUV\ : MX2 - port map(A => \un6_ex_add_res_s1_i[12]\, B => N_6631, S => - ldbp2_3, Y => \eaddress[11]\); - - \r.x.result_RNILHB25[0]\ : NOR2 - port map(A => \bpdata[0]\, B => N_3703_i, Y => - \bpdata_i_m_1[0]\); - - \r.e.op1_RNIIGKS4[18]\ : AO1A - port map(A => \bpdata[18]\, B => edata_2_sqmuxa, C => - \op1_i_m[18]\, Y => \edata2_0_iv_0[18]\); - - \r.a.ctrl.inst_RNICC1E_0[19]\ : OR2A - port map(A => \inst_2[20]\, B => \inst_2[19]\, Y => N_472); - - un6_ex_add_res_d1_ADD_33x33_fast_I260_Y_0 : MIN3 - port map(A => \op2[29]\, B => \un1_iu0_6[29]\, C => N481_0, - Y => ADD_33x33_fast_I260_Y_0_0); - - \r.d.inst_0_RNI66J4_1[23]\ : NOR3A - port map(A => \inst_0_0[23]\, B => \inst_0_0[24]\, C => - \inst_0_0[22]\, Y => un19_inst); - - un23_ra_I_1 : AND2 - port map(A => \cwp_0[0]\, B => \inst_0[18]\, Y => - \DWACT_ADD_CI_0_TMP_1[0]\); - - \r.m.y_RNO_0[11]\ : AOI1B - port map(A => wy_1_0, B => \y[11]\, C => \y_m[11]\, Y => - \y_iv_1[11]\); - - \r.e.op2_RNIAK9P[2]\ : OR2A - port map(A => \un1_iu0_5[68]\, B => \un1_iu0_6[2]\, Y => - \logicout_4[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I320_Y_0_1 : XOR2 - port map(A => \data_0_0[29]\, B => \un1_iu0_6[29]\, Y => - \un6_ex_add_res_s2_1[30]\); - - \r.e.aluop_2_RNIRI6R2[1]\ : MX2C - port map(A => N_3553, B => \logicout_3[26]\, S => - \aluop_2[1]\, Y => N_3585); - - un6_ex_add_res_d0_ADD_33x33_fast_I5_P0N : OR3A - port map(A => \data_0[4]\, B => \op1[4]\, C => ldbp1_0, Y - => N410_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I25_G0N : NOR2A - port map(A => \un1_iu0_6[24]\, B => \data_0[24]\, Y => - N469_1); - - \r.x.result_RNIUVKA[7]\ : MX2 - port map(A => \result_0[7]\, B => \data_0_2[7]\, S => ld_0, - Y => \un1_p0_6[359]\); - - \r.x.ctrl.rd_RNIA2NU[4]\ : MX2 - port map(A => \cwp[0]\, B => \rd_2[4]\, S => N_6357, Y => - waddr(4)); - - un6_ex_add_res_d1_ADD_33x33_fast_I322_Y_0 : AX1E - port map(A => I259_un1_Y, B => ADD_33x33_fast_I259_Y_3_1, C - => ADD_33x33_fast_I322_Y_0_0, Y => - \un6_ex_add_res_s1[32]\); - - \r.x.data_0_RNIBJ9E[21]\ : XNOR2 - port map(A => \data_0[21]\, B => invop2_1, Y => N_4268_i); - - \r.f.pc_RNO_0[19]\ : NAND2 - port map(A => \tmp[19]\, B => un2_rstn_5_0, Y => - \tmp_m[19]\); - - \r.e.op2[25]\ : DFN1E0 - port map(D => N_309, CLK => lclk_c, E => holdn, Q => - \op2[25]\); - - \r.a.ctrl.pc_RNIM3E2C[12]\ : MX2 - port map(A => \pc[12]\, B => N_3889, S => ex_bpmiss_1_0, Y - => \fe_pc[12]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I320_Y_0 : XOR2 - port map(A => N768, B => \un6_ex_add_res_s2_1[30]\, Y => - \un6_ex_add_res_s2[30]\); - - \r.a.ctrl.pc[5]\ : DFN1E0 - port map(D => \dpc[5]\, CLK => lclk_c, E => holdn, Q => - \pc_0[5]\); - - \r.w.s.icc_RNO_0[1]\ : AOI1B - port map(A => icc_2_sqmuxa, B => \result_0[21]\, C => - \icc_m_0[1]\, Y => \icc_1_iv_0[1]\); - - \r.e.op1_RNIALL2O3[13]\ : NOR3C - port map(A => \op1_m_0[13]\, B => \d_iv_2[13]\, C => - \aluresult_m_0[13]\, Y => \d_i[13]\); - - \r.e.op2_RNI4GMB1[31]\ : OR2A - port map(A => \un1_iu0_5[97]\, B => \un1_iu0_6[31]\, Y => - \logicout_4[31]\); - - \r.x.data_0_RNO_1[5]\ : NAND2 - port map(A => data_0_0_21, B => N_3455, Y => \dco_m_i[117]\); - - \r.e.op1_RNIMAEPF5[19]\ : NOR3C - port map(A => \op1_m_0[19]\, B => \d_iv_2[19]\, C => - \aluresult_m_0[19]\, Y => \d_i[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I183_Y : OR2A - port map(A => I183_un1_Y_i_0, B => N586_1, Y => N652_0); - - \r.a.rfa2_RNIDF461[3]\ : MX2 - port map(A => \inst_0_RNI3RUM[3]\, B => \rfa2[3]\, S => - holdn, Y => raddr2(3)); - - \un1_r.w.s.cwp_1_SUM2_0\ : AX1E - port map(A => ANC1, B => CO1_0, C => SUM2_0_0, Y => N_6529); - - \r.x.ctrl.inst_RNIQD1E[19]\ : NOR2A - port map(A => \inst_1[19]\, B => \inst[20]\, Y => y6_0_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I299_Y_0 : XNOR2 - port map(A => N817_i, B => ADD_33x33_fast_I299_Y_0_0, Y => - \un6_ex_add_res_s1[9]\); - - \r.e.op2_RNIIONB1_0[18]\ : OR2 - port map(A => \un1_iu0_6[18]\, B => \un1_iu0_5[84]\, Y => - \logicout_3[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I81_Y\ : OA1 - port map(A => \dpc[5]\, B => \inst_0_RNI3RUM[3]\, C => N365, - Y => N498_0); - - \r.a.rsel1_0_RNII7LJ2[2]\ : OR2B - port map(A => data1(28), B => d11_0, Y => \rfo_m[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I145_Y_0 : MAJ3 - port map(A => \op2[5]\, B => \un1_iu0_6[5]\, C => N409, Y - => ADD_33x33_fast_I145_Y_0); - - \r.e.ldbp2_2_RNIOL2G65\ : OR2A - port map(A => \eaddress[31]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[32]\); - - \r.m.y_RNO[5]\ : AO1C - port map(A => y14_0, B => \logicout[5]\, C => \y_iv_2[5]\, - Y => \y_0[5]\); - - \r.e.jmpl_RNIUUEBP_0\ : OR2B - port map(A => \shiftin_17[15]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[15]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I130_un1_Y\ : NOR2B - port map(A => N495_1, B => N492, Y => I130_un1_Y); - - \r.x.data_0_RNO_1[28]\ : NOR2A - port map(A => \data_0[28]\, B => ld_3, Y => \data_0_m[28]\); - - \r.e.op2_RNO_2[20]\ : AOI1B - port map(A => data2(20), B => d25_0, C => \d_1_iv_2[20]\, Y - => \d_1_iv_3[20]\); - - \r.a.imm[3]\ : DFN1E0 - port map(D => \un3_de_ren1[121]\, CLK => lclk_c, E => holdn, - Q => \imm[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I43_Y\ : NOR2B - port map(A => N425, B => N422, Y => N460_0); - - \r.x.ctrl.inst_RNIHVSN2[30]\ : OR2 - port map(A => cwp_1_sqmuxa_0, B => holdn, Y => N_6699); - - \r.d.cwp_RNO_0[2]\ : MX2 - port map(A => \ncwp[2]\, B => N_4220, S => un1_wcwp, Y => - N_4229); - - un6_ex_add_res_d1_ADD_33x33_fast_I183_un1_Y : OR3C - port map(A => N521_1, B => N525, C => N594_1, Y => - I183_un1_Y_i_0); - - \r.e.ctrl.inst_RNIVC1S[20]\ : NOR2 - port map(A => aluresult_13_sqmuxa_3, B => - aluresult_11_sqmuxa_4, Y => aluresult_11_sqmuxa_6); - - un6_ex_add_res_d2_ADD_33x33_fast_I269_Y : NAND2 - port map(A => I269_un1_Y, B => ADD_33x33_fast_I269_Y_0_0, Y - => N784_0); - - \r.m.ctrl.pc_RNI4MF8[3]\ : MX2 - port map(A => \pc_3[3]\, B => \pc[3]\, S => \npc[1]\, Y => - N_3244); - - \r.f.branch_RNIMJA92\ : XOR2 - port map(A => branch_0, B => \fbranch\, Y => - branch_RNIMJA92); - - \r.e.op1_RNIFHQEF[27]\ : NOR2B - port map(A => \edata2_iv_2[27]\, B => \edata2_iv_1[27]\, Y - => edata2_iv_i_0(27)); - - \r.e.aluop_RNI2TEB4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[28]\, Y => - \aluop_RNI2TEB4[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_a3 : NOR2B - port map(A => N614_1, B => N407_2, Y => - ADD_33x33_fast_I206_Y_0_a3); - - \r.e.shleft_1_RNI5FBG\ : NOR2A - port map(A => \un1_iu0_6[4]\, B => shleft_1, Y => - shleft_1_RNI5FBG); - - \r.e.op1_RNIMM8G[11]\ : OR2B - port map(A => \op1[11]\, B => un14_casaen_s1_0, Y => - \op1_m_0[11]\); - - \r.e.aluop_RNIMPHR1[2]\ : OR2 - port map(A => aluresult_6_sqmuxa, B => aluresult_5_sqmuxa, - Y => N_3974); - - \r.m.y_RNO[1]\ : OR3C - port map(A => \y_iv_0_1[1]\, B => \y_iv_0_0[1]\, C => N_377, - Y => \y_1[1]\); - - \r.d.inst_0_RNI2SEN2[13]\ : NOR2A - port map(A => ldcheck2, B => imm, Y => rfe_0); - - \r.a.ctrl.inst_RNISU854[20]\ : AOI1B - port map(A => illegal_inst_1_sqmuxa_i_2, B => N_434, C => - \cpi_m_i[133]\, Y => illegal_inst_7_iv_0); - - \r.e.ldbp2_RNIC2ODE2\ : OR2A - port map(A => annul_RNI5L7FE1, B => \eaddress[11]\, Y => - N_9); - - \r.x.data_0_RNO[14]\ : OR3 - port map(A => \dco_m_0[110]\, B => \data_0_1_0_iv_0[14]\, C - => \data_0_1_4[9]\, Y => \data_0_1[14]\); - - \r.e.op2_RNO_1[12]\ : OR2B - port map(A => \op1[12]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[12]\); - - \r.e.aluop_0_RNIULOS3[0]\ : OR2B - port map(A => \logicout[8]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[8]\); - - \r.w.s.y_RNO[2]\ : MX2 - port map(A => \y_2[2]\, B => \result_0[2]\, S => N_481_0, Y - => N_3766); - - \r.e.op1_RNO[3]\ : MX2 - port map(A => \d[3]\, B => \d[4]\, S => N_227_0, Y => - \aop1[3]\); - - \r.d.inst_0_RNI62J4[21]\ : OR3C - port map(A => \inst_0[19]\, B => \inst_0_0[21]\, C => - \inst_0_0[22]\, Y => un12_op3); - - \r.e.op2_RNIF4U51_0[23]\ : NOR2 - port map(A => \un1_iu0_6[23]\, B => \un1_iu0_5[89]\, Y => - \logicout_3[23]\); - - \r.e.op2_RNO[10]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[10]\, Y => N_294); - - un6_ex_add_res_d0_ADD_33x33_fast_I63_Y_0 : AO1 - port map(A => N443_0, B => N439_0, C => N442, Y => N522_0); - - \r.d.inst_0_RNI42J4[21]\ : OR2A - port map(A => N_67, B => \inst_0_0[21]\, Y => un4_op3); - - un6_ex_add_res_d2_ADD_33x33_fast_I30_G0N : NOR2B - port map(A => \data_0_0[29]\, B => \un1_iu0_6[29]\, Y => - N484); - - \r.e.op1[8]\ : DFN1E0 - port map(D => \aop1[8]\, CLK => lclk_c, E => holdn, Q => - \op1[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I121_Y_0 : MIN3 - port map(A => \op2[17]\, B => \un1_iu0_6[17]\, C => N445_1, - Y => ADD_33x33_fast_I121_Y_0_1); - - \r.x.data_0_RNO_1[15]\ : OR2 - port map(A => \dco_m_0[127]\, B => \data_0_m[15]\, Y => - \data_0_1_0_iv_0[15]\); - - \r.e.op1_RNI2TNO6[24]\ : NOR3C - port map(A => \ex_op1_i_m[24]\, B => \op1_RNI1JNF[24]\, C - => \bpdata_i_m[24]\, Y => \edata2_iv_1[24]\); - - \r.w.result_RNIO6PF[13]\ : AOI1B - port map(A => \un1_p0_6[365]\, B => d14, C => - \result_m_0_0[13]\, Y => \d_iv_0[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I189_Y : AO1 - port map(A => N600_1, B => N593_0, C => N592_0, Y => N658_0); - - \r.x.data_0_RNO[18]\ : OR3 - port map(A => \dco_m_0[114]\, B => \data_0_m[18]\, C => - \data_0_1_4[18]\, Y => \data_0_1[18]\); - - \r.d.inst_0_RNIFK901[17]\ : MX2C - port map(A => \de_raddr1_2[5]\, B => \de_raddr1_1[5]\, S - => rs1mod, Y => \un3_de_ren1[96]\); - - \r.m.result_RNO[8]\ : MX2 - port map(A => \aluresult[8]\, B => \op1[8]\, S => - un17_casaen_0_1, Y => \eres2[8]\); - - \r.d.inst_0[10]\ : DFN1 - port map(D => \inst_0_RNO[10]\, CLK => lclk_c, Q => - \inst_0[10]\); - - \comb.lock_gen.icc_check5_0_a3\ : NAND2 - port map(A => N_145, B => ticc_exception_1, Y => icc_check5); - - un6_ex_add_res_d0_ADD_33x33_fast_I23_P0N : OR3A - port map(A => \data_0_0[22]\, B => \op1[22]\, C => ldbp1_4, - Y => N464_2); - - \r.m.icc_RNO_7[2]\ : NOR3C - port map(A => icc_0_sqmuxa_1_18, B => icc_0_sqmuxa_1_17, C - => icc_0_sqmuxa_1_26, Y => icc_0_sqmuxa_1_29); - - \r.e.shleft_RNIFMRJ\ : OR2A - port map(A => \un1_iu0_6[25]\, B => shleft, Y => - \shiftin_5[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I92_un1_Y\ : OAI1 - port map(A => N427, B => ADD_30x30_fast_I40_Y_0_a3, C => - N454, Y => I92_un1_Y); - - \r.a.nobp_RNO_1\ : AO1C - port map(A => \inst_0[31]\, B => un19_inst, C => N_85, Y - => N_16827_tz); - - un6_ex_add_res_d1_ADD_33x33_fast_I261_Y : NAND2 - port map(A => I261_un1_Y_0, B => ADD_33x33_fast_I261_Y_2_0, - Y => N768_1); - - \r.x.result_RNIRV6B[9]\ : OR2B - port map(A => \un1_p0_6[361]\, B => d14, Y => - \cpi_m_0[361]\); - - \r.e.aluop_0_RNIBL5R[1]\ : XOR3 - port map(A => \un1_iu0_6[3]\, B => \aluop_0[1]\, C => - \un1_iu0_5[69]\, Y => N_6829); - - \r.a.rsel1_0_RNIB7LJ2[2]\ : OR2B - port map(A => data1(21), B => d11_0, Y => \rfo_m[21]\); - - \r.a.ctrl.wicc\ : DFN1E0 - port map(D => wicc_1, CLK => lclk_c, E => holdn, Q => - wicc_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_un1_Y_0 : NOR2B - port map(A => N637_0, B => N653_1, Y => - ADD_33x33_fast_I265_un1_Y_0_0); - - \r.m.y_RNICRD92[18]\ : NOR2B - port map(A => \y_m_1[18]\, B => \cpi_m[163]\, Y => - \aluresult_1_iv_1[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I263_un1_Y : NOR3C - port map(A => N649, B => N633_0, C => N808, Y => - I263_un1_Y_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I159_un1_Y : OR3A - port map(A => N570_0, B => N497_2, C => N501, Y => - I159_un1_Y); - - \r.f.pc_RNO_5[18]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[18]\, Y => \xc_trap_address_m[18]\); - - \r.a.rfa1_RNINNUA1[0]\ : MX2 - port map(A => \rs1_iv_i_0[0]\, B => \rfa1[0]\, S => holdn, - Y => raddr1(0)); - - \r.x.ctrl.pc_RNIBIGF[31]\ : MX2 - port map(A => \pc_2[31]\, B => \pc[31]\, S => \npc_1[1]\, Y - => N_3242); - - \r.e.aluop_RNIUF511[2]\ : XA1 - port map(A => \un1_iu0_5[68]\, B => \aluop_1[2]\, C => - \un1_iu0_6[2]\, Y => N_3529); - - \r.a.ctrl.rd_RNIGC1L[3]\ : XNOR2 - port map(A => \rd_1[3]\, B => \un3_de_ren1[94]\, Y => - un2_rs1_3_i); - - \r.m.y_RNO_1[30]\ : OR2B - port map(A => \y[31]\, B => mulstep_0, Y => \y_m_1[31]\); - - \r.e.op1_RNIR8E64[4]\ : AOI1B - port map(A => \op1[4]\, B => un14_casaen_s1_0_1, C => - \d_1_iv_3[4]\, Y => \d_1_iv_4[4]\); - - \r.d.pc_RNIUTGB4[17]\ : MX2 - port map(A => \dpc[17]\, B => \fpc[17]\, S => - \ra_bpmiss_1_0\, Y => N_3894); - - un6_ex_add_res_d2_ADD_33x33_fast_I5_G0N : OA1 - port map(A => \op1[4]\, B => ldbp1_1, C => \data_0[4]\, Y - => N409_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I315_Y_0 : XNOR2 - port map(A => N778_0, B => \un6_ex_add_res_s2_1[25]\, Y => - \un6_ex_add_res_s0[25]\); - - \r.x.result_RNII62O3[31]\ : MX2C - port map(A => \un1_iu0_6[31]\, B => \un1_p0_6[383]\, S => - bpdata6_0_0, Y => \bpdata[31]\); - - \r.f.pc_RNI04KTU4[9]\ : NOR2B - port map(A => \un6_fe_npc_m[7]\, B => - \xc_trap_address_m[9]\, Y => \npc_iv_2[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I299_Y_0 : XOR2 - port map(A => N817_0, B => \un6_ex_add_res_s2_1[9]\, Y => - \un6_ex_add_res_s2[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I200_Y : NOR3C - port map(A => N545_1, B => N549_0, C => N603, Y => N669); - - \r.x.result_RNI3L6E[28]\ : MX2 - port map(A => \result_0[28]\, B => \data_0[28]\, S => ld_4, - Y => \un1_p0_6[380]\); - - \r.x.ctrl.pc[24]\ : DFN1E0 - port map(D => \pc_2[24]\, CLK => lclk_c, E => holdn, Q => - \pc_0[24]\); - - \r.e.op1_RNO[13]\ : MX2C - port map(A => \d_i[13]\, B => \d_i[14]\, S => N_227, Y => - \aop1[13]\); - - \r.x.laddr_RNIF5HB51[1]\ : OR3B - port map(A => rdata200, B => ld_0_0, C => \me_laddr_2[1]\, - Y => rdata_5_sqmuxa); - - un6_ex_add_res_d2_ADD_33x33_fast_I317_Y_0_1 : XOR2 - port map(A => \data_0[26]\, B => \un1_iu0_6[26]\, Y => - \un6_ex_add_res_s2_1[27]\); - - \r.e.shleft_RNI9KCC2\ : MX2B - port map(A => \shiftin_5[43]\, B => \shiftin_5[27]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[27]\); - - \r.x.rstate_RNI64FC2[0]\ : MX2C - port map(A => N_3410, B => \xc_result[19]\, S => - \rstate[0]\, Y => \wdata[19]\); - - \r.d.pc_RNO[4]\ : MX2 - port map(A => \fpc[4]\, B => \dpc[4]\, S => N_6763_i, Y => - \pc_RNO[4]\); - - \r.x.npc_RNIAT411[0]\ : MX2C - port map(A => N_3240, B => N_3270, S => \npc[0]\, Y => - \xc_result[29]\); - - \r.e.op1_RNI9HUH[24]\ : MX2 - port map(A => \op1[24]\, B => \data_0[24]\, S => ldbp1_4, Y - => \un1_iu0_6[24]\); - - \r.e.ctrl.tt_RNO_0[1]\ : OA1B - port map(A => ticc, B => wunf, C => wovf, Y => N_16735_tz); - - \r.e.op2_RNI9S3F[0]\ : OR2A - port map(A => \op2_RNI59C6[0]\, B => \un1_iu0_6[0]\, Y => - \logicout_4[0]\); - - \r.e.op2_RNO_0[31]\ : OR3C - port map(A => \op1_m_i[31]\, B => \d_1_iv_3[31]\, C => - \aluresult_m_i[31]\, Y => \d_1[31]\); - - \r.x.data_0_RNO[3]\ : AO1B - port map(A => N_3456, B => N_3387_i_0, C => - \data_0_1_1_iv_2[3]\, Y => \data_0_1[3]\); - - \r.e.op2_RNIF4U51[23]\ : NOR2A - port map(A => \un1_iu0_5[89]\, B => \un1_iu0_6[23]\, Y => - \logicout_4[23]\); - - \r.e.ctrl.pc_RNIF1L11[29]\ : OR2B - port map(A => \pc_0[29]\, B => jmpl_0, Y => \cpi_m[174]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I39_Y_0_a3 : NOR3C - port map(A => \op2[26]\, B => \un1_iu0_6[26]\, C => N479_2, - Y => ADD_33x33_fast_I39_Y_0_a3); - - un6_ex_add_res_d0_ADD_33x33_fast_I265_Y : NAND2 - port map(A => I265_un1_Y_i_1, B => - ADD_33x33_fast_I265_Y_1_1, Y => N776_0); - - un6_fe_npc_I_5 : XOR2 - port map(A => \fe_pc[2]\, B => \fe_pc[3]\, Y => I_5); - - un6_ex_add_res_d0_ADD_33x33_fast_I145_Y_0 : AO13 - port map(A => N409_0, B => \un1_iu0_6[5]\, C => \data_0[5]\, - Y => ADD_33x33_fast_I145_Y_0_0); - - \r.e.ldbp2_RNIEEFAF1\ : OR2 - port map(A => un12_ex_add_res, B => \eaddress[13]\, Y => - un1_addout_12_0); - - \r.e.invop2_RNIR5ON11\ : MX2C - port map(A => \un6_ex_add_res_s2[16]\, B => - \un6_ex_add_res_s0[16]\, S => invop2, Y => N_6635); - - un6_ex_add_res_d0_ADD_33x33_fast_I262_Y_0_a3 : OAI1 - port map(A => N506_0, B => N_74, C => - ADD_33x33_fast_I262_Y_0_a3_0, Y => N_51_i_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I112_Y : NOR2B - port map(A => N513_2, B => N509_0, Y => N575_2); - - \r.e.ctrl.pc[2]\ : DFN1E0 - port map(D => \pc[2]\, CLK => lclk_c, E => holdn, Q => - \pc_2[2]\); - - \r.e.ctrl.pc[24]\ : DFN1E0 - port map(D => \pc_3[24]\, CLK => lclk_c, E => holdn, Q => - \pc[24]\); - - \r.a.ctrl.rd_RNI97P71[6]\ : XNOR2 - port map(A => \rd[6]\, B => \un3_de_ren1[97]\, Y => - un2_rs1_6_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I321_Y_0_0 : XOR2 - port map(A => \op2[30]\, B => \un1_iu0_6[30]\, Y => - ADD_33x33_fast_I321_Y_0_0); - - \r.m.ctrl.annul_RNIPFOQ\ : AO1B - port map(A => annul_1tt_N_7, B => annul_1tt_N_5, C => rst, - Y => annul_RNIPFOQ); - - \r.e.op2_RNO_5[17]\ : AOI1B - port map(A => \result[17]\, B => d31_0, C => \imm_m_i[17]\, - Y => \d_1_iv_0[17]\); - - \r.e.jmpl_RNIR18H6\ : OR2 - port map(A => aluresult_0_sqmuxa, B => \eaddress[2]\, Y => - jmpl_RNIR18H6); - - \r.e.aluop_1_RNIKB2T2[1]\ : MX2C - port map(A => \logicout_4[26]\, B => N_6859, S => - N_6866_i_0, Y => N_3649); - - \r.m.result_0_RNIQ9USD[3]\ : AO1D - port map(A => trap_1_sqmuxa, B => trap_0_sqmuxa_6, C => - annul_3, Y => un1_trap_0_sqmuxa_5); - - \r.w.s.icc_RNO_0[2]\ : AOI1B - port map(A => icc_2_sqmuxa, B => \result_0[22]\, C => - \icc_m_0[2]\, Y => \icc_1_iv_0[2]\); - - \r.x.dci.size_RNIQ1HOI[0]\ : NOR2 - port map(A => \me_size_1[1]\, B => \me_size_1[0]\, Y => - rdata200); - - \r.x.dci.size[1]\ : DFN1E0 - port map(D => \size_0[1]\, CLK => lclk_c, E => holdn, Q => - \size_2[1]\); - - \r.m.y_RNO_1[11]\ : AOI1B - port map(A => \y_0[11]\, B => y08_0, C => \y_m[12]\, Y => - \y_iv_0[11]\); - - \r.e.op2_RNII0OB1_0[19]\ : OR2 - port map(A => \op1_RNID1VH[19]\, B => \un1_iu0_5[85]\, Y - => \logicout_3[19]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I292_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[2]\, B => N552, Y => - \un6_ex_add_res_s0[2]\); - - \r.e.op2_RNO_8[11]\ : OR3B - port map(A => d29_0_0, B => \imm[11]\, C => \rsel2_1[0]\, Y - => \imm_m_i[11]\); - - \r.f.pc_RNO_2[14]\ : NAND2 - port map(A => \tmp[14]\, B => un2_rstn_5_0, Y => N_6619); - - \r.e.op1_RNO[21]\ : MX2C - port map(A => \d_i[21]\, B => \d_i[22]\, S => N_227_0, Y - => \aop1[21]\); - - \r.x.data_0[18]\ : DFN1E0 - port map(D => \data_0_1[18]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_0[18]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I138_Y_0 : OA1A - port map(A => \data_0[6]\, B => \un1_iu0_6[6]\, C => N419, - Y => ADD_33x33_fast_I138_Y_0); - - \r.w.s.icc_RNO_1[0]\ : OR2B - port map(A => icc_0_sqmuxa, B => \icc_2[0]\, Y => - \icc_m_0[0]\); - - \r.e.cwp[1]\ : DFN1E0 - port map(D => \cwp_3[1]\, CLK => lclk_c, E => holdn, Q => - \cwp_2[1]\); - - \r.e.aluop_0_RNIHK9O1[1]\ : MX2C - port map(A => \logicout_4[8]\, B => N_6868, S => N_6866_i_0, - Y => N_3631); - - \r.d.inst_0_RNO_0[5]\ : MX2 - port map(A => data_0_0_5, B => \inst_0[5]\, S => - mexc_1_sqmuxa_1_0, Y => N_4605); - - \r.d.inst_0_RNIBO79[24]\ : MX2C - port map(A => \un1_p0_6_0[60]\, B => \inst_0_0[24]\, S => - \inst_0[30]\, Y => \inst_0_1[26]\); - - \r.f.pc_RNO_1[22]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[22]\, C => - \pc_1_iv_0[22]\, Y => \pc_1_iv_1[22]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I276_Y_0_0\ : XOR2 - port map(A => \dpc[18]\, B => \inst_0[16]\, Y => - ADD_30x30_fast_I276_Y_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I7_G0N : OA1 - port map(A => \op1[6]\, B => ldbp1_1, C => \data_0[6]\, Y - => N415_2); - - \r.e.shcnt_RNIV5R9D[2]\ : MX2C - port map(A => \shiftin_11[29]\, B => \shiftin_11[25]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[25]\); - - \r.e.shcnt_RNIP4QF5[3]\ : MX2 - port map(A => \shiftin_8[23]\, B => \shiftin_8[15]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[15]\); - - \r.d.pc[27]\ : DFN1 - port map(D => \pc_RNO[27]\, CLK => lclk_c, Q => \dpc[27]\); - - \r.x.ctrl.rd_RNIGU7Q[3]\ : NOR3C - port map(A => rd_4_i_0, B => rd_3_i_0, C => bpdata6_4, Y - => bpdata6_7); - - \r.e.ldbp2_1_RNIB95RE4\ : MX2C - port map(A => \un6_ex_add_res_s1_i[27]\, B => N_6658, S => - ldbp2_1, Y => \eaddress[26]\); - - \r.d.inst_0_RNIF6J4[25]\ : NOR2 - port map(A => \inst_0[25]\, B => N_122_2, Y => tmp); - - \r.x.result_RNIL62O3[24]\ : MX2C - port map(A => \un1_iu0_6[24]\, B => \un1_p0_6[376]\, S => - bpdata6_0_0, Y => \bpdata[24]\); - - \r.e.ctrl.inst[22]\ : DFN1E0 - port map(D => \inst[22]\, CLK => lclk_c, E => holdn, Q => - \inst_1[22]\); - - \r.w.s.tba_RNIUK1K4[11]\ : AOI1B - port map(A => \tba[11]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_2[23]\, Y => \aluresult_1_iv_4[23]\); - - \r.a.ctrl.inst_RNIFRN9A[20]\ : OR3B - port map(A => aluop_2_1_0_1, B => aluop_2_1_0_2, C => N_230, - Y => \aluop[2]\); - - \r.w.s.y[15]\ : DFN1E0 - port map(D => N_3779, CLK => lclk_c, E => N_6922_i_0, Q => - \y_2[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I182_Y : NOR2B - port map(A => N593_0, B => N585_0, Y => N651_1); - - \r.e.ctrl.pc_RNI6TJ11[20]\ : OR2B - port map(A => \pc_0[20]\, B => jmpl_0, Y => \cpi_m[165]\); - - \r.a.ctrl.pc_RNI65FI82[2]\ : OR2A - port map(A => un2_rstn_4_0_0, B => \fe_pc[2]\, Y => - \un6_fe_npc_m[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I1_G0N\ : NOR2B - port map(A => \inst_0_RNI1JUM[1]\, B => \dpc[3]\, Y => N361); - - \r.a.imm[17]\ : DFN1E0 - port map(D => \un3_de_ren1[135]\, CLK => lclk_c, E => holdn, - Q => \imm[17]\); - - \r.x.result_RNINBRV[1]\ : NOR2B - port map(A => \un1_p0_6[353]\, B => N_6357, Y => \wdata[1]\); - - \r.d.inst_0_RNI6AJ4[25]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[25]\, S => - \inst_0[30]\, Y => \inst_0_1[27]\); - - \r.w.s.dwt_RNO_0\ : MX2C - port map(A => dwt, B => \result_0[14]\, S => dwt_1_sqmuxa, - Y => N_318); - - \r.m.casa_RNI8BU9\ : NOR2A - port map(A => casa, B => N_3355_1, Y => \un17_casaen_0_0\); - - \r.d.inst_0_RNO_0[27]\ : MX2 - port map(A => data_0_2_27, B => \inst_0[27]\, S => - inull_RNIFV6VG2_0, Y => N_4627); - - \r.e.op2_RNO_6[12]\ : OR3B - port map(A => d29_0_0, B => \imm[12]\, C => \rsel2_1[0]\, Y - => \imm_m_i[12]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I115_Y : AO1A - port map(A => N516_1, B => N513_2, C => N512_1, Y => N578_0); - - \r.x.result_RNIJ5SBB[1]\ : MX2C - port map(A => \result_0[1]\, B => N_6528, S => - cwp_1_sqmuxa_0, Y => N_3871); - - \r.f.pc_RNIAIBJB2[3]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[3]\, Y => - \pc_4_m[3]\); - - \r.x.rstate_RNIDJJ62[0]\ : MX2C - port map(A => N_3418, B => \xc_result[27]\, S => - \rstate[0]\, Y => \wdata[27]\); - - \r.e.aluop_RNIQDMD8[2]\ : NOR2A - port map(A => \aluop_RNI6QSC4[2]\, B => \bpdata_i_m_2[0]\, - Y => \edata2_iv_2[24]\); - - \r.x.data_0[5]\ : DFN1E0 - port map(D => \data_0_1[5]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[5]\); - - \r.x.ctrl.pc[23]\ : DFN1E0 - port map(D => \pc_2[23]\, CLK => lclk_c, E => holdn, Q => - \pc[23]\); - - \r.e.op1_RNI0HHD[30]\ : MX2 - port map(A => \op1[30]\, B => \data_0[30]\, S => ldbp1, Y - => \un1_iu0_6[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I8_P0N : OR3A - port map(A => \data_0_2[7]\, B => \op1[7]\, C => ldbp1_2, Y - => N419); - - \r.f.pc_RNO_7[15]\ : MX2 - port map(A => \fpc[15]\, B => \tba[3]\, S => - rstate_6314_d_0, Y => \xc_trap_address[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I303_Y_0 : AX1D - port map(A => N430_0, B => ADD_33x33_fast_I246_Y_0_a3, C - => \un6_ex_add_res_s0_1[13]\, Y => - \un6_ex_add_res_s0[13]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I234_Y_0\ : AOI1 - port map(A => N455, B => N452, C => N451, Y => - ADD_30x30_fast_I234_Y_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I29_P0N : OR2 - port map(A => \un1_iu0_6[28]\, B => \data_0[28]\, Y => N482); - - \r.e.shcnt_RNI490TB[2]\ : MX2C - port map(A => \shiftin_11[21]\, B => \shiftin_11[17]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[17]\); - - \r.e.op2_RNIKONB1_0[27]\ : OR2 - port map(A => \un1_iu0_6[27]\, B => \un1_iu0_5[93]\, Y => - \logicout_3[27]\); - - \r.e.ctrl.tt[2]\ : DFN1E0 - port map(D => \tt_1[2]\, CLK => lclk_c, E => holdn, Q => - \tt_3[2]\); - - \r.e.shcnt_RNI36MUA[2]\ : MX2C - port map(A => \shiftin_11[17]\, B => \shiftin_11[13]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[13]\); - - \r.a.imm_RNO[30]\ : MX2 - port map(A => \inst_0[20]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[148]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I317_Y_0_0 : XOR2 - port map(A => \op2[26]\, B => \un1_iu0_6[26]\, Y => - ADD_33x33_fast_I317_Y_0_0); - - \r.e.ctrl.wreg_RNO\ : NOR3B - port map(A => ra_bpannul_1, B => wreg_0, C => \un1_p0_6[0]\, - Y => wreg_1_10); - - \r.m.icc_RNO_13[2]\ : NOR3B - port map(A => icc_0_sqmuxa_1_0, B => icc_0_sqmuxa_1_12, C - => \logicout[30]\, Y => icc_0_sqmuxa_1_22); - - \r.e.ctrl.inst_RNIKC1E_0[20]\ : OR2 - port map(A => \inst_1[20]\, B => \inst[19]\, Y => N_3749_1); - - \r.x.ctrl.pc_RNI29R31[2]\ : MX2C - port map(A => \un1_p0_6[354]\, B => \pc_0[2]\, S => - s_3_sqmuxa_0, Y => N_3393); - - un6_ex_add_res_d0_ADD_33x33_fast_I195_Y : AO1A - port map(A => N599_0, B => N606_0, C => N598_0, Y => N664_0); - - \r.x.ctrl.ld_0_RNIH0TN2\ : NOR3C - port map(A => bpdata6_8, B => bpdata6_7, C => bpdata6_9, Y - => bpdata6_0_0); - - \r.d.inull_RNIFV6VG2\ : OA1B - port map(A => holdn, B => de_hold_pc_1_0, C => mds, Y => - mexc_1_sqmuxa_1_0); - - \r.e.op1_RNI6C9M3[29]\ : NOR3C - port map(A => \rfo_m[29]\, B => \d_iv_1[29]\, C => - \op1_m_0[29]\, Y => \d_iv_3[29]\); - - \r.a.ctrl.ld_RNI99DC\ : AND2 - port map(A => wreg_0, B => ld_1, Y => ldlock2_0); - - \r.f.pc_RNI3830J[6]\ : MX2B - port map(A => \fpc[6]\, B => \eaddress[6]\, S => jump, Y - => N_4049); - - \r.a.ctrl.inst_RNIBO0L[31]\ : NOR3A - port map(A => \inst[22]\, B => \inst[30]\, C => \inst[31]\, - Y => cp_disabled_2_sqmuxa_0); - - \r.a.ctrl.inst_RNI5H3O1_0[23]\ : OR3 - port map(A => N_202, B => illegal_inst37_4, C => N_212, Y - => cp_disabled_6_sqmuxa); - - \r.e.op1_RNI11UH[20]\ : MX2 - port map(A => \op1[20]\, B => \data_0_2[20]\, S => ldbp1_4, - Y => \un1_iu0_6[20]\); - - \r.e.op2_RNO_5[24]\ : AOI1B - port map(A => \result[24]\, B => d31_0, C => \imm_m_i[24]\, - Y => \d_1_iv_0[24]\); - - \r.e.op2[2]\ : DFN1E0 - port map(D => N_286, CLK => lclk_c, E => holdn, Q => - \op2[2]\); - - \r.e.ctrl.pc[23]\ : DFN1E0 - port map(D => \pc_3[23]\, CLK => lclk_c, E => holdn, Q => - \pc_0[23]\); - - \r.m.result[13]\ : DFN1E0 - port map(D => \eres2[13]\, CLK => lclk_c, E => holdn, Q => - \maddress[13]\); - - \r.w.s.pil_RNI05PJ3[2]\ : OA1A - port map(A => \pil[2]\, B => aluresult_11_sqmuxa, C => - \aluresult_1_iv_0[10]\, Y => \aluresult_1_iv_2[10]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I90_Y : NOR2B - port map(A => N404_1, B => N401_0, Y => N549); - - \r.f.pc_RNO_5[22]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[22]\, Y => \xc_trap_address_m[22]\); - - \r.f.pc[19]\ : DFN1E0 - port map(D => \pc_1[19]\, CLK => lclk_c, E => holdn, Q => - \fpc[19]\); - - \r.x.ctrl.pc[10]\ : DFN1E0 - port map(D => \pc_2[10]\, CLK => lclk_c, E => holdn, Q => - \pc[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I20_P0N\ : OR2 - port map(A => \inst_0[20]\, B => \dpc[22]\, Y => N419_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I262_Y_0_0\ : XOR2 - port map(A => \dpc[4]\, B => \inst_0_RNI2NUM[2]\, Y => - ADD_30x30_fast_I262_Y_0_0); - - \r.x.data_0_RNI7VS8[6]\ : XOR2 - port map(A => \data_0[6]\, B => invop2_0, Y => N_4253); - - \r.a.wunf\ : DFN1E0 - port map(D => \wovf_exc_1_sqmuxa\, CLK => lclk_c, E => - holdn, Q => wunf); - - un6_ex_add_res_d1_ADD_33x33_fast_I303_Y_0 : AX1B - port map(A => N430, B => ADD_33x33_fast_I246_Y_0_a3_0, C - => ADD_33x33_fast_I303_Y_0_0, Y => - \un6_ex_add_res_s1_i[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I140_Y : OR2B - port map(A => N541_1, B => N537_1, Y => N603_0); - - \r.x.ctrl.rd_RNI5G6A1[1]\ : NOR3B - port map(A => bpdata6_2, B => bpdata6_1, C => N_3356_3, Y - => bpdata6_9); - - \r.m.ctrl.inst[19]\ : DFN1E0 - port map(D => \inst[19]\, CLK => lclk_c, E => holdn, Q => - \inst_3[19]\); - - \r.e.jmpl_RNILTD2M\ : OR2B - port map(A => \shiftin_17[6]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[6]\); - - \r.e.op1_RNO[28]\ : MX2C - port map(A => \d_i[28]\, B => \d_i[29]\, S => N_227, Y => - \aop1[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I82_Y : AND2 - port map(A => N413, B => N416, Y => N541); - - \r.x.laddr_RNI45NB9[1]\ : MX2 - port map(A => \maddress[1]\, B => \laddr[1]\, S => - dco_i_2(132), Y => \me_laddr_2[1]\); - - \r.m.icc[3]\ : DFN1E0 - port map(D => \icco[3]\, CLK => lclk_c, E => holdn, Q => - \icc[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I274_Y_0_a3 : NOR2B - port map(A => N796_0, B => N443_1, Y => - ADD_33x33_fast_I274_Y_0_a3); - - \r.m.y_RNO_0[19]\ : AOI1B - port map(A => wy_1_0, B => \y[19]\, C => \y_m[19]\, Y => - \y_iv_1[19]\); - - \r.e.ldbp2_2_RNI3L9F582\ : OR3B - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_24, B => - \un1_addout_12\, C => \eaddress[31]\, Y => un1_addout); - - \r.w.s.tba_RNI74CA1[6]\ : OR2B - port map(A => \tba[6]\, B => aluresult_12_sqmuxa, Y => - \tba_m[6]\); - - \r.w.result_RNIL8V6[0]\ : OR2B - port map(A => \result_0[0]\, B => d31, Y => \result_m_i[0]\); - - \r.e.aluop_2_RNIDPAI2[1]\ : MX2C - port map(A => N_3557, B => \logicout_3[30]\, S => - \aluop_2[1]\, Y => N_3589); - - un6_ex_add_res_d2_ADD_33x33_fast_I300_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[9]\, B => \data_0[9]\, Y => - \un6_ex_add_res_s2_1[10]\); - - \r.e.alusel_RNO_3[0]\ : OR3A - port map(A => \alusel_i_0_a5_0_0[0]\, B => N_487, C => - N_492, Y => N_352); - - \r.m.y_RNI9N6P6[21]\ : NOR3C - port map(A => \cpi_m[166]\, B => \y_m_1[21]\, C => - \bpdata_m[21]\, Y => \aluresult_1_iv_3[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I266_Y_0_a3 : NOR2A - port map(A => N782_1, B => N_15_0, Y => N_74); - - \r.m.ctrl.inst[26]\ : DFN1E0 - port map(D => \inst_1[26]\, CLK => lclk_c, E => holdn, Q - => \inst_3[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I184_Y : NOR2A - port map(A => N587_1, B => N595, Y => N653_1); - - \r.x.ctrl.inst[19]\ : DFN1E0 - port map(D => \inst_3[19]\, CLK => lclk_c, E => holdn, Q - => \inst_1[19]\); - - \r.m.y_RNO_0[3]\ : NOR3C - port map(A => \y_m[4]\, B => \y_m_0[3]\, C => \y_iv_1[3]\, - Y => \y_iv_2[3]\); - - \r.e.op1_RNIHHAT4[20]\ : AO1A - port map(A => \bpdata[20]\, B => edata_2_sqmuxa, C => - \op1_i_m[20]\, Y => \edata2_0_iv_0[20]\); - - \r.e.shcnt_RNIBG9HR[1]\ : MX2C - port map(A => \shiftin_14[25]\, B => \shiftin_14[23]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[23]\); - - \r.e.ctrl.pc_RNI61K11[11]\ : OR2B - port map(A => \pc_2[11]\, B => jmpl_4, Y => \cpi_m[156]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_2\ : OR2A - port map(A => irl_0(1), B => \pil[1]\, Y => \ACT_LT4_E[1]\); - - \r.m.result_RNIBVU53[10]\ : NOR3C - port map(A => \d_iv_0[10]\, B => \result_m_0[10]\, C => - \rfo_m[10]\, Y => \d_iv_2[10]\); - - \r.e.aluop_0_RNILC591[1]\ : XOR3 - port map(A => \un1_iu0_6[30]\, B => \aluop_0[1]\, C => - \un1_iu0_5[96]\, Y => N_6853); - - \comb.un6_xc_exception_RNIIV70L2\ : AOI1B - port map(A => I_5, B => un2_rstn_4_0_0, C => - \xc_trap_address_m[3]\, Y => \npc_iv_2[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I90_Y : NOR2B - port map(A => N404, B => N401_1, Y => N549_1); - - \r.e.ctrl.inst_RNII01E[24]\ : OR2B - port map(A => \inst_1[22]\, B => \inst[24]\, Y => - aluresult_13_sqmuxa_3); - - \r.d.annul_RNIBH7NS4\ : OR2B - port map(A => I_38, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[7]\); - - \r.m.ctrl.rd[7]\ : DFN1E0 - port map(D => \rd_1[7]\, CLK => lclk_c, E => holdn, Q => - \rd_0[7]\); - - \r.a.rsel2_0_RNIUSKM[0]\ : NOR2B - port map(A => \result_m_i[1]\, B => \cpi_m_i[353]\, Y => - \d_1_iv_1[1]\); - - un2_rstn_5_RNI5B15D2 : NOR2B - port map(A => \tmp_m[3]\, B => \pc_4_m[3]\, Y => - \npc_iv_0[3]\); - - \r.m.y_RNO_0[7]\ : NOR3C - port map(A => \y_m_0[8]\, B => \y_m_0[7]\, C => \y_iv_1[7]\, - Y => \y_iv_2[7]\); - - \r.f.pc_RNO_2[27]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[27]\, C => - \xc_trap_address_m[27]\, Y => \pc_1_iv_0[27]\); - - \r.d.inst_0_RNIV323[21]\ : NOR2B - port map(A => \inst_0_0[21]\, B => \inst_0[20]\, Y => - un14_op_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I164_Y : NOR2B - port map(A => N575_2, B => N567_0, Y => N633_0); - - \r.e.op1_RNIV6NF[31]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[31]\, Y => - \op1_i_m[31]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_8\ : NOR2A - port map(A => \pil[2]\, B => irl_0(2), Y => \ACT_LT4_E[7]\); - - \r.e.shcnt_RNI8LT6T[1]\ : MX2C - port map(A => \shiftin_14[29]\, B => \shiftin_14[27]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[27]\); - - \r.x.ctrl.ld_0\ : DFN1E0 - port map(D => ld, CLK => lclk_c, E => holdn, Q => ld_0); - - \r.m.y_RNO_0[20]\ : AOI1B - port map(A => wy_1_0, B => \y[20]\, C => \y_m[20]\, Y => - \y_iv_1[20]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I310_Y_0_0 : XOR2 - port map(A => \op2[19]\, B => \op1_RNID1VH[19]\, Y => - ADD_33x33_fast_I310_Y_0_0); - - \r.e.shcnt_RNI0V6M[3]\ : MX2C - port map(A => \shcnt[3]\, B => N_3307, S => ldbp2_0, Y => - \ex_shcnt_1_i_0[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I13_G0N\ : NOR2B - port map(A => \inst_0[13]\, B => \dpc[15]\, Y => N397_2); - - \r.a.ctrl.inst_RNID81L[22]\ : NOR2B - port map(A => \inst[22]\, B => alusel24_2, Y => - illegal_inst_1_sqmuxa_i_0); - - \r.m.nalign_RNIV7Q8\ : OR2A - port map(A => nalign, B => \inst[21]\, Y => - trap_0_sqmuxa_1_0); - - \r.m.result_RNO[2]\ : MX2 - port map(A => \aluresult[2]\, B => \op1[2]\, S => - un17_casaen_0, Y => \eres2[2]\); - - \r.w.s.y_RNO_2[1]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[1]\, Y => - N_400); - - \r.f.pc_RNO_1[31]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[31]\, C => - \pc_1_iv_0[31]\, Y => \pc_1_iv_1[31]\); - - \r.e.shleft_RNI3RMD2\ : MX2B - port map(A => \shiftin_5[45]\, B => \shiftin_5[29]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[29]\); - - \r.e.op1_RNI0NCR1[18]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[18]\, Y => - \ex_op1_i_m[18]\); - - \r.e.ldbp2_RNIVPRB3\ : OR2 - port map(A => \eaddress[1]\, B => \eaddress[0]\, Y => - un12_ex_add_res); - - \r.e.aluop_0_RNIMC591[2]\ : XA1 - port map(A => \un1_iu0_5[96]\, B => \aluop_0[2]\, C => - \un1_iu0_6[30]\, Y => N_3557); - - \r.a.ctrl.inst_RNIK42S[21]\ : NOR3A - port map(A => inst_11_0, B => \inst_2[20]\, C => - \inst_2[21]\, Y => inst_11_1); - - \r.a.rsel2_RNI9LB_2[1]\ : NOR2A - port map(A => \rsel2[2]\, B => \rsel2[1]\, Y => d29_0); - - \r.e.op2_RNO_8[25]\ : OR3B - port map(A => d29_0, B => \imm[25]\, C => \rsel2[0]\, Y => - \imm_m_i[25]\); - - \r.d.mexc\ : DFN1E0 - port map(D => mexc_2, CLK => lclk_c, E => inull_RNIFV6VG2_0, - Q => mexc_1); - - \r.e.sari\ : DFN1E0 - port map(D => sari_0, CLK => lclk_c, E => holdn, Q => sari); - - \r.w.result_RNIASGG[10]\ : AOI1B - port map(A => \un1_p0_6[362]\, B => d14, C => - \result_m_0_0[10]\, Y => \d_iv_0[10]\); - - \r.d.inst_0_RNO[30]\ : NOR2B - port map(A => rst, B => N_4630, Y => \inst_0_RNO[30]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I173_un1_Y : OAI1 - port map(A => I121_un1_Y, B => ADD_33x33_fast_I121_Y_0, C - => N577_1, Y => I173_un1_Y_i); - - \r.e.aluop_RNIUSCV5G[0]\ : MX2B - port map(A => \logicout[21]\, B => \icc_16[1]\, S => - un3_op_i, Y => N_4176); - - un6_ex_add_res_d0_ADD_33x33_fast_I247_Y : AO1 - port map(A => N665_0, B => N614_1, C => N664_0, Y => N808_1); - - \r.e.op2_RNO_3[10]\ : NOR3C - port map(A => \result_m_i[10]\, B => \imm_m_i[10]\, C => - \d_1_iv_1[10]\, Y => \d_1_iv_2[10]\); - - \r.a.rsel2_0_RNIO5CM2[0]\ : OR2B - port map(A => data2(3), B => d25_0, Y => \rfo_m_i[35]\); - - \r.a.ctrl.pc_RNI2KE2C[16]\ : MX2 - port map(A => \pc_0[16]\, B => N_3893, S => ex_bpmiss_1, Y - => \fe_pc[16]\); - - \r.e.aluop_RNIJ0UN6[0]\ : MX2C - port map(A => N_3569, B => N_3633, S => \aluop_1[0]\, Y => - \logicout[10]\); - - \r.e.bp_RNIE5V7\ : OA1B - port map(A => bp, B => bp_0, C => annul_1, Y => - de_fins_hold_1_1); - - \r.m.ctrl.trap_RNIALRKM1\ : OR2B - port map(A => tt_1_sqmuxa_1, B => un6_annul, Y => - N_4210_i_0); - - \r.e.op2[10]\ : DFN1E0 - port map(D => N_294, CLK => lclk_c, E => holdn, Q => - \op2[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I18_P0N : OR3A - port map(A => \data_0[17]\, B => \op1[17]\, C => ldbp1_0, Y - => N449); - - \r.w.result_RNISQ3C[3]\ : AOI1B - port map(A => \result[3]\, B => d31, C => \imm_m_i[3]\, Y - => \d_1_iv_0[3]\); - - \r.d.pc[13]\ : DFN1 - port map(D => \pc_RNO[13]\, CLK => lclk_c, Q => \dpc[13]\); - - \r.e.op2[26]\ : DFN1E0 - port map(D => N_310, CLK => lclk_c, E => holdn, Q => - \op2[26]\); - - \r.e.shcnt_RNIUQ6M_0[2]\ : MX2C - port map(A => \shcnt[2]\, B => N_3306, S => ldbp2_0, Y => - \ex_shcnt_1_i[2]\); - - \r.e.op2_RNIPUUD4[5]\ : AOI1B - port map(A => \un1_iu0_5[71]\, B => aluresult_7_sqmuxa_0_0, - C => \aluresult_1_iv_0[5]\, Y => \aluresult_1_iv_1[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I250_Y_0_o3 : NOR2 - port map(A => N418_1, B => ADD_33x33_fast_I250_Y_0_a3, Y - => N817_i); - - \r.e.aluop_RNI7R22F[1]\ : NOR2B - port map(A => \edata2_iv_2[25]\, B => \edata2_iv_1[25]\, Y - => edata2_iv_i_0(25)); - - \r.e.ctrl.tt_RNO_2[1]\ : NOR2B - port map(A => trap_4_1, B => privileged_inst_5, Y => N_4036); - - \r.x.result_RNI2NED[18]\ : MX2 - port map(A => \result_0[18]\, B => \data_0_0[18]\, S => - ld_0, Y => \un1_p0_6[370]\); - - \r.e.jmpl_RNI8D3FJ7\ : OR3C - port map(A => \aluresult_1_iv_8[29]\, B => - \shiftin_17_m_0[29]\, C => \un6_ex_add_res_m[30]\, Y => - \aluresult[29]\); - - \r.e.invop2_RNI7J1L4\ : MX2C - port map(A => \un6_ex_add_res_s2[5]\, B => - \un6_ex_add_res_s0[5]\, S => invop2, Y => N_6644); - - \r.w.s.tt_RNILFEJ3[3]\ : AOI1B - port map(A => aluresult_12_sqmuxa_0_0, B => \irl[3]\, C => - \aluresult_1_iv_2[7]\, Y => \aluresult_1_iv_4[7]\); - - \r.m.icc_RNO_3[2]\ : MX2C - port map(A => un1_addout, B => icc_0_sqmuxa_1_i, S => - aluresult12, Y => \icc_16[2]\); - - \r.e.shcnt_RNI2NUM6[3]\ : MX2 - port map(A => \shiftin_8[39]\, B => \shiftin_8[31]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I66_Y : OR2A - port map(A => N440_1, B => N437_2, Y => N525_0); - - \r.a.ctrl.inst_RNIGVLQB[31]\ : OR2 - port map(A => fp_disabled_4, B => cp_disabled_4, Y => - trap_4_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I301_Y_0 : XOR2 - port map(A => N811_0, B => \un6_ex_add_res_s2_1[11]\, Y => - \un6_ex_add_res_s2[11]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I95_un1_Y : OR3C - port map(A => N485, B => N488_2, C => N496_0, Y => - I95_un1_Y); - - \r.x.result[17]\ : DFN1E0 - port map(D => \maddress[17]\, CLK => lclk_c, E => holdn, Q - => \result_0[17]\); - - \r.d.inull_RNI35OFT_0\ : NOR2 - port map(A => un2_rstn_5_0_i, B => un18_hold_pc, Y => - de_hold_pc_1_0); - - \r.a.rsel1_RNIMB2204[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[14]\, Y => - \aluresult_m_0[14]\); - - \r.a.ctrl.inst_RNIE41S[30]\ : NOR3 - port map(A => N_203, B => \inst[30]\, C => \inst_2[20]\, Y - => aluop_0_1_0_a5_3_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I16_P0N : OR2 - port map(A => \un1_iu0_6[15]\, B => \op2[15]\, Y => N443); - - \r.x.ctrl.pc[21]\ : DFN1E0 - port map(D => \pc_3[21]\, CLK => lclk_c, E => holdn, Q => - \pc_2[21]\); - - \r.m.result[2]\ : DFN1E0 - port map(D => \eres2[2]\, CLK => lclk_c, E => holdn, Q => - \maddress[2]\); - - \r.e.op1_RNI5HFC[1]\ : OR2B - port map(A => \op1[1]\, B => un14_casaen_s1_0, Y => - \op1_m_0[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I20_G0N : NOR2B - port map(A => \op1_RNID1VH[19]\, B => \op2[19]\, Y => - N454_2); - - \r.e.shcnt_RNIPR6OB[2]\ : MX2C - port map(A => \shiftin_11[20]\, B => \shiftin_11[16]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[16]\); - - \r.e.op1_RNIOC5I1[0]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[0]\, Y => - \ex_op1_i_m[0]\); - - \r.a.ctrl.inst_RNIT2954[13]\ : AOI1B - port map(A => illegal_inst_4_m_0, B => illegal_inst33, C - => cp_disabled_3_sqmuxa_2, Y => illegal_inst_7_iv_1); - - \r.a.ctrl.annul\ : DFN1E0 - port map(D => ctrl_annul_i, CLK => lclk_c, E => holdn, Q - => annul_2); - - \r.x.result_RNI3OJJ5[15]\ : OR2B - port map(A => \bpdata[15]\, B => N_3974, Y => - \bpdata_m[15]\); - - un6_fe_npc_I_84 : XOR2 - port map(A => N_93, B => \fe_pc[16]\, Y => I_84); - - un6_ex_add_res_d2_ADD_33x33_fast_I263_Y_0 : AO1 - port map(A => N574_0, B => N567_0, C => N566, Y => - ADD_33x33_fast_I263_Y_0_0); - - \r.w.s.et_RNI1DI8\ : NOR2B - port map(A => et, B => pv_1, Y => un6_annul_1); - - \r.e.aluop_RNI5JL9F[1]\ : NOR2B - port map(A => \edata2_iv_2[30]\, B => \edata2_iv_1[30]\, Y - => edata2_iv_i_0(30)); - - \r.e.op1_RNITECR1[16]\ : NOR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[16]\, Y => - \ex_op1_i_m[16]\); - - \r.x.result_RNIAGOA5[11]\ : NOR2B - port map(A => \bpdata[11]\, B => \aluop_RNIGM3N1[2]\, Y => - \bpdata_i_m[11]\); - - \r.e.op1_RNIG7O8[5]\ : MX2 - port map(A => \op1[5]\, B => \data_0[5]\, S => ldbp1_3, Y - => \un1_iu0_6[5]\); - - \r.x.data_0_RNO[15]\ : OR3 - port map(A => \dco_m_0[111]\, B => \data_0_1_0_iv_0[15]\, C - => \data_0_1_4[9]\, Y => \data_0_1[15]\); - - \r.x.data_0_RNI83T8[7]\ : XOR2 - port map(A => \data_0_2[7]\, B => invop2_0, Y => N_4254); - - un6_ex_add_res_d0_ADD_33x33_fast_I9_G0N : NOR3A - port map(A => \op1[8]\, B => ldbp1_0, C => \data_0[8]\, Y - => N421); - - un6_ex_add_res_d0_ADD_33x33_fast_I172_Y : NOR2B - port map(A => N583_0, B => N575_0, Y => N641_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I41_Y_i\ : OAI1 - port map(A => \dpc[25]\, B => \inst_0_1[25]\, C => N425, Y - => N_11); - - un6_ex_add_res_d0_ADD_33x33_fast_I18_G0N : NOR3A - port map(A => \op1[17]\, B => ldbp1_0, C => \data_0[17]\, Y - => N448); - - un6_ex_add_res_d0_ADD_33x33_fast_I180_Y : NOR2A - port map(A => N583_0, B => N591_2, Y => N649_0); - - \r.e.op1_RNIRGNO6[23]\ : OR3 - port map(A => \bpdata_i_m[23]\, B => \op1_i_m[23]\, C => - \ex_op1_i_m[23]\, Y => \edata2_0_iv_1[23]\); - - \r.a.ctrl.rd_RNII0FK1[0]\ : XA1A - port map(A => \rd_2[0]\, B => \inst_0_RNI0FUM[0]\, C => - un1_de_ren1_1_i, Y => un1_de_ren1_NE_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I12_G0N : NOR3A - port map(A => \op1[11]\, B => ldbp1, C => \data_0_2[11]\, Y - => N430_0); - - \r.a.ctrl.rett_RNIUMQB\ : OR2 - port map(A => rett_2, B => rett_3, Y => rett_0_0); - - \r.a.ctrl.trap\ : DFN1E0 - port map(D => mexc_1, CLK => lclk_c, E => holdn, Q => - trap_1); - - \r.m.dci.asi[3]\ : DFN1E0 - port map(D => \asi[3]\, CLK => lclk_c, E => holdn, Q => - asi_0(3)); - - \r.m.ctrl.pc_RNI42IF[17]\ : MX2 - port map(A => \pc_3[17]\, B => \pc[17]\, S => \npc_1[1]\, Y - => N_3258); - - \r.e.ctrl.pc[21]\ : DFN1E0 - port map(D => \pc[21]\, CLK => lclk_c, E => holdn, Q => - \pc_0[21]\); - - \r.e.alusel_RNIRC5C_0[0]\ : NOR3A - port map(A => \alusel[1]\, B => \alusel[0]\, C => jmpl, Y - => aluresult_3_sqmuxa); - - \r.e.alusel_RNIJDA9_0[0]\ : OR2 - port map(A => \alusel[1]\, B => \alusel[0]\, Y => - aluresult12); - - \r.m.icc_RNI88I3[3]\ : XNOR2 - port map(A => \icc[1]\, B => \icc[3]\, Y => N_211); - - \r.e.aluop_0_RNIS2ML[1]\ : AO1 - port map(A => \un1_iu0_6[24]\, B => \aluop_0[0]\, C => - \aluop_0[1]\, Y => \logicout_5_0_i_a5_0_0[24]\); - - \r.m.result_RNI3TGL[2]\ : OA1A - port map(A => \maddress[2]\, B => d27, C => \cpi_m_i[354]\, - Y => \d_1_iv_1[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I171_un1_Y : OR2B - port map(A => N582_1, B => N575_0, Y => I171_un1_Y_i); - - \r.a.ctrl.trap_RNI2LGGI\ : NOR2A - port map(A => privileged_inst_5, B => trap_1, Y => - \tt_9_1[0]\); - - \r.a.ctrl.ld_RNO_0\ : OR2A - port map(A => un54_casaen, B => call_hold7_i, Y => - write_reg_0_sqmuxa_1); - - \r.e.aluop_RNIO3ML1[0]\ : XA1B - port map(A => N_246, B => \aluop_1[0]\, C => - \un1_iu0_6[24]\, Y => N_447); - - \r.x.result_RNI03MJ3[28]\ : MX2C - port map(A => \un1_iu0_6[28]\, B => \un1_p0_6[380]\, S => - bpdata6, Y => \bpdata[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I160_Y : NOR2B - port map(A => N571_2, B => N563, Y => N629_0); - - \r.a.ctrl.inst_RNIDG9A_0[29]\ : NOR2A - port map(A => pv, B => \inst[29]\, Y => un6_rabpmiss_0); - - \r.m.y_RNO_4[20]\ : OR2B - port map(A => \y[21]\, B => mulstep_0, Y => \y_m_2[21]\); - - \r.m.y_RNO_1[3]\ : OR2B - port map(A => \y[4]\, B => mulstep_1, Y => \y_m[4]\); - - \r.d.annul_RNIFVDAE2\ : OR2A - port map(A => un8_op, B => ctrl_annul_i, Y => un1_wcwp); - - \comb.branch_address.tmp_ADD_30x30_fast_I271_Y_0\ : XOR2 - port map(A => N735, B => ADD_30x30_fast_I271_Y_0_0, Y => - \tmp[13]\); - - \r.e.op1_RNICPUH[26]\ : MX2 - port map(A => \op1[26]\, B => \data_0[26]\, S => ldbp1_3, Y - => \un1_iu0_6[26]\); - - \r.d.inst_0_RNI66J4_2[23]\ : AOI1B - port map(A => \inst_0_0[23]\, B => \inst_0_0[22]\, C => - \inst_0_0[24]\, Y => ldcheck1_5_i_a6_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I243_un1_Y : NOR2B - port map(A => N672, B => N657, Y => I243_un1_Y_1); - - \r.d.inst_0_0_0_RNI9O79[21]\ : MX2 - port map(A => \un1_p0_6_0[60]\, B => \inst_0_0[22]\, S => - \inst_0[30]\, Y => \inst_0_0_0_RNI9O79[21]\); - - \r.d.cwp_RNO_1[1]\ : MX2 - port map(A => \cwp[1]\, B => \maddress[1]\, S => wcwp, Y - => N_4219); - - \comb.branch_address.tmp_ADD_30x30_fast_I236_un1_Y_0\ : NOR2B - port map(A => N591, B => N575, Y => - ADD_30x30_fast_I236_un1_Y_0); - - \r.a.bp_RNIQD984_0\ : OR2B - port map(A => ra_bpmiss_1_1, B => branch, Y => ra_bpmiss_1); - - \r.w.s.tba_RNI9E524[16]\ : AOI1B - port map(A => \tba[16]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[28]\, Y => \aluresult_1_iv_3[28]\); - - \r.m.y_RNO_1[19]\ : AOI1B - port map(A => \y_0[19]\, B => y08_0, C => \y_m_0[20]\, Y - => \y_iv_0[19]\); - - \r.d.cnt_RNISDD3[1]\ : NOR2A - port map(A => \cnt_0[1]\, B => annul_1, Y => ldchkex_0); - - wovf_exc_0_sqmuxa : NAND2 - port map(A => un8_op, B => un25_op, Y => - \wovf_exc_0_sqmuxa\); - - un6_ex_add_res_d1_ADD_33x33_fast_I299_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[8]\, B => \op2[8]\, Y => - ADD_33x33_fast_I299_Y_0_0); - - \r.e.ldbp2_1_RNIMTP2J2\ : MX2C - port map(A => \un6_ex_add_res_s1_i[18]\, B => N_6637, S => - ldbp2_1, Y => \eaddress[17]\); - - \r.d.pc_RNI4KCA4[9]\ : MX2 - port map(A => \dpc[9]\, B => \fpc[9]\, S => \ra_bpmiss_1_0\, - Y => N_3886); - - \r.m.y_RNO[10]\ : OR3C - port map(A => \y_iv_1[10]\, B => \y_iv_0[10]\, C => - \logicout_m[10]\, Y => \y_1[10]\); - - \r.d.pc[15]\ : DFN1 - port map(D => \pc_RNO[15]\, CLK => lclk_c, Q => \dpc[15]\); - - un6_fe_npc_I_156 : XOR2 - port map(A => N_42, B => \fe_pc[25]\, Y => I_156); - - \r.d.pc[30]\ : DFN1 - port map(D => \pc_RNO[30]\, CLK => lclk_c, Q => \dpc[30]\); - - \r.x.data_0_RNO_2[11]\ : NOR2A - port map(A => \data_0_2[11]\, B => ld_3, Y => - \data_0_m[11]\); - - \r.m.result_0_RNI4MR8[3]\ : OR2B - port map(A => d13_0, B => \maddress_0[3]\, Y => - \result_m_0[3]\); - - \r.e.op2_RNO_5[21]\ : OR2B - port map(A => data2(21), B => d25, Y => \rfo_m_i[53]\); - - \r.m.y_RNO_0[16]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[16]\, C => \y_m_0[16]\, - Y => \y_iv_1[16]\); - - \r.f.pc_RNO_2[12]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[12]\, C => - \xc_trap_address_m[12]\, Y => \pc_1_iv_0[12]\); - - \r.e.shcnt_RNI5I91O[1]\ : MX2C - port map(A => \shiftin_14[16]\, B => \shiftin_14[14]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[14]\); - - \r.d.inull_RNI35OFT\ : NOR2 - port map(A => un2_rstn_5_0_i, B => un18_hold_pc, Y => - \de_hold_pc_1\); - - un2_rstn_5_RNI1D94ME : OR2B - port map(A => m14_2, B => N_6620, Y => N_15); - - \r.x.data_0[14]\ : DFN1E0 - port map(D => \data_0_1[14]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[14]\); - - \r.w.result[4]\ : DFN1E0 - port map(D => \wdata[4]\, CLK => lclk_c, E => holdn, Q => - \result_0[4]\); - - \r.e.op2_RNO_4[24]\ : NOR2B - port map(A => \result_m_i[24]\, B => \cpi_m_i[376]\, Y => - \d_1_iv_1[24]\); - - \r.e.op2_RNO[25]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[25]\, Y => N_309); - - \r.e.ldbp2_2_RNIHO2FK1\ : NOR2A - port map(A => annul_RNI5L7FE1, B => \eaddress[3]\, Y => - \un6_ex_add_res_m_1[4]\); - - \r.m.ctrl.pc_RNI17AE[7]\ : MX2 - port map(A => \pc_2[7]\, B => \pc_3[7]\, S => \npc_0[1]\, Y - => N_3248); - - \r.x.data_0_RNO_1[21]\ : NOR2A - port map(A => \data_0[21]\, B => ld_3, Y => \data_0_m[21]\); - - \r.e.aluop_RNIF68AC[2]\ : AOI1B - port map(A => \bpdata[10]\, B => aluresult_5_sqmuxa, C => - \aluresult_1_iv_2[26]\, Y => \aluresult_1_iv_4[26]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I295_Y_0 : AX1B - port map(A => N406, B => ADD_33x33_fast_I206_Y_0_a3, C => - \un6_ex_add_res_s2_1[5]\, Y => \un6_ex_add_res_s0[5]\); - - \r.w.s.tba_RNI3M424[13]\ : AOI1B - port map(A => \tba[13]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[25]\, Y => \aluresult_1_iv_3[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I283_Y_0\ : XOR2 - port map(A => N706, B => ADD_30x30_fast_I283_Y_0_0, Y => - \tmp[25]\); - - \r.x.result_RNI5FI75[3]\ : NAND2 - port map(A => N_3957_1, B => \bpdata[3]\, Y => - \bpdata_m_1[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_Y_0 : MIN3 - port map(A => \data_0_0[29]\, B => \un1_iu0_6[29]\, C => - N481_1, Y => ADD_33x33_fast_I260_Y_0_1); - - \r.e.op2_RNO_0[15]\ : OR3C - port map(A => \op1_m_i[15]\, B => \d_1_iv_3[15]\, C => - \aluresult_m_i[15]\, Y => \d_1[15]\); - - \r.d.inst_0[4]\ : DFN1 - port map(D => \inst_0_RNO[4]\, CLK => lclk_c, Q => - \inst_0[4]\); - - \r.x.ctrl.annul\ : DFN1E0 - port map(D => annul_RNIPFOQ, CLK => lclk_c, E => holdn, Q - => annul_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I204_un1_Y\ : NOR2B - port map(A => N596, B => N581, Y => I204_un1_Y); - - \r.x.icc[3]\ : DFN1E0 - port map(D => \icc[3]\, CLK => lclk_c, E => holdn, Q => - \icc_2[3]\); - - \r.e.aluop_RNIJ6473[1]\ : MX2C - port map(A => N_3539, B => \logicout_3[12]\, S => - \aluop_3[1]\, Y => N_3571); - - un6_ex_add_res_d0_ADD_33x33_fast_I14_P0N : OR3A - port map(A => \data_0[13]\, B => \op1[13]\, C => ldbp1_0, Y - => N437); - - un6_ex_add_res_d0_ADD_33x33_fast_I129_Y : OR3 - port map(A => I67_un1_Y, B => N436_1, C => I129_un1_Y, Y - => N592); - - \r.x.result_RNINK5H2[6]\ : OR2A - port map(A => \result_0[6]\, B => cwp_1_sqmuxa_0, Y => - \result_m[6]\); - - \r.m.y_RNIB3QA7[29]\ : OA1A - port map(A => aluresult_6_sqmuxa, B => \bpdata[29]\, C => - \aluresult_1_iv_0[29]\, Y => \aluresult_1_iv_2[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I274_Y_0_o3 : AOI1 - port map(A => N796, B => N443, C => N442_0, Y => N794_i); - - \r.x.ctrl.pc_RNIEIHF[15]\ : MX2 - port map(A => \pc_0[15]\, B => \pc_2[15]\, S => \npc_0[1]\, - Y => N_3226); - - \r.d.cnt_RNO_1[1]\ : OR3 - port map(A => ldlock, B => annul_1, C => hold_pc_2_sqmuxa, - Y => cnt_3_sqmuxa_0); - - \r.a.rfa1[7]\ : DFN1E0 - port map(D => \un3_de_ren1[98]\, CLK => lclk_c, E => holdn, - Q => \rfa1[7]\); - - \r.x.data_0_RNO_3[5]\ : OA1A - port map(A => \data_0[5]\, B => ld_0_0, C => \dco_m_i[109]\, - Y => \data_0_1_1_iv_0[5]\); - - \r.e.ldbp2_0_RNIP5D6S\ : MX2C - port map(A => \un6_ex_add_res_s1_i[11]\, B => N_6630, S => - ldbp2_0, Y => \eaddress[10]\); - - \r.d.annul_RNIP2H4_0\ : NOR2 - port map(A => annul_1, B => N_85, Y => hold_pc_0_sqmuxa); - - \r.a.ctrl.inst_RNIIG1S[31]\ : NOR3A - port map(A => N_216, B => \inst[30]\, C => \inst[31]\, Y - => cp_disabled_3_sqmuxa_2_0); - - \r.x.result_RNIPS6E[30]\ : MX2 - port map(A => \result_0[30]\, B => \data_0[30]\, S => ld_4, - Y => \un1_p0_6[382]\); - - \r.e.ctrl.rd[3]\ : DFN1E0 - port map(D => \rd_1[3]\, CLK => lclk_c, E => holdn, Q => - \rd[3]\); - - \r.e.aluop_RNIVGDQB[1]\ : NOR2 - port map(A => \edata2_0_iv_1[14]\, B => \bpdata_i_m_2[6]\, - Y => edata2_0_iv(14)); - - \r.a.ctrl.pc[17]\ : DFN1E0 - port map(D => \dpc[17]\, CLK => lclk_c, E => holdn, Q => - \pc[17]\); - - \r.w.s.wim_RNIC5RD2[6]\ : OR2B - port map(A => \wim[6]\, B => aluresult_13_sqmuxa, Y => - \wim_m[6]\); - - \r.m.y[7]\ : DFN1E0 - port map(D => \y_1[7]\, CLK => lclk_c, E => holdn, Q => - \y[7]\); - - \r.m.dci.asi[1]\ : DFN1E0 - port map(D => \asi[1]\, CLK => lclk_c, E => holdn, Q => - asi_0(1)); - - \r.e.aluop_RNISTEO2[1]\ : MX2C - port map(A => N_3556, B => \logicout_3[29]\, S => - \aluop_3[1]\, Y => N_3588); - - \r.x.rstate_RNI5S7L_1[1]\ : NOR2 - port map(A => annul_1_0, B => \rstate_d[2]\, Y => - rstate_9_0); - - \r.a.ctrl.inst_RNIP42A1[21]\ : OR3 - port map(A => N_201, B => N_216, C => N_492, Y => N_365); - - \r.x.npc_RNIMBFL[0]\ : MX2C - port map(A => N_3229, B => N_3259, S => \npc[0]\, Y => - \xc_result[18]\); - - \r.m.result_RNILLE71[2]\ : OA1B - port map(A => \maddress[2]\, B => result_1, C => - trap_0_sqmuxa_3_1, Y => trap_0_sqmuxa_3); - - un6_ex_add_res_d1_ADD_33x33_fast_I316_Y_0 : XNOR2 - port map(A => N776_1, B => ADD_33x33_fast_I316_Y_0_0, Y => - \un6_ex_add_res_s1_i[26]\); - - \r.x.npc[0]\ : DFN1E0 - port map(D => \npc_1[0]\, CLK => lclk_c, E => holdn, Q => - \npc[0]\); - - \r.m.y[3]\ : DFN1E0 - port map(D => \y_0[3]\, CLK => lclk_c, E => holdn, Q => - \y_1[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I8_G0N : OA1 - port map(A => \op1[7]\, B => ldbp1_2, C => \data_0_2[7]\, Y - => N418); - - \r.e.op1_RNO[0]\ : MX2 - port map(A => \d[0]\, B => \d[1]\, S => N_227_0, Y => - \aop1[0]\); - - \r.e.ctrl.pc_RNIO2OI4[27]\ : NOR3C - port map(A => \ex_op2_m[27]\, B => aluresult_8_sqmuxa_i, C - => \aluresult_0_iv_1[27]\, Y => \aluresult_0_iv_2[27]\); - - \r.m.y_RNO[28]\ : AO1C - port map(A => y14_0, B => \logicout[28]\, C => \y_iv_2[28]\, - Y => \y_1[28]\); - - \r.e.shleft_RNIA99D2\ : MX2B - port map(A => \shiftin_5[38]\, B => \shiftin_5[22]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[22]\); - - \r.x.data_0_RNIDF9E[17]\ : XOR2 - port map(A => \data_0[17]\, B => invop2_0, Y => N_4264); - - un6_ex_add_res_d0_ADD_33x33_fast_I7_P0N : OR2A - port map(A => \data_0[6]\, B => \un1_iu0_6[6]\, Y => N416_0); - - \comb.v.x.data_0_1_1_iv[19]\ : OR2 - port map(A => \data_0_1_2[17]\, B => \data_0_1_1_iv_1[19]\, - Y => \data_0_1[19]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I68_Y : AND2 - port map(A => N434, B => N437, Y => N527); - - \r.e.ctrl.annul_RNIMA264\ : AOI1 - port map(A => jump_1_sqmuxa_1_i_0, B => jump_0_sqmuxa_1_i_0, - C => annul, Y => jump_0); - - \r.w.result_RNIVCHF[5]\ : AOI1B - port map(A => \un1_p0_6[357]\, B => d14, C => N_403, Y => - \d_iv_0_0[5]\); - - \r.d.inst_0_RNI4023_2[20]\ : NOR2A - port map(A => \inst_0[19]\, B => \inst_0[20]\, Y => N_152); - - \r.d.inst_0_RNO[2]\ : NOR2B - port map(A => rst, B => N_4602, Y => \inst_0_RNO[2]\); - - \r.x.y[30]\ : DFN1E0 - port map(D => \y[30]\, CLK => lclk_c, E => holdn, Q => - \y_2[30]\); - - \r.a.rsel2_RNO[1]\ : NOR3 - port map(A => N_3950, B => N_3946_1, C => un1_de_ren1_2, Y - => N_3946); - - \r.m.y_RNO[15]\ : AO1C - port map(A => y14_0, B => \logicout[15]\, C => \y_iv_2[15]\, - Y => \y_0[15]\); - - \r.e.shleft_0_RNI0KCN2\ : MX2B - port map(A => \shiftin_5[35]\, B => \shiftin_5[19]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[19]\); - - \r.e.ldbp2_RNIA1PAC1\ : OR2A - port map(A => \eaddress[13]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I124_un1_Y\ : OA1 - port map(A => N379, B => N_44, C => N486, Y => I124_un1_Y); - - \r.e.op2_RNO_2[27]\ : NOR3C - port map(A => \d_1_iv_1[27]\, B => \d_1_iv_0[27]\, C => - \rfo_m_i[59]\, Y => \d_1_iv_3[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I67_Y\ : OA1 - port map(A => \dpc[12]\, B => \inst_0[10]\, C => N386, Y - => N484_1); - - \r.w.result[19]\ : DFN1E0 - port map(D => \wdata[19]\, CLK => lclk_c, E => holdn, Q => - \result[19]\); - - \r.e.op1_RNIB33185[0]\ : NOR3 - port map(A => \un1_iu0_6[1]\, B => \un1_iu0_6[0]\, C => - \icc_2[1]\, Y => \icc_8_1[1]\); - - \r.d.annul_RNIVI35T\ : XNOR2 - port map(A => ldlock, B => branch_0, Y => annul_RNIVI35T); - - \comb.branch_address.tmp_ADD_30x30_fast_I93_Y\ : NOR2A - port map(A => N454, B => N_11, Y => N513); - - \r.m.result_RNIUC5D3[26]\ : NOR3C - port map(A => \d_iv_0[26]\, B => \result_m_0[26]\, C => - \rfo_m[26]\, Y => \d_iv_2[26]\); - - \r.e.aluop_1_RNICGR61_1[1]\ : NOR3B - port map(A => miscout69, B => logicout20, C => - aluresult_9_sqmuxa_1, Y => aluresult_10_sqmuxa_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_a3_1 : OR2B - port map(A => ADD_33x33_fast_I206_Y_0_a3_1_0_0, B => N401_1, - Y => N_57_i_0); - - \r.x.ctrl.tt_RNIL6SJ[0]\ : OR3C - port map(A => tt_1, B => tt_0, C => tt_2, Y => tt_i); - - \r.m.icc_RNIUN961[2]\ : OR2A - port map(A => \icc_0[2]\, B => aluresult_11_sqmuxa, Y => - \icc_m[2]\); - - \r.f.pc_RNO_0[24]\ : OR3A - port map(A => \tmp[24]\, B => un2_rstn_5_2, C => - \un2_rstn_5_0_0\, Y => \tmp_m[24]\); - - \r.w.result_RNIVPSI[3]\ : AOI1B - port map(A => \un1_p0_6[355]\, B => d14, C => - \result_m_0_0[3]\, Y => \d_iv_0[3]\); - - \r.m.ctrl.rd_RNIDE501[0]\ : XA1A - port map(A => \rd_1[0]\, B => \inst_0_RNI0FUM[0]\, C => - wreg_4, Y => wreg_0_0); - - \r.d.inst_0[17]\ : DFN1 - port map(D => \inst_0_RNO[17]\, CLK => lclk_c, Q => - \inst_0[17]\); - - \r.m.y_RNILEVOG[11]\ : NOR3C - port map(A => \bpdata_m_2[3]\, B => \aluresult_1_iv_3[11]\, - C => \aluresult_1_iv_4[11]\, Y => \aluresult_1_iv_6[11]\); - - \r.a.ctrl.inst_RNIPC231[19]\ : OR3 - port map(A => \inst_1[24]\, B => \inst_2[19]\, C => N_204, - Y => N_476); - - \r.m.y_RNIA4K91[4]\ : OR2B - port map(A => \y[4]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[4]\); - - \r.a.su_RNID9KK42\ : OR2B - port map(A => privileged_inst_5, B => illegal_inst_7_i_0, Y - => N_4033_i); - - \r.x.ctrl.pc_RNIDKI61[26]\ : MX2C - port map(A => \un1_p0_6[378]\, B => \pc_2[26]\, S => - s_3_sqmuxa, Y => N_3417); - - \r.e.ldbp2_1_RNI6MA7F4\ : OR2A - port map(A => \eaddress[26]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[27]\); - - \comb.v.f.pc_1_iv_RNO_1[3]\ : NOR3B - port map(A => \pc_4_m[3]\, B => \xc_trap_address_m[3]\, C - => \un6_ex_add_res_m_1[4]\, Y => \pc_1_iv_1[3]\); - - \r.e.aluop_0_RNIB57K2[0]\ : OR2A - port map(A => \logicout[0]\, B => y14, Y => N_463); - - \r.e.op2_RNO[22]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[22]\, Y => N_306); - - \r.x.result_RNIUPEGK[2]\ : NOR2A - port map(A => rst, B => N_3872, Y => \cwp_1_0[2]\); - - \r.w.s.y_RNO_1[29]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y_0[29]\, Y => N_412); - - \r.e.shleft_1_RNIJ9G13\ : MX2 - port map(A => \shiftin_5[49]\, B => \shiftin_5[33]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[33]\); - - \r.x.data_0_RNO[4]\ : AO1B - port map(A => N_3456, B => data_0_0_4, C => - \data_0_1_1_iv_2[4]\, Y => \data_0_1[4]\); - - \r.e.jmpl_RNIDV0T56\ : OR2B - port map(A => \aluresult_1_iv_9[23]\, B => - \un6_ex_add_res_m[24]\, Y => \aluresult[23]\); - - \r.e.ldbp2_1_RNIHAVEJ2\ : OR2A - port map(A => \eaddress[17]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[18]\); - - \r.m.result_RNI2DB4[5]\ : OR2B - port map(A => d13, B => \maddress[5]\, Y => N_406); - - \r.e.jmpl_RNISR9OQ\ : OR2B - port map(A => \shiftin_17[19]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[19]\); - - \r.x.y[21]\ : DFN1E0 - port map(D => \y[21]\, CLK => lclk_c, E => holdn, Q => - \y_1[21]\); - - \r.m.result[19]\ : DFN1E0 - port map(D => \eres2[19]\, CLK => lclk_c, E => holdn, Q => - \maddress[19]\); - - \r.e.op1_RNI8D6I1[8]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[8]\, Y => - \ex_op1_i_m[8]\); - - \r.w.s.tt[5]\ : DFN1E0 - port map(D => \xc_vectt_1[5]\, CLK => lclk_c, E => N_6747, - Q => \tt[5]\); - - \r.e.op2[7]\ : DFN1E0 - port map(D => N_291, CLK => lclk_c, E => holdn, Q => - \op2[7]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I264_un1_Y : NAND2 - port map(A => N811_0, B => ADD_33x33_fast_I264_un1_Y_0_0, Y - => I264_un1_Y_0); - - \r.x.data_0_RNILVG8[23]\ : XOR2 - port map(A => \data_0[23]\, B => invop2, Y => N_4270); - - \r.x.ctrl.pc[7]\ : DFN1E0 - port map(D => \pc_2[7]\, CLK => lclk_c, E => holdn, Q => - \pc[7]\); - - \r.m.y_RNI4RC92[14]\ : NOR2B - port map(A => \y_m_1[14]\, B => \cpi_m[159]\, Y => - \aluresult_1_iv_2[14]\); - - \r.m.result_RNIV9753[13]\ : NOR3C - port map(A => \d_iv_0[13]\, B => \result_m_0[13]\, C => - \rfo_m[13]\, Y => \d_iv_2[13]\); - - \r.e.ctrl.inst_RNIQTV42[22]\ : OR3B - port map(A => aluresult_11_sqmuxa_6, B => jump_1_sqmuxa_1_1, - C => jump_0_sqmuxa, Y => jump_1_sqmuxa_1_i_0); - - un6_fe_npc_I_186 : XOR2 - port map(A => N_21, B => \fe_pc[28]\, Y => I_186); - - un6_ex_add_res_d2_ADD_33x33_fast_I158_Y : NOR3B - port map(A => N495_0, B => N569_1, C => N_50_1, Y => N627); - - \r.x.result_RNIV2I75[2]\ : OR2B - port map(A => \bpdata[2]\, B => N_3957_1, Y => - \bpdata_m_1[2]\); - - \r.e.ldbp2_RNIBAJGP1\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[5]\, Y => - \un6_ex_add_res_m_1[6]\); - - \r.m.result_RNITOA4[0]\ : OR2B - port map(A => d13, B => \maddress[0]\, Y => \result_m_0[0]\); - - \r.e.aluop_RNI8OH84[0]\ : OR2B - port map(A => \logicout[1]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[1]\); - - \r.e.aluop_1_RNIV8ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[31]\, B => \aluop_1[1]\, C => - \un1_iu0_5[97]\, Y => N_6916); - - \r.x.data_0_RNO_3[3]\ : AO1B - port map(A => rdatav_0_1_0_iv_5_1, B => mcdo_m_0_17, C => - N_3455, Y => \dco_m_i[115]\); - - \r.x.npc_0_RNIPME41[0]\ : MX2C - port map(A => N_3213, B => N_3243, S => \npc_0[0]\, Y => - \xc_result[2]\); - - \r.f.pc_RNIII9LP1[5]\ : OA1A - port map(A => \fpc[5]\, B => rst, C => - \un6_ex_add_res_m_1[6]\, Y => \npc_iv_1[5]\); - - \r.a.ctrl.inst_RNIA01E_0[22]\ : OR2 - port map(A => \inst_1[24]\, B => \inst[22]\, Y => inst_9_3); - - \r.m.y_RNO[23]\ : OR3C - port map(A => \y_iv_1[23]\, B => \y_iv_0[23]\, C => - \y_RNO_2[23]\, Y => \y_1[23]\); - - \r.f.pc_RNO_4[13]\ : MX2 - port map(A => I_66, B => N_4056, S => bpmiss_1_i_0_0, Y => - \pc_4[13]\); - - \r.x.result[9]\ : DFN1E0 - port map(D => \maddress[9]\, CLK => lclk_c, E => holdn, Q - => \result_0[9]\); - - \r.m.icc_RNO[2]\ : MX2C - port map(A => N_4187, B => N_4177, S => wicc_2, Y => - \icco[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I183_Y\ : OR2A - port map(A => I183_un1_Y_i, B => N550, Y => N610); - - un6_ex_add_res_d0_ADD_33x33_fast_I263_un1_Y : OR3C - port map(A => N649_0, B => N633, C => N808_1, Y => - I263_un1_Y); - - \r.e.ldbp2_RNI85BQ7\ : OR2A - port map(A => \eaddress[4]\, B => aluresult_0_sqmuxa, Y => - \un6_ex_add_res_m[5]\); - - \r.m.irqen2\ : DFN1E0 - port map(D => irqen, CLK => lclk_c, E => holdn, Q => irqen2); - - un2_rstn_5_0_0_RNIPEBG8 : NAND2 - port map(A => \tmp[10]\, B => un2_rstn_5_0, Y => - \tmp_m[10]\); - - \r.m.y_RNO_1[16]\ : AOI1B - port map(A => \y[16]\, B => y08, C => \y_m_1[17]\, Y => - \y_iv_0[16]\); - - \r.a.ctrl.inst_RNIKU8G3[22]\ : AOI1B - port map(A => \inst[22]\, B => N_263, C => - illegal_inst_7_iv_2_0_a5_4_2, Y => illegal_inst_7_iv_6_tz); - - \comb.branch_address.tmp_ADD_30x30_fast_I277_Y_0_0\ : XOR2 - port map(A => \dpc[19]\, B => \inst_0[17]\, Y => - ADD_30x30_fast_I277_Y_0_0); - - \r.e.op2_RNII0OB1[19]\ : OR2A - port map(A => \un1_iu0_5[85]\, B => \op1_RNID1VH[19]\, Y - => \logicout_4[19]\); - - \r.a.imm_RNO[16]\ : MX2 - port map(A => \inst_0[6]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[134]\); - - \r.m.ctrl.pc[17]\ : DFN1E0 - port map(D => \pc_0[17]\, CLK => lclk_c, E => holdn, Q => - \pc_3[17]\); - - \r.e.shcnt_RNIIJ6E6[3]\ : MX2 - port map(A => \shiftin_8[38]\, B => \shiftin_8[30]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[30]\); - - \r.m.y_RNO[27]\ : OR3C - port map(A => \y_iv_0_1[27]\, B => \y_iv_0_0[27]\, C => - N_420, Y => \y_1[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I140_un1_Y\ : OR2B - port map(A => N514, B => N507, Y => I140_un1_Y_i); - - un6_fe_npc_I_146 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \fe_pc[23]\, C => - \fe_pc[24]\, Y => \DWACT_FINC_E[33]\); - - \r.x.npc_RNI4S8R[0]\ : MX2C - port map(A => N_3227, B => N_3257, S => \npc[0]\, Y => - \xc_result[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I222_Y\ : AO1 - port map(A => N605, B => N501_0, C => N604, Y => N738); - - un6_ex_add_res_d0_ADD_33x33_fast_I2_P0N : OR2A - port map(A => \data_0[1]\, B => \un1_iu0_6[1]\, Y => N401); - - \r.a.ctrl.wicc_RNO_3\ : NOR3A - port map(A => \inst_0_0[24]\, B => \inst_0_0[22]\, C => - \un1_p0_6_0[60]\, Y => wicc_1_0_a3_1_1_0); - - \r.e.op1_RNIPU8G[23]\ : OR2B - port map(A => \op1[23]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I272_Y : OR3A - port map(A => N650, B => I272_un1_Y_0, C => I237_un1_Y_0, Y - => N790_0); - - \r.x.data_0_RNO_1[9]\ : AO1A - port map(A => rdata_5_sqmuxa, B => data_0_0_25, C => - \data_0_m[9]\, Y => \data_0_1_0_iv_0[9]\); - - \r.e.shleft_1_RNIEL5I1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[25]\, S => - shleft_1, Y => \shiftin_5[56]\); - - \r.e.aluop_2_RNI4TAS1[1]\ : MX2C - port map(A => N_3529, B => \logicout_3[2]\, S => - \aluop_2[1]\, Y => N_3561); - - \r.e.op2_RNO[15]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[15]\, Y => N_299); - - \r.d.inst_0_RNO[19]\ : NOR2B - port map(A => rst, B => N_4619, Y => \inst_0_RNO[19]\); - - \r.x.rstate_0_RNI4HKE2[0]\ : MX2C - port map(A => N_3406, B => \xc_result[15]\, S => - \rstate_0[0]\, Y => \wdata[15]\); - - \r.m.icc[1]\ : DFN1E0 - port map(D => \icco[1]\, CLK => lclk_c, E => holdn, Q => - \icc[1]\); - - \r.x.result[21]\ : DFN1E0 - port map(D => \maddress[21]\, CLK => lclk_c, E => holdn, Q - => \result_0[21]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I123_Y : OAI1 - port map(A => N521_0, B => N524_1, C => N520_2, Y => N586_0); - - \r.e.op2_RNO_2[14]\ : NOR3C - port map(A => \d_1_iv_1[14]\, B => \d_1_iv_0[14]\, C => - \rfo_m_i[46]\, Y => \d_1_iv_3[14]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I121_Y : AO1 - port map(A => N522_0, B => N519_0, C => - ADD_33x33_fast_I121_Y_0_0, Y => N584); - - \comb.branch_address.tmp_ADD_30x30_fast_I111_Y\ : NOR2B - port map(A => N476_0, B => N472, Y => N531); - - \r.x.rstate_RNIPCH12[0]\ : MX2C - port map(A => N_3419, B => \xc_result[28]\, S => - \rstate[0]\, Y => \wdata[28]\); - - \r.e.op2_RNO_4[21]\ : AOI1B - port map(A => \result[21]\, B => d31_0, C => \imm_m_i[21]\, - Y => \d_1_iv_0[21]\); - - \r.f.pc_RNI7BPRFE[9]\ : OR3C - port map(A => \npc_iv_1[9]\, B => \npc_iv_0[9]\, C => - \npc_iv_2[9]\, Y => rpc_7); - - \r.m.y_RNI80LA2[7]\ : AOI1B - port map(A => \y[7]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[152]\, Y => \aluresult_1_iv_2[7]\); - - \r.e.op2_RNO_9[24]\ : OR3B - port map(A => d29_0, B => \imm[24]\, C => \rsel2[0]\, Y => - \imm_m_i[24]\); - - \r.x.y[15]\ : DFN1E0 - port map(D => \y[15]\, CLK => lclk_c, E => holdn, Q => - \y_1[15]\); - - \r.e.op2[11]\ : DFN1E0 - port map(D => N_295, CLK => lclk_c, E => holdn, Q => - \op2[11]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I235_un1_Y : OR2B - port map(A => N664_1, B => N649_1, Y => I235_un1_Y_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I49_Y : MAJ3 - port map(A => \data_0_0[22]\, B => \un1_iu0_6[22]\, C => - N460_2, Y => N508_0); - - \r.w.s.y_RNO_2[14]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[14]\, Y - => N_384); - - \r.e.ldbp2_RNI6LB1B\ : MX2C - port map(A => \un6_ex_add_res_s1_i[6]\, B => N_6645, S => - ldbp2_3, Y => \eaddress[5]\); - - \r.x.rstate_RNIR4LS1[0]\ : MX2C - port map(A => N_3421, B => \xc_result[30]\, S => - \rstate[0]\, Y => \wdata[30]\); - - \r.e.op1_RNI6HFC[2]\ : OR2B - port map(A => \op1[2]\, B => un14_casaen_s1_0, Y => - \op1_m_0[2]\); - - \r.e.op2_RNIQCAP_0[5]\ : OR2 - port map(A => \un1_iu0_6[5]\, B => \un1_iu0_5[71]\, Y => - \logicout_3[5]\); - - \r.e.aluop_0_RNI13R31[1]\ : MX2C - port map(A => \logicout_4[0]\, B => N_6865, S => N_6866_i_0, - Y => N_3623); - - \comb.v.f.pc_1_iv_RNO[3]\ : NAND2 - port map(A => un2_rstn_4_0_0, B => I_5, Y => - \un6_fe_npc_m[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I127_Y : AO1 - port map(A => N528_1, B => N525, C => N524, Y => N590_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I53_Y : MAJ3 - port map(A => \op2[20]\, B => \un1_iu0_6[20]\, C => N454_2, - Y => N512_0); - - \r.m.icc_RNO_16[2]\ : NOR3C - port map(A => icc_0_sqmuxa_1_8, B => icc_0_sqmuxa_1_7, C - => icc_0_sqmuxa_1_19, Y => icc_0_sqmuxa_1_26); - - \r.f.pc_RNO_1[27]\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[27]\, Y => - \un6_ex_add_res_m_1[28]\); - - \r.a.cwp[1]\ : DFN1E0 - port map(D => \cwp[1]\, CLK => lclk_c, E => holdn, Q => - \cwp_3[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I269_un1_Y_0 : NOR3A - port map(A => N645_0, B => N595, C => N603_i, Y => - ADD_33x33_fast_I269_un1_Y_0); - - \r.e.aluop_RNI79OO6[1]\ : AOI1B - port map(A => edata_2_sqmuxa, B => \bpdata[25]\, C => - \edata2_iv_0[25]\, Y => \edata2_iv_1[25]\); - - \r.d.pc_RNIO3BA4[3]\ : MX2 - port map(A => \dpc[3]\, B => \fpc[3]\, S => ra_bpmiss_1, Y - => N_3880); - - \r.a.rsel2_0_RNII0B2T1[0]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[1]\, Y - => \aluresult_m_i[1]\); - - \r.a.ctrl.rd[3]\ : DFN1E0 - port map(D => N_17, CLK => lclk_c, E => holdn, Q => - \rd_1[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I113_Y : NOR3 - port map(A => I51_un1_Y, B => N460, C => I113_un1_Y, Y => - N576); - - un6_ex_add_res_d1_ADD_33x33_fast_I298_Y_0 : XOR3 - port map(A => \un1_iu0_6[7]\, B => \op2[7]\, C => N672_0, Y - => \un6_ex_add_res_s1[8]\); - - \r.x.ctrl.pc[2]\ : DFN1E0 - port map(D => \pc_3[2]\, CLK => lclk_c, E => holdn, Q => - \pc_0[2]\); - - \r.e.invop2_RNI1CH9Q1\ : MX2C - port map(A => \un6_ex_add_res_s2[20]\, B => - \un6_ex_add_res_s0[20]\, S => invop2, Y => N_6654); - - \r.d.cnt_RNITPRI[1]\ : OR3C - port map(A => N_142, B => wy_1_0_a3_1_0, C => - de_inst_0_sqmuxa_0, Y => de_inst_0_sqmuxa_i_0); - - \r.m.y_RNO_4[31]\ : OR2B - port map(A => mulstep_1, B => ex_ymsb_1, Y => ex_ymsb_1_m); - - \r.x.y[8]\ : DFN1E0 - port map(D => \y[8]\, CLK => lclk_c, E => holdn, Q => - \y_2[8]\); - - \r.e.op1_RNI49UH[22]\ : MX2 - port map(A => \op1[22]\, B => \data_0_0[22]\, S => ldbp1_3, - Y => \un1_iu0_6[22]\); - - \r.e.shcnt_RNINC346[3]\ : MX2 - port map(A => \shiftin_8[33]\, B => \shiftin_8[25]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I237_un1_Y : OR2B - port map(A => N666_0, B => N651, Y => I237_un1_Y_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I319_Y_0 : AX1C - port map(A => N_51_i_0, B => ADD_33x33_fast_I262_Y_0_0_0, C - => \un6_ex_add_res_s2_1[29]\, Y => - \un6_ex_add_res_s0[29]\); - - \r.d.pc_RNO[5]\ : MX2 - port map(A => \fpc[5]\, B => \dpc[5]\, S => N_6763_i_0, Y - => \pc_RNO[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I9_G0N : OA1 - port map(A => \op1[8]\, B => ldbp1_1, C => \data_0[8]\, Y - => N421_1); - - \r.e.op1_RNIDHFC[9]\ : OR2B - port map(A => \op1[9]\, B => un14_casaen_s1_0, Y => - \op1_m_0[9]\); - - \r.a.ctrl.inst_RNIO55K2[31]\ : OA1A - port map(A => cp_disabled_2_sqmuxa_0, B => N_216, C => - cp_disabled_8_sqmuxa_1, Y => cp_disabled_4_0_1_0); - - \r.e.shleft_0_RNI17BG\ : OR2A - port map(A => \un1_iu0_6[2]\, B => shleft_0, Y => - \shiftin_5[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I45_Y : MAJ3 - port map(A => \data_0[24]\, B => \un1_iu0_6[24]\, C => - N466_0, Y => N504_0); - - \r.d.inst_0_RNICEJ4[28]\ : OR2A - port map(A => N_85, B => \inst_0[28]\, Y => N_17); - - \r.f.pc_RNO_4[23]\ : MX2 - port map(A => I_136, B => N_4066, S => bpmiss_1_i_0, Y => - \pc_4[23]\); - - \r.e.aluop_2_RNI3BEI2[1]\ : MX2C - port map(A => N_3555, B => \logicout_3[28]\, S => - \aluop_2[1]\, Y => N_3587); - - \comb.branch_address.tmp_ADD_30x30_fast_I94_Y\ : AO1 - port map(A => N459, B => N456, C => N455, Y => N514); - - \r.d.inst_0_RNIE0IP1[25]\ : OR2 - port map(A => \inst_0_RNIFKEG[25]\, B => branch_1, Y => - N_108); - - \r.e.op1_RNIRA9G[16]\ : OR2B - port map(A => \op1[16]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[16]\); - - \r.a.rsel1_0_RNITC8M2[2]\ : OR3 - port map(A => d11_0_a5_0, B => \rsel1_0[2]\, C => data1(5), - Y => \rsel1_0_RNITC8M2[2]\); - - \r.x.ctrl.pc_RNIHMA71[29]\ : MX2C - port map(A => \un1_p0_6[381]\, B => \pc_2[29]\, S => - s_3_sqmuxa, Y => N_3420); - - \r.x.data_0_RNO_1[4]\ : AND2 - port map(A => \dco_m_i[108]\, B => \data_0_m_i[4]\, Y => - \data_0_1_1_iv_0[4]\); - - \r.a.imm[21]\ : DFN1E0 - port map(D => \un3_de_ren1[139]\, CLK => lclk_c, E => holdn, - Q => \imm[21]\); - - \r.e.op2[3]\ : DFN1E0 - port map(D => N_287, CLK => lclk_c, E => holdn, Q => - \op2[3]\); - - \r.w.s.wim_RNIMSJV2[7]\ : NOR2B - port map(A => aluresult_8_sqmuxa_i, B => \wim_m[7]\, Y => - \aluresult_1_iv_0[7]\); - - \r.e.aluop_2_RNILH4R2[1]\ : MX2C - port map(A => N_3549, B => \logicout_3[22]\, S => - \aluop_2[1]\, Y => N_3581); - - \r.d.inst_0_RNIQCIO[31]\ : OR2A - port map(A => imm9, B => un1_inst, Y => N_127); - - \comb.branch_address.tmp_ADD_30x30_fast_I160_Y\ : NOR2A - port map(A => I160_un1_Y_i, B => N526, Y => N586_i); - - \r.e.shcnt_RNIAARK6[3]\ : MX2A - port map(A => \shiftin_8[40]\, B => \shiftin_8[32]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[32]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I74_un1_Y\ : NAND2 - port map(A => N373, B => N377, Y => I74_un1_Y_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I151_Y : OR2 - port map(A => N548_0, B => I151_un1_Y, Y => N614_2); - - \r.a.ctrl.rd[7]\ : DFN1E0 - port map(D => un3_reg, CLK => lclk_c, E => holdn, Q => - \rd[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I320_Y_0 : XNOR2 - port map(A => N768_0, B => \un6_ex_add_res_s2_1[30]\, Y => - \un6_ex_add_res_s0[30]\); - - \r.m.ctrl.ld_RNIHU879\ : OR2 - port map(A => ld, B => dco_i_2(132), Y => ld_3); - - \r.e.jmpl_RNITR4DO\ : OR2B - port map(A => \shiftin_17[13]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[13]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I6_G0N\ : OR2B - port map(A => \inst_0[6]\, B => \dpc[8]\, Y => N376_i); - - \r.e.ctrl.pc_RNI71K11[21]\ : OR2B - port map(A => \pc_0[21]\, B => jmpl_0, Y => \cpi_m[166]\); - - \r.a.rsel1_0_RNIA7LJ2[2]\ : OR2B - port map(A => data1(20), B => d11, Y => \rfo_m[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I131_Y : AO1B - port map(A => N532_1, B => N529_2, C => N528_2, Y => N594_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I242_un1_Y_0\ : NOR3B - port map(A => N551, B => N587, C => N543, Y => - ADD_30x30_fast_I242_un1_Y_0); - - \r.x.data_0[10]\ : DFN1E0 - port map(D => \data_0_1[10]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[10]\); - - \un1_r.w.s.cwp_1_SUM2_0_0\ : XOR2 - port map(A => \cwp[2]\, B => et_RNI1BRF2, Y => SUM2_0_0); - - \r.x.ctrl.inst_RNITM3O1[19]\ : OR2B - port map(A => y_0_sqmuxa_1_1, B => y_0_sqmuxa_1_2, Y => - y_0_sqmuxa_1); - - \r.e.jmpl_RNITN6O_0\ : NOR3A - port map(A => \ex_shcnt_1[0]\, B => jmpl, C => - aluresult_1_sqmuxa_0_0, Y => aluresult_2_sqmuxa_0); - - \r.a.ctrl.inst_RNIM82S[21]\ : OA1C - port map(A => \inst_2[21]\, B => \inst_2[19]\, C => N_518, - Y => N_334); - - \r.x.ctrl.inst_RNI50723[30]\ : OA1 - port map(A => y6, B => y11, C => y15, Y => y6_2); - - \r.m.result_RNO[29]\ : MX2 - port map(A => \aluresult[29]\, B => \op1[29]\, S => - un17_casaen_0_2, Y => \eres2[29]\); - - \r.e.op1[24]\ : DFN1E0 - port map(D => \aop1[24]\, CLK => lclk_c, E => holdn, Q => - \op1[24]\); - - \r.a.ctrl.inst_RNIBO0L[22]\ : NOR2 - port map(A => \inst[22]\, B => N_201, Y => N_351_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I137_Y_0 : MIN3 - port map(A => \op2[9]\, B => \un1_iu0_6[9]\, C => N421_0, Y - => ADD_33x33_fast_I137_Y_0_0); - - \r.d.pv_RNIH9E08\ : OR2A - port map(A => un2_exbpmiss_0, B => ra_bpannul_1, Y => - un25_exbpmiss); - - \r.e.op2_RNO[12]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[12]\, Y => N_296); - - \r.d.inst_0_RNI7EVG1[30]\ : AOI1B - port map(A => de_fins_hold_1_2, B => N_3832, C => - un5_ldlock, Y => ldlock_2_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I119_Y : AO1 - port map(A => N520_1, B => N517_0, C => N516_0, Y => N582); - - \r.e.shcnt_RNIHQ03B[2]\ : MX2C - port map(A => \shiftin_11[15]\, B => \shiftin_11[11]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[11]\); - - \r.d.annul_RNI0N4LO3\ : OR2B - port map(A => I_20, B => annul_RNIVCQHS1, Y => N_6618); - - un6_ex_add_res_d2_ADD_33x33_fast_I203_Y : OR2 - port map(A => N606_2, B => I203_un1_Y_0, Y => N672); - - \r.f.pc_RNO_3[25]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[25]\, C => - \xc_trap_address_m[25]\, Y => \pc_1_iv_0[25]\); - - \r.e.aluop_RNII15D6[0]\ : OR2A - port map(A => aluresult_3_sqmuxa, B => \logicout[23]\, Y - => \aluop_RNII15D6[0]\); - - \comb.un6_xc_exception_RNI9HMBS5\ : OR3C - port map(A => \xc_trap_address_m[2]\, B => - \un6_fe_npc_m[0]\, C => \npc_iv_3[2]\, Y => rpc_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I52_Y : OA1A - port map(A => \data_0_2[20]\, B => \un1_iu0_6[20]\, C => - N461, Y => N511_0); - - \r.f.pc_RNO_5[27]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[27]\, Y => \xc_trap_address_m[27]\); - - \r.w.result[7]\ : DFN1E0 - port map(D => \wdata[7]\, CLK => lclk_c, E => holdn, Q => - \result[7]\); - - \r.m.y_RNO_1[8]\ : AOI1B - port map(A => \y[8]\, B => y08, C => \y_m_2[9]\, Y => - \y_iv_0[8]\); - - \r.d.cnt_RNO_0[1]\ : OR2 - port map(A => cnt_3_sqmuxa_0, B => annul_4, Y => - cnt_3_sqmuxa); - - \r.x.data_0_RNO_2[14]\ : NOR2A - port map(A => \data_0[14]\, B => ld_3, Y => \data_0_m[14]\); - - \r.d.annul\ : DFN1E0 - port map(D => annul_4, CLK => lclk_c, E => holdn, Q => - annul_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_un1_Y_0 : NOR2A - port map(A => N627, B => N643, Y => - ADD_33x33_fast_I260_un1_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I196_Y : NOR2 - port map(A => N607_1, B => N599_0, Y => N665_0); - - \r.d.inull_RNIIH9QT_0\ : OR2 - port map(A => \de_hold_pc_1\, B => holdn, Y => N_6763_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I259_Y_1 : NOR3C - port map(A => I33_un1_Y, B => N487_0, C => I95_un1_Y_0, Y - => ADD_33x33_fast_I259_Y_1_0); - - \r.d.pc_RNIMRAA4[2]\ : MX2 - port map(A => \dpc[2]\, B => \fpc[2]\, S => \ra_bpmiss_1_0\, - Y => N_3879); - - \r.x.data_0_RNO[2]\ : OR3C - port map(A => \dco_m_i[114]\, B => \data_0_1_1_iv_1[2]\, C - => \dco_m_i[98]\, Y => \data_0_1[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I149_Y\ : NOR2B - port map(A => N523, B => N515, Y => N575); - - \r.e.op2_RNO_0[22]\ : OR3C - port map(A => \op1_m_i[22]\, B => \d_1_iv_3[22]\, C => - \aluresult_m_i[22]\, Y => \d_1[22]\); - - \r.a.ctrl.inst_RNIJ02L[19]\ : OR2A - port map(A => \inst_2[19]\, B => N_518, Y => - \inst_RNIJ02L[19]\); - - \r.m.dci.asi_RNO[4]\ : NOR2B - port map(A => \inst_0[23]\, B => \inst_1[9]\, Y => \asi[4]\); - - \r.d.pc_RNO[15]\ : MX2 - port map(A => \fpc[15]\, B => \dpc[15]\, S => N_6763_i_0, Y - => \pc_RNO[15]\); - - \r.x.data_0_RNO_1[24]\ : OR2A - port map(A => \data_0[24]\, B => ld_3, Y => - \data_0_m_i[24]\); - - \r.e.shleft_1_RNI9JBG\ : NOR2A - port map(A => \un1_iu0_6[5]\, B => shleft_1, Y => - shleft_1_RNI9JBG); - - \comb.branch_address.tmp_ADD_30x30_fast_I72_Y_0_a3\ : NOR3C - port map(A => \dpc[8]\, B => \inst_0[6]\, C => N380, Y => - N_44); - - \r.a.ctrl.inst[14]\ : DFN1E0 - port map(D => \inst_0[14]\, CLK => lclk_c, E => holdn, Q - => \inst_1[14]\); - - \r.e.jmpl_RNI4QHFF2\ : OR3C - port map(A => \aluresult_1_iv_8[7]\, B => - \shiftin_17_m_0[7]\, C => ldbp2_0_RNIKEHUF, Y => - \aluresult[7]\); - - \r.a.wovf_RNIO7N5\ : OR2 - port map(A => wunf, B => wovf, Y => \tt_4[3]\); - - \r.e.op2[22]\ : DFN1E0 - port map(D => N_306, CLK => lclk_c, E => holdn, Q => - \op2[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I24_G0N : NOR2B - port map(A => \op2[23]\, B => \un1_iu0_6[23]\, Y => N466); - - \r.x.data_0_RNO_2[13]\ : NOR2A - port map(A => data_0_29, B => rdata_5_sqmuxa, Y => - \dco_m_0[125]\); - - \r.e.shleft_1_RNIABBQ1\ : MX2A - port map(A => \shiftin_5[20]\, B => shleft_1_RNI5FBG, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[4]\); - - \r.x.ctrl.rett_RNO\ : NOR2A - port map(A => rett, B => annul_5, Y => rett_1_1); - - \r.e.ldbp2_2_RNICBJHB3\ : OR2A - port map(A => \eaddress[21]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[22]\); - - \r.e.ldbp2_2_RNI7G0C6\ : OR2 - port map(A => aluresult_0_sqmuxa, B => \eaddress[3]\, Y => - ldbp2_2_RNI7G0C6); - - \r.x.data_0_RNO_1[23]\ : NOR2A - port map(A => \data_0[23]\, B => ld_0_0, Y => - \data_0_m[23]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I57_Y : AO13 - port map(A => N448, B => \un1_iu0_6[18]\, C => - \data_0_0[18]\, Y => N516); - - un6_fe_npc_I_111 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I271_Y_0 : AOI1 - port map(A => N664_0, B => N649_0, C => N648, Y => - ADD_33x33_fast_I271_Y_0_1); - - \r.e.ctrl.inst_RNIV42L[22]\ : NOR3C - port map(A => \inst_1[22]\, B => \inst_0[23]\, C => - \inst[19]\, Y => jump_1_sqmuxa_1_1); - - \r.a.ctrl.inst_RNI4P3H1[24]\ : MX2 - port map(A => illegal_inst35_4, B => \inst_1[24]\, S => - N_207, Y => N_263); - - \r.a.ctrl.inst_RNIB8549_0[30]\ : NOR3C - port map(A => N_451, B => \aop2_i_o2_2[0]\, C => N_452, Y - => N_6697_i_0_0); - - \r.e.op2_RNO_1[25]\ : OR2B - port map(A => \op1[25]\, B => un14_casaen_s1, Y => - \op1_m_i[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I261_Y_0\ : XOR2 - port map(A => N358, B => ADD_30x30_fast_I261_Y_0_0, Y => - \tmp[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I297_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[6]\, B => \data_0[6]\, Y => - \un6_ex_add_res_s2_1[7]\); - - \r.a.ctrl.inst[22]\ : DFN1E0 - port map(D => \inst_0_0[22]\, CLK => lclk_c, E => holdn, Q - => \inst[22]\); - - \r.x.rstate_0_RNID9182[0]\ : MX2C - port map(A => N_3400, B => \xc_result[9]\, S => - \rstate_0[0]\, Y => \wdata[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I263_Y : NAND2 - port map(A => I263_un1_Y, B => ADD_33x33_fast_I263_Y_1, Y - => N772); - - \r.x.rstate_0_RNIN5N82[0]\ : MX2C - port map(A => N_3393, B => \xc_result[2]\, S => - \rstate_0[0]\, Y => \wdata[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I145_Y : AO1 - port map(A => N546, B => N543_0, C => - ADD_33x33_fast_I145_Y_0_0, Y => N608); - - \r.w.s.y[25]\ : DFN1E0 - port map(D => N_3789, CLK => lclk_c, E => N_6922_i, Q => - \y[25]\); - - \r.x.data_0_RNO_2[7]\ : OR2B - port map(A => N_3456, B => data_0_7, Y => \dco_m_i[103]\); - - \r.f.pc_RNO_6[25]\ : MX2 - port map(A => \fpc[25]\, B => \eaddress[25]\, S => jump, Y - => N_4068); - - \r.e.ctrl.inst_RNILO0L[20]\ : OR2B - port map(A => \inst_1[20]\, B => N_3749_3, Y => N_3755); - - \r.m.result_0_RNIUK0I3[3]\ : NOR3C - port map(A => \d_iv_0[3]\, B => \result_m_0[3]\, C => - \rfo_m[3]\, Y => \d_iv_2[3]\); - - \r.e.op2_RNO_4[19]\ : OA1A - port map(A => \maddress[19]\, B => d27_0, C => - \cpi_m_i[371]\, Y => \d_1_iv_1[19]\); - - \r.e.shleft_0_RNIVOHP\ : OR2A - port map(A => \un1_iu0_6[23]\, B => shleft_0, Y => - \shiftin_5[23]\); - - \r.m.result_RNIUO4D3[19]\ : NOR3C - port map(A => \d_iv_0[19]\, B => \result_m_0[19]\, C => - \rfo_m[19]\, Y => \d_iv_2[19]\); - - \r.e.jmpl_RNIHHBJU\ : OR2B - port map(A => \shiftin_17[29]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[29]\); - - \r.e.invop2_0_RNIJ6B541\ : MX2C - port map(A => \un6_ex_add_res_s2[17]\, B => - \un6_ex_add_res_s0[17]\, S => invop2_0, Y => N_6563); - - \r.m.dci.size_RNO[1]\ : AO1C - port map(A => \inst[19]\, B => N_3755, C => \size_1[1]\, Y - => \size[1]\); - - \r.w.result[5]\ : DFN1E0 - port map(D => \wdata[5]\, CLK => lclk_c, E => holdn, Q => - \result[5]\); - - \r.e.op2_RNO_0[5]\ : OR3C - port map(A => \op1_m_i[5]\, B => \d_1_iv_3[5]\, C => - \aluresult_m_i[5]\, Y => \d_1[5]\); - - \r.e.ctrl.pc[18]\ : DFN1E0 - port map(D => \pc[18]\, CLK => lclk_c, E => holdn, Q => - \pc_0[18]\); - - \r.d.inst_0_RNIRPAV1[29]\ : NOR3A - port map(A => \rs1[4]\, B => \un3_de_ren1[92]\, C => - \rs1_iv_i_0[0]\, Y => rs1_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I17_P0N : OR3A - port map(A => \data_0[16]\, B => \op1[16]\, C => ldbp1_4, Y - => N446); - - \r.f.pc_RNO_0[22]\ : NAND2 - port map(A => \tmp[22]\, B => un2_rstn_5_0, Y => - \tmp_m[22]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I270_Y_0\ : XOR2 - port map(A => N738, B => ADD_30x30_fast_I270_Y_0_0, Y => - \tmp[12]\); - - \r.m.ctrl.rd_RNIM0A51[4]\ : XA1A - port map(A => \un3_de_ren1[95]\, B => \rd[4]\, C => wreg_4, - Y => wreg_1_0_0); - - \r.e.op2_RNO_8[23]\ : OR2A - port map(A => \maddress[23]\, B => d27, Y => - \result_m_i_0[23]\); - - \r.e.op1_RNO[20]\ : MX2C - port map(A => \d_i[20]\, B => \d_i[21]\, S => N_227_0, Y - => \aop1[20]\); - - \r.a.ctrl.inst[17]\ : DFN1E0 - port map(D => \inst_0[17]\, CLK => lclk_c, E => holdn, Q - => \inst_1[17]\); - - \r.e.op1_RNIC1UB[1]\ : OR2A - port map(A => un17_casaen_0_2, B => \op1[1]\, Y => - \op1_i_m[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I175_Y : NOR2 - port map(A => N578, B => I175_un1_Y, Y => N644_i); - - \r.f.pc_RNO_0[13]\ : NAND2 - port map(A => \tmp[13]\, B => \un2_rstn_5\, Y => - \tmp_m[13]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I2_G0N\ : OR2B - port map(A => \inst_0_RNI2NUM[2]\, B => \dpc[4]\, Y => N364); - - un6_ex_add_res_d2_ADD_33x33_fast_I54_Y : NOR2B - port map(A => N458_0, B => N455_1, Y => N513_2); - - \r.x.data_0_RNI3BS8[1]\ : XOR2 - port map(A => \data_0[1]\, B => invop2_1, Y => N_3305); - - \r.e.op2_RNO_3[17]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[17]\, Y => - \aluresult_m_i[17]\); - - \r.e.op2_RNO_2[11]\ : NOR3C - port map(A => \d_1_iv_1[11]\, B => \d_1_iv_0[11]\, C => - \rfo_m_i[43]\, Y => \d_1_iv_3[11]\); - - \r.a.rsel1_0_RNIF7LJ2[2]\ : OR2B - port map(A => data1(25), B => d11_0, Y => \rfo_m[25]\); - - \r.e.aluop_RNI30QD1[2]\ : XAI1 - port map(A => \un1_iu0_5[89]\, B => \aluop_1[2]\, C => - \un1_iu0_6[23]\, Y => N_3550); - - \r.d.pc[21]\ : DFN1 - port map(D => \pc_RNO[21]\, CLK => lclk_c, Q => \dpc[21]\); - - \r.x.result_RNIU4OE[29]\ : OR2B - port map(A => \un1_p0_6[381]\, B => d14, Y => - \cpi_m_0[381]\); - - \r.e.op2_RNO_6[22]\ : OR2B - port map(A => data2(22), B => d25, Y => \rfo_m_i[54]\); - - \r.w.s.wim_RNI3N5S3[1]\ : NOR2B - port map(A => \wim_m[1]\, B => \ex_op2_m[1]\, Y => - \aluresult_2_iv_0[1]\); - - \r.e.ctrl.inst_RNIM53A1[21]\ : NOR3A - port map(A => jump_0_sqmuxa_1_0, B => N_3749_1, C => - N_3749_2, Y => jump_0_sqmuxa_1_2); - - \r.a.ctrl.wicc_RNI0ERB\ : OR2 - port map(A => wicc_2, B => wicc_0, Y => not_valid); - - \r.e.shleft_0_RNI8THM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[22]\, S => - shleft_0, Y => \shiftin_5[53]\); - - \r.a.rsel1_RNIEECQ18[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[30]\, Y - => \aluresult_m_0[30]\); - - \r.x.ctrl.pc_RNITVH61[13]\ : MX2C - port map(A => \un1_p0_6[365]\, B => \pc_0[13]\, S => - s_3_sqmuxa, Y => N_3404); - - \r.a.ctrl.inst_RNIF8Q8[28]\ : XOR2 - port map(A => \inst_1[28]\, B => \icc[3]\, Y => branch_7); - - \r.e.op1_RNIK3C4[9]\ : MX2 - port map(A => \op1[9]\, B => \data_0[9]\, S => ldbp1, Y => - \un1_iu0_6[9]\); - - \r.d.pv_RNIJARPF\ : NOR2B - port map(A => un5_exbpmiss_i_0, B => un25_exbpmiss, Y => - un1_annul_next_1_sqmuxa_3_0); - - \r.d.inst_0_RNIKI1A[20]\ : OR3 - port map(A => N_67, B => un52_casaen, C => N_122_1, Y => - rd_0_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I112_Y : NOR2B - port map(A => N513_1, B => N509, Y => N575_1); - - \r.e.ctrl.pc_RNIESTN2[25]\ : AOI1 - port map(A => \pc[25]\, B => jmpl_0, C => \aluresult_6[31]\, - Y => \aluresult_1_iv_1[25]\); - - \r.a.rsel2_0_RNIFA4D_1[0]\ : NOR2A - port map(A => d26, B => un17_casaen_0_2, Y => - un14_casaen_s0); - - \r.d.pc[4]\ : DFN1 - port map(D => \pc_RNO[4]\, CLK => lclk_c, Q => \dpc[4]\); - - \r.e.op2_RNIO2OP[12]\ : MX2 - port map(A => \op2[12]\, B => N_4259, S => ldbp2_1, Y => - \un1_iu0_5[78]\); - - \r.a.imm_RNO[27]\ : MX2 - port map(A => \inst_0[17]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[145]\); - - \r.m.ctrl.cnt[0]\ : DFN1E0 - port map(D => \cnt[0]\, CLK => lclk_c, E => holdn, Q => - \cnt_0[0]\); - - \r.a.rsel1[1]\ : DFN1E0 - port map(D => N_4021, CLK => lclk_c, E => holdn, Q => - \rsel1[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I266_Y_0_a3_1 : AND2 - port map(A => N464_0, B => N467_0, Y => N_74_1); - - \r.m.result_RNI0TAI[31]\ : NOR3C - port map(A => \result_m_0[31]\, B => \cpi_m_0[383]\, C => - \result_m_0_0[31]\, Y => \d_iv_1[31]\); - - \r.a.rfa2[6]\ : DFN1E0 - port map(D => \un3_de_ren1[105]\, CLK => lclk_c, E => holdn, - Q => \rfa2[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I304_Y_0 : XNOR3 - port map(A => \data_0[13]\, B => \un1_iu0_6[13]\, C => N802, - Y => \un6_ex_add_res_s0[14]\); - - \r.x.data_0[25]\ : DFN1E0 - port map(D => \data_0_1[25]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[25]\); - - \r.e.op1_RNIMB1O6[27]\ : NOR3C - port map(A => \ex_op1_i_m[27]\, B => \op1_RNI4VNF[27]\, C - => \bpdata_i_m[27]\, Y => \edata2_iv_1[27]\); - - \r.e.op1[23]\ : DFN1E0 - port map(D => \aop1[23]\, CLK => lclk_c, E => holdn, Q => - \op1[23]\); - - \r.w.s.tba_RNI54CA1[4]\ : OR2B - port map(A => \tba[4]\, B => aluresult_12_sqmuxa, Y => - \tba_m[4]\); - - \r.e.jmpl_RNIUQG9G2\ : AOI1B - port map(A => \shiftin_17[23]\, B => aluresult_2_sqmuxa_0, - C => \aluresult_1_iv_8[23]\, Y => \aluresult_1_iv_9[23]\); - - \r.e.op1_RNIVU4RB[22]\ : NOR3 - port map(A => \edata2_0_iv_0[22]\, B => \ex_op1_i_m[22]\, C - => \bpdata_i_m_1[6]\, Y => edata2_0_iv(22)); - - \r.m.icc_RNI87QF4[0]\ : NOR3C - port map(A => \icc_m[0]\, B => \aluresult_1_iv_0[20]\, C - => \tba_m[8]\, Y => \aluresult_1_iv_4[20]\); - - \r.e.shleft_RNI4PSU\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[9]\, S => shleft, - Y => \shiftin_5[40]\); - - \r.d.inst_0_RNI66J4_0[23]\ : NOR3C - port map(A => \inst_0_0[23]\, B => \inst_0_0[24]\, C => - \inst_0_0[22]\, Y => N_142); - - \r.x.ctrl.pc[20]\ : DFN1E0 - port map(D => \pc_3[20]\, CLK => lclk_c, E => holdn, Q => - \pc_2[20]\); - - \r.d.inst_0_RNIA869[19]\ : OR2B - port map(A => icc_check8_1, B => N_3518_1, Y => icc_check8); - - \r.e.op1_RNIEHID[29]\ : MX2 - port map(A => \op1[29]\, B => \data_0_0[29]\, S => ldbp1, Y - => \un1_iu0_6[29]\); - - \r.e.ctrl.rd_RNI1FQ3S[6]\ : OR2 - port map(A => un1_rs1, B => N_3948, Y => \osel_i_a3_0[0]\); - - \r.e.op2_RNISLAE1[2]\ : OR2B - port map(A => \un1_iu0_5[68]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I33_un1_Y : NAND2 - port map(A => N484, B => N488, Y => I33_un1_Y); - - un6_ex_add_res_d0_ADD_33x33_fast_I269_Y : NAND2 - port map(A => I269_un1_Y_i, B => ADD_33x33_fast_I269_Y_0, Y - => N784); - - \r.x.ctrl.pc[31]\ : DFN1E0 - port map(D => \pc_3[31]\, CLK => lclk_c, E => holdn, Q => - \pc_2[31]\); - - \r.e.op2_RNO_4[16]\ : OA1A - port map(A => \maddress[16]\, B => d27_0, C => - \cpi_m_i[368]\, Y => \d_1_iv_1[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I34_Y\ : MAJ3 - port map(A => \dpc[28]\, B => \inst_0_1[28]\, C => N433, Y - => N451); - - \r.x.ctrl.rd_RNIBSGO[7]\ : NOR2B - port map(A => \rd_2[7]\, B => N_6357, Y => waddr(7)); - - \r.m.result_RNIUVO1[14]\ : OR2B - port map(A => d13, B => \maddress[14]\, Y => - \result_m_0[14]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I156_Y : NOR3C - port map(A => N493, B => N497, C => N567_0, Y => N625_0); - - \r.e.ldbp2_1_RNIQS1LJ1\ : OR2B - port map(A => annul_RNI5L7FE1, B => ldbp2_1_RNIL7Q55, Y => - \un6_ex_add_res_m[3]\); - - \r.m.y_RNI6APD2[0]\ : AOI1B - port map(A => \op2_RNI59C6[0]\, B => aluresult_7_sqmuxa, C - => \y_m_0[0]\, Y => \aluresult_2_iv_1[0]\); - - \r.e.ctrl.tt[5]\ : DFN1E0 - port map(D => \tt_2[5]\, CLK => lclk_c, E => holdn, Q => - \tt_3[5]\); - - \r.d.pc_RNO[7]\ : MX2 - port map(A => \fpc[7]\, B => \dpc[7]\, S => N_6763_i, Y => - \pc_RNO[7]\); - - \r.e.shleft_RNIPEFC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[17]\, S => - shleft, Y => \shiftin_5[48]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I136_Y : NOR2B - port map(A => N537_2, B => N533_1, Y => N599_2); - - \r.x.data_0_RNO_4[7]\ : OR2A - port map(A => \data_0_2[7]\, B => ld_3, Y => - \data_0_m_i[7]\); - - \r.x.ctrl.rd_RNIJVH6[4]\ : XNOR2 - port map(A => \rd_2[4]\, B => \rd_0[4]\, Y => rd_4_i_0); - - \r.e.ctrl.wreg\ : DFN1E0 - port map(D => wreg_1_10, CLK => lclk_c, E => holdn, Q => - wreg_7); - - \r.a.rsel2_0_RNIRR7232[0]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[2]\, Y => - \aluresult_m_i[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I81_un1_Y : NOR2B - port map(A => N416_1, B => N412_1, Y => I81_un1_Y); - - \r.e.jmpl_RNIEF4GN\ : OR2B - port map(A => \shiftin_17[11]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[11]\); - - \r.a.ctrl.cnt_RNIUBDQ4[0]\ : NOR3C - port map(A => N_360, B => \cnt_RNILD6A1[0]\, C => N_345, Y - => aluop_2_1_0_1); - - \r.e.ctrl.rd[2]\ : DFN1E0 - port map(D => \rd[2]\, CLK => lclk_c, E => holdn, Q => - \rd_1[2]\); - - \r.e.bp_RNO\ : NOR2B - port map(A => bp, B => \ra_bpmiss_1_0\, Y => bp_1_1); - - \r.a.rsel1_0_RNI4V53[2]\ : NOR2A - port map(A => N_484, B => \rsel1_0[2]\, Y => d13_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I60_Y : NOR2B - port map(A => N449_0, B => N446_1, Y => N519_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I316_Y_0_1 : XOR2 - port map(A => \data_0[25]\, B => \un1_iu0_6[25]\, Y => - \un6_ex_add_res_s2_1[26]\); - - \r.m.ctrl.pc[28]\ : DFN1E0 - port map(D => \pc_2[28]\, CLK => lclk_c, E => holdn, Q => - \pc_3[28]\); - - \r.e.ctrl.pc[20]\ : DFN1E0 - port map(D => \pc[20]\, CLK => lclk_c, E => holdn, Q => - \pc_0[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I244_un1_Y : NOR2 - port map(A => N674, B => N659_0, Y => I244_un1_Y); - - \r.e.jmpl_RNI5D4VT\ : OR2B - port map(A => \shiftin_17[27]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[27]\); - - \r.e.aluop_RNI402I6[0]\ : MX2C - port map(A => N_3573, B => N_3637, S => \aluop_1[0]\, Y => - \logicout[14]\); - - \r.d.inst_0_RNO[26]\ : NOR2B - port map(A => rst, B => N_4626, Y => \inst_0_RNO[26]\); - - \r.a.ctrl.wreg_RNI9KRTQ\ : NOR3C - port map(A => rfe_1_1, B => ldcheck1, C => rfe_1_2, Y => - rfe_1); - - \r.e.shleft_RNIS2381\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[28]\, S => - shleft, Y => \shiftin_5[59]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I28_P0N : OR2 - port map(A => \un1_iu0_6[27]\, B => \data_0[27]\, Y => N479); - - un6_ex_add_res_d0_ADD_33x33_fast_I268_Y : AO1 - port map(A => ADD_33x33_fast_I268_un1_Y_0_0, B => N674_1, C - => ADD_33x33_fast_I268_Y_0_1, Y => N782_1); - - \r.a.ctrl.inst_RNI9O0E[30]\ : OR2 - port map(A => \inst[30]\, B => \inst_1[24]\, Y => N_518); - - \r.d.pc_RNI66HB4[28]\ : MX2 - port map(A => \dpc[28]\, B => \fpc[28]\, S => ra_bpmiss_1, - Y => N_3905); - - \r.e.aluop_0_RNIST6R[2]\ : XA1 - port map(A => \un1_iu0_5[74]\, B => \aluop_0[2]\, C => - \un1_iu0_6[8]\, Y => N_3535); - - \r.d.inst_0[16]\ : DFN1 - port map(D => \inst_0_RNO[16]\, CLK => lclk_c, Q => - \inst_0[16]\); - - \comb.cwp_ctrl.ncwp_3_I_7\ : XNOR2 - port map(A => \inst_0[19]\, B => \cwp[1]\, Y => - \DWACT_ADD_CI_0_pog_array_0[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I122_Y : NOR3C - port map(A => N443_1, B => N440_1, C => N519_2, Y => N585_1); - - \r.f.pc_RNO_6[16]\ : MX2 - port map(A => \fpc[16]\, B => \eaddress[16]\, S => jump, Y - => N_4059); - - un6_ex_add_res_d2_ADD_33x33_fast_I318_Y_0_1 : XOR2 - port map(A => \data_0[27]\, B => \un1_iu0_6[27]\, Y => - \un6_ex_add_res_s2_1[28]\); - - \r.w.result[28]\ : DFN1E0 - port map(D => \wdata[28]\, CLK => lclk_c, E => holdn, Q => - \result[28]\); - - \r.m.y_RNO_3[10]\ : OR3A - port map(A => \y_2[10]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[10]\); - - \r.m.result_RNIREJ83[11]\ : NOR3C - port map(A => \d_iv_0[11]\, B => \result_m_0[11]\, C => - \rfo_m[11]\, Y => \d_iv_2[11]\); - - \r.a.rfa1_RNICHT01[3]\ : MX2 - port map(A => \un3_de_ren1[94]\, B => \rfa1[3]\, S => holdn, - Y => raddr1(3)); - - un6_ex_add_res_d2_ADD_33x33_fast_I295_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[4]\, B => \data_0[4]\, Y => - \un6_ex_add_res_s2_1[5]\); - - \r.e.shleft_1_RNI2UPK3\ : MX2 - port map(A => \shiftin_5[60]\, B => \shiftin_5[44]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[44]\); - - \r.x.laddr_RNI66ENI_0[0]\ : NOR2A - port map(A => \me_laddr_2[1]\, B => \me_laddr_2[0]\, Y => - rdata_2_sqmuxa_0); - - \r.m.result_RNIAJD4[22]\ : OR2B - port map(A => d13_0, B => \maddress[22]\, Y => - \result_m_0[22]\); - - \r.e.aluop_RNI4A334[1]\ : OR2B - port map(A => \bpdata[7]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[7]\); - - \r.a.et_RNINOBR1\ : OR3C - port map(A => N_256_i_0, B => illegal_inst_7_iv_2_0_a5_5_0, - C => N_6696, Y => N_444); - - un6_ex_add_res_d2_ADD_33x33_fast_I114_Y : NOR3C - port map(A => N458_0, B => N461_1, C => N_71_1, Y => N577_1); - - \r.w.s.y_RNO_1[24]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y_0[24]\, Y => N_367); - - \r.f.pc_RNO_2[17]\ : OR2B - port map(A => I_91, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[15]\); - - \un1_r.w.s.cwp_1_ANC1\ : OR3B - port map(A => \cwp[0]\, B => \cwp_0[1]\, C => - \rstate_RNIRDFU5[1]\, Y => ANC1); - - \r.x.data_0_RNO[9]\ : OR3 - port map(A => \dco_m_0[105]\, B => \data_0_1_0_iv_0[9]\, C - => \data_0_1_4[9]\, Y => \data_0_1[9]\); - - \r.w.s.icc[0]\ : DFN1E0 - port map(D => \icc_1[0]\, CLK => lclk_c, E => holdn, Q => - \icc[0]\); - - \r.m.ctrl.tt[2]\ : DFN1E0 - port map(D => \tt_3[2]\, CLK => lclk_c, E => holdn, Q => - \tt_2[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I264_Y_0_0\ : XOR2 - port map(A => \dpc[6]\, B => \inst_0_RNI4VUM[4]\, Y => - ADD_30x30_fast_I264_Y_0_0); - - \r.f.pc_RNO_1[14]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[14]\, C => m7_0, - Y => m7_1); - - \r.w.result[20]\ : DFN1E0 - port map(D => \wdata[20]\, CLK => lclk_c, E => holdn, Q => - \result_0[20]\); - - \r.e.op1_RNI2H3V15[17]\ : NOR3C - port map(A => \op1_m_0[17]\, B => \d_iv_2[17]\, C => - \aluresult_m_0[17]\, Y => \d_i[17]\); - - \r.w.result_RNIC0P1[18]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[18]\, Y - => \result_m_0_0[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I272_Y_0\ : XNOR2 - port map(A => N732_i, B => ADD_30x30_fast_I272_Y_0_0, Y => - \tmp[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I223_Y\ : AO1 - port map(A => N607, B => N358, C => N606, Y => N741); - - \r.m.ctrl.inst_RNI6E2S[19]\ : OR3A - port map(A => \inst_3[19]\, B => \inst_0[24]\, C => - trap_0_sqmuxa_3_2, Y => trap_0_sqmuxa_3_1); - - \r.e.jmpl_RNI2UJLU\ : OR2B - port map(A => \shiftin_17[28]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[28]\); - - \r.m.ctrl.ld_RNICKJJ\ : AO1 - port map(A => ld, B => d13_0, C => N_219, Y => ldbp); - - \r.d.inst_0_RNI62J4_0[23]\ : NOR3B - port map(A => \inst_0_0[23]\, B => \inst_0[20]\, C => - \inst_0[19]\, Y => icc_check_3_0_a3_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I23_G0N : AND2 - port map(A => \op2[22]\, B => \un1_iu0_6[22]\, Y => N463); - - \r.w.s.y[19]\ : DFN1E0 - port map(D => N_3783, CLK => lclk_c, E => N_6922_i_0, Q => - \y[19]\); - - \r.m.result[11]\ : DFN1E0 - port map(D => \eres2[11]\, CLK => lclk_c, E => holdn, Q => - \maddress[11]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I297_Y_0 : XOR3 - port map(A => \un1_iu0_6[6]\, B => \op2[6]\, C => N674_0, Y - => \un6_ex_add_res_s1[7]\); - - \r.w.s.tba[2]\ : DFN1E1 - port map(D => \result_0[14]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[2]\); - - \r.e.op2_RNO_7[28]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[380]\, - Y => \cpi_m_i[380]\); - - \r.m.ctrl.pc_RNI21M9[11]\ : MX2 - port map(A => \pc_1[11]\, B => \pc[11]\, S => \npc[1]\, Y - => N_3252); - - \r.m.ctrl.rd[3]\ : DFN1E0 - port map(D => \rd[3]\, CLK => lclk_c, E => holdn, Q => - \rd_0[3]\); - - \r.e.op2_RNO_0[13]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[13]\, C - => \d_1_iv_4[13]\, Y => \d_1[13]\); - - \r.e.op1_RNIT2NF[20]\ : NOR2A - port map(A => un17_casaen_0_2, B => \op1[20]\, Y => - \op1_i_m[20]\); - - \r.e.op2_RNO_5[15]\ : AOI1B - port map(A => \result[15]\, B => d31_0, C => \imm_m_i[15]\, - Y => \d_1_iv_0[15]\); - - \r.e.aluop_RNI99SC4[1]\ : NOR2A - port map(A => edata_2_sqmuxa, B => \bpdata[17]\, Y => - \bpdata_i_m[17]\); - - \r.e.alucin_RNI0313\ : XOR2 - port map(A => alucin, B => \data_0[0]\, Y => - \un6_ex_add_res_s0_0_0[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I81_Y : AO13 - port map(A => \un1_iu0_6[6]\, B => \data_0[6]\, C => N412_2, - Y => N540_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I28_G0N : NOR2B - port map(A => \un1_iu0_6[27]\, B => \data_0[27]\, Y => - N478_2); - - \comb.lock_gen.un1_icc_check5_RNO\ : NOR2A - port map(A => un1_icc_check5_1, B => imm9, Y => - un1_icc_check5_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I22_G0N : OA1 - port map(A => \op1[21]\, B => ldbp1_4, C => \data_0[21]\, Y - => N460_2); - - \r.m.result_RNI64P1[29]\ : OR2B - port map(A => d13, B => \maddress[29]\, Y => - \result_m_0_0[29]\); - - \r.e.alusel_RNO_1[0]\ : NOR3C - port map(A => N_351, B => N_352, C => N_602, Y => - \alusel_i_0_1[0]\); - - \r.w.s.et_RNI4T46\ : NOR2B - port map(A => N_6337, B => rst, Y => G_9_0); - - \r.e.invop2_1_RNIDR3T73\ : MX2 - port map(A => \un6_ex_add_res_s2[32]\, B => - \un6_ex_add_res_s0[32]\, S => invop2_1, Y => N_6659); - - \r.m.dci.write_RNO\ : NOR3 - port map(A => N_3356_3, B => annul, C => write_3_tz, Y => - write); - - \r.x.ctrl.pc_RNIPL971[21]\ : MX2C - port map(A => \un1_p0_6[373]\, B => \pc_2[21]\, S => - s_3_sqmuxa, Y => N_3412); - - \r.e.aluop_RNIOSDKR[0]\ : AOI1B - port map(A => \logicout[31]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[31]\, Y => \aluresult_1_iv_7[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I105_un1_Y : NOR2B - port map(A => N506_1, B => N503, Y => I105_un1_Y); - - \r.e.op1_RNO[8]\ : MX2C - port map(A => \d_i[8]\, B => \d_i[9]\, S => N_227, Y => - \aop1[8]\); - - \r.x.ctrl.pc_RNI12A71[16]\ : MX2C - port map(A => \un1_p0_6[368]\, B => \pc_2[16]\, S => - s_3_sqmuxa, Y => N_3407); - - \r.e.alusel_RNO_3[1]\ : NOR3 - port map(A => N_487, B => N_492, C => \cnt_2[1]\, Y => - \alusel_i_0_a5_0_0[1]\); - - \r.e.op2_RNO_0[9]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[9]\, C - => \d_1_iv_4[9]\, Y => \d_1[9]\); - - \r.a.ctrl.inst_RNI5H3O1[19]\ : NOR3A - port map(A => N_226, B => N_203, C => N_204, Y => N_227); - - \r.f.pc_RNI77A6U1[7]\ : OA1A - port map(A => annul_RNI5L7FE1, B => \eaddress[7]\, C => - \pc_m[7]\, Y => \npc_iv_1[7]\); - - \r.m.y_RNI62BTG[10]\ : NOR3C - port map(A => \bpdata_m_2[2]\, B => \aluresult_1_iv_3[10]\, - C => \aluresult_1_iv_4[10]\, Y => \aluresult_1_iv_6[10]\); - - \r.m.ctrl.rd[5]\ : DFN1E0 - port map(D => \rd[5]\, CLK => lclk_c, E => holdn, Q => - \rd_2[5]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I125_Y\ : OR2B - port map(A => ADD_30x30_fast_I125_Y_0, B => N486, Y => N545); - - \r.a.rsel1_0_RNIR48M2[2]\ : OR2B - port map(A => data1(3), B => d11_0, Y => \rfo_m[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I292_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[2]\, B => N552_1, Y => - \un6_ex_add_res_s2[2]\); - - \r.w.result_RNIGTB4[9]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[9]\, Y - => \result_m_0[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I172_Y\ : OR2 - port map(A => N538_2, B => I172_un1_Y, Y => N598); - - \r.e.aluop_0_RNIN7K85[0]\ : MX2C - port map(A => N_3587, B => N_3651, S => \aluop_0[0]\, Y => - \logicout[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I273_un1_Y_0 : NOR3A - port map(A => N552_1, B => N603_i, C => N611, Y => - ADD_33x33_fast_I273_un1_Y_0_1); - - \r.x.y[9]\ : DFN1E0 - port map(D => \y_1[9]\, CLK => lclk_c, E => holdn, Q => - \y_2[9]\); - - \r.a.ctrl.rd[5]\ : DFN1E0 - port map(D => N_35, CLK => lclk_c, E => holdn, Q => - \rd_1[5]\); - - \r.m.ctrl.rd_RNIOM7Q[2]\ : XNOR2 - port map(A => \inst_0_RNI2NUM[2]\, B => \rd_0[2]\, Y => - un1_de_ren1_1_2_i_0); - - \r.a.ctrl.pc_RNI7OK0C[2]\ : MX2 - port map(A => \pc[2]\, B => N_3879, S => ex_bpmiss_1_0, Y - => \fe_pc[2]\); - - \r.m.ctrl.inst_RNIVK0E[21]\ : OR2 - port map(A => \inst_2[22]\, B => \inst[21]\, Y => - trap_0_sqmuxa_2_2); - - \r.f.pc_RNILIC62[9]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[9]\, Y => \xc_trap_address_m[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I25_G0N\ : NOR2B - port map(A => \inst_0_1[27]\, B => \dpc[27]\, Y => N433); - - \r.x.data_0_RNICF9E[15]\ : XOR2 - port map(A => \data_0_2[15]\, B => invop2_1, Y => N_4262); - - \r.m.y_RNO_0[9]\ : NOR3C - port map(A => \y_m[10]\, B => \y_m_0[9]\, C => \y_iv_1[9]\, - Y => \y_iv_2[9]\); - - \r.e.aluop_0_RNIGGO4K[0]\ : NOR3C - port map(A => \aluresult_1_iv_5[8]\, B => - \aluresult_1_iv_4[8]\, C => \logicout_m_0[8]\, Y => - \aluresult_1_iv_7[8]\); - - \r.x.mexc\ : DFN1 - port map(D => mexc_RNO, CLK => lclk_c, Q => mexc_0); - - \r.d.inst_0_RNIB423[26]\ : OR2 - port map(A => \inst_0[27]\, B => \inst_0[26]\, Y => N_122_2); - - \r.w.result_RNIGGFF[0]\ : AOI1B - port map(A => \un1_p0_6[352]\, B => d14, C => - \result_m_0_0[0]\, Y => \d_iv_0[0]\); - - \r.m.result[9]\ : DFN1E0 - port map(D => \eres2[9]\, CLK => lclk_c, E => holdn, Q => - \maddress[9]\); - - \r.e.jmpl_RNIN2MUS\ : OR2B - port map(A => \shiftin_17[24]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[24]\); - - \r.d.inst_0[28]\ : DFN1 - port map(D => \inst_0_RNO[28]\, CLK => lclk_c, Q => - \inst_0[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I129_Y_0 : AO18 - port map(A => \un1_iu0_6[13]\, B => N433_1, C => - \data_0[13]\, Y => ADD_33x33_fast_I129_Y_0_0); - - un2_rstn_5_RNIUJPE8 : NAND2 - port map(A => \tmp[7]\, B => \un2_rstn_5\, Y => \tmp_m[7]\); - - \r.e.shleft_RNI2OCF1\ : MX2C - port map(A => \shiftin_5[29]\, B => \shiftin_5[13]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[13]\); - - \r.m.ctrl.annul_RNO\ : OR2 - port map(A => annul, B => \un1_p0_6[0]\, Y => annul_1_1); - - \r.e.aluop_RNIKFE1O[0]\ : AOI1B - port map(A => \logicout[10]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[10]\, Y => \aluresult_1_iv_7[10]\); - - \r.x.ctrl.pc[4]\ : DFN1E0 - port map(D => \pc_3[4]\, CLK => lclk_c, E => holdn, Q => - \pc_2[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I24_P0N : AO1A - port map(A => ldbp1, B => \op1[23]\, C => \data_0[23]\, Y - => N467); - - \r.e.invop2_RNI9V6D1\ : MX2C - port map(A => \un6_ex_add_res_s2[2]\, B => - \un6_ex_add_res_s0[2]\, S => invop2, Y => N_6641); - - \r.d.inst_0_RNI73A31[13]\ : OR3C - port map(A => N_127, B => N_126, C => N_128, Y => imm); - - \r.x.laddr_RNIUO2VN1[1]\ : OR2 - port map(A => rdata_6_sqmuxa, B => rdata_4_sqmuxa, Y => - N_3473); - - \r.x.ctrl.pc_RNI5HR31[3]\ : MX2C - port map(A => \un1_p0_6[355]\, B => \pc_2[3]\, S => - s_3_sqmuxa, Y => N_3394); - - un6_ex_add_res_d2_ADD_33x33_fast_I2_P0N : AO1A - port map(A => ldbp1_0, B => \op1[1]\, C => \data_0[1]\, Y - => N401_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I55_Y_0_o3 : AO1 - port map(A => N455_0, B => N451_0, C => N454_0, Y => N514_0); - - \r.w.result[26]\ : DFN1E0 - port map(D => \wdata[26]\, CLK => lclk_c, E => holdn, Q => - \result_0[26]\); - - \r.e.shleft_0_RNIATHM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[31]\, S => - shleft_0, Y => \shiftin_5[62]\); - - \r.a.rsel1_RNIK8V804[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[15]\, Y => - \aluresult_m_0[15]\); - - \r.e.aluop_0_RNIH2S72[0]\ : NOR3A - port map(A => aluresult_13_sqmuxa_3_0, B => miscout140_1, C - => \aluop_0[0]\, Y => aluresult_13_sqmuxa); - - \r.x.data_0_RNI1P5I1[3]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[3]\, Y => - \ex_op1_i_m[3]\); - - \r.m.result_RNO[4]\ : MX2 - port map(A => \aluresult[4]\, B => \op1[4]\, S => - \un17_casaen_0_0\, Y => \eres2[4]\); - - \r.w.result_RNILKV6[3]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[3]\, - Y => \result_m_0_0[3]\); - - \r.w.s.y_RNO_1[27]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y[27]\, Y => N_409); - - \r.e.op2_RNI0OMB1_0[14]\ : OR2 - port map(A => \un1_iu0_6[14]\, B => \un1_iu0_5[80]\, Y => - \logicout_3[14]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I62_Y : OR2B - port map(A => N446_1, B => N443_1, Y => N521_0); - - \r.w.result_RNI4C5J[15]\ : AOI1B - port map(A => \un1_p0_6[367]\, B => d14_0, C => - \result_m_0_0[15]\, Y => \d_iv_0[15]\); - - \r.w.s.wim[7]\ : DFN1E0 - port map(D => \wim_1[7]\, CLK => lclk_c, E => holdn, Q => - \wim[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I246_Y_0_a3 : NOR2B - port map(A => N808_1, B => N431_0, Y => - ADD_33x33_fast_I246_Y_0_a3); - - un23_ra_I_13 : XOR2 - port map(A => \cwp[1]\, B => \DWACT_ADD_CI_0_TMP_1[0]\, Y - => I_13_2); - - \r.w.s.pil[1]\ : DFN1E0 - port map(D => \result_0[9]\, CLK => lclk_c, E => N_6699, Q - => \pil[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_un1_Y_0 : AND2 - port map(A => N653, B => N637, Y => - ADD_33x33_fast_I265_un1_Y_0); - - \r.m.y_RNI52BV2[29]\ : AOI1B - port map(A => \y[29]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[29]\, Y => \aluresult_1_iv_0[29]\); - - \r.e.op2_RNO_7[12]\ : NOR2B - port map(A => \result_m_i_0[12]\, B => \cpi_m_i[364]\, Y - => \d_1_iv_1[12]\); - - \r.e.op2_RNO[29]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[29]\, Y => N_313); - - \r.f.pc[3]\ : DFN1E0 - port map(D => \pc_1[3]\, CLK => lclk_c, E => holdn, Q => - \fpc[3]\); - - \r.e.aluop_0_RNINF093[1]\ : MX2C - port map(A => \logicout_4[13]\, B => N_6898, S => N_6866_i, - Y => N_3636); - - \r.a.ctrl.rd_RNO[2]\ : OR2A - port map(A => N_85, B => \inst_0[27]\, Y => \rd_2[2]\); - - \r.m.casa_RNI8BU9_1\ : NOR2A - port map(A => casa, B => N_3355_1, Y => un17_casaen_0_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I273_Y_0 : AO1 - port map(A => ADD_33x33_fast_I273_un1_Y_0, B => N653_0, C - => N652_1, Y => ADD_33x33_fast_I273_Y_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I19_P0N : OR2 - port map(A => \un1_iu0_6[18]\, B => \op2[18]\, Y => N452_0); - - \r.x.ctrl.wy_RNI4SI14\ : OR2 - port map(A => wy_RNILF1N3, B => holdn, Y => N_6922_i); - - \r.a.imm_RNO[7]\ : NOR2B - port map(A => \inst_0[7]\, B => call_hold5, Y => - \un3_de_ren1[125]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y : NAND2 - port map(A => I260_un1_Y_i, B => ADD_33x33_fast_I260_Y_3, Y - => N766); - - un6_ex_add_res_d2_ADD_33x33_fast_I74_Y : OA1 - port map(A => \data_0[10]\, B => \un1_iu0_6[10]\, C => - N425_2, Y => N533_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I108_Y : NOR2B - port map(A => N509_0, B => N505_0, Y => N571); - - \r.x.result_RNIRK6E[24]\ : MX2 - port map(A => \result_0[24]\, B => \data_0[24]\, S => ld_4, - Y => \un1_p0_6[376]\); - - \r.d.inst_0_RNI3KR23[16]\ : NOR3A - port map(A => rs1_2, B => \un3_de_ren1[94]\, C => - \un3_de_ren1[93]\, Y => rs1); - - \comb.branch_address.tmp_ADD_30x30_fast_I99_Y\ : NOR2B - port map(A => N464_1, B => N460_0, Y => N519); - - \r.e.shcnt_RNI06RGQ[1]\ : MX2C - port map(A => \shiftin_14[22]\, B => \shiftin_14[20]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[20]\); - - \r.m.ctrl.trap_RNI1J7731\ : OR2B - port map(A => tt_0_sqmuxa, B => trap_0_sqmuxa_7, Y => - tt_1_sqmuxa_1); - - \r.e.shcnt_RNIFVRIB[2]\ : MX2C - port map(A => \shiftin_11[18]\, B => \shiftin_11[14]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[14]\); - - \r.d.annul_RNIF0HMG4\ : OR2B - port map(A => I_31, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[6]\); - - \r.f.pc_RNIF1DAA7[9]\ : NOR2B - port map(A => \tmp_m[9]\, B => \pc_4_m[9]\, Y => - \npc_iv_0[9]\); - - \r.e.op2_RNI8NVJ[23]\ : MX2 - port map(A => \op2[23]\, B => N_4270, S => ldbp2_2, Y => - \un1_iu0_5[89]\); - - \r.d.inst_0_RNO[8]\ : NOR2B - port map(A => rst, B => N_4608, Y => \inst_0_RNO[8]\); - - \r.x.result[24]\ : DFN1E0 - port map(D => \maddress[24]\, CLK => lclk_c, E => holdn, Q - => \result_0[24]\); - - \r.m.ctrl.rd_RNI7V2V[0]\ : XNOR2 - port map(A => \rs1_iv_i_0[0]\, B => \rd_1[0]\, Y => - un2_rs1_2_0_i_0); - - \r.e.shcnt_RNIOVDVE[2]\ : MX2C - port map(A => \shiftin_11[34]\, B => \shiftin_11[30]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[30]\); - - \r.e.op2_RNIBHPA_0[9]\ : OR2 - port map(A => \un1_iu0_6[9]\, B => \un1_iu0_5[75]\, Y => - \logicout_3[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I296_Y_0 : XOR3 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N676, - Y => \un6_ex_add_res_s2[6]\); - - \r.d.pc_RNO[14]\ : MX2 - port map(A => \fpc[14]\, B => \dpc[14]\, S => N_6763_i, Y - => \pc_RNO[14]\); - - \r.d.pv_RNI0R6T91\ : AO1D - port map(A => un6_rabpmiss_2, B => un13_exbpmiss_0, C => - \de_hold_pc_1\, Y => annul_next_2_sqmuxa_1_8); - - un6_ex_add_res_d2_ADD_33x33_fast_I297_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[7]\, B => N674, Y => - \un6_ex_add_res_s2[7]\); - - \r.x.ctrl.pc_RNIFOI61[19]\ : MX2C - port map(A => \un1_p0_6[371]\, B => \pc_0[19]\, S => - s_3_sqmuxa, Y => N_3410); - - \r.e.op1_RNI0NCR1[27]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[27]\, Y => - \ex_op1_i_m[27]\); - - \r.e.ctrl.trap_RNISBSJ\ : OR2A - port map(A => un3_notag, B => trap_0, Y => jump_0_sqmuxa); - - un6_fe_npc_I_52 : XOR2 - port map(A => N_116, B => \fe_pc[11]\, Y => I_52); - - \r.m.y[21]\ : DFN1E0 - port map(D => \y_0[21]\, CLK => lclk_c, E => holdn, Q => - \y[21]\); - - \r.m.result_RNO[26]\ : MX2 - port map(A => \aluresult[26]\, B => \op1[26]\, S => - un17_casaen_0_1, Y => \eres2[26]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I56_Y_0\ : AO1 - port map(A => N404_0, B => N400, C => N403, Y => N473_0); - - \r.x.annul_all_RNIPVOS\ : AO1D - port map(A => rett_1_0, B => rett_0_0, C => annul_all, Y - => su2); - - \r.d.inst_0_RNO_0[20]\ : MX2 - port map(A => data_0_20, B => \inst_0[20]\, S => - inull_RNIFV6VG2_0, Y => N_4620); - - \r.d.inst_0_RNI62J4[23]\ : OR3A - port map(A => \inst_0[19]\, B => \inst_0_0[23]\, C => - \inst_0[20]\, Y => N_3721); - - un6_ex_add_res_d1_ADD_33x33_fast_I270_Y_0_o3 : OA1C - port map(A => N790_0, B => N_30, C => N514_1, Y => N786_i); - - \r.e.op1_RNIMI8G[20]\ : OR2B - port map(A => \op1[20]\, B => un14_casaen_s1_0, Y => - \op1_m_0[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I299_Y_0 : XNOR2 - port map(A => N817, B => \un6_ex_add_res_s2_1[9]\, Y => - \un6_ex_add_res_s0[9]\); - - \r.e.jmpl_RNI3D91I1\ : AOI1B - port map(A => \shiftin_17[20]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[19]\, Y => \aluresult_1_iv_7[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I271_Y_0 : NOR3A - port map(A => I235_un1_Y_i, B => I179_un1_Y, C => N582, Y - => ADD_33x33_fast_I271_Y_0_0); - - \r.e.shleft_RNID1MH2\ : MX2B - port map(A => \shiftin_5[34]\, B => \shiftin_5[18]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[18]\); - - \r.d.inst_0[31]\ : DFN1 - port map(D => \inst_0_RNO[31]\, CLK => lclk_c, Q => - \inst_0[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I1_G0N : OA1 - port map(A => \op1[0]\, B => ldbp1_0, C => \data_0[0]\, Y - => N397_1); - - \r.d.inst_0_RNO_0[3]\ : MX2 - port map(A => data_0_0_3, B => \inst_0[3]\, S => - mexc_1_sqmuxa_1_0, Y => N_4603); - - \r.d.annul_RNIRK1K4_0\ : OR2A - port map(A => un9_rabpmiss_1, B => \ra_bpmiss_1_0\, Y => - un9_rabpmiss); - - \r.e.op1[2]\ : DFN1E0 - port map(D => \aop1[2]\, CLK => lclk_c, E => holdn, Q => - \op1[2]\); - - \r.m.y_RNIOJEJ3[8]\ : AND2 - port map(A => \tt_m[4]\, B => \aluresult_1_iv_1[8]\, Y => - \aluresult_1_iv_3[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I269_un1_Y : OR3C - port map(A => N645_1, B => N661_0, C => N676_1, Y => - I269_un1_Y_0); - - \r.e.op1_RNIVG9GN5[20]\ : NOR3C - port map(A => \op1_m_0[20]\, B => \d_iv_2[20]\, C => - \aluresult_m_0[20]\, Y => \d_i[20]\); - - \r.e.ldbp2_RNI12HDB\ : OR2A - port map(A => \eaddress[5]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[6]\); - - \r.w.s.pil_RNI7MFA1[0]\ : OR2A - port map(A => \pil[0]\, B => aluresult_11_sqmuxa, Y => - \pil_m[0]\); - - \r.m.ctrl.pc[8]\ : DFN1E0 - port map(D => \pc_2[8]\, CLK => lclk_c, E => holdn, Q => - \pc_3[8]\); - - \r.e.invop2_0_RNID83K9\ : MX2 - port map(A => \un6_ex_add_res_s2[8]\, B => - \un6_ex_add_res_s0[8]\, S => invop2_0, Y => N_6554); - - \r.m.ctrl.inst_RNIVC0E[30]\ : OR2B - port map(A => \inst_1[31]\, B => \inst_1[30]\, Y => - un5_trap); - - un6_ex_add_res_d2_ADD_33x33_fast_I79_Y_0 : AO1 - port map(A => N419_0, B => N415_2, C => N418, Y => N538_0); - - \r.f.pc_RNO_5[14]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[14]\, Y => \xc_trap_address_m[14]\); - - \r.x.data_0_RNO_2[12]\ : NOR2A - port map(A => \data_0_2[12]\, B => ld_0_0, Y => - \data_0_m[12]\); - - \r.m.ctrl.rd_RNI3RO53[1]\ : NOR3C - port map(A => un2_rs1_2_7_i_0, B => un2_rs1_2_5_i_0, C => - wreg_1_2_0, Y => wreg_1_5); - - \r.m.dci.size[1]\ : DFN1E0 - port map(D => \size[1]\, CLK => lclk_c, E => holdn, Q => - \size_0[1]\); - - \r.w.s.y_RNO[12]\ : MX2 - port map(A => \y_2[12]\, B => \result[12]\, S => N_481_0, Y - => N_3776); - - un23_ra_I_9 : XOR2 - port map(A => \cwp_0[0]\, B => \inst_0[18]\, Y => - \DWACT_ADD_CI_0_partial_sum_0[0]\); - - \r.e.aluop_0_RNI67I22[0]\ : OR2B - port map(A => \logicout[9]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[9]\); - - \r.a.ctrl.inst_RNIK42S[22]\ : NOR2A - port map(A => N_271, B => N_256_i_0, Y => - illegal_inst12_tz_tz); - - \r.x.result_RNIOMED[13]\ : MX2 - port map(A => \result_0[13]\, B => \data_0[13]\, S => ld_0, - Y => \un1_p0_6[365]\); - - \r.e.op1_RNIRE4U1[8]\ : AO1A - port map(A => \op1[8]\, B => \un17_casaen_0_0\, C => - \ex_op1_i_m[8]\, Y => \edata2_0_iv_0[8]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I4_P0N\ : OR2 - port map(A => \inst_0_RNI4VUM[4]\, B => \dpc[6]\, Y => N371); - - \r.e.aluop_1_RNIMO642[1]\ : MX2C - port map(A => \logicout_4[2]\, B => N_6907, S => N_6866_i, - Y => N_3625); - - \r.x.data_0_RNO_1[22]\ : NOR2A - port map(A => \data_0_0[22]\, B => ld_3, Y => - \data_0_m[22]\); - - \r.f.pc_RNO[22]\ : OR3C - port map(A => \tmp_m[22]\, B => \pc_1_iv_1[22]\, C => - \un6_fe_npc_m[20]\, Y => \pc_1[22]\); - - \r.e.shleft_RNI1RFM2\ : MX2B - port map(A => \shiftin_5[44]\, B => \shiftin_5[28]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[28]\); - - \r.e.jmpl_RNIUPCSQ5\ : OR3C - port map(A => \aluresult_1_iv_8[21]\, B => - \shiftin_17_m_0[21]\, C => \un6_ex_add_res_m[22]\, Y => - \aluresult[21]\); - - \r.e.sari_RNIC80T\ : MX2 - port map(A => sari, B => ex_sari_1, S => ldbp1_0, Y => - ex_sari_1_1_0_0); - - \r.e.jmpl_RNIGRVKM2\ : NOR3C - port map(A => \shiftin_17_m[27]\, B => - \aluresult_1_iv_7[26]\, C => \shiftin_17_m_0[26]\, Y => - \aluresult_1_iv_9[26]\); - - un6_fe_npc_I_115 : XOR2 - port map(A => N_71_0, B => \fe_pc[20]\, Y => I_115); - - un6_ex_add_res_d2_ADD_33x33_fast_I190_Y : OR3C - port map(A => N535_1, B => ADD_33x33_fast_I138_Y_0_0, C => - N593_1, Y => N659_0); - - \r.w.s.y[10]\ : DFN1E0 - port map(D => N_3774, CLK => lclk_c, E => N_6922_i_0, Q => - \y[10]\); - - \r.e.ldbp1\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1); - - \r.x.ctrl.rd_RNIE2NU[6]\ : MX2 - port map(A => \cwp[2]\, B => \rd_2[6]\, S => N_6357, Y => - waddr(6)); - - \r.x.data_0_RNIIJ9E[29]\ : XNOR2 - port map(A => \data_0_0[29]\, B => invop2_0, Y => N_4276_i); - - \r.f.pc_RNO[14]\ : OR3C - port map(A => N_29, B => m7_1, C => N_6619, Y => N_8_0_i_0); - - \r.e.op1_RNIKPAT4[21]\ : AO1A - port map(A => \bpdata[21]\, B => edata_2_sqmuxa, C => - \op1_i_m[21]\, Y => \edata2_0_iv_0[21]\); - - \r.e.op1_RNIAHFC[6]\ : OR2B - port map(A => \op1[6]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[6]\); - - \r.e.shcnt_RNID03J9[2]\ : MX2C - port map(A => \shiftin_11[7]\, B => \shiftin_11[3]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[3]\); - - \r.e.op2_RNI59C6[0]\ : MX2 - port map(A => \op2[0]\, B => N_3304, S => ldbp2_3, Y => - \op2_RNI59C6[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I41_Y : AO13 - port map(A => N472_2, B => \un1_iu0_6[26]\, C => - \data_0[26]\, Y => N500); - - \r.a.ctrl.rd_RNIRVMDC[6]\ : NOR2B - port map(A => wreg_6, B => un1_de_ren1_NE_i_0, Y => - un1_de_ren1_2); - - \r.a.ctrl.inst_RNI23QQ3[22]\ : OAI1 - port map(A => N_483, B => N_6696, C => \inst[22]\, Y => - N_500); - - \r.w.s.y_RNO_1[18]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y[18]\, Y => N_390); - - \r.f.pc_RNI429LB[4]\ : MX2 - port map(A => \fpc[4]\, B => \eaddress[4]\, S => jump, Y - => N_4047); - - \r.d.inst_0_RNI3IRK91[13]\ : OA1B - port map(A => un1_de_ren1_2, B => \osel_i_a3_0[0]\, C => - imm, Y => N_3944); - - \r.e.jmpl_RNI8ML1S\ : OR2B - port map(A => \shiftin_17[22]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[22]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I86_Y : NOR2B - port map(A => N410_0, B => N407_2, Y => N545_1); - - \r.f.pc_RNO_2[31]\ : OR2B - port map(A => I_210, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[29]\); - - \r.e.op2_RNI88NB1_0[16]\ : OR2 - port map(A => \un1_iu0_6[16]\, B => \un1_iu0_5[82]\, Y => - \logicout_3[16]\); - - \r.d.inst_0_RNIKD1B[31]\ : NOR3C - port map(A => \inst_0[31]\, B => \inst_0_0[24]\, C => - de_fins_hold_1_1, Y => de_fins_hold_1_2); - - \r.a.ctrl.inst_RNI5H3O1[22]\ : OR3A - port map(A => aluop_2_1_0_a2_1, B => N_225, C => N_204, Y - => N_473_i); - - \r.e.shleft_0_RNIU2BG\ : NOR2A - port map(A => \un1_iu0_6[1]\, B => shleft_0, Y => - shleft_0_RNIU2BG); - - \r.e.ldbp2_2_RNILAU51\ : MX2C - port map(A => \un6_ex_add_res_s1_i[1]\, B => N_6640_i, S - => ldbp2_2, Y => \eaddress[0]\); - - \r.e.cwp_RNIGTJ61[1]\ : OR2A - port map(A => \cwp_2[1]\, B => aluresult_11_sqmuxa, Y => - \cwp_m[1]\); - - \r.d.inull_RNIPRHA\ : NOR3C - port map(A => un19_inst, B => \inull\, C => - hold_pc_1_sqmuxa, Y => hold_pc_2_m); - - \comb.branch_address.tmp_ADD_30x30_fast_I157_Y\ : NOR2B - port map(A => N531, B => N523, Y => N583); - - \r.e.shcnt_RNIV2HIP[1]\ : MX2C - port map(A => \shiftin_14[20]\, B => \shiftin_14[18]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[18]\); - - \r.e.ldbp2_2_RNIC3RV5\ : MX2C - port map(A => \un6_ex_add_res_s1[4]\, B => N_6643, S => - ldbp2_2, Y => \eaddress[3]\); - - \r.e.mulstep_RNI8VGC\ : OR2A - port map(A => wy_0, B => mulstep, Y => y14); - - \r.d.inst_0[22]\ : DFN1 - port map(D => \inst_0_RNO[22]\, CLK => lclk_c, Q => - \inst_0_0[22]\); - - \r.e.op1_RNIS2NF[10]\ : NOR2A - port map(A => un17_casaen_0, B => \op1[10]\, Y => - \op1_i_m[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I259_un1_Y : OR3C - port map(A => N641_0, B => N625, C => N796, Y => I259_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I260_un1_Y : OR3C - port map(A => N643_0, B => N627_1, C => N799_0, Y => - I260_un1_Y); - - \r.d.pc_RNO[16]\ : MX2 - port map(A => \fpc[16]\, B => \dpc[16]\, S => N_6763_i, Y - => \pc_RNO[16]\); - - \r.e.ctrl.pc_RNI40LA2[5]\ : AOI1B - port map(A => \pc[5]\, B => jmpl_0, C => \y_m_1[5]\, Y => - \aluresult_1_iv_2[5]\); - - \comb.v.x.data_0_1_1_iv[31]\ : OR2 - port map(A => \data_0_1_2[17]\, B => \data_0_1_1_iv_1[31]\, - Y => \data_0_1[31]\); - - \r.x.ctrl.annul_RNIK8PV\ : OR2A - port map(A => s_3_sqmuxa, B => holdn, Y => N_6747); - - \r.e.ldbp2_2_RNI8OPVN\ : MX2 - port map(A => \un6_ex_add_res_s1[10]\, B => N_6629, S => - ldbp2_2, Y => \eaddress[9]\); - - \r.f.pc_RNO_2[20]\ : OR2B - port map(A => I_115, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[18]\); - - \r.e.op2_RNI15BP_0[8]\ : OR2 - port map(A => \un1_iu0_6[8]\, B => \un1_iu0_5[74]\, Y => - \logicout_3[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I268_Y : OR2 - port map(A => I229_un1_Y, B => ADD_33x33_fast_I268_Y_0, Y - => N782); - - \r.e.op1[15]\ : DFN1E0 - port map(D => \aop1[15]\, CLK => lclk_c, E => holdn, Q => - \op1[15]\); - - \r.w.s.wim_RNI85RD2[2]\ : OR2B - port map(A => \wim[2]\, B => aluresult_13_sqmuxa, Y => - \wim_m[2]\); - - \r.d.pc_RNO[10]\ : MX2 - port map(A => \fpc[10]\, B => \dpc[10]\, S => N_6763_i_0, Y - => \pc_RNO[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I26_G0N : NOR2A - port map(A => \un1_iu0_6[25]\, B => \data_0[25]\, Y => - N472_2); - - \r.e.aluop_RNIS3JJ1[2]\ : XA1 - port map(A => \un1_iu0_5[82]\, B => \aluop_1[2]\, C => - \un1_iu0_6[16]\, Y => N_3543); - - \r.a.ctrl.inst_RNITAMH[5]\ : NOR3B - port map(A => \inst[8]\, B => un29_casaen_3, C => \inst[5]\, - Y => un29_casaen_5); - - \r.f.pc_RNIPJB2P2[4]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[4]\, Y => - \pc_4_m[4]\); - - \r.d.inst_0_RNO_0[29]\ : MX2 - port map(A => data_0_2_29, B => \inst_0[29]\, S => - inull_RNIFV6VG2_0, Y => N_4629); - - \r.e.op2[4]\ : DFN1E0 - port map(D => N_288, CLK => lclk_c, E => holdn, Q => - \op2[4]\); - - \r.a.imm[8]\ : DFN1E0 - port map(D => \un3_de_ren1[126]\, CLK => lclk_c, E => holdn, - Q => \imm[8]\); - - \r.e.jmpl_RNIL4D8K\ : OR2B - port map(A => \shiftin_17[2]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I267_un1_Y : OR3C - port map(A => N641_1, B => N657_1, C => N672_1, Y => - I267_un1_Y_0); - - \r.f.pc_RNO_1[12]\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[12]\, Y => - \un6_ex_add_res_m_1[13]\); - - \r.f.pc_RNI88JQL8[5]\ : OR3C - port map(A => \npc_iv_1[5]\, B => \npc_iv_0[5]\, C => - \npc_iv_2[5]\, Y => rpc_3); - - \r.f.pc_RNO[30]\ : OR3C - port map(A => \tmp_m[30]\, B => \pc_1_iv_1[30]\, C => - \un6_fe_npc_m[28]\, Y => \pc_1[30]\); - - \r.e.shcnt_RNI380K7[3]\ : MX2 - port map(A => \shiftin_8[46]\, B => \shiftin_8[38]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[38]\); - - \r.x.data_0_RNO_0[7]\ : AO1B - port map(A => rdatav_0_1_0_iv_4_14, B => mcdo_m_0_21, C => - N_3455, Y => \dco_m_i[119]\); - - \r.e.aluop_RNIAURO4[2]\ : OR2B - port map(A => edata_1_sqmuxa, B => \bpdata[13]\, Y => - \bpdata_i_m_0[13]\); - - \r.e.ctrl.inst_RNIKC1E[20]\ : OR2B - port map(A => \inst_1[20]\, B => \inst[19]\, Y => - ex_sari_1_1_0); - - \r.x.ctrl.inst[28]\ : DFN1E0 - port map(D => \inst_3[28]\, CLK => lclk_c, E => holdn, Q - => \inst[28]\); - - \r.w.s.tt_RNIFNP81[5]\ : OR2B - port map(A => \tt[5]\, B => aluresult_12_sqmuxa, Y => - \tt_m[5]\); - - \r.m.y[11]\ : DFN1E0 - port map(D => \y_1[11]\, CLK => lclk_c, E => holdn, Q => - \y_0[11]\); - - \r.e.invop2_RNIUBQUU1\ : MX2C - port map(A => \un6_ex_add_res_s2[21]\, B => - \un6_ex_add_res_s0[21]\, S => invop2, Y => N_6567); - - \r.e.ctrl.rd_RNIGM7Q[2]\ : XNOR2 - port map(A => \inst_0_RNI2NUM[2]\, B => \rd_1[2]\, Y => - un1_de_ren1_2_0_i_0); - - \r.e.aluop_RNIPS566[0]\ : MX2C - port map(A => N_3577, B => N_3641, S => \aluop_1[0]\, Y => - \logicout[18]\); - - \r.d.inst_0_RNIHDQK[17]\ : MX2C - port map(A => un26_rs1opt, B => N_3525_3, S => rs1mod, Y - => \un3_de_ren1[98]\); - - \r.m.y_RNO_2[12]\ : OR2A - port map(A => \logicout[12]\, B => y14, Y => - \logicout_m[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I27_P0N\ : NOR2 - port map(A => \inst_0_RNI8AJ4[27]\, B => \dpc[29]\, Y => - N440_2); - - \r.e.op2_RNO[19]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[19]\, Y => N_303); - - \r.e.op2_RNI93PP[29]\ : MX2B - port map(A => \op2[29]\, B => N_4276_i, S => ldbp2_0, Y => - \un1_iu0_5[95]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I259_Y_2 : NOR3C - port map(A => I95_un1_Y_1, B => ADD_33x33_fast_I259_Y_0, C - => I155_un1_Y_1, Y => ADD_33x33_fast_I259_Y_2); - - \r.f.pc_RNINH122[6]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[6]\, Y => \xc_trap_address_m[6]\); - - \r.x.result[29]\ : DFN1E0 - port map(D => \maddress[29]\, CLK => lclk_c, E => holdn, Q - => \result_0[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I30_P0N : NOR2 - port map(A => \op2[29]\, B => \un1_iu0_6[29]\, Y => N485_i); - - \r.w.result_RNI2PHF[6]\ : AOI1B - port map(A => \un1_p0_6[358]\, B => d14, C => - \result_m_0_0[6]\, Y => \d_iv_0[6]\); - - \r.m.dci.asi_RNO[1]\ : OR2A - port map(A => \inst_0[23]\, B => \inst_1[6]\, Y => \asi[1]\); - - \r.m.result_RNIGJD4[28]\ : OR2B - port map(A => d13_0, B => \maddress[28]\, Y => - \result_m_0_0[28]\); - - \r.a.ctrl.inst_RNIGH462[31]\ : OR3C - port map(A => N_259, B => cp_disabled_3_sqmuxa_2_0, C => - N_515, Y => cp_disabled_3_sqmuxa_2); - - \r.w.s.tba_RNIF0QP4[10]\ : AOI1B - port map(A => \tba[10]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_2[22]\, Y => \aluresult_1_iv_4[22]\); - - \r.x.ctrl.pc_RNIJPL9[30]\ : MX2 - port map(A => \pc_2[30]\, B => \pc_0[30]\, S => \npc[1]\, Y - => N_3241); - - un6_ex_add_res_d0_ADD_33x33_fast_I48_Y_i : OR2B - port map(A => N467_2, B => N464_2, Y => N_15_0); - - \r.m.y_RNO_4[10]\ : OR2B - port map(A => \y_0[11]\, B => mulstep_1, Y => \y_m_0[11]\); - - \r.a.ctrl.inst_RNIJ25Q1[26]\ : MX2C - port map(A => N_3342, B => N_3343, S => \inst_2[26]\, Y => - N_3344); - - \r.w.s.y[16]\ : DFN1E0 - port map(D => N_3780, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[16]\); - - \r.w.result[13]\ : DFN1E0 - port map(D => \wdata[13]\, CLK => lclk_c, E => holdn, Q => - \result[13]\); - - \r.m.y_RNO[24]\ : AO1C - port map(A => y14_0, B => N_198, C => \y_iv_0_2[24]\, Y => - \y_1[24]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I245_Y : AO1 - port map(A => N676_1, B => N661_0, C => N660_0, Y => N802_0); - - \r.w.result[2]\ : DFN1E0 - port map(D => \wdata[2]\, CLK => lclk_c, E => holdn, Q => - \result[2]\); - - \r.m.y_RNO_2[4]\ : OR2B - port map(A => wy_RNIMKUI, B => \y_2[4]\, Y => \y_m_2[4]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I97_un1_Y : OAI1 - port map(A => N478, B => ADD_33x33_fast_I39_Y_0_a3, C => - N495, Y => I97_un1_Y); - - \r.e.op1_RNI98FC72[4]\ : AO1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[4]\, C - => \d_iv_3[4]\, Y => \d[4]\); - - \r.a.imm[9]\ : DFN1E0 - port map(D => \un3_de_ren1[127]\, CLK => lclk_c, E => holdn, - Q => \imm[9]\); - - \r.a.ctrl.cnt_RNI6P4J3_0[0]\ : NOR3C - port map(A => N_457, B => N_456, C => N_458, Y => - un1_aop2_1_sqmuxa_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I84_Y\ : MAJ3 - port map(A => \dpc[3]\, B => \inst_0_RNI1JUM[1]\, C => N358, - Y => N501_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I39_Y\ : AND2 - port map(A => N428, B => N431, Y => N456); - - wovf_exc_0_sqmuxa_RNO_4 : MX2 - port map(A => \wim_1[0]\, B => \wim_1[4]\, S => \ncwp_3[2]\, - Y => N_3725); - - \r.e.ctrl.inst[14]\ : DFN1E0 - port map(D => \inst_1[14]\, CLK => lclk_c, E => holdn, Q - => \inst[14]\); - - \r.m.dci.asi_RNO[3]\ : OR2A - port map(A => \inst_0[23]\, B => \inst_1[8]\, Y => \asi[3]\); - - \r.e.op2_RNO_1[23]\ : NOR3C - port map(A => \rfo_m_i[55]\, B => \d_1_iv_2[23]\, C => - \op1_m_i[23]\, Y => \d_1_iv_4[23]\); - - \r.e.ctrl.tt_RNO[0]\ : AOI1 - port map(A => \tt_9_1[0]\, B => \tt_RNO_0[0]\, C => annul_2, - Y => \tt_1[0]\); - - \r.w.s.y_RNO[19]\ : MX2 - port map(A => \y_2[19]\, B => \result_0[19]\, S => N_481, Y - => N_3783); - - \r.e.cwp_RNIOJ6CI[1]\ : NOR3C - port map(A => \logicout_m_0[1]\, B => \aluresult_2_iv_3[1]\, - C => \bpdata_m[1]\, Y => \aluresult_2_iv_5[1]\); - - \r.e.aluop_0_RNIKD6R[1]\ : XOR3 - port map(A => \un1_iu0_6[6]\, B => \aluop_0[1]\, C => - \un1_iu0_5[72]\, Y => N_6838); - - \r.e.aluop_RNIAGR04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[5]\, Y => - \bpdata_i_m_2[5]\); - - \r.x.ctrl.pc_RNIAQGF[22]\ : MX2 - port map(A => \pc_0[22]\, B => \pc_2[22]\, S => \npc_0[1]\, - Y => N_3233); - - \r.d.pv_RNI7DFS7\ : OR2A - port map(A => un5_exbpmiss_i_0, B => un1_inst, Y => - annul_current_2_sqmuxa_1); - - \r.x.data_0_RNO_5[5]\ : OR2B - port map(A => rdata_2_sqmuxa, B => data_0_2_13, Y => - \dco_m_i[109]\); - - \r.a.rsel1_RNO[0]\ : OR2A - port map(A => rfe_1_2, B => \rsel1_RNO_0[0]\, Y => - \osel[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I63_Y_0 : OR2 - port map(A => N_53, B => N442_0, Y => N522_1); - - \r.m.y_RNITF5NM[12]\ : NOR3C - port map(A => \aluresult_1_iv_4[12]\, B => - \aluresult_1_iv_3[12]\, C => \logicout_m_0[12]\, Y => - \aluresult_1_iv_6[12]\); - - \r.a.rsel1_0_RNIU65A3[2]\ : NOR3C - port map(A => \d_iv_0_0[5]\, B => N_406, C => - \rsel1_0_RNITC8M2[2]\, Y => \d_iv_0_2[5]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I276_Y_0\ : AX1D - port map(A => N403, B => ADD_30x30_fast_I216_Y_0_a3, C => - ADD_30x30_fast_I276_Y_0_0, Y => \tmp[18]\); - - \r.x.dci.SIGNED_RNIEJUC9\ : MX2 - port map(A => SIGNED, B => SIGNED_0, S => dco_i_2(132), Y - => me_signed_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I320_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[29]\, B => \op2[29]\, Y => - ADD_33x33_fast_I320_Y_0_0); - - \r.e.aluop_1_RNIGPA03[1]\ : MX2C - port map(A => \logicout_4[29]\, B => N_6850, S => N_6866_i, - Y => N_3652); - - \r.f.pc_RNIVNTQA2[10]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[10]\, C => - \pc_m[10]\, Y => \npc_iv_1[10]\); - - \r.d.inst_0_RNIKDP8[17]\ : OR2B - port map(A => I_13_2, B => un26_rs1opt, Y => - \de_raddr1_2[5]\); - - \r.x.rstate_0_RNIGE601[0]\ : MX2 - port map(A => s_3_sqmuxa_0, B => \rstate_0[0]\, S => holdn, - Y => N_6322); - - \r.x.ctrl.tt_RNO[2]\ : MX2C - port map(A => tt_2_sqmuxa_1, B => N_4206, S => N_4210_i_0, - Y => \tt2[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I146_Y : NOR3C - port map(A => N407_2, B => N404_2, C => N543_0, Y => N609_1); - - \r.e.sari_RNIBKJO\ : MX2 - port map(A => sari, B => ex_sari_1, S => ldbp1, Y => - ex_sari_1_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I269_un1_Y : OR2B - port map(A => ADD_33x33_fast_I269_un1_Y_0, B => N676, Y => - I269_un1_Y); - - \r.x.result_RNIQFKA[5]\ : MX2 - port map(A => \result_0[5]\, B => \data_0[5]\, S => ld_0, Y - => \un1_p0_6[357]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I39_Y_0_o3 : MAJ3 - port map(A => N475_1, B => \data_0[27]\, C => - \un1_iu0_6[27]\, Y => N498); - - un6_ex_add_res_d1_ADD_33x33_fast_I69_Y : MAJ3 - port map(A => \op2[12]\, B => \un1_iu0_6[12]\, C => N430, Y - => N528_1); - - \r.e.aluop_0_RNILD6R[2]\ : XA1 - port map(A => \un1_iu0_5[72]\, B => \aluop_0[2]\, C => - \un1_iu0_6[6]\, Y => N_3533); - - \comb.irq_trap.op_gt.un2_irl_0_I_6\ : NOR2A - port map(A => irl_0(3), B => \pil[3]\, Y => \ACT_LT4_E[5]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I262_Y_0\ : XOR2 - port map(A => N501_0, B => ADD_30x30_fast_I262_Y_0_0, Y => - \tmp[4]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I130_Y : NOR2B - port map(A => ADD_33x33_fast_I130_Y_0_0, B => N527_0, Y => - N593_0); - - \r.x.rstate_RNIJKCQ_0[1]\ : OR2A - port map(A => rstate_6314_d_0, B => s_3_sqmuxa_0, Y => - xc_exception_1); - - \r.f.pc_RNO_0[27]\ : NOR3C - port map(A => \un6_ex_add_res_m_1[28]\, B => - \pc_1_iv_0[27]\, C => \tmp_m[27]\, Y => \pc_1_iv_2[27]\); - - \r.e.op1_RNI6A2VM2[8]\ : NOR3C - port map(A => \op1_m_0[8]\, B => \d_iv_2[8]\, C => - \aluresult_m_0[8]\, Y => \d_i[8]\); - - \r.d.inst_0_RNI5NNB[27]\ : MX2C - port map(A => branch_3_i, B => branch_7_i, S => - \inst_0[27]\, Y => N_3347); - - \comb.branch_address.tmp_ADD_30x30_fast_I194_un1_Y\ : AO1C - port map(A => N526, B => I160_un1_Y_i, C => N571_1, Y => - I194_un1_Y); - - \r.w.result_RNIR3RK[7]\ : AOI1B - port map(A => \un1_p0_6[359]\, B => d14_0, C => - \result_m_0_0[7]\, Y => \d_iv_0[7]\); - - \r.x.result_RNIE4MO5[3]\ : OR2A - port map(A => N_3687, B => \bpdata[3]\, Y => - \bpdata_i_m[3]\); - - \r.e.op2_RNIP3HN1[31]\ : OR2B - port map(A => \un1_iu0_5[97]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I204_Y : NOR2 - port map(A => N608_0, B => I204_un1_Y_0, Y => N674); - - \r.m.result_RNICOV6[4]\ : OR2B - port map(A => d13_0, B => \maddress[4]\, Y => - \result_m_0_0[4]\); - - \r.e.op2_RNI8M541[4]\ : OR2B - port map(A => \un1_iu0_5[70]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[4]\); - - \dci.enaddr_1_sqmuxa_1\ : NAND2 - port map(A => trap, B => enaddr_1_sqmuxa_1_1, Y => - enaddr_1_sqmuxa_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I262_Y_0_a3 : AO1C - port map(A => N506, B => N_74_i, C => - ADD_33x33_fast_I262_Y_0_a3_0_0, Y => N_51_i); - - \r.a.ctrl.inst_RNI3RVN5[30]\ : OR3B - port map(A => illegal_inst37_2, B => \y_1[0]\, C => - \inst[30]\, Y => N_452); - - \r.x.ctrl.rd[3]\ : DFN1E0 - port map(D => \rd_0[3]\, CLK => lclk_c, E => holdn, Q => - \rd_2[3]\); - - \r.e.alusel_RNI71FHG[0]\ : AOI1B - port map(A => aluresult_3_sqmuxa_0, B => N_198, C => - \aluresult_1_iv_4[24]\, Y => \aluresult_1_iv_6[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I176_Y : NOR2B - port map(A => N587_0, B => N579_0, Y => N645); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_un1_Y_0 : AND2 - port map(A => N651_0, B => N635_0, Y => - ADD_33x33_fast_I264_un1_Y_0); - - \r.e.op2_RNO_2[25]\ : NOR3C - port map(A => \d_1_iv_1[25]\, B => \d_1_iv_0[25]\, C => - \rfo_m_i[57]\, Y => \d_1_iv_3[25]\); - - \r.e.ctrl.inst[17]\ : DFN1E0 - port map(D => \inst_1[17]\, CLK => lclk_c, E => holdn, Q - => \inst[17]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I31_G0N : OR2A - port map(A => \un1_iu0_6[30]\, B => \data_0[30]\, Y => N487); - - \r.a.rsel1_RNII9L1U4[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[17]\, Y - => \aluresult_m_0[17]\); - - \r.a.ctrl.inst_RNI72LH8[21]\ : OR3B - port map(A => inst_14, B => illegal_inst34_3, C => - illegal_inst35, Y => un1_illegal_inst34); - - \r.a.rsel1_RNI7HGCE2[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[6]\, Y => - \aluresult_m_0[6]\); - - \r.e.op2_RNIBHPA[9]\ : OR2A - port map(A => \un1_iu0_5[75]\, B => \un1_iu0_6[9]\, Y => - \logicout_4[9]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I65_Y : OR2 - port map(A => I65_un1_Y, B => N439, Y => N524); - - \r.e.op1_RNI5AO62[28]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[28]\, C => - \ex_op1_i_m[28]\, Y => \edata2_iv_0[28]\); - - \r.d.cnt_RNIDLUQ[0]\ : AO1 - port map(A => un54_casaen, B => \inst_0_RNIPQUJ[21]\, C => - call_hold7_i, Y => ld_1_sqmuxa); - - \r.a.ctrl.inst_RNIIC131[20]\ : NOR3A - port map(A => \inst_2[20]\, B => N_203, C => N_201, Y => - aluadd_16_sqmuxa_0_a5_1); - - \r.x.ctrl.inst_RNICAF93[20]\ : OA1 - port map(A => y6, B => y10, C => rstate_4_1, Y => - rstate_4_2); - - \r.x.result_RNI6VED[27]\ : MX2 - port map(A => \result_0[27]\, B => \data_0[27]\, S => ld_0, - Y => \un1_p0_6[379]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I206_un1_Y\ : OR2B - port map(A => N598, B => N583, Y => I206_un1_Y); - - \r.m.y_RNI0JS5C[28]\ : NOR3C - port map(A => \aluop_RNI2TEB4[1]\, B => - \aluresult_1_iv_0[28]\, C => \aluop_RNIPR2R4[2]\, Y => - \aluresult_1_iv_4[28]\); - - \r.a.imm[14]\ : DFN1E0 - port map(D => \un3_de_ren1[132]\, CLK => lclk_c, E => holdn, - Q => \imm[14]\); - - \r.d.annul_RNITDPJ03\ : OR2B - port map(A => I_9, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[2]\); - - \r.m.ctrl.rd_RNI2Q6H1[7]\ : XOR2 - port map(A => \rd_0[7]\, B => un1_reg, Y => - \rd_RNI2Q6H1[7]\); - - \r.e.ctrl.tt_RNO_1[3]\ : NOR3A - port map(A => ticc, B => annul_2, C => \tt_4[3]\, Y => - \tt_1[3]\); - - \r.w.result_RNIJSFF[1]\ : AOI1B - port map(A => \un1_p0_6[353]\, B => d14, C => - \result_m_0_0[1]\, Y => \d_iv_0[1]\); - - \r.f.pc_RNO_2[26]\ : OR2B - port map(A => I_166, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[24]\); - - \r.e.ldbp2_RNIB0VAD7\ : OR2B - port map(A => \aluresult_1_iv_9[28]\, B => - \un6_ex_add_res_m[29]\, Y => \aluresult[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I259_un1_Y : OR3C - port map(A => N641, B => N625_0, C => N796_0, Y => - I259_un1_Y_0); - - \r.x.ctrl.pc[5]\ : DFN1E0 - port map(D => \pc_2[5]\, CLK => lclk_c, E => holdn, Q => - \pc_3[5]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I204_Y : AO1 - port map(A => N616, B => N609_1, C => N608, Y => N674_1); - - \r.x.data_0_RNO_2[15]\ : NOR2A - port map(A => data_0_31, B => rdata_5_sqmuxa, Y => - \dco_m_0[127]\); - - \r.a.rsel1_0_RNIC3LJ2[2]\ : OR2B - port map(A => data1(15), B => d11, Y => \rfo_m[15]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I275_Y_0_0\ : XOR2 - port map(A => \dpc[17]\, B => \inst_0[15]\, Y => - ADD_30x30_fast_I275_Y_0_0); - - \r.e.shcnt[0]\ : DFN1E0 - port map(D => N_266_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[0]\); - - \r.e.alucin_RNO_3\ : OR3 - port map(A => \inst_2[21]\, B => \inst[30]\, C => inst_9_3, - Y => N_350); - - \r.x.result_RNIO7KA[4]\ : MX2 - port map(A => \result[4]\, B => \data_0[4]\, S => ld_0, Y - => \un1_p0_6[356]\); - - \r.w.s.tba[11]\ : DFN1E1 - port map(D => \result[23]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[11]\); - - \r.w.result_RNIIRPL[16]\ : AOI1B - port map(A => \un1_p0_6[368]\, B => d14_0, C => - \result_m_0_0[16]\, Y => \d_iv_0[16]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I106_Y : NOR3C - port map(A => N464, B => N467, C => N503_1, Y => N569_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I272_un1_Y : NOR3C - port map(A => N667_0, B => N616_0, C => N651_1, Y => - I272_un1_Y_0); - - \r.f.pc_RNO[2]\ : OR2B - port map(A => \pc_1_iv_2[2]\, B => \un6_fe_npc_m[0]\, Y => - \pc_1[2]\); - - \r.e.op1_RNO[25]\ : MX2C - port map(A => \d_i[25]\, B => \d_i[26]\, S => N_227_0, Y - => \aop1[25]\); - - \r.e.ldbp1_3\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_3); - - \r.e.aluop_RNIFCHBN[0]\ : AOI1B - port map(A => \logicout[11]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[11]\, Y => \aluresult_1_iv_7[11]\); - - un2_rstn_5_0_0_RNIQRRG7 : NAND2 - port map(A => \tmp[8]\, B => un2_rstn_5_0, Y => \tmp_m[8]\); - - \r.e.aluop_RNINKV06[0]\ : MX2C - port map(A => N_3582, B => N_3646, S => \aluop_1[0]\, Y => - \logicout[23]\); - - \r.m.ctrl.inst_RNI5A2S[21]\ : NOR3B - port map(A => \inst[21]\, B => iflush_1, C => \inst_0[24]\, - Y => inst_1); - - \r.x.data_0_RNO_1[25]\ : NOR2A - port map(A => \data_0[25]\, B => ld_0_0, Y => - \data_0_m[25]\); - - \r.f.pc[25]\ : DFN1E0 - port map(D => \pc_1[25]\, CLK => lclk_c, E => holdn, Q => - \fpc[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I27_P0N : AO1A - port map(A => ldbp1_3, B => \op1[26]\, C => \data_0[26]\, Y - => N476_2); - - \r.x.ctrl.pc[30]\ : DFN1E0 - port map(D => \pc_3[30]\, CLK => lclk_c, E => holdn, Q => - \pc_2[30]\); - - \r.e.aluop_RNIKJP04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[0]\, Y => - \bpdata_i_m_2[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I130_Y_0 : OA1 - port map(A => \op2[10]\, B => \un1_iu0_6[10]\, C => N431_1, - Y => ADD_33x33_fast_I130_Y_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I164_Y\ : AO1 - port map(A => N538_2, B => N531, C => N530_1, Y => N590); - - annul_current_3_sqmuxa_1_RNIVK738 : AND2 - port map(A => G_6_0, B => \annul_current_3_sqmuxa_1\, Y => - G_6_1); - - \r.f.pc_RNO[29]\ : OR3C - port map(A => \tmp_m[29]\, B => \pc_1_iv_1[29]\, C => - \un6_fe_npc_m[27]\, Y => \pc_1[29]\); - - \r.a.ctrl.rd[1]\ : DFN1E0 - port map(D => \rd_3[1]\, CLK => lclk_c, E => holdn, Q => - \rd_2[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I293_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[3]\, B => N616, Y => - \un6_ex_add_res_s0[3]\); - - \r.e.aluop_1_RNIK9TF1[1]\ : MX2C - port map(A => \logicout_4[4]\, B => N_6832, S => N_6866_i, - Y => N_3627); - - \r.d.inull_RNO_1\ : OR3A - port map(A => N_96, B => \inst_0[20]\, C => N_150, Y => - N_117); - - \r.x.ctrl.pc_RNIHQHF[16]\ : MX2 - port map(A => \pc_2[16]\, B => \pc[16]\, S => \npc_1[1]\, Y - => N_3227); - - un6_ex_add_res_d0_ADD_33x33_fast_I132_Y : NOR2B - port map(A => N533, B => N529_0, Y => N595_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I19_G0N : NOR3A - port map(A => \op1[18]\, B => ldbp1_3, C => \data_0_0[18]\, - Y => N451_0); - - \r.e.aluop_0_RNI1NHB1[2]\ : XA1C - port map(A => \aluop_0[2]\, B => \un1_iu0_5[90]\, C => - \logicout_5_0_i_a5_0_0[24]\, Y => N_448); - - \r.a.ctrl.cnt[0]\ : DFN1E0 - port map(D => \cnt_2[0]\, CLK => lclk_c, E => holdn, Q => - \cnt_1[0]\); - - \r.w.s.tba_RNI44CA1[3]\ : OR2B - port map(A => \tba[3]\, B => aluresult_12_sqmuxa, Y => - \tba_m[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I158_Y : NOR2B - port map(A => N569_0, B => N561, Y => N627_0); - - \r.m.icc_RNIB6A3[2]\ : XNOR2 - port map(A => \inst_0[28]\, B => \icc_0[2]\, Y => - branch_2_i); - - \r.e.op1_RNIDQEP68[31]\ : NOR3C - port map(A => \op1_m_0[31]\, B => \d_iv_2[31]\, C => - \aluresult_m_0[31]\, Y => \d_i[31]\); - - \r.x.ctrl.tt_RNIBTVQ[3]\ : MX2 - port map(A => \result_0[3]\, B => \tt[3]\, S => tt_i, Y => - N_3322); - - \r.x.result_RNI2PAN3[19]\ : MX2 - port map(A => \op1_RNID1VH[19]\, B => \un1_p0_6[371]\, S - => bpdata6, Y => \bpdata[19]\); - - \r.e.op2_RNO_8[12]\ : OR2A - port map(A => \maddress[12]\, B => d27, Y => - \result_m_i_0[12]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I138_Y : NOR2B - port map(A => ADD_33x33_fast_I138_Y_0, B => N535, Y => - N601_0); - - \r.f.pc_RNO_5[12]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[12]\, Y => \xc_trap_address_m[12]\); - - \r.a.rsel1_0_RNI4V53_1[2]\ : NOR2 - port map(A => d11_0_a5_0, B => \rsel1_0[2]\, Y => d11); - - un6_ex_add_res_d2_ADD_33x33_fast_I8_P0N : AO1A - port map(A => ldbp1_2, B => \op1[7]\, C => \data_0_2[7]\, Y - => N419_0); - - \r.w.s.y_RNO[31]\ : MX2 - port map(A => \y_1[31]\, B => \result_0[31]\, S => N_481, Y - => N_3795); - - \r.e.aluop_1_RNIKL0H[1]\ : XOR3 - port map(A => \un1_iu0_6[4]\, B => \aluop_1[1]\, C => - \un1_iu0_5[70]\, Y => N_6832); - - \r.m.icc_RNIJ0N92[1]\ : NOR2A - port map(A => trap_0_sqmuxa_2, B => trap_0_sqmuxa_1, Y => - un1_trap_0_sqmuxa_0); - - \comb.op_mux.d_1_iv_RNO_7[29]\ : OR3B - port map(A => d29_0, B => \imm[29]\, C => \rsel2[0]\, Y => - \imm_m_i[29]\); - - \r.d.inull_RNO\ : OAI1 - port map(A => N_149, B => de_inull_0_2004_0, C => N_117, Y - => de_inull); - - un6_ex_add_res_d1_ADD_33x33_fast_I123_Y : AO1 - port map(A => N524, B => N521_1, C => N520_1, Y => N586_1); - - \r.x.result_RNILB9B3[4]\ : MX2 - port map(A => \un1_iu0_6[4]\, B => \un1_p0_6[356]\, S => - bpdata6_0_0, Y => \bpdata[4]\); - - \r.e.shcnt_RNI39LF9[2]\ : MX2C - port map(A => \shiftin_11[8]\, B => \shiftin_11[4]\, S => - \ex_shcnt_1_i[2]\, Y => \shiftin_14[4]\); - - \r.e.op2_RNO_5[13]\ : OR2A - port map(A => \maddress[13]\, B => d27, Y => - \result_m_i[13]\); - - \r.d.inst_0_RNO_0[18]\ : MX2 - port map(A => data_0_18, B => \inst_0[18]\, S => - mexc_1_sqmuxa_1_0, Y => N_4618); - - \r.d.cnt_RNIFET3_0[0]\ : NOR2A - port map(A => \cnt_0[1]\, B => \cnt_2[0]\, Y => un11_op); - - \r.a.ctrl.rd[6]\ : DFN1E0 - port map(D => N_37, CLK => lclk_c, E => holdn, Q => \rd[6]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I291_Y_0 : XNOR3 - port map(A => alucin, B => \op2[0]\, C => \un1_iu0_6[0]\, Y - => \un6_ex_add_res_s1_i[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I21_G0N : NOR3A - port map(A => \op1[20]\, B => ldbp1_4, C => \data_0_2[20]\, - Y => N457); - - \r.e.op2_RNO_7[9]\ : NOR2B - port map(A => \result_m_i_0[9]\, B => \cpi_m_i[361]\, Y => - \d_1_iv_1[9]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I318_Y_0 : AX1C - port map(A => I263_un1_Y_i, B => ADD_33x33_fast_I263_Y_1_1, - C => ADD_33x33_fast_I318_Y_0_0, Y => - \un6_ex_add_res_s1_i[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I47_Y_0_o3 : AO1B - port map(A => N467_2, B => N463_2, C => N466_1, Y => N506_0); - - \r.x.intack_RNO\ : NOR3C - port map(A => intack_1, B => intack_0, C => \rstate_0[0]\, - Y => intack); - - \r.x.data_0_RNIFJ9E[25]\ : XOR2 - port map(A => \data_0[25]\, B => invop2_1, Y => N_4272); - - \r.w.result_RNIJ07I[8]\ : AOI1B - port map(A => \un1_p0_6[360]\, B => d14_0, C => - \result_m_0_0[8]\, Y => \d_iv_0[8]\); - - \r.w.s.wim_RNIMSUV3[0]\ : AOI1B - port map(A => \wim[0]\, B => aluresult_13_sqmuxa, C => - \un6_ex_add_res_m[1]\, Y => \aluresult_2_iv_0[0]\); - - \r.w.result_RNI80P1[14]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[14]\, Y - => \result_m_0_0[14]\); - - \r.x.ctrl.pc[3]\ : DFN1E0 - port map(D => \pc_3[3]\, CLK => lclk_c, E => holdn, Q => - \pc_2[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I249_un1_Y : OR2B - port map(A => N669_0, B => N552_0, Y => I249_un1_Y_i); - - \r.e.op1_RNI2NNF[25]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[25]\, Y => - \op1_RNI2NNF[25]\); - - \r.x.result_RNI5R7B3[0]\ : MX2 - port map(A => \un1_iu0_6[0]\, B => \un1_p0_6[352]\, S => - bpdata6_0_0, Y => \bpdata[0]\); - - \r.m.ctrl.pc_RNI0IHF[15]\ : MX2 - port map(A => \pc_3[15]\, B => \pc[15]\, S => \npc_1[1]\, Y - => N_3256); - - \r.w.s.wim_RNIKSJV2[5]\ : NOR2B - port map(A => aluresult_8_sqmuxa_i, B => \wim_m[5]\, Y => - \aluresult_1_iv_0[5]\); - - \r.m.result_RNIMBJN[24]\ : NOR3C - port map(A => \result_m_0[24]\, B => \cpi_m_0[376]\, C => - \result_m_0_0[24]\, Y => \d_iv_1[24]\); - - \r.a.rsel1_0_RNIE8063[2]\ : AOI1B - port map(A => data1(31), B => d11_0, C => \d_iv_1[31]\, Y - => \d_iv_2[31]\); - - \r.x.result_RNIOAHFB[1]\ : NOR2A - port map(A => rst, B => N_3871, Y => \cwp_1[1]\); - - \r.a.rfa2[2]\ : DFN1E0 - port map(D => \inst_0_RNI2NUM[2]\, CLK => lclk_c, E => - holdn, Q => \rfa2[2]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_7\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \r.e.aluop_1_RNIDPJD1[1]\ : XOR3 - port map(A => \op1_RNID1VH[19]\, B => \aluop_1[1]\, C => - \un1_iu0_5[85]\, Y => N_6913); - - \comb.branch_address.tmp_ADD_30x30_fast_I8_P0N\ : OR2 - port map(A => \inst_0[8]\, B => \dpc[10]\, Y => N383); - - \r.d.inst_0_RNIFKEG[25]\ : NOR2A - port map(A => not_valid, B => tmp, Y => - \inst_0_RNIFKEG[25]\); - - \r.m.y_RNO_0[4]\ : NOR3C - port map(A => \y_m_0[4]\, B => \y_m_2[4]\, C => \y_iv_0[4]\, - Y => \y_iv_2[4]\); - - \r.d.inst_0_RNIBGM6[29]\ : OR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_1[0]\, B => - N_3525_3, Y => \de_raddr1_1[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I47_Y_0_o3 : AO1 - port map(A => N467, B => N463_1, C => N466_0, Y => N506); - - \r.w.s.tt[3]\ : DFN1E0 - port map(D => \xc_vectt_1[3]\, CLK => lclk_c, E => N_6747, - Q => \irl[3]\); - - \r.d.pv_RNI2QQLO3\ : NOR3C - port map(A => un2_exbpmiss, B => annul_next_2_sqmuxa_1_6, C - => annul_next_2_sqmuxa_1_8, Y => annul_next_2_sqmuxa_1); - - \r.a.ctrl.inst_RNIJO1S[31]\ : OR2 - port map(A => \inst[31]\, B => N_259, Y => N_363); - - un6_ex_add_res_d0_ADD_33x33_fast_I259_Y_3 : NOR3C - port map(A => I155_un1_Y, B => ADD_33x33_fast_I259_Y_1, C - => I211_un1_Y, Y => ADD_33x33_fast_I259_Y_3); - - \r.e.op1_RNO[22]\ : MX2C - port map(A => \d_i[22]\, B => \d_i[23]\, S => N_227_0, Y - => \aop1[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I16_G0N : OA1 - port map(A => \op1[15]\, B => ldbp1_3, C => \data_0_2[15]\, - Y => N442_1); - - \r.m.ctrl.inst_RNI8BQV3[30]\ : OA1 - port map(A => un5_trap, B => trap_0_sqmuxa_7, C => - me_nullify2_1_2_0, Y => me_nullify2_1_2_1); - - \r.w.s.y_RNO_0[14]\ : NOR2A - port map(A => N_481, B => \result_0[14]\, Y => N_383); - - \comb.branch_address.tmp_ADD_30x30_fast_I71_Y\ : NOR2B - port map(A => N383, B => N380, Y => N488_1); - - \r.a.rsel2_0_RNI7V53_3[0]\ : NOR2A - port map(A => d26_0, B => \rsel2_0[0]\, Y => d25_0); - - \r.a.ctrl.cnt_RNI995L[0]\ : OR2 - port map(A => aluop_0_1_0_a5_1_0_0, B => N_519, Y => - aluop_1_1_0_a5_0); - - \r.w.s.cwp[0]\ : DFN1E0 - port map(D => \cwp_1_0[0]\, CLK => lclk_c, E => holdn, Q - => \cwp[0]\); - - \r.e.aluop_1_RNICGR61[1]\ : OR3A - port map(A => logicout20, B => aluresult_9_sqmuxa_1, C => - miscout69, Y => aluresult_9_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I15_G0N\ : NOR2B - port map(A => \inst_0[15]\, B => \dpc[17]\, Y => N403); - - \r.x.ctrl.rd_RNIPVH6[7]\ : XNOR2 - port map(A => \rd_2[7]\, B => \rd_1[7]\, Y => rd_7_i_0); - - \r.x.ctrl.tt[1]\ : DFN1E0 - port map(D => \tt2[1]\, CLK => lclk_c, E => holdn, Q => - \tt[1]\); - - un6_fe_npc_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \fe_pc[10]\, C => - \fe_pc[11]\, Y => N_113); - - \r.e.shleft_RNI44CC2\ : MX2B - port map(A => \shiftin_5[41]\, B => \shiftin_5[25]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[25]\); - - \r.e.ldbp2_RNIJSVH34\ : OR2A - port map(A => \eaddress[25]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[26]\); - - \r.a.ctrl.inst[8]\ : DFN1E0 - port map(D => \inst_0[8]\, CLK => lclk_c, E => holdn, Q => - \inst[8]\); - - \r.w.result[31]\ : DFN1E0 - port map(D => \wdata[31]\, CLK => lclk_c, E => holdn, Q => - \result[31]\); - - \r.e.op2_RNIAVOP[28]\ : MX2 - port map(A => \op2[28]\, B => N_4275, S => ldbp2_2, Y => - \un1_iu0_5[94]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I129_Y : AO1 - port map(A => N530, B => N527_0, C => - ADD_33x33_fast_I129_Y_0, Y => N592_0); - - \r.x.ctrl.inst_RNILD0E[30]\ : NOR2A - port map(A => \inst_3[31]\, B => \inst_3[30]\, Y => y15); - - \r.a.ctrl.inst[6]\ : DFN1E0 - port map(D => \inst_0[6]\, CLK => lclk_c, E => holdn, Q => - \inst[6]\); - - \r.x.result_RNIDU1O3[15]\ : MX2 - port map(A => \un1_iu0_6[15]\, B => \un1_p0_6[367]\, S => - bpdata6_0_0, Y => \bpdata[15]\); - - \r.w.result[25]\ : DFN1E0 - port map(D => \wdata[25]\, CLK => lclk_c, E => holdn, Q => - \result[25]\); - - \r.m.ctrl.inst_RNIVASI1[30]\ : NOR2A - port map(A => trap_0_sqmuxa_1, B => trap63, Y => - \inst_RNIVASI1[30]\); - - \r.e.aluop_0_RNI5BT8N2[0]\ : NOR3C - port map(A => \shiftin_17_m[29]\, B => - \aluresult_1_iv_7[28]\, C => \shiftin_17_m_0[28]\, Y => - \aluresult_1_iv_9[28]\); - - \r.x.rstate_0_RNI17SD2[0]\ : MX2C - port map(A => N_3405, B => \xc_result[14]\, S => - \rstate_0[0]\, Y => \wdata[14]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I206_Y_0_o3_1_0 : MIN3 - port map(A => \data_0[1]\, B => \un1_iu0_6[1]\, C => N397_1, - Y => ADD_33x33_fast_I206_Y_0_o3_1_0_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I237_Y_0_o3\ : OR3A - port map(A => N_59, B => N427, C => - ADD_30x30_fast_I40_Y_0_a3, Y => N704); - - \r.e.invop2_1_RNI7H6D92\ : MX2C - port map(A => \un6_ex_add_res_s2[23]\, B => - \un6_ex_add_res_s0[23]\, S => invop2_1, Y => N_6569); - - \r.m.ctrl.inst_RNI0P0E[23]\ : OR2B - port map(A => \inst_2[23]\, B => \inst[21]\, Y => - inst_3_2_0); - - \r.f.pc_RNIAKM4[8]\ : OR2A - port map(A => \fpc[8]\, B => rst, Y => \pc_m[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I262_Y_0_a3 : OR3B - port map(A => N503, B => N778_1, C => N_50, Y => N_51_i_1); - - \r.m.casa_RNO\ : NOR3 - port map(A => N_3356_3, B => annul, C => N_3749_2, Y => - mcasa); - - \r.m.y_RNO[31]\ : AO1C - port map(A => y14_0, B => \logicout[31]\, C => \y_iv_2[31]\, - Y => \y_0[31]\); - - \r.e.ldbp2_1_RNI26N5J2\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[8]\, Y => - \aluresult_m_0[8]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I221_un1_Y\ : NOR3B - port map(A => N551, B => N558, C => N543, Y => I221_un1_Y_0); - - \r.d.pv_RNI21DP7\ : OR3A - port map(A => pv, B => ex_bpmiss_1, C => annul_2, Y => - un5_exbpmiss_i_0); - - \r.d.inst_0_RNIOKIB[25]\ : AOI1 - port map(A => un14_op_1, B => un14_op_2, C => \inst_0[25]\, - Y => \inst_0_m_0[26]\); - - \r.x.ctrl.pc_RNIMH971[20]\ : MX2C - port map(A => \un1_p0_6[372]\, B => \pc_2[20]\, S => - s_3_sqmuxa, Y => N_3411); - - \r.f.pc[28]\ : DFN1E0 - port map(D => \pc_1[28]\, CLK => lclk_c, E => holdn, Q => - \fpc[28]\); - - un6_fe_npc_I_101 : AND2 - port map(A => \fe_pc[17]\, B => \fe_pc[18]\, Y => - \DWACT_FINC_E[11]\); - - \r.m.result[14]\ : DFN1E0 - port map(D => \eres2[14]\, CLK => lclk_c, E => holdn, Q => - \maddress[14]\); - - \r.m.y_RNO_4[8]\ : OR2B - port map(A => \y_1[9]\, B => mulstep_0, Y => \y_m_2[9]\); - - \r.e.shleft_1_RNIANU81\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[1]\, S => - shleft_1, Y => \shiftin_5[32]\); - - \r.e.aluop_1_RNI5D5R[1]\ : XOR3 - port map(A => \un1_iu0_6[2]\, B => \aluop_1[1]\, C => - \un1_iu0_5[68]\, Y => N_6907); - - \r.e.op1_RNI57OF[19]\ : NOR2A - port map(A => un17_casaen_0, B => \op1[19]\, Y => - \op1_i_m[19]\); - - \r.a.ctrl.pc[18]\ : DFN1E0 - port map(D => \dpc[18]\, CLK => lclk_c, E => holdn, Q => - \pc[18]\); - - \r.m.result[25]\ : DFN1E0 - port map(D => \eres2[25]\, CLK => lclk_c, E => holdn, Q => - \maddress[25]\); - - \r.e.op1[16]\ : DFN1E0 - port map(D => \aop1[16]\, CLK => lclk_c, E => holdn, Q => - \op1[16]\); - - \r.w.s.y[29]\ : DFN1E0 - port map(D => N_174, CLK => lclk_c, E => holdn, Q => - \y_0[29]\); - - \r.m.ctrl.inst_RNI673A1[23]\ : NOR3 - port map(A => trap_0_sqmuxa_2_2, B => trap27_0, C => - trap_0_sqmuxa_1_2_i, Y => trap27); - - \r.e.shleft_RNIJIFF\ : OR2A - port map(A => \un1_iu0_6[29]\, B => shleft, Y => - \shiftin_5[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I173_Y\ : NOR2 - port map(A => N547, B => N539, Y => N599); - - \r.x.data_0_RNO_5[7]\ : AO1 - port map(A => rdatav_0_1_0_iv_4_22, B => mcdo_m_0_29, C => - rdata_0_sqmuxa, Y => \dco_m_i[127]\); - - \r.x.data_0_RNO[26]\ : OR3 - port map(A => \dco_m_1[122]\, B => \data_0_m[26]\, C => - \data_0_1_4[18]\, Y => \data_0_1[26]\); - - \r.e.jmpl_RNINRDUK\ : OR2B - port map(A => \shiftin_17[5]\, B => aluresult_2_sqmuxa_0, Y - => \shiftin_17_m_0[5]\); - - \r.e.ctrl.pc_RNI20LA2[4]\ : AOI1B - port map(A => \pc[4]\, B => jmpl_0, C => \y_m_1[4]\, Y => - \aluresult_1_iv_2[4]\); - - \r.a.ctrl.pc[27]\ : DFN1E0 - port map(D => \dpc[27]\, CLK => lclk_c, E => holdn, Q => - \pc_0[27]\); - - \r.m.irqen\ : DFN1E0 - port map(D => irqen_0, CLK => lclk_c, E => holdn, Q => - irqen); - - \r.e.op2_RNO_7[20]\ : OA1A - port map(A => \maddress[20]\, B => d27_0, C => - \cpi_m_i[372]\, Y => \d_1_iv_1[20]\); - - \r.m.ctrl.inst_RNI884O1[22]\ : OA1B - port map(A => inst_2_0, B => inst_3_2, C => trap54_1517_0, - Y => \inst_RNI884O1[22]\); - - \r.m.y[2]\ : DFN1E0 - port map(D => \y_1[2]\, CLK => lclk_c, E => holdn, Q => - \y_0[2]\); - - \r.e.ldbp2_RNI2QLA01\ : OR2 - port map(A => aluresult_0_sqmuxa, B => \eaddress[11]\, Y - => \un6_ex_add_res_m[12]\); - - \r.e.aluop_RNISBUL9[1]\ : OA1A - port map(A => N_3974, B => \bpdata[13]\, C => - \bpdata_m_2[5]\, Y => \aluresult_1_iv_4[13]\); - - \r.x.npc_0_RNI9TS61[0]\ : MX2C - port map(A => N_3235, B => N_3265, S => \npc_0[0]\, Y => - \xc_result[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I98_Y : NOR3B - port map(A => N482_1, B => N485, C => N_50_0, Y => N561); - - \r.d.inst_0[29]\ : DFN1 - port map(D => \inst_0_RNO[29]\, CLK => lclk_c, Q => - \inst_0[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I234_un1_Y\ : OR3C - port map(A => N571_1, B => N587, C => N735, Y => I234_un1_Y); - - un2_rstn_5_0_0_RNIJHKER2 : NOR2B - port map(A => \tmp_m[4]\, B => \pc_4_m[4]\, Y => - \npc_iv_0[4]\); - - \un1_r.w.s.cwp_1_SUM1_0\ : XOR2 - port map(A => CO0, B => SUM1_0_0, Y => N_6528); - - \r.f.pc_RNO_1[20]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[20]\, C => - \pc_1_iv_0[20]\, Y => \pc_1_iv_1[20]\); - - \r.e.op1_RNIRSTH[10]\ : MX2 - port map(A => \op1[10]\, B => \data_0[10]\, S => ldbp1_2, Y - => \un1_iu0_6[10]\); - - \r.x.data_0_RNIE343[4]\ : XOR2 - port map(A => \data_0[4]\, B => invop2, Y => N_3308); - - un6_ex_add_res_d1_ADD_33x33_fast_I300_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[9]\, B => \op2[9]\, Y => - ADD_33x33_fast_I300_Y_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I240_un1_Y\ : OR3C - port map(A => N583, B => N599, C => N614, Y => I240_un1_Y); - - \r.x.result_RNIOA2O3[25]\ : MX2C - port map(A => \un1_iu0_6[25]\, B => \un1_p0_6[377]\, S => - bpdata6_0_0, Y => \bpdata[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I213_un1_Y : OR2B - port map(A => N642_1, B => N627, Y => I213_un1_Y_i); - - \comb.branch_address.tmp_ADD_30x30_fast_I49_Y_i\ : OA1 - port map(A => \dpc[20]\, B => \inst_0[18]\, C => N416_2, Y - => N_14); - - \comb.branch_address.tmp_ADD_30x30_fast_I20_G0N\ : NOR2B - port map(A => \inst_0[20]\, B => \dpc[22]\, Y => N418_2); - - \r.e.op2_RNO_8[30]\ : OR3B - port map(A => d29_0, B => \imm[30]\, C => \rsel2[0]\, Y => - \imm_m_i[30]\); - - \r.x.y[17]\ : DFN1E0 - port map(D => \y[17]\, CLK => lclk_c, E => holdn, Q => - \y_2[17]\); - - \r.e.op2_RNO_0[7]\ : OR3C - port map(A => \op1_m_i[7]\, B => \d_1_iv_3[7]\, C => - \aluresult_m_i[7]\, Y => \d_1[7]\); - - \r.e.ctrl.tt_RNO_2[5]\ : NOR3A - port map(A => ticc, B => trap_1, C => \tt_4[3]\, Y => - \tt_9_0_a3_0_1[5]\); - - \r.d.inst_0_RNI5423[23]\ : OR2B - port map(A => \inst_0_0[24]\, B => \inst_0_0[23]\, Y => - N_89); - - un6_ex_add_res_d1_ADD_33x33_fast_I43_Y : MAJ3 - port map(A => \op2[25]\, B => \un1_iu0_6[25]\, C => N469, Y - => N502); - - un6_fe_npc_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \fe_pc[8]\, Y => N_126_0); - - \r.e.ctrl.inst_RNIDC0E[20]\ : OR2 - port map(A => \inst_1[21]\, B => \inst_1[20]\, Y => - aluresult_11_sqmuxa_4); - - \r.w.s.tba_RNIIC7GK[19]\ : NOR3C - port map(A => \bpdata_m_2[7]\, B => \aluresult_1_iv_3[31]\, - C => \aluresult_1_iv_4[31]\, Y => \aluresult_1_iv_6[31]\); - - \r.x.result[28]\ : DFN1E0 - port map(D => \maddress[28]\, CLK => lclk_c, E => holdn, Q - => \result_0[28]\); - - \r.a.rsel2_0_RNI7V53[0]\ : OR2A - port map(A => d28_0_0, B => \rsel2_0[0]\, Y => d27_0); - - \r.e.alusel_RNO[1]\ : NOR3B - port map(A => N_500, B => \alusel_i_0_o5_0[1]\, C => - \alusel_i_0_1[1]\, Y => N_3840); - - un6_ex_add_res_d1_ADD_33x33_fast_I321_Y_0 : AX1C - port map(A => I260_un1_Y, B => ADD_33x33_fast_I260_Y_3_1, C - => ADD_33x33_fast_I321_Y_0_0, Y => - \un6_ex_add_res_s1_i[31]\); - - \r.x.data_0_RNIAF9E[13]\ : XOR2 - port map(A => \data_0[13]\, B => invop2_1, Y => N_4260); - - \r.m.y_RNO_4[1]\ : OR2B - port map(A => \y_0[2]\, B => mulstep_1, Y => N_381); - - \comb.branch_address.tmp_ADD_30x30_fast_I5_P0N\ : OR2 - port map(A => \inst_0[5]\, B => \dpc[7]\, Y => N374); - - \r.x.npc_0_RNI3DS61[0]\ : MX2C - port map(A => N_3224, B => N_3254, S => \npc_0[0]\, Y => - \xc_result[13]\); - - \r.w.s.et_RNIGF034\ : AOI1B - port map(A => et_0_sqmuxa, B => rstate_6314_d, C => et, Y - => et_m); - - \r.e.op1_RNIP3LOJ2[7]\ : NOR3C - port map(A => \op1_m_0[7]\, B => \d_iv_2[7]\, C => - \aluresult_m_0[7]\, Y => \d_i[7]\); - - \r.e.alucin_RNO_4\ : OA1 - port map(A => N_203, B => \inst[30]\, C => \inst[31]\, Y - => cin_iv_i_0); - - \r.m.y_RNO_2[31]\ : OR2B - port map(A => wy_RNIMKUI, B => \y_2[31]\, Y => \y_m_0[31]\); - - \r.a.ctrl.inst_RNIV03A1[21]\ : OR3 - port map(A => N_201, B => N_216, C => N_225, Y => N_602); - - \r.w.s.cwp[1]\ : DFN1E0 - port map(D => \cwp_1[1]\, CLK => lclk_c, E => holdn, Q => - \cwp_0[1]\); - - \r.x.rstate_0_RNI2HJE2[0]\ : MX2C - port map(A => N_3414, B => \xc_result[23]\, S => - \rstate_0[0]\, Y => \wdata[23]\); - - \r.x.ctrl.wicc_RNISNBL\ : NOR3B - port map(A => rst, B => wicc, C => annul_1_0, Y => - icc_0_sqmuxa_1); - - \r.e.op2_RNO_3[28]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[28]\, Y => - \aluresult_m_i[28]\); - - \r.m.result_RNI00P1[16]\ : OR2B - port map(A => d13, B => \maddress[16]\, Y => - \result_m_0[16]\); - - \r.e.bp_RNI77CD\ : NOR3B - port map(A => bp_0, B => \inst_2[28]\, C => annul, Y => - N_482); - - un6_ex_add_res_d1_ADD_33x33_fast_I122_Y : NOR2B - port map(A => ADD_33x33_fast_I122_Y_0, B => N519_1, Y => - N585_0); - - \r.m.y_RNIJ59V2[31]\ : AOI1B - port map(A => \y[31]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[31]\, Y => \aluresult_1_iv_0[31]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I156_Y\ : AOI1 - port map(A => N530_1, B => N523, C => N522, Y => N582_0); - - \r.x.rstate_0_RNI1B24[0]\ : OR2A - port map(A => rst, B => \rstate_0[0]\, Y => N_6358); - - un6_ex_add_res_d1_ADD_33x33_fast_I31_P0N : OR2 - port map(A => \un1_iu0_6[30]\, B => \op2[30]\, Y => N488_0); - - \r.e.aluop_0_RNI5I6K2[1]\ : MX2C - port map(A => \logicout_4[30]\, B => N_6853, S => - N_6866_i_0, Y => N_3653); - - \comb.lock_gen.un1_icc_check5_RNO_3\ : OR3B - port map(A => N_3515_1, B => N_3834_2, C => \inst_0_0[22]\, - Y => icc_check10); - - \r.e.op1_RNI6KL5C5[18]\ : NOR3C - port map(A => \op1_m_0[18]\, B => \d_iv_2[18]\, C => - \aluresult_m_0[18]\, Y => \d_i[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I249_un1_Y : NOR3A - port map(A => N552_1, B => N603_i, C => N611, Y => - I249_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I296_Y_0 : XNOR3 - port map(A => \un1_iu0_6[5]\, B => \op2[5]\, C => N676_1, Y - => \un6_ex_add_res_s1_i[6]\); - - \r.e.op2_RNO_3[15]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[15]\, Y => - \aluresult_m_i[15]\); - - \r.e.ctrl.rd_RNI7QPB1[4]\ : XA1C - port map(A => \un3_de_ren1[95]\, B => \rd_0[4]\, C => - wreg_2, Y => wreg_2_0); - - \r.x.data_0_RNO_1[17]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_2_17, Y => - \dco_m_0[113]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I206_Y_0_a3 : NOR2B - port map(A => N614_2, B => N407_1, Y => - ADD_33x33_fast_I206_Y_0_a3_0); - - \r.a.ctrl.rd_RNO[1]\ : OR2A - port map(A => N_85, B => \inst_0[26]\, Y => \rd_3[1]\); - - \r.d.pc[8]\ : DFN1 - port map(D => \pc_RNO[8]\, CLK => lclk_c, Q => \dpc[8]\); - - \r.e.op1_RNIVM9G[29]\ : OR2B - port map(A => \op1[29]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[29]\); - - \r.e.ldbp2_2_RNIQLAKN3\ : OR2A - port map(A => \eaddress[22]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[23]\); - - \r.e.aluop_RNIEPDN4[2]\ : OR2A - port map(A => aluresult_5_sqmuxa, B => \bpdata[11]\, Y => - \aluop_RNIEPDN4[2]\); - - \r.f.pc_RNO_5[20]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[20]\, Y => \xc_trap_address_m[20]\); - - \r.a.rsel1_0_RNID7LJ2[2]\ : OR2B - port map(A => data1(23), B => d11_0, Y => \rfo_m[23]\); - - \r.m.ctrl.annul_RNIE1G3\ : OR2A - port map(A => \rstate_0[0]\, B => annul_5, Y => - annul_1tt_N_5); - - \r.x.data_0_RNO[27]\ : OR3 - port map(A => \dco_m_1[123]\, B => \data_0_m[27]\, C => - \data_0_1_4[18]\, Y => \data_0_1[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I288_Y_0_0\ : XOR2 - port map(A => \dpc[30]\, B => \inst_0_1[30]\, Y => - ADD_30x30_fast_I288_Y_0_0); - - \r.a.rsel1_RNIU3DLA2[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[5]\, Y => - N_408); - - \r.a.ctrl.inst[7]\ : DFN1E0 - port map(D => \inst_0[7]\, CLK => lclk_c, E => holdn, Q => - \inst[7]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I266_Y_0\ : XOR2 - port map(A => N612, B => ADD_30x30_fast_I266_Y_0_0, Y => - \tmp[8]\); - - \r.f.pc_RNO_3[18]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[18]\, C => - \xc_trap_address_m[18]\, Y => \pc_1_iv_0[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I153_Y\ : NOR2B - port map(A => N527_2, B => N519, Y => N579); - - \r.x.ctrl.wicc_RNISNBL_0\ : NOR3A - port map(A => rst, B => wicc, C => annul_1_0, Y => - icc_2_sqmuxa_1); - - \r.e.aluop_0_RNINM3Q5[0]\ : MX2C - port map(A => N_3584, B => N_3648, S => \aluop_0[0]\, Y => - \logicout[25]\); - - \r.m.icc_RNO_0[2]\ : MX2C - port map(A => N_4182, B => \icc_0[2]\, S => wicc_3, Y => - N_4187); - - \r.e.ctrl.rd_RNIVO2A1[1]\ : XA1A - port map(A => \un3_de_ren1[92]\, B => \rd[1]\, C => - un2_rs1_1_2_i_0, Y => wreg_2_2); - - \r.m.ctrl.pc[18]\ : DFN1E0 - port map(D => \pc_0[18]\, CLK => lclk_c, E => holdn, Q => - \pc_3[18]\); - - \r.x.ctrl.pc_RNIF9971[10]\ : MX2C - port map(A => \un1_p0_6[362]\, B => \pc[10]\, S => - s_3_sqmuxa_0, Y => N_3401); - - \r.e.ctrl.tt_RNO[2]\ : NOR3 - port map(A => N_4039, B => \tt_0[2]\, C => N_4033_i, Y => - \tt_1[2]\); - - \r.e.ctrl.annul_RNI5L7FE1_0\ : NOR3 - port map(A => un2_rstn_5_0_i, B => un12_de_hold_pc, C => - de_hold_pc_1_0, Y => un2_rstn_3_0); - - \r.m.result_RNI52TD3[22]\ : NOR3C - port map(A => \d_iv_0[22]\, B => \result_m_0[22]\, C => - \rfo_m[22]\, Y => \d_iv_2[22]\); - - \r.w.s.icc_RNO_1[3]\ : OR2B - port map(A => icc_0_sqmuxa, B => \icc_2[3]\, Y => - \icc_m_0[3]\); - - \r.m.result_RNO[27]\ : MX2 - port map(A => \aluresult[27]\, B => \op1[27]\, S => - un17_casaen_0_1, Y => \eres2[27]\); - - \r.a.ctrl.inst_RNI6C0E[21]\ : OR2B - port map(A => \inst[30]\, B => \inst_2[21]\, Y => N_519); - - un6_ex_add_res_d1_ADD_33x33_fast_I1_P0N : OR2 - port map(A => \un1_iu0_6[0]\, B => \op2[0]\, Y => N398_0); - - \r.d.annul_RNI35C5\ : NOR2 - port map(A => annul_1, B => un54_casaen, Y => ldchkra_0); - - \r.d.inst_0_RNIBO9C[23]\ : OR3B - port map(A => \inst_0_0[22]\, B => icc_check7_2, C => - \inst_0_0[23]\, Y => icc_check7_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_Y_1 : AOI1B - port map(A => N652, B => N637_0, C => - ADD_33x33_fast_I265_Y_0, Y => ADD_33x33_fast_I265_Y_1_0); - - \r.w.s.tba_RNIFA6JB[9]\ : NOR3C - port map(A => \aluresult_1_iv_2[21]\, B => \tba_m[9]\, C - => \aluresult_1_iv_3[21]\, Y => \aluresult_1_iv_5[21]\); - - \r.w.result_RNI3I2L[27]\ : AOI1B - port map(A => \un1_p0_6[379]\, B => d14_0, C => - \result_m_0_0[27]\, Y => \d_iv_0[27]\); - - \r.d.inull_RNIFV6VG2_0\ : OA1B - port map(A => holdn, B => \de_hold_pc_1\, C => mds, Y => - inull_RNIFV6VG2_0); - - \r.d.inst_0_RNI5C23_0[31]\ : OR2A - port map(A => \inst_0[30]\, B => \inst_0[31]\, Y => N_85); - - \comb.branch_address.tmp_ADD_30x30_fast_I51_Y\ : OA1 - port map(A => \dpc[20]\, B => \inst_0[18]\, C => N410, Y - => N468); - - \r.x.ctrl.annul_RNI2ROB\ : OR2A - port map(A => \un1_p0_6[349]\, B => annul_0, Y => annul_1_0); - - \r.a.ctrl.cnt_RNI3T47[0]\ : OR2A - port map(A => \cnt_1[0]\, B => \cnt_2[1]\, Y => - aluop_0_1_0_a5_1_0_0); - - \r.a.ctrl.inst_RNIH95V1[20]\ : AOI1B - port map(A => inst_32_1, B => inst_32_0, C => inst_21, Y - => illegal_inst34_0); - - \r.e.op2_RNIRI992[11]\ : AOI1B - port map(A => \un1_iu0_5[77]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[11]\); - - \r.x.ctrl.pc_RNIMR431[7]\ : MX2C - port map(A => \un1_p0_6[359]\, B => \pc[7]\, S => - s_3_sqmuxa_0, Y => N_3398); - - \r.w.result_RNI7PA4[0]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[0]\, Y - => \result_m_0_0[0]\); - - \un1_r.w.s.cwp_1_SUM1_0_0\ : XOR2 - port map(A => et_RNI1BRF2, B => \cwp_0[1]\, Y => SUM1_0_0); - - \r.d.inst_0[23]\ : DFN1 - port map(D => \inst_0_RNO[23]\, CLK => lclk_c, Q => - \inst_0_0[23]\); - - \r.e.shcnt_RNILEIO4[3]\ : MX2 - port map(A => \shiftin_8[22]\, B => \shiftin_8[14]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[14]\); - - \r.e.ldbp2_2_RNIFB78T1\ : OR2A - port map(A => annul_RNI5L7FE1, B => \eaddress[6]\, Y => - ldbp2_2_RNIFB78T1); - - \r.d.inst_0_RNI4EL7[30]\ : AO1 - port map(A => fins_0_a3_0, B => N_3834_2, C => \inst_0[30]\, - Y => N_3832); - - un6_ex_add_res_d2_ADD_33x33_fast_I263_Y : OR2 - port map(A => I263_un1_Y_0, B => ADD_33x33_fast_I263_Y_1_0, - Y => N772_0); - - \r.a.ticc\ : DFN1E0 - port map(D => ticc_exception, CLK => lclk_c, E => holdn, Q - => ticc); - - \r.a.rsel2_RNI9LB[1]\ : NOR2A - port map(A => \rsel2[1]\, B => \rsel2[2]\, Y => d28_0_0); - - \r.m.ctrl.cnt_RNIQA5L[0]\ : OR3 - port map(A => \cnt_1[1]\, B => \cnt_0[0]\, C => un5_trap, Y - => trap_1_sqmuxa_1); - - \r.e.op2_RNO_7[31]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[383]\, - Y => \cpi_m_i[383]\); - - \r.e.ctrl.rd[1]\ : DFN1E0 - port map(D => \rd_2[1]\, CLK => lclk_c, E => holdn, Q => - \rd[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I124_Y : NOR2 - port map(A => N525_0, B => N521_0, Y => N587_1); - - \r.m.ctrl.rd[6]\ : DFN1E0 - port map(D => \rd_0[6]\, CLK => lclk_c, E => holdn, Q => - \rd_1[6]\); - - \r.e.op2_RNO_5[22]\ : AOI1B - port map(A => \result[22]\, B => d31_0, C => \imm_m_i[22]\, - Y => \d_1_iv_0[22]\); - - \r.e.aluop_0_RNIMMJ24[0]\ : OR2B - port map(A => \logicout[3]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I307_Y_0_1 : XNOR2 - port map(A => \un1_iu0_6[16]\, B => \data_0[16]\, Y => - \un6_ex_add_res_s0_1[17]\); - - \r.m.ctrl.pc_RNISHGF[31]\ : MX2 - port map(A => \pc_3[31]\, B => \pc_0[31]\, S => \npc_1[1]\, - Y => N_3272); - - \r.e.ctrl.inst_RNILG1E[21]\ : NOR2 - port map(A => \inst[19]\, B => \inst_1[21]\, Y => - aluresult_13_sqmuxa_0_0); - - \r.w.s.dwt_RNI7TJM3\ : NOR2B - port map(A => \aluresult_1_iv_0[14]\, B => \ex_op2_m[14]\, - Y => \aluresult_1_iv_1[14]\); - - \r.e.shcnt_RNIOC3GA[2]\ : MX2C - port map(A => \shiftin_11[11]\, B => \shiftin_11[7]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[7]\); - - \r.f.pc_RNO_1[17]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[17]\, C => - \pc_1_iv_0[17]\, Y => \pc_1_iv_1[17]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I250_Y_0_a3 : NOR2B - port map(A => N672_1, B => N419, Y => - ADD_33x33_fast_I250_Y_0_a3_0); - - \r.e.shleft_0_RNIANBQ1\ : MX2A - port map(A => \shiftin_5[17]\, B => shleft_0_RNIU2BG, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I140_Y : OR2B - port map(A => N541, B => N537_2, Y => N603_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I266_Y_0_o3 : OR2 - port map(A => N506_0, B => N_74, Y => N778_0); - - \r.w.s.tba[19]\ : DFN1E1 - port map(D => \result_0[31]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[19]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I17_P0N\ : OR2 - port map(A => \inst_0[17]\, B => \dpc[19]\, Y => N410); - - \r.f.pc_RNO_1[9]\ : NOR2B - port map(A => \xc_trap_address_m[9]\, B => \pc_4_m[9]\, Y - => \pc_1_iv_0[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I100_Y_0\ : MIN3 - port map(A => \dpc[23]\, B => \un1_p0_6_0[60]\, C => N418_2, - Y => ADD_30x30_fast_I100_Y_0); - - \r.e.ldbp2_RNIIHL2K3\ : OR3C - port map(A => \aluresult_1_iv_7[13]\, B => - \shiftin_17_m_0[13]\, C => \un6_ex_add_res_m[14]\, Y => - \aluresult[13]\); - - \r.e.aluop_RNIPR2R4[2]\ : OR2A - port map(A => aluresult_5_sqmuxa, B => \bpdata[12]\, Y => - \aluop_RNIPR2R4[2]\); - - \r.d.inst_0[24]\ : DFN1 - port map(D => \inst_0_RNO[24]\, CLK => lclk_c, Q => - \inst_0_0[24]\); - - \r.e.op1_RNISUNP1[9]\ : AO1A - port map(A => \op1[9]\, B => \un17_casaen_0_0\, C => - \ex_op1_i_m[9]\, Y => \edata2_0_iv_0[9]\); - - \r.d.inull_RNIBBMHS\ : NOR2A - port map(A => \hold_pc_7\, B => ldlock, Y => un18_hold_pc); - - \r.m.icc_RNO_22[2]\ : NOR2 - port map(A => \logicout[19]\, B => \logicout[25]\, Y => - icc_0_sqmuxa_1_8); - - \r.e.op1_RNIL20JT1[0]\ : OR2B - port map(A => \d_1_iv_4[0]\, B => \aluresult_m_i[0]\, Y => - \d_1[0]\); - - \r.d.cwp_RNO[2]\ : MX2 - port map(A => N_4229, B => \cwp_1_0[2]\, S => N_6358, Y => - \cwp_1[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I71_Y_0 : AO1B - port map(A => N431_2, B => N427_2, C => N430_1, Y => N530_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I11_G0N : OA1 - port map(A => \op1[10]\, B => ldbp1_2, C => \data_0[10]\, Y - => N427_2); - - \r.a.rsel2_RNI7V53_0[1]\ : NOR3B - port map(A => \rsel2[2]\, B => \rsel2[1]\, C => - \rsel2_0[0]\, Y => d31_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I0_CO1\ : NOR2B - port map(A => \inst_0_RNI0FUM[0]\, B => \dpc[2]\, Y => N358); - - \r.f.pc_RNO_1[26]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[26]\, C => - \pc_1_iv_0[26]\, Y => \pc_1_iv_1[26]\); - - \r.d.pc_RNO[13]\ : MX2 - port map(A => \fpc[13]\, B => \dpc[13]\, S => N_6763_i_0, Y - => \pc_RNO[13]\); - - \r.d.inst_0_RNIJVPR[14]\ : MX2B - port map(A => \inst_0[14]\, B => \inst_0_m_0[26]\, S => - rs1mod, Y => \rs1_iv_i_0[0]\); - - \r.d.inst_0_RNO_0[17]\ : MX2 - port map(A => data_0_0_17, B => \inst_0[17]\, S => - mexc_1_sqmuxa_1_0, Y => N_4617); - - \r.m.y_RNO_0[22]\ : AOI1B - port map(A => wy_1_0, B => \y_0[22]\, C => \y_m[22]\, Y => - \y_iv_1[22]\); - - \r.e.shleft_1_RNIS94T2\ : MX2C - port map(A => \shiftin_5[56]\, B => \shiftin_5[40]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[40]\); - - \r.e.op2_RNI3B4V1[20]\ : AOI1B - port map(A => \un1_iu0_5[86]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[20]\); - - \r.e.op2_RNIBGNB1[17]\ : OR2A - port map(A => \un1_iu0_5[83]\, B => \un1_iu0_6[17]\, Y => - \logicout_4[17]\); - - \r.x.data_0[15]\ : DFN1E0 - port map(D => \data_0_1[15]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_2[15]\); - - \r.e.shcnt_RNIFN69J[1]\ : MX2C - port map(A => \shiftin_14[5]\, B => \shiftin_14[3]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[3]\); - - \r.d.inst_0_RNI6MTD1[4]\ : NOR2 - port map(A => \inst_0_RNI2NUM[2]\, B => \inst_0_RNI4VUM[4]\, - Y => un1_rs1_1); - - \r.w.s.pil[0]\ : DFN1E0 - port map(D => \result[8]\, CLK => lclk_c, E => N_6699, Q - => \pil[0]\); - - \r.w.result_RNIKJD4[22]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[22]\, - Y => \result_m_0_0[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I61_Y : MIN3 - port map(A => \data_0[16]\, B => \un1_iu0_6[16]\, C => - N442_1, Y => N520_2); - - \r.d.inst_0_RNINSV2_0[31]\ : NOR2 - port map(A => \inst_0[31]\, B => annul_1, Y => N_3033_1_i); - - \r.d.inst_0_RNIA423[25]\ : NOR2 - port map(A => \inst_0[25]\, B => \inst_0[27]\, Y => - annul_next_1_sqmuxa_1_1); - - \r.a.imm_RNO[21]\ : MX2 - port map(A => \inst_0[11]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[139]\); - - \r.x.result_RNIFC6E[11]\ : MX2 - port map(A => \result_0[11]\, B => \data_0_2[11]\, S => - ld_4, Y => \un1_p0_6[363]\); - - \r.x.result[13]\ : DFN1E0 - port map(D => \maddress[13]\, CLK => lclk_c, E => holdn, Q - => \result_0[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I18_P0N : OR2 - port map(A => \un1_iu0_6[17]\, B => \op2[17]\, Y => N449_1); - - \r.m.ctrl.trap\ : DFN1E0 - port map(D => trap_0, CLK => lclk_c, E => holdn, Q => - trap_2); - - \r.e.shcnt[3]\ : DFN1E0 - port map(D => N_269_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[3]\); - - \r.x.ctrl.annul_RNI5S7L\ : NOR2 - port map(A => \rstate_d[2]\, B => xc_wreg9, Y => s_3_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I263_un1_Y : OR3C - port map(A => N649_1, B => N633_1, C => N808_0, Y => - I263_un1_Y_i); - - \r.e.op2_RNO_6[6]\ : OR2B - port map(A => data2(6), B => d25_0, Y => \rfo_m_i[38]\); - - \r.w.s.y[20]\ : DFN1E0 - port map(D => N_3784, CLK => lclk_c, E => N_6922_i_0, Q => - \y[20]\); - - \r.a.nobp_RNO\ : OAI1 - port map(A => N_150, B => \inst_0[19]\, C => nobp_RNO_0, Y - => nobp_1); - - \r.x.ctrl.annul_RNI5S7L_0\ : NOR2 - port map(A => \rstate_d[2]\, B => xc_wreg9, Y => - s_3_sqmuxa_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I36_Y : NOR2A - port map(A => N482, B => N485_i_0, Y => N495_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I4_P0N : OR2 - port map(A => \un1_iu0_6[3]\, B => \op2[3]\, Y => N407); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_Y_0\ : NOR3B - port map(A => I36_un1_Y_i, B => I92_un1_Y, C => N433, Y => - ADD_30x30_fast_I235_Y_0); - - \r.m.y_RNO_4[5]\ : OR3A - port map(A => \y_1[5]\, B => wy_3, C => wy_1_0_1, Y => - \y_m_2[5]\); - - \r.e.op1_RNIPD7JF[31]\ : NOR3B - port map(A => \aluop_RNIESJP4[2]\, B => \edata2_iv_1[31]\, - C => \bpdata_i_m_2[7]\, Y => edata2_iv_i_0(31)); - - \comb.branch_address.tmp_ADD_30x30_fast_I273_Y_0_0\ : XOR2 - port map(A => \dpc[15]\, B => \inst_0[13]\, Y => - ADD_30x30_fast_I273_Y_0_0); - - \r.f.pc_RNO_6[31]\ : MX2 - port map(A => \fpc[31]\, B => \eaddress[31]\, S => jump_0, - Y => N_4074); - - \r.f.pc_RNO_1[2]\ : NOR2B - port map(A => \xc_trap_address_m[2]\, B => \pc_4_m[2]\, Y - => \pc_1_iv_0[2]\); - - \r.e.shcnt_RNIOC6GJ[1]\ : MX2C - port map(A => \shiftin_14[4]\, B => \shiftin_14[2]\, S => - \ex_shcnt_1_i[1]\, Y => \shiftin_17[2]\); - - \r.e.ldbp2_2_RNIGN3I1\ : OR2A - port map(A => \eaddress[0]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[1]\); - - \r.e.jmpl_RNIRC5C\ : OR2 - port map(A => jmpl, B => aluresult12, Y => - aluresult_0_sqmuxa_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I287_Y_0\ : XOR2 - port map(A => N698, B => ADD_30x30_fast_I287_Y_0_0, Y => - \tmp[29]\); - - \r.e.op2_RNO_1[18]\ : OR2B - port map(A => \op1[18]\, B => un14_casaen_s1, Y => - \op1_m_i[18]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I261_Y_1 : NOR3B - port map(A => I99_un1_Y, B => I159_un1_Y, C => N496, Y => - ADD_33x33_fast_I261_Y_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I302_Y_0 : XNOR3 - port map(A => \un1_iu0_6[11]\, B => \op2[11]\, C => N808_0, - Y => \un6_ex_add_res_s1_i[12]\); - - \r.d.annul_RNI6C772\ : MX2 - port map(A => hold_pc_0_sqmuxa, B => N_108, S => - branch_1_sqmuxa_i, Y => branch_0); - - \r.x.rstate_RNI5S7L_0[1]\ : NOR2 - port map(A => \rstate_d[2]\, B => annul_1_0, Y => - xc_wreg_0_sqmuxa); - - \r.e.op2[28]\ : DFN1E0 - port map(D => N_312, CLK => lclk_c, E => holdn, Q => - \op2[28]\); - - \r.x.data_0_RNICN9E[30]\ : XOR2 - port map(A => \data_0[30]\, B => invop2_0, Y => N_4277); - - un6_ex_add_res_d2_ADD_33x33_fast_I300_Y_0 : AX1D - port map(A => I249_un1_Y, B => N668_0, C => - \un6_ex_add_res_s2_1[10]\, Y => \un6_ex_add_res_s2[10]\); - - \r.e.ctrl.pc[5]\ : DFN1E0 - port map(D => \pc_0[5]\, CLK => lclk_c, E => holdn, Q => - \pc[5]\); - - \r.e.aluop_RNIJV794[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[29]\, Y => - \bpdata_i_m[29]\); - - \r.e.aluop_1_RNID9JD1[1]\ : XOR3 - port map(A => \un1_iu0_6[26]\, B => \aluop_1[1]\, C => - \un1_iu0_5[92]\, Y => N_6859); - - \r.m.ctrl.inst_RNI7P1E[23]\ : OR2B - port map(A => \inst_2[23]\, B => \inst_3[19]\, Y => - trap27_0); - - \r.e.jmpl_RNICFD1K\ : OR2B - port map(A => \shiftin_17[3]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[3]\); - - \r.f.pc_RNO_7[28]\ : MX2 - port map(A => \fpc[28]\, B => \tba[16]\, S => rstate_6314_d, - Y => \xc_trap_address[28]\); - - \r.e.alucin_RNO_2\ : OR2A - port map(A => N_207, B => N_518, Y => alucin_RNO_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I18_G0N : NOR2B - port map(A => \un1_iu0_6[17]\, B => \op2[17]\, Y => N448_0); - - \r.e.aluop_RNIB1134[1]\ : OR2B - port map(A => \bpdata[1]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[1]\); - - \comb.v.x.data_0_1_1_iv_RNO_0[31]\ : AO1A - port map(A => ld_0_0, B => \data_0_0[31]\, C => - \dco_m_1[127]\, Y => \data_0_1_1_iv_0[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I12_G0N : NOR2B - port map(A => \un1_iu0_6[11]\, B => \op2[11]\, Y => N430); - - \r.f.pc_RNO_5[26]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[26]\, Y => \xc_trap_address_m[26]\); - - \r.x.data_0_RNO[24]\ : OR3A - port map(A => \data_0_1_1_iv_1[24]\, B => \rdata_13_m_9[8]\, - C => \data_0_1_1[16]\, Y => \data_0_1[24]\); - - \r.a.rfa1[1]\ : DFN1E0 - port map(D => \un3_de_ren1[92]\, CLK => lclk_c, E => holdn, - Q => \rfa1[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I304_Y_0 : XOR3 - port map(A => \un1_iu0_6[13]\, B => \op2[13]\, C => N802_0, - Y => \un6_ex_add_res_s1[14]\); - - \r.x.ctrl.pc[19]\ : DFN1E0 - port map(D => \pc_2[19]\, CLK => lclk_c, E => holdn, Q => - \pc_0[19]\); - - \r.e.ctrl.annul_RNIMA264_0\ : AOI1 - port map(A => jump_1_sqmuxa_1_i_0, B => jump_0_sqmuxa_1_i_0, - C => annul, Y => jump); - - \r.a.ctrl.inst[19]\ : DFN1E0 - port map(D => \inst_0[19]\, CLK => lclk_c, E => holdn, Q - => \inst_2[19]\); - - \r.f.pc_RNO_4[15]\ : MX2 - port map(A => I_77, B => N_4058, S => bpmiss_1_i_0_0, Y => - \pc_4[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I78_Y : OA1 - port map(A => \op2[8]\, B => \un1_iu0_6[8]\, C => N419_1, Y - => N537_1); - - \r.m.result_RNO[14]\ : MX2 - port map(A => \aluresult[14]\, B => \op1[14]\, S => - un17_casaen_0_2, Y => \eres2[14]\); - - \r.m.ctrl.rett_RNO\ : NOR2A - port map(A => rett_3, B => annul, Y => rett_1_3); - - un6_ex_add_res_d0_ADD_33x33_fast_I120_Y : NOR2B - port map(A => N521, B => N517, Y => N583_0); - - \r.x.npc_RNI6T411[0]\ : MX2C - port map(A => N_3230, B => N_3260, S => \npc[0]\, Y => - \xc_result[19]\); - - \r.e.shleft_RNID1G13\ : MX2 - port map(A => \shiftin_5[48]\, B => \shiftin_5[32]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[32]\); - - \r.e.shleft_0_RNIFRBQ1\ : MX2C - port map(A => \shiftin_5[22]\, B => \shiftin_5[6]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[6]\); - - \r.e.op2_RNO_2[23]\ : OR2B - port map(A => data2(23), B => d25, Y => \rfo_m_i[55]\); - - \r.x.data_0_RNO[28]\ : OR3 - port map(A => \dco_m_1[124]\, B => \data_0_m[28]\, C => - \data_0_1_4[18]\, Y => \data_0_1[28]\); - - \r.x.ctrl.tt_RNO_1[3]\ : MX2C - port map(A => irl_0(3), B => \tt_2[3]\, S => tt_0_sqmuxa, Y - => N_4207); - - \r.w.s.et_RNIM09S\ : NOR3A - port map(A => y15, B => error_1_sqmuxa, C => annul_1_0, Y - => rstate_4_1); - - \comb.ld_align.rdata199\ : OR2A - port map(A => \me_size_1[0]\, B => \me_size_1[1]\, Y => - rdata199); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y_3 : AOI1B - port map(A => N642, B => N627_0, C => - ADD_33x33_fast_I260_Y_2, Y => ADD_33x33_fast_I260_Y_3); - - un6_ex_add_res_d0_ADD_33x33_fast_I135_Y : AO1 - port map(A => N536_0, B => N533, C => N532, Y => N598_0); - - \r.m.y_RNO_4[22]\ : OR2B - port map(A => \y[23]\, B => mulstep_0, Y => \y_m[23]\); - - \r.e.op1_RNIU77Q34[14]\ : NOR3C - port map(A => \op1_m_0[14]\, B => \d_iv_2[14]\, C => - \aluresult_m_0[14]\, Y => \d_i[14]\); - - \r.x.ctrl.inst_RNI05531[27]\ : NOR3A - port map(A => y_0_sqmuxa_2, B => \inst[28]\, C => - \inst[27]\, Y => y_0_sqmuxa_3); - - \r.a.ctrl.rd_RNO[4]\ : NOR2A - port map(A => \DWACT_ADD_CI_0_partial_sum_2[0]\, B => - un3_reg, Y => N_33); - - \r.a.ctrl.wreg_RNO_3\ : AO1A - port map(A => call_hold5_0, B => un3_op2, C => - write_reg_4_sqmuxa, Y => un1_ld_1_sqmuxa_1_0); - - \r.e.aluop_RNIESJP4[2]\ : OR2A - port map(A => edata_1_sqmuxa, B => \bpdata[15]\, Y => - \aluop_RNIESJP4[2]\); - - \r.a.ctrl.inst_RNI9G0L[20]\ : OR2 - port map(A => \inst_2[20]\, B => N_201, Y => N_204); - - \r.m.ctrl.inst[28]\ : DFN1E0 - port map(D => \inst_2[28]\, CLK => lclk_c, E => holdn, Q - => \inst_3[28]\); - - \r.e.op1_RNITE9G[27]\ : OR2B - port map(A => \op1[27]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[27]\); - - \r.e.op1[9]\ : DFN1E0 - port map(D => \aop1[9]\, CLK => lclk_c, E => holdn, Q => - \op1[9]\); - - \r.a.rfa1[3]\ : DFN1E0 - port map(D => \un3_de_ren1[94]\, CLK => lclk_c, E => holdn, - Q => \rfa1[3]\); - - \r.w.s.y[26]\ : DFN1E0 - port map(D => N_3790, CLK => lclk_c, E => N_6922_i, Q => - \y[26]\); - - \r.d.cnt_RNO_0[0]\ : OR3 - port map(A => ldlock, B => annul_1, C => hold_pc_0_sqmuxa_1, - Y => cnt_2_sqmuxa_0); - - \r.x.data_0_RNO[8]\ : OR3B - port map(A => \data_0_1_0_iv_1[8]\, B => \dco_m_0_i[104]\, - C => \data_0_1_1[12]\, Y => \data_0_1[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I266_Y_0_a3 : NAND2 - port map(A => N782, B => N_15_i, Y => N_74_i); - - \r.x.dci.SIGNED_RNI2CVK71\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_14, B => mcdo_m_0_21, C => - me_signed_1, Y => \rdata_9_m_0[8]\); - - un6_fe_npc_I_179 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[20]\, Y => \DWACT_FINC_E[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I82_Y : AND2 - port map(A => N413_0, B => N416_0, Y => N541_0); - - \r.d.inst_0[11]\ : DFN1 - port map(D => \inst_0_RNO[11]\, CLK => lclk_c, Q => - \inst_0[11]\); - - \r.e.jmpl_RNIN50TT_0\ : OR2B - port map(A => \shiftin_17[26]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[26]\); - - \r.d.pc[16]\ : DFN1 - port map(D => \pc_RNO[16]\, CLK => lclk_c, Q => \dpc[16]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I14_P0N : OR2 - port map(A => \un1_iu0_6[13]\, B => \op2[13]\, Y => N437_0); - - \r.e.aluadd\ : DFN1E0 - port map(D => un1_aop2_1_sqmuxa, CLK => lclk_c, E => holdn, - Q => aluadd); - - \r.e.shleft_0_RNI6FFJ3\ : MX2 - port map(A => \shiftin_5[57]\, B => \shiftin_5[41]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[41]\); - - \r.e.ctrl.inst_RNISSQF[25]\ : XAI1 - port map(A => \inst_2[25]\, B => \inst_1[27]\, C => - \icc_0[2]\, Y => N_6695_i); - - \r.d.inst_0[3]\ : DFN1 - port map(D => \inst_0_RNO[3]\, CLK => lclk_c, Q => - \inst_0[3]\); - - \r.x.ctrl.wy_RNIRE1D_0\ : OR2A - port map(A => wy_2, B => wy_1, Y => wy_1_0_1); - - \r.a.ctrl.inst[11]\ : DFN1E0 - port map(D => \inst_0[11]\, CLK => lclk_c, E => holdn, Q - => \inst[11]\); - - \r.x.data_0_RNO_4[2]\ : AO1B - port map(A => rdatav_0_1_0_iv_0_2(10), B => N_3305_0, C => - rdata_2_sqmuxa, Y => \dco_m_i[106]\); - - \r.m.result_RNO[20]\ : MX2 - port map(A => \aluresult[20]\, B => \op1[20]\, S => - un17_casaen_0, Y => \eres2[20]\); - - \r.a.rfa2_RNIAR5M2[4]\ : MX2 - port map(A => \un3_de_ren1[103]\, B => \rfa2[4]\, S => - holdn, Y => raddr2(4)); - - \r.m.ctrl.trap_RNI3CIA11\ : NOR2B - port map(A => un1_trap_0_sqmuxa_5, B => un6_annul, Y => - tt_0_sqmuxa); - - \r.e.op1_RNITUR144[15]\ : NOR3C - port map(A => \op1_m_0[15]\, B => \d_iv_2[15]\, C => - \aluresult_m_0[15]\, Y => \d_i[15]\); - - \r.f.pc_RNIUONPJ1[2]\ : OA1A - port map(A => \fpc[2]\, B => rst, C => - \un6_ex_add_res_m[3]\, Y => \npc_iv_1[2]\); - - \r.e.op2_RNIA5IG[5]\ : MX2 - port map(A => \op2[5]\, B => N_4252, S => ldbp2_2, Y => - \un1_iu0_5[71]\); - - \r.e.op2_RNO_4[5]\ : OA1A - port map(A => \maddress[5]\, B => d27, C => \cpi_m_i[357]\, - Y => \d_1_iv_1[5]\); - - \r.x.data_0_RNO_0[8]\ : NOR3A - port map(A => \data_0_1_0_iv_0[8]\, B => \rdata_13_m[8]\, C - => \rdata_17_m[8]\, Y => \data_0_1_0_iv_1[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I304_Y_0 : XOR3 - port map(A => \data_0[13]\, B => \un1_iu0_6[13]\, C => - N802_1, Y => \un6_ex_add_res_s2[14]\); - - \r.w.result_RNICDB4[5]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[5]\, Y - => N_403); - - \r.e.op2[14]\ : DFN1E0 - port map(D => N_298, CLK => lclk_c, E => holdn, Q => - \op2[14]\); - - \r.e.ctrl.cnt_RNI458O[0]\ : NOR2A - port map(A => read_1_sqmuxa_0, B => N_3356_3, Y => - read_1_sqmuxa_i); - - \r.x.ctrl.rd[0]\ : DFN1E0 - port map(D => \rd_1[0]\, CLK => lclk_c, E => holdn, Q => - \rd_0[0]\); - - \r.d.inst_0_RNO_0[11]\ : MX2 - port map(A => data_0_11, B => \inst_0[11]\, S => - mexc_1_sqmuxa_1_0, Y => N_4611); - - \r.m.ctrl.trap_RNIJQBC\ : NOR2B - port map(A => trap_2, B => pv_1, Y => nullify_0_sqmuxa_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y_0 : AO18 - port map(A => N481, B => \data_0_0[29]\, C => - \un1_iu0_6[29]\, Y => ADD_33x33_fast_I260_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I108_Y : NOR3C - port map(A => N461, B => N464_2, C => N505_1, Y => N571_2); - - \r.a.rsel1_RNI5LB_1[0]\ : NOR2A - port map(A => \rsel1[1]\, B => \rsel1[0]\, Y => N_484_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I262_Y_0_0 : OA1C - port map(A => N502_1, B => N_50_1, C => N498, Y => - ADD_33x33_fast_I262_Y_0_0_1); - - \r.m.y_RNO_0[6]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y[6]\, C => \y_m_0[6]\, Y - => \y_iv_1[6]\); - - \r.f.pc_RNO_4[25]\ : MX2 - port map(A => I_156, B => N_4068, S => bpmiss_1_i_0, Y => - \pc_4[25]\); - - \r.e.op2_RNO_4[22]\ : OA1A - port map(A => \maddress[22]\, B => d27_0, C => - \cpi_m_i[374]\, Y => \d_1_iv_1[22]\); - - \r.e.op1_RNIBDM62[11]\ : AO1A - port map(A => \op1[11]\, B => \un17_casaen_0_0\, C => - \ex_op1_i_m[11]\, Y => \edata2_0_iv_0[11]\); - - \r.a.ctrl.inst_RNIU43A1[19]\ : NOR2 - port map(A => illegal_inst35_4, B => N_207, Y => - illegal_inst35); - - un6_ex_add_res_d2_ADD_33x33_fast_I273_Y_0 : AOI1 - port map(A => ADD_33x33_fast_I273_un1_Y_0_1, B => N653_1, C - => N652, Y => ADD_33x33_fast_I273_Y_0_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I36_Y : OA1 - port map(A => \op2[29]\, B => \un1_iu0_6[29]\, C => N482_0, - Y => N495); - - \r.w.result[9]\ : DFN1E0 - port map(D => \wdata[9]\, CLK => lclk_c, E => holdn, Q => - \result[9]\); - - un6_fe_npc_I_105 : XOR2 - port map(A => N_78, B => \fe_pc[19]\, Y => I_105); - - \r.m.icc_RNIB3R93[3]\ : NOR2B - port map(A => \aluresult_1_iv_0[23]\, B => \icc_m[3]\, Y - => \aluresult_1_iv_2[23]\); - - \r.f.pc_RNO_5[17]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[17]\, Y => \xc_trap_address_m[17]\); - - \r.e.aluop_1_RNIEVV83[1]\ : MX2C - port map(A => \logicout_4[12]\, B => N_6919, S => N_6866_i, - Y => N_3635); - - un6_ex_add_res_d2_ADD_33x33_fast_I221_un1_Y : OR2B - port map(A => N650_1, B => N635, Y => I221_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I318_Y_0_0 : XOR2 - port map(A => \op2[27]\, B => \un1_iu0_6[27]\, Y => - ADD_33x33_fast_I318_Y_0_0); - - \r.w.result_RNIJBTP3[3]\ : NOR3C - port map(A => \d_1_iv_1[3]\, B => \d_1_iv_0[3]\, C => - \rfo_m_i[35]\, Y => \d_1_iv_3[3]\); - - \r.a.ctrl.inst_RNIQ2954[31]\ : AO1D - port map(A => un1_illegal_inst11_0, B => illegal_inst12, C - => N_201, Y => privileged_inst_1_sqmuxa); - - \r.w.s.y[8]\ : DFN1E0 - port map(D => N_3772, CLK => lclk_c, E => N_6922_i, Q => - \y_0[8]\); - - \r.m.y_RNIHQSPB[25]\ : NOR2B - port map(A => \aluresult_1_iv_2[25]\, B => \bpdata_m_0[9]\, - Y => \aluresult_1_iv_4[25]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y_1 : NOR2B - port map(A => ADD_33x33_fast_I260_Y_0, B => - ADD_33x33_fast_I97_un1_Y, Y => ADD_33x33_fast_I260_Y_1); - - \r.e.alusel_RNO_2[1]\ : AO1A - port map(A => N_212, B => \alusel_i_0_a5_0_0[1]\, C => - N_339, Y => \alusel_i_0_0[1]\); - - \r.a.ctrl.inst_RNIEQKH8[30]\ : OR3B - port map(A => aluop_0_1_0_1, B => aluop_0_1_0_2, C => N_230, - Y => \aluop[0]\); - - \dci.enaddr_1_sqmuxa_1_RNO_0\ : NOR2 - port map(A => annul, B => N_3356_3, Y => - enaddr_1_sqmuxa_1_0); - - \r.w.result[24]\ : DFN1E0 - port map(D => \wdata[24]\, CLK => lclk_c, E => holdn, Q => - \result[24]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I315_Y_0_1 : XOR2 - port map(A => \data_0[24]\, B => \un1_iu0_6[24]\, Y => - \un6_ex_add_res_s2_1[25]\); - - \r.e.ldbp2_1_RNIF4GJL3\ : OR2A - port map(A => \eaddress[23]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I66_Y\ : MAJ3 - port map(A => \dpc[12]\, B => \inst_0[10]\, C => N385, Y - => N483); - - \r.x.data_0_RNO_2[2]\ : AO1B - port map(A => rdatav_0_1_0_iv_7(2), B => mcdo_m_0_0, C => - N_3456, Y => \dco_m_i[98]\); - - \r.e.op2_RNO_6[18]\ : OR2B - port map(A => data2(18), B => d25, Y => \rfo_m_i[50]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I259_Y_0 : AOI1B - port map(A => \un1_iu0_6[30]\, B => \op2[30]\, C => - I33_un1_Y_0, Y => ADD_33x33_fast_I259_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I10_G0N : NOR3A - port map(A => \op1[9]\, B => ldbp1, C => \data_0[9]\, Y => - N424_0); - - \r.w.s.wim_RNICB4N2[3]\ : MX2 - port map(A => \wim[3]\, B => \result_0[3]\, S => - wim_1_sqmuxa, Y => \wim_1[3]\); - - \r.m.result[22]\ : DFN1E0 - port map(D => \eres2[22]\, CLK => lclk_c, E => holdn, Q => - \maddress[22]\); - - \r.x.result_RNI2GLA[9]\ : MX2 - port map(A => \result_0[9]\, B => \data_0[9]\, S => ld_0, Y - => \un1_p0_6[361]\); - - \r.w.s.tt_RNO[1]\ : MX2A - port map(A => \xc_vectt_1[1]\, B => \irl[1]\, S => N_6747, - Y => \tt_RNO[1]\); - - \r.d.inst_0_RNI2423[24]\ : NOR2A - port map(A => \inst_0_0[24]\, B => \inst_0[20]\, Y => - N_3515_1); - - \r.m.ctrl.wicc_RNION9L\ : MX2A - port map(A => N_4181, B => \icc[1]\, S => wicc_3, Y => - N_4186); - - \r.e.op1_RNIVD884[1]\ : AOI1B - port map(A => \op1[1]\, B => un14_casaen_s1_0_1, C => - \d_1_iv_3[1]\, Y => \d_1_iv_4[1]\); - - \r.e.invop2_RNIK8QGR\ : MX2 - port map(A => \un6_ex_add_res_s2[14]\, B => - \un6_ex_add_res_s0[14]\, S => invop2, Y => N_6633); - - \r.f.pc_RNO_6[19]\ : MX2 - port map(A => \fpc[19]\, B => \eaddress[19]\, S => jump, Y - => N_4062); - - \r.x.result_RNIJLFP8[0]\ : NOR2A - port map(A => rst, B => N_3870, Y => \cwp_1_0[0]\); - - \r.w.result[27]\ : DFN1E0 - port map(D => \wdata[27]\, CLK => lclk_c, E => holdn, Q => - \result[27]\); - - \r.x.data_0_RNO[11]\ : OR3 - port map(A => \dco_m_0[107]\, B => \data_0_1_0_iv_0[11]\, C - => \data_0_1_4[9]\, Y => \data_0_1[11]\); - - \r.w.result_RNI90P1[15]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[15]\, Y - => \result_m_0_0[15]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I3_P0N : AO1A - port map(A => ldbp1_2, B => \op1[2]\, C => \data_0[2]\, Y - => N404_1); - - \r.m.y_RNO_1[20]\ : AOI1B - port map(A => \y_0[20]\, B => y08_0, C => \y_m_2[21]\, Y - => \y_iv_0[20]\); - - \r.e.op2_RNO_8[26]\ : OR3B - port map(A => d29_0, B => \imm[26]\, C => \rsel2[0]\, Y => - \imm_m_i[26]\); - - \r.a.imm[31]\ : DFN1E0 - port map(D => \un3_de_ren1[149]\, CLK => lclk_c, E => holdn, - Q => \imm[31]\); - - \r.x.dci.size_RNIB0QVR[0]\ : NOR3B - port map(A => \me_size_1[0]\, B => ld_3, C => - \me_size_1[1]\, Y => rdata_3_sqmuxa_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I268_Y : AO1B - port map(A => ADD_33x33_fast_I268_un1_Y_0_1, B => N674_0, C - => ADD_33x33_fast_I268_Y_0_0, Y => N782_0); - - \r.e.aluop_0_RNI2NHB1[0]\ : NOR3C - port map(A => \aluop_0[0]\, B => \un1_iu0_6[24]\, C => - \logicout_5_0_i_0_tz[24]\, Y => \logicout_5_0_i_0[24]\); - - \r.e.op1[12]\ : DFN1E0 - port map(D => \aop1[12]\, CLK => lclk_c, E => holdn, Q => - \op1[12]\); - - \r.m.y_RNIFT8V2[30]\ : AOI1B - port map(A => \y[30]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[30]\, Y => \aluresult_1_iv_0[30]\); - - \r.e.shleft_1_RNI5D9G1\ : MX2A - port map(A => \shiftin_5[24]\, B => shleft_1_RNIDVBG, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[8]\); - - \r.m.icc_RNIC6A3[3]\ : XNOR2 - port map(A => \inst_0[28]\, B => \icc[3]\, Y => branch_7_i); - - \r.d.inst_0_RNIES9C[23]\ : OR2B - port map(A => ldcheck1_5_i_a6_1_1, B => N_3736_2, Y => - N_3736); - - un6_ex_add_res_d2_ADD_33x33_fast_I29_G0N : NOR2B - port map(A => \un1_iu0_6[28]\, B => \data_0[28]\, Y => - N481_1); - - \r.e.op1_RNI2PCQB[17]\ : NOR3 - port map(A => \edata2_0_iv_0[17]\, B => \ex_op1_i_m[17]\, C - => \bpdata_i_m_1[1]\, Y => edata2_0_iv(17)); - - \r.d.inst_0_RNIAK79[24]\ : OR3B - port map(A => \inst_0_0[24]\, B => \un1_p0_6_0[60]\, C => - \inst_0_0[22]\, Y => un5_op3); - - un6_ex_add_res_d0_ADD_33x33_fast_I262_Y_0_0 : OA1A - port map(A => N502_0, B => N_50_0, C => N498_i, Y => - ADD_33x33_fast_I262_Y_0_0_0); - - \r.e.aluop_RNIVT234[1]\ : OR2B - port map(A => \bpdata[6]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[6]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I303_Y_0_0 : XOR2 - port map(A => \op2[12]\, B => \un1_iu0_6[12]\, Y => - ADD_33x33_fast_I303_Y_0_0); - - \r.m.result_RNISVO1[12]\ : OR2B - port map(A => d13, B => \maddress[12]\, Y => - \result_m_0[12]\); - - \r.e.ctrl.trap_RNO\ : MX2A - port map(A => trap_4, B => trap_1, S => annul_2, Y => - trap_3); - - \r.e.ctrl.inst_RNI1FB51[25]\ : MX2 - port map(A => N_475, B => N_482, S => \inst_RNIJ0JA[25]\, Y - => N_261); - - \r.m.y_RNO_2[13]\ : OR2A - port map(A => \logicout[13]\, B => y14, Y => - \logicout_m[13]\); - - \r.e.aluop_RNI6KJJ1[2]\ : XA1 - port map(A => \un1_iu0_5[84]\, B => \aluop_1[2]\, C => - \un1_iu0_6[18]\, Y => N_3545); - - \r.e.op1_RNO[29]\ : MX2C - port map(A => \d_i[29]\, B => \d_i[30]\, S => N_227, Y => - \aop1[29]\); - - \r.e.ctrl.inst_RNI04ER[26]\ : NOR3B - port map(A => \inst_1[26]\, B => N_482, C => \inst_1[27]\, - Y => ex_bpmiss_1_0_a5_1_1); - - \r.e.op1_RNIB75RB[18]\ : NOR3 - port map(A => \edata2_0_iv_0[18]\, B => \ex_op1_i_m[18]\, C - => \bpdata_i_m_1[2]\, Y => edata2_0_iv(18)); - - \r.x.ctrl.tt_RNO[0]\ : MX2C - port map(A => N_4200_i_0, B => N_4204, S => N_4210_i_0, Y - => \tt2[0]\); - - \r.x.ctrl.inst_RNIFU0L_0[23]\ : NOR3B - port map(A => \inst[23]\, B => \inst[20]\, C => - \inst_0[21]\, Y => tba_610_e_2); - - \r.w.result[12]\ : DFN1E0 - port map(D => \wdata[12]\, CLK => lclk_c, E => holdn, Q => - \result_0[12]\); - - \r.e.op2_RNIRFMB1_0[13]\ : OR2 - port map(A => \un1_iu0_6[13]\, B => \un1_iu0_5[79]\, Y => - \logicout_3[13]\); - - \r.x.result_RNIFDBB[2]\ : MX2 - port map(A => \result_0[2]\, B => \data_0[2]\, S => ld_4, Y - => \un1_p0_6[354]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I178_Y\ : AO1A - port map(A => N545, B => N552_2, C => N544, Y => N604); - - \r.m.y_RNIHMJO6[3]\ : NOR3C - port map(A => \cpi_m[148]\, B => \y_m_1[3]\, C => - \aluresult_1_iv_1[3]\, Y => \aluresult_1_iv_3[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_o3_1 : OR2B - port map(A => ADD_33x33_fast_I206_Y_0_o3_1_0_0, B => - N_57_i_0, Y => N616_0); - - \r.f.pc_RNO_2[16]\ : OR2B - port map(A => I_84, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[14]\); - - \r.e.op1_RNIC9HR3[21]\ : NOR3C - port map(A => \rfo_m[21]\, B => \d_iv_1[21]\, C => - \op1_m_0[21]\, Y => \d_iv_3[21]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I262_Y_0_a3_0_0 : NOR2A - port map(A => N503_1, B => N_50_1, Y => - ADD_33x33_fast_I262_Y_0_a3_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I272_un1_Y : NOR3C - port map(A => N667, B => N616, C => N651_0, Y => I272_un1_Y); - - \r.x.ctrl.pc_RNI56A71[25]\ : MX2C - port map(A => \un1_p0_6[377]\, B => \pc_2[25]\, S => - s_3_sqmuxa, Y => N_3416); - - \r.e.ctrl.tt_RNO[3]\ : NOR3C - port map(A => \tt_9_1[0]\, B => \tt_3[3]\, C => - illegal_inst_7_i_0, Y => \tt_0[3]\); - - \r.d.annul_RNIIHK0F\ : OR3B - port map(A => bpmiss_1_i_0_0, B => branch_0, C => - un2_rstn_5_0_i, Y => \un2_rstn_5_0_0\); - - \r.a.imm_RNO[12]\ : MX2 - port map(A => \inst_0_RNI2NUM[2]\, B => \un1_p0_6_0[51]\, S - => call_hold5_0, Y => \un3_de_ren1[130]\); - - \r.e.shcnt_RNIFCE9D[2]\ : MX2C - port map(A => \shiftin_11[28]\, B => \shiftin_11[24]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[24]\); - - \r.a.imm_RNI4645[3]\ : OR3B - port map(A => d29_0_0, B => \imm[3]\, C => \rsel2_0[0]\, Y - => \imm_m_i[3]\); - - \r.w.s.wim_RNI95RD2[3]\ : OR2B - port map(A => \wim[3]\, B => aluresult_13_sqmuxa, Y => - \wim_m[3]\); - - \r.d.pv_RNI2POTF\ : OR2B - port map(A => un23_exbpmiss_i_0, B => un5_exbpmiss_i_0, Y - => un1_exbpmiss); - - \r.w.s.tt[7]\ : DFN1E0 - port map(D => xc_vectt14, CLK => lclk_c, E => N_6747, Q => - \tt[7]\); - - \r.e.shleft_RNIHURJ_0\ : OR2A - port map(A => \un1_iu0_6[27]\, B => shleft, Y => - \shiftin_5[27]\); - - \r.e.op2_RNO_0[19]\ : OR3C - port map(A => \op1_m_i[19]\, B => \d_1_iv_3[19]\, C => - \aluresult_m_i[19]\, Y => \d_1[19]\); - - \r.a.rfa1[0]\ : DFN1E0 - port map(D => \rs1_iv_i_0[0]\, CLK => lclk_c, E => holdn, Q - => \rfa1[0]\); - - \r.x.rstate_RNI5S7L[0]\ : NOR2 - port map(A => \rstate[0]\, B => N_6352, Y => N_6357); - - \r.m.icc_RNITIJF3[2]\ : NOR2B - port map(A => \aluresult_1_iv_0[22]\, B => \icc_m[2]\, Y - => \aluresult_1_iv_2[22]\); - - \r.a.ctrl.inst_RNI3T3A1[22]\ : OA1C - port map(A => N_203, B => N_472, C => N_256_i_0, Y => - illegal_inst_7_iv_8_tz); - - un6_ex_add_res_d2_ADD_33x33_fast_I188_Y : NOR2B - port map(A => N599_2, B => N591_1, Y => N657); - - \r.e.op2_RNO_4[14]\ : OA1A - port map(A => \maddress[14]\, B => d27_0, C => - \cpi_m_i[366]\, Y => \d_1_iv_1[14]\); - - \r.f.pc_RNO_8[24]\ : MX2 - port map(A => \fpc[24]\, B => \eaddress[24]\, S => jump, Y - => N_4067); - - \r.f.pc_RNO_7[21]\ : MX2 - port map(A => \fpc[21]\, B => \tba[9]\, S => - rstate_6314_d_0, Y => \xc_trap_address[21]\); - - \r.m.y_RNO_0[5]\ : NOR3C - port map(A => \y_m[6]\, B => \y_m_0[5]\, C => \y_iv_1[5]\, - Y => \y_iv_2[5]\); - - \r.f.pc_RNIERSAK7[4]\ : OR3C - port map(A => \npc_iv_1[4]\, B => \npc_iv_0[4]\, C => - \npc_iv_2[4]\, Y => rpc_2); - - \r.e.jmpl_RNIUMD1Q1\ : NOR2B - port map(A => \shiftin_17_m_0[3]\, B => - \aluresult_1_iv_6[3]\, Y => \aluresult_1_iv_7[3]\); - - \r.f.pc_RNO_0[7]\ : OA1A - port map(A => un2_rstn_3_0, B => \eaddress[7]\, C => - \pc_1_iv_0[7]\, Y => \pc_1_iv_1[7]\); - - \r.m.ctrl.pc[2]\ : DFN1E0 - port map(D => \pc_2[2]\, CLK => lclk_c, E => holdn, Q => - \pc_3[2]\); - - \r.e.aluadd_RNIMNSQ75\ : XA1B - port map(A => \icc_3_i_0[0]\, B => aluadd, C => aluresult12, - Y => \icc_16[0]\); - - \r.m.y_RNO[4]\ : AO1C - port map(A => y14_0, B => \logicout[4]\, C => \y_iv_2[4]\, - Y => \y_0[4]\); - - \r.x.result[30]\ : DFN1E0 - port map(D => \maddress[30]\, CLK => lclk_c, E => holdn, Q - => \result_0[30]\); - - \r.w.s.y_RNO[1]\ : NOR3 - port map(A => N_399, B => N_398, C => N_400, Y => N_163); - - \r.e.op2[13]\ : DFN1E0 - port map(D => N_297, CLK => lclk_c, E => holdn, Q => - \op2[13]\); - - \r.e.ctrl.inst_RNIFK0E[21]\ : OR2B - port map(A => \inst_1[22]\, B => \inst_1[21]\, Y => - N_3749_3); - - un6_ex_add_res_d2_ADD_33x33_fast_I168_Y : NOR2B - port map(A => N579_1, B => N571, Y => N637_0); - - \r.x.rstate_0_RNIPSIE2[0]\ : MX2C - port map(A => N_3413, B => \xc_result[22]\, S => - \rstate_0[0]\, Y => \wdata[22]\); - - \r.f.pc_RNO_0[15]\ : NAND2 - port map(A => \tmp[15]\, B => un2_rstn_5_0, Y => - \tmp_m[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I26_P0N : OR3A - port map(A => \data_0[25]\, B => \op1[25]\, C => ldbp1_3, Y - => N473_1); - - \r.e.op1_RNIMV5RB[19]\ : NOR3 - port map(A => \edata2_0_iv_0[19]\, B => \ex_op1_i_m[19]\, C - => \bpdata_i_m_1[3]\, Y => edata2_0_iv(19)); - - \r.d.annul_RNIRCLP85\ : OR2B - port map(A => I_45, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[8]\); - - \r.e.shcnt_RNO[4]\ : XOR2 - port map(A => \d_1[4]\, B => N_208, Y => N_270_i_i_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I30_P0N : NOR2 - port map(A => \un1_iu0_6[29]\, B => \data_0_0[29]\, Y => - N485_i_0); - - \r.m.result_RNIDJD4[25]\ : OR2B - port map(A => d13_0, B => \maddress[25]\, Y => - \result_m_0[25]\); - - \r.e.op2_RNO[2]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[2]\, Y => N_286); - - un6_fe_npc_I_129 : XOR2 - port map(A => N_61, B => \fe_pc[22]\, Y => I_129); - - \r.x.data_0_RNO_1[8]\ : OR2B - port map(A => N_3473, B => data_0_0_8, Y => - \dco_m_0_i[104]\); - - \r.x.ctrl.inst_RNIEJ1S[24]\ : NOR2B - port map(A => y15, B => y6_0, Y => y_0_sqmuxa_1_2); - - \r.e.op2_RNO_7[27]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[379]\, - Y => \cpi_m_i[379]\); - - \r.x.ctrl.tt[3]\ : DFN1E0 - port map(D => \tt2[3]\, CLK => lclk_c, E => holdn, Q => - \tt[3]\); - - \r.x.rstate_RNIJKCQ[1]\ : OR2A - port map(A => rstate_6314_d_0, B => s_3_sqmuxa_0, Y => - \xc_exception_1_0\); - - \r.x.data_0_RNO_0[28]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_28, Y => - \dco_m_1[124]\); - - \r.e.ctrl.inst_RNIO41L[21]\ : OR3 - port map(A => \inst_1[22]\, B => \inst_0[23]\, C => - \inst_1[21]\, Y => \icc_8_m_5[1]\); - - \r.d.inst_0_RNIV66G[25]\ : OR2B - port map(A => N_3361, B => N_85, Y => \rd_3[0]\); - - \r.m.su\ : DFN1E0 - port map(D => esu, CLK => lclk_c, E => holdn, Q => msu); - - \r.a.rsel1_0_RNIG3LJ2[2]\ : OR2B - port map(A => data1(19), B => d11_0, Y => \rfo_m[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I267_Y : NAND2 - port map(A => I267_un1_Y, B => ADD_33x33_fast_I267_Y_0, Y - => N780_1); - - \r.d.inst_0_RNIP2VJ[31]\ : NOR2 - port map(A => un1_inst, B => un6_op, Y => un8_op); - - \comb.branch_address.tmp_ADD_30x30_fast_I40_Y_0_a3\ : AND2 - port map(A => N424, B => N428, Y => - ADD_30x30_fast_I40_Y_0_a3); - - \comb.branch_address.tmp_ADD_30x30_fast_I10_G0N\ : NOR2B - port map(A => \inst_0[10]\, B => \dpc[12]\, Y => N388); - - \r.m.y_RNICM5I3[10]\ : NOR3C - port map(A => \cpi_m[155]\, B => \y_m_1[10]\, C => - \tt_m[6]\, Y => \aluresult_1_iv_3[10]\); - - \r.e.op2_RNO_7[6]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[358]\, Y => \cpi_m_i[358]\); - - \r.d.inst_0_RNI419C[28]\ : OR3 - port map(A => N_17, B => N_122_2, C => N_79, Y => un19_rd_1); - - \r.a.rsel2_RNI7V53[1]\ : NOR3B - port map(A => \rsel2[2]\, B => \rsel2[1]\, C => - \rsel2_0[0]\, Y => d31); - - \r.e.ldbp2_RNIAFT52\ : MX2C - port map(A => \un6_ex_add_res_s1_i[2]\, B => N_6641, S => - ldbp2_3, Y => \eaddress[1]\); - - \r.e.aluop_0_RNIBQCM1[0]\ : MX2C - port map(A => N_3568, B => N_3632, S => \aluop_0[0]\, Y => - \logicout[9]\); - - \r.x.data_0_RNO_3[6]\ : OR2B - port map(A => rdata_2_sqmuxa, B => data_0_2_14, Y => - \dco_m_i[110]\); - - \r.x.data_0_RNO_3[13]\ : NOR2A - port map(A => \data_0[13]\, B => ld_3, Y => \data_0_m[13]\); - - \r.m.result_RNITVO1[13]\ : OR2B - port map(A => d13, B => \maddress[13]\, Y => - \result_m_0[13]\); - - \r.d.inst_0_RNI9MOA[24]\ : NOR3A - port map(A => ldcheck1_5_i_a6_2_1, B => \inst_0[20]\, C => - \inst_0_0[24]\, Y => ldcheck1_5_i_a6_2_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I264_Y_0 : OR2 - port map(A => I165_un1_Y, B => N568, Y => - ADD_33x33_fast_I264_Y_0); - - \r.e.shcnt[4]\ : DFN1E0 - port map(D => N_270_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[4]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I238_Y_0\ : AOI1 - port map(A => N526, B => N519, C => N518, Y => - ADD_30x30_fast_I238_Y_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I191_Y : AO1A - port map(A => N595_2, B => N602_0, C => N594_1, Y => N660_0); - - \r.e.alucin_RNO\ : NOR3B - port map(A => cin_iv_i_2, B => N_348, C => N_236, Y => - N_6684_i_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I198_Y : NOR2B - port map(A => N609_0, B => N601, Y => N667_0); - - \r.e.op1_RNI070N1[28]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[28]\, Y => - \ex_op1_i_m[28]\); - - \r.a.ctrl.inst_RNIOVAT5[31]\ : OR3C - port map(A => cp_disabled_6_sqmuxa, B => - cp_disabled_1_sqmuxa, C => fp_disabled_4_0_1_1, Y => - fp_disabled_4); - - \r.m.y[1]\ : DFN1E0 - port map(D => \y_1[1]\, CLK => lclk_c, E => holdn, Q => - \y[1]\); - - \r.f.pc[29]\ : DFN1E0 - port map(D => \pc_1[29]\, CLK => lclk_c, E => holdn, Q => - \fpc[29]\); - - \r.e.ctrl.wreg_RNIIPDC\ : AO1C - port map(A => call_hold7_i, B => ldchkex_0, C => wreg_7, Y - => wreg_2); - - \r.x.ctrl.pc_RNID2HF[23]\ : MX2 - port map(A => \pc[23]\, B => \pc_0[23]\, S => \npc_1[1]\, Y - => N_3234); - - \r.d.pv_RNI21DP7_0\ : NOR3 - port map(A => ex_bpmiss_1_0, B => annul_2, C => pv, Y => - un13_exbpmiss_0); - - \r.e.op1_RNI4JN8[0]\ : MX2 - port map(A => \op1[0]\, B => \data_0[0]\, S => ldbp1_1, Y - => \un1_iu0_6[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I243_un1_Y : NOR2B - port map(A => N672_0, B => N657_0, Y => I243_un1_Y_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I179_Y\ : NOR3B - port map(A => N494, B => N498_0, C => N545, Y => N605); - - un6_ex_add_res_d0_ADD_33x33_fast_I121_Y_0 : AO13 - port map(A => N445_0, B => \un1_iu0_6[17]\, C => - \data_0[17]\, Y => ADD_33x33_fast_I121_Y_0_0); - - \r.e.op2_RNO_2[12]\ : AOI1B - port map(A => data2(12), B => d25_0, C => \d_1_iv_2[12]\, Y - => \d_1_iv_3[12]\); - - \r.e.op2_RNIR2OP[30]\ : MX2 - port map(A => \op2[30]\, B => N_4277, S => ldbp2_0, Y => - \un1_iu0_5[96]\); - - \r.e.ctrl.annul_RNIQ60BE\ : NOR3B - port map(A => ex_bpmiss_1_0, B => branch_1_m7_1, C => - \xc_exception_1_0\, Y => branch_1_m7_3); - - un6_ex_add_res_d0_ADD_33x33_fast_I78_Y : NOR2B - port map(A => N422_0, B => N419, Y => N537_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I36_un1_Y\ : OR3B - port map(A => \dpc[26]\, B => N434_1, C => \inst_0_1[26]\, - Y => I36_un1_Y_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I47_Y_0_o3 : OR2 - port map(A => N466, B => N_72, Y => N506_1); - - \r.e.op2_RNO_0[16]\ : OR3C - port map(A => \op1_m_i[16]\, B => \d_1_iv_3[16]\, C => - \aluresult_m_i[16]\, Y => \d_1[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I272_Y : OR3 - port map(A => N650_0, B => I272_un1_Y, C => I237_un1_Y, Y - => N790); - - \r.a.ctrl.rd_RNI1VUG3[0]\ : NOR3C - port map(A => un2_rs1_0_i, B => un2_rs1_6_i, C => - un2_rs1_NE_2, Y => un2_rs1_NE_5); - - \r.d.annul_RNI17OB\ : NOR2A - port map(A => un9_rabpmiss_0, B => annul_1, Y => - un9_rabpmiss_1); - - \r.x.result_RNIP91O3[10]\ : MX2 - port map(A => \un1_iu0_6[10]\, B => \un1_p0_6[362]\, S => - bpdata6, Y => \bpdata[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I50_Y : OA1 - port map(A => \op2[22]\, B => \un1_iu0_6[22]\, C => N461_0, - Y => N509); - - \r.x.ctrl.annul_RNIVHS32\ : OR2 - port map(A => cwp_1_sqmuxa, B => annul_1_0, Y => - pil_0_sqmuxa); - - \r.f.pc_RNO_7[18]\ : MX2 - port map(A => \fpc[18]\, B => \tba[6]\, S => - rstate_6314_d_0, Y => \xc_trap_address[18]\); - - \r.m.ctrl.rd_RNIQQ7Q[3]\ : XNOR2 - port map(A => \inst_0_RNI3RUM[3]\, B => \rd_0[3]\, Y => - un1_de_ren1_1_3_i_0); - - \r.d.inst_0_RNIV3M6[17]\ : OR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_0[0]\, B => - un26_rs1opt, Y => \de_raddr1_2[4]\); - - \r.e.shcnt_RNIA7HM5[3]\ : MX2 - port map(A => \shiftin_8[32]\, B => \shiftin_8[24]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[24]\); - - \r.d.cnt_RNO[0]\ : NOR2 - port map(A => cnt_2_sqmuxa_0, B => annul_4, Y => - cnt_2_sqmuxa); - - \r.x.result_RNILK6E[21]\ : MX2 - port map(A => \result_0[21]\, B => \data_0[21]\, S => ld_4, - Y => \un1_p0_6[373]\); - - \r.e.ldbp2_2_RNIHUD5B3\ : MX2C - port map(A => \un6_ex_add_res_s1_i[22]\, B => N_6568, S => - ldbp2_2, Y => \eaddress[21]\); - - \r.a.ctrl.inst_RNIIO1S[21]\ : OR2A - port map(A => illegal_inst35_4_0, B => N_216, Y => - illegal_inst35_4); - - \r.w.result_RNIF7QL[22]\ : AOI1B - port map(A => \un1_p0_6[374]\, B => d14_0, C => - \result_m_0_0[22]\, Y => \d_iv_0[22]\); - - \r.d.pv_RNO\ : NOR3C - port map(A => pv_4_0, B => pv_2, C => pv_3, Y => pv_6); - - \r.e.shleft_1_RNIFL5S2\ : MX2B - port map(A => \shiftin_5[42]\, B => \shiftin_5[26]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[26]\); - - \r.e.op2_RNO_3[13]\ : NOR3C - port map(A => \cpi_m_i[365]\, B => \result_m_i[13]\, C => - \d_1_iv_0[13]\, Y => \d_1_iv_2[13]\); - - \r.x.result_RNIRLS65[8]\ : OR2B - port map(A => \bpdata[8]\, B => N_3974, Y => \bpdata_m[8]\); - - \r.e.jmpl_RNI6M02E2\ : OR3C - port map(A => \aluresult_1_iv_8[6]\, B => - \shiftin_17_m_0[6]\, C => ldbp2_2_RNI5355F, Y => - \aluresult[6]\); - - \r.f.pc_RNIN6L9KD[10]\ : OR3C - port map(A => \npc_iv_1[10]\, B => \npc_iv_0[10]\, C => - \npc_iv_2[10]\, Y => rpc_8); - - \r.w.s.tba[1]\ : DFN1E1 - port map(D => \result_0[13]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[1]\); - - \r.x.data_0_RNO_1[26]\ : NOR2A - port map(A => \data_0[26]\, B => ld_3, Y => \data_0_m[26]\); - - \r.x.ctrl.wicc_RNO\ : NOR2A - port map(A => wicc_3, B => \un1_p0_6[0]\, Y => wicc_1_2); - - \r.e.aluop_1_RNI9GHD1[1]\ : XOR3 - port map(A => \un1_iu0_6[10]\, B => \aluop_1[1]\, C => - \un1_iu0_5[76]\, Y => N_6844); - - \comb.fpstdata.edata2_0_iv[2]\ : NAND2 - port map(A => \bpdata_i_m[2]\, B => \edata2_0_iv_0[2]\, Y - => edata2_0_iv(2)); - - \r.x.result_RNIHLBB9[5]\ : AO1C - port map(A => N_3029, B => G_9_0, C => et_2_sqmuxa, Y => - et_1_0); - - \r.x.data_0_RNO[25]\ : OR3 - port map(A => \dco_m_1[121]\, B => \data_0_m[25]\, C => - \data_0_1_4[18]\, Y => \data_0_1[25]\); - - \r.e.shleft_1_RNIEJBQ1\ : MX2A - port map(A => \shiftin_5[21]\, B => shleft_1_RNI9JBG, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[5]\); - - \r.e.aluop_RNIHFP34[1]\ : OR2B - port map(A => \bpdata[3]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I319_Y_0 : AX1E - port map(A => N_51_i, B => ADD_33x33_fast_I262_Y_0_0_1, C - => \un6_ex_add_res_s2_1[29]\, Y => - \un6_ex_add_res_s2[29]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I181_Y : OR3A - port map(A => I181_un1_Y_i, B => I121_un1_Y, C => - ADD_33x33_fast_I121_Y_0, Y => N650_1); - - \r.x.npc_0_RNILSQ61[0]\ : MX2C - port map(A => N_3221, B => N_3251, S => \npc_0[0]\, Y => - \xc_result[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I62_un1_Y\ : OAI1 - port map(A => \dpc[14]\, B => \inst_0[12]\, C => N391, Y - => I62_un1_Y_i); - - \r.m.icc_RNO_25[2]\ : NOR2 - port map(A => \logicout[13]\, B => \logicout[14]\, Y => - icc_0_sqmuxa_1_5); - - \r.w.s.tba_RNICNFP5[7]\ : AND2 - port map(A => \tba_m[7]\, B => \bpdata_m[19]\, Y => - \aluresult_1_iv_3[19]\); - - \un1_r.w.s.cwp_1_CO1_0\ : OR2B - port map(A => et_RNI1BRF2, B => CO1_0_tz, Y => CO1_0); - - \r.m.dci.size_RNO_0[1]\ : NOR3A - port map(A => ex_sari_1_1_0, B => \inst[24]\, C => N_3356_3, - Y => \size_1[1]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I244_un1_Y\ : NOR2B - port map(A => ADD_30x30_fast_I244_un1_Y_0, B => N607, Y => - I244_un1_Y_0); - - \r.d.inst_0_RNI4423_0[24]\ : NOR2A - port map(A => \inst_0_0[22]\, B => \inst_0_0[24]\, Y => - icc_check9_2); - - \r.a.ctrl.inst_RNI9S0E_0[21]\ : OR2A - port map(A => \inst_1[24]\, B => \inst_2[21]\, Y => - alusel24_2); - - \r.f.pc_RNO_3[30]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[30]\, Y => - \pc_4_m[30]\); - - \r.m.y_RNO_3[20]\ : OR3A - port map(A => \y_2[20]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[20]\); - - \r.x.result_RNITQDE5[14]\ : NOR2B - port map(A => \bpdata[14]\, B => \aluop_RNIGM3N1[2]\, Y => - \bpdata_i_m[14]\); - - \r.e.aluop_RNIP5PM8[2]\ : AOI1 - port map(A => edata_1_sqmuxa, B => \bpdata[11]\, C => - \bpdata_i_m_2[3]\, Y => \edata2_iv_2[27]\); - - \r.m.ctrl.rd[2]\ : DFN1E0 - port map(D => \rd_1[2]\, CLK => lclk_c, E => holdn, Q => - \rd_0[2]\); - - \r.e.op2_RNO[9]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[9]\, Y => N_293); - - un6_ex_add_res_d0_ADD_33x33_fast_I37_Y : AO13 - port map(A => N478_1, B => \un1_iu0_6[28]\, C => - \data_0[28]\, Y => N496_0); - - \r.e.op2_RNIBGNB1_0[17]\ : OR2 - port map(A => \un1_iu0_6[17]\, B => \un1_iu0_5[83]\, Y => - \logicout_3[17]\); - - \r.e.op1_RNIE93M7[5]\ : OR2B - port map(A => \edata2_0_iv_0[5]\, B => \bpdata_i_m[5]\, Y - => edata2_0_iv(5)); - - \r.e.ldbp2_0_RNIP1CIF\ : MX2C - port map(A => \un6_ex_add_res_s1[8]\, B => N_6554, S => - ldbp2_0, Y => \eaddress[7]\); - - \r.e.jmpl_RNIGRK585\ : OR3C - port map(A => \aluresult_1_iv_7[18]\, B => - \shiftin_17_m_0[18]\, C => \un6_ex_add_res_m[19]\, Y => - \aluresult[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I279_Y_0_0\ : XOR2 - port map(A => \dpc[21]\, B => \inst_0[19]\, Y => - ADD_30x30_fast_I279_Y_0_0); - - \r.a.rsel1_0_RNI0P8M2[2]\ : OR2B - port map(A => data1(8), B => d11, Y => \rfo_m[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I145_Y_0 : MIN3 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N409_1, - Y => ADD_33x33_fast_I145_Y_0_1); - - \r.x.ctrl.pc_RNII7AE[8]\ : MX2 - port map(A => \pc_0[8]\, B => \pc_2[8]\, S => \npc_0[1]\, Y - => N_3219); - - \r.w.s.ps_RNIBCGT5\ : OR3C - port map(A => s_m, B => ps_m, C => \result_m[6]\, Y => ps_1); - - \r.d.inst_0_RNIR7G41[17]\ : MX2C - port map(A => \de_raddr1_2[6]\, B => \de_raddr1_1[6]\, S - => rs1mod, Y => \un3_de_ren1[97]\); - - \r.m.y_RNO_3[2]\ : OR3A - port map(A => \y_2[2]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[2]\); - - \r.a.rfa1[2]\ : DFN1E0 - port map(D => \un3_de_ren1[93]\, CLK => lclk_c, E => holdn, - Q => \rfa1[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I306_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[15]\, B => \data_0_2[15]\, Y => - \un6_ex_add_res_s2_1[16]\); - - \r.x.ctrl.pc_RNIB7AE[4]\ : MX2 - port map(A => \pc_2[4]\, B => \pc[4]\, S => \npc_1[1]\, Y - => N_3215); - - \r.d.pc[23]\ : DFN1 - port map(D => \pc_RNO[23]\, CLK => lclk_c, Q => \dpc[23]\); - - \r.x.ctrl.rd[1]\ : DFN1E0 - port map(D => \rd_0[1]\, CLK => lclk_c, E => holdn, Q => - \rd_1[1]\); - - \r.m.y_RNO_1[7]\ : OR2B - port map(A => \y[8]\, B => mulstep_0, Y => \y_m_0[8]\); - - \r.e.shcnt_RNINCAA9[2]\ : MX2C - port map(A => \shiftin_11[6]\, B => \shiftin_11[2]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[2]\); - - \r.a.rsel1_RNINCQ667[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[26]\, Y - => \aluresult_m_0[26]\); - - \r.e.ctrl.cnt[1]\ : DFN1E0 - port map(D => \cnt_2[1]\, CLK => lclk_c, E => holdn, Q => - \cnt[1]\); - - \r.e.shcnt_RNI50TV8[2]\ : MX2C - port map(A => \shiftin_11[9]\, B => \shiftin_11[5]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I308_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[17]\, B => \data_0[17]\, Y => - \un6_ex_add_res_s2_1[18]\); - - \r.w.s.s_RNO_0\ : MX2 - port map(A => s_1_iv, B => s, S => holdn, Y => N_4943); - - \r.e.aluop_2_RNIDKAP[1]\ : MX2C - port map(A => N_3536, B => \logicout_3[9]\, S => - \aluop_2[1]\, Y => N_3568); - - \r.e.op1_RNO[16]\ : MX2C - port map(A => \d_i[16]\, B => \d_i[17]\, S => N_227_0, Y - => \aop1[16]\); - - \r.d.cwp_RNI1M5O[0]\ : MX2B - port map(A => \cwp_0[0]\, B => \cwp_0[0]\, S => un8_op, Y - => \ncwp[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I313_Y_0 : AX1D - port map(A => I229_un1_Y, B => ADD_33x33_fast_I268_Y_0, C - => \un6_ex_add_res_s2_1[23]\, Y => - \un6_ex_add_res_s2[23]\); - - \r.x.dci.SIGNED_RNIIMS3D1\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_22, B => mcdo_m_0_29, C => - me_signed_1, Y => \rdata_5[8]\); - - \r.x.ctrl.tt_RNI72K6[2]\ : NOR2B - port map(A => \tt[2]\, B => \tt[3]\, Y => tt_1); - - \r.e.op1_RNITICR1[17]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[17]\, Y => - \ex_op1_i_m[17]\); - - \r.e.jmpl_RNIS1V9M_0\ : OR2B - port map(A => \shiftin_17[9]\, B => aluresult_2_sqmuxa_0, Y - => \shiftin_17_m_0[9]\); - - aluresult_11_sqmuxa_5 : NOR2 - port map(A => miscout140, B => aluresult_11_sqmuxa_5_0, Y - => aluresult_12_sqmuxa_5); - - \r.x.result_RNIQ6VN5[5]\ : OR2A - port map(A => N_3687, B => \bpdata[5]\, Y => - \bpdata_i_m[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I25_P0N : OR2 - port map(A => \op2[24]\, B => \un1_iu0_6[24]\, Y => N470); - - \r.e.op2_RNO_8[9]\ : OR2A - port map(A => \maddress[9]\, B => d27, Y => - \result_m_i_0[9]\); - - \r.e.op1_RNISAA2F3[12]\ : NOR3C - port map(A => \op1_m_0[12]\, B => \d_iv_2[12]\, C => - \aluresult_m_0[12]\, Y => \d_i[12]\); - - \comb.v.f.pc_1_iv[3]\ : NAND2 - port map(A => \un6_fe_npc_m[1]\, B => \pc_1_iv_2[3]\, Y => - \pc_1[3]\); - - \r.e.op1_RNI4LC1B[8]\ : NOR3 - port map(A => \bpdata_i_m_2[0]\, B => \edata2_0_iv_0[8]\, C - => \bpdata_i_m[8]\, Y => edata2_0_iv(8)); - - \r.e.op2_RNI0SHN1[19]\ : OR2B - port map(A => \un1_iu0_5[85]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[19]\); - - \r.d.cnt_RNITFU4[1]\ : NOR3B - port map(A => \inst_0_0[22]\, B => \cnt_0[1]\, C => annul_1, - Y => ldcheck2_2_sqmuxa_1_1); - - \r.m.y_RNO_4[6]\ : OR2B - port map(A => \y[7]\, B => mulstep_0, Y => \y_m[7]\); - - \r.e.aluop_RNITH234[1]\ : OR2B - port map(A => \bpdata[5]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[5]\); - - \r.x.ctrl.rd_RNIHVH6[3]\ : XNOR2 - port map(A => \rd_2[3]\, B => \rd[3]\, Y => rd_3_i_0); - - \r.m.y_RNO_2[14]\ : OR2A - port map(A => \logicout[14]\, B => y14, Y => N_385); - - \r.f.pc_RNO_0[20]\ : NAND2 - port map(A => \tmp[20]\, B => \un2_rstn_5\, Y => - \tmp_m[20]\); - - \r.e.op2_RNO_4[11]\ : OA1A - port map(A => \maddress[11]\, B => d27_0, C => - \cpi_m_i[363]\, Y => \d_1_iv_1[11]\); - - \r.a.imm_RNO[17]\ : MX2 - port map(A => \inst_0[7]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[135]\); - - \r.x.ctrl.inst[22]\ : DFN1E0 - port map(D => \inst_2[22]\, CLK => lclk_c, E => holdn, Q - => \inst_0[22]\); - - \r.e.aluop_RNIN5234[1]\ : OR2B - port map(A => \bpdata[4]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[4]\); - - \r.x.ctrl.wreg_RNI0N1T1\ : NOR2 - port map(A => xc_wreg_1, B => holdn, Y => wren); - - \r.w.s.dwt_RNIEL2V1\ : OA1A - port map(A => dwt, B => aluresult_9_sqmuxa, C => - aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[14]\); - - \r.m.y_RNI5FKVP[30]\ : NOR3C - port map(A => \aluresult_1_iv_5[30]\, B => - \aluresult_1_iv_4[30]\, C => \logicout_m_0[30]\, Y => - \aluresult_1_iv_7[30]\); - - \r.e.op2_RNO_3[20]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[20]\, Y => - \aluresult_m_i[20]\); - - \r.m.dci.read_0\ : DFN1E0 - port map(D => read, CLK => lclk_c, E => holdn, Q => read_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I17_P0N : OR2 - port map(A => \un1_iu0_6[16]\, B => \op2[16]\, Y => N446_0); - - \r.m.result[30]\ : DFN1E0 - port map(D => \eres2[30]\, CLK => lclk_c, E => holdn, Q => - \maddress[30]\); - - \r.a.imm_RNO[3]\ : NOR2B - port map(A => \inst_0_RNI3RUM[3]\, B => call_hold5, Y => - \un3_de_ren1[121]\); - - \r.e.shcnt[1]\ : DFN1E0 - port map(D => N_267_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[1]\); - - \r.e.op2[20]\ : DFN1E0 - port map(D => N_304, CLK => lclk_c, E => holdn, Q => - \op2[20]\); - - \r.x.result_RNI5S9N3[12]\ : MX2C - port map(A => \un1_iu0_6[12]\, B => \un1_p0_6[364]\, S => - bpdata6, Y => \bpdata[12]\); - - \r.e.op1_RNI4HFC[0]\ : OR2B - port map(A => \op1[0]\, B => un14_casaen_s1_0, Y => - \op1_m_0[0]\); - - \r.f.pc_RNO_0[4]\ : NOR3C - port map(A => \pc_4_m[4]\, B => \xc_trap_address_m[4]\, C - => \un6_ex_add_res_m_1[5]\, Y => \pc_1_iv_1[4]\); - - \r.e.ctrl.inst[24]\ : DFN1E0 - port map(D => \inst_1[24]\, CLK => lclk_c, E => holdn, Q - => \inst[24]\); - - \r.x.ctrl.pc_RNIEAHF[24]\ : MX2 - port map(A => \pc_0[24]\, B => \pc[24]\, S => \npc_0[1]\, Y - => N_3235); - - \r.d.inull_RNILH7FU\ : OA1C - port map(A => \inull\, B => \de_hold_pc_1\, C => - \un1_p0_6[0]\, Y => pv_4_0); - - \r.x.ctrl.wreg\ : DFN1E0 - port map(D => wreg_4, CLK => lclk_c, E => holdn, Q => wreg); - - \r.x.ctrl.ld_0_RNIH0TN2_0\ : NOR3C - port map(A => bpdata6_8, B => bpdata6_7, C => bpdata6_9, Y - => bpdata6); - - \r.d.inst_0_RNI38FS[28]\ : NOR2 - port map(A => un19_rd_1, B => \rd_3[0]\, Y => un19_rd); - - \r.m.y_RNO_4[3]\ : OR3A - port map(A => \y_2[3]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[3]\); - - \r.e.aluop_RNIFOHL_0[1]\ : NOR3A - port map(A => logicout19_0, B => \aluop_3[1]\, C => - un17_casaen_0, Y => edata_2_sqmuxa); - - \r.x.result_RNICU1O3[22]\ : MX2 - port map(A => \un1_iu0_6[22]\, B => \un1_p0_6[374]\, S => - bpdata6, Y => \bpdata[22]\); - - \r.d.inst_0_RNO[18]\ : NOR2B - port map(A => rst, B => N_4618, Y => \inst_0_RNO[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I293_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[3]\, B => N616_1, Y => - \un6_ex_add_res_s2[3]\); - - \r.x.icc[0]\ : DFN1E0 - port map(D => \icc_0[0]\, CLK => lclk_c, E => holdn, Q => - \icc_2[0]\); - - \r.d.inst_0[6]\ : DFN1 - port map(D => \inst_0_RNO[6]\, CLK => lclk_c, Q => - \inst_0[6]\); - - un6_fe_npc_I_9 : XOR2 - port map(A => N_147, B => \fe_pc[4]\, Y => I_9); - - \r.m.y_RNO_1[9]\ : OR2B - port map(A => \y_0[10]\, B => mulstep_1, Y => \y_m[10]\); - - \r.m.ctrl.wreg_RNO\ : NOR2A - port map(A => wreg_7, B => \un1_p0_6[0]\, Y => wreg_1_9); - - \r.a.imm[29]\ : DFN1E0 - port map(D => \un3_de_ren1[147]\, CLK => lclk_c, E => holdn, - Q => \imm[29]\); - - \r.x.ctrl.wicc_RNIIE1U1\ : NOR2 - port map(A => cwp_1_sqmuxa, B => wicc, Y => icc_0_sqmuxa_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I25_P0N\ : OR2 - port map(A => \inst_0_1[27]\, B => \dpc[27]\, Y => N434_1); - - \r.e.op2_RNIAFA92[18]\ : AOI1B - port map(A => \un1_iu0_5[84]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I274_Y_0\ : XNOR2 - port map(A => N726_i, B => ADD_30x30_fast_I274_Y_0_0, Y => - \tmp[16]\); - - \r.w.s.et_RNI8EAN\ : NOR2A - port map(A => et, B => N_6357, Y => N_6350); - - \r.w.s.tt_RNIEOR7H[0]\ : AOI1B - port map(A => \bpdata[4]\, B => N_3957, C => - \aluresult_1_iv_5[4]\, Y => \aluresult_1_iv_6[4]\); - - \r.a.rfa2_RNI9V361[1]\ : MX2 - port map(A => \inst_0_RNI1JUM[1]\, B => \rfa2[1]\, S => - holdn, Y => raddr2(1)); - - \r.m.icc[2]\ : DFN1E0 - port map(D => \icco[2]\, CLK => lclk_c, E => holdn, Q => - \icc_0[2]\); - - \r.f.pc[4]\ : DFN1E0 - port map(D => \pc_1[4]\, CLK => lclk_c, E => holdn, Q => - \fpc[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I268_Y_0 : AO1D - port map(A => ADD_33x33_fast_I268_un1_Y_0, B => N674, C => - N642_1, Y => ADD_33x33_fast_I268_Y_0); - - \r.x.annul_all\ : DFN1E0 - port map(D => \un1_p0_6[0]\, CLK => lclk_c, E => holdn, Q - => annul_all); - - \r.w.s.y[12]\ : DFN1E0 - port map(D => N_3776, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[12]\); - - \r.e.op1_RNIJ8CP02[3]\ : MX2 - port map(A => \aluresult[3]\, B => \op1[3]\, S => - \un17_casaen_0_0\, Y => \eres2[3]\); - - \r.a.ticc_RNO\ : NOR3C - port map(A => N_145, B => ticc_exception_0_a3_1, C => - branch_1, Y => ticc_exception); - - \r.a.ctrl.trap_RNIFQU8\ : OR2 - port map(A => trap_1, B => annul_2, Y => \tt_0[2]\); - - \r.m.y_RNO[29]\ : AO1C - port map(A => y14_0, B => \logicout[29]\, C => - \y_iv_0_2[29]\, Y => \y_1[29]\); - - \r.d.pc[25]\ : DFN1 - port map(D => \pc_RNO[25]\, CLK => lclk_c, Q => \dpc[25]\); - - \r.w.s.y[7]\ : DFN1E0 - port map(D => N_3771, CLK => lclk_c, E => N_6922_i, Q => - \y_0[7]\); - - \r.e.aluop_1_RNI20LK2[1]\ : MX2C - port map(A => \logicout_4[20]\, B => N_6847, S => N_6866_i, - Y => N_3643); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_Y_0 : AOI1 - port map(A => N578_1, B => N571_0, C => N570_0, Y => - ADD_33x33_fast_I265_Y_0_0); - - \r.e.op2_RNI40NB1_0[15]\ : OR2 - port map(A => \un1_iu0_6[15]\, B => \un1_iu0_5[81]\, Y => - \logicout_3[15]\); - - \r.d.inst_0_RNIMRAH[23]\ : AO1 - port map(A => N_3739, B => N_3738, C => un5_op3, Y => - \inst_0_RNIMRAH[23]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I265_un1_Y : OR2B - port map(A => ADD_33x33_fast_I265_un1_Y_0_1, B => N814_0, Y - => I265_un1_Y_i_1); - - \r.x.rstate_RNI31F9[1]\ : OR2A - port map(A => \rstate[1]\, B => \rstate[0]\, Y => - rstate_6314_d); - - \r.d.pc_RNIQBBA4[4]\ : MX2 - port map(A => \dpc[4]\, B => \fpc[4]\, S => ra_bpmiss_1, Y - => N_3881); - - un6_ex_add_res_d1_ADD_33x33_fast_I259_Y_3 : OA1A - port map(A => N625, B => N640, C => ADD_33x33_fast_I259_Y_2, - Y => ADD_33x33_fast_I259_Y_3_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I264_Y : NAND2 - port map(A => I264_un1_Y_0, B => ADD_33x33_fast_I264_Y_1_0, - Y => N774); - - un6_ex_add_res_d1_ADD_33x33_fast_I57_Y : MAJ3 - port map(A => \op2[18]\, B => \un1_iu0_6[18]\, C => N448_0, - Y => N516_0); - - \r.e.shleft_RNI29S82\ : MX2B - port map(A => \shiftin_5[32]\, B => \shiftin_5[16]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[16]\); - - \r.e.op2_RNO_3[31]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[31]\, Y => - \aluresult_m_i[31]\); - - \comb.op_mux.d_1_iv_RNO[29]\ : NAND2 - port map(A => \aluresult[29]\, B => un14_casaen_s0_0_1, Y - => \aluresult_m_i[29]\); - - \r.m.ctrl.pc_RNIQHGF[21]\ : MX2 - port map(A => \pc_3[21]\, B => \pc[21]\, S => \npc_1[1]\, Y - => N_3262); - - \comb.branch_address.tmp_ADD_30x30_fast_I102_Y\ : AO1 - port map(A => N467_1, B => N464_1, C => N463_0, Y => N522); - - \r.e.ctrl.pc_RNICPK11[17]\ : OR2B - port map(A => \pc_0[17]\, B => jmpl_0, Y => \cpi_m[162]\); - - \r.a.ctrl.inst_RNIPCKH[27]\ : AX1E - port map(A => N_375, B => \inst_2[27]\, C => \inst_1[28]\, - Y => N_3339); - - \r.m.dci.asi_RNO[0]\ : MX2 - port map(A => su, B => \inst_1[5]\, S => \inst_0[23]\, Y - => \asi[0]\); - - \r.m.result_RNIF407[7]\ : OR2B - port map(A => d13_0, B => \maddress[7]\, Y => - \result_m_0[7]\); - - \r.x.result_RNIK4OE[24]\ : OR2B - port map(A => \un1_p0_6[376]\, B => d14, Y => - \cpi_m_0[376]\); - - \r.e.ctrl.inst[27]\ : DFN1E0 - port map(D => \inst_2[27]\, CLK => lclk_c, E => holdn, Q - => \inst_1[27]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I79_Y_0 : AO1 - port map(A => N419, B => N415_0, C => N418_0, Y => N538); - - \r.e.aluop_RNI50MK4[0]\ : OR2B - port map(A => \logicout[5]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[5]\); - - \r.m.y_RNINTN71[10]\ : OR2B - port map(A => \y_0[10]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[10]\); - - \r.a.ctrl.pc[7]\ : DFN1E0 - port map(D => \dpc[7]\, CLK => lclk_c, E => holdn, Q => - \pc_3[7]\); - - \r.a.ctrl.inst_RNIB41E_1[23]\ : NOR2A - port map(A => \inst_1[23]\, B => \inst_1[24]\, Y => - inst_22_0); - - \r.w.s.tba[18]\ : DFN1E1 - port map(D => \result_0[30]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[18]\); - - \r.m.result_RNO[23]\ : MX2 - port map(A => \aluresult[23]\, B => \op1[23]\, S => - un17_casaen_0_1, Y => \eres2[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I244_un1_Y_0\ : NOR2B - port map(A => N591, B => N358, Y => - ADD_30x30_fast_I244_un1_Y_0); - - \r.w.s.tt_RNI1P79B[0]\ : AOI1B - port map(A => \logicout[4]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_4[4]\, Y => \aluresult_1_iv_5[4]\); - - \r.a.ctrl.inst_RNIJ02S_0[21]\ : OR2 - port map(A => N_271, B => N_209, Y => - illegal_inst_7_iv_2_0_a5_1_0); - - \r.a.ctrl.rd[0]\ : DFN1E0 - port map(D => \rd_3[0]\, CLK => lclk_c, E => holdn, Q => - \rd_2[0]\); - - \r.m.ctrl.pc_RNIT9HF[14]\ : MX2 - port map(A => \pc_2[14]\, B => \pc[14]\, S => \npc_0[1]\, Y - => N_3255); - - \r.e.aluop_RNIBKTF6[1]\ : AOI1B - port map(A => edata_2_sqmuxa, B => \bpdata[30]\, C => - \edata2_iv_0[30]\, Y => \edata2_iv_1[30]\); - - \r.a.ctrl.cnt_RNIA2OG2[1]\ : AOI1 - port map(A => N_470, B => N_469, C => \cnt_2[1]\, Y => - N_483); - - un6_fe_npc_I_38 : XOR2 - port map(A => N_126_0, B => \fe_pc[9]\, Y => I_38); - - \r.w.s.y[1]\ : DFN1E0 - port map(D => N_163, CLK => lclk_c, E => holdn, Q => - \y_0[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I16_P0N : AO1A - port map(A => ldbp1_2, B => \op1[15]\, C => \data_0_2[15]\, - Y => N443_1); - - \r.w.result_RNI0I2L[26]\ : AOI1B - port map(A => \un1_p0_6[378]\, B => d14_0, C => - \result_m_0_0[26]\, Y => \d_iv_0[26]\); - - \r.d.pv_RNO_2\ : OR3B - port map(A => pv_RNO_6, B => pv_12_i_a6_0_2, C => ldlock, Y - => N_4241_i_0); - - \r.e.op2_RNO_2[8]\ : NOR3C - port map(A => \d_1_iv_1[8]\, B => \d_1_iv_0[8]\, C => - \rfo_m_i[40]\, Y => \d_1_iv_3[8]\); - - un6_fe_npc_I_135 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[15]\, Y => N_56); - - \r.e.aluop_1_RNIFAJ5[1]\ : NOR3B - port map(A => \aluop_0[2]\, B => \aluop_0[0]\, C => - \aluop_1[1]\, Y => logicout20); - - \r.e.op2_RNIMCB71_0[28]\ : OR2 - port map(A => \un1_iu0_6[28]\, B => \un1_iu0_5[94]\, Y => - \logicout_3[28]\); - - \r.e.op1_RNI3E4B2[26]\ : AND2 - port map(A => \ex_op1_i_m[26]\, B => \op1_RNI3RNF[26]\, Y - => \edata2_iv_0[26]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I14_G0N : NOR3A - port map(A => \op1[13]\, B => ldbp1_0, C => \data_0[13]\, Y - => N436_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I292_Y_0 : XNOR3 - port map(A => \un1_iu0_6[1]\, B => \op2[1]\, C => N552_0, Y - => \un6_ex_add_res_s1_i[2]\); - - \r.x.data_0_RNI6F9E[10]\ : XOR2 - port map(A => \data_0[10]\, B => invop2_0, Y => N_4257); - - un6_ex_add_res_d0_ADD_33x33_fast_I105_Y : AO1 - port map(A => N506_0, B => N503_0, C => N502_0, Y => N568_0); - - \r.x.ctrl.inst[31]\ : DFN1E0 - port map(D => \inst_1[31]\, CLK => lclk_c, E => holdn, Q - => \inst_3[31]\); - - \r.e.ctrl.inst[19]\ : DFN1E0 - port map(D => \inst_2[19]\, CLK => lclk_c, E => holdn, Q - => \inst[19]\); - - \r.m.ctrl.pc[5]\ : DFN1E0 - port map(D => \pc[5]\, CLK => lclk_c, E => holdn, Q => - \pc_2[5]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_Y : OR2 - port map(A => I264_un1_Y, B => ADD_33x33_fast_I264_Y_1, Y - => N774_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I262_Y_0_a3_0_0 : NOR2A - port map(A => N503_0, B => N_50_0, Y => - ADD_33x33_fast_I262_Y_0_a3_0); - - \r.e.op1_RNIIDM62[30]\ : OA1A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[30]\, C => - \op1_RNIU2NF[30]\, Y => \edata2_iv_0[30]\); - - \r.e.aluop_0_RNIRT6R[1]\ : XOR3 - port map(A => \un1_iu0_6[8]\, B => \aluop_0[1]\, C => - \un1_iu0_5[74]\, Y => N_6868); - - \comb.branch_address.tmp_ADD_30x30_fast_I24_P0N\ : OR2A - port map(A => \inst_0_1[26]\, B => \dpc[26]\, Y => N431); - - un6_ex_add_res_d2_ADD_33x33_fast_I166_Y : NOR2B - port map(A => N577_1, B => N569_1, Y => N635); - - \r.m.y_RNI64K91[0]\ : OR2B - port map(A => \y_0[0]\, B => aluresult_10_sqmuxa, Y => - \y_m_0[0]\); - - \r.a.ctrl.wreg\ : DFN1E0 - port map(D => wreg_1_11, CLK => lclk_c, E => holdn, Q => - wreg_0); - - \r.e.ctrl.inst[5]\ : DFN1E0 - port map(D => \inst[5]\, CLK => lclk_c, E => holdn, Q => - \inst_1[5]\); - - \r.m.icc_RNO_12[2]\ : NOR2 - port map(A => \logicout[26]\, B => \logicout[27]\, Y => - icc_0_sqmuxa_1_9); - - un6_fe_npc_I_34 : AND3 - port map(A => \fe_pc[5]\, B => \fe_pc[6]\, C => \fe_pc[7]\, - Y => \DWACT_FINC_E[2]\); - - \r.d.pc[12]\ : DFN1 - port map(D => \pc_RNO[12]\, CLK => lclk_c, Q => \dpc[12]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I156_Y : NOR2B - port map(A => N567, B => N559, Y => N625_1); - - \r.f.pc_RNO_1[7]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[7]\, C => - \xc_trap_address_m[7]\, Y => \pc_1_iv_0[7]\); - - \r.d.inst_0_RNO[27]\ : NOR2B - port map(A => rst, B => N_4627, Y => \inst_0_RNO[27]\); - - \r.a.ctrl.rd_RNO[6]\ : NOR2A - port map(A => I_14, B => un3_reg, Y => N_37); - - un6_ex_add_res_d1_ADD_33x33_fast_I20_P0N : OR2 - port map(A => \op1_RNID1VH[19]\, B => \op2[19]\, Y => - N455_2); - - \r.m.y_RNO_3[12]\ : OR3A - port map(A => \y_2[12]\, B => wy_3, C => wy_1_0_1, Y => - \y_m_0[12]\); - - \r.e.op1_RNIH1UB[6]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[6]\, Y => - \op1_i_m[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I136_Y : OR2B - port map(A => N537_0, B => N533, Y => N599_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I84_Y : OA1 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N410_2, - Y => N543_1); - - \r.e.ctrl.tt[1]\ : DFN1E0 - port map(D => \tt_1[1]\, CLK => lclk_c, E => holdn, Q => - \tt_3[1]\); - - \r.m.y_RNO_3[6]\ : OR3A - port map(A => \y_2[6]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[6]\); - - \r.e.ctrl.tt_RNO_1[5]\ : OR2B - port map(A => \tt_9_0_a3_0[5]\, B => privileged_inst_5, Y - => N_4042); - - \r.d.pc_RNO[25]\ : MX2 - port map(A => \fpc[25]\, B => \dpc[25]\, S => N_6763_i, Y - => \pc_RNO[25]\); - - \r.e.op2_RNO_1[9]\ : NOR3C - port map(A => \rfo_m_i[41]\, B => \d_1_iv_2[9]\, C => - \op1_m_i[9]\, Y => \d_1_iv_4[9]\); - - \r.m.ctrl.pc_RNIIPN9[28]\ : MX2 - port map(A => \pc_3[28]\, B => \pc[28]\, S => \npc[1]\, Y - => N_3269); - - \r.d.cwp_RNO[0]\ : MX2 - port map(A => N_4227, B => \cwp_1_0[0]\, S => N_6358, Y => - \cwp_1_1[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I308_Y_0 : AX1B - port map(A => I239_un1_Y_1, B => ADD_33x33_fast_I273_Y_0, C - => \un6_ex_add_res_s2_1[18]\, Y => - \un6_ex_add_res_s0[18]\); - - \r.e.op2_RNIA9IG[6]\ : MX2 - port map(A => \op2[6]\, B => N_4253, S => ldbp2_1, Y => - \un1_iu0_5[72]\); - - \r.a.ctrl.inst[13]\ : DFN1E0 - port map(D => \inst_0[13]\, CLK => lclk_c, E => holdn, Q - => \inst[13]\); - - \r.e.ctrl.inst_RNIFP984[26]\ : AO1 - port map(A => ex_bpmiss_1_0_a5_0_0, B => N_261, C => - ex_bpmiss_1_0_0, Y => ex_bpmiss_1_0_1); - - \r.w.s.icc[1]\ : DFN1E0 - port map(D => \icc_1[1]\, CLK => lclk_c, E => holdn, Q => - \icc_0[1]\); - - \r.d.annul_RNIR3UT7\ : NOR2A - port map(A => annul_current_2_sqmuxa_1, B => annul_1, Y => - G_6_0); - - \comb.ld_align.rdata199_RNICVM0R4\ : OR2 - port map(A => \rdata_17_m[8]\, B => \rdata_9_m[8]\, Y => - \data_0_1_1[16]\); - - un6_fe_npc_I_45 : XOR2 - port map(A => N_121, B => \fe_pc[10]\, Y => I_45); - - \r.d.inst_0[20]\ : DFN1 - port map(D => \inst_0_RNO[20]\, CLK => lclk_c, Q => - \inst_0[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I202_un1_Y\ : OR2B - port map(A => N594, B => N579, Y => I202_un1_Y_i); - - \comb.branch_address.tmp_ADD_30x30_fast_I107_Y\ : NOR2B - port map(A => N472, B => N468, Y => N527_2); - - un9_ra_I_15 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP_2[0]\, B => \cwp[1]\, Y - => \DWACT_ADD_CI_0_g_array_1_2[0]\); - - \r.d.inst_0[9]\ : DFN1 - port map(D => \inst_0_RNO[9]\, CLK => lclk_c, Q => - \inst_0[9]\); - - \r.x.data_0[8]\ : DFN1E0 - port map(D => \data_0_1[8]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[8]\); - - \r.f.pc_RNO_0[26]\ : NAND2 - port map(A => \tmp[26]\, B => \un2_rstn_5\, Y => - \tmp_m[26]\); - - \r.e.op2_RNO[23]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[23]\, Y => N_307); - - \r.m.result_RNIUSA4[1]\ : OR2B - port map(A => d13, B => \maddress[1]\, Y => \result_m_0[1]\); - - \r.m.ctrl.rd_RNI8KI31[5]\ : XNOR2 - port map(A => \rd_2[5]\, B => \un3_de_ren1[96]\, Y => - un2_rs1_2_5_i_0); - - \r.e.ctrl.inst_RNIJP861[21]\ : AO1B - port map(A => read_1_sqmuxa_i, B => \inst_1[22]\, C => - \inst_1[21]\, Y => read); - - \r.w.s.s\ : DFN1 - port map(D => s_RNO, CLK => lclk_c, Q => s); - - \r.w.s.tba_RNI2FFP5[5]\ : AOI1B - port map(A => \bpdata[17]\, B => aluresult_6_sqmuxa, C => - \tba_m[5]\, Y => \aluresult_1_iv_3[17]\); - - \r.x.result_RNILIE25[8]\ : NOR2A - port map(A => \aluop_RNIGM3N1[2]\, B => \bpdata[8]\, Y => - \bpdata_i_m[8]\); - - \r.w.s.tba_RNIQ07Q5[4]\ : AOI1B - port map(A => \bpdata[16]\, B => aluresult_6_sqmuxa, C => - \tba_m[4]\, Y => \aluresult_1_iv_3[16]\); - - \r.e.op1_RNI3RNF[26]\ : OR2A - port map(A => \un17_casaen_0_0\, B => \op1[26]\, Y => - \op1_RNI3RNF[26]\); - - \r.a.ctrl.inst_RNIPUDB[12]\ : NOR2A - port map(A => \inst[6]\, B => \inst[12]\, Y => - un29_casaen_1); - - \r.x.result_RNI8TQJF[3]\ : AND2 - port map(A => \aluresult_1_iv_4[19]\, B => \bpdata_m_1[3]\, - Y => \aluresult_1_iv_5[19]\); - - \r.w.s.tt_RNI7M7N7[0]\ : AOI1B - port map(A => aluresult_12_sqmuxa_0_0, B => \irl[0]\, C => - \aluresult_1_iv_3[4]\, Y => \aluresult_1_iv_4[4]\); - - \r.a.ctrl.inst_RNIR82H1[20]\ : OR3B - port map(A => N_351_1, B => \inst_2[20]\, C => N_260, Y => - cp_disabled_11_sqmuxa); - - \r.m.y_RNISB823[1]\ : AOI1 - port map(A => \y[1]\, B => aluresult_10_sqmuxa_0, C => - \aluresult_4[1]\, Y => \aluresult_2_iv_1[1]\); - - \comb.lock_gen.un1_icc_check5_RNO_2\ : NOR2B - port map(A => icc_check10, B => icc_check9, Y => - un1_icc_check5_0); - - \r.w.s.et\ : DFN1E0 - port map(D => et_1_0, CLK => lclk_c, E => holdn, Q => et); - - \r.e.op2_RNO_1[10]\ : NOR3C - port map(A => \rfo_m_i[42]\, B => \d_1_iv_2[10]\, C => - \op1_m_i[10]\, Y => \d_1_iv_4[10]\); - - \r.e.op2_RNO_7[5]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[357]\, Y => \cpi_m_i[357]\); - - \r.e.aluop_1_RNIFHJD1[1]\ : XOR3 - port map(A => \un1_iu0_6[27]\, B => \aluop_1[1]\, C => - \un1_iu0_5[93]\, Y => N_6892); - - \r.e.shcnt_RNI8TD86[3]\ : MX2 - port map(A => \shiftin_8[31]\, B => \shiftin_8[23]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[23]\); - - \r.x.ctrl.pc_RNIJQHF[26]\ : MX2 - port map(A => \pc_2[26]\, B => \pc[26]\, S => \npc_1[1]\, Y - => N_3237); - - \r.e.jmpl_RNI2AGPO\ : OR2B - port map(A => \shiftin_17[14]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[14]\); - - \r.d.inst_0_RNO[25]\ : NOR2B - port map(A => rst, B => N_4625, Y => \inst_0_RNO[25]\); - - \r.d.pc_RNI2UGB4[19]\ : MX2 - port map(A => \dpc[19]\, B => \fpc[19]\, S => ra_bpmiss_1, - Y => N_3896); - - \r.f.pc_RNO_2[29]\ : OR2B - port map(A => I_196, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[27]\); - - \r.a.ctrl.inst_RNIJ42L[19]\ : OR2A - port map(A => \inst_2[19]\, B => N_202, Y => N_205); - - \r.e.alusel[0]\ : DFN1E0 - port map(D => N_3838_i_0, CLK => lclk_c, E => holdn, Q => - \alusel[0]\); - - \r.m.y_RNIV9AV2[26]\ : AOI1B - port map(A => \un1_iu0_5[92]\, B => aluresult_7_sqmuxa_0_0, - C => \y_m_1[26]\, Y => \aluresult_1_iv_0[26]\); - - \r.x.ctrl.pc_RNIGB431[5]\ : MX2C - port map(A => \un1_p0_6[357]\, B => \pc_3[5]\, S => - s_3_sqmuxa, Y => N_3396); - - \r.e.op1_RNO[17]\ : MX2C - port map(A => \d_i[17]\, B => \d_i[18]\, S => N_227_0, Y - => \aop1[17]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_Y : NAND2 - port map(A => I260_un1_Y_i_0, B => - ADD_33x33_fast_I260_Y_3_0, Y => N766_0); - - \r.e.op1_RNI8V5RB[15]\ : NOR2 - port map(A => \edata2_0_iv_1[15]\, B => \bpdata_i_m[15]\, Y - => edata2_0_iv(15)); - - \r.e.aluop_RNICEFV[1]\ : NOR2B - port map(A => miscout140_1, B => logicout21_1, Y => - un1_logicout21); - - \r.e.shcnt_RNIP0L54[3]\ : MX2 - port map(A => \shiftin_8[14]\, B => \shiftin_8[6]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[6]\); - - \r.m.icc_RNIJES6[2]\ : AX1 - port map(A => \icc_0[2]\, B => N_211, C => \inst_0[28]\, Y - => branch_3_i); - - \r.f.pc[10]\ : DFN1E0 - port map(D => \pc_1[10]\, CLK => lclk_c, E => holdn, Q => - \fpc[10]\); - - \r.w.result_RNI40P1[10]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[10]\, - Y => \result_m_0_0[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I47_Y\ : NOR2B - port map(A => N419_2, B => N416_2, Y => N464_1); - - \r.m.y_RNO[30]\ : AO1C - port map(A => y14_0, B => \logicout[30]\, C => \y_iv_2[30]\, - Y => \y_1[30]\); - - \r.e.shleft_RNIP496\ : NOR2A - port map(A => \un1_iu0_6[9]\, B => shleft, Y => - \shiftin_5_i[9]\); - - \r.m.ctrl.pc[31]\ : DFN1E0 - port map(D => \pc[31]\, CLK => lclk_c, E => holdn, Q => - \pc_3[31]\); - - \r.e.op2_RNO_1[26]\ : OR2B - port map(A => \op1[26]\, B => un14_casaen_s1, Y => - \op1_m_i[26]\); - - \r.x.ctrl.pc_RNIJMF8[3]\ : MX2 - port map(A => \pc_2[3]\, B => \pc_0[3]\, S => \npc[1]\, Y - => N_3214); - - \r.m.casa_RNISFIB692\ : OR2B - port map(A => me_nullify2_1_0, B => un17_casaen, Y => - nullify); - - \r.f.pc_RNIUDRO73[7]\ : MX2 - port map(A => I_24, B => N_4050, S => bpmiss_1_i_0, Y => - \pc_4[7]\); - - \r.a.imm_RNIDE7U[0]\ : NOR3C - port map(A => \result_m_i[0]\, B => \imm_m_i[0]\, C => - \d_1_iv_1[0]\, Y => \d_1_iv_2[0]\); - - \r.e.aluop_RNIFBIJ1[2]\ : XA1 - port map(A => \un1_iu0_5[79]\, B => \aluop_1[2]\, C => - \un1_iu0_6[13]\, Y => N_3540); - - un37_ra_I_9 : XOR2 - port map(A => \cwp_0[0]\, B => \inst_0_RNI4VUM[4]\, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \r.m.y_RNO[21]\ : AO1C - port map(A => y14_0, B => \logicout[21]\, C => \y_iv_2[21]\, - Y => \y_0[21]\); - - \r.d.inst_0_RNIAO79_0[23]\ : MX2 - port map(A => \un1_p0_6_0[60]\, B => \inst_0_0[23]\, S => - \inst_0[30]\, Y => \inst_0_1[25]\); - - \r.e.shleft_1_RNIQGHP\ : OR2A - port map(A => \un1_iu0_6[21]\, B => shleft_1, Y => - \shiftin_5[21]\); - - \r.e.jmpl_RNIS6CTU1\ : NOR3C - port map(A => \shiftin_17_m[6]\, B => \aluresult_1_iv_7[5]\, - C => \shiftin_17_m_0[5]\, Y => \aluresult_1_iv_9[5]\); - - \r.e.aluop_0_RNIUIRJ2[0]\ : OR2B - port map(A => \logicout[0]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I31_P0N : OR2 - port map(A => \un1_iu0_6[30]\, B => \data_0[30]\, Y => N488); - - \r.x.rstate_RNIASEN3[1]\ : AO1A - port map(A => annul_1_0, B => y6_2, C => \rstate_d[2]\, Y - => et_0_sqmuxa); - - \r.a.rsel1_RNO[1]\ : NOR2A - port map(A => rfe_1_2, B => rfe_1_1, Y => N_4021); - - \r.a.ctrl.inst_RNIFG1L_0[22]\ : NOR2 - port map(A => \inst[22]\, B => N_216, Y => N_6681_1); - - \r.e.shleft_0_RNIHJBD1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[3]\, S => - shleft_0, Y => \shiftin_5[34]\); - - \r.d.inst_0_RNIT5TJ[26]\ : MX2C - port map(A => N_3346, B => N_3347, S => \inst_0[26]\, Y => - N_3348); - - \r.x.ctrl.pc[29]\ : DFN1E0 - port map(D => \pc_3[29]\, CLK => lclk_c, E => holdn, Q => - \pc_2[29]\); - - \r.e.op2_RNO_9[12]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[364]\, Y => \cpi_m_i[364]\); - - \r.e.op2_RNO_1[6]\ : OR2B - port map(A => \op1[6]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[6]\); - - \r.e.jmpl_RNIHHBJU_0\ : OR2B - port map(A => \shiftin_17[29]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[29]\); - - un6_fe_npc_I_159 : AND3 - port map(A => \fe_pc[23]\, B => \fe_pc[24]\, C => - \fe_pc[25]\, Y => \DWACT_FINC_E[17]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I22_P0N : OR2 - port map(A => \un1_iu0_6[21]\, B => \op2[21]\, Y => N461_0); - - \r.e.ctrl.inst_RNIFK0E_0[21]\ : NOR2A - port map(A => \inst_1[22]\, B => \inst_1[21]\, Y => - jump_0_sqmuxa_1_0); - - \r.d.cnt_RNID315[1]\ : NOR3B - port map(A => \inst_0[30]\, B => \inst_0[31]\, C => - \cnt_0[1]\, Y => de_inst_0_sqmuxa_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I321_Y_0 : XNOR2 - port map(A => N766, B => \un6_ex_add_res_s2_1[31]\, Y => - \un6_ex_add_res_s0[31]\); - - \r.a.rfa1[4]\ : DFN1E0 - port map(D => \un3_de_ren1[95]\, CLK => lclk_c, E => holdn, - Q => \rfa1[4]\); - - \r.a.ctrl.inst_RNIOVAT5[20]\ : OR2B - port map(A => cp_disabled_4_0_1_1, B => cp_disabled_4_0_1_0, - Y => cp_disabled_4); - - \r.m.y_RNO_2[6]\ : OR2A - port map(A => \logicout[6]\, B => y14, Y => \logicout_m[6]\); - - \r.f.pc_RNI26HB4[26]\ : MX2 - port map(A => \dpc[26]\, B => \fpc[26]\, S => - \ra_bpmiss_1_0\, Y => N_3903); - - \r.m.y_RNO_3[31]\ : AOI1B - port map(A => \y[31]\, B => y08_0, C => ex_ymsb_1_m, Y => - \y_iv_0[31]\); - - \r.e.op2_RNO[31]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[31]\, Y => N_315); - - un6_ex_add_res_d2_ADD_33x33_fast_I2_G0N : OAI1 - port map(A => \op1[1]\, B => ldbp1_0, C => \data_0[1]\, Y - => N400_1); - - \r.f.pc_RNI3O4Q23[4]\ : NOR2B - port map(A => \un6_fe_npc_m[2]\, B => - \xc_trap_address_m[4]\, Y => \npc_iv_2[4]\); - - \r.e.op2_RNIH11O85_0[0]\ : OR3A - port map(A => \icc_8_1[1]\, B => \op2_RNI1LHG[1]\, C => - \op2_RNI59C6[0]\, Y => \icc_7[1]\); - - \r.a.imm[25]\ : DFN1E0 - port map(D => \un3_de_ren1[143]\, CLK => lclk_c, E => holdn, - Q => \imm[25]\); - - un6_fe_npc_I_73 : XOR2 - port map(A => N_101, B => \fe_pc[14]\, Y => I_73); - - \r.f.pc_RNI6AB62[4]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[4]\, Y => \xc_trap_address_m[4]\); - - \r.e.op2_RNO_5[31]\ : AOI1B - port map(A => \result[31]\, B => d31_0, C => \imm_m_i[31]\, - Y => \d_1_iv_0[31]\); - - \r.x.ctrl.inst_RNI2JBD2[24]\ : OR3A - port map(A => cwp_2_sqmuxa_4, B => annul_1_0, C => - tba_1_sqmuxa_3, Y => cwp_2_sqmuxa_i); - - \r.e.ctrl.pc[29]\ : DFN1E0 - port map(D => \pc[29]\, CLK => lclk_c, E => holdn, Q => - \pc_0[29]\); - - \r.d.inull_RNO_4\ : OR2A - port map(A => jmpl_2, B => annul_2, Y => N_96); - - un6_ex_add_res_d1_ADD_33x33_fast_I86_Y : NOR2B - port map(A => N410_1, B => N407, Y => N545_2); - - \r.e.op1_RNIQCHD[11]\ : MX2 - port map(A => \op1[11]\, B => \data_0_2[11]\, S => ldbp1, Y - => \un1_iu0_6[11]\); - - \r.x.data_0_RNO_0[21]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_21, Y => - \dco_m_0[117]\); - - \r.x.intack_RNO_0\ : NOR2 - port map(A => \tt[6]\, B => \tt[7]\, Y => intack_1); - - \r.m.ctrl.wicc_RNIUN9L\ : MX2A - port map(A => N_4183, B => \icc[3]\, S => wicc_3, Y => - N_4188); - - \r.e.aluop_RNIQUNP8[2]\ : NOR2A - port map(A => \bpdata_i_m_0[14]\, B => \bpdata_i_m_2[6]\, Y - => \edata2_iv_2[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I270_Y_0_a3 : NOR2A - port map(A => N790, B => N_30_0, Y => N_71); - - \r.e.op2_RNO_0[28]\ : OR3C - port map(A => \op1_m_i[28]\, B => \d_1_iv_3[28]\, C => - \aluresult_m_i[28]\, Y => \d_1[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I163_un1_Y : OR2A - port map(A => N574_1, B => N567_2, Y => I163_un1_Y_i); - - \r.m.result_0[1]\ : DFN1E0 - port map(D => \eres2[1]\, CLK => lclk_c, E => holdn, Q => - \maddress_0[1]\); - - \r.e.alusel_RNI5B9LTF[0]\ : AO1 - port map(A => \icc_12_iv_0[1]\, B => \icc_8_m_i[1]\, C => - aluresult12, Y => \icc_16[1]\); - - \r.m.icc_RNO_2[2]\ : MX2 - port map(A => \icc[2]\, B => \icc_2[2]\, S => wicc, Y => - N_4182); - - \comb.branch_address.tmp_ADD_30x30_fast_I241_Y_0_o3\ : AOI1 - port map(A => N_14, B => N716, C => N465, Y => N712_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I263_Y_1 : AO1 - port map(A => N648_0, B => N633_0, C => - ADD_33x33_fast_I263_Y_0_0, Y => ADD_33x33_fast_I263_Y_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I46_Y : AND2 - port map(A => N467_0, B => N470, Y => N505); - - \r.m.y_RNO_0[23]\ : AOI1B - port map(A => wy_1_0, B => \y_0[23]\, C => \y_m_0[23]\, Y - => \y_iv_1[23]\); - - \r.e.op1_RNIDU2LS6[25]\ : NOR3C - port map(A => \op1_m_0[25]\, B => \d_iv_2[25]\, C => - \aluresult_m_0[25]\, Y => \d_i[25]\); - - \r.d.cnt_RNIM0KB[0]\ : AXOI4 - port map(A => un4_op_0, B => \cnt_2[0]\, C => \cnt_0[1]\, Y - => un10_op); - - \r.x.data_0_RNIBF9E[14]\ : XOR2 - port map(A => \data_0[14]\, B => invop2_1, Y => N_4261); - - \r.d.pv_RNO_7\ : NOR3B - port map(A => \inst_0[31]\, B => pv_12_i_a6_0_1, C => - \cnt_0[1]\, Y => pv_12_i_a6_0_2); - - \r.m.ctrl.pc_RNIAIIF[29]\ : MX2 - port map(A => \pc_3[29]\, B => \pc[29]\, S => \npc_1[1]\, Y - => N_3270); - - \r.e.op2_RNI1LHG[1]\ : MX2 - port map(A => \op2[1]\, B => N_3305, S => ldbp2_1, Y => - \op2_RNI1LHG[1]\); - - \r.a.ctrl.inst[31]\ : DFN1E0 - port map(D => \inst_0[31]\, CLK => lclk_c, E => holdn, Q - => \inst[31]\); - - \r.m.ctrl.wicc\ : DFN1E0 - port map(D => wicc_1_1, CLK => lclk_c, E => holdn, Q => - wicc_3); - - \r.e.ctrl.trap_RNI202261\ : NOR3A - port map(A => enaddr_2_sqmuxa_3, B => un1_annul, C => - trap_0, Y => enaddr_2_sqmuxa); - - \r.e.aluop_RNIH2GOB[2]\ : AOI1B - port map(A => \bpdata[8]\, B => aluresult_5_sqmuxa, C => - \aluresult_1_iv_2[24]\, Y => \aluresult_1_iv_4[24]\); - - \r.x.data_0_RNO_4[0]\ : OR2A - port map(A => \data_0[0]\, B => ld_0_0, Y => - \data_0_m_i[0]\); - - \r.e.ctrl.inst[25]\ : DFN1E0 - port map(D => \inst_1[25]\, CLK => lclk_c, E => holdn, Q - => \inst_2[25]\); - - \r.e.aluop_0_RNIB49O1[1]\ : MX2C - port map(A => \logicout_4[7]\, B => N_6871, S => N_6866_i_0, - Y => N_3630); - - un6_ex_add_res_d2_ADD_33x33_fast_I37_Y : MAJ3 - port map(A => \data_0[28]\, B => \un1_iu0_6[28]\, C => - N478_2, Y => N496_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I20_G0N : OA1 - port map(A => \op1[19]\, B => ldbp1_1, C => \data_0[19]\, Y - => N454_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I300_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[10]\, B => N814_0, Y => - \un6_ex_add_res_s0[10]\); - - \r.x.ctrl.pc_RNI8QGF[12]\ : MX2 - port map(A => \pc_0[12]\, B => \pc_2[12]\, S => \npc_0[1]\, - Y => N_3223); - - \r.e.op1[4]\ : DFN1E0 - port map(D => N_167, CLK => lclk_c, E => holdn, Q => - \op1[4]\); - - \r.e.op2_RNO_5[19]\ : AOI1B - port map(A => \result[19]\, B => d31_0, C => \imm_m_i[19]\, - Y => \d_1_iv_0[19]\); - - \r.x.data_0_RNO[13]\ : OR3 - port map(A => \dco_m_0[109]\, B => \data_0_1_0_iv_0[13]\, C - => \data_0_1_4[9]\, Y => \data_0_1[13]\); - - \r.e.aluop[0]\ : DFN1E0 - port map(D => \aluop[0]\, CLK => lclk_c, E => holdn, Q => - \aluop_1[0]\); - - \r.w.s.tba[13]\ : DFN1E1 - port map(D => \result_0[25]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[13]\); - - \r.w.s.icc[2]\ : DFN1E0 - port map(D => \icc_1[2]\, CLK => lclk_c, E => holdn, Q => - \icc[2]\); - - \r.m.result_RNIAGV6[2]\ : OR2B - port map(A => d13_0, B => \maddress[2]\, Y => - \result_m_0[2]\); - - \r.e.shleft_1_RNIV05I1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[11]\, S => - shleft_1, Y => \shiftin_5[42]\); - - \r.e.aluop_RNI72NM9[1]\ : NOR2B - port map(A => \bpdata_m[15]\, B => \bpdata_m_2[7]\, Y => - \aluresult_1_iv_4[15]\); - - un6_fe_npc_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \r.w.s.wim_RNI834N2[1]\ : MX2 - port map(A => \wim[1]\, B => \result_0[1]\, S => - wim_1_sqmuxa, Y => \wim_1[1]\); - - \r.a.imm_RNI3645[2]\ : OR3B - port map(A => d29_0_0, B => \imm[2]\, C => \rsel2_0[0]\, Y - => \imm_m_i[2]\); - - un6_fe_npc_I_132 : AND3 - port map(A => \fe_pc[20]\, B => \fe_pc[21]\, C => - \fe_pc[22]\, Y => \DWACT_FINC_E[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I66_Y : NOR2B - port map(A => N440_0, B => N437, Y => N525_1); - - \r.e.aluop_0_RNI69JD1[2]\ : XA1 - port map(A => \un1_iu0_5[83]\, B => \aluop_0[2]\, C => - \un1_iu0_6[17]\, Y => N_3544); - - \comb.un6_xc_exception\ : AND2 - port map(A => \xc_exception_1_0\, B => rst, Y => - un6_xc_exception); - - \r.x.rstate_0_RNIJUQD2[0]\ : MX2C - port map(A => N_3403, B => \xc_result[12]\, S => - \rstate_0[0]\, Y => \wdata[12]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu_dcache is - - port( data_1_19 : out std_logic; - data_1_18 : out std_logic; - data_1_17 : out std_logic; - data_1_16 : out std_logic; - data_1_15 : out std_logic; - data_1_14 : out std_logic; - data_1_13 : out std_logic; - data_1_12 : out std_logic; - data_1_9 : out std_logic; - data_1_8 : out std_logic; - data_1_5 : out std_logic; - data_1_4 : out std_logic; - data_1_3 : out std_logic; - data_1_2 : out std_logic; - data_1_1 : out std_logic; - data_1_0 : out std_logic; - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - size_1 : out std_logic_vector(1 downto 0); - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - dci_m_94 : out std_logic; - dci_m_93 : out std_logic; - dci_m_91 : out std_logic; - dci_m_90 : out std_logic; - dci_m_89 : out std_logic; - dci_m_88 : out std_logic; - faddr_RNI7879K : out std_logic_vector(0 to 0); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 downto 24); - ctx : out std_logic_vector(7 downto 0); - hrdata_0_d0 : in std_logic; - hrdata_24 : in std_logic; - hrdata_26 : in std_logic; - hrdata_25 : in std_logic; - hrdata_23 : in std_logic; - hrdata_1 : in std_logic; - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - size_0_0 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_0 : in std_logic; - dco_i_2 : out std_logic_vector(132 to 132); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - newtag_1_0_9 : out std_logic; - newtag_1_0_8 : out std_logic; - newtag_1_0_7 : out std_logic; - newtag_1_0_6 : out std_logic; - edata2_0_iv : in std_logic_vector(23 downto 0); - asi_0_0 : out std_logic; - dataout_1 : in std_logic_vector(11 downto 10); - size_1_d0 : in std_logic; - bo_d : in std_logic_vector(2 to 2); - rdatav_0_1_1_iv_7 : out std_logic_vector(6 to 6); - rdatav_0_1_0_iv_0_2_0 : out std_logic; - rdatav_0_1_0_iv_7_2 : out std_logic; - un1_m0_2_0 : in std_logic_vector(35 to 35); - ics : out std_logic_vector(1 downto 0); - maddress_0_2 : in std_logic; - maddress_0_0 : in std_logic; - asi : in std_logic_vector(4 downto 0); - data : out std_logic_vector(31 downto 0); - LVL_RNIT69H911 : in std_logic_vector(0 to 0); - data_1_3_i_a3_6_2 : in std_logic; - data_1_3_i_a3_6_4 : in std_logic; - data_1_3_i_a3_6_0 : in std_logic; - data_1_3_i_a3_6_1 : in std_logic; - data_RNIKU1T4 : in std_logic_vector(16 to 16); - un1_m0_2_73 : in std_logic; - un1_m0_2_2 : in std_logic; - un1_m0_2_4 : in std_logic; - un1_m0_2_10 : in std_logic; - un1_m0_2_9 : in std_logic; - un1_m0_2_40 : in std_logic; - un1_m0_2_5 : in std_logic; - un1_m0_2_1 : in std_logic; - un1_m0_2_7 : in std_logic; - un1_m0_2_68 : in std_logic; - un1_m0_2_38 : in std_logic; - un1_m0_2_42 : in std_logic; - un1_m0_2_59 : in std_logic; - un1_m0_2_58 : in std_logic; - un1_m0_2_67 : in std_logic; - un1_m0_2_43 : in std_logic; - un1_m0_2_65 : in std_logic; - un1_m0_2_77 : out std_logic; - un1_m0_2_34 : in std_logic; - un1_m0_2_78 : out std_logic; - un1_m0_2_75 : out std_logic; - un1_m0_2_6 : in std_logic; - un1_m0_2_29 : in std_logic; - un1_m0_2_19 : in std_logic; - un1_m0_2_23 : in std_logic; - un1_m0_2_60 : in std_logic; - un1_m0_2_79 : out std_logic; - un1_m0_2_80 : out std_logic; - un1_m0_2_81 : out std_logic; - un1_m0_2_84 : out std_logic; - un1_m0_2_83 : out std_logic; - un1_m0_2_86 : out std_logic; - un1_m0_2_76 : out std_logic; - un1_m0_2_15 : in std_logic; - un1_m0_2_11 : in std_logic; - un1_m0_2_18 : in std_logic; - un1_m0_2_85 : out std_logic; - un1_m0_2_54 : in std_logic; - un1_m0_2_71 : in std_logic; - un1_m0_2_55 : in std_logic; - un1_m0_2_70 : in std_logic; - un1_m0_2_61 : in std_logic; - un1_m0_2_69 : in std_logic; - un1_m0_2_37 : in std_logic; - un1_m0_2_66 : in std_logic; - un1_m0_2_56 : in std_logic; - un1_m0_2_64 : in std_logic; - un1_m0_2_62 : in std_logic; - un1_m0_2_57 : in std_logic; - un1_m0_2_41 : in std_logic; - un1_m0_2_94 : in std_logic; - un1_m0_2_91 : in std_logic; - un1_m0_2_106 : in std_logic; - un1_m0_2_96 : in std_logic; - un1_m0_2_92 : in std_logic; - un1_m0_2_95 : in std_logic; - un1_m0_2_97 : in std_logic; - un1_m0_2_93 : in std_logic; - un1_m0_2_98 : in std_logic; - un1_m0_2_33 : in std_logic; - un1_m0_2_72 : in std_logic; - un1_m0_2_39 : in std_logic; - un1_m0_2_63 : in std_logic; - un1_m0_2_44 : in std_logic; - un1_m0_2_35 : in std_logic; - un1_m0_2_36 : in std_logic; - un1_m0_2_0_d0 : in std_logic; - un1_m0_2_3 : in std_logic; - un1_m0_2_12 : in std_logic; - un1_m0_2_82 : out std_logic; - un1_m0_2_8 : in std_logic; - un1_m0_2_31 : in std_logic; - un1_m0_2_108 : in std_logic; - eaddress_7 : in std_logic; - eaddress_3 : in std_logic; - eaddress_0 : in std_logic; - eaddress_8 : in std_logic; - eaddress_1 : in std_logic; - eaddress_4 : in std_logic; - eaddress_12 : in std_logic; - eaddress_16 : in std_logic; - eaddress_24 : in std_logic; - eaddress_2 : in std_logic; - eaddress_20 : in std_logic; - eaddress_5 : in std_logic; - eaddress_15 : in std_logic; - eaddress_27 : in std_logic; - eaddress_17 : in std_logic; - eaddress_9 : in std_logic; - eaddress_19 : in std_logic; - eaddress_23 : in std_logic; - eaddress_25 : in std_logic; - eaddress_10 : in std_logic; - eaddress_6 : in std_logic; - eaddress_18 : in std_logic; - eaddress_28 : in std_logic; - eaddress_13 : in std_logic; - eaddress_21 : in std_logic; - eaddress_22 : in std_logic; - eaddress_29 : in std_logic; - rdatav_0_1_0_iv_5_18 : out std_logic; - rdatav_0_1_0_iv_5_14 : out std_logic; - rdatav_0_1_0_iv_5_15 : out std_logic; - rdatav_0_1_0_iv_5_20 : out std_logic; - rdatav_0_1_0_iv_4_23 : out std_logic; - rdatav_0_1_0_iv_4_9 : out std_logic; - rdatav_0_1_0_iv_4_29 : out std_logic; - rdatav_0_1_0_iv_4_31 : out std_logic; - mcdo_m_0_8 : out std_logic; - mcdo_m_0_5 : out std_logic; - mcdo_m_0_18 : out std_logic; - mcdo_m_0_21 : out std_logic; - mcdo_m_0_22 : out std_logic; - mcdo_m_0_17 : out std_logic; - mcdo_m_0_1 : out std_logic; - mcdo_m_0_28 : out std_logic; - mcdo_m_0_23 : out std_logic; - mcdo_m_0_30 : out std_logic; - data_0_23 : out std_logic; - data_0_22 : out std_logic; - data_0_19 : out std_logic; - data_0_18 : out std_logic; - data_0_7 : out std_logic; - data_0_15 : out std_logic; - data_0_12 : out std_logic; - data_0_0 : out std_logic; - data_0_26 : out std_logic; - data_0_4 : out std_logic; - data_0_21 : out std_logic; - data_0_11 : out std_logic; - data_0_8 : out std_logic; - data_0_28 : out std_logic; - data_0_17 : out std_logic; - data_0_16 : out std_logic; - data_0_25 : out std_logic; - data_0_14 : out std_logic; - data_0_20 : out std_logic; - data_0_27 : out std_logic; - data_0_30 : out std_logic; - data_0_13 : out std_logic; - data_0_29 : out std_logic; - data_0_24 : out std_logic; - data_0_31 : out std_logic; - dataout : in std_logic_vector(35 downto 0); - ctxp_13 : out std_logic; - ctxp_16 : out std_logic; - ctxp_7 : out std_logic; - ctxp_10 : out std_logic; - ctxp_3 : out std_logic; - ctxp_8 : out std_logic; - ctxp_19 : out std_logic; - ctxp_17 : out std_logic; - ctxp_15 : out std_logic; - ctxp_14 : out std_logic; - ctxp_20 : out std_logic; - ctxp_18 : out std_logic; - ctxp_6 : out std_logic; - ctxp_21 : out std_logic; - ctxp_11 : out std_logic; - ctxp_4 : out std_logic; - ctxp_25 : out std_logic; - ctxp_0 : out std_logic; - ctxp_22 : out std_logic; - ctxp_23 : out std_logic; - ctxp_24 : out std_logic; - ctxp_5 : out std_logic; - ctxp_12 : out std_logic; - ctxp_9 : out std_logic; - ctxp_1 : out std_logic; - ctxp_2 : out std_logic; - diagdata_6 : in std_logic; - diagdata_7 : in std_logic; - diagdata_1 : in std_logic; - diagdata_3 : in std_logic; - diagdata_5 : in std_logic; - diagdata_29 : in std_logic; - diagdata_22 : in std_logic; - diagdata_27 : in std_logic; - diagdata_20 : in std_logic; - diagdata_8 : in std_logic; - diagdata_25 : in std_logic; - diagdata_18 : in std_logic; - diagdata_31 : in std_logic; - diagdata_17 : in std_logic; - diagdata_24 : in std_logic; - diagdata_23 : in std_logic; - diagdata_21 : in std_logic; - diagdata_16 : in std_logic; - diagdata_12 : in std_logic; - diagdata_9 : in std_logic; - diagdata_26 : in std_logic; - diagdata_0 : in std_logic; - diagdata_19 : in std_logic; - diagdata_14 : in std_logic; - diagdata_15 : in std_logic; - diagdata_2 : in std_logic; - diagdata_13 : in std_logic; - diagdata_30 : in std_logic; - diagdata_4 : in std_logic; - diagdata_28 : in std_logic; - address : out std_logic_vector(31 downto 0); - addr_30 : out std_logic; - addr_11 : out std_logic; - addr_6 : out std_logic; - addr_4 : out std_logic; - addr_7 : out std_logic; - addr_5 : out std_logic; - addr_3 : out std_logic; - addr_8 : out std_logic; - addr_10 : out std_logic; - addr_9 : out std_logic; - addr_2 : out std_logic; - dataout_0 : in std_logic_vector(31 downto 0); - maddress : in std_logic_vector(31 downto 0); - un1_p0_2_0 : out std_logic_vector(498 to 498); - ctx_0 : out std_logic_vector(7 downto 0); - size_1z : out std_logic; - enable : out std_logic; - N_10 : out std_logic; - write : in std_logic; - eenaddr : in std_logic; - msu : in std_logic; - su : out std_logic; - read_3 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - N_415 : in std_logic; - N_351 : in std_logic; - flush_RNIGBB873 : out std_logic; - N_192 : in std_logic; - N_190_0 : in std_logic; - diagrdy : in std_logic; - burst_0 : out std_logic; - N_264_0 : in std_logic; - N_425 : out std_logic; - trans_op_0 : out std_logic; - flush_op_i_0 : out std_logic; - trans_op : out std_logic; - un2_m_tlb_type : in std_logic; - tlbdis : out std_logic; - read_2 : out std_logic; - grant : in std_logic; - N_317_0 : in std_logic; - N_2886 : in std_logic; - N_2887 : in std_logic; - N_270 : out std_logic; - N_269 : out std_logic; - N_267 : out std_logic; - N_353 : in std_logic; - N_259 : out std_logic; - N_258 : out std_logic; - N_236_0 : in std_logic; - N_417 : in std_logic; - N_144 : out std_logic; - N_3846 : out std_logic; - e : out std_logic; - N_421_0 : in std_logic; - N_3305 : out std_logic; - nf : out std_logic; - N_262_0 : in std_logic; - un54_fault_pro_m : in std_logic; - M_m : in std_logic; - r_N_6 : in std_logic; - vaddr_1_sqmuxa_0_a2_2 : out std_logic; - fault_pro : in std_logic; - stpend_RNI6P41NG3 : out std_logic; - read_1 : in std_logic; - read_RNIQH64D1 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIRO4K31 : out std_logic; - N_3389_i_0 : out std_logic; - read_RNI0IQ7R : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNICKHE91 : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - un59_nbo : in std_logic; - lock_m : out std_logic; - N_2699_i_0 : in std_logic; - mexc_1 : out std_logic; - N_3239_i_0 : out std_logic; - N_2701 : in std_logic; - N_2703_i_0 : in std_logic; - N_2714 : in std_logic; - N_3227_i_0 : out std_logic; - N_3387_i_0 : out std_logic; - N_26 : out std_logic; - read_RNIEKS231 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIC9O9B1 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNICAQK41 : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIEEGDD1 : out std_logic; - N_12_i_0 : out std_logic; - N_16_i_0 : out std_logic; - N_696 : in std_logic; - N_695 : in std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - N_2702_i_0 : in std_logic; - N_2717 : in std_logic; - N_2720 : in std_logic; - N_694 : in std_logic; - N_2711_i_0 : in std_logic; - fsread_i_0 : out std_logic; - N_24 : out std_logic; - N_329 : out std_logic; - N_330 : out std_logic; - N_78_0 : in std_logic; - ba : in std_logic; - hcache : in std_logic; - cache : out std_logic; - cdwrite_0_sqmuxa_i_0_0 : in std_logic; - lock_0 : out std_logic; - un17_casaen_0_0 : in std_logic; - mexc : in std_logic; - me_nullify2_1_2 : in std_logic; - nullify2_0_sqmuxa : in std_logic; - flush : in std_logic; - hold_0 : in std_logic; - fault_pro67 : in std_logic; - req : out std_logic; - intack : in std_logic; - N_523 : out std_logic; - fault_pri : in std_logic; - iflush_1_0_a2_0 : out std_logic; - N_419 : in std_logic; - N_2709_i_0 : in std_logic; - nullify : in std_logic; - flush_i_0 : in std_logic; - N_293 : in std_logic; - read_0 : in std_logic; - rst : in std_logic; - burst : out std_logic; - accexc_6 : in std_logic; - un1_addout_12 : in std_logic; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : out std_logic; - G_80_0 : in std_logic; - lock : in std_logic; - ready : in std_logic; - mmudci_trans_op_1_sqmuxa_1 : out std_logic; - hold : out std_logic; - enaddr : in std_logic; - N_425_0 : out std_logic; - N_121 : out std_logic; - N_3254_0 : out std_logic; - e_0 : out std_logic; - lclk_c : in std_logic - ); - -end mmu_dcache; - -architecture DEF_ARCH of mmu_dcache is - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \ctx_RNIB8BR[0]\, \ctx_0_0_RNIQIPQ[1]\, - \ctx_RNIFGBR[2]\, \ctx_RNIAM7T[3]\, \ctx_0_0_RNI7TTO[4]\, - \ctx_0_0_RNI91UO[5]\, \ctx_RNIN0CR[6]\, - \ctx_0_0_RNID9UO[7]\, N_2710_i, e_0_sqmuxa_RNIQKNL, - \dstate_2[7]\, \dstate_nss[1]\, \dstate_1[7]\, - \dstate_0[7]\, \dstate_0[2]\, \dstate_nss[6]\, - paddress_1_sqmuxa_0, N_487, N_506, addr_1_sqmuxa_0, - dwrite_1_sqmuxa, rdatasel_1_sqmuxa_1_0, N_3253_i, N_526, - mexc_0_sqmuxa_0_0, data2_0_sqmuxa_1, holdn_2_sqmuxa, - mexc_0_sqmuxa_0, addr_1_sqmuxa_2_0, un18_m_en, - \dstate_i_0[8]\, N_328, addr_2_sqmuxa_0, un47_m_en, - N_3331, data1_0_sqmuxa_0, stpend_0_sqmuxa, - \dstate_RNI5GFM4[5]\, rdatav_0_6_sqmuxa_0, - rdatav_0_6_sqmuxa_3, N_2165_0, burst_0_sqmuxa, - rdatav_012_0, nomds, \dstate_i[8]\, \dstate_i_2[8]\, - \dstate_nss_i_0[0]\, \dstate_i_1[8]\, - tdiagwrite_1_0_0_o2_1, N_3749, N_3748, N_484_0, - un1_m_en_2, un1_m_en_1, \e_0\, req_0_sqmuxa_1_0, N_566, - dstate_14, N_3331_0, N_485, N_486_0, vaddr_1_sqmuxa_0, - vaddr_1_sqmuxa_0_0, ctxp_1_sqmuxa_0_0, e_0_sqmuxa_2, - ctxp_1_sqmuxa_0, N_3344_i_0_0, N_3321, edata_0_sqmuxa_i_0, - edata_0_sqmuxa_1, N_3443_i, \dstate[1]\, N_20, \faddr[1]\, - \faddr[0]\, N_12, \faddr[3]\, \DWACT_FINC_E[0]\, N_500_i, - N_499, un6_validrawv, N_3041_11, N_3514, N_139_i_i, - un1_dci_2_i, un1_dci_5_i, un1_dci_13_i, N_559, N_3747, - N_502, N_501, \dcs[0]\, addr_1_sqmuxa_1, addr_0_sqmuxa_2, - N_3715, N_514, \dcramo_m_i[255]\, N_2088, \edata_m_i[31]\, - ddatainv_0_6_sqmuxa, \edata[31]\, \dcramo_m_0[252]\, - \ico_m[162]\, \ctxp_m[2]\, \dcramo_m_0[228]\, - \ico_m[138]\, N_3723, \dcramo_m_0[254]\, \ico_m[164]\, - N_264, \dcramo_m_i[242]\, \xaddress_RNI1CIE2_0[0]\, - \edata_m_i[18]\, \edata[18]\, \dcramo_m_i[251]\, - \edata_m_i[27]\, \edata[27]\, burst_2_sqmuxa_m3_e, - burst_2_sqmuxa_m3_e_RNO, burst_16_m, burst_16_m_0, - \dstate_RNO_8[4]\, dstate_ns_0_2065_0, - twrite_14_iv_0_a2_a0, un1_addout_13_i, - twrite_14_iv_0_a2_a0_4, burst_2_sqmuxa_m8_0_a4_0, - burst_2_sqmuxa_m8_0_a4_0_2, N_1_28_i, - twrite_14_iv_0_o2_a0_4, N_3654, - \vmaskraw_1_i_o2_i_a2_0_0[1]\, N_3661, - \vmaskraw_1_i_o2_i_a3_0_a2_0_0[3]\, \addr_1[10]\, - \addr_1_1_iv_0_3[10]\, e_0_sqmuxa, e_0_sqmuxa_0, - ctxp_1_sqmuxa, mmctrl1wr, \addr[3]\, \addr[8]\, - \ddatainv_0_1_0_iv_0[18]\, \ddatainv_0_1_0_iv_0[27]\, - \ddatainv_0_1_0_iv_0[31]\, un1_dci_NE_3, un1_dci_NE_1, - \rdatav_0_1_0_iv_7[4]\, \rdatav_0_1_0_iv_6[4]\, - \rdatav_0_1_0_iv_5[4]\, \rdatav_0_1_0_iv_4[4]\, - \ctx_m[4]\, \rdatav_0_1_0_iv_3[30]\, - \rdatav_0_1_1_iv_5[28]\, N_421, \addr[2]\, - \addr_1_1_iv_0_2[10]\, \addr_1_1_iv_0_1[10]\, - twrite_14_iv_0_o2_a0_3, twrite_14_iv_0_a2_a0_3, - \addr_1_1_iv_0_1[31]\, N_3652, \addr_1_1_iv_0_0[31]\, - burst_1_sqmuxa_1, burst_1_sqmuxa_0, data2_1_sqmuxa, - N_3151, N_3499, N_16887_tz_tz, burst_2_sqmuxa_m8_0_a4_0_1, - \addr_1_1_iv_0_2[29]\, \addr_1_1_iv_0_1[29]\, N_261, - \addr_1_1_iv_0_0[29]\, \addr_1_1_iv_0_2[31]\, - \dstate_ns_i_a4_i_9[0]\, N_611, \dstate_ns_i_a4_i_8[0]\, - \dstate_ns_i_a4_i_6[0]\, N_3680_i, N_3679, - \dstate_ns_i_a4_i_4[0]\, N_3683_i, N_3815, N_3682, - \dstate_ns_i_a4_i_2[0]\, \dcs_RNIBN6EB[0]\, - \dstate_ns_i_a4_i_0[0]\, N_3685, N_3677, - \dstate_ns_i_a4_i_a2_7_0[0]\, N_519, holdn_0_0, - stpend_1_0, holdn_1_5, \dstate_ns_i_a4_i_a2_0[0]\, N_507, - N_3745, req_1_2, req_0_sqmuxa_3_1, N_547, req_1_1, - N_2471_i, burst_1_m8_i_0, burst_0_sqmuxa_5, holdn_0_5, - holdn_0_3, holdn_1_sqmuxa_3, holdn_1_sqmuxa, holdn_0_1, - N_3750, dstate_0_sqmuxa, dstate_tr22_2, N_3545, N_3089_7, - dstate_tr22_1, \dstate_RNO_5[1]\, N_3086_i, - dstate_tr22_15_N_10_i, \dstate_ns_0_3[4]\, - dstate_tr16_13_0_0_a2_0_5, \dstate_ns_0_2[4]\, - \dstate_RNO_6[4]\, \dstate_ns_0_0[4]\, dstate_ns_0_2064_1, - N_3511, N_3181, burst_1_m8_i_a5_0, burst_2_sqmuxa_m8_0_0, - burst_1_iv_2, holdn_1, holdn_3_sqmuxa_0_0_2, N_3611, - holdn_0, N_3604, flush_0_0, I_31_1, flush_0_sqmuxa_0, - dstate_tr16_10_0_i_2, dstate_tr16_10_0_i_0, N_395, - N_581_i, burst_1_m8_i_o5_0, req_2_sqmuxa_1_0, - \addr_1_1_iv_2[26]\, \dci_m[34]\, \addr_1_1_iv_0[26]\, - \addr_m[26]\, \paddress[26]\, \mmudco_m[28]\, - \addr_1_1_iv_2[30]\, \dci_m[38]\, \addr_1_1_iv_0[30]\, - \addr_m[30]\, \paddress_m[30]\, \addr_1_1_iv_2[25]\, - \dci_m[33]\, \addr_1_1_iv_0[25]\, \addr_m[25]\, - \paddress[25]\, \mmudco_m[27]\, \addr_1_1_iv_0_2[28]\, - N_3888, \addr_1_1_iv_0_0[28]\, N_214, N_3839, N_213, - \addr_1_1_iv_0_2[27]\, N_250, \addr_1_1_iv_0_0[27]\, - N_253, N_249, N_546, N_262, N_544, N_3716, - \addr_1_1_iv_0_2[24]\, N_3634, \addr_1_1_iv_0_0[24]\, - N_3739, N_545, N_3740, holdns_iv_0_1, N_3615, - holdns_iv_0_0, holdns_iv_0_a2_2_3, - \dstate_i_RNIF4S5B92[8]\, N_3614, \addr_1_1_iv_2[15]\, - \dci_m[23]\, \addr_1_1_iv_0[15]\, \addr_m[15]\, N_673, - \mmudco_m[17]\, \addr_1_1_iv_0_2[12]\, N_277, - \addr_1_1_iv_0_0[12]\, N_280, N_676, N_278, - faddr_1_sqmuxa_0, \un1_p0_2_0[498]\, holdn_3_sqmuxa_0_0_0, - e_0_0_RNI8APPC92, N_510, \addr_1_1_iv_2[16]\, \dci_m[24]\, - \addr_1_1_iv_0[16]\, \addr_m[16]\, \paddress_m[16]\, - \addr_1_1_iv_0_2[14]\, N_3636, \addr_1_1_iv_0_0[14]\, - N_3728, N_554, N_3729, \addr_1_1_iv_0_2[17]\, N_3640, - \addr_1_1_iv_0_0[17]\, N_3721, N_553, N_3722, - \addr_1_1_iv_0_2[13]\, N_272, \addr_1_1_iv_0_0[13]\, - N_275, N_677, N_273, ready_0_sqmuxa_0_2, - ready_0_sqmuxa_0_a2_1_0, N_3697, ready_0_sqmuxa_0_0, - N_511, ready_0_sqmuxa_0_a2_1, N_572, cctrlwr13, - mmudci_diag_op_1_0_a2_0, N_3790, - dstate_tr22_15_m8_i_a5_0_0, N_3586, N_595, - \mmudco_m_0[102]\, \mmudco_m_0[106]\, \mmudco_m_0[101]\, - \addr_1_1_iv_0_a3_2_0[29]\, \addr_1_1_iv_0_a3_2_0[27]\, - \addr_1_1_iv_0_a3_1_0[28]\, \dstate_ns_0_0_1[1]\, - \dstate_ns_0_0_a2_0[1]\, N_3781, \dstate_ns_0_0_0[1]\, - N_585, N_3707, N_3505_i, dstate_tr16_13_0_0_a2_0_3, - dstate_tr16_13_0_0_a2_0_1, N_114_i_i_0, - dstate_tr16_13_0_0_a2_0_0, \mmudco_m_0[91]\, - \addr_1_1_iv_0_a3_2_0[12]\, dstate_tr22_15_a2_2_m8_i_0_0, - dstate_tr22_15_a2_2_m8_i_0_tz, N_3576, N_3583, - burst_1_sqmuxa_3, data2_0_sqmuxa, burst_0_sqmuxa_3, - holdns_iv_0_a2_1_0, e_RNIKN3D, N_489, N_481, - holdns_iv_0_a2_2_1, holdn_3_sqmuxa_0_0_a2_2_0, N_590, - \dstate_ns_0_0_o2_0[1]\, N_3746, ready_RNO_7, - mexc_1_m_0_1, N_176, N_175, N_174, \dstate_ns_0_6[3]\, - \dstate_ns_0_7_i[3]\, \dstate_ns_0_1[3]\, - \dstate_RNO_4[5]\, \dstate_ns_0_5[3]\, N_3028, - \dstate_ns_0_2_0[3]\, \dstate_ns_0_3[3]\, N_2996_8, - \dstate_ns_0_4_tz[3]\, N_29, N_3180_i, N_3035, - dstate_tr22_15_a2_2_m8_i_a5_1_1, - dstate_tr22_15_a2_2_m8_i_a5_1_0, dstate_tr22_15_a2_14_1_0, - N_459, \addr_1_1_iv_0_2[19]\, N_221, - \addr_1_1_iv_0_0[19]\, N_224, N_3837, N_3890, - \addr_1_1_iv_0_2[21]\, N_3638, \addr_1_1_iv_0_0[21]\, - N_3718, N_3717, \addr_1_1_iv_0_2[20]\, N_3860, - \addr_1_1_iv_0_0[20]\, N_3863, N_3859, N_3862, - \addr_1_1_iv_0_2[22]\, N_3871, \addr_1_1_iv_0_0[22]\, - N_185, N_3870, N_3873, \addr_1_1_iv_0_2[18]\, N_187, - \addr_1_1_iv_0_0[18]\, N_190, N_3841, N_189, - \addr_1_1_iv_0_2[23]\, N_216, \addr_1_1_iv_0_0[23]\, - N_3889, N_3838, N_218, \req_0_sqmuxa[0]\, - mexc_1_m_0_2000_0, mexc_1_m_0_2000_tz_1, - mexc_1_m_0_a2_1_0, mexc_0_sqmuxa_1, cctrlwr11_0, - vaddr_1_sqmuxa_0_a2_a0_0, dstate_tr22_15_a2_1_1_0, - \ics_0_i_0[1]\, un19_eholdn_3, - \mmudci_fsread_1_sqmuxa_0_a2_0\, un30_m_en, N_527, N_3758, - N_3778, \dcs_0_i_0_a2_0[1]\, dfrz, \ics_0_i_0[0]\, - \N_523\, burst_1_iv_2_1, un116_m_en_m, burst_19_m, - dstate_tr16_13_0_0_a2_0, holdn_0_sqmuxa_1_m8_0_a2_5, - holdn_0_sqmuxa_1_m8_0_a2_3, holdn_0_sqmuxa_1_m8_0_a2_1, - cctrlwr19_2_0_a2_1_1, dcs_1_i_s_0_o2_0_RNIMMIH9, - holdn_0_sqmuxa_1_m8_0_a2_0, N_576, \ics_0_i_a4_1_0[1]\, - ifrz, burst_3_m_3, burst_3_m_1, burst_0_sqmuxa_2, - burst_2_sqmuxa_2, dstate_tr22_15_0_a2_1, - dstate_tr22_15_0_a2_0, N_666, dstate_tr20_2, - dstate_tr20_0, dstate_tr22_15_a2_3_1_0, d_m6_i_a3_1, - holdn_RNO_20, cctrlwr19_1_0, un1_eholdn_2, \un1_dci_5[0]\, - N_16886_tz_tz, flush_0_sqmuxa_0_o3_i_o2_5, - flush_0_sqmuxa_0_o3_i_o2_0, flush_0_sqmuxa_0_o3_i_o2_4, - flush_0_sqmuxa_0_o3_i_o2_2, cctrlwr, \dstate_ns_0_0_0[8]\, - \dstate_ns_0_0_a2_0_3[8]\, N_135, lock_1_iv_0_a2_1_0, - \addr_1_1_iv_2[1]\, \addr_1_1_iv_0[1]\, \addr_m[1]\, - \mmudco_m[3]\, \paddress[1]\, \mmudco_m[77]\, - \addr_1_0_iv_0_3[2]\, \addr_1_0_iv_0_1[2]\, N_315, N_314, - N_316, N_317, N_318, \addr_1_1_iv_0_2[3]\, - \addr_1_1_iv_0_0[3]\, N_295, N_293_0, - \dstate_RNIP22L4[7]\, N_675, N_294, \addr_1_1_iv_0_2[5]\, - \addr_1_1_iv_0_0[5]\, N_290, N_288, - \addr_1_1_iv_0_a3_0_0[5]\, N_289, \addr_1_1_iv_0_2[4]\, - \addr_1_1_iv_0_0[4]\, \addr_m[4]\, \mmudco_m[6]\, N_678, - \mmudco_m[80]\, \addr_1_1_iv_1[0]\, dstate_19, - \addr_1_1_iv_0[0]\, \paddress[0]\, \mmudco_m[76]\, - \addr_1_1_iv_0_2[6]\, \paddress[6]\, N_3792, N_3731, - \addr_1_1_iv_0_1[6]\, N_3733, N_3628, N_3732, - \addr_1_1_iv_0_3[7]\, N_3735, N_3734, - \addr_1_1_iv_0_1[7]\, \addr_1_1_iv_0_0[7]\, N_3737, - twrite_14_iv_0_o2_0_0, twrite_14_iv_0_o2_a1_3, - twrite_11_m, \addr_1_1_iv_2[9]\, \mmudco_m[11]\, - \addr_1_1_iv_0[9]\, \dci_m[17]\, \paddress[9]\, - \mmudco_m[85]\, \addr_1_1_iv_2[8]\, \mmudco_m[10]\, - \addr_1_1_iv_0[8]\, \dci_m[16]\, \paddress[8]\, - \mmudco_m[84]\, \addr_1_1_iv_0_1[11]\, - \addr_1_1_iv_0_0[11]\, \addr_1_1_iv_0_a3_0[11]\, N_284, - N_3726, N_3641, N_3642, \paddress[10]\, N_3725, - vaddr_1_sqmuxa_0_a2_5, vaddr_1_sqmuxa_0_a2_3, - dcs_1_i_s_0_o2_0_RNIAN3E3, vaddr_1_sqmuxa_0_a2_1, - stpend_RNI07PA2, vaddr_1_sqmuxa_0_a2_0, - twrite_14_iv_0_o2_a0_1, setrepl_0_sqmuxa_1_m_i_5_4, - twrite_14_iv_0_o2_a1_0, un1_dci_12_0, - twrite_14_iv_0_a2_a0_1, flush_i, mexc_0_sqmuxa, - twrite_14_iv_0_o2_a1_2, twrite_14_iv_0_o2_a1_1, - twrite_14_iv_0_a2_a1_2, twrite_14_iv_0_a2_a1_0, - \dstate_ns_i_a4_i_a2_3_2[0]\, - \dstate_ns_i_a4_i_a2_3_0[0]\, N_3788, - \dstate_ns_i_a4_i_a2_16_0[0]\, N_496, - \vaddr_1_sqmuxa_0_a2_4_m1_e_24\, - vaddr_1_sqmuxa_0_a2_4_m1_e_21, - vaddr_1_sqmuxa_0_a2_4_m1_e_20, - vaddr_1_sqmuxa_0_a2_4_m1_e_22, - vaddr_1_sqmuxa_0_a2_4_m1_e_19, - vaddr_1_sqmuxa_0_a2_4_m1_e_13, - vaddr_1_sqmuxa_0_a2_4_m1_e_12, - vaddr_1_sqmuxa_0_a2_4_m1_e_11, - vaddr_1_sqmuxa_0_a2_4_m1_e_16, - vaddr_1_sqmuxa_0_a2_4_m1_e_10, - vaddr_1_sqmuxa_0_a2_4_m1_e_9, - vaddr_1_sqmuxa_0_a2_4_m1_e_3, - vaddr_1_sqmuxa_0_a2_4_m1_e_5, - vaddr_1_sqmuxa_0_a2_4_m1_e_2, lock_1_iv_0_a2_0, \req\, - \dstate_ns_i_a4_i_o2_11_2[0]\, - \dstate_ns_i_a4_i_o2_11_0[0]\, N_72_i, ready_0, - \dstate[5]\, stpend, \paddress[11]\, \paddress[5]\, - \addr[5]\, burst_19_m_0, \dstate_ns_i_a4_i_a2_6_0[0]\, - N_522, \rdatav_0_1_1_iv_i_a2_6[3]\, - \rdatav_0_1_1_iv_i_a2_5[3]\, \rdatav_0_1_1_iv_i_a2_2[3]\, - \rdatav_0_1_1_iv_i_a2_1[3]\, \rdatav_0_1_1_iv_i_a2_4[3]\, - \ctx_0[3]\, miscdata_2_sqmuxa, \rdatav_0_1_6[3]\, - \dcs[1]\, rdatav_0_0_sqmuxa, N_3399, N_3400, N_3403, - N_3401, dstate_19_4, addr_3_sqmuxa, dstate_19_3, - dstate_19_1, \dstate[0]\, \dstate[3]\, - \rdatav_0_1_0_iv_3[13]\, \dcramo_m_0[237]\, - \rdatav_0_1_0_iv_2[13]\, \mmudco_m[56]\, - \rdatav_0_1_0_iv_0[13]\, \ctxp_m[11]\, \data2_m[13]\, - \rdatav_0_1_1_iv_3[11]\, \rdatav_0_1_1_iv_2[11]\, - \ico_m_0[145]\, \rdatav_0_1_1_iv_1[11]\, - rdatav_0_1_sqmuxa, \data2_m[11]\, rdatav_0_2_sqmuxa, - \dstate_ns_i_a4_i_o2_9_2[0]\, - \dstate_ns_i_a4_i_o2_9_0[0]\, N_3811, - \dstate_ns_i_a4_i_a2_15_0[0]\, \ctxp_m[0]\, - \rdatav_0_1_0_iv_4[2]\, \rdatav_0_1_0_iv_6[2]\, - \dcramo_m_0[226]\, \ctx_0[2]\, \rdatav_0_1_0_iv_3[2]\, - \rdatav_0_1_0_iv_1[2]\, \rdatav_0_1_0_iv_2[2]\, - \mmudco_m[38]\, \dcramo_m[410]\, \data2_m[2]\, - \dcramo_m[98]\, mexc_1_m_0_a2_3_0, mexc_0, - mexc_1_m_0_a2_4_0, N_84, \rdatav_0_1_0_iv_i_a4_6[1]\, - nf_m, \rdatav_0_1_0_iv_i_a4_4[1]\, \dcramo_m_0[225]\, - N_3232, \rdatav_0_1_0_iv_i_a4_1[1]\, - \rdatav_0_1_0_iv_i_a4_3[1]\, miscdata_3_sqmuxa, N_3231, - rdatasel_3_sqmuxa, \rdatav_0_1_0_iv_i_a4_0[1]\, N_89, - N_3233, \rdatav_0_1_0_iv_0_5[15]\, \dcramo_m_0[239]\, - \rdatav_0_1_0_iv_0_4[15]\, tlbdis_m, - \rdatav_0_1_0_iv_0_2[15]\, \ctxp_m[13]\, - \rdatav_0_1_0_iv_0_0[15]\, N_205, \mmudco_m[58]\, - \data2[15]\, N_204, \rdatav_0_1_0_iv_5[14]\, - \dcramo_m_0[238]\, \rdatav_0_1_0_iv_4[14]\, - \rdatav_0_1_0_iv_3[14]\, \mmudco_m[57]\, - \rdatav_0_1_0_iv_1[14]\, miscdata_0_sqmuxa, flush_m, - \rdatav_0_1_0_iv_0[14]\, \data2[14]\, \dcramo_m[110]\, - \ctxp_m[17]\, \rdatav_0_1_0_iv_2[19]\, - \rdatav_0_1_0_iv_4[19]\, \dcramo_m_0[243]\, - \mmudco_m[62]\, \rdatav_0_1_0_iv_0[19]\, \data2[19]\, - \dcramo_m[115]\, \rdatav_0_1_1_iv_0_6[7]\, N_3312, - \rdatav_0_1_1_iv_0_5[7]\, \rdatav_0_1_1_iv_0_4[7]\, - \rdatav_0_1_1_iv_0_2[7]\, \mmudco_m[41]\, - \rdatav_0_1_1_iv_0_0[7]\, N_3302, N_3311, N_3314, - \dcramo_m[415]\, \rdatav_0_1_0_iv_7[0]\, - \rdatav_0_1_0_iv_6[0]\, e_m, \rdatav_0_1_0_iv_4[0]\, - \dcramo_m_0[224]\, \rdatav_0_1_0_iv_2[0]\, - \rdatav_0_1_0_iv_1[0]\, \ctx_m[0]\, \ics_m[0]\, - \dcramo_m[408]\, \data2_m[0]\, \dcramo_m[96]\, - \rdatav_0_1_0_iv_3[26]\, \dcramo_m_0[250]\, - \rdatav_0_1_0_iv_2[26]\, \rdatav_0_1_0_iv_1[26]\, - \dcramo_m[122]\, \data2_m[26]\, \mmudco_m[69]\, - \ctxp_m[7]\, \rdatav_0_1_0_iv_1[9]\, - \rdatav_0_1_0_iv_3[9]\, \dcramo_m_0[233]\, - \rdatav_0_1_0_iv_0[9]\, \data2_m[9]\, \dcramo_m_0[105]\, - \rdatav_0_1_0_iv_0_3[12]\, N_160, - \rdatav_0_1_0_iv_0_2[12]\, \mmudco_m[55]\, - \rdatav_0_1_0_iv_0_0[12]\, \ctxp_m[10]\, \data2_m[12]\, - N_159, \rdatav_0_1_0_iv_0_1[10]\, N_3306, N_3304, N_167, - \rdatav_0_1_1_iv_5[16]\, \dcramo_m_0[240]\, - \rdatav_0_1_1_iv_4[16]\, \rdatav_0_1_1_iv_2[16]\, - \mmudco_m[59]\, \ctxp_m[14]\, \rdatav_0_1_1_iv_0[16]\, - burst_m, \data2_m[16]\, \dcramo_m[112]\, - \rdatav_0_1_1_iv_5[21]\, \dcramo_m_0[245]\, - \rdatav_0_1_1_iv_4[21]\, \rdatav_0_1_1_iv_2[21]\, - \rdatav_0_1_1_iv_1[21]\, \ctxp_m[19]\, miscdata_4_sqmuxa, - \dcramo_m[117]\, \data2_m[21]\, \ctxp_m[21]\, - \rdatav_0_1_0_iv_1[23]\, \rdatav_0_1_0_iv_3[23]\, - \dcramo_m_0[247]\, \dcramo_m[119]\, \data2_m[23]\, - \mmudco_m[66]\, \ctxp_m[4]\, \rdatav_0_1_1_iv_4[6]\, - \rdatav_0_1_1_iv_6[6]\, \ico_m[140]\, - \rdatav_0_1_1_iv_1[6]\, \mmudco_m[42]\, - \rdatav_0_1_1_iv_3[6]\, \ctx_m[6]\, \dcramo_m[414]\, - \data2_m[6]\, \dcramo_m[102]\, \dcramo_m[100]\, - \rdatav_0_1_0_iv_1[4]\, \rdatav_0_1_0_iv_3[4]\, ifrz_m, - \dcramo_m[412]\, \data2_m[4]\, \rdatav_0_1_0_iv_5[24]\, - \ctxp_m[22]\, \rdatav_0_1_0_iv_2[24]\, - \rdatav_0_1_0_iv_4[24]\, \dcramo_m_0[248]\, - \mmudco_m[67]\, \rdatav_0_1_0_iv_0[24]\, \data2_m[24]\, - \dcramo_m[120]\, \rdatav_0_1_0_iv_4[30]\, \ctxp_m[28]\, - \rdatav_0_1_0_iv_1[30]\, \rdatav_0_1_0_iv_0[30]\, - \data2_m[30]\, \rdatav_0_1_1_iv_5[17]\, \dcramo_m_0[241]\, - \rdatav_0_1_1_iv_4[17]\, \mmudco_m[60]\, - \rdatav_0_1_1_iv_2[17]\, \ctxp_m[15]\, - \rdatav_0_1_1_iv_0[17]\, \dcramo_m[113]\, \data2[17]\, - \rdatav_0_1_0_iv_4[31]\, \ctxp_m[29]\, - \rdatav_0_1_0_iv_1[31]\, \rdatav_0_1_0_iv_3[31]\, - \dstate[2]\, \dcramo_m_0[255]\, \dcramo_m[127]\, - \data2_m[31]\, \mmudco_m[74]\, - \rdatav_0_1_1_iv_i_a2_6[5]\, \rdatav_0_1_1_iv_i_a2_4[5]\, - \rdatav_0_1_1_iv_i_a2_3[5]\, N_3395, \ctx_0[5]\, N_3392, - N_3329, \rdatav_0_1_1_iv_i_a2_1[5]\, - \rdatav_0_1_1_iv_i_a2_0[5]\, N_3396, - \rdatav_0_1_1_iv_4[28]\, \mmudco_m[71]\, - \rdatav_0_1_1_iv_2[28]\, \ctxp_m[26]\, - \rdatav_0_1_1_iv_1[28]\, \data2_m[28]\, - twrite_14_iv_0_o4_0_o2_0, \dstate[4]\, N_58, \ctxp_m[16]\, - \rdatav_0_1_0_iv_2[18]\, \rdatav_0_1_0_iv_4[18]\, - \dcramo_m_0[242]\, \mmudco_m[61]\, - \rdatav_0_1_0_iv_0[18]\, \data2_m[18]\, \dcramo_m[114]\, - \rdatav_0_1_0_iv_3[25]\, \dcramo_m_0[249]\, - \rdatav_0_1_0_iv_2[25]\, \rdatav_0_1_0_iv_1[25]\, - \dcramo_m[121]\, \data2_m[25]\, \mmudco_m[68]\, - \rdatav_0_1_0_iv_3[8]\, \dcramo_m_0[232]\, - \rdatav_0_1_0_iv_2[8]\, \rdatav_0_1_0_iv_0[8]\, - \mmudco_m[44]\, \ctxp_m[6]\, \data2[8]\, - \rdatav_0_1_0_iv_4[20]\, \ctxp_m[18]\, - \rdatav_0_1_0_iv_1[20]\, \rdatav_0_1_0_iv_3[20]\, - \dcramo_m_0[244]\, \dcramo_m[116]\, \data2_m[20]\, - \mmudco_m[63]\, \rdatav_0_1_0_iv_3[27]\, - \dcramo_m_0[251]\, \rdatav_0_1_0_iv_2[27]\, - \mmudco_m[70]\, \rdatav_0_1_0_iv_0[27]\, \ctxp_m[25]\, - \data2_m[27]\, \ctxp_m[20]\, \rdatav_0_1_0_iv_2[22]\, - \rdatav_0_1_0_iv_4[22]\, \dcramo_m_0[246]\, - \mmudco_m[65]\, \rdatav_0_1_0_iv_0[22]\, \data2[22]\, - \dcramo_m[118]\, \dstate_ns_0_0_a2_0_1[8]\, - un121_m_en_i_s_0, hit, lock_m_0, \lock_0\, - \rdatav_0_1_0_iv_4[29]\, \ctxp_m[27]\, - \rdatav_0_1_0_iv_1[29]\, \rdatav_0_1_0_iv_3[29]\, - \dcramo_m_0[253]\, \dcramo_m[125]\, \data2_m[29]\, - \mmudco_m[72]\, setrepl_0_sqmuxa_1_m_i_5_2, - setrepl_0_sqmuxa_1_m_i_5_1, setrepl_0_sqmuxa_1_m_i_5_0, - un10_m_en, N_495, ready_0_sqmuxa_0_a2_0_a2_0, - cache_1_0_0_0, cache_1_0_a3_0_0, dstate_15_1, N_508, - cctrlwr19_2_0_2072_0, N_3779, N_494, dcs_1_i_s_0_0, N_512, - dstate_25_0_a2_0, \miscdata_4_sqmuxa_0_a2_1\, - \miscdata_4_sqmuxa_0_a2_0\, - \miscdata_2_sqmuxa_0_a4_0_a2_0_a3_0\, N_3569_2, - cache_1_0_a2_0_0, \vmask_0_5_1_0[4]\, - \vmask_0_5_1_a4_0_0[4]\, rdatav_0_6_sqmuxa_3_2, - rdatav_0_6_sqmuxa_3_0, rdatav_0_6_sqmuxa_3_1, N_206_1, - N_2042, \vmask_0_5_1_0[2]\, \vmask_0_5_1_a2_2_0[2]\, - \rdatav_0_1_0_iv_i_a2_2_0[1]\, \ctx_0[1]\, - \dstate_ns_0_7_tz_0[3]\, dstate_tr8_4_9_0_a2_0_a2_0_a2_0, - wbinit, hit_1_iv_0_a2_0_3, hit_1_iv_0_a2_0_2, un1_dci_NE, - hit_1_iv_0_a2_0_0, cctrlwr19_2_0_a2_1_1_0, - mexc_1_m_0_a2_0, mexc_1_m_0_a2_0_1, mexc_1_m_0_a2_5_0, - cctrlwr12, tdiagwrite_1_0_0_o2_1_0, N_132, - dstate_tr8_2_8_0_a2_1_a2_0, dstate_tr8_1_8_0_a2_0, N_505, - cctrlwr19_2_0_o2_0_0, N_223, N_3091_3, - cctrlwr19_2_0_o2_7_0, N_3798, dstate_tr8_5_9_0_a2_0_a2_0, - \rdatasel_1_i_a5_1[7]\, un1_dci_NE_17, un1_dci_NE_9, - un1_dci_NE_8, un1_dci_NE_15, un1_dci_NE_16, un1_dci_NE_5, - un1_dci_NE_4, un1_dci_NE_13, un1_dci_NE_0, un1_dci_NE_11, - un1_dci_16_i, un1_dci_11_i, un1_dci_NE_7, un1_dci_15_i, - un1_dci_14_i, un1_dci_9_i, N_149_i_i, un1_dci_18_i, - un1_dci_10_i, un1_dci_7_i, un1_dci_1_i, cctrlwr13_0_a2_0, - \faddr[6]\, ctx_NE_5, ctx_4_i, ctx_2_i, ctx_NE_3, - ctx_NE_4, N_103_i_i, N_102_i_i, ctx_NE_1, \ctx_0[6]\, - ctx_7_i, ctx_0_i, twrite_11_m_0_a2_0_2, - twrite_11_m_0_a2_0_1, N_3845, twrite_11_m_0_a2_0_0, - cache_0, mexc_1_m_0_a2_0_2_0, mmudci_read_1_1_0_a2_0_0, - mmudci_read_1_1_0_a2_0, read, dlock, \valid_0[4]\, - \valid_0[2]\, \vmask_0_1_2_o3_0_a2_0[3]\, \valid_0[3]\, - ctx_1_sqmuxa_0_a2_0, \addr[9]\, - \rdatasel_1_i_a3_2_0[7]_net_1\, \ctx\, \asi_0[1]\, - \asi_0[2]\, \asi_0[3]\, \ddatainv_0_1_1_iv_0[15]\, - \edata[15]\, \size_RNIBHS22[0]\, \dcramo_m[239]\, - \ddatainv_0_1_1_iv_0[7]\, \edata[7]\, ddatainv_0_3_sqmuxa, - \dcramo_m[231]\, dstate_17_2, \dstate_RNIET0O2[5]\, - dstate_17_1, \dstate[6]\, \ddatainv_0_1_1_iv_0[3]\, - \edata[3]\, \dcramo_m[227]\, \ddatainv_0_1_1_iv_1[0]\, - \edata[0]\, \mcdo_m[0]\, \ddatainv_0_1_1_iv_1[1]\, - \edata[1]\, \mcdo_m[1]\, \ddatainv_0_1_1_iv_0[2]\, - \edata[2]\, \dcramo_m[226]\, \ddatainv_0_1_1_iv_0[4]\, - \xaddress_RNIQDEG2_0[0]\, \edata_m[4]\, - \ddatainv_0_1_1_iv_0[8]\, \dstate_RNII450C[1]\, - \dcramo_m[232]\, \ddatainv_0_1_1_iv_0[9]\, \edata[9]\, - \dcramo_m[233]\, \ddatainv_0_1_1_iv_0[10]\, \edata[10]\, - \dcramo_m[234]\, \ddatainv_0_1_1_iv_0[11]\, \edata[11]\, - \dcramo_m[235]\, \ddatainv_0_1_1_iv_0[13]\, \edata[13]\, - \dcramo_m[237]\, \ddatainv_0_1_1_iv_0[14]\, \edata[14]\, - \dcramo_m[238]\, \ddatainv_0_1_0_iv_1[19]\, - ddatainv_0_1_sqmuxa, ddatainv_0_4_sqmuxa, - \ddatainv_0_1_0_iv_0[19]\, \edata[19]\, \dcramo_m_i[243]\, - \newtag_1_0[19]\, \N_3254_0\, N_3875, \vmask_0_1_i_1[7]\, - N_3248, N_3282, \address_i_0[7]\, N_195, N_3291, - \ddatainv_0_1_1_iv_0[12]\, \edata[12]\, \dcramo_m[236]\, - \ddatainv_0_1_1_iv_0[5]\, \edata_m[5]\, - \ddatainv_0_1_0_iv_1[21]\, \edata[5]\, - \ddatainv_0_1_0_iv_0[21]\, \edata_m_i[21]\, un19_m_en_m_2, - N_533, \N_121\, un19_m_en_m_1, N_3595, \vmask_0_1_2_0[4]\, - \vmask_0_1_2_a4_0_0[4]\, N_128_1, dwrite_1_iv_1, - un157_m_en_m, dwrite_1_iv_0, N_55, - \ddatainv_0_1_1_iv_1[6]\, \edata[6]\, \mcdo_m[6]\, - \ddatainv_0_1_0_iv_1[16]\, \ddatainv_0_1_0_iv_0[16]\, - \edata[16]\, \dcramo_m_i[240]\, \ddatainv_0_1_0_iv_1[17]\, - \ddatainv_0_1_0_iv_0[17]\, \edata[17]\, \dcramo_m_i[241]\, - \ddatainv_0_1_0_iv_1[18]\, \ddatainv_0_1_0_iv_1[20]\, - \edata[4]\, \ddatainv_0_1_0_iv_0[20]\, \edata_m_i[20]\, - \ddatainv_0_1_0_iv_1[22]\, \ddatainv_0_1_0_iv_0[22]\, - \edata[22]\, \dcramo_m_i[246]\, \ddatainv_0_1_0_iv_1[23]\, - \ddatainv_0_1_0_iv_0[23]\, \edata[23]\, \dcramo_m_i[247]\, - \ddatainv_0_1_0_iv_1[24]\, ddatainv_0_0_sqmuxa, - \edata_m_0_i[8]\, \ddatainv_0_1_0_iv_0[24]\, \edata[24]\, - \dcramo_m_i[248]\, \ddatainv_0_1_0_iv_2[25]\, \N_425_0\, - \ddatainv_0_1_0_iv_0[25]\, \edata[25]\, \dcramo_m_i[249]\, - \ddatainv_0_1_0_iv_1[26]\, \edata_m_0_i[10]\, - \ddatainv_0_1_0_iv_0[26]\, \edata[26]\, \dcramo_m_i[250]\, - \ddatainv_0_1_0_iv_1[27]\, \edata_m_4_i[3]\, - \ddatainv_0_1_0_iv_1[28]\, \edata_m_4_i[4]\, - \ddatainv_0_1_0_iv_0[28]\, \edata_m_i[28]\, - \ddatainv_0_1_0_iv_1[29]\, \edata_m_0_i[13]\, - \ddatainv_0_1_0_iv_0[29]\, \edata[29]\, \dcramo_m_i[253]\, - \ddatainv_0_1_0_iv_1[30]\, \edata_m_4_i[6]\, - \ddatainv_0_1_0_iv_0[30]\, \edata[30]\, \dcramo_m_i[254]\, - \ddatainv_0_1_0_iv_1[31]\, \edata_m_0_i[15]\, - \newtag_1_0[18]\, N_3850, \newtag_1_0[22]\, N_3864, - \newtag_1_0[23]\, \addr[23]\, N_3878, \addr[24]\, \N_330\, - N_3892, \addr[25]\, N_236, \addr[26]\, N_245, N_3895, - \address_i_1[6]\, N_3289, N_3290, \address_i_0[8]\, - N_3295, un1_dci_12, \dstate_ns_0_8_tz[3]\, N_2994_6, - \dstate_ns_0_2_0_tz[3]\, N_2994_8, N_3002_9, N_2995_8, - un30_m_en_0, rdatasel_4_sqmuxa, \mcdo_m_0[13]\, N_2047, - flush2, \mcdo_m_0[30]\, \dstate_RNI5ED76[1]\, N_3556, - N_162, N_3298, N_3297, N_3288, N_3287, un19_eholdn, - addr_0_sqmuxa, N_27, N_3203, N_3204, addr_1_sqmuxa_2, - \addr_1[12]\, \addr_1[13]\, \addr_1[29]\, \addr_1[27]\, - \addr_1[23]\, \addr_1[28]\, \addr_1[18]\, \addr_1[22]\, - \addr_1[20]\, N_3675, N_302, N_301, N_303, N_257, N_255, - \dci_m[87]\, N_242, N_240, \dci_m[88]\, N_239, N_237, - \dci_m[86]\, N_3894, N_232, \dci_m[93]\, N_3893, N_229, - \dci_m[89]\, \N_329\, N_156, N_155, N_157, N_3849, N_3848, - \dci_m[85]\, N_148, N_146, \dci_m[84]\, addr_0_sqmuxa_1, - N_3755, N_102, \addr_1[7]\, N_2164, cache_RNO_0, N_3674, - N_2481, N_51, N_672, N_3664, \addr_1[17]\, \addr_1[21]\, - \addr_1[14]\, \addr_1[24]\, N_3197, N_111, N_32, N_19, - N_3360, N_3362, N_3363, \data2[3]\, N_130, N_91, N_131, - N_126, \vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\, N_110, - \mcdo_m_i[31]\, \mcdo_m_i[30]\, \mcdo_m_i[29]\, - \mcdo_m_i[28]\, \mcdo_m_i[27]\, \mcdo_m_i[26]\, - \edata_m_4_i[1]\, \edata_m_0_i[9]\, \mcdo_m_i[24]\, - \mcdo_m_i[23]\, \mcdo_m_i[22]\, \mcdo_m_i[20]\, - \mcdo_m_i[18]\, \mcdo_m_i[17]\, \mcdo_m_i[16]\, - \edata_m[6]\, \dcramo_m[230]\, N_3770, N_3765, N_490, - \addr_1[31]\, vaddr_1_sqmuxa, - \mmudci_trans_op_1_sqmuxa_1\, N_227, N_2938_2, N_3605, - un157_m_en, holdn_10, N_3613, flush_1_i_0, - dwrite_4_sqmuxa, holdn_RNO_0, holdn_0_sqmuxa_1, N_305, - N_304, N_306, N_349, \vmask_0_5[4]\, req_2_sqmuxa, req16, - N_60, N_580, \dstate_i_2_RNITVLGB92[8]\, N_3607, N_561, - N_3610, N_608, N_492, edata_0_sqmuxa_i, N_665, N_563, - N_3710, N_3676, N_3818, N_688, N_3814, N_562, N_467, - \mcdo_m_i[21]\, \addr_1[6]\, N_3627, ctx_1_sqmuxa, - \addr[10]\, \mcdo_m[5]\, \edata_m_0[5]\, \mcdo_m[12]\, - \edata_m_1[4]\, \mcdo_m_0[27]\, N_3294, N_3293, - \mcdo_m_0[20]\, \mcdo_m_0[14]\, \mcdo_m_0[25]\, - \mcdo_m_0[16]\, \mcdo_m_0[17]\, \mcdo_m_0[28]\, - \mcdo_m_0[8]\, \dcramo_m_0[235]\, \mcdo_m_0[11]\, - \mcdo_m_0[21]\, \mcdo_m_0[4]\, N_3069_i, N_551, N_3404, - N_3340, \ico_m[135]\, \mcdo_m_0[1]\, N_179, N_178, - \addr_1[25]\, \mcdo_m_0[26]\, \addr_1[30]\, \addr_1[26]\, - \addr_1[16]\, N_587, N_3775, N_556, \addr_1[0]\, - \mmudco_m[2]\, \dci_m[8]\, N_90, N_3279, N_3278, - \addr_1[15]\, N_3494, \addr_1[4]\, N_3320, \addr_1[5]\, - \addr_1[11]\, N_282, N_285, \addr_1[19]\, N_158, - ready_0_sqmuxa, ready_RNO_0, \vmask_0_5[2]\, N_3657, - N_3655, N_345, \valid_0[0]\, un17_m_en, N_3653, N_568, - N_3564_i, N_3546, N_3700, N_3699, \size_0[1]\, \size[0]\, - \addr[1]\, ready_0_sqmuxa_0, N_3660, N_21, N_3364, N_3365, - N_3366, \data2[5]\, N_3421, N_679, N_143, N_25, \ics[0]\, - \mcdo_m_i[19]\, \mcdo_m[14]\, \edata_m_1[6]\, - \mcdo_m[13]\, \edata_m_1[5]\, \mcdo_m[11]\, - \edata_m_1[3]\, \mcdo_m[10]\, \edata_m_1[2]\, \mcdo_m[9]\, - \edata_m_1[1]\, \mcdo_m[8]\, \edata_m_1[0]\, \mcdo_m[4]\, - \edata_m_0[4]\, \mcdo_m[2]\, \edata_m_0[2]\, \edata_m[1]\, - \dcramo_m[225]\, \edata_m[0]\, \dcramo_m[224]\, N_202, - N_3259, N_3313, N_3397, N_3341, rdatasel_0_sqmuxa_1, - hit_1_iv_0_a2_0, lock_2_sqmuxa, N_86, N_3554, lock_1, - N_3553, N_3555, N_56, \addr_1[8]\, \mcdo_m[3]\, - \edata_m_0[3]\, \addr_1[9]\, flush_1_sqmuxa, - un1_eholdn_2_9, \valid_0_1[7]\, N_3285, N_3283, N_3286, - N_3286_1, twrite_14, \dstate_RNIR2CO3[4]\, N_3752, N_3760, - N_3698, N_503, \xaddress_1[2]\, N_652_i, N_115, - \addr_1[3]\, \addr_1[2]\, \addr_1[1]\, \mcdo_m[7]\, - \edata_m_0[7]\, \mcdo_m[15]\, \edata_m_1[7]\, N_557, - flush_RNICQGM51, N_3322, flush_RNITKH06, - dstate_tr22_15_a2_2_m1_e, e_0_0_RNIIAUC4Q1, burst_1_N_9, - burst_1_N_7, burst_1_N_12, burst_RNO_3, burst_RNO, - vaddr_1_sqmuxa_0_a2_4_m7_i_a4, dstate_tr22_15_a2_1, - N_3787, holdn_RNO_4, dstate_tr22_15_a2_2_m8_i_a5_0_0, - dstate_tr22_15_a2_4_1, dstate_tr22_15_a2_9_0, - \ddatainv_0_1_3_0[0]\, N_3763, N_3782, - \ddatainv_0_1_0_0[24]\, \addr[0]\, N_3764, N_3785, - \dstate_ns_0_0_a2_0_1[2]\, N_549, N_574, N_3153, - hit_RNO_2, N_575, N_3569, N_3835, \xaddress_RNIQDEG2[0]\, - holdn_RNO_3, dstate_tr22_15_a2_15_0, - \vaddr_1_sqmuxa_0_a2_2\, \stpend_RNI6P41NG3\, - \valid_0_1_1_0[5]\, \valid_0_1_1_a4_1_0[5]\, N_188, - \valid_0_1_1_0[1]\, \valid_0_1_1_a4_1_0[1]\, N_16828_tz, - \dstate_RNO_1[6]\, \dstate_ns_0_0_a2_0[2]\, N_95, N_96, - N_136, \valid_0_1[5]\, N_88, \dstate_i_RNII68N892_0[8]\, - \valid_0_1[1]\, cache_1, N_3836, \edata[20]\, \edata[28]\, - dstate_25, N_2675, N_2684, N_3668, \dstate_nss[8]\, - N_2664, N_2667, \ctx_0[4]\, N_2668, N_2669, N_2670, - \ctx_0[7]\, \data2[24]\, \mcdo_m_0[24]\, \data2[28]\, - \ctxp[26]\, \valid_0[1]\, \data2[4]\, \data2[6]\, - \ctx[6]\, N_3338, N_2126, \data1_1[28]\, \data2_1[28]\, - N_2105, \data2[7]\, N_2108, \data2[10]\, N_2110, - \data2[12]\, \data1_1[7]\, \data1_1[10]\, \data1_1[11]\, - N_2109, \data1_1[12]\, \data2_1[10]\, \data2_1[12]\, - N_2111, \data2[13]\, N_2116, \data2[18]\, N_2118, - \data2[20]\, \data1_1[13]\, \data1_1[18]\, \data1_1[20]\, - \data2_1[13]\, \data2_1[18]\, \data2_1[20]\, N_2120, - \data1_1[22]\, \data2_1[22]\, N_2099, \data2[1]\, N_2112, - N_2121, \data2[23]\, \data1_1[1]\, \data1_1[14]\, - \data1_1[23]\, \data2_1[1]\, \data2_1[14]\, \data2_1[23]\, - N_2122, \data1_1[19]\, N_2117, \data1_1[24]\, - \data2_1[24]\, N_2115, N_2123, \data2[25]\, \data1_1[17]\, - req_0_sqmuxa_1, \data1_1[25]\, \data2_1[17]\, - \data2_1[25]\, N_2124, \data2[26]\, \data1_1[26]\, - \data2_1[26]\, N_2098, \data2[0]\, N_2125, \data2[27]\, - \data1_1[0]\, \data1_1[27]\, \data2_1[0]\, \data2_1[27]\, - N_2113, N_2127, \data2[29]\, \data1_1[15]\, \data1_1[29]\, - \ctxp[27]\, \mcdo_m_0[29]\, \data2_1[15]\, \data2_1[29]\, - N_2128, \data2[30]\, \data1_1[30]\, \data2_1[30]\, N_2129, - \data2[31]\, \data1_1[31]\, \data2_1[31]\, N_184, - twrite_14_iv_0_a2_a0_RNIGON1LK, N_2102, \data1_1[4]\, N_8, - N_3260, N_3270, N_2100, \data2[2]\, N_2104, \data1_1[2]\, - \data1_1[6]\, \data2_1[6]\, N_3347, N_3348, N_2114, - \data2[16]\, \data1_1[16]\, \data2_1[16]\, N_727, N_3598, - N_3599, N_3805, N_3600, N_3757, N_552, N_3796, - \paddress[7]\, \addr[7]\, N_486, \hold\, \paddress[24]\, - \paddress[29]\, \addr[29]\, \paddress[21]\, \addr[21]\, - \paddress[17]\, \addr[17]\, \paddress[14]\, \addr[14]\, - N_564, \data[28]\, \vaddr[28]\, \data[12]\, \vaddr[12]\, - \vaddr[18]\, \vaddr[20]\, \vaddr[22]\, \vaddr[23]\, - \vaddr[13]\, \vaddr[24]\, \vaddr[17]\, \vaddr[25]\, - \vaddr[26]\, \vaddr[27]\, \data[15]\, \vaddr[15]\, - \vaddr[29]\, \vaddr[1]\, \vaddr[16]\, \data[30]\, - \vaddr[30]\, \vaddr[11]\, \vaddr[14]\, \vaddr[31]\, - \vaddr[19]\, \vaddr[8]\, \vaddr[9]\, \un1_m0_2[86]\, - \vaddr[10]\, \un1_m0_2[83]\, \vaddr[7]\, \vaddr[6]\, - \vaddr[5]\, \vaddr[4]\, N_674, \paddress[27]\, \addr[27]\, - \paddress[12]\, \addr[12]\, \paddress[13]\, \addr[13]\, - N_710, \addr[6]\, N_712, N_718, \e\, \ctxp[28]\, N_3319, - un1_taddr_1_sqmuxa, \faddr[5]\, N_2233, \taddr_7[6]\, - taddr_2_sqmuxa, N_3344_i_0, \un1_m0_2[80]\, N_2232, - \taddr_7[5]\, lrr_1_sqmuxa, read_RNO, nf_RNO, \ctx_0[0]\, - N_3780, \addr[28]\, \addr[18]\, \addr[20]\, N_3842, - \addr[22]\, N_3840, \addr[16]\, \addr[15]\, addr_2_sqmuxa, - \addr[31]\, addr_1_sqmuxa, \un1_m0_2[81]\, - \valid_0_RNI7F6M2[0]\, \dstate_i_RNID1NU1[8]\, N_3833, - \paddress[23]\, \paddress[28]\, \paddress[22]\, - \paddress[18]\, \paddress[20]\, N_484, N_3246, N_3665_1, - N_582, N_2663, \vaddr[0]\, N_3799, N_537, \paddress[31]\, - mmctrl1wr_RNO, \vaddr[3]\, flush_0, pso_RNO, N_2674, pso, - tlbdis_RNO, N_2673, N_716, \un1_m0_2[85]\, - \dstate_nss[5]\, \dstate_ns[5]\, trans_op_RNO_1, - flush_op_RNO, N_3672, \trans_op\, \flush_op_i_0\, - flush_op, N_2715_i, \taddr_7[11]\, \faddr_1_i[6]\, - \faddr_1[5]\, I_24_1, \faddr_1[4]\, I_20_1, \faddr_1[3]\, - I_13_5, \faddr_1[2]\, I_9_1, \faddr_1[1]\, I_5_1, - \faddr_1[0]\, N_2238, \addr[11]\, faddr_2_sqmuxa, - dstate_5_sqmuxa, stpend_RNO, \data2_1[4]\, req_RNO, - N_3588, N_3572, N_3671, \dstate_nss[2]\, N_3810, N_3709, - N_3743, N_3742, \vaddr[21]\, \data2_1[21]\, \data1_1[21]\, - N_2119, \data2[21]\, \edata[21]\, N_2666, N_2665, - \vaddr[2]\, \un1_m0_2[82]\, \burst\, N_419_0, - \un1_m0_2[78]\, \un1_m0_2[77]\, ddatainv_0_2_sqmuxa, - \faddr[4]\, \N_425\, N_2629, N_2676, \dstate_nss[3]\, - \dstate_nss[4]\, ilramen_1_sqmuxa, \dstate_nss[7]\, \nf\, - \burst_0\, rdatav_012, rdatav_0_6_sqmuxa, - rdatasel_1_sqmuxa_1, \ctx[2]\, \data2[11]\, \dstate[7]\, - N_3377, N_3380, \valid_0_1[0]\, \valid_0_1[3]\, N_3339, - \ctx[3]\, N_2107, \data2[9]\, \data1_1[9]\, \data2_1[7]\, - \data2_1[9]\, \data2_1[11]\, \data2_1[19]\, - \paddress_0[25]\, \paddress[30]\, \paddress_0[30]\, - \paddress_0[26]\, valid_0_2_sqmuxa, N_2362, - \vmask_0_6[2]\, N_2366, \vmask_0_6[6]\, N_2381, N_2385, - \valid_0_1[2]\, \valid_0_1[6]\, \data2_1[2]\, N_3244_i_0, - N_3808, N_3800, paddress_1_sqmuxa, \paddress[16]\, - \paddress_0[16]\, N_3662, N_534, N_3793, N_3621, N_3623, - N_3625, N_3626, \addr[4]\, N_3766, N_3768, \dcs_RNO[0]\, - N_671, N_591, \paddress[15]\, \paddress[4]\, N_709, N_713, - N_715, N_719, \un1_m0_2[76]\, \paddress_0[0]\, N_7, - N_2016, N_2017, \vmask_0_5[7]\, N_3315, N_2230, N_2229, - mexc_1_sqmuxa, burst_RNO_0, \ctx[0]\, \ics[1]\, - \addr[19]\, \un1_m0_2[87]\, N_296, N_298, N_348, - \vmask_0_5[6]\, \paddress[19]\, \cache\, \tlbdis\, - \ctx[7]\, N_3754, N_182, N_2013, N_2014, N_2012, N_9, - hit_1, data1_0_sqmuxa, \paddress_0[8]\, \un1_m0_2[84]\, - su_0, \paddress_0[9]\, N_509, \vmask_0_4[6]\, N_2026, - \valid_0[6]\, \valid_0_1[4]\, N_2364, N_44_i_0, - \vmask_0_4[7]\, N_2027, \valid_0[7]\, \valid_0[5]\, - \taddr_7[7]\, \faddr[2]\, N_2234, burst_1_sqmuxa, - nomds_RNO, N_2596, nomds_1, N_670, N_3791, \paddress[2]\, - N_323, size, \un1_m0_2[79]\, \paddress_0[1]\, - \paddress[3]\, N_654, N_653, \mcdo_m_0[31]\, \ctxp[29]\, - N_3261, \read_2\, \trans_op_0\, \ctx[5]\, \asi_0[0]\, - \size_1[0]\, \size_1[1]\, \ctxp[0]\, \ctxp[1]\, \ctxp[2]\, - \ctxp[3]\, \ctxp[4]\, \ctxp[5]\, \ctxp[6]\, \ctxp[7]\, - \ctxp[8]\, \ctxp[9]\, \ctxp[10]\, \ctxp[11]\, \ctxp[12]\, - \ctxp[13]\, \ctxp[14]\, \ctxp[15]\, \ctxp[16]\, - \ctxp[17]\, \ctxp[18]\, \ctxp[19]\, \ctxp[20]\, - \ctxp[21]\, \ctxp[22]\, \ctxp[23]\, \ctxp[24]\, - \ctxp[25]\, \addr[30]\, \address[0]\, \address[1]\, - \address[2]\, \address[3]\, \address[4]\, \address[5]\, - \address[6]\, \address[7]\, \address[8]\, \address[9]\, - \address[10]\, \address[11]\, \address[12]\, - \address[13]\, \address[14]\, \address[15]\, - \address[16]\, \address[17]\, \address[18]\, - \address[19]\, \address[20]\, \address[21]\, - \address[22]\, \address[23]\, \address[24]\, - \address[25]\, \address[26]\, \address[27]\, - \address[28]\, \address[29]\, \address[30]\, - \address[31]\, N_4, \DWACT_FINC_E[1]\, N_9_0, N_17, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - size_1(1) <= \size_1[1]\; - size_1(0) <= \size_1[0]\; - ctx(7) <= \ctx[7]\; - ctx(6) <= \ctx[6]\; - ctx(5) <= \ctx[5]\; - ctx(3) <= \ctx[3]\; - ctx(2) <= \ctx[2]\; - ctx(0) <= \ctx[0]\; - asi_0_0 <= \asi_0[0]\; - ics(1) <= \ics[1]\; - ics(0) <= \ics[0]\; - data(30) <= \data[30]\; - data(28) <= \data[28]\; - data(15) <= \data[15]\; - data(12) <= \data[12]\; - un1_m0_2_77 <= \un1_m0_2[78]\; - un1_m0_2_78 <= \un1_m0_2[79]\; - un1_m0_2_75 <= \un1_m0_2[76]\; - un1_m0_2_79 <= \un1_m0_2[80]\; - un1_m0_2_80 <= \un1_m0_2[81]\; - un1_m0_2_81 <= \un1_m0_2[82]\; - un1_m0_2_84 <= \un1_m0_2[85]\; - un1_m0_2_83 <= \un1_m0_2[84]\; - un1_m0_2_86 <= \un1_m0_2[87]\; - un1_m0_2_76 <= \un1_m0_2[77]\; - un1_m0_2_85 <= \un1_m0_2[86]\; - un1_m0_2_82 <= \un1_m0_2[83]\; - rdatav_0_1_0_iv_5_20 <= \rdatav_0_1_0_iv_5[24]\; - rdatav_0_1_0_iv_4_29 <= \rdatav_0_1_0_iv_4[29]\; - rdatav_0_1_0_iv_4_31 <= \rdatav_0_1_0_iv_4[31]\; - mcdo_m_0_28 <= \mcdo_m_0[29]\; - mcdo_m_0_23 <= \mcdo_m_0[24]\; - mcdo_m_0_30 <= \mcdo_m_0[31]\; - ctxp_13 <= \ctxp[13]\; - ctxp_16 <= \ctxp[16]\; - ctxp_7 <= \ctxp[7]\; - ctxp_10 <= \ctxp[10]\; - ctxp_3 <= \ctxp[3]\; - ctxp_8 <= \ctxp[8]\; - ctxp_19 <= \ctxp[19]\; - ctxp_17 <= \ctxp[17]\; - ctxp_15 <= \ctxp[15]\; - ctxp_14 <= \ctxp[14]\; - ctxp_20 <= \ctxp[20]\; - ctxp_18 <= \ctxp[18]\; - ctxp_6 <= \ctxp[6]\; - ctxp_21 <= \ctxp[21]\; - ctxp_11 <= \ctxp[11]\; - ctxp_4 <= \ctxp[4]\; - ctxp_25 <= \ctxp[25]\; - ctxp_0 <= \ctxp[0]\; - ctxp_22 <= \ctxp[22]\; - ctxp_23 <= \ctxp[23]\; - ctxp_24 <= \ctxp[24]\; - ctxp_5 <= \ctxp[5]\; - ctxp_12 <= \ctxp[12]\; - ctxp_9 <= \ctxp[9]\; - ctxp_1 <= \ctxp[1]\; - ctxp_2 <= \ctxp[2]\; - address(31) <= \address[31]\; - address(30) <= \address[30]\; - address(29) <= \address[29]\; - address(28) <= \address[28]\; - address(27) <= \address[27]\; - address(26) <= \address[26]\; - address(25) <= \address[25]\; - address(24) <= \address[24]\; - address(23) <= \address[23]\; - address(22) <= \address[22]\; - address(21) <= \address[21]\; - address(20) <= \address[20]\; - address(19) <= \address[19]\; - address(18) <= \address[18]\; - address(17) <= \address[17]\; - address(16) <= \address[16]\; - address(15) <= \address[15]\; - address(14) <= \address[14]\; - address(13) <= \address[13]\; - address(12) <= \address[12]\; - address(11) <= \address[11]\; - address(10) <= \address[10]\; - address(9) <= \address[9]\; - address(8) <= \address[8]\; - address(7) <= \address[7]\; - address(6) <= \address[6]\; - address(5) <= \address[5]\; - address(4) <= \address[4]\; - address(3) <= \address[3]\; - address(2) <= \address[2]\; - address(1) <= \address[1]\; - address(0) <= \address[0]\; - addr_30 <= \addr[30]\; - addr_11 <= \addr[11]\; - addr_6 <= \addr[6]\; - addr_4 <= \addr[4]\; - addr_7 <= \addr[7]\; - addr_5 <= \addr[5]\; - addr_3 <= \addr[3]\; - addr_8 <= \addr[8]\; - addr_10 <= \addr[10]\; - addr_9 <= \addr[9]\; - addr_2 <= \addr[2]\; - un1_p0_2_0(498) <= \un1_p0_2_0[498]\; - ctx_0(7) <= \ctx_0[7]\; - ctx_0(6) <= \ctx_0[6]\; - ctx_0(5) <= \ctx_0[5]\; - ctx_0(4) <= \ctx_0[4]\; - ctx_0(3) <= \ctx_0[3]\; - ctx_0(2) <= \ctx_0[2]\; - ctx_0(1) <= \ctx_0[1]\; - ctx_0(0) <= \ctx_0[0]\; - size_1z <= size; - burst_0 <= \burst_0\; - N_425 <= \N_425\; - trans_op_0 <= \trans_op_0\; - flush_op_i_0 <= \flush_op_i_0\; - trans_op <= \trans_op\; - tlbdis <= \tlbdis\; - read_2 <= \read_2\; - e <= \e\; - nf <= \nf\; - vaddr_1_sqmuxa_0_a2_2 <= \vaddr_1_sqmuxa_0_a2_2\; - stpend_RNI6P41NG3 <= \stpend_RNI6P41NG3\; - N_329 <= \N_329\; - N_330 <= \N_330\; - cache <= \cache\; - lock_0 <= \lock_0\; - req <= \req\; - N_523 <= \N_523\; - burst <= \burst\; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 <= - \vaddr_1_sqmuxa_0_a2_4_m1_e_24\; - mmudci_trans_op_1_sqmuxa_1 <= \mmudci_trans_op_1_sqmuxa_1\; - hold <= \hold\; - N_425_0 <= \N_425_0\; - N_121 <= \N_121\; - N_3254_0 <= \N_3254_0\; - e_0 <= \e_0\; - - \r.wb.addr_RNO_3[2]\ : OR2B - port map(A => un1_m0_2_3, B => addr_1_sqmuxa, Y => N_314); - - \r.cctrl.burst_RNO\ : NOR2B - port map(A => rst, B => N_2629, Y => burst_RNO_0); - - \r.wb.data1_RNO[22]\ : MX2A - port map(A => N_2120, B => maddress(22), S => - req_0_sqmuxa_1_0, Y => \data1_1[22]\); - - \r.holdn_RNI8AEJ\ : NOR3B - port map(A => enaddr, B => \hold\, C => \dstate_i_0[8]\, Y - => N_486_0); - - mexc_1_sqmuxa_0_o2 : OR2 - port map(A => un1_m0_2_0_d0, B => un1_m0_2_34, Y => N_506); - - \r.mmctrl1.ctx_0_0_RNI5V101[1]\ : NOR3C - port map(A => N_103_i_i, B => N_102_i_i, C => ctx_NE_1, Y - => ctx_NE_4); - - \v.mmctrl1.e_0_sqmuxa_RNILF2I\ : MX2 - port map(A => \e\, B => maddress(0), S => e_0_sqmuxa, Y => - N_2676); - - \r.mmctrl1.ctxp_RNIRQ1UD[18]\ : NOR3C - port map(A => \ctxp_m[18]\, B => \rdatav_0_1_0_iv_1[20]\, C - => \rdatav_0_1_0_iv_3[20]\, Y => \rdatav_0_1_0_iv_4[20]\); - - \r.wb.addr[23]\ : DFN1 - port map(D => \addr_1[23]\, CLK => lclk_c, Q => - \address[23]\); - - \r.flush_0_1_RNI4FE0MI\ : NOR3C - port map(A => flush_1_i_0, B => faddr_1_sqmuxa_0, C => rst, - Y => faddr_2_sqmuxa); - - \r.holdn_RNIPU251\ : OR2B - port map(A => maddress(3), B => N_534, Y => N_3808); - - \r.cctrl.dcs_RNO_0[0]\ : MX2C - port map(A => maddress(2), B => \dcs[0]\, S => \N_523\, Y - => N_671); - - \r.vaddr[2]\ : DFN1E1 - port map(D => maddress(2), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[2]\); - - \r.dstate_RNI1JGE7_2[2]\ : AOI1B - port map(A => diagdata_8, B => \dstate[2]\, C => - \dcramo_m_0[232]\, Y => \rdatav_0_1_0_iv_3[8]\); - - \r.holdn_RNIQ28U_0\ : OR3 - port map(A => N_3763, B => maddress(0), C => maddress(1), Y - => N_3621); - - \r.dstate_i_2_RNISK8N1_25[8]\ : OR2B - port map(A => dataout_0(18), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[118]\); - - \r.xaddress[28]\ : DFN1E1 - port map(D => maddress(28), CLK => lclk_c, E => N_486, Q - => \addr[28]\); - - \r.wb.addr[13]\ : DFN1 - port map(D => \addr_1[13]\, CLK => lclk_c, Q => - \address[13]\); - - \r.flush2_RNIP0PM5\ : OA1A - port map(A => un6_validrawv, B => un10_m_en, C => N_499, Y - => setrepl_0_sqmuxa_1_m_i_5_1); - - \r.wb.addr_RNO_1[24]\ : OR2B - port map(A => maddress(24), B => addr_2_sqmuxa_0, Y => - N_3634); - - \r.dstate_RNIV347A[1]\ : NOR2B - port map(A => \edata[0]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[0]\); - - \r.wb.data2_RNIIVB46[15]\ : NOR3C - port map(A => \rdatav_0_1_0_iv_0_0[15]\, B => N_205, C => - \mmudco_m[58]\, Y => \rdatav_0_1_0_iv_0_2[15]\); - - \r.wb.data1_RNO_2[5]\ : NOR3A - port map(A => edata2_0_iv(5), B => req_0_sqmuxa_1_0, C => - N_3331_0, Y => N_3366); - - \r.wb.addr_RNO_4[27]\ : OR2B - port map(A => \address[27]\, B => N_514, Y => N_253); - - \r.wb.addr_RNO_2[25]\ : OR2B - port map(A => maddress(25), B => addr_2_sqmuxa, Y => - \dci_m[33]\); - - \r.mmctrl1.ctxp[5]\ : DFN1E1 - port map(D => maddress(7), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[5]\); - - \r.wb.addr_RNO[11]\ : OR3C - port map(A => N_282, B => \addr_1_1_iv_0_1[11]\, C => N_285, - Y => \addr_1[11]\); - - \r.wb.addr_RNO_6[12]\ : OR2B - port map(A => N_2886, B => addr_1_sqmuxa, Y => N_278); - - \r.wb.addr_RNO_0[2]\ : NOR3C - port map(A => \addr_1_0_iv_0_1[2]\, B => N_315, C => N_314, - Y => \addr_1_0_iv_0_3[2]\); - - \r.dstate_0_RNI0ASD21[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_0_5[15]\, B => - \rdatav_0_1_0_iv_0_4[15]\, C => N_202, Y => data_0_15); - - \r.wb.data2_RNO[16]\ : MX2 - port map(A => edata2_0_iv(16), B => hrdata_0_16, S => - \dstate_1[7]\, Y => \data2_1[16]\); - - \r.holdn_RNO_23\ : NOR2B - port map(A => e_RNIKN3D, B => N_489, Y => - holdns_iv_0_a2_1_0); - - \r.dstate_RNIHILB6_12[7]\ : OR2B - port map(A => dataout(0), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[224]\); - - \r.dstate_RNI123K[0]\ : NOR3 - port map(A => \dstate[1]\, B => \dstate[0]\, C => - \dstate[3]\, Y => dstate_19_1); - - \r.wb.addr_RNO_5[19]\ : OR2B - port map(A => N_415, B => addr_1_sqmuxa, Y => N_3890); - - \r.cctrlwr\ : DFN1 - port map(D => N_2715_i, CLK => lclk_c, Q => cctrlwr); - - \r.wb.data2[3]\ : DFN1E1 - port map(D => N_3347, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[3]\); - - \r.size_RNIQO6E_0[1]\ : NOR3A - port map(A => N_3749, B => \size_0[1]\, C => \addr[1]\, Y - => N_3805); - - \r.dstate_i_RNI3KIBI6[8]\ : OAI1 - port map(A => N_188, B => \dstate_i[8]\, C => N_182, Y => - N_88); - - \r.stpend_RNIO6COHV3\ : NOR2B - port map(A => dstate_tr22_15_a2_1_1_0, B => fault_pri, Y - => vaddr_1_sqmuxa_0_a2_a0_0); - - \r.dstate_RNIHILB6_13[7]\ : OR2B - port map(A => dataout(9), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[233]\); - - \r.dstate_0_RNIIC256_5[7]\ : OR2B - port map(A => dataout(1), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[225]\); - - \r.dstate_0_RNI8VO931[7]\ : AO1B - port map(A => \dstate_0[7]\, B => hrdata_0_0, C => - \rdatav_0_1_0_iv_7[0]\, Y => data_0_0); - - \dctrl.0.genmux.un6_validrawv_6\ : MX2C - port map(A => N_7, B => N_2016, S => maddress(3), Y => - N_2017); - - \r.dstate_RNIS3GB3[6]\ : OR2A - port map(A => \dstate[6]\, B => N_580, Y => N_3750); - - \un1_v.holdn_3_sqmuxa_0_0_a2_4\ : OR2A - port map(A => N_489, B => asi(3), Y => N_3743); - - \r.vaddr_RNIBQHC[31]\ : MX2 - port map(A => maddress(31), B => \vaddr[31]\, S => - \dstate_i_2[8]\, Y => data(31)); - - \dctrl.un1_eholdn_2_1_0_a2_0\ : NOR2 - port map(A => N_3799, B => N_2938_2, Y => N_227); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_12\ : NOR3A - port map(A => eaddress_9, B => eaddress_17, C => - eaddress_27, Y => vaddr_1_sqmuxa_0_a2_4_m1_e_12); - - \r.asi[3]\ : DFN1E1 - port map(D => asi(3), CLK => lclk_c, E => N_486_0, Q => - \asi_0[3]\); - - N_3253_i_0_a2 : NOR2 - port map(A => N_533, B => N_505, Y => N_3253_i); - - \dctrl.twrite_14_iv_0_o2_a0_RNO\ : AND2 - port map(A => twrite_14_iv_0_o2_a0_3, B => un1_addout_12, Y - => twrite_14_iv_0_o2_a0_4); - - \r.dstate_RNO_12[4]\ : OR2A - port map(A => \req\, B => N_16887_tz_tz, Y => - dstate_tr16_13_0_0_a2_0); - - \r.dstate[4]\ : DFN1 - port map(D => \dstate_nss[4]\, CLK => lclk_c, Q => - \dstate[4]\); - - \dctrl.0.un1_dci_0_0_0_x2\ : XNOR2 - port map(A => maddress(12), B => dataout_0(8), Y => - N_139_i_i); - - \r.wb.addr_RNO_5[6]\ : OR2B - port map(A => \un1_m0_2[82]\, B => addr_1_sqmuxa_2, Y => - N_3628); - - \r.dstate_2_RNIAQ3G8[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_27, Y => - \mcdo_m_0[27]\); - - \r.xaddress_RNO[4]\ : MX2 - port map(A => \addr[4]\, B => maddress(4), S => N_486_0, Y - => N_715); - - \r.vaddr_RNIIJ9G[3]\ : MX2 - port map(A => maddress_0_2, B => \vaddr[3]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[79]\); - - \dctrl.twrite_14_iv_0_o2_a0_RNO_0\ : NOR3A - port map(A => twrite_14_iv_0_o2_a0_1, B => me_nullify2_1_2, - C => nullify2_0_sqmuxa, Y => twrite_14_iv_0_o2_a0_3); - - \r.holdn_RNI1TJA\ : OR2 - port map(A => maddress(2), B => N_3443_i, Y => N_3754); - - \r.vaddr[25]\ : DFN1E1 - port map(D => maddress(25), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[25]\); - - \r.read_RNIQH64D1\ : OR3 - port map(A => \mcdo_m[15]\, B => \edata_m_1[7]\, C => - \ddatainv_0_1_1_iv_0[15]\, Y => read_RNIQH64D1); - - \r.wb.data2_RNIIOUT5[21]\ : NOR3B - port map(A => \dcramo_m[117]\, B => \data2_m[21]\, C => - \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_1[21]\); - - \r.mmctrl1.ctxp[19]\ : DFN1E1 - port map(D => maddress(21), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[19]\); - - \r.dstate_RNIN17FC[1]\ : MX2 - port map(A => maddress(11), B => edata2_0_iv(11), S => - edata_0_sqmuxa_i, Y => \edata[11]\); - - \r.dstate_RNI86ELB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[3]\, Y => \ddatainv_0_1_0_iv_1[19]\); - - \r.read_RNIEG3AM\ : OR2B - port map(A => \N_425_0\, B => hrdata_26, Y => - \mcdo_m_i[31]\); - - \r.flush_RNIJCBP1\ : NOR2B - port map(A => tdiagwrite_1_0_0_o2_1_0, B => N_3253_i, Y => - tdiagwrite_1_0_0_o2_1); - - \r.dstate_0_RNI1JGE7_7[2]\ : AOI1B - port map(A => diagdata_14, B => \dstate_0[2]\, C => - \dcramo_m_0[238]\, Y => \rdatav_0_1_0_iv_5[14]\); - - \r.mmctrl1.e_0_0_RNIPO5UKG3\ : NOR2B - port map(A => un1_m0_2_108, B => \e_0\, Y => N_3787); - - \r.dstate_RNIHILB6_8[7]\ : OR2B - port map(A => dataout(16), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[240]\); - - \r.dstate_i_1[8]\ : DFN1 - port map(D => \dstate_nss_i_0[0]\, CLK => lclk_c, Q => - \dstate_i_1[8]\); - - \dctrl.iflush_1_0_a2_0_0\ : OA1B - port map(A => cctrlwr13, B => cctrlwr11_0, C => read_0, Y - => iflush_1_0_a2_0); - - \r.nomds_RNIGK9H\ : NOR2 - port map(A => nomds, B => un17_m_en, Y => un1_dci_12_0); - - \r.mmctrl1.pso_RNI3H092\ : OR3B - port map(A => N_3259, B => N_3320, C => maddress(8), Y => - N_3302); - - \r.dstate_i_2_RNISK8N1_10[8]\ : OR2B - port map(A => dataout_0(12), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[112]\); - - \r.dstate_i_2_RNIPA514[8]\ : AOI1 - port map(A => un1_m0_2_63, B => miscdata_4_sqmuxa, C => - miscdata_0_sqmuxa, Y => \rdatav_0_1_1_iv_2[21]\); - - \r.size[0]\ : DFN1E1 - port map(D => size_0_0, CLK => lclk_c, E => N_486_0, Q => - \size[0]\); - - \r.mmctrl1.e_RNIVDG11\ : NOR3B - port map(A => asi(4), B => e_RNIKN3D, C => N_505, Y => - dstate_tr8_4_9_0_a2_0_a2_0_a2_0); - - \r.xaddress_RNIQDEG2[0]\ : OR2B - port map(A => \ddatainv_0_1_0_0[24]\, B => N_575, Y => - \xaddress_RNIQDEG2[0]\); - - \r.xaddress_RNIA46U81[11]\ : MX2A - port map(A => N_2238, B => eaddress_9, S => taddr_2_sqmuxa, - Y => \taddr_7[11]\); - - \r.valid_0_RNI7F6M2[0]\ : AO1C - port map(A => N_679, B => N_3421, C => N_345, Y => - \valid_0_RNI7F6M2[0]\); - - \r.xaddress_RNIS0S1I[8]\ : OR2 - port map(A => N_3289, B => N_3290, Y => \address_i_1[6]\); - - \r.dstate_RNICFIMC[1]\ : MX2 - port map(A => maddress(17), B => edata2_0_iv(17), S => - edata_0_sqmuxa_i, Y => \edata[17]\); - - \r.xaddress_RNI74LI2[4]\ : NOR3 - port map(A => N_3657, B => \vmask_0_5_1_0[2]\, C => N_3655, - Y => \vmask_0_5[2]\); - - \r.xaddress_RNIJH2O2[0]\ : NOR2B - port map(A => dataout(15), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[239]\); - - \r.dstate_i_2_RNITQRS1_1[8]\ : NOR2B - port map(A => \miscdata_2_sqmuxa_0_a4_0_a2_0_a3_0\, B => - N_3320, Y => miscdata_2_sqmuxa); - - mexc_0_sqmuxa_i_o2 : OR2A - port map(A => un1_m0_2_34, B => un1_m0_2_0_d0, Y => N_580); - - \r.flush_RNI7M41E91\ : AO1C - port map(A => twrite_14_iv_0_a2_a0_RNIGON1LK, B => - \dstate_RNIR2CO3[4]\, C => N_349, Y => N_3835); - - \r.mmctrl1.ctxp_RNI1J38A[13]\ : NOR3C - port map(A => tlbdis_m, B => \rdatav_0_1_0_iv_0_2[15]\, C - => \ctxp_m[13]\, Y => \rdatav_0_1_0_iv_0_4[15]\); - - \r.dstate_i_RNISEF4J92[8]\ : AO1D - port map(A => cctrlwr19_1_0, B => un1_dci_12, C => - \dstate_i[8]\, Y => burst_0_sqmuxa_3); - - \r.wb.addr_RNO[2]\ : AO1B - port map(A => maddress(2), B => N_2164, C => - \addr_1_0_iv_0_3[2]\, Y => \addr_1[2]\); - - \r.vaddr[24]\ : DFN1E1 - port map(D => maddress(24), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[24]\); - - \r.dstate_0_RNI6TSB21[2]\ : OR3C - port map(A => \rdatav_0_1_1_iv_5[21]\, B => - \rdatav_0_1_1_iv_4[21]\, C => \mcdo_m_0[21]\, Y => - data_0_21); - - \r.hit_RNO_2\ : NOR2B - port map(A => hit_1_iv_0_a2_0, B => N_84, Y => hit_RNO_2); - - \r.wb.data2_RNI24132[30]\ : AOI1B - port map(A => dataout_0(26), B => rdatasel_1_sqmuxa_1_0, C - => \data2_m[30]\, Y => \rdatav_0_1_0_iv_0[30]\); - - \r.paddress[6]\ : DFN1E1 - port map(D => un1_m0_2_7, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[6]\); - - \r.mmctrl1.ctxp_RNI3QJ12[27]\ : OR2B - port map(A => \ctxp[27]\, B => N_3344_i_0_0, Y => - \ctxp_m[27]\); - - \r.dstate_i_2_RNIAD9N[8]\ : NOR2B - port map(A => N_507, B => N_3745, Y => - \dstate_ns_i_a4_i_a2_0[0]\); - - \r.dstate_i_2_RNI76B62[8]\ : OR2 - port map(A => \dstate_i_2[8]\, B => N_485, Y => - addr_3_sqmuxa); - - \r.ready_RNO_3\ : MX2C - port map(A => N_512, B => asi(3), S => N_519, Y => - N_16828_tz); - - \r.wb.data2[14]\ : DFN1E1 - port map(D => \data2_1[14]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[14]\); - - \r.cctrl.dcs_RNIB9M04[0]\ : AOI1B - port map(A => \dcs[0]\, B => rdatav_0_0_sqmuxa, C => - \mmudco_m[38]\, Y => \rdatav_0_1_0_iv_2[2]\); - - \r.burst_RNO_0\ : AO1C - port map(A => \burst\, B => burst_0_sqmuxa_5, C => rst, Y - => burst_1_m8_i_0); - - \r.dstate_i_RNICU82792[8]\ : NOR2A - port map(A => read_1, B => \N_121\, Y => N_3781); - - \r.wb.data2_RNO[9]\ : MX2 - port map(A => edata2_0_iv(9), B => hrdata_0_9, S => - \dstate[7]\, Y => \data2_1[9]\); - - \r.flush_RNIKBAG1\ : AO1 - port map(A => read_1, B => N_132, C => mexc_1_m_0_a2_0_2_0, - Y => mexc_1_m_0_a2_0_1); - - \r.faddr_RNO[5]\ : NOR3C - port map(A => rst, B => flush_0, C => I_24_1, Y => - \faddr_1[5]\); - - \dctrl.0.un1_dci_9_0\ : XNOR2 - port map(A => dataout_0(17), B => maddress(21), Y => - un1_dci_9_i); - - \r.read_RNILAFM8\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_16, Y => - \mcdo_m_i[16]\); - - \r.asi_RNIF2TA[2]\ : NOR2B - port map(A => \asi_0[2]\, B => \asi_0[3]\, Y => un1_m_en_1); - - \r.mmctrl1.ctx_0_0[7]\ : DFN1 - port map(D => \ctx_0_0_RNID9UO[7]\, CLK => lclk_c, Q => - \ctx_0[7]\); - - \r.dstate_RNIPE6G5[1]\ : AO1 - port map(A => \edata[2]\, B => ddatainv_0_3_sqmuxa, C => - \dcramo_m[226]\, Y => \ddatainv_0_1_1_iv_0[2]\); - - \r.wb.addr_RNO_4[23]\ : MX2 - port map(A => \paddress[23]\, B => \addr[23]\, S => N_484_0, - Y => N_3838); - - \r.dstate_RNO_15[4]\ : OR2 - port map(A => N_3499, B => N_16887_tz_tz, Y => - dstate_ns_0_2065_0); - - \r.wb.addr[21]\ : DFN1 - port map(D => \addr_1[21]\, CLK => lclk_c, Q => - \address[21]\); - - \r.mmctrl1.ctxp_RNIRD91A[26]\ : NOR3C - port map(A => \mmudco_m[71]\, B => \rdatav_0_1_1_iv_2[28]\, - C => \ctxp_m[26]\, Y => \rdatav_0_1_1_iv_4[28]\); - - \r.mmctrl1.ctxp_RNIDPN0C[19]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_2[21]\, B => - \rdatav_0_1_1_iv_1[21]\, C => \ctxp_m[19]\, Y => - \rdatav_0_1_1_iv_4[21]\); - - \r.dstate_i_0_RNIQR7N[8]\ : NOR3B - port map(A => dstate_tr20_0, B => hold_0, C => - \dstate_i_0[8]\, Y => dstate_tr20_2); - - \r.vaddr[5]\ : DFN1E1 - port map(D => maddress(5), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[5]\); - - \r.mmctrl1.ctxp_RNIK8BOF[20]\ : NOR3C - port map(A => \ctxp_m[20]\, B => \rdatav_0_1_0_iv_2[22]\, C - => \rdatav_0_1_0_iv_4[22]\, Y => rdatav_0_1_0_iv_5_18); - - \r.flush_RNI2I582\ : OR2 - port map(A => flush_0, B => mexc, Y => flush_i); - - \r.vaddr_RNI66HC[30]\ : MX2 - port map(A => maddress(30), B => \vaddr[30]\, S => - \dstate_i_1[8]\, Y => \data[30]\); - - \r.paddress[17]\ : DFN1E1 - port map(D => un1_m0_2_18, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[17]\); - - \r.dstate_RNO[0]\ : AOI1B - port map(A => \dstate_ns_0_0_0[8]\, B => N_3556, C => rst, - Y => \dstate_nss[8]\); - - \r.dstate_RNIIRS9_0[2]\ : NOR2A - port map(A => \dstate[2]\, B => diagrdy, Y => - ilramen_1_sqmuxa); - - \r.cctrl.dcs_RNI14TA2[0]\ : NOR2B - port map(A => \dcs[0]\, B => N_495, Y => - setrepl_0_sqmuxa_1_m_i_5_0); - - \r.xaddress[13]\ : DFN1E1 - port map(D => maddress(13), CLK => lclk_c, E => N_486, Q - => \addr[13]\); - - \r.wb.addr[29]\ : DFN1 - port map(D => \addr_1[29]\, CLK => lclk_c, Q => - \address[29]\); - - \r.wb.addr[11]\ : DFN1 - port map(D => \addr_1[11]\, CLK => lclk_c, Q => - \address[11]\); - - \r.dstate_RNIG74RG[1]\ : AO1 - port map(A => \dstate_RNII450C[1]\, B => \size_RNIBHS22[0]\, - C => \dcramo_m[232]\, Y => \ddatainv_0_1_1_iv_0[8]\); - - \dctrl.vmaskraw_1_i_o2_i_o2[1]\ : OR2A - port map(A => N_3747, B => \addr[2]\, Y => N_559); - - \r.mmctrl1.e_0_0_RNI8APPC92\ : NOR3 - port map(A => \dstate_i_2_RNITVLGB92[8]\, B => N_3778, C - => holdn_3_sqmuxa_0_0_a2_2_0, Y => e_0_0_RNI8APPC92); - - \r.flush_RNI8M718\ : NOR3B - port map(A => \mmudco_m[57]\, B => \rdatav_0_1_0_iv_1[14]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_3[14]\); - - \r.wb.data2_RNI9BB72[1]\ : NOR2B - port map(A => N_89, B => N_3233, Y => - \rdatav_0_1_0_iv_i_a4_0[1]\); - - \r.wb.addr[19]\ : DFN1 - port map(D => \addr_1[19]\, CLK => lclk_c, Q => - \address[19]\); - - \r.dstate_RNO_8[5]\ : OR3A - port map(A => \dstate[4]\, B => wbinit, C => N_506, Y => - N_3180_i); - - \r.mmctrl1.ctxp_RNIBIFRD[29]\ : NOR3C - port map(A => \ctxp_m[29]\, B => \rdatav_0_1_0_iv_1[31]\, C - => \rdatav_0_1_0_iv_3[31]\, Y => \rdatav_0_1_0_iv_4[31]\); - - \r.vaddr[11]\ : DFN1E1 - port map(D => maddress(11), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[11]\); - - \r.dstate_i_2_RNISK8N1_9[8]\ : OR2B - port map(A => dataout_0(14), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[114]\); - - \r.wb.data1[28]\ : DFN1E0 - port map(D => \data1_1[28]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_16); - - \r.dstate_RNIGLO42[7]\ : NOR2A - port map(A => \dstate[7]\, B => N_510, Y => N_84); - - \dctrl.0.un1_dci_5_0\ : XNOR2 - port map(A => maddress(17), B => dataout_0(13), Y => - un1_dci_5_i); - - \r.wb.data2_RNI5S032[19]\ : AOI1B - port map(A => \data2[19]\, B => rdatav_012_0, C => - \dcramo_m[115]\, Y => \rdatav_0_1_0_iv_0[19]\); - - \r.cctrlwr_RNO\ : NOR2A - port map(A => N_227, B => N_3790, Y => N_2715_i); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_0[10]\ : NOR3C - port map(A => N_3726, B => N_3641, C => N_3642, Y => - \addr_1_1_iv_0_2[10]\); - - \r.wb.addr_RNO_4[25]\ : OR2B - port map(A => \address[25]\, B => N_514, Y => \addr_m[25]\); - - \r.dstate_i_2_RNISK8N1_21[8]\ : OR2B - port map(A => dataout_0(25), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[125]\); - - \r.cctrl.ics_RNO_1[1]\ : NOR3B - port map(A => \ics_0_i_a4_1_0[1]\, B => \N_523\, C => - intack, Y => N_3204); - - \un1_r.faddr_I_16\ : AND3 - port map(A => \faddr[0]\, B => \faddr[1]\, C => \faddr[2]\, - Y => \DWACT_FINC_E[0]\); - - \r.mmctrl1.ctxp_RNII5F32[2]\ : NAND2 - port map(A => N_3344_i_0_0, B => \ctxp[2]\, Y => - \ctxp_m[2]\); - - \r.holdn_RNIFRAS\ : OR3A - port map(A => size_0_0, B => N_3757, C => maddress_0_0, Y - => N_3600); - - \r.valid_0_RNIQ2NB[2]\ : NOR2B - port map(A => \valid_0[2]\, B => hit, Y => - \vmask_0_5_1_a2_2_0[2]\); - - \r.xaddress_RNI4PC9O[1]\ : AOI1B - port map(A => \edata[12]\, B => ddatainv_0_4_sqmuxa, C => - \edata_m_4_i[4]\, Y => \ddatainv_0_1_0_iv_1[28]\); - - \r.wb.addr_RNO_2[6]\ : OR2B - port map(A => maddress(6), B => N_2164, Y => N_3627); - - \r.vaddr_RNI12EE[7]\ : MX2 - port map(A => maddress(7), B => \vaddr[7]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[83]\); - - \r.dstate_2_RNI4UR08[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_8, Y => - \mcdo_m_0[8]\); - - \r.burst_RNO_2\ : NOR3 - port map(A => burst_0_sqmuxa_5, B => burst_1_m8_i_a5_0, C - => burst_1_N_7, Y => burst_1_N_9); - - \r.wb.addr_RNO_5[26]\ : MX2 - port map(A => \paddress_0[26]\, B => \addr[26]\, S => N_484, - Y => \paddress[26]\); - - \r.dstate_i_2_RNIN4022[8]\ : OR2B - port map(A => un1_m0_2_37, B => miscdata_3_sqmuxa, Y => - \mmudco_m[38]\); - - \r.dstate_i_2[8]\ : DFN1 - port map(D => \dstate_nss_i_0[0]\, CLK => lclk_c, Q => - \dstate_i_2[8]\); - - \r.wb.addr_RNO[22]\ : AO1B - port map(A => un1_m0_2_97, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[22]\, Y => \addr_1[22]\); - - \r.vaddr_RNICQHC[17]\ : MX2 - port map(A => maddress(17), B => \vaddr[17]\, S => - \dstate_i_1[8]\, Y => data(17)); - - \r.mmctrl1.tlbdis_RNIJT322\ : OR2B - port map(A => \tlbdis\, B => miscdata_0_sqmuxa, Y => - tlbdis_m); - - \r.xaddress_RNIQF6M2_3[0]\ : OR2B - port map(A => dataout(24), B => N_2088, Y => - \dcramo_m_i[248]\); - - \r.dstate_RNIVFCD[0]\ : NOR2 - port map(A => \dstate[1]\, B => \dstate[0]\, Y => holdn_0_0); - - \r.xaddress_RNIQDEG2_0[0]\ : OR2B - port map(A => \ddatainv_0_1_3_0[0]\, B => N_575, Y => - \xaddress_RNIQDEG2_0[0]\); - - \r.wb.addr_RNO[16]\ : AO1B - port map(A => un1_m0_2_91, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_2[16]\, Y => \addr_1[16]\); - - \r.faddr_RNO[1]\ : NOR3C - port map(A => rst, B => flush_0, C => I_5_1, Y => - \faddr_1[1]\); - - \r.wb.data1_RNO[30]\ : MX2A - port map(A => N_2128, B => maddress(30), S => - req_0_sqmuxa_1, Y => \data1_1[30]\); - - \r.mmctrl1.tlbdis_RNO\ : NOR2B - port map(A => rst, B => N_2673, Y => tlbdis_RNO); - - \r.wb.size_RNO[0]\ : MX2 - port map(A => size_0_0, B => \size[0]\, S => \dstate_i[8]\, - Y => N_653); - - \r.mmctrl1.ctx[7]\ : DFN1 - port map(D => \ctx_0_0_RNID9UO[7]\, CLK => lclk_c, Q => - \ctx[7]\); - - \r.mmctrl1.ctxp[3]\ : DFN1E1 - port map(D => maddress(5), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[3]\); - - \r.holdn_RNIABJM\ : OR3C - port map(A => maddress_0_0, B => N_3748, C => size_0_0, Y - => N_3700); - - mmudci_trans_op_1_sqmuxa_1_0_o2 : NOR2 - port map(A => N_3791, B => N_492, Y => N_503); - - \r.vaddr_RNI26HC[12]\ : MX2 - port map(A => maddress(12), B => \vaddr[12]\, S => - \dstate_i_1[8]\, Y => \data[12]\); - - \r.dstate_RNIS3JC[2]\ : NOR2B - port map(A => dataout_1(11), B => \dstate[2]\, Y => - \ico_m_0[145]\); - - \r.dstate_i_2_RNI9SET1[8]\ : OR3B - port map(A => maddress_0_2, B => maddress(2), C => - rdatasel_0_sqmuxa_1, Y => rdatav_0_2_sqmuxa); - - \dctrl.0.un1_dci_11_0\ : XNOR2 - port map(A => dataout_0(19), B => maddress(23), Y => - un1_dci_11_i); - - \r.wb.addr_RNO[25]\ : AO1B - port map(A => \mmudco_m_0[101]\, B => N_2714, C => - \addr_1_1_iv_2[25]\, Y => \addr_1[25]\); - - \r.dstate_RNI6BSIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[6]\, Y => \ddatainv_0_1_0_iv_1[22]\); - - \r.dstate_2_RNISVQTU[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_7[4]\, B => - \rdatav_0_1_0_iv_6[4]\, C => \mcdo_m_0[4]\, Y => data_0_4); - - \r.xaddress_RNIV1DSTI[23]\ : AOI1B - port map(A => \addr[23]\, B => \N_330\, C => N_3878, Y => - \newtag_1_0[23]\); - - \r.wb.data2_RNO[12]\ : MX2 - port map(A => edata2_0_iv(12), B => hrdata_0_12, S => - \dstate_0[7]\, Y => \data2_1[12]\); - - \r.nomds_RNISER4B92\ : OR2A - port map(A => N_509, B => un1_dci_12, Y => N_511); - - \r.paddress[3]\ : DFN1E1 - port map(D => un1_m0_2_4, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[3]\); - - \r.mmctrl1.ctx_0_0_RNIETOV1[4]\ : OR2B - port map(A => \ctx_0[4]\, B => miscdata_2_sqmuxa, Y => - \ctx_m[4]\); - - \dctrl.0.un1_dci_3_0_0_x2\ : XNOR2 - port map(A => dataout_0(11), B => maddress(15), Y => - N_149_i_i); - - \r.dstate_i_2_RNISK8N1_6[8]\ : OR2B - port map(A => dataout_0(21), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[121]\); - - \r.read_RNIL633F1\ : OR3 - port map(A => \mcdo_m[14]\, B => \edata_m_1[6]\, C => - \ddatainv_0_1_1_iv_0[14]\, Y => read_RNIL633F1); - - \r.paddress[30]\ : DFN1E1 - port map(D => un1_m0_2_31, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress_0[30]\); - - \r.nomds_RNIJ0HM01\ : NOR2A - port map(A => twrite_14_iv_0_o2_a1_2, B => me_nullify2_1_2, - Y => twrite_14_iv_0_o2_a1_3); - - \r.size[1]\ : DFN1E1 - port map(D => size_1_d0, CLK => lclk_c, E => N_486_0, Q => - \size_0[1]\); - - \r.holdn_RNO_19\ : NOR2A - port map(A => N_3604, B => \dstate_0[2]\, Y => holdn_0); - - \dctrl.0.un1_dci_NE_13\ : NOR3C - port map(A => un1_dci_16_i, B => un1_dci_11_i, C => - un1_dci_NE_7, Y => un1_dci_NE_13); - - \r.dstate_i_2_RNIKF842[8]\ : OR2B - port map(A => un1_m0_2_55, B => miscdata_4_sqmuxa, Y => - \mmudco_m[56]\); - - \r.wb.data1_RNO_0[2]\ : MX2B - port map(A => edata2_0_iv(2), B => \data2[2]\, S => N_3331, - Y => N_2100); - - \r.xaddress_RNIQ3QK4[2]\ : MX2C - port map(A => maddress(2), B => \addr[2]\, S => - un1_taddr_1_sqmuxa, Y => N_2229); - - \r.wb.addr_RNO_1[4]\ : AOI1B - port map(A => \dstate_RNIP22L4[7]\, B => N_678, C => - \mmudco_m[80]\, Y => \addr_1_1_iv_0_0[4]\); - - \r.dstate_0_RNISS4BF[2]\ : NOR3C - port map(A => \ctxp_m[22]\, B => \rdatav_0_1_0_iv_2[24]\, C - => \rdatav_0_1_0_iv_4[24]\, Y => \rdatav_0_1_0_iv_5[24]\); - - \r.xaddress_RNIUGTB[3]\ : NOR3A - port map(A => flush_0_sqmuxa_0_o3_i_o2_0, B => \addr[3]\, C - => read_0, Y => flush_0_sqmuxa_0_o3_i_o2_5); - - \r.flush\ : DFN1 - port map(D => N_2710_i, CLK => lclk_c, Q => flush_0); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_2\ : NOR3A - port map(A => eaddress_0, B => eaddress_3, C => eaddress_7, - Y => vaddr_1_sqmuxa_0_a2_4_m1_e_2); - - \r.wb.addr_RNO_3[24]\ : OR2B - port map(A => \address[24]\, B => N_514, Y => N_3739); - - \r.mmctrl1.ctx[4]\ : DFN1 - port map(D => \ctx_0_0_RNI7TTO[4]\, CLK => lclk_c, Q => - ctx(4)); - - \r.dstate_RNIFF53J[4]\ : NOR3C - port map(A => N_3682, B => \dstate_ns_i_a4_i_2[0]\, C => - \dcs_RNIBN6EB[0]\, Y => \dstate_ns_i_a4_i_4[0]\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNI9ON72\ : OR2A - port map(A => N_495, B => N_502, Y => N_527); - - \dctrl.twrite_14_iv_0_a2_a0_RNIGON1LK\ : AO1B - port map(A => N_3322, B => N_3246, C => - \dstate_i_RNII68N892_0[8]\, Y => - twrite_14_iv_0_a2_a0_RNIGON1LK); - - \r.wb.data1_RNO_0[19]\ : MX2C - port map(A => edata2_0_iv(19), B => \data2[19]\, S => - N_3331, Y => N_2117); - - \r.faddr_RNIBVMU01[5]\ : AO1D - port map(A => eaddress_8, B => N_195, C => N_3295, Y => - \address_i_0[8]\); - - \r.dstate_RNI7GDD[5]\ : NOR2 - port map(A => \dstate[5]\, B => \dstate[4]\, Y => - edata_0_sqmuxa_1); - - \r.wb.addr[26]\ : DFN1 - port map(D => \addr_1[26]\, CLK => lclk_c, Q => - \address[26]\); - - \r.paddress[0]\ : DFN1E1 - port map(D => un1_m0_2_1, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress_0[0]\); - - \r.dstate_i_2_RNISK8N1_27[8]\ : OR2B - port map(A => dataout_0(4), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[100]\); - - \r.wb.data1[16]\ : DFN1E0 - port map(D => \data1_1[16]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_4); - - \r.mmctrl1.nf\ : DFN1 - port map(D => nf_RNO, CLK => lclk_c, Q => \nf\); - - \r.dstate_i_2_RNIF2GP[8]\ : NOR2A - port map(A => lock, B => N_526, Y => dstate_tr22_15_a2_9_0); - - \r.dstate_RNIHTD53[3]\ : NOR3A - port map(A => \dstate_RNIET0O2[5]\, B => \dstate[3]\, C => - \dstate[2]\, Y => dstate_17_2); - - \r.dstate_RNI3I7EH[7]\ : MX2C - port map(A => N_3339, B => hrdata_0_3, S => \dstate[7]\, Y - => N_3340); - - \r.dstate_0_RNI16DP2[2]\ : NOR3B - port map(A => dstate_19_1, B => data2_1_sqmuxa, C => - \dstate_0[2]\, Y => dstate_19_3); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_1[10]\ : AOI1B - port map(A => \paddress[10]\, B => N_3792, C => N_3725, Y - => \addr_1_1_iv_0_1[10]\); - - \r.wb.addr[16]\ : DFN1 - port map(D => \addr_1[16]\, CLK => lclk_c, Q => - \address[16]\); - - \r.dstate_i_RNIKIKVI92[8]\ : AOI1B - port map(A => un19_m_en_m_2, B => un19_m_en_m_1, C => - un157_m_en_m, Y => dwrite_1_iv_1); - - \r.cctrl.burst_RNI4ATO7\ : NOR3B - port map(A => \rdatav_0_1_1_iv_0[16]\, B => burst_m, C => - \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_2[16]\); - - \r.xaddress_RNICFI17S2[13]\ : OR3C - port map(A => N_3849, B => N_3848, C => \dci_m[85]\, Y => - xaddress_RNICFI17S2(13)); - - \r.wb.data1_RNO_0[25]\ : MX2C - port map(A => edata2_iv_i_0(25), B => \data2[25]\, S => - N_3331_0, Y => N_2123); - - \r.paddress[5]\ : DFN1E1 - port map(D => un1_m0_2_6, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[5]\); - - \r.mmctrl1.ctxp[9]\ : DFN1E1 - port map(D => maddress(11), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[9]\); - - \r.trans_op_RNO\ : NOR3A - port map(A => rst, B => un2_m_tlb_type, C => \trans_op\, Y - => trans_op_RNO_1); - - \r.dstate_i_2_RNIOV842[8]\ : OR2B - port map(A => un1_m0_2_59, B => miscdata_4_sqmuxa, Y => - \mmudco_m[60]\); - - \r.dstate_i_2_RNI447L1[8]\ : NOR2 - port map(A => maddress(10), B => rdatasel_4_sqmuxa, Y => - N_3320); - - \r.wb.data1_RNO[20]\ : MX2A - port map(A => N_2118, B => maddress(20), S => - req_0_sqmuxa_1_0, Y => \data1_1[20]\); - - \r.dstate_i_2_RNISK8N1_7[8]\ : OR2B - port map(A => dataout_0(17), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[117]\); - - \r.wb.data2_RNI7FOB[31]\ : OR2B - port map(A => \data2[31]\, B => rdatav_012, Y => - \data2_m[31]\); - - \r.flush_0_1_RNIO3F3O61\ : OA1A - port map(A => \un1_p0_2_0[498]\, B => N_3248, C => N_3282, - Y => \vmask_0_1_i_1[7]\); - - \r.dstate_i_RNICGCDG92[8]\ : OR2A - port map(A => edata2_0_iv(7), B => - \dstate_i_RNII68N892_0[8]\, Y => N_3279); - - \r.xaddress_RNIRDIV8[8]\ : NOR3B - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - \addr[8]\, Y => N_3290); - - \r.xaddress_RNIK99NK1[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[29]\, B => - \mcdo_m_i[29]\, C => \ddatainv_0_1_0_iv_1[29]\, Y => - xaddress_RNIK99NK1(1)); - - \r.wb.data1[30]\ : DFN1E0 - port map(D => \data1_1[30]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_18); - - \r.mmctrl1.ctx_0_0_RNINUPHF[5]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_i_a2_4[5]\, B => - \rdatav_0_1_1_iv_i_a2_3[5]\, C => N_3395, Y => - \rdatav_0_1_1_iv_i_a2_6[5]\); - - \r.holdn_RNO_27\ : NOR2A - port map(A => holdn_0_sqmuxa_1_m8_0_a2_0, B => N_576, Y => - holdn_0_sqmuxa_1_m8_0_a2_1); - - \r.dstate_i_2_RNIA2SML3[8]\ : OR2A - port map(A => vaddr_1_sqmuxa_0_0, B => - \mmudci_trans_op_1_sqmuxa_1\, Y => vaddr_1_sqmuxa_0); - - \r.wb.addr_RNO_5[20]\ : OR2B - port map(A => N_417, B => addr_1_sqmuxa_0, Y => N_3862); - - \r.dstate_1_RNIP4DE1[7]\ : OR2B - port map(A => \dstate_1[7]\, B => hrdata_0_13, Y => - \mcdo_m_0[13]\); - - \r.dstate_RNI9MVN21[2]\ : OR3C - port map(A => \rdatav_0_1_1_iv_i_a2_6[5]\, B => N_3397, C - => N_3341, Y => N_3389_i_0); - - \r.dstate_i_2_RNIHH1P1[8]\ : NOR2A - port map(A => N_3320, B => maddress(9), Y => N_3321); - - \r.read_RNISF83A\ : NOR2B - port map(A => \N_425\, B => hrdata_0_7, Y => \mcdo_m[7]\); - - \r.mmctrl1.e_RNIVSEJ1\ : NOR3B - port map(A => N_3755, B => e_RNIKN3D, C => N_590, Y => - N_2994_8); - - \r.mmctrl1.ctx_RNIB8BR[0]\ : NOR2B - port map(A => rst, B => N_2663, Y => \ctx_RNIB8BR[0]\); - - \r.wb.lock\ : DFN1E0 - port map(D => lock_1, CLK => lclk_c, E => lock_2_sqmuxa, Q - => \lock_0\); - - \r.holdn_RNI1OS81\ : NOR2 - port map(A => maddress(4), B => N_3808, Y => N_3655); - - \r.read_RNIC9O9B1\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[21]\, B => - \mcdo_m_i[21]\, C => \ddatainv_0_1_0_iv_1[21]\, Y => - read_RNIC9O9B1); - - \r.dstate_RNI1G47MJ[1]\ : OR3C - port map(A => dwrite_1_iv_0, B => dwrite_4_sqmuxa, C => - dwrite_1_iv_1, Y => dstate_RNI1G47MJ(1)); - - \r.dstate_i_2_RNINR842[8]\ : OR2B - port map(A => un1_m0_2_58, B => miscdata_4_sqmuxa, Y => - \mmudco_m[59]\); - - \r.cctrl.burst\ : DFN1 - port map(D => burst_RNO_0, CLK => lclk_c, Q => \burst_0\); - - \r.mmctrl1.ctxp_RNI7PLC21[1]\ : OR3C - port map(A => \rdatav_0_1_1_iv_i_a2_6[3]\, B => N_3404, C - => N_3340, Y => N_3387_i_0); - - \r.dstate_0_RNIJAURF92[7]\ : AOI1B - port map(A => \dstate_ns_0_0_a2_0[1]\, B => N_3781, C => - \dstate_ns_0_0_0[1]\, Y => \dstate_ns_0_0_1[1]\); - - \dctrl.0.un1_dci_13_0\ : XNOR2 - port map(A => maddress(25), B => dataout_0(21), Y => - un1_dci_13_i); - - \r.flush_op_RNO\ : NOR3A - port map(A => rst, B => un2_m_tlb_type, C => \flush_op_i_0\, - Y => flush_op_RNO); - - \r.wb.addr_RNO_5[22]\ : OR2B - port map(A => un1_m0_2_23, B => addr_1_sqmuxa_0, Y => - N_3873); - - \dctrl.rdatav_0_1_0_iv[24]\ : NAND2 - port map(A => \mcdo_m_0[24]\, B => \rdatav_0_1_0_iv_5[24]\, - Y => data_0_24); - - \dctrl.mexc_1_m_0_a2_0_2_0\ : OR2 - port map(A => N_519, B => N_3091_3, Y => - mexc_1_m_0_a2_0_2_0); - - \r.wb.addr_RNO_0[4]\ : NOR3C - port map(A => \addr_1_1_iv_0_0[4]\, B => \addr_m[4]\, C => - \mmudco_m[6]\, Y => \addr_1_1_iv_0_2[4]\); - - \r.read_RNIOV4L7\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_22, Y => - \mcdo_m_i[22]\); - - \r.dstate_tr22_15_a2_15_0\ : OR2 - port map(A => asi(3), B => N_505, Y => - dstate_tr22_15_a2_15_0); - - \r.dstate_RNO_1[3]\ : NOR2B - port map(A => un1_m0_2_0_d0, B => \dstate[3]\, Y => N_3672); - - \r.wb.data2_RNI37OB[13]\ : OR2B - port map(A => \data2[13]\, B => rdatav_012_0, Y => - \data2_m[13]\); - - \r.mmctrl1.ctxp_RNIVLJ12[16]\ : OR2B - port map(A => \ctxp[16]\, B => N_3344_i_0, Y => - \ctxp_m[16]\); - - \r.mmctrl1.ctxp_RNIATS86[10]\ : NOR3C - port map(A => \mmudco_m[55]\, B => - \rdatav_0_1_0_iv_0_0[12]\, C => \ctxp_m[10]\, Y => - \rdatav_0_1_0_iv_0_2[12]\); - - \r.flush_0_1_RNIHVA8LK\ : NOR3B - port map(A => N_3322, B => \un1_p0_2_0[498]\, C => N_3248, - Y => N_184); - - \r.wb.addr_RNO[21]\ : AO1B - port map(A => un1_m0_2_96, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[21]\, Y => \addr_1[21]\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNIMS3C2\ : OR2A - port map(A => read_1, B => N_527, Y => N_608); - - \r.read_RNIQFOD21\ : OR3 - port map(A => \mcdo_m[4]\, B => \edata_m_0[4]\, C => - \ddatainv_0_1_1_iv_0[4]\, Y => read_RNIQFOD21); - - \r.dstate_RNIJ9IBG[1]\ : AOI1B - port map(A => dataout(20), B => \xaddress_RNI1CIE2_0[0]\, C - => \edata_m_i[20]\, Y => \ddatainv_0_1_0_iv_0[20]\); - - \r.mmctrl1.tlbdis_RNO_0\ : MX2 - port map(A => \tlbdis\, B => maddress(15), S => e_0_sqmuxa, - Y => N_2673); - - \r.mmctrl1.ctxp_RNI2MJ12[19]\ : OR2B - port map(A => \ctxp[19]\, B => N_3344_i_0, Y => - \ctxp_m[19]\); - - \r.wb.data2_RNIQBA74[20]\ : NOR3C - port map(A => \dcramo_m[116]\, B => \data2_m[20]\, C => - \mmudco_m[63]\, Y => \rdatav_0_1_0_iv_1[20]\); - - \r.dstate_RNI1HM61[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_0_26, Y => - \mcdo_m_0[26]\); - - \dctrl.twrite_14_iv_0_a2_a0_RNIGF1B4U2\ : AO1C - port map(A => N_3248, B => N_3322, C => N_2381, Y => N_296); - - \r.holdn_RNO_21\ : NOR3A - port map(A => holdn_0_sqmuxa_1_m8_0_a2_1, B => - cctrlwr19_2_0_a2_1_1, C => dcs_1_i_s_0_o2_0_RNIMMIH9, Y - => holdn_0_sqmuxa_1_m8_0_a2_3); - - \r.wb.data2_RNIOLJ16[22]\ : NOR3B - port map(A => \mmudco_m[65]\, B => \rdatav_0_1_0_iv_0[22]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_2[22]\); - - \un1_v.cctrlwr11_0\ : AO1C - port map(A => asi(0), B => N_3779, C => cctrlwr12, Y => - cctrlwr11_0); - - \r.paddress[8]\ : DFN1E1 - port map(D => un1_m0_2_9, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress_0[8]\); - - \r.paddress[27]\ : DFN1E1 - port map(D => N_293, CLK => lclk_c, E => paddress_1_sqmuxa, - Q => \paddress[27]\); - - \r.faddr_RNIB0UOO[2]\ : MX2 - port map(A => \taddr_7[7]\, B => \faddr[2]\, S => flush_0, - Y => faddr_RNIB0UOO(2)); - - \r.dstate_RNI9QJBG[1]\ : AOI1B - port map(A => \edata[22]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[246]\, Y => \ddatainv_0_1_0_iv_0[22]\); - - \r.xaddress[23]\ : DFN1E1 - port map(D => maddress(23), CLK => lclk_c, E => N_486, Q - => \addr[23]\); - - \r.mmctrl1.pso_RNO_0\ : MX2 - port map(A => pso, B => maddress(7), S => e_0_sqmuxa, Y => - N_2674); - - \r.wb.data2_RNI4S032[18]\ : NOR2B - port map(A => \data2_m[18]\, B => \dcramo_m[114]\, Y => - \rdatav_0_1_0_iv_0[18]\); - - \r.wb.data2[12]\ : DFN1E1 - port map(D => \data2_1[12]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[12]\); - - \r.wb.addr_RNO_5[3]\ : OR2B - port map(A => \un1_m0_2[79]\, B => addr_1_sqmuxa_2, Y => - N_294); - - \r.valid_0_RNO[4]\ : OA1B - port map(A => hit_1_iv_0_a2_0_0, B => twrite_14, C => - N_2364, Y => \valid_0_1[4]\); - - \r.size_RNI8H2U[1]\ : AO1B - port map(A => size_1_d0, B => N_3748, C => N_3766, Y => - ddatainv_0_6_sqmuxa); - - \r.dstate_RNIFHVNC[1]\ : MX2 - port map(A => maddress(10), B => edata2_0_iv(10), S => - edata_0_sqmuxa_i_0, Y => \edata[10]\); - - \r.dstate_i_0_RNI4GFP2[8]\ : AO1B - port map(A => N_3421, B => N_679, C => \vmask_0_5_1_0[4]\, - Y => \vmask_0_5[4]\); - - \r.read_RNIS71C7\ : NOR2B - port map(A => \N_425_0\, B => hrdata_0_12, Y => - \mcdo_m[12]\); - - \r.ready_RNO_0\ : OR2B - port map(A => \dstate_i_RNIF4S5B92[8]\, B => N_16828_tz, Y - => ready_RNO_0); - - \r.mmctrl1.ctxp[29]\ : DFN1E1 - port map(D => maddress(31), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[29]\); - - \r.dstate_RNO[6]\ : AOI1B - port map(A => N_3671, B => \dstate_RNO_1[6]\, C => rst, Y - => \dstate_nss[2]\); - - \r.dstate_i_0_RNITRO4892[8]\ : OR3A - port map(A => dstate_tr20_2, B => N_551, C => N_581_i, Y - => N_3069_i); - - \r.wb.size[0]\ : DFN1E0 - port map(D => N_653, CLK => lclk_c, E => - \dstate_RNI5GFM4[5]\, Q => \size_1[0]\); - - \r.wb.data2[29]\ : DFN1E1 - port map(D => \data2_1[29]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[29]\); - - \r.dstate_i_2_RNIAME21[8]\ : OR3A - port map(A => read_0, B => N_490, C => N_3758, Y => N_3685); - - \r.mmctrl1.ctx_0_0_RNIATOV1[0]\ : OR2B - port map(A => \ctx_0[0]\, B => miscdata_2_sqmuxa, Y => - \ctx_m[0]\); - - \r.dstate_RNISB0BG[1]\ : MX2 - port map(A => maddress(27), B => edata2_iv_i_0(27), S => - edata_0_sqmuxa_i, Y => \edata[27]\); - - \r.mmctrl1.ctxp[7]\ : DFN1E1 - port map(D => maddress(9), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[7]\); - - \r.holdn_RNO_3\ : OA1B - port map(A => un1_dci_12, B => d_m6_i_a3_1, C => - \dstate_i_0[8]\, Y => holdn_RNO_3); - - \r.dstate_RNIVP6I3_0[6]\ : NOR2B - port map(A => N_506, B => N_487, Y => N_3775); - - \r.dstate_i_RNIAGA5V92[8]\ : AO1C - port map(A => \N_121\, B => mexc_1_m_0_2000_0, C => - mexc_1_m_0_1, Y => mexc_1); - - \r.wb.data1[21]\ : DFN1E0 - port map(D => \data1_1[21]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_9); - - \r.holdn_RNO_9\ : AOI1B - port map(A => holdn_3_sqmuxa_0_0_2, B => N_3611, C => - holdn_0, Y => holdn_1); - - \r.mmctrl1.e_RNIL9MBLG3\ : NOR3B - port map(A => un1_m0_2_108, B => \e\, C => lock, Y => N_564); - - \dctrl.v.dstate34_i_o2_0\ : OR2B - port map(A => hold_0, B => eenaddr, Y => N_563); - - \r.xaddress_RNIEOTFII[25]\ : AO1 - port map(A => \addr[25]\, B => \N_330\, C => N_236, Y => - newtag_1_0_7); - - \r.mmctrl1.ctxp_RNID1T86[11]\ : NOR3C - port map(A => \mmudco_m[56]\, B => \rdatav_0_1_0_iv_0[13]\, - C => \ctxp_m[11]\, Y => \rdatav_0_1_0_iv_2[13]\); - - \r.dstate_i_1_RNI0LGRA92[8]\ : OR3C - port map(A => N_111, B => N_32, C => \N_3254_0\, Y => - N_3197); - - \r.paddress[1]\ : DFN1E1 - port map(D => un1_m0_2_2, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress_0[1]\); - - \r.mmctrl1.e_0_0_RNIJB6I3\ : NOR2B - port map(A => dstate_tr22_15_a2_2_m8_i_a5_1_0, B => N_3576, - Y => dstate_tr22_15_a2_2_m8_i_a5_1_1); - - \r.dstate_2_RNIH205M[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[27]\, B => - \rdatav_0_1_0_iv_2[27]\, C => \mcdo_m_0[27]\, Y => - data_0_27); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_0\ : OA1 - port map(A => N_512, B => N_519, C => asi(3), Y => - dcs_1_i_s_0_0); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0_RNIV8VH1[3]\ : AOI1B - port map(A => N_3661, B => N_3660, C => N_679, Y => - N_44_i_0); - - \r.wb.addr_RNO_3[19]\ : OR2B - port map(A => \address[19]\, B => N_514, Y => N_224); - - \r.dstate_i_RNINFEAO92[8]\ : NOR2A - port map(A => edata2_iv_i_0(26), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_90); - - \r.dstate_2_RNIOMNPG[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_23, Y => - mcdo_m_0_22); - - \r.vaddr_RNIBR8G[1]\ : MX2 - port map(A => maddress_0_0, B => \vaddr[1]\, S => - \dstate_i_1[8]\, Y => \un1_m0_2[77]\); - - \r.dstate_i_RNI7IS4E92[8]\ : MX2C - port map(A => N_547, B => N_487, S => \dstate_i[8]\, Y => - N_556); - - \r.wb.addr_RNO_6[26]\ : OR2B - port map(A => N_192, B => addr_1_sqmuxa, Y => - \mmudco_m[28]\); - - \r.flush_RNI7MOL2\ : NOR2 - port map(A => N_3595, B => flush_i, Y => un19_m_en_m_1); - - \un1_r.faddr_I_12\ : AND3 - port map(A => \faddr[0]\, B => \faddr[1]\, C => \faddr[2]\, - Y => N_17); - - \r.dstate_RNIGIR6[4]\ : OR2 - port map(A => \dstate_2[7]\, B => \dstate[4]\, Y => N_3833); - - \r.wb.data1_RNO_0[18]\ : MX2C - port map(A => edata2_0_iv(18), B => \data2[18]\, S => - N_3331_0, Y => N_2116); - - \r.wb.data2_RNO[30]\ : MX2 - port map(A => edata2_iv_i_0(30), B => hrdata_25, S => - \dstate_1[7]\, Y => \data2_1[30]\); - - \r.holdn_RNO_4\ : NOR3A - port map(A => holdn_0_sqmuxa_1_m8_0_a2_5, B => un1_dci_12, - C => accexc_6, Y => holdn_RNO_4); - - \r.dstate_i_RNIKVKHK92[8]\ : OR2A - port map(A => edata2_0_iv(17), B => \N_3254_0\, Y => - \dci_m[89]\); - - \r.wb.data1_RNO[28]\ : MX2A - port map(A => N_2126, B => maddress(28), S => - req_0_sqmuxa_1_0, Y => \data1_1[28]\); - - \r.wb.addr_RNO_5[21]\ : MX2 - port map(A => \paddress[21]\, B => \addr[21]\, S => N_484_0, - Y => N_552); - - \r.wb.size_RNI1RLD[0]\ : OR2B - port map(A => \size_1[1]\, B => \size_1[0]\, Y => size); - - \r.req_RNI9CCP1\ : OR2A - port map(A => ready, B => \req\, Y => N_72_i); - - \r.cctrl.dcs_RNO_1[1]\ : NOR3C - port map(A => \N_523\, B => \dcs[0]\, C => - \dcs_0_i_0_a2_0[1]\, Y => N_3664); - - \r.dstate_RNIFS6E51[1]\ : OR3 - port map(A => \edata_m[6]\, B => \dcramo_m[230]\, C => - \ddatainv_0_1_1_iv_1[6]\, Y => dstate_RNIFS6E51(1)); - - \r.wbinit_RNI2J1A3\ : OR2A - port map(A => wbinit, B => N_506, Y => dwrite_1_sqmuxa); - - \r.stpend_RNI07PA2\ : OR3B - port map(A => lock, B => N_485, C => read_1, Y => - stpend_RNI07PA2); - - \dctrl.mmudci_read_1_1_0_a2_0_0_0\ : NOR2A - port map(A => read_0, B => lock, Y => - mmudci_read_1_1_0_a2_0_0); - - \r.wb.addr_RNO_5[8]\ : OR2B - port map(A => \un1_m0_2[84]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[84]\); - - \r.wb.data1_RNO[6]\ : MX2A - port map(A => N_2104, B => maddress(6), S => req_0_sqmuxa_1, - Y => \data1_1[6]\); - - \r.mmctrl1.ctxp_RNIGTE32[0]\ : OR2B - port map(A => \ctxp[0]\, B => N_3344_i_0_0, Y => - \ctxp_m[0]\); - - \r.dstate_ns_0_0_a2_2[5]\ : NOR3A - port map(A => asi(4), B => asi(0), C => N_490, Y => N_3791); - - \r.dstate_i_2_RNI9SET1_0[8]\ : OR3A - port map(A => maddress_0_2, B => maddress(2), C => - rdatasel_0_sqmuxa_1, Y => rdatav_0_1_sqmuxa); - - \r.stpend_RNISIQ5F1\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_3, B => me_nullify2_1_2, - C => nullify2_0_sqmuxa, Y => vaddr_1_sqmuxa_0_a2_5); - - \r.dstate_i_2_RNI3RM12[8]\ : OR2B - port map(A => un1_m0_2_73, B => miscdata_4_sqmuxa, Y => - \mmudco_m[74]\); - - mmudci_fsread_1_sqmuxa_0_a2_0 : OR2A - port map(A => read_0, B => un30_m_en, Y => - \mmudci_fsread_1_sqmuxa_0_a2_0\); - - \r.dstate_i_RNII68N892_0[8]\ : OR2A - port map(A => tdiagwrite_1_0_0_o2_1, B => \N_121\, Y => - \dstate_i_RNII68N892_0[8]\); - - \r.dstate_i_2_RNISK8N1_28[8]\ : OR2B - port map(A => dataout_0(1), B => rdatasel_1_sqmuxa_1_0, Y - => N_3232); - - \r.dstate_tr16_10_0_i_o2_0_i\ : OR2B - port map(A => N_3586, B => N_595, Y => N_395); - - \r.dstate_i_0_RNIQA6JH92[8]\ : AO1C - port map(A => N_328, B => lock, C => req_2_sqmuxa_1_0, Y - => burst_2_sqmuxa_m8_0_0); - - \dctrl.twrite_14_iv_0_a2_a0_RNO_1\ : NOR3A - port map(A => tdiagwrite_1_0_0_o2_1, B => - vaddr_1_sqmuxa_0_a2_0, C => flush_i, Y => - twrite_14_iv_0_a2_a0_1); - - \r.mmctrl1.ctxp_RNIA69ED[28]\ : NOR3C - port map(A => \ctxp_m[28]\, B => \rdatav_0_1_0_iv_1[30]\, C - => \rdatav_0_1_0_iv_3[30]\, Y => \rdatav_0_1_0_iv_4[30]\); - - \r.flush_0_1_RNI6GU5992\ : OR2B - port map(A => maddress(12), B => \N_329\, Y => N_148); - - \r.flush2_RNIRVRLG\ : NOR3B - port map(A => setrepl_0_sqmuxa_1_m_i_5_2, B => - setrepl_0_sqmuxa_1_m_i_5_1, C => un1_eholdn_2, Y => - setrepl_0_sqmuxa_1_m_i_5_4); - - \r.dstate_RNI0P3L7_2[2]\ : AOI1B - port map(A => diagdata_20, B => \dstate[2]\, C => - \dcramo_m_0[244]\, Y => \rdatav_0_1_0_iv_3[20]\); - - \r.xaddress_RNO[6]\ : MX2 - port map(A => \addr[6]\, B => maddress(6), S => N_486_0, Y - => N_710); - - \r.dstate_RNIVRDN8[1]\ : MX2B - port map(A => maddress_0_2, B => edata2_0_iv(3), S => - edata_0_sqmuxa_i, Y => \edata[3]\); - - \r.cctrl.dcs_RNIELEH[1]\ : NOR2A - port map(A => \cache\, B => bo_d(2), Y => - twrite_11_m_0_a2_0_2); - - \r.cctrl.ics_RNIP4MU1[0]\ : OR2B - port map(A => \ics[0]\, B => rdatav_0_0_sqmuxa, Y => - \ics_m[0]\); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0_RNIV8VH1_0[3]\ : AO1 - port map(A => N_3661, B => N_3660, C => N_679, Y => N_348); - - \r.wb.data2_RNI67OB[16]\ : OR2B - port map(A => \data2[16]\, B => rdatav_012, Y => - \data2_m[16]\); - - \r.wb.data1_RNO[1]\ : MX2A - port map(A => N_2099, B => maddress_0_0, S => - req_0_sqmuxa_1_0, Y => \data1_1[1]\); - - \r.holdn_RNO_7\ : NOR2B - port map(A => N_3615, B => holdns_iv_0_0, Y => - holdns_iv_0_1); - - \r.wb.addr_RNO_0[18]\ : NOR3C - port map(A => N_187, B => \addr_1_1_iv_0_0[18]\, C => N_190, - Y => \addr_1_1_iv_0_2[18]\); - - \v.mmctrl1.ctxp_1_sqmuxa\ : AND2 - port map(A => e_0_sqmuxa_2, B => ctxp_1_sqmuxa_0, Y => - ctxp_1_sqmuxa); - - \r.nomds_RNIO3D071\ : MX2B - port map(A => enaddr, B => N_563, S => N_522, Y => N_162); - - \r.vaddr[23]\ : DFN1E1 - port map(D => maddress(23), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[23]\); - - \r.dstate_i_0_RNILKM24[8]\ : NOR3C - port map(A => \dstate_ns_i_a4_i_0[0]\, B => N_3685, C => - N_3677, Y => \dstate_ns_i_a4_i_2[0]\); - - \r.wb.data2_RNI60132[27]\ : AOI1B - port map(A => dataout_0(23), B => rdatasel_1_sqmuxa_1_0, C - => \data2_m[27]\, Y => \rdatav_0_1_0_iv_0[27]\); - - \r.wb.addr_RNO_5[0]\ : OR2B - port map(A => \un1_m0_2[76]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[76]\); - - \r.xaddress[17]\ : DFN1E1 - port map(D => maddress(17), CLK => lclk_c, E => N_486, Q - => \addr[17]\); - - \r.holdn_RNO_10\ : OR3 - port map(A => dcs_1_i_s_0_o2_0_RNIMMIH9, B => N_576, C => - holdn_RNO_20, Y => d_m6_i_a3_1); - - \r.vaddr_RNII2IC[28]\ : MX2 - port map(A => maddress(28), B => \vaddr[28]\, S => - \dstate_i_1[8]\, Y => \data[28]\); - - \r.dstate_RNIJA4E[6]\ : NOR2A - port map(A => \dstate_i_0[8]\, B => \dstate[6]\, Y => - dstate_17_1); - - \r.wb.addr_RNO_4[14]\ : MX2 - port map(A => \paddress[14]\, B => \addr[14]\, S => N_484_0, - Y => N_554); - - \r.holdn_RNILLEQ\ : NOR2A - port map(A => maddress(0), B => N_3763, Y => N_3785); - - \r.dstate_i[8]\ : DFN1 - port map(D => \dstate_nss_i_0[0]\, CLK => lclk_c, Q => - \dstate_i[8]\); - - \r.cctrl.ics[1]\ : DFN1 - port map(D => N_27, CLK => lclk_c, Q => \ics[1]\); - - \dctrl.0.un1_dci_16_0\ : XNOR2 - port map(A => dataout_0(24), B => maddress(28), Y => - un1_dci_16_i); - - \r.mmctrl1.ctxp_RNI4QJ12[28]\ : OR2B - port map(A => \ctxp[28]\, B => N_3344_i_0_0, Y => - \ctxp_m[28]\); - - \r.cctrl.dcs_RNI58EH[0]\ : NOR2A - port map(A => \dcs[0]\, B => N_496, Y => - \dstate_ns_i_a4_i_a2_16_0[0]\); - - \r.read_RNIQK3U8\ : NOR2B - port map(A => \N_425\, B => hrdata_0_11, Y => \mcdo_m[11]\); - - \r.dstate_i_RNINPT0O92[8]\ : OR2A - port map(A => edata2_iv_i_0(30), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_94); - - \dctrl.v.burst_16_m_RNO\ : NOR2 - port map(A => N_421, B => \addr[2]\, Y => burst_16_m_0); - - \r.wb.data1[3]\ : DFN1E0 - port map(D => N_19, CLK => lclk_c, E => data1_0_sqmuxa, Q - => data(3)); - - \r.hit_RNO\ : AO1 - port map(A => hit_1_iv_0_a2_0_3, B => N_495, C => hit_RNO_2, - Y => hit_1); - - \r.dstate_RNIB977A[1]\ : NOR2B - port map(A => \edata[5]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[5]\); - - \r.flush_0_1_RNI7KU5992\ : OR2B - port map(A => maddress(20), B => \N_329\, Y => N_157); - - \r.xaddress_RNIJH2O2_0[0]\ : NOR2B - port map(A => dataout(14), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[238]\); - - \r.wb.data1_RNO_1[5]\ : NOR2A - port map(A => req_0_sqmuxa_1, B => maddress(5), Y => N_3365); - - \r.wb.addr_RNO[26]\ : AO1B - port map(A => \mmudco_m_0[102]\, B => N_2701, C => - \addr_1_1_iv_2[26]\, Y => \addr_1[26]\); - - \r.wb.data2_RNIOV3M3[3]\ : NOR3C - port map(A => N_3400, B => N_3403, C => N_3401, Y => - \rdatav_0_1_1_iv_i_a2_1[3]\); - - \r.wb.addr_RNO_6[20]\ : MX2 - port map(A => \paddress[20]\, B => \addr[20]\, S => N_484, - Y => N_3842); - - \r.dstate_RNO[5]\ : AOI1B - port map(A => \dstate_ns_0_6[3]\, B => \dstate_ns_0_5[3]\, - C => rst, Y => \dstate_nss[3]\); - - \r.ready_RNIL4492\ : OR2B - port map(A => N_566, B => N_508, Y => burst_0_sqmuxa); - - \dctrl.0.un1_dci_14_0\ : XNOR2 - port map(A => dataout_0(22), B => maddress(26), Y => - un1_dci_14_i); - - \r.wb.addr_RNO_5[18]\ : OR2B - port map(A => un1_m0_2_19, B => addr_1_sqmuxa_0, Y => N_189); - - \r.dstate_i_2_RNI3KVJ1[8]\ : NOR3 - port map(A => N_223, B => N_3091_3, C => N_526, Y => - rdatasel_3_sqmuxa); - - \r.wb.data2_RNO[10]\ : MX2 - port map(A => edata2_0_iv(10), B => hrdata_0_10, S => - \dstate_0[7]\, Y => \data2_1[10]\); - - \r.ready_RNO_7\ : NOR2B - port map(A => asi(1), B => N_608, Y => ready_RNO_7); - - \r.dstate_i_2_RNISK8N1_15[8]\ : OR2B - port map(A => dataout_0(6), B => rdatasel_1_sqmuxa_1, Y => - \dcramo_m[102]\); - - \r.xaddress_RNID252J1[10]\ : NOR3 - port map(A => N_3298, B => N_3297, C => \address_i_0[8]\, Y - => xaddress_RNID252J1(10)); - - \r.wb.addr_RNO_1[14]\ : OR2B - port map(A => maddress(14), B => addr_2_sqmuxa_0, Y => - N_3636); - - \r.dstate_RNII450C[1]\ : MX2 - port map(A => maddress(8), B => edata2_0_iv(8), S => - edata_0_sqmuxa_i, Y => \dstate_RNII450C[1]\); - - \r.dstate_0_RNI1JGE7_6[2]\ : AOI1B - port map(A => diagdata_17, B => \dstate_0[2]\, C => - \dcramo_m_0[241]\, Y => \rdatav_0_1_1_iv_5[17]\); - - \r.wb.addr_RNO_6[22]\ : MX2 - port map(A => \paddress[22]\, B => \addr[22]\, S => N_484_0, - Y => N_3840); - - \r.dstate_RNIBGU46[2]\ : NOR2B - port map(A => dataout(5), B => rdatav_0_6_sqmuxa_3, Y => - N_3338); - - \r.wb.data2[13]\ : DFN1E1 - port map(D => \data2_1[13]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[13]\); - - \r.wb.addr[5]\ : DFN1 - port map(D => \addr_1[5]\, CLK => lclk_c, Q => \address[5]\); - - \r.dstate_RNO_2[6]\ : AOI1B - port map(A => \dstate_ns_0_0_o2_0[1]\, B => N_3746, C => - \e_0\, Y => \dstate_ns_0_0_a2_0[2]\); - - \r.flush_op_RNI1CME892\ : OA1C - port map(A => cctrlwr13, B => N_3790, C => flush_op, Y => - \flush_op_i_0\); - - \r.cctrl.ics_RNO_3[1]\ : NOR2B - port map(A => ifrz, B => \ics[0]\, Y => \ics_0_i_a4_1_0[1]\); - - \r.holdn_RNI9UQO3\ : AO1B - port map(A => dstate_17_2, B => dstate_17_1, C => \hold\, Y - => N_3665_1); - - \r.dstate_i_2_RNIA9PN1[8]\ : NOR2 - port map(A => maddress(3), B => rdatasel_0_sqmuxa_1, Y => - rdatav_0_0_sqmuxa); - - \r.wb.addr_RNO[20]\ : AO1B - port map(A => un1_m0_2_95, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[20]\, Y => \addr_1[20]\); - - \r.dstate_tr22_15_a2_14_1_0\ : NOR2 - port map(A => asi(0), B => asi(1), Y => - dstate_tr22_15_a2_14_1_0); - - \dctrl.0.un1_dci_NE_9\ : XA1A - port map(A => maddress(16), B => dataout_0(12), C => - un1_dci_9_i, Y => un1_dci_NE_9); - - \r.wb.addr_RNO_0[0]\ : AOI1B - port map(A => \address[0]\, B => dstate_19, C => - \addr_1_1_iv_0[0]\, Y => \addr_1_1_iv_1[0]\); - - \r.wb.addr[0]\ : DFN1 - port map(D => \addr_1[0]\, CLK => lclk_c, Q => \address[0]\); - - \r.read_RNIDG9BF\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_21, Y => - \mcdo_m_i[21]\); - - \r.holdn_RNO_12\ : OR3B - port map(A => N_60, B => \dstate[4]\, C => N_580, Y => - holdn_1_sqmuxa); - - \r.wb.data1_RNO[31]\ : MX2A - port map(A => N_2129, B => maddress(31), S => - req_0_sqmuxa_1, Y => \data1_1[31]\); - - \r.vaddr[17]\ : DFN1E1 - port map(D => maddress(17), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[17]\); - - \dctrl.v.wb.addr_1_1_iv_0[10]\ : NAND2 - port map(A => N_3723, B => \addr_1_1_iv_0_3[10]\, Y => - \addr_1[10]\); - - \dctrl.0.un1_dci_5_0_RNID777\ : AND2 - port map(A => un1_dci_5_i, B => N_139_i_i, Y => - un1_dci_NE_3); - - \dctrl.v.burst_16_m_RNILVFJ6\ : NOR3C - port map(A => burst_16_m, B => un116_m_en_m, C => - burst_19_m, Y => burst_1_iv_2_1); - - \r.wb.addr_RNO_0[17]\ : NOR3C - port map(A => N_3640, B => \addr_1_1_iv_0_0[17]\, C => - N_3721, Y => \addr_1_1_iv_0_2[17]\); - - \r.mmctrl1.ctx_0_0[2]\ : DFN1 - port map(D => \ctx_RNIFGBR[2]\, CLK => lclk_c, Q => - \ctx_0[2]\); - - \r.dstate_RNIHILB6_0[7]\ : OR2B - port map(A => dataout_0(31), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[255]\); - - \dctrl.0.un1_dci_15_0\ : XNOR2 - port map(A => dataout_0(23), B => maddress(27), Y => - un1_dci_15_i); - - \r.flush_op\ : DFN1 - port map(D => flush_op_RNO, CLK => lclk_c, Q => flush_op); - - \r.xaddress_RNIQF6M2_1[0]\ : OR2B - port map(A => dataout(26), B => N_2088, Y => - \dcramo_m_i[250]\); - - \r.flush2_RNIHI3F73\ : OR2A - port map(A => hit_1_iv_0_a2_0_0, B => twrite_14, Y => N_182); - - \r.dstate_RNO_1[4]\ : OR3B - port map(A => un1_m0_2_108, B => dstate_tr16_10_0_i_2, C - => lock, Y => N_3494); - - \r.valid_0_RNO_0[7]\ : OR2 - port map(A => N_3286_1, B => N_3246, Y => N_3285); - - \r.xaddress_RNO_0[2]\ : MX2B - port map(A => N_670, B => \addr[2]\, S => \dstate_i[8]\, Y - => N_652_i); - - \r.dstate_i_RNICP4M4[8]\ : MX2 - port map(A => \vmask_0_4[6]\, B => N_2026, S => - \dstate_i[8]\, Y => \vmask_0_5[6]\); - - \r.cache_RNO_4\ : MX2C - port map(A => cache_1_0_0_0, B => un47_m_en, S => N_3836, Y - => cache_1); - - \r.read_RNI5R3ND\ : NOR2B - port map(A => \N_425_0\, B => hrdata_1, Y => \mcdo_m[6]\); - - \dctrl.twrite_14_iv_0_a2_a0_RNIQKKTDU2\ : AO1C - port map(A => N_3248, B => N_3322, C => N_2385, Y => N_298); - - \r.wb.addr_RNO[14]\ : AO1B - port map(A => N_695, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_0_2[14]\, Y => \addr_1[14]\); - - \r.vaddr_RNI36EE[8]\ : MX2 - port map(A => maddress(8), B => \vaddr[8]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[84]\); - - \v.burst_2_sqmuxa_m8_0_a4_0\ : AND2 - port map(A => burst_2_sqmuxa_m3_e, B => - burst_2_sqmuxa_m8_0_a4_0_2, Y => burst_2_sqmuxa_m8_0_a4_0); - - \r.wb.addr_RNO_2[14]\ : AOI1B - port map(A => N_2165_0, B => N_554, C => N_3729, Y => - \addr_1_1_iv_0_0[14]\); - - \r.size_RNI7099[0]\ : OR3B - port map(A => \size_0[1]\, B => \size[0]\, C => read, Y => - N_3747); - - \r.holdn_RNID0UG\ : OR2A - port map(A => N_3748, B => size_1_d0, Y => N_3757); - - \r.dstate_RNI7IF44[4]\ : OR2A - port map(A => burst_19_m_0, B => holdn_2_sqmuxa, Y => - burst_19_m); - - \r.wb.data1_RNO[24]\ : MX2A - port map(A => N_2122, B => maddress(24), S => - req_0_sqmuxa_1_0, Y => \data1_1[24]\); - - \r.wb.addr_RNO_0[24]\ : NOR3C - port map(A => N_3634, B => \addr_1_1_iv_0_0[24]\, C => - N_3739, Y => \addr_1_1_iv_0_2[24]\); - - \r.dstate_RNII69VC[1]\ : AO1 - port map(A => dataout(4), B => \xaddress_RNIQDEG2_0[0]\, C - => \edata_m[4]\, Y => \ddatainv_0_1_1_iv_0[4]\); - - \rdatasel_1_i_a5_0_0_a2_1[7]\ : NOR2 - port map(A => N_505, B => N_459, Y => N_206_1); - - \r.xaddress_RNIQ0B62[3]\ : NOR2 - port map(A => dataout_0(6), B => N_3244_i_0, Y => - \vmask_0_4[6]\); - - \r.stpend_RNIUDDF6_0\ : NOR2B - port map(A => stpend_0_sqmuxa, B => \dstate_RNI5GFM4[5]\, Y - => data1_0_sqmuxa); - - \dctrl.0.un1_dci_2_0_RNISLRJ2\ : OR2B - port map(A => un1_dci_NE_17, B => un1_dci_NE_16, Y => - un1_dci_NE); - - \v.burst_2_sqmuxa_m3_e\ : NAND2 - port map(A => burst_2_sqmuxa_m3_e_RNO, B => G_80_0, Y => - burst_2_sqmuxa_m3_e); - - \r.xaddress_RNIUVU9992[14]\ : OR2B - port map(A => \addr[14]\, B => \N_330\, Y => N_237); - - \r.xaddress[14]\ : DFN1E1 - port map(D => maddress(14), CLK => lclk_c, E => N_486, Q - => \addr[14]\); - - \r.wb.data2_RNI1S032[15]\ : AOI1B - port map(A => \data2[15]\, B => rdatav_012_0, C => N_204, Y - => \rdatav_0_1_0_iv_0_0[15]\); - - \r.dstate_i_2_RNII5MM2[8]\ : OR2B - port map(A => dstate_tr22_15_a2_9_0, B => N_395, Y => - N_3576); - - \r.wb.data1_RNO_0[27]\ : MX2C - port map(A => edata2_iv_i_0(27), B => \data2[27]\, S => - N_3331, Y => N_2125); - - \r.wb.data1_RNO_0[11]\ : MX2C - port map(A => edata2_0_iv(11), B => \data2[11]\, S => - N_3331, Y => N_2109); - - \r.wb.data2_RNIV05V5[7]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_0_0[7]\, B => N_3302, C => - N_3311, Y => \rdatav_0_1_1_iv_0_2[7]\); - - \r.nomds_RNIA0RVJ\ : NOR3B - port map(A => setrepl_0_sqmuxa_1_m_i_5_4, B => - twrite_14_iv_0_o2_a1_1, C => mexc, Y => - twrite_14_iv_0_o2_a1_2); - - \r.wb.addr_RNO_5[17]\ : OR2B - port map(A => un1_m0_2_18, B => addr_1_sqmuxa_0, Y => - N_3722); - - \r.dstate_RNI5ED76_0[1]\ : OR3B - port map(A => data2_0_sqmuxa_1, B => holdn_2_sqmuxa, C => - mexc_0_sqmuxa_0, Y => mexc_0_sqmuxa_0_0); - - \r.vaddr_RNICMHC[25]\ : MX2 - port map(A => maddress(25), B => \vaddr[25]\, S => - \dstate_i_1[8]\, Y => data(25)); - - \r.vaddr[7]\ : DFN1E1 - port map(D => maddress(7), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[7]\); - - \r.dstate_RNI5UPJ2[5]\ : AND2 - port map(A => data2_1_sqmuxa, B => N_3151, Y => - burst_1_sqmuxa_0); - - \r.wb.addr_RNO_1[26]\ : NOR3C - port map(A => \dci_m[34]\, B => \addr_1_1_iv_0[26]\, C => - \addr_m[26]\, Y => \addr_1_1_iv_2[26]\); - - \r.holdn_RNO_25\ : OR3B - port map(A => N_510, B => \dstate_2[7]\, C => N_3588, Y => - N_3614); - - \r.dstate_i_2_RNISK8N1[8]\ : OR2B - port map(A => dataout(34), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[414]\); - - \r.xaddress_RNO[11]\ : MX2 - port map(A => \addr[11]\, B => maddress(11), S => N_486_0, - Y => N_713); - - \r.wb.data1[27]\ : DFN1E0 - port map(D => \data1_1[27]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_15); - - \r.mmctrl1wr_RNIBK68\ : AND2 - port map(A => \addr[8]\, B => mmctrl1wr, Y => - ctxp_1_sqmuxa_0); - - \r.dstate_RNO_1[5]\ : NOR3C - port map(A => N_3028, B => \dstate_ns_0_2_0[3]\, C => - \dstate_ns_0_3[3]\, Y => \dstate_ns_0_5[3]\); - - \r.dstate_i_RNIKNRVF91[8]\ : OR2B - port map(A => N_3835, B => \dstate_i_RNID1NU1[8]\, Y => - N_304); - - \r.dstate_RNIPCRK8[1]\ : MX2B - port map(A => maddress(5), B => edata2_0_iv(5), S => - edata_0_sqmuxa_i_0, Y => \edata[5]\); - - \r.dstate_i_2_RNI1EFJ1[8]\ : OA1C - port map(A => N_206_1, B => N_526, C => rdatav_012_0, Y => - rdatav_0_6_sqmuxa_3_1); - - \r.wb.data2_RNIRB4M3[6]\ : NOR3C - port map(A => \dcramo_m[414]\, B => \data2_m[6]\, C => - \dcramo_m[102]\, Y => \rdatav_0_1_1_iv_1[6]\); - - \r.dstate_2_RNILP1MF[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_1, Y => - \mcdo_m_0[1]\); - - \r.size_RNIDM4B2[0]\ : OR2 - port map(A => data2_0_sqmuxa_1, B => N_421, Y => - un116_m_en_m); - - \r.mmctrl1.ctxp_RNIOTF32[8]\ : OR2B - port map(A => \ctxp[8]\, B => N_3344_i_0, Y => N_167); - - \r.flush_0_1_RNIOMB27S2\ : AO1B - port map(A => maddress(19), B => \N_329\, C => - \newtag_1_0[19]\, Y => flush_0_1_RNIOMB27S2); - - \r.dstate_i_2_RNI3KVJ1_0[8]\ : OR2A - port map(A => N_227, B => N_526, Y => rdatasel_0_sqmuxa_1); - - \un1_r.dstate_25_0_o2_0\ : OR2A - port map(A => asi(2), B => asi(0), Y => N_512); - - \r.xaddress_RNIPQFG1[0]\ : AO1C - port map(A => maddress(1), B => N_3785, C => N_3623, Y => - ddatainv_0_1_sqmuxa); - - \r.read_RNIFPFT31\ : OR3 - port map(A => \mcdo_m[5]\, B => \edata_m_0[5]\, C => - \ddatainv_0_1_1_iv_0[5]\, Y => read_RNIFPFT31); - - \dctrl.vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\ : AO1B - port map(A => N_3654, B => N_3653, C => N_679, Y => - \vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\); - - \r.wb.data1_RNO_0[12]\ : MX2C - port map(A => edata2_0_iv(12), B => \data2[12]\, S => - N_3331_0, Y => N_2110); - - \r.cctrl.ics_RNO[1]\ : NOR3 - port map(A => N_3203, B => N_3204, C => \ics_0_i_0[1]\, Y - => N_27); - - \r.xaddress_RNILHOK61[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[26]\, B => - \mcdo_m_i[26]\, C => \ddatainv_0_1_0_iv_1[26]\, Y => - xaddress_RNILHOK61(1)); - - \r.wb.data1_RNO[21]\ : MX2A - port map(A => N_2119, B => maddress(21), S => - req_0_sqmuxa_1, Y => \data1_1[21]\); - - \r.wb.data2_RNO[18]\ : MX2 - port map(A => edata2_0_iv(18), B => hrdata_0_18, S => - \dstate_0[7]\, Y => \data2_1[18]\); - - \dctrl.v.cctrlwr4_0_a2_0_0_a2_0\ : OR2A - port map(A => asi(0), B => N_519, Y => N_3798); - - \r.flush_RNIRA645\ : NOR3B - port map(A => tdiagwrite_1_0_0_o2_1, B => - twrite_14_iv_0_a2_a1_0, C => flush_i, Y => - twrite_14_iv_0_a2_a1_2); - - \r.xaddress_RNI24RK4[6]\ : MX2C - port map(A => maddress(6), B => \addr[6]\, S => - un1_taddr_1_sqmuxa, Y => N_2233); - - \r.xaddress_RNI1Q9ST1[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[24]\, B => - \mcdo_m_i[24]\, C => \ddatainv_0_1_0_iv_1[24]\, Y => - xaddress_RNI1Q9ST1(1)); - - \r.hit_RNO_1\ : NOR2A - port map(A => hit_1_iv_0_a2_0_2, B => un1_dci_NE, Y => - hit_1_iv_0_a2_0_3); - - \r.xaddress_RNITFTTE[3]\ : MX2C - port map(A => N_2230, B => eaddress_1, S => taddr_2_sqmuxa, - Y => xaddress_RNITFTTE(3)); - - \r.mmctrl1.ctx_0_0_RNIVLMQ5[3]\ : AOI1 - port map(A => \ctx_0[3]\, B => miscdata_2_sqmuxa, C => - \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_i_a2_4[3]\); - - \r.dstate_2_RNIE3VV21[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_i_a4_6[1]\, B => - \ico_m[135]\, C => \mcdo_m_0[1]\, Y => N_3227_i_0); - - \r.dstate_RNI5ED76[1]\ : OR3B - port map(A => data2_0_sqmuxa_1, B => holdn_2_sqmuxa, C => - mexc_0_sqmuxa_0, Y => \dstate_RNI5ED76[1]\); - - \r.xaddress_RNIB6DSTI[19]\ : OA1A - port map(A => edata2_0_iv(19), B => \N_3254_0\, C => N_3875, - Y => \newtag_1_0[19]\); - - \r.xaddress_RNI10232[3]\ : AOI1B - port map(A => N_3808, B => N_3800, C => N_679, Y => - N_3244_i_0); - - \r.wb.data2[15]\ : DFN1E1 - port map(D => \data2_1[15]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[15]\); - - \un1_v.cctrlwr19_2_0_o2_1\ : OR3B - port map(A => asi(2), B => asi(3), C => asi(4), Y => N_533); - - \r.size_RNIQO6E[1]\ : NOR3B - port map(A => N_3749, B => \addr[1]\, C => \size_0[1]\, Y - => N_3768); - - \r.wb.addr_RNO_3[4]\ : OR2B - port map(A => un1_m0_2_5, B => addr_1_sqmuxa, Y => - \mmudco_m[6]\); - - \r.dstate_ns_0_2065_tz_tz\ : NOR2B - port map(A => N_3569_2, B => N_666, Y => N_16887_tz_tz); - - \r.dstate_i_RNIDOO0HI[8]\ : OA1A - port map(A => maddress(22), B => \N_523\, C => - flush_1_sqmuxa, Y => flush_1_i_0); - - \r.mmctrl1.e_RNI1TEJ1\ : NOR3B - port map(A => N_3755, B => e_RNIKN3D, C => - dstate_tr8_2_8_0_a2_1_a2_0, Y => N_2996_8); - - \r.wb.addr_RNO_0[13]\ : NOR3C - port map(A => N_272, B => \addr_1_1_iv_0_0[13]\, C => N_275, - Y => \addr_1_1_iv_0_2[13]\); - - \r.wb.addr_RNO_7[2]\ : OR2A - port map(A => ready, B => size, Y => N_323); - - \r.dstate_RNIV0IM2_0[5]\ : NOR2A - port map(A => N_566, B => dstate_14, Y => req_0_sqmuxa_1); - - \r.dstate_0_RNI1JGE7_0[2]\ : AOI1B - port map(A => diagdata_9, B => \dstate_0[2]\, C => - \dcramo_m_0[233]\, Y => \rdatav_0_1_0_iv_3[9]\); - - \r.xaddress_RNIISBI1[0]\ : OR2B - port map(A => N_3598, B => N_727, Y => ddatainv_0_3_sqmuxa); - - \r.xaddress[27]\ : DFN1E1 - port map(D => maddress(27), CLK => lclk_c, E => N_486, Q - => \addr[27]\); - - \r.wb.data1_RNO_0[30]\ : MX2C - port map(A => edata2_iv_i_0(30), B => \data2[30]\, S => - N_3331, Y => N_2128); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0_RNIO98L1[3]\ : NOR2 - port map(A => dataout_0(7), B => N_44_i_0, Y => - \vmask_0_4[7]\); - - \dctrl.v.cctrlwr12_0_a2\ : OR3A - port map(A => asi(4), B => N_3595, C => N_2938_2, Y => - cctrlwr12); - - \r.nomds_RNIC4SS692\ : OR2A - port map(A => un1_dci_12_0, B => nullify, Y => un1_dci_12); - - \v.mmctrl1.ctxp_1_sqmuxa_0_0\ : AND2 - port map(A => e_0_sqmuxa_2, B => ctxp_1_sqmuxa_0, Y => - ctxp_1_sqmuxa_0_0); - - \r.mmctrl1.e_0_0_RNI3LED1\ : NOR2A - port map(A => N_3755, B => dstate_tr8_5_9_0_a2_0_a2_0, Y - => N_3002_9); - - \r.dstate_RNIVP6I3[6]\ : OR2A - port map(A => N_487, B => N_580, Y => mexc_0_sqmuxa_1); - - \r.dstate_i_2_RNISK8N1_24[8]\ : OR2B - port map(A => dataout_0(16), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[116]\); - - \r.dstate_i_2_RNISK8N1_11[8]\ : OR2B - port map(A => dataout_0(15), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[115]\); - - \r.dstate_RNILC7J1[3]\ : OR2A - port map(A => \dstate[3]\, B => un1_m0_2_0_d0, Y => - dstate_0_sqmuxa); - - \r.dstate_RNI26UQ[1]\ : OR3B - port map(A => edata_0_sqmuxa_1, B => N_3443_i, C => - \dstate[1]\, Y => edata_0_sqmuxa_i_0); - - \r.dlock\ : DFN1E1 - port map(D => lock, CLK => lclk_c, E => N_486_0, Q => dlock); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNI75A73\ : NOR3B - port map(A => N_481, B => asi(3), C => N_608, Y => N_3610); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_20\ : NOR3B - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_11, B => - vaddr_1_sqmuxa_0_a2_4_m1_e_16, C => eaddress_28, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_20); - - \r.mmctrl1.e\ : DFN1 - port map(D => e_0_sqmuxa_RNIQKNL, CLK => lclk_c, Q => \e\); - - \r.dstate_RNII7B5A[1]\ : NOR2B - port map(A => \edata[5]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[5]\); - - \r.wb.data2[7]\ : DFN1E1 - port map(D => \data2_1[7]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[7]\); - - \r.asi_RNIQTPH[2]\ : OR3B - port map(A => \asi_0[3]\, B => \dcs[1]\, C => \asi_0[2]\, Y - => N_3845); - - \r.mmctrl1.ctx_0_0_RNILD4N[1]\ : MX2 - port map(A => \ctx_0[1]\, B => maddress_0_0, S => - ctx_1_sqmuxa, Y => N_2664); - - \r.dstate_i_RNI6E3LA92[8]\ : OR3C - port map(A => \vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\, B => - N_110, C => \N_3254_0\, Y => N_130); - - \r.dstate_i_2_RNI1HQB[8]\ : NOR2 - port map(A => read_1, B => \dstate_i_2[8]\, Y => N_3745); - - \r.wb.read_RNO\ : MX2 - port map(A => read_1, B => read, S => \dstate_i[8]\, Y => - N_419_0); - - \r.wb.addr[8]\ : DFN1 - port map(D => \addr_1[8]\, CLK => lclk_c, Q => \address[8]\); - - \r.wb.addr[2]\ : DFN1 - port map(D => \addr_1[2]\, CLK => lclk_c, Q => \address[2]\); - - \r.dstate_RNO_7[1]\ : OR3 - port map(A => dstate_tr22_15_a2_1, B => - dstate_tr22_15_m8_i_a5_0_0, C => N_3787, Y => - dstate_tr22_15_N_10_i); - - \dctrl.hit_1_i_a2_0_a2_0\ : NOR2A - port map(A => asi(4), B => N_512, Y => N_3780); - - \r.dstate_RNI35VL5[4]\ : OR2B - port map(A => data2_0_sqmuxa_1, B => holdn_2_sqmuxa, Y => - holdn_1_5); - - \r.xaddress_RNIV7L4O[1]\ : AOI1B - port map(A => \edata[11]\, B => ddatainv_0_4_sqmuxa, C => - \edata_m_4_i[3]\, Y => \ddatainv_0_1_0_iv_1[27]\); - - \r.wb.addr_RNO_0[15]\ : OA1 - port map(A => \data[15]\, B => N_2709_i_0, C => - addr_1_sqmuxa_2_0, Y => \mmudco_m_0[91]\); - - \r.read_RNI7G7G41\ : OR3 - port map(A => \mcdo_m[11]\, B => \edata_m_1[3]\, C => - \ddatainv_0_1_1_iv_0[11]\, Y => read_RNI7G7G41); - - \r.dstate_i_RNI0GBDG92[8]\ : OR2A - port map(A => edata2_0_iv(5), B => \N_3254_0\, Y => N_131); - - \r.burst_RNO_5\ : OA1C - port map(A => un1_m0_2_108, B => lock, C => - burst_1_m8_i_o5_0, Y => burst_1_N_7); - - \r.dstate_RNIR2CO3[4]\ : OR2A - port map(A => twrite_14_iv_0_o4_0_o2_0, B => N_580, Y => - \dstate_RNIR2CO3[4]\); - - \r.wb.addr[28]\ : DFN1 - port map(D => \addr_1[28]\, CLK => lclk_c, Q => - \address[28]\); - - \r.wb.addr_RNO_5[13]\ : OR2B - port map(A => N_2887, B => addr_1_sqmuxa, Y => N_273); - - \r.mmctrl1.e_RNI92T4J\ : OR3C - port map(A => N_495, B => \dstate_ns_i_a4_i_a2_3_2[0]\, C - => N_3814, Y => N_3680_i); - - \r.mmctrl1.ctx_RNIAM7T[3]\ : NOR2B - port map(A => rst, B => N_2666, Y => \ctx_RNIAM7T[3]\); - - \r.dstate_0_RNI2DT77_4[2]\ : AND2 - port map(A => \ico_m[162]\, B => \dcramo_m_0[252]\, Y => - \rdatav_0_1_1_iv_5[28]\); - - \r.vaddr[8]\ : DFN1E1 - port map(D => maddress(8), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[8]\); - - \r.dstate_RNO_7[4]\ : OA1A - port map(A => dstate_ns_0_2064_1, B => N_3511, C => N_3181, - Y => \dstate_ns_0_0[4]\); - - \dctrl.0.un1_dci_10_0\ : XNOR2 - port map(A => dataout_0(18), B => maddress(22), Y => - un1_dci_10_i); - - \r.wb.data2_RNO[26]\ : MX2 - port map(A => edata2_iv_i_0(26), B => hrdata_0_26, S => - \dstate_1[7]\, Y => \data2_1[26]\); - - \r.wb.data1[31]\ : DFN1E0 - port map(D => \data1_1[31]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_19); - - \r.dstate_i_0_RNID0P84_1[8]\ : NOR3 - port map(A => un18_m_en, B => \dstate_i_0[8]\, C => N_328, - Y => addr_1_sqmuxa_2_0); - - \r.wb.addr_RNO_1[20]\ : OR2B - port map(A => maddress(20), B => addr_2_sqmuxa_0, Y => - N_3860); - - \r.wb.addr[18]\ : DFN1 - port map(D => \addr_1[18]\, CLK => lclk_c, Q => - \address[18]\); - - \r.wb.data2_RNIQ74M3[5]\ : AOI1B - port map(A => dataout_0(5), B => rdatasel_1_sqmuxa_1_0, C - => \rdatav_0_1_1_iv_i_a2_0[5]\, Y => - \rdatav_0_1_1_iv_i_a2_1[5]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m7_i_a4\ : AO1C - port map(A => eaddress_29, B => - \vaddr_1_sqmuxa_0_a2_4_m1_e_24\, C => un17_casaen_0_0, Y - => vaddr_1_sqmuxa_0_a2_4_m7_i_a4); - - \r.wb.data2_RNIABOB[27]\ : OR2B - port map(A => \data2[27]\, B => rdatav_012_0, Y => - \data2_m[27]\); - - \r.wb.addr_RNO[1]\ : AO1B - port map(A => maddress_0_0, B => N_2164, C => - \addr_1_1_iv_2[1]\, Y => \addr_1[1]\); - - \r.dstate_i_0_RNI15JQ8[8]\ : NOR3 - port map(A => un47_m_en, B => vaddr_1_sqmuxa_0_a2_0, C => - un1_eholdn_2, Y => vaddr_1_sqmuxa_0_a2_1); - - \dctrl.un17_m_en\ : OR2B - port map(A => hold_0, B => enaddr, Y => un17_m_en); - - \r.stpend_RNIB3GJE\ : NOR3C - port map(A => dcs_1_i_s_0_o2_0_RNIAN3E3, B => - vaddr_1_sqmuxa_0_a2_1, C => stpend_RNI07PA2, Y => - vaddr_1_sqmuxa_0_a2_3); - - \r.dstate_tr16_10_0_i_o2_0_i_a2\ : AO1A - port map(A => N_3572, B => N_590, C => asi(3), Y => N_3586); - - \r.mmctrl1.ctx_0_0_RNIQBN6[1]\ : NOR2A - port map(A => \ctx_0[1]\, B => maddress(8), Y => - \rdatav_0_1_0_iv_i_a2_2_0[1]\); - - \r.dstate_RNIL46AH[1]\ : AO1 - port map(A => \edata[11]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[235]\, Y => \ddatainv_0_1_1_iv_0[11]\); - - \r.wb.data2_RNIVR032[13]\ : AOI1B - port map(A => dataout_0(9), B => rdatasel_1_sqmuxa_1_0, C - => \data2_m[13]\, Y => \rdatav_0_1_0_iv_0[13]\); - - \r.xaddress_RNISVU9992[12]\ : OR2B - port map(A => \addr[12]\, B => \N_330\, Y => N_146); - - \r.xaddress_RNI9MB27S2[23]\ : AO1B - port map(A => maddress(23), B => \N_329\, C => - \newtag_1_0[23]\, Y => xaddress_RNI9MB27S2(23)); - - \r.wb.data2_RNO[31]\ : MX2 - port map(A => edata2_iv_i_0(31), B => hrdata_26, S => - \dstate_1[7]\, Y => \data2_1[31]\); - - \r.wb.addr_RNO_1[22]\ : OR2B - port map(A => maddress(22), B => addr_2_sqmuxa_0, Y => - N_3871); - - \r.wb.data1_RNO_0[24]\ : MX2C - port map(A => edata2_iv_i_0(24), B => \data2[24]\, S => - N_3331_0, Y => N_2122); - - \r.dstate_RNIHILB6_5[7]\ : OR2B - port map(A => dataout(19), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[243]\); - - GND_i : GND - port map(Y => \GND\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNIAN3E3\ : OR2A - port map(A => read_1, B => N_102, Y => - dcs_1_i_s_0_o2_0_RNIAN3E3); - - \r.wb.addr_RNO_5[15]\ : MX2 - port map(A => \paddress[15]\, B => \addr[15]\, S => N_484, - Y => N_673); - - \r.mmctrl1.ctxp[18]\ : DFN1E1 - port map(D => maddress(20), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[18]\); - - \r.mmctrl1.ctxp_RNIMKK2V[5]\ : OR3C - port map(A => \rdatav_0_1_1_iv_0_6[7]\, B => - \rdatav_0_1_1_iv_0_5[7]\, C => N_3313, Y => data_0_7); - - \r.cache_RNO_6\ : AO1D - port map(A => \dstate[4]\, B => cache_1_0_a3_0_0, C => - un1_m0_2_33, Y => cache_1_0_0_0); - - \dctrl.v.cctrlwr4_0_a2_1_o2\ : OR3A - port map(A => asi(2), B => asi(4), C => N_490, Y => N_551); - - \r.xaddress[7]\ : DFN1 - port map(D => N_712, CLK => lclk_c, Q => \addr[7]\); - - \r.vaddr_RNIJ5DE[0]\ : MX2 - port map(A => maddress(0), B => \vaddr[0]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[76]\); - - \r.dstate_RNIUEDLD[1]\ : NAND2 - port map(A => ddatainv_0_6_sqmuxa, B => \edata[18]\, Y => - \edata_m_i[18]\); - - \r.dstate_RNIHILB6_6[7]\ : OR2B - port map(A => dataout(18), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[242]\); - - \r.dstate_i_2_RNISK8N1_17[8]\ : OR2B - port map(A => dataout_0(2), B => rdatasel_1_sqmuxa_1, Y => - \dcramo_m[98]\); - - \r.asi[0]\ : DFN1E1 - port map(D => asi(0), CLK => lclk_c, E => N_486_0, Q => - \asi_0[0]\); - - \r.wb.addr[7]\ : DFN1 - port map(D => \addr_1[7]\, CLK => lclk_c, Q => \address[7]\); - - \v.burst_2_sqmuxa_m8_0_a4_0_RNO_0\ : NOR3B - port map(A => fault_pri, B => fault_pro67, C => N_328, Y - => burst_2_sqmuxa_m8_0_a4_0_1); - - \r.mmctrl1.ctxp[6]\ : DFN1E1 - port map(D => maddress(8), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[6]\); - - \r.dstate_i_RNIGJ620T2[8]\ : MX2B - port map(A => edata2_0_iv(4), B => \vmask_0_1_2_a4_0_0[4]\, - S => \N_3254_0\, Y => \vmask_0_1_2_0[4]\); - - \r.mmctrl1.ctx_0_0_RNI91UO[5]\ : NOR2B - port map(A => rst, B => N_2668, Y => \ctx_0_0_RNI91UO[5]\); - - \r.dstate_2_RNI2QG1A[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_4, Y => - \mcdo_m_0[4]\); - - \r.wb.data2[24]\ : DFN1E1 - port map(D => \data2_1[24]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[24]\); - - \r.wb.data1_RNO[16]\ : MX2A - port map(A => N_2114, B => maddress(16), S => - req_0_sqmuxa_1, Y => \data1_1[16]\); - - \r.dstate_i_RNIF4S5B92[8]\ : NOR2 - port map(A => \dstate_i[8]\, B => N_511, Y => - \dstate_i_RNIF4S5B92[8]\); - - \r.paddress[31]\ : DFN1E1 - port map(D => N_317_0, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[31]\); - - \r.wb.addr_RNO_4[1]\ : MX2 - port map(A => \paddress_0[1]\, B => \addr[1]\, S => N_484, - Y => \paddress[1]\); - - \r.dstate_i_2_RNISK8N1_22[8]\ : OR2B - port map(A => dataout_0(20), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[120]\); - - \r.wb.addr[4]\ : DFN1 - port map(D => \addr_1[4]\, CLK => lclk_c, Q => \address[4]\); - - \r.valid_0[2]\ : DFN1E0 - port map(D => \valid_0_1[2]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[2]\); - - \r.xaddress_RNIPQFG1_0[1]\ : OR2B - port map(A => N_3626, B => N_3625, Y => ddatainv_0_2_sqmuxa); - - \r.xaddress_RNIJH2O2_3[0]\ : NOR2B - port map(A => dataout(11), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[235]\); - - \r.xaddress[24]\ : DFN1E1 - port map(D => maddress(24), CLK => lclk_c, E => N_486, Q - => \addr[24]\); - - \r.valid_0[0]\ : DFN1E0 - port map(D => \valid_0_1[0]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[0]\); - - \un1_v.cctrlwr19_2_0_a2_5\ : OR3 - port map(A => asi(4), B => asi(2), C => N_490, Y => N_3765); - - \r.read_RNIA18D\ : OR2 - port map(A => read, B => N_135, Y => N_143); - - \r.dstate_RNI0P3L7_1[2]\ : AOI1B - port map(A => diagdata_22, B => \dstate[2]\, C => - \dcramo_m_0[246]\, Y => \rdatav_0_1_0_iv_4[22]\); - - \r.req_RNO_4\ : OA1A - port map(A => read_1, B => N_102, C => un47_m_en, Y => - \req_0_sqmuxa[0]\); - - \r.flush_0_1_RNICPBQ3D2\ : NOR3C - port map(A => N_3279, B => N_3278, C => \vmask_0_1_i_1[7]\, - Y => N_3239_i_0); - - \r.dstate_i_RNI1O26O92[8]\ : NOR2A - port map(A => edata2_iv_i_0(27), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_91); - - \r.dstate_RNIEOAIH[1]\ : AO1 - port map(A => \edata[15]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[239]\, Y => \ddatainv_0_1_1_iv_0[15]\); - - \r.cache_RNO\ : OR3 - port map(A => N_3674, B => N_3675, C => N_2481, Y => - cache_RNO_0); - - \r.xaddress_RNO[8]\ : MX2 - port map(A => \addr[8]\, B => maddress(8), S => N_486_0, Y - => N_716); - - \r.wb.data2_RNO[14]\ : MX2 - port map(A => edata2_0_iv(14), B => hrdata_0_14, S => - \dstate_1[7]\, Y => \data2_1[14]\); - - \r.wb.data2_RNI46J7[7]\ : OR2B - port map(A => \data2[7]\, B => rdatav_012, Y => N_3314); - - \r.vaddr_RNIVTDE[6]\ : MX2 - port map(A => maddress(6), B => \vaddr[6]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[82]\); - - \r.dstate_RNO[4]\ : AOI1B - port map(A => \dstate_ns_0_3[4]\, B => N_3494, C => rst, Y - => \dstate_nss[4]\); - - \r.wb.data1[7]\ : DFN1E0 - port map(D => \data1_1[7]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(7)); - - \r.nomds_RNIMCHA\ : OR2 - port map(A => \hold\, B => nomds, Y => N_522); - - \r.mmctrl1.e_RNIUU9O\ : OR2A - port map(A => \e\, B => N_526, Y => N_3499); - - \r.mmctrl1.e_RNIN8042\ : AO1B - port map(A => ctx_NE_5, B => ctx_NE_4, C => \e\, Y => N_495); - - \r.dstate_RNICUS5G[1]\ : MX2 - port map(A => maddress(28), B => edata2_iv_i_0(28), S => - edata_0_sqmuxa_i_0, Y => \edata[28]\); - - \r.dstate_i_2_RNIOU7E[8]\ : OR2 - port map(A => asi(2), B => \dstate_i_2[8]\, Y => N_3758); - - \r.xaddress_RNI0L8AO[1]\ : AOI1B - port map(A => \edata[7]\, B => ddatainv_0_0_sqmuxa, C => - \edata_m_0_i[15]\, Y => \ddatainv_0_1_0_iv_1[31]\); - - \r.wb.addr_RNO_2[24]\ : AOI1B - port map(A => N_2165_0, B => N_545, C => N_3740, Y => - \addr_1_1_iv_0_0[24]\); - - \r.wb.data1_RNO_0[26]\ : MX2C - port map(A => edata2_iv_i_0(26), B => \data2[26]\, S => - N_3331, Y => N_2124); - - \r.stpend_RNITKI6C\ : OR2 - port map(A => un1_eholdn_2, B => \un1_dci_5[0]\, Y => - cctrlwr19_1_0); - - \r.cctrl.dcs_RNI25QM7[0]\ : NOR2B - port map(A => \rdatav_0_1_0_iv_1[2]\, B => - \rdatav_0_1_0_iv_2[2]\, Y => \rdatav_0_1_0_iv_3[2]\); - - \r.wb.data1_RNO_2[3]\ : NOR3A - port map(A => edata2_0_iv(3), B => req_0_sqmuxa_1_0, C => - N_3331_0, Y => N_3363); - - \r.wb.addr_RNO_1[21]\ : OR2B - port map(A => maddress(21), B => addr_2_sqmuxa_0, Y => - N_3638); - - \r.cctrl.ics_RNIJFPM9[1]\ : NOR3C - port map(A => N_3232, B => \rdatav_0_1_0_iv_i_a4_1[1]\, C - => \rdatav_0_1_0_iv_i_a4_3[1]\, Y => - \rdatav_0_1_0_iv_i_a4_4[1]\); - - \r.wb.addr_RNO_5[9]\ : OR2B - port map(A => \un1_m0_2[85]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[85]\); - - \r.mmctrl1.e_RNIEMFKMG3\ : AO1B - port map(A => asi(3), B => N_3780, C => N_3810, Y => N_688); - - \r.dstate_RNI5GFM4[5]\ : MX2A - port map(A => N_566, B => N_3331, S => dstate_14, Y => - \dstate_RNI5GFM4[5]\); - - \r.cctrl.dcs_RNO[1]\ : NOR3A - port map(A => rst, B => N_672, C => N_3664, Y => N_51); - - \r.wb.data2[10]\ : DFN1E1 - port map(D => \data2_1[10]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[10]\); - - \r.dstate_RNIMHOIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[0]\, Y => \ddatainv_0_1_0_iv_1[16]\); - - \r.dstate_i_2_RNIU4F1Q92[8]\ : NOR3A - port map(A => setrepl_0_sqmuxa_1_m_i_5_4, B => mexc, C => - N_3790, Y => N_55); - - \r.dstate_RNIT0SK8[1]\ : MX2B - port map(A => maddress(6), B => edata2_0_iv(6), S => - edata_0_sqmuxa_i_0, Y => \edata[6]\); - - \r.wb.addr_RNO_3[26]\ : AOI1B - port map(A => \paddress[26]\, B => N_2165_0, C => - \mmudco_m[28]\, Y => \addr_1_1_iv_0[26]\); - - \dctrl.v.wb.addr_1_1_iv_0_RNO[10]\ : AND2 - port map(A => \addr_1_1_iv_0_2[10]\, B => - \addr_1_1_iv_0_1[10]\, Y => \addr_1_1_iv_0_3[10]\); - - \r.xaddress_RNIVN7I[0]\ : OR3C - port map(A => N_3764, B => \addr[0]\, C => \addr[1]\, Y => - N_727); - - \r.mmctrl1.ctxp_RNIPLJ12[10]\ : OR2B - port map(A => \ctxp[10]\, B => N_3344_i_0, Y => - \ctxp_m[10]\); - - \r.dstate_i_RNIR6KHK92[8]\ : OR2A - port map(A => edata2_0_iv(12), B => \N_3254_0\, Y => - \dci_m[84]\); - - \r.dstate_0_RNIIC256_10[7]\ : NAND2 - port map(A => rdatav_0_6_sqmuxa_0, B => dataout(4), Y => - \dcramo_m_0[228]\); - - \r.mmctrl1wr_RNO\ : NOR2 - port map(A => un19_eholdn, B => N_3790, Y => mmctrl1wr_RNO); - - \r.mmctrl1.ctxp[11]\ : DFN1E1 - port map(D => maddress(13), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[11]\); - - \r.dstate_RNO_17[4]\ : OR2A - port map(A => ready, B => \req\, Y => N_16886_tz_tz); - - \dctrl.twrite_14_iv_0_o2_a0\ : NAND2 - port map(A => un1_addout_13_i, B => twrite_14_iv_0_o2_a0_4, - Y => N_1_28_i); - - \r.wb.data2_RNO[11]\ : MX2 - port map(A => edata2_0_iv(11), B => hrdata_0_11, S => - \dstate[7]\, Y => \data2_1[11]\); - - \r.read_RNIDMGV6\ : NOR2B - port map(A => \N_425\, B => hrdata_0_10, Y => \mcdo_m[10]\); - - \r.faddr[2]\ : DFN1E0 - port map(D => \faddr_1[2]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[2]\); - - \r.xaddress_RNIJH2O2_6[0]\ : NOR2B - port map(A => dataout(8), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[232]\); - - \r.flush_0_1_RNI30N4992\ : NOR3B - port map(A => \dstate_i_RNII68N892_0[8]\, B => N_3833, C - => \un1_p0_2_0[498]\, Y => \N_330\); - - \r.flush_0_1_RNIBKU5992\ : NOR2B - port map(A => maddress(24), B => \N_329\, Y => N_3892); - - \r.faddr[0]\ : DFN1E0 - port map(D => \faddr_1[0]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[0]\); - - \r.xaddress[12]\ : DFN1E1 - port map(D => maddress(12), CLK => lclk_c, E => N_486_0, Q - => \addr[12]\); - - \r.wb.addr_RNO_3[9]\ : OR2B - port map(A => maddress(9), B => addr_2_sqmuxa, Y => - \dci_m[17]\); - - \r.wb.addr_RNO_3[18]\ : OR2B - port map(A => \address[18]\, B => N_514, Y => N_190); - - \r.wb.addr_RNO[24]\ : AO1B - port map(A => N_696, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_0_2[24]\, Y => \addr_1[24]\); - - \r.ready_RNO_6\ : OR3 - port map(A => \dstate_i_2_RNITVLGB92[8]\, B => N_3778, C - => asi(2), Y => N_3697); - - \r.xaddress_RNI44V9992[27]\ : NOR2B - port map(A => \addr[27]\, B => \N_330\, Y => N_3895); - - \r.flush_0_1_RNISQE2E91\ : OA1B - port map(A => twrite_14_iv_0_a2_a0_RNIGON1LK, B => - \dstate_RNIR2CO3[4]\, C => N_184, Y => N_91); - - \r.dstate_0_RNIMIEID[2]\ : NOR3C - port map(A => \ctxp_m[7]\, B => \rdatav_0_1_0_iv_1[9]\, C - => \rdatav_0_1_0_iv_3[9]\, Y => rdatav_0_1_0_iv_4_9); - - \r.dstate_i_0[8]\ : DFN1 - port map(D => \dstate_nss_i_0[0]\, CLK => lclk_c, Q => - \dstate_i_0[8]\); - - \r.dstate_2_RNIGGD211[7]\ : OR2B - port map(A => \rdatav_0_1_0_iv_4[20]\, B => \mcdo_m_0[20]\, - Y => data_0_20); - - \r.xaddress_RNIVVU9992[15]\ : OR2B - port map(A => \addr[15]\, B => \N_330\, Y => N_255); - - \r.vaddr[9]\ : DFN1E1 - port map(D => maddress(9), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[9]\); - - \r.dstate_tr22_15_a2_2_m1_e\ : OR3B - port map(A => fault_pri, B => fault_pro, C => accexc_6, Y - => dstate_tr22_15_a2_2_m1_e); - - \r.dstate_0_RNIKBNPH[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_0_2, Y => - mcdo_m_0_1); - - \r.wb.data1_RNO_0[1]\ : MX2B - port map(A => edata2_0_iv(1), B => \data2[1]\, S => - N_3331_0, Y => N_2099); - - \r.wb.addr_RNO_4[2]\ : OR3B - port map(A => \dstate[7]\, B => N_115, C => burst_0_sqmuxa, - Y => N_316); - - \r.holdn_RNO_5\ : NOR3C - port map(A => holdn_1_sqmuxa, B => holdn_0_1, C => N_3750, - Y => holdn_0_3); - - \r.dstate_i_RNI8TBIK92[8]\ : OR2A - port map(A => edata2_0_iv(16), B => - \dstate_i_RNII68N892_0[8]\, Y => \dci_m[88]\); - - \r.dstate_RNIFMKG5_0[7]\ : NOR2A - port map(A => \dstate_RNIP22L4[7]\, B => N_484_0, Y => - N_3792); - - \rdatasel_1_i_a3_2_0[7]\ : OR2 - port map(A => asi(0), B => asi(4), Y => - \rdatasel_1_i_a3_2_0[7]_net_1\); - - \r.xaddress_RNIAOA4[5]\ : NOR3A - port map(A => flush_0_sqmuxa_0_o3_i_o2_2, B => \addr[5]\, C - => \addr[7]\, Y => flush_0_sqmuxa_0_o3_i_o2_4); - - \r.wb.addr_RNO_2[4]\ : OR2B - port map(A => \address[4]\, B => dstate_19, Y => - \addr_m[4]\); - - \r.holdn_RNO_2\ : AO1B - port map(A => holdns_iv_0_1, B => N_3613, C => holdn_1, Y - => holdn_10); - - \r.dstate_RNIHILB6_2[7]\ : OR2B - port map(A => dataout(22), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[246]\); - - \r.cctrl.dcs_RNIKN0L[0]\ : NOR3B - port map(A => \dcs[0]\, B => read_0, C => lock, Y => - \dstate_ns_i_a4_i_a2_3_0[0]\); - - \r.wb.lock_RNO_4\ : OR3A - port map(A => lock_1_iv_0_a2_1_0, B => N_3331_0, C => - nullify, Y => N_3555); - - \r.dstate_RNIAQNB0A2[7]\ : NOR2A - port map(A => twrite_11_m, B => N_55, Y => N_3246); - - \r.dstate_RNI05S4E[1]\ : OR2B - port map(A => \edata[15]\, B => ddatainv_0_4_sqmuxa, Y => - \edata_m_0_i[15]\); - - \dctrl.un1_eholdn_2_i_i_o2\ : OR2A - port map(A => N_509, B => N_503, Y => un1_eholdn_2); - - \r.vaddr[31]\ : DFN1E1 - port map(D => maddress(31), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[31]\); - - \r.vaddr[12]\ : DFN1E1 - port map(D => maddress(12), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[12]\); - - \r.mmctrl1.ctx_0_0_RNI4S8L[5]\ : MX2 - port map(A => \ctx_0[5]\, B => maddress(5), S => - ctx_1_sqmuxa, Y => N_2668); - - \r.nomds_RNICGJOB\ : AO1 - port map(A => \dstate_ns_i_a4_i_o2_9_2[0]\, B => - mexc_0_sqmuxa_1, C => \dstate_ns_i_a4_i_a2_6_0[0]\, Y => - N_3683_i); - - \r.wb.data2_RNO[22]\ : MX2 - port map(A => edata2_0_iv(22), B => hrdata_0_22, S => - \dstate_0[7]\, Y => \data2_1[22]\); - - \r.paddress[12]\ : DFN1E1 - port map(D => N_2886, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[12]\); - - \r.wb.data1[26]\ : DFN1E0 - port map(D => \data1_1[26]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_14); - - \r.dstate_i_0_RNINTFVC[8]\ : NOR3B - port map(A => burst_3_m_1, B => burst_0_sqmuxa_2, C => - burst_2_sqmuxa_2, Y => burst_3_m_3); - - \r.mmctrl1.ctx[0]\ : DFN1 - port map(D => \ctx_RNIB8BR[0]\, CLK => lclk_c, Q => - \ctx[0]\); - - \r.wb.data2_RNIT9I7[0]\ : OR2B - port map(A => \data2[0]\, B => rdatav_012, Y => - \data2_m[0]\); - - \r.wb.addr_RNO_5[29]\ : MX2 - port map(A => \paddress[29]\, B => \addr[29]\, S => N_484_0, - Y => N_546); - - \r.mmctrl1.e_0_0_RNIMJIR\ : AO1B - port map(A => un1_m_en_2, B => un1_m_en_1, C => \e_0\, Y - => N_484_0); - - \r.dstate_RNIQDJBR[1]\ : AO1 - port map(A => \edata[0]\, B => \size_RNIBHS22[0]\, C => - \mcdo_m[0]\, Y => \ddatainv_0_1_1_iv_1[0]\); - - \r.wb.addr[24]\ : DFN1 - port map(D => \addr_1[24]\, CLK => lclk_c, Q => - \address[24]\); - - \un1_v.cctrlwr19_2_0_a2_4\ : AO1D - port map(A => flush, B => asi(1), C => N_533, Y => N_3770); - - \r.mmctrl1.ctx_0_0_RNIBTOV1[1]\ : OR3B - port map(A => \rdatav_0_1_0_iv_i_a2_2_0[1]\, B => - un30_m_en_0, C => rdatasel_4_sqmuxa, Y => N_3233); - - \r.dstate_RNIFT77A[1]\ : NOR2B - port map(A => \edata[6]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[6]\); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_2[10]\ : OR2B - port map(A => un1_m0_2_11, B => addr_1_sqmuxa_0, Y => - N_3726); - - \r.mmctrl1.ctx_0_0_RNI1MMQ5[5]\ : AOI1 - port map(A => \ctx_0[5]\, B => miscdata_2_sqmuxa, C => - \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_i_a2_4[5]\); - - \r.valid_0_RNO_0[5]\ : AO1 - port map(A => \valid_0_1_1_a4_1_0[5]\, B => - \vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\, C => N_188, Y => - \valid_0_1_1_0[5]\); - - \r.read_RNI2LUJG\ : NOR2B - port map(A => \N_425\, B => hrdata_0_0, Y => \mcdo_m[0]\); - - \r.wb.data2_RNO[3]\ : MX2A - port map(A => edata2_0_iv(3), B => hrdata_0_3, S => - \dstate_1[7]\, Y => N_3347); - - \r.wb.data2_RNI6FOB[30]\ : OR2B - port map(A => \data2[30]\, B => rdatav_012_0, Y => - \data2_m[30]\); - - \r.valid_0_RNIUBMT1[7]\ : AOI1 - port map(A => hit, B => \valid_0[7]\, C => N_44_i_0, Y => - N_2027); - - \r.holdn_RNIRBQ6\ : OR2A - port map(A => \hold\, B => write, Y => N_3443_i); - - \r.wb.addr[14]\ : DFN1 - port map(D => \addr_1[14]\, CLK => lclk_c, Q => - \address[14]\); - - \dctrl.twrite_14_iv_0_o2_a0_RNO_1\ : NOR3B - port map(A => setrepl_0_sqmuxa_1_m_i_5_4, B => - twrite_14_iv_0_o2_a1_0, C => mexc, Y => - twrite_14_iv_0_o2_a0_1); - - \r.dstate_i_2_RNISK8N1_18[8]\ : OR2B - port map(A => dataout_0(0), B => rdatasel_1_sqmuxa_1, Y => - \dcramo_m[96]\); - - \r.wb.addr_RNO_3[30]\ : AOI1B - port map(A => un1_m0_2_31, B => addr_1_sqmuxa_0, C => - \paddress_m[30]\, Y => \addr_1_1_iv_0[30]\); - - \r.flush_0_1\ : DFN1 - port map(D => N_2710_i, CLK => lclk_c, Q => - \un1_p0_2_0[498]\); - - \r.dstate_RNIHILB6_9[7]\ : OR2B - port map(A => dataout(15), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[239]\); - - \r.wb.lock_RNI3VPBB\ : OR2A - port map(A => lock_m_0, B => un59_nbo, Y => lock_m); - - \r.wb.data1_RNO[7]\ : MX2A - port map(A => N_2105, B => maddress(7), S => - req_0_sqmuxa_1_0, Y => \data1_1[7]\); - - \r.read_RNID1UNB\ : NOR2B - port map(A => \N_425\, B => hrdata_0_3, Y => \mcdo_m[3]\); - - \r.wb.data2_RNI27OB[12]\ : OR2B - port map(A => \data2[12]\, B => rdatav_012, Y => - \data2_m[12]\); - - \r.read_RNI3V8BG\ : NOR2B - port map(A => \N_425\, B => hrdata_0_1, Y => \mcdo_m[1]\); - - \r.dstate_i_0_RNI48F4E92[8]\ : NOR3 - port map(A => burst_2_sqmuxa_2, B => read_0, C => - un1_dci_12, Y => req_2_sqmuxa_1_0); - - \r.cctrl.dcs_RNIJNS78H3[0]\ : OR3C - port map(A => N_3818, B => \dstate_ns_i_a4_i_a2_0[0]\, C - => N_688, Y => N_3676); - - \r.cctrl.burst_RNIGLUQ1\ : OR2B - port map(A => \burst_0\, B => rdatav_0_0_sqmuxa, Y => - burst_m); - - \r.xaddress_RNIJH2O2_9[0]\ : NOR2B - port map(A => dataout(0), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[224]\); - - \r.wb.addr_RNO_3[17]\ : OR2B - port map(A => \address[17]\, B => N_514, Y => N_3721); - - \r.dstate_i_RNI7TT2I92[8]\ : NOR3 - port map(A => N_3775, B => N_3745, C => N_556, Y => N_587); - - \r.wb.data1_RNO[12]\ : MX2A - port map(A => N_2110, B => maddress(12), S => - req_0_sqmuxa_1_0, Y => \data1_1[12]\); - - \r.wb.addr_RNO_3[20]\ : OR2B - port map(A => \address[20]\, B => N_514, Y => N_3863); - - \r.dstate_RNIK0O51[1]\ : MX2B - port map(A => maddress(2), B => edata2_0_iv(2), S => - edata_0_sqmuxa_i, Y => \edata[2]\); - - \un1_v.cctrlwr19_2_0_o2_3\ : OR2 - port map(A => flush, B => N_551, Y => N_561); - - \r.mmctrl1.ctx_0_0_RNI7TTO[4]\ : NOR2B - port map(A => rst, B => N_2667, Y => \ctx_0_0_RNI7TTO[4]\); - - \r.xaddress_RNIUJQK4[4]\ : MX2 - port map(A => maddress(4), B => \addr[4]\, S => - un1_taddr_1_sqmuxa, Y => N_3261); - - \r.mmctrl1.e_RNIMP673\ : OR2A - port map(A => N_485, B => un47_m_en, Y => N_328); - - \r.cache_RNIRE2K\ : NOR3C - port map(A => hcache, B => ba, C => cache_0, Y => - twrite_11_m_0_a2_0_0); - - \r.dstate_RNIF6E91[2]\ : OR2B - port map(A => diagdata_1, B => \dstate[2]\, Y => - \ico_m[135]\); - - \r.cctrl.dfrz\ : DFN1E0 - port map(D => maddress(5), CLK => lclk_c, E => \N_523\, Q - => dfrz); - - \r.stpend_RNIJPSU1\ : AO1C - port map(A => \req\, B => ready, C => stpend, Y => N_485); - - \r.xaddress[10]\ : DFN1 - port map(D => N_718, CLK => lclk_c, Q => \addr[10]\); - - \r.wb.addr[30]\ : DFN1 - port map(D => \addr_1[30]\, CLK => lclk_c, Q => - \address[30]\); - - \r.dstate_RNO_2[5]\ : OR3A - port map(A => \req\, B => \dstate_ns_0_8_tz[3]\, C => - N_3514, Y => \dstate_ns_0_7_i[3]\); - - \r.xaddress_RNIQF6M2_11[0]\ : NAND2 - port map(A => \xaddress_RNI1CIE2_0[0]\, B => dataout(18), Y - => \dcramo_m_i[242]\); - - \r.wb.data2[9]\ : DFN1E1 - port map(D => \data2_1[9]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[9]\); - - \r.mmctrl1.ctxp_RNIMLF32[6]\ : OR2B - port map(A => \ctxp[6]\, B => N_3344_i_0, Y => \ctxp_m[6]\); - - \r.wb.addr_RNO_4[24]\ : MX2 - port map(A => \paddress[24]\, B => \addr[24]\, S => N_484_0, - Y => N_545); - - \r.wb.addr_RNO_3[22]\ : OR2B - port map(A => \address[22]\, B => N_514, Y => N_185); - - \r.dstate_RNIKFV3H[1]\ : OR2B - port map(A => \edata[28]\, B => ddatainv_0_6_sqmuxa, Y => - \edata_m_i[28]\); - - \r.dstate_RNIGVSIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[7]\, Y => \ddatainv_0_1_0_iv_1[23]\); - - \r.size_RNI2C3G[0]\ : NOR3A - port map(A => N_3749, B => \size_0[1]\, C => \size[0]\, Y - => N_3764); - - \r.dstate_0_RNIQF2BJ[2]\ : AOI1B - port map(A => diagdata_0, B => \dstate_0[2]\, C => - \rdatav_0_1_0_iv_6[0]\, Y => \rdatav_0_1_0_iv_7[0]\); - - \r.wb.addr_RNO_0[30]\ : OA1 - port map(A => \data[30]\, B => LVL_RNIT69H911(0), C => - addr_1_sqmuxa_2_0, Y => \mmudco_m_0[106]\); - - \r.cctrl.dcs_RNIJJUSO[0]\ : AO1B - port map(A => \dstate_ns_i_a4_i_a2_16_0[0]\, B => N_3815, C - => N_3709, Y => N_467); - - \r.wb.data1_RNO[25]\ : MX2A - port map(A => N_2123, B => maddress(25), S => - req_0_sqmuxa_1, Y => \data1_1[25]\); - - \r.flush_0_1_RNIIH0S4\ : NOR2A - port map(A => flush_i_0, B => \un1_p0_2_0[498]\, Y => - faddr_1_sqmuxa_0); - - \r.dstate_2_RNIP66J9[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_18, Y => - mcdo_m_0_17); - - \r.dstate_1_RNIER442[7]\ : NOR2A - port map(A => \dstate_1[7]\, B => N_585, Y => N_3811); - - \r.dstate_0_RNIRJ8TD[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_23, Y => - \mcdo_m_0[28]\); - - \r.cache_RNO_9\ : NOR2B - port map(A => \dstate[6]\, B => cache_0, Y => - cache_1_0_a3_0_0); - - \r.xaddress[6]\ : DFN1 - port map(D => N_710, CLK => lclk_c, Q => \addr[6]\); - - \r.wb.data2[22]\ : DFN1E1 - port map(D => \data2_1[22]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[22]\); - - \r.wb.data2_RNI17OB[11]\ : OR2B - port map(A => \data2[11]\, B => rdatav_012, Y => - \data2_m[11]\); - - \r.mmctrl1.ctx_0_0_RNI6JTGB[4]\ : AND2 - port map(A => \rdatav_0_1_0_iv_4[4]\, B => \ctx_m[4]\, Y - => \rdatav_0_1_0_iv_5[4]\); - - \r.holdn_RNO_18\ : OR3A - port map(A => N_492, B => \e_0\, C => - \dstate_i_2_RNITVLGB92[8]\, Y => N_3611); - - \r.flush2_RNIPC79F\ : AO1A - port map(A => un6_validrawv, B => N_499, C => N_562, Y => - N_3814); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_19\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_10, B => - eaddress_18, C => eaddress_6, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_19); - - \r.xaddress_RNO_3[2]\ : OR2B - port map(A => \hold\, B => enaddr, Y => N_591); - - \r.xaddress_RNIVDCSTI[18]\ : OA1A - port map(A => edata2_0_iv(18), B => \N_3254_0\, C => N_3850, - Y => \newtag_1_0[18]\); - - \r.mmctrl1.ctxp_RNI3LB66[24]\ : AOI1B - port map(A => \ctxp[24]\, B => N_3344_i_0_0, C => - \rdatav_0_1_0_iv_1[26]\, Y => \rdatav_0_1_0_iv_2[26]\); - - \un1_r.faddr_I_5\ : XOR2 - port map(A => \faddr[0]\, B => \faddr[1]\, Y => I_5_1); - - \r.dstate_tr13_11_11\ : OR2 - port map(A => N_3514, B => ready, Y => N_3041_11); - - \v.burst_2_sqmuxa_m3_e_RNO\ : OR2 - port map(A => M_m, B => un54_fault_pro_m, Y => - burst_2_sqmuxa_m3_e_RNO); - - \un1_v.ready_0_sqmuxa_0_a2_4\ : OR3B - port map(A => asi(4), B => asi(3), C => asi(0), Y => N_3778); - - \r.cache_RNO_1\ : NOR3 - port map(A => N_3788, B => cache_1_0_a2_0_0, C => N_502, Y - => N_3675); - - \r.wb.data1[19]\ : DFN1E0 - port map(D => \data1_1[19]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_0_19); - - \r.dstate_i_RNI6DCIK92[8]\ : OR2A - port map(A => edata2_0_iv(21), B => \N_3254_0\, Y => - \dci_m[93]\); - - \r.dstate_i_0_RNI1GDM[8]\ : MX2 - port map(A => dataout_0(2), B => \vmask_0_5_1_a2_2_0[2]\, S - => \dstate_i_0[8]\, Y => \vmask_0_5_1_0[2]\); - - \r.dstate_RNO_11[4]\ : XNOR2 - port map(A => asi(3), B => asi(0), Y => N_114_i_i_0); - - \r.flush_0_1_RNI8KU5992\ : OR2B - port map(A => maddress(21), B => \N_329\, Y => N_3894); - - \dctrl.v.holdns_iv_0_o2\ : OR2B - port map(A => asi(4), B => N_512, Y => N_489); - - \r.wb.data1_RNO_0[8]\ : MX2 - port map(A => edata2_0_iv(8), B => \data2[8]\, S => N_3331, - Y => N_3260); - - \r.valid_0_RNO_1[7]\ : OR3B - port map(A => hit_1_iv_0_a2_0_0, B => dataout_0(7), C => - twrite_14, Y => N_3283); - - \r.stpend_RNO_0\ : OA1 - port map(A => un47_m_en, B => req16, C => req_2_sqmuxa_1_0, - Y => dstate_5_sqmuxa); - - \un1_r.faddr_I_9\ : XOR2 - port map(A => N_20, B => \faddr[2]\, Y => I_9_1); - - \r.wb.data2_RNI07OB[10]\ : OR2B - port map(A => \data2[10]\, B => rdatav_012, Y => N_3304); - - \r.wb.addr_RNO_5[7]\ : OR2B - port map(A => \address[7]\, B => dstate_19, Y => N_3737); - - \r.wb.addr_RNO[31]\ : AO1B - port map(A => un1_m0_2_106, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_0_2[31]\, Y => \addr_1[31]\); - - \r.xaddress_RNITVU9992[13]\ : OR2B - port map(A => \addr[13]\, B => \N_330\, Y => N_3848); - - \r.paddress[14]\ : DFN1E1 - port map(D => un1_m0_2_15, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[14]\); - - \r.nomds_RNO_0\ : MX2 - port map(A => nomds_1, B => nomds, S => N_3153, Y => N_2596); - - \r.mmctrl1.ctxp[14]\ : DFN1E1 - port map(D => maddress(16), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[14]\); - - \dctrl.mmudci_diag_op_1_0_a2_0\ : NOR2B - port map(A => asi(2), B => un19_eholdn_3, Y => - mmudci_diag_op_1_0_a2_0); - - \r.vaddr[10]\ : DFN1E1 - port map(D => maddress(10), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[10]\); - - \r.mmctrl1.ctxp[28]\ : DFN1E1 - port map(D => maddress(30), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[28]\); - - \r.dstate_RNO_3[5]\ : NOR3C - port map(A => N_3180_i, B => data2_1_sqmuxa, C => N_3035, Y - => \dstate_ns_0_1[3]\); - - \r.vaddr_RNIK6IC[29]\ : MX2 - port map(A => maddress(29), B => \vaddr[29]\, S => - \dstate_i_1[8]\, Y => data(29)); - - \r.wb.data2_RNO[5]\ : MX2A - port map(A => edata2_0_iv(5), B => hrdata_0_d0, S => - \dstate_1[7]\, Y => N_3348); - - \r.wb.data2_RNI3BOB[20]\ : OR2B - port map(A => \data2[20]\, B => rdatav_012, Y => - \data2_m[20]\); - - \dctrl.0.un1_dci_7_0\ : XNOR2 - port map(A => dataout_0(15), B => maddress(19), Y => - un1_dci_7_i); - - \r.wb.addr_RNO_3[31]\ : AOI1B - port map(A => N_2165_0, B => N_544, C => N_3716, Y => - \addr_1_1_iv_0_0[31]\); - - \r.flush_0_1_RNIPTA27S2\ : AO1B - port map(A => maddress(22), B => \N_329\, C => - \newtag_1_0[22]\, Y => flush_0_1_RNIPTA27S2); - - \r.wb.addr_RNO[19]\ : AO1B - port map(A => un1_m0_2_94, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_0_2[19]\, Y => \addr_1[19]\); - - \r.dstate_RNIUR652[5]\ : OR2B - port map(A => \dstate[5]\, B => N_566, Y => - data2_0_sqmuxa_1); - - \r.xaddress[22]\ : DFN1E1 - port map(D => maddress(22), CLK => lclk_c, E => N_486, Q - => \addr[22]\); - - \r.faddr[6]\ : DFN1E0 - port map(D => \faddr_1_i[6]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[6]\); - - \r.wb.data2_RNIVHI7[2]\ : OR2B - port map(A => \data2[2]\, B => rdatav_012, Y => - \data2_m[2]\); - - \r.dstate_i_RNI7SGE8[8]\ : NOR2A - port map(A => \dstate_RNIR2CO3[4]\, B => \vmask_0_5[6]\, Y - => \vmask_0_6[6]\); - - \r.dstate_2_RNIAQTV6[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_22, Y => - mcdo_m_0_21); - - \r.wb.data2[18]\ : DFN1E1 - port map(D => \data2_1[18]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[18]\); - - \r.dstate_RNO_0[3]\ : AO1A - port map(A => N_3790, B => cctrlwr13, C => N_3672, Y => - \dstate_ns[5]\); - - \r.wb.addr_RNO_3[13]\ : OR2B - port map(A => \address[13]\, B => N_514, Y => N_275); - - \r.wb.addr_RNO_3[21]\ : OR2B - port map(A => \address[21]\, B => N_514, Y => N_3718); - - \r.dstate_RNIOGKSE[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_0_21, Y => - \mcdo_m_0[21]\); - - \r.wb.addr_RNO_4[16]\ : OR2B - port map(A => \paddress[16]\, B => \dstate_RNIP22L4[7]\, Y - => \paddress_m[16]\); - - \r.vaddr[3]\ : DFN1E1 - port map(D => maddress(3), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[3]\); - - \un1_v.cctrlwr19_2_0_o2\ : OR2B - port map(A => asi(2), B => N_537, Y => N_481); - - \r.req_RNO_1\ : OR3B - port map(A => req_2_sqmuxa_1_0, B => req16, C => un47_m_en, - Y => req_2_sqmuxa); - - \r.asi[4]\ : DFN1E1 - port map(D => asi(4), CLK => lclk_c, E => N_486_0, Q => - \ctx\); - - \r.dstate_0_RNIIC256_8[7]\ : NAND2 - port map(A => rdatav_0_6_sqmuxa_0, B => dataout_0(30), Y - => \dcramo_m_0[254]\); - - \r.flush_0_1_RNIOHD0NI\ : AOI1B - port map(A => faddr_1_sqmuxa_0, B => flush_1_i_0, C => - flush_0_0, Y => N_2710_i); - - \r.dstate_2_RNIU38NG[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_15, Y => N_202); - - \v.wb.addr_1_sqmuxa_1_0_i2_0_a2\ : NOR2A - port map(A => \dstate_0[7]\, B => burst_0_sqmuxa, Y => - addr_1_sqmuxa_1); - - \r.xaddress_RNIIEFGO[7]\ : MX2C - port map(A => N_2234, B => eaddress_5, S => taddr_2_sqmuxa, - Y => \taddr_7[7]\); - - \r.wb.data2_RNIBBOB[28]\ : OR2B - port map(A => \data2[28]\, B => rdatav_012_0, Y => - \data2_m[28]\); - - \r.ready_RNO\ : OR3C - port map(A => ready_RNO_0, B => ready_0_sqmuxa_0_0, C => - ready_0_sqmuxa_0_2, Y => ready_0_sqmuxa); - - \r.wb.data1_RNO_0[7]\ : MX2B - port map(A => edata2_0_iv(7), B => \data2[7]\, S => - N_3331_0, Y => N_2105); - - \r.wb.addr_RNO_2[9]\ : AOI1B - port map(A => \paddress[9]\, B => \dstate_RNIP22L4[7]\, C - => \mmudco_m[85]\, Y => \addr_1_1_iv_0[9]\); - - \r.mmctrl1.ctxp_RNIK377L[4]\ : NOR3C - port map(A => \ctxp_m[4]\, B => \rdatav_0_1_1_iv_4[6]\, C - => \rdatav_0_1_1_iv_6[6]\, Y => rdatav_0_1_1_iv_7(6)); - - \r.burst_RNO_4\ : AO1D - port map(A => burst_2_sqmuxa_m8_0_0, B => - burst_2_sqmuxa_m8_0_a4_0, C => burst_1_iv_2, Y => - burst_1_m8_i_a5_0); - - \r.holdn_RNINK401\ : OR3B - port map(A => maddress_0_2, B => N_568, C => N_3443_i, Y - => N_3660); - - \r.dstate_tr22_15_a2_11\ : NOR2 - port map(A => N_581_i, B => N_507, Y => N_3583); - - \r.wb.addr_RNO_0[31]\ : AND2 - port map(A => N_3715, B => \addr_1_1_iv_0_1[31]\, Y => - \addr_1_1_iv_0_2[31]\); - - \r.read_RNICKHE91\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[19]\, B => - \mcdo_m_i[19]\, C => \ddatainv_0_1_0_iv_1[19]\, Y => - read_RNICKHE91); - - \r.dstate_RNIACT4D[1]\ : OR2B - port map(A => \edata[9]\, B => ddatainv_0_4_sqmuxa, Y => - \edata_m_0_i[9]\); - - \r.mmctrl1.ctx_0_0_RNIE2JM9[2]\ : AOI1B - port map(A => \ctx_0[2]\, B => miscdata_2_sqmuxa, C => - \rdatav_0_1_0_iv_3[2]\, Y => \rdatav_0_1_0_iv_4[2]\); - - \r.holdn_RNIHCLM\ : OR2 - port map(A => size_0_0, B => N_3757, Y => N_3763); - - \r.cache_RNO_8\ : OR2A - port map(A => N_512, B => N_3788, Y => dstate_25_0_a2_0); - - \r.paddress[22]\ : DFN1E1 - port map(D => un1_m0_2_23, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[22]\); - - \r.wb.addr_RNO_3[15]\ : AOI1B - port map(A => N_2165_0, B => N_673, C => \mmudco_m[17]\, Y - => \addr_1_1_iv_0[15]\); - - \r.cache\ : DFN1 - port map(D => cache_RNO_0, CLK => lclk_c, Q => cache_0); - - \r.paddress[13]\ : DFN1E1 - port map(D => N_2887, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[13]\); - - \r.xaddress[3]\ : DFN1 - port map(D => N_719, CLK => lclk_c, Q => \addr[3]\); - - \r.wb.data2_RNI10132[22]\ : AOI1B - port map(A => \data2[22]\, B => rdatav_012_0, C => - \dcramo_m[118]\, Y => \rdatav_0_1_0_iv_0[22]\); - - \r.wb.addr_RNO_1[16]\ : OR2B - port map(A => maddress(16), B => addr_2_sqmuxa_0, Y => - \dci_m[24]\); - - \r.ready_RNI3M8L2\ : NOR3B - port map(A => \dstate_ns_i_a4_i_o2_11_0[0]\, B => N_72_i, C - => N_496, Y => \dstate_ns_i_a4_i_o2_11_2[0]\); - - \r.dstate_RNO_2[4]\ : NOR3B - port map(A => N_3505_i, B => dstate_tr16_13_0_0_a2_0_3, C - => nullify, Y => dstate_tr16_13_0_0_a2_0_5); - - \r.xaddress_RNIT3V9992[20]\ : OR2B - port map(A => \addr[20]\, B => \N_330\, Y => N_155); - - \r.mexc_RNICCRR3\ : OR2B - port map(A => mexc_1_m_0_a2_3_0, B => mexc_0_sqmuxa_1, Y - => N_175); - - \r.valid_0_RNO_0[1]\ : AO1 - port map(A => \valid_0_1_1_a4_1_0[1]\, B => N_32, C => - N_188, Y => \valid_0_1_1_0[1]\); - - \r.size_RNI29NJ[0]\ : NOR2 - port map(A => N_421, B => un1_m0_2_3, Y => burst_19_m_0); - - \r.wb.addr_RNO_6[29]\ : OR2B - port map(A => N_353, B => addr_1_sqmuxa_0, Y => N_262); - - \r.dstate_tr0_32_0_0_a2_1_2_i\ : OR2B - port map(A => asi(3), B => asi(2), Y => N_459); - - \r.dstate_i_1_RNI30EM[8]\ : MX2C - port map(A => dataout_0(1), B => N_95, S => \dstate_i_1[8]\, - Y => N_111); - - \r.wb.data2_RNI6BOB[23]\ : OR2B - port map(A => \data2[23]\, B => rdatav_012_0, Y => - \data2_m[23]\); - - \r.wb.data1_RNO_0[13]\ : MX2C - port map(A => edata2_0_iv(13), B => \data2[13]\, S => - N_3331_0, Y => N_2111); - - \r.dstate_0[7]\ : DFN1 - port map(D => \dstate_nss[1]\, CLK => lclk_c, Q => - \dstate_0[7]\); - - \r.wb.data1[0]\ : DFN1E0 - port map(D => \data1_1[0]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data(0)); - - \r.wb.data2_RNI32J7[6]\ : OR2B - port map(A => \data2[6]\, B => rdatav_012_0, Y => - \data2_m[6]\); - - \r.vaddr_RNI1EHC[10]\ : MX2 - port map(A => maddress(10), B => \vaddr[10]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[86]\); - - \r.read_RNILU2J8\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_17, Y => - \mcdo_m_i[17]\); - - \r.mmctrl1.e_RNIIRI11\ : AO1B - port map(A => un1_m_en_2, B => un1_m_en_1, C => \e\, Y => - N_484); - - \r.flush2_RNO\ : OR2A - port map(A => rst, B => \un1_p0_2_0[498]\, Y => - lrr_1_sqmuxa); - - \r.xaddress_RNIEHIUT1[1]\ : OR3C - port map(A => \edata_m_4_i[1]\, B => \edata_m_0_i[9]\, C - => \ddatainv_0_1_0_iv_2[25]\, Y => xaddress_RNIEHIUT1(1)); - - \r.mmctrl1.ctxp[21]\ : DFN1E1 - port map(D => maddress(23), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[21]\); - - \r.xaddress[0]\ : DFN1E1 - port map(D => maddress(0), CLK => lclk_c, E => N_486_0, Q - => \addr[0]\); - - \r.wb.data2[6]\ : DFN1E1 - port map(D => \data2_1[6]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[6]\); - - \r.mmctrl1.ctxp_RNIL00LF[1]\ : AOI1B - port map(A => \ctxp[1]\, B => N_3344_i_0_0, C => - \rdatav_0_1_1_iv_i_a2_5[3]\, Y => - \rdatav_0_1_1_iv_i_a2_6[3]\); - - \r.dstate_i_2_RNI0RM12[8]\ : OR2B - port map(A => un1_m0_2_70, B => miscdata_4_sqmuxa, Y => - \mmudco_m[71]\); - - \r.xaddress_RNI20V9992[18]\ : OR2B - port map(A => \addr[18]\, B => \N_330\, Y => N_3850); - - \r.wb.addr_RNO_5[5]\ : OR2B - port map(A => \un1_m0_2[81]\, B => addr_1_sqmuxa_2, Y => - N_289); - - \r.xaddress_RNI9SHE[10]\ : NOR3A - port map(A => ctx_1_sqmuxa_0_a2_0, B => \addr[8]\, C => - \addr[10]\, Y => ctx_1_sqmuxa); - - \r.dstate_RNI15BH[7]\ : NOR2B - port map(A => \dstate[7]\, B => N_508, Y => mexc_1_sqmuxa); - - \r.xaddress[20]\ : DFN1E1 - port map(D => maddress(20), CLK => lclk_c, E => N_486, Q - => \addr[20]\); - - \r.wb.data1_RNO[2]\ : MX2A - port map(A => N_2100, B => maddress(2), S => req_0_sqmuxa_1, - Y => \data1_1[2]\); - - \r.mmctrl1.ctxp_RNIBAR3A[15]\ : NOR3C - port map(A => \mmudco_m[60]\, B => \rdatav_0_1_1_iv_2[17]\, - C => \ctxp_m[15]\, Y => \rdatav_0_1_1_iv_4[17]\); - - \r.wb.addr_RNO_2[16]\ : AOI1B - port map(A => data_RNIKU1T4(16), B => addr_1_sqmuxa_0, C - => \paddress_m[16]\, Y => \addr_1_1_iv_0[16]\); - - \r.wb.addr_RNO_0[26]\ : AOI1B - port map(A => data_1_3_i_a3_6_1, B => LVL_RNIT69H911(0), C - => addr_1_sqmuxa_2_0, Y => \mmudco_m_0[102]\); - - \r.dstate_0_RNIOEF6V[7]\ : OR3C - port map(A => \rdatav_0_1_1_iv_5[28]\, B => - \rdatav_0_1_1_iv_4[28]\, C => \mcdo_m_0[28]\, Y => - data_0_28); - - \r.mmctrl1.ctxp_RNIP9TQF[16]\ : NOR3C - port map(A => \ctxp_m[16]\, B => \rdatav_0_1_0_iv_2[18]\, C - => \rdatav_0_1_0_iv_4[18]\, Y => rdatav_0_1_0_iv_5_14); - - \r.dstate_1_RNI7S4O73[7]\ : NOR3C - port map(A => \dstate_ns_i_a4_i_6[0]\, B => N_3680_i, C => - N_3679, Y => \dstate_ns_i_a4_i_8[0]\); - - \r.xaddress[5]\ : DFN1E1 - port map(D => maddress(5), CLK => lclk_c, E => N_486, Q => - \addr[5]\); - - \dctrl.0.un1_dci_NE_7\ : XA1A - port map(A => maddress(29), B => dataout_0(25), C => - un1_dci_18_i, Y => un1_dci_NE_7); - - \r.read_RNIMGBL1\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_26, Y => - \mcdo_m_i[26]\); - - \r.mmctrl1.ctxp[13]\ : DFN1E1 - port map(D => maddress(15), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[13]\); - - \r.hit\ : DFN1E1 - port map(D => hit_1, CLK => lclk_c, E => N_9, Q => hit); - - \r.wb.data2[23]\ : DFN1E1 - port map(D => \data2_1[23]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[23]\); - - \r.dstate_i_2_RNISK8N1_14[8]\ : OR2B - port map(A => dataout_0(7), B => rdatasel_1_sqmuxa_1, Y => - N_3311); - - \dctrl.mexc_1_m_0_a2_5_0\ : OR2 - port map(A => N_3798, B => N_3091_3, Y => mexc_1_m_0_a2_5_0); - - \r.dstate_i_0_RNIRI691[8]\ : OA1A - port map(A => \dstate_ns_i_a4_i_a2_7_0[0]\, B => N_519, C - => holdn_0_0, Y => \dstate_ns_i_a4_i_0[0]\); - - \r.dlock_RNIKFGT\ : MX2B - port map(A => mmudci_read_1_1_0_a2_0_0, B => - mmudci_read_1_1_0_a2_0, S => N_3443_i, Y => read_3); - - \r.xaddress_RNI388I[3]\ : OR2B - port map(A => \addr[3]\, B => N_3793, Y => N_3800); - - \r.mmctrl1.nf_RNIA3F0I\ : NOR3C - port map(A => nf_m, B => \rdatav_0_1_0_iv_i_a4_4[1]\, C => - \dcramo_m_0[225]\, Y => \rdatav_0_1_0_iv_i_a4_6[1]\); - - \r.dstate_RNIRVS21[2]\ : OR3C - port map(A => \dstate[2]\, B => dataout_1(10), C => - cdwrite_0_sqmuxa_i_0_0, Y => N_3306); - - \r.dstate_i_2_RNIQ7942[8]\ : OR2B - port map(A => un1_m0_2_61, B => miscdata_4_sqmuxa, Y => - \mmudco_m[62]\); - - \r.dstate_tr16_1_4_0_a2_0_a2_0_a2_0_a2\ : OR2A - port map(A => asi(2), B => asi(3), Y => N_3091_3); - - \dctrl.0.un1_dci_2_0_RNIGHMF1\ : NOR3C - port map(A => un1_dci_NE_9, B => un1_dci_NE_8, C => - un1_dci_NE_15, Y => un1_dci_NE_17); - - \r.mmctrl1.ctx_RNIIUJ8[0]\ : XNOR2 - port map(A => dataout(28), B => \ctx[0]\, Y => ctx_0_i); - - \r.vaddr_RNIMMV7[2]\ : MX2 - port map(A => maddress(2), B => \vaddr[2]\, S => - \dstate_i[8]\, Y => \un1_m0_2[78]\); - - \r.wb.addr_RNO[8]\ : AO1B - port map(A => \address[8]\, B => N_514, C => - \addr_1_1_iv_2[8]\, Y => \addr_1[8]\); - - \r.read_RNIRO4K31\ : OR3 - port map(A => \mcdo_m[3]\, B => \edata_m_0[3]\, C => - \ddatainv_0_1_1_iv_0[3]\, Y => read_RNIRO4K31); - - \r.flush_RNIVHBN\ : NOR2A - port map(A => N_132, B => read_0, Y => - tdiagwrite_1_0_0_o2_1_0); - - \r.dstate_RNIT1JBG[1]\ : AOI1B - port map(A => dataout(21), B => \xaddress_RNI1CIE2_0[0]\, C - => \edata_m_i[21]\, Y => \ddatainv_0_1_0_iv_0[21]\); - - \r.dstate_0_RNIEKF0B[2]\ : OR3C - port map(A => dstate_19_4, B => dstate_19_3, C => - addr_0_sqmuxa, Y => dstate_19); - - \r.nomds_RNI4C96_0\ : NOR2A - port map(A => nomds, B => \dstate_i[8]\, Y => rdatav_012_0); - - \r.dstate_RNIHILB6_10[7]\ : OR2B - port map(A => dataout(14), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[238]\); - - \dctrl.0.un1_dci_NE_4\ : XA1A - port map(A => maddress(18), B => dataout_0(14), C => - un1_dci_7_i, Y => un1_dci_NE_4); - - \r.wb.addr_RNO_4[12]\ : OR2B - port map(A => \address[12]\, B => N_514, Y => N_280); - - \r.wb.data2_RNO[8]\ : MX2 - port map(A => edata2_0_iv(8), B => hrdata_0_8, S => - \dstate_1[7]\, Y => N_3270); - - \r.wb.data2_RNO[20]\ : MX2 - port map(A => edata2_0_iv(20), B => N_262_0, S => - \dstate_0[7]\, Y => \data2_1[20]\); - - \r.dstate_i_0_RNID0P84_0[8]\ : NOR3 - port map(A => un18_m_en, B => \dstate_i_0[8]\, C => N_328, - Y => addr_1_sqmuxa_2); - - \r.read_RNIR05CJ\ : NOR2B - port map(A => \N_425\, B => hrdata_0_14, Y => \mcdo_m[14]\); - - \r.dstate_RNIVP6I3_1[6]\ : NOR2A - port map(A => N_487, B => N_506, Y => paddress_1_sqmuxa_0); - - \r.dstate_0_RNI2DT77_1[2]\ : AOI1B - port map(A => diagdata_2, B => \dstate_0[2]\, C => - \dcramo_m_0[226]\, Y => \rdatav_0_1_0_iv_6[2]\); - - \r.wb.data2_RNO[15]\ : MX2 - port map(A => edata2_0_iv(15), B => hrdata_0_15, S => - \dstate_1[7]\, Y => \data2_1[15]\); - - \r.flush_RNIJEN4SI3\ : OAI1 - port map(A => N_349, B => \vmask_0_5[2]\, C => N_296, Y => - flush_RNIJEN4SI3); - - \r.dstate_RNO_7[5]\ : OAI1 - port map(A => N_2996_8, B => \dstate_ns_0_4_tz[3]\, C => - N_29, Y => \dstate_ns_0_3[3]\); - - \r.dstate_i_RNIF52EG92[8]\ : OR2 - port map(A => edata2_0_iv(3), B => - \dstate_i_RNII68N892_0[8]\, Y => N_306); - - \r.dstate_0[2]\ : DFN1 - port map(D => \dstate_nss[6]\, CLK => lclk_c, Q => - \dstate_0[2]\); - - \r.wb.data1[5]\ : DFN1E0 - port map(D => N_21, CLK => lclk_c, E => data1_0_sqmuxa, Q - => data(5)); - - \r.wb.data2_RNI50KU3[1]\ : AOI1B - port map(A => dataout(29), B => rdatasel_3_sqmuxa, C => - \rdatav_0_1_0_iv_i_a4_0[1]\, Y => - \rdatav_0_1_0_iv_i_a4_1[1]\); - - \r.wb.addr_RNO_3[1]\ : OR2B - port map(A => un1_m0_2_2, B => addr_1_sqmuxa, Y => - \mmudco_m[3]\); - - \r.paddress[24]\ : DFN1E1 - port map(D => N_421_0, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[24]\); - - \r.holdn_RNO_24\ : NOR3C - port map(A => N_481, B => holdns_iv_0_a2_2_1, C => N_485, Y - => holdns_iv_0_a2_2_3); - - \r.dstate_RNIOVBIG[1]\ : AO1 - port map(A => \edata[9]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[233]\, Y => \ddatainv_0_1_1_iv_0[9]\); - - \r.dstate_i_2_RNITQRS1_2[8]\ : NOR2B - port map(A => maddress(8), B => N_3321, Y => N_3344_i_0); - - \r.read_RNIQPCQ11\ : OR3 - port map(A => \mcdo_m[7]\, B => \edata_m_0[7]\, C => - \ddatainv_0_1_1_iv_0[7]\, Y => read_RNIQPCQ11); - - \r.trans_op_RNIFVCECQ1\ : NOR2 - port map(A => \trans_op_0\, B => - \mmudci_trans_op_1_sqmuxa_1\, Y => \trans_op\); - - \r.dstate_2_RNIE2QM6[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_12, Y => N_158); - - \r.flush_0_1_RNIBOU5992\ : OR2B - port map(A => maddress(31), B => \N_329\, Y => N_270); - - \r.dstate_RNIJP5O3[3]\ : AO1A - port map(A => \dstate[3]\, B => N_3752, C => un1_m0_2_0_d0, - Y => N_3760); - - \r.dstate_0_RNIIC256_0[7]\ : OR2B - port map(A => dataout(27), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[251]\); - - \r.cctrl.dcs_RNIRJ3SG[0]\ : OR3B - port map(A => N_3710, B => \dstate_ns_i_a4_i_o2_11_2[0]\, C - => N_562, Y => N_3818); - - \r.xaddress[8]\ : DFN1 - port map(D => N_716, CLK => lclk_c, Q => \addr[8]\); - - \r.dstate_RNICU24E[1]\ : OR2B - port map(A => \edata[13]\, B => ddatainv_0_4_sqmuxa, Y => - \edata_m_0_i[13]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_24\ : NOR3C - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_21, B => - vaddr_1_sqmuxa_0_a2_4_m1_e_20, C => - vaddr_1_sqmuxa_0_a2_4_m1_e_22, Y => - \vaddr_1_sqmuxa_0_a2_4_m1_e_24\); - - \r.vaddr[18]\ : DFN1E1 - port map(D => maddress(18), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[18]\); - - \r.wb.addr_RNO[30]\ : AO1B - port map(A => \mmudco_m_0[106]\, B => N_2703_i_0, C => - \addr_1_1_iv_2[30]\, Y => \addr_1[30]\); - - \r.dstate_0_RNI1JGE7_4[2]\ : AOI1B - port map(A => diagdata_12, B => \dstate_0[2]\, C => N_160, - Y => \rdatav_0_1_0_iv_0_3[12]\); - - \r.dlock_RNIF7I8\ : OR2A - port map(A => read, B => dlock, Y => mmudci_read_1_1_0_a2_0); - - \r.wb.addr_RNO_1[1]\ : AOI1B - port map(A => \paddress[1]\, B => N_2165_0, C => - \mmudco_m[77]\, Y => \addr_1_1_iv_0[1]\); - - \r.dstate_RNO_0[6]\ : OR2B - port map(A => un1_m0_2_0_d0, B => \dstate[6]\, Y => N_3671); - - \r.wb.addr_RNO_1[12]\ : NOR3C - port map(A => N_277, B => \addr_1_1_iv_0_0[12]\, C => N_280, - Y => \addr_1_1_iv_0_2[12]\); - - \r.mmctrl1.ctx_0_0_RNIA366[4]\ : XNOR2 - port map(A => dataout(32), B => \ctx_0[4]\, Y => ctx_4_i); - - \r.faddr_RNI4DPMS[4]\ : AO1D - port map(A => eaddress_7, B => N_195, C => N_3291, Y => - \address_i_0[7]\); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_5[10]\ : OR2B - port map(A => \addr[10]\, B => N_3796, Y => N_3725); - - \r.dstate_RNIDOQK8[1]\ : MX2B - port map(A => maddress(4), B => edata2_0_iv(4), S => - edata_0_sqmuxa_i_0, Y => \edata[4]\); - - \r.dstate_i_RNIVTDIK92[8]\ : OR2A - port map(A => edata2_0_iv(23), B => \N_3254_0\, Y => N_3878); - - \r.mmctrl1.pso_RNO\ : NOR2B - port map(A => rst, B => N_2674, Y => pso_RNO); - - \r.wb.data1_RNO[27]\ : MX2A - port map(A => N_2125, B => maddress(27), S => - req_0_sqmuxa_1, Y => \data1_1[27]\); - - \r.dstate_RNO_10[4]\ : NOR2A - port map(A => dstate_tr16_13_0_0_a2_0_0, B => read_0, Y => - dstate_tr16_13_0_0_a2_0_1); - - \r.xaddress_RNI0G5H[0]\ : NOR2A - port map(A => N_3764, B => \addr[0]\, Y => N_3782); - - \r.dstate_RNO_8[1]\ : OR2A - port map(A => dstate_tr22_15_a2_9_0, B => N_3569_2, Y => - N_3569); - - \r.wb.data1_RNO[10]\ : MX2A - port map(A => N_2108, B => maddress(10), S => - req_0_sqmuxa_1_0, Y => \data1_1[10]\); - - \r.wb.data2_RNI2UI7[5]\ : OR2B - port map(A => \data2[5]\, B => rdatav_012, Y => N_3396); - - \r.paddress[2]\ : DFN1E1 - port map(D => un1_m0_2_3, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[2]\); - - \r.dstate_i_2_RNIP3942[8]\ : OR2B - port map(A => un1_m0_2_60, B => miscdata_4_sqmuxa, Y => - \mmudco_m[61]\); - - \r.xaddress_RNI64V9992[29]\ : OR2B - port map(A => \addr[29]\, B => \N_330\, Y => N_258); - - \r.wb.data2[11]\ : DFN1E1 - port map(D => \data2_1[11]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[11]\); - - \r.wb.addr[27]\ : DFN1 - port map(D => \addr_1[27]\, CLK => lclk_c, Q => - \address[27]\); - - \r.dstate_i_RNI0P84892[8]\ : OR2A - port map(A => N_3781, B => un10_m_en, Y => N_3668); - - \r.dstate_RNIUQT5G[1]\ : MX2 - port map(A => maddress(29), B => edata2_iv_i_0(29), S => - edata_0_sqmuxa_i, Y => \edata[29]\); - - \r.xaddress[1]\ : DFN1 - port map(D => N_709, CLK => lclk_c, Q => \addr[1]\); - - \r.valid_0_RNO[6]\ : OA1B - port map(A => hit_1_iv_0_a2_0_0, B => twrite_14, C => - N_2366, Y => \valid_0_1[6]\); - - \r.faddr_RNI7MK691[6]\ : MX2A - port map(A => \taddr_7[11]\, B => \faddr[6]\, S => flush_0, - Y => faddr_RNI7MK691(6)); - - \r.vaddr[16]\ : DFN1E1 - port map(D => maddress(16), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[16]\); - - \r.wb.addr[17]\ : DFN1 - port map(D => \addr_1[17]\, CLK => lclk_c, Q => - \address[17]\); - - \r.dstate_i_2_RNISK8N1_19[8]\ : OR2B - port map(A => dataout(35), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m_0[105]\); - - \r.ready_RNO_5\ : OA1 - port map(A => N_572, B => ready_RNO_7, C => N_481, Y => - ready_0_sqmuxa_0_a2_1_0); - - \r.dstate_i_2_RNISK8N1_12[8]\ : OR2B - port map(A => dataout_0(11), B => rdatasel_1_sqmuxa_1, Y - => N_204); - - \r.wb.addr_RNO_2[1]\ : OR2B - port map(A => \address[1]\, B => dstate_19, Y => - \addr_m[1]\); - - \r.mexc_RNIDIK9\ : NOR2B - port map(A => mexc_0, B => rdatav_012_0, Y => - mexc_1_m_0_a2_3_0); - - \rdatasel_1_i_a3_2[7]\ : NOR3A - port map(A => asi(1), B => asi(3), C => - \rdatasel_1_i_a3_2_0[7]_net_1\, Y => N_2047); - - \r.wb.addr_RNO_0[20]\ : NOR3C - port map(A => N_3860, B => \addr_1_1_iv_0_0[20]\, C => - N_3863, Y => \addr_1_1_iv_0_2[20]\); - - \r.vaddr[19]\ : DFN1E1 - port map(D => maddress(19), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[19]\); - - \r.req_RNI4F042\ : OR2 - port map(A => \req\, B => N_510, Y => N_585); - - \r.read_RNIHTEII\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_24, Y => - \mcdo_m_i[24]\); - - \r.dstate_RNIJ4ON8[6]\ : AOI1B - port map(A => mexc_1_m_0_2000_tz_1, B => mexc_1_m_0_a2_1_0, - C => mexc_0_sqmuxa_1, Y => mexc_1_m_0_2000_0); - - \r.dstate_i_RNI4EBC7[8]\ : OR2B - port map(A => \vmask_0_5[7]\, B => \dstate_RNIR2CO3[4]\, Y - => N_3286_1); - - \r.xaddress_RNI1D927S2[20]\ : OR3C - port map(A => N_156, B => N_155, C => N_157, Y => - xaddress_RNI1D927S2(20)); - - \r.read_RNI75LJ31\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[22]\, B => - \mcdo_m_i[22]\, C => \ddatainv_0_1_0_iv_1[22]\, Y => - read_RNI75LJ31); - - \dctrl.0.genmux.un6_validrawv_3\ : MX2C - port map(A => N_2012, B => N_2013, S => maddress(3), Y => - N_2014); - - \r.wb.lock_RNO_6\ : NOR2B - port map(A => hold_0, B => lock, Y => lock_1_iv_0_a2_1_0); - - \r.wb.data2_RNI4BOB[21]\ : OR2B - port map(A => \data2[21]\, B => rdatav_012, Y => - \data2_m[21]\); - - \r.wb.addr_RNO_4[11]\ : MX2 - port map(A => \paddress[11]\, B => \addr[11]\, S => N_484_0, - Y => \addr_1_1_iv_0_a3_0[11]\); - - \r.mmctrl1.ctx_RNI63MN[0]\ : MX2 - port map(A => \ctx[0]\, B => maddress(0), S => ctx_1_sqmuxa, - Y => N_2663); - - \dctrl.rdatav_0_1_0_iv_i_a2_2_0[1]\ : NOR2A - port map(A => maddress(9), B => maddress(10), Y => - un30_m_en_0); - - \r.xaddress_RNIQF6M2_2[0]\ : OR2B - port map(A => dataout(25), B => N_2088, Y => - \dcramo_m_i[249]\); - - \r.valid_0[3]\ : DFN1E0 - port map(D => \valid_0_1[3]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[3]\); - - \r.dstate_0_RNIO8S3OI[7]\ : AOI1B - port map(A => \dstate_ns_0_0_1[1]\, B => N_3668, C => rst, - Y => \dstate_nss[1]\); - - \r.wb.addr_RNO_2[12]\ : OR2B - port map(A => maddress(12), B => addr_2_sqmuxa, Y => N_277); - - \r.wb.addr_RNO_1[5]\ : AOI1B - port map(A => \addr_1_1_iv_0_a3_0_0[5]\, B => - \dstate_RNIP22L4[7]\, C => N_289, Y => - \addr_1_1_iv_0_0[5]\); - - \r.paddress[23]\ : DFN1E1 - port map(D => N_236_0, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[23]\); - - \dctrl.0.un1_dci_18_0\ : XNOR2 - port map(A => dataout_0(26), B => maddress(30), Y => - un1_dci_18_i); - - \r.xaddress_RNI6JA5A[1]\ : OR2B - port map(A => \edata[4]\, B => ddatainv_0_0_sqmuxa, Y => - \edata_m_4_i[4]\); - - \r.wb.data2[25]\ : DFN1E1 - port map(D => \data2_1[25]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[25]\); - - \r.wb.addr_RNO_0[22]\ : NOR3C - port map(A => N_3871, B => \addr_1_1_iv_0_0[22]\, C => - N_185, Y => \addr_1_1_iv_0_2[22]\); - - \r.mmctrl1.ctx_RNINUJ8[5]\ : XNOR2 - port map(A => dataout(33), B => \ctx[5]\, Y => N_103_i_i); - - \r.holdn_RNO_13\ : NOR3C - port map(A => rst, B => holdn_0_0, C => dstate_0_sqmuxa, Y - => holdn_0_1); - - \r.xaddress_RNIEV5QJ[0]\ : AOI1B - port map(A => dataout_0(28), B => N_2088, C => - \edata_m_i[28]\, Y => \ddatainv_0_1_0_iv_0[28]\); - - \r.mmctrl1.ctx_0_0_RNI34KT[4]\ : NOR3C - port map(A => ctx_4_i, B => ctx_2_i, C => ctx_NE_3, Y => - ctx_NE_5); - - \r.wb.data2_RNIPV0SB[7]\ : NOR3B - port map(A => \rdatav_0_1_1_iv_0_2[7]\, B => \mmudco_m[41]\, - C => \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_0_4[7]\); - - \r.mmctrl1.ctx_0_0_RNIP1QE[1]\ : XA1A - port map(A => \ctx_0[1]\, B => dataout(29), C => ctx_0_i, Y - => ctx_NE_1); - - \r.dstate_i_2_RNITQRS1_0[8]\ : NOR2 - port map(A => rdatasel_4_sqmuxa, B => un30_m_en, Y => - miscdata_3_sqmuxa); - - \r.faddr_RNIHMO9[5]\ : NOR2A - port map(A => \un1_p0_2_0[498]\, B => \faddr[5]\, Y => - N_3295); - - \r.cctrl.ics_RNIQ4MU1[1]\ : OR2B - port map(A => \ics[1]\, B => rdatav_0_0_sqmuxa, Y => N_3231); - - \un1_r.faddr_I_24\ : XOR2 - port map(A => N_9_0, B => \faddr[5]\, Y => I_24_1); - - \r.wb.data2_RNO[28]\ : MX2 - port map(A => edata2_iv_i_0(28), B => hrdata_23, S => - \dstate_0[7]\, Y => \data2_1[28]\); - - \r.mmctrl1.ctxp[24]\ : DFN1E1 - port map(D => maddress(26), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[24]\); - - \r.dstate_RNIK6UF4[0]\ : OA1C - port map(A => N_582, B => N_3665_1, C => \dstate[0]\, Y => - un1_taddr_1_sqmuxa); - - \r.dstate_i_RNIO3TO792[8]\ : NOR3 - port map(A => N_533, B => \N_121\, C => read_0, Y => - un19_m_en_m_2); - - \r.dstate_0_RNIJM7GP[2]\ : OR3C - port map(A => \rdatav_0_1_1_iv_5[17]\, B => - \rdatav_0_1_1_iv_4[17]\, C => \mcdo_m_0[17]\, Y => - data_0_17); - - N_3503_i_i : OR2B - port map(A => asi(1), B => asi(0), Y => N_3595); - - \r.faddr_RNIEHR0O[1]\ : MX2 - port map(A => \taddr_7[6]\, B => \faddr[1]\, S => - \un1_p0_2_0[498]\, Y => faddr_RNIEHR0O(1)); - - \r.wb.addr_RNO_1[11]\ : AOI1B - port map(A => un1_m0_2_12, B => addr_1_sqmuxa_0, C => - \addr_1_1_iv_0_0[11]\, Y => \addr_1_1_iv_0_1[11]\); - - \r.stpend_RNIPT84NG3\ : OA1A - port map(A => un1_m0_2_108, B => lock, C => N_485, Y => - req16); - - \r.dstate_RNIIRS9[2]\ : OR2B - port map(A => diagrdy, B => \dstate[2]\, Y => N_135); - - \dctrl.mexc_1_m_0_a2_1_0\ : AO1C - port map(A => size_0_0, B => size_1_d0, C => N_3253_i, Y - => mexc_1_m_0_a2_1_0); - - \r.valid_0_RNO_1[1]\ : OR2B - port map(A => \dstate_i_1[8]\, B => N_95, Y => - \valid_0_1_1_a4_1_0[1]\); - - \r.xaddress_RNISBQK4[3]\ : MX2C - port map(A => maddress(3), B => \addr[3]\, S => - un1_taddr_1_sqmuxa, Y => N_2230); - - \r.wb.addr_RNO_1[29]\ : AND2 - port map(A => N_264, B => \addr_1_1_iv_0_1[29]\, Y => - \addr_1_1_iv_0_2[29]\); - - \r.read_RNIEKS231\ : OR3 - port map(A => \mcdo_m[12]\, B => \edata_m_1[4]\, C => - \ddatainv_0_1_1_iv_0[12]\, Y => read_RNIEKS231); - - \r.wb.addr_RNO_6[15]\ : OR2B - port map(A => N_351, B => addr_1_sqmuxa, Y => - \mmudco_m[17]\); - - \dctrl.0.genmux.un6_validrawv_7\ : MX2 - port map(A => N_2014, B => N_2017, S => maddress(2), Y => - un6_validrawv); - - \r.wb.data2_RNI9RN44[29]\ : NOR3C - port map(A => \dcramo_m[125]\, B => \data2_m[29]\, C => - \mmudco_m[72]\, Y => \rdatav_0_1_0_iv_1[29]\); - - \r.wb.addr_RNO[29]\ : AO1B - port map(A => \addr_1_1_iv_0_a3_2_0[29]\, B => N_2720, C - => \addr_1_1_iv_0_2[29]\, Y => \addr_1[29]\); - - \r.dstate_RNI86TMJ[1]\ : AOI1B - port map(A => \edata[24]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[248]\, Y => \ddatainv_0_1_0_iv_0[24]\); - - \r.cctrl.dcs_RNI4NCI3[0]\ : OR3A - port map(A => \dstate[4]\, B => \dcs[0]\, C => N_580, Y => - N_3710); - - \r.wb.data1_RNO_0[9]\ : MX2C - port map(A => edata2_0_iv(9), B => \data2[9]\, S => N_3331, - Y => N_2107); - - \r.mmctrl1.ctxp_RNI5QJ12[29]\ : OR2B - port map(A => \ctxp[29]\, B => N_3344_i_0, Y => - \ctxp_m[29]\); - - \r.flush2_RNID91C\ : NOR2 - port map(A => \un1_p0_2_0[498]\, B => flush2, Y => - hit_1_iv_0_a2_0_0); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_3[10]\ : OR2B - port map(A => \un1_m0_2[86]\, B => addr_1_sqmuxa_2, Y => - N_3641); - - \v.burst_2_sqmuxa_m8_0_a4_0_RNO\ : NOR2A - port map(A => burst_2_sqmuxa_m8_0_a4_0_1, B => accexc_6, Y - => burst_2_sqmuxa_m8_0_a4_0_2); - - \r.xaddress_RNIC5A27S2[21]\ : OR3C - port map(A => N_3894, B => N_232, C => \dci_m[93]\, Y => - xaddress_RNIC5A27S2(21)); - - \r.dstate_RNIM2RIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[4]\, Y => \ddatainv_0_1_0_iv_1[20]\); - - \r.wb.data1_RNO_0[10]\ : MX2C - port map(A => edata2_0_iv(10), B => \data2[10]\, S => - N_3331_0, Y => N_2108); - - \r.valid_0_RNO[0]\ : AO1B - port map(A => dataout_0(0), B => N_88, C => N_3377, Y => - \valid_0_1[0]\); - - \r.dstate_0_RNI37JF4[7]\ : AOI1B - port map(A => burst_0_sqmuxa, B => \dstate_0[7]\, C => - addr_3_sqmuxa, Y => dstate_19_4); - - \un1_v.cctrlwr19_2_0_o2_0\ : OR2A - port map(A => cctrlwr19_2_0_o2_0_0, B => N_227, Y => N_494); - - \r.dstate_RNIDJ8UEJ[4]\ : AO1A - port map(A => N_3248, B => mexc, C => \dstate_RNIR2CO3[4]\, - Y => N_3315); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_21\ : NOR3B - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_13, B => - vaddr_1_sqmuxa_0_a2_4_m1_e_12, C => eaddress_13, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_21); - - \r.wb.data2_RNI1QI7[4]\ : OR2B - port map(A => \data2[4]\, B => rdatav_012_0, Y => - \data2_m[4]\); - - \r.dstate_RNIEARL2[2]\ : NOR2A - port map(A => N_2042, B => \dstate[2]\, Y => - rdatav_0_6_sqmuxa_3_0); - - \r.wb.addr_RNO_0[8]\ : NOR3C - port map(A => \mmudco_m[10]\, B => \addr_1_1_iv_0[8]\, C - => \dci_m[16]\, Y => \addr_1_1_iv_2[8]\); - - \r.read_RNIG3IS2\ : OR3B - port map(A => N_143, B => N_84, C => N_522, Y => N_178); - - \r.wb.data1_RNO[18]\ : MX2A - port map(A => N_2116, B => maddress(18), S => - req_0_sqmuxa_1_0, Y => \data1_1[18]\); - - \r.flush_0_1_RNIAOU5992\ : OR2B - port map(A => maddress(30), B => \N_329\, Y => N_267); - - \r.mmctrl1.ctxp_RNINPF32[7]\ : OR2B - port map(A => \ctxp[7]\, B => N_3344_i_0, Y => \ctxp_m[7]\); - - \r.mmctrl1.ctxp_RNIORPUB[14]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_2[16]\, B => \mmudco_m[59]\, - C => \ctxp_m[14]\, Y => \rdatav_0_1_1_iv_4[16]\); - - \r.dstate_RNO_3[6]\ : NOR3B - port map(A => N_481, B => N_549, C => N_495, Y => - \dstate_ns_0_0_a2_0_1[2]\); - - \r.wb.data2_RNI23SU1[9]\ : NOR2B - port map(A => \data2_m[9]\, B => \dcramo_m_0[105]\, Y => - \rdatav_0_1_0_iv_0[9]\); - - \r.wb.data2[8]\ : DFN1E1 - port map(D => N_3270, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[8]\); - - \r.wb.data1_RNO[0]\ : MX2A - port map(A => N_2098, B => maddress(0), S => req_0_sqmuxa_1, - Y => \data1_1[0]\); - - \r.dstate_RNI1JGE7_3[2]\ : AOI1B - port map(A => dataout(7), B => rdatav_0_6_sqmuxa_0, C => - N_3312, Y => \rdatav_0_1_1_iv_0_6[7]\); - - \r.wb.data1_RNO_0[4]\ : MX2B - port map(A => edata2_0_iv(4), B => \data2[4]\, S => N_3331, - Y => N_2102); - - \r.dstate_0_RNI2DT77_5[2]\ : AND2 - port map(A => \ico_m[164]\, B => \dcramo_m_0[254]\, Y => - \rdatav_0_1_0_iv_3[30]\); - - \r.wb.data2_RNI0MI7[3]\ : OR2B - port map(A => \data2[3]\, B => rdatav_012, Y => N_3403); - - \dctrl.hit_1_i_a2_0_a2\ : OR2A - port map(A => N_3780, B => N_490, Y => un10_m_en); - - \r.wb.data2_RNIJ45I3[10]\ : NOR3C - port map(A => N_3306, B => N_3304, C => N_167, Y => - \rdatav_0_1_0_iv_0_1[10]\); - - \r.stpend_RNIPTTO1\ : OR2B - port map(A => ready, B => stpend, Y => stpend_0_sqmuxa); - - \r.dstate_i_RNIASSRO92[8]\ : MX2A - port map(A => edata2_0_iv(6), B => \vmask_0_6[6]\, S => - \dstate_i_RNII68N892_0[8]\, Y => N_2385); - - \r.wb.size[1]\ : DFN1E0 - port map(D => N_654, CLK => lclk_c, E => - \dstate_RNI5GFM4[5]\, Q => \size_1[1]\); - - \r.wb.addr_RNO_2[11]\ : OR2B - port map(A => \address[11]\, B => N_514, Y => N_285); - - \r.dstate_0_RNIIC256_2[7]\ : OR2B - port map(A => dataout(24), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[248]\); - - \r.wb.addr_RNO_0[21]\ : NOR3C - port map(A => N_3638, B => \addr_1_1_iv_0_0[21]\, C => - N_3718, Y => \addr_1_1_iv_0_2[21]\); - - \r.flush_0_1_RNI30N4992_0\ : NOR3A - port map(A => \dstate_i_RNII68N892_0[8]\, B => - \un1_p0_2_0[498]\, C => N_3833, Y => \N_329\); - - \dctrl.un1_r.cctrl.dcs_1_i_a2_0_0_a2\ : OR2 - port map(A => asi(0), B => N_519, Y => N_223); - - \r.wb.addr_RNO_5[28]\ : MX2 - port map(A => \paddress[28]\, B => \addr[28]\, S => N_484_0, - Y => N_3839); - - \r.size_RNI1K5H[0]\ : OR2B - port map(A => \size[0]\, B => N_3805, Y => N_3599); - - \r.dstate_RNO_3[0]\ : NOR2B - port map(A => hit, B => \dstate[4]\, Y => - \dstate_ns_0_0_a2_0_1[8]\); - - \r.wb.data2_RNO[2]\ : MX2A - port map(A => edata2_0_iv(2), B => hrdata_0_2, S => - \dstate[7]\, Y => \data2_1[2]\); - - \r.dstate_RNI7LSK8[1]\ : MX2B - port map(A => maddress(7), B => edata2_0_iv(7), S => - edata_0_sqmuxa_i, Y => \edata[7]\); - - \r.dstate_0_RNIPG8A6[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_0_10, Y => N_3305); - - \r.wb.data2_RNIOL4H9[4]\ : NOR3C - port map(A => \dcramo_m[100]\, B => \rdatav_0_1_0_iv_1[4]\, - C => \rdatav_0_1_0_iv_3[4]\, Y => \rdatav_0_1_0_iv_4[4]\); - - \r.wb.addr_RNO_4[9]\ : MX2 - port map(A => \paddress_0[9]\, B => \addr[9]\, S => N_484, - Y => \paddress[9]\); - - \r.dstate_RNI0P3L7_0[2]\ : AOI1B - port map(A => diagdata_18, B => \dstate[2]\, C => - \dcramo_m_0[242]\, Y => \rdatav_0_1_0_iv_4[18]\); - - \dctrl.0.un1_dci_5_0_RNIKH8G\ : NOR3C - port map(A => un1_dci_15_i, B => un1_dci_14_i, C => - un1_dci_NE_3, Y => un1_dci_NE_11); - - \r.wb.addr_RNO_2[5]\ : OR2B - port map(A => \address[5]\, B => dstate_19, Y => N_290); - - \r.xaddress_RNI2052[4]\ : NOR2 - port map(A => \addr[4]\, B => \addr[2]\, Y => - flush_0_sqmuxa_0_o3_i_o2_2); - - \r.size_RNIFQT5[0]\ : OR2B - port map(A => \size_0[1]\, B => \size[0]\, Y => N_421); - - \un1_v.holdn_3_sqmuxa_0_0_a2_3\ : OR2B - port map(A => asi(1), B => N_481, Y => N_3742); - - \r.wb.addr_RNO_2[26]\ : OR2B - port map(A => maddress(26), B => addr_2_sqmuxa, Y => - \dci_m[34]\); - - \r.dstate_RNO_9[5]\ : OR3A - port map(A => N_2996_8, B => N_3511, C => ready, Y => - N_3035); - - \r.flush_RNINJ2O3\ : NOR3C - port map(A => mexc_1_m_0_a2_0, B => mexc_1_m_0_a2_0_1, C - => mexc_1_m_0_a2_5_0, Y => mexc_1_m_0_2000_tz_1); - - \r.ready_RNIQ1GU1\ : OR2A - port map(A => N_72_i, B => ready_0, Y => N_566); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNI6AN51\ : OR3C - port map(A => N_481, B => N_549, C => N_502, Y => N_3746); - - \r.xaddress_RNO[2]\ : OR3B - port map(A => N_652_i, B => N_3698, C => N_84, Y => - \xaddress_1[2]\); - - \r.wb.data1[14]\ : DFN1E0 - port map(D => \data1_1[14]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_2); - - \dctrl.v.burst_16_m\ : NAND2 - port map(A => addr_1_sqmuxa_1, B => burst_16_m_0, Y => - burst_16_m); - - \r.dstate_RNI3HNSH[7]\ : MX2C - port map(A => N_3338, B => hrdata_0_d0, S => \dstate[7]\, Y - => N_3341); - - \r.dstate_i_2_RNILJ842[8]\ : OR2B - port map(A => un1_m0_2_56, B => miscdata_4_sqmuxa, Y => - \mmudco_m[57]\); - - \r.dstate_RNI0Q09A[1]\ : NOR2B - port map(A => \edata[1]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[1]\); - - \r.asi_RNIKJBG[1]\ : NOR3A - port map(A => \ctx\, B => \asi_0[1]\, C => \asi_0[0]\, Y - => un1_m_en_2); - - \r.wb.addr_RNO_1[8]\ : OR2B - port map(A => un1_m0_2_9, B => addr_1_sqmuxa, Y => - \mmudco_m[10]\); - - \r.wb.addr[20]\ : DFN1 - port map(D => \addr_1[20]\, CLK => lclk_c, Q => - \address[20]\); - - \r.dstate_0_RNIPI7EK[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_0_3[12]\, B => - \rdatav_0_1_0_iv_0_2[12]\, C => N_158, Y => data_0_12); - - \dctrl.vmaskraw_1_i_o2_i_o2_0[1]\ : AO1D - port map(A => read_1, B => N_507, C => maddress(2), Y => - N_568); - - \r.dstate_i_2_RNITQRS1_4[8]\ : NOR2A - port map(A => N_3321, B => maddress(8), Y => - miscdata_0_sqmuxa); - - N_68_i_i_o2 : OR2B - port map(A => asi(2), B => asi(1), Y => N_590); - - \r.dstate_RNI26UQ_0[1]\ : OR3B - port map(A => edata_0_sqmuxa_1, B => N_3443_i, C => - \dstate[1]\, Y => edata_0_sqmuxa_i); - - \r.dstate_2_RNISOJVV[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[25]\, B => - \rdatav_0_1_0_iv_2[25]\, C => \mcdo_m_0[25]\, Y => - data_0_25); - - \r.nomds_RNIRCHA\ : OR2A - port map(A => hold_0, B => nomds, Y => N_496); - - \r.wb.addr[10]\ : DFN1 - port map(D => \addr_1[10]\, CLK => lclk_c, Q => - \address[10]\); - - \r.dstate_tr0_32_0_0_a3_0_o2\ : OR2A - port map(A => asi(4), B => asi(1), Y => N_519); - - \r.nomds_RNIS8RHB\ : OR3B - port map(A => mexc_0_sqmuxa_1, B => - \dstate_ns_i_a4_i_o2_9_2[0]\, C => N_496, Y => N_3709); - - \r.mmctrl1.ctx[6]\ : DFN1 - port map(D => \ctx_RNIN0CR[6]\, CLK => lclk_c, Q => - \ctx[6]\); - - \r.dstate_RNI7O47A[1]\ : NOR2B - port map(A => \edata[1]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[1]\); - - \r.wb.addr_RNO[6]\ : OR3C - port map(A => \addr_1_1_iv_0_2[6]\, B => - \addr_1_1_iv_0_1[6]\, C => N_3627, Y => \addr_1[6]\); - - \r.xaddress_RNIMRB5A[1]\ : OR2B - port map(A => \edata[6]\, B => ddatainv_0_0_sqmuxa, Y => - \edata_m_4_i[6]\); - - \r.wb.data2_RNIUIRU1[5]\ : AOI1B - port map(A => dataout(33), B => rdatasel_3_sqmuxa, C => - N_3396, Y => \rdatav_0_1_1_iv_i_a2_0[5]\); - - \r.xaddress_RNI5SAJ[4]\ : NOR2 - port map(A => \addr[4]\, B => N_3800, Y => N_3657); - - \r.mmctrl1.ctxp[23]\ : DFN1E1 - port map(D => maddress(25), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[23]\); - - \r.wb.data2_RNILKUT5[17]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_0[17]\, B => - rdatav_0_2_sqmuxa, C => \dcramo_m[113]\, Y => - \rdatav_0_1_1_iv_2[17]\); - - \r.dstate_RNO_0[1]\ : AOI1B - port map(A => N_3545, B => N_3089_7, C => dstate_tr22_1, Y - => dstate_tr22_2); - - \r.xaddress_RNITMH17S2[12]\ : OR3C - port map(A => N_148, B => N_146, C => \dci_m[84]\, Y => - xaddress_RNITMH17S2(12)); - - \r.dstate_RNIC3BVC[1]\ : AO1 - port map(A => \edata[7]\, B => ddatainv_0_3_sqmuxa, C => - \dcramo_m[231]\, Y => \ddatainv_0_1_1_iv_0[7]\); - - \r.wb.data2_RNO[17]\ : MX2 - port map(A => edata2_0_iv(17), B => hrdata_0_17, S => - \dstate_1[7]\, Y => \data2_1[17]\); - - \r.mmctrl1.ctx_RNIKUJ8[2]\ : XNOR2 - port map(A => dataout(30), B => \ctx[2]\, Y => ctx_2_i); - - \r.faddr[1]\ : DFN1E0 - port map(D => \faddr_1[1]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[1]\); - - \r.faddr_RNIP7K31[6]\ : OA1 - port map(A => I_31_1, B => flush_0_sqmuxa_0, C => rst, Y - => flush_0_0); - - \r.dstate_RNO_3[4]\ : NOR3C - port map(A => \dstate_RNO_6[4]\, B => \dstate_ns_0_0[4]\, C - => \dstate_RNO_8[4]\, Y => \dstate_ns_0_2[4]\); - - \r.valid_0[4]\ : DFN1E0 - port map(D => \valid_0_1[4]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[4]\); - - \r.mmctrl1.ctxp_RNISLJ12[13]\ : OR2B - port map(A => \ctxp[13]\, B => N_3344_i_0, Y => - \ctxp_m[13]\); - - \r.dstate_2_RNI75818[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_16, Y => - \mcdo_m_0[16]\); - - \r.wb.data2_RNI8BOB[25]\ : OR2B - port map(A => \data2[25]\, B => rdatav_012, Y => - \data2_m[25]\); - - \r.valid_0_RNIT2NB[5]\ : NOR2B - port map(A => \valid_0[5]\, B => hit, Y => N_96); - - \r.xaddress_RNIGOTFII[26]\ : AO1 - port map(A => \addr[26]\, B => \N_330\, C => N_245, Y => - newtag_1_0_8); - - \r.wb.addr_RNO_5[27]\ : OR2B - port map(A => \dstate_RNIP22L4[7]\, B => N_674, Y => N_249); - - \r.wb.addr[22]\ : DFN1 - port map(D => \addr_1[22]\, CLK => lclk_c, Q => - \address[22]\); - - \r.flush_RNI1J929\ : NOR3A - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - maddress(8), Y => N_3289); - - \r.dstate_RNI59OG3[4]\ : OR2B - port map(A => \dstate[4]\, B => dwrite_1_sqmuxa, Y => - data2_0_sqmuxa); - - \r.wb.data2[20]\ : DFN1E1 - port map(D => \data2_1[20]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[20]\); - - \r.mmctrl1.ctxp_RNIKDF32[4]\ : OR2B - port map(A => \ctxp[4]\, B => N_3344_i_0_0, Y => - \ctxp_m[4]\); - - \r.faddr_RNO[3]\ : NOR3C - port map(A => rst, B => flush_0, C => I_13_5, Y => - \faddr_1[3]\); - - \r.dstate_tr8_9_10_i_o2_i_a2_i_o2\ : OR2A - port map(A => N_549, B => N_537, Y => N_666); - - \r.dstate_RNO_4[1]\ : OAI1 - port map(A => N_3787, B => dstate_tr22_15_a2_4_1, C => - e_0_0_RNIIAUC4Q1, Y => N_3546); - - \r.mmctrl1.e_RNI30A81\ : OR2B - port map(A => \e\, B => un10_m_en, Y => un47_m_en); - - \r.wb.data2_RNO[24]\ : MX2 - port map(A => edata2_iv_i_0(24), B => hrdata_0_24, S => - \dstate_1[7]\, Y => \data2_1[24]\); - - \r.wb.data2[17]\ : DFN1E1 - port map(D => \data2_1[17]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[17]\); - - \r.wb.addr[12]\ : DFN1 - port map(D => \addr_1[12]\, CLK => lclk_c, Q => - \address[12]\); - - \r.read_RNI8HVEI\ : NOR2B - port map(A => \N_425\, B => hrdata_0_2, Y => \mcdo_m[2]\); - - \dctrl.rdatav_0_1_0_iv[31]\ : NAND2 - port map(A => \mcdo_m_0[31]\, B => \rdatav_0_1_0_iv_4[31]\, - Y => data_0_31); - - \dctrl.0.un1_dci_NE_8\ : XA1A - port map(A => maddress(31), B => dataout_0(27), C => - N_149_i_i, Y => un1_dci_NE_8); - - \r.wb.addr_RNO_0[14]\ : NOR3C - port map(A => N_3636, B => \addr_1_1_iv_0_0[14]\, C => - N_3728, Y => \addr_1_1_iv_0_2[14]\); - - \r.flush_RNICQGM51\ : NOR3A - port map(A => twrite_14_iv_0_a2_a1_2, B => me_nullify2_1_2, - C => nullify2_0_sqmuxa, Y => flush_RNICQGM51); - - \r.dstate_RNIGI4QJ[1]\ : AOI1B - port map(A => \edata[30]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[254]\, Y => \ddatainv_0_1_0_iv_0[30]\); - - \r.read_RNI0IQ7R\ : OR3 - port map(A => \mcdo_m[2]\, B => \edata_m_0[2]\, C => - \ddatainv_0_1_1_iv_0[2]\, Y => read_RNI0IQ7R); - - \r.xaddress_RNI00V9992[16]\ : OR2B - port map(A => \addr[16]\, B => \N_330\, Y => N_240); - - \r.cctrl.ifrz_RNITGHR1\ : OR2B - port map(A => ifrz, B => rdatav_0_0_sqmuxa, Y => ifrz_m); - - \r.dstate_0_RNI1JGE7[2]\ : AOI1B - port map(A => diagdata_19, B => \dstate_0[2]\, C => - \dcramo_m_0[243]\, Y => \rdatav_0_1_0_iv_4[19]\); - - \r.wb.data1_RNO[23]\ : MX2A - port map(A => N_2121, B => maddress(23), S => - req_0_sqmuxa_1_0, Y => \data1_1[23]\); - - \r.wb.data2_RNI30132[24]\ : NOR2B - port map(A => \data2_m[24]\, B => \dcramo_m[120]\, Y => - \rdatav_0_1_0_iv_0[24]\); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0_RNO[3]\ : AND2 - port map(A => N_3443_i, B => \addr[3]\, Y => - \vmaskraw_1_i_o2_i_a3_0_a2_0_0[3]\); - - \r.xaddress_RNI1I3MQ1[0]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[28]\, B => - \mcdo_m_i[28]\, C => \ddatainv_0_1_0_iv_1[28]\, Y => - xaddress_RNI1I3MQ1(0)); - - \r.wb.addr_RNO_4[6]\ : OR2B - port map(A => \address[6]\, B => dstate_19, Y => N_3733); - - \r.dstate_i_1_RNISU8B9S1[8]\ : NOR3C - port map(A => N_126, B => N_91, C => N_3197, Y => N_12_i_0); - - \r.vaddr[15]\ : DFN1E1 - port map(D => maddress(15), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[15]\); - - \r.mmctrl1.ctxp[8]\ : DFN1E1 - port map(D => maddress(10), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[8]\); - - \r.wb.addr_RNO_6[6]\ : OR2B - port map(A => un1_m0_2_7, B => addr_1_sqmuxa, Y => N_3732); - - \r.cctrl.burst_RNO_0\ : MX2 - port map(A => maddress(16), B => \burst_0\, S => \N_523\, Y - => N_2629); - - \r.wb.addr_RNO_3[7]\ : AOI1B - port map(A => un1_m0_2_8, B => addr_1_sqmuxa_0, C => - \addr_1_1_iv_0_0[7]\, Y => \addr_1_1_iv_0_1[7]\); - - \r.wb.addr_RNO_2[20]\ : NOR2B - port map(A => N_3859, B => N_3862, Y => - \addr_1_1_iv_0_0[20]\); - - \r.read_RNIEEGDD1\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[23]\, B => - \mcdo_m_i[23]\, C => \ddatainv_0_1_0_iv_1[23]\, Y => - read_RNIEEGDD1); - - \r.wb.data1_RNO[3]\ : NOR3 - port map(A => N_3360, B => N_3362, C => N_3363, Y => N_19); - - \r.dstate_0_RNIG0R21[2]\ : NAND2 - port map(A => \dstate_0[2]\, B => diagdata_30, Y => - \ico_m[164]\); - - \r.xaddress_RNIL5KB1[0]\ : AOI1 - port map(A => \addr[0]\, B => N_3764, C => N_3785, Y => - \ddatainv_0_1_0_0[24]\); - - \r.xaddress_RNIJH2O2_10[0]\ : NOR2B - port map(A => dataout(7), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[231]\); - - \r.xaddress_RNICOTFII[24]\ : AO1 - port map(A => \addr[24]\, B => \N_330\, C => N_3892, Y => - newtag_1_0_6); - - \r.xaddress_RNI0SQK4[5]\ : MX2 - port map(A => maddress(5), B => \addr[5]\, S => - un1_taddr_1_sqmuxa, Y => N_2232); - - \r.su_RNI2PIF\ : MX2 - port map(A => msu, B => su_0, S => N_3443_i, Y => su); - - \r.faddr_RNIQHE8[3]\ : NOR2A - port map(A => flush_0, B => \faddr[3]\, Y => N_3287); - - \r.cctrl.ifrz_RNIMLHT3\ : AOI1B - port map(A => un1_m0_2_39, B => miscdata_3_sqmuxa, C => - ifrz_m, Y => \rdatav_0_1_0_iv_3[4]\); - - \r.burst_RNO_3\ : NOR2A - port map(A => N_485, B => N_507, Y => burst_RNO_3); - - \r.wb.addr_RNO_3[6]\ : OR2B - port map(A => \addr[6]\, B => N_3796, Y => N_3731); - - \r.dstate_RNO_3[1]\ : NOR3C - port map(A => \dstate_RNO_5[1]\, B => N_3086_i, C => - dstate_tr22_15_N_10_i, Y => dstate_tr22_1); - - \r.wb.data1_RNO[14]\ : MX2A - port map(A => N_2112, B => maddress(14), S => - req_0_sqmuxa_1_0, Y => \data1_1[14]\); - - \r.read_RNIJH5A\ : NOR2A - port map(A => N_3443_i, B => read, Y => N_3749); - - \r.dstate_RNIEMHMC[1]\ : MX2 - port map(A => maddress(12), B => edata2_0_iv(12), S => - edata_0_sqmuxa_i_0, Y => \edata[12]\); - - \un1_r.faddr_I_30\ : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \faddr[5]\, Y => N_4); - - \r.wb.data2_RNO[21]\ : MX2 - port map(A => edata2_0_iv(21), B => hrdata_0_21, S => - \dstate_2[7]\, Y => \data2_1[21]\); - - \r.mmctrl1.ctxp_RNIEHGVD[5]\ : AOI1B - port map(A => \ctxp[5]\, B => N_3344_i_0_0, C => - \rdatav_0_1_1_iv_0_4[7]\, Y => \rdatav_0_1_1_iv_0_5[7]\); - - \r.dstate_RNO_5[4]\ : NOR3B - port map(A => dstate_tr16_13_0_0_a2_0_1, B => N_114_i_i_0, - C => lock, Y => dstate_tr16_13_0_0_a2_0_3); - - \dctrl.twrite_14_iv_0_o2_a0_RNIVBERA3\ : OR2B - port map(A => twrite_14, B => \dstate_RNIR2CO3[4]\, Y => - N_188); - - \r.paddress[19]\ : DFN1E1 - port map(D => N_415, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[19]\); - - \r.wb.addr_RNO_2[22]\ : NOR2B - port map(A => N_3870, B => N_3873, Y => - \addr_1_1_iv_0_0[22]\); - - \r.holdn_RNO_26\ : AOI1 - port map(A => \dstate_0[7]\, B => N_510, C => \dstate_0[2]\, - Y => holdn_3_sqmuxa_0_0_0); - - \r.wb.addr_RNO_5[14]\ : OR2B - port map(A => un1_m0_2_15, B => addr_1_sqmuxa_0, Y => - N_3729); - - \r.vaddr[21]\ : DFN1E1 - port map(D => maddress(21), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[21]\); - - miscdata_4_sqmuxa_0_a2_0 : NOR2A - port map(A => maddress(10), B => maddress(9), Y => - \miscdata_4_sqmuxa_0_a2_0\); - - \r.wb.addr_RNO_2[8]\ : AOI1B - port map(A => \paddress[8]\, B => \dstate_RNIP22L4[7]\, C - => \mmudco_m[84]\, Y => \addr_1_1_iv_0[8]\); - - miscdata_2_sqmuxa_0_a4_0_a2_0_a3_0 : NOR2A - port map(A => maddress(9), B => maddress(8), Y => - \miscdata_2_sqmuxa_0_a4_0_a2_0_a3_0\); - - \r.wb.data2[0]\ : DFN1E1 - port map(D => \data2_1[0]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[0]\); - - \r.wbinit_RNIA7FN3_0\ : NOR2A - port map(A => N_487, B => dwrite_1_sqmuxa, Y => - addr_1_sqmuxa_0); - - \r.dstate_i_2_RNITQRS1[8]\ : NOR2A - port map(A => \miscdata_4_sqmuxa_0_a2_1\, B => - rdatasel_4_sqmuxa, Y => miscdata_4_sqmuxa); - - \r.wb.data2_RNIUR032[12]\ : NOR2B - port map(A => \data2_m[12]\, B => N_159, Y => - \rdatav_0_1_0_iv_0_0[12]\); - - \r.wb.addr_RNO_3[0]\ : AOI1B - port map(A => \paddress[0]\, B => \dstate_RNIP22L4[7]\, C - => \mmudco_m[76]\, Y => \addr_1_1_iv_0[0]\); - - \r.hit_RNIG1QI\ : NOR2A - port map(A => N_58, B => N_421, Y => un157_m_en); - - \r.xaddress_RNIJH2O2_5[0]\ : NOR2B - port map(A => dataout(9), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[233]\); - - \r.wb.addr_RNO_4[26]\ : OR2B - port map(A => \address[26]\, B => N_514, Y => \addr_m[26]\); - - \r.vaddr[14]\ : DFN1E1 - port map(D => maddress(14), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[14]\); - - \r.vaddr_RNIRLDE[4]\ : MX2 - port map(A => maddress(4), B => \vaddr[4]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[80]\); - - \r.xaddress_RNIU5E9O[1]\ : AOI1B - port map(A => \edata[5]\, B => ddatainv_0_0_sqmuxa, C => - \edata_m_0_i[13]\, Y => \ddatainv_0_1_0_iv_1[29]\); - - \r.holdn_RNO_17\ : NOR3B - port map(A => N_3604, B => holdn_3_sqmuxa_0_0_0, C => - e_0_0_RNI8APPC92, Y => holdn_3_sqmuxa_0_0_2); - - \r.dstate_RNI3CDFG[1]\ : MX2 - port map(A => maddress(31), B => edata2_iv_i_0(31), S => - edata_0_sqmuxa_i, Y => \edata[31]\); - - \r.wb.addr_RNO_3[29]\ : OR2B - port map(A => maddress(29), B => addr_2_sqmuxa, Y => N_261); - - \r.read_RNIR1CL\ : NOR2 - port map(A => N_3749, B => N_3748, Y => \N_425\); - - \dctrl.v.wb.addr_1_1_iv_0_a3_3[29]\ : NAND2 - port map(A => N_514, B => \address[29]\, Y => N_264); - - \r.dstate_RNIDDSEO[1]\ : AO1 - port map(A => \edata[6]\, B => \size_RNIBHS22[0]\, C => - \mcdo_m[6]\, Y => \ddatainv_0_1_1_iv_1[6]\); - - \dctrl.0.un1_dci_NE_0\ : XA1A - port map(A => maddress(24), B => dataout_0(20), C => - un1_dci_1_i, Y => un1_dci_NE_0); - - \r.wb.data2[30]\ : DFN1E1 - port map(D => \data2_1[30]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[30]\); - - \r.dstate_RNIP22L4[7]\ : AO1C - port map(A => burst_0_sqmuxa, B => \dstate[7]\, C => - data2_0_sqmuxa_1, Y => \dstate_RNIP22L4[7]\); - - \r.wb.data1_RNO_0[29]\ : MX2C - port map(A => edata2_iv_i_0(29), B => \data2[29]\, S => - N_3331, Y => N_2127); - - \r.req\ : DFN1 - port map(D => req_RNO, CLK => lclk_c, Q => \req\); - - \r.dstate_RNIGLBNC[1]\ : MX2 - port map(A => maddress(15), B => edata2_0_iv(15), S => - edata_0_sqmuxa_i_0, Y => \edata[15]\); - - \r.mmctrl1.e_0_0_RNI16GR\ : OA1A - port map(A => dstate_tr22_15_a2_14_1_0, B => N_459, C => - \e_0\, Y => dstate_tr22_15_a2_2_m8_i_a5_1_0); - - \r.icenable\ : DFN1 - port map(D => ilramen_1_sqmuxa, CLK => lclk_c, Q => enable); - - \r.holdn_RNO\ : OR3C - port map(A => holdn_0_sqmuxa_1, B => holdn_0_5, C => - holdn_10, Y => holdn_RNO_0); - - \r.mmctrl1.ctxp[17]\ : DFN1E1 - port map(D => maddress(19), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[17]\); - - \r.wb.addr_RNO_5[4]\ : OR2B - port map(A => \un1_m0_2[80]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[80]\); - - \r.dstate_RNO_1[1]\ : OR3A - port map(A => N_3546, B => N_72_i, C => read_0, Y => - N_3564_i); - - \r.wb.data1_RNO[11]\ : MX2A - port map(A => N_2109, B => maddress(11), S => - req_0_sqmuxa_1_0, Y => \data1_1[11]\); - - \r.wb.addr_RNO_5[23]\ : OR2B - port map(A => N_236_0, B => addr_1_sqmuxa_0, Y => N_218); - - \r.mmctrl1.ctx_RNILUJ8[3]\ : XNOR2 - port map(A => dataout(31), B => \ctx[3]\, Y => N_102_i_i); - - \r.mmctrl1.e_RNIJ62V\ : NOR2B - port map(A => \e\, B => N_3755, Y => N_3505_i); - - \r.wb.addr_RNO_6[28]\ : OR2B - port map(A => un1_m0_2_29, B => addr_1_sqmuxa_0, Y => N_213); - - \dctrl.0.un1_dci_NE_5\ : XA1A - port map(A => maddress(20), B => dataout_0(16), C => - un1_dci_10_i, Y => un1_dci_NE_5); - - \r.wb.data2_RNICBOB[29]\ : OR2B - port map(A => \data2[29]\, B => rdatav_012_0, Y => - \data2_m[29]\); - - \r.size_RNIPK6E[0]\ : OR3C - port map(A => \size[0]\, B => N_3749, C => \addr[1]\, Y => - N_3699); - - \r.dstate_RNIKSAI892[2]\ : OA1A - port map(A => N_3069_i, B => ilramen_1_sqmuxa, C => rst, Y - => \dstate_nss[6]\); - - \r.dstate_i_0_RNIV2M5JU1[8]\ : NOR3C - port map(A => N_3676, B => \dstate_ns_i_a4_i_9[0]\, C => - rst, Y => \dstate_nss_i_0[0]\); - - \r.dstate_0_RNIIC256_7[7]\ : OR2B - port map(A => dataout(2), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[226]\); - - \r.wb.addr_RNO_5[30]\ : OR2B - port map(A => \paddress[30]\, B => \dstate_RNIP22L4[7]\, Y - => \paddress_m[30]\); - - \r.dstate_0_RNI8J7VE[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[13]\, B => - \rdatav_0_1_0_iv_2[13]\, C => \mcdo_m_0[13]\, Y => - data_0_13); - - \r.holdn_RNO_11\ : NOR3C - port map(A => N_485, B => holdn_0_sqmuxa_1_m8_0_a2_3, C => - fault_pri, Y => holdn_0_sqmuxa_1_m8_0_a2_5); - - \r.read\ : DFN1 - port map(D => read_RNO, CLK => lclk_c, Q => read); - - \r.asi[2]\ : DFN1E1 - port map(D => asi(2), CLK => lclk_c, E => N_486_0, Q => - \asi_0[2]\); - - \r.valid_0_RNO_1[5]\ : OR2B - port map(A => \dstate_i_1[8]\, B => N_96, Y => - \valid_0_1_1_a4_1_0[5]\); - - \r.nomds_RNIPG271\ : NOR2A - port map(A => twrite_14_iv_0_o2_a1_0, B => un17_casaen_0_0, - Y => twrite_14_iv_0_o2_a1_1); - - \r.mmctrl1.e_RNIUU9O_0\ : OR2 - port map(A => \e\, B => N_526, Y => N_2994_6); - - \r.dstate_RNI7GJK9[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_0_7, Y => N_3313); - - \r.dstate_RNO_0[4]\ : AOI1B - port map(A => dstate_tr16_13_0_0_a2_0_5, B => un1_m0_2_108, - C => \dstate_ns_0_2[4]\, Y => \dstate_ns_0_3[4]\); - - \r.mmctrl1.ctxp_RNITPJ12[21]\ : OR2B - port map(A => \ctxp[21]\, B => N_3344_i_0, Y => - \ctxp_m[21]\); - - \r.dstate_RNIDR7M2[1]\ : NOR2B - port map(A => \edata[2]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[2]\); - - \r.stpend_RNI897S692\ : OR3A - port map(A => stpend, B => read_1, C => N_581_i, Y => - N_3514); - - \r.mmctrl1.ctx_0_0_RNI4VGHD[3]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_i_a2_2[3]\, B => - \rdatav_0_1_1_iv_i_a2_1[3]\, C => - \rdatav_0_1_1_iv_i_a2_4[3]\, Y => - \rdatav_0_1_1_iv_i_a2_5[3]\); - - \r.dstate_i_0_RNID0P84[8]\ : OR3A - port map(A => un18_m_en, B => \dstate_i_0[8]\, C => N_328, - Y => addr_0_sqmuxa_1); - - \r.dstate_RNIEVI95[2]\ : AOI1B - port map(A => \ico_m_0[145]\, B => cdwrite_0_sqmuxa_i_0_0, - C => \rdatav_0_1_1_iv_1[11]\, Y => - \rdatav_0_1_1_iv_2[11]\); - - \r.wb.addr_RNO_5[25]\ : MX2 - port map(A => \paddress_0[25]\, B => \addr[25]\, S => N_484, - Y => \paddress[25]\); - - \r.read_RNIMJHQT\ : OR3 - port map(A => \mcdo_m[13]\, B => \edata_m_1[5]\, C => - \ddatainv_0_1_1_iv_0[13]\, Y => read_RNIMJHQT); - - \r.wb.addr_RNO_2[21]\ : AOI1B - port map(A => N_419, B => addr_1_sqmuxa_0, C => N_3717, Y - => \addr_1_1_iv_0_0[21]\); - - \r.xaddress_RNIRHEVJ[5]\ : MX2 - port map(A => N_2232, B => eaddress_3, S => taddr_2_sqmuxa, - Y => \taddr_7[5]\); - - \r.wb.lock_RNI35I6\ : NOR2B - port map(A => \lock_0\, B => bo_d(2), Y => lock_m_0); - - \r.dstate_RNI67JMC[1]\ : MX2 - port map(A => maddress(14), B => edata2_0_iv(14), S => - edata_0_sqmuxa_i_0, Y => \edata[14]\); - - \un1_r.faddr_I_27\ : AND2 - port map(A => \faddr[3]\, B => \faddr[4]\, Y => - \DWACT_FINC_E[1]\); - - \r.mmctrl1.ctxp_RNIQLJ12[11]\ : OR2B - port map(A => \ctxp[11]\, B => N_3344_i_0_0, Y => - \ctxp_m[11]\); - - \r.dstate_RNII2LPC[5]\ : NOR2A - port map(A => data2_0_sqmuxa_1, B => N_562, Y => N_3815); - - \dctrl.0.un1_dci_NE_16\ : NOR3C - port map(A => un1_dci_NE_5, B => un1_dci_NE_4, C => - un1_dci_NE_13, Y => un1_dci_NE_16); - - \r.faddr[5]\ : DFN1E0 - port map(D => \faddr_1[5]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[5]\); - - \r.cctrl.dcs_RNIITHQ2A2[0]\ : OR3A - port map(A => N_467, B => N_576, C => N_581_i, Y => N_611); - - \r.wb.data1[12]\ : DFN1E0 - port map(D => \data1_1[12]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_0); - - \r.read_RNI0NEDD\ : OR2B - port map(A => \N_425\, B => N_264_0, Y => \mcdo_m_i[19]\); - - \r.dstate[0]\ : DFN1 - port map(D => \dstate_nss[8]\, CLK => lclk_c, Q => - \dstate[0]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_10\ : NOR2A - port map(A => eaddress_5, B => eaddress_20, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_10); - - \r.wb.data1[29]\ : DFN1E0 - port map(D => \data1_1[29]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_17); - - \r.wb.addr_RNO[9]\ : AO1B - port map(A => \address[9]\, B => N_514, C => - \addr_1_1_iv_2[9]\, Y => \addr_1[9]\); - - \r.stpend_RNIUDDF6\ : NOR2B - port map(A => stpend_0_sqmuxa, B => \dstate_RNI5GFM4[5]\, Y - => data1_0_sqmuxa_0); - - \r.xaddress_RNI0GI17S2[17]\ : OR3C - port map(A => N_3893, B => N_229, C => \dci_m[89]\, Y => - xaddress_RNI0GI17S2(17)); - - \r.read_RNO\ : NOR2B - port map(A => rst, B => N_2684, Y => read_RNO); - - \dctrl.un11_eholdn_2_0_a2_0_a4_0_a2\ : OR2 - port map(A => asi(3), B => asi(2), Y => N_2938_2); - - \r.dstate_RNO_2[0]\ : NOR3B - port map(A => \dstate_ns_0_0_a2_0_1[8]\, B => - un121_m_en_i_s_0, C => un1_m0_2_0_d0, Y => - \dstate_ns_0_0_a2_0_3[8]\); - - \r.dstate_i_2_RNISK8N1_4[8]\ : OR2B - port map(A => dataout(28), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[408]\); - - \r.dstate_i_2_RNIDLM8792[8]\ : OR2A - port map(A => N_3745, B => un1_dci_12, Y => N_3790); - - \r.paddress[4]\ : DFN1E1 - port map(D => un1_m0_2_5, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[4]\); - - \r.dstate_i_RNINU2473[8]\ : NOR2A - port map(A => \dstate_i[8]\, B => twrite_14, Y => - valid_0_2_sqmuxa); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e\ : NOR2A - port map(A => \vaddr_1_sqmuxa_0_a2_4_m1_e_24\, B => - eaddress_29, Y => un1_addout_13_i); - - \r.mmctrl1.ctx_RNIEH4T5[6]\ : NOR2A - port map(A => \ctx_m[6]\, B => \rdatav_0_1_6[3]\, Y => - \rdatav_0_1_1_iv_3[6]\); - - \r.cctrl.ifrz\ : DFN1E0 - port map(D => maddress(4), CLK => lclk_c, E => \N_523\, Q - => ifrz); - - \r.wb.addr_RNO_4[20]\ : OR2B - port map(A => N_3842, B => \dstate_RNIP22L4[7]\, Y => - N_3859); - - \r.dstate_2_RNI7PRT7[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_17, Y => - \mcdo_m_0[17]\); - - \r.xaddress[11]\ : DFN1 - port map(D => N_713, CLK => lclk_c, Q => \addr[11]\); - - \r.read_RNID0E6C\ : NOR2B - port map(A => \N_425_0\, B => hrdata_0_d0, Y => \mcdo_m[5]\); - - \r.vaddr_RNIEQHC[26]\ : MX2 - port map(A => maddress(26), B => \vaddr[26]\, S => - \dstate_i_1[8]\, Y => data(26)); - - \r.wb.addr_RNO_6[27]\ : MX2 - port map(A => \paddress[27]\, B => \addr[27]\, S => N_484_0, - Y => N_674); - - \r.dstate_RNO_8[4]\ : OR2 - port map(A => N_3041_11, B => dstate_ns_0_2065_0, Y => - \dstate_RNO_8[4]\); - - \r.wb.data1_RNO[29]\ : MX2A - port map(A => N_2127, B => maddress(29), S => - req_0_sqmuxa_1, Y => \data1_1[29]\); - - \r.dstate_RNIR0ANC[1]\ : MX2 - port map(A => maddress(21), B => edata2_0_iv(21), S => - edata_0_sqmuxa_i, Y => \edata[21]\); - - \r.dstate_i_2_RNISK8N1_3[8]\ : OR2B - port map(A => dataout(30), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[410]\); - - \r.dstate_RNIVHK83[1]\ : NOR2B - port map(A => \edata[2]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[2]\); - - \r.mmctrl1.ctxp_RNI1QJ12[25]\ : OR2B - port map(A => \ctxp[25]\, B => N_3344_i_0_0, Y => - \ctxp_m[25]\); - - \dctrl.rdatav_0_1_0_iv[29]\ : NAND2 - port map(A => \mcdo_m_0[29]\, B => \rdatav_0_1_0_iv_4[29]\, - Y => data_0_29); - - \r.xaddress_RNIFP43F[2]\ : MX2C - port map(A => N_2229, B => eaddress_0, S => taddr_2_sqmuxa, - Y => xaddress_RNIFP43F(2)); - - \r.flush_RNIMPMV8\ : NOR3A - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - maddress(10), Y => N_3297); - - \r.xaddress_RNI7O47A[1]\ : OR2B - port map(A => \edata[1]\, B => ddatainv_0_0_sqmuxa, Y => - \edata_m_4_i[1]\); - - \r.wb.addr_RNO_4[22]\ : OR2B - port map(A => N_3840, B => \dstate_RNIP22L4[7]\, Y => - N_3870); - - \r.valid_0_RNO_0[3]\ : OR2A - port map(A => \dstate_i_RNID1NU1[8]\, B => N_188, Y => - N_3380); - - \r.holdn_RNO_0\ : MX2C - port map(A => holdn_RNO_3, B => fault_pro, S => holdn_RNO_4, - Y => holdn_0_sqmuxa_1); - - \dctrl.0.un1_dci_2_0_RNII1KT\ : NOR3C - port map(A => un1_dci_NE_1, B => un1_dci_NE_0, C => - un1_dci_NE_11, Y => un1_dci_NE_15); - - \r.wb.size_RNO[1]\ : MX2 - port map(A => size_1_d0, B => \size_0[1]\, S => - \dstate_i[8]\, Y => N_654); - - \r.wb.data2[28]\ : DFN1E1 - port map(D => \data2_1[28]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[28]\); - - \dctrl.0.genmux.un6_validrawv_5\ : MX2 - port map(A => dataout_0(3), B => dataout_0(7), S => - maddress(4), Y => N_2016); - - \r.xaddress_RNI1CIE2[0]\ : OR2B - port map(A => \ddatainv_0_1_0_0[24]\, B => N_574, Y => - N_2088); - - \r.wb.addr_RNO_1[0]\ : OR2B - port map(A => un1_m0_2_1, B => addr_1_sqmuxa, Y => - \mmudco_m[2]\); - - \r.vaddr_RNI7MHC[21]\ : MX2 - port map(A => maddress(21), B => \vaddr[21]\, S => - \dstate_i_2[8]\, Y => data(21)); - - \r.dstate_0_RNI0KIER[2]\ : OR3C - port map(A => \rdatav_0_1_1_iv_5[16]\, B => - \rdatav_0_1_1_iv_4[16]\, C => \mcdo_m_0[16]\, Y => - data_0_16); - - \un1_r.faddr_I_31\ : XOR2 - port map(A => N_4, B => \faddr[6]\, Y => I_31_1); - - \r.wb.data2_RNI6BAS3[4]\ : NOR3C - port map(A => \dcramo_m[412]\, B => \data2_m[4]\, C => - rdatav_0_2_sqmuxa, Y => \rdatav_0_1_0_iv_1[4]\); - - \r.valid_0[1]\ : DFN1E0 - port map(D => \valid_0_1[1]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[1]\); - - \r.wb.addr_RNO_5[31]\ : OR2B - port map(A => N_317_0, B => addr_1_sqmuxa, Y => N_3716); - - \r.size_RNIRG4D[1]\ : OR2B - port map(A => \size_0[1]\, B => N_3749, Y => N_3766); - - \r.flush_RNI13HE4\ : OR2A - port map(A => taddr_2_sqmuxa, B => flush_0, Y => N_195); - - \r.dstate_i_RNI9P0G[8]\ : MX2C - port map(A => dataout_0(5), B => N_96, S => \dstate_i[8]\, - Y => N_110); - - \r.wb.data1[1]\ : DFN1E0 - port map(D => \data1_1[1]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data(1)); - - \r.dstate_i_RNI29QQ7J3[8]\ : OAI1 - port map(A => N_349, B => \vmask_0_5[6]\, C => N_298, Y => - dstate_i_RNI29QQ7J3(8)); - - \r.dstate_RNO_14[4]\ : OR2B - port map(A => un1_m0_2_0_d0, B => \dstate[4]\, Y => N_3181); - - \r.dstate_i_RNI85G9RS2[8]\ : AO1B - port map(A => \vmask_0_5[7]\, B => N_3315, C => - \dstate_i_RNII68N892_0[8]\, Y => N_3278); - - \r.wbinit\ : DFN1E1 - port map(D => N_485, CLK => lclk_c, E => - \mmudci_trans_op_1_sqmuxa_1\, Q => wbinit); - - \r.wb.addr_RNO_0[7]\ : NOR3C - port map(A => N_3735, B => N_3734, C => - \addr_1_1_iv_0_1[7]\, Y => \addr_1_1_iv_0_3[7]\); - - \r.dstate_0_RNI2DT77_2[2]\ : AOI1B - port map(A => diagdata_13, B => \dstate_0[2]\, C => - \dcramo_m_0[237]\, Y => \rdatav_0_1_0_iv_3[13]\); - - \r.wb.data1_RNO_0[28]\ : MX2C - port map(A => edata2_iv_i_0(28), B => \data2[28]\, S => - N_3331_0, Y => N_2126); - - \r.wb.addr_RNO_4[7]\ : AOI1B - port map(A => \un1_m0_2[83]\, B => addr_1_sqmuxa_2_0, C => - N_3737, Y => \addr_1_1_iv_0_0[7]\); - - \r.valid_0[6]\ : DFN1E0 - port map(D => \valid_0_1[6]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[6]\); - - \r.cctrl.dcs_RNO_2[1]\ : NOR2A - port map(A => dfrz, B => intack, Y => \dcs_0_i_0_a2_0[1]\); - - \r.xaddress_RNIC9N39[10]\ : NOR3B - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - \addr[10]\, Y => N_3298); - - \r.wb.data1_RNO_0[0]\ : MX2B - port map(A => edata2_0_iv(0), B => \data2[0]\, S => N_3331, - Y => N_2098); - - \r.read_RNIOVA59\ : OR2B - port map(A => \N_425\, B => hrdata_0_27, Y => - \mcdo_m_i[27]\); - - \r.wb.data2_RNO[13]\ : MX2 - port map(A => edata2_0_iv(13), B => hrdata_0_13, S => - \dstate_0[7]\, Y => \data2_1[13]\); - - \r.paddress[29]\ : DFN1E1 - port map(D => N_353, CLK => lclk_c, E => paddress_1_sqmuxa, - Q => \paddress[29]\); - - \r.wb.addr[25]\ : DFN1 - port map(D => \addr_1[25]\, CLK => lclk_c, Q => - \address[25]\); - - \un1_r.faddr_I_23\ : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \faddr[3]\, C => - \faddr[4]\, Y => N_9_0); - - \r.wb.addr_RNO[18]\ : AO1B - port map(A => un1_m0_2_93, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[18]\, Y => \addr_1[18]\); - - \r.dstate_i_RNI8VKHK92[8]\ : OR2A - port map(A => edata2_0_iv(13), B => \N_3254_0\, Y => - \dci_m[85]\); - - \r.mmctrl1.ctxp_RNISPJ12[20]\ : OR2B - port map(A => \ctxp[20]\, B => N_3344_i_0, Y => - \ctxp_m[20]\); - - \r.mmctrl1.ctxp[2]\ : DFN1E1 - port map(D => maddress(4), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[2]\); - - \r.dstate_i_RNIPU8DG92[8]\ : OR2 - port map(A => edata2_0_iv(0), B => - \dstate_i_RNII68N892_0[8]\, Y => N_303); - - \r.dstate_i_2_RNI41OO[8]\ : NOR3A - port map(A => enaddr, B => \dstate_i_2[8]\, C => N_496, Y - => N_3755); - - \r.mmctrl1.e_RNIG9094\ : OA1B - port map(A => N_666, B => N_2994_6, C => - \dstate_ns_0_7_tz_0[3]\, Y => \dstate_ns_0_8_tz[3]\); - - \r.dstate_RNO_9[4]\ : NOR2 - port map(A => read_0, B => N_3499, Y => - dstate_tr16_10_0_i_0); - - \r.wb.addr[15]\ : DFN1 - port map(D => \addr_1[15]\, CLK => lclk_c, Q => - \address[15]\); - - \r.req_RNO\ : AOI1B - port map(A => req_1_2, B => req_2_sqmuxa, C => rst, Y => - req_RNO); - - \r.flush_RNISQ07LK\ : OR3A - port map(A => N_3322, B => N_3248, C => flush_0, Y => N_349); - - \r.dstate_RNIMTANC[1]\ : MX2 - port map(A => maddress(18), B => edata2_0_iv(18), S => - edata_0_sqmuxa_i_0, Y => \edata[18]\); - - \r.cctrl.dcs_RNI2RG54[0]\ : OA1A - port map(A => un6_validrawv, B => size_1_d0, C => - setrepl_0_sqmuxa_1_m_i_5_0, Y => - setrepl_0_sqmuxa_1_m_i_5_2); - - \r.wb.addr_RNO_3[3]\ : OR2B - port map(A => un1_m0_2_4, B => addr_1_sqmuxa, Y => N_293_0); - - \r.wb.addr_RNO_1[30]\ : NOR3C - port map(A => \dci_m[38]\, B => \addr_1_1_iv_0[30]\, C => - \addr_m[30]\, Y => \addr_1_1_iv_2[30]\); - - \r.holdn_RNI8G6B\ : NOR2 - port map(A => read_1, B => N_3443_i, Y => N_3748); - - \r.vaddr[30]\ : DFN1E1 - port map(D => maddress(30), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[30]\); - - \r.faddr_RNI7879K[0]\ : MX2 - port map(A => \taddr_7[5]\, B => \faddr[0]\, S => - \un1_p0_2_0[498]\, Y => faddr_RNI7879K(0)); - - \r.dstate_RNIBGU46_0[2]\ : NOR2B - port map(A => dataout(3), B => rdatav_0_6_sqmuxa_3, Y => - N_3339); - - \r.dstate_i_2_RNISK8N1_8[8]\ : OR2B - port map(A => dataout_0(13), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[113]\); - - \r.wb.addr_RNO_2[2]\ : AO1C - port map(A => \address[2]\, B => N_323, C => dstate_19, Y - => N_315); - - \r.mmctrl1.ctx_0_0[1]\ : DFN1 - port map(D => \ctx_0_0_RNIQIPQ[1]\, CLK => lclk_c, Q => - \ctx_0[1]\); - - \r.dstate_RNIO9NNA[1]\ : NOR2B - port map(A => \edata[4]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[4]\); - - \r.dstate_ns_0_0_o2_0[1]\ : NOR2B - port map(A => N_3569_2, B => N_3586, Y => - \dstate_ns_0_0_o2_0[1]\); - - \r.xaddress_RNIJH2O2_11[0]\ : NOR2B - port map(A => dataout(3), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[227]\); - - \r.wb.addr_RNO_2[3]\ : OR2B - port map(A => \address[3]\, B => dstate_19, Y => N_295); - - \r.wb.data2_RNISU546[19]\ : NOR3B - port map(A => \mmudco_m[62]\, B => \rdatav_0_1_0_iv_0[19]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_2[19]\); - - \r.dstate_1_RNI223L7[7]\ : NOR3B - port map(A => \dstate_ns_i_a4_i_o2_9_0[0]\, B => - data2_0_sqmuxa_1, C => N_3811, Y => - \dstate_ns_i_a4_i_o2_9_2[0]\); - - \r.dstate_i_RNII68N892[8]\ : OR2A - port map(A => tdiagwrite_1_0_0_o2_1, B => \N_121\, Y => - \N_3254_0\); - - \r.xaddress_RNIID927S2[16]\ : OR3C - port map(A => N_242, B => N_240, C => \dci_m[88]\, Y => - xaddress_RNIID927S2(16)); - - \r.mmctrl1.ctxp_RNIOOCKD[2]\ : AND2 - port map(A => \ctxp_m[2]\, B => \rdatav_0_1_0_iv_5[4]\, Y - => \rdatav_0_1_0_iv_6[4]\); - - \r.cctrl.dcs[0]\ : DFN1 - port map(D => \dcs_RNO[0]\, CLK => lclk_c, Q => \dcs[0]\); - - \r.wb.addr_RNO_4[21]\ : OR2B - port map(A => \dstate_RNIP22L4[7]\, B => N_552, Y => N_3717); - - \r.wb.data1_RNO_0[15]\ : MX2C - port map(A => edata2_0_iv(15), B => \data2[15]\, S => - N_3331, Y => N_2113); - - \r.cctrl.dcs_RNIBN6EB[0]\ : AO1 - port map(A => \dstate_ns_i_a4_i_o2_9_2[0]\, B => - mexc_0_sqmuxa_1, C => \dcs[0]\, Y => \dcs_RNIBN6EB[0]\); - - \r.read_RNIFPGIE\ : OR2B - port map(A => \N_425_0\, B => hrdata_23, Y => - \mcdo_m_i[28]\); - - \r.dstate_RNO_6[5]\ : OR3A - port map(A => \dstate_ns_0_2_0_tz[3]\, B => N_3511, C => - ready, Y => \dstate_ns_0_2_0[3]\); - - \r.dstate_RNI4UNNA[1]\ : NOR2B - port map(A => \edata[5]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[5]\); - - \r.stpend_RNIGCK85\ : NOR2B - port map(A => N_485, B => N_102, Y => burst_0_sqmuxa_2); - - \r.xaddress_RNIQF6M2_10[0]\ : OR2B - port map(A => dataout(16), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[240]\); - - \r.wb.data2[16]\ : DFN1E1 - port map(D => \data2_1[16]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[16]\); - - \r.ready\ : DFN1E1 - port map(D => ready_0_sqmuxa_0, CLK => lclk_c, E => - ready_0_sqmuxa, Q => ready_0); - - \r.mmctrl1.e_RNIC0632\ : OR2B - port map(A => \e\, B => miscdata_0_sqmuxa, Y => e_m); - - \r.holdn_RNO_29\ : NOR2 - port map(A => \dstate_i_0[8]\, B => lock, Y => - holdn_0_sqmuxa_1_m8_0_a2_0); - - \r.flush_0_1_RNI7GU5992\ : OR2B - port map(A => maddress(13), B => \N_329\, Y => N_3849); - - \r.dstate_RNIN7LKB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[1]\, Y => \ddatainv_0_1_0_iv_1[17]\); - - \r.dstate_RNIMK5S4[7]\ : AO1A - port map(A => burst_0_sqmuxa, B => \dstate[7]\, C => - ready_0_sqmuxa_0, Y => N_572); - - \r.xaddress_RNI5PMB[4]\ : MX2 - port map(A => maddress(4), B => \addr[4]\, S => N_3443_i, Y - => N_679); - - \r.wb.data2_RNI9BOB[26]\ : OR2B - port map(A => \data2[26]\, B => rdatav_012, Y => - \data2_m[26]\); - - \r.wb.addr_RNO_4[19]\ : MX2 - port map(A => \paddress[19]\, B => \addr[19]\, S => N_484, - Y => N_3837); - - \un1_v.cctrlwr19_2_0_a2_0\ : NOR3C - port map(A => N_561, B => read_0, C => cctrlwr13, Y => - N_3607); - - \r.flush_RNILUNG\ : NOR3A - port map(A => size_1_d0, B => size_0_0, C => flush_0, Y => - N_132); - - \r.stpend_RNIRDAC2\ : NOR2 - port map(A => ready_0_sqmuxa_0_a2_0_a2_0, B => N_72_i, Y - => ready_0_sqmuxa_0); - - \r.dstate_RNIHILB6_7[7]\ : OR2B - port map(A => dataout(17), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[241]\); - - \v.burst_2_sqmuxa_m8_0_a4_0_RNIQKINJ92\ : OR3 - port map(A => burst_2_sqmuxa_m8_0_a4_0, B => - burst_2_sqmuxa_m8_0_0, C => N_485, Y => burst_1_sqmuxa); - - \dctrl.v.burst_16_m_RNIO1SFQ92\ : AO1C - port map(A => un1_dci_12, B => burst_3_m_3, C => - burst_1_iv_2_1, Y => burst_1_iv_2); - - \r.dstate_RNI1JGE7[2]\ : AOI1B - port map(A => diagdata_29, B => \dstate[2]\, C => - \dcramo_m_0[253]\, Y => \rdatav_0_1_0_iv_3[29]\); - - \r.dstate_2_RNIPUOKL[7]\ : OR2B - port map(A => \rdatav_0_1_0_iv_4[30]\, B => \mcdo_m_0[30]\, - Y => data_0_30); - - \r.dstate_0_RNI5PIRE[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[26]\, B => - \rdatav_0_1_0_iv_2[26]\, C => \mcdo_m_0[26]\, Y => - data_0_26); - - \r.xaddress_RNI10V9992[17]\ : OR2B - port map(A => \addr[17]\, B => \N_330\, Y => N_229); - - \r.wb.addr_RNO_3[8]\ : OR2B - port map(A => maddress(8), B => addr_2_sqmuxa, Y => - \dci_m[16]\); - - \r.hit_RNO_3\ : NOR3B - port map(A => hit_1_iv_0_a2_0_0, B => un10_m_en, C => - \dstate_i_0[8]\, Y => hit_1_iv_0_a2_0_2); - - \r.dstate_i_RNINECF892[8]\ : OR3 - port map(A => un19_eholdn, B => - \mmudci_fsread_1_sqmuxa_0_a2_0\, C => \N_121\, Y => - fsread_i_0); - - \r.cache_RNO_7\ : NOR2A - port map(A => N_102, B => \dstate_i_2[8]\, Y => N_3836); - - \r.dstate_i_RNIGAV0O92[8]\ : OR2A - port map(A => edata2_iv_i_0(28), B => \N_3254_0\, Y => - N_144); - - \r.wb.addr_RNO_1[28]\ : NOR3C - port map(A => N_3888, B => \addr_1_1_iv_0_0[28]\, C => - N_214, Y => \addr_1_1_iv_0_2[28]\); - - \r.wb.addr_RNO_0[9]\ : NOR3C - port map(A => \mmudco_m[11]\, B => \addr_1_1_iv_0[9]\, C - => \dci_m[17]\, Y => \addr_1_1_iv_2[9]\); - - \r.mmctrl1.nf_RNO\ : NOR2B - port map(A => rst, B => N_2675, Y => nf_RNO); - - \r.dstate_0_RNIIC256_6[7]\ : OR2B - port map(A => dataout(8), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[232]\); - - \r.wb.addr_RNO_5[1]\ : OR2B - port map(A => \un1_m0_2[77]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[77]\); - - \r.vaddr_RNI6AHC[22]\ : MX2 - port map(A => maddress(22), B => \vaddr[22]\, S => - \dstate_i_1[8]\, Y => data(22)); - - \r.paddress[18]\ : DFN1E1 - port map(D => un1_m0_2_19, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[18]\); - - \r.mmctrl1.ctx_RNISO622[6]\ : OR2B - port map(A => \ctx[6]\, B => miscdata_2_sqmuxa, Y => - \ctx_m[6]\); - - \r.dstate_RNIF6E91_0[2]\ : OR2B - port map(A => diagdata_5, B => \dstate[2]\, Y => N_3397); - - \r.xaddress_RNIP2BVK1[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[30]\, B => - \mcdo_m_i[30]\, C => \ddatainv_0_1_0_iv_1[30]\, Y => - xaddress_RNIP2BVK1(1)); - - \r.xaddress_RNIQF6M2[0]\ : OR2B - port map(A => dataout_0(30), B => N_2088, Y => - \dcramo_m_i[254]\); - - \r.wb.data2_RNI1VRU1[8]\ : AOI1B - port map(A => \data2[8]\, B => rdatav_012_0, C => - \dcramo_m_0[105]\, Y => \rdatav_0_1_0_iv_0[8]\); - - \r.read_RNI8DFM31\ : OR3 - port map(A => \mcdo_m[8]\, B => \edata_m_1[0]\, C => - \ddatainv_0_1_1_iv_0[8]\, Y => read_RNI8DFM31); - - \r.dstate_RNIVK67A[1]\ : NOR2B - port map(A => \edata[4]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[4]\); - - \r.dstate_0_RNI7FKF5[7]\ : AOI1B - port map(A => \dstate_0[7]\, B => N_585, C => N_3707, Y => - \dstate_ns_0_0_0[1]\); - - \r.faddr_RNIRHE8[4]\ : NOR2A - port map(A => flush_0, B => \faddr[4]\, Y => N_3291); - - \r.wb.data1[13]\ : DFN1E0 - port map(D => \data1_1[13]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_1); - - \r.dstate_RNIF6E91_2[2]\ : OR2B - port map(A => diagdata_6, B => \dstate[2]\, Y => - \ico_m[140]\); - - \r.dstate_i_2_RNIRQM12[8]\ : OR2B - port map(A => un1_m0_2_65, B => miscdata_4_sqmuxa, Y => - \mmudco_m[66]\); - - \r.dstate_i_0_RNI3GDM[8]\ : MX2C - port map(A => dataout_0(4), B => \vmask_0_5_1_a4_0_0[4]\, S - => \dstate_i_0[8]\, Y => \vmask_0_5_1_0[4]\); - - \r.mexc\ : DFN1E1 - port map(D => mexc, CLK => lclk_c, E => mexc_0_sqmuxa, Q - => mexc_0); - - \r.xaddress_RNIUC9VJ[0]\ : AND2 - port map(A => \edata_m_i[27]\, B => \dcramo_m_i[251]\, Y - => \ddatainv_0_1_0_iv_0[27]\); - - \r.dstate_i_2_RNIPLVA892[8]\ : OR2B - port map(A => dstate_tr22_15_a2_3_1_0, B => N_3583, Y => - dstate_tr22_15_a2_4_1); - - \r.wb.addr_RNO_6[25]\ : OR2B - port map(A => N_190_0, B => addr_1_sqmuxa, Y => - \mmudco_m[27]\); - - \r.wb.addr_RNO_1[19]\ : OR2B - port map(A => maddress(19), B => addr_2_sqmuxa, Y => N_221); - - \r.dstate_RNO_11[5]\ : OR2 - port map(A => N_2995_8, B => N_2994_8, Y => - \dstate_ns_0_4_tz[3]\); - - \r.dstate_RNIETKM8[1]\ : MX2B - port map(A => maddress_0_0, B => edata2_0_iv(1), S => - edata_0_sqmuxa_i_0, Y => \edata[1]\); - - \r.mmctrl1.ctxp_RNI0MJ12[17]\ : OR2B - port map(A => \ctxp[17]\, B => N_3344_i_0, Y => - \ctxp_m[17]\); - - \r.stpend_RNIFU09L92\ : NOR3C - port map(A => vaddr_1_sqmuxa_0_a2_4_m7_i_a4, B => - vaddr_1_sqmuxa_0_a2_5, C => r_N_6, Y => - \vaddr_1_sqmuxa_0_a2_2\); - - \r.dstate_i_0_RNIE3RBE91_0[8]\ : OR3B - port map(A => N_3835, B => dataout_0(0), C => - \dstate_i_0[8]\, Y => N_302); - - \r.dstate_0_RNI2DT77_0[2]\ : AOI1B - port map(A => diagdata_24, B => \dstate_0[2]\, C => - \dcramo_m_0[248]\, Y => \rdatav_0_1_0_iv_4[24]\); - - \r.xaddress_RNI0D8CG[4]\ : MX2 - port map(A => N_3261, B => eaddress_2, S => taddr_2_sqmuxa, - Y => N_10); - - \r.read_RNITTMR8\ : OR2B - port map(A => \N_425_0\, B => hrdata_25, Y => - \mcdo_m_i[30]\); - - \r.dstate_RNIK6EKA[3]\ : OR3C - port map(A => N_3750, B => N_3760, C => holdn_2_sqmuxa, Y - => N_562); - - \r.dstate_i_0_RNIRJRKFJ[8]\ : NOR2B - port map(A => N_128_1, B => N_3248, Y => - \vmask_0_1_2_a4_0_0[4]\); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_4[10]\ : OR2B - port map(A => maddress(10), B => addr_2_sqmuxa_0, Y => - N_3642); - - \r.ready_RNIR2KA\ : OR2 - port map(A => stpend, B => ready_0, Y => N_508); - - \r.dstate_RNI0S6QJ[1]\ : AOI1B - port map(A => \edata[29]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[253]\, Y => \ddatainv_0_1_0_iv_0[29]\); - - \r.valid_0_RNO[5]\ : AO1B - port map(A => dataout_0(5), B => N_88, C => - \valid_0_1_1_0[5]\, Y => \valid_0_1[5]\); - - \r.paddress[9]\ : DFN1E1 - port map(D => un1_m0_2_10, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress_0[9]\); - - \r.mmctrl1.ctx_0_0_RNI849L[7]\ : MX2 - port map(A => \ctx_0[7]\, B => maddress(7), S => - ctx_1_sqmuxa, Y => N_2670); - - \r.dstate_tr8_9_10_i_o2_i_a2_i_o2_0\ : OR2B - port map(A => asi(4), B => asi(0), Y => N_537); - - \r.hit_RNICORB1\ : OA1A - port map(A => N_3845, B => hit, C => twrite_11_m_0_a2_0_0, - Y => twrite_11_m_0_a2_0_1); - - \r.burst\ : DFN1 - port map(D => burst_RNO, CLK => lclk_c, Q => \burst\); - - \r.mmctrl1.ctxp[10]\ : DFN1E1 - port map(D => maddress(12), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[10]\); - - \r.size_RNIBHS22[0]\ : OR3B - port map(A => N_3700, B => N_3699, C => ddatainv_0_6_sqmuxa, - Y => \size_RNIBHS22[0]\); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0[3]\ : NAND2 - port map(A => N_559, B => - \vmaskraw_1_i_o2_i_a3_0_a2_0_0[3]\, Y => N_3661); - - \v.mmctrl1.e_0_sqmuxa\ : AND2 - port map(A => e_0_sqmuxa_2, B => e_0_sqmuxa_0, Y => - e_0_sqmuxa); - - \r.wb.addr_RNO_1[31]\ : AND2 - port map(A => N_3652, B => \addr_1_1_iv_0_0[31]\, Y => - \addr_1_1_iv_0_1[31]\); - - \r.dstate_RNI4TIJ[4]\ : NOR2B - port map(A => \dstate[4]\, B => N_58, Y => - twrite_14_iv_0_o4_0_o2_0); - - \r.xaddress_RNIQF6M2_8[0]\ : OR2B - port map(A => dataout(19), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[243]\); - - \r.valid_0[7]\ : DFN1E0 - port map(D => \valid_0_1[7]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[7]\); - - \r.nomds_RNIH54T\ : NOR2B - port map(A => un1_dci_12_0, B => N_3745, Y => - twrite_14_iv_0_o2_a1_0); - - \r.dstate_RNI0GC5A[1]\ : NOR2B - port map(A => \edata[7]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[7]\); - - \r.wb.addr_RNO_1[7]\ : OR2B - port map(A => \addr[7]\, B => N_3796, Y => N_3735); - - \r.nomds_RNIRCHA_0\ : OR2A - port map(A => nomds, B => hold_0, Y => N_3588); - - \r.wb.lock_RNO_3\ : OR3B - port map(A => lock, B => N_566, C => dstate_14, Y => N_3554); - - \r.xaddress[21]\ : DFN1E1 - port map(D => maddress(21), CLK => lclk_c, E => N_486, Q - => \addr[21]\); - - \r.wb.addr_RNO_2[7]\ : OR2B - port map(A => \paddress[7]\, B => N_3792, Y => N_3734); - - \r.vaddr_RNIAMHC[16]\ : MX2 - port map(A => maddress(16), B => \vaddr[16]\, S => - \dstate_i_1[8]\, Y => data(16)); - - \r.mmctrl1.ctxp[27]\ : DFN1E1 - port map(D => maddress(29), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[27]\); - - \r.dstate_RNIV0IM2[5]\ : NOR2A - port map(A => N_566, B => dstate_14, Y => req_0_sqmuxa_1_0); - - \r.wb.data2[2]\ : DFN1E1 - port map(D => \data2_1[2]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[2]\); - - \r.holdn_RNO_15\ : OR3B - port map(A => N_485, B => holdns_iv_0_a2_1_0, C => - \dstate_i_2_RNITVLGB92[8]\, Y => N_3615); - - \r.dstate_RNID7OK8[1]\ : MX2B - port map(A => maddress(0), B => edata2_0_iv(0), S => - edata_0_sqmuxa_i, Y => \edata[0]\); - - \r.mmctrl1.ctx_RNIABMN[2]\ : MX2 - port map(A => \ctx[2]\, B => maddress(2), S => ctx_1_sqmuxa, - Y => N_2665); - - \r.xaddress_RNIU3V9992[21]\ : OR2B - port map(A => \addr[21]\, B => \N_330\, Y => N_232); - - miscdata_4_sqmuxa_0_a2_1 : NOR2A - port map(A => \miscdata_4_sqmuxa_0_a2_0\, B => maddress(8), - Y => \miscdata_4_sqmuxa_0_a2_1\); - - \dctrl.v.cctrlwr13_0_a2\ : NOR2 - port map(A => cctrlwr13_0_a2_0, B => N_223, Y => cctrlwr13); - - \r.dstate_0_RNI0DV1J[2]\ : NOR3C - port map(A => \ctxp_m[0]\, B => \rdatav_0_1_0_iv_4[2]\, C - => \rdatav_0_1_0_iv_6[2]\, Y => rdatav_0_1_0_iv_7_2); - - \r.dstate_RNIQHHHH[1]\ : AO1 - port map(A => \edata[13]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[237]\, Y => \ddatainv_0_1_1_iv_0[13]\); - - \r.wb.addr_RNO_2[19]\ : AOI1B - port map(A => N_3837, B => N_2165_0, C => N_3890, Y => - \addr_1_1_iv_0_0[19]\); - - \r.wb.addr_RNO_0[29]\ : AOI1B - port map(A => data_1_3_i_a3_6_4, B => LVL_RNIT69H911(0), C - => addr_1_sqmuxa_2_0, Y => \addr_1_1_iv_0_a3_2_0[29]\); - - \r.xaddress[16]\ : DFN1E1 - port map(D => maddress(16), CLK => lclk_c, E => N_486, Q - => \addr[16]\); - - \r.wb.data2_RNIPOUT5[28]\ : AOI1B - port map(A => dataout_0(24), B => rdatasel_1_sqmuxa_1_0, C - => \rdatav_0_1_1_iv_1[28]\, Y => \rdatav_0_1_1_iv_2[28]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_22\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_19, B => - eaddress_22, C => eaddress_21, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_22); - - \r.wb.data1_RNO_1[3]\ : NOR2A - port map(A => req_0_sqmuxa_1, B => maddress_0_2, Y => - N_3362); - - \r.wb.data2_RNO[25]\ : MX2 - port map(A => edata2_iv_i_0(25), B => N_78_0, S => - \dstate_1[7]\, Y => \data2_1[25]\); - - \r.wb.addr_RNO_3[14]\ : OR2B - port map(A => \address[14]\, B => N_514, Y => N_3728); - - \r.mmctrl1.e_RNI9F783_0\ : NOR2A - port map(A => un47_m_en, B => N_3331, Y => addr_2_sqmuxa); - - \r.dstate_RNIF6E91_1[2]\ : OR2B - port map(A => diagdata_3, B => \dstate[2]\, Y => N_3404); - - \r.wb.addr_RNO_1[27]\ : NOR3C - port map(A => N_250, B => \addr_1_1_iv_0_0[27]\, C => N_253, - Y => \addr_1_1_iv_0_2[27]\); - - \r.size_RNI58Q41[1]\ : OA1B - port map(A => N_3757, B => maddress_0_0, C => N_3805, Y => - N_575); - - \r.dstate_RNIM2E08[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_0_9, Y => mcdo_m_0_8); - - \r.xaddress_RNIVN7I_0[0]\ : OR3B - port map(A => N_3764, B => \addr[0]\, C => \addr[1]\, Y => - N_3623); - - \r.dstate_RNIHILB6_1[7]\ : OR2B - port map(A => dataout(26), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[250]\); - - \r.dstate_RNIFMKG5[7]\ : NOR2B - port map(A => \dstate_RNIP22L4[7]\, B => N_484_0, Y => - N_3796); - - \r.wb.data2[21]\ : DFN1E1 - port map(D => \data2_1[21]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[21]\); - - \r.wb.addr_RNO[7]\ : AO1B - port map(A => maddress(7), B => N_2164, C => - \addr_1_1_iv_0_3[7]\, Y => \addr_1[7]\); - - \r.dstate_i_RNI0F9DG92[8]\ : OR2A - port map(A => edata2_0_iv(1), B => \N_3254_0\, Y => N_126); - - \r.cctrl.ics_RNIEBF34[0]\ : AOI1B - port map(A => un1_m0_2_35, B => miscdata_3_sqmuxa, C => - \ics_m[0]\, Y => \rdatav_0_1_0_iv_2[0]\); - - \r.wb.data2_RNIG3792[17]\ : AOI1B - port map(A => \data2[17]\, B => rdatav_012_0, C => - rdatav_0_1_sqmuxa, Y => \rdatav_0_1_1_iv_0[17]\); - - \r.dstate_RNIH89NC[1]\ : MX2 - port map(A => maddress(20), B => edata2_0_iv(20), S => - edata_0_sqmuxa_i_0, Y => \edata[20]\); - - \r.wb.data2_RNO[19]\ : MX2 - port map(A => edata2_0_iv(19), B => N_264_0, S => - \dstate[7]\, Y => \data2_1[19]\); - - \r.wb.addr[3]\ : DFN1 - port map(D => \addr_1[3]\, CLK => lclk_c, Q => \address[3]\); - - \r.dstate_i_2_RNIA2SML3_0[8]\ : OR2A - port map(A => vaddr_1_sqmuxa_0_0, B => - \mmudci_trans_op_1_sqmuxa_1\, Y => vaddr_1_sqmuxa); - - \r.xaddress_RNO[7]\ : MX2 - port map(A => \addr[7]\, B => maddress(7), S => N_486_0, Y - => N_712); - - \r.wbinit_RNIMANB3\ : OA1A - port map(A => \dstate_ns_i_a4_i_a2_15_0[0]\, B => - un1_m0_2_0_d0, C => dstate_0_sqmuxa, Y => - \dstate_ns_i_a4_i_o2_9_0[0]\); - - \r.dstate_RNI33OR2[1]\ : OR3B - port map(A => N_58, B => \dstate[1]\, C => flush_i, Y => - dwrite_4_sqmuxa); - - \r.vaddr[27]\ : DFN1E1 - port map(D => maddress(27), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[27]\); - - \r.wb.data1_RNO_0[21]\ : MX2C - port map(A => edata2_0_iv(21), B => \data2[21]\, S => - N_3331, Y => N_2119); - - \r.vaddr[13]\ : DFN1E1 - port map(D => maddress(13), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[13]\); - - \r.dstate_RNIAQNB0A2_0[7]\ : NOR2A - port map(A => twrite_11_m, B => N_55, Y => dwrite_1_iv_0); - - \r.dstate_i_2_RNIGB1N1[8]\ : OR3A - port map(A => N_665, B => N_3758, C => asi(3), Y => N_3677); - - \r.nomds_RNI4C96\ : NOR2A - port map(A => nomds, B => \dstate_i[8]\, Y => rdatav_012); - - \r.dstate_i_RNIQ5EIK92[8]\ : OR2A - port map(A => edata2_0_iv(15), B => - \dstate_i_RNII68N892_0[8]\, Y => \dci_m[87]\); - - \r.dstate[3]\ : DFN1 - port map(D => \dstate_nss[5]\, CLK => lclk_c, Q => - \dstate[3]\); - - \r.read_RNI9KP09\ : OR3C - port map(A => N_179, B => N_178, C => mexc_0_sqmuxa_1, Y - => dco_i_2(132)); - - \r.mmctrl1.e_RNIAF78I\ : NOR3C - port map(A => e_m, B => \rdatav_0_1_0_iv_4[0]\, C => - \dcramo_m_0[224]\, Y => \rdatav_0_1_0_iv_6[0]\); - - \r.wb.addr_RNO_6[30]\ : MX2 - port map(A => \paddress_0[30]\, B => \addr[30]\, S => N_484, - Y => \paddress[30]\); - - \r.dstate_RNIUR652_0[5]\ : OR2A - port map(A => \dstate[5]\, B => N_566, Y => data2_1_sqmuxa); - - \r.mmctrl1.ctxp_RNI6LB66[25]\ : NOR3C - port map(A => \mmudco_m[70]\, B => \rdatav_0_1_0_iv_0[27]\, - C => \ctxp_m[25]\, Y => \rdatav_0_1_0_iv_2[27]\); - - \r.dstate_RNO_10[1]\ : NOR2A - port map(A => dstate_tr22_15_0_a2_0, B => N_666, Y => - dstate_tr22_15_0_a2_1); - - \r.dstate_i_2_RNIV16D1[8]\ : NOR2 - port map(A => N_666, B => N_526, Y => - dstate_tr22_15_a2_3_1_0); - - \r.dstate_i_2_RNI3KVJ1_3[8]\ : NOR2A - port map(A => N_3253_i, B => N_526, Y => - rdatasel_1_sqmuxa_1); - - \r.wb.read\ : DFN1E0 - port map(D => N_419_0, CLK => lclk_c, E => - \dstate_RNI5GFM4[5]\, Q => \read_2\); - - \r.read_RNIQMJI41\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[17]\, B => - \mcdo_m_i[17]\, C => \ddatainv_0_1_0_iv_1[17]\, Y => - read_RNIQMJI41); - - \dctrl.un1_eholdn_2_i_i_o2_0\ : NOR2 - port map(A => cctrlwr13, B => N_494, Y => N_509); - - \r.ready_RNO_4\ : OR3A - port map(A => N_527, B => N_3758, C => N_3778, Y => - ready_0_sqmuxa_0_a2_1); - - \r.flush_RNIGBB873\ : OR2 - port map(A => flush_0, B => twrite_14, Y => flush_RNIGBB873); - - \r.wb.data2_RNIQQ546[18]\ : NOR3B - port map(A => \mmudco_m[61]\, B => \rdatav_0_1_0_iv_0[18]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_2[18]\); - - \r.mmctrl1.pso_RNIJ3VF\ : MX2 - port map(A => pso, B => \ctx[7]\, S => maddress(9), Y => - N_3259); - - \r.dstate_i_RNIRRRPEJ[8]\ : OR3A - port map(A => mexc, B => N_3248, C => \vmask_0_5[7]\, Y => - N_3282); - - \dctrl.un1_eholdn_2_1_0_a2_1_0_o2_i_a2\ : OR2 - port map(A => asi(4), B => N_505, Y => N_3799); - - \dctrl.0.genmux.un6_validrawv_1\ : MX2 - port map(A => dataout_0(0), B => dataout_0(4), S => - maddress(4), Y => N_2012); - - \r.wb.data1_RNO[15]\ : MX2A - port map(A => N_2113, B => maddress(15), S => - req_0_sqmuxa_1, Y => \data1_1[15]\); - - \r.wb.data1[15]\ : DFN1E0 - port map(D => \data1_1[15]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_3); - - \r.xaddress_RNO_2[2]\ : MX2C - port map(A => maddress(2), B => \addr[2]\, S => N_591, Y - => N_670); - - \r.flush_0_1_RNIDKU5992\ : NOR2B - port map(A => maddress(26), B => \N_329\, Y => N_245); - - \r.mmctrl1.ctxp_RNI1MJ12[18]\ : OR2B - port map(A => \ctxp[18]\, B => N_3344_i_0, Y => - \ctxp_m[18]\); - - \r.dstate_RNO_5[5]\ : OR2B - port map(A => N_3002_9, B => N_29, Y => N_3028); - - \r.stpend_RNO\ : OA1 - port map(A => dstate_5_sqmuxa, B => stpend_1_0, C => rst, Y - => stpend_RNO); - - \r.xaddress_RNIS6BN1[3]\ : AO1C - port map(A => \addr[3]\, B => N_3793, C => N_3662, Y => - N_3421); - - \r.wb.data1_RNO_0[22]\ : MX2C - port map(A => edata2_0_iv(22), B => \data2[22]\, S => - N_3331_0, Y => N_2120); - - \r.wb.data1[2]\ : DFN1E0 - port map(D => \data1_1[2]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(2)); - - \r.flush_RNI13HE4_0\ : NOR2 - port map(A => flush_0, B => taddr_2_sqmuxa, Y => N_3319); - - \r.faddr[3]\ : DFN1E0 - port map(D => \faddr_1[3]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[3]\); - - \r.dstate_i_2_RNISK8N1_26[8]\ : OR2B - port map(A => dataout_0(10), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[110]\); - - \r.dstate_RNO_2[1]\ : OAI1 - port map(A => dstate_tr22_15_a2_4_1, B => un1_m0_2_108, C - => e_0_0_RNIIAUC4Q1, Y => N_3545); - - \r.paddress[10]\ : DFN1E1 - port map(D => un1_m0_2_11, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[10]\); - - \r.mmctrl1.e_RNI0TEJ1\ : NOR3B - port map(A => N_3755, B => e_RNIKN3D, C => - dstate_tr8_1_8_0_a2_0, Y => N_2995_8); - - \dctrl.twrite_14_iv_0_a2_a0_RNO\ : AND2 - port map(A => twrite_14_iv_0_a2_a0_3, B => un1_addout_12, Y - => twrite_14_iv_0_a2_a0_4); - - \v.wb.addr_0_sqmuxa_2_RNI7GIK2\ : AND2 - port map(A => burst_1_sqmuxa_0, B => addr_0_sqmuxa_2, Y => - burst_1_sqmuxa_1); - - \r.wb.data2_RNIT3M64[28]\ : NOR3C - port map(A => rdatav_0_1_sqmuxa, B => \data2_m[28]\, C => - rdatav_0_2_sqmuxa, Y => \rdatav_0_1_1_iv_1[28]\); - - \r.cctrl.ics_RNO_0[1]\ : NOR2A - port map(A => \N_523\, B => \ics[1]\, Y => N_3203); - - \r.xaddress_RNI30V9992[19]\ : OR2B - port map(A => \addr[19]\, B => \N_330\, Y => N_3875); - - \r.dstate_0_RNI7RSMI[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_0_14, Y => - \mcdo_m_0[14]\); - - \r.xaddress_RNO_1[2]\ : OR3 - port map(A => N_503, B => N_507, C => - \dstate_i_2_RNITVLGB92[8]\, Y => N_3698); - - \r.mmctrl1.ctxp_RNID8SKD[27]\ : NOR3C - port map(A => \ctxp_m[27]\, B => \rdatav_0_1_0_iv_1[29]\, C - => \rdatav_0_1_0_iv_3[29]\, Y => \rdatav_0_1_0_iv_4[29]\); - - \r.dstate_RNO_11[1]\ : AO1 - port map(A => N_3586, B => N_595, C => N_526, Y => - dstate_tr22_15_m8_i_a5_0_0); - - \r.dstate_i_RNIVPST692[8]\ : OR2 - port map(A => \dstate_i[8]\, B => un1_dci_12, Y => \N_121\); - - \r.wb.data2_RNIV27LB[6]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_1[6]\, B => \mmudco_m[42]\, - C => \rdatav_0_1_1_iv_3[6]\, Y => \rdatav_0_1_1_iv_4[6]\); - - \r.nomds_RNIBK9H\ : OR2 - port map(A => enaddr, B => N_522, Y => - \dstate_ns_i_a4_i_a2_6_0[0]\); - - \r.cache_RNO_5\ : OAI1 - port map(A => N_527, B => dstate_25_0_a2_0, C => N_587, Y - => dstate_25); - - \dctrl.vmaskraw_1_i_o2_i_a2_0_RNIBEQD1_0[1]\ : AO1 - port map(A => N_3654, B => N_3653, C => N_679, Y => N_32); - - \r.vaddr_RNI9UHC[14]\ : MX2 - port map(A => maddress(14), B => \vaddr[14]\, S => - \dstate_i_2[8]\, Y => data(14)); - - \r.cctrl.ics_RNO[0]\ : OA1C - port map(A => \N_523\, B => \ics[0]\, C => \ics_0_i_0[0]\, - Y => N_25); - - \r.dstate_RNI5V1O[5]\ : NOR2 - port map(A => mexc_1_sqmuxa, B => \dstate[5]\, Y => - dstate_14); - - \r.dstate_RNIPGERL[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_26, Y => - \mcdo_m_0[31]\); - - \r.dstate_i_0_RNIDBOO[8]\ : NOR3 - port map(A => N_496, B => asi(2), C => \dstate_i_0[8]\, Y - => \rdatasel_1_i_a5_1[7]\); - - \r.dstate_RNI7PANC[1]\ : MX2 - port map(A => maddress(22), B => edata2_0_iv(22), S => - edata_0_sqmuxa_i_0, Y => \edata[22]\); - - \r.valid_0_RNO_0[2]\ : MX2C - port map(A => dataout_0(2), B => \vmask_0_6[2]\, S => - twrite_14, Y => N_2362); - - \r.flush_RNIFDO51\ : OR2A - port map(A => N_136, B => N_533, Y => mexc_1_m_0_a2_0); - - \r.dstate_i_2_RNISK8N1_23[8]\ : OR2B - port map(A => dataout_0(19), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[119]\); - - \r.dstate_RNIPPBLD[1]\ : OR2B - port map(A => \edata[20]\, B => ddatainv_0_6_sqmuxa, Y => - \edata_m_i[20]\); - - \r.dstate_RNIJ4L3K[1]\ : AOI1B - port map(A => \edata[26]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[250]\, Y => \ddatainv_0_1_0_iv_0[26]\); - - \r.dstate_0_RNIT7AKF[2]\ : NOR3C - port map(A => \ctxp_m[17]\, B => \rdatav_0_1_0_iv_2[19]\, C - => \rdatav_0_1_0_iv_4[19]\, Y => rdatav_0_1_0_iv_5_15); - - \r.xaddress_RNIJH2O2_7[0]\ : NOR2B - port map(A => dataout(6), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[230]\); - - \r.vaddr_RNITPDE[5]\ : MX2 - port map(A => maddress(5), B => \vaddr[5]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[81]\); - - \r.holdn_RNII9911\ : AO1C - port map(A => N_507, B => N_3748, C => N_3754, Y => N_534); - - \r.wb.data2[31]\ : DFN1E1 - port map(D => \data2_1[31]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[31]\); - - \r.dstate_RNIBTFDH[1]\ : NAND2 - port map(A => ddatainv_0_6_sqmuxa, B => \edata[31]\, Y => - \edata_m_i[31]\); - - \r.valid_0_RNO_0[0]\ : OR2A - port map(A => \valid_0_RNI7F6M2[0]\, B => N_188, Y => - N_3377); - - \r.paddress[28]\ : DFN1E1 - port map(D => un1_m0_2_29, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[28]\); - - \dctrl.0.un1_dci_2_0\ : XNOR2 - port map(A => maddress(14), B => dataout_0(10), Y => - un1_dci_2_i); - - \r.xaddress_RNI2MB27S2[15]\ : OR3C - port map(A => N_257, B => N_255, C => \dci_m[87]\, Y => - xaddress_RNI2MB27S2(15)); - - \r.wb.data2_RNI87OB[18]\ : OR2B - port map(A => \data2[18]\, B => rdatav_012, Y => - \data2_m[18]\); - - \r.wb.addr_RNO[5]\ : AO1B - port map(A => maddress(5), B => N_2164, C => - \addr_1_1_iv_0_2[5]\, Y => \addr_1[5]\); - - \r.dstate_2_RNICFS88[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_11, Y => - \mcdo_m_0[11]\); - - \dctrl.v.cctrlwr13_0_a2_0\ : OR2A - port map(A => asi(3), B => asi(2), Y => cctrlwr13_0_a2_0); - - \un1_r.faddr_I_20\ : XOR2 - port map(A => N_12, B => \faddr[4]\, Y => I_20_1); - - \r.mmctrl1.ctx_0_0_RNIQIPQ[1]\ : NOR2B - port map(A => rst, B => N_2664, Y => \ctx_0_0_RNIQIPQ[1]\); - - \r.dstate_i_RNI2PT49S1[8]\ : NOR3C - port map(A => N_130, B => N_91, C => N_131, Y => N_16_i_0); - - \r.wb.addr_RNO_1[23]\ : OR2B - port map(A => maddress(23), B => addr_2_sqmuxa_0, Y => - N_216); - - \r.dstate_0_RNI5H7N9[7]\ : AOI1B - port map(A => dataout(10), B => rdatav_0_6_sqmuxa_0, C => - \rdatav_0_1_0_iv_0_1[10]\, Y => rdatav_0_1_0_iv_0_2_0); - - \r.wb.addr_RNO_4[5]\ : MX2 - port map(A => \paddress[5]\, B => \addr[5]\, S => N_484_0, - Y => \addr_1_1_iv_0_a3_0_0[5]\); - - \r.xaddress_RNIG9CSTI[22]\ : OA1A - port map(A => edata2_0_iv(22), B => \N_3254_0\, C => N_3864, - Y => \newtag_1_0[22]\); - - \r.wb.data1_RNO_0[6]\ : MX2B - port map(A => edata2_0_iv(6), B => \data2[6]\, S => N_3331, - Y => N_2104); - - \r.dstate_0_RNIS19ED[2]\ : NOR3C - port map(A => \ctxp_m[21]\, B => \rdatav_0_1_0_iv_1[23]\, C - => \rdatav_0_1_0_iv_3[23]\, Y => rdatav_0_1_0_iv_4_23); - - \r.wb.data1_RNO[4]\ : MX2A - port map(A => N_2102, B => maddress(4), S => req_0_sqmuxa_1, - Y => \data1_1[4]\); - - \r.valid_0_RNIE5BNG91[0]\ : OR2B - port map(A => N_3835, B => \valid_0_RNI7F6M2[0]\, Y => - N_301); - - \r.mmctrl1.ctx_RNIN0CR[6]\ : NOR2B - port map(A => rst, B => N_2669, Y => \ctx_RNIN0CR[6]\); - - \r.flush_0_1_RNI9GU5992\ : OR2B - port map(A => maddress(15), B => \N_329\, Y => N_257); - - \r.dstate_RNI0P3L7[2]\ : AOI1B - port map(A => diagdata_31, B => \dstate[2]\, C => - \dcramo_m_0[255]\, Y => \rdatav_0_1_0_iv_3[31]\); - - \r.mmctrl1.e_0_0_RNIUJMK\ : AO1C - port map(A => asi(2), B => \e_0\, C => N_590, Y => - holdn_3_sqmuxa_0_0_a2_2_0); - - \r.dstate_0_RNI2DT77_3[2]\ : AND2 - port map(A => \ico_m[138]\, B => \dcramo_m_0[228]\, Y => - \rdatav_0_1_0_iv_7[4]\); - - \r.dstate_RNIIL8UF[1]\ : MX2 - port map(A => maddress(25), B => edata2_iv_i_0(25), S => - edata_0_sqmuxa_i, Y => \edata[25]\); - - \r.dstate_i_0_RNIDS4F2[8]\ : OAI1 - port map(A => N_2047, B => un19_eholdn_3, C => - \rdatasel_1_i_a5_1[7]\, Y => N_2042); - - \dctrl.0.genmux.un6_validrawv_4_i\ : MX2 - port map(A => dataout_0(1), B => dataout_0(5), S => - maddress(4), Y => N_7); - - \r.wb.data2_RNO[4]\ : MX2A - port map(A => edata2_0_iv(4), B => hrdata_0_4, S => - \dstate_2[7]\, Y => \data2_1[4]\); - - \r.wb.addr_RNO[28]\ : AO1B - port map(A => \addr_1_1_iv_0_a3_1_0[28]\, B => N_2702_i_0, - C => \addr_1_1_iv_0_2[28]\, Y => \addr_1[28]\); - - \r.holdn_RNO_20\ : NOR3B - port map(A => lock, B => N_485, C => cctrlwr19_2_0_a2_1_1, - Y => holdn_RNO_20); - - \r.faddr[4]\ : DFN1E0 - port map(D => \faddr_1[4]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[4]\); - - \r.dstate_RNI59OG3_0[4]\ : OR2A - port map(A => \dstate[4]\, B => dwrite_1_sqmuxa, Y => - holdn_2_sqmuxa); - - \un1_r.faddr_I_19\ : NOR2B - port map(A => \faddr[3]\, B => \DWACT_FINC_E[0]\, Y => N_12); - - \r.dstate_RNO_12[1]\ : NOR2A - port map(A => N_3089_7, B => N_507, Y => - dstate_tr22_15_0_a2_0); - - \r.dstate_RNO_4[4]\ : NOR3B - port map(A => dstate_tr16_10_0_i_0, B => N_395, C => - N_581_i, Y => dstate_tr16_10_0_i_2); - - \r.dstate_0_RNIIC256_1[7]\ : OR2B - port map(A => dataout(25), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[249]\); - - \dctrl.0.un1_dci_2_0_RNI0AA4\ : AND2 - port map(A => un1_dci_13_i, B => un1_dci_2_i, Y => - un1_dci_NE_1); - - \r.wb.addr_RNO_3[28]\ : AOI1B - port map(A => N_3839, B => N_2165_0, C => N_213, Y => - \addr_1_1_iv_0_0[28]\); - - \r.xaddress_RNO[3]\ : MX2 - port map(A => \addr[3]\, B => maddress(3), S => N_486_0, Y - => N_719); - - \r.wb.addr_RNO_1[25]\ : NOR3C - port map(A => \dci_m[33]\, B => \addr_1_1_iv_0[25]\, C => - \addr_m[25]\, Y => \addr_1_1_iv_2[25]\); - - \r.vaddr_RNI8EHC[23]\ : MX2 - port map(A => maddress(23), B => \vaddr[23]\, S => - \dstate_i_1[8]\, Y => data(23)); - - \r.stpend_RNILN5ACQ1\ : NOR2B - port map(A => \vaddr_1_sqmuxa_0_a2_2\, B => - \stpend_RNI6P41NG3\, Y => \mmudci_trans_op_1_sqmuxa_1\); - - \r.dstate_RNIHILB6[7]\ : OR2B - port map(A => dataout(11), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[235]\); - - \r.xaddress_RNI2MLOE1[9]\ : NOR3 - port map(A => N_3294, B => N_3293, C => \address_i_0[7]\, Y - => N_26); - - \r.mmctrl1.ctx[2]\ : DFN1 - port map(D => \ctx_RNIFGBR[2]\, CLK => lclk_c, Q => - \ctx[2]\); - - \r.faddr_RNIIMO9[6]\ : OR2B - port map(A => \faddr[6]\, B => \un1_p0_2_0[498]\, Y => - flush_0_sqmuxa_0); - - \r.cctrl.ics_RNO_0[0]\ : OAI1 - port map(A => \N_523\, B => maddress(0), C => rst, Y => - \ics_0_i_0[0]\); - - \r.xaddress[30]\ : DFN1E1 - port map(D => maddress(30), CLK => lclk_c, E => N_486, Q - => \addr[30]\); - - \r.faddr_RNO[0]\ : NOR3B - port map(A => rst, B => flush_0, C => \faddr[0]\, Y => - \faddr_1[0]\); - - \r.wb.data1[24]\ : DFN1E0 - port map(D => \data1_1[24]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_12); - - \r.dstate_0_RNIIC256_9[7]\ : NAND2 - port map(A => rdatav_0_6_sqmuxa_0, B => dataout_0(28), Y - => \dcramo_m_0[252]\); - - \r.mmctrl1.ctx_0_0[4]\ : DFN1 - port map(D => \ctx_0_0_RNI7TTO[4]\, CLK => lclk_c, Q => - \ctx_0[4]\); - - \r.wb.addr_RNO_1[2]\ : NOR3C - port map(A => N_316, B => N_317, C => N_318, Y => - \addr_1_0_iv_0_1[2]\); - - \r.dstate_RNIF6E91_3[2]\ : OR2B - port map(A => diagdata_7, B => \dstate[2]\, Y => N_3312); - - \r.dstate_i_2_RNI22GL2[8]\ : OA1C - port map(A => un10_m_en, B => - dstate_tr8_4_9_0_a2_0_a2_0_a2_0, C => N_526, Y => - \dstate_ns_0_7_tz_0[3]\); - - \r.dstate_0_RNIG0R21_0[2]\ : NAND2 - port map(A => \dstate_0[2]\, B => diagdata_28, Y => - \ico_m[162]\); - - \un1_v.cctrlwr19_2_0_o2_0_0\ : OA1 - port map(A => N_223, B => N_3091_3, C => cctrlwr12, Y => - cctrlwr19_2_0_o2_0_0); - - \r.wb.addr_RNO_0[6]\ : AOI1B - port map(A => \paddress[6]\, B => N_3792, C => N_3731, Y - => \addr_1_1_iv_0_2[6]\); - - \r.dstate_RNI6285A[1]\ : NOR2B - port map(A => \edata[0]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[0]\); - - \r.wb.addr_RNO_4[3]\ : MX2 - port map(A => \paddress[3]\, B => \addr[3]\, S => N_484, Y - => N_675); - - \r.dstate_i_2_RNI86U12[8]\ : OR2B - port map(A => un1_m0_2_40, B => miscdata_3_sqmuxa, Y => - \mmudco_m[41]\); - - \r.xaddress_RNIN7J17S2[14]\ : OR3C - port map(A => N_239, B => N_237, C => \dci_m[86]\, Y => - xaddress_RNIN7J17S2(14)); - - \r.holdn_RNIBQEJ\ : NOR3B - port map(A => enaddr, B => \hold\, C => \dstate_i_1[8]\, Y - => N_486); - - \r.wb.addr_RNO_5[2]\ : OR3B - port map(A => N_115, B => N_421, C => data2_0_sqmuxa_1, Y - => N_317); - - \r.wb.addr_RNO_4[0]\ : MX2 - port map(A => \paddress_0[0]\, B => \addr[0]\, S => N_484, - Y => \paddress[0]\); - - \r.dstate_0_RNI1JGE7_1[2]\ : AOI1B - port map(A => diagdata_15, B => \dstate_0[2]\, C => - \dcramo_m_0[239]\, Y => \rdatav_0_1_0_iv_0_5[15]\); - - \r.xaddress[26]\ : DFN1E1 - port map(D => maddress(26), CLK => lclk_c, E => N_486, Q - => \addr[26]\); - - \r.req_RNO_3\ : NOR3A - port map(A => N_2471_i, B => req_0_sqmuxa_1_0, C => - addr_1_sqmuxa_0, Y => req_1_1); - - \r.wb.addr_RNO_0[16]\ : NOR3C - port map(A => \dci_m[24]\, B => \addr_1_1_iv_0[16]\, C => - \addr_m[16]\, Y => \addr_1_1_iv_2[16]\); - - \r.dstate_0_RNI1JGE7_5[2]\ : AOI1B - port map(A => diagdata_16, B => \dstate_0[2]\, C => - \dcramo_m_0[240]\, Y => \rdatav_0_1_1_iv_5[16]\); - - \r.wb.addr_RNO_4[30]\ : OR2B - port map(A => \address[30]\, B => N_514, Y => \addr_m[30]\); - - \r.vaddr_RNIEUHC[18]\ : MX2 - port map(A => maddress(18), B => \vaddr[18]\, S => - \dstate_i_1[8]\, Y => data(18)); - - \r.dstate_i_2_RNI1RM12[8]\ : OR2B - port map(A => un1_m0_2_71, B => miscdata_4_sqmuxa, Y => - \mmudco_m[72]\); - - \r.vaddr_RNI5AEE[9]\ : MX2 - port map(A => maddress(9), B => \vaddr[9]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[85]\); - - \r.dstate_RNIF38I3[4]\ : OR3A - port map(A => \dstate[4]\, B => enaddr, C => N_580, Y => - N_3682); - - \r.dstate_i_RNI9BVJ3[8]\ : MX2C - port map(A => \vmask_0_4[7]\, B => N_2027, S => - \dstate_i[8]\, Y => \vmask_0_5[7]\); - - \r.wb.data1_RNO_0[17]\ : MX2C - port map(A => edata2_0_iv(17), B => \data2[17]\, S => - N_3331_0, Y => N_2115); - - \r.dstate_i_0_RNIH0PPES[8]\ : OR3C - port map(A => N_305, B => N_304, C => N_306, Y => - dstate_i_0_RNIH0PPES(8)); - - \r.xaddress[19]\ : DFN1E1 - port map(D => maddress(19), CLK => lclk_c, E => N_486, Q - => \addr[19]\); - - \r.wb.data2_RNILJ3M3[0]\ : NOR3C - port map(A => \dcramo_m[408]\, B => \data2_m[0]\, C => - \dcramo_m[96]\, Y => \rdatav_0_1_0_iv_1[0]\); - - \r.wbinit_RNIA7FN3_1\ : NOR2A - port map(A => N_487, B => dwrite_1_sqmuxa, Y => - addr_1_sqmuxa); - - \r.xaddress_RNIQF6M2_5[0]\ : NAND2 - port map(A => N_2088, B => dataout(27), Y => - \dcramo_m_i[251]\); - - \r.read_RNITCGI61\ : AOI1B - port map(A => \N_425_0\, B => N_78_0, C => - \ddatainv_0_1_0_iv_0[25]\, Y => \ddatainv_0_1_0_iv_2[25]\); - - \r.holdn_RNO_22\ : OR2B - port map(A => un121_m_en_i_s_0, B => hit, Y => N_60); - - \dctrl.un1_eholdn_2_9_0\ : OR3A - port map(A => cctrlwr12, B => N_3779, C => cctrlwr13, Y => - un1_eholdn_2_9); - - \r.xaddress[15]\ : DFN1E1 - port map(D => maddress(15), CLK => lclk_c, E => N_486, Q - => \addr[15]\); - - \r.faddr_RNO[4]\ : NOR3C - port map(A => rst, B => flush_0, C => I_20_1, Y => - \faddr_1[4]\); - - \r.dstate_i_2_RNIMN842[8]\ : OR2B - port map(A => un1_m0_2_57, B => miscdata_4_sqmuxa, Y => - \mmudco_m[58]\); - - \r.mmctrl1.ctxp_RNI0LB66[23]\ : AOI1B - port map(A => \ctxp[23]\, B => N_3344_i_0_0, C => - \rdatav_0_1_0_iv_1[25]\, Y => \rdatav_0_1_0_iv_2[25]\); - - \r.dstate_2_RNIFOF68[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_25, Y => - \mcdo_m_0[30]\); - - \r.wb.addr_RNO_2[30]\ : OR2B - port map(A => maddress(30), B => addr_2_sqmuxa, Y => - \dci_m[38]\); - - \r.mmctrl1.ctxp_RNIJ9F32[3]\ : OR2B - port map(A => \ctxp[3]\, B => N_3344_i_0, Y => N_3395); - - \r.nomds_RNI2PHA\ : NOR2 - port map(A => nomds, B => flush, Y => dstate_tr20_0); - - \r.paddress_RNIAJN31[2]\ : MX2 - port map(A => \paddress[2]\, B => \addr[2]\, S => N_484, Y - => N_115); - - \r.holdn_RNIL0894\ : NOR2 - port map(A => N_3665_1, B => N_582, Y => taddr_2_sqmuxa); - - \un1_v.cctrlwr19_2_0_o2_2\ : OR2A - port map(A => asi(3), B => N_481, Y => N_557); - - \r.dstate_i_2_RNIVQM12[8]\ : OR2B - port map(A => un1_m0_2_69, B => miscdata_4_sqmuxa, Y => - \mmudco_m[70]\); - - \r.xaddress_RNIPQFG1[1]\ : AO1C - port map(A => \addr[1]\, B => N_3782, C => N_3621, Y => - ddatainv_0_0_sqmuxa); - - \r.wb.addr_RNO[4]\ : AO1B - port map(A => maddress(4), B => N_2164, C => - \addr_1_1_iv_0_2[4]\, Y => \addr_1[4]\); - - \r.mmctrl1.e_0_0_RNITGT6\ : NOR2A - port map(A => \e_0\, B => read_0, Y => - cctrlwr19_2_0_a2_1_1_0); - - \r.faddr_RNO[6]\ : NOR3C - port map(A => rst, B => flush_0, C => I_31_1, Y => - \faddr_1_i[6]\); - - \r.dstate_RNITAO34[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[2]\, Y => \ddatainv_0_1_0_iv_1[18]\); - - \r.read_RNO_0\ : MX2 - port map(A => read, B => read_1, S => N_486_0, Y => N_2684); - - \r.wb.data1[10]\ : DFN1E0 - port map(D => \data1_1[10]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data(10)); - - \r.dstate_i_RNIEHMTN92[8]\ : NOR2A - port map(A => edata2_iv_i_0(24), B => \N_3254_0\, Y => - dci_m_88); - - \r.xaddress_RNIQF6M2_7[0]\ : OR2B - port map(A => dataout(22), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[246]\); - - \r.wb.addr_RNO_5[16]\ : MX2 - port map(A => \paddress_0[16]\, B => \addr[16]\, S => N_484, - Y => \paddress[16]\); - - \r.wb.addr_RNO_3[27]\ : AOI1B - port map(A => N_293, B => addr_1_sqmuxa_0, C => N_249, Y - => \addr_1_1_iv_0_0[27]\); - - \r.stpend_RNI0U832\ : NOR2A - port map(A => N_485, B => read_1, Y => - dstate_tr22_15_a2_1_1_0); - - \r.xaddress[2]\ : DFN1 - port map(D => \xaddress_1[2]\, CLK => lclk_c, Q => - \addr[2]\); - - \r.dstate_i_RNI6FTV1[8]\ : OR2A - port map(A => N_485, B => \dstate_i[8]\, Y => N_3331); - - \r.wb.data2[27]\ : DFN1E1 - port map(D => \data2_1[27]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[27]\); - - \r.wb.addr_RNO_2[29]\ : AND2 - port map(A => N_261, B => \addr_1_1_iv_0_0[29]\, Y => - \addr_1_1_iv_0_1[29]\); - - \r.stpend_RNIQH21992\ : OR2B - port map(A => dstate_tr22_15_a2_1_1_0, B => N_3583, Y => - dstate_tr22_15_a2_1); - - \r.dstate_RNI29EH[1]\ : OR2 - port map(A => \dstate[1]\, B => mexc_0_sqmuxa, Y => - mexc_0_sqmuxa_0); - - \r.dstate_i_RNID1NU1[8]\ : AO1B - port map(A => \vmask_0_1_2_o3_0_a2_0[3]\, B => - \dstate_i[8]\, C => N_348, Y => \dstate_i_RNID1NU1[8]\); - - \r.mmctrl1.ctxp[20]\ : DFN1E1 - port map(D => maddress(22), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[20]\); - - \r.wb.data2_RNI0S032[14]\ : AOI1B - port map(A => \data2[14]\, B => rdatav_012_0, C => - \dcramo_m[110]\, Y => \rdatav_0_1_0_iv_0[14]\); - - \r.mmctrl1wr\ : DFN1 - port map(D => mmctrl1wr_RNO, CLK => lclk_c, Q => mmctrl1wr); - - \r.read_RNIAQK32\ : NOR2B - port map(A => \N_425\, B => hrdata_0_13, Y => \mcdo_m[13]\); - - \r.dstate_RNIOE146[7]\ : NOR2A - port map(A => rdatav_0_6_sqmuxa_3, B => \dstate[7]\, Y => - rdatav_0_6_sqmuxa); - - \r.cctrl.dcs_RNO_0[1]\ : MX2C - port map(A => maddress(3), B => \dcs[1]\, S => \N_523\, Y - => N_672); - - \dctrl.un1_eholdn_2_9_0_a2\ : NOR2 - port map(A => N_2938_2, B => N_519, Y => N_3779); - - \r.read_RNI7CD8A\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_18, Y => - \mcdo_m_i[18]\); - - \r.paddress[20]\ : DFN1E1 - port map(D => N_417, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[20]\); - - \r.dstate_RNIDKUIH[1]\ : AO1 - port map(A => \edata[10]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[234]\, Y => \ddatainv_0_1_1_iv_0[10]\); - - \r.dstate_i_0_RNIL7FGFS[8]\ : OR3C - port map(A => N_302, B => N_301, C => N_303, Y => - dstate_i_0_RNIL7FGFS(8)); - - \r.dstate_2[7]\ : DFN1 - port map(D => \dstate_nss[1]\, CLK => lclk_c, Q => - \dstate_2[7]\); - - \r.wb.data2_RNO[27]\ : MX2 - port map(A => edata2_iv_i_0(27), B => hrdata_0_27, S => - \dstate_1[7]\, Y => \data2_1[27]\); - - \r.holdn_RNO_1\ : NOR3B - port map(A => holdn_0_3, B => holdn_1_sqmuxa_3, C => - holdn_1_5, Y => holdn_0_5); - - \r.flush_0_1_RNIBGU5992\ : OR2B - port map(A => maddress(17), B => \N_329\, Y => N_3893); - - \r.dstate_ns_i_a4_i_o2_2[0]\ : OR2B - port map(A => N_3799, B => N_537, Y => N_665); - - \r.dstate_RNICPGHH[1]\ : AO1 - port map(A => \edata[12]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[236]\, Y => \ddatainv_0_1_1_iv_0[12]\); - - \r.req_RNO_2\ : NOR3B - port map(A => \req_0_sqmuxa[0]\, B => N_485, C => - \dstate_i_0[8]\, Y => req_0_sqmuxa_3_1); - - \r.dstate_i_2_RNITQRS1_3[8]\ : NOR2B - port map(A => maddress(8), B => N_3321, Y => N_3344_i_0_0); - - \r.vaddr_RNIJIIC[19]\ : MX2 - port map(A => maddress(19), B => \vaddr[19]\, S => - \dstate_i_2[8]\, Y => data(19)); - - \r.dstate_i_0_RNIVIRH6[8]\ : NOR2B - port map(A => \vmask_0_5[4]\, B => \dstate_RNIR2CO3[4]\, Y - => N_128_1); - - \r.dstate_i_0_RNIMF0H7[8]\ : OR2A - port map(A => addr_0_sqmuxa_1, B => addr_2_sqmuxa, Y => - N_2164); - - \r.valid_0_RNIS2NB[4]\ : NOR2B - port map(A => \valid_0[4]\, B => hit, Y => - \vmask_0_5_1_a4_0_0[4]\); - - \r.mmctrl1.ctx_0_0[0]\ : DFN1 - port map(D => \ctx_RNIB8BR[0]\, CLK => lclk_c, Q => - \ctx_0[0]\); - - \r.wb.addr[9]\ : DFN1 - port map(D => \addr_1[9]\, CLK => lclk_c, Q => \address[9]\); - - \r.vaddr_RNIGUHC[27]\ : MX2 - port map(A => maddress(27), B => \vaddr[27]\, S => - \dstate_i_1[8]\, Y => data(27)); - - \r.dstate_RNI4NKBG[1]\ : AOI1B - port map(A => \edata[19]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[243]\, Y => \ddatainv_0_1_0_iv_0[19]\); - - \r.wb.data1[8]\ : DFN1E0 - port map(D => N_8, CLK => lclk_c, E => data1_0_sqmuxa, Q - => data(8)); - - \r.dstate_0_RNI2VNA[7]\ : NOR2A - port map(A => \dstate_0[7]\, B => N_508, Y => mexc_0_sqmuxa); - - \r.read_RNICAQK41\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[16]\, B => - \mcdo_m_i[16]\, C => \ddatainv_0_1_0_iv_1[16]\, Y => - read_RNICAQK41); - - \r.mmctrl1.e_0_0_RNI2K342\ : OR3B - port map(A => N_557, B => cctrlwr19_2_0_a2_1_1_0, C => - cctrlwr13, Y => cctrlwr19_2_0_a2_1_1); - - \r.valid_0_RNO[1]\ : AO1B - port map(A => dataout_0(1), B => N_88, C => - \valid_0_1_1_0[1]\, Y => \valid_0_1[1]\); - - \r.read_RNIC70OF1\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[20]\, B => - \mcdo_m_i[20]\, C => \ddatainv_0_1_0_iv_1[20]\, Y => - read_RNIC70OF1); - - \r.dstate_2_RNILLB4J[7]\ : OR2B - port map(A => \dstate_2[7]\, B => N_262_0, Y => - \mcdo_m_0[20]\); - - \r.stpend_RNINHS9\ : NOR2 - port map(A => read_1, B => stpend, Y => N_3089_7); - - \r.wb.data2_RNI7BOB[24]\ : OR2B - port map(A => \data2[24]\, B => rdatav_012_0, Y => - \data2_m[24]\); - - \v.mmctrl1.ctxp_1_sqmuxa_2\ : NOR2 - port map(A => \addr[9]\, B => \addr[10]\, Y => e_0_sqmuxa_2); - - \r.wb.addr_RNO_3[5]\ : OR2B - port map(A => un1_m0_2_6, B => addr_1_sqmuxa, Y => N_288); - - \r.dstate_tr22_15_a2_6_i_o2\ : OR2A - port map(A => N_549, B => asi(2), Y => N_595); - - \r.wb.lock_RNO_2\ : OR3A - port map(A => \dstate_RNI5GFM4[5]\, B => N_56, C => - lock_1_iv_0_a2_0, Y => N_3553); - - \r.wb.addr_RNO_4[31]\ : MX2 - port map(A => \paddress[31]\, B => \addr[31]\, S => N_484, - Y => N_544); - - \r.wbinit_RNIA7FN3\ : OR2B - port map(A => dwrite_1_sqmuxa, B => N_487, Y => - addr_0_sqmuxa); - - \r.dstate_i_0_RNIE3RBE91[8]\ : OR3B - port map(A => N_3835, B => dataout_0(3), C => - \dstate_i_0[8]\, Y => N_305); - - \r.stpend_RNII1UI\ : OR2B - port map(A => stpend, B => N_487, Y => - ready_0_sqmuxa_0_a2_0_a2_0); - - \r.dstate_RNI4AS1D[1]\ : AO1 - port map(A => \edata[3]\, B => ddatainv_0_3_sqmuxa, C => - \dcramo_m[227]\, Y => \ddatainv_0_1_1_iv_0[3]\); - - \r.mmctrl1.ctx_0_0[5]\ : DFN1 - port map(D => \ctx_0_0_RNI91UO[5]\, CLK => lclk_c, Q => - \ctx_0[5]\); - - \r.dstate_0_RNI1JGE7_3[2]\ : AOI1B - port map(A => diagdata_21, B => \dstate_0[2]\, C => - \dcramo_m_0[245]\, Y => \rdatav_0_1_1_iv_5[21]\); - - \r.wb.data2_RNI3RN44[26]\ : NOR3C - port map(A => \dcramo_m[122]\, B => \data2_m[26]\, C => - \mmudco_m[69]\, Y => \rdatav_0_1_0_iv_1[26]\); - - \r.dstate_RNO_4[5]\ : OR3 - port map(A => N_3514, B => ready, C => - \dstate_ns_0_8_tz[3]\, Y => \dstate_RNO_4[5]\); - - \r.dstate_RNIH3CFG[1]\ : MX2 - port map(A => maddress(26), B => edata2_iv_i_0(26), S => - edata_0_sqmuxa_i, Y => \edata[26]\); - - \r.wb.data1_RNO[17]\ : MX2A - port map(A => N_2115, B => maddress(17), S => - req_0_sqmuxa_1, Y => \data1_1[17]\); - - \r.holdn_RNIQ28U\ : OR3A - port map(A => maddress(1), B => N_3763, C => maddress(0), Y - => N_3626); - - \r.wb.data2_RNITQN44[23]\ : NOR3C - port map(A => \dcramo_m[119]\, B => \data2_m[23]\, C => - \mmudco_m[66]\, Y => \rdatav_0_1_0_iv_1[23]\); - - \r.valid_0_RNO_0[4]\ : MX2C - port map(A => dataout_0(4), B => N_128_1, S => twrite_14, Y - => N_2364); - - \r.mmctrl1.ctxp_RNIULJ12[15]\ : OR2B - port map(A => \ctxp[15]\, B => N_3344_i_0, Y => - \ctxp_m[15]\); - - \dctrl.twrite_14_iv_0_a2_a0_RNIKNNUB1\ : NOR3 - port map(A => flush_RNICQGM51, B => flush_RNITKH06, C => - twrite_14_iv_0_a2_a0, Y => N_3322); - - \r.wb.addr_RNO_2[31]\ : OR2B - port map(A => maddress(31), B => addr_2_sqmuxa, Y => N_3652); - - \r.nomds\ : DFN1 - port map(D => nomds_RNO, CLK => lclk_c, Q => nomds); - - \r.dstate[5]\ : DFN1 - port map(D => \dstate_nss[3]\, CLK => lclk_c, Q => - \dstate[5]\); - - \r.wb.data2_RNI2S032[16]\ : NOR2B - port map(A => \data2_m[16]\, B => \dcramo_m[112]\, Y => - \rdatav_0_1_1_iv_0[16]\); - - \r.wb.addr_RNO_0[12]\ : OA1 - port map(A => \data[12]\, B => N_2709_i_0, C => - addr_1_sqmuxa_2_0, Y => \addr_1_1_iv_0_a3_2_0[12]\); - - \r.mmctrl1.nf_RNI57J42\ : OR2B - port map(A => \nf\, B => miscdata_0_sqmuxa, Y => nf_m); - - \r.dstate_i_0_RNIJU6E[8]\ : NOR2 - port map(A => asi(3), B => \dstate_i_0[8]\, Y => - \dstate_ns_i_a4_i_a2_7_0[0]\); - - \r.xaddress_RNIQF6M2_4[0]\ : NAND2 - port map(A => N_2088, B => dataout_0(31), Y => - \dcramo_m_i[255]\); - - \r.wb.data2_RNINR3M3[2]\ : NOR3C - port map(A => \dcramo_m[410]\, B => \data2_m[2]\, C => - \dcramo_m[98]\, Y => \rdatav_0_1_0_iv_1[2]\); - - \r.dstate_2_RNIN4AJL[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[8]\, B => - \rdatav_0_1_0_iv_2[8]\, C => \mcdo_m_0[8]\, Y => data_0_8); - - \r.dstate_i_RNI25CU792[8]\ : OR2 - port map(A => N_561, B => \N_121\, Y => N_3604); - - \r.wb.data1_RNO[9]\ : MX2A - port map(A => N_2107, B => maddress(9), S => req_0_sqmuxa_1, - Y => \data1_1[9]\); - - \r.wbinit_RNIE3VB\ : NOR2B - port map(A => wbinit, B => \dstate[4]\, Y => - \dstate_ns_i_a4_i_a2_15_0[0]\); - - \r.vaddr_RNI4AHC[13]\ : MX2 - port map(A => maddress(13), B => \vaddr[13]\, S => - \dstate_i_1[8]\, Y => data(13)); - - \r.vaddr[1]\ : DFN1E1 - port map(D => maddress(1), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[1]\); - - \r.flush_0_1_RNICKU5992\ : NOR2B - port map(A => maddress(25), B => \N_329\, Y => N_236); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.dstate_ns_i_a4_i_o2_6[0]\ : NOR2A - port map(A => \dcs[0]\, B => lock, Y => N_501); - - \r.dstate_i_2_RNIDAC82[8]\ : OR3B - port map(A => dstate_tr22_15_a2_2_m8_i_a5_0_0, B => asi(4), - C => N_526, Y => dstate_tr22_15_a2_2_m8_i_0_tz); - - \r.read_RNISLPNU\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[18]\, B => - \mcdo_m_i[18]\, C => \ddatainv_0_1_0_iv_1[18]\, Y => - read_RNISLPNU); - - \r.valid_0_RNO_2[7]\ : OR3 - port map(A => N_3286_1, B => flush_i, C => \N_3254_0\, Y - => N_3286); - - \r.vaddr[0]\ : DFN1E1 - port map(D => maddress(0), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[0]\); - - \r.flush_RNIMB2T1\ : OR2B - port map(A => flush_0, B => rdatav_0_0_sqmuxa, Y => flush_m); - - \r.ready_RNIAJ1U1\ : OR2A - port map(A => ready, B => N_508, Y => N_510); - - \r.wb.data2_RNIIJT36[8]\ : NOR3C - port map(A => \rdatav_0_1_0_iv_0[8]\, B => \mmudco_m[44]\, - C => \ctxp_m[6]\, Y => \rdatav_0_1_0_iv_2[8]\); - - \r.wb.data1_RNO_0[14]\ : MX2C - port map(A => edata2_0_iv(14), B => \data2[14]\, S => - N_3331_0, Y => N_2112); - - \r.dstate_RNIMHBNC[1]\ : MX2 - port map(A => maddress(23), B => edata2_0_iv(23), S => - edata_0_sqmuxa_i_0, Y => \edata[23]\); - - \r.wb.addr_RNO_3[23]\ : OR2B - port map(A => \address[23]\, B => N_514, Y => N_3889); - - \r.vaddr_RNI22HC[20]\ : MX2 - port map(A => maddress(20), B => \vaddr[20]\, S => - \dstate_i_1[8]\, Y => data(20)); - - \r.dstate_RNO_16[4]\ : NOR2B - port map(A => asi(4), B => asi(1), Y => - dstate_tr16_13_0_0_a2_0_0); - - \r.dstate_RNISEIMC[1]\ : MX2 - port map(A => maddress(13), B => edata2_0_iv(13), S => - edata_0_sqmuxa_i_0, Y => \edata[13]\); - - \r.wb.data2_RNISLJ16[24]\ : NOR3B - port map(A => \mmudco_m[67]\, B => \rdatav_0_1_0_iv_0[24]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_2[24]\); - - \r.read_RNIAQJ831\ : OR3 - port map(A => \mcdo_m[9]\, B => \edata_m_1[1]\, C => - \ddatainv_0_1_1_iv_0[9]\, Y => read_RNIAQJ831); - - \r.dstate_RNI2MBNC[1]\ : MX2 - port map(A => maddress(19), B => edata2_0_iv(19), S => - edata_0_sqmuxa_i, Y => \edata[19]\); - - \r.read_RNIC9FCH\ : NOR2B - port map(A => \N_425\, B => hrdata_0_15, Y => \mcdo_m[15]\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNITIN93\ : OR2A - port map(A => dcs_1_i_s_0_0, B => N_527, Y => N_102); - - \r.mmctrl1.ctxp[16]\ : DFN1E1 - port map(D => maddress(18), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[16]\); - - \r.dstate_i_2_RNISK8N1_5[8]\ : OR2B - port map(A => dataout_0(22), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[122]\); - - \v.mmctrl1.e_0_sqmuxa_RNO\ : NOR2A - port map(A => mmctrl1wr, B => \addr[8]\, Y => e_0_sqmuxa_0); - - \r.hit_RNIQDAT1\ : NOR2B - port map(A => twrite_11_m_0_a2_0_2, B => - twrite_11_m_0_a2_0_1, Y => hit_1_iv_0_a2_0); - - \dctrl.un30_m_en\ : OR2B - port map(A => maddress(8), B => un30_m_en_0, Y => un30_m_en); - - \r.wb.data1[4]\ : DFN1E0 - port map(D => \data1_1[4]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(4)); - - \r.wb.addr_RNO_5[12]\ : MX2 - port map(A => \paddress[12]\, B => \addr[12]\, S => N_484_0, - Y => N_676); - - \r.dstate_i_2_RNIM5U12[8]\ : OR2B - port map(A => un1_m0_2_41, B => miscdata_3_sqmuxa, Y => - \mmudco_m[42]\); - - \r.dstate_RNIKMHIJ[1]\ : AOI1B - port map(A => \edata[25]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[249]\, Y => \ddatainv_0_1_0_iv_0[25]\); - - \r.wb.addr_RNO_4[18]\ : MX2 - port map(A => \paddress[18]\, B => \addr[18]\, S => N_484_0, - Y => N_3841); - - \r.vaddr[22]\ : DFN1E1 - port map(D => maddress(22), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[22]\); - - \r.nomds_RNO_2\ : NOR3B - port map(A => \req\, B => \dstate_i_0[8]\, C => N_508, Y - => dstate_15_1); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_13\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_9, B => - eaddress_23, C => eaddress_19, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_13); - - \r.wb.addr_RNO[3]\ : AO1B - port map(A => maddress_0_2, B => N_2164, C => - \addr_1_1_iv_0_2[3]\, Y => \addr_1[3]\); - - \r.wb.lock_RNO\ : OR3C - port map(A => N_3553, B => N_3554, C => N_3555, Y => lock_1); - - \r.mmctrl1.e_RNIKN3D\ : NOR2 - port map(A => asi(3), B => \e\, Y => e_RNIKN3D); - - \r.xaddress_RNIEMDM4[11]\ : MX2 - port map(A => maddress(11), B => \addr[11]\, S => - un1_taddr_1_sqmuxa, Y => N_2238); - - \un1_v.cctrlwr19_2_0_o2_7_0\ : NOR2A - port map(A => N_3798, B => N_206_1, Y => - cctrlwr19_2_0_o2_7_0); - - \r.wb.addr_RNO_3[25]\ : AOI1B - port map(A => \paddress[25]\, B => N_2165_0, C => - \mmudco_m[27]\, Y => \addr_1_1_iv_0[25]\); - - \r.xaddress[29]\ : DFN1E1 - port map(D => maddress(29), CLK => lclk_c, E => N_486, Q - => \addr[29]\); - - \r.flush_RNIGUM2OH3\ : AO1C - port map(A => N_349, B => \vmask_0_5[4]\, C => - \vmask_0_1_2_0[4]\, Y => flush_RNIGUM2OH3); - - \r.wb.addr_RNO_4[29]\ : AOI1B - port map(A => N_2165_0, B => N_546, C => N_262, Y => - \addr_1_1_iv_0_0[29]\); - - \r.valid_0_RNIP2NB[1]\ : NOR2B - port map(A => \valid_0[1]\, B => hit, Y => N_95); - - \r.mmctrl1.ctx_0_0[6]\ : DFN1 - port map(D => \ctx_RNIN0CR[6]\, CLK => lclk_c, Q => - \ctx_0[6]\); - - \r.xaddress[25]\ : DFN1E1 - port map(D => maddress(25), CLK => lclk_c, E => N_486, Q - => \addr[25]\); - - \r.cctrl.ics_RNIIQS04[1]\ : AOI1B - port map(A => un1_m0_2_36, B => miscdata_3_sqmuxa, C => - N_3231, Y => \rdatav_0_1_0_iv_i_a4_3[1]\); - - \dctrl.vmaskraw_1_i_o2_i_a2_0[1]\ : NAND2 - port map(A => N_559, B => \vmaskraw_1_i_o2_i_a2_0_0[1]\, Y - => N_3654); - - \r.wb.data1[22]\ : DFN1E0 - port map(D => \data1_1[22]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_0_22); - - \r.dstate_1_RNI5ICU7[7]\ : OR2B - port map(A => \dstate_1[7]\, B => hrdata_24, Y => - \mcdo_m_0[29]\); - - \un1_r.faddr_I_13\ : XOR2 - port map(A => N_17, B => \faddr[3]\, Y => I_13_5); - - \r.wb.addr_RNO_1[9]\ : OR2B - port map(A => un1_m0_2_10, B => addr_1_sqmuxa, Y => - \mmudco_m[11]\); - - \r.flush_0_1_RNIAGU5992\ : OR2B - port map(A => maddress(16), B => \N_329\, Y => N_242); - - \r.dstate_i_2_RNIP3SSB92[8]\ : AOI1B - port map(A => dstate_tr22_15_a2_2_m8_i_0_tz, B => N_3576, C - => N_3583, Y => dstate_tr22_15_a2_2_m8_i_0_0); - - \r.wb.data1_RNO[5]\ : NOR3 - port map(A => N_3364, B => N_3365, C => N_3366, Y => N_21); - - \r.dstate_RNO_5[1]\ : AO1 - port map(A => N_3569, B => N_90, C => dstate_tr22_15_a2_1, - Y => \dstate_RNO_5[1]\); - - \r.vaddr[6]\ : DFN1E1 - port map(D => maddress(6), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[6]\); - - \r.wb.addr_RNO_0[11]\ : OR2B - port map(A => maddress(11), B => addr_2_sqmuxa, Y => N_282); - - \r.mmctrl1.ctx_0_0_RNID9UO[7]\ : NOR2B - port map(A => rst, B => N_2670, Y => \ctx_0_0_RNID9UO[7]\); - - \r.dstate_RNI65K2G[1]\ : MX2 - port map(A => maddress(24), B => edata2_iv_i_0(24), S => - edata_0_sqmuxa_i_0, Y => \edata[24]\); - - \r.dstate_i_RNI1701O92[8]\ : OR2A - port map(A => edata2_iv_i_0(29), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_93); - - \r.dstate_i_2_RNIJB842[8]\ : OR2B - port map(A => un1_m0_2_54, B => miscdata_4_sqmuxa, Y => - \mmudco_m[55]\); - - \r.wb.addr_RNO_1[18]\ : OR2B - port map(A => maddress(18), B => addr_2_sqmuxa_0, Y => - N_187); - - \r.wb.addr_RNO[0]\ : OR3C - port map(A => \addr_1_1_iv_1[0]\, B => \mmudco_m[2]\, C => - \dci_m[8]\, Y => \addr_1[0]\); - - \r.burst_RNO_6\ : OR2A - port map(A => req_2_sqmuxa_1_0, B => un47_m_en, Y => - burst_1_m8_i_o5_0); - - \r.dstate_i_RNITKBIK92[8]\ : OR2A - port map(A => edata2_0_iv(20), B => \N_3254_0\, Y => N_156); - - \r.hit_RNO_0\ : AO1 - port map(A => \cache\, B => N_84, C => N_486_0, Y => N_9); - - \r.flush_0_1_RNI8GU5992\ : OR2B - port map(A => maddress(14), B => \N_329\, Y => N_239); - - \r.ready_RNO_1\ : OA1B - port map(A => N_511, B => ready_0_sqmuxa_0_a2_1, C => N_572, - Y => ready_0_sqmuxa_0_0); - - \r.dstate_RNO_13[4]\ : NOR3C - port map(A => N_395, B => N_3505_i, C => N_16886_tz_tz, Y - => dstate_ns_0_2064_1); - - \r.mmctrl1.e_RNITD9PLG3\ : OR2A - port map(A => N_490, B => N_564, Y => N_3810); - - \r.dstate_i_0_RNI764QAD2[8]\ : OA1A - port map(A => N_611, B => \dstate_i_0[8]\, C => - \dstate_ns_i_a4_i_8[0]\, Y => \dstate_ns_i_a4_i_9[0]\); - - \r.cctrl.ics[0]\ : DFN1 - port map(D => N_25, CLK => lclk_c, Q => \ics[0]\); - - \r.wb.data1_RNO_0[16]\ : MX2C - port map(A => edata2_0_iv(16), B => \data2[16]\, S => - N_3331, Y => N_2114); - - \r.dstate_RNO_0[0]\ : AOI1B - port map(A => \dstate_ns_0_0_a2_0_3[8]\, B => - un1_m0_2_0(35), C => N_135, Y => \dstate_ns_0_0_0[8]\); - - \r.xaddress_RNICIF9O[1]\ : AOI1B - port map(A => \edata[14]\, B => ddatainv_0_4_sqmuxa, C => - \edata_m_4_i[6]\, Y => \ddatainv_0_1_0_iv_1[30]\); - - \r.wb.data1[9]\ : DFN1E0 - port map(D => \data1_1[9]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(9)); - - \r.dstate_i_2_RNISK8N1_1[8]\ : OR2B - port map(A => dataout(32), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[412]\); - - un1_taddr_1_sqmuxa_0_o2 : AO1C - port map(A => read_1, B => enaddr, C => hold_0, Y => N_582); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_11\ : NOR3B - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_3, B => - vaddr_1_sqmuxa_0_a2_4_m1_e_5, C => eaddress_15, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_11); - - \r.su\ : DFN1E1 - port map(D => msu, CLK => lclk_c, E => N_486_0, Q => su_0); - - \r.dstate_RNIVC9NC[1]\ : MX2 - port map(A => maddress(16), B => edata2_0_iv(16), S => - edata_0_sqmuxa_i_0, Y => \edata[16]\); - - \r.dstate[1]\ : DFN1 - port map(D => \dstate_nss[7]\, CLK => lclk_c, Q => - \dstate[1]\); - - \r.mmctrl1.ctxp[4]\ : DFN1E1 - port map(D => maddress(6), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[4]\); - - \r.size_RNIC6U21[1]\ : OA1C - port map(A => maddress(1), B => N_3757, C => N_3768, Y => - N_574); - - \r.dstate_RNI2KLDD[1]\ : OR2B - port map(A => ddatainv_0_4_sqmuxa, B => - \dstate_RNII450C[1]\, Y => \edata_m_0_i[8]\); - - \r.dstate_0_RNIIC256_3[7]\ : OR2B - port map(A => dataout(23), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[247]\); - - \r.dstate_0_RNIQSEE4[7]\ : AO1C - port map(A => burst_0_sqmuxa, B => \dstate_0[7]\, C => - data2_0_sqmuxa_1, Y => N_2165_0); - - \r.cctrl.dcs_RNO[0]\ : NOR2A - port map(A => rst, B => N_671, Y => \dcs_RNO[0]\); - - \r.dstate_i_2_RNIO4022[8]\ : OR2B - port map(A => un1_m0_2_38, B => miscdata_3_sqmuxa, Y => - N_3399); - - \dctrl.0.un1_dci_1_0\ : XNOR2 - port map(A => dataout_0(9), B => maddress(13), Y => - un1_dci_1_i); - - \r.wb.data1[18]\ : DFN1E0 - port map(D => \data1_1[18]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_0_18); - - \r.xaddress_RNIJH2O2_1[0]\ : NOR2B - port map(A => dataout(13), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[237]\); - - \r.wb.addr_RNO_5[11]\ : OR2B - port map(A => \un1_m0_2[87]\, B => addr_1_sqmuxa_2, Y => - N_284); - - \r.hit_RNIUCU42\ : OR3B - port map(A => \dstate[4]\, B => un1_m0_2_0(35), C => hit, Y - => N_3752); - - \dctrl.un19_eholdn_3_0_a2_0_a2\ : NOR2 - port map(A => N_537, B => N_490, Y => un19_eholdn_3); - - \r.wb.addr_RNO_4[17]\ : MX2 - port map(A => \paddress[17]\, B => \addr[17]\, S => N_484_0, - Y => N_553); - - \r.holdn_RNIPU251_0\ : OR2A - port map(A => N_534, B => maddress(3), Y => N_3662); - - \r.wb.data1[6]\ : DFN1E0 - port map(D => \data1_1[6]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(6)); - - \r.paddress[16]\ : DFN1E1 - port map(D => data_RNIKU1T4(16), CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress_0[16]\); - - \r.xaddress_RNIJH2O2_8[0]\ : NOR2B - port map(A => dataout(1), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[225]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_9\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_2, B => eaddress_2, - C => eaddress_24, Y => vaddr_1_sqmuxa_0_a2_4_m1_e_9); - - \r.wb.addr_RNO_2[18]\ : AOI1B - port map(A => N_3841, B => N_2165_0, C => N_189, Y => - \addr_1_1_iv_0_0[18]\); - - \r.stpend_RNITG0D5\ : NOR2A - port map(A => read_1, B => burst_0_sqmuxa_2, Y => - \un1_dci_5[0]\); - - \r.wb.addr_RNO_0[28]\ : OA1 - port map(A => \data[28]\, B => LVL_RNIT69H911(0), C => - addr_1_sqmuxa_2_0, Y => \addr_1_1_iv_0_a3_1_0[28]\); - - \r.dstate_i_RNIS0039J[8]\ : OR2B - port map(A => \dstate_i_RNII68N892_0[8]\, B => N_3246, Y - => N_3248); - - \r.wb.addr_RNO_1[6]\ : NOR3C - port map(A => N_3733, B => N_3628, C => N_3732, Y => - \addr_1_1_iv_0_1[6]\); - - \r.dstate_RNO_0[5]\ : NOR3C - port map(A => \dstate_ns_0_7_i[3]\, B => \dstate_ns_0_1[3]\, - C => \dstate_RNO_4[5]\, Y => \dstate_ns_0_6[3]\); - - \r.dstate_RNIS3GB3_0[6]\ : OR2A - port map(A => \dstate[6]\, B => N_506, Y => N_3707); - - \r.dstate_i_2_RNISK8N1_0[8]\ : OR2B - port map(A => dataout(35), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[415]\); - - \r.wb.lock_RNO_0\ : NOR3C - port map(A => N_86, B => stpend_0_sqmuxa, C => - \dstate_RNI5GFM4[5]\, Y => lock_2_sqmuxa); - - \r.dstate_tr22_15_a2_2_0_i_o2\ : OR2B - port map(A => size_1_d0, B => size_0_0, Y => N_507); - - \r.dstate_i_RNIHNLHK92[8]\ : OR2A - port map(A => edata2_0_iv(14), B => - \dstate_i_RNII68N892_0[8]\, Y => \dci_m[86]\); - - \r.dstate_i_2_RNIRB942[8]\ : OR2B - port map(A => un1_m0_2_62, B => miscdata_4_sqmuxa, Y => - \mmudco_m[63]\); - - \r.dstate_RNO_6[4]\ : OR3 - port map(A => dstate_tr16_13_0_0_a2_0, B => N_3499, C => - N_3514, Y => \dstate_RNO_6[4]\); - - \r.dstate_0_RNIIC256_4[7]\ : OR2B - port map(A => dataout(13), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[237]\); - - \r.wb.addr_RNO_1[3]\ : AOI1B - port map(A => \dstate_RNIP22L4[7]\, B => N_675, C => N_294, - Y => \addr_1_1_iv_0_0[3]\); - - \r.mmctrl1.pso\ : DFN1 - port map(D => pso_RNO, CLK => lclk_c, Q => pso); - - \r.dstate_RNIGRE8D[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_1, Y => mcdo_m_0_5); - - \r.xaddress_RNIV3V9992[22]\ : OR2B - port map(A => \addr[22]\, B => \N_330\, Y => N_3864); - - \r.dstate_RNIHILB6_4[7]\ : OR2B - port map(A => dataout(20), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[244]\); - - \r.wb.addr_RNO_1[17]\ : OR2B - port map(A => maddress(17), B => addr_2_sqmuxa_0, Y => - N_3640); - - \dctrl.twrite_14_iv_0_a2_a0\ : AND2 - port map(A => un1_addout_13_i, B => twrite_14_iv_0_a2_a0_4, - Y => twrite_14_iv_0_a2_a0); - - \r.wb.addr[1]\ : DFN1 - port map(D => \addr_1[1]\, CLK => lclk_c, Q => \address[1]\); - - \r.dstate_i_2_RNI3KVJ1_2[8]\ : NOR2A - port map(A => N_3253_i, B => N_526, Y => - rdatasel_1_sqmuxa_1_0); - - \dctrl.v.wb.addr_1_1_iv_0_a2_2[31]\ : NAND2 - port map(A => N_514, B => \address[31]\, Y => N_3715); - - \r.mmctrl1.ctx_RNIIRMN[6]\ : MX2 - port map(A => \ctx[6]\, B => maddress(6), S => ctx_1_sqmuxa, - Y => N_2669); - - \r.dstate_0_RNI2DT77[2]\ : AOI1B - port map(A => diagdata_23, B => \dstate_0[2]\, C => - \dcramo_m_0[247]\, Y => \rdatav_0_1_0_iv_3[23]\); - - \r.wb.addr_RNO[17]\ : AO1B - port map(A => un1_m0_2_92, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[17]\, Y => \addr_1[17]\); - - \r.nomds_RNO\ : NOR2B - port map(A => rst, B => N_2596, Y => nomds_RNO); - - \r.flush_RNILOUG8\ : OR3B - port map(A => un157_m_en, B => holdn_1_5, C => flush_i, Y - => un157_m_en_m); - - \r.xaddress_RNO[1]\ : MX2 - port map(A => \addr[1]\, B => maddress(1), S => N_486_0, Y - => N_709); - - \r.holdn\ : DFN1 - port map(D => holdn_RNO_0, CLK => lclk_c, Q => \hold\); - - \r.dstate_RNI3ICLD[1]\ : OR2B - port map(A => \edata[21]\, B => ddatainv_0_6_sqmuxa, Y => - \edata_m_i[21]\); - - \r.vaddr[20]\ : DFN1E1 - port map(D => maddress(20), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[20]\); - - \r.xaddress_RNI54V9992[28]\ : OR2B - port map(A => \addr[28]\, B => \N_330\, Y => N_3846); - - \r.wb.addr_RNO_6[2]\ : OR2B - port map(A => \un1_m0_2[78]\, B => addr_1_sqmuxa_2, Y => - N_318); - - \r.dstate_i_2_RNISK8N1_20[8]\ : OR2B - port map(A => dataout_0(27), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[127]\); - - \r.xaddress_RNIQF6M2_6[0]\ : OR2B - port map(A => dataout(23), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[247]\); - - \r.wb.data1_RNO_0[3]\ : NOR3A - port map(A => N_3331_0, B => req_0_sqmuxa_1_0, C => - \data2[3]\, Y => N_3360); - - \r.dstate_RNO_6[1]\ : OR3A - port map(A => dstate_tr22_15_0_a2_1, B => N_2994_6, C => - N_581_i, Y => N_3086_i); - - \r.wb.data2_RNO[23]\ : MX2 - port map(A => edata2_0_iv(23), B => hrdata_0_23, S => - \dstate_1[7]\, Y => \data2_1[23]\); - - \r.wb.addr_RNO[13]\ : AO1B - port map(A => N_694, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[13]\, Y => \addr_1[13]\); - - \r.mmctrl1.ctx[1]\ : DFN1 - port map(D => \ctx_0_0_RNIQIPQ[1]\, CLK => lclk_c, Q => - ctx(1)); - - \r.xaddress_RNIL5KB1_0[0]\ : OA1B - port map(A => N_3763, B => maddress(0), C => N_3782, Y => - \ddatainv_0_1_3_0[0]\); - - \r.wb.addr_RNO_5[24]\ : OR2B - port map(A => N_421_0, B => addr_1_sqmuxa_0, Y => N_3740); - - \r.valid_0_RNI6F4J[0]\ : OR3C - port map(A => hit, B => \valid_0[0]\, C => \dstate_i_0[8]\, - Y => N_345); - - \r.dstate_i_0_RNIEGV07[8]\ : OR2 - port map(A => \dstate_i_0[8]\, B => un1_eholdn_2, Y => - burst_2_sqmuxa_2); - - \r.cache_RNO_0\ : NOR2 - port map(A => \e_0\, B => N_587, Y => N_3674); - - \dctrl.twrite_14_iv_0_a2_a0_RNO_0\ : NOR3A - port map(A => twrite_14_iv_0_a2_a0_1, B => me_nullify2_1_2, - C => nullify2_0_sqmuxa, Y => twrite_14_iv_0_a2_a0_3); - - \r.xaddress_RNI4CRK4[7]\ : MX2C - port map(A => maddress(7), B => \addr[7]\, S => - un1_taddr_1_sqmuxa, Y => N_2234); - - \r.wb.data2[26]\ : DFN1E1 - port map(D => \data2_1[26]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[26]\); - - \r.dstate_1[7]\ : DFN1 - port map(D => \dstate_nss[1]\, CLK => lclk_c, Q => - \dstate_1[7]\); - - \r.cctrl.ics_RNO_2[1]\ : OAI1 - port map(A => \N_523\, B => maddress_0_0, C => rst, Y => - \ics_0_i_0[1]\); - - \r.vaddr[4]\ : DFN1E1 - port map(D => maddress(4), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[4]\); - - \r.mmctrl1.ctx_RNI5HIP[3]\ : MX2 - port map(A => \ctx[3]\, B => maddress_0_2, S => - ctx_1_sqmuxa, Y => N_2666); - - \r.wb.data2_RNO[0]\ : MX2A - port map(A => edata2_0_iv(0), B => hrdata_0_0, S => - \dstate_1[7]\, Y => \data2_1[0]\); - - \r.wb.addr_RNO_2[17]\ : AOI1B - port map(A => N_2165_0, B => N_553, C => N_3722, Y => - \addr_1_1_iv_0_0[17]\); - - \r.dstate_i_2_RNISK8N1_16[8]\ : OR2B - port map(A => dataout_0(3), B => rdatasel_1_sqmuxa_1, Y => - N_3401); - - \r.wb.data1_RNO_0[23]\ : MX2C - port map(A => edata2_0_iv(23), B => \data2[23]\, S => - N_3331_0, Y => N_2121); - - \r.wb.addr_RNO_0[27]\ : AOI1B - port map(A => data_1_3_i_a3_6_2, B => LVL_RNIT69H911(0), C - => addr_1_sqmuxa_2_0, Y => \addr_1_1_iv_0_a3_2_0[27]\); - - \r.mmctrl1.ctxp_RNIUPJ12[22]\ : OR2B - port map(A => \ctxp[22]\, B => N_3344_i_0_0, Y => - \ctxp_m[22]\); - - \r.valid_0_RNIR2NB[3]\ : NOR2B - port map(A => \valid_0[3]\, B => hit, Y => - \vmask_0_1_2_o3_0_a2_0[3]\); - - \r.flush2\ : DFN1 - port map(D => lrr_1_sqmuxa, CLK => lclk_c, Q => flush2); - - \r.dstate_tr22_15_a2_6_i_o2_1\ : NOR2B - port map(A => asi(3), B => asi(1), Y => N_549); - - \r.wb.data2_RNI0RRU1[7]\ : NOR2B - port map(A => N_3314, B => \dcramo_m[415]\, Y => - \rdatav_0_1_1_iv_0_0[7]\); - - \r.dstate_tr8_1_8_0_a2_0_0\ : OR2A - port map(A => asi(0), B => asi(4), Y => - dstate_tr8_1_8_0_a2_0); - - \r.dstate_i_2_RNITVLGB92[8]\ : OR2A - port map(A => N_3745, B => N_511, Y => - \dstate_i_2_RNITVLGB92[8]\); - - \r.xaddress_RNI4PQR692[3]\ : OR3B - port map(A => flush_0_sqmuxa_0_o3_i_o2_5, B => - flush_0_sqmuxa_0_o3_i_o2_4, C => nullify, Y => \N_523\); - - \r.wb.data1_RNO[13]\ : MX2A - port map(A => N_2111, B => maddress(13), S => - req_0_sqmuxa_1_0, Y => \data1_1[13]\); - - \r.read_RNIM7KJ8\ : OR2B - port map(A => \N_425_0\, B => hrdata_24, Y => - \mcdo_m_i[29]\); - - \v.mmctrl1.e_0_sqmuxa_RNIQKNL\ : NOR2B - port map(A => rst, B => N_2676, Y => e_0_sqmuxa_RNIQKNL); - - \r.wb.data1[23]\ : DFN1E0 - port map(D => \data1_1[23]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_0_23); - - \r.wb.addr_RNO_4[13]\ : MX2 - port map(A => \paddress[13]\, B => \addr[13]\, S => N_484_0, - Y => N_677); - - \r.dstate_RNI1JGE7_1[2]\ : AOI1B - port map(A => diagdata_25, B => \dstate[2]\, C => - \dcramo_m_0[249]\, Y => \rdatav_0_1_0_iv_3[25]\); - - \r.dstate_i_2_RNISK8N1_2[8]\ : OR2B - port map(A => dataout(31), B => rdatasel_3_sqmuxa, Y => - N_3400); - - \v.wb.addr_0_sqmuxa_2_RNI88Q9P92\ : NOR3C - port map(A => data2_0_sqmuxa, B => burst_1_sqmuxa_1, C => - burst_0_sqmuxa_3, Y => burst_1_sqmuxa_3); - - \r.read_RNI76N8R\ : OR3 - port map(A => \mcdo_m[10]\, B => \edata_m_1[2]\, C => - \ddatainv_0_1_1_iv_0[10]\, Y => read_RNI76N8R); - - \r.wb.data2_RNO[7]\ : MX2A - port map(A => edata2_0_iv(7), B => hrdata_0_7, S => - \dstate[7]\, Y => \data2_1[7]\); - - \r.xaddress_RNI8MTIN[1]\ : AOI1B - port map(A => \edata[0]\, B => ddatainv_0_0_sqmuxa, C => - \edata_m_0_i[8]\, Y => \ddatainv_0_1_0_iv_1[24]\); - - \r.dstate_RNIADAQA[1]\ : NOR2B - port map(A => \edata[3]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[3]\); - - \r.dstate_2_RNI43L1M[7]\ : OR3C - port map(A => \rdatav_0_1_1_iv_3[11]\, B => - \dcramo_m_0[235]\, C => \mcdo_m_0[11]\, Y => data_0_11); - - \r.flush_0_1_RNIGKU5992\ : OR2B - port map(A => maddress(29), B => \N_329\, Y => N_259); - - \r.xaddress_RNIIOTFII[27]\ : AO1 - port map(A => maddress(27), B => \N_329\, C => N_3895, Y - => newtag_1_0_9); - - \r.mmctrl1.ctx_RNIFGBR[2]\ : NOR2B - port map(A => rst, B => N_2665, Y => \ctx_RNIFGBR[2]\); - - \r.mmctrl1.ctxp[0]\ : DFN1E1 - port map(D => maddress(2), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[0]\); - - \r.wb.data2_RNI1RN44[25]\ : NOR3C - port map(A => \dcramo_m[121]\, B => \data2_m[25]\, C => - \mmudco_m[68]\, Y => \rdatav_0_1_0_iv_1[25]\); - - \r.dstate_RNO_1[0]\ : OR3C - port map(A => N_3811, B => \dcs[0]\, C => N_162, Y => - N_3556); - - \un1_r.faddr_I_8\ : NOR2B - port map(A => \faddr[1]\, B => \faddr[0]\, Y => N_20); - - \r.wb.addr_RNO_3[16]\ : OR2B - port map(A => \address[16]\, B => N_514, Y => \addr_m[16]\); - - \r.holdn_RNO_14\ : OR3B - port map(A => \dcs[0]\, B => N_162, C => \req\, Y => N_3605); - - \r.dstate_i_2_RNI3KVJ1_1[8]\ : OR2 - port map(A => un19_eholdn, B => N_526, Y => - rdatasel_4_sqmuxa); - - \r.cache_RNO_2\ : MX2 - port map(A => cache_1, B => cache_0, S => dstate_25, Y => - N_2481); - - \r.dstate_i_2_RNISK8N1_13[8]\ : OR2B - port map(A => dataout_0(8), B => rdatasel_1_sqmuxa_1, Y => - N_159); - - \r.read_RNIGVNMA\ : NOR2B - port map(A => \N_425\, B => hrdata_0_4, Y => \mcdo_m[4]\); - - \r.mmctrl1.ctx_0_0_RNI52QE[6]\ : XA1A - port map(A => \ctx_0[6]\, B => dataout(34), C => ctx_7_i, Y - => ctx_NE_3); - - \r.wb.data2_RNIJVL64[11]\ : NOR3C - port map(A => rdatav_0_1_sqmuxa, B => \data2_m[11]\, C => - rdatav_0_2_sqmuxa, Y => \rdatav_0_1_1_iv_1[11]\); - - \r.mmctrl1.ctxp[15]\ : DFN1E1 - port map(D => maddress(17), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[15]\); - - \r.dstate_i_RNI72JE[8]\ : OR2B - port map(A => edata_0_sqmuxa_1, B => N_3153, Y => N_3151); - - \r.mmctrl1.ctxp[12]\ : DFN1E1 - port map(D => maddress(14), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[12]\); - - \r.xaddress_RNISHIV8[9]\ : NOR3B - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - \addr[9]\, Y => N_3294); - - \r.wb.addr_RNO_0[1]\ : NOR3C - port map(A => \addr_1_1_iv_0[1]\, B => \addr_m[1]\, C => - \mmudco_m[3]\, Y => \addr_1_1_iv_2[1]\); - - \r.paddress[11]\ : DFN1E1 - port map(D => un1_m0_2_12, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[11]\); - - \r.mmctrl1.ctxp_RNI3CR2A[12]\ : AOI1B - port map(A => \ctxp[12]\, B => N_3344_i_0_0, C => - \rdatav_0_1_0_iv_3[14]\, Y => \rdatav_0_1_0_iv_4[14]\); - - \r.wb.addr_RNO_4[15]\ : OR2B - port map(A => \address[15]\, B => N_514, Y => \addr_m[15]\); - - \r.wb.addr_RNO_1[13]\ : OR2B - port map(A => maddress(13), B => addr_2_sqmuxa, Y => N_272); - - \r.dstate_RNIOUJBG[1]\ : AND2 - port map(A => \edata_m_i[18]\, B => \dcramo_m_i[242]\, Y - => \ddatainv_0_1_0_iv_0[18]\); - - \r.dstate_i_2_RNIIOTQ3[8]\ : OR2B - port map(A => rdatav_0_2_sqmuxa, B => rdatav_0_1_sqmuxa, Y - => \rdatav_0_1_6[3]\); - - \r.wb.addr[31]\ : DFN1 - port map(D => \addr_1[31]\, CLK => lclk_c, Q => - \address[31]\); - - \r.read_RNIR1CL_0\ : NOR2 - port map(A => N_3749, B => N_3748, Y => \N_425_0\); - - \r.dstate_RNIFOA94[2]\ : NOR2B - port map(A => rdatav_0_6_sqmuxa_3_0, B => - rdatav_0_6_sqmuxa_3_1, Y => rdatav_0_6_sqmuxa_3_2); - - \r.xaddress_RNIJH2O2_12[0]\ : NOR2B - port map(A => dataout(2), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[226]\); - - \r.nomds_RNO_1\ : AO1B - port map(A => dstate_15_1, B => ready, C => N_3588, Y => - nomds_1); - - \r.mmctrl1.tlbdis\ : DFN1 - port map(D => tlbdis_RNO, CLK => lclk_c, Q => \tlbdis\); - - \r.dstate_i_2_RNISQM12[8]\ : OR2B - port map(A => un1_m0_2_66, B => miscdata_4_sqmuxa, Y => - \mmudco_m[67]\); - - \v.burst_2_sqmuxa_m8_0_a4_0_RNIOK01QJ\ : AOI1 - port map(A => burst_1_sqmuxa_3, B => burst_1_sqmuxa, C => - grant, Y => burst_0_sqmuxa_5); - - \r.stpend\ : DFN1 - port map(D => stpend_RNO, CLK => lclk_c, Q => stpend); - - \r.wb.data2[5]\ : DFN1E1 - port map(D => N_3348, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[5]\); - - \r.wb.data1_RNO[8]\ : MX2 - port map(A => N_3260, B => maddress(8), S => req_0_sqmuxa_1, - Y => N_8); - - \r.stpend_RNI6P41NG3\ : OR3B - port map(A => vaddr_1_sqmuxa_0_a2_a0_0, B => fault_pro, C - => accexc_6, Y => \stpend_RNI6P41NG3\); - - \dctrl.v.burst_3_m_1\ : NOR3A - port map(A => read_0, B => maddress(2), C => N_507, Y => - burst_3_m_1); - - \r.wb.addr_RNO_4[8]\ : MX2 - port map(A => \paddress_0[8]\, B => \addr[8]\, S => N_484, - Y => \paddress[8]\); - - \r.dstate_RNI8KDD[6]\ : OR2 - port map(A => \dstate[6]\, B => \dstate[4]\, Y => N_487); - - \r.dstate_0_RNIG0R21_1[2]\ : NAND2 - port map(A => \dstate_0[2]\, B => diagdata_4, Y => - \ico_m[138]\); - - \r.flush_RNI2N929\ : NOR3A - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - maddress(9), Y => N_3293); - - \r.dstate_tr22_15_o2_7_i_o2\ : OR2A - port map(A => asi(1), B => asi(0), Y => N_505); - - \r.xaddress_RNIJI2O22[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[31]\, B => - \mcdo_m_i[31]\, C => \ddatainv_0_1_0_iv_1[31]\, Y => - xaddress_RNIJI2O22(1)); - - \r.nomds_RNIC8EMD92\ : NOR2 - port map(A => N_511, B => N_503, Y => N_547); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.wb.data2_RNI4VN44[30]\ : AOI1B - port map(A => un1_m0_2_72, B => miscdata_4_sqmuxa, C => - \rdatav_0_1_0_iv_0[30]\, Y => \rdatav_0_1_0_iv_1[30]\); - - \r.ready_RNIVSAH\ : AOI1B - port map(A => ready_0, B => \dstate[5]\, C => stpend, Y => - \dstate_ns_i_a4_i_o2_11_0[0]\); - - \r.xaddress_RNI271B6[4]\ : NOR2A - port map(A => \dstate_RNIR2CO3[4]\, B => \vmask_0_5[2]\, Y - => \vmask_0_6[2]\); - - \r.wb.data2[19]\ : DFN1E1 - port map(D => \data2_1[19]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[19]\); - - \r.vaddr_RNI3IHC[11]\ : MX2 - port map(A => maddress(11), B => \vaddr[11]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[87]\); - - \r.dstate_RNI1JGE7_0[2]\ : AOI1B - port map(A => diagdata_27, B => \dstate[2]\, C => - \dcramo_m_0[251]\, Y => \rdatav_0_1_0_iv_3[27]\); - - \r.mmctrl1.ctxp[26]\ : DFN1E1 - port map(D => maddress(28), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[26]\); - - \r.xaddress_RNIVN7I[1]\ : OR2B - port map(A => \addr[1]\, B => N_3782, Y => N_3625); - - \r.mmctrl1wr_RNICO68\ : NOR2B - port map(A => mmctrl1wr, B => \addr[9]\, Y => - ctx_1_sqmuxa_0_a2_0); - - \r.wb.read_RNIVLJ2D\ : NOR2A - port map(A => grant, B => \read_2\, Y => N_56); - - \r.wb.addr_RNO_1[15]\ : NOR3C - port map(A => \dci_m[23]\, B => \addr_1_1_iv_0[15]\, C => - \addr_m[15]\, Y => \addr_1_1_iv_2[15]\); - - \r.req_RNO_0\ : AOI1B - port map(A => req_0_sqmuxa_3_1, B => N_547, C => req_1_1, Y - => req_1_2); - - \r.xaddress_RNI1CIE2_0[0]\ : OR2B - port map(A => \ddatainv_0_1_3_0[0]\, B => N_574, Y => - \xaddress_RNI1CIE2_0[0]\); - - \r.vaddr_RNI8IHC[15]\ : MX2 - port map(A => maddress(15), B => \vaddr[15]\, S => - \dstate_i_1[8]\, Y => \data[15]\); - - \r.dstate_0_RNI1JGE7_2[2]\ : AOI1B - port map(A => diagdata_26, B => \dstate_0[2]\, C => - \dcramo_m_0[250]\, Y => \rdatav_0_1_0_iv_3[26]\); - - \r.xaddress[4]\ : DFN1 - port map(D => N_715, CLK => lclk_c, Q => \addr[4]\); - - \r.wb.data2_RNO[6]\ : MX2A - port map(A => edata2_0_iv(6), B => hrdata_1, S => - \dstate_1[7]\, Y => \data2_1[6]\); - - \r.wb.data1[11]\ : DFN1E0 - port map(D => \data1_1[11]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data(11)); - - \r.paddress[26]\ : DFN1E1 - port map(D => N_192, CLK => lclk_c, E => paddress_1_sqmuxa, - Q => \paddress_0[26]\); - - \r.trans_op\ : DFN1 - port map(D => trans_op_RNO_1, CLK => lclk_c, Q => - \trans_op_0\); - - \r.faddr_RNI0MQ381[3]\ : NOR3 - port map(A => N_3288, B => N_3287, C => \address_i_1[6]\, Y - => N_24); - - \r.dstate_RNIET0O2[5]\ : AO1B - port map(A => un157_m_en, B => N_566, C => \dstate[5]\, Y - => \dstate_RNIET0O2[5]\); - - \r.holdn_RNO_8\ : OR2B - port map(A => e_0_0_RNI8APPC92, B => N_485, Y => N_3613); - - \r.holdn_RNO_28\ : NOR3A - port map(A => asi(1), B => \e_0\, C => read_0, Y => - holdns_iv_0_a2_2_1); - - \r.wb.addr_RNO_2[13]\ : AOI1B - port map(A => N_2165_0, B => N_677, C => N_273, Y => - \addr_1_1_iv_0_0[13]\); - - \r.burst_RNO_1\ : NOR3 - port map(A => burst_1_iv_2, B => burst_RNO_3, C => - burst_0_sqmuxa_5, Y => burst_1_N_12); - - \r.wb.addr_RNO_0[23]\ : NOR3C - port map(A => N_216, B => \addr_1_1_iv_0_0[23]\, C => - N_3889, Y => \addr_1_1_iv_0_2[23]\); - - \r.mmctrl1.e_0_0_RNI0T0A3\ : AOI1 - port map(A => \dstate_ns_0_0_o2_0[1]\, B => N_3746, C => - \e_0\, Y => \dstate_ns_0_0_a2_0[1]\); - - \dctrl.0.genmux.un6_validrawv_2\ : MX2 - port map(A => dataout_0(2), B => dataout_0(6), S => - maddress(4), Y => N_2013); - - \r.xaddress_RNI5DM3K[0]\ : AND2 - port map(A => \edata_m_i[31]\, B => \dcramo_m_i[255]\, Y - => \ddatainv_0_1_0_iv_0[31]\); - - \r.wb.addr_RNO_0[3]\ : NOR3C - port map(A => \addr_1_1_iv_0_0[3]\, B => N_295, C => - N_293_0, Y => \addr_1_1_iv_0_2[3]\); - - \r.paddress[15]\ : DFN1E1 - port map(D => N_351, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[15]\); - - \r.mmctrl1.nf_RNIOHLFF\ : NOR3C - port map(A => N_176, B => N_175, C => N_174, Y => - mexc_1_m_0_1); - - \r.mmctrl1.ctx_RNIPUJ8[7]\ : XNOR2 - port map(A => dataout(35), B => \ctx[7]\, Y => ctx_7_i); - - \r.dstate_RNI4T29H[1]\ : NAND2 - port map(A => ddatainv_0_6_sqmuxa, B => \edata[27]\, Y => - \edata_m_i[27]\); - - \r.burst_RNO\ : NOR3 - port map(A => burst_1_m8_i_0, B => burst_1_N_12, C => - burst_1_N_9, Y => burst_RNO); - - \un1_v.holdn_3_sqmuxa_0_0_o2\ : OR2B - port map(A => N_3743, B => N_3742, Y => N_492); - - \r.holdn_RNIJ4401\ : OR2B - port map(A => maddress_0_0, B => N_3785, Y => N_3598); - - \r.flush_RNITKH06\ : NOR2 - port map(A => flush_i, B => \dstate_RNIR2CO3[4]\, Y => - flush_RNITKH06); - - \r.dstate_i_0_RNIRK89F[8]\ : OR2A - port map(A => addr_0_sqmuxa_1, B => dstate_19, Y => N_514); - - \r.dstate_RNIV0G5E[1]\ : OR2B - port map(A => \edata[10]\, B => ddatainv_0_4_sqmuxa, Y => - \edata_m_0_i[10]\); - - \r.dstate_RNI1EIBG[1]\ : AOI1B - port map(A => \edata[16]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[240]\, Y => \ddatainv_0_1_0_iv_0[16]\); - - \r.valid_0_RNO[7]\ : OR3C - port map(A => N_3285, B => N_3283, C => N_3286, Y => - \valid_0_1[7]\); - - \r.xaddress_RNO[10]\ : MX2 - port map(A => \addr[10]\, B => maddress(10), S => N_486_0, - Y => N_718); - - \r.dstate_i_0_RNI16A62[8]\ : OR2A - port map(A => N_485, B => \dstate_i_0[8]\, Y => N_3331_0); - - \r.dstate_2_RNIRGNAI[7]\ : OR2B - port map(A => \dstate_2[7]\, B => N_78_0, Y => - \mcdo_m_0[25]\); - - \r.wb.lock_RNO_5\ : OR2B - port map(A => \lock_0\, B => \req\, Y => lock_1_iv_0_a2_0); - - \r.dstate_i_2_RNIH6U12[8]\ : OR2B - port map(A => un1_m0_2_42, B => miscdata_3_sqmuxa, Y => - N_3392); - - \un1_v.cctrlwr19_2_0_2072_0\ : OR2 - port map(A => N_3779, B => N_494, Y => cctrlwr19_2_0_2072_0); - - \r.dstate_0_RNITN6TH[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_0_24, Y => - \mcdo_m_0[24]\); - - \r.wb.data1[25]\ : DFN1E0 - port map(D => \data1_1[25]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_13); - - \r.wb.data2_RNO[29]\ : MX2 - port map(A => edata2_iv_i_0(29), B => hrdata_24, S => - \dstate_1[7]\, Y => \data2_1[29]\); - - \r.dstate_i_RNI0I51[8]\ : NOR2A - port map(A => \dstate_i[8]\, B => \dstate_2[7]\, Y => - N_3153); - - \r.wb.data2[1]\ : DFN1E1 - port map(D => \data2_1[1]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[1]\); - - \r.wb.data2[4]\ : DFN1E1 - port map(D => \data2_1[4]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[4]\); - - \r.wb.addr_RNO_0[5]\ : NOR3C - port map(A => \addr_1_1_iv_0_0[5]\, B => N_290, C => N_288, - Y => \addr_1_1_iv_0_2[5]\); - - \r.wb.addr_RNO_2[15]\ : OR2B - port map(A => maddress(15), B => addr_2_sqmuxa_0, Y => - \dci_m[23]\); - - \r.vaddr[28]\ : DFN1E1 - port map(D => maddress(28), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[28]\); - - \r.wb.addr_RNO_0[25]\ : AOI1B - port map(A => data_1_3_i_a3_6_0, B => LVL_RNIT69H911(0), C - => addr_1_sqmuxa_2_0, Y => \mmudco_m_0[101]\); - - \r.valid_0_RNIV2PE2[6]\ : AOI1 - port map(A => hit, B => \valid_0[6]\, C => N_3244_i_0, Y - => N_2026); - - \r.dstate_RNI65L74[7]\ : NOR2B - port map(A => mexc, B => N_84, Y => mexc_1_m_0_a2_4_0); - - \r.wb.data1_RNO_0[5]\ : NOR3A - port map(A => N_3331_0, B => req_0_sqmuxa_1_0, C => - \data2[5]\, Y => N_3364); - - \r.mmctrl1.ctxp_RNI2QJ12[26]\ : OR2B - port map(A => \ctxp[26]\, B => N_3344_i_0_0, Y => - \ctxp_m[26]\); - - \r.flush_RNI0NBH\ : MX2 - port map(A => flush, B => flush_0, S => asi(1), Y => N_136); - - \dctrl.un18_m_en\ : NOR3A - port map(A => lock, B => read_0, C => un17_m_en, Y => - un18_m_en); - - \r.cctrl.dcs[1]\ : DFN1 - port map(D => N_51, CLK => lclk_c, Q => \dcs[1]\); - - \r.dstate_RNIEGRAG[1]\ : AOI1B - port map(A => \edata[17]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[241]\, Y => \ddatainv_0_1_0_iv_0[17]\); - - \r.dstate_RNI2NRIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[5]\, Y => \ddatainv_0_1_0_iv_1[21]\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNIMMIH9\ : OR3 - port map(A => cctrlwr19_2_0_2072_0, B => N_3607, C => - N_3610, Y => dcs_1_i_s_0_o2_0_RNIMMIH9); - - \r.wb.addr_RNO_2[28]\ : OR2B - port map(A => maddress(28), B => addr_2_sqmuxa_0, Y => - N_3888); - - \r.read_RNII33M8\ : NOR2B - port map(A => \N_425\, B => hrdata_0_8, Y => \mcdo_m[8]\); - - \r.read_RNI3RIPJ\ : OR2B - port map(A => \N_425_0\, B => N_262_0, Y => \mcdo_m_i[20]\); - - \r.wb.addr_RNO_3[12]\ : AOI1B - port map(A => N_2165_0, B => N_676, C => N_278, Y => - \addr_1_1_iv_0_0[12]\); - - \r.dstate_RNIMRB5A[1]\ : NOR2B - port map(A => \edata[6]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[6]\); - - \r.dstate_RNO_1[6]\ : OAI1 - port map(A => \dstate_ns_0_0_a2_0[2]\, B => - \dstate_ns_0_0_a2_0_1[2]\, C => N_3781, Y => - \dstate_RNO_1[6]\); - - \r.dstate_i_2_RNIRUH12[8]\ : OR2B - port map(A => un1_m0_2_43, B => miscdata_3_sqmuxa, Y => - \mmudco_m[44]\); - - \r.cctrl.dcs_RNID9M04[1]\ : AOI1B - port map(A => \dcs[1]\, B => rdatav_0_0_sqmuxa, C => N_3399, - Y => \rdatav_0_1_1_iv_i_a2_2[3]\); - - \r.dstate_tr22_15_a2_1_0\ : OR2A - port map(A => enaddr, B => nullify, Y => N_581_i); - - \r.dstate_RNIVP6I3_2[6]\ : NOR2A - port map(A => N_487, B => N_506, Y => paddress_1_sqmuxa); - - \r.flush_RNIM7304\ : NOR2B - port map(A => flush_m, B => \rdatav_0_1_0_iv_0[14]\, Y => - \rdatav_0_1_0_iv_1[14]\); - - \r.xaddress_RNI2O5H[2]\ : AOI1B - port map(A => \addr[2]\, B => N_3747, C => N_3443_i, Y => - N_3793); - - \r.wb.data1_RNO[26]\ : MX2A - port map(A => N_2124, B => maddress(26), S => - req_0_sqmuxa_1, Y => \data1_1[26]\); - - \r.stpend_RNO_1\ : OR2A - port map(A => N_485, B => holdn_1_5, Y => stpend_1_0); - - \r.valid_0_RNO[3]\ : AO1B - port map(A => dataout_0(3), B => N_88, C => N_3380, Y => - \valid_0_1[3]\); - - \r.cctrl.dcs_RNILMPD[1]\ : OR2 - port map(A => \dcs[1]\, B => \dcs[0]\, Y => \cache\); - - \r.mmctrl1.e_0_0_RNIIAUC4Q1\ : AO1B - port map(A => dstate_tr22_15_a2_2_m8_i_a5_1_1, B => - dstate_tr22_15_a2_2_m1_e, C => - dstate_tr22_15_a2_2_m8_i_0_0, Y => e_0_0_RNIIAUC4Q1); - - \r.vaddr[26]\ : DFN1E1 - port map(D => maddress(26), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[26]\); - - \r.wb.data1_RNO[19]\ : MX2A - port map(A => N_2117, B => maddress(19), S => - req_0_sqmuxa_1_0, Y => \data1_1[19]\); - - \r.dstate_RNI1JGE7_4[2]\ : AOI1B - port map(A => dataout(6), B => rdatav_0_6_sqmuxa_0, C => - \ico_m[140]\, Y => \rdatav_0_1_1_iv_6[6]\); - - \r.wb.lock_RNO_1\ : OR2B - port map(A => \req\, B => N_56, Y => N_86); - - \r.stpend_RNIJ1FL692\ : OR3A - port map(A => stpend, B => read_1, C => nullify, Y => - N_3511); - - \r.xaddress_RNIJH2O2_2[0]\ : NOR2B - port map(A => dataout(12), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[236]\); - - \r.dstate_RNI5VRP7[7]\ : OR2B - port map(A => mexc_1_m_0_a2_4_0, B => mexc_0_sqmuxa_1, Y - => N_176); - - \r.vaddr[29]\ : DFN1E1 - port map(D => maddress(29), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[29]\); - - \r.mmctrl1.nf_RNO_0\ : MX2 - port map(A => \nf\, B => maddress_0_0, S => e_0_sqmuxa, Y - => N_2675); - - \r.mmctrl1.ctx[3]\ : DFN1 - port map(D => \ctx_RNIAM7T[3]\, CLK => lclk_c, Q => - \ctx[3]\); - - \r.xaddress[18]\ : DFN1E1 - port map(D => maddress(18), CLK => lclk_c, E => N_486, Q - => \addr[18]\); - - \r.wb.data2_RNI6VN44[31]\ : NOR3C - port map(A => \dcramo_m[127]\, B => \data2_m[31]\, C => - \mmudco_m[74]\, Y => \rdatav_0_1_0_iv_1[31]\); - - \r.dstate_RNIHILB6_11[7]\ : OR2B - port map(A => dataout(12), B => rdatav_0_6_sqmuxa, Y => - N_160); - - VCC_i : VCC - port map(Y => \VCC\); - - \dctrl.un19_eholdn_0_a2_0_a2_0_a2_0_a2\ : OR2A - port map(A => un19_eholdn_3, B => asi(2), Y => un19_eholdn); - - \r.xaddress_RNIQF6M2_0[0]\ : OR2B - port map(A => dataout_0(29), B => N_2088, Y => - \dcramo_m_i[253]\); - - \r.mmctrl1.ctx[5]\ : DFN1 - port map(D => \ctx_0_0_RNI91UO[5]\, CLK => lclk_c, Q => - \ctx[5]\); - - \r.dstate_tr16_10_0_i_o2_0_i_a2_0\ : NOR2A - port map(A => N_505, B => asi(4), Y => N_3572); - - \dctrl.v.wb.addr_1_1_iv_0_a2_1[10]\ : NAND2 - port map(A => N_514, B => \address[10]\, Y => N_3723); - - \r.mmctrl1.ctxp_RNITLJ12[14]\ : OR2B - port map(A => \ctxp[14]\, B => N_3344_i_0, Y => - \ctxp_m[14]\); - - \r.dstate_i_0_RNIU0NO[8]\ : OR2A - port map(A => un1_dci_12_0, B => \dstate_i_0[8]\, Y => - vaddr_1_sqmuxa_0_a2_0); - - \dctrl.vmaskraw_1_i_o2_i_a2_0_RNO[1]\ : NOR2A - port map(A => N_3443_i, B => \addr[3]\, Y => - \vmaskraw_1_i_o2_i_a2_0_0[1]\); - - \r.mmctrl1.e_RNI9F783\ : NOR2A - port map(A => un47_m_en, B => N_3331, Y => addr_2_sqmuxa_0); - - \r.flush_0_1_RNIBUA27S2\ : AO1B - port map(A => maddress(18), B => \N_329\, C => - \newtag_1_0[18]\, Y => flush_0_1_RNIBUA27S2); - - \r.faddr_RNO[2]\ : NOR3C - port map(A => rst, B => flush_0, C => I_9_1, Y => - \faddr_1[2]\); - - \r.xaddress_RNI18V9992[31]\ : OR2B - port map(A => \addr[31]\, B => \N_330\, Y => N_269); - - \r.wb.data1_RNO_0[20]\ : MX2C - port map(A => edata2_0_iv(20), B => \data2[20]\, S => - N_3331_0, Y => N_2118); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0\ : NAND2 - port map(A => N_500_i, B => N_501, Y => N_502); - - \r.dstate_RNI6JA5A[1]\ : NOR2B - port map(A => \edata[4]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[4]\); - - \r.dstate_ns_i_a4_i_o2_5[0]\ : OR2A - port map(A => asi(3), B => asi(1), Y => N_490); - - \r.dstate_i_RNIP1BPN92[8]\ : NOR2A - port map(A => edata2_iv_i_0(25), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_89); - - \r.valid_0_RNO_0[6]\ : MX2C - port map(A => dataout_0(6), B => \vmask_0_6[6]\, S => - twrite_14, Y => N_2366); - - \r.dstate_RNO_10[5]\ : OR3 - port map(A => N_2994_8, B => N_3002_9, C => N_2995_8, Y => - \dstate_ns_0_2_0_tz[3]\); - - \r.dstate_i_2_RNIUQM12[8]\ : OR2B - port map(A => un1_m0_2_68, B => miscdata_4_sqmuxa, Y => - \mmudco_m[69]\); - - \r.dstate_i_0_RNI6CL21[8]\ : NOR2 - port map(A => vaddr_1_sqmuxa_0_a2_0, B => un17_casaen_0_0, - Y => twrite_14_iv_0_a2_a1_0); - - \r.paddress[21]\ : DFN1E1 - port map(D => N_419, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[21]\); - - \r.hit_RNI17SC\ : NOR2B - port map(A => \dcs[0]\, B => hit, Y => N_58); - - \r.dstate_RNO[3]\ : NOR2B - port map(A => rst, B => \dstate_ns[5]\, Y => - \dstate_nss[5]\); - - \r.dstate_i_RNI0N99F92[8]\ : MX2A - port map(A => edata2_0_iv(2), B => \vmask_0_6[2]\, S => - \dstate_i_RNII68N892_0[8]\, Y => N_2381); - - \un1_v.cctrlwr19_2_0_o2_7\ : OR3C - port map(A => N_3770, B => N_3765, C => - cctrlwr19_2_0_o2_7_0, Y => N_576); - - \r.paddress[7]\ : DFN1E1 - port map(D => un1_m0_2_8, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[7]\); - - \r.xaddress_RNILK99L1[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[27]\, B => - \mcdo_m_i[27]\, C => \ddatainv_0_1_0_iv_1[27]\, Y => - xaddress_RNILK99L1(1)); - - \r.wb.addr_RNO_2[27]\ : OR2B - port map(A => maddress(27), B => addr_2_sqmuxa_0, Y => - N_250); - - \r.wb.addr_RNO[27]\ : AO1B - port map(A => \addr_1_1_iv_0_a3_2_0[27]\, B => N_2717, C - => \addr_1_1_iv_0_2[27]\, Y => \addr_1[27]\); - - \r.xaddress_RNIQF6M2_9[0]\ : OR2B - port map(A => dataout(17), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[241]\); - - \r.wb.addr_RNO_3[11]\ : AOI1B - port map(A => \addr_1_1_iv_0_a3_0[11]\, B => - \dstate_RNIP22L4[7]\, C => N_284, Y => - \addr_1_1_iv_0_0[11]\); - - \r.wb.addr[6]\ : DFN1 - port map(D => \addr_1[6]\, CLK => lclk_c, Q => \address[6]\); - - \r.dstate_RNIC3QA81[1]\ : OR3 - port map(A => \edata_m[0]\, B => \dcramo_m[224]\, C => - \ddatainv_0_1_1_iv_1[0]\, Y => dstate_RNIC3QA81(1)); - - \r.mmctrl1.ctx_0_0_RNI2O8L[4]\ : MX2 - port map(A => \ctx_0[4]\, B => maddress(4), S => - ctx_1_sqmuxa, Y => N_2667); - - \r.dstate_0_RNIBQ8841[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_5[14]\, B => - \rdatav_0_1_0_iv_4[14]\, C => \mcdo_m_0[14]\, Y => - data_0_14); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_16\ : NOR2 - port map(A => eaddress_10, B => eaddress_25, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_16); - - \r.req_RNIDTDR692\ : NOR2A - port map(A => \req\, B => N_3511, Y => N_29); - - \r.cctrl.dfrz_RNI3VJJ7\ : NOR3C - port map(A => N_3392, B => N_3329, C => - \rdatav_0_1_1_iv_i_a2_1[5]\, Y => - \rdatav_0_1_1_iv_i_a2_3[5]\); - - \r.dstate_tr22_15_a2_2_m8_i_a5_0_0\ : AO1C - port map(A => N_459, B => dstate_tr22_15_a2_14_1_0, C => - dstate_tr22_15_a2_15_0, Y => - dstate_tr22_15_a2_2_m8_i_a5_0_0); - - \r.wb.data2_RNIU5E04[9]\ : AOI1B - port map(A => un1_m0_2_44, B => miscdata_3_sqmuxa, C => - \rdatav_0_1_0_iv_0[9]\, Y => \rdatav_0_1_0_iv_1[9]\); - - \r.xaddress_RNIOMT7A[1]\ : OR2B - port map(A => \edata[3]\, B => ddatainv_0_0_sqmuxa, Y => - \edata_m_4_i[3]\); - - \r.wb.addr_RNO[23]\ : AO1B - port map(A => un1_m0_2_98, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[23]\, Y => \addr_1[23]\); - - \r.vaddr_RNIAIHC[24]\ : MX2 - port map(A => maddress(24), B => \vaddr[24]\, S => - \dstate_i_1[8]\, Y => data(24)); - - \r.dstate[6]\ : DFN1 - port map(D => \dstate_nss[2]\, CLK => lclk_c, Q => - \dstate[6]\); - - \r.wb.addr_RNO[12]\ : AO1B - port map(A => \addr_1_1_iv_0_a3_2_0[12]\, B => N_2711_i_0, - C => \addr_1_1_iv_0_2[12]\, Y => \addr_1[12]\); - - \r.dstate_RNISDQ4R[1]\ : AO1 - port map(A => \edata[1]\, B => \size_RNIBHS22[0]\, C => - \mcdo_m[1]\, Y => \ddatainv_0_1_1_iv_1[1]\); - - \r.mmctrl1.ctxp_RNI713D7[9]\ : AOI1B - port map(A => \ctxp[9]\, B => N_3344_i_0_0, C => - \rdatav_0_1_1_iv_2[11]\, Y => \rdatav_0_1_1_iv_3[11]\); - - \r.wb.data2_RNI6EJ7[9]\ : OR2B - port map(A => \data2[9]\, B => rdatav_012, Y => - \data2_m[9]\); - - \r.dstate_RNIQSCNB[1]\ : MX2 - port map(A => maddress(9), B => edata2_0_iv(9), S => - edata_0_sqmuxa_i, Y => \edata[9]\); - - \r.dstate_2_RNIIH7OC[7]\ : OR2B - port map(A => \dstate_2[7]\, B => N_264_0, Y => mcdo_m_0_18); - - \r.xaddress[9]\ : DFN1E1 - port map(D => maddress(9), CLK => lclk_c, E => N_486, Q => - \addr[9]\); - - \r.wb.data1_RNO_0[31]\ : MX2C - port map(A => edata2_iv_i_0(31), B => \data2[31]\, S => - N_3331, Y => N_2129); - - \r.dstate_tr8_2_8_0_a2_1_a2_0\ : OR2 - port map(A => asi(4), B => asi(1), Y => - dstate_tr8_2_8_0_a2_1_a2_0); - - \r.read_RNIB23F8\ : NOR2B - port map(A => \N_425\, B => hrdata_0_9, Y => \mcdo_m[9]\); - - \r.wb.data2_RNIUDI7[1]\ : OR2B - port map(A => \data2[1]\, B => rdatav_012, Y => N_89); - - \r.mmctrl1.nf_RNI76UP3\ : OR2 - port map(A => \nf\, B => mexc_0_sqmuxa_1, Y => N_174); - - \r.dstate_RNIOIKBG[1]\ : AOI1B - port map(A => \edata[23]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[247]\, Y => \ddatainv_0_1_0_iv_0[23]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_3\ : NOR3B - port map(A => eaddress_4, B => eaddress_1, C => eaddress_8, - Y => vaddr_1_sqmuxa_0_a2_4_m1_e_3); - - \r.wb.addr_RNO_4[4]\ : MX2 - port map(A => \paddress[4]\, B => \addr[4]\, S => N_484, Y - => N_678); - - \r.holdn_RNO_6\ : OR3C - port map(A => ready, B => mexc_0_sqmuxa, C => N_3605, Y => - holdn_1_sqmuxa_3); - - \r.dstate_0_RNIP8ET5[7]\ : NOR2A - port map(A => rdatav_0_6_sqmuxa_3, B => \dstate_0[7]\, Y - => rdatav_0_6_sqmuxa_0); - - \r.cctrl.dfrz_RNIOGHR1\ : OR2B - port map(A => dfrz, B => rdatav_0_0_sqmuxa, Y => N_3329); - - \r.wb.addr_RNO[15]\ : AO1B - port map(A => \mmudco_m_0[91]\, B => N_2699_i_0, C => - \addr_1_1_iv_2[15]\, Y => \addr_1[15]\); - - \r.dstate_RNIEHR5G[1]\ : MX2 - port map(A => maddress(30), B => edata2_iv_i_0(30), S => - edata_0_sqmuxa_i, Y => \edata[30]\); - - \r.dstate_i_2_RNITQM12[8]\ : OR2B - port map(A => un1_m0_2_67, B => miscdata_4_sqmuxa, Y => - \mmudco_m[68]\); - - \r.mmctrl1.e_0_0\ : DFN1 - port map(D => e_0_sqmuxa_RNIQKNL, CLK => lclk_c, Q => \e_0\); - - \r.dstate_RNO[1]\ : AOI1B - port map(A => dstate_tr22_2, B => N_3564_i, C => rst, Y => - \dstate_nss[7]\); - - \r.dstate_RNIUQ9VC[1]\ : AO1 - port map(A => dataout(5), B => \xaddress_RNIQDEG2_0[0]\, C - => \edata_m[5]\, Y => \ddatainv_0_1_1_iv_0[5]\); - - \r.dstate_RNIOMT7A[1]\ : NOR2B - port map(A => \edata[3]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[3]\); - - \r.read_RNIQM0I2\ : OR3A - port map(A => read, B => N_135, C => N_84, Y => N_179); - - \r.read_RNI6SUEH\ : OR2B - port map(A => \N_425\, B => hrdata_0_23, Y => - \mcdo_m_i[23]\); - - \r.dstate_RNICL8A6[7]\ : OR3B - port map(A => N_84, B => hit_1_iv_0_a2_0, C => flush_i, Y - => twrite_11_m); - - \r.dstate[7]\ : DFN1 - port map(D => \dstate_nss[1]\, CLK => lclk_c, Q => - \dstate[7]\); - - \r.paddress[25]\ : DFN1E1 - port map(D => N_190_0, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress_0[25]\); - - \r.wb.addr_RNO_4[28]\ : OR2B - port map(A => \address[28]\, B => N_514, Y => N_214); - - \r.dstate_i_2_RNILAMC992[8]\ : AO1D - port map(A => cctrlwr13, B => mmudci_diag_op_1_0_a2_0, C - => N_3790, Y => vaddr_1_sqmuxa_0_0); - - \r.mmctrl1.ctx_0_0_RNIDSBP9[0]\ : NOR3C - port map(A => \rdatav_0_1_0_iv_2[0]\, B => - \rdatav_0_1_0_iv_1[0]\, C => \ctx_m[0]\, Y => - \rdatav_0_1_0_iv_4[0]\); - - \r.dstate_RNID2ELB1[4]\ : NOR3C - port map(A => \dstate_ns_i_a4_i_4[0]\, B => N_3683_i, C => - N_3815, Y => \dstate_ns_i_a4_i_6[0]\); - - \r.dstate_i_2_RNIRB2T1[8]\ : OR2B - port map(A => flush, B => rdatav_0_0_sqmuxa, Y => N_205); - - \r.size_RNIGFGD1[0]\ : OR2B - port map(A => N_3600, B => N_3599, Y => ddatainv_0_4_sqmuxa); - - \r.xaddress[31]\ : DFN1E1 - port map(D => maddress(31), CLK => lclk_c, E => N_486, Q - => \addr[31]\); - - \r.flush_RNIA3GPL\ : NOR2 - port map(A => eaddress_6, B => N_195, Y => N_3288); - - \r.dstate_1_RNIHNPT81[7]\ : OR3C - port map(A => N_3811, B => N_522, C => N_563, Y => N_3679); - - \r.dstate_RNI75ESQ1[7]\ : OA1A - port map(A => twrite_14_iv_0_o2_a1_3, B => - nullify2_0_sqmuxa, C => twrite_11_m, Y => - twrite_14_iv_0_o2_0_0); - - \r.ready_RNO_2\ : AOI1B - port map(A => ready_0_sqmuxa_0_a2_1_0, B => - \dstate_i_RNIF4S5B92[8]\, C => N_3697, Y => - ready_0_sqmuxa_0_2); - - \r.wb.data1[20]\ : DFN1E0 - port map(D => \data1_1[20]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_8); - - \r.dstate_RNIICAT5[2]\ : NOR2A - port map(A => rdatav_0_6_sqmuxa_3_2, B => rdatasel_3_sqmuxa, - Y => rdatav_0_6_sqmuxa_3); - - \r.wb.data2_RNO[1]\ : MX2A - port map(A => edata2_0_iv(1), B => hrdata_0_1, S => - \dstate_1[7]\, Y => \data2_1[1]\); - - \r.flush2_RNI9VSV2\ : NOR3 - port map(A => \un1_p0_2_0[498]\, B => flush2, C => - un1_dci_NE, Y => N_499); - - \r.dstate_0_RNIIC256[7]\ : OR2B - port map(A => dataout_0(29), B => rdatav_0_6_sqmuxa_0, Y - => \dcramo_m_0[253]\); - - \r.dstate_RNII6PNA[1]\ : NOR2B - port map(A => \edata[7]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[7]\); - - \r.req_RNO_5\ : MX2C - port map(A => \req\, B => \burst\, S => grant, Y => - N_2471_i); - - \r.dstate_i_2_RNIPU7E[8]\ : OR2A - port map(A => asi(3), B => \dstate_i_2[8]\, Y => N_3788); - - \r.mmctrl1.e_0_0_RNIVJMK\ : OR2 - port map(A => \e_0\, B => N_595, Y => - dstate_tr8_5_9_0_a2_0_a2_0); - - \r.mmctrl1.ctxp[25]\ : DFN1E1 - port map(D => maddress(27), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[25]\); - - \r.valid_0[5]\ : DFN1E0 - port map(D => \valid_0_1[5]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[5]\); - - \r.mmctrl1.ctxp[22]\ : DFN1E1 - port map(D => maddress(24), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[22]\); - - \r.xaddress_RNI1R2NN[6]\ : MX2C - port map(A => N_2233, B => eaddress_4, S => taddr_2_sqmuxa, - Y => \taddr_7[6]\); - - \r.wb.data1[17]\ : DFN1E0 - port map(D => \data1_1[17]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_5); - - \r.wb.addr_RNO_2[0]\ : OR2B - port map(A => maddress(0), B => N_2164, Y => \dci_m[8]\); - - \r.dstate_i_RNI3BM3A92[8]\ : OR3A - port map(A => un1_eholdn_2_9, B => read_0, C => \N_121\, Y - => flush_1_sqmuxa); - - \r.mmctrl1.ctxp[1]\ : DFN1E1 - port map(D => maddress(3), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[1]\); - - \r.dstate_RNIHILB6_3[7]\ : OR2B - port map(A => dataout(21), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[245]\); - - \r.dstate_i_2_RNIQQM12[8]\ : OR2B - port map(A => un1_m0_2_64, B => miscdata_4_sqmuxa, Y => - \mmudco_m[65]\); - - \v.wb.addr_0_sqmuxa_2\ : NAND2 - port map(A => \dstate_0[7]\, B => burst_0_sqmuxa, Y => - addr_0_sqmuxa_2); - - \r.dstate_RNI4AIHH[1]\ : AO1 - port map(A => \edata[14]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[238]\, Y => \ddatainv_0_1_1_iv_0[14]\); - - \r.cache_RNO_3\ : OR2A - port map(A => N_512, B => \e_0\, Y => cache_1_0_a2_0_0); - - \dctrl.twrite_14_iv_0_o2_a0_RNI492373\ : OR3C - port map(A => N_1_28_i, B => twrite_14_iv_0_o2_0_0, C => - N_3322, Y => twrite_14); - - \r.cctrl.dcs_RNIPCLN1[0]\ : NOR3B - port map(A => \dstate_ns_i_a4_i_a2_3_0[0]\, B => N_481, C - => N_3788, Y => \dstate_ns_i_a4_i_a2_3_2[0]\); - - \r.asi[1]\ : DFN1E1 - port map(D => asi(1), CLK => lclk_c, E => N_486_0, Q => - \asi_0[1]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_5\ : NOR2 - port map(A => eaddress_16, B => eaddress_12, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_5); - - \r.xaddress_RNIJH2O2_4[0]\ : NOR2B - port map(A => dataout(10), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[234]\); - - \r.dstate_i_2_RNIFPVH[8]\ : OR2 - port map(A => \dstate_i_2[8]\, B => N_496, Y => N_526); - - \r.cctrlwr_RNIJD74\ : NOR2A - port map(A => cctrlwr, B => \addr[6]\, Y => - flush_0_sqmuxa_0_o3_i_o2_0); - - \r.xaddress_RNICSNRG[1]\ : AOI1B - port map(A => \edata[2]\, B => ddatainv_0_0_sqmuxa, C => - \edata_m_0_i[10]\, Y => \ddatainv_0_1_0_iv_1[26]\); - - \r.valid_0_RNO[2]\ : OA1B - port map(A => hit_1_iv_0_a2_0_0, B => twrite_14, C => - N_2362, Y => \valid_0_1[2]\); - - \r.dstate_tr22_15_a2_7_2_0_a2\ : OR3A - port map(A => asi(4), B => N_505, C => asi(3), Y => - N_3569_2); - - \r.holdn_RNO_16\ : AOI1B - port map(A => holdns_iv_0_a2_2_3, B => - \dstate_i_RNIF4S5B92[8]\, C => N_3614, Y => holdns_iv_0_0); - - \r.holdn_RNINK401_0\ : OR3A - port map(A => N_568, B => N_3443_i, C => maddress_0_2, Y - => N_3653); - - \r.dstate[2]\ : DFN1 - port map(D => \dstate_nss[6]\, CLK => lclk_c, Q => - \dstate[2]\); - - \r.cctrl.dcs_RNIV2LD[0]\ : NOR2B - port map(A => \dcs[0]\, B => enaddr, Y => un121_m_en_i_s_0); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_1\ : NOR2A - port map(A => N_499, B => un6_validrawv, Y => N_500_i); - - \r.wb.addr_RNO_0[19]\ : NOR3C - port map(A => N_221, B => \addr_1_1_iv_0_0[19]\, C => N_224, - Y => \addr_1_1_iv_0_2[19]\); - - \r.dstate_RNO_9[1]\ : OR3A - port map(A => lock, B => N_666, C => N_526, Y => N_90); - - \r.wb.addr_RNO_2[23]\ : AOI1B - port map(A => N_3838, B => N_2165_0, C => N_218, Y => - \addr_1_1_iv_0_0[23]\); - - \r.mmctrl1.ctx_0_0[3]\ : DFN1 - port map(D => \ctx_RNIAM7T[3]\, CLK => lclk_c, Q => - \ctx_0[3]\); - - \r.dstate_RNIFPT581[1]\ : OR3 - port map(A => \edata_m[1]\, B => \dcramo_m[225]\, C => - \ddatainv_0_1_1_iv_1[1]\, Y => dstate_RNIFPT581(1)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu_acache is - - port( iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - hgrant : in std_logic_vector(0 to 0); - hsize_5 : out std_logic_vector(1 to 1); - size : in std_logic_vector(1 to 1); - iosn_1 : in std_logic_vector(93 to 93); - data_0_18 : in std_logic; - data_0_1 : in std_logic; - data_0_3 : in std_logic; - data_0_17 : in std_logic; - data_0_22 : in std_logic; - data_0_21 : in std_logic; - data_0_9 : in std_logic; - data_0_23 : in std_logic; - data_0_20 : in std_logic; - data_0_4 : in std_logic; - data_0_31 : in std_logic; - data_0_26 : in std_logic; - data_0_15 : in std_logic; - data_0_7 : in std_logic; - data_0_27 : in std_logic; - data_0_25 : in std_logic; - data_0_16 : in std_logic; - data_0_30 : in std_logic; - data_0_28 : in std_logic; - data_0_14 : in std_logic; - data_0_2 : in std_logic; - data_0_11 : in std_logic; - data_0_0 : in std_logic; - data_0_12 : in std_logic; - data_0_6 : in std_logic; - data_0_19 : in std_logic; - data_18 : in std_logic; - data_1 : in std_logic; - data_3 : in std_logic; - data_17 : in std_logic; - data_22 : in std_logic; - data_21 : in std_logic; - data_9 : in std_logic; - data_23 : in std_logic; - data_20 : in std_logic; - data_4 : in std_logic; - data_31 : in std_logic; - data_26 : in std_logic; - data_15 : in std_logic; - data_7 : in std_logic; - data_27 : in std_logic; - data_25 : in std_logic; - data_16 : in std_logic; - data_30 : in std_logic; - data_28 : in std_logic; - data_14 : in std_logic; - data_2 : in std_logic; - data_11 : in std_logic; - data_0_d0 : in std_logic; - data_12 : in std_logic; - data_6 : in std_logic; - data_19 : in std_logic; - hwdata_15 : out std_logic; - hwdata_0 : out std_logic; - hwdata_14 : out std_logic; - hwdata_1 : out std_logic; - hwdata_28 : out std_logic; - hwdata_23 : out std_logic; - hwdata_12 : out std_logic; - hwdata_4 : out std_logic; - hwdata_13 : out std_logic; - hwdata_27 : out std_logic; - hwdata_25 : out std_logic; - hwdata_11 : out std_logic; - hwdata_9 : out std_logic; - hwdata_3 : out std_logic; - hwdata_16 : out std_logic; - address_1 : in std_logic_vector(31 downto 2); - haddr : out std_logic_vector(31 downto 2); - address_0 : in std_logic_vector(31 downto 2); - htrans_tz : out std_logic_vector(1 to 1); - bo_d : out std_logic_vector(3 downto 2); - iosn_0 : in std_logic_vector(93 to 93); - address : in std_logic_vector(31 downto 2); - htrans : out std_logic_vector(1 to 1); - nbo_5_0 : out std_logic_vector(1 downto 0); - size_1z : in std_logic; - werr : out std_logic; - lclk_c : in std_logic; - ready_0 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - mexc_1 : out std_logic; - ready : out std_logic; - N_466 : out std_logic; - lock : in std_logic; - lock_m : in std_logic; - hwrite_1_m_0 : out std_logic; - N_468 : out std_logic; - N_463 : out std_logic; - N_461 : out std_logic; - N_459 : out std_logic; - N_458 : out std_logic; - bo_5842_d : out std_logic; - N_139 : out std_logic; - N_138 : out std_logic; - un91_nbo_i_0 : out std_logic; - grant_1 : out std_logic; - hcache_1 : out std_logic; - werr_2_m_0 : out std_logic; - N_467 : out std_logic; - N_462 : out std_logic; - N_457 : out std_logic; - mexc_0 : out std_logic; - read_0 : in std_logic; - mexc : out std_logic; - un60_nbo : out std_logic; - hbusreq : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - N_5054 : out std_logic; - burst_0 : in std_logic; - hlock : out std_logic; - un59_nbo : out std_logic; - ba : out std_logic; - cache : in std_logic; - read : in std_logic; - burst : in std_logic; - req_1 : in std_logic; - req_0 : in std_logic; - req : in std_logic; - N_6093_i : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - grant_0 : out std_logic; - grant : out std_logic; - rst : in std_logic; - bo_5842_d_0 : out std_logic - ); - -end mmu_acache; - -architecture DEF_ARCH of mmu_acache is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \nbo_5_1[0]\, N_5210_i_0, N_4258, N_6040_2, un14_dreq, - N_4259, \bo[1]\, \bo[0]\, ba_3, bg_m, ba_m, un15_dreq_i, - un3_dreq, nbo4, N_5618_i, nba_0_0, \htrans_4_sqmuxa_1_1\, - htrans_4_sqmuxa_1_1_0, un17_dreq, hbusreq_0, - htrans_4_sqmuxa_1_0, lb, hcache_1_0, htrans_1_sqmuxa_0, - un71_nbo, \nbo_5_0[0]\, lb_0_sqmuxa_0, dgrant_0_sqmuxa_1, - bg, mmgrant_0_sqmuxa_1, igrant_0_sqmuxa_1, - \hburst_1_i_0[0]\, \nbo_5_0[1]\, un6_dreq, \bo_ns_0_3[0]\, - N_6039, \bo_RNI35I6[0]\, N_6037, \bo_ns_0_2[0]\, N_6042, - N_6036, \nbo_m[0]\, nbo4_0, N_6043_1, \bo_ns_i_2[1]\, - \bo_RNO_8[1]\, N_6044, hlocken_1, hlocken_0, hlocken, - un88_nbo_0, \bo_ns_i_a7_0[1]\, nba, \nbo_m_0[0]\, - \nbo[0]\, un71_nbo_0, \bo_ns_i_o7_0_0[1]\, \ba\, - un6_dreq_0, \bo_ns_0_a7_0[0]\, un569_dec_hcache_NE_7, - un569_dec_hcache_NE_6, un569_dec_hcache_NE_6_0, - un569_dec_hcache_NE_3, un569_dec_hcache_NE_5, - un569_dec_hcache_NE_1, hcache, hcache_0, - un509_dec_hcache_NE, un569_dec_hcache_NE, \grant\, - un19_nbo, retry2_RNILAS7, un11_dreq, \bo_5842_d_0\, - dgrant_0_sqmuxa, N_6030, N_6049, N_6040, \bo_ns[0]\, - N_4302, hlock_0_sqmuxa, hlock_1_sqmuxa, N_6025_i_0, - \bo_RNO_2[1]\, N_6043, N_6027, \nbo_RNO[1]\, nbo95, - \nbo[1]\, N_5056, lb_0_sqmuxa, \htrans[1]\, un10_hbusreq, - \grant_0\, un30_nbo, \bo_RNO_5[1]\, - \un1_htrans_1_sqmuxa_0\, \htrans_tz[1]\, N_4986, N_4987, - N_4960, \haddr_6[4]\, \haddr_10[4]\, N_4992, \N_6093_i\, - hwrite_1_m, werr_2_m, werr_RNO, N_4978, N_4983, N_4974, - N_4982, N_5006, N_5014, N_4979, N_5011, \un59_nbo\, - hcache_RNO, N_5540, retry2, dgrant_1, retry2_RNO, N_6050, - N_5939s, N_5939, un87_nbo, \haddr_6[3]\, N_4985, N_5017, - N_4977, N_4980, N_4981, N_5009, N_5012, N_5013, N_4966, - N_4998, N_4965, N_4997, N_4959, \haddr_10[3]\, N_4991, - N_4968, N_5000, N_5010, N_4964, N_4996, N_4976, N_4961, - N_4993, N_5008, \nbo_5[1]\, N_4958, \haddr_6_i[2]\, - \haddr_10_i[2]\, N_4970, N_4971, N_4990, N_5002, N_5003, - N_4975, N_5007, \nbo_5[0]\, \bo_5842_d\, N_5016, N_4984, - N_5001, N_4969, CO1, N_5539, hlocken_2, N_5542, N_5940, - N_5940s, N_5018, N_5019, \hlock\, N_4967, N_4999, - \bo_d[2]\, \lb_0_sqmuxa_1\, N_5015, bg_RNO, hlocken_RNO, - N_5620_i, N_4963, N_4995, N_4962, N_4994, N_4972, N_4973, - N_5004, N_5005, ready_1, mmmexc_2_sqmuxa, \mexc\, - \mexc_0\, \bo_d[3]\, lb_RNO, N_5541, ba_RNO, un11_hbusreq, - \N_5054\, un5_hlock, \un60_nbo\, \hcache_1\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - htrans_tz(1) <= \htrans_tz[1]\; - bo_d(3) <= \bo_d[3]\; - bo_d(2) <= \bo_d[2]\; - htrans(1) <= \htrans[1]\; - nbo_5_0(1) <= \nbo_5_0[1]\; - nbo_5_0(0) <= \nbo_5_0[0]\; - bo_5842_d <= \bo_5842_d\; - hcache_1 <= \hcache_1\; - mexc_0 <= \mexc_0\; - mexc <= \mexc\; - un60_nbo <= \un60_nbo\; - lb_0_sqmuxa_1 <= \lb_0_sqmuxa_1\; - N_5054 <= \N_5054\; - hlock <= \hlock\; - un59_nbo <= \un59_nbo\; - ba <= \ba\; - N_6093_i <= \N_6093_i\; - un1_htrans_1_sqmuxa_0 <= \un1_htrans_1_sqmuxa_0\; - grant_0 <= \grant_0\; - grant <= \grant\; - bo_5842_d_0 <= \bo_5842_d_0\; - - \r.bo_RNIDH8P7[0]\ : MX2 - port map(A => address(14), B => address_0(14), S => - \nbo_5_1[0]\, Y => N_4970); - - \r.bo_RNIB98P7[0]\ : MX2 - port map(A => address_0(21), B => address(21), S => - \nbo_5_0[0]\, Y => N_4977); - - \r.bo_RNIFDOG[0]\ : MX2C - port map(A => data_20, B => data_0_20, S => \bo_5842_d\, Y - => N_458); - - \r.hlocken_RNI8OP6\ : OR2A - port map(A => req_0, B => hlocken, Y => hlocken_0); - - \r.bg\ : DFN1 - port map(D => bg_RNO, CLK => lclk_c, Q => bg); - - \r.bo_RNITQI7[0]\ : MX2C - port map(A => data_0_d0, B => data_0_0, S => \bo_5842_d_0\, - Y => N_457); - - \r.bo_RNID98P7[0]\ : MX2 - port map(A => address_0(30), B => address(30), S => - \nbo_5_0[0]\, Y => N_4986); - - \r.ba_RNI7OED\ : NOR2B - port map(A => req_1, B => \ba\, Y => un6_dreq_0); - - \r.bg_RNIMDNL1\ : OR3C - port map(A => req, B => bg, C => iosn_0(93), Y => - dgrant_0_sqmuxa_1); - - \r.nbo_RNISOR4J[1]\ : MX2C - port map(A => N_4976, B => N_5008, S => \nbo_5[1]\, Y => - haddr(20)); - - \r.nbo[0]\ : DFN1 - port map(D => N_5620_i, CLK => lclk_c, Q => \nbo[0]\); - - \r.bo_RNO_8[0]\ : OR3C - port map(A => \bo_ns_0_a7_0[0]\, B => N_6030, C => N_6049, - Y => N_6036); - - \r.lb_RNO_0\ : MX2 - port map(A => lb, B => lb_0_sqmuxa, S => iosn_1(93), Y => - N_5541); - - \r.bo_RNILPOG[0]\ : MX2 - port map(A => data_23, B => data_0_23, S => \bo_5842_d\, Y - => N_459); - - \r.bo_RNIBNJ7[0]\ : MX2C - port map(A => data_7, B => data_0_7, S => \bo_5842_d\, Y - => hwdata_4); - - \r.bo_RNO_0[0]\ : MX2 - port map(A => \bo[0]\, B => \bo_ns[0]\, S => iosn_1(93), Y - => N_5939); - - \r.retry2_RNIHCJF\ : AO1A - port map(A => \ba\, B => retry2, C => nba, Y => N_6040_2); - - \r.hcache_RNO_1\ : OR2B - port map(A => \grant\, B => \grant_0\, Y => hcache_1_0); - - un20_haddr_1_CO1 : OR2B - port map(A => address_0(3), B => address_0(2), Y => CO1); - - \r.nbo_RNIHN2CB[1]\ : OA1A - port map(A => size(1), B => \nbo_5[1]\, C => \nbo_5[0]\, Y - => hsize_5(1)); - - \r.bo_RNIFD8P7[0]\ : MX2 - port map(A => address_0(31), B => address(31), S => - \nbo_5_0[0]\, Y => N_4987); - - \r.bo_RNO_6[1]\ : AO1C - port map(A => req_0, B => \ba\, C => \bo[1]\, Y => - \bo_ns_i_o7_0_0[1]\); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_1\ : NOR2 - port map(A => address(22), B => address(23), Y => - un569_dec_hcache_NE_1); - - \r.bo_RNI8LOP7[0]\ : NOR2A - port map(A => address_1(19), B => \nbo_5[0]\, Y => N_5007); - - \r.ba_RNIRM3H\ : OR2A - port map(A => un71_nbo_0, B => \bo_d[2]\, Y => un71_nbo); - - \r.bo_RNIJPOG[0]\ : MX2C - port map(A => data_14, B => data_0_14, S => \bo_5842_d_0\, - Y => hwdata_11); - - \r.nbo_RNIFH3IK[1]\ : MX2C - port map(A => N_4960, B => N_4992, S => \nbo_5_0[1]\, Y => - haddr(4)); - - \r.bo_RNIFH8P7[0]\ : MX2 - port map(A => address_0(23), B => address(23), S => - \nbo_5_0[0]\, Y => N_4979); - - \r.retry2_RNO\ : NOR2A - port map(A => rst, B => retry2_RNILAS7, Y => retry2_RNO); - - \r.bo_RNI5G0Q7[0]\ : MX2 - port map(A => address_0(5), B => address_1(5), S => - \nbo_5_1[0]\, Y => N_4961); - - \r.ba_RNI2OED\ : NOR2B - port map(A => req, B => \ba\, Y => un71_nbo_0); - - \r.bo_RNIPUK3_0[0]\ : OR2A - port map(A => \bo[0]\, B => \bo[1]\, Y => \bo_d[2]\); - - \r.bo_RNI6DOP7[0]\ : NOR2A - port map(A => address_1(17), B => \nbo_5[0]\, Y => N_5005); - - \r.bo_RNI0HNP7[0]\ : NOR2A - port map(A => address_1(20), B => \nbo_5_1[0]\, Y => N_5008); - - \r.nbo_RNI29S4J[1]\ : MX2C - port map(A => N_4978, B => N_5010, S => \nbo_5_0[1]\, Y => - haddr(22)); - - \r.bg_RNIOE4OO\ : OA1A - port map(A => bg, B => un10_hbusreq, C => hbusreq_0, Y => - hbusreq); - - \r.bo_RNILLOG[0]\ : MX2 - port map(A => data_31, B => data_0_31, S => \bo_5842_d\, Y - => hwdata_28); - - \r.nbo_RNO[0]\ : OA1 - port map(A => nbo95, B => \nbo_5[0]\, C => rst, Y => - N_5620_i); - - \r.hlocken_RNO_0\ : MX2 - port map(A => hlocken, B => hlocken_2, S => iosn_1(93), Y - => N_5539); - - \r.bo_RNIV28P[0]\ : MX2 - port map(A => \bo[0]\, B => \nbo_m_0[0]\, S => - retry2_RNILAS7, Y => N_4258); - - \r.bo_RNIDNBJ7[0]\ : MX2 - port map(A => N_5210_i_0, B => N_4258, S => N_6040_2, Y => - \nbo_5[0]\); - - \r.nbo_RNII8CAK[1]\ : MX2C - port map(A => N_4959, B => N_4991, S => \nbo_5_0[1]\, Y => - haddr(3)); - - \r.nbo_RNIHDLAB[1]\ : AO1D - port map(A => burst, B => \nbo_5_0[0]\, C => \nbo_5_0[1]\, - Y => \hburst_1_i_0[0]\); - - \r.ba_RNITG7V1\ : OR2A - port map(A => hresp(0), B => ready_1, Y => mmmexc_2_sqmuxa); - - \r.nbo[1]\ : DFN1 - port map(D => \nbo_RNO[1]\, CLK => lclk_c, Q => \nbo[1]\); - - \r.bg_RNIR7VQC\ : OR2A - port map(A => igrant_0_sqmuxa_1, B => un30_nbo, Y => - \grant_0\); - - \r.ba_RNI6ANVJ\ : NOR2B - port map(A => un11_hbusreq, B => \N_5054\, Y => - un10_hbusreq); - - \r.bo_RNI69OP7[0]\ : NOR2A - port map(A => address_1(26), B => \nbo_5_0[0]\, Y => N_5014); - - \r.bo_RNO_3[1]\ : OAI1 - port map(A => N_6027, B => \bo_ns_i_o7_0_0[1]\, C => - \bo_ns_i_a7_0[1]\, Y => N_6043); - - \r.bo_RNIJLOG[0]\ : MX2 - port map(A => data_22, B => data_0_22, S => \bo_5842_d\, Y - => N_468); - - \r.bo_RNID01Q7[0]\ : MX2 - port map(A => address(9), B => address_0(9), S => - \nbo_5_1[0]\, Y => N_4965); - - \r.bo_RNIVGNP7[0]\ : OR2A - port map(A => address_1(10), B => \nbo_5_1[0]\, Y => N_4998); - - \r.bo_RNI998P7[0]\ : MX2 - port map(A => address(12), B => address_0(12), S => - \nbo_5_1[0]\, Y => N_4968); - - \r.nba_RNIMTLD\ : NOR2A - port map(A => req, B => nba, Y => N_6049); - - \r.bo_RNIT9PG[0]\ : MX2 - port map(A => data_27, B => data_0_27, S => \bo_5842_d_0\, - Y => N_139); - - \r.bo_RNI2TNP7[0]\ : NOR2A - port map(A => address(13), B => \nbo_5[0]\, Y => N_5001); - - \r.bo_RNI1HNP7[0]\ : NOR2A - port map(A => address_1(30), B => \nbo_5[0]\, Y => N_5018); - - \r.bo_RNIL19P7[0]\ : MX2 - port map(A => address(18), B => address_0(18), S => - \nbo_5_0[0]\, Y => N_4974); - - \r.retry2_RNILAS7\ : OR2A - port map(A => retry2, B => \ba\, Y => retry2_RNILAS7); - - \r.bo_RNI2PNP7[0]\ : NOR2A - port map(A => address_1(22), B => \nbo_5_1[0]\, Y => N_5010); - - \r.bo[1]\ : DFN1 - port map(D => N_5940s, CLK => lclk_c, Q => \bo[1]\); - - \r.bo_RNI758P7[0]\ : MX2C - port map(A => address(11), B => address_0(11), S => - \nbo_5[0]\, Y => N_4967); - - \r.ba_RNI0HBMB\ : OR2 - port map(A => un30_nbo, B => un6_dreq, Y => \lb_0_sqmuxa_1\); - - \r.bo_RNI958P7[0]\ : MX2 - port map(A => address_0(20), B => address(20), S => - \nbo_5_1[0]\, Y => N_4976); - - \r.werr_RNO_1\ : OR2A - port map(A => \mexc\, B => read_0, Y => hwrite_1_m); - - \r.bo_RNIHP8P7[0]\ : MX2 - port map(A => address(16), B => address_0(16), S => - \nbo_5[0]\, Y => N_4972); - - \r.hlocken_RNIU579\ : NOR2A - port map(A => hlocken, B => retry2_RNILAS7, Y => un5_hlock); - - \r.bo_RNI41OP7[0]\ : NOR2A - port map(A => address_1(24), B => \nbo_5_0[0]\, Y => N_5012); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_5\ : NOR3A - port map(A => un569_dec_hcache_NE_1, B => address(21), C - => address(20), Y => un569_dec_hcache_NE_5); - - \r.hcache\ : DFN1 - port map(D => hcache_RNO, CLK => lclk_c, Q => \hcache_1\); - - \r.bo_RNIN59P7[0]\ : MX2 - port map(A => address(19), B => address_0(19), S => - \nbo_5_1[0]\, Y => N_4975); - - \r.bo_RNO_11[0]\ : OR2A - port map(A => req_1, B => \bo[0]\, Y => N_6030); - - \r.bo_RNI9O0Q7[0]\ : MX2 - port map(A => address(7), B => address_0(7), S => - \nbo_5[0]\, Y => N_4963); - - \r.bg_RNIO1K8T\ : NOR3C - port map(A => iosn_0(93), B => bg, C => \htrans[1]\, Y => - bg_m); - - \r.retry2_RNI1QM9\ : MX2A - port map(A => retry2, B => \bo[0]\, S => \ba\, Y => N_6027); - - \r.nbo_RNICDT4J[1]\ : MX2C - port map(A => N_4973, B => N_5005, S => \nbo_5[1]\, Y => - haddr(17)); - - \r.ba_RNIJPV24\ : NOR2A - port map(A => un6_dreq, B => \nbo_5_0[1]\, Y => - htrans_1_sqmuxa_0); - - \r.bo_RNO_5[1]\ : NOR3B - port map(A => \ba\, B => \bo[1]\, C => req_0, Y => - \bo_RNO_5[1]\); - - \r.bo_RNO_7[1]\ : NOR2A - port map(A => N_6043_1, B => nba, Y => \bo_ns_i_a7_0[1]\); - - \r.bo_RNIL3KL7[0]\ : NOR2A - port map(A => address_1(7), B => \nbo_5[0]\, Y => N_4995); - - GND_i : GND - port map(Y => \GND\); - - \comb.un87_nbo\ : AO1B - port map(A => un88_nbo_0, B => hcache, C => size_1z, Y => - un87_nbo); - - \r.nba_0_RNO\ : AND2 - port map(A => \htrans[1]\, B => rst, Y => nba_0_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.bo_RNIMFS22_0[0]\ : NOR2 - port map(A => \bo_d[2]\, B => mmmexc_2_sqmuxa, Y => - \mexc_0\); - - \r.retry2\ : DFN1 - port map(D => retry2_RNO, CLK => lclk_c, Q => retry2); - - \r.bo_RNO_8[1]\ : OR3B - port map(A => nba, B => retry2_RNILAS7, C => \nbo[1]\, Y - => \bo_RNO_8[1]\); - - \r.bg_RNIRE7L1\ : NOR3C - port map(A => req_0, B => bg, C => iosn_0(93), Y => - mmgrant_0_sqmuxa_1); - - \r.nbo_RNI9O78B[1]\ : OR2 - port map(A => read, B => \un59_nbo\, Y => werr_2_m_0); - - \r.bo_RNIVUI7[0]\ : MX2 - port map(A => data_1, B => data_0_1, S => \bo_5842_d\, Y - => N_466); - - \r.bg_RNIR8FQC\ : OR2B - port map(A => mmgrant_0_sqmuxa_1, B => un19_nbo, Y => - \grant\); - - \r.bo_RNI5BJ7[0]\ : MX2 - port map(A => data_4, B => data_0_4, S => \bo_5842_d\, Y - => hwdata_1); - - \r.bo_RNIHHOG[0]\ : MX2 - port map(A => data_21, B => data_0_21, S => \bo_5842_d\, Y - => N_463); - - \r.bo_RNIP59P7[0]\ : MX2 - port map(A => address_1(28), B => address(28), S => - \nbo_5[0]\, Y => N_4984); - - \r.nbo_RNIJ2SH3_0[1]\ : MX2A - port map(A => un14_dreq, B => N_4259, S => N_6040_2, Y => - \nbo_5[1]\); - - \r.nbo_RNI1TR4J[1]\ : MX2C - port map(A => N_4986, B => N_5018, S => \nbo_5[1]\, Y => - haddr(30)); - - \r.bo_RNO_10[0]\ : NOR2A - port map(A => \ba\, B => \bo[1]\, Y => \bo_ns_0_a7_0[0]\); - - \r.bo[0]\ : DFN1 - port map(D => N_5939s, CLK => lclk_c, Q => \bo[0]\); - - \r.nbo_RNIT4S4J[1]\ : MX2C - port map(A => N_4968, B => N_5000, S => \nbo_5_0[1]\, Y => - haddr(12)); - - \r.ba_RNIR7F7C\ : MX2C - port map(A => htrans_1_sqmuxa_0, B => un71_nbo, S => - \nbo_5_0[0]\, Y => \un1_htrans_1_sqmuxa_0\); - - \r.nba_0\ : AND2 - port map(A => ba_3, B => nba_0_0, Y => N_5618_i); - - \r.ba_RNIFGDJ1\ : OR2 - port map(A => ready_1, B => \bo_d[3]\, Y => ready_0); - - \r.bo_RNIP5PG[0]\ : MX2C - port map(A => data_17, B => data_0_17, S => \bo_5842_d\, Y - => hwdata_14); - - \r.ba_RNI8OP11\ : AX1B - port map(A => CO1, B => un71_nbo, C => address_1(4), Y => - \haddr_10[4]\); - - \r.nbo_RNIBMG1J[1]\ : MX2C - port map(A => N_4961, B => N_4993, S => \nbo_5_0[1]\, Y => - haddr(5)); - - \r.bo_RNO_9[1]\ : AO1 - port map(A => N_6050, B => retry2_RNILAS7, C => \bo[1]\, Y - => N_6044); - - htrans_4_sqmuxa_1_1_RNISFROR : AO1B - port map(A => \un1_htrans_1_sqmuxa_0\, B => \un60_nbo\, C - => \htrans_tz[1]\, Y => \htrans[1]\); - - \r.bo_RNILT8P7[0]\ : MX2 - port map(A => address_0(26), B => address(26), S => - \nbo_5_0[0]\, Y => N_4982); - - \r.bo_RNIE2S29[0]\ : MX2C - port map(A => \haddr_6[3]\, B => \haddr_10[3]\, S => - \nbo_5_1[0]\, Y => N_4959); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.lb\ : DFN1 - port map(D => lb_RNO, CLK => lclk_c, Q => lb); - - \r.bo_RNIJT8P7[0]\ : MX2 - port map(A => address(17), B => address_0(17), S => - \nbo_5[0]\, Y => N_4973); - - \r.ba\ : DFN1 - port map(D => ba_RNO, CLK => lclk_c, Q => \ba\); - - htrans_4_sqmuxa_1_1 : NOR2 - port map(A => un15_dreq_i, B => htrans_4_sqmuxa_1_1_0, Y - => \htrans_4_sqmuxa_1_1\); - - \r.bo_RNIR5PG[0]\ : MX2 - port map(A => data_26, B => data_0_26, S => \bo_5842_d\, Y - => hwdata_23); - - \r.bo_RNO_4[1]\ : NOR3C - port map(A => \bo_RNO_8[1]\, B => \bo_RNI35I6[0]\, C => - N_6044, Y => \bo_ns_i_2[1]\); - - \r.bo_RNIJP8P7[0]\ : MX2 - port map(A => address_0(25), B => address(25), S => - \nbo_5_0[0]\, Y => N_4981); - - \r.bo_RNO[1]\ : NOR2B - port map(A => rst, B => N_5940, Y => N_5940s); - - \r.bo_RNO_2[0]\ : NOR3C - port map(A => N_6039, B => \bo_RNI35I6[0]\, C => N_6037, Y - => \bo_ns_0_3[0]\); - - \r.werr\ : DFN1 - port map(D => werr_RNO, CLK => lclk_c, Q => werr); - - \r.ba_RNIFGDJ1_0\ : NOR2 - port map(A => ready_1, B => \bo_d[2]\, Y => ready); - - \r.nbo_RNIITT4J[1]\ : MX2C - port map(A => N_4975, B => N_5007, S => \nbo_5[1]\, Y => - haddr(19)); - - \r.bo_RNIPOS8B[0]\ : XAI1A - port map(A => \nbo_5[1]\, B => \nbo_5[0]\, C => \bo_d[2]\, - Y => hlock_1_sqmuxa); - - \r.bo_RNIFVJ7[0]\ : MX2 - port map(A => data_9, B => data_0_9, S => \bo_5842_d\, Y - => N_461); - - \r.nbo_RNIQSR4J[1]\ : MX2C - port map(A => N_4967, B => N_4999, S => \nbo_5[1]\, Y => - haddr(11)); - - \r.bo_RNIMFS22_1[0]\ : NOR2 - port map(A => \bo_5842_d\, B => mmmexc_2_sqmuxa, Y => - \mexc\); - - \r.nbo_RNI0DS4J[1]\ : MX2C - port map(A => N_4969, B => N_5001, S => \nbo_5[1]\, Y => - haddr(13)); - - \r.bo_RNI7DOP7[0]\ : NOR2A - port map(A => address_1(27), B => \nbo_5[0]\, Y => N_5015); - - \r.ba_RNO\ : OA1 - port map(A => bg_m, B => ba_m, C => rst, Y => ba_RNO); - - \r.ba_RNIRGBMB\ : OR2 - port map(A => un71_nbo, B => \un59_nbo\, Y => - htrans_0_sqmuxa_2); - - \r.lb_RNO_2\ : OR3A - port map(A => address(2), B => address(3), C => \N_6093_i\, - Y => lb_0_sqmuxa_0); - - \r.bo_RNIR9PG[0]\ : MX2C - port map(A => data_18, B => data_0_18, S => \bo_5842_d\, Y - => hwdata_15); - - htrans_4_sqmuxa_1_1_RNO : OR2 - port map(A => N_6040_2, B => un17_dreq, Y => - htrans_4_sqmuxa_1_1_0); - - \r.bo_RNO_1[0]\ : OR3C - port map(A => \bo_ns_0_3[0]\, B => \bo_ns_0_2[0]\, C => - N_6040, Y => \bo_ns[0]\); - - \r.hlocken\ : DFN1 - port map(D => hlocken_RNO, CLK => lclk_c, Q => hlocken); - - \r.bo_RNIPOS8B_0[0]\ : OR2B - port map(A => \bo_d[2]\, B => un19_nbo, Y => hlock_0_sqmuxa); - - \r.bo_RNIN3KL7[0]\ : NOR2A - port map(A => address_1(9), B => \nbo_5_1[0]\, Y => N_4997); - - \r.bo_RNIDDOG[0]\ : MX2 - port map(A => data_11, B => data_0_11, S => \bo_5842_d_0\, - Y => N_462); - - \r.nbo_RNIE9T4J[1]\ : MX2C - port map(A => N_4982, B => N_5014, S => \nbo_5_0[1]\, Y => - haddr(26)); - - \r.bo_RNI1PNP7[0]\ : NOR2A - port map(A => address_1(12), B => \nbo_5_1[0]\, Y => N_5000); - - \r.bo_RNI7HOP7[0]\ : NOR2A - port map(A => address_1(18), B => \nbo_5_0[0]\, Y => N_5006); - - \r.ba_RNI436I\ : XOR2 - port map(A => address(2), B => un6_dreq, Y => - \haddr_6_i[2]\); - - \r.nba_RNILPKJ\ : OR2A - port map(A => N_6049, B => req_1, Y => N_6050); - - \r.bo_RNI8HOP7[0]\ : NOR2A - port map(A => address_0(28), B => \nbo_5[0]\, Y => N_5016); - - \r.bo_RNII3KL7[0]\ : OR2A - port map(A => address_0(4), B => \nbo_5_0[0]\, Y => N_4992); - - \r.hlocken_RNI4AJRB\ : OR2A - port map(A => lock_m, B => nbo95, Y => N_4302); - - \r.bo_RNI2LNP7[0]\ : NOR2A - port map(A => address_1(31), B => \nbo_5[0]\, Y => N_5019); - - \r.ba_RNI1R4B\ : OR2B - port map(A => \ba\, B => \bo_d[3]\, Y => un11_hbusreq); - - \r.ba_RNION7S\ : AX1A - port map(A => un71_nbo, B => address_0(2), C => - address_0(3), Y => \haddr_10[3]\); - - \r.bo_RNIN19P7[0]\ : MX2 - port map(A => address_0(27), B => address(27), S => - \nbo_5_0[0]\, Y => N_4983); - - \r.ba_RNI0N3H\ : OR2A - port map(A => un6_dreq_0, B => \bo_d[3]\, Y => un6_dreq); - - \r.nbo_RNIU8HF[0]\ : NOR2B - port map(A => \nbo[0]\, B => nba, Y => \nbo_m_0[0]\); - - \r.nbo_RNIB1T4J[1]\ : MX2C - port map(A => N_4981, B => N_5013, S => \nbo_5_0[1]\, Y => - haddr(25)); - - \r.ba_RNILRDL\ : MX2A - port map(A => \N_6093_i\, B => address(4), S => un6_dreq, Y - => \haddr_6[4]\); - - \r.bo_RNIHL8P7[0]\ : MX2 - port map(A => address_0(24), B => address(24), S => - \nbo_5_0[0]\, Y => N_4980); - - \r.bo_RNIK3KL7[0]\ : NOR2A - port map(A => address_1(6), B => \nbo_5[0]\, Y => N_4994); - - \r.retry2_RNI0GK4\ : OR2 - port map(A => retry2, B => un17_dreq, Y => dgrant_1); - - \r.ba_RNIK1T98\ : NOR3B - port map(A => un71_nbo, B => \nbo_5_0[0]\, C => burst_0, Y - => N_5056); - - \r.bo_RNIPUK3_2[0]\ : OR2 - port map(A => \bo[1]\, B => \bo[0]\, Y => \bo_d[3]\); - - \r.ba_RNIT7GA6\ : AO1D - port map(A => un3_dreq, B => nbo4, C => htrans_4_sqmuxa_1_0, - Y => N_5210_i_0); - - \r.hcache_RNO_0\ : MX2 - port map(A => \hcache_1\, B => hcache, S => dgrant_0_sqmuxa, - Y => N_5540); - - \r.nbo_RNIN1U4J[1]\ : MX2C - port map(A => N_4985, B => N_5017, S => \nbo_5_0[1]\, Y => - haddr(29)); - - \r.nbo_RNIJ2SH3[1]\ : MX2A - port map(A => un14_dreq, B => N_4259, S => N_6040_2, Y => - \nbo_5_0[1]\); - - \r.nbo_RNI0Q75B_0[1]\ : OR2A - port map(A => \nbo_5[0]\, B => \nbo_5[1]\, Y => \un59_nbo\); - - \r.nbo_RNI0Q75B[1]\ : OR2B - port map(A => \nbo_5[1]\, B => \nbo_5[0]\, Y => \un60_nbo\); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_6\ : NOR3A - port map(A => un569_dec_hcache_NE_3, B => address(25), C - => address(24), Y => un569_dec_hcache_NE_6_0); - - \r.retry2_RNIMNJVC\ : NOR2B - port map(A => dgrant_0_sqmuxa, B => dgrant_1, Y => grant_1); - - \r.bo_RNIJHOG[0]\ : MX2 - port map(A => data_30, B => data_0_30, S => \bo_5842_d_0\, - Y => hwdata_27); - - \r.nbo_RNIEQG1J[1]\ : MX2C - port map(A => N_4962, B => N_4994, S => \nbo_5[1]\, Y => - haddr(6)); - - \comb.ahb_slv_dec_cache.hcache_0\ : AO1A - port map(A => address(30), B => address(29), C => - address(31), Y => hcache_0); - - \r.bo_RNIM3KL7[0]\ : NOR2A - port map(A => address_1(8), B => \nbo_5_1[0]\, Y => N_4996); - - \r.ba_RNI9J8J\ : AX1A - port map(A => un6_dreq, B => address(2), C => address(3), Y - => \haddr_6[3]\); - - \comb.un15_dreq\ : OR2 - port map(A => un3_dreq, B => nbo4, Y => un15_dreq_i); - - \r.hlocken_RNO\ : NOR2B - port map(A => rst, B => N_5539, Y => hlocken_RNO); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_3\ : NOR2 - port map(A => address(26), B => address(27), Y => - un569_dec_hcache_NE_3); - - \r.bo_RNIABJA9[0]\ : MX2C - port map(A => \haddr_6[4]\, B => \haddr_10[4]\, S => - \nbo_5_0[0]\, Y => N_4960); - - \r.ba_RNI0OJG\ : NOR3B - port map(A => \ba\, B => req_0, C => \bo_5842_d_0\, Y => - un11_dreq); - - \r.werr_RNO\ : AOI1B - port map(A => werr_2_m, B => hwrite_1_m, C => rst, Y => - werr_RNO); - - \r.bo_RNIBS0Q7[0]\ : MX2 - port map(A => address(8), B => address_0(8), S => - \nbo_5_1[0]\, Y => N_4964); - - \r.bo_RNI9LOP7[0]\ : OR2A - port map(A => address_1(29), B => \nbo_5_0[0]\, Y => N_5017); - - \comb.ahb_slv_dec_cache.6.4.un509_dec_hcache_NE\ : OR3B - port map(A => address(28), B => un569_dec_hcache_NE_6, C - => address(29), Y => un509_dec_hcache_NE); - - \r.nbo_RNI6TS4J[1]\ : MX2C - port map(A => N_4971, B => N_5003, S => \nbo_5[1]\, Y => - haddr(15)); - - \r.lb_RNO_1\ : NOR2 - port map(A => lb_0_sqmuxa_0, B => \lb_0_sqmuxa_1\, Y => - lb_0_sqmuxa); - - \r.hlocken_RNO_1\ : NOR2 - port map(A => \hlock\, B => hgrant(0), Y => hlocken_2); - - \r.bo_RNIMFS22[0]\ : OR2 - port map(A => \bo_d[3]\, B => mmmexc_2_sqmuxa, Y => mexc_1); - - \r.bg_RNO\ : NOR2B - port map(A => rst, B => N_5542, Y => bg_RNO); - - \comb.v.ba_3_iv\ : NOR2 - port map(A => bg_m, B => ba_m, Y => ba_3); - - \r.nbo_RNI9H2GC[1]\ : OR2A - port map(A => un87_nbo, B => \un59_nbo\, Y => un91_nbo_i_0); - - \r.bo_RNO_7[0]\ : OR3 - port map(A => retry2, B => \ba\, C => N_6050, Y => N_6042); - - \r.bo_RNIQH7S8[0]\ : MX2C - port map(A => \haddr_6_i[2]\, B => \haddr_10_i[2]\, S => - \nbo_5_1[0]\, Y => N_4958); - - \r.bo_RNO_4[0]\ : OR3 - port map(A => req_1, B => req_0, C => N_6040_2, Y => N_6040); - - \r.bo_RNI7K0Q7[0]\ : MX2 - port map(A => address(6), B => address_0(6), S => - \nbo_5[0]\, Y => N_4962); - - \r.nbo_RNO[1]\ : NOR3B - port map(A => rst, B => \nbo_5_0[1]\, C => nbo95, Y => - \nbo_RNO[1]\); - - \r.lb_RNI48TG4\ : OA1C - port map(A => htrans_4_sqmuxa_1_0, B => N_6040_2, C => lb, - Y => hbusreq_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.bo_RNO_6[0]\ : AO1B - port map(A => N_6050, B => retry2_RNILAS7, C => \bo[0]\, Y - => N_6037); - - \r.bo_RNIFL8P7[0]\ : MX2 - port map(A => address(15), B => address_0(15), S => - \nbo_5_1[0]\, Y => N_4971); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE\ : OR3C - port map(A => un569_dec_hcache_NE_6_0, B => - un569_dec_hcache_NE_5, C => un569_dec_hcache_NE_7, Y => - un569_dec_hcache_NE); - - \r.bo_RNO_5[0]\ : OR3B - port map(A => hlocken, B => retry2_RNILAS7, C => nba, Y => - N_6039); - - \r.nbo_RNIMNB8B[1]\ : OR2A - port map(A => un19_nbo, B => read_0, Y => hwrite_1_m_0); - - \r.hlocken_RNI3EDO\ : OR2B - port map(A => N_6043_1, B => un71_nbo, Y => nbo4_0); - - \r.nba\ : DFN1 - port map(D => N_5618_i, CLK => lclk_c, Q => nba); - - \r.bo_RNO_2[1]\ : OAI1 - port map(A => N_6027, B => \bo_RNO_5[1]\, C => N_6049, Y - => \bo_RNO_2[1]\); - - \r.bo_RNI37J7[0]\ : MX2 - port map(A => data_3, B => data_0_3, S => \bo_5842_d\, Y - => hwdata_0); - - \r.bo_RNO[0]\ : NOR2B - port map(A => rst, B => N_5939, Y => N_5939s); - - \r.bo_RNI0LNP7[0]\ : OR2A - port map(A => address_1(11), B => \nbo_5[0]\, Y => N_4999); - - \r.nbo_RNI45S4J[1]\ : MX2C - port map(A => N_4987, B => N_5019, S => \nbo_5[1]\, Y => - haddr(31)); - - \r.nbo_RNIHUG1J[1]\ : MX2C - port map(A => N_4963, B => N_4995, S => \nbo_5[1]\, Y => - haddr(7)); - - \r.hlocken_RNI8FTN\ : OR2A - port map(A => un6_dreq, B => hlocken_0, Y => hlocken_1); - - \r.bo_RNIDNBJ7_1[0]\ : MX2 - port map(A => N_5210_i_0, B => N_4258, S => N_6040_2, Y => - \nbo_5_0[0]\); - - \r.ba_RNITGNG2\ : OR2A - port map(A => un3_dreq, B => nbo4, Y => un14_dreq); - - \r.nbo_RNIFLT4J[1]\ : MX2C - port map(A => N_4974, B => N_5006, S => \nbo_5_0[1]\, Y => - haddr(18)); - - \r.bo_RNIMRCD21[0]\ : OR3C - port map(A => N_4302, B => hlock_0_sqmuxa, C => - hlock_1_sqmuxa, Y => \hlock\); - - \r.bo_RNIJ3KL7[0]\ : NOR2A - port map(A => address(5), B => \nbo_5_1[0]\, Y => N_4993); - - \r.ba_RNIQAM71\ : OR3B - port map(A => un6_dreq, B => req, C => un11_dreq, Y => - un3_dreq); - - \r.nbo_RNI5HS4J[1]\ : MX2C - port map(A => N_4979, B => N_5011, S => \nbo_5_0[1]\, Y => - haddr(23)); - - \r.werr_RNO_0\ : OR2A - port map(A => \mexc_0\, B => read, Y => werr_2_m); - - \r.nbo_RNI55HH[1]\ : MX2 - port map(A => \bo[1]\, B => \nbo[1]\, S => retry2_RNILAS7, - Y => N_4259); - - \r.nbo_RNIKPT4J[1]\ : MX2C - port map(A => N_4984, B => N_5016, S => \nbo_5[1]\, Y => - haddr(28)); - - \r.nbo_RNIK2H1J[1]\ : MX2C - port map(A => N_4964, B => N_4996, S => \nbo_5_0[1]\, Y => - haddr(8)); - - \r.bo_RNI13J7[0]\ : MX2C - port map(A => data_2, B => data_0_2, S => \bo_5842_d_0\, Y - => N_467); - - \r.bo_RNIH3KL7[0]\ : NOR2A - port map(A => address_1(3), B => \nbo_5_1[0]\, Y => N_4991); - - \r.bo_RNO_1[1]\ : NOR3C - port map(A => \bo_RNO_2[1]\, B => N_6043, C => - \bo_ns_i_2[1]\, Y => N_6025_i_0); - - \r.bo_RNIFHOG[0]\ : MX2C - port map(A => data_12, B => data_0_12, S => \bo_5842_d_0\, - Y => hwdata_9); - - \r.ba_RNIMHOF1_0\ : NOR2A - port map(A => \ba\, B => iosn_2(93), Y => ba_m); - - \r.hlocken_RNIJ184\ : OR2A - port map(A => lock, B => hlocken, Y => un17_dreq); - - \r.bo_RNIVDPG[0]\ : MX2 - port map(A => data_28, B => data_0_28, S => \bo_5842_d_0\, - Y => hwdata_25); - - \r.bo_RNI1LNP7[0]\ : NOR2A - port map(A => address_1(21), B => \nbo_5_0[0]\, Y => N_5009); - - \r.bo_RNIR99P7[0]\ : MX2C - port map(A => address_0(29), B => address(29), S => - \nbo_5_0[0]\, Y => N_4985); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_7\ : NOR3B - port map(A => address(29), B => un569_dec_hcache_NE_6, C - => address(28), Y => un569_dec_hcache_NE_7); - - \comb.ahb_slv_dec_cache.6.4.un509_dec_hcache_NE_2\ : NOR2A - port map(A => address(31), B => address(30), Y => - un569_dec_hcache_NE_6); - - \r.hlocken_RNI1BPF\ : OA1B - port map(A => un5_hlock, B => lock, C => \bo_d[2]\, Y => - nbo95); - - \r.bo_RNITDPG[0]\ : MX2C - port map(A => data_19, B => data_0_19, S => \bo_5842_d_0\, - Y => hwdata_16); - - \r.nbo_RNI0Q75B_1[1]\ : NOR2A - port map(A => \nbo_5[1]\, B => \nbo_5[0]\, Y => un19_nbo); - - \r.ba_RNI9NLM\ : XOR2 - port map(A => address_0(2), B => un71_nbo, Y => - \haddr_10_i[2]\); - - \r.bo_RNIPUK3_1[0]\ : OR2A - port map(A => \bo[1]\, B => \bo[0]\, Y => \bo_5842_d\); - - \r.ba_RNI36191\ : NOR2 - port map(A => nbo4_0, B => un11_dreq, Y => nbo4); - - \r.ba_RNI5FIKJ\ : NOR2 - port map(A => \hburst_1_i_0[0]\, B => N_5056, Y => \N_5054\); - - \r.bo_RNILTOG[0]\ : MX2C - port map(A => data_15, B => data_0_15, S => \bo_5842_d\, Y - => hwdata_12); - - \r.bo_RNI59OP7[0]\ : NOR2A - port map(A => address_1(16), B => \nbo_5[0]\, Y => N_5004); - - \r.bo_RNO_9[0]\ : OR2B - port map(A => \nbo_m_0[0]\, B => retry2_RNILAS7, Y => - \nbo_m[0]\); - - \r.bo_RNI518P7[0]\ : MX2C - port map(A => address(10), B => address_0(10), S => - \nbo_5_1[0]\, Y => N_4966); - - \r.bo_RNO_0[1]\ : MX2 - port map(A => \bo[1]\, B => N_6025_i_0, S => iosn_1(93), Y - => N_5940); - - \r.bo_RNI31OP7[0]\ : NOR2A - port map(A => address_1(14), B => \nbo_5_1[0]\, Y => N_5002); - - \r.hlocken_RNI0NOP3\ : OA1C - port map(A => un71_nbo, B => hlocken_1, C => un14_dreq, Y - => htrans_4_sqmuxa_1_0); - - \r.bo_RNI3TNP7[0]\ : NOR2A - port map(A => address_1(23), B => \nbo_5_0[0]\, Y => N_5011); - - \r.nbo_RNIHHT4J[1]\ : MX2C - port map(A => N_4983, B => N_5015, S => \nbo_5[1]\, Y => - haddr(27)); - - \r.bo_RNIP1PG[0]\ : MX2 - port map(A => data_25, B => data_0_25, S => \bo_5842_d_0\, - Y => N_138); - - \r.bo_RNIN1PG[0]\ : MX2C - port map(A => data_16, B => data_0_16, S => \bo_5842_d_0\, - Y => hwdata_13); - - \r.bo_RNI55OP7[0]\ : NOR2A - port map(A => address_1(25), B => \nbo_5_1[0]\, Y => N_5013); - - \r.nbo_RNIV0S4J[1]\ : MX2C - port map(A => N_4977, B => N_5009, S => \nbo_5_0[1]\, Y => - haddr(21)); - - \r.ba_RNIMHOF1\ : OR2B - port map(A => iosn_2(93), B => \ba\, Y => ready_1); - - \r.bo_RNIDNBJ7_0[0]\ : MX2 - port map(A => N_5210_i_0, B => N_4258, S => N_6040_2, Y => - \nbo_5_1[0]\); - - \r.bo_RNI35I6[0]\ : OR2A - port map(A => lock, B => \bo_d[2]\, Y => \bo_RNI35I6[0]\); - - \r.nbo_RNI95T4J[1]\ : MX2C - port map(A => N_4972, B => N_5004, S => \nbo_5[1]\, Y => - haddr(16)); - - \r.nbo_RNITNN3K[1]\ : MX2C - port map(A => N_4958, B => N_4990, S => \nbo_5[1]\, Y => - haddr(2)); - - \comb.un88_nbo_0\ : NOR2B - port map(A => read, B => cache, Y => un88_nbo_0); - - \r.lb_RNO\ : NOR2B - port map(A => rst, B => N_5541, Y => lb_RNO); - - htrans_4_sqmuxa_1_1_RNI1E4C4 : AO1A - port map(A => N_6040_2, B => htrans_4_sqmuxa_1_0, C => - \htrans_4_sqmuxa_1_1\, Y => \htrans_tz[1]\); - - \comb.ahb_slv_dec_cache.hcache\ : OR3C - port map(A => hcache_0, B => un509_dec_hcache_NE, C => - un569_dec_hcache_NE, Y => hcache); - - \r.bg_RNIRDNL1\ : NOR3C - port map(A => req_1, B => bg, C => iosn_0(93), Y => - igrant_0_sqmuxa_1); - - \r.bo_RNI45OP7[0]\ : NOR2A - port map(A => address_1(15), B => \nbo_5_1[0]\, Y => N_5003); - - \r.hcache_RNO\ : OA1 - port map(A => N_5540, B => hcache_1_0, C => rst, Y => - hcache_RNO); - - \r.bg_RNIM7VQC\ : NOR2 - port map(A => dgrant_0_sqmuxa_1, B => \un59_nbo\, Y => - dgrant_0_sqmuxa); - - \r.bg_RNO_0\ : MX2B - port map(A => bg, B => hgrant(0), S => iosn_1(93), Y => - N_5542); - - \r.bo_RNIBD8P7[0]\ : MX2 - port map(A => address_0(13), B => address_1(13), S => - \nbo_5[0]\, Y => N_4969); - - \r.bo_RNI9JJ7[0]\ : MX2C - port map(A => data_6, B => data_0_6, S => \bo_5842_d_0\, Y - => hwdata_3); - - \r.nbo_RNI3LS4J[1]\ : MX2C - port map(A => N_4970, B => N_5002, S => \nbo_5[1]\, Y => - haddr(14)); - - \r.bo_RNIG3KL7[0]\ : NOR2A - port map(A => address_1(2), B => \nbo_5_1[0]\, Y => N_4990); - - \r.bo_RNO_3[0]\ : NOR3C - port map(A => N_6042, B => N_6036, C => \nbo_m[0]\, Y => - \bo_ns_0_2[0]\); - - \r.bo_RNIPUK3[0]\ : OR2A - port map(A => \bo[1]\, B => \bo[0]\, Y => \bo_5842_d_0\); - - un7_haddr_1_SUM2_0 : AX1E - port map(A => address(2), B => address(3), C => address(4), - Y => \N_6093_i\); - - \r.bo_RNIDD8P7[0]\ : MX2 - port map(A => address_0(22), B => address(22), S => - \nbo_5_0[0]\, Y => N_4978); - - \r.nbo_RNIN6H1J[1]\ : MX2C - port map(A => N_4965, B => N_4997, S => \nbo_5_0[1]\, Y => - haddr(9)); - - \r.nbo_RNI0Q75B_2[1]\ : OR2 - port map(A => \nbo_5_0[1]\, B => \nbo_5_1[0]\, Y => - un30_nbo); - - \r.nbo_RNINKR4J[1]\ : MX2C - port map(A => N_4966, B => N_4998, S => \nbo_5_0[1]\, Y => - haddr(10)); - - \r.hlocken_RNI8N97\ : NOR2A - port map(A => req_1, B => hlocken, Y => N_6043_1); - - \r.nbo_RNI8PS4J[1]\ : MX2C - port map(A => N_4980, B => N_5012, S => \nbo_5_0[1]\, Y => - haddr(24)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu_icache is - - port( istate_RNIJCMP6 : out std_logic_vector(0 to 0); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - ics : in std_logic_vector(1 downto 0); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - un1_p0_2_i_4 : out std_logic; - un1_p0_2_i_0 : out std_logic; - ctx_5 : in std_logic; - ctx_4 : in std_logic; - ctx_3 : in std_logic; - ctx_1 : in std_logic; - ctx_0_d0 : in std_logic; - istate_RNI6HPAI : out std_logic_vector(0 to 0); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - istate_RNI57KLB : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - un1_m0_30 : in std_logic; - un1_m0_5 : in std_logic; - un1_m0_9 : in std_logic; - un1_m0_8 : in std_logic; - un1_m0_1 : in std_logic; - un1_m0_22 : in std_logic; - un1_m0_6 : in std_logic; - un1_m0_0 : in std_logic; - un1_m0_17 : in std_logic; - un1_m0_16 : in std_logic; - un1_m0_7 : in std_logic; - un1_m0_4 : in std_logic; - un1_m0_2 : in std_logic; - un1_m0_3 : in std_logic; - istate_RNIH0NBI : out std_logic_vector(0 to 0); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - istate_RNI5V68H : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIEC82C : out std_logic_vector(0 to 0); - maddress_0_2 : in std_logic; - maddress_0_0 : in std_logic; - istate_RNIPSU8G : out std_logic_vector(0 to 0); - diagdata_6 : out std_logic; - diagdata_15 : out std_logic; - diagdata_4 : out std_logic; - diagdata_19 : out std_logic; - diagdata_18 : out std_logic; - diagdata_17 : out std_logic; - diagdata_16 : out std_logic; - diagdata_20 : out std_logic; - diagdata_26 : out std_logic; - diagdata_25 : out std_logic; - diagdata_22 : out std_logic; - diagdata_14 : out std_logic; - diagdata_12 : out std_logic; - diagdata_9 : out std_logic; - diagdata_8 : out std_logic; - diagdata_5 : out std_logic; - diagdata_3 : out std_logic; - diagdata_0 : out std_logic; - diagdata_7 : out std_logic; - diagdata_27 : out std_logic; - diagdata_23 : out std_logic; - diagdata_24 : out std_logic; - diagdata_31 : out std_logic; - diagdata_29 : out std_logic; - diagdata_28 : out std_logic; - diagdata_21 : out std_logic; - diagdata_13 : out std_logic; - diagdata_2 : out std_logic; - diagdata_30 : out std_logic; - diagdata_1 : out std_logic; - hrdata_26 : in std_logic; - hrdata_25 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - rpc_6 : in std_logic; - rpc_5 : in std_logic; - rpc_8 : in std_logic; - rpc_7 : in std_logic; - rpc_2 : in std_logic; - rpc_3 : in std_logic; - rpc_1 : in std_logic; - rpc_0 : in std_logic; - addr : in std_logic_vector(11 downto 2); - data_0 : out std_logic_vector(31 downto 0); - hrdata_0_3 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_15 : in std_logic; - istate_RNIA8N5H : out std_logic_vector(0 to 0); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - vitdatain_0_1_0 : in std_logic_vector(22 to 22); - fault_isid_1_i : in std_logic_vector(0 to 0); - dataout_1 : in std_logic_vector(31 downto 0); - dataout_0 : in std_logic_vector(35 downto 32); - ctx_0_5 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_4 : in std_logic; - address : out std_logic_vector(31 downto 2); - bo_d : in std_logic_vector(3 to 3); - un1_p0_6 : in std_logic_vector(0 to 0); - maddress : in std_logic_vector(31 downto 0); - dataout_2 : in std_logic_vector(31 downto 0); - fpc : in std_logic_vector(31 downto 2); - asi : in std_logic_vector(0 to 0); - un1_p0_2_0 : out std_logic_vector(148 to 148); - su_0 : in std_logic; - diagrdy : out std_logic; - hold_0 : out std_logic; - mexc_0 : out std_logic; - fbranch : in std_logic; - rbranch : in std_logic; - flush2_RNIFMGM2 : out std_logic; - N_425_1 : in std_logic; - flush2_RNI5I3N7 : out std_logic; - N_984 : out std_logic; - N_980 : out std_logic; - N_28 : in std_logic; - N_987 : out std_logic; - N_986 : out std_logic; - e : in std_logic; - flush2 : out std_logic; - N_26 : in std_logic; - flush2_0_0_RNI146O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - mds : out std_logic; - su : out std_logic; - nf : in std_logic; - N_981 : out std_logic; - N_429 : in std_logic; - N_359 : in std_logic; - N_2626 : in std_logic; - N_43 : in std_logic; - N_427 : in std_logic; - N_2625 : in std_logic; - N_6093_i : in std_logic; - N_423 : in std_logic; - N_425 : in std_logic; - N_45 : in std_logic; - N_2623 : in std_logic; - N_365 : in std_logic; - N_357 : in std_logic; - N_985 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_363 : in std_logic; - N_321 : in std_logic; - N_319 : in std_logic; - N_361 : in std_logic; - N_2624 : in std_logic; - N_264_0 : in std_logic; - N_262_0 : in std_logic; - N_78_0 : in std_logic; - inull : in std_logic; - hold : in std_logic; - ldlock_3_0 : in std_logic; - un9_icc_check_bp : in std_logic; - trans_op_0 : out std_logic; - flush_op_i_0 : in std_logic; - un2_m_tlb_type : in std_logic; - stpend_RNI6P41NG3 : in std_logic; - vaddr_1_sqmuxa_0_a2_2 : in std_logic; - ldlock_2 : in std_logic; - xc_exception_1_0 : in std_logic; - grant : in std_logic; - iflush_1_0_a2_0 : in std_logic; - N_121 : in std_logic; - un1_ici : out std_logic; - fault_trans_RNIA0K0D1 : in std_logic; - N_66_0 : in std_logic; - de_hold_pc_1 : in std_logic; - N_425_0 : in std_logic; - flush_0 : out std_logic; - flush : in std_logic; - trans_op : in std_logic; - ba : in std_logic; - hcache : in std_logic; - mexc : in std_logic; - req : out std_logic; - e_0 : in std_logic; - hold_pc_7 : in std_logic; - istate_0_sqmuxa : out std_logic; - flush_i_0 : in std_logic; - N_523 : in std_logic; - ready : in std_logic; - burst_0 : out std_logic; - burst : in std_logic; - rst : in std_logic; - un81_m_tlb_type : in std_logic; - holdn : out std_logic; - cdwrite_0_sqmuxa_i_0_0 : out std_logic; - N_66 : in std_logic; - enable : in std_logic; - lclk_c : in std_logic - ); - -end mmu_icache; - -architecture DEF_ARCH of mmu_icache is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \faddr_RNID788NI[6]\, idle_0, \istate[1]\, - \istate[0]\, diagen_0_sqmuxa_0, error_1_sqmuxa_0, - un5_m_en, N_1320, istate_1259_d_0, vaddress_0_sqmuxa_1, - un2_eholdn, vaddress_0_sqmuxa_0, holdn_RNIFCHA, N_20, - \faddr[1]\, \faddr[0]\, N_12, \faddr[3]\, - \DWACT_FINC_E[0]\, req_7_m, req_7, req_0_sqmuxa, - un1_ici_10_i_0, un1_ici_11_i_0, burst_1, burst_1_iv_0, - hit_1_6, burst_5_m, burst_2_m, req_1_0, N_1201, - \istate_ns_0_1[1]\, \istate_ns_0_0[1]\, underrun_1_sqmuxa, - N_1350, N_1348, trans_op_1_2, trans_op_1_0, - trans_op_RNO_4, trans_op_RNO_5, trans_op_0_a3_0, req_7_1, - un1_mcio_1_i_0, underrun_1_0, underrun2, overrun_4, - overrun_4_0, underrun, un1_ici_0, un1_mcio_4_0, overrun, - un2_eholdn_0_0, un2_eholdn_0, \istate_ns_0_0[0]\, - istate_0_sqmuxa_0_a3_m6_5, istate_0_sqmuxa_0_a3_m6_3, - un5_eholdn, istate_0_sqmuxa_0_a3_m6_1, - istate_0_sqmuxa_0_a3_m2_e, burst_5_m_0, twrite_3_iv_4, - twrite_3_iv_2, cacheon_1, twrite_3_iv_0, hit_RNIR2PJ, - cache, un1_mcio_1_0, hit_1_18, hit_1_10, hit_1_9, - hit_1_16, hit_1_17, hit_1_8, hit_1_7, hit_1_13, hit_1_2, - hit_1_1, hit_1_12, un1_ici_9_i_0, un1_ici_8_i_0, - un1_ici_5_i_0, un1_ici_4_i_0, hit_1_4, hit_1_0, - un1_ici_18_i_0, un1_ici_15_i_0, un1_ici_13_i_0, - un1_ici_7_i_0, un1_ici_3_i_0, un1_ici_0_i_0, - un1_icramo_NE_5, un1_icramo_5_i, un1_icramo_4_i, - un1_icramo_NE_3, un1_icramo_NE_4, un1_icramo_1_0_i, - un1_icramo_0_i, un1_icramo_NE_1, un1_icramo_7_i, - un1_icramo_3_i, taddr_1_sqmuxa_0, N_1346_1, - taddr_9_sn_m2_1, taddr_0_sqmuxa, \cdwrite_4_m_0[0]\, - twrite_3, underrun_1, N_1372, underrun_2, N_1312, N_1331, - overrun_0, un2_m_en, flush2_0_sqmuxa, valid_1, hit_1, - un1_icramo_1, \un1_p0_2_0[148]\, \faddr[6]\, I_31_0, - ctwrite_0_sqmuxa_1, N_1163_i, \istate_li[0]\, - \un4_validv[7]\, istate_5, burst_2_sqmuxa, N_1310, - \istate_0_sqmuxa\, trans_op_RNO_0, trans_op_0_a2_0, - trans_op_RNO, trans_op_RNO_2, hit, un1_dco_1, CO1, - \vaddress[3]\, \vaddress[2]\, N_971, \vaddress[15]\, - \un1_ici\, N_1121, N_1143, taddr_0_sqmuxa_1, - \cdwrite_0_sqmuxa_i_0_0\, N_969, \vaddress[13]\, idle, - istate_1259_d, N_973, \vaddress[17]\, N_974, - \vaddress[18]\, N_1122, N_1144, N_1042, N_1050, N_1063, - N_1064, N_1065, N_1066, \waddress_1[5]\, \waddress_1[13]\, - \waddress_1[26]\, \waddress_1[27]\, \waddress_1[28]\, - \waddress_1[29]\, N_1043, N_1046, \waddress_1[4]\, N_1041, - \waddress_1[6]\, \waddress_1[9]\, \vaddress_1[2]\, - \vaddress_4_i[2]\, \vaddress[26]\, \vaddress[27]\, - \vaddress[29]\, N_1052, N_1068, \waddress_1[15]\, - \waddress_1[31]\, N_1049, \waddress_1[12]\, N_1051, - N_1055, N_1056, \waddress_1[14]\, \waddress_1[18]\, - \waddress_1[19]\, N_1124, N_1146, \vaddress[5]\, - \taddr_9[5]\, \vaddress_1[3]\, \vaddress_4[3]\, - \un95_res[6]\, \address[3]\, \address[4]\, \un95_res[1]\, - \address[2]\, \un95_res[0]\, \un95_res[5]\, \un95_res[2]\, - \un95_res[3]\, \un95_res[4]\, \un95_res[7]\, - \waddress_4[2]\, \waddress_1[2]\, N_1039, error_1_sqmuxa, - \waddress_1[17]\, N_1054, \waddress_1[16]\, N_1053, - \waddress_1[8]\, N_1045, \waddress_4[4]\, - \waddress_1[20]\, N_1057, \waddress_1[24]\, N_1061, - \waddress_1[21]\, N_1058, \waddress_1[30]\, N_1067, - \waddress_1[25]\, N_1062, \waddress_1[23]\, N_1060, - \waddress_1[22]\, N_1059, \istate_nss[1]\, - istate_1_sqmuxa, overrun_1, holdn_1_i, holdn_RNO, - holdn_0_sqmuxa_1, \req\, N_1213, underrun_RNO, - vaddress_0_sqmuxa, N_970, \vaddress[14]\, N_978, - \vaddress[22]\, diagen_0_sqmuxa, \vaddress[25]\, - error_0_sqmuxa_1, un5_mds, \istate_RNI21Q02[0]\, - \waddress_1[3]\, N_1040, \waddress_4[3]\, N_1012, - \valid[2]\, N_1015, \valid[5]\, \vmask_6[2]\, N_1022, - N_1028_i, \vmask_6[5]\, N_1025, N_1011, \valid[1]\, - N_1013, \valid[3]\, N_1017, \valid[7]\, \vmask_6[1]\, - N_1021, \vmask_6[3]\, N_1023, \vmask_6[7]\, N_1027, - N_1102, \vmask_6[0]\, N_1103, N_1104, N_1105, N_1107, - N_1109, \valid_1[3]\, N_1123, N_1145, \vaddress[4]\, - cdwrite_0_sqmuxa_i_0, N_968, \vaddress[12]\, N_979, - \vaddress[23]\, N_972, \vaddress[16]\, N_1125, - \taddr_9[6]\, N_1147, N_1010, \valid[0]\, N_1014, - \valid[4]\, N_1020, \vmask_6[4]\, N_1024, N_1106, N_1130, - N_1152, \vaddress[11]\, \taddr_9[11]\, \faddr_1[0]\, - \faddr_1[1]\, I_5_0, \faddr_1[2]\, I_9_0, \faddr_1[3]\, - \flush2\, I_13_4, \faddr_1[4]\, I_20_0, \faddr_1[5]\, - I_24_0, \faddr_1[6]\, N_1047, \waddress_1[10]\, N_1128, - N_1150, \vaddress[9]\, \taddr_9[9]\, \faddr[4]\, - \vaddress_1[4]\, \vaddress_4[4]\, \vaddress[30]\, - \vaddress[31]\, N_1048, \waddress_1[11]\, N_1129, N_1151, - \vaddress[10]\, \taddr_9[10]\, \faddr[5]\, N_976, - \vaddress[20]\, N_1044, \waddress_1[7]\, N_1126, - \vaddress[6]\, N_1148, \vaddress[7]\, \taddr_9[7]\, - \faddr[2]\, N_964, N_965, N_963, N_962, \vaddress[24]\, - \flush_0\, N_975, \vaddress[19]\, N_977, \vaddress[21]\, - \vaddress[28]\, flush_RNO, N_1214, cache_RNO, N_1203, - N_1317, N_1333, \taddr_9[8]\, N_1149, N_1127, - \vaddress[8]\, pflushr_1_sqmuxa_1, N_960, N_961, hit_RNO, - N_1215, \valid_1[5]\, \valid_1[4]\, \valid_1[2]\, - \valid_1[0]\, \valid_1[7]\, \valid_1[1]\, N_1108, - \vmask_6[6]\, valid_1_sqmuxa, \istate_nss[0]\, N_1345, - N_1212, overrun_RNO, N_1016, \valid[6]\, N_1026, - \valid_1[6]\, N_1202, \burst_0\, burst_RNO_0, N_1230_i, - \su\, \hold_0\, \trans_op_0\, \address[5]\, \address[6]\, - \address[7]\, \address[8]\, \address[9]\, \address[10]\, - \address[11]\, \address[12]\, \address[13]\, - \address[14]\, \address[15]\, \address[16]\, - \address[17]\, \address[18]\, \address[19]\, - \address[20]\, \address[21]\, \address[22]\, - \address[23]\, \address[24]\, \address[25]\, - \address[26]\, \address[27]\, \address[28]\, - \address[29]\, \address[30]\, \address[31]\, N_4, - \DWACT_FINC_E[1]\, N_9, N_17, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - address(31) <= \address[31]\; - address(30) <= \address[30]\; - address(29) <= \address[29]\; - address(28) <= \address[28]\; - address(27) <= \address[27]\; - address(26) <= \address[26]\; - address(25) <= \address[25]\; - address(24) <= \address[24]\; - address(23) <= \address[23]\; - address(22) <= \address[22]\; - address(21) <= \address[21]\; - address(20) <= \address[20]\; - address(19) <= \address[19]\; - address(18) <= \address[18]\; - address(17) <= \address[17]\; - address(16) <= \address[16]\; - address(15) <= \address[15]\; - address(14) <= \address[14]\; - address(13) <= \address[13]\; - address(12) <= \address[12]\; - address(11) <= \address[11]\; - address(10) <= \address[10]\; - address(9) <= \address[9]\; - address(8) <= \address[8]\; - address(7) <= \address[7]\; - address(6) <= \address[6]\; - address(5) <= \address[5]\; - address(4) <= \address[4]\; - address(3) <= \address[3]\; - address(2) <= \address[2]\; - un1_p0_2_0(148) <= \un1_p0_2_0[148]\; - hold_0 <= \hold_0\; - flush2 <= \flush2\; - su <= \su\; - trans_op_0 <= \trans_op_0\; - un1_ici <= \un1_ici\; - flush_0 <= \flush_0\; - req <= \req\; - istate_0_sqmuxa <= \istate_0_sqmuxa\; - burst_0 <= \burst_0\; - cdwrite_0_sqmuxa_i_0_0 <= \cdwrite_0_sqmuxa_i_0_0\; - - \r.vaddress_RNIJG6QR7[4]\ : MX2C - port map(A => N_1145, B => N_1123, S => N_1163_i, Y => - vaddress_RNIJG6QR7(4)); - - \r.vaddress_RNI1CS1SD[10]\ : MX2C - port map(A => N_1151, B => N_1129, S => N_1163_i, Y => - \taddr_9[10]\); - - \r.waddress_RNO_0[5]\ : MX2C - port map(A => \address[5]\, B => fpc(5), S => - vaddress_0_sqmuxa_0, Y => N_1042); - - \r.valid_RNIITEC[0]\ : AOI1 - port map(A => hit, B => \valid[0]\, C => \un95_res[0]\, Y - => N_1010); - - \ictrl.hit_1_9\ : XA1A - port map(A => fpc(29), B => dataout_2(25), C => - un1_ici_18_i_0, Y => hit_1_9); - - \r.waddress_RNO[12]\ : MX2C - port map(A => N_1049, B => N_2623, S => error_1_sqmuxa_0, Y - => \waddress_1[12]\); - - \r.vaddress_RNITQAN[14]\ : MX2C - port map(A => \vaddress[14]\, B => maddress(14), S => - diagen_0_sqmuxa_0, Y => N_970); - - \r.su_RNIA1LEG1\ : OR3C - port map(A => fault_isid_1_i(0), B => un2_m_en, C => - fault_trans_RNIA0K0D1, Y => un5_m_en); - - \r.underrun_RNO_0\ : MX2 - port map(A => underrun_1, B => underrun, S => istate_1259_d, - Y => N_1213); - - \r.req_RNO\ : OA1 - port map(A => istate_1_sqmuxa, B => req_1_0, C => rst, Y - => N_1230_i); - - \r.istate_RNIRASC8[0]\ : MX2 - port map(A => hrdata_24, B => maddress(29), S => idle_0, Y - => istate_RNIRASC8(0)); - - \r.flush2_RNI5I3N7\ : MX2C - port map(A => pflushr_1_sqmuxa_1, B => N_425_1, S => - ctwrite_0_sqmuxa_1, Y => flush2_RNI5I3N7); - - \r.flush2_0_0_RNIRN5O2\ : NOR2A - port map(A => N_1103, B => \un1_p0_2_0[148]\, Y => - un1_p0_2_i_0); - - \ictrl.0.un1_ici_9_0\ : XNOR2 - port map(A => dataout_2(17), B => fpc(21), Y => - un1_ici_9_i_0); - - \r.vaddress_RNI1BBN[30]\ : MX2 - port map(A => \vaddress[30]\, B => maddress(30), S => - diagen_0_sqmuxa, Y => N_986); - - \r.istate_RNIEOB8D[0]\ : NOR2 - port map(A => grant, B => istate_1259_d, Y => req_0_sqmuxa); - - \ictrl.0.un1_icramo_NE_1\ : XA1A - port map(A => ctx_0_0, B => dataout_1(30), C => - un1_icramo_3_i, Y => un1_icramo_NE_1); - - \r.waddress_RNO_1[2]\ : XNOR2 - port map(A => ready, B => \address[2]\, Y => - \waddress_4[2]\); - - \r.waddress[6]\ : DFN1 - port map(D => \waddress_1[6]\, CLK => lclk_c, Q => - \address[6]\); - - \r.vaddress_RNII112ND[10]\ : MX2C - port map(A => rpc_8, B => \vaddress[10]\, S => - taddr_0_sqmuxa_1, Y => N_1151); - - \r.trans_op_RNO_1\ : NOR3C - port map(A => trans_op_1_0, B => trans_op_RNO_4, C => - trans_op_RNO_5, Y => trans_op_1_2); - - \r.req\ : DFN1 - port map(D => N_1230_i, CLK => lclk_c, Q => \req\); - - \r.istate_RNIP0SCH[0]\ : MX2 - port map(A => hrdata_0_23, B => dataout_1(23), S => - istate_1259_d, Y => data_0(23)); - - \r.istate_RNI3MVI[0]\ : MX2 - port map(A => fpc(7), B => addr(7), S => diagen_0_sqmuxa, Y - => N_1126); - - \r.valid_RNIKTEC[2]\ : AOI1 - port map(A => hit, B => \valid[2]\, C => \un95_res[2]\, Y - => N_1012); - - \r.vaddress_RNIG9T9T8[5]\ : MX2C - port map(A => N_1146, B => N_1124, S => N_1163_i, Y => - \taddr_9[5]\); - - \r.istate_RNI0L69F[0]\ : MX2 - port map(A => hrdata_0_21, B => dataout_1(21), S => - istate_1259_d_0, Y => data_0(21)); - - \r.faddr[5]\ : DFN1E1 - port map(D => \faddr_1[5]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[5]\); - - \ictrl.un2_eholdn_0\ : NOR2A - port map(A => hold, B => inull, Y => un2_eholdn_0); - - \r.istate_RNITUH12[0]\ : MX2 - port map(A => hrdata_0_13, B => dataout_1(13), S => - istate_1259_d, Y => data_0(13)); - - \r.req_RNO_1\ : MX2 - port map(A => \req\, B => req_7, S => req_0_sqmuxa, Y => - N_1201); - - \r.vaddress[14]\ : DFN1E1 - port map(D => fpc(14), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[14]\); - - \r.vaddress[11]\ : DFN1E1 - port map(D => fpc(11), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[11]\); - - \r.istate_RNO_0[1]\ : NOR2B - port map(A => \istate_ns_0_0[1]\, B => underrun_1_sqmuxa, Y - => \istate_ns_0_1[1]\); - - \r.istate_RNIV5VI[0]\ : MX2C - port map(A => fpc(5), B => addr(5), S => diagen_0_sqmuxa_0, - Y => N_1124); - - \r.istate_RNIEC82C[0]\ : MX2 - port map(A => hrdata_0_d0, B => maddress(5), S => idle_0, Y - => istate_RNIEC82C(0)); - - \r.vaddress_RNIJ5GUFB[8]\ : MX2C - port map(A => rpc_6, B => \vaddress[8]\, S => - taddr_0_sqmuxa_1, Y => N_1149); - - \r.istate_RNIK9NF8[0]\ : MX2 - port map(A => hrdata_0_16, B => maddress(16), S => idle, Y - => istate_RNIK9NF8(0)); - - \r.istate_RNIEON21_25[0]\ : MX2 - port map(A => dataout_2(3), B => dataout_1(3), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_3); - - \ictrl.0.un1_icramo_3_0\ : XNOR2 - port map(A => dataout_1(31), B => ctx_3, Y => - un1_icramo_3_i); - - \r.istate_RNIEON21_22[0]\ : MX2 - port map(A => dataout_2(17), B => dataout_1(21), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_21); - - \r.vaddress_RNO_0[2]\ : XOR2 - port map(A => ready, B => \vaddress[2]\, Y => - \vaddress_4_i[2]\); - - \r.faddr_RNO[2]\ : NOR2B - port map(A => \flush2\, B => I_9_0, Y => \faddr_1[2]\); - - \r.faddr_RNO[5]\ : NOR2B - port map(A => \flush2\, B => I_24_0, Y => \faddr_1[5]\); - - \r.waddress_RNO[14]\ : MX2C - port map(A => N_1051, B => N_45, S => error_1_sqmuxa_0, Y - => \waddress_1[14]\); - - \r.flush2_RNI1R3J2\ : OA1B - port map(A => N_1346_1, B => underrun2, C => istate_1259_d, - Y => taddr_0_sqmuxa_1); - - \r.valid[1]\ : DFN1E0 - port map(D => \valid_1[1]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[1]\); - - \ictrl.0.un1_ici_7_0\ : XNOR2 - port map(A => dataout_2(15), B => fpc(19), Y => - un1_ici_7_i_0); - - \r.valid_RNO[3]\ : MX2 - port map(A => \vmask_6[3]\, B => dataout_2(3), S => - twrite_3, Y => \valid_1[3]\); - - \r.vaddress_RNI1RAN[16]\ : MX2C - port map(A => \vaddress[16]\, B => maddress(16), S => - diagen_0_sqmuxa, Y => N_972); - - \r.istate_RNI9L8J1[0]\ : MX2 - port map(A => hrdata_0_26, B => dataout_1(26), S => - istate_1259_d_0, Y => data_0(26)); - - \r.hit_RNIR2PJ\ : OR2 - port map(A => hit, B => un1_dco_1, Y => hit_RNIR2PJ); - - \ictrl.un1_ici_0\ : OA1A - port map(A => maddress(21), B => N_523, C => flush_i_0, Y - => un1_ici_0); - - \un1_r.faddr_I_23\ : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \faddr[3]\, C => - \faddr[4]\, Y => N_9); - - \r.vaddress_RNI73BN[26]\ : MX2C - port map(A => \vaddress[26]\, B => maddress(26), S => - diagen_0_sqmuxa_0, Y => N_982); - - \r.vaddress_RNI2GAKMI[17]\ : NOR2 - port map(A => \un1_ici\, B => N_973, Y => - vaddress_RNI2GAKMI(17)); - - \ictrl.0.un1_ici_10_0\ : XNOR2 - port map(A => fpc(22), B => dataout_2(18), Y => - un1_ici_10_i_0); - - \ictrl.un1_ici\ : AO1C - port map(A => N_121, B => iflush_1_0_a2_0, C => un1_ici_0, - Y => \un1_ici\); - - \r.istate_RNIEON21_11[0]\ : MX2 - port map(A => dataout_2(8), B => dataout_1(12), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_12); - - \r.waddress[20]\ : DFN1 - port map(D => \waddress_1[20]\, CLK => lclk_c, Q => - \address[20]\); - - \r.vaddress_RNIQBKPKB[8]\ : MX2C - port map(A => N_1149, B => N_1127, S => N_1163_i, Y => - \taddr_9[8]\); - - \r.istate_RNIEON21_8[0]\ : MX2 - port map(A => dataout_2(10), B => dataout_1(14), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_14); - - \ictrl.valid_1_6\ : MX2C - port map(A => N_963, B => N_964, S => fpc(3), Y => N_965); - - \r.istate_RNIDP0S8[0]\ : MX2 - port map(A => hrdata_0_11, B => dataout_1(11), S => - istate_1259_d_0, Y => data_0(11)); - - \un1_r.faddr_I_24\ : XOR2 - port map(A => N_9, B => \faddr[5]\, Y => I_24_0); - - \r.waddress[24]\ : DFN1 - port map(D => \waddress_1[24]\, CLK => lclk_c, Q => - \address[24]\); - - \ictrl.valid_1_3\ : MX2C - port map(A => N_960, B => N_961, S => fpc(3), Y => N_962); - - \ictrl.0.un1_ici_10_0_RNISL5R7\ : NOR3C - port map(A => hit_1_18, B => hit_1_17, C => un1_icramo_1, Y - => hit_1); - - \r.vaddress_RNIKA3VM7[4]\ : MX2C - port map(A => rpc_2, B => \vaddress[4]\, S => - taddr_0_sqmuxa_1, Y => N_1145); - - \r.istate_RNIJGCD_1[0]\ : OR2A - port map(A => \istate[1]\, B => \istate[0]\, Y => - istate_1259_d_0); - - \r.valid[2]\ : DFN1E0 - port map(D => \valid_1[2]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[2]\); - - \r.vaddress_RNISNKBT9[6]\ : MX2C - port map(A => N_1147, B => N_1125, S => N_1163_i, Y => - \taddr_9[6]\); - - \r.req_RNIECCP1\ : OR2 - port map(A => ready, B => \req\, Y => underrun2); - - \r.cache_RNO\ : OA1A - port map(A => holdn_0_sqmuxa_1, B => N_1203, C => - \istate_0_sqmuxa\, Y => cache_RNO); - - \r.valid_RNO[4]\ : MX2A - port map(A => \vmask_6[4]\, B => dataout_2(4), S => - twrite_3, Y => \valid_1[4]\); - - \r.burst_RNO_1\ : OR3C - port map(A => burst_2_sqmuxa, B => \istate_li[0]\, C => - N_1310, Y => istate_5); - - \r.waddress_RNO[19]\ : MX2C - port map(A => N_1056, B => un1_m0_17, S => error_1_sqmuxa_0, - Y => \waddress_1[19]\); - - \r.su\ : DFN1E1 - port map(D => su_0, CLK => lclk_c, E => idle, Q => \su\); - - \r.waddress_RNO_0[17]\ : MX2C - port map(A => \address[17]\, B => fpc(17), S => - vaddress_0_sqmuxa_0, Y => N_1054); - - \r.vaddress[7]\ : DFN1E1 - port map(D => fpc(7), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[7]\); - - \ictrl.hit_1_4\ : XA1A - port map(A => fpc(18), B => dataout_2(14), C => - un1_ici_7_i_0, Y => hit_1_4); - - \r.waddress_RNI3LUL[4]\ : AO1D - port map(A => dataout_2(0), B => \un95_res[0]\, C => - cacheon_1, Y => N_1020); - - \r.vaddress[16]\ : DFN1E1 - port map(D => fpc(16), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[16]\); - - \r.istate_RNIEON21_9[0]\ : MX2 - port map(A => dataout_0(35), B => dataout_1(9), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_9); - - \r.istate_RNI34LKA[0]\ : MX2 - port map(A => hrdata_0_4, B => dataout_1(4), S => - istate_1259_d, Y => data_0(4)); - - \r.istate_RNI1L08M[0]\ : MX2 - port map(A => hrdata_26, B => dataout_2(31), S => - istate_1259_d_0, Y => data_0(31)); - - \r.holdn_RNO_0\ : MX2 - port map(A => overrun_1, B => N_1312, S => - underrun_1_sqmuxa, Y => holdn_1_i); - - \r.vaddress[12]\ : DFN1E1 - port map(D => fpc(12), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[12]\); - - \r.overrun_RNILCS93\ : AOI1B - port map(A => taddr_1_sqmuxa_0, B => overrun, C => - taddr_0_sqmuxa, Y => taddr_9_sn_m2_1); - - \r.waddress_RNO_1[3]\ : AX1 - port map(A => ready, B => \address[2]\, C => \address[3]\, - Y => \waddress_4[3]\); - - \r.valid_RNIN7DS1[3]\ : MX2C - port map(A => N_1013, B => N_1023, S => N_1028_i, Y => - \vmask_6[3]\); - - \r.vaddress_RNIDOSVU5[2]\ : MX2C - port map(A => rpc_0, B => \vaddress[2]\, S => - taddr_0_sqmuxa_1, Y => N_1143); - - \r.faddr_RNID788NI[6]\ : NOR3B - port map(A => rst, B => vitdatain_0_1_0(22), C => - flush2_0_sqmuxa, Y => \faddr_RNID788NI[6]\); - - \ictrl.0.un1_ici_13_0\ : XNOR2 - port map(A => dataout_2(21), B => fpc(25), Y => - un1_ici_13_i_0); - - \r.waddress_RNO[10]\ : MX2C - port map(A => N_1047, B => un1_m0_8, S => error_1_sqmuxa, Y - => \waddress_1[10]\); - - \r.faddr_RNIDN2CUE[6]\ : MX2A - port map(A => \taddr_9[11]\, B => \faddr[6]\, S => - \un1_p0_2_0[148]\, Y => faddr_RNIDN2CUE(6)); - - \r.trans_op_RNO_4\ : OR3A - port map(A => un81_m_tlb_type, B => un2_m_tlb_type, C => - flush, Y => trans_op_RNO_4); - - \r.waddress_RNIQKIL1[4]\ : OR2A - port map(A => un1_mcio_1_0, B => ready, Y => un1_mcio_1_i_0); - - \r.overrun_RNIMIJOU\ : NOR2A - port map(A => un2_eholdn, B => overrun, Y => overrun_0); - - \r.waddress[9]\ : DFN1 - port map(D => \waddress_1[9]\, CLK => lclk_c, Q => - \address[9]\); - - \r.flush2_RNI4S946\ : OA1B - port map(A => diagen_0_sqmuxa, B => twrite_3, C => \flush2\, - Y => pflushr_1_sqmuxa_1); - - \r.waddress_RNI3LUL_0[4]\ : OA1B - port map(A => \un95_res[1]\, B => dataout_2(1), C => - cacheon_1, Y => N_1021); - - \ictrl.v.burst_1_iv_RNO_4\ : OR3C - port map(A => fpc(3), B => fpc(2), C => fpc(4), Y => - \un4_validv[7]\); - - \un1_r.faddr_I_12\ : AND3 - port map(A => \faddr[0]\, B => \faddr[1]\, C => \faddr[2]\, - Y => N_17); - - \ictrl.valid_1_5\ : MX2 - port map(A => dataout_2(3), B => dataout_2(7), S => fpc(4), - Y => N_964); - - \r.flush_RNI41ED\ : XA1C - port map(A => fpc(13), B => dataout_2(9), C => \flush_0\, Y - => hit_1_0); - - \r.waddress_RNO_0[31]\ : MX2C - port map(A => \address[31]\, B => fpc(31), S => - vaddress_0_sqmuxa_0, Y => N_1068); - - \r.underrun_RNITDT4J1\ : MX2C - port map(A => error_0_sqmuxa_1, B => un5_mds, S => - \istate_RNI21Q02[0]\, Y => mds); - - \r.istate_RNI57KLB[0]\ : MX2 - port map(A => hrdata_0_3, B => maddress_0_2, S => idle, Y - => istate_RNI57KLB(0)); - - \r.vaddress[24]\ : DFN1E1 - port map(D => fpc(24), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[24]\); - - \r.waddress[11]\ : DFN1 - port map(D => \waddress_1[11]\, CLK => lclk_c, Q => - \address[11]\); - - \r.vaddress[21]\ : DFN1E1 - port map(D => fpc(21), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[21]\); - - \r.trans_op_RNO\ : NOR3C - port map(A => trans_op_RNO_0, B => trans_op_1_2, C => - trans_op_RNO_2, Y => trans_op_RNO); - - \r.flush_RNO_0\ : MX2 - port map(A => \flush2\, B => \flush_0\, S => N_1317, Y => - N_1214); - - \r.valid_RNISF2H2[5]\ : MX2A - port map(A => \vmask_6[5]\, B => maddress(5), S => - diagen_0_sqmuxa_0, Y => N_1107); - - \r.underrun_RNI7JVF01\ : AO1A - port map(A => un1_mcio_4_0, B => un2_eholdn, C => underrun, - Y => underrun_2); - - \r.waddress_RNIB452[4]\ : NOR2B - port map(A => \address[3]\, B => \address[4]\, Y => - un1_mcio_1_0); - - \r.istate_RNIDOS1V_1[0]\ : NOR2A - port map(A => idle_0, B => un2_eholdn, Y => - vaddress_0_sqmuxa_0); - - \r.trans_op_RNO_0\ : OR3C - port map(A => vaddr_1_sqmuxa_0_a2_2, B => trans_op_0_a2_0, - C => stpend_RNI6P41NG3, Y => trans_op_RNO_0); - - \r.istate_RNO[1]\ : OA1A - port map(A => \istate_ns_0_1[1]\, B => istate_1_sqmuxa, C - => rst, Y => \istate_nss[1]\); - - \r.underrun_RNI7JVF01_0\ : NOR2 - port map(A => overrun_4_0, B => overrun_0, Y => overrun_4); - - \r.holdn_RNIFCHA\ : OR2B - port map(A => \hold_0\, B => hold, Y => holdn_RNIFCHA); - - \r.waddress_RNO_0[6]\ : MX2C - port map(A => \address[6]\, B => fpc(6), S => - vaddress_0_sqmuxa_0, Y => N_1043); - - \ictrl.0.un1_ici_0_0\ : XNOR2 - port map(A => dataout_2(8), B => fpc(12), Y => - un1_ici_0_i_0); - - \r.valid_RNIOTEC[6]\ : AO1 - port map(A => hit, B => \valid[6]\, C => \un95_res[6]\, Y - => N_1016); - - \r.waddress_RNO_0[24]\ : MX2C - port map(A => \address[24]\, B => fpc(24), S => - vaddress_0_sqmuxa_1, Y => N_1061); - - \r.waddress_RNO[21]\ : MX2C - port map(A => N_1058, B => N_427, S => error_1_sqmuxa, Y - => \waddress_1[21]\); - - \r.valid_RNO[2]\ : MX2 - port map(A => \vmask_6[2]\, B => dataout_2(2), S => - twrite_3, Y => \valid_1[2]\); - - \r.istate_RNIPSU8G[0]\ : MX2 - port map(A => hrdata_0_1, B => maddress_0_0, S => idle_0, Y - => istate_RNIPSU8G(0)); - - \r.waddress_RNI3LUL_3[4]\ : OA1B - port map(A => \un95_res[5]\, B => dataout_2(5), C => - cacheon_1, Y => N_1025); - - \r.istate_RNI21Q02[0]\ : NOR2 - port map(A => ready, B => istate_1259_d, Y => - \istate_RNI21Q02[0]\); - - \ictrl.0.un1_icramo_4_0\ : XNOR2 - port map(A => dataout_0(32), B => ctx_4, Y => - un1_icramo_4_i); - - \r.vaddress[8]\ : DFN1E1 - port map(D => fpc(8), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[8]\); - - \r.burst\ : DFN1 - port map(D => burst_RNO_0, CLK => lclk_c, Q => \burst_0\); - - \un1_r.faddr_I_13\ : XOR2 - port map(A => N_17, B => \faddr[3]\, Y => I_13_4); - - \r.overrun_RNI28484\ : OR3B - port map(A => \istate_li[0]\, B => taddr_9_sn_m2_1, C => - diagen_0_sqmuxa_0, Y => N_1163_i); - - \un1_r.faddr_I_9\ : XOR2 - port map(A => N_20, B => \faddr[2]\, Y => I_9_0); - - un11_xaddr_inc_1_CO1 : OR2B - port map(A => \vaddress[3]\, B => \vaddress[2]\, Y => CO1); - - \r.waddress[12]\ : DFN1 - port map(D => \waddress_1[12]\, CLK => lclk_c, Q => - \address[12]\); - - \ictrl.0.un1_icramo_NE_5\ : NOR3C - port map(A => un1_icramo_5_i, B => un1_icramo_4_i, C => - un1_icramo_NE_3, Y => un1_icramo_NE_5); - - \ictrl.0.un1_ici_15_0\ : XNOR2 - port map(A => dataout_2(23), B => fpc(27), Y => - un1_ici_15_i_0); - - \r.waddress_RNO_0[2]\ : MX2C - port map(A => \waddress_4[2]\, B => fpc(2), S => - vaddress_0_sqmuxa_0, Y => N_1039); - - \r.waddress_RNO[17]\ : MX2C - port map(A => N_1054, B => N_425, S => error_1_sqmuxa, Y - => \waddress_1[17]\); - - \ictrl.0.un1_ici_10_0_RNIA8AL\ : NOR3C - port map(A => un1_ici_9_i_0, B => un1_ici_8_i_0, C => - hit_1_6, Y => hit_1_13); - - \r.valid[5]\ : DFN1E0 - port map(D => \valid_1[5]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[5]\); - - \r.vaddress_RNI3RAN[17]\ : MX2C - port map(A => \vaddress[17]\, B => maddress(17), S => - diagen_0_sqmuxa_0, Y => N_973); - - \r.valid_RNIP7DS1[5]\ : MX2C - port map(A => N_1015, B => N_1025, S => N_1028_i, Y => - \vmask_6[5]\); - - \r.valid_RNIK7DS1[0]\ : MX2C - port map(A => N_1010, B => N_1020, S => N_1028_i, Y => - \vmask_6[0]\); - - GND_i : GND - port map(Y => \GND\); - - \r.waddress_RNO_0[20]\ : MX2C - port map(A => \address[20]\, B => fpc(20), S => - vaddress_0_sqmuxa_1, Y => N_1057); - - \r.istate_RNIJGCD[0]\ : OR2B - port map(A => \istate[1]\, B => \istate[0]\, Y => - \istate_li[0]\); - - \r.flush_RNIPE0E5\ : OR2A - port map(A => twrite_3_iv_4, B => ready, Y => twrite_3); - - \r.flush2_0_0\ : DFN1 - port map(D => \faddr_RNID788NI[6]\, CLK => lclk_c, Q => - \un1_p0_2_0[148]\); - - \r.waddress[15]\ : DFN1 - port map(D => \waddress_1[15]\, CLK => lclk_c, Q => - \address[15]\); - - \r.vaddress_RNIQFAKMI[13]\ : NOR2 - port map(A => \un1_ici\, B => N_969, Y => - vaddress_RNIQFAKMI(13)); - - \r.istate_RNIJSOBE[0]\ : MX2 - port map(A => hrdata_23, B => maddress(28), S => idle_0, Y - => istate_RNIJSOBE(0)); - - \r.waddress_RNO_0[23]\ : MX2C - port map(A => \address[23]\, B => fpc(23), S => - vaddress_0_sqmuxa_1, Y => N_1060); - - \r.valid[7]\ : DFN1E0 - port map(D => \valid_1[7]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[7]\); - - \r.flush_RNICAO491\ : OR2A - port map(A => vaddress_0_sqmuxa_1, B => un5_eholdn, Y => - holdn_0_sqmuxa_1); - - \r.vaddress_RNIQNAKMI[20]\ : NOR2 - port map(A => \un1_ici\, B => N_976, Y => - vaddress_RNIQNAKMI(20)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.waddress_RNIFG73_4[4]\ : NOR3A - port map(A => \address[4]\, B => \address[2]\, C => - \address[3]\, Y => \un95_res[4]\); - - \ictrl.hit_1_7\ : XA1A - port map(A => fpc(24), B => dataout_2(20), C => - un1_ici_13_i_0, Y => hit_1_7); - - \r.vaddress_RNO_0[4]\ : AX1D - port map(A => CO1, B => ready, C => \vaddress[4]\, Y => - \vaddress_4[4]\); - - \r.istate_RNIN6957[0]\ : MX2 - port map(A => hrdata_0_12, B => maddress(12), S => idle_0, - Y => istate_RNIN6957(0)); - - \r.waddress_RNO[22]\ : MX2C - port map(A => N_1059, B => N_429, S => error_1_sqmuxa, Y - => \waddress_1[22]\); - - \ictrl.hit_1_16\ : NOR3C - port map(A => hit_1_2, B => hit_1_1, C => hit_1_12, Y => - hit_1_16); - - \ictrl.cdwrite_4_m_0[0]\ : NOR2A - port map(A => asi(0), B => N_425_0, Y => \cdwrite_4_m_0[0]\); - - \r.valid_RNIQ7DS1[6]\ : MX2C - port map(A => N_1016, B => N_1026, S => N_1028_i, Y => - \vmask_6[6]\); - - \r.istate_RNIEON21_24[0]\ : MX2 - port map(A => dataout_2(7), B => dataout_1(7), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_7); - - \r.vaddress[26]\ : DFN1E1 - port map(D => fpc(26), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[26]\); - - \r.waddress[16]\ : DFN1 - port map(D => \waddress_1[16]\, CLK => lclk_c, Q => - \address[16]\); - - \r.istate_RNI830H8[0]\ : MX2 - port map(A => hrdata_0_17, B => dataout_1(17), S => - istate_1259_d, Y => data_0(17)); - - \r.vaddress_RNIUFAKMI[15]\ : NOR2 - port map(A => \un1_ici\, B => N_971, Y => - vaddress_RNIUFAKMI(15)); - - \r.underrun_RNO_1\ : OA1B - port map(A => N_1372, B => underrun_2, C => underrun_1_0, Y - => underrun_1); - - \r.vaddress[22]\ : DFN1E1 - port map(D => fpc(22), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[22]\); - - \r.trans_op_0_a0_0\ : NOR2A - port map(A => un81_m_tlb_type, B => flush, Y => - trans_op_0_a2_0); - - \ictrl.un2_eholdn\ : OR2A - port map(A => un2_eholdn_0_0, B => de_hold_pc_1, Y => - un2_eholdn); - - \r.istate_RNIM2DE7[0]\ : MX2 - port map(A => hrdata_0_22, B => maddress(22), S => idle, Y - => istate_RNIM2DE7(0)); - - \r.istate_RNI6LOO6[0]\ : MX2 - port map(A => hrdata_0_10, B => maddress(10), S => idle_0, - Y => istate_RNI6LOO6(0)); - - \r.hit_RNO_0\ : MX2 - port map(A => hit, B => hit_1, S => idle, Y => N_1215); - - \r.vaddress_RNI5RAN[18]\ : MX2C - port map(A => \vaddress[18]\, B => maddress(18), S => - diagen_0_sqmuxa_0, Y => N_974); - - \r.trans_op_RNO_3\ : AOI1B - port map(A => trans_op_0_a3_0, B => un81_m_tlb_type, C => - rst, Y => trans_op_1_0); - - \r.istate_RNI580K8[0]\ : MX2 - port map(A => hrdata_0_8, B => dataout_1(8), S => - istate_1259_d, Y => data_0(8)); - - \r.trans_op_RNO_5\ : OR2A - port map(A => \istate_0_sqmuxa\, B => \trans_op_0\, Y => - trans_op_RNO_5); - - \r.istate_RNI05B4C[0]\ : MX2 - port map(A => hrdata_0_d0, B => dataout_1(5), S => - istate_1259_d_0, Y => data_0(5)); - - \r.vaddress_RNI93BN[27]\ : MX2C - port map(A => \vaddress[27]\, B => maddress(27), S => - diagen_0_sqmuxa_0, Y => N_983); - - \ictrl.0.un1_icramo_1\ : AO1B - port map(A => un1_icramo_NE_5, B => un1_icramo_NE_4, C => e, - Y => un1_icramo_1); - - \r.vaddress_RNI53BN[25]\ : MX2C - port map(A => \vaddress[25]\, B => maddress(25), S => - diagen_0_sqmuxa_0, Y => N_981); - - \r.vaddress_RNI0OAKMI[23]\ : NOR2 - port map(A => \un1_ici\, B => N_979, Y => - vaddress_RNI0OAKMI(23)); - - \r.istate_RNIEON21_15[0]\ : MX2 - port map(A => dataout_2(26), B => dataout_2(30), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_30); - - \r.istate_RNI9CHH8[0]\ : MX2 - port map(A => hrdata_24, B => dataout_2(29), S => - istate_1259_d_0, Y => data_0(29)); - - \r.holdn\ : DFN1 - port map(D => holdn_RNO, CLK => lclk_c, Q => \hold_0\); - - \r.istate_RNIS4VK8[0]\ : MX2 - port map(A => hrdata_25, B => maddress(30), S => idle_0, Y - => istate_RNIS4VK8(0)); - - \r.istate_RNIEON21_12[0]\ : MX2 - port map(A => dataout_2(4), B => dataout_1(4), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_4); - - \r.faddr[6]\ : DFN1E1 - port map(D => \faddr_1[6]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[6]\); - - \r.istate_RNIF2NN[0]\ : MX2 - port map(A => fpc(11), B => addr(11), S => diagen_0_sqmuxa, - Y => N_1130); - - \r.istate_RNIEON21_23[0]\ : MX2 - port map(A => dataout_2(9), B => dataout_1(13), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_13); - - \r.istate_RNIVR9M_0[0]\ : OR2A - port map(A => diagen_0_sqmuxa_0, B => asi(0), Y => - \cdwrite_0_sqmuxa_i_0_0\); - - \r.istate_RNIEON21_28[0]\ : MX2 - port map(A => dataout_2(0), B => dataout_1(0), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_0); - - \r.waddress[21]\ : DFN1 - port map(D => \waddress_1[21]\, CLK => lclk_c, Q => - \address[21]\); - - \r.istate_RNIR2JU8[0]\ : MX2 - port map(A => hrdata_0_27, B => maddress(27), S => idle_0, - Y => istate_RNIR2JU8(0)); - - \r.waddress_RNO[9]\ : MX2C - port map(A => N_1046, B => un1_m0_7, S => error_1_sqmuxa_0, - Y => \waddress_1[9]\); - - \r.waddress_RNO_0[15]\ : MX2C - port map(A => \address[15]\, B => fpc(15), S => - vaddress_0_sqmuxa_0, Y => N_1052); - - \r.waddress_RNIFG73_2[4]\ : NOR3B - port map(A => \address[2]\, B => \address[4]\, C => - \address[3]\, Y => \un95_res[5]\); - - \r.istate_RNIFCU97[0]\ : MX2 - port map(A => hrdata_0_12, B => dataout_1(12), S => - istate_1259_d_0, Y => data_0(12)); - - \r.waddress_RNO[24]\ : MX2C - port map(A => N_1061, B => un1_m0_22, S => error_1_sqmuxa, - Y => \waddress_1[24]\); - - \r.istate_RNIEON21_0[0]\ : MX2 - port map(A => dataout_2(21), B => dataout_1(25), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_25); - - \r.flush2_0_0_RNI6KDT\ : NOR3A - port map(A => diagen_0_sqmuxa_0, B => asi(0), C => - \un1_p0_2_0[148]\, Y => ctwrite_0_sqmuxa_1); - - \r.istate_RNILTAC8[0]\ : MX2 - port map(A => hrdata_0_17, B => maddress(17), S => idle, Y - => istate_RNILTAC8(0)); - - \r.flush_RNIVKVP\ : OR2A - port map(A => un1_dco_1, B => cacheon_1, Y => N_1028_i); - - \un1_r.faddr_I_27\ : AND2 - port map(A => \faddr[3]\, B => \faddr[4]\, Y => - \DWACT_FINC_E[1]\); - - \r.valid_RNILTEC[3]\ : AOI1 - port map(A => hit, B => \valid[3]\, C => \un95_res[3]\, Y - => N_1013); - - \r.req_RNO_0\ : OR2 - port map(A => error_1_sqmuxa_0, B => N_1201, Y => req_1_0); - - \r.cache\ : DFN1 - port map(D => cache_RNO, CLK => lclk_c, Q => cache); - - \r.waddress_RNO_1[4]\ : MX2A - port map(A => N_6093_i, B => \address[4]\, S => ready, Y - => \waddress_4[4]\); - - \r.istate_RNIEON21_6[0]\ : MX2 - port map(A => dataout_2(12), B => dataout_1(16), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_16); - - \r.faddr[2]\ : DFN1E1 - port map(D => \faddr_1[2]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[2]\); - - \ictrl.v.burst_1_iv_RNO_1\ : OR3C - port map(A => un1_mcio_1_i_0, B => burst_5_m_0, C => grant, - Y => burst_5_m); - - \r.waddress[22]\ : DFN1 - port map(D => \waddress_1[22]\, CLK => lclk_c, Q => - \address[22]\); - - \r.underrun_RNIH0CN1\ : OR2A - port map(A => ready, B => underrun, Y => overrun_4_0); - - \ictrl.0.un1_ici_18_0\ : XNOR2 - port map(A => dataout_2(26), B => fpc(30), Y => - un1_ici_18_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.waddress[19]\ : DFN1 - port map(D => \waddress_1[19]\, CLK => lclk_c, Q => - \address[19]\); - - \r.valid_RNIIR1H2[0]\ : MX2C - port map(A => \vmask_6[0]\, B => maddress(0), S => - diagen_0_sqmuxa_0, Y => N_1102); - - \r.istate_RNIMVFNJ[0]\ : MX2 - port map(A => N_262_0, B => dataout_1(20), S => - istate_1259_d, Y => data_0(20)); - - \r.waddress[18]\ : DFN1 - port map(D => \waddress_1[18]\, CLK => lclk_c, Q => - \address[18]\); - - \r.istate_RNI7BUID[0]\ : MX2 - port map(A => hrdata_1, B => maddress(6), S => idle_0, Y - => istate_RNI7BUID(0)); - - \r.vaddress[30]\ : DFN1E1 - port map(D => fpc(30), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[30]\); - - \r.su_RNI7H7D\ : OR2A - port map(A => nf, B => \su\, Y => un2_m_en); - - \ictrl.0.un1_ici_5_0\ : XNOR2 - port map(A => dataout_2(13), B => fpc(17), Y => - un1_ici_5_i_0); - - \r.waddress_RNO_0[28]\ : MX2C - port map(A => \address[28]\, B => fpc(28), S => - vaddress_0_sqmuxa_0, Y => N_1065); - - \r.waddress[25]\ : DFN1 - port map(D => \waddress_1[25]\, CLK => lclk_c, Q => - \address[25]\); - - \r.valid_RNO[1]\ : MX2A - port map(A => \vmask_6[1]\, B => dataout_2(1), S => - twrite_3, Y => \valid_1[1]\); - - \ictrl.hit_1_2\ : XA1A - port map(A => fpc(14), B => dataout_2(10), C => - un1_ici_3_i_0, Y => hit_1_2); - - \r.vaddress[18]\ : DFN1E1 - port map(D => fpc(18), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[18]\); - - \r.overrun_RNIBRGN1\ : OR2 - port map(A => overrun, B => ready, Y => un1_mcio_4_0); - - \r.flush2_0_0_RNIVV5O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1105, Y => - flush2_0_0_RNIVV5O2); - - \r.waddress_RNO[29]\ : MX2C - port map(A => N_1066, B => N_363, S => error_1_sqmuxa_0, Y - => \waddress_1[29]\); - - \r.waddress_RNIFG73_6[4]\ : NOR3 - port map(A => \address[2]\, B => \address[3]\, C => - \address[4]\, Y => \un95_res[0]\); - - \r.overrun_RNO\ : OA1A - port map(A => holdn_0_sqmuxa_1, B => N_1212, C => rst, Y - => overrun_RNO); - - \r.istate_RNO[0]\ : AOI1B - port map(A => \istate_ns_0_0[0]\, B => N_1345, C => rst, Y - => \istate_nss[0]\); - - \r.vaddress_RNID3BN[29]\ : MX2 - port map(A => \vaddress[29]\, B => maddress(29), S => - diagen_0_sqmuxa_0, Y => N_985); - - \r.istate_RNISQRTI[0]\ : MX2 - port map(A => N_78_0, B => dataout_1(25), S => - istate_1259_d_0, Y => data_0(25)); - - \r.istate_RNIKJBN8[0]\ : MX2 - port map(A => hrdata_0_11, B => maddress(11), S => idle_0, - Y => istate_RNIKJBN8(0)); - - \r.waddress_RNO[7]\ : MX2C - port map(A => N_1044, B => un1_m0_5, S => error_1_sqmuxa, Y - => \waddress_1[7]\); - - \r.istate_RNIEON21_26[0]\ : MX2 - port map(A => dataout_2(1), B => dataout_1(1), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_1); - - \ictrl.v.burst_1_iv_RNO_2\ : OR3C - port map(A => \un4_validv[7]\, B => burst, C => idle_0, Y - => burst_2_m); - - \r.waddress[26]\ : DFN1 - port map(D => \waddress_1[26]\, CLK => lclk_c, Q => - \address[26]\); - - \r.istate_RNILPRHG[0]\ : MX2 - port map(A => hrdata_0_0, B => dataout_1(0), S => - istate_1259_d_0, Y => data_0(0)); - - \r.istate_RNIEON21_2[0]\ : MX2 - port map(A => dataout_2(16), B => dataout_1(20), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_20); - - \r.waddress[3]\ : DFN1 - port map(D => \waddress_1[3]\, CLK => lclk_c, Q => - \address[3]\); - - \ictrl.0.un1_icramo_5_0\ : XNOR2 - port map(A => dataout_0(33), B => ctx_5, Y => - un1_icramo_5_i); - - \r.istate_RNITH1SG1[0]\ : OR2 - port map(A => un5_m_en, B => N_1320, Y => error_0_sqmuxa_1); - - \r.istate_RNIPMA0F[0]\ : NOR3B - port map(A => istate_0_sqmuxa_0_a3_m6_3, B => hold_pc_7, C - => un5_eholdn, Y => istate_0_sqmuxa_0_a3_m6_5); - - \r.waddress_RNO_0[4]\ : MX2C - port map(A => \waddress_4[4]\, B => fpc(4), S => - vaddress_0_sqmuxa_0, Y => N_1041); - - \r.istate_RNIRLUI[0]\ : MX2C - port map(A => fpc(3), B => addr(3), S => diagen_0_sqmuxa_0, - Y => N_1122); - - \r.istate_RNIOJJE1[0]\ : MX2 - port map(A => hrdata_0_26, B => maddress(26), S => idle_0, - Y => istate_RNIOJJE1(0)); - - \r.waddress_RNO[20]\ : MX2C - port map(A => N_1057, B => N_2625, S => error_1_sqmuxa, Y - => \waddress_1[20]\); - - \r.waddress_RNO[16]\ : MX2C - port map(A => N_1053, B => N_423, S => error_1_sqmuxa, Y - => \waddress_1[16]\); - - \v.istate_0_sqmuxa_0_a3_m6_1\ : NOR3C - port map(A => e_0, B => un2_eholdn_0, C => rst, Y => - istate_0_sqmuxa_0_a3_m6_1); - - \r.istate_RNIOVC5J[0]\ : MX2 - port map(A => hrdata_0_14, B => maddress(14), S => idle, Y - => istate_RNIOVC5J(0)); - - \r.underrun_RNIUQ18\ : OR2A - port map(A => overrun, B => underrun, Y => un5_mds); - - \r.faddr[3]\ : DFN1E1 - port map(D => \faddr_1[3]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[3]\); - - \r.vaddress[6]\ : DFN1E1 - port map(D => fpc(6), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[6]\); - - \r.istate_RNIJCMP6[0]\ : MX2A - port map(A => twrite_3, B => \cdwrite_4_m_0[0]\, S => - diagen_0_sqmuxa, Y => istate_RNIJCMP6(0)); - - \ictrl.valid_1_1\ : MX2 - port map(A => dataout_2(0), B => dataout_2(4), S => fpc(4), - Y => N_960); - - \r.istate[1]\ : DFN1 - port map(D => \istate_nss[1]\, CLK => lclk_c, Q => - \istate[1]\); - - \r.faddr_RNIUT72LB[3]\ : MX2 - port map(A => \taddr_9[8]\, B => \faddr[3]\, S => \flush2\, - Y => faddr_RNIUT72LB(3)); - - \r.waddress[4]\ : DFN1 - port map(D => \waddress_1[4]\, CLK => lclk_c, Q => - \address[4]\); - - \r.vaddress_RNIIE8DP6[3]\ : MX2C - port map(A => rpc_1, B => \vaddress[3]\, S => - taddr_0_sqmuxa_1, Y => N_1144); - - \r.istate_RNIJGCD_4[0]\ : NOR2 - port map(A => \istate[1]\, B => \istate[0]\, Y => idle_0); - - \r.istate_RNIFK51A[0]\ : MX2 - port map(A => hrdata_0_7, B => dataout_1(7), S => - istate_1259_d_0, Y => data_0(7)); - - \r.waddress_RNIFG73_0[4]\ : NOR3B - port map(A => \address[2]\, B => \address[3]\, C => - \address[4]\, Y => \un95_res[3]\); - - \r.vaddress_RNIUNAKMI[22]\ : NOR2 - port map(A => \un1_ici\, B => N_978, Y => - vaddress_RNIUNAKMI(22)); - - \un1_r.faddr_I_19\ : NOR2B - port map(A => \faddr[3]\, B => \DWACT_FINC_E[0]\, Y => N_12); - - \r.trans_op_RNO_6\ : NOR2A - port map(A => trans_op, B => flush, Y => trans_op_0_a3_0); - - \r.waddress_RNO_0[19]\ : MX2C - port map(A => \address[19]\, B => fpc(19), S => - vaddress_0_sqmuxa_0, Y => N_1056); - - \ictrl.v.burst_1_iv_RNO_0\ : AND2 - port map(A => burst_5_m, B => burst_2_m, Y => burst_1_iv_0); - - \r.waddress[2]\ : DFN1 - port map(D => \waddress_1[2]\, CLK => lclk_c, Q => - \address[2]\); - - \r.istate_RNIEON21[0]\ : MX2 - port map(A => dataout_2(22), B => dataout_1(26), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_26); - - \r.hit_RNO\ : OR2A - port map(A => twrite_3, B => N_1215, Y => hit_RNO); - - \r.waddress_RNO[3]\ : MX2C - port map(A => N_1040, B => un1_m0_1, S => error_1_sqmuxa, Y - => \waddress_1[3]\); - - \ictrl.0.un1_icramo_NE_3\ : XA1A - port map(A => ctx_0_4, B => dataout_0(34), C => - un1_icramo_7_i, Y => un1_icramo_NE_3); - - \r.waddress_RNO_0[11]\ : MX2C - port map(A => \address[11]\, B => fpc(11), S => - vaddress_0_sqmuxa_1, Y => N_1048); - - \r.waddress_RNI3LUL_1[4]\ : OA1B - port map(A => \un95_res[4]\, B => dataout_2(4), C => - cacheon_1, Y => N_1024); - - \r.vaddress_RNO[3]\ : MX2A - port map(A => \vaddress_4[3]\, B => fpc(3), S => - vaddress_0_sqmuxa_0, Y => \vaddress_1[3]\); - - \r.faddr[1]\ : DFN1E1 - port map(D => \faddr_1[1]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[1]\); - - \r.waddress_RNO[2]\ : MX2C - port map(A => N_1039, B => un1_m0_0, S => error_1_sqmuxa, Y - => \waddress_1[2]\); - - \r.req_RNI1TO62\ : OR2A - port map(A => underrun2, B => istate_1259_d, Y => - underrun_1_sqmuxa); - - \r.istate_RNIEON21_1[0]\ : MX2 - port map(A => dataout_2(18), B => dataout_1(22), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_22); - - \r.waddress_RNO[31]\ : MX2C - port map(A => N_1068, B => N_365, S => error_1_sqmuxa_0, Y - => \waddress_1[31]\); - - \r.vaddress_RNO[2]\ : MX2A - port map(A => \vaddress_4_i[2]\, B => fpc(2), S => - vaddress_0_sqmuxa_0, Y => \vaddress_1[2]\); - - \r.istate_RNIEON21_27[0]\ : MX2 - port map(A => dataout_2(2), B => dataout_1(2), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_2); - - \r.istate_RNIDOS1V[0]\ : NOR2A - port map(A => idle, B => un2_eholdn, Y => vaddress_0_sqmuxa); - - \r.flush2_RNI0UAC\ : NOR2A - port map(A => ics(0), B => \flush2\, Y => N_1346_1); - - \r.vaddress_RNIGFP1UE[11]\ : MX2C - port map(A => N_1152, B => N_1130, S => N_1163_i, Y => - \taddr_9[11]\); - - \r.istate_RNIDOS1V_0[0]\ : NOR2A - port map(A => idle_0, B => un2_eholdn, Y => - vaddress_0_sqmuxa_1); - - \r.underrun_RNO\ : NOR2B - port map(A => rst, B => N_1213, Y => underrun_RNO); - - \r.istate_RNICVCR5[0]\ : NOR2A - port map(A => twrite_3, B => idle, Y => valid_1_sqmuxa); - - \r.waddress_RNO[27]\ : MX2C - port map(A => N_1064, B => N_319, S => error_1_sqmuxa_0, Y - => \waddress_1[27]\); - - \r.istate_RNO_1[1]\ : NOR2B - port map(A => N_1350, B => N_1348, Y => \istate_ns_0_0[1]\); - - \r.waddress[29]\ : DFN1 - port map(D => \waddress_1[29]\, CLK => lclk_c, Q => - \address[29]\); - - \r.istate_RNIMRTH8[0]\ : MX2 - port map(A => hrdata_0_8, B => maddress(8), S => idle_0, Y - => istate_RNIMRTH8(0)); - - \r.burst_RNO_0\ : MX2 - port map(A => burst_1, B => \burst_0\, S => istate_5, Y => - N_1202); - - \r.waddress[5]\ : DFN1 - port map(D => \waddress_1[5]\, CLK => lclk_c, Q => - \address[5]\); - - \r.flush2_RNI1R3J2_0\ : NOR3 - port map(A => N_1346_1, B => underrun2, C => - istate_1259_d_0, Y => taddr_1_sqmuxa_0); - - \r.waddress_RNI3LUL_5[4]\ : AO1D - port map(A => dataout_2(3), B => \un95_res[3]\, C => - cacheon_1, Y => N_1023); - - \r.waddress[28]\ : DFN1 - port map(D => \waddress_1[28]\, CLK => lclk_c, Q => - \address[28]\); - - \r.istate_RNIEON21_14[0]\ : MX2 - port map(A => dataout_2(5), B => dataout_1(5), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_5); - - \r.vaddress_RNIV4U1PE[11]\ : MX2 - port map(A => N_26, B => \vaddress[11]\, S => - taddr_0_sqmuxa_1, Y => N_1152); - - \r.istate_RNIIMI4I1_0[0]\ : NOR3A - port map(A => un5_m_en, B => N_66, C => N_1320, Y => - error_1_sqmuxa); - - \r.waddress_RNO_0[16]\ : MX2C - port map(A => \address[16]\, B => fpc(16), S => - vaddress_0_sqmuxa_0, Y => N_1053); - - \r.vaddress[19]\ : DFN1E1 - port map(D => fpc(19), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[19]\); - - \r.istate_RNIQGA6A[0]\ : MX2 - port map(A => hrdata_0_18, B => dataout_1(18), S => - istate_1259_d, Y => data_0(18)); - - \r.faddr_RNI2LF01[6]\ : NOR3B - port map(A => \un1_p0_2_0[148]\, B => \faddr[6]\, C => - I_31_0, Y => flush2_0_sqmuxa); - - \r.waddress_RNO_0[27]\ : MX2C - port map(A => \address[27]\, B => fpc(27), S => - vaddress_0_sqmuxa_0, Y => N_1064); - - \r.vaddress[28]\ : DFN1E1 - port map(D => fpc(28), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[28]\); - - \r.waddress_RNIFG73[4]\ : NOR3C - port map(A => \address[2]\, B => \address[3]\, C => - \address[4]\, Y => \un95_res[7]\); - - \r.istate_RNIH0NBI[0]\ : MX2 - port map(A => hrdata_0_24, B => maddress(24), S => idle, Y - => istate_RNIH0NBI(0)); - - \r.burst_RNO_3\ : OR2B - port map(A => \istate[0]\, B => un5_m_en, Y => N_1310); - - \r.vaddress_RNIT2BN[21]\ : MX2C - port map(A => \vaddress[21]\, B => maddress(21), S => - diagen_0_sqmuxa, Y => N_977); - - \r.waddress_RNO[13]\ : MX2C - port map(A => N_1050, B => N_2624, S => error_1_sqmuxa_0, Y - => \waddress_1[13]\); - - \r.vaddress_RNIOFAKMI[12]\ : NOR2 - port map(A => \un1_ici\, B => N_968, Y => - vaddress_RNIOFAKMI(12)); - - \ictrl.un1_dco_1\ : OR2A - port map(A => ics(0), B => ics(1), Y => un1_dco_1); - - \r.flush_RNIR7JL\ : XA1A - port map(A => fpc(31), B => dataout_2(27), C => hit_1_0, Y - => hit_1_10); - - \r.istate_RNIJ1UUI1[0]\ : OR2B - port map(A => mexc, B => error_0_sqmuxa_1, Y => mexc_0); - - \r.istate_RNI6HPAI[0]\ : MX2 - port map(A => hrdata_0_2, B => maddress(2), S => idle, Y - => istate_RNI6HPAI(0)); - - \r.flush2_0_0_RNI7G6O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1109, Y => - flush2_0_0_RNI7G6O2); - - \r.vaddress_RNIP199QA[7]\ : MX2C - port map(A => N_1148, B => N_1126, S => N_1163_i, Y => - \taddr_9[7]\); - - \r.flush2_0_0_RNI386O2\ : NOR2A - port map(A => N_1107, B => \un1_p0_2_0[148]\, Y => - un1_p0_2_i_4); - - \r.valid_RNI0O2H2[7]\ : MX2B - port map(A => \vmask_6[7]\, B => maddress(7), S => - diagen_0_sqmuxa_0, Y => N_1109); - - \r.istate_RNIJRBBD[0]\ : MX2 - port map(A => N_264_0, B => dataout_1(19), S => - istate_1259_d, Y => data_0(19)); - - \r.istate_RNI6PSS1[0]\ : MX2 - port map(A => hrdata_0_13, B => maddress(13), S => idle, Y - => istate_RNI6PSS1(0)); - - \r.waddress_RNO_0[30]\ : MX2C - port map(A => \address[30]\, B => fpc(30), S => - vaddress_0_sqmuxa_1, Y => N_1067); - - \r.vaddress_RNIB3BN[28]\ : MX2 - port map(A => \vaddress[28]\, B => maddress(28), S => - diagen_0_sqmuxa, Y => N_984); - - \r.vaddress[9]\ : DFN1E1 - port map(D => fpc(9), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[9]\); - - \r.istate_RNIEON21_13[0]\ : MX2 - port map(A => dataout_2(6), B => dataout_1(6), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_6); - - \r.istate_RNIB4839[0]\ : MX2 - port map(A => hrdata_0_27, B => dataout_1(27), S => - istate_1259_d_0, Y => data_0(27)); - - \r.istate_RNIEON21_18[0]\ : MX2 - port map(A => dataout_2(25), B => dataout_2(29), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_29); - - \r.vaddress_RNIRQAN[13]\ : MX2C - port map(A => \vaddress[13]\, B => maddress(13), S => - diagen_0_sqmuxa_0, Y => N_969); - - \r.waddress_RNO[18]\ : MX2C - port map(A => N_1055, B => un1_m0_16, S => error_1_sqmuxa_0, - Y => \waddress_1[18]\); - - \r.waddress[13]\ : DFN1 - port map(D => \waddress_1[13]\, CLK => lclk_c, Q => - \address[13]\); - - \r.underrun\ : DFN1 - port map(D => underrun_RNO, CLK => lclk_c, Q => underrun); - - \r.istate_RNIRLSCI[0]\ : MX2 - port map(A => hrdata_0_2, B => dataout_1(2), S => - istate_1259_d_0, Y => data_0(2)); - - \un1_r.faddr_I_8\ : NOR2B - port map(A => \faddr[1]\, B => \faddr[0]\, Y => N_20); - - \r.waddress_RNO_0[12]\ : MX2C - port map(A => \address[12]\, B => fpc(12), S => - vaddress_0_sqmuxa_0, Y => N_1049); - - \r.valid_RNIR7DS1[7]\ : MX2C - port map(A => N_1017, B => N_1027, S => N_1028_i, Y => - \vmask_6[7]\); - - \r.vaddress_RNO_0[3]\ : AX1A - port map(A => ready, B => \vaddress[2]\, C => \vaddress[3]\, - Y => \vaddress_4[3]\); - - \ictrl.valid_1_2\ : MX2 - port map(A => dataout_2(2), B => dataout_2(6), S => fpc(4), - Y => N_961); - - \r.valid_RNIKV1H2[1]\ : MX2A - port map(A => \vmask_6[1]\, B => maddress(1), S => - diagen_0_sqmuxa_0, Y => N_1103); - - \r.vaddress_RNIV2BN[22]\ : MX2C - port map(A => \vaddress[22]\, B => maddress(22), S => - diagen_0_sqmuxa_0, Y => N_978); - - \r.istate_RNIEON21_5[0]\ : MX2 - port map(A => dataout_2(13), B => dataout_1(17), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_17); - - \r.istate_RNO_1[0]\ : AO1A - port map(A => N_66, B => un5_m_en, C => N_1320, Y => N_1345); - - \r.valid_RNIMTEC[4]\ : AO1 - port map(A => hit, B => \valid[4]\, C => \un95_res[4]\, Y - => N_1014); - - \r.valid_RNIJTEC[1]\ : AO1 - port map(A => hit, B => \valid[1]\, C => \un95_res[1]\, Y - => N_1011); - - \r.vaddress_RNIK35ELA[7]\ : MX2 - port map(A => rpc_5, B => \vaddress[7]\, S => - taddr_0_sqmuxa_1, Y => N_1148); - - \un1_r.faddr_I_20\ : XOR2 - port map(A => N_12, B => \faddr[4]\, Y => I_20_0); - - \r.waddress_RNIFG73_3[4]\ : NOR3A - port map(A => \address[3]\, B => \address[2]\, C => - \address[4]\, Y => \un95_res[2]\); - - \r.istate_RNI8BL1A[0]\ : MX2 - port map(A => hrdata_0_18, B => maddress(18), S => idle, Y - => istate_RNI8BL1A(0)); - - \r.waddress_RNO[4]\ : MX2C - port map(A => N_1041, B => un1_m0_2, S => error_1_sqmuxa_0, - Y => \waddress_1[4]\); - - \r.vaddress_RNIRS4BNE[9]\ : MX2C - port map(A => N_1150, B => N_1128, S => N_1163_i, Y => - \taddr_9[9]\); - - \r.vaddress_RNI7RAN[19]\ : MX2C - port map(A => \vaddress[19]\, B => maddress(19), S => - diagen_0_sqmuxa, Y => N_975); - - \r.vaddress_RNO[4]\ : MX2A - port map(A => \vaddress_4[4]\, B => fpc(4), S => - vaddress_0_sqmuxa_1, Y => \vaddress_1[4]\); - - \r.trans_op\ : DFN1 - port map(D => trans_op_RNO, CLK => lclk_c, Q => - \trans_op_0\); - - \r.cache_RNO_0\ : MX2 - port map(A => cache, B => un1_m0_30, S => error_1_sqmuxa, Y - => N_1203); - - \r.valid_RNO[6]\ : MX2A - port map(A => \vmask_6[6]\, B => dataout_2(6), S => - twrite_3, Y => \valid_1[6]\); - - \ictrl.0.un1_icramo_NE_4\ : NOR3C - port map(A => un1_icramo_1_0_i, B => un1_icramo_0_i, C => - un1_icramo_NE_1, Y => un1_icramo_NE_4); - - \r.istate[0]\ : DFN1 - port map(D => \istate_nss[0]\, CLK => lclk_c, Q => - \istate[0]\); - - \r.overrun\ : DFN1 - port map(D => overrun_RNO, CLK => lclk_c, Q => overrun); - - \r.flush_RNO_1\ : OR2B - port map(A => \istate[1]\, B => N_1333, Y => N_1317); - - \r.faddr[0]\ : DFN1E1 - port map(D => \faddr_1[0]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[0]\); - - \r.holdn_RNO_1\ : OR3 - port map(A => N_1372, B => underrun_2, C => overrun_4, Y - => overrun_1); - - \r.waddress[30]\ : DFN1 - port map(D => \waddress_1[30]\, CLK => lclk_c, Q => - \address[30]\); - - \ictrl.v.burst_1_iv_RNO\ : NAND2 - port map(A => req_7, B => req_0_sqmuxa, Y => req_7_m); - - \r.vaddress_RNI33BN[24]\ : MX2C - port map(A => \vaddress[24]\, B => maddress(24), S => - diagen_0_sqmuxa, Y => N_980); - - \r.istate_RNI5V68H[0]\ : MX2 - port map(A => hrdata_0_23, B => maddress(23), S => idle, Y - => istate_RNI5V68H(0)); - - \r.valid_RNIO7DS1[4]\ : MX2C - port map(A => N_1014, B => N_1024, S => N_1028_i, Y => - \vmask_6[4]\); - - \r.istate_RNIJGCD_3[0]\ : NOR2 - port map(A => \istate[1]\, B => \istate[0]\, Y => idle); - - \r.flush\ : DFN1 - port map(D => flush_RNO, CLK => lclk_c, Q => \flush_0\); - - \v.istate_0_sqmuxa_0_a3_m2_e\ : OR2A - port map(A => un9_icc_check_bp, B => ldlock_3_0, Y => - istate_0_sqmuxa_0_a3_m2_e); - - \r.istate_RNIG7IIA[0]\ : MX2 - port map(A => hrdata_0_4, B => maddress(4), S => idle, Y - => istate_RNIG7IIA(0)); - - \r.flush2_0_0_RNITR5O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1104, Y => - flush2_0_0_RNITR5O2); - - \r.waddress_RNO[15]\ : MX2C - port map(A => N_1052, B => N_357, S => error_1_sqmuxa_0, Y - => \waddress_1[15]\); - - \r.istate_RNIAJH4F[0]\ : MX2 - port map(A => hrdata_0_21, B => maddress(21), S => idle, Y - => istate_RNIAJH4F(0)); - - \r.vaddress_RNISFAKMI[14]\ : NOR2 - port map(A => \un1_ici\, B => N_970, Y => - vaddress_RNISFAKMI(14)); - - \r.burst_RNO\ : NOR2B - port map(A => rst, B => N_1202, Y => burst_RNO_0); - - \ictrl.v.burst_1_iv\ : NAND2 - port map(A => req_7_m, B => burst_1_iv_0, Y => burst_1); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.vaddress_RNI8EVQ36[2]\ : MX2C - port map(A => N_1143, B => N_1121, S => N_1163_i, Y => - vaddress_RNI8EVQ36(2)); - - \r.vaddress_RNI6GAKMI[19]\ : NOR2 - port map(A => \un1_ici\, B => N_975, Y => - vaddress_RNI6GAKMI(19)); - - \r.istate_RNIPDUI[0]\ : MX2C - port map(A => fpc(2), B => addr(2), S => diagen_0_sqmuxa_0, - Y => N_1121); - - \r.istate_RNIEON21_4[0]\ : MX2 - port map(A => dataout_2(14), B => dataout_1(18), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_18); - - \r.istate_RNIAP6PI[0]\ : MX2 - port map(A => N_78_0, B => maddress(25), S => idle_0, Y => - istate_RNIAP6PI(0)); - - \r.istate_RNIEON21_16[0]\ : MX2 - port map(A => dataout_2(24), B => dataout_2(28), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_28); - - \r.valid[4]\ : DFN1E0 - port map(D => \valid_1[4]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[4]\); - - \r.vaddress[29]\ : DFN1E1 - port map(D => fpc(29), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[29]\); - - \r.istate_RNIEON21_20[0]\ : MX2 - port map(A => dataout_2(20), B => dataout_1(24), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_24); - - \r.istate_RNIE52AJ[0]\ : MX2 - port map(A => hrdata_0_14, B => dataout_1(14), S => - istate_1259_d, Y => data_0(14)); - - \ictrl.0.un1_ici_8_0\ : XNOR2 - port map(A => dataout_2(16), B => fpc(20), Y => - un1_ici_8_i_0); - - \r.holdn_RNO_3\ : OR3 - port map(A => un5_eholdn, B => \istate[1]\, C => un2_eholdn, - Y => N_1331); - - \un1_r.faddr_I_16\ : AND3 - port map(A => \faddr[0]\, B => \faddr[1]\, C => \faddr[2]\, - Y => \DWACT_FINC_E[0]\); - - \r.flush_RNI0U5C\ : OR2A - port map(A => ics(0), B => \flush_0\, Y => cacheon_1); - - \r.istate_RNI2MM6D[0]\ : MX2 - port map(A => N_264_0, B => maddress(19), S => idle, Y => - istate_RNI2MM6D(0)); - - \r.istate_RNIM369G[0]\ : MX2 - port map(A => hrdata_0_1, B => dataout_1(1), S => - istate_1259_d_0, Y => data_0(1)); - - \r.istate_RNIJGCD_0[0]\ : OR2A - port map(A => \istate[1]\, B => \istate[0]\, Y => - istate_1259_d); - - \r.istate_RNID2NN[0]\ : MX2C - port map(A => fpc(10), B => addr(10), S => diagen_0_sqmuxa, - Y => N_1129); - - \r.faddr_RNO[3]\ : NOR2B - port map(A => \flush2\, B => I_13_4, Y => \faddr_1[3]\); - - \r.waddress_RNO[26]\ : MX2C - port map(A => N_1063, B => N_361, S => error_1_sqmuxa_0, Y - => \waddress_1[26]\); - - \ictrl.hit_1_12\ : NOR3C - port map(A => un1_ici_5_i_0, B => un1_ici_4_i_0, C => - hit_1_4, Y => hit_1_12); - - \un1_r.faddr_I_30\ : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \faddr[5]\, Y => N_4); - - \r.istate_RNIQARG[0]\ : NOR2B - port map(A => idle, B => enable, Y => diagen_0_sqmuxa); - - \ictrl.0.un1_icramo_7_0\ : XNOR2 - port map(A => dataout_0(35), B => ctx_0_5, Y => - un1_icramo_7_i); - - \r.waddress_RNO[30]\ : MX2C - port map(A => N_1067, B => N_43, S => error_1_sqmuxa, Y => - \waddress_1[30]\); - - \r.vaddress_RNIFRPEO8[5]\ : MX2C - port map(A => rpc_3, B => \vaddress[5]\, S => - taddr_0_sqmuxa_1, Y => N_1146); - - \r.waddress_RNO_0[7]\ : MX2C - port map(A => \address[7]\, B => fpc(7), S => - vaddress_0_sqmuxa_1, Y => N_1044); - - \un1_r.faddr_I_31\ : XOR2 - port map(A => N_4, B => \faddr[6]\, Y => I_31_0); - - \r.waddress_RNO[8]\ : MX2C - port map(A => N_1045, B => un1_m0_6, S => error_1_sqmuxa, Y - => \waddress_1[8]\); - - \r.vaddress_RNIPQAN[12]\ : MX2C - port map(A => \vaddress[12]\, B => maddress(12), S => - diagen_0_sqmuxa, Y => N_968); - - \r.cache_RNIKGGB1\ : NOR3B - port map(A => twrite_3_iv_0, B => hit_RNIR2PJ, C => bo_d(3), - Y => twrite_3_iv_2); - - \r.vaddress[17]\ : DFN1E1 - port map(D => fpc(17), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[17]\); - - \r.istate_RNIUCOFG[0]\ : MX2 - port map(A => hrdata_0_0, B => maddress(0), S => idle, Y - => istate_RNIUCOFG(0)); - - \r.vaddress_RNIVQAN[15]\ : MX2C - port map(A => \vaddress[15]\, B => maddress(15), S => - diagen_0_sqmuxa_0, Y => N_971); - - \r.vaddress[10]\ : DFN1E1 - port map(D => fpc(10), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[10]\); - - \ictrl.valid_1_7\ : MX2C - port map(A => N_962, B => N_965, S => fpc(2), Y => valid_1); - - \r.waddress[23]\ : DFN1 - port map(D => \waddress_1[23]\, CLK => lclk_c, Q => - \address[23]\); - - \r.valid[0]\ : DFN1E0 - port map(D => \valid_1[0]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[0]\); - - \r.faddr_RNO[4]\ : NOR2B - port map(A => \flush2\, B => I_20_0, Y => \faddr_1[4]\); - - \r.istate_RNI8FCK8[0]\ : MX2 - port map(A => hrdata_0_16, B => dataout_1(16), S => - istate_1259_d, Y => data_0(16)); - - \r.waddress[7]\ : DFN1 - port map(D => \waddress_1[7]\, CLK => lclk_c, Q => - \address[7]\); - - \r.vaddress[31]\ : DFN1E1 - port map(D => fpc(31), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[31]\); - - \ictrl.hit_1_8\ : XA1A - port map(A => fpc(26), B => dataout_2(22), C => - un1_ici_15_i_0, Y => hit_1_8); - - \r.overrun_RNI75H932\ : MX2 - port map(A => rbranch, B => fbranch, S => overrun, Y => - N_1372); - - \r.valid_RNIO72H2[3]\ : MX2C - port map(A => \vmask_6[3]\, B => maddress(3), S => - diagen_0_sqmuxa_0, Y => N_1105); - - \r.vaddress_RNIFCB8U6[3]\ : MX2C - port map(A => N_1144, B => N_1122, S => N_1163_i, Y => - vaddress_RNIFCB8U6(3)); - - \r.istate_RNIOV0LD[0]\ : MX2 - port map(A => hrdata_1, B => dataout_1(6), S => - istate_1259_d, Y => data_0(6)); - - \r.waddress_RNO_0[25]\ : MX2C - port map(A => \address[25]\, B => fpc(25), S => - vaddress_0_sqmuxa_1, Y => N_1062); - - \r.istate_RNIQARG_0[0]\ : NOR2B - port map(A => idle_0, B => enable, Y => diagen_0_sqmuxa_0); - - \r.istate_RNIEON21_17[0]\ : MX2 - port map(A => dataout_2(27), B => dataout_2(31), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_31); - - \r.faddr_RNO[0]\ : NOR2A - port map(A => \un1_p0_2_0[148]\, B => \faddr[0]\, Y => - \faddr_1[0]\); - - \r.faddr_RNI7UFASD[5]\ : MX2 - port map(A => \taddr_9[10]\, B => \faddr[5]\, S => \flush2\, - Y => faddr_RNI7UFASD(5)); - - \r.waddress_RNO_0[3]\ : MX2C - port map(A => \waddress_4[3]\, B => fpc(3), S => - vaddress_0_sqmuxa_1, Y => N_1040); - - \r.istate_RNI80L93[0]\ : NOR3C - port map(A => idle_0, B => istate_0_sqmuxa_0_a3_m6_1, C => - istate_0_sqmuxa_0_a3_m2_e, Y => istate_0_sqmuxa_0_a3_m6_3); - - \r.faddr_RNI7H6KT8[0]\ : MX2 - port map(A => \taddr_9[5]\, B => \faddr[0]\, S => - \un1_p0_2_0[148]\, Y => faddr_RNI7H6KT8(0)); - - \r.holdn_RNO_2\ : OR3C - port map(A => N_1350, B => N_1320, C => N_1331, Y => N_1312); - - \r.waddress_RNIFG73_1[4]\ : NOR3B - port map(A => \address[3]\, B => \address[4]\, C => - \address[2]\, Y => \un95_res[6]\); - - \r.vaddress_RNI0GAKMI[16]\ : NOR2 - port map(A => \un1_ici\, B => N_972, Y => - vaddress_RNI0GAKMI(16)); - - \r.vaddress_RNI13BN[23]\ : MX2C - port map(A => \vaddress[23]\, B => maddress(23), S => - diagen_0_sqmuxa, Y => N_979); - - \ictrl.0.un1_ici_4_0\ : XNOR2 - port map(A => dataout_2(12), B => fpc(16), Y => - un1_ici_4_i_0); - - \r.waddress_RNO_0[9]\ : MX2C - port map(A => \address[9]\, B => fpc(9), S => - vaddress_0_sqmuxa_0, Y => N_1046); - - \r.vaddress[13]\ : DFN1E1 - port map(D => fpc(13), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[13]\); - - \r.holdn_RNO\ : OR2B - port map(A => rst, B => holdn_1_i, Y => holdn_RNO); - - \r.valid_RNIPTEC[7]\ : AO1 - port map(A => hit, B => \valid[7]\, C => \un95_res[7]\, Y - => N_1017); - - \r.faddr_RNI0FOJNE[4]\ : MX2 - port map(A => \taddr_9[9]\, B => \faddr[4]\, S => \flush2\, - Y => faddr_RNI0FOJNE(4)); - - \r.cache_RNI0F2K\ : NOR3C - port map(A => hcache, B => ba, C => cache, Y => - twrite_3_iv_0); - - \r.istate_RNI42CGI[0]\ : MX2 - port map(A => hrdata_0_24, B => dataout_1(24), S => - istate_1259_d, Y => data_0(24)); - - \r.faddr_RNO[1]\ : NOR2B - port map(A => \un1_p0_2_0[148]\, B => I_5_0, Y => - \faddr_1[1]\); - - \r.waddress_RNIFG73_5[4]\ : NOR3A - port map(A => \address[2]\, B => \address[3]\, C => - \address[4]\, Y => \un95_res[1]\); - - \r.istate_RNIGUTA8[0]\ : MX2 - port map(A => hrdata_0_9, B => maddress(9), S => idle_0, Y - => istate_RNIGUTA8(0)); - - \r.istate_RNI2UDGE[0]\ : MX2 - port map(A => hrdata_23, B => dataout_2(28), S => - istate_1259_d_0, Y => data_0(28)); - - \r.waddress[17]\ : DFN1 - port map(D => \waddress_1[17]\, CLK => lclk_c, Q => - \address[17]\); - - \r.istate_RNIV33V9[0]\ : MX2 - port map(A => hrdata_0_7, B => maddress(7), S => idle_0, Y - => istate_RNIV33V9(0)); - - \ictrl.un2_eholdn_0_0\ : NOR2A - port map(A => un2_eholdn_0, B => un1_p0_6(0), Y => - un2_eholdn_0_0); - - \r.waddress_RNO[23]\ : MX2C - port map(A => N_1060, B => N_359, S => error_1_sqmuxa, Y - => \waddress_1[23]\); - - \r.valid[6]\ : DFN1E0 - port map(D => \valid_1[6]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[6]\); - - \r.flush_RNO_2\ : AO1D - port map(A => underrun2, B => N_1346_1, C => \istate[0]\, Y - => N_1333); - - \r.diagrdy\ : DFN1 - port map(D => diagen_0_sqmuxa, CLK => lclk_c, Q => diagrdy); - - \r.istate_RNIB42J7[0]\ : MX2 - port map(A => hrdata_0_22, B => dataout_1(22), S => - istate_1259_d, Y => data_0(22)); - - \r.istate_RNI1EVI[0]\ : MX2 - port map(A => fpc(6), B => addr(6), S => diagen_0_sqmuxa, Y - => N_1125); - - \r.istate_RNI0RDT6[0]\ : MX2 - port map(A => hrdata_0_10, B => dataout_1(10), S => - istate_1259_d_0, Y => data_0(10)); - - \r.flush2_RNIFMGM2\ : NOR2 - port map(A => \flush2\, B => N_1108, Y => flush2_RNIFMGM2); - - \r.flush2\ : DFN1 - port map(D => \faddr_RNID788NI[6]\, CLK => lclk_c, Q => - \flush2\); - - \r.waddress_RNO_0[14]\ : MX2C - port map(A => \address[14]\, B => fpc(14), S => - vaddress_0_sqmuxa_0, Y => N_1051); - - \r.underrun_RNO_2\ : OR2A - port map(A => underrun2, B => overrun_4, Y => underrun_1_0); - - \r.waddress_RNI3LUL_2[4]\ : AO1D - port map(A => dataout_2(2), B => \un95_res[2]\, C => - cacheon_1, Y => N_1022); - - \r.waddress[8]\ : DFN1 - port map(D => \waddress_1[8]\, CLK => lclk_c, Q => - \address[8]\); - - \r.istate_RNO_2[1]\ : OR3A - port map(A => \istate[0]\, B => \istate[1]\, C => N_66_0, Y - => N_1348); - - \r.flush_RNO\ : OA1 - port map(A => N_1214, B => \un1_ici\, C => rst, Y => - flush_RNO); - - \r.vaddress[3]\ : DFN1 - port map(D => \vaddress_1[3]\, CLK => lclk_c, Q => - \vaddress[3]\); - - \r.istate_RNIVDCAH[0]\ : MX2 - port map(A => hrdata_0_15, B => dataout_1(15), S => - istate_1259_d_0, Y => data_0(15)); - - \r.istate_RNIU60D8[0]\ : MX2 - port map(A => hrdata_0_9, B => dataout_1(9), S => - istate_1259_d_0, Y => data_0(9)); - - \r.valid_RNIQB2H2[4]\ : MX2B - port map(A => \vmask_6[4]\, B => maddress(4), S => - diagen_0_sqmuxa, Y => N_1106); - - \r.faddr_RNO[6]\ : NOR2B - port map(A => \flush2\, B => I_31_0, Y => \faddr_1[6]\); - - \r.vaddress[15]\ : DFN1E1 - port map(D => fpc(15), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[15]\); - - \r.istate_RNO_0[0]\ : OA1 - port map(A => N_1350, B => underrun2, C => - \istate_0_sqmuxa\, Y => \istate_ns_0_0[0]\); - - \r.istate_RNIEON21_19[0]\ : MX2 - port map(A => dataout_2(23), B => dataout_1(27), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_27); - - \r.istate_RNIEON21_21[0]\ : MX2 - port map(A => dataout_2(19), B => dataout_1(23), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_23); - - \r.waddress_RNO[5]\ : MX2C - port map(A => N_1042, B => un1_m0_3, S => error_1_sqmuxa_0, - Y => \waddress_1[5]\); - - \r.valid_RNIM32H2[2]\ : MX2C - port map(A => \vmask_6[2]\, B => maddress(2), S => - diagen_0_sqmuxa_0, Y => N_1104); - - \r.waddress_RNO_0[10]\ : MX2C - port map(A => \address[10]\, B => fpc(10), S => - vaddress_0_sqmuxa_1, Y => N_1047); - - \r.waddress_RNO[28]\ : MX2C - port map(A => N_1065, B => N_321, S => error_1_sqmuxa_0, Y - => \waddress_1[28]\); - - \r.vaddress[27]\ : DFN1E1 - port map(D => fpc(27), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[27]\); - - \r.istate_RNIA8N5H[0]\ : MX2 - port map(A => hrdata_0_15, B => maddress(15), S => idle_0, - Y => istate_RNIA8N5H(0)); - - \r.vaddress[4]\ : DFN1 - port map(D => \vaddress_1[4]\, CLK => lclk_c, Q => - \vaddress[4]\); - - \r.vaddress[20]\ : DFN1E1 - port map(D => fpc(20), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[20]\); - - \r.vaddress_RNI3BBN[31]\ : MX2 - port map(A => \vaddress[31]\, B => maddress(31), S => - diagen_0_sqmuxa, Y => N_987); - - \r.flush2_0_0_RNIPJ5O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1102, Y => - flush2_0_0_RNIPJ5O2); - - \r.waddress_RNO_0[29]\ : MX2C - port map(A => \address[29]\, B => fpc(29), S => - vaddress_0_sqmuxa_0, Y => N_1066); - - \r.waddress_RNO_0[13]\ : MX2C - port map(A => \address[13]\, B => fpc(13), S => - vaddress_0_sqmuxa_0, Y => N_1050); - - \r.waddress_RNO_0[8]\ : MX2C - port map(A => \address[8]\, B => fpc(8), S => - vaddress_0_sqmuxa_0, Y => N_1045); - - \r.valid_RNO[0]\ : MX2 - port map(A => \vmask_6[0]\, B => dataout_2(0), S => - twrite_3, Y => \valid_1[0]\); - - \r.istate_RNIEON21_3[0]\ : MX2 - port map(A => dataout_2(15), B => dataout_1(19), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_19); - - \r.waddress[31]\ : DFN1 - port map(D => \waddress_1[31]\, CLK => lclk_c, Q => - \address[31]\); - - \r.flush2_0_0_RNI146O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1106, Y => - flush2_0_0_RNI146O2); - - \r.valid_RNIUJ2H2[6]\ : MX2B - port map(A => \vmask_6[6]\, B => maddress(6), S => - diagen_0_sqmuxa, Y => N_1108); - - \r.istate_RNITTUI[0]\ : MX2C - port map(A => fpc(4), B => addr(4), S => diagen_0_sqmuxa_0, - Y => N_1123); - - \r.waddress_RNO_0[21]\ : MX2C - port map(A => \address[21]\, B => fpc(21), S => - vaddress_0_sqmuxa_1, Y => N_1058); - - \r.valid_RNO[7]\ : MX2A - port map(A => \vmask_6[7]\, B => dataout_2(7), S => - twrite_3, Y => \valid_1[7]\); - - \r.vaddress[2]\ : DFN1 - port map(D => \vaddress_1[2]\, CLK => lclk_c, Q => - \vaddress[2]\); - - \r.overrun_RNO_0\ : MX2 - port map(A => overrun_4, B => overrun, S => istate_1259_d, - Y => N_1212); - - \ictrl.0.un1_icramo_0_0\ : XNOR2 - port map(A => dataout_1(28), B => ctx_0_d0, Y => - un1_icramo_0_i); - - \r.istate_RNI5UVI[0]\ : MX2C - port map(A => fpc(8), B => addr(8), S => diagen_0_sqmuxa, Y - => N_1127); - - \r.waddress_RNI3LUL_4[4]\ : OA1B - port map(A => \un95_res[6]\, B => dataout_2(6), C => - cacheon_1, Y => N_1026); - - \r.istate_RNIG2KP8[0]\ : MX2 - port map(A => hrdata_25, B => dataout_2(30), S => - istate_1259_d_0, Y => data_0(30)); - - \r.holdn_RNIFCHA_0\ : CLKINT - port map(A => holdn_RNIFCHA, Y => holdn); - - \r.waddress_RNI3LUL_6[4]\ : OA1B - port map(A => \un95_res[7]\, B => dataout_2(7), C => - cacheon_1, Y => N_1027); - - \r.flush2_RNIJENP\ : OR2A - port map(A => N_1346_1, B => istate_1259_d_0, Y => N_1350); - - \r.burst_RNIHK5U1\ : NOR3C - port map(A => burst, B => \burst_0\, C => un1_mcio_1_i_0, Y - => req_7_1); - - \r.hit\ : DFN1 - port map(D => hit_RNO, CLK => lclk_c, Q => hit); - - \r.faddr[4]\ : DFN1E1 - port map(D => \faddr_1[4]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[4]\); - - \r.valid_RNIL7DS1[1]\ : MX2C - port map(A => N_1011, B => N_1021, S => N_1028_i, Y => - \vmask_6[1]\); - - \r.burst_RNIO5BQ21\ : AOI1B - port map(A => underrun_2, B => cacheon_1, C => req_7_1, Y - => req_7); - - \r.waddress_RNO[6]\ : MX2C - port map(A => N_1043, B => un1_m0_4, S => error_1_sqmuxa_0, - Y => \waddress_1[6]\); - - \r.istate_RNI06RLB[0]\ : MX2 - port map(A => hrdata_0_3, B => dataout_1(3), S => - istate_1259_d, Y => data_0(3)); - - \r.flush_RNIAUIQ3\ : NOR3B - port map(A => twrite_3_iv_2, B => mexc, C => cacheon_1, Y - => twrite_3_iv_4); - - \ictrl.0.un1_ici_3_0\ : XNOR2 - port map(A => dataout_2(11), B => fpc(15), Y => - un1_ici_3_i_0); - - \un1_r.faddr_I_5\ : XOR2 - port map(A => \faddr[0]\, B => \faddr[1]\, Y => I_5_0); - - \r.burst_RNO_2\ : OR3C - port map(A => ready, B => \istate[1]\, C => grant, Y => - burst_2_sqmuxa); - - \ictrl.valid_1_4\ : MX2 - port map(A => dataout_2(1), B => dataout_2(5), S => fpc(4), - Y => N_963); - - \r.flush_RNI1B573\ : NOR3C - port map(A => hit_1_10, B => hit_1_9, C => hit_1_16, Y => - hit_1_18); - - \r.faddr_RNISJSHQA[2]\ : MX2A - port map(A => \taddr_9[7]\, B => \faddr[2]\, S => \flush2\, - Y => faddr_RNISJSHQA(2)); - - \r.valid_RNINTEC[5]\ : AO1 - port map(A => hit, B => \valid[5]\, C => \un95_res[5]\, Y - => N_1015); - - \r.vaddress[23]\ : DFN1E1 - port map(D => fpc(23), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[23]\); - - \ictrl.0.un1_ici_10_0_RNICJUL1\ : NOR3C - port map(A => hit_1_8, B => hit_1_7, C => hit_1_13, Y => - hit_1_17); - - \r.vaddress[5]\ : DFN1E1 - port map(D => fpc(5), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[5]\); - - \r.istate_RNIJGCD_2[0]\ : OR2A - port map(A => \istate[0]\, B => \istate[1]\, Y => N_1320); - - \r.waddress_RNO[25]\ : MX2C - port map(A => N_1062, B => N_2626, S => error_1_sqmuxa, Y - => \waddress_1[25]\); - - \r.istate_RNI7E0781[0]\ : OR3A - port map(A => istate_0_sqmuxa_0_a3_m6_5, B => - xc_exception_1_0, C => ldlock_2, Y => \istate_0_sqmuxa\); - - \r.istate_RNIEON21_10[0]\ : MX2 - port map(A => dataout_0(35), B => dataout_1(8), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_8); - - \r.flush_RNIVHR2A\ : NOR3B - port map(A => valid_1, B => hit_1, C => cacheon_1, Y => - un5_eholdn); - - \ictrl.0.un1_icramo_1_0_0\ : XNOR2 - port map(A => dataout_1(29), B => ctx_1, Y => - un1_icramo_1_0_i); - - \r.waddress_RNO_0[26]\ : MX2C - port map(A => \address[26]\, B => fpc(26), S => - vaddress_0_sqmuxa_0, Y => N_1063); - - \r.trans_op_RNO_2\ : OR2B - port map(A => flush_op_i_0, B => trans_op_0_a2_0, Y => - trans_op_RNO_2); - - \r.flush_RNIRF2B91\ : NOR2 - port map(A => e, B => holdn_0_sqmuxa_1, Y => - istate_1_sqmuxa); - - \r.waddress[27]\ : DFN1 - port map(D => \waddress_1[27]\, CLK => lclk_c, Q => - \address[27]\); - - \ictrl.v.burst_1_iv_RNO_3\ : NOR2B - port map(A => \req\, B => \istate[1]\, Y => burst_5_m_0); - - \r.istate_RNIIMI4I1[0]\ : NOR3A - port map(A => un5_m_en, B => N_66, C => N_1320, Y => - error_1_sqmuxa_0); - - \r.vaddress_RNIP1HGO9[6]\ : MX2 - port map(A => N_28, B => \vaddress[6]\, S => - taddr_0_sqmuxa_1, Y => N_1147); - - \r.istate_RNI760J[0]\ : MX2C - port map(A => fpc(9), B => addr(9), S => diagen_0_sqmuxa, Y - => N_1128); - - \ictrl.0.un1_ici_10_0_RNI3305\ : AND2 - port map(A => un1_ici_11_i_0, B => un1_ici_10_i_0, Y => - hit_1_6); - - \r.valid[3]\ : DFN1E0 - port map(D => \valid_1[3]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[3]\); - - \ictrl.hit_1_1\ : XA1A - port map(A => fpc(28), B => dataout_2(24), C => - un1_ici_0_i_0, Y => hit_1_1); - - \r.istate_RNIEON21_7[0]\ : MX2 - port map(A => dataout_2(11), B => dataout_1(15), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_15); - - \r.faddr_RNIKVTLT9[1]\ : MX2A - port map(A => \taddr_9[6]\, B => \faddr[1]\, S => - \un1_p0_2_0[148]\, Y => faddr_RNIKVTLT9(1)); - - \r.waddress_RNO[11]\ : MX2C - port map(A => N_1048, B => un1_m0_9, S => error_1_sqmuxa, Y - => \waddress_1[11]\); - - \r.istate_RNIVR9M[0]\ : OR2A - port map(A => diagen_0_sqmuxa, B => asi(0), Y => - cdwrite_0_sqmuxa_i_0); - - \r.istate_RNIO6LI[0]\ : OR2A - port map(A => idle, B => hold, Y => taddr_0_sqmuxa); - - \r.valid_RNIM7DS1[2]\ : MX2C - port map(A => N_1012, B => N_1022, S => N_1028_i, Y => - \vmask_6[2]\); - - \r.vaddress_RNIIE0GIE[9]\ : MX2C - port map(A => rpc_7, B => \vaddress[9]\, S => - taddr_0_sqmuxa_1, Y => N_1150); - - \r.valid_RNO[5]\ : MX2A - port map(A => \vmask_6[5]\, B => dataout_2(5), S => - twrite_3, Y => \valid_1[5]\); - - \r.waddress[10]\ : DFN1 - port map(D => \waddress_1[10]\, CLK => lclk_c, Q => - \address[10]\); - - \r.waddress[14]\ : DFN1 - port map(D => \waddress_1[14]\, CLK => lclk_c, Q => - \address[14]\); - - \r.vaddress[25]\ : DFN1E1 - port map(D => fpc(25), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[25]\); - - \r.vaddress_RNISNAKMI[21]\ : NOR2 - port map(A => \un1_ici\, B => N_977, Y => - vaddress_RNISNAKMI(21)); - - \ictrl.0.un1_ici_11_0\ : XNOR2 - port map(A => fpc(23), B => dataout_2(19), Y => - un1_ici_11_i_0); - - \r.vaddress_RNI4GAKMI[18]\ : NOR2 - port map(A => \un1_ici\, B => N_974, Y => - vaddress_RNI4GAKMI(18)); - - \r.waddress_RNO_0[22]\ : MX2C - port map(A => \address[22]\, B => fpc(22), S => - vaddress_0_sqmuxa_1, Y => N_1059); - - \r.vaddress_RNIR2BN[20]\ : MX2C - port map(A => \vaddress[20]\, B => maddress(20), S => - diagen_0_sqmuxa, Y => N_976); - - \r.istate_RNIVTQIJ[0]\ : MX2 - port map(A => N_262_0, B => maddress(20), S => idle, Y => - istate_RNIVTQIJ(0)); - - \r.istate_RNIENB3M[0]\ : MX2 - port map(A => hrdata_26, B => maddress(31), S => idle_0, Y - => istate_RNIENB3M(0)); - - \r.waddress_RNO_0[18]\ : MX2C - port map(A => \address[18]\, B => fpc(18), S => - vaddress_0_sqmuxa_0, Y => N_1055); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutw is - - port( data_1 : out std_logic_vector(31 downto 12); - address : out std_logic_vector(31 downto 2); - twowner : in std_logic_vector(0 to 0); - twowner_2 : in std_logic_vector(0 to 0); - aaddr_0_25 : in std_logic; - aaddr_0_24 : in std_logic; - aaddr_0_29 : in std_logic; - aaddr_0_18 : in std_logic; - aaddr_0_17 : in std_logic; - aaddr_0_9 : in std_logic; - aaddr_0_8 : in std_logic; - aaddr_0_7 : in std_logic; - aaddr_0_4 : in std_logic; - aaddr_0_0 : in std_logic; - aaddr_0_21 : in std_logic; - aaddr_0_22 : in std_logic; - aaddr_0_23 : in std_logic; - aaddr_0_28 : in std_logic; - aaddr_0_27 : in std_logic; - aaddr_0_26 : in std_logic; - aaddr_0_20 : in std_logic; - aaddr_0_19 : in std_logic; - aaddr_0_16 : in std_logic; - aaddr_0_15 : in std_logic; - aaddr_0_14 : in std_logic; - aaddr_0_13 : in std_logic; - aaddr_0_12 : in std_logic; - aaddr_0_11 : in std_logic; - aaddr_0_10 : in std_logic; - aaddr_0_6 : in std_logic; - aaddr_0_3 : in std_logic; - aaddr_0_2 : in std_logic; - aaddr_0_1 : in std_logic; - aaddr_25 : in std_logic; - aaddr_24 : in std_logic; - aaddr_29 : in std_logic; - aaddr_18 : in std_logic; - aaddr_17 : in std_logic; - aaddr_9 : in std_logic; - aaddr_8 : in std_logic; - aaddr_7 : in std_logic; - aaddr_4 : in std_logic; - aaddr_0_d0 : in std_logic; - aaddr_21 : in std_logic; - aaddr_22 : in std_logic; - aaddr_23 : in std_logic; - aaddr_28 : in std_logic; - aaddr_27 : in std_logic; - aaddr_26 : in std_logic; - aaddr_20 : in std_logic; - aaddr_19 : in std_logic; - aaddr_16 : in std_logic; - aaddr_15 : in std_logic; - aaddr_14 : in std_logic; - aaddr_13 : in std_logic; - aaddr_12 : in std_logic; - aaddr_11 : in std_logic; - aaddr_10 : in std_logic; - aaddr_6 : in std_logic; - aaddr_3 : in std_logic; - aaddr_2 : in std_logic; - aaddr_1 : in std_logic; - twowner_1 : in std_logic_vector(0 to 0); - data_0 : in std_logic_vector(31 downto 12); - data_11 : out std_logic; - data_10 : out std_logic; - data_9 : out std_logic; - data_8 : out std_logic; - data_7 : out std_logic; - data_6 : out std_logic; - data_4 : out std_logic; - data_3 : out std_logic; - data_2 : out std_logic; - data_1_d0 : out std_logic; - data_0_d0 : out std_logic; - data_12 : in std_logic; - data_18 : in std_logic; - data_24 : in std_logic; - data_16 : in std_logic; - data_22 : in std_logic; - data_28 : in std_logic; - data_20 : in std_logic; - data_26 : in std_logic; - data_17 : in std_logic; - data_15 : in std_logic; - data_14 : in std_logic; - data_13 : in std_logic; - data_23 : in std_logic; - data_29 : in std_logic; - data_30 : in std_logic; - data_31 : in std_logic; - data_21 : in std_logic; - data_27 : in std_logic; - data_19 : in std_logic; - data_25 : in std_logic; - adata_0_19 : in std_logic; - adata_0_20 : in std_logic; - adata_0_18 : in std_logic; - adata_0_10 : in std_logic; - adata_0_2 : in std_logic; - adata_0_13 : in std_logic; - adata_0_14 : in std_logic; - adata_0_30 : in std_logic; - adata_0_29 : in std_logic; - adata_0_28 : in std_logic; - adata_0_6 : in std_logic; - adata_0_1 : in std_logic; - adata_0_0 : in std_logic; - adata_0_31 : in std_logic; - adata_0_17 : in std_logic; - adata_0_7 : in std_logic; - adata_0_25 : in std_logic; - adata_0_22 : in std_logic; - adata_0_11 : in std_logic; - adata_0_24 : in std_logic; - adata_0_23 : in std_logic; - adata_0_15 : in std_logic; - adata_0_12 : in std_logic; - adata_0_21 : in std_logic; - adata_0_16 : in std_logic; - adata_0_9 : in std_logic; - adata_0_8 : in std_logic; - adata_0_26 : in std_logic; - adata_0_27 : in std_logic; - adata_0_4 : in std_logic; - adata_0_3 : in std_logic; - adata_19 : in std_logic; - adata_20 : in std_logic; - adata_18 : in std_logic; - adata_10 : in std_logic; - adata_2 : in std_logic; - adata_13 : in std_logic; - adata_14 : in std_logic; - adata_30 : in std_logic; - adata_29 : in std_logic; - adata_28 : in std_logic; - adata_6 : in std_logic; - adata_1 : in std_logic; - adata_0_d0 : in std_logic; - adata_31 : in std_logic; - adata_17 : in std_logic; - adata_7 : in std_logic; - adata_25 : in std_logic; - adata_22 : in std_logic; - adata_11 : in std_logic; - adata_24 : in std_logic; - adata_23 : in std_logic; - adata_15 : in std_logic; - adata_12 : in std_logic; - adata_21 : in std_logic; - adata_16 : in std_logic; - adata_9 : in std_logic; - adata_8 : in std_logic; - adata_26 : in std_logic; - adata_27 : in std_logic; - adata_4 : in std_logic; - adata_3 : in std_logic; - twowner_0 : in std_logic_vector(0 to 0); - lvl_i_1 : out std_logic_vector(1 downto 0); - ctx_0_d0 : in std_logic; - ctx_1 : in std_logic; - ctx_2 : in std_logic; - ctx_3 : in std_logic; - ctx_6 : in std_logic; - ctx_7 : in std_logic; - hrdata : in std_logic_vector(6 downto 5); - iosn_0 : in std_logic_vector(93 to 93); - ctx_0 : in std_logic_vector(5 downto 4); - ctxp : in std_logic_vector(25 downto 0); - hrdata_0_3 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_27 : in std_logic; - lvl_i_1_0 : out std_logic_vector(1 to 1); - lclk_c : in std_logic; - grant : in std_logic; - N_264_0 : in std_logic; - N_262_0 : in std_logic; - N_82 : out std_logic; - N_80 : out std_logic; - N_709 : in std_logic; - finish : out std_logic; - N_78_0 : in std_logic; - d_N_6_1 : out std_logic; - N_2563_i_0_a4_m7_0_a2_1 : out std_logic; - fault_trans_i_2 : out std_logic; - walk_op_2_0_0_o2_0 : out std_logic; - N_2488 : in std_logic; - N_2487 : in std_logic; - read : out std_logic; - bo_5842_d_0 : in std_logic; - ba : in std_logic; - req : out std_logic; - inv_1_0_a2_0_a2_0 : out std_logic; - rst : in std_logic; - mexc : in std_logic; - fault_mexc : out std_logic; - N_2484 : in std_logic; - N_2485 : in std_logic; - N_207 : out std_logic - ); - -end mmutw; - -architecture DEF_ARCH of mmutw is - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_456_0, N_206, N_365, N_215_0, N_204_0, N_366, - N_366_0, N_388_0, N_210, \state_i[5]\, N_226, \state[4]\, - walk_op, \N_207\, fault_mexc_1_0_a2_0_a2_0, - \addr_1_i_i_0[31]\, N_610, \addr_1_i_i_0[26]\, N_622, - \addr_1_i_i_0[27]\, N_625, \addr_1_i_i_0[10]\, N_712, - N_652, \addr_1_i_i_0[11]\, N_309, \addr_1_i_i_0[19]\, - N_721, N_331, \addr_1_i_i_0[20]\, N_722, N_334, - \addr_1_i_i_0_0[9]\, \addr_1_i_i_0_tz[9]\, N_589, - \addr_1_1_0_0[2]\, N_369, N_626, N_355, - \addr_1_i_i_0[23]\, N_725, N_596, \addr_1_i_i_0[24]\, - N_726, N_599, \addr_1_i_i_0[21]\, N_592, - \addr_1_i_i_0[22]\, N_595, \addr_1_i_i_0[29]\, N_728, - N_602, \addr_1_i_i_0[30]\, N_729, N_605, - \addr_1_i_i_0[25]\, N_619, \addr_1_i_i_0[28]\, N_727, - N_627, \addr_1_i_i_0[12]\, N_714, N_310, - \addr_1_i_i_0[13]\, N_715, N_313, \addr_1_i_i_0[14]\, - N_716, N_316, \addr_1_i_i_0[15]\, N_321, - \addr_1_i_i_0[16]\, N_324, \addr_1_i_i_0[17]\, N_719, - N_325, \addr_1_i_i_0[18]\, N_330, \addr_1_i_i_0_0[8]\, - \addr_1_i_i_0_tz[8]\, N_586, \addr_1_1_0_0[5]\, N_629, - N_343, \addr_1_1_0_0[4]\, N_628, N_347, \addr_1_1_0_0[3]\, - N_627_0, N_351, \addr_1_i_0_0[6]\, \addr_1_i_0_a2_1[6]\, - N_339, \addr_1_i_i_1[7]\, \addr_1_i_i_o2_0[7]\, N_361, - \addr_1_i_i_0[7]\, N_647, N_358, \addr_1_i_i_a2_2_0[7]\, - N_225, addr_1_1_0_a2_3_5_m2_0, \state[1]\, - \state_ns_0_0_0_a2_0[0]\, walk_op_2_0_0_a2_1_0, - \state[0]\, fault_trans_1_i_0_0_0, req_2_0_0_a2_0_0, - \fault_lvl_1_0_iv_0_a2_i_o2_0[0]\, \req\, - \state_RNIP074T3_0[0]\, N_189, N_205, \addr_1[3]\, N_349, - N_352, \addr_1[4]\, N_345, N_348, \addr_1[5]\, N_341, - N_344, N_11, N_53_1, N_178, N_176, N_174, N_172, N_170, - N_168, N_166, N_582, N_579, N_43, N_39, N_17, N_15, N_651, - N_630, N_645, N_648, N_617, walk_op_RNO, N_646, N_35, - N_23, N_204, \addr_1[2]\, N_353, N_356, N_479, N_338, - N_340, N_13, N_56_1, N_182, N_180, N_164, N_159, N_581, - N_580, N_47, N_231, N_370, \state_i_RNIJP3JC1[5]\, - \state[3]\, N_592_0, N_611, \state_ns_i_0_0_0[2]\, N_386, - \walk_op_2_0_0_o2_0\, \state_nss[1]\, N_633, N_634, - \state_nss[2]\, N_637, \state_nss[4]\, N_642, N_641, - \state_nss[5]\, N_644, N_643, N_710, N_723, N_724, N_220, - N_737, N_388, N_639, N_364, N_367, \state[2]\, N_717, - N_718, N_720, N_230, N_707, N_229, N_706, N_228, N_705, - N_362, N_232, read_RNO, N_215, N_591, N_589_0, N_659, - N_648_0, N_619_0, N_590, N_660, N_618, N_100, N_101, - N_588, N_610_0, N_621, N_622_0, N_624, N_625_0, N_642_0, - N_644_0, N_645_0, N_646_0, N_652_0, N_654, N_655, N_668, - N_669, N_702, N_731, N_3142, N_3143, N_3144, N_3145, - N_3146, \adata_1[14]\, N_643_0, N_99, N_640, - \state_nss[3]\, \state_nss_i_0[0]\, \finish\, N_698, - N_649, N_609, N_623, N_697, N_670, N_653, N_649_0, - req_RNO_0, N_704, N_673, N_616, N_227, N_711, N_730, - N_3148, N_3149, N_713, N_708, \read\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - finish <= \finish\; - walk_op_2_0_0_o2_0 <= \walk_op_2_0_0_o2_0\; - read <= \read\; - req <= \req\; - N_207 <= \N_207\; - - \r.wb.data[11]\ : DFN1E0 - port map(D => N_652_0, CLK => lclk_c, E => N_215_0, Q => - data_11); - - \r.wb.addr_RNO_5[4]\ : MX2C - port map(A => N_659, B => N_648_0, S => twowner_0(0), Y => - N_229); - - \r.wb.addr_RNO_0[30]\ : OA1A - port map(A => N_729, B => N_388_0, C => N_605, Y => - \addr_1_i_i_0[30]\); - - \r.walk_op_2_0_0_o2_0\ : OR2A - port map(A => hrdata_0_0, B => mexc, Y => - \walk_op_2_0_0_o2_0\); - - \r.wb.addr_RNO_0[10]\ : OA1A - port map(A => N_712, B => N_388_0, C => N_652, Y => - \addr_1_i_i_0[10]\); - - \r.wb.data[10]\ : DFN1E0 - port map(D => N_623, CLK => lclk_c, E => N_215_0, Q => - data_10); - - \r.walk_op_RNO_2\ : OR3A - port map(A => rst, B => N_206, C => walk_op, Y => N_646); - - \r.wb.addr_RNO_2[27]\ : MX2 - port map(A => aaddr_25, B => aaddr_0_25, S => twowner(0), Y - => N_3149); - - \r.wb.data[22]\ : DFN1E0 - port map(D => N_654, CLK => lclk_c, E => N_215, Q => - data_1(22)); - - \r.req_RNO\ : AO1B - port map(A => req_2_0_0_a2_0_0, B => grant, C => N_649_0, Y - => req_RNO_0); - - \r.wb.data_RNO[6]\ : MX2 - port map(A => adata_6, B => adata_0_6, S => twowner_2(0), Y - => N_3143); - - \r.wb.data_RNO[15]\ : MX2 - port map(A => adata_15, B => adata_0_15, S => twowner_1(0), - Y => N_644_0); - - \r.wb.addr_RNO_7[4]\ : MX2C - port map(A => data_0(26), B => data_0(20), S => \state[2]\, - Y => N_659); - - \r.state_RNIODA9G2_0[0]\ : OR2A - port map(A => N_206, B => N_365, Y => N_366_0); - - \r.req\ : DFN1 - port map(D => req_RNO_0, CLK => lclk_c, Q => \req\); - - \r.wb.addr_RNO_0[13]\ : OA1A - port map(A => N_715, B => N_388_0, C => N_313, Y => - \addr_1_i_i_0[13]\); - - \r.wb.addr_RNO_1[15]\ : OR2A - port map(A => N_717, B => N_388, Y => N_321); - - \r.wb.addr_RNO[30]\ : AO1C - port map(A => N_204_0, B => ctxp(24), C => - \addr_1_i_i_0[30]\, Y => N_43); - - \r.state_RNO_0[4]\ : OA1B - port map(A => N_386, B => \state[4]\, C => \N_207\, Y => - N_633); - - \r.wb.addr_RNO_3[9]\ : OR2A - port map(A => N_711, B => N_388, Y => N_589); - - \r.walk_op_RNIO4TR1\ : NOR2 - port map(A => walk_op, B => \N_207\, Y => N_367); - - \r.wb.data_RNO[1]\ : MX2 - port map(A => adata_1, B => adata_0_1, S => twowner_2(0), Y - => N_3142); - - \r.wb.data[15]\ : DFN1E0 - port map(D => N_644_0, CLK => lclk_c, E => N_215_0, Q => - data_1(15)); - - \r.req_RNO_1\ : OR2B - port map(A => rst, B => N_456_0, Y => N_649_0); - - \r.state_RNIULR8[4]\ : OR3A - port map(A => walk_op, B => \state[0]\, C => \state[4]\, Y - => N_2563_i_0_a4_m7_0_a2_1); - - \r.wb.data_RNO[28]\ : MX2 - port map(A => adata_28, B => adata_0_28, S => twowner_2(0), - Y => N_3144); - - \r.wb.addr_RNO_2[3]\ : OR2A - port map(A => ctx_1, B => N_204, Y => N_352); - - \r.wb.addr_RNO_1[14]\ : MX2 - port map(A => aaddr_12, B => aaddr_0_12, S => twowner_2(0), - Y => N_716); - - \r.state_RNO_1[0]\ : OAI1 - port map(A => N_364, B => N_367, C => \state[1]\, Y => - N_643); - - \r.state_RNIMR2IG2[1]\ : NOR3 - port map(A => N_365, B => addr_1_1_0_a2_3_5_m2_0, C => - \state_i_RNIJP3JC1[5]\, Y => N_369); - - \r.walk_op_RNO_0\ : OR3A - port map(A => walk_op_2_0_0_a2_1_0, B => hrdata_0_1, C => - \walk_op_2_0_0_o2_0\, Y => N_648); - - \r.wb.addr_RNO_10[6]\ : MX2C - port map(A => data_16, B => data_0(16), S => twowner(0), Y - => N_609); - - \r.wb.data_RNO[19]\ : MX2 - port map(A => adata_19, B => adata_0_19, S => twowner(0), Y - => N_653); - - \r.wb.addr_RNO_2[11]\ : MX2 - port map(A => aaddr_9, B => aaddr_0_9, S => twowner(0), Y - => N_713); - - \r.wb.addr_RNO_1[30]\ : MX2 - port map(A => aaddr_28, B => aaddr_0_28, S => twowner_2(0), - Y => N_729); - - \r.wb.addr_RNO_0[26]\ : OA1A - port map(A => hrdata_0_22, B => N_366_0, C => N_622, Y => - \addr_1_i_i_0[26]\); - - \r.wb.addr[19]\ : DFN1E1 - port map(D => N_180, CLK => lclk_c, E => N_456_0, Q => - address(19)); - - \r.wb.addr[31]\ : DFN1E1 - port map(D => N_47, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(31)); - - \r.wb.addr_RNO_0[19]\ : OA1A - port map(A => N_721, B => N_388_0, C => N_331, Y => - \addr_1_i_i_0[19]\); - - \r.wb.addr_RNO_2[26]\ : MX2 - port map(A => aaddr_24, B => aaddr_0_24, S => twowner(0), Y - => N_3148); - - \r.wb.addr_RNO_0[20]\ : OA1A - port map(A => N_722, B => N_388_0, C => N_334, Y => - \addr_1_i_i_0[20]\); - - \r.wb.data[27]\ : DFN1E0 - port map(D => N_588, CLK => lclk_c, E => N_215, Q => - data_1(27)); - - \r.wb.addr_RNO_5[5]\ : MX2C - port map(A => N_619_0, B => N_590, S => twowner_0(0), Y => - N_230); - - \r.state_RNO[3]\ : NOR3A - port map(A => rst, B => N_637, C => \state_ns_i_0_0_0[2]\, - Y => \state_nss[2]\); - - \r.wb.read_RNO_0\ : OR3C - port map(A => rst, B => \read\, C => N_215_0, Y => N_651); - - \r.wb.addr_RNO_2[2]\ : OR2A - port map(A => ctx_0_d0, B => N_204, Y => N_356); - - \r.wb.addr_RNO_4[7]\ : MX2C - port map(A => N_660, B => N_618, S => twowner_0(0), Y => - N_232); - - \r.req_RNI7PUC\ : NOR2A - port map(A => ba, B => \req\, Y => - \fault_lvl_1_0_iv_0_a2_i_o2_0[0]\); - - \r.wb.addr_RNO_2[20]\ : OR2A - port map(A => hrdata_0_16, B => N_366, Y => N_334); - - \r.wb.addr_RNO[26]\ : AO1C - port map(A => N_204, B => ctxp(20), C => \addr_1_i_i_0[26]\, - Y => N_580); - - \r.wb.addr_RNO[23]\ : AO1C - port map(A => N_204, B => ctxp(17), C => \addr_1_i_i_0[23]\, - Y => N_23); - - \r.wb.addr_RNO[17]\ : AO1C - port map(A => N_204_0, B => ctxp(11), C => - \addr_1_i_i_0[17]\, Y => N_176); - - \r.wb.addr[11]\ : DFN1E1 - port map(D => N_164, CLK => lclk_c, E => N_456_0, Q => - address(11)); - - \r.wb.data_RNO[4]\ : MX2 - port map(A => adata_4, B => adata_0_4, S => twowner_0(0), Y - => N_101); - - \r.wb.addr_RNO_0[23]\ : OA1A - port map(A => N_725, B => N_388_0, C => N_596, Y => - \addr_1_i_i_0[23]\); - - \r.wb.data_RNO[25]\ : MX2 - port map(A => adata_25, B => adata_0_25, S => twowner_1(0), - Y => N_655); - - \r.wb.addr_RNO[21]\ : AO1C - port map(A => N_204_0, B => ctxp(15), C => - \addr_1_i_i_0[21]\, Y => N_15); - - \p0.fault_mexc_1_0_a2_0_o2\ : NOR2 - port map(A => \state[4]\, B => walk_op, Y => N_226); - - \r.state_RNIUDO8[1]\ : OR2A - port map(A => \state[1]\, B => N_210, Y => - addr_1_1_0_a2_3_5_m2_0); - - \r.wb.addr_RNO[9]\ : AO1C - port map(A => N_204, B => N_56_1, C => \addr_1_i_i_0_0[9]\, - Y => N_13); - - \r.wb.addr_RNO_5[7]\ : MX2 - port map(A => data_17, B => data_0(17), S => twowner_1(0), - Y => N_647); - - \r.wb.addr_RNO_2[30]\ : OR2A - port map(A => hrdata_0_26, B => N_366, Y => N_605); - - \r.wb.addr_RNO_1[7]\ : AOI1B - port map(A => \addr_1_i_i_o2_0[7]\, B => N_361, C => - \addr_1_i_i_0[7]\, Y => \addr_1_i_i_1[7]\); - - \r.wb.addr[29]\ : DFN1E1 - port map(D => N_39, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(29)); - - \r.wb.addr_RNO_1[17]\ : MX2 - port map(A => aaddr_15, B => aaddr_0_15, S => twowner_2(0), - Y => N_719); - - \r.wb.addr_RNO_2[23]\ : OR2A - port map(A => N_264_0, B => N_366, Y => N_596); - - \r.wb.addr[9]\ : DFN1E1 - port map(D => N_13, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(9)); - - \r.wb.addr[13]\ : DFN1E1 - port map(D => N_168, CLK => lclk_c, E => N_456_0, Q => - address(13)); - - \r.wb.addr_RNO[7]\ : AO1B - port map(A => N_210, B => N_205, C => \addr_1_i_i_1[7]\, Y - => N_189); - - \r.wb.data[29]\ : DFN1E0 - port map(D => N_3145, CLK => lclk_c, E => N_215, Q => - data_1(29)); - - \r.wb.addr_RNO_2[12]\ : OR2A - port map(A => hrdata_0_8, B => N_366, Y => N_310); - - \r.wb.addr_RNO_0[2]\ : AOI1B - port map(A => N_369, B => N_626, C => N_355, Y => - \addr_1_1_0_0[2]\); - - \r.wb.addr_RNO_4[3]\ : OR2A - port map(A => N_705, B => N_388, Y => N_351); - - \r.wb.addr_RNO[14]\ : AO1C - port map(A => N_204_0, B => ctxp(8), C => - \addr_1_i_i_0[14]\, Y => N_170); - - \r.state_RNO[2]\ : AOI1B - port map(A => N_640, B => N_639, C => rst, Y => - \state_nss[3]\); - - \r.req_RNIL0FNH\ : NOR2A - port map(A => hrdata_0_0, B => \N_207\, Y => - fault_trans_1_i_0_0_0); - - \r.state_i_RNI1JSQC1_0[5]\ : AO1 - port map(A => N_2485, B => N_2484, C => \state_i[5]\, Y => - N_215_0); - - \r.wb.data_RNO[29]\ : MX2 - port map(A => adata_29, B => adata_0_29, S => twowner_2(0), - Y => N_3145); - - \r.wb.addr_RNO_0[29]\ : OA1A - port map(A => N_728, B => N_388_0, C => N_602, Y => - \addr_1_i_i_0[29]\); - - \r.state[1]\ : DFN1 - port map(D => \state_nss[4]\, CLK => lclk_c, Q => - \state[1]\); - - \r.state_RNO_0[3]\ : NOR2A - port map(A => N_206, B => \state[3]\, Y => N_637); - - \r.wb.data[13]\ : DFN1E0 - port map(D => N_643_0, CLK => lclk_c, E => N_215_0, Q => - data_1(13)); - - \r.wb.addr_RNO_0[4]\ : AOI1B - port map(A => N_369, B => N_628, C => N_347, Y => - \addr_1_1_0_0[4]\); - - \r.wb.addr_RNO_4[2]\ : OR2A - port map(A => N_704, B => N_388, Y => N_355); - - \r.wb.addr[7]\ : DFN1E1 - port map(D => N_189, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(7)); - - \r.state[2]\ : DFN1 - port map(D => \state_nss[3]\, CLK => lclk_c, Q => - \state[2]\); - - \r.wb.addr_RNO_0[6]\ : NOR3 - port map(A => hrdata_0_2, B => N_231, C => N_370, Y => - N_338); - - \r.wb.addr_RNO_2[29]\ : OR2A - port map(A => N_78_0, B => N_366_0, Y => N_602); - - \r.wb.addr[21]\ : DFN1E1 - port map(D => N_15, CLK => lclk_c, E => N_456_0, Q => - address(21)); - - \r.wb.addr_RNO_1[25]\ : OR2A - port map(A => N_737, B => N_388, Y => N_619); - - \r.state_RNO_0[0]\ : OR2B - port map(A => \state[0]\, B => \N_207\, Y => N_644); - - \r.state_i_RNO_1[5]\ : OR3B - port map(A => N_2484, B => N_2485, C => \state_i[5]\, Y => - \state_ns_0_0_0_a2_0[0]\); - - \r.wb.data_RNO[30]\ : MX2 - port map(A => adata_30, B => adata_0_30, S => twowner_2(0), - Y => N_3146); - - \r.wb.addr_RNO[2]\ : OR3C - port map(A => \addr_1_1_0_0[2]\, B => N_353, C => N_356, Y - => \addr_1[2]\); - - \r.state_RNO[0]\ : AOI1B - port map(A => N_644, B => N_643, C => rst, Y => - \state_nss[5]\); - - \r.wb.data_RNO[7]\ : MX2 - port map(A => adata_7, B => adata_0_7, S => twowner_1(0), Y - => N_668); - - \r.wb.addr_RNO_1[24]\ : MX2 - port map(A => aaddr_22, B => aaddr_0_22, S => twowner(0), Y - => N_726); - - GND_i : GND - port map(Y => \GND\); - - \r.req_RNIL0FNH_0\ : NOR2 - port map(A => \N_207\, B => hrdata_0_0, Y => - inv_1_0_a2_0_a2_0); - - \r.wb.addr_RNO_1[16]\ : OR2A - port map(A => N_718, B => N_388, Y => N_324); - - \r.wb.addr[23]\ : DFN1E1 - port map(D => N_23, CLK => lclk_c, E => N_456_0, Q => - address(23)); - - \r.wb.addr_RNO_3[2]\ : MX2 - port map(A => data_12, B => data_0(12), S => twowner(0), Y - => N_626); - - \p0.fault_mexc_1_0_a2_0_a2\ : NOR2 - port map(A => \N_207\, B => fault_mexc_1_0_a2_0_a2_0, Y => - fault_mexc); - - \r.state_RNI673HG2[0]\ : OR2A - port map(A => N_365, B => N_215_0, Y => N_388_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.wb.addr_RNO_0[18]\ : OA1A - port map(A => hrdata_0_14, B => N_366_0, C => N_330, Y => - \addr_1_i_i_0[18]\); - - \r.state_RNIP074T3_0[0]\ : OR3C - port map(A => N_206, B => N_365, C => N_215_0, Y => - \state_RNIP074T3_0[0]\); - - \r.wb.data[7]\ : DFN1E0 - port map(D => N_668, CLK => lclk_c, E => N_215, Q => data_7); - - \r.wb.addr_RNO_1[3]\ : OR2A - port map(A => N_228, B => N_370, Y => N_349); - - \r.wb.addr[5]\ : DFN1E1 - port map(D => \addr_1[5]\, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(5)); - - \r.wb.data[24]\ : DFN1E0 - port map(D => N_646_0, CLK => lclk_c, E => N_215, Q => - data_1(24)); - - \r.wb.addr_RNO[4]\ : OR3C - port map(A => \addr_1_1_0_0[4]\, B => N_345, C => N_348, Y - => \addr_1[4]\); - - \r.wb.addr_RNO_2[7]\ : OR2 - port map(A => N_366, B => N_232, Y => N_362); - - \r.wb.addr_RNO_1[10]\ : MX2 - port map(A => aaddr_8, B => aaddr_0_8, S => twowner(0), Y - => N_712); - - \r.state_RNI3M7021[4]\ : NOR3 - port map(A => N_386, B => \state[4]\, C => \state[0]\, Y - => N_220); - - \r.wb.addr_RNO_0[8]\ : OR2 - port map(A => ctxp(2), B => ctx_6, Y => N_53_1); - - \r.wb.data_RNO[16]\ : MX2 - port map(A => adata_16, B => adata_0_16, S => twowner_0(0), - Y => N_624); - - \r.walk_op\ : DFN1 - port map(D => walk_op_RNO, CLK => lclk_c, Q => walk_op); - - \r.wb.data_RNO[10]\ : MX2 - port map(A => adata_10, B => adata_0_10, S => twowner(0), Y - => N_623); - - \r.state_RNI3CNU1_0[3]\ : NOR2A - port map(A => N_210, B => \N_207\, Y => lvl_i_1_0(1)); - - \r.wb.addr_RNO_1[13]\ : MX2 - port map(A => aaddr_11, B => aaddr_0_11, S => twowner_1(0), - Y => N_715); - - \r.wb.addr_RNO[3]\ : OR3C - port map(A => \addr_1_1_0_0[3]\, B => N_349, C => N_352, Y - => \addr_1[3]\); - - \r.state_RNO_1[4]\ : NOR2A - port map(A => N_215_0, B => \state[4]\, Y => N_634); - - \r.wb.data_RNO[13]\ : MX2 - port map(A => adata_13, B => adata_0_13, S => twowner_2(0), - Y => N_643_0); - - \r.wb.data[18]\ : DFN1E0 - port map(D => N_697, CLK => lclk_c, E => N_215_0, Q => - data_1(18)); - - \r.wb.data_RNO[3]\ : MX2 - port map(A => adata_3, B => adata_0_3, S => twowner_0(0), Y - => N_100); - - \r.wb.addr_RNO_2[9]\ : AO1 - port map(A => \state[3]\, B => N_592_0, C => hrdata(5), Y - => \addr_1_i_i_0_tz[9]\); - - \r.wb.data[4]\ : DFN1E0 - port map(D => N_101, CLK => lclk_c, E => N_215, Q => data_4); - - \r.wb.addr_RNO_1[27]\ : OR2A - port map(A => N_3149, B => N_388, Y => N_625); - - \r.wb.addr_RNO_0[31]\ : OA1A - port map(A => hrdata_0_27, B => N_366_0, C => N_610, Y => - \addr_1_i_i_0[31]\); - - \r.wb.addr_RNO_0[11]\ : OA1A - port map(A => hrdata_0_7, B => N_366_0, C => N_309, Y => - \addr_1_i_i_0[11]\); - - \r.req_RNO_0\ : NOR2B - port map(A => \req\, B => rst, Y => req_2_0_0_a2_0_0); - - \r.wb.addr_RNO_0[28]\ : OA1A - port map(A => N_727, B => N_388_0, C => N_627, Y => - \addr_1_i_i_0[28]\); - - \r.state_RNIH34P31[4]\ : OR2 - port map(A => N_220, B => \N_207\, Y => \finish\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.wb.addr_RNO_5[9]\ : MX2 - port map(A => aaddr_7, B => aaddr_0_7, S => twowner(0), Y - => N_711); - - \r.wb.addr_RNO_1[19]\ : MX2 - port map(A => aaddr_17, B => aaddr_0_17, S => twowner(0), Y - => N_721); - - \r.state_RNO_1[2]\ : OAI1 - port map(A => N_364, B => N_367, C => \state[3]\, Y => - N_639); - - \r.wb.data_RNO[2]\ : MX2 - port map(A => adata_2, B => adata_0_2, S => twowner_2(0), Y - => N_99); - - \r.wb.addr_RNO[10]\ : AO1C - port map(A => N_204, B => ctxp(4), C => \addr_1_i_i_0[10]\, - Y => N_159); - - \r.wb.addr_RNO_2[28]\ : OR2A - port map(A => hrdata_0_24, B => N_366, Y => N_627); - - \r.wb.data_RNO[12]\ : MX2 - port map(A => adata_12, B => adata_0_12, S => twowner_1(0), - Y => N_642_0); - - \r.wb.addr_RNO_3[8]\ : OR2A - port map(A => N_710, B => N_388_0, Y => N_586); - - \r.wb.data[21]\ : DFN1E0 - port map(D => N_625_0, CLK => lclk_c, E => N_215, Q => - data_1(21)); - - \r.wb.addr_RNO_1[5]\ : OR2A - port map(A => N_230, B => N_370, Y => N_341); - - \r.wb.data_RNO[26]\ : MX2 - port map(A => adata_26, B => adata_0_26, S => twowner_0(0), - Y => N_610_0); - - \r.wb.data[20]\ : DFN1E0 - port map(D => N_670, CLK => lclk_c, E => N_215, Q => - data_1(20)); - - \r.wb.addr_RNO_2[5]\ : OR2A - port map(A => ctx_3, B => N_204, Y => N_344); - - \r.wb.data[16]\ : DFN1E0 - port map(D => N_624, CLK => lclk_c, E => N_215_0, Q => - data_1(16)); - - \r.wb.addr[14]\ : DFN1E1 - port map(D => N_170, CLK => lclk_c, E => N_456_0, Q => - address(14)); - - \r.wb.addr_RNO_4[4]\ : OR2A - port map(A => N_706, B => N_388, Y => N_347); - - \r.wb.addr[16]\ : DFN1E1 - port map(D => N_174, CLK => lclk_c, E => N_456_0, Q => - address(16)); - - \r.wb.addr_RNO_1[31]\ : OR2A - port map(A => N_730, B => N_388, Y => N_610); - - \r.wb.data_RNO[20]\ : MX2 - port map(A => adata_20, B => adata_0_20, S => twowner(0), Y - => N_670); - - \r.wb.addr_RNO_1[26]\ : OR2A - port map(A => N_3148, B => N_388, Y => N_622); - - \r.wb.data_RNO[31]\ : MX2 - port map(A => adata_31, B => adata_0_31, S => twowner_1(0), - Y => N_702); - - \r.wb.data[9]\ : DFN1E0 - port map(D => N_622_0, CLK => lclk_c, E => N_215, Q => - data_9); - - \r.wb.data_RNO[23]\ : MX2 - port map(A => adata_23, B => adata_0_23, S => twowner_1(0), - Y => N_645_0); - - \r.wb.addr_RNO[27]\ : AO1C - port map(A => N_204, B => ctxp(21), C => \addr_1_i_i_0[27]\, - Y => N_581); - - \r.wb.addr_RNO_0[21]\ : OA1A - port map(A => hrdata_0_17, B => N_366_0, C => N_592, Y => - \addr_1_i_i_0[21]\); - - \r.wb.addr_RNO_8[2]\ : MX2C - port map(A => data_0(24), B => data_0(18), S => \state[2]\, - Y => N_616); - - \r.wb.addr_RNO_1[20]\ : MX2 - port map(A => aaddr_18, B => aaddr_0_18, S => twowner(0), Y - => N_722); - - \r.wb.addr_RNO_0[12]\ : OA1A - port map(A => N_714, B => N_388_0, C => N_310, Y => - \addr_1_i_i_0[12]\); - - \r.wb.data[25]\ : DFN1E0 - port map(D => N_655, CLK => lclk_c, E => N_215, Q => - data_1(25)); - - \r.wb.addr[15]\ : DFN1E1 - port map(D => N_172, CLK => lclk_c, E => N_456_0, Q => - address(15)); - - \r.state_RNIODA9G2[0]\ : OR2A - port map(A => N_206, B => N_365, Y => N_366); - - \r.wb.addr[12]\ : DFN1E1 - port map(D => N_166, CLK => lclk_c, E => N_456_0, Q => - address(12)); - - \r.wb.data[8]\ : DFN1E0 - port map(D => N_621, CLK => lclk_c, E => N_215, Q => data_8); - - \r.wb.addr_RNO_2[21]\ : MX2 - port map(A => aaddr_19, B => aaddr_0_19, S => twowner_2(0), - Y => N_723); - - \r.wb.addr_RNO[12]\ : AO1C - port map(A => N_204_0, B => ctxp(6), C => - \addr_1_i_i_0[12]\, Y => N_166); - - \r.wb.addr_RNO_0[3]\ : AOI1B - port map(A => N_369, B => N_627_0, C => N_351, Y => - \addr_1_1_0_0[3]\); - - \r.state_i_RNIP074T3_0[5]\ : OR2B - port map(A => N_366, B => N_215_0, Y => N_204_0); - - \r.wb.addr_RNO_6[6]\ : MX2C - port map(A => data_0(28), B => data_0(22), S => \state[2]\, - Y => N_649); - - \r.wb.addr_RNO_4[5]\ : OR2A - port map(A => N_707, B => N_388, Y => N_343); - - \r.wb.addr_RNO_3[4]\ : MX2 - port map(A => data_14, B => data_0(14), S => twowner_1(0), - Y => N_628); - - \r.wb.addr_RNO_2[15]\ : MX2 - port map(A => aaddr_13, B => aaddr_0_13, S => twowner_2(0), - Y => N_717); - - \r.wb.addr_RNO[31]\ : AO1C - port map(A => N_204, B => ctxp(25), C => \addr_1_i_i_0[31]\, - Y => N_47); - - \r.state_i_RNIV9NDT3[5]\ : OA1A - port map(A => N_215_0, B => \addr_1_i_i_a2_2_0[7]\, C => - N_366_0, Y => \addr_1_i_i_o2_0[7]\); - - \r.wb.addr_RNO[18]\ : AO1C - port map(A => N_204_0, B => ctxp(12), C => - \addr_1_i_i_0[18]\, Y => N_178); - - \r.state_RNO[4]\ : NOR3A - port map(A => rst, B => N_633, C => N_634, Y => - \state_nss[1]\); - - \r.wb.addr_RNO_1[23]\ : MX2 - port map(A => aaddr_21, B => aaddr_0_21, S => twowner(0), Y - => N_725); - - \r.wb.addr_RNO[24]\ : AO1C - port map(A => N_204_0, B => ctxp(18), C => - \addr_1_i_i_0[24]\, Y => N_35); - - \r.wb.addr_RNO_2[14]\ : OR2A - port map(A => hrdata_0_10, B => N_366, Y => N_316); - - \r.wb.addr[24]\ : DFN1E1 - port map(D => N_35, CLK => lclk_c, E => N_456_0, Q => - address(24)); - - \r.wb.data[6]\ : DFN1E0 - port map(D => N_3143, CLK => lclk_c, E => N_215, Q => - data_6); - - \r.wb.addr[26]\ : DFN1E1 - port map(D => N_580, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(26)); - - \r.wb.addr_RNO_8[5]\ : MX2C - port map(A => data_27, B => data_21, S => \state[2]\, Y => - N_590); - - \r.state_RNI5D9G11[0]\ : OR2B - port map(A => fault_trans_1_i_0_0_0, B => N_617, Y => - fault_trans_i_2); - - \r.wb.addr_RNO_5[2]\ : MX2C - port map(A => N_673, B => N_616, S => twowner(0), Y => - N_227); - - \r.wb.addr_RNO_2[31]\ : MX2 - port map(A => aaddr_29, B => aaddr_0_29, S => twowner(0), Y - => N_730); - - \r.wb.data_RNO[22]\ : MX2 - port map(A => adata_22, B => adata_0_22, S => twowner_1(0), - Y => N_654); - - \r.wb.addr_RNO_8[3]\ : MX2C - port map(A => data_25, B => data_19, S => \state[2]\, Y => - N_589_0); - - \r.wb.data_RNO[11]\ : MX2 - port map(A => adata_11, B => adata_0_11, S => twowner_1(0), - Y => N_652_0); - - \r.state_RNI673HG2_0[0]\ : OR2A - port map(A => N_365, B => N_215_0, Y => N_388); - - \r.wb.addr_RNO[15]\ : AO1C - port map(A => N_204_0, B => ctxp(9), C => - \addr_1_i_i_0[15]\, Y => N_172); - - \r.wb.addr_RNO_1[18]\ : OR2A - port map(A => N_720, B => N_388, Y => N_330); - - \r.wb.addr[25]\ : DFN1E1 - port map(D => N_579, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(25)); - - \r.state_RNIVBNU1[1]\ : OA1B - port map(A => \state[0]\, B => \state[1]\, C => \N_207\, Y - => N_82); - - \r.wb.addr_RNO_0[7]\ : AO1B - port map(A => \addr_1_i_i_o2_0[7]\, B => N_361, C => N_362, - Y => N_205); - - \r.state_RNI5K6M31[0]\ : OR3B - port map(A => walk_op, B => N_364, C => \state[0]\, Y => - N_365); - - \r.wb.addr_RNO_1[29]\ : MX2 - port map(A => aaddr_27, B => aaddr_0_27, S => twowner_2(0), - Y => N_728); - - \r.wb.addr[22]\ : DFN1E1 - port map(D => N_17, CLK => lclk_c, E => N_456_0, Q => - address(22)); - - \r.wb.addr_RNO_0[22]\ : OA1A - port map(A => hrdata_0_18, B => N_366_0, C => N_595, Y => - \addr_1_i_i_0[22]\); - - \r.wb.addr_RNO[19]\ : AO1C - port map(A => N_204, B => ctxp(13), C => \addr_1_i_i_0[19]\, - Y => N_180); - - \p0.fault_mexc_1_0_a2_0_a2_RNO\ : OR2A - port map(A => mexc, B => N_226, Y => - fault_mexc_1_0_a2_0_a2_0); - - \r.state_RNIDC5FG2[3]\ : OR2A - port map(A => N_210, B => N_366, Y => N_370); - - \r.wb.data_RNO[9]\ : MX2 - port map(A => adata_9, B => adata_0_9, S => twowner_0(0), Y - => N_622_0); - - \r.wb.addr_RNO_2[22]\ : MX2 - port map(A => aaddr_20, B => aaddr_0_20, S => twowner_2(0), - Y => N_724); - - \r.wb.addr[17]\ : DFN1E1 - port map(D => N_176, CLK => lclk_c, E => N_456_0, Q => - address(17)); - - \r.wb.data[12]\ : DFN1E0 - port map(D => N_642_0, CLK => lclk_c, E => N_215_0, Q => - data_1(12)); - - \r.wb.addr_RNO_2[17]\ : OR2A - port map(A => hrdata_0_13, B => N_366, Y => N_325); - - \r.wb.data[23]\ : DFN1E0 - port map(D => N_645_0, CLK => lclk_c, E => N_215, Q => - data_1(23)); - - \r.wb.addr_RNO_3[3]\ : MX2 - port map(A => data_13, B => data_0(13), S => twowner_1(0), - Y => N_627_0); - - \r.wb.addr_RNO_2[4]\ : OR2A - port map(A => ctx_2, B => N_204, Y => N_348); - - \r.wb.addr_RNO_1[11]\ : OR2A - port map(A => N_713, B => N_388, Y => N_309); - - \r.wb.addr_RNO[6]\ : NOR3 - port map(A => N_338, B => \addr_1_i_0_0[6]\, C => N_340, Y - => N_479); - - \r.state_RNO_1[3]\ : OA1B - port map(A => N_386, B => \state[3]\, C => \N_207\, Y => - \state_ns_i_0_0_0[2]\); - - \r.req_RNIEDSO1\ : OR3B - port map(A => \fault_lvl_1_0_iv_0_a2_i_o2_0[0]\, B => - iosn_0(93), C => bo_5842_d_0, Y => \N_207\); - - \r.state[4]\ : DFN1 - port map(D => \state_nss[1]\, CLK => lclk_c, Q => - \state[4]\); - - \r.wb.data_RNO[21]\ : MX2 - port map(A => adata_21, B => adata_0_21, S => twowner_0(0), - Y => N_625_0); - - \r.wb.addr_RNO_7[5]\ : MX2C - port map(A => data_0(27), B => data_0(21), S => \state[2]\, - Y => N_619_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.state_RNI2CNU1[1]\ : OA1B - port map(A => \state[1]\, B => \state[3]\, C => \N_207\, Y - => lvl_i_1(0)); - - \r.req_RNIJD8G31\ : NOR3 - port map(A => hrdata_0_1, B => \walk_op_2_0_0_o2_0\, C => - \N_207\, Y => N_364); - - \r.wb.addr_RNO_7[7]\ : MX2 - port map(A => data_0(29), B => data_0(23), S => \state[2]\, - Y => N_660); - - \r.wb.read_RNO\ : AO1C - port map(A => N_206, B => rst, C => N_651, Y => read_RNO); - - \r.wb.addr[27]\ : DFN1E1 - port map(D => N_581, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(27)); - - \r.walk_op_RNO\ : OR3C - port map(A => N_648, B => N_645, C => N_646, Y => - walk_op_RNO); - - \r.wb.addr_RNO_5[3]\ : MX2C - port map(A => N_591, B => N_589_0, S => twowner_0(0), Y => - N_228); - - \r.wb.addr_RNO[8]\ : AO1C - port map(A => N_204_0, B => N_53_1, C => - \addr_1_i_i_0_0[8]\, Y => N_11); - - \r.wb.data[17]\ : DFN1E0 - port map(D => N_669, CLK => lclk_c, E => N_215_0, Q => - data_1(17)); - - \r.wb.data[0]\ : DFN1E0 - port map(D => N_731, CLK => lclk_c, E => N_215_0, Q => - data_0_d0); - - \r.wb.addr_RNO_3[6]\ : MX2C - port map(A => N_649, B => N_698, S => twowner(0), Y => - N_231); - - \r.state[0]\ : DFN1 - port map(D => \state_nss[5]\, CLK => lclk_c, Q => - \state[0]\); - - \r.state_RNILUQ5[3]\ : OR2 - port map(A => \state[3]\, B => \state[2]\, Y => N_210); - - \r.wb.addr_RNO_2[16]\ : MX2 - port map(A => aaddr_14, B => aaddr_0_14, S => twowner_2(0), - Y => N_718); - - \r.state_RNO_1[1]\ : OAI1 - port map(A => N_364, B => N_367, C => \state[2]\, Y => - N_641); - - \r.wb.addr_RNO[20]\ : AO1C - port map(A => N_204, B => ctxp(14), C => \addr_1_i_i_0[20]\, - Y => N_182); - - \r.wb.addr_RNO_2[10]\ : OR2A - port map(A => hrdata(6), B => N_366, Y => N_652); - - \r.wb.addr_RNO_1[28]\ : MX2 - port map(A => aaddr_26, B => aaddr_0_26, S => twowner_2(0), - Y => N_727); - - \r.wb.addr[18]\ : DFN1E1 - port map(D => N_178, CLK => lclk_c, E => N_456_0, Q => - address(18)); - - \r.wb.addr_RNO_6[3]\ : MX2 - port map(A => aaddr_1, B => aaddr_0_1, S => twowner_1(0), Y - => N_705); - - \r.wb.addr_RNO_1[12]\ : MX2 - port map(A => aaddr_10, B => aaddr_0_10, S => twowner_1(0), - Y => N_714); - - \r.wb.addr_RNO_9[6]\ : MX2 - port map(A => aaddr_4, B => aaddr_0_4, S => twowner(0), Y - => N_708); - - \r.wb.data[28]\ : DFN1E0 - port map(D => N_3144, CLK => lclk_c, E => N_215, Q => - data_1(28)); - - \r.walk_op_RNIFNCQ11\ : OA1 - port map(A => hrdata_0_1, B => \walk_op_2_0_0_o2_0\, C => - walk_op, Y => N_386); - - \r.wb.data_RNO[14]\ : MX2 - port map(A => adata_14, B => adata_0_14, S => twowner_2(0), - Y => \adata_1[14]\); - - \r.wb.addr_RNO_0[15]\ : OA1A - port map(A => hrdata_0_11, B => N_366_0, C => N_321, Y => - \addr_1_i_i_0[15]\); - - \r.walk_op_RNO_3\ : NOR3B - port map(A => walk_op, B => rst, C => \state[0]\, Y => - walk_op_2_0_0_a2_1_0); - - \r.wb.addr_RNO_2[13]\ : OR2A - port map(A => hrdata_0_9, B => N_366, Y => N_313); - - \r.wb.data[1]\ : DFN1E0 - port map(D => N_3142, CLK => lclk_c, E => N_215_0, Q => - data_1_d0); - - \r.wb.data[19]\ : DFN1E0 - port map(D => N_653, CLK => lclk_c, E => N_215_0, Q => - data_1(19)); - - \r.state[3]\ : DFN1 - port map(D => \state_nss[2]\, CLK => lclk_c, Q => - \state[3]\); - - \r.wb.addr_RNO_6[7]\ : OR2A - port map(A => hrdata_0_3, B => N_366, Y => N_358); - - \r.wb.addr_RNO_0[9]\ : OR2 - port map(A => ctxp(3), B => ctx_7, Y => N_56_1); - - \r.wb.data_RNO[0]\ : MX2 - port map(A => adata_0_d0, B => adata_0_0, S => twowner_2(0), - Y => N_731); - - \r.wb.addr_RNO_4[6]\ : OR3 - port map(A => N_225, B => N_210, C => hrdata_0_2, Y => - \addr_1_i_0_a2_1[6]\); - - \r.wb.addr_RNO_0[14]\ : OA1A - port map(A => N_716, B => N_388_0, C => N_316, Y => - \addr_1_i_i_0[14]\); - - \r.wb.addr_RNO_4[8]\ : MX2 - port map(A => data_30, B => data_0(30), S => twowner_0(0), - Y => N_611); - - \r.wb.addr_RNO_2[6]\ : NOR3 - port map(A => ctx_0(4), B => ctxp(0), C => N_204, Y => - N_340); - - \r.wb.addr_RNO_8[6]\ : NOR2A - port map(A => \state[1]\, B => N_609, Y => N_225); - - \r.wb.addr_RNO[22]\ : AO1C - port map(A => N_204_0, B => ctxp(16), C => - \addr_1_i_i_0[22]\, Y => N_17); - - \r.state_i_RNO[5]\ : NOR3C - port map(A => N_630, B => \finish\, C => rst, Y => - \state_nss_i_0[0]\); - - \r.wb.addr_RNO_6[5]\ : MX2 - port map(A => aaddr_3, B => aaddr_0_3, S => twowner_1(0), Y - => N_707); - - \r.wb.data[31]\ : DFN1E0 - port map(D => N_702, CLK => lclk_c, E => N_215, Q => - data_1(31)); - - \r.wb.data[30]\ : DFN1E0 - port map(D => N_3146, CLK => lclk_c, E => N_215, Q => - data_1(30)); - - \r.state_RNI0CNU1[0]\ : OA1B - port map(A => \state[0]\, B => \state[2]\, C => \N_207\, Y - => N_80); - - \r.wb.addr_RNO[16]\ : AO1C - port map(A => N_204_0, B => ctxp(10), C => - \addr_1_i_i_0[16]\, Y => N_174); - - \r.wb.addr[28]\ : DFN1E1 - port map(D => N_582, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(28)); - - \r.state_i_RNI1JSQC1[5]\ : AO1 - port map(A => N_2485, B => N_2484, C => \state_i[5]\, Y => - N_215); - - \r.wb.addr_RNO_1[21]\ : OR2A - port map(A => N_723, B => N_388_0, Y => N_592); - - \r.wb.addr_RNO[28]\ : AO1C - port map(A => N_204_0, B => ctxp(22), C => - \addr_1_i_i_0[28]\, Y => N_582); - - \r.state_RNIGCQOF[0]\ : OR2 - port map(A => \state[0]\, B => hrdata_0_1, Y => N_617); - - \r.wb.addr_RNO_2[19]\ : OR2A - port map(A => hrdata_0_15, B => N_366, Y => N_331); - - \r.wb.addr_RNO[13]\ : AO1C - port map(A => N_204_0, B => ctxp(7), C => - \addr_1_i_i_0[13]\, Y => N_168); - - \r.walk_op_RNO_1\ : OR3C - port map(A => rst, B => walk_op, C => \N_207\, Y => N_645); - - \r.state_RNO_0[2]\ : OR2B - port map(A => \state[2]\, B => \N_207\, Y => N_640); - - \r.state_RNIULR8_0[4]\ : NOR3 - port map(A => \state[0]\, B => \state[4]\, C => walk_op, Y - => d_N_6_1); - - \r.wb.addr_RNO[11]\ : AO1C - port map(A => N_204, B => ctxp(5), C => \addr_1_i_i_0[11]\, - Y => N_164); - - \r.wb.data[26]\ : DFN1E0 - port map(D => N_610_0, CLK => lclk_c, E => N_215, Q => - data_1(26)); - - \r.wb.addr_RNO_1[4]\ : OR2A - port map(A => N_229, B => N_370, Y => N_345); - - \r.state_RNO_0[1]\ : OR2B - port map(A => \state[1]\, B => \N_207\, Y => N_642); - - \r.state_i_RNIJP3JC1[5]\ : AOI1 - port map(A => N_2488, B => N_2487, C => \state_i[5]\, Y => - \state_i_RNIJP3JC1[5]\); - - \r.wb.addr_RNO_7[6]\ : MX2C - port map(A => data_28, B => data_22, S => \state[2]\, Y => - N_698); - - \r.wb.addr_RNO_5[6]\ : NOR2 - port map(A => N_388, B => N_708, Y => N_339); - - \r.wb.data_RNO[17]\ : MX2 - port map(A => adata_17, B => adata_0_17, S => twowner_1(0), - Y => N_669); - - \r.state_i_RNIP074T3[5]\ : OR2B - port map(A => N_366, B => N_215_0, Y => N_204); - - \r.wb.addr_RNO_6[2]\ : MX2 - port map(A => aaddr_0_d0, B => aaddr_0_0, S => twowner(0), - Y => N_704); - - \r.wb.addr_RNO[25]\ : AO1C - port map(A => N_204_0, B => ctxp(19), C => - \addr_1_i_i_0[25]\, Y => N_579); - - \r.wb.addr[30]\ : DFN1E1 - port map(D => N_43, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(30)); - - \r.wb.data[2]\ : DFN1E0 - port map(D => N_99, CLK => lclk_c, E => N_215, Q => data_2); - - \r.wb.data[14]\ : DFN1E0 - port map(D => \adata_1[14]\, CLK => lclk_c, E => N_215_0, Q - => data_1(14)); - - \r.wb.addr_RNO_7[3]\ : MX2C - port map(A => data_0(25), B => data_0(19), S => \state[2]\, - Y => N_591); - - \r.wb.addr_RNO_0[25]\ : OA1A - port map(A => hrdata_0_21, B => N_366_0, C => N_619, Y => - \addr_1_i_i_0[25]\); - - \r.wb.addr[6]\ : DFN1E1 - port map(D => N_479, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(6)); - - \r.wb.data_RNO[24]\ : MX2 - port map(A => adata_24, B => adata_0_24, S => twowner_1(0), - Y => N_646_0); - - \r.wb.addr_RNO[29]\ : AO1C - port map(A => N_204_0, B => ctxp(23), C => - \addr_1_i_i_0[29]\, Y => N_39); - - \r.wb.addr_RNO_0[24]\ : OA1A - port map(A => N_726, B => N_388_0, C => N_599, Y => - \addr_1_i_i_0[24]\); - - \r.wb.addr_RNO_0[17]\ : OA1A - port map(A => N_719, B => N_388_0, C => N_325, Y => - \addr_1_i_i_0[17]\); - - \r.wb.addr[8]\ : DFN1E1 - port map(D => N_11, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(8)); - - \r.wb.addr_RNO_2[25]\ : MX2 - port map(A => aaddr_23, B => aaddr_0_23, S => twowner_2(0), - Y => N_737); - - \r.wb.addr_RNO_8[4]\ : MX2C - port map(A => data_26, B => data_20, S => \state[2]\, Y => - N_648_0); - - \r.wb.addr_RNO[5]\ : OR3C - port map(A => \addr_1_1_0_0[5]\, B => N_341, C => N_344, Y - => \addr_1[5]\); - - \r.wb.addr[4]\ : DFN1E1 - port map(D => \addr_1[4]\, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(4)); - - \r.wb.addr[10]\ : DFN1E1 - port map(D => N_159, CLK => lclk_c, E => N_456_0, Q => - address(10)); - - \r.wb.addr_RNO_2[24]\ : OR2A - port map(A => N_262_0, B => N_366, Y => N_599); - - \r.wb.addr_RNO_1[8]\ : OA1A - port map(A => \addr_1_i_i_0_tz[8]\, B => N_366_0, C => - N_586, Y => \addr_1_i_i_0_0[8]\); - - \r.wb.addr_RNO_0[5]\ : AOI1B - port map(A => N_369, B => N_629, C => N_343, Y => - \addr_1_1_0_0[5]\); - - \r.wb.addr_RNO_6[4]\ : MX2 - port map(A => aaddr_2, B => aaddr_0_2, S => twowner_1(0), Y - => N_706); - - \r.wb.addr_RNO_1[22]\ : OR2A - port map(A => N_724, B => N_388_0, Y => N_595); - - \r.wb.addr_RNO_1[6]\ : AO1D - port map(A => \addr_1_i_0_a2_1[6]\, B => N_366_0, C => - N_339, Y => \addr_1_i_0_0[6]\); - - \r.wb.addr_RNO_4[9]\ : MX2 - port map(A => data_31, B => data_0(31), S => twowner_0(0), - Y => N_592_0); - - \r.wb.addr_RNO_3[5]\ : MX2 - port map(A => data_15, B => data_0(15), S => twowner_1(0), - Y => N_629); - - \r.state_i_RNIS16DD1[5]\ : OR2A - port map(A => N_709, B => N_215_0, Y => N_361); - - \r.wb.addr_RNO_7[2]\ : MX2C - port map(A => data_24, B => data_18, S => \state[2]\, Y => - N_673); - - \r.state_RNIP074T3[0]\ : OR3C - port map(A => N_206, B => N_365, C => N_215_0, Y => N_456_0); - - \r.state_i_RNIJP3JC1_0[5]\ : AO1 - port map(A => N_2488, B => N_2487, C => \state_i[5]\, Y => - N_206); - - \r.wb.data_RNO[8]\ : MX2 - port map(A => adata_8, B => adata_0_8, S => twowner_0(0), Y - => N_621); - - \r.wb.data_RNO[18]\ : MX2 - port map(A => adata_18, B => adata_0_18, S => twowner(0), Y - => N_697); - - \r.state_i_RNO_0[5]\ : OR3B - port map(A => N_2487, B => N_2488, C => - \state_ns_0_0_0_a2_0[0]\, Y => N_630); - - \r.wb.addr[2]\ : DFN1E1 - port map(D => \addr_1[2]\, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(2)); - - \r.wb.addr_RNO_3[7]\ : AOI1B - port map(A => N_369, B => N_647, C => N_358, Y => - \addr_1_i_i_0[7]\); - - \r.state_RNO[1]\ : AOI1B - port map(A => N_642, B => N_641, C => rst, Y => - \state_nss[4]\); - - \r.state_i[5]\ : DFN1 - port map(D => \state_nss_i_0[0]\, CLK => lclk_c, Q => - \state_i[5]\); - - \r.wb.addr_RNO_1[9]\ : OA1A - port map(A => \addr_1_i_i_0_tz[9]\, B => N_366_0, C => - N_589, Y => \addr_1_i_i_0_0[9]\); - - \r.wb.data[3]\ : DFN1E0 - port map(D => N_100, CLK => lclk_c, E => N_215, Q => data_3); - - \r.wb.data_RNO[27]\ : MX2 - port map(A => adata_27, B => adata_0_27, S => twowner_0(0), - Y => N_588); - - \r.wb.addr_RNO_5[8]\ : MX2 - port map(A => aaddr_6, B => aaddr_0_6, S => twowner_1(0), Y - => N_710); - - \r.wb.addr_RNO_1[2]\ : OR2A - port map(A => N_227, B => N_370, Y => N_353); - - \r.wb.addr_RNO_0[16]\ : OA1A - port map(A => hrdata_0_12, B => N_366_0, C => N_324, Y => - \addr_1_i_i_0[16]\); - - \r.wb.addr[3]\ : DFN1E1 - port map(D => \addr_1[3]\, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(3)); - - \r.state_RNI3CNU1[3]\ : NOR2A - port map(A => N_210, B => \N_207\, Y => lvl_i_1(1)); - - \r.wb.addr_RNO_2[8]\ : AO1 - port map(A => \state[3]\, B => N_611, C => hrdata_0_4, Y - => \addr_1_i_i_0_tz[8]\); - - \r.wb.addr_RNO_8[7]\ : MX2 - port map(A => data_29, B => data_23, S => \state[2]\, Y => - N_618); - - \r.wb.addr_RNO_2[18]\ : MX2 - port map(A => aaddr_16, B => aaddr_0_16, S => twowner_2(0), - Y => N_720); - - \r.wb.addr_RNO_0[27]\ : OA1A - port map(A => hrdata_0_23, B => N_366_0, C => N_625, Y => - \addr_1_i_i_0[27]\); - - \r.wb.addr[20]\ : DFN1E1 - port map(D => N_182, CLK => lclk_c, E => N_456_0, Q => - address(20)); - - \r.wb.read\ : DFN1 - port map(D => read_RNO, CLK => lclk_c, Q => \read\); - - \p0.v.wb.addr_1_i_i_a2_2_0[7]\ : OR2 - port map(A => ctxp(1), B => ctx_0(5), Y => - \addr_1_i_i_a2_2_0[7]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_2 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - data_0_11 : in std_logic; - data_0_9 : in std_logic; - data_0_8 : in std_logic; - data_0_7 : in std_logic; - data_0_4 : in std_logic; - data_0_3 : in std_logic; - data_0_2 : in std_logic; - data_0_0 : in std_logic; - tlbcam_write_op_1_1 : in std_logic_vector(0 to 0); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_17 : in std_logic; - hrdata_10 : in std_logic; - hrdata_7 : in std_logic; - hrdata_6 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_0_d0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(0 to 0); - TYP_1 : in std_logic_vector(2 downto 0); - s2_entry : in std_logic_vector(2 to 2); - LVL_1 : in std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - data : in std_logic_vector(31 downto 12); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_1 : in std_logic_vector(2 to 2); - pteout_1 : in std_logic_vector(4 downto 2); - s2_entry_0 : in std_logic_vector(2 to 2); - pteout_0_17 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - tlbcam_write_op_1_0 : in std_logic_vector(0 to 0); - cam_hitaddr_21 : in std_logic_vector(0 to 0); - pteout_3 : in std_logic; - pteout_2 : in std_logic; - pteout_4 : in std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_0 : out std_logic; - un1_m0_2_15 : out std_logic; - un2_wb_acc_iv_2 : in std_logic_vector(14 to 14); - un2_wb_acc_iv_3 : in std_logic_vector(14 to 14); - un2_wb_acc_iv_5 : in std_logic_vector(18 downto 16); - data_1_3_i_a3_0_5_3 : in std_logic; - data_1_3_i_a3_0_5_0 : in std_logic; - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - ctx_4 : in std_logic; - ctx_3 : in std_logic; - ctx_0_d0 : in std_logic; - ctx_1 : in std_logic; - ctx_0_7 : in std_logic; - ctx_0_3 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_6 : in std_logic; - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - pteout_m_i_1 : in std_logic_vector(15 to 15); - un2_wb_acc_iv_0_12 : out std_logic; - un2_wb_acc_iv_1_8 : in std_logic; - un2_wb_acc_iv_1_11 : in std_logic; - un2_wb_acc_iv_1_10 : in std_logic; - un2_wb_acc_iv_1_9 : in std_logic; - un2_wb_acc_iv_1_7 : in std_logic; - un2_wb_acc_iv_1_5 : in std_logic; - un2_wb_acc_iv_1_4 : in std_logic; - un2_wb_acc_iv_1_1 : in std_logic; - un2_wb_acc_iv_1_0 : in std_logic; - un2_wb_acc_iv_1_3 : in std_logic; - pteout_m_i_11 : in std_logic; - pteout_m_i_10 : in std_logic; - pteout_m_i_9 : in std_logic; - pteout_m_i_7 : in std_logic; - pteout_m_i_6 : in std_logic; - pteout_m_i_5 : in std_logic; - pteout_m_i_4 : in std_logic; - pteout_m_i_1_d0 : in std_logic; - pteout_m_i_0_d0 : in std_logic; - pteout_m_i_3 : in std_logic; - un2_wb_acc_iv_4_11 : out std_logic; - un2_wb_acc_iv_4_10 : out std_logic; - un2_wb_acc_iv_4_6 : out std_logic; - un2_wb_acc_iv_4_4 : out std_logic; - un2_wb_acc_iv_4_1 : out std_logic; - un2_wb_acc_iv_4_0 : out std_logic; - un2_wb_acc_iv_4_3 : out std_logic; - data_1_3_i_a3_0_1_0 : in std_logic; - data_1_3_i_a3_0_1_3 : in std_logic; - data_1_3_i_a3_2 : in std_logic_vector(29 to 29); - data_1_3_i_a3_3 : in std_logic_vector(29 to 29); - pteout_m_i_0_1 : in std_logic_vector(26 to 26); - pteout_m_i_0_9 : in std_logic; - pteout_m_i_0_7 : in std_logic; - pteout_m_i_0_19 : in std_logic; - pteout_m_i_0_0_d0 : in std_logic; - pteout_m_i_0_3 : in std_logic; - pteout_m_i_0_16 : in std_logic; - pteout_m_i_0_15 : in std_logic; - pteout_m_i_0_17 : in std_logic; - pteout_m_i_0_18 : in std_logic; - pteout_m_i_0_0_14 : in std_logic; - pteout_m_i_0_0_18 : in std_logic; - pteout_m_i_0_0_13 : in std_logic; - data_1_3_i_a3_5_5 : in std_logic; - data_1_3_i_a3_5_3 : in std_logic; - data_1_3_i_a3_5_2 : in std_logic; - data_1_3_i_a3_5_1 : in std_logic; - data_1_3_i_a3_5_0 : in std_logic; - data_1_3_i_a3_1 : in std_logic_vector(29 downto 25); - data_1_3_i_a3_6_2 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_0 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_2701 : out std_logic; - N_1104 : out std_logic; - N_1496 : in std_logic; - N_1506 : in std_logic; - N_1117 : out std_logic; - N_1481 : in std_logic; - N_1120 : out std_logic; - N_1103 : out std_logic; - M_1 : in std_logic; - N_2483 : in std_logic; - trans_op : in std_logic; - un1_tlbcami_3 : out std_logic; - fault_pro67 : out std_logic; - read : in std_logic; - M_m : out std_logic; - N_1133 : out std_logic; - N_1479 : in std_logic; - s2_flush : in std_logic; - e : in std_logic; - rst : in std_logic; - un1_rst_i_0 : out std_logic; - N_1505 : in std_logic; - N_1482 : in std_logic; - N_1495 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_1513 : out std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - N_2720 : out std_logic; - N_2717 : out std_logic; - N_2714 : out std_logic; - N_1132 : out std_logic; - N_1131 : out std_logic; - N_1130 : out std_logic; - N_1129 : out std_logic; - N_1128 : out std_logic; - N_1127 : out std_logic; - N_1126 : out std_logic; - N_1125 : out std_logic; - N_1124 : out std_logic; - N_1123 : out std_logic; - N_1122 : out std_logic; - N_1121 : out std_logic; - N_1119 : out std_logic; - N_1118 : out std_logic; - N_1116 : out std_logic; - N_1115 : out std_logic; - N_1114 : out std_logic; - N_1113 : out std_logic; - N_1112 : out std_logic; - N_1111 : out std_logic; - N_1110 : out std_logic; - N_1109 : out std_logic; - N_1108 : out std_logic; - N_1107 : out std_logic; - N_1106 : out std_logic; - N_1102 : out std_logic; - N_1101 : out std_logic; - N_1100 : out std_logic; - s2_flush_0 : in std_logic; - G_80_0 : out std_logic; - N_1467 : in std_logic; - N_1480 : in std_logic; - N_1466 : in std_logic; - cam_hit_all_5_sqmuxa_0_a2_0 : in std_logic; - N_2551 : in std_logic; - N_1468 : in std_logic; - N_2703_i_0 : out std_logic; - N_2699_i_0 : out std_logic; - su : in std_logic; - un54_fault_pro_m_0 : in std_logic; - un54_fault_pro_m : out std_logic; - accexc_6 : in std_logic; - fault_pro : out std_logic; - fault_pri : out std_logic; - N_2709_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2702_i_0 : out std_logic; - tlbcamo_needsync : out std_logic; - WBNEEDSYNC_m_0 : in std_logic; - cam_hit_all_1 : out std_logic; - accexc_6_4 : out std_logic; - cam_hit_all_5_sqmuxa : in std_logic - ); - -end mmutlbcam_2_0_2; - -architecture DEF_ARCH of mmutlbcam_2_0_2 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hf_1_i, h_l3_1_i, hf_1_1_0, h_l3_1_4, h_l2_1, hf_1_0, - un3_hf, \data_1_3_i_a3_0[25]\, \pteout_m_i_0[21]\, - \data_1_3_i_a3_4[30]\, \data_1_3_i_a3_0[30]\, - \pteout[26]\, \data_1_3_i_a3_0[26]\, \pteout_m_i_0[22]\, - \data_1_3_i_a3_4[29]\, \pteout_m_i_0_0[25]\, - \data_1_3_i_a3_0[27]\, \pteout[23]\, - \data_1_3_i_a3_4[28]\, \pteout_m_i_0_0[24]\, - \data_1_3_i_a3_0_4[15]\, \pteout_m_i_0_0[11]\, - \data_1_3_i_a3_0_4[12]\, \pteout_m_i_0_0[8]\, - WBNEEDSYNC_m, \pteout_m_i_0[12]\, \pteout_m_i[27]\, - \pteout_m_i_0[9]\, \pteout_m_i_0[10]\, \pteout_m_i_0[13]\, - \un2_wb_acc_iv_4[14]\, \pteout_m_i_0[14]\, - \un2_wb_acc_iv_0[15]\, \pteout[15]\, - \un2_wb_acc_iv_4[16]\, \pteout_m_i_0[16]\, - \un2_wb_acc_iv_0[17]\, \pteout_m_i[17]\, - \un2_wb_acc_iv_4[18]\, \pteout_m_i_0[18]\, - \pteout_m_i_0[19]\, \pteout_m_i_0[20]\, WBNEEDSYNC_m_0_0, - hm_1_1, cam_hit_all_1_0, un18_hm, \LVL[0]\, \LVL[1]\, - \I3_RNIDS1Q[4]\, \I3_RNI7G1Q[3]\, h_l3_1_3, - \un1_tag0[61]\, h_l3_1_1, \I3_RNIL8291[2]\, - \I3_RNITM55[1]\, \I3_RNIOB0Q[0]\, h_l2_1_3, - \I2_RNIM82Q[1]\, \I2_RNIEC1Q[0]\, h_l2_1_1, h_l2_1_2, - \un1_tag0[66]\, \I2_RNIQ4UU[5]\, \un1_tag0[64]\, - \I2_RNI0O0Q[3]\, h_i13_NE_4, \I1_RNI7G0Q[1]\, - \I1_RNIIO091[0]\, h_i13_NE_1, h_i13_NE_3, \un1_tag0[75]\, - \I1_RNI040Q[6]\, h_i13_NE_2, \un1_tag0[72]\, - \I1_RNIF5VU[5]\, \un1_tag0[70]\, \I1_RNIH81Q[3]\, - h_c2_NE_5, h_c2_5_i, h_c2_4_i, h_c2_NE_3, h_c2_NE_4, - h_c2_1_i, h_c2_0_i, h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, - \un1_tag0[37]\, h_c2_3_i, h_i13_NE, hf_2_i, hf_3, - \un45_res[3]\, hf_4, \un1_tag0[43]\, \SU\, h_c2_NE, - \un2_wb_acc[18]\, \un2_wb_acc[17]\, \un2_wb_acc[16]\, - \un2_wb_acc[14]\, \cam_hit_all_1\, N_1490, - \ACC_RNIN7OINV1[1]\, \fault_pri\, \N_2709_i_0\, - \LVL_RNIT69H911[0]\, hm_4, hm_3, hm_1, N_1485, - \ACC_RNI6GVGC7[2]\, \pteout_0[4]\, N_1483, - \ACC_RNI2GVGC7[0]\, \pteout_0[2]\, \ACC_RNI638B8Q[1]\, - \ACC_RNI4GVGC7[1]\, \pteout_0[3]\, N_1488, N_15, - \un1_tag0[56]\, \un1_tag0[59]\, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[74]\, \un1_tag0[35]\, - \un1_tag0[36]\, \un1_tag0[38]\, \un1_tag0[39]\, - \un1_tag0[40]\, \un1_tag0[42]\, \pteout[0]\, \pteout[1]\, - \pteout[6]\, \pteout[7]\, \pteout[8]\, \pteout[9]\, - \pteout[10]\, \pteout[11]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[16]\, \pteout[18]\, \pteout[19]\, - \pteout[21]\, \pteout[22]\, \pteout[24]\, \pteout[25]\, - \pteout[27]\, \pteout[28]\, \pteout[29]\, \pteout[30]\, - \pteout[31]\, \pteout[20]\, \un1_tag0[62]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, - \un1_tag0[57]\, \un1_tag0[58]\, \N_1513\, \un1_tag0[60]\, - \un1_tag0[68]\, \un1_tag0[73]\, N_1, N_3, N_8, N_1501, - N_1508, N_1512, VALID_RNO_9, \un1_rst_i_0\, hf_1_1, - fault_pro63, \fault_pro\, \G_80_0\, N_686, \M_m\, - \un54_fault_pro_m\, \fault_pro67\, M_1_sqmuxa, - \un1_tlbcami_3\, M_5, M_2, \tlbcamo_needsync\, N_9, N_6, - N_7, N_5, \pteout[17]\, N_1509, N_1502, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - LVL_RNIT69H911(0) <= \LVL_RNIT69H911[0]\; - un1_tlbcami_3 <= \un1_tlbcami_3\; - fault_pro67 <= \fault_pro67\; - M_m <= \M_m\; - un1_rst_i_0 <= \un1_rst_i_0\; - N_1513 <= \N_1513\; - G_80_0 <= \G_80_0\; - un54_fault_pro_m <= \un54_fault_pro_m\; - fault_pro <= \fault_pro\; - fault_pri <= \fault_pri\; - N_2709_i_0 <= \N_2709_i_0\; - tlbcamo_needsync <= \tlbcamo_needsync\; - cam_hit_all_1 <= \cam_hit_all_1\; - - \r.btag.PPN_RNIPGU5[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry_0(2), Y => N_1111); - - \r.btag.PPN_RNIQT9G263[16]\ : NOR3C - port map(A => pteout_m_i_0_16, B => \pteout_m_i_0_0[24]\, C - => data_1_3_i_a3_1(28), Y => \data_1_3_i_a3_4[28]\); - - \r.btag.CTX_RNIOJNA[2]\ : XA1A - port map(A => ctx_1, B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.PPN_RNIMNQ5263[6]\ : NOR3C - port map(A => pteout_m_i_5, B => \pteout_m_i_0[14]\, C => - un2_wb_acc_iv_1_5, Y => \un2_wb_acc_iv_4[14]\); - - \r.btag.I2_RNIFTRT1[4]\ : XA1 - port map(A => I2_1(4), B => \un1_tag0[66]\, C => - \I2_RNIQ4UU[5]\, Y => h_l2_1_2); - - \r.btag.LVL_RNI92HNDD1[0]\ : MX2C - port map(A => N_1495, B => N_1501, S => N_1482, Y => N_1508); - - \r.btag.SU_RNIAE73B\ : NOR2A - port map(A => TYP_1(2), B => N_8, Y => N_9); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[8]\); - - \r.btag.I2_RNIQ4UU[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => - \I2_RNIQ4UU[5]\); - - \r.btag.PPN_RNIPK8C3H[1]\ : OR2A - port map(A => \pteout[9]\, B => cam_hit_all_5_sqmuxa, Y => - \pteout_m_i_0[9]\); - - \r.btag.PPN_RNIABPKDD1[9]\ : NOR2B - port map(A => \pteout_m_i[17]\, B => pteout_m_i_0_9, Y => - \un2_wb_acc_iv_0[17]\); - - \r.btag.ACC_RNIF7OINV1[0]\ : MX2C - port map(A => N_1479, B => N_1483, S => cam_hitaddr_21(0), - Y => N_1488); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \LVL[1]\); - - \r.btag.PPN_RNI146B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_0(2), Y => N_1124); - - \r.btag.CTX_RNI7S44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[63]\); - - \r.btag.ACC_RNIA38B8Q[2]\ : MX2C - port map(A => \ACC_RNI6GVGC7[2]\, B => N_1468, S => N_2551, - Y => N_1485); - - \r.btag.PPN_RNIIQSE3H[19]\ : OR2A - port map(A => \pteout[27]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i[27]\); - - \r.btag.ACC_RNIV7OINV1[2]\ : MX2 - port map(A => N_1481, B => N_1485, S => cam_hitaddr_21(0), - Y => N_1490); - - \r.btag.VALID_RNIDRLBF\ : MX2 - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[19]\); - - \r.btag.PPN_RNIC2SE3H[13]\ : OR2A - port map(A => \pteout[21]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[21]\); - - \r.btag.PPN_RNIRGU5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_0(2), Y => N_1112); - - \r.btag.CTX_RNIFNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_d0, Y => h_c2_1_i); - - \r.btag.PPN_RNIDSOSBN2[13]\ : NOR3C - port map(A => data_1_3_i_a3_1(25), B => - \data_1_3_i_a3_0[25]\, C => data_1_3_i_a3_5_0, Y => - data_1_3_i_a3_6_0); - - \r.btag.C_RNIT346\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_0(2), Y => N_1107); - - \r.btag.LVL_RNIFGKD3H[1]\ : MX2C - port map(A => \LVL[1]\, B => LVL_1(1), S => - cam_hit_all_5_sqmuxa, Y => N_1502); - - \r.btag.VALID_RNI5MVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.PPN_RNI0S5B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_1(2), Y => N_1131); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[67]\); - - \r.btag.PPN_RNIQK8C3H[2]\ : OR2A - port map(A => \pteout[10]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[10]\); - - \r.btag.LVL_RNIB81HCE2[1]\ : MX2 - port map(A => N_1506, B => N_1509, S => cam_hitaddr_21(0), - Y => \N_1513\); - - \r.btag.ACC_RNI6RRTKG3[2]\ : OR3B - port map(A => \fault_pri\, B => \fault_pro\, C => accexc_6, - Y => un1_m0_2_15); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(0), Y => N_15); - - \r.btag.PPN_RNISV09[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry(2), Y => N_1120); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNIUDAG263[17]\ : NOR3C - port map(A => pteout_m_i_0_17, B => \pteout_m_i_0_0[25]\, C - => data_1_3_i_a3_1(29), Y => \data_1_3_i_a3_4[29]\); - - \r.btag.M_RNIH446\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_0(2), Y => N_1106); - - \r.btag.LVL_RNIOM8VD[1]\ : NOR3 - port map(A => un3_hf, B => \LVL[1]\, C => h_l2_1, Y => - hf_2_i); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \SU\); - - \r.btag.PPN_RNI4M0QDD1[15]\ : OA1A - port map(A => \pteout[23]\, B => cam_hit_all_5_sqmuxa, C - => pteout_m_i_0_15, Y => \data_1_3_i_a3_0[27]\); - - \r.btag.CTX_RNISO98[6]\ : XA1A - port map(A => ctx_0_6, B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[36]\); - - \r.btag.M_RNIUO73932\ : NOR3C - port map(A => WBNEEDSYNC_m, B => \cam_hit_all_1\, C => - WBNEEDSYNC_m_0, Y => accexc_6_4); - - \r.btag.LVL_RNID2HNDD1[1]\ : MX2C - port map(A => N_1496, B => N_1502, S => N_1482, Y => N_1509); - - \r.btag.LVL_RNI11RPD[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.I3_RNIAB882[0]\ : NOR3C - port map(A => \I3_RNIL8291[2]\, B => \I3_RNITM55[1]\, C => - \I3_RNIOB0Q[0]\, Y => h_l3_1_1); - - \r.btag.PPN_RNICM1QDD1[19]\ : NOR2B - port map(A => \pteout_m_i[27]\, B => pteout_m_i_0_19, Y => - un2_wb_acc_iv_0_12); - - \r.btag.I3_RNITM55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNITM55[1]\); - - \r.btag.ET_RNIP4SA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_0(2), Y => N_1100); - - \r.btag.LVL_RNIM356[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_1(2), - Y => N_1132); - - \r.btag.ACC_RNIS65RFU3[1]\ : NOR2 - port map(A => \M_m\, B => \un54_fault_pro_m\, Y => N_686); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[10]\); - - \r.btag.I3_RNIOB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIOB0Q[0]\); - - \r.btag.PPN_RNIANQ5263[3]\ : NOR3C - port map(A => pteout_m_i_0_3, B => \pteout_m_i_0_0[11]\, C - => data_1_3_i_a3_0_1_3, Y => \data_1_3_i_a3_0_4[15]\); - - \r.btag.PPN_RNI7GG5O51[9]\ : MX2 - port map(A => \un2_wb_acc[17]\, B => data(21), S => - \N_1513\, Y => un1_m0_2_3); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNILGU5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_0(2), Y => N_1109); - - \r.btag.M_RNI7DNKDI\ : OR2A - port map(A => WBNEEDSYNC_m_0_0, B => cam_hit_all_5_sqmuxa, - Y => WBNEEDSYNC_m); - - \r.btag.LVL_RNIT69H911[0]\ : OR2B - port map(A => \N_1513\, B => N_1512, Y => - \LVL_RNIT69H911[0]\); - - \r.btag.PPN_RNITGT7BN2[6]\ : OR3C - port map(A => un2_wb_acc_iv_3(14), B => un2_wb_acc_iv_2(14), - C => \un2_wb_acc_iv_4[14]\, Y => \un2_wb_acc[14]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN_RNILSPSBN2[14]\ : NOR3C - port map(A => data_1_3_i_a3_1(26), B => - \data_1_3_i_a3_0[26]\, C => data_1_3_i_a3_5_1, Y => - data_1_3_i_a3_6_1); - - \r.btag.CTX_RNI88FL[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.ACC_RNI2GVGC7[0]\ : MX2 - port map(A => pteout_2, B => \pteout_0[2]\, S => - cam_hit_all_5_sqmuxa_0_a2_0, Y => \ACC_RNI2GVGC7[0]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_0_21, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[21]\); - - \r.btag.I3_RNIL8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIL8291[2]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => \un1_rst_i_0\, B => N_15, Y => VALID_RNO_9); - - \r.btag.LVL_RNIQ1S291[0]\ : MX2C - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.PPN_RNI5K6B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_0(2), Y => N_1126); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[66]\); - - \r.btag.PPN_RNIUJ5B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_1(2), Y => N_1130); - - \r.btag.I2_RNIM82Q[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => - \I2_RNIM82Q[1]\); - - \r.btag.I1_RNI040Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI040Q[6]\); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[68]\); - - \r.btag.PPN_RNI7S6B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_0(2), Y => N_1127); - - \r.btag.M_RNI2HK9A1\ : NOR2B - port map(A => \tlbcamo_needsync\, B => hm_1_1, Y => - WBNEEDSYNC_m_0_0); - - \r.btag.PPN_RNI245ELO3[16]\ : OR3C - port map(A => data_1_3_i_a3_5_3, B => \data_1_3_i_a3_4[28]\, - C => \LVL_RNIT69H911[0]\, Y => N_2702_i_0); - - \r.btag.PPN_RNILJ4B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_0(2), Y => N_1118); - - \r.btag.LVL_RNIT69H911_0[0]\ : NOR2 - port map(A => \N_1513\, B => N_1512, Y => \N_2709_i_0\); - - \r.btag.PPN_RNI6NQ5263[2]\ : NOR3C - port map(A => pteout_m_i_1_d0, B => \pteout_m_i_0[10]\, C - => un2_wb_acc_iv_1_1, Y => un2_wb_acc_iv_4_1); - - \r.btag.I2_RNIOJ0K1[2]\ : XA1 - port map(A => I2_1(2), B => \un1_tag0[64]\, C => - \I2_RNI0O0Q[3]\, Y => h_l2_1_1); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_0_22, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[22]\); - - \r.btag.PPN_RNI3C6B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_0(2), Y => N_1125); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout_0[2]\); - - \r.btag.PPN_RNIRK8C3H[3]\ : OR2A - port map(A => \pteout[11]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0_0[11]\); - - \r.btag.PPN_RNIENQ5263[4]\ : NOR3C - port map(A => pteout_m_i_3, B => \pteout_m_i_0[12]\, C => - un2_wb_acc_iv_1_3, Y => un2_wb_acc_iv_4_3); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[29]\); - - \r.btag.I3_RNI35BR4[3]\ : NOR3C - port map(A => \I3_RNIDS1Q[4]\, B => \I3_RNI7G1Q[3]\, C => - h_l3_1_3, Y => h_l3_1_4); - - \r.btag.PPN_RNIJGU5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_0(2), Y => N_1108); - - \r.btag.PPN_RNIAE1QDD1[18]\ : OA1A - port map(A => \pteout[26]\, B => cam_hit_all_5_sqmuxa, C - => pteout_m_i_0_1(26), Y => \data_1_3_i_a3_0[30]\); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data_0_2, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[64]\); - - \r.btag.M_RNI8FO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => - \tlbcamo_needsync\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_9, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout_0[4]\); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[25]\); - - \r.btag.ACC_RNI5N8O6V1[0]\ : OR3B - port map(A => \ACC_RNIN7OINV1[1]\, B => N_1490, C => N_1488, - Y => \fault_pro67\); - - \r.btag.ACC_RNIN7OINV1[1]\ : MX2 - port map(A => N_1480, B => \ACC_RNI638B8Q[1]\, S => - cam_hitaddr_21(0), Y => \ACC_RNIN7OINV1[1]\); - - \r.btag.PPN_RNI3HU5[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_0(2), Y => N_1116); - - \r.btag.I1_RNIIO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIIO091[0]\); - - \r.btag.ACC_RNI6GVGC7[2]\ : MX2C - port map(A => pteout_4, B => \pteout_0[4]\, S => - cam_hit_all_5_sqmuxa_0_a2_0, Y => \ACC_RNI6GVGC7[2]\); - - \r.btag.ACC_RNI4GVGC7[1]\ : MX2 - port map(A => pteout_3, B => \pteout_0[3]\, S => - cam_hit_all_5_sqmuxa_0_a2_0, Y => \ACC_RNI4GVGC7[1]\); - - \r.btag.SU_RNI6AQJ1_0\ : AO1C - port map(A => \SU\, B => h_c2_NE, C => \un1_tag0[43]\, Y - => un3_hf); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout_0[3]\); - - \r.btag.PPN_RNIQ35B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_1(2), Y => N_1128); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[60]\); - - \r.btag.I2_RNI0O0Q[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => - \I2_RNI0O0Q[3]\); - - \r.btag.LVL_RNIGAHQ8[0]\ : NOR3 - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.I1_RNI3C547[4]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.PPN_RNID6SE3H[14]\ : OR2A - port map(A => \pteout[22]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[22]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_0_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[1]\); - - \r.btag.PPN_RNIBURE3H[12]\ : OR2A - port map(A => \pteout[20]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[20]\); - - \r.btag.PPN_RNI2E0QDD1[14]\ : NOR2B - port map(A => \pteout_m_i_0[22]\, B => pteout_m_i_0_0_14, Y - => \data_1_3_i_a3_0[26]\); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[11]\); - - \r.btag.LVL_RNIB1RT911[0]\ : OR2 - port map(A => \LVL_RNIT69H911[0]\, B => data(26), Y => - N_2701); - - \r.btag.LVL_RNIDGKD3H[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_1(0), S => - cam_hit_all_5_sqmuxa, Y => N_1501); - - \r.btag.VALID_RNI08E5R\ : NOR2A - port map(A => s2_flush, B => hf_1_1, Y => un18_hm); - - \r.btag.PPN_RNIUMQ5263[0]\ : NOR3C - port map(A => pteout_m_i_0_0_d0, B => \pteout_m_i_0_0[8]\, - C => data_1_3_i_a3_0_1_0, Y => \data_1_3_i_a3_0_4[12]\); - - \r.btag.PPN_RNILRLSBN2[10]\ : OR2B - port map(A => un2_wb_acc_iv_5(18), B => - \un2_wb_acc_iv_4[18]\, Y => \un2_wb_acc[18]\); - - \r.btag.I1_RNIF5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIF5VU[5]\); - - \p0.hf_1\ : AND2 - port map(A => h_l3_1_i, B => hf_1_1_0, Y => hf_1_i); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[20]\); - - \r.btag.CTX_RNIFS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0_7, Y => h_c2_7_i); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[42]\); - - \r.btag.I1_RNIT42K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIH81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[65]\); - - \r.btag.PPN_RNI2NQ5263[1]\ : NOR3C - port map(A => pteout_m_i_0_d0, B => \pteout_m_i_0[9]\, C - => un2_wb_acc_iv_1_0, Y => un2_wb_acc_iv_4_0); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_0_27, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[27]\); - - \r.btag.LVL_RNIOF04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_1133); - - \r.btag.CTX_RNILNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_3, Y => h_c2_4_i); - - \r.btag.I3_RNIFO773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_1, Y - => h_l3_1_3); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(0), - Y => M_5); - - \r.btag.LVL_RNIQ9A842[0]\ : OR2 - port map(A => hm_1_1, B => un18_hm, Y => cam_hit_all_1_0); - - \r.btag.PPN_RNI8DQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_1117); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[56]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data_0_9, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[71]\); - - \p0.h_l3_1\ : NOR2A - port map(A => h_l3_1_4, B => h_l2_1, Y => h_l3_1_i); - - \r.btag.PPN_RNITSQSBN2[15]\ : NOR3C - port map(A => data_1_3_i_a3_1(27), B => - \data_1_3_i_a3_0[27]\, C => data_1_3_i_a3_5_2, Y => - data_1_3_i_a3_6_2); - - \r.btag.PPN_RNIRB5B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_0(2), Y => N_1121); - - \r.btag.PPN_RNIOK8C3H[0]\ : OR2A - port map(A => \pteout[8]\, B => cam_hit_all_5_sqmuxa, Y => - \pteout_m_i_0_0[8]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[9]\); - - \r.btag.I1_RNI7G0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNI7G0Q[1]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[70]\); - - \r.btag.CTX_RNI1S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_0, Y => h_c2_0_i); - - \r.btag.VALID_RNII0II8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[24]\); - - \r.btag.LVL_RNID5RT911[0]\ : OR2 - port map(A => \LVL_RNIT69H911[0]\, B => data(27), Y => - N_2717); - - \r.btag.CTX_RNI87FL[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN_RNIQNQ5263[7]\ : NOR3C - port map(A => pteout_m_i_6, B => pteout_m_i_0_7, C => - \un2_wb_acc_iv_0[15]\, Y => un2_wb_acc_iv_4_6); - - \r.btag.PPN_RNIMNG5O51[6]\ : MX2 - port map(A => \un2_wb_acc[14]\, B => data(18), S => - \N_1513\, Y => un1_m0_2_0); - - \r.btag.VALID_RNIFKCE1\ : OR2A - port map(A => \un1_tag0[43]\, B => h_c2_NE, Y => hm_4); - - \r.btag.SU_RNI6AQJ1\ : NOR3A - port map(A => \un1_tag0[43]\, B => \SU\, C => h_c2_NE, Y - => hf_4); - - \r.btag.PPN_RNIINQ5263[5]\ : NOR3C - port map(A => pteout_m_i_4, B => \pteout_m_i_0[13]\, C => - un2_wb_acc_iv_1_4, Y => un2_wb_acc_iv_4_4); - - \r.btag.PPN_RNI6E8QO51[10]\ : MX2 - port map(A => \un2_wb_acc[18]\, B => data(22), S => - \N_1513\, Y => un1_m0_2_4); - - \r.btag.I1_RNIH81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIH81Q[3]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.ACC_RNIGEH8VU3[1]\ : OA1C - port map(A => \ACC_RNIN7OINV1[1]\, B => fault_pro63, C => - read, Y => \M_m\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data_0_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[40]\); - - \r.btag.LVL_RNIV5DJ7J[0]\ : OR2 - port map(A => cam_hit_all_1_0, B => cam_hit_all_5_sqmuxa, Y - => \cam_hit_all_1\); - - \r.btag.PPN_RNIUNQ5263[8]\ : NOR3C - port map(A => pteout_m_i_7, B => \pteout_m_i_0[16]\, C => - un2_wb_acc_iv_1_7, Y => \un2_wb_acc_iv_4[16]\); - - \r.btag.I2_RNIS8483[0]\ : NOR3C - port map(A => \I2_RNIM82Q[1]\, B => \I2_RNIEC1Q[0]\, C => - h_l2_1_1, Y => h_l2_1_3); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[37]\); - - \r.btag.PPN_RNISB5B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_1(2), Y => N_1129); - - \r.btag.PPN_RNI6BPKDD1[7]\ : OA1A - port map(A => \pteout[15]\, B => cam_hit_all_5_sqmuxa, C - => pteout_m_i_1(15), Y => \un2_wb_acc_iv_0[15]\); - - \r.btag.PPN_RNI2T6G263[10]\ : NOR3C - port map(A => pteout_m_i_9, B => \pteout_m_i_0[18]\, C => - un2_wb_acc_iv_1_9, Y => \un2_wb_acc_iv_4[18]\); - - \p0.un1_rst\ : NOR2B - port map(A => rst, B => e, Y => \un1_rst_i_0\); - - \r.btag.PPN_RNITGU5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_0(2), Y => N_1113); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_0_15, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[15]\); - - \r.btag.ET_RNIRCSA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_0(2), Y => N_1101); - - \r.btag.PPN_RNIQRF5O51[8]\ : MX2 - port map(A => \un2_wb_acc[16]\, B => data(20), S => - \N_1513\, Y => un1_m0_2_2); - - \r.btag.I3_RNIDS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIDS1Q[4]\); - - \r.btag.ACC_RNIL7H5[0]\ : MX2 - port map(A => \pteout_0[2]\, B => pteout_1(2), S => - s2_entry_0(2), Y => N_1102); - - \r.btag.ACC_RNI238B8Q[0]\ : MX2C - port map(A => \ACC_RNI2GVGC7[0]\, B => N_1466, S => N_2551, - Y => N_1483); - - \p0.hf_1_RNO\ : NOR2A - port map(A => hf_1_0, B => un3_hf, Y => hf_1_1_0); - - \r.btag.ACC_RNI5N8O6V1_1[0]\ : AO1B - port map(A => N_1490, B => \ACC_RNIN7OINV1[1]\, C => N_1488, - Y => \G_80_0\); - - \r.btag.LVL_RNIIU70TI2[0]\ : MX2C - port map(A => N_1505, B => N_1508, S => cam_hitaddr_21(0), - Y => N_1512); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[14]\); - - \r.btag.LVL_RNIPIA991[0]\ : NOR2B - port map(A => hm_1_1, B => trans_op, Y => \un1_tlbcami_3\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[7]\); - - \r.btag.PPN_RNINGU5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_0(2), Y => N_1110); - - \r.btag.ACC_RNIQ3D3[1]\ : MX2 - port map(A => \pteout_0[3]\, B => pteout_1(3), S => - s2_entry(2), Y => N_1103); - - \r.btag.ACC_RNIO83LFV3[2]\ : OR3A - port map(A => N_1490, B => \ACC_RNIN7OINV1[1]\, C => su, Y - => \fault_pri\); - - \r.btag.LVL_RNIM6O7R[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.ACC_RNI638B8Q[1]\ : MX2C - port map(A => \ACC_RNI4GVGC7[1]\, B => N_1467, S => N_2551, - Y => \ACC_RNI638B8Q[1]\); - - \r.btag.PPN_RNI9MRE3H[10]\ : OR2A - port map(A => \pteout[18]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[18]\); - - \r.btag.PPN_RNIUK8C3H[6]\ : OR2A - port map(A => \pteout[14]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[14]\); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \LVL[0]\); - - \r.btag.SU_RNIRCLRA\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1_0(0), Y => N_8); - - \r.btag.PPN_RNI2N6PKO3[3]\ : OR3C - port map(A => data_1_3_i_a3_0_5_3, B => - \data_1_3_i_a3_0_4[15]\, C => \N_2709_i_0\, Y => - N_2699_i_0); - - \r.btag.I2_RNIEC1Q[0]\ : XOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => - \I2_RNIEC1Q[0]\); - - \r.btag.I2_RNIEI5AC[4]\ : OR3B - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE, Y => - h_l2_1); - - \r.btag.PPN_RNI060QDD1[13]\ : NOR2B - port map(A => \pteout_m_i_0[21]\, B => pteout_m_i_0_0_13, Y - => \data_1_3_i_a3_0[25]\); - - \r.btag.PPN_RNIAM6PKO3[0]\ : OR3C - port map(A => data_1_3_i_a3_0_5_0, B => - \data_1_3_i_a3_0_4[12]\, C => \N_2709_i_0\, Y => - N_2711_i_0); - - \r.btag.LVL_RNI7KH2[0]\ : NOR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.PPN_RNIVGU5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_0(2), Y => N_1114); - - \r.btag.PPN_RNIAQRE3H[11]\ : OR2A - port map(A => \pteout[19]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[19]\); - - \r.btag.I1_RNI5Q0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIF5VU[5]\, Y => h_i13_NE_2); - - \r.btag.ACC_RNI6LMBTS3[0]\ : OA1A - port map(A => \G_80_0\, B => N_686, C => \fault_pro67\, Y - => \fault_pro\); - - \r.btag.I3_RNI7G1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNI7G1Q[3]\); - - \r.btag.PPN_RNIVR5B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_0(2), Y => N_1123); - - \r.btag.PPN_RNISK8C3H[4]\ : OR2A - port map(A => \pteout[12]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[12]\); - - \r.btag.PPN_RNI1L8C3H[9]\ : OR2A - port map(A => \pteout[17]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i[17]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[30]\); - - \r.btag.LVL_RNIHDRT911[0]\ : OR2 - port map(A => \LVL_RNIT69H911[0]\, B => data(29), Y => - N_2720); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[74]\); - - \r.btag.PPN_RNIAT7G263[12]\ : NOR3C - port map(A => pteout_m_i_11, B => \pteout_m_i_0[20]\, C => - un2_wb_acc_iv_1_11, Y => un2_wb_acc_iv_4_11); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_0_12, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[12]\); - - \r.btag.ACC_RNICOJIGV3[2]\ : NOR3B - port map(A => N_1490, B => \ACC_RNIN7OINV1[1]\, C => - un54_fault_pro_m_0, Y => \un54_fault_pro_m\); - - \r.btag.PPN_RNINR4B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_0(2), Y => N_1119); - - \r.btag.PPN_RNII47ELO3[18]\ : OR3C - port map(A => data_1_3_i_a3_5_5, B => \data_1_3_i_a3_4[30]\, - C => \LVL_RNIT69H911[0]\, Y => N_2703_i_0); - - \r.btag.PPN_RNI1HU5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_0(2), Y => N_1115); - - \r.btag.LVL_RNI9TQT911[0]\ : OR2 - port map(A => \LVL_RNIT69H911[0]\, B => data(25), Y => - N_2714); - - \r.btag.ACC_RNIS3D3[2]\ : MX2 - port map(A => \pteout_0[4]\, B => pteout_1(4), S => - s2_entry(2), Y => N_1104); - - \r.btag.PPN_RNIFESE3H[16]\ : OR2A - port map(A => \pteout[24]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0_0[24]\); - - \p0.hf_1_RNIP34IE\ : MX2 - port map(A => hf_2_i, B => hf_1_i, S => TYP_1(0), Y => N_5); - - \r.btag.CTX_RNIGFUA1[0]\ : OR2B - port map(A => h_c2_NE_5, B => h_c2_NE_4, Y => h_c2_NE); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_0_26, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_0_23, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_0_16, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => \un1_tlbcami_3\, B => tlbcam_write_op_1_0(0), - Y => M_1_sqmuxa); - - \r.btag.PPN_RNILHT7BN2[9]\ : OR3C - port map(A => un2_wb_acc_iv_1_8, B => \un2_wb_acc_iv_0[17]\, - C => un2_wb_acc_iv_5(17), Y => \un2_wb_acc[17]\); - - \r.btag.ACC_RNI5N8O6V1_0[0]\ : NOR3A - port map(A => \ACC_RNIN7OINV1[1]\, B => N_1488, C => N_1490, - Y => fault_pro63); - - \r.btag.VALID_RNIUQETQ\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[59]\); - - \r.btag.I1_RNIMD3N3[0]\ : NOR3C - port map(A => \I1_RNI7G0Q[1]\, B => \I1_RNIIO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN_RNITK8C3H[5]\ : OR2A - port map(A => \pteout[13]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[13]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[72]\); - - \r.btag.VALID_RNI0CTJI\ : NOR3A - port map(A => h_l3_1_4, B => h_l2_1, C => hm_4, Y => hm_1); - - \r.btag.PPN_RNI2UAG263[18]\ : NOR3C - port map(A => pteout_m_i_0_18, B => pteout_m_i_0_0_18, C - => \data_1_3_i_a3_0[30]\, Y => \data_1_3_i_a3_4[30]\); - - \r.btag.I1_RNI841K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI040Q[6]\, Y => h_i13_NE_3); - - \r.btag.PPN_RNIGISE3H[17]\ : OR2A - port map(A => \pteout[25]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0_0[25]\); - - \r.btag.PPN_RNIDHT7BN2[8]\ : OR2B - port map(A => un2_wb_acc_iv_5(16), B => - \un2_wb_acc_iv_4[16]\, Y => \un2_wb_acc[16]\); - - \r.btag.PPN_RNI6D7G263[11]\ : NOR3C - port map(A => pteout_m_i_10, B => \pteout_m_i_0[19]\, C => - un2_wb_acc_iv_1_10, Y => un2_wb_acc_iv_4_10); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \p0.hf_1_RNO_0\ : NOR2 - port map(A => \LVL[0]\, B => \LVL[1]\, Y => hf_1_0); - - \r.btag.PPN_RNIDTSSBN2[17]\ : NOR3C - port map(A => data_1_3_i_a3_3(29), B => data_1_3_i_a3_2(29), - C => \data_1_3_i_a3_4[29]\, Y => data_1_3_i_a3_6_4); - - \r.btag.PPN_RNITJ5B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_0(2), Y => N_1122); - - \r.btag.CTX_RNINNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_4, Y => h_c2_5_i); - - \r.btag.PPN_RNI0L8C3H[8]\ : OR2A - port map(A => \pteout[16]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[16]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data_0_11, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_4 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1 : in std_logic_vector(5 to 5); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_7 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(5 to 5); - pteout_0 : in std_logic_vector(4 downto 2); - cam_hitaddr_18 : in std_logic_vector(1 to 1); - LVL_0 : in std_logic_vector(0 to 0); - TYP_1 : in std_logic_vector(2 downto 0); - tlbcam_write_op_1_0 : in std_logic_vector(5 to 5); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - ctx : in std_logic_vector(7 downto 0); - I2_1 : in std_logic_vector(5 downto 0); - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I3_1_5 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - cam_hitaddr_21_1 : out std_logic_vector(0 to 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_11 : in std_logic; - pteout_m_i_10 : in std_logic; - pteout_m_i_9 : in std_logic; - pteout_m_i_7 : in std_logic; - pteout_m_i_4 : in std_logic; - pteout_m_i_1 : in std_logic; - pteout_m_i_0_d0 : in std_logic; - pteout_m_i_3 : in std_logic; - un2_wb_acc_iv_1_11 : out std_logic; - un2_wb_acc_iv_1_10 : out std_logic; - un2_wb_acc_iv_1_9 : out std_logic; - un2_wb_acc_iv_1_7 : out std_logic; - un2_wb_acc_iv_1_4 : out std_logic; - un2_wb_acc_iv_1_1 : out std_logic; - un2_wb_acc_iv_1_0 : out std_logic; - un2_wb_acc_iv_1_3 : out std_logic; - data_1_3_i_a3_0_1 : out std_logic_vector(12 to 12); - data_1_3_i_a3_1_0 : out std_logic; - data_1_3_i_a3_1_2 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(58 to 58); - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0_d0 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_24 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_6 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_13 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_12 : out std_logic; - pteout_8 : out std_logic; - pteout_23 : out std_logic; - pteout_25 : out std_logic; - pteout_11 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_0 : in std_logic; - pteout_m_i_0_15 : in std_logic; - pteout_m_i_0_17 : in std_logic; - pteout_m_i_0_3 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_1471 : out std_logic; - NEEDSYNC : out std_logic; - N_1470 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_1469 : out std_logic; - N_1497 : out std_logic; - s2_flush_1 : in std_logic; - trans_op : in std_logic; - N_2483 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - WBNEEDSYNC_m : out std_logic; - N_61 : in std_logic; - hit_1 : in std_logic; - hit_0 : out std_logic; - hit : in std_logic; - M_1 : in std_logic - ); - -end mmutlbcam_2_0_4; - -architecture DEF_ARCH of mmutlbcam_2_0_4 is - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal WBNEEDSYNC_m_0, hm_1_1, hf_1_1_1_a0_3_3, - hf_1_1_1_a0_3_2, h_l2_1_2, hf_1_1_1_a0_3_1, un3_hf, - hf_1_1_1_a1_2_1, \LVL[1]\, h_l3_1_4_2, \un1_tag0[59]\, - \I3_RNIIS1Q[4]\, h_l3_1_4_1, \un1_tag0[56]\, h_l3_1_4_0, - \un1_tag0[57]\, \I3_RNIQ8291[2]\, h_i13_NE_4, - \I1_RNICG0Q[1]\, \I1_RNINO091[0]\, h_i13_NE_1, h_i13_NE_3, - \un1_tag0[75]\, \I1_RNI540Q[6]\, h_i13_NE_2, - \un1_tag0[72]\, \I1_RNIK5VU[5]\, \un1_tag0[70]\, - \I1_RNIM81Q[3]\, h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, - hf_4_0, \un1_tag0[43]\, SU, h_c2_NE_5, h_c2_5_i, h_c2_4_i, - h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, - h_l2_1, h_l2_1_3, h_i13_NE, hf_3, \un45_res[3]\, hm_1, - h_l3_1_4_i, hm_4, hf_4, h_c2_NE_i_0, h_i22_1, h_i22_0, - \I3_RNIADVU[5]\, hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, hm_3, - N_5, h_i22_5, h_i22_4, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[74]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[62]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[66]\, \un1_tag0[67]\, - \un1_tag0[58]\, \un1_tag0[60]\, \un1_tag0[61]\, - \un1_tag0[68]\, \un1_tag0[73]\, M_2, \pteout[6]\, M_5, - un1_tlbcami_3, \hit_0\, hf_1_1, M_1_sqmuxa, \LVL[0]\, N_1, - N_3, N_7, N_6, N_8, N_9, VALID_RNO_11, N_15, \pteout[2]\, - \pteout[3]\, \pteout[4]\, \pteout[8]\, \pteout[9]\, - \pteout[10]\, \pteout[11]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[15]\, \pteout[16]\, \pteout[17]\, - \pteout[18]\, \pteout[19]\, \pteout[20]\, \pteout[21]\, - \pteout[22]\, \pteout[23]\, \pteout[24]\, \pteout[25]\, - \pteout[26]\, \pteout[27]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - pteout_17 <= \pteout[17]\; - pteout_4 <= \pteout[4]\; - pteout_3 <= \pteout[3]\; - pteout_2 <= \pteout[2]\; - pteout_27 <= \pteout[27]\; - pteout_26 <= \pteout[26]\; - pteout_24 <= \pteout[24]\; - pteout_22 <= \pteout[22]\; - pteout_21 <= \pteout[21]\; - pteout_15 <= \pteout[15]\; - pteout_14 <= \pteout[14]\; - pteout_6 <= \pteout[6]\; - pteout_20 <= \pteout[20]\; - pteout_19 <= \pteout[19]\; - pteout_18 <= \pteout[18]\; - pteout_16 <= \pteout[16]\; - pteout_13 <= \pteout[13]\; - pteout_10 <= \pteout[10]\; - pteout_9 <= \pteout[9]\; - pteout_12 <= \pteout[12]\; - pteout_8 <= \pteout[8]\; - pteout_23 <= \pteout[23]\; - pteout_25 <= \pteout[25]\; - pteout_11 <= \pteout[11]\; - hit_0 <= \hit_0\; - - \r.btag.PPN_RNIIN8MKO1[15]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[23]\, C => - pteout_m_i_0_15, Y => data_1_3_i_a3_1_0); - - \r.btag.I3_RNI8JOEC[0]\ : OR3B - port map(A => hf_1_1_1_a0_3_3, B => h_l2_1_3, C => - h_l3_1_4_i, Y => hf_1_1_1_a0_3_i); - - \r.btag.ACC_RNIPU6U49[2]\ : MX2C - port map(A => \pteout[4]\, B => pteout_0(4), S => - cam_hitaddr_18(1), Y => N_1471); - - \r.btag.LVL_RNI197RR[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.CTX_RNIKNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx(1), Y => h_c2_1_i); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[8]\); - - \r.btag.I2_RNIPTRT1[4]\ : NOR2 - port map(A => h_i22_5, B => h_i22_4, Y => h_l2_1_2); - - \r.btag.LVL_RNIIJ25R[1]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \LVL[1]\); - - \r.btag.I2_RNIR82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[63]\); - - \r.btag.I2_RNI5O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[19]\); - - \r.btag.I3_RNIQ8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIQ8291[2]\); - - \r.btag.PPN_RNIGC1HKO1[5]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[13]\, C => - pteout_m_i_4, Y => un2_wb_acc_iv_1_4); - - \r.btag.I3_RNI16BR4[0]\ : OR3C - port map(A => h_l3_1_4_1, B => \I3_RNIADVU[5]\, C => - h_l3_1_4_2, Y => h_l3_1_4_i); - - \r.btag.I3_RNISV7E1[1]\ : XA1 - port map(A => N_61, B => \un1_tag0[57]\, C => - \I3_RNIQ8291[2]\, Y => h_l3_1_4_0); - - \r.btag.LVL_RNIH6H6A1[0]\ : NOR2A - port map(A => trans_op, B => hm_1_1, Y => un1_tlbcami_3); - - \r.btag.VALID_RNIJ34581\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[67]\); - - \r.btag.M_RNIV4R6B1\ : NOR3 - port map(A => M_1, B => \pteout[6]\, C => hm_1_1, Y => - WBNEEDSYNC_m_0); - - \r.btag.I3_RNIUC3K1[3]\ : XA1 - port map(A => I3_1_i(3), B => \un1_tag0[59]\, C => - \I3_RNIIS1Q[4]\, Y => h_l3_1_4_2); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(5), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNIAC1HKO1[2]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[10]\, C => - pteout_m_i_1, Y => un2_wb_acc_iv_1_1); - - \r.btag.LVL_RNIMCRF[0]\ : NOR3A - port map(A => TYP_1_0(0), B => \LVL[1]\, C => \LVL[0]\, Y - => hf_1_1_1_a0_3_1); - - \r.btag.CTX_RNI8ULK1[0]\ : NOR2B - port map(A => h_c2_NE_5, B => h_c2_NE_4, Y => h_c2_NE_i_0); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => SU); - - \r.btag.CTX_RNIQNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx(4), Y => h_c2_4_i); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[36]\); - - \r.btag.PPN_RNIUR4BAS[19]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[27]\, Y => - pteout_m_i_18); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[10]\); - - \r.btag.I1_RNIM81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIM81Q[3]\); - - \r.btag.VALID_RNIBBKUR\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[57]\); - - \r.btag.CTX_RNIONI6[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx(3), Y => h_c2_3_i); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_28); - - \r.btag.VALID_RNING9S8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[38]\); - - \r.btag.PPN_RNIP74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[22]\, Y => - pteout_m_i_0_14); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_11); - - \r.btag.PPN_RNI8C1HKO1[1]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[9]\, C => - pteout_m_i_0_d0, Y => un2_wb_acc_iv_1_0); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[66]\); - - \r.btag.LVL_RNII5CGB[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1(0), Y => N_8); - - \r.btag.CTX_RNIKVAQ[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[68]\); - - \r.btag.PPN_RNIDMG8AS[9]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[17]\, Y => - pteout_m_i_8); - - \r.btag.VALID_RNIAMVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.PPN_RNIBMG8AS[7]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[15]\, Y => - pteout_m_i_6); - - \r.btag.LVL_RNIIL20A1[0]\ : MX2 - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.M_RNIUL9DB1\ : OR3A - port map(A => un1_tlbcami_3, B => M_1, C => \pteout[6]\, Y - => NEEDSYNC); - - \r.btag.CTX_RNISNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx(5), Y => h_c2_5_i); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[22]\); - - \r.btag.LVL_RNIVI4I7[1]\ : OR3C - port map(A => h_l2_1_2, B => hf_1_1_1_a1_2_1, C => h_l2_1_3, - Y => hf_1_1_1_a1_2_i); - - \r.btag.CTX_RNIUF5D[6]\ : XA1A - port map(A => ctx(6), B => \un1_tag0[41]\, C => h_c2_7_i, Y - => h_c2_NE_3); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_29); - - \r.btag.PPN_RNIAMG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[14]\, Y => - pteout_m_i_5); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[64]\); - - \r.btag.I2_RNIG9483[0]\ : NOR3 - port map(A => h_i22_1, B => h_i22_0, C => h_l2_1_3_1, Y => - h_l2_1_3); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_11, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.LVL_RNI9II3E[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \pteout[4]\); - - \r.btag.I1_RNIAE3N3[0]\ : NOR3C - port map(A => \I1_RNICG0Q[1]\, B => \I1_RNINO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.CTX_RNIKUAQ[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[25]\); - - \r.btag.PPN_RNIO34BAS[13]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[21]\, Y => - pteout_m_i_0_13); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \pteout[3]\); - - \r.btag.I2_RNIQOTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[60]\); - - \r.btag.I1_RNI752K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIM81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.LVL_RNIOA1DM6[0]\ : OR3 - port map(A => hit, B => \hit_0\, C => hit_1, Y => - cam_hitaddr_21_1(0)); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_1); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[11]\); - - \r.btag.SU_RNI8PHT1_0\ : OR2B - port map(A => hf_4_0, B => h_c2_NE_i_0, Y => hf_4); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_0_d0); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[20]\); - - \r.btag.I1_RNII41K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI540Q[6]\, Y => h_i13_NE_3); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_31); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[42]\); - - \r.btag.CTX_RNI0OI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx(7), Y => h_c2_7_i); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[65]\); - - \r.btag.I2_RNI2K0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.PPN_RNICV7MKO1[12]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[20]\, C => - pteout_m_i_11, Y => un2_wb_acc_iv_1_11); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(5), - Y => M_5); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[56]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNIEC1HKO1[4]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[12]\, C => - pteout_m_i_3, Y => un2_wb_acc_iv_1_3); - - \r.btag.SU_RNI8PHT1\ : OA1 - port map(A => h_c2_NE_i_0, B => SU, C => \un1_tag0[43]\, Y - => un3_hf); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[24]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[37]\); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[15]\); - - \r.btag.CTX_RNIEF5D[2]\ : XA1A - port map(A => ctx(2), B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.I3_RNIADVU[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => I3_1_5, Y => - \I3_RNIADVU[5]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_7); - - \r.btag.CTX_RNIINI6[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx(0), Y => h_c2_0_i); - - \r.btag.LVL_RNIU5DD2[0]\ : NOR2B - port map(A => hf_1_1_1_a0_3_1, B => un3_hf, Y => - hf_1_1_1_a0_3_2); - - \r.btag.PPN_RNIMC1HKO1[8]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[16]\, C => - pteout_m_i_7, Y => un2_wb_acc_iv_1_7); - - \r.btag.LVL_RNIMB4C2[1]\ : NOR3A - port map(A => un3_hf, B => TYP_1_0(0), C => \LVL[1]\, Y => - hf_1_1_1_a1_2_1); - - \r.btag.I1_RNIBD547[4]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.ACC_RNILU6U49[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0(2), S => - cam_hitaddr_18(1), Y => N_1469); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \LVL[0]\); - - \r.btag.VALID_RNI1UKTI\ : NOR3 - port map(A => h_l3_1_4_i, B => hm_4, C => h_l2_1, Y => hm_1); - - \r.btag.PPN_RNIAN7MKO1[11]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[19]\, C => - pteout_m_i_10, Y => un2_wb_acc_iv_1_10); - - \r.btag.M_RNIB26ELT\ : OR2B - port map(A => WBNEEDSYNC_m_0, B => un1_cam_hitaddr(58), Y - => WBNEEDSYNC_m); - - \r.btag.LVL_RNI4R849[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.SU_RNI0RR8\ : NOR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.LVL_RNIJAQU49[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => - cam_hitaddr_18(1), Y => N_1497); - - \r.btag.LVL_RNI7DUBI2[0]\ : AO1B - port map(A => hf_1_1, B => s2_flush_1, C => hm_1_1, Y => - \hit_0\); - - \r.btag.I1_RNINO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNINO091[0]\); - - \r.btag.ACC_RNINU6U49[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0(3), S => - cam_hitaddr_18(1), Y => N_1470); - - \r.btag.I3_RNIIS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIIS1Q[4]\); - - \r.btag.I1_RNIK5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIK5VU[5]\); - - \r.btag.PPN_RNI7MG8AS[3]\ : NAND2 - port map(A => \pteout[11]\, B => un1_cam_hitaddr(58), Y => - pteout_m_i_0_3); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_30); - - \r.btag.I2_RNIKK5AC[0]\ : OR3B - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE, Y => - h_l2_1); - - \r.btag.VALID_RNIC34O1\ : OR2B - port map(A => \un1_tag0[43]\, B => h_c2_NE_i_0, Y => hm_4); - - \r.btag.LVL_RNIHKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[12]\); - - \r.btag.LVL_RNIN39B4[0]\ : NOR2B - port map(A => hf_1_1_1_a0_3_2, B => h_l2_1_2, Y => - hf_1_1_1_a0_3_3); - - \r.btag.I1_RNI540Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI540Q[6]\); - - \r.btag.PPN_RNITN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[26]\, Y => - pteout_m_i_0_18); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => un1_tlbcami_3, B => tlbcam_write_op_1_0(5), Y - => M_1_sqmuxa); - - \r.btag.I1_RNICG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNICG0Q[1]\); - - \r.btag.PPN_RNI8F7MKO1[10]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[18]\, C => - pteout_m_i_9, Y => un2_wb_acc_iv_1_9); - - \r.btag.I3_RNIPB882[0]\ : XA1 - port map(A => I3_1_0, B => \un1_tag0[56]\, C => h_l3_1_4_0, - Y => h_l3_1_4_1); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[59]\); - - \r.btag.I1_RNIFQ0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIK5VU[5]\, Y => h_i13_NE_2); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[72]\); - - \r.btag.PPN_RNI6C1HKO1[0]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[8]\, C => - pteout_m_i_0_0, Y => data_1_3_i_a3_0_1(12)); - - \r.btag.I2_RNIV4UU[5]\ : XNOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => h_i22_5); - - \r.btag.I2_RNIJC1Q[0]\ : XNOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => h_i22_0); - - \r.btag.LVL_RNI17UNB[0]\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.PPN_RNIRF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[24]\, Y => - pteout_m_i_0_16); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.PPN_RNIM79MKO1[17]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[25]\, C => - pteout_m_i_0_17, Y => data_1_3_i_a3_1_2); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1_0 : in std_logic_vector(4 to 4); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_7 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(4 to 4); - un1_cam_hitaddr_1_0 : in std_logic; - un1_cam_hitaddr_1_6 : in std_logic; - un1_cam_hitaddr_1_5 : in std_logic; - un1_cam_hitaddr_0 : out std_logic; - un1_cam_hitaddr_2 : out std_logic; - un1_cam_hitaddr_4 : out std_logic; - un1_cam_hitaddr_5 : out std_logic; - un1_cam_hitaddr_6 : out std_logic; - un1_cam_hitaddr_1_d0 : out std_logic; - pteout_0 : in std_logic_vector(4 downto 2); - cam_hitaddr_18 : in std_logic_vector(1 to 1); - LVL_0 : in std_logic_vector(1 downto 0); - TYP_1 : in std_logic_vector(2 downto 1); - TYP_1_0 : in std_logic_vector(0 to 0); - tlbcam_write_op_1_0 : in std_logic_vector(4 to 4); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0_d0 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_27 : out std_logic; - pteout_6 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - ctx : in std_logic_vector(4 to 4); - I3_1_i : in std_logic_vector(3 to 3); - ctx_0_7 : in std_logic; - ctx_0_5 : in std_logic; - ctx_0_3 : in std_logic; - ctx_0_1 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_2 : in std_logic; - ctx_0_6 : in std_logic; - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - LVL : out std_logic_vector(1 downto 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_5 : in std_logic; - un2_wb_acc_iv_2 : out std_logic_vector(14 to 14); - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_0_d0 : out std_logic; - pteout_m_i_0_17 : in std_logic; - data_1_3_i_a3_2 : out std_logic_vector(29 to 29); - data_1_3_i_a3_3_2 : in std_logic; - data_1_3_i_a3_3_0 : in std_logic; - data_1_3_i_a3_5_2 : out std_logic; - data_1_3_i_a3_5_0 : out std_logic; - pteout_m_i_0_0_13 : in std_logic; - pteout_m_i_0_0_11 : in std_logic; - pteout_m_i_0_0_0 : in std_logic; - data_1_3_i_a3_0_2 : out std_logic_vector(15 to 15); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_1496 : out std_logic; - N_1468 : out std_logic; - NEEDSYNC : out std_logic; - N_1467 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_1466 : out std_logic; - N_1495 : out std_logic; - trans_op : in std_logic; - s2_flush_1 : in std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - hit_1 : in std_logic; - hit_0 : in std_logic; - N_2551 : out std_logic; - un1_cam_hitaddr_4_0 : in std_logic; - WBNEEDSYNC_m : out std_logic; - hit : in std_logic - ); - -end mmutlbcam_2_0; - -architecture DEF_ARCH of mmutlbcam_2_0 is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal h_c2_NE, h_c2_NE_4, h_c2_NE_5, hf_4, hf_4_0, - \un1_tag0[43]\, SU, \pteout_m_i_0[11]\, - \pteout_m_i_0[22]\, \pteout_m_i_0_0[25]\, - \pteout_m_i_0[24]\, \pteout_m_i_0[14]\, - \cam_hitaddr_12_i_a2_2[2]\, un18_hm, hm_1_1, hf_1_1_0, - hf_1_0, un3_hf, h_l3_1_4, \I3_RNIHS1Q[4]\, - \I3_RNIBG1Q[3]\, h_l3_1_3, \un1_tag0[61]\, h_l3_1_1, - \I3_RNIP8291[2]\, \I3_RNI1N55[1]\, \I3_RNISB0Q[0]\, - h_l2_1_3, \I2_RNIQ82Q[1]\, \I2_RNIIC1Q[0]\, h_l2_1_1, - h_l2_1_2, \un1_tag0[66]\, \I2_RNIU4UU[5]\, \un1_tag0[64]\, - \I2_RNI4O0Q[3]\, h_i13_NE_4, \I1_RNIBG0Q[1]\, - \I1_RNIMO091[0]\, h_i13_NE_1, h_i13_NE_3, \un1_tag0[75]\, - \I1_RNI440Q[6]\, h_i13_NE_2, \un1_tag0[72]\, - \I1_RNIJ5VU[5]\, \un1_tag0[70]\, \I1_RNIL81Q[3]\, - h_c2_5_i, h_c2_4_i, h_c2_NE_3, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, h_l2_1, h_i13_NE_i_0, hf_1, hf_3, \un45_res[3]\, - hf_2, \LVL[1]\, tlbcamo_needsync, \un1_cam_hitaddr[59]\, - \N_2551\, hm_4, hm_3, hm_1, \un1_tag0[56]\, - \un1_tag0[59]\, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[74]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[62]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[67]\, \un1_tag0[57]\, - \un1_tag0[58]\, \un1_tag0[60]\, \un1_tag0[68]\, - \un1_tag0[73]\, M_2, \pteout[6]\, M_5, h_su_cnt_1, hf_1_1, - M_1_sqmuxa, \LVL[0]\, N_89, N_90, N_92, N_94, N_93, N_95, - N_96, VALID_RNO_7, N_102, \pteout[2]\, \pteout[3]\, - \pteout[4]\, \pteout[8]\, \pteout[9]\, \pteout[10]\, - \pteout[11]\, \pteout[12]\, \pteout[13]\, \pteout[14]\, - \pteout[15]\, \pteout[16]\, \pteout[17]\, \pteout[18]\, - \pteout[19]\, \pteout[20]\, \pteout[21]\, \pteout[22]\, - \pteout[23]\, \pteout[24]\, \pteout[25]\, \pteout[26]\, - \pteout[27]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - pteout_17 <= \pteout[17]\; - pteout_4 <= \pteout[4]\; - pteout_3 <= \pteout[3]\; - pteout_2 <= \pteout[2]\; - pteout_27 <= \pteout[27]\; - pteout_6 <= \pteout[6]\; - pteout_26 <= \pteout[26]\; - pteout_25 <= \pteout[25]\; - pteout_24 <= \pteout[24]\; - pteout_23 <= \pteout[23]\; - pteout_22 <= \pteout[22]\; - pteout_21 <= \pteout[21]\; - pteout_20 <= \pteout[20]\; - pteout_19 <= \pteout[19]\; - pteout_18 <= \pteout[18]\; - pteout_16 <= \pteout[16]\; - pteout_15 <= \pteout[15]\; - pteout_14 <= \pteout[14]\; - pteout_13 <= \pteout[13]\; - pteout_12 <= \pteout[12]\; - pteout_11 <= \pteout[11]\; - pteout_10 <= \pteout[10]\; - pteout_9 <= \pteout[9]\; - pteout_8 <= \pteout[8]\; - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - N_2551 <= \N_2551\; - - \r.btag.LVL_RNIN7SP01[1]\ : MX2C - port map(A => hf_2, B => hf_1, S => TYP_1_0(0), Y => N_92); - - \r.btag.I3_RNIP8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIP8291[2]\); - - \r.btag.CTX_RNI4P98[6]\ : XA1A - port map(A => ctx_0_6, B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \p0.hf_4_RNI3FR49\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1_0(0), Y => N_95); - - \r.btag.PPN_RNILR3BAS[11]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[19]\, Y - => pteout_m_i_10); - - \r.btag.PPN_RNI3VGC9H3[14]\ : NOR3C - port map(A => \pteout_m_i_0[22]\, B => pteout_m_i_0_0_11, C - => data_1_3_i_a3_3_0, Y => data_1_3_i_a3_5_0); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[8]\); - - \r.btag.CTX_RNIJS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0_7, Y => h_c2_7_i); - - \r.btag.VALID_RNI8TNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1_0(0), Y => N_93); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \LVL[1]\); - - \r.btag.PPN_RNITR4BAS[19]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[27]\, Y - => pteout_m_i_18); - - \r.btag.LVL_RNITHHID[1]\ : OA1B - port map(A => h_l2_1, B => \LVL[1]\, C => hm_4, Y => N_90); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[63]\); - - \r.btag.I3_RNISB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNISB0Q[0]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[19]\); - - \r.btag.I1_RNIMO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIMO091[0]\); - - \r.btag.CTX_RNIFS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0_5, Y => h_c2_5_i); - - \r.btag.PPN_RNIO74BAS[14]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[22]\, Y - => \pteout_m_i_0[22]\); - - \r.btag.PPN_RNI4MG8AS[1]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[9]\, Y - => pteout_m_i_0_d0); - - \r.btag.LVL_RNIFKH2_0[0]\ : NOR2 - port map(A => \LVL[0]\, B => \LVL[1]\, Y => hf_1_0); - - \p0.hf_4\ : OR2 - port map(A => h_c2_NE, B => hf_4_0, Y => hf_4); - - \r.btag.PPN_RNICMG8AS[9]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[17]\, Y - => pteout_m_i_8); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[67]\); - - \p0.hf_4_RNIIGDC9\ : OR2B - port map(A => N_95, B => TYP_1(2), Y => N_96); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(4), Y => N_102); - - \r.btag.I2_RNIU4UU[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => - \I2_RNIU4UU[5]\); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNILC1HKO1[6]\ : NOR2B - port map(A => pteout_m_i_5, B => \pteout_m_i_0[14]\, Y => - un2_wb_acc_iv_2(14)); - - \r.btag.PPN_RNI3MG8AS[0]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[8]\, Y - => pteout_m_i_0_0_d0); - - \r.btag.LVL_RNIA85PQ[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_89); - - \r.btag.I3_RNIR5BR4[3]\ : NOR3C - port map(A => \I3_RNIHS1Q[4]\, B => \I3_RNIBG1Q[3]\, C => - h_l3_1_3, Y => h_l3_1_4); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[36]\); - - \r.btag.VALID_RNIGTJCI\ : OR3B - port map(A => h_l2_1, B => h_l3_1_4, C => hm_4, Y => hm_1); - - \r.btag.PPN_RNI7MG8AS[4]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[12]\, Y - => pteout_m_i_3); - - \r.btag.LVL_RNICTA7AS[0]\ : NOR2B - port map(A => un1_cam_hitaddr_4_0, B => \N_2551\, Y => - \un1_cam_hitaddr[59]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[10]\); - - \r.btag.VALID_RNIF3371\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_4); - - \r.btag.VALID_RNIIG8B8\ : OR2A - port map(A => h_i13_NE_i_0, B => hm_4, Y => hm_3); - - \r.btag.SU_RNI7K291\ : AO1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.CTX_RNI0HJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.I2_RNIC9483[0]\ : NOR3C - port map(A => \I2_RNIQ82Q[1]\, B => \I2_RNIIC1Q[0]\, C => - h_l2_1_1, Y => h_l2_1_3); - - \r.btag.LVL_RNIQ7JKI[0]\ : OR3C - port map(A => h_l2_1, B => h_l3_1_4, C => hf_1_1_0, Y => - hf_1); - - \r.btag.PPN_RNIP79MKO1[17]\ : NOR2B - port map(A => pteout_m_i_0_17, B => \pteout_m_i_0_0[25]\, Y - => data_1_3_i_a3_2(29)); - - \r.btag.PPN_RNI8MG8AS[5]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[13]\, Y - => pteout_m_i_4); - - \r.btag.M_RNI613RJT\ : OR3C - port map(A => hm_1_1, B => tlbcamo_needsync, C => - \un1_cam_hitaddr[59]\, Y => WBNEEDSYNC_m); - - \r.btag.LVL_RNICTA7AS_5[0]\ : NOR2A - port map(A => un1_cam_hitaddr_1_5, B => \N_2551\, Y => - un1_cam_hitaddr_5); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_28); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[17]\); - - \r.btag.I2_RNI0K0K1[2]\ : XA1 - port map(A => I2_1(2), B => \un1_tag0[64]\, C => - \I2_RNI4O0Q[3]\, Y => h_l2_1_1); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[21]\); - - \p0.h_c2_NE\ : NAND2 - port map(A => h_c2_NE_4, B => h_c2_NE_5, Y => h_c2_NE); - - \r.btag.LVL_RNIPD2F1[0]\ : NOR2B - port map(A => hf_1_0, B => un3_hf, Y => hf_1_1_0); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[38]\); - - \r.btag.ACC_RNIJU6U49[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0(2), S => - cam_hitaddr_18(1), Y => N_1466); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_102, B => un1_rst_i_0, Y => VALID_RNO_7); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[66]\); - - \r.btag.PPN_RNIQF4BAS[16]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[24]\, Y - => \pteout_m_i_0[24]\); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[68]\); - - \r.btag.CTX_RNIKO98[2]\ : XA1A - port map(A => ctx_0_2, B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.I2_RNINTRT1[4]\ : XA1 - port map(A => I2_1(4), B => \un1_tag0[66]\, C => - \I2_RNIU4UU[5]\, Y => h_l2_1_2); - - \r.btag.CTX_RNI7S44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_1, Y => h_c2_1_i); - - \r.btag.CTX_RNIPNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx(4), Y => h_c2_4_i); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_29); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[64]\); - - \r.btag.VALID_RNIE66I11\ : MX2C - port map(A => N_93, B => N_92, S => TYP_1(2), Y => N_94); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_7, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.LVL_RNIHAQU49[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => - cam_hitaddr_18(1), Y => N_1495); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \pteout[4]\); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[25]\); - - \r.btag.ACC_RNILU6U49[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0(3), S => - cam_hitaddr_18(1), Y => N_1467); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \pteout[3]\); - - \r.btag.LVL_RNIFKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[75]\); - - \r.btag.VALID_RNIAPGC1\ : NOR2B - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_1); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[11]\); - - \r.btag.M_RNIPK6Q91\ : OR3C - port map(A => trans_op, B => hm_1_1, C => tlbcamo_needsync, - Y => NEEDSYNC); - - \r.btag.CTX_RNICD1J[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.I1_RNIL81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIL81Q[3]\); - - \r.btag.I1_RNI440Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI440Q[6]\); - - \r.btag.I1_RNI552K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIL81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I1_RNIJ5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIJ5VU[5]\); - - \r.btag.I1_RNI3D547[4]\ : NOR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE_i_0); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_0_d0); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[20]\); - - \r.btag.I3_RNIMB882[0]\ : NOR3C - port map(A => \I3_RNIP8291[2]\, B => \I3_RNI1N55[1]\, C => - \I3_RNISB0Q[0]\, Y => h_l3_1_1); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_31); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[65]\); - - \r.btag.LVL_RNICTA7AS_1[0]\ : NOR2B - port map(A => un1_cam_hitaddr_1_6, B => \N_2551\, Y => - un1_cam_hitaddr_2); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(4), - Y => M_5); - - \r.btag.LVL_RNIO7VND[1]\ : OR3B - port map(A => un3_hf, B => h_l2_1, C => \LVL[1]\, Y => hf_2); - - \r.btag.LVL_RNIJAQU49[1]\ : MX2C - port map(A => \LVL[1]\, B => LVL_0(1), S => - cam_hitaddr_18(1), Y => N_1496); - - \r.btag.I3_RNIHS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIHS1Q[4]\); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[56]\); - - \r.btag.LVL_RNICTA7AS_0[0]\ : NOR2B - port map(A => un1_cam_hitaddr_1_5, B => \N_2551\, Y => - un1_cam_hitaddr_1_d0); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[71]\); - - \r.btag.LVL_RNICTA7AS_3[0]\ : NOR2A - port map(A => un1_cam_hitaddr_1_0, B => \N_2551\, Y => - un1_cam_hitaddr_4); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[9]\); - - \r.btag.PPN_RNI6MG8AS[3]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[11]\, Y - => \pteout_m_i_0[11]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[24]\); - - \r.btag.PPN_RNIBMG8AS[8]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[16]\, Y - => pteout_m_i_7); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.PPN_RNIMV3BAS[12]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[20]\, Y - => pteout_m_i_11); - - \r.btag.LVL_RNICTA7AS_4[0]\ : NOR2A - port map(A => un1_cam_hitaddr_1_6, B => \N_2551\, Y => - un1_cam_hitaddr_6); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[40]\); - - \r.btag.I1_RNI6E3N3[0]\ : NOR3C - port map(A => \I1_RNIBG0Q[1]\, B => \I1_RNIMO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.CTX_RNIBS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.I3_RNI1N55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNI1N55[1]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[37]\); - - \r.btag.LVL_RNIEKVC81[0]\ : MX2 - port map(A => N_89, B => N_90, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.PPN_RNIKN3BAS[10]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[18]\, Y - => pteout_m_i_9); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[15]\); - - \r.btag.LVL_RNIAURM25[0]\ : NOR3A - port map(A => un18_hm, B => hit, C => hm_1_1, Y => - \cam_hitaddr_12_i_a2_2[2]\); - - \r.btag.I1_RNIDQ0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIJ5VU[5]\, Y => h_i13_NE_2); - - \p0.hf_4_RNO\ : OR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[14]\); - - \r.btag.I2_RNI4O0Q[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => - \I2_RNI4O0Q[3]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_7); - - \r.btag.PPN_RNI9MG8AS[6]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[14]\, Y - => \pteout_m_i_0[14]\); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \LVL[0]\); - - \r.btag.LVL_RNISQ7J8[0]\ : OR3C - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE_i_0, - Y => hf_3); - - \r.btag.LVL_RNIDK1SM9[0]\ : OR3A - port map(A => \cam_hitaddr_12_i_a2_2[2]\, B => hit_0, C => - hit_1, Y => \N_2551\); - - \r.btag.ACC_RNINU6U49[2]\ : MX2C - port map(A => \pteout[4]\, B => pteout_0(4), S => - cam_hitaddr_18(1), Y => N_1468); - - \r.btag.I2_RNIQ82Q[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => - \I2_RNIQ82Q[1]\); - - \r.btag.PPN_RNIRJ4BAS[17]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[25]\, Y - => \pteout_m_i_0_0[25]\); - - \r.btag.CTX_RNI5S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_0, Y => h_c2_0_i); - - \r.btag.PPN_RNIN34BAS[13]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[21]\, Y - => pteout_m_i_0_13); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_30); - - \r.btag.PPN_RNIAMG8AS[7]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[15]\, Y - => pteout_m_i_6); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[12]\); - - \r.btag.PPN_RNI5MG8AS[2]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[10]\, Y - => pteout_m_i_1); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[16]\); - - \r.btag.PPN_RNIPB4BAS[15]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[23]\, Y - => pteout_m_i_0_15); - - \r.btag.M_RNO_0\ : AOI1 - port map(A => hm_1_1, B => trans_op, C => - tlbcam_write_op_1_0(4), Y => M_1_sqmuxa); - - \r.btag.LVL_RNICTA7AS_2[0]\ : NOR2B - port map(A => un1_cam_hitaddr_1_0, B => \N_2551\, Y => - un1_cam_hitaddr_0); - - \r.btag.I1_RNIBG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNIBG0Q[1]\); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[59]\); - - \r.btag.M_RNICFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => tlbcamo_needsync); - - \r.btag.I1_RNIG41K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI440Q[6]\, Y => h_i13_NE_3); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[72]\); - - \r.btag.I3_RNIBG1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNIBG1Q[3]\); - - \r.btag.PPN_RNIBVHC9H3[16]\ : NOR3C - port map(A => \pteout_m_i_0[24]\, B => pteout_m_i_0_0_13, C - => data_1_3_i_a3_3_2, Y => data_1_3_i_a3_5_2); - - \r.btag.VALID_RNI9SSJB1\ : OR2B - port map(A => hf_1_1, B => s2_flush_1, Y => un18_hm); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.I2_RNI6K5AC[4]\ : NOR3C - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE_i_0, Y - => h_l2_1); - - \r.btag.PPN_RNISN4BAS[18]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[26]\, Y - => pteout_m_i_0_18); - - \r.btag.PPN_RNIFC1HKO1[3]\ : AND2 - port map(A => \pteout_m_i_0[11]\, B => pteout_m_i_0_0_0, Y - => data_1_3_i_a3_0_2(15)); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[18]\); - - \r.btag.VALID_RNI785DB1\ : MX2C - port map(A => N_96, B => N_94, S => TYP_1(1), Y => hf_1_1); - - \r.btag.I3_RNIVO773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_1, Y - => h_l3_1_3); - - \r.btag.I2_RNIIC1Q[0]\ : XOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => - \I2_RNIIC1Q[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_5 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - tlbcam_write_op_1_1_0 : in std_logic_vector(1 to 1); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_17 : in std_logic; - hrdata_10 : in std_logic; - hrdata_7 : in std_logic; - hrdata_6 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_0_d0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(1 to 1); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - un1_cam_hitaddr_1_0 : out std_logic; - un1_cam_hitaddr_1_5 : out std_logic; - un1_cam_hitaddr_1_6 : out std_logic; - TYP_1 : in std_logic_vector(2 downto 0); - s2_entry : in std_logic_vector(2 to 2); - pteout_1 : in std_logic_vector(4 downto 2); - LVL_1 : in std_logic_vector(0 to 0); - tlbcam_write_op_1_0 : in std_logic_vector(1 to 1); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_3 : in std_logic_vector(2 to 2); - s2_entry_2 : in std_logic_vector(2 to 2); - pteout_0_17 : in std_logic; - pteout_0_4 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - ctx_0_d0 : in std_logic; - ctx_1 : in std_logic; - ctx_4 : in std_logic; - ctx_5 : in std_logic; - ctx_7 : in std_logic; - ctx_3 : in std_logic; - cam_hitaddr_21_1 : in std_logic_vector(0 to 0); - un1_cam_hitaddr : in std_logic_vector(62 to 62); - ctx_0_0 : in std_logic; - ctx_0_4 : in std_logic; - I1_1_6 : in std_logic; - I1_1_3 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_5 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I3_1_5 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - LVL_1_d0 : out std_logic; - cam_hitaddr_18 : in std_logic_vector(1 to 1); - cam_hitaddr_21 : out std_logic_vector(0 to 0); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_3043 : in std_logic; - s2_flush : in std_logic; - N_1206 : out std_logic; - un1_rst_i_0 : in std_logic; - N_1219 : out std_logic; - N_1482 : out std_logic; - N_1471 : in std_logic; - N_1481 : out std_logic; - N_1205 : out std_logic; - N_1470 : in std_logic; - N_1480 : out std_logic; - N_1235 : out std_logic; - N_1469 : in std_logic; - N_1479 : out std_logic; - N_1497 : in std_logic; - N_1505 : out std_logic; - NEEDSYNC : out std_logic; - s2_flush_1 : in std_logic; - trans_op : in std_logic; - N_2483 : in std_logic; - N_3046 : in std_logic; - N_1234 : out std_logic; - N_1233 : out std_logic; - N_1232 : out std_logic; - N_1231 : out std_logic; - N_1230 : out std_logic; - N_1229 : out std_logic; - N_1228 : out std_logic; - N_1227 : out std_logic; - N_1226 : out std_logic; - N_1225 : out std_logic; - N_1224 : out std_logic; - N_1223 : out std_logic; - N_1222 : out std_logic; - N_1221 : out std_logic; - N_1220 : out std_logic; - N_1218 : out std_logic; - N_1217 : out std_logic; - N_1216 : out std_logic; - N_1215 : out std_logic; - N_1214 : out std_logic; - N_1213 : out std_logic; - N_1212 : out std_logic; - N_1211 : out std_logic; - N_1210 : out std_logic; - N_1209 : out std_logic; - N_1208 : out std_logic; - N_1204 : out std_logic; - N_1203 : out std_logic; - N_1202 : out std_logic; - N_2551 : in std_logic; - cam_hit_all_5_sqmuxa : out std_logic; - cam_hit_all_5_sqmuxa_2 : in std_logic; - cam_hit_all_5_sqmuxa_0_a2_0 : out std_logic; - accexc_6_3 : in std_logic; - accexc_6_4 : in std_logic; - accexc_6 : out std_logic; - N_661 : in std_logic; - N_61 : in std_logic; - un1_cam_hitaddr_4_0 : out std_logic; - M_1 : in std_logic; - accexc_6_2 : in std_logic; - WBNEEDSYNC_m : in std_logic - ); - -end mmutlbcam_2_0_5; - -architecture DEF_ARCH of mmutlbcam_2_0_5 is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal accexc_6_5, WBNEEDSYNC_m_0, WBNEEDSYNC_m_0_0, hm_1_1, - \pteout[6]\, hf_1_0, \LVL[0]\, h_l3_1_4, h_l3_1_1, - \I3_RNI6DVU[5]\, h_l3_1_2, \un1_tag0[59]\, - \I3_RNIES1Q[4]\, \un1_tag0[56]\, h_l3_1_0, \un1_tag0[57]\, - \I3_RNIM8291[2]\, h_l2_1_4, h_l2_1_1, h_l2_1_0, h_l2_1_2, - \un1_tag0[66]\, \I2_RNIR4UU[5]\, \un1_tag0[64]\, - \I2_RNI1O0Q[3]\, \un1_tag0[62]\, \I2_RNIN82Q[1]\, - h_i13_NE_4, \I1_RNI8G0Q[1]\, \I1_RNIJO091[0]\, h_i13_NE_1, - h_i13_NE_3, \un1_tag0[74]\, \I1_RNI901Q[7]\, h_i13_NE_2, - \un1_tag0[73]\, \I1_RNINK1Q[4]\, \un1_tag0[70]\, - \I1_RNII81Q[3]\, h_c2_NE_5, h_c2_5_i, h_c2_4_i, h_c2_NE_3, - h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, \un1_tag0[41]\, - h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, h_l2_1, h_i13_NE, - h_l3_1, hf_4, \un1_tag0[43]\, SU, h_c2_NE, hf_3, un3_hf, - \un45_res[3]\, hf_2_i, \LVL[1]\, hf_1_i, - \cam_hitaddr_21[0]\, hit, hm_4, hm_3, hm_1, - \cam_hit_all_5_sqmuxa_0_a2_0\, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[72]\, \un1_tag0[75]\, - \un1_tag0[38]\, \pteout[0]\, \pteout[1]\, \pteout[2]\, - \pteout[7]\, \pteout[8]\, \pteout[9]\, \pteout[10]\, - \pteout[11]\, \pteout[12]\, \pteout[13]\, \pteout[14]\, - \pteout[15]\, \pteout[16]\, \pteout[18]\, \pteout[19]\, - \pteout[20]\, \pteout[21]\, \pteout[22]\, \pteout[23]\, - \pteout[24]\, \pteout[25]\, \pteout[26]\, \pteout[27]\, - \pteout[28]\, \pteout[29]\, \pteout[30]\, \pteout[31]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, - \un1_tag0[60]\, \un1_tag0[61]\, \un1_tag0[68]\, M_2, M_5, - un1_tlbcami_3, hf_1_1, M_1_sqmuxa, N_1, N_3, N_1493, - N_1463, N_1464, \pteout[3]\, N_9, N_8, N_6, N_7_i, N_5, - N_1465, \pteout[4]\, \pteout[17]\, VALID_RNO_12, N_15, - \un1_tag0[42]\, \un1_tag0[40]\, \un1_tag0[39]\, - \un1_tag0[36]\, \un1_tag0[35]\, \un1_tag0[58]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - LVL_1_d0 <= \LVL[1]\; - cam_hitaddr_21(0) <= \cam_hitaddr_21[0]\; - cam_hit_all_5_sqmuxa_0_a2_0 <= \cam_hit_all_5_sqmuxa_0_a2_0\; - - \r.btag.LVL_RNIA8FH91[0]\ : MX2C - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.CTX_RNIENI6[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_d0, Y => h_c2_0_i); - - \r.btag.LVL_RNIUI0FE9[0]\ : NOR2A - port map(A => hit, B => cam_hitaddr_21_1(0), Y => - \cam_hitaddr_21[0]\); - - \r.btag.ET_RNI3DTA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_2(2), Y => N_1203); - - \r.btag.VALID_RNIL3POI\ : NOR2 - port map(A => hm_4, B => h_l3_1, Y => hm_1); - - \r.btag.VALID_RNIGB8J1\ : OR2A - port map(A => \un1_tag0[43]\, B => h_c2_NE, Y => hm_4); - - \r.btag.I2_RNI1O0Q[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => - \I2_RNI1O0Q[3]\); - - \r.btag.VALID_RNI6MVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.M_RNII8MUA1\ : OR3A - port map(A => un1_tlbcami_3, B => M_1, C => \pteout[6]\, Y - => NEEDSYNC); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[8]\); - - \r.btag.PPN_RNIIR3BAS[11]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[19]\, Y => - pteout_m_i_10); - - \r.btag.I1_RNI901Q[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => I1_1_6, Y => - \I1_RNI901Q[7]\); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \LVL[1]\); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[63]\); - - \r.btag.ACC_RNIU3D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_1(4), S => - s2_entry(2), Y => N_1206); - - \r.btag.I1_RNIJO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIJO091[0]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[19]\); - - \r.btag.PPN_RNIPN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[26]\, Y => - pteout_m_i_0_18); - - \r.btag.PPN_RNI6K6B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_3(2), Y => N_1232); - - \r.btag.LVL_RNIV89BJI[0]\ : NOR2B - port map(A => \cam_hitaddr_21[0]\, B => cam_hitaddr_18(1), - Y => un1_cam_hitaddr_1_5); - - \r.btag.I1_RNIA41K1[6]\ : XA1 - port map(A => I1_1_5, B => \un1_tag0[74]\, C => - \I1_RNI901Q[7]\, Y => h_i13_NE_3); - - \r.btag.PPN_RNIJV3BAS[12]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[20]\, Y => - pteout_m_i_11); - - \r.btag.M_RNIK7HGLL3\ : NOR3C - port map(A => WBNEEDSYNC_m, B => WBNEEDSYNC_m_0, C => - accexc_6_2, Y => accexc_6_5); - - \r.btag.I3_RNIDB882[0]\ : XA1 - port map(A => I3_1_0, B => \un1_tag0[56]\, C => h_l3_1_0, Y - => h_l3_1_1); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[67]\); - - \r.btag.PPN_RNI6S6B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_3(2), Y => N_1223); - - \r.btag.I1_RNINK1Q[4]\ : XOR2 - port map(A => \un1_tag0[72]\, B => I1_1_3, Y => - \I1_RNINK1Q[4]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(1), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[41]\); - - \r.btag.CTX_RNISNI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_7, Y => h_c2_7_i); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[36]\); - - \r.btag.LVL_RNI9KH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.PPN_RNI4C6B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_3(2), Y => N_1231); - - \r.btag.LVL_RNI9E44E[1]\ : NOR3A - port map(A => un3_hf, B => \LVL[1]\, C => h_l2_1, Y => - hf_2_i); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[10]\); - - \r.btag.I1_RNI8G0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNI8G0Q[1]\); - - \r.btag.I2_RNIN82Q[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => - \I2_RNIN82Q[1]\); - - \r.btag.I2_RNIH6065[0]\ : NOR3C - port map(A => h_l2_1_1, B => h_l2_1_0, C => h_l2_1_2, Y => - h_l2_1_4); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.SU_RNIAKK6B\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1(0), Y => N_8); - - \r.btag.PPN_RNIHN3BAS[10]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[18]\, Y => - pteout_m_i_9); - - \r.btag.I3_RNIM8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIM8291[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.ACC_RNIFHFO0S[0]\ : MX2C - port map(A => N_1463, B => N_1469, S => N_2551, Y => N_1479); - - \r.btag.CTX_RNIMNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_4, Y => h_c2_4_i); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_0_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => un1_rst_i_0, B => N_15, Y => VALID_RNO_12); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[66]\); - - \r.btag.CTX_RNIKNI6[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_3, Y => h_c2_3_i); - - \r.btag.I1_RNIBC547[5]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[68]\); - - \r.btag.ACC_RNIHU6U49[2]\ : MX2C - port map(A => \pteout[4]\, B => pteout_0_4, S => - cam_hitaddr_18(1), Y => N_1465); - - \r.btag.LVL_RNI68V1O2[0]\ : AOI1 - port map(A => hf_1_1, B => s2_flush_1, C => hm_1_1, Y => - hit); - - \r.btag.I3_RNI5OG5H[0]\ : OR2A - port map(A => h_l3_1_4, B => h_l2_1, Y => h_l3_1); - - \r.btag.I3_RNIKV7E1[1]\ : XA1 - port map(A => N_61, B => \un1_tag0[57]\, C => - \I3_RNIM8291[2]\, Y => h_l3_1_0); - - \r.btag.I3_RNIMC3K1[3]\ : XA1 - port map(A => I3_1_i(3), B => \un1_tag0[59]\, C => - \I3_RNIES1Q[4]\, Y => h_l3_1_2); - - \r.btag.PPN_RNIE106[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_3(2), Y => N_1218); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_0_22, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[29]\); - - \r.btag.LVL_RNIU366[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_3(2), - Y => N_1234); - - \r.btag.ACC_RNIDU6U49[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_1(2), S => - cam_hitaddr_18(1), Y => N_1463); - - \r.btag.LVL_RNIB72B5J[0]\ : OR2B - port map(A => \cam_hitaddr_21[0]\, B => N_2551, Y => N_1482); - - \r.btag.SU_RNIPL6EB\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_12, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.PPN_RNIAC7B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_3(2), Y => N_1225); - - \r.btag.LVL_RNIB9MP0S[0]\ : MX2C - port map(A => N_1493, B => N_1497, S => N_2551, Y => N_1505); - - \r.btag.VALID_RNIQ40D21\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7_i); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[4]\); - - \r.btag.PPN_RNI7MG8AS[7]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[15]\, Y => - pteout_m_i_6); - - \r.btag.I1_RNIV42K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNII81Q[3]\, Y => h_i13_NE_1); - - \r.btag.PPN_RNI9HV5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_2(2), Y => N_1217); - - \r.btag.ACC_RNIFU6U49[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - cam_hitaddr_18(1), Y => N_1464); - - \r.btag.PPN_RNI9MG8AS[9]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[17]\, Y => - pteout_m_i_8); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[25]\); - - \r.btag.M_RNIVKIVKT\ : OR2B - port map(A => WBNEEDSYNC_m_0_0, B => un1_cam_hitaddr(62), Y - => WBNEEDSYNC_m_0); - - \r.btag.LVL_RNI9PTN91[0]\ : NOR2B - port map(A => hm_1_1, B => trans_op, Y => un1_tlbcami_3); - - \r.btag.I1_RNI7Q0P1[5]\ : XA1 - port map(A => N_661, B => \un1_tag0[73]\, C => - \I1_RNINK1Q[4]\, Y => h_i13_NE_2); - - \r.btag.LVL_RNI5S2B3H[0]\ : OR2A - port map(A => \cam_hit_all_5_sqmuxa_0_a2_0\, B => N_2551, Y - => cam_hit_all_5_sqmuxa); - - \r.btag.I2_RNIHTRT1[4]\ : XA1 - port map(A => I2_1(4), B => \un1_tag0[66]\, C => - \I2_RNIR4UU[5]\, Y => h_l2_1_2); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[3]\); - - \r.btag.SU_RNI81MO1\ : OR3A - port map(A => \un1_tag0[43]\, B => SU, C => h_c2_NE, Y => - hf_4); - - \r.btag.PPN_RNIL74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[22]\, Y => - pteout_m_i_0_14); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[60]\); - - \r.btag.ET_RNI15TA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_2(2), Y => N_1202); - - \r.btag.PPN_RNIIC8B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_3(2), Y => N_1229); - - \r.btag.LVL_RNI5DEJ11[1]\ : MX2 - port map(A => hf_2_i, B => hf_1_i, S => TYP_1(0), Y => N_5); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[75]\); - - \r.btag.CTX_RNIGNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_1, Y => h_c2_1_i); - - \r.btag.PPN_RNI1MG8AS[1]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[9]\, Y => - pteout_m_i_0_d0); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_0_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[1]\); - - \r.btag.SU_RNI81MO1_0\ : OA1A - port map(A => h_c2_NE, B => SU, C => \un1_tag0[43]\, Y => - un3_hf); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[11]\); - - \r.btag.PPN_RNIMB4BAS[15]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[23]\, Y => - pteout_m_i_0_15); - - \r.btag.PPN_RNIVGV5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_2(2), Y => N_1212); - - \r.btag.PPN_RNI8S6B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_3(2), Y => N_1233); - - \r.btag.PPN_RNITGV5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_2(2), Y => N_1211); - - \r.btag.PPN_RNI4K6B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_3(2), Y => N_1222); - - \r.btag.I2_RNISI5AC[0]\ : OR2A - port map(A => h_l2_1_4, B => h_i13_NE, Y => h_l2_1); - - \r.btag.PPN_RNI5HV5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_2(2), Y => N_1215); - - \r.btag.PPN_RNI2MG8AS[2]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[10]\, Y => - pteout_m_i_1); - - \r.btag.LVL_RNI9KH2_0[0]\ : NOR2 - port map(A => \LVL[0]\, B => \LVL[1]\, Y => hf_1_0); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[20]\); - - \r.btag.PPN_RNI4MG8AS[4]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[12]\, Y => - pteout_m_i_3); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[65]\); - - \r.btag.CTX_RNIO3TN[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_0_27, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(1), - Y => M_5); - - \r.btag.I3_RNIES1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIES1Q[4]\); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[56]\); - - \r.btag.LVL_RNIV89BJI_2[0]\ : NOR2 - port map(A => \cam_hitaddr_21[0]\, B => cam_hitaddr_18(1), - Y => un1_cam_hitaddr_1_6); - - \r.btag.CTX_RNIG6QF1[0]\ : OR2B - port map(A => h_c2_NE_5, B => h_c2_NE_4, Y => h_c2_NE); - - \r.btag.PPN_RNI0MG8AS[0]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[8]\, Y => - pteout_m_i_0_0); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[70]\); - - \r.btag.PPN_RNI046B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_3(2), Y => N_1220); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[24]\); - - \r.btag.LVL_RNIS1DV8[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.I1_RNIQD3N3[0]\ : NOR3C - port map(A => \I1_RNI8G0Q[1]\, B => \I1_RNIJO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.LVL_RNIQF04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_1235); - - \r.btag.ACC_RNIT7I5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_2(2), Y => N_1204); - - \r.btag.CTX_RNIO2TN[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.PPN_RNIG48B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_3(2), Y => N_1228); - - \r.btag.M_RNIP456\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_2(2), Y => N_1208); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[40]\); - - \r.btag.PPN_RNIOJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[25]\, Y => - pteout_m_i_0_17); - - \r.btag.I3_RNI6DVU[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => I3_1_5, Y => - \I3_RNI6DVU[5]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[37]\); - - \r.btag.LVL_RNIV89BJI_0[0]\ : NOR2A - port map(A => cam_hitaddr_18(1), B => \cam_hitaddr_21[0]\, - Y => un1_cam_hitaddr_1_0); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_0_15, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[15]\); - - \r.btag.PPN_RNINF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[24]\, Y => - pteout_m_i_0_16); - - \r.btag.PPN_RNI8MG8AS[8]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[16]\, Y => - pteout_m_i_7); - - \r.btag.PPN_RNIADQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_1219); - - \r.btag.ACC_RNINHFO0S[2]\ : MX2C - port map(A => N_1465, B => N_1471, S => N_2551, Y => N_1481); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[14]\); - - \r.btag.LVL_RNIBAQU49[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_1(0), S => - cam_hitaddr_18(1), Y => N_1493); - - \r.btag.I2_RNIQJ0K1[2]\ : XA1 - port map(A => I2_1(2), B => \un1_tag0[64]\, C => - \I2_RNI1O0Q[3]\, Y => h_l2_1_1); - - \r.btag.CTX_RNIAKNA[6]\ : XA1A - port map(A => ctx_0_4, B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[7]\); - - \r.btag.CTX_RNIQJNA[2]\ : XA1A - port map(A => ctx_0_0, B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.PPN_RNI847B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_3(2), Y => N_1224); - - \r.btag.PPN_RNI6MG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[14]\, Y => - pteout_m_i_5); - - \r.btag.PPN_RNIRGV5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_2(2), Y => N_1210); - - \r.btag.LVL_RNIMDO0J[0]\ : NOR3B - port map(A => un3_hf, B => hf_1_0, C => h_l3_1, Y => hf_1_i); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \LVL[0]\); - - \r.btag.PPN_RNIES7B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_3(2), Y => N_1227); - - \r.btag.ACC_RNIS3D3[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_1(3), S => - s2_entry(2), Y => N_1205); - - \r.btag.LVL_RNILLFHR[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.PPN_RNI1HV5[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry_2(2), Y => N_1213); - - \r.btag.PPN_RNIQR4BAS[19]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[27]\, Y => - pteout_m_i_18); - - \r.btag.PPN_RNI3HV5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_2(2), Y => N_1214); - - \r.btag.I3_RNI95BR4[0]\ : NOR3C - port map(A => h_l3_1_1, B => \I3_RNI6DVU[5]\, C => h_l3_1_2, - Y => h_l3_1_4); - - \r.btag.I2_RNI6L3K1[0]\ : XA1 - port map(A => I2_1(0), B => \un1_tag0[62]\, C => - \I2_RNIN82Q[1]\, Y => h_l2_1_0); - - \r.btag.VALID_RNIQBO9E1\ : MX2C - port map(A => N_9, B => N_7_i, S => TYP_1(1), Y => hf_1_1); - - \r.btag.LVL_RNIHOMUD[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.ACC_RNIJHFO0S[1]\ : MX2C - port map(A => N_1464, B => N_1470, S => N_2551, Y => N_1480); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[30]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[74]\); - - \r.btag.I1_RNII81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNII81Q[3]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_0_12, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[12]\); - - \r.btag.CTX_RNIONI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_5, Y => h_c2_5_i); - - \r.btag.LVL_RNIV89BJI_1[0]\ : NOR2A - port map(A => \cam_hitaddr_21[0]\, B => cam_hitaddr_18(1), - Y => un1_cam_hitaddr_4_0); - - \r.btag.C_RNI5456\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_2(2), Y => N_1209); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_0_26, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_0_23, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_0_16, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => un1_tlbcami_3, B => tlbcam_write_op_1_0(1), Y - => M_1_sqmuxa); - - \r.btag.M_RNI8T1T7K3\ : OR3C - port map(A => accexc_6_4, B => accexc_6_3, C => accexc_6_5, - Y => accexc_6); - - \r.btag.PPN_RNI2C6B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_3(2), Y => N_1221); - - \r.btag.PPN_RNICK7B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_3(2), Y => N_1226); - - \r.btag.PPN_RNI5MG8AS[5]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[13]\, Y => - pteout_m_i_4); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[72]\); - - \r.btag.PPN_RNIK34BAS[13]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[21]\, Y => - pteout_m_i_0_13); - - \r.btag.M_RNIJN7OA1\ : NOR3A - port map(A => hm_1_1, B => M_1, C => \pteout[6]\, Y => - WBNEEDSYNC_m_0_0); - - \r.btag.PPN_RNI7HV5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_2(2), Y => N_1216); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.LVL_RNIO71FC7[0]\ : NOR2B - port map(A => hit, B => cam_hit_all_5_sqmuxa_2, Y => - \cam_hit_all_5_sqmuxa_0_a2_0\); - - \r.btag.PPN_RNI3MG8AS[3]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[11]\, Y => - pteout_m_i_0_3); - - \r.btag.I2_RNIR4UU[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => - \I2_RNIR4UU[5]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[73]\); - - \r.btag.PPN_RNI246B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_3(2), Y => N_1230); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[18]\); - - \r.btag.VALID_RNIRNDN8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_work_leon3mp_wfp_rtl_3 is - - port( clk : in std_logic; - address : in std_logic_vector(2 downto 0); - datain : in std_logic_vector(29 downto 0); - dataout : out std_logic_vector(29 downto 0); - enable : in std_logic; - write : in std_logic - ); - -end proasic3_syncram_work_leon3mp_wfp_rtl_3; - -architecture DEF_ARCH of proasic3_syncram_work_leon3mp_wfp_rtl_3 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ0_1 is - - port( address : in std_logic_vector(31 downto 2); - s2_entry : in std_logic_vector(2 downto 0); - twowner_1 : in std_logic_vector(0 to 0); - aaddr : inout std_logic_vector(31 downto 2) := (others => 'Z'); - dr1write_0_sqmuxa : in std_logic; - syncramZ0_1_VCC : in std_logic; - lclk_c : in std_logic; - N_709 : out std_logic - ); - -end syncramZ0_1; - -architecture DEF_ARCH of syncramZ0_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_3 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(2 downto 0) := (others => 'U'); - datain : in std_logic_vector(29 downto 0) := (others => 'U'); - dataout : out std_logic_vector(29 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \aaddr_0[7]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_3 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_3(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_3 - port map(clk => lclk_c, address(2) => s2_entry(2), - address(1) => s2_entry(1), address(0) => s2_entry(0), - datain(29) => address(31), datain(28) => address(30), - datain(27) => address(29), datain(26) => address(28), - datain(25) => address(27), datain(24) => address(26), - datain(23) => address(25), datain(22) => address(24), - datain(21) => address(23), datain(20) => address(22), - datain(19) => address(21), datain(18) => address(20), - datain(17) => address(19), datain(16) => address(18), - datain(15) => address(17), datain(14) => address(16), - datain(13) => address(15), datain(12) => address(14), - datain(11) => address(13), datain(10) => address(12), - datain(9) => address(11), datain(8) => address(10), - datain(7) => address(9), datain(6) => address(8), - datain(5) => address(7), datain(4) => address(6), - datain(3) => address(5), datain(2) => address(4), - datain(1) => address(3), datain(0) => address(2), - dataout(29) => aaddr(31), dataout(28) => aaddr(30), - dataout(27) => aaddr(29), dataout(26) => aaddr(28), - dataout(25) => aaddr(27), dataout(24) => aaddr(26), - dataout(23) => aaddr(25), dataout(22) => aaddr(24), - dataout(21) => aaddr(23), dataout(20) => aaddr(22), - dataout(19) => aaddr(21), dataout(18) => aaddr(20), - dataout(17) => aaddr(19), dataout(16) => aaddr(18), - dataout(15) => aaddr(17), dataout(14) => aaddr(16), - dataout(13) => aaddr(15), dataout(12) => aaddr(14), - dataout(11) => aaddr(13), dataout(10) => aaddr(12), - dataout(9) => aaddr(11), dataout(8) => aaddr(10), - dataout(7) => aaddr(9), dataout(6) => aaddr(8), - dataout(5) => \aaddr_0[7]\, dataout(4) => aaddr(6), - dataout(3) => aaddr(5), dataout(2) => aaddr(4), - dataout(1) => aaddr(3), dataout(0) => aaddr(2), enable - => syncramZ0_1_VCC, write => dr1write_0_sqmuxa); - - GND_i_0 : GND - port map(Y => GND_0); - - \proa3.x0_RNIRE9I\ : MX2C - port map(A => aaddr(7), B => \aaddr_0[7]\, S => - twowner_1(0), Y => N_709); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_3 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1_0 : in std_logic_vector(7 to 7); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_7 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(7 to 7); - cam_hitaddr_18 : in std_logic_vector(1 to 1); - LVL_0 : in std_logic_vector(1 to 1); - TYP_1 : in std_logic_vector(2 downto 0); - tlbcam_write_op_1_0 : in std_logic_vector(7 to 7); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - ctx_0_3 : in std_logic; - ctx_0_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - ctx_6 : in std_logic; - ctx_4 : in std_logic; - ctx_3 : in std_logic; - ctx_0_d0 : in std_logic; - ctx_1 : in std_logic; - ctx_5 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I1_1_6 : in std_logic; - I1_1_3 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_5 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_11 : in std_logic; - pteout_m_i_10 : in std_logic; - pteout_m_i_8 : in std_logic; - pteout_m_i_6 : in std_logic; - pteout_m_i_4 : in std_logic; - pteout_m_i_1 : in std_logic; - pteout_m_i_0_d0 : in std_logic; - pteout_m_i_18 : in std_logic; - pteout_m_i_3 : in std_logic; - un2_wb_acc_iv_2_11 : out std_logic; - un2_wb_acc_iv_2_10 : out std_logic; - un2_wb_acc_iv_2_8 : out std_logic; - un2_wb_acc_iv_2_6 : out std_logic; - un2_wb_acc_iv_2_4 : out std_logic; - un2_wb_acc_iv_2_1 : out std_logic; - un2_wb_acc_iv_2_0 : out std_logic; - un2_wb_acc_iv_2_18 : out std_logic; - un2_wb_acc_iv_2_3 : out std_logic; - data_1_3_i_a3_3 : in std_logic_vector(30 to 30); - data_1_3_i_a3_5 : out std_logic_vector(30 to 30); - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - pteout_m_i_0_18 : in std_logic; - pteout_m_i_0_13 : in std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_14 : out std_logic; - pteout_11 : out std_logic; - pteout_8 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_17 : out std_logic; - pteout_15 : out std_logic; - pteout_13 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_27 : out std_logic; - pteout_12 : out std_logic; - pteout_26 : out std_logic; - pteout_21 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(56 to 56); - data_1_3_i_a3_2_0 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_1498 : out std_logic; - NEEDSYNC : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - trans_op : in std_logic; - s2_flush_1 : in std_logic; - hit : out std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - WBNEEDSYNC_m : out std_logic; - N_661 : in std_logic - ); - -end mmutlbcam_2_0_3; - -architecture DEF_ARCH of mmutlbcam_2_0_3 is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \data_1_3_i_a3_2[30]\, hm_1_1_3_m8_i_1, - hf_1_1_1_a0_3_0, h_l3_1_4_i_0, hm_1_1_3_m8_i_0, h_c2_NE_4, - h_c2_NE_5, \un1_tag0[43]\, hm_1_1_3_m8_i_o5_0, h_l2_1_2, - h_l2_1_3, hf_1_1_1_a0_3_2, un3_hf, hf_1_1_1_a0_3_0_0, - hf_1_1_1_a1_2_2, hf_1_1_1_a1_2_1, h_l3_1_4_3, - \un1_tag0[61]\, h_l3_1_4_1, \I3_RNIS8291[2]\, - \I3_RNI4N55[1]\, \I3_RNIVB0Q[0]\, h_i13_NE_4, - \I1_RNIEG0Q[1]\, \I1_RNIPO091[0]\, h_i13_NE_1, h_i13_NE_3, - \un1_tag0[74]\, \I1_RNIF01Q[7]\, h_i13_NE_2, - \un1_tag0[73]\, \I1_RNITK1Q[4]\, \un1_tag0[70]\, - \I1_RNIO81Q[3]\, h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, - h_l2_1_3_0, \un1_tag0[62]\, h_i22_1, hf_4_0, SU, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, hf_3, - \un45_res[3]\, h_i13_NE, hf_4, tlbcamo_needsync, - hm_1_1_3_N_9, \I3_RNIKS1Q[4]\, \I3_RNIEG1Q[3]\, - hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, hm_1_1_3_N_14, - hm_1_1_3_N_12, \LVL[1]\, N_5, \LVL[0]\, h_i22_5, h_i22_4, - \un1_tag0[56]\, \un1_tag0[59]\, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[72]\, \un1_tag0[75]\, - \un1_tag0[35]\, \un1_tag0[36]\, \un1_tag0[38]\, - \un1_tag0[39]\, \un1_tag0[40]\, \un1_tag0[42]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[66]\, - \un1_tag0[67]\, \un1_tag0[57]\, \un1_tag0[58]\, - \un1_tag0[60]\, \un1_tag0[68]\, M_2, \pteout[6]\, M_5, - h_su_cnt_1, hf_1_1, M_1_sqmuxa, N_7, N_6, N_8, N_9, - VALID_RNO_10, N_15, \pteout[8]\, \pteout[9]\, - \pteout[10]\, \pteout[11]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[15]\, \pteout[16]\, \pteout[17]\, - \pteout[18]\, \pteout[19]\, \pteout[20]\, \pteout[21]\, - \pteout[22]\, \pteout[23]\, \pteout[24]\, \pteout[25]\, - \pteout[26]\, \pteout[27]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - pteout_6 <= \pteout[6]\; - pteout_25 <= \pteout[25]\; - pteout_24 <= \pteout[24]\; - pteout_23 <= \pteout[23]\; - pteout_22 <= \pteout[22]\; - pteout_18 <= \pteout[18]\; - pteout_16 <= \pteout[16]\; - pteout_14 <= \pteout[14]\; - pteout_11 <= \pteout[11]\; - pteout_8 <= \pteout[8]\; - pteout_20 <= \pteout[20]\; - pteout_19 <= \pteout[19]\; - pteout_17 <= \pteout[17]\; - pteout_15 <= \pteout[15]\; - pteout_13 <= \pteout[13]\; - pteout_10 <= \pteout[10]\; - pteout_9 <= \pteout[9]\; - pteout_27 <= \pteout[27]\; - pteout_12 <= \pteout[12]\; - pteout_26 <= \pteout[26]\; - pteout_21 <= \pteout[21]\; - - \r.btag.VALID_RNI43MO1\ : NOR2B - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.LVL_RNIKL872[1]\ : NOR3A - port map(A => un3_hf, B => TYP_1_0(0), C => \LVL[1]\, Y => - hf_1_1_1_a1_2_1); - - \r.btag.VALID_RNIV0TKR\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[8]\); - - \r.btag.SU_RNIUT7L1\ : AO1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \LVL[1]\); - - \r.btag.VALID_RNIIKDG71\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.CTX_RNISVAQ[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[63]\); - - \r.btag.I3_RNIVB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIVB0Q[0]\); - - \r.btag.I3_RNIEG1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNIEG1Q[3]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[19]\); - - \r.btag.VALID_RNIRDD64\ : NOR3C - port map(A => un3_hf, B => hf_1_1_1_a0_3_0_0, C => h_l2_1_2, - Y => hf_1_1_1_a0_3_2); - - \r.btag.PPN_RNIEMG8AS[8]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[16]\, Y => - pteout_m_i_7); - - \r.btag.LVL_RNIT0D5B[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1_0(0), Y => N_8); - - \r.btag.PPN_RNIUJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[25]\, Y => - pteout_m_i_0_17); - - \r.btag.PPN_RNIDN7MKO1[11]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[19]\, C => - pteout_m_i_10, Y => un2_wb_acc_iv_2_10); - - \r.btag.CTX_RNI48FL[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(7), Y => N_15); - - \r.btag.I1_RNI49BRQ[5]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.PPN_RNIHC1HKO1[4]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[12]\, C => - pteout_m_i_3, Y => un2_wb_acc_iv_2_3); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[41]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => SU); - - \r.btag.PPN_RNITN9MKO1[19]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[27]\, C => - pteout_m_i_18, Y => un2_wb_acc_iv_2_18); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[36]\); - - \r.btag.I2_RNIO9483[0]\ : NOR2 - port map(A => h_l2_1_3_1, B => h_l2_1_3_0, Y => h_l2_1_3); - - \r.btag.I3_RNIS8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIS8291[2]\); - - \r.btag.LVL_RNIC2VCB[0]\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[10]\); - - \r.btag.I3_RNI4N55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNI4N55[1]\); - - \r.btag.LVL_RNILKH2_0[0]\ : NOR2 - port map(A => \LVL[1]\, B => \LVL[0]\, Y => hf_1_1_1_a0_3_0); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNIJC1HKO1[5]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[13]\, C => - pteout_m_i_4, Y => un2_wb_acc_iv_2_4); - - \r.btag.LVL_RNIQCRF[0]\ : NOR2B - port map(A => hf_1_1_1_a0_3_0, B => TYP_1_0(0), Y => - hf_1_1_1_a0_3_0_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_28); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[21]\); - - \r.btag.CTX_RNI6KNA[2]\ : XA1A - port map(A => ctx_1, B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_10); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[66]\); - - \r.btag.CTX_RNI2G5D[6]\ : XA1A - port map(A => ctx_5, B => \un1_tag0[41]\, C => h_c2_7_i, Y - => h_c2_NE_3); - - \r.btag.I1_RNIM41K1[6]\ : XA1 - port map(A => I1_1_5, B => \un1_tag0[74]\, C => - \I1_RNIF01Q[7]\, Y => h_i13_NE_3); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[68]\); - - \r.btag.PPN_RNIH78MKO1[13]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[21]\, C => - pteout_m_i_0_13, Y => data_1_3_i_a3_2_0); - - \r.btag.LVL_RNIHJ454[1]\ : NOR2B - port map(A => hf_1_1_1_a1_2_1, B => h_l2_1_2, Y => - hf_1_1_1_a1_2_2); - - \r.btag.CTX_RNIMNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_d0, Y => h_c2_1_i); - - \r.btag.I2_RNI15UU[5]\ : XNOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => h_i22_5); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[22]\); - - \r.btag.SU_RNI4RR8\ : NOR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_2); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_29); - - \r.btag.LVL_RNIRFEBC[1]\ : AO1A - port map(A => h_i13_NE, B => hm_1_1_3_m8_i_o5_0, C => - \LVL[1]\, Y => hm_1_1_3_N_12); - - \r.btag.CTX_RNISNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_3, Y => h_c2_4_i); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_10, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.I2_RNI6K0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_4); - - \r.btag.LVL_RNIK5DV8[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.VALID_RNI0US9C\ : OR3B - port map(A => hf_1_1_1_a0_3_2, B => h_l2_1_3, C => - h_l3_1_4_i_0, Y => hf_1_1_1_a0_3_i); - - \r.btag.PPN_RNICMG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[14]\, Y => - pteout_m_i_5); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[25]\); - - \r.btag.PPN_RNIBC1HKO1[1]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[9]\, C => - pteout_m_i_0_d0, Y => un2_wb_acc_iv_2_0); - - \r.btag.I3_RNIKS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIKS1Q[4]\); - - \r.btag.I1_RNIB52K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIO81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I3_RNID6BR4[3]\ : OR3C - port map(A => \I3_RNIKS1Q[4]\, B => \I3_RNIEG1Q[3]\, C => - h_l3_1_4_3, Y => h_l3_1_4_i_0); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_3); - - \r.btag.I1_RNIRD547[5]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[60]\); - - \r.btag.LVL_RNILKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[75]\); - - \r.btag.I2_RNISOTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.CTX_RNIUNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_4, Y => h_c2_5_i); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_1); - - \r.btag.CTX_RNIES44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.PPN_RNIR74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[22]\, Y => - pteout_m_i_0_14); - - \r.btag.M_RNIM09FR\ : OR3B - port map(A => trans_op, B => tlbcamo_needsync, C => - hm_1_1_3_N_9, Y => NEEDSYNC); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[11]\); - - \r.btag.I1_RNIPO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIPO091[0]\); - - \r.btag.I1_RNIO81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIO81Q[3]\); - - \r.btag.PPN_RNIRF9MKO1[18]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[26]\, C => - pteout_m_i_0_18, Y => \data_1_3_i_a3_2[30]\); - - \r.btag.I1_RNITK1Q[4]\ : XOR2 - port map(A => \un1_tag0[72]\, B => I1_1_3, Y => - \I1_RNITK1Q[4]\); - - \r.btag.LVL_RNI8022Q[0]\ : OR3C - port map(A => hm_1_1_3_m8_i_1, B => hm_1_1_3_N_14, C => - hm_1_1_3_N_12, Y => hm_1_1_3_N_9); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_0); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[20]\); - - \r.btag.PPN_RNIFV7MKO1[12]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[20]\, C => - pteout_m_i_11, Y => un2_wb_acc_iv_2_11); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_31); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[65]\); - - \r.btag.I1_RNIIE3N3[0]\ : NOR3C - port map(A => \I1_RNIEG0Q[1]\, B => \I1_RNIPO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(7), - Y => M_5); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[56]\); - - \r.btag.PPN_RNINN3BAS[10]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[18]\, Y => - pteout_m_i_9); - - \r.btag.I2_RNITTRT1[4]\ : NOR2 - port map(A => h_i22_5, B => h_i22_4, Y => h_l2_1_2); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNI9MG8AS[3]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[11]\, Y => - pteout_m_i_0_3); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[70]\); - - \r.btag.I1_RNIJQ0P1[5]\ : XA1 - port map(A => N_661, B => \un1_tag0[73]\, C => - \I1_RNITK1Q[4]\, Y => h_i13_NE_2); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[24]\); - - \r.btag.I2_RNIIL3K1[0]\ : XO1A - port map(A => I2_1(0), B => \un1_tag0[62]\, C => h_i22_1, Y - => h_l2_1_3_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.M_RNI3D5G5T\ : OR3B - port map(A => tlbcamo_needsync, B => un1_cam_hitaddr(56), C - => hm_1_1_3_N_9, Y => WBNEEDSYNC_m); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[40]\); - - \r.btag.LVL_RNI9T8D7[1]\ : OR2B - port map(A => hf_1_1_1_a1_2_2, B => h_l2_1_3, Y => - hf_1_1_1_a1_2_i); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[37]\); - - \r.btag.M_RNIFFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => tlbcamo_needsync); - - \r.btag.VALID_RNI6D8J1\ : NOR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_1_1_3_m8_i_0); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[15]\); - - \r.btag.CTX_RNI8S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_0, Y => h_c2_0_i); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_7); - - \r.btag.I1_RNIEG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNIEG0Q[1]\); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \LVL[0]\); - - \r.btag.VALID_RNICMVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.PPN_RNITF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[24]\, Y => - pteout_m_i_0_16); - - \r.btag.PPN_RNI6MG8AS[0]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[8]\, Y => - pteout_m_i_0_0); - - \r.btag.SU_RNI43MO1\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => hf_4_0, Y => - hf_4); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_30); - - \r.btag.PPN_RNINC1HKO1[7]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[15]\, C => - pteout_m_i_6, Y => un2_wb_acc_iv_2_6); - - \r.btag.I3_RNIBP773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_4_1, - Y => h_l3_1_4_3); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[12]\); - - \r.btag.PPN_RNIDC1HKO1[2]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[10]\, C => - pteout_m_i_1, Y => un2_wb_acc_iv_2_1); - - \r.btag.LVL_RNI58E57[0]\ : OR2A - port map(A => h_i13_NE, B => \LVL[0]\, Y => hm_1_1_3_N_14); - - \r.btag.VALID_RNI885H6\ : AOI1B - port map(A => hf_1_1_1_a0_3_0, B => h_l3_1_4_i_0, C => - hm_1_1_3_m8_i_0, Y => hm_1_1_3_m8_i_1); - - \r.btag.I2_RNIT82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.PPN_RNIJVIC9H3[18]\ : NOR2B - port map(A => \data_1_3_i_a3_2[30]\, B => - data_1_3_i_a3_3(30), Y => data_1_3_i_a3_5(30)); - - \r.btag.PPN_RNIRC1HKO1[9]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[17]\, C => - pteout_m_i_8, Y => un2_wb_acc_iv_2_8); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[16]\); - - \r.btag.I1_RNIF01Q[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => I1_1_6, Y => - \I1_RNIF01Q[7]\); - - \r.btag.M_RNO_0\ : OA1C - port map(A => trans_op, B => hm_1_1_3_N_9, C => - tlbcam_write_op_1_0(7), Y => M_1_sqmuxa); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[72]\); - - \r.btag.LVL_RNIS87P12[0]\ : AO1B - port map(A => hf_1_1, B => s2_flush_1, C => hm_1_1_3_N_9, Y - => hit); - - \r.btag.I2_RNI7O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.I3_RNIVB882[0]\ : NOR3C - port map(A => \I3_RNIS8291[2]\, B => \I3_RNI4N55[1]\, C => - \I3_RNIVB0Q[0]\, Y => h_l3_1_4_1); - - \r.btag.CTX_RNI2OI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_6, Y => h_c2_7_i); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.PPN_RNISB4BAS[15]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[23]\, Y => - pteout_m_i_0_15); - - \r.btag.LVL_RNILAQU49[1]\ : MX2C - port map(A => LVL_0(1), B => \LVL[1]\, S => - cam_hitaddr_18(1), Y => N_1498); - - \r.btag.I2_RNIL7065[0]\ : NOR2B - port map(A => h_l2_1_2, B => h_l2_1_3, Y => - hm_1_1_3_m8_i_o5_0); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_6 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - data_0_18 : in std_logic; - data_0_11 : in std_logic; - data_0_10 : in std_logic; - data_0_6 : in std_logic; - data_0_4 : in std_logic; - data_0_3 : in std_logic; - data_0_1 : in std_logic; - data_0_0 : in std_logic; - tlbcam_write_op_1_1_0 : in std_logic_vector(2 to 2); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_23 : in std_logic; - hrdata_16 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(2 to 2); - TYP_1_2 : in std_logic; - TYP_1_0_d0 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - LVL_RNIT69H911 : in std_logic_vector(0 to 0); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - data_21 : in std_logic; - data_20 : in std_logic; - data_19 : in std_logic; - data_18 : in std_logic; - data_17 : in std_logic; - data_16 : in std_logic; - data_13 : in std_logic; - data_12 : in std_logic; - data_11 : in std_logic; - data_9 : in std_logic; - data_6 : in std_logic; - data_3 : in std_logic; - data_7 : in std_logic; - data_0_d0 : in std_logic; - data_22 : in std_logic; - data_8 : in std_logic; - data_15 : in std_logic; - data_5 : in std_logic; - data_4 : in std_logic; - data_14 : in std_logic; - data_10 : in std_logic; - un1_m0_2_0 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_3 : out std_logic; - I3_1_i_0_0 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_2 : in std_logic_vector(2 to 2); - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - s2_entry_1 : in std_logic_vector(2 to 2); - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - tlbcam_write_op_1_0 : in std_logic_vector(2 to 2); - cam_hitaddr_18 : out std_logic_vector(1 to 1); - un2_wb_acc_iv_4_3 : in std_logic; - un2_wb_acc_iv_4_18 : in std_logic; - un2_wb_acc_iv_4_0 : in std_logic; - un2_wb_acc_iv_4_1 : in std_logic; - un2_wb_acc_iv_4_4 : in std_logic; - un2_wb_acc_iv_4_6 : in std_logic; - un2_wb_acc_iv_4_10 : in std_logic; - un2_wb_acc_iv_4_11 : in std_logic; - ctx : in std_logic_vector(7 downto 0); - I2_1 : in std_logic_vector(5 downto 0); - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - un2_wb_acc_iv_2_3 : in std_logic; - un2_wb_acc_iv_2_18 : in std_logic; - un2_wb_acc_iv_2_0 : in std_logic; - un2_wb_acc_iv_2_1 : in std_logic; - un2_wb_acc_iv_2_4 : in std_logic; - un2_wb_acc_iv_2_6 : in std_logic; - un2_wb_acc_iv_2_10 : in std_logic; - un2_wb_acc_iv_2_11 : in std_logic; - un2_wb_acc_iv_2_8 : in std_logic; - pteout_m_i_1_2 : in std_logic; - pteout_m_i_1_0 : in std_logic; - un2_wb_acc_iv_5 : out std_logic_vector(18 downto 16); - un2_wb_acc_iv_3_5 : out std_logic; - pteout_m_i_11 : in std_logic; - pteout_m_i_10 : in std_logic; - pteout_m_i_9 : in std_logic; - pteout_m_i_8 : in std_logic; - pteout_m_i_7 : in std_logic; - pteout_m_i_6 : in std_logic; - pteout_m_i_4 : in std_logic; - pteout_m_i_1_d0 : in std_logic; - pteout_m_i_0_d0 : in std_logic; - pteout_m_i_18 : in std_logic; - pteout_m_i_3 : in std_logic; - pteout_m_i_0_1_0 : in std_logic; - pteout_m_i_0_1_15 : in std_logic; - pteout_m_i_0_0_0 : in std_logic; - pteout_m_i_0_0_16 : in std_logic; - pteout_m_i_0_0_15 : in std_logic; - pteout_m_i_0_0_17 : in std_logic; - pteout_m_i_0_0_14 : in std_logic; - pteout_m_i_0_0_18 : in std_logic; - data_1_3_i_a3_3_3 : out std_logic; - data_1_3_i_a3_3_4 : out std_logic; - data_1_3_i_a3_3_1 : out std_logic; - data_1_3_i_a3_3_5 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(61 to 61); - data_1_3_i_a3_2 : in std_logic_vector(25 to 25); - data_1_3_i_a3_5_2 : out std_logic; - data_1_3_i_a3_5_0 : out std_logic; - pteout_m_i_0_10 : in std_logic; - pteout_m_i_0_8 : in std_logic; - pteout_m_i_0_6 : in std_logic; - pteout_m_i_0_0_d0 : in std_logic; - pteout_m_i_0_15 : in std_logic; - pteout_m_i_0_13 : in std_logic; - pteout_m_i_0_3 : in std_logic; - data_1_3_i_a3_0_2 : in std_logic_vector(15 to 15); - data_1_3_i_a3_0_5_0 : out std_logic; - data_1_3_i_a3_0_5_3 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_1138 : out std_logic; - cam_hit_all_5_sqmuxa_2 : out std_logic; - N_1151 : out std_logic; - N_1154 : out std_logic; - s2_flush : in std_logic; - N_1137 : out std_logic; - NEEDSYNC : out std_logic; - N_1167 : out std_logic; - un1_rst_i_0 : in std_logic; - N_696 : out std_logic; - N_695 : out std_logic; - N_2709_i_0 : in std_logic; - N_694 : out std_logic; - trans_op : in std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_1513 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - N_1166 : out std_logic; - N_1165 : out std_logic; - N_1164 : out std_logic; - N_1163 : out std_logic; - N_1162 : out std_logic; - N_1161 : out std_logic; - N_1160 : out std_logic; - N_1159 : out std_logic; - N_1158 : out std_logic; - N_1157 : out std_logic; - N_1156 : out std_logic; - N_1155 : out std_logic; - N_1153 : out std_logic; - N_1152 : out std_logic; - N_1150 : out std_logic; - N_1149 : out std_logic; - N_1148 : out std_logic; - N_1147 : out std_logic; - N_1146 : out std_logic; - N_1145 : out std_logic; - N_1144 : out std_logic; - N_1143 : out std_logic; - N_1142 : out std_logic; - N_1141 : out std_logic; - N_1140 : out std_logic; - N_1136 : out std_logic; - N_1135 : out std_logic; - N_1134 : out std_logic; - s2_flush_0 : in std_logic; - hit_1 : in std_logic; - hit_0 : in std_logic; - hit : in std_logic; - WBNEEDSYNC_m : in std_logic; - accexc_6_3 : out std_logic - ); - -end mmutlbcam_2_0_6; - -architecture DEF_ARCH of mmutlbcam_2_0_6 is - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \data_1_3_i_a3_0_3[15]\, \pteout_m_i_0_0[11]\, - \data_1_3_i_a3_3[25]\, \pteout[21]\, \pteout_m_i_0[26]\, - \pteout_m_i_0[22]\, \pteout_m_i_0[25]\, - \data_1_3_i_a3_3[27]\, \pteout[23]\, \pteout_m_i_0[24]\, - \data_1_3_i_a3_0_3[12]\, \pteout[8]\, WBNEEDSYNC_m_0, - \un2_wb_acc_iv_3[12]\, \pteout[12]\, - \un2_wb_acc_iv_3[27]\, \pteout[27]\, \un2_wb_acc_iv_3[9]\, - \pteout[9]\, \un2_wb_acc_iv_3[10]\, \pteout[10]\, - \un2_wb_acc_iv_3[13]\, \pteout[13]\, \pteout_m_i[14]\, - \un2_wb_acc_iv_3[15]\, \pteout[15]\, - \un2_wb_acc_iv_3[16]\, \pteout[16]\, - \un2_wb_acc_iv_3[17]\, \pteout[17]\, - \un2_wb_acc_iv_3[18]\, \pteout[18]\, - \un2_wb_acc_iv_3[19]\, \pteout[19]\, - \un2_wb_acc_iv_3[20]\, \pteout[20]\, tlbcamo_needsync, - hm_1_1, \cam_hitaddr_18_0[1]\, un18_hm, hf_1_1_1_a0_3_3, - un3_hf, hf_1_1_1_a0_3_1, h_l2_1_2, hf_1_1_1_a1_2_1, - hf_1_1_1_a1_2_0, \LVL[1]\, h_l3_1_4_3, \un1_tag0[61]\, - h_l3_1_4_1, \I3_RNIN8291[2]\, \I3_RNIVM55[1]\, - \I3_RNIQB0Q[0]\, h_i13_NE_4, \I1_RNI9G0Q[1]\, - \I1_RNIKO091[0]\, h_i13_NE_1, h_i13_NE_3, \un1_tag0[75]\, - \I1_RNI240Q[6]\, h_i13_NE_2, \un1_tag0[72]\, - \I1_RNIH5VU[5]\, \un1_tag0[70]\, \I1_RNIJ81Q[3]\, - h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, hf_4_0, - \un1_tag0[43]\, SU, h_c2_NE_5, h_c2_5_i, h_c2_4_i, - h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, - h_l2_1, h_l2_1_3, h_i13_NE, hm_1, h_l3_1_4_i, hm_4, - \un2_wb_acc[20]\, \un2_wb_acc[19]\, \un2_wb_acc[15]\, - \un2_wb_acc[13]\, \un2_wb_acc[10]\, \un2_wb_acc[9]\, - \un2_wb_acc[27]\, hf_4, hf_3, \un45_res[3]\, - \un2_wb_acc[12]\, h_i22_1, h_i22_0, \I3_RNIFS1Q[4]\, - \I3_RNI9G1Q[3]\, hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, hm_3, - N_5, \un1_tag0[67]\, h_i22_4, N_15, \un1_tag0[56]\, - \un1_tag0[59]\, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[74]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \pteout[0]\, \pteout[1]\, \pteout[6]\, - \pteout[7]\, \pteout[11]\, \pteout[14]\, \pteout[22]\, - \pteout[24]\, \pteout[25]\, \pteout[26]\, \pteout[28]\, - \pteout[29]\, \pteout[30]\, \pteout[31]\, \LVL[0]\, - \un1_tag0[62]\, \un1_tag0[63]\, \un1_tag0[65]\, - \un1_tag0[57]\, \un1_tag0[58]\, \un1_tag0[60]\, - \un1_tag0[68]\, \un1_tag0[73]\, M_2, M_5, h_su_cnt_1, - M_1_sqmuxa, N_1, N_3, VALID_RNO_13, N_6, hf_1_1, N_7, N_9, - N_8, \un1_tag0[66]\, \pteout[2]\, \pteout[3]\, - \pteout[4]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - pteout_4 <= \pteout[4]\; - pteout_3 <= \pteout[3]\; - pteout_2 <= \pteout[2]\; - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - - \r.btag.LVL_RNIBKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.LVL_RNI8P849[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.PPN_RNIIN8MKO1[15]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[23]\, C => - pteout_m_i_0_1_15, Y => \data_1_3_i_a3_3[27]\); - - \r.btag.CTX_RNINNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx(4), Y => h_c2_4_i); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[8]\); - - \r.btag.LVL_RNIGCRF[0]\ : NOR3A - port map(A => TYP_1_0(0), B => \LVL[1]\, C => \LVL[0]\, Y - => hf_1_1_1_a0_3_1); - - \r.btag.PPN_RNIUB5B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_1(2), Y => N_1153); - - \r.btag.I2_RNI2O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.PPN_RNI01V5[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry_1(2), Y => N_1145); - - \r.btag.I2_RNIO82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \LVL[1]\); - - \r.btag.PPN_RNIKDO5LO3[4]\ : MX2 - port map(A => data_7, B => \un2_wb_acc[12]\, S => - N_2709_i_0, Y => un1_m0_2_0); - - \r.btag.PPN_RNIDC7B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_2(2), Y => N_1159); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data_0_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[63]\); - - \r.btag.I1_RNI9Q0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIH5VU[5]\, Y => h_i13_NE_2); - - \r.btag.LVL_RNIGO5R05[0]\ : NOR3A - port map(A => hm_1_1, B => un18_hm, C => hit, Y => - \cam_hitaddr_18_0[1]\); - - \r.btag.I1_RNI9G0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNI9G0Q[1]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[19]\); - - \r.btag.PPN_RNIGC1HKO1[5]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[13]\, C => - pteout_m_i_4, Y => \un2_wb_acc_iv_3[13]\); - - \r.btag.LVL_RNIQE20A1[0]\ : MX2 - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.LVL_RNIK47RR[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.PPN_RNIJUEC9H3[10]\ : NOR3C - port map(A => pteout_m_i_9, B => pteout_m_i_0_10, C => - \un2_wb_acc_iv_3[18]\, Y => un2_wb_acc_iv_5(18)); - - \r.btag.CTX_RNITNI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx(7), Y => h_c2_7_i); - - \r.btag.PPN_RNI9S6B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_2(2), Y => N_1157); - - \r.btag.VALID_RNI1F4T71\ : MX2C - port map(A => N_7, B => N_9, S => data_0_d0, Y => hf_1_1); - - \r.btag.PPN_RNIFK7B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_2(2), Y => N_1160); - - \r.btag.M_RNI3F9DB1\ : OR3B - port map(A => trans_op, B => tlbcamo_needsync, C => hm_1_1, - Y => NEEDSYNC); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data_0_10, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(2), Y => N_15); - - \r.btag.PPN_RNILGT7BN2[5]\ : OR3C - port map(A => \un2_wb_acc_iv_3[13]\, B => un2_wb_acc_iv_2_4, - C => un2_wb_acc_iv_4_4, Y => \un2_wb_acc[13]\); - - \r.btag.LVL_RNILA4C2[1]\ : NOR2B - port map(A => hf_1_1_1_a1_2_0, B => un3_hf, Y => - hf_1_1_1_a1_2_1); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNIKV8MKO1[16]\ : NOR2B - port map(A => \pteout_m_i_0[24]\, B => pteout_m_i_0_0_16, Y - => data_1_3_i_a3_3_3); - - \r.btag.LVL_RNI0HOEC[0]\ : OR3B - port map(A => hf_1_1_1_a0_3_3, B => h_l2_1_3, C => - h_l3_1_4_i, Y => hf_1_1_1_a0_3_i); - - \r.btag.PPN_RNIB47B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_2(2), Y => N_1158); - - \r.btag.CTX_RNI8F5D[2]\ : XA1A - port map(A => ctx(2), B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.PPN_RNIAC1HKO1[2]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[10]\, C => - pteout_m_i_1_d0, Y => \un2_wb_acc_iv_3[10]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => SU); - - \r.btag.ACC_RNISNH5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_1(2), Y => N_1136); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data_9, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[62]\); - - \r.btag.I2_RNISJ0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[36]\); - - \r.btag.CTX_RNI8VAQ[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIJP229H3[9]\ : NOR2B - port map(A => un2_wb_acc_iv_2_8, B => \un2_wb_acc_iv_3[17]\, - Y => un2_wb_acc_iv_5(17)); - - \r.btag.PPN_RNIPJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[25]\, Y => - \pteout_m_i_0[25]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[10]\); - - \r.btag.LVL_RNI74UNB[0]\ : OR2B - port map(A => N_8, B => TYP_1_2, Y => N_9); - - \r.btag.PPN_RNI4MG8AS[3]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[11]\, Y => - \pteout_m_i_0_0[11]\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[57]\); - - \r.btag.PPN_RNICLIQLO3[12]\ : MX2 - port map(A => data_15, B => \un2_wb_acc[20]\, S => - LVL_RNIT69H911(0), Y => N_696); - - \r.btag.PPN_RNIE78MKO1[13]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[21]\, C => - pteout_m_i_0_13, Y => \data_1_3_i_a3_3[25]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNIOF9MKO1[18]\ : NOR2B - port map(A => \pteout_m_i_0[26]\, B => pteout_m_i_0_0_18, Y - => data_1_3_i_a3_3_5); - - \r.btag.PPN_RNITTUSBN2[19]\ : OR3C - port map(A => \un2_wb_acc_iv_3[27]\, B => - un2_wb_acc_iv_2_18, C => un2_wb_acc_iv_4_18, Y => - \un2_wb_acc[27]\); - - \r.btag.I3_RNIN8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIN8291[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.M_RNI4UQ6B1\ : NOR2A - port map(A => tlbcamo_needsync, B => hm_1_1, Y => - WBNEEDSYNC_m_0); - - \r.btag.I3_RNIVM55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNIVM55[1]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_0_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[21]\); - - \r.btag.PPN_RNITFT7BN2[2]\ : OR3C - port map(A => \un2_wb_acc_iv_3[10]\, B => un2_wb_acc_iv_2_1, - C => un2_wb_acc_iv_4_1, Y => \un2_wb_acc[10]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data_0_1, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => un1_rst_i_0, B => N_15, Y => VALID_RNO_13); - - \r.btag.PPN_RNI8C1HKO1[1]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[9]\, C => - pteout_m_i_0_d0, Y => \un2_wb_acc_iv_3[9]\); - - \r.btag.PPN_RNIM0O5LO3[1]\ : MX2 - port map(A => data_4, B => \un2_wb_acc[9]\, S => N_2709_i_0, - Y => N_694); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data_13, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[66]\); - - \r.btag.PPN_RNI3S5B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_2(2), Y => N_1163); - - \r.btag.CTX_RNI8UAQ[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.LVL_RNI1GI3E[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.PPN_RNIGF8MKO1[14]\ : NOR2B - port map(A => \pteout_m_i_0[22]\, B => pteout_m_i_0_0_14, Y - => data_1_3_i_a3_3_1); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data_0_11, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[68]\); - - \r.btag.CTX_RNIPNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx(5), Y => h_c2_5_i); - - \r.btag.ACC_RNI04D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_1138); - - \r.btag.PPN_RNIGI9QO51[11]\ : MX2 - port map(A => \un2_wb_acc[19]\, B => data_14, S => N_1513, - Y => un1_m0_2_7); - - \r.btag.PPN_RNIFO229H3[0]\ : NOR3C - port map(A => pteout_m_i_0_0_d0, B => pteout_m_i_0_0_0, C - => \data_1_3_i_a3_0_3[12]\, Y => data_1_3_i_a3_0_5_0); - - \r.btag.I2_RNIVE25R[5]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.PPN_RNIQN9MKO1[19]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[27]\, C => - pteout_m_i_18, Y => \un2_wb_acc_iv_3[27]\); - - \r.btag.PPN_RNIU0V5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_1(2), Y => N_1144); - - \r.btag.PPN_RNIOF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[24]\, Y => - \pteout_m_i_0[24]\); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_0_22, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[22]\); - - \r.btag.I3_RNIGB882[0]\ : NOR3C - port map(A => \I3_RNIN8291[2]\, B => \I3_RNIVM55[1]\, C => - \I3_RNIQB0Q[0]\, Y => h_l3_1_4_1); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[2]\); - - \r.btag.PPN_RNIDGT7BN2[4]\ : OR3C - port map(A => \un2_wb_acc_iv_3[12]\, B => un2_wb_acc_iv_2_3, - C => un2_wb_acc_iv_4_3, Y => \un2_wb_acc[12]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[29]\); - - \r.btag.PPN_RNI7C6B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_2(2), Y => N_1165); - - \r.btag.ET_RNI0LSA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_1(2), Y => N_1134); - - \r.btag.PPN_RNIFP229H3[8]\ : NOR3C - port map(A => pteout_m_i_7, B => pteout_m_i_0_8, C => - \un2_wb_acc_iv_3[16]\, Y => un2_wb_acc_iv_5(16)); - - \r.btag.I2_RNIAJ5AC[5]\ : OR3B - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE, Y => - h_l2_1); - - \r.btag.PPN_RNI546B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_2(2), Y => N_1164); - - \r.btag.M_RNIOK46\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_1(2), Y => N_1140); - - \r.btag.PPN_RNI3CH5O51[7]\ : MX2 - port map(A => \un2_wb_acc[15]\, B => data_10, S => N_1513, - Y => un1_m0_2_3); - - \r.btag.LVL_RNID29B4[0]\ : NOR3C - port map(A => un3_hf, B => hf_1_1_1_a0_3_1, C => h_l2_1_2, - Y => hf_1_1_1_a0_3_3); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data_11, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_13, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[4]\); - - \r.btag.I1_RNI152K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIJ81Q[3]\, Y => h_i13_NE_1); - - \r.btag.SU_RNIAOHT1\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => hf_4_0, Y => - hf_4); - - \r.btag.CTX_RNIOF5D[6]\ : XA1A - port map(A => ctx(6), B => \un1_tag0[41]\, C => h_c2_7_i, Y - => h_c2_NE_3); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[25]\); - - \r.btag.VALID_RNIAOHT1\ : NOR2B - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.I1_RNIC41K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI240Q[6]\, Y => h_i13_NE_3); - - \r.btag.PPN_RNIQN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[26]\, Y => - \pteout_m_i_0[26]\); - - \r.btag.PPN_RNICC1HKO1[3]\ : AND2 - port map(A => pteout_m_i_0_3, B => \pteout_m_i_0_0[11]\, Y - => \data_1_3_i_a3_0_3[15]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[3]\); - - \r.btag.M_RNIMS899R1\ : AOI1B - port map(A => WBNEEDSYNC_m_0, B => un1_cam_hitaddr(61), C - => WBNEEDSYNC_m, Y => accexc_6_3); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.PPN_RNIQ0V5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_1(2), Y => N_1142); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[1]\); - - \r.btag.LVL_RNIIV1DK4[0]\ : NOR3A - port map(A => hm_1_1, B => un18_hm, C => hit_1, Y => - cam_hit_all_5_sqmuxa_2); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[11]\); - - \r.btag.LVL_RNITJ56[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_2(2), - Y => N_1166); - - \r.btag.SU_RNIQQR8\ : NOR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.I3_RNI9G1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNI9G1Q[3]\); - - \r.btag.I3_RNIF5BR4[3]\ : OR3C - port map(A => \I3_RNIFS1Q[4]\, B => \I3_RNI9G1Q[3]\, C => - h_l3_1_4_3, Y => h_l3_1_4_i); - - \r.btag.PPN_RNI61V5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_1(2), Y => N_1148); - - \r.btag.LVL_RNI1M8S49[0]\ : OR3A - port map(A => \cam_hitaddr_18_0[1]\, B => hit_0, C => hit_1, - Y => cam_hitaddr_18(1)); - - \r.btag.I3_RNINO773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_4_1, - Y => h_l3_1_4_3); - - \r.btag.PPN_RNITRMSBN2[11]\ : OR3C - port map(A => \un2_wb_acc_iv_3[19]\, B => - un2_wb_acc_iv_2_10, C => un2_wb_acc_iv_4_10, Y => - \un2_wb_acc[19]\); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data_12, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[65]\); - - \r.btag.I1_RNIUD3N3[0]\ : NOR3C - port map(A => \I1_RNI9G0Q[1]\, B => \I1_RNIKO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN_RNICV7MKO1[12]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[20]\, C => - pteout_m_i_11, Y => \un2_wb_acc_iv_3[20]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_0_27, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(2), - Y => M_5); - - \r.btag.ET_RNI2TSA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_1(2), Y => N_1135); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data_3, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[56]\); - - \r.btag.CTX_RNIFNI6[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx(0), Y => h_c2_0_i); - - \r.btag.I1_RNIJC547[4]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.PPN_RNI41V5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_1(2), Y => N_1147); - - \r.btag.I1_RNIKO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIKO091[0]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data_18, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNIEC1HKO1[4]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[12]\, C => - pteout_m_i_3, Y => \un2_wb_acc_iv_3[12]\); - - \r.btag.LVL_RNISF04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_1167); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data_17, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[70]\); - - \r.btag.PPN_RNI21V5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_1(2), Y => N_1146); - - \r.btag.I3_RNIQB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIQB0Q[0]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[24]\); - - \r.btag.VALID_RNI4F9S8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.VALID_RNI3S3581\ : NOR2B - port map(A => hf_1_1, B => s2_flush, Y => un18_hm); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data_16, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[40]\); - - \r.btag.VALID_RNIH24O1\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_4); - - \r.btag.I2_RNIGC1Q[0]\ : XNOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => h_i22_0); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[37]\); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_0_15, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[15]\); - - \r.btag.PPN_RNI5VPQLO3[19]\ : MX2 - port map(A => data_22, B => \un2_wb_acc[27]\, S => - LVL_RNIT69H911(0), Y => un1_m0_2_15); - - \r.btag.PPN_RNIA1V5[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_1(2), Y => N_1150); - - \r.btag.CTX_RNIHNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx(1), Y => h_c2_1_i); - - \r.btag.PPN_RNIS0V5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_1(2), Y => N_1143); - - \r.btag.PPN_RNI446B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_1(2), Y => N_1156); - - \r.btag.VALID_RNIARKTI\ : NOR3 - port map(A => h_l3_1_4_i, B => hm_4, C => h_l2_1, Y => hm_1); - - \r.btag.I2_RNIJTRT1[5]\ : XA1B - port map(A => I2_1(5), B => \un1_tag0[67]\, C => h_i22_4, Y - => h_l2_1_2); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[14]\); - - \r.btag.PPN_RNIM74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[22]\, Y => - \pteout_m_i_0[22]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[7]\); - - \r.btag.I1_RNIH5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIH5VU[5]\); - - \r.btag.PPN_RNIMC1HKO1[8]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[16]\, C => - pteout_m_i_1_0, Y => \un2_wb_acc_iv_3[16]\); - - \r.btag.I2_RNI49483[0]\ : NOR3 - port map(A => h_i22_1, B => h_i22_0, C => h_l2_1_3_1, Y => - h_l2_1_3); - - \r.btag.PPN_RNIKC1HKO1[7]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[15]\, C => - pteout_m_i_6, Y => \un2_wb_acc_iv_3[15]\); - - \r.btag.PPN_RNI5HT7BN2[7]\ : OR3C - port map(A => \un2_wb_acc_iv_3[15]\, B => un2_wb_acc_iv_2_6, - C => un2_wb_acc_iv_4_6, Y => \un2_wb_acc[15]\); - - \r.btag.C_RNI4K46\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_1(2), Y => N_1141); - - \r.btag.VALID_RNI7MVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1_0_d0, Y => N_6); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \LVL[0]\); - - \r.btag.PPN_RNIVEGC9H3[13]\ : NOR2B - port map(A => data_1_3_i_a3_2(25), B => - \data_1_3_i_a3_3[25]\, Y => data_1_3_i_a3_5_0); - - \r.btag.PPN_RNIUHO5LO3[5]\ : MX2 - port map(A => data_8, B => \un2_wb_acc[13]\, S => - N_2709_i_0, Y => un1_m0_2_1); - - \r.btag.PPN_RNIAN7MKO1[11]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[19]\, C => - pteout_m_i_10, Y => \un2_wb_acc_iv_3[19]\); - - \r.btag.LVL_RNIO2CGB[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1_0_d0, Y => N_8); - - \r.btag.PPN_RNIS35B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_1(2), Y => N_1152); - - \r.btag.PPN_RNI7FHC9H3[15]\ : NOR3C - port map(A => pteout_m_i_0_15, B => pteout_m_i_0_0_15, C - => \data_1_3_i_a3_3[27]\, Y => data_1_3_i_a3_5_2); - - \r.btag.I1_RNIJ81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIJ81Q[3]\); - - \r.btag.PPN_RNIIC1HKO1[6]\ : NOR2B - port map(A => \pteout_m_i[14]\, B => pteout_m_i_0_6, Y => - un2_wb_acc_iv_3_5); - - \r.btag.PPN_RNI0019[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry(2), Y => N_1154); - - \r.btag.VALID_RNIL6KUR\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1_2, Y => N_7); - - \r.btag.PPN_RNIHS7B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_2(2), Y => N_1161); - - \r.btag.M_RNIAFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => tlbcamo_needsync); - - \r.btag.PPN_RNICDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_1151); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[13]\); - - \r.btag.I1_RNI240Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI240Q[6]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[30]\); - - \r.btag.I2_RNICH4I7[5]\ : OR3C - port map(A => h_l2_1_2, B => hf_1_1_1_a1_2_1, C => h_l2_1_3, - Y => hf_1_1_1_a1_2_i); - - \r.btag.PPN_RNI3LO5LO3[2]\ : MX2 - port map(A => data_5, B => \un2_wb_acc[10]\, S => - N_2709_i_0, Y => N_695); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_0_12, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[12]\); - - \r.btag.PPN_RNIRO229H3[3]\ : AND2 - port map(A => \data_1_3_i_a3_0_3[15]\, B => - data_1_3_i_a3_0_2(15), Y => data_1_3_i_a3_0_5_3); - - \r.btag.SU_RNI9J3Q1\ : AO1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_0_26, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_0_23, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_0_16, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : OA1C - port map(A => trans_op, B => hm_1_1, C => - tlbcam_write_op_1_0(2), Y => M_1_sqmuxa); - - \r.btag.PPN_RNIOC1HKO1[9]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[17]\, C => - pteout_m_i_8, Y => \un2_wb_acc_iv_3[17]\); - - \r.btag.PPN_RNI8F7MKO1[10]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[18]\, C => - pteout_m_i_1_2, Y => \un2_wb_acc_iv_3[18]\); - - \r.btag.I3_RNIFS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIFS1Q[4]\); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[59]\); - - \r.btag.PPN_RNI81V5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_1(2), Y => N_1149); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data_19, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[72]\); - - \r.btag.CTX_RNILNI6[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx(3), Y => h_c2_3_i); - - \r.btag.PPN_RNI6C1HKO1[0]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[8]\, C => - pteout_m_i_0_1_0, Y => \data_1_3_i_a3_0_3[12]\); - - \r.btag.I2_RNINOTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.PPN_RNI1K5B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_2(2), Y => N_1162); - - \r.btag.PPN_RNI5SNSBN2[12]\ : OR3C - port map(A => \un2_wb_acc_iv_3[20]\, B => - un2_wb_acc_iv_2_11, C => un2_wb_acc_iv_4_11, Y => - \un2_wb_acc[20]\); - - \r.btag.PPN_RNI2S5B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_1(2), Y => N_1155); - - \r.btag.PPN_RNILFT7BN2[1]\ : OR3C - port map(A => \un2_wb_acc_iv_3[9]\, B => un2_wb_acc_iv_2_0, - C => un2_wb_acc_iv_4_0, Y => \un2_wb_acc[9]\); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.LVL_RNIBIIE[1]\ : NOR2 - port map(A => \LVL[1]\, B => TYP_1_0(0), Y => - hf_1_1_1_a1_2_0); - - \r.btag.PPN_RNIM79MKO1[17]\ : NOR2B - port map(A => \pteout_m_i_0[25]\, B => pteout_m_i_0_0_17, Y - => data_1_3_i_a3_3_4); - - \r.btag.PPN_RNI7MG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[14]\, Y => - \pteout_m_i[14]\); - - \r.btag.ACC_RNIU3D3[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry(2), Y => N_1137); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data_20, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_7 is - - port( hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_0 : in std_logic; - lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1 : in std_logic_vector(3 to 3); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_23 : in std_logic; - hrdata_16 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_1 : in std_logic; - hrdata_6 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(3 to 3); - LVL_1 : in std_logic_vector(1 to 1); - TYP_1 : in std_logic_vector(2 downto 0); - s2_entry : in std_logic_vector(2 to 2); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_4 : in std_logic_vector(2 to 2); - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - s2_entry_3 : in std_logic_vector(2 to 2); - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - tlbcam_write_op_1_0 : in std_logic_vector(3 to 3); - LVL_0_d0 : out std_logic; - ctx_7 : in std_logic; - ctx_6 : in std_logic; - ctx_5 : in std_logic; - ctx_3 : in std_logic; - ctx_1 : in std_logic; - ctx_0_d0 : in std_logic; - ctx_2 : in std_logic; - ctx_0 : in std_logic_vector(4 to 4); - I2_1 : in std_logic_vector(5 downto 0); - I1_1_6 : in std_logic; - I1_1_3 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_5 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - TYP_1_0 : in std_logic_vector(0 to 0); - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_8 : in std_logic; - pteout_m_i_5 : in std_logic; - un2_wb_acc_iv_1_3 : out std_logic; - un2_wb_acc_iv_1_0 : out std_logic; - un2_wb_acc_iv_0 : in std_logic_vector(27 to 27); - un2_wb_acc_iv_4 : out std_logic_vector(27 to 27); - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_0_d0 : out std_logic; - pteout_m_i_0_19 : in std_logic; - pteout_m_i_0_16 : in std_logic; - pteout_m_i_0_14 : in std_logic; - pteout_m_i_0_13 : in std_logic; - data_1_3_i_a3_1_3 : out std_logic; - data_1_3_i_a3_1_1 : out std_logic; - data_1_3_i_a3_1_0 : out std_logic; - pteout_m_i_0_0_0 : in std_logic; - data_1_3_i_a3_0_1 : out std_logic_vector(15 to 15); - un1_cam_hitaddr : in std_logic_vector(60 to 60); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - cam_hit_all_5_sqmuxa_2 : in std_logic; - N_2551 : in std_logic; - N_1498 : in std_logic; - N_1506 : out std_logic; - N_1240 : out std_logic; - N_1253 : out std_logic; - trans_op : in std_logic; - s2_flush : in std_logic; - hit : out std_logic; - N_1239 : out std_logic; - N_1269 : out std_logic; - N_1249 : out std_logic; - un1_rst_i_0 : in std_logic; - un1_tlbcami_3 : out std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - N_1268 : out std_logic; - N_1267 : out std_logic; - N_1266 : out std_logic; - N_1265 : out std_logic; - N_1264 : out std_logic; - N_1263 : out std_logic; - N_1262 : out std_logic; - N_1261 : out std_logic; - N_1260 : out std_logic; - N_1259 : out std_logic; - N_1258 : out std_logic; - N_1257 : out std_logic; - N_1256 : out std_logic; - N_1255 : out std_logic; - N_1254 : out std_logic; - N_1252 : out std_logic; - N_1251 : out std_logic; - N_1250 : out std_logic; - N_1248 : out std_logic; - N_1247 : out std_logic; - N_1246 : out std_logic; - N_1245 : out std_logic; - N_1244 : out std_logic; - N_1243 : out std_logic; - N_1242 : out std_logic; - N_1238 : out std_logic; - N_1237 : out std_logic; - N_1236 : out std_logic; - s2_flush_0 : in std_logic; - N_661 : in std_logic; - tlbcamo_needsync : out std_logic; - WBNEEDSYNC_m : in std_logic; - accexc_6_2 : out std_logic - ); - -end mmutlbcam_2_0_7; - -architecture DEF_ARCH of mmutlbcam_2_0_7 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \pteout_m_i_0[11]\, \pteout[11]\, - \pteout_m_i_0_0[21]\, \pteout_m_i_0_0[22]\, - \pteout_m_i_0_0[24]\, WBNEEDSYNC_m_0, \pteout_m_i[27]\, - \pteout_m_i_0[14]\, \pteout_m_i_0[17]\, hm_1_1_3_N_9, - hm_1_1_3_m8_i_1, hf_1_1_1_a0_3_0, h_l3_1_4_i_0, - hm_1_1_3_m8_i_0, h_c2_NE_4, h_c2_NE_5, \un1_tag0[43]\, - hm_1_1_3_m8_i_o5_0, h_l2_1_2, h_l2_1_3, hf_1_1_1_a0_3_2, - un3_hf, hf_1_1_1_a0_3_0_0, hf_1_1_1_a1_2_1, \LVL[1]\, - h_l3_1_4_3, \un1_tag0[61]\, h_l3_1_4_1, \I3_RNIO8291[2]\, - \I3_RNI0N55[1]\, \I3_RNIRB0Q[0]\, h_i13_NE_4, - \I1_RNIAG0Q[1]\, \I1_RNILO091[0]\, h_i13_NE_1, h_i13_NE_3, - \un1_tag0[74]\, \I1_RNIB01Q[7]\, h_i13_NE_2, - \un1_tag0[73]\, \I1_RNIPK1Q[4]\, \un1_tag0[70]\, - \I1_RNIK81Q[3]\, h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, - h_l2_1_3_0, \un1_tag0[62]\, h_i22_1, hf_4_0, SU, h_c2_7_i, - h_c2_6_i, h_c2_NE_2, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[39]\, h_c2_5_i, \un1_tag0[37]\, h_c2_3_i, - h_i13_NE, hf_4, hf_3, \un45_res[3]\, \I3_RNIGS1Q[4]\, - \I3_RNIAG1Q[3]\, hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, - hm_1_1_3_N_14, hm_1_1_3_N_12, N_5, \LVL[0]\, h_i22_5, - h_i22_4, N_15, \un1_tag0[56]\, \un1_tag0[59]\, - \un1_tag0[69]\, \un1_tag0[71]\, \un1_tag0[72]\, - \un1_tag0[75]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[40]\, \un1_tag0[41]\, - \un1_tag0[42]\, \pteout[0]\, \pteout[1]\, \pteout[6]\, - \pteout[7]\, \pteout[8]\, \pteout[9]\, \pteout[10]\, - \pteout[12]\, \pteout[14]\, \pteout[15]\, \pteout[16]\, - \pteout[18]\, \pteout[19]\, \pteout[20]\, \pteout[21]\, - \pteout[22]\, \pteout[23]\, \pteout[24]\, \pteout[25]\, - \pteout[26]\, \pteout[27]\, \pteout[28]\, \pteout[29]\, - \pteout[30]\, \pteout[31]\, \pteout[13]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[66]\, \un1_tag0[67]\, - \un1_tag0[57]\, \un1_tag0[58]\, \un1_tag0[68]\, M_2, - \tlbcamo_needsync\, M_5, M_1_sqmuxa, VALID_RNO_14, N_9, - N_8, N_6, hf_1_1, N_7, \un1_tlbcami_3\, \pteout[17]\, - h_su_cnt_1, \un1_tag0[60]\, N_1494, \pteout[2]\, - \pteout[3]\, \pteout[4]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - pteout_4 <= \pteout[4]\; - pteout_3 <= \pteout[3]\; - pteout_2 <= \pteout[2]\; - LVL_0_d0 <= \LVL[0]\; - un1_tlbcami_3 <= \un1_tlbcami_3\; - tlbcamo_needsync <= \tlbcamo_needsync\; - - \r.btag.PPN_RNIEDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_1253); - - \r.btag.CTX_RNIGNI6[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_d0, Y => h_c2_0_i); - - \r.btag.PPN_RNIDC7B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_4(2), Y => N_1257); - - \r.btag.VALID_RNI8T3R1\ : NOR2B - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.I1_RNI2E3N3[0]\ : NOR3C - port map(A => \I1_RNIAG0Q[1]\, B => \I1_RNILO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[8]\); - - \r.btag.ACC_RNI24D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_1240); - - \r.btag.PPN_RNIPS8B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_4(2), Y => N_1263); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \LVL[1]\); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[39]\); - - \r.btag.I3_RNIRB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIRB0Q[0]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[63]\); - - \r.btag.CTX_RNIAF5D[2]\ : XA1A - port map(A => ctx_2, B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.LVL_RNILKR722[0]\ : AO1B - port map(A => hf_1_1, B => s2_flush, C => hm_1_1_3_N_9, Y - => hit); - - \r.btag.LVL_RNIDE2JB[0]\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[19]\); - - \r.btag.LVL_RNIICRF[0]\ : NOR2B - port map(A => hf_1_1_1_a0_3_0, B => TYP_1_0(0), Y => - hf_1_1_1_a0_3_0_0); - - \r.btag.PPN_RNIJN3BAS[10]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[18]\, Y => - pteout_m_i_9); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[67]\); - - \r.btag.CTX_RNIQNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_5, Y => h_c2_5_i); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(3), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNIKV8MKO1[16]\ : NOR2B - port map(A => pteout_m_i_0_16, B => \pteout_m_i_0_0[24]\, Y - => data_1_3_i_a3_1_3); - - \r.btag.ET_RNIATTA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_3(2), Y => N_1237); - - \r.btag.I1_RNI352K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIK81Q[3]\, Y => h_i13_NE_1); - - \r.btag.PPN_RNIAMG8AS[8]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[16]\, Y => - pteout_m_i_7); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[36]\); - - \r.btag.VALID_RNI3HCR71\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.SU_RNI6OLN1\ : AO1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - \r.btag.LVL_RNIF7UAQ[0]\ : NOR2A - port map(A => trans_op, B => hm_1_1_3_N_9, Y => - \un1_tlbcami_3\); - - \r.btag.VALID_RNIFHOPR\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.I2_RNIAL3K1[0]\ : XO1A - port map(A => I2_1(0), B => \un1_tag0[62]\, C => h_i22_1, Y - => h_l2_1_3_0); - - \r.btag.PPN_RNI9MG8AS[7]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[15]\, Y => - pteout_m_i_6); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[10]\); - - \r.btag.CTX_RNIINI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_1, Y => h_c2_1_i); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[57]\); - - \r.btag.PPN_RNIE78MKO1[13]\ : NOR2B - port map(A => pteout_m_i_0_13, B => \pteout_m_i_0_0[21]\, Y - => data_1_3_i_a3_1_0); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNIRN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[26]\, Y => - pteout_m_i_0_18); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.LVL_RNIUJJFK4[1]\ : MX2C - port map(A => \LVL[1]\, B => LVL_1(1), S => - cam_hit_all_5_sqmuxa_2, Y => N_1494); - - \r.btag.M_RNI0L56\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_3(2), Y => N_1242); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_0_21, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[21]\); - - \r.btag.PPN_RNIKR3BAS[11]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[19]\, Y => - pteout_m_i_10); - - \r.btag.PPN_RNI7MG8AS[5]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[13]\, Y => - pteout_m_i_4); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNICMACC\ : OR3B - port map(A => hf_1_1_1_a0_3_2, B => h_l2_1_3, C => - h_l3_1_4_i_0, Y => hf_1_1_1_a0_3_i); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => un1_rst_i_0, B => N_15, Y => VALID_RNO_14); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[66]\); - - \r.btag.ET_RNI8LTA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_3(2), Y => N_1236); - - \r.btag.CTX_RNIUNI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_7, Y => h_c2_7_i); - - \r.btag.PPN_RNIGF8MKO1[14]\ : NOR2B - port map(A => pteout_m_i_0_14, B => \pteout_m_i_0_0[22]\, Y - => data_1_3_i_a3_1_1); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[68]\); - - \r.btag.C_RNICK56\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_3(2), Y => N_1243); - - \r.btag.PPN_RNI2MG8AS[0]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[8]\, Y => - pteout_m_i_0_0_d0); - - \r.btag.PPN_RNIJH06[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_4(2), Y => N_1251); - - \r.btag.PPN_RNISR4BAS[19]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[27]\, Y => - \pteout_m_i[27]\); - - \r.btag.M_RNIAGO2BQ1\ : AOI1B - port map(A => WBNEEDSYNC_m_0, B => un1_cam_hitaddr(60), C - => WBNEEDSYNC_m, Y => accexc_6_2); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_0_22, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[29]\); - - \r.btag.PPN_RNI9S6B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_4(2), Y => N_1255); - - \r.btag.LVL_RNIGUQ19[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.M_RNIBFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => - \tlbcamo_needsync\); - - \r.btag.LVL_RNIUF04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_1269); - - \r.btag.PPN_RNI4106[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_3(2), Y => N_1245); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[64]\); - - \r.btag.I1_RNIRC547[5]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_14, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.LVL_RNIUCGBB[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1(0), Y => N_8); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[4]\); - - \r.btag.I1_RNIAG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNIAG0Q[1]\); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[25]\); - - \r.btag.ACC_RNI4OI5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_3(2), Y => N_1238); - - \r.btag.PPN_RNIFK7B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_4(2), Y => N_1258); - - \r.btag.PPN_RNICC1HKO1[3]\ : AND2 - port map(A => \pteout_m_i_0[11]\, B => pteout_m_i_0_0_0, Y - => data_1_3_i_a3_0_1(15)); - - \r.btag.PPN_RNI6DQ3[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry(2), Y => N_1249); - - \r.btag.I1_RNIB01Q[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => I1_1_6, Y => - \I1_RNIB01Q[7]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[3]\); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[60]\); - - \r.btag.PPN_RNI5MG8AS[3]\ : NAND2 - port map(A => \pteout[11]\, B => un1_cam_hitaddr(60), Y => - \pteout_m_i_0[11]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[75]\); - - \r.btag.I3_RNIGS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIGS1Q[4]\); - - \r.btag.PPN_RNI7K6B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_4(2), Y => N_1254); - - \r.btag.LVL_RNIKFM92[1]\ : NOR3A - port map(A => un3_hf, B => TYP_1_0(0), C => \LVL[1]\, Y => - hf_1_1_1_a1_2_1); - - \r.btag.I3_RNIJB882[0]\ : NOR3C - port map(A => \I3_RNIO8291[2]\, B => \I3_RNI0N55[1]\, C => - \I3_RNIRB0Q[0]\, Y => h_l3_1_4_1); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[1]\); - - \r.btag.PPN_RNIM34BAS[13]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[21]\, Y => - \pteout_m_i_0_0[21]\); - - \r.btag.PPN_RNIHS7B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_4(2), Y => N_1259); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[11]\); - - \r.btag.I1_RNIK81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIK81Q[3]\); - - \r.btag.I3_RNIL5BR4[3]\ : OR3C - port map(A => \I3_RNIGS1Q[4]\, B => \I3_RNIAG1Q[3]\, C => - h_l3_1_4_3, Y => h_l3_1_4_i_0); - - \r.btag.I2_RNI89483[0]\ : NOR2 - port map(A => h_l2_1_3_1, B => h_l2_1_3_0, Y => h_l2_1_3); - - \r.btag.VALID_RNIE7ML1\ : NOR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_1_1_3_m8_i_0); - - \r.btag.LVL_RNIDKH2_0[0]\ : NOR2 - port map(A => \LVL[1]\, B => \LVL[0]\, Y => hf_1_1_1_a0_3_0); - - \r.btag.I1_RNIBQ0P1[5]\ : XA1 - port map(A => N_661, B => \un1_tag0[73]\, C => - \I1_RNIPK1Q[4]\, Y => h_i13_NE_2); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[42]\); - - \r.btag.PPN_RNILH06[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_4(2), Y => N_1252); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[65]\); - - \r.btag.I3_RNI0N55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNI0N55[1]\); - - \r.btag.PPN_RNIBMG8AS[9]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[17]\, Y => - \pteout_m_i_0[17]\); - - \r.btag.I3_RNIO8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIO8291[2]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_0_27, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[27]\); - - \r.btag.I2_RNIOOTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(3), - Y => M_5); - - \r.btag.I3_RNIAG1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNIAG1Q[3]\); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[56]\); - - \r.btag.I1_RNIE41K1[6]\ : XA1 - port map(A => I1_1_5, B => \un1_tag0[74]\, C => - \I1_RNIB01Q[7]\, Y => h_i13_NE_3); - - \r.btag.PPN_RNI4MG8AS[2]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[10]\, Y => - pteout_m_i_1); - - \r.btag.CTX_RNIMNI6[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_3, Y => h_c2_3_i); - - \r.btag.PPN_RNI9H06[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_4(2), Y => N_1246); - - \r.btag.VALID_RNI8MVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[24]\); - - \r.btag.PPN_RNIPF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[24]\, Y => - \pteout_m_i_0_0[24]\); - - \r.btag.LVL_RNI5K66[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_4(2), - Y => N_1268); - - \r.btag.PPN_RNIQJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[25]\, Y => - pteout_m_i_0_17); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I1_RNIPK1Q[4]\ : XOR2 - port map(A => \un1_tag0[72]\, B => I1_1_3, Y => - \I1_RNIPK1Q[4]\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[69]\); - - \r.btag.CTX_RNI04TN[4]\ : NOR3C - port map(A => h_c2_7_i, B => h_c2_6_i, C => h_c2_NE_2, Y - => h_c2_NE_5); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[40]\); - - \r.btag.PPN_RNIBS6B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_4(2), Y => N_1265); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[37]\); - - \r.btag.PPN_RNIJ48B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_4(2), Y => N_1260); - - \r.btag.VALID_RNIG1JJ6\ : AOI1B - port map(A => hf_1_1_1_a0_3_0, B => h_l3_1_4_i_0, C => - hm_1_1_3_m8_i_0, Y => hm_1_1_3_m8_i_1); - - \r.btag.LVL_RNIGMF4Q[0]\ : OR3C - port map(A => hm_1_1_3_m8_i_1, B => hm_1_1_3_N_14, C => - hm_1_1_3_N_12, Y => hm_1_1_3_N_9); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_0_15, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[15]\); - - \r.btag.I2_RNIUJ0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.PPN_RNI6EBG263[19]\ : NOR3C - port map(A => \pteout_m_i[27]\, B => pteout_m_i_0_19, C => - un2_wb_acc_iv_0(27), Y => un2_wb_acc_iv_4(27)); - - \r.btag.I2_RNILTRT1[4]\ : NOR2 - port map(A => h_i22_5, B => h_i22_4, Y => h_l2_1_2); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[14]\); - - \r.btag.LVL_RNIVDEBC[1]\ : AO1A - port map(A => h_i13_NE, B => hm_1_1_3_m8_i_o5_0, C => - \LVL[1]\, Y => hm_1_1_3_N_12); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[7]\); - - \r.btag.I3_RNIRO773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_4_1, - Y => h_l3_1_4_3); - - \r.btag.LVL_RNI17E57[0]\ : OR2A - port map(A => h_i13_NE, B => \LVL[0]\, Y => hm_1_1_3_N_14); - - \r.btag.SU_RNISQR8\ : OR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.PPN_RNIN74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[22]\, Y => - \pteout_m_i_0_0[22]\); - - \r.btag.I1_RNILO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNILO091[0]\); - - \r.btag.PPN_RNIB47B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_4(2), Y => N_1256); - - \r.btag.PPN_RNILC8B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_4(2), Y => N_1261); - - \r.btag.PPN_RNIDH06[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_4(2), Y => N_1248); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \LVL[0]\); - - \r.btag.PPN_RNILV3BAS[12]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[20]\, Y => - pteout_m_i_11); - - \r.btag.PPN_RNIIC1HKO1[6]\ : NOR2B - port map(A => pteout_m_i_5, B => \pteout_m_i_0[14]\, Y => - un2_wb_acc_iv_1_0); - - \r.btag.LVL_RNI0JFAGN[1]\ : MX2C - port map(A => N_1494, B => N_1498, S => N_2551, Y => N_1506); - - \r.btag.PPN_RNIOB4BAS[15]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[23]\, Y => - pteout_m_i_0_15); - - \r.btag.PPN_RNI3MG8AS[1]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[9]\, Y => - pteout_m_i_0_d0); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[13]\); - - \r.btag.PPN_RNID47B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_4(2), Y => N_1266); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[30]\); - - \r.btag.PPN_RNI2106[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_3(2), Y => N_1244); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[74]\); - - \r.btag.I2_RNIT6065[0]\ : NOR2B - port map(A => h_l2_1_2, B => h_l2_1_3, Y => - hm_1_1_3_m8_i_o5_0); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_0_12, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[12]\); - - \r.btag.LVL_RNIDKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_0_26, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_0_23, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[23]\); - - \r.btag.CTX_RNICUAQ[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN_RNIBH06[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry_4(2), Y => N_1247); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_0_16, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => \un1_tlbcami_3\, B => tlbcam_write_op_1_0(3), - Y => M_1_sqmuxa); - - \r.btag.PPN_RNIOC1HKO1[9]\ : NOR2B - port map(A => pteout_m_i_8, B => \pteout_m_i_0[17]\, Y => - un2_wb_acc_iv_1_3); - - \r.btag.I2_RNIP82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.LVL_RNIHMMF7[1]\ : OR3C - port map(A => h_l2_1_2, B => hf_1_1_1_a1_2_1, C => h_l2_1_3, - Y => hf_1_1_1_a1_2_i); - - \r.btag.CTX_RNI6KNA[4]\ : XA1A - port map(A => ctx_0(4), B => \un1_tag0[39]\, C => h_c2_5_i, - Y => h_c2_NE_2); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[59]\); - - \r.btag.PPN_RNIHH06[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_4(2), Y => N_1250); - - \r.btag.I2_RNI3O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[72]\); - - \r.btag.I2_RNIT4UU[5]\ : XNOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => h_i22_5); - - \r.btag.PPN_RNINK8B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_4(2), Y => N_1262); - - \r.btag.PPN_RNI9K6B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_4(2), Y => N_1264); - - \r.btag.PPN_RNI8MG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[14]\, Y => - \pteout_m_i_0[14]\); - - \r.btag.LVL_RNIOP60R[1]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.M_RNIR58BR\ : NOR2A - port map(A => \tlbcamo_needsync\, B => hm_1_1_3_N_9, Y => - WBNEEDSYNC_m_0); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[73]\); - - \r.btag.ACC_RNI04D3[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry(2), Y => N_1239); - - \r.btag.PPN_RNI6MG8AS[4]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[12]\, Y => - pteout_m_i_3); - - \r.btag.SU_RNI8T3R1\ : OR3B - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => hf_4_0, Y => - hf_4); - - \r.btag.PPN_RNIFC7B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_4(2), Y => N_1267); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[18]\); - - \r.btag.CTX_RNISNI6[6]\ : XNOR2 - port map(A => \un1_tag0[41]\, B => ctx_6, Y => h_c2_6_i); - - \r.btag.VALID_RNIF7R84\ : NOR3C - port map(A => un3_hf, B => hf_1_1_1_a0_3_0_0, C => h_l2_1_2, - Y => hf_1_1_1_a0_3_2); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_1 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1 : in std_logic_vector(6 to 6); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_7 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(6 to 6); - TYP_1 : in std_logic_vector(2 downto 0); - tlbcam_write_op_1_0 : in std_logic_vector(6 to 6); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_27 : out std_logic; - pteout_6 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - ctx : in std_logic_vector(4 to 4); - I3_1_i : in std_logic_vector(3 to 3); - un1_cam_hitaddr : in std_logic_vector(57 to 57); - ctx_0_7 : in std_logic; - ctx_0_5 : in std_logic; - ctx_0_3 : in std_logic; - ctx_0_1 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_2 : in std_logic; - ctx_0_6 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - trans_op : in std_logic; - hit : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - un1_tlbcami_3 : out std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - WBNEEDSYNC_m : out std_logic; - tlbcamo_needsync : out std_logic - ); - -end mmutlbcam_2_0_1; - -architecture DEF_ARCH of mmutlbcam_2_0_1 is - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal WBNEEDSYNC_m_0, hm_1_1, hf_1_1_1_a0_3_3, un3_hf, - hf_1_1_1_a0_3_1, h_l2_1_2, hf_1_1_1_a1_2_1, \LVL[1]\, - h_l3_1_4_3, \un1_tag0[61]\, h_l3_1_4_1, \I3_RNIR8291[2]\, - \I3_RNI3N55[1]\, \I3_RNIUB0Q[0]\, h_i13_NE_4, - \I1_RNIDG0Q[1]\, \I1_RNIOO091[0]\, h_i13_NE_1, h_i13_NE_3, - \un1_tag0[75]\, \I1_RNI640Q[6]\, h_i13_NE_2, - \un1_tag0[72]\, \I1_RNIL5VU[5]\, \un1_tag0[70]\, - \I1_RNIN81Q[3]\, h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, - hf_4_0, \un1_tag0[43]\, SU, h_c2_NE_5, h_c2_5_i, h_c2_4_i, - h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, - h_l2_1, h_l2_1_3, h_i13_NE, hf_4, hm_1, h_l3_1_4_i, hm_4, - hf_3, \un45_res[3]\, h_i22_1, h_i22_0, \I3_RNIJS1Q[4]\, - \I3_RNIDG1Q[3]\, hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, hm_3, - N_5, \un1_tag0[67]\, h_i22_4, \un1_tag0[56]\, - \un1_tag0[59]\, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[74]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[62]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[66]\, \un1_tag0[57]\, - \un1_tag0[58]\, \un1_tag0[60]\, \un1_tag0[68]\, - \un1_tag0[73]\, M_2, \tlbcamo_needsync\, \pteout[6]\, M_5, - h_su_cnt_1, M_1_sqmuxa, VALID_RNO_8, N_15, N_9, N_8, N_6, - hf_1_1, N_7, N_1, N_3, \LVL[0]\, \un1_tlbcami_3\, - \pteout[8]\, \pteout[9]\, \pteout[10]\, \pteout[11]\, - \pteout[12]\, \pteout[13]\, \pteout[14]\, \pteout[15]\, - \pteout[16]\, \pteout[17]\, \pteout[18]\, \pteout[19]\, - \pteout[20]\, \pteout[21]\, \pteout[22]\, \pteout[23]\, - \pteout[24]\, \pteout[25]\, \pteout[26]\, \pteout[27]\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - pteout_17 <= \pteout[17]\; - pteout_27 <= \pteout[27]\; - pteout_6 <= \pteout[6]\; - pteout_26 <= \pteout[26]\; - pteout_25 <= \pteout[25]\; - pteout_24 <= \pteout[24]\; - pteout_23 <= \pteout[23]\; - pteout_22 <= \pteout[22]\; - pteout_21 <= \pteout[21]\; - pteout_20 <= \pteout[20]\; - pteout_19 <= \pteout[19]\; - pteout_18 <= \pteout[18]\; - pteout_16 <= \pteout[16]\; - pteout_15 <= \pteout[15]\; - pteout_14 <= \pteout[14]\; - pteout_13 <= \pteout[13]\; - pteout_12 <= \pteout[12]\; - pteout_11 <= \pteout[11]\; - pteout_10 <= \pteout[10]\; - pteout_9 <= \pteout[9]\; - pteout_8 <= \pteout[8]\; - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - un1_tlbcami_3 <= \un1_tlbcami_3\; - tlbcamo_needsync <= \tlbcamo_needsync\; - - \r.btag.PPN_RNIOV3BAS[12]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[20]\, Y => - pteout_m_i_11); - - \r.btag.VALID_RNIUPGC1\ : NOR2A - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.PPN_RNIEMG8AS[9]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[17]\, Y => - pteout_m_i_8); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[8]\); - - \r.btag.CTX_RNIKD1J[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIVR4BAS[19]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[27]\, Y => - pteout_m_i_18); - - \r.btag.I3_RNI7P773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_4_1, - Y => h_l3_1_4_3); - - \r.btag.LVL_RNI8B5PQ[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \LVL[1]\); - - \r.btag.LVL_RNIJKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[63]\); - - \r.btag.I2_RNIS82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.LVL_RNIUOVC81[0]\ : MX2 - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[19]\); - - \r.btag.CTX_RNIDS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.LVL_RNIRL03Q[1]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.LVL_RNIDJHID[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.I1_RNI640Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI640Q[6]\); - - \r.btag.M_RNIC8OJ91\ : NOR2A - port map(A => \tlbcamo_needsync\, B => hm_1_1, Y => - WBNEEDSYNC_m_0); - - \r.btag.PPN_RNITJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[25]\, Y => - pteout_m_i_0_17); - - \r.btag.I1_RNIDG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNIDG0Q[1]\); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNIBMVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(6), Y => N_15); - - \r.btag.I2_RNI2L5AC[5]\ : OR3B - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE, Y => - h_l2_1); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[41]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[36]\); - - \r.btag.I1_RNIEE3N3[0]\ : NOR3C - port map(A => \I1_RNIDG0Q[1]\, B => \I1_RNIOO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.CTX_RNILS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0_7, Y => h_c2_7_i); - - \r.btag.CTX_RNI9S44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_1, Y => h_c2_1_i); - - \r.btag.CTX_RNIRNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx(4), Y => h_c2_4_i); - - \r.btag.I3_RNIDG1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNIDG1Q[3]\); - - \r.btag.I1_RNIHQ0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIL5VU[5]\, Y => h_i13_NE_2); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[10]\); - - \r.btag.LVL_RNI4S7J8[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.PPN_RNI7MG8AS[2]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[10]\, Y => - pteout_m_i_1); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[57]\); - - \r.btag.SU_RNIPK291\ : AOI1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.I2_RNI6O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_28); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[58]\); - - \r.btag.CTX_RNI8P98[6]\ : XA1A - port map(A => ctx_0_6, B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_8); - - \r.btag.I2_RNIRTRT1[5]\ : XA1B - port map(A => I2_1(5), B => \un1_tag0[67]\, C => h_i22_4, Y - => h_l2_1_2); - - \r.btag.I3_RNIR8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIR8291[2]\); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[66]\); - - \r.btag.VALID_RNI14371\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_4); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[68]\); - - \r.btag.SU_RNI2RR8\ : OR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.I3_RNI3N55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNI3N55[1]\); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_2); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_29); - - \r.btag.PPN_RNIDMG8AS[8]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[16]\, Y => - pteout_m_i_7); - - \r.btag.CTX_RNIOO98[2]\ : XA1A - port map(A => ctx_0_2, B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[64]\); - - \r.btag.VALID_RNILDISQ\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_8, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.PPN_RNISF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[24]\, Y => - pteout_m_i_0_16); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_4); - - \r.btag.VALID_RNIJ70161\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[25]\); - - \r.btag.LVL_RNIDC3R1[1]\ : NOR3A - port map(A => un3_hf, B => TYP_1_0(0), C => \LVL[1]\, Y => - hf_1_1_1_a1_2_1); - - \r.btag.I3_RNIUB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIUB0Q[0]\); - - \r.btag.I3_RNISB882[0]\ : NOR3C - port map(A => \I3_RNIR8291[2]\, B => \I3_RNI3N55[1]\, C => - \I3_RNIUB0Q[0]\, Y => h_l3_1_4_1); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_3); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_1); - - \r.btag.SU_RNIUPGC1\ : OR3B - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => hf_4_0, Y => - hf_4); - - \r.btag.PPN_RNI6MG8AS[1]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[9]\, Y => - pteout_m_i_0_d0); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[11]\); - - \r.btag.I1_RNIOO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIOO091[0]\); - - \r.btag.LVL_RNIOCRF[0]\ : NOR3A - port map(A => TYP_1_0(0), B => \LVL[1]\, C => \LVL[0]\, Y - => hf_1_1_1_a0_3_1); - - \r.btag.LVL_RNI87AEA[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1(0), Y => N_8); - - \r.btag.I1_RNIK41K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI640Q[6]\, Y => h_i13_NE_3); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_0); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_31); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[65]\); - - \r.btag.I2_RNI4K0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[27]\); - - \r.btag.CTX_RNI8HJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.VALID_RNIAVJCI\ : NOR3 - port map(A => h_l3_1_4_i, B => hm_4, C => h_l2_1, Y => hm_1); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(6), - Y => M_5); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[56]\); - - \r.btag.M_RNIO53RJT\ : OR2B - port map(A => WBNEEDSYNC_m_0, B => un1_cam_hitaddr(57), Y - => WBNEEDSYNC_m); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[9]\); - - \r.btag.I1_RNIL5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIL5VU[5]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[70]\); - - \r.btag.LVL_RNIH48Q3[0]\ : NOR3C - port map(A => un3_hf, B => hf_1_1_1_a0_3_1, C => h_l2_1_2, - Y => hf_1_1_1_a0_3_3); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[24]\); - - \r.btag.I2_RNIKC1Q[0]\ : XNOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => h_i22_0); - - \r.btag.PPN_RNINR3BAS[11]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[19]\, Y => - pteout_m_i_10); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.M_RNIEFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => - \tlbcamo_needsync\); - - \r.btag.PPN_RNI5MG8AS[0]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[8]\, Y => - pteout_m_i_0_0); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[37]\); - - \r.btag.I1_RNIJD547[4]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.LVL_RNIN8SLA[0]\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.PPN_RNIMN3BAS[10]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[18]\, Y => - pteout_m_i_9); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[15]\); - - \r.btag.PPN_RNIP34BAS[13]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[21]\, Y => - pteout_m_i_0_13); - - \r.btag.PPN_RNIAMG8AS[5]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[13]\, Y => - pteout_m_i_4); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_7); - - \r.btag.CTX_RNIHS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0_5, Y => h_c2_5_i); - - \r.btag.LVL_RNIT9EJ81[0]\ : NOR2A - port map(A => trans_op, B => hm_1_1, Y => \un1_tlbcami_3\); - - \r.btag.I1_RNI952K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIN81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I2_RNIK9483[0]\ : NOR3 - port map(A => h_i22_1, B => h_i22_0, C => h_l2_1_3_1, Y => - h_l2_1_3); - - \r.btag.I3_RNIJS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIJS1Q[4]\); - - \r.btag.I1_RNIN81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIN81Q[3]\); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \LVL[0]\); - - \r.btag.I3_RNI76BR4[3]\ : OR3C - port map(A => \I3_RNIJS1Q[4]\, B => \I3_RNIDG1Q[3]\, C => - h_l3_1_4_3, Y => h_l3_1_4_i); - - \r.btag.LVL_RNIJDVLE2[0]\ : AO1B - port map(A => hf_1_1, B => s2_flush, C => hm_1_1, Y => hit); - - \r.btag.PPN_RNI8MG8AS[3]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[11]\, Y => - pteout_m_i_0_3); - - \r.btag.LVL_RNICKNTB[0]\ : OR3B - port map(A => hf_1_1_1_a0_3_3, B => h_l2_1_3, C => - h_l3_1_4_i, Y => hf_1_1_1_a0_3_i); - - \r.btag.PPN_RNIUN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[26]\, Y => - pteout_m_i_0_18); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_30); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[12]\); - - \r.btag.CTX_RNI7S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_0, Y => h_c2_0_i); - - \r.btag.VALID_RNIKH8B8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - \r.btag.PPN_RNIBMG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[14]\, Y => - pteout_m_i_5); - - \r.btag.PPN_RNICMG8AS[7]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[15]\, Y => - pteout_m_i_6); - - \r.btag.LVL_RNISJ317[1]\ : OR3C - port map(A => h_l2_1_2, B => hf_1_1_1_a1_2_1, C => h_l2_1_3, - Y => hf_1_1_1_a1_2_i); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => \un1_tlbcami_3\, B => tlbcam_write_op_1_0(6), - Y => M_1_sqmuxa); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[72]\); - - \r.btag.PPN_RNIQ74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[22]\, Y => - pteout_m_i_0_14); - - \r.btag.PPN_RNIRB4BAS[15]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[23]\, Y => - pteout_m_i_0_15); - - \r.btag.I2_RNIROTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.PPN_RNI9MG8AS[4]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[12]\, Y => - pteout_m_i_3); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlb_10_8_2_1_0 is - - port( aaddr : inout std_logic_vector(31 downto 2) := (others => 'Z'); - twowner_1 : in std_logic_vector(0 to 0); - address : in std_logic_vector(31 downto 2); - data_1_3_i_a3_6_0 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_2 : out std_logic; - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - ctx_0 : in std_logic_vector(7 downto 0); - ctx : in std_logic_vector(7 downto 0); - fault_lvl : out std_logic_vector(1 downto 0); - lvl_i_1 : in std_logic_vector(1 downto 0); - data_2_0 : in std_logic; - lvl_i_1_0 : in std_logic_vector(1 to 1); - data_1_17 : in std_logic; - data_1_5 : out std_logic; - data_1_11 : in std_logic; - data_1_10 : in std_logic; - data_1_9 : in std_logic; - data_1_8 : in std_logic; - data_1_7 : in std_logic; - data_1_4 : in std_logic; - data_1_12 : in std_logic; - data_1_15 : in std_logic; - hrdata_2 : in std_logic; - hrdata_3 : in std_logic; - hrdata_4 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_8 : in std_logic; - hrdata_9 : in std_logic; - hrdata_10 : in std_logic; - hrdata_11 : in std_logic; - hrdata_12 : in std_logic; - hrdata_13 : in std_logic; - hrdata_14 : in std_logic; - hrdata_15 : in std_logic; - hrdata_16 : in std_logic; - hrdata_17 : in std_logic; - hrdata_18 : in std_logic; - hrdata_21 : in std_logic; - hrdata_22 : in std_logic; - hrdata_23 : in std_logic; - hrdata_24 : in std_logic; - hrdata_26 : in std_logic; - hrdata_27 : in std_logic; - hrdata_28 : in std_logic; - hrdata_29 : in std_logic; - hrdata_30 : in std_logic; - hrdata_31 : in std_logic; - hrdata_7 : in std_logic; - hrdata_5 : in std_logic; - hrdata_6 : in std_logic; - maddress : in std_logic_vector(31 downto 12); - twowner_0 : in std_logic_vector(0 to 0); - data_RNIKU1T4 : out std_logic_vector(16 to 16); - un1_m0_2_94 : out std_logic; - un1_m0_2_98 : out std_logic; - un1_m0_2_92 : out std_logic; - un1_m0_2_106 : out std_logic; - un1_m0_2_91 : out std_logic; - un1_m0_2_108 : out std_logic; - un1_m0_2_93 : out std_logic; - un1_m0_2_95 : out std_logic; - un1_m0_2_96 : out std_logic; - un1_m0_2_97 : out std_logic; - un1_m0_2_86 : in std_logic; - un1_m0_2_85 : in std_logic; - un1_m0_2_84 : in std_logic; - un1_m0_2_83 : in std_logic; - un1_m0_2_82 : in std_logic; - un1_m0_2_81 : in std_logic; - un1_m0_2_80 : in std_logic; - un1_m0_2_79 : in std_logic; - un1_m0_2_78 : in std_logic; - un1_m0_2_77 : in std_logic; - un1_m0_2_76 : in std_logic; - un1_m0_2_75 : in std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_10 : out std_logic; - un1_m0_2_9 : out std_logic; - un1_m0_2_0_d0 : out std_logic; - un1_m0_2_19 : out std_logic; - un1_m0_2_29 : out std_logic; - un1_m0_2_18 : out std_logic; - un1_m0_2_12 : out std_logic; - un1_m0_2_11 : out std_logic; - un1_m0_2_8 : out std_logic; - un1_m0_2_6 : out std_logic; - un1_m0_2_5 : out std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_33 : out std_logic; - un1_m0_2_31 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_23 : out std_logic; - data_0_18 : in std_logic; - data_0_14 : in std_logic; - data_0_22 : out std_logic; - data_0_21 : out std_logic; - data_0_20 : out std_logic; - data_0_19 : out std_logic; - data_0_23 : out std_logic; - data_0_16 : out std_logic; - data_0_28 : in std_logic; - data_0_30 : in std_logic; - data_0_26 : in std_logic; - data_0_25 : in std_logic; - data_0_15 : in std_logic; - data_0_12 : in std_logic; - data_0_31 : in std_logic; - data_0_27 : out std_logic; - data_0_29 : out std_logic; - data_0_13 : out std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_1 : in std_logic; - un1_m0_2_0 : in std_logic_vector(35 to 35); - ft_1_i_a2_0 : out std_logic_vector(0 to 0); - twowner_2_0_a2_0_0 : out std_logic_vector(0 to 0); - data_18 : out std_logic; - data_28 : out std_logic; - data_30 : out std_logic; - data_25 : out std_logic; - data_26 : out std_logic; - data_31 : out std_logic; - data_24 : out std_logic; - data_14 : out std_logic; - data_15 : out std_logic; - data_12 : out std_logic; - data_13 : in std_logic; - adata_20 : out std_logic; - adata_13 : out std_logic; - adata_17 : out std_logic; - adata_31 : out std_logic; - adata_30 : out std_logic; - adata_29 : out std_logic; - adata_28 : out std_logic; - adata_26 : out std_logic; - adata_24 : out std_logic; - adata_19 : out std_logic; - adata_18 : out std_logic; - adata_16 : out std_logic; - adata_15 : out std_logic; - adata_14 : out std_logic; - adata_11 : out std_logic; - adata_8 : out std_logic; - adata_7 : out std_logic; - adata_6 : out std_logic; - adata_1 : out std_logic; - adata_0 : out std_logic; - adata_9 : out std_logic; - adata_12 : out std_logic; - adata_2 : out std_logic; - adata_3 : out std_logic; - adata_4 : out std_logic; - adata_10 : out std_logic; - adata_27 : out std_logic; - adata_22 : out std_logic; - adata_21 : out std_logic; - adata_25 : out std_logic; - adata_23 : out std_logic; - N_709 : out std_logic; - mmutlb_10_8_2_1_0_VCC : in std_logic; - N_694 : out std_logic; - N_695 : out std_logic; - N_696 : out std_logic; - N_2702_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2709_i_0 : out std_logic; - fault_pri_2 : out std_logic; - fault_pro_0 : out std_logic; - accexc_6 : out std_logic; - un54_fault_pro_m : out std_logic; - N_2699_i_0 : out std_logic; - N_2703_i_0 : out std_logic; - G_80_0 : out std_logic; - N_2714 : out std_logic; - N_2717 : out std_logic; - N_2720 : out std_logic; - e : in std_logic; - M_m : out std_logic; - fault_pro67 : out std_logic; - N_2701 : out std_logic; - un1_rst_i_0 : out std_logic; - N_264 : in std_logic; - N_262 : in std_logic; - N_78 : in std_logic; - N_82_0 : in std_logic; - N_80 : in std_logic; - fault_pro_1_0 : in std_logic; - fault_mexc_3_2 : out std_logic; - flush_op : in std_logic; - N_264_0 : in std_logic; - fault_mexc_0 : out std_logic; - tlbactive : in std_logic; - tlbdis : in std_logic; - trans_op : in std_logic; - N_78_0 : in std_logic; - N_3160 : out std_logic; - N_2571 : in std_logic; - N_262_0 : in std_logic; - fault_pri_m : in std_logic; - fault_pri_1 : out std_logic; - fault_pri : out std_logic; - trans_op_0 : in std_logic; - N_2488 : out std_logic; - N_2482 : out std_logic; - N_2886 : out std_logic; - N_2887 : out std_logic; - N_190 : out std_logic; - N_192 : out std_logic; - N_236 : out std_logic; - N_293 : out std_logic; - N_317 : out std_logic; - N_351 : out std_logic; - N_353 : out std_logic; - N_415 : out std_logic; - N_417 : out std_logic; - N_419 : out std_logic; - N_421 : out std_logic; - fault_trans_i_2 : in std_logic; - fault_su : out std_logic; - fault_read : out std_logic; - inv_1_0_a2_0_a2_0 : in std_logic; - fault_trans : out std_logic; - fault_inv : out std_logic; - fault_mexc : in std_logic; - areq_ur_1_0_a2_0_0 : out std_logic; - N_2550 : out std_logic; - N_2532 : out std_logic; - rst : in std_logic; - read : in std_logic; - su : in std_logic; - fault_pro_1_iv_1 : out std_logic; - fault_pro_1_iv_2 : out std_logic; - fault_pro_i : out std_logic; - N_82 : in std_logic; - s1finished_0 : out std_logic; - walk_use_0 : out std_logic; - lclk_c : in std_logic; - N_86_i : out std_logic - ); - -end mmutlb_10_8_2_1_0; - -architecture DEF_ARCH of mmutlb_10_8_2_1_0 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_2 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - data_0_11 : in std_logic := 'U'; - data_0_9 : in std_logic := 'U'; - data_0_8 : in std_logic := 'U'; - data_0_7 : in std_logic := 'U'; - data_0_4 : in std_logic := 'U'; - data_0_3 : in std_logic := 'U'; - data_0_2 : in std_logic := 'U'; - data_0_0 : in std_logic := 'U'; - tlbcam_write_op_1_1 : in std_logic_vector(0 to 0) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(0 to 0) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_1 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_1 : in std_logic_vector(4 downto 2) := (others => 'U'); - s2_entry_0 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_17 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - cam_hitaddr_21 : in std_logic_vector(0 to 0) := (others => 'U'); - pteout_3 : in std_logic := 'U'; - pteout_2 : in std_logic := 'U'; - pteout_4 : in std_logic := 'U'; - un1_m0_2_4 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_0 : out std_logic; - un1_m0_2_15 : out std_logic; - un2_wb_acc_iv_2 : in std_logic_vector(14 to 14) := (others => 'U'); - un2_wb_acc_iv_3 : in std_logic_vector(14 to 14) := (others => 'U'); - un2_wb_acc_iv_5 : in std_logic_vector(18 downto 16) := (others => 'U'); - data_1_3_i_a3_0_5_3 : in std_logic := 'U'; - data_1_3_i_a3_0_5_0 : in std_logic := 'U'; - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - ctx_4 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_0_7 : in std_logic := 'U'; - ctx_0_3 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_6 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - pteout_m_i_1 : in std_logic_vector(15 to 15) := (others => 'U'); - un2_wb_acc_iv_0_12 : out std_logic; - un2_wb_acc_iv_1_8 : in std_logic := 'U'; - un2_wb_acc_iv_1_11 : in std_logic := 'U'; - un2_wb_acc_iv_1_10 : in std_logic := 'U'; - un2_wb_acc_iv_1_9 : in std_logic := 'U'; - un2_wb_acc_iv_1_7 : in std_logic := 'U'; - un2_wb_acc_iv_1_5 : in std_logic := 'U'; - un2_wb_acc_iv_1_4 : in std_logic := 'U'; - un2_wb_acc_iv_1_1 : in std_logic := 'U'; - un2_wb_acc_iv_1_0 : in std_logic := 'U'; - un2_wb_acc_iv_1_3 : in std_logic := 'U'; - pteout_m_i_11 : in std_logic := 'U'; - pteout_m_i_10 : in std_logic := 'U'; - pteout_m_i_9 : in std_logic := 'U'; - pteout_m_i_7 : in std_logic := 'U'; - pteout_m_i_6 : in std_logic := 'U'; - pteout_m_i_5 : in std_logic := 'U'; - pteout_m_i_4 : in std_logic := 'U'; - pteout_m_i_1_d0 : in std_logic := 'U'; - pteout_m_i_0_d0 : in std_logic := 'U'; - pteout_m_i_3 : in std_logic := 'U'; - un2_wb_acc_iv_4_11 : out std_logic; - un2_wb_acc_iv_4_10 : out std_logic; - un2_wb_acc_iv_4_6 : out std_logic; - un2_wb_acc_iv_4_4 : out std_logic; - un2_wb_acc_iv_4_1 : out std_logic; - un2_wb_acc_iv_4_0 : out std_logic; - un2_wb_acc_iv_4_3 : out std_logic; - data_1_3_i_a3_0_1_0 : in std_logic := 'U'; - data_1_3_i_a3_0_1_3 : in std_logic := 'U'; - data_1_3_i_a3_2 : in std_logic_vector(29 to 29) := (others => 'U'); - data_1_3_i_a3_3 : in std_logic_vector(29 to 29) := (others => 'U'); - pteout_m_i_0_1 : in std_logic_vector(26 to 26) := (others => 'U'); - pteout_m_i_0_9 : in std_logic := 'U'; - pteout_m_i_0_7 : in std_logic := 'U'; - pteout_m_i_0_19 : in std_logic := 'U'; - pteout_m_i_0_0_d0 : in std_logic := 'U'; - pteout_m_i_0_3 : in std_logic := 'U'; - pteout_m_i_0_16 : in std_logic := 'U'; - pteout_m_i_0_15 : in std_logic := 'U'; - pteout_m_i_0_17 : in std_logic := 'U'; - pteout_m_i_0_18 : in std_logic := 'U'; - pteout_m_i_0_0_14 : in std_logic := 'U'; - pteout_m_i_0_0_18 : in std_logic := 'U'; - pteout_m_i_0_0_13 : in std_logic := 'U'; - data_1_3_i_a3_5_5 : in std_logic := 'U'; - data_1_3_i_a3_5_3 : in std_logic := 'U'; - data_1_3_i_a3_5_2 : in std_logic := 'U'; - data_1_3_i_a3_5_1 : in std_logic := 'U'; - data_1_3_i_a3_5_0 : in std_logic := 'U'; - data_1_3_i_a3_1 : in std_logic_vector(29 downto 25) := (others => 'U'); - data_1_3_i_a3_6_2 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_0 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_2701 : out std_logic; - N_1104 : out std_logic; - N_1496 : in std_logic := 'U'; - N_1506 : in std_logic := 'U'; - N_1117 : out std_logic; - N_1481 : in std_logic := 'U'; - N_1120 : out std_logic; - N_1103 : out std_logic; - M_1 : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - un1_tlbcami_3 : out std_logic; - fault_pro67 : out std_logic; - read : in std_logic := 'U'; - M_m : out std_logic; - N_1133 : out std_logic; - N_1479 : in std_logic := 'U'; - s2_flush : in std_logic := 'U'; - e : in std_logic := 'U'; - rst : in std_logic := 'U'; - un1_rst_i_0 : out std_logic; - N_1505 : in std_logic := 'U'; - N_1482 : in std_logic := 'U'; - N_1495 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_1513 : out std_logic; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - N_2720 : out std_logic; - N_2717 : out std_logic; - N_2714 : out std_logic; - N_1132 : out std_logic; - N_1131 : out std_logic; - N_1130 : out std_logic; - N_1129 : out std_logic; - N_1128 : out std_logic; - N_1127 : out std_logic; - N_1126 : out std_logic; - N_1125 : out std_logic; - N_1124 : out std_logic; - N_1123 : out std_logic; - N_1122 : out std_logic; - N_1121 : out std_logic; - N_1119 : out std_logic; - N_1118 : out std_logic; - N_1116 : out std_logic; - N_1115 : out std_logic; - N_1114 : out std_logic; - N_1113 : out std_logic; - N_1112 : out std_logic; - N_1111 : out std_logic; - N_1110 : out std_logic; - N_1109 : out std_logic; - N_1108 : out std_logic; - N_1107 : out std_logic; - N_1106 : out std_logic; - N_1102 : out std_logic; - N_1101 : out std_logic; - N_1100 : out std_logic; - s2_flush_0 : in std_logic := 'U'; - G_80_0 : out std_logic; - N_1467 : in std_logic := 'U'; - N_1480 : in std_logic := 'U'; - N_1466 : in std_logic := 'U'; - cam_hit_all_5_sqmuxa_0_a2_0 : in std_logic := 'U'; - N_2551 : in std_logic := 'U'; - N_1468 : in std_logic := 'U'; - N_2703_i_0 : out std_logic; - N_2699_i_0 : out std_logic; - su : in std_logic := 'U'; - un54_fault_pro_m_0 : in std_logic := 'U'; - un54_fault_pro_m : out std_logic; - accexc_6 : in std_logic := 'U'; - fault_pro : out std_logic; - fault_pri : out std_logic; - N_2709_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2702_i_0 : out std_logic; - tlbcamo_needsync : out std_logic; - WBNEEDSYNC_m_0 : in std_logic := 'U'; - cam_hit_all_1 : out std_logic; - accexc_6_4 : out std_logic; - cam_hit_all_5_sqmuxa : in std_logic := 'U' - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_4 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(5 to 5) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(5 to 5) := (others => 'U'); - pteout_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - cam_hitaddr_18 : in std_logic_vector(1 to 1) := (others => 'U'); - LVL_0 : in std_logic_vector(0 to 0) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(5 to 5) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - cam_hitaddr_21_1 : out std_logic_vector(0 to 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_11 : in std_logic := 'U'; - pteout_m_i_10 : in std_logic := 'U'; - pteout_m_i_9 : in std_logic := 'U'; - pteout_m_i_7 : in std_logic := 'U'; - pteout_m_i_4 : in std_logic := 'U'; - pteout_m_i_1 : in std_logic := 'U'; - pteout_m_i_0_d0 : in std_logic := 'U'; - pteout_m_i_3 : in std_logic := 'U'; - un2_wb_acc_iv_1_11 : out std_logic; - un2_wb_acc_iv_1_10 : out std_logic; - un2_wb_acc_iv_1_9 : out std_logic; - un2_wb_acc_iv_1_7 : out std_logic; - un2_wb_acc_iv_1_4 : out std_logic; - un2_wb_acc_iv_1_1 : out std_logic; - un2_wb_acc_iv_1_0 : out std_logic; - un2_wb_acc_iv_1_3 : out std_logic; - data_1_3_i_a3_0_1 : out std_logic_vector(12 to 12); - data_1_3_i_a3_1_0 : out std_logic; - data_1_3_i_a3_1_2 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(58 to 58) := (others => 'U'); - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0_d0 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_24 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_6 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_13 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_12 : out std_logic; - pteout_8 : out std_logic; - pteout_23 : out std_logic; - pteout_25 : out std_logic; - pteout_11 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_0 : in std_logic := 'U'; - pteout_m_i_0_15 : in std_logic := 'U'; - pteout_m_i_0_17 : in std_logic := 'U'; - pteout_m_i_0_3 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_1471 : out std_logic; - NEEDSYNC : out std_logic; - N_1470 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_1469 : out std_logic; - N_1497 : out std_logic; - s2_flush_1 : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - WBNEEDSYNC_m : out std_logic; - N_61 : in std_logic := 'U'; - hit_1 : in std_logic := 'U'; - hit_0 : out std_logic; - hit : in std_logic := 'U'; - M_1 : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(4 to 4) := (others => 'U'); - un1_cam_hitaddr_1_0 : in std_logic := 'U'; - un1_cam_hitaddr_1_6 : in std_logic := 'U'; - un1_cam_hitaddr_1_5 : in std_logic := 'U'; - un1_cam_hitaddr_0 : out std_logic; - un1_cam_hitaddr_2 : out std_logic; - un1_cam_hitaddr_4 : out std_logic; - un1_cam_hitaddr_5 : out std_logic; - un1_cam_hitaddr_6 : out std_logic; - un1_cam_hitaddr_1_d0 : out std_logic; - pteout_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - cam_hitaddr_18 : in std_logic_vector(1 to 1) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 1) := (others => 'U'); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0_d0 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_27 : out std_logic; - pteout_6 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - ctx : in std_logic_vector(4 to 4) := (others => 'U'); - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - ctx_0_7 : in std_logic := 'U'; - ctx_0_5 : in std_logic := 'U'; - ctx_0_3 : in std_logic := 'U'; - ctx_0_1 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_2 : in std_logic := 'U'; - ctx_0_6 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - LVL : out std_logic_vector(1 downto 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_5 : in std_logic := 'U'; - un2_wb_acc_iv_2 : out std_logic_vector(14 to 14); - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_0_d0 : out std_logic; - pteout_m_i_0_17 : in std_logic := 'U'; - data_1_3_i_a3_2 : out std_logic_vector(29 to 29); - data_1_3_i_a3_3_2 : in std_logic := 'U'; - data_1_3_i_a3_3_0 : in std_logic := 'U'; - data_1_3_i_a3_5_2 : out std_logic; - data_1_3_i_a3_5_0 : out std_logic; - pteout_m_i_0_0_13 : in std_logic := 'U'; - pteout_m_i_0_0_11 : in std_logic := 'U'; - pteout_m_i_0_0_0 : in std_logic := 'U'; - data_1_3_i_a3_0_2 : out std_logic_vector(15 to 15); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_1496 : out std_logic; - N_1468 : out std_logic; - NEEDSYNC : out std_logic; - N_1467 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_1466 : out std_logic; - N_1495 : out std_logic; - trans_op : in std_logic := 'U'; - s2_flush_1 : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - hit_1 : in std_logic := 'U'; - hit_0 : in std_logic := 'U'; - N_2551 : out std_logic; - un1_cam_hitaddr_4_0 : in std_logic := 'U'; - WBNEEDSYNC_m : out std_logic; - hit : in std_logic := 'U' - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component mmutlbcam_2_0_5 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - tlbcam_write_op_1_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(1 to 1) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - un1_cam_hitaddr_1_0 : out std_logic; - un1_cam_hitaddr_1_5 : out std_logic; - un1_cam_hitaddr_1_6 : out std_logic; - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_1 : in std_logic_vector(4 downto 2) := (others => 'U'); - LVL_1 : in std_logic_vector(0 to 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_3 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_2 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_17 : in std_logic := 'U'; - pteout_0_4 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_4 : in std_logic := 'U'; - ctx_5 : in std_logic := 'U'; - ctx_7 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - cam_hitaddr_21_1 : in std_logic_vector(0 to 0) := (others => 'U'); - un1_cam_hitaddr : in std_logic_vector(62 to 62) := (others => 'U'); - ctx_0_0 : in std_logic := 'U'; - ctx_0_4 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I3_1_5 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - LVL_1_d0 : out std_logic; - cam_hitaddr_18 : in std_logic_vector(1 to 1) := (others => 'U'); - cam_hitaddr_21 : out std_logic_vector(0 to 0); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - s2_flush : in std_logic := 'U'; - N_1206 : out std_logic; - un1_rst_i_0 : in std_logic := 'U'; - N_1219 : out std_logic; - N_1482 : out std_logic; - N_1471 : in std_logic := 'U'; - N_1481 : out std_logic; - N_1205 : out std_logic; - N_1470 : in std_logic := 'U'; - N_1480 : out std_logic; - N_1235 : out std_logic; - N_1469 : in std_logic := 'U'; - N_1479 : out std_logic; - N_1497 : in std_logic := 'U'; - N_1505 : out std_logic; - NEEDSYNC : out std_logic; - s2_flush_1 : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_1234 : out std_logic; - N_1233 : out std_logic; - N_1232 : out std_logic; - N_1231 : out std_logic; - N_1230 : out std_logic; - N_1229 : out std_logic; - N_1228 : out std_logic; - N_1227 : out std_logic; - N_1226 : out std_logic; - N_1225 : out std_logic; - N_1224 : out std_logic; - N_1223 : out std_logic; - N_1222 : out std_logic; - N_1221 : out std_logic; - N_1220 : out std_logic; - N_1218 : out std_logic; - N_1217 : out std_logic; - N_1216 : out std_logic; - N_1215 : out std_logic; - N_1214 : out std_logic; - N_1213 : out std_logic; - N_1212 : out std_logic; - N_1211 : out std_logic; - N_1210 : out std_logic; - N_1209 : out std_logic; - N_1208 : out std_logic; - N_1204 : out std_logic; - N_1203 : out std_logic; - N_1202 : out std_logic; - N_2551 : in std_logic := 'U'; - cam_hit_all_5_sqmuxa : out std_logic; - cam_hit_all_5_sqmuxa_2 : in std_logic := 'U'; - cam_hit_all_5_sqmuxa_0_a2_0 : out std_logic; - accexc_6_3 : in std_logic := 'U'; - accexc_6_4 : in std_logic := 'U'; - accexc_6 : out std_logic; - N_661 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - un1_cam_hitaddr_4_0 : out std_logic; - M_1 : in std_logic := 'U'; - accexc_6_2 : in std_logic := 'U'; - WBNEEDSYNC_m : in std_logic := 'U' - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ0_1 - port( address : in std_logic_vector(31 downto 2) := (others => 'U'); - s2_entry : in std_logic_vector(2 downto 0) := (others => 'U'); - twowner_1 : in std_logic_vector(0 to 0) := (others => 'U'); - aaddr : inout std_logic_vector(31 downto 2); - dr1write_0_sqmuxa : in std_logic := 'U'; - syncramZ0_1_VCC : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_709 : out std_logic - ); - end component; - - component mmutlbcam_2_0_3 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(7 to 7) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(7 to 7) := (others => 'U'); - cam_hitaddr_18 : in std_logic_vector(1 to 1) := (others => 'U'); - LVL_0 : in std_logic_vector(1 to 1) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(7 to 7) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - ctx_0_3 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - ctx_6 : in std_logic := 'U'; - ctx_4 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_5 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_6 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_11 : in std_logic := 'U'; - pteout_m_i_10 : in std_logic := 'U'; - pteout_m_i_8 : in std_logic := 'U'; - pteout_m_i_6 : in std_logic := 'U'; - pteout_m_i_4 : in std_logic := 'U'; - pteout_m_i_1 : in std_logic := 'U'; - pteout_m_i_0_d0 : in std_logic := 'U'; - pteout_m_i_18 : in std_logic := 'U'; - pteout_m_i_3 : in std_logic := 'U'; - un2_wb_acc_iv_2_11 : out std_logic; - un2_wb_acc_iv_2_10 : out std_logic; - un2_wb_acc_iv_2_8 : out std_logic; - un2_wb_acc_iv_2_6 : out std_logic; - un2_wb_acc_iv_2_4 : out std_logic; - un2_wb_acc_iv_2_1 : out std_logic; - un2_wb_acc_iv_2_0 : out std_logic; - un2_wb_acc_iv_2_18 : out std_logic; - un2_wb_acc_iv_2_3 : out std_logic; - data_1_3_i_a3_3 : in std_logic_vector(30 to 30) := (others => 'U'); - data_1_3_i_a3_5 : out std_logic_vector(30 to 30); - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - pteout_m_i_0_18 : in std_logic := 'U'; - pteout_m_i_0_13 : in std_logic := 'U'; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_14 : out std_logic; - pteout_11 : out std_logic; - pteout_8 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_17 : out std_logic; - pteout_15 : out std_logic; - pteout_13 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_27 : out std_logic; - pteout_12 : out std_logic; - pteout_26 : out std_logic; - pteout_21 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(56 to 56) := (others => 'U'); - data_1_3_i_a3_2_0 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_1498 : out std_logic; - NEEDSYNC : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - s2_flush_1 : in std_logic := 'U'; - hit : out std_logic; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - WBNEEDSYNC_m : out std_logic; - N_661 : in std_logic := 'U' - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_6 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - data_0_18 : in std_logic := 'U'; - data_0_11 : in std_logic := 'U'; - data_0_10 : in std_logic := 'U'; - data_0_6 : in std_logic := 'U'; - data_0_4 : in std_logic := 'U'; - data_0_3 : in std_logic := 'U'; - data_0_1 : in std_logic := 'U'; - data_0_0 : in std_logic := 'U'; - tlbcam_write_op_1_1_0 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(2 to 2) := (others => 'U'); - TYP_1_2 : in std_logic := 'U'; - TYP_1_0_d0 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_RNIT69H911 : in std_logic_vector(0 to 0) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - data_21 : in std_logic := 'U'; - data_20 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - data_18 : in std_logic := 'U'; - data_17 : in std_logic := 'U'; - data_16 : in std_logic := 'U'; - data_13 : in std_logic := 'U'; - data_12 : in std_logic := 'U'; - data_11 : in std_logic := 'U'; - data_9 : in std_logic := 'U'; - data_6 : in std_logic := 'U'; - data_3 : in std_logic := 'U'; - data_7 : in std_logic := 'U'; - data_0_d0 : in std_logic := 'U'; - data_22 : in std_logic := 'U'; - data_8 : in std_logic := 'U'; - data_15 : in std_logic := 'U'; - data_5 : in std_logic := 'U'; - data_4 : in std_logic := 'U'; - data_14 : in std_logic := 'U'; - data_10 : in std_logic := 'U'; - un1_m0_2_0 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_3 : out std_logic; - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_2 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - s2_entry_1 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(2 to 2) := (others => 'U'); - cam_hitaddr_18 : out std_logic_vector(1 to 1); - un2_wb_acc_iv_4_3 : in std_logic := 'U'; - un2_wb_acc_iv_4_18 : in std_logic := 'U'; - un2_wb_acc_iv_4_0 : in std_logic := 'U'; - un2_wb_acc_iv_4_1 : in std_logic := 'U'; - un2_wb_acc_iv_4_4 : in std_logic := 'U'; - un2_wb_acc_iv_4_6 : in std_logic := 'U'; - un2_wb_acc_iv_4_10 : in std_logic := 'U'; - un2_wb_acc_iv_4_11 : in std_logic := 'U'; - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - un2_wb_acc_iv_2_3 : in std_logic := 'U'; - un2_wb_acc_iv_2_18 : in std_logic := 'U'; - un2_wb_acc_iv_2_0 : in std_logic := 'U'; - un2_wb_acc_iv_2_1 : in std_logic := 'U'; - un2_wb_acc_iv_2_4 : in std_logic := 'U'; - un2_wb_acc_iv_2_6 : in std_logic := 'U'; - un2_wb_acc_iv_2_10 : in std_logic := 'U'; - un2_wb_acc_iv_2_11 : in std_logic := 'U'; - un2_wb_acc_iv_2_8 : in std_logic := 'U'; - pteout_m_i_1_2 : in std_logic := 'U'; - pteout_m_i_1_0 : in std_logic := 'U'; - un2_wb_acc_iv_5 : out std_logic_vector(18 downto 16); - un2_wb_acc_iv_3_5 : out std_logic; - pteout_m_i_11 : in std_logic := 'U'; - pteout_m_i_10 : in std_logic := 'U'; - pteout_m_i_9 : in std_logic := 'U'; - pteout_m_i_8 : in std_logic := 'U'; - pteout_m_i_7 : in std_logic := 'U'; - pteout_m_i_6 : in std_logic := 'U'; - pteout_m_i_4 : in std_logic := 'U'; - pteout_m_i_1_d0 : in std_logic := 'U'; - pteout_m_i_0_d0 : in std_logic := 'U'; - pteout_m_i_18 : in std_logic := 'U'; - pteout_m_i_3 : in std_logic := 'U'; - pteout_m_i_0_1_0 : in std_logic := 'U'; - pteout_m_i_0_1_15 : in std_logic := 'U'; - pteout_m_i_0_0_0 : in std_logic := 'U'; - pteout_m_i_0_0_16 : in std_logic := 'U'; - pteout_m_i_0_0_15 : in std_logic := 'U'; - pteout_m_i_0_0_17 : in std_logic := 'U'; - pteout_m_i_0_0_14 : in std_logic := 'U'; - pteout_m_i_0_0_18 : in std_logic := 'U'; - data_1_3_i_a3_3_3 : out std_logic; - data_1_3_i_a3_3_4 : out std_logic; - data_1_3_i_a3_3_1 : out std_logic; - data_1_3_i_a3_3_5 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(61 to 61) := (others => 'U'); - data_1_3_i_a3_2 : in std_logic_vector(25 to 25) := (others => 'U'); - data_1_3_i_a3_5_2 : out std_logic; - data_1_3_i_a3_5_0 : out std_logic; - pteout_m_i_0_10 : in std_logic := 'U'; - pteout_m_i_0_8 : in std_logic := 'U'; - pteout_m_i_0_6 : in std_logic := 'U'; - pteout_m_i_0_0_d0 : in std_logic := 'U'; - pteout_m_i_0_15 : in std_logic := 'U'; - pteout_m_i_0_13 : in std_logic := 'U'; - pteout_m_i_0_3 : in std_logic := 'U'; - data_1_3_i_a3_0_2 : in std_logic_vector(15 to 15) := (others => 'U'); - data_1_3_i_a3_0_5_0 : out std_logic; - data_1_3_i_a3_0_5_3 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_1138 : out std_logic; - cam_hit_all_5_sqmuxa_2 : out std_logic; - N_1151 : out std_logic; - N_1154 : out std_logic; - s2_flush : in std_logic := 'U'; - N_1137 : out std_logic; - NEEDSYNC : out std_logic; - N_1167 : out std_logic; - un1_rst_i_0 : in std_logic := 'U'; - N_696 : out std_logic; - N_695 : out std_logic; - N_2709_i_0 : in std_logic := 'U'; - N_694 : out std_logic; - trans_op : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_1513 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - N_1166 : out std_logic; - N_1165 : out std_logic; - N_1164 : out std_logic; - N_1163 : out std_logic; - N_1162 : out std_logic; - N_1161 : out std_logic; - N_1160 : out std_logic; - N_1159 : out std_logic; - N_1158 : out std_logic; - N_1157 : out std_logic; - N_1156 : out std_logic; - N_1155 : out std_logic; - N_1153 : out std_logic; - N_1152 : out std_logic; - N_1150 : out std_logic; - N_1149 : out std_logic; - N_1148 : out std_logic; - N_1147 : out std_logic; - N_1146 : out std_logic; - N_1145 : out std_logic; - N_1144 : out std_logic; - N_1143 : out std_logic; - N_1142 : out std_logic; - N_1141 : out std_logic; - N_1140 : out std_logic; - N_1136 : out std_logic; - N_1135 : out std_logic; - N_1134 : out std_logic; - s2_flush_0 : in std_logic := 'U'; - hit_1 : in std_logic := 'U'; - hit_0 : in std_logic := 'U'; - hit : in std_logic := 'U'; - WBNEEDSYNC_m : in std_logic := 'U'; - accexc_6_3 : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_7 - port( hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(3 to 3) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(3 to 3) := (others => 'U'); - LVL_1 : in std_logic_vector(1 to 1) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_4 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - s2_entry_3 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(3 to 3) := (others => 'U'); - LVL_0_d0 : out std_logic; - ctx_7 : in std_logic := 'U'; - ctx_6 : in std_logic := 'U'; - ctx_5 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - ctx_2 : in std_logic := 'U'; - ctx_0 : in std_logic_vector(4 to 4) := (others => 'U'); - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_6 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_8 : in std_logic := 'U'; - pteout_m_i_5 : in std_logic := 'U'; - un2_wb_acc_iv_1_3 : out std_logic; - un2_wb_acc_iv_1_0 : out std_logic; - un2_wb_acc_iv_0 : in std_logic_vector(27 to 27) := (others => 'U'); - un2_wb_acc_iv_4 : out std_logic_vector(27 to 27); - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_0_d0 : out std_logic; - pteout_m_i_0_19 : in std_logic := 'U'; - pteout_m_i_0_16 : in std_logic := 'U'; - pteout_m_i_0_14 : in std_logic := 'U'; - pteout_m_i_0_13 : in std_logic := 'U'; - data_1_3_i_a3_1_3 : out std_logic; - data_1_3_i_a3_1_1 : out std_logic; - data_1_3_i_a3_1_0 : out std_logic; - pteout_m_i_0_0_0 : in std_logic := 'U'; - data_1_3_i_a3_0_1 : out std_logic_vector(15 to 15); - un1_cam_hitaddr : in std_logic_vector(60 to 60) := (others => 'U'); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - cam_hit_all_5_sqmuxa_2 : in std_logic := 'U'; - N_2551 : in std_logic := 'U'; - N_1498 : in std_logic := 'U'; - N_1506 : out std_logic; - N_1240 : out std_logic; - N_1253 : out std_logic; - trans_op : in std_logic := 'U'; - s2_flush : in std_logic := 'U'; - hit : out std_logic; - N_1239 : out std_logic; - N_1269 : out std_logic; - N_1249 : out std_logic; - un1_rst_i_0 : in std_logic := 'U'; - un1_tlbcami_3 : out std_logic; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - N_1268 : out std_logic; - N_1267 : out std_logic; - N_1266 : out std_logic; - N_1265 : out std_logic; - N_1264 : out std_logic; - N_1263 : out std_logic; - N_1262 : out std_logic; - N_1261 : out std_logic; - N_1260 : out std_logic; - N_1259 : out std_logic; - N_1258 : out std_logic; - N_1257 : out std_logic; - N_1256 : out std_logic; - N_1255 : out std_logic; - N_1254 : out std_logic; - N_1252 : out std_logic; - N_1251 : out std_logic; - N_1250 : out std_logic; - N_1248 : out std_logic; - N_1247 : out std_logic; - N_1246 : out std_logic; - N_1245 : out std_logic; - N_1244 : out std_logic; - N_1243 : out std_logic; - N_1242 : out std_logic; - N_1238 : out std_logic; - N_1237 : out std_logic; - N_1236 : out std_logic; - s2_flush_0 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - tlbcamo_needsync : out std_logic; - WBNEEDSYNC_m : in std_logic := 'U'; - accexc_6_2 : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_1 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(6 to 6) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(6 to 6) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(6 to 6) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_27 : out std_logic; - pteout_6 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - ctx : in std_logic_vector(4 to 4) := (others => 'U'); - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - un1_cam_hitaddr : in std_logic_vector(57 to 57) := (others => 'U'); - ctx_0_7 : in std_logic := 'U'; - ctx_0_5 : in std_logic := 'U'; - ctx_0_3 : in std_logic := 'U'; - ctx_0_1 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_2 : in std_logic := 'U'; - ctx_0_6 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - hit : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - un1_tlbcami_3 : out std_logic; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - WBNEEDSYNC_m : out std_logic; - tlbcamo_needsync : out std_logic - ); - end component; - - signal dr1write_0_sqmuxa_0, cache_0_sqmuxa_0, s2_flush_1, - s2_flush_1_0, un1_rst_3, s2_flush_0, \s2_entry_1[0]\, - \s2_entry_1_0[0]\, N_53, \s2_entry_0[0]\, \s2_entry_1[1]\, - \s2_entry_1_0[1]\, \s2_entry_0[1]\, \s2_entry_4[2]\, - \s2_entry_1[2]\, \s2_entry_3[2]\, \s2_entry_2[2]\, - \s2_entry_1_0[2]\, \s2_entry_0[2]\, walk_use_1, - sync_isw_RNII96B91, s2_tlbstate_3, s1finished_1, N_2530, - N_93, \tlbcam_write_op_1_1_0[4]\, - \tlbcam_write_op_1_1[4]\, \tlbcam_write_op_1_0[4]\, - \tlbcam_write_op_1_1[6]\, \tlbcam_write_op_1_1[7]\, - \tlbcam_write_op_1_0[6]\, \tlbcam_write_op_1_1[0]\, - \tlbcam_write_op_1_1[1]\, \tlbcam_write_op_1_0[0]\, - \tlbcam_write_op_1_1_0[7]\, \tlbcam_write_op_1_0[7]\, - \tlbcam_write_op_1_1[5]\, \tlbcam_write_op_1_0[5]\, - \tlbcam_write_op_1_1_0[1]\, \tlbcam_write_op_1_0[1]\, - \tlbcam_write_op_1_1_0[2]\, \tlbcam_write_op_1_1[2]\, - \tlbcam_write_op_1_0[2]\, dr1write_0_sqmuxa, - \tlbcam_write_op_1_1[3]\, \tlbcam_write_op_1_0[3]\, - \TYP_1_0[0]\, \data[8]\, \s2_tlbstate[0]\, - \s2_tlbstate[1]\, N_2957, N_3060, N_2959, \walk_use_0\, - \data[27]\, N_2977, N_2978, \data[29]\, N_3040, N_3073, - N_61, \I3_1_i_0_0[1]\, N_3041, N_3039, - \data_1_i_m2_i_0[27]\, \data_1_i_0[29]\, - un54_fault_pro_m_0, sync_isw_1_i_0_0, - \s2_tlbstate_ns_0_0_0[0]\, N_166, N_2547, N_2538, - sync_isw, \s2_tlbstate_ns_0_0_0[1]\, N_2552, - cache_0_sqmuxa_0_a2_0, \s2_tlbstate_ns_0_0_a2_0_0[0]\, - N_95, s2_needsync_4, un1_tlbcami_3, tlbcamo_needsync, - NEEDSYNC, s2_needsync_3, NEEDSYNC_0, s2_needsync_0, - s2_needsync_2, un1_tlbcami_3_0, tlbcamo_needsync_0, - NEEDSYNC_1, un1_tlbcami_3_1, tlbcamo_needsync_1, - NEEDSYNC_2, un9_twneedsync_i_a2_i_o2_i_a4_0, - fault_pro_1_iv_0_a2_0, fault_pro_1_iv_0_a2_0_0, - \data_1_i_m2_i_0[25]\, N_2927, \data_1_i_m2_i_0[26]\, - N_2931, \data_1_i_0[31]\, N_2962, \data_1_i_m2_i_0[12]\, - N_3066, N_2904, \data_1_i_m2_i_0[13]\, N_2909, - \data_1_i_m2_i_0[16]\, \data[16]\, N_2912, - \data_1_i_0[15]\, N_805, \data_1_i_i_0[14]\, N_3065, - N_2955, \fault_pro_1_iv_2\, fault_pro_5_m_0_3, - fault_pro_5_m_0_2, \un1_dtlb0_1_m_0_i[45]\, - \un1_dtlb0_1_m_0_1[45]\, N_2241, \adata[4]\, - fault_pro_5_m_0_0, \fault_read\, fault_pri_1_m_1, - \fault_su\, fault_pro_1_m_0_4_0, \I3_1_i_0_0[2]\, N_3044, - \I1_1_i_0_0[0]\, N_3047, nrep_n1_0_i_0, \nrep[0]\, - \nrep[1]\, fault_pri_1_m, \adata[3]\, N_2499, N_97, - \N_86_i\, N_3038, N_3036, N_3037, N_3010, N_3011, N_3012, - N_3009, N_3006, N_3007, N_3005, N_3002, N_3003, N_3001, - N_2998, N_2999, N_3059, N_2976, N_2943, N_2940, N_2941, - N_2905, N_38, sync_isw_RNO_0, N_2494, \N_2532\, N_2509, - N_2539, N_55, N_2531, \N_2550\, fault_pro_1_m_0_4, - \adata[2]\, N_2954, s2_needsync, NEEDSYNC_3, N_2511, - N_2525, N_2922, N_2923, N_2924, N_1168, N_1100, N_1134, - N_1169, N_1101, N_1135, N_1170, N_1102, N_1136, N_1174, - N_1106, N_1140, N_1175, N_1107, N_1141, N_1176, N_1108, - N_1142, N_1177, N_1109, N_1143, N_1178, N_1110, N_1144, - N_1179, N_1111, N_1145, N_1180, N_1112, N_1146, N_1182, - N_1114, N_1148, N_1183, N_1115, N_1149, N_1184, N_1116, - N_1150, N_1186, N_1118, N_1152, N_1187, N_1119, N_1153, - N_1189, N_1121, N_1155, N_1190, N_1122, N_1156, N_1191, - N_1123, N_1157, N_1192, N_1124, N_1158, N_1193, N_1125, - N_1159, N_1194, N_1126, N_1160, N_1195, N_1127, N_1161, - N_1196, N_1128, N_1162, N_1197, N_1129, N_1163, N_1198, - N_1130, N_1164, N_1199, N_1131, N_1165, N_1200, N_1132, - N_1166, N_1270, N_1202, N_1236, N_1271, N_1203, N_1237, - N_1272, N_1204, N_1238, N_1276, N_1208, N_1242, N_1277, - N_1209, N_1243, N_1278, N_1210, N_1244, N_1279, N_1211, - N_1245, N_1280, N_1212, N_1246, N_1281, N_1213, N_1247, - N_1282, N_1214, N_1248, N_1284, N_1216, N_1250, N_1285, - N_1217, N_1251, N_1286, N_1218, N_1252, N_1288, N_1220, - N_1254, N_1289, N_1221, N_1255, N_1291, N_1223, N_1257, - N_1292, N_1224, N_1258, N_1293, N_1225, N_1259, N_1294, - N_1226, N_1260, N_1295, N_1227, N_1261, N_1296, N_1228, - N_1262, N_1297, N_1229, N_1263, \s2_entry[1]\, N_1298, - N_1230, N_1264, N_1299, N_1231, N_1265, N_1300, N_1232, - N_1266, N_1301, N_1233, N_1267, N_1302, N_1234, N_1268, - \adata[9]\, \adata[10]\, \adata[12]\, \adata[21]\, - \adata[22]\, \adata[23]\, \adata[25]\, \adata[27]\, - \s2_entry[0]\, \un1_acc[32]\, \cam_addr[31]_net_1\, - \fault_trans\, fault_trans_0, \fault_inv\, fault_inv_0, - fault_pri_0, \fault_pri\, \I1_1[7]\, \data[31]\, N_2483, - fault_pro_1, cache_0_sqmuxa, N_25, N_27, N_2523, N_29, - N_31, N_2276, s1finished, N_89, \I3_1[0]\, - \cam_addr[12]_net_1\, \data[12]\, \I3_1_i[3]\, - \cam_addr[15]_net_1\, \data[15]\, \I1_1[1]\, - \cam_addr[25]_net_1\, \data[25]\, \I1_1[2]\, - \cam_addr[26]_net_1\, \data[26]\, \I1_1[3]\, - \cam_addr[27]_net_1\, \data_0[27]\, \I1_1[6]\, - \cam_addr[30]_net_1\, \I1_1[4]\, \cam_addr[28]_net_1\, - N_2737, \data[24]\, N_2738, N_2739, N_2740, \data_1[12]\, - \adata[8]\, \data_1[13]\, \adata[26]\, \data_1[30]\, - \data[30]\, \data_1[25]\, \data_1[26]\, \data[23]\, - N_3063, N_3062, \adata[19]\, \data_1[31]\, \data_1[15]\, - \adata[11]\, \data[19]\, \adata[15]\, \data[20]\, - \adata[16]\, \data[21]\, \data_0[24]\, \data[22]\, - \adata[18]\, \data_0[13]\, N_3043, N_3046, N_550, N_19, - N_2735, \N_3160\, N_37, \data[14]\, N_2736, \data_0[16]\, - N_73, N_2747, \data_0[29]\, \adata[7]\, cache, \data[0]\, - \data_0[0]\, \data[1]\, \data_0[1]\, \data[2]\, - \data_0[2]\, \data[3]\, \data_0[3]\, \data[4]\, - \data_0[4]\, \data[5]\, \data_0[5]\, \data[7]\, - \data_0[7]\, walk_use, \data[10]\, \data_0[10]\, - \data[11]\, \data_0[11]\, N_691, \data_0[21]\, N_692, - \data_0[22]\, \I2_1[0]\, \cam_addr[18]_net_1\, \I2_1[1]\, - \cam_addr[19]_net_1\, \data_0[19]\, \I2_1[2]\, - \cam_addr[20]_net_1\, \data_0[20]\, \I2_1[3]\, - \cam_addr[21]_net_1\, \I2_1[4]\, \cam_addr[22]_net_1\, - \I2_1[5]\, \cam_addr[23]_net_1\, \data_0[23]\, \I3_1[4]\, - \cam_addr[16]_net_1\, \data_1[18]\, \adata[14]\, - \data[18]\, \un1_acc[33]\, \data[17]\, \data_0[17]\, - \data_1[28]\, \data_2[28]\, \I3_1[5]\, - \cam_addr[17]_net_1\, \data_2[18]\, N_661, N_701, - \TYP_1[2]\, \N_2482\, \data_2[31]\, \data_3[28]\, - \data[28]\, \data_2[30]\, \data_3[17]\, \data_1[17]\, - N_552, \adata[24]\, \tlbcam_write_op_1[6]\, - \tlbcam_write_op_1[5]\, \tlbcam_write_op_1[4]\, - \tlbcam_write_op_1[3]\, \tlbcam_write_op_1[2]\, - \tlbcam_write_op_1[0]\, \tlbcam_write_op_1[7]\, - \s2_entry[2]\, s2_hm, s2_needsync_1, N_2543, s2_flush, - N_2522, fault_mexc_1, \s2_tlbstate_nss[1]\, - \s2_tlbstate_nss[0]\, \adata[13]\, N_1181, N_1283, N_1215, - N_1249, N_1113, N_1147, N_700, N_693, N_690, N_2544, - N_2265, fault_pro_m, fault_pro, \data_1[14]\, N_1201, - N_1303, N_1235, N_1269, N_1133, N_1167, \TYP_1[0]\, - \data_0[8]\, M_1, N_1171, N_1273, N_1205, N_1239, N_1103, - N_1137, \TYP_1[1]\, \data[9]\, \data_0[9]\, \adata[20]\, - N_1188, N_1290, N_1222, N_1256, N_1120, N_1154, nrep_n0, - nrepe, N_2512, N_2513, \nrep[2]\, \cam_hitaddr_21[0]\, - \s1finished_0\, \cam_hitaddr_18[1]\, N_2551, N_699, - \adata[17]\, N_1185, N_1287, N_1219, N_1253, N_1117, - N_1151, \data[6]\, \data_0[6]\, \tlbcam_write_op_1[1]\, - N_1172, N_1274, N_1206, N_1240, N_1104, N_1138, - \fault_pri_1\, \fault_pro_1_iv_1\, cam_hit_all_1, - \s2_ctx[0]\, \s2_ctx[1]\, \s2_ctx[2]\, \s2_ctx[3]\, - \s2_ctx[4]\, \s2_ctx[5]\, \s2_ctx[6]\, \s2_ctx[7]\, - \un1_cam_hitaddr_1[56]\, \un1_cam_hitaddr_1[62]\, - \un1_cam_hitaddr_1[61]\, \un1_cam_hitaddr[56]\, - \un1_cam_hitaddr[58]\, \un1_cam_hitaddr[60]\, - \un1_cam_hitaddr[61]\, \un1_cam_hitaddr[62]\, - \un1_cam_hitaddr[57]\, \pteout[2]\, \pteout[3]\, - \pteout[4]\, \LVL[0]\, \LVL[1]\, \pteout[31]\, - \pteout[30]\, \pteout[29]\, \pteout[28]\, \pteout[1]\, - \pteout[0]\, \pteout[7]\, \pteout[17]\, \pteout_0[4]\, - \pteout_0[3]\, \pteout_0[2]\, \pteout[27]\, \pteout[6]\, - \pteout[26]\, \pteout[25]\, \pteout[24]\, \pteout[23]\, - \pteout[22]\, \pteout[21]\, \pteout[20]\, \pteout[19]\, - \pteout[18]\, \pteout[16]\, \pteout[15]\, \pteout[14]\, - \pteout[13]\, \pteout[12]\, \pteout[11]\, \pteout[10]\, - \pteout[9]\, \pteout[8]\, \LVL_0[0]\, \LVL_0[1]\, - \pteout_m_i[17]\, \pteout_m_i[27]\, \pteout_m_i[20]\, - \pteout_m_i[19]\, \pteout_m_i[18]\, \pteout_m_i[16]\, - \pteout_m_i[15]\, \pteout_m_i[13]\, \pteout_m_i[12]\, - \pteout_m_i[10]\, \pteout_m_i[9]\, \pteout_m_i[14]\, - \un2_wb_acc_iv_2[14]\, \pteout_m_i_0[26]\, - \pteout_m_i_0[23]\, \pteout_m_i_0[21]\, \pteout_m_i_0[8]\, - \pteout_m_i_0[25]\, \data_1_3_i_a3_2[29]\, - \data_1_3_i_a3_3[28]\, \data_1_3_i_a3_3[26]\, - \data_1_3_i_a3_5[28]\, \data_1_3_i_a3_5[26]\, - \pteout_m_i_0[24]\, \pteout_m_i_0[22]\, - \pteout_m_i_0[11]\, \data_1_3_i_a3_0_2[15]\, N_1496, - N_1468, N_1467, N_1466, N_1495, hit, hit_0, - un1_cam_hitaddr_4_0, WBNEEDSYNC_m, hit_1, - \pteout_m_i_0[17]\, \pteout_m_i_0[27]\, - \pteout_m_i_0[20]\, \pteout_m_i_0[19]\, - \pteout_m_i_0[18]\, \pteout_m_i_0[16]\, - \pteout_m_i_0[15]\, \pteout_m_i_0[14]\, - \pteout_m_i_0[13]\, \pteout_m_i_0[12]\, - \pteout_m_i_0[10]\, \pteout_m_i_0[9]\, \pteout_0[31]\, - \pteout_0[30]\, \pteout_0[29]\, \pteout_0[28]\, - \pteout_0[1]\, \pteout_0[0]\, \pteout_0[7]\, - \pteout_0[17]\, \pteout_0[27]\, \pteout_0[6]\, - \pteout_0[26]\, \pteout_0[25]\, \pteout_0[24]\, - \pteout_0[23]\, \pteout_0[22]\, \pteout_0[21]\, - \pteout_0[20]\, \pteout_0[19]\, \pteout_0[18]\, - \pteout_0[16]\, \pteout_0[15]\, \pteout_0[14]\, - \pteout_0[13]\, \pteout_0[12]\, \pteout_0[11]\, - \pteout_0[10]\, \pteout_0[9]\, \pteout_0[8]\, - \pteout_m_i_0_0[26]\, \pteout_m_i_0_0[25]\, - \pteout_m_i_0_0[24]\, \pteout_m_i_0_0[23]\, - \pteout_m_i_0_0[22]\, \pteout_m_i_0_0[21]\, - \pteout_m_i_0_0[11]\, \pteout_m_i_0_0[8]\, \un1_rst_i_0\, - WBNEEDSYNC_m_0, \LVL_1[0]\, \LVL_1[1]\, \pteout_1[3]\, - \pteout_1[2]\, \pteout_1[4]\, \un2_wb_acc_iv_3[14]\, - \un2_wb_acc_iv_5[16]\, \un2_wb_acc_iv_5[17]\, - \un2_wb_acc_iv_5[18]\, \data_1_3_i_a3_0_5[15]\, - \data_1_3_i_a3_0_5[12]\, \pteout_m_i_1[15]\, - \un2_wb_acc_iv_0[27]\, \un2_wb_acc_iv_1[17]\, - \un2_wb_acc_iv_1[20]\, \un2_wb_acc_iv_1[19]\, - \un2_wb_acc_iv_1[18]\, \un2_wb_acc_iv_1[16]\, - \un2_wb_acc_iv_1[14]\, \un2_wb_acc_iv_1[13]\, - \un2_wb_acc_iv_1[10]\, \un2_wb_acc_iv_1[9]\, - \un2_wb_acc_iv_1[12]\, \pteout_m_i_1[20]\, - \pteout_m_i_1[19]\, \pteout_m_i_1[18]\, - \pteout_m_i_1[16]\, \pteout_m_i_2[15]\, - \pteout_m_i_1[14]\, \pteout_m_i_1[13]\, - \pteout_m_i_1[10]\, \pteout_m_i_1[9]\, \pteout_m_i_1[12]\, - \un2_wb_acc_iv_4[20]\, \un2_wb_acc_iv_4[19]\, - \un2_wb_acc_iv_4[15]\, \un2_wb_acc_iv_4[13]\, - \un2_wb_acc_iv_4[10]\, \un2_wb_acc_iv_4[9]\, - \un2_wb_acc_iv_4[12]\, \data_1_3_i_a3_0_1[12]\, - \data_1_3_i_a3_0_1[15]\, \data_1_3_i_a3_3[29]\, - \pteout_m_i_0_1[26]\, \pteout_m_i_1[17]\, - \pteout_m_i_3[15]\, \pteout_m_i_1[27]\, - \pteout_m_i_0_1[8]\, \pteout_m_i_0_1[11]\, - \pteout_m_i_0_1[24]\, \pteout_m_i_0_1[23]\, - \pteout_m_i_0_1[25]\, \pteout_m_i_0_2[26]\, - \pteout_m_i_0_1[22]\, \pteout_m_i_0_3[26]\, - \pteout_m_i_0_1[21]\, \data_1_3_i_a3_5[30]\, - \data_1_3_i_a3_5[27]\, \data_1_3_i_a3_5[25]\, - \data_1_3_i_a3_1[25]\, \data_1_3_i_a3_1[26]\, - \data_1_3_i_a3_1[27]\, \data_1_3_i_a3_1[28]\, - \data_1_3_i_a3_1[29]\, N_1506, N_1481, N_1479, N_1505, - N_1482, N_1513, N_1480, cam_hit_all_5_sqmuxa_0_a2_0, - accexc_6_4, cam_hit_all_5_sqmuxa, \LVL_2[1]\, \LVL_2[0]\, - \LVL_3[1]\, \pteout_m_i_2[18]\, \pteout_m_i_2[16]\, - \un2_wb_acc_iv_2[20]\, \un2_wb_acc_iv_2[19]\, - \un2_wb_acc_iv_2[17]\, \un2_wb_acc_iv_2[15]\, - \un2_wb_acc_iv_2[13]\, \un2_wb_acc_iv_2[10]\, - \un2_wb_acc_iv_2[9]\, \un2_wb_acc_iv_2[27]\, - \un2_wb_acc_iv_2[12]\, \data_1_3_i_a3_3[30]\, - \pteout_m_i_0_2[23]\, \pteout_m_i_0_2[8]\, \pteout_1[31]\, - \pteout_1[30]\, \pteout_1[29]\, \pteout_1[28]\, - \pteout_1[1]\, \pteout_1[0]\, \pteout_2[4]\, - \pteout_2[3]\, \pteout_2[2]\, \pteout_1[7]\, - \pteout_1[6]\, \pteout_1[25]\, \pteout_1[24]\, - \pteout_1[23]\, \pteout_1[22]\, \pteout_1[18]\, - \pteout_1[16]\, \pteout_1[14]\, \pteout_1[11]\, - \pteout_1[8]\, \pteout_1[20]\, \pteout_1[19]\, - \pteout_1[17]\, \pteout_1[15]\, \pteout_1[13]\, - \pteout_1[10]\, \pteout_1[9]\, \pteout_1[27]\, - \pteout_1[12]\, \pteout_1[26]\, \pteout_1[21]\, - \data_1_3_i_a3_2[25]\, N_1498, WBNEEDSYNC_m_1, \LVL_3[0]\, - \cam_hitaddr_21_1[0]\, \pteout_m_i_2[17]\, - \pteout_m_i_2[27]\, \pteout_m_i_2[14]\, - \pteout_m_i_2[20]\, \pteout_m_i_2[19]\, - \pteout_m_i_3[18]\, \pteout_m_i_3[16]\, - \pteout_m_i_2[13]\, \pteout_m_i_2[10]\, \pteout_m_i_2[9]\, - \pteout_m_i_2[12]\, \pteout_2[31]\, \pteout_2[30]\, - \pteout_2[29]\, \pteout_2[28]\, \pteout_2[1]\, - \pteout_2[0]\, \pteout_2[7]\, \pteout_2[17]\, - \pteout_3[4]\, \pteout_3[3]\, \pteout_3[2]\, - \pteout_2[27]\, \pteout_2[26]\, \pteout_2[24]\, - \pteout_2[22]\, \pteout_2[21]\, \pteout_2[15]\, - \pteout_2[14]\, \pteout_2[6]\, \pteout_2[20]\, - \pteout_2[19]\, \pteout_2[18]\, \pteout_2[16]\, - \pteout_2[13]\, \pteout_2[10]\, \pteout_2[9]\, - \pteout_2[12]\, \pteout_2[8]\, \pteout_2[23]\, - \pteout_2[25]\, \pteout_2[11]\, \pteout_m_i_0_2[24]\, - \pteout_m_i_0_2[22]\, \pteout_m_i_0_2[21]\, - \pteout_m_i_0_3[8]\, \pteout_m_i_0_3[23]\, - \pteout_m_i_0_2[25]\, \pteout_m_i_0_2[11]\, N_1471, - N_1470, N_1469, N_1497, WBNEEDSYNC_m_2, hit_2, - \pteout_4[2]\, \LVL_4[0]\, \pteout_4[4]\, \pteout_4[3]\, - \LVL_4[1]\, cam_hit_all_5_sqmuxa_2, accexc_6_3, - \accexc_6\, accexc_6_2, \LVL_RNIT69H911[0]\, - \un2_wb_acc_iv_4[27]\, \N_2709_i_0\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : mmutlbcam_2_0_2 - Use entity work.mmutlbcam_2_0_2(DEF_ARCH); - for all : mmutlbcam_2_0_4 - Use entity work.mmutlbcam_2_0_4(DEF_ARCH); - for all : mmutlbcam_2_0 - Use entity work.mmutlbcam_2_0(DEF_ARCH); - for all : mmutlbcam_2_0_5 - Use entity work.mmutlbcam_2_0_5(DEF_ARCH); - for all : syncramZ0_1 - Use entity work.syncramZ0_1(DEF_ARCH); - for all : mmutlbcam_2_0_3 - Use entity work.mmutlbcam_2_0_3(DEF_ARCH); - for all : mmutlbcam_2_0_6 - Use entity work.mmutlbcam_2_0_6(DEF_ARCH); - for all : mmutlbcam_2_0_7 - Use entity work.mmutlbcam_2_0_7(DEF_ARCH); - for all : mmutlbcam_2_0_1 - Use entity work.mmutlbcam_2_0_1(DEF_ARCH); -begin - - LVL_RNIT69H911(0) <= \LVL_RNIT69H911[0]\; - data_1_5 <= \data_1[17]\; - data_0_22 <= \data_0[22]\; - data_0_21 <= \data_0[21]\; - data_0_20 <= \data_0[20]\; - data_0_19 <= \data_0[19]\; - data_0_23 <= \data_0[23]\; - data_0_16 <= \data_0[16]\; - data_0_27 <= \data_0[27]\; - data_0_29 <= \data_0[29]\; - data_0_13 <= \data_0[13]\; - data_18 <= \data[18]\; - data_28 <= \data[28]\; - data_30 <= \data[30]\; - data_25 <= \data[25]\; - data_26 <= \data[26]\; - data_31 <= \data[31]\; - data_24 <= \data[24]\; - data_14 <= \data[14]\; - data_15 <= \data[15]\; - data_12 <= \data[12]\; - adata_20 <= \adata[20]\; - adata_13 <= \adata[13]\; - adata_17 <= \adata[17]\; - adata_26 <= \adata[26]\; - adata_24 <= \adata[24]\; - adata_19 <= \adata[19]\; - adata_18 <= \adata[18]\; - adata_16 <= \adata[16]\; - adata_15 <= \adata[15]\; - adata_14 <= \adata[14]\; - adata_11 <= \adata[11]\; - adata_8 <= \adata[8]\; - adata_7 <= \adata[7]\; - adata_9 <= \adata[9]\; - adata_12 <= \adata[12]\; - adata_2 <= \adata[2]\; - adata_3 <= \adata[3]\; - adata_4 <= \adata[4]\; - adata_10 <= \adata[10]\; - adata_27 <= \adata[27]\; - adata_22 <= \adata[22]\; - adata_21 <= \adata[21]\; - adata_25 <= \adata[25]\; - adata_23 <= \adata[23]\; - N_2709_i_0 <= \N_2709_i_0\; - accexc_6 <= \accexc_6\; - un1_rst_i_0 <= \un1_rst_i_0\; - N_3160 <= \N_3160\; - fault_pri_1 <= \fault_pri_1\; - fault_pri <= \fault_pri\; - N_2482 <= \N_2482\; - fault_su <= \fault_su\; - fault_read <= \fault_read\; - fault_trans <= \fault_trans\; - fault_inv <= \fault_inv\; - N_2550 <= \N_2550\; - N_2532 <= \N_2532\; - fault_pro_1_iv_1 <= \fault_pro_1_iv_1\; - fault_pro_1_iv_2 <= \fault_pro_1_iv_2\; - s1finished_0 <= \s1finished_0\; - walk_use_0 <= \walk_use_0\; - N_86_i <= \N_86_i\; - - \r.s2_entry_1_RNICBOE[1]\ : MX2 - port map(A => N_1204, B => N_1238, S => \s2_entry_1[1]\, Y - => N_1272); - - \r.s2_entry_0_RNIHUSSN2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_1_0[7]\); - - \r.s2_data_RNIRH0O1[18]\ : MX2 - port map(A => \adata[14]\, B => \data[18]\, S => - \un1_acc[33]\, Y => \data_1[18]\); - - \cam_addr[17]\ : MX2 - port map(A => maddress(17), B => data_2_0, S => trans_op, Y - => \cam_addr[17]_net_1\); - - \r.s2_entry_RNI0N35_0[1]\ : NOR2A - port map(A => \s2_entry_4[2]\, B => \s2_entry[1]\, Y => - \tlbcam_write_op_1_1[4]\); - - \r.s2_entry_1_RNII44Q[1]\ : MX2 - port map(A => N_1228, B => N_1262, S => \s2_entry_1[1]\, Y - => N_1296); - - \r.s2_tlbstate_RNO_2[0]\ : OAI1 - port map(A => N_82, B => \N_2550\, C => \s2_tlbstate[0]\, Y - => N_2538); - - \cam_addr[28]\ : MX2 - port map(A => maddress(28), B => data_0_28, S => trans_op_0, - Y => \cam_addr[28]_net_1\); - - \r.s2_entry_RNIC1EK[0]\ : MX2 - port map(A => N_1201, B => N_1303, S => \s2_entry[0]\, Y - => \un1_acc[33]\); - - \r.s2_entry_RNIQVRN[1]\ : MX2 - port map(A => N_1231, B => N_1265, S => \s2_entry[1]\, Y - => N_1299); - - \r.s2_needsync_RNO_0\ : NOR3C - port map(A => NEEDSYNC_0, B => s2_needsync_0, C => - s2_needsync_2, Y => s2_needsync_3); - - \r.s2_data_RNITSTM[27]\ : MX2C - port map(A => \cam_addr[27]_net_1\, B => \data_0[27]\, S - => s2_flush_0, Y => \I1_1[3]\); - - \r.walk_use_RNI7P5M1_0\ : NOR2 - port map(A => walk_use, B => N_552, Y => N_3065); - - \r.s2_data_RNI11QR[23]\ : MX2C - port map(A => \cam_addr[23]_net_1\, B => \data_0[23]\, S - => s2_flush_1, Y => \I2_1[5]\); - - \r.walk_fault.fault_pro_RNO_1\ : OR3B - port map(A => N_97, B => fault_pro_1_iv_0_a2_0, C => - hrdata_0_3, Y => N_2499); - - \r.s2_flush_0_RNI64RC1\ : NOR2 - port map(A => N_2530, B => N_93, Y => s1finished_1); - - \r.walk_transdata.data_RNO[19]\ : MX2 - port map(A => hrdata_0_15, B => \data_0[19]\, S => - lvl_i_1_0(1), Y => N_699); - - \r.s2_entry_RNIVH39[1]\ : MX2 - port map(A => N_1117, B => N_1151, S => \s2_entry[1]\, Y - => N_1185); - - \cam_addr[30]\ : MX2 - port map(A => maddress(30), B => data_0_30, S => trans_op_0, - Y => \cam_addr[30]_net_1\); - - \r.walk_fault.fault_inv_RNIQ09E\ : NOR2B - port map(A => \walk_use_0\, B => fault_inv_0, Y => - \fault_inv\); - - \r.s2_entry_RNI20TN[1]\ : MX2 - port map(A => N_1233, B => N_1267, S => \s2_entry[1]\, Y - => N_1301); - - \tlbcam0.0.tag0\ : mmutlbcam_2_0_2 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - hrdata_0_27 => hrdata_0_27, hrdata_0_26 => hrdata_0_26, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_21 => hrdata_0_21, hrdata_0_18 => hrdata_0_18, - hrdata_0_16 => hrdata_0_16, hrdata_0_15 => hrdata_0_15, - hrdata_0_12 => hrdata_0_12, hrdata_0_8 => hrdata_0_8, - hrdata_0_1 => hrdata_0_1, hrdata_0_0 => hrdata_0_0, - hrdata_0_4 => hrdata_0_4, hrdata_0_3 => hrdata_0_3, - hrdata_0_2 => hrdata_0_2, data_0_11 => \data_0[29]\, - data_0_9 => \data_0[27]\, data_0_8 => \data[26]\, - data_0_7 => \data[25]\, data_0_4 => \data_0[22]\, - data_0_3 => \data_0[21]\, data_0_2 => \data_0[20]\, - data_0_0 => \data[18]\, tlbcam_write_op_1_1(0) => - \tlbcam_write_op_1_1[0]\, s2_ctx(7) => \s2_ctx[7]\, - s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => \s2_ctx[5]\, - s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => \s2_ctx[3]\, - s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => \s2_ctx[1]\, - s2_ctx(0) => \s2_ctx[0]\, hrdata_24 => hrdata_31, - hrdata_23 => hrdata_30, hrdata_22 => hrdata_29, hrdata_21 - => hrdata_28, hrdata_17 => hrdata_24, hrdata_10 => - hrdata_17, hrdata_7 => hrdata_14, hrdata_6 => hrdata_13, - hrdata_4 => hrdata_11, hrdata_3 => hrdata_10, hrdata_2 - => hrdata_9, hrdata_0_d0 => hrdata_7, - tlbcam_write_op_1(0) => \tlbcam_write_op_1[0]\, TYP_1(2) - => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, TYP_1(0) => - \TYP_1[0]\, s2_entry(2) => \s2_entry[2]\, LVL_1(1) => - \LVL_1[1]\, LVL_1(0) => \LVL_1[0]\, TYP_1_0(0) => - \TYP_1_0[0]\, I1_1_i_0_0(0) => \I1_1_i_0_0[0]\, - I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, data(31) => \data[31]\, - data(30) => \data[30]\, data(29) => data_1_17, data(28) - => \data[28]\, data(27) => data_1_15, data(26) => - data_0_26, data(25) => data_0_25, data(24) => \data[24]\, - data(23) => \data_0[23]\, data(22) => data_1_10, data(21) - => data_1_9, data(20) => data_1_8, data(19) => - \data_0[19]\, data(18) => data_0_18, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, LVL_0(1) => - \LVL_0[1]\, LVL_0(0) => \LVL_0[0]\, s2_entry_1(2) => - \s2_entry_1_0[2]\, pteout_1(4) => \pteout_0[4]\, - pteout_1(3) => \pteout_0[3]\, pteout_1(2) => - \pteout_0[2]\, s2_entry_0(2) => \s2_entry_0[2]\, - pteout_0_17 => \pteout[17]\, pteout_0_20 => \pteout[20]\, - pteout_0_31 => \pteout[31]\, pteout_0_30 => \pteout[30]\, - pteout_0_29 => \pteout[29]\, pteout_0_28 => \pteout[28]\, - pteout_0_27 => \pteout[27]\, pteout_0_26 => \pteout[26]\, - pteout_0_25 => \pteout[25]\, pteout_0_24 => \pteout[24]\, - pteout_0_23 => \pteout[23]\, pteout_0_22 => \pteout[22]\, - pteout_0_21 => \pteout[21]\, pteout_0_19 => \pteout[19]\, - pteout_0_18 => \pteout[18]\, pteout_0_16 => \pteout[16]\, - pteout_0_15 => \pteout[15]\, pteout_0_14 => \pteout[14]\, - pteout_0_13 => \pteout[13]\, pteout_0_12 => \pteout[12]\, - pteout_0_11 => \pteout[11]\, pteout_0_10 => \pteout[10]\, - pteout_0_9 => \pteout[9]\, pteout_0_8 => \pteout[8]\, - pteout_0_7 => \pteout[7]\, pteout_0_6 => \pteout[6]\, - pteout_0_1 => \pteout[1]\, pteout_0_0 => \pteout[0]\, - I3_1_i(3) => \I3_1_i[3]\, tlbcam_write_op_1_0(0) => - \tlbcam_write_op_1_0[0]\, cam_hitaddr_21(0) => - \cam_hitaddr_21[0]\, pteout_3 => \pteout_1[3]\, pteout_2 - => \pteout_1[2]\, pteout_4 => \pteout_1[4]\, un1_m0_2_4 - => un1_m0_2_97, un1_m0_2_3 => un1_m0_2_96, un1_m0_2_2 - => un1_m0_2_95, un1_m0_2_0 => un1_m0_2_93, un1_m0_2_15 - => un1_m0_2_108, un2_wb_acc_iv_2(14) => - \un2_wb_acc_iv_2[14]\, un2_wb_acc_iv_3(14) => - \un2_wb_acc_iv_3[14]\, un2_wb_acc_iv_5(18) => - \un2_wb_acc_iv_5[18]\, un2_wb_acc_iv_5(17) => - \un2_wb_acc_iv_5[17]\, un2_wb_acc_iv_5(16) => - \un2_wb_acc_iv_5[16]\, data_1_3_i_a3_0_5_3 => - \data_1_3_i_a3_0_5[15]\, data_1_3_i_a3_0_5_0 => - \data_1_3_i_a3_0_5[12]\, LVL_RNIT69H911(0) => - \LVL_RNIT69H911[0]\, ctx_4 => ctx(5), ctx_3 => ctx(4), - ctx_0_d0 => ctx(1), ctx_1 => ctx(2), ctx_0_7 => ctx_0(7), - ctx_0_3 => ctx_0(3), ctx_0_0 => ctx_0(0), ctx_0_6 => - ctx_0(6), I1_1_5 => \I1_1[6]\, I1_1_2 => \I1_1[3]\, - I1_1_0 => \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_3 => - \I1_1[4]\, I1_1_6 => \I1_1[7]\, I2_1(5) => \I2_1[5]\, - I2_1(4) => \I2_1[4]\, I2_1(3) => \I2_1[3]\, I2_1(2) => - \I2_1[2]\, I2_1(1) => \I2_1[1]\, I2_1(0) => \I2_1[0]\, - I3_1_4 => \I3_1[4]\, I3_1_0 => \I3_1[0]\, I3_1_5 => - \I3_1[5]\, pteout_m_i_1(15) => \pteout_m_i_1[15]\, - un2_wb_acc_iv_0_12 => \un2_wb_acc_iv_0[27]\, - un2_wb_acc_iv_1_8 => \un2_wb_acc_iv_1[17]\, - un2_wb_acc_iv_1_11 => \un2_wb_acc_iv_1[20]\, - un2_wb_acc_iv_1_10 => \un2_wb_acc_iv_1[19]\, - un2_wb_acc_iv_1_9 => \un2_wb_acc_iv_1[18]\, - un2_wb_acc_iv_1_7 => \un2_wb_acc_iv_1[16]\, - un2_wb_acc_iv_1_5 => \un2_wb_acc_iv_1[14]\, - un2_wb_acc_iv_1_4 => \un2_wb_acc_iv_1[13]\, - un2_wb_acc_iv_1_1 => \un2_wb_acc_iv_1[10]\, - un2_wb_acc_iv_1_0 => \un2_wb_acc_iv_1[9]\, - un2_wb_acc_iv_1_3 => \un2_wb_acc_iv_1[12]\, pteout_m_i_11 - => \pteout_m_i_1[20]\, pteout_m_i_10 => - \pteout_m_i_1[19]\, pteout_m_i_9 => \pteout_m_i_1[18]\, - pteout_m_i_7 => \pteout_m_i_1[16]\, pteout_m_i_6 => - \pteout_m_i_2[15]\, pteout_m_i_5 => \pteout_m_i_1[14]\, - pteout_m_i_4 => \pteout_m_i_1[13]\, pteout_m_i_1_d0 => - \pteout_m_i_1[10]\, pteout_m_i_0_d0 => \pteout_m_i_1[9]\, - pteout_m_i_3 => \pteout_m_i_1[12]\, un2_wb_acc_iv_4_11 - => \un2_wb_acc_iv_4[20]\, un2_wb_acc_iv_4_10 => - \un2_wb_acc_iv_4[19]\, un2_wb_acc_iv_4_6 => - \un2_wb_acc_iv_4[15]\, un2_wb_acc_iv_4_4 => - \un2_wb_acc_iv_4[13]\, un2_wb_acc_iv_4_1 => - \un2_wb_acc_iv_4[10]\, un2_wb_acc_iv_4_0 => - \un2_wb_acc_iv_4[9]\, un2_wb_acc_iv_4_3 => - \un2_wb_acc_iv_4[12]\, data_1_3_i_a3_0_1_0 => - \data_1_3_i_a3_0_1[12]\, data_1_3_i_a3_0_1_3 => - \data_1_3_i_a3_0_1[15]\, data_1_3_i_a3_2(29) => - \data_1_3_i_a3_2[29]\, data_1_3_i_a3_3(29) => - \data_1_3_i_a3_3[29]\, pteout_m_i_0_1(26) => - \pteout_m_i_0_1[26]\, pteout_m_i_0_9 => - \pteout_m_i_1[17]\, pteout_m_i_0_7 => \pteout_m_i_3[15]\, - pteout_m_i_0_19 => \pteout_m_i_1[27]\, pteout_m_i_0_0_d0 - => \pteout_m_i_0_1[8]\, pteout_m_i_0_3 => - \pteout_m_i_0_1[11]\, pteout_m_i_0_16 => - \pteout_m_i_0_1[24]\, pteout_m_i_0_15 => - \pteout_m_i_0_1[23]\, pteout_m_i_0_17 => - \pteout_m_i_0_1[25]\, pteout_m_i_0_18 => - \pteout_m_i_0_2[26]\, pteout_m_i_0_0_14 => - \pteout_m_i_0_1[22]\, pteout_m_i_0_0_18 => - \pteout_m_i_0_3[26]\, pteout_m_i_0_0_13 => - \pteout_m_i_0_1[21]\, data_1_3_i_a3_5_5 => - \data_1_3_i_a3_5[30]\, data_1_3_i_a3_5_3 => - \data_1_3_i_a3_5[28]\, data_1_3_i_a3_5_2 => - \data_1_3_i_a3_5[27]\, data_1_3_i_a3_5_1 => - \data_1_3_i_a3_5[26]\, data_1_3_i_a3_5_0 => - \data_1_3_i_a3_5[25]\, data_1_3_i_a3_1(29) => - \data_1_3_i_a3_1[29]\, data_1_3_i_a3_1(28) => - \data_1_3_i_a3_1[28]\, data_1_3_i_a3_1(27) => - \data_1_3_i_a3_1[27]\, data_1_3_i_a3_1(26) => - \data_1_3_i_a3_1[26]\, data_1_3_i_a3_1(25) => - \data_1_3_i_a3_1[25]\, data_1_3_i_a3_6_2 => - data_1_3_i_a3_6_2, data_1_3_i_a3_6_4 => data_1_3_i_a3_6_4, - data_1_3_i_a3_6_1 => data_1_3_i_a3_6_1, data_1_3_i_a3_6_0 - => data_1_3_i_a3_6_0, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, - N_2701 => N_2701, N_1104 => N_1104, N_1496 => N_1496, - N_1506 => N_1506, N_1117 => N_1117, N_1481 => N_1481, - N_1120 => N_1120, N_1103 => N_1103, M_1 => M_1, N_2483 - => N_2483, trans_op => trans_op, un1_tlbcami_3 => - un1_tlbcami_3, fault_pro67 => fault_pro67, read => read, - M_m => M_m, N_1133 => N_1133, N_1479 => N_1479, s2_flush - => s2_flush, e => e, rst => rst, un1_rst_i_0 => - \un1_rst_i_0\, N_1505 => N_1505, N_1482 => N_1482, N_1495 - => N_1495, N_661 => N_661, N_3046 => N_3046, N_1513 => - N_1513, N_3043 => N_3043, N_61 => N_61, N_2720 => N_2720, - N_2717 => N_2717, N_2714 => N_2714, N_1132 => N_1132, - N_1131 => N_1131, N_1130 => N_1130, N_1129 => N_1129, - N_1128 => N_1128, N_1127 => N_1127, N_1126 => N_1126, - N_1125 => N_1125, N_1124 => N_1124, N_1123 => N_1123, - N_1122 => N_1122, N_1121 => N_1121, N_1119 => N_1119, - N_1118 => N_1118, N_1116 => N_1116, N_1115 => N_1115, - N_1114 => N_1114, N_1113 => N_1113, N_1112 => N_1112, - N_1111 => N_1111, N_1110 => N_1110, N_1109 => N_1109, - N_1108 => N_1108, N_1107 => N_1107, N_1106 => N_1106, - N_1102 => N_1102, N_1101 => N_1101, N_1100 => N_1100, - s2_flush_0 => s2_flush_0, G_80_0 => G_80_0, N_1467 => - N_1467, N_1480 => N_1480, N_1466 => N_1466, - cam_hit_all_5_sqmuxa_0_a2_0 => - cam_hit_all_5_sqmuxa_0_a2_0, N_2551 => N_2551, N_1468 => - N_1468, N_2703_i_0 => N_2703_i_0, N_2699_i_0 => - N_2699_i_0, su => su, un54_fault_pro_m_0 => - un54_fault_pro_m_0, un54_fault_pro_m => un54_fault_pro_m, - accexc_6 => \accexc_6\, fault_pro => fault_pro_0, - fault_pri => fault_pri_2, N_2709_i_0 => \N_2709_i_0\, - N_2711_i_0 => N_2711_i_0, N_2702_i_0 => N_2702_i_0, - tlbcamo_needsync => tlbcamo_needsync, WBNEEDSYNC_m_0 => - WBNEEDSYNC_m_0, cam_hit_all_1 => cam_hit_all_1, - accexc_6_4 => accexc_6_4, cam_hit_all_5_sqmuxa => - cam_hit_all_5_sqmuxa); - - \r.walk_transdata.data_RNIJ4V9[10]\ : MX2 - port map(A => \data[10]\, B => \data_0[10]\, S => walk_use, - Y => un1_m0_2_11); - - \r.s2_entry_1_RNIEHEE2[0]\ : NOR2A - port map(A => N_3062, B => \adata[19]\, Y => N_2943); - - \r.sync_isw_RNO_1\ : AOI1B - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, C - => rst, Y => sync_isw_1_i_0_0); - - \r.s2_entry_0_RNI4IDM1[0]\ : MX2 - port map(A => N_1169, B => N_1271, S => \s2_entry_0[0]\, Y - => adata_1); - - \r.s2_entry_1_RNIA43Q[1]\ : MX2 - port map(A => N_1226, B => N_1260, S => \s2_entry_1[1]\, Y - => N_1294); - - \r.s2_data_RNILCTM[25]\ : MX2C - port map(A => \cam_addr[25]_net_1\, B => \data[25]\, S => - s2_flush_0, Y => \I1_1[1]\); - - \r.s2_entry_RNI7NGJ[1]\ : MX2 - port map(A => N_1120, B => N_1154, S => \s2_entry[1]\, Y - => N_1188); - - \r.s2_entry_RNIMFRN[1]\ : MX2 - port map(A => N_1230, B => N_1264, S => \s2_entry[1]\, Y - => N_1298); - - \r.walk_transdata.data_RNIKU1T4[16]\ : OA1C - port map(A => N_3065, B => \adata[12]\, C => - \data_1_i_m2_i_0[16]\, Y => data_RNIKU1T4(16)); - - \r.s2_read_RNIGT0OO\ : OAI1 - port map(A => hrdata_6, B => \fault_read\, C => hrdata_5, Y - => N_95); - - \r.s2_entry_0_RNIOJ0Q[1]\ : MX2 - port map(A => N_1125, B => N_1159, S => \s2_entry_0[1]\, Y - => N_1193); - - \r.walk_fault.fault_trans_RNIJMK7\ : NOR2B - port map(A => \walk_use_0\, B => fault_trans_0, Y => - \fault_trans\); - - \r.s2_needsync_RNO_2\ : AOI1B - port map(A => un1_tlbcami_3_1, B => tlbcamo_needsync_1, C - => NEEDSYNC_2, Y => s2_needsync_0); - - \cam_addr[27]\ : MX2 - port map(A => maddress(27), B => data_1_15, S => trans_op_0, - Y => \cam_addr[27]_net_1\); - - \r.nrep[0]\ : DFN1E1 - port map(D => nrep_n0, CLK => lclk_c, E => nrepe, Q => - \nrep[0]\); - - \r.walk_transdata.data[20]\ : DFN1E0 - port map(D => N_700, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data[20]\); - - \r.s2_data[13]\ : DFN1E1 - port map(D => data_13, CLK => lclk_c, E => s1finished_1, Q - => \data_0[13]\); - - \r.walk_transdata.data_RNI6G3D[21]\ : NOR2A - port map(A => walk_use_1, B => \data[21]\, Y => N_3006); - - \r.s2_entry_0_RNICT011[0]\ : MX2 - port map(A => N_1170, B => N_1272, S => \s2_entry_0[0]\, Y - => \adata[2]\); - - \r.s2_data_RNI1QRN5[31]\ : OA1C - port map(A => N_3059, B => \data[31]\, C => - \data_1_i_0[31]\, Y => N_317); - - \r.walk_fault.fault_trans_RNO\ : NOR2 - port map(A => fault_trans_i_2, B => N_2523, Y => N_27); - - \r.sync_isw_RNI7DR9\ : NOR2B - port map(A => sync_isw, B => \s2_tlbstate[1]\, Y => - \N_2550\); - - \r.s2_data_RNI23LE2[17]\ : MX2 - port map(A => \adata[13]\, B => \data_1[17]\, S => N_552, Y - => \data[17]\); - - \p0.transdata.data_1_i_a2_0[29]\ : NOR2A - port map(A => \walk_use_0\, B => \data[29]\, Y => N_2978); - - \r.s2_entry_1_RNIGFNN1[0]\ : MX2 - port map(A => N_1193, B => N_1295, S => \s2_entry_1[0]\, Y - => \adata[25]\); - - \r.walk_fault.fault_mexc_RNO_1\ : OA1B - port map(A => N_89, B => s2_flush, C => \s2_tlbstate[0]\, Y - => N_2531); - - \r.s2_data[17]\ : DFN1E1 - port map(D => data_2_0, CLK => lclk_c, E => s1finished_1, Q - => \data_1[17]\); - - \r.s2_data[22]\ : DFN1E1 - port map(D => data_1_10, CLK => lclk_c, E => s1finished_1, - Q => \data_0[22]\); - - \r.s2_ctx[1]\ : DFN1E1 - port map(D => ctx(1), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[1]\); - - \r.s2_entry_RNIUFSN[1]\ : MX2 - port map(A => N_1232, B => N_1266, S => \s2_entry[1]\, Y - => N_1300); - - \r.s2_entry_RNIM00O[1]\ : MX2 - port map(A => N_1229, B => N_1263, S => \s2_entry[1]\, Y - => N_1297); - - \r.s2_entry_1_RNILTFN1[0]\ : MX2 - port map(A => N_1186, B => N_1288, S => \s2_entry_1[0]\, Y - => \adata[18]\); - - \r.s2_entry[0]\ : DFN1E0 - port map(D => \s2_entry_1_0[0]\, CLK => lclk_c, E => N_53, - Q => \s2_entry[0]\); - - \r.walk_fault.fault_pri_RNIO7TIU\ : OR2 - port map(A => fault_pro_1_0, B => \fault_pri_1\, Y => - fault_mexc_3_2); - - \r.s2_entry_1_RNI242Q[1]\ : MX2 - port map(A => N_1224, B => N_1258, S => \s2_entry_1[1]\, Y - => N_1292); - - \r.s2_flush_0_RNIB9GG1\ : OR2A - port map(A => rst, B => \s1finished_0\, Y => un1_rst_3); - - \r.walk_transdata.data_RNIHEPD[1]\ : MX2 - port map(A => \data[1]\, B => \data_0[1]\, S => walk_use_1, - Y => un1_m0_2_2); - - \r.walk_use_RNI7P5M1\ : OR2A - port map(A => N_552, B => walk_use, Y => N_3066); - - \r.s2_tlbstate_RNO_0[1]\ : MX2C - port map(A => N_2552, B => \s2_tlbstate[1]\, S => - \s2_tlbstate[0]\, Y => \s2_tlbstate_ns_0_0_0[1]\); - - \r.walk_use_1\ : DFN1E1 - port map(D => sync_isw_RNII96B91, CLK => lclk_c, E => - s2_tlbstate_3, Q => walk_use_1); - - \r.s2_entry_1_RNIOFON1[0]\ : MX2 - port map(A => N_1194, B => N_1296, S => \s2_entry_1[0]\, Y - => \adata[26]\); - - \r.walk_transdata.data[1]\ : DFN1E0 - port map(D => \data[1]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[1]\); - - \r.s2_flush_0_RNI64RC1_1\ : NOR2 - port map(A => N_2530, B => N_93, Y => \s1finished_0\); - - \r.s2_entry_RNIEFRD[1]\ : MX2 - port map(A => N_1234, B => N_1268, S => \s2_entry[1]\, Y - => N_1302); - - \r.s2_entry_1_RNIA2N21[0]\ : MX2 - port map(A => N_1180, B => N_1282, S => \s2_entry_1[0]\, Y - => \adata[12]\); - - \r.walk_fault.fault_pro_RNIF8BA\ : OR2B - port map(A => walk_use, B => fault_pro, Y => fault_pro_m); - - \r.s2_data_RNI15UM[28]\ : MX2C - port map(A => \cam_addr[28]_net_1\, B => \data[28]\, S => - s2_flush_0, Y => \I1_1[4]\); - - \r.s2_tlbstate_RNI667LK_0[1]\ : OR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => N_82, Y => cache_0_sqmuxa_0); - - \r.walk_transdata.data_RNIFEPD[0]\ : MX2 - port map(A => \data[0]\, B => \data_0[0]\, S => walk_use_1, - Y => un1_m0_2_1); - - \r.s2_entry_0_RNIQ23VN2_2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[4]\, Y => - \tlbcam_write_op_1_0[5]\); - - \r.nrep_RNILFC969[1]\ : MX2 - port map(A => \nrep[1]\, B => \cam_hitaddr_18[1]\, S => - \s1finished_0\, Y => \s2_entry_1_0[1]\); - - \p0.tlbcam_tagin.I3_1_i_0_a2_0[1]\ : OR2 - port map(A => data_13, B => N_3073, Y => N_3040); - - \r.walk_fault.fault_trans\ : DFN1E1 - port map(D => N_27, CLK => lclk_c, E => N_2276, Q => - fault_trans_0); - - \r.s2_data_RNIICTM[16]\ : MX2C - port map(A => \cam_addr[16]_net_1\, B => \data_0[16]\, S - => s2_flush_1, Y => \I3_1[4]\); - - \r.s2_ctx[0]\ : DFN1E1 - port map(D => ctx(0), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[0]\); - - \r.walk_transdata.data_RNO[18]\ : MX2 - port map(A => hrdata_0_14, B => \data[18]\, S => - lvl_i_1_0(1), Y => N_690); - - \p0.transdata.data_1_i_a2_0_RNI5PC2[29]\ : OR2 - port map(A => N_2977, B => N_2978, Y => \data_1_i_0[29]\); - - \r.s2_flush\ : DFN1E1 - port map(D => s2_flush_1_0, CLK => lclk_c, E => un1_rst_3, - Q => s2_flush); - - \r.s2_entry_0_RNIGJVP[1]\ : MX2 - port map(A => N_1123, B => N_1157, S => \s2_entry_0[1]\, Y - => N_1191); - - \r.s2_data_RNIOM0N1[14]\ : OR2A - port map(A => \data[14]\, B => N_3066, Y => N_2954); - - \r.s2_data_RNIBM1T4[15]\ : NOR2 - port map(A => \data_1_i_0[15]\, B => N_2976, Y => N_351); - - \r.nrep_RNO_1[1]\ : XNOR2 - port map(A => \nrep[0]\, B => \nrep[1]\, Y => nrep_n1_0_i_0); - - \r.walk_fault.fault_pro_RNO\ : AO1C - port map(A => hrdata_0_2, B => fault_pro_1_iv_0_a2_0_0, C - => N_2499, Y => fault_pro_1); - - \r.walk_use_0_RNISPLU1\ : NOR3A - port map(A => \adata[4]\, B => N_2241, C => \walk_use_0\, Y - => \un1_dtlb0_1_m_0_1[45]\); - - \r.s2_flush_1_RNIOIQK\ : OR2 - port map(A => N_3073, B => data_1_12, Y => N_3046); - - \r.s2_entry_1_RNI7EJF[1]\ : MX2 - port map(A => N_1217, B => N_1251, S => \s2_entry_1[1]\, Y - => N_1285); - - \r.s2_su_RNIMK6L2\ : NOR3B - port map(A => fault_pro_5_m_0_0, B => \adata[2]\, C => - N_2241, Y => fault_pro_5_m_0_2); - - \r.walk_fault.fault_lvl[0]\ : DFN1E0 - port map(D => N_80, CLK => lclk_c, E => cache_0_sqmuxa_0, Q - => fault_lvl(0)); - - \r.s2_entry_RNI27MJ1_0[0]\ : NOR2B - port map(A => \un1_acc[33]\, B => \un1_acc[32]\, Y => N_550); - - \r.s2_entry_RNITUUSN2_2[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[2]\, C => \s2_entry[0]\, Y => - \tlbcam_write_op_1[2]\); - - \r.s2_su_RNIMHUE1\ : NOR3 - port map(A => \walk_use_0\, B => \fault_su\, C => N_2241, Y - => fault_pri_1_m_1); - - \r.s2_entry_RNITUUSN2_0[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry[0]\, C => - \tlbcam_write_op_1_1[4]\, Y => \tlbcam_write_op_1[5]\); - - \r.s2_entry_0_RNIQ23VN2_0[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[4]\, Y => - \tlbcam_write_op_1_1[5]\); - - \p0.transdata.data_1_i_m2_i_a2_0[27]\ : NOR2A - port map(A => \walk_use_0\, B => \data[27]\, Y => N_2959); - - \r.walk_transdata.data_RNI5C3D[20]\ : NOR2A - port map(A => walk_use_1, B => \data[20]\, Y => N_3002); - - \r.s2_hm_RNI84O9_0\ : NOR3B - port map(A => s2_hm, B => s2_needsync_1, C => tlbdis, Y => - N_2543); - - \r.s2_entry_1_RNIEUJF[1]\ : MX2 - port map(A => N_1218, B => N_1252, S => \s2_entry_1[1]\, Y - => N_1286); - - \r.s2_data[25]\ : DFN1E1 - port map(D => data_0_25, CLK => lclk_c, E => s1finished_1, - Q => \data[25]\); - - \r.walk_transdata.data[10]\ : DFN1E0 - port map(D => \data[10]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[10]\); - - \r.s2_entry_1_RNIQ1N21[0]\ : MX2 - port map(A => N_1178, B => N_1280, S => \s2_entry_1[0]\, Y - => \adata[10]\); - - \r.s2_data_RNIKRUQ1[30]\ : OR2B - port map(A => \data[30]\, B => N_3059, Y => N_2924); - - \r.s2_data[31]\ : DFN1E1 - port map(D => data_0_31, CLK => lclk_c, E => s1finished, Q - => \data[31]\); - - \r.walk_transdata.data[24]\ : DFN1E0 - port map(D => N_2737, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data_0[24]\); - - \r.s2_tlbstate_RNIN69E[0]\ : NOR2 - port map(A => \s2_tlbstate[0]\, B => s2_flush, Y => N_2544); - - \r.s2_entry_RNIKQOQN2_1[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[7]\, C => \s2_entry[0]\, Y => - \tlbcam_write_op_1[6]\); - - \r.s2_entry_0_RNI55CP[1]\ : MX2 - port map(A => N_1101, B => N_1135, S => \s2_entry_0[1]\, Y - => N_1169); - - \p0.tlb_checkfault.un14_two_error_i\ : NOR2B - port map(A => hrdata_0_4, B => hrdata_0_3, Y => \N_2482\); - - \r.s2_flush_1\ : DFN1E1 - port map(D => s2_flush_1_0, CLK => lclk_c, E => un1_rst_3, - Q => s2_flush_1); - - \r.s2_entry_1_RNINDJF[1]\ : MX2 - port map(A => N_1213, B => N_1247, S => \s2_entry_1[1]\, Y - => N_1281); - - \r.walk_transdata.cache\ : DFN1E0 - port map(D => hrdata_7, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => cache); - - \r.s2_entry_0_RNITCGF[1]\ : MX2 - port map(A => N_1110, B => N_1144, S => \s2_entry_0[1]\, Y - => N_1178); - - \r.s2_data_RNI5O9D[8]\ : OR2B - port map(A => \data[8]\, B => s2_flush_0, Y => \TYP_1_0[0]\); - - \r.s2_data[12]\ : DFN1E1 - port map(D => data_0_12, CLK => lclk_c, E => s1finished_1, - Q => \data[12]\); - - \r.s2_flush_1_RNIJGG9\ : OR3 - port map(A => trans_op_0, B => s2_flush_1, C => - maddress(14), Y => N_3044); - - \r.walk_fault.fault_inv\ : DFN1E1 - port map(D => N_31, CLK => lclk_c, E => N_2276, Q => - fault_inv_0); - - \r.nrep[2]\ : DFN1E1 - port map(D => N_2512, CLK => lclk_c, E => nrepe, Q => - \nrep[2]\); - - \r.s2_data_RNI7HHE[9]\ : OR2B - port map(A => \data[9]\, B => s2_flush, Y => \TYP_1[1]\); - - \r.walk_transdata.data_RNIRCRU3[25]\ : AO1A - port map(A => \adata[21]\, B => N_3060, C => N_2927, Y => - \data_1_i_m2_i_0[25]\); - - \r.walk_transdata.data_RNO[25]\ : MX2 - port map(A => \data[25]\, B => hrdata_0_21, S => N_2571, Y - => N_2738); - - \r.walk_transdata.data[31]\ : DFN1E0 - port map(D => \data_2[31]\, CLK => lclk_c, E => - cache_0_sqmuxa, Q => \data_1[31]\); - - \r.s2_read_RNIMCLB\ : OR2 - port map(A => \fault_read\, B => \walk_use_0\, Y => - fault_pro_1_m_0_4_0); - - \r.s2_data[3]\ : DFN1E1 - port map(D => un1_m0_2_78, CLK => lclk_c, E => s1finished, - Q => \data[3]\); - - \r.walk_transdata.data_RNI9S3D[24]\ : NOR2A - port map(A => walk_use_1, B => \data_0[24]\, Y => N_3011); - - \r.s2_ctx[4]\ : DFN1E1 - port map(D => ctx(4), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[4]\); - - GND_i : GND - port map(Y => \GND\); - - \r.s2_entry_0_RNILCGF[1]\ : MX2 - port map(A => N_1108, B => N_1142, S => \s2_entry_0[1]\, Y - => N_1176); - - \r.s2_flush_0_RNI64RC1_0\ : NOR2 - port map(A => N_2530, B => N_93, Y => s1finished); - - \r.s2_data_RNIPHRR[29]\ : MX2C - port map(A => N_701, B => \data_0[29]\, S => s2_flush_1, Y - => N_661); - - \r.s2_entry_0_RNIHDGF[1]\ : MX2 - port map(A => N_1115, B => N_1149, S => \s2_entry_0[1]\, Y - => N_1183); - - \r.s2_entry_0_RNI53UP[1]\ : MX2 - port map(A => N_1121, B => N_1155, S => \s2_entry_0[1]\, Y - => N_1189); - - \r.s2_ctx[6]\ : DFN1E1 - port map(D => ctx(6), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[6]\); - - \tlbcam0.5.tag0\ : mmutlbcam_2_0_4 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1(5) => \tlbcam_write_op_1_1[5]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0 => hrdata_0_d0, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_7 => hrdata_7, - tlbcam_write_op_1(5) => \tlbcam_write_op_1[5]\, - pteout_0(4) => \pteout_2[4]\, pteout_0(3) => - \pteout_2[3]\, pteout_0(2) => \pteout_2[2]\, - cam_hitaddr_18(1) => \cam_hitaddr_18[1]\, LVL_0(0) => - \LVL_2[0]\, TYP_1(2) => \TYP_1[2]\, TYP_1(1) => - \TYP_1[1]\, TYP_1(0) => \TYP_1[0]\, - tlbcam_write_op_1_0(5) => \tlbcam_write_op_1_0[5]\, - I1_1_i_0_0(0) => \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => - \I3_1_i_0_0[2]\, ctx(7) => ctx(7), ctx(6) => ctx(6), - ctx(5) => ctx(5), ctx(4) => ctx(4), ctx(3) => ctx(3), - ctx(2) => ctx(2), ctx(1) => ctx(1), ctx(0) => ctx(0), - I2_1(5) => \I2_1[5]\, I2_1(4) => \I2_1[4]\, I2_1(3) => - \I2_1[3]\, I2_1(2) => \I2_1[2]\, I2_1(1) => \I2_1[1]\, - I2_1(0) => \I2_1[0]\, I1_1_5 => \I1_1[6]\, I1_1_2 => - \I1_1[3]\, I1_1_0 => \I1_1[1]\, I1_1_1 => \I1_1[2]\, - I1_1_3 => \I1_1[4]\, I1_1_6 => \I1_1[7]\, I3_1_5 => - \I3_1[5]\, I3_1_4 => \I3_1[4]\, I3_1_0 => \I3_1[0]\, - I3_1_i(3) => \I3_1_i[3]\, LVL(1) => \LVL_2[1]\, LVL(0) - => \LVL_3[0]\, TYP_1_0(0) => \TYP_1_0[0]\, - cam_hitaddr_21_1(0) => \cam_hitaddr_21_1[0]\, - pteout_m_i_8 => \pteout_m_i_2[17]\, pteout_m_i_18 => - \pteout_m_i_2[27]\, pteout_m_i_6 => \pteout_m_i_3[15]\, - pteout_m_i_5 => \pteout_m_i_2[14]\, pteout_m_i_11 => - \pteout_m_i_2[20]\, pteout_m_i_10 => \pteout_m_i_2[19]\, - pteout_m_i_9 => \pteout_m_i_3[18]\, pteout_m_i_7 => - \pteout_m_i_3[16]\, pteout_m_i_4 => \pteout_m_i_2[13]\, - pteout_m_i_1 => \pteout_m_i_2[10]\, pteout_m_i_0_d0 => - \pteout_m_i_2[9]\, pteout_m_i_3 => \pteout_m_i_2[12]\, - un2_wb_acc_iv_1_11 => \un2_wb_acc_iv_1[20]\, - un2_wb_acc_iv_1_10 => \un2_wb_acc_iv_1[19]\, - un2_wb_acc_iv_1_9 => \un2_wb_acc_iv_1[18]\, - un2_wb_acc_iv_1_7 => \un2_wb_acc_iv_1[16]\, - un2_wb_acc_iv_1_4 => \un2_wb_acc_iv_1[13]\, - un2_wb_acc_iv_1_1 => \un2_wb_acc_iv_1[10]\, - un2_wb_acc_iv_1_0 => \un2_wb_acc_iv_1[9]\, - un2_wb_acc_iv_1_3 => \un2_wb_acc_iv_1[12]\, - data_1_3_i_a3_0_1(12) => \data_1_3_i_a3_0_1[12]\, - data_1_3_i_a3_1_0 => \data_1_3_i_a3_1[27]\, - data_1_3_i_a3_1_2 => \data_1_3_i_a3_1[29]\, - un1_cam_hitaddr(58) => \un1_cam_hitaddr[58]\, pteout_31 - => \pteout_2[31]\, pteout_30 => \pteout_2[30]\, - pteout_29 => \pteout_2[29]\, pteout_28 => \pteout_2[28]\, - pteout_1 => \pteout_2[1]\, pteout_0_d0 => \pteout_2[0]\, - pteout_7 => \pteout_2[7]\, pteout_17 => \pteout_2[17]\, - pteout_4 => \pteout_3[4]\, pteout_3 => \pteout_3[3]\, - pteout_2 => \pteout_3[2]\, pteout_27 => \pteout_2[27]\, - pteout_26 => \pteout_2[26]\, pteout_24 => \pteout_2[24]\, - pteout_22 => \pteout_2[22]\, pteout_21 => \pteout_2[21]\, - pteout_15 => \pteout_2[15]\, pteout_14 => \pteout_2[14]\, - pteout_6 => \pteout_2[6]\, pteout_20 => \pteout_2[20]\, - pteout_19 => \pteout_2[19]\, pteout_18 => \pteout_2[18]\, - pteout_16 => \pteout_2[16]\, pteout_13 => \pteout_2[13]\, - pteout_10 => \pteout_2[10]\, pteout_9 => \pteout_2[9]\, - pteout_12 => \pteout_2[12]\, pteout_8 => \pteout_2[8]\, - pteout_23 => \pteout_2[23]\, pteout_25 => \pteout_2[25]\, - pteout_11 => \pteout_2[11]\, pteout_m_i_0_18 => - \pteout_m_i_0_3[26]\, pteout_m_i_0_16 => - \pteout_m_i_0_2[24]\, pteout_m_i_0_14 => - \pteout_m_i_0_2[22]\, pteout_m_i_0_13 => - \pteout_m_i_0_2[21]\, pteout_m_i_0_0 => - \pteout_m_i_0_3[8]\, pteout_m_i_0_15 => - \pteout_m_i_0_3[23]\, pteout_m_i_0_17 => - \pteout_m_i_0_2[25]\, pteout_m_i_0_3 => - \pteout_m_i_0_2[11]\, N_78 => N_78, N_262 => N_262, N_264 - => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, N_1471 - => N_1471, NEEDSYNC => NEEDSYNC_1, N_1470 => N_1470, - s2_flush => s2_flush, un1_rst_i_0 => \un1_rst_i_0\, - N_1469 => N_1469, N_1497 => N_1497, s2_flush_1 => - s2_flush_1, trans_op => trans_op, N_2483 => N_2483, N_661 - => N_661, N_3046 => N_3046, N_3043 => N_3043, - WBNEEDSYNC_m => WBNEEDSYNC_m_2, N_61 => N_61, hit_1 => - hit_0, hit_0 => hit, hit => hit_2, M_1 => M_1); - - \r.s2_entry_0_RNILDGF[1]\ : MX2 - port map(A => N_1116, B => N_1150, S => \s2_entry_0[1]\, Y - => N_1184); - - \r.s2_tlbstate_RNIMSES[0]\ : OR2A - port map(A => N_2544, B => N_89, Y => N_2547); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.walk_transdata.data_RNI7K3D[22]\ : OR2B - port map(A => walk_use_1, B => \data[22]\, Y => N_3036); - - \r.s2_entry_RNI21VA7[0]\ : AOI1B - port map(A => fault_pro_5_m_0_3, B => fault_pro_5_m_0_2, C - => \un1_dtlb0_1_m_0_i[45]\, Y => \fault_pro_1_iv_2\); - - \r.walk_transdata.data[0]\ : DFN1E0 - port map(D => \data[0]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[0]\); - - \p0.tlbcam_tagin.I3_1_i_0_RNO_1[1]\ : OR2A - port map(A => s2_flush_0, B => \data_0[13]\, Y => N_3039); - - \p0.tlbcam_tagin.I3_1_i_0_RNO[1]\ : AND2 - port map(A => N_3041, B => N_3039, Y => \I3_1_i_0_0[1]\); - - \r.s2_entry_1_RNIDUIN1[0]\ : MX2 - port map(A => N_1189, B => N_1291, S => \s2_entry_1[0]\, Y - => \adata[21]\); - - \r.s2_entry_1[0]\ : DFN1E0 - port map(D => \s2_entry_1_0[0]\, CLK => lclk_c, E => N_53, - Q => \s2_entry_1[0]\); - - \r.s2_data_RNI2DON[23]\ : NOR2A - port map(A => N_3063, B => \data_0[23]\, Y => N_2941); - - \r.walk_transdata.data_RNI904D[25]\ : NOR2A - port map(A => \walk_use_0\, B => \data_1[25]\, Y => N_2927); - - \r.s2_entry_RNIBQRC1[0]\ : MX2 - port map(A => N_1188, B => N_1290, S => \s2_entry[0]\, Y - => \adata[20]\); - - \r.s2_data[26]\ : DFN1E1 - port map(D => data_0_26, CLK => lclk_c, E => s1finished_1, - Q => \data[26]\); - - \tlbcam0.4.tag0\ : mmutlbcam_2_0 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1_0(4) => \tlbcam_write_op_1_1_0[4]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0 => hrdata_0_d0, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_7 => hrdata_7, - tlbcam_write_op_1(4) => \tlbcam_write_op_1[4]\, - un1_cam_hitaddr_1_0 => \un1_cam_hitaddr_1[56]\, - un1_cam_hitaddr_1_6 => \un1_cam_hitaddr_1[62]\, - un1_cam_hitaddr_1_5 => \un1_cam_hitaddr_1[61]\, - un1_cam_hitaddr_0 => \un1_cam_hitaddr[56]\, - un1_cam_hitaddr_2 => \un1_cam_hitaddr[58]\, - un1_cam_hitaddr_4 => \un1_cam_hitaddr[60]\, - un1_cam_hitaddr_5 => \un1_cam_hitaddr[61]\, - un1_cam_hitaddr_6 => \un1_cam_hitaddr[62]\, - un1_cam_hitaddr_1_d0 => \un1_cam_hitaddr[57]\, - pteout_0(4) => \pteout[4]\, pteout_0(3) => \pteout[3]\, - pteout_0(2) => \pteout[2]\, cam_hitaddr_18(1) => - \cam_hitaddr_18[1]\, LVL_0(1) => \LVL[1]\, LVL_0(0) => - \LVL[0]\, TYP_1(2) => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, - TYP_1_0(0) => \TYP_1_0[0]\, tlbcam_write_op_1_0(4) => - \tlbcam_write_op_1_0[4]\, I1_1_i_0_0(0) => - \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, - pteout_31 => \pteout[31]\, pteout_30 => \pteout[30]\, - pteout_29 => \pteout[29]\, pteout_28 => \pteout[28]\, - pteout_1 => \pteout[1]\, pteout_0_d0 => \pteout[0]\, - pteout_7 => \pteout[7]\, pteout_17 => \pteout[17]\, - pteout_4 => \pteout_0[4]\, pteout_3 => \pteout_0[3]\, - pteout_2 => \pteout_0[2]\, pteout_27 => \pteout[27]\, - pteout_6 => \pteout[6]\, pteout_26 => \pteout[26]\, - pteout_25 => \pteout[25]\, pteout_24 => \pteout[24]\, - pteout_23 => \pteout[23]\, pteout_22 => \pteout[22]\, - pteout_21 => \pteout[21]\, pteout_20 => \pteout[20]\, - pteout_19 => \pteout[19]\, pteout_18 => \pteout[18]\, - pteout_16 => \pteout[16]\, pteout_15 => \pteout[15]\, - pteout_14 => \pteout[14]\, pteout_13 => \pteout[13]\, - pteout_12 => \pteout[12]\, pteout_11 => \pteout[11]\, - pteout_10 => \pteout[10]\, pteout_9 => \pteout[9]\, - pteout_8 => \pteout[8]\, ctx(4) => ctx(4), I3_1_i(3) => - \I3_1_i[3]\, ctx_0_7 => ctx_0(7), ctx_0_5 => ctx_0(5), - ctx_0_3 => ctx_0(3), ctx_0_1 => ctx_0(1), ctx_0_0 => - ctx_0(0), ctx_0_2 => ctx_0(2), ctx_0_6 => ctx_0(6), - I1_1_5 => \I1_1[6]\, I1_1_2 => \I1_1[3]\, I1_1_0 => - \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_3 => \I1_1[4]\, - I1_1_6 => \I1_1[7]\, I2_1(5) => \I2_1[5]\, I2_1(4) => - \I2_1[4]\, I2_1(3) => \I2_1[3]\, I2_1(2) => \I2_1[2]\, - I2_1(1) => \I2_1[1]\, I2_1(0) => \I2_1[0]\, I3_1_4 => - \I3_1[4]\, I3_1_0 => \I3_1[0]\, I3_1_5 => \I3_1[5]\, - LVL(1) => \LVL_0[1]\, LVL(0) => \LVL_0[0]\, pteout_m_i_8 - => \pteout_m_i[17]\, pteout_m_i_18 => \pteout_m_i[27]\, - pteout_m_i_11 => \pteout_m_i[20]\, pteout_m_i_10 => - \pteout_m_i[19]\, pteout_m_i_9 => \pteout_m_i[18]\, - pteout_m_i_7 => \pteout_m_i[16]\, pteout_m_i_6 => - \pteout_m_i[15]\, pteout_m_i_4 => \pteout_m_i[13]\, - pteout_m_i_3 => \pteout_m_i[12]\, pteout_m_i_1 => - \pteout_m_i[10]\, pteout_m_i_0_d0 => \pteout_m_i[9]\, - pteout_m_i_5 => \pteout_m_i[14]\, un2_wb_acc_iv_2(14) => - \un2_wb_acc_iv_2[14]\, pteout_m_i_0_18 => - \pteout_m_i_0[26]\, pteout_m_i_0_15 => \pteout_m_i_0[23]\, - pteout_m_i_0_13 => \pteout_m_i_0[21]\, pteout_m_i_0_0_d0 - => \pteout_m_i_0[8]\, pteout_m_i_0_17 => - \pteout_m_i_0[25]\, data_1_3_i_a3_2(29) => - \data_1_3_i_a3_2[29]\, data_1_3_i_a3_3_2 => - \data_1_3_i_a3_3[28]\, data_1_3_i_a3_3_0 => - \data_1_3_i_a3_3[26]\, data_1_3_i_a3_5_2 => - \data_1_3_i_a3_5[28]\, data_1_3_i_a3_5_0 => - \data_1_3_i_a3_5[26]\, pteout_m_i_0_0_13 => - \pteout_m_i_0[24]\, pteout_m_i_0_0_11 => - \pteout_m_i_0[22]\, pteout_m_i_0_0_0 => - \pteout_m_i_0[11]\, data_1_3_i_a3_0_2(15) => - \data_1_3_i_a3_0_2[15]\, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, - N_1496 => N_1496, N_1468 => N_1468, NEEDSYNC => - NEEDSYNC_3, N_1467 => N_1467, s2_flush => s2_flush, - un1_rst_i_0 => \un1_rst_i_0\, N_1466 => N_1466, N_1495 - => N_1495, trans_op => trans_op, s2_flush_1 => - s2_flush_1, N_2483 => N_2483, M_1 => M_1, N_661 => N_661, - N_3046 => N_3046, N_3043 => N_3043, N_61 => N_61, hit_1 - => hit, hit_0 => hit_0, N_2551 => N_2551, - un1_cam_hitaddr_4_0 => un1_cam_hitaddr_4_0, WBNEEDSYNC_m - => WBNEEDSYNC_m, hit => hit_1); - - \r.s2_entry_RNIG3141[0]\ : NOR2A - port map(A => \adata[4]\, B => \adata[3]\, Y => - fault_pro_5_m_0_3); - - \r.s2_data_RNIOMAJ3[23]\ : NOR3 - port map(A => N_2943, B => N_2940, C => N_2941, Y => N_236); - - \r.s2_tlbstate_RNILVMNK[1]\ : OR3A - port map(A => twowner_0(0), B => \s2_tlbstate[1]\, C => - \N_2532\, Y => N_2488); - - \r.walk_transdata.data[23]\ : DFN1E0 - port map(D => N_693, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[23]\); - - \r.s2_tlbstate_RNIBBSOK[1]\ : OR2B - port map(A => rst, B => cache_0_sqmuxa_0, Y => nrepe); - - \r.s2_data_RNI30FF2[21]\ : NOR3 - port map(A => N_3009, B => N_3006, C => N_3007, Y => N_419); - - \r.s2_data[15]\ : DFN1E1 - port map(D => data_0_15, CLK => lclk_c, E => s1finished_1, - Q => \data[15]\); - - \r.s2_data_RNIT4SP5[26]\ : OA1C - port map(A => N_3059, B => \data[26]\, C => - \data_1_i_m2_i_0[26]\, Y => N_192); - - \r.s2_data_RNI6HHE[8]\ : OR2B - port map(A => \data[8]\, B => s2_flush, Y => \TYP_1[0]\); - - \r.s2_entry_1_RNI3EJF[1]\ : MX2 - port map(A => N_1216, B => N_1250, S => \s2_entry_1[1]\, Y - => N_1284); - - \r.s2_data_RNIV2D32[27]\ : OA1C - port map(A => N_3059, B => \data_0[27]\, C => - \data_1_i_m2_i_0[27]\, Y => N_293); - - \r.s2_data_RNIJSQP5[25]\ : OA1C - port map(A => N_3059, B => \data[25]\, C => - \data_1_i_m2_i_0[25]\, Y => N_190); - - \r.s2_data_RNI75PN[19]\ : NOR2A - port map(A => N_3063, B => \data_0[19]\, Y => N_2999); - - \r.walk_transdata.data[14]\ : DFN1E0 - port map(D => N_37, CLK => lclk_c, E => cache_0_sqmuxa_0, Q - => \data_1[14]\); - - \r.s2_tlbstate_RNITSPN91[1]\ : OR2 - port map(A => sync_isw_RNII96B91, B => N_2522, Y => - s2_tlbstate_3); - - \cam_addr[12]\ : MX2 - port map(A => maddress(12), B => data_0_12, S => trans_op_0, - Y => \cam_addr[12]_net_1\); - - \r.s2_entry_0_RNIHUSSN2_6[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[1]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_0[0]\); - - \r.s2_tlbstate_RNO[1]\ : AOI1B - port map(A => \s2_tlbstate_ns_0_0_0[1]\, B => N_2509, C => - rst, Y => \s2_tlbstate_nss[1]\); - - \r.s2_data[28]\ : DFN1E1 - port map(D => data_0_28, CLK => lclk_c, E => s1finished, Q - => \data[28]\); - - \r.s2_entry_0_RNI73UP[1]\ : MX2 - port map(A => N_1129, B => N_1163, S => \s2_entry_0[1]\, Y - => N_1197); - - \r.walk_transdata.data[21]\ : DFN1E0 - port map(D => N_691, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[21]\); - - \r.walk_fault.fault_pro_RNO_0\ : NOR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => \fault_read\, Y => fault_pro_1_iv_0_a2_0_0); - - \r.s2_entry_RNIG8073[0]\ : NOR2A - port map(A => N_3060, B => \adata[20]\, Y => N_3010); - - \r.s2_entry_1_RNIOLEP[1]\ : MX2 - port map(A => N_1203, B => N_1237, S => \s2_entry_1[1]\, Y - => N_1271); - - \r.walk_transdata.data_RNO[29]\ : MX2 - port map(A => \data_0[29]\, B => N_78_0, S => N_2571, Y => - N_2747); - - \r.s2_entry_1_RNII30Q[1]\ : MX2 - port map(A => N_1220, B => N_1254, S => \s2_entry_1[1]\, Y - => N_1288); - - \r.s2_entry_1_RNI7HM21[0]\ : MX2 - port map(A => N_1176, B => N_1278, S => \s2_entry_1[0]\, Y - => \adata[8]\); - - \r.s2_entry_RNIKQOQN2_2[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[1]\, C => \s2_entry[0]\, Y => - \tlbcam_write_op_1[0]\); - - \r.s2_entry_RNIKQOQN2_0[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry[0]\, C => - \tlbcam_write_op_1_1[1]\, Y => \tlbcam_write_op_1[1]\); - - \r.s2_entry[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry[2]\); - - \r.s2_data[6]\ : DFN1E1 - port map(D => un1_m0_2_81, CLK => lclk_c, E => s1finished, - Q => \data[6]\); - - \r.walk_fault.fault_pro_RNO_3\ : NOR3B - port map(A => \s2_tlbstate[0]\, B => hrdata_0_4, C => - \s2_tlbstate[1]\, Y => fault_pro_1_iv_0_a2_0); - - \r.s2_data_RNIQU0N1[16]\ : NOR2 - port map(A => \data_0[16]\, B => N_3066, Y => N_2912); - - \r.s2_data_RNINBVQ1[24]\ : NOR2A - port map(A => N_3059, B => \data[24]\, Y => N_3012); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.s2_flush_0_RNIB92J1\ : NOR2B - port map(A => \s1finished_0\, B => flush_op, Y => - s2_flush_1_0); - - \r.s2_data_RNID4TM[15]\ : MX2C - port map(A => \cam_addr[15]_net_1\, B => \data[15]\, S => - s2_flush_0, Y => \I3_1_i[3]\); - - \r.s2_entry_RNI3NF9[1]\ : MX2 - port map(A => N_1235, B => N_1269, S => \s2_entry[1]\, Y - => N_1303); - - \p0.un9_twneedsync_i_a2_i_o2_i_a4\ : OR2B - port map(A => un9_twneedsync_i_a2_i_o2_i_a4_0, B => - fault_trans_i_2, Y => \N_86_i\); - - \r.s2_entry_1_RNI6K2Q[1]\ : MX2 - port map(A => N_1225, B => N_1259, S => \s2_entry_1[1]\, Y - => N_1293); - - \r.s2_data_RNIR2442[12]\ : AO1D - port map(A => \data[12]\, B => N_3066, C => N_2904, Y => - \data_1_i_m2_i_0[12]\); - - \r.walk_transdata.data[7]\ : DFN1E0 - port map(D => \data[7]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[7]\); - - \r.s2_entry_RNIKH0I[0]\ : MX2 - port map(A => N_1171, B => N_1273, S => \s2_entry[0]\, Y - => \adata[3]\); - - \r.walk_use_RNIHJTM_0\ : NOR2 - port map(A => \un1_acc[33]\, B => walk_use, Y => N_3062); - - \cam_addr[31]\ : MX2 - port map(A => maddress(31), B => data_0_31, S => trans_op_0, - Y => \cam_addr[31]_net_1\); - - \r.s2_tlbstate_RNI9HRIO2[0]\ : OR2A - port map(A => N_2547, B => dr1write_0_sqmuxa, Y => N_25); - - \r.s2_entry_RNIC9CD[1]\ : MX2 - port map(A => N_1113, B => N_1147, S => \s2_entry[1]\, Y - => N_1181); - - \r.s2_entry_1_RNIDJN21[0]\ : MX2 - port map(A => N_1184, B => N_1286, S => \s2_entry_1[0]\, Y - => \adata[16]\); - - \cam_addr[22]\ : MX2 - port map(A => maddress(22), B => data_1_10, S => trans_op, - Y => \cam_addr[22]_net_1\); - - \r.s2_tlbstate_RNO[0]\ : AOI1B - port map(A => \s2_tlbstate_ns_0_0_0[0]\, B => N_2539, C => - rst, Y => \s2_tlbstate_nss[0]\); - - \r.s2_entry_1_RNI8FMN1[0]\ : MX2 - port map(A => N_1192, B => N_1294, S => \s2_entry_1[0]\, Y - => \adata[24]\); - - \p0.tlbcam_tagin.I3_1_i_0[1]\ : NAND2 - port map(A => N_3040, B => \I3_1_i_0_0[1]\, Y => N_61); - - \r.s2_data[16]\ : DFN1E1 - port map(D => data_1_4, CLK => lclk_c, E => s1finished_1, Q - => \data_0[16]\); - - \r.walk_transdata.data_RNIDG4D[19]\ : NOR2A - port map(A => walk_use_1, B => \data[19]\, Y => N_2998); - - \r.s2_read_RNI0BTI2\ : NOR3 - port map(A => N_2241, B => fault_pro_1_m_0_4_0, C => - \adata[2]\, Y => fault_pro_1_m_0_4); - - \p0.tlbcam_tagin.I3_1_i_0_RNO_0[1]\ : OR3 - port map(A => trans_op_0, B => s2_flush_0, C => - maddress(13), Y => N_3041); - - \r.walk_fault.fault_trans_RNIH26E2\ : OAI1 - port map(A => \fault_inv\, B => \fault_trans\, C => - un1_m0_2_0(35), Y => ft_1_i_a2_0(0)); - - \r.s2_entry_0_RNIDDGF[1]\ : MX2 - port map(A => N_1114, B => N_1148, S => \s2_entry_0[1]\, Y - => N_1182); - - \r.walk_fault.fault_pro\ : DFN1E1 - port map(D => fault_pro_1, CLK => lclk_c, E => N_25, Q => - fault_pro); - - \r.s2_needsync\ : DFN1E1 - port map(D => s2_needsync, CLK => lclk_c, E => s1finished, - Q => s2_needsync_1); - - \r.s2_entry_0_RNIK30Q[1]\ : MX2 - port map(A => N_1124, B => N_1158, S => \s2_entry_0[1]\, Y - => N_1192); - - \r.s2_data_RNIV0ON[20]\ : NOR2A - port map(A => N_3063, B => \data_0[20]\, Y => N_3003); - - \r.walk_transdata.data[13]\ : DFN1E0 - port map(D => N_2735, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data_1[13]\); - - \r.s2_flush_RNI97TV\ : OA1B - port map(A => N_2543, B => s2_flush, C => N_89, Y => N_2552); - - \r.s2_entry_1_RNITTSH3[0]\ : OR2B - port map(A => \adata[26]\, B => N_3060, Y => N_2922); - - \r.s2_tlbstate[1]\ : DFN1 - port map(D => \s2_tlbstate_nss[1]\, CLK => lclk_c, Q => - \s2_tlbstate[1]\); - - \r.walk_transdata.data[28]\ : DFN1E0 - port map(D => \data_3[28]\, CLK => lclk_c, E => - cache_0_sqmuxa, Q => \data_2[28]\); - - \r.s2_su\ : DFN1E1 - port map(D => su, CLK => lclk_c, E => s1finished, Q => - \fault_su\); - - \r.s2_entry_1_RNI8TIF[1]\ : MX2 - port map(A => N_1210, B => N_1244, S => \s2_entry_1[1]\, Y - => N_1278); - - \r.s2_data_RNIJL0T4[13]\ : OA1C - port map(A => N_3065, B => \adata[9]\, C => - \data_1_i_m2_i_0[13]\, Y => N_2887); - - \r.s2_entry_0_RNIQ23VN2_1[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[2]\, Y => - \tlbcam_write_op_1_0[3]\); - - \r.s2_data[18]\ : DFN1E1 - port map(D => data_0_18, CLK => lclk_c, E => s1finished_1, - Q => \data[18]\); - - \p0.transdata.data_1_i_m2_i_a2_RNI5BD8[27]\ : OR2 - port map(A => N_2957, B => N_2959, Y => - \data_1_i_m2_i_0[27]\); - - \r.walk_use_0_RNIS8NH3\ : OR3A - port map(A => \un1_dtlb0_1_m_0_1[45]\, B => \adata[3]\, C - => \adata[2]\, Y => \un1_dtlb0_1_m_0_i[45]\); - - \r.walk_transdata.data[11]\ : DFN1E0 - port map(D => \data[11]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[11]\); - - \r.walk_fault.fault_pro_RNO_2\ : OAI1 - port map(A => \fault_read\, B => \fault_su\, C => - hrdata_0_2, Y => N_97); - - \r.s2_entry_0_RNI0K1Q[1]\ : MX2 - port map(A => N_1127, B => N_1161, S => \s2_entry_0[1]\, Y - => N_1195); - - \p0.tlb_checkfault.un54_fault_pro_m_0\ : OR2 - port map(A => su, B => read, Y => un54_fault_pro_m_0); - - \r.walk_transdata.data_RNO[28]\ : MX2 - port map(A => \data[28]\, B => hrdata_0_24, S => N_2571, Y - => \data_3[28]\); - - \r.s2_data[5]\ : DFN1E1 - port map(D => un1_m0_2_80, CLK => lclk_c, E => s1finished, - Q => \data[5]\); - - \r.walk_transdata.data[25]\ : DFN1E0 - port map(D => N_2738, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data_1[25]\); - - \tlbcam0.1.tag0\ : mmutlbcam_2_0_5 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - hrdata_0_27 => hrdata_0_27, hrdata_0_26 => hrdata_0_26, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_21 => hrdata_0_21, hrdata_0_18 => hrdata_0_18, - hrdata_0_16 => hrdata_0_16, hrdata_0_15 => hrdata_0_15, - hrdata_0_12 => hrdata_0_12, hrdata_0_8 => hrdata_0_8, - hrdata_0_1 => hrdata_0_1, hrdata_0_0 => hrdata_0_0, - hrdata_0_4 => hrdata_0_4, hrdata_0_3 => hrdata_0_3, - hrdata_0_2 => hrdata_0_2, tlbcam_write_op_1_1_0(1) => - \tlbcam_write_op_1_1_0[1]\, data(31) => \data[31]\, - data(30) => \data[30]\, data(29) => \data_0[29]\, - data(28) => \data[28]\, data(27) => \data_0[27]\, - data(26) => \data[26]\, data(25) => \data[25]\, data(24) - => \data[24]\, data(23) => \data_0[23]\, data(22) => - \data_0[22]\, data(21) => \data_0[21]\, data(20) => - \data_0[20]\, data(19) => \data_0[19]\, data(18) => - \data[18]\, data(17) => \data_1[17]\, data(16) => - \data_0[16]\, data(15) => \data[15]\, data(14) => - \data[14]\, data(13) => \data_0[13]\, data(12) => - \data[12]\, s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => - \s2_ctx[6]\, s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => - \s2_ctx[4]\, s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => - \s2_ctx[2]\, s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => - \s2_ctx[0]\, hrdata_24 => hrdata_31, hrdata_23 => - hrdata_30, hrdata_22 => hrdata_29, hrdata_21 => hrdata_28, - hrdata_17 => hrdata_24, hrdata_10 => hrdata_17, hrdata_7 - => hrdata_14, hrdata_6 => hrdata_13, hrdata_4 => - hrdata_11, hrdata_3 => hrdata_10, hrdata_2 => hrdata_9, - hrdata_0_d0 => hrdata_7, tlbcam_write_op_1(1) => - \tlbcam_write_op_1[1]\, I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, - un1_cam_hitaddr_1_0 => \un1_cam_hitaddr_1[56]\, - un1_cam_hitaddr_1_5 => \un1_cam_hitaddr_1[61]\, - un1_cam_hitaddr_1_6 => \un1_cam_hitaddr_1[62]\, TYP_1(2) - => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, TYP_1(0) => - \TYP_1[0]\, s2_entry(2) => \s2_entry[2]\, pteout_1(4) => - \pteout_3[4]\, pteout_1(3) => \pteout_3[3]\, pteout_1(2) - => \pteout_4[2]\, LVL_1(0) => \LVL_4[0]\, - tlbcam_write_op_1_0(1) => \tlbcam_write_op_1_0[1]\, - I1_1_i_0_0(0) => \I1_1_i_0_0[0]\, pteout_m_i_8 => - \pteout_m_i_1[17]\, pteout_m_i_18 => \pteout_m_i_1[27]\, - pteout_m_i_11 => \pteout_m_i_1[20]\, pteout_m_i_10 => - \pteout_m_i_1[19]\, pteout_m_i_9 => \pteout_m_i_1[18]\, - pteout_m_i_7 => \pteout_m_i_1[16]\, pteout_m_i_6 => - \pteout_m_i_1[15]\, pteout_m_i_5 => \pteout_m_i_1[14]\, - pteout_m_i_4 => \pteout_m_i_1[13]\, pteout_m_i_3 => - \pteout_m_i_1[12]\, pteout_m_i_1 => \pteout_m_i_1[10]\, - pteout_m_i_0_d0 => \pteout_m_i_1[9]\, pteout_m_i_0_18 => - \pteout_m_i_0_1[26]\, pteout_m_i_0_17 => - \pteout_m_i_0_1[25]\, pteout_m_i_0_16 => - \pteout_m_i_0_1[24]\, pteout_m_i_0_15 => - \pteout_m_i_0_1[23]\, pteout_m_i_0_14 => - \pteout_m_i_0_1[22]\, pteout_m_i_0_13 => - \pteout_m_i_0_1[21]\, pteout_m_i_0_3 => - \pteout_m_i_0_1[11]\, pteout_m_i_0_0 => - \pteout_m_i_0_1[8]\, LVL_0(1) => \LVL_2[1]\, LVL_0(0) => - \LVL_3[0]\, s2_entry_3(2) => \s2_entry_3[2]\, - s2_entry_2(2) => \s2_entry_2[2]\, pteout_0_17 => - \pteout_2[17]\, pteout_0_4 => \pteout_4[4]\, pteout_0_3 - => \pteout_4[3]\, pteout_0_31 => \pteout_2[31]\, - pteout_0_30 => \pteout_2[30]\, pteout_0_29 => - \pteout_2[29]\, pteout_0_28 => \pteout_2[28]\, - pteout_0_27 => \pteout_2[27]\, pteout_0_26 => - \pteout_2[26]\, pteout_0_25 => \pteout_2[25]\, - pteout_0_24 => \pteout_2[24]\, pteout_0_23 => - \pteout_2[23]\, pteout_0_22 => \pteout_2[22]\, - pteout_0_21 => \pteout_2[21]\, pteout_0_20 => - \pteout_2[20]\, pteout_0_19 => \pteout_2[19]\, - pteout_0_18 => \pteout_2[18]\, pteout_0_16 => - \pteout_2[16]\, pteout_0_15 => \pteout_2[15]\, - pteout_0_14 => \pteout_2[14]\, pteout_0_13 => - \pteout_2[13]\, pteout_0_12 => \pteout_2[12]\, - pteout_0_11 => \pteout_2[11]\, pteout_0_10 => - \pteout_2[10]\, pteout_0_9 => \pteout_2[9]\, pteout_0_8 - => \pteout_2[8]\, pteout_0_7 => \pteout_2[7]\, - pteout_0_6 => \pteout_2[6]\, pteout_0_2 => \pteout_3[2]\, - pteout_0_1 => \pteout_2[1]\, pteout_0_0 => \pteout_2[0]\, - ctx_0_d0 => ctx(0), ctx_1 => ctx(1), ctx_4 => ctx(4), - ctx_5 => ctx(5), ctx_7 => ctx(7), ctx_3 => ctx(3), - cam_hitaddr_21_1(0) => \cam_hitaddr_21_1[0]\, - un1_cam_hitaddr(62) => \un1_cam_hitaddr[62]\, ctx_0_0 => - ctx_0(2), ctx_0_4 => ctx_0(6), I1_1_6 => \I1_1[7]\, - I1_1_3 => \I1_1[4]\, I1_1_2 => \I1_1[3]\, I1_1_0 => - \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_5 => \I1_1[6]\, - I2_1(5) => \I2_1[5]\, I2_1(4) => \I2_1[4]\, I2_1(3) => - \I2_1[3]\, I2_1(2) => \I2_1[2]\, I2_1(1) => \I2_1[1]\, - I2_1(0) => \I2_1[0]\, I3_1_5 => \I3_1[5]\, I3_1_4 => - \I3_1[4]\, I3_1_0 => \I3_1[0]\, I3_1_i(3) => \I3_1_i[3]\, - LVL_1_d0 => \LVL_4[1]\, cam_hitaddr_18(1) => - \cam_hitaddr_18[1]\, cam_hitaddr_21(0) => - \cam_hitaddr_21[0]\, N_78 => N_78, N_262 => N_262, N_264 - => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, N_3043 - => N_3043, s2_flush => s2_flush, N_1206 => N_1206, - un1_rst_i_0 => \un1_rst_i_0\, N_1219 => N_1219, N_1482 - => N_1482, N_1471 => N_1471, N_1481 => N_1481, N_1205 - => N_1205, N_1470 => N_1470, N_1480 => N_1480, N_1235 - => N_1235, N_1469 => N_1469, N_1479 => N_1479, N_1497 - => N_1497, N_1505 => N_1505, NEEDSYNC => NEEDSYNC, - s2_flush_1 => s2_flush_1, trans_op => trans_op, N_2483 - => N_2483, N_3046 => N_3046, N_1234 => N_1234, N_1233 - => N_1233, N_1232 => N_1232, N_1231 => N_1231, N_1230 - => N_1230, N_1229 => N_1229, N_1228 => N_1228, N_1227 - => N_1227, N_1226 => N_1226, N_1225 => N_1225, N_1224 - => N_1224, N_1223 => N_1223, N_1222 => N_1222, N_1221 - => N_1221, N_1220 => N_1220, N_1218 => N_1218, N_1217 - => N_1217, N_1216 => N_1216, N_1215 => N_1215, N_1214 - => N_1214, N_1213 => N_1213, N_1212 => N_1212, N_1211 - => N_1211, N_1210 => N_1210, N_1209 => N_1209, N_1208 - => N_1208, N_1204 => N_1204, N_1203 => N_1203, N_1202 - => N_1202, N_2551 => N_2551, cam_hit_all_5_sqmuxa => - cam_hit_all_5_sqmuxa, cam_hit_all_5_sqmuxa_2 => - cam_hit_all_5_sqmuxa_2, cam_hit_all_5_sqmuxa_0_a2_0 => - cam_hit_all_5_sqmuxa_0_a2_0, accexc_6_3 => accexc_6_3, - accexc_6_4 => accexc_6_4, accexc_6 => \accexc_6\, N_661 - => N_661, N_61 => N_61, un1_cam_hitaddr_4_0 => - un1_cam_hitaddr_4_0, M_1 => M_1, accexc_6_2 => accexc_6_2, - WBNEEDSYNC_m => WBNEEDSYNC_m_2); - - \r.nrep_RNI2I59O9[2]\ : MX2 - port map(A => \nrep[2]\, B => N_2551, S => \s1finished_0\, - Y => \s2_entry_1[2]\); - - \p0.tlb_mergedata.v.walk_transdata.data_3_e[17]\ : OR2 - port map(A => lvl_i_1_0(1), B => lvl_i_1(0), Y => \N_3160\); - - \r.s2_entry_RNIKQOQN2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry[0]\, C => - \tlbcam_write_op_1_1[7]\, Y => \tlbcam_write_op_1[7]\); - - \r.walk_transdata.data_RNI6O3D[13]\ : NOR2A - port map(A => \walk_use_0\, B => \data_1[13]\, Y => N_2909); - - \r.s2_tlbstate_RNIJQGC1[1]\ : AOI1 - port map(A => N_2544, B => N_2265, C => N_2522, Y => - un1_m0_2_0_d0); - - \r.s2_needsync_RNO_3\ : AOI1B - port map(A => un1_tlbcami_3_0, B => tlbcamo_needsync_0, C - => NEEDSYNC_1, Y => s2_needsync_2); - - \r.s2_entry_1[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_1_0[2]\); - - \r.s2_entry_0_RNIQ23VN2_5[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[2]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_0[2]\); - - \r.walk_transdata.data_RNIFRDL3[28]\ : MX2 - port map(A => \data_1[28]\, B => \data_2[28]\, S => - walk_use, Y => un1_m0_2_29); - - \r.s2_su_RNICMUD\ : NOR3 - port map(A => \fault_read\, B => \fault_su\, C => - \walk_use_0\, Y => fault_pro_5_m_0_0); - - \r.s2_data[7]\ : DFN1E1 - port map(D => un1_m0_2_82, CLK => lclk_c, E => s1finished, - Q => \data[7]\); - - \r.s2_tlbstate_RNIU0761[1]\ : OAI1 - port map(A => N_2265, B => \s2_tlbstate[1]\, C => N_2544, Y - => N_2241); - - \r.walk_transdata.data_RNO[13]\ : MX2 - port map(A => hrdata_0_9, B => \data_0[13]\, S => \N_3160\, - Y => N_2735); - - \r.walk_transdata.data[27]\ : DFN1E0 - port map(D => N_2740, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[27]\); - - \r.s2_entry_1_RNI9RSO2[0]\ : NOR2A - port map(A => N_3065, B => \adata[11]\, Y => N_2976); - - \r.walk_use_1_RNI5E4Q1\ : NOR2A - port map(A => N_550, B => walk_use_1, Y => N_3059); - - \r.s2_tlbstate_RNI667LK[1]\ : OR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => N_82, Y => cache_0_sqmuxa); - - \r.s2_entry_0_RNIHUSSN2_3[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[7]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_1[6]\); - - \r.walk_transdata.data_RNO[16]\ : MX2 - port map(A => hrdata_0_12, B => \data_0[16]\, S => \N_3160\, - Y => N_2736); - - \r.s2_entry_RNIBV88[1]\ : MX2 - port map(A => N_1206, B => N_1240, S => \s2_entry[1]\, Y - => N_1274); - - \r.s2_entry_1_RNIIJVP[1]\ : MX2 - port map(A => N_1131, B => N_1165, S => \s2_entry_1[1]\, Y - => N_1199); - - \r.s2_ctx[5]\ : DFN1E1 - port map(D => ctx(5), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[5]\); - - dataram : syncramZ0_1 - port map(address(31) => address(31), address(30) => - address(30), address(29) => address(29), address(28) => - address(28), address(27) => address(27), address(26) => - address(26), address(25) => address(25), address(24) => - address(24), address(23) => address(23), address(22) => - address(22), address(21) => address(21), address(20) => - address(20), address(19) => address(19), address(18) => - address(18), address(17) => address(17), address(16) => - address(16), address(15) => address(15), address(14) => - address(14), address(13) => address(13), address(12) => - address(12), address(11) => address(11), address(10) => - address(10), address(9) => address(9), address(8) => - address(8), address(7) => address(7), address(6) => - address(6), address(5) => address(5), address(4) => - address(4), address(3) => address(3), address(2) => - address(2), s2_entry(2) => \s2_entry[2]\, s2_entry(1) => - \s2_entry[1]\, s2_entry(0) => \s2_entry[0]\, twowner_1(0) - => twowner_1(0), aaddr(31) => aaddr(31), aaddr(30) => - aaddr(30), aaddr(29) => aaddr(29), aaddr(28) => aaddr(28), - aaddr(27) => aaddr(27), aaddr(26) => aaddr(26), aaddr(25) - => aaddr(25), aaddr(24) => aaddr(24), aaddr(23) => - aaddr(23), aaddr(22) => aaddr(22), aaddr(21) => aaddr(21), - aaddr(20) => aaddr(20), aaddr(19) => aaddr(19), aaddr(18) - => aaddr(18), aaddr(17) => aaddr(17), aaddr(16) => - aaddr(16), aaddr(15) => aaddr(15), aaddr(14) => aaddr(14), - aaddr(13) => aaddr(13), aaddr(12) => aaddr(12), aaddr(11) - => aaddr(11), aaddr(10) => aaddr(10), aaddr(9) => - aaddr(9), aaddr(8) => aaddr(8), aaddr(7) => aaddr(7), - aaddr(6) => aaddr(6), aaddr(5) => aaddr(5), aaddr(4) => - aaddr(4), aaddr(3) => aaddr(3), aaddr(2) => aaddr(2), - dr1write_0_sqmuxa => dr1write_0_sqmuxa, syncramZ0_1_VCC - => mmutlb_10_8_2_1_0_VCC, lclk_c => lclk_c, N_709 => - N_709); - - \tlbcam0.7.tag0\ : mmutlbcam_2_0_3 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1_0(7) => \tlbcam_write_op_1_1_0[7]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0 => hrdata_0_d0, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_7 => hrdata_7, - tlbcam_write_op_1(7) => \tlbcam_write_op_1[7]\, - cam_hitaddr_18(1) => \cam_hitaddr_18[1]\, LVL_0(1) => - \LVL_2[1]\, TYP_1(2) => \TYP_1[2]\, TYP_1(1) => - \TYP_1[1]\, TYP_1(0) => \TYP_1[0]\, - tlbcam_write_op_1_0(7) => \tlbcam_write_op_1_0[7]\, - I1_1_i_0_0(0) => \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => - \I3_1_i_0_0[2]\, ctx_0_3 => ctx_0(3), ctx_0_0 => ctx_0(0), - I3_1_i(3) => \I3_1_i[3]\, ctx_6 => ctx(7), ctx_4 => - ctx(5), ctx_3 => ctx(4), ctx_0_d0 => ctx(1), ctx_1 => - ctx(2), ctx_5 => ctx(6), I2_1(5) => \I2_1[5]\, I2_1(4) - => \I2_1[4]\, I2_1(3) => \I2_1[3]\, I2_1(2) => \I2_1[2]\, - I2_1(1) => \I2_1[1]\, I2_1(0) => \I2_1[0]\, I1_1_6 => - \I1_1[7]\, I1_1_3 => \I1_1[4]\, I1_1_2 => \I1_1[3]\, - I1_1_0 => \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_5 => - \I1_1[6]\, I3_1_4 => \I3_1[4]\, I3_1_0 => \I3_1[0]\, - I3_1_5 => \I3_1[5]\, LVL(1) => \LVL_3[1]\, LVL(0) => - \LVL_2[0]\, TYP_1_0(0) => \TYP_1_0[0]\, pteout_m_i_9 => - \pteout_m_i_2[18]\, pteout_m_i_7 => \pteout_m_i_2[16]\, - pteout_m_i_5 => \pteout_m_i[14]\, pteout_m_i_11 => - \pteout_m_i[20]\, pteout_m_i_10 => \pteout_m_i[19]\, - pteout_m_i_8 => \pteout_m_i[17]\, pteout_m_i_6 => - \pteout_m_i[15]\, pteout_m_i_4 => \pteout_m_i[13]\, - pteout_m_i_1 => \pteout_m_i[10]\, pteout_m_i_0_d0 => - \pteout_m_i[9]\, pteout_m_i_18 => \pteout_m_i[27]\, - pteout_m_i_3 => \pteout_m_i[12]\, un2_wb_acc_iv_2_11 => - \un2_wb_acc_iv_2[20]\, un2_wb_acc_iv_2_10 => - \un2_wb_acc_iv_2[19]\, un2_wb_acc_iv_2_8 => - \un2_wb_acc_iv_2[17]\, un2_wb_acc_iv_2_6 => - \un2_wb_acc_iv_2[15]\, un2_wb_acc_iv_2_4 => - \un2_wb_acc_iv_2[13]\, un2_wb_acc_iv_2_1 => - \un2_wb_acc_iv_2[10]\, un2_wb_acc_iv_2_0 => - \un2_wb_acc_iv_2[9]\, un2_wb_acc_iv_2_18 => - \un2_wb_acc_iv_2[27]\, un2_wb_acc_iv_2_3 => - \un2_wb_acc_iv_2[12]\, data_1_3_i_a3_3(30) => - \data_1_3_i_a3_3[30]\, data_1_3_i_a3_5(30) => - \data_1_3_i_a3_5[30]\, pteout_m_i_0_17 => - \pteout_m_i_0[25]\, pteout_m_i_0_16 => \pteout_m_i_0[24]\, - pteout_m_i_0_15 => \pteout_m_i_0_2[23]\, pteout_m_i_0_14 - => \pteout_m_i_0[22]\, pteout_m_i_0_3 => - \pteout_m_i_0[11]\, pteout_m_i_0_0 => \pteout_m_i_0_2[8]\, - pteout_m_i_0_18 => \pteout_m_i_0[26]\, pteout_m_i_0_13 - => \pteout_m_i_0[21]\, pteout_31 => \pteout_1[31]\, - pteout_30 => \pteout_1[30]\, pteout_29 => \pteout_1[29]\, - pteout_28 => \pteout_1[28]\, pteout_1 => \pteout_1[1]\, - pteout_0 => \pteout_1[0]\, pteout_4 => \pteout_2[4]\, - pteout_3 => \pteout_2[3]\, pteout_2 => \pteout_2[2]\, - pteout_7 => \pteout_1[7]\, pteout_6 => \pteout_1[6]\, - pteout_25 => \pteout_1[25]\, pteout_24 => \pteout_1[24]\, - pteout_23 => \pteout_1[23]\, pteout_22 => \pteout_1[22]\, - pteout_18 => \pteout_1[18]\, pteout_16 => \pteout_1[16]\, - pteout_14 => \pteout_1[14]\, pteout_11 => \pteout_1[11]\, - pteout_8 => \pteout_1[8]\, pteout_20 => \pteout_1[20]\, - pteout_19 => \pteout_1[19]\, pteout_17 => \pteout_1[17]\, - pteout_15 => \pteout_1[15]\, pteout_13 => \pteout_1[13]\, - pteout_10 => \pteout_1[10]\, pteout_9 => \pteout_1[9]\, - pteout_27 => \pteout_1[27]\, pteout_12 => \pteout_1[12]\, - pteout_26 => \pteout_1[26]\, pteout_21 => \pteout_1[21]\, - un1_cam_hitaddr(56) => \un1_cam_hitaddr[56]\, - data_1_3_i_a3_2_0 => \data_1_3_i_a3_2[25]\, N_78 => N_78, - N_262 => N_262, N_264 => N_264, N_2482 => \N_2482\, - lclk_c => lclk_c, N_1498 => N_1498, NEEDSYNC => - NEEDSYNC_2, s2_flush => s2_flush, un1_rst_i_0 => - \un1_rst_i_0\, trans_op => trans_op, s2_flush_1 => - s2_flush_1, hit => hit_0, N_2483 => N_2483, M_1 => M_1, - N_3046 => N_3046, N_3043 => N_3043, N_61 => N_61, - WBNEEDSYNC_m => WBNEEDSYNC_m_1, N_661 => N_661); - - \r.s2_needsync_RNO\ : OR3C - port map(A => NEEDSYNC_3, B => s2_needsync_3, C => - s2_needsync_4, Y => s2_needsync); - - \r.s2_entry_1_RNIEASO2[0]\ : NOR2A - port map(A => N_3065, B => \adata[8]\, Y => N_2905); - - \r.s2_entry_0_RNIHKRF[1]\ : MX2 - port map(A => N_1106, B => N_1140, S => \s2_entry_0[1]\, Y - => N_1174); - - \r.s2_entry_4[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_4[2]\); - - \r.s2_data_RNI19ON[22]\ : OR2B - port map(A => \data_0[22]\, B => N_3063, Y => N_3037); - - \r.walk_transdata.data_RNITPQ9[6]\ : MX2 - port map(A => \data[6]\, B => \data_0[6]\, S => walk_use, Y - => un1_m0_2_7); - - \r.s2_entry_0_RNI1LBP[1]\ : MX2 - port map(A => N_1100, B => N_1134, S => \s2_entry_0[1]\, Y - => N_1168); - - \r.walk_use\ : DFN1E1 - port map(D => sync_isw_RNII96B91, CLK => lclk_c, E => - s2_tlbstate_3, Q => walk_use); - - \r.walk_transdata.data_RNILEPD[3]\ : MX2 - port map(A => \data[3]\, B => \data_0[3]\, S => walk_use_1, - Y => un1_m0_2_4); - - \r.walk_transdata.data_RNI99612[18]\ : MX2 - port map(A => \data_1[18]\, B => \data_2[18]\, S => - walk_use, Y => un1_m0_2_19); - - \r.s2_entry_1_RNIK5EP[1]\ : MX2 - port map(A => N_1202, B => N_1236, S => \s2_entry_1[1]\, Y - => N_1270); - - \r.s2_data[2]\ : DFN1E1 - port map(D => un1_m0_2_77, CLK => lclk_c, E => s1finished, - Q => \data[2]\); - - \r.s2_data_RNI9CSM[30]\ : MX2C - port map(A => \cam_addr[30]_net_1\, B => \data[30]\, S => - s2_flush_0, Y => \I1_1[6]\); - - \r.walk_transdata.data_RNO[20]\ : MX2 - port map(A => hrdata_0_16, B => \data_0[20]\, S => - lvl_i_1_0(1), Y => N_700); - - \r.walk_fault.fault_inv_RNO\ : NOR3A - port map(A => inv_1_0_a2_0_a2_0, B => hrdata_0_1, C => - N_2523, Y => N_31); - - \r.walk_transdata.data[4]\ : DFN1E0 - port map(D => \data[4]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[4]\); - - \r.s2_entry_RNICI3Q[0]\ : MX2 - port map(A => N_1181, B => N_1283, S => \s2_entry[0]\, Y - => \adata[13]\); - - \r.s2_entry_1_RNI23N21[0]\ : MX2 - port map(A => N_1183, B => N_1285, S => \s2_entry_1[0]\, Y - => \adata[15]\); - - \r.s2_entry_0_RNI5DGF[1]\ : MX2 - port map(A => N_1112, B => N_1146, S => \s2_entry_0[1]\, Y - => N_1180); - - \r.s2_data[0]\ : DFN1E1 - port map(D => un1_m0_2_75, CLK => lclk_c, E => - \s1finished_0\, Q => \data[0]\); - - \cam_addr[20]\ : MX2 - port map(A => maddress(20), B => data_1_8, S => trans_op_0, - Y => \cam_addr[20]_net_1\); - - \r.walk_transdata.data[18]\ : DFN1E0 - port map(D => N_690, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data_2[18]\); - - \r.sync_isw_RNISM17\ : OR2A - port map(A => fault_mexc, B => sync_isw, Y => - cache_0_sqmuxa_0_a2_0); - - \r.s2_hm_RNIH0KH\ : NOR2A - port map(A => tlbactive, B => N_166, Y => N_2265); - - \r.s2_entry_0_RNIQ23VN2_6[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[4]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_0[4]\); - - \r.s2_data_RNI3P2P4[14]\ : OR2B - port map(A => \data_1_i_i_0[14]\, B => N_2954, Y => - un1_m0_2_15); - - \r.s2_data[20]\ : DFN1E1 - port map(D => data_1_8, CLK => lclk_c, E => s1finished_1, Q - => \data_0[20]\); - - \r.s2_data_RNIG4TM[31]\ : MX2C - port map(A => \cam_addr[31]_net_1\, B => \data[31]\, S => - s2_flush_0, Y => \I1_1[7]\); - - \r.s2_data_RNI7CIU2[19]\ : NOR3 - port map(A => N_3001, B => N_2998, C => N_2999, Y => N_415); - - \r.s2_data_RNI1LUM[19]\ : MX2C - port map(A => \cam_addr[19]_net_1\, B => \data_0[19]\, S - => s2_flush_1, Y => \I2_1[1]\); - - \r.s2_entry_1_RNI0SKL1[0]\ : MX2 - port map(A => N_1195, B => N_1297, S => \s2_entry_1[0]\, Y - => \adata[27]\); - - \r.walk_transdata.data[15]\ : DFN1E0 - port map(D => N_73, CLK => lclk_c, E => cache_0_sqmuxa_0, Q - => \data_1[15]\); - - \r.s2_entry_0_RNISGC31[0]\ : MX2 - port map(A => N_1174, B => N_1276, S => \s2_entry_0[0]\, Y - => adata_6); - - \r.s2_entry_0_RNIHUSSN2_0[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[1]\, Y => - \tlbcam_write_op_1_1_0[1]\); - - \r.s2_data_RNIGG3F5[24]\ : NOR3 - port map(A => N_3010, B => N_3011, C => N_3012, Y => N_421); - - \r.s2_data_RNIQSTM[18]\ : MX2C - port map(A => \cam_addr[18]_net_1\, B => \data[18]\, S => - s2_flush_1, Y => \I2_1[0]\); - - \r.s2_data_RNI9D0T4[12]\ : NOR2 - port map(A => \data_1_i_m2_i_0[12]\, B => N_2905, Y => - N_2886); - - \r.s2_entry_RNITAJA1[0]\ : NOR2A - port map(A => N_3062, B => \adata[17]\, Y => N_3009); - - \p0.transdata.data_1_i_a2[29]\ : NOR2A - port map(A => N_3060, B => \adata[25]\, Y => N_2977); - - \r.walk_fault.fault_pri_RNI73Q9B\ : AO1B - port map(A => un1_m0_2_0(35), B => \fault_pri\, C => - fault_pri_m, Y => \fault_pri_1\); - - \r.sync_isw_RNII96B91\ : OAI1 - port map(A => N_2509, B => cache_0_sqmuxa_0_a2_0, C => - cache_0_sqmuxa_0, Y => sync_isw_RNII96B91); - - \r.s2_entry_RNI27MJ1[0]\ : OR2 - port map(A => \un1_acc[33]\, B => \un1_acc[32]\, Y => N_552); - - \r.walk_transdata.data[26]\ : DFN1E0 - port map(D => N_2739, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data_1[26]\); - - \r.walk_transdata.cache_RNIA6TE1\ : MX2C - port map(A => \adata[7]\, B => cache, S => walk_use_1, Y - => un1_m0_2_33); - - \r.walk_transdata.data[17]\ : DFN1E0 - port map(D => \data_3[17]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[17]\); - - \r.walk_fault.fault_mexc\ : DFN1E0 - port map(D => N_29, CLK => lclk_c, E => N_55, Q => - fault_mexc_1); - - \r.s2_tlbstate_RNIJKCMN2_0[1]\ : NOR2 - port map(A => cache_0_sqmuxa_0, B => \N_86_i\, Y => - dr1write_0_sqmuxa_0); - - \r.s2_entry_RNIVMF9[1]\ : MX2 - port map(A => N_1133, B => N_1167, S => \s2_entry[1]\, Y - => N_1201); - - \r.s2_entry_0_RNISHCM1[0]\ : MX2 - port map(A => N_1168, B => N_1270, S => \s2_entry_0[0]\, Y - => adata_0); - - \r.walk_use_0\ : DFN1E1 - port map(D => sync_isw_RNII96B91, CLK => lclk_c, E => - s2_tlbstate_3, Q => \walk_use_0\); - - \r.walk_transdata.data[5]\ : DFN1E0 - port map(D => \data[5]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[5]\); - - \r.walk_transdata.data_RNO[12]\ : MX2 - port map(A => hrdata_0_8, B => \data[12]\, S => \N_3160\, Y - => N_19); - - \r.walk_transdata.data[6]\ : DFN1E0 - port map(D => \data[6]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[6]\); - - \r.s2_tlbstate_RNIJKCMN2[1]\ : NOR2 - port map(A => cache_0_sqmuxa_0, B => \N_86_i\, Y => - dr1write_0_sqmuxa); - - \r.sync_isw\ : DFN1 - port map(D => sync_isw_RNO_0, CLK => lclk_c, Q => sync_isw); - - \r.s2_tlbstate_RNO_1[0]\ : OR2A - port map(A => \s2_tlbstate_ns_0_0_a2_0_0[0]\, B => \N_86_i\, - Y => N_2539); - - \r.s2_tlbstate[0]\ : DFN1 - port map(D => \s2_tlbstate_nss[0]\, CLK => lclk_c, Q => - \s2_tlbstate[0]\); - - \r.s2_entry_0_RNIT2TP[1]\ : MX2 - port map(A => N_1119, B => N_1153, S => \s2_entry_0[1]\, Y - => N_1187); - - \r.s2_hm\ : DFN1E1 - port map(D => cam_hit_all_1, CLK => lclk_c, E => s1finished, - Q => s2_hm); - - \r.walk_transdata.data_RNI5K3D[12]\ : NOR2A - port map(A => \walk_use_0\, B => \data_1[12]\, Y => N_2904); - - \r.s2_entry_1_RNIFUC31[0]\ : MX2 - port map(A => N_1175, B => N_1277, S => \s2_entry_1[0]\, Y - => \adata[7]\); - - \r.s2_entry_0_RNI9JUP[1]\ : MX2 - port map(A => N_1122, B => N_1156, S => \s2_entry_0[1]\, Y - => N_1190); - - \r.s2_data[1]\ : DFN1E1 - port map(D => un1_m0_2_76, CLK => lclk_c, E => s1finished_1, - Q => \data[1]\); - - \r.walk_transdata.data_RNI904D[15]\ : NOR2A - port map(A => walk_use_1, B => \data_1[15]\, Y => N_805); - - \r.walk_fault.fault_mexc_RNI5NF5\ : NOR2B - port map(A => walk_use, B => fault_mexc_1, Y => - fault_mexc_0); - - \r.walk_transdata.data[8]\ : DFN1E0 - port map(D => \data[8]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[8]\); - - \r.s2_su_RNI6LVI2\ : NOR3C - port map(A => \adata[4]\, B => fault_pri_1_m_1, C => - \adata[3]\, Y => fault_pri_1_m); - - \r.walk_transdata.data_RNO[14]\ : MX2 - port map(A => hrdata_0_10, B => \data[14]\, S => \N_3160\, - Y => N_37); - - \r.s2_entry_RNIML8B[1]\ : MX2 - port map(A => N_1215, B => N_1249, S => \s2_entry[1]\, Y - => N_1283); - - \r.s2_entry_1_RNICTIF[1]\ : MX2 - port map(A => N_1211, B => N_1245, S => \s2_entry_1[1]\, Y - => N_1279); - - \r.walk_fault.fault_pri_RNO\ : NOR3B - port map(A => N_2547, B => \N_2482\, C => \fault_su\, Y => - N_38); - - \r.s2_entry_1_RNIRDJF[1]\ : MX2 - port map(A => N_1214, B => N_1248, S => \s2_entry_1[1]\, Y - => N_1282); - - \r.nrep_RNO[0]\ : NOR2A - port map(A => rst, B => \nrep[0]\, Y => nrep_n0); - - \r.s2_entry_0_RNIPCGF[1]\ : MX2 - port map(A => N_1109, B => N_1143, S => \s2_entry_0[1]\, Y - => N_1177); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.walk_transdata.data_RNIPEPD[5]\ : MX2 - port map(A => \data[5]\, B => \data_0[5]\, S => walk_use_1, - Y => un1_m0_2_6); - - \r.s2_entry_2[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_2[2]\); - - \r.s2_data[10]\ : DFN1E1 - port map(D => un1_m0_2_85, CLK => lclk_c, E => - \s1finished_0\, Q => \data[10]\); - - \r.walk_transdata.data_RNO[30]\ : MX2 - port map(A => \data[30]\, B => hrdata_0_26, S => N_2571, Y - => \data_2[30]\); - - \r.s2_data[29]\ : DFN1E1 - port map(D => data_1_17, CLK => lclk_c, E => s1finished, Q - => \data_0[29]\); - - \r.walk_transdata.data_RNI8O3D[23]\ : NOR2A - port map(A => walk_use_1, B => \data[23]\, Y => N_2940); - - \r.sync_isw_RNO\ : OA1A - port map(A => N_2494, B => sync_isw, C => sync_isw_1_i_0_0, - Y => sync_isw_RNO_0); - - \tlbcam0.2.tag0\ : mmutlbcam_2_0_6 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - hrdata_0_27 => hrdata_0_27, hrdata_0_26 => hrdata_0_26, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_21 => hrdata_0_21, hrdata_0_18 => hrdata_0_18, - hrdata_0_16 => hrdata_0_16, hrdata_0_15 => hrdata_0_15, - hrdata_0_12 => hrdata_0_12, hrdata_0_8 => hrdata_0_8, - hrdata_0_0 => hrdata_0_0, hrdata_0_4 => hrdata_0_4, - hrdata_0_3 => hrdata_0_3, hrdata_0_2 => hrdata_0_2, - data_0_18 => \data[31]\, data_0_11 => \data[24]\, - data_0_10 => \data_0[23]\, data_0_6 => \data_0[19]\, - data_0_4 => \data_1[17]\, data_0_3 => \data_0[16]\, - data_0_1 => \data[14]\, data_0_0 => \data_0[13]\, - tlbcam_write_op_1_1_0(2) => \tlbcam_write_op_1_1_0[2]\, - s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - hrdata_30 => hrdata_31, hrdata_29 => hrdata_30, hrdata_28 - => hrdata_29, hrdata_27 => hrdata_28, hrdata_23 => - hrdata_24, hrdata_16 => hrdata_17, hrdata_13 => hrdata_14, - hrdata_12 => hrdata_13, hrdata_10 => hrdata_11, hrdata_9 - => hrdata_10, hrdata_8 => hrdata_9, hrdata_0_d0 => - hrdata_1, hrdata_6 => hrdata_7, tlbcam_write_op_1(2) => - \tlbcam_write_op_1[2]\, TYP_1_2 => \TYP_1[2]\, TYP_1_0_d0 - => \TYP_1[0]\, s2_entry(2) => \s2_entry[2]\, - LVL_RNIT69H911(0) => \LVL_RNIT69H911[0]\, I1_1_i_0_0(0) - => \I1_1_i_0_0[0]\, data_21 => \data[30]\, data_20 => - \data_0[29]\, data_19 => \data[28]\, data_18 => - \data_0[27]\, data_17 => \data[26]\, data_16 => - \data[25]\, data_13 => \data_0[22]\, data_12 => - \data_0[21]\, data_11 => \data_0[20]\, data_9 => - \data[18]\, data_6 => \data[15]\, data_3 => \data[12]\, - data_7 => data_1_4, data_0_d0 => \data[9]\, data_22 => - data_0_31, data_8 => data_2_0, data_15 => data_1_12, - data_5 => data_0_14, data_4 => data_13, data_14 => - data_1_11, data_10 => data_1_7, un1_m0_2_0 => un1_m0_2_91, - un1_m0_2_15 => un1_m0_2_106, un1_m0_2_1 => un1_m0_2_92, - un1_m0_2_7 => un1_m0_2_98, un1_m0_2_3 => un1_m0_2_94, - I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, LVL_0(1) => \LVL[1]\, - LVL_0(0) => \LVL[0]\, s2_entry_2(2) => \s2_entry_2[2]\, - pteout_4 => \pteout_1[4]\, pteout_3 => \pteout_1[3]\, - pteout_2 => \pteout_1[2]\, s2_entry_1(2) => - \s2_entry_1_0[2]\, pteout_0_4 => \pteout[4]\, pteout_0_17 - => \pteout_0[17]\, pteout_0_20 => \pteout_0[20]\, - pteout_0_3 => \pteout[3]\, pteout_0_31 => \pteout_0[31]\, - pteout_0_30 => \pteout_0[30]\, pteout_0_29 => - \pteout_0[29]\, pteout_0_28 => \pteout_0[28]\, - pteout_0_27 => \pteout_0[27]\, pteout_0_26 => - \pteout_0[26]\, pteout_0_25 => \pteout_0[25]\, - pteout_0_24 => \pteout_0[24]\, pteout_0_23 => - \pteout_0[23]\, pteout_0_22 => \pteout_0[22]\, - pteout_0_21 => \pteout_0[21]\, pteout_0_19 => - \pteout_0[19]\, pteout_0_18 => \pteout_0[18]\, - pteout_0_16 => \pteout_0[16]\, pteout_0_15 => - \pteout_0[15]\, pteout_0_14 => \pteout_0[14]\, - pteout_0_13 => \pteout_0[13]\, pteout_0_12 => - \pteout_0[12]\, pteout_0_11 => \pteout_0[11]\, - pteout_0_10 => \pteout_0[10]\, pteout_0_9 => - \pteout_0[9]\, pteout_0_8 => \pteout_0[8]\, pteout_0_7 - => \pteout_0[7]\, pteout_0_6 => \pteout_0[6]\, - pteout_0_2 => \pteout[2]\, pteout_0_1 => \pteout_0[1]\, - pteout_0_0 => \pteout_0[0]\, I3_1_i(3) => \I3_1_i[3]\, - tlbcam_write_op_1_0(2) => \tlbcam_write_op_1_0[2]\, - cam_hitaddr_18(1) => \cam_hitaddr_18[1]\, - un2_wb_acc_iv_4_3 => \un2_wb_acc_iv_4[12]\, - un2_wb_acc_iv_4_18 => \un2_wb_acc_iv_4[27]\, - un2_wb_acc_iv_4_0 => \un2_wb_acc_iv_4[9]\, - un2_wb_acc_iv_4_1 => \un2_wb_acc_iv_4[10]\, - un2_wb_acc_iv_4_4 => \un2_wb_acc_iv_4[13]\, - un2_wb_acc_iv_4_6 => \un2_wb_acc_iv_4[15]\, - un2_wb_acc_iv_4_10 => \un2_wb_acc_iv_4[19]\, - un2_wb_acc_iv_4_11 => \un2_wb_acc_iv_4[20]\, ctx(7) => - ctx(7), ctx(6) => ctx(6), ctx(5) => ctx(5), ctx(4) => - ctx(4), ctx(3) => ctx(3), ctx(2) => ctx(2), ctx(1) => - ctx(1), ctx(0) => ctx(0), I2_1(5) => \I2_1[5]\, I2_1(4) - => \I2_1[4]\, I2_1(3) => \I2_1[3]\, I2_1(2) => \I2_1[2]\, - I2_1(1) => \I2_1[1]\, I2_1(0) => \I2_1[0]\, I1_1_5 => - \I1_1[6]\, I1_1_2 => \I1_1[3]\, I1_1_0 => \I1_1[1]\, - I1_1_1 => \I1_1[2]\, I1_1_3 => \I1_1[4]\, I1_1_6 => - \I1_1[7]\, I3_1_4 => \I3_1[4]\, I3_1_0 => \I3_1[0]\, - I3_1_5 => \I3_1[5]\, LVL(1) => \LVL_1[1]\, LVL(0) => - \LVL_1[0]\, TYP_1_0(0) => \TYP_1_0[0]\, un2_wb_acc_iv_2_3 - => \un2_wb_acc_iv_2[12]\, un2_wb_acc_iv_2_18 => - \un2_wb_acc_iv_2[27]\, un2_wb_acc_iv_2_0 => - \un2_wb_acc_iv_2[9]\, un2_wb_acc_iv_2_1 => - \un2_wb_acc_iv_2[10]\, un2_wb_acc_iv_2_4 => - \un2_wb_acc_iv_2[13]\, un2_wb_acc_iv_2_6 => - \un2_wb_acc_iv_2[15]\, un2_wb_acc_iv_2_10 => - \un2_wb_acc_iv_2[19]\, un2_wb_acc_iv_2_11 => - \un2_wb_acc_iv_2[20]\, un2_wb_acc_iv_2_8 => - \un2_wb_acc_iv_2[17]\, pteout_m_i_1_2 => - \pteout_m_i_0[18]\, pteout_m_i_1_0 => \pteout_m_i_0[16]\, - un2_wb_acc_iv_5(18) => \un2_wb_acc_iv_5[18]\, - un2_wb_acc_iv_5(17) => \un2_wb_acc_iv_5[17]\, - un2_wb_acc_iv_5(16) => \un2_wb_acc_iv_5[16]\, - un2_wb_acc_iv_3_5 => \un2_wb_acc_iv_3[14]\, pteout_m_i_11 - => \pteout_m_i_0[20]\, pteout_m_i_10 => - \pteout_m_i_0[19]\, pteout_m_i_9 => \pteout_m_i[18]\, - pteout_m_i_8 => \pteout_m_i_0[17]\, pteout_m_i_7 => - \pteout_m_i[16]\, pteout_m_i_6 => \pteout_m_i_0[15]\, - pteout_m_i_4 => \pteout_m_i_0[13]\, pteout_m_i_1_d0 => - \pteout_m_i_0[10]\, pteout_m_i_0_d0 => \pteout_m_i_0[9]\, - pteout_m_i_18 => \pteout_m_i_0[27]\, pteout_m_i_3 => - \pteout_m_i_0[12]\, pteout_m_i_0_1_0 => - \pteout_m_i_0_0[8]\, pteout_m_i_0_1_15 => - \pteout_m_i_0_0[23]\, pteout_m_i_0_0_0 => - \pteout_m_i_0_2[8]\, pteout_m_i_0_0_16 => - \pteout_m_i_0_0[24]\, pteout_m_i_0_0_15 => - \pteout_m_i_0_2[23]\, pteout_m_i_0_0_17 => - \pteout_m_i_0_0[25]\, pteout_m_i_0_0_14 => - \pteout_m_i_0_0[22]\, pteout_m_i_0_0_18 => - \pteout_m_i_0_0[26]\, data_1_3_i_a3_3_3 => - \data_1_3_i_a3_3[28]\, data_1_3_i_a3_3_4 => - \data_1_3_i_a3_3[29]\, data_1_3_i_a3_3_1 => - \data_1_3_i_a3_3[26]\, data_1_3_i_a3_3_5 => - \data_1_3_i_a3_3[30]\, un1_cam_hitaddr(61) => - \un1_cam_hitaddr[61]\, data_1_3_i_a3_2(25) => - \data_1_3_i_a3_2[25]\, data_1_3_i_a3_5_2 => - \data_1_3_i_a3_5[27]\, data_1_3_i_a3_5_0 => - \data_1_3_i_a3_5[25]\, pteout_m_i_0_10 => - \pteout_m_i_2[18]\, pteout_m_i_0_8 => \pteout_m_i_2[16]\, - pteout_m_i_0_6 => \pteout_m_i_0[14]\, pteout_m_i_0_0_d0 - => \pteout_m_i_0[8]\, pteout_m_i_0_15 => - \pteout_m_i_0[23]\, pteout_m_i_0_13 => - \pteout_m_i_0_0[21]\, pteout_m_i_0_3 => - \pteout_m_i_0_0[11]\, data_1_3_i_a3_0_2(15) => - \data_1_3_i_a3_0_2[15]\, data_1_3_i_a3_0_5_0 => - \data_1_3_i_a3_0_5[12]\, data_1_3_i_a3_0_5_3 => - \data_1_3_i_a3_0_5[15]\, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, - N_1138 => N_1138, cam_hit_all_5_sqmuxa_2 => - cam_hit_all_5_sqmuxa_2, N_1151 => N_1151, N_1154 => - N_1154, s2_flush => s2_flush, N_1137 => N_1137, NEEDSYNC - => NEEDSYNC_0, N_1167 => N_1167, un1_rst_i_0 => - \un1_rst_i_0\, N_696 => N_696, N_695 => N_695, N_2709_i_0 - => \N_2709_i_0\, N_694 => N_694, trans_op => trans_op, - N_2483 => N_2483, M_1 => M_1, N_661 => N_661, N_3046 => - N_3046, N_1513 => N_1513, N_3043 => N_3043, N_61 => N_61, - N_1166 => N_1166, N_1165 => N_1165, N_1164 => N_1164, - N_1163 => N_1163, N_1162 => N_1162, N_1161 => N_1161, - N_1160 => N_1160, N_1159 => N_1159, N_1158 => N_1158, - N_1157 => N_1157, N_1156 => N_1156, N_1155 => N_1155, - N_1153 => N_1153, N_1152 => N_1152, N_1150 => N_1150, - N_1149 => N_1149, N_1148 => N_1148, N_1147 => N_1147, - N_1146 => N_1146, N_1145 => N_1145, N_1144 => N_1144, - N_1143 => N_1143, N_1142 => N_1142, N_1141 => N_1141, - N_1140 => N_1140, N_1136 => N_1136, N_1135 => N_1135, - N_1134 => N_1134, s2_flush_0 => s2_flush_0, hit_1 => - hit_2, hit_0 => hit_0, hit => hit_1, WBNEEDSYNC_m => - WBNEEDSYNC_m, accexc_6_3 => accexc_6_3); - - \r.walk_transdata.data_RNIA759[14]\ : OR2B - port map(A => walk_use, B => \data_1[14]\, Y => N_2955); - - \r.walk_fault.fault_mexc_RNO\ : NOR2A - port map(A => fault_mexc, B => N_2523, Y => N_29); - - \r.s2_entry_RNICNLJ[0]\ : MX2 - port map(A => N_1185, B => N_1287, S => \s2_entry[0]\, Y - => \adata[17]\); - - \r.s2_entry_1[1]\ : DFN1E0 - port map(D => \s2_entry_1_0[1]\, CLK => lclk_c, E => N_53, - Q => \s2_entry_1[1]\); - - \cam_addr[16]\ : MX2 - port map(A => maddress(16), B => data_1_4, S => trans_op_0, - Y => \cam_addr[16]_net_1\); - - \r.walk_transdata.data_RNI4HSU3[26]\ : AO1A - port map(A => \adata[22]\, B => N_3060, C => N_2931, Y => - \data_1_i_m2_i_0[26]\); - - \r.s2_entry_1_RNIBADL1[0]\ : MX2 - port map(A => N_1197, B => N_1299, S => \s2_entry_1[0]\, Y - => adata_29); - - \r.s2_data_RNI048C3[28]\ : MX2 - port map(A => \adata[24]\, B => \data[28]\, S => N_550, Y - => \data_1[28]\); - - \r.s2_entry_1_RNIE3VP[1]\ : MX2 - port map(A => N_1130, B => N_1164, S => \s2_entry_1[1]\, Y - => N_1198); - - \r.walk_transdata.data_RNO[17]\ : MX2 - port map(A => hrdata_0_13, B => \data_1[17]\, S => \N_3160\, - Y => \data_3[17]\); - - \r.walk_transdata.data[22]\ : DFN1E0 - port map(D => N_692, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[22]\); - - \r.s2_entry_1_RNI0FLN1[0]\ : MX2 - port map(A => N_1191, B => N_1293, S => \s2_entry_1[0]\, Y - => \adata[23]\); - - \r.walk_use_1_RNI5E4Q1_0\ : NOR2 - port map(A => walk_use_1, B => N_550, Y => N_3060); - - \r.walk_transdata.data_RNI5C3D[30]\ : OR2B - port map(A => \walk_use_0\, B => \data_1[30]\, Y => N_2923); - - \r.s2_tlbstate_RNO_0[0]\ : OA1A - port map(A => N_166, B => N_2547, C => N_2538, Y => - \s2_tlbstate_ns_0_0_0[0]\); - - \r.s2_entry_1_RNIUJ1Q[1]\ : MX2 - port map(A => N_1223, B => N_1257, S => \s2_entry_1[1]\, Y - => N_1291); - - \r.s2_entry_RNI3I39[1]\ : MX2 - port map(A => N_1219, B => N_1253, S => \s2_entry[1]\, Y - => N_1287); - - \r.nrep_RNO[1]\ : NOR3A - port map(A => rst, B => N_2525, C => nrep_n1_0_i_0, Y => - N_2511); - - \r.walk_transdata.data[16]\ : DFN1E0 - port map(D => N_2736, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data[16]\); - - \r.s2_entry_RNI7V88[1]\ : MX2 - port map(A => N_1205, B => N_1239, S => \s2_entry[1]\, Y - => N_1273); - - \r.s2_entry_1_RNI22N21[0]\ : MX2 - port map(A => N_1179, B => N_1281, S => \s2_entry_1[0]\, Y - => \adata[11]\); - - \r.s2_flush_RNIMSF51\ : OR2 - port map(A => s2_flush, B => read, Y => M_1); - - \r.walk_fault.fault_pri_RNICI913\ : AO1 - port map(A => \walk_use_0\, B => fault_pri_0, C => - fault_pri_1_m, Y => \fault_pri\); - - \r.s2_read_RNIUUU6D\ : NOR2A - port map(A => \fault_read\, B => hrdata_6, Y => N_2483); - - \r.s2_tlbstate_RNIUL5E[0]\ : NOR2B - port map(A => \s2_tlbstate[0]\, B => tlbactive, Y => N_2530); - - \r.walk_transdata.data_RNICQSS3[31]\ : AO1A - port map(A => \adata[27]\, B => N_3060, C => N_2962, Y => - \data_1_i_0[31]\); - - \r.s2_entry_RNINIT2[2]\ : NOR2B - port map(A => \s2_entry[2]\, B => \s2_entry[1]\, Y => - \tlbcam_write_op_1_1[7]\); - - \r.walk_transdata.data[3]\ : DFN1E0 - port map(D => \data[3]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[3]\); - - \r.s2_tlbstate_RNIBJJC[1]\ : NOR2A - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => N_2522); - - \r.s2_entry_1_RNIQ2N21[0]\ : MX2 - port map(A => N_1182, B => N_1284, S => \s2_entry_1[0]\, Y - => \adata[14]\); - - \cam_addr[19]\ : MX2 - port map(A => maddress(19), B => data_1_7, S => trans_op_0, - Y => \cam_addr[19]_net_1\); - - \r.s2_entry_1_RNIEK3Q[1]\ : MX2 - port map(A => N_1227, B => N_1261, S => \s2_entry_1[1]\, Y - => N_1295); - - \r.s2_data_RNI9SSM[21]\ : MX2C - port map(A => \cam_addr[21]_net_1\, B => \data_0[21]\, S - => s2_flush_1, Y => \I2_1[3]\); - - \r.s2_data[9]\ : DFN1E1 - port map(D => un1_m0_2_84, CLK => lclk_c, E => s1finished, - Q => \data[9]\); - - \r.s2_tlbstate_RNIVL5E[1]\ : OR2A - port map(A => tlbactive, B => \s2_tlbstate[1]\, Y => N_89); - - \r.walk_transdata.data_RNIVPQ9[7]\ : MX2 - port map(A => \data[7]\, B => \data_0[7]\, S => walk_use, Y - => un1_m0_2_8); - - \cam_addr[26]\ : MX2 - port map(A => maddress(26), B => data_0_26, S => trans_op_0, - Y => \cam_addr[26]_net_1\); - - \r.walk_transdata.data_RNI7G3D[31]\ : NOR2A - port map(A => walk_use_1, B => \data_1[31]\, Y => N_2962); - - \r.s2_data_RNIEE9J3[22]\ : OR3C - port map(A => N_3038, B => N_3036, C => N_3037, Y => - un1_m0_2_23); - - \r.s2_entry_RNIM58V[0]\ : MX2 - port map(A => N_1200, B => N_1302, S => \s2_entry[0]\, Y - => \un1_acc[32]\); - - \r.s2_entry_0_RNIQ23VN2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[2]\, Y => - \tlbcam_write_op_1_1[3]\); - - \r.s2_entry_1_RNIJMKP1[0]\ : NOR2A - port map(A => N_3062, B => \adata[15]\, Y => N_3001); - - \r.s2_data_RNI1CSM[12]\ : MX2C - port map(A => \cam_addr[12]_net_1\, B => \data[12]\, S => - s2_flush_0, Y => \I3_1[0]\); - - \cam_addr_i_m4[29]\ : MX2 - port map(A => maddress(29), B => data_1_17, S => trans_op, - Y => N_701); - - \r.s2_tlbstate_RNO_3[0]\ : NOR3B - port map(A => \s2_tlbstate[0]\, B => N_95, C => - \s2_tlbstate[1]\, Y => \s2_tlbstate_ns_0_0_a2_0_0[0]\); - - \r.s2_entry_0_RNIQ23VN2_4[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[4]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_1_0[4]\); - - \r.s2_flush_1_RNINUQK\ : OR2 - port map(A => N_3073, B => data_0_14, Y => N_3043); - - \r.s2_entry_1_RNIU2UF[1]\ : MX2 - port map(A => N_1132, B => N_1166, S => \s2_entry_1[1]\, Y - => N_1200); - - \r.s2_entry_1_RNIU6LP1[0]\ : NOR2A - port map(A => N_3062, B => \adata[16]\, Y => N_3005); - - \r.s2_entry_0[1]\ : DFN1E0 - port map(D => \s2_entry_1_0[1]\, CLK => lclk_c, E => N_53, - Q => \s2_entry_0[1]\); - - \r.s2_data_RNI9PQR[17]\ : MX2C - port map(A => \cam_addr[17]_net_1\, B => \data_1[17]\, S - => s2_flush_1, Y => \I3_1[5]\); - - \r.s2_entry_0_RNIS31Q[1]\ : MX2 - port map(A => N_1126, B => N_1160, S => \s2_entry_0[1]\, Y - => N_1194); - - \r.walk_transdata.data_RNO[23]\ : MX2 - port map(A => N_264_0, B => \data_0[23]\, S => lvl_i_1_0(1), - Y => N_693); - - \r.sync_isw_RNISUDSK\ : NOR3A - port map(A => rst, B => \N_2532\, C => \N_2550\, Y => - twowner_2_0_a2_0_0(0)); - - \r.s2_entry_0[0]\ : DFN1E0 - port map(D => \s2_entry_1_0[0]\, CLK => lclk_c, E => N_53, - Q => \s2_entry_0[0]\); - - \r.walk_transdata.data_RNI1QQ9[8]\ : MX2 - port map(A => \data[8]\, B => \data_0[8]\, S => walk_use, Y - => un1_m0_2_9); - - \r.s2_data[19]\ : DFN1E1 - port map(D => data_1_7, CLK => lclk_c, E => s1finished_1, Q - => \data_0[19]\); - - \r.walk_transdata.data[29]\ : DFN1E0 - port map(D => N_2747, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[29]\); - - \r.s2_entry_3[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_3[2]\); - - \r.s2_needsync_RNO_1\ : AOI1B - port map(A => un1_tlbcami_3, B => tlbcamo_needsync, C => - NEEDSYNC, Y => s2_needsync_4); - - \r.s2_entry_1_RNIJDJF[1]\ : MX2 - port map(A => N_1212, B => N_1246, S => \s2_entry_1[1]\, Y - => N_1280); - - \r.walk_transdata.data_RNO[21]\ : MX2 - port map(A => hrdata_0_17, B => \data_0[21]\, S => - lvl_i_1_0(1), Y => N_691); - - \r.walk_transdata.data[12]\ : DFN1E0 - port map(D => N_19, CLK => lclk_c, E => cache_0_sqmuxa_0, Q - => \data_1[12]\); - - \r.s2_entry_1_RNILUJN1[0]\ : MX2 - port map(A => N_1190, B => N_1292, S => \s2_entry_1[0]\, Y - => \adata[22]\); - - \r.walk_transdata.data_RNO[26]\ : MX2 - port map(A => \data[26]\, B => hrdata_0_22, S => N_2571, Y - => N_2739); - - \r.walk_fault.fault_mexc_RNO_0\ : OR3A - port map(A => \N_2532\, B => N_2531, C => \N_2550\, Y => - N_55); - - \r.s2_entry_1_RNI3ACL1[0]\ : MX2 - port map(A => N_1196, B => N_1298, S => \s2_entry_1[0]\, Y - => adata_28); - - \r.s2_data[4]\ : DFN1E1 - port map(D => un1_m0_2_79, CLK => lclk_c, E => s1finished, - Q => \data[4]\); - - \p0.transdata.data_1_i_m2_i_a2[27]\ : NOR2A - port map(A => N_3060, B => \adata[23]\, Y => N_2957); - - \r.walk_transdata.data_RNIJEPD[2]\ : MX2 - port map(A => \data[2]\, B => \data_0[2]\, S => walk_use_1, - Y => un1_m0_2_3); - - \r.s2_data[21]\ : DFN1E1 - port map(D => data_1_9, CLK => lclk_c, E => s1finished_1, Q - => \data_0[21]\); - - \r.sync_isw_RNO_0\ : OR3A - port map(A => N_95, B => \N_86_i\, C => N_2509, Y => N_2494); - - \r.s2_data[24]\ : DFN1E1 - port map(D => data_1_12, CLK => lclk_c, E => s1finished_1, - Q => \data[24]\); - - \r.s2_entry_RNITUUSN2_1[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[4]\, C => \s2_entry[0]\, Y => - \tlbcam_write_op_1[4]\); - - \r.s2_ctx[3]\ : DFN1E1 - port map(D => ctx(3), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[3]\); - - \r.s2_tlbstate_RNIBJJC_0[1]\ : NOR2 - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => N_2523); - - \r.s2_entry_0_RNIQ23VN2_3[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[2]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_1_0[2]\); - - \r.s2_entry_0_RNIHUSSN2_1[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[1]\, Y => - \tlbcam_write_op_1_0[1]\); - - \r.nrep_RNIH84SF9[0]\ : MX2B - port map(A => \nrep[0]\, B => \cam_hitaddr_21[0]\, S => - \s1finished_0\, Y => \s2_entry_1_0[0]\); - - \r.s2_entry_0_RNIPQLE[1]\ : MX2 - port map(A => N_1102, B => N_1136, S => \s2_entry_0[1]\, Y - => N_1170); - - \r.s2_data_RNI523H[14]\ : OA1A - port map(A => s2_flush_0, B => \data[14]\, C => N_3044, Y - => \I3_1_i_0_0[2]\); - - \tlbcam0.3.tag0\ : mmutlbcam_2_0_7 - port map(hrdata_0_27 => hrdata_0_27, hrdata_0_26 => - hrdata_0_26, hrdata_0_23 => hrdata_0_23, hrdata_0_22 => - hrdata_0_22, hrdata_0_21 => hrdata_0_21, hrdata_0_18 => - hrdata_0_18, hrdata_0_16 => hrdata_0_16, hrdata_0_15 => - hrdata_0_15, hrdata_0_12 => hrdata_0_12, hrdata_0_8 => - hrdata_0_8, hrdata_0_0 => hrdata_0_0, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1(3) => \tlbcam_write_op_1_1[3]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_30 => - hrdata_31, hrdata_29 => hrdata_30, hrdata_28 => hrdata_29, - hrdata_27 => hrdata_28, hrdata_23 => hrdata_24, hrdata_16 - => hrdata_17, hrdata_13 => hrdata_14, hrdata_12 => - hrdata_13, hrdata_10 => hrdata_11, hrdata_9 => hrdata_10, - hrdata_8 => hrdata_9, hrdata_0_d0 => hrdata_1, hrdata_3 - => hrdata_4, hrdata_2 => hrdata_3, hrdata_1 => hrdata_2, - hrdata_6 => hrdata_7, tlbcam_write_op_1(3) => - \tlbcam_write_op_1[3]\, LVL_1(1) => \LVL_4[1]\, TYP_1(2) - => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, TYP_1(0) => - \TYP_1[0]\, s2_entry(2) => \s2_entry[2]\, I1_1_i_0_0(0) - => \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, - LVL_0(1) => \LVL_3[1]\, LVL_0(0) => \LVL_2[0]\, - s2_entry_4(2) => \s2_entry_4[2]\, pteout_4 => - \pteout_4[4]\, pteout_3 => \pteout_4[3]\, pteout_2 => - \pteout_4[2]\, s2_entry_3(2) => \s2_entry_3[2]\, - pteout_0_4 => \pteout_2[4]\, pteout_0_17 => - \pteout_1[17]\, pteout_0_3 => \pteout_2[3]\, pteout_0_13 - => \pteout_1[13]\, pteout_0_31 => \pteout_1[31]\, - pteout_0_30 => \pteout_1[30]\, pteout_0_29 => - \pteout_1[29]\, pteout_0_28 => \pteout_1[28]\, - pteout_0_27 => \pteout_1[27]\, pteout_0_26 => - \pteout_1[26]\, pteout_0_25 => \pteout_1[25]\, - pteout_0_24 => \pteout_1[24]\, pteout_0_23 => - \pteout_1[23]\, pteout_0_22 => \pteout_1[22]\, - pteout_0_21 => \pteout_1[21]\, pteout_0_20 => - \pteout_1[20]\, pteout_0_19 => \pteout_1[19]\, - pteout_0_18 => \pteout_1[18]\, pteout_0_16 => - \pteout_1[16]\, pteout_0_15 => \pteout_1[15]\, - pteout_0_14 => \pteout_1[14]\, pteout_0_12 => - \pteout_1[12]\, pteout_0_11 => \pteout_1[11]\, - pteout_0_10 => \pteout_1[10]\, pteout_0_9 => - \pteout_1[9]\, pteout_0_8 => \pteout_1[8]\, pteout_0_7 - => \pteout_1[7]\, pteout_0_6 => \pteout_1[6]\, - pteout_0_2 => \pteout_2[2]\, pteout_0_1 => \pteout_1[1]\, - pteout_0_0 => \pteout_1[0]\, I3_1_i(3) => \I3_1_i[3]\, - tlbcam_write_op_1_0(3) => \tlbcam_write_op_1_0[3]\, - LVL_0_d0 => \LVL_4[0]\, ctx_7 => ctx(7), ctx_6 => ctx(6), - ctx_5 => ctx(5), ctx_3 => ctx(3), ctx_1 => ctx(1), - ctx_0_d0 => ctx(0), ctx_2 => ctx(2), ctx_0(4) => ctx_0(4), - I2_1(5) => \I2_1[5]\, I2_1(4) => \I2_1[4]\, I2_1(3) => - \I2_1[3]\, I2_1(2) => \I2_1[2]\, I2_1(1) => \I2_1[1]\, - I2_1(0) => \I2_1[0]\, I1_1_6 => \I1_1[7]\, I1_1_3 => - \I1_1[4]\, I1_1_2 => \I1_1[3]\, I1_1_0 => \I1_1[1]\, - I1_1_1 => \I1_1[2]\, I1_1_5 => \I1_1[6]\, I3_1_4 => - \I3_1[4]\, I3_1_0 => \I3_1[0]\, I3_1_5 => \I3_1[5]\, - TYP_1_0(0) => \TYP_1_0[0]\, pteout_m_i_11 => - \pteout_m_i_2[20]\, pteout_m_i_10 => \pteout_m_i_2[19]\, - pteout_m_i_9 => \pteout_m_i_3[18]\, pteout_m_i_7 => - \pteout_m_i_3[16]\, pteout_m_i_6 => \pteout_m_i_2[15]\, - pteout_m_i_4 => \pteout_m_i_2[13]\, pteout_m_i_3 => - \pteout_m_i_2[12]\, pteout_m_i_1 => \pteout_m_i_2[10]\, - pteout_m_i_0_d0 => \pteout_m_i_2[9]\, pteout_m_i_8 => - \pteout_m_i_2[17]\, pteout_m_i_5 => \pteout_m_i_2[14]\, - un2_wb_acc_iv_1_3 => \un2_wb_acc_iv_1[17]\, - un2_wb_acc_iv_1_0 => \un2_wb_acc_iv_1[14]\, - un2_wb_acc_iv_0(27) => \un2_wb_acc_iv_0[27]\, - un2_wb_acc_iv_4(27) => \un2_wb_acc_iv_4[27]\, - pteout_m_i_0_18 => \pteout_m_i_0_2[26]\, pteout_m_i_0_17 - => \pteout_m_i_0_2[25]\, pteout_m_i_0_15 => - \pteout_m_i_0_3[23]\, pteout_m_i_0_0_d0 => - \pteout_m_i_0_3[8]\, pteout_m_i_0_19 => - \pteout_m_i_2[27]\, pteout_m_i_0_16 => - \pteout_m_i_0_2[24]\, pteout_m_i_0_14 => - \pteout_m_i_0_2[22]\, pteout_m_i_0_13 => - \pteout_m_i_0_2[21]\, data_1_3_i_a3_1_3 => - \data_1_3_i_a3_1[28]\, data_1_3_i_a3_1_1 => - \data_1_3_i_a3_1[26]\, data_1_3_i_a3_1_0 => - \data_1_3_i_a3_1[25]\, pteout_m_i_0_0_0 => - \pteout_m_i_0_2[11]\, data_1_3_i_a3_0_1(15) => - \data_1_3_i_a3_0_1[15]\, un1_cam_hitaddr(60) => - \un1_cam_hitaddr[60]\, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, - cam_hit_all_5_sqmuxa_2 => cam_hit_all_5_sqmuxa_2, N_2551 - => N_2551, N_1498 => N_1498, N_1506 => N_1506, N_1240 - => N_1240, N_1253 => N_1253, trans_op => trans_op, - s2_flush => s2_flush, hit => hit_2, N_1239 => N_1239, - N_1269 => N_1269, N_1249 => N_1249, un1_rst_i_0 => - \un1_rst_i_0\, un1_tlbcami_3 => un1_tlbcami_3_1, N_2483 - => N_2483, M_1 => M_1, N_3046 => N_3046, N_3043 => - N_3043, N_61 => N_61, N_1268 => N_1268, N_1267 => N_1267, - N_1266 => N_1266, N_1265 => N_1265, N_1264 => N_1264, - N_1263 => N_1263, N_1262 => N_1262, N_1261 => N_1261, - N_1260 => N_1260, N_1259 => N_1259, N_1258 => N_1258, - N_1257 => N_1257, N_1256 => N_1256, N_1255 => N_1255, - N_1254 => N_1254, N_1252 => N_1252, N_1251 => N_1251, - N_1250 => N_1250, N_1248 => N_1248, N_1247 => N_1247, - N_1246 => N_1246, N_1245 => N_1245, N_1244 => N_1244, - N_1243 => N_1243, N_1242 => N_1242, N_1238 => N_1238, - N_1237 => N_1237, N_1236 => N_1236, s2_flush_0 => - s2_flush_0, N_661 => N_661, tlbcamo_needsync => - tlbcamo_needsync_1, WBNEEDSYNC_m => WBNEEDSYNC_m_1, - accexc_6_2 => accexc_6_2); - - \r.s2_read\ : DFN1E1 - port map(D => read, CLK => lclk_c, E => s1finished, Q => - \fault_read\); - - \r.s2_entry_1_RNIMJ0Q[1]\ : MX2 - port map(A => N_1221, B => N_1255, S => \s2_entry_1[1]\, Y - => N_1289); - - \r.walk_transdata.data_RNI3QQ9[9]\ : MX2 - port map(A => \data[9]\, B => \data_0[9]\, S => walk_use, Y - => un1_m0_2_10); - - \r.s2_flush_1_RNIE098\ : OR2A - port map(A => trans_op_0, B => s2_flush_1, Y => N_3073); - - \r.s2_flush_RNI7T2E1\ : OR2 - port map(A => N_2552, B => N_2530, Y => N_53); - - \r.s2_entry_1_RNITTGN1[0]\ : MX2 - port map(A => N_1187, B => N_1289, S => \s2_entry_1[0]\, Y - => \adata[19]\); - - \r.s2_entry_0[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_0[2]\); - - \r.s2_data_RNIM5VP5[30]\ : OR3C - port map(A => N_2922, B => N_2923, C => N_2924, Y => - un1_m0_2_31); - - \cam_addr[23]\ : MX2 - port map(A => maddress(23), B => data_1_11, S => trans_op, - Y => \cam_addr[23]_net_1\); - - \r.s2_hm_RNI84O9\ : OR3A - port map(A => s2_hm, B => tlbdis, C => s2_needsync_1, Y => - N_166); - - \r.s2_data_RNIPKTM[26]\ : MX2C - port map(A => \cam_addr[26]_net_1\, B => \data[26]\, S => - s2_flush_0, Y => \I1_1[2]\); - - \r.s2_entry_RNIM6AJ1[0]\ : MX2 - port map(A => N_1198, B => N_1300, S => \s2_entry[0]\, Y - => adata_30); - - \r.s2_ctx[7]\ : DFN1E1 - port map(D => ctx(7), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[7]\); - - \r.s2_ctx[2]\ : DFN1E1 - port map(D => ctx(2), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[2]\); - - \r.nrep_RNO[2]\ : XA1 - port map(A => N_2513, B => \nrep[2]\, C => rst, Y => N_2512); - - \r.s2_entry_1_RNIS3UF[1]\ : MX2 - port map(A => N_1209, B => N_1243, S => \s2_entry_1[1]\, Y - => N_1277); - - \r.sync_isw_RNI7DR9_0\ : NOR2A - port map(A => \s2_tlbstate[1]\, B => sync_isw, Y => - areq_ur_1_0_a2_0_0); - - \r.s2_entry_RNIQFSN[1]\ : MX2 - port map(A => N_1222, B => N_1256, S => \s2_entry[1]\, Y - => N_1290); - - \r.s2_entry_0_RNI1DGF[1]\ : MX2 - port map(A => N_1111, B => N_1145, S => \s2_entry_0[1]\, Y - => N_1179); - - \tlbcam0.6.tag0\ : mmutlbcam_2_0_1 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1(6) => \tlbcam_write_op_1_1[6]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0 => hrdata_0_d0, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_7 => hrdata_7, - tlbcam_write_op_1(6) => \tlbcam_write_op_1[6]\, TYP_1(2) - => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, TYP_1(0) => - \TYP_1[0]\, tlbcam_write_op_1_0(6) => - \tlbcam_write_op_1_0[6]\, I1_1_i_0_0(0) => - \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, - pteout_m_i_8 => \pteout_m_i_0[17]\, pteout_m_i_18 => - \pteout_m_i_0[27]\, pteout_m_i_11 => \pteout_m_i_0[20]\, - pteout_m_i_10 => \pteout_m_i_0[19]\, pteout_m_i_9 => - \pteout_m_i_0[18]\, pteout_m_i_7 => \pteout_m_i_0[16]\, - pteout_m_i_6 => \pteout_m_i_0[15]\, pteout_m_i_5 => - \pteout_m_i_0[14]\, pteout_m_i_4 => \pteout_m_i_0[13]\, - pteout_m_i_3 => \pteout_m_i_0[12]\, pteout_m_i_1 => - \pteout_m_i_0[10]\, pteout_m_i_0_d0 => \pteout_m_i_0[9]\, - pteout_31 => \pteout_0[31]\, pteout_30 => \pteout_0[30]\, - pteout_29 => \pteout_0[29]\, pteout_28 => \pteout_0[28]\, - pteout_1 => \pteout_0[1]\, pteout_0 => \pteout_0[0]\, - pteout_4 => \pteout[4]\, pteout_3 => \pteout[3]\, - pteout_2 => \pteout[2]\, pteout_7 => \pteout_0[7]\, - pteout_17 => \pteout_0[17]\, pteout_27 => \pteout_0[27]\, - pteout_6 => \pteout_0[6]\, pteout_26 => \pteout_0[26]\, - pteout_25 => \pteout_0[25]\, pteout_24 => \pteout_0[24]\, - pteout_23 => \pteout_0[23]\, pteout_22 => \pteout_0[22]\, - pteout_21 => \pteout_0[21]\, pteout_20 => \pteout_0[20]\, - pteout_19 => \pteout_0[19]\, pteout_18 => \pteout_0[18]\, - pteout_16 => \pteout_0[16]\, pteout_15 => \pteout_0[15]\, - pteout_14 => \pteout_0[14]\, pteout_13 => \pteout_0[13]\, - pteout_12 => \pteout_0[12]\, pteout_11 => \pteout_0[11]\, - pteout_10 => \pteout_0[10]\, pteout_9 => \pteout_0[9]\, - pteout_8 => \pteout_0[8]\, pteout_m_i_0_18 => - \pteout_m_i_0_0[26]\, pteout_m_i_0_17 => - \pteout_m_i_0_0[25]\, pteout_m_i_0_16 => - \pteout_m_i_0_0[24]\, pteout_m_i_0_15 => - \pteout_m_i_0_0[23]\, pteout_m_i_0_14 => - \pteout_m_i_0_0[22]\, pteout_m_i_0_13 => - \pteout_m_i_0_0[21]\, pteout_m_i_0_3 => - \pteout_m_i_0_0[11]\, pteout_m_i_0_0 => - \pteout_m_i_0_0[8]\, ctx(4) => ctx(4), I3_1_i(3) => - \I3_1_i[3]\, un1_cam_hitaddr(57) => \un1_cam_hitaddr[57]\, - ctx_0_7 => ctx_0(7), ctx_0_5 => ctx_0(5), ctx_0_3 => - ctx_0(3), ctx_0_1 => ctx_0(1), ctx_0_0 => ctx_0(0), - ctx_0_2 => ctx_0(2), ctx_0_6 => ctx_0(6), I2_1(5) => - \I2_1[5]\, I2_1(4) => \I2_1[4]\, I2_1(3) => \I2_1[3]\, - I2_1(2) => \I2_1[2]\, I2_1(1) => \I2_1[1]\, I2_1(0) => - \I2_1[0]\, I1_1_5 => \I1_1[6]\, I1_1_2 => \I1_1[3]\, - I1_1_0 => \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_3 => - \I1_1[4]\, I1_1_6 => \I1_1[7]\, I3_1_4 => \I3_1[4]\, - I3_1_0 => \I3_1[0]\, I3_1_5 => \I3_1[5]\, LVL(1) => - \LVL[1]\, LVL(0) => \LVL[0]\, TYP_1_0(0) => \TYP_1_0[0]\, - N_78 => N_78, N_262 => N_262, N_264 => N_264, N_2482 => - \N_2482\, lclk_c => lclk_c, trans_op => trans_op, hit => - hit_1, s2_flush => s2_flush, un1_rst_i_0 => \un1_rst_i_0\, - un1_tlbcami_3 => un1_tlbcami_3_0, N_2483 => N_2483, M_1 - => M_1, N_661 => N_661, N_3046 => N_3046, N_3043 => - N_3043, N_61 => N_61, WBNEEDSYNC_m => WBNEEDSYNC_m_0, - tlbcamo_needsync => tlbcamo_needsync_0); - - \r.s2_entry_0_RNIHUSSN2_5[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[7]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_0[6]\); - - \r.s2_data_RNIF1I7[10]\ : OR2B - port map(A => \data[10]\, B => s2_flush_1, Y => \TYP_1[2]\); - - \r.s2_entry_1_RNIFHM21[0]\ : MX2 - port map(A => N_1177, B => N_1279, S => \s2_entry_1[0]\, Y - => \adata[9]\); - - \r.s2_data_RNI24SM[20]\ : MX2C - port map(A => \cam_addr[20]_net_1\, B => \data_0[20]\, S - => s2_flush_1, Y => \I2_1[2]\); - - \r.nrep_RNO_0[1]\ : NOR2B - port map(A => \nrep[2]\, B => N_2513, Y => N_2525); - - \cam_addr[21]\ : MX2 - port map(A => maddress(21), B => data_1_9, S => trans_op_0, - Y => \cam_addr[21]_net_1\); - - \r.s2_entry_RNINIT2_0[2]\ : NOR2 - port map(A => \s2_entry[2]\, B => \s2_entry[1]\, Y => - \tlbcam_write_op_1_1[1]\); - - \r.walk_fault.fault_pri\ : DFN1E1 - port map(D => N_38, CLK => lclk_c, E => N_25, Q => - fault_pri_0); - - \r.s2_flush_0\ : DFN1E1 - port map(D => s2_flush_1_0, CLK => lclk_c, E => un1_rst_3, - Q => s2_flush_0); - - \r.walk_transdata.data[19]\ : DFN1E0 - port map(D => N_699, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data[19]\); - - \r.walk_fault.fault_pro_RNIFJ8T2\ : NOR2A - port map(A => fault_pro_m, B => fault_pro_1_m_0_4, Y => - \fault_pro_1_iv_1\); - - \r.walk_transdata.data_RNO[22]\ : MX2 - port map(A => hrdata_0_18, B => \data_0[22]\, S => - lvl_i_1_0(1), Y => N_692); - - \r.s2_data[8]\ : DFN1E1 - port map(D => un1_m0_2_83, CLK => lclk_c, E => s1finished, - Q => \data[8]\); - - \cam_addr[15]\ : MX2 - port map(A => maddress(15), B => data_0_15, S => trans_op_0, - Y => \cam_addr[15]_net_1\); - - \r.s2_tlbstate_RNIS2MHL[1]\ : OR2B - port map(A => cache_0_sqmuxa_0, B => N_2547, Y => N_2276); - - \r.s2_entry_RNI3V88[1]\ : MX2 - port map(A => N_1103, B => N_1137, S => \s2_entry[1]\, Y - => N_1171); - - \r.s2_data_RNI2R442[15]\ : AO1D - port map(A => \data[15]\, B => N_3066, C => N_805, Y => - \data_1_i_0[15]\); - - \r.walk_fault.fault_lvl[1]\ : DFN1E0 - port map(D => N_82_0, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => fault_lvl(1)); - - \r.walk_transdata.data[2]\ : DFN1E0 - port map(D => \data[2]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[2]\); - - \r.s2_data[11]\ : DFN1E1 - port map(D => un1_m0_2_86, CLK => lclk_c, E => s1finished_1, - Q => \data[11]\); - - \r.s2_entry_0_RNIHUSSN2_4[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[1]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_1[0]\); - - \r.walk_transdata.data_RNINEPD[4]\ : MX2 - port map(A => \data[4]\, B => \data_0[4]\, S => walk_use_1, - Y => un1_m0_2_5); - - \r.s2_flush_1_RNIMKG9\ : OR3 - port map(A => trans_op_0, B => s2_flush_1, C => - maddress(24), Y => N_3047); - - \r.s2_data_RNI05ON[21]\ : NOR2A - port map(A => N_3063, B => \data_0[21]\, Y => N_3007); - - \r.s2_data[14]\ : DFN1E1 - port map(D => data_0_14, CLK => lclk_c, E => s1finished_1, - Q => \data[14]\); - - \r.s2_entry_RNIU6BJ1[0]\ : MX2 - port map(A => N_1199, B => N_1301, S => \s2_entry[0]\, Y - => adata_31); - - \r.s2_entry_1_RNI45UF[1]\ : MX2 - port map(A => N_1208, B => N_1242, S => \s2_entry_1[1]\, Y - => N_1276); - - \r.walk_transdata.data_RNO[31]\ : MX2 - port map(A => \data[31]\, B => hrdata_0_27, S => N_2571, Y - => \data_2[31]\); - - \r.walk_transdata.data_RNO[15]\ : MX2 - port map(A => hrdata_0_11, B => \data[15]\, S => \N_3160\, - Y => N_73); - - \cam_addr[18]\ : MX2 - port map(A => maddress(18), B => data_0_18, S => trans_op_0, - Y => \cam_addr[18]_net_1\); - - \r.s2_entry_RNI0N35[1]\ : NOR2A - port map(A => \s2_entry[1]\, B => \s2_entry_4[2]\, Y => - \tlbcam_write_op_1_1[2]\); - - \r.s2_entry_0_RNIHUSSN2_2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_0[7]\); - - \r.walk_transdata.data_RNO[24]\ : MX2 - port map(A => \data[24]\, B => N_262_0, S => N_2571, Y => - N_2737); - - \r.s2_data[30]\ : DFN1E1 - port map(D => data_0_30, CLK => lclk_c, E => s1finished, Q - => \data[30]\); - - \r.s2_flush_0_RNI8ELU\ : OA1B - port map(A => N_166, B => s2_flush_0, C => N_89, Y => N_93); - - \r.walk_transdata.data_RNI33542[16]\ : AO1A - port map(A => \data[16]\, B => \walk_use_0\, C => N_2912, Y - => \data_1_i_m2_i_0[16]\); - - \r.s2_entry_RNISH0I[0]\ : MX2 - port map(A => N_1172, B => N_1274, S => \s2_entry[0]\, Y - => \adata[4]\); - - \r.s2_entry_1_RNI6HDE2[0]\ : OR2B - port map(A => \adata[18]\, B => N_3062, Y => N_3038); - - \r.nrep_RNIR6H[1]\ : NOR2B - port map(A => \nrep[1]\, B => \nrep[0]\, Y => N_2513); - - \r.s2_entry_0_RNI3JTP[1]\ : MX2 - port map(A => N_1128, B => N_1162, S => \s2_entry_0[1]\, Y - => N_1196); - - \p0.fault.fault_pro_1_iv\ : NOR2B - port map(A => \fault_pro_1_iv_2\, B => \fault_pro_1_iv_1\, - Y => fault_pro_i); - - \r.s2_data_RNITA442[13]\ : AO1D - port map(A => \data_0[13]\, B => N_3066, C => N_2909, Y => - \data_1_i_m2_i_0[13]\); - - \p0.un9_twneedsync_i_a2_i_o2_i_a4_0\ : OA1C - port map(A => inv_1_0_a2_0_a2_0, B => hrdata_0_1, C => - fault_mexc, Y => un9_twneedsync_i_a2_i_o2_i_a4_0); - - \r.walk_transdata.data_RNILCV9[11]\ : MX2 - port map(A => \data[11]\, B => \data_0[11]\, S => walk_use, - Y => un1_m0_2_12); - - \r.s2_data_RNITOPR[22]\ : MX2C - port map(A => \cam_addr[22]_net_1\, B => \data_0[22]\, S - => s2_flush_1, Y => \I2_1[4]\); - - \r.s2_data_RNI2KGU2[20]\ : NOR3 - port map(A => N_3005, B => N_3002, C => N_3003, Y => N_417); - - \r.walk_transdata.data_RNIFMQN2[17]\ : MX2 - port map(A => \data[17]\, B => \data_0[17]\, S => walk_use, - Y => un1_m0_2_18); - - \r.s2_entry[1]\ : DFN1E0 - port map(D => \s2_entry_1_0[1]\, CLK => lclk_c, E => N_53, - Q => \s2_entry[1]\); - - \r.s2_tlbstate_RNIGCTEK[0]\ : OR2B - port map(A => \s2_tlbstate[0]\, B => N_82, Y => \N_2532\); - - \r.s2_data[23]\ : DFN1E1 - port map(D => data_1_11, CLK => lclk_c, E => s1finished_1, - Q => \data_0[23]\); - - \r.s2_tlbstate_RNIGCTEK_0[0]\ : OR2A - port map(A => \s2_tlbstate[0]\, B => N_82, Y => N_2509); - - \r.nrep[1]\ : DFN1E1 - port map(D => N_2511, CLK => lclk_c, E => nrepe, Q => - \nrep[1]\); - - \r.s2_entry_RNI7V88_0[1]\ : MX2 - port map(A => N_1104, B => N_1138, S => \s2_entry[1]\, Y - => N_1172); - - \r.s2_entry_0_RNI9JRF[1]\ : MX2 - port map(A => N_1107, B => N_1141, S => \s2_entry_0[1]\, Y - => N_1175); - - \r.walk_transdata.data_RNIB2223[14]\ : AOI1B - port map(A => \adata[10]\, B => N_3065, C => N_2955, Y => - \data_1_i_i_0[14]\); - - \r.walk_transdata.data_RNO[27]\ : MX2 - port map(A => \data_0[27]\, B => hrdata_0_23, S => N_2571, - Y => N_2740); - - \r.s2_data[27]\ : DFN1E1 - port map(D => data_1_15, CLK => lclk_c, E => s1finished, Q - => \data_0[27]\); - - \r.walk_transdata.data[9]\ : DFN1E0 - port map(D => \data[9]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[9]\); - - \r.s2_entry_RNITUUSN2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry[0]\, C => - \tlbcam_write_op_1_1[2]\, Y => \tlbcam_write_op_1[3]\); - - \r.s2_entry_0_RNIPISP[1]\ : MX2 - port map(A => N_1118, B => N_1152, S => \s2_entry_0[1]\, Y - => N_1186); - - \cam_addr[25]\ : MX2 - port map(A => maddress(25), B => data_0_25, S => trans_op_0, - Y => \cam_addr[25]_net_1\); - - \r.walk_transdata.data[30]\ : DFN1E0 - port map(D => \data_2[30]\, CLK => lclk_c, E => - cache_0_sqmuxa, Q => \data_1[30]\); - - \r.walk_use_RNIHJTM\ : NOR2A - port map(A => \un1_acc[33]\, B => walk_use, Y => N_3063); - - \r.s2_data_RNI963H[24]\ : OA1A - port map(A => s2_flush_0, B => \data[24]\, C => N_3047, Y - => \I1_1_i_0_0[0]\); - - \r.s2_data_RNI1PCT1[29]\ : OA1C - port map(A => N_3059, B => \data_0[29]\, C => - \data_1_i_0[29]\, Y => N_353); - - \r.walk_transdata.data_RNIA44D[26]\ : NOR2A - port map(A => \walk_use_0\, B => \data_1[26]\, Y => N_2931); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_2 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_17 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_6 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(0 to 0); - tlbcam_write_op_1_1_0 : in std_logic_vector(0 to 0); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - s2_entry_5 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_1 : in std_logic_vector(2 to 2); - s2_entry_0 : in std_logic_vector(2 to 2); - pteout_0_17 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_4 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(0 to 0); - data_14 : in std_logic; - data_13 : in std_logic; - data_12 : in std_logic; - data_11 : in std_logic; - data_10 : in std_logic; - data_9 : in std_logic; - data_8 : in std_logic; - data_7 : in std_logic; - data_6 : in std_logic; - data_5 : in std_logic; - data_4 : in std_logic; - data_3 : in std_logic; - data_22 : in std_logic; - data_21 : in std_logic; - data_20 : in std_logic; - data_19 : in std_logic; - data_18 : in std_logic; - data_17 : in std_logic; - data_16 : in std_logic; - data_15 : in std_logic; - data_0 : in std_logic; - ctx_0 : in std_logic_vector(7 downto 0); - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_749 : out std_logic; - N_743 : out std_logic; - N_765 : out std_logic; - s2_flush : in std_logic; - N_764 : out std_logic; - N_596 : in std_logic; - un1_rst_i_0 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_763 : out std_logic; - N_762 : out std_logic; - N_761 : out std_logic; - N_760 : out std_logic; - N_759 : out std_logic; - N_758 : out std_logic; - N_757 : out std_logic; - N_756 : out std_logic; - N_755 : out std_logic; - N_754 : out std_logic; - N_753 : out std_logic; - N_752 : out std_logic; - N_751 : out std_logic; - N_750 : out std_logic; - N_748 : out std_logic; - N_747 : out std_logic; - N_746 : out std_logic; - N_745 : out std_logic; - N_744 : out std_logic; - N_742 : out std_logic; - N_741 : out std_logic; - N_740 : out std_logic; - N_739 : out std_logic; - N_738 : out std_logic; - N_736 : out std_logic; - N_735 : out std_logic; - N_734 : out std_logic; - N_733 : out std_logic; - N_732 : out std_logic; - N_634 : in std_logic; - N_632 : in std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - SU_RNIAA5O8 : out std_logic; - hit_0_a3_0 : out std_logic; - s2_flush_0 : in std_logic; - N_169_1 : out std_logic; - N_200 : in std_logic; - N_32_i : out std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - hit_0_a3_2_0 : out std_logic; - N_17_i_0 : out std_logic; - N_204 : in std_logic; - N_170_1 : out std_logic; - N_170 : out std_logic; - N_200_0 : in std_logic; - N_42 : out std_logic - ); - -end mmutlbcam_0_0_2; - -architecture DEF_ARCH of mmutlbcam_0_0_2 is - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_165, N_41, N_40, N_16, N_163, N_39, hit_0_a3_3_0, - hit_0_a3_0_0, h_i32_NE, hit_0_a3_7_0, \un1_tag0[43]\, - \LVL[0]\, N_159, M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNISE6H[5]\, \un1_tag0[64]\, \I2_RNIL5UF[3]\, - \un1_tag0[62]\, \I2_RNIVPUF[1]\, hit_0_a3_5_0, SU, - \LVL[1]\, h_i13_NE_5, h_i13_NE_2, h_i13_NE_3, h_i13_NE_4, - h_i13_NE_0, h_i13_NE_1, \un1_tag0[74]\, \I1_RNIQ9UF[7]\, - \un1_tag0[72]\, \I1_RNI5N6H[5]\, \un1_tag0[70]\, - \I1_RNIUDUF[3]\, \un1_tag0[68]\, \I1_RNIOTTF[1]\, - h_i32_NE_2, \un1_tag0[60]\, \I3_RNI3B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNIS1VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNIMHUF[1]\, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, N_43, N_160, h_i13_NE_i_0, N_162, N_44, - \N_17_i_0\, \N_169_1\, \hit_0_a3_0\, N_15, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[57]\, \un1_tag0[59]\, - \pteout[0]\, \pteout[1]\, \pteout[2]\, \pteout[3]\, - \pteout[4]\, \pteout[6]\, \pteout[7]\, \pteout[8]\, - \pteout[9]\, \pteout[10]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[15]\, \pteout[16]\, \pteout[18]\, - \pteout[19]\, \pteout[20]\, \pteout[21]\, \pteout[22]\, - \pteout[23]\, \pteout[24]\, \pteout[25]\, \pteout[26]\, - \pteout[27]\, \pteout[28]\, \pteout[29]\, \pteout[30]\, - \pteout[31]\, \un1_tag0[73]\, \un1_tag0[75]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, - VALID_RNO_1, N_38, \un1_tag0[61]\, \N_170_1\, - \pteout[11]\, \N_42\, \pteout[17]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - hit_0_a3_0 <= \hit_0_a3_0\; - N_169_1 <= \N_169_1\; - N_17_i_0 <= \N_17_i_0\; - N_170_1 <= \N_170_1\; - N_42 <= \N_42\; - - \r.btag.LVL_RNIL7784[0]\ : OA1C - port map(A => h_i32_NE, B => \LVL[0]\, C => N_159, Y => - hit_0_a3_2_0); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[8]\); - - \r.btag.PPN_RNI745B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_1(2), Y => N_750); - - \r.btag.LVL_RNI7CI44[0]\ : NOR2 - port map(A => \LVL[0]\, B => h_i13_NE_i_0, Y => N_162); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \LVL[1]\); - - \r.btag.CTX_RNI6S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.I2_RNIKS411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNISE6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data_10, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[63]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[19]\); - - \r.btag.I3_RNILRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNIS1VF[3]\, Y => h_i32_NE_1); - - \r.btag.CTX_RNIES44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0(4), Y => h_c2_4_i); - - \r.btag.I2_RNIN4623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.ET_RNIADSA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_0(2), Y => N_733); - - \r.btag.PPN_RNINDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_749); - - \r.btag.PPN_RNIHC6B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_1(2), Y => N_755); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data_14, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(0), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[41]\); - - \r.btag.C_RNIC446\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_0(2), Y => N_739); - - \r.btag.I1_RNIQ9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIQ9UF[7]\); - - \r.btag.CTX_RNIKS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.PPN_RNIH1V5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_1(2), Y => N_746); - - \r.btag.SU_RNIAA5O8\ : AO1 - port map(A => N_44, B => N_43, C => \hit_0_a3_0\, Y => - SU_RNIAA5O8); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data_9, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[36]\); - - \r.btag.I1_RNIVH934[0]\ : NOR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => - h_i13_NE_i_0); - - \r.btag.PPN_RNILS6B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_1(2), Y => N_757); - - \r.btag.CTX_RNI8S44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[10]\); - - \r.btag.PPN_RNIL1V5[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_1(2), Y => N_748); - - \tlbcamo.hit_0_a3_3_RNO\ : NOR2B - port map(A => N_204, B => \N_17_i_0\, Y => hit_0_a3_3_0); - - \r.btag.ACC_RNI88H5[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry_0(2), Y => N_736); - - \r.btag.I3_RNIMHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIMHUF[1]\); - - \tlbcamo.hit_0_a3_8\ : NOR2 - port map(A => N_200_0, B => N_16, Y => N_40); - - \r.btag.SU_RNIH3KE1\ : AO1C - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data_4, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[57]\); - - \r.btag.I3_RNI3B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI3B7H[5]\); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.I3_RNI15923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.LVL_RNISEGA5[1]\ : OR3A - port map(A => \LVL[1]\, B => N_159, C => N_162, Y => N_32_i); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[28]\); - - \r.btag.CTX_RNIGS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_0_10, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data_5, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_1); - - \r.btag.LVL_RNIH476[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_5(2), - Y => N_764); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data_13, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[66]\); - - \r.btag.ACC_RNI48H5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_0(2), Y => N_734); - - \tlbcamo.hit_0_a3_0_RNO\ : NOR2A - port map(A => \un1_tag0[43]\, B => \N_170_1\, Y => - hit_0_a3_0_0); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data_15, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[68]\); - - \r.btag.PPN_RNIJK6B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_1(2), Y => N_756); - - \r.btag.PPN_RNIN47B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_1(2), Y => N_758); - - \r.btag.PPN_RNIBC5B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_1(2), Y => N_761); - - \tlbcamo.hit_0_a3_3\ : NAND2 - port map(A => N_163, B => hit_0_a3_3_0, Y => N_41); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[29]\); - - \r.btag.I1_RNI67OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN_RNIDS5B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_1(2), Y => N_753); - - \r.btag.PPN_RNI91V5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_1(2), Y => N_742); - - \r.btag.PPN_RNIDK5B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_1(2), Y => N_762); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data_11, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[64]\); - - \r.btag.I2_RNIS4511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNIVPUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_1, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[4]\); - - \r.btag.PPN_RNIF46B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_1(2), Y => N_754); - - \r.btag.PPN_RNI51V5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_1(2), Y => N_740); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78_0, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[25]\); - - \r.btag.VALID_RNI3JL26\ : OR3C - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE_i_0, - Y => N_43); - - \r.btag.CTX_RNI4IJG[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIBK5B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_1(2), Y => N_752); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[3]\); - - \tlbcamo.hit_0_a3_0\ : NAND2 - port map(A => N_165, B => hit_0_a3_0_0, Y => N_170); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data_7, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[60]\); - - \r.btag.I1_RNIPJSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNIUDUF[3]\, Y => h_i13_NE_1); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data_22, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[75]\); - - \r.btag.ACC_RNI68H5[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry_0(2), Y => N_735); - - \r.btag.I3_RNIS1VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNIS1VF[3]\); - - \r.btag.PPN_RNIBDQ3[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry(2), Y => N_743); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[1]\); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[11]\); - - \r.btag.LVL_RNI5GM6[1]\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.I2_RNIVPUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNIVPUF[1]\); - - \r.btag.PPN_RNIFS5B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_1(2), Y => N_763); - - \r.btag.I3_RNI3EE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI3B7H[5]\, Y => h_i32_NE_2); - - \r.btag.PPN_RNIJ1V5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_1(2), Y => N_747); - - \tlbcamo.hit_0_a3_4\ : OR2A - port map(A => N_200, B => N_204, Y => \N_42\); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data_12, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[65]\); - - \r.btag.VALID_RNIJTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[27]\); - - \r.btag.M_RNI0546\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_0(2), Y => N_738); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data_3, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[56]\); - - \r.btag.PPN_RNIPC7B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_1(2), Y => N_759); - - \r.btag.I1_RNI5N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI5N6H[5]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data_18, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNI9C5B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_1(2), Y => N_751); - - \r.btag.PPN_RNID1V5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_1(2), Y => N_744); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[9]\); - - \tlbcamo.hit_0_a3_7_RNO\ : OR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data_17, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_0_17, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[24]\); - - \r.btag.I1_RNIDJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIOTTF[1]\, Y => h_i13_NE_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data_16, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[37]\); - - \r.btag.I1_RNI76D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNI5N6H[5]\, Y => h_i13_NE_2); - - \tlbcamo.hit_0_a3_0_1\ : OR2A - port map(A => s2_flush, B => data_0, Y => \N_170_1\); - - \r.btag.CTX_RNICS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.PPN_RNI71V5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_1(2), Y => N_741); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[15]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_0_7, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[7]\); - - \r.btag.I2_RNIMMF57[0]\ : NOR2B - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE_i_0, Y => - \N_17_i_0\); - - \r.btag.PPN_RNI945B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_1(2), Y => N_760); - - \r.btag.I2_RNI73SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIL5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.PPN_RNIF1V5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_1(2), Y => N_745); - - \r.btag.ET_RNI85SA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_0(2), Y => N_732); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \LVL[0]\); - - \tlbcamo.hit_0_a3_1_0\ : NOR3C - port map(A => s2_flush_0, B => data_0, C => N_204, Y => - \N_169_1\); - - \r.btag.LVL_RNIDJT71[1]\ : AOI1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => N_38, Y => - N_16); - - \r.btag.LVL_RNI7G04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_765); - - \r.btag.I3_RNI9RSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNIMHUF[1]\, Y => h_i32_NE_0); - - \r.btag.I1_RNIPAH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \tlbcamo.hit_0_o3_0\ : NAND2 - port map(A => N_41, B => \N_42\, Y => N_165); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_0_6, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[30]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[12]\); - - \r.btag.I1_RNIUDUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNIUDUF[3]\); - - \r.btag.I1_RNII4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIQ9UF[7]\, Y => h_i13_NE_3); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[16]\); - - \r.btag.I1_RNIOTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIOTTF[1]\); - - \r.btag.VALID_RNIC8L41\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => N_159); - - \tlbcamo.hit_0_o3_4\ : OR2 - port map(A => N_39, B => N_40, Y => N_163); - - \r.btag.SU_RNIOFKO1\ : OR3 - port map(A => N_200, B => SU, C => N_159, Y => N_44); - - \r.btag.CTX_RNI6P98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data_19, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[72]\); - - \tlbcamo.hit_0_a3_0_0\ : OR2B - port map(A => \N_169_1\, B => s2_flush_0, Y => \hit_0_a3_0\); - - \r.btag.CTX_RNI4HJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.I2_RNISE6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNISE6H[5]\); - - \r.btag.I2_RNIL5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIL5UF[3]\); - - \tlbcamo.hit_0_a3_7\ : NOR2 - port map(A => h_i32_NE, B => hit_0_a3_7_0, Y => N_39); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data_20, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[18]\); - - \r.btag.CTX_RNIMO98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_4 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0 : in std_logic_vector(7 to 7); - tlbcam_write_op_1 : in std_logic_vector(5 to 5); - tlbcam_write_op_1_1_0 : in std_logic_vector(5 to 5); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(5 to 5); - ctx_0 : in std_logic_vector(7 downto 0); - LVL : out std_logic_vector(1 downto 0); - s2_entry_1_i_a2_1 : out std_logic_vector(0 to 0); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_2937_1 : in std_logic; - cam_hit_all_1_sqmuxa : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_42 : in std_logic; - N_635 : in std_logic; - N_639 : in std_logic; - N_632 : in std_logic; - N_634 : in std_logic; - N_594 : in std_logic; - N_596 : in std_logic; - N_620 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - hit_0_a3_0 : in std_logic; - N_200 : in std_logic; - N_170_1 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_204 : in std_logic; - hit : in std_logic - ); - -end mmutlbcam_0_0_4; - -architecture DEF_ARCH of mmutlbcam_0_0_4 is - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hit_0, hit_0_1, N_33, N_32_i, N_169_i, hit_0_a3_3_0, - N_17_i_0, M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNI1F6H[5]\, \un1_tag0[64]\, \I2_RNIQ5UF[3]\, - \un1_tag0[62]\, \I2_RNI4QUF[1]\, hit_0_a3_5_0, - \un1_tag0[43]\, hit_0_a3_7_0, SU, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI8B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNI12VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNIRHUF[1]\, h_i13_NE_5, h_i13_NE_2, - h_i13_NE_3, h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, - \un1_tag0[74]\, \I1_RNIV9UF[7]\, \un1_tag0[72]\, - \I1_RNIAN6H[5]\, \un1_tag0[70]\, \I1_RNI3EUF[3]\, - \un1_tag0[68]\, \I1_RNITTTF[1]\, h_c2_NE_5, h_c2_NE_2, - h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[39]\, h_c2_5_i, - \un1_tag0[37]\, h_c2_3_i, N_43, N_160, h_i13_NE_i_0, - h_c2_NE, h_i32_NE, N_161, N_159, N_170_i, N_165, N_44, - \LVL[1]\, N_162, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[40]\, \un1_tag0[42]\, - \un1_tag0[73]\, \un1_tag0[75]\, \un1_tag0[63]\, - \un1_tag0[67]\, N_38, N_16, \LVL[0]\, \un1_tag0[61]\, - \un1_tag0[65]\, \un1_tag0[59]\, \un1_tag0[57]\, - \un1_tag0[71]\, \un1_tag0[69]\, N_163, N_40, VALID_RNO_3, - N_15, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - - \r.btag.SU_RNI5F5O8\ : AO1 - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => - N_169_i); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_30); - - \r.btag.I2_RNILJ9E7[0]\ : NOR2B - port map(A => N_204, B => N_17_i_0, Y => hit_0_a3_3_0); - - \r.btag.I1_RNIQ7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.VALID_RNITCGSE2\ : NOR2 - port map(A => hit, B => hit_0, Y => s2_entry_1_i_a2_1(0)); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_12); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_20); - - \r.btag.I2_RNISOF57[0]\ : NOR2B - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE_i_0, Y => - N_17_i_0); - - \r.btag.I1_RNIV9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIV9UF[7]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[73]\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[69]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[38]\); - - \r.btag.I3_RNI12VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNI12VF[3]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.VALID_RNI3IP871\ : OR2B - port map(A => hit_0_1, B => N_170_i, Y => hit_0); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[57]\); - - \r.btag.VALID_RNI2ECOD\ : OR3B - port map(A => \un1_tag0[43]\, B => N_165, C => N_170_1, Y - => N_170_i); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_28); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_6); - - \r.btag.CTX_RNIOHJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_17); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_24); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_8); - - \r.btag.I1_RNITTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNITTTF[1]\); - - \r.btag.I1_RNIS4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIV9UF[7]\, Y => h_i13_NE_3); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[42]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_13); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[40]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_18); - - \r.btag.I1_RNIAN6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNIAN6H[5]\); - - \r.btag.CTX_RNI0P98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.SU_RNIAHKO1\ : OR3 - port map(A => N_200, B => SU, C => N_159, Y => N_44); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[59]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[35]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_16); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[41]\); - - \r.btag.I1_RNIDBH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_0); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_7); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_23); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[68]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_14); - - \r.btag.CTX_RNIDS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_31); - - \r.btag.LVL_RNIKDI44[0]\ : NOR2 - port map(A => \LVL[0]\, B => h_i13_NE_i_0, Y => N_162); - - \r.btag.I3_RNIV5923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[74]\); - - \r.btag.CTX_RNIBS44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_22); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[72]\); - - \r.btag.CTX_RNIOIJG[4]\ : NOR2B - port map(A => h_c2_NE_2, B => h_c2_NE_3, Y => h_c2_NE_5); - - \r.btag.CTX_RNIGP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.VALID_RNIP9L41\ : OR2A - port map(A => \un1_tag0[43]\, B => h_c2_NE, Y => N_159); - - \r.btag.LVL_RNIVKT71[1]\ : NOR2A - port map(A => h_c2_NE, B => N_38, Y => N_16); - - \r.btag.I2_RNI1F6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNI1F6H[5]\); - - \r.btag.CTX_RNIPS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.I1_RNIH6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNIAN6H[5]\, Y => h_i13_NE_2); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_27); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_21); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[66]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[75]\); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_15); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[60]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[65]\); - - \r.btag.I1_RNI7J934[0]\ : NOR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => - h_i13_NE_i_0); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_29); - - \r.btag.LVL_RNI8NC6D[1]\ : AO1B - port map(A => hit_0_a3_3_0, B => N_163, C => N_42, Y => - N_165); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \LVL[1]\); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[67]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_10); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[56]\); - - \r.btag.I2_RNIUS411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNI1F6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[63]\); - - \r.btag.I1_RNI3KSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI3EUF[3]\, Y => h_i13_NE_1); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_3, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.I2_RNI65511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI4QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_19); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_9); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_25); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[58]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_1); - - \r.btag.LVL_RNI14DGP[1]\ : NOR3C - port map(A => N_33, B => N_32_i, C => N_169_i, Y => hit_0_1); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[61]\); - - \r.btag.I3_RNIJRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNIRHUF[1]\, Y => h_i32_NE_0); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[64]\); - - \r.btag.I1_RNINJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNITTTF[1]\, Y => h_i13_NE_0); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[37]\); - - \r.btag.SU_RNID5KE1\ : AO1C - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.LVL_RNIC0I33[0]\ : OR2A - port map(A => h_i32_NE, B => \LVL[0]\, Y => N_161); - - \r.btag.I3_RNIDEE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI8B7H[5]\, Y => h_i32_NE_2); - - \r.btag.I2_RNIQ5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIQ5UF[3]\); - - \r.btag.I2_RNIL5623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.CTX_RNIG4711[0]\ : OR2B - port map(A => h_c2_NE_5, B => h_c2_NE_4, Y => h_c2_NE); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[62]\); - - \r.btag.I3_RNIRHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIRHUF[1]\); - - \r.btag.LVL_RNI13NDB[0]\ : OR3B - port map(A => N_161, B => N_17_i_0, C => N_159, Y => N_33); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \LVL[0]\); - - \r.btag.CTX_RNIHS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.VALID_RNIU75PL3\ : NOR2 - port map(A => hit_0, B => N_2937_1, Y => - cam_hit_all_1_sqmuxa); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(5), Y => N_15); - - \r.btag.VALID_RNICML26\ : OR3C - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE_i_0, - Y => N_43); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_3); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[39]\); - - \r.btag.I2_RNI4QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI4QUF[1]\); - - \r.btag.CTX_RNI8P98[4]\ : XA1A - port map(A => ctx_0(4), B => \un1_tag0[39]\, C => h_c2_5_i, - Y => h_c2_NE_2); - - \r.btag.LVL_RNISAV7[1]\ : OR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.I2_RNIH3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIQ5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[71]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[36]\); - - \r.btag.LVL_RNIFGM6[1]\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.VALID_RNIOTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_26); - - \r.btag.I3_RNIVRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNI12VF[3]\, Y => h_i32_NE_1); - - \r.btag.LVL_RNIF6FM1[1]\ : OR2 - port map(A => N_16, B => N_200, Y => N_40); - - \r.btag.I1_RNI3EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI3EUF[3]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_3); - - \r.btag.LVL_RNIRHGA5[1]\ : OR3A - port map(A => \LVL[1]\, B => N_159, C => N_162, Y => N_32_i); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_2); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[70]\); - - \r.btag.CTX_RNILS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => SU); - - \r.btag.I3_RNI8B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI8B7H[5]\); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_11); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.LVL_RNIANN05[1]\ : OAI1 - port map(A => h_i32_NE, B => hit_0_a3_7_0, C => N_40, Y => - N_163); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1_0 : in std_logic_vector(1 to 1); - lvl_i_1 : in std_logic_vector(0 to 0); - hrdata_0_17 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_6 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(4 to 4); - tlbcam_write_op_1_1 : in std_logic_vector(4 to 4); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(4 to 4); - cam_hitaddr_12 : out std_logic_vector(2 to 2); - ctx_0 : in std_logic_vector(7 downto 0); - LVL : out std_logic_vector(1 downto 0); - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_634 : in std_logic; - N_594 : in std_logic; - N_596 : in std_logic; - N_169_1 : in std_logic; - un1_rst_i_0 : in std_logic; - s2_flush : in std_logic; - cam_hit_all_1_sqmuxa : in std_logic; - N_635 : in std_logic; - N_639 : in std_logic; - N_665 : in std_logic; - N_597 : in std_logic; - N_620 : in std_logic; - N_593 : in std_logic; - N_632 : in std_logic; - N_204 : in std_logic; - N_200 : in std_logic; - N_42 : in std_logic; - hit_i : out std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_170_1 : in std_logic - ); - -end mmutlbcam_0_0; - -architecture DEF_ARCH of mmutlbcam_0_0 is - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hit_0_0, N_233, N_234, hit_0_a3_0_0, \un1_tag0[43]\, - hit_0_a3_2_0, h_i32_NE, N_11, hit_0_a3_1_0, - M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNI0F6H[5]\, \un1_tag0[64]\, \I2_RNIP5UF[3]\, - \un1_tag0[62]\, \I2_RNI3QUF[1]\, hit_0_a3_5_0, - hit_0_a3_7_0, SU, \LVL[0]\, \LVL[1]\, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI7B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNI02VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNIQHUF[1]\, h_i13_NE_5, h_i13_NE_2, - h_i13_NE_3, h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, - \un1_tag0[74]\, \I1_RNIU9UF[7]\, \un1_tag0[72]\, - \I1_RNI9N6H[5]\, \un1_tag0[70]\, \I1_RNI2EUF[3]\, - \un1_tag0[68]\, \I1_RNISTTF[1]\, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, h_i13_NE, N_10, N_231, N_232, N_36, N_12, - N_34_i, N_37, N_15, N_32, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[57]\, \un1_tag0[63]\, - \un1_tag0[67]\, N_239, \un1_tag0[75]\, \un1_tag0[73]\, - \un1_tag0[71]\, \un1_tag0[69]\, \hit_i\, N_99, VALID_RNO, - N_9, \un1_tag0[61]\, \un1_tag0[65]\, \un1_tag0[59]\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - hit_i <= \hit_i\; - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_30); - - \r.btag.I1_RNI9BH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.I1_RNI1KSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI2EUF[3]\, Y => h_i13_NE_1); - - \r.btag.I2_RNIEOF57[0]\ : OR2A - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE, Y => N_10); - - \r.btag.LVL_RNIBQ1271[0]\ : NOR3 - port map(A => hit_0_0, B => N_231, C => N_232, Y => \hit_i\); - - \r.btag.I1_RNIQ4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIU9UF[7]\, Y => h_i13_NE_3); - - \r.btag.LVL_RNINMN05[1]\ : OA1C - port map(A => N_9, B => N_200, C => N_32, Y => N_15); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_12); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262_0, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_20); - - \r.btag.VALID_RNINTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.I2_RNIF5623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.I1_RNISTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNISTTF[1]\); - - \r.btag.I2_RNI0F6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNI0F6H[5]\); - - \r.btag.I1_RNILJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNISTTF[1]\, Y => h_i13_NE_0); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[73]\); - - \r.btag.I2_RNIP5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIP5UF[3]\); - - \r.btag.I1_RNIM7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[69]\); - - \r.btag.CTX_RNIOS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.I3_RNI02VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNI02VF[3]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[38]\); - - \r.btag.SU_RNI0QDH8\ : OA1 - port map(A => N_36, B => N_37, C => N_169_1, Y => N_231); - - \r.btag.I3_RNIHRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNIQHUF[1]\, Y => h_i32_NE_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[57]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_28); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_6); - - \r.btag.LVL_RNI32NDB[0]\ : NOR2 - port map(A => hit_0_a3_2_0, B => N_10, Y => N_234); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_0_10, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_17); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_0_17, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_24); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_8); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[42]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_0_6, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_13); - - \r.btag.I1_RNI2EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI2EUF[3]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[40]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_18); - - \r.btag.LVL_RNILKT71[1]\ : AO1B - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => N_239, Y => - N_9); - - \r.btag.I2_RNI45511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI3QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[59]\); - - \r.btag.CTX_RNIEP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[35]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_16); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[41]\); - - \r.btag.VALID_RNINLL26\ : NOR3B - port map(A => N_12, B => hit_0_a3_5_0, C => h_i13_NE, Y => - N_36); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_0); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_7); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_23); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[68]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_0_7, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_14); - - \r.btag.CTX_RNIIS44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0(4), Y => h_c2_4_i); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_31); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[74]\); - - \r.btag.CTX_RNIUO98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_22); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[72]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_27); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_21); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[66]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[75]\); - - \r.btag.I2_RNIF3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIP5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_15); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[60]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[65]\); - - \r.btag.I3_RNI7B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI7B7H[5]\); - - \r.btag.CTX_RNIAS44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.SU_RNI15KE1\ : AO1A - port map(A => \LVL[0]\, B => SU, C => N_9, Y => N_12); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_29); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1_0(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \LVL[1]\); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[67]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_10); - - \r.btag.LVL_RNI927RS4[0]\ : OR2B - port map(A => \hit_i\, B => cam_hit_all_1_sqmuxa, Y => - cam_hitaddr_12(2)); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[56]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[63]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO, CLK => lclk_c, Q => \un1_tag0[43]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264_0, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_19); - - \r.btag.LVL_RNIT3U51[1]\ : NOR2A - port map(A => \LVL[1]\, B => N_11, Y => hit_0_a3_1_0); - - \r.btag.LVL_RNI8HGA5[0]\ : OA1A - port map(A => h_i13_NE, B => \LVL[0]\, C => hit_0_a3_1_0, Y - => N_233); - - \r.btag.I1_RNI9N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI9N6H[5]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_9); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78_0, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_25); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[58]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_1); - - \r.btag.VALID_RNIG9L41\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => N_11); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[61]\); - - \r.btag.LVL_RNIDGM6[1]\ : OR2A - port map(A => SU, B => \LVL[1]\, Y => N_239); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[64]\); - - \r.btag.CTX_RNIKHJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[37]\); - - \r.btag.I3_RNITRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNI02VF[3]\, Y => h_i32_NE_1); - - \r.btag.LVL_RNIIG8A3[1]\ : NOR2A - port map(A => hit_0_a3_7_0, B => h_i32_NE, Y => N_32); - - \r.btag.LVL_RNIBJ7OG[0]\ : OR2 - port map(A => N_233, B => N_234, Y => hit_0_0); - - \r.btag.I3_RNIBEE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI7B7H[5]\, Y => h_i32_NE_2); - - \r.btag.CTX_RNICS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[62]\); - - \r.btag.LVL_RNIPAV7[1]\ : NOR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \LVL[0]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(4), Y => N_99); - - \r.btag.I3_RNIP5923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_99, B => un1_rst_i_0, Y => VALID_RNO); - - \r.btag.I1_RNIF6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNI9N6H[5]\, Y => h_i13_NE_2); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[39]\); - - \r.btag.LVL_RNIU91FC[1]\ : OR3A - port map(A => N_204, B => N_10, C => N_15, Y => N_34_i); - - \r.btag.I2_RNI3QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI3QUF[1]\); - - \r.btag.I1_RNIU9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIU9UF[7]\); - - \r.btag.CTX_RNIGS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[71]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[36]\); - - \r.btag.LVL_RNIL9784[0]\ : AO1A - port map(A => \LVL[0]\, B => h_i32_NE, C => N_11, Y => - hit_0_a3_2_0); - - \r.btag.CTX_RNIKIJG[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_26); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_3); - - \r.btag.VALID_RNIPMVH\ : NOR2A - port map(A => \un1_tag0[43]\, B => N_170_1, Y => - hit_0_a3_0_0); - - \r.btag.I3_RNIQHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIQHUF[1]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_2); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[70]\); - - \r.btag.I2_RNISS411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNI0F6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.CTX_RNIKS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.SU_RNI0HKO1\ : NOR3 - port map(A => N_200, B => SU, C => N_11, Y => N_37); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => SU); - - \r.btag.I1_RNIVI934[0]\ : OR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => h_i13_NE); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_11); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.VALID_RNI0DCOD\ : AOI1B - port map(A => N_34_i, B => N_42, C => hit_0_a3_0_0, Y => - N_232); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_5 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0 : in std_logic_vector(7 to 7); - tlbcam_write_op_1 : in std_logic_vector(1 to 1); - tlbcam_write_op_1_1 : in std_logic_vector(1 to 1); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - tlbcam_write_op_1_0 : in std_logic_vector(1 to 1); - s2_entry_5 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_4 : in std_logic_vector(2 to 2); - s2_entry_3 : in std_logic_vector(2 to 2); - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - ctx_0 : in std_logic_vector(7 downto 0); - s2_entry_1_i_a2_0 : out std_logic_vector(0 to 0); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_838 : out std_logic; - N_851 : out std_logic; - N_852 : out std_logic; - N_845 : out std_logic; - N_867 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_200 : in std_logic; - N_42 : in std_logic; - N_866 : out std_logic; - N_596 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_651 : in std_logic; - N_865 : out std_logic; - N_864 : out std_logic; - N_863 : out std_logic; - N_862 : out std_logic; - N_861 : out std_logic; - N_860 : out std_logic; - N_859 : out std_logic; - N_858 : out std_logic; - N_857 : out std_logic; - N_856 : out std_logic; - N_855 : out std_logic; - N_854 : out std_logic; - N_853 : out std_logic; - N_850 : out std_logic; - N_849 : out std_logic; - N_848 : out std_logic; - N_847 : out std_logic; - N_846 : out std_logic; - N_844 : out std_logic; - N_843 : out std_logic; - N_842 : out std_logic; - N_841 : out std_logic; - N_840 : out std_logic; - N_837 : out std_logic; - N_836 : out std_logic; - N_835 : out std_logic; - N_834 : out std_logic; - N_634 : in std_logic; - N_632 : in std_logic; - N_662 : in std_logic; - N_650 : in std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - hit_0_a3_0 : in std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_612 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_204 : in std_logic; - N_170_1 : in std_logic; - hit_i_0 : out std_logic; - N_557 : in std_logic - ); - -end mmutlbcam_0_0_5; - -architecture DEF_ARCH of mmutlbcam_0_0_5 is - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hit_0_1, N_33, N_32, N_169, hit_0_a3_0_0, - \un1_tag0[43]\, hit_0_a3_3_0, h_i13_NE_i_0, - M_1_sqmuxa_0_o3_1_4, hit_0_a3_2_0, \LVL[0]\, h_i32_NE_i_0, - N_159, \I2_RNITE6H[5]\, \I2_RNIPDUF[4]\, - M_1_sqmuxa_0_o3_1_3, \I2_RNIM5UF[3]\, \I2_RNIJTTF[2]\, - M_1_sqmuxa_0_o3_1_0, \un1_tag0[62]\, \I2_RNI0QUF[1]\, - hit_0_a3_5_0, hit_0_a3_7_0, SU, \LVL[1]\, h_i13_NE_5, - \I1_RNI6N6H[5]\, \I1_RNI3F6H[4]\, h_i13_NE_3, - \un1_tag0[74]\, \I1_RNIR9UF[7]\, h_i13_NE_1, - \un1_tag0[70]\, \I1_RNIVDUF[3]\, h_i13_NE_0, - \un1_tag0[68]\, \I1_RNIPTTF[1]\, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI4B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNIT1VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNINHUF[1]\, h_c2_NE_4, h_c2_1_i, - h_c2_0_i, h_c2_NE_1, h_c2_NE_3, \un1_tag0[41]\, h_c2_7_i, - h_c2_NE_2, \un1_tag0[39]\, h_c2_5_i, \un1_tag0[37]\, - h_c2_3_i, h_c2_NE_i_0, N_44, N_43, N_160, N_39, N_162, - \hit_i_0\, N_165, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[35]\, \un1_tag0[36]\, \un1_tag0[38]\, - \un1_tag0[40]\, \un1_tag0[42]\, \un1_tag0[64]\, - \un1_tag0[66]\, \un1_tag0[57]\, \un1_tag0[59]\, - \pteout[0]\, \pteout[1]\, \pteout[2]\, \pteout[3]\, - \pteout[6]\, \pteout[7]\, \pteout[8]\, \pteout[9]\, - \pteout[10]\, \pteout[12]\, \pteout[13]\, \pteout[14]\, - \pteout[15]\, \pteout[16]\, \pteout[19]\, \pteout[20]\, - \pteout[21]\, \pteout[22]\, \pteout[23]\, \pteout[24]\, - \pteout[25]\, \pteout[26]\, \pteout[27]\, \pteout[28]\, - \pteout[29]\, \pteout[30]\, \pteout[31]\, \un1_tag0[72]\, - \un1_tag0[73]\, \un1_tag0[75]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[67]\, \un1_tag0[61]\, N_16, - N_163, VALID_RNO_4, N_15, \pteout[11]\, \pteout[18]\, - \pteout[17]\, \pteout[4]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - hit_i_0 <= \hit_i_0\; - - \r.btag.LVL_RNI4JC6D[1]\ : OA1 - port map(A => N_163, B => hit_0_a3_3_0, C => N_42, Y => - N_165); - - \r.btag.LVL_RNIFFGA5[1]\ : NOR3A - port map(A => \LVL[1]\, B => N_159, C => N_162, Y => N_32); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[8]\); - - \r.btag.I2_RNIJTTF[2]\ : XOR2 - port map(A => \un1_tag0[64]\, B => N_650, Y => - \I2_RNIJTTF[2]\); - - \r.btag.I1_RNI7I934[0]\ : NOR3C - port map(A => h_i13_NE_1, B => h_i13_NE_0, C => h_i13_NE_5, - Y => h_i13_NE_i_0); - - \r.btag.PPN_RNIL106[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_3(2), Y => N_846); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \LVL[1]\); - - \r.btag.I2_RNITH9E7[4]\ : OR3C - port map(A => h_i13_NE_i_0, B => M_1_sqmuxa_0_o3_1_4, C => - N_204, Y => hit_0_a3_3_0); - - \r.btag.I2_RNIU4511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI0QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.LVL_RNIUKN05[1]\ : OA1C - port map(A => N_16, B => N_200, C => N_39, Y => N_163); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[63]\); - - \r.btag.I3_RNINRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNIT1VF[3]\, Y => h_i32_NE_1); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[19]\); - - \r.btag.CTX_RNIDS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.ACC_RNIHOI5[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry_3(2), Y => N_837); - - \r.btag.I1_RNI3F6H[4]\ : XOR2 - port map(A => \un1_tag0[72]\, B => N_651, Y => - \I1_RNI3F6H[4]\); - - \r.btag.I1_RNIR9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIR9UF[7]\); - - \r.btag.LVL_RNINF8A3[1]\ : NOR2B - port map(A => hit_0_a3_7_0, B => h_i32_NE_i_0, Y => N_39); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[67]\); - - \r.btag.SU_RNI1NCN1\ : OR3 - port map(A => N_200_0, B => SU, C => N_159, Y => N_44); - - \r.btag.I2_RNIPDUF[4]\ : XOR2 - port map(A => \un1_tag0[66]\, B => N_662, Y => - \I2_RNIPDUF[4]\); - - \r.btag.I1_RNI6N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI6N6H[5]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(1), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[41]\); - - \r.btag.VALID_RNIQ9NA81\ : NOR2B - port map(A => N_557, B => \hit_i_0\, Y => - s2_entry_1_i_a2_0(0)); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => SU); - - \r.btag.PPN_RNI0D8B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_4(2), Y => N_859); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[36]\); - - \r.btag.CTX_RNILS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.CTX_RNI9S44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.PPN_RNIKK6B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_4(2), Y => N_862); - - \r.btag.ACC_RNID4D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_838); - - \r.btag.VALID_RNIKTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[10]\); - - \r.btag.PPN_RNIF106[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_3(2), Y => N_843); - - \r.btag.ACC_RNIFOI5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_3(2), Y => N_836); - - \r.btag.PPN_RNIHC6B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_3(2), Y => N_853); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNIT106[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_3(2), Y => N_850); - - \r.btag.I3_RNIT1VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNIT1VF[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.C_RNINK56\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_3(2), Y => N_841); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[58]\); - - \r.btag.CTX_RNI8P98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_4); - - \r.btag.M_RNIBL56\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_3(2), Y => N_840); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[66]\); - - \r.btag.I1_RNIRJSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNIVDUF[3]\, Y => h_i13_NE_1); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[68]\); - - \r.btag.SU_RNI8ITM8\ : AOI1 - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => N_169); - - \r.btag.PPN_RNID106[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_3(2), Y => N_842); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[22]\); - - \r.btag.LVL_RNI9VMDB[0]\ : NOR3B - port map(A => h_i13_NE_i_0, B => M_1_sqmuxa_0_o3_1_4, C => - hit_0_a3_2_0, Y => N_33); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[29]\); - - \r.btag.CTX_RNIOO98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_4, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[4]\); - - \r.btag.VALID_RNIQAH771\ : OA1B - port map(A => N_165, B => hit_0_a3_0_0, C => hit_0_1, Y => - \hit_i_0\); - - \r.btag.PPN_RNIO47B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_4(2), Y => N_864); - - \r.btag.PPN_RNIMS6B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_4(2), Y => N_863); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[25]\); - - \r.btag.I2_RNITE6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNITE6H[5]\); - - \r.btag.VALID_RNIL8L41\ : OR2B - port map(A => \un1_tag0[43]\, B => h_c2_NE_i_0, Y => N_159); - - \r.btag.PPN_RNI2L8B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_4(2), Y => N_860); - - \r.btag.PPN_RNIN47B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_3(2), Y => N_856); - - \r.btag.I2_RNIT4623[4]\ : NOR3C - port map(A => \I2_RNITE6H[5]\, B => \I2_RNIPDUF[4]\, C => - M_1_sqmuxa_0_o3_1_3, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.PPN_RNIQC7B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_4(2), Y => N_865); - - \r.btag.PPN_RNIPDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_851); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[3]\); - - \r.btag.ET_RNIJLTA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_3(2), Y => N_834); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[1]\); - - \r.btag.CTX_RNI0P98[4]\ : XA1A - port map(A => ctx_0(4), B => \un1_tag0[39]\, C => h_c2_5_i, - Y => h_c2_NE_2); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[11]\); - - \r.btag.I1_RNIK4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIR9UF[7]\, Y => h_i13_NE_3); - - \r.btag.I2_RNIM5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIM5UF[3]\); - - \r.btag.PPN_RNISS7B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_4(2), Y => N_857); - - \r.btag.LVL_RNIGCI44[0]\ : NOR2 - port map(A => \LVL[0]\, B => h_i13_NE_i_0, Y => N_162); - - \r.btag.CTX_RNIG3711[4]\ : NOR3C - port map(A => h_c2_NE_3, B => h_c2_NE_2, C => h_c2_NE_4, Y - => h_c2_NE_i_0); - - \r.btag.PPN_RNIP106[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_3(2), Y => N_848); - - \r.btag.PPN_RNIDDQ3[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry(2), Y => N_845); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[42]\); - - \r.btag.I2_RNI0QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI0QUF[1]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[65]\); - - \r.btag.LVL_RNIJ476[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_5(2), - Y => N_866); - - \r.btag.PPN_RNI9G09[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry(2), Y => N_852); - - \r.btag.LVL_RNI58784[0]\ : AO1D - port map(A => \LVL[0]\, B => h_i32_NE_i_0, C => N_159, Y - => hit_0_a3_2_0); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[27]\); - - \r.btag.CTX_RNI8HJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[56]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[9]\); - - \r.btag.I2_RNI78112[0]\ : NOR3C - port map(A => \I2_RNIM5UF[3]\, B => \I2_RNIJTTF[2]\, C => - M_1_sqmuxa_0_o3_1_0, Y => M_1_sqmuxa_0_o3_1_3); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[24]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I3_RNI5EE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI4B7H[5]\, Y => h_i32_NE_2); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[37]\); - - \r.btag.I1_RNIVDUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNIVDUF[3]\); - - \r.btag.I1_RNITAH32[4]\ : NOR3C - port map(A => \I1_RNI6N6H[5]\, B => \I1_RNI3F6H[4]\, C => - h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[15]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[14]\); - - \r.btag.LVL_RNI9G04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_867); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[7]\); - - \r.btag.I3_RNINHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNINHUF[1]\); - - \r.btag.I1_RNIPTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIPTTF[1]\); - - \r.btag.PPN_RNILS6B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_3(2), Y => N_855); - - \r.btag.CTX_RNIHS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.I1_RNIFJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIPTTF[1]\, Y => h_i13_NE_0); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \LVL[0]\); - - \r.btag.PPN_RNI4T8B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_4(2), Y => N_861); - - \r.btag.I3_RNIBRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNINHUF[1]\, Y => h_i32_NE_0); - - \r.btag.I3_RNI75923[0]\ : NOR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE_i_0); - - \r.btag.LVL_RNINJT71[1]\ : AO1A - port map(A => \LVL[1]\, B => SU, C => h_c2_NE_i_0, Y => - N_16); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[30]\); - - \r.btag.SU_RNIT3KE1\ : AO1A - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.PPN_RNIR106[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_3(2), Y => N_849); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[12]\); - - \r.btag.VALID_RNIMMVH\ : OR2A - port map(A => \un1_tag0[43]\, B => N_170_1, Y => - hit_0_a3_0_0); - - \r.btag.CTX_RNI7S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[16]\); - - \r.btag.PPN_RNIH106[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_3(2), Y => N_844); - - \r.btag.VALID_RNIOJL26\ : OR3C - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE_i_0, - Y => N_43); - - \r.btag.PPN_RNIU48B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_4(2), Y => N_858); - - \r.btag.ET_RNILTTA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_3(2), Y => N_835); - - \r.btag.PPN_RNIN106[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_3(2), Y => N_847); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[72]\); - - \r.btag.PPN_RNIJK6B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_3(2), Y => N_854); - - \r.btag.LVL_RNIGAV7[1]\ : NOR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.LVL_RNI015FP[1]\ : OR3 - port map(A => N_33, B => N_32, C => N_169, Y => hit_0_1); - - \r.btag.I3_RNI4B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI4B7H[5]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ0 is - - port( aaddr : out std_logic_vector(31 downto 2); - address : in std_logic_vector(31 downto 2); - s2_entry : in std_logic_vector(2 downto 0); - dr1write_0_sqmuxa : in std_logic; - syncramZ0_VCC : in std_logic; - lclk_c : in std_logic - ); - -end syncramZ0; - -architecture DEF_ARCH of syncramZ0 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_3 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(2 downto 0) := (others => 'U'); - datain : in std_logic_vector(29 downto 0) := (others => 'U'); - dataout : out std_logic_vector(29 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_3 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_3(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_3 - port map(clk => lclk_c, address(2) => s2_entry(2), - address(1) => s2_entry(1), address(0) => s2_entry(0), - datain(29) => address(31), datain(28) => address(30), - datain(27) => address(29), datain(26) => address(28), - datain(25) => address(27), datain(24) => address(26), - datain(23) => address(25), datain(22) => address(24), - datain(21) => address(23), datain(20) => address(22), - datain(19) => address(21), datain(18) => address(20), - datain(17) => address(19), datain(16) => address(18), - datain(15) => address(17), datain(14) => address(16), - datain(13) => address(15), datain(12) => address(14), - datain(11) => address(13), datain(10) => address(12), - datain(9) => address(11), datain(8) => address(10), - datain(7) => address(9), datain(6) => address(8), - datain(5) => address(7), datain(4) => address(6), - datain(3) => address(5), datain(2) => address(4), - datain(1) => address(3), datain(0) => address(2), - dataout(29) => aaddr(31), dataout(28) => aaddr(30), - dataout(27) => aaddr(29), dataout(26) => aaddr(28), - dataout(25) => aaddr(27), dataout(24) => aaddr(26), - dataout(23) => aaddr(25), dataout(22) => aaddr(24), - dataout(21) => aaddr(23), dataout(20) => aaddr(22), - dataout(19) => aaddr(21), dataout(18) => aaddr(20), - dataout(17) => aaddr(19), dataout(16) => aaddr(18), - dataout(15) => aaddr(17), dataout(14) => aaddr(16), - dataout(13) => aaddr(15), dataout(12) => aaddr(14), - dataout(11) => aaddr(13), dataout(10) => aaddr(12), - dataout(9) => aaddr(11), dataout(8) => aaddr(10), - dataout(7) => aaddr(9), dataout(6) => aaddr(8), - dataout(5) => aaddr(7), dataout(4) => aaddr(6), - dataout(3) => aaddr(5), dataout(2) => aaddr(4), - dataout(1) => aaddr(3), dataout(0) => aaddr(2), enable - => syncramZ0_VCC, write => dr1write_0_sqmuxa); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_3 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_17 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_6 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(7 to 7); - tlbcam_write_op_1_1_0 : in std_logic_vector(7 to 7); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(7 to 7); - s2_entry_1_i_a2_1_2 : in std_logic_vector(1 to 1); - ctx_0 : in std_logic_vector(7 downto 0); - LVL : out std_logic_vector(1 downto 0); - s2_entry_1_i_a2_0 : in std_logic_vector(0 to 0); - s2_entry_1_i_a2_2 : out std_logic_vector(0 to 0); - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_42 : in std_logic; - N_200 : in std_logic; - un1_rst_i_0 : in std_logic; - N_596 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_634 : in std_logic; - N_632 : in std_logic; - N_631_i : in std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - s2_flush_0 : in std_logic; - hit_0_a3_0 : in std_logic; - N_2937_1 : out std_logic; - N_170_1 : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_204 : in std_logic - ); - -end mmutlbcam_0_0_3; - -architecture DEF_ARCH of mmutlbcam_0_0_3 is - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_170, hit_0_1, N_33, N_32, N_169, hit_0_a3_3_0, N_17, - hit_0_a3_1_0, N_159, M_1_sqmuxa_0_o3_1_4, - M_1_sqmuxa_0_o3_1_1, M_1_sqmuxa_0_o3_1_0, - M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, \I2_RNI3F6H[5]\, - \un1_tag0[64]\, \I2_RNIS5UF[3]\, \un1_tag0[62]\, - \I2_RNI6QUF[1]\, hit_0_a3_5_0, \un1_tag0[43]\, - hit_0_a3_7_0, SU, \LVL[1]\, h_i13_NE_5, h_i13_NE_2, - h_i13_NE_3, h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, - \un1_tag0[74]\, \I1_RNI1AUF[7]\, \un1_tag0[72]\, - \I1_RNICN6H[5]\, \un1_tag0[70]\, \I1_RNI5EUF[3]\, - \un1_tag0[68]\, \I1_RNIVTTF[1]\, h_i32_NE_3, - \I3_RNITHUF[1]\, \I3_RNIQ9UF[0]\, h_i32_NE_1, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNIAB7H[5]\, \un1_tag0[58]\, - \I3_RNI32VF[3]\, hit_0_a3_6_0, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, h_i13_NE, N_165, N_44, N_39, \LVL[0]\, N_43, - N_160, \LVL_RNIQ0I33[0]\, N_15, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[56]\, \un1_tag0[57]\, - \un1_tag0[59]\, \un1_tag0[73]\, \un1_tag0[75]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, - \un1_tag0[61]\, VALID_RNO_2, N_38, N_16, N_163, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - - \r.btag.I3_RNIAB7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNIAB7H[5]\); - - \r.btag.VALID_RNIQTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_30); - - \r.btag.VALID_RNIMNL26\ : NOR3B - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE, Y - => N_43); - - \r.btag.I1_RNIL6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNICN6H[5]\, Y => h_i13_NE_2); - - \r.btag.LVL_RNIT4NDB[0]\ : NOR3A - port map(A => \LVL_RNIQ0I33[0]\, B => N_159, C => N_17, Y - => N_33); - - \r.btag.VALID_RNIRLBGE2\ : OR3A - port map(A => s2_entry_1_i_a2_1_2(1), B => N_170, C => - hit_0_1, Y => N_2937_1); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_12); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_20); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[73]\); - - \r.btag.I2_RNI6QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI6QUF[1]\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[69]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[38]\); - - \r.btag.I2_RNI16623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[57]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_28); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_6); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_0_10, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_17); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_0_17, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_24); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_8); - - \r.btag.I2_RNI3F6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNI3F6H[5]\); - - \r.btag.CTX_RNILS44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0(4), Y => h_c2_4_i); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[42]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_0_6, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_13); - - \r.btag.CTX_RNI0IJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[40]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_18); - - \r.btag.I2_RNI2T411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNI3F6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.LVL_RNI0G5FP[0]\ : OR3 - port map(A => N_33, B => N_32, C => N_169, Y => hit_0_1); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[59]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[35]\); - - \r.btag.I2_RNIA5511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI6QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_16); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[41]\); - - \r.btag.I3_RNIHEE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNIAB7H[5]\, Y => h_i32_NE_2); - - \r.btag.I2_RNIHK9E7[0]\ : OR2A - port map(A => N_204, B => N_17, Y => hit_0_a3_3_0); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_0); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_7); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_23); - - \r.btag.SU_RNIIENI\ : OR2 - port map(A => SU, B => N_200_0, Y => hit_0_a3_6_0); - - \r.btag.I1_RNI28OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[68]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_0_7, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_14); - - \r.btag.LVL_RNIR4U51[1]\ : NOR2A - port map(A => \LVL[1]\, B => N_159, Y => hit_0_a3_1_0); - - \r.btag.LVL_RNIAPC6D[1]\ : OA1 - port map(A => N_163, B => hit_0_a3_3_0, C => N_42, Y => - N_165); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_31); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[74]\); - - \r.btag.I3_RNI3STV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNI32VF[3]\, Y => h_i32_NE_1); - - \r.btag.CTX_RNIRS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.CTX_RNIFS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.LVL_RNIQ0I33[0]\ : AO1 - port map(A => h_i32_NE_3, B => h_i32_NE_2, C => \LVL[0]\, Y - => \LVL_RNIQ0I33[0]\); - - \r.btag.I2_RNIS5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIS5UF[3]\); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_22); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[72]\); - - \r.btag.I1_RNIVTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIVTTF[1]\); - - \r.btag.CTX_RNINS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.VALID_RNIBAL41\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => N_159); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_27); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_21); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[66]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[75]\); - - \r.btag.VALID_RNI0A9IF2\ : NOR3A - port map(A => s2_entry_1_i_a2_0(0), B => N_170, C => - hit_0_1, Y => s2_entry_1_i_a2_2(0)); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_15); - - \r.btag.I3_RNIQ9UF[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => N_631_i, Y => - \I3_RNIQ9UF[0]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[60]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[65]\); - - \r.btag.I1_RNICN6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNICN6H[5]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_29); - - \r.btag.LVL_RNIDH8A3[1]\ : NOR3C - port map(A => h_i32_NE_2, B => h_i32_NE_3, C => - hit_0_a3_7_0, Y => N_39); - - \r.btag.LVL_RNI2BV7[1]\ : NOR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.LVL_RNI1JGA5[0]\ : OA1A - port map(A => h_i13_NE, B => \LVL[0]\, C => hit_0_a3_1_0, Y - => N_32); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \LVL[1]\); - - \r.btag.I3_RNIQNQV1[0]\ : NOR3C - port map(A => \I3_RNITHUF[1]\, B => \I3_RNIQ9UF[0]\, C => - h_i32_NE_1, Y => h_i32_NE_3); - - \r.btag.I1_RNI7KSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI5EUF[3]\, Y => h_i13_NE_1); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[67]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_10); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[56]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[63]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_2, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.VALID_RNI6GCOD\ : NOR3A - port map(A => \un1_tag0[43]\, B => N_170_1, C => N_165, Y - => N_170); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_19); - - \r.btag.CTX_RNI4P98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_9); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78_0, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_25); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[58]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_1); - - \r.btag.LVL_RNIGON05[1]\ : OA1B - port map(A => N_200, B => N_16, C => N_39, Y => N_163); - - \r.btag.I3_RNI32VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNI32VF[3]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[61]\); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[64]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[37]\); - - \r.btag.I1_RNINJ934[0]\ : OR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => h_i13_NE); - - \r.btag.I1_RNI5EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI5EUF[3]\); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[62]\); - - \r.btag.I1_RNIRJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIVTTF[1]\, Y => h_i13_NE_0); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \LVL[0]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(7), Y => N_15); - - \r.btag.LVL_RNIJLT71[1]\ : AOI1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => N_38, Y => - N_16); - - \r.btag.CTX_RNIDS44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_2); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[39]\); - - \r.btag.LVL_RNIJGM6[1]\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.I3_RNITHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNITHUF[1]\); - - \r.btag.I2_RNIOPF57[0]\ : OR2A - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE, Y => N_17); - - \r.btag.CTX_RNIKP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[71]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[36]\); - - \r.btag.SU_RNITOCN1\ : NOR2 - port map(A => hit_0_a3_6_0, B => N_159, Y => N_44); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_26); - - \r.btag.CTX_RNIJS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.I1_RNI1AUF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNI1AUF[7]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_3); - - \r.btag.I1_RNILBH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.VALID_RNI2OTM8\ : OA1B - port map(A => N_43, B => N_44, C => hit_0_a3_0, Y => N_169); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_2); - - \r.btag.SU_RNI56KE1\ : AO1C - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.I1_RNI05411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNI1AUF[7]\, Y => h_i13_NE_3); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[70]\); - - \r.btag.I2_RNIL3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIS5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.CTX_RNI0JJG[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => SU); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_11); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_6 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1 : in std_logic_vector(2 to 2); - tlbcam_write_op_1_1 : in std_logic_vector(2 to 2); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_7 : in std_logic; - hrdata_6 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - tlbcam_write_op_1_0 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 to 1); - s2_entry_3 : in std_logic_vector(2 to 2); - s2_entry_2 : in std_logic_vector(2 to 2); - s2_entry_1 : in std_logic_vector(2 to 2); - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - ctx_0 : in std_logic_vector(7 downto 0); - LVL_0_d0 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_770 : out std_logic; - N_783 : out std_logic; - N_777 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_631_i : in std_logic; - N_632 : in std_logic; - N_634 : in std_logic; - N_596 : in std_logic; - N_42 : in std_logic; - N_200 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_799 : out std_logic; - N_797 : out std_logic; - N_796 : out std_logic; - N_795 : out std_logic; - N_794 : out std_logic; - N_793 : out std_logic; - N_792 : out std_logic; - N_791 : out std_logic; - N_790 : out std_logic; - N_789 : out std_logic; - N_788 : out std_logic; - N_787 : out std_logic; - N_786 : out std_logic; - N_785 : out std_logic; - N_784 : out std_logic; - N_782 : out std_logic; - N_781 : out std_logic; - N_780 : out std_logic; - N_779 : out std_logic; - N_778 : out std_logic; - N_776 : out std_logic; - N_775 : out std_logic; - N_774 : out std_logic; - N_773 : out std_logic; - N_772 : out std_logic; - N_769 : out std_logic; - N_768 : out std_logic; - N_767 : out std_logic; - N_766 : out std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - hit_0_a3_0 : in std_logic; - N_2937_1 : in std_logic; - N_557 : in std_logic; - N_2937 : out std_logic; - hit : in std_logic; - N_3068 : out std_logic; - N_170_1 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_204 : in std_logic - ); - -end mmutlbcam_0_0_6; - -architecture DEF_ARCH of mmutlbcam_0_0_6 is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal cam_hit_all_1_2_i_a4_1, N_33, N_32, VALID_RNI7JTM8, - hit_0_a3_3_0, N_17_i_0, hit_0_a3_1_0, \LVL[1]\, N_159, - M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNIUE6H[5]\, \un1_tag0[64]\, \I2_RNIN5UF[3]\, - \un1_tag0[62]\, \I2_RNI1QUF[1]\, hit_0_a3_5_0, - \un1_tag0[43]\, hit_0_a3_7_0, SU, h_i32_NE_3, - \I3_RNIOHUF[1]\, \I3_RNIL9UF[0]\, h_i32_NE_1, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI5B7H[5]\, \un1_tag0[58]\, - \I3_RNIU1VF[3]\, h_i13_NE_5, h_i13_NE_2, h_i13_NE_3, - h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, \un1_tag0[74]\, - \I1_RNIS9UF[7]\, \un1_tag0[72]\, \I1_RNI7N6H[5]\, - \un1_tag0[70]\, \I1_RNI0EUF[3]\, \un1_tag0[68]\, - \I1_RNIQTTF[1]\, hit_0_a3_6_0, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, h_i13_NE_i_0, N_43, N_160, N_170, N_165, N_44, - N_39, N_161, \LVL[0]\, \N_3068\, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \pteout[0]\, \pteout[1]\, \pteout[2]\, - \pteout[3]\, \pteout[6]\, \pteout[7]\, \pteout[8]\, - \pteout[9]\, \pteout[10]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[15]\, \pteout[16]\, \pteout[18]\, - \pteout[19]\, \pteout[20]\, \pteout[21]\, \pteout[22]\, - \pteout[23]\, \pteout[24]\, \pteout[25]\, \pteout[26]\, - \pteout[27]\, \pteout[28]\, \pteout[29]\, \pteout[30]\, - \pteout[31]\, \un1_tag0[73]\, \un1_tag0[75]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, N_38, - N_16, N_163, \un1_tag0[61]\, \un1_tag0[59]\, - \un1_tag0[57]\, \un1_tag0[56]\, VALID_RNO_5, N_15, - \pteout[11]\, \pteout[17]\, \pteout[4]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - LVL_0_d0 <= \LVL[0]\; - N_3068 <= \N_3068\; - - \r.btag.I1_RNI1BH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.LVL_RNI2GGA5[0]\ : OAI1 - port map(A => h_i13_NE_i_0, B => \LVL[0]\, C => - hit_0_a3_1_0, Y => N_32); - - \r.btag.PPN_RNIGHV5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_2(2), Y => N_776); - - \r.btag.CTX_RNICHJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[8]\); - - \r.btag.LVL_RNIJAV7[1]\ : NOR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.I1_RNI0EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI0EUF[3]\); - - \r.btag.PPN_RNIEK5B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_2(2), Y => N_784); - - \r.btag.PPN_RNIKHV5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_2(2), Y => N_778); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \LVL[1]\); - - \r.btag.I2_RNIN5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIN5UF[3]\); - - \r.btag.I2_RNI35623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.PPN_RNIMHV5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_2(2), Y => N_779); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[63]\); - - \r.btag.LVL_RNI9GM6[1]\ : OR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.LVL_RNI70NDB[0]\ : OR3C - port map(A => N_161, B => N_159, C => N_17_i_0, Y => N_33); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[19]\); - - \r.btag.I2_RNIB3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIN5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.PPN_RNIQHV5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_2(2), Y => N_781); - - \r.btag.PPN_RNI0T7B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_2(2), Y => N_793); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(2), Y => N_15); - - \r.btag.PPN_RNIRDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_783); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[41]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[36]\); - - \r.btag.I3_RNI7EE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI5B7H[5]\, Y => h_i32_NE_2); - - \r.btag.PPN_RNIGS5B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_2(2), Y => N_785); - - \r.btag.PPN_RNINK6B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_3(2), Y => N_796); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[10]\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.I3_RNIU1VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNIU1VF[3]\); - - \r.btag.PPN_RNIQ47B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_2(2), Y => N_790); - - \r.btag.LVL_RNI0G8A3[1]\ : OR3C - port map(A => h_i32_NE_2, B => h_i32_NE_3, C => - hit_0_a3_7_0, Y => N_39); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.I1_RNIE7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_5); - - \r.btag.I1_RNIHJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIQTTF[1]\, Y => h_i13_NE_0); - - \r.btag.CTX_RNIGS44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0(4), Y => h_c2_4_i); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[66]\); - - \r.btag.I3_RNIOHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIOHUF[1]\); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[68]\); - - \r.btag.CTX_RNIIS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.M_RNIA556\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_2(2), Y => N_772); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[22]\); - - \r.btag.LVL_RNI1KT71[1]\ : AO1B - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => N_38, Y => - N_16); - - \r.btag.LVL_RNIH466[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry_3(2), - Y => N_799); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[29]\); - - \r.btag.LVL_RNI5KC6D[1]\ : AO1B - port map(A => hit_0_a3_3_0, B => N_163, C => N_42, Y => - N_165); - - \r.btag.PPN_RNICHV5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_2(2), Y => N_774); - - \r.btag.CTX_RNIMS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.ACC_RNIG8I5[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry_2(2), Y => N_769); - - \r.btag.CTX_RNIQO98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_5, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[4]\); - - \r.btag.I1_RNI7N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI7N6H[5]\); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[25]\); - - \r.btag.PPN_RNIPS6B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_3(2), Y => N_797); - - \r.btag.PPN_RNILC6B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_3(2), Y => N_795); - - \r.btag.CTX_RNIAP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[3]\); - - \r.btag.VALID_RNILTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.I3_RNI6NQV1[0]\ : NOR3C - port map(A => \I3_RNIOHUF[1]\, B => \I3_RNIL9UF[0]\, C => - h_i32_NE_1, Y => h_i32_NE_3); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[60]\); - - \r.btag.I3_RNI5B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI5B7H[5]\); - - \r.btag.C_RNIM456\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_2(2), Y => N_773); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[75]\); - - \r.btag.PPN_RNISC7B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_2(2), Y => N_791); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[1]\); - - \r.btag.CTX_RNIES44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.PPN_RNIFDQ3[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry(2), Y => N_777); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[11]\); - - \r.btag.I2_RNI1QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI1QUF[1]\); - - \r.btag.LVL_RNIHLN05[1]\ : AO1C - port map(A => N_200, B => N_16, C => N_39, Y => N_163); - - \r.btag.CTX_RNICIJG[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIEHV5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_2(2), Y => N_775); - - \r.btag.VALID_RNI698RE2\ : NOR3B - port map(A => N_170, B => cam_hit_all_1_2_i_a4_1, C => hit, - Y => \N_3068\); - - \r.btag.PPN_RNIKC6B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_2(2), Y => N_787); - - \r.btag.I3_RNIPRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNIU1VF[3]\, Y => h_i32_NE_1); - - \r.btag.VALID_RNI1UPEU4\ : OR3B - port map(A => N_557, B => \N_3068\, C => N_2937_1, Y => - N_2937); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[0]\); - - \r.btag.PPN_RNIOHV5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_2(2), Y => N_780); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[20]\); - - \r.btag.I2_RNIOS411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNIUE6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[65]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[27]\); - - \r.btag.PPN_RNIOS6B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_2(2), Y => N_789); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[56]\); - - \r.btag.I2_RNIUE6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNIUE6H[5]\); - - \r.btag.I2_RNIBI9E7[0]\ : NOR2B - port map(A => N_204, B => N_17_i_0, Y => hit_0_a3_3_0); - - \r.btag.I1_RNIB6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNI7N6H[5]\, Y => h_i13_NE_2); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[9]\); - - \r.btag.PPN_RNIMK6B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_2(2), Y => N_788); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[24]\); - - \r.btag.VALID_RNISACOD\ : OR3B - port map(A => \un1_tag0[43]\, B => N_165, C => N_170_1, Y - => N_170); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I1_RNITJSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI0EUF[3]\, Y => h_i13_NE_1); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[37]\); - - \r.btag.PPN_RNISHV5[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_2(2), Y => N_782); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[15]\); - - \r.btag.PPN_RNIUK7B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_2(2), Y => N_792); - - \r.btag.ET_RNIKDTA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_2(2), Y => N_767); - - \r.btag.SU_RNIBNCN1\ : OR2B - port map(A => hit_0_a3_6_0, B => N_159, Y => N_44); - - \r.btag.CTX_RNI8S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[7]\); - - \r.btag.PPN_RNII46B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_2(2), Y => N_786); - - \r.btag.ACC_RNIE8I5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_2(2), Y => N_768); - - \r.btag.I2_RNI05511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI1QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.SU_RNIDENI\ : NOR2 - port map(A => SU, B => N_200_0, Y => hit_0_a3_6_0); - - \r.btag.LVL_RNINVH33[0]\ : AO1 - port map(A => h_i32_NE_3, B => h_i32_NE_2, C => \LVL[0]\, Y - => N_161); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \LVL[0]\); - - \r.btag.I1_RNIQTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIQTTF[1]\); - - \r.btag.I1_RNIFI934[0]\ : NOR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => - h_i13_NE_i_0); - - \r.btag.PPN_RNIJ46B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_3(2), Y => N_794); - - \r.btag.I3_RNIL9UF[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => N_631_i, Y => - \I3_RNIL9UF[0]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[30]\); - - \r.btag.LVL_RNIG35FP[0]\ : NOR3C - port map(A => N_33, B => N_32, C => VALID_RNI7JTM8, Y => - cam_hit_all_1_2_i_a4_1); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[12]\); - - \r.btag.VALID_RNIU8L41\ : NOR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => N_159); - - \r.btag.I2_RNIINF57[0]\ : NOR2B - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE_i_0, Y => - N_17_i_0); - - \r.btag.LVL_RNI93U51[1]\ : NOR2B - port map(A => \LVL[1]\, B => N_159, Y => hit_0_a3_1_0); - - \r.btag.VALID_RNIDKL26\ : OR3C - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE_i_0, - Y => N_43); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[16]\); - - \r.btag.VALID_RNI7JTM8\ : AO1 - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => - VALID_RNI7JTM8); - - \r.btag.I1_RNIS9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIS9UF[7]\); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[72]\); - - \r.btag.I1_RNIM4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIS9UF[7]\, Y => h_i13_NE_3); - - \r.btag.CTX_RNIAS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.ACC_RNIF4D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_770); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[73]\); - - \r.btag.ET_RNIFLSA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_1(2), Y => N_766); - - \r.btag.SU_RNI94KE1\ : AO1A - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_7 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1 : in std_logic_vector(3 to 3); - tlbcam_write_op_1_1 : in std_logic_vector(3 to 3); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_7 : in std_logic; - hrdata_6 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - tlbcam_write_op_1_0 : in std_logic_vector(3 to 3); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_5 : in std_logic_vector(2 to 2); - s2_entry_4 : in std_logic_vector(2 to 2); - pteout_0_7 : in std_logic; - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - ctx : in std_logic_vector(6 to 6); - ctx_0_5 : in std_logic; - ctx_0_4 : in std_logic; - ctx_0_3 : in std_logic; - ctx_0_1 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_2 : in std_logic; - ctx_0_7 : in std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - C_RNIL004 : out std_logic; - N_872 : out std_logic; - N_885 : out std_logic; - N_886 : out std_logic; - N_879 : out std_logic; - N_901 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_900 : out std_logic; - N_200 : in std_logic; - N_596 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_899 : out std_logic; - N_898 : out std_logic; - N_897 : out std_logic; - N_896 : out std_logic; - N_895 : out std_logic; - N_894 : out std_logic; - N_893 : out std_logic; - N_892 : out std_logic; - N_891 : out std_logic; - N_890 : out std_logic; - N_889 : out std_logic; - N_888 : out std_logic; - N_887 : out std_logic; - N_884 : out std_logic; - N_883 : out std_logic; - N_882 : out std_logic; - N_881 : out std_logic; - N_880 : out std_logic; - N_878 : out std_logic; - N_877 : out std_logic; - N_876 : out std_logic; - N_874 : out std_logic; - N_871 : out std_logic; - N_870 : out std_logic; - N_869 : out std_logic; - N_868 : out std_logic; - N_634 : in std_logic; - N_632 : in std_logic; - N_662 : in std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - hit_0_a3_0 : in std_logic; - N_204 : in std_logic; - N_42 : in std_logic; - hit : out std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_620 : in std_logic; - N_170_1 : in std_logic - ); - -end mmutlbcam_0_0_7; - -architecture DEF_ARCH of mmutlbcam_0_0_7 is - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hit_0_0, hit_0_a3_2_0, N_17_i_0, N_32_i, hit_0_a3_0_0, - \un1_tag0[43]\, h_i32_NE, \LVL[0]\, N_159, hit_0_a3_1_0, - \LVL[1]\, M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[67]\, - \I2_RNIRDUF[4]\, \un1_tag0[64]\, \I2_RNIO5UF[3]\, - \un1_tag0[62]\, \I2_RNI2QUF[1]\, hit_0_a3_5_0, - hit_0_a3_7_0, N_45, h_i13_NE_5, h_i13_NE_2, h_i13_NE_3, - h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, \un1_tag0[74]\, - \I1_RNIT9UF[7]\, \un1_tag0[72]\, \I1_RNI8N6H[5]\, - \un1_tag0[70]\, \I1_RNI1EUF[3]\, \un1_tag0[68]\, - \I1_RNIRTTF[1]\, h_i32_NE_2, \un1_tag0[60]\, - \I3_RNI6B7H[5]\, h_i32_NE_1, \un1_tag0[58]\, - \I3_RNIV1VF[3]\, h_i32_NE_0, \un1_tag0[56]\, - \I3_RNIPHUF[1]\, hit_0_a3_6_0, SU, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, \un1_tag0[42]\, h_c2_6_i, h_c2_NE_1, - \un1_tag0[37]\, h_c2_3_i, h_c2_NE_0, \un1_tag0[35]\, - h_c2_1_i, h_i13_NE, N_169, N_170, N_41, N_163, - h_c2_NE_i_0, N_44, N_43, N_160, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[36]\, \un1_tag0[38]\, - \un1_tag0[39]\, \un1_tag0[40]\, \un1_tag0[41]\, - \un1_tag0[66]\, \un1_tag0[57]\, \un1_tag0[59]\, - \pteout[0]\, \pteout[1]\, \pteout[2]\, \pteout[3]\, - \pteout[6]\, \pteout[8]\, \pteout[9]\, \pteout[10]\, - \pteout[12]\, \pteout[13]\, \pteout[14]\, \pteout[15]\, - \pteout[16]\, \pteout[19]\, \pteout[20]\, \pteout[21]\, - \pteout[22]\, \pteout[23]\, \pteout[24]\, \pteout[25]\, - \pteout[26]\, \pteout[27]\, \pteout[28]\, \pteout[29]\, - \pteout[30]\, \pteout[31]\, \un1_tag0[73]\, - \un1_tag0[75]\, \un1_tag0[63]\, \un1_tag0[65]\, - \un1_tag0[61]\, N_38, N_40, VALID_RNO_6, N_15, - \pteout[11]\, \pteout[18]\, \pteout[17]\, \pteout[4]\, - \pteout[7]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \r.btag.I2_RNI25511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI2QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.PPN_RNITDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_885); - - \r.btag.I1_RNID6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNI8N6H[5]\, Y => h_i13_NE_2); - - \r.btag.LVL_RNI94FHC[1]\ : OR3C - port map(A => N_17_i_0, B => N_204, C => N_163, Y => N_41); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[8]\); - - \r.btag.PPN_RNIUH06[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_4(2), Y => N_881); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \LVL[1]\); - - \r.btag.SU_RNIEENI\ : NOR2 - port map(A => SU, B => N_200_0, Y => hit_0_a3_6_0); - - \r.btag.I1_RNIT9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIT9UF[7]\); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[63]\); - - \r.btag.CTX_RNIOKNA[7]\ : XA1A - port map(A => ctx_0_7, B => \un1_tag0[42]\, C => h_c2_6_i, - Y => h_c2_NE_3); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[19]\); - - \r.btag.PPN_RNIVK7B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_5(2), Y => N_898); - - \r.btag.I3_RNIRRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNIV1VF[3]\, Y => h_i32_NE_1); - - \r.btag.LVL_RNIVUB81[1]\ : OR2A - port map(A => \LVL[1]\, B => N_159, Y => hit_0_a3_1_0); - - \r.btag.LVL_RNIN476[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_5(2), - Y => N_900); - - \r.btag.LVL_RNIH4LA4[0]\ : OA1C - port map(A => h_i32_NE, B => \LVL[0]\, C => N_159, Y => - hit_0_a3_2_0); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(3), Y => N_15); - - \r.btag.PPN_RNIKH06[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_4(2), Y => N_876); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[41]\); - - \r.btag.I1_RNIJJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIRTTF[1]\, Y => h_i13_NE_0); - - \r.btag.VALID_RNIUAPR8\ : AO1D - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => N_169); - - \r.btag.I1_RNI5BH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[36]\); - - \r.btag.LVL_RNI1CUC5[0]\ : AO1A - port map(A => \LVL[0]\, B => h_i13_NE, C => hit_0_a3_1_0, Y - => N_32_i); - - \r.btag.SU_RNIAGM6\ : NOR2A - port map(A => SU, B => \LVL[0]\, Y => N_45); - - \r.btag.PPN_RNISH06[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_4(2), Y => N_880); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[10]\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[57]\); - - \r.btag.PPN_RNI3D8B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_5(2), Y => N_891); - - \r.btag.PPN_RNIMH06[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_4(2), Y => N_877); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN_RNI5L8B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_5(2), Y => N_892); - - \r.btag.I1_RNIRTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIRTTF[1]\); - - \r.btag.VALID_RNIEG356\ : NOR3B - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE, Y - => N_43); - - \r.btag.SU_RNI102H1\ : OR3 - port map(A => N_38, B => h_c2_NE_i_0, C => N_45, Y => N_160); - - \r.btag.PPN_RNI4I06[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_4(2), Y => N_884); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[21]\); - - \r.btag.CTX_RNIKO98[0]\ : XA1A - port map(A => ctx_0_0, B => \un1_tag0[35]\, C => h_c2_1_i, - Y => h_c2_NE_0); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[58]\); - - \r.btag.I2_RNI95623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[38]\); - - \r.btag.I3_RNIJ5923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_6); - - \r.btag.PPN_RNI158B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_5(2), Y => N_890); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[66]\); - - \r.btag.VALID_RNIOMVH\ : NOR2A - port map(A => \un1_tag0[43]\, B => N_170_1, Y => - hit_0_a3_0_0); - - \r.btag.PPN_RNIBD9B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_5(2), Y => N_895); - - \r.btag.I3_RNIV1VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNIV1VF[3]\); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[68]\); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[22]\); - - \r.btag.PPN_RNITK7B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_5(2), Y => N_888); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[2]\); - - \r.btag.PPN_RNI959B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_5(2), Y => N_894); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[29]\); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[64]\); - - \r.btag.ACC_RNIM8J5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_4(2), Y => N_870); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_6, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[4]\); - - \r.btag.SU_RNIBGM6\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.I2_RNIRDUF[4]\ : XOR2 - port map(A => \un1_tag0[66]\, B => N_662, Y => - \I2_RNIRDUF[4]\); - - \r.btag.PPN_RNIVS7B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_5(2), Y => N_889); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[25]\); - - \r.btag.PPN_RNIDG09[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry(2), Y => N_886); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[3]\); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[1]\); - - \r.btag.PPN_RNIHDQ3[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry(2), Y => N_879); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[11]\); - - \r.btag.CTX_RNIFS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.C_RNIL004\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry(2), Y => C_RNIL004); - - \r.btag.ACC_RNIO8J5[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry_4(2), Y => N_871); - - \r.btag.I1_RNINI934[0]\ : OR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => h_i13_NE); - - \r.btag.VALID_RNIA7QQD\ : AO1B - port map(A => N_42, B => N_41, C => hit_0_a3_0_0, Y => - N_170); - - \r.btag.CTX_RNIJS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0_5, Y => h_c2_5_i); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[20]\); - - \r.btag.SU_RNI71TO1\ : OA1B - port map(A => N_38, B => h_c2_NE_i_0, C => N_200, Y => N_40); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[42]\); - - \r.btag.ACC_RNIH4D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_872); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[65]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[27]\); - - \r.btag.I2_RNI2QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI2QUF[1]\); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[56]\); - - \r.btag.PPN_RNI0I06[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_4(2), Y => N_882); - - \r.btag.I2_RNIO5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIO5UF[3]\); - - \r.btag.SU_RNI1JQP1\ : NOR2A - port map(A => hit_0_a3_6_0, B => N_159, Y => N_44); - - \r.btag.I2_RNI0OF57[0]\ : NOR2A - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE, Y => - N_17_i_0); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNI2I06[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_4(2), Y => N_883); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[24]\); - - \r.btag.CTX_RNI1OI6[6]\ : XNOR2 - port map(A => \un1_tag0[41]\, B => ctx(6), Y => h_c2_6_i); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.VALID_RNIMTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[40]\); - - \r.btag.PPN_RNI1T7B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_5(2), Y => N_899); - - \r.btag.LVL_RNIGH535[1]\ : AO1A - port map(A => h_i32_NE, B => hit_0_a3_7_0, C => N_40, Y => - N_163); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[37]\); - - \r.btag.LVL_RNIMAV7[1]\ : NOR2A - port map(A => N_45, B => \LVL[1]\, Y => hit_0_a3_7_0); - - \r.btag.PPN_RNIOH06[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_4(2), Y => N_878); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[15]\); - - \r.btag.LVL_RNIQQMJ71[0]\ : OR3C - port map(A => hit_0_0, B => N_169, C => N_170, Y => hit); - - \r.btag.I1_RNIVJSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI1EUF[3]\, Y => h_i13_NE_1); - - \r.btag.ET_RNISDUA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_4(2), Y => N_869); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[7]\); - - \r.btag.I3_RNI9EE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI6B7H[5]\, Y => h_i32_NE_2); - - \r.btag.VALID_RNIJ4371\ : OR2B - port map(A => \un1_tag0[43]\, B => h_c2_NE_i_0, Y => N_159); - - \r.btag.CTX_RNIHS44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0_4, Y => h_c2_4_i); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \LVL[0]\); - - \r.btag.ET_RNIQ5UA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_4(2), Y => N_868); - - \r.btag.CTX_RNISD1J[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIR47B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_5(2), Y => N_896); - - \r.btag.CTX_RNISO98[2]\ : XA1A - port map(A => ctx_0_2, B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.CTX_RNICVK31[0]\ : NOR3C - port map(A => h_c2_NE_1, B => h_c2_NE_0, C => h_c2_NE_5, Y - => h_c2_NE_i_0); - - \r.btag.LVL_RNII83TG[0]\ : AOI1B - port map(A => hit_0_a3_2_0, B => N_17_i_0, C => N_32_i, Y - => hit_0_0); - - \r.btag.I1_RNIO4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIT9UF[7]\, Y => h_i13_NE_3); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[30]\); - - \r.btag.PPN_RNIOS6B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_4(2), Y => N_887); - - \r.btag.I3_RNIFRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNIPHUF[1]\, Y => h_i32_NE_0); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[12]\); - - \r.btag.I3_RNI6B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI6B7H[5]\); - - \r.btag.I3_RNIPHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIPHUF[1]\); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[16]\); - - \r.btag.I1_RNII7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN_RNITC7B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_5(2), Y => N_897); - - \r.btag.LVL_RNIDG04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_901); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[59]\); - - \r.btag.M_RNII566\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_4(2), Y => N_874); - - \r.btag.PPN_RNI7T8B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_5(2), Y => N_893); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[72]\); - - \r.btag.I1_RNI8N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI8N6H[5]\); - - \r.btag.CTX_RNIBS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_1, Y => h_c2_1_i); - - \r.btag.I2_RNIQS411[5]\ : XA1 - port map(A => N_620, B => \un1_tag0[67]\, C => - \I2_RNIRDUF[4]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.I1_RNI1EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI1EUF[3]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[73]\); - - \r.btag.I2_RNID3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIO5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_1 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_17 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_6 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(6 to 6); - tlbcam_write_op_1_1_0 : in std_logic_vector(6 to 6); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - s2_entry_5 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(0 to 0); - tlbcam_write_op_1_0 : in std_logic_vector(6 to 6); - ctx_0 : in std_logic_vector(7 downto 0); - LVL_1 : out std_logic; - s2_entry_1_i_a2_1_2 : out std_logic_vector(1 to 1); - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_635 : in std_logic; - N_639 : in std_logic; - N_665 : in std_logic; - N_597 : in std_logic; - N_798 : out std_logic; - N_632 : in std_logic; - N_634 : in std_logic; - N_596 : in std_logic; - un1_rst_i_0 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - s2_flush_0 : in std_logic; - hit_0_a3_0 : in std_logic; - N_42 : in std_logic; - N_200 : in std_logic; - N_204 : in std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_170_1 : in std_logic - ); - -end mmutlbcam_0_0_1; - -architecture DEF_ARCH of mmutlbcam_0_0_1 is - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \s2_entry_1_i_a2_1_1[1]\, N_170, N_33, N_32_i_0, - SU_RNI4G5O8, hit_0_a3_0_0, \un1_tag0[43]\, - M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNI2F6H[5]\, \un1_tag0[64]\, \I2_RNIR5UF[3]\, - \un1_tag0[62]\, \I2_RNI5QUF[1]\, hit_0_a3_5_1, N_45, N_16, - hit_0_a3_5_0, hit_0_a3_7_0, h_i13_NE_5, h_i13_NE_2, - h_i13_NE_3, h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, - \un1_tag0[74]\, \I1_RNI0AUF[7]\, \un1_tag0[72]\, - \I1_RNIBN6H[5]\, \un1_tag0[70]\, \I1_RNI4EUF[3]\, - \un1_tag0[68]\, \I1_RNIUTTF[1]\, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI9B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNI22VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNISHUF[1]\, h_c2_NE_4, h_c2_1_i, - h_c2_0_i, h_c2_NE_1, h_c2_NE_3, \un1_tag0[41]\, h_c2_7_i, - h_c2_NE_2, \un1_tag0[39]\, h_c2_5_i, \un1_tag0[37]\, - h_c2_3_i, N_17_i_0, h_c2_NE_i_0, h_i32_NE, N_161, N_159, - \LVL[1]\, N_162, N_41, N_163, N_44, SU, N_43, N_15, - \un1_tag0[35]\, \un1_tag0[36]\, \un1_tag0[38]\, - \un1_tag0[40]\, \un1_tag0[42]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[67]\, VALID_RNO_0, N_38, - \LVL[0]\, N_40, \un1_tag0[61]\, \un1_tag0[59]\, - \un1_tag0[57]\, \un1_tag0[75]\, \un1_tag0[73]\, - \un1_tag0[71]\, \un1_tag0[69]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - LVL_1 <= \LVL[1]\; - - \r.btag.VALID_RNI4FCOD\ : AO1B - port map(A => N_41, B => N_42, C => hit_0_a3_0_0, Y => - N_170); - - \r.btag.VALID_RNI2AL41\ : OR2B - port map(A => \un1_tag0[43]\, B => h_c2_NE_i_0, Y => N_159); - - \r.btag.I1_RNIPJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIUTTF[1]\, Y => h_i13_NE_0); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_30); - - \r.btag.I1_RNIHBH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.LVL_RNITNN05[1]\ : AO1D - port map(A => hit_0_a3_7_0, B => h_i32_NE, C => N_40, Y => - N_163); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_12); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_20); - - \r.btag.VALID_RNI1NL26\ : OR3C - port map(A => h_i13_NE_4, B => h_i13_NE_5, C => - hit_0_a3_5_1, Y => N_43); - - \r.btag.LVL_RNI0C1FC[1]\ : OR3C - port map(A => N_17_i_0, B => N_204, C => N_163, Y => N_41); - - \r.btag.CTX_RNIMS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.LVL_RNILLP871[1]\ : NOR2B - port map(A => \s2_entry_1_i_a2_1_1[1]\, B => N_170, Y => - s2_entry_1_i_a2_1_2(1)); - - \r.btag.CTX_RNICS44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.I1_RNI0AUF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNI0AUF[7]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[73]\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[69]\); - - \r.btag.CTX_RNIAP98[4]\ : XA1A - port map(A => ctx_0(4), B => \un1_tag0[39]\, C => h_c2_5_i, - Y => h_c2_NE_2); - - \r.btag.LVL_RNIL476[0]\ : MX2 - port map(A => LVL_0(0), B => \LVL[0]\, S => s2_entry_5(2), - Y => N_798); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[38]\); - - \r.btag.I3_RNI22VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNI22VF[3]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[57]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_28); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_6); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_0_10, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_17); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_0_17, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_24); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_8); - - \r.btag.I2_RNI2F6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNI2F6H[5]\); - - \r.btag.LVL_RNIH6DGP[1]\ : NOR3C - port map(A => N_33, B => N_32_i_0, C => SU_RNI4G5O8, Y => - \s2_entry_1_i_a2_1_1[1]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[42]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_0_6, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_13); - - \r.btag.I2_RNIJ3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIR5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[40]\); - - \r.btag.VALID_RNII3CV1\ : AOI1B - port map(A => N_45, B => N_16, C => hit_0_a3_5_0, Y => - hit_0_a3_5_1); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_18); - - \r.btag.LVL_RNIV3NDB[0]\ : OR3B - port map(A => N_161, B => N_17_i_0, C => N_159, Y => N_33); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[59]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[35]\); - - \r.btag.I3_RNILRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNISHUF[1]\, Y => h_i32_NE_0); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_16); - - \r.btag.I1_RNI5KSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI4EUF[3]\, Y => h_i13_NE_1); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[41]\); - - \r.btag.LVL_RNITDI44[0]\ : AOI1 - port map(A => h_i13_NE_5, B => h_i13_NE_4, C => \LVL[0]\, Y - => N_162); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_0); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_7); - - \r.btag.SU_RNIGGM6\ : OR2A - port map(A => SU, B => \LVL[0]\, Y => N_45); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_23); - - \r.btag.I2_RNI0T411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNI2F6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[68]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_0_7, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_14); - - \r.btag.SU_RNI9LT71\ : NOR2 - port map(A => h_c2_NE_i_0, B => N_38, Y => N_16); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_31); - - \r.btag.LVL_RNIJ0I33[0]\ : OR2A - port map(A => h_i32_NE, B => \LVL[0]\, Y => N_161); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[74]\); - - \r.btag.CTX_RNIIS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.SU_RNIKHKO1\ : OR3 - port map(A => N_200, B => SU, C => N_159, Y => N_44); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_22); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[72]\); - - \r.btag.VALID_RNIRMVH\ : NOR2A - port map(A => \un1_tag0[43]\, B => N_170_1, Y => - hit_0_a3_0_0); - - \r.btag.I3_RNI9B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI9B7H[5]\); - - \r.btag.I3_RNIFEE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI9B7H[5]\, Y => h_i32_NE_2); - - \r.btag.I2_RNIAPF57[0]\ : NOR3C - port map(A => h_i13_NE_4, B => h_i13_NE_5, C => - M_1_sqmuxa_0_o3_1_4, Y => N_17_i_0); - - \r.btag.VALID_RNIPTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_27); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_21); - - \r.btag.I2_RNI85511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI5QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[66]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[75]\); - - \r.btag.CTX_RNIQS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_15); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[60]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[65]\); - - \r.btag.I1_RNIBN6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNIBN6H[5]\); - - \r.btag.SU_RNIHGM6\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_29); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \LVL[1]\); - - \r.btag.I2_RNIR5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIR5UF[3]\); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[67]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_10); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[56]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[63]\); - - \r.btag.I1_RNIU4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNI0AUF[7]\, Y => h_i13_NE_3); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_0, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.I3_RNISHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNISHUF[1]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_19); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_9); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78_0, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_25); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[58]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_1); - - \r.btag.I2_RNI5QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI5QUF[1]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[61]\); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[64]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[37]\); - - \r.btag.I2_RNIR5623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.CTX_RNISHJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.CTX_RNI2P98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.CTX_RNIES44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.I3_RNI1STV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNI22VF[3]\, Y => h_i32_NE_1); - - \r.btag.CTX_RNIO4711[4]\ : NOR3C - port map(A => h_c2_NE_3, B => h_c2_NE_2, C => h_c2_NE_4, Y - => h_c2_NE_i_0); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[62]\); - - \r.btag.SU_RNIP6FM1\ : NOR2 - port map(A => N_16, B => N_200, Y => N_40); - - \r.btag.I3_RNI56923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \LVL[0]\); - - \r.btag.I1_RNIU7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(6), Y => N_15); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_0); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[39]\); - - \r.btag.I1_RNIUTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIUTTF[1]\); - - \r.btag.LVL_RNIEIGA5[1]\ : OR3A - port map(A => \LVL[1]\, B => N_159, C => N_162, Y => - N_32_i_0); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[71]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[36]\); - - \r.btag.I1_RNIJ6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNIBN6H[5]\, Y => h_i13_NE_2); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_26); - - \r.btag.I1_RNI4EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI4EUF[3]\); - - \r.btag.CTX_RNIIP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_3); - - \r.btag.LVL_RNIVAV7[1]\ : OR2 - port map(A => \LVL[1]\, B => N_45, Y => hit_0_a3_7_0); - - \r.btag.SU_RNI4G5O8\ : AO1 - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => - SU_RNI4G5O8); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_2); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[70]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => SU); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_11); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlb_10_8_0_1_0 is - - port( address_0 : in std_logic_vector(31 downto 2); - aaddr : out std_logic_vector(31 downto 2); - ctx_0 : in std_logic_vector(7 downto 0); - ctx : in std_logic_vector(7 downto 0); - fault_lvl_1 : out std_logic; - lvl_i_1 : in std_logic_vector(1 downto 0); - lvl_i_1_0 : in std_logic_vector(1 to 1); - un1_m0_30 : out std_logic; - un1_m0_9 : out std_logic; - un1_m0_8 : out std_logic; - un1_m0_5 : out std_logic; - un1_m0_1 : out std_logic; - un1_m0_22 : out std_logic; - un1_m0_6 : out std_logic; - un1_m0_0 : out std_logic; - un1_m0_17 : out std_logic; - un1_m0_16 : out std_logic; - un1_m0_7 : out std_logic; - un1_m0_4 : out std_logic; - un1_m0_3 : out std_logic; - un1_m0_2 : out std_logic; - un1_itlb0_1 : out std_logic_vector(41 to 41); - un1_m0_2_0 : in std_logic_vector(35 to 35); - data_0_29 : out std_logic; - data_0_27 : out std_logic; - data_0_26 : out std_logic; - data_0_20 : out std_logic; - data_0_12 : out std_logic; - address : in std_logic_vector(31 downto 2); - data_14 : out std_logic; - data_21 : out std_logic; - data_16 : out std_logic; - data_19 : out std_logic; - data_17 : out std_logic; - data_15 : out std_logic; - data_24 : out std_logic; - data_22 : out std_logic; - data_18 : out std_logic; - data_25 : out std_logic; - data_13 : out std_logic; - data_11 : out std_logic; - data_10 : out std_logic; - data_23 : out std_logic; - data_28 : out std_logic; - fault_isid_1_i : in std_logic_vector(0 to 0); - ft_1_i_a2_0 : in std_logic_vector(0 to 0); - hrdata_0_6 : in std_logic; - hrdata_0_25 : in std_logic; - hrdata_0_20 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_9 : in std_logic; - hrdata_10 : in std_logic; - hrdata_11 : in std_logic; - hrdata_13 : in std_logic; - hrdata_14 : in std_logic; - hrdata_17 : in std_logic; - hrdata_24 : in std_logic; - hrdata_6 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_8 : in std_logic; - hrdata_12 : in std_logic; - hrdata_15 : in std_logic; - hrdata_16 : in std_logic; - hrdata_18 : in std_logic; - hrdata_21 : in std_logic; - hrdata_22 : in std_logic; - hrdata_23 : in std_logic; - hrdata_26 : in std_logic; - hrdata_27 : in std_logic; - hrdata_28 : in std_logic; - hrdata_29 : in std_logic; - hrdata_30 : in std_logic; - hrdata_31 : in std_logic; - hrdata_2 : in std_logic; - hrdata_3 : in std_logic; - hrdata_4 : in std_logic; - hrdata_7 : in std_logic; - hrdata_5 : in std_logic; - adata_11 : out std_logic; - adata_31 : out std_logic; - adata_30 : out std_logic; - adata_29 : out std_logic; - adata_28 : out std_logic; - adata_27 : out std_logic; - adata_25 : out std_logic; - adata_24 : out std_logic; - adata_23 : out std_logic; - adata_22 : out std_logic; - adata_20 : out std_logic; - adata_17 : out std_logic; - adata_16 : out std_logic; - adata_15 : out std_logic; - adata_14 : out std_logic; - adata_13 : out std_logic; - adata_12 : out std_logic; - adata_10 : out std_logic; - adata_9 : out std_logic; - adata_8 : out std_logic; - adata_7 : out std_logic; - adata_6 : out std_logic; - adata_2 : out std_logic; - adata_1 : out std_logic; - adata_0 : out std_logic; - adata_18 : out std_logic; - adata_21 : out std_logic; - adata_26 : out std_logic; - adata_4 : out std_logic; - adata_3 : out std_logic; - adata_19 : out std_logic; - s2_tlbstate_0 : out std_logic; - mmutlb_10_8_0_1_0_VCC : in std_logic; - N_264 : in std_logic; - N_262 : in std_logic; - N_78 : in std_logic; - un1_rst_i_0 : in std_logic; - N_82 : in std_logic; - N_80 : in std_logic; - su : in std_logic; - N_2625 : out std_logic; - walk_use : out std_logic; - flush_op : in std_logic; - N_2933 : out std_logic; - tlbactive : in std_logic; - N_180 : out std_logic; - walk_op_ur : out std_logic; - fault_pro_m : in std_logic; - fault_pro_1 : out std_logic; - N_2899 : out std_logic; - tlbdis : in std_logic; - inv_1_0_a2_0_a2_0 : in std_logic; - fault_mexc_2 : in std_logic; - fault_trans_i_2 : in std_logic; - N_264_0 : in std_logic; - N_78_0 : in std_logic; - N_3160 : in std_logic; - N_2571 : out std_logic; - N_262_0 : in std_logic; - fault_pri_m_0 : out std_logic; - fault_mexc_0 : in std_logic; - fault_trans_RNIA0K0D1 : out std_logic; - N_429 : out std_logic; - N_427 : out std_logic; - N_2626 : out std_logic; - N_43 : out std_logic; - N_2482 : in std_logic; - N_423 : out std_logic; - N_425 : out std_logic; - N_2623 : out std_logic; - N_2624 : out std_logic; - N_45 : out std_logic; - N_319 : out std_logic; - N_321 : out std_logic; - N_361 : out std_logic; - N_363 : out std_logic; - N_365 : out std_logic; - N_357 : out std_logic; - N_1629 : out std_logic; - fault_su : out std_logic; - twi_areq_ur_1_0_a3_i_0 : out std_logic; - fault_mexc_3_2 : in std_logic; - fault_mexc_1 : out std_logic; - rst : in std_logic; - N_359 : out std_logic; - N_2563_i : in std_logic; - s1finished_0 : out std_logic; - lclk_c : in std_logic; - N_86_i : in std_logic - ); - -end mmutlb_10_8_0_1_0; - -architecture DEF_ARCH of mmutlb_10_8_0_1_0 is - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_2 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(0 to 0) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_5 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_1 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_0 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_17 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_4 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - tlbcam_write_op_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - data_14 : in std_logic := 'U'; - data_13 : in std_logic := 'U'; - data_12 : in std_logic := 'U'; - data_11 : in std_logic := 'U'; - data_10 : in std_logic := 'U'; - data_9 : in std_logic := 'U'; - data_8 : in std_logic := 'U'; - data_7 : in std_logic := 'U'; - data_6 : in std_logic := 'U'; - data_5 : in std_logic := 'U'; - data_4 : in std_logic := 'U'; - data_3 : in std_logic := 'U'; - data_22 : in std_logic := 'U'; - data_21 : in std_logic := 'U'; - data_20 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - data_18 : in std_logic := 'U'; - data_17 : in std_logic := 'U'; - data_16 : in std_logic := 'U'; - data_15 : in std_logic := 'U'; - data_0 : in std_logic := 'U'; - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_749 : out std_logic; - N_743 : out std_logic; - N_765 : out std_logic; - s2_flush : in std_logic := 'U'; - N_764 : out std_logic; - N_596 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_763 : out std_logic; - N_762 : out std_logic; - N_761 : out std_logic; - N_760 : out std_logic; - N_759 : out std_logic; - N_758 : out std_logic; - N_757 : out std_logic; - N_756 : out std_logic; - N_755 : out std_logic; - N_754 : out std_logic; - N_753 : out std_logic; - N_752 : out std_logic; - N_751 : out std_logic; - N_750 : out std_logic; - N_748 : out std_logic; - N_747 : out std_logic; - N_746 : out std_logic; - N_745 : out std_logic; - N_744 : out std_logic; - N_742 : out std_logic; - N_741 : out std_logic; - N_740 : out std_logic; - N_739 : out std_logic; - N_738 : out std_logic; - N_736 : out std_logic; - N_735 : out std_logic; - N_734 : out std_logic; - N_733 : out std_logic; - N_732 : out std_logic; - N_634 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - SU_RNIAA5O8 : out std_logic; - hit_0_a3_0 : out std_logic; - s2_flush_0 : in std_logic := 'U'; - N_169_1 : out std_logic; - N_200 : in std_logic := 'U'; - N_32_i : out std_logic; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - hit_0_a3_2_0 : out std_logic; - N_17_i_0 : out std_logic; - N_204 : in std_logic := 'U'; - N_170_1 : out std_logic; - N_170 : out std_logic; - N_200_0 : in std_logic := 'U'; - N_42 : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_4 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0 : in std_logic_vector(7 to 7) := (others => 'U'); - tlbcam_write_op_1 : in std_logic_vector(5 to 5) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(5 to 5) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(5 to 5) := (others => 'U'); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL : out std_logic_vector(1 downto 0); - s2_entry_1_i_a2_1 : out std_logic_vector(0 to 0); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_2937_1 : in std_logic := 'U'; - cam_hit_all_1_sqmuxa : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - hit : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component mmutlbcam_0_0 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - lvl_i_1 : in std_logic_vector(0 to 0) := (others => 'U'); - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(4 to 4) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(4 to 4) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - cam_hitaddr_12 : out std_logic_vector(2 to 2); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL : out std_logic_vector(1 downto 0); - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_169_1 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - s2_flush : in std_logic := 'U'; - cam_hit_all_1_sqmuxa : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - hit_i : out std_logic; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U' - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_5 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0 : in std_logic_vector(7 to 7) := (others => 'U'); - tlbcam_write_op_1 : in std_logic_vector(1 to 1) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - s2_entry_5 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_4 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_3 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - s2_entry_1_i_a2_0 : out std_logic_vector(0 to 0); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_838 : out std_logic; - N_851 : out std_logic; - N_852 : out std_logic; - N_845 : out std_logic; - N_867 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_866 : out std_logic; - N_596 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_865 : out std_logic; - N_864 : out std_logic; - N_863 : out std_logic; - N_862 : out std_logic; - N_861 : out std_logic; - N_860 : out std_logic; - N_859 : out std_logic; - N_858 : out std_logic; - N_857 : out std_logic; - N_856 : out std_logic; - N_855 : out std_logic; - N_854 : out std_logic; - N_853 : out std_logic; - N_850 : out std_logic; - N_849 : out std_logic; - N_848 : out std_logic; - N_847 : out std_logic; - N_846 : out std_logic; - N_844 : out std_logic; - N_843 : out std_logic; - N_842 : out std_logic; - N_841 : out std_logic; - N_840 : out std_logic; - N_837 : out std_logic; - N_836 : out std_logic; - N_835 : out std_logic; - N_834 : out std_logic; - N_634 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U'; - hit_i_0 : out std_logic; - N_557 : in std_logic := 'U' - ); - end component; - - component syncramZ0 - port( aaddr : out std_logic_vector(31 downto 2); - address : in std_logic_vector(31 downto 2) := (others => 'U'); - s2_entry : in std_logic_vector(2 downto 0) := (others => 'U'); - dr1write_0_sqmuxa : in std_logic := 'U'; - syncramZ0_VCC : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component mmutlbcam_0_0_3 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(7 to 7) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(7 to 7) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(7 to 7) := (others => 'U'); - s2_entry_1_i_a2_1_2 : in std_logic_vector(1 to 1) := (others => 'U'); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL : out std_logic_vector(1 downto 0); - s2_entry_1_i_a2_0 : in std_logic_vector(0 to 0) := (others => 'U'); - s2_entry_1_i_a2_2 : out std_logic_vector(0 to 0); - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - s2_flush_0 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_2937_1 : out std_logic; - N_170_1 : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_204 : in std_logic := 'U' - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_6 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1 : in std_logic_vector(2 to 2) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(2 to 2) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 to 1) := (others => 'U'); - s2_entry_3 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_2 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_1 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL_0_d0 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_770 : out std_logic; - N_783 : out std_logic; - N_777 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_799 : out std_logic; - N_797 : out std_logic; - N_796 : out std_logic; - N_795 : out std_logic; - N_794 : out std_logic; - N_793 : out std_logic; - N_792 : out std_logic; - N_791 : out std_logic; - N_790 : out std_logic; - N_789 : out std_logic; - N_788 : out std_logic; - N_787 : out std_logic; - N_786 : out std_logic; - N_785 : out std_logic; - N_784 : out std_logic; - N_782 : out std_logic; - N_781 : out std_logic; - N_780 : out std_logic; - N_779 : out std_logic; - N_778 : out std_logic; - N_776 : out std_logic; - N_775 : out std_logic; - N_774 : out std_logic; - N_773 : out std_logic; - N_772 : out std_logic; - N_769 : out std_logic; - N_768 : out std_logic; - N_767 : out std_logic; - N_766 : out std_logic; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_2937_1 : in std_logic := 'U'; - N_557 : in std_logic := 'U'; - N_2937 : out std_logic; - hit : in std_logic := 'U'; - N_3068 : out std_logic; - N_170_1 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_204 : in std_logic := 'U' - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_7 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1 : in std_logic_vector(3 to 3) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(3 to 3) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(3 to 3) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_5 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_4 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_7 : in std_logic := 'U'; - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - ctx : in std_logic_vector(6 to 6) := (others => 'U'); - ctx_0_5 : in std_logic := 'U'; - ctx_0_4 : in std_logic := 'U'; - ctx_0_3 : in std_logic := 'U'; - ctx_0_1 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_2 : in std_logic := 'U'; - ctx_0_7 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - C_RNIL004 : out std_logic; - N_872 : out std_logic; - N_885 : out std_logic; - N_886 : out std_logic; - N_879 : out std_logic; - N_901 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_900 : out std_logic; - N_200 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_899 : out std_logic; - N_898 : out std_logic; - N_897 : out std_logic; - N_896 : out std_logic; - N_895 : out std_logic; - N_894 : out std_logic; - N_893 : out std_logic; - N_892 : out std_logic; - N_891 : out std_logic; - N_890 : out std_logic; - N_889 : out std_logic; - N_888 : out std_logic; - N_887 : out std_logic; - N_884 : out std_logic; - N_883 : out std_logic; - N_882 : out std_logic; - N_881 : out std_logic; - N_880 : out std_logic; - N_878 : out std_logic; - N_877 : out std_logic; - N_876 : out std_logic; - N_874 : out std_logic; - N_871 : out std_logic; - N_870 : out std_logic; - N_869 : out std_logic; - N_868 : out std_logic; - N_634 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - hit : out std_logic; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U' - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_1 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(6 to 6) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(6 to 6) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - s2_entry_5 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(0 to 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(6 to 6) := (others => 'U'); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL_1 : out std_logic; - s2_entry_1_i_a2_1_2 : out std_logic_vector(1 to 1); - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_798 : out std_logic; - N_632 : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - s2_flush_0 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U' - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal dr1write_0_sqmuxa_0, N_6_i_0, s2_flush_0, s2_flush_1, - un1_rst_2, \s2_entry_0[0]\, N_208, s2_entry_0_sqmuxa, - \s2_entry_1[1]\, N_212_i_0, \s2_entry_0[1]\, - \s2_entry_5[2]\, \s2_entry_1[2]\, \s2_entry_4[2]\, - \s2_entry_3[2]\, \s2_entry_2[2]\, \s2_entry_1_0[2]\, - \s2_entry_0[2]\, walk_use_1, cache_0_sqmuxa_1_1, - s2_tlbstate_3, walk_use_0, N_553, N_2355, N_572, - \s2_tlbstate[1]\, \tlbcam_write_op_1_1[4]\, - \tlbcam_write_op_1_1[0]\, \tlbcam_write_op_1_0[4]\, - \tlbcam_write_op_1_1_0[6]\, \tlbcam_write_op_1_1[6]\, - \tlbcam_write_op_1_0[6]\, \tlbcam_write_op_1_1_0[0]\, - \tlbcam_write_op_1_0[0]\, \tlbcam_write_op_1_1_0[7]\, - \tlbcam_write_op_1_1[7]\, \tlbcam_write_op_1_0[7]\, - \tlbcam_write_op_1_1_0[5]\, \tlbcam_write_op_1_1[5]\, - \tlbcam_write_op_1_0[5]\, \tlbcam_write_op_1_1[1]\, - \tlbcam_write_op_1_0[1]\, \tlbcam_write_op_1_1[2]\, - \tlbcam_write_op_1_0[2]\, \tlbcam_write_op_1_1[3]\, - dr1write_0_sqmuxa, \tlbcam_write_op_1_0[3]\, N_200_0, - \data[8]\, N_2987, N_3069, \data_1_i_0[23]\, N_2985, - N_2984, sync_isw_1_i_i_a2_0_0, \s2_tlbstate_ns_0_0_1[0]\, - \s2_tlbstate[0]\, \s2_tlbstate_ns_0_0_0[0]\, sync_isw, - N_2568, N_557, \s2_tlbstate_ns_0_0_a2_2_0[0]\, - fault_mexc_3_0, fault_mexc_1_sqmuxa_1_0_i_i_a2_0, - N_1637_i_i_0, cam_hit_all_1_4, hit_i_0, cam_hit_all_1_2, - hit_i, cam_hit_all_1_0, SU_RNIAA5O8, N_170, hit_0_a3_2_0, - N_17_i_0, N_32_i, \data_1_i_0[14]\, \data[14]\, N_2667, - \data_1_i_0[22]\, \data[22]\, N_3026, fault_pri_6_m_1, - un11_finish_li, fault_inv_m, fault_trans_m, fault_pri_6_m, - N_2593, N_2981, N_2982, N_2983, N_2995, N_2996, N_2997, - N_2992, N_2993, N_2994, N_2988, N_2989, N_2990, N_2968, - N_2969, N_2970, N_2964, N_2965, N_2966, N_2669, N_2664, - N_2665, N_2666, N_2661, N_2662, N_2663, fault_inv, - fault_mexc_m, fault_mexc, N_3017, N_3019, N_3020, N_839, - N_3016, N_3014, cam_hit_all_1, N_3068, - cam_hit_all_1_sqmuxa, N_1633, \adata[3]\, N_2492, N_206, - N_556, \fault_su\, N_2559, N_2602, N_3162, N_2604, N_2603, - N_2673, N_2675, N_2674, N_3022, N_3021, N_3024, \N_1629\, - fault_trans, N_2611, nrep_n2, \nrep[2]\, nrep_494_0, - \nrep[1]\, \nrep[0]\, N_800, N_732, N_766, N_801, N_733, - N_767, N_802, N_734, N_768, N_803, N_735, N_769, N_806, - N_738, N_772, N_807, N_739, N_773, N_808, N_740, N_774, - N_809, N_741, N_775, N_810, N_742, N_776, N_812, N_744, - N_778, N_813, N_745, N_779, N_814, N_746, N_780, N_815, - N_747, N_781, N_816, N_748, N_782, N_817, N_749, N_783, - N_818, N_750, N_784, N_819, N_751, N_785, N_820, N_752, - N_786, N_821, N_753, N_787, N_822, N_754, N_788, N_823, - N_755, N_789, N_824, N_756, N_790, N_825, N_757, N_791, - N_826, N_758, N_792, N_827, N_759, N_793, N_828, N_760, - N_794, N_829, N_761, N_795, N_830, N_762, N_796, N_831, - N_763, N_797, N_902, N_834, N_868, N_903, N_835, N_869, - N_904, N_836, N_870, N_905, N_837, N_871, N_908, N_840, - N_874, N_909, N_841, C_RNIL004, N_910, N_842, N_876, - N_911, N_843, N_877, N_912, N_844, N_878, N_914, N_846, - N_880, N_915, N_847, N_881, N_916, N_848, N_882, N_917, - N_849, N_883, N_918, N_850, N_884, N_921, N_853, N_887, - N_922, N_854, N_888, N_923, N_855, N_889, N_924, N_856, - N_890, N_925, N_857, N_891, N_926, N_858, N_892, - \s2_entry[1]\, N_927, N_859, N_893, N_928, N_860, N_894, - N_929, N_861, N_895, N_930, N_862, N_896, N_931, N_863, - N_897, N_932, N_864, N_898, N_933, N_865, N_899, N_919, - \adata[19]\, \adata[21]\, \s2_entry[0]\, \adata[26]\, - N_631_i, N_632, N_633, N_634, N_635, \data[25]\, N_639, - N_650, N_662, N_663, N_664, fault_pri_m, fault_pri, - \fault_mexc_1\, N_554, \data[12]\, \data_0[12]\, - \adata[8]\, \data[13]\, \data_0[13]\, \adata[9]\, - \data_0[14]\, \adata[10]\, \fault_lvl[0]\, N_2728, - \data[24]\, N_2730, \data[26]\, \N_2571\, N_2731, - \data[27]\, \adata[23]\, N_3064, \data_0[27]\, N_3061, - \adata[24]\, \data[28]\, \adata[22]\, \data_0[26]\, - \adata[25]\, \data[29]\, \adata[27]\, \data[31]\, N_70, - \data_0[31]\, N_2621, N_2622, N_15, N_17, \data[15]\, - N_331, \data_0[29]\, N_67, N_593, N_594, N_597, \data[4]\, - \data_0[4]\, \data[5]\, \data_0[5]\, \data[6]\, - \data_0[6]\, \data[9]\, \data_0[9]\, N_612, \data[30]\, - s2_flush, N_617, N_620, N_630, \adata[16]\, \data[20]\, - \un1_acc[33]\, N_636, \data[19]\, N_640, N_651, - \data_0[28]\, N_665, N_667, \adata[15]\, N_2890, - \data[18]\, N_687, \data[21]\, N_689, \data[23]\, N_1039, - \adata[14]\, \data_0[18]\, \data_0[19]\, \data_0[15]\, - N_595, N_14, N_2917, N_16, N_18, N_175, N_573, N_204, - \data[10]\, sync_isw_RNO, \data_1[28]\, - \tlbcam_write_op_1[4]\, \tlbcam_write_op_1[3]\, - \tlbcam_write_op_1[2]\, \tlbcam_write_op_1[1]\, - \tlbcam_write_op_1[0]\, s2_hm, \data[2]\, \data_0[2]\, - N_562, N_596, \data[17]\, \adata[12]\, \data_0[16]\, - \data[16]\, N_2727, \adata[13]\, \data_0[17]\, - \un1_acc[32]\, N_832, N_934, N_866, N_900, N_764, N_798, - \tlbcam_write_op_1[6]\, \tlbcam_write_op_1[7]\, N_6_i, - N_198, N_2577, fault_pro, \adata[4]\, \adata[2]\, nrep_n1, - nrep_n0, nrepe, \cam_hitaddr_12[2]\, N_2937, - \s2_entry_1_i_a2_2[0]\, \s2_entry_1_i_a2_1[0]\, - \nrep_RNIIGE31[0]\, N_3058, N_167, N_555, - \twi_areq_ur_1_0_a3_i_0\, \walk_op_ur\, \N_2933\, - \s2_tlbstate_nss[1]\, \s1finished_0\, s1finished, N_688, - \data_0[22]\, N_833, N_935, N_867, N_901, N_765, N_799, - \tlbcam_write_op_1[5]\, \s2_entry[2]\, \adata[11]\, N_811, - N_913, N_845, N_879, N_743, N_777, N_200, \data_0[8]\, - \data_0[20]\, \walk_use\, \data_0[24]\, \adata[20]\, - \adata[17]\, \data_0[21]\, \data_0[23]\, N_2729, - \data_1[24]\, \data_0[25]\, \data_0[30]\, \adata[18]\, - N_920, N_852, N_886, N_2554, N_851, N_885, N_804, N_906, - N_838, N_872, N_736, N_770, \data[3]\, \data_0[3]\, - \data[7]\, \data_0[7]\, \data_0[10]\, \data[11]\, - \data_0[11]\, \adata[7]\, cache, \s2_tlbstate_nss[0]\, - \s2_ctx[0]\, \s2_ctx[1]\, \s2_ctx[2]\, \s2_ctx[3]\, - \s2_ctx[4]\, \s2_ctx[5]\, \s2_ctx[6]\, \s2_ctx[7]\, - \pteout[4]\, \pteout[3]\, \pteout[2]\, \pteout[31]\, - \pteout[30]\, \pteout[29]\, \pteout[28]\, \pteout[27]\, - \pteout[26]\, \pteout[25]\, \pteout[24]\, \pteout[23]\, - \pteout[22]\, \pteout[21]\, \pteout[20]\, \pteout[19]\, - \pteout[18]\, \pteout[17]\, \pteout[16]\, \pteout[15]\, - \pteout[14]\, \pteout[13]\, \pteout[12]\, \pteout[11]\, - \pteout[10]\, \pteout[9]\, \pteout[8]\, \pteout[1]\, - \pteout[0]\, \pteout[7]\, \pteout[6]\, \LVL[0]\, \LVL[1]\, - N_169_1, N_42, N_170_1, \pteout_0[4]\, \pteout_0[3]\, - \pteout_0[2]\, \pteout_0[31]\, \pteout_0[30]\, - \pteout_0[29]\, \pteout_0[28]\, \pteout_0[27]\, - \pteout_0[26]\, \pteout_0[25]\, \pteout_0[24]\, - \pteout_0[23]\, \pteout_0[22]\, \pteout_0[21]\, - \pteout_0[20]\, \pteout_0[19]\, \pteout_0[18]\, - \pteout_0[17]\, \pteout_0[16]\, \pteout_0[15]\, - \pteout_0[14]\, \pteout_0[13]\, \pteout_0[12]\, - \pteout_0[11]\, \pteout_0[10]\, \pteout_0[9]\, - \pteout_0[8]\, \pteout_0[1]\, \pteout_0[0]\, - \pteout_0[7]\, \pteout_0[6]\, \LVL_0[0]\, \LVL_0[1]\, - \s2_entry_1_i_a2_1_2[1]\, hit_0_a3_0, \pteout_1[4]\, - \pteout_1[3]\, \pteout_1[2]\, \pteout_1[31]\, - \pteout_1[30]\, \pteout_1[29]\, \pteout_1[28]\, - \pteout_1[27]\, \pteout_1[26]\, \pteout_1[25]\, - \pteout_1[24]\, \pteout_1[23]\, \pteout_1[22]\, - \pteout_1[21]\, \pteout_1[20]\, \pteout_1[19]\, - \pteout_1[18]\, \pteout_1[17]\, \pteout_1[16]\, - \pteout_1[15]\, \pteout_1[14]\, \pteout_1[13]\, - \pteout_1[12]\, \pteout_1[11]\, \pteout_1[10]\, - \pteout_1[9]\, \pteout_1[8]\, \pteout_1[1]\, - \pteout_1[0]\, \pteout_1[7]\, \pteout_1[6]\, \LVL_1[0]\, - \LVL_1[1]\, \s2_entry_1_i_a2_0[0]\, N_2937_1, - \pteout_2[4]\, \pteout_2[3]\, \pteout_2[2]\, - \pteout_2[31]\, \pteout_2[30]\, \pteout_2[29]\, - \pteout_2[28]\, \pteout_2[27]\, \pteout_2[26]\, - \pteout_2[25]\, \pteout_2[24]\, \pteout_2[23]\, - \pteout_2[22]\, \pteout_2[21]\, \pteout_2[20]\, - \pteout_2[19]\, \pteout_2[18]\, \pteout_2[17]\, - \pteout_2[16]\, \pteout_2[15]\, \pteout_2[14]\, - \pteout_2[13]\, \pteout_2[12]\, \pteout_2[11]\, - \pteout_2[10]\, \pteout_2[9]\, \pteout_2[8]\, - \pteout_2[1]\, \pteout_2[0]\, \pteout_2[7]\, - \pteout_2[6]\, \LVL_2[0]\, \LVL_2[1]\, hit, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : mmutlbcam_0_0_2 - Use entity work.mmutlbcam_0_0_2(DEF_ARCH); - for all : mmutlbcam_0_0_4 - Use entity work.mmutlbcam_0_0_4(DEF_ARCH); - for all : mmutlbcam_0_0 - Use entity work.mmutlbcam_0_0(DEF_ARCH); - for all : mmutlbcam_0_0_5 - Use entity work.mmutlbcam_0_0_5(DEF_ARCH); - for all : syncramZ0 - Use entity work.syncramZ0(DEF_ARCH); - for all : mmutlbcam_0_0_3 - Use entity work.mmutlbcam_0_0_3(DEF_ARCH); - for all : mmutlbcam_0_0_6 - Use entity work.mmutlbcam_0_0_6(DEF_ARCH); - for all : mmutlbcam_0_0_7 - Use entity work.mmutlbcam_0_0_7(DEF_ARCH); - for all : mmutlbcam_0_0_1 - Use entity work.mmutlbcam_0_0_1(DEF_ARCH); -begin - - data_0_29 <= \data_0[31]\; - data_0_27 <= \data_0[29]\; - data_0_26 <= \data_0[28]\; - data_0_20 <= \data_0[22]\; - data_0_12 <= \data_0[14]\; - data_14 <= \data[16]\; - data_21 <= \data[23]\; - data_16 <= \data[18]\; - data_19 <= \data[21]\; - data_17 <= \data[19]\; - data_15 <= \data[17]\; - data_24 <= \data[26]\; - data_22 <= \data[24]\; - data_18 <= \data[20]\; - data_25 <= \data[27]\; - data_13 <= \data[15]\; - data_11 <= \data[13]\; - data_10 <= \data[12]\; - data_23 <= \data[25]\; - data_28 <= \data[30]\; - adata_11 <= \adata[11]\; - adata_27 <= \adata[27]\; - adata_25 <= \adata[25]\; - adata_24 <= \adata[24]\; - adata_23 <= \adata[23]\; - adata_22 <= \adata[22]\; - adata_20 <= \adata[20]\; - adata_17 <= \adata[17]\; - adata_16 <= \adata[16]\; - adata_15 <= \adata[15]\; - adata_14 <= \adata[14]\; - adata_13 <= \adata[13]\; - adata_12 <= \adata[12]\; - adata_10 <= \adata[10]\; - adata_9 <= \adata[9]\; - adata_8 <= \adata[8]\; - adata_7 <= \adata[7]\; - adata_2 <= \adata[2]\; - adata_18 <= \adata[18]\; - adata_21 <= \adata[21]\; - adata_26 <= \adata[26]\; - adata_4 <= \adata[4]\; - adata_3 <= \adata[3]\; - adata_19 <= \adata[19]\; - s2_tlbstate_0 <= \s2_tlbstate[0]\; - walk_use <= \walk_use\; - N_2933 <= \N_2933\; - walk_op_ur <= \walk_op_ur\; - N_2571 <= \N_2571\; - N_1629 <= \N_1629\; - fault_su <= \fault_su\; - twi_areq_ur_1_0_a3_i_0 <= \twi_areq_ur_1_0_a3_i_0\; - fault_mexc_1 <= \fault_mexc_1\; - s1finished_0 <= \s1finished_0\; - - \r.s2_entry_5_RNIA2ARQ2[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => \tlbcam_write_op_1[7]\); - - \r.s2_entry_0_RNI61LN1[0]\ : MX2 - port map(A => N_822, B => N_924, S => \s2_entry_0[0]\, Y - => \adata[22]\); - - \r.s2_data_RNIPDQC[13]\ : MX2C - port map(A => address(13), B => \data[13]\, S => s2_flush_0, - Y => N_632); - - \p0.transdata.data_1_i_RNO_1[23]\ : OR2A - port map(A => \walk_use\, B => \data_0[23]\, Y => N_2984); - - \r.s2_entry_RNIVAT2_0[0]\ : OR2A - port map(A => \s2_entry[1]\, B => \s2_entry[0]\, Y => - \tlbcam_write_op_1_1[6]\); - - \r.s2_data_RNISVTP[22]\ : OR3A - port map(A => \un1_acc[33]\, B => \walk_use\, C => - \data_0[22]\, Y => N_3026); - - \r.s2_tlbstate_RNO_2[0]\ : OA1A - port map(A => sync_isw, B => N_2568, C => N_557, Y => - \s2_tlbstate_ns_0_0_0[0]\); - - \r.s2_entry_RNI2PQ93[0]\ : OR2 - port map(A => \adata[24]\, B => N_3064, Y => N_2968); - - \r.s2_entry_1_RNI9L2Q[1]\ : MX2 - port map(A => N_759, B => N_793, S => \s2_entry_1[1]\, Y - => N_827); - - \r.s2_data_RNITLQC[15]\ : MX2C - port map(A => address(15), B => \data[15]\, S => s2_flush_0, - Y => N_634); - - \r.s2_hm_RNO\ : OR3C - port map(A => cam_hit_all_1_4, B => N_3068, C => - cam_hit_all_1_sqmuxa, Y => cam_hit_all_1); - - \r.s2_entry_RNINAIJ1[0]\ : MX2 - port map(A => N_827, B => N_929, S => \s2_entry[0]\, Y => - \adata[27]\); - - \r.walk_transdata.data_RNO[19]\ : MX2 - port map(A => hrdata_0_14, B => \data[19]\, S => - lvl_i_1_0(1), Y => N_636); - - \r.s2_entry_0_RNI487L1[0]\ : NOR2A - port map(A => \adata[4]\, B => \adata[2]\, Y => N_2492); - - \r.s2_data_RNI0J2E[16]\ : MX2C - port map(A => address(16), B => \data[16]\, S => s2_flush, - Y => N_595); - - \tlbcam0.0.tag0\ : mmutlbcam_0_0_2 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - hrdata_0_17 => hrdata_0_23, hrdata_0_10 => hrdata_0_16, - hrdata_0_7 => hrdata_0_13, hrdata_0_6 => hrdata_0_12, - hrdata_0_4 => hrdata_0_10, hrdata_0_3 => hrdata_0_9, - hrdata_0_2 => hrdata_0_8, hrdata_0_0 => hrdata_0_6, - tlbcam_write_op_1(0) => \tlbcam_write_op_1[0]\, - tlbcam_write_op_1_1_0(0) => \tlbcam_write_op_1_1_0[0]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 - => hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => - hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 => - hrdata_0_d0, hrdata_6 => hrdata_6, s2_entry(2) => - \s2_entry[2]\, s2_entry_5(2) => \s2_entry_5[2]\, LVL_0(1) - => \LVL[1]\, LVL_0(0) => \LVL[0]\, s2_entry_1(2) => - \s2_entry_1_0[2]\, s2_entry_0(2) => \s2_entry_0[2]\, - pteout_0_17 => \pteout[17]\, pteout_0_11 => \pteout[11]\, - pteout_0_31 => \pteout[31]\, pteout_0_30 => \pteout[30]\, - pteout_0_29 => \pteout[29]\, pteout_0_28 => \pteout[28]\, - pteout_0_27 => \pteout[27]\, pteout_0_26 => \pteout[26]\, - pteout_0_25 => \pteout[25]\, pteout_0_24 => \pteout[24]\, - pteout_0_23 => \pteout[23]\, pteout_0_22 => \pteout[22]\, - pteout_0_21 => \pteout[21]\, pteout_0_20 => \pteout[20]\, - pteout_0_19 => \pteout[19]\, pteout_0_18 => \pteout[18]\, - pteout_0_16 => \pteout[16]\, pteout_0_15 => \pteout[15]\, - pteout_0_14 => \pteout[14]\, pteout_0_13 => \pteout[13]\, - pteout_0_12 => \pteout[12]\, pteout_0_10 => \pteout[10]\, - pteout_0_9 => \pteout[9]\, pteout_0_8 => \pteout[8]\, - pteout_0_7 => \pteout[7]\, pteout_0_6 => \pteout[6]\, - pteout_0_4 => \pteout[4]\, pteout_0_3 => \pteout[3]\, - pteout_0_2 => \pteout[2]\, pteout_0_1 => \pteout[1]\, - pteout_0_0 => \pteout[0]\, tlbcam_write_op_1_0(0) => - \tlbcam_write_op_1_0[0]\, data_14 => \data[23]\, data_13 - => \data_0[22]\, data_12 => \data[21]\, data_11 => - \data[20]\, data_10 => \data[19]\, data_9 => \data[18]\, - data_8 => \data[17]\, data_7 => \data[16]\, data_6 => - \data[15]\, data_5 => \data_0[14]\, data_4 => \data[13]\, - data_3 => \data[12]\, data_22 => \data_0[31]\, data_21 - => \data[30]\, data_20 => \data_0[29]\, data_19 => - \data_0[28]\, data_18 => \data[27]\, data_17 => - \data[26]\, data_16 => \data[25]\, data_15 => \data[24]\, - data_0 => \data[9]\, ctx_0(7) => ctx_0(7), ctx_0(6) => - ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), - ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => - ctx_0(1), ctx_0(0) => ctx_0(0), N_78_0 => N_78_0, N_262_0 - => N_262_0, N_264_0 => N_264_0, N_2482 => N_2482, lclk_c - => lclk_c, N_749 => N_749, N_743 => N_743, N_765 => - N_765, s2_flush => s2_flush, N_764 => N_764, N_596 => - N_596, un1_rst_i_0 => un1_rst_i_0, N_620 => N_620, N_594 - => N_594, N_593 => N_593, N_597 => N_597, N_665 => N_665, - N_763 => N_763, N_762 => N_762, N_761 => N_761, N_760 => - N_760, N_759 => N_759, N_758 => N_758, N_757 => N_757, - N_756 => N_756, N_755 => N_755, N_754 => N_754, N_753 => - N_753, N_752 => N_752, N_751 => N_751, N_750 => N_750, - N_748 => N_748, N_747 => N_747, N_746 => N_746, N_745 => - N_745, N_744 => N_744, N_742 => N_742, N_741 => N_741, - N_740 => N_740, N_739 => N_739, N_738 => N_738, N_736 => - N_736, N_735 => N_735, N_734 => N_734, N_733 => N_733, - N_732 => N_732, N_634 => N_634, N_632 => N_632, N_639 => - N_639, N_635 => N_635, SU_RNIAA5O8 => SU_RNIAA5O8, - hit_0_a3_0 => hit_0_a3_0, s2_flush_0 => s2_flush_0, - N_169_1 => N_169_1, N_200 => N_200, N_32_i => N_32_i, - N_631_i => N_631_i, N_633 => N_633, N_595 => N_595, N_663 - => N_663, N_664 => N_664, N_651 => N_651, N_612 => N_612, - N_617 => N_617, N_650 => N_650, N_662 => N_662, - hit_0_a3_2_0 => hit_0_a3_2_0, N_17_i_0 => N_17_i_0, N_204 - => N_204, N_170_1 => N_170_1, N_170 => N_170, N_200_0 - => N_200_0, N_42 => N_42); - - \r.sync_isw_RNO_1\ : OR3C - port map(A => N_2568, B => sync_isw, C => rst, Y => N_2593); - - \r.walk_fault.fault_mexc_RNIEUV75\ : AO1B - port map(A => un1_m0_2_0(35), B => fault_mexc_0, C => - fault_mexc_m, Y => \fault_mexc_1\); - - \r.s2_entry_1_RNIPCPE[1]\ : MX2 - port map(A => N_837, B => N_871, S => \s2_entry_1[1]\, Y - => N_905); - - \r.s2_entry_0_RNIIKVP[1]\ : MX2 - port map(A => N_754, B => N_788, S => \s2_entry_0[1]\, Y - => N_822); - - \r.s2_entry_0_RNIRH7RQ2_2[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => - \tlbcam_write_op_1_1[4]\); - - \r.s2_entry_RNI4QFJ1[0]\ : MX2 - port map(A => N_825, B => N_927, S => \s2_entry[0]\, Y => - \adata[25]\); - - \r.s2_entry_0_RNI8G211[0]\ : MX2 - port map(A => N_803, B => N_905, S => \s2_entry_0[0]\, Y - => \adata[3]\); - - \r.s2_su_RNI2GTB1\ : NOR3 - port map(A => walk_use_0, B => \fault_su\, C => - un11_finish_li, Y => fault_pri_6_m_1); - - \r.s2_entry_RNI7HTN[1]\ : MX2 - port map(A => N_864, B => N_898, S => \s2_entry[1]\, Y => - N_932); - - \r.s2_entry_5_RNIA2ARQ2_2[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => \tlbcam_write_op_1[3]\); - - \r.s2_entry_1_RNI452Q[1]\ : MX2 - port map(A => N_855, B => N_889, S => \s2_entry_1[1]\, Y - => N_923); - - \r.s2_entry_RNIUD3PQ2[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => \s2_entry[2]\, C => - \tlbcam_write_op_1_1[5]\, Y => \tlbcam_write_op_1[5]\); - - \r.nrep[0]\ : DFN1E1 - port map(D => nrep_n0, CLK => lclk_c, E => nrepe, Q => - \nrep[0]\); - - \r.walk_transdata.data[20]\ : DFN1E0 - port map(D => N_640, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[20]\); - - \r.s2_entry_0_RNIR4O21[0]\ : MX2 - port map(A => N_812, B => N_914, S => \s2_entry_0[0]\, Y - => \adata[12]\); - - \r.s2_data[13]\ : DFN1E1 - port map(D => address(13), CLK => lclk_c, E => - \s1finished_0\, Q => \data[13]\); - - \r.s2_data_RNI3UQC[26]\ : MX2C - port map(A => address(26), B => \data[26]\, S => s2_flush_0, - Y => N_664); - - \r.walk_fault.fault_trans_RNO\ : NOR2 - port map(A => fault_trans_i_2, B => N_2917, Y => N_14); - - \r.s2_entry_RNIVAT2_1[0]\ : OR2A - port map(A => \s2_entry[0]\, B => \s2_entry[1]\, Y => - \tlbcam_write_op_1_1[5]\); - - \r.s2_entry_0_RNI34O21[0]\ : MX2 - port map(A => N_809, B => N_911, S => \s2_entry_0[0]\, Y - => \adata[9]\); - - \r.s2_entry_0_RNIF4SF[1]\ : MX2 - port map(A => N_739, B => N_773, S => \s2_entry_0[1]\, Y - => N_807); - - \r.walk_transdata.cache_RNIUFP81\ : MX2 - port map(A => \adata[7]\, B => cache, S => \walk_use\, Y - => un1_m0_30); - - \r.s2_entry_0_RNIUDHF[1]\ : MX2 - port map(A => N_740, B => N_774, S => \s2_entry_0[1]\, Y - => N_808); - - \r.walk_fault.fault_mexc_RNO_1\ : OR2A - port map(A => \s2_tlbstate[0]\, B => sync_isw, Y => - fault_mexc_1_sqmuxa_1_0_i_i_a2_0); - - \r.s2_data[17]\ : DFN1E1 - port map(D => address(17), CLK => lclk_c, E => - \s1finished_0\, Q => \data[17]\); - - \r.walk_fault.fault_pri_RNIGT9E\ : NOR2B - port map(A => walk_use_0, B => fault_pri, Y => fault_pri_m); - - \r.s2_data[22]\ : DFN1E1 - port map(D => address(22), CLK => lclk_c, E => s1finished, - Q => \data_0[22]\); - - \r.s2_ctx[1]\ : DFN1E1 - port map(D => ctx(1), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[1]\); - - \r.s2_entry[0]\ : DFN1E1 - port map(D => N_208, CLK => lclk_c, E => s2_entry_0_sqmuxa, - Q => \s2_entry[0]\); - - \r.s2_data_RNIP9QC[21]\ : MX2C - port map(A => address(21), B => \data[21]\, S => s2_flush_0, - Y => N_594); - - \r.s2_entry_RNI6OF9[1]\ : MX2 - port map(A => N_867, B => N_901, S => \s2_entry[1]\, Y => - N_935); - - \r.s2_entry_0_RNIMEHF[1]\ : MX2 - port map(A => N_746, B => N_780, S => \s2_entry_0[1]\, Y - => N_814); - - \r.s2_data_RNITDQC[31]\ : MX2C - port map(A => address(31), B => \data_0[31]\, S => - s2_flush_0, Y => N_597); - - \r.s2_hm_RNO_2\ : AOI1B - port map(A => hit_0_a3_2_0, B => N_17_i_0, C => N_32_i, Y - => cam_hit_all_1_0); - - \r.s2_tlbstate_RNO_0[1]\ : AOI1 - port map(A => s2_flush, B => N_555, C => \s2_tlbstate[0]\, - Y => N_167); - - \r.s2_entry_0_RNIAKUP[1]\ : MX2 - port map(A => N_752, B => N_786, S => \s2_entry_0[1]\, Y - => N_820); - - \r.walk_use_1\ : DFN1E1 - port map(D => cache_0_sqmuxa_1_1, CLK => lclk_c, E => - s2_tlbstate_3, Q => walk_use_1); - - \r.s2_entry_0_RNIRH7RQ2_4[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => - \tlbcam_write_op_1_0[5]\); - - \r.walk_use_0_RNI6O2T2\ : OR3 - port map(A => N_554, B => walk_use_0, C => \adata[9]\, Y - => N_2666); - - \r.s2_tlbstate_RNI1PHJN[1]\ : OR3B - port map(A => \s2_tlbstate[0]\, B => N_2563_i, C => - \s2_tlbstate[1]\, Y => N_6_i); - - \r.s2_tlbstate_RNI3O7FO[1]\ : OR2B - port map(A => N_556, B => N_6_i_0, Y => N_573); - - \r.s2_entry_0_RNINS711[0]\ : MX2 - port map(A => N_807, B => N_909, S => \s2_entry_0[0]\, Y - => \adata[7]\); - - \r.nrep_RNO_0[2]\ : OR2B - port map(A => \nrep[1]\, B => \nrep[0]\, Y => nrep_494_0); - - \r.s2_entry_0_RNIRH7RQ2_12[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => - \tlbcam_write_op_1_0[1]\); - - \r.s2_data_RNI56RC[19]\ : MX2C - port map(A => address(19), B => \data[19]\, S => s2_flush_0, - Y => N_593); - - \r.walk_fault.fault_trans\ : DFN1E1 - port map(D => N_14, CLK => lclk_c, E => N_573, Q => - fault_trans); - - \r.s2_entry_0_RNIB5O21[0]\ : MX2 - port map(A => N_814, B => N_916, S => \s2_entry_0[0]\, Y - => \adata[14]\); - - \r.s2_ctx[0]\ : DFN1E1 - port map(D => ctx(0), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[0]\); - - \r.walk_transdata.data_RNO[18]\ : MX2 - port map(A => hrdata_0_13, B => \data[18]\, S => - lvl_i_1_0(1), Y => N_2890); - - \r.s2_entry_0_RNIRH7RQ2[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_1_0[7]\); - - \r.s2_flush\ : DFN1E1 - port map(D => s2_flush_1, CLK => lclk_c, E => un1_rst_2, Q - => s2_flush); - - \r.s2_data_RNIPQP8[10]\ : OR2B - port map(A => \data[10]\, B => s2_flush, Y => N_204); - - \r.s2_entry_RNI7OLJ[0]\ : MX2 - port map(A => N_811, B => N_913, S => \s2_entry[0]\, Y => - \adata[11]\); - - \r.walk_transdata.data_RNIEQQ9[7]\ : MX2C - port map(A => \data[7]\, B => \data_0[7]\, S => \walk_use\, - Y => un1_m0_5); - - \r.walk_fault.fault_pro_RNO\ : OA1C - port map(A => hrdata_0_3, B => hrdata_0_1, C => - N_1637_i_i_0, Y => N_2559); - - \r.s2_entry_1_RNID6VF[1]\ : MX2 - port map(A => N_840, B => N_874, S => \s2_entry_1[1]\, Y - => N_908); - - \r.s2_entry_RNIV11O[1]\ : MX2 - port map(A => N_861, B => N_895, S => \s2_entry[1]\, Y => - N_929); - - \r.walk_use_0_RNIUN2T2\ : OR3 - port map(A => N_554, B => walk_use_0, C => \adata[8]\, Y - => N_2663); - - \r.sync_isw_RNI1N17\ : NOR2A - port map(A => fault_mexc_2, B => sync_isw, Y => N_3058); - - \r.s2_entry_1_RNI1VJF[1]\ : MX2 - port map(A => N_846, B => N_880, S => \s2_entry_1[1]\, Y - => N_914); - - \r.s2_entry_5_RNIA2ARQ2_0[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => \tlbcam_write_op_1[6]\); - - \r.walk_fault.fault_lvl[0]\ : DFN1E0 - port map(D => N_80, CLK => lclk_c, E => N_6_i_0, Q => - \fault_lvl[0]\); - - \r.s2_tlbstate_RNILJJC[1]\ : OR2B - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => N_2568); - - \r.s2_tlbstate_RNIRHMJ[1]\ : NOR2B - port map(A => tlbactive, B => \N_2933\, Y => N_572); - - \r.s2_data[25]\ : DFN1E1 - port map(D => address(25), CLK => lclk_c, E => s1finished, - Q => \data[25]\); - - \r.walk_transdata.data[10]\ : DFN1E0 - port map(D => \data[10]\, CLK => lclk_c, E => N_6_i_0, Q - => \data_0[10]\); - - \r.s2_entry_RNIEI39[1]\ : MX2 - port map(A => N_845, B => N_879, S => \s2_entry[1]\, Y => - N_913); - - \r.walk_use_0_RNI1LUH3\ : OR3A - port map(A => N_3162, B => \adata[21]\, C => walk_use_0, Y - => N_2673); - - \r.walk_transdata.data_RNIL84D[17]\ : OR2A - port map(A => walk_use_1, B => \data_0[17]\, Y => N_3019); - - \r.s2_entry_0_RNIRH7RQ2_14[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => - \tlbcam_write_op_1_0[0]\); - - \r.s2_data[31]\ : DFN1E1 - port map(D => address(31), CLK => lclk_c, E => s1finished, - Q => \data_0[31]\); - - \r.s2_entry_0_RNIOB1H1[0]\ : OR2 - port map(A => \adata[17]\, B => N_3069, Y => N_3024); - - \r.walk_transdata.data[24]\ : DFN1E0 - port map(D => N_2728, CLK => lclk_c, E => N_6_i, Q => - \data_1[24]\); - - \r.s2_data_RNIFNC55[16]\ : OR3C - port map(A => N_839, B => N_3016, C => N_3014, Y => N_423); - - \r.s2_data_RNIQI6E5[28]\ : OR3C - port map(A => N_2968, B => N_2969, C => N_2970, Y => N_321); - - \r.walk_transdata.data_RNIAFPD[6]\ : MX2C - port map(A => \data[6]\, B => \data_0[6]\, S => walk_use_1, - Y => un1_m0_4); - - \r.s2_hm_RNIQOF91_0\ : OAI1 - port map(A => N_553, B => N_2355, C => N_572, Y => - \s1finished_0\); - - \r.walk_use_0_RNIFERD3\ : OR3A - port map(A => N_3162, B => \adata[26]\, C => walk_use_0, Y - => N_2602); - - \r.walk_transdata.cache\ : DFN1E0 - port map(D => hrdata_7, CLK => lclk_c, E => N_6_i_0, Q => - cache); - - \r.s2_data[12]\ : DFN1E1 - port map(D => address(12), CLK => lclk_c, E => - \s1finished_0\, Q => \data[12]\); - - \p0.tlb_mergedata.v.walk_transdata.data_3_i_o2_0_o2[30]\ : - OR2B - port map(A => lvl_i_1_0(1), B => lvl_i_1(0), Y => \N_2571\); - - \r.walk_fault.fault_inv\ : DFN1E1 - port map(D => N_18, CLK => lclk_c, E => N_573, Q => - fault_inv); - - \r.s2_data_RNIVLQC[24]\ : MX2C - port map(A => address(24), B => \data[24]\, S => s2_flush_0, - Y => N_663); - - \r.s2_entry_0_RNIM0JN1[0]\ : MX2 - port map(A => N_820, B => N_922, S => \s2_entry_0[0]\, Y - => \adata[20]\); - - \r.nrep[2]\ : DFN1E1 - port map(D => nrep_n2, CLK => lclk_c, E => nrepe, Q => - \nrep[2]\); - - \r.walk_transdata.data_RNIJ04D[15]\ : OR2A - port map(A => walk_use_1, B => \data_0[15]\, Y => N_2982); - - \r.s2_tlbstate_RNIMALJ[1]\ : OA1A - port map(A => \s2_tlbstate[1]\, B => N_3058, C => - \s2_tlbstate[0]\, Y => cache_0_sqmuxa_1_1); - - \r.s2_entry_0_RNIH1UN[0]\ : MX2 - port map(A => N_817, B => N_919, S => \s2_entry_0[0]\, Y - => \adata[17]\); - - \r.s2_data_RNIRHQC[14]\ : MX2C - port map(A => address(14), B => \data_0[14]\, S => - s2_flush_0, Y => N_633); - - \r.walk_transdata.data_RNO[25]\ : MX2 - port map(A => \data[25]\, B => hrdata_0_20, S => \N_2571\, - Y => N_2729); - - \r.walk_transdata.data_RNIGQQ9[8]\ : MX2C - port map(A => \data[8]\, B => \data_0[8]\, S => \walk_use\, - Y => un1_m0_6); - - \r.walk_transdata.data[31]\ : DFN1E0 - port map(D => N_70, CLK => lclk_c, E => N_6_i, Q => - \data[31]\); - - \r.s2_data[3]\ : DFN1E1 - port map(D => address(3), CLK => lclk_c, E => s1finished, Q - => \data[3]\); - - \r.walk_transdata.data_RNIGO3D[13]\ : OR2A - port map(A => walk_use_0, B => \data_0[13]\, Y => N_2665); - - \r.s2_hm_RNI4UIE\ : NOR2A - port map(A => tlbactive, B => N_2355, Y => N_562); - - \r.s2_entry_RNIVAT2[0]\ : OR2B - port map(A => \s2_entry[1]\, B => \s2_entry[0]\, Y => - \tlbcam_write_op_1_1[7]\); - - \r.s2_ctx[4]\ : DFN1E1 - port map(D => ctx(4), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[4]\); - - \r.s2_tlbstate_RNI179E[0]\ : OR2 - port map(A => \s2_tlbstate[0]\, B => s2_flush, Y => N_553); - - GND_i : GND - port map(Y => \GND\); - - \r.s2_entry_5_RNIA2ARQ2_5[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => \tlbcam_write_op_1[0]\); - - \r.s2_entry_0_RNIN5SF[1]\ : MX2 - port map(A => N_738, B => N_772, S => \s2_entry_0[1]\, Y - => N_806); - - \r.s2_data_RNI534K2[21]\ : OR3C - port map(A => N_3022, B => N_3021, C => N_3024, Y => N_427); - - \r.s2_ctx[6]\ : DFN1E1 - port map(D => ctx(6), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[6]\); - - \tlbcam0.5.tag0\ : mmutlbcam_0_0_4 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0(7) => - hrdata_0_6, tlbcam_write_op_1(5) => - \tlbcam_write_op_1[5]\, tlbcam_write_op_1_1_0(5) => - \tlbcam_write_op_1_1_0[5]\, hrdata_4 => hrdata_4, - hrdata_3 => hrdata_3, hrdata_2 => hrdata_2, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0_d0 => hrdata_0_d0, hrdata_6 => hrdata_6, - pteout_4 => \pteout_2[4]\, pteout_3 => \pteout_2[3]\, - pteout_2 => \pteout_2[2]\, pteout_31 => \pteout_2[31]\, - pteout_30 => \pteout_2[30]\, pteout_29 => \pteout_2[29]\, - pteout_28 => \pteout_2[28]\, pteout_27 => \pteout_2[27]\, - pteout_26 => \pteout_2[26]\, pteout_25 => \pteout_2[25]\, - pteout_24 => \pteout_2[24]\, pteout_23 => \pteout_2[23]\, - pteout_22 => \pteout_2[22]\, pteout_21 => \pteout_2[21]\, - pteout_20 => \pteout_2[20]\, pteout_19 => \pteout_2[19]\, - pteout_18 => \pteout_2[18]\, pteout_17 => \pteout_2[17]\, - pteout_16 => \pteout_2[16]\, pteout_15 => \pteout_2[15]\, - pteout_14 => \pteout_2[14]\, pteout_13 => \pteout_2[13]\, - pteout_12 => \pteout_2[12]\, pteout_11 => \pteout_2[11]\, - pteout_10 => \pteout_2[10]\, pteout_9 => \pteout_2[9]\, - pteout_8 => \pteout_2[8]\, pteout_1 => \pteout_2[1]\, - pteout_0 => \pteout_2[0]\, pteout_7 => \pteout_2[7]\, - pteout_6 => \pteout_2[6]\, tlbcam_write_op_1_0(5) => - \tlbcam_write_op_1_0[5]\, ctx_0(7) => ctx_0(7), ctx_0(6) - => ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), - ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => - ctx_0(1), ctx_0(0) => ctx_0(0), LVL(1) => \LVL_2[1]\, - LVL(0) => \LVL_2[0]\, s2_entry_1_i_a2_1(0) => - \s2_entry_1_i_a2_1[0]\, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => N_2482, lclk_c => lclk_c, - N_2937_1 => N_2937_1, cam_hit_all_1_sqmuxa => - cam_hit_all_1_sqmuxa, s2_flush => s2_flush, un1_rst_i_0 - => un1_rst_i_0, N_42 => N_42, N_635 => N_635, N_639 => - N_639, N_632 => N_632, N_634 => N_634, N_594 => N_594, - N_596 => N_596, N_620 => N_620, N_593 => N_593, N_597 => - N_597, N_665 => N_665, hit_0_a3_0 => hit_0_a3_0, N_200 - => N_200, N_170_1 => N_170_1, N_663 => N_663, N_664 => - N_664, N_651 => N_651, N_612 => N_612, N_631_i => N_631_i, - N_633 => N_633, N_595 => N_595, N_200_0 => N_200_0, N_617 - => N_617, N_650 => N_650, N_662 => N_662, N_204 => N_204, - hit => hit); - - \r.s2_entry_RNIRH0O[1]\ : MX2 - port map(A => N_860, B => N_894, S => \s2_entry[1]\, Y => - N_928); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.s2_entry_0_RNIRH7RQ2_6[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => - \tlbcam_write_op_1_0[4]\); - - \r.walk_transdata.data_RNIAU0F3[22]\ : OAI1 - port map(A => N_3069, B => \adata[18]\, C => - \data_1_i_0[22]\, Y => N_429); - - \r.s2_entry_0_RNI64UP[1]\ : MX2 - port map(A => N_751, B => N_785, S => \s2_entry_0[1]\, Y - => N_819); - - \r.s2_tlbstate_RNILJJC_0[1]\ : OR2A - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => \N_2933\); - - \r.s2_data[26]\ : DFN1E1 - port map(D => address(26), CLK => lclk_c, E => s1finished, - Q => \data[26]\); - - \tlbcam0.4.tag0\ : mmutlbcam_0_0 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1_0(1) => - lvl_i_1_0(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0_17 => - hrdata_0_23, hrdata_0_10 => hrdata_0_16, hrdata_0_7 => - hrdata_0_13, hrdata_0_6 => hrdata_0_12, hrdata_0_4 => - hrdata_0_10, hrdata_0_3 => hrdata_0_9, hrdata_0_2 => - hrdata_0_8, hrdata_0_0 => hrdata_0_6, - tlbcam_write_op_1(4) => \tlbcam_write_op_1[4]\, - tlbcam_write_op_1_1(4) => \tlbcam_write_op_1_1[4]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 - => hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => - hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 => - hrdata_0_d0, hrdata_6 => hrdata_6, pteout_4 => - \pteout[4]\, pteout_3 => \pteout[3]\, pteout_2 => - \pteout[2]\, pteout_31 => \pteout[31]\, pteout_30 => - \pteout[30]\, pteout_29 => \pteout[29]\, pteout_28 => - \pteout[28]\, pteout_27 => \pteout[27]\, pteout_26 => - \pteout[26]\, pteout_25 => \pteout[25]\, pteout_24 => - \pteout[24]\, pteout_23 => \pteout[23]\, pteout_22 => - \pteout[22]\, pteout_21 => \pteout[21]\, pteout_20 => - \pteout[20]\, pteout_19 => \pteout[19]\, pteout_18 => - \pteout[18]\, pteout_17 => \pteout[17]\, pteout_16 => - \pteout[16]\, pteout_15 => \pteout[15]\, pteout_14 => - \pteout[14]\, pteout_13 => \pteout[13]\, pteout_12 => - \pteout[12]\, pteout_11 => \pteout[11]\, pteout_10 => - \pteout[10]\, pteout_9 => \pteout[9]\, pteout_8 => - \pteout[8]\, pteout_1 => \pteout[1]\, pteout_0 => - \pteout[0]\, pteout_7 => \pteout[7]\, pteout_6 => - \pteout[6]\, tlbcam_write_op_1_0(4) => - \tlbcam_write_op_1_0[4]\, cam_hitaddr_12(2) => - \cam_hitaddr_12[2]\, ctx_0(7) => ctx_0(7), ctx_0(6) => - ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), - ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => - ctx_0(1), ctx_0(0) => ctx_0(0), LVL(1) => \LVL[1]\, - LVL(0) => \LVL[0]\, N_78_0 => N_78_0, N_262_0 => N_262_0, - N_264_0 => N_264_0, N_2482 => N_2482, lclk_c => lclk_c, - N_634 => N_634, N_594 => N_594, N_596 => N_596, N_169_1 - => N_169_1, un1_rst_i_0 => un1_rst_i_0, s2_flush => - s2_flush, cam_hit_all_1_sqmuxa => cam_hit_all_1_sqmuxa, - N_635 => N_635, N_639 => N_639, N_665 => N_665, N_597 => - N_597, N_620 => N_620, N_593 => N_593, N_632 => N_632, - N_204 => N_204, N_200 => N_200, N_42 => N_42, hit_i => - hit_i, N_663 => N_663, N_664 => N_664, N_651 => N_651, - N_612 => N_612, N_631_i => N_631_i, N_633 => N_633, N_595 - => N_595, N_200_0 => N_200_0, N_617 => N_617, N_650 => - N_650, N_662 => N_662, N_170_1 => N_170_1); - - \r.s2_entry_RNI4O4K[0]\ : MX2 - port map(A => N_804, B => N_906, S => \s2_entry[0]\, Y => - \adata[4]\); - - \r.s2_entry_0_RNIRH7RQ2_13[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => - \tlbcam_write_op_1_0[2]\); - - \r.walk_transdata.data_RNIHG3D[31]\ : OR2A - port map(A => walk_use_1, B => \data[31]\, Y => N_2996); - - \r.s2_entry_0_RNIRH7RQ2_8[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => - \tlbcam_write_op_1_1[1]\); - - \r.walk_transdata.data_RNICK171[22]\ : OA1A - port map(A => walk_use_0, B => \data[22]\, C => N_3026, Y - => \data_1_i_0[22]\); - - \r.walk_transdata.data[23]\ : DFN1E0 - port map(D => N_689, CLK => lclk_c, E => N_6_i, Q => - \data_0[23]\); - - \r.walk_transdata.data_RNIK44D[16]\ : OR2A - port map(A => walk_use_1, B => \data_0[16]\, Y => N_3016); - - \r.s2_data[15]\ : DFN1E1 - port map(D => address(15), CLK => lclk_c, E => - \s1finished_0\, Q => \data[15]\); - - \r.walk_transdata.data_RNIGFPD[9]\ : MX2C - port map(A => \data[9]\, B => \data_0[9]\, S => walk_use_1, - Y => un1_m0_7); - - \r.s2_entry_RNIQO9J1[0]\ : MX2 - port map(A => N_828, B => N_930, S => \s2_entry[0]\, Y => - adata_28); - - \r.walk_transdata.data[14]\ : DFN1E0 - port map(D => N_15, CLK => lclk_c, E => N_6_i_0, Q => - \data[14]\); - - \r.nrep_RNIIGE31[0]\ : NOR2 - port map(A => \nrep[0]\, B => N_557, Y => - \nrep_RNIIGE31[0]\); - - \r.s2_data_RNIA33E[29]\ : MX2C - port map(A => address(29), B => \data_0[29]\, S => s2_flush, - Y => N_665); - - \p0.transdata.data_1_i_a2_1[23]\ : OR2 - port map(A => N_3069, B => \adata[19]\, Y => N_2987); - - \r.nrep_RNIF78IV4[0]\ : AOI1 - port map(A => \s2_entry_1_i_a2_2[0]\, B => - \s2_entry_1_i_a2_1[0]\, C => \nrep_RNIIGE31[0]\, Y => - N_208); - - \r.s2_entry_1_RNIHVJF[1]\ : MX2 - port map(A => N_850, B => N_884, S => \s2_entry_1[1]\, Y - => N_918); - - \r.s2_tlbstate_RNO[1]\ : NOR3A - port map(A => rst, B => N_167, C => \walk_op_ur\, Y => - \s2_tlbstate_nss[1]\); - - \r.s2_data[28]\ : DFN1E1 - port map(D => address(28), CLK => lclk_c, E => s1finished, - Q => \data_0[28]\); - - \p0.transdata.data_1_i_RNO_0[23]\ : OR3A - port map(A => \un1_acc[33]\, B => \walk_use\, C => - \data[23]\, Y => N_2985); - - \r.walk_transdata.data[21]\ : DFN1E0 - port map(D => N_687, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[21]\); - - \r.s2_entry_1_RNIG4VP[1]\ : MX2 - port map(A => N_761, B => N_795, S => \s2_entry_1[1]\, Y - => N_829); - - \r.s2_data_RNIRG6N1[31]\ : OR2A - port map(A => N_3061, B => \data_0[31]\, Y => N_2997); - - \r.walk_use_1_RNIVO2T2\ : OR3 - port map(A => N_554, B => walk_use_1, C => \adata[12]\, Y - => N_839); - - \r.s2_entry_1_RNIDVJF[1]\ : MX2 - port map(A => N_849, B => N_883, S => \s2_entry_1[1]\, Y - => N_917); - - \r.s2_entry_0_RNIO4FM1[0]\ : MX2 - port map(A => N_801, B => N_903, S => \s2_entry_0[0]\, Y - => adata_1); - - \r.walk_use_RNI6VBM1\ : OR2A - port map(A => N_3162, B => \walk_use\, Y => N_3064); - - \r.walk_fault.fault_pro_RNO_0\ : OR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => hrdata_0_2, Y => N_1637_i_i_0); - - \r.walk_transdata.data_RNIIR49[21]\ : OR2A - port map(A => \walk_use\, B => \data_0[21]\, Y => N_3021); - - \r.s2_entry_1_RNIT6FP[1]\ : MX2 - port map(A => N_834, B => N_868, S => \s2_entry_1[1]\, Y - => N_902); - - \r.s2_data_RNIV47N1[26]\ : OR2A - port map(A => N_3061, B => \data[26]\, Y => N_2990); - - \r.s2_entry_0_RNIRH7RQ2_11[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_0[3]\); - - \r.walk_transdata.data_RNO[29]\ : MX2 - port map(A => \data_0[29]\, B => N_78_0, S => \N_2571\, Y - => N_331); - - \r.s2_entry[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry[2]\); - - \r.walk_transdata.data_RNIFK3D[12]\ : OR2A - port map(A => walk_use_0, B => \data_0[12]\, Y => N_2662); - - \r.walk_transdata.data_RNIONB72[18]\ : MX2C - port map(A => N_1039, B => \data_0[18]\, S => walk_use_1, Y - => un1_m0_16); - - \r.s2_data[6]\ : DFN1E1 - port map(D => address(6), CLK => lclk_c, E => s1finished, Q - => \data[6]\); - - \r.s2_hm_RNI0V531\ : OR2A - port map(A => N_2355, B => N_556, Y => N_557); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.s2_data_RNI2B7Q1[18]\ : MX2 - port map(A => \adata[14]\, B => \data[18]\, S => - \un1_acc[33]\, Y => N_1039); - - \r.walk_transdata.data[7]\ : DFN1E0 - port map(D => \data[7]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[7]\); - - \r.s2_tlbstate_RNI0V531[1]\ : AO1D - port map(A => \s2_tlbstate[1]\, B => N_562, C => N_553, Y - => un11_finish_li); - - \r.s2_data_RNIIM9M5[25]\ : OR3C - port map(A => N_2673, B => N_2674, C => N_2675, Y => N_2626); - - \r.s2_entry_0_RNIBMCP[1]\ : MX2 - port map(A => N_733, B => N_767, S => \s2_entry_0[1]\, Y - => N_801); - - \r.s2_tlbstate_RNO[0]\ : AOI1B - port map(A => \s2_tlbstate_ns_0_0_1[0]\, B => N_2611, C => - rst, Y => \s2_tlbstate_nss[0]\); - - \r.s2_entry_RNI2PAJ1[0]\ : MX2 - port map(A => N_829, B => N_931, S => \s2_entry[0]\, Y => - adata_29); - - \r.walk_use_1_RNIBC0E2\ : OR3 - port map(A => N_554, B => walk_use_1, C => \adata[11]\, Y - => N_2983); - - \r.s2_hm_RNIQOF91\ : OAI1 - port map(A => N_553, B => N_2355, C => N_572, Y => - s1finished); - - \r.s2_entry_RNIM0TD[1]\ : MX2 - port map(A => N_764, B => N_798, S => \s2_entry[1]\, Y => - N_832); - - \r.s2_data[16]\ : DFN1E1 - port map(D => address(16), CLK => lclk_c, E => - \s1finished_0\, Q => \data[16]\); - - \r.walk_transdata.data_RNI6FPD[4]\ : MX2C - port map(A => \data[4]\, B => \data_0[4]\, S => walk_use_1, - Y => un1_m0_2); - - \r.walk_fault.fault_mexc_RNI66TQ31\ : NOR2 - port map(A => \fault_mexc_1\, B => fault_mexc_3_2, Y => - fault_mexc_3_0); - - \r.s2_entry_1_RNIFL3Q[1]\ : MX2 - port map(A => N_857, B => N_891, S => \s2_entry_1[1]\, Y - => N_925); - - \r.s2_entry_0_RNIB4O21[0]\ : MX2 - port map(A => N_810, B => N_912, S => \s2_entry_0[0]\, Y - => \adata[10]\); - - \r.walk_fault.fault_pro\ : DFN1E1 - port map(D => N_2559, CLK => lclk_c, E => N_198, Q => - fault_pro); - - \r.walk_fault.fault_lvl_RNI1M09[0]\ : NOR2B - port map(A => walk_use_0, B => \fault_lvl[0]\, Y => - un1_itlb0_1(41)); - - \r.walk_transdata.data[13]\ : DFN1E0 - port map(D => N_2622, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[13]\); - - \r.s2_entry_1_RNIPUJF[1]\ : MX2 - port map(A => N_844, B => N_878, S => \s2_entry_1[1]\, Y - => N_912); - - \r.s2_tlbstate[1]\ : DFN1 - port map(D => \s2_tlbstate_nss[1]\, CLK => lclk_c, Q => - \s2_tlbstate[1]\); - - \r.s2_entry_0_RNIDKDM1[0]\ : MX2 - port map(A => N_800, B => N_902, S => \s2_entry_0[0]\, Y - => adata_0); - - \r.walk_transdata.data[28]\ : DFN1E0 - port map(D => \data_1[28]\, CLK => lclk_c, E => N_6_i, Q - => \data[28]\); - - \p0.transdata.data_1_i_RNO[23]\ : AND2 - port map(A => N_2985, B => N_2984, Y => \data_1_i_0[23]\); - - \r.s2_su\ : DFN1E1 - port map(D => su, CLK => lclk_c, E => s1finished, Q => - \fault_su\); - - \r.s2_entry_5_RNIA2ARQ2_3[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => \tlbcam_write_op_1[2]\); - - \r.s2_data_RNI8V2E[28]\ : MX2C - port map(A => address(28), B => \data_0[28]\, S => s2_flush, - Y => N_651); - - \r.s2_data[18]\ : DFN1E1 - port map(D => address(18), CLK => lclk_c, E => - \s1finished_0\, Q => \data[18]\); - - \r.s2_entry_0_RNIRH7RQ2_1[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => - \tlbcam_write_op_1_1_0[6]\); - - \r.s2_data_RNI4R2E[18]\ : MX2C - port map(A => address(18), B => \data[18]\, S => s2_flush, - Y => N_617); - - \r.walk_transdata.data[11]\ : DFN1E0 - port map(D => \data[11]\, CLK => lclk_c, E => N_6_i_0, Q - => \data_0[11]\); - - \r.s2_entry_1_RNIKKVP[1]\ : MX2 - port map(A => N_762, B => N_796, S => \s2_entry_1[1]\, Y - => N_830); - - \r.walk_transdata.data_RNO[28]\ : MX2 - port map(A => \data_0[28]\, B => hrdata_0_23, S => \N_2571\, - Y => \data_1[28]\); - - \r.s2_entry_RNIAPR93[0]\ : OR2 - port map(A => \adata[25]\, B => N_3064, Y => N_2992); - - \r.s2_data[5]\ : DFN1E1 - port map(D => address(5), CLK => lclk_c, E => s1finished, Q - => \data[5]\); - - \r.walk_transdata.data[25]\ : DFN1E0 - port map(D => N_2729, CLK => lclk_c, E => N_6_i, Q => - \data_0[25]\); - - \r.s2_entry_RNISCSJ1_0[0]\ : OR2 - port map(A => \un1_acc[33]\, B => \un1_acc[32]\, Y => N_554); - - \r.s2_data_RNI2N2E[17]\ : MX2C - port map(A => address(17), B => \data[17]\, S => s2_flush, - Y => N_596); - - \r.s2_data_RNI097N1[27]\ : OR2A - port map(A => N_3061, B => \data[27]\, Y => N_2966); - - \tlbcam0.1.tag0\ : mmutlbcam_0_0_5 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0(7) => - hrdata_0_6, tlbcam_write_op_1(1) => - \tlbcam_write_op_1[1]\, tlbcam_write_op_1_1(1) => - \tlbcam_write_op_1_1[1]\, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0_d0 => hrdata_0_d0, hrdata_6 => hrdata_6, - s2_entry(2) => \s2_entry[2]\, tlbcam_write_op_1_0(1) => - \tlbcam_write_op_1_0[1]\, s2_entry_5(2) => - \s2_entry_5[2]\, LVL_0(1) => \LVL_2[1]\, LVL_0(0) => - \LVL_2[0]\, s2_entry_4(2) => \s2_entry_4[2]\, - s2_entry_3(2) => \s2_entry_3[2]\, pteout_0_4 => - \pteout_2[4]\, pteout_0_17 => \pteout_2[17]\, pteout_0_18 - => \pteout_2[18]\, pteout_0_11 => \pteout_2[11]\, - pteout_0_31 => \pteout_2[31]\, pteout_0_30 => - \pteout_2[30]\, pteout_0_29 => \pteout_2[29]\, - pteout_0_28 => \pteout_2[28]\, pteout_0_27 => - \pteout_2[27]\, pteout_0_26 => \pteout_2[26]\, - pteout_0_25 => \pteout_2[25]\, pteout_0_24 => - \pteout_2[24]\, pteout_0_23 => \pteout_2[23]\, - pteout_0_22 => \pteout_2[22]\, pteout_0_21 => - \pteout_2[21]\, pteout_0_20 => \pteout_2[20]\, - pteout_0_19 => \pteout_2[19]\, pteout_0_16 => - \pteout_2[16]\, pteout_0_15 => \pteout_2[15]\, - pteout_0_14 => \pteout_2[14]\, pteout_0_13 => - \pteout_2[13]\, pteout_0_12 => \pteout_2[12]\, - pteout_0_10 => \pteout_2[10]\, pteout_0_9 => - \pteout_2[9]\, pteout_0_8 => \pteout_2[8]\, pteout_0_7 - => \pteout_2[7]\, pteout_0_6 => \pteout_2[6]\, - pteout_0_3 => \pteout_2[3]\, pteout_0_2 => \pteout_2[2]\, - pteout_0_1 => \pteout_2[1]\, pteout_0_0 => \pteout_2[0]\, - ctx_0(7) => ctx_0(7), ctx_0(6) => ctx_0(6), ctx_0(5) => - ctx_0(5), ctx_0(4) => ctx_0(4), ctx_0(3) => ctx_0(3), - ctx_0(2) => ctx_0(2), ctx_0(1) => ctx_0(1), ctx_0(0) => - ctx_0(0), s2_entry_1_i_a2_0(0) => \s2_entry_1_i_a2_0[0]\, - N_78 => N_78, N_262 => N_262, N_264 => N_264, N_2482 => - N_2482, lclk_c => lclk_c, N_838 => N_838, N_851 => N_851, - N_852 => N_852, N_845 => N_845, N_867 => N_867, s2_flush - => s2_flush, un1_rst_i_0 => un1_rst_i_0, N_200 => N_200, - N_42 => N_42, N_866 => N_866, N_596 => N_596, N_620 => - N_620, N_594 => N_594, N_593 => N_593, N_597 => N_597, - N_665 => N_665, N_651 => N_651, N_865 => N_865, N_864 => - N_864, N_863 => N_863, N_862 => N_862, N_861 => N_861, - N_860 => N_860, N_859 => N_859, N_858 => N_858, N_857 => - N_857, N_856 => N_856, N_855 => N_855, N_854 => N_854, - N_853 => N_853, N_850 => N_850, N_849 => N_849, N_848 => - N_848, N_847 => N_847, N_846 => N_846, N_844 => N_844, - N_843 => N_843, N_842 => N_842, N_841 => N_841, N_840 => - N_840, N_837 => N_837, N_836 => N_836, N_835 => N_835, - N_834 => N_834, N_634 => N_634, N_632 => N_632, N_662 => - N_662, N_650 => N_650, N_639 => N_639, N_635 => N_635, - hit_0_a3_0 => hit_0_a3_0, N_631_i => N_631_i, N_633 => - N_633, N_595 => N_595, N_663 => N_663, N_664 => N_664, - N_612 => N_612, N_200_0 => N_200_0, N_617 => N_617, N_204 - => N_204, N_170_1 => N_170_1, hit_i_0 => hit_i_0, N_557 - => N_557); - - \r.s2_entry_RNIQ0TD[1]\ : MX2 - port map(A => N_866, B => N_900, S => \s2_entry[1]\, Y => - N_934); - - \r.s2_entry_RNIB1UN[1]\ : MX2 - port map(A => N_865, B => N_899, S => \s2_entry[1]\, Y => - N_933); - - \r.walk_fault.fault_pro_RNI3LP74\ : MX2 - port map(A => N_1633, B => fault_pro, S => walk_use_1, Y - => N_2577); - - \r.s2_entry_1[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_1_0[2]\); - - \r.s2_entry_0_RNIRH7RQ2_0[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => - \tlbcam_write_op_1_1_0[5]\); - - \r.s2_data_RNIBF7Q1[19]\ : MX2 - port map(A => \adata[15]\, B => \data[19]\, S => - \un1_acc[33]\, Y => N_667); - - \r.s2_data_RNITT5R1[17]\ : OR3A - port map(A => N_554, B => walk_use_1, C => \data[17]\, Y - => N_3017); - - \r.s2_data[7]\ : DFN1E1 - port map(D => address(7), CLK => lclk_c, E => s1finished, Q - => \data[7]\); - - \r.s2_entry_1_RNI5VJF[1]\ : MX2 - port map(A => N_847, B => N_881, S => \s2_entry_1[1]\, Y - => N_915); - - \r.s2_entry_0_RNI4MBP[1]\ : MX2 - port map(A => N_732, B => N_766, S => \s2_entry_0[1]\, Y - => N_800); - - \r.walk_transdata.data_RNO[13]\ : MX2 - port map(A => hrdata_0_8, B => \data[13]\, S => N_3160, Y - => N_2622); - - \r.walk_transdata.data[27]\ : DFN1E0 - port map(D => N_2731, CLK => lclk_c, E => N_6_i, Q => - \data_0[27]\); - - \r.s2_data_RNI4R7E5[29]\ : OR3C - port map(A => N_2992, B => N_2993, C => N_2994, Y => N_363); - - \r.s2_data_RNI9B8E5[31]\ : OR3C - port map(A => N_2995, B => N_2996, C => N_2997, Y => N_365); - - \r.s2_entry_1_RNIHUJF[1]\ : MX2 - port map(A => N_842, B => N_876, S => \s2_entry_1[1]\, Y - => N_910); - - \r.s2_entry_0_RNIRH7RQ2_3[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_0[7]\); - - \r.walk_transdata.data_RNO[16]\ : MX2 - port map(A => hrdata_0_11, B => \data[16]\, S => N_3160, Y - => N_2727); - - \r.s2_ctx[5]\ : DFN1E1 - port map(D => ctx(5), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[5]\); - - dataram : syncramZ0 - port map(aaddr(31) => aaddr(31), aaddr(30) => aaddr(30), - aaddr(29) => aaddr(29), aaddr(28) => aaddr(28), aaddr(27) - => aaddr(27), aaddr(26) => aaddr(26), aaddr(25) => - aaddr(25), aaddr(24) => aaddr(24), aaddr(23) => aaddr(23), - aaddr(22) => aaddr(22), aaddr(21) => aaddr(21), aaddr(20) - => aaddr(20), aaddr(19) => aaddr(19), aaddr(18) => - aaddr(18), aaddr(17) => aaddr(17), aaddr(16) => aaddr(16), - aaddr(15) => aaddr(15), aaddr(14) => aaddr(14), aaddr(13) - => aaddr(13), aaddr(12) => aaddr(12), aaddr(11) => - aaddr(11), aaddr(10) => aaddr(10), aaddr(9) => aaddr(9), - aaddr(8) => aaddr(8), aaddr(7) => aaddr(7), aaddr(6) => - aaddr(6), aaddr(5) => aaddr(5), aaddr(4) => aaddr(4), - aaddr(3) => aaddr(3), aaddr(2) => aaddr(2), address(31) - => address_0(31), address(30) => address_0(30), - address(29) => address_0(29), address(28) => - address_0(28), address(27) => address_0(27), address(26) - => address_0(26), address(25) => address_0(25), - address(24) => address_0(24), address(23) => - address_0(23), address(22) => address_0(22), address(21) - => address_0(21), address(20) => address_0(20), - address(19) => address_0(19), address(18) => - address_0(18), address(17) => address_0(17), address(16) - => address_0(16), address(15) => address_0(15), - address(14) => address_0(14), address(13) => - address_0(13), address(12) => address_0(12), address(11) - => address_0(11), address(10) => address_0(10), - address(9) => address_0(9), address(8) => address_0(8), - address(7) => address_0(7), address(6) => address_0(6), - address(5) => address_0(5), address(4) => address_0(4), - address(3) => address_0(3), address(2) => address_0(2), - s2_entry(2) => \s2_entry[2]\, s2_entry(1) => - \s2_entry[1]\, s2_entry(0) => \s2_entry[0]\, - dr1write_0_sqmuxa => dr1write_0_sqmuxa, syncramZ0_VCC => - mmutlb_10_8_0_1_0_VCC, lclk_c => lclk_c); - - \r.s2_entry_RNITNJM[0]\ : MX2 - port map(A => N_833, B => N_935, S => \s2_entry[0]\, Y => - \un1_acc[33]\); - - \tlbcam0.7.tag0\ : mmutlbcam_0_0_3 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0_17 => - hrdata_0_23, hrdata_0_10 => hrdata_0_16, hrdata_0_7 => - hrdata_0_13, hrdata_0_6 => hrdata_0_12, hrdata_0_4 => - hrdata_0_10, hrdata_0_3 => hrdata_0_9, hrdata_0_2 => - hrdata_0_8, hrdata_0_0 => hrdata_0_6, - tlbcam_write_op_1(7) => \tlbcam_write_op_1[7]\, - tlbcam_write_op_1_1_0(7) => \tlbcam_write_op_1_1_0[7]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 - => hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => - hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 => - hrdata_0_d0, hrdata_6 => hrdata_6, pteout_4 => - \pteout_1[4]\, pteout_3 => \pteout_1[3]\, pteout_2 => - \pteout_1[2]\, pteout_31 => \pteout_1[31]\, pteout_30 => - \pteout_1[30]\, pteout_29 => \pteout_1[29]\, pteout_28 - => \pteout_1[28]\, pteout_27 => \pteout_1[27]\, - pteout_26 => \pteout_1[26]\, pteout_25 => \pteout_1[25]\, - pteout_24 => \pteout_1[24]\, pteout_23 => \pteout_1[23]\, - pteout_22 => \pteout_1[22]\, pteout_21 => \pteout_1[21]\, - pteout_20 => \pteout_1[20]\, pteout_19 => \pteout_1[19]\, - pteout_18 => \pteout_1[18]\, pteout_17 => \pteout_1[17]\, - pteout_16 => \pteout_1[16]\, pteout_15 => \pteout_1[15]\, - pteout_14 => \pteout_1[14]\, pteout_13 => \pteout_1[13]\, - pteout_12 => \pteout_1[12]\, pteout_11 => \pteout_1[11]\, - pteout_10 => \pteout_1[10]\, pteout_9 => \pteout_1[9]\, - pteout_8 => \pteout_1[8]\, pteout_1 => \pteout_1[1]\, - pteout_0 => \pteout_1[0]\, pteout_7 => \pteout_1[7]\, - pteout_6 => \pteout_1[6]\, tlbcam_write_op_1_0(7) => - \tlbcam_write_op_1_0[7]\, s2_entry_1_i_a2_1_2(1) => - \s2_entry_1_i_a2_1_2[1]\, ctx_0(7) => ctx_0(7), ctx_0(6) - => ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), - ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => - ctx_0(1), ctx_0(0) => ctx_0(0), LVL(1) => \LVL_1[1]\, - LVL(0) => \LVL_1[0]\, s2_entry_1_i_a2_0(0) => - \s2_entry_1_i_a2_0[0]\, s2_entry_1_i_a2_2(0) => - \s2_entry_1_i_a2_2[0]\, N_78_0 => N_78_0, N_262_0 => - N_262_0, N_264_0 => N_264_0, N_2482 => N_2482, lclk_c => - lclk_c, N_42 => N_42, N_200 => N_200, un1_rst_i_0 => - un1_rst_i_0, N_596 => N_596, N_620 => N_620, N_594 => - N_594, N_593 => N_593, N_597 => N_597, N_665 => N_665, - N_634 => N_634, N_632 => N_632, N_631_i => N_631_i, N_639 - => N_639, N_635 => N_635, s2_flush_0 => s2_flush_0, - hit_0_a3_0 => hit_0_a3_0, N_2937_1 => N_2937_1, N_170_1 - => N_170_1, N_633 => N_633, N_595 => N_595, N_663 => - N_663, N_664 => N_664, N_651 => N_651, N_612 => N_612, - N_200_0 => N_200_0, N_617 => N_617, N_650 => N_650, N_662 - => N_662, N_204 => N_204); - - \r.walk_transdata.data_RNIL44D[26]\ : OR2A - port map(A => walk_use_1, B => \data_0[26]\, Y => N_2989); - - \r.sync_isw_RNIO5LAF1\ : AO1D - port map(A => \twi_areq_ur_1_0_a3_i_0\, B => N_2563_i, C - => \walk_op_ur\, Y => N_180); - - \r.s2_entry_RNIE098[1]\ : MX2 - port map(A => N_838, B => N_872, S => \s2_entry[1]\, Y => - N_906); - - \r.s2_entry_5[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_5[2]\); - - \r.sync_isw_RNIB75G\ : OR2 - port map(A => sync_isw, B => N_2568, Y => - \twi_areq_ur_1_0_a3_i_0\); - - \r.s2_entry_4[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_4[2]\); - - \r.s2_tlbstate_RNI65SS[1]\ : AO1A - port map(A => s2_flush, B => N_562, C => \s2_tlbstate[1]\, - Y => N_2899); - - \r.s2_hm_RNIVT4D1\ : OR2A - port map(A => rst, B => \s1finished_0\, Y => un1_rst_2); - - \r.walk_use\ : DFN1E1 - port map(D => cache_0_sqmuxa_1_1, CLK => lclk_c, E => - s2_tlbstate_3, Q => \walk_use\); - - \r.s2_data_RNI9BAC3[24]\ : MX2 - port map(A => \data[24]\, B => \adata[20]\, S => N_3162, Y - => \data_0[24]\); - - \r.s2_data[2]\ : DFN1E1 - port map(D => address(2), CLK => lclk_c, E => s1finished, Q - => \data[2]\); - - \r.walk_transdata.data_RNO[20]\ : MX2 - port map(A => hrdata_0_15, B => \data[20]\, S => - lvl_i_1_0(1), Y => N_640); - - \r.walk_fault.fault_inv_RNO\ : NOR3A - port map(A => inv_1_0_a2_0_a2_0, B => hrdata_0_0, C => - N_2917, Y => N_18); - - \r.walk_transdata.data[4]\ : DFN1E0 - port map(D => \data[4]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[4]\); - - \r.s2_data_RNIPH5R1[14]\ : OR3A - port map(A => N_554, B => walk_use_0, C => \data_0[14]\, Y - => N_2667); - - \r.walk_use_0_RNIO6C55\ : OR2B - port map(A => \data_1_i_0[14]\, B => N_2669, Y => N_45); - - \r.s2_entry_0_RNIBGHN1[0]\ : MX2 - port map(A => N_819, B => N_921, S => \s2_entry_0[0]\, Y - => \adata[19]\); - - \r.walk_transdata.data[18]\ : DFN1E0 - port map(D => N_2890, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[18]\); - - \r.s2_entry_1_RNI0L1Q[1]\ : MX2 - port map(A => N_854, B => N_888, S => \s2_entry_1[1]\, Y - => N_922); - - \r.s2_tlbstate_RNICNFP3[1]\ : NOR3 - port map(A => \adata[3]\, B => un11_finish_li, C => N_2492, - Y => N_1633); - - \r.s2_entry_0_RNIQK0Q[1]\ : MX2 - port map(A => N_756, B => N_790, S => \s2_entry_0[1]\, Y - => N_824); - - \r.s2_data[20]\ : DFN1E1 - port map(D => address(20), CLK => lclk_c, E => s1finished, - Q => \data[20]\); - - \r.s2_entry_5_RNIA2ARQ2_1[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => \tlbcam_write_op_1[4]\); - - \r.walk_transdata.data[15]\ : DFN1E0 - port map(D => N_17, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[15]\); - - \r.s2_data_RNIEUB55[13]\ : OR3C - port map(A => N_2664, B => N_2665, C => N_2666, Y => N_2624); - - \r.s2_tlbstate_RNI6U6NN[1]\ : OR2B - port map(A => rst, B => N_6_i_0, Y => nrepe); - - \r.s2_data_RNISP5R1[16]\ : OR3A - port map(A => N_554, B => walk_use_1, C => \data[16]\, Y - => N_3014); - - \r.walk_transdata.data[26]\ : DFN1E0 - port map(D => N_2730, CLK => lclk_c, E => N_6_i, Q => - \data_0[26]\); - - \r.s2_data_RNIRDQC[22]\ : MX2C - port map(A => address(22), B => \data_0[22]\, S => - s2_flush_0, Y => N_662); - - \r.walk_transdata.data_RNIOG4D[29]\ : OR2A - port map(A => walk_use_1, B => \data[29]\, Y => N_2993); - - \r.walk_transdata.data[17]\ : DFN1E0 - port map(D => N_67, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[17]\); - - \r.s2_entry_0_RNI3CME[1]\ : MX2 - port map(A => N_735, B => N_769, S => \s2_entry_0[1]\, Y - => N_803); - - \r.walk_fault.fault_mexc\ : DFN1E1 - port map(D => N_16, CLK => lclk_c, E => N_175, Q => - fault_mexc); - - \r.s2_entry_RNIQCUB3[0]\ : OR2 - port map(A => \adata[23]\, B => N_3064, Y => N_2964); - - \r.s2_data_RNIO75I5[30]\ : OR3C - port map(A => N_2602, B => N_2603, C => N_2604, Y => N_43); - - \r.s2_data_RNI1QQC[25]\ : MX2C - port map(A => address(25), B => \data[25]\, S => s2_flush_0, - Y => N_635); - - \r.s2_entry_RNIKDIL1[0]\ : MX2 - port map(A => N_823, B => N_925, S => \s2_entry[0]\, Y => - \adata[23]\); - - \r.walk_transdata.data_RNIUIFL3[24]\ : MX2C - port map(A => \data_0[24]\, B => \data_1[24]\, S => - \walk_use\, Y => un1_m0_22); - - \r.s2_hm_RNIMNCD1\ : NOR2B - port map(A => \s1finished_0\, B => flush_op, Y => - s2_flush_1); - - \r.walk_use_0\ : DFN1E1 - port map(D => cache_0_sqmuxa_1_1, CLK => lclk_c, E => - s2_tlbstate_3, Q => walk_use_0); - - \r.walk_transdata.data[5]\ : DFN1E0 - port map(D => \data[5]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[5]\); - - \r.s2_entry_RNIAI39[1]\ : MX2 - port map(A => N_743, B => N_777, S => \s2_entry[1]\, Y => - N_811); - - \r.s2_data_RNI1D7N1[28]\ : OR2A - port map(A => N_3061, B => \data_0[28]\, Y => N_2970); - - \r.walk_transdata.data_RNO[12]\ : MX2 - port map(A => hrdata_0_7, B => \data[12]\, S => N_3160, Y - => N_2621); - - \r.walk_transdata.data[6]\ : DFN1E0 - port map(D => \data[6]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[6]\); - - \r.s2_entry_0_RNI2EHF[1]\ : MX2 - port map(A => N_741, B => N_775, S => \s2_entry_0[1]\, Y - => N_809); - - \r.sync_isw\ : DFN1 - port map(D => sync_isw_RNO, CLK => lclk_c, Q => sync_isw); - - \r.s2_tlbstate_RNO_1[0]\ : OR2A - port map(A => \s2_tlbstate_ns_0_0_a2_2_0[0]\, B => N_86_i, - Y => N_2611); - - \r.s2_entry_RNI6OFJ[1]\ : MX2 - port map(A => N_852, B => N_886, S => \s2_entry[1]\, Y => - N_920); - - \r.s2_tlbstate[0]\ : DFN1 - port map(D => \s2_tlbstate_nss[0]\, CLK => lclk_c, Q => - \s2_tlbstate[0]\); - - \r.s2_data_RNIPVC55[17]\ : OR3C - port map(A => N_3017, B => N_3019, C => N_3020, Y => N_425); - - \r.s2_entry_1_RNIPK0Q[1]\ : MX2 - port map(A => N_853, B => N_887, S => \s2_entry_1[1]\, Y - => N_921); - - \r.s2_data_RNIFU9G5[27]\ : OR3C - port map(A => N_2964, B => N_2965, C => N_2966, Y => N_319); - - \r.s2_entry_0_RNIU41Q[1]\ : MX2 - port map(A => N_757, B => N_791, S => \s2_entry_0[1]\, Y - => N_825); - - \r.s2_hm\ : DFN1E1 - port map(D => cam_hit_all_1, CLK => lclk_c, E => s1finished, - Q => s2_hm); - - \r.s2_entry_1_RNI1NFP[1]\ : MX2 - port map(A => N_835, B => N_869, S => \s2_entry_1[1]\, Y - => N_903); - - \r.walk_transdata.data[8]\ : DFN1E0 - port map(D => \data[8]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[8]\); - - \r.s2_entry_0_RNIIEHF[1]\ : MX2 - port map(A => N_745, B => N_779, S => \s2_entry_0[1]\, Y - => N_813); - - \r.walk_transdata.data_RNO[14]\ : MX2 - port map(A => hrdata_0_9, B => \data_0[14]\, S => N_3160, Y - => N_15); - - \r.s2_hm_RNIUVF7\ : OR2A - port map(A => s2_hm, B => tlbdis, Y => N_2355); - - \r.walk_fault.fault_pri_RNO\ : NOR3B - port map(A => N_556, B => N_2482, C => \fault_su\, Y => - N_206); - - \r.s2_entry_0_RNI2KTP[1]\ : MX2 - port map(A => N_750, B => N_784, S => \s2_entry_0[1]\, Y - => N_818); - - \r.walk_transdata.data_RNI25V9[10]\ : MX2C - port map(A => \data[10]\, B => \data_0[10]\, S => - \walk_use\, Y => un1_m0_8); - - \r.s2_tlbstate_RNIG6DGR2[1]\ : OR2A - port map(A => N_556, B => dr1write_0_sqmuxa, Y => N_198); - - \r.s2_entry_1_RNIS0PD[1]\ : MX2 - port map(A => N_841, B => C_RNIL004, S => \s2_entry_1[1]\, - Y => N_909); - - \r.nrep_RNO[0]\ : NOR2A - port map(A => rst, B => \nrep[0]\, Y => nrep_n0); - - \r.s2_hm_RNO_1\ : NOR3C - port map(A => cam_hit_all_1_0, B => SU_RNIAA5O8, C => N_170, - Y => cam_hit_all_1_2); - - \r.s2_entry_RNIVAT2_2[0]\ : OR2 - port map(A => \s2_entry[1]\, B => \s2_entry[0]\, Y => - \tlbcam_write_op_1_1[0]\); - - \r.s2_data_RNI52RC[27]\ : MX2C - port map(A => address(27), B => \data[27]\, S => s2_flush_0, - Y => N_639); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.walk_transdata.data_RNI20C72[19]\ : MX2C - port map(A => N_667, B => \data_0[19]\, S => walk_use_1, Y - => un1_m0_17); - - \r.walk_transdata.data_RNIIN49[30]\ : OR2A - port map(A => \walk_use\, B => \data_0[30]\, Y => N_2603); - - \r.s2_entry_2[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_2[2]\); - - \r.s2_data[10]\ : DFN1E1 - port map(D => address(10), CLK => lclk_c, E => - \s1finished_0\, Q => \data[10]\); - - \r.walk_transdata.data_RNO[30]\ : MX2 - port map(A => \data[30]\, B => hrdata_0_25, S => \N_2571\, - Y => N_2554); - - \r.s2_entry_0_RNIC01E3[0]\ : OR2 - port map(A => \adata[22]\, B => N_3064, Y => N_2988); - - \r.s2_data[29]\ : DFN1E1 - port map(D => address(29), CLK => lclk_c, E => s1finished, - Q => \data_0[29]\); - - \r.sync_isw_RNO\ : AO1B - port map(A => sync_isw_1_i_i_a2_0_0, B => dr1write_0_sqmuxa, - C => N_2593, Y => sync_isw_RNO); - - \tlbcam0.2.tag0\ : mmutlbcam_0_0_6 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1(2) => \tlbcam_write_op_1[2]\, - tlbcam_write_op_1_1(2) => \tlbcam_write_op_1_1[2]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_24 => - hrdata_24, hrdata_23 => hrdata_23, hrdata_22 => hrdata_22, - hrdata_21 => hrdata_21, hrdata_18 => hrdata_18, hrdata_17 - => hrdata_17, hrdata_16 => hrdata_16, hrdata_15 => - hrdata_15, hrdata_14 => hrdata_14, hrdata_13 => hrdata_13, - hrdata_12 => hrdata_12, hrdata_11 => hrdata_11, hrdata_10 - => hrdata_10, hrdata_9 => hrdata_9, hrdata_8 => hrdata_8, - hrdata_1 => hrdata_1, hrdata_0 => hrdata_0_d0, hrdata_7 - => hrdata_7, hrdata_6 => hrdata_6, s2_entry(2) => - \s2_entry[2]\, tlbcam_write_op_1_0(2) => - \tlbcam_write_op_1_0[2]\, LVL_0(1) => \LVL_0[1]\, - s2_entry_3(2) => \s2_entry_3[2]\, s2_entry_2(2) => - \s2_entry_2[2]\, s2_entry_1(2) => \s2_entry_1_0[2]\, - pteout_0_4 => \pteout_0[4]\, pteout_0_17 => - \pteout_0[17]\, pteout_0_11 => \pteout_0[11]\, - pteout_0_31 => \pteout_0[31]\, pteout_0_30 => - \pteout_0[30]\, pteout_0_29 => \pteout_0[29]\, - pteout_0_28 => \pteout_0[28]\, pteout_0_27 => - \pteout_0[27]\, pteout_0_26 => \pteout_0[26]\, - pteout_0_25 => \pteout_0[25]\, pteout_0_24 => - \pteout_0[24]\, pteout_0_23 => \pteout_0[23]\, - pteout_0_22 => \pteout_0[22]\, pteout_0_21 => - \pteout_0[21]\, pteout_0_20 => \pteout_0[20]\, - pteout_0_19 => \pteout_0[19]\, pteout_0_18 => - \pteout_0[18]\, pteout_0_16 => \pteout_0[16]\, - pteout_0_15 => \pteout_0[15]\, pteout_0_14 => - \pteout_0[14]\, pteout_0_13 => \pteout_0[13]\, - pteout_0_12 => \pteout_0[12]\, pteout_0_10 => - \pteout_0[10]\, pteout_0_9 => \pteout_0[9]\, pteout_0_8 - => \pteout_0[8]\, pteout_0_7 => \pteout_0[7]\, - pteout_0_6 => \pteout_0[6]\, pteout_0_3 => \pteout_0[3]\, - pteout_0_2 => \pteout_0[2]\, pteout_0_1 => \pteout_0[1]\, - pteout_0_0 => \pteout_0[0]\, ctx_0(7) => ctx_0(7), - ctx_0(6) => ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => - ctx_0(4), ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), - ctx_0(1) => ctx_0(1), ctx_0(0) => ctx_0(0), LVL_0_d0 => - \LVL_0[0]\, N_78 => N_78, N_262 => N_262, N_264 => N_264, - N_2482 => N_2482, lclk_c => lclk_c, N_770 => N_770, N_783 - => N_783, N_777 => N_777, s2_flush => s2_flush, - un1_rst_i_0 => un1_rst_i_0, N_631_i => N_631_i, N_632 => - N_632, N_634 => N_634, N_596 => N_596, N_42 => N_42, - N_200 => N_200, N_620 => N_620, N_594 => N_594, N_593 => - N_593, N_597 => N_597, N_665 => N_665, N_799 => N_799, - N_797 => N_797, N_796 => N_796, N_795 => N_795, N_794 => - N_794, N_793 => N_793, N_792 => N_792, N_791 => N_791, - N_790 => N_790, N_789 => N_789, N_788 => N_788, N_787 => - N_787, N_786 => N_786, N_785 => N_785, N_784 => N_784, - N_782 => N_782, N_781 => N_781, N_780 => N_780, N_779 => - N_779, N_778 => N_778, N_776 => N_776, N_775 => N_775, - N_774 => N_774, N_773 => N_773, N_772 => N_772, N_769 => - N_769, N_768 => N_768, N_767 => N_767, N_766 => N_766, - N_639 => N_639, N_635 => N_635, hit_0_a3_0 => hit_0_a3_0, - N_2937_1 => N_2937_1, N_557 => N_557, N_2937 => N_2937, - hit => hit, N_3068 => N_3068, N_170_1 => N_170_1, N_663 - => N_663, N_664 => N_664, N_651 => N_651, N_612 => N_612, - N_633 => N_633, N_595 => N_595, N_200_0 => N_200_0, N_617 - => N_617, N_650 => N_650, N_662 => N_662, N_204 => N_204); - - \r.walk_fault.fault_mexc_RNO\ : NOR2A - port map(A => fault_mexc_2, B => N_2917, Y => N_16); - - \r.s2_tlbstate_RNI1PHJN_1[1]\ : NOR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => N_2563_i, Y => \walk_op_ur\); - - \r.s2_entry_1[1]\ : DFN1E1 - port map(D => N_212_i_0, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_1[1]\); - - \r.nrep_RNIKI8IV4[1]\ : OA1 - port map(A => N_557, B => \nrep[1]\, C => N_2937, Y => - N_212_i_0); - - \r.walk_transdata.data_RNIMB59[25]\ : OR2A - port map(A => \walk_use\, B => \data_0[25]\, Y => N_2674); - - \r.walk_fault.fault_trans_RNI4QM59\ : NOR3C - port map(A => fault_inv_m, B => ft_1_i_a2_0(0), C => - fault_trans_m, Y => \N_1629\); - - \r.walk_transdata.data_RNO[17]\ : MX2 - port map(A => hrdata_0_12, B => \data[17]\, S => N_3160, Y - => N_67); - - \r.walk_transdata.data[22]\ : DFN1E0 - port map(D => N_688, CLK => lclk_c, E => N_6_i, Q => - \data[22]\); - - \r.s2_tlbstate_RNO_0[0]\ : OA1A - port map(A => \s2_tlbstate[0]\, B => N_2563_i, C => - \s2_tlbstate_ns_0_0_0[0]\, Y => \s2_tlbstate_ns_0_0_1[0]\); - - \r.nrep_RNO[1]\ : XA1 - port map(A => \nrep[1]\, B => \nrep[0]\, C => rst, Y => - nrep_n1); - - \r.walk_transdata.data[16]\ : DFN1E0 - port map(D => N_2727, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[16]\); - - \r.s2_tlbstate_RNIN377O[1]\ : AO1B - port map(A => cache_0_sqmuxa_1_1, B => N_2563_i, C => - \N_2933\, Y => s2_tlbstate_3); - - \r.s2_entry_RNIVGSN[1]\ : MX2 - port map(A => N_862, B => N_896, S => \s2_entry[1]\, Y => - N_930); - - \r.s2_entry_0_RNIUEHF[1]\ : MX2 - port map(A => N_748, B => N_782, S => \s2_entry_0[1]\, Y - => N_816); - - \r.s2_entry_0_RNI0G211[0]\ : MX2 - port map(A => N_802, B => N_904, S => \s2_entry_0[0]\, Y - => \adata[2]\); - - \r.s2_entry_1_RNIO40Q[1]\ : MX2 - port map(A => N_763, B => N_797, S => \s2_entry_1[1]\, Y - => N_831); - - \r.s2_entry_0_RNI6EHF[1]\ : MX2 - port map(A => N_742, B => N_776, S => \s2_entry_0[1]\, Y - => N_810); - - \r.walk_transdata.data[3]\ : DFN1E0 - port map(D => \data[3]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[3]\); - - \r.walk_transdata.data_RNIAE982[14]\ : OA1A - port map(A => walk_use_0, B => \data[14]\, C => N_2667, Y - => \data_1_i_0[14]\); - - \r.s2_entry_1_RNILCPE[1]\ : MX2 - port map(A => N_836, B => N_870, S => \s2_entry_1[1]\, Y - => N_904); - - \r.s2_data_RNIN95R1[12]\ : OR3A - port map(A => N_554, B => walk_use_0, C => \data[12]\, Y - => N_2661); - - \r.s2_data[9]\ : DFN1E1 - port map(D => address(9), CLK => lclk_c, E => s1finished, Q - => \data[9]\); - - \r.s2_entry_0_RNIEEHF[1]\ : MX2 - port map(A => N_744, B => N_778, S => \s2_entry_0[1]\, Y - => N_812); - - \r.walk_transdata.data_RNIS2B32[20]\ : MX2B - port map(A => N_630, B => \data_0[20]\, S => \walk_use\, Y - => N_2625); - - \r.walk_transdata.data_RNI2FPD[2]\ : MX2C - port map(A => \data[2]\, B => \data_0[2]\, S => walk_use_1, - Y => un1_m0_0); - - \r.walk_fault.fault_pro_RNIH439J\ : AO1B - port map(A => fault_isid_1_i(0), B => N_2577, C => - fault_pro_m, Y => fault_pro_1); - - \r.s2_tlbstate_RNIE7NKQ2[1]\ : NOR2 - port map(A => N_86_i, B => N_6_i_0, Y => dr1write_0_sqmuxa); - - \r.s2_entry_RNINVRE1[0]\ : MX2 - port map(A => N_818, B => N_920, S => \s2_entry[0]\, Y => - \adata[18]\); - - \r.walk_use_1_RNI7P2T2\ : OR3 - port map(A => N_554, B => walk_use_1, C => \adata[13]\, Y - => N_3020); - - \r.s2_tlbstate_RNO_3[0]\ : NOR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => hrdata_5, Y => \s2_tlbstate_ns_0_0_a2_2_0[0]\); - - \r.s2_entry_0_RNI2L1Q[1]\ : MX2 - port map(A => N_758, B => N_792, S => \s2_entry_0[1]\, Y - => N_826); - - \r.s2_entry_0[1]\ : DFN1E1 - port map(D => N_212_i_0, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_0[1]\); - - \r.walk_fault.fault_trans_RNIM6E83\ : OR3C - port map(A => walk_use_0, B => fault_trans, C => - fault_isid_1_i(0), Y => fault_trans_m); - - \r.s2_entry_5_RNIA2ARQ2_4[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => \tlbcam_write_op_1[1]\); - - \r.walk_transdata.data_RNIL84D[27]\ : OR2A - port map(A => walk_use_0, B => \data_0[27]\, Y => N_2965); - - \r.s2_tlbstate_RNI2VLR[1]\ : OR2A - port map(A => N_555, B => N_553, Y => N_556); - - \r.s2_entry_0_RNIM40Q[1]\ : MX2 - port map(A => N_755, B => N_789, S => \s2_entry_0[1]\, Y - => N_823); - - \r.walk_transdata.data_RNO[23]\ : MX2 - port map(A => N_264_0, B => \data[23]\, S => lvl_i_1_0(1), - Y => N_689); - - \r.s2_entry_0[0]\ : DFN1E1 - port map(D => N_208, CLK => lclk_c, E => s2_entry_0_sqmuxa, - Q => \s2_entry_0[0]\); - - \r.s2_data[19]\ : DFN1E1 - port map(D => address(19), CLK => lclk_c, E => - \s1finished_0\, Q => \data[19]\); - - \r.s2_entry_1_RNI9VJF[1]\ : MX2 - port map(A => N_848, B => N_882, S => \s2_entry_1[1]\, Y - => N_916); - - \r.s2_data_RNIRL5R1[25]\ : OR3 - port map(A => walk_use_0, B => \data[25]\, C => N_3162, Y - => N_2675); - - \r.s2_data_RNIN15R1[30]\ : OR3 - port map(A => walk_use_0, B => \data[30]\, C => N_3162, Y - => N_2604); - - \r.walk_use_RNI7A3P\ : OR2 - port map(A => \un1_acc[33]\, B => \walk_use\, Y => N_3069); - - \r.walk_transdata.data[29]\ : DFN1E0 - port map(D => N_331, CLK => lclk_c, E => N_6_i, Q => - \data[29]\); - - \r.s2_entry_RNIAPBJ1[0]\ : MX2 - port map(A => N_830, B => N_932, S => \s2_entry[0]\, Y => - adata_30); - - \r.s2_entry_3[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_3[2]\); - - \r.walk_transdata.data_RNO[21]\ : MX2 - port map(A => hrdata_0_16, B => \data[21]\, S => - lvl_i_1_0(1), Y => N_687); - - \r.walk_transdata.data[12]\ : DFN1E0 - port map(D => N_2621, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[12]\); - - \r.walk_fault.fault_pri_RNIN58G6\ : OAI1 - port map(A => fault_pri_6_m, B => fault_pri_m, C => - fault_isid_1_i(0), Y => fault_pri_m_0); - - \r.walk_transdata.data_RNO[26]\ : MX2 - port map(A => \data[26]\, B => hrdata_0_21, S => \N_2571\, - Y => N_2730); - - \r.walk_fault.fault_mexc_RNO_0\ : AO1A - port map(A => fault_mexc_1_sqmuxa_1_0_i_i_a2_0, B => - N_2563_i, C => N_573, Y => N_175); - - \r.s2_entry_RNISPEJ1[0]\ : MX2 - port map(A => N_824, B => N_926, S => \s2_entry[0]\, Y => - \adata[24]\); - - \r.s2_entry_RNISCSJ1[0]\ : OR2B - port map(A => \un1_acc[33]\, B => \un1_acc[32]\, Y => - N_3162); - - \r.s2_data_RNIRRTP[21]\ : OR3A - port map(A => \un1_acc[33]\, B => \walk_use\, C => - \data[21]\, Y => N_3022); - - \r.s2_data[4]\ : DFN1E1 - port map(D => address(4), CLK => lclk_c, E => s1finished, Q - => \data[4]\); - - \r.s2_data_RNIOD5R1[13]\ : OR3A - port map(A => N_554, B => walk_use_0, C => \data[13]\, Y - => N_2664); - - \r.s2_data[21]\ : DFN1E1 - port map(D => address(21), CLK => lclk_c, E => s1finished, - Q => \data[21]\); - - \r.sync_isw_RNO_0\ : NOR2A - port map(A => rst, B => hrdata_5, Y => - sync_isw_1_i_i_a2_0_0); - - \r.s2_entry_RNIIPCJ1[0]\ : MX2 - port map(A => N_831, B => N_933, S => \s2_entry[0]\, Y => - adata_31); - - \r.s2_data_RNIUA2E[23]\ : MX2C - port map(A => address(23), B => \data[23]\, S => s2_flush, - Y => N_620); - - \r.walk_use_0_RNIEO2T2\ : OR3 - port map(A => N_554, B => walk_use_0, C => \adata[10]\, Y - => N_2669); - - \r.s2_entry_0_RNIR5O21[0]\ : MX2 - port map(A => N_816, B => N_918, S => \s2_entry_0[0]\, Y - => \adata[16]\); - - \r.s2_data[24]\ : DFN1E1 - port map(D => address(24), CLK => lclk_c, E => s1finished, - Q => \data[24]\); - - \r.walk_fault.fault_inv_RNITG2F3\ : OR3C - port map(A => walk_use_0, B => fault_inv, C => - fault_isid_1_i(0), Y => fault_inv_m); - - \r.s2_tlbstate_RNI1PHJN_0[1]\ : OR3B - port map(A => \s2_tlbstate[0]\, B => N_2563_i, C => - \s2_tlbstate[1]\, Y => N_6_i_0); - - \r.s2_entry_0_RNIVBME[1]\ : MX2 - port map(A => N_734, B => N_768, S => \s2_entry_0[1]\, Y - => N_802); - - \r.s2_data_RNIBB6Q1[20]\ : MX2C - port map(A => \adata[16]\, B => \data[20]\, S => - \un1_acc[33]\, Y => N_630); - - \r.s2_ctx[3]\ : DFN1E1 - port map(D => ctx(3), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[3]\); - - \r.s2_entry_0_RNI35O21[0]\ : MX2 - port map(A => N_813, B => N_915, S => \s2_entry_0[0]\, Y - => \adata[13]\); - - \r.walk_transdata.data_RNI8FPD[5]\ : MX2C - port map(A => \data[5]\, B => \data_0[5]\, S => walk_use_1, - Y => un1_m0_3); - - \r.s2_entry_0_RNIRH7RQ2_7[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_1[3]\); - - \r.s2_entry_0_RNIR3O21[0]\ : MX2 - port map(A => N_808, B => N_910, S => \s2_entry_0[0]\, Y - => \adata[8]\); - - \r.s2_entry_RNI74DA[1]\ : MX2 - port map(A => N_736, B => N_770, S => \s2_entry[1]\, Y => - N_804); - - \r.s2_data_RNI0ACI5[26]\ : OR3C - port map(A => N_2988, B => N_2989, C => N_2990, Y => N_361); - - \tlbcam0.3.tag0\ : mmutlbcam_0_0_7 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1(3) => \tlbcam_write_op_1[3]\, - tlbcam_write_op_1_1(3) => \tlbcam_write_op_1_1[3]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_24 => - hrdata_24, hrdata_23 => hrdata_23, hrdata_22 => hrdata_22, - hrdata_21 => hrdata_21, hrdata_18 => hrdata_18, hrdata_17 - => hrdata_17, hrdata_16 => hrdata_16, hrdata_15 => - hrdata_15, hrdata_14 => hrdata_14, hrdata_13 => hrdata_13, - hrdata_12 => hrdata_12, hrdata_11 => hrdata_11, hrdata_10 - => hrdata_10, hrdata_9 => hrdata_9, hrdata_8 => hrdata_8, - hrdata_1 => hrdata_1, hrdata_0 => hrdata_0_d0, hrdata_7 - => hrdata_7, hrdata_6 => hrdata_6, s2_entry(2) => - \s2_entry[2]\, tlbcam_write_op_1_0(3) => - \tlbcam_write_op_1_0[3]\, LVL_0(1) => \LVL_1[1]\, - LVL_0(0) => \LVL_1[0]\, s2_entry_5(2) => \s2_entry_5[2]\, - s2_entry_4(2) => \s2_entry_4[2]\, pteout_0_7 => - \pteout_1[7]\, pteout_0_4 => \pteout_1[4]\, pteout_0_17 - => \pteout_1[17]\, pteout_0_18 => \pteout_1[18]\, - pteout_0_11 => \pteout_1[11]\, pteout_0_31 => - \pteout_1[31]\, pteout_0_30 => \pteout_1[30]\, - pteout_0_29 => \pteout_1[29]\, pteout_0_28 => - \pteout_1[28]\, pteout_0_27 => \pteout_1[27]\, - pteout_0_26 => \pteout_1[26]\, pteout_0_25 => - \pteout_1[25]\, pteout_0_24 => \pteout_1[24]\, - pteout_0_23 => \pteout_1[23]\, pteout_0_22 => - \pteout_1[22]\, pteout_0_21 => \pteout_1[21]\, - pteout_0_20 => \pteout_1[20]\, pteout_0_19 => - \pteout_1[19]\, pteout_0_16 => \pteout_1[16]\, - pteout_0_15 => \pteout_1[15]\, pteout_0_14 => - \pteout_1[14]\, pteout_0_13 => \pteout_1[13]\, - pteout_0_12 => \pteout_1[12]\, pteout_0_10 => - \pteout_1[10]\, pteout_0_9 => \pteout_1[9]\, pteout_0_8 - => \pteout_1[8]\, pteout_0_6 => \pteout_1[6]\, - pteout_0_3 => \pteout_1[3]\, pteout_0_2 => \pteout_1[2]\, - pteout_0_1 => \pteout_1[1]\, pteout_0_0 => \pteout_1[0]\, - ctx(6) => ctx(6), ctx_0_5 => ctx_0(5), ctx_0_4 => - ctx_0(4), ctx_0_3 => ctx_0(3), ctx_0_1 => ctx_0(1), - ctx_0_0 => ctx_0(0), ctx_0_2 => ctx_0(2), ctx_0_7 => - ctx_0(7), N_78 => N_78, N_262 => N_262, N_264 => N_264, - N_2482 => N_2482, lclk_c => lclk_c, C_RNIL004 => - C_RNIL004, N_872 => N_872, N_885 => N_885, N_886 => N_886, - N_879 => N_879, N_901 => N_901, s2_flush => s2_flush, - un1_rst_i_0 => un1_rst_i_0, N_900 => N_900, N_200 => - N_200, N_596 => N_596, N_594 => N_594, N_593 => N_593, - N_597 => N_597, N_665 => N_665, N_899 => N_899, N_898 => - N_898, N_897 => N_897, N_896 => N_896, N_895 => N_895, - N_894 => N_894, N_893 => N_893, N_892 => N_892, N_891 => - N_891, N_890 => N_890, N_889 => N_889, N_888 => N_888, - N_887 => N_887, N_884 => N_884, N_883 => N_883, N_882 => - N_882, N_881 => N_881, N_880 => N_880, N_878 => N_878, - N_877 => N_877, N_876 => N_876, N_874 => N_874, N_871 => - N_871, N_870 => N_870, N_869 => N_869, N_868 => N_868, - N_634 => N_634, N_632 => N_632, N_662 => N_662, N_639 => - N_639, N_635 => N_635, hit_0_a3_0 => hit_0_a3_0, N_204 - => N_204, N_42 => N_42, hit => hit, N_631_i => N_631_i, - N_633 => N_633, N_595 => N_595, N_663 => N_663, N_664 => - N_664, N_651 => N_651, N_612 => N_612, N_200_0 => N_200_0, - N_617 => N_617, N_650 => N_650, N_620 => N_620, N_170_1 - => N_170_1); - - \r.s2_tlbstate_RNIE7NKQ2_0[1]\ : NOR2 - port map(A => N_86_i, B => N_6_i_0, Y => - dr1write_0_sqmuxa_0); - - \r.s2_tlbstate_RNI1OCD[1]\ : NOR2A - port map(A => tlbactive, B => \s2_tlbstate[1]\, Y => N_555); - - \r.s2_entry_1_RNI8L2Q[1]\ : MX2 - port map(A => N_856, B => N_890, S => \s2_entry_1[1]\, Y - => N_924); - - \r.s2_entry_0[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_0[2]\); - - \r.s2_data_RNIP2AM4[15]\ : OR3C - port map(A => N_2981, B => N_2982, C => N_2983, Y => N_357); - - \r.s2_ctx[7]\ : DFN1E1 - port map(D => ctx(7), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[7]\); - - \r.s2_data_RNIN9QC[12]\ : MX2C - port map(A => address(12), B => \data[12]\, S => s2_flush_0, - Y => N_631_i); - - \r.s2_ctx[2]\ : DFN1E1 - port map(D => ctx(2), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[2]\); - - \r.nrep_RNO[2]\ : XA1A - port map(A => \nrep[2]\, B => nrep_494_0, C => rst, Y => - nrep_n2); - - \r.s2_tlbstate_RNISOV11[0]\ : OR2B - port map(A => N_572, B => N_553, Y => s2_entry_0_sqmuxa); - - \r.walk_fault.fault_mexc_RNI5S7A3\ : OR3C - port map(A => walk_use_0, B => fault_mexc, C => - fault_isid_1_i(0), Y => fault_mexc_m); - - \r.s2_entry_0_RNIU0KN1[0]\ : MX2 - port map(A => N_821, B => N_923, S => \s2_entry_0[0]\, Y - => \adata[21]\); - - \r.s2_entry_0_RNIJ5O21[0]\ : MX2 - port map(A => N_815, B => N_917, S => \s2_entry_0[0]\, Y - => \adata[15]\); - - \tlbcam0.6.tag0\ : mmutlbcam_0_0_1 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0_17 => - hrdata_0_23, hrdata_0_10 => hrdata_0_16, hrdata_0_7 => - hrdata_0_13, hrdata_0_6 => hrdata_0_12, hrdata_0_4 => - hrdata_0_10, hrdata_0_3 => hrdata_0_9, hrdata_0_2 => - hrdata_0_8, hrdata_0_0 => hrdata_0_6, - tlbcam_write_op_1(6) => \tlbcam_write_op_1[6]\, - tlbcam_write_op_1_1_0(6) => \tlbcam_write_op_1_1_0[6]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 - => hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => - hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 => - hrdata_0_d0, hrdata_6 => hrdata_6, pteout_4 => - \pteout_0[4]\, pteout_3 => \pteout_0[3]\, pteout_2 => - \pteout_0[2]\, pteout_31 => \pteout_0[31]\, pteout_30 => - \pteout_0[30]\, pteout_29 => \pteout_0[29]\, pteout_28 - => \pteout_0[28]\, pteout_27 => \pteout_0[27]\, - pteout_26 => \pteout_0[26]\, pteout_25 => \pteout_0[25]\, - pteout_24 => \pteout_0[24]\, pteout_23 => \pteout_0[23]\, - pteout_22 => \pteout_0[22]\, pteout_21 => \pteout_0[21]\, - pteout_20 => \pteout_0[20]\, pteout_19 => \pteout_0[19]\, - pteout_18 => \pteout_0[18]\, pteout_17 => \pteout_0[17]\, - pteout_16 => \pteout_0[16]\, pteout_15 => \pteout_0[15]\, - pteout_14 => \pteout_0[14]\, pteout_13 => \pteout_0[13]\, - pteout_12 => \pteout_0[12]\, pteout_11 => \pteout_0[11]\, - pteout_10 => \pteout_0[10]\, pteout_9 => \pteout_0[9]\, - pteout_8 => \pteout_0[8]\, pteout_1 => \pteout_0[1]\, - pteout_0 => \pteout_0[0]\, pteout_7 => \pteout_0[7]\, - pteout_6 => \pteout_0[6]\, s2_entry_5(2) => - \s2_entry_5[2]\, LVL_0(0) => \LVL_0[0]\, - tlbcam_write_op_1_0(6) => \tlbcam_write_op_1_0[6]\, - ctx_0(7) => ctx_0(7), ctx_0(6) => ctx_0(6), ctx_0(5) => - ctx_0(5), ctx_0(4) => ctx_0(4), ctx_0(3) => ctx_0(3), - ctx_0(2) => ctx_0(2), ctx_0(1) => ctx_0(1), ctx_0(0) => - ctx_0(0), LVL_1 => \LVL_0[1]\, s2_entry_1_i_a2_1_2(1) => - \s2_entry_1_i_a2_1_2[1]\, N_78_0 => N_78_0, N_262_0 => - N_262_0, N_264_0 => N_264_0, N_2482 => N_2482, lclk_c => - lclk_c, N_635 => N_635, N_639 => N_639, N_665 => N_665, - N_597 => N_597, N_798 => N_798, N_632 => N_632, N_634 => - N_634, N_596 => N_596, un1_rst_i_0 => un1_rst_i_0, N_620 - => N_620, N_594 => N_594, N_593 => N_593, s2_flush_0 => - s2_flush_0, hit_0_a3_0 => hit_0_a3_0, N_42 => N_42, N_200 - => N_200, N_204 => N_204, N_631_i => N_631_i, N_633 => - N_633, N_595 => N_595, N_663 => N_663, N_664 => N_664, - N_651 => N_651, N_612 => N_612, N_200_0 => N_200_0, N_617 - => N_617, N_650 => N_650, N_662 => N_662, N_170_1 => - N_170_1); - - \r.s2_hm_RNO_0\ : NOR3C - port map(A => hit_i_0, B => cam_hit_all_1_2, C => hit_i, Y - => cam_hit_all_1_4); - - \r.s2_entry_RNIVK8T[0]\ : MX2 - port map(A => N_832, B => N_934, S => \s2_entry[0]\, Y => - \un1_acc[32]\); - - \r.walk_fault.fault_trans_RNIA0K0D1\ : OR2B - port map(A => fault_mexc_3_0, B => \N_1629\, Y => - fault_trans_RNIA0K0D1); - - \r.s2_entry_RNI8CLB[1]\ : MX2 - port map(A => N_765, B => N_799, S => \s2_entry[1]\, Y => - N_833); - - \r.walk_fault.fault_pri\ : DFN1E1 - port map(D => N_206, CLK => lclk_c, E => N_198, Q => - fault_pri); - - \r.s2_data_RNIRL5R1[15]\ : OR3A - port map(A => N_554, B => walk_use_1, C => \data[15]\, Y - => N_2981); - - \r.s2_flush_0\ : DFN1E1 - port map(D => s2_flush_1, CLK => lclk_c, E => un1_rst_2, Q - => s2_flush_0); - - \r.s2_data_RNIFO9D[8]\ : OR2B - port map(A => \data[8]\, B => s2_flush_0, Y => N_200_0); - - \r.walk_transdata.data[19]\ : DFN1E0 - port map(D => N_636, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[19]\); - - \r.s2_entry_RNICQGJ1[0]\ : MX2 - port map(A => N_826, B => N_928, S => \s2_entry[0]\, Y => - \adata[26]\); - - \r.s2_entry_0_RNIRH7RQ2_9[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => - \tlbcam_write_op_1_1[2]\); - - \r.s2_data_RNIS22E[30]\ : MX2C - port map(A => address(30), B => \data[30]\, S => s2_flush, - Y => N_612); - - \r.walk_transdata.data_RNO[22]\ : MX2 - port map(A => hrdata_0_17, B => \data_0[22]\, S => - lvl_i_1_0(1), Y => N_688); - - \r.s2_data[8]\ : DFN1E1 - port map(D => address(8), CLK => lclk_c, E => s1finished, Q - => \data[8]\); - - \r.walk_transdata.data_RNI6QQ9[3]\ : MX2C - port map(A => \data[3]\, B => \data_0[3]\, S => \walk_use\, - Y => un1_m0_1); - - \r.s2_entry_0_RNIQEHF[1]\ : MX2 - port map(A => N_747, B => N_781, S => \s2_entry_0[1]\, Y - => N_815); - - \r.s2_entry_0_RNIG3E31[0]\ : MX2 - port map(A => N_806, B => N_908, S => \s2_entry_0[0]\, Y - => adata_6); - - \r.walk_transdata.data_RNI4DV9[11]\ : MX2C - port map(A => \data[11]\, B => \data_0[11]\, S => - \walk_use\, Y => un1_m0_9); - - \r.walk_fault.fault_lvl[1]\ : DFN1E0 - port map(D => N_82, CLK => lclk_c, E => N_6_i_0, Q => - fault_lvl_1); - - \r.walk_transdata.data[2]\ : DFN1E0 - port map(D => \data[2]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[2]\); - - \r.s2_data[11]\ : DFN1E1 - port map(D => address(11), CLK => lclk_c, E => - \s1finished_0\, Q => \data[11]\); - - \r.s2_entry_RNIT9U93[0]\ : OR2 - port map(A => \adata[27]\, B => N_3064, Y => N_2995); - - \r.s2_entry_0_RNIE4VP[1]\ : MX2 - port map(A => N_753, B => N_787, S => \s2_entry_0[1]\, Y - => N_821); - - \r.s2_data_RNI2H7N1[29]\ : OR2A - port map(A => N_3061, B => \data_0[29]\, Y => N_2994); - - \r.s2_data[14]\ : DFN1E1 - port map(D => address(14), CLK => lclk_c, E => - \s1finished_0\, Q => \data_0[14]\); - - \r.s2_data_RNIGHHE[8]\ : OR2B - port map(A => \data[8]\, B => s2_flush, Y => N_200); - - \r.s2_entry_RNIN10O[1]\ : MX2 - port map(A => N_859, B => N_893, S => \s2_entry[1]\, Y => - N_927); - - \r.nrep_RNITQLUT4[2]\ : MX2 - port map(A => \nrep[2]\, B => \cam_hitaddr_12[2]\, S => - N_557, Y => \s2_entry_1[2]\); - - \r.walk_transdata.data_RNO[31]\ : MX2 - port map(A => \data_0[31]\, B => hrdata_0_26, S => \N_2571\, - Y => N_70); - - \r.walk_transdata.data_RNO[15]\ : MX2 - port map(A => hrdata_0_10, B => \data[15]\, S => N_3160, Y - => N_17); - - \r.walk_transdata.data_RNO[24]\ : MX2 - port map(A => \data[24]\, B => N_262_0, S => \N_2571\, Y - => N_2728); - - \r.s2_data[30]\ : DFN1E1 - port map(D => address(30), CLK => lclk_c, E => s1finished, - Q => \data[30]\); - - \r.s2_su_RNIEO413\ : NOR3C - port map(A => \adata[3]\, B => fault_pri_6_m_1, C => - \adata[4]\, Y => fault_pri_6_m); - - \p0.transdata.data_1_i[23]\ : NAND2 - port map(A => N_2987, B => \data_1_i_0[23]\, Y => N_359); - - \r.s2_entry_1_RNICKUP[1]\ : MX2 - port map(A => N_760, B => N_794, S => \s2_entry_1[1]\, Y - => N_828); - - \r.s2_entry_1_RNILUJF[1]\ : MX2 - port map(A => N_843, B => N_877, S => \s2_entry_1[1]\, Y - => N_911); - - \r.s2_tlbstate_RNILJJC_1[1]\ : NOR2 - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => N_2917); - - \r.walk_use_RNI6VBM1_0\ : NOR2 - port map(A => \walk_use\, B => N_3162, Y => N_3061); - - \r.s2_entry_0_RNIVM7B[1]\ : MX2 - port map(A => N_749, B => N_783, S => \s2_entry_0[1]\, Y - => N_817); - - \r.s2_entry_0_RNIRH7RQ2_10[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => - \tlbcam_write_op_1_1_0[0]\); - - \r.s2_entry[1]\ : DFN1E1 - port map(D => N_212_i_0, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry[1]\); - - \r.s2_data_RNIN5QC[20]\ : MX2C - port map(A => address(20), B => \data[20]\, S => s2_flush_0, - Y => N_650); - - \r.s2_data_RNI4MB55[12]\ : OR3C - port map(A => N_2661, B => N_2662, C => N_2663, Y => N_2623); - - \r.s2_entry_0_RNIRH7RQ2_5[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => - \tlbcam_write_op_1_0[6]\); - - \r.s2_data[23]\ : DFN1E1 - port map(D => address(23), CLK => lclk_c, E => s1finished, - Q => \data[23]\); - - \r.walk_transdata.data_RNINC4D[28]\ : OR2A - port map(A => walk_use_1, B => \data[28]\, Y => N_2969); - - \r.nrep[1]\ : DFN1E1 - port map(D => nrep_n1, CLK => lclk_c, E => nrepe, Q => - \nrep[1]\); - - \r.s2_entry_RNIJHVN[1]\ : MX2 - port map(A => N_858, B => N_892, S => \s2_entry[1]\, Y => - N_926); - - \r.walk_transdata.data_RNO[27]\ : MX2 - port map(A => \data[27]\, B => hrdata_0_22, S => \N_2571\, - Y => N_2731); - - \r.s2_data[27]\ : DFN1E1 - port map(D => address(27), CLK => lclk_c, E => s1finished, - Q => \data[27]\); - - \r.walk_transdata.data[9]\ : DFN1E0 - port map(D => \data[9]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[9]\); - - \r.walk_transdata.data[30]\ : DFN1E0 - port map(D => N_2554, CLK => lclk_c, E => N_6_i, Q => - \data_0[30]\); - - \r.s2_entry_RNI6J39[1]\ : MX2 - port map(A => N_851, B => N_885, S => \s2_entry[1]\, Y => - N_919); - - \r.s2_entry_RNI31TN[1]\ : MX2 - port map(A => N_863, B => N_897, S => \s2_entry[1]\, Y => - N_931); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu is - - port( ctxp : in std_logic_vector(25 downto 0); - iosn_0 : in std_logic_vector(93 to 93); - data_0 : out std_logic; - data_1_d0 : out std_logic; - data_2_d0 : out std_logic; - data_3 : out std_logic; - data_4 : out std_logic; - data_6 : out std_logic; - data_7 : out std_logic; - data_8 : out std_logic; - data_9 : out std_logic; - data_10 : out std_logic; - data_11 : out std_logic; - data_2 : out std_logic_vector(31 downto 12); - data_RNIKU1T4 : out std_logic_vector(16 to 16); - maddress : in std_logic_vector(31 downto 12); - data_1 : in std_logic_vector(31 downto 12); - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - data_1_3_i_a3_6_2 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_0 : out std_logic; - hrdata_5 : in std_logic; - hrdata_7 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - hrdata_24 : in std_logic; - hrdata_17 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_7 : in std_logic; - address_0 : in std_logic_vector(31 downto 2); - un1_m0_2_d0 : out std_logic; - un1_m0_3 : out std_logic; - un1_m0_4 : out std_logic; - un1_m0_7 : out std_logic; - un1_m0_16 : out std_logic; - un1_m0_17 : out std_logic; - un1_m0_0 : out std_logic; - un1_m0_6 : out std_logic; - un1_m0_22 : out std_logic; - un1_m0_1 : out std_logic; - un1_m0_5 : out std_logic; - un1_m0_8 : out std_logic; - un1_m0_9 : out std_logic; - un1_m0_30 : out std_logic; - ctx : in std_logic_vector(7 downto 0); - ctx_0 : in std_logic_vector(7 downto 0); - address : out std_logic_vector(31 downto 2); - hrdata_1_0_1 : in std_logic_vector(1 to 1); - un1_m0_2_23 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_31 : out std_logic; - un1_m0_2_33 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_5 : out std_logic; - un1_m0_2_6 : out std_logic; - un1_m0_2_8 : out std_logic; - un1_m0_2_11 : out std_logic; - un1_m0_2_12 : out std_logic; - un1_m0_2_18 : out std_logic; - un1_m0_2_29 : out std_logic; - un1_m0_2_19 : out std_logic; - un1_m0_2_9 : out std_logic; - un1_m0_2_10 : out std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_75 : in std_logic; - un1_m0_2_76 : in std_logic; - un1_m0_2_77 : in std_logic; - un1_m0_2_78 : in std_logic; - un1_m0_2_79 : in std_logic; - un1_m0_2_80 : in std_logic; - un1_m0_2_81 : in std_logic; - un1_m0_2_82 : in std_logic; - un1_m0_2_83 : in std_logic; - un1_m0_2_84 : in std_logic; - un1_m0_2_85 : in std_logic; - un1_m0_2_86 : in std_logic; - un1_m0_2_97 : out std_logic; - un1_m0_2_96 : out std_logic; - un1_m0_2_95 : out std_logic; - un1_m0_2_93 : out std_logic; - un1_m0_2_108 : out std_logic; - un1_m0_2_91 : out std_logic; - un1_m0_2_106 : out std_logic; - un1_m0_2_92 : out std_logic; - un1_m0_2_98 : out std_logic; - un1_m0_2_94 : out std_logic; - un1_m0_2_44 : out std_logic; - un1_m0_2_43 : out std_logic; - un1_m0_2_73 : out std_logic; - un1_m0_2_72 : out std_logic; - un1_m0_2_71 : out std_logic; - un1_m0_2_70 : out std_logic; - un1_m0_2_69 : out std_logic; - un1_m0_2_68 : out std_logic; - un1_m0_2_67 : out std_logic; - un1_m0_2_66 : out std_logic; - un1_m0_2_65 : out std_logic; - un1_m0_2_64 : out std_logic; - un1_m0_2_63 : out std_logic; - un1_m0_2_62 : out std_logic; - un1_m0_2_61 : out std_logic; - un1_m0_2_60 : out std_logic; - un1_m0_2_59 : out std_logic; - un1_m0_2_58 : out std_logic; - un1_m0_2_57 : out std_logic; - un1_m0_2_56 : out std_logic; - un1_m0_2_55 : out std_logic; - un1_m0_2_54 : out std_logic; - un1_m0_2_40 : out std_logic; - un1_m0_2_42 : out std_logic; - un1_m0_2_35 : out std_logic; - un1_m0_2_36 : out std_logic; - un1_m0_2_34 : out std_logic; - un1_m0_2_39 : out std_logic; - un1_m0_2_38 : out std_logic; - un1_m0_2_37 : out std_logic; - un1_m0_2_0_d0 : out std_logic; - un1_m0_2_41 : out std_logic; - fault_isid_1_i : out std_logic_vector(0 to 0); - un1_m0_2_0 : out std_logic_vector(35 to 35); - mexc : in std_logic; - req : out std_logic; - ba : in std_logic; - bo_5842_d_0 : in std_logic; - read_0 : out std_logic; - grant : in std_logic; - su_0 : in std_logic; - read : in std_logic; - N_421 : out std_logic; - N_419 : out std_logic; - N_417 : out std_logic; - N_415 : out std_logic; - N_353 : out std_logic; - N_351 : out std_logic; - N_317 : out std_logic; - N_293 : out std_logic; - N_236 : out std_logic; - N_192 : out std_logic; - N_190 : out std_logic; - N_2887 : out std_logic; - N_2886 : out std_logic; - N_2701 : out std_logic; - fault_pro67 : out std_logic; - M_m : out std_logic; - e : in std_logic; - N_2720 : out std_logic; - N_2717 : out std_logic; - N_2714 : out std_logic; - G_80_0 : out std_logic; - N_2703_i_0 : out std_logic; - N_2699_i_0 : out std_logic; - un54_fault_pro_m : out std_logic; - accexc_6 : out std_logic; - fault_pro : out std_logic; - fault_pri_0 : out std_logic; - N_2709_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2702_i_0 : out std_logic; - N_696 : out std_logic; - N_695 : out std_logic; - N_694 : out std_logic; - N_359 : out std_logic; - N_357 : out std_logic; - N_365 : out std_logic; - N_363 : out std_logic; - N_361 : out std_logic; - N_321 : out std_logic; - N_319 : out std_logic; - N_45 : out std_logic; - N_2624 : out std_logic; - N_2623 : out std_logic; - N_425 : out std_logic; - N_423 : out std_logic; - N_43 : out std_logic; - N_2626 : out std_logic; - N_427 : out std_logic; - N_429 : out std_logic; - N_262_0 : in std_logic; - N_78_0 : in std_logic; - N_264_0 : in std_logic; - tlbdis : in std_logic; - N_2625 : out std_logic; - su : in std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - mmu_VCC : in std_logic; - fsread_i_0 : in std_logic; - trans_op_2 : in std_logic; - flush_op_i_0 : in std_logic; - mmudci_trans_op_1_sqmuxa_1 : in std_logic; - N_66 : out std_logic; - trans_op_1 : in std_logic; - un2_m_tlb_type : out std_logic; - flush : out std_logic; - trans_op : in std_logic; - istate_0_sqmuxa : in std_logic; - un81_m_tlb_type : out std_logic; - rst : in std_logic; - N_546 : in std_logic; - N_66_0 : out std_logic; - fault_trans_RNIA0K0D1 : out std_logic; - lclk_c : in std_logic - ); - -end mmu; - -architecture DEF_ARCH of mmu is - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutw - port( data_1 : out std_logic_vector(31 downto 12); - address : out std_logic_vector(31 downto 2); - twowner : in std_logic_vector(0 to 0) := (others => 'U'); - twowner_2 : in std_logic_vector(0 to 0) := (others => 'U'); - aaddr_0_25 : in std_logic := 'U'; - aaddr_0_24 : in std_logic := 'U'; - aaddr_0_29 : in std_logic := 'U'; - aaddr_0_18 : in std_logic := 'U'; - aaddr_0_17 : in std_logic := 'U'; - aaddr_0_9 : in std_logic := 'U'; - aaddr_0_8 : in std_logic := 'U'; - aaddr_0_7 : in std_logic := 'U'; - aaddr_0_4 : in std_logic := 'U'; - aaddr_0_0 : in std_logic := 'U'; - aaddr_0_21 : in std_logic := 'U'; - aaddr_0_22 : in std_logic := 'U'; - aaddr_0_23 : in std_logic := 'U'; - aaddr_0_28 : in std_logic := 'U'; - aaddr_0_27 : in std_logic := 'U'; - aaddr_0_26 : in std_logic := 'U'; - aaddr_0_20 : in std_logic := 'U'; - aaddr_0_19 : in std_logic := 'U'; - aaddr_0_16 : in std_logic := 'U'; - aaddr_0_15 : in std_logic := 'U'; - aaddr_0_14 : in std_logic := 'U'; - aaddr_0_13 : in std_logic := 'U'; - aaddr_0_12 : in std_logic := 'U'; - aaddr_0_11 : in std_logic := 'U'; - aaddr_0_10 : in std_logic := 'U'; - aaddr_0_6 : in std_logic := 'U'; - aaddr_0_3 : in std_logic := 'U'; - aaddr_0_2 : in std_logic := 'U'; - aaddr_0_1 : in std_logic := 'U'; - aaddr_25 : in std_logic := 'U'; - aaddr_24 : in std_logic := 'U'; - aaddr_29 : in std_logic := 'U'; - aaddr_18 : in std_logic := 'U'; - aaddr_17 : in std_logic := 'U'; - aaddr_9 : in std_logic := 'U'; - aaddr_8 : in std_logic := 'U'; - aaddr_7 : in std_logic := 'U'; - aaddr_4 : in std_logic := 'U'; - aaddr_0_d0 : in std_logic := 'U'; - aaddr_21 : in std_logic := 'U'; - aaddr_22 : in std_logic := 'U'; - aaddr_23 : in std_logic := 'U'; - aaddr_28 : in std_logic := 'U'; - aaddr_27 : in std_logic := 'U'; - aaddr_26 : in std_logic := 'U'; - aaddr_20 : in std_logic := 'U'; - aaddr_19 : in std_logic := 'U'; - aaddr_16 : in std_logic := 'U'; - aaddr_15 : in std_logic := 'U'; - aaddr_14 : in std_logic := 'U'; - aaddr_13 : in std_logic := 'U'; - aaddr_12 : in std_logic := 'U'; - aaddr_11 : in std_logic := 'U'; - aaddr_10 : in std_logic := 'U'; - aaddr_6 : in std_logic := 'U'; - aaddr_3 : in std_logic := 'U'; - aaddr_2 : in std_logic := 'U'; - aaddr_1 : in std_logic := 'U'; - twowner_1 : in std_logic_vector(0 to 0) := (others => 'U'); - data_0 : in std_logic_vector(31 downto 12) := (others => 'U'); - data_11 : out std_logic; - data_10 : out std_logic; - data_9 : out std_logic; - data_8 : out std_logic; - data_7 : out std_logic; - data_6 : out std_logic; - data_4 : out std_logic; - data_3 : out std_logic; - data_2 : out std_logic; - data_1_d0 : out std_logic; - data_0_d0 : out std_logic; - data_12 : in std_logic := 'U'; - data_18 : in std_logic := 'U'; - data_24 : in std_logic := 'U'; - data_16 : in std_logic := 'U'; - data_22 : in std_logic := 'U'; - data_28 : in std_logic := 'U'; - data_20 : in std_logic := 'U'; - data_26 : in std_logic := 'U'; - data_17 : in std_logic := 'U'; - data_15 : in std_logic := 'U'; - data_14 : in std_logic := 'U'; - data_13 : in std_logic := 'U'; - data_23 : in std_logic := 'U'; - data_29 : in std_logic := 'U'; - data_30 : in std_logic := 'U'; - data_31 : in std_logic := 'U'; - data_21 : in std_logic := 'U'; - data_27 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - data_25 : in std_logic := 'U'; - adata_0_19 : in std_logic := 'U'; - adata_0_20 : in std_logic := 'U'; - adata_0_18 : in std_logic := 'U'; - adata_0_10 : in std_logic := 'U'; - adata_0_2 : in std_logic := 'U'; - adata_0_13 : in std_logic := 'U'; - adata_0_14 : in std_logic := 'U'; - adata_0_30 : in std_logic := 'U'; - adata_0_29 : in std_logic := 'U'; - adata_0_28 : in std_logic := 'U'; - adata_0_6 : in std_logic := 'U'; - adata_0_1 : in std_logic := 'U'; - adata_0_0 : in std_logic := 'U'; - adata_0_31 : in std_logic := 'U'; - adata_0_17 : in std_logic := 'U'; - adata_0_7 : in std_logic := 'U'; - adata_0_25 : in std_logic := 'U'; - adata_0_22 : in std_logic := 'U'; - adata_0_11 : in std_logic := 'U'; - adata_0_24 : in std_logic := 'U'; - adata_0_23 : in std_logic := 'U'; - adata_0_15 : in std_logic := 'U'; - adata_0_12 : in std_logic := 'U'; - adata_0_21 : in std_logic := 'U'; - adata_0_16 : in std_logic := 'U'; - adata_0_9 : in std_logic := 'U'; - adata_0_8 : in std_logic := 'U'; - adata_0_26 : in std_logic := 'U'; - adata_0_27 : in std_logic := 'U'; - adata_0_4 : in std_logic := 'U'; - adata_0_3 : in std_logic := 'U'; - adata_19 : in std_logic := 'U'; - adata_20 : in std_logic := 'U'; - adata_18 : in std_logic := 'U'; - adata_10 : in std_logic := 'U'; - adata_2 : in std_logic := 'U'; - adata_13 : in std_logic := 'U'; - adata_14 : in std_logic := 'U'; - adata_30 : in std_logic := 'U'; - adata_29 : in std_logic := 'U'; - adata_28 : in std_logic := 'U'; - adata_6 : in std_logic := 'U'; - adata_1 : in std_logic := 'U'; - adata_0_d0 : in std_logic := 'U'; - adata_31 : in std_logic := 'U'; - adata_17 : in std_logic := 'U'; - adata_7 : in std_logic := 'U'; - adata_25 : in std_logic := 'U'; - adata_22 : in std_logic := 'U'; - adata_11 : in std_logic := 'U'; - adata_24 : in std_logic := 'U'; - adata_23 : in std_logic := 'U'; - adata_15 : in std_logic := 'U'; - adata_12 : in std_logic := 'U'; - adata_21 : in std_logic := 'U'; - adata_16 : in std_logic := 'U'; - adata_9 : in std_logic := 'U'; - adata_8 : in std_logic := 'U'; - adata_26 : in std_logic := 'U'; - adata_27 : in std_logic := 'U'; - adata_4 : in std_logic := 'U'; - adata_3 : in std_logic := 'U'; - twowner_0 : in std_logic_vector(0 to 0) := (others => 'U'); - lvl_i_1 : out std_logic_vector(1 downto 0); - ctx_0_d0 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_2 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_6 : in std_logic := 'U'; - ctx_7 : in std_logic := 'U'; - hrdata : in std_logic_vector(6 downto 5) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - ctx_0 : in std_logic_vector(5 downto 4) := (others => 'U'); - ctxp : in std_logic_vector(25 downto 0) := (others => 'U'); - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - lvl_i_1_0 : out std_logic_vector(1 to 1); - lclk_c : in std_logic := 'U'; - grant : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_82 : out std_logic; - N_80 : out std_logic; - N_709 : in std_logic := 'U'; - finish : out std_logic; - N_78_0 : in std_logic := 'U'; - d_N_6_1 : out std_logic; - N_2563_i_0_a4_m7_0_a2_1 : out std_logic; - fault_trans_i_2 : out std_logic; - walk_op_2_0_0_o2_0 : out std_logic; - N_2488 : in std_logic := 'U'; - N_2487 : in std_logic := 'U'; - read : out std_logic; - bo_5842_d_0 : in std_logic := 'U'; - ba : in std_logic := 'U'; - req : out std_logic; - inv_1_0_a2_0_a2_0 : out std_logic; - rst : in std_logic := 'U'; - mexc : in std_logic := 'U'; - fault_mexc : out std_logic; - N_2484 : in std_logic := 'U'; - N_2485 : in std_logic := 'U'; - N_207 : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component mmutlb_10_8_2_1_0 - port( aaddr : inout std_logic_vector(31 downto 2); - twowner_1 : in std_logic_vector(0 to 0) := (others => 'U'); - address : in std_logic_vector(31 downto 2) := (others => 'U'); - data_1_3_i_a3_6_0 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_2 : out std_logic; - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - fault_lvl : out std_logic_vector(1 downto 0); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - data_2_0 : in std_logic := 'U'; - lvl_i_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - data_1_17 : in std_logic := 'U'; - data_1_5 : out std_logic; - data_1_11 : in std_logic := 'U'; - data_1_10 : in std_logic := 'U'; - data_1_9 : in std_logic := 'U'; - data_1_8 : in std_logic := 'U'; - data_1_7 : in std_logic := 'U'; - data_1_4 : in std_logic := 'U'; - data_1_12 : in std_logic := 'U'; - data_1_15 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - maddress : in std_logic_vector(31 downto 12) := (others => 'U'); - twowner_0 : in std_logic_vector(0 to 0) := (others => 'U'); - data_RNIKU1T4 : out std_logic_vector(16 to 16); - un1_m0_2_94 : out std_logic; - un1_m0_2_98 : out std_logic; - un1_m0_2_92 : out std_logic; - un1_m0_2_106 : out std_logic; - un1_m0_2_91 : out std_logic; - un1_m0_2_108 : out std_logic; - un1_m0_2_93 : out std_logic; - un1_m0_2_95 : out std_logic; - un1_m0_2_96 : out std_logic; - un1_m0_2_97 : out std_logic; - un1_m0_2_86 : in std_logic := 'U'; - un1_m0_2_85 : in std_logic := 'U'; - un1_m0_2_84 : in std_logic := 'U'; - un1_m0_2_83 : in std_logic := 'U'; - un1_m0_2_82 : in std_logic := 'U'; - un1_m0_2_81 : in std_logic := 'U'; - un1_m0_2_80 : in std_logic := 'U'; - un1_m0_2_79 : in std_logic := 'U'; - un1_m0_2_78 : in std_logic := 'U'; - un1_m0_2_77 : in std_logic := 'U'; - un1_m0_2_76 : in std_logic := 'U'; - un1_m0_2_75 : in std_logic := 'U'; - un1_m0_2_7 : out std_logic; - un1_m0_2_10 : out std_logic; - un1_m0_2_9 : out std_logic; - un1_m0_2_0_d0 : out std_logic; - un1_m0_2_19 : out std_logic; - un1_m0_2_29 : out std_logic; - un1_m0_2_18 : out std_logic; - un1_m0_2_12 : out std_logic; - un1_m0_2_11 : out std_logic; - un1_m0_2_8 : out std_logic; - un1_m0_2_6 : out std_logic; - un1_m0_2_5 : out std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_33 : out std_logic; - un1_m0_2_31 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_23 : out std_logic; - data_0_18 : in std_logic := 'U'; - data_0_14 : in std_logic := 'U'; - data_0_22 : out std_logic; - data_0_21 : out std_logic; - data_0_20 : out std_logic; - data_0_19 : out std_logic; - data_0_23 : out std_logic; - data_0_16 : out std_logic; - data_0_28 : in std_logic := 'U'; - data_0_30 : in std_logic := 'U'; - data_0_26 : in std_logic := 'U'; - data_0_25 : in std_logic := 'U'; - data_0_15 : in std_logic := 'U'; - data_0_12 : in std_logic := 'U'; - data_0_31 : in std_logic := 'U'; - data_0_27 : out std_logic; - data_0_29 : out std_logic; - data_0_13 : out std_logic; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - un1_m0_2_0 : in std_logic_vector(35 to 35) := (others => 'U'); - ft_1_i_a2_0 : out std_logic_vector(0 to 0); - twowner_2_0_a2_0_0 : out std_logic_vector(0 to 0); - data_18 : out std_logic; - data_28 : out std_logic; - data_30 : out std_logic; - data_25 : out std_logic; - data_26 : out std_logic; - data_31 : out std_logic; - data_24 : out std_logic; - data_14 : out std_logic; - data_15 : out std_logic; - data_12 : out std_logic; - data_13 : in std_logic := 'U'; - adata_20 : out std_logic; - adata_13 : out std_logic; - adata_17 : out std_logic; - adata_31 : out std_logic; - adata_30 : out std_logic; - adata_29 : out std_logic; - adata_28 : out std_logic; - adata_26 : out std_logic; - adata_24 : out std_logic; - adata_19 : out std_logic; - adata_18 : out std_logic; - adata_16 : out std_logic; - adata_15 : out std_logic; - adata_14 : out std_logic; - adata_11 : out std_logic; - adata_8 : out std_logic; - adata_7 : out std_logic; - adata_6 : out std_logic; - adata_1 : out std_logic; - adata_0 : out std_logic; - adata_9 : out std_logic; - adata_12 : out std_logic; - adata_2 : out std_logic; - adata_3 : out std_logic; - adata_4 : out std_logic; - adata_10 : out std_logic; - adata_27 : out std_logic; - adata_22 : out std_logic; - adata_21 : out std_logic; - adata_25 : out std_logic; - adata_23 : out std_logic; - N_709 : out std_logic; - mmutlb_10_8_2_1_0_VCC : in std_logic := 'U'; - N_694 : out std_logic; - N_695 : out std_logic; - N_696 : out std_logic; - N_2702_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2709_i_0 : out std_logic; - fault_pri_2 : out std_logic; - fault_pro_0 : out std_logic; - accexc_6 : out std_logic; - un54_fault_pro_m : out std_logic; - N_2699_i_0 : out std_logic; - N_2703_i_0 : out std_logic; - G_80_0 : out std_logic; - N_2714 : out std_logic; - N_2717 : out std_logic; - N_2720 : out std_logic; - e : in std_logic := 'U'; - M_m : out std_logic; - fault_pro67 : out std_logic; - N_2701 : out std_logic; - un1_rst_i_0 : out std_logic; - N_264 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - N_82_0 : in std_logic := 'U'; - N_80 : in std_logic := 'U'; - fault_pro_1_0 : in std_logic := 'U'; - fault_mexc_3_2 : out std_logic; - flush_op : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - fault_mexc_0 : out std_logic; - tlbactive : in std_logic := 'U'; - tlbdis : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_3160 : out std_logic; - N_2571 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - fault_pri_m : in std_logic := 'U'; - fault_pri_1 : out std_logic; - fault_pri : out std_logic; - trans_op_0 : in std_logic := 'U'; - N_2488 : out std_logic; - N_2482 : out std_logic; - N_2886 : out std_logic; - N_2887 : out std_logic; - N_190 : out std_logic; - N_192 : out std_logic; - N_236 : out std_logic; - N_293 : out std_logic; - N_317 : out std_logic; - N_351 : out std_logic; - N_353 : out std_logic; - N_415 : out std_logic; - N_417 : out std_logic; - N_419 : out std_logic; - N_421 : out std_logic; - fault_trans_i_2 : in std_logic := 'U'; - fault_su : out std_logic; - fault_read : out std_logic; - inv_1_0_a2_0_a2_0 : in std_logic := 'U'; - fault_trans : out std_logic; - fault_inv : out std_logic; - fault_mexc : in std_logic := 'U'; - areq_ur_1_0_a2_0_0 : out std_logic; - N_2550 : out std_logic; - N_2532 : out std_logic; - rst : in std_logic := 'U'; - read : in std_logic := 'U'; - su : in std_logic := 'U'; - fault_pro_1_iv_1 : out std_logic; - fault_pro_1_iv_2 : out std_logic; - fault_pro_i : out std_logic; - N_82 : in std_logic := 'U'; - s1finished_0 : out std_logic; - walk_use_0 : out std_logic; - lclk_c : in std_logic := 'U'; - N_86_i : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlb_10_8_0_1_0 - port( address_0 : in std_logic_vector(31 downto 2) := (others => 'U'); - aaddr : out std_logic_vector(31 downto 2); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - fault_lvl_1 : out std_logic; - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - lvl_i_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - un1_m0_30 : out std_logic; - un1_m0_9 : out std_logic; - un1_m0_8 : out std_logic; - un1_m0_5 : out std_logic; - un1_m0_1 : out std_logic; - un1_m0_22 : out std_logic; - un1_m0_6 : out std_logic; - un1_m0_0 : out std_logic; - un1_m0_17 : out std_logic; - un1_m0_16 : out std_logic; - un1_m0_7 : out std_logic; - un1_m0_4 : out std_logic; - un1_m0_3 : out std_logic; - un1_m0_2 : out std_logic; - un1_itlb0_1 : out std_logic_vector(41 to 41); - un1_m0_2_0 : in std_logic_vector(35 to 35) := (others => 'U'); - data_0_29 : out std_logic; - data_0_27 : out std_logic; - data_0_26 : out std_logic; - data_0_20 : out std_logic; - data_0_12 : out std_logic; - address : in std_logic_vector(31 downto 2) := (others => 'U'); - data_14 : out std_logic; - data_21 : out std_logic; - data_16 : out std_logic; - data_19 : out std_logic; - data_17 : out std_logic; - data_15 : out std_logic; - data_24 : out std_logic; - data_22 : out std_logic; - data_18 : out std_logic; - data_25 : out std_logic; - data_13 : out std_logic; - data_11 : out std_logic; - data_10 : out std_logic; - data_23 : out std_logic; - data_28 : out std_logic; - fault_isid_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - ft_1_i_a2_0 : in std_logic_vector(0 to 0) := (others => 'U'); - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_25 : in std_logic := 'U'; - hrdata_0_20 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - adata_11 : out std_logic; - adata_31 : out std_logic; - adata_30 : out std_logic; - adata_29 : out std_logic; - adata_28 : out std_logic; - adata_27 : out std_logic; - adata_25 : out std_logic; - adata_24 : out std_logic; - adata_23 : out std_logic; - adata_22 : out std_logic; - adata_20 : out std_logic; - adata_17 : out std_logic; - adata_16 : out std_logic; - adata_15 : out std_logic; - adata_14 : out std_logic; - adata_13 : out std_logic; - adata_12 : out std_logic; - adata_10 : out std_logic; - adata_9 : out std_logic; - adata_8 : out std_logic; - adata_7 : out std_logic; - adata_6 : out std_logic; - adata_2 : out std_logic; - adata_1 : out std_logic; - adata_0 : out std_logic; - adata_18 : out std_logic; - adata_21 : out std_logic; - adata_26 : out std_logic; - adata_4 : out std_logic; - adata_3 : out std_logic; - adata_19 : out std_logic; - s2_tlbstate_0 : out std_logic; - mmutlb_10_8_0_1_0_VCC : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_82 : in std_logic := 'U'; - N_80 : in std_logic := 'U'; - su : in std_logic := 'U'; - N_2625 : out std_logic; - walk_use : out std_logic; - flush_op : in std_logic := 'U'; - N_2933 : out std_logic; - tlbactive : in std_logic := 'U'; - N_180 : out std_logic; - walk_op_ur : out std_logic; - fault_pro_m : in std_logic := 'U'; - fault_pro_1 : out std_logic; - N_2899 : out std_logic; - tlbdis : in std_logic := 'U'; - inv_1_0_a2_0_a2_0 : in std_logic := 'U'; - fault_mexc_2 : in std_logic := 'U'; - fault_trans_i_2 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_3160 : in std_logic := 'U'; - N_2571 : out std_logic; - N_262_0 : in std_logic := 'U'; - fault_pri_m_0 : out std_logic; - fault_mexc_0 : in std_logic := 'U'; - fault_trans_RNIA0K0D1 : out std_logic; - N_429 : out std_logic; - N_427 : out std_logic; - N_2626 : out std_logic; - N_43 : out std_logic; - N_2482 : in std_logic := 'U'; - N_423 : out std_logic; - N_425 : out std_logic; - N_2623 : out std_logic; - N_2624 : out std_logic; - N_45 : out std_logic; - N_319 : out std_logic; - N_321 : out std_logic; - N_361 : out std_logic; - N_363 : out std_logic; - N_365 : out std_logic; - N_357 : out std_logic; - N_1629 : out std_logic; - fault_su : out std_logic; - twi_areq_ur_1_0_a3_i_0 : out std_logic; - fault_mexc_3_2 : in std_logic := 'U'; - fault_mexc_1 : out std_logic; - rst : in std_logic := 'U'; - N_359 : out std_logic; - N_2563_i : in std_logic := 'U'; - s1finished_0 : out std_logic; - lclk_c : in std_logic := 'U'; - N_86_i : in std_logic := 'U' - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_m0_2_1[35]\, fault_access_0_sqmuxa_0, - un207_m_tlb_type_i, trans_op_0, trans_op_RNIFAOCEQ1, - \twowner_2[0]\, twactive_RNI0KM7C4, \twowner_1[0]\, - \twowner_0[0]\, fav_0_sqmuxa_0, ow_2_sqmuxa, N_2899, - \s2_tlbstate[0]\, flush_op, ow_2_sqmuxa_1, fault_mexc_1, - valid_2, fav_1_sqmuxa, ft, fav_1_sqmuxa_RNO, - finish_1_i_o2_m7_0_a2, finish_1_i_o2_m7_0_a2_2, - \twowner_0_RNIK5713[0]\, N_2563_i_0_a4_m7_0_a2_2, - fault_pro_i, un207_m_tlb_type_2, ow_1_sqmuxa, - ow_1_sqmuxa_1, un207_m_tlb_type_1, fault_pri, - N_2563_i_0_a4_m7_0_a2_1_0, N_207, finish_1_i_o2_m7_0_a2_1, - ow_1_sqmuxa_0, flush_0_0, tlbactive_1_2, - \un81_m_tlb_type\, tlbactive_1_0, flush_op_2_m6_i_3, - flush_op_2_m6_i_1, \flush\, \twowner_2_0_a2_0[0]\, - twactive_1_i_a2_0, N_2550, N_2532, N_180, - \ft_1_i_a3_0[0]\, fault_pro_1, fault_pri_1, - N_2563_i_0_a4_m7_0_a2_1, fault_mexc, fault_inv, - fault_trans, N_2485, areq_ur_1_0_a2_0_0, N_2497, - twactive_2, flush_RNO_0, flush_1_sqmuxa, flush_op_RNO_1, - N_4_5_i, d_N_6_1, d_N_5_1, N_2563_i, walk_op_2_0_0_o2_0, - N_82, flush_op_RNO, flush_op_RNO_0, flush_op_RNO_2, - flush_op_0, \fault_isid_1_i[0]\, \un1_m0_2[42]\, N_1576, - \data[12]\, \data_0[12]\, \un1_m0_2_0[35]\, N_1578, - \data[14]\, \data_0[14]\, N_1579, \data[15]\, - \data_0[15]\, N_1580, \data[16]\, \data_0[16]\, N_1581, - \data[17]\, \data_0[17]\, N_1582, \data[18]\, - \data_0[18]\, N_1591, \data[27]\, \data_0[27]\, N_1592, - \data[28]\, \data_0[28]\, N_1594, \data[30]\, - \data_0[30]\, \fault_addr_1[12]\, \N_66_0\, - \fault_addr_1[14]\, \fault_addr_1[15]\, - \fault_addr_1[16]\, \fault_addr_1[17]\, - \fault_addr_1[18]\, \fault_addr_1[27]\, - \fault_addr_1[28]\, \fault_addr_1[30]\, N_2490, fault_su, - fault_read_1, fault_read, fault_su_1, fault_su_0, N_2575, - walk_use_0, \fault_lvl[1]\, \un1_dtlb0_1_i_m[41]\, - \fault_lvl[0]\, \fault_lvl_1_iv[0]\, \un1_itlb0_1[41]\, - \fault_addr_1[23]\, N_582, \fault_addr_1[29]\, N_586, - \fault_addr_1[31]\, \N_66\, N_587, \data[23]\, - \data_0[23]\, \data[29]\, \data_0[29]\, \data[31]\, - \data_0[31]\, N_1584, \data[20]\, \data_0[20]\, N_1586, - \data[22]\, \data_0[22]\, \fault_addr_1[20]\, - \fault_addr_1[22]\, \fault_addr_1[24]\, \un1_m0_2[35]\, - N_583, \fault_addr_1[25]\, N_584, \fault_addr_1[26]\, - N_585, \data[24]\, \data_0[24]\, \data[25]\, \data_0[25]\, - \data[26]\, \data_0[26]\, fav_0_sqmuxa, - \fault_trans_RNIA0K0D1\, N_2484, twi_areq_ur_1_0_a3_i_0, - \fault_addr_1[13]\, N_1577, \data[13]\, \data_0[13]\, - fault_pro_m, fault_pro_1_iv_2, fault_pro_1_iv_1, - \twowner_2_0_a2_0_0[0]\, N_46, N_2487, walk_op_ur, - \twowner[0]\, finish, twactive, tlbactive, s1finished_0, - N_57, N_1748, flush_op_RNO_3, N_1750, N_2933, N_1755, - tlbactive_0, tlbactive_1, s1finished_0_0, N_1757, - flush_op_1, un76_m_tlb_type, \un2_m_tlb_type\, - un75_m_tlb_type, trans_op_RNIA539EQ1, trans_op_3, N_47, - N_49, N_51, N_1583, \data[19]\, \data_0[19]\, - \fault_addr_1[19]\, \fault_addr_1[21]\, N_1585, - \data[21]\, \data_0[21]\, \un1_m0_2[54]\, \ft_RNO[0]\, - N_1629, \ft_1[1]\, fault_mexc_3_2, \ft_1[2]\, N_1744, - N_1947_i, fav_RNO, N_2588, walk_use, \fault_lvl_0[1]\, - \fault_lvl_1_iv[1]\, tlbactive_RNO, \un1_m0_2[37]\, - tlbactive_2, \un1_m0_2[38]\, \un1_m0_2[39]\, - \un1_m0_2[40]\, \aaddr[2]\, \aaddr[3]\, \aaddr[4]\, - \aaddr[5]\, \aaddr[6]\, \aaddr[7]\, \aaddr[8]\, - \aaddr[9]\, \aaddr[10]\, \aaddr[11]\, \aaddr[12]\, - \aaddr[13]\, \aaddr[14]\, \aaddr[15]\, \aaddr[16]\, - \aaddr[17]\, \aaddr[18]\, \aaddr[19]\, \aaddr[20]\, - \aaddr[21]\, \aaddr[22]\, \aaddr[23]\, \aaddr[24]\, - \aaddr[25]\, \aaddr[26]\, \aaddr[27]\, \aaddr[28]\, - \aaddr[29]\, \aaddr[30]\, \aaddr[31]\, \lvl_i_1[0]\, - \lvl_i_1[1]\, \lvl_i_1_0[1]\, \ft_1_i_a2_0[0]\, - \adata[11]\, \adata[31]\, \adata[30]\, \adata[29]\, - \adata[28]\, \adata[27]\, \adata[25]\, \adata[24]\, - \adata[23]\, \adata[22]\, \adata[20]\, \adata[17]\, - \adata[16]\, \adata[15]\, \adata[14]\, \adata[13]\, - \adata[12]\, \adata[10]\, \adata[9]\, \adata[8]\, - \adata[7]\, \adata[6]\, \adata[2]\, \adata[1]\, - \adata[0]\, \adata[18]\, \adata[21]\, \adata[26]\, - \adata[4]\, \adata[3]\, \adata[19]\, un1_rst_i_0, N_82_0, - N_80, inv_1_0_a2_0_a2_0, fault_mexc_0, fault_trans_i_2, - N_3160, N_2571, fault_pri_m, N_2482, N_86_i, \aaddr_0[2]\, - \aaddr_0[3]\, \aaddr_0[4]\, \aaddr_0[5]\, \aaddr_0[6]\, - \aaddr_0[8]\, \aaddr_0[9]\, \aaddr_0[10]\, \aaddr_0[11]\, - \aaddr_0[12]\, \aaddr_0[13]\, \aaddr_0[14]\, - \aaddr_0[15]\, \aaddr_0[16]\, \aaddr_0[17]\, - \aaddr_0[18]\, \aaddr_0[19]\, \aaddr_0[20]\, - \aaddr_0[21]\, \aaddr_0[22]\, \aaddr_0[23]\, - \aaddr_0[24]\, \aaddr_0[25]\, \aaddr_0[26]\, - \aaddr_0[27]\, \aaddr_0[28]\, \aaddr_0[29]\, - \aaddr_0[30]\, \aaddr_0[31]\, \address[2]\, \address[3]\, - \address[4]\, \address[5]\, \address[6]\, \address[7]\, - \address[8]\, \address[9]\, \address[10]\, \address[11]\, - \address[12]\, \address[13]\, \address[14]\, - \address[15]\, \address[16]\, \address[17]\, - \address[18]\, \address[19]\, \address[20]\, - \address[21]\, \address[22]\, \address[23]\, - \address[24]\, \address[25]\, \address[26]\, - \address[27]\, \address[28]\, \address[29]\, - \address[30]\, \address[31]\, \un1_m0_2[1]\, - \adata_0[20]\, \adata_0[13]\, \adata_0[17]\, - \adata_0[31]\, \adata_0[30]\, \adata_0[29]\, - \adata_0[28]\, \adata_0[26]\, \adata_0[24]\, - \adata_0[19]\, \adata_0[18]\, \adata_0[16]\, - \adata_0[15]\, \adata_0[14]\, \adata_0[11]\, \adata_0[8]\, - \adata_0[7]\, \adata_0[6]\, \adata_0[1]\, \adata_0[0]\, - \adata_0[9]\, \adata_0[12]\, \adata_0[2]\, \adata_0[3]\, - \adata_0[4]\, \adata_0[10]\, \adata_0[27]\, \adata_0[22]\, - \adata_0[21]\, \adata_0[25]\, \adata_0[23]\, N_709, - N_2488, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : mmutw - Use entity work.mmutw(DEF_ARCH); - for all : mmutlb_10_8_2_1_0 - Use entity work.mmutlb_10_8_2_1_0(DEF_ARCH); - for all : mmutlb_10_8_0_1_0 - Use entity work.mmutlb_10_8_0_1_0(DEF_ARCH); -begin - - address(31) <= \address[31]\; - address(30) <= \address[30]\; - address(29) <= \address[29]\; - address(28) <= \address[28]\; - address(27) <= \address[27]\; - address(26) <= \address[26]\; - address(25) <= \address[25]\; - address(24) <= \address[24]\; - address(23) <= \address[23]\; - address(22) <= \address[22]\; - address(21) <= \address[21]\; - address(20) <= \address[20]\; - address(19) <= \address[19]\; - address(18) <= \address[18]\; - address(17) <= \address[17]\; - address(16) <= \address[16]\; - address(15) <= \address[15]\; - address(14) <= \address[14]\; - address(13) <= \address[13]\; - address(12) <= \address[12]\; - address(11) <= \address[11]\; - address(10) <= \address[10]\; - address(9) <= \address[9]\; - address(8) <= \address[8]\; - address(7) <= \address[7]\; - address(6) <= \address[6]\; - address(5) <= \address[5]\; - address(4) <= \address[4]\; - address(3) <= \address[3]\; - address(2) <= \address[2]\; - un1_m0_2_36 <= \un1_m0_2[37]\; - un1_m0_2_34 <= \un1_m0_2[35]\; - un1_m0_2_39 <= \un1_m0_2[40]\; - un1_m0_2_38 <= \un1_m0_2[39]\; - un1_m0_2_37 <= \un1_m0_2[38]\; - un1_m0_2_0_d0 <= \un1_m0_2[1]\; - un1_m0_2_41 <= \un1_m0_2[42]\; - fault_isid_1_i(0) <= \fault_isid_1_i[0]\; - un1_m0_2_0(35) <= \un1_m0_2_0[35]\; - N_66 <= \N_66\; - un2_m_tlb_type <= \un2_m_tlb_type\; - flush <= \flush\; - un81_m_tlb_type <= \un81_m_tlb_type\; - N_66_0 <= \N_66_0\; - fault_trans_RNIA0K0D1 <= \fault_trans_RNIA0K0D1\; - - \r.mmctrl2.fs.l_RNO[1]\ : OA1C - port map(A => \un1_m0_2[35]\, B => N_2575, C => N_2588, Y - => \fault_lvl_1_iv[1]\); - - \r.mmctrl2.fa[9]\ : DFN1E1 - port map(D => \fault_addr_1[21]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_63); - - \p0.twod.finish_1_i_o2_m7_0_a2\ : AND2 - port map(A => N_546, B => finish_1_i_o2_m7_0_a2_2, Y => - finish_1_i_o2_m7_0_a2); - - \p0.twod.finish_1_i_o2_m7_0_a2_RNIRIJ8K\ : MX2B - port map(A => N_4_5_i, B => walk_op_2_0_0_o2_0, S => - finish_1_i_o2_m7_0_a2, Y => N_82); - - \r.splt_ds2.tlbactive\ : DFN1 - port map(D => N_51, CLK => lclk_c, Q => tlbactive_0); - - \r.mmctrl2.valid_RNIE60N892\ : OR2B - port map(A => \un1_m0_2[54]\, B => fsread_i_0, Y => valid_2); - - \r.mmctrl2.fa_RNO_0[17]\ : MX2C - port map(A => \data[29]\, B => \data_0[29]\, S => - \un1_m0_2_1[35]\, Y => N_586); - - \r.splt_is1.op.flush_op_RNO_2\ : MX2 - port map(A => flush_op_0, B => \flush\, S => - \un81_m_tlb_type\, Y => flush_op_RNO_2); - - \r.mmctrl2.fa[5]\ : DFN1E1 - port map(D => \fault_addr_1[17]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_59); - - \r.mmctrl2.fs.ft_RNIHTCF[0]\ : OR3A - port map(A => \un1_m0_2[38]\, B => \un1_m0_2[39]\, C => - \un1_m0_2[40]\, Y => ft); - - \r.mmctrl2.fa_RNO_0[18]\ : MX2C - port map(A => \data[30]\, B => \data_0[30]\, S => - \un1_m0_2_0[35]\, Y => N_1594); - - \r.twowner_0_RNIK5713[0]\ : AND2 - port map(A => N_546, B => N_2563_i_0_a4_m7_0_a2_2, Y => - \twowner_0_RNIK5713[0]\); - - \r.mmctrl2.fs.l_RNO[0]\ : OA1C - port map(A => \fault_isid_1_i[0]\, B => \un1_itlb0_1[41]\, - C => \un1_dtlb0_1_i_m[41]\, Y => \fault_lvl_1_iv[0]\); - - \r.mmctrl2.fs.ft[1]\ : DFN1E1 - port map(D => \ft_1[1]\, CLK => lclk_c, E => fav_0_sqmuxa, - Q => \un1_m0_2[39]\); - - \r.twactive_RNIC87T31\ : OR2B - port map(A => finish, B => twactive, Y => twactive_2); - - \r.splt_is2.tlbactive_RNO_0\ : MX2 - port map(A => N_2933, B => tlbactive, S => s1finished_0, Y - => N_1748); - - \r.splt_is2.op.flush_op_RNO\ : NOR2B - port map(A => rst, B => N_1750, Y => flush_op_RNO_3); - - \r.mmctrl2.fs.at_ls_RNO\ : MX2B - port map(A => \N_66_0\, B => fault_read, S => - \un1_m0_2_1[35]\, Y => fault_read_1); - - \r.mmctrl2.fs.ft_RNO[1]\ : AO1 - port map(A => fault_mexc_3_2, B => N_1629, C => - fault_mexc_1, Y => \ft_1[1]\); - - \r.mmctrl2.fa[2]\ : DFN1E1 - port map(D => \fault_addr_1[14]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_56); - - \r.mmctrl2.fs.at_su_RNO_0\ : OR2B - port map(A => fault_su, B => \fault_isid_1_i[0]\, Y => - N_2490); - - \r.mmctrl2.fa_RNO[3]\ : AO1C - port map(A => \un1_m0_2_0[35]\, B => \N_66_0\, C => N_1579, - Y => \fault_addr_1[15]\); - - \r.splt_is1.tlbactive\ : DFN1 - port map(D => tlbactive_RNO, CLK => lclk_c, Q => tlbactive); - - \r.twactive\ : DFN1 - port map(D => N_46, CLK => lclk_c, Q => twactive); - - \r.mmctrl2.fs.l_RNO_0[0]\ : AOI1B - port map(A => walk_use_0, B => \fault_lvl[0]\, C => - \un1_m0_2_1[35]\, Y => \un1_dtlb0_1_i_m[41]\); - - \r.mmctrl2.fa_RNO[16]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1592, - Y => \fault_addr_1[28]\); - - \r.splt_ds1.op.trans_op_0\ : DFN1 - port map(D => trans_op_RNIFAOCEQ1, CLK => lclk_c, Q => - trans_op_0); - - \p0.un207_m_tlb_type\ : AND2 - port map(A => fault_pro_i, B => un207_m_tlb_type_2, Y => - un207_m_tlb_type_i); - - \r.splt_is1.tlbactive_RNIDB3G1\ : OR2A - port map(A => tlbactive, B => s1finished_0, Y => - \un81_m_tlb_type\); - - tw0 : mmutw - port map(data_1(31) => data_2(31), data_1(30) => data_2(30), - data_1(29) => data_2(29), data_1(28) => data_2(28), - data_1(27) => data_2(27), data_1(26) => data_2(26), - data_1(25) => data_2(25), data_1(24) => data_2(24), - data_1(23) => data_2(23), data_1(22) => data_2(22), - data_1(21) => data_2(21), data_1(20) => data_2(20), - data_1(19) => data_2(19), data_1(18) => data_2(18), - data_1(17) => data_2(17), data_1(16) => data_2(16), - data_1(15) => data_2(15), data_1(14) => data_2(14), - data_1(13) => data_2(13), data_1(12) => data_2(12), - address(31) => \address[31]\, address(30) => - \address[30]\, address(29) => \address[29]\, address(28) - => \address[28]\, address(27) => \address[27]\, - address(26) => \address[26]\, address(25) => - \address[25]\, address(24) => \address[24]\, address(23) - => \address[23]\, address(22) => \address[22]\, - address(21) => \address[21]\, address(20) => - \address[20]\, address(19) => \address[19]\, address(18) - => \address[18]\, address(17) => \address[17]\, - address(16) => \address[16]\, address(15) => - \address[15]\, address(14) => \address[14]\, address(13) - => \address[13]\, address(12) => \address[12]\, - address(11) => \address[11]\, address(10) => - \address[10]\, address(9) => \address[9]\, address(8) => - \address[8]\, address(7) => \address[7]\, address(6) => - \address[6]\, address(5) => \address[5]\, address(4) => - \address[4]\, address(3) => \address[3]\, address(2) => - \address[2]\, twowner(0) => \twowner[0]\, twowner_2(0) - => \twowner_2[0]\, aaddr_0_25 => \aaddr_0[27]\, - aaddr_0_24 => \aaddr_0[26]\, aaddr_0_29 => \aaddr_0[31]\, - aaddr_0_18 => \aaddr_0[20]\, aaddr_0_17 => \aaddr_0[19]\, - aaddr_0_9 => \aaddr_0[11]\, aaddr_0_8 => \aaddr_0[10]\, - aaddr_0_7 => \aaddr_0[9]\, aaddr_0_4 => \aaddr_0[6]\, - aaddr_0_0 => \aaddr_0[2]\, aaddr_0_21 => \aaddr_0[23]\, - aaddr_0_22 => \aaddr_0[24]\, aaddr_0_23 => \aaddr_0[25]\, - aaddr_0_28 => \aaddr_0[30]\, aaddr_0_27 => \aaddr_0[29]\, - aaddr_0_26 => \aaddr_0[28]\, aaddr_0_20 => \aaddr_0[22]\, - aaddr_0_19 => \aaddr_0[21]\, aaddr_0_16 => \aaddr_0[18]\, - aaddr_0_15 => \aaddr_0[17]\, aaddr_0_14 => \aaddr_0[16]\, - aaddr_0_13 => \aaddr_0[15]\, aaddr_0_12 => \aaddr_0[14]\, - aaddr_0_11 => \aaddr_0[13]\, aaddr_0_10 => \aaddr_0[12]\, - aaddr_0_6 => \aaddr_0[8]\, aaddr_0_3 => \aaddr_0[5]\, - aaddr_0_2 => \aaddr_0[4]\, aaddr_0_1 => \aaddr_0[3]\, - aaddr_25 => \aaddr[27]\, aaddr_24 => \aaddr[26]\, - aaddr_29 => \aaddr[31]\, aaddr_18 => \aaddr[20]\, - aaddr_17 => \aaddr[19]\, aaddr_9 => \aaddr[11]\, aaddr_8 - => \aaddr[10]\, aaddr_7 => \aaddr[9]\, aaddr_4 => - \aaddr[6]\, aaddr_0_d0 => \aaddr[2]\, aaddr_21 => - \aaddr[23]\, aaddr_22 => \aaddr[24]\, aaddr_23 => - \aaddr[25]\, aaddr_28 => \aaddr[30]\, aaddr_27 => - \aaddr[29]\, aaddr_26 => \aaddr[28]\, aaddr_20 => - \aaddr[22]\, aaddr_19 => \aaddr[21]\, aaddr_16 => - \aaddr[18]\, aaddr_15 => \aaddr[17]\, aaddr_14 => - \aaddr[16]\, aaddr_13 => \aaddr[15]\, aaddr_12 => - \aaddr[14]\, aaddr_11 => \aaddr[13]\, aaddr_10 => - \aaddr[12]\, aaddr_6 => \aaddr[8]\, aaddr_3 => \aaddr[5]\, - aaddr_2 => \aaddr[4]\, aaddr_1 => \aaddr[3]\, - twowner_1(0) => \twowner_1[0]\, data_0(31) => - \data_0[31]\, data_0(30) => \data_0[30]\, data_0(29) => - \data[29]\, data_0(28) => \data[28]\, data_0(27) => - \data[27]\, data_0(26) => \data[26]\, data_0(25) => - \data[25]\, data_0(24) => \data_0[24]\, data_0(23) => - \data[23]\, data_0(22) => \data[22]\, data_0(21) => - \data[21]\, data_0(20) => \data[20]\, data_0(19) => - \data[19]\, data_0(18) => \data_0[18]\, data_0(17) => - \data_0[17]\, data_0(16) => \data_0[16]\, data_0(15) => - \data_0[15]\, data_0(14) => \data_0[14]\, data_0(13) => - \data_0[13]\, data_0(12) => \data_0[12]\, data_11 => - data_11, data_10 => data_10, data_9 => data_9, data_8 => - data_8, data_7 => data_7, data_6 => data_6, data_4 => - data_4, data_3 => data_3, data_2 => data_2_d0, data_1_d0 - => data_1_d0, data_0_d0 => data_0, data_12 => \data[12]\, - data_18 => \data[18]\, data_24 => \data[24]\, data_16 => - \data[16]\, data_22 => \data_0[22]\, data_28 => - \data_0[28]\, data_20 => \data_0[20]\, data_26 => - \data_0[26]\, data_17 => \data[17]\, data_15 => - \data[15]\, data_14 => \data[14]\, data_13 => \data[13]\, - data_23 => \data_0[23]\, data_29 => \data_0[29]\, data_30 - => \data[30]\, data_31 => \data[31]\, data_21 => - \data_0[21]\, data_27 => \data_0[27]\, data_19 => - \data_0[19]\, data_25 => \data_0[25]\, adata_0_19 => - \adata_0[19]\, adata_0_20 => \adata_0[20]\, adata_0_18 - => \adata_0[18]\, adata_0_10 => \adata_0[10]\, adata_0_2 - => \adata_0[2]\, adata_0_13 => \adata_0[13]\, adata_0_14 - => \adata_0[14]\, adata_0_30 => \adata_0[30]\, - adata_0_29 => \adata_0[29]\, adata_0_28 => \adata_0[28]\, - adata_0_6 => \adata_0[6]\, adata_0_1 => \adata_0[1]\, - adata_0_0 => \adata_0[0]\, adata_0_31 => \adata_0[31]\, - adata_0_17 => \adata_0[17]\, adata_0_7 => \adata_0[7]\, - adata_0_25 => \adata_0[25]\, adata_0_22 => \adata_0[22]\, - adata_0_11 => \adata_0[11]\, adata_0_24 => \adata_0[24]\, - adata_0_23 => \adata_0[23]\, adata_0_15 => \adata_0[15]\, - adata_0_12 => \adata_0[12]\, adata_0_21 => \adata_0[21]\, - adata_0_16 => \adata_0[16]\, adata_0_9 => \adata_0[9]\, - adata_0_8 => \adata_0[8]\, adata_0_26 => \adata_0[26]\, - adata_0_27 => \adata_0[27]\, adata_0_4 => \adata_0[4]\, - adata_0_3 => \adata_0[3]\, adata_19 => \adata[19]\, - adata_20 => \adata[20]\, adata_18 => \adata[18]\, - adata_10 => \adata[10]\, adata_2 => \adata[2]\, adata_13 - => \adata[13]\, adata_14 => \adata[14]\, adata_30 => - \adata[30]\, adata_29 => \adata[29]\, adata_28 => - \adata[28]\, adata_6 => \adata[6]\, adata_1 => \adata[1]\, - adata_0_d0 => \adata[0]\, adata_31 => \adata[31]\, - adata_17 => \adata[17]\, adata_7 => \adata[7]\, adata_25 - => \adata[25]\, adata_22 => \adata[22]\, adata_11 => - \adata[11]\, adata_24 => \adata[24]\, adata_23 => - \adata[23]\, adata_15 => \adata[15]\, adata_12 => - \adata[12]\, adata_21 => \adata[21]\, adata_16 => - \adata[16]\, adata_9 => \adata[9]\, adata_8 => \adata[8]\, - adata_26 => \adata[26]\, adata_27 => \adata[27]\, adata_4 - => \adata[4]\, adata_3 => \adata[3]\, twowner_0(0) => - \twowner_0[0]\, lvl_i_1(1) => \lvl_i_1[1]\, lvl_i_1(0) - => \lvl_i_1[0]\, ctx_0_d0 => ctx(0), ctx_1 => ctx(1), - ctx_2 => ctx(2), ctx_3 => ctx(3), ctx_6 => ctx(6), ctx_7 - => ctx(7), hrdata(6) => hrdata_6, hrdata(5) => hrdata_5, - iosn_0(93) => iosn_0(93), ctx_0(5) => ctx_0(5), ctx_0(4) - => ctx_0(4), ctxp(25) => ctxp(25), ctxp(24) => ctxp(24), - ctxp(23) => ctxp(23), ctxp(22) => ctxp(22), ctxp(21) => - ctxp(21), ctxp(20) => ctxp(20), ctxp(19) => ctxp(19), - ctxp(18) => ctxp(18), ctxp(17) => ctxp(17), ctxp(16) => - ctxp(16), ctxp(15) => ctxp(15), ctxp(14) => ctxp(14), - ctxp(13) => ctxp(13), ctxp(12) => ctxp(12), ctxp(11) => - ctxp(11), ctxp(10) => ctxp(10), ctxp(9) => ctxp(9), - ctxp(8) => ctxp(8), ctxp(7) => ctxp(7), ctxp(6) => - ctxp(6), ctxp(5) => ctxp(5), ctxp(4) => ctxp(4), ctxp(3) - => ctxp(3), ctxp(2) => ctxp(2), ctxp(1) => ctxp(1), - ctxp(0) => ctxp(0), hrdata_0_3 => hrdata_0_3, hrdata_0_16 - => hrdata_0_16, hrdata_0_15 => hrdata_0_15, hrdata_0_13 - => hrdata_0_13, hrdata_0_10 => hrdata_0_10, hrdata_0_9 - => hrdata_0_9, hrdata_0_8 => hrdata_0_8, hrdata_0_24 => - hrdata_0_24, hrdata_0_26 => hrdata_0_26, hrdata_0_4 => - hrdata_0_4, hrdata_0_1 => hrdata_0_1, hrdata_0_0 => - hrdata_0_0, hrdata_0_2 => hrdata_0_2, hrdata_0_14 => - hrdata_0_14, hrdata_0_12 => hrdata_0_12, hrdata_0_11 => - hrdata_0_11, hrdata_0_21 => hrdata_0_21, hrdata_0_18 => - hrdata_0_18, hrdata_0_17 => hrdata_0_17, hrdata_0_7 => - hrdata_0_7, hrdata_0_23 => hrdata_0_23, hrdata_0_22 => - hrdata_0_22, hrdata_0_27 => hrdata_0_27, lvl_i_1_0(1) => - \lvl_i_1_0[1]\, lclk_c => lclk_c, grant => grant, N_264_0 - => N_264_0, N_262_0 => N_262_0, N_82 => N_82_0, N_80 => - N_80, N_709 => N_709, finish => finish, N_78_0 => N_78_0, - d_N_6_1 => d_N_6_1, N_2563_i_0_a4_m7_0_a2_1 => - N_2563_i_0_a4_m7_0_a2_1, fault_trans_i_2 => - fault_trans_i_2, walk_op_2_0_0_o2_0 => walk_op_2_0_0_o2_0, - N_2488 => N_2488, N_2487 => N_2487, read => read_0, - bo_5842_d_0 => bo_5842_d_0, ba => ba, req => req, - inv_1_0_a2_0_a2_0 => inv_1_0_a2_0_a2_0, rst => rst, mexc - => mexc, fault_mexc => fault_mexc_0, N_2484 => N_2484, - N_2485 => N_2485, N_207 => N_207); - - \v.mmctrl2.fs.ow_1_sqmuxa_RNO\ : AND2 - port map(A => \fault_isid_1_i[0]\, B => ow_1_sqmuxa_0, Y - => ow_1_sqmuxa_1); - - \r.splt_ds1.tlbactive_RNO\ : OA1A - port map(A => \un2_m_tlb_type\, B => un75_m_tlb_type, C => - rst, Y => N_49); - - \r.mmctrl2.fa_RNO_0[10]\ : MX2C - port map(A => \data[22]\, B => \data_0[22]\, S => - \un1_m0_2_1[35]\, Y => N_1586); - - \r.mmctrl2.fa[17]\ : DFN1E1 - port map(D => \fault_addr_1[29]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_71); - - \r.splt_ds1.tlbactive_RNO_0\ : OR2B - port map(A => trans_op_2, B => flush_op_i_0, Y => - un75_m_tlb_type); - - \r.twowner_2[0]\ : DFN1 - port map(D => twactive_RNI0KM7C4, CLK => lclk_c, Q => - \twowner_2[0]\); - - \r.twactive_RNO_0\ : AO1D - port map(A => N_2550, B => N_2532, C => N_180, Y => - twactive_1_i_a2_0); - - \r.splt_ds1.op.trans_op_RNIFAOCEQ1\ : NOR2A - port map(A => rst, B => trans_op_RNIA539EQ1, Y => - trans_op_RNIFAOCEQ1); - - \r.flush_RNO_0\ : OR2A - port map(A => rst, B => \un81_m_tlb_type\, Y => flush_0_0); - - \r.mmctrl2.fa_RNO_0[16]\ : MX2C - port map(A => \data[28]\, B => \data_0[28]\, S => - \un1_m0_2_0[35]\, Y => N_1592); - - \r.mmctrl2.fa_RNO[7]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_1583, Y - => \fault_addr_1[19]\); - - \p0.un207_m_tlb_type_RNI4B8O1\ : NOR2 - port map(A => fault_access_0_sqmuxa_0, B => - un207_m_tlb_type_i, Y => \un1_m0_2_0[35]\); - - \p0.twod.finish_1_i_o2_m7_0_a2_RNO\ : NOR2A - port map(A => finish_1_i_o2_m7_0_a2_1, B => N_207, Y => - finish_1_i_o2_m7_0_a2_2); - - \r.splt_is1.op.flush_op_RNO_4\ : NOR3A - port map(A => rst, B => \flush\, C => trans_op_1, Y => - flush_op_2_m6_i_1); - - \r.mmctrl2.fa_RNO[14]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_585, Y - => \fault_addr_1[26]\); - - GND_i : GND - port map(Y => \GND\); - - \r.splt_is1.op.flush_op_RNO_3\ : NOR3C - port map(A => \un2_m_tlb_type\, B => flush_op_2_m6_i_1, C - => \un81_m_tlb_type\, Y => flush_op_2_m6_i_3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.mmctrl2.fa_RNO[9]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_1585, Y - => \fault_addr_1[21]\); - - \r.splt_ds2.tlbactive_RNO\ : NOR2B - port map(A => rst, B => N_1755, Y => N_51); - - \r.splt_is2.op.flush_op_RNO_0\ : MX2 - port map(A => flush_op, B => flush_op_0, S => s1finished_0, - Y => N_1750); - - \r.mmctrl2.fa_RNO[0]\ : AO1C - port map(A => \un1_m0_2_0[35]\, B => \N_66_0\, C => N_1576, - Y => \fault_addr_1[12]\); - - \r.mmctrl2.fa_RNO_0[4]\ : MX2C - port map(A => \data[16]\, B => \data_0[16]\, S => - \un1_m0_2_0[35]\, Y => N_1580); - - \r.mmctrl2.fa[7]\ : DFN1E1 - port map(D => \fault_addr_1[19]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_61); - - \tlbsplit0.dtlb0\ : mmutlb_10_8_2_1_0 - port map(aaddr(31) => \aaddr_0[31]\, aaddr(30) => - \aaddr_0[30]\, aaddr(29) => \aaddr_0[29]\, aaddr(28) => - \aaddr_0[28]\, aaddr(27) => \aaddr_0[27]\, aaddr(26) => - \aaddr_0[26]\, aaddr(25) => \aaddr_0[25]\, aaddr(24) => - \aaddr_0[24]\, aaddr(23) => \aaddr_0[23]\, aaddr(22) => - \aaddr_0[22]\, aaddr(21) => \aaddr_0[21]\, aaddr(20) => - \aaddr_0[20]\, aaddr(19) => \aaddr_0[19]\, aaddr(18) => - \aaddr_0[18]\, aaddr(17) => \aaddr_0[17]\, aaddr(16) => - \aaddr_0[16]\, aaddr(15) => \aaddr_0[15]\, aaddr(14) => - \aaddr_0[14]\, aaddr(13) => \aaddr_0[13]\, aaddr(12) => - \aaddr_0[12]\, aaddr(11) => \aaddr_0[11]\, aaddr(10) => - \aaddr_0[10]\, aaddr(9) => \aaddr_0[9]\, aaddr(8) => - \aaddr_0[8]\, aaddr(7) => \aaddr[7]\, aaddr(6) => - \aaddr_0[6]\, aaddr(5) => \aaddr_0[5]\, aaddr(4) => - \aaddr_0[4]\, aaddr(3) => \aaddr_0[3]\, aaddr(2) => - \aaddr_0[2]\, twowner_1(0) => \twowner_1[0]\, address(31) - => \address[31]\, address(30) => \address[30]\, - address(29) => \address[29]\, address(28) => - \address[28]\, address(27) => \address[27]\, address(26) - => \address[26]\, address(25) => \address[25]\, - address(24) => \address[24]\, address(23) => - \address[23]\, address(22) => \address[22]\, address(21) - => \address[21]\, address(20) => \address[20]\, - address(19) => \address[19]\, address(18) => - \address[18]\, address(17) => \address[17]\, address(16) - => \address[16]\, address(15) => \address[15]\, - address(14) => \address[14]\, address(13) => - \address[13]\, address(12) => \address[12]\, address(11) - => \address[11]\, address(10) => \address[10]\, - address(9) => \address[9]\, address(8) => \address[8]\, - address(7) => \address[7]\, address(6) => \address[6]\, - address(5) => \address[5]\, address(4) => \address[4]\, - address(3) => \address[3]\, address(2) => \address[2]\, - data_1_3_i_a3_6_0 => data_1_3_i_a3_6_0, data_1_3_i_a3_6_1 - => data_1_3_i_a3_6_1, data_1_3_i_a3_6_4 => - data_1_3_i_a3_6_4, data_1_3_i_a3_6_2 => data_1_3_i_a3_6_2, - LVL_RNIT69H911(0) => LVL_RNIT69H911(0), ctx_0(7) => - ctx_0(7), ctx_0(6) => ctx_0(6), ctx_0(5) => ctx_0(5), - ctx_0(4) => ctx_0(4), ctx_0(3) => ctx_0(3), ctx_0(2) => - ctx_0(2), ctx_0(1) => ctx_0(1), ctx_0(0) => ctx_0(0), - ctx(7) => ctx(7), ctx(6) => ctx(6), ctx(5) => ctx(5), - ctx(4) => ctx(4), ctx(3) => ctx(3), ctx(2) => ctx(2), - ctx(1) => ctx(1), ctx(0) => ctx(0), fault_lvl(1) => - \fault_lvl[1]\, fault_lvl(0) => \fault_lvl[0]\, - lvl_i_1(1) => \lvl_i_1[1]\, lvl_i_1(0) => \lvl_i_1[0]\, - data_2_0 => data_1(17), lvl_i_1_0(1) => \lvl_i_1_0[1]\, - data_1_17 => data_1(29), data_1_5 => \data_0[17]\, - data_1_11 => data_1(23), data_1_10 => data_1(22), - data_1_9 => data_1(21), data_1_8 => data_1(20), data_1_7 - => data_1(19), data_1_4 => data_1(16), data_1_12 => - data_1(24), data_1_15 => data_1(27), hrdata_2 => hrdata_2, - hrdata_3 => hrdata_3, hrdata_4 => hrdata_4, hrdata_0_d0 - => hrdata_0_d0, hrdata_1 => hrdata_1, hrdata_8 => - hrdata_8, hrdata_9 => hrdata_9, hrdata_10 => hrdata_10, - hrdata_11 => hrdata_11, hrdata_12 => hrdata_12, hrdata_13 - => hrdata_13, hrdata_14 => hrdata_14, hrdata_15 => - hrdata_15, hrdata_16 => hrdata_16, hrdata_17 => hrdata_17, - hrdata_18 => hrdata_18, hrdata_21 => hrdata_21, hrdata_22 - => hrdata_22, hrdata_23 => hrdata_23, hrdata_24 => - hrdata_24, hrdata_26 => hrdata_26, hrdata_27 => hrdata_27, - hrdata_28 => hrdata_28, hrdata_29 => hrdata_29, hrdata_30 - => hrdata_30, hrdata_31 => hrdata_31, hrdata_7 => - hrdata_7, hrdata_5 => hrdata_5, hrdata_6 => hrdata_6, - maddress(31) => maddress(31), maddress(30) => - maddress(30), maddress(29) => maddress(29), maddress(28) - => maddress(28), maddress(27) => maddress(27), - maddress(26) => maddress(26), maddress(25) => - maddress(25), maddress(24) => maddress(24), maddress(23) - => maddress(23), maddress(22) => maddress(22), - maddress(21) => maddress(21), maddress(20) => - maddress(20), maddress(19) => maddress(19), maddress(18) - => maddress(18), maddress(17) => maddress(17), - maddress(16) => maddress(16), maddress(15) => - maddress(15), maddress(14) => maddress(14), maddress(13) - => maddress(13), maddress(12) => maddress(12), - twowner_0(0) => \twowner_0[0]\, data_RNIKU1T4(16) => - data_RNIKU1T4(16), un1_m0_2_94 => un1_m0_2_94, - un1_m0_2_98 => un1_m0_2_98, un1_m0_2_92 => un1_m0_2_92, - un1_m0_2_106 => un1_m0_2_106, un1_m0_2_91 => un1_m0_2_91, - un1_m0_2_108 => un1_m0_2_108, un1_m0_2_93 => un1_m0_2_93, - un1_m0_2_95 => un1_m0_2_95, un1_m0_2_96 => un1_m0_2_96, - un1_m0_2_97 => un1_m0_2_97, un1_m0_2_86 => un1_m0_2_86, - un1_m0_2_85 => un1_m0_2_85, un1_m0_2_84 => un1_m0_2_84, - un1_m0_2_83 => un1_m0_2_83, un1_m0_2_82 => un1_m0_2_82, - un1_m0_2_81 => un1_m0_2_81, un1_m0_2_80 => un1_m0_2_80, - un1_m0_2_79 => un1_m0_2_79, un1_m0_2_78 => un1_m0_2_78, - un1_m0_2_77 => un1_m0_2_77, un1_m0_2_76 => un1_m0_2_76, - un1_m0_2_75 => un1_m0_2_75, un1_m0_2_7 => un1_m0_2_7, - un1_m0_2_10 => un1_m0_2_10, un1_m0_2_9 => un1_m0_2_9, - un1_m0_2_0_d0 => \un1_m0_2[1]\, un1_m0_2_19 => - un1_m0_2_19, un1_m0_2_29 => un1_m0_2_29, un1_m0_2_18 => - un1_m0_2_18, un1_m0_2_12 => un1_m0_2_12, un1_m0_2_11 => - un1_m0_2_11, un1_m0_2_8 => un1_m0_2_8, un1_m0_2_6 => - un1_m0_2_6, un1_m0_2_5 => un1_m0_2_5, un1_m0_2_4 => - un1_m0_2_4, un1_m0_2_3 => un1_m0_2_3, un1_m0_2_2 => - un1_m0_2_2, un1_m0_2_1 => un1_m0_2_1, un1_m0_2_33 => - un1_m0_2_33, un1_m0_2_31 => un1_m0_2_31, un1_m0_2_15 => - un1_m0_2_15, un1_m0_2_23 => un1_m0_2_23, data_0_18 => - data_1(18), data_0_14 => data_1(14), data_0_22 => - \data_0[22]\, data_0_21 => \data_0[21]\, data_0_20 => - \data_0[20]\, data_0_19 => \data_0[19]\, data_0_23 => - \data_0[23]\, data_0_16 => \data_0[16]\, data_0_28 => - data_1(28), data_0_30 => data_1(30), data_0_26 => - data_1(26), data_0_25 => data_1(25), data_0_15 => - data_1(15), data_0_12 => data_1(12), data_0_31 => - data_1(31), data_0_27 => \data_0[27]\, data_0_29 => - \data_0[29]\, data_0_13 => \data_0[13]\, hrdata_0_0 => - hrdata_0_0, hrdata_0_15 => hrdata_0_15, hrdata_0_14 => - hrdata_0_14, hrdata_0_16 => hrdata_0_16, hrdata_0_13 => - hrdata_0_13, hrdata_0_26 => hrdata_0_26, hrdata_0_24 => - hrdata_0_24, hrdata_0_27 => hrdata_0_27, hrdata_0_18 => - hrdata_0_18, hrdata_0_17 => hrdata_0_17, hrdata_0_11 => - hrdata_0_11, hrdata_0_12 => hrdata_0_12, hrdata_0_10 => - hrdata_0_10, hrdata_0_9 => hrdata_0_9, hrdata_0_8 => - hrdata_0_8, hrdata_0_23 => hrdata_0_23, hrdata_0_22 => - hrdata_0_22, hrdata_0_21 => hrdata_0_21, hrdata_0_2 => - hrdata_0_2, hrdata_0_3 => hrdata_0_3, hrdata_0_4 => - hrdata_0_4, hrdata_0_1 => hrdata_0_1, un1_m0_2_0(35) => - \un1_m0_2_0[35]\, ft_1_i_a2_0(0) => \ft_1_i_a2_0[0]\, - twowner_2_0_a2_0_0(0) => \twowner_2_0_a2_0_0[0]\, data_18 - => \data_0[18]\, data_28 => \data_0[28]\, data_30 => - \data_0[30]\, data_25 => \data_0[25]\, data_26 => - \data_0[26]\, data_31 => \data_0[31]\, data_24 => - \data_0[24]\, data_14 => \data_0[14]\, data_15 => - \data_0[15]\, data_12 => \data_0[12]\, data_13 => - data_1(13), adata_20 => \adata_0[20]\, adata_13 => - \adata_0[13]\, adata_17 => \adata_0[17]\, adata_31 => - \adata_0[31]\, adata_30 => \adata_0[30]\, adata_29 => - \adata_0[29]\, adata_28 => \adata_0[28]\, adata_26 => - \adata_0[26]\, adata_24 => \adata_0[24]\, adata_19 => - \adata_0[19]\, adata_18 => \adata_0[18]\, adata_16 => - \adata_0[16]\, adata_15 => \adata_0[15]\, adata_14 => - \adata_0[14]\, adata_11 => \adata_0[11]\, adata_8 => - \adata_0[8]\, adata_7 => \adata_0[7]\, adata_6 => - \adata_0[6]\, adata_1 => \adata_0[1]\, adata_0 => - \adata_0[0]\, adata_9 => \adata_0[9]\, adata_12 => - \adata_0[12]\, adata_2 => \adata_0[2]\, adata_3 => - \adata_0[3]\, adata_4 => \adata_0[4]\, adata_10 => - \adata_0[10]\, adata_27 => \adata_0[27]\, adata_22 => - \adata_0[22]\, adata_21 => \adata_0[21]\, adata_25 => - \adata_0[25]\, adata_23 => \adata_0[23]\, N_709 => N_709, - mmutlb_10_8_2_1_0_VCC => mmu_VCC, N_694 => N_694, N_695 - => N_695, N_696 => N_696, N_2702_i_0 => N_2702_i_0, - N_2711_i_0 => N_2711_i_0, N_2709_i_0 => N_2709_i_0, - fault_pri_2 => fault_pri_0, fault_pro_0 => fault_pro, - accexc_6 => accexc_6, un54_fault_pro_m => - un54_fault_pro_m, N_2699_i_0 => N_2699_i_0, N_2703_i_0 - => N_2703_i_0, G_80_0 => G_80_0, N_2714 => N_2714, - N_2717 => N_2717, N_2720 => N_2720, e => e, M_m => M_m, - fault_pro67 => fault_pro67, N_2701 => N_2701, un1_rst_i_0 - => un1_rst_i_0, N_264 => N_264, N_262 => N_262, N_78 => - N_78, N_82_0 => N_82_0, N_80 => N_80, fault_pro_1_0 => - fault_pro_1, fault_mexc_3_2 => fault_mexc_3_2, flush_op - => flush_op_1, N_264_0 => N_264_0, fault_mexc_0 => - fault_mexc, tlbactive => tlbactive_0, tlbdis => tlbdis, - trans_op => trans_op_3, N_78_0 => N_78_0, N_3160 => - N_3160, N_2571 => N_2571, N_262_0 => N_262_0, fault_pri_m - => fault_pri_m, fault_pri_1 => fault_pri_1, fault_pri - => fault_pri, trans_op_0 => trans_op_0, N_2488 => N_2488, - N_2482 => N_2482, N_2886 => N_2886, N_2887 => N_2887, - N_190 => N_190, N_192 => N_192, N_236 => N_236, N_293 => - N_293, N_317 => N_317, N_351 => N_351, N_353 => N_353, - N_415 => N_415, N_417 => N_417, N_419 => N_419, N_421 => - N_421, fault_trans_i_2 => fault_trans_i_2, fault_su => - fault_su_0, fault_read => fault_read, inv_1_0_a2_0_a2_0 - => inv_1_0_a2_0_a2_0, fault_trans => fault_trans, - fault_inv => fault_inv, fault_mexc => fault_mexc_0, - areq_ur_1_0_a2_0_0 => areq_ur_1_0_a2_0_0, N_2550 => - N_2550, N_2532 => N_2532, rst => rst, read => read, su - => su_0, fault_pro_1_iv_1 => fault_pro_1_iv_1, - fault_pro_1_iv_2 => fault_pro_1_iv_2, fault_pro_i => - fault_pro_i, N_82 => N_82, s1finished_0 => s1finished_0_0, - walk_use_0 => walk_use_0, lclk_c => lclk_c, N_86_i => - N_86_i); - - \un1_v.mmctrl2.fs.fav_1_sqmuxa_RNO\ : NOR2A - port map(A => \fault_isid_1_i[0]\, B => \un1_m0_2[42]\, Y - => fav_1_sqmuxa_RNO); - - \r.mmctrl2.fa[18]\ : DFN1E1 - port map(D => \fault_addr_1[30]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_72); - - \r.mmctrl2.fa_RNO_0[1]\ : MX2C - port map(A => \data[13]\, B => \data_0[13]\, S => - \un1_m0_2[35]\, Y => N_1577); - - \r.twowner_0_RNIKU46[0]\ : NOR2B - port map(A => \twowner_0[0]\, B => rst, Y => - \twowner_2_0_a2_0[0]\); - - \r.mmctrl2.fa_RNO_0[8]\ : MX2C - port map(A => \data[20]\, B => \data_0[20]\, S => - \un1_m0_2_1[35]\, Y => N_1584); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.mmctrl2.fa_RNO_0[3]\ : MX2C - port map(A => \data[15]\, B => \data_0[15]\, S => - \un1_m0_2_0[35]\, Y => N_1579); - - \r.mmctrl2.fa_RNO[18]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1594, - Y => \fault_addr_1[30]\); - - \p0.twod.finish_1_i_o2_m7_0_a2_RNO_0\ : NOR3B - port map(A => \twowner_0[0]\, B => hrdata_1_0_1(1), C => - N_2563_i_0_a4_m7_0_a2_1, Y => finish_1_i_o2_m7_0_a2_1); - - \r.splt_is2.tlbactive\ : DFN1 - port map(D => N_57, CLK => lclk_c, Q => tlbactive_2); - - \r.mmctrl2.fa_RNO_0[9]\ : MX2C - port map(A => \data[21]\, B => \data_0[21]\, S => - \un1_m0_2[35]\, Y => N_1585); - - \r.mmctrl2.fa[4]\ : DFN1E1 - port map(D => \fault_addr_1[16]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_58); - - \r.mmctrl2.fa[11]\ : DFN1E1 - port map(D => \fault_addr_1[23]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_65); - - \r.splt_ds1.op.flush_op\ : DFN1 - port map(D => N_47, CLK => lclk_c, Q => flush_op_1); - - \r.mmctrl2.fa_RNO[2]\ : AO1C - port map(A => \un1_m0_2_0[35]\, B => \N_66_0\, C => N_1578, - Y => \fault_addr_1[14]\); - - \r.splt_ds1.tlbactive_RNISK7K1\ : OR2A - port map(A => tlbactive_1, B => s1finished_0_0, Y => - \un2_m_tlb_type\); - - \r.mmctrl2.valid_RNO\ : OA1A - port map(A => valid_2, B => \fault_trans_RNIA0K0D1\, C => - rst, Y => N_1947_i); - - \r.mmctrl2.fa_RNO[6]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1582, - Y => \fault_addr_1[18]\); - - \r.mmctrl2.fa_RNO_0[11]\ : MX2C - port map(A => \data[23]\, B => \data_0[23]\, S => - \un1_m0_2_1[35]\, Y => N_582); - - \r.mmctrl2.fa[15]\ : DFN1E1 - port map(D => \fault_addr_1[27]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_69); - - \r.twactive_RNO\ : OA1A - port map(A => twactive_2, B => twactive_1_i_a2_0, C => rst, - Y => N_46); - - \r.mmctrl2.fa[13]\ : DFN1E1 - port map(D => \fault_addr_1[25]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_67); - - \r.splt_is1.op.flush_op_RNO\ : MX2C - port map(A => flush_op_i_0, B => flush_op_RNO_0, S => - flush_op_RNO_1, Y => flush_op_RNO); - - \r.mmctrl2.fa_RNO[11]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_582, - Y => \fault_addr_1[23]\); - - \r.mmctrl2.fa_RNO_0[13]\ : MX2C - port map(A => \data[25]\, B => \data_0[25]\, S => - \un1_m0_2[35]\, Y => N_584); - - \r.mmctrl2.fa_RNO[19]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66\, C => N_587, Y - => \fault_addr_1[31]\); - - \r.mmctrl2.fa_RNO[17]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_586, - Y => \fault_addr_1[29]\); - - \r.mmctrl2.fs.l[1]\ : DFN1E1 - port map(D => \fault_lvl_1_iv[1]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_44); - - \r.mmctrl2.fa[8]\ : DFN1E1 - port map(D => \fault_addr_1[20]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_62); - - \p0.un207_m_tlb_type_RNO\ : NOR2A - port map(A => un207_m_tlb_type_1, B => fault_pri, Y => - un207_m_tlb_type_2); - - \r.splt_is2.tlbactive_RNO\ : NOR2B - port map(A => rst, B => N_1748, Y => N_57); - - \r.splt_ds1.op.flush_op_RNO_0\ : MX2 - port map(A => flush_op_1, B => un76_m_tlb_type, S => - \un2_m_tlb_type\, Y => N_1757); - - \r.mmctrl2.fa_RNO[13]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_584, Y - => \fault_addr_1[25]\); - - \v.mmctrl2.fs.ow_2_sqmuxa_RNIBOO1D1\ : NOR2A - port map(A => \fault_trans_RNIA0K0D1\, B => ow_2_sqmuxa, Y - => fav_0_sqmuxa); - - \r.twowner_0_RNIRS742[0]\ : OR3A - port map(A => \twowner_0[0]\, B => d_N_6_1, C => N_207, Y - => N_4_5_i); - - \r.mmctrl2.fa_RNO[15]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1591, - Y => \fault_addr_1[27]\); - - \r.mmctrl2.fa[1]\ : DFN1E1 - port map(D => \fault_addr_1[13]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_55); - - \r.mmctrl2.fa_RNO_0[12]\ : MX2C - port map(A => \data[24]\, B => \data_0[24]\, S => - \un1_m0_2[35]\, Y => N_583); - - \r.mmctrl2.fa_RNO[4]\ : AO1C - port map(A => \un1_m0_2_0[35]\, B => \N_66_0\, C => N_1580, - Y => \fault_addr_1[16]\); - - \r.splt_is2.op.flush_op_RNIL4H81\ : OR3A - port map(A => N_2899, B => \s2_tlbstate[0]\, C => flush_op, - Y => \N_66\); - - \v.mmctrl2.fs.ow_2_sqmuxa_1\ : NOR2 - port map(A => fault_mexc_1, B => valid_2, Y => - ow_2_sqmuxa_1); - - \r.mmctrl2.fs.l[0]\ : DFN1E1 - port map(D => \fault_lvl_1_iv[0]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_43); - - \r.mmctrl2.fs.at_ls\ : DFN1E1 - port map(D => fault_read_1, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_40); - - \r.mmctrl2.fa[3]\ : DFN1E1 - port map(D => \fault_addr_1[15]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_57); - - \r.mmctrl2.valid\ : DFN1 - port map(D => N_1947_i, CLK => lclk_c, Q => \un1_m0_2[54]\); - - \r.mmctrl2.fs.at_su\ : DFN1E1 - port map(D => fault_su_1, CLK => lclk_c, E => fav_0_sqmuxa, - Q => un1_m0_2_42); - - \r.mmctrl2.fa_RNO_0[7]\ : MX2C - port map(A => \data[19]\, B => \data_0[19]\, S => - \un1_m0_2[35]\, Y => N_1583); - - \r.splt_is1.op.flush_op_RNO_0\ : OR2B - port map(A => rst, B => flush_op_RNO_2, Y => flush_op_RNO_0); - - \r.mmctrl2.fa_RNO_0[19]\ : MX2C - port map(A => \data[31]\, B => \data_0[31]\, S => - \un1_m0_2_1[35]\, Y => N_587); - - \r.mmctrl2.fa_RNO[1]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_1577, Y - => \fault_addr_1[13]\); - - \r.twowner_0_RNIRS742_0[0]\ : NOR3 - port map(A => \twowner_0[0]\, B => d_N_6_1, C => N_207, Y - => d_N_5_1); - - \p0.un207_m_tlb_type_RNILVF0C\ : AO1B - port map(A => fault_pro_1_iv_2, B => fault_pro_1_iv_1, C - => \un1_m0_2[35]\, Y => fault_pro_m); - - \r.mmctrl2.fa_RNO[8]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66\, C => N_1584, Y - => \fault_addr_1[20]\); - - \r.flush\ : DFN1 - port map(D => flush_RNO_0, CLK => lclk_c, Q => \flush\); - - \r.twowner_1[0]\ : DFN1 - port map(D => twactive_RNI0KM7C4, CLK => lclk_c, Q => - \twowner_1[0]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.mmctrl2.fs.l_RNO_1[1]\ : AOI1B - port map(A => walk_use, B => \fault_lvl_0[1]\, C => - \fault_isid_1_i[0]\, Y => N_2588); - - \r.mmctrl2.fa_RNO[5]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1581, - Y => \fault_addr_1[17]\); - - \r.twowner_0_RNIOC1EJ2[0]\ : AO1B - port map(A => twactive_2, B => N_180, C => - \twowner_2_0_a2_0[0]\, Y => N_2497); - - \p0.un207_m_tlb_type_RNI4B8O1_0\ : NOR2 - port map(A => fault_access_0_sqmuxa_0, B => - un207_m_tlb_type_i, Y => \un1_m0_2_1[35]\); - - \r.splt_is2.op.flush_op_RNIL4H81_0\ : OR3A - port map(A => N_2899, B => \s2_tlbstate[0]\, C => flush_op, - Y => \N_66_0\); - - \r.splt_is2.op.flush_op\ : DFN1 - port map(D => flush_op_RNO_3, CLK => lclk_c, Q => flush_op); - - \r.twactive_RNI0KM7C4\ : AO1B - port map(A => \twowner_2_0_a2_0_0[0]\, B => twactive_2, C - => N_2497, Y => twactive_RNI0KM7C4); - - \r.splt_is1.tlbactive_RNO_1\ : NOR2 - port map(A => trans_op, B => \flush\, Y => tlbactive_1_0); - - \r.twowner[0]\ : DFN1 - port map(D => twactive_RNI0KM7C4, CLK => lclk_c, Q => - \twowner[0]\); - - \r.splt_ds1.tlbactive\ : DFN1 - port map(D => N_49, CLK => lclk_c, Q => tlbactive_1); - - \r.mmctrl2.fa[16]\ : DFN1E1 - port map(D => \fault_addr_1[28]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_70); - - \r.mmctrl2.fa[6]\ : DFN1E1 - port map(D => \fault_addr_1[18]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_60); - - \r.mmctrl2.fa[14]\ : DFN1E1 - port map(D => \fault_addr_1[26]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_68); - - \p0.un207_m_tlb_type_RNO_0\ : NOR3 - port map(A => fault_mexc, B => fault_inv, C => fault_trans, - Y => un207_m_tlb_type_1); - - \r.mmctrl2.fa_RNO_0[2]\ : MX2C - port map(A => \data[14]\, B => \data_0[14]\, S => - \un1_m0_2_0[35]\, Y => N_1578); - - \r.splt_is1.tlbactive_RNO_0\ : NOR3C - port map(A => \un81_m_tlb_type\, B => tlbactive_1_0, C => - istate_0_sqmuxa, Y => tlbactive_1_2); - - \r.twowner_0[0]\ : DFN1 - port map(D => twactive_RNI0KM7C4, CLK => lclk_c, Q => - \twowner_0[0]\); - - \r.splt_is2.op.flush_op_RNIPFP03\ : NOR2 - port map(A => \un1_m0_2[35]\, B => \N_66\, Y => - \fault_isid_1_i[0]\); - - \r.mmctrl2.fs.ft[0]\ : DFN1E1 - port map(D => \ft_RNO[0]\, CLK => lclk_c, E => fav_0_sqmuxa, - Q => \un1_m0_2[38]\); - - \r.mmctrl2.fa_RNO_0[5]\ : MX2C - port map(A => \data[17]\, B => \data_0[17]\, S => - \un1_m0_2_0[35]\, Y => N_1581); - - \r.twowner_0_RNIU0661[0]\ : NOR3A - port map(A => hrdata_1_0_1(1), B => \twowner_0[0]\, C => - N_2563_i_0_a4_m7_0_a2_1, Y => N_2563_i_0_a4_m7_0_a2_1_0); - - \r.mmctrl2.fs.fav_RNO_0\ : NOR2B - port map(A => \un1_m0_2[37]\, B => fsread_i_0, Y => N_1744); - - \r.mmctrl2.fs.ow\ : DFN1E1 - port map(D => ow_1_sqmuxa, CLK => lclk_c, E => fav_0_sqmuxa, - Q => un1_m0_2_35); - - \r.splt_ds1.op.trans_op\ : DFN1 - port map(D => trans_op_RNIFAOCEQ1, CLK => lclk_c, Q => - trans_op_3); - - \r.mmctrl2.fs.at_su_RNO\ : AO1B - port map(A => \un1_m0_2_1[35]\, B => fault_su_0, C => - N_2490, Y => fault_su_1); - - \r.splt_ds2.tlbactive_RNO_0\ : MX2 - port map(A => tlbactive_0, B => tlbactive_1, S => - s1finished_0_0, Y => N_1755); - - \r.mmctrl2.fs.ft_RNO[0]\ : AOI1 - port map(A => \ft_1_i_a3_0[0]\, B => N_1629, C => - fault_mexc_1, Y => \ft_RNO[0]\); - - \r.splt_is1.op.flush_op_RNO_1\ : OR2A - port map(A => flush_op_2_m6_i_3, B => - mmudci_trans_op_1_sqmuxa_1, Y => flush_op_RNO_1); - - \v.mmctrl2.fs.ow_1_sqmuxa_RNO_0\ : NOR2B - port map(A => \un1_m0_2[42]\, B => ft, Y => ow_1_sqmuxa_0); - - \un1_v.mmctrl2.fs.fav_1_sqmuxa\ : OR2A - port map(A => ft, B => fav_1_sqmuxa_RNO, Y => fav_1_sqmuxa); - - \r.flush_RNO\ : OA1B - port map(A => \flush\, B => flush_1_sqmuxa, C => flush_0_0, - Y => flush_RNO_0); - - \r.twowner_0_RNIC5U6N[0]\ : MX2 - port map(A => d_N_5_1, B => walk_op_2_0_0_o2_0, S => - \twowner_0_RNIK5713[0]\, Y => N_2563_i); - - \r.mmctrl2.fa_RNO_0[6]\ : MX2C - port map(A => \data[18]\, B => \data_0[18]\, S => - \un1_m0_2_0[35]\, Y => N_1582); - - \r.mmctrl2.fs.fav_RNO\ : OR2 - port map(A => fav_0_sqmuxa_0, B => N_1744, Y => fav_RNO); - - \tlbsplit0.itlb0\ : mmutlb_10_8_0_1_0 - port map(address_0(31) => \address[31]\, address_0(30) => - \address[30]\, address_0(29) => \address[29]\, - address_0(28) => \address[28]\, address_0(27) => - \address[27]\, address_0(26) => \address[26]\, - address_0(25) => \address[25]\, address_0(24) => - \address[24]\, address_0(23) => \address[23]\, - address_0(22) => \address[22]\, address_0(21) => - \address[21]\, address_0(20) => \address[20]\, - address_0(19) => \address[19]\, address_0(18) => - \address[18]\, address_0(17) => \address[17]\, - address_0(16) => \address[16]\, address_0(15) => - \address[15]\, address_0(14) => \address[14]\, - address_0(13) => \address[13]\, address_0(12) => - \address[12]\, address_0(11) => \address[11]\, - address_0(10) => \address[10]\, address_0(9) => - \address[9]\, address_0(8) => \address[8]\, address_0(7) - => \address[7]\, address_0(6) => \address[6]\, - address_0(5) => \address[5]\, address_0(4) => - \address[4]\, address_0(3) => \address[3]\, address_0(2) - => \address[2]\, aaddr(31) => \aaddr[31]\, aaddr(30) => - \aaddr[30]\, aaddr(29) => \aaddr[29]\, aaddr(28) => - \aaddr[28]\, aaddr(27) => \aaddr[27]\, aaddr(26) => - \aaddr[26]\, aaddr(25) => \aaddr[25]\, aaddr(24) => - \aaddr[24]\, aaddr(23) => \aaddr[23]\, aaddr(22) => - \aaddr[22]\, aaddr(21) => \aaddr[21]\, aaddr(20) => - \aaddr[20]\, aaddr(19) => \aaddr[19]\, aaddr(18) => - \aaddr[18]\, aaddr(17) => \aaddr[17]\, aaddr(16) => - \aaddr[16]\, aaddr(15) => \aaddr[15]\, aaddr(14) => - \aaddr[14]\, aaddr(13) => \aaddr[13]\, aaddr(12) => - \aaddr[12]\, aaddr(11) => \aaddr[11]\, aaddr(10) => - \aaddr[10]\, aaddr(9) => \aaddr[9]\, aaddr(8) => - \aaddr[8]\, aaddr(7) => \aaddr[7]\, aaddr(6) => - \aaddr[6]\, aaddr(5) => \aaddr[5]\, aaddr(4) => - \aaddr[4]\, aaddr(3) => \aaddr[3]\, aaddr(2) => - \aaddr[2]\, ctx_0(7) => ctx_0(7), ctx_0(6) => ctx_0(6), - ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), ctx_0(3) => - ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => ctx_0(1), - ctx_0(0) => ctx_0(0), ctx(7) => ctx(7), ctx(6) => ctx(6), - ctx(5) => ctx(5), ctx(4) => ctx(4), ctx(3) => ctx(3), - ctx(2) => ctx(2), ctx(1) => ctx(1), ctx(0) => ctx(0), - fault_lvl_1 => \fault_lvl_0[1]\, lvl_i_1(1) => - \lvl_i_1[1]\, lvl_i_1(0) => \lvl_i_1[0]\, lvl_i_1_0(1) - => \lvl_i_1_0[1]\, un1_m0_30 => un1_m0_30, un1_m0_9 => - un1_m0_9, un1_m0_8 => un1_m0_8, un1_m0_5 => un1_m0_5, - un1_m0_1 => un1_m0_1, un1_m0_22 => un1_m0_22, un1_m0_6 - => un1_m0_6, un1_m0_0 => un1_m0_0, un1_m0_17 => - un1_m0_17, un1_m0_16 => un1_m0_16, un1_m0_7 => un1_m0_7, - un1_m0_4 => un1_m0_4, un1_m0_3 => un1_m0_3, un1_m0_2 => - un1_m0_2_d0, un1_itlb0_1(41) => \un1_itlb0_1[41]\, - un1_m0_2_0(35) => \un1_m0_2_0[35]\, data_0_29 => - \data[31]\, data_0_27 => \data[29]\, data_0_26 => - \data[28]\, data_0_20 => \data[22]\, data_0_12 => - \data[14]\, address(31) => address_0(31), address(30) => - address_0(30), address(29) => address_0(29), address(28) - => address_0(28), address(27) => address_0(27), - address(26) => address_0(26), address(25) => - address_0(25), address(24) => address_0(24), address(23) - => address_0(23), address(22) => address_0(22), - address(21) => address_0(21), address(20) => - address_0(20), address(19) => address_0(19), address(18) - => address_0(18), address(17) => address_0(17), - address(16) => address_0(16), address(15) => - address_0(15), address(14) => address_0(14), address(13) - => address_0(13), address(12) => address_0(12), - address(11) => address_0(11), address(10) => - address_0(10), address(9) => address_0(9), address(8) => - address_0(8), address(7) => address_0(7), address(6) => - address_0(6), address(5) => address_0(5), address(4) => - address_0(4), address(3) => address_0(3), address(2) => - address_0(2), data_14 => \data[16]\, data_21 => - \data[23]\, data_16 => \data[18]\, data_19 => \data[21]\, - data_17 => \data[19]\, data_15 => \data[17]\, data_24 => - \data[26]\, data_22 => \data[24]\, data_18 => \data[20]\, - data_25 => \data[27]\, data_13 => \data[15]\, data_11 => - \data[13]\, data_10 => \data[12]\, data_23 => \data[25]\, - data_28 => \data[30]\, fault_isid_1_i(0) => - \fault_isid_1_i[0]\, ft_1_i_a2_0(0) => \ft_1_i_a2_0[0]\, - hrdata_0_6 => hrdata_0_7, hrdata_0_25 => hrdata_0_26, - hrdata_0_20 => hrdata_0_21, hrdata_0_17 => hrdata_0_18, - hrdata_0_11 => hrdata_0_12, hrdata_0_23 => hrdata_0_24, - hrdata_0_0 => hrdata_0_1, hrdata_0_16 => hrdata_0_17, - hrdata_0_13 => hrdata_0_14, hrdata_0_15 => hrdata_0_16, - hrdata_0_14 => hrdata_0_15, hrdata_0_12 => hrdata_0_13, - hrdata_0_10 => hrdata_0_11, hrdata_0_9 => hrdata_0_10, - hrdata_0_8 => hrdata_0_9, hrdata_0_7 => hrdata_0_8, - hrdata_0_26 => hrdata_0_27, hrdata_0_22 => hrdata_0_23, - hrdata_0_21 => hrdata_0_22, hrdata_0_1 => hrdata_0_2, - hrdata_0_3 => hrdata_0_4, hrdata_0_2 => hrdata_0_3, - hrdata_9 => hrdata_9, hrdata_10 => hrdata_10, hrdata_11 - => hrdata_11, hrdata_13 => hrdata_13, hrdata_14 => - hrdata_14, hrdata_17 => hrdata_17, hrdata_24 => hrdata_24, - hrdata_6 => hrdata_6, hrdata_0_d0 => hrdata_0_d0, - hrdata_1 => hrdata_1, hrdata_8 => hrdata_8, hrdata_12 => - hrdata_12, hrdata_15 => hrdata_15, hrdata_16 => hrdata_16, - hrdata_18 => hrdata_18, hrdata_21 => hrdata_21, hrdata_22 - => hrdata_22, hrdata_23 => hrdata_23, hrdata_26 => - hrdata_26, hrdata_27 => hrdata_27, hrdata_28 => hrdata_28, - hrdata_29 => hrdata_29, hrdata_30 => hrdata_30, hrdata_31 - => hrdata_31, hrdata_2 => hrdata_2, hrdata_3 => hrdata_3, - hrdata_4 => hrdata_4, hrdata_7 => hrdata_7, hrdata_5 => - hrdata_5, adata_11 => \adata[11]\, adata_31 => - \adata[31]\, adata_30 => \adata[30]\, adata_29 => - \adata[29]\, adata_28 => \adata[28]\, adata_27 => - \adata[27]\, adata_25 => \adata[25]\, adata_24 => - \adata[24]\, adata_23 => \adata[23]\, adata_22 => - \adata[22]\, adata_20 => \adata[20]\, adata_17 => - \adata[17]\, adata_16 => \adata[16]\, adata_15 => - \adata[15]\, adata_14 => \adata[14]\, adata_13 => - \adata[13]\, adata_12 => \adata[12]\, adata_10 => - \adata[10]\, adata_9 => \adata[9]\, adata_8 => \adata[8]\, - adata_7 => \adata[7]\, adata_6 => \adata[6]\, adata_2 => - \adata[2]\, adata_1 => \adata[1]\, adata_0 => \adata[0]\, - adata_18 => \adata[18]\, adata_21 => \adata[21]\, - adata_26 => \adata[26]\, adata_4 => \adata[4]\, adata_3 - => \adata[3]\, adata_19 => \adata[19]\, s2_tlbstate_0 - => \s2_tlbstate[0]\, mmutlb_10_8_0_1_0_VCC => mmu_VCC, - N_264 => N_264, N_262 => N_262, N_78 => N_78, un1_rst_i_0 - => un1_rst_i_0, N_82 => N_82_0, N_80 => N_80, su => su, - N_2625 => N_2625, walk_use => walk_use, flush_op => - flush_op_0, N_2933 => N_2933, tlbactive => tlbactive_2, - N_180 => N_180, walk_op_ur => walk_op_ur, fault_pro_m => - fault_pro_m, fault_pro_1 => fault_pro_1, N_2899 => N_2899, - tlbdis => tlbdis, inv_1_0_a2_0_a2_0 => inv_1_0_a2_0_a2_0, - fault_mexc_2 => fault_mexc_0, fault_trans_i_2 => - fault_trans_i_2, N_264_0 => N_264_0, N_78_0 => N_78_0, - N_3160 => N_3160, N_2571 => N_2571, N_262_0 => N_262_0, - fault_pri_m_0 => fault_pri_m, fault_mexc_0 => fault_mexc, - fault_trans_RNIA0K0D1 => \fault_trans_RNIA0K0D1\, N_429 - => N_429, N_427 => N_427, N_2626 => N_2626, N_43 => N_43, - N_2482 => N_2482, N_423 => N_423, N_425 => N_425, N_2623 - => N_2623, N_2624 => N_2624, N_45 => N_45, N_319 => - N_319, N_321 => N_321, N_361 => N_361, N_363 => N_363, - N_365 => N_365, N_357 => N_357, N_1629 => N_1629, - fault_su => fault_su, twi_areq_ur_1_0_a3_i_0 => - twi_areq_ur_1_0_a3_i_0, fault_mexc_3_2 => fault_mexc_3_2, - fault_mexc_1 => fault_mexc_1, rst => rst, N_359 => N_359, - N_2563_i => N_2563_i, s1finished_0 => s1finished_0, - lclk_c => lclk_c, N_86_i => N_86_i); - - \r.mmctrl2.fa_RNO_0[14]\ : MX2C - port map(A => \data[26]\, B => \data_0[26]\, S => - \un1_m0_2[35]\, Y => N_585); - - \r.mmctrl2.fa[10]\ : DFN1E1 - port map(D => \fault_addr_1[22]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_64); - - \r.splt_ds1.tlbactive_RNIC0BHM3\ : NOR2B - port map(A => un76_m_tlb_type, B => \un2_m_tlb_type\, Y => - flush_1_sqmuxa); - - \r.mmctrl2.fa_RNO_0[15]\ : MX2C - port map(A => \data[27]\, B => \data_0[27]\, S => - \un1_m0_2_0[35]\, Y => N_1591); - - \r.mmctrl2.fs.ft_RNO_0[0]\ : NOR2A - port map(A => fault_pro_1, B => fault_pri_1, Y => - \ft_1_i_a3_0[0]\); - - \r.twowner_0_RNI6J8RK[0]\ : OR3B - port map(A => \twowner_0[0]\, B => areq_ur_1_0_a2_0_0, C - => N_2532, Y => N_2485); - - \r.splt_is1.op.flush_op\ : DFN1 - port map(D => flush_op_RNO, CLK => lclk_c, Q => flush_op_0); - - \r.mmctrl2.fs.ft[2]\ : DFN1E1 - port map(D => \ft_1[2]\, CLK => lclk_c, E => fav_0_sqmuxa, - Q => \un1_m0_2[40]\); - - \r.twowner_RNIB0CLN[0]\ : OR2A - port map(A => walk_op_ur, B => \twowner[0]\, Y => N_2487); - - \r.mmctrl2.fs.l_RNO_0[1]\ : NOR2B - port map(A => walk_use_0, B => \fault_lvl[1]\, Y => N_2575); - - \p0.un207_m_tlb_type_RNI4B8O1_1\ : NOR2 - port map(A => fault_access_0_sqmuxa_0, B => - un207_m_tlb_type_i, Y => \un1_m0_2[35]\); - - \r.twowner_2_RNI86JPN[0]\ : OR3 - port map(A => N_2563_i, B => twi_areq_ur_1_0_a3_i_0, C => - \twowner_2[0]\, Y => N_2484); - - \r.splt_ds1.op.trans_op_RNIA539EQ1\ : MX2A - port map(A => trans_op_3, B => trans_op_2, S => - \un2_m_tlb_type\, Y => trans_op_RNIA539EQ1); - - \r.mmctrl2.fa_RNO_0[0]\ : MX2C - port map(A => \data[12]\, B => \data_0[12]\, S => - \un1_m0_2_0[35]\, Y => N_1576); - - \v.mmctrl2.fs.ow_1_sqmuxa\ : NOR2B - port map(A => ow_1_sqmuxa_1, B => ow_2_sqmuxa_1, Y => - ow_1_sqmuxa); - - \r.splt_is1.tlbactive_RNO\ : OA1A - port map(A => tlbactive_1_2, B => flush_1_sqmuxa, C => rst, - Y => tlbactive_RNO); - - \p0.un76_m_tlb_type\ : NOR2A - port map(A => trans_op_2, B => flush_op_i_0, Y => - un76_m_tlb_type); - - \r.splt_is2.op.flush_op_RNI80SH1\ : OR2 - port map(A => flush_op, B => \un1_m0_2[1]\, Y => - fault_access_0_sqmuxa_0); - - \r.mmctrl2.fs.ft_RNO[2]\ : AO1A - port map(A => fault_mexc_3_2, B => N_1629, C => - fault_mexc_1, Y => \ft_1[2]\); - - \r.mmctrl2.fa_RNO[10]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66\, C => N_1586, Y - => \fault_addr_1[22]\); - - \r.mmctrl2.fa[0]\ : DFN1E1 - port map(D => \fault_addr_1[12]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_54); - - \r.splt_ds1.op.flush_op_RNO\ : NOR2B - port map(A => rst, B => N_1757, Y => N_47); - - \r.mmctrl2.fa[12]\ : DFN1E1 - port map(D => \fault_addr_1[24]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_66); - - \r.twowner_0_RNICE2V2[0]\ : NOR2A - port map(A => N_2563_i_0_a4_m7_0_a2_1_0, B => N_207, Y => - N_2563_i_0_a4_m7_0_a2_2); - - \r.mmctrl2.fa_RNO[12]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_583, Y - => \fault_addr_1[24]\); - - \r.mmctrl2.fs.at_id\ : DFN1E1 - port map(D => \fault_isid_1_i[0]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => \un1_m0_2[42]\); - - \v.mmctrl2.fs.ow_2_sqmuxa_RNIBOO1D1_0\ : NOR2A - port map(A => \fault_trans_RNIA0K0D1\, B => ow_2_sqmuxa, Y - => fav_0_sqmuxa_0); - - \r.mmctrl2.fs.fav\ : DFN1 - port map(D => fav_RNO, CLK => lclk_c, Q => \un1_m0_2[37]\); - - \r.mmctrl2.fa[19]\ : DFN1E1 - port map(D => \fault_addr_1[31]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_73); - - \v.mmctrl2.fs.ow_2_sqmuxa\ : AND2 - port map(A => fav_1_sqmuxa, B => ow_2_sqmuxa_1, Y => - ow_2_sqmuxa); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu_cache is - - port( hrdata_1_0_1 : in std_logic_vector(1 to 1); - data_2_17 : out std_logic; - data_2_12 : out std_logic; - data_2_1 : out std_logic; - data_1_10 : out std_logic; - data_1_8 : out std_logic; - nbo_5_0 : out std_logic_vector(1 downto 0); - htrans : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - htrans_tz : out std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 2); - hwdata_16 : out std_logic; - hwdata_3 : out std_logic; - hwdata_9 : out std_logic; - hwdata_11 : out std_logic; - hwdata_25 : out std_logic; - hwdata_27 : out std_logic; - hwdata_13 : out std_logic; - hwdata_4 : out std_logic; - hwdata_12 : out std_logic; - hwdata_23 : out std_logic; - hwdata_28 : out std_logic; - hwdata_1 : out std_logic; - hwdata_14 : out std_logic; - hwdata_0 : out std_logic; - hwdata_15 : out std_logic; - iosn_1 : in std_logic_vector(93 to 93); - hsize_5 : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(0 to 0); - hresp : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - addr_28 : out std_logic; - address_1 : out std_logic; - address_0 : out std_logic; - dataout : in std_logic_vector(35 downto 0); - data_0_0_31 : out std_logic; - data_0_0_24 : out std_logic; - data_0_0_29 : out std_logic; - data_0_0_13 : out std_logic; - data_0_0_30 : out std_logic; - data_0_0_27 : out std_logic; - data_0_0_20 : out std_logic; - data_0_0_14 : out std_logic; - data_0_0_25 : out std_logic; - data_0_0_16 : out std_logic; - data_0_0_17 : out std_logic; - data_0_0_28 : out std_logic; - data_0_0_8 : out std_logic; - data_0_0_11 : out std_logic; - data_0_0_21 : out std_logic; - data_0_0_4 : out std_logic; - data_0_0_26 : out std_logic; - data_0_0_0 : out std_logic; - data_0_0_12 : out std_logic; - data_0_0_15 : out std_logic; - data_0_0_7 : out std_logic; - mcdo_m_0_29 : out std_logic; - mcdo_m_0_22 : out std_logic; - mcdo_m_0_27 : out std_logic; - mcdo_m_0_0 : out std_logic; - mcdo_m_0_16 : out std_logic; - mcdo_m_0_21 : out std_logic; - mcdo_m_0_20 : out std_logic; - mcdo_m_0_17 : out std_logic; - mcdo_m_0_4 : out std_logic; - mcdo_m_0_7 : out std_logic; - rdatav_0_1_0_iv_4_22 : out std_logic; - rdatav_0_1_0_iv_4_20 : out std_logic; - rdatav_0_1_0_iv_4_0 : out std_logic; - rdatav_0_1_0_iv_4_14 : out std_logic; - rdatav_0_1_0_iv_5_6 : out std_logic; - rdatav_0_1_0_iv_5_1 : out std_logic; - rdatav_0_1_0_iv_5_0 : out std_logic; - rdatav_0_1_0_iv_5_4 : out std_logic; - eaddress_29 : in std_logic; - eaddress_22 : in std_logic; - eaddress_21 : in std_logic; - eaddress_13 : in std_logic; - eaddress_28 : in std_logic; - eaddress_18 : in std_logic; - eaddress_6 : in std_logic; - eaddress_10 : in std_logic; - eaddress_25 : in std_logic; - eaddress_23 : in std_logic; - eaddress_19 : in std_logic; - eaddress_9 : in std_logic; - eaddress_17 : in std_logic; - eaddress_27 : in std_logic; - eaddress_15 : in std_logic; - eaddress_5 : in std_logic; - eaddress_20 : in std_logic; - eaddress_2 : in std_logic; - eaddress_24 : in std_logic; - eaddress_16 : in std_logic; - eaddress_12 : in std_logic; - eaddress_4 : in std_logic; - eaddress_1 : in std_logic; - eaddress_8 : in std_logic; - eaddress_0 : in std_logic; - eaddress_3 : in std_logic; - eaddress_7 : in std_logic; - asi_4 : in std_logic; - asi_3 : in std_logic; - asi_2 : in std_logic; - asi_1 : in std_logic; - asi_0 : in std_logic_vector(0 to 0); - rdatav_0_1_0_iv_7 : out std_logic_vector(2 to 2); - rdatav_0_1_0_iv_0_2 : out std_logic_vector(10 to 10); - rdatav_0_1_1_iv_7 : out std_logic_vector(6 to 6); - edata2_0_iv : in std_logic_vector(23 downto 0); - newtag_1_0 : out std_logic_vector(27 downto 24); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dco_i_2 : out std_logic_vector(132 to 132); - size_0 : in std_logic_vector(1 downto 0); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 downto 24); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - faddr_RNI7879K : out std_logic_vector(0 to 0); - dci_m_0 : out std_logic; - dci_m_1 : out std_logic; - dci_m_2 : out std_logic; - dci_m_3 : out std_logic; - dci_m_5 : out std_logic; - dci_m_6 : out std_logic; - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - size_0_d0 : out std_logic; - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - data_10 : out std_logic; - data_8 : out std_logic; - data_5 : out std_logic; - data_13 : out std_logic; - data_24 : out std_logic; - data_29 : out std_logic; - un1_p0_2_0_350 : out std_logic; - un1_p0_2_0_0 : out std_logic; - fpc : in std_logic_vector(31 downto 2); - dataout_2 : in std_logic_vector(31 downto 0); - maddress : in std_logic_vector(31 downto 0); - un1_p0_6 : in std_logic_vector(0 to 0); - dataout_0 : in std_logic_vector(35 downto 0); - dataout_1 : in std_logic_vector(31 downto 0); - vitdatain_0_1_0 : in std_logic_vector(22 to 22); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - istate_RNIA8N5H : out std_logic_vector(0 to 0); - hrdata_0_15 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_3 : in std_logic; - data_0 : out std_logic_vector(31 downto 0); - rpc_0 : in std_logic; - rpc_1 : in std_logic; - rpc_3 : in std_logic; - rpc_2 : in std_logic; - rpc_7 : in std_logic; - rpc_8 : in std_logic; - rpc_5 : in std_logic; - rpc_6 : in std_logic; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - hrdata_9 : in std_logic; - hrdata_10 : in std_logic; - hrdata_11 : in std_logic; - hrdata_13 : in std_logic; - hrdata_14 : in std_logic; - hrdata_17 : in std_logic; - hrdata_24 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_8 : in std_logic; - hrdata_12 : in std_logic; - hrdata_15 : in std_logic; - hrdata_16 : in std_logic; - hrdata_18 : in std_logic; - hrdata_21 : in std_logic; - hrdata_22 : in std_logic; - hrdata_23 : in std_logic; - hrdata_26 : in std_logic; - hrdata_27 : in std_logic; - hrdata_2 : in std_logic; - hrdata_3 : in std_logic; - hrdata_4 : in std_logic; - hrdata_7 : in std_logic; - hrdata_5 : in std_logic; - hrdata_6 : in std_logic; - hrdata_28 : in std_logic; - hrdata_29 : in std_logic; - hrdata_30 : in std_logic; - hrdata_31 : in std_logic; - istate_RNIPSU8G : out std_logic_vector(0 to 0); - maddress_0_0 : in std_logic; - maddress_0_2 : in std_logic; - istate_RNIEC82C : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNI5V68H : out std_logic_vector(0 to 0); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - istate_RNIH0NBI : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - istate_RNI57KLB : out std_logic_vector(0 to 0); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - istate_RNI6HPAI : out std_logic_vector(0 to 0); - ctx : out std_logic_vector(7 downto 0); - un1_p0_2_i_0 : out std_logic; - un1_p0_2_i_4 : out std_logic; - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - istate_RNIJCMP6 : out std_logic_vector(0 to 0); - N_546 : in std_logic; - mmu_cache_VCC : in std_logic; - N_264 : in std_logic; - N_262 : in std_logic; - N_78 : in std_logic; - bo_5842_d_0 : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - hlock : out std_logic; - N_5054 : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - hbusreq : out std_logic; - un60_nbo : out std_logic; - N_457 : out std_logic; - N_462 : out std_logic; - N_467 : out std_logic; - werr_2_m_0 : out std_logic; - un91_nbo_i_0 : out std_logic; - N_138 : out std_logic; - N_139 : out std_logic; - bo_5842_d : out std_logic; - N_458 : out std_logic; - N_459 : out std_logic; - N_461 : out std_logic; - N_463 : out std_logic; - N_468 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_466 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - werr : out std_logic; - N_3254_0 : out std_logic; - enaddr : in std_logic; - lock_0 : in std_logic; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : out std_logic; - un1_addout_12 : in std_logic; - read_0_0 : in std_logic; - nullify : in std_logic; - intack : in std_logic; - nullify2_0_sqmuxa : in std_logic; - me_nullify2_1_2 : in std_logic; - un17_casaen_0_0 : in std_logic; - N_330 : out std_logic; - N_329 : out std_logic; - N_24 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - N_16_i_0 : out std_logic; - N_12_i_0 : out std_logic; - read_RNIEEGDD1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNICAQK41 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNIC9O9B1 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIEKS231 : out std_logic; - N_26_0 : out std_logic; - N_3387_i_0 : out std_logic; - N_3227_i_0 : out std_logic; - N_3239_i_0 : out std_logic; - mexc_1 : out std_logic; - un59_nbo : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - read_RNICKHE91 : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI0IQ7R : out std_logic; - N_3389_i_0 : out std_logic; - read_RNIRO4K31 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIQH64D1 : out std_logic; - read_1 : in std_logic; - r_N_6 : in std_logic; - N_3305 : out std_logic; - N_3846 : out std_logic; - N_144 : out std_logic; - N_258 : out std_logic; - N_259 : out std_logic; - N_267 : out std_logic; - N_269 : out std_logic; - N_270 : out std_logic; - flush_RNIGBB873 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - msu : in std_logic; - eenaddr : in std_logic; - write : in std_logic; - N_10 : out std_logic; - lclk_c : in std_logic; - holdn : out std_logic; - rst : in std_logic; - flush_i_0 : in std_logic; - hold_pc_7 : in std_logic; - de_hold_pc_1 : in std_logic; - un1_ici : out std_logic; - xc_exception_1_0 : in std_logic; - ldlock_2 : in std_logic; - un9_icc_check_bp : in std_logic; - ldlock_3_0 : in std_logic; - inull : in std_logic; - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_982 : out std_logic; - N_983 : out std_logic; - N_985 : out std_logic; - N_981 : out std_logic; - mds : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNI146O2 : out std_logic; - N_26 : in std_logic; - flush2 : out std_logic; - N_986 : out std_logic; - N_987 : out std_logic; - N_28 : in std_logic; - N_980 : out std_logic; - N_984 : out std_logic; - flush2_RNI5I3N7 : out std_logic; - flush2_RNIFMGM2 : out std_logic; - rbranch : in std_logic; - fbranch : in std_logic; - mexc : out std_logic; - su : in std_logic - ); - -end mmu_cache; - -architecture DEF_ARCH of mmu_cache is - - component VCC - port( Y : out std_logic - ); - end component; - - component mmu_dcache - port( data_1_19 : out std_logic; - data_1_18 : out std_logic; - data_1_17 : out std_logic; - data_1_16 : out std_logic; - data_1_15 : out std_logic; - data_1_14 : out std_logic; - data_1_13 : out std_logic; - data_1_12 : out std_logic; - data_1_9 : out std_logic; - data_1_8 : out std_logic; - data_1_5 : out std_logic; - data_1_4 : out std_logic; - data_1_3 : out std_logic; - data_1_2 : out std_logic; - data_1_1 : out std_logic; - data_1_0 : out std_logic; - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - size_1 : out std_logic_vector(1 downto 0); - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - dci_m_94 : out std_logic; - dci_m_93 : out std_logic; - dci_m_91 : out std_logic; - dci_m_90 : out std_logic; - dci_m_89 : out std_logic; - dci_m_88 : out std_logic; - faddr_RNI7879K : out std_logic_vector(0 to 0); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 downto 24) := (others => 'U'); - ctx : out std_logic_vector(7 downto 0); - hrdata_0_d0 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_25 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - size_0_0 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - dco_i_2 : out std_logic_vector(132 to 132); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - newtag_1_0_9 : out std_logic; - newtag_1_0_8 : out std_logic; - newtag_1_0_7 : out std_logic; - newtag_1_0_6 : out std_logic; - edata2_0_iv : in std_logic_vector(23 downto 0) := (others => 'U'); - asi_0_0 : out std_logic; - dataout_1 : in std_logic_vector(11 downto 10) := (others => 'U'); - size_1_d0 : in std_logic := 'U'; - bo_d : in std_logic_vector(2 to 2) := (others => 'U'); - rdatav_0_1_1_iv_7 : out std_logic_vector(6 to 6); - rdatav_0_1_0_iv_0_2_0 : out std_logic; - rdatav_0_1_0_iv_7_2 : out std_logic; - un1_m0_2_0 : in std_logic_vector(35 to 35) := (others => 'U'); - ics : out std_logic_vector(1 downto 0); - maddress_0_2 : in std_logic := 'U'; - maddress_0_0 : in std_logic := 'U'; - asi : in std_logic_vector(4 downto 0) := (others => 'U'); - data : out std_logic_vector(31 downto 0); - LVL_RNIT69H911 : in std_logic_vector(0 to 0) := (others => 'U'); - data_1_3_i_a3_6_2 : in std_logic := 'U'; - data_1_3_i_a3_6_4 : in std_logic := 'U'; - data_1_3_i_a3_6_0 : in std_logic := 'U'; - data_1_3_i_a3_6_1 : in std_logic := 'U'; - data_RNIKU1T4 : in std_logic_vector(16 to 16) := (others => 'U'); - un1_m0_2_73 : in std_logic := 'U'; - un1_m0_2_2 : in std_logic := 'U'; - un1_m0_2_4 : in std_logic := 'U'; - un1_m0_2_10 : in std_logic := 'U'; - un1_m0_2_9 : in std_logic := 'U'; - un1_m0_2_40 : in std_logic := 'U'; - un1_m0_2_5 : in std_logic := 'U'; - un1_m0_2_1 : in std_logic := 'U'; - un1_m0_2_7 : in std_logic := 'U'; - un1_m0_2_68 : in std_logic := 'U'; - un1_m0_2_38 : in std_logic := 'U'; - un1_m0_2_42 : in std_logic := 'U'; - un1_m0_2_59 : in std_logic := 'U'; - un1_m0_2_58 : in std_logic := 'U'; - un1_m0_2_67 : in std_logic := 'U'; - un1_m0_2_43 : in std_logic := 'U'; - un1_m0_2_65 : in std_logic := 'U'; - un1_m0_2_77 : out std_logic; - un1_m0_2_34 : in std_logic := 'U'; - un1_m0_2_78 : out std_logic; - un1_m0_2_75 : out std_logic; - un1_m0_2_6 : in std_logic := 'U'; - un1_m0_2_29 : in std_logic := 'U'; - un1_m0_2_19 : in std_logic := 'U'; - un1_m0_2_23 : in std_logic := 'U'; - un1_m0_2_60 : in std_logic := 'U'; - un1_m0_2_79 : out std_logic; - un1_m0_2_80 : out std_logic; - un1_m0_2_81 : out std_logic; - un1_m0_2_84 : out std_logic; - un1_m0_2_83 : out std_logic; - un1_m0_2_86 : out std_logic; - un1_m0_2_76 : out std_logic; - un1_m0_2_15 : in std_logic := 'U'; - un1_m0_2_11 : in std_logic := 'U'; - un1_m0_2_18 : in std_logic := 'U'; - un1_m0_2_85 : out std_logic; - un1_m0_2_54 : in std_logic := 'U'; - un1_m0_2_71 : in std_logic := 'U'; - un1_m0_2_55 : in std_logic := 'U'; - un1_m0_2_70 : in std_logic := 'U'; - un1_m0_2_61 : in std_logic := 'U'; - un1_m0_2_69 : in std_logic := 'U'; - un1_m0_2_37 : in std_logic := 'U'; - un1_m0_2_66 : in std_logic := 'U'; - un1_m0_2_56 : in std_logic := 'U'; - un1_m0_2_64 : in std_logic := 'U'; - un1_m0_2_62 : in std_logic := 'U'; - un1_m0_2_57 : in std_logic := 'U'; - un1_m0_2_41 : in std_logic := 'U'; - un1_m0_2_94 : in std_logic := 'U'; - un1_m0_2_91 : in std_logic := 'U'; - un1_m0_2_106 : in std_logic := 'U'; - un1_m0_2_96 : in std_logic := 'U'; - un1_m0_2_92 : in std_logic := 'U'; - un1_m0_2_95 : in std_logic := 'U'; - un1_m0_2_97 : in std_logic := 'U'; - un1_m0_2_93 : in std_logic := 'U'; - un1_m0_2_98 : in std_logic := 'U'; - un1_m0_2_33 : in std_logic := 'U'; - un1_m0_2_72 : in std_logic := 'U'; - un1_m0_2_39 : in std_logic := 'U'; - un1_m0_2_63 : in std_logic := 'U'; - un1_m0_2_44 : in std_logic := 'U'; - un1_m0_2_35 : in std_logic := 'U'; - un1_m0_2_36 : in std_logic := 'U'; - un1_m0_2_0_d0 : in std_logic := 'U'; - un1_m0_2_3 : in std_logic := 'U'; - un1_m0_2_12 : in std_logic := 'U'; - un1_m0_2_82 : out std_logic; - un1_m0_2_8 : in std_logic := 'U'; - un1_m0_2_31 : in std_logic := 'U'; - un1_m0_2_108 : in std_logic := 'U'; - eaddress_7 : in std_logic := 'U'; - eaddress_3 : in std_logic := 'U'; - eaddress_0 : in std_logic := 'U'; - eaddress_8 : in std_logic := 'U'; - eaddress_1 : in std_logic := 'U'; - eaddress_4 : in std_logic := 'U'; - eaddress_12 : in std_logic := 'U'; - eaddress_16 : in std_logic := 'U'; - eaddress_24 : in std_logic := 'U'; - eaddress_2 : in std_logic := 'U'; - eaddress_20 : in std_logic := 'U'; - eaddress_5 : in std_logic := 'U'; - eaddress_15 : in std_logic := 'U'; - eaddress_27 : in std_logic := 'U'; - eaddress_17 : in std_logic := 'U'; - eaddress_9 : in std_logic := 'U'; - eaddress_19 : in std_logic := 'U'; - eaddress_23 : in std_logic := 'U'; - eaddress_25 : in std_logic := 'U'; - eaddress_10 : in std_logic := 'U'; - eaddress_6 : in std_logic := 'U'; - eaddress_18 : in std_logic := 'U'; - eaddress_28 : in std_logic := 'U'; - eaddress_13 : in std_logic := 'U'; - eaddress_21 : in std_logic := 'U'; - eaddress_22 : in std_logic := 'U'; - eaddress_29 : in std_logic := 'U'; - rdatav_0_1_0_iv_5_18 : out std_logic; - rdatav_0_1_0_iv_5_14 : out std_logic; - rdatav_0_1_0_iv_5_15 : out std_logic; - rdatav_0_1_0_iv_5_20 : out std_logic; - rdatav_0_1_0_iv_4_23 : out std_logic; - rdatav_0_1_0_iv_4_9 : out std_logic; - rdatav_0_1_0_iv_4_29 : out std_logic; - rdatav_0_1_0_iv_4_31 : out std_logic; - mcdo_m_0_8 : out std_logic; - mcdo_m_0_5 : out std_logic; - mcdo_m_0_18 : out std_logic; - mcdo_m_0_21 : out std_logic; - mcdo_m_0_22 : out std_logic; - mcdo_m_0_17 : out std_logic; - mcdo_m_0_1 : out std_logic; - mcdo_m_0_28 : out std_logic; - mcdo_m_0_23 : out std_logic; - mcdo_m_0_30 : out std_logic; - data_0_23 : out std_logic; - data_0_22 : out std_logic; - data_0_19 : out std_logic; - data_0_18 : out std_logic; - data_0_7 : out std_logic; - data_0_15 : out std_logic; - data_0_12 : out std_logic; - data_0_0 : out std_logic; - data_0_26 : out std_logic; - data_0_4 : out std_logic; - data_0_21 : out std_logic; - data_0_11 : out std_logic; - data_0_8 : out std_logic; - data_0_28 : out std_logic; - data_0_17 : out std_logic; - data_0_16 : out std_logic; - data_0_25 : out std_logic; - data_0_14 : out std_logic; - data_0_20 : out std_logic; - data_0_27 : out std_logic; - data_0_30 : out std_logic; - data_0_13 : out std_logic; - data_0_29 : out std_logic; - data_0_24 : out std_logic; - data_0_31 : out std_logic; - dataout : in std_logic_vector(35 downto 0) := (others => 'U'); - ctxp_13 : out std_logic; - ctxp_16 : out std_logic; - ctxp_7 : out std_logic; - ctxp_10 : out std_logic; - ctxp_3 : out std_logic; - ctxp_8 : out std_logic; - ctxp_19 : out std_logic; - ctxp_17 : out std_logic; - ctxp_15 : out std_logic; - ctxp_14 : out std_logic; - ctxp_20 : out std_logic; - ctxp_18 : out std_logic; - ctxp_6 : out std_logic; - ctxp_21 : out std_logic; - ctxp_11 : out std_logic; - ctxp_4 : out std_logic; - ctxp_25 : out std_logic; - ctxp_0 : out std_logic; - ctxp_22 : out std_logic; - ctxp_23 : out std_logic; - ctxp_24 : out std_logic; - ctxp_5 : out std_logic; - ctxp_12 : out std_logic; - ctxp_9 : out std_logic; - ctxp_1 : out std_logic; - ctxp_2 : out std_logic; - diagdata_6 : in std_logic := 'U'; - diagdata_7 : in std_logic := 'U'; - diagdata_1 : in std_logic := 'U'; - diagdata_3 : in std_logic := 'U'; - diagdata_5 : in std_logic := 'U'; - diagdata_29 : in std_logic := 'U'; - diagdata_22 : in std_logic := 'U'; - diagdata_27 : in std_logic := 'U'; - diagdata_20 : in std_logic := 'U'; - diagdata_8 : in std_logic := 'U'; - diagdata_25 : in std_logic := 'U'; - diagdata_18 : in std_logic := 'U'; - diagdata_31 : in std_logic := 'U'; - diagdata_17 : in std_logic := 'U'; - diagdata_24 : in std_logic := 'U'; - diagdata_23 : in std_logic := 'U'; - diagdata_21 : in std_logic := 'U'; - diagdata_16 : in std_logic := 'U'; - diagdata_12 : in std_logic := 'U'; - diagdata_9 : in std_logic := 'U'; - diagdata_26 : in std_logic := 'U'; - diagdata_0 : in std_logic := 'U'; - diagdata_19 : in std_logic := 'U'; - diagdata_14 : in std_logic := 'U'; - diagdata_15 : in std_logic := 'U'; - diagdata_2 : in std_logic := 'U'; - diagdata_13 : in std_logic := 'U'; - diagdata_30 : in std_logic := 'U'; - diagdata_4 : in std_logic := 'U'; - diagdata_28 : in std_logic := 'U'; - address : out std_logic_vector(31 downto 0); - addr_30 : out std_logic; - addr_11 : out std_logic; - addr_6 : out std_logic; - addr_4 : out std_logic; - addr_7 : out std_logic; - addr_5 : out std_logic; - addr_3 : out std_logic; - addr_8 : out std_logic; - addr_10 : out std_logic; - addr_9 : out std_logic; - addr_2 : out std_logic; - dataout_0 : in std_logic_vector(31 downto 0) := (others => 'U'); - maddress : in std_logic_vector(31 downto 0) := (others => 'U'); - un1_p0_2_0 : out std_logic_vector(498 to 498); - ctx_0 : out std_logic_vector(7 downto 0); - size_1z : out std_logic; - enable : out std_logic; - N_10 : out std_logic; - write : in std_logic := 'U'; - eenaddr : in std_logic := 'U'; - msu : in std_logic := 'U'; - su : out std_logic; - read_3 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - N_415 : in std_logic := 'U'; - N_351 : in std_logic := 'U'; - flush_RNIGBB873 : out std_logic; - N_192 : in std_logic := 'U'; - N_190_0 : in std_logic := 'U'; - diagrdy : in std_logic := 'U'; - burst_0 : out std_logic; - N_264_0 : in std_logic := 'U'; - N_425 : out std_logic; - trans_op_0 : out std_logic; - flush_op_i_0 : out std_logic; - trans_op : out std_logic; - un2_m_tlb_type : in std_logic := 'U'; - tlbdis : out std_logic; - read_2 : out std_logic; - grant : in std_logic := 'U'; - N_317_0 : in std_logic := 'U'; - N_2886 : in std_logic := 'U'; - N_2887 : in std_logic := 'U'; - N_270 : out std_logic; - N_269 : out std_logic; - N_267 : out std_logic; - N_353 : in std_logic := 'U'; - N_259 : out std_logic; - N_258 : out std_logic; - N_236_0 : in std_logic := 'U'; - N_417 : in std_logic := 'U'; - N_144 : out std_logic; - N_3846 : out std_logic; - e : out std_logic; - N_421_0 : in std_logic := 'U'; - N_3305 : out std_logic; - nf : out std_logic; - N_262_0 : in std_logic := 'U'; - un54_fault_pro_m : in std_logic := 'U'; - M_m : in std_logic := 'U'; - r_N_6 : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_2 : out std_logic; - fault_pro : in std_logic := 'U'; - stpend_RNI6P41NG3 : out std_logic; - read_1 : in std_logic := 'U'; - read_RNIQH64D1 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIRO4K31 : out std_logic; - N_3389_i_0 : out std_logic; - read_RNI0IQ7R : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNICKHE91 : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - un59_nbo : in std_logic := 'U'; - lock_m : out std_logic; - N_2699_i_0 : in std_logic := 'U'; - mexc_1 : out std_logic; - N_3239_i_0 : out std_logic; - N_2701 : in std_logic := 'U'; - N_2703_i_0 : in std_logic := 'U'; - N_2714 : in std_logic := 'U'; - N_3227_i_0 : out std_logic; - N_3387_i_0 : out std_logic; - N_26 : out std_logic; - read_RNIEKS231 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIC9O9B1 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNICAQK41 : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIEEGDD1 : out std_logic; - N_12_i_0 : out std_logic; - N_16_i_0 : out std_logic; - N_696 : in std_logic := 'U'; - N_695 : in std_logic := 'U'; - flush_0_1_RNIBUA27S2 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - N_2702_i_0 : in std_logic := 'U'; - N_2717 : in std_logic := 'U'; - N_2720 : in std_logic := 'U'; - N_694 : in std_logic := 'U'; - N_2711_i_0 : in std_logic := 'U'; - fsread_i_0 : out std_logic; - N_24 : out std_logic; - N_329 : out std_logic; - N_330 : out std_logic; - N_78_0 : in std_logic := 'U'; - ba : in std_logic := 'U'; - hcache : in std_logic := 'U'; - cache : out std_logic; - cdwrite_0_sqmuxa_i_0_0 : in std_logic := 'U'; - lock_0 : out std_logic; - un17_casaen_0_0 : in std_logic := 'U'; - mexc : in std_logic := 'U'; - me_nullify2_1_2 : in std_logic := 'U'; - nullify2_0_sqmuxa : in std_logic := 'U'; - flush : in std_logic := 'U'; - hold_0 : in std_logic := 'U'; - fault_pro67 : in std_logic := 'U'; - req : out std_logic; - intack : in std_logic := 'U'; - N_523 : out std_logic; - fault_pri : in std_logic := 'U'; - iflush_1_0_a2_0 : out std_logic; - N_419 : in std_logic := 'U'; - N_2709_i_0 : in std_logic := 'U'; - nullify : in std_logic := 'U'; - flush_i_0 : in std_logic := 'U'; - N_293 : in std_logic := 'U'; - read_0 : in std_logic := 'U'; - rst : in std_logic := 'U'; - burst : out std_logic; - accexc_6 : in std_logic := 'U'; - un1_addout_12 : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : out std_logic; - G_80_0 : in std_logic := 'U'; - lock : in std_logic := 'U'; - ready : in std_logic := 'U'; - mmudci_trans_op_1_sqmuxa_1 : out std_logic; - hold : out std_logic; - enaddr : in std_logic := 'U'; - N_425_0 : out std_logic; - N_121 : out std_logic; - N_3254_0 : out std_logic; - e_0 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component mmu_acache - port( iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - hgrant : in std_logic_vector(0 to 0) := (others => 'U'); - hsize_5 : out std_logic_vector(1 to 1); - size : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - data_0_18 : in std_logic := 'U'; - data_0_1 : in std_logic := 'U'; - data_0_3 : in std_logic := 'U'; - data_0_17 : in std_logic := 'U'; - data_0_22 : in std_logic := 'U'; - data_0_21 : in std_logic := 'U'; - data_0_9 : in std_logic := 'U'; - data_0_23 : in std_logic := 'U'; - data_0_20 : in std_logic := 'U'; - data_0_4 : in std_logic := 'U'; - data_0_31 : in std_logic := 'U'; - data_0_26 : in std_logic := 'U'; - data_0_15 : in std_logic := 'U'; - data_0_7 : in std_logic := 'U'; - data_0_27 : in std_logic := 'U'; - data_0_25 : in std_logic := 'U'; - data_0_16 : in std_logic := 'U'; - data_0_30 : in std_logic := 'U'; - data_0_28 : in std_logic := 'U'; - data_0_14 : in std_logic := 'U'; - data_0_2 : in std_logic := 'U'; - data_0_11 : in std_logic := 'U'; - data_0_0 : in std_logic := 'U'; - data_0_12 : in std_logic := 'U'; - data_0_6 : in std_logic := 'U'; - data_0_19 : in std_logic := 'U'; - data_18 : in std_logic := 'U'; - data_1 : in std_logic := 'U'; - data_3 : in std_logic := 'U'; - data_17 : in std_logic := 'U'; - data_22 : in std_logic := 'U'; - data_21 : in std_logic := 'U'; - data_9 : in std_logic := 'U'; - data_23 : in std_logic := 'U'; - data_20 : in std_logic := 'U'; - data_4 : in std_logic := 'U'; - data_31 : in std_logic := 'U'; - data_26 : in std_logic := 'U'; - data_15 : in std_logic := 'U'; - data_7 : in std_logic := 'U'; - data_27 : in std_logic := 'U'; - data_25 : in std_logic := 'U'; - data_16 : in std_logic := 'U'; - data_30 : in std_logic := 'U'; - data_28 : in std_logic := 'U'; - data_14 : in std_logic := 'U'; - data_2 : in std_logic := 'U'; - data_11 : in std_logic := 'U'; - data_0_d0 : in std_logic := 'U'; - data_12 : in std_logic := 'U'; - data_6 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - hwdata_15 : out std_logic; - hwdata_0 : out std_logic; - hwdata_14 : out std_logic; - hwdata_1 : out std_logic; - hwdata_28 : out std_logic; - hwdata_23 : out std_logic; - hwdata_12 : out std_logic; - hwdata_4 : out std_logic; - hwdata_13 : out std_logic; - hwdata_27 : out std_logic; - hwdata_25 : out std_logic; - hwdata_11 : out std_logic; - hwdata_9 : out std_logic; - hwdata_3 : out std_logic; - hwdata_16 : out std_logic; - address_1 : in std_logic_vector(31 downto 2) := (others => 'U'); - haddr : out std_logic_vector(31 downto 2); - address_0 : in std_logic_vector(31 downto 2) := (others => 'U'); - htrans_tz : out std_logic_vector(1 to 1); - bo_d : out std_logic_vector(3 downto 2); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - address : in std_logic_vector(31 downto 2) := (others => 'U'); - htrans : out std_logic_vector(1 to 1); - nbo_5_0 : out std_logic_vector(1 downto 0); - size_1z : in std_logic := 'U'; - werr : out std_logic; - lclk_c : in std_logic := 'U'; - ready_0 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - mexc_1 : out std_logic; - ready : out std_logic; - N_466 : out std_logic; - lock : in std_logic := 'U'; - lock_m : in std_logic := 'U'; - hwrite_1_m_0 : out std_logic; - N_468 : out std_logic; - N_463 : out std_logic; - N_461 : out std_logic; - N_459 : out std_logic; - N_458 : out std_logic; - bo_5842_d : out std_logic; - N_139 : out std_logic; - N_138 : out std_logic; - un91_nbo_i_0 : out std_logic; - grant_1 : out std_logic; - hcache_1 : out std_logic; - werr_2_m_0 : out std_logic; - N_467 : out std_logic; - N_462 : out std_logic; - N_457 : out std_logic; - mexc_0 : out std_logic; - read_0 : in std_logic := 'U'; - mexc : out std_logic; - un60_nbo : out std_logic; - hbusreq : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - N_5054 : out std_logic; - burst_0 : in std_logic := 'U'; - hlock : out std_logic; - un59_nbo : out std_logic; - ba : out std_logic; - cache : in std_logic := 'U'; - read : in std_logic := 'U'; - burst : in std_logic := 'U'; - req_1 : in std_logic := 'U'; - req_0 : in std_logic := 'U'; - req : in std_logic := 'U'; - N_6093_i : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - grant_0 : out std_logic; - grant : out std_logic; - rst : in std_logic := 'U'; - bo_5842_d_0 : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component mmu_icache - port( istate_RNIJCMP6 : out std_logic_vector(0 to 0); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - ics : in std_logic_vector(1 downto 0) := (others => 'U'); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - un1_p0_2_i_4 : out std_logic; - un1_p0_2_i_0 : out std_logic; - ctx_5 : in std_logic := 'U'; - ctx_4 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - istate_RNI6HPAI : out std_logic_vector(0 to 0); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - istate_RNI57KLB : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - un1_m0_30 : in std_logic := 'U'; - un1_m0_5 : in std_logic := 'U'; - un1_m0_9 : in std_logic := 'U'; - un1_m0_8 : in std_logic := 'U'; - un1_m0_1 : in std_logic := 'U'; - un1_m0_22 : in std_logic := 'U'; - un1_m0_6 : in std_logic := 'U'; - un1_m0_0 : in std_logic := 'U'; - un1_m0_17 : in std_logic := 'U'; - un1_m0_16 : in std_logic := 'U'; - un1_m0_7 : in std_logic := 'U'; - un1_m0_4 : in std_logic := 'U'; - un1_m0_2 : in std_logic := 'U'; - un1_m0_3 : in std_logic := 'U'; - istate_RNIH0NBI : out std_logic_vector(0 to 0); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - istate_RNI5V68H : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIEC82C : out std_logic_vector(0 to 0); - maddress_0_2 : in std_logic := 'U'; - maddress_0_0 : in std_logic := 'U'; - istate_RNIPSU8G : out std_logic_vector(0 to 0); - diagdata_6 : out std_logic; - diagdata_15 : out std_logic; - diagdata_4 : out std_logic; - diagdata_19 : out std_logic; - diagdata_18 : out std_logic; - diagdata_17 : out std_logic; - diagdata_16 : out std_logic; - diagdata_20 : out std_logic; - diagdata_26 : out std_logic; - diagdata_25 : out std_logic; - diagdata_22 : out std_logic; - diagdata_14 : out std_logic; - diagdata_12 : out std_logic; - diagdata_9 : out std_logic; - diagdata_8 : out std_logic; - diagdata_5 : out std_logic; - diagdata_3 : out std_logic; - diagdata_0 : out std_logic; - diagdata_7 : out std_logic; - diagdata_27 : out std_logic; - diagdata_23 : out std_logic; - diagdata_24 : out std_logic; - diagdata_31 : out std_logic; - diagdata_29 : out std_logic; - diagdata_28 : out std_logic; - diagdata_21 : out std_logic; - diagdata_13 : out std_logic; - diagdata_2 : out std_logic; - diagdata_30 : out std_logic; - diagdata_1 : out std_logic; - hrdata_26 : in std_logic := 'U'; - hrdata_25 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - rpc_6 : in std_logic := 'U'; - rpc_5 : in std_logic := 'U'; - rpc_8 : in std_logic := 'U'; - rpc_7 : in std_logic := 'U'; - rpc_2 : in std_logic := 'U'; - rpc_3 : in std_logic := 'U'; - rpc_1 : in std_logic := 'U'; - rpc_0 : in std_logic := 'U'; - addr : in std_logic_vector(11 downto 2) := (others => 'U'); - data_0 : out std_logic_vector(31 downto 0); - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - istate_RNIA8N5H : out std_logic_vector(0 to 0); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - vitdatain_0_1_0 : in std_logic_vector(22 to 22) := (others => 'U'); - fault_isid_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - dataout_1 : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout_0 : in std_logic_vector(35 downto 32) := (others => 'U'); - ctx_0_5 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_4 : in std_logic := 'U'; - address : out std_logic_vector(31 downto 2); - bo_d : in std_logic_vector(3 to 3) := (others => 'U'); - un1_p0_6 : in std_logic_vector(0 to 0) := (others => 'U'); - maddress : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout_2 : in std_logic_vector(31 downto 0) := (others => 'U'); - fpc : in std_logic_vector(31 downto 2) := (others => 'U'); - asi : in std_logic_vector(0 to 0) := (others => 'U'); - un1_p0_2_0 : out std_logic_vector(148 to 148); - su_0 : in std_logic := 'U'; - diagrdy : out std_logic; - hold_0 : out std_logic; - mexc_0 : out std_logic; - fbranch : in std_logic := 'U'; - rbranch : in std_logic := 'U'; - flush2_RNIFMGM2 : out std_logic; - N_425_1 : in std_logic := 'U'; - flush2_RNI5I3N7 : out std_logic; - N_984 : out std_logic; - N_980 : out std_logic; - N_28 : in std_logic := 'U'; - N_987 : out std_logic; - N_986 : out std_logic; - e : in std_logic := 'U'; - flush2 : out std_logic; - N_26 : in std_logic := 'U'; - flush2_0_0_RNI146O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - mds : out std_logic; - su : out std_logic; - nf : in std_logic := 'U'; - N_981 : out std_logic; - N_429 : in std_logic := 'U'; - N_359 : in std_logic := 'U'; - N_2626 : in std_logic := 'U'; - N_43 : in std_logic := 'U'; - N_427 : in std_logic := 'U'; - N_2625 : in std_logic := 'U'; - N_6093_i : in std_logic := 'U'; - N_423 : in std_logic := 'U'; - N_425 : in std_logic := 'U'; - N_45 : in std_logic := 'U'; - N_2623 : in std_logic := 'U'; - N_365 : in std_logic := 'U'; - N_357 : in std_logic := 'U'; - N_985 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_363 : in std_logic := 'U'; - N_321 : in std_logic := 'U'; - N_319 : in std_logic := 'U'; - N_361 : in std_logic := 'U'; - N_2624 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - inull : in std_logic := 'U'; - hold : in std_logic := 'U'; - ldlock_3_0 : in std_logic := 'U'; - un9_icc_check_bp : in std_logic := 'U'; - trans_op_0 : out std_logic; - flush_op_i_0 : in std_logic := 'U'; - un2_m_tlb_type : in std_logic := 'U'; - stpend_RNI6P41NG3 : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_2 : in std_logic := 'U'; - ldlock_2 : in std_logic := 'U'; - xc_exception_1_0 : in std_logic := 'U'; - grant : in std_logic := 'U'; - iflush_1_0_a2_0 : in std_logic := 'U'; - N_121 : in std_logic := 'U'; - un1_ici : out std_logic; - fault_trans_RNIA0K0D1 : in std_logic := 'U'; - N_66_0 : in std_logic := 'U'; - de_hold_pc_1 : in std_logic := 'U'; - N_425_0 : in std_logic := 'U'; - flush_0 : out std_logic; - flush : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - ba : in std_logic := 'U'; - hcache : in std_logic := 'U'; - mexc : in std_logic := 'U'; - req : out std_logic; - e_0 : in std_logic := 'U'; - hold_pc_7 : in std_logic := 'U'; - istate_0_sqmuxa : out std_logic; - flush_i_0 : in std_logic := 'U'; - N_523 : in std_logic := 'U'; - ready : in std_logic := 'U'; - burst_0 : out std_logic; - burst : in std_logic := 'U'; - rst : in std_logic := 'U'; - un81_m_tlb_type : in std_logic := 'U'; - holdn : out std_logic; - cdwrite_0_sqmuxa_i_0_0 : out std_logic; - N_66 : in std_logic := 'U'; - enable : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component mmu - port( ctxp : in std_logic_vector(25 downto 0) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - data_0 : out std_logic; - data_1_d0 : out std_logic; - data_2_d0 : out std_logic; - data_3 : out std_logic; - data_4 : out std_logic; - data_6 : out std_logic; - data_7 : out std_logic; - data_8 : out std_logic; - data_9 : out std_logic; - data_10 : out std_logic; - data_11 : out std_logic; - data_2 : out std_logic_vector(31 downto 12); - data_RNIKU1T4 : out std_logic_vector(16 to 16); - maddress : in std_logic_vector(31 downto 12) := (others => 'U'); - data_1 : in std_logic_vector(31 downto 12) := (others => 'U'); - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - data_1_3_i_a3_6_2 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_0 : out std_logic; - hrdata_5 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - address_0 : in std_logic_vector(31 downto 2) := (others => 'U'); - un1_m0_2_d0 : out std_logic; - un1_m0_3 : out std_logic; - un1_m0_4 : out std_logic; - un1_m0_7 : out std_logic; - un1_m0_16 : out std_logic; - un1_m0_17 : out std_logic; - un1_m0_0 : out std_logic; - un1_m0_6 : out std_logic; - un1_m0_22 : out std_logic; - un1_m0_1 : out std_logic; - un1_m0_5 : out std_logic; - un1_m0_8 : out std_logic; - un1_m0_9 : out std_logic; - un1_m0_30 : out std_logic; - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - address : out std_logic_vector(31 downto 2); - hrdata_1_0_1 : in std_logic_vector(1 to 1) := (others => 'U'); - un1_m0_2_23 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_31 : out std_logic; - un1_m0_2_33 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_5 : out std_logic; - un1_m0_2_6 : out std_logic; - un1_m0_2_8 : out std_logic; - un1_m0_2_11 : out std_logic; - un1_m0_2_12 : out std_logic; - un1_m0_2_18 : out std_logic; - un1_m0_2_29 : out std_logic; - un1_m0_2_19 : out std_logic; - un1_m0_2_9 : out std_logic; - un1_m0_2_10 : out std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_75 : in std_logic := 'U'; - un1_m0_2_76 : in std_logic := 'U'; - un1_m0_2_77 : in std_logic := 'U'; - un1_m0_2_78 : in std_logic := 'U'; - un1_m0_2_79 : in std_logic := 'U'; - un1_m0_2_80 : in std_logic := 'U'; - un1_m0_2_81 : in std_logic := 'U'; - un1_m0_2_82 : in std_logic := 'U'; - un1_m0_2_83 : in std_logic := 'U'; - un1_m0_2_84 : in std_logic := 'U'; - un1_m0_2_85 : in std_logic := 'U'; - un1_m0_2_86 : in std_logic := 'U'; - un1_m0_2_97 : out std_logic; - un1_m0_2_96 : out std_logic; - un1_m0_2_95 : out std_logic; - un1_m0_2_93 : out std_logic; - un1_m0_2_108 : out std_logic; - un1_m0_2_91 : out std_logic; - un1_m0_2_106 : out std_logic; - un1_m0_2_92 : out std_logic; - un1_m0_2_98 : out std_logic; - un1_m0_2_94 : out std_logic; - un1_m0_2_44 : out std_logic; - un1_m0_2_43 : out std_logic; - un1_m0_2_73 : out std_logic; - un1_m0_2_72 : out std_logic; - un1_m0_2_71 : out std_logic; - un1_m0_2_70 : out std_logic; - un1_m0_2_69 : out std_logic; - un1_m0_2_68 : out std_logic; - un1_m0_2_67 : out std_logic; - un1_m0_2_66 : out std_logic; - un1_m0_2_65 : out std_logic; - un1_m0_2_64 : out std_logic; - un1_m0_2_63 : out std_logic; - un1_m0_2_62 : out std_logic; - un1_m0_2_61 : out std_logic; - un1_m0_2_60 : out std_logic; - un1_m0_2_59 : out std_logic; - un1_m0_2_58 : out std_logic; - un1_m0_2_57 : out std_logic; - un1_m0_2_56 : out std_logic; - un1_m0_2_55 : out std_logic; - un1_m0_2_54 : out std_logic; - un1_m0_2_40 : out std_logic; - un1_m0_2_42 : out std_logic; - un1_m0_2_35 : out std_logic; - un1_m0_2_36 : out std_logic; - un1_m0_2_34 : out std_logic; - un1_m0_2_39 : out std_logic; - un1_m0_2_38 : out std_logic; - un1_m0_2_37 : out std_logic; - un1_m0_2_0_d0 : out std_logic; - un1_m0_2_41 : out std_logic; - fault_isid_1_i : out std_logic_vector(0 to 0); - un1_m0_2_0 : out std_logic_vector(35 to 35); - mexc : in std_logic := 'U'; - req : out std_logic; - ba : in std_logic := 'U'; - bo_5842_d_0 : in std_logic := 'U'; - read_0 : out std_logic; - grant : in std_logic := 'U'; - su_0 : in std_logic := 'U'; - read : in std_logic := 'U'; - N_421 : out std_logic; - N_419 : out std_logic; - N_417 : out std_logic; - N_415 : out std_logic; - N_353 : out std_logic; - N_351 : out std_logic; - N_317 : out std_logic; - N_293 : out std_logic; - N_236 : out std_logic; - N_192 : out std_logic; - N_190 : out std_logic; - N_2887 : out std_logic; - N_2886 : out std_logic; - N_2701 : out std_logic; - fault_pro67 : out std_logic; - M_m : out std_logic; - e : in std_logic := 'U'; - N_2720 : out std_logic; - N_2717 : out std_logic; - N_2714 : out std_logic; - G_80_0 : out std_logic; - N_2703_i_0 : out std_logic; - N_2699_i_0 : out std_logic; - un54_fault_pro_m : out std_logic; - accexc_6 : out std_logic; - fault_pro : out std_logic; - fault_pri_0 : out std_logic; - N_2709_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2702_i_0 : out std_logic; - N_696 : out std_logic; - N_695 : out std_logic; - N_694 : out std_logic; - N_359 : out std_logic; - N_357 : out std_logic; - N_365 : out std_logic; - N_363 : out std_logic; - N_361 : out std_logic; - N_321 : out std_logic; - N_319 : out std_logic; - N_45 : out std_logic; - N_2624 : out std_logic; - N_2623 : out std_logic; - N_425 : out std_logic; - N_423 : out std_logic; - N_43 : out std_logic; - N_2626 : out std_logic; - N_427 : out std_logic; - N_429 : out std_logic; - N_262_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - tlbdis : in std_logic := 'U'; - N_2625 : out std_logic; - su : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - mmu_VCC : in std_logic := 'U'; - fsread_i_0 : in std_logic := 'U'; - trans_op_2 : in std_logic := 'U'; - flush_op_i_0 : in std_logic := 'U'; - mmudci_trans_op_1_sqmuxa_1 : in std_logic := 'U'; - N_66 : out std_logic; - trans_op_1 : in std_logic := 'U'; - un2_m_tlb_type : out std_logic; - flush : out std_logic; - trans_op : in std_logic := 'U'; - istate_0_sqmuxa : in std_logic := 'U'; - un81_m_tlb_type : out std_logic; - rst : in std_logic := 'U'; - N_546 : in std_logic := 'U'; - N_66_0 : out std_logic; - fault_trans_RNIA0K0D1 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - signal \ics[0]\, \ics[1]\, \un1_m0[34]\, \un1_m0[9]\, - \un1_m0[13]\, \un1_m0[12]\, \un1_m0[5]\, \un1_m0[26]\, - \un1_m0[10]\, \un1_m0[4]\, \un1_m0[21]\, \un1_m0[20]\, - \un1_m0[11]\, \un1_m0[8]\, \un1_m0[6]\, \un1_m0[7]\, - \diagdata[6]\, \diagdata[15]\, \diagdata[4]\, - \diagdata[19]\, \diagdata[18]\, \diagdata[17]\, - \diagdata[16]\, \diagdata[20]\, \diagdata[26]\, - \diagdata[25]\, \diagdata[22]\, \diagdata[14]\, - \diagdata[12]\, \diagdata[9]\, \diagdata[8]\, - \diagdata[5]\, \diagdata[3]\, \diagdata[0]\, - \diagdata[7]\, \diagdata[27]\, \diagdata[23]\, - \diagdata[24]\, \diagdata[31]\, \diagdata[29]\, - \diagdata[28]\, \diagdata[21]\, \diagdata[13]\, - \diagdata[2]\, \diagdata[30]\, \diagdata[1]\, \addr[2]\, - \addr[3]\, \addr[4]\, \addr[5]\, \addr[6]\, \addr[7]\, - \addr[8]\, \addr[9]\, \addr[10]\, \addr[11]\, - \fault_isid_1_i[0]\, \ctx_0[7]\, \ctx_0[2]\, \ctx_0[6]\, - \address[2]\, \address[3]\, \address[4]\, \address[5]\, - \address[6]\, \address[7]\, \address[8]\, \address[9]\, - \address[10]\, \address[11]\, \address[12]\, - \address[13]\, \address[14]\, \address[15]\, - \address[16]\, \address[17]\, \address[18]\, - \address[19]\, \address[20]\, \address[21]\, - \address[22]\, \address[23]\, \address[24]\, - \address[25]\, \address[26]\, \address[27]\, - \address[28]\, \address[29]\, \address[30]\, - \address[31]\, \bo_d[3]\, \asi[0]\, diagrdy, hold, N_425, - e, su_0, nf, N_429, N_359, N_2626, N_43, N_427, N_2625, - N_6093_i, N_423, N_425_0, N_45, N_2623, N_365, N_357, - N_363, N_321, N_319, N_361, N_2624, hold_0, trans_op, - flush_op_i_0, un2_m_tlb_type, stpend_RNI6P41NG3, - vaddr_1_sqmuxa_0_a2_2, grant, iflush_1_0_a2_0, N_121, - fault_trans_RNIA0K0D1, N_66_0, N_425_0_0, flush, flush_0, - trans_op_0, ba, hcache, mexc_0, req, e_0, istate_0_sqmuxa, - N_523, ready, burst, burst_0, un81_m_tlb_type, - cdwrite_0_sqmuxa_i_0_0, N_66, enable, \data[31]\, - \data[30]\, \data[28]\, \data[27]\, \data[26]\, - \data[25]\, \data[21]\, \data[20]\, \data[17]\, - \data[16]\, \data[15]\, \data[14]\, \data[12]\, \size[1]\, - \ctx[0]\, \ctx[1]\, \ctx[3]\, \ctx[4]\, \ctx[5]\, - \bo_d[2]\, \un1_m0_2_0[35]\, \data[0]\, \data[1]\, - \data[2]\, \data[3]\, \data[4]\, \data[6]\, \data[7]\, - \data[9]\, \data[11]\, \data_1[12]\, \data_1[13]\, - \data_1[14]\, \data_1[15]\, \data_1[16]\, \data_1[17]\, - \data[18]\, \data[19]\, \data_1[20]\, \data_1[21]\, - \data[22]\, \data[23]\, \data_1[24]\, \data_1[25]\, - \data_1[26]\, \data_1[27]\, \data_1[28]\, \data_1[29]\, - \data_1[30]\, \data_1[31]\, \LVL_RNIT69H911[0]\, - \data_1_3_i_a3_6[27]\, \data_1_3_i_a3_6[29]\, - \data_1_3_i_a3_6[25]\, \data_1_3_i_a3_6[26]\, - \data_RNIKU1T4[16]\, \un1_m0_2[74]\, \un1_m0_2[3]\, - \un1_m0_2[5]\, \un1_m0_2[11]\, \un1_m0_2[10]\, - \un1_m0_2[41]\, \un1_m0_2[6]\, \un1_m0_2[2]\, - \un1_m0_2[8]\, \un1_m0_2[69]\, \un1_m0_2[39]\, - \un1_m0_2[43]\, \un1_m0_2[60]\, \un1_m0_2[59]\, - \un1_m0_2[68]\, \un1_m0_2[44]\, \un1_m0_2[66]\, - \un1_m0_2[78]\, \un1_m0_2[35]\, \un1_m0_2[79]\, - \un1_m0_2[76]\, \un1_m0_2[7]\, \un1_m0_2[30]\, - \un1_m0_2[20]\, \un1_m0_2[24]\, \un1_m0_2[61]\, - \un1_m0_2[80]\, \un1_m0_2[81]\, \un1_m0_2[82]\, - \un1_m0_2[85]\, \un1_m0_2[84]\, \un1_m0_2[87]\, - \un1_m0_2[77]\, \un1_m0_2[16]\, \un1_m0_2[12]\, - \un1_m0_2[19]\, \un1_m0_2[86]\, \un1_m0_2[55]\, - \un1_m0_2[72]\, \un1_m0_2[56]\, \un1_m0_2[71]\, - \un1_m0_2[62]\, \un1_m0_2[70]\, \un1_m0_2[38]\, - \un1_m0_2[67]\, \un1_m0_2[57]\, \un1_m0_2[65]\, - \un1_m0_2[63]\, \un1_m0_2[58]\, \un1_m0_2[42]\, - \un1_m0_2[95]\, \un1_m0_2[92]\, \un1_m0_2[107]\, - \un1_m0_2[97]\, \un1_m0_2[93]\, \un1_m0_2[96]\, - \un1_m0_2[98]\, \un1_m0_2[94]\, \un1_m0_2[99]\, - \un1_m0_2[34]\, \un1_m0_2[73]\, \un1_m0_2[40]\, - \un1_m0_2[64]\, \un1_m0_2[45]\, \un1_m0_2[36]\, - \un1_m0_2[37]\, \un1_m0_2[1]\, \un1_m0_2[4]\, - \un1_m0_2[13]\, \un1_m0_2[83]\, \un1_m0_2[9]\, - \un1_m0_2[32]\, \un1_m0_2[109]\, \data_1[23]\, - \data_1[22]\, \data_1[19]\, \data_1[18]\, \ctxp[13]\, - \ctxp[16]\, \ctxp[7]\, \ctxp[10]\, \ctxp[3]\, \ctxp[8]\, - \ctxp[19]\, \ctxp[17]\, \ctxp[15]\, \ctxp[14]\, - \ctxp[20]\, \ctxp[18]\, \ctxp[6]\, \ctxp[21]\, \ctxp[11]\, - \ctxp[4]\, \ctxp[25]\, \ctxp[0]\, \ctxp[22]\, \ctxp[23]\, - \ctxp[24]\, \ctxp[5]\, \ctxp[12]\, \ctxp[9]\, \ctxp[1]\, - \ctxp[2]\, \address_0[2]\, \address_0[3]\, \address_0[4]\, - \address_0[5]\, \address_0[6]\, \address_0[7]\, - \address_0[8]\, \address_0[9]\, \address_0[10]\, - \address_0[11]\, \address_0[12]\, \address_0[13]\, - \address_0[14]\, \address_0[15]\, \address_0[16]\, - \address_0[17]\, \address_0[18]\, \address_0[19]\, - \address_0[20]\, \address_0[21]\, \address_0[22]\, - \address_0[23]\, \address_0[24]\, \address_0[25]\, - \address_0[26]\, \address_0[27]\, \address_0[28]\, - \address_0[29]\, \address_0[30]\, \address_0[31]\, - \ctx_0[0]\, \ctx_0[1]\, \ctx_0[3]\, \ctx_0[4]\, - \ctx_0[5]\, size, su_1, read, N_415, N_351, N_192, N_190, - trans_op_1, tlbdis, read_0, grant_0, N_317, N_2886, - N_2887, N_353, N_236, N_417, N_421, un54_fault_pro_m, M_m, - fault_pro, lock_m, N_2699_i_0, N_2701, N_2703_i_0, N_2714, - N_696, N_695, N_2702_i_0, N_2717, N_2720, N_694, - N_2711_i_0, fsread_i_0, cache, lock, mexc_2, fault_pro67, - req_0, fault_pri, N_419, N_2709_i_0, N_293, burst_1, - accexc_6, G_80_0, ready_0, mmudci_trans_op_1_sqmuxa_1, - \data_2[18]\, \data_1[1]\, \data_1[3]\, \data_2[17]\, - \data_2[22]\, \data_2[21]\, \data_1[9]\, \data_2[23]\, - \data_2[20]\, \data_1[4]\, \data_2[31]\, \data_2[26]\, - \data_2[15]\, \data_1[7]\, \data_2[27]\, \data_2[25]\, - \data_2[16]\, \data_2[30]\, \data_2[28]\, \data_2[14]\, - \data_1[2]\, \data_1[11]\, \data_1[0]\, \data_2[12]\, - \data_1[6]\, \data_2[19]\, \address_1[2]\, \address_1[3]\, - \address_1[6]\, \address_1[7]\, \address_1[8]\, - \address_1[9]\, \address_1[10]\, \address_1[11]\, - \address_1[12]\, \address_1[14]\, \address_1[15]\, - \address_1[16]\, \address_1[17]\, \address_1[18]\, - \address_1[19]\, \address_1[20]\, \address_1[21]\, - \address_1[22]\, \address_1[23]\, \address_1[24]\, - \address_1[25]\, \address_1[26]\, \address_1[27]\, - \address_1[29]\, \address_1[30]\, \address_1[31]\, - \address_1[4]\, \address_1[28]\, \address_1[5]\, - \address_1[13]\, read_2, mexc_3, \un59_nbo\, req_1, - grant_1, \ctx[2]\, \ctx[6]\, \ctx[7]\, \bo_5842_d_0\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : mmu_dcache - Use entity work.mmu_dcache(DEF_ARCH); - for all : mmu_acache - Use entity work.mmu_acache(DEF_ARCH); - for all : mmu_icache - Use entity work.mmu_icache(DEF_ARCH); - for all : mmu - Use entity work.mmu(DEF_ARCH); -begin - - ctx(7) <= \ctx[7]\; - ctx(6) <= \ctx[6]\; - ctx(5) <= \ctx[5]\; - ctx(4) <= \ctx[4]\; - ctx(3) <= \ctx[3]\; - ctx(2) <= \ctx[2]\; - ctx(1) <= \ctx[1]\; - ctx(0) <= \ctx[0]\; - bo_5842_d_0 <= \bo_5842_d_0\; - un59_nbo <= \un59_nbo\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - dcache0 : mmu_dcache - port map(data_1_19 => \data[31]\, data_1_18 => \data[30]\, - data_1_17 => data_29, data_1_16 => \data[28]\, data_1_15 - => \data[27]\, data_1_14 => \data[26]\, data_1_13 => - \data[25]\, data_1_12 => data_24, data_1_9 => \data[21]\, - data_1_8 => \data[20]\, data_1_5 => \data[17]\, data_1_4 - => \data[16]\, data_1_3 => \data[15]\, data_1_2 => - \data[14]\, data_1_1 => data_13, data_1_0 => \data[12]\, - faddr_RNIB0UOO(2) => faddr_RNIB0UOO(2), - dstate_i_RNI29QQ7J3(8) => dstate_i_RNI29QQ7J3(8), - xaddress_RNITFTTE(3) => xaddress_RNITFTTE(3), - xaddress_RNIFP43F(2) => xaddress_RNIFP43F(2), size_1(1) - => \size[1]\, size_1(0) => size_0_d0, faddr_RNI7MK691(6) - => faddr_RNI7MK691(6), dci_m_94 => dci_m_6, dci_m_93 => - dci_m_5, dci_m_91 => dci_m_3, dci_m_90 => dci_m_2, - dci_m_89 => dci_m_1, dci_m_88 => dci_m_0, - faddr_RNI7879K(0) => faddr_RNI7879K(0), faddr_RNIEHR0O(1) - => faddr_RNIEHR0O(1), edata2_iv_i_0(31) => - edata2_iv_i_0(31), edata2_iv_i_0(30) => edata2_iv_i_0(30), - edata2_iv_i_0(29) => edata2_iv_i_0(29), edata2_iv_i_0(28) - => edata2_iv_i_0(28), edata2_iv_i_0(27) => - edata2_iv_i_0(27), edata2_iv_i_0(26) => edata2_iv_i_0(26), - edata2_iv_i_0(25) => edata2_iv_i_0(25), edata2_iv_i_0(24) - => edata2_iv_i_0(24), ctx(7) => \ctx[7]\, ctx(6) => - \ctx[6]\, ctx(5) => \ctx[5]\, ctx(4) => \ctx[4]\, ctx(3) - => \ctx[3]\, ctx(2) => \ctx[2]\, ctx(1) => \ctx[1]\, - ctx(0) => \ctx[0]\, hrdata_0_d0 => hrdata_5, hrdata_24 - => hrdata_29, hrdata_26 => hrdata_31, hrdata_25 => - hrdata_30, hrdata_23 => hrdata_28, hrdata_1 => hrdata_6, - dstate_RNIC3QA81(1) => dstate_RNIC3QA81(1), - dstate_RNIFPT581(1) => dstate_RNIFPT581(1), size_0_0 => - size_0(0), hrdata_0_7 => hrdata_0_7, hrdata_0_11 => - hrdata_0_11, hrdata_0_9 => hrdata_0_9, hrdata_0_21 => - hrdata_0_21, hrdata_0_4 => hrdata_0_4, hrdata_0_3 => - hrdata_0_3, hrdata_0_8 => hrdata_0_8, hrdata_0_15 => - hrdata_0_15, hrdata_0_27 => hrdata_0_27, hrdata_0_23 => - hrdata_0_23, hrdata_0_1 => hrdata_0_1, hrdata_0_13 => - hrdata_0_13, hrdata_0_12 => hrdata_0_12, hrdata_0_10 => - hrdata_0_10, hrdata_0_2 => hrdata_0_2, hrdata_0_14 => - hrdata_0_14, hrdata_0_26 => hrdata_0_26, hrdata_0_24 => - hrdata_0_24, hrdata_0_22 => hrdata_0_22, hrdata_0_18 => - hrdata_0_18, hrdata_0_17 => hrdata_0_17, hrdata_0_16 => - hrdata_0_16, hrdata_0_0 => hrdata_0_0, dco_i_2(132) => - dco_i_2(132), dstate_i_0_RNIH0PPES(8) => - dstate_i_0_RNIH0PPES(8), dstate_RNI1G47MJ(1) => - dstate_RNI1G47MJ(1), dstate_RNIFS6E51(1) => - dstate_RNIFS6E51(1), xaddress_RNI1Q9ST1(1) => - xaddress_RNI1Q9ST1(1), xaddress_RNIEHIUT1(1) => - xaddress_RNIEHIUT1(1), xaddress_RNILHOK61(1) => - xaddress_RNILHOK61(1), xaddress_RNILK99L1(1) => - xaddress_RNILK99L1(1), xaddress_RNI1I3MQ1(0) => - xaddress_RNI1I3MQ1(0), xaddress_RNIK99NK1(1) => - xaddress_RNIK99NK1(1), xaddress_RNIP2BVK1(1) => - xaddress_RNIP2BVK1(1), xaddress_RNIJI2O22(1) => - xaddress_RNIJI2O22(1), xaddress_RNITMH17S2(12) => - xaddress_RNITMH17S2(12), xaddress_RNICFI17S2(13) => - xaddress_RNICFI17S2(13), xaddress_RNI1D927S2(20) => - xaddress_RNI1D927S2(20), xaddress_RNI9MB27S2(23) => - xaddress_RNI9MB27S2(23), xaddress_RNI0GI17S2(17) => - xaddress_RNI0GI17S2(17), xaddress_RNIC5A27S2(21) => - xaddress_RNIC5A27S2(21), xaddress_RNIN7J17S2(14) => - xaddress_RNIN7J17S2(14), xaddress_RNIID927S2(16) => - xaddress_RNIID927S2(16), xaddress_RNI2MB27S2(15) => - xaddress_RNI2MB27S2(15), dstate_i_0_RNIL7FGFS(8) => - dstate_i_0_RNIL7FGFS(8), xaddress_RNID252J1(10) => - xaddress_RNID252J1(10), newtag_1_0_9 => newtag_1_0(27), - newtag_1_0_8 => newtag_1_0(26), newtag_1_0_7 => - newtag_1_0(25), newtag_1_0_6 => newtag_1_0(24), - edata2_0_iv(23) => edata2_0_iv(23), edata2_0_iv(22) => - edata2_0_iv(22), edata2_0_iv(21) => edata2_0_iv(21), - edata2_0_iv(20) => edata2_0_iv(20), edata2_0_iv(19) => - edata2_0_iv(19), edata2_0_iv(18) => edata2_0_iv(18), - edata2_0_iv(17) => edata2_0_iv(17), edata2_0_iv(16) => - edata2_0_iv(16), edata2_0_iv(15) => edata2_0_iv(15), - edata2_0_iv(14) => edata2_0_iv(14), edata2_0_iv(13) => - edata2_0_iv(13), edata2_0_iv(12) => edata2_0_iv(12), - edata2_0_iv(11) => edata2_0_iv(11), edata2_0_iv(10) => - edata2_0_iv(10), edata2_0_iv(9) => edata2_0_iv(9), - edata2_0_iv(8) => edata2_0_iv(8), edata2_0_iv(7) => - edata2_0_iv(7), edata2_0_iv(6) => edata2_0_iv(6), - edata2_0_iv(5) => edata2_0_iv(5), edata2_0_iv(4) => - edata2_0_iv(4), edata2_0_iv(3) => edata2_0_iv(3), - edata2_0_iv(2) => edata2_0_iv(2), edata2_0_iv(1) => - edata2_0_iv(1), edata2_0_iv(0) => edata2_0_iv(0), asi_0_0 - => \asi[0]\, dataout_1(11) => dataout_1(11), - dataout_1(10) => dataout_1(10), size_1_d0 => size_0(1), - bo_d(2) => \bo_d[2]\, rdatav_0_1_1_iv_7(6) => - rdatav_0_1_1_iv_7(6), rdatav_0_1_0_iv_0_2_0 => - rdatav_0_1_0_iv_0_2(10), rdatav_0_1_0_iv_7_2 => - rdatav_0_1_0_iv_7(2), un1_m0_2_0(35) => \un1_m0_2_0[35]\, - ics(1) => \ics[1]\, ics(0) => \ics[0]\, maddress_0_2 => - maddress_0_2, maddress_0_0 => maddress_0_0, asi(4) => - asi_4, asi(3) => asi_3, asi(2) => asi_2, asi(1) => asi_1, - asi(0) => asi_0(0), data(31) => \data_1[31]\, data(30) - => \data_1[30]\, data(29) => \data_1[29]\, data(28) => - \data_1[28]\, data(27) => \data_1[27]\, data(26) => - \data_1[26]\, data(25) => \data_1[25]\, data(24) => - \data_1[24]\, data(23) => \data[23]\, data(22) => - \data[22]\, data(21) => \data_1[21]\, data(20) => - \data_1[20]\, data(19) => \data[19]\, data(18) => - \data[18]\, data(17) => \data_1[17]\, data(16) => - \data_1[16]\, data(15) => \data_1[15]\, data(14) => - \data_1[14]\, data(13) => \data_1[13]\, data(12) => - \data_1[12]\, data(11) => \data[11]\, data(10) => data_10, - data(9) => \data[9]\, data(8) => data_8, data(7) => - \data[7]\, data(6) => \data[6]\, data(5) => data_5, - data(4) => \data[4]\, data(3) => \data[3]\, data(2) => - \data[2]\, data(1) => \data[1]\, data(0) => \data[0]\, - LVL_RNIT69H911(0) => \LVL_RNIT69H911[0]\, - data_1_3_i_a3_6_2 => \data_1_3_i_a3_6[27]\, - data_1_3_i_a3_6_4 => \data_1_3_i_a3_6[29]\, - data_1_3_i_a3_6_0 => \data_1_3_i_a3_6[25]\, - data_1_3_i_a3_6_1 => \data_1_3_i_a3_6[26]\, - data_RNIKU1T4(16) => \data_RNIKU1T4[16]\, un1_m0_2_73 => - \un1_m0_2[74]\, un1_m0_2_2 => \un1_m0_2[3]\, un1_m0_2_4 - => \un1_m0_2[5]\, un1_m0_2_10 => \un1_m0_2[11]\, - un1_m0_2_9 => \un1_m0_2[10]\, un1_m0_2_40 => - \un1_m0_2[41]\, un1_m0_2_5 => \un1_m0_2[6]\, un1_m0_2_1 - => \un1_m0_2[2]\, un1_m0_2_7 => \un1_m0_2[8]\, - un1_m0_2_68 => \un1_m0_2[69]\, un1_m0_2_38 => - \un1_m0_2[39]\, un1_m0_2_42 => \un1_m0_2[43]\, - un1_m0_2_59 => \un1_m0_2[60]\, un1_m0_2_58 => - \un1_m0_2[59]\, un1_m0_2_67 => \un1_m0_2[68]\, - un1_m0_2_43 => \un1_m0_2[44]\, un1_m0_2_65 => - \un1_m0_2[66]\, un1_m0_2_77 => \un1_m0_2[78]\, - un1_m0_2_34 => \un1_m0_2[35]\, un1_m0_2_78 => - \un1_m0_2[79]\, un1_m0_2_75 => \un1_m0_2[76]\, un1_m0_2_6 - => \un1_m0_2[7]\, un1_m0_2_29 => \un1_m0_2[30]\, - un1_m0_2_19 => \un1_m0_2[20]\, un1_m0_2_23 => - \un1_m0_2[24]\, un1_m0_2_60 => \un1_m0_2[61]\, - un1_m0_2_79 => \un1_m0_2[80]\, un1_m0_2_80 => - \un1_m0_2[81]\, un1_m0_2_81 => \un1_m0_2[82]\, - un1_m0_2_84 => \un1_m0_2[85]\, un1_m0_2_83 => - \un1_m0_2[84]\, un1_m0_2_86 => \un1_m0_2[87]\, - un1_m0_2_76 => \un1_m0_2[77]\, un1_m0_2_15 => - \un1_m0_2[16]\, un1_m0_2_11 => \un1_m0_2[12]\, - un1_m0_2_18 => \un1_m0_2[19]\, un1_m0_2_85 => - \un1_m0_2[86]\, un1_m0_2_54 => \un1_m0_2[55]\, - un1_m0_2_71 => \un1_m0_2[72]\, un1_m0_2_55 => - \un1_m0_2[56]\, un1_m0_2_70 => \un1_m0_2[71]\, - un1_m0_2_61 => \un1_m0_2[62]\, un1_m0_2_69 => - \un1_m0_2[70]\, un1_m0_2_37 => \un1_m0_2[38]\, - un1_m0_2_66 => \un1_m0_2[67]\, un1_m0_2_56 => - \un1_m0_2[57]\, un1_m0_2_64 => \un1_m0_2[65]\, - un1_m0_2_62 => \un1_m0_2[63]\, un1_m0_2_57 => - \un1_m0_2[58]\, un1_m0_2_41 => \un1_m0_2[42]\, - un1_m0_2_94 => \un1_m0_2[95]\, un1_m0_2_91 => - \un1_m0_2[92]\, un1_m0_2_106 => \un1_m0_2[107]\, - un1_m0_2_96 => \un1_m0_2[97]\, un1_m0_2_92 => - \un1_m0_2[93]\, un1_m0_2_95 => \un1_m0_2[96]\, - un1_m0_2_97 => \un1_m0_2[98]\, un1_m0_2_93 => - \un1_m0_2[94]\, un1_m0_2_98 => \un1_m0_2[99]\, - un1_m0_2_33 => \un1_m0_2[34]\, un1_m0_2_72 => - \un1_m0_2[73]\, un1_m0_2_39 => \un1_m0_2[40]\, - un1_m0_2_63 => \un1_m0_2[64]\, un1_m0_2_44 => - \un1_m0_2[45]\, un1_m0_2_35 => \un1_m0_2[36]\, - un1_m0_2_36 => \un1_m0_2[37]\, un1_m0_2_0_d0 => - \un1_m0_2[1]\, un1_m0_2_3 => \un1_m0_2[4]\, un1_m0_2_12 - => \un1_m0_2[13]\, un1_m0_2_82 => \un1_m0_2[83]\, - un1_m0_2_8 => \un1_m0_2[9]\, un1_m0_2_31 => - \un1_m0_2[32]\, un1_m0_2_108 => \un1_m0_2[109]\, - eaddress_7 => eaddress_7, eaddress_3 => eaddress_3, - eaddress_0 => eaddress_0, eaddress_8 => eaddress_8, - eaddress_1 => eaddress_1, eaddress_4 => eaddress_4, - eaddress_12 => eaddress_12, eaddress_16 => eaddress_16, - eaddress_24 => eaddress_24, eaddress_2 => eaddress_2, - eaddress_20 => eaddress_20, eaddress_5 => eaddress_5, - eaddress_15 => eaddress_15, eaddress_27 => eaddress_27, - eaddress_17 => eaddress_17, eaddress_9 => eaddress_9, - eaddress_19 => eaddress_19, eaddress_23 => eaddress_23, - eaddress_25 => eaddress_25, eaddress_10 => eaddress_10, - eaddress_6 => eaddress_6, eaddress_18 => eaddress_18, - eaddress_28 => eaddress_28, eaddress_13 => eaddress_13, - eaddress_21 => eaddress_21, eaddress_22 => eaddress_22, - eaddress_29 => eaddress_29, rdatav_0_1_0_iv_5_18 => - rdatav_0_1_0_iv_5_4, rdatav_0_1_0_iv_5_14 => - rdatav_0_1_0_iv_5_0, rdatav_0_1_0_iv_5_15 => - rdatav_0_1_0_iv_5_1, rdatav_0_1_0_iv_5_20 => - rdatav_0_1_0_iv_5_6, rdatav_0_1_0_iv_4_23 => - rdatav_0_1_0_iv_4_14, rdatav_0_1_0_iv_4_9 => - rdatav_0_1_0_iv_4_0, rdatav_0_1_0_iv_4_29 => - rdatav_0_1_0_iv_4_20, rdatav_0_1_0_iv_4_31 => - rdatav_0_1_0_iv_4_22, mcdo_m_0_8 => mcdo_m_0_7, - mcdo_m_0_5 => mcdo_m_0_4, mcdo_m_0_18 => mcdo_m_0_17, - mcdo_m_0_21 => mcdo_m_0_20, mcdo_m_0_22 => mcdo_m_0_21, - mcdo_m_0_17 => mcdo_m_0_16, mcdo_m_0_1 => mcdo_m_0_0, - mcdo_m_0_28 => mcdo_m_0_27, mcdo_m_0_23 => mcdo_m_0_22, - mcdo_m_0_30 => mcdo_m_0_29, data_0_23 => \data_1[23]\, - data_0_22 => \data_1[22]\, data_0_19 => \data_1[19]\, - data_0_18 => \data_1[18]\, data_0_7 => data_0_0_7, - data_0_15 => data_0_0_15, data_0_12 => data_0_0_12, - data_0_0 => data_0_0_0, data_0_26 => data_0_0_26, - data_0_4 => data_0_0_4, data_0_21 => data_0_0_21, - data_0_11 => data_0_0_11, data_0_8 => data_0_0_8, - data_0_28 => data_0_0_28, data_0_17 => data_0_0_17, - data_0_16 => data_0_0_16, data_0_25 => data_0_0_25, - data_0_14 => data_0_0_14, data_0_20 => data_0_0_20, - data_0_27 => data_0_0_27, data_0_30 => data_0_0_30, - data_0_13 => data_0_0_13, data_0_29 => data_0_0_29, - data_0_24 => data_0_0_24, data_0_31 => data_0_0_31, - dataout(35) => dataout(35), dataout(34) => dataout(34), - dataout(33) => dataout(33), dataout(32) => dataout(32), - dataout(31) => dataout(31), dataout(30) => dataout(30), - dataout(29) => dataout(29), dataout(28) => dataout(28), - dataout(27) => dataout(27), dataout(26) => dataout(26), - dataout(25) => dataout(25), dataout(24) => dataout(24), - dataout(23) => dataout(23), dataout(22) => dataout(22), - dataout(21) => dataout(21), dataout(20) => dataout(20), - dataout(19) => dataout(19), dataout(18) => dataout(18), - dataout(17) => dataout(17), dataout(16) => dataout(16), - dataout(15) => dataout(15), dataout(14) => dataout(14), - dataout(13) => dataout(13), dataout(12) => dataout(12), - dataout(11) => dataout(11), dataout(10) => dataout(10), - dataout(9) => dataout(9), dataout(8) => dataout(8), - dataout(7) => dataout(7), dataout(6) => dataout(6), - dataout(5) => dataout(5), dataout(4) => dataout(4), - dataout(3) => dataout(3), dataout(2) => dataout(2), - dataout(1) => dataout(1), dataout(0) => dataout(0), - ctxp_13 => \ctxp[13]\, ctxp_16 => \ctxp[16]\, ctxp_7 => - \ctxp[7]\, ctxp_10 => \ctxp[10]\, ctxp_3 => \ctxp[3]\, - ctxp_8 => \ctxp[8]\, ctxp_19 => \ctxp[19]\, ctxp_17 => - \ctxp[17]\, ctxp_15 => \ctxp[15]\, ctxp_14 => \ctxp[14]\, - ctxp_20 => \ctxp[20]\, ctxp_18 => \ctxp[18]\, ctxp_6 => - \ctxp[6]\, ctxp_21 => \ctxp[21]\, ctxp_11 => \ctxp[11]\, - ctxp_4 => \ctxp[4]\, ctxp_25 => \ctxp[25]\, ctxp_0 => - \ctxp[0]\, ctxp_22 => \ctxp[22]\, ctxp_23 => \ctxp[23]\, - ctxp_24 => \ctxp[24]\, ctxp_5 => \ctxp[5]\, ctxp_12 => - \ctxp[12]\, ctxp_9 => \ctxp[9]\, ctxp_1 => \ctxp[1]\, - ctxp_2 => \ctxp[2]\, diagdata_6 => \diagdata[6]\, - diagdata_7 => \diagdata[7]\, diagdata_1 => \diagdata[1]\, - diagdata_3 => \diagdata[3]\, diagdata_5 => \diagdata[5]\, - diagdata_29 => \diagdata[29]\, diagdata_22 => - \diagdata[22]\, diagdata_27 => \diagdata[27]\, - diagdata_20 => \diagdata[20]\, diagdata_8 => - \diagdata[8]\, diagdata_25 => \diagdata[25]\, diagdata_18 - => \diagdata[18]\, diagdata_31 => \diagdata[31]\, - diagdata_17 => \diagdata[17]\, diagdata_24 => - \diagdata[24]\, diagdata_23 => \diagdata[23]\, - diagdata_21 => \diagdata[21]\, diagdata_16 => - \diagdata[16]\, diagdata_12 => \diagdata[12]\, diagdata_9 - => \diagdata[9]\, diagdata_26 => \diagdata[26]\, - diagdata_0 => \diagdata[0]\, diagdata_19 => - \diagdata[19]\, diagdata_14 => \diagdata[14]\, - diagdata_15 => \diagdata[15]\, diagdata_2 => - \diagdata[2]\, diagdata_13 => \diagdata[13]\, diagdata_30 - => \diagdata[30]\, diagdata_4 => \diagdata[4]\, - diagdata_28 => \diagdata[28]\, address(31) => - \address_0[31]\, address(30) => \address_0[30]\, - address(29) => \address_0[29]\, address(28) => - \address_0[28]\, address(27) => \address_0[27]\, - address(26) => \address_0[26]\, address(25) => - \address_0[25]\, address(24) => \address_0[24]\, - address(23) => \address_0[23]\, address(22) => - \address_0[22]\, address(21) => \address_0[21]\, - address(20) => \address_0[20]\, address(19) => - \address_0[19]\, address(18) => \address_0[18]\, - address(17) => \address_0[17]\, address(16) => - \address_0[16]\, address(15) => \address_0[15]\, - address(14) => \address_0[14]\, address(13) => - \address_0[13]\, address(12) => \address_0[12]\, - address(11) => \address_0[11]\, address(10) => - \address_0[10]\, address(9) => \address_0[9]\, address(8) - => \address_0[8]\, address(7) => \address_0[7]\, - address(6) => \address_0[6]\, address(5) => - \address_0[5]\, address(4) => \address_0[4]\, address(3) - => \address_0[3]\, address(2) => \address_0[2]\, - address(1) => address_1, address(0) => address_0, addr_30 - => addr_28, addr_11 => \addr[11]\, addr_6 => \addr[6]\, - addr_4 => \addr[4]\, addr_7 => \addr[7]\, addr_5 => - \addr[5]\, addr_3 => \addr[3]\, addr_8 => \addr[8]\, - addr_10 => \addr[10]\, addr_9 => \addr[9]\, addr_2 => - \addr[2]\, dataout_0(31) => dataout_0(31), dataout_0(30) - => dataout_0(30), dataout_0(29) => dataout_0(29), - dataout_0(28) => dataout_0(28), dataout_0(27) => - dataout_0(27), dataout_0(26) => dataout_0(26), - dataout_0(25) => dataout_0(25), dataout_0(24) => - dataout_0(24), dataout_0(23) => dataout_0(23), - dataout_0(22) => dataout_0(22), dataout_0(21) => - dataout_0(21), dataout_0(20) => dataout_0(20), - dataout_0(19) => dataout_0(19), dataout_0(18) => - dataout_0(18), dataout_0(17) => dataout_0(17), - dataout_0(16) => dataout_0(16), dataout_0(15) => - dataout_0(15), dataout_0(14) => dataout_0(14), - dataout_0(13) => dataout_0(13), dataout_0(12) => - dataout_0(12), dataout_0(11) => dataout_0(11), - dataout_0(10) => dataout_0(10), dataout_0(9) => - dataout_0(9), dataout_0(8) => dataout_0(8), dataout_0(7) - => dataout_0(7), dataout_0(6) => dataout_0(6), - dataout_0(5) => dataout_0(5), dataout_0(4) => - dataout_0(4), dataout_0(3) => dataout_0(3), dataout_0(2) - => dataout_0(2), dataout_0(1) => dataout_0(1), - dataout_0(0) => dataout_0(0), maddress(31) => - maddress(31), maddress(30) => maddress(30), maddress(29) - => maddress(29), maddress(28) => maddress(28), - maddress(27) => maddress(27), maddress(26) => - maddress(26), maddress(25) => maddress(25), maddress(24) - => maddress(24), maddress(23) => maddress(23), - maddress(22) => maddress(22), maddress(21) => - maddress(21), maddress(20) => maddress(20), maddress(19) - => maddress(19), maddress(18) => maddress(18), - maddress(17) => maddress(17), maddress(16) => - maddress(16), maddress(15) => maddress(15), maddress(14) - => maddress(14), maddress(13) => maddress(13), - maddress(12) => maddress(12), maddress(11) => - maddress(11), maddress(10) => maddress(10), maddress(9) - => maddress(9), maddress(8) => maddress(8), maddress(7) - => maddress(7), maddress(6) => maddress(6), maddress(5) - => maddress(5), maddress(4) => maddress(4), maddress(3) - => maddress(3), maddress(2) => maddress(2), maddress(1) - => maddress(1), maddress(0) => maddress(0), - un1_p0_2_0(498) => un1_p0_2_0_350, ctx_0(7) => \ctx_0[7]\, - ctx_0(6) => \ctx_0[6]\, ctx_0(5) => \ctx_0[5]\, ctx_0(4) - => \ctx_0[4]\, ctx_0(3) => \ctx_0[3]\, ctx_0(2) => - \ctx_0[2]\, ctx_0(1) => \ctx_0[1]\, ctx_0(0) => - \ctx_0[0]\, size_1z => size, enable => enable, N_10 => - N_10, write => write, eenaddr => eenaddr, msu => msu, su - => su_1, read_3 => read, flush_RNIJEN4SI3 => - flush_RNIJEN4SI3, N_415 => N_415, N_351 => N_351, - flush_RNIGBB873 => flush_RNIGBB873, N_192 => N_192, - N_190_0 => N_190, diagrdy => diagrdy, burst_0 => burst_0, - N_264_0 => N_264_0, N_425 => N_425, trans_op_0 => - trans_op_0, flush_op_i_0 => flush_op_i_0, trans_op => - trans_op_1, un2_m_tlb_type => un2_m_tlb_type, tlbdis => - tlbdis, read_2 => read_0, grant => grant_0, N_317_0 => - N_317, N_2886 => N_2886, N_2887 => N_2887, N_270 => N_270, - N_269 => N_269, N_267 => N_267, N_353 => N_353, N_259 => - N_259, N_258 => N_258, N_236_0 => N_236, N_417 => N_417, - N_144 => N_144, N_3846 => N_3846, e => e, N_421_0 => - N_421, N_3305 => N_3305, nf => nf, N_262_0 => N_262_0, - un54_fault_pro_m => un54_fault_pro_m, M_m => M_m, r_N_6 - => r_N_6, vaddr_1_sqmuxa_0_a2_2 => vaddr_1_sqmuxa_0_a2_2, - fault_pro => fault_pro, stpend_RNI6P41NG3 => - stpend_RNI6P41NG3, read_1 => read_1, read_RNIQH64D1 => - read_RNIQH64D1, read_RNIQPCQ11 => read_RNIQPCQ11, - read_RNIRO4K31 => read_RNIRO4K31, N_3389_i_0 => - N_3389_i_0, read_RNI0IQ7R => read_RNI0IQ7R, - read_RNIQFOD21 => read_RNIQFOD21, read_RNI8DFM31 => - read_RNI8DFM31, read_RNIAQJ831 => read_RNIAQJ831, - read_RNI76N8R => read_RNI76N8R, read_RNI7G7G41 => - read_RNI7G7G41, read_RNIMJHQT => read_RNIMJHQT, - read_RNIL633F1 => read_RNIL633F1, read_RNICKHE91 => - read_RNICKHE91, flush_0_1_RNIOMB27S2 => - flush_0_1_RNIOMB27S2, un59_nbo => \un59_nbo\, lock_m => - lock_m, N_2699_i_0 => N_2699_i_0, mexc_1 => mexc_1, - N_3239_i_0 => N_3239_i_0, N_2701 => N_2701, N_2703_i_0 - => N_2703_i_0, N_2714 => N_2714, N_3227_i_0 => - N_3227_i_0, N_3387_i_0 => N_3387_i_0, N_26 => N_26_0, - read_RNIEKS231 => read_RNIEKS231, read_RNIFPFT31 => - read_RNIFPFT31, read_RNIC9O9B1 => read_RNIC9O9B1, - flush_RNIGUM2OH3 => flush_RNIGUM2OH3, read_RNICAQK41 => - read_RNICAQK41, read_RNIQMJI41 => read_RNIQMJI41, - read_RNISLPNU => read_RNISLPNU, read_RNIC70OF1 => - read_RNIC70OF1, read_RNI75LJ31 => read_RNI75LJ31, - read_RNIEEGDD1 => read_RNIEEGDD1, N_12_i_0 => N_12_i_0, - N_16_i_0 => N_16_i_0, N_696 => N_696, N_695 => N_695, - flush_0_1_RNIBUA27S2 => flush_0_1_RNIBUA27S2, - flush_0_1_RNIPTA27S2 => flush_0_1_RNIPTA27S2, N_2702_i_0 - => N_2702_i_0, N_2717 => N_2717, N_2720 => N_2720, N_694 - => N_694, N_2711_i_0 => N_2711_i_0, fsread_i_0 => - fsread_i_0, N_24 => N_24, N_329 => N_329, N_330 => N_330, - N_78_0 => N_78_0, ba => ba, hcache => hcache, cache => - cache, cdwrite_0_sqmuxa_i_0_0 => cdwrite_0_sqmuxa_i_0_0, - lock_0 => lock, un17_casaen_0_0 => un17_casaen_0_0, mexc - => mexc_2, me_nullify2_1_2 => me_nullify2_1_2, - nullify2_0_sqmuxa => nullify2_0_sqmuxa, flush => flush, - hold_0 => hold, fault_pro67 => fault_pro67, req => req_0, - intack => intack, N_523 => N_523, fault_pri => fault_pri, - iflush_1_0_a2_0 => iflush_1_0_a2_0, N_419 => N_419, - N_2709_i_0 => N_2709_i_0, nullify => nullify, flush_i_0 - => flush_i_0, N_293 => N_293, read_0 => read_0_0, rst - => rst, burst => burst_1, accexc_6 => accexc_6, - un1_addout_12 => un1_addout_12, - vaddr_1_sqmuxa_0_a2_4_m1_e_24 => - vaddr_1_sqmuxa_0_a2_4_m1_e_24, G_80_0 => G_80_0, lock => - lock_0, ready => ready_0, mmudci_trans_op_1_sqmuxa_1 => - mmudci_trans_op_1_sqmuxa_1, hold => hold_0, enaddr => - enaddr, N_425_0 => N_425_0_0, N_121 => N_121, N_3254_0 - => N_3254_0, e_0 => e_0, lclk_c => lclk_c); - - a0 : mmu_acache - port map(iosn_2(93) => iosn_2(93), hresp(0) => hresp(0), - hgrant(0) => hgrant(0), hsize_5(1) => hsize_5(1), size(1) - => \size[1]\, iosn_1(93) => iosn_1(93), data_0_18 => - \data_1[18]\, data_0_1 => \data[1]\, data_0_3 => - \data[3]\, data_0_17 => \data[17]\, data_0_22 => - \data_1[22]\, data_0_21 => \data[21]\, data_0_9 => - \data[9]\, data_0_23 => \data_1[23]\, data_0_20 => - \data[20]\, data_0_4 => \data[4]\, data_0_31 => - \data[31]\, data_0_26 => \data[26]\, data_0_15 => - \data[15]\, data_0_7 => \data[7]\, data_0_27 => - \data[27]\, data_0_25 => \data[25]\, data_0_16 => - \data[16]\, data_0_30 => \data[30]\, data_0_28 => - \data[28]\, data_0_14 => \data[14]\, data_0_2 => - \data[2]\, data_0_11 => \data[11]\, data_0_0 => \data[0]\, - data_0_12 => \data[12]\, data_0_6 => \data[6]\, data_0_19 - => \data_1[19]\, data_18 => \data_2[18]\, data_1 => - \data_1[1]\, data_3 => \data_1[3]\, data_17 => - \data_2[17]\, data_22 => \data_2[22]\, data_21 => - \data_2[21]\, data_9 => \data_1[9]\, data_23 => - \data_2[23]\, data_20 => \data_2[20]\, data_4 => - \data_1[4]\, data_31 => \data_2[31]\, data_26 => - \data_2[26]\, data_15 => \data_2[15]\, data_7 => - \data_1[7]\, data_27 => \data_2[27]\, data_25 => - \data_2[25]\, data_16 => \data_2[16]\, data_30 => - \data_2[30]\, data_28 => \data_2[28]\, data_14 => - \data_2[14]\, data_2 => \data_1[2]\, data_11 => - \data_1[11]\, data_0_d0 => \data_1[0]\, data_12 => - \data_2[12]\, data_6 => \data_1[6]\, data_19 => - \data_2[19]\, hwdata_15 => hwdata_15, hwdata_0 => - hwdata_0, hwdata_14 => hwdata_14, hwdata_1 => hwdata_1, - hwdata_28 => hwdata_28, hwdata_23 => hwdata_23, hwdata_12 - => hwdata_12, hwdata_4 => hwdata_4, hwdata_13 => - hwdata_13, hwdata_27 => hwdata_27, hwdata_25 => hwdata_25, - hwdata_11 => hwdata_11, hwdata_9 => hwdata_9, hwdata_3 - => hwdata_3, hwdata_16 => hwdata_16, address_1(31) => - \address_1[31]\, address_1(30) => \address_1[30]\, - address_1(29) => \address_1[29]\, address_1(28) => - \address[28]\, address_1(27) => \address_1[27]\, - address_1(26) => \address_1[26]\, address_1(25) => - \address_1[25]\, address_1(24) => \address_1[24]\, - address_1(23) => \address_1[23]\, address_1(22) => - \address_1[22]\, address_1(21) => \address_1[21]\, - address_1(20) => \address_1[20]\, address_1(19) => - \address_1[19]\, address_1(18) => \address_1[18]\, - address_1(17) => \address_1[17]\, address_1(16) => - \address_1[16]\, address_1(15) => \address_1[15]\, - address_1(14) => \address_1[14]\, address_1(13) => - \address_0[13]\, address_1(12) => \address_1[12]\, - address_1(11) => \address_1[11]\, address_1(10) => - \address_1[10]\, address_1(9) => \address_1[9]\, - address_1(8) => \address_1[8]\, address_1(7) => - \address_1[7]\, address_1(6) => \address_1[6]\, - address_1(5) => \address_0[5]\, address_1(4) => - \address_0[4]\, address_1(3) => \address_1[3]\, - address_1(2) => \address_1[2]\, haddr(31) => haddr(31), - haddr(30) => haddr(30), haddr(29) => haddr(29), haddr(28) - => haddr(28), haddr(27) => haddr(27), haddr(26) => - haddr(26), haddr(25) => haddr(25), haddr(24) => haddr(24), - haddr(23) => haddr(23), haddr(22) => haddr(22), haddr(21) - => haddr(21), haddr(20) => haddr(20), haddr(19) => - haddr(19), haddr(18) => haddr(18), haddr(17) => haddr(17), - haddr(16) => haddr(16), haddr(15) => haddr(15), haddr(14) - => haddr(14), haddr(13) => haddr(13), haddr(12) => - haddr(12), haddr(11) => haddr(11), haddr(10) => haddr(10), - haddr(9) => haddr(9), haddr(8) => haddr(8), haddr(7) => - haddr(7), haddr(6) => haddr(6), haddr(5) => haddr(5), - haddr(4) => haddr(4), haddr(3) => haddr(3), haddr(2) => - haddr(2), address_0(31) => \address[31]\, address_0(30) - => \address[30]\, address_0(29) => \address[29]\, - address_0(28) => \address_1[28]\, address_0(27) => - \address[27]\, address_0(26) => \address[26]\, - address_0(25) => \address[25]\, address_0(24) => - \address[24]\, address_0(23) => \address[23]\, - address_0(22) => \address[22]\, address_0(21) => - \address[21]\, address_0(20) => \address[20]\, - address_0(19) => \address_0[19]\, address_0(18) => - \address_0[18]\, address_0(17) => \address_0[17]\, - address_0(16) => \address_0[16]\, address_0(15) => - \address_0[15]\, address_0(14) => \address_0[14]\, - address_0(13) => \address[13]\, address_0(12) => - \address_0[12]\, address_0(11) => \address_0[11]\, - address_0(10) => \address_0[10]\, address_0(9) => - \address_0[9]\, address_0(8) => \address_0[8]\, - address_0(7) => \address_0[7]\, address_0(6) => - \address_0[6]\, address_0(5) => \address[5]\, - address_0(4) => \address_1[4]\, address_0(3) => - \address_0[3]\, address_0(2) => \address_0[2]\, - htrans_tz(1) => htrans_tz(1), bo_d(3) => \bo_d[3]\, - bo_d(2) => \bo_d[2]\, iosn_0(93) => iosn_0(93), - address(31) => \address_0[31]\, address(30) => - \address_0[30]\, address(29) => \address_0[29]\, - address(28) => \address_0[28]\, address(27) => - \address_0[27]\, address(26) => \address_0[26]\, - address(25) => \address_0[25]\, address(24) => - \address_0[24]\, address(23) => \address_0[23]\, - address(22) => \address_0[22]\, address(21) => - \address_0[21]\, address(20) => \address_0[20]\, - address(19) => \address[19]\, address(18) => - \address[18]\, address(17) => \address[17]\, address(16) - => \address[16]\, address(15) => \address[15]\, - address(14) => \address[14]\, address(13) => - \address_1[13]\, address(12) => \address[12]\, - address(11) => \address[11]\, address(10) => - \address[10]\, address(9) => \address[9]\, address(8) => - \address[8]\, address(7) => \address[7]\, address(6) => - \address[6]\, address(5) => \address_1[5]\, address(4) - => \address[4]\, address(3) => \address[3]\, address(2) - => \address[2]\, htrans(1) => htrans(1), nbo_5_0(1) => - nbo_5_0(1), nbo_5_0(0) => nbo_5_0(0), size_1z => size, - werr => werr, lclk_c => lclk_c, ready_0 => ready, - htrans_0_sqmuxa_2 => htrans_0_sqmuxa_2, mexc_1 => mexc_0, - ready => ready_0, N_466 => N_466, lock => lock, lock_m - => lock_m, hwrite_1_m_0 => hwrite_1_m_0, N_468 => N_468, - N_463 => N_463, N_461 => N_461, N_459 => N_459, N_458 => - N_458, bo_5842_d => bo_5842_d, N_139 => N_139, N_138 => - N_138, un91_nbo_i_0 => un91_nbo_i_0, grant_1 => grant_0, - hcache_1 => hcache, werr_2_m_0 => werr_2_m_0, N_467 => - N_467, N_462 => N_462, N_457 => N_457, mexc_0 => mexc_2, - read_0 => read_2, mexc => mexc_3, un60_nbo => un60_nbo, - hbusreq => hbusreq, lb_0_sqmuxa_1 => lb_0_sqmuxa_1, - N_5054 => N_5054, burst_0 => burst_1, hlock => hlock, - un59_nbo => \un59_nbo\, ba => ba, cache => cache, read - => read_0, burst => burst, req_1 => req, req_0 => req_1, - req => req_0, N_6093_i => N_6093_i, un1_htrans_1_sqmuxa_0 - => un1_htrans_1_sqmuxa_0, grant_0 => grant, grant => - grant_1, rst => rst, bo_5842_d_0 => \bo_5842_d_0\); - - GND_i_0 : GND - port map(Y => GND_0); - - icache0 : mmu_icache - port map(istate_RNIJCMP6(0) => istate_RNIJCMP6(0), - faddr_RNIUT72LB(3) => faddr_RNIUT72LB(3), - vaddress_RNISNAKMI(21) => vaddress_RNISNAKMI(21), - vaddress_RNI6GAKMI(19) => vaddress_RNI6GAKMI(19), - faddr_RNISJSHQA(2) => faddr_RNISJSHQA(2), - vaddress_RNIQNAKMI(20) => vaddress_RNIQNAKMI(20), - faddr_RNI7UFASD(5) => faddr_RNI7UFASD(5), - faddr_RNI0FOJNE(4) => faddr_RNI0FOJNE(4), - faddr_RNIDN2CUE(6) => faddr_RNIDN2CUE(6), ics(1) => - \ics[1]\, ics(0) => \ics[0]\, faddr_RNIKVTLT9(1) => - faddr_RNIKVTLT9(1), vaddress_RNI0GAKMI(16) => - vaddress_RNI0GAKMI(16), vaddress_RNI0OAKMI(23) => - vaddress_RNI0OAKMI(23), vaddress_RNIOFAKMI(12) => - vaddress_RNIOFAKMI(12), vaddress_RNIJG6QR7(4) => - vaddress_RNIJG6QR7(4), un1_p0_2_i_4 => un1_p0_2_i_4, - un1_p0_2_i_0 => un1_p0_2_i_0, ctx_5 => \ctx[5]\, ctx_4 - => \ctx[4]\, ctx_3 => \ctx[3]\, ctx_1 => \ctx[1]\, - ctx_0_d0 => \ctx[0]\, istate_RNI6HPAI(0) => - istate_RNI6HPAI(0), istate_RNIAJH4F(0) => - istate_RNIAJH4F(0), vaddress_RNIUNAKMI(22) => - vaddress_RNIUNAKMI(22), vaddress_RNISFAKMI(14) => - vaddress_RNISFAKMI(14), istate_RNI57KLB(0) => - istate_RNI57KLB(0), istate_RNIUCOFG(0) => - istate_RNIUCOFG(0), faddr_RNI7H6KT8(0) => - faddr_RNI7H6KT8(0), un1_m0_30 => \un1_m0[34]\, un1_m0_5 - => \un1_m0[9]\, un1_m0_9 => \un1_m0[13]\, un1_m0_8 => - \un1_m0[12]\, un1_m0_1 => \un1_m0[5]\, un1_m0_22 => - \un1_m0[26]\, un1_m0_6 => \un1_m0[10]\, un1_m0_0 => - \un1_m0[4]\, un1_m0_17 => \un1_m0[21]\, un1_m0_16 => - \un1_m0[20]\, un1_m0_7 => \un1_m0[11]\, un1_m0_4 => - \un1_m0[8]\, un1_m0_2 => \un1_m0[6]\, un1_m0_3 => - \un1_m0[7]\, istate_RNIH0NBI(0) => istate_RNIH0NBI(0), - istate_RNIG7IIA(0) => istate_RNIG7IIA(0), - vaddress_RNIFCB8U6(3) => vaddress_RNIFCB8U6(3), - istate_RNI2MM6D(0) => istate_RNI2MM6D(0), - istate_RNI8BL1A(0) => istate_RNI8BL1A(0), - istate_RNILTAC8(0) => istate_RNILTAC8(0), - istate_RNIK9NF8(0) => istate_RNIK9NF8(0), - vaddress_RNI4GAKMI(18) => vaddress_RNI4GAKMI(18), - vaddress_RNI2GAKMI(17) => vaddress_RNI2GAKMI(17), - istate_RNI5V68H(0) => istate_RNI5V68H(0), - istate_RNIM2DE7(0) => istate_RNIM2DE7(0), - istate_RNIVTQIJ(0) => istate_RNIVTQIJ(0), - istate_RNIOVC5J(0) => istate_RNIOVC5J(0), - istate_RNI6PSS1(0) => istate_RNI6PSS1(0), - istate_RNIGUTA8(0) => istate_RNIGUTA8(0), - istate_RNIMRTH8(0) => istate_RNIMRTH8(0), - vaddress_RNIQFAKMI(13) => vaddress_RNIQFAKMI(13), - istate_RNIAP6PI(0) => istate_RNIAP6PI(0), - istate_RNIENB3M(0) => istate_RNIENB3M(0), - istate_RNIS4VK8(0) => istate_RNIS4VK8(0), - istate_RNIRASC8(0) => istate_RNIRASC8(0), - istate_RNIJSOBE(0) => istate_RNIJSOBE(0), - istate_RNIR2JU8(0) => istate_RNIR2JU8(0), - istate_RNIOJJE1(0) => istate_RNIOJJE1(0), - istate_RNIN6957(0) => istate_RNIN6957(0), - istate_RNIKJBN8(0) => istate_RNIKJBN8(0), - istate_RNI6LOO6(0) => istate_RNI6LOO6(0), - istate_RNIV33V9(0) => istate_RNIV33V9(0), - istate_RNI7BUID(0) => istate_RNI7BUID(0), - istate_RNIEC82C(0) => istate_RNIEC82C(0), maddress_0_2 - => maddress_0_2, maddress_0_0 => maddress_0_0, - istate_RNIPSU8G(0) => istate_RNIPSU8G(0), diagdata_6 => - \diagdata[6]\, diagdata_15 => \diagdata[15]\, diagdata_4 - => \diagdata[4]\, diagdata_19 => \diagdata[19]\, - diagdata_18 => \diagdata[18]\, diagdata_17 => - \diagdata[17]\, diagdata_16 => \diagdata[16]\, - diagdata_20 => \diagdata[20]\, diagdata_26 => - \diagdata[26]\, diagdata_25 => \diagdata[25]\, - diagdata_22 => \diagdata[22]\, diagdata_14 => - \diagdata[14]\, diagdata_12 => \diagdata[12]\, diagdata_9 - => \diagdata[9]\, diagdata_8 => \diagdata[8]\, - diagdata_5 => \diagdata[5]\, diagdata_3 => \diagdata[3]\, - diagdata_0 => \diagdata[0]\, diagdata_7 => \diagdata[7]\, - diagdata_27 => \diagdata[27]\, diagdata_23 => - \diagdata[23]\, diagdata_24 => \diagdata[24]\, - diagdata_31 => \diagdata[31]\, diagdata_29 => - \diagdata[29]\, diagdata_28 => \diagdata[28]\, - diagdata_21 => \diagdata[21]\, diagdata_13 => - \diagdata[13]\, diagdata_2 => \diagdata[2]\, diagdata_30 - => \diagdata[30]\, diagdata_1 => \diagdata[1]\, - hrdata_26 => hrdata_31, hrdata_25 => hrdata_30, hrdata_24 - => hrdata_29, hrdata_23 => hrdata_28, hrdata_1 => - hrdata_6, hrdata_0_d0 => hrdata_5, vaddress_RNI8EVQ36(2) - => vaddress_RNI8EVQ36(2), rpc_6 => rpc_6, rpc_5 => rpc_5, - rpc_8 => rpc_8, rpc_7 => rpc_7, rpc_2 => rpc_2, rpc_3 => - rpc_3, rpc_1 => rpc_1, rpc_0 => rpc_0, addr(11) => - \addr[11]\, addr(10) => \addr[10]\, addr(9) => \addr[9]\, - addr(8) => \addr[8]\, addr(7) => \addr[7]\, addr(6) => - \addr[6]\, addr(5) => \addr[5]\, addr(4) => \addr[4]\, - addr(3) => \addr[3]\, addr(2) => \addr[2]\, data_0(31) - => data_0(31), data_0(30) => data_0(30), data_0(29) => - data_0(29), data_0(28) => data_0(28), data_0(27) => - data_0(27), data_0(26) => data_0(26), data_0(25) => - data_0(25), data_0(24) => data_0(24), data_0(23) => - data_0(23), data_0(22) => data_0(22), data_0(21) => - data_0(21), data_0(20) => data_0(20), data_0(19) => - data_0(19), data_0(18) => data_0(18), data_0(17) => - data_0(17), data_0(16) => data_0(16), data_0(15) => - data_0(15), data_0(14) => data_0(14), data_0(13) => - data_0(13), data_0(12) => data_0(12), data_0(11) => - data_0(11), data_0(10) => data_0(10), data_0(9) => - data_0(9), data_0(8) => data_0(8), data_0(7) => data_0(7), - data_0(6) => data_0(6), data_0(5) => data_0(5), data_0(4) - => data_0(4), data_0(3) => data_0(3), data_0(2) => - data_0(2), data_0(1) => data_0(1), data_0(0) => data_0(0), - hrdata_0_3 => hrdata_0_3, hrdata_0_24 => hrdata_0_24, - hrdata_0_4 => hrdata_0_4, hrdata_0_18 => hrdata_0_18, - hrdata_0_17 => hrdata_0_17, hrdata_0_16 => hrdata_0_16, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_14 => hrdata_0_14, hrdata_0_13 => hrdata_0_13, - hrdata_0_9 => hrdata_0_9, hrdata_0_8 => hrdata_0_8, - hrdata_0_21 => hrdata_0_21, hrdata_0_27 => hrdata_0_27, - hrdata_0_12 => hrdata_0_12, hrdata_0_11 => hrdata_0_11, - hrdata_0_10 => hrdata_0_10, hrdata_0_7 => hrdata_0_7, - hrdata_0_1 => hrdata_0_1, hrdata_0_2 => hrdata_0_2, - hrdata_0_26 => hrdata_0_26, hrdata_0_0 => hrdata_0_0, - hrdata_0_15 => hrdata_0_15, istate_RNIA8N5H(0) => - istate_RNIA8N5H(0), vaddress_RNIUFAKMI(15) => - vaddress_RNIUFAKMI(15), vitdatain_0_1_0(22) => - vitdatain_0_1_0(22), fault_isid_1_i(0) => - \fault_isid_1_i[0]\, dataout_1(31) => dataout_1(31), - dataout_1(30) => dataout_1(30), dataout_1(29) => - dataout_1(29), dataout_1(28) => dataout_1(28), - dataout_1(27) => dataout_1(27), dataout_1(26) => - dataout_1(26), dataout_1(25) => dataout_1(25), - dataout_1(24) => dataout_1(24), dataout_1(23) => - dataout_1(23), dataout_1(22) => dataout_1(22), - dataout_1(21) => dataout_1(21), dataout_1(20) => - dataout_1(20), dataout_1(19) => dataout_1(19), - dataout_1(18) => dataout_1(18), dataout_1(17) => - dataout_1(17), dataout_1(16) => dataout_1(16), - dataout_1(15) => dataout_1(15), dataout_1(14) => - dataout_1(14), dataout_1(13) => dataout_1(13), - dataout_1(12) => dataout_1(12), dataout_1(11) => - dataout_1(11), dataout_1(10) => dataout_1(10), - dataout_1(9) => dataout_1(9), dataout_1(8) => - dataout_1(8), dataout_1(7) => dataout_1(7), dataout_1(6) - => dataout_1(6), dataout_1(5) => dataout_1(5), - dataout_1(4) => dataout_1(4), dataout_1(3) => - dataout_1(3), dataout_1(2) => dataout_1(2), dataout_1(1) - => dataout_1(1), dataout_1(0) => dataout_1(0), - dataout_0(35) => dataout_0(35), dataout_0(34) => - dataout_0(34), dataout_0(33) => dataout_0(33), - dataout_0(32) => dataout_0(32), ctx_0_5 => \ctx_0[7]\, - ctx_0_0 => \ctx_0[2]\, ctx_0_4 => \ctx_0[6]\, address(31) - => \address[31]\, address(30) => \address[30]\, - address(29) => \address[29]\, address(28) => - \address[28]\, address(27) => \address[27]\, address(26) - => \address[26]\, address(25) => \address[25]\, - address(24) => \address[24]\, address(23) => - \address[23]\, address(22) => \address[22]\, address(21) - => \address[21]\, address(20) => \address[20]\, - address(19) => \address[19]\, address(18) => - \address[18]\, address(17) => \address[17]\, address(16) - => \address[16]\, address(15) => \address[15]\, - address(14) => \address[14]\, address(13) => - \address[13]\, address(12) => \address[12]\, address(11) - => \address[11]\, address(10) => \address[10]\, - address(9) => \address[9]\, address(8) => \address[8]\, - address(7) => \address[7]\, address(6) => \address[6]\, - address(5) => \address[5]\, address(4) => \address[4]\, - address(3) => \address[3]\, address(2) => \address[2]\, - bo_d(3) => \bo_d[3]\, un1_p0_6(0) => un1_p0_6(0), - maddress(31) => maddress(31), maddress(30) => - maddress(30), maddress(29) => maddress(29), maddress(28) - => maddress(28), maddress(27) => maddress(27), - maddress(26) => maddress(26), maddress(25) => - maddress(25), maddress(24) => maddress(24), maddress(23) - => maddress(23), maddress(22) => maddress(22), - maddress(21) => maddress(21), maddress(20) => - maddress(20), maddress(19) => maddress(19), maddress(18) - => maddress(18), maddress(17) => maddress(17), - maddress(16) => maddress(16), maddress(15) => - maddress(15), maddress(14) => maddress(14), maddress(13) - => maddress(13), maddress(12) => maddress(12), - maddress(11) => maddress(11), maddress(10) => - maddress(10), maddress(9) => maddress(9), maddress(8) => - maddress(8), maddress(7) => maddress(7), maddress(6) => - maddress(6), maddress(5) => maddress(5), maddress(4) => - maddress(4), maddress(3) => maddress(3), maddress(2) => - maddress(2), maddress(1) => maddress(1), maddress(0) => - maddress(0), dataout_2(31) => dataout_2(31), - dataout_2(30) => dataout_2(30), dataout_2(29) => - dataout_2(29), dataout_2(28) => dataout_2(28), - dataout_2(27) => dataout_2(27), dataout_2(26) => - dataout_2(26), dataout_2(25) => dataout_2(25), - dataout_2(24) => dataout_2(24), dataout_2(23) => - dataout_2(23), dataout_2(22) => dataout_2(22), - dataout_2(21) => dataout_2(21), dataout_2(20) => - dataout_2(20), dataout_2(19) => dataout_2(19), - dataout_2(18) => dataout_2(18), dataout_2(17) => - dataout_2(17), dataout_2(16) => dataout_2(16), - dataout_2(15) => dataout_2(15), dataout_2(14) => - dataout_2(14), dataout_2(13) => dataout_2(13), - dataout_2(12) => dataout_2(12), dataout_2(11) => - dataout_2(11), dataout_2(10) => dataout_2(10), - dataout_2(9) => dataout_2(9), dataout_2(8) => - dataout_2(8), dataout_2(7) => dataout_2(7), dataout_2(6) - => dataout_2(6), dataout_2(5) => dataout_2(5), - dataout_2(4) => dataout_2(4), dataout_2(3) => - dataout_2(3), dataout_2(2) => dataout_2(2), dataout_2(1) - => dataout_2(1), dataout_2(0) => dataout_2(0), fpc(31) - => fpc(31), fpc(30) => fpc(30), fpc(29) => fpc(29), - fpc(28) => fpc(28), fpc(27) => fpc(27), fpc(26) => - fpc(26), fpc(25) => fpc(25), fpc(24) => fpc(24), fpc(23) - => fpc(23), fpc(22) => fpc(22), fpc(21) => fpc(21), - fpc(20) => fpc(20), fpc(19) => fpc(19), fpc(18) => - fpc(18), fpc(17) => fpc(17), fpc(16) => fpc(16), fpc(15) - => fpc(15), fpc(14) => fpc(14), fpc(13) => fpc(13), - fpc(12) => fpc(12), fpc(11) => fpc(11), fpc(10) => - fpc(10), fpc(9) => fpc(9), fpc(8) => fpc(8), fpc(7) => - fpc(7), fpc(6) => fpc(6), fpc(5) => fpc(5), fpc(4) => - fpc(4), fpc(3) => fpc(3), fpc(2) => fpc(2), asi(0) => - \asi[0]\, un1_p0_2_0(148) => un1_p0_2_0_0, su_0 => su, - diagrdy => diagrdy, hold_0 => hold, mexc_0 => mexc, - fbranch => fbranch, rbranch => rbranch, flush2_RNIFMGM2 - => flush2_RNIFMGM2, N_425_1 => N_425, flush2_RNI5I3N7 - => flush2_RNI5I3N7, N_984 => N_984, N_980 => N_980, N_28 - => N_28, N_987 => N_987, N_986 => N_986, e => e, flush2 - => flush2, N_26 => N_26, flush2_0_0_RNI146O2 => - flush2_0_0_RNI146O2, flush2_0_0_RNI7G6O2 => - flush2_0_0_RNI7G6O2, flush2_0_0_RNIVV5O2 => - flush2_0_0_RNIVV5O2, flush2_0_0_RNITR5O2 => - flush2_0_0_RNITR5O2, flush2_0_0_RNIPJ5O2 => - flush2_0_0_RNIPJ5O2, mds => mds, su => su_0, nf => nf, - N_981 => N_981, N_429 => N_429, N_359 => N_359, N_2626 - => N_2626, N_43 => N_43, N_427 => N_427, N_2625 => - N_2625, N_6093_i => N_6093_i, N_423 => N_423, N_425 => - N_425_0, N_45 => N_45, N_2623 => N_2623, N_365 => N_365, - N_357 => N_357, N_985 => N_985, N_983 => N_983, N_982 => - N_982, N_363 => N_363, N_321 => N_321, N_319 => N_319, - N_361 => N_361, N_2624 => N_2624, N_264_0 => N_264_0, - N_262_0 => N_262_0, N_78_0 => N_78_0, inull => inull, - hold => hold_0, ldlock_3_0 => ldlock_3_0, - un9_icc_check_bp => un9_icc_check_bp, trans_op_0 => - trans_op, flush_op_i_0 => flush_op_i_0, un2_m_tlb_type - => un2_m_tlb_type, stpend_RNI6P41NG3 => - stpend_RNI6P41NG3, vaddr_1_sqmuxa_0_a2_2 => - vaddr_1_sqmuxa_0_a2_2, ldlock_2 => ldlock_2, - xc_exception_1_0 => xc_exception_1_0, grant => grant, - iflush_1_0_a2_0 => iflush_1_0_a2_0, N_121 => N_121, - un1_ici => un1_ici, fault_trans_RNIA0K0D1 => - fault_trans_RNIA0K0D1, N_66_0 => N_66_0, de_hold_pc_1 => - de_hold_pc_1, N_425_0 => N_425_0_0, flush_0 => flush, - flush => flush_0, trans_op => trans_op_0, ba => ba, - hcache => hcache, mexc => mexc_0, req => req, e_0 => e_0, - hold_pc_7 => hold_pc_7, istate_0_sqmuxa => - istate_0_sqmuxa, flush_i_0 => flush_i_0, N_523 => N_523, - ready => ready, burst_0 => burst, burst => burst_0, rst - => rst, un81_m_tlb_type => un81_m_tlb_type, holdn => - holdn, cdwrite_0_sqmuxa_i_0_0 => cdwrite_0_sqmuxa_i_0_0, - N_66 => N_66, enable => enable, lclk_c => lclk_c); - - VCC_i : VCC - port map(Y => \VCC\); - - \mmugen.m0\ : mmu - port map(ctxp(25) => \ctxp[25]\, ctxp(24) => \ctxp[24]\, - ctxp(23) => \ctxp[23]\, ctxp(22) => \ctxp[22]\, ctxp(21) - => \ctxp[21]\, ctxp(20) => \ctxp[20]\, ctxp(19) => - \ctxp[19]\, ctxp(18) => \ctxp[18]\, ctxp(17) => - \ctxp[17]\, ctxp(16) => \ctxp[16]\, ctxp(15) => - \ctxp[15]\, ctxp(14) => \ctxp[14]\, ctxp(13) => - \ctxp[13]\, ctxp(12) => \ctxp[12]\, ctxp(11) => - \ctxp[11]\, ctxp(10) => \ctxp[10]\, ctxp(9) => \ctxp[9]\, - ctxp(8) => \ctxp[8]\, ctxp(7) => \ctxp[7]\, ctxp(6) => - \ctxp[6]\, ctxp(5) => \ctxp[5]\, ctxp(4) => \ctxp[4]\, - ctxp(3) => \ctxp[3]\, ctxp(2) => \ctxp[2]\, ctxp(1) => - \ctxp[1]\, ctxp(0) => \ctxp[0]\, iosn_0(93) => iosn_0(93), - data_0 => \data_1[0]\, data_1_d0 => \data_1[1]\, - data_2_d0 => \data_1[2]\, data_3 => \data_1[3]\, data_4 - => \data_1[4]\, data_6 => \data_1[6]\, data_7 => - \data_1[7]\, data_8 => data_1_8, data_9 => \data_1[9]\, - data_10 => data_1_10, data_11 => \data_1[11]\, data_2(31) - => \data_2[31]\, data_2(30) => \data_2[30]\, data_2(29) - => data_2_17, data_2(28) => \data_2[28]\, data_2(27) => - \data_2[27]\, data_2(26) => \data_2[26]\, data_2(25) => - \data_2[25]\, data_2(24) => data_2_12, data_2(23) => - \data_2[23]\, data_2(22) => \data_2[22]\, data_2(21) => - \data_2[21]\, data_2(20) => \data_2[20]\, data_2(19) => - \data_2[19]\, data_2(18) => \data_2[18]\, data_2(17) => - \data_2[17]\, data_2(16) => \data_2[16]\, data_2(15) => - \data_2[15]\, data_2(14) => \data_2[14]\, data_2(13) => - data_2_1, data_2(12) => \data_2[12]\, data_RNIKU1T4(16) - => \data_RNIKU1T4[16]\, maddress(31) => maddress(31), - maddress(30) => maddress(30), maddress(29) => - maddress(29), maddress(28) => maddress(28), maddress(27) - => maddress(27), maddress(26) => maddress(26), - maddress(25) => maddress(25), maddress(24) => - maddress(24), maddress(23) => maddress(23), maddress(22) - => maddress(22), maddress(21) => maddress(21), - maddress(20) => maddress(20), maddress(19) => - maddress(19), maddress(18) => maddress(18), maddress(17) - => maddress(17), maddress(16) => maddress(16), - maddress(15) => maddress(15), maddress(14) => - maddress(14), maddress(13) => maddress(13), maddress(12) - => maddress(12), data_1(31) => \data_1[31]\, data_1(30) - => \data_1[30]\, data_1(29) => \data_1[29]\, data_1(28) - => \data_1[28]\, data_1(27) => \data_1[27]\, data_1(26) - => \data_1[26]\, data_1(25) => \data_1[25]\, data_1(24) - => \data_1[24]\, data_1(23) => \data[23]\, data_1(22) - => \data[22]\, data_1(21) => \data_1[21]\, data_1(20) - => \data_1[20]\, data_1(19) => \data[19]\, data_1(18) - => \data[18]\, data_1(17) => \data_1[17]\, data_1(16) - => \data_1[16]\, data_1(15) => \data_1[15]\, data_1(14) - => \data_1[14]\, data_1(13) => \data_1[13]\, data_1(12) - => \data_1[12]\, LVL_RNIT69H911(0) => - \LVL_RNIT69H911[0]\, data_1_3_i_a3_6_2 => - \data_1_3_i_a3_6[27]\, data_1_3_i_a3_6_4 => - \data_1_3_i_a3_6[29]\, data_1_3_i_a3_6_1 => - \data_1_3_i_a3_6[26]\, data_1_3_i_a3_6_0 => - \data_1_3_i_a3_6[25]\, hrdata_5 => hrdata_5, hrdata_7 => - hrdata_7, hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, - hrdata_2 => hrdata_2, hrdata_31 => hrdata_31, hrdata_30 - => hrdata_30, hrdata_29 => hrdata_29, hrdata_28 => - hrdata_28, hrdata_27 => hrdata_27, hrdata_26 => hrdata_26, - hrdata_23 => hrdata_23, hrdata_22 => hrdata_22, hrdata_21 - => hrdata_21, hrdata_18 => hrdata_18, hrdata_16 => - hrdata_16, hrdata_15 => hrdata_15, hrdata_12 => hrdata_12, - hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 - => hrdata_0_d0, hrdata_6 => hrdata_6, hrdata_24 => - hrdata_24, hrdata_17 => hrdata_17, hrdata_14 => hrdata_14, - hrdata_13 => hrdata_13, hrdata_11 => hrdata_11, hrdata_10 - => hrdata_10, hrdata_9 => hrdata_9, hrdata_0_0 => - hrdata_0_0, hrdata_0_3 => hrdata_0_3, hrdata_0_4 => - hrdata_0_4, hrdata_0_2 => hrdata_0_2, hrdata_0_22 => - hrdata_0_22, hrdata_0_23 => hrdata_0_23, hrdata_0_27 => - hrdata_0_27, hrdata_0_8 => hrdata_0_8, hrdata_0_9 => - hrdata_0_9, hrdata_0_10 => hrdata_0_10, hrdata_0_11 => - hrdata_0_11, hrdata_0_13 => hrdata_0_13, hrdata_0_15 => - hrdata_0_15, hrdata_0_16 => hrdata_0_16, hrdata_0_14 => - hrdata_0_14, hrdata_0_17 => hrdata_0_17, hrdata_0_1 => - hrdata_0_1, hrdata_0_24 => hrdata_0_24, hrdata_0_12 => - hrdata_0_12, hrdata_0_18 => hrdata_0_18, hrdata_0_21 => - hrdata_0_21, hrdata_0_26 => hrdata_0_26, hrdata_0_7 => - hrdata_0_7, address_0(31) => \address[31]\, address_0(30) - => \address[30]\, address_0(29) => \address[29]\, - address_0(28) => \address[28]\, address_0(27) => - \address[27]\, address_0(26) => \address[26]\, - address_0(25) => \address[25]\, address_0(24) => - \address[24]\, address_0(23) => \address[23]\, - address_0(22) => \address[22]\, address_0(21) => - \address[21]\, address_0(20) => \address[20]\, - address_0(19) => \address[19]\, address_0(18) => - \address[18]\, address_0(17) => \address[17]\, - address_0(16) => \address[16]\, address_0(15) => - \address[15]\, address_0(14) => \address[14]\, - address_0(13) => \address[13]\, address_0(12) => - \address[12]\, address_0(11) => \address[11]\, - address_0(10) => \address[10]\, address_0(9) => - \address[9]\, address_0(8) => \address[8]\, address_0(7) - => \address[7]\, address_0(6) => \address[6]\, - address_0(5) => \address[5]\, address_0(4) => - \address[4]\, address_0(3) => \address[3]\, address_0(2) - => \address[2]\, un1_m0_2_d0 => \un1_m0[6]\, un1_m0_3 - => \un1_m0[7]\, un1_m0_4 => \un1_m0[8]\, un1_m0_7 => - \un1_m0[11]\, un1_m0_16 => \un1_m0[20]\, un1_m0_17 => - \un1_m0[21]\, un1_m0_0 => \un1_m0[4]\, un1_m0_6 => - \un1_m0[10]\, un1_m0_22 => \un1_m0[26]\, un1_m0_1 => - \un1_m0[5]\, un1_m0_5 => \un1_m0[9]\, un1_m0_8 => - \un1_m0[12]\, un1_m0_9 => \un1_m0[13]\, un1_m0_30 => - \un1_m0[34]\, ctx(7) => \ctx[7]\, ctx(6) => \ctx[6]\, - ctx(5) => \ctx[5]\, ctx(4) => \ctx[4]\, ctx(3) => - \ctx[3]\, ctx(2) => \ctx[2]\, ctx(1) => \ctx[1]\, ctx(0) - => \ctx[0]\, ctx_0(7) => \ctx_0[7]\, ctx_0(6) => - \ctx_0[6]\, ctx_0(5) => \ctx_0[5]\, ctx_0(4) => - \ctx_0[4]\, ctx_0(3) => \ctx_0[3]\, ctx_0(2) => - \ctx_0[2]\, ctx_0(1) => \ctx_0[1]\, ctx_0(0) => - \ctx_0[0]\, address(31) => \address_1[31]\, address(30) - => \address_1[30]\, address(29) => \address_1[29]\, - address(28) => \address_1[28]\, address(27) => - \address_1[27]\, address(26) => \address_1[26]\, - address(25) => \address_1[25]\, address(24) => - \address_1[24]\, address(23) => \address_1[23]\, - address(22) => \address_1[22]\, address(21) => - \address_1[21]\, address(20) => \address_1[20]\, - address(19) => \address_1[19]\, address(18) => - \address_1[18]\, address(17) => \address_1[17]\, - address(16) => \address_1[16]\, address(15) => - \address_1[15]\, address(14) => \address_1[14]\, - address(13) => \address_1[13]\, address(12) => - \address_1[12]\, address(11) => \address_1[11]\, - address(10) => \address_1[10]\, address(9) => - \address_1[9]\, address(8) => \address_1[8]\, address(7) - => \address_1[7]\, address(6) => \address_1[6]\, - address(5) => \address_1[5]\, address(4) => - \address_1[4]\, address(3) => \address_1[3]\, address(2) - => \address_1[2]\, hrdata_1_0_1(1) => hrdata_1_0_1(1), - un1_m0_2_23 => \un1_m0_2[24]\, un1_m0_2_15 => - \un1_m0_2[16]\, un1_m0_2_31 => \un1_m0_2[32]\, - un1_m0_2_33 => \un1_m0_2[34]\, un1_m0_2_1 => - \un1_m0_2[2]\, un1_m0_2_2 => \un1_m0_2[3]\, un1_m0_2_3 - => \un1_m0_2[4]\, un1_m0_2_4 => \un1_m0_2[5]\, - un1_m0_2_5 => \un1_m0_2[6]\, un1_m0_2_6 => \un1_m0_2[7]\, - un1_m0_2_8 => \un1_m0_2[9]\, un1_m0_2_11 => - \un1_m0_2[12]\, un1_m0_2_12 => \un1_m0_2[13]\, - un1_m0_2_18 => \un1_m0_2[19]\, un1_m0_2_29 => - \un1_m0_2[30]\, un1_m0_2_19 => \un1_m0_2[20]\, un1_m0_2_9 - => \un1_m0_2[10]\, un1_m0_2_10 => \un1_m0_2[11]\, - un1_m0_2_7 => \un1_m0_2[8]\, un1_m0_2_75 => - \un1_m0_2[76]\, un1_m0_2_76 => \un1_m0_2[77]\, - un1_m0_2_77 => \un1_m0_2[78]\, un1_m0_2_78 => - \un1_m0_2[79]\, un1_m0_2_79 => \un1_m0_2[80]\, - un1_m0_2_80 => \un1_m0_2[81]\, un1_m0_2_81 => - \un1_m0_2[82]\, un1_m0_2_82 => \un1_m0_2[83]\, - un1_m0_2_83 => \un1_m0_2[84]\, un1_m0_2_84 => - \un1_m0_2[85]\, un1_m0_2_85 => \un1_m0_2[86]\, - un1_m0_2_86 => \un1_m0_2[87]\, un1_m0_2_97 => - \un1_m0_2[98]\, un1_m0_2_96 => \un1_m0_2[97]\, - un1_m0_2_95 => \un1_m0_2[96]\, un1_m0_2_93 => - \un1_m0_2[94]\, un1_m0_2_108 => \un1_m0_2[109]\, - un1_m0_2_91 => \un1_m0_2[92]\, un1_m0_2_106 => - \un1_m0_2[107]\, un1_m0_2_92 => \un1_m0_2[93]\, - un1_m0_2_98 => \un1_m0_2[99]\, un1_m0_2_94 => - \un1_m0_2[95]\, un1_m0_2_44 => \un1_m0_2[45]\, - un1_m0_2_43 => \un1_m0_2[44]\, un1_m0_2_73 => - \un1_m0_2[74]\, un1_m0_2_72 => \un1_m0_2[73]\, - un1_m0_2_71 => \un1_m0_2[72]\, un1_m0_2_70 => - \un1_m0_2[71]\, un1_m0_2_69 => \un1_m0_2[70]\, - un1_m0_2_68 => \un1_m0_2[69]\, un1_m0_2_67 => - \un1_m0_2[68]\, un1_m0_2_66 => \un1_m0_2[67]\, - un1_m0_2_65 => \un1_m0_2[66]\, un1_m0_2_64 => - \un1_m0_2[65]\, un1_m0_2_63 => \un1_m0_2[64]\, - un1_m0_2_62 => \un1_m0_2[63]\, un1_m0_2_61 => - \un1_m0_2[62]\, un1_m0_2_60 => \un1_m0_2[61]\, - un1_m0_2_59 => \un1_m0_2[60]\, un1_m0_2_58 => - \un1_m0_2[59]\, un1_m0_2_57 => \un1_m0_2[58]\, - un1_m0_2_56 => \un1_m0_2[57]\, un1_m0_2_55 => - \un1_m0_2[56]\, un1_m0_2_54 => \un1_m0_2[55]\, - un1_m0_2_40 => \un1_m0_2[41]\, un1_m0_2_42 => - \un1_m0_2[43]\, un1_m0_2_35 => \un1_m0_2[36]\, - un1_m0_2_36 => \un1_m0_2[37]\, un1_m0_2_34 => - \un1_m0_2[35]\, un1_m0_2_39 => \un1_m0_2[40]\, - un1_m0_2_38 => \un1_m0_2[39]\, un1_m0_2_37 => - \un1_m0_2[38]\, un1_m0_2_0_d0 => \un1_m0_2[1]\, - un1_m0_2_41 => \un1_m0_2[42]\, fault_isid_1_i(0) => - \fault_isid_1_i[0]\, un1_m0_2_0(35) => \un1_m0_2_0[35]\, - mexc => mexc_3, req => req_1, ba => ba, bo_5842_d_0 => - \bo_5842_d_0\, read_0 => read_2, grant => grant_1, su_0 - => su_1, read => read, N_421 => N_421, N_419 => N_419, - N_417 => N_417, N_415 => N_415, N_353 => N_353, N_351 => - N_351, N_317 => N_317, N_293 => N_293, N_236 => N_236, - N_192 => N_192, N_190 => N_190, N_2887 => N_2887, N_2886 - => N_2886, N_2701 => N_2701, fault_pro67 => fault_pro67, - M_m => M_m, e => e, N_2720 => N_2720, N_2717 => N_2717, - N_2714 => N_2714, G_80_0 => G_80_0, N_2703_i_0 => - N_2703_i_0, N_2699_i_0 => N_2699_i_0, un54_fault_pro_m - => un54_fault_pro_m, accexc_6 => accexc_6, fault_pro => - fault_pro, fault_pri_0 => fault_pri, N_2709_i_0 => - N_2709_i_0, N_2711_i_0 => N_2711_i_0, N_2702_i_0 => - N_2702_i_0, N_696 => N_696, N_695 => N_695, N_694 => - N_694, N_359 => N_359, N_357 => N_357, N_365 => N_365, - N_363 => N_363, N_361 => N_361, N_321 => N_321, N_319 => - N_319, N_45 => N_45, N_2624 => N_2624, N_2623 => N_2623, - N_425 => N_425_0, N_423 => N_423, N_43 => N_43, N_2626 - => N_2626, N_427 => N_427, N_429 => N_429, N_262_0 => - N_262_0, N_78_0 => N_78_0, N_264_0 => N_264_0, tlbdis => - tlbdis, N_2625 => N_2625, su => su_0, N_78 => N_78, N_262 - => N_262, N_264 => N_264, mmu_VCC => mmu_cache_VCC, - fsread_i_0 => fsread_i_0, trans_op_2 => trans_op_1, - flush_op_i_0 => flush_op_i_0, mmudci_trans_op_1_sqmuxa_1 - => mmudci_trans_op_1_sqmuxa_1, N_66 => N_66, trans_op_1 - => trans_op_0, un2_m_tlb_type => un2_m_tlb_type, flush - => flush_0, trans_op => trans_op, istate_0_sqmuxa => - istate_0_sqmuxa, un81_m_tlb_type => un81_m_tlb_type, rst - => rst, N_546 => N_546, N_66_0 => N_66_0, - fault_trans_RNIA0K0D1 => fault_trans_RNIA0K0D1, lclk_c - => lclk_c); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proc3 is - - port( istate_RNIJCMP6 : out std_logic_vector(0 to 0); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - un1_p0_2_i_4 : out std_logic; - un1_p0_2_i_0 : out std_logic; - ctx : out std_logic_vector(7 downto 0); - istate_RNI6HPAI : out std_logic_vector(0 to 0); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - istate_RNI57KLB : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - istate_RNIH0NBI : out std_logic_vector(0 to 0); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - istate_RNI5V68H : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIEC82C : out std_logic_vector(0 to 0); - istate_RNIPSU8G : out std_logic_vector(0 to 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_6 : in std_logic; - hrdata_5 : in std_logic; - hrdata_7 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_24 : in std_logic; - hrdata_17 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - hrdata_0_3 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_15 : in std_logic; - istate_RNIA8N5H : out std_logic_vector(0 to 0); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - vitdatain_0_1_0 : in std_logic_vector(22 to 22); - dataout_1 : in std_logic_vector(31 downto 0); - dataout_0 : in std_logic_vector(35 downto 0); - dataout_2 : in std_logic_vector(31 downto 0); - un1_p0_2_0_0 : out std_logic; - un1_p0_2_0_350 : out std_logic; - data_1_21 : out std_logic; - data_1_16 : out std_logic; - data_1_5 : out std_logic; - data_1_0 : out std_logic; - data_1_2 : out std_logic; - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - size_0 : out std_logic_vector(0 to 0); - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - dci_m_6 : out std_logic; - dci_m_5 : out std_logic; - dci_m_3 : out std_logic; - dci_m_2 : out std_logic; - dci_m_1 : out std_logic; - dci_m_0 : out std_logic; - faddr_RNI7879K : out std_logic_vector(0 to 0); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - newtag_1_0 : out std_logic_vector(27 downto 24); - dataout : in std_logic_vector(35 downto 0); - address : out std_logic_vector(1 downto 0); - addr : out std_logic_vector(30 to 30); - iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - hgrant : in std_logic_vector(0 to 0); - hsize_5 : out std_logic_vector(1 to 1); - iosn_1 : in std_logic_vector(93 to 93); - hwdata_15 : out std_logic; - hwdata_0 : out std_logic; - hwdata_14 : out std_logic; - hwdata_1 : out std_logic; - hwdata_28 : out std_logic; - hwdata_23 : out std_logic; - hwdata_12 : out std_logic; - hwdata_4 : out std_logic; - hwdata_13 : out std_logic; - hwdata_27 : out std_logic; - hwdata_25 : out std_logic; - hwdata_11 : out std_logic; - hwdata_9 : out std_logic; - hwdata_3 : out std_logic; - hwdata_16 : out std_logic; - haddr : out std_logic_vector(31 downto 2); - htrans_tz : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - htrans : out std_logic_vector(1 to 1); - nbo_5_0 : out std_logic_vector(1 downto 0); - data_0 : out std_logic; - data_3 : out std_logic; - data_5 : out std_logic; - data_8 : out std_logic; - data_19 : out std_logic; - data_24 : out std_logic; - hrdata_1_0_1 : in std_logic_vector(1 to 1); - data1 : in std_logic_vector(31 downto 0); - maddress_28 : out std_logic; - data2 : in std_logic_vector(31 downto 0); - irl_0 : out std_logic_vector(3 downto 0); - irl : in std_logic_vector(3 downto 0); - edata2_iv_i_0_7 : out std_logic; - raddr1 : out std_logic_vector(7 downto 0); - rfa1 : out std_logic_vector(7 downto 0); - raddr2 : out std_logic_vector(7 downto 0); - rfa2 : out std_logic_vector(7 downto 0); - waddr : out std_logic_vector(7 downto 0); - wdata : out std_logic_vector(31 downto 0); - flush2_RNIFMGM2 : out std_logic; - flush2_RNI5I3N7 : out std_logic; - N_984 : out std_logic; - N_980 : out std_logic; - N_987 : out std_logic; - N_986 : out std_logic; - flush2 : out std_logic; - flush2_0_0_RNI146O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - N_981 : out std_logic; - N_985 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_264_0 : in std_logic; - N_262_0 : in std_logic; - N_78_0 : in std_logic; - un1_ici : out std_logic; - N_10 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - flush_RNIGBB873 : out std_logic; - N_270 : out std_logic; - N_269 : out std_logic; - N_267 : out std_logic; - N_259 : out std_logic; - N_258 : out std_logic; - N_144 : out std_logic; - N_3846 : out std_logic; - read_RNIQH64D1 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIRO4K31 : out std_logic; - read_RNI0IQ7R : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNICKHE91 : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - un59_nbo : out std_logic; - N_3239_i_0 : out std_logic; - N_26_0 : out std_logic; - read_RNIEKS231 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIC9O9B1 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNICAQK41 : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIEEGDD1 : out std_logic; - N_12_i_0 : out std_logic; - N_16_i_0 : out std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - N_24 : out std_logic; - N_329 : out std_logic; - N_330 : out std_logic; - N_3254_0 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - N_466 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_468 : out std_logic; - N_463 : out std_logic; - N_461 : out std_logic; - N_459 : out std_logic; - N_458 : out std_logic; - bo_5842_d : out std_logic; - N_139 : out std_logic; - N_138 : out std_logic; - un91_nbo_i_0 : out std_logic; - werr_2_m_0 : out std_logic; - N_467 : out std_logic; - N_462 : out std_logic; - N_457 : out std_logic; - un60_nbo : out std_logic; - hbusreq : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - N_5054 : out std_logic; - hlock : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - bo_5842_d_0 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - proc3_VCC : in std_logic; - N_546 : in std_logic; - lclk_c : in std_logic; - ra_bpmiss_1_0 : out std_logic; - rst : in std_logic; - d_m5_0_a3_2 : out std_logic; - rst_RNIINI1H : in std_logic; - rstate_1188n : in std_logic; - ren1 : out std_logic; - rfe1 : out std_logic; - wren : out std_logic; - intack : out std_logic; - ren2 : out std_logic; - rfe2 : out std_logic; - error_i_2 : out std_logic - ); - -end proc3; - -architecture DEF_ARCH of proc3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component iu3 - port( asi_0 : out std_logic_vector(4 downto 0); - wdata : out std_logic_vector(31 downto 0); - size_0_1 : out std_logic; - size_1_0 : out std_logic; - rdatav_0_1_1_iv_7 : in std_logic_vector(6 to 6) := (others => 'U'); - rdatav_0_1_0_iv_7 : in std_logic_vector(2 to 2) := (others => 'U'); - rdatav_0_1_0_iv_0_2 : in std_logic_vector(10 to 10) := (others => 'U'); - rdatav_0_1_0_iv_5_4 : in std_logic := 'U'; - rdatav_0_1_0_iv_5_1 : in std_logic := 'U'; - rdatav_0_1_0_iv_5_0 : in std_logic := 'U'; - rdatav_0_1_0_iv_5_6 : in std_logic := 'U'; - waddr : out std_logic_vector(7 downto 0); - rfa2 : out std_logic_vector(7 downto 0); - raddr2 : out std_logic_vector(7 downto 0); - rfa1 : out std_logic_vector(7 downto 0); - raddr1 : out std_logic_vector(7 downto 0); - data_0_2_13 : in std_logic := 'U'; - data_0_2_14 : in std_logic := 'U'; - data_0_2_17 : in std_logic := 'U'; - data_0_2_16 : in std_logic := 'U'; - data_0_2_8 : in std_logic := 'U'; - data_0_2_24 : in std_logic := 'U'; - data_0_2_31 : in std_logic := 'U'; - data_0_2_30 : in std_logic := 'U'; - data_0_2_29 : in std_logic := 'U'; - data_0_2_28 : in std_logic := 'U'; - data_0_2_27 : in std_logic := 'U'; - data_0_2_26 : in std_logic := 'U'; - data_0_2_25 : in std_logic := 'U'; - data_0_2_21 : in std_logic := 'U'; - data_0_2_4 : in std_logic := 'U'; - data_0_2_0 : in std_logic := 'U'; - edata2_iv_i_0 : out std_logic_vector(31 downto 24); - rpc_6 : out std_logic; - rpc_8 : out std_logic; - rpc_5 : out std_logic; - rpc_7 : out std_logic; - rpc_2 : out std_logic; - rpc_0 : out std_logic; - rpc_1 : out std_logic; - rpc_3 : out std_logic; - irl_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - irl : out std_logic_vector(3 downto 0); - data2 : in std_logic_vector(31 downto 0) := (others => 'U'); - mcdo_m_0_27 : in std_logic := 'U'; - mcdo_m_0_29 : in std_logic := 'U'; - mcdo_m_0_4 : in std_logic := 'U'; - mcdo_m_0_20 : in std_logic := 'U'; - mcdo_m_0_17 : in std_logic := 'U'; - mcdo_m_0_0 : in std_logic := 'U'; - mcdo_m_0_16 : in std_logic := 'U'; - mcdo_m_0_7 : in std_logic := 'U'; - mcdo_m_0_22 : in std_logic := 'U'; - mcdo_m_0_21 : in std_logic := 'U'; - rdatav_0_1_0_iv_4_20 : in std_logic := 'U'; - rdatav_0_1_0_iv_4_22 : in std_logic := 'U'; - rdatav_0_1_0_iv_4_0 : in std_logic := 'U'; - rdatav_0_1_0_iv_4_14 : in std_logic := 'U'; - maddress : out std_logic_vector(31 downto 0); - data1 : in std_logic_vector(31 downto 0) := (others => 'U'); - un1_p0_6_0 : out std_logic; - edata2_0_iv : out std_logic_vector(23 downto 0); - fpc : out std_logic_vector(31 downto 2); - data_0_0_15 : in std_logic := 'U'; - data_0_0_20 : in std_logic := 'U'; - data_0_0_11 : in std_logic := 'U'; - data_0_0_6 : in std_logic := 'U'; - data_0_0_23 : in std_logic := 'U'; - data_0_0_19 : in std_logic := 'U'; - data_0_0_17 : in std_logic := 'U'; - data_0_0_16 : in std_logic := 'U'; - data_0_0_14 : in std_logic := 'U'; - data_0_0_13 : in std_logic := 'U'; - data_0_0_12 : in std_logic := 'U'; - data_0_0_10 : in std_logic := 'U'; - data_0_0_9 : in std_logic := 'U'; - data_0_0_7 : in std_logic := 'U'; - data_0_0_5 : in std_logic := 'U'; - data_0_0_3 : in std_logic := 'U'; - data_0_0_2 : in std_logic := 'U'; - data_0_0_1 : in std_logic := 'U'; - data_0_0_0 : in std_logic := 'U'; - data_0_0_4 : in std_logic := 'U'; - data_0_0_26 : in std_logic := 'U'; - data_0_0_8 : in std_logic := 'U'; - data_0_0_28 : in std_logic := 'U'; - data_0_0_27 : in std_logic := 'U'; - data_0_0_30 : in std_logic := 'U'; - data_0_0_25 : in std_logic := 'U'; - data_0_0_24 : in std_logic := 'U'; - data_0_0_21 : in std_logic := 'U'; - eaddress_4 : out std_logic; - eaddress_2 : out std_logic; - eaddress_12 : out std_logic; - eaddress_24 : out std_logic; - eaddress_5 : out std_logic; - eaddress_11 : out std_logic; - eaddress_30 : out std_logic; - eaddress_6 : out std_logic; - eaddress_3 : out std_logic; - eaddress_27 : out std_logic; - eaddress_31 : out std_logic; - eaddress_15 : out std_logic; - eaddress_17 : out std_logic; - eaddress_20 : out std_logic; - eaddress_18 : out std_logic; - eaddress_26 : out std_logic; - eaddress_14 : out std_logic; - eaddress_21 : out std_logic; - eaddress_25 : out std_logic; - eaddress_29 : out std_logic; - eaddress_19 : out std_logic; - eaddress_23 : out std_logic; - eaddress_22 : out std_logic; - eaddress_9 : out std_logic; - eaddress_10 : out std_logic; - eaddress_7 : out std_logic; - eaddress_8 : out std_logic; - data_0_22 : in std_logic := 'U'; - data_0_20 : in std_logic := 'U'; - data_0_18 : in std_logic := 'U'; - data_0_15 : in std_logic := 'U'; - data_0_11 : in std_logic := 'U'; - data_0_7 : in std_logic := 'U'; - data_0_12 : in std_logic := 'U'; - data_0_31 : in std_logic := 'U'; - data_0_29 : in std_logic := 'U'; - dco_i_2 : in std_logic_vector(132 to 132) := (others => 'U'); - maddress_0_2 : out std_logic; - maddress_0_0 : out std_logic; - msu : out std_logic; - error_i_2 : out std_logic; - read_1 : out std_logic; - write_0 : out std_logic; - mexc_2 : in std_logic := 'U'; - enaddr : out std_logic; - eenaddr : out std_logic; - N_26 : out std_logic; - lock : out std_logic; - N_28 : out std_logic; - su_0 : out std_logic; - rfe2 : out std_logic; - ren2 : out std_logic; - mexc : in std_logic := 'U'; - N_3305_0 : in std_logic := 'U'; - intack_2 : out std_logic; - wren : out std_logic; - rfe1 : out std_logic; - ren1 : out std_logic; - werr_2 : in std_logic := 'U'; - rstate_1188n : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : in std_logic := 'U'; - ldlock_3_0 : out std_logic; - rst_RNIINI1H : in std_logic := 'U'; - rbranch : out std_logic; - r_N_6 : out std_logic; - un1_addout_12 : out std_logic; - flush_i_0 : out std_logic; - N_3389_i_0 : in std_logic := 'U'; - N_3227_i_0 : in std_logic := 'U'; - N_3387_i_0 : in std_logic := 'U'; - nullify : out std_logic; - ldlock_2 : out std_logic; - fbranch : out std_logic; - d_m5_0_a3_2 : out std_logic; - hold_pc_7 : out std_logic; - nullify2_0_sqmuxa : out std_logic; - me_nullify2_1_2 : out std_logic; - un9_icc_check_bp : out std_logic; - inull : out std_logic; - de_hold_pc_1 : out std_logic; - rst : in std_logic := 'U'; - un17_casaen_0_0 : out std_logic; - xc_exception_1_0 : out std_logic; - mds : in std_logic := 'U'; - ra_bpmiss_1_0 : out std_logic; - read_0 : out std_logic; - holdn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component mmu_cache - port( hrdata_1_0_1 : in std_logic_vector(1 to 1) := (others => 'U'); - data_2_17 : out std_logic; - data_2_12 : out std_logic; - data_2_1 : out std_logic; - data_1_10 : out std_logic; - data_1_8 : out std_logic; - nbo_5_0 : out std_logic_vector(1 downto 0); - htrans : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans_tz : out std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 2); - hwdata_16 : out std_logic; - hwdata_3 : out std_logic; - hwdata_9 : out std_logic; - hwdata_11 : out std_logic; - hwdata_25 : out std_logic; - hwdata_27 : out std_logic; - hwdata_13 : out std_logic; - hwdata_4 : out std_logic; - hwdata_12 : out std_logic; - hwdata_23 : out std_logic; - hwdata_28 : out std_logic; - hwdata_1 : out std_logic; - hwdata_14 : out std_logic; - hwdata_0 : out std_logic; - hwdata_15 : out std_logic; - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hsize_5 : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(0 to 0) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - addr_28 : out std_logic; - address_1 : out std_logic; - address_0 : out std_logic; - dataout : in std_logic_vector(35 downto 0) := (others => 'U'); - data_0_0_31 : out std_logic; - data_0_0_24 : out std_logic; - data_0_0_29 : out std_logic; - data_0_0_13 : out std_logic; - data_0_0_30 : out std_logic; - data_0_0_27 : out std_logic; - data_0_0_20 : out std_logic; - data_0_0_14 : out std_logic; - data_0_0_25 : out std_logic; - data_0_0_16 : out std_logic; - data_0_0_17 : out std_logic; - data_0_0_28 : out std_logic; - data_0_0_8 : out std_logic; - data_0_0_11 : out std_logic; - data_0_0_21 : out std_logic; - data_0_0_4 : out std_logic; - data_0_0_26 : out std_logic; - data_0_0_0 : out std_logic; - data_0_0_12 : out std_logic; - data_0_0_15 : out std_logic; - data_0_0_7 : out std_logic; - mcdo_m_0_29 : out std_logic; - mcdo_m_0_22 : out std_logic; - mcdo_m_0_27 : out std_logic; - mcdo_m_0_0 : out std_logic; - mcdo_m_0_16 : out std_logic; - mcdo_m_0_21 : out std_logic; - mcdo_m_0_20 : out std_logic; - mcdo_m_0_17 : out std_logic; - mcdo_m_0_4 : out std_logic; - mcdo_m_0_7 : out std_logic; - rdatav_0_1_0_iv_4_22 : out std_logic; - rdatav_0_1_0_iv_4_20 : out std_logic; - rdatav_0_1_0_iv_4_0 : out std_logic; - rdatav_0_1_0_iv_4_14 : out std_logic; - rdatav_0_1_0_iv_5_6 : out std_logic; - rdatav_0_1_0_iv_5_1 : out std_logic; - rdatav_0_1_0_iv_5_0 : out std_logic; - rdatav_0_1_0_iv_5_4 : out std_logic; - eaddress_29 : in std_logic := 'U'; - eaddress_22 : in std_logic := 'U'; - eaddress_21 : in std_logic := 'U'; - eaddress_13 : in std_logic := 'U'; - eaddress_28 : in std_logic := 'U'; - eaddress_18 : in std_logic := 'U'; - eaddress_6 : in std_logic := 'U'; - eaddress_10 : in std_logic := 'U'; - eaddress_25 : in std_logic := 'U'; - eaddress_23 : in std_logic := 'U'; - eaddress_19 : in std_logic := 'U'; - eaddress_9 : in std_logic := 'U'; - eaddress_17 : in std_logic := 'U'; - eaddress_27 : in std_logic := 'U'; - eaddress_15 : in std_logic := 'U'; - eaddress_5 : in std_logic := 'U'; - eaddress_20 : in std_logic := 'U'; - eaddress_2 : in std_logic := 'U'; - eaddress_24 : in std_logic := 'U'; - eaddress_16 : in std_logic := 'U'; - eaddress_12 : in std_logic := 'U'; - eaddress_4 : in std_logic := 'U'; - eaddress_1 : in std_logic := 'U'; - eaddress_8 : in std_logic := 'U'; - eaddress_0 : in std_logic := 'U'; - eaddress_3 : in std_logic := 'U'; - eaddress_7 : in std_logic := 'U'; - asi_4 : in std_logic := 'U'; - asi_3 : in std_logic := 'U'; - asi_2 : in std_logic := 'U'; - asi_1 : in std_logic := 'U'; - asi_0 : in std_logic_vector(0 to 0) := (others => 'U'); - rdatav_0_1_0_iv_7 : out std_logic_vector(2 to 2); - rdatav_0_1_0_iv_0_2 : out std_logic_vector(10 to 10); - rdatav_0_1_1_iv_7 : out std_logic_vector(6 to 6); - edata2_0_iv : in std_logic_vector(23 downto 0) := (others => 'U'); - newtag_1_0 : out std_logic_vector(27 downto 24); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dco_i_2 : out std_logic_vector(132 to 132); - size_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 downto 24) := (others => 'U'); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - faddr_RNI7879K : out std_logic_vector(0 to 0); - dci_m_0 : out std_logic; - dci_m_1 : out std_logic; - dci_m_2 : out std_logic; - dci_m_3 : out std_logic; - dci_m_5 : out std_logic; - dci_m_6 : out std_logic; - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - size_0_d0 : out std_logic; - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - data_10 : out std_logic; - data_8 : out std_logic; - data_5 : out std_logic; - data_13 : out std_logic; - data_24 : out std_logic; - data_29 : out std_logic; - un1_p0_2_0_350 : out std_logic; - un1_p0_2_0_0 : out std_logic; - fpc : in std_logic_vector(31 downto 2) := (others => 'U'); - dataout_2 : in std_logic_vector(31 downto 0) := (others => 'U'); - maddress : in std_logic_vector(31 downto 0) := (others => 'U'); - un1_p0_6 : in std_logic_vector(0 to 0) := (others => 'U'); - dataout_0 : in std_logic_vector(35 downto 0) := (others => 'U'); - dataout_1 : in std_logic_vector(31 downto 0) := (others => 'U'); - vitdatain_0_1_0 : in std_logic_vector(22 to 22) := (others => 'U'); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - istate_RNIA8N5H : out std_logic_vector(0 to 0); - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - data_0 : out std_logic_vector(31 downto 0); - rpc_0 : in std_logic := 'U'; - rpc_1 : in std_logic := 'U'; - rpc_3 : in std_logic := 'U'; - rpc_2 : in std_logic := 'U'; - rpc_7 : in std_logic := 'U'; - rpc_8 : in std_logic := 'U'; - rpc_5 : in std_logic := 'U'; - rpc_6 : in std_logic := 'U'; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - hrdata_9 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - istate_RNIPSU8G : out std_logic_vector(0 to 0); - maddress_0_0 : in std_logic := 'U'; - maddress_0_2 : in std_logic := 'U'; - istate_RNIEC82C : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNI5V68H : out std_logic_vector(0 to 0); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - istate_RNIH0NBI : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - istate_RNI57KLB : out std_logic_vector(0 to 0); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - istate_RNI6HPAI : out std_logic_vector(0 to 0); - ctx : out std_logic_vector(7 downto 0); - un1_p0_2_i_0 : out std_logic; - un1_p0_2_i_4 : out std_logic; - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - istate_RNIJCMP6 : out std_logic_vector(0 to 0); - N_546 : in std_logic := 'U'; - mmu_cache_VCC : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - bo_5842_d_0 : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - hlock : out std_logic; - N_5054 : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - hbusreq : out std_logic; - un60_nbo : out std_logic; - N_457 : out std_logic; - N_462 : out std_logic; - N_467 : out std_logic; - werr_2_m_0 : out std_logic; - un91_nbo_i_0 : out std_logic; - N_138 : out std_logic; - N_139 : out std_logic; - bo_5842_d : out std_logic; - N_458 : out std_logic; - N_459 : out std_logic; - N_461 : out std_logic; - N_463 : out std_logic; - N_468 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_466 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - werr : out std_logic; - N_3254_0 : out std_logic; - enaddr : in std_logic := 'U'; - lock_0 : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : out std_logic; - un1_addout_12 : in std_logic := 'U'; - read_0_0 : in std_logic := 'U'; - nullify : in std_logic := 'U'; - intack : in std_logic := 'U'; - nullify2_0_sqmuxa : in std_logic := 'U'; - me_nullify2_1_2 : in std_logic := 'U'; - un17_casaen_0_0 : in std_logic := 'U'; - N_330 : out std_logic; - N_329 : out std_logic; - N_24 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - N_16_i_0 : out std_logic; - N_12_i_0 : out std_logic; - read_RNIEEGDD1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNICAQK41 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNIC9O9B1 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIEKS231 : out std_logic; - N_26_0 : out std_logic; - N_3387_i_0 : out std_logic; - N_3227_i_0 : out std_logic; - N_3239_i_0 : out std_logic; - mexc_1 : out std_logic; - un59_nbo : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - read_RNICKHE91 : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI0IQ7R : out std_logic; - N_3389_i_0 : out std_logic; - read_RNIRO4K31 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIQH64D1 : out std_logic; - read_1 : in std_logic := 'U'; - r_N_6 : in std_logic := 'U'; - N_3305 : out std_logic; - N_3846 : out std_logic; - N_144 : out std_logic; - N_258 : out std_logic; - N_259 : out std_logic; - N_267 : out std_logic; - N_269 : out std_logic; - N_270 : out std_logic; - flush_RNIGBB873 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - msu : in std_logic := 'U'; - eenaddr : in std_logic := 'U'; - write : in std_logic := 'U'; - N_10 : out std_logic; - lclk_c : in std_logic := 'U'; - holdn : out std_logic; - rst : in std_logic := 'U'; - flush_i_0 : in std_logic := 'U'; - hold_pc_7 : in std_logic := 'U'; - de_hold_pc_1 : in std_logic := 'U'; - un1_ici : out std_logic; - xc_exception_1_0 : in std_logic := 'U'; - ldlock_2 : in std_logic := 'U'; - un9_icc_check_bp : in std_logic := 'U'; - ldlock_3_0 : in std_logic := 'U'; - inull : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_982 : out std_logic; - N_983 : out std_logic; - N_985 : out std_logic; - N_981 : out std_logic; - mds : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNI146O2 : out std_logic; - N_26 : in std_logic := 'U'; - flush2 : out std_logic; - N_986 : out std_logic; - N_987 : out std_logic; - N_28 : in std_logic := 'U'; - N_980 : out std_logic; - N_984 : out std_logic; - flush2_RNI5I3N7 : out std_logic; - flush2_RNIFMGM2 : out std_logic; - rbranch : in std_logic := 'U'; - fbranch : in std_logic := 'U'; - mexc : out std_logic; - su : in std_logic := 'U' - ); - end component; - - signal \asi[0]\, \asi[1]\, \asi[2]\, \asi[3]\, \asi[4]\, - \size[1]\, \size[0]\, \rdatav_0_1_1_iv_7[6]\, - \rdatav_0_1_0_iv_7[2]\, \rdatav_0_1_0_iv_0_2[10]\, - \rdatav_0_1_0_iv_5[22]\, \rdatav_0_1_0_iv_5[19]\, - \rdatav_0_1_0_iv_5[18]\, \rdatav_0_1_0_iv_5[24]\, - \data_0[13]\, \data_0[14]\, \data_0[17]\, \data_0[16]\, - \data_0[8]\, \data_0[24]\, \data_0[31]\, \data_0[30]\, - \data_0[29]\, \data_0[28]\, \data_0[27]\, \data_0[26]\, - \data_0[25]\, \data_0[21]\, \data_0[4]\, \data_0[0]\, - \edata2_iv_i_0[24]\, \edata2_iv_i_0[25]\, - \edata2_iv_i_0[26]\, \edata2_iv_i_0[27]\, - \edata2_iv_i_0[28]\, \edata2_iv_i_0[29]\, - \edata2_iv_i_0[30]\, \rpc[8]\, \rpc[10]\, \rpc[7]\, - \rpc[9]\, \rpc[4]\, \rpc[2]\, \rpc[3]\, \rpc[5]\, - \mcdo_m_0[29]\, \mcdo_m_0[31]\, \mcdo_m_0[6]\, - \mcdo_m_0[22]\, \mcdo_m_0[19]\, \mcdo_m_0[2]\, - \mcdo_m_0[18]\, \mcdo_m_0[9]\, \mcdo_m_0[24]\, - \mcdo_m_0[23]\, \rdatav_0_1_0_iv_4[29]\, - \rdatav_0_1_0_iv_4[31]\, \rdatav_0_1_0_iv_4[9]\, - \rdatav_0_1_0_iv_4[23]\, \maddress[0]\, \maddress[1]\, - \maddress[2]\, \maddress[3]\, \maddress[4]\, - \maddress[5]\, \maddress[6]\, \maddress[7]\, - \maddress[8]\, \maddress[9]\, \maddress[10]\, - \maddress[11]\, \maddress[12]\, \maddress[13]\, - \maddress[14]\, \maddress[15]\, \maddress[16]\, - \maddress[17]\, \maddress[18]\, \maddress[19]\, - \maddress[20]\, \maddress[21]\, \maddress[22]\, - \maddress[23]\, \maddress[24]\, \maddress[25]\, - \maddress[26]\, \maddress[27]\, \maddress[29]\, - \maddress[30]\, \maddress[31]\, \un1_p0_6[0]\, - \edata2_0_iv[0]\, \edata2_0_iv[1]\, \edata2_0_iv[2]\, - \edata2_0_iv[3]\, \edata2_0_iv[4]\, \edata2_0_iv[5]\, - \edata2_0_iv[6]\, \edata2_0_iv[7]\, \edata2_0_iv[8]\, - \edata2_0_iv[9]\, \edata2_0_iv[10]\, \edata2_0_iv[11]\, - \edata2_0_iv[12]\, \edata2_0_iv[13]\, \edata2_0_iv[14]\, - \edata2_0_iv[15]\, \edata2_0_iv[16]\, \edata2_0_iv[17]\, - \edata2_0_iv[18]\, \edata2_0_iv[19]\, \edata2_0_iv[20]\, - \edata2_0_iv[21]\, \edata2_0_iv[22]\, \edata2_0_iv[23]\, - \fpc[2]\, \fpc[3]\, \fpc[4]\, \fpc[5]\, \fpc[6]\, - \fpc[7]\, \fpc[8]\, \fpc[9]\, \fpc[10]\, \fpc[11]\, - \fpc[12]\, \fpc[13]\, \fpc[14]\, \fpc[15]\, \fpc[16]\, - \fpc[17]\, \fpc[18]\, \fpc[19]\, \fpc[20]\, \fpc[21]\, - \fpc[22]\, \fpc[23]\, \fpc[24]\, \fpc[25]\, \fpc[26]\, - \fpc[27]\, \fpc[28]\, \fpc[29]\, \fpc[30]\, \fpc[31]\, - \data_0[15]\, \data_0[20]\, \data_0[11]\, \data_0[6]\, - \data_0[23]\, \data_0[19]\, \data_0_0[17]\, - \data_0_0[16]\, \data_0_0[14]\, \data_0_0[13]\, - \data_0[12]\, \data_0[10]\, \data_0[9]\, \data_0[7]\, - \data_0[5]\, \data_0[3]\, \data_0[2]\, \data_0[1]\, - \data_0_0[0]\, \data_0_0[4]\, \data_0_0[26]\, - \data_0_0[8]\, \data_0_0[28]\, \data_0_0[27]\, - \data_0_0[30]\, \data_0_0[25]\, \data_0_0[24]\, - \data_0_0[21]\, \eaddress[4]\, \eaddress[2]\, - \eaddress[12]\, \eaddress[24]\, \eaddress[5]\, - \eaddress[11]\, \eaddress[30]\, \eaddress[6]\, - \eaddress[3]\, \eaddress[27]\, \eaddress[31]\, - \eaddress[15]\, \eaddress[17]\, \eaddress[20]\, - \eaddress[18]\, \eaddress[26]\, \eaddress[14]\, - \eaddress[21]\, \eaddress[25]\, \eaddress[29]\, - \eaddress[19]\, \eaddress[23]\, \eaddress[22]\, - \eaddress[9]\, \eaddress[10]\, \eaddress[7]\, - \eaddress[8]\, \data_0[22]\, \data_0_0[20]\, \data_0[18]\, - \data_0_0[15]\, \data_0_0[11]\, \data_0_0[7]\, - \data_0_0[12]\, \data_0_0[31]\, \data_0_0[29]\, - \dco_i_2[132]\, \maddress_0[3]\, \maddress_0[1]\, msu, - read, write, mexc, enaddr, eenaddr, N_26, lock, N_28, su, - mexc_0, N_3305, werr, vaddr_1_sqmuxa_0_a2_4_m1_e_24, - ldlock_3_0, rbranch, r_N_6, un1_addout_12, flush_i_0, - N_3389_i_0, N_3227_i_0, N_3387_i_0, nullify, ldlock_2, - fbranch, hold_pc_7, nullify2_0_sqmuxa, me_nullify2_1_2, - un9_icc_check_bp, inull, de_hold_pc_1, un17_casaen_0_0, - xc_exception_1_0, mds, read_0, holdn, \edata2_iv_i_0[31]\, - \maddress[28]\, \intack\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : iu3 - Use entity work.iu3(DEF_ARCH); - for all : mmu_cache - Use entity work.mmu_cache(DEF_ARCH); -begin - - maddress_28 <= \maddress[28]\; - edata2_iv_i_0_7 <= \edata2_iv_i_0[31]\; - intack <= \intack\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - iu0 : iu3 - port map(asi_0(4) => \asi[4]\, asi_0(3) => \asi[3]\, - asi_0(2) => \asi[2]\, asi_0(1) => \asi[1]\, asi_0(0) => - \asi[0]\, wdata(31) => wdata(31), wdata(30) => wdata(30), - wdata(29) => wdata(29), wdata(28) => wdata(28), wdata(27) - => wdata(27), wdata(26) => wdata(26), wdata(25) => - wdata(25), wdata(24) => wdata(24), wdata(23) => wdata(23), - wdata(22) => wdata(22), wdata(21) => wdata(21), wdata(20) - => wdata(20), wdata(19) => wdata(19), wdata(18) => - wdata(18), wdata(17) => wdata(17), wdata(16) => wdata(16), - wdata(15) => wdata(15), wdata(14) => wdata(14), wdata(13) - => wdata(13), wdata(12) => wdata(12), wdata(11) => - wdata(11), wdata(10) => wdata(10), wdata(9) => wdata(9), - wdata(8) => wdata(8), wdata(7) => wdata(7), wdata(6) => - wdata(6), wdata(5) => wdata(5), wdata(4) => wdata(4), - wdata(3) => wdata(3), wdata(2) => wdata(2), wdata(1) => - wdata(1), wdata(0) => wdata(0), size_0_1 => \size[1]\, - size_1_0 => \size[0]\, rdatav_0_1_1_iv_7(6) => - \rdatav_0_1_1_iv_7[6]\, rdatav_0_1_0_iv_7(2) => - \rdatav_0_1_0_iv_7[2]\, rdatav_0_1_0_iv_0_2(10) => - \rdatav_0_1_0_iv_0_2[10]\, rdatav_0_1_0_iv_5_4 => - \rdatav_0_1_0_iv_5[22]\, rdatav_0_1_0_iv_5_1 => - \rdatav_0_1_0_iv_5[19]\, rdatav_0_1_0_iv_5_0 => - \rdatav_0_1_0_iv_5[18]\, rdatav_0_1_0_iv_5_6 => - \rdatav_0_1_0_iv_5[24]\, waddr(7) => waddr(7), waddr(6) - => waddr(6), waddr(5) => waddr(5), waddr(4) => waddr(4), - waddr(3) => waddr(3), waddr(2) => waddr(2), waddr(1) => - waddr(1), waddr(0) => waddr(0), rfa2(7) => rfa2(7), - rfa2(6) => rfa2(6), rfa2(5) => rfa2(5), rfa2(4) => - rfa2(4), rfa2(3) => rfa2(3), rfa2(2) => rfa2(2), rfa2(1) - => rfa2(1), rfa2(0) => rfa2(0), raddr2(7) => raddr2(7), - raddr2(6) => raddr2(6), raddr2(5) => raddr2(5), raddr2(4) - => raddr2(4), raddr2(3) => raddr2(3), raddr2(2) => - raddr2(2), raddr2(1) => raddr2(1), raddr2(0) => raddr2(0), - rfa1(7) => rfa1(7), rfa1(6) => rfa1(6), rfa1(5) => - rfa1(5), rfa1(4) => rfa1(4), rfa1(3) => rfa1(3), rfa1(2) - => rfa1(2), rfa1(1) => rfa1(1), rfa1(0) => rfa1(0), - raddr1(7) => raddr1(7), raddr1(6) => raddr1(6), raddr1(5) - => raddr1(5), raddr1(4) => raddr1(4), raddr1(3) => - raddr1(3), raddr1(2) => raddr1(2), raddr1(1) => raddr1(1), - raddr1(0) => raddr1(0), data_0_2_13 => \data_0[13]\, - data_0_2_14 => \data_0[14]\, data_0_2_17 => \data_0[17]\, - data_0_2_16 => \data_0[16]\, data_0_2_8 => \data_0[8]\, - data_0_2_24 => \data_0[24]\, data_0_2_31 => \data_0[31]\, - data_0_2_30 => \data_0[30]\, data_0_2_29 => \data_0[29]\, - data_0_2_28 => \data_0[28]\, data_0_2_27 => \data_0[27]\, - data_0_2_26 => \data_0[26]\, data_0_2_25 => \data_0[25]\, - data_0_2_21 => \data_0[21]\, data_0_2_4 => \data_0[4]\, - data_0_2_0 => \data_0[0]\, edata2_iv_i_0(31) => - \edata2_iv_i_0[31]\, edata2_iv_i_0(30) => - \edata2_iv_i_0[30]\, edata2_iv_i_0(29) => - \edata2_iv_i_0[29]\, edata2_iv_i_0(28) => - \edata2_iv_i_0[28]\, edata2_iv_i_0(27) => - \edata2_iv_i_0[27]\, edata2_iv_i_0(26) => - \edata2_iv_i_0[26]\, edata2_iv_i_0(25) => - \edata2_iv_i_0[25]\, edata2_iv_i_0(24) => - \edata2_iv_i_0[24]\, rpc_6 => \rpc[8]\, rpc_8 => - \rpc[10]\, rpc_5 => \rpc[7]\, rpc_7 => \rpc[9]\, rpc_2 - => \rpc[4]\, rpc_0 => \rpc[2]\, rpc_1 => \rpc[3]\, rpc_3 - => \rpc[5]\, irl_0(3) => irl(3), irl_0(2) => irl(2), - irl_0(1) => irl(1), irl_0(0) => irl(0), irl(3) => - irl_0(3), irl(2) => irl_0(2), irl(1) => irl_0(1), irl(0) - => irl_0(0), data2(31) => data2(31), data2(30) => - data2(30), data2(29) => data2(29), data2(28) => data2(28), - data2(27) => data2(27), data2(26) => data2(26), data2(25) - => data2(25), data2(24) => data2(24), data2(23) => - data2(23), data2(22) => data2(22), data2(21) => data2(21), - data2(20) => data2(20), data2(19) => data2(19), data2(18) - => data2(18), data2(17) => data2(17), data2(16) => - data2(16), data2(15) => data2(15), data2(14) => data2(14), - data2(13) => data2(13), data2(12) => data2(12), data2(11) - => data2(11), data2(10) => data2(10), data2(9) => - data2(9), data2(8) => data2(8), data2(7) => data2(7), - data2(6) => data2(6), data2(5) => data2(5), data2(4) => - data2(4), data2(3) => data2(3), data2(2) => data2(2), - data2(1) => data2(1), data2(0) => data2(0), mcdo_m_0_27 - => \mcdo_m_0[29]\, mcdo_m_0_29 => \mcdo_m_0[31]\, - mcdo_m_0_4 => \mcdo_m_0[6]\, mcdo_m_0_20 => - \mcdo_m_0[22]\, mcdo_m_0_17 => \mcdo_m_0[19]\, mcdo_m_0_0 - => \mcdo_m_0[2]\, mcdo_m_0_16 => \mcdo_m_0[18]\, - mcdo_m_0_7 => \mcdo_m_0[9]\, mcdo_m_0_22 => - \mcdo_m_0[24]\, mcdo_m_0_21 => \mcdo_m_0[23]\, - rdatav_0_1_0_iv_4_20 => \rdatav_0_1_0_iv_4[29]\, - rdatav_0_1_0_iv_4_22 => \rdatav_0_1_0_iv_4[31]\, - rdatav_0_1_0_iv_4_0 => \rdatav_0_1_0_iv_4[9]\, - rdatav_0_1_0_iv_4_14 => \rdatav_0_1_0_iv_4[23]\, - maddress(31) => \maddress[31]\, maddress(30) => - \maddress[30]\, maddress(29) => \maddress[29]\, - maddress(28) => \maddress[28]\, maddress(27) => - \maddress[27]\, maddress(26) => \maddress[26]\, - maddress(25) => \maddress[25]\, maddress(24) => - \maddress[24]\, maddress(23) => \maddress[23]\, - maddress(22) => \maddress[22]\, maddress(21) => - \maddress[21]\, maddress(20) => \maddress[20]\, - maddress(19) => \maddress[19]\, maddress(18) => - \maddress[18]\, maddress(17) => \maddress[17]\, - maddress(16) => \maddress[16]\, maddress(15) => - \maddress[15]\, maddress(14) => \maddress[14]\, - maddress(13) => \maddress[13]\, maddress(12) => - \maddress[12]\, maddress(11) => \maddress[11]\, - maddress(10) => \maddress[10]\, maddress(9) => - \maddress[9]\, maddress(8) => \maddress[8]\, maddress(7) - => \maddress[7]\, maddress(6) => \maddress[6]\, - maddress(5) => \maddress[5]\, maddress(4) => - \maddress[4]\, maddress(3) => \maddress[3]\, maddress(2) - => \maddress[2]\, maddress(1) => \maddress[1]\, - maddress(0) => \maddress[0]\, data1(31) => data1(31), - data1(30) => data1(30), data1(29) => data1(29), data1(28) - => data1(28), data1(27) => data1(27), data1(26) => - data1(26), data1(25) => data1(25), data1(24) => data1(24), - data1(23) => data1(23), data1(22) => data1(22), data1(21) - => data1(21), data1(20) => data1(20), data1(19) => - data1(19), data1(18) => data1(18), data1(17) => data1(17), - data1(16) => data1(16), data1(15) => data1(15), data1(14) - => data1(14), data1(13) => data1(13), data1(12) => - data1(12), data1(11) => data1(11), data1(10) => data1(10), - data1(9) => data1(9), data1(8) => data1(8), data1(7) => - data1(7), data1(6) => data1(6), data1(5) => data1(5), - data1(4) => data1(4), data1(3) => data1(3), data1(2) => - data1(2), data1(1) => data1(1), data1(0) => data1(0), - un1_p0_6_0 => \un1_p0_6[0]\, edata2_0_iv(23) => - \edata2_0_iv[23]\, edata2_0_iv(22) => \edata2_0_iv[22]\, - edata2_0_iv(21) => \edata2_0_iv[21]\, edata2_0_iv(20) => - \edata2_0_iv[20]\, edata2_0_iv(19) => \edata2_0_iv[19]\, - edata2_0_iv(18) => \edata2_0_iv[18]\, edata2_0_iv(17) => - \edata2_0_iv[17]\, edata2_0_iv(16) => \edata2_0_iv[16]\, - edata2_0_iv(15) => \edata2_0_iv[15]\, edata2_0_iv(14) => - \edata2_0_iv[14]\, edata2_0_iv(13) => \edata2_0_iv[13]\, - edata2_0_iv(12) => \edata2_0_iv[12]\, edata2_0_iv(11) => - \edata2_0_iv[11]\, edata2_0_iv(10) => \edata2_0_iv[10]\, - edata2_0_iv(9) => \edata2_0_iv[9]\, edata2_0_iv(8) => - \edata2_0_iv[8]\, edata2_0_iv(7) => \edata2_0_iv[7]\, - edata2_0_iv(6) => \edata2_0_iv[6]\, edata2_0_iv(5) => - \edata2_0_iv[5]\, edata2_0_iv(4) => \edata2_0_iv[4]\, - edata2_0_iv(3) => \edata2_0_iv[3]\, edata2_0_iv(2) => - \edata2_0_iv[2]\, edata2_0_iv(1) => \edata2_0_iv[1]\, - edata2_0_iv(0) => \edata2_0_iv[0]\, fpc(31) => \fpc[31]\, - fpc(30) => \fpc[30]\, fpc(29) => \fpc[29]\, fpc(28) => - \fpc[28]\, fpc(27) => \fpc[27]\, fpc(26) => \fpc[26]\, - fpc(25) => \fpc[25]\, fpc(24) => \fpc[24]\, fpc(23) => - \fpc[23]\, fpc(22) => \fpc[22]\, fpc(21) => \fpc[21]\, - fpc(20) => \fpc[20]\, fpc(19) => \fpc[19]\, fpc(18) => - \fpc[18]\, fpc(17) => \fpc[17]\, fpc(16) => \fpc[16]\, - fpc(15) => \fpc[15]\, fpc(14) => \fpc[14]\, fpc(13) => - \fpc[13]\, fpc(12) => \fpc[12]\, fpc(11) => \fpc[11]\, - fpc(10) => \fpc[10]\, fpc(9) => \fpc[9]\, fpc(8) => - \fpc[8]\, fpc(7) => \fpc[7]\, fpc(6) => \fpc[6]\, fpc(5) - => \fpc[5]\, fpc(4) => \fpc[4]\, fpc(3) => \fpc[3]\, - fpc(2) => \fpc[2]\, data_0_0_15 => \data_0[15]\, - data_0_0_20 => \data_0[20]\, data_0_0_11 => \data_0[11]\, - data_0_0_6 => \data_0[6]\, data_0_0_23 => \data_0[23]\, - data_0_0_19 => \data_0[19]\, data_0_0_17 => - \data_0_0[17]\, data_0_0_16 => \data_0_0[16]\, - data_0_0_14 => \data_0_0[14]\, data_0_0_13 => - \data_0_0[13]\, data_0_0_12 => \data_0[12]\, data_0_0_10 - => \data_0[10]\, data_0_0_9 => \data_0[9]\, data_0_0_7 - => \data_0[7]\, data_0_0_5 => \data_0[5]\, data_0_0_3 - => \data_0[3]\, data_0_0_2 => \data_0[2]\, data_0_0_1 - => \data_0[1]\, data_0_0_0 => \data_0_0[0]\, data_0_0_4 - => \data_0_0[4]\, data_0_0_26 => \data_0_0[26]\, - data_0_0_8 => \data_0_0[8]\, data_0_0_28 => - \data_0_0[28]\, data_0_0_27 => \data_0_0[27]\, - data_0_0_30 => \data_0_0[30]\, data_0_0_25 => - \data_0_0[25]\, data_0_0_24 => \data_0_0[24]\, - data_0_0_21 => \data_0_0[21]\, eaddress_4 => - \eaddress[4]\, eaddress_2 => \eaddress[2]\, eaddress_12 - => \eaddress[12]\, eaddress_24 => \eaddress[24]\, - eaddress_5 => \eaddress[5]\, eaddress_11 => - \eaddress[11]\, eaddress_30 => \eaddress[30]\, eaddress_6 - => \eaddress[6]\, eaddress_3 => \eaddress[3]\, - eaddress_27 => \eaddress[27]\, eaddress_31 => - \eaddress[31]\, eaddress_15 => \eaddress[15]\, - eaddress_17 => \eaddress[17]\, eaddress_20 => - \eaddress[20]\, eaddress_18 => \eaddress[18]\, - eaddress_26 => \eaddress[26]\, eaddress_14 => - \eaddress[14]\, eaddress_21 => \eaddress[21]\, - eaddress_25 => \eaddress[25]\, eaddress_29 => - \eaddress[29]\, eaddress_19 => \eaddress[19]\, - eaddress_23 => \eaddress[23]\, eaddress_22 => - \eaddress[22]\, eaddress_9 => \eaddress[9]\, eaddress_10 - => \eaddress[10]\, eaddress_7 => \eaddress[7]\, - eaddress_8 => \eaddress[8]\, data_0_22 => \data_0[22]\, - data_0_20 => \data_0_0[20]\, data_0_18 => \data_0[18]\, - data_0_15 => \data_0_0[15]\, data_0_11 => \data_0_0[11]\, - data_0_7 => \data_0_0[7]\, data_0_12 => \data_0_0[12]\, - data_0_31 => \data_0_0[31]\, data_0_29 => \data_0_0[29]\, - dco_i_2(132) => \dco_i_2[132]\, maddress_0_2 => - \maddress_0[3]\, maddress_0_0 => \maddress_0[1]\, msu => - msu, error_i_2 => error_i_2, read_1 => read, write_0 => - write, mexc_2 => mexc, enaddr => enaddr, eenaddr => - eenaddr, N_26 => N_26, lock => lock, N_28 => N_28, su_0 - => su, rfe2 => rfe2, ren2 => ren2, mexc => mexc_0, - N_3305_0 => N_3305, intack_2 => \intack\, wren => wren, - rfe1 => rfe1, ren1 => ren1, werr_2 => werr, rstate_1188n - => rstate_1188n, vaddr_1_sqmuxa_0_a2_4_m1_e_24 => - vaddr_1_sqmuxa_0_a2_4_m1_e_24, ldlock_3_0 => ldlock_3_0, - rst_RNIINI1H => rst_RNIINI1H, rbranch => rbranch, r_N_6 - => r_N_6, un1_addout_12 => un1_addout_12, flush_i_0 => - flush_i_0, N_3389_i_0 => N_3389_i_0, N_3227_i_0 => - N_3227_i_0, N_3387_i_0 => N_3387_i_0, nullify => nullify, - ldlock_2 => ldlock_2, fbranch => fbranch, d_m5_0_a3_2 => - d_m5_0_a3_2, hold_pc_7 => hold_pc_7, nullify2_0_sqmuxa - => nullify2_0_sqmuxa, me_nullify2_1_2 => me_nullify2_1_2, - un9_icc_check_bp => un9_icc_check_bp, inull => inull, - de_hold_pc_1 => de_hold_pc_1, rst => rst, un17_casaen_0_0 - => un17_casaen_0_0, xc_exception_1_0 => xc_exception_1_0, - mds => mds, ra_bpmiss_1_0 => ra_bpmiss_1_0, read_0 => - read_0, holdn => holdn, lclk_c => lclk_c); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - c0mmu : mmu_cache - port map(hrdata_1_0_1(1) => hrdata_1_0_1(1), data_2_17 => - data_24, data_2_12 => data_19, data_2_1 => data_8, - data_1_10 => data_5, data_1_8 => data_3, nbo_5_0(1) => - nbo_5_0(1), nbo_5_0(0) => nbo_5_0(0), htrans(1) => - htrans(1), iosn_0(93) => iosn_0(93), htrans_tz(1) => - htrans_tz(1), haddr(31) => haddr(31), haddr(30) => - haddr(30), haddr(29) => haddr(29), haddr(28) => haddr(28), - haddr(27) => haddr(27), haddr(26) => haddr(26), haddr(25) - => haddr(25), haddr(24) => haddr(24), haddr(23) => - haddr(23), haddr(22) => haddr(22), haddr(21) => haddr(21), - haddr(20) => haddr(20), haddr(19) => haddr(19), haddr(18) - => haddr(18), haddr(17) => haddr(17), haddr(16) => - haddr(16), haddr(15) => haddr(15), haddr(14) => haddr(14), - haddr(13) => haddr(13), haddr(12) => haddr(12), haddr(11) - => haddr(11), haddr(10) => haddr(10), haddr(9) => - haddr(9), haddr(8) => haddr(8), haddr(7) => haddr(7), - haddr(6) => haddr(6), haddr(5) => haddr(5), haddr(4) => - haddr(4), haddr(3) => haddr(3), haddr(2) => haddr(2), - hwdata_16 => hwdata_16, hwdata_3 => hwdata_3, hwdata_9 - => hwdata_9, hwdata_11 => hwdata_11, hwdata_25 => - hwdata_25, hwdata_27 => hwdata_27, hwdata_13 => hwdata_13, - hwdata_4 => hwdata_4, hwdata_12 => hwdata_12, hwdata_23 - => hwdata_23, hwdata_28 => hwdata_28, hwdata_1 => - hwdata_1, hwdata_14 => hwdata_14, hwdata_0 => hwdata_0, - hwdata_15 => hwdata_15, iosn_1(93) => iosn_1(93), - hsize_5(1) => hsize_5(1), hgrant(0) => hgrant(0), - hresp(0) => hresp(0), iosn_2(93) => iosn_2(93), addr_28 - => addr(30), address_1 => address(1), address_0 => - address(0), dataout(35) => dataout(35), dataout(34) => - dataout(34), dataout(33) => dataout(33), dataout(32) => - dataout(32), dataout(31) => dataout(31), dataout(30) => - dataout(30), dataout(29) => dataout(29), dataout(28) => - dataout(28), dataout(27) => dataout(27), dataout(26) => - dataout(26), dataout(25) => dataout(25), dataout(24) => - dataout(24), dataout(23) => dataout(23), dataout(22) => - dataout(22), dataout(21) => dataout(21), dataout(20) => - dataout(20), dataout(19) => dataout(19), dataout(18) => - dataout(18), dataout(17) => dataout(17), dataout(16) => - dataout(16), dataout(15) => dataout(15), dataout(14) => - dataout(14), dataout(13) => dataout(13), dataout(12) => - dataout(12), dataout(11) => dataout(11), dataout(10) => - dataout(10), dataout(9) => dataout(9), dataout(8) => - dataout(8), dataout(7) => dataout(7), dataout(6) => - dataout(6), dataout(5) => dataout(5), dataout(4) => - dataout(4), dataout(3) => dataout(3), dataout(2) => - dataout(2), dataout(1) => dataout(1), dataout(0) => - dataout(0), data_0_0_31 => \data_0_0[31]\, data_0_0_24 - => \data_0_0[24]\, data_0_0_29 => \data_0_0[29]\, - data_0_0_13 => \data_0[13]\, data_0_0_30 => - \data_0_0[30]\, data_0_0_27 => \data_0_0[27]\, - data_0_0_20 => \data_0[20]\, data_0_0_14 => \data_0[14]\, - data_0_0_25 => \data_0_0[25]\, data_0_0_16 => - \data_0[16]\, data_0_0_17 => \data_0[17]\, data_0_0_28 - => \data_0_0[28]\, data_0_0_8 => \data_0_0[8]\, - data_0_0_11 => \data_0[11]\, data_0_0_21 => - \data_0_0[21]\, data_0_0_4 => \data_0_0[4]\, data_0_0_26 - => \data_0_0[26]\, data_0_0_0 => \data_0_0[0]\, - data_0_0_12 => \data_0_0[12]\, data_0_0_15 => - \data_0[15]\, data_0_0_7 => \data_0_0[7]\, mcdo_m_0_29 - => \mcdo_m_0[31]\, mcdo_m_0_22 => \mcdo_m_0[24]\, - mcdo_m_0_27 => \mcdo_m_0[29]\, mcdo_m_0_0 => - \mcdo_m_0[2]\, mcdo_m_0_16 => \mcdo_m_0[18]\, mcdo_m_0_21 - => \mcdo_m_0[23]\, mcdo_m_0_20 => \mcdo_m_0[22]\, - mcdo_m_0_17 => \mcdo_m_0[19]\, mcdo_m_0_4 => - \mcdo_m_0[6]\, mcdo_m_0_7 => \mcdo_m_0[9]\, - rdatav_0_1_0_iv_4_22 => \rdatav_0_1_0_iv_4[31]\, - rdatav_0_1_0_iv_4_20 => \rdatav_0_1_0_iv_4[29]\, - rdatav_0_1_0_iv_4_0 => \rdatav_0_1_0_iv_4[9]\, - rdatav_0_1_0_iv_4_14 => \rdatav_0_1_0_iv_4[23]\, - rdatav_0_1_0_iv_5_6 => \rdatav_0_1_0_iv_5[24]\, - rdatav_0_1_0_iv_5_1 => \rdatav_0_1_0_iv_5[19]\, - rdatav_0_1_0_iv_5_0 => \rdatav_0_1_0_iv_5[18]\, - rdatav_0_1_0_iv_5_4 => \rdatav_0_1_0_iv_5[22]\, - eaddress_29 => \eaddress[31]\, eaddress_22 => - \eaddress[24]\, eaddress_21 => \eaddress[23]\, - eaddress_13 => \eaddress[15]\, eaddress_28 => - \eaddress[30]\, eaddress_18 => \eaddress[20]\, eaddress_6 - => \eaddress[8]\, eaddress_10 => \eaddress[12]\, - eaddress_25 => \eaddress[27]\, eaddress_23 => - \eaddress[25]\, eaddress_19 => \eaddress[21]\, eaddress_9 - => \eaddress[11]\, eaddress_17 => \eaddress[19]\, - eaddress_27 => \eaddress[29]\, eaddress_15 => - \eaddress[17]\, eaddress_5 => \eaddress[7]\, eaddress_20 - => \eaddress[22]\, eaddress_2 => \eaddress[4]\, - eaddress_24 => \eaddress[26]\, eaddress_16 => - \eaddress[18]\, eaddress_12 => \eaddress[14]\, eaddress_4 - => \eaddress[6]\, eaddress_1 => \eaddress[3]\, - eaddress_8 => \eaddress[10]\, eaddress_0 => \eaddress[2]\, - eaddress_3 => \eaddress[5]\, eaddress_7 => \eaddress[9]\, - asi_4 => \asi[4]\, asi_3 => \asi[3]\, asi_2 => \asi[2]\, - asi_1 => \asi[1]\, asi_0(0) => \asi[0]\, - rdatav_0_1_0_iv_7(2) => \rdatav_0_1_0_iv_7[2]\, - rdatav_0_1_0_iv_0_2(10) => \rdatav_0_1_0_iv_0_2[10]\, - rdatav_0_1_1_iv_7(6) => \rdatav_0_1_1_iv_7[6]\, - edata2_0_iv(23) => \edata2_0_iv[23]\, edata2_0_iv(22) => - \edata2_0_iv[22]\, edata2_0_iv(21) => \edata2_0_iv[21]\, - edata2_0_iv(20) => \edata2_0_iv[20]\, edata2_0_iv(19) => - \edata2_0_iv[19]\, edata2_0_iv(18) => \edata2_0_iv[18]\, - edata2_0_iv(17) => \edata2_0_iv[17]\, edata2_0_iv(16) => - \edata2_0_iv[16]\, edata2_0_iv(15) => \edata2_0_iv[15]\, - edata2_0_iv(14) => \edata2_0_iv[14]\, edata2_0_iv(13) => - \edata2_0_iv[13]\, edata2_0_iv(12) => \edata2_0_iv[12]\, - edata2_0_iv(11) => \edata2_0_iv[11]\, edata2_0_iv(10) => - \edata2_0_iv[10]\, edata2_0_iv(9) => \edata2_0_iv[9]\, - edata2_0_iv(8) => \edata2_0_iv[8]\, edata2_0_iv(7) => - \edata2_0_iv[7]\, edata2_0_iv(6) => \edata2_0_iv[6]\, - edata2_0_iv(5) => \edata2_0_iv[5]\, edata2_0_iv(4) => - \edata2_0_iv[4]\, edata2_0_iv(3) => \edata2_0_iv[3]\, - edata2_0_iv(2) => \edata2_0_iv[2]\, edata2_0_iv(1) => - \edata2_0_iv[1]\, edata2_0_iv(0) => \edata2_0_iv[0]\, - newtag_1_0(27) => newtag_1_0(27), newtag_1_0(26) => - newtag_1_0(26), newtag_1_0(25) => newtag_1_0(25), - newtag_1_0(24) => newtag_1_0(24), xaddress_RNID252J1(10) - => xaddress_RNID252J1(10), dstate_i_0_RNIL7FGFS(8) => - dstate_i_0_RNIL7FGFS(8), xaddress_RNI2MB27S2(15) => - xaddress_RNI2MB27S2(15), xaddress_RNIID927S2(16) => - xaddress_RNIID927S2(16), xaddress_RNIN7J17S2(14) => - xaddress_RNIN7J17S2(14), xaddress_RNIC5A27S2(21) => - xaddress_RNIC5A27S2(21), xaddress_RNI0GI17S2(17) => - xaddress_RNI0GI17S2(17), xaddress_RNI9MB27S2(23) => - xaddress_RNI9MB27S2(23), xaddress_RNI1D927S2(20) => - xaddress_RNI1D927S2(20), xaddress_RNICFI17S2(13) => - xaddress_RNICFI17S2(13), xaddress_RNITMH17S2(12) => - xaddress_RNITMH17S2(12), xaddress_RNIJI2O22(1) => - xaddress_RNIJI2O22(1), xaddress_RNIP2BVK1(1) => - xaddress_RNIP2BVK1(1), xaddress_RNIK99NK1(1) => - xaddress_RNIK99NK1(1), xaddress_RNI1I3MQ1(0) => - xaddress_RNI1I3MQ1(0), xaddress_RNILK99L1(1) => - xaddress_RNILK99L1(1), xaddress_RNILHOK61(1) => - xaddress_RNILHOK61(1), xaddress_RNIEHIUT1(1) => - xaddress_RNIEHIUT1(1), xaddress_RNI1Q9ST1(1) => - xaddress_RNI1Q9ST1(1), dstate_RNIFS6E51(1) => - dstate_RNIFS6E51(1), dstate_RNI1G47MJ(1) => - dstate_RNI1G47MJ(1), dstate_i_0_RNIH0PPES(8) => - dstate_i_0_RNIH0PPES(8), dco_i_2(132) => \dco_i_2[132]\, - size_0(1) => \size[1]\, size_0(0) => \size[0]\, - dstate_RNIFPT581(1) => dstate_RNIFPT581(1), - dstate_RNIC3QA81(1) => dstate_RNIC3QA81(1), - edata2_iv_i_0(31) => \edata2_iv_i_0[31]\, - edata2_iv_i_0(30) => \edata2_iv_i_0[30]\, - edata2_iv_i_0(29) => \edata2_iv_i_0[29]\, - edata2_iv_i_0(28) => \edata2_iv_i_0[28]\, - edata2_iv_i_0(27) => \edata2_iv_i_0[27]\, - edata2_iv_i_0(26) => \edata2_iv_i_0[26]\, - edata2_iv_i_0(25) => \edata2_iv_i_0[25]\, - edata2_iv_i_0(24) => \edata2_iv_i_0[24]\, - faddr_RNIEHR0O(1) => faddr_RNIEHR0O(1), faddr_RNI7879K(0) - => faddr_RNI7879K(0), dci_m_0 => dci_m_0, dci_m_1 => - dci_m_1, dci_m_2 => dci_m_2, dci_m_3 => dci_m_3, dci_m_5 - => dci_m_5, dci_m_6 => dci_m_6, faddr_RNI7MK691(6) => - faddr_RNI7MK691(6), size_0_d0 => size_0(0), - xaddress_RNIFP43F(2) => xaddress_RNIFP43F(2), - xaddress_RNITFTTE(3) => xaddress_RNITFTTE(3), - dstate_i_RNI29QQ7J3(8) => dstate_i_RNI29QQ7J3(8), - faddr_RNIB0UOO(2) => faddr_RNIB0UOO(2), data_10 => - data_1_2, data_8 => data_1_0, data_5 => data_0, data_13 - => data_1_5, data_24 => data_1_16, data_29 => data_1_21, - un1_p0_2_0_350 => un1_p0_2_0_350, un1_p0_2_0_0 => - un1_p0_2_0_0, fpc(31) => \fpc[31]\, fpc(30) => \fpc[30]\, - fpc(29) => \fpc[29]\, fpc(28) => \fpc[28]\, fpc(27) => - \fpc[27]\, fpc(26) => \fpc[26]\, fpc(25) => \fpc[25]\, - fpc(24) => \fpc[24]\, fpc(23) => \fpc[23]\, fpc(22) => - \fpc[22]\, fpc(21) => \fpc[21]\, fpc(20) => \fpc[20]\, - fpc(19) => \fpc[19]\, fpc(18) => \fpc[18]\, fpc(17) => - \fpc[17]\, fpc(16) => \fpc[16]\, fpc(15) => \fpc[15]\, - fpc(14) => \fpc[14]\, fpc(13) => \fpc[13]\, fpc(12) => - \fpc[12]\, fpc(11) => \fpc[11]\, fpc(10) => \fpc[10]\, - fpc(9) => \fpc[9]\, fpc(8) => \fpc[8]\, fpc(7) => - \fpc[7]\, fpc(6) => \fpc[6]\, fpc(5) => \fpc[5]\, fpc(4) - => \fpc[4]\, fpc(3) => \fpc[3]\, fpc(2) => \fpc[2]\, - dataout_2(31) => dataout_2(31), dataout_2(30) => - dataout_2(30), dataout_2(29) => dataout_2(29), - dataout_2(28) => dataout_2(28), dataout_2(27) => - dataout_2(27), dataout_2(26) => dataout_2(26), - dataout_2(25) => dataout_2(25), dataout_2(24) => - dataout_2(24), dataout_2(23) => dataout_2(23), - dataout_2(22) => dataout_2(22), dataout_2(21) => - dataout_2(21), dataout_2(20) => dataout_2(20), - dataout_2(19) => dataout_2(19), dataout_2(18) => - dataout_2(18), dataout_2(17) => dataout_2(17), - dataout_2(16) => dataout_2(16), dataout_2(15) => - dataout_2(15), dataout_2(14) => dataout_2(14), - dataout_2(13) => dataout_2(13), dataout_2(12) => - dataout_2(12), dataout_2(11) => dataout_2(11), - dataout_2(10) => dataout_2(10), dataout_2(9) => - dataout_2(9), dataout_2(8) => dataout_2(8), dataout_2(7) - => dataout_2(7), dataout_2(6) => dataout_2(6), - dataout_2(5) => dataout_2(5), dataout_2(4) => - dataout_2(4), dataout_2(3) => dataout_2(3), dataout_2(2) - => dataout_2(2), dataout_2(1) => dataout_2(1), - dataout_2(0) => dataout_2(0), maddress(31) => - \maddress[31]\, maddress(30) => \maddress[30]\, - maddress(29) => \maddress[29]\, maddress(28) => - \maddress[28]\, maddress(27) => \maddress[27]\, - maddress(26) => \maddress[26]\, maddress(25) => - \maddress[25]\, maddress(24) => \maddress[24]\, - maddress(23) => \maddress[23]\, maddress(22) => - \maddress[22]\, maddress(21) => \maddress[21]\, - maddress(20) => \maddress[20]\, maddress(19) => - \maddress[19]\, maddress(18) => \maddress[18]\, - maddress(17) => \maddress[17]\, maddress(16) => - \maddress[16]\, maddress(15) => \maddress[15]\, - maddress(14) => \maddress[14]\, maddress(13) => - \maddress[13]\, maddress(12) => \maddress[12]\, - maddress(11) => \maddress[11]\, maddress(10) => - \maddress[10]\, maddress(9) => \maddress[9]\, maddress(8) - => \maddress[8]\, maddress(7) => \maddress[7]\, - maddress(6) => \maddress[6]\, maddress(5) => - \maddress[5]\, maddress(4) => \maddress[4]\, maddress(3) - => \maddress[3]\, maddress(2) => \maddress[2]\, - maddress(1) => \maddress[1]\, maddress(0) => - \maddress[0]\, un1_p0_6(0) => \un1_p0_6[0]\, - dataout_0(35) => dataout_0(35), dataout_0(34) => - dataout_0(34), dataout_0(33) => dataout_0(33), - dataout_0(32) => dataout_0(32), dataout_0(31) => - dataout_0(31), dataout_0(30) => dataout_0(30), - dataout_0(29) => dataout_0(29), dataout_0(28) => - dataout_0(28), dataout_0(27) => dataout_0(27), - dataout_0(26) => dataout_0(26), dataout_0(25) => - dataout_0(25), dataout_0(24) => dataout_0(24), - dataout_0(23) => dataout_0(23), dataout_0(22) => - dataout_0(22), dataout_0(21) => dataout_0(21), - dataout_0(20) => dataout_0(20), dataout_0(19) => - dataout_0(19), dataout_0(18) => dataout_0(18), - dataout_0(17) => dataout_0(17), dataout_0(16) => - dataout_0(16), dataout_0(15) => dataout_0(15), - dataout_0(14) => dataout_0(14), dataout_0(13) => - dataout_0(13), dataout_0(12) => dataout_0(12), - dataout_0(11) => dataout_0(11), dataout_0(10) => - dataout_0(10), dataout_0(9) => dataout_0(9), dataout_0(8) - => dataout_0(8), dataout_0(7) => dataout_0(7), - dataout_0(6) => dataout_0(6), dataout_0(5) => - dataout_0(5), dataout_0(4) => dataout_0(4), dataout_0(3) - => dataout_0(3), dataout_0(2) => dataout_0(2), - dataout_0(1) => dataout_0(1), dataout_0(0) => - dataout_0(0), dataout_1(31) => dataout_1(31), - dataout_1(30) => dataout_1(30), dataout_1(29) => - dataout_1(29), dataout_1(28) => dataout_1(28), - dataout_1(27) => dataout_1(27), dataout_1(26) => - dataout_1(26), dataout_1(25) => dataout_1(25), - dataout_1(24) => dataout_1(24), dataout_1(23) => - dataout_1(23), dataout_1(22) => dataout_1(22), - dataout_1(21) => dataout_1(21), dataout_1(20) => - dataout_1(20), dataout_1(19) => dataout_1(19), - dataout_1(18) => dataout_1(18), dataout_1(17) => - dataout_1(17), dataout_1(16) => dataout_1(16), - dataout_1(15) => dataout_1(15), dataout_1(14) => - dataout_1(14), dataout_1(13) => dataout_1(13), - dataout_1(12) => dataout_1(12), dataout_1(11) => - dataout_1(11), dataout_1(10) => dataout_1(10), - dataout_1(9) => dataout_1(9), dataout_1(8) => - dataout_1(8), dataout_1(7) => dataout_1(7), dataout_1(6) - => dataout_1(6), dataout_1(5) => dataout_1(5), - dataout_1(4) => dataout_1(4), dataout_1(3) => - dataout_1(3), dataout_1(2) => dataout_1(2), dataout_1(1) - => dataout_1(1), dataout_1(0) => dataout_1(0), - vitdatain_0_1_0(22) => vitdatain_0_1_0(22), - vaddress_RNIUFAKMI(15) => vaddress_RNIUFAKMI(15), - istate_RNIA8N5H(0) => istate_RNIA8N5H(0), hrdata_0_15 => - hrdata_0_15, hrdata_0_0 => hrdata_0_0, hrdata_0_26 => - hrdata_0_26, hrdata_0_2 => hrdata_0_2, hrdata_0_1 => - hrdata_0_1, hrdata_0_7 => hrdata_0_7, hrdata_0_10 => - hrdata_0_10, hrdata_0_11 => hrdata_0_11, hrdata_0_12 => - hrdata_0_12, hrdata_0_27 => hrdata_0_27, hrdata_0_21 => - hrdata_0_21, hrdata_0_8 => hrdata_0_8, hrdata_0_9 => - hrdata_0_9, hrdata_0_13 => hrdata_0_13, hrdata_0_14 => - hrdata_0_14, hrdata_0_22 => hrdata_0_22, hrdata_0_23 => - hrdata_0_23, hrdata_0_16 => hrdata_0_16, hrdata_0_17 => - hrdata_0_17, hrdata_0_18 => hrdata_0_18, hrdata_0_4 => - hrdata_0_4, hrdata_0_24 => hrdata_0_24, hrdata_0_3 => - hrdata_0_3, data_0(31) => \data_0[31]\, data_0(30) => - \data_0[30]\, data_0(29) => \data_0[29]\, data_0(28) => - \data_0[28]\, data_0(27) => \data_0[27]\, data_0(26) => - \data_0[26]\, data_0(25) => \data_0[25]\, data_0(24) => - \data_0[24]\, data_0(23) => \data_0[23]\, data_0(22) => - \data_0[22]\, data_0(21) => \data_0[21]\, data_0(20) => - \data_0_0[20]\, data_0(19) => \data_0[19]\, data_0(18) - => \data_0[18]\, data_0(17) => \data_0_0[17]\, - data_0(16) => \data_0_0[16]\, data_0(15) => - \data_0_0[15]\, data_0(14) => \data_0_0[14]\, data_0(13) - => \data_0_0[13]\, data_0(12) => \data_0[12]\, - data_0(11) => \data_0_0[11]\, data_0(10) => \data_0[10]\, - data_0(9) => \data_0[9]\, data_0(8) => \data_0[8]\, - data_0(7) => \data_0[7]\, data_0(6) => \data_0[6]\, - data_0(5) => \data_0[5]\, data_0(4) => \data_0[4]\, - data_0(3) => \data_0[3]\, data_0(2) => \data_0[2]\, - data_0(1) => \data_0[1]\, data_0(0) => \data_0[0]\, rpc_0 - => \rpc[2]\, rpc_1 => \rpc[3]\, rpc_3 => \rpc[5]\, rpc_2 - => \rpc[4]\, rpc_7 => \rpc[9]\, rpc_8 => \rpc[10]\, - rpc_5 => \rpc[7]\, rpc_6 => \rpc[8]\, - vaddress_RNI8EVQ36(2) => vaddress_RNI8EVQ36(2), hrdata_9 - => hrdata_9, hrdata_10 => hrdata_10, hrdata_11 => - hrdata_11, hrdata_13 => hrdata_13, hrdata_14 => hrdata_14, - hrdata_17 => hrdata_17, hrdata_24 => hrdata_24, - hrdata_0_d0 => hrdata_0_d0, hrdata_1 => hrdata_1, - hrdata_8 => hrdata_8, hrdata_12 => hrdata_12, hrdata_15 - => hrdata_15, hrdata_16 => hrdata_16, hrdata_18 => - hrdata_18, hrdata_21 => hrdata_21, hrdata_22 => hrdata_22, - hrdata_23 => hrdata_23, hrdata_26 => hrdata_26, hrdata_27 - => hrdata_27, hrdata_2 => hrdata_2, hrdata_3 => hrdata_3, - hrdata_4 => hrdata_4, hrdata_7 => hrdata_7, hrdata_5 => - hrdata_5, hrdata_6 => hrdata_6, hrdata_28 => hrdata_28, - hrdata_29 => hrdata_29, hrdata_30 => hrdata_30, hrdata_31 - => hrdata_31, istate_RNIPSU8G(0) => istate_RNIPSU8G(0), - maddress_0_0 => \maddress_0[1]\, maddress_0_2 => - \maddress_0[3]\, istate_RNIEC82C(0) => istate_RNIEC82C(0), - istate_RNI7BUID(0) => istate_RNI7BUID(0), - istate_RNIV33V9(0) => istate_RNIV33V9(0), - istate_RNI6LOO6(0) => istate_RNI6LOO6(0), - istate_RNIKJBN8(0) => istate_RNIKJBN8(0), - istate_RNIN6957(0) => istate_RNIN6957(0), - istate_RNIOJJE1(0) => istate_RNIOJJE1(0), - istate_RNIR2JU8(0) => istate_RNIR2JU8(0), - istate_RNIJSOBE(0) => istate_RNIJSOBE(0), - istate_RNIRASC8(0) => istate_RNIRASC8(0), - istate_RNIS4VK8(0) => istate_RNIS4VK8(0), - istate_RNIENB3M(0) => istate_RNIENB3M(0), - istate_RNIAP6PI(0) => istate_RNIAP6PI(0), - vaddress_RNIQFAKMI(13) => vaddress_RNIQFAKMI(13), - istate_RNIMRTH8(0) => istate_RNIMRTH8(0), - istate_RNIGUTA8(0) => istate_RNIGUTA8(0), - istate_RNI6PSS1(0) => istate_RNI6PSS1(0), - istate_RNIOVC5J(0) => istate_RNIOVC5J(0), - istate_RNIVTQIJ(0) => istate_RNIVTQIJ(0), - istate_RNIM2DE7(0) => istate_RNIM2DE7(0), - istate_RNI5V68H(0) => istate_RNI5V68H(0), - vaddress_RNI2GAKMI(17) => vaddress_RNI2GAKMI(17), - vaddress_RNI4GAKMI(18) => vaddress_RNI4GAKMI(18), - istate_RNIK9NF8(0) => istate_RNIK9NF8(0), - istate_RNILTAC8(0) => istate_RNILTAC8(0), - istate_RNI8BL1A(0) => istate_RNI8BL1A(0), - istate_RNI2MM6D(0) => istate_RNI2MM6D(0), - vaddress_RNIFCB8U6(3) => vaddress_RNIFCB8U6(3), - istate_RNIG7IIA(0) => istate_RNIG7IIA(0), - istate_RNIH0NBI(0) => istate_RNIH0NBI(0), - faddr_RNI7H6KT8(0) => faddr_RNI7H6KT8(0), - istate_RNIUCOFG(0) => istate_RNIUCOFG(0), - istate_RNI57KLB(0) => istate_RNI57KLB(0), - vaddress_RNISFAKMI(14) => vaddress_RNISFAKMI(14), - vaddress_RNIUNAKMI(22) => vaddress_RNIUNAKMI(22), - istate_RNIAJH4F(0) => istate_RNIAJH4F(0), - istate_RNI6HPAI(0) => istate_RNI6HPAI(0), ctx(7) => - ctx(7), ctx(6) => ctx(6), ctx(5) => ctx(5), ctx(4) => - ctx(4), ctx(3) => ctx(3), ctx(2) => ctx(2), ctx(1) => - ctx(1), ctx(0) => ctx(0), un1_p0_2_i_0 => un1_p0_2_i_0, - un1_p0_2_i_4 => un1_p0_2_i_4, vaddress_RNIJG6QR7(4) => - vaddress_RNIJG6QR7(4), vaddress_RNIOFAKMI(12) => - vaddress_RNIOFAKMI(12), vaddress_RNI0OAKMI(23) => - vaddress_RNI0OAKMI(23), vaddress_RNI0GAKMI(16) => - vaddress_RNI0GAKMI(16), faddr_RNIKVTLT9(1) => - faddr_RNIKVTLT9(1), faddr_RNIDN2CUE(6) => - faddr_RNIDN2CUE(6), faddr_RNI0FOJNE(4) => - faddr_RNI0FOJNE(4), faddr_RNI7UFASD(5) => - faddr_RNI7UFASD(5), vaddress_RNIQNAKMI(20) => - vaddress_RNIQNAKMI(20), faddr_RNISJSHQA(2) => - faddr_RNISJSHQA(2), vaddress_RNI6GAKMI(19) => - vaddress_RNI6GAKMI(19), vaddress_RNISNAKMI(21) => - vaddress_RNISNAKMI(21), faddr_RNIUT72LB(3) => - faddr_RNIUT72LB(3), istate_RNIJCMP6(0) => - istate_RNIJCMP6(0), N_546 => N_546, mmu_cache_VCC => - proc3_VCC, N_264 => N_264, N_262 => N_262, N_78 => N_78, - bo_5842_d_0 => bo_5842_d_0, un1_htrans_1_sqmuxa_0 => - un1_htrans_1_sqmuxa_0, hlock => hlock, N_5054 => N_5054, - lb_0_sqmuxa_1 => lb_0_sqmuxa_1, hbusreq => hbusreq, - un60_nbo => un60_nbo, N_457 => N_457, N_462 => N_462, - N_467 => N_467, werr_2_m_0 => werr_2_m_0, un91_nbo_i_0 - => un91_nbo_i_0, N_138 => N_138, N_139 => N_139, - bo_5842_d => bo_5842_d, N_458 => N_458, N_459 => N_459, - N_461 => N_461, N_463 => N_463, N_468 => N_468, - hwrite_1_m_0 => hwrite_1_m_0, N_466 => N_466, - htrans_0_sqmuxa_2 => htrans_0_sqmuxa_2, werr => werr, - N_3254_0 => N_3254_0, enaddr => enaddr, lock_0 => lock, - vaddr_1_sqmuxa_0_a2_4_m1_e_24 => - vaddr_1_sqmuxa_0_a2_4_m1_e_24, un1_addout_12 => - un1_addout_12, read_0_0 => read_0, nullify => nullify, - intack => \intack\, nullify2_0_sqmuxa => - nullify2_0_sqmuxa, me_nullify2_1_2 => me_nullify2_1_2, - un17_casaen_0_0 => un17_casaen_0_0, N_330 => N_330, N_329 - => N_329, N_24 => N_24, flush_0_1_RNIPTA27S2 => - flush_0_1_RNIPTA27S2, flush_0_1_RNIBUA27S2 => - flush_0_1_RNIBUA27S2, N_16_i_0 => N_16_i_0, N_12_i_0 => - N_12_i_0, read_RNIEEGDD1 => read_RNIEEGDD1, - read_RNI75LJ31 => read_RNI75LJ31, read_RNIC70OF1 => - read_RNIC70OF1, read_RNISLPNU => read_RNISLPNU, - read_RNIQMJI41 => read_RNIQMJI41, read_RNICAQK41 => - read_RNICAQK41, flush_RNIGUM2OH3 => flush_RNIGUM2OH3, - read_RNIC9O9B1 => read_RNIC9O9B1, read_RNIFPFT31 => - read_RNIFPFT31, read_RNIEKS231 => read_RNIEKS231, N_26_0 - => N_26_0, N_3387_i_0 => N_3387_i_0, N_3227_i_0 => - N_3227_i_0, N_3239_i_0 => N_3239_i_0, mexc_1 => mexc_0, - un59_nbo => un59_nbo, flush_0_1_RNIOMB27S2 => - flush_0_1_RNIOMB27S2, read_RNICKHE91 => read_RNICKHE91, - read_RNIL633F1 => read_RNIL633F1, read_RNIMJHQT => - read_RNIMJHQT, read_RNI7G7G41 => read_RNI7G7G41, - read_RNI76N8R => read_RNI76N8R, read_RNIAQJ831 => - read_RNIAQJ831, read_RNI8DFM31 => read_RNI8DFM31, - read_RNIQFOD21 => read_RNIQFOD21, read_RNI0IQ7R => - read_RNI0IQ7R, N_3389_i_0 => N_3389_i_0, read_RNIRO4K31 - => read_RNIRO4K31, read_RNIQPCQ11 => read_RNIQPCQ11, - read_RNIQH64D1 => read_RNIQH64D1, read_1 => read, r_N_6 - => r_N_6, N_3305 => N_3305, N_3846 => N_3846, N_144 => - N_144, N_258 => N_258, N_259 => N_259, N_267 => N_267, - N_269 => N_269, N_270 => N_270, flush_RNIGBB873 => - flush_RNIGBB873, flush_RNIJEN4SI3 => flush_RNIJEN4SI3, - msu => msu, eenaddr => eenaddr, write => write, N_10 => - N_10, lclk_c => lclk_c, holdn => holdn, rst => rst, - flush_i_0 => flush_i_0, hold_pc_7 => hold_pc_7, - de_hold_pc_1 => de_hold_pc_1, un1_ici => un1_ici, - xc_exception_1_0 => xc_exception_1_0, ldlock_2 => - ldlock_2, un9_icc_check_bp => un9_icc_check_bp, - ldlock_3_0 => ldlock_3_0, inull => inull, N_78_0 => - N_78_0, N_262_0 => N_262_0, N_264_0 => N_264_0, N_982 => - N_982, N_983 => N_983, N_985 => N_985, N_981 => N_981, - mds => mds, flush2_0_0_RNIPJ5O2 => flush2_0_0_RNIPJ5O2, - flush2_0_0_RNITR5O2 => flush2_0_0_RNITR5O2, - flush2_0_0_RNIVV5O2 => flush2_0_0_RNIVV5O2, - flush2_0_0_RNI7G6O2 => flush2_0_0_RNI7G6O2, - flush2_0_0_RNI146O2 => flush2_0_0_RNI146O2, N_26 => N_26, - flush2 => flush2, N_986 => N_986, N_987 => N_987, N_28 - => N_28, N_980 => N_980, N_984 => N_984, flush2_RNI5I3N7 - => flush2_RNI5I3N7, flush2_RNIFMGM2 => flush2_RNIFMGM2, - rbranch => rbranch, fbranch => fbranch, mexc => mexc, su - => su); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 is - - port( rclk : in std_logic; - rena : in std_logic; - raddr : in std_logic_vector(7 downto 0); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic; - waddr : in std_logic_vector(7 downto 0); - din : in std_logic_vector(31 downto 0); - write : in std_logic - ); - -end proasic3_syncram_2p_work_leon3mp_wfp_rtl_1; - -architecture DEF_ARCH of - proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ0_1 is - - port( wdata : in std_logic_vector(31 downto 0); - waddr_0 : in std_logic_vector(7 downto 0); - raddr2 : in std_logic_vector(7 downto 0); - datain : in std_logic_vector(31 downto 0); - data2 : out std_logic_vector(31 downto 0); - waddr : in std_logic_vector(7 downto 0); - rfa2 : in std_logic_vector(7 downto 0); - wren : in std_logic; - ren2 : in std_logic; - lclk_c : in std_logic; - rfe2 : in std_logic; - write : in std_logic - ); - -end syncram_2pZ0_1; - -architecture DEF_ARCH of syncram_2pZ0_1 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - port( rclk : in std_logic := 'U'; - rena : in std_logic := 'U'; - raddr : in std_logic_vector(7 downto 0) := (others => 'U'); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic := 'U'; - waddr : in std_logic_vector(7 downto 0) := (others => 'U'); - din : in std_logic_vector(31 downto 0) := (others => 'U'); - write : in std_logic := 'U' - ); - end component; - - signal un4_scantestbp_0, un4_scantestbp_3, un4_scantestbp_2, - un4_scantestbp_7, un4_scantestbp_1, un5_scantestbp_7_0, - un4_scantestbp_4, un5_scantestbp_6_i_0, - un5_scantestbp_4_i_0, un5_scantestbp_2_i_0, - un5_scantestbp_0_i_0, un4_scantestbp, \dataoutx[1]\, - \dataoutx[2]\, \dataoutx[3]\, \dataoutx[25]\, - \dataoutx[26]\, \dataoutx[27]\, \dataoutx[28]\, - \dataoutx[29]\, \dataoutx[30]\, \dataoutx[31]\, - \dataoutx[18]\, \dataoutx[19]\, \dataoutx[20]\, - \dataoutx[21]\, \dataoutx[22]\, \dataoutx[23]\, - \dataoutx[24]\, \dataoutx[11]\, \dataoutx[12]\, - \dataoutx[13]\, \dataoutx[14]\, \dataoutx[15]\, - \dataoutx[16]\, \dataoutx[17]\, \dataoutx[4]\, - \dataoutx[5]\, \dataoutx[6]\, \dataoutx[7]\, - \dataoutx[8]\, \dataoutx[9]\, \dataoutx[10]\, - \dataoutx[0]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - Use entity work. - proasic3_syncram_2p_work_leon3mp_wfp_rtl_1(DEF_ARCH); -begin - - - \proa3.x0_RNI49JG2\ : MX2 - port map(A => \dataoutx[24]\, B => datain(24), S => - un4_scantestbp, Y => data2(24)); - - \proa3.x0_RNI25JG2\ : MX2 - port map(A => \dataoutx[15]\, B => datain(15), S => - un4_scantestbp, Y => data2(15)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_2\ : - XA1A - port map(A => rfa2(1), B => waddr(1), C => - un5_scantestbp_2_i_0, Y => un4_scantestbp_2); - - \proa3.x0_RNI89JG2\ : MX2 - port map(A => \dataoutx[28]\, B => datain(28), S => - un4_scantestbp_0, Y => data2(28)); - - \proa3.x0_RNI45JG2\ : MX2 - port map(A => \dataoutx[17]\, B => datain(17), S => - un4_scantestbp, Y => data2(17)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_1\ : - NOR3C - port map(A => write, B => rfe2, C => un5_scantestbp_0_i_0, - Y => un4_scantestbp_1); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_4_0\ : - XNOR2 - port map(A => waddr(4), B => rfa2(4), Y => - un5_scantestbp_4_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_3\ : - XA1A - port map(A => rfa2(3), B => waddr(3), C => - un5_scantestbp_4_i_0, Y => un4_scantestbp_3); - - \proa3.x0_RNIT4JG2\ : MX2 - port map(A => \dataoutx[10]\, B => datain(10), S => - un4_scantestbp, Y => data2(10)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_0_0\ : - XNOR2 - port map(A => waddr(0), B => rfa2(0), Y => - un5_scantestbp_0_i_0); - - \proa3.x0_RNIV4JG2\ : MX2 - port map(A => \dataoutx[12]\, B => datain(12), S => - un4_scantestbp, Y => data2(12)); - - \proa3.x0_RNI79JG2\ : MX2 - port map(A => \dataoutx[27]\, B => datain(27), S => - un4_scantestbp_0, Y => data2(27)); - - \proa3.x0_RNI3DJG2\ : MX2 - port map(A => \dataoutx[30]\, B => datain(30), S => - un4_scantestbp_0, Y => data2(30)); - - \proa3.x0_RNI99JG2\ : MX2 - port map(A => \dataoutx[29]\, B => datain(29), S => - un4_scantestbp_0, Y => data2(29)); - - \proa3.x0_RNI39JG2\ : MX2 - port map(A => \dataoutx[23]\, B => datain(23), S => - un4_scantestbp_0, Y => data2(23)); - - \proa3.x0_RNIU4JG2\ : MX2 - port map(A => \dataoutx[11]\, B => datain(11), S => - un4_scantestbp, Y => data2(11)); - - \proa3.x0_RNIEQ5J2\ : MX2 - port map(A => \dataoutx[0]\, B => datain(0), S => - un4_scantestbp, Y => data2(0)); - - \proa3.x0_RNI35JG2\ : MX2 - port map(A => \dataoutx[16]\, B => datain(16), S => - un4_scantestbp, Y => data2(16)); - - GND_i : GND - port map(Y => \GND\); - - \proa3.x0_RNI69JG2\ : MX2 - port map(A => \dataoutx[26]\, B => datain(26), S => - un4_scantestbp_0, Y => data2(26)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_6_0\ : - XNOR2 - port map(A => waddr(6), B => rfa2(6), Y => - un5_scantestbp_6_i_0); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_0\ : - NOR3C - port map(A => un4_scantestbp_3, B => un4_scantestbp_2, C - => un4_scantestbp_7, Y => un4_scantestbp_0); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_4\ : - XA1A - port map(A => rfa2(5), B => waddr(5), C => - un5_scantestbp_6_i_0, Y => un4_scantestbp_4); - - \proa3.x0_RNIKI6J2\ : MX2 - port map(A => \dataoutx[6]\, B => datain(6), S => - un4_scantestbp, Y => data2(6)); - - \proa3.x0_RNI65JG2\ : MX2 - port map(A => \dataoutx[19]\, B => datain(19), S => - un4_scantestbp_0, Y => data2(19)); - - \proa3.x0_RNIFU5J2\ : MX2 - port map(A => \dataoutx[1]\, B => datain(1), S => - un4_scantestbp_0, Y => data2(1)); - - \proa3.x0_RNIMQ6J2\ : MX2 - port map(A => \dataoutx[8]\, B => datain(8), S => - un4_scantestbp, Y => data2(8)); - - \proa3.x0\ : proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - port map(rclk => lclk_c, rena => ren2, raddr(7) => - raddr2(7), raddr(6) => raddr2(6), raddr(5) => raddr2(5), - raddr(4) => raddr2(4), raddr(3) => raddr2(3), raddr(2) - => raddr2(2), raddr(1) => raddr2(1), raddr(0) => - raddr2(0), dout(31) => \dataoutx[31]\, dout(30) => - \dataoutx[30]\, dout(29) => \dataoutx[29]\, dout(28) => - \dataoutx[28]\, dout(27) => \dataoutx[27]\, dout(26) => - \dataoutx[26]\, dout(25) => \dataoutx[25]\, dout(24) => - \dataoutx[24]\, dout(23) => \dataoutx[23]\, dout(22) => - \dataoutx[22]\, dout(21) => \dataoutx[21]\, dout(20) => - \dataoutx[20]\, dout(19) => \dataoutx[19]\, dout(18) => - \dataoutx[18]\, dout(17) => \dataoutx[17]\, dout(16) => - \dataoutx[16]\, dout(15) => \dataoutx[15]\, dout(14) => - \dataoutx[14]\, dout(13) => \dataoutx[13]\, dout(12) => - \dataoutx[12]\, dout(11) => \dataoutx[11]\, dout(10) => - \dataoutx[10]\, dout(9) => \dataoutx[9]\, dout(8) => - \dataoutx[8]\, dout(7) => \dataoutx[7]\, dout(6) => - \dataoutx[6]\, dout(5) => \dataoutx[5]\, dout(4) => - \dataoutx[4]\, dout(3) => \dataoutx[3]\, dout(2) => - \dataoutx[2]\, dout(1) => \dataoutx[1]\, dout(0) => - \dataoutx[0]\, wclk => lclk_c, waddr(7) => waddr_0(7), - waddr(6) => waddr_0(6), waddr(5) => waddr_0(5), waddr(4) - => waddr_0(4), waddr(3) => waddr_0(3), waddr(2) => - waddr_0(2), waddr(1) => waddr_0(1), waddr(0) => - waddr_0(0), din(31) => wdata(31), din(30) => wdata(30), - din(29) => wdata(29), din(28) => wdata(28), din(27) => - wdata(27), din(26) => wdata(26), din(25) => wdata(25), - din(24) => wdata(24), din(23) => wdata(23), din(22) => - wdata(22), din(21) => wdata(21), din(20) => wdata(20), - din(19) => wdata(19), din(18) => wdata(18), din(17) => - wdata(17), din(16) => wdata(16), din(15) => wdata(15), - din(14) => wdata(14), din(13) => wdata(13), din(12) => - wdata(12), din(11) => wdata(11), din(10) => wdata(10), - din(9) => wdata(9), din(8) => wdata(8), din(7) => - wdata(7), din(6) => wdata(6), din(5) => wdata(5), din(4) - => wdata(4), din(3) => wdata(3), din(2) => wdata(2), - din(1) => wdata(1), din(0) => wdata(0), write => wren); - - \proa3.x0_RNI19JG2\ : MX2 - port map(A => \dataoutx[21]\, B => datain(21), S => - un4_scantestbp_0, Y => data2(21)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp\ : - NOR3C - port map(A => un4_scantestbp_3, B => un4_scantestbp_2, C - => un4_scantestbp_7, Y => un4_scantestbp); - - \proa3.x0_RNIJE6J2\ : MX2 - port map(A => \dataoutx[5]\, B => datain(5), S => - un4_scantestbp, Y => data2(5)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_2_0\ : - XNOR2 - port map(A => waddr(2), B => rfa2(2), Y => - un5_scantestbp_2_i_0); - - \proa3.x0_RNI15JG2\ : MX2 - port map(A => \dataoutx[14]\, B => datain(14), S => - un4_scantestbp, Y => data2(14)); - - \proa3.x0_RNIG26J2\ : MX2 - port map(A => \dataoutx[2]\, B => datain(2), S => - un4_scantestbp_0, Y => data2(2)); - - \proa3.x0_RNI09JG2\ : MX2 - port map(A => \dataoutx[20]\, B => datain(20), S => - un4_scantestbp_0, Y => data2(20)); - - \proa3.x0_RNINU6J2\ : MX2 - port map(A => \dataoutx[9]\, B => datain(9), S => - un4_scantestbp, Y => data2(9)); - - \proa3.x0_RNIIA6J2\ : MX2 - port map(A => \dataoutx[4]\, B => datain(4), S => - un4_scantestbp, Y => data2(4)); - - \proa3.x0_RNI59JG2\ : MX2 - port map(A => \dataoutx[25]\, B => datain(25), S => - un4_scantestbp_0, Y => data2(25)); - - \proa3.x0_RNI05JG2\ : MX2 - port map(A => \dataoutx[13]\, B => datain(13), S => - un4_scantestbp, Y => data2(13)); - - \proa3.x0_RNILM6J2\ : MX2 - port map(A => \dataoutx[7]\, B => datain(7), S => - un4_scantestbp, Y => data2(7)); - - \proa3.x0_RNI4DJG2\ : MX2 - port map(A => \dataoutx[31]\, B => datain(31), S => - un4_scantestbp_0, Y => data2(31)); - - \proa3.x0_RNIH66J2\ : MX2 - port map(A => \dataoutx[3]\, B => datain(3), S => - un4_scantestbp_0, Y => data2(3)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_7_0\ : - XNOR2 - port map(A => waddr(7), B => rfa2(7), Y => - un5_scantestbp_7_0); - - \proa3.x0_RNI55JG2\ : MX2 - port map(A => \dataoutx[18]\, B => datain(18), S => - un4_scantestbp_0, Y => data2(18)); - - \proa3.x0_RNI29JG2\ : MX2 - port map(A => \dataoutx[22]\, B => datain(22), S => - un4_scantestbp_0, Y => data2(22)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_7\ : - NOR3C - port map(A => un4_scantestbp_1, B => un5_scantestbp_7_0, C - => un4_scantestbp_4, Y => un4_scantestbp_7); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ0 is - - port( raddr1 : in std_logic_vector(7 downto 0); - wdata : in std_logic_vector(31 downto 0); - waddr_0 : in std_logic_vector(7 downto 0); - datain : out std_logic_vector(31 downto 0); - data1 : out std_logic_vector(31 downto 0); - waddr : out std_logic_vector(7 downto 0); - rfa1 : in std_logic_vector(7 downto 0); - ren1 : in std_logic; - wren : in std_logic; - lclk_c : in std_logic; - rfe1 : in std_logic; - write : out std_logic - ); - -end syncram_2pZ0; - -architecture DEF_ARCH of syncram_2pZ0 is - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - port( rclk : in std_logic := 'U'; - rena : in std_logic := 'U'; - raddr : in std_logic_vector(7 downto 0) := (others => 'U'); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic := 'U'; - waddr : in std_logic_vector(7 downto 0) := (others => 'U'); - din : in std_logic_vector(31 downto 0) := (others => 'U'); - write : in std_logic := 'U' - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un4_scantestbp_0, un4_scantestbp_3, un4_scantestbp_2, - un4_scantestbp_7, un4_scantestbp_1, un5_scantestbp_7_i_0, - un4_scantestbp_4, un5_scantestbp_6_i_0, - un5_scantestbp_4_i_0, un5_scantestbp_2_i_0, - un5_scantestbp_0_i_0, un4_scantestbp, \dataoutx[0]\, - \dataoutx[1]\, \dataoutx[3]\, \dataoutx[25]\, - \dataoutx[26]\, \dataoutx[27]\, \dataoutx[28]\, - \dataoutx[29]\, \dataoutx[30]\, \dataoutx[19]\, - \dataoutx[21]\, \dataoutx[22]\, \dataoutx[23]\, - \dataoutx[24]\, \dataoutx[11]\, \dataoutx[12]\, - \dataoutx[13]\, \dataoutx[14]\, \dataoutx[15]\, - \dataoutx[16]\, \dataoutx[17]\, \dataoutx[4]\, - \dataoutx[5]\, \dataoutx[6]\, \dataoutx[7]\, - \dataoutx[8]\, \dataoutx[9]\, \dataoutx[10]\, - \dataoutx[2]\, \dataoutx[20]\, \dataoutx[31]\, - \dataoutx[18]\, \write\, \waddr[0]\, \waddr[1]\, - \waddr[2]\, \waddr[3]\, \waddr[4]\, \waddr[5]\, - \waddr[6]\, \waddr[7]\, \datain[0]\, \datain[1]\, - \datain[2]\, \datain[3]\, \datain[4]\, \datain[5]\, - \datain[6]\, \datain[7]\, \datain[8]\, \datain[9]\, - \datain[10]\, \datain[11]\, \datain[12]\, \datain[13]\, - \datain[14]\, \datain[15]\, \datain[16]\, \datain[17]\, - \datain[18]\, \datain[19]\, \datain[20]\, \datain[21]\, - \datain[22]\, \datain[23]\, \datain[24]\, \datain[25]\, - \datain[26]\, \datain[27]\, \datain[28]\, \datain[29]\, - \datain[30]\, \datain[31]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - Use entity work. - proasic3_syncram_2p_work_leon3mp_wfp_rtl_1(DEF_ARCH); -begin - - datain(31) <= \datain[31]\; - datain(30) <= \datain[30]\; - datain(29) <= \datain[29]\; - datain(28) <= \datain[28]\; - datain(27) <= \datain[27]\; - datain(26) <= \datain[26]\; - datain(25) <= \datain[25]\; - datain(24) <= \datain[24]\; - datain(23) <= \datain[23]\; - datain(22) <= \datain[22]\; - datain(21) <= \datain[21]\; - datain(20) <= \datain[20]\; - datain(19) <= \datain[19]\; - datain(18) <= \datain[18]\; - datain(17) <= \datain[17]\; - datain(16) <= \datain[16]\; - datain(15) <= \datain[15]\; - datain(14) <= \datain[14]\; - datain(13) <= \datain[13]\; - datain(12) <= \datain[12]\; - datain(11) <= \datain[11]\; - datain(10) <= \datain[10]\; - datain(9) <= \datain[9]\; - datain(8) <= \datain[8]\; - datain(7) <= \datain[7]\; - datain(6) <= \datain[6]\; - datain(5) <= \datain[5]\; - datain(4) <= \datain[4]\; - datain(3) <= \datain[3]\; - datain(2) <= \datain[2]\; - datain(1) <= \datain[1]\; - datain(0) <= \datain[0]\; - waddr(7) <= \waddr[7]\; - waddr(6) <= \waddr[6]\; - waddr(5) <= \waddr[5]\; - waddr(4) <= \waddr[4]\; - waddr(3) <= \waddr[3]\; - waddr(2) <= \waddr[2]\; - waddr(1) <= \waddr[1]\; - waddr(0) <= \waddr[0]\; - write <= \write\; - - \wrfst_gen.no_contention_check.r.waddr_RNIEBBH[1]\ : XA1A - port map(A => rfa1(1), B => \waddr[1]\, C => - un5_scantestbp_2_i_0, Y => un4_scantestbp_2); - - \wrfst_gen.no_contention_check.r.datain[23]\ : DFN1 - port map(D => wdata(23), CLK => lclk_c, Q => \datain[23]\); - - \wrfst_gen.no_contention_check.r.waddr_RNI08M8[6]\ : XNOR2 - port map(A => \waddr[6]\, B => rfa1(6), Y => - un5_scantestbp_6_i_0); - - \wrfst_gen.no_contention_check.r.datain[26]\ : DFN1 - port map(D => wdata(26), CLK => lclk_c, Q => \datain[26]\); - - \wrfst_gen.no_contention_check.r.waddr_RNIDAN82[1]\ : NOR3C - port map(A => un4_scantestbp_3, B => un4_scantestbp_2, C - => un4_scantestbp_7, Y => un4_scantestbp); - - \proa3.x0_RNI74FG2\ : MX2 - port map(A => \dataoutx[14]\, B => \datain[14]\, S => - un4_scantestbp, Y => data1(14)); - - \proa3.x0_RNI68FG2\ : MX2 - port map(A => \dataoutx[20]\, B => \datain[20]\, S => - un4_scantestbp, Y => data1(20)); - - \wrfst_gen.no_contention_check.r.datain[4]\ : DFN1 - port map(D => wdata(4), CLK => lclk_c, Q => \datain[4]\); - - \wrfst_gen.no_contention_check.r.datain[27]\ : DFN1 - port map(D => wdata(27), CLK => lclk_c, Q => \datain[27]\); - - \wrfst_gen.no_contention_check.r.write\ : DFN1 - port map(D => wren, CLK => lclk_c, Q => \write\); - - \wrfst_gen.no_contention_check.r.datain[13]\ : DFN1 - port map(D => wdata(13), CLK => lclk_c, Q => \datain[13]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \wrfst_gen.no_contention_check.r.waddr_RNI2CM8[7]\ : XNOR2 - port map(A => \waddr[7]\, B => rfa1(7), Y => - un5_scantestbp_7_i_0); - - \wrfst_gen.no_contention_check.r.datain[16]\ : DFN1 - port map(D => wdata(16), CLK => lclk_c, Q => \datain[16]\); - - \proa3.x0_RNI94FG2\ : MX2 - port map(A => \dataoutx[16]\, B => \datain[16]\, S => - un4_scantestbp, Y => data1(16)); - - \proa3.x0_RNIF8FG2\ : MX2 - port map(A => \dataoutx[29]\, B => \datain[29]\, S => - un4_scantestbp_0, Y => data1(29)); - - \proa3.x0_RNI84FG2\ : MX2 - port map(A => \dataoutx[15]\, B => \datain[15]\, S => - un4_scantestbp, Y => data1(15)); - - \wrfst_gen.no_contention_check.r.waddr[6]\ : DFN1 - port map(D => waddr_0(6), CLK => lclk_c, Q => \waddr[6]\); - - \proa3.x0_RNID8FG2\ : MX2 - port map(A => \dataoutx[27]\, B => \datain[27]\, S => - un4_scantestbp_0, Y => data1(27)); - - \wrfst_gen.no_contention_check.r.datain[8]\ : DFN1 - port map(D => wdata(8), CLK => lclk_c, Q => \datain[8]\); - - \wrfst_gen.no_contention_check.r.datain[25]\ : DFN1 - port map(D => wdata(25), CLK => lclk_c, Q => \datain[25]\); - - \wrfst_gen.no_contention_check.r.waddr[5]\ : DFN1 - port map(D => waddr_0(5), CLK => lclk_c, Q => \waddr[5]\); - - \wrfst_gen.no_contention_check.r.datain[17]\ : DFN1 - port map(D => wdata(17), CLK => lclk_c, Q => \datain[17]\); - - \wrfst_gen.no_contention_check.r.waddr[3]\ : DFN1 - port map(D => waddr_0(3), CLK => lclk_c, Q => \waddr[3]\); - - \wrfst_gen.no_contention_check.r.waddr_RNIONL8[2]\ : XNOR2 - port map(A => \waddr[2]\, B => rfa1(2), Y => - un5_scantestbp_2_i_0); - - \proa3.x0_RNISP2J2\ : MX2 - port map(A => \dataoutx[8]\, B => \datain[8]\, S => - un4_scantestbp, Y => data1(8)); - - \proa3.x0_RNIA8FG2\ : MX2 - port map(A => \dataoutx[24]\, B => \datain[24]\, S => - un4_scantestbp_0, Y => data1(24)); - - \wrfst_gen.no_contention_check.r.waddr_RNIUBCH[5]\ : XA1A - port map(A => rfa1(5), B => \waddr[5]\, C => - un5_scantestbp_6_i_0, Y => un4_scantestbp_4); - - \wrfst_gen.no_contention_check.r.datain[2]\ : DFN1 - port map(D => wdata(2), CLK => lclk_c, Q => \datain[2]\); - - \wrfst_gen.no_contention_check.r.datain[22]\ : DFN1 - port map(D => wdata(22), CLK => lclk_c, Q => \datain[22]\); - - \wrfst_gen.no_contention_check.r.waddr[4]\ : DFN1 - port map(D => waddr_0(4), CLK => lclk_c, Q => \waddr[4]\); - - \wrfst_gen.no_contention_check.r.datain[31]\ : DFN1 - port map(D => wdata(31), CLK => lclk_c, Q => \datain[31]\); - - \wrfst_gen.no_contention_check.r.datain[30]\ : DFN1 - port map(D => wdata(30), CLK => lclk_c, Q => \datain[30]\); - - \wrfst_gen.no_contention_check.r.datain[7]\ : DFN1 - port map(D => wdata(7), CLK => lclk_c, Q => \datain[7]\); - - \proa3.x0_RNI64FG2\ : MX2 - port map(A => \dataoutx[13]\, B => \datain[13]\, S => - un4_scantestbp, Y => data1(13)); - - \wrfst_gen.no_contention_check.r.waddr[2]\ : DFN1 - port map(D => waddr_0(2), CLK => lclk_c, Q => \waddr[2]\); - - \wrfst_gen.no_contention_check.r.datain[24]\ : DFN1 - port map(D => wdata(24), CLK => lclk_c, Q => \datain[24]\); - - \wrfst_gen.no_contention_check.r.datain[28]\ : DFN1 - port map(D => wdata(28), CLK => lclk_c, Q => \datain[28]\); - - \wrfst_gen.no_contention_check.r.datain[15]\ : DFN1 - port map(D => wdata(15), CLK => lclk_c, Q => \datain[15]\); - - \wrfst_gen.no_contention_check.r.waddr_RNIMRBH[3]\ : XA1A - port map(A => rfa1(3), B => \waddr[3]\, C => - un5_scantestbp_4_i_0, Y => un4_scantestbp_3); - - \wrfst_gen.no_contention_check.r.datain[3]\ : DFN1 - port map(D => wdata(3), CLK => lclk_c, Q => \datain[3]\); - - \proa3.x0_RNI9CFG2\ : MX2 - port map(A => \dataoutx[30]\, B => \datain[30]\, S => - un4_scantestbp_0, Y => data1(30)); - - \proa3.x0_RNI44FG2\ : MX2 - port map(A => \dataoutx[11]\, B => \datain[11]\, S => - un4_scantestbp_0, Y => data1(11)); - - \proa3.x0_RNIQH2J2\ : MX2 - port map(A => \dataoutx[6]\, B => \datain[6]\, S => - un4_scantestbp, Y => data1(6)); - - \proa3.x0_RNIRL2J2\ : MX2 - port map(A => \dataoutx[7]\, B => \datain[7]\, S => - un4_scantestbp, Y => data1(7)); - - GND_i : GND - port map(Y => \GND\); - - \wrfst_gen.no_contention_check.r.datain[12]\ : DFN1 - port map(D => wdata(12), CLK => lclk_c, Q => \datain[12]\); - - \proa3.x0_RNIO92J2\ : MX2 - port map(A => \dataoutx[4]\, B => \datain[4]\, S => - un4_scantestbp, Y => data1(4)); - - \wrfst_gen.no_contention_check.r.write_RNI93061\ : NOR3C - port map(A => un4_scantestbp_1, B => un5_scantestbp_7_i_0, - C => un4_scantestbp_4, Y => un4_scantestbp_7); - - \wrfst_gen.no_contention_check.r.waddr[7]\ : DFN1 - port map(D => waddr_0(7), CLK => lclk_c, Q => \waddr[7]\); - - \wrfst_gen.no_contention_check.r.datain[14]\ : DFN1 - port map(D => wdata(14), CLK => lclk_c, Q => \datain[14]\); - - \proa3.x0_RNIB8FG2\ : MX2 - port map(A => \dataoutx[25]\, B => \datain[25]\, S => - un4_scantestbp_0, Y => data1(25)); - - \wrfst_gen.no_contention_check.r.datain[18]\ : DFN1 - port map(D => wdata(18), CLK => lclk_c, Q => \datain[18]\); - - \wrfst_gen.no_contention_check.r.datain[29]\ : DFN1 - port map(D => wdata(29), CLK => lclk_c, Q => \datain[29]\); - - \proa3.x0_RNILT1J2\ : MX2 - port map(A => \dataoutx[1]\, B => \datain[1]\, S => - un4_scantestbp_0, Y => data1(1)); - - \proa3.x0_RNIA4FG2\ : MX2 - port map(A => \dataoutx[17]\, B => \datain[17]\, S => - un4_scantestbp, Y => data1(17)); - - \proa3.x0_RNIM12J2\ : MX2 - port map(A => \dataoutx[2]\, B => \datain[2]\, S => - un4_scantestbp, Y => data1(2)); - - \proa3.x0\ : proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - port map(rclk => lclk_c, rena => ren1, raddr(7) => - raddr1(7), raddr(6) => raddr1(6), raddr(5) => raddr1(5), - raddr(4) => raddr1(4), raddr(3) => raddr1(3), raddr(2) - => raddr1(2), raddr(1) => raddr1(1), raddr(0) => - raddr1(0), dout(31) => \dataoutx[31]\, dout(30) => - \dataoutx[30]\, dout(29) => \dataoutx[29]\, dout(28) => - \dataoutx[28]\, dout(27) => \dataoutx[27]\, dout(26) => - \dataoutx[26]\, dout(25) => \dataoutx[25]\, dout(24) => - \dataoutx[24]\, dout(23) => \dataoutx[23]\, dout(22) => - \dataoutx[22]\, dout(21) => \dataoutx[21]\, dout(20) => - \dataoutx[20]\, dout(19) => \dataoutx[19]\, dout(18) => - \dataoutx[18]\, dout(17) => \dataoutx[17]\, dout(16) => - \dataoutx[16]\, dout(15) => \dataoutx[15]\, dout(14) => - \dataoutx[14]\, dout(13) => \dataoutx[13]\, dout(12) => - \dataoutx[12]\, dout(11) => \dataoutx[11]\, dout(10) => - \dataoutx[10]\, dout(9) => \dataoutx[9]\, dout(8) => - \dataoutx[8]\, dout(7) => \dataoutx[7]\, dout(6) => - \dataoutx[6]\, dout(5) => \dataoutx[5]\, dout(4) => - \dataoutx[4]\, dout(3) => \dataoutx[3]\, dout(2) => - \dataoutx[2]\, dout(1) => \dataoutx[1]\, dout(0) => - \dataoutx[0]\, wclk => lclk_c, waddr(7) => waddr_0(7), - waddr(6) => waddr_0(6), waddr(5) => waddr_0(5), waddr(4) - => waddr_0(4), waddr(3) => waddr_0(3), waddr(2) => - waddr_0(2), waddr(1) => waddr_0(1), waddr(0) => - waddr_0(0), din(31) => wdata(31), din(30) => wdata(30), - din(29) => wdata(29), din(28) => wdata(28), din(27) => - wdata(27), din(26) => wdata(26), din(25) => wdata(25), - din(24) => wdata(24), din(23) => wdata(23), din(22) => - wdata(22), din(21) => wdata(21), din(20) => wdata(20), - din(19) => wdata(19), din(18) => wdata(18), din(17) => - wdata(17), din(16) => wdata(16), din(15) => wdata(15), - din(14) => wdata(14), din(13) => wdata(13), din(12) => - wdata(12), din(11) => wdata(11), din(10) => wdata(10), - din(9) => wdata(9), din(8) => wdata(8), din(7) => - wdata(7), din(6) => wdata(6), din(5) => wdata(5), din(4) - => wdata(4), din(3) => wdata(3), din(2) => wdata(2), - din(1) => wdata(1), din(0) => wdata(0), write => wren); - - \wrfst_gen.no_contention_check.r.waddr_RNIDAN82_0[1]\ : NOR3C - port map(A => un4_scantestbp_3, B => un4_scantestbp_2, C - => un4_scantestbp_7, Y => un4_scantestbp_0); - - \wrfst_gen.no_contention_check.r.datain[5]\ : DFN1 - port map(D => wdata(5), CLK => lclk_c, Q => \datain[5]\); - - \proa3.x0_RNIC8FG2\ : MX2 - port map(A => \dataoutx[26]\, B => \datain[26]\, S => - un4_scantestbp_0, Y => data1(26)); - - \proa3.x0_RNIN52J2\ : MX2 - port map(A => \dataoutx[3]\, B => \datain[3]\, S => - un4_scantestbp_0, Y => data1(3)); - - \wrfst_gen.no_contention_check.r.datain[21]\ : DFN1 - port map(D => wdata(21), CLK => lclk_c, Q => \datain[21]\); - - \wrfst_gen.no_contention_check.r.datain[20]\ : DFN1 - port map(D => wdata(20), CLK => lclk_c, Q => \datain[20]\); - - \wrfst_gen.no_contention_check.r.datain[0]\ : DFN1 - port map(D => wdata(0), CLK => lclk_c, Q => \datain[0]\); - - \proa3.x0_RNITT2J2\ : MX2 - port map(A => \dataoutx[9]\, B => \datain[9]\, S => - un4_scantestbp, Y => data1(9)); - - \wrfst_gen.no_contention_check.r.datain[19]\ : DFN1 - port map(D => wdata(19), CLK => lclk_c, Q => \datain[19]\); - - \proa3.x0_RNIPD2J2\ : MX2C - port map(A => \dataoutx[5]\, B => \datain[5]\, S => - un4_scantestbp, Y => data1(5)); - - \wrfst_gen.no_contention_check.r.datain[6]\ : DFN1 - port map(D => wdata(6), CLK => lclk_c, Q => \datain[6]\); - - \proa3.x0_RNI78FG2\ : MX2 - port map(A => \dataoutx[21]\, B => \datain[21]\, S => - un4_scantestbp_0, Y => data1(21)); - - \proa3.x0_RNIKP1J2\ : MX2 - port map(A => \dataoutx[0]\, B => \datain[0]\, S => - un4_scantestbp_0, Y => data1(0)); - - \wrfst_gen.no_contention_check.r.waddr_RNISVL8[4]\ : XNOR2 - port map(A => \waddr[4]\, B => rfa1(4), Y => - un5_scantestbp_4_i_0); - - \wrfst_gen.no_contention_check.r.waddr[0]\ : DFN1 - port map(D => waddr_0(0), CLK => lclk_c, Q => \waddr[0]\); - - \wrfst_gen.no_contention_check.r.waddr[1]\ : DFN1 - port map(D => waddr_0(1), CLK => lclk_c, Q => \waddr[1]\); - - \proa3.x0_RNIB4FG2\ : MX2 - port map(A => \dataoutx[18]\, B => \datain[18]\, S => - un4_scantestbp, Y => data1(18)); - - \wrfst_gen.no_contention_check.r.datain[11]\ : DFN1 - port map(D => wdata(11), CLK => lclk_c, Q => \datain[11]\); - - \wrfst_gen.no_contention_check.r.datain[10]\ : DFN1 - port map(D => wdata(10), CLK => lclk_c, Q => \datain[10]\); - - \proa3.x0_RNIE8FG2\ : MX2 - port map(A => \dataoutx[28]\, B => \datain[28]\, S => - un4_scantestbp_0, Y => data1(28)); - - \proa3.x0_RNIACFG2\ : MX2 - port map(A => \dataoutx[31]\, B => \datain[31]\, S => - un4_scantestbp, Y => data1(31)); - - \proa3.x0_RNI54FG2\ : MX2 - port map(A => \dataoutx[12]\, B => \datain[12]\, S => - un4_scantestbp_0, Y => data1(12)); - - \wrfst_gen.no_contention_check.r.datain[9]\ : DFN1 - port map(D => wdata(9), CLK => lclk_c, Q => \datain[9]\); - - \wrfst_gen.no_contention_check.r.write_RNI9BTB\ : NOR3C - port map(A => \write\, B => rfe1, C => un5_scantestbp_0_i_0, - Y => un4_scantestbp_1); - - \wrfst_gen.no_contention_check.r.waddr_RNIKFL8[0]\ : XNOR2 - port map(A => \waddr[0]\, B => rfa1(0), Y => - un5_scantestbp_0_i_0); - - \proa3.x0_RNI98FG2\ : MX2 - port map(A => \dataoutx[23]\, B => \datain[23]\, S => - un4_scantestbp_0, Y => data1(23)); - - \wrfst_gen.no_contention_check.r.datain[1]\ : DFN1 - port map(D => wdata(1), CLK => lclk_c, Q => \datain[1]\); - - \proa3.x0_RNIC4FG2\ : MX2 - port map(A => \dataoutx[19]\, B => \datain[19]\, S => - un4_scantestbp_0, Y => data1(19)); - - \proa3.x0_RNI88FG2\ : MX2 - port map(A => \dataoutx[22]\, B => \datain[22]\, S => - un4_scantestbp_0, Y => data1(22)); - - \proa3.x0_RNI34FG2\ : MX2 - port map(A => \dataoutx[10]\, B => \datain[10]\, S => - un4_scantestbp, Y => data1(10)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity regfile_3p is - - port( rfa2 : in std_logic_vector(7 downto 0); - data2 : out std_logic_vector(31 downto 0); - raddr2 : in std_logic_vector(7 downto 0); - rfa1 : in std_logic_vector(7 downto 0); - data1 : out std_logic_vector(31 downto 0); - waddr : in std_logic_vector(7 downto 0); - wdata : in std_logic_vector(31 downto 0); - raddr1 : in std_logic_vector(7 downto 0); - rfe2 : in std_logic; - ren2 : in std_logic; - rfe1 : in std_logic; - lclk_c : in std_logic; - wren : in std_logic; - ren1 : in std_logic - ); - -end regfile_3p; - -architecture DEF_ARCH of regfile_3p is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component syncram_2pZ0_1 - port( wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - waddr_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - raddr2 : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(31 downto 0) := (others => 'U'); - data2 : out std_logic_vector(31 downto 0); - waddr : in std_logic_vector(7 downto 0) := (others => 'U'); - rfa2 : in std_logic_vector(7 downto 0) := (others => 'U'); - wren : in std_logic := 'U'; - ren2 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - rfe2 : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component syncram_2pZ0 - port( raddr1 : in std_logic_vector(7 downto 0) := (others => 'U'); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - waddr_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : out std_logic_vector(31 downto 0); - data1 : out std_logic_vector(31 downto 0); - waddr : out std_logic_vector(7 downto 0); - rfa1 : in std_logic_vector(7 downto 0) := (others => 'U'); - ren1 : in std_logic := 'U'; - wren : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - rfe1 : in std_logic := 'U'; - write : out std_logic - ); - end component; - - signal \datain[0]\, \datain[1]\, \datain[2]\, \datain[3]\, - \datain[4]\, \datain[5]\, \datain[6]\, \datain[7]\, - \datain[8]\, \datain[9]\, \datain[10]\, \datain[11]\, - \datain[12]\, \datain[13]\, \datain[14]\, \datain[15]\, - \datain[16]\, \datain[17]\, \datain[18]\, \datain[19]\, - \datain[20]\, \datain[21]\, \datain[22]\, \datain[23]\, - \datain[24]\, \datain[25]\, \datain[26]\, \datain[27]\, - \datain[28]\, \datain[29]\, \datain[30]\, \datain[31]\, - \waddr_0[0]\, \waddr_0[1]\, \waddr_0[2]\, \waddr_0[3]\, - \waddr_0[4]\, \waddr_0[5]\, \waddr_0[6]\, \waddr_0[7]\, - write, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : syncram_2pZ0_1 - Use entity work.syncram_2pZ0_1(DEF_ARCH); - for all : syncram_2pZ0 - Use entity work.syncram_2pZ0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \s1.dp.x1\ : syncram_2pZ0_1 - port map(wdata(31) => wdata(31), wdata(30) => wdata(30), - wdata(29) => wdata(29), wdata(28) => wdata(28), wdata(27) - => wdata(27), wdata(26) => wdata(26), wdata(25) => - wdata(25), wdata(24) => wdata(24), wdata(23) => wdata(23), - wdata(22) => wdata(22), wdata(21) => wdata(21), wdata(20) - => wdata(20), wdata(19) => wdata(19), wdata(18) => - wdata(18), wdata(17) => wdata(17), wdata(16) => wdata(16), - wdata(15) => wdata(15), wdata(14) => wdata(14), wdata(13) - => wdata(13), wdata(12) => wdata(12), wdata(11) => - wdata(11), wdata(10) => wdata(10), wdata(9) => wdata(9), - wdata(8) => wdata(8), wdata(7) => wdata(7), wdata(6) => - wdata(6), wdata(5) => wdata(5), wdata(4) => wdata(4), - wdata(3) => wdata(3), wdata(2) => wdata(2), wdata(1) => - wdata(1), wdata(0) => wdata(0), waddr_0(7) => waddr(7), - waddr_0(6) => waddr(6), waddr_0(5) => waddr(5), - waddr_0(4) => waddr(4), waddr_0(3) => waddr(3), - waddr_0(2) => waddr(2), waddr_0(1) => waddr(1), - waddr_0(0) => waddr(0), raddr2(7) => raddr2(7), raddr2(6) - => raddr2(6), raddr2(5) => raddr2(5), raddr2(4) => - raddr2(4), raddr2(3) => raddr2(3), raddr2(2) => raddr2(2), - raddr2(1) => raddr2(1), raddr2(0) => raddr2(0), - datain(31) => \datain[31]\, datain(30) => \datain[30]\, - datain(29) => \datain[29]\, datain(28) => \datain[28]\, - datain(27) => \datain[27]\, datain(26) => \datain[26]\, - datain(25) => \datain[25]\, datain(24) => \datain[24]\, - datain(23) => \datain[23]\, datain(22) => \datain[22]\, - datain(21) => \datain[21]\, datain(20) => \datain[20]\, - datain(19) => \datain[19]\, datain(18) => \datain[18]\, - datain(17) => \datain[17]\, datain(16) => \datain[16]\, - datain(15) => \datain[15]\, datain(14) => \datain[14]\, - datain(13) => \datain[13]\, datain(12) => \datain[12]\, - datain(11) => \datain[11]\, datain(10) => \datain[10]\, - datain(9) => \datain[9]\, datain(8) => \datain[8]\, - datain(7) => \datain[7]\, datain(6) => \datain[6]\, - datain(5) => \datain[5]\, datain(4) => \datain[4]\, - datain(3) => \datain[3]\, datain(2) => \datain[2]\, - datain(1) => \datain[1]\, datain(0) => \datain[0]\, - data2(31) => data2(31), data2(30) => data2(30), data2(29) - => data2(29), data2(28) => data2(28), data2(27) => - data2(27), data2(26) => data2(26), data2(25) => data2(25), - data2(24) => data2(24), data2(23) => data2(23), data2(22) - => data2(22), data2(21) => data2(21), data2(20) => - data2(20), data2(19) => data2(19), data2(18) => data2(18), - data2(17) => data2(17), data2(16) => data2(16), data2(15) - => data2(15), data2(14) => data2(14), data2(13) => - data2(13), data2(12) => data2(12), data2(11) => data2(11), - data2(10) => data2(10), data2(9) => data2(9), data2(8) - => data2(8), data2(7) => data2(7), data2(6) => data2(6), - data2(5) => data2(5), data2(4) => data2(4), data2(3) => - data2(3), data2(2) => data2(2), data2(1) => data2(1), - data2(0) => data2(0), waddr(7) => \waddr_0[7]\, waddr(6) - => \waddr_0[6]\, waddr(5) => \waddr_0[5]\, waddr(4) => - \waddr_0[4]\, waddr(3) => \waddr_0[3]\, waddr(2) => - \waddr_0[2]\, waddr(1) => \waddr_0[1]\, waddr(0) => - \waddr_0[0]\, rfa2(7) => rfa2(7), rfa2(6) => rfa2(6), - rfa2(5) => rfa2(5), rfa2(4) => rfa2(4), rfa2(3) => - rfa2(3), rfa2(2) => rfa2(2), rfa2(1) => rfa2(1), rfa2(0) - => rfa2(0), wren => wren, ren2 => ren2, lclk_c => lclk_c, - rfe2 => rfe2, write => write); - - VCC_i : VCC - port map(Y => \VCC\); - - \s1.dp.x0\ : syncram_2pZ0 - port map(raddr1(7) => raddr1(7), raddr1(6) => raddr1(6), - raddr1(5) => raddr1(5), raddr1(4) => raddr1(4), raddr1(3) - => raddr1(3), raddr1(2) => raddr1(2), raddr1(1) => - raddr1(1), raddr1(0) => raddr1(0), wdata(31) => wdata(31), - wdata(30) => wdata(30), wdata(29) => wdata(29), wdata(28) - => wdata(28), wdata(27) => wdata(27), wdata(26) => - wdata(26), wdata(25) => wdata(25), wdata(24) => wdata(24), - wdata(23) => wdata(23), wdata(22) => wdata(22), wdata(21) - => wdata(21), wdata(20) => wdata(20), wdata(19) => - wdata(19), wdata(18) => wdata(18), wdata(17) => wdata(17), - wdata(16) => wdata(16), wdata(15) => wdata(15), wdata(14) - => wdata(14), wdata(13) => wdata(13), wdata(12) => - wdata(12), wdata(11) => wdata(11), wdata(10) => wdata(10), - wdata(9) => wdata(9), wdata(8) => wdata(8), wdata(7) => - wdata(7), wdata(6) => wdata(6), wdata(5) => wdata(5), - wdata(4) => wdata(4), wdata(3) => wdata(3), wdata(2) => - wdata(2), wdata(1) => wdata(1), wdata(0) => wdata(0), - waddr_0(7) => waddr(7), waddr_0(6) => waddr(6), - waddr_0(5) => waddr(5), waddr_0(4) => waddr(4), - waddr_0(3) => waddr(3), waddr_0(2) => waddr(2), - waddr_0(1) => waddr(1), waddr_0(0) => waddr(0), - datain(31) => \datain[31]\, datain(30) => \datain[30]\, - datain(29) => \datain[29]\, datain(28) => \datain[28]\, - datain(27) => \datain[27]\, datain(26) => \datain[26]\, - datain(25) => \datain[25]\, datain(24) => \datain[24]\, - datain(23) => \datain[23]\, datain(22) => \datain[22]\, - datain(21) => \datain[21]\, datain(20) => \datain[20]\, - datain(19) => \datain[19]\, datain(18) => \datain[18]\, - datain(17) => \datain[17]\, datain(16) => \datain[16]\, - datain(15) => \datain[15]\, datain(14) => \datain[14]\, - datain(13) => \datain[13]\, datain(12) => \datain[12]\, - datain(11) => \datain[11]\, datain(10) => \datain[10]\, - datain(9) => \datain[9]\, datain(8) => \datain[8]\, - datain(7) => \datain[7]\, datain(6) => \datain[6]\, - datain(5) => \datain[5]\, datain(4) => \datain[4]\, - datain(3) => \datain[3]\, datain(2) => \datain[2]\, - datain(1) => \datain[1]\, datain(0) => \datain[0]\, - data1(31) => data1(31), data1(30) => data1(30), data1(29) - => data1(29), data1(28) => data1(28), data1(27) => - data1(27), data1(26) => data1(26), data1(25) => data1(25), - data1(24) => data1(24), data1(23) => data1(23), data1(22) - => data1(22), data1(21) => data1(21), data1(20) => - data1(20), data1(19) => data1(19), data1(18) => data1(18), - data1(17) => data1(17), data1(16) => data1(16), data1(15) - => data1(15), data1(14) => data1(14), data1(13) => - data1(13), data1(12) => data1(12), data1(11) => data1(11), - data1(10) => data1(10), data1(9) => data1(9), data1(8) - => data1(8), data1(7) => data1(7), data1(6) => data1(6), - data1(5) => data1(5), data1(4) => data1(4), data1(3) => - data1(3), data1(2) => data1(2), data1(1) => data1(1), - data1(0) => data1(0), waddr(7) => \waddr_0[7]\, waddr(6) - => \waddr_0[6]\, waddr(5) => \waddr_0[5]\, waddr(4) => - \waddr_0[4]\, waddr(3) => \waddr_0[3]\, waddr(2) => - \waddr_0[2]\, waddr(1) => \waddr_0[1]\, waddr(0) => - \waddr_0[0]\, rfa1(7) => rfa1(7), rfa1(6) => rfa1(6), - rfa1(5) => rfa1(5), rfa1(4) => rfa1(4), rfa1(3) => - rfa1(3), rfa1(2) => rfa1(2), rfa1(1) => rfa1(1), rfa1(0) - => rfa1(0), ren1 => ren1, wren => wren, lclk_c => lclk_c, - rfe1 => rfe1, write => write); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity leon3s is - - port( irl_0 : in std_logic_vector(3 downto 0); - irl : out std_logic_vector(3 downto 0); - hrdata_1_0_1 : in std_logic_vector(1 to 1); - data_0_21 : out std_logic; - data_0_16 : out std_logic; - data_0_5 : out std_logic; - data_0_2 : out std_logic; - data_0_0 : out std_logic; - nbo_5_0 : out std_logic_vector(1 downto 0); - htrans : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - htrans_tz : out std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 2); - hwdata_16 : out std_logic; - hwdata_3 : out std_logic; - hwdata_9 : out std_logic; - hwdata_11 : out std_logic; - hwdata_25 : out std_logic; - hwdata_27 : out std_logic; - hwdata_13 : out std_logic; - hwdata_4 : out std_logic; - hwdata_12 : out std_logic; - hwdata_23 : out std_logic; - hwdata_28 : out std_logic; - hwdata_1 : out std_logic; - hwdata_14 : out std_logic; - hwdata_0 : out std_logic; - hwdata_15 : out std_logic; - iosn_1 : in std_logic_vector(93 to 93); - hsize_5 : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(0 to 0); - hresp : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - address : out std_logic_vector(1 downto 0); - size : out std_logic_vector(0 to 0); - data_0_d0 : out std_logic; - data_5 : out std_logic; - data_3 : out std_logic; - data_8 : out std_logic; - data_19 : out std_logic; - data_24 : out std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_9 : in std_logic; - hrdata_10 : in std_logic; - hrdata_11 : in std_logic; - hrdata_13 : in std_logic; - hrdata_14 : in std_logic; - hrdata_17 : in std_logic; - hrdata_24 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_8 : in std_logic; - hrdata_12 : in std_logic; - hrdata_15 : in std_logic; - hrdata_16 : in std_logic; - hrdata_18 : in std_logic; - hrdata_21 : in std_logic; - hrdata_22 : in std_logic; - hrdata_23 : in std_logic; - hrdata_26 : in std_logic; - hrdata_27 : in std_logic; - hrdata_2 : in std_logic; - hrdata_3 : in std_logic; - hrdata_4 : in std_logic; - hrdata_7 : in std_logic; - hrdata_5 : in std_logic; - hrdata_6 : in std_logic; - hrdata_28 : in std_logic; - hrdata_29 : in std_logic; - hrdata_30 : in std_logic; - hrdata_31 : in std_logic; - error_i_2 : out std_logic; - intack : out std_logic; - N_546 : in std_logic; - leon3s_VCC : in std_logic; - N_264 : in std_logic; - N_262 : in std_logic; - N_78 : in std_logic; - bo_5842_d_0 : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - hlock : out std_logic; - N_5054 : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - hbusreq : out std_logic; - un60_nbo : out std_logic; - N_457 : out std_logic; - N_462 : out std_logic; - N_467 : out std_logic; - werr_2_m_0 : out std_logic; - un91_nbo_i_0 : out std_logic; - N_138 : out std_logic; - N_139 : out std_logic; - bo_5842_d : out std_logic; - N_458 : out std_logic; - N_459 : out std_logic; - N_461 : out std_logic; - N_463 : out std_logic; - N_468 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_466 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - un59_nbo : out std_logic; - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end leon3s; - -architecture DEF_ARCH of leon3s is - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component cachemem - port( xaddress_RNIFP43F : in std_logic_vector(2 to 2) := (others => 'U'); - xaddress_RNITFTTE : in std_logic_vector(3 to 3) := (others => 'U'); - dstate_RNIC3QA81 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIFPT581 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIFS6E51 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNI1Q9ST1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIEHIUT1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNILHOK61 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNILK99L1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNI1I3MQ1 : in std_logic_vector(0 to 0) := (others => 'U'); - xaddress_RNIK99NK1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIP2BVK1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIJI2O22 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNI1G47MJ : in std_logic_vector(1 to 1) := (others => 'U'); - edata2_iv_i_0 : in std_logic_vector(31 to 31) := (others => 'U'); - addr : in std_logic_vector(30 to 30) := (others => 'U'); - maddress : in std_logic_vector(28 to 28) := (others => 'U'); - newtag_1_0 : in std_logic_vector(27 downto 24) := (others => 'U'); - faddr_RNI7879K : in std_logic_vector(0 to 0) := (others => 'U'); - faddr_RNIEHR0O : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNIB0UOO : in std_logic_vector(2 to 2) := (others => 'U'); - xaddress_RNID252J1 : in std_logic_vector(10 to 10) := (others => 'U'); - faddr_RNI7MK691 : in std_logic_vector(6 to 6) := (others => 'U'); - dstate_i_0_RNIL7FGFS : in std_logic_vector(8 to 8) := (others => 'U'); - dstate_i_0_RNIH0PPES : in std_logic_vector(8 to 8) := (others => 'U'); - dstate_i_RNI29QQ7J3 : in std_logic_vector(8 to 8) := (others => 'U'); - xaddress_RNITMH17S2 : in std_logic_vector(12 to 12) := (others => 'U'); - xaddress_RNICFI17S2 : in std_logic_vector(13 to 13) := (others => 'U'); - xaddress_RNIN7J17S2 : in std_logic_vector(14 to 14) := (others => 'U'); - xaddress_RNI2MB27S2 : in std_logic_vector(15 to 15) := (others => 'U'); - xaddress_RNIID927S2 : in std_logic_vector(16 to 16) := (others => 'U'); - xaddress_RNI0GI17S2 : in std_logic_vector(17 to 17) := (others => 'U'); - xaddress_RNI1D927S2 : in std_logic_vector(20 to 20) := (others => 'U'); - xaddress_RNIC5A27S2 : in std_logic_vector(21 to 21) := (others => 'U'); - xaddress_RNI9MB27S2 : in std_logic_vector(23 to 23) := (others => 'U'); - dataout : out std_logic_vector(35 downto 0); - vaddress_RNI8EVQ36 : in std_logic_vector(2 to 2) := (others => 'U'); - vaddress_RNIFCB8U6 : in std_logic_vector(3 to 3) := (others => 'U'); - vaddress_RNIJG6QR7 : in std_logic_vector(4 to 4) := (others => 'U'); - istate_RNIUCOFG : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIPSU8G : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6HPAI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI57KLB : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIG7IIA : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIEC82C : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI7BUID : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIV33V9 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIMRTH8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIGUTA8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6LOO6 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIKJBN8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIN6957 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6PSS1 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIOVC5J : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIA8N5H : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIK9NF8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNILTAC8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI8BL1A : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI2MM6D : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIVTQIJ : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIAJH4F : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIM2DE7 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI5V68H : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIH0NBI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIAP6PI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIOJJE1 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIR2JU8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIJSOBE : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIRASC8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIS4VK8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIENB3M : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIJCMP6 : in std_logic_vector(0 to 0) := (others => 'U'); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0) := (others => 'U'); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNISJSHQA : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIUT72LB : in std_logic_vector(3 to 3) := (others => 'U'); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4) := (others => 'U'); - faddr_RNI7UFASD : in std_logic_vector(5 to 5) := (others => 'U'); - faddr_RNIDN2CUE : in std_logic_vector(6 to 6) := (others => 'U'); - un1_p0_2_i_0 : in std_logic := 'U'; - un1_p0_2_i_4 : in std_logic := 'U'; - vaddress_RNIOFAKMI : in std_logic_vector(12 to 12) := (others => 'U'); - vaddress_RNIQFAKMI : in std_logic_vector(13 to 13) := (others => 'U'); - vaddress_RNISFAKMI : in std_logic_vector(14 to 14) := (others => 'U'); - vaddress_RNIUFAKMI : in std_logic_vector(15 to 15) := (others => 'U'); - vaddress_RNI0GAKMI : in std_logic_vector(16 to 16) := (others => 'U'); - vaddress_RNI2GAKMI : in std_logic_vector(17 to 17) := (others => 'U'); - vaddress_RNI4GAKMI : in std_logic_vector(18 to 18) := (others => 'U'); - vaddress_RNI6GAKMI : in std_logic_vector(19 to 19) := (others => 'U'); - vaddress_RNIQNAKMI : in std_logic_vector(20 to 20) := (others => 'U'); - vaddress_RNISNAKMI : in std_logic_vector(21 to 21) := (others => 'U'); - vaddress_RNIUNAKMI : in std_logic_vector(22 to 22) := (others => 'U'); - vaddress_RNI0OAKMI : in std_logic_vector(23 to 23) := (others => 'U'); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout_2 : out std_logic_vector(31 downto 0); - dataout_1 : out std_logic_vector(31 downto 0); - dataout_0 : out std_logic_vector(35 downto 0); - vitdatain_0_1_0 : out std_logic_vector(22 to 22); - un1_p0_2_0_0 : in std_logic := 'U'; - un1_p0_2_0_350 : in std_logic := 'U'; - dci_m_6 : in std_logic := 'U'; - dci_m_0 : in std_logic := 'U'; - dci_m_1 : in std_logic := 'U'; - dci_m_2 : in std_logic := 'U'; - dci_m_3 : in std_logic := 'U'; - dci_m_5 : in std_logic := 'U'; - N_10 : in std_logic := 'U'; - read_RNI0IQ7R : in std_logic := 'U'; - read_RNIRO4K31 : in std_logic := 'U'; - read_RNIQFOD21 : in std_logic := 'U'; - read_RNIFPFT31 : in std_logic := 'U'; - read_RNIQPCQ11 : in std_logic := 'U'; - read_RNI8DFM31 : in std_logic := 'U'; - read_RNIAQJ831 : in std_logic := 'U'; - read_RNI76N8R : in std_logic := 'U'; - read_RNI7G7G41 : in std_logic := 'U'; - read_RNIEKS231 : in std_logic := 'U'; - read_RNIMJHQT : in std_logic := 'U'; - read_RNIL633F1 : in std_logic := 'U'; - read_RNIQH64D1 : in std_logic := 'U'; - read_RNICAQK41 : in std_logic := 'U'; - read_RNIQMJI41 : in std_logic := 'U'; - read_RNISLPNU : in std_logic := 'U'; - read_RNICKHE91 : in std_logic := 'U'; - read_RNIC70OF1 : in std_logic := 'U'; - read_RNIC9O9B1 : in std_logic := 'U'; - read_RNI75LJ31 : in std_logic := 'U'; - read_RNIEEGDD1 : in std_logic := 'U'; - N_3254_0 : in std_logic := 'U'; - N_330 : in std_logic := 'U'; - N_267 : in std_logic := 'U'; - N_329 : in std_logic := 'U'; - N_144 : in std_logic := 'U'; - N_3846 : in std_logic := 'U'; - N_270 : in std_logic := 'U'; - N_269 : in std_logic := 'U'; - N_24 : in std_logic := 'U'; - N_26 : in std_logic := 'U'; - N_12_i_0 : in std_logic := 'U'; - flush_RNIJEN4SI3 : in std_logic := 'U'; - flush_RNIGUM2OH3 : in std_logic := 'U'; - N_16_i_0 : in std_logic := 'U'; - N_3239_i_0 : in std_logic := 'U'; - flush_0_1_RNIBUA27S2 : in std_logic := 'U'; - flush_0_1_RNIOMB27S2 : in std_logic := 'U'; - flush_0_1_RNIPTA27S2 : in std_logic := 'U'; - flush_RNIGBB873 : in std_logic := 'U'; - N_980 : in std_logic := 'U'; - N_981 : in std_logic := 'U'; - N_983 : in std_logic := 'U'; - N_982 : in std_logic := 'U'; - N_985 : in std_logic := 'U'; - N_986 : in std_logic := 'U'; - flush2 : in std_logic := 'U'; - N_987 : in std_logic := 'U'; - N_984 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - flush2_0_0_RNIPJ5O2 : in std_logic := 'U'; - flush2_0_0_RNITR5O2 : in std_logic := 'U'; - flush2_0_0_RNIVV5O2 : in std_logic := 'U'; - flush2_0_0_RNI146O2 : in std_logic := 'U'; - flush2_RNIFMGM2 : in std_logic := 'U'; - flush2_0_0_RNI7G6O2 : in std_logic := 'U'; - cachemem_VCC : in std_logic := 'U'; - flush2_RNI5I3N7 : in std_logic := 'U'; - un1_ici : in std_logic := 'U'; - N_258 : in std_logic := 'U'; - N_259 : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component proc3 - port( istate_RNIJCMP6 : out std_logic_vector(0 to 0); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - un1_p0_2_i_4 : out std_logic; - un1_p0_2_i_0 : out std_logic; - ctx : out std_logic_vector(7 downto 0); - istate_RNI6HPAI : out std_logic_vector(0 to 0); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - istate_RNI57KLB : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - istate_RNIH0NBI : out std_logic_vector(0 to 0); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - istate_RNI5V68H : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIEC82C : out std_logic_vector(0 to 0); - istate_RNIPSU8G : out std_logic_vector(0 to 0); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - istate_RNIA8N5H : out std_logic_vector(0 to 0); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - vitdatain_0_1_0 : in std_logic_vector(22 to 22) := (others => 'U'); - dataout_1 : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout_0 : in std_logic_vector(35 downto 0) := (others => 'U'); - dataout_2 : in std_logic_vector(31 downto 0) := (others => 'U'); - un1_p0_2_0_0 : out std_logic; - un1_p0_2_0_350 : out std_logic; - data_1_21 : out std_logic; - data_1_16 : out std_logic; - data_1_5 : out std_logic; - data_1_0 : out std_logic; - data_1_2 : out std_logic; - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - size_0 : out std_logic_vector(0 to 0); - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - dci_m_6 : out std_logic; - dci_m_5 : out std_logic; - dci_m_3 : out std_logic; - dci_m_2 : out std_logic; - dci_m_1 : out std_logic; - dci_m_0 : out std_logic; - faddr_RNI7879K : out std_logic_vector(0 to 0); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - newtag_1_0 : out std_logic_vector(27 downto 24); - dataout : in std_logic_vector(35 downto 0) := (others => 'U'); - address : out std_logic_vector(1 downto 0); - addr : out std_logic_vector(30 to 30); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - hgrant : in std_logic_vector(0 to 0) := (others => 'U'); - hsize_5 : out std_logic_vector(1 to 1); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hwdata_15 : out std_logic; - hwdata_0 : out std_logic; - hwdata_14 : out std_logic; - hwdata_1 : out std_logic; - hwdata_28 : out std_logic; - hwdata_23 : out std_logic; - hwdata_12 : out std_logic; - hwdata_4 : out std_logic; - hwdata_13 : out std_logic; - hwdata_27 : out std_logic; - hwdata_25 : out std_logic; - hwdata_11 : out std_logic; - hwdata_9 : out std_logic; - hwdata_3 : out std_logic; - hwdata_16 : out std_logic; - haddr : out std_logic_vector(31 downto 2); - htrans_tz : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : out std_logic_vector(1 to 1); - nbo_5_0 : out std_logic_vector(1 downto 0); - data_0 : out std_logic; - data_3 : out std_logic; - data_5 : out std_logic; - data_8 : out std_logic; - data_19 : out std_logic; - data_24 : out std_logic; - hrdata_1_0_1 : in std_logic_vector(1 to 1) := (others => 'U'); - data1 : in std_logic_vector(31 downto 0) := (others => 'U'); - maddress_28 : out std_logic; - data2 : in std_logic_vector(31 downto 0) := (others => 'U'); - irl_0 : out std_logic_vector(3 downto 0); - irl : in std_logic_vector(3 downto 0) := (others => 'U'); - edata2_iv_i_0_7 : out std_logic; - raddr1 : out std_logic_vector(7 downto 0); - rfa1 : out std_logic_vector(7 downto 0); - raddr2 : out std_logic_vector(7 downto 0); - rfa2 : out std_logic_vector(7 downto 0); - waddr : out std_logic_vector(7 downto 0); - wdata : out std_logic_vector(31 downto 0); - flush2_RNIFMGM2 : out std_logic; - flush2_RNI5I3N7 : out std_logic; - N_984 : out std_logic; - N_980 : out std_logic; - N_987 : out std_logic; - N_986 : out std_logic; - flush2 : out std_logic; - flush2_0_0_RNI146O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - N_981 : out std_logic; - N_985 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_264_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - un1_ici : out std_logic; - N_10 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - flush_RNIGBB873 : out std_logic; - N_270 : out std_logic; - N_269 : out std_logic; - N_267 : out std_logic; - N_259 : out std_logic; - N_258 : out std_logic; - N_144 : out std_logic; - N_3846 : out std_logic; - read_RNIQH64D1 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIRO4K31 : out std_logic; - read_RNI0IQ7R : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNICKHE91 : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - un59_nbo : out std_logic; - N_3239_i_0 : out std_logic; - N_26_0 : out std_logic; - read_RNIEKS231 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIC9O9B1 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNICAQK41 : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIEEGDD1 : out std_logic; - N_12_i_0 : out std_logic; - N_16_i_0 : out std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - N_24 : out std_logic; - N_329 : out std_logic; - N_330 : out std_logic; - N_3254_0 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - N_466 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_468 : out std_logic; - N_463 : out std_logic; - N_461 : out std_logic; - N_459 : out std_logic; - N_458 : out std_logic; - bo_5842_d : out std_logic; - N_139 : out std_logic; - N_138 : out std_logic; - un91_nbo_i_0 : out std_logic; - werr_2_m_0 : out std_logic; - N_467 : out std_logic; - N_462 : out std_logic; - N_457 : out std_logic; - un60_nbo : out std_logic; - hbusreq : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - N_5054 : out std_logic; - hlock : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - bo_5842_d_0 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - proc3_VCC : in std_logic := 'U'; - N_546 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - ra_bpmiss_1_0 : out std_logic; - rst : in std_logic := 'U'; - d_m5_0_a3_2 : out std_logic; - rst_RNIINI1H : in std_logic := 'U'; - rstate_1188n : in std_logic := 'U'; - ren1 : out std_logic; - rfe1 : out std_logic; - wren : out std_logic; - intack : out std_logic; - ren2 : out std_logic; - rfe2 : out std_logic; - error_i_2 : out std_logic - ); - end component; - - component regfile_3p - port( rfa2 : in std_logic_vector(7 downto 0) := (others => 'U'); - data2 : out std_logic_vector(31 downto 0); - raddr2 : in std_logic_vector(7 downto 0) := (others => 'U'); - rfa1 : in std_logic_vector(7 downto 0) := (others => 'U'); - data1 : out std_logic_vector(31 downto 0); - waddr : in std_logic_vector(7 downto 0) := (others => 'U'); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - raddr1 : in std_logic_vector(7 downto 0) := (others => 'U'); - rfe2 : in std_logic := 'U'; - ren2 : in std_logic := 'U'; - rfe1 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - wren : in std_logic := 'U'; - ren1 : in std_logic := 'U' - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \rst\, rst_0, rstate_1188n, \rst_RNIINI1H\, - d_m5_0_a3_2, ra_bpmiss_1_0, \istate_RNIJCMP6[0]\, - \faddr_RNIUT72LB[3]\, \vaddress_RNISNAKMI[21]\, - \vaddress_RNI6GAKMI[19]\, \faddr_RNISJSHQA[2]\, - \vaddress_RNIQNAKMI[20]\, \faddr_RNI7UFASD[5]\, - \faddr_RNI0FOJNE[4]\, \faddr_RNIDN2CUE[6]\, - \faddr_RNIKVTLT9[1]\, \vaddress_RNI0GAKMI[16]\, - \vaddress_RNI0OAKMI[23]\, \vaddress_RNIOFAKMI[12]\, - \vaddress_RNIJG6QR7[4]\, \un1_p0_2_i[121]\, - \un1_p0_2_i[117]\, \ctx[0]\, \ctx[1]\, \ctx[2]\, \ctx[3]\, - \ctx[4]\, \ctx[5]\, \ctx[6]\, \ctx[7]\, - \istate_RNI6HPAI[0]\, \istate_RNIAJH4F[0]\, - \vaddress_RNIUNAKMI[22]\, \vaddress_RNISFAKMI[14]\, - \istate_RNI57KLB[0]\, \istate_RNIUCOFG[0]\, - \faddr_RNI7H6KT8[0]\, \istate_RNIH0NBI[0]\, - \istate_RNIG7IIA[0]\, \vaddress_RNIFCB8U6[3]\, - \istate_RNI2MM6D[0]\, \istate_RNI8BL1A[0]\, - \istate_RNILTAC8[0]\, \istate_RNIK9NF8[0]\, - \vaddress_RNI4GAKMI[18]\, \vaddress_RNI2GAKMI[17]\, - \istate_RNI5V68H[0]\, \istate_RNIM2DE7[0]\, - \istate_RNIVTQIJ[0]\, \istate_RNIOVC5J[0]\, - \istate_RNI6PSS1[0]\, \istate_RNIGUTA8[0]\, - \istate_RNIMRTH8[0]\, \vaddress_RNIQFAKMI[13]\, - \istate_RNIAP6PI[0]\, \istate_RNIENB3M[0]\, - \istate_RNIS4VK8[0]\, \istate_RNIRASC8[0]\, - \istate_RNIJSOBE[0]\, \istate_RNIR2JU8[0]\, - \istate_RNIOJJE1[0]\, \istate_RNIN6957[0]\, - \istate_RNIKJBN8[0]\, \istate_RNI6LOO6[0]\, - \istate_RNIV33V9[0]\, \istate_RNI7BUID[0]\, - \istate_RNIEC82C[0]\, \istate_RNIPSU8G[0]\, - \vaddress_RNI8EVQ36[2]\, \istate_RNIA8N5H[0]\, - \vaddress_RNIUFAKMI[15]\, \vitdatain_0_1_0[22]\, - \dataout_1[0]\, \dataout_1[1]\, \dataout_1[2]\, - \dataout_1[3]\, \dataout_1[4]\, \dataout_1[5]\, - \dataout_1[6]\, \dataout_1[7]\, \dataout_1[8]\, - \dataout_1[9]\, \dataout_1[10]\, \dataout_1[11]\, - \dataout_1[12]\, \dataout_1[13]\, \dataout_1[14]\, - \dataout_1[15]\, \dataout_1[16]\, \dataout_1[17]\, - \dataout_1[18]\, \dataout_1[19]\, \dataout_1[20]\, - \dataout_1[21]\, \dataout_1[22]\, \dataout_1[23]\, - \dataout_1[24]\, \dataout_1[25]\, \dataout_1[26]\, - \dataout_1[27]\, \dataout_1[28]\, \dataout_1[29]\, - \dataout_1[30]\, \dataout_1[31]\, \dataout_0[0]\, - \dataout_0[1]\, \dataout_0[2]\, \dataout_0[3]\, - \dataout_0[4]\, \dataout_0[5]\, \dataout_0[6]\, - \dataout_0[7]\, \dataout_0[8]\, \dataout_0[9]\, - \dataout_0[10]\, \dataout_0[11]\, \dataout_0[12]\, - \dataout_0[13]\, \dataout_0[14]\, \dataout_0[15]\, - \dataout_0[16]\, \dataout_0[17]\, \dataout_0[18]\, - \dataout_0[19]\, \dataout_0[20]\, \dataout_0[21]\, - \dataout_0[22]\, \dataout_0[23]\, \dataout_0[24]\, - \dataout_0[25]\, \dataout_0[26]\, \dataout_0[27]\, - \dataout_0[28]\, \dataout_0[29]\, \dataout_0[30]\, - \dataout_0[31]\, \dataout_0[32]\, \dataout_0[33]\, - \dataout_0[34]\, \dataout_0[35]\, \dataout_2[0]\, - \dataout_2[1]\, \dataout_2[2]\, \dataout_2[3]\, - \dataout_2[4]\, \dataout_2[5]\, \dataout_2[6]\, - \dataout_2[7]\, \dataout_2[8]\, \dataout_2[9]\, - \dataout_2[10]\, \dataout_2[11]\, \dataout_2[12]\, - \dataout_2[13]\, \dataout_2[14]\, \dataout_2[15]\, - \dataout_2[16]\, \dataout_2[17]\, \dataout_2[18]\, - \dataout_2[19]\, \dataout_2[20]\, \dataout_2[21]\, - \dataout_2[22]\, \dataout_2[23]\, \dataout_2[24]\, - \dataout_2[25]\, \dataout_2[26]\, \dataout_2[27]\, - \dataout_2[28]\, \dataout_2[29]\, \dataout_2[30]\, - \dataout_2[31]\, \un1_p0_2_0[148]\, \un1_p0_2_0[498]\, - \faddr_RNIB0UOO[2]\, \dstate_i_RNI29QQ7J3[8]\, - \xaddress_RNITFTTE[3]\, \xaddress_RNIFP43F[2]\, - \faddr_RNI7MK691[6]\, \dci_m[102]\, \dci_m[101]\, - \dci_m[99]\, \dci_m[98]\, \dci_m[97]\, \dci_m[96]\, - \faddr_RNI7879K[0]\, \faddr_RNIEHR0O[1]\, - \dstate_RNIC3QA81[1]\, \dstate_RNIFPT581[1]\, - \dstate_i_0_RNIH0PPES[8]\, \dstate_RNI1G47MJ[1]\, - \dstate_RNIFS6E51[1]\, \xaddress_RNI1Q9ST1[1]\, - \xaddress_RNIEHIUT1[1]\, \xaddress_RNILHOK61[1]\, - \xaddress_RNILK99L1[1]\, \xaddress_RNI1I3MQ1[0]\, - \xaddress_RNIK99NK1[1]\, \xaddress_RNIP2BVK1[1]\, - \xaddress_RNIJI2O22[1]\, \xaddress_RNITMH17S2[12]\, - \xaddress_RNICFI17S2[13]\, \xaddress_RNI1D927S2[20]\, - \xaddress_RNI9MB27S2[23]\, \xaddress_RNI0GI17S2[17]\, - \xaddress_RNIC5A27S2[21]\, \xaddress_RNIN7J17S2[14]\, - \xaddress_RNIID927S2[16]\, \xaddress_RNI2MB27S2[15]\, - \dstate_i_0_RNIL7FGFS[8]\, \xaddress_RNID252J1[10]\, - \newtag_1_0[24]\, \newtag_1_0[25]\, \newtag_1_0[26]\, - \newtag_1_0[27]\, \dataout[0]\, \dataout[1]\, - \dataout[2]\, \dataout[3]\, \dataout[4]\, \dataout[5]\, - \dataout[6]\, \dataout[7]\, \dataout[8]\, \dataout[9]\, - \dataout[10]\, \dataout[11]\, \dataout[12]\, - \dataout[13]\, \dataout[14]\, \dataout[15]\, - \dataout[16]\, \dataout[17]\, \dataout[18]\, - \dataout[19]\, \dataout[20]\, \dataout[21]\, - \dataout[22]\, \dataout[23]\, \dataout[24]\, - \dataout[25]\, \dataout[26]\, \dataout[27]\, - \dataout[28]\, \dataout[29]\, \dataout[30]\, - \dataout[31]\, \dataout[32]\, \dataout[33]\, - \dataout[34]\, \dataout[35]\, \addr[30]\, \data1[0]\, - \data1[1]\, \data1[2]\, \data1[3]\, \data1[4]\, - \data1[5]\, \data1[6]\, \data1[7]\, \data1[8]\, - \data1[9]\, \data1[10]\, \data1[11]\, \data1[12]\, - \data1[13]\, \data1[14]\, \data1[15]\, \data1[16]\, - \data1[17]\, \data1[18]\, \data1[19]\, \data1[20]\, - \data1[21]\, \data1[22]\, \data1[23]\, \data1[24]\, - \data1[25]\, \data1[26]\, \data1[27]\, \data1[28]\, - \data1[29]\, \data1[30]\, \data1[31]\, \maddress[28]\, - \data2[0]\, \data2[1]\, \data2[2]\, \data2[3]\, - \data2[4]\, \data2[5]\, \data2[6]\, \data2[7]\, - \data2[8]\, \data2[9]\, \data2[10]\, \data2[11]\, - \data2[12]\, \data2[13]\, \data2[14]\, \data2[15]\, - \data2[16]\, \data2[17]\, \data2[18]\, \data2[19]\, - \data2[20]\, \data2[21]\, \data2[22]\, \data2[23]\, - \data2[24]\, \data2[25]\, \data2[26]\, \data2[27]\, - \data2[28]\, \data2[29]\, \data2[30]\, \data2[31]\, - \edata2_iv_i_0[31]\, \raddr1[0]\, \raddr1[1]\, - \raddr1[2]\, \raddr1[3]\, \raddr1[4]\, \raddr1[5]\, - \raddr1[6]\, \raddr1[7]\, \rfa1[0]\, \rfa1[1]\, \rfa1[2]\, - \rfa1[3]\, \rfa1[4]\, \rfa1[5]\, \rfa1[6]\, \rfa1[7]\, - \raddr2[0]\, \raddr2[1]\, \raddr2[2]\, \raddr2[3]\, - \raddr2[4]\, \raddr2[5]\, \raddr2[6]\, \raddr2[7]\, - \rfa2[0]\, \rfa2[1]\, \rfa2[2]\, \rfa2[3]\, \rfa2[4]\, - \rfa2[5]\, \rfa2[6]\, \rfa2[7]\, \waddr[0]\, \waddr[1]\, - \waddr[2]\, \waddr[3]\, \waddr[4]\, \waddr[5]\, - \waddr[6]\, \waddr[7]\, \wdata[0]\, \wdata[1]\, - \wdata[2]\, \wdata[3]\, \wdata[4]\, \wdata[5]\, - \wdata[6]\, \wdata[7]\, \wdata[8]\, \wdata[9]\, - \wdata[10]\, \wdata[11]\, \wdata[12]\, \wdata[13]\, - \wdata[14]\, \wdata[15]\, \wdata[16]\, \wdata[17]\, - \wdata[18]\, \wdata[19]\, \wdata[20]\, \wdata[21]\, - \wdata[22]\, \wdata[23]\, \wdata[24]\, \wdata[25]\, - \wdata[26]\, \wdata[27]\, \wdata[28]\, \wdata[29]\, - \wdata[30]\, \wdata[31]\, flush2_RNIFMGM2, - flush2_RNI5I3N7, N_984, N_980, N_987, N_986, flush2, - flush2_0_0_RNI146O2, flush2_0_0_RNI7G6O2, - flush2_0_0_RNIVV5O2, flush2_0_0_RNITR5O2, - flush2_0_0_RNIPJ5O2, N_981, N_985, N_983, N_982, un1_ici, - N_10, flush_RNIJEN4SI3, flush_RNIGBB873, N_270, N_269, - N_267, N_259, N_258, N_144, N_3846, read_RNIQH64D1, - read_RNIQPCQ11, read_RNIRO4K31, read_RNI0IQ7R, - read_RNIQFOD21, read_RNI8DFM31, read_RNIAQJ831, - read_RNI76N8R, read_RNI7G7G41, read_RNIMJHQT, - read_RNIL633F1, read_RNICKHE91, flush_0_1_RNIOMB27S2, - N_3239_i_0, N_26, read_RNIEKS231, read_RNIFPFT31, - read_RNIC9O9B1, flush_RNIGUM2OH3, read_RNICAQK41, - read_RNIQMJI41, read_RNISLPNU, read_RNIC70OF1, - read_RNI75LJ31, read_RNIEEGDD1, N_12_i_0, N_16_i_0, - flush_0_1_RNIBUA27S2, flush_0_1_RNIPTA27S2, N_24, N_329, - N_330, N_3254_0, ren1, rfe1, wren, ren2, rfe2, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : cachemem - Use entity work.cachemem(DEF_ARCH); - for all : proc3 - Use entity work.proc3(DEF_ARCH); - for all : regfile_3p - Use entity work.regfile_3p(DEF_ARCH); -begin - - - rst_RNI55L3 : CLKINT - port map(A => rst_0, Y => \rst\); - - rst : DFN1 - port map(D => rstn, CLK => lclk_c, Q => rst_0); - - cmem0 : cachemem - port map(xaddress_RNIFP43F(2) => \xaddress_RNIFP43F[2]\, - xaddress_RNITFTTE(3) => \xaddress_RNITFTTE[3]\, - dstate_RNIC3QA81(1) => \dstate_RNIC3QA81[1]\, - dstate_RNIFPT581(1) => \dstate_RNIFPT581[1]\, - dstate_RNIFS6E51(1) => \dstate_RNIFS6E51[1]\, - xaddress_RNI1Q9ST1(1) => \xaddress_RNI1Q9ST1[1]\, - xaddress_RNIEHIUT1(1) => \xaddress_RNIEHIUT1[1]\, - xaddress_RNILHOK61(1) => \xaddress_RNILHOK61[1]\, - xaddress_RNILK99L1(1) => \xaddress_RNILK99L1[1]\, - xaddress_RNI1I3MQ1(0) => \xaddress_RNI1I3MQ1[0]\, - xaddress_RNIK99NK1(1) => \xaddress_RNIK99NK1[1]\, - xaddress_RNIP2BVK1(1) => \xaddress_RNIP2BVK1[1]\, - xaddress_RNIJI2O22(1) => \xaddress_RNIJI2O22[1]\, - dstate_RNI1G47MJ(1) => \dstate_RNI1G47MJ[1]\, - edata2_iv_i_0(31) => \edata2_iv_i_0[31]\, addr(30) => - \addr[30]\, maddress(28) => \maddress[28]\, - newtag_1_0(27) => \newtag_1_0[27]\, newtag_1_0(26) => - \newtag_1_0[26]\, newtag_1_0(25) => \newtag_1_0[25]\, - newtag_1_0(24) => \newtag_1_0[24]\, faddr_RNI7879K(0) => - \faddr_RNI7879K[0]\, faddr_RNIEHR0O(1) => - \faddr_RNIEHR0O[1]\, faddr_RNIB0UOO(2) => - \faddr_RNIB0UOO[2]\, xaddress_RNID252J1(10) => - \xaddress_RNID252J1[10]\, faddr_RNI7MK691(6) => - \faddr_RNI7MK691[6]\, dstate_i_0_RNIL7FGFS(8) => - \dstate_i_0_RNIL7FGFS[8]\, dstate_i_0_RNIH0PPES(8) => - \dstate_i_0_RNIH0PPES[8]\, dstate_i_RNI29QQ7J3(8) => - \dstate_i_RNI29QQ7J3[8]\, xaddress_RNITMH17S2(12) => - \xaddress_RNITMH17S2[12]\, xaddress_RNICFI17S2(13) => - \xaddress_RNICFI17S2[13]\, xaddress_RNIN7J17S2(14) => - \xaddress_RNIN7J17S2[14]\, xaddress_RNI2MB27S2(15) => - \xaddress_RNI2MB27S2[15]\, xaddress_RNIID927S2(16) => - \xaddress_RNIID927S2[16]\, xaddress_RNI0GI17S2(17) => - \xaddress_RNI0GI17S2[17]\, xaddress_RNI1D927S2(20) => - \xaddress_RNI1D927S2[20]\, xaddress_RNIC5A27S2(21) => - \xaddress_RNIC5A27S2[21]\, xaddress_RNI9MB27S2(23) => - \xaddress_RNI9MB27S2[23]\, dataout(35) => \dataout[35]\, - dataout(34) => \dataout[34]\, dataout(33) => - \dataout[33]\, dataout(32) => \dataout[32]\, dataout(31) - => \dataout[31]\, dataout(30) => \dataout[30]\, - dataout(29) => \dataout[29]\, dataout(28) => - \dataout[28]\, dataout(27) => \dataout[27]\, dataout(26) - => \dataout[26]\, dataout(25) => \dataout[25]\, - dataout(24) => \dataout[24]\, dataout(23) => - \dataout[23]\, dataout(22) => \dataout[22]\, dataout(21) - => \dataout[21]\, dataout(20) => \dataout[20]\, - dataout(19) => \dataout[19]\, dataout(18) => - \dataout[18]\, dataout(17) => \dataout[17]\, dataout(16) - => \dataout[16]\, dataout(15) => \dataout[15]\, - dataout(14) => \dataout[14]\, dataout(13) => - \dataout[13]\, dataout(12) => \dataout[12]\, dataout(11) - => \dataout[11]\, dataout(10) => \dataout[10]\, - dataout(9) => \dataout[9]\, dataout(8) => \dataout[8]\, - dataout(7) => \dataout[7]\, dataout(6) => \dataout[6]\, - dataout(5) => \dataout[5]\, dataout(4) => \dataout[4]\, - dataout(3) => \dataout[3]\, dataout(2) => \dataout[2]\, - dataout(1) => \dataout[1]\, dataout(0) => \dataout[0]\, - vaddress_RNI8EVQ36(2) => \vaddress_RNI8EVQ36[2]\, - vaddress_RNIFCB8U6(3) => \vaddress_RNIFCB8U6[3]\, - vaddress_RNIJG6QR7(4) => \vaddress_RNIJG6QR7[4]\, - istate_RNIUCOFG(0) => \istate_RNIUCOFG[0]\, - istate_RNIPSU8G(0) => \istate_RNIPSU8G[0]\, - istate_RNI6HPAI(0) => \istate_RNI6HPAI[0]\, - istate_RNI57KLB(0) => \istate_RNI57KLB[0]\, - istate_RNIG7IIA(0) => \istate_RNIG7IIA[0]\, - istate_RNIEC82C(0) => \istate_RNIEC82C[0]\, - istate_RNI7BUID(0) => \istate_RNI7BUID[0]\, - istate_RNIV33V9(0) => \istate_RNIV33V9[0]\, - istate_RNIMRTH8(0) => \istate_RNIMRTH8[0]\, - istate_RNIGUTA8(0) => \istate_RNIGUTA8[0]\, - istate_RNI6LOO6(0) => \istate_RNI6LOO6[0]\, - istate_RNIKJBN8(0) => \istate_RNIKJBN8[0]\, - istate_RNIN6957(0) => \istate_RNIN6957[0]\, - istate_RNI6PSS1(0) => \istate_RNI6PSS1[0]\, - istate_RNIOVC5J(0) => \istate_RNIOVC5J[0]\, - istate_RNIA8N5H(0) => \istate_RNIA8N5H[0]\, - istate_RNIK9NF8(0) => \istate_RNIK9NF8[0]\, - istate_RNILTAC8(0) => \istate_RNILTAC8[0]\, - istate_RNI8BL1A(0) => \istate_RNI8BL1A[0]\, - istate_RNI2MM6D(0) => \istate_RNI2MM6D[0]\, - istate_RNIVTQIJ(0) => \istate_RNIVTQIJ[0]\, - istate_RNIAJH4F(0) => \istate_RNIAJH4F[0]\, - istate_RNIM2DE7(0) => \istate_RNIM2DE7[0]\, - istate_RNI5V68H(0) => \istate_RNI5V68H[0]\, - istate_RNIH0NBI(0) => \istate_RNIH0NBI[0]\, - istate_RNIAP6PI(0) => \istate_RNIAP6PI[0]\, - istate_RNIOJJE1(0) => \istate_RNIOJJE1[0]\, - istate_RNIR2JU8(0) => \istate_RNIR2JU8[0]\, - istate_RNIJSOBE(0) => \istate_RNIJSOBE[0]\, - istate_RNIRASC8(0) => \istate_RNIRASC8[0]\, - istate_RNIS4VK8(0) => \istate_RNIS4VK8[0]\, - istate_RNIENB3M(0) => \istate_RNIENB3M[0]\, - istate_RNIJCMP6(0) => \istate_RNIJCMP6[0]\, - faddr_RNI7H6KT8(0) => \faddr_RNI7H6KT8[0]\, - faddr_RNIKVTLT9(1) => \faddr_RNIKVTLT9[1]\, - faddr_RNISJSHQA(2) => \faddr_RNISJSHQA[2]\, - faddr_RNIUT72LB(3) => \faddr_RNIUT72LB[3]\, - faddr_RNI0FOJNE(4) => \faddr_RNI0FOJNE[4]\, - faddr_RNI7UFASD(5) => \faddr_RNI7UFASD[5]\, - faddr_RNIDN2CUE(6) => \faddr_RNIDN2CUE[6]\, un1_p0_2_i_0 - => \un1_p0_2_i[117]\, un1_p0_2_i_4 => \un1_p0_2_i[121]\, - vaddress_RNIOFAKMI(12) => \vaddress_RNIOFAKMI[12]\, - vaddress_RNIQFAKMI(13) => \vaddress_RNIQFAKMI[13]\, - vaddress_RNISFAKMI(14) => \vaddress_RNISFAKMI[14]\, - vaddress_RNIUFAKMI(15) => \vaddress_RNIUFAKMI[15]\, - vaddress_RNI0GAKMI(16) => \vaddress_RNI0GAKMI[16]\, - vaddress_RNI2GAKMI(17) => \vaddress_RNI2GAKMI[17]\, - vaddress_RNI4GAKMI(18) => \vaddress_RNI4GAKMI[18]\, - vaddress_RNI6GAKMI(19) => \vaddress_RNI6GAKMI[19]\, - vaddress_RNIQNAKMI(20) => \vaddress_RNIQNAKMI[20]\, - vaddress_RNISNAKMI(21) => \vaddress_RNISNAKMI[21]\, - vaddress_RNIUNAKMI(22) => \vaddress_RNIUNAKMI[22]\, - vaddress_RNI0OAKMI(23) => \vaddress_RNI0OAKMI[23]\, - ctx(7) => \ctx[7]\, ctx(6) => \ctx[6]\, ctx(5) => - \ctx[5]\, ctx(4) => \ctx[4]\, ctx(3) => \ctx[3]\, ctx(2) - => \ctx[2]\, ctx(1) => \ctx[1]\, ctx(0) => \ctx[0]\, - dataout_2(31) => \dataout_2[31]\, dataout_2(30) => - \dataout_2[30]\, dataout_2(29) => \dataout_2[29]\, - dataout_2(28) => \dataout_2[28]\, dataout_2(27) => - \dataout_2[27]\, dataout_2(26) => \dataout_2[26]\, - dataout_2(25) => \dataout_2[25]\, dataout_2(24) => - \dataout_2[24]\, dataout_2(23) => \dataout_2[23]\, - dataout_2(22) => \dataout_2[22]\, dataout_2(21) => - \dataout_2[21]\, dataout_2(20) => \dataout_2[20]\, - dataout_2(19) => \dataout_2[19]\, dataout_2(18) => - \dataout_2[18]\, dataout_2(17) => \dataout_2[17]\, - dataout_2(16) => \dataout_2[16]\, dataout_2(15) => - \dataout_2[15]\, dataout_2(14) => \dataout_2[14]\, - dataout_2(13) => \dataout_2[13]\, dataout_2(12) => - \dataout_2[12]\, dataout_2(11) => \dataout_2[11]\, - dataout_2(10) => \dataout_2[10]\, dataout_2(9) => - \dataout_2[9]\, dataout_2(8) => \dataout_2[8]\, - dataout_2(7) => \dataout_2[7]\, dataout_2(6) => - \dataout_2[6]\, dataout_2(5) => \dataout_2[5]\, - dataout_2(4) => \dataout_2[4]\, dataout_2(3) => - \dataout_2[3]\, dataout_2(2) => \dataout_2[2]\, - dataout_2(1) => \dataout_2[1]\, dataout_2(0) => - \dataout_2[0]\, dataout_1(31) => \dataout_1[31]\, - dataout_1(30) => \dataout_1[30]\, dataout_1(29) => - \dataout_1[29]\, dataout_1(28) => \dataout_1[28]\, - dataout_1(27) => \dataout_1[27]\, dataout_1(26) => - \dataout_1[26]\, dataout_1(25) => \dataout_1[25]\, - dataout_1(24) => \dataout_1[24]\, dataout_1(23) => - \dataout_1[23]\, dataout_1(22) => \dataout_1[22]\, - dataout_1(21) => \dataout_1[21]\, dataout_1(20) => - \dataout_1[20]\, dataout_1(19) => \dataout_1[19]\, - dataout_1(18) => \dataout_1[18]\, dataout_1(17) => - \dataout_1[17]\, dataout_1(16) => \dataout_1[16]\, - dataout_1(15) => \dataout_1[15]\, dataout_1(14) => - \dataout_1[14]\, dataout_1(13) => \dataout_1[13]\, - dataout_1(12) => \dataout_1[12]\, dataout_1(11) => - \dataout_1[11]\, dataout_1(10) => \dataout_1[10]\, - dataout_1(9) => \dataout_1[9]\, dataout_1(8) => - \dataout_1[8]\, dataout_1(7) => \dataout_1[7]\, - dataout_1(6) => \dataout_1[6]\, dataout_1(5) => - \dataout_1[5]\, dataout_1(4) => \dataout_1[4]\, - dataout_1(3) => \dataout_1[3]\, dataout_1(2) => - \dataout_1[2]\, dataout_1(1) => \dataout_1[1]\, - dataout_1(0) => \dataout_1[0]\, dataout_0(35) => - \dataout_0[35]\, dataout_0(34) => \dataout_0[34]\, - dataout_0(33) => \dataout_0[33]\, dataout_0(32) => - \dataout_0[32]\, dataout_0(31) => \dataout_0[31]\, - dataout_0(30) => \dataout_0[30]\, dataout_0(29) => - \dataout_0[29]\, dataout_0(28) => \dataout_0[28]\, - dataout_0(27) => \dataout_0[27]\, dataout_0(26) => - \dataout_0[26]\, dataout_0(25) => \dataout_0[25]\, - dataout_0(24) => \dataout_0[24]\, dataout_0(23) => - \dataout_0[23]\, dataout_0(22) => \dataout_0[22]\, - dataout_0(21) => \dataout_0[21]\, dataout_0(20) => - \dataout_0[20]\, dataout_0(19) => \dataout_0[19]\, - dataout_0(18) => \dataout_0[18]\, dataout_0(17) => - \dataout_0[17]\, dataout_0(16) => \dataout_0[16]\, - dataout_0(15) => \dataout_0[15]\, dataout_0(14) => - \dataout_0[14]\, dataout_0(13) => \dataout_0[13]\, - dataout_0(12) => \dataout_0[12]\, dataout_0(11) => - \dataout_0[11]\, dataout_0(10) => \dataout_0[10]\, - dataout_0(9) => \dataout_0[9]\, dataout_0(8) => - \dataout_0[8]\, dataout_0(7) => \dataout_0[7]\, - dataout_0(6) => \dataout_0[6]\, dataout_0(5) => - \dataout_0[5]\, dataout_0(4) => \dataout_0[4]\, - dataout_0(3) => \dataout_0[3]\, dataout_0(2) => - \dataout_0[2]\, dataout_0(1) => \dataout_0[1]\, - dataout_0(0) => \dataout_0[0]\, vitdatain_0_1_0(22) => - \vitdatain_0_1_0[22]\, un1_p0_2_0_0 => \un1_p0_2_0[148]\, - un1_p0_2_0_350 => \un1_p0_2_0[498]\, dci_m_6 => - \dci_m[102]\, dci_m_0 => \dci_m[96]\, dci_m_1 => - \dci_m[97]\, dci_m_2 => \dci_m[98]\, dci_m_3 => - \dci_m[99]\, dci_m_5 => \dci_m[101]\, N_10 => N_10, - read_RNI0IQ7R => read_RNI0IQ7R, read_RNIRO4K31 => - read_RNIRO4K31, read_RNIQFOD21 => read_RNIQFOD21, - read_RNIFPFT31 => read_RNIFPFT31, read_RNIQPCQ11 => - read_RNIQPCQ11, read_RNI8DFM31 => read_RNI8DFM31, - read_RNIAQJ831 => read_RNIAQJ831, read_RNI76N8R => - read_RNI76N8R, read_RNI7G7G41 => read_RNI7G7G41, - read_RNIEKS231 => read_RNIEKS231, read_RNIMJHQT => - read_RNIMJHQT, read_RNIL633F1 => read_RNIL633F1, - read_RNIQH64D1 => read_RNIQH64D1, read_RNICAQK41 => - read_RNICAQK41, read_RNIQMJI41 => read_RNIQMJI41, - read_RNISLPNU => read_RNISLPNU, read_RNICKHE91 => - read_RNICKHE91, read_RNIC70OF1 => read_RNIC70OF1, - read_RNIC9O9B1 => read_RNIC9O9B1, read_RNI75LJ31 => - read_RNI75LJ31, read_RNIEEGDD1 => read_RNIEEGDD1, - N_3254_0 => N_3254_0, N_330 => N_330, N_267 => N_267, - N_329 => N_329, N_144 => N_144, N_3846 => N_3846, N_270 - => N_270, N_269 => N_269, N_24 => N_24, N_26 => N_26, - N_12_i_0 => N_12_i_0, flush_RNIJEN4SI3 => - flush_RNIJEN4SI3, flush_RNIGUM2OH3 => flush_RNIGUM2OH3, - N_16_i_0 => N_16_i_0, N_3239_i_0 => N_3239_i_0, - flush_0_1_RNIBUA27S2 => flush_0_1_RNIBUA27S2, - flush_0_1_RNIOMB27S2 => flush_0_1_RNIOMB27S2, - flush_0_1_RNIPTA27S2 => flush_0_1_RNIPTA27S2, - flush_RNIGBB873 => flush_RNIGBB873, N_980 => N_980, N_981 - => N_981, N_983 => N_983, N_982 => N_982, N_985 => N_985, - N_986 => N_986, flush2 => flush2, N_987 => N_987, N_984 - => N_984, lclk_c => lclk_c, flush2_0_0_RNIPJ5O2 => - flush2_0_0_RNIPJ5O2, flush2_0_0_RNITR5O2 => - flush2_0_0_RNITR5O2, flush2_0_0_RNIVV5O2 => - flush2_0_0_RNIVV5O2, flush2_0_0_RNI146O2 => - flush2_0_0_RNI146O2, flush2_RNIFMGM2 => flush2_RNIFMGM2, - flush2_0_0_RNI7G6O2 => flush2_0_0_RNI7G6O2, cachemem_VCC - => leon3s_VCC, flush2_RNI5I3N7 => flush2_RNI5I3N7, - un1_ici => un1_ici, N_258 => N_258, N_259 => N_259); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - p0 : proc3 - port map(istate_RNIJCMP6(0) => \istate_RNIJCMP6[0]\, - faddr_RNIUT72LB(3) => \faddr_RNIUT72LB[3]\, - vaddress_RNISNAKMI(21) => \vaddress_RNISNAKMI[21]\, - vaddress_RNI6GAKMI(19) => \vaddress_RNI6GAKMI[19]\, - faddr_RNISJSHQA(2) => \faddr_RNISJSHQA[2]\, - vaddress_RNIQNAKMI(20) => \vaddress_RNIQNAKMI[20]\, - faddr_RNI7UFASD(5) => \faddr_RNI7UFASD[5]\, - faddr_RNI0FOJNE(4) => \faddr_RNI0FOJNE[4]\, - faddr_RNIDN2CUE(6) => \faddr_RNIDN2CUE[6]\, - faddr_RNIKVTLT9(1) => \faddr_RNIKVTLT9[1]\, - vaddress_RNI0GAKMI(16) => \vaddress_RNI0GAKMI[16]\, - vaddress_RNI0OAKMI(23) => \vaddress_RNI0OAKMI[23]\, - vaddress_RNIOFAKMI(12) => \vaddress_RNIOFAKMI[12]\, - vaddress_RNIJG6QR7(4) => \vaddress_RNIJG6QR7[4]\, - un1_p0_2_i_4 => \un1_p0_2_i[121]\, un1_p0_2_i_0 => - \un1_p0_2_i[117]\, ctx(7) => \ctx[7]\, ctx(6) => \ctx[6]\, - ctx(5) => \ctx[5]\, ctx(4) => \ctx[4]\, ctx(3) => - \ctx[3]\, ctx(2) => \ctx[2]\, ctx(1) => \ctx[1]\, ctx(0) - => \ctx[0]\, istate_RNI6HPAI(0) => \istate_RNI6HPAI[0]\, - istate_RNIAJH4F(0) => \istate_RNIAJH4F[0]\, - vaddress_RNIUNAKMI(22) => \vaddress_RNIUNAKMI[22]\, - vaddress_RNISFAKMI(14) => \vaddress_RNISFAKMI[14]\, - istate_RNI57KLB(0) => \istate_RNI57KLB[0]\, - istate_RNIUCOFG(0) => \istate_RNIUCOFG[0]\, - faddr_RNI7H6KT8(0) => \faddr_RNI7H6KT8[0]\, - istate_RNIH0NBI(0) => \istate_RNIH0NBI[0]\, - istate_RNIG7IIA(0) => \istate_RNIG7IIA[0]\, - vaddress_RNIFCB8U6(3) => \vaddress_RNIFCB8U6[3]\, - istate_RNI2MM6D(0) => \istate_RNI2MM6D[0]\, - istate_RNI8BL1A(0) => \istate_RNI8BL1A[0]\, - istate_RNILTAC8(0) => \istate_RNILTAC8[0]\, - istate_RNIK9NF8(0) => \istate_RNIK9NF8[0]\, - vaddress_RNI4GAKMI(18) => \vaddress_RNI4GAKMI[18]\, - vaddress_RNI2GAKMI(17) => \vaddress_RNI2GAKMI[17]\, - istate_RNI5V68H(0) => \istate_RNI5V68H[0]\, - istate_RNIM2DE7(0) => \istate_RNIM2DE7[0]\, - istate_RNIVTQIJ(0) => \istate_RNIVTQIJ[0]\, - istate_RNIOVC5J(0) => \istate_RNIOVC5J[0]\, - istate_RNI6PSS1(0) => \istate_RNI6PSS1[0]\, - istate_RNIGUTA8(0) => \istate_RNIGUTA8[0]\, - istate_RNIMRTH8(0) => \istate_RNIMRTH8[0]\, - vaddress_RNIQFAKMI(13) => \vaddress_RNIQFAKMI[13]\, - istate_RNIAP6PI(0) => \istate_RNIAP6PI[0]\, - istate_RNIENB3M(0) => \istate_RNIENB3M[0]\, - istate_RNIS4VK8(0) => \istate_RNIS4VK8[0]\, - istate_RNIRASC8(0) => \istate_RNIRASC8[0]\, - istate_RNIJSOBE(0) => \istate_RNIJSOBE[0]\, - istate_RNIR2JU8(0) => \istate_RNIR2JU8[0]\, - istate_RNIOJJE1(0) => \istate_RNIOJJE1[0]\, - istate_RNIN6957(0) => \istate_RNIN6957[0]\, - istate_RNIKJBN8(0) => \istate_RNIKJBN8[0]\, - istate_RNI6LOO6(0) => \istate_RNI6LOO6[0]\, - istate_RNIV33V9(0) => \istate_RNIV33V9[0]\, - istate_RNI7BUID(0) => \istate_RNI7BUID[0]\, - istate_RNIEC82C(0) => \istate_RNIEC82C[0]\, - istate_RNIPSU8G(0) => \istate_RNIPSU8G[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_6 => hrdata_6, hrdata_5 - => hrdata_5, hrdata_7 => hrdata_7, hrdata_4 => hrdata_4, - hrdata_3 => hrdata_3, hrdata_2 => hrdata_2, hrdata_27 => - hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => hrdata_23, - hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, hrdata_18 - => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 => - hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => hrdata_8, - hrdata_1 => hrdata_1, hrdata_0_d0 => hrdata_0_d0, - hrdata_24 => hrdata_24, hrdata_17 => hrdata_17, hrdata_14 - => hrdata_14, hrdata_13 => hrdata_13, hrdata_11 => - hrdata_11, hrdata_10 => hrdata_10, hrdata_9 => hrdata_9, - vaddress_RNI8EVQ36(2) => \vaddress_RNI8EVQ36[2]\, - hrdata_0_3 => hrdata_0_3, hrdata_0_24 => hrdata_0_24, - hrdata_0_4 => hrdata_0_4, hrdata_0_18 => hrdata_0_18, - hrdata_0_17 => hrdata_0_17, hrdata_0_16 => hrdata_0_16, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_14 => hrdata_0_14, hrdata_0_13 => hrdata_0_13, - hrdata_0_9 => hrdata_0_9, hrdata_0_8 => hrdata_0_8, - hrdata_0_21 => hrdata_0_21, hrdata_0_27 => hrdata_0_27, - hrdata_0_12 => hrdata_0_12, hrdata_0_11 => hrdata_0_11, - hrdata_0_10 => hrdata_0_10, hrdata_0_7 => hrdata_0_7, - hrdata_0_1 => hrdata_0_1, hrdata_0_2 => hrdata_0_2, - hrdata_0_26 => hrdata_0_26, hrdata_0_0 => hrdata_0_0, - hrdata_0_15 => hrdata_0_15, istate_RNIA8N5H(0) => - \istate_RNIA8N5H[0]\, vaddress_RNIUFAKMI(15) => - \vaddress_RNIUFAKMI[15]\, vitdatain_0_1_0(22) => - \vitdatain_0_1_0[22]\, dataout_1(31) => \dataout_1[31]\, - dataout_1(30) => \dataout_1[30]\, dataout_1(29) => - \dataout_1[29]\, dataout_1(28) => \dataout_1[28]\, - dataout_1(27) => \dataout_1[27]\, dataout_1(26) => - \dataout_1[26]\, dataout_1(25) => \dataout_1[25]\, - dataout_1(24) => \dataout_1[24]\, dataout_1(23) => - \dataout_1[23]\, dataout_1(22) => \dataout_1[22]\, - dataout_1(21) => \dataout_1[21]\, dataout_1(20) => - \dataout_1[20]\, dataout_1(19) => \dataout_1[19]\, - dataout_1(18) => \dataout_1[18]\, dataout_1(17) => - \dataout_1[17]\, dataout_1(16) => \dataout_1[16]\, - dataout_1(15) => \dataout_1[15]\, dataout_1(14) => - \dataout_1[14]\, dataout_1(13) => \dataout_1[13]\, - dataout_1(12) => \dataout_1[12]\, dataout_1(11) => - \dataout_1[11]\, dataout_1(10) => \dataout_1[10]\, - dataout_1(9) => \dataout_1[9]\, dataout_1(8) => - \dataout_1[8]\, dataout_1(7) => \dataout_1[7]\, - dataout_1(6) => \dataout_1[6]\, dataout_1(5) => - \dataout_1[5]\, dataout_1(4) => \dataout_1[4]\, - dataout_1(3) => \dataout_1[3]\, dataout_1(2) => - \dataout_1[2]\, dataout_1(1) => \dataout_1[1]\, - dataout_1(0) => \dataout_1[0]\, dataout_0(35) => - \dataout_0[35]\, dataout_0(34) => \dataout_0[34]\, - dataout_0(33) => \dataout_0[33]\, dataout_0(32) => - \dataout_0[32]\, dataout_0(31) => \dataout_0[31]\, - dataout_0(30) => \dataout_0[30]\, dataout_0(29) => - \dataout_0[29]\, dataout_0(28) => \dataout_0[28]\, - dataout_0(27) => \dataout_0[27]\, dataout_0(26) => - \dataout_0[26]\, dataout_0(25) => \dataout_0[25]\, - dataout_0(24) => \dataout_0[24]\, dataout_0(23) => - \dataout_0[23]\, dataout_0(22) => \dataout_0[22]\, - dataout_0(21) => \dataout_0[21]\, dataout_0(20) => - \dataout_0[20]\, dataout_0(19) => \dataout_0[19]\, - dataout_0(18) => \dataout_0[18]\, dataout_0(17) => - \dataout_0[17]\, dataout_0(16) => \dataout_0[16]\, - dataout_0(15) => \dataout_0[15]\, dataout_0(14) => - \dataout_0[14]\, dataout_0(13) => \dataout_0[13]\, - dataout_0(12) => \dataout_0[12]\, dataout_0(11) => - \dataout_0[11]\, dataout_0(10) => \dataout_0[10]\, - dataout_0(9) => \dataout_0[9]\, dataout_0(8) => - \dataout_0[8]\, dataout_0(7) => \dataout_0[7]\, - dataout_0(6) => \dataout_0[6]\, dataout_0(5) => - \dataout_0[5]\, dataout_0(4) => \dataout_0[4]\, - dataout_0(3) => \dataout_0[3]\, dataout_0(2) => - \dataout_0[2]\, dataout_0(1) => \dataout_0[1]\, - dataout_0(0) => \dataout_0[0]\, dataout_2(31) => - \dataout_2[31]\, dataout_2(30) => \dataout_2[30]\, - dataout_2(29) => \dataout_2[29]\, dataout_2(28) => - \dataout_2[28]\, dataout_2(27) => \dataout_2[27]\, - dataout_2(26) => \dataout_2[26]\, dataout_2(25) => - \dataout_2[25]\, dataout_2(24) => \dataout_2[24]\, - dataout_2(23) => \dataout_2[23]\, dataout_2(22) => - \dataout_2[22]\, dataout_2(21) => \dataout_2[21]\, - dataout_2(20) => \dataout_2[20]\, dataout_2(19) => - \dataout_2[19]\, dataout_2(18) => \dataout_2[18]\, - dataout_2(17) => \dataout_2[17]\, dataout_2(16) => - \dataout_2[16]\, dataout_2(15) => \dataout_2[15]\, - dataout_2(14) => \dataout_2[14]\, dataout_2(13) => - \dataout_2[13]\, dataout_2(12) => \dataout_2[12]\, - dataout_2(11) => \dataout_2[11]\, dataout_2(10) => - \dataout_2[10]\, dataout_2(9) => \dataout_2[9]\, - dataout_2(8) => \dataout_2[8]\, dataout_2(7) => - \dataout_2[7]\, dataout_2(6) => \dataout_2[6]\, - dataout_2(5) => \dataout_2[5]\, dataout_2(4) => - \dataout_2[4]\, dataout_2(3) => \dataout_2[3]\, - dataout_2(2) => \dataout_2[2]\, dataout_2(1) => - \dataout_2[1]\, dataout_2(0) => \dataout_2[0]\, - un1_p0_2_0_0 => \un1_p0_2_0[148]\, un1_p0_2_0_350 => - \un1_p0_2_0[498]\, data_1_21 => data_24, data_1_16 => - data_19, data_1_5 => data_8, data_1_0 => data_3, data_1_2 - => data_5, faddr_RNIB0UOO(2) => \faddr_RNIB0UOO[2]\, - dstate_i_RNI29QQ7J3(8) => \dstate_i_RNI29QQ7J3[8]\, - xaddress_RNITFTTE(3) => \xaddress_RNITFTTE[3]\, - xaddress_RNIFP43F(2) => \xaddress_RNIFP43F[2]\, size_0(0) - => size(0), faddr_RNI7MK691(6) => \faddr_RNI7MK691[6]\, - dci_m_6 => \dci_m[102]\, dci_m_5 => \dci_m[101]\, dci_m_3 - => \dci_m[99]\, dci_m_2 => \dci_m[98]\, dci_m_1 => - \dci_m[97]\, dci_m_0 => \dci_m[96]\, faddr_RNI7879K(0) - => \faddr_RNI7879K[0]\, faddr_RNIEHR0O(1) => - \faddr_RNIEHR0O[1]\, dstate_RNIC3QA81(1) => - \dstate_RNIC3QA81[1]\, dstate_RNIFPT581(1) => - \dstate_RNIFPT581[1]\, dstate_i_0_RNIH0PPES(8) => - \dstate_i_0_RNIH0PPES[8]\, dstate_RNI1G47MJ(1) => - \dstate_RNI1G47MJ[1]\, dstate_RNIFS6E51(1) => - \dstate_RNIFS6E51[1]\, xaddress_RNI1Q9ST1(1) => - \xaddress_RNI1Q9ST1[1]\, xaddress_RNIEHIUT1(1) => - \xaddress_RNIEHIUT1[1]\, xaddress_RNILHOK61(1) => - \xaddress_RNILHOK61[1]\, xaddress_RNILK99L1(1) => - \xaddress_RNILK99L1[1]\, xaddress_RNI1I3MQ1(0) => - \xaddress_RNI1I3MQ1[0]\, xaddress_RNIK99NK1(1) => - \xaddress_RNIK99NK1[1]\, xaddress_RNIP2BVK1(1) => - \xaddress_RNIP2BVK1[1]\, xaddress_RNIJI2O22(1) => - \xaddress_RNIJI2O22[1]\, xaddress_RNITMH17S2(12) => - \xaddress_RNITMH17S2[12]\, xaddress_RNICFI17S2(13) => - \xaddress_RNICFI17S2[13]\, xaddress_RNI1D927S2(20) => - \xaddress_RNI1D927S2[20]\, xaddress_RNI9MB27S2(23) => - \xaddress_RNI9MB27S2[23]\, xaddress_RNI0GI17S2(17) => - \xaddress_RNI0GI17S2[17]\, xaddress_RNIC5A27S2(21) => - \xaddress_RNIC5A27S2[21]\, xaddress_RNIN7J17S2(14) => - \xaddress_RNIN7J17S2[14]\, xaddress_RNIID927S2(16) => - \xaddress_RNIID927S2[16]\, xaddress_RNI2MB27S2(15) => - \xaddress_RNI2MB27S2[15]\, dstate_i_0_RNIL7FGFS(8) => - \dstate_i_0_RNIL7FGFS[8]\, xaddress_RNID252J1(10) => - \xaddress_RNID252J1[10]\, newtag_1_0(27) => - \newtag_1_0[27]\, newtag_1_0(26) => \newtag_1_0[26]\, - newtag_1_0(25) => \newtag_1_0[25]\, newtag_1_0(24) => - \newtag_1_0[24]\, dataout(35) => \dataout[35]\, - dataout(34) => \dataout[34]\, dataout(33) => - \dataout[33]\, dataout(32) => \dataout[32]\, dataout(31) - => \dataout[31]\, dataout(30) => \dataout[30]\, - dataout(29) => \dataout[29]\, dataout(28) => - \dataout[28]\, dataout(27) => \dataout[27]\, dataout(26) - => \dataout[26]\, dataout(25) => \dataout[25]\, - dataout(24) => \dataout[24]\, dataout(23) => - \dataout[23]\, dataout(22) => \dataout[22]\, dataout(21) - => \dataout[21]\, dataout(20) => \dataout[20]\, - dataout(19) => \dataout[19]\, dataout(18) => - \dataout[18]\, dataout(17) => \dataout[17]\, dataout(16) - => \dataout[16]\, dataout(15) => \dataout[15]\, - dataout(14) => \dataout[14]\, dataout(13) => - \dataout[13]\, dataout(12) => \dataout[12]\, dataout(11) - => \dataout[11]\, dataout(10) => \dataout[10]\, - dataout(9) => \dataout[9]\, dataout(8) => \dataout[8]\, - dataout(7) => \dataout[7]\, dataout(6) => \dataout[6]\, - dataout(5) => \dataout[5]\, dataout(4) => \dataout[4]\, - dataout(3) => \dataout[3]\, dataout(2) => \dataout[2]\, - dataout(1) => \dataout[1]\, dataout(0) => \dataout[0]\, - address(1) => address(1), address(0) => address(0), - addr(30) => \addr[30]\, iosn_2(93) => iosn_2(93), - hresp(0) => hresp(0), hgrant(0) => hgrant(0), hsize_5(1) - => hsize_5(1), iosn_1(93) => iosn_1(93), hwdata_15 => - hwdata_15, hwdata_0 => hwdata_0, hwdata_14 => hwdata_14, - hwdata_1 => hwdata_1, hwdata_28 => hwdata_28, hwdata_23 - => hwdata_23, hwdata_12 => hwdata_12, hwdata_4 => - hwdata_4, hwdata_13 => hwdata_13, hwdata_27 => hwdata_27, - hwdata_25 => hwdata_25, hwdata_11 => hwdata_11, hwdata_9 - => hwdata_9, hwdata_3 => hwdata_3, hwdata_16 => - hwdata_16, haddr(31) => haddr(31), haddr(30) => haddr(30), - haddr(29) => haddr(29), haddr(28) => haddr(28), haddr(27) - => haddr(27), haddr(26) => haddr(26), haddr(25) => - haddr(25), haddr(24) => haddr(24), haddr(23) => haddr(23), - haddr(22) => haddr(22), haddr(21) => haddr(21), haddr(20) - => haddr(20), haddr(19) => haddr(19), haddr(18) => - haddr(18), haddr(17) => haddr(17), haddr(16) => haddr(16), - haddr(15) => haddr(15), haddr(14) => haddr(14), haddr(13) - => haddr(13), haddr(12) => haddr(12), haddr(11) => - haddr(11), haddr(10) => haddr(10), haddr(9) => haddr(9), - haddr(8) => haddr(8), haddr(7) => haddr(7), haddr(6) => - haddr(6), haddr(5) => haddr(5), haddr(4) => haddr(4), - haddr(3) => haddr(3), haddr(2) => haddr(2), htrans_tz(1) - => htrans_tz(1), iosn_0(93) => iosn_0(93), htrans(1) => - htrans(1), nbo_5_0(1) => nbo_5_0(1), nbo_5_0(0) => - nbo_5_0(0), data_0 => data_0_d0, data_3 => data_0_0, - data_5 => data_0_2, data_8 => data_0_5, data_19 => - data_0_16, data_24 => data_0_21, hrdata_1_0_1(1) => - hrdata_1_0_1(1), data1(31) => \data1[31]\, data1(30) => - \data1[30]\, data1(29) => \data1[29]\, data1(28) => - \data1[28]\, data1(27) => \data1[27]\, data1(26) => - \data1[26]\, data1(25) => \data1[25]\, data1(24) => - \data1[24]\, data1(23) => \data1[23]\, data1(22) => - \data1[22]\, data1(21) => \data1[21]\, data1(20) => - \data1[20]\, data1(19) => \data1[19]\, data1(18) => - \data1[18]\, data1(17) => \data1[17]\, data1(16) => - \data1[16]\, data1(15) => \data1[15]\, data1(14) => - \data1[14]\, data1(13) => \data1[13]\, data1(12) => - \data1[12]\, data1(11) => \data1[11]\, data1(10) => - \data1[10]\, data1(9) => \data1[9]\, data1(8) => - \data1[8]\, data1(7) => \data1[7]\, data1(6) => - \data1[6]\, data1(5) => \data1[5]\, data1(4) => - \data1[4]\, data1(3) => \data1[3]\, data1(2) => - \data1[2]\, data1(1) => \data1[1]\, data1(0) => - \data1[0]\, maddress_28 => \maddress[28]\, data2(31) => - \data2[31]\, data2(30) => \data2[30]\, data2(29) => - \data2[29]\, data2(28) => \data2[28]\, data2(27) => - \data2[27]\, data2(26) => \data2[26]\, data2(25) => - \data2[25]\, data2(24) => \data2[24]\, data2(23) => - \data2[23]\, data2(22) => \data2[22]\, data2(21) => - \data2[21]\, data2(20) => \data2[20]\, data2(19) => - \data2[19]\, data2(18) => \data2[18]\, data2(17) => - \data2[17]\, data2(16) => \data2[16]\, data2(15) => - \data2[15]\, data2(14) => \data2[14]\, data2(13) => - \data2[13]\, data2(12) => \data2[12]\, data2(11) => - \data2[11]\, data2(10) => \data2[10]\, data2(9) => - \data2[9]\, data2(8) => \data2[8]\, data2(7) => - \data2[7]\, data2(6) => \data2[6]\, data2(5) => - \data2[5]\, data2(4) => \data2[4]\, data2(3) => - \data2[3]\, data2(2) => \data2[2]\, data2(1) => - \data2[1]\, data2(0) => \data2[0]\, irl_0(3) => irl(3), - irl_0(2) => irl(2), irl_0(1) => irl(1), irl_0(0) => - irl(0), irl(3) => irl_0(3), irl(2) => irl_0(2), irl(1) - => irl_0(1), irl(0) => irl_0(0), edata2_iv_i_0_7 => - \edata2_iv_i_0[31]\, raddr1(7) => \raddr1[7]\, raddr1(6) - => \raddr1[6]\, raddr1(5) => \raddr1[5]\, raddr1(4) => - \raddr1[4]\, raddr1(3) => \raddr1[3]\, raddr1(2) => - \raddr1[2]\, raddr1(1) => \raddr1[1]\, raddr1(0) => - \raddr1[0]\, rfa1(7) => \rfa1[7]\, rfa1(6) => \rfa1[6]\, - rfa1(5) => \rfa1[5]\, rfa1(4) => \rfa1[4]\, rfa1(3) => - \rfa1[3]\, rfa1(2) => \rfa1[2]\, rfa1(1) => \rfa1[1]\, - rfa1(0) => \rfa1[0]\, raddr2(7) => \raddr2[7]\, raddr2(6) - => \raddr2[6]\, raddr2(5) => \raddr2[5]\, raddr2(4) => - \raddr2[4]\, raddr2(3) => \raddr2[3]\, raddr2(2) => - \raddr2[2]\, raddr2(1) => \raddr2[1]\, raddr2(0) => - \raddr2[0]\, rfa2(7) => \rfa2[7]\, rfa2(6) => \rfa2[6]\, - rfa2(5) => \rfa2[5]\, rfa2(4) => \rfa2[4]\, rfa2(3) => - \rfa2[3]\, rfa2(2) => \rfa2[2]\, rfa2(1) => \rfa2[1]\, - rfa2(0) => \rfa2[0]\, waddr(7) => \waddr[7]\, waddr(6) - => \waddr[6]\, waddr(5) => \waddr[5]\, waddr(4) => - \waddr[4]\, waddr(3) => \waddr[3]\, waddr(2) => - \waddr[2]\, waddr(1) => \waddr[1]\, waddr(0) => - \waddr[0]\, wdata(31) => \wdata[31]\, wdata(30) => - \wdata[30]\, wdata(29) => \wdata[29]\, wdata(28) => - \wdata[28]\, wdata(27) => \wdata[27]\, wdata(26) => - \wdata[26]\, wdata(25) => \wdata[25]\, wdata(24) => - \wdata[24]\, wdata(23) => \wdata[23]\, wdata(22) => - \wdata[22]\, wdata(21) => \wdata[21]\, wdata(20) => - \wdata[20]\, wdata(19) => \wdata[19]\, wdata(18) => - \wdata[18]\, wdata(17) => \wdata[17]\, wdata(16) => - \wdata[16]\, wdata(15) => \wdata[15]\, wdata(14) => - \wdata[14]\, wdata(13) => \wdata[13]\, wdata(12) => - \wdata[12]\, wdata(11) => \wdata[11]\, wdata(10) => - \wdata[10]\, wdata(9) => \wdata[9]\, wdata(8) => - \wdata[8]\, wdata(7) => \wdata[7]\, wdata(6) => - \wdata[6]\, wdata(5) => \wdata[5]\, wdata(4) => - \wdata[4]\, wdata(3) => \wdata[3]\, wdata(2) => - \wdata[2]\, wdata(1) => \wdata[1]\, wdata(0) => - \wdata[0]\, flush2_RNIFMGM2 => flush2_RNIFMGM2, - flush2_RNI5I3N7 => flush2_RNI5I3N7, N_984 => N_984, N_980 - => N_980, N_987 => N_987, N_986 => N_986, flush2 => - flush2, flush2_0_0_RNI146O2 => flush2_0_0_RNI146O2, - flush2_0_0_RNI7G6O2 => flush2_0_0_RNI7G6O2, - flush2_0_0_RNIVV5O2 => flush2_0_0_RNIVV5O2, - flush2_0_0_RNITR5O2 => flush2_0_0_RNITR5O2, - flush2_0_0_RNIPJ5O2 => flush2_0_0_RNIPJ5O2, N_981 => - N_981, N_985 => N_985, N_983 => N_983, N_982 => N_982, - N_264_0 => N_264_0, N_262_0 => N_262_0, N_78_0 => N_78_0, - un1_ici => un1_ici, N_10 => N_10, flush_RNIJEN4SI3 => - flush_RNIJEN4SI3, flush_RNIGBB873 => flush_RNIGBB873, - N_270 => N_270, N_269 => N_269, N_267 => N_267, N_259 => - N_259, N_258 => N_258, N_144 => N_144, N_3846 => N_3846, - read_RNIQH64D1 => read_RNIQH64D1, read_RNIQPCQ11 => - read_RNIQPCQ11, read_RNIRO4K31 => read_RNIRO4K31, - read_RNI0IQ7R => read_RNI0IQ7R, read_RNIQFOD21 => - read_RNIQFOD21, read_RNI8DFM31 => read_RNI8DFM31, - read_RNIAQJ831 => read_RNIAQJ831, read_RNI76N8R => - read_RNI76N8R, read_RNI7G7G41 => read_RNI7G7G41, - read_RNIMJHQT => read_RNIMJHQT, read_RNIL633F1 => - read_RNIL633F1, read_RNICKHE91 => read_RNICKHE91, - flush_0_1_RNIOMB27S2 => flush_0_1_RNIOMB27S2, un59_nbo - => un59_nbo, N_3239_i_0 => N_3239_i_0, N_26_0 => N_26, - read_RNIEKS231 => read_RNIEKS231, read_RNIFPFT31 => - read_RNIFPFT31, read_RNIC9O9B1 => read_RNIC9O9B1, - flush_RNIGUM2OH3 => flush_RNIGUM2OH3, read_RNICAQK41 => - read_RNICAQK41, read_RNIQMJI41 => read_RNIQMJI41, - read_RNISLPNU => read_RNISLPNU, read_RNIC70OF1 => - read_RNIC70OF1, read_RNI75LJ31 => read_RNI75LJ31, - read_RNIEEGDD1 => read_RNIEEGDD1, N_12_i_0 => N_12_i_0, - N_16_i_0 => N_16_i_0, flush_0_1_RNIBUA27S2 => - flush_0_1_RNIBUA27S2, flush_0_1_RNIPTA27S2 => - flush_0_1_RNIPTA27S2, N_24 => N_24, N_329 => N_329, N_330 - => N_330, N_3254_0 => N_3254_0, htrans_0_sqmuxa_2 => - htrans_0_sqmuxa_2, N_466 => N_466, hwrite_1_m_0 => - hwrite_1_m_0, N_468 => N_468, N_463 => N_463, N_461 => - N_461, N_459 => N_459, N_458 => N_458, bo_5842_d => - bo_5842_d, N_139 => N_139, N_138 => N_138, un91_nbo_i_0 - => un91_nbo_i_0, werr_2_m_0 => werr_2_m_0, N_467 => - N_467, N_462 => N_462, N_457 => N_457, un60_nbo => - un60_nbo, hbusreq => hbusreq, lb_0_sqmuxa_1 => - lb_0_sqmuxa_1, N_5054 => N_5054, hlock => hlock, - un1_htrans_1_sqmuxa_0 => un1_htrans_1_sqmuxa_0, - bo_5842_d_0 => bo_5842_d_0, N_78 => N_78, N_262 => N_262, - N_264 => N_264, proc3_VCC => leon3s_VCC, N_546 => N_546, - lclk_c => lclk_c, ra_bpmiss_1_0 => ra_bpmiss_1_0, rst => - \rst\, d_m5_0_a3_2 => d_m5_0_a3_2, rst_RNIINI1H => - \rst_RNIINI1H\, rstate_1188n => rstate_1188n, ren1 => - ren1, rfe1 => rfe1, wren => wren, intack => intack, ren2 - => ren2, rfe2 => rfe2, error_i_2 => error_i_2); - - VCC_i : VCC - port map(Y => \VCC\); - - rf0 : regfile_3p - port map(rfa2(7) => \rfa2[7]\, rfa2(6) => \rfa2[6]\, - rfa2(5) => \rfa2[5]\, rfa2(4) => \rfa2[4]\, rfa2(3) => - \rfa2[3]\, rfa2(2) => \rfa2[2]\, rfa2(1) => \rfa2[1]\, - rfa2(0) => \rfa2[0]\, data2(31) => \data2[31]\, data2(30) - => \data2[30]\, data2(29) => \data2[29]\, data2(28) => - \data2[28]\, data2(27) => \data2[27]\, data2(26) => - \data2[26]\, data2(25) => \data2[25]\, data2(24) => - \data2[24]\, data2(23) => \data2[23]\, data2(22) => - \data2[22]\, data2(21) => \data2[21]\, data2(20) => - \data2[20]\, data2(19) => \data2[19]\, data2(18) => - \data2[18]\, data2(17) => \data2[17]\, data2(16) => - \data2[16]\, data2(15) => \data2[15]\, data2(14) => - \data2[14]\, data2(13) => \data2[13]\, data2(12) => - \data2[12]\, data2(11) => \data2[11]\, data2(10) => - \data2[10]\, data2(9) => \data2[9]\, data2(8) => - \data2[8]\, data2(7) => \data2[7]\, data2(6) => - \data2[6]\, data2(5) => \data2[5]\, data2(4) => - \data2[4]\, data2(3) => \data2[3]\, data2(2) => - \data2[2]\, data2(1) => \data2[1]\, data2(0) => - \data2[0]\, raddr2(7) => \raddr2[7]\, raddr2(6) => - \raddr2[6]\, raddr2(5) => \raddr2[5]\, raddr2(4) => - \raddr2[4]\, raddr2(3) => \raddr2[3]\, raddr2(2) => - \raddr2[2]\, raddr2(1) => \raddr2[1]\, raddr2(0) => - \raddr2[0]\, rfa1(7) => \rfa1[7]\, rfa1(6) => \rfa1[6]\, - rfa1(5) => \rfa1[5]\, rfa1(4) => \rfa1[4]\, rfa1(3) => - \rfa1[3]\, rfa1(2) => \rfa1[2]\, rfa1(1) => \rfa1[1]\, - rfa1(0) => \rfa1[0]\, data1(31) => \data1[31]\, data1(30) - => \data1[30]\, data1(29) => \data1[29]\, data1(28) => - \data1[28]\, data1(27) => \data1[27]\, data1(26) => - \data1[26]\, data1(25) => \data1[25]\, data1(24) => - \data1[24]\, data1(23) => \data1[23]\, data1(22) => - \data1[22]\, data1(21) => \data1[21]\, data1(20) => - \data1[20]\, data1(19) => \data1[19]\, data1(18) => - \data1[18]\, data1(17) => \data1[17]\, data1(16) => - \data1[16]\, data1(15) => \data1[15]\, data1(14) => - \data1[14]\, data1(13) => \data1[13]\, data1(12) => - \data1[12]\, data1(11) => \data1[11]\, data1(10) => - \data1[10]\, data1(9) => \data1[9]\, data1(8) => - \data1[8]\, data1(7) => \data1[7]\, data1(6) => - \data1[6]\, data1(5) => \data1[5]\, data1(4) => - \data1[4]\, data1(3) => \data1[3]\, data1(2) => - \data1[2]\, data1(1) => \data1[1]\, data1(0) => - \data1[0]\, waddr(7) => \waddr[7]\, waddr(6) => - \waddr[6]\, waddr(5) => \waddr[5]\, waddr(4) => - \waddr[4]\, waddr(3) => \waddr[3]\, waddr(2) => - \waddr[2]\, waddr(1) => \waddr[1]\, waddr(0) => - \waddr[0]\, wdata(31) => \wdata[31]\, wdata(30) => - \wdata[30]\, wdata(29) => \wdata[29]\, wdata(28) => - \wdata[28]\, wdata(27) => \wdata[27]\, wdata(26) => - \wdata[26]\, wdata(25) => \wdata[25]\, wdata(24) => - \wdata[24]\, wdata(23) => \wdata[23]\, wdata(22) => - \wdata[22]\, wdata(21) => \wdata[21]\, wdata(20) => - \wdata[20]\, wdata(19) => \wdata[19]\, wdata(18) => - \wdata[18]\, wdata(17) => \wdata[17]\, wdata(16) => - \wdata[16]\, wdata(15) => \wdata[15]\, wdata(14) => - \wdata[14]\, wdata(13) => \wdata[13]\, wdata(12) => - \wdata[12]\, wdata(11) => \wdata[11]\, wdata(10) => - \wdata[10]\, wdata(9) => \wdata[9]\, wdata(8) => - \wdata[8]\, wdata(7) => \wdata[7]\, wdata(6) => - \wdata[6]\, wdata(5) => \wdata[5]\, wdata(4) => - \wdata[4]\, wdata(3) => \wdata[3]\, wdata(2) => - \wdata[2]\, wdata(1) => \wdata[1]\, wdata(0) => - \wdata[0]\, raddr1(7) => \raddr1[7]\, raddr1(6) => - \raddr1[6]\, raddr1(5) => \raddr1[5]\, raddr1(4) => - \raddr1[4]\, raddr1(3) => \raddr1[3]\, raddr1(2) => - \raddr1[2]\, raddr1(1) => \raddr1[1]\, raddr1(0) => - \raddr1[0]\, rfe2 => rfe2, ren2 => ren2, rfe1 => rfe1, - lclk_c => lclk_c, wren => wren, ren1 => ren1); - - rst_RNIINI1H : AO1B - port map(A => d_m5_0_a3_2, B => ra_bpmiss_1_0, C => \rst\, - Y => \rst_RNIINI1H\); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - rst_RNI55L3_0 : INV - port map(A => \rst\, Y => rstate_1188n); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity irqmp is - - port( irl_2 : out std_logic_vector(2 to 2); - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - pwdata_1_0 : in std_logic; - irl_3 : in std_logic; - irl_1 : in std_logic; - irl_0_d0 : in std_logic; - irl_0 : inout std_logic_vector(3 downto 0) := (others => 'Z'); - ipend_10 : out std_logic; - pwdata_4 : in std_logic; - pwdata_0_d0 : in std_logic; - pwdata_17 : in std_logic; - pwdata_21 : in std_logic; - pwdata_23 : in std_logic; - pwdata_26 : in std_logic; - pwdata_16 : in std_logic; - pwdata_18 : in std_logic; - pwdata_15 : in std_logic; - pwdata_25 : in std_logic; - pwdata_27 : in std_logic; - pwdata_28 : in std_logic; - pwdata_29 : in std_logic; - pwdata_20 : in std_logic; - pwdata_19 : in std_logic; - pwdata_24 : in std_logic; - pwdata_22 : in std_logic; - iforce_0_11 : out std_logic; - iforce_0_5 : out std_logic; - iforce_0_9 : out std_logic; - iforce_0_4 : out std_logic; - iforce_0_6 : out std_logic; - ipend_m : out std_logic_vector(4 to 4); - prdata_0 : out std_logic; - prdata_13 : out std_logic; - prdata_1 : out std_logic; - iforce_0_m : out std_logic_vector(4 to 4); - ilevel_5 : out std_logic; - ilevel_4 : out std_logic; - ilevel_6 : out std_logic; - ilevel_3 : out std_logic; - ilevel_11 : out std_logic; - ilevel_7 : out std_logic; - ilevel_9 : out std_logic; - prdata_11_m_1_0 : out std_logic_vector(4 to 4); - prdata_13_m_1_0 : out std_logic_vector(4 to 4); - paddr : in std_logic_vector(7 downto 3); - prdata_0_iv_0_0_0_12 : out std_logic; - prdata_0_iv_0_0_0_0 : out std_logic; - prdata_0_iv_0_0_0_13 : out std_logic; - prdata_0_iv_0_0_1_12 : out std_logic; - prdata_0_iv_0_0_1_0 : out std_logic; - prdata_0_iv_0_0_1_13 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 1); - pirq_10 : in std_logic; - pirq_11 : in std_logic; - pirq_13 : in std_logic; - pirq_7 : in std_logic; - pirq_6 : in std_logic; - pirq_0 : in std_logic; - paddr_0 : in std_logic_vector(4 downto 2); - lclk_c : in std_logic; - N_365 : out std_logic; - N_367 : out std_logic; - N_863 : out std_logic; - intack : in std_logic; - N_865 : out std_logic; - N_861 : out std_logic; - N_859 : out std_logic; - N_478 : out std_logic; - N_476 : out std_logic; - N_474 : out std_logic; - N_473 : out std_logic; - N_472 : out std_logic; - N_471 : out std_logic; - N_470 : out std_logic; - N_468 : out std_logic; - N_467 : out std_logic; - N_842 : out std_logic; - N_841 : out std_logic; - N_839 : out std_logic; - N_363 : out std_logic; - N_361 : out std_logic; - N_773 : in std_logic; - N_769 : in std_logic; - rstn : in std_logic; - un1_apbi_0 : in std_logic; - N_749 : in std_logic; - prdata_0_sqmuxa : out std_logic; - N_898 : out std_logic; - prdata_1_sqmuxa : out std_logic - ); - -end irqmp; - -architecture DEF_ARCH of irqmp is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_262_0, N_258, N_258_0, un1_apbi_1, N_257, N_264, - N_261, \ipend_0_i_0_a6[15]\, \ipend_0_i_0_a6_0[15]\, - N_831, \ipend_0_i_0_a6_2_0[9]\, N_830, N_894, - \ipend_0_i_0_a6_1_0[9]\, N_828, \ipend_0_i_0_a6_0[9]\, - \ipend_0_i_0_a6_2[8]\, \ipend_0_i_0_a6_2_0[8]\, - \ipend_0_i_0_a6_1[8]\, \ipend_0_i_0_a6_1_0[8]\, - \ipend_0_i_0_a6[8]\, \ipend_0_i_0_a6_0[8]\, N_818_i, - \ipend_0_i_0_a6_0[2]\, N_820, \ipend_0_i_0_a6_1_0[2]\, - N_403, \ipend_0_i_0_a6_2_0[2]\, \ipend_0_i_a2_0[5]\, - N_876, \ipend_0_i_0_a6_2_0[13]\, N_875, - \ipend_0_i_0_a6_1_0[13]\, \ipend_0_i_0_a6[13]\, - \ipend_0_i_0_a6_0[13]\, \ipend_0_i_0_a6_2[15]\, - \ipend_0_i_0_a6_2_0[15]\, \ipend_0_i_0_a6_1[15]\, - \ipend_0_i_0_a6_1_0[15]\, \ipend[2]\, \ipend[8]\, - \ipend[15]\, \ipend[13]\, \ipend[9]\, \ipend_0_i_0_1[2]\, - \ipend_0_i_0_1[12]\, N_877_i, N_881, N_882, - \ipend_0_i_0_1[6]\, \ipend_RNO_2[6]\, N_410, N_411, - \ipend_0_i_1[5]\, N_359, N_358, N_356, \ipend_0_i_0_1[3]\, - N_371, N_370, N_368, \ipend_0_i_0_1[7]\, \ipend_RNO_2[7]\, - N_374, N_375, \ipend_0_i_0_1[8]\, \ipend_0_i_0_1[4]\, - N_407, N_406, \ipend_RNO_4[4]\, \iforce_0_0_i_0_1[8]\, - N_822, N_413, \iforce_0_RNO_3[8]\, \iforce_0_0_i_0_1[10]\, - N_826, N_416, \iforce_0_RNO_3[10]\, \ipend_0_i_0_1[9]\, - \iforce_0_0_i_0_1[5]\, N_835, N_834, \iforce_0_RNO_3[5]\, - \iforce_0_0_i_0_1[6]\, N_838, N_837, \iforce_0_RNO_3[6]\, - \iforce_0_0_i_0_1[15]\, N_442, N_441, - \iforce_0_RNO_3[15]\, \iforce_0_0_i_0_1[14]\, N_445, - N_444, \iforce_0_RNO_3[14]\, \iforce_0_0_i_0_1[13]\, - N_448, N_447, \iforce_0_RNO_3[13]\, - \iforce_0_0_i_0_1[11]\, N_451, N_450, - \iforce_0_RNO_3[11]\, \iforce_0_0_i_0_1[1]\, N_454, N_453, - \iforce_0_RNO_3[1]\, \ipend_0_i_0_1[14]\, N_458, N_457, - N_455, \ipend_0_i_0_1[11]\, N_462, N_461, N_459, - \iforce_0_0_i_0_1[4]\, N_489, N_488, \iforce_0_RNO_3[4]\, - \iforce_0_0_i_0_1[2]\, N_492, N_491, \iforce_0_RNO_3[2]\, - \ipend_0_i_0_1[15]\, \ipend_0_i_0_1[10]\, N_500, N_499, - N_497, \iforce_0_0_i_0_1[12]\, N_510, N_509, - \iforce_0_RNO_3[12]\, \iforce_0_0_i_0_1[9]\, N_513, N_512, - \iforce_0_RNO_3[9]\, \ipend_0_i_0_1[1]\, N_517, N_516, - N_514, \iforce_0_0_i_0_1[7]\, N_868, N_867, - \iforce_0_RNO_3[7]\, \iforce_0_0_i_0_1[3]\, N_871, N_870, - \iforce_0_RNO_3[3]\, \ipend_0_i_0_1[13]\, - \ipend_0_i_0_a6_2_0[12]\, \ipend_0_i_0_a6_0[12]\, - \ipend[12]\, \ipend_0_i_0_a6_1_0[12]\, \ipend[14]\, N_439, - \iforce_0[14]\, N_438, \ilevel[1]\, N_504, \iforce_0[1]\, - \N_898\, N_502, \prdata_0_iv_0_0_0[2]\, N_463, N_464, - \imask_0[13]\, N_895, N_481, \iforce_0[13]\, N_480, - \prdata_0_iv_0_0_1[15]\, \ilevel[15]\, \prdata_0_sqmuxa\, - N_486, \prdata_0_iv_0_0_0[3]\, N_519, N_520, irl_02_1, - \irl[2]\, N_400, \irl_i_0[0]\, N_885, \irl_0_0_i_0[1]\, - N_311, \irl_0_0_i_a6_1[1]\, N_506, - \prdata_0_iv_0_a2_0[6]_net_1\, \irl_0_1[0]\, N_198, N_384, - \irl_0_0[0]\, \a[14]\, \a_i_0[13]\, \a[15]\, - \irl_1_0_1[0]\, \irl_0_RNO_4[0]\, N_426, \a_1[15]\, - \irl_0_1[2]\, \irl_0_0[2]\, \irl_1_0_1[1]\, N_431_1, - N_422, \irl_1_0_0[1]\, \a_1[14]\, \irl_1_0_1[2]\, N_417, - \irl_1_0_0[2]\, \a_1[13]\, un1_apbi_1_0, - \irl_1_i_a2_1[3]\, N_19, \a_1[11]\, \a_i_0[6]\, \a[7]\, - \irl_0_0_i_a6_0[1]\, N_310, N_271, \irl_0_0_i_1_tz_1[1]\, - \a_i_i[9]\, N_883, N_165, \irl_0_a2_0[2]\, N_614, - \irl_i_a2_0[3]\, \irl_1_0_a2_0_1[1]\, \irl_1_0_a2_0_0[1]\, - N_792, \irl_i_a2_0_0[3]\, \irl_1_0_a2_1[2]\, N_434, - \irl_1_0_3_tz_0[0]\, \a_1_i_0[6]\, \a_1[5]\, \a_1[7]\, - \irl_0_3_tz_0[0]\, \a[5]\, \irl_1_0_a2_1_0_0[0]\, - \a_1[4]\, \irl_0_a2_1_0_0[0]\, \a[4]\, \a_1_0[11]\, - \imask_0[11]\, \ilevel[11]\, \iforce_0[4]\, \imask_0[4]\, - \a_i_0_o6_0[13]\, \ilevel[13]\, \a_1_0_a3_i_0[10]\, - \imask_0[10]\, \a_1_i_s_0_0[9]\, \imask_0[9]\, - \ilevel[9]\, \a_i_i_o2_0_o6_0[10]\, \ilevel[10]\, - \a_1_0[13]\, \a_1_0[14]\, \imask_0[14]\, \ilevel[14]\, - \irl_0_a2_1[0]\, N_402_i, \irl_1_0_a2_1[0]\, \a_1[3]\, - N_435_i, N_306, N_896, \irl_1[2]\, N_419_i, \irl_1_i[0]\, - \irl_0_RNO_2[0]\, \irl_1_0_3[0]\, N_433, N_437, N_386, - N_394, \irl_0_3[0]\, N_404, irl_02_i, N_240, N_892, N_631, - N_290, N_600_i_0, N_874, N_601_i_0, N_923, N_602_i_0, - N_930, N_857, N_856, N_70_i_0, N_515, N_82_i_0, N_919, - N_628_i_0, N_922, N_15_i_0, \ipend_RNO_0[10]\, N_648_i_0, - N_494, N_649_i_0, N_925, N_21_i_0, N_924, N_484, N_483, - N_466, N_465, N_703_i_0, \ipend_RNO_0[11]\, N_704_i_0, - \ipend_RNO_0[14]\, N_705_i_0, N_928, N_708_i_0, N_927, - N_709_i_0, N_926, N_710_i_0, N_931, N_711_i_0, N_917, - N_707_i_0, N_918, N_706_i_0, N_920, N_702_i_0, - \ipend_RNO_0[9]\, N_84_i_0, N_921, N_80_i_0, N_929, - N_76_i_0, \ipend_RNO_0[4]\, N_598_i_0, \ipend_RNO_0[8]\, - N_25_i_0, \ipend_RNO_0[7]\, N_23_i_0, \ipend_RNO_0[3]\, - N_794_i_0, \ipend_RNO_0[5]\, N_285, N_795, \imask_0[8]\, - N_291, \imask_0[12]\, N_298, \ilevel[8]\, N_17, - \imask_0[2]\, \ilevel[2]\, N_383, N_4, N_270, N_13, - \ilevel[12]\, \irl_0_0_i_1_tz[1]\, \irl_1[1]\, N_421, - N_289, N_78_i_0, \ipend_RNO_0[6]\, N_599_i_0, - \ipend_RNO_0[12]\, N_266_i, N_259, N_263, N_627_i_0, - \ipend_RNO_0[2]\, N_884, \irl_0_0_i_a6_1_0[1]\, N_385, - N_521, \imask_0[1]\, imask_0_1_sqmuxa, N_523, - \imask_0[3]\, N_524, N_525, \imask_0[5]\, N_526, - \imask_0[6]\, N_527, \imask_0[7]\, N_528, N_529, N_530, - N_533, N_535, \imask_0[15]\, \un1_temp[4]\, \ipend[4]\, - \temp_0_1[15]\, \iforce_0[15]\, N_350, N_269, \ilevel[3]\, - \ilevel[4]\, \ilevel[7]\, \prdata_1_sqmuxa\, N_414, N_415, - N_418, \irl_0_1_0[0]\, \irl_0_1_0[2]\, \irl_0_1[3]\, N_20, - N_24, \ilevel[5]\, \ilevel[6]\, \ipend[7]\, \ipend[5]\, - \ipend[6]\, \ipend[3]\, \iforce_0[3]\, \iforce_0[7]\, - \iforce_0[8]\, \imask_0_RNO[1]\, \imask_0_RNO[3]\, N_388, - N_389, N_390, \imask_0_RNO[7]\, \imask_0_RNO[8]\, - \imask_0_RNO[9]\, \imask_0_RNO[10]\, N_397, - \imask_0_RNO[15]\, N_827, \iforce_0[9]\, \iforce_0[5]\, - \iforce_0[11]\, N_262, \ipend[10]\, \iforce_0[10]\, - \ipend[1]\, N_886, N_889, N_899, N_904, N_905, N_908, - N_910, \iforce_0_0_i_0_a2_0[15]\, \iforce_0[6]\, - \ipend[11]\, \iforce_0[12]\, \iforce_0[2]\, N_915_i, - N_398, N_534, \imask_0_RNO[12]\, N_532, \irl_0_1[1]\, - \imask_0_RNO[11]\, N_531, \imask_0_RNO[2]\, N_522, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - ipend_10 <= \ipend[11]\; - iforce_0_11 <= \iforce_0[12]\; - iforce_0_5 <= \iforce_0[6]\; - iforce_0_9 <= \iforce_0[10]\; - iforce_0_4 <= \iforce_0[5]\; - iforce_0_6 <= \iforce_0[7]\; - ilevel_5 <= \ilevel[6]\; - ilevel_4 <= \ilevel[5]\; - ilevel_6 <= \ilevel[7]\; - ilevel_3 <= \ilevel[4]\; - ilevel_11 <= \ilevel[12]\; - ilevel_7 <= \ilevel[8]\; - ilevel_9 <= \ilevel[10]\; - prdata_0_sqmuxa <= \prdata_0_sqmuxa\; - N_898 <= \N_898\; - prdata_1_sqmuxa <= \prdata_1_sqmuxa\; - - \r.imask_0_RNO[3]\ : NOR2B - port map(A => rstn, B => N_523, Y => \imask_0_RNO[3]\); - - \r.ipend_RNO[9]\ : NOR3C - port map(A => \ipend_RNO_0[9]\, B => \ipend_0_i_0_1[9]\, C - => rstn, Y => N_702_i_0); - - \r.ipend_0_i_0_a6_2_RNO[2]\ : NOR2 - port map(A => pwdata_0(2), B => pirq_0, Y => - \ipend_0_i_0_a6_2_0[2]\); - - \r.ilevel_RNI84GN[12]\ : OR2A - port map(A => N_13, B => \a_1[14]\, Y => N_417); - - \r.irl_0_RNO_2[0]\ : OR3A - port map(A => N_795, B => N_19, C => N_417, Y => - \irl_0_RNO_2[0]\); - - \r.ipend_RNO[7]\ : NOR3C - port map(A => \ipend_RNO_0[7]\, B => \ipend_0_i_0_1[7]\, C - => rstn, Y => N_25_i_0); - - \r.ipend[10]\ : DFN1 - port map(D => N_15_i_0, CLK => lclk_c, Q => \ipend[10]\); - - \r.ilevel_RNI5U95[14]\ : OR2A - port map(A => \imask_0[14]\, B => \ilevel[14]\, Y => - \a_1_0[14]\); - - \r.iforce_0_RNO_2[10]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(10), Y => - N_416); - - \r.ipend_0_i_o2_0_0[5]\ : OR2 - port map(A => un1_apbi_1, B => N_257, Y => N_258_0); - - \r.ilevel_RNISHGN1[11]\ : NOR2B - port map(A => N_614, B => \irl_i_a2_0[3]\, Y => - \irl_0_a2_0[2]\); - - \r.ipend_RNO_1[7]\ : NOR3C - port map(A => \ipend_RNO_2[7]\, B => N_374, C => N_375, Y - => \ipend_0_i_0_1[7]\); - - \r.ilevel[14]\ : DFN1E1 - port map(D => pwdata_0(14), CLK => lclk_c, E => N_827, Q - => \ilevel[14]\); - - \r.iforce_0_RNO_2[12]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(12), Y => - N_509); - - \r.ipend_0_i_0_a6_2_RNO[8]\ : OR2 - port map(A => pwdata_0(8), B => pirq_6, Y => - \ipend_0_i_0_a6_2_0[8]\); - - \r.iforce_0_RNO_0[13]\ : NOR3C - port map(A => N_448, B => N_447, C => \iforce_0_RNO_3[13]\, - Y => \iforce_0_0_i_0_1[13]\); - - \r.iforce_0_RNIEFHJ[3]\ : OR2B - port map(A => \iforce_0[3]\, B => \N_898\, Y => N_519); - - \r.iforce_0_RNO[2]\ : NOR3C - port map(A => N_925, B => \iforce_0_0_i_0_1[2]\, C => rstn, - Y => N_649_i_0); - - \r.iforce_0_0_i_0_a2[8]\ : OR3B - port map(A => irl_3, B => N_910, C => irl_1, Y => N_929); - - \r.irl_0[3]\ : DFN1 - port map(D => \irl_0_1[3]\, CLK => lclk_c, Q => irl_0(3)); - - \r.ipend_0_i_0_a6_2[9]\ : NAND2 - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[9]\, Y => - N_831); - - \r.ilevel_RNIA6VF[2]\ : OR3B - port map(A => \imask_0[2]\, B => \ilevel[2]\, C => N_383, Y - => N_310); - - \r.ipend_RNO_0[4]\ : OR2 - port map(A => \iforce_0[4]\, B => N_924, Y => - \ipend_RNO_0[4]\); - - \r.iforce_0_RNO_2[3]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(3), Y => - N_870); - - \r.iforce_0_0_i_0_a2[4]\ : OR3A - port map(A => N_905, B => irl_1, C => irl_3, Y => N_924); - - \r.iforce_0[6]\ : DFN1 - port map(D => N_707_i_0, CLK => lclk_c, Q => \iforce_0[6]\); - - \r.imask_0[14]\ : DFN1 - port map(D => N_398, CLK => lclk_c, Q => \imask_0[14]\); - - \r.iforce_0_RNO_1[11]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_25, Y => N_451); - - \r.imask_0_RNIT60B[12]\ : OR2B - port map(A => \imask_0[12]\, B => N_895, Y => N_865); - - \r.iforce_0_RNO_3[13]\ : AO1 - port map(A => N_266_i, B => pwdata_0(13), C => - \iforce_0[13]\, Y => \iforce_0_RNO_3[13]\); - - \r.imask_0_RNIHLO8[15]\ : OA1 - port map(A => \iforce_0[15]\, B => \ipend[15]\, C => - \imask_0[15]\, Y => \temp_0_1[15]\); - - \r.iforce_0_0_i_0_a2[5]\ : OR3A - port map(A => N_908, B => irl_1, C => irl_3, Y => N_920); - - \r.ipend_RNO_4[1]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[1]\, Y => - N_514); - - \r.ipend_RNI9LH8[2]\ : NOR2 - port map(A => \ipend[2]\, B => \iforce_0[2]\, Y => N_383); - - \r.ipend_RNO_2[4]\ : OR3 - port map(A => N_258_0, B => N_261, C => pwdata_0(4), Y => - N_407); - - \r.ipend_RNO_1[15]\ : NOR3C - port map(A => \ipend_0_i_0_a6[15]\, B => - \ipend_0_i_0_a6_1[15]\, C => \ipend_0_i_0_a6_2[15]\, Y - => \ipend_0_i_0_1[15]\); - - \r.ipend_RNIUQ2A[4]\ : OR2B - port map(A => \ipend[4]\, B => \prdata_1_sqmuxa\, Y => - ipend_m(4)); - - \r.iforce_0_RNO_3[8]\ : AO1 - port map(A => N_266_i, B => pwdata_0(8), C => \iforce_0[8]\, - Y => \iforce_0_RNO_3[8]\); - - \r.ipend_RNISQ2A[2]\ : OR2B - port map(A => \ipend[2]\, B => \prdata_1_sqmuxa\, Y => - N_464); - - \r.ipend_RNIRQ2A[1]\ : OR2B - port map(A => \ipend[1]\, B => \prdata_1_sqmuxa\, Y => - N_502); - - \r.irl_0_RNO_2[2]\ : OR3A - port map(A => N_19, B => \a_1[11]\, C => N_434, Y => - \irl_1_0_a2_1[2]\); - - \r.ipend_RNID0DC[12]\ : OR2B - port map(A => \ipend[12]\, B => \prdata_1_sqmuxa\, Y => - N_863); - - \r.ipend_0_i_0_a6_2[15]\ : OR2A - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[15]\, Y => - \ipend_0_i_0_a6_2[15]\); - - \r.iforce_0_RNIJ3IJ[8]\ : OR2B - port map(A => \iforce_0[8]\, B => \N_898\, Y => N_467); - - \r.ilevel_RNIO9NB_0[10]\ : OR2B - port map(A => \a_i_i_o2_0_o6_0[10]\, B => N_290, Y => N_631); - - \r.iforce_0_RNILK3F[15]\ : OR2B - port map(A => \iforce_0[15]\, B => \N_898\, Y => N_483); - - \r.ipend_RNO_1[3]\ : NOR3C - port map(A => N_371, B => N_370, C => N_368, Y => - \ipend_0_i_0_1[3]\); - - \r.ilevel_RNIEEVF_0[3]\ : OR2A - port map(A => N_269, B => \ilevel[3]\, Y => \a_1[3]\); - - \r.ipend_RNIGCDC[15]\ : OR2B - port map(A => \ipend[15]\, B => \prdata_1_sqmuxa\, Y => - N_484); - - \r.ipend_0_i_0_a6_2[2]\ : NAND2 - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[2]\, Y => - N_403); - - \r.imask_0_RNO[14]\ : NOR2B - port map(A => rstn, B => N_534, Y => N_398); - - \r.ilevel_RNIKL631[11]\ : AO1 - port map(A => N_631, B => N_198, C => N_883, Y => N_915_i); - - \r.ipend_0_i_o2[5]\ : NOR2 - port map(A => N_258_0, B => N_261, Y => N_264); - - \r.imask_0_RNIVE0B[14]\ : OR2B - port map(A => \imask_0[14]\, B => N_895, Y => N_439); - - \r.irl_0_RNO_2[1]\ : AO1A - port map(A => N_418, B => N_415, C => N_414, Y => N_421); - - \r.iforce_0_RNO_3[6]\ : AO1 - port map(A => N_266_i, B => pwdata_0(6), C => \iforce_0[6]\, - Y => \iforce_0_RNO_3[6]\); - - \r.iforce_0_0_i_0_a2[11]\ : OR2B - port map(A => \iforce_0_0_i_0_a2_0[15]\, B => N_904, Y => - N_927); - - \r.ipend_RNIRRD6[10]\ : OR2 - port map(A => \ipend[10]\, B => \iforce_0[10]\, Y => N_290); - - \r.ipend_0_i_0_a6_1_RNO[9]\ : AND2 - port map(A => pwdata_0(9), B => pirq_7, Y => - \ipend_0_i_0_a6_1_0[9]\); - - \r.iforce_0_RNO[6]\ : NOR3C - port map(A => N_918, B => \iforce_0_0_i_0_1[6]\, C => rstn, - Y => N_707_i_0); - - \r.iforce_0[1]\ : DFN1 - port map(D => N_705_i_0, CLK => lclk_c, Q => \iforce_0[1]\); - - \r.imask_0[2]\ : DFN1 - port map(D => \imask_0_RNO[2]\, CLK => lclk_c, Q => - \imask_0[2]\); - - \r.ilevel[10]\ : DFN1E1 - port map(D => pwdata_0(10), CLK => lclk_c, E => N_827, Q - => \ilevel[10]\); - - \r.ilevel_RNIIMVF_0[4]\ : OR3B - port map(A => \un1_temp[4]\, B => \imask_0[4]\, C => - \ilevel[4]\, Y => \a_1[4]\); - - \r.imask_0[15]\ : DFN1 - port map(D => \imask_0_RNO[15]\, CLK => lclk_c, Q => - \imask_0[15]\); - - \r.ipend_RNO_1[2]\ : NOR3C - port map(A => N_403, B => N_820, C => N_818_i, Y => - \ipend_0_i_0_1[2]\); - - \r.iforce_0_RNO[7]\ : NOR3C - port map(A => N_930, B => \iforce_0_0_i_0_1[7]\, C => rstn, - Y => N_602_i_0); - - \r.ilevel_RNI09H4A[14]\ : AO1D - port map(A => \irl_0_0_i_1_tz[1]\, B => N_311, C => - \irl_0_0_i_0[1]\, Y => N_240); - - \r.iforce_0_RNO[15]\ : NOR3B - port map(A => \iforce_0_0_i_0_1[15]\, B => rstn, C => N_917, - Y => N_711_i_0); - - \r.iforce_0_0_i_0_a2[12]\ : OR3B - port map(A => irl_3, B => N_905, C => irl_1, Y => N_922); - - \r.ipend_RNO_0[6]\ : OR2 - port map(A => \iforce_0[6]\, B => N_918, Y => - \ipend_RNO_0[6]\); - - \r.ipend[1]\ : DFN1 - port map(D => N_70_i_0, CLK => lclk_c, Q => \ipend[1]\); - - \r.ilevel_RNIQ0OR[8]\ : NOR2A - port map(A => N_631, B => N_165, Y => N_614); - - \r.imask_0[11]\ : DFN1 - port map(D => \imask_0_RNO[11]\, CLK => lclk_c, Q => - \imask_0[11]\); - - \r.ipend_RNIBPH8[3]\ : NOR2 - port map(A => \ipend[3]\, B => \iforce_0[3]\, Y => N_886); - - \r.iforce_0_RNO_3[3]\ : AO1 - port map(A => N_266_i, B => pwdata_0(3), C => \iforce_0[3]\, - Y => \iforce_0_RNO_3[3]\); - - \r.imask_0[6]\ : DFN1 - port map(D => N_390, CLK => lclk_c, Q => \imask_0[6]\); - - \r.ilevel_RNI8INQ1[14]\ : OR3B - port map(A => \a[15]\, B => N_915_i, C => \a[14]\, Y => - N_311); - - \prdata_0_iv_0_a2_0[6]\ : OA1 - port map(A => N_885, B => N_892, C => N_896, Y => \N_898\); - - \r.ilevel_RNI4SFN[12]\ : NOR2B - port map(A => \a_1[13]\, B => N_13, Y => N_431_1); - - \r.iforce_0_RNO[1]\ : NOR3B - port map(A => \iforce_0_0_i_0_1[1]\, B => rstn, C => N_928, - Y => N_705_i_0); - - \r.iforce_0_RNO_1[4]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_18, Y => N_489); - - \r.ipend_RNIVQ2A[5]\ : OR2B - port map(A => \ipend[5]\, B => \prdata_1_sqmuxa\, Y => - N_365); - - \r.ipend[8]\ : DFN1 - port map(D => N_598_i_0, CLK => lclk_c, Q => \ipend[8]\); - - \r.ipend[6]\ : DFN1 - port map(D => N_78_i_0, CLK => lclk_c, Q => \ipend[6]\); - - \r.ilevel_RNIUE0G[7]\ : OR3B - port map(A => \imask_0[7]\, B => \ilevel[7]\, C => N_350, Y - => \a[7]\); - - \r.iforce_0_RNO_1[10]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_24, Y => - N_826); - - \r.ipend_RNILDI8[8]\ : OR2 - port map(A => \ipend[8]\, B => \iforce_0[8]\, Y => N_291); - - \r.imask_0_RNO_0[7]\ : MX2 - port map(A => \imask_0[7]\, B => pwdata_0(7), S => - imask_0_1_sqmuxa, Y => N_527); - - \r.ilevel[12]\ : DFN1E1 - port map(D => pwdata_0(12), CLK => lclk_c, E => N_827, Q - => \ilevel[12]\); - - \r.ipend_0_i_0_a6_1[13]\ : NAND2 - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[13]\, Y => - N_875); - - \r.ilevel_RNIEEVF[3]\ : OR2B - port map(A => \ilevel[3]\, B => N_269, Y => N_271); - - \r.iforce_0_RNO_1[12]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_26, Y => N_510); - - \r.iforce_0_0_i_0_a2_1[9]\ : NOR2A - port map(A => irl_0_d0, B => N_899, Y => N_904); - - \r.ipend_RNIBOCC[10]\ : OR2B - port map(A => \ipend[10]\, B => \prdata_1_sqmuxa\, Y => - N_476); - - \r.iforce_0_RNO[10]\ : NOR3C - port map(A => N_921, B => \iforce_0_0_i_0_1[10]\, C => rstn, - Y => N_84_i_0); - - \r.imask_0_RNO[12]\ : NOR2B - port map(A => rstn, B => N_532, Y => \imask_0_RNO[12]\); - - \r.imask_0[10]\ : DFN1 - port map(D => \imask_0_RNO[10]\, CLK => lclk_c, Q => - \imask_0[10]\); - - \r.ilevel[15]\ : DFN1E1 - port map(D => pwdata_0(15), CLK => lclk_c, E => N_827, Q - => \ilevel[15]\); - - \r.ipend_0_i_0_a6_RNO[9]\ : NOR2A - port map(A => pirq_7, B => \ipend[9]\, Y => - \ipend_0_i_0_a6_0[9]\); - - \r.ilevel_RNICIOB_0[15]\ : NOR2A - port map(A => \temp_0_1[15]\, B => \ilevel[15]\, Y => - \a_1[15]\); - - \r.ilevel_RNIQ96J5[1]\ : AO1B - port map(A => \irl_0_3_tz_0[0]\, B => \irl_0_a2_1[0]\, C - => N_404, Y => \irl_0_3[0]\); - - \r.ipend_RNI1R2A[7]\ : OR2B - port map(A => \ipend[7]\, B => \prdata_1_sqmuxa\, Y => - N_859); - - \r.iforce_0_RNIDBHJ[2]\ : OR2B - port map(A => \iforce_0[2]\, B => \N_898\, Y => N_463); - - \r.ilevel_RNI7IEC[2]\ : OR2B - port map(A => \ilevel[2]\, B => \prdata_0_sqmuxa\, Y => - N_465); - - \r.ilevel_RNI8LVV_0[4]\ : OR2A - port map(A => \a[4]\, B => \a[5]\, Y => N_385); - - \r.iforce_0_RNIHK3F[11]\ : OR2B - port map(A => \iforce_0[11]\, B => \N_898\, Y => N_839); - - \r.imask_0_RNO_0[6]\ : MX2 - port map(A => \imask_0[6]\, B => pwdata_0(6), S => - imask_0_1_sqmuxa, Y => N_526); - - \r.iforce_0_RNO_0[11]\ : NOR3C - port map(A => N_451, B => N_450, C => \iforce_0_RNO_3[11]\, - Y => \iforce_0_0_i_0_1[11]\); - - \r.ilevel_RNI6V0G_0[9]\ : OR2B - port map(A => \a_1_i_s_0_0[9]\, B => N_285, Y => N_19); - - \r.irl_0_RNO[2]\ : MX2C - port map(A => \irl_1[2]\, B => \irl[2]\, S => irl_02_i, Y - => \irl_0_1_0[2]\); - - \r.imask_0_RNIC5LB[2]\ : OR2B - port map(A => \imask_0[2]\, B => N_895, Y => N_466); - - \r.iforce_0_RNO[11]\ : NOR3C - port map(A => N_927, B => \iforce_0_0_i_0_1[11]\, C => rstn, - Y => N_708_i_0); - - \r.imask_0_RNI3T45[4]\ : NOR2A - port map(A => \imask_0[4]\, B => paddr(7), Y => - prdata_11_m_1_0(4)); - - \r.iforce_0_0_i_0_a2_0[10]\ : NOR2 - port map(A => irl_0_d0, B => N_899, Y => N_910); - - \r.iforce_0[15]\ : DFN1 - port map(D => N_711_i_0, CLK => lclk_c, Q => \iforce_0[15]\); - - \r.ipend_0_i_0_a6_1_RNO[2]\ : NOR2A - port map(A => pwdata_0(2), B => pirq_0, Y => - \ipend_0_i_0_a6_1_0[2]\); - - \r.imask_0[9]\ : DFN1 - port map(D => \imask_0_RNO[9]\, CLK => lclk_c, Q => - \imask_0[9]\); - - \r.ipend_0_i_0_a6_2_RNO[15]\ : OR2 - port map(A => pwdata_0(15), B => pirq_13, Y => - \ipend_0_i_0_a6_2_0[15]\); - - \r.imask_0[3]\ : DFN1 - port map(D => \imask_0_RNO[3]\, CLK => lclk_c, Q => - \imask_0[3]\); - - \r.ipend_RNO_0[7]\ : OR2 - port map(A => \iforce_0[7]\, B => N_930, Y => - \ipend_RNO_0[7]\); - - \r.iforce_0_RNO_3[11]\ : AO1 - port map(A => N_266_i, B => pwdata_0(11), C => - \iforce_0[11]\, Y => \iforce_0_RNO_3[11]\); - - \v.ilevel_0_sqmuxa_i_i_o2\ : OR2 - port map(A => paddr(7), B => paddr_0(3), Y => N_259); - - \r.ipend_RNO_2[10]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(10), Y => - N_500); - - \r.iforce_0_RNO[4]\ : NOR3C - port map(A => N_924, B => \iforce_0_0_i_0_1[4]\, C => rstn, - Y => N_21_i_0); - - \r.irl_0_RNO_3[2]\ : OR2 - port map(A => N_417, B => \irl_1_0_0[2]\, Y => - \irl_1_0_1[2]\); - - \r.iforce_0_RNO_0[2]\ : NOR3C - port map(A => N_492, B => N_491, C => \iforce_0_RNO_3[2]\, - Y => \iforce_0_0_i_0_1[2]\); - - GND_i : GND - port map(Y => \GND\); - - \r.ipend_0_i_0_a6_1_RNO[8]\ : OR2A - port map(A => pwdata_0(8), B => pirq_6, Y => - \ipend_0_i_0_a6_1_0[8]\); - - \r.imask_0[13]\ : DFN1 - port map(D => N_397, CLK => lclk_c, Q => \imask_0[13]\); - - \r.iforce_0_RNO_1[9]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_23, Y => N_513); - - \r.ipend_RNO_0[5]\ : OR2 - port map(A => \iforce_0[5]\, B => N_920, Y => - \ipend_RNO_0[5]\); - - \r.ipend_0_i_0_a6_1_RNO[13]\ : NOR2A - port map(A => pwdata_0(13), B => pirq_11, Y => - \ipend_0_i_0_a6_1_0[13]\); - - \r.ipend[13]\ : DFN1 - port map(D => N_600_i_0, CLK => lclk_c, Q => \ipend[13]\); - - \r.iforce_0_0_i_0_a2_1[15]\ : NOR2A - port map(A => irl_0_d0, B => N_889, Y => N_908); - - \r.ipend_RNO_0[12]\ : OR2 - port map(A => \iforce_0[12]\, B => N_922, Y => - \ipend_RNO_0[12]\); - - \r.ipend_RNO_4[12]\ : OR3A - port map(A => \ipend_0_i_0_a6_2_0[12]\, B => N_258_0, C => - N_261, Y => N_882); - - \r.ipend_RNO[11]\ : NOR3C - port map(A => \ipend_RNO_0[11]\, B => \ipend_0_i_0_1[11]\, - C => rstn, Y => N_703_i_0); - - \r.irl_0_RNO_1[3]\ : NOR3B - port map(A => N_19, B => \a_1[13]\, C => \a_1[11]\, Y => - \irl_1_i_a2_1[3]\); - - \r.ipend_RNO_3[1]\ : OR3A - port map(A => pwdata_0(1), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_516); - - \r.ipend[4]\ : DFN1 - port map(D => N_76_i_0, CLK => lclk_c, Q => \ipend[4]\); - - \r.iforce_0_RNO[3]\ : NOR3C - port map(A => N_923, B => \iforce_0_0_i_0_1[3]\, C => rstn, - Y => N_601_i_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.irl_0_RNO[1]\ : AO1B - port map(A => \irl_1[1]\, B => irl_02_1, C => N_240, Y => - \irl_0_1[1]\); - - \r.iforce_0_RNO_3[2]\ : AO1 - port map(A => N_266_i, B => pwdata_0(2), C => \iforce_0[2]\, - Y => \iforce_0_RNO_3[2]\); - - \r.ilevel_RNIOO0F1[15]\ : OR2 - port map(A => N_384, B => \irl_0_0[2]\, Y => \irl_0_1[2]\); - - \r.iforce_0_0_i_0_a2[15]\ : NOR2B - port map(A => N_908, B => \iforce_0_0_i_0_a2_0[15]\, Y => - N_917); - - \r.ipend_RNO_2[14]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(14), Y => - N_458); - - \r.iforce_0_RNO_1[8]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_22, Y => - N_822); - - \r.ipend_RNO_1[6]\ : NOR3C - port map(A => \ipend_RNO_2[6]\, B => N_410, C => N_411, Y - => \ipend_0_i_0_1[6]\); - - \r.ilevel_RNIQ60G[6]\ : OR2A - port map(A => \ilevel[6]\, B => N_24, Y => \a_i_0[6]\); - - \r.ilevel_RNILLVA[11]\ : OR2B - port map(A => \ilevel[11]\, B => \prdata_0_sqmuxa\, Y => - N_841); - - \r.iforce_0[11]\ : DFN1 - port map(D => N_708_i_0, CLK => lclk_c, Q => \iforce_0[11]\); - - \r.ipend_RNO_0[9]\ : OR2 - port map(A => \iforce_0[9]\, B => N_919, Y => - \ipend_RNO_0[9]\); - - \r.ipend_RNITQ2A[3]\ : OR2B - port map(A => \ipend[3]\, B => \prdata_1_sqmuxa\, Y => - N_520); - - \r.ipend_RNO_3[3]\ : OR3A - port map(A => pwdata_0(3), B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_370); - - \r.ipend_RNO[13]\ : NOR3C - port map(A => N_874, B => \ipend_0_i_0_1[13]\, C => rstn, Y - => N_600_i_0); - - \r.ilevel_RNIGKGN[15]\ : OR2B - port map(A => \a_i_0[13]\, B => \a[15]\, Y => \irl_0_0[2]\); - - \r.iforce_0[2]\ : DFN1 - port map(D => N_649_i_0, CLK => lclk_c, Q => \iforce_0[2]\); - - \r.ilevel_RNI42OB[13]\ : OR2B - port map(A => \a_1_0[13]\, B => N_306, Y => \a_1[13]\); - - \r.iforce_0_0_i_0_a2_2[8]\ : NOR3A - port map(A => paddr(7), B => paddr(5), C => paddr_0(3), Y - => N_892); - - \r.ipend_RNO_3[10]\ : OR3A - port map(A => pwdata_0(10), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_499); - - \r.iforce_0_0_i_0_m2[8]\ : MX2C - port map(A => paddr(5), B => paddr(7), S => paddr(3), Y => - N_263); - - \r.irl_0_RNO_1[1]\ : NOR2B - port map(A => \irl_1_0_a2_0_0[1]\, B => N_431_1, Y => - \irl_1_0_a2_0_1[1]\); - - \r.irl_0_RNO[0]\ : MX2C - port map(A => \irl_1_i[0]\, B => \irl_i_0[0]\, S => - irl_02_i, Y => \irl_0_1_0[0]\); - - \r.imask_0[5]\ : DFN1 - port map(D => N_389, CLK => lclk_c, Q => \imask_0[5]\); - - \r.iforce_0_RNO_2[14]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(14), Y => - N_444); - - \r.ipend_0_i_a2_0[5]\ : OR2B - port map(A => paddr_0(2), B => N_885, Y => - \ipend_0_i_a2_0[5]\); - - \r.ipend_RNO_0[1]\ : OR2A - port map(A => N_928, B => \iforce_0[1]\, Y => N_515); - - \r.iforce_0_RNO_2[6]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(6), Y => - N_837); - - \r.ilevel_RNICIOB[15]\ : OR2B - port map(A => \ilevel[15]\, B => \temp_0_1[15]\, Y => - \a[15]\); - - \r.iforce_0_RNO_2[2]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(2), Y => - N_491); - - prdata_0_sqmuxa_0_a2_0_a2 : NOR2 - port map(A => N_884, B => N_257, Y => \prdata_0_sqmuxa\); - - \r.iforce_0_0_i_0_a2_2[9]\ : OR2 - port map(A => irl_0(2), B => intack, Y => N_899); - - \r.iforce_0[8]\ : DFN1 - port map(D => N_80_i_0, CLK => lclk_c, Q => \iforce_0[8]\); - - \r.ipend[12]\ : DFN1 - port map(D => N_599_i_0, CLK => lclk_c, Q => \ipend[12]\); - - \r.iforce_0_RNO_0[10]\ : NOR3C - port map(A => N_826, B => N_416, C => \iforce_0_RNO_3[10]\, - Y => \iforce_0_0_i_0_1[10]\); - - \r.imask_0_RNO[1]\ : NOR2B - port map(A => rstn, B => N_521, Y => \imask_0_RNO[1]\); - - \r.ipend_RNO_3[14]\ : OR3A - port map(A => pwdata_0(14), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_457); - - \r.ilevel_RNIHJ3O[1]\ : AOI1B - port map(A => \ilevel[1]\, B => \prdata_0_sqmuxa\, C => - N_504, Y => prdata_0_iv_0_0_1_0); - - \r.iforce_0_RNO_0[8]\ : NOR3C - port map(A => N_822, B => N_413, C => \iforce_0_RNO_3[8]\, - Y => \iforce_0_0_i_0_1[8]\); - - \r.iforce_0_RNO_0[12]\ : NOR3C - port map(A => N_510, B => N_509, C => \iforce_0_RNO_3[12]\, - Y => \iforce_0_0_i_0_1[12]\); - - \r.iforce_0_0_i_0_a2[14]\ : OR2B - port map(A => \iforce_0_0_i_0_a2_0[15]\, B => N_905, Y => - N_931); - - \r.iforce_0_RNO_1[6]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_20, Y => - N_838); - - \r.iforce_0[13]\ : DFN1 - port map(D => N_709_i_0, CLK => lclk_c, Q => \iforce_0[13]\); - - \r.imask_0_RNIS20B[11]\ : OR2B - port map(A => \imask_0[11]\, B => N_895, Y => N_842); - - \r.ipend_RNO_1[13]\ : NOR3C - port map(A => \ipend_0_i_0_a6[13]\, B => N_875, C => N_876, - Y => \ipend_0_i_0_1[13]\); - - \r.ipend[7]\ : DFN1 - port map(D => N_25_i_0, CLK => lclk_c, Q => \ipend[7]\); - - \r.iforce_0_RNO_3[7]\ : AO1 - port map(A => N_266_i, B => pwdata_0(7), C => \iforce_0[7]\, - Y => \iforce_0_RNO_3[7]\); - - \r.iforce_0[9]\ : DFN1 - port map(D => N_82_i_0, CLK => lclk_c, Q => \iforce_0[9]\); - - \r.iforce_0_RNO_3[10]\ : AO1 - port map(A => N_266_i, B => pwdata_0(10), C => - \iforce_0[10]\, Y => \iforce_0_RNO_3[10]\); - - \r.ilevel_RNI8RPB3[7]\ : NOR2 - port map(A => \irl_0_0_i_1_tz_1[1]\, B => - \irl_0_0_i_a6_1_0[1]\, Y => \irl_0_0_i_1_tz[1]\); - - \r.ilevel[3]\ : DFN1E1 - port map(D => pwdata_1_2, CLK => lclk_c, E => N_827, Q => - \ilevel[3]\); - - \r.imask_0_RNO[8]\ : NOR2B - port map(A => rstn, B => N_528, Y => \imask_0_RNO[8]\); - - \r.iforce_0_RNO_3[12]\ : AO1 - port map(A => N_266_i, B => pwdata_0(12), C => - \iforce_0[12]\, Y => \iforce_0_RNO_3[12]\); - - \r.ipend_RNO_1[10]\ : NOR3C - port map(A => N_500, B => N_499, C => N_497, Y => - \ipend_0_i_0_1[10]\); - - \r.ilevel_RNI258J1[8]\ : NOR2A - port map(A => N_614, B => N_384, Y => N_404); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.ilevel_RNI2HOR[11]\ : NOR2B - port map(A => \a_i_i[9]\, B => N_198, Y => \irl_i_a2_0[3]\); - - \r.iforce_0_0_i_0_a2[10]\ : OR2B - port map(A => N_910, B => \iforce_0_0_i_0_a2_0[15]\, Y => - N_921); - - \r.ipend_0_i_0_a6_2[8]\ : OR2A - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[8]\, Y => - \ipend_0_i_0_a6_2[8]\); - - \r.ilevel_RNIG4UV[1]\ : OR3B - port map(A => \ilevel[1]\, B => N_310, C => N_4, Y => - N_402_i); - - \r.iforce_0_RNO_3[5]\ : AO1 - port map(A => N_266_i, B => pwdata_0(5), C => \iforce_0[5]\, - Y => \iforce_0_RNO_3[5]\); - - \r.ipend_RNO_4[6]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(6), Y => - N_411); - - \r.ipend_RNO_2[6]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[6]\, Y => - \ipend_RNO_2[6]\); - - \r.iforce_0[4]\ : DFN1 - port map(D => N_21_i_0, CLK => lclk_c, Q => \iforce_0[4]\); - - \r.ipend_RNO_2[3]\ : OR3 - port map(A => N_258_0, B => N_261, C => pwdata_0(3), Y => - N_371); - - \r.irl_0_RNO_4[0]\ : OR2 - port map(A => \a_1[14]\, B => \a_1[13]\, Y => - \irl_0_RNO_4[0]\); - - \r.imask_0_RNI06OL1[3]\ : OR3C - port map(A => N_857, B => N_856, C => - \prdata_0_iv_0_0_0[3]\, Y => prdata_1); - - prdata_0_sqmuxa_0_a2_0_o2 : OR2 - port map(A => paddr(6), B => paddr(4), Y => N_257); - - \r.ilevel[4]\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => N_827, Q => - \ilevel[4]\); - - \r.iforce_0_0_i_0_a2_0[15]\ : NOR2B - port map(A => irl_3, B => irl_1, Y => - \iforce_0_0_i_0_a2_0[15]\); - - \r.imask_0_RNIG5LB[6]\ : OR2B - port map(A => \imask_0[6]\, B => N_895, Y => N_363); - - \r.iforce_0_RNO_2[8]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(8), Y => - N_413); - - \r.ipend_RNO_1[14]\ : NOR3C - port map(A => N_458, B => N_457, C => N_455, Y => - \ipend_0_i_0_1[14]\); - - \r.ilevel_RNISHNB_0[11]\ : NOR2B - port map(A => \a_1_0[11]\, B => N_289, Y => \a_1[11]\); - - \r.irl_0_RNO_7[0]\ : AO1B - port map(A => \a_1[3]\, B => N_435_i, C => - \irl_1_0_a2_1_0_0[0]\, Y => \irl_1_0_a2_1[0]\); - - \r.iforce_0_0_i_0_a2[3]\ : OR3B - port map(A => irl_1, B => N_904, C => irl_3, Y => N_923); - - \r.ipend_RNO_3[5]\ : OR3A - port map(A => pwdata_0(5), B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_358); - - \r.ipend_0_i_0_a6_RNO[8]\ : OR2 - port map(A => pirq_6, B => \ipend[8]\, Y => - \ipend_0_i_0_a6_0[8]\); - - \comb.un1_apbi_1_0\ : NOR2 - port map(A => N_749, B => un1_apbi_0, Y => un1_apbi_1_0); - - \r.irl_0_RNO_7[1]\ : NOR2 - port map(A => \a_1[14]\, B => \a_1[15]\, Y => - \irl_1_0_0[1]\); - - \r.ipend_RNO_2[11]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(11), Y => - N_462); - - \r.imask_0_RNO_0[4]\ : MX2 - port map(A => \imask_0[4]\, B => pwdata_0(4), S => - imask_0_1_sqmuxa, Y => N_524); - - \r.ipend_RNO_1[5]\ : NOR3C - port map(A => N_359, B => N_358, C => N_356, Y => - \ipend_0_i_1[5]\); - - \r.imask_0_RNO[4]\ : NOR2B - port map(A => rstn, B => N_524, Y => N_388); - - \r.ipend_RNI2R2A[8]\ : OR2B - port map(A => \ipend[8]\, B => \prdata_1_sqmuxa\, Y => - N_468); - - \r.ilevel_RNIO9NB[10]\ : OR2B - port map(A => \a_1_0_a3_i_0[10]\, B => N_290, Y => N_795); - - \r.ilevel[6]\ : DFN1E1 - port map(D => pwdata_4, CLK => lclk_c, E => N_827, Q => - \ilevel[6]\); - - \r.irl_0[1]\ : DFN1 - port map(D => \irl_0_1[1]\, CLK => lclk_c, Q => irl_0(1)); - - \r.iforce_0_RNO_3[4]\ : AO1 - port map(A => N_266_i, B => pwdata_0(4), C => \iforce_0[4]\, - Y => \iforce_0_RNO_3[4]\); - - \r.iforce_0_RNO[13]\ : NOR3B - port map(A => \iforce_0_0_i_0_1[13]\, B => rstn, C => N_926, - Y => N_709_i_0); - - \r.ipend_0_i_0_a6_1[15]\ : OR2A - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[15]\, Y => - \ipend_0_i_0_a6_1[15]\); - - \r.ilevel[8]\ : DFN1E1 - port map(D => pwdata_0(8), CLK => lclk_c, E => N_827, Q => - \ilevel[8]\); - - \r.imask_0_RNISTNL1[2]\ : OR3C - port map(A => N_466, B => N_465, C => - \prdata_0_iv_0_0_0[2]\, Y => prdata_0); - - \r.ipend_0_i_0_a6[15]\ : OR2 - port map(A => N_264, B => \ipend_0_i_0_a6_0[15]\, Y => - \ipend_0_i_0_a6[15]\); - - \comb.un1_apbi_1\ : OR3C - port map(A => N_769, B => N_773, C => un1_apbi_1_0, Y => - un1_apbi_1); - - \r.irl_0_RNO_5[1]\ : OR2B - port map(A => \a_1[3]\, B => N_17, Y => N_415); - - \r.irl_0_RNO_4[2]\ : OR2A - port map(A => \a_1[13]\, B => \a_1[15]\, Y => - \irl_1_0_0[2]\); - - \r.ilevel_RNIKAH63[15]\ : NOR3C - port map(A => \irl_i_a2_0_0[3]\, B => \irl_i_a2_0[3]\, C - => N_404, Y => N_400); - - \r.ipend_RNI0R2A[6]\ : OR2B - port map(A => \ipend[6]\, B => \prdata_1_sqmuxa\, Y => - N_361); - - \r.ipend[3]\ : DFN1 - port map(D => N_23_i_0, CLK => lclk_c, Q => \ipend[3]\); - - \r.imask_0_RNIH5LB[7]\ : OR2B - port map(A => \imask_0[7]\, B => N_895, Y => N_861); - - \r.imask_0[4]\ : DFN1 - port map(D => N_388, CLK => lclk_c, Q => \imask_0[4]\); - - \r.iforce_0_RNO_1[14]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_28, Y => - N_445); - - \r.ilevel_RNIOU831_0[14]\ : NOR3A - port map(A => \a[15]\, B => \a[14]\, C => \a_i_0[13]\, Y - => N_506); - - \r.iforce_0_RNO_2[9]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(9), Y => - N_512); - - prdata_2_sqmuxa_0_a2_0_a2_0 : NOR2 - port map(A => N_257, B => paddr_0(2), Y => N_896); - - \r.ipend_RNIAPGB[5]\ : OAI1 - port map(A => \iforce_0[5]\, B => \ipend[5]\, C => - \imask_0[5]\, Y => N_20); - - \r.iforce_0_RNO_2[15]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(15), Y => - N_441); - - \r.irl_0_RNO_0[3]\ : NOR3B - port map(A => \irl_1_i_a2_1[3]\, B => N_437, C => \a_1[15]\, - Y => N_433); - - \r.ipend_RNO_3[11]\ : OR3A - port map(A => pwdata_0(11), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_461); - - \r.ipend_RNO_1[9]\ : NOR3C - port map(A => N_831, B => N_830, C => N_828, Y => - \ipend_0_i_0_1[9]\); - - \r.ipend_RNI3R2A[9]\ : OR2B - port map(A => \ipend[9]\, B => \prdata_1_sqmuxa\, Y => - N_472); - - \r.iforce_0_0_i_0_o2_0[8]\ : NOR3C - port map(A => N_259, B => N_263, C => N_262_0, Y => N_266_i); - - \r.iforce_0_RNO_0[5]\ : NOR3C - port map(A => N_835, B => N_834, C => \iforce_0_RNO_3[5]\, - Y => \iforce_0_0_i_0_1[5]\); - - \r.iforce_0_0_i_0_a2[1]\ : NOR3A - port map(A => N_904, B => irl_1, C => irl_3, Y => N_928); - - \r.ipend_0_i_0_a6_RNO[15]\ : OR2 - port map(A => \ipend[15]\, B => pirq_13, Y => - \ipend_0_i_0_a6_0[15]\); - - \r.ipend[11]\ : DFN1 - port map(D => N_703_i_0, CLK => lclk_c, Q => \ipend[11]\); - - \r.imask_0_RNO_0[15]\ : MX2 - port map(A => \imask_0[15]\, B => pwdata_0(15), S => - imask_0_1_sqmuxa, Y => N_535); - - \r.imask_0_RNO_0[10]\ : MX2 - port map(A => \imask_0[10]\, B => pwdata_0(10), S => - imask_0_1_sqmuxa, Y => N_530); - - \r.ilevel_RNIMUVF[5]\ : NOR2A - port map(A => \ilevel[5]\, B => N_20, Y => \a[5]\); - - \r.ilevel_RNIQ0OR_0[8]\ : OR2B - port map(A => N_795, B => N_792, Y => N_434); - - \r.cpurst_0_0_a3_0_a2[0]\ : OR2 - port map(A => N_259, B => paddr_0(2), Y => N_884); - - \r.ilevel[7]\ : DFN1E1 - port map(D => pwdata_0(7), CLK => lclk_c, E => N_827, Q => - \ilevel[7]\); - - \r.ilevel_RNI6V0G[9]\ : OR3C - port map(A => \imask_0[9]\, B => \ilevel[9]\, C => N_285, Y - => \a_i_i[9]\); - - \r.ipend_0_i_0_a6_2_RNO[9]\ : NOR2A - port map(A => pirq_7, B => pwdata_0(9), Y => - \ipend_0_i_0_a6_2_0[9]\); - - \r.ipend_0_i_0_a6_1[2]\ : NAND2 - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[2]\, Y => - N_820); - - \r.iforce_0_RNO_1[5]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_19, Y => - N_835); - - \r.ipend_RNO_0[15]\ : OR2A - port map(A => N_917, B => \iforce_0[15]\, Y => N_494); - - \r.iforce_0[7]\ : DFN1 - port map(D => N_602_i_0, CLK => lclk_c, Q => \iforce_0[7]\); - - \v.ilevel_0_sqmuxa_i_i_o2_0\ : NOR2 - port map(A => N_258, B => paddr_0(2), Y => N_262); - - \r.irl_0[2]\ : DFN1 - port map(D => \irl_0_1_0[2]\, CLK => lclk_c, Q => irl_2(2)); - - \r.ipend_RNO_0[8]\ : OR2 - port map(A => \iforce_0[8]\, B => N_929, Y => - \ipend_RNO_0[8]\); - - \r.ipend_RNO_0[3]\ : OR2 - port map(A => \iforce_0[3]\, B => N_923, Y => - \ipend_RNO_0[3]\); - - \r.iforce_0_0_i_0_a2_2[6]\ : OR2A - port map(A => irl_0(2), B => intack, Y => N_889); - - \r.iforce_0[12]\ : DFN1 - port map(D => N_628_i_0, CLK => lclk_c, Q => \iforce_0[12]\); - - \r.ilevel_RNI258J1_0[8]\ : NOR2 - port map(A => N_434, B => N_417, Y => N_437); - - \r.iforce_0_RNO_1[3]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_17, Y => N_871); - - \r.ilevel_RNI3Q95[13]\ : NOR2B - port map(A => \ilevel[13]\, B => \imask_0[13]\, Y => - \a_i_0_o6_0[13]\); - - \r.imask_0_RNIRUVA[10]\ : OR2B - port map(A => \imask_0[10]\, B => N_895, Y => N_478); - - \r.ilevel_RNIOU831[14]\ : OA1 - port map(A => \a[14]\, B => \a_i_0[13]\, C => \a[15]\, Y - => \irl_0_0[0]\); - - \r.ipend_0_i_0_a6_1[8]\ : OR2A - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[8]\, Y => - \ipend_0_i_0_a6_1[8]\); - - \r.irl_0_RNO_9[0]\ : NOR2B - port map(A => \a_1[4]\, B => \a_1_i_0[6]\, Y => - \irl_1_0_a2_1_0_0[0]\); - - \r.ilevel_RNIIMVF[4]\ : OR3C - port map(A => \un1_temp[4]\, B => \imask_0[4]\, C => - \ilevel[4]\, Y => \a[4]\); - - \r.ilevel_RNIGAVV1[7]\ : NOR3C - port map(A => \a_i_0[6]\, B => \a[7]\, C => - \irl_0_0_i_a6_0[1]\, Y => \irl_0_0_i_a6_1[1]\); - - \r.ilevel_RNI0QNB_0[12]\ : NOR3C - port map(A => \imask_0[12]\, B => \ilevel[12]\, C => N_298, - Y => N_883); - - \r.iforce_0_RNI72KT[1]\ : AOI1B - port map(A => \iforce_0[1]\, B => \N_898\, C => N_502, Y - => prdata_0_iv_0_0_0_0); - - \r.ipend_RNO_1[11]\ : NOR3C - port map(A => N_462, B => N_461, C => N_459, Y => - \ipend_0_i_0_1[11]\); - - \r.ilevel_RNIOLVA[14]\ : OR2B - port map(A => \ilevel[14]\, B => \prdata_0_sqmuxa\, Y => - N_438); - - \r.ipend_0_i_0_a6[8]\ : OR2 - port map(A => N_264, B => \ipend_0_i_0_a6_0[8]\, Y => - \ipend_0_i_0_a6[8]\); - - \r.iforce_0_RNO[12]\ : NOR3C - port map(A => N_922, B => \iforce_0_0_i_0_1[12]\, C => rstn, - Y => N_628_i_0); - - \r.imask_0_RNO_0[12]\ : MX2 - port map(A => \imask_0[12]\, B => pwdata_0(12), S => - imask_0_1_sqmuxa, Y => N_532); - - \r.imask_0_RNO_0[1]\ : MX2 - port map(A => \imask_0[1]\, B => pwdata_0(1), S => - imask_0_1_sqmuxa, Y => N_521); - - \r.ipend_RNO[8]\ : NOR3C - port map(A => \ipend_RNO_0[8]\, B => \ipend_0_i_0_1[8]\, C - => rstn, Y => N_598_i_0); - - \r.ipend_RNO[12]\ : NOR3C - port map(A => \ipend_RNO_0[12]\, B => \ipend_0_i_0_1[12]\, - C => rstn, Y => N_599_i_0); - - \r.ilevel_RNITD95_0[10]\ : NOR2A - port map(A => \imask_0[10]\, B => \ilevel[10]\, Y => - \a_1_0_a3_i_0[10]\); - - \r.ilevel[1]\ : DFN1E1 - port map(D => pwdata_1_0, CLK => lclk_c, E => N_827, Q => - \ilevel[1]\); - - \r.ipend_0_i_0_a6_2_RNO[13]\ : NOR2 - port map(A => pirq_11, B => pwdata_0(13), Y => - \ipend_0_i_0_a6_2_0[13]\); - - \r.ilevel_RNI8MEC[3]\ : OR2B - port map(A => \ilevel[3]\, B => \prdata_0_sqmuxa\, Y => - N_856); - - \r.iforce_0_RNO[5]\ : NOR3C - port map(A => N_920, B => \iforce_0_0_i_0_1[5]\, C => rstn, - Y => N_706_i_0); - - \r.imask_0[7]\ : DFN1 - port map(D => \imask_0_RNO[7]\, CLK => lclk_c, Q => - \imask_0[7]\); - - \r.ilevel[11]\ : DFN1E1 - port map(D => pwdata_0(11), CLK => lclk_c, E => N_827, Q - => \ilevel[11]\); - - \r.irl_0_RNO_6[0]\ : AOI1B - port map(A => \a_1_i_0[6]\, B => \a_1[5]\, C => \a_1[7]\, Y - => \irl_1_0_3_tz_0[0]\); - - \r.iforce_0_RNO_0[9]\ : NOR3C - port map(A => N_513, B => N_512, C => \iforce_0_RNO_3[9]\, - Y => \iforce_0_0_i_0_1[9]\); - - \r.imask_0[8]\ : DFN1 - port map(D => \imask_0_RNO[8]\, CLK => lclk_c, Q => - \imask_0[8]\); - - \r.iforce_0_0_i_0_a2[13]\ : NOR3B - port map(A => irl_3, B => N_908, C => irl_1, Y => N_926); - - \r.ipend_RNO_4[7]\ : OR3 - port map(A => N_258_0, B => N_261, C => pwdata_0(7), Y => - N_375); - - \r.ipend_0_i_o2_1[5]\ : OR2A - port map(A => paddr_0(2), B => N_259, Y => N_261); - - \v.ilevel_0_sqmuxa_i_i_o2_0_0\ : NOR2 - port map(A => N_258, B => paddr_0(2), Y => N_262_0); - - \r.iforce_0_RNO_1[1]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_15, Y => N_454); - - \r.ilevel[9]\ : DFN1E1 - port map(D => pwdata_0(9), CLK => lclk_c, E => N_827, Q => - \ilevel[9]\); - - \r.ilevel[2]\ : DFN1E1 - port map(D => pwdata_0_d0, CLK => lclk_c, E => N_827, Q => - \ilevel[2]\); - - \r.ilevel_RNISBVC9[11]\ : NOR3C - port map(A => \irl_0_1[0]\, B => N_394, C => \irl_0_3[0]\, - Y => \irl_i_0[0]\); - - \r.irl_0[0]\ : DFN1 - port map(D => \irl_0_1_0[0]\, CLK => lclk_c, Q => irl_0(0)); - - \r.ilevel_RNIP80M[15]\ : AOI1B - port map(A => \ilevel[15]\, B => \prdata_0_sqmuxa\, C => - N_486, Y => \prdata_0_iv_0_0_1[15]\); - - \r.ilevel[13]\ : DFN1E1 - port map(D => pwdata_0(13), CLK => lclk_c, E => N_827, Q - => \ilevel[13]\); - - \r.iforce_0_RNO_0[3]\ : NOR3C - port map(A => N_871, B => N_870, C => \iforce_0_RNO_3[3]\, - Y => \iforce_0_0_i_0_1[3]\); - - \r.ilevel_RNI6D8J1[9]\ : OR3A - port map(A => N_631, B => \a_i_i[9]\, C => N_384, Y => - N_394); - - \r.ilevel_RNI8AOB[14]\ : NOR3B - port map(A => \imask_0[14]\, B => \ilevel[14]\, C => N_270, - Y => \a[14]\); - - \prdata_0_iv_0_a2_0_0[6]\ : NOR3A - port map(A => paddr(6), B => paddr(5), C => paddr_0(4), Y - => \prdata_0_iv_0_a2_0[6]_net_1\); - - \r.iforce_0_RNIK7IJ[9]\ : OR2B - port map(A => \iforce_0[9]\, B => \N_898\, Y => N_471); - - \r.iforce_0_0_i_0_a2[6]\ : OR3B - port map(A => irl_1, B => N_905, C => irl_3, Y => N_918); - - \r.iforce_0_RNO_1[15]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_29, Y => - N_442); - - \r.iforce_0_RNO_0[14]\ : NOR3C - port map(A => N_445, B => N_444, C => \iforce_0_RNO_3[14]\, - Y => \iforce_0_0_i_0_1[14]\); - - \r.ipend_RNO_6[12]\ : NOR2A - port map(A => pwdata_0(12), B => pirq_10, Y => - \ipend_0_i_0_a6_1_0[12]\); - - \r.imask_0_RNO_0[14]\ : MX2 - port map(A => \imask_0[14]\, B => pwdata_0(14), S => - imask_0_1_sqmuxa, Y => N_534); - - \r.irl_0_RNO_0[2]\ : OA1B - port map(A => N_419_i, B => \irl_1_0_a2_1[2]\, C => - \irl_1_0_1[2]\, Y => \irl_1[2]\); - - \r.imask_0_RNI4HGB[3]\ : NOR2A - port map(A => \imask_0[3]\, B => N_886, Y => N_269); - - \r.ipend_0_i_0_a6[13]\ : OR2 - port map(A => N_264, B => \ipend_0_i_0_a6_0[13]\, Y => - \ipend_0_i_0_a6[13]\); - - \r.iforce_0[5]\ : DFN1 - port map(D => N_706_i_0, CLK => lclk_c, Q => \iforce_0[5]\); - - \r.ipend_RNIV3E6[12]\ : OR2 - port map(A => \ipend[12]\, B => \iforce_0[12]\, Y => N_298); - - \r.ipend_RNO_3[4]\ : OR3A - port map(A => pwdata_0(4), B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_406); - - \r.irl_0_RNO_4[1]\ : NOR2B - port map(A => N_792, B => N_19, Y => \irl_1_0_a2_0_0[1]\); - - \r.irl_0_RNO[3]\ : MX2C - port map(A => N_433, B => N_400, S => irl_02_i, Y => - \irl_0_1[3]\); - - \r.iforce_0_RNO_3[1]\ : AO1 - port map(A => N_266_i, B => pwdata_1_0, C => \iforce_0[1]\, - Y => \iforce_0_RNO_3[1]\); - - \r.ipend[5]\ : DFN1 - port map(D => N_794_i_0, CLK => lclk_c, Q => \ipend[5]\); - - \r.iforce_0_RNO_0[7]\ : NOR3C - port map(A => N_868, B => N_867, C => \iforce_0_RNO_3[7]\, - Y => \iforce_0_0_i_0_1[7]\); - - \r.ilevel_RNISHNB[11]\ : OR3C - port map(A => \imask_0[11]\, B => \ilevel[11]\, C => N_289, - Y => N_198); - - \r.iforce_0_0_i_0_a2[7]\ : OR3B - port map(A => irl_1, B => N_908, C => irl_3, Y => N_930); - - \r.imask_0[12]\ : DFN1 - port map(D => \imask_0_RNO[12]\, CLK => lclk_c, Q => - \imask_0[12]\); - - \r.iforce_0_RNO_3[14]\ : AO1 - port map(A => N_266_i, B => pwdata_0(14), C => - \iforce_0[14]\, Y => \iforce_0_RNO_3[14]\); - - \r.iforce_0_RNO_1[7]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_21, Y => N_868); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.imask_0_RNO_0[9]\ : MX2 - port map(A => \imask_0[9]\, B => pwdata_0(9), S => - imask_0_1_sqmuxa, Y => N_529); - - \r.imask_0_RNIJ5LB[9]\ : OR2B - port map(A => \imask_0[9]\, B => N_895, Y => N_474); - - \r.ipend_RNO_2[5]\ : OR3 - port map(A => N_258_0, B => N_261, C => pwdata_0(5), Y => - N_359); - - \r.ipend_RNO_1[1]\ : NOR3C - port map(A => N_517, B => N_516, C => N_514, Y => - \ipend_0_i_0_1[1]\); - - \r.iforce_0_RNO_1[2]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_16, Y => N_492); - - \r.ipend_RNO_4[5]\ : AO1D - port map(A => N_261, B => N_258_0, C => \ipend[5]\, Y => - N_356); - - \r.iforce_0_0_i_0_a2[2]\ : OR3B - port map(A => irl_1, B => N_910, C => irl_3, Y => N_925); - - \r.ipend_RNO_7[12]\ : NOR2 - port map(A => pirq_10, B => pwdata_0(12), Y => - \ipend_0_i_0_a6_2_0[12]\); - - \r.ipend_RNIU8GB[1]\ : OAI1 - port map(A => \iforce_0[1]\, B => \ipend[1]\, C => - \imask_0[1]\, Y => N_4); - - \r.imask_0_RNID5LB[3]\ : OR2B - port map(A => \imask_0[3]\, B => N_895, Y => N_857); - - \r.ipend_RNO_2[12]\ : AO1D - port map(A => N_261, B => N_258_0, C => - \ipend_0_i_0_a6_0[12]\, Y => N_877_i); - - \r.ipend_RNIENDN[14]\ : AOI1B - port map(A => \ipend[14]\, B => \prdata_1_sqmuxa\, C => - N_439, Y => prdata_0_iv_0_0_1_13); - - \r.ilevel_RNI8AOB_0[14]\ : NOR2 - port map(A => \a_1_0[14]\, B => N_270, Y => \a_1[14]\); - - \r.ilevel_RNIOKUV[2]\ : NOR2B - port map(A => N_310, B => N_271, Y => \irl_0_0_i_a6_0[1]\); - - \r.imask_0_RNO[6]\ : NOR2B - port map(A => rstn, B => N_526, Y => N_390); - - \r.iforce_0_RNO_2[13]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(13), Y => - N_447); - - \r.iforce_0_RNO[9]\ : NOR3C - port map(A => N_919, B => \iforce_0_0_i_0_1[9]\, C => rstn, - Y => N_82_i_0); - - \v.ilevel_0_sqmuxa_i_i_a6\ : NOR2A - port map(A => N_262_0, B => N_259, Y => N_827); - - \r.ilevel_RNIVH95[11]\ : NOR2A - port map(A => \imask_0[11]\, B => \ilevel[11]\, Y => - \a_1_0[11]\); - - \r.ipend_RNO_3[7]\ : OR3A - port map(A => pwdata_0(7), B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_374); - - \r.ipend_RNO_1[8]\ : NOR3C - port map(A => \ipend_0_i_0_a6[8]\, B => - \ipend_0_i_0_a6_1[8]\, C => \ipend_0_i_0_a6_2[8]\, Y => - \ipend_0_i_0_1[8]\); - - \r.imask_0_RNO[9]\ : NOR2B - port map(A => rstn, B => N_529, Y => \imask_0_RNO[9]\); - - \r.ipend_RNO[3]\ : NOR3C - port map(A => \ipend_RNO_0[3]\, B => \ipend_0_i_0_1[3]\, C - => rstn, Y => N_23_i_0); - - \r.ipend[15]\ : DFN1 - port map(D => N_648_i_0, CLK => lclk_c, Q => \ipend[15]\); - - \r.imask_0_RNO_0[5]\ : MX2 - port map(A => \imask_0[5]\, B => pwdata_0(5), S => - imask_0_1_sqmuxa, Y => N_525); - - \r.ipend_RNO[6]\ : NOR3C - port map(A => \ipend_RNO_0[6]\, B => \ipend_0_i_0_1[6]\, C - => rstn, Y => N_78_i_0); - - \r.ipend_0_i_0_a6[9]\ : OR2A - port map(A => \ipend_0_i_0_a6_0[9]\, B => N_264, Y => N_828); - - \r.imask_0_RNO[11]\ : NOR2B - port map(A => rstn, B => N_531, Y => \imask_0_RNO[11]\); - - \r.imask_0_RNO[10]\ : NOR2B - port map(A => rstn, B => N_530, Y => \imask_0_RNO[10]\); - - \r.ilevel_RNI8LVV[4]\ : OR2A - port map(A => \a_1[4]\, B => \a_1[5]\, Y => N_418); - - \r.imask_0_RNIL00M[13]\ : AOI1B - port map(A => \imask_0[13]\, B => N_895, C => N_481, Y => - prdata_0_iv_0_0_1_12); - - \r.ilevel_RNIA6VF_0[2]\ : OR3A - port map(A => \imask_0[2]\, B => \ilevel[2]\, C => N_383, Y - => N_17); - - \v.imask_0_1_sqmuxa_0_a2_1_a6\ : NOR2A - port map(A => N_895, B => un1_apbi_1, Y => imask_0_1_sqmuxa); - - \r.iforce_0_RNO_2[4]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(4), Y => - N_488); - - \r.ipend_RNO_3[12]\ : OR3A - port map(A => \ipend_0_i_0_a6_1_0[12]\, B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_881); - - \r.imask_0_RNO_0[8]\ : MX2 - port map(A => \imask_0[8]\, B => pwdata_0(8), S => - imask_0_1_sqmuxa, Y => N_528); - - \r.ipend_RNO_2[1]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(1), Y => - N_517); - - \r.ilevel_RNI0B002_0[7]\ : NOR3C - port map(A => \a_i_0[6]\, B => \a[7]\, C => N_385, Y => - \irl_0_0_i_a6_1_0[1]\); - - \r.ilevel_RNISKG62[11]\ : OA1 - port map(A => N_198, B => N_384, C => \irl_0_0[0]\, Y => - \irl_0_1[0]\); - - \r.ilevel_RNIKLH65[7]\ : AOI1 - port map(A => \irl_0_a2_0[2]\, B => N_386, C => - \irl_0_1[2]\, Y => \irl[2]\); - - \r.ipend_RNO[1]\ : NOR3C - port map(A => N_515, B => \ipend_0_i_0_1[1]\, C => rstn, Y - => N_70_i_0); - - \r.ipend_RNIDTH8[4]\ : OR2 - port map(A => \ipend[4]\, B => \iforce_0[4]\, Y => - \un1_temp[4]\); - - \r.ilevel_RNICTVV[4]\ : NOR2B - port map(A => \a[4]\, B => \a_i_0[6]\, Y => - \irl_0_a2_1_0_0[0]\); - - \r.iforce_0_0_i_0_a2[9]\ : OR3B - port map(A => irl_3, B => N_904, C => irl_1, Y => N_919); - - \r.ipend_RNO_1[4]\ : NOR3C - port map(A => N_407, B => N_406, C => \ipend_RNO_4[4]\, Y - => \ipend_0_i_0_1[4]\); - - \r.ilevel_RNI2N0G_0[8]\ : NOR3C - port map(A => \imask_0[8]\, B => \ilevel[8]\, C => N_291, Y - => N_165); - - \r.ilevel_RNIEEFC[9]\ : OR2B - port map(A => \ilevel[9]\, B => \prdata_0_sqmuxa\, Y => - N_473); - - prdata_2_sqmuxa_0_a2_0_a2 : NOR2A - port map(A => paddr_0(3), B => paddr(7), Y => N_885); - - \r.ipend_RNO_0[2]\ : OR2 - port map(A => \iforce_0[2]\, B => N_925, Y => - \ipend_RNO_0[2]\); - - \r.ipend_RNO[10]\ : NOR3C - port map(A => \ipend_RNO_0[10]\, B => \ipend_0_i_0_1[10]\, - C => rstn, Y => N_15_i_0); - - \r.imask_0_RNO[15]\ : NOR2B - port map(A => rstn, B => N_535, Y => \imask_0_RNO[15]\); - - \r.ilevel_RNIUE0G_0[7]\ : OR3A - port map(A => \imask_0[7]\, B => N_350, C => \ilevel[7]\, Y - => \a_1[7]\); - - \r.ilevel_RNIOL001[7]\ : OR2B - port map(A => \a_1[7]\, B => \a_1_i_0[6]\, Y => N_414); - - \r.ilevel_RNI8GPB1[8]\ : OR3A - port map(A => \a_i_i[9]\, B => N_883, C => N_165, Y => - \irl_0_0_i_1_tz_1[1]\); - - \r.ilevel_RNI4LJUR[14]\ : OR2B - port map(A => irl_02_1, B => N_240, Y => irl_02_i); - - \r.ipend_0_i_0_a6_2[13]\ : NAND2 - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[13]\, Y => - N_876); - - \r.ilevel_RNITD95[10]\ : NOR2B - port map(A => \ilevel[10]\, B => \imask_0[10]\, Y => - \a_i_i_o2_0_o6_0[10]\); - - \r.ilevel_RNI0QNB[12]\ : OR3B - port map(A => \imask_0[12]\, B => N_298, C => \ilevel[12]\, - Y => N_13); - - \r.iforce_0_RNO_0[15]\ : NOR3C - port map(A => N_442, B => N_441, C => \iforce_0_RNO_3[15]\, - Y => \iforce_0_0_i_0_1[15]\); - - \r.ipend_RNINHI8[9]\ : OR2 - port map(A => \ipend[9]\, B => \iforce_0[9]\, Y => N_285); - - \r.ilevel_RNIAGTF2[1]\ : AO1B - port map(A => N_402_i, B => N_271, C => \irl_0_a2_1_0_0[0]\, - Y => \irl_0_a2_1[0]\); - - \r.ipend_RNO_2[7]\ : AO1D - port map(A => N_261, B => N_258_0, C => \ipend[7]\, Y => - \ipend_RNO_2[7]\); - - \r.ipend_RNO_0[13]\ : OR2A - port map(A => N_926, B => \iforce_0[13]\, Y => N_874); - - \r.ipend_RNO_1[12]\ : NOR3C - port map(A => N_877_i, B => N_881, C => N_882, Y => - \ipend_0_i_0_1[12]\); - - \r.irl_0_RNO_1[2]\ : NOR2 - port map(A => N_418, B => N_414, Y => N_419_i); - - \r.iforce_0_RNO_2[5]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(5), Y => - N_834); - - \r.imask_0_RNIF5LB[5]\ : OR2B - port map(A => \imask_0[5]\, B => N_895, Y => N_367); - - \r.iforce_0_RNIM0L8[4]\ : NOR2B - port map(A => \iforce_0[4]\, B => paddr(7), Y => - prdata_13_m_1_0(4)); - - \r.ipend_RNO_0[10]\ : OR2 - port map(A => \iforce_0[10]\, B => N_921, Y => - \ipend_RNO_0[10]\); - - \r.imask_0_RNI0J0B[15]\ : OR2B - port map(A => \imask_0[15]\, B => N_895, Y => N_486); - - \r.ipend_RNO_4[10]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[10]\, Y => - N_497); - - \r.imask_0_RNO[13]\ : NOR2B - port map(A => rstn, B => N_533, Y => N_397); - - \r.ilevel_RNIFDE7[9]\ : NOR2A - port map(A => \imask_0[9]\, B => \ilevel[9]\, Y => - \a_1_i_s_0_0[9]\); - - \r.iforce_0_RNO_3[15]\ : AO1 - port map(A => N_266_i, B => pwdata_0(15), C => - \iforce_0[15]\, Y => \iforce_0_RNO_3[15]\); - - \r.ilevel_RNI84GN_0[12]\ : OR2 - port map(A => \a[14]\, B => N_883, Y => N_384); - - \r.irl_0_RNO_5[0]\ : OR2A - port map(A => \a_1[11]\, B => N_417, Y => N_426); - - \r.ipend_RNO[4]\ : NOR3C - port map(A => \ipend_RNO_0[4]\, B => \ipend_0_i_0_1[4]\, C - => rstn, Y => N_76_i_0); - - \r.ilevel_RNI3Q95_0[13]\ : NOR2A - port map(A => \imask_0[13]\, B => \ilevel[13]\, Y => - \a_1_0[13]\); - - \r.ilevel_RNIGKGN_0[15]\ : NOR2B - port map(A => \a_i_0[13]\, B => \a[15]\, Y => - \irl_i_a2_0_0[3]\); - - \r.ilevel_RNIEK0G1[5]\ : AOI1B - port map(A => \a_i_0[6]\, B => \a[5]\, C => \a[7]\, Y => - \irl_0_3_tz_0[0]\); - - \r.imask_0_RNII5LB[8]\ : OR2B - port map(A => \imask_0[8]\, B => N_895, Y => N_470); - - \r.ilevel_RNIGRVT4[14]\ : AO1A - port map(A => N_311, B => \irl_0_0_i_a6_1[1]\, C => N_506, - Y => \irl_0_0_i_0[1]\); - - \r.ilevel[5]\ : DFN1E1 - port map(D => pwdata_0(5), CLK => lclk_c, E => N_827, Q => - \ilevel[5]\); - - \r.ilevel_RNIQ60G_0[6]\ : OR2 - port map(A => \ilevel[6]\, B => N_24, Y => \a_1_i_0[6]\); - - \r.irl_0_RNO_8[0]\ : OR3A - port map(A => N_17, B => N_4, C => \ilevel[1]\, Y => - N_435_i); - - \r.ipend[2]\ : DFN1 - port map(D => N_627_i_0, CLK => lclk_c, Q => \ipend[2]\); - - \r.iforce_0_RNO_1[13]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_27, Y => - N_448); - - \r.ipend_RNO[5]\ : NOR3C - port map(A => \ipend_RNO_0[5]\, B => \ipend_0_i_1[5]\, C - => rstn, Y => N_794_i_0); - - \r.ipend_RNI3CE6[14]\ : NOR2 - port map(A => \ipend[14]\, B => \iforce_0[14]\, Y => N_270); - - \r.imask_0_RNO_0[3]\ : MX2 - port map(A => \imask_0[3]\, B => pwdata_0(3), S => - imask_0_1_sqmuxa, Y => N_523); - - \r.ipend_RNO_0[14]\ : OR2 - port map(A => \iforce_0[14]\, B => N_931, Y => - \ipend_RNO_0[14]\); - - \r.ipend_RNO_4[14]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[14]\, Y => - N_455); - - \r.ipend_0_i_0_a6[2]\ : OR2 - port map(A => N_264, B => \ipend_0_i_0_a6_0[2]\, Y => - N_818_i); - - \r.imask_0_RNO_0[11]\ : MX2 - port map(A => \imask_0[11]\, B => pwdata_0(11), S => - imask_0_1_sqmuxa, Y => N_531); - - \r.imask_0_RNIB5LB[1]\ : OR2B - port map(A => \imask_0[1]\, B => N_895, Y => N_504); - - \r.ilevel_RNI2N0G[8]\ : OR3B - port map(A => \imask_0[8]\, B => N_291, C => \ilevel[8]\, Y - => N_792); - - \r.iforce_0[14]\ : DFN1 - port map(D => N_710_i_0, CLK => lclk_c, Q => \iforce_0[14]\); - - \r.ipend_RNI18E6[13]\ : OR2 - port map(A => \ipend[13]\, B => \iforce_0[13]\, Y => N_306); - - \r.irl_0_RNO_0[1]\ : AO1B - port map(A => \irl_1_0_a2_0_1[1]\, B => N_421, C => - \irl_1_0_1[1]\, Y => \irl_1[1]\); - - \r.imask_0_RNO_0[13]\ : MX2 - port map(A => \imask_0[13]\, B => pwdata_0(13), S => - imask_0_1_sqmuxa, Y => N_533); - - \r.ipend_RNO_4[3]\ : AO1D - port map(A => N_261, B => N_258_0, C => \ipend[3]\, Y => - N_368); - - \r.ipend_RNIDTGB[6]\ : OAI1 - port map(A => \iforce_0[6]\, B => \ipend[6]\, C => - \imask_0[6]\, Y => N_24); - - \r.ipend_RNO_5[12]\ : OR2 - port map(A => pirq_10, B => \ipend[12]\, Y => - \ipend_0_i_0_a6_0[12]\); - - \r.ipend_0_i_a2[5]\ : NOR2 - port map(A => N_258_0, B => \ipend_0_i_a2_0[5]\, Y => N_894); - - \r.irl_0_RNO_6[1]\ : OR2A - port map(A => N_795, B => \a_1[11]\, Y => N_422); - - \r.iforce_0_RNO_2[11]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(11), Y => - N_450); - - \r.ipend_RNIE4DC[13]\ : OR2B - port map(A => \ipend[13]\, B => \prdata_1_sqmuxa\, Y => - N_480); - - \r.ipend_0_i_0_a6_1[9]\ : NAND2 - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[9]\, Y => - N_830); - - \r.iforce_0_RNIU9HH1[15]\ : OR3C - port map(A => N_484, B => N_483, C => - \prdata_0_iv_0_0_1[15]\, Y => prdata_13); - - \r.ipend[9]\ : DFN1 - port map(D => N_702_i_0, CLK => lclk_c, Q => \ipend[9]\); - - \r.ipend_RNO[14]\ : NOR3C - port map(A => \ipend_RNO_0[14]\, B => \ipend_0_i_0_1[14]\, - C => rstn, Y => N_704_i_0); - - \r.iforce_0_RNO_0[6]\ : NOR3C - port map(A => N_838, B => N_837, C => \iforce_0_RNO_3[6]\, - Y => \iforce_0_0_i_0_1[6]\); - - \r.irl_0_RNO_0[0]\ : NOR3C - port map(A => \irl_1_0_1[0]\, B => \irl_0_RNO_2[0]\, C => - \irl_1_0_3[0]\, Y => \irl_1_i[0]\); - - \r.ipend_0_i_o2_0[5]\ : OR2 - port map(A => un1_apbi_1, B => N_257, Y => N_258); - - \r.imask_0_RNO[7]\ : NOR2B - port map(A => rstn, B => N_527, Y => \imask_0_RNO[7]\); - - \r.irl_0_RNO_3[0]\ : AO1B - port map(A => \irl_1_0_3_tz_0[0]\, B => \irl_1_0_a2_1[0]\, - C => N_437, Y => \irl_1_0_3[0]\); - - \r.iforce_0_RNO_0[1]\ : NOR3C - port map(A => N_454, B => N_453, C => \iforce_0_RNO_3[1]\, - Y => \iforce_0_0_i_0_1[1]\); - - \r.ilevel_RNI42OB_0[13]\ : OR2B - port map(A => \a_i_0_o6_0[13]\, B => N_306, Y => - \a_i_0[13]\); - - \r.iforce_0_RNO_0[4]\ : NOR3C - port map(A => N_489, B => N_488, C => \iforce_0_RNO_3[4]\, - Y => \iforce_0_0_i_0_1[4]\); - - \prdata_0_iv_0_a2[6]\ : NOR2A - port map(A => \prdata_0_iv_0_a2_0[6]_net_1\, B => N_884, Y - => N_895); - - \r.irl_0_RNO_3[1]\ : AOI1B - port map(A => N_431_1, B => N_422, C => \irl_1_0_0[1]\, Y - => \irl_1_0_1[1]\); - - \r.ipend_RNO[15]\ : NOR3C - port map(A => N_494, B => \ipend_0_i_0_1[15]\, C => rstn, Y - => N_648_i_0); - - \r.iforce_0_RNIBKEE[4]\ : OR3C - port map(A => N_885, B => \iforce_0[4]\, C => N_896, Y => - iforce_0_m(4)); - - \r.iforce_0_0_i_0_a2_1[6]\ : NOR2 - port map(A => irl_0_d0, B => N_889, Y => N_905); - - \r.ipend_RNIJ9I8[7]\ : NOR2 - port map(A => \ipend[7]\, B => \iforce_0[7]\, Y => N_350); - - \r.iforce_0_RNO_2[7]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(7), Y => - N_867); - - \r.ipend_0_i_0_a6_1_RNO[15]\ : OR2A - port map(A => pwdata_0(15), B => pirq_13, Y => - \ipend_0_i_0_a6_1_0[15]\); - - \r.imask_0[1]\ : DFN1 - port map(D => \imask_0_RNO[1]\, CLK => lclk_c, Q => - \imask_0[1]\); - - \r.ipend_RNO_3[6]\ : OR3A - port map(A => pwdata_0(6), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_410); - - \r.ipend_0_i_0_a6_RNO[13]\ : OR2 - port map(A => \ipend[13]\, B => pirq_11, Y => - \ipend_0_i_0_a6_0[13]\); - - \r.ipend[14]\ : DFN1 - port map(D => N_704_i_0, CLK => lclk_c, Q => \ipend[14]\); - - \r.iforce_0_RNICA3Q[14]\ : AOI1B - port map(A => \iforce_0[14]\, B => \N_898\, C => N_438, Y - => prdata_0_iv_0_0_0_13); - - \r.imask_0_RNO[5]\ : NOR2B - port map(A => rstn, B => N_525, Y => N_389); - - \r.ilevel_RNIMUVF_0[5]\ : NOR2 - port map(A => \ilevel[5]\, B => N_20, Y => \a_1[5]\); - - \r.iforce_0[10]\ : DFN1 - port map(D => N_84_i_0, CLK => lclk_c, Q => \iforce_0[10]\); - - \r.ilevel_RNI0B002[7]\ : OR3B - port map(A => \a_i_0[6]\, B => \a[7]\, C => N_385, Y => - N_386); - - \r.iforce_0_RNO_3[9]\ : AO1 - port map(A => N_266_i, B => pwdata_0(9), C => \iforce_0[9]\, - Y => \iforce_0_RNO_3[9]\); - - \r.irl_0_RNO_1[0]\ : NOR3B - port map(A => \irl_0_RNO_4[0]\, B => N_426, C => \a_1[15]\, - Y => \irl_1_0_1[0]\); - - \r.imask_0_RNO_0[2]\ : MX2 - port map(A => \imask_0[2]\, B => pwdata_0(2), S => - imask_0_1_sqmuxa, Y => N_522); - - \r.imask_0_RNO[2]\ : NOR2B - port map(A => rstn, B => N_522, Y => \imask_0_RNO[2]\); - - \r.ipend_RNO[2]\ : NOR3C - port map(A => \ipend_RNO_0[2]\, B => \ipend_0_i_0_1[2]\, C - => rstn, Y => N_627_i_0); - - \r.ilevel_RNI4C2QH[11]\ : NOR3C - port map(A => \irl[2]\, B => N_400, C => \irl_i_0[0]\, Y - => irl_02_1); - - prdata_1_sqmuxa_0_a2_0_a2 : NOR2 - port map(A => N_261, B => N_257, Y => \prdata_1_sqmuxa\); - - \r.ipend_RNO_4[4]\ : AO1D - port map(A => N_261, B => N_258_0, C => \ipend[4]\, Y => - \ipend_RNO_4[4]\); - - \r.ipend_RNI96KT[2]\ : NOR2B - port map(A => N_463, B => N_464, Y => - \prdata_0_iv_0_0_0[2]\); - - \r.iforce_0_RNO_2[1]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(1), Y => - N_453); - - \r.ipend_0_i_0_a6_RNO[2]\ : OR2 - port map(A => \ipend[2]\, B => pirq_0, Y => - \ipend_0_i_0_a6_0[2]\); - - \r.ipend_RNIBAKT[3]\ : NOR2B - port map(A => N_519, B => N_520, Y => - \prdata_0_iv_0_0_0[3]\); - - \r.iforce_0_RNI1PGR[13]\ : AOI1B - port map(A => \iforce_0[13]\, B => \N_898\, C => N_480, Y - => prdata_0_iv_0_0_0_12); - - \r.ilevel_RNINLVA[13]\ : OR2B - port map(A => \ilevel[13]\, B => \prdata_0_sqmuxa\, Y => - N_481); - - \r.ipend_RNO_0[11]\ : OR2 - port map(A => \iforce_0[11]\, B => N_927, Y => - \ipend_RNO_0[11]\); - - \r.ipend_RNO_4[11]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[11]\, Y => - N_459); - - \r.ipend_RNITVD6[11]\ : OR2 - port map(A => \ipend[11]\, B => \iforce_0[11]\, Y => N_289); - - \r.iforce_0_RNO[8]\ : NOR3C - port map(A => N_929, B => \iforce_0_0_i_0_1[8]\, C => rstn, - Y => N_80_i_0); - - \r.iforce_0_RNO[14]\ : NOR3C - port map(A => N_931, B => \iforce_0_0_i_0_1[14]\, C => rstn, - Y => N_710_i_0); - - \r.iforce_0[3]\ : DFN1 - port map(D => N_601_i_0, CLK => lclk_c, Q => \iforce_0[3]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity apbuart is - - port( pwdata_12 : in std_logic; - pwdata_13 : in std_logic; - pwdata_14 : in std_logic; - pwdata_0_d0 : in std_logic; - pwdata_2 : in std_logic; - pwdata_5 : in std_logic; - pwdata_6 : in std_logic; - pwdata_7 : in std_logic; - pwdata_8 : in std_logic; - pwdata_9 : in std_logic; - pwdata_10 : in std_logic; - pwdata_11 : in std_logic; - pirq : out std_logic_vector(2 to 2); - rcnt_RNI8FBM3 : out std_logic_vector(1 to 1); - rdata_2_0 : out std_logic; - pwdata_1_0 : in std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - paddr : in std_logic_vector(4 to 4); - rdata_2_m_3 : out std_logic; - rdata_2_m_4 : out std_logic; - rdata_2_m_2 : out std_logic; - brate_0 : out std_logic; - brate_10 : out std_logic; - brate_9 : out std_logic; - brate_8 : out std_logic; - brate_7 : out std_logic; - brate_6 : out std_logic; - brate_m_3 : out std_logic; - brate_m_2 : out std_logic; - brate_m_9 : out std_logic; - pwdata_0 : in std_logic_vector(11 downto 0); - rcnt_0 : out std_logic; - rcnt_1 : out std_logic; - rdata_17_m_0_d0 : out std_logic; - rdata_17_m_5 : out std_logic; - rdata_17_m_4 : out std_logic; - un1_uart1_34 : out std_logic; - rdata_17_m_0_4 : out std_logic; - rdata_iv_0_a2_3_0 : out std_logic_vector(7 to 7); - tcnt_0 : out std_logic; - tcnt_1 : out std_logic; - rdata_iv_2 : out std_logic_vector(3 downto 2); - rdata_iv_0_2 : out std_logic_vector(1 to 1); - prdata_6 : out std_logic; - prdata_0 : out std_logic; - prdata_9 : out std_logic; - paddr_0 : in std_logic_vector(4 to 4); - apbuart_VCC : in std_logic; - apbuart_GND : in std_logic; - rxd1_c : in std_logic; - lclk_c : in std_logic; - txd1_c : out std_logic; - N_227 : out std_logic; - thempty_1_m : out std_logic; - debug_m : out std_logic; - N_232 : in std_logic; - rdata60 : in std_logic; - frame : out std_logic; - rdata59 : in std_logic; - parerr_m : out std_logic; - rdata60_4 : out std_logic; - rdata62 : out std_logic; - N_6455_0 : in std_logic; - rdata59_4 : out std_logic; - parsel_m_0 : out std_logic; - ovf_m : out std_logic; - break_m : out std_logic; - N_223 : out std_logic; - N_220 : out std_logic; - rfifoirqen_m : out std_logic; - tfifoirqen_m : out std_logic; - N_156 : out std_logic; - rhalffull_1_m : out std_logic; - rdata_3_sqmuxa : out std_logic; - ctrl2 : in std_logic; - rstn : in std_logic; - tsemptyirqen_0 : out std_logic; - N_773 : in std_logic; - N_769 : in std_logic; - paren : out std_logic; - N_750 : in std_logic; - penable : in std_logic; - breakirqen : out std_logic; - delayirqen : out std_logic; - rdata_4_sqmuxa : out std_logic; - rdata_0_sqmuxa : out std_logic; - tcnt_i : out std_logic; - flow_m : out std_logic; - extclken_m : out std_logic; - rdata61 : in std_logic; - pwrite : in std_logic; - un1_apbi_8 : in std_logic; - rdata62_0 : out std_logic; - rdata60_1 : in std_logic; - rdata61_2 : in std_logic; - rdata60_4_0 : out std_logic - ); - -end apbuart; - -architecture DEF_ARCH of apbuart is - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component RAM512X18 - generic (MEMORYFILE:string := ""); - - port( RADDR8 : in std_logic := 'U'; - RADDR7 : in std_logic := 'U'; - RADDR6 : in std_logic := 'U'; - RADDR5 : in std_logic := 'U'; - RADDR4 : in std_logic := 'U'; - RADDR3 : in std_logic := 'U'; - RADDR2 : in std_logic := 'U'; - RADDR1 : in std_logic := 'U'; - RADDR0 : in std_logic := 'U'; - WADDR8 : in std_logic := 'U'; - WADDR7 : in std_logic := 'U'; - WADDR6 : in std_logic := 'U'; - WADDR5 : in std_logic := 'U'; - WADDR4 : in std_logic := 'U'; - WADDR3 : in std_logic := 'U'; - WADDR2 : in std_logic := 'U'; - WADDR1 : in std_logic := 'U'; - WADDR0 : in std_logic := 'U'; - WD17 : in std_logic := 'U'; - WD16 : in std_logic := 'U'; - WD15 : in std_logic := 'U'; - WD14 : in std_logic := 'U'; - WD13 : in std_logic := 'U'; - WD12 : in std_logic := 'U'; - WD11 : in std_logic := 'U'; - WD10 : in std_logic := 'U'; - WD9 : in std_logic := 'U'; - WD8 : in std_logic := 'U'; - WD7 : in std_logic := 'U'; - WD6 : in std_logic := 'U'; - WD5 : in std_logic := 'U'; - WD4 : in std_logic := 'U'; - WD3 : in std_logic := 'U'; - WD2 : in std_logic := 'U'; - WD1 : in std_logic := 'U'; - WD0 : in std_logic := 'U'; - RW0 : in std_logic := 'U'; - RW1 : in std_logic := 'U'; - WW0 : in std_logic := 'U'; - WW1 : in std_logic := 'U'; - PIPE : in std_logic := 'U'; - REN : in std_logic := 'U'; - WEN : in std_logic := 'U'; - RCLK : in std_logic := 'U'; - WCLK : in std_logic := 'U'; - RESET : in std_logic := 'U'; - RD17 : out std_logic; - RD16 : out std_logic; - RD15 : out std_logic; - RD14 : out std_logic; - RD13 : out std_logic; - RD12 : out std_logic; - RD11 : out std_logic; - RD10 : out std_logic; - RD9 : out std_logic; - RD8 : out std_logic; - RD7 : out std_logic; - RD6 : out std_logic; - RD5 : out std_logic; - RD4 : out std_logic; - RD3 : out std_logic; - RD2 : out std_logic; - RD1 : out std_logic; - RD0 : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal brate_1_sqmuxa_0, un1_apbi_2, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_12[0]\, \irqcnt[2]\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, \irqcnt[4]\, - \DWACT_ADD_CI_0_TMP[0]\, \irqcnt[1]\, N_45, - \un1_uart1[3]\, \un1_uart1[2]\, N_37, \un1_uart1[5]\, - \DWACT_FDEC_E[0]\, N_14, \un1_uart1[10]\, - \DWACT_FDEC_E[4]\, un1_apbi_1_i, \un1_apbi_1\, un1_apbi_6, - N_194, \thold[7]\, N_134, CO1, \rxclk[0]\, \rxclk[1]\, - extclken, \prdata[31]\, flow, \tshift_13[7]\, - \tshift_13_0_iv_0_0[7]\, twaddr_0_sqmuxa, - twaddr_0_sqmuxa_0, rxtick_0_0, tick, \rxclk[2]\, - rxtick_0_1, N_193, N_192, thold_32, \tcnt[2]\, - \rxstate_srsts_0_a3_0_0[2]\, rxtick, N_876, - \tshift_1_0_0[0]\, \tshift_1_0_a2_0[0]\, N_260, N_218, - irq_1_0, un4_thalffull_0, un4_rhalffull, \un1_uart1[34]\, - \rdata_iv_0_1[1]\, N_165, \rdata_iv_0_0[1]\, - traddr_1_sqmuxa, \thold[2]\, N_225, \rdata_iv_0[2]\, - \rdata_2_m[2]\, rirqen_m, \rdata_17_m_0[2]\, \brate_m[2]\, - tirqen, \rdata_iv_1[3]\, \rdata_17_m[3]\, \brate_m[3]\, - \rdata_2_m[3]\, un6_thempty_1, \tcnt_11[0]\, thempty_1, - \tcnt_11[1]\, SUM2_0_1, N_914, \rcnt[2]\, rraddr_0_sqmuxa, - SUM2_0_0, N_22, SUM1_0_0, N_913_i, irq_10_1, irq_5, - irq_10_0, rirqen_m_1, SUM1_0_0_0, irq_6_m_0, \delayirqen\, - irq10, rhold_1_0_sqmuxa_0, \rwaddr[0]\, \rwaddr[1]\, - rhold_2_0_sqmuxa_0, \thold[3]\, N_155, \thold[8]\, - \tshift_13_0_iv_0_0[6]\, txtick_1_sqmuxa, \tshift[6]\, - N_189, traddr_1_sqmuxa_0, \rdata62_0\, txtick_0_i_1, - \txclk[2]\, CO1_0, un1_apbi_2_0, \txstate_ns_i_0_0[0]\, - \txstate_ns_i_0_a2_3_1[0]\, N_209, txtick_1, txtick, - debug, frame_1_sqmuxa_0, \rxdb[0]\, frame_1_sqmuxa_1, - \rxstate_nss_i_0_0_0_tz_0[0]\, \rxstate[0]\, \rxstate[1]\, - tpar, N_247, \paren\, \txstate[0]\, \tshift[1]\, - dpar_4_m_0, N_906, dpar_4, \txstate_ns_i_0_1_tz_0[0]\, - break6_5, break6_3, \rshift[3]\, \rshift[0]\, break6_4, - break6_1, \rshift[2]\, \rshift[1]\, \rshift[6]\, - \rshift[4]\, \rshift[5]\, \rshift[7]\, - rwaddr_0_sqmuxa_1_1, dpar, rwaddr_0_sqmuxa_1_0, - tfifoirqen, \txstate_ns_i_0_a2_4_5[0]\, - \txstate_ns_i_0_a2_4_2[0]\, \txstate_ns_i_0_a2_4_3[0]\, - \tshift[8]\, \tshift[9]\, \tshift[7]\, - \txstate_ns_i_0_a2_4_1[0]\, \tshift[4]\, \tshift[5]\, - \txstate_ns_i_0_a2_4_0[0]\, \tshift[2]\, \tshift[3]\, - un4_rhalffull_0, rfifoirqen, I_5_0, \WADDR_REG1[1]\, - \traddr[1]\, N_5, \thold[4]\, \rdata_4_sqmuxa\, - \thold[5]\, tick_1, txen, tick_2_i, \tshift_13[4]\, N_184, - N_183, N_185, \tshift_13[1]\, N_175, N_174, N_176, - un1_apbi_5, \tshift_13[8]\, N_196, N_195, N_197, - tsemptyirqen, tsempty, tsempty_4, un6_thempty, CO1_1, - irq_1, irq_16_i, rhalffull_1, \tshift_13[6]\, \thold[6]\, - rxtick_RNO, rshift_0_sqmuxa_1, N_98, irqpend_0_sqmuxa, - irqpend_1_sqmuxa, irqpend_1, rirqen, irq_10_i, irq_6_m, - rirqen_m_0, break_0_sqmuxa, delayirqen_0, irq_14, irq_7_m, - irq_10_m, \rxstate_nss_i[0]\, N_78, - \rxstate_nss_i_0_0_0[0]\, N_897, rxdb_1, \un1_uart1[36]\, - \rxdb[1]\, N_86, N_204, N_205, ovf_0_sqmuxa, \rcnt_1\, - \rxstate_i[4]\, N_69, N_199, \tcnt[1]\, N_9, txtick_0, - un2_ctsn_1, irq_5_2, \thold[1]\, N_167, \tshift[0]\, - loopb, N_929, N_210, \txstate_ns_i_0_1[0]\, N_133, - N_210_1, N_17_i_0, N_172, N_171, N_170, \rxf[2]\, - \rxf[3]\, \rxf[4]\, N_143, N_214, N_243, \tshift_13[3]\, - N_181, N_180, N_182, \tshift_13[5]\, N_187, N_186, N_188, - \tshift_1[0]\, N_219, N_7, \WADDR_REG1[0]\, \traddr[0]\, - break6, N_898, N_88, N_206, N_207, N_142, rwaddr_0_sqmuxa, - rsempty, rcnt, \tshift_13[2]\, N_178, N_177, N_179, - rhold_2_0_sqmuxa, rwaddr_0_sqmuxa_0, rhold_1_0_sqmuxa, - \rxstate_nss_i_0_a3_0[0]\, CO1_i_o3_0, N_16, CO1_i_o3_0_0, - N_16_0, \txstate_ns_i_0_a2_2_0[0]\, \rxstate_nss[1]\, - \rxstate_RNO_0[3]\, \rxstate[3]\, \tcnt_i\, \tcnt[0]\, - CO1_2, N_9_0, N_649, breakirqen_1_sqmuxa, \DIN_REG1[0]\, - \DOUT_TMP[0]\, \DIN_REG1[1]\, \DOUT_TMP[1]\, - \DIN_REG1[2]\, \DOUT_TMP[2]\, \DIN_REG1[3]\, - \DOUT_TMP[3]\, \DIN_REG1[4]\, \DOUT_TMP[4]\, - \DIN_REG1[6]\, \DOUT_TMP[6]\, \DIN_REG1[7]\, - \DOUT_TMP[7]\, \brate[11]\, N_503, \brate[1]\, I_5_4, - N_504, \brate[2]\, I_9_4, \scaler_1[1]\, \scaler_1[2]\, - I_66_1, \un1_uart1[13]\, N_505, \brate[3]\, I_13_8, N_507, - \brate[5]\, I_24_4, N_508, I_31_3, N_509, I_38_1, N_510, - I_45_1, N_511, I_52_1, N_512, I_56_1, N_513, - \scaler_1[3]\, \scaler_1[5]\, \scaler_1[6]\, - \scaler_1[7]\, \scaler_1[8]\, \scaler_1[9]\, - \scaler_1[10]\, \scaler_1[11]\, \rdata_2[7]\, - \rdata_0_sqmuxa\, N_100, scaler_2_sqmuxa, N_479, - \rhold_0[6]\, \rhold_2[6]\, \rraddr[1]\, \rdata_2[6]\, - N_487, \rraddr[0]\, \rdata_2[3]\, break, \N_156\, - rdata_3_sqmuxa_net_1, \rdata_2[4]\, ovf, parsel, - \brate[4]\, N_502, \scaler_1[0]\, brate_1_sqmuxa, N_477, - N_485, N_480, N_488, N_506, I_20_4, \scaler_1[4]\, - \txstate_RNIURTC6[1]\, \rdata62\, tsempty_RNO_0, - \tcnt_RNO[2]\, \tcnt_RNO_0[1]\, \tcnt_RNO_0[0]\, - \rhold_1[6]\, \rhold_3[6]\, \rdata_2[5]\, N_478, N_486, - parerr, \rhold_0[5]\, \rhold_2[5]\, \DIN_REG1[5]\, - \DOUT_TMP[5]\, N_666, N_860, \rshift_RNO_0[5]\, N_484, - \rhold_1[3]\, \rhold_3[3]\, \rhold_1[5]\, \rhold_3[5]\, - \rhold_0_1[3]\, rhold_0_1_sqmuxa_1, \rhold_3_1[4]\, - rhold_3_1_sqmuxa_1, \rhold_3_1[6]\, N_973_i, - rxclk_1_sqmuxa_1, N_869, \rxclk_1[0]\, \rxclk_1[1]\, - \rxclk_1[2]\, N_161, N_476, \rhold_0[3]\, \rhold_2[3]\, - dpar_RNI4PT94, \rhold_1_1[4]\, \rhold_1[7]\, \rhold_3[7]\, - N_483, \rhold_1[2]\, \rhold_3[2]\, \rhold_0[7]\, - \rhold_2[7]\, N_475, \rhold_0[2]\, \rhold_2[2]\, - \rdata_2[2]\, \rhold_0_1[4]\, \rhold_1[4]\, \rhold_3[4]\, - \rhold_0[4]\, \rhold_2[4]\, \rshift_RNO_0[4]\, N_665, - \rshift_RNO_0[3]\, N_664, N_638, rsempty_1, rxstate_5, - N_216, rsempty_1_sqmuxa, N_442, N_897_1, N_441, dpar_m_1, - \irqcnt[5]\, N_643, irqpend, N_110, rxtick_0, irq_7, - break_1_sqmuxa, N_641, frame_1, frame_0_sqmuxa, N_644, - parerr_1, parerr_0_sqmuxa_1, N_108, N_112, parerr_5, - parerr_0_sqmuxa, break_1, break_0_sqmuxa_1, \irqcnt_1[5]\, - I_26, \irqcnt_1[4]\, I_24_5, \irqcnt_1[3]\, I_23, - \irqcnt_1[2]\, I_22, \irqcnt_1[1]\, I_21, \irqcnt_1[0]\, - \DWACT_ADD_CI_0_partial_sum[0]\, N_114, N_640, ovf_RNO_0, - N_645, \txclk[1]\, N_976_i_2, N_29, N_29_1, N_473, - \rhold_0[0]\, \rhold_2[0]\, N_481, \rhold_1[0]\, - \rhold_3[0]\, N_163, N_164, \rhold_1[1]\, \rhold_3[1]\, - \rhold_0[1]\, \rhold_2[1]\, N_27, N_25, N_801, N_801s, - tpar_3_i, \txstate[1]\, txtick_0_sqmuxa_1, tpar_1, - txstate_1, \txstate_ns[1]\, \tshift_13_0_iv[9]\, N_802s, - N_802, N_661, \rshift_RNO_0[0]\, \rhold_0_1[6]\, - \rhold_3_1[0]\, \rhold_3_1[3]\, \rhold_3_1[5]\, N_667, - \rshift_RNO_0[6]\, \un26_rxd[0]\, rhold_0_0_sqmuxa, - \un26_rxd[3]\, rhold_3_0_sqmuxa, N_668, \rshift_RNO_0[7]\, - dpar_1, parsel_m, N_140, \rxstate[2]\, N_875, N_893, - \rxstate_nss[2]\, \rhold_0_1[1]\, N_235, \rhold_0_1[7]\, - \rhold_0_1[2]\, \rshift_RNO_0[2]\, N_663, - \rshift_RNO_0[1]\, N_662, \rcnt[1]\, N_646, N_647, N_104, - N_106, \rcnt[0]\, N_940_1, \rcnt_RNO[0]\, \rcnt_RNO[1]\, - \rcnt_RNO[2]\, N_102, N_648, \rraddr_RNO[1]\, I_10_2, - \rraddr_RNO[0]\, \DWACT_ADD_CI_0_partial_sum_0[0]\, - \rwaddr_RNO[1]\, I_10_0, \rwaddr_RNO[0]\, - \DWACT_ADD_CI_0_partial_sum_1[0]\, N_37_0, I_10, N_35, - \DWACT_ADD_CI_0_partial_sum_2[0]\, N_33, I_10_1, N_31, - \DWACT_ADD_CI_0_partial_sum_3[0]\, \irqcnt[0]\, - \irqcnt[3]\, \twaddr[0]\, \twaddr[1]\, \rxf[0]\, \rxf[1]\, - \brate[10]\, \brate[9]\, \brate[8]\, \brate[7]\, - \brate[6]\, \brate[0]\, \un1_uart1[12]\, \un1_uart1[11]\, - \un1_uart1[9]\, \un1_uart1[8]\, \un1_uart1[7]\, - \un1_uart1[6]\, \un1_uart1[4]\, \tsemptyirqen_0\, - \breakirqen\, \frame\, N_4, \DWACT_FDEC_E[6]\, - \DWACT_FDEC_E[2]\, \DWACT_FDEC_E[5]\, N_11, - \DWACT_FDEC_E[3]\, N_19, N_24, N_29_0, \DWACT_FDEC_E[1]\, - N_34, N_42, \DWACT_ADD_CI_0_TMP_0[0]\, - \DWACT_ADD_CI_0_TMP_1[0]\, \DWACT_ADD_CI_0_TMP_2[0]\, - \DWACT_ADD_CI_0_TMP_3[0]\, \DOUT_TMP[8]\, \DOUT_TMP[9]\, - \DOUT_TMP[10]\, \DOUT_TMP[11]\, \DOUT_TMP[12]\, - \DOUT_TMP[13]\, \DOUT_TMP[14]\, \DOUT_TMP[15]\, - \DOUT_TMP[16]\, \DOUT_TMP[17]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - brate_0 <= \brate[0]\; - brate_10 <= \brate[10]\; - brate_9 <= \brate[9]\; - brate_8 <= \brate[8]\; - brate_7 <= \brate[7]\; - brate_6 <= \brate[6]\; - rcnt_0 <= \rcnt[0]\; - rcnt_1 <= \rcnt[1]\; - un1_uart1_34 <= \un1_uart1[36]\; - tcnt_0 <= \tcnt[0]\; - tcnt_1 <= \tcnt[1]\; - prdata_9 <= \prdata[31]\; - frame <= \frame\; - rdata62 <= \rdata62\; - N_156 <= \N_156\; - rdata_3_sqmuxa <= rdata_3_sqmuxa_net_1; - tsemptyirqen_0 <= \tsemptyirqen_0\; - paren <= \paren\; - breakirqen <= \breakirqen\; - delayirqen <= \delayirqen\; - rdata_4_sqmuxa <= \rdata_4_sqmuxa\; - rdata_0_sqmuxa <= \rdata_0_sqmuxa\; - tcnt_i <= \tcnt_i\; - rdata62_0 <= \rdata62_0\; - - \r.rxen_RNIKPF53\ : NOR2A - port map(A => txen, B => brate_1_sqmuxa_0, Y => - scaler_2_sqmuxa); - - \r.thold_tile_I_1_RNI4VRO\ : MX2 - port map(A => \DIN_REG1[5]\, B => \DOUT_TMP[5]\, S => N_7, - Y => \thold[6]\); - - \r.irqcnt_RNO[0]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => - \DWACT_ADD_CI_0_partial_sum[0]\, Y => \irqcnt_1[0]\); - - \r.flow_RNICI551\ : OR2B - port map(A => flow, B => N_210_1, Y => un2_ctsn_1); - - \r.txstate_RNO_1[1]\ : AO1C - port map(A => \txstate[0]\, B => \txstate[1]\, C => N_214, - Y => \txstate_ns[1]\); - - \r.tshift_RNO_0[4]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[4]\, Y => N_184); - - \r.rsempty_RNO_2\ : OR2B - port map(A => frame_1_sqmuxa_1, B => \rxstate_i[4]\, Y => - rxstate_5); - - \r.rxstate_i[4]\ : DFN1 - port map(D => \rxstate_nss_i[0]\, CLK => lclk_c, Q => - \rxstate_i[4]\); - - \un1_r.irqcnt_I_33\ : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - \r.txtick_RNI1BJL2\ : AO1B - port map(A => txtick_0, B => N_133, C => txtick, Y => - txtick_1_sqmuxa); - - \r.thold_tile_I_1_RNI3RRO\ : MX2 - port map(A => \DIN_REG1[4]\, B => \DOUT_TMP[4]\, S => N_7, - Y => \thold[5]\); - - \r.rxstate_RNO[3]\ : OA1A - port map(A => rshift_0_sqmuxa_1, B => \rxstate_RNO_0[3]\, C - => rstn, Y => \rxstate_nss[1]\); - - \r.thold_tile_I_1_RNIHCSI4\ : OR3C - port map(A => N_155, B => \thold[6]\, C => \rdata_4_sqmuxa\, - Y => rdata_17_m_5); - - \r.tick_RNO\ : NOR3 - port map(A => txen, B => extclken, C => tick_2_i, Y => - tick_1); - - \r.tcnt_RNIQEOL[2]\ : NOR3 - port map(A => \tcnt[2]\, B => \tcnt[0]\, C => \tcnt[1]\, Y - => thempty_1); - - \r.flow_RNII2133\ : NAND2 - port map(A => \prdata[31]\, B => flow, Y => flow_m); - - \r.scaler_RNO[1]\ : MX2A - port map(A => N_503, B => pwdata_0(1), S => - brate_1_sqmuxa_0, Y => \scaler_1[1]\); - - \r.tshift_RNO_1[6]\ : OR3B - port map(A => txtick, B => \tshift[7]\, C => N_133, Y => - N_189); - - \r.rwaddr_RNI3BBD1_0[1]\ : NOR2B - port map(A => rwaddr_0_sqmuxa_0, B => \un26_rxd[0]\, Y => - rhold_3_1_sqmuxa_1); - - un4_scaler_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \un1_uart1[11]\, C - => \un1_uart1[12]\, Y => N_4); - - \r.scaler[2]\ : DFN1E0 - port map(D => \scaler_1[2]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[4]\); - - rdata_1_sqmuxa_i_o2 : OR2 - port map(A => un1_apbi_5, B => rdata59, Y => \N_156\); - - \r.brate[9]\ : DFN1E1 - port map(D => pwdata_9, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[9]\); - - \r.rshift_RNIL9DD1[6]\ : MX2 - port map(A => pwdata_0(6), B => \rshift[6]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_0_1[6]\); - - \rdata_3_sqmuxa\ : NOR2A - port map(A => rdata61, B => un1_apbi_5, Y => - rdata_3_sqmuxa_net_1); - - \r.irq_RNO_1\ : OA1C - port map(A => un4_thalffull_0, B => \tcnt_i\, C => - un4_rhalffull, Y => irq_1_0); - - \r.txstate_RNO_0[1]\ : MX2 - port map(A => \txstate[1]\, B => \txstate_ns[1]\, S => - txtick, Y => N_802); - - \r.rxdb[1]\ : DFN1 - port map(D => \rxdb[0]\, CLK => lclk_c, Q => \rxdb[1]\); - - \r.parsel_RNILR733\ : OR2B - port map(A => parsel, B => \prdata[31]\, Y => parsel_m_0); - - \r.tcnt_RNO[1]\ : NOR2B - port map(A => \tcnt_11[1]\, B => rstn, Y => \tcnt_RNO_0[1]\); - - \un1_r.irqcnt_I_22\ : XOR2 - port map(A => \irqcnt[2]\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_22); - - \r.break_RNO_2\ : OA1C - port map(A => break_0_sqmuxa, B => frame_1_sqmuxa_1, C => - break_1_sqmuxa, Y => break_0_sqmuxa_1); - - \r.rhold_0_RNIEH39[3]\ : MX2C - port map(A => \rhold_0[3]\, B => \rhold_2[3]\, S => - \rraddr[1]\, Y => N_476); - - \r.rcnt_RNI1K6F3[1]\ : OR2 - port map(A => rhalffull_1, B => \N_156\, Y => rhalffull_1_m); - - \r.txstate_RNO_0[0]\ : MX2 - port map(A => \txstate[0]\, B => N_929, S => txtick, Y => - N_801); - - \r.txd_RNO\ : OR3 - port map(A => debug, B => \tshift[0]\, C => loopb, Y => - N_167); - - \uartop.un1_apbi_6\ : NAND2 - port map(A => pwrite, B => un1_apbi_2, Y => un1_apbi_6); - - \r.scaler_RNO[4]\ : MX2A - port map(A => N_506, B => pwdata_0(4), S => - brate_1_sqmuxa_0, Y => \scaler_1[4]\); - - \r.parerr_RNO_0\ : MX2 - port map(A => parerr_1, B => parerr, S => parerr_0_sqmuxa_1, - Y => N_644); - - \un1_r.rcnt_1_0_1_CO1_i_o3_0\ : AO1B - port map(A => N_16, B => N_913_i, C => rraddr_0_sqmuxa, Y - => CO1_i_o3_0); - - un4_scaler_I_24 : XNOR2 - port map(A => N_34, B => \un1_uart1[7]\, Y => I_24_4); - - \r.rhold_3[1]\ : DFN1E0 - port map(D => \rhold_0_1[1]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[1]\); - - \r.rhold_0_RNO[4]\ : MX2 - port map(A => pwdata_1_3, B => \rshift[4]\, S => - rhold_0_1_sqmuxa_1, Y => \rhold_0_1[4]\); - - \r.brate[10]\ : DFN1E1 - port map(D => pwdata_10, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[10]\); - - \r.brate[4]\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => - brate_1_sqmuxa, Q => \brate[4]\); - - \v.tshift_13_0_iv_0[7]\ : NAND2 - port map(A => N_194, B => \tshift_13_0_iv_0_0[7]\, Y => - \tshift_13[7]\); - - \r.rshift_RNO_0[1]\ : MX2 - port map(A => \rshift[2]\, B => \rshift[1]\, S => N_860, Y - => N_662); - - \r.scaler_RNO_0[8]\ : MX2C - port map(A => \brate[8]\, B => I_45_1, S => tick_2_i, Y => - N_510); - - \r.rxdb_RNO_2[0]\ : OR3 - port map(A => loopb, B => \rxf[4]\, C => N_143, Y => N_170); - - \r.rshift_RNISEI8[1]\ : NOR2B - port map(A => break6_5, B => break6_4, Y => break6); - - \r.txclk_RNO[1]\ : XA1B - port map(A => N_976_i_2, B => \txclk[1]\, C => N_29_1, Y - => N_27); - - \r.rxen_RNO_0\ : MX2 - port map(A => \un1_uart1[36]\, B => pwdata_0(0), S => - breakirqen_1_sqmuxa, Y => N_647); - - \r.txstate_RNO_3[0]\ : OA1 - port map(A => \txstate_ns_i_0_a2_2_0[0]\, B => - \txstate_ns_i_0_1_tz_0[0]\, C => N_133, Y => - \txstate_ns_i_0_1[0]\); - - \r.scaler_RNO[8]\ : MX2A - port map(A => N_510, B => pwdata_0(8), S => - brate_1_sqmuxa_0, Y => \scaler_1[8]\); - - \r.rxstate_RNO_1[1]\ : NOR2 - port map(A => rxtick, B => \rxstate[1]\, Y => N_207); - - \r.rxdb_RNO_0[0]\ : OR3 - port map(A => \rxf[2]\, B => \rxf[3]\, C => loopb, Y => - N_172); - - \r.tshift_RNI6SH5[6]\ : NOR2B - port map(A => \txstate_ns_i_0_a2_4_2[0]\, B => - \txstate_ns_i_0_a2_4_3[0]\, Y => - \txstate_ns_i_0_a2_4_5[0]\); - - \r.rxdb_RNIKLUE[0]\ : OR2 - port map(A => \rxdb[0]\, B => frame_1_sqmuxa_1, Y => - frame_1_sqmuxa_0); - - \r.tshift_RNI5UO2[8]\ : NOR2B - port map(A => \tshift[8]\, B => \tshift[9]\, Y => - \txstate_ns_i_0_a2_4_3[0]\); - - \r.thold_tile_I_1\ : RAM512X18 - port map(RADDR8 => apbuart_GND, RADDR7 => apbuart_GND, - RADDR6 => apbuart_GND, RADDR5 => apbuart_GND, RADDR4 => - apbuart_GND, RADDR3 => apbuart_GND, RADDR2 => apbuart_GND, - RADDR1 => N_37_0, RADDR0 => N_35, WADDR8 => apbuart_GND, - WADDR7 => apbuart_GND, WADDR6 => apbuart_GND, WADDR5 => - apbuart_GND, WADDR4 => apbuart_GND, WADDR3 => apbuart_GND, - WADDR2 => apbuart_GND, WADDR1 => \twaddr[1]\, WADDR0 => - \twaddr[0]\, WD17 => apbuart_GND, WD16 => apbuart_GND, - WD15 => apbuart_GND, WD14 => apbuart_GND, WD13 => - apbuart_GND, WD12 => apbuart_GND, WD11 => apbuart_GND, - WD10 => apbuart_GND, WD9 => apbuart_GND, WD8 => - apbuart_GND, WD7 => pwdata_7, WD6 => pwdata_6, WD5 => - pwdata_5, WD4 => pwdata_1_3, WD3 => pwdata_1_2, WD2 => - pwdata_2, WD1 => pwdata_1_0, WD0 => pwdata_0_d0, RW0 => - apbuart_VCC, RW1 => apbuart_GND, WW0 => apbuart_VCC, WW1 - => apbuart_GND, PIPE => apbuart_GND, REN => apbuart_GND, - WEN => un1_apbi_1_i, RCLK => lclk_c, WCLK => lclk_c, - RESET => apbuart_VCC, RD17 => \DOUT_TMP[17]\, RD16 => - \DOUT_TMP[16]\, RD15 => \DOUT_TMP[15]\, RD14 => - \DOUT_TMP[14]\, RD13 => \DOUT_TMP[13]\, RD12 => - \DOUT_TMP[12]\, RD11 => \DOUT_TMP[11]\, RD10 => - \DOUT_TMP[10]\, RD9 => \DOUT_TMP[9]\, RD8 => - \DOUT_TMP[8]\, RD7 => \DOUT_TMP[7]\, RD6 => \DOUT_TMP[6]\, - RD5 => \DOUT_TMP[5]\, RD4 => \DOUT_TMP[4]\, RD3 => - \DOUT_TMP[3]\, RD2 => \DOUT_TMP[2]\, RD1 => \DOUT_TMP[1]\, - RD0 => \DOUT_TMP[0]\); - - \v.tshift_13_0_iv_0_a2_1[7]\ : OR2A - port map(A => \thold[7]\, B => N_134, Y => N_194); - - \r.loopb_RNI4NC73\ : OR2B - port map(A => loopb, B => \prdata[31]\, Y => N_220); - - \r.scaler[0]\ : DFN1E0 - port map(D => \scaler_1[0]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[2]\); - - \r.rxf[4]\ : DFN1E1 - port map(D => \rxf[3]\, CLK => lclk_c, E => tick, Q => - \rxf[4]\); - - \uartop.v.tcnt_11_0_0_1_CO1_i_o3_0\ : AO1C - port map(A => \tcnt[1]\, B => N_16_0, C => N_22, Y => - CO1_i_o3_0_0); - - \r.rhold_2[3]\ : DFN1E0 - port map(D => \rhold_3_1[3]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[3]\); - - \r.parerr_RNO_3\ : NOR2 - port map(A => parerr, B => dpar, Y => parerr_5); - - \r.thold_tile_I_1_RNI4KUK1\ : NOR2B - port map(A => \thold[7]\, B => N_155, Y => rdata_17_m_0_4); - - \r.scaler[6]\ : DFN1E0 - port map(D => \scaler_1[6]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[8]\); - - \r.thold_tile_I_1_RNI53SO\ : MX2 - port map(A => \DIN_REG1[6]\, B => \DOUT_TMP[6]\, S => N_7, - Y => \thold[7]\); - - \r.thold_tile_DIN_REG1[1]\ : DFN1 - port map(D => pwdata_1_0, CLK => lclk_c, Q => \DIN_REG1[1]\); - - \r.irqcnt_RNO[3]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_23, Y => - \irqcnt_1[3]\); - - \r.txstate_RNIVPSC_0[1]\ : NOR2 - port map(A => \txstate[1]\, B => \txstate[0]\, Y => N_133); - - \r.rhold_0_RNIGP39[4]\ : MX2C - port map(A => \rhold_0[4]\, B => \rhold_2[4]\, S => - \rraddr[1]\, Y => N_477); - - \r.thold_tile_DIN_REG1[7]\ : DFN1 - port map(D => pwdata_7, CLK => lclk_c, Q => \DIN_REG1[7]\); - - \un1_r.rcnt_1_0_1_SUM2_0_1\ : XOR3 - port map(A => N_914, B => \rcnt[2]\, C => rraddr_0_sqmuxa, - Y => SUM2_0_1); - - \r.tshift_RNO[9]\ : OA1A - port map(A => txtick_1_sqmuxa, B => \tshift[9]\, C => N_134, - Y => \tshift_13_0_iv[9]\); - - \r.rshift_RNIQJ42[6]\ : NOR2 - port map(A => \rshift[6]\, B => \rshift[4]\, Y => break6_3); - - \r.rhold_2[2]\ : DFN1E0 - port map(D => \rhold_0_1[2]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[2]\); - - \r.scaler_RNO_0[9]\ : MX2C - port map(A => \brate[9]\, B => I_52_1, S => tick_2_i, Y => - N_511); - - \r.brate[6]\ : DFN1E1 - port map(D => pwdata_6, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[6]\); - - \r.scaler_RNO[10]\ : MX2A - port map(A => N_512, B => pwdata_0(10), S => - brate_1_sqmuxa_0, Y => \scaler_1[10]\); - - \r.scaler[9]\ : DFN1E0 - port map(D => \scaler_1[9]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[11]\); - - \r.brate[2]\ : DFN1E1 - port map(D => pwdata_2, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[2]\); - - \r.txtick_RNO\ : NOR2B - port map(A => txtick_0_i_1, B => N_134, Y => N_98); - - un1_apbi_1 : NOR3B - port map(A => pwrite, B => un1_apbi_2, C => thold_32, Y => - \un1_apbi_1\); - - \r.brate_RNIASBR7[2]\ : AOI1B - port map(A => \rdata_17_m_0[2]\, B => \rdata_4_sqmuxa\, C - => \brate_m[2]\, Y => \rdata_iv_0[2]\); - - \r.irqpend_RNO_1\ : NOR3A - port map(A => rirqen, B => un4_rhalffull, C => - irqpend_0_sqmuxa, Y => irqpend_1); - - \r.irqpend_RNO\ : NOR2B - port map(A => N_643, B => rstn, Y => N_110); - - \r.rirqen\ : DFN1E1 - port map(D => pwdata_2, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => rirqen); - - \r.rsempty_RNO_0\ : MX2 - port map(A => rsempty, B => rsempty_1, S => rxstate_5, Y - => N_638); - - \r.thold_tile_I_1_RNI0FRO\ : MX2 - port map(A => \DIN_REG1[1]\, B => \DOUT_TMP[1]\, S => N_7, - Y => \thold[2]\); - - \r.txclk_RNO_0[0]\ : OR2B - port map(A => N_976_i_2, B => N_134, Y => N_199); - - \r.parerr_RNO_1\ : MX2B - port map(A => pwdata_0(5), B => parerr_5, S => - parerr_0_sqmuxa, Y => parerr_1); - - \r.rshift_RNO_0[4]\ : MX2 - port map(A => \rshift[5]\, B => \rshift[4]\, S => N_860, Y - => N_665); - - \r.rxstate_i_RNIVC7N[4]\ : OR2B - port map(A => rshift_0_sqmuxa_1, B => rstn, Y => N_869); - - \r.rshift_RNO[5]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_666, Y => - \rshift_RNO_0[5]\); - - \r.irqcnt[4]\ : DFN1 - port map(D => \irqcnt_1[4]\, CLK => lclk_c, Q => - \irqcnt[4]\); - - \r.txstate_RNI831J2[1]\ : OR2A - port map(A => N_133, B => txtick_0, Y => N_134); - - \un1_r.irqcnt_I_26\ : XOR2 - port map(A => \irqcnt[5]\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_26); - - un4_scaler_I_12 : OR3 - port map(A => \un1_uart1[2]\, B => \un1_uart1[3]\, C => - \un1_uart1[4]\, Y => N_42); - - \r.tsempty_RNILMPS2\ : MX2C - port map(A => txtick_0, B => tsempty, S => txstate_1, Y => - tsempty_4); - - un4_scaler_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \r.tcnt_RNIT9GE[2]\ : OR2 - port map(A => \tcnt[2]\, B => \tcnt[1]\, Y => \tcnt_i\); - - \r.txstate_RNO[0]\ : NOR2B - port map(A => N_801, B => rstn, Y => N_801s); - - \r.rraddr_RNO[1]\ : NOR2B - port map(A => I_10_2, B => rstn, Y => \rraddr_RNO[1]\); - - \uartop.v.tcnt_11_0_0_1_CO0_i_a3_0\ : NOR2 - port map(A => twaddr_0_sqmuxa, B => \tcnt[0]\, Y => N_16_0); - - \r.txstate_RNIURTC6[1]\ : AO1A - port map(A => N_134, B => rstn, C => traddr_1_sqmuxa, Y => - \txstate_RNIURTC6[1]\); - - \r.rxstate_RNO[0]\ : NOR3A - port map(A => rstn, B => N_204, C => N_205, Y => N_86); - - \r.rraddr_RNIRPSI[0]\ : MX2C - port map(A => N_163, B => N_164, S => \rraddr[0]\, Y => - N_165); - - \r.brate_RNIU3G83[4]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[4]\, Y => - brate_m_2); - - \r.scaler_RNO[0]\ : MX2A - port map(A => N_502, B => pwdata_0(0), S => - brate_1_sqmuxa_0, Y => \scaler_1[0]\); - - \r.rwaddr_RNI3BBD1[1]\ : NOR2B - port map(A => rwaddr_0_sqmuxa_0, B => \un26_rxd[3]\, Y => - rhold_0_1_sqmuxa_1); - - \r.rshift_RNIIDDD1[3]\ : MX2 - port map(A => pwdata_1_2, B => \rshift[3]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_3_1[3]\); - - \r.rxstate_RNO_1[2]\ : AO1A - port map(A => \rshift[0]\, B => rxtick, C => N_78, Y => - N_893); - - \r.extclken\ : DFN1 - port map(D => N_100, CLK => lclk_c, Q => extclken); - - \r.tshift_RNO[3]\ : OR3C - port map(A => N_181, B => N_180, C => N_182, Y => - \tshift_13[3]\); - - \r.rhold_1_RNIMP49[4]\ : MX2C - port map(A => \rhold_1[4]\, B => \rhold_3[4]\, S => - \rraddr[1]\, Y => N_485); - - \r.loopb\ : DFN1E1 - port map(D => pwdata_7, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => loopb); - - \r.rxstate_RNINFI6[2]\ : OR2A - port map(A => \rxstate[2]\, B => \rshift[0]\, Y => N_140); - - \r.tshift_RNO_2[4]\ : OR2A - port map(A => \thold[4]\, B => N_134, Y => N_185); - - \r.txclk[2]\ : DFN1E1 - port map(D => N_29, CLK => lclk_c, E => N_25, Q => - \txclk[2]\); - - \r.rhold_0[6]\ : DFN1E0 - port map(D => \rhold_0_1[6]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[6]\); - - \r.brate_RNIN3SP7[1]\ : AOI1B - port map(A => traddr_1_sqmuxa, B => \thold[2]\, C => N_225, - Y => \rdata_iv_0_0[1]\); - - \v.twaddr_0_sqmuxa_RNO\ : OR2 - port map(A => thold_32, B => \tcnt[2]\, Y => - twaddr_0_sqmuxa_0); - - \r.irqcnt_RNIF1F[5]\ : NOR2B - port map(A => \irqcnt[5]\, B => \irqcnt[4]\, Y => irq10); - - \r.scaler_RNO_0[3]\ : MX2C - port map(A => \brate[3]\, B => I_13_8, S => tick_2_i, Y => - N_505); - - \r.rcnt_RNI6ECJ3[1]\ : NOR3 - port map(A => un1_apbi_5, B => rcnt, C => ctrl2, Y => - rraddr_0_sqmuxa); - - \r.rhold_3[0]\ : DFN1E0 - port map(D => \rhold_3_1[0]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[0]\); - - \r.rcnt_RNO[0]\ : XA1 - port map(A => N_940_1, B => rraddr_0_sqmuxa, C => rstn, Y - => \rcnt_RNO[0]\); - - \r.rhold_0_RNII149[5]\ : MX2C - port map(A => \rhold_0[5]\, B => \rhold_2[5]\, S => - \rraddr[1]\, Y => N_478); - - \r.tpar_RNO_1\ : XNOR2 - port map(A => \tshift[1]\, B => tpar, Y => tpar_3_i); - - rdata_0_sqmuxa_0_a2_0 : OR2A - port map(A => un1_apbi_8, B => un1_apbi_5, Y => N_235); - - \r.rhold_0[0]\ : DFN1E0 - port map(D => \rhold_3_1[0]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[0]\); - - \r.txen_RNILLTDE\ : AOI1B - port map(A => \un1_uart1[34]\, B => \prdata[31]\, C => - \rdata_iv_0_1[1]\, Y => rdata_iv_0_2(1)); - - \uartop.rdata60_4\ : OR2 - port map(A => rdata61_2, B => rdata60_1, Y => rdata60_4); - - \r.rxstate_i_RNO_2[4]\ : AOI1B - port map(A => rxtick, B => \rxdb[0]\, C => \rxstate[3]\, Y - => \rxstate_nss_i_0_a3_0[0]\); - - \r.tpar_RNO_0\ : OR2A - port map(A => N_134, B => N_247, Y => txtick_0_sqmuxa_1); - - \r.rhold_1[6]\ : DFN1E0 - port map(D => \rhold_0_1[6]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[6]\); - - un4_scaler_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \un1_uart1[8]\, Y => N_24); - - \r.rraddr[0]\ : DFN1 - port map(D => \rraddr_RNO[0]\, CLK => lclk_c, Q => - \rraddr[0]\); - - \r.delayirqen_RNIGVAM\ : OR3B - port map(A => \rxdb[0]\, B => \delayirqen\, C => - frame_1_sqmuxa_1, Y => irqpend_0_sqmuxa); - - \uartop.v.irq_5_2\ : NOR3B - port map(A => pwrite, B => un1_apbi_2, C => \rdata62\, Y - => irq_5_2); - - \r.tsempty_RNO\ : OR2B - port map(A => tsempty_4, B => rstn, Y => tsempty_RNO_0); - - un4_scaler_I_45 : XNOR2 - port map(A => N_19, B => \un1_uart1[10]\, Y => I_45_1); - - \r.irqcnt_RNO[1]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_21, Y => - \irqcnt_1[1]\); - - \r.scaler_RNO_0[10]\ : MX2C - port map(A => \brate[10]\, B => I_56_1, S => tick_2_i, Y - => N_512); - - \r.irqpend_RNIP55E\ : NOR2B - port map(A => irqpend, B => \delayirqen\, Y => delayirqen_0); - - \r.rxstate_RNIT70B[2]\ : OR2 - port map(A => \rxstate[2]\, B => \rxstate[1]\, Y => N_906); - - \r.rhold_3[2]\ : DFN1E0 - port map(D => \rhold_0_1[2]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[2]\); - - \r.scaler_RNO_0[0]\ : MX2A - port map(A => \brate[0]\, B => \un1_uart1[2]\, S => - tick_2_i, Y => N_502); - - \r.rxf_RNO[3]\ : MX2 - port map(A => \rxf[3]\, B => \rxf[2]\, S => tick, Y => - N_161); - - \r.txstate_RNO_2[1]\ : OR3B - port map(A => N_243, B => N_260, C => \tshift[1]\, Y => - N_214); - - \r.ovf_RNO_0\ : MX2 - port map(A => ovf, B => pwdata_1_3, S => break_1_sqmuxa, Y - => N_645); - - \r.rraddr_RNIFAVI[0]\ : MX2C - port map(A => N_479, B => N_487, S => \rraddr[0]\, Y => - \rdata_2[6]\); - - \r.frame_RNO_1\ : AO1D - port map(A => frame_1_sqmuxa_0, B => break6, C => - pwdata_0(6), Y => frame_1); - - \r.brate[8]\ : DFN1E1 - port map(D => pwdata_8, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[8]\); - - \r.rshift[5]\ : DFN1 - port map(D => \rshift_RNO_0[5]\, CLK => lclk_c, Q => - \rshift[5]\); - - \r.debug\ : DFN1E1 - port map(D => pwdata_11, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => debug); - - un2_rxclk_1_SUM2_0 : AX1E - port map(A => \rxclk[0]\, B => \rxclk[1]\, C => \rxclk[2]\, - Y => N_973_i); - - \r.rshift_RNO[6]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_667, Y => - \rshift_RNO_0[6]\); - - \r.tshift_RNI1UO2[6]\ : NOR2B - port map(A => \tshift[6]\, B => \tshift[7]\, Y => - \txstate_ns_i_0_a2_4_2[0]\); - - \r.rxstate[1]\ : DFN1 - port map(D => N_88, CLK => lclk_c, Q => \rxstate[1]\); - - \r.rwaddr[1]\ : DFN1 - port map(D => \rwaddr_RNO[1]\, CLK => lclk_c, Q => - \rwaddr[1]\); - - \uartop.rdata62_0_a2_0\ : OR2B - port map(A => un1_apbi_8, B => paddr_0(4), Y => \rdata62_0\); - - \r.tshift[5]\ : DFN1 - port map(D => \tshift_13[5]\, CLK => lclk_c, Q => - \tshift[5]\); - - \v.tshift_13_0_iv_0_RNO_0[7]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[7]\, Y => N_193); - - \r.rxclk_RNO[0]\ : NOR2 - port map(A => \rxclk[0]\, B => N_869, Y => \rxclk_1[0]\); - - un4_scaler_I_38 : XNOR2 - port map(A => N_24, B => \un1_uart1[9]\, Y => I_38_1); - - \r.rsempty_RNO_1\ : MX2C - port map(A => N_442, B => N_897_1, S => N_441, Y => - rsempty_1); - - \r.rxstate_RNINPR6[0]\ : NOR2A - port map(A => rstn, B => \rxstate[0]\, Y => N_897_1); - - \r.irq_RNO_9\ : NOR3B - port map(A => break_0_sqmuxa, B => irq_10_i, C => - frame_1_sqmuxa_1, Y => irq_10_m); - - \uartop.rdata59_4\ : NOR2 - port map(A => rdata61_2, B => N_6455_0, Y => rdata59_4); - - \r.tshift_RNISN3B[2]\ : NOR3C - port map(A => \txstate_ns_i_0_a2_4_1[0]\, B => - \txstate_ns_i_0_a2_4_0[0]\, C => - \txstate_ns_i_0_a2_4_5[0]\, Y => N_260); - - \r.rxtick_RNO\ : NOR2B - port map(A => rxtick_0_1, B => rshift_0_sqmuxa_1, Y => - rxtick_RNO); - - \r.flow\ : DFN1 - port map(D => N_102, CLK => lclk_c, Q => flow); - - \r.rcnt_RNO[1]\ : XA1 - port map(A => N_9_0, B => SUM1_0_0, C => rstn, Y => - \rcnt_RNO[1]\); - - GND_i : GND - port map(Y => \GND\); - - \r.txtick_RNIO1FF_0\ : NOR2B - port map(A => txtick, B => N_243, Y => N_247); - - \uartop.v.tcnt_11_0_0_1_SUM2_0_0\ : XOR2 - port map(A => \tcnt[2]\, B => N_22, Y => SUM2_0_0); - - \r.rfifoirqen\ : DFN1E1 - port map(D => pwdata_10, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => rfifoirqen); - - \r.rshift_RNO_0[7]\ : MX2 - port map(A => \rxdb[0]\, B => \rshift[7]\, S => N_860, Y - => N_668); - - \r.rhold_0_RNI8P29[0]\ : MX2C - port map(A => \rhold_0[0]\, B => \rhold_2[0]\, S => - \rraddr[1]\, Y => N_473); - - \r.txen\ : DFN1 - port map(D => N_106, CLK => lclk_c, Q => \un1_uart1[34]\); - - \r.rxf[1]\ : DFN1 - port map(D => \rxf[0]\, CLK => lclk_c, Q => \rxf[1]\); - - \r.rwaddr_RNIDEB1_2[1]\ : NOR2 - port map(A => \rwaddr[1]\, B => \rwaddr[0]\, Y => - \un26_rxd[3]\); - - \r.tshift_RNO_1[5]\ : OR3B - port map(A => txtick, B => \tshift[6]\, C => N_133, Y => - N_186); - - \r.tcnt[0]\ : DFN1 - port map(D => \tcnt_RNO_0[0]\, CLK => lclk_c, Q => - \tcnt[0]\); - - \un1_r.rwaddr_I_8\ : XOR2 - port map(A => \rwaddr[0]\, B => dpar_RNI4PT94, Y => - \DWACT_ADD_CI_0_partial_sum_1[0]\); - - \r.rxstate_RNO_1[0]\ : NOR2 - port map(A => rxtick, B => \rxstate[0]\, Y => N_205); - - \r.rhold_2[4]\ : DFN1E0 - port map(D => \rhold_1_1[4]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[4]\); - - \r.break_RNO_1\ : AO1A - port map(A => frame_1_sqmuxa_1, B => break_0_sqmuxa, C => - pwdata_1_2, Y => break_1); - - \r.rraddr_RNIT6TG3[0]\ : OR2B - port map(A => \rdata_2[6]\, B => \rdata_0_sqmuxa\, Y => - rdata_2_m_4); - - \r.brate[11]\ : DFN1E1 - port map(D => pwdata_11, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[11]\); - - \r.frame_RNO_2\ : OA1B - port map(A => break6, B => frame_1_sqmuxa_0, C => - break_1_sqmuxa, Y => frame_0_sqmuxa); - - \r.tshift[8]\ : DFN1 - port map(D => \tshift_13[8]\, CLK => lclk_c, Q => - \tshift[8]\); - - \r.rxclk_RNO[1]\ : XA1B - port map(A => \rxclk[0]\, B => \rxclk[1]\, C => N_869, Y - => \rxclk_1[1]\); - - \r.rxstate_RNIM7FK[2]\ : OAI1 - port map(A => N_876, B => \rxstate[2]\, C => rxtick, Y => - N_860); - - un4_scaler_I_5 : XNOR2 - port map(A => \un1_uart1[2]\, B => \un1_uart1[3]\, Y => - I_5_4); - - \r.txen_RNO_0\ : MX2 - port map(A => \un1_uart1[34]\, B => pwdata_1_0, S => - breakirqen_1_sqmuxa, Y => N_646); - - \r.brate_RNISRF83[2]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[2]\, Y => - \brate_m[2]\); - - \r.scaler[7]\ : DFN1E0 - port map(D => \scaler_1[7]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[9]\); - - \r.scaler_RNO_0[7]\ : MX2C - port map(A => \brate[7]\, B => I_38_1, S => tick_2_i, Y => - N_509); - - \r.tsemptyirqen\ : DFN1E1 - port map(D => pwdata_14, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => \tsemptyirqen_0\); - - \r.rwaddr_RNO[1]\ : NOR2B - port map(A => I_10_0, B => rstn, Y => \rwaddr_RNO[1]\); - - rdata_0_sqmuxa_0_a2 : NOR2 - port map(A => N_235, B => paddr(4), Y => \rdata_0_sqmuxa\); - - \r.rxstate_i_RNO[4]\ : OR3C - port map(A => N_78, B => \rxstate_nss_i_0_0_0[0]\, C => - N_897, Y => \rxstate_nss_i[0]\); - - \r.rhold_2[6]\ : DFN1E0 - port map(D => \rhold_0_1[6]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[6]\); - - \r.txclk[0]\ : DFN1E1 - port map(D => N_69, CLK => lclk_c, E => N_25, Q => - N_976_i_2); - - \r.rsempty_RNO\ : OR2A - port map(A => rstn, B => N_638, Y => N_216); - - \un1_r.rwaddr_I_10\ : XOR2 - port map(A => \rwaddr[1]\, B => \DWACT_ADD_CI_0_TMP_2[0]\, - Y => I_10_0); - - \un1_r.rcnt_1_0_1_CO1_i_o3\ : OAI1 - port map(A => N_913_i, B => N_9_0, C => CO1_i_o3_0, Y => - CO1_2); - - \r.rxf[3]\ : DFN1 - port map(D => N_161, CLK => lclk_c, Q => \rxf[3]\); - - un4_scaler_I_8 : OR2 - port map(A => \un1_uart1[3]\, B => \un1_uart1[2]\, Y => - N_45); - - \r.tcnt_RNIACLM3[2]\ : OR2A - port map(A => thempty_1, B => \N_156\, Y => thempty_1_m); - - \r.rshift[0]\ : DFN1 - port map(D => \rshift_RNO_0[0]\, CLK => lclk_c, Q => - \rshift[0]\); - - \r.rhold_0[7]\ : DFN1E0 - port map(D => \rhold_0_1[7]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[7]\); - - \r.twaddr_RNO[1]\ : NOR2B - port map(A => I_10_1, B => rstn, Y => N_33); - - \r.thold_tile_I_1_RNIG8SI4\ : OR3C - port map(A => N_155, B => \thold[5]\, C => \rdata_4_sqmuxa\, - Y => rdata_17_m_4); - - \r.tshift[0]\ : DFN1 - port map(D => \tshift_1[0]\, CLK => lclk_c, Q => - \tshift[0]\); - - \r.debug_RNIVG2S\ : NOR2A - port map(A => debug, B => thempty_1, Y => N_155); - - \r.txstate_RNO_6[0]\ : OR2A - port map(A => \un1_uart1[34]\, B => debug, Y => - \txstate_ns_i_0_1_tz_0[0]\); - - \r.rraddr_RNIV9TI[0]\ : MX2C - port map(A => N_475, B => N_483, S => \rraddr[0]\, Y => - \rdata_2[2]\); - - \r.rhold_1[2]\ : DFN1E0 - port map(D => \rhold_0_1[2]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[2]\); - - \r.rxdb_RNI0F8G[1]\ : NOR3B - port map(A => \un1_uart1[36]\, B => \rxdb[1]\, C => - \rxdb[0]\, Y => rxdb_1); - - \r.rshift_RNINDDD1[7]\ : MX2 - port map(A => pwdata_0(7), B => \rshift[7]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_0_1[7]\); - - \r.tshift_RNO_2[5]\ : OR2A - port map(A => \thold[5]\, B => N_134, Y => N_188); - - \r.rhold_2[7]\ : DFN1E0 - port map(D => \rhold_0_1[7]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[7]\); - - \uartop.v.tcnt_11_0_0_1_CO0_i\ : MAJ3 - port map(A => \tcnt[0]\, B => twaddr_0_sqmuxa, C => N_22, Y - => N_9); - - \r.rraddr_RNIHMRG3[0]\ : OR2B - port map(A => \rdata_2[3]\, B => \rdata_0_sqmuxa\, Y => - \rdata_2_m[3]\); - - \r.rwaddr_RNIDEB1[1]\ : NOR2B - port map(A => \rwaddr[1]\, B => \rwaddr[0]\, Y => - \un26_rxd[0]\); - - \r.brate[0]\ : DFN1E1 - port map(D => pwdata_0_d0, CLK => lclk_c, E => - brate_1_sqmuxa, Q => \brate[0]\); - - \r.thold_tile_I_1_RNI04UK1\ : NOR2B - port map(A => \thold[3]\, B => N_155, Y => - \rdata_17_m_0[2]\); - - \r.rxstate_RNI4TU7[0]\ : OR2B - port map(A => rxtick, B => \rxstate[0]\, Y => - frame_1_sqmuxa_1); - - \r.rshift_RNI9HCD1[0]\ : MX2 - port map(A => pwdata_0(0), B => \rshift[0]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_3_1[0]\); - - \r.tcnt_RNO[2]\ : XA1 - port map(A => CO1_1, B => SUM2_0_0, C => rstn, Y => - \tcnt_RNO[2]\); - - \r.rcnt_RNIHM9E[1]\ : NOR2 - port map(A => \rcnt[2]\, B => \rcnt[1]\, Y => rhalffull_1); - - \r.rxclk[2]\ : DFN1E0 - port map(D => \rxclk_1[2]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[2]\); - - \r.tshift_RNO_2[3]\ : OR2A - port map(A => \thold[3]\, B => N_134, Y => N_182); - - \r.rxstate_RNO[1]\ : NOR3A - port map(A => rstn, B => N_206, C => N_207, Y => N_88); - - \r.rhold_1[3]\ : DFN1E0 - port map(D => \rhold_3_1[3]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[3]\); - - \r.rshift_RNO[2]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_663, Y => - \rshift_RNO_0[2]\); - - \uartop.v.tcnt_11_0_0_1_SUM1_0\ : XOR2 - port map(A => SUM1_0_0_0, B => N_9, Y => \tcnt_11[1]\); - - \r.rsempty_RNICVQJ\ : OR3 - port map(A => \rxstate_i[4]\, B => rsempty, C => \rcnt[2]\, - Y => rwaddr_0_sqmuxa); - - \r.rhold_2[0]\ : DFN1E0 - port map(D => \rhold_3_1[0]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[0]\); - - \r.irq_RNO_8\ : NOR3A - port map(A => rirqen_m_1, B => frame_1_sqmuxa_1, C => - break_0_sqmuxa, Y => rirqen_m_0); - - \un1_r.rraddr_I_10\ : XOR2 - port map(A => \rraddr[1]\, B => \DWACT_ADD_CI_0_TMP_1[0]\, - Y => I_10_2); - - \uartop.v.tcnt_11_0_0_1_CO1_i_o3\ : AO1B - port map(A => N_9, B => \tcnt[1]\, C => CO1_i_o3_0_0, Y => - CO1_1); - - \r.rxen\ : DFN1 - port map(D => N_104, CLK => lclk_c, Q => \un1_uart1[36]\); - - \r.traddr[0]\ : DFN1 - port map(D => N_35, CLK => lclk_c, Q => \traddr[0]\); - - \r.txtick\ : DFN1 - port map(D => N_98, CLK => lclk_c, Q => txtick); - - \r.rirqen_RNII5M63\ : NOR3C - port map(A => debug, B => rirqen, C => irq_5_2, Y => irq_5); - - \un1_r.irqcnt_I_27\ : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \irqcnt[2]\, Y => \DWACT_ADD_CI_0_g_array_12[0]\); - - \r.scaler[10]\ : DFN1E0 - port map(D => \scaler_1[10]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[12]\); - - \r.dpar_RNI4PT94\ : OR2 - port map(A => rwaddr_0_sqmuxa_0, B => irq_5_2, Y => - dpar_RNI4PT94); - - \r.rhold_3[7]\ : DFN1E0 - port map(D => \rhold_0_1[7]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[7]\); - - \r.scaler_RNO[5]\ : MX2A - port map(A => N_507, B => pwdata_0(5), S => - brate_1_sqmuxa_0, Y => \scaler_1[5]\); - - \r.thold_tile_I_1_RNICORI4\ : OR3C - port map(A => N_155, B => \thold[1]\, C => \rdata_4_sqmuxa\, - Y => rdata_17_m_0_d0); - - \r.rxstate_RNO_0[3]\ : NOR2A - port map(A => \rxstate[3]\, B => rxtick, Y => - \rxstate_RNO_0[3]\); - - \r.rxstate_i_RNO_0[4]\ : OAI1 - port map(A => \rxstate_nss_i_0_a3_0[0]\, B => - \rxstate_nss_i_0_0_0_tz_0[0]\, C => rstn, Y => - \rxstate_nss_i_0_0_0[0]\); - - \r.rraddr_RNID6RG3[0]\ : OR2B - port map(A => \rdata_2[2]\, B => \rdata_0_sqmuxa\, Y => - \rdata_2_m[2]\); - - \r.rhold_0[4]\ : DFN1E0 - port map(D => \rhold_0_1[4]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[4]\); - - \r.delayirqen\ : DFN1E1 - port map(D => pwdata_13, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => \delayirqen\); - - \r.tfifoirqen_RNIN2T63\ : NOR2B - port map(A => tfifoirqen, B => \prdata[31]\, Y => - tfifoirqen_m); - - \r.tshift_RNO[5]\ : OR3C - port map(A => N_187, B => N_186, C => N_188, Y => - \tshift_13[5]\); - - \r.thold_tile_WADDR_REG1[0]\ : DFN1 - port map(D => \twaddr[0]\, CLK => lclk_c, Q => - \WADDR_REG1[0]\); - - \r.rirqen_RNIF4B33\ : OR2B - port map(A => rirqen, B => \prdata[31]\, Y => rirqen_m); - - \un1_r.irqcnt_I_30\ : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \irqcnt[4]\, Y => \DWACT_ADD_CI_0_g_array_12_1[0]\); - - \r.ovf_RNO_1\ : NOR3B - port map(A => \rcnt_1\, B => rxdb_1, C => \rxstate_i[4]\, Y - => ovf_0_sqmuxa); - - \r.rshift[3]\ : DFN1 - port map(D => \rshift_RNO_0[3]\, CLK => lclk_c, Q => - \rshift[3]\); - - \r.tshift[3]\ : DFN1 - port map(D => \tshift_13[3]\, CLK => lclk_c, Q => - \tshift[3]\); - - \r.txclk_RNO[0]\ : NOR3C - port map(A => N_199, B => tick, C => rstn, Y => N_69); - - \r.rhold_1_RNIQ959[6]\ : MX2C - port map(A => \rhold_1[6]\, B => \rhold_3[6]\, S => - \rraddr[1]\, Y => N_487); - - \r.twaddr[1]\ : DFN1 - port map(D => N_33, CLK => lclk_c, Q => \twaddr[1]\); - - \r.tshift_RNO_1[1]\ : OR3B - port map(A => txtick, B => \tshift[2]\, C => N_133, Y => - N_174); - - \r.thold_tile_WADDR_REG1_RNI16OE[0]\ : XAI1A - port map(A => \WADDR_REG1[0]\, B => \traddr[0]\, C => I_5_0, - Y => N_7); - - \r.parerr\ : DFN1 - port map(D => N_108, CLK => lclk_c, Q => parerr); - - un4_scaler_I_31 : XNOR2 - port map(A => N_29_0, B => \un1_uart1[8]\, Y => I_31_3); - - \r.tfifoirqen\ : DFN1E1 - port map(D => pwdata_9, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => tfifoirqen); - - \r.irqcnt_RNO[4]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_24_5, Y - => \irqcnt_1[4]\); - - \r.tshift_RNO_0[0]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[0]\, Y => N_219); - - \r.rxen_RNO\ : NOR2B - port map(A => N_647, B => rstn, Y => N_104); - - \r.tshift_RNO_0[6]\ : AOI1B - port map(A => txtick_1_sqmuxa, B => \tshift[6]\, C => N_189, - Y => \tshift_13_0_iv_0_0[6]\); - - \r.rwaddr_RNIULKC4_0[1]\ : AOI1 - port map(A => irq_5_2, B => \un26_rxd[0]\, C => - rhold_3_1_sqmuxa_1, Y => rhold_3_0_sqmuxa); - - \r.txclk_RNO[2]\ : XA1B - port map(A => \txclk[2]\, B => CO1_0, C => N_29_1, Y => - N_29); - - \r.rirqen_RNI67IFE\ : NOR3C - port map(A => \rdata_iv_0[2]\, B => \rdata_2_m[2]\, C => - rirqen_m, Y => rdata_iv_2(2)); - - \r.extclken_RNO_0\ : MX2 - port map(A => extclken, B => pwdata_0(8), S => - breakirqen_1_sqmuxa, Y => N_649); - - \r.txstate_RNO_5[0]\ : NOR2 - port map(A => \tcnt_i\, B => \tcnt[0]\, Y => - \txstate_ns_i_0_a2_2_0[0]\); - - \r.rraddr_RNIBQUI[0]\ : MX2C - port map(A => N_478, B => N_486, S => \rraddr[0]\, Y => - \rdata_2[5]\); - - \uartop.v.traddr_1_i[1]\ : NOR2B - port map(A => I_10, B => rstn, Y => N_37_0); - - \r.rxstate_i_RNO_3[4]\ : AO1A - port map(A => rxtick, B => \rxstate[0]\, C => \rxstate[1]\, - Y => \rxstate_nss_i_0_0_0_tz_0[0]\); - - un4_scaler_I_56 : XNOR2 - port map(A => N_11, B => \un1_uart1[12]\, Y => I_56_1); - - \r.rhold_3_RNO[6]\ : MX2 - port map(A => pwdata_0(6), B => \rshift[6]\, S => - rhold_3_1_sqmuxa_1, Y => \rhold_3_1[6]\); - - \uartop.v.tcnt_11_0_0_1_SUM1_0_0\ : XOR2 - port map(A => \tcnt[1]\, B => N_22, Y => SUM1_0_0_0); - - \r.rhold_1[0]\ : DFN1E0 - port map(D => \rhold_3_1[0]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[0]\); - - un4_scaler_I_51 : OR2 - port map(A => \un1_uart1[10]\, B => \DWACT_FDEC_E[4]\, Y - => N_14); - - \r.scaler_RNO_0[1]\ : MX2C - port map(A => \brate[1]\, B => I_5_4, S => tick_2_i, Y => - N_503); - - \un1_r.rcnt_1_0_1_CO0_i\ : AO1A - port map(A => rraddr_0_sqmuxa, B => N_940_1, C => N_16, Y - => N_9_0); - - un4_scaler_I_34 : OR3 - port map(A => \un1_uart1[5]\, B => \un1_uart1[6]\, C => - \un1_uart1[7]\, Y => \DWACT_FDEC_E[2]\); - - \r.rshift_RNO[7]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_668, Y => - \rshift_RNO_0[7]\); - - \r.dpar_RNIT6LB\ : OR3A - port map(A => rxtick, B => dpar, C => \rcnt[2]\, Y => - rwaddr_0_sqmuxa_1_1); - - \r.thold_tile_I_1_RNI67SO\ : MX2 - port map(A => \DIN_REG1[7]\, B => \DOUT_TMP[7]\, S => N_7, - Y => \thold[8]\); - - \r.tcnt[1]\ : DFN1 - port map(D => \tcnt_RNO_0[1]\, CLK => lclk_c, Q => - \tcnt[1]\); - - \r.tcnt[2]\ : DFN1 - port map(D => \tcnt_RNO[2]\, CLK => lclk_c, Q => \tcnt[2]\); - - \r.rshift_RNIF794[1]\ : NOR3A - port map(A => break6_1, B => \rshift[2]\, C => \rshift[1]\, - Y => break6_4); - - \r.rwaddr_RNO[0]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_1[0]\, B => rstn, - Y => \rwaddr_RNO[0]\); - - \r.rxstate_RNO_0[1]\ : OA1A - port map(A => \paren\, B => N_140, C => rxtick, Y => N_206); - - \r.break_RNO\ : NOR2B - port map(A => N_640, B => rstn, Y => N_114); - - \r.txclk[1]\ : DFN1E1 - port map(D => N_27, CLK => lclk_c, E => N_25, Q => - \txclk[1]\); - - \r.rshift_RNIDPCD1[2]\ : MX2 - port map(A => pwdata_0(2), B => \rshift[2]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_0_1[2]\); - - \r.rxstate_RNO_0[2]\ : NOR2B - port map(A => rxtick, B => N_876, Y => - \rxstate_srsts_0_a3_0_0[2]\); - - \r.rhold_0[3]\ : DFN1E0 - port map(D => \rhold_0_1[3]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[3]\); - - \v.tshift_13_0_iv_0_RNO[7]\ : AND2 - port map(A => N_193, B => N_192, Y => - \tshift_13_0_iv_0_0[7]\); - - \r.twaddr_RNO[0]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_3[0]\, B => rstn, - Y => N_31); - - \r.scaler[11]\ : DFN1E0 - port map(D => \scaler_1[11]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[13]\); - - \r.irqcnt[1]\ : DFN1 - port map(D => \irqcnt_1[1]\, CLK => lclk_c, Q => - \irqcnt[1]\); - - \r.rraddr_RNIN9SI[0]\ : MX2C - port map(A => N_473, B => N_481, S => \rraddr[0]\, Y => - rdata_2_0); - - \r.tshift_RNIPTO2[2]\ : NOR2B - port map(A => \tshift[2]\, B => \tshift[3]\, Y => - \txstate_ns_i_0_a2_4_0[0]\); - - \r.tsempty_RNI49383\ : OR2A - port map(A => tsempty, B => \N_156\, Y => N_227); - - \uartop.rdata60_4_0\ : OR2 - port map(A => rdata61_2, B => rdata60_1, Y => rdata60_4_0); - - \r.rhold_0[1]\ : DFN1E0 - port map(D => \rhold_0_1[1]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[1]\); - - \r.extclken_RNIMU723\ : NAND2 - port map(A => \prdata[31]\, B => extclken, Y => extclken_m); - - un2_rxclk_1_CO1 : AND2 - port map(A => \rxclk[0]\, B => \rxclk[1]\, Y => CO1); - - \r.tshift_RNO[6]\ : AO1C - port map(A => N_134, B => \thold[6]\, C => - \tshift_13_0_iv_0_0[6]\, Y => \tshift_13[6]\); - - \r.debug_RNIJUO41\ : OR2A - port map(A => N_155, B => \rdata62_0\, Y => - traddr_1_sqmuxa_0); - - \r.rxdb_RNO[0]\ : NOR3C - port map(A => N_172, B => N_171, C => N_170, Y => N_17_i_0); - - \r.parerr_RNO\ : NOR2B - port map(A => N_644, B => rstn, Y => N_108); - - \r.rhold_3_RNO[4]\ : MX2 - port map(A => pwdata_1_3, B => \rshift[4]\, S => - rhold_3_1_sqmuxa_1, Y => \rhold_3_1[4]\); - - \r.rshift_RNO[4]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_665, Y => - \rshift_RNO_0[4]\); - - un4_scaler_I_59 : OR3 - port map(A => \un1_uart1[8]\, B => \un1_uart1[9]\, C => - \un1_uart1[10]\, Y => \DWACT_FDEC_E[5]\); - - \r.ovf_RNO\ : OA1 - port map(A => N_645, B => ovf_0_sqmuxa, C => rstn, Y => - ovf_RNO_0); - - \uartop.un1_apbi_2_0\ : NOR2A - port map(A => penable, B => N_750, Y => un1_apbi_2_0); - - \r.rraddr_RNI3QTI[0]\ : MX2C - port map(A => N_476, B => N_484, S => \rraddr[0]\, Y => - \rdata_2[3]\); - - \r.txstate[0]\ : DFN1 - port map(D => N_801s, CLK => lclk_c, Q => \txstate[0]\); - - \r.tshift_RNO_0[3]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[3]\, Y => N_181); - - \r.brate_RNI6GS63[11]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[11]\, Y => - brate_m_9); - - \r.rcnt_RNIOHEL[1]\ : NOR3 - port map(A => \rcnt[1]\, B => \rcnt[0]\, C => \rcnt[2]\, Y - => rcnt); - - \r.ovf\ : DFN1 - port map(D => ovf_RNO_0, CLK => lclk_c, Q => ovf); - - \r.rshift[6]\ : DFN1 - port map(D => \rshift_RNO_0[6]\, CLK => lclk_c, Q => - \rshift[6]\); - - \r.rirqen_RNIRGQ9\ : NOR2A - port map(A => rirqen, B => \delayirqen\, Y => rirqen_m_1); - - \r.thold_tile_DIN_REG1[6]\ : DFN1 - port map(D => pwdata_6, CLK => lclk_c, Q => \DIN_REG1[6]\); - - \r.rhold_1_RNIO159[5]\ : MX2C - port map(A => \rhold_1[5]\, B => \rhold_3[5]\, S => - \rraddr[1]\, Y => N_486); - - \r.tshift[6]\ : DFN1 - port map(D => \tshift_13[6]\, CLK => lclk_c, Q => - \tshift[6]\); - - \r.frame\ : DFN1 - port map(D => N_112, CLK => lclk_c, Q => \frame\); - - \un1_r.rwaddr_I_1\ : AND2 - port map(A => \rwaddr[0]\, B => dpar_RNI4PT94, Y => - \DWACT_ADD_CI_0_TMP_2[0]\); - - \r.thold_tile_WADDR_REG1[1]\ : DFN1 - port map(D => \twaddr[1]\, CLK => lclk_c, Q => - \WADDR_REG1[1]\); - - \r.scaler_RNO_0[5]\ : MX2C - port map(A => \brate[5]\, B => I_24_4, S => tick_2_i, Y => - N_507); - - \r.irq_RNO_4\ : XA1C - port map(A => CO1_1, B => SUM2_0_0, C => un6_thempty_1, Y - => un6_thempty); - - \r.rwaddr_RNIH79B4[1]\ : OAI1 - port map(A => irq_5_2, B => rwaddr_0_sqmuxa_0, C => - rhold_1_0_sqmuxa_0, Y => rhold_1_0_sqmuxa); - - un4_scaler_I_20 : XNOR2 - port map(A => N_37, B => \un1_uart1[6]\, Y => I_20_4); - - \r.tshift_RNO[8]\ : OR3C - port map(A => N_196, B => N_195, C => N_197, Y => - \tshift_13[8]\); - - \r.rshift[1]\ : DFN1 - port map(D => \rshift_RNO_0[1]\, CLK => lclk_c, Q => - \rshift[1]\); - - \r.rxstate_RNIG2GC[3]\ : NOR2A - port map(A => \rxstate[3]\, B => \rxdb[0]\, Y => N_876); - - \r.tshift_RNO_1[0]\ : AOI1B - port map(A => \tshift_1_0_a2_0[0]\, B => N_260, C => N_218, - Y => \tshift_1_0_0[0]\); - - \r.tshift[1]\ : DFN1 - port map(D => \tshift_13[1]\, CLK => lclk_c, Q => - \tshift[1]\); - - \r.rshift[2]\ : DFN1 - port map(D => \rshift_RNO_0[2]\, CLK => lclk_c, Q => - \rshift[2]\); - - \r.tshift[2]\ : DFN1 - port map(D => \tshift_13[2]\, CLK => lclk_c, Q => - \tshift[2]\); - - \r.rshift_RNO_0[0]\ : MX2 - port map(A => \rshift[1]\, B => \rshift[0]\, S => N_860, Y - => N_661); - - \r.txtick_RNO_0\ : NOR3C - port map(A => tick, B => \txclk[2]\, C => CO1_0, Y => - txtick_0_i_1); - - \r.rshift_RNO_0[6]\ : MX2 - port map(A => \rshift[7]\, B => \rshift[6]\, S => N_860, Y - => N_667); - - \r.txstate_RNO_7[0]\ : NOR3B - port map(A => \paren\, B => \txstate[0]\, C => \tshift[1]\, - Y => \txstate_ns_i_0_a2_3_1[0]\); - - \un1_r.twaddr_I_8\ : XOR2 - port map(A => \twaddr[0]\, B => twaddr_0_sqmuxa, Y => - \DWACT_ADD_CI_0_partial_sum_3[0]\); - - \r.rraddr[1]\ : DFN1 - port map(D => \rraddr_RNO[1]\, CLK => lclk_c, Q => - \rraddr[1]\); - - \r.rshift_RNIJ5DD1[5]\ : MX2 - port map(A => pwdata_0(5), B => \rshift[5]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_3_1[5]\); - - \r.rxstate_i_RNO_1[4]\ : OR2B - port map(A => rxdb_1, B => N_897_1, Y => N_897); - - \r.rxf[2]\ : DFN1E1 - port map(D => \rxf[1]\, CLK => lclk_c, E => tick, Q => - \rxf[2]\); - - \r.brate_RNITVF83[3]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[3]\, Y => - \brate_m[3]\); - - \r.rfifoirqen_RNI4MA7\ : OR2B - port map(A => rfifoirqen, B => \un1_uart1[36]\, Y => - un4_rhalffull_0); - - \r.rhold_0_RNIK949[6]\ : MX2C - port map(A => \rhold_0[6]\, B => \rhold_2[6]\, S => - \rraddr[1]\, Y => N_479); - - \r.irqpend_RNO_2\ : NOR3A - port map(A => irqpend_0_sqmuxa, B => un4_rhalffull, C => - irq10, Y => irqpend_1_sqmuxa); - - \r.scaler_RNO[9]\ : MX2A - port map(A => N_511, B => pwdata_0(9), S => - brate_1_sqmuxa_0, Y => \scaler_1[9]\); - - \r.rxstate_RNO[2]\ : AO1B - port map(A => \rxstate_srsts_0_a3_0_0[2]\, B => rstn, C => - N_893, Y => \rxstate_nss[2]\); - - \un1_r.rraddr_I_1\ : AND2 - port map(A => \rraddr[0]\, B => rraddr_0_sqmuxa, Y => - \DWACT_ADD_CI_0_TMP_1[0]\); - - \r.irqcnt[2]\ : DFN1 - port map(D => \irqcnt_1[2]\, CLK => lclk_c, Q => - \irqcnt[2]\); - - \r.brate_RNIV7G83[5]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[5]\, Y => - brate_m_3); - - \r.rcnt_RNO[2]\ : XA1 - port map(A => CO1_2, B => SUM2_0_1, C => rstn, Y => - \rcnt_RNO[2]\); - - rdata_2_sqmuxa : NOR2A - port map(A => rdata60, B => un1_apbi_5, Y => \prdata[31]\); - - \r.tshift_RNO_2[2]\ : OR2A - port map(A => \thold[2]\, B => N_134, Y => N_179); - - \r.rxf[0]\ : DFN1 - port map(D => rxd1_c, CLK => lclk_c, Q => \rxf[0]\); - - \r.rraddr_RNIJQVI[0]\ : MX2C - port map(A => N_480, B => N_488, S => \rraddr[0]\, Y => - \rdata_2[7]\); - - \v.tshift_13_0_iv_0_RNO_1[7]\ : OR3B - port map(A => txtick, B => \tshift[8]\, C => N_133, Y => - N_192); - - \r.rxstate_RNIKLUE[0]\ : NOR3C - port map(A => \rxdb[0]\, B => rxtick, C => \rxstate[0]\, Y - => parerr_0_sqmuxa); - - \r.dpar_RNO_4\ : XOR2 - port map(A => \rxdb[0]\, B => dpar, Y => dpar_4); - - \r.txstate_RNO_1[0]\ : NOR3 - port map(A => N_210, B => \txstate_ns_i_0_1[0]\, C => - \txstate_ns_i_0_0[0]\, Y => N_929); - - \r.tick_RNIJKMM2\ : OR2 - port map(A => tick, B => N_29_1, Y => N_25); - - \r.txen_RNI386B\ : NOR3B - port map(A => \un1_uart1[34]\, B => txtick, C => debug, Y - => txtick_1); - - \r.rsempty_RNI7T7E\ : NOR2A - port map(A => \rcnt[2]\, B => rsempty, Y => \rcnt_1\); - - \r.rhold_1_RNII949[2]\ : MX2C - port map(A => \rhold_1[2]\, B => \rhold_3[2]\, S => - \rraddr[1]\, Y => N_483); - - \r.thold_tile_I_1_RNI5OUK1\ : NOR2B - port map(A => \thold[8]\, B => N_155, Y => - rdata_iv_0_a2_3_0(7)); - - \r.tshift_RNO[2]\ : OR3C - port map(A => N_178, B => N_177, C => N_179, Y => - \tshift_13[2]\); - - \r.rhold_0[5]\ : DFN1E0 - port map(D => \rhold_3_1[5]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[5]\); - - \r.rshift[4]\ : DFN1 - port map(D => \rshift_RNO_0[4]\, CLK => lclk_c, Q => - \rshift[4]\); - - \r.rraddr_RNIL6SG3[0]\ : OR2B - port map(A => \rdata_2[4]\, B => \rdata_0_sqmuxa\, Y => - rdata_2_m_2); - - \r.tshift[4]\ : DFN1 - port map(D => \tshift_13[4]\, CLK => lclk_c, Q => - \tshift[4]\); - - \v.breakirqen_1_sqmuxa\ : NOR3C - port map(A => pwrite, B => un1_apbi_2, C => rdata60, Y => - breakirqen_1_sqmuxa); - - \r.tirqen_RNIU7MFE\ : AOI1B - port map(A => tirqen, B => \prdata[31]\, C => - \rdata_iv_1[3]\, Y => rdata_iv_2(3)); - - \r.rxstate_RNO_2[0]\ : NOR2 - port map(A => \paren\, B => N_140, Y => N_142); - - \r.paren\ : DFN1E1 - port map(D => pwdata_5, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => \paren\); - - \r.irq_RNO\ : OR3C - port map(A => tsemptyirqen, B => irq_1_0, C => irq_16_i, Y - => irq_1); - - \r.tshift[9]\ : DFN1 - port map(D => \tshift_13_0_iv[9]\, CLK => lclk_c, Q => - \tshift[9]\); - - \r.thold_tile_DIN_REG1[0]\ : DFN1 - port map(D => pwdata_0_d0, CLK => lclk_c, Q => - \DIN_REG1[0]\); - - \r.scaler_RNO[11]\ : MX2A - port map(A => N_513, B => pwdata_0(11), S => - brate_1_sqmuxa_0, Y => \scaler_1[11]\); - - \r.irq\ : DFN1 - port map(D => irq_1, CLK => lclk_c, Q => pirq(2)); - - \r.irq_RNO_3\ : NOR2B - port map(A => tfifoirqen, B => \un1_uart1[34]\, Y => - un4_thalffull_0); - - \v.brate_1_sqmuxa\ : NOR3C - port map(A => pwrite, B => un1_apbi_2, C => rdata61, Y => - brate_1_sqmuxa); - - \r.irq_RNO_13\ : OA1 - port map(A => delayirqen_0, B => irq_5, C => irq_6_m_0, Y - => irq_6_m); - - \r.tshift_RNO_2[0]\ : OA1A - port map(A => \paren\, B => tpar, C => N_247, Y => - \tshift_1_0_a2_0[0]\); - - \r.tshift_RNO_1[4]\ : OR3B - port map(A => txtick, B => \tshift[5]\, C => N_133, Y => - N_183); - - \r.rraddr_RNI1NTG3[0]\ : OR2B - port map(A => \rdata_2[7]\, B => \rdata_0_sqmuxa\, Y => - N_223); - - \r.rxstate_RNO_0[0]\ : NOR3A - port map(A => rxtick, B => \rxstate[1]\, C => N_142, Y => - N_204); - - \r.txstate_RNO_2[0]\ : NOR3C - port map(A => N_133, B => flow, C => N_210_1, Y => N_210); - - \r.rcnt_RNI8FBM3[1]\ : OR2 - port map(A => rcnt, B => \N_156\, Y => rcnt_RNI8FBM3(1)); - - \r.thold_tile_I_1_RNI2NRO\ : MX2 - port map(A => \DIN_REG1[3]\, B => \DOUT_TMP[3]\, S => N_7, - Y => \thold[4]\); - - \r.scaler[1]\ : DFN1E0 - port map(D => \scaler_1[1]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[3]\); - - \r.rshift_RNISJ42[5]\ : NOR2 - port map(A => \rshift[5]\, B => \rshift[7]\, Y => break6_1); - - \r.irq_RNO_7\ : OA1B - port map(A => rxtick_0, B => frame_1_sqmuxa_1, C => irq_7, - Y => irq_7_m); - - \r.rxstate_i_RNI5HRL[4]\ : OR2A - port map(A => rxdb_1, B => \rxstate_i[4]\, Y => - rshift_0_sqmuxa_1); - - \r.dpar_RNO_2\ : OR3 - port map(A => \rxstate[1]\, B => \rshift[0]\, C => \paren\, - Y => N_898); - - \r.rshift_RNO_0[3]\ : MX2 - port map(A => \rshift[4]\, B => \rshift[3]\, S => N_860, Y - => N_664); - - \r.rxen_RNI4SI4\ : NOR2 - port map(A => \un1_uart1[36]\, B => \un1_uart1[34]\, Y => - txen); - - \r.tirqen\ : DFN1E1 - port map(D => pwdata_1_2, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => tirqen); - - \r.rxtick_RNO_1\ : AND2 - port map(A => tick, B => \rxclk[2]\, Y => rxtick_0_0); - - \r.rxclk[0]\ : DFN1E0 - port map(D => \rxclk_1[0]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[0]\); - - \r.txstate_RNO_4[0]\ : AO1 - port map(A => \txstate_ns_i_0_a2_3_1[0]\, B => N_260, C => - N_209, Y => \txstate_ns_i_0_0[0]\); - - \r.rraddr_RNIPMSG3[0]\ : OR2B - port map(A => \rdata_2[5]\, B => \rdata_0_sqmuxa\, Y => - rdata_2_m_3); - - \r.rxdb_RNO_1[0]\ : OR2A - port map(A => loopb, B => \tshift[0]\, Y => N_171); - - \r.brate_RNIRNF83[1]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[1]\, Y => - N_225); - - \r.irq_RNO_6\ : OR3 - port map(A => \tcnt_11[0]\, B => thempty_1, C => - \tcnt_11[1]\, Y => un6_thempty_1); - - \un1_r.irqcnt_I_1\ : AND2 - port map(A => \irqcnt[0]\, B => rxtick_0, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - \r.rhold_1_RNISH59[7]\ : MX2C - port map(A => \rhold_1[7]\, B => \rhold_3[7]\, S => - \rraddr[1]\, Y => N_488); - - \r.txstate_RNO[1]\ : NOR2B - port map(A => N_802, B => rstn, Y => N_802s); - - \r.tshift_RNO_1[8]\ : OR3B - port map(A => txtick, B => \tshift[9]\, C => N_133, Y => - N_195); - - \r.extclken_RNO\ : NOR2B - port map(A => N_649, B => rstn, Y => N_100); - - \r.rsempty\ : DFN1 - port map(D => N_216, CLK => lclk_c, Q => rsempty); - - \un1_r.irqcnt_I_15\ : XOR2 - port map(A => \irqcnt[0]\, B => rxtick_0, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \r.tshift_RNO_0[2]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[2]\, Y => N_178); - - \uartop.v.thold_32\ : OR2 - port map(A => N_232, B => paddr(4), Y => thold_32); - - \r.irqpend\ : DFN1 - port map(D => N_110, CLK => lclk_c, Q => irqpend); - - \r.rwaddr_RNIULKC4[1]\ : AOI1 - port map(A => irq_5_2, B => \un26_rxd[3]\, C => - rhold_0_1_sqmuxa_1, Y => rhold_0_0_sqmuxa); - - un4_scaler_I_13 : XNOR2 - port map(A => N_42, B => \un1_uart1[5]\, Y => I_13_8); - - \r.brate[1]\ : DFN1E1 - port map(D => pwdata_1_0, CLK => lclk_c, E => - brate_1_sqmuxa, Q => \brate[1]\); - - \un1_r.rraddr_I_8\ : XOR2 - port map(A => \rraddr[0]\, B => rraddr_0_sqmuxa, Y => - \DWACT_ADD_CI_0_partial_sum_0[0]\); - - \r.rhold_1_RNIKH49[3]\ : MX2C - port map(A => \rhold_1[3]\, B => \rhold_3[3]\, S => - \rraddr[1]\, Y => N_484); - - \un1_r.rcnt_1_0_1_SUM0_0_1\ : XOR3 - port map(A => \rcnt[0]\, B => rwaddr_0_sqmuxa_0, C => - irq_5_2, Y => N_940_1); - - \r.irq_RNO_15\ : NOR2B - port map(A => \delayirqen\, B => irq10, Y => irq_6_m_0); - - \r.irqcnt[3]\ : DFN1 - port map(D => \irqcnt_1[3]\, CLK => lclk_c, Q => - \irqcnt[3]\); - - \r.rshift_RNO[1]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_662, Y => - \rshift_RNO_0[1]\); - - \r.thold_tile_DIN_REG1[4]\ : DFN1 - port map(D => pwdata_1_3, CLK => lclk_c, Q => \DIN_REG1[4]\); - - \r.rhold_2[5]\ : DFN1E0 - port map(D => \rhold_3_1[5]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[5]\); - - \r.flow_RNO\ : NOR2B - port map(A => N_648, B => rstn, Y => N_102); - - \r.tshift_RNO_1[2]\ : OR3B - port map(A => txtick, B => \tshift[3]\, C => N_133, Y => - N_177); - - un4_scaler_I_16 : OR3 - port map(A => \un1_uart1[2]\, B => \un1_uart1[3]\, C => - \un1_uart1[4]\, Y => \DWACT_FDEC_E[0]\); - - un4_scaler_I_66 : XNOR2 - port map(A => N_4, B => \un1_uart1[13]\, Y => I_66_1); - - \r.tick_RNIG2HP\ : NOR2 - port map(A => tick, B => N_869, Y => rxclk_1_sqmuxa_1); - - \r.rshift_RNO[0]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_661, Y => - \rshift_RNO_0[0]\); - - \r.rhold_0_RNIA139[1]\ : MX2C - port map(A => \rhold_0[1]\, B => \rhold_2[1]\, S => - \rraddr[1]\, Y => N_163); - - \r.txstate[1]\ : DFN1 - port map(D => N_802s, CLK => lclk_c, Q => \txstate[1]\); - - \r.rxdb_RNIC7IF[0]\ : NOR2A - port map(A => break6, B => \rxdb[0]\, Y => break_0_sqmuxa); - - \r.rsempty_RNO_5\ : NOR2B - port map(A => \rxstate[0]\, B => dpar, Y => dpar_m_1); - - \r.irqcnt_RNO[5]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_26, Y => - \irqcnt_1[5]\); - - \r.rshift_RNID794[3]\ : NOR3A - port map(A => break6_3, B => \rshift[3]\, C => \rshift[0]\, - Y => break6_5); - - \r.frame_RNO\ : NOR2B - port map(A => N_641, B => rstn, Y => N_112); - - \r.scaler_RNO[7]\ : MX2A - port map(A => N_509, B => pwdata_0(7), S => - brate_1_sqmuxa_0, Y => \scaler_1[7]\); - - \r.rraddr_RNI7AUI[0]\ : MX2C - port map(A => N_477, B => N_485, S => \rraddr[0]\, Y => - \rdata_2[4]\); - - \r.traddr[1]\ : DFN1 - port map(D => N_37_0, CLK => lclk_c, Q => \traddr[1]\); - - \r.scaler_RNO[2]\ : MX2A - port map(A => N_504, B => pwdata_0(2), S => - brate_1_sqmuxa_0, Y => \scaler_1[2]\); - - \r.irq_RNO_2\ : AOI1B - port map(A => un6_thempty, B => tirqen, C => irq_14, Y => - irq_16_i); - - \r.thold_tile_WADDR_REG1_RNI0OG9[1]\ : XA1A - port map(A => \WADDR_REG1[1]\, B => \traddr[1]\, C => N_5, - Y => I_5_0); - - \r.irq_RNO_14\ : OR2 - port map(A => \breakirqen\, B => rirqen_m_1, Y => irq_10_0); - - \r.txstate_RNI2VCK2[1]\ : OR2B - port map(A => N_134, B => rstn, Y => N_29_1); - - \r.dpar_RNO\ : AO1B - port map(A => dpar_4_m_0, B => N_898, C => parsel_m, Y => - dpar_1); - - \r.scaler_RNO_0[2]\ : MX2C - port map(A => \brate[2]\, B => I_9_4, S => tick_2_i, Y => - N_504); - - \r.rwaddr[0]\ : DFN1 - port map(D => \rwaddr_RNO[0]\, CLK => lclk_c, Q => - \rwaddr[0]\); - - \r.scaler[4]\ : DFN1E0 - port map(D => \scaler_1[4]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[6]\); - - \r.flow_RNO_0\ : MX2 - port map(A => flow, B => pwdata_0(6), S => - breakirqen_1_sqmuxa, Y => N_648); - - un4_scaler_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \un1_uart1[10]\, C - => \un1_uart1[11]\, Y => N_11); - - \r.rhold_3[3]\ : DFN1E0 - port map(D => \rhold_3_1[3]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[3]\); - - \r.tshift_RNO[4]\ : OR3C - port map(A => N_184, B => N_183, C => N_185, Y => - \tshift_13[4]\); - - \r.tick\ : DFN1 - port map(D => tick_1, CLK => lclk_c, Q => tick); - - \r.break_RNI9B673\ : OR2A - port map(A => break, B => \N_156\, Y => break_m); - - \r.irq_RNO_0\ : OR3A - port map(A => \tsemptyirqen_0\, B => tsempty, C => - tsempty_4, Y => tsemptyirqen); - - \un1_r.irqcnt_I_24\ : XOR2 - port map(A => \irqcnt[4]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_24_5); - - \r.txen_RNO\ : NOR2B - port map(A => N_646, B => rstn, Y => N_106); - - \r.rhold_1[7]\ : DFN1E0 - port map(D => \rhold_0_1[7]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[7]\); - - \r.break_RNO_0\ : MX2 - port map(A => break_1, B => break, S => break_0_sqmuxa_1, Y - => N_640); - - \r.irqcnt_RNO[2]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_22, Y => - \irqcnt_1[2]\); - - \r.tshift_RNO_0[5]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[5]\, Y => N_187); - - \r.brate[3]\ : DFN1E1 - port map(D => pwdata_1_2, CLK => lclk_c, E => - brate_1_sqmuxa, Q => \brate[3]\); - - un4_scaler_I_9 : XNOR2 - port map(A => N_45, B => \un1_uart1[4]\, Y => I_9_4); - - \r.thold_tile_I_3\ : DFN1 - port map(D => \un1_apbi_1\, CLK => lclk_c, Q => N_5); - - \r.rhold_3[6]\ : DFN1E0 - port map(D => \rhold_3_1[6]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[6]\); - - \r.debug_RNILV673\ : OR2B - port map(A => debug, B => \prdata[31]\, Y => debug_m); - - \r.thold_tile_I_1_RNIVARO\ : MX2 - port map(A => \DIN_REG1[0]\, B => \DOUT_TMP[0]\, S => N_7, - Y => \thold[1]\); - - \r.rcnt_RNIPO183[2]\ : OR2A - port map(A => \rcnt[2]\, B => \N_156\, Y => prdata_6); - - un4_scaler_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - \r.tsempty\ : DFN1 - port map(D => tsempty_RNO_0, CLK => lclk_c, Q => tsempty); - - \r.tpar\ : DFN1E1 - port map(D => tpar_1, CLK => lclk_c, E => txtick_0_sqmuxa_1, - Q => tpar); - - \r.rraddr_RNI0QMAB[0]\ : AOI1B - port map(A => \rdata_0_sqmuxa\, B => N_165, C => - \rdata_iv_0_0[1]\, Y => \rdata_iv_0_1[1]\); - - \r.rsempty_RNO_3\ : OA1B - port map(A => \rxstate_i[4]\, B => \rcnt_1\, C => dpar_m_1, - Y => N_442); - - \r.rxdb[0]\ : DFN1 - port map(D => N_17_i_0, CLK => lclk_c, Q => \rxdb[0]\); - - un4_scaler_I_19 : OR2 - port map(A => \un1_uart1[5]\, B => \DWACT_FDEC_E[0]\, Y => - N_37); - - \r.irq_RNO_5\ : NOR3 - port map(A => irq_7_m, B => rirqen_m_0, C => irq_10_m, Y - => irq_14); - - \r.parsel\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => parsel); - - \v.break_1_sqmuxa\ : NOR3B - port map(A => pwrite, B => un1_apbi_2, C => rdata59, Y => - break_1_sqmuxa); - - \r.irqcnt[5]\ : DFN1 - port map(D => \irqcnt_1[5]\, CLK => lclk_c, Q => - \irqcnt[5]\); - - \r.delayirqen_RNI39R9\ : NOR2B - port map(A => rxtick, B => \delayirqen\, Y => rxtick_0); - - \un1_r.irqcnt_I_34\ : AND2 - port map(A => \irqcnt[2]\, B => \irqcnt[3]\, Y => - \DWACT_ADD_CI_0_pog_array_1[0]\); - - \r.thold_tile_I_1_RNO\ : INV - port map(A => \un1_apbi_1\, Y => un1_apbi_1_i); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.rxclk_RNO[2]\ : AOI1B - port map(A => N_973_i, B => rshift_0_sqmuxa_1, C => rstn, Y - => \rxclk_1[2]\); - - \r.rhold_2[1]\ : DFN1E0 - port map(D => \rhold_0_1[1]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[1]\); - - \r.rcnt[0]\ : DFN1 - port map(D => \rcnt_RNO[0]\, CLK => lclk_c, Q => \rcnt[0]\); - - \r.rcnt_RNI5J9Q1[1]\ : NOR3C - port map(A => \rcnt[0]\, B => rwaddr_0_sqmuxa_0, C => - \rcnt[1]\, Y => N_914); - - \r.rshift_RNO_0[2]\ : MX2 - port map(A => \rshift[3]\, B => \rshift[2]\, S => N_860, Y - => N_663); - - \r.rwaddr_RNIH79B4_0[1]\ : OAI1 - port map(A => irq_5_2, B => rwaddr_0_sqmuxa_0, C => - rhold_2_0_sqmuxa_0, Y => rhold_2_0_sqmuxa); - - \v.twaddr_0_sqmuxa\ : NOR2 - port map(A => un1_apbi_6, B => twaddr_0_sqmuxa_0, Y => - twaddr_0_sqmuxa); - - \r.rxstate[0]\ : DFN1 - port map(D => N_86, CLK => lclk_c, Q => \rxstate[0]\); - - \r.rsempty_RNIAD131\ : NOR3A - port map(A => loopb, B => rsempty, C => rcnt, Y => N_210_1); - - \un1_r.twaddr_I_1\ : AND2 - port map(A => \twaddr[0]\, B => twaddr_0_sqmuxa, Y => - \DWACT_ADD_CI_0_TMP_0[0]\); - - \r.rxtick\ : DFN1 - port map(D => rxtick_RNO, CLK => lclk_c, Q => rxtick); - - \r.rwaddr_RNIDEB1_0[1]\ : NOR2A - port map(A => \rwaddr[1]\, B => \rwaddr[0]\, Y => - rhold_2_0_sqmuxa_0); - - \r.irq_RNO_11\ : OR2 - port map(A => irq_10_1, B => irq_6_m, Y => irq_10_i); - - \r.rraddr_RNO[0]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_0[0]\, B => rstn, - Y => \rraddr_RNO[0]\); - - rdata_4_sqmuxa_0_a2 : NOR2A - port map(A => paddr(4), B => N_235, Y => \rdata_4_sqmuxa\); - - un4_scaler_I_27 : OR2 - port map(A => \un1_uart1[5]\, B => \un1_uart1[6]\, Y => - \DWACT_FDEC_E[1]\); - - \r.thold_tile_I_1_RNI1JRO\ : MX2 - port map(A => \DIN_REG1[2]\, B => \DOUT_TMP[2]\, S => N_7, - Y => \thold[3]\); - - \r.parerr_RNIQF933\ : OR2A - port map(A => parerr, B => \N_156\, Y => parerr_m); - - \r.rhold_1[4]\ : DFN1E0 - port map(D => \rhold_1_1[4]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[4]\); - - \r.rhold_3[5]\ : DFN1E0 - port map(D => \rhold_3_1[5]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[5]\); - - \r.dpar_RNIMSVB1\ : OAI1 - port map(A => rwaddr_0_sqmuxa_1_0, B => rwaddr_0_sqmuxa_1_1, - C => rwaddr_0_sqmuxa, Y => rwaddr_0_sqmuxa_0); - - \r.thold_tile_I_1_RNIF4SI4\ : OR3C - port map(A => N_155, B => \thold[4]\, C => \rdata_4_sqmuxa\, - Y => \rdata_17_m[3]\); - - \r.rhold_1_RNIEP39[0]\ : MX2C - port map(A => \rhold_1[0]\, B => \rhold_3[0]\, S => - \rraddr[1]\, Y => N_481); - - \r.txtick_RNIO1FF\ : OR2B - port map(A => txtick, B => N_133, Y => txstate_1); - - \r.dpar_RNO_1\ : NOR2B - port map(A => N_906, B => dpar_4, Y => dpar_4_m_0); - - \r.tshift_RNO_0[8]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[8]\, Y => N_196); - - \r.scaler[3]\ : DFN1E0 - port map(D => \scaler_1[3]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[5]\); - - \un1_r.irqcnt_I_21\ : XOR2 - port map(A => \irqcnt[1]\, B => \DWACT_ADD_CI_0_TMP[0]\, Y - => I_21); - - \uartop.v.traddr_1_i[0]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_2[0]\, B => rstn, - Y => N_35); - - \r.dpar_RNO_0\ : OAI1 - port map(A => N_876, B => N_906, C => rxtick, Y => N_875); - - \r.thold_tile_DIN_REG1[2]\ : DFN1 - port map(D => pwdata_2, CLK => lclk_c, Q => \DIN_REG1[2]\); - - \r.rhold_0_RNIC939[2]\ : MX2C - port map(A => \rhold_0[2]\, B => \rhold_2[2]\, S => - \rraddr[1]\, Y => N_475); - - \r.txd\ : DFN1 - port map(D => N_167, CLK => lclk_c, Q => txd1_c); - - \r.brate[7]\ : DFN1E1 - port map(D => pwdata_7, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[7]\); - - \un1_r.traddr_I_1\ : AND2 - port map(A => \traddr[0]\, B => \txstate_RNIURTC6[1]\, Y - => \DWACT_ADD_CI_0_TMP_3[0]\); - - \r.dpar\ : DFN1E0 - port map(D => dpar_1, CLK => lclk_c, E => N_875, Q => dpar); - - \r.irq_RNO_10\ : AOI1 - port map(A => irq10, B => delayirqen_0, C => irq_5, Y => - irq_7); - - \r.rwaddr_RNIDEB1_1[1]\ : NOR2A - port map(A => \rwaddr[0]\, B => \rwaddr[1]\, Y => - rhold_1_0_sqmuxa_0); - - \r.rhold_1_RNIG149[1]\ : MX2C - port map(A => \rhold_1[1]\, B => \rhold_3[1]\, S => - \rraddr[1]\, Y => N_164); - - \r.scaler[5]\ : DFN1E0 - port map(D => \scaler_1[5]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[7]\); - - \r.thold_tile_DIN_REG1[5]\ : DFN1 - port map(D => pwdata_5, CLK => lclk_c, Q => \DIN_REG1[5]\); - - \uartop.v.tcnt_11_0_0_1_SUM0_0\ : XOR3 - port map(A => \tcnt[0]\, B => twaddr_0_sqmuxa, C => N_22, Y - => \tcnt_11[0]\); - - \v.brate_1_sqmuxa_0\ : NOR3C - port map(A => pwrite, B => un1_apbi_2, C => rdata61, Y => - brate_1_sqmuxa_0); - - \un1_r.twaddr_I_10\ : XOR2 - port map(A => \twaddr[1]\, B => \DWACT_ADD_CI_0_TMP_0[0]\, - Y => I_10_1); - - un4_scaler_I_52 : XNOR2 - port map(A => N_14, B => \un1_uart1[11]\, Y => I_52_1); - - \r.brate[5]\ : DFN1E1 - port map(D => pwdata_5, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[5]\); - - \un1_r.irqcnt_I_31\ : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => \irqcnt[1]\, Y - => \DWACT_ADD_CI_0_g_array_1[0]\); - - \r.rxclk[1]\ : DFN1E0 - port map(D => \rxclk_1[1]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[1]\); - - \r.tshift_RNO_2[8]\ : OR2A - port map(A => \thold[8]\, B => N_134, Y => N_197); - - \r.rsempty_RNO_4\ : AO1C - port map(A => rsempty_1_sqmuxa, B => \rxstate[0]\, C => - rshift_0_sqmuxa_1, Y => N_441); - - \r.parerr_RNO_2\ : NOR2 - port map(A => break_1_sqmuxa, B => parerr_0_sqmuxa, Y => - parerr_0_sqmuxa_1); - - \r.break\ : DFN1 - port map(D => N_114, CLK => lclk_c, Q => break); - - \r.twaddr[0]\ : DFN1 - port map(D => N_31, CLK => lclk_c, Q => \twaddr[0]\); - - \r.rshift_RNO_0[5]\ : MX2 - port map(A => \rshift[6]\, B => \rshift[5]\, S => N_860, Y - => N_666); - - \r.irq_RNO_12\ : AO1 - port map(A => irq_5, B => \delayirqen\, C => irq_10_0, Y - => irq_10_1); - - \r.rcnt_RNI5J9Q1_0[1]\ : AX1E - port map(A => \rcnt[0]\, B => rwaddr_0_sqmuxa_0, C => - \rcnt[1]\, Y => N_913_i); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.tpar_RNO\ : MX2B - port map(A => parsel, B => tpar_3_i, S => \txstate[0]\, Y - => tpar_1); - - \r.txstate_RNO_8[0]\ : NOR2B - port map(A => \txstate[1]\, B => \txstate[0]\, Y => N_209); - - \r.breakirqen\ : DFN1E1 - port map(D => pwdata_12, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => \breakirqen\); - - \r.dpar_RNO_3\ : OR2B - port map(A => \rxstate[3]\, B => parsel, Y => parsel_m); - - \uartop.un1_apbi_2\ : NOR3C - port map(A => N_769, B => N_773, C => un1_apbi_2_0, Y => - un1_apbi_2); - - \r.brate_RNITQ7CB[3]\ : NOR3C - port map(A => \rdata_17_m[3]\, B => \brate_m[3]\, C => - \rdata_2_m[3]\, Y => \rdata_iv_1[3]\); - - \r.rshift_RNIE5DD1[1]\ : MX2 - port map(A => pwdata_1_0, B => \rshift[1]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_0_1[1]\); - - \r.rhold_0_RNIMH49[7]\ : MX2C - port map(A => \rhold_0[7]\, B => \rhold_2[7]\, S => - \rraddr[1]\, Y => N_480); - - \r.tshift_RNO_0[1]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[1]\, Y => N_175); - - \r.rfifoirqen_RNILLU53\ : OR2B - port map(A => rfifoirqen, B => \prdata[31]\, Y => - rfifoirqen_m); - - \r.tcnt_RNIF2583[2]\ : NOR2A - port map(A => \tcnt[2]\, B => \N_156\, Y => prdata_0); - - \r.thold_tile_DIN_REG1[3]\ : DFN1 - port map(D => pwdata_1_2, CLK => lclk_c, Q => \DIN_REG1[3]\); - - un4_scaler_I_41 : OR2 - port map(A => \un1_uart1[8]\, B => \un1_uart1[9]\, Y => - \DWACT_FDEC_E[3]\); - - un2_txclk_1_CO1 : NOR2B - port map(A => \txclk[1]\, B => N_976_i_2, Y => CO1_0); - - \r.tshift_RNO[1]\ : OR3C - port map(A => N_175, B => N_174, C => N_176, Y => - \tshift_13[1]\); - - un4_scaler_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \un1_uart1[7]\, Y => N_29_0); - - \r.rhold_0_RNO[3]\ : MX2 - port map(A => pwdata_1_2, B => \rshift[3]\, S => - rhold_0_1_sqmuxa_1, Y => \rhold_0_1[3]\); - - \r.rhold_1[5]\ : DFN1E0 - port map(D => \rhold_3_1[5]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[5]\); - - \r.flow_RNI99462\ : OR3B - port map(A => txtick_1, B => un2_ctsn_1, C => thempty_1, Y - => txtick_0); - - \un1_r.traddr_I_10\ : XOR2 - port map(A => \traddr[1]\, B => \DWACT_ADD_CI_0_TMP_3[0]\, - Y => I_10); - - \r.rxstate[2]\ : DFN1 - port map(D => \rxstate_nss[2]\, CLK => lclk_c, Q => - \rxstate[2]\); - - \r.frame_RNO_0\ : MX2 - port map(A => frame_1, B => \frame\, S => frame_0_sqmuxa, Y - => N_641); - - \r.rshift_RNO[3]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_664, Y => - \rshift_RNO_0[3]\); - - \r.scaler[8]\ : DFN1E0 - port map(D => \scaler_1[8]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[10]\); - - \uartop.rdata62_0_a2\ : OR2B - port map(A => un1_apbi_8, B => paddr(4), Y => \rdata62\); - - \r.tshift_RNO[0]\ : OR3C - port map(A => N_219, B => \tshift_1_0_0[0]\, C => rstn, Y - => \tshift_1[0]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.rxstate_RNIDMFC[0]\ : OR2B - port map(A => \rxstate[0]\, B => \rxdb[0]\, Y => - rwaddr_0_sqmuxa_1_0); - - \r.rxdb_RNO_3[0]\ : NOR2B - port map(A => \rxf[3]\, B => \rxf[2]\, Y => N_143); - - \uartop.un1_apbi_5\ : OR2A - port map(A => un1_apbi_2, B => pwrite, Y => un1_apbi_5); - - \r.ovf_RNIN7223\ : OR2A - port map(A => ovf, B => \N_156\, Y => ovf_m); - - \r.scaler_RNO_0[6]\ : MX2C - port map(A => \brate[6]\, B => I_31_3, S => tick_2_i, Y => - N_508); - - \r.scaler_RNO[3]\ : MX2A - port map(A => N_505, B => pwdata_0(3), S => - brate_1_sqmuxa_0, Y => \scaler_1[3]\); - - \r.irqpend_RNO_0\ : MX2 - port map(A => irqpend_1, B => irqpend, S => - irqpend_1_sqmuxa, Y => N_643); - - \r.rhold_1[1]\ : DFN1E0 - port map(D => \rhold_0_1[1]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[1]\); - - \r.scaler_RNI6J3I[11]\ : OR2A - port map(A => I_66_1, B => \un1_uart1[13]\, Y => tick_2_i); - - \r.rshift_RNIKHDD1[4]\ : MX2 - port map(A => pwdata_1_3, B => \rshift[4]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_1_1[4]\); - - \r.rxstate_RNIP1S6[2]\ : OR2B - port map(A => \rxstate[2]\, B => rstn, Y => N_78); - - \r.rhold_3[4]\ : DFN1E0 - port map(D => \rhold_3_1[4]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[4]\); - - un4_scaler_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_19); - - \r.rshift[7]\ : DFN1 - port map(D => \rshift_RNO_0[7]\, CLK => lclk_c, Q => - \rshift[7]\); - - \r.tshift_RNO_2[1]\ : OR2A - port map(A => \thold[1]\, B => N_134, Y => N_176); - - \r.tshift_RNO_1[3]\ : OR3B - port map(A => txtick, B => \tshift[4]\, C => N_133, Y => - N_180); - - \un1_r.traddr_I_8\ : XOR2 - port map(A => \traddr[0]\, B => \txstate_RNIURTC6[1]\, Y - => \DWACT_ADD_CI_0_partial_sum_2[0]\); - - \r.scaler_RNO[6]\ : MX2A - port map(A => N_508, B => pwdata_0(6), S => - brate_1_sqmuxa_0, Y => \scaler_1[6]\); - - \r.txstate_RNIVPSC[1]\ : NOR2A - port map(A => \txstate[0]\, B => \txstate[1]\, Y => N_243); - - \r.tshift[7]\ : DFN1 - port map(D => \tshift_13[7]\, CLK => lclk_c, Q => - \tshift[7]\); - - \r.rfifoirqen_RNILCKL\ : NOR2 - port map(A => un4_rhalffull_0, B => rhalffull_1, Y => - un4_rhalffull); - - \r.rsempty_RNO_6\ : OA1 - port map(A => dpar, B => \rcnt[2]\, C => \rxdb[0]\, Y => - rsempty_1_sqmuxa); - - \r.debug_RNISSGO3\ : NOR2 - port map(A => traddr_1_sqmuxa_0, B => un1_apbi_5, Y => - traddr_1_sqmuxa); - - \un1_r.irqcnt_I_23\ : XOR2 - port map(A => \irqcnt[3]\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_23); - - \r.rxstate[3]\ : DFN1 - port map(D => \rxstate_nss[1]\, CLK => lclk_c, Q => - \rxstate[3]\); - - \r.rcnt[1]\ : DFN1 - port map(D => \rcnt_RNO[1]\, CLK => lclk_c, Q => \rcnt[1]\); - - \r.rcnt[2]\ : DFN1 - port map(D => \rcnt_RNO[2]\, CLK => lclk_c, Q => \rcnt[2]\); - - \r.rhold_0[2]\ : DFN1E0 - port map(D => \rhold_0_1[2]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[2]\); - - \r.tcnt_RNO[0]\ : NOR2B - port map(A => \tcnt_11[0]\, B => rstn, Y => \tcnt_RNO_0[0]\); - - \r.tshift_RNO_3[0]\ : OR3B - port map(A => txtick, B => \tshift[1]\, C => N_133, Y => - N_218); - - \r.scaler_RNO_0[11]\ : OAI1 - port map(A => \un1_uart1[13]\, B => \brate[11]\, C => - I_66_1, Y => N_513); - - \r.scaler_RNO_0[4]\ : MX2C - port map(A => \brate[4]\, B => I_20_4, S => tick_2_i, Y => - N_506); - - \r.irqcnt[0]\ : DFN1 - port map(D => \irqcnt_1[0]\, CLK => lclk_c, Q => - \irqcnt[0]\); - - un4_scaler_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \un1_uart1[5]\, C => - \un1_uart1[6]\, Y => N_34); - - \un1_r.rcnt_1_0_1_SUM1_0_0\ : XOR2 - port map(A => N_913_i, B => rraddr_0_sqmuxa, Y => SUM1_0_0); - - \r.rxtick_RNO_0\ : AND2 - port map(A => rxtick_0_0, B => CO1, Y => rxtick_0_1); - - \un1_r.rcnt_1_0_1_CO0_i_a3_0\ : XA1C - port map(A => \rcnt[0]\, B => rwaddr_0_sqmuxa_0, C => - irq_5_2, Y => N_16); - - \r.tshift_RNITTO2[4]\ : NOR2B - port map(A => \tshift[4]\, B => \tshift[5]\, Y => - \txstate_ns_i_0_a2_4_1[0]\); - - \r.txstate_RNI40IB6[1]\ : OR2A - port map(A => N_134, B => traddr_1_sqmuxa, Y => N_22); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity apbctrl is - - port( hrdata : out std_logic_vector(31 downto 0); - pwdata : out std_logic_vector(31 downto 0); - psel_1 : out std_logic_vector(7 to 7); - prdata_4 : in std_logic_vector(31 to 31); - rdata_iv_0_2 : in std_logic_vector(1 to 1); - prdata_iv_0_0 : in std_logic_vector(2 to 2); - ramrws : in std_logic_vector(1 to 1); - ramwws : in std_logic_vector(1 downto 0); - romrws : in std_logic_vector(3 downto 1); - prdata_iv_0_2 : in std_logic; - prdata_iv_0_0_d0 : in std_logic; - un1_grgpio0_0 : in std_logic; - un1_grgpio0_2 : in std_logic; - ramwidth : in std_logic_vector(1 downto 0); - rdata_iv_2 : in std_logic_vector(3 downto 2); - readdata_iv_3 : in std_logic_vector(3 downto 2); - tcnt : in std_logic_vector(1 downto 0); - prdata_3_29 : in std_logic; - prdata_3_12 : in std_logic; - prdata_3_0 : in std_logic; - prdata_3_1 : in std_logic; - prdata_3_14 : in std_logic; - prdata_3_13 : in std_logic; - prdata_3_26 : in std_logic; - prdata_3_23 : in std_logic; - prdata_3_16 : in std_logic; - prdata_3_28 : in std_logic; - prdata_3_27 : in std_logic; - prdata_3_17 : in std_logic; - prdata_3_15 : in std_logic; - romwws : in std_logic_vector(3 downto 0); - romwidth : in std_logic_vector(1 downto 0); - rambanksz_0 : in std_logic; - rambanksz_1 : in std_logic; - rambanksz_3 : in std_logic; - prdata_0_iv_0_0_0_13 : in std_logic; - prdata_0_iv_0_0_0_0 : in std_logic; - prdata_0_iv_0_0_0_12 : in std_logic; - prdata_0_iv_0_0_1_13 : in std_logic; - prdata_0_iv_0_0_1_0 : in std_logic; - prdata_0_iv_0_0_1_12 : in std_logic; - readdata_1_iv_0_13 : in std_logic; - readdata_1_iv_0_2 : in std_logic; - readdata_1_iv_0_0 : in std_logic; - readdata_1_iv_0_9 : in std_logic; - readdata_1_iv_0_11 : in std_logic; - prdata_2_20 : in std_logic; - prdata_2_31 : in std_logic; - prdata_2_14 : in std_logic; - prdata_2_1 : in std_logic; - prdata_2_2 : in std_logic; - prdata_2_5 : in std_logic; - prdata_2_0 : in std_logic; - prdata_2_3 : in std_logic; - prdata_2_16 : in std_logic; - prdata_2_21 : in std_logic; - prdata_2_23 : in std_logic; - prdata_2_15 : in std_logic; - prdata_2_27 : in std_logic; - prdata_2_28 : in std_logic; - prdata_2_25 : in std_logic; - prdata_2_18 : in std_logic; - prdata_2_30 : in std_logic; - prdata_2_29 : in std_logic; - prdata_2_19 : in std_logic; - prdata_2_17 : in std_logic; - prdata_2_9 : in std_logic; - prdata_2_13 : in std_logic; - prdata_2_22 : in std_logic; - prdata_2_24 : in std_logic; - prdata_2_26 : in std_logic; - prdata_11_m_1_0 : in std_logic_vector(4 to 4); - prdata_13_m_1_0 : in std_logic_vector(4 to 4); - psel_0 : out std_logic; - psel_15 : out std_logic; - psel_11 : out std_logic; - reload_RNI6SNI : in std_logic_vector(1 to 1); - readdata_9_i_m : in std_logic_vector(1 to 1); - un1_uart1 : in std_logic_vector(36 to 36); - reload_m_0 : in std_logic_vector(0 to 0); - reload_0 : in std_logic_vector(7 downto 6); - un1_dcom0 : in std_logic_vector(19 downto 12); - iows : in std_logic_vector(3 downto 2); - ipend : in std_logic_vector(11 to 11); - iforce_0_m : in std_logic_vector(4 to 4); - ipend_m : in std_logic_vector(4 to 4); - iforce_0_5 : in std_logic; - iforce_0_2 : in std_logic; - iforce_0_1 : in std_logic; - iforce_0_7 : in std_logic; - iforce_0_0 : in std_logic; - ilevel_6 : in std_logic; - ilevel_4 : in std_logic; - ilevel_3 : in std_logic; - ilevel_2 : in std_logic; - ilevel_0 : in std_logic; - ilevel_8 : in std_logic; - ilevel_1 : in std_logic; - oen : in std_logic_vector(7 to 7); - readdata_2_m : in std_logic_vector(5 to 5); - dout_2 : in std_logic; - dout_0 : in std_logic; - dout_6 : in std_logic; - dout_5 : in std_logic; - dout_4 : in std_logic; - value_RNIBAHH : in std_logic_vector(1 to 1); - reload_RNIRDRG : in std_logic_vector(1 to 1); - scaler_i_m : in std_logic_vector(1 to 1); - scaler : in std_logic_vector(4 to 4); - value_6 : in std_logic; - value_0 : in std_logic; - reload_8 : in std_logic; - reload_7 : in std_logic; - reload_6 : in std_logic; - reload_24 : in std_logic; - reload_4 : in std_logic; - reload_3 : in std_logic; - reload_2 : in std_logic; - reload_0_d0 : in std_logic; - reload_1 : in std_logic; - scaler_m_7 : in std_logic; - scaler_m_6 : in std_logic; - scaler_m_0 : in std_logic; - scaler_m_5 : in std_logic; - rcnt : in std_logic_vector(1 downto 0); - rdata_2 : in std_logic_vector(0 to 0); - rcnt_RNI8FBM3 : in std_logic_vector(1 to 1); - rdata_iv_0_a2_3_0 : in std_logic_vector(7 to 7); - brate_9 : in std_logic; - brate_8 : in std_logic; - brate_0 : in std_logic; - brate_10 : in std_logic; - brate_7 : in std_logic; - brate_6 : in std_logic; - rdata_17_m_0 : in std_logic_vector(6 to 6); - brate_m_7 : in std_logic; - brate_m_0 : in std_logic; - brate_m_1 : in std_logic; - rdata_17_m_0_d0 : in std_logic; - rdata_17_m_4 : in std_logic; - rdata_17_m_5 : in std_logic; - rdata_2_m : in std_logic_vector(6 downto 4); - prdata_1_20 : in std_logic; - prdata_1_5 : in std_logic; - prdata_1_12 : in std_logic; - prdata_1_21 : in std_logic; - prdata_1_23 : in std_logic; - prdata_1_27 : in std_logic; - prdata_1_0 : in std_logic; - prdata_1_4 : in std_logic; - prdata_1_6 : in std_logic; - prdata_1_7 : in std_logic; - prdata_1_8 : in std_logic; - prdata_1_9 : in std_logic; - prdata_1_10 : in std_logic; - prdata_1_11 : in std_logic; - prdata_1_22 : in std_logic; - prdata_1_28 : in std_logic; - paddr_5 : out std_logic; - paddr_2_d0 : out std_logic; - paddr_0_d0 : out std_logic; - paddr_1_d0 : out std_logic; - paddr_3 : out std_logic; - paddr_4 : out std_logic; - htrans : in std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - readdata_9_4 : in std_logic; - readdata_9_0 : in std_logic; - readdata_9_5 : in std_logic; - readdata_9_27 : in std_logic; - reload_m_2 : in std_logic; - reload_m_3 : in std_logic; - reload_m_21 : in std_logic; - reload_m_9 : in std_logic; - reload_m_0_d0 : in std_logic; - reload_m_5 : in std_logic; - reload_m_27 : in std_logic; - reload_m_20 : in std_logic; - reload_m_4 : in std_logic; - value_m_22 : in std_logic; - value_m_11 : in std_logic; - value_m_9 : in std_logic; - value_m_18 : in std_logic; - value_m_20 : in std_logic; - value_m_17 : in std_logic; - value_m_4 : in std_logic; - value_m_5 : in std_logic; - value_m_3 : in std_logic; - value_m_0 : in std_logic; - value_m_1 : in std_logic; - value_m_8 : in std_logic; - value_m_7 : in std_logic; - value_m_6 : in std_logic; - value_m_23 : in std_logic; - value_m_24 : in std_logic; - value_m_16 : in std_logic; - prdata_0_1 : in std_logic; - prdata_0_23 : in std_logic; - prdata_0_18 : in std_logic; - prdata_0_30 : in std_logic; - prdata_0_29 : in std_logic; - prdata_0_0 : in std_logic; - prdata_0_8 : in std_logic; - prdata_0_10 : in std_logic; - prdata_0_11 : in std_logic; - prdata_0_12 : in std_logic; - prdata_0_13 : in std_logic; - prdata_0_24 : in std_logic; - prdata_0_26 : in std_logic; - prdata_0_17 : in std_logic; - prdata_0_19 : in std_logic; - prdata_0_25 : in std_logic; - prdata_0_16 : in std_logic; - prdata_0_22 : in std_logic; - prdata_0_15 : in std_logic; - prdata_0_31 : in std_logic; - prdata_0_14 : in std_logic; - prdata_0_21 : in std_logic; - prdata_0_27 : in std_logic; - prdata_0_20 : in std_logic; - prdata_0_4 : in std_logic; - prdata_0_6 : in std_logic; - prdata_0_7 : in std_logic; - prdata_0_5 : in std_logic; - prdata_0_3 : in std_logic; - prdata_0_2 : in std_logic; - prdata_0_28 : in std_logic; - prdata : in std_logic_vector(31 downto 0); - pwdata_i : out std_logic_vector(7 downto 0); - pwdata_1_3 : out std_logic; - pwdata_1_2 : out std_logic; - pwdata_1_0 : out std_logic; - hwdata : in std_logic_vector(31 downto 0); - pwdata_0 : out std_logic_vector(15 downto 0); - paddr_0 : out std_logic_vector(4 downto 2); - paddr_1 : out std_logic_vector(2 to 2); - haddr : in std_logic_vector(19 downto 2); - paddr_2 : out std_logic_vector(2 to 2); - hready : out std_logic; - readdata51_1 : in std_logic; - N_227 : in std_logic; - thempty_1_m : in std_logic; - N_6432 : in std_logic; - rmw : in std_logic; - penable : out std_logic; - un1_apbi_2 : in std_logic; - N_5062 : in std_logic; - break_m : in std_logic; - N_332 : in std_logic; - N_333 : in std_logic; - N_334 : in std_logic; - N_335 : in std_logic; - N_336 : in std_logic; - N_5070 : in std_logic; - breakirqen : in std_logic; - N_6455_0 : in std_logic; - N_773 : out std_logic; - hwrite : in std_logic; - un1_apbi_7_3 : out std_logic; - N_330 : in std_logic; - parerr_m : in std_logic; - rdata60_1 : in std_logic; - N_331 : in std_logic; - N_86 : in std_logic; - N_85 : in std_logic; - un1_apbi_7_1 : in std_logic; - rstn : in std_logic; - bexcen : in std_logic; - ioen : in std_logic; - ovf_m : in std_logic; - parsel_m_0 : in std_logic; - frame : in std_logic; - tcnt_i : in std_logic; - N_156 : in std_logic; - readdata56 : in std_logic; - tfifoirqen_m : in std_logic; - rfifoirqen_m : in std_logic; - debug_m : in std_logic; - delayirqen : in std_logic; - N_127 : in std_logic; - N_78 : out std_logic; - N_232_0 : in std_logic; - brdyen : in std_logic; - N_839 : in std_logic; - prdata_1_sqmuxa : in std_logic; - N_842 : in std_logic; - N_841 : in std_logic; - N_476 : in std_logic; - N_478 : in std_logic; - N_474 : in std_logic; - N_473 : in std_logic; - N_471 : in std_logic; - N_472 : in std_logic; - N_470 : in std_logic; - N_467 : in std_logic; - N_468 : in std_logic; - N_859 : in std_logic; - N_861 : in std_logic; - N_361 : in std_logic; - N_363 : in std_logic; - readdata55_3 : in std_logic; - N_863 : in std_logic; - N_865 : in std_logic; - N_365 : in std_logic; - N_898 : in std_logic; - N_367 : in std_logic; - prdata_0_sqmuxa : in std_logic; - rdata60_4_0 : in std_logic; - N_6437 : in std_logic; - N_6439 : in std_logic; - N_6435 : in std_logic; - N_6436 : in std_logic; - N_6434 : in std_logic; - N_6429 : in std_logic; - N_6430 : in std_logic; - N_6428 : in std_logic; - rdata59_4 : in std_logic; - N_220_0 : in std_logic; - N_219 : in std_logic; - N_240 : in std_logic; - N_218 : in std_logic; - N_236 : in std_logic; - N_229 : in std_logic; - N_228 : in std_logic; - N_216 : in std_logic; - N_217 : in std_logic; - dishlt : in std_logic; - restart_RNIIKBB : in std_logic; - N_215 : in std_logic; - N_214 : in std_logic; - N_240_0 : in std_logic; - readdata57 : in std_logic; - irqpen_m : in std_logic; - readdata55 : in std_logic; - enable_m : in std_logic; - value_0_sqmuxa_0 : in std_logic; - chain_m : in std_logic; - readdata_1_sqmuxa_1_0 : in std_logic; - tsemptyirqen : in std_logic; - rdata_0_sqmuxa : in std_logic; - N_223 : in std_logic; - N_220 : in std_logic; - rdata_3_sqmuxa : in std_logic; - rdata_4_sqmuxa : in std_logic; - paren : in std_logic; - N_770 : in std_logic; - rhalffull_1_m : in std_logic; - flow_m : in std_logic; - extclken_m : in std_logic; - N_769 : out std_logic; - N_116 : out std_logic; - N_796 : out std_logic; - N_750 : out std_logic; - N_749 : out std_logic; - lclk_c : in std_logic; - pwrite : out std_logic; - un51_ioen_NE : in std_logic - ); - -end apbctrl; - -architecture DEF_ARCH of apbctrl is - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal hready_0_sqmuxa_0, hready_0_sqmuxa_0_a3_0_a2_0, - N_12_0_1, \state[0]\, N_12_0_0, \pwrite\, N_751_0, N_745, - N_752_0, N_12_0, \pwdata_0[0]\, \pwdata_0[1]\, - \pwdata_0[2]\, \pwdata_0[3]\, \pwdata_0[4]\, - \pwdata_0[5]\, \pwdata_0[6]\, \pwdata_0[7]\, - \prdata_1_i_0_a11[20]\, N_782_i, \prdata_1_i_0_a11[28]\, - N_678, N_756, \prdata_1_i_0_a11[27]\, - \prdata_1_i_0_a11[21]\, N_111, cfgsel, N_156_i, N_786, - N_101, N_710, \prdata_1_i_0_a11_2_1[20]\, N_50_i_0, - \prdata_1_i_0_4[28]\, N_585, \prdata_1_i_0_a11_6_1[8]\, - N_619_i, \prdata_1_i_0_a11_3_4[4]\, N_675, - \prdata_1_i_0_a11_1_1[28]\, N_681, - \prdata_1_i_0_a11_1_1[27]\, \prdata_1_i_0_a11_2_0[20]\, - \prdata_1_i_0_a11_1_0[27]\, N_761, - \prdata_1_i_0_a11_3_3[4]\, \prdata_1_i_0_a11_3_2[4]\, - \prdata_1_i_0_a11_8_3[6]\, \prdata_1_i_0_a11_8_2[6]\, - \prdata_1_i_0_a11_8_1[6]\, \prdata_1_i_0_a11_8_0[6]\, - \prdata_1_i_0_a11_6_0[8]\, \prdata_1_i_0_3[28]\, - \prdata_1_i_0_2[28]\, \prdata_1_i_0_3[27]\, - \prdata_1_0_0_7[1]\, \prdata_1_0_0_3[1]\, - \prdata_1_0_0_2[1]\, N_630_i, \prdata_1_0_0_6[1]\, N_628, - N_632, N_629, N_633, N_624, \prdata_1_0_0_0[1]\, N_627, - \prdata_1_0_0_a11_1_0[1]\, N_776, N_625, - \prdata_1_0_0_6[2]\, N_735, \prdata_1_0_0_3[2]\, - \prdata_1_0_0_4[2]\, N_733, \prdata_1_0_0_0[2]\, - \prdata_1_0_0_2[2]\, N_762, N_734, N_739, N_722, N_732, - \prdata_1_0_0_7[3]\, N_726, \prdata_1_0_0_4[3]\, - \prdata_1_0_0_5[3]\, N_724, \prdata_1_0_0_1[3]\, - \prdata_1_0_0_3[3]\, N_725, N_730, \prdata_1_0_0_0[3]\, - N_721, N_777, \prdata_1_i_0_8[5]\, - \prdata_1_i_0_a11_4_4[5]\, \prdata_1_i_0_7[5]\, - \prdata_1_i_0_3[5]\, \prdata_1_i_0_2[5]\, - \prdata_1_i_0_6[5]\, \prdata_1_i_0_a11_3_1[5]\, N_771, - \prdata_1_i_0_4[5]\, \prdata_RNO_21[5]\, N_755, N_612_i, - \prdata_RNO_12[5]\, \prdata_1_i_0_0[5]\, - \prdata_RNO_14[5]\, N_544, \prdata_1_i_0_6[7]\, - \prdata_1_i_0_2[7]\, \prdata_1_i_0_1[7]\, - \prdata_1_i_0_5[7]\, \prdata_1_i_0_a11_2_1[7]\, - \prdata_1_i_0_3[7]\, \prdata_RNO_20[7]\, N_592_i, - \prdata_RNO_9[7]\, \prdata_RNO_10[7]\, N_554_i, - \prdata_1_i_0_7[6]\, \prdata_1_i_0_3[6]\, - \prdata_1_i_0_2[6]\, \prdata_1_i_0_6[6]\, - \prdata_1_i_0_a11_3_1[6]\, \prdata_1_i_0_4[6]\, - \prdata_RNO_23[6]\, N_602_i, \prdata_RNO_12[6]\, - \prdata_1_i_0_0[6]\, \prdata_RNO_14[6]\, N_595, N_139, - \prdata_1_i_0_6[4]\, \prdata_1_i_0_2[4]\, - \prdata_1_i_0_1[4]\, \prdata_1_i_0_5[4]\, - \prdata_1_i_0_a11_2_1[4]\, \prdata_1_i_0_3[4]\, - \prdata_RNO_15[4]\, N_621_i, \prdata_RNO_7[4]\, - \prdata_RNO_8[4]\, \prdata_1_i_0_6[10]\, - \prdata_1_i_0_a11_1_1[10]\, \prdata_1_i_0_4[10]\, - \prdata_1_i_0_5[10]\, N_567_i, \prdata_1_i_0_2[10]\, - \prdata_RNO_9[10]\, \prdata_1_i_0_0[10]\, - \prdata_RNO_13[10]\, \prdata_RNO_14[10]\, - \prdata_RNO_15[10]\, \prdata_1_i_0_8[0]\, - \prdata_1_i_0_4[0]\, N_641, \prdata_1_i_0_7[0]\, - \prdata_1_i_0_a11_6_1[0]\, \prdata_1_i_0_5[0]\, - \prdata_RNO_18[0]\, \prdata_1_i_0_2[0]\, - \prdata_RNO_10[0]\, \prdata_1_i_0_0[0]\, - \prdata_1_i_0_1[0]\, N_790, N_82, N_638, - \prdata_1_i_0_1[28]\, \prdata_1_i_0_RNO_3[28]\, - \prdata_1_i_0_RNO_4[28]\, \prdata_1_i_0_6[20]\, - \prdata_RNO_3[20]\, \prdata_1_i_0_3[20]\, - \prdata_1_i_0_5[20]\, \prdata_1_i_0_1[20]\, - \prdata_RNO_6[20]\, N_708, N_789, N_760, - \prdata_1_i_0_2[27]\, \prdata_1_i_0_1[27]\, - \prdata_RNO_4[27]\, \prdata_RNO_5[27]\, - \prdata_1_i_0_6[21]\, \prdata_RNO_3[21]\, - \prdata_1_i_0_3[21]\, N_703, \prdata_1_i_0_5[21]\, - \prdata_1_i_0_1[21]\, \prdata_RNO_7[21]\, N_84, - \prdata_1_i_0_0[21]\, \paddr_0[4]\, \prdata_1_i_0_6[11]\, - \prdata_1_i_0_a11_2_1[11]\, \prdata_1_i_0_4[11]\, - \prdata_1_i_0_5[11]\, N_559_i, \prdata_1_i_0_2[11]\, - \prdata_RNO_8[11]\, \prdata_1_i_0_0[11]\, - \prdata_RNO_12[11]\, \prdata_RNO_13[11]\, - \prdata_RNO_14[11]\, \prdata_1_i_0_6[9]\, - \prdata_1_i_0_3[9]\, \prdata_1_i_0_2[9]\, - \prdata_1_i_0_4[9]\, \prdata_RNO_12[9]\, - \prdata_1_i_0_a11_4_2[9]\, \prdata_1_i_0_0[9]\, - \prdata_RNO_11[9]\, N_778_i, \prdata_0[9]\, - \prdata_RNO_15[9]\, \prdata_1_i_0_6[8]\, - \prdata_RNO_2[8]\, \prdata_RNO_3[8]\, N_580_i, - \prdata_1_i_0_5[8]\, \prdata_RNO_5[8]\, - \prdata_1_i_0_1[8]\, \prdata_1_i_0_3[8]\, - \prdata_1_i_0_a11_4_2[8]\, \prdata_RNO_10[8]\, - \prdata_RNO_11[8]\, \prdata_1_i_0_7[12]\, - \prdata_1_i_0_a11_3_1[12]\, \prdata_1_i_0_5[12]\, - \prdata_1_i_0_6[12]\, N_550_i, \prdata_1_i_0_3[12]\, - \prdata_RNO_8[12]\, \prdata_1_i_0_1[12]\, - \prdata_RNO_12[12]\, \prdata_RNO_13[12]\, - \prdata_RNO_14[12]\, N_543, \prdata_1_i_0_a11_8_3[5]\, - \prdata_1_i_0_a11_8_2[5]\, \prdata_1_i_0_a11_8_0[5]\, - \prdata_1_i_0_a11_7_2[4]\, \prdata_1_i_0_a11_7_0[4]\, - \prdata_1_i_0_a11_7_3[7]\, \prdata_1_i_0_a11_7_1[7]\, - \prdata_1_i_0_a11_7_0[7]\, \prdata_1_0_0_3[26]\, N_516, - \prdata_1_0_0_0[26]\, \prdata_1_0_0_2[26]\, N_519, - \prdata_1_0_0_a11_0[26]\, N_767, N_515, - \prdata_1_i_0_a11_6_0[10]\, \prdata_1_0_0_0_7[14]\, N_758, - \prdata_1_0_0_0_6[14]\, N_207, N_498, - \prdata_1_0_0_0_5[14]\, N_204, \prdata_1_0_0_0_1[14]\, - \prdata_1_0_0_0_3[14]\, N_499, N_202, \prdata_RNO_9[14]\, - N_138, \prdata_1_0_0_6[13]\, N_537, N_540, - \prdata_1_0_0_5[13]\, N_536, \prdata_1_0_0_1[13]\, - \prdata_1_0_0_3[13]\, N_541, \prdata_RNO_9[13]\, N_534, - \prdata_1_0_0_0_2[31]\, \prdata_1_0_0_0_1[31]\, N_509, - N_507, N_510, \prdata_1_i_0_a11_9_3[0]\, - \prdata_1_i_0_a11_9_1[0]\, \prdata_1_i_0_a11_9_0[0]\, - \prdata_1_i_i_5[22]\, \prdata_1_i_i_3[22]\, - \prdata_1_i_i_2[22]\, N_530, N_532, N_527, - \prdata_1_i_i_0[22]\, N_529, N_781, N_526, - \prdata_1_i_0_a11_6_0[9]\, \prdata_1_0_0_a11_5_0[26]\, - \prdata_1_0_0_a11_7_0[14]\, \prdata_1_0_0_2[24]\, N_751, - N_525, \prdata_1_0_0_1[24]\, N_521, N_522, - \prdata_1_0_0_2[17]\, N_649, N_646, \prdata_1_0_0_1[17]\, - N_647, \prdata_1_0_0_2[19]\, N_655, N_654, - \prdata_1_0_0_0[19]\, N_651, \prdata_1_0_0_2[25]\, N_669, - N_668, \prdata_1_0_0_1[25]\, N_672, \prdata_1_0_0_6[15]\, - N_688, \prdata_1_0_0_2[15]\, \prdata_1_0_0_4[15]\, - \prdata_1_0_0_5[15]\, N_689, N_693, \prdata_RNO_7[15]\, - \prdata_1_0_0_0[15]\, \prdata_1_0_0_a11_1_0[15]\, N_766, - N_685, \prdata_1_i_i_4[23]\, N_699, N_698, - \prdata_1_i_i_2[23]\, N_694, \prdata_1_i_i_0[23]\, N_696, - \paddr[6]\, \prdata_1_0_0_4[16]\, \prdata_1_0_0_1[16]\, - N_717, \prdata_1_0_0_2[16]\, N_720, N_715, N_714, N_716, - \prdata_1_0_0_1[29]\, N_658, N_656, N_659, - \prdata_1_0_0_1[30]\, N_662, N_660, N_663, - \prdata_1_0_0_1[18]\, N_666, N_664, N_667, - \prdata_1_i_0_a11_4_1[5]\, \prdata_1_i_0_a11_4_2[5]\, - \prdata_1_i_0_a11_3_4[0]\, \prdata_1_i_0_a11_3_3[0]\, - \prdata_1_i_0_a11_3_1[0]\, \paddr[9]\, N_747, - \prdata_1_i_0_a11_3_1[4]\, \prdata_1_i_0_a11_4_4[6]\, - \prdata_1_i_0_a11_4_1[6]\, \prdata_1_i_0_a11_4_0[6]\, - \prdata_1_i_0_a11_4_2[6]\, \prdata_1_i_0_a11_3_3[7]\, - \prdata_1_i_0_a11_3_0[7]\, \prdata_1_i_0_a11_3_1[7]\, - \prdata_1_0_0_a11_5_3[1]\, \prdata_1_0_0_a11_5_1[1]\, - \prdata_1_i_0_a11_1_2[9]\, \prdata_1_i_0_a11_1_0[9]\, - \prdata_1_i_0_a11_1_2[8]\, \prdata_1_i_0_a11_1_0[8]\, - \prdata_1_i_0_a11_2_0[21]\, \prdata_1_i_0_a11_1_0[28]\, - \prdata_1_i_0_a11_1_0[10]\, \prdata_1_i_0_a11_2_0[11]\, - \prdata_1_i_0_a11_3_0[12]\, \prdata_1_i_0_a11_3_0[5]\, - \un1_grgpio0_m[69]\, \prdata_1_i_0_a11_3_0[6]\, - \prdata_1_i_0_a11_2_0[7]\, \un1_grgpio0_m[71]\, - \prdata_1_i_0_a11_6_1[5]\, \prdata_1_i_0_a11_6_0[5]\, - \prdata_1_i_0_a11_6_1[12]\, \prdata_1_i_0_a11_6_0[12]\, - \prdata_1_i_0_a11_5_1[4]\, \prdata_RNO_16[4]\, - \prdata_1_i_0_a11_5_0[4]\, \prdata_1_i_0_a11_6_1[6]\, - \prdata_1_i_0_a11_6_0[6]\, \prdata_1_i_0_a11_5_1[7]\, - \prdata_1_i_0_a11_5_0[7]\, \prdata_1_i_0_a11_4_1[8]\, - \prdata_1_i_0_a11_4_1[9]\, \prdata_1_i_0_a11_4_1[10]\, - \prdata_1_i_0_a11_4_0[10]\, \prdata_1_i_0_a11_5_1[11]\, - \prdata_1_i_0_a11_5_0[11]\, \prdata_1_i_0_o2_0[11]\, N_90, - \prdata_1_0_0_a11_0[13]\, \prdata_1_i_0_a2_0[21]\, - \paddr[10]\, \paddr[11]\, \psel_0_a3_0_a2_0_a11_0[11]\, - N_772, \prdata_1_i_0_o2_1_0[12]\, \N_78\, - \prdata_1_0_0_0_a2_0[14]\, \paddr_0[3]\, - penable_1_0_0_i_0_a11_0_4, \paddr[13]\, \paddr[12]\, - penable_1_0_0_i_0_a11_0_1, penable_1_0_0_i_0_a11_0_3, - \paddr[18]\, \paddr[19]\, penable_1_0_0_i_0_a11_0_2, - \paddr[16]\, \paddr[17]\, \paddr[14]\, \paddr[15]\, - \prdata_1_i_0_o2_1_5[0]\, \prdata_1_i_0_o2_1_3[0]\, - \prdata_1_i_0_o2_1_4[0]\, \prdata_1_i_0_o2_1_1[0]\, N_763, - N_542, N_561, N_569, N_572_i, N_577_i, N_590_i, N_594_i, - N_600_i, N_604_i, N_623_i, \prdata_1[3]\, N_727, N_731, - \prdata_1[16]\, N_41_i_0, \prdata_RNO_2[21]\, N_60, - \prdata_1[15]\, N_690, N_46_i_0, \prdata_RNO_2[27]\, - \prdata_1[25]\, \prdata_1[18]\, \prdata_1[30]\, - \prdata_1[29]\, \prdata_1[19]\, \prdata_1[17]\, N_58_i_0, - N_639_i, N_645_i, N_61_i_0, N_65_i_0, N_100_i_0, - N_102_i_0, N_104_i_0, N_106_i_0, N_108_i_0, N_110_i_0, - \prdata_RNO_2[12]\, \prdata_1[13]\, N_538, N_30, - \prdata_1[24]\, N_523, penable_RNO, cfgsel2, N_199, N_774, - \paddr_0[2]\, N_117, N_5065, N_63_i_0, hready_0_sqmuxa, - N_5063, \prdata_1[31]\, \prdata_1[2]\, N_736, N_740, - N_6427, \prdata_1[1]\, N_634, \prdata_1[14]\, N_176, - N_794, \N_769\, N_39_i_0, \prdata_RNO_2[20]\, - \prdata_1[26]\, N_517, N_520, \un1_apbi_7_3\, \paddr[5]\, - N_793, \prdata_1_i_0_a11_0[0]\, \prdata_1_i_0_a11_1_0[0]\, - \paddr[8]\, \N_116\, N_5913, \state_nss[0]\, N_795, N_788, - N_131, N_743, N_455, N_132, N_791, N_752, N_744, \N_749\, - N_748, \state[1]\, N_12, N_17, psel_RNO_0, N_5069, - \paddr_2[2]\, \dout_m[1]\, \dout_m[3]\, N_133, \paddr[2]\, - \paddr[3]\, \N_750\, \paddr[4]\, N_155_i, N_746, \N_773\, - psel, N_5860, \state_nss[1]\, N_198, N_34, N_168, - \penable\, \hready\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - paddr_2_d0 <= \paddr[4]\; - paddr_0_d0 <= \paddr[2]\; - paddr_1_d0 <= \paddr[3]\; - paddr_3 <= \paddr[5]\; - paddr_4 <= \paddr[6]\; - pwdata_0(7) <= \pwdata_0[7]\; - pwdata_0(6) <= \pwdata_0[6]\; - pwdata_0(5) <= \pwdata_0[5]\; - pwdata_0(4) <= \pwdata_0[4]\; - pwdata_0(3) <= \pwdata_0[3]\; - pwdata_0(2) <= \pwdata_0[2]\; - pwdata_0(1) <= \pwdata_0[1]\; - pwdata_0(0) <= \pwdata_0[0]\; - paddr_0(4) <= \paddr_0[4]\; - paddr_0(3) <= \paddr_0[3]\; - paddr_0(2) <= \paddr_0[2]\; - paddr_2(2) <= \paddr_2[2]\; - hready <= \hready\; - penable <= \penable\; - N_773 <= \N_773\; - un1_apbi_7_3 <= \un1_apbi_7_3\; - N_78 <= \N_78\; - N_769 <= \N_769\; - N_116 <= \N_116\; - N_750 <= \N_750\; - N_749 <= \N_749\; - pwrite <= \pwrite\; - - \r.pwdata[15]\ : DFN1E0 - port map(D => hwdata(15), CLK => lclk_c, E => N_12_0, Q => - pwdata(15)); - - \r.prdata_RNO_16[0]\ : AOI1B - port map(A => N_790, B => N_82, C => N_638, Y => - \prdata_1_i_0_0[0]\); - - \r.prdata_RNO_0[10]\ : AOI1B - port map(A => \prdata_1_i_0_a11_1_1[10]\, B => value_m_6, C - => \prdata_1_i_0_4[10]\, Y => \prdata_1_i_0_6[10]\); - - \r.prdata_RNO[6]\ : NOR3C - port map(A => N_600_i, B => \prdata_1_i_0_7[6]\, C => - N_604_i, Y => N_65_i_0); - - \r.prdata_RNO_3[29]\ : OR2B - port map(A => prdata_3_27, B => N_752, Y => N_659); - - \r.prdata_RNO_15[9]\ : OR3A - port map(A => N_772, B => N_743, C => prdata_1_9, Y => - \prdata_RNO_15[9]\); - - \r.prdata_RNO_2[10]\ : OR3C - port map(A => rfifoirqen_m, B => \prdata_1_i_0_a11_6_0[10]\, - C => prdata_0_28, Y => N_569); - - \r.prdata_RNO_8[12]\ : OR2A - port map(A => N_752, B => prdata_1_12, Y => - \prdata_RNO_8[12]\); - - \r.prdata_RNO_2[9]\ : OR3 - port map(A => prdata_0_22, B => \prdata_1_i_0_a11_6_0[9]\, - C => tfifoirqen_m, Y => N_577_i); - - \r.prdata_RNO_3[23]\ : NOR3C - port map(A => N_694, B => \prdata_1_i_i_0[23]\, C => N_696, - Y => \prdata_1_i_i_2[23]\); - - \r.prdata_RNO[8]\ : NOR3C - port map(A => \prdata_1_i_0_6[8]\, B => \prdata_1_i_0_5[8]\, - C => N_585, Y => N_102_i_0); - - \r.prdata_RNO_4[14]\ : AO1B - port map(A => prdata_0_iv_0_0_1_13, B => - prdata_0_iv_0_0_0_13, C => N_762, Y => N_498); - - \r.prdata_RNO_0[0]\ : NOR3C - port map(A => \prdata_1_i_0_4[0]\, B => N_641, C => - \prdata_1_i_0_7[0]\, Y => \prdata_1_i_0_8[0]\); - - \r.pwdata[30]\ : DFN1E0 - port map(D => hwdata(30), CLK => lclk_c, E => N_12, Q => - pwdata(30)); - - \r.prdata_RNO_7[14]\ : NOR3C - port map(A => N_202, B => \prdata_RNO_9[14]\, C => N_138, Y - => \prdata_1_0_0_0_1[14]\); - - \r.prdata_RNO[19]\ : AO1B - port map(A => prdata_0_19, B => N_758, C => - \prdata_1_0_0_2[19]\, Y => \prdata_1[19]\); - - \r.prdata[2]\ : DFN1 - port map(D => \prdata_1[2]\, CLK => lclk_c, Q => hrdata(2)); - - \r.prdata_RNO_3[27]\ : NOR3C - port map(A => \prdata_RNO_4[27]\, B => - \prdata_1_i_0_a11[27]\, C => \prdata_RNO_5[27]\, Y => - \prdata_1_i_0_1[27]\); - - \r.prdata_RNO_1[31]\ : NOR3C - port map(A => N_509, B => N_507, C => N_510, Y => - \prdata_1_0_0_0_1[31]\); - - \r.prdata_RNO_5[7]\ : AOI1B - port map(A => \prdata_1_i_0_a11_2_1[7]\, B => N_771, C => - \prdata_1_i_0_3[7]\, Y => \prdata_1_i_0_5[7]\); - - \r.prdata_RNO_12[6]\ : AO1C - port map(A => \paddr_0[3]\, B => N_455, C => N_767, Y => - \prdata_RNO_12[6]\); - - \r.prdata_RNO_12[0]\ : OA1A - port map(A => N_751_0, B => prdata(0), C => - \prdata_RNO_18[0]\, Y => \prdata_1_i_0_5[0]\); - - \r.prdata_RNO_4[23]\ : OR3B - port map(A => iows(3), B => N_767, C => N_232_0, Y => N_694); - - \r.pwdata_0[11]\ : DFN1E0 - port map(D => hwdata(11), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(11)); - - \r.prdata_RNO_4[0]\ : OR2A - port map(A => prdata_0_0, B => N_763, Y => N_641); - - \r.cfgsel_RNIESL4\ : OR2B - port map(A => cfgsel, B => N_90, Y => N_793); - - \r.hwrite_RNO\ : NOR2B - port map(A => rstn, B => N_5913, Y => N_17); - - \r.prdata_RNO_11[10]\ : AOI1B - port map(A => iforce_0_5, B => N_898, C => N_476, Y => - \prdata_1_i_0_a11_4_0[10]\); - - \r.prdata_RNO_4[27]\ : OR3A - port map(A => N_744, B => \N_78\, C => prdata_1_27, Y => - \prdata_RNO_4[27]\); - - \r.prdata_RNO_1[18]\ : OR2B - port map(A => prdata_2_18, B => N_751, Y => N_666); - - \r.prdata_RNO[17]\ : AO1B - port map(A => prdata_0_17, B => N_758, C => - \prdata_1_0_0_2[17]\, Y => \prdata_1[17]\); - - \r.prdata_RNO_6[11]\ : NOR3B - port map(A => \prdata_1_i_0_0[11]\, B => - \prdata_RNO_12[11]\, C => N_554_i, Y => - \prdata_1_i_0_2[11]\); - - \r.haddr[17]\ : DFN1E1 - port map(D => haddr(17), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[17]\); - - \r.prdata_RNO_1[0]\ : OR3C - port map(A => \prdata_1_i_0_a11_3_4[0]\, B => - \prdata_1_i_0_a11_3_3[0]\, C => reload_m_0(0), Y => - N_639_i); - - \r.prdata_RNO_13[7]\ : AOI1B - port map(A => N_240_0, B => N_215, C => N_758, Y => - \prdata_1_i_0_a11_3_0[7]\); - - \r.prdata_RNO_0[22]\ : NOR3C - port map(A => \prdata_1_i_i_3[22]\, B => - \prdata_1_i_i_2[22]\, C => N_530, Y => - \prdata_1_i_i_5[22]\); - - \r.prdata_RNO_7[3]\ : OR3B - port map(A => N_331, B => rdata60_1, C => N_763, Y => N_725); - - \r.prdata_RNO_11[12]\ : NOR3B - port map(A => \prdata_RNO_14[12]\, B => N_543, C => N_544, - Y => \prdata_1_i_0_1[12]\); - - \r.prdata_RNO_4[3]\ : AOI1B - port map(A => prdata(3), B => N_762, C => N_725, Y => - \prdata_1_0_0_4[3]\); - - \r.prdata_RNO_8[16]\ : XOR2 - port map(A => \paddr[4]\, B => \paddr[3]\, Y => N_155_i); - - \r.prdata_RNO_3[10]\ : OA1A - port map(A => reload_6, B => readdata_1_sqmuxa_1_0, C => - \prdata_1_i_0_a11_1_0[10]\, Y => - \prdata_1_i_0_a11_1_1[10]\); - - \comb.v.prdata_1_i_0_RNO_0[28]\ : AND2 - port map(A => N_156_i, B => N_675, Y => - \prdata_1_i_0_3[28]\); - - \r.prdata_RNO_5[3]\ : NOR3C - port map(A => N_724, B => \prdata_1_0_0_1[3]\, C => - \prdata_1_0_0_3[3]\, Y => \prdata_1_0_0_5[3]\); - - \r.prdata_RNO_5[15]\ : AOI1B - port map(A => prdata_0_15, B => N_751, C => N_693, Y => - \prdata_1_0_0_4[15]\); - - \r.prdata_RNO_2[0]\ : AO1B - port map(A => un1_uart1(36), B => prdata(31), C => - \prdata_1_i_0_a11_9_3[0]\, Y => N_645_i); - - \r.prdata_RNO_9[8]\ : OA1A - port map(A => reload_4, B => readdata_1_sqmuxa_1_0, C => - value_m_4, Y => \prdata_1_i_0_a11_1_2[8]\); - - \r.prdata_RNO_9[6]\ : AOI1B - port map(A => N_240_0, B => N_214, C => N_758, Y => - \prdata_1_i_0_a11_4_0[6]\); - - \r.prdata[1]\ : DFN1 - port map(D => \prdata_1[1]\, CLK => lclk_c, Q => hrdata(1)); - - \r.haddr[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[2]\); - - \r.prdata_RNO[16]\ : AO1B - port map(A => prdata_0_16, B => N_758, C => - \prdata_1_0_0_4[16]\, Y => \prdata_1[16]\); - - \r.haddr[3]\ : DFN1E1 - port map(D => haddr(3), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[3]\); - - \r.prdata_RNO_4[11]\ : OA1A - port map(A => N_751_0, B => prdata(11), C => - \prdata_RNO_8[11]\, Y => \prdata_1_i_0_4[11]\); - - \comb.v.prdata_1_i_0_a2_1_RNO[28]\ : XA1C - port map(A => \paddr[10]\, B => \paddr[11]\, C => N_82, Y - => N_111); - - \r.prdata_RNO_0[26]\ : AO1B - port map(A => readdata_1_iv_0_13, B => value_m_22, C => - N_758, Y => N_517); - - \r.prdata_RNO_7[11]\ : AOI1B - port map(A => N_240, B => N_219, C => N_761, Y => - \prdata_1_i_0_a11_2_0[11]\); - - \r.cfgsel_RNIR01K\ : AOI1B - port map(A => \paddr[2]\, B => N_176, C => cfgsel, Y => - N_554_i); - - \r.prdata_RNO_7[5]\ : OA1A - port map(A => reload_1, B => readdata_1_sqmuxa_1_0, C => - value_m_1, Y => \prdata_1_i_0_a11_4_2[5]\); - - \r.prdata_RNO[25]\ : AO1B - port map(A => prdata_0_25, B => N_758, C => - \prdata_1_0_0_2[25]\, Y => \prdata_1[25]\); - - \r.pwdata_1[4]\ : DFN1E0 - port map(D => hwdata(4), CLK => lclk_c, E => N_12_0_1, Q - => pwdata_1_3); - - \comb.v.prdata_1_i_0_a11_2[20]\ : NAND2 - port map(A => value_m_16, B => \prdata_1_i_0_a11_2_1[20]\, - Y => N_710); - - \r.prdata_RNO_13[0]\ : NOR3B - port map(A => \paddr[9]\, B => enable_m, C => N_747, Y => - \prdata_1_i_0_a11_3_1[0]\); - - \r.haddr_RNIPGOP1[8]\ : OR3C - port map(A => \prdata_1_i_0_o2_1_4[0]\, B => - \prdata_1_i_0_o2_1_5[0]\, C => N_788, Y => N_82); - - \r.prdata_RNO_11[3]\ : OA1A - port map(A => N_777, B => N_770, C => N_722, Y => - \prdata_1_0_0_0[3]\); - - \r.prdata[14]\ : DFN1 - port map(D => \prdata_1[14]\, CLK => lclk_c, Q => - hrdata(14)); - - \r.haddr_RNIBMI7[4]\ : OR3B - port map(A => N_766, B => \paddr[4]\, C => N_760, Y => - N_722); - - \r.prdata_RNO_1[22]\ : AOI1B - port map(A => prdata(22), B => N_751_0, C => N_532, Y => - \prdata_1_i_i_3[22]\); - - \r.prdata_RNO_2[5]\ : NOR3C - port map(A => rdata_2_m(5), B => rdata_17_m_5, C => - \prdata_1_i_0_a11_8_0[5]\, Y => \prdata_1_i_0_a11_8_2[5]\); - - \r.prdata_RNO_9[13]\ : OR2A - port map(A => N_84, B => N_793, Y => \prdata_RNO_9[13]\); - - \r.prdata_RNO_10[1]\ : OR3B - port map(A => N_5063, B => N_767, C => \paddr_0[3]\, Y => - N_624); - - \r.prdata_RNO_25[6]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_6, C => N_756, Y - => \prdata_1_i_0_a11_8_0[6]\); - - \r.cfgsel_RNINRQH\ : NOR2A - port map(A => cfgsel, B => N_176, Y => N_544); - - \r.pwdata_0[15]\ : DFN1E0 - port map(D => hwdata(15), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(15)); - - \r.hwrite\ : DFN1 - port map(D => N_17, CLK => lclk_c, Q => \pwrite\); - - \r.prdata[22]\ : DFN1 - port map(D => N_30, CLK => lclk_c, Q => hrdata(22)); - - \r.prdata[8]\ : DFN1 - port map(D => N_102_i_0, CLK => lclk_c, Q => hrdata(8)); - - \r.pwdata[27]\ : DFN1E0 - port map(D => hwdata(27), CLK => lclk_c, E => N_12, Q => - pwdata(27)); - - \r.prdata_RNO_11[4]\ : NOR2B - port map(A => N_756, B => brate_m_0, Y => - \prdata_1_i_0_a11_7_0[4]\); - - \r.prdata_RNO_6[9]\ : AOI1B - port map(A => N_240_0, B => N_217, C => N_761, Y => - \prdata_1_i_0_a11_1_0[9]\); - - \r.prdata_RNO_8[15]\ : AOI1B - port map(A => \prdata_1_0_0_a11_1_0[15]\, B => N_766, C => - N_685, Y => \prdata_1_0_0_0[15]\); - - \r.prdata_RNO_3[24]\ : OR2B - port map(A => prdata_2_24, B => N_752_0, Y => N_525); - - \r.prdata_RNO_18[0]\ : OR2A - port map(A => N_752, B => prdata_1_0, Y => - \prdata_RNO_18[0]\); - - \r.prdata_RNO_14[6]\ : AO1 - port map(A => rdata60_1, B => N_333, C => N_763, Y => - \prdata_RNO_14[6]\); - - \r.prdata_RNO_8[7]\ : OR3C - port map(A => \prdata_1_i_0_a11_5_1[7]\, B => - \prdata_1_i_0_a11_5_0[7]\, C => N_762, Y => N_592_i); - - \comb.v.prdata_1_i_0_a11_1_RNO[28]\ : OA1A - port map(A => reload_24, B => readdata_1_sqmuxa_1_0, C => - \prdata_1_i_0_a11_1_0[28]\, Y => - \prdata_1_i_0_a11_1_1[28]\); - - \v.hready_0_sqmuxa_0_a3_0_a2_0\ : NOR2B - port map(A => iosn_0(93), B => htrans(1), Y => - hready_0_sqmuxa_0_a3_0_a2_0); - - \r.prdata_RNO_1[26]\ : NOR3C - port map(A => N_516, B => \prdata_1_0_0_0[26]\, C => - \prdata_1_0_0_2[26]\, Y => \prdata_1_0_0_3[26]\); - - \r.prdata_RNO_10[15]\ : NOR3B - port map(A => cfgsel, B => \paddr_0[3]\, C => \paddr_0[4]\, - Y => \prdata_1_0_0_a11_1_0[15]\); - - \r.prdata[0]\ : DFN1 - port map(D => N_58_i_0, CLK => lclk_c, Q => hrdata(0)); - - \r.prdata_RNO_4[24]\ : OR3A - port map(A => un1_apbi_7_1, B => N_760, C => N_84, Y => - N_521); - - \r.prdata_RNO_1[4]\ : OR3C - port map(A => parsel_m_0, B => \prdata_1_i_0_a11_7_2[4]\, C - => ovf_m, Y => N_623_i); - - \comb.v.prdata_1_i_0_a11_1_RNO_0[28]\ : AOI1B - port map(A => N_240_0, B => N_236, C => N_761, Y => - \prdata_1_i_0_a11_1_0[28]\); - - \r.haddr_0[4]\ : DFN1E1 - port map(D => haddr(4), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr_0[4]\); - - \comb.v.prdata_1_i_0_a11_1[27]\ : NAND2 - port map(A => value_m_23, B => \prdata_1_i_0_a11_1_1[27]\, - Y => N_681); - - \r.pwdata[12]\ : DFN1E0 - port map(D => hwdata(12), CLK => lclk_c, E => N_12_0, Q => - pwdata(12)); - - \r.prdata[31]\ : DFN1 - port map(D => \prdata_1[31]\, CLK => lclk_c, Q => - hrdata(31)); - - \r.prdata_RNO_2[20]\ : AO1C - port map(A => N_156, B => tcnt(0), C => N_756, Y => - \prdata_RNO_2[20]\); - - \r.prdata_RNO_1[10]\ : NOR3B - port map(A => N_567_i, B => \prdata_1_i_0_2[10]\, C => - N_771, Y => \prdata_1_i_0_5[10]\); - - \comb.v.prdata_1_i_0_a11_3[4]\ : NAND2 - port map(A => reload_m_4, B => \prdata_1_i_0_a11_3_4[4]\, Y - => N_619_i); - - \r.psel\ : DFN1 - port map(D => N_34, CLK => lclk_c, Q => psel); - - \r.prdata_RNO_11[0]\ : NOR3C - port map(A => N_6428, B => N_6430, C => N_6429, Y => - \prdata_1_i_0_a11_6_1[0]\); - - \r.prdata_RNO_0[25]\ : NOR3C - port map(A => N_669, B => N_668, C => \prdata_1_0_0_1[25]\, - Y => \prdata_1_0_0_2[25]\); - - \r.prdata_RNO_12[3]\ : OR3B - port map(A => N_5065, B => N_767, C => \paddr_0[3]\, Y => - N_721); - - \r.prdata_RNO_6[7]\ : NOR3C - port map(A => \prdata_1_i_0_a11_3_0[7]\, B => scaler_m_7, C - => \prdata_1_i_0_a11_3_1[7]\, Y => - \prdata_1_i_0_a11_3_3[7]\); - - \r.haddr[12]\ : DFN1E1 - port map(D => haddr(12), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[12]\); - - \r.pwdata[6]\ : DFN1E0 - port map(D => hwdata(6), CLK => lclk_c, E => N_12, Q => - pwdata(6)); - - \r.prdata_RNO_7[20]\ : OR3B - port map(A => cfgsel, B => N_84, C => \paddr[4]\, Y => - N_708); - - \r.pwdata_0[9]\ : DFN1E0 - port map(D => hwdata(9), CLK => lclk_c, E => N_12_0_1, Q - => pwdata_0(9)); - - \r.prdata_RNO_5[6]\ : NOR3C - port map(A => \prdata_RNO_12[6]\, B => \prdata_1_i_0_0[6]\, - C => \prdata_RNO_14[6]\, Y => \prdata_1_i_0_2[6]\); - - \r.pwdata[0]\ : DFN1E0 - port map(D => hwdata(0), CLK => lclk_c, E => N_12_0, Q => - pwdata(0)); - - \r.prdata_RNO_12[1]\ : OR2B - port map(A => prdata_0_1, B => N_755, Y => N_627); - - \r.haddr_RNI3SB72_1[11]\ : NOR2 - port map(A => \N_750\, B => N_747, Y => N_756); - - \r.pwdata_0_RNI13B[6]\ : INV - port map(A => \pwdata_0[6]\, Y => pwdata_i(6)); - - \r.prdata_RNO_6[23]\ : OR2B - port map(A => prdata_0_23, B => N_755, Y => N_696); - - \r.pwdata[23]\ : DFN1E0 - port map(D => hwdata(23), CLK => lclk_c, E => N_12_0_0, Q - => pwdata(23)); - - \r.prdata_RNO_12[8]\ : NOR3C - port map(A => N_468, B => N_467, C => - \prdata_1_i_0_a11_4_1[8]\, Y => \prdata_1_i_0_a11_4_2[8]\); - - \r.pwdata_0[8]\ : DFN1E0 - port map(D => hwdata(8), CLK => lclk_c, E => N_12_0_1, Q - => pwdata_0(8)); - - \r.prdata_RNO_9[26]\ : OR2B - port map(A => prdata_2_26, B => N_752_0, Y => N_519); - - \r.haddr_RNIBAC4[3]\ : NOR2B - port map(A => \paddr[4]\, B => \paddr[3]\, Y => N_90); - - \r.prdata_RNO_20[6]\ : MX2 - port map(A => romwws(2), B => rmw, S => \paddr_2[2]\, Y => - N_455); - - \r.prdata_RNO_23[6]\ : OR2A - port map(A => N_752_0, B => prdata_1_6, Y => - \prdata_RNO_23[6]\); - - \r.prdata_RNO_16[6]\ : OA1A - port map(A => N_751_0, B => prdata(6), C => - \prdata_RNO_23[6]\, Y => \prdata_1_i_0_4[6]\); - - \r.cfgsel_RNI7OLL1\ : OR3B - port map(A => \prdata_1_i_0_o2_1_4[0]\, B => - \prdata_1_i_0_o2_1_5[0]\, C => cfgsel, Y => N_743); - - \r.prdata_RNO_3[21]\ : OR2A - port map(A => N_751, B => prdata_2_21, Y => - \prdata_RNO_3[21]\); - - \comb.v.prdata_1_i_0_a11_1_RNO_0[27]\ : AND2 - port map(A => readdata_9_27, B => N_761, Y => - \prdata_1_i_0_a11_1_0[27]\); - - \r.prdata_RNO_13[9]\ : NOR2B - port map(A => N_473, B => N_474, Y => - \prdata_1_i_0_a11_4_1[9]\); - - \r.prdata_RNO_6[6]\ : AOI1B - port map(A => \prdata_1_i_0_a11_3_1[6]\, B => N_771, C => - \prdata_1_i_0_4[6]\, Y => \prdata_1_i_0_6[6]\); - - \r.pwdata[8]\ : DFN1E0 - port map(D => hwdata(8), CLK => lclk_c, E => N_12, Q => - pwdata(8)); - - \r.prdata_RNO_1[8]\ : NOR3C - port map(A => \prdata_RNO_5[8]\, B => \prdata_1_i_0_1[8]\, - C => \prdata_1_i_0_3[8]\, Y => \prdata_1_i_0_5[8]\); - - \r.prdata_RNO_5[13]\ : NOR3C - port map(A => N_536, B => \prdata_1_0_0_1[13]\, C => - \prdata_1_0_0_3[13]\, Y => \prdata_1_0_0_5[13]\); - - \r.prdata_RNO_4[21]\ : NOR3C - port map(A => \prdata_1_i_0_a11[21]\, B => - \prdata_1_i_0_1[21]\, C => \prdata_RNO_7[21]\, Y => - \prdata_1_i_0_3[21]\); - - \r.haddr[10]\ : DFN1E1 - port map(D => haddr(10), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[10]\); - - \r.prdata_RNO_0[2]\ : AO1B - port map(A => readdata_iv_3(2), B => reload_m_2, C => N_758, - Y => N_736); - - \r.prdata[15]\ : DFN1 - port map(D => \prdata_1[15]\, CLK => lclk_c, Q => - hrdata(15)); - - \r.state[1]\ : DFN1 - port map(D => \state_nss[1]\, CLK => lclk_c, Q => - \state[1]\); - - \r.prdata_RNO_3[2]\ : AO1B - port map(A => prdata_iv_0_0(2), B => N_6432, C => N_771, Y - => N_735); - - \r.haddr[8]\ : DFN1E1 - port map(D => haddr(8), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[8]\); - - \comb.v.prdata_1_i_0_a11_3_RNO[4]\ : AND2 - port map(A => \prdata_1_i_0_a11_3_3[4]\, B => - \prdata_1_i_0_a11_3_2[4]\, Y => \prdata_1_i_0_a11_3_4[4]\); - - \r.state_RNI4KU3_2[0]\ : OR2B - port map(A => \pwrite\, B => \state[0]\, Y => N_12_0); - - \r.cfgsel_RNIM601_0\ : NOR2B - port map(A => \paddr_0[2]\, B => cfgsel, Y => N_774); - - \r.haddr[9]\ : DFN1E1 - port map(D => haddr(9), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[9]\); - - \r.prdata_RNO_1[25]\ : OR2B - port map(A => prdata_2_25, B => N_755, Y => N_669); - - \r.cfgsel_RNI1HC5\ : NOR2B - port map(A => N_774, B => N_90, Y => N_781); - - \r.prdata_RNO_9[14]\ : OR2 - port map(A => readdata51_1, B => N_793, Y => - \prdata_RNO_9[14]\); - - \r.prdata_RNO_13[1]\ : NOR3C - port map(A => N_758, B => \prdata_1_0_0_a11_5_1[1]\, C => - scaler_i_m(1), Y => \prdata_1_0_0_a11_5_3[1]\); - - \r.haddr_RNIFPAD[14]\ : NOR2B - port map(A => \paddr[14]\, B => \paddr[15]\, Y => - penable_1_0_0_i_0_a11_0_1); - - \r.prdata_RNO_14[3]\ : MX2 - port map(A => romrws(3), B => ramwws(1), S => \paddr[2]\, Y - => N_5065); - - \r.prdata_RNO_5[9]\ : OA1A - port map(A => N_751_0, B => prdata(9), C => - \prdata_RNO_12[9]\, Y => \prdata_1_i_0_4[9]\); - - \r.prdata_RNO_1[9]\ : OR3C - port map(A => reload_m_9, B => \prdata_1_i_0_a11_1_0[9]\, C - => \prdata_1_i_0_a11_1_2[9]\, Y => N_572_i); - - \r.prdata_RNO_18[5]\ : AOI1B - port map(A => iforce_0_0, B => N_898, C => N_365, Y => - \prdata_1_i_0_a11_6_0[5]\); - - \r.haddr_RNI991B[11]\ : NOR2A - port map(A => \paddr[11]\, B => \N_78\, Y => N_772); - - \r.state_RNO[1]\ : NOR3B - port map(A => \state[0]\, B => rstn, C => \state[1]\, Y => - \state_nss[1]\); - - \r.pwdata[3]\ : DFN1E0 - port map(D => hwdata(3), CLK => lclk_c, E => N_12, Q => - pwdata(3)); - - \comb.v.prdata_1_i_0_o11[28]\ : NOR2B - port map(A => N_786, B => N_101, Y => N_156_i); - - \r.prdata_RNO_8[9]\ : AO1B - port map(A => rdata_3_sqmuxa, B => brate_9, C => N_756, Y - => \prdata_1_i_0_a11_6_0[9]\); - - \r.prdata_RNO_9[9]\ : NOR3C - port map(A => N_472, B => N_471, C => - \prdata_1_i_0_a11_4_1[9]\, Y => \prdata_1_i_0_a11_4_2[9]\); - - \r.pwdata[29]\ : DFN1E0 - port map(D => hwdata(29), CLK => lclk_c, E => N_12, Q => - pwdata(29)); - - \r.prdata_RNO_3[31]\ : OR2B - port map(A => prdata_4(31), B => N_755, Y => N_507); - - \r.haddr_RNIS3MH_1[10]\ : AXOI5 - port map(A => \N_78\, B => \paddr[10]\, C => \paddr[11]\, Y - => \prdata_1_i_0_o2_1_0[12]\); - - \r.prdata_RNO_14[1]\ : OR2B - port map(A => rdata59_4, B => dout_0, Y => \dout_m[1]\); - - \r.prdata_RNO_21[6]\ : AO1A - port map(A => \paddr[6]\, B => \paddr_0[4]\, C => N_760, Y - => N_595); - - \r.haddr_RNILAC4[8]\ : OR2B - port map(A => \paddr[9]\, B => \paddr[8]\, Y => \N_78\); - - \r.prdata_RNO[23]\ : AO1B - port map(A => prdata(23), B => N_758, C => - \prdata_1_i_i_4[23]\, Y => N_60); - - \r.hwrite_RNO_0\ : MX2 - port map(A => \pwrite\, B => hwrite, S => hready_0_sqmuxa_0, - Y => N_5913); - - GND_i : GND - port map(Y => \GND\); - - \r.prdata_RNO_11[7]\ : AOI1B - port map(A => rdata59_4, B => dout_6, C => - \prdata_1_i_0_a11_2_0[7]\, Y => \prdata_1_i_0_a11_2_1[7]\); - - \r.prdata_RNO_15[10]\ : AO1A - port map(A => N_6455_0, B => rambanksz_1, C => N_778_i, Y - => \prdata_RNO_15[10]\); - - \r.prdata[28]\ : DFN1 - port map(D => N_50_i_0, CLK => lclk_c, Q => hrdata(28)); - - \r.prdata_RNO_5[8]\ : AO1 - port map(A => rdata60_1, B => N_335, C => N_763, Y => - \prdata_RNO_5[8]\); - - \r.prdata_RNO_5[22]\ : OR3B - port map(A => iows(2), B => N_767, C => N_232_0, Y => N_527); - - \r.prdata_RNO_15[12]\ : AO1C - port map(A => \paddr[6]\, B => \paddr_0[4]\, C => N_776, Y - => N_543); - - \r.pwdata_0[1]\ : DFN1E0 - port map(D => hwdata(1), CLK => lclk_c, E => N_12_0_0, Q - => \pwdata_0[1]\); - - \r.prdata_RNO_4[8]\ : OR3C - port map(A => readdata57, B => \prdata_1_i_0_a11_1_0[8]\, C - => \prdata_1_i_0_a11_1_2[8]\, Y => N_580_i); - - \r.state_RNO[0]\ : NOR3C - port map(A => N_795, B => hready_0_sqmuxa_0, C => rstn, Y - => \state_nss[0]\); - - \r.pwdata_0[14]\ : DFN1E0 - port map(D => hwdata(14), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(14)); - - \r.pwdata_0[5]\ : DFN1E0 - port map(D => hwdata(5), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[5]\); - - \r.prdata_RNO_1[30]\ : OR2B - port map(A => prdata_2_30, B => N_751, Y => N_662); - - \comb.v.prdata_1_i_0_RNO_1[28]\ : OA1A - port map(A => N_752_0, B => prdata_1_28, C => - \prdata_1_i_0_1[28]\, Y => \prdata_1_i_0_2[28]\); - - \r.prdata_RNO_8[26]\ : OR2A - port map(A => \un1_apbi_7_3\, B => N_760, Y => N_515); - - \r.haddr[18]\ : DFN1E1 - port map(D => haddr(18), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[18]\); - - \r.prdata_RNO_8[13]\ : AOI1B - port map(A => prdata(13), B => N_751_0, C => N_541, Y => - \prdata_1_0_0_3[13]\); - - \r.prdata_RNO_7[6]\ : AND2 - port map(A => flow_m, B => \prdata_1_i_0_a11_8_2[6]\, Y => - \prdata_1_i_0_a11_8_3[6]\); - - \r.prdata_RNO_0[12]\ : AOI1B - port map(A => \prdata_1_i_0_a11_3_1[12]\, B => value_m_8, C - => \prdata_1_i_0_5[12]\, Y => \prdata_1_i_0_7[12]\); - - \r.prdata_RNO_16[7]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_7, C => N_756, Y - => \prdata_1_i_0_a11_7_0[7]\); - - \r.prdata_RNO_9[11]\ : NOR2B - port map(A => N_841, B => N_842, Y => - \prdata_1_i_0_a11_5_1[11]\); - - \r.prdata_RNO_2[12]\ : AO1B - port map(A => breakirqen, B => prdata(31), C => N_756, Y - => \prdata_RNO_2[12]\); - - \r.pwdata[18]\ : DFN1E0 - port map(D => hwdata(18), CLK => lclk_c, E => N_12_0, Q => - pwdata(18)); - - \r.haddr_RNIBAC4_0[3]\ : NOR2A - port map(A => \paddr[4]\, B => \paddr[3]\, Y => N_791); - - \r.prdata_RNO_6[10]\ : NOR3B - port map(A => \prdata_1_i_0_0[10]\, B => - \prdata_RNO_13[10]\, C => N_554_i, Y => - \prdata_1_i_0_2[10]\); - - \r.haddr[16]\ : DFN1E1 - port map(D => haddr(16), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[16]\); - - \r.prdata_RNO_8[6]\ : OA1A - port map(A => reload_2, B => readdata_1_sqmuxa_1_0, C => - readdata57, Y => \prdata_1_i_0_a11_4_1[6]\); - - \r.haddr[19]\ : DFN1E1 - port map(D => haddr(19), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[19]\); - - \r.prdata_RNO_10[13]\ : AO1C - port map(A => \paddr_0[2]\, B => un1_apbi_7_1, C => - \prdata_1_0_0_a11_0[13]\, Y => N_534); - - \r.prdata_RNO_12[11]\ : AO1 - port map(A => un1_dcom0(13), B => N_127, C => N_763, Y => - \prdata_RNO_12[11]\); - - \r.prdata_RNO_9[5]\ : NOR3C - port map(A => \prdata_RNO_12[5]\, B => \prdata_1_i_0_0[5]\, - C => \prdata_RNO_14[5]\, Y => \prdata_1_i_0_2[5]\); - - \r.prdata_RNO_5[26]\ : AOI1B - port map(A => prdata(26), B => N_751_0, C => N_519, Y => - \prdata_1_0_0_2[26]\); - - \r.penable_RNO_1\ : NOR2A - port map(A => \state[1]\, B => \penable\, Y => N_131); - - \r.haddr_RNI3SB72[8]\ : NOR2 - port map(A => \N_749\, B => N_745, Y => N_751); - - \r.prdata_RNO_0[29]\ : NOR3C - port map(A => N_658, B => N_656, C => N_659, Y => - \prdata_1_0_0_1[29]\); - - \r.haddr_RNIQIAS1[10]\ : NOR2A - port map(A => \paddr[10]\, B => N_743, Y => N_744); - - \r.state_RNO_0[0]\ : NOR2 - port map(A => \state[1]\, B => \state[0]\, Y => N_795); - - \r.prdata_RNO_0[23]\ : NOR3C - port map(A => N_699, B => N_698, C => \prdata_1_i_i_2[23]\, - Y => \prdata_1_i_i_4[23]\); - - \r.prdata[4]\ : DFN1 - port map(D => N_61_i_0, CLK => lclk_c, Q => hrdata(4)); - - \r.cfgsel_RNIISL4\ : OR2A - port map(A => cfgsel, B => N_770, Y => - \prdata_1_0_0_0_a2_0[14]\); - - \r.pwdata_0_RNIVQA[4]\ : INV - port map(A => \pwdata_0[4]\, Y => pwdata_i(4)); - - \r.prdata_RNO_3[4]\ : NOR3B - port map(A => \prdata_RNO_7[4]\, B => \prdata_RNO_8[4]\, C - => N_554_i, Y => \prdata_1_i_0_1[4]\); - - \r.psel_RNO_1\ : MX2A - port map(A => \state[0]\, B => \penable\, S => \state[1]\, - Y => N_168); - - \r.prdata_RNO_0[27]\ : AND2 - port map(A => N_156_i, B => N_681, Y => - \prdata_1_i_0_3[27]\); - - \r.pwdata[26]\ : DFN1E0 - port map(D => hwdata(26), CLK => lclk_c, E => N_12_0_1, Q - => pwdata(26)); - - \r.prdata_RNO_0[16]\ : NOR3C - port map(A => \prdata_1_0_0_1[16]\, B => N_717, C => - \prdata_1_0_0_2[16]\, Y => \prdata_1_0_0_4[16]\); - - \r.prdata_RNO_12[4]\ : OA1 - port map(A => \prdata_RNO_16[4]\, B => readdata55_3, C => - ipend_m(4), Y => \prdata_1_i_0_a11_5_1[4]\); - - \r.prdata_RNO[21]\ : NOR3C - port map(A => \prdata_1_i_0_6[21]\, B => - \prdata_1_i_0_5[21]\, C => \prdata_RNO_2[21]\, Y => - N_41_i_0); - - \r.prdata_RNO_5[14]\ : NOR3C - port map(A => N_204, B => \prdata_1_0_0_0_1[14]\, C => - \prdata_1_0_0_0_3[14]\, Y => \prdata_1_0_0_0_5[14]\); - - \r.haddr_RNIEHV22_0[11]\ : OR2A - port map(A => N_746, B => \paddr[11]\, Y => N_747); - - \r.haddr_RNI3SB72_0[11]\ : NOR2B - port map(A => \paddr[11]\, B => N_761, Y => N_771); - - \r.prdata_RNO_2[16]\ : OR3B - port map(A => N_127, B => un1_dcom0(18), C => N_763, Y => - N_717); - - \r.prdata_RNO_4[10]\ : OA1A - port map(A => N_751_0, B => prdata(10), C => - \prdata_RNO_9[10]\, Y => \prdata_1_i_0_4[10]\); - - \r.prdata[21]\ : DFN1 - port map(D => N_41_i_0, CLK => lclk_c, Q => hrdata(21)); - - \r.prdata_RNO_3[12]\ : OA1A - port map(A => reload_8, B => readdata_1_sqmuxa_1_0, C => - \prdata_1_i_0_a11_3_0[12]\, Y => - \prdata_1_i_0_a11_3_1[12]\); - - \r.prdata_RNO_1[3]\ : NOR3C - port map(A => N_726, B => \prdata_1_0_0_4[3]\, C => - \prdata_1_0_0_5[3]\, Y => \prdata_1_0_0_7[3]\); - - \r.prdata_RNO_7[10]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_10, C => N_756, Y - => \prdata_1_i_0_a11_6_0[10]\); - - \r.prdata_RNO[4]\ : NOR3C - port map(A => \prdata_1_i_0_6[4]\, B => N_619_i, C => - N_623_i, Y => N_61_i_0); - - \r.pwdata[7]\ : DFN1E0 - port map(D => hwdata(7), CLK => lclk_c, E => N_12, Q => - pwdata(7)); - - \r.prdata_RNO[22]\ : AO1B - port map(A => prdata_0_22, B => N_756, C => - \prdata_1_i_i_5[22]\, Y => N_30); - - \r.haddr_RNIFTM02[10]\ : NOR2A - port map(A => N_746, B => \N_78\, Y => N_761); - - \r.prdata_RNO_3[6]\ : NOR3C - port map(A => \prdata_1_i_0_a11_4_1[6]\, B => - \prdata_1_i_0_a11_4_0[6]\, C => \prdata_1_i_0_a11_4_2[6]\, - Y => \prdata_1_i_0_a11_4_4[6]\); - - \r.prdata_RNO_17[5]\ : AOI1B - port map(A => ilevel_1, B => prdata_0_sqmuxa, C => N_367, Y - => \prdata_1_i_0_a11_6_1[5]\); - - \r.haddr_RNIPNNE2_0[10]\ : OR3B - port map(A => \N_116\, B => \N_769\, C => \N_78\, Y => - psel_15); - - \r.prdata_RNO_4[9]\ : NOR3B - port map(A => \prdata_1_i_0_0[9]\, B => \prdata_RNO_11[9]\, - C => N_554_i, Y => \prdata_1_i_0_2[9]\); - - \r.prdata_RNO_16[4]\ : MX2C - port map(A => prdata_13_m_1_0(4), B => prdata_11_m_1_0(4), - S => \paddr[6]\, Y => \prdata_RNO_16[4]\); - - \r.prdata_RNO_3[1]\ : AOI1B - port map(A => prdata(1), B => N_751_0, C => N_633, Y => - \prdata_1_0_0_3[1]\); - - \r.prdata_RNO_0[4]\ : NOR3C - port map(A => \prdata_1_i_0_2[4]\, B => \prdata_1_i_0_1[4]\, - C => \prdata_1_i_0_5[4]\, Y => \prdata_1_i_0_6[4]\); - - \r.prdata_RNO_7[9]\ : OA1A - port map(A => dishlt, B => readdata57, C => value_m_5, Y - => \prdata_1_i_0_a11_1_2[9]\); - - \r.pwdata[20]\ : DFN1E0 - port map(D => hwdata(20), CLK => lclk_c, E => N_12_0_0, Q - => pwdata(20)); - - \r.pwdata[9]\ : DFN1E0 - port map(D => hwdata(9), CLK => lclk_c, E => N_12, Q => - pwdata(9)); - - \r.prdata_RNO_6[21]\ : OA1A - port map(A => N_84, B => N_789, C => \prdata_1_i_0_0[21]\, - Y => \prdata_1_i_0_1[21]\); - - \r.prdata_RNO_9[0]\ : NOR3C - port map(A => \prdata_1_i_0_0[0]\, B => \prdata_1_i_0_1[0]\, - C => N_139, Y => \prdata_1_i_0_2[0]\); - - \r.prdata_RNO_0[31]\ : AOI1B - port map(A => prdata_0_31, B => N_758, C => - \prdata_1_0_0_0_1[31]\, Y => \prdata_1_0_0_0_2[31]\); - - \r.prdata_RNO[20]\ : NOR3C - port map(A => \prdata_1_i_0_6[20]\, B => - \prdata_1_i_0_5[20]\, C => \prdata_RNO_2[20]\, Y => - N_39_i_0); - - \r.prdata_RNO_5[4]\ : NOR3C - port map(A => rdata_2_m(4), B => rdata_17_m_4, C => - \prdata_1_i_0_a11_7_0[4]\, Y => \prdata_1_i_0_a11_7_2[4]\); - - \r.pwdata[4]\ : DFN1E0 - port map(D => hwdata(4), CLK => lclk_c, E => N_12, Q => - pwdata(4)); - - \r.prdata_RNO_22[6]\ : NOR2B - port map(A => N_6439, B => N_6437, Y => - \prdata_1_i_0_a11_3_0[6]\); - - \r.pwdata[11]\ : DFN1E0 - port map(D => hwdata(11), CLK => lclk_c, E => N_12_0, Q => - pwdata(11)); - - \r.prdata_RNO_1[29]\ : OR2B - port map(A => prdata_2_29, B => N_751, Y => N_658); - - \r.prdata[12]\ : DFN1 - port map(D => N_110_i_0, CLK => lclk_c, Q => hrdata(12)); - - \r.pwdata_0[0]\ : DFN1E0 - port map(D => hwdata(0), CLK => lclk_c, E => N_12_0_0, Q - => \pwdata_0[0]\); - - \comb.v.prdata_1_i_0_a11_2_RNO[20]\ : AND2 - port map(A => reload_m_20, B => \prdata_1_i_0_a11_2_0[20]\, - Y => \prdata_1_i_0_a11_2_1[20]\); - - \r.prdata_RNO_2[8]\ : OR2A - port map(A => N_752_0, B => prdata_1_8, Y => - \prdata_RNO_2[8]\); - - \r.haddr_RNINPBD[18]\ : NOR2B - port map(A => \paddr[18]\, B => \paddr[19]\, Y => - penable_1_0_0_i_0_a11_0_3); - - \r.prdata_RNO_4[31]\ : OR2B - port map(A => prdata_2_31, B => N_752, Y => N_510); - - \r.prdata_RNO_1[23]\ : OR2B - port map(A => prdata_2_23, B => N_752, Y => N_699); - - \r.prdata_RNO_11[11]\ : NOR2B - port map(A => \prdata_RNO_13[11]\, B => \prdata_RNO_14[11]\, - Y => \prdata_1_i_0_0[11]\); - - \r.prdata_RNO_3[16]\ : AOI1B - port map(A => prdata(16), B => N_751, C => N_720, Y => - \prdata_1_0_0_2[16]\); - - \r.prdata_RNO_8[8]\ : AOI1B - port map(A => N_240_0, B => N_216, C => N_761, Y => - \prdata_1_i_0_a11_1_0[8]\); - - \r.prdata_RNO_3[9]\ : AOI1 - port map(A => \prdata_1_i_0_a11_4_2[9]\, B => N_762, C => - N_771, Y => \prdata_1_i_0_3[9]\); - - \r.prdata_RNO_2[3]\ : AO1B - port map(A => rdata_iv_2(3), B => break_m, C => N_756, Y - => N_731); - - \r.prdata_RNO_14[0]\ : AOI1B - port map(A => rdata_2(0), B => rdata_0_sqmuxa, C => - rdata_17_m_0_d0, Y => \prdata_1_i_0_a11_9_1[0]\); - - \r.haddr[15]\ : DFN1E1 - port map(D => haddr(15), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[15]\); - - \r.prdata_RNO_13[4]\ : AOI1B - port map(A => ilevel_0, B => prdata_0_sqmuxa, C => - iforce_0_m(4), Y => \prdata_1_i_0_a11_5_0[4]\); - - \r.prdata_RNO_1[27]\ : OA1A - port map(A => N_752_0, B => prdata_0_27, C => - \prdata_1_i_0_1[27]\, Y => \prdata_1_i_0_2[27]\); - - \comb.v.prdata_1_i_0_a11[27]\ : OR2 - port map(A => N_782_i, B => prdata(27), Y => - \prdata_1_i_0_a11[27]\); - - \r.prdata_RNO_0[6]\ : AO1C - port map(A => readdata56, B => reload_0(6), C => - \prdata_1_i_0_a11_4_4[6]\, Y => N_600_i); - - \r.prdata_RNO_17[1]\ : OR3B - port map(A => N_766, B => N_791, C => N_760, Y => N_625); - - \r.prdata_RNO[18]\ : AO1B - port map(A => prdata(18), B => N_758, C => - \prdata_1_0_0_1[18]\, Y => \prdata_1[18]\); - - \r.haddr_RNIQ2LQ[12]\ : NOR3C - port map(A => \paddr[13]\, B => \paddr[12]\, C => - penable_1_0_0_i_0_a11_0_1, Y => penable_1_0_0_i_0_a11_0_4); - - \r.prdata_RNO_5[11]\ : OR3C - port map(A => \prdata_1_i_0_a11_5_1[11]\, B => - \prdata_1_i_0_a11_5_0[11]\, C => N_762, Y => N_559_i); - - \r.prdata_RNO_18[6]\ : AOI1B - port map(A => ilevel_2, B => prdata_0_sqmuxa, C => N_363, Y - => \prdata_1_i_0_a11_6_1[6]\); - - \r.haddr[14]\ : DFN1E1 - port map(D => haddr(14), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[14]\); - - \r.pwdata_0_RNIUMA[3]\ : INV - port map(A => \pwdata_0[3]\, Y => pwdata_i(3)); - - \r.haddr[6]\ : DFN1E1 - port map(D => haddr(6), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[6]\); - - \r.prdata_RNO_8[14]\ : AOI1B - port map(A => prdata_0_14, B => N_751_0, C => N_499, Y => - \prdata_1_0_0_0_3[14]\); - - \r.prdata_RNO_0[15]\ : NOR3C - port map(A => N_688, B => \prdata_1_0_0_2[15]\, C => - \prdata_1_0_0_4[15]\, Y => \prdata_1_0_0_6[15]\); - - \r.pwdata_0_RNI27B[7]\ : INV - port map(A => \pwdata_0[7]\, Y => pwdata_i(7)); - - \r.prdata_RNO_2[15]\ : AO1B - port map(A => readdata_1_iv_0_2, B => value_m_11, C => - N_758, Y => N_690); - - \r.haddr_RNILAC4_0[8]\ : OR2A - port map(A => \paddr[8]\, B => \paddr[9]\, Y => \N_750\); - - \r.prdata_RNO_3[8]\ : OR2A - port map(A => N_751, B => prdata_0_8, Y => - \prdata_RNO_3[8]\); - - \r.prdata_RNO[15]\ : OR3C - port map(A => \prdata_1_0_0_6[15]\, B => - \prdata_1_0_0_5[15]\, C => N_690, Y => \prdata_1[15]\); - - \r.prdata_RNO_11[8]\ : OR3A - port map(A => N_772, B => N_743, C => prdata(8), Y => - \prdata_RNO_11[8]\); - - \r.haddr_RNIQIAS1_0[10]\ : NOR2 - port map(A => \paddr[10]\, B => N_743, Y => N_746); - - \r.haddr_RNI46CL1[12]\ : NOR3C - port map(A => penable_1_0_0_i_0_a11_0_3, B => - penable_1_0_0_i_0_a11_0_2, C => penable_1_0_0_i_0_a11_0_4, - Y => cfgsel2); - - \r.pwdata_0_RNI0VA[5]\ : INV - port map(A => \pwdata_0[5]\, Y => pwdata_i(5)); - - \r.prdata_RNO_10[2]\ : OR3B - port map(A => N_6427, B => N_767, C => \paddr_0[3]\, Y => - N_732); - - \comb.v.prdata_1_i_0_a11_1[28]\ : NAND2 - port map(A => value_m_24, B => \prdata_1_i_0_a11_1_1[28]\, - Y => N_675); - - \r.hready_RNO\ : OR2A - port map(A => rstn, B => N_5860, Y => N_198); - - \comb.v.prdata_1_i_0_a11_6_RNO[8]\ : AND2 - port map(A => rhalffull_1_m, B => \prdata_1_i_0_a11_6_0[8]\, - Y => \prdata_1_i_0_a11_6_1[8]\); - - \comb.v.prdata_1_i_0_a11[20]\ : OR2 - port map(A => N_782_i, B => prdata(20), Y => - \prdata_1_i_0_a11[20]\); - - \r.prdata_RNO_0[24]\ : AOI1B - port map(A => prdata(24), B => N_751, C => N_525, Y => - \prdata_1_0_0_2[24]\); - - \r.state[0]\ : DFN1 - port map(D => \state_nss[0]\, CLK => lclk_c, Q => - \state[0]\); - - \r.pwdata_1[3]\ : DFN1E0 - port map(D => hwdata(3), CLK => lclk_c, E => N_12_0_1, Q - => pwdata_1_2); - - \r.prdata_RNO_5[5]\ : NOR2B - port map(A => N_756, B => brate_m_1, Y => - \prdata_1_i_0_a11_8_0[5]\); - - \r.prdata_RNO_6[8]\ : NOR3B - port map(A => \prdata_RNO_10[8]\, B => \prdata_RNO_11[8]\, - C => N_554_i, Y => \prdata_1_i_0_1[8]\); - - \r.prdata_RNO_2[1]\ : AO1B - port map(A => rdata_iv_0_2(1), B => N_227, C => N_756, Y - => N_634); - - \r.prdata_RNO_7[8]\ : AOI1 - port map(A => \prdata_1_i_0_a11_4_2[8]\, B => N_762, C => - N_771, Y => \prdata_1_i_0_3[8]\); - - \r.haddr_1[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => paddr_1(2)); - - \r.prdata_RNO_2[7]\ : OAI1 - port map(A => N_156, B => tcnt_i, C => - \prdata_1_i_0_a11_7_3[7]\, Y => N_594_i); - - \r.prdata_RNO_2[22]\ : NOR3C - port map(A => N_527, B => \prdata_1_i_i_0[22]\, C => N_529, - Y => \prdata_1_i_i_2[22]\); - - \r.prdata_RNO_1[12]\ : NOR3B - port map(A => N_550_i, B => \prdata_1_i_0_3[12]\, C => - N_771, Y => \prdata_1_i_0_6[12]\); - - \r.prdata[9]\ : DFN1 - port map(D => N_104_i_0, CLK => lclk_c, Q => hrdata(9)); - - \r.prdata_RNO_8[0]\ : NOR3C - port map(A => \prdata_1_i_0_a11_9_1[0]\, B => - \prdata_1_i_0_a11_9_0[0]\, C => rcnt_RNI8FBM3(1), Y => - \prdata_1_i_0_a11_9_3[0]\); - - \r.haddr_RNI3SB72_2[8]\ : NOR2 - port map(A => \N_750\, B => N_745, Y => N_752_0); - - \r.prdata_RNO_1[5]\ : AOI1B - port map(A => \prdata_1_i_0_a11_4_4[5]\, B => reload_m_5, C - => \prdata_1_i_0_7[5]\, Y => \prdata_1_i_0_8[5]\); - - \comb.v.prdata_1_i_0_RNO[28]\ : AND2 - port map(A => \prdata_1_i_0_3[28]\, B => - \prdata_1_i_0_2[28]\, Y => \prdata_1_i_0_4[28]\); - - \r.prdata_RNO_15[4]\ : OR2A - port map(A => N_752_0, B => prdata_1_4, Y => - \prdata_RNO_15[4]\); - - \r.prdata_RNO_10[5]\ : AOI1B - port map(A => \prdata_1_i_0_a11_3_1[5]\, B => N_771, C => - \prdata_1_i_0_4[5]\, Y => \prdata_1_i_0_6[5]\); - - \r.cfgsel_RNIO6OB2\ : OA1B - port map(A => N_82, B => N_748, C => cfgsel, Y => N_767); - - \r.prdata_RNO_7[22]\ : OR2B - port map(A => prdata_1_22, B => N_755, Y => N_529); - - \r.prdata_RNO_3[20]\ : OR2A - port map(A => N_751, B => prdata_1_20, Y => - \prdata_RNO_3[20]\); - - \r.prdata_RNO_3[15]\ : OR2B - port map(A => prdata_2_15, B => N_755, Y => N_688); - - \r.prdata_RNO_13[10]\ : AO1 - port map(A => un1_dcom0(12), B => N_127, C => N_763, Y => - \prdata_RNO_13[10]\); - - \r.prdata_RNO_6[3]\ : OR2B - port map(A => rdata59_4, B => dout_2, Y => \dout_m[3]\); - - \r.prdata_RNO_9[1]\ : OR2B - port map(A => prdata_2_1, B => N_752, Y => N_633); - - \r.haddr_RNIFPAD_0[14]\ : NOR2 - port map(A => \paddr[14]\, B => \paddr[15]\, Y => - \prdata_1_i_0_o2_1_1[0]\); - - \r.pwdata[1]\ : DFN1E0 - port map(D => hwdata(1), CLK => lclk_c, E => N_12_0, Q => - pwdata(1)); - - \r.pwdata[24]\ : DFN1E0 - port map(D => hwdata(24), CLK => lclk_c, E => N_12_0_1, Q - => pwdata(24)); - - \v.hready_0_sqmuxa_0_a3_0_a2_0_0\ : NOR2A - port map(A => hready_0_sqmuxa_0_a3_0_a2_0, B => - un51_ioen_NE, Y => hready_0_sqmuxa_0); - - \r.prdata_RNO_4[20]\ : NOR3C - port map(A => \prdata_1_i_0_a11[20]\, B => - \prdata_1_i_0_1[20]\, C => \prdata_RNO_6[20]\, Y => - \prdata_1_i_0_3[20]\); - - \r.prdata_RNO_13[12]\ : AO1 - port map(A => un1_dcom0(14), B => N_127, C => N_763, Y => - \prdata_RNO_13[12]\); - - \r.prdata_RNO_8[11]\ : OR2A - port map(A => N_752_0, B => prdata_1_11, Y => - \prdata_RNO_8[11]\); - - \r.prdata_RNO_2[2]\ : AO1B - port map(A => rdata_iv_2(2), B => thempty_1_m, C => N_756, - Y => N_740); - - \r.cfgsel_RNIGRO9\ : OR2B - port map(A => N_794, B => N_774, Y => N_526); - - \r.prdata_RNO_24[6]\ : AOI1B - port map(A => rdata_17_m_0(6), B => rdata_4_sqmuxa, C => - rdata_2_m(6), Y => \prdata_1_i_0_a11_8_1[6]\); - - \r.prdata_RNO_2[26]\ : OR2A - port map(A => \prdata_1_0_0_a11_5_0[26]\, B => N_156, Y => - N_520); - - \r.prdata_RNO_1[16]\ : NOR3C - port map(A => N_715, B => N_714, C => N_716, Y => - \prdata_1_0_0_1[16]\); - - \r.prdata_RNO_0[1]\ : NOR3C - port map(A => \prdata_1_0_0_3[1]\, B => \prdata_1_0_0_2[1]\, - C => N_630_i, Y => \prdata_1_0_0_7[1]\); - - \r.prdata_RNO_16[5]\ : OA1A - port map(A => N_751_0, B => prdata(5), C => - \prdata_RNO_21[5]\, Y => \prdata_1_i_0_4[5]\); - - \r.haddr_RNILAC4_2[8]\ : OR2 - port map(A => \paddr[9]\, B => \paddr[8]\, Y => N_788); - - \r.prdata_RNO_13[8]\ : AOI1B - port map(A => ilevel_4, B => prdata_0_sqmuxa, C => N_470, Y - => \prdata_1_i_0_a11_4_1[8]\); - - \r.prdata_RNO_7[26]\ : NOR2A - port map(A => brdyen, B => N_232_0, Y => - \prdata_1_0_0_a11_0[26]\); - - \r.prdata_RNO_2[31]\ : OR2B - port map(A => prdata_3_29, B => N_751, Y => N_509); - - \r.prdata_RNO[24]\ : OR3C - port map(A => \prdata_1_0_0_2[24]\, B => - \prdata_1_0_0_1[24]\, C => N_523, Y => \prdata_1[24]\); - - \r.prdata_RNO_1[24]\ : NOR3B - port map(A => N_521, B => N_522, C => N_777, Y => - \prdata_1_0_0_1[24]\); - - \r.pwdata[5]\ : DFN1E0 - port map(D => hwdata(5), CLK => lclk_c, E => N_12, Q => - pwdata(5)); - - \r.haddr_RNIPNNE2[8]\ : OR3B - port map(A => \N_769\, B => \N_773\, C => N_788, Y => - psel_0); - - \r.prdata_RNO_3[30]\ : OR2B - port map(A => prdata_3_28, B => N_752, Y => N_663); - - \r.haddr_RNIPNNE2[10]\ : OR2B - port map(A => \psel_0_a3_0_a2_0_a11_0[11]\, B => \N_769\, Y - => psel_11); - - \r.prdata_RNO_21[0]\ : XA1B - port map(A => \paddr[10]\, B => \paddr[11]\, C => - \paddr[9]\, Y => \prdata_1_i_0_a11_1_0[0]\); - - \r.pwdata_0[3]\ : DFN1E0 - port map(D => hwdata(3), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[3]\); - - \r.prdata_RNO_0[21]\ : NOR3C - port map(A => \prdata_RNO_3[21]\, B => \prdata_1_i_0_3[21]\, - C => N_703, Y => \prdata_1_i_0_6[21]\); - - \r.prdata_RNO_3[5]\ : NOR3C - port map(A => \prdata_1_i_0_a11_4_1[5]\, B => scaler_m_5, C - => \prdata_1_i_0_a11_4_2[5]\, Y => - \prdata_1_i_0_a11_4_4[5]\); - - \r.haddr_RNIQKO8[5]\ : NOR2B - port map(A => un1_apbi_7_1, B => N_766, Y => N_794); - - \r.haddr_0[3]\ : DFN1E1 - port map(D => haddr(3), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr_0[3]\); - - \r.prdata[27]\ : DFN1 - port map(D => N_46_i_0, CLK => lclk_c, Q => hrdata(27)); - - \r.haddr_0_RNIN601[3]\ : OR2A - port map(A => cfgsel, B => \paddr_0[3]\, Y => N_789); - - \r.prdata_RNO_7[7]\ : NOR3C - port map(A => \prdata_1_i_0_a11_7_1[7]\, B => - \prdata_1_i_0_a11_7_0[7]\, C => N_220, Y => - \prdata_1_i_0_a11_7_3[7]\); - - \r.prdata_RNO_18[7]\ : AOI1B - port map(A => iforce_0_2, B => N_898, C => N_859, Y => - \prdata_1_i_0_a11_5_0[7]\); - - \r.prdata[18]\ : DFN1 - port map(D => \prdata_1[18]\, CLK => lclk_c, Q => - hrdata(18)); - - \r.prdata_RNO_17[7]\ : AOI1B - port map(A => ilevel_3, B => prdata_0_sqmuxa, C => N_861, Y - => \prdata_1_i_0_a11_5_1[7]\); - - \r.haddr_RNIRB63[3]\ : NOR2A - port map(A => \paddr[3]\, B => N_760, Y => N_776); - - \r.prdata_RNO_4[5]\ : NOR3C - port map(A => \prdata_1_i_0_3[5]\, B => \prdata_1_i_0_2[5]\, - C => \prdata_1_i_0_6[5]\, Y => \prdata_1_i_0_7[5]\); - - \r.haddr_RNIFAC4[5]\ : XOR2 - port map(A => \paddr[5]\, B => \paddr[6]\, Y => N_84); - - \r.haddr[13]\ : DFN1E1 - port map(D => haddr(13), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[13]\); - - \r.prdata_RNO_4[6]\ : OA1A - port map(A => N_755, B => prdata_0_6, C => N_602_i, Y => - \prdata_1_i_0_3[6]\); - - \r.pwdata_0[13]\ : DFN1E0 - port map(D => hwdata(13), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(13)); - - \r.prdata_RNO_0[5]\ : AOI1B - port map(A => paren, B => prdata(31), C => - \prdata_1_i_0_a11_8_2[5]\, Y => \prdata_1_i_0_a11_8_3[5]\); - - \r.prdata_RNO_14[10]\ : OR3A - port map(A => N_772, B => N_743, C => prdata_0_10, Y => - \prdata_RNO_14[10]\); - - \r.pwdata[17]\ : DFN1E0 - port map(D => hwdata(17), CLK => lclk_c, E => N_12_0, Q => - pwdata(17)); - - \r.prdata_RNO_5[23]\ : AOI1B - port map(A => \paddr[6]\, B => N_781, C => N_526, Y => - \prdata_1_i_i_0[23]\); - - \r.prdata_RNO_14[12]\ : OR3A - port map(A => N_772, B => N_743, C => prdata_0_12, Y => - \prdata_RNO_14[12]\); - - \r.prdata_RNO_9[10]\ : OR2A - port map(A => N_752_0, B => prdata_1_10, Y => - \prdata_RNO_9[10]\); - - \r.prdata_RNO_12[2]\ : MX2 - port map(A => romrws(2), B => ramwws(0), S => \paddr[2]\, Y - => N_6427); - - \r.prdata_RNO_5[27]\ : OR2A - port map(A => N_751, B => prdata_2_27, Y => - \prdata_RNO_5[27]\); - - \r.haddr_RNIS3MH[10]\ : XO1A - port map(A => \paddr[10]\, B => \paddr[11]\, C => \N_78\, Y - => \prdata_1_i_0_a2_0[21]\); - - \r.prdata_RNO_13[3]\ : OR2B - port map(A => prdata_3_1, B => N_752, Y => N_730); - - \r.prdata_RNO_16[9]\ : MX2 - port map(A => romwidth(1), B => rambanksz_0, S => - \paddr_2[2]\, Y => N_5069); - - \r.prdata_RNO_0[19]\ : NOR3C - port map(A => N_655, B => N_654, C => \prdata_1_0_0_0[19]\, - Y => \prdata_1_0_0_2[19]\); - - \r.prdata_RNO_10[8]\ : AO1A - port map(A => N_232_0, B => romwidth(0), C => N_778_i, Y - => \prdata_RNO_10[8]\); - - \r.prdata_RNO_8[2]\ : NOR2B - port map(A => N_722, B => N_732, Y => \prdata_1_0_0_0[2]\); - - \r.prdata[30]\ : DFN1 - port map(D => \prdata_1[30]\, CLK => lclk_c, Q => - hrdata(30)); - - \r.prdata[23]\ : DFN1 - port map(D => N_60, CLK => lclk_c, Q => hrdata(23)); - - \r.prdata_RNO_2[25]\ : OR3B - port map(A => bexcen, B => N_767, C => N_232_0, Y => N_668); - - \r.prdata_RNO_1[15]\ : AOI1B - port map(A => prdata(15), B => N_762, C => N_689, Y => - \prdata_1_0_0_5[15]\); - - \r.prdata_RNO_2[19]\ : OR2B - port map(A => prdata_2_19, B => N_751, Y => N_654); - - \r.prdata_RNO_0[7]\ : NOR3C - port map(A => \prdata_1_i_0_2[7]\, B => \prdata_1_i_0_1[7]\, - C => \prdata_1_i_0_5[7]\, Y => \prdata_1_i_0_6[7]\); - - \comb.v.prdata_1_i_0_a11_3_RNO_0[4]\ : AOI1B - port map(A => scaler(4), B => readdata55, C => - \prdata_1_i_0_a11_3_1[4]\, Y => \prdata_1_i_0_a11_3_3[4]\); - - \r.prdata_RNO_1[21]\ : OA1A - port map(A => N_752_0, B => prdata_0_21, C => N_101, Y => - \prdata_1_i_0_5[21]\); - - \r.prdata_RNO_0[13]\ : AO1B - port map(A => readdata_1_iv_0_0, B => value_m_9, C => N_758, - Y => N_538); - - \r.pwdata[2]\ : DFN1E0 - port map(D => hwdata(2), CLK => lclk_c, E => N_12, Q => - pwdata(2)); - - \r.prdata_RNO_0[3]\ : AO1B - port map(A => readdata_iv_3(3), B => reload_m_3, C => N_758, - Y => N_727); - - \r.prdata_RNO_10[10]\ : AOI1B - port map(A => ilevel_6, B => prdata_0_sqmuxa, C => N_478, Y - => \prdata_1_i_0_a11_4_1[10]\); - - \r.prdata_RNO_15[0]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_0, C => N_756, Y - => \prdata_1_i_0_a11_9_0[0]\); - - \r.prdata_RNO_2[13]\ : OR3C - port map(A => N_756, B => delayirqen, C => prdata(31), Y - => N_542); - - \r.prdata_RNO_19[0]\ : OR2 - port map(A => \paddr[6]\, B => N_760, Y => N_638); - - \r.cfgsel_RNIO6OB2_0\ : AO1D - port map(A => \prdata_1_i_0_o2_1_0[12]\, B => N_82, C => - cfgsel, Y => N_778_i); - - \r.prdata_RNO_0[17]\ : NOR3C - port map(A => N_649, B => N_646, C => \prdata_1_0_0_1[17]\, - Y => \prdata_1_0_0_2[17]\); - - \comb.v.prdata_1_i_0_a11[28]\ : OR2 - port map(A => N_782_i, B => prdata(28), Y => - \prdata_1_i_0_a11[28]\); - - \r.haddr_RNIS3MH_2[10]\ : NOR2A - port map(A => N_772, B => \paddr[10]\, Y => - \psel_0_a3_0_a2_0_a11_0[11]\); - - \r.prdata_RNO_10[12]\ : AOI1B - port map(A => iforce_0_7, B => N_898, C => N_863, Y => - \prdata_1_i_0_a11_6_0[12]\); - - \r.prdata_RNO_2[17]\ : OR2B - port map(A => prdata_2_17, B => N_755, Y => N_646); - - \r.prdata_RNO_7[2]\ : OR2B - port map(A => prdata_3_0, B => N_755, Y => N_733); - - \r.pwdata[25]\ : DFN1E0 - port map(D => hwdata(25), CLK => lclk_c, E => N_12_0_1, Q - => pwdata(25)); - - \r.prdata_RNO_6[12]\ : NOR3C - port map(A => \prdata_1_i_0_1[12]\, B => - \prdata_RNO_12[12]\, C => \prdata_RNO_13[12]\, Y => - \prdata_1_i_0_3[12]\); - - \r.pwdata_0[4]\ : DFN1E0 - port map(D => hwdata(4), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[4]\); - - \r.cfgsel_RNII71L\ : NOR2 - port map(A => N_776, B => N_544, Y => N_139); - - \comb.v.prdata_1_0_0_a11_0_0[26]\ : NOR2 - port map(A => un1_apbi_7_1, B => N_770, Y => \un1_apbi_7_3\); - - \r.haddr_RNI7P9D[10]\ : NOR2B - port map(A => \paddr[11]\, B => \paddr[10]\, Y => \N_116\); - - \r.prdata_RNO[9]\ : NOR3C - port map(A => \prdata_1_i_0_6[9]\, B => N_572_i, C => - N_577_i, Y => N_104_i_0); - - \r.prdata[11]\ : DFN1 - port map(D => N_108_i_0, CLK => lclk_c, Q => hrdata(11)); - - \r.prdata_RNO[13]\ : OR3C - port map(A => N_538, B => \prdata_1_0_0_6[13]\, C => N_542, - Y => \prdata_1[13]\); - - \r.pwdata[13]\ : DFN1E0 - port map(D => hwdata(13), CLK => lclk_c, E => N_12_0, Q => - pwdata(13)); - - \r.prdata_RNO_6[2]\ : OR3B - port map(A => N_330, B => rdata60_1, C => N_763, Y => N_734); - - \comb.v.prdata_1_i_0[28]\ : AND2 - port map(A => N_678, B => \prdata_1_i_0_4[28]\, Y => - N_50_i_0); - - \r.prdata_RNO_9[21]\ : OA1A - port map(A => cfgsel, B => \paddr_0[4]\, C => N_760, Y => - \prdata_1_i_0_0[21]\); - - \r.prdata_RNO_5[1]\ : OR3C - port map(A => readdata_9_i_m(1), B => reload_RNI6SNI(1), C - => \prdata_1_0_0_a11_5_3[1]\, Y => N_630_i); - - \r.prdata_RNO_11[5]\ : OR3C - port map(A => \prdata_1_i_0_a11_6_1[5]\, B => - \prdata_1_i_0_a11_6_0[5]\, C => N_762, Y => N_612_i); - - \r.prdata[5]\ : DFN1 - port map(D => N_63_i_0, CLK => lclk_c, Q => hrdata(5)); - - \r.prdata_RNO_21[7]\ : OR2A - port map(A => un1_grgpio0_2, B => readdata55_3, Y => - \un1_grgpio0_m[71]\); - - \r.prdata_RNO_3[19]\ : AOI1B - port map(A => prdata(19), B => N_755, C => N_651, Y => - \prdata_1_0_0_0[19]\); - - \r.prdata_RNO_6[5]\ : NOR3C - port map(A => readdata_9_5, B => chain_m, C => N_758, Y => - \prdata_1_i_0_a11_4_1[5]\); - - \r.pwdata[31]\ : DFN1E0 - port map(D => hwdata(31), CLK => lclk_c, E => N_12, Q => - pwdata(31)); - - \r.prdata_RNO_3[13]\ : OR3B - port map(A => N_127, B => un1_dcom0(15), C => N_763, Y => - N_537); - - \r.prdata_RNO_1[2]\ : NOR3C - port map(A => N_735, B => \prdata_1_0_0_3[2]\, C => - \prdata_1_0_0_4[2]\, Y => \prdata_1_0_0_6[2]\); - - \r.prdata_RNO_6[20]\ : OR3A - port map(A => N_744, B => \N_78\, C => prdata_2_20, Y => - \prdata_RNO_6[20]\); - - \r.prdata_RNO_11[15]\ : OR3C - port map(A => N_766, B => \paddr_0[4]\, C => N_774, Y => - N_685); - - \r.pwdata_0_RNISEA[1]\ : INV - port map(A => \pwdata_0[1]\, Y => pwdata_i(1)); - - \r.prdata_RNO_0[30]\ : NOR3C - port map(A => N_662, B => N_660, C => N_663, Y => - \prdata_1_0_0_1[30]\); - - \r.prdata_RNO_10[7]\ : AO1 - port map(A => rdata60_1, B => N_334, C => N_763, Y => - \prdata_RNO_10[7]\); - - \r.prdata_RNO_4[12]\ : OA1A - port map(A => N_751_0, B => prdata(12), C => - \prdata_RNO_8[12]\, Y => \prdata_1_i_0_5[12]\); - - \r.prdata_RNO_6[16]\ : OR2B - port map(A => prdata_2_16, B => N_755, Y => N_716); - - \r.prdata_RNO_3[17]\ : AOI1B - port map(A => prdata(17), B => N_752_0, C => N_647, Y => - \prdata_1_0_0_1[17]\); - - \r.prdata_RNO_10[0]\ : OR2A - port map(A => N_755, B => prdata_2_0, Y => - \prdata_RNO_10[0]\); - - \r.haddr_RNIA3NQ[16]\ : NOR3A - port map(A => \prdata_1_i_0_o2_1_3[0]\, B => \paddr[17]\, C - => \paddr[16]\, Y => \prdata_1_i_0_o2_1_5[0]\); - - \r.prdata_RNO_7[12]\ : AOI1B - port map(A => N_240, B => N_220_0, C => N_761, Y => - \prdata_1_i_0_a11_3_0[12]\); - - \r.haddr_RNIEHV22[11]\ : OR2B - port map(A => \paddr[11]\, B => N_744, Y => N_745); - - \r.prdata[29]\ : DFN1 - port map(D => \prdata_1[29]\, CLK => lclk_c, Q => - hrdata(29)); - - \comb.v.prdata_1_i_0_a11_3_RNO_2[4]\ : NOR3C - port map(A => readdata_9_4, B => irqpen_m, C => N_758, Y - => \prdata_1_i_0_a11_3_1[4]\); - - \r.prdata_RNO_0[8]\ : NOR3C - port map(A => \prdata_RNO_2[8]\, B => \prdata_RNO_3[8]\, C - => N_580_i, Y => \prdata_1_i_0_6[8]\); - - \r.cfgsel_RNIM601\ : OR2A - port map(A => cfgsel, B => \paddr_0[2]\, Y => N_760); - - \r.prdata_RNO_13[5]\ : OA1C - port map(A => N_777, B => \paddr[6]\, C => N_544, Y => - \prdata_1_i_0_0[5]\); - - \r.pwdata_0[7]\ : DFN1E0 - port map(D => hwdata(7), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[7]\); - - \comb.v.prdata_1_i_0_a11_3_RNO_1[4]\ : OA1A - port map(A => reload_0_d0, B => readdata_1_sqmuxa_1_0, C - => value_m_0, Y => \prdata_1_i_0_a11_3_2[4]\); - - \r.prdata_RNO_10[14]\ : OR2B - port map(A => prdata_2_14, B => N_752, Y => N_499); - - \r.prdata_RNO[3]\ : OR3C - port map(A => N_727, B => \prdata_1_0_0_7[3]\, C => N_731, - Y => \prdata_1[3]\); - - \r.prdata_RNO[1]\ : OR3C - port map(A => \prdata_1_0_0_7[1]\, B => \prdata_1_0_0_6[1]\, - C => N_634, Y => \prdata_1[1]\); - - \r.prdata_RNO_12[5]\ : AO1C - port map(A => \paddr[3]\, B => N_133, C => N_767, Y => - \prdata_RNO_12[5]\); - - \r.prdata_RNO_5[10]\ : OR3C - port map(A => \prdata_1_i_0_a11_4_1[10]\, B => - \prdata_1_i_0_a11_4_0[10]\, C => N_762, Y => N_567_i); - - \r.prdata_RNO_4[4]\ : AOI1B - port map(A => \prdata_1_i_0_a11_2_1[4]\, B => N_771, C => - \prdata_1_i_0_3[4]\, Y => \prdata_1_i_0_5[4]\); - - \r.prdata_RNO_5[24]\ : OR2B - port map(A => prdata_0_24, B => N_755, Y => N_522); - - \r.pwdata[19]\ : DFN1E0 - port map(D => hwdata(19), CLK => lclk_c, E => N_12_0, Q => - pwdata(19)); - - \r.prdata_RNO_4[16]\ : OR2A - port map(A => N_777, B => \paddr[5]\, Y => N_715); - - \r.prdata_RNO[11]\ : NOR3C - port map(A => \prdata_1_i_0_6[11]\, B => - \prdata_1_i_0_5[11]\, C => N_561, Y => N_108_i_0); - - \r.prdata_RNO_7[16]\ : OR2B - port map(A => prdata_3_14, B => N_752, Y => N_720); - - \r.prdata_RNO_9[4]\ : NOR3C - port map(A => N_6434, B => N_6436, C => N_6435, Y => - \prdata_1_i_0_a11_2_1[4]\); - - \r.prdata_RNO[12]\ : NOR3C - port map(A => \prdata_1_i_0_7[12]\, B => - \prdata_1_i_0_6[12]\, C => \prdata_RNO_2[12]\, Y => - N_110_i_0); - - \r.cfgsel_RNIJD2A\ : MX2B - port map(A => \prdata_1_0_0_0_a2_0[14]\, B => N_774, S => - N_90, Y => N_138); - - \r.prdata_RNO_10[4]\ : OA1A - port map(A => N_751_0, B => prdata(4), C => - \prdata_RNO_15[4]\, Y => \prdata_1_i_0_3[4]\); - - \r.prdata_RNO_2[4]\ : OA1A - port map(A => N_755, B => prdata_0_4, C => N_621_i, Y => - \prdata_1_i_0_2[4]\); - - \r.hready\ : DFN1 - port map(D => N_198, CLK => lclk_c, Q => \hready\); - - \r.prdata_RNO_0[14]\ : NOR2B - port map(A => tsemptyirqen, B => N_756, Y => - \prdata_1_0_0_a11_7_0[14]\); - - \r.prdata[3]\ : DFN1 - port map(D => \prdata_1[3]\, CLK => lclk_c, Q => hrdata(3)); - - \r.prdata_RNO_3[7]\ : OA1A - port map(A => N_755, B => prdata_0_7, C => N_592_i, Y => - \prdata_1_i_0_2[7]\); - - \r.prdata_RNO_2[14]\ : NOR3C - port map(A => N_207, B => N_498, C => - \prdata_1_0_0_0_5[14]\, Y => \prdata_1_0_0_0_6[14]\); - - \r.prdata_RNO[29]\ : AO1B - port map(A => prdata(29), B => N_758, C => - \prdata_1_0_0_1[29]\, Y => \prdata_1[29]\); - - \r.prdata_RNO[10]\ : NOR3C - port map(A => \prdata_1_i_0_6[10]\, B => - \prdata_1_i_0_5[10]\, C => N_569, Y => N_106_i_0); - - \r.pwdata_0_RNITIA[2]\ : INV - port map(A => \pwdata_0[2]\, Y => pwdata_i(2)); - - \r.prdata_RNO_12[13]\ : NOR2A - port map(A => cfgsel, B => N_770, Y => - \prdata_1_0_0_a11_0[13]\); - - \r.prdata_RNO_8[21]\ : AOI1B - port map(A => N_240_0, B => N_229, C => N_761, Y => - \prdata_1_i_0_a11_2_0[21]\); - - \r.prdata_RNO_6[15]\ : OR3B - port map(A => N_127, B => un1_dcom0(17), C => N_763, Y => - N_689); - - \r.prdata_RNO_14[4]\ : MX2 - port map(A => romwws(0), B => ramwidth(0), S => - \paddr_2[2]\, Y => N_132); - - \r.haddr[4]\ : DFN1E1 - port map(D => haddr(4), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[4]\); - - \r.prdata_RNO[31]\ : AO1B - port map(A => prdata(31), B => N_756, C => - \prdata_1_0_0_0_2[31]\, Y => \prdata_1[31]\); - - \r.prdata_RNO_16[1]\ : NOR2 - port map(A => \paddr_0[4]\, B => N_770, Y => - \prdata_1_0_0_a11_1_0[1]\); - - \r.prdata_RNO_2[29]\ : OR2B - port map(A => prdata_0_29, B => N_755, Y => N_656); - - \r.prdata_RNO_1[19]\ : OR2B - port map(A => prdata_3_17, B => N_752, Y => N_655); - - \r.prdata_RNO[27]\ : NOR3C - port map(A => \prdata_1_i_0_3[27]\, B => - \prdata_1_i_0_2[27]\, C => \prdata_RNO_2[27]\, Y => - N_46_i_0); - - \r.haddr_2[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr_2[2]\); - - \r.prdata_RNO_0[9]\ : NOR3C - port map(A => \prdata_1_i_0_3[9]\, B => \prdata_1_i_0_2[9]\, - C => \prdata_1_i_0_4[9]\, Y => \prdata_1_i_0_6[9]\); - - \r.prdata_RNO_9[3]\ : NOR2B - port map(A => \prdata_1_0_0_0[3]\, B => N_721, Y => - \prdata_1_0_0_1[3]\); - - \r.psel_RNO\ : AOI1B - port map(A => psel_RNO_0, B => N_168, C => rstn, Y => N_34); - - \r.prdata[26]\ : DFN1 - port map(D => \prdata_1[26]\, CLK => lclk_c, Q => - hrdata(26)); - - \r.prdata_RNO_2[23]\ : OR2B - port map(A => prdata_1_23, B => N_751, Y => N_698); - - \r.prdata_RNO_1[13]\ : NOR3C - port map(A => N_537, B => N_540, C => \prdata_1_0_0_5[13]\, - Y => \prdata_1_0_0_6[13]\); - - \r.prdata_RNO_11[1]\ : AOI1B - port map(A => \prdata_1_0_0_a11_1_0[1]\, B => N_776, C => - N_625, Y => \prdata_1_0_0_0[1]\); - - \r.prdata_RNO_2[27]\ : AO1C - port map(A => N_156, B => rcnt(1), C => N_756, Y => - \prdata_RNO_2[27]\); - - \r.prdata_RNO_1[17]\ : OR2B - port map(A => prdata_3_15, B => N_751, Y => N_649); - - \r.prdata_RNO_8[10]\ : AOI1B - port map(A => N_240_0, B => N_218, C => N_761, Y => - \prdata_1_i_0_a11_1_0[10]\); - - \r.prdata_RNO_5[21]\ : OR3C - port map(A => reload_m_21, B => \prdata_1_i_0_a11_2_0[21]\, - C => value_m_17, Y => N_703); - - \r.pwdata_0[12]\ : DFN1E0 - port map(D => hwdata(12), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(12)); - - \r.prdata_RNO_3[14]\ : OR3B - port map(A => N_127, B => un1_dcom0(16), C => N_763, Y => - N_207); - - \r.prdata_RNO[30]\ : AO1B - port map(A => prdata(30), B => N_758, C => - \prdata_1_0_0_1[30]\, Y => \prdata_1[30]\); - - \comb.v.prdata_1_i_0_a11_4[28]\ : NAND2 - port map(A => N_756, B => prdata_0_28, Y => N_678); - - \r.pwdata[22]\ : DFN1E0 - port map(D => hwdata(22), CLK => lclk_c, E => N_12_0_0, Q - => pwdata(22)); - - \r.prdata_RNO_3[22]\ : AO1B - port map(A => readdata_1_iv_0_9, B => value_m_18, C => - N_758, Y => N_530); - - \r.prdata_RNO_4[15]\ : NOR3C - port map(A => \prdata_RNO_7[15]\, B => \prdata_1_0_0_0[15]\, - C => N_138, Y => \prdata_1_0_0_2[15]\); - - \r.prdata_RNO_15[1]\ : MX2 - port map(A => romrws(1), B => ramrws(1), S => \paddr[2]\, Y - => N_5063); - - \v.hready_0_sqmuxa_0_a3_0_a2\ : NOR2A - port map(A => hready_0_sqmuxa_0_a3_0_a2_0, B => - un51_ioen_NE, Y => hready_0_sqmuxa); - - \r.prdata[20]\ : DFN1 - port map(D => N_39_i_0, CLK => lclk_c, Q => hrdata(20)); - - \r.pwdata[16]\ : DFN1E0 - port map(D => hwdata(16), CLK => lclk_c, E => N_12_0, Q => - pwdata(16)); - - \r.haddr_RNILAC4_1[8]\ : OR2A - port map(A => \paddr[9]\, B => \paddr[8]\, Y => \N_749\); - - \r.prdata_RNO_7[15]\ : OR3A - port map(A => \paddr[6]\, B => \paddr[5]\, C => N_793, Y - => \prdata_RNO_7[15]\); - - \r.prdata_RNO[26]\ : OR3C - port map(A => N_517, B => \prdata_1_0_0_3[26]\, C => N_520, - Y => \prdata_1[26]\); - - \r.pwdata_0_RNIRAA[0]\ : INV - port map(A => \pwdata_0[0]\, Y => pwdata_i(0)); - - \r.prdata_RNO_1[6]\ : NOR3C - port map(A => \prdata_1_i_0_3[6]\, B => \prdata_1_i_0_2[6]\, - C => \prdata_1_i_0_6[6]\, Y => \prdata_1_i_0_7[6]\); - - \r.prdata_RNO_0[11]\ : AOI1B - port map(A => \prdata_1_i_0_a11_2_1[11]\, B => value_m_7, C - => \prdata_1_i_0_4[11]\, Y => \prdata_1_i_0_6[11]\); - - \r.prdata_RNO_14[9]\ : NOR2A - port map(A => N_5069, B => \paddr[3]\, Y => \prdata_0[9]\); - - \r.prdata[7]\ : DFN1 - port map(D => N_100_i_0, CLK => lclk_c, Q => hrdata(7)); - - \r.prdata_RNO_2[30]\ : OR2B - port map(A => prdata_0_30, B => N_755, Y => N_660); - - \r.prdata_RNO_2[11]\ : OR3C - port map(A => brate_m_7, B => N_756, C => debug_m, Y => - N_561); - - \r.prdata_RNO_19[6]\ : AOI1B - port map(A => iforce_0_1, B => N_898, C => N_361, Y => - \prdata_1_i_0_a11_6_0[6]\); - - \r.haddr_0_RNI0QIB[3]\ : OA1C - port map(A => N_5062, B => \paddr_0[3]\, C => cfgsel, Y => - N_790); - - \r.prdata_RNO_4[22]\ : OR2B - port map(A => prdata_2_22, B => N_752_0, Y => N_532); - - \comb.v.prdata_1_i_0_RNO_2[28]\ : NOR3C - port map(A => \prdata_1_i_0_RNO_3[28]\, B => - \prdata_1_i_0_a11[28]\, C => \prdata_1_i_0_RNO_4[28]\, Y - => \prdata_1_i_0_1[28]\); - - \r.cfgsel_RNI6HED\ : OR3C - port map(A => N_766, B => cfgsel, C => N_117, Y => N_202); - - \comb.v.prdata_1_i_0_RNO_3[28]\ : OR3A - port map(A => N_744, B => \N_78\, C => prdata_2_28, Y => - \prdata_1_i_0_RNO_3[28]\); - - \r.prdata_RNO[7]\ : NOR3C - port map(A => \prdata_1_i_0_6[7]\, B => N_590_i, C => - N_594_i, Y => N_100_i_0); - - \r.prdata_RNO_0[20]\ : NOR3C - port map(A => \prdata_RNO_3[20]\, B => \prdata_1_i_0_3[20]\, - C => N_710, Y => \prdata_1_i_0_6[20]\); - - \r.prdata[17]\ : DFN1 - port map(D => \prdata_1[17]\, CLK => lclk_c, Q => - hrdata(17)); - - \r.haddr_RNI3SB72_1[8]\ : NOR2 - port map(A => \N_750\, B => N_745, Y => N_752); - - \r.haddr_0[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr_0[2]\); - - \r.penable_RNO_0\ : OA1C - port map(A => \state[0]\, B => \pwrite\, C => N_131, Y => - N_199); - - \r.haddr_RNIKKO8[3]\ : OR2A - port map(A => un1_apbi_2, B => N_791, Y => N_117); - - \r.prdata_RNO_6[0]\ : OA1A - port map(A => value_0, B => value_0_sqmuxa_0, C => - scaler_m_0, Y => \prdata_1_i_0_a11_3_4[0]\); - - \r.prdata_RNO_11[13]\ : OR2B - port map(A => prdata_2_13, B => N_752_0, Y => N_541); - - \r.prdata_RNO_15[6]\ : AOI1B - port map(A => rdata59_4, B => dout_5, C => - \prdata_1_i_0_a11_3_0[6]\, Y => \prdata_1_i_0_a11_3_1[6]\); - - \r.haddr_RNI7P9D_0[10]\ : NOR2A - port map(A => \paddr[10]\, B => \paddr[11]\, Y => psel_1(7)); - - \r.pwdata[10]\ : DFN1E0 - port map(D => hwdata(10), CLK => lclk_c, E => N_12_0, Q => - pwdata(10)); - - \r.prdata_RNO_4[7]\ : NOR3B - port map(A => \prdata_RNO_9[7]\, B => \prdata_RNO_10[7]\, C - => N_554_i, Y => \prdata_1_i_0_1[7]\); - - \r.cfgsel\ : DFN1 - port map(D => cfgsel2, CLK => lclk_c, Q => cfgsel); - - \r.prdata_RNO_3[26]\ : OR2B - port map(A => prdata_0_26, B => N_755, Y => N_516); - - \r.haddr_RNI3SB72_4[11]\ : NOR2 - port map(A => N_745, B => \N_78\, Y => N_755); - - \r.prdata_RNO_8[5]\ : OA1A - port map(A => N_755, B => prdata_0_5, C => N_612_i, Y => - \prdata_1_i_0_3[5]\); - - \r.prdata_RNO_19[5]\ : MX2 - port map(A => romwws(1), B => ramwidth(1), S => \paddr[2]\, - Y => N_133); - - \r.haddr_RNI3SB72[11]\ : OR3A - port map(A => N_744, B => \N_78\, C => \paddr[11]\, Y => - N_763); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.prdata_RNO_9[2]\ : AOI1B - port map(A => prdata_0_2, B => N_751_0, C => N_739, Y => - \prdata_1_0_0_2[2]\); - - \r.prdata_RNO_20[5]\ : NOR2B - port map(A => readdata_2_m(5), B => \un1_grgpio0_m[69]\, Y - => \prdata_1_i_0_a11_3_0[5]\); - - \r.prdata_RNO_4[26]\ : AOI1B - port map(A => \prdata_1_0_0_a11_0[26]\, B => N_767, C => - N_515, Y => \prdata_1_0_0_0[26]\); - - \apbi.psel_0_a3_1_a2_2_a2[15]\ : NAND2 - port map(A => \N_116\, B => \N_769\, Y => N_796); - - \r.prdata_RNO_3[11]\ : OA1A - port map(A => reload_7, B => readdata_1_sqmuxa_1_0, C => - \prdata_1_i_0_a11_2_0[11]\, Y => - \prdata_1_i_0_a11_2_1[11]\); - - \r.prdata_RNO_13[11]\ : OR3A - port map(A => N_772, B => N_743, C => prdata_0_11, Y => - \prdata_RNO_13[11]\); - - \r.prdata_RNO_4[1]\ : NOR3C - port map(A => N_624, B => \prdata_1_0_0_0[1]\, C => N_627, - Y => \prdata_1_0_0_2[1]\); - - \r.prdata[13]\ : DFN1 - port map(D => \prdata_1[13]\, CLK => lclk_c, Q => - hrdata(13)); - - \r.haddr_RNIS3MH_0[10]\ : XA1 - port map(A => \paddr[10]\, B => \paddr[11]\, C => \N_78\, Y - => N_748); - - \r.prdata_RNO_8[1]\ : AO1B - port map(A => prdata_iv_0_0_d0, B => \dout_m[1]\, C => - N_771, Y => N_629); - - \r.prdata_RNO_8[4]\ : AO1 - port map(A => rdata60_1, B => N_332, C => N_763, Y => - \prdata_RNO_8[4]\); - - \r.haddr_RNIQ2LQ_0[12]\ : NOR3A - port map(A => \prdata_1_i_0_o2_1_1[0]\, B => \paddr[13]\, C - => \paddr[12]\, Y => \prdata_1_i_0_o2_1_4[0]\); - - \r.prdata_RNO_1[20]\ : OA1A - port map(A => N_752_0, B => prdata_0_20, C => N_101, Y => - \prdata_1_i_0_5[20]\); - - \comb.v.prdata_1_i_0_a11[21]\ : OR2 - port map(A => N_782_i, B => prdata(21), Y => - \prdata_1_i_0_a11[21]\); - - \r.prdata_RNO_1[1]\ : NOR3C - port map(A => N_628, B => N_632, C => N_629, Y => - \prdata_1_0_0_6[1]\); - - \r.pwdata_0[10]\ : DFN1E0 - port map(D => hwdata(10), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(10)); - - \r.prdata_RNO[14]\ : AO1B - port map(A => \prdata_1_0_0_a11_7_0[14]\, B => prdata(31), - C => \prdata_1_0_0_0_7[14]\, Y => \prdata_1[14]\); - - \r.prdata_RNO_18[1]\ : NOR3C - port map(A => reload_RNIRDRG(1), B => restart_RNIIKBB, C - => value_RNIBAHH(1), Y => \prdata_1_0_0_a11_5_1[1]\); - - \r.prdata_RNO[0]\ : NOR3C - port map(A => \prdata_1_i_0_8[0]\, B => N_639_i, C => - N_645_i, Y => N_58_i_0); - - \r.prdata_RNO[2]\ : OR3C - port map(A => N_736, B => \prdata_1_0_0_6[2]\, C => N_740, - Y => \prdata_1[2]\); - - \r.prdata_RNO_19[7]\ : OA1 - port map(A => oen(7), B => rdata60_4_0, C => - \un1_grgpio0_m[71]\, Y => \prdata_1_i_0_a11_2_0[7]\); - - \r.prdata_RNO_9[12]\ : AOI1B - port map(A => ilevel_8, B => prdata_0_sqmuxa, C => N_865, Y - => \prdata_1_i_0_a11_6_1[12]\); - - \r.prdata_RNO_2[24]\ : AO1B - port map(A => readdata_1_iv_0_11, B => value_m_20, C => - N_758, Y => N_523); - - \r.prdata_RNO_1[14]\ : AOI1B - port map(A => prdata(14), B => N_758, C => - \prdata_1_0_0_0_6[14]\, Y => \prdata_1_0_0_0_7[14]\); - - \r.prdata_RNO_10[9]\ : OA1 - port map(A => N_778_i, B => \prdata_0[9]\, C => - \prdata_RNO_15[9]\, Y => \prdata_1_i_0_0[9]\); - - \comb.v.prdata_1_i_0_a11_6_RNO_0[8]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_8, C => N_756, Y - => \prdata_1_i_0_a11_6_0[8]\); - - \r.prdata_RNO_14[7]\ : OA1A - port map(A => reload_3, B => readdata_1_sqmuxa_1_0, C => - value_m_3, Y => \prdata_1_i_0_a11_3_1[7]\); - - \r.prdata_RNO_10[6]\ : OA1A - port map(A => value_6, B => value_0_sqmuxa_0, C => - scaler_m_6, Y => \prdata_1_i_0_a11_4_2[6]\); - - \r.haddr_RNINPBD_0[18]\ : NOR2 - port map(A => \paddr[18]\, B => \paddr[19]\, Y => - \prdata_1_i_0_o2_1_3[0]\); - - \r.prdata_RNO_13[6]\ : NOR2B - port map(A => N_595, B => N_139, Y => \prdata_1_i_0_0[6]\); - - \r.prdata[24]\ : DFN1 - port map(D => \prdata_1[24]\, CLK => lclk_c, Q => - hrdata(24)); - - \r.prdata_RNO_3[0]\ : NOR3B - port map(A => \prdata_1_i_0_2[0]\, B => \prdata_RNO_10[0]\, - C => N_762, Y => \prdata_1_i_0_4[0]\); - - \r.prdata_RNO_17[0]\ : OAI1 - port map(A => \prdata_1_i_0_a11_0[0]\, B => - \prdata_1_i_0_a11_1_0[0]\, C => N_790, Y => - \prdata_1_i_0_1[0]\); - - \r.prdata_RNO_6[13]\ : OR2B - port map(A => prdata_0_13, B => N_755, Y => N_536); - - \r.hready_RNO_0\ : AO1A - port map(A => hready_0_sqmuxa_0, B => \hready\, C => - \state[1]\, Y => N_5860); - - \r.haddr_RNI3SB72_2[11]\ : NOR2 - port map(A => N_747, B => \N_78\, Y => N_758); - - \r.prdata_RNO_3[25]\ : AOI1B - port map(A => prdata(25), B => N_751, C => N_672, Y => - \prdata_1_0_0_1[25]\); - - \comb.v.prdata_1_i_0_a11_6[8]\ : NAND2 - port map(A => extclken_m, B => \prdata_1_i_0_a11_6_1[8]\, Y - => N_585); - - \comb.v.prdata_1_i_0_RNO_4[28]\ : OR2A - port map(A => N_751, B => prdata_3_26, Y => - \prdata_1_i_0_RNO_4[28]\); - - \r.prdata_RNO_3[3]\ : AO1B - port map(A => prdata_iv_0_2, B => \dout_m[3]\, C => N_771, - Y => N_726); - - \r.haddr_RNI3SB72_3[11]\ : NOR2 - port map(A => \N_749\, B => N_747, Y => N_762); - - \r.haddr[7]\ : DFN1E1 - port map(D => haddr(7), CLK => lclk_c, E => hready_0_sqmuxa, - Q => paddr_5); - - \r.prdata_RNO_4[25]\ : OR2B - port map(A => prdata_3_23, B => N_752, Y => N_672); - - \r.state_RNI4KU3[0]\ : OR2B - port map(A => \pwrite\, B => \state[0]\, Y => N_12_0_1); - - \r.prdata_RNO_14[11]\ : AO1A - port map(A => \paddr_0[3]\, B => N_5070, C => N_778_i, Y - => \prdata_RNO_14[11]\); - - \r.prdata_RNO_7[4]\ : AO1C - port map(A => \paddr_0[3]\, B => N_132, C => N_767, Y => - \prdata_RNO_7[4]\); - - \r.pwdata[28]\ : DFN1E0 - port map(D => hwdata(28), CLK => lclk_c, E => N_12, Q => - pwdata(28)); - - \r.prdata[19]\ : DFN1 - port map(D => \prdata_1[19]\, CLK => lclk_c, Q => - hrdata(19)); - - \r.haddr_RNI6ONE4[10]\ : OA1B - port map(A => N_743, B => \prdata_1_i_0_a2_0[21]\, C => - N_762, Y => N_101); - - \r.haddr[5]\ : DFN1E1 - port map(D => haddr(5), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[5]\); - - \r.prdata_RNO_17[6]\ : AND2 - port map(A => \prdata_1_i_0_a11_8_1[6]\, B => - \prdata_1_i_0_a11_8_0[6]\, Y => \prdata_1_i_0_a11_8_2[6]\); - - \r.pwdata[14]\ : DFN1E0 - port map(D => hwdata(14), CLK => lclk_c, E => N_12_0, Q => - pwdata(14)); - - \r.psel_RNO_0\ : OR2A - port map(A => hready_0_sqmuxa_0, B => hwrite, Y => - psel_RNO_0); - - \comb.v.prdata_1_i_0_a11_1_RNO[27]\ : AND2 - port map(A => reload_m_27, B => \prdata_1_i_0_a11_1_0[27]\, - Y => \prdata_1_i_0_a11_1_1[27]\); - - \r.prdata_RNO_0[18]\ : NOR3C - port map(A => N_666, B => N_664, C => N_667, Y => - \prdata_1_0_0_1[18]\); - - \r.prdata_RNO_4[19]\ : OR3B - port map(A => ioen, B => N_767, C => N_232_0, Y => N_651); - - \r.state_RNI4KU3_1[0]\ : OR2B - port map(A => \pwrite\, B => \state[0]\, Y => N_12); - - \r.prdata_RNO_2[18]\ : OR2B - port map(A => prdata_0_18, B => N_755, Y => N_664); - - \r.prdata_RNO_14[5]\ : OR2 - port map(A => prdata_2_5, B => N_763, Y => - \prdata_RNO_14[5]\); - - \r.prdata_RNO_5[0]\ : AOI1B - port map(A => \prdata_1_i_0_a11_6_1[0]\, B => N_771, C => - \prdata_1_i_0_5[0]\, Y => \prdata_1_i_0_7[0]\); - - \r.prdata_RNO_9[7]\ : AO1C - port map(A => N_232_0, B => romwws(3), C => N_767, Y => - \prdata_RNO_9[7]\); - - \r.prdata_RNO_12[7]\ : OA1A - port map(A => N_751_0, B => prdata(7), C => - \prdata_RNO_20[7]\, Y => \prdata_1_i_0_3[7]\); - - \r.prdata_RNO_4[13]\ : AO1B - port map(A => prdata_0_iv_0_0_1_12, B => - prdata_0_iv_0_0_0_12, C => N_762, Y => N_540); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.prdata_RNO_5[2]\ : NOR3C - port map(A => N_733, B => \prdata_1_0_0_0[2]\, C => - \prdata_1_0_0_2[2]\, Y => \prdata_1_0_0_4[2]\); - - \r.haddr_RNIJ9BD[16]\ : NOR2B - port map(A => \paddr[16]\, B => \paddr[17]\, Y => - penable_1_0_0_i_0_a11_0_2); - - \r.prdata_RNO_10[3]\ : AOI1B - port map(A => prdata_0_3, B => N_751_0, C => N_730, Y => - \prdata_1_0_0_3[3]\); - - \comb.v.prdata_1_i_0_o11_RNO[28]\ : AO1C - port map(A => \paddr_0[2]\, B => N_794, C => cfgsel, Y => - N_786); - - \r.prdata_RNO_6[22]\ : AOI1B - port map(A => \paddr[5]\, B => N_781, C => N_526, Y => - \prdata_1_i_i_0[22]\); - - \r.prdata_RNO_2[21]\ : AO1C - port map(A => N_156, B => tcnt(1), C => N_756, Y => - \prdata_RNO_2[21]\); - - \r.prdata_RNO_1[11]\ : NOR3B - port map(A => N_559_i, B => \prdata_1_i_0_2[11]\, C => - N_771, Y => \prdata_1_i_0_5[11]\); - - \r.prdata_RNO_7[13]\ : NOR3C - port map(A => \prdata_RNO_9[13]\, B => N_534, C => N_202, Y - => \prdata_1_0_0_1[13]\); - - \r.prdata_RNO_4[17]\ : OR3B - port map(A => N_127, B => un1_dcom0(19), C => N_763, Y => - N_647); - - \r.prdata_RNO_8[3]\ : OR2B - port map(A => prdata_2_3, B => N_755, Y => N_724); - - \r.haddr_RNIFAC4_0[5]\ : NOR2B - port map(A => \paddr[6]\, B => \paddr[5]\, Y => N_766); - - \r.prdata_RNO_10[11]\ : AOI1B - port map(A => ipend(11), B => prdata_1_sqmuxa, C => N_839, - Y => \prdata_1_i_0_a11_5_0[11]\); - - \r.haddr[11]\ : DFN1E1 - port map(D => haddr(11), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[11]\); - - \r.prdata_RNO_11[6]\ : OR3C - port map(A => \prdata_1_i_0_a11_6_1[6]\, B => - \prdata_1_i_0_a11_6_0[6]\, C => N_762, Y => N_602_i); - - \r.prdata_RNO_15[5]\ : AOI1B - port map(A => rdata59_4, B => dout_4, C => - \prdata_1_i_0_a11_3_0[5]\, Y => \prdata_1_i_0_a11_3_1[5]\); - - \r.prdata_RNO_7[21]\ : OR3A - port map(A => N_744, B => \N_78\, C => prdata_1_21, Y => - \prdata_RNO_7[21]\); - - \comb.v.prdata_1_i_0_a11_2_RNO_0[20]\ : AOI1B - port map(A => N_240_0, B => N_228, C => N_761, Y => - \prdata_1_i_0_a11_2_0[20]\); - - \r.prdata_RNO_11[9]\ : AO1 - port map(A => rdata60_1, B => N_336, C => N_763, Y => - \prdata_RNO_11[9]\); - - \r.haddr_RNIK9HH[3]\ : OR2 - port map(A => \prdata_1_i_0_o2_0[11]\, B => N_794, Y => - N_176); - - \comb.v.prdata_1_i_0_a2_1[28]\ : OR2 - port map(A => N_111, B => cfgsel, Y => N_782_i); - - \r.prdata_RNO_7[1]\ : AO1B - port map(A => prdata_0_iv_0_0_1_0, B => prdata_0_iv_0_0_0_0, - C => N_762, Y => N_632); - - \r.haddr_RNI1HC5[3]\ : NOR2A - port map(A => N_90, B => N_760, Y => N_777); - - \r.prdata_RNO_3[18]\ : OR2B - port map(A => prdata_3_16, B => N_752, Y => N_667); - - \r.prdata_RNO_12[9]\ : OR2A - port map(A => N_752_0, B => prdata_2_9, Y => - \prdata_RNO_12[9]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.prdata_RNO_5[12]\ : OR3C - port map(A => \prdata_1_i_0_a11_6_1[12]\, B => - \prdata_1_i_0_a11_6_0[12]\, C => N_762, Y => N_550_i); - - \r.prdata_RNO_6[26]\ : NOR2B - port map(A => rcnt(0), B => N_756, Y => - \prdata_1_0_0_a11_5_0[26]\); - - \r.prdata_RNO_21[5]\ : OR2A - port map(A => N_752, B => prdata_1_5, Y => - \prdata_RNO_21[5]\); - - \r.haddr_RNIQKO8[3]\ : OR2A - port map(A => N_770, B => N_90, Y => - \prdata_1_i_0_o2_0[11]\); - - \r.pwdata_0[6]\ : DFN1E0 - port map(D => hwdata(6), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[6]\); - - \r.prdata_RNO_6[1]\ : OR3B - port map(A => N_85, B => N_86, C => N_763, Y => N_628); - - \r.prdata_RNO_2[6]\ : AO1C - port map(A => N_156, B => frame, C => - \prdata_1_i_0_a11_8_3[6]\, Y => N_604_i); - - \r.prdata_RNO_9[15]\ : OR2B - port map(A => prdata_3_13, B => N_752, Y => N_693); - - \r.prdata_RNO_6[4]\ : OR3C - port map(A => \prdata_1_i_0_a11_5_1[4]\, B => - \prdata_1_i_0_a11_5_0[4]\, C => N_762, Y => N_621_i); - - \r.prdata_RNO_15[7]\ : AOI1B - port map(A => rdata_iv_0_a2_3_0(7), B => rdata_4_sqmuxa, C - => N_223, Y => \prdata_1_i_0_a11_7_1[7]\); - - \r.pwdata[21]\ : DFN1E0 - port map(D => hwdata(21), CLK => lclk_c, E => N_12_0_0, Q - => pwdata(21)); - - \r.prdata_RNO[5]\ : AOI1B - port map(A => \prdata_1_i_0_a11_8_3[5]\, B => parerr_m, C - => \prdata_1_i_0_8[5]\, Y => N_63_i_0); - - \r.prdata[6]\ : DFN1 - port map(D => N_65_i_0, CLK => lclk_c, Q => hrdata(6)); - - \r.penable\ : DFN1 - port map(D => penable_RNO, CLK => lclk_c, Q => \penable\); - - \r.prdata_RNO_20[7]\ : OR2A - port map(A => N_752_0, B => prdata_1_7, Y => - \prdata_RNO_20[7]\); - - \r.prdata_RNO_12[10]\ : NOR2B - port map(A => \prdata_RNO_14[10]\, B => \prdata_RNO_15[10]\, - Y => \prdata_1_i_0_0[10]\); - - \r.prdata[16]\ : DFN1 - port map(D => \prdata_1[16]\, CLK => lclk_c, Q => - hrdata(16)); - - \r.haddr_RNI3SB72_0[8]\ : NOR2 - port map(A => \N_749\, B => N_745, Y => N_751_0); - - \r.pwdata_1[1]\ : DFN1E0 - port map(D => hwdata(1), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_1_0); - - \r.prdata_RNO_20[0]\ : NOR2 - port map(A => \paddr[8]\, B => \N_116\, Y => - \prdata_1_i_0_a11_0[0]\); - - \r.prdata[25]\ : DFN1 - port map(D => \prdata_1[25]\, CLK => lclk_c, Q => - hrdata(25)); - - \r.haddr_RNI7P9D_1[10]\ : NOR2 - port map(A => \paddr[11]\, B => \paddr[10]\, Y => \N_773\); - - \r.prdata_RNO_7[0]\ : NOR3C - port map(A => readdata_9_0, B => \prdata_1_i_0_a11_3_1[0]\, - C => reload_m_0_d0, Y => \prdata_1_i_0_a11_3_3[0]\); - - \r.prdata_RNO_12[12]\ : AO1A - port map(A => N_6455_0, B => rambanksz_3, C => N_778_i, Y - => \prdata_RNO_12[12]\); - - \r.state_RNI4KU3_0[0]\ : OR2B - port map(A => \pwrite\, B => \state[0]\, Y => N_12_0_0); - - \r.prdata_RNO_6[14]\ : OR2B - port map(A => prdata_3_12, B => N_755, Y => N_204); - - \r.penable_RNO\ : NOR3A - port map(A => rstn, B => cfgsel2, C => N_199, Y => - penable_RNO); - - \r.pwdata_0[2]\ : DFN1E0 - port map(D => hwdata(2), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[2]\); - - \r.prdata_RNO_5[16]\ : OR3B - port map(A => N_766, B => N_155_i, C => N_760, Y => N_714); - - \r.prdata_RNO_5[20]\ : NOR3C - port map(A => N_708, B => N_789, C => N_760, Y => - \prdata_1_i_0_1[20]\); - - \r.prdata_RNO_11[2]\ : OR2B - port map(A => prdata_2_2, B => N_752, Y => N_739); - - \r.prdata_RNO_4[2]\ : AOI1B - port map(A => prdata(2), B => N_762, C => N_734, Y => - \prdata_1_0_0_3[2]\); - - \r.psel_RNITJ1T1\ : NOR3C - port map(A => \prdata_1_i_0_o2_1_4[0]\, B => - \prdata_1_i_0_o2_1_5[0]\, C => psel, Y => \N_769\); - - \r.prdata_RNO_1[7]\ : AO1C - port map(A => readdata56, B => reload_0(7), C => - \prdata_1_i_0_a11_3_3[7]\, Y => N_590_i); - - \r.prdata[10]\ : DFN1 - port map(D => N_106_i_0, CLK => lclk_c, Q => hrdata(10)); - - \r.prdata_RNO_22[5]\ : OR2A - port map(A => un1_grgpio0_0, B => readdata55_3, Y => - \un1_grgpio0_m[69]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_work_leon3mp_wfp_rtl_0 is - - port( clk : in std_logic; - address : in std_logic_vector(7 downto 0); - datain : in std_logic_vector(7 downto 0); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic; - write : in std_logic - ); - -end proasic3_syncram_work_leon3mp_wfp_rtl_0; - -architecture DEF_ARCH of proasic3_syncram_work_leon3mp_wfp_rtl_0 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ3 is - - port( hrdata : out std_logic_vector(15 downto 8); - hwdata : in std_logic_vector(15 downto 8); - haddr_1 : in std_logic_vector(7 downto 0); - N_17 : in std_logic; - lclk_c : in std_logic; - N_18 : in std_logic; - N_22 : in std_logic; - N_14 : in std_logic - ); - -end syncramZ3; - -architecture DEF_ARCH of syncramZ3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_0 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_8, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_0 - port map(clk => lclk_c, address(7) => haddr_1(7), - address(6) => haddr_1(6), address(5) => haddr_1(5), - address(4) => haddr_1(4), address(3) => haddr_1(3), - address(2) => haddr_1(2), address(1) => haddr_1(1), - address(0) => haddr_1(0), datain(7) => hwdata(15), - datain(6) => hwdata(14), datain(5) => hwdata(13), - datain(4) => hwdata(12), datain(3) => hwdata(11), - datain(2) => hwdata(10), datain(1) => hwdata(9), - datain(0) => hwdata(8), dataout(7) => hrdata(15), - dataout(6) => hrdata(14), dataout(5) => hrdata(13), - dataout(4) => hrdata(12), dataout(3) => hrdata(11), - dataout(2) => hrdata(10), dataout(1) => hrdata(9), - dataout(0) => hrdata(8), enable => N_17, write => N_8); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO\ : NOR3B - port map(A => N_14, B => N_22, C => N_18, Y => N_8); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ3_3 is - - port( hrdata : out std_logic_vector(7 downto 0); - hwdata : in std_logic_vector(7 downto 0); - haddr_1 : in std_logic_vector(7 downto 0); - N_17 : in std_logic; - lclk_c : in std_logic; - N_18 : in std_logic; - N_21 : in std_logic; - N_14 : in std_logic - ); - -end syncramZ3_3; - -architecture DEF_ARCH of syncramZ3_3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_0 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_6, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_0 - port map(clk => lclk_c, address(7) => haddr_1(7), - address(6) => haddr_1(6), address(5) => haddr_1(5), - address(4) => haddr_1(4), address(3) => haddr_1(3), - address(2) => haddr_1(2), address(1) => haddr_1(1), - address(0) => haddr_1(0), datain(7) => hwdata(7), - datain(6) => hwdata(6), datain(5) => hwdata(5), datain(4) - => hwdata(4), datain(3) => hwdata(3), datain(2) => - hwdata(2), datain(1) => hwdata(1), datain(0) => hwdata(0), - dataout(7) => hrdata(7), dataout(6) => hrdata(6), - dataout(5) => hrdata(5), dataout(4) => hrdata(4), - dataout(3) => hrdata(3), dataout(2) => hrdata(2), - dataout(1) => hrdata(1), dataout(0) => hrdata(0), enable - => N_17, write => N_6); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO\ : NOR3B - port map(A => N_14, B => N_21, C => N_18, Y => N_6); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ3_2 is - - port( hrdata : out std_logic_vector(31 downto 24); - hwdata : in std_logic_vector(31 downto 24); - haddr_1 : in std_logic_vector(7 downto 0); - N_17 : in std_logic; - lclk_c : in std_logic; - N_19 : in std_logic; - N_22 : in std_logic; - N_14 : in std_logic - ); - -end syncramZ3_2; - -architecture DEF_ARCH of syncramZ3_2 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_0 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_0 - port map(clk => lclk_c, address(7) => haddr_1(7), - address(6) => haddr_1(6), address(5) => haddr_1(5), - address(4) => haddr_1(4), address(3) => haddr_1(3), - address(2) => haddr_1(2), address(1) => haddr_1(1), - address(0) => haddr_1(0), datain(7) => hwdata(31), - datain(6) => hwdata(30), datain(5) => hwdata(29), - datain(4) => hwdata(28), datain(3) => hwdata(27), - datain(2) => hwdata(26), datain(1) => hwdata(25), - datain(0) => hwdata(24), dataout(7) => hrdata(31), - dataout(6) => hrdata(30), dataout(5) => hrdata(29), - dataout(4) => hrdata(28), dataout(3) => hrdata(27), - dataout(2) => hrdata(26), dataout(1) => hrdata(25), - dataout(0) => hrdata(24), enable => N_17, write => N_12); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO\ : NOR3B - port map(A => N_14, B => N_22, C => N_19, Y => N_12); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ3_1 is - - port( hrdata : out std_logic_vector(23 downto 16); - hwdata : in std_logic_vector(23 downto 16); - haddr_1 : in std_logic_vector(7 downto 0); - N_17 : in std_logic; - lclk_c : in std_logic; - N_19 : in std_logic; - N_21 : in std_logic; - N_14 : in std_logic - ); - -end syncramZ3_1; - -architecture DEF_ARCH of syncramZ3_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_0 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_10, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_0 - port map(clk => lclk_c, address(7) => haddr_1(7), - address(6) => haddr_1(6), address(5) => haddr_1(5), - address(4) => haddr_1(4), address(3) => haddr_1(3), - address(2) => haddr_1(2), address(1) => haddr_1(1), - address(0) => haddr_1(0), datain(7) => hwdata(23), - datain(6) => hwdata(22), datain(5) => hwdata(21), - datain(4) => hwdata(20), datain(3) => hwdata(19), - datain(2) => hwdata(18), datain(1) => hwdata(17), - datain(0) => hwdata(16), dataout(7) => hrdata(23), - dataout(6) => hrdata(22), dataout(5) => hrdata(21), - dataout(4) => hrdata(20), dataout(3) => hrdata(19), - dataout(2) => hrdata(18), dataout(1) => hrdata(17), - dataout(0) => hrdata(16), enable => N_17, write => N_10); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO\ : NOR3B - port map(A => N_14, B => N_21, C => N_19, Y => N_10); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbram is - - port( hwdata : in std_logic_vector(31 downto 0); - hrdata : out std_logic_vector(31 downto 0); - hsize : in std_logic_vector(1 downto 0); - iosn : in std_logic_vector(93 to 93); - htrans : in std_logic_vector(1 to 1); - iosn_1 : in std_logic_vector(93 to 93); - haddr : in std_logic_vector(9 downto 0); - lclk_c : in std_logic; - un315_ioen_NE : in std_logic; - hready : out std_logic; - hwrite_1 : in std_logic; - rstn : in std_logic - ); - -end ahbram; - -architecture DEF_ARCH of ahbram is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ3 - port( hrdata : out std_logic_vector(15 downto 8); - hwdata : in std_logic_vector(15 downto 8) := (others => 'U'); - haddr_1 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_17 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_18 : in std_logic := 'U'; - N_22 : in std_logic := 'U'; - N_14 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component syncramZ3_3 - port( hrdata : out std_logic_vector(7 downto 0); - hwdata : in std_logic_vector(7 downto 0) := (others => 'U'); - haddr_1 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_17 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_18 : in std_logic := 'U'; - N_21 : in std_logic := 'U'; - N_14 : in std_logic := 'U' - ); - end component; - - component syncramZ3_2 - port( hrdata : out std_logic_vector(31 downto 24); - hwdata : in std_logic_vector(31 downto 24) := (others => 'U'); - haddr_1 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_17 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_19 : in std_logic := 'U'; - N_22 : in std_logic := 'U'; - N_14 : in std_logic := 'U' - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ3_1 - port( hrdata : out std_logic_vector(23 downto 16); - hwdata : in std_logic_vector(23 downto 16) := (others => 'U'); - haddr_1 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_17 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_19 : in std_logic := 'U'; - N_21 : in std_logic := 'U'; - N_14 : in std_logic := 'U' - ); - end component; - - signal hready_RNO, hsel, hwrite, hwrite_RNO, hwrite_3, - \haddr_1[1]\, \addr[3]\, hwrite_0, \haddr_1[2]\, - \addr[4]\, \haddr_1[3]\, \addr[5]\, \haddr_1[4]\, - \addr[6]\, \haddr_1[5]\, \addr[7]\, \haddr_1[6]\, - \addr[8]\, \haddr_1[7]\, \addr[9]\, \haddr_1[0]\, - \addr[2]\, N_17, hsel_1, hsel_2, hsel_0, N_21, \size[0]\, - \size[1]\, \addr[0]\, N_22, N_14, N_18, \addr[1]\, N_19, - \hready\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : syncramZ3 - Use entity work.syncramZ3(DEF_ARCH); - for all : syncramZ3_3 - Use entity work.syncramZ3_3(DEF_ARCH); - for all : syncramZ3_2 - Use entity work.syncramZ3_2(DEF_ARCH); - for all : syncramZ3_1 - Use entity work.syncramZ3_1(DEF_ARCH); -begin - - hready <= \hready\; - - \r.addr_RNI9NSIJ[7]\ : MX2 - port map(A => haddr(7), B => \addr[7]\, S => hwrite_0, Y - => \haddr_1[5]\); - - \r.hready_RNI8IE2\ : OR2A - port map(A => \hready\, B => hwrite, Y => hwrite_0); - - \r.addr_RNIJ1QKJ[8]\ : MX2 - port map(A => haddr(8), B => \addr[8]\, S => hwrite_0, Y - => \haddr_1[6]\); - - \r.addr[6]\ : DFN1E1 - port map(D => haddr(6), CLK => lclk_c, E => iosn(93), Q => - \addr[6]\); - - \r.addr[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => iosn(93), Q => - \addr[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.addr_RNI27LTK[3]\ : MX2 - port map(A => haddr(3), B => \addr[3]\, S => hwrite_0, Y - => \haddr_1[1]\); - - \r.size[0]\ : DFN1E1 - port map(D => hsize(0), CLK => lclk_c, E => iosn(93), Q => - \size[0]\); - - \r.addr[3]\ : DFN1E1 - port map(D => haddr(3), CLK => lclk_c, E => iosn(93), Q => - \addr[3]\); - - \r.addr[4]\ : DFN1E1 - port map(D => haddr(4), CLK => lclk_c, E => iosn(93), Q => - \addr[4]\); - - \comb.v.hsel_2\ : NOR2A - port map(A => htrans(1), B => un315_ioen_NE, Y => hsel_2); - - \r.addr_RNIMME2_0[1]\ : NOR2 - port map(A => \size[1]\, B => \addr[1]\, Y => N_18); - - \r.addr[0]\ : DFN1E1 - port map(D => haddr(0), CLK => lclk_c, E => iosn(93), Q => - \addr[0]\); - - \r.hsel\ : DFN1E1 - port map(D => hsel_2, CLK => lclk_c, E => iosn(93), Q => - hsel_0); - - \r.addr_RNI3JSIJ[6]\ : MX2 - port map(A => haddr(6), B => \addr[6]\, S => hwrite_0, Y - => \haddr_1[4]\); - - \r.hsel_RNI91NO19\ : NOR2A - port map(A => hsel_1, B => hwrite_1, Y => hsel); - - \r.addr_RNI2FLVK[4]\ : MX2 - port map(A => haddr(4), B => \addr[4]\, S => hwrite_0, Y - => \haddr_1[2]\); - - \r.addr_RNI0A9OK[2]\ : MX2 - port map(A => haddr(2), B => \addr[2]\, S => hwrite_0, Y - => \haddr_1[0]\); - - \r.addr_RNIHGA4_0[0]\ : OR3 - port map(A => \size[0]\, B => \size[1]\, C => \addr[0]\, Y - => N_21); - - \ra.1.aram\ : syncramZ3 - port map(hrdata(15) => hrdata(15), hrdata(14) => hrdata(14), - hrdata(13) => hrdata(13), hrdata(12) => hrdata(12), - hrdata(11) => hrdata(11), hrdata(10) => hrdata(10), - hrdata(9) => hrdata(9), hrdata(8) => hrdata(8), - hwdata(15) => hwdata(15), hwdata(14) => hwdata(14), - hwdata(13) => hwdata(13), hwdata(12) => hwdata(12), - hwdata(11) => hwdata(11), hwdata(10) => hwdata(10), - hwdata(9) => hwdata(9), hwdata(8) => hwdata(8), - haddr_1(7) => \haddr_1[7]\, haddr_1(6) => \haddr_1[6]\, - haddr_1(5) => \haddr_1[5]\, haddr_1(4) => \haddr_1[4]\, - haddr_1(3) => \haddr_1[3]\, haddr_1(2) => \haddr_1[2]\, - haddr_1(1) => \haddr_1[1]\, haddr_1(0) => \haddr_1[0]\, - N_17 => N_17, lclk_c => lclk_c, N_18 => N_18, N_22 => - N_22, N_14 => N_14); - - \r.addr[5]\ : DFN1E1 - port map(D => haddr(5), CLK => lclk_c, E => iosn(93), Q => - \addr[5]\); - - GND_i : GND - port map(Y => \GND\); - - \r.size[1]\ : DFN1E1 - port map(D => hsize(1), CLK => lclk_c, E => iosn(93), Q => - \size[1]\); - - \ra.0.aram\ : syncramZ3_3 - port map(hrdata(7) => hrdata(7), hrdata(6) => hrdata(6), - hrdata(5) => hrdata(5), hrdata(4) => hrdata(4), hrdata(3) - => hrdata(3), hrdata(2) => hrdata(2), hrdata(1) => - hrdata(1), hrdata(0) => hrdata(0), hwdata(7) => hwdata(7), - hwdata(6) => hwdata(6), hwdata(5) => hwdata(5), hwdata(4) - => hwdata(4), hwdata(3) => hwdata(3), hwdata(2) => - hwdata(2), hwdata(1) => hwdata(1), hwdata(0) => hwdata(0), - haddr_1(7) => \haddr_1[7]\, haddr_1(6) => \haddr_1[6]\, - haddr_1(5) => \haddr_1[5]\, haddr_1(4) => \haddr_1[4]\, - haddr_1(3) => \haddr_1[3]\, haddr_1(2) => \haddr_1[2]\, - haddr_1(1) => \haddr_1[1]\, haddr_1(0) => \haddr_1[0]\, - N_17 => N_17, lclk_c => lclk_c, N_18 => N_18, N_21 => - N_21, N_14 => N_14); - - \ra.3.aram\ : syncramZ3_2 - port map(hrdata(31) => hrdata(31), hrdata(30) => hrdata(30), - hrdata(29) => hrdata(29), hrdata(28) => hrdata(28), - hrdata(27) => hrdata(27), hrdata(26) => hrdata(26), - hrdata(25) => hrdata(25), hrdata(24) => hrdata(24), - hwdata(31) => hwdata(31), hwdata(30) => hwdata(30), - hwdata(29) => hwdata(29), hwdata(28) => hwdata(28), - hwdata(27) => hwdata(27), hwdata(26) => hwdata(26), - hwdata(25) => hwdata(25), hwdata(24) => hwdata(24), - haddr_1(7) => \haddr_1[7]\, haddr_1(6) => \haddr_1[6]\, - haddr_1(5) => \haddr_1[5]\, haddr_1(4) => \haddr_1[4]\, - haddr_1(3) => \haddr_1[3]\, haddr_1(2) => \haddr_1[2]\, - haddr_1(1) => \haddr_1[1]\, haddr_1(0) => \haddr_1[0]\, - N_17 => N_17, lclk_c => lclk_c, N_19 => N_19, N_22 => - N_22, N_14 => N_14); - - \r.hwrite\ : DFN1 - port map(D => hwrite_RNO, CLK => lclk_c, Q => hwrite); - - \r.hwrite_RNINTSGA8\ : OR2 - port map(A => hwrite, B => hsel_1, Y => N_17); - - \r.addr_RNI1LPKJ[5]\ : MX2 - port map(A => haddr(5), B => \addr[5]\, S => hwrite_0, Y - => \haddr_1[3]\); - - \r.addr[7]\ : DFN1E1 - port map(D => haddr(7), CLK => lclk_c, E => iosn(93), Q => - \addr[7]\); - - \r.addr[1]\ : DFN1E1 - port map(D => haddr(1), CLK => lclk_c, E => iosn(93), Q => - \addr[1]\); - - \r.addr_RNIMME2[1]\ : NOR2A - port map(A => \addr[1]\, B => \size[1]\, Y => N_19); - - \r.hwrite_RNO_0\ : MX2C - port map(A => hwrite, B => hsel_2, S => iosn_1(93), Y => - hwrite_3); - - \r.hready_RNO\ : OR3C - port map(A => hsel, B => hwrite, C => rstn, Y => hready_RNO); - - \r.addr_RNIP5QKJ[9]\ : MX2 - port map(A => haddr(9), B => \addr[9]\, S => hwrite_0, Y - => \haddr_1[7]\); - - \r.hsel_RNIRBHFA8\ : MX2 - port map(A => hsel_0, B => hsel_2, S => iosn_1(93), Y => - hsel_1); - - \r.size_RNIL535[0]\ : AOI1B - port map(A => \size[1]\, B => \size[0]\, C => hwrite, Y => - N_14); - - \r.hready\ : DFN1 - port map(D => hready_RNO, CLK => lclk_c, Q => \hready\); - - \r.addr_RNIHGA4[0]\ : OR3A - port map(A => \addr[0]\, B => \size[0]\, C => \size[1]\, Y - => N_22); - - \r.hwrite_RNO\ : NOR3A - port map(A => rstn, B => hsel, C => hwrite_3, Y => - hwrite_RNO); - - \r.addr[9]\ : DFN1E1 - port map(D => haddr(9), CLK => lclk_c, E => iosn(93), Q => - \addr[9]\); - - \r.addr[8]\ : DFN1E1 - port map(D => haddr(8), CLK => lclk_c, E => iosn(93), Q => - \addr[8]\); - - \ra.2.aram\ : syncramZ3_1 - port map(hrdata(23) => hrdata(23), hrdata(22) => hrdata(22), - hrdata(21) => hrdata(21), hrdata(20) => hrdata(20), - hrdata(19) => hrdata(19), hrdata(18) => hrdata(18), - hrdata(17) => hrdata(17), hrdata(16) => hrdata(16), - hwdata(23) => hwdata(23), hwdata(22) => hwdata(22), - hwdata(21) => hwdata(21), hwdata(20) => hwdata(20), - hwdata(19) => hwdata(19), hwdata(18) => hwdata(18), - hwdata(17) => hwdata(17), hwdata(16) => hwdata(16), - haddr_1(7) => \haddr_1[7]\, haddr_1(6) => \haddr_1[6]\, - haddr_1(5) => \haddr_1[5]\, haddr_1(4) => \haddr_1[4]\, - haddr_1(3) => \haddr_1[3]\, haddr_1(2) => \haddr_1[2]\, - haddr_1(1) => \haddr_1[1]\, haddr_1(0) => \haddr_1[0]\, - N_17 => N_17, lclk_c => lclk_c, N_19 => N_19, N_21 => - N_21, N_14 => N_14); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbrom is - - port( hrdata_12 : out std_logic; - hrdata_10 : out std_logic; - hrdata_11 : out std_logic; - hrdata_2 : out std_logic; - hrdata_15 : out std_logic; - hrdata_22 : out std_logic; - hrdata_14 : out std_logic; - hrdata_28 : out std_logic; - hrdata_4 : out std_logic; - hrdata_23 : out std_logic; - hrdata_1 : out std_logic; - hrdata_0 : out std_logic; - hrdata_3 : out std_logic; - hrdata_21 : out std_logic; - hrdata_27 : out std_logic; - hrdata_25 : out std_logic; - hrdata_9 : out std_logic; - hrdata_30 : out std_logic; - hrdata_16 : out std_logic; - hrdata_7 : out std_logic; - hrdata_17 : out std_logic; - hrdata_19 : out std_logic; - hrdata_6 : out std_logic; - hrdata_18 : out std_logic; - hrdata_29 : out std_logic; - hrdata_5 : out std_logic; - hrdata_8 : out std_logic; - hrdata_13 : out std_logic; - hrdata_26 : out std_logic; - haddr : in std_logic_vector(9 downto 2); - N_95_i_0 : out std_logic; - N_90_i_0 : out std_logic; - N_103_i_0 : out std_logic; - lclk_c : in std_logic - ); - -end ahbrom; - -architecture DEF_ARCH of ahbrom is - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI4 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component ZOR3I - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \addr_0[2]_net_1\, \addr_0[3]_net_1\, - \addr_0[4]_net_1\, \addr_0[5]_net_1\, \addr_0[6]_net_1\, - \addr_0[9]_net_1\, N_430_0, \addr[7]_net_1\, - \addr[8]_net_1\, N_491_i, N_114, N_133_i, N_443, N_236, - \romdata_0_8[26]\, \romdata_0_9[26]\, N_289, - \romdata_0_8[13]\, N_297, \romdata_0_a19_5_0[14]\, - \romdata_0_RNO_1[26]_net_1\, N_392, \romdata_0_7[26]\, - \romdata_0_6[26]\, \romdata_0_7[13]\, - \romdata_0_RNO_2[13]_net_1\, \romdata_0_6[13]\, - \romdata_0_5[13]\, \romdata_0_6[21]\, \romdata_0_4[21]\, - \romdata_0_2[21]\, N_344, \romdata_0_2[13]\, N_290, N_285, - N_286_i, N_281, N_287, N_438, \romdata_0_a19_2_0[13]\, - \romdata_0_1[13]\, N_282, N_288, N_284, \romdata_0_3[3]\, - \romdata_0_1[3]\, \romdata_0_0[3]\, N_525, N_256_1, N_160, - N_494, N_117_i, N_469, N_250, \romdata_0_0[11]\, N_278, - N_134, \romdata_0_7[1]\, N_495, N_259, N_342, - \romdata_0_5[1]\, \romdata_0_a19_5_0[1]\, N_472, N_240, - \romdata_0_4[1]\, \romdata_0_2[1]\, \romdata_0_1[1]\, - N_243, N_242, N_245, N_247, N_241, N_244, - \romdata_0_4[19]\, \romdata_0_3[19]\, N_316, N_315, N_317, - \romdata_0_2[19]\, N_313, \addr_0_RNIP7M91[5]_net_1\, - N_302, \romdata_0_6[0]\, \romdata_0_3[0]\, - \romdata_0_2[0]\, \romdata_0_4[0]\, N_235, N_234, N_238, - \romdata_0_a19_1_0[0]\, N_343_1, N_232, N_237, N_239, - \romdata_0_0[6]\, N_264, N_265, \romdata_0_0[5]\, N_270, - N_439, N_262, \romdata_0_6[2]\, N_248, \romdata_0_2[2]\, - N_148, \romdata_0_5[2]\, N_255, N_251, \romdata_0_0[2]\, - N_253, N_249, \romdata_0_a19_5_0[2]\, N_482, N_252, - \romdata_0_8[21]\, N_345, \romdata_0_3[21]\, N_336, - \romdata_0_7[21]\, N_105, N_465, N_338, \romdata_0_0[21]\, - N_341, \romdata_0_a19_0_1[21]\, N_343, N_463, - \romdata_0_6[15]\, N_479, N_304, \romdata_0_5[15]\, N_301, - \romdata_0_1[15]\, \romdata_0_4[15]\, N_258, N_300, N_303, - \romdata_0_2[4]\, N_260, N_515, \romdata_0_1[4]\, N_261, - \romdata_0_7[23]\, \romdata_0_4[23]\, \romdata_0_3[23]\, - \romdata_0_6[23]\, N_509, N_471, N_351, N_352, N_347, - \romdata_0_0[23]\, N_354, N_156, \romdata_0_a19_1[23]\, - \romdata_0_0[7]\, N_268, N_267, N_379, \romdata_0_2[26]\, - \romdata_0_5[26]\, N_523, N_390, N_153_i, - \romdata_0_1[26]\, N_393, N_387, N_388, N_481, N_437, - N_385, \romdata_0_8[14]\, \romdata_0_4[14]\, N_294, - \romdata_0_5[14]\, N_292, N_291, N_299, \romdata_0_1[14]\, - N_298, N_296, N_293, N_295, \romdata_0_1[9]\, N_276, - \romdata_0_o19_0_0[5]\, N_457, \romdata_0_1[18]\, N_306, - N_312, N_311, \romdata_0_11[25]\, \romdata_0_5[25]\, - N_373, \romdata_0_9[25]\, \romdata_0_10[25]\, - \romdata_0_4[25]\, \romdata_0_7[25]\, N_512, N_448, N_384, - N_383, N_377, N_375, \romdata_0_1[25]\, \romdata_0_0[25]\, - N_380, \romdata_0_a19_9_0[25]\, N_428, N_378, - \romdata_0_a19_1[25]\, N_108, N_376, \romdata_0_1[8]\, - N_138, N_271, \romdata_0_0[8]\, N_516, \romdata_i_16[20]\, - \romdata_i_9[20]\, N_485, \romdata_i_15[20]\, - \romdata_i_8[20]\, N_328, N_334, \romdata_i_14[20]\, - \romdata_i_6[20]\, \romdata_i_11[20]\, N_493, - \addr_0_RNI1PM21[4]_net_1\, N_332, N_331, - \romdata_i_a19_0[20]\, N_329, \romdata_i_2[20]\, N_322, - \romdata_i_4[20]\, N_323, N_330, N_320, N_326, N_324, - N_327, N_319, \addr_RNIGR5M[3]_net_1\, - \addr_RNIER5M_0[9]_net_1\, \romdata_i_15[31]\, - \romdata_i_10[31]\, \romdata_i_9[31]\, N_427, - \romdata_i_12[31]\, N_414, \romdata_i_4[31]\, - \romdata_i_8[31]\, \romdata_i_11[31]\, - \romdata_i_a19_5_0[31]\, N_436, N_412, - \romdata_i_a19_11_0[31]\, \romdata_i_6[31]\, - \romdata_i_2[31]\, N_422, N_425, N_170, N_132, N_417, - N_420, N_421, N_426, N_362, \romdata_i_0[31]\, - \romdata_i_a19_3_1[31]\, N_110, N_419, - \romdata_i_a19_10_0[31]\, N_415, \romdata_0_1[22]\, N_348, - \romdata_0_6[28]\, \romdata_0_2[28]\, N_401, - \romdata_0_5[28]\, N_405, \romdata_0_1[28]\, - \addr_RNIMM7F1[9]_net_1\, N_442, N_398, N_403, N_402, - N_508, \romdata_0_a19_0[11]\, N_109, - \romdata_0_a19_0[21]\, N_136_i, \romdata_i_14[24]\, - \romdata_i_8[24]\, N_364, N_369, \romdata_i_13[24]\, - N_358, \romdata_i_7[24]\, N_367, \romdata_i_12[24]\, - \romdata_i_6[24]\, \romdata_i_5[24]\, N_519, N_489, N_359, - N_370, N_360, \romdata_i_3[24]\, N_361, N_355, N_371, - \romdata_i_a19_10_0[24]\, N_368, N_356, \romdata_i_0[24]\, - \romdata_i_a19_1_1[24]\, N_131, N_363, \romdata_0_0[30]\, - \romdata_0_a19_0_0[30]\, N_410, \romdata_0_a19_1_0[21]\, - \romdata_0_1[17]\, N_172, \romdata_0_0[17]\, N_127, - \romdata_0_a19_1_0[17]\, \addr_0_RNIQ9T21[9]_net_1\, - \romdata_0_a19_3_0[8]\, N_445, \romdata_0_3[27]\, N_112, - \romdata_0_1[27]\, N_397, \romdata_0_0[27]\, - \romdata_0_a19_0_0[27]\, \romdata_0_a19_2_1[28]\, N_399, - \romdata_0_a19_2_0[19]\, \romdata_0_1[29]\, - \romdata_0_a19_0[29]\, \romdata_0_0[29]\, N_450, N_503, - N_407, \romdata_0_o19_0[14]\, N_461, - \romdata_0_a19_0[18]\, \romdata_0_a19_11_0[25]\, N_124, - \romdata_0_a19_0_0[0]\, N_135, \romdata_i_a19_0[31]\, - N_449, N_446, N_107, \romdata_0_a19_0[19]\, N_207, - \romdata_0_a19_0_0[23]\, N_116, \romdata_i_a19_15_0[24]\, - N_500, \romdata_0_a19_3_0[13]\, \romdata_0_a19_0_0[17]\, - N_151, \romdata_0_a19_5_0[21]\, \romdata_0_a19_5_0[25]\, - N_480, \romdata_i_a19_0[24]\, \romdata_i_a19_6_0[31]\, - N_468, \romdata_0_a19_0[25]\, N_499, - \romdata_0_a19_2_0[28]\, N_166, \romdata_i_a19_2_0[31]\, - N_122, \romdata_i_a19_4_0[20]\, \romdata_0_a19_1_0[28]\, - \romdata_i_a19_0_0[24]\, N_273, N_263, N_196, N_185, - N_488, N_408, N_310, N_440, N_184, N_496, N_266, N_441, - N_451, N_511, N_431, N_507, N_453, N_505, N_126, N_470, - N_484, N_277, N_274, N_143, N_275, N_374, N_149_i_i_0, - N_478, \addr_RNIMM7F1[4]_net_1\, N_257, - \addr_RNIPMPD1[4]_net_1\, N_155_i, N_197_i, N_404, - N_291_1, N_293_1, N_16427_tz, N_459, - \addr_0_RNI7CUK_0[6]_net_1\, N_198_i, \addr[2]_net_1\, - N_162_i_i_0, N_400_1, N_106_i, \addr_0_RNIIC2I[4]_net_1\, - N_514, N_279, N_490, \addr_0_RNIP9101_1[6]_net_1\, N_473, - \addr_RNI2ANR_0[3]_net_1\, N_433, N_475, N_476, N_171, - N_432, N_452, \addr[9]_net_1\, N_227, N_130, - \addr[4]_net_1\, \addr[6]_net_1\, N_430, N_497, - \addr_RNIMM7F1_0[2]_net_1\, \romdata_0_RNO_5[13]_net_1\, - N_492, N_502, \addr_RNI7R5M[3]_net_1\, \addr[3]_net_1\, - \addr[5]_net_1\, N_460, N_462, N_454, N_455, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - - \addr_0_RNI5KOR1[9]\ : NOR2A - port map(A => N_397, B => N_398, Y => \romdata_0_1[27]\); - - \addr_RNIMR5M_0[6]\ : OR2 - port map(A => N_449, B => N_431, Y => N_503); - - \addr_RNIER5M[6]\ : OR2B - port map(A => \addr[6]_net_1\, B => N_459, Y => N_364); - - \addr_0_RNIBM8G6[6]\ : OR3C - port map(A => N_275, B => \romdata_0_1[9]\, C => N_274, Y - => hrdata_9); - - \addr_RNIJR5M[9]\ : OR2 - port map(A => N_431, B => N_110, Y => N_475); - - \addr_0_RNIU7881[6]\ : OR3B - port map(A => N_451, B => \addr_0[6]_net_1\, C => N_438, Y - => N_299); - - \addr_0_RNIJUFN2[6]\ : OA1A - port map(A => \romdata_0_a19_0_1[21]\, B => N_438, C => - N_343, Y => \romdata_0_2[21]\); - - \addr_0_RNIBTUD[2]\ : NOR2A - port map(A => \addr_0[3]_net_1\, B => \addr_0[2]_net_1\, Y - => \romdata_0_a19_5_0[25]\); - - \addr_RNIT7Q61_0[7]\ : OR3A - port map(A => N_468, B => N_143, C => N_437, Y => N_425); - - \addr_RNIO44Q6[4]\ : NOR3C - port map(A => N_315, B => N_317, C => \romdata_0_2[19]\, Y - => \romdata_0_3[19]\); - - \addr_RNIFCKG[6]\ : NOR2A - port map(A => \addr[6]_net_1\, B => N_126, Y => N_482); - - \addr_RNIMM7F1_0[2]\ : NOR2A - port map(A => N_511, B => N_471, Y => - \addr_RNIMM7F1_0[2]_net_1\); - - \addr_RNILR5M[5]\ : NOR2A - port map(A => \addr[5]_net_1\, B => N_430, Y => N_343_1); - - \addr_0_RNIV95T[2]\ : OR3A - port map(A => N_108, B => N_437, C => \addr_0[2]_net_1\, Y - => N_453); - - \addr_0_RNIIL1NB[2]\ : OR2A - port map(A => \romdata_0_4[19]\, B => N_134, Y => hrdata_19); - - \addr_0_RNIGM3I1[4]\ : OR3A - port map(A => N_484, B => N_109, C => N_114, Y => N_277); - - \addr_0_RNIERJN[4]\ : OA1C - port map(A => \addr_0[4]_net_1\, B => \addr[7]_net_1\, C - => N_138, Y => \romdata_i_a19_0[20]\); - - \addr_RNI1P811[7]\ : OR2B - port map(A => N_480, B => N_256_1, Y => N_370); - - \addr_0_RNIF3EU1[5]\ : AO1B - port map(A => N_433, B => N_432, C => \addr_0[5]_net_1\, Y - => N_294); - - \romdata_0_RNO_1[13]\ : AND2 - port map(A => \romdata_0_6[13]\, B => \romdata_0_5[13]\, Y - => \romdata_0_7[13]\); - - \addr_RNI1ID52[9]\ : OA1A - port map(A => \romdata_0_a19_9_0[25]\, B => N_428, C => - N_378, Y => \romdata_0_1[25]\); - - \addr_RNINT2B_0[5]\ : OR2A - port map(A => \addr[5]_net_1\, B => \addr[6]_net_1\, Y => - N_437); - - \addr_0_RNICCUK[9]\ : OR2A - port map(A => \addr_0[9]_net_1\, B => N_151, Y => - \romdata_0_a19_0_0[17]\); - - \addr[7]\ : DFN1 - port map(D => haddr(7), CLK => lclk_c, Q => \addr[7]_net_1\); - - \addr_RNIK6SS3[2]\ : NOR3B - port map(A => N_258, B => N_260, C => N_515, Y => - \romdata_0_2[4]\); - - \addr_0_RNIU7881_0[6]\ : OR2B - port map(A => \addr_0[6]_net_1\, B => N_514, Y => N_275); - - \addr_0_RNIMM7F1_0[5]\ : OR3 - port map(A => N_116, B => N_430_0, C => N_442, Y => N_271); - - \addr_RNIA18Q4[9]\ : OR3 - port map(A => N_306, B => N_312, C => N_311, Y => - \romdata_0_1[18]\); - - \addr_0_RNIU9101[9]\ : OR3A - port map(A => \addr_0[9]_net_1\, B => N_109, C => N_114, Y - => N_420); - - \addr_RNID2T07[7]\ : OR2 - port map(A => \romdata_0_0[30]\, B => N_185, Y => hrdata_30); - - \addr_RNIP7Q61[5]\ : AOI1 - port map(A => N_446, B => N_110, C => N_107, Y => - \romdata_0_a19_0[29]\); - - \romdata_0_RNO_0[26]\ : AND2 - port map(A => \romdata_0_RNO_1[26]_net_1\, B => N_392, Y - => \romdata_0_9[26]\); - - \addr_RNISMBC1_1[3]\ : NOR2 - port map(A => N_465, B => N_143, Y => N_259); - - \addr_0_RNIJRJN[6]\ : NOR2 - port map(A => \addr_0[6]_net_1\, B => N_436, Y => N_509); - - \addr_RNIOT2B[3]\ : NOR2B - port map(A => \addr[9]_net_1\, B => \addr[3]_net_1\, Y => - N_156); - - \addr_RNIJCKG[5]\ : OR2B - port map(A => \addr[5]_net_1\, B => N_156, Y => N_324); - - \addr_0_RNI2QLD3[5]\ : NOR3C - port map(A => N_296, B => N_293, C => N_295, Y => - \romdata_0_1[14]\); - - \addr_RNI2P811[9]\ : NOR2A - port map(A => N_463, B => N_428, Y => N_494); - - \addr_RNIUNSL3[2]\ : NOR3B - port map(A => N_237, B => N_239, C => N_236, Y => - \romdata_0_2[0]\); - - \addr_RNIQ7M91[2]\ : NOR3 - port map(A => N_122, B => N_430_0, C => N_107, Y => N_515); - - \romdata_0_RNO_4[26]\ : OA1A - port map(A => N_523, B => \addr_0[3]_net_1\, C => N_390, Y - => \romdata_0_6[26]\); - - \romdata_0_RNO_3[13]\ : NOR3C - port map(A => \romdata_0_2[13]\, B => N_290, C => N_285, Y - => \romdata_0_6[13]\); - - \addr_RNIDCPE5[5]\ : NOR3C - port map(A => \romdata_i_2[20]\, B => N_322, C => - \romdata_i_4[20]\, Y => \romdata_i_8[20]\); - - \addr_RNI1HQCH[2]\ : OR3C - port map(A => N_374, B => \romdata_0_10[25]\, C => - \romdata_0_11[25]\, Y => hrdata_25); - - \addr_0_RNI5VO65[9]\ : NOR3C - port map(A => N_370, B => N_360, C => \romdata_i_3[24]\, Y - => \romdata_i_7[24]\); - - \addr_0_RNI1PM21[4]\ : OR2 - port map(A => N_446, B => \addr_0_RNIIC2I[4]_net_1\, Y => - \addr_0_RNI1PM21[4]_net_1\); - - \addr_RNIRT2B_0[7]\ : NOR2B - port map(A => \addr[8]_net_1\, B => \addr[7]_net_1\, Y => - N_468); - - \addr_RNIER5M_0[9]\ : OR2A - port map(A => N_126, B => N_490, Y => - \addr_RNIER5M_0[9]_net_1\); - - \addr_0_RNIUO5P3[9]\ : AOI1B - port map(A => \addr_0[9]_net_1\, B => N_172, C => - \romdata_0_0[17]\, Y => \romdata_0_1[17]\); - - \addr_0_RNIAC2I[3]\ : NOR2 - port map(A => \addr_0[3]_net_1\, B => N_109, Y => - \romdata_0_a19_0[11]\); - - \addr_RNIRT2B_0[9]\ : NOR2A - port map(A => \addr[9]_net_1\, B => \addr[6]_net_1\, Y => - N_489); - - \addr_RNIGR5M[3]\ : OR2 - port map(A => N_449, B => N_207, Y => - \addr_RNIGR5M[3]_net_1\); - - \addr_0_RNIT7M91_0[4]\ : OR2A - port map(A => N_485, B => \addr_0[4]_net_1\, Y => N_265); - - \addr_RNINCKG[6]\ : OR2A - port map(A => N_480, B => \addr[6]_net_1\, Y => N_363); - - \addr_RNIAO77G[5]\ : OR3C - port map(A => \romdata_0_7[23]\, B => \romdata_0_6[23]\, C - => N_197_i, Y => hrdata_23); - - \addr_RNINVDP9[3]\ : OR3B - port map(A => \romdata_0_3[3]\, B => N_257, C => N_240, Y - => hrdata_3); - - \addr_RNI170Q3[6]\ : NOR3C - port map(A => N_255, B => N_250, C => N_251, Y => - \romdata_0_5[2]\); - - \addr_0_RNIG6AU3[3]\ : NOR3 - port map(A => N_270, B => N_439, C => - \addr_RNIMM7F1_0[2]_net_1\, Y => N_184); - - \addr_0_RNINC2I[9]\ : OR3B - port map(A => \addr[7]_net_1\, B => \addr[8]_net_1\, C => - \addr_0[9]_net_1\, Y => N_430_0); - - \addr_RNIQ7881[7]\ : OR3B - port map(A => N_116, B => \romdata_i_a19_2_0[31]\, C => - N_449, Y => N_415); - - \addr_0_RNIOO071[2]\ : OR3C - port map(A => N_468, B => \romdata_i_a19_0_0[24]\, C => - N_151, Y => N_356); - - \addr_RNIHCKG[5]\ : NOR2 - port map(A => \addr[5]_net_1\, B => N_445, Y => N_502); - - \addr_0_RNIRHR62[9]\ : AOI1 - port map(A => \addr_0[9]_net_1\, B => N_463, C => N_342, Y - => \romdata_0_0[21]\); - - \addr_RNI5P811[7]\ : OR3B - port map(A => N_110, B => N_468, C => N_116, Y => N_322); - - \addr_RNI4P811[7]\ : OR3A - port map(A => N_105, B => N_132, C => N_110, Y => N_361); - - \addr_RNIVR043[3]\ : NOR3C - port map(A => N_420, B => N_421, C => N_426, Y => - \romdata_i_6[31]\); - - \addr_RNISMBC1_0[8]\ : OR3 - port map(A => N_143, B => N_437, C => N_470, Y => N_405); - - \addr_RNIHR5M[4]\ : NOR2A - port map(A => N_499, B => N_138, Y => - \romdata_i_a19_10_0[31]\); - - \addr_RNIFR5M[9]\ : NOR2 - port map(A => N_428, B => N_116, Y => - \romdata_0_a19_5_0[2]\); - - \addr_RNI15CK6[9]\ : OR3 - port map(A => N_259, B => N_306, C => N_134, Y => hrdata_16); - - \addr_0_RNI3CUK[2]\ : NOR2A - port map(A => \addr_0[2]_net_1\, B => N_114, Y => - \romdata_0_a19_2_0[19]\); - - \addr_RNIQPITF[9]\ : OR3C - port map(A => N_197_i, B => \romdata_0_5[15]\, C => - \romdata_0_6[15]\, Y => hrdata_15); - - \addr_RNIPF2F2[6]\ : AOI1B - port map(A => \romdata_0_a19_5_0[2]\, B => N_482, C => - N_252, Y => \romdata_0_0[2]\); - - \addr_RNISMBC1[3]\ : OR3A - port map(A => N_451, B => N_110, C => N_438, Y => N_250); - - \addr_RNI7Q7C3[4]\ : OR2B - port map(A => N_440, B => N_304, Y => N_134); - - \romdata_0_RNO_12[13]\ : OR3 - port map(A => N_105, B => N_132, C => N_448, Y => N_288); - - \addr_0_RNIUO441[2]\ : OR3A - port map(A => \romdata_0_a19_5_0[25]\, B => N_110, C => - N_428, Y => N_378); - - \addr_0_RNIP9101_0[6]\ : NOR2B - port map(A => \addr_0[6]_net_1\, B => N_450, Y => N_130); - - \addr_RNI7HOA7[3]\ : NOR3C - port map(A => N_358, B => \romdata_i_7[24]\, C => N_367, Y - => \romdata_i_13[24]\); - - \romdata_0_RNO_5[26]\ : NOR3C - port map(A => N_393, B => N_387, C => N_388, Y => - \romdata_0_2[26]\); - - \addr_0_RNIO74B1[3]\ : OR2B - port map(A => \romdata_0_a19_0[11]\, B => N_484, Y => N_278); - - \addr_0_RNIIDJR2[5]\ : NOR2B - port map(A => N_241, B => N_244, Y => \romdata_0_1[1]\); - - \addr_0_RNIJC2I[4]\ : NOR2A - port map(A => \addr_0[4]_net_1\, B => N_428, Y => - \romdata_0_a19_11_0[25]\); - - \addr_0_RNI2L584[5]\ : NOR3C - port map(A => N_292, B => N_291, C => N_285, Y => - \romdata_0_5[14]\); - - \addr_RNI5ANR[9]\ : OR2A - port map(A => N_459, B => N_126, Y => N_242); - - \addr_0_RNIKN6Q3[9]\ : NOR3B - port map(A => N_351, B => N_352, C => N_347, Y => - \romdata_0_4[23]\); - - \addr_0_RNIBRPA8[2]\ : NOR2B - port map(A => \romdata_0_3[19]\, B => N_316, Y => - \romdata_0_4[19]\); - - \addr_0_RNI46P09[3]\ : NOR3C - port map(A => \romdata_0_4[25]\, B => N_379, C => - \romdata_0_7[25]\, Y => \romdata_0_10[25]\); - - \addr_RNI7ANR[3]\ : OR3A - port map(A => N_499, B => N_110, C => \addr[3]_net_1\, Y - => N_421); - - \addr_RNI48Q61[5]\ : OR3A - port map(A => N_107, B => N_448, C => N_438, Y => N_408); - - \addr_RNI43T07[2]\ : NOR3C - port map(A => \romdata_0_5[25]\, B => N_373, C => - \romdata_0_9[25]\, Y => \romdata_0_11[25]\); - - \addr_RNI5A5T[2]\ : OR2A - port map(A => N_508, B => \addr[2]_net_1\, Y => N_245); - - \addr_RNIO7Q61[5]\ : OR2 - port map(A => N_502, B => \addr_RNI7R5M[3]_net_1\, Y => - N_170); - - \addr_RNI7R5M[4]\ : NOR2A - port map(A => N_127, B => N_124, Y => - \romdata_0_a19_1_0[0]\); - - \addr_0_RNIPMPD1_0[5]\ : OR3 - port map(A => N_438, B => N_442, C => N_107, Y => N_244); - - \addr_RNIKJFGG[6]\ : OR3C - port map(A => \romdata_0_6[2]\, B => \romdata_0_5[2]\, C - => N_155_i, Y => hrdata_2); - - \addr_RNI2DTV2[5]\ : AOI1B - port map(A => \romdata_0_a19_1_0[0]\, B => N_343_1, C => - N_232, Y => \romdata_0_3[0]\); - - \addr_0_RNINC2I_0[9]\ : NOR2A - port map(A => N_132, B => \addr_0[9]_net_1\, Y => - \romdata_0_a19_0_0[23]\); - - \romdata_0_RNO_13[13]\ : OR3A - port map(A => \romdata_0_a19_3_0[13]\, B => N_114, C => - N_428, Y => N_284); - - \addr_RNIQNEK3[8]\ : NOR2 - port map(A => N_462, B => N_240, Y => N_155_i); - - \addr_RNIHT2B_0[2]\ : OR2 - port map(A => \addr[3]_net_1\, B => \addr[2]_net_1\, Y => - N_124); - - \addr_0_RNIARJN[9]\ : OR2B - port map(A => \addr_0[9]_net_1\, B => N_478, Y => N_397); - - \addr_RNINCKG_0[7]\ : NOR2 - port map(A => \addr[7]_net_1\, B => N_449, Y => - \romdata_i_a19_0[31]\); - - \addr_0_RNI0LJ94[6]\ : OA1A - port map(A => \romdata_i_a19_11_0[31]\, B => N_436, C => - \romdata_i_6[31]\, Y => \romdata_i_10[31]\); - - \addr_RNIQUJK2[2]\ : AOI1 - port map(A => N_256_1, B => N_160, C => N_494, Y => - \romdata_0_1[3]\); - - \addr_0_RNIUHV32[2]\ : AOI1 - port map(A => N_453, B => N_452, C => N_400_1, Y => N_488); - - \addr_0_RNI1SA83[9]\ : NOR3C - port map(A => N_356, B => \romdata_i_0[24]\, C => N_362, Y - => \romdata_i_3[24]\); - - \addr_RNISMBC1_0[6]\ : OR3A - port map(A => N_482, B => N_108, C => N_430, Y => N_238); - - \addr_RNIU7Q61[6]\ : OR3B - port map(A => N_293_1, B => N_131, C => N_116, Y => N_293); - - \addr_RNI7ANR[8]\ : OR3 - port map(A => N_126, B => \addr[8]_net_1\, C => N_445, Y - => N_327); - - \addr_RNI59TE3[9]\ : NOR2A - port map(A => N_261, B => N_148, Y => \romdata_0_1[4]\); - - \addr_0[4]\ : DFN1 - port map(D => haddr(4), CLK => lclk_c, Q => - \addr_0[4]_net_1\); - - \addr_RNIDANR[9]\ : OR2 - port map(A => N_430, B => N_107, Y => N_472); - - \addr_0_RNIKFGG2[2]\ : OA1A - port map(A => \romdata_i_a19_3_1[31]\, B => N_110, C => - N_419, Y => \romdata_i_2[31]\); - - \addr_RNIGANR[4]\ : NOR2 - port map(A => N_445, B => N_438, Y => N_511); - - \addr_0_RNIQH982[6]\ : AO1C - port map(A => N_514, B => N_286_i, C => \addr_0[6]_net_1\, - Y => N_496); - - \addr_RNISMBC1[2]\ : OR3 - port map(A => N_116, B => N_441, C => N_438, Y => N_239); - - \addr_0_RNIML5KB[4]\ : OR3B - port map(A => N_184, B => \romdata_0_0[6]\, C => N_196, Y - => hrdata_6); - - GND_i : GND - port map(Y => \GND\); - - \addr_0_RNI3A5T[4]\ : OR3A - port map(A => \addr[7]_net_1\, B => \addr_0[4]_net_1\, C - => N_441, Y => N_331); - - \addr[8]\ : DFN1 - port map(D => haddr(8), CLK => lclk_c, Q => \addr[8]_net_1\); - - \addr_RNIQ7881_0[7]\ : OR3A - port map(A => N_480, B => N_107, C => N_442, Y => N_426); - - \addr_0_RNINNOO3[3]\ : NOR3B - port map(A => N_244, B => N_276, C => N_270, Y => - \romdata_0_1[9]\); - - \addr_RNIL65O8[3]\ : OR3B - port map(A => \romdata_0_1[4]\, B => \romdata_0_2[4]\, C - => N_259, Y => hrdata_4); - - \addr_RNI8ANR[4]\ : OR2B - port map(A => \addr[4]_net_1\, B => N_493, Y => N_249); - - \addr_RNI1BR48[4]\ : OR3C - port map(A => N_184, B => \romdata_0_0[7]\, C => N_266, Y - => hrdata_7); - - \addr_RNIER5M[9]\ : NOR2A - port map(A => \addr[9]_net_1\, B => N_446, Y => N_493); - - \addr_0_RNI553P1[5]\ : OA1A - port map(A => N_489, B => N_471, C => N_359, Y => - \romdata_i_8[24]\); - - \addr_0_RNI1CVL5[6]\ : NOR3C - port map(A => \romdata_0_2[28]\, B => N_153_i, C => N_401, - Y => \romdata_0_6[28]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \addr_RNIMT2B[3]\ : OR2A - port map(A => \addr[3]_net_1\, B => \addr[7]_net_1\, Y => - N_207); - - \addr_RNI9ANR[5]\ : OR2A - port map(A => N_459, B => N_448, Y => N_235); - - \addr_RNI6B853[2]\ : NOR3C - port map(A => N_242, B => N_245, C => N_247, Y => - \romdata_0_2[1]\); - - \addr_0_RNI7A5T[6]\ : OR3 - port map(A => N_132, B => \addr_0[6]_net_1\, C => N_107, Y - => N_330); - - \addr_RNI7RJN[4]\ : NOR2A - port map(A => N_112, B => N_437, Y => - \romdata_i_a19_5_0[31]\); - - \addr_RNI2A5T[8]\ : OR3A - port map(A => \addr_0[6]_net_1\, B => \addr[8]_net_1\, C - => N_143, Y => N_329); - - \addr_0_RNI88881[6]\ : NOR2B - port map(A => N_476, B => N_475, Y => N_171); - - \addr_RNIKT2B[2]\ : OR2A - port map(A => \addr[2]_net_1\, B => \addr[6]_net_1\, Y => - N_109); - - \addr_RNI9P811[6]\ : OR3 - port map(A => N_116, B => N_430, C => \addr[6]_net_1\, Y - => N_251); - - \addr_RNIH6AU3[8]\ : NOR3A - port map(A => N_258, B => N_494, C => N_302, Y => - \romdata_0_4[15]\); - - \addr_RNI18Q61[9]\ : OR3 - port map(A => N_116, B => N_430, C => N_109, Y => N_261); - - \addr_0_RNIGM3I1[2]\ : OR3A - port map(A => \romdata_0_a19_3_0[8]\, B => N_114, C => - N_430_0, Y => N_273); - - \addr_RNIRT2B[7]\ : OR2 - port map(A => \addr[8]_net_1\, B => \addr[7]_net_1\, Y => - N_132); - - \addr_RNIR83M3[8]\ : OA1A - port map(A => N_523, B => N_112, C => \romdata_0_1[27]\, Y - => \romdata_0_3[27]\); - - \addr_RNI3RJN[2]\ : OR2 - port map(A => N_122, B => N_107, Y => N_505); - - \addr_RNIICKG[9]\ : NOR2A - port map(A => \addr[9]_net_1\, B => N_108, Y => N_459); - - \addr_RNI08881[4]\ : OR2A - port map(A => N_512, B => N_442, Y => N_276); - - \addr_0_RNIV7881[3]\ : NOR2 - port map(A => N_519, B => N_430, Y => N_443); - - \addr_RNISMBC1[8]\ : OR3A - port map(A => N_143, B => N_437, C => N_470, Y => N_407); - - \addr_RNIT7Q61[7]\ : AO1B - port map(A => N_126, B => N_116, C => \romdata_i_a19_0[24]\, - Y => N_355); - - \addr_RNIMUFN2[2]\ : OA1 - port map(A => N_105, B => N_465, C => N_338, Y => - \romdata_0_7[21]\); - - \addr_RNI91H92[4]\ : OA1A - port map(A => N_512, B => N_448, C => N_287, Y => - \romdata_0_9[25]\); - - \addr_RNI8P811_0[5]\ : OR2B - port map(A => \addr[5]_net_1\, B => N_492, Y => N_334); - - \addr_RNI3THD5[6]\ : NOR3C - port map(A => \romdata_0_1[25]\, B => \romdata_0_0[25]\, C - => N_380, Y => \romdata_0_4[25]\); - - \addr_0_RNIMC2I[9]\ : OR2 - port map(A => \addr_0[9]_net_1\, B => N_449, Y => - \romdata_0_a19_5_0[21]\); - - \addr_0_RNIHTUD[2]\ : NOR2B - port map(A => \addr_0[2]_net_1\, B => \addr_0[9]_net_1\, Y - => \romdata_0_a19_0_0[0]\); - - \addr_0_RNIUOM21[3]\ : NOR3A - port map(A => N_105, B => \addr_0[3]_net_1\, C => N_469, Y - => N_270); - - \addr_RNI2ANR[3]\ : NOR2A - port map(A => N_451, B => N_448, Y => N_516); - - \addr_0_RNIJMLG1[2]\ : OR2B - port map(A => \romdata_0_a19_2_0[19]\, B => N_511, Y => - N_316); - - \addr_0_RNIGUP7A[4]\ : NOR3C - port map(A => \romdata_i_10[31]\, B => \romdata_i_9[31]\, C - => N_427, Y => \romdata_i_15[31]\); - - \addr_0_RNIV9JU[5]\ : OR3B - port map(A => N_291_1, B => \addr_0[5]_net_1\, C => N_112, - Y => N_417); - - \addr_RNI9ANR[9]\ : NOR2A - port map(A => N_459, B => N_437, Y => N_497); - - \addr_RNI08Q61_0[2]\ : OR3 - port map(A => N_116, B => N_430, C => N_126, Y => N_404); - - \addr_RNIIT2B[2]\ : XOR2 - port map(A => \addr[4]_net_1\, B => \addr[2]_net_1\, Y => - N_117_i); - - \addr_0_RNIT7M91[4]\ : OR2B - port map(A => \addr_0[4]_net_1\, B => N_485, Y => N_427); - - \addr_RNIP7M91[4]\ : OR2A - port map(A => N_227, B => N_507, Y => N_300); - - \addr_RNIJMLG1[2]\ : OR3 - port map(A => N_471, B => N_445, C => N_430_0, Y => N_310); - - \addr_0_RNIMUFN2[4]\ : NOR2B - port map(A => N_264, B => N_265, Y => \romdata_0_0[6]\); - - \addr_RNIHCKG[8]\ : NOR2A - port map(A => \addr[8]_net_1\, B => N_107, Y => - \romdata_i_a19_10_0[24]\); - - \addr_RNI3RP2I[5]\ : NOR3C - port map(A => \romdata_i_15[20]\, B => \romdata_i_14[20]\, - C => \romdata_i_16[20]\, Y => N_90_i_0); - - \addr_RNI1P811[6]\ : OR2B - port map(A => N_482, B => N_459, Y => N_380); - - \addr_0_RNI0G2F2[3]\ : AOI1B - port map(A => \romdata_0_a19_0_0[27]\, B => - \romdata_0_a19_2_1[28]\, C => N_399, Y => - \romdata_0_0[27]\); - - \addr_RNIMR5M[6]\ : NOR2 - port map(A => N_431, B => N_138, Y => - \romdata_0_a19_2_1[28]\); - - \addr_RNINT2B[5]\ : OR2B - port map(A => \addr[6]_net_1\, B => \addr[5]_net_1\, Y => - N_110); - - \addr[5]\ : DFN1 - port map(D => haddr(5), CLK => lclk_c, Q => \addr[5]_net_1\); - - \addr_RNIMM7F1[9]\ : OR3 - port map(A => N_400_1, B => N_198_i, C => N_519, Y => - \addr_RNIMM7F1[9]_net_1\); - - \addr_RNI9MQE6[9]\ : NOR3B - port map(A => \romdata_i_6[20]\, B => \romdata_i_11[20]\, C - => N_493, Y => \romdata_i_14[20]\); - - \addr_0_RNIDC2I[4]\ : NOR2A - port map(A => N_207, B => \addr_0[4]_net_1\, Y => - \romdata_0_a19_0[19]\); - - \addr_RNIMT2B[4]\ : XNOR2 - port map(A => \addr[4]_net_1\, B => \addr[6]_net_1\, Y => - N_127); - - \addr_0_RNILD5Q2[9]\ : NOR2B - port map(A => N_268, B => N_267, Y => \romdata_0_0[7]\); - - \addr_0_RNI7CUK_0[6]\ : NOR2 - port map(A => \addr_0[6]_net_1\, B => N_114, Y => - \addr_0_RNI7CUK_0[6]_net_1\); - - \romdata_0_RNO_2[26]\ : NOR3C - port map(A => N_379, B => \romdata_0_2[26]\, C => - \romdata_0_5[26]\, Y => \romdata_0_7[26]\); - - \addr_RNIQT2B[6]\ : XOR2 - port map(A => \addr[8]_net_1\, B => \addr[6]_net_1\, Y => - N_106_i); - - \addr_0_RNIGM3I1[6]\ : NOR3 - port map(A => N_114, B => N_430_0, C => - \romdata_0_a19_0[18]\, Y => N_311); - - \addr_0_RNIP9101[6]\ : NOR3B - port map(A => \addr_0[6]_net_1\, B => N_135, C => N_105, Y - => \romdata_0_a19_0_1[21]\); - - \romdata_0_RNO_2[13]\ : OR2 - port map(A => N_465, B => \romdata_0_RNO_5[13]_net_1\, Y - => \romdata_0_RNO_2[13]_net_1\); - - \addr_RNIHFDK7[4]\ : OR3C - port map(A => \addr_RNIMM7F1[4]_net_1\, B => - \romdata_0_0[27]\, C => \romdata_0_3[27]\, Y => hrdata_27); - - \addr_RNIRT2B_1[7]\ : NOR2A - port map(A => \addr[7]_net_1\, B => \addr[8]_net_1\, Y => - N_480); - - \addr_0_RNIPMPD1[9]\ : OR3A - port map(A => \romdata_0_a19_0_0[23]\, B => N_116, C => - N_441, Y => N_351); - - \addr_RNISMBC1_1[6]\ : OR3A - port map(A => N_482, B => N_108, C => N_438, Y => N_247); - - \addr_RNI0I427[5]\ : NOR3C - port map(A => \romdata_0_2[1]\, B => \romdata_0_1[1]\, C - => N_243, Y => \romdata_0_4[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \addr_RNICMLG1[2]\ : OAI1 - port map(A => N_478, B => \addr_0_RNI7CUK_0[6]_net_1\, C - => N_291_1, Y => N_291); - - \addr_0_RNI2AJU[2]\ : OR3B - port map(A => N_149_i_i_0, B => N_468, C => - \addr_0[2]_net_1\, Y => N_319); - - \addr_RNI2ID52[3]\ : OA1B - port map(A => N_450, B => N_503, C => N_460, Y => N_153_i); - - \addr_0[9]\ : DFN1 - port map(D => haddr(9), CLK => lclk_c, Q => - \addr_0[9]_net_1\); - - \addr_0_RNI6MHJ1[2]\ : OAI1 - port map(A => N_478, B => \addr_0_RNI7CUK_0[6]_net_1\, C - => \romdata_0_a19_0_0[0]\, Y => N_232); - - \romdata_0_RNO_9[13]\ : OR3B - port map(A => \addr_0[3]_net_1\, B => \addr_0[5]_net_1\, C - => N_127, Y => \romdata_0_a19_2_0[13]\); - - \addr_RNIR7881[4]\ : OR3 - port map(A => N_446, B => N_431, C => N_112, Y => N_315); - - \addr_RNIJ5GH6[5]\ : OR3C - port map(A => N_408, B => \romdata_0_0[29]\, C => - \romdata_0_1[29]\, Y => hrdata_29); - - \addr_0_RNIU7881_1[6]\ : OR2B - port map(A => N_509, B => N_451, Y => N_287); - - \addr_0_RNILC2I[5]\ : NOR2B - port map(A => \addr_0[5]_net_1\, B => N_500, Y => - \romdata_i_a19_15_0[24]\); - - \addr_0_RNIPMPD1[4]\ : OR3B - port map(A => \romdata_0_a19_0[19]\, B => N_500, C => N_441, - Y => N_313); - - \addr_RNIQCKG[8]\ : OR2A - port map(A => \addr[8]_net_1\, B => N_431, Y => N_470); - - \addr_RNI0R1P[4]\ : AXOI4 - port map(A => \addr[4]_net_1\, B => N_122, C => - \addr_0[3]_net_1\, Y => N_227); - - \addr_0_RNIETUD_0[5]\ : OR2 - port map(A => \addr_0[5]_net_1\, B => \addr_0[3]_net_1\, Y - => N_114); - - \addr_RNIOCKG[6]\ : NOR2 - port map(A => \addr[6]_net_1\, B => N_431, Y => N_293_1); - - \addr_RNIIA5T[9]\ : OR2B - port map(A => N_490, B => N_430_0, Y => N_160); - - \addr_RNI9P811_0[6]\ : OR3 - port map(A => N_107, B => N_428, C => N_106_i, Y => N_433); - - \addr_RNI2ANR[2]\ : OR2 - port map(A => N_441, B => N_108, Y => N_473); - - \addr_0_RNIL74B1[3]\ : OR3A - port map(A => \romdata_0_a19_11_0[25]\, B => N_442, C => - \addr_0[3]_net_1\, Y => N_384); - - \addr_RNI6R5M[5]\ : NOR2A - port map(A => N_166, B => N_124, Y => - \romdata_0_a19_0_0[27]\); - - \addr_0_RNIK0ED7[9]\ : OR3A - port map(A => \romdata_0_0[11]\, B => N_259, C => N_342, Y - => hrdata_11); - - \addr_0_RNI3A5T[2]\ : NOR3B - port map(A => N_480, B => N_116, C => \addr_0[2]_net_1\, Y - => \romdata_i_a19_3_1[31]\); - - \addr_RNI0P441[4]\ : OR3 - port map(A => N_114, B => N_428, C => N_445, Y => N_296); - - \addr_RNIRO441_0[9]\ : OR2A - port map(A => N_489, B => N_450, Y => N_383); - - \romdata_0_RNO_3[26]\ : OR2 - port map(A => \addr[5]_net_1\, B => N_472, Y => N_392); - - \addr_RNI08H36[2]\ : NOR3B - port map(A => \romdata_0_1[3]\, B => \romdata_0_0[3]\, C - => N_525, Y => \romdata_0_3[3]\); - - \addr_RNI38Q61[4]\ : OR2A - port map(A => N_512, B => N_446, Y => N_455); - - \addr_0_RNIRO441[9]\ : NOR3C - port map(A => N_479, B => \addr_0[9]_net_1\, C => N_451, Y - => N_347); - - \romdata_0_RNO[26]\ : AND2 - port map(A => \romdata_0_7[26]\, B => \romdata_0_6[26]\, Y - => \romdata_0_8[26]\); - - \romdata_0_a19_5[14]\ : NAND2 - port map(A => N_491_i, B => \romdata_0_a19_5_0[14]\, Y => - N_297); - - \addr_0_RNIQ9T21[9]\ : OR2 - port map(A => \romdata_0_a19_0_0[17]\, B => N_135, Y => - \addr_0_RNIQ9T21[9]_net_1\); - - \romdata_0[26]\ : NAND2 - port map(A => \romdata_0_8[26]\, B => \romdata_0_9[26]\, Y - => hrdata_26); - - \romdata_0_RNO_10[13]\ : NOR3C - port map(A => N_282, B => N_288, C => N_284, Y => - \romdata_0_1[13]\); - - \addr_0_RNILC2I[6]\ : OR2 - port map(A => \addr_0[6]_net_1\, B => N_428, Y => N_476); - - \addr_0_RNIDVA55[3]\ : OR3B - port map(A => N_310, B => N_440, C => N_279, Y => hrdata_12); - - \addr_RNIST2B[9]\ : OR2A - port map(A => \addr[7]_net_1\, B => \addr[9]_net_1\, Y => - N_428); - - \addr_0_RNIJTUD[4]\ : NOR2A - port map(A => \addr_0[9]_net_1\, B => \addr_0[4]_net_1\, Y - => \romdata_0_a19_1_0[28]\); - - \addr_0_RNICC2I[5]\ : OR2A - port map(A => \addr_0[5]_net_1\, B => N_109, Y => N_442); - - \romdata_0_RNO_12[26]\ : OR3A - port map(A => N_198_i, B => \addr_0[2]_net_1\, C => N_507, - Y => N_385); - - \addr_RNICL954[5]\ : AND2 - port map(A => \romdata_0_2[21]\, B => N_344, Y => - \romdata_0_4[21]\); - - \addr_RNIMCKG[9]\ : OR2A - port map(A => \addr[9]_net_1\, B => N_437, Y => N_469); - - \addr_RNIST2B_0[9]\ : OR2 - port map(A => \addr[9]_net_1\, B => \addr[7]_net_1\, Y => - N_431); - - \addr_RNIG7M91[5]\ : AO1A - port map(A => N_109, B => N_114, C => N_478, Y => N_172); - - \addr_RNIFCKG[2]\ : OR2A - port map(A => \addr[2]_net_1\, B => N_110, Y => N_441); - - \addr_RNI6PM21[8]\ : NOR2 - port map(A => N_442, B => N_436, Y => N_485); - - \addr_0_RNI8C2I_0[4]\ : NOR2A - port map(A => \addr_0[4]_net_1\, B => N_124, Y => N_481); - - \romdata_0_RNO_14[13]\ : NOR2B - port map(A => \addr_0[6]_net_1\, B => N_117_i, Y => - \romdata_0_a19_3_0[13]\); - - \addr_RNIUOM21[9]\ : OR3B - port map(A => N_489, B => N_107, C => N_122, Y => N_303); - - \addr_RNIFCKG[5]\ : OR2 - port map(A => \addr[5]_net_1\, B => N_109, Y => N_446); - - \addr_RNICDFU2[3]\ : OR2 - port map(A => N_461, B => N_302, Y => \romdata_0_o19_0[14]\); - - \addr_RNIBCKG_0[3]\ : NOR2A - port map(A => \addr[3]_net_1\, B => N_105, Y => N_451); - - \addr_0_RNIBC2I[5]\ : XNOR2 - port map(A => \addr_0[5]_net_1\, B => N_107, Y => - N_162_i_i_0); - - \addr_RNIBANR[6]\ : OR2A - port map(A => N_482, B => N_431, Y => N_332); - - \addr_RNIPTDSC[2]\ : OR3C - port map(A => N_404, B => \romdata_0_5[28]\, C => - \romdata_0_6[28]\, Y => hrdata_28); - - \addr_0_RNIT5K24[9]\ : NOR3C - port map(A => \romdata_0_0[21]\, B => N_341, C => N_286_i, - Y => \romdata_0_3[21]\); - - \addr_RNIDC2I[7]\ : NOR2A - port map(A => \addr[7]_net_1\, B => N_122, Y => - \romdata_i_a19_2_0[31]\); - - \addr_0_RNIPHR62[6]\ : AO1D - port map(A => N_463, B => \addr_0_RNIP9101_1[6]_net_1\, C - => N_430, Y => N_248); - - \addr_0[6]\ : DFN1 - port map(D => haddr(6), CLK => lclk_c, Q => - \addr_0[6]_net_1\); - - \addr_RNIUOM21_0[9]\ : OR2A - port map(A => N_481, B => N_469, Y => N_237); - - \romdata_0_a19_5_RNII17T7[14]\ : NOR3C - port map(A => \romdata_0_4[14]\, B => N_294, C => N_297, Y - => \romdata_0_8[14]\); - - \addr_RNITT2B[9]\ : OR2A - port map(A => \addr[8]_net_1\, B => \addr[9]_net_1\, Y => - N_400_1); - - \addr_RNIGCKG[7]\ : OR2 - port map(A => \addr[7]_net_1\, B => N_116, Y => - \romdata_0_a19_0_0[30]\); - - \addr_0_RNI0A5T[2]\ : OR3B - port map(A => \addr[7]_net_1\, B => N_478, C => - \addr_0[2]_net_1\, Y => N_328); - - \romdata_0_RNO_5[13]\ : NOR2B - port map(A => \addr_0[3]_net_1\, B => N_117_i, Y => - \romdata_0_RNO_5[13]_net_1\); - - \addr_0_RNICC2I[6]\ : NOR2B - port map(A => \addr_0[6]_net_1\, B => N_108, Y => - \romdata_0_a19_1_0[21]\); - - \addr_0_RNITR043[4]\ : NOR3C - port map(A => N_383, B => N_377, C => N_375, Y => - \romdata_0_5[25]\); - - \addr_RNI6NPD1[8]\ : NOR2 - port map(A => \addr[8]_net_1\, B => N_171, Y => N_523); - - \addr_RNIO7M91[6]\ : OR2A - port map(A => N_293_1, B => N_450, Y => N_317); - - \addr_0_RNI4RFQ[5]\ : OR3C - port map(A => \addr_0[5]_net_1\, B => \addr_0[9]_net_1\, C - => N_112, Y => N_359); - - \addr_RNIGFQ0A[9]\ : NOR3C - port map(A => N_301, B => \romdata_0_1[15]\, C => - \romdata_0_4[15]\, Y => \romdata_0_5[15]\); - - \addr_RNI2A5T[9]\ : OR2A - port map(A => \addr[9]_net_1\, B => N_505, Y => N_422); - - \addr_0_RNIKTGC[5]\ : NOR2A - port map(A => \addr[6]_net_1\, B => \addr_0[5]_net_1\, Y - => N_479); - - \romdata_0_RNO_7[26]\ : OR3A - port map(A => \addr[5]_net_1\, B => N_108, C => N_430, Y - => N_390); - - \addr_RNI9NPD1[6]\ : OA1C - port map(A => N_106_i, B => N_428, C => N_509, Y => - N_16427_tz); - - \addr_0[5]\ : DFN1 - port map(D => haddr(5), CLK => lclk_c, Q => - \addr_0[5]_net_1\); - - \addr[9]\ : DFN1 - port map(D => haddr(9), CLK => lclk_c, Q => \addr[9]_net_1\); - - \addr_RNIQCKG_0[8]\ : OR2 - port map(A => \addr[8]_net_1\, B => N_428, Y => N_438); - - \addr_0_RNIIFGG2[5]\ : OA1A - port map(A => N_170, B => N_132, C => N_417, Y => - \romdata_i_8[31]\); - - \addr_RNIRT2B[9]\ : OR2B - port map(A => \addr[9]_net_1\, B => \addr[6]_net_1\, Y => - N_490); - - \addr_RNIU5BJ1[2]\ : OR2B - port map(A => \addr[2]_net_1\, B => N_523, Y => N_373); - - \addr_RNIPK029[4]\ : NOR3B - port map(A => N_248, B => \romdata_0_2[2]\, C => N_148, Y - => \romdata_0_6[2]\); - - \addr_RNIMT2B_0[4]\ : OR2B - port map(A => \addr[6]_net_1\, B => \addr[4]_net_1\, Y => - N_445); - - \addr_0_RNIU7M91[6]\ : OR3A - port map(A => N_162_i_i_0, B => \addr_0[6]_net_1\, C => - N_438, Y => N_401); - - \addr_0_RNI2RFQ[9]\ : OR2A - port map(A => \addr_0[9]_net_1\, B => N_471, Y => - \romdata_0_a19_1_0[17]\); - - \addr_RNI8P811[5]\ : OR3 - port map(A => N_116, B => N_430, C => \addr[5]_net_1\, Y - => N_243); - - \addr_0_RNIBC2I[6]\ : OR2 - port map(A => \addr_0[6]_net_1\, B => N_117_i, Y => - \romdata_0_a19_0[18]\); - - \addr_0_RNI1IR62[5]\ : OA1B - port map(A => N_438, B => N_442, C => N_398, Y => - \romdata_0_2[28]\); - - \romdata_0_RNO[13]\ : OR2 - port map(A => \addr[6]_net_1\, B => N_495, Y => N_289); - - \addr_RNIO9KV5[8]\ : NOR3C - port map(A => N_405, B => \romdata_0_1[28]\, C => - \addr_RNIMM7F1[9]_net_1\, Y => \romdata_0_5[28]\); - - \addr_0_RNICCGJ[3]\ : NOR3B - port map(A => \addr_0[3]_net_1\, B => \addr[7]_net_1\, C - => \addr_0[6]_net_1\, Y => \romdata_i_a19_1_1[24]\); - - \addr_RNIJ1GK4[9]\ : NOR3C - port map(A => \romdata_i_2[31]\, B => N_422, C => N_425, Y - => \romdata_i_9[31]\); - - \addr_0_RNIJ6SS3[9]\ : OR3 - port map(A => N_312, B => N_347, C => N_348, Y => - \romdata_0_1[22]\); - - \addr_0_RNIJC2I[9]\ : OR2A - port map(A => \addr_0[9]_net_1\, B => N_110, Y => N_362); - - \addr_0_RNIPMPD1[5]\ : OR3B - port map(A => N_451, B => N_479, C => N_436, Y => N_241); - - \romdata_0_RNO_11[26]\ : OA1A - port map(A => N_481, B => N_437, C => N_385, Y => - \romdata_0_1[26]\); - - \addr_RNI08Q61[2]\ : OR3A - port map(A => N_126, B => N_116, C => N_436, Y => N_358); - - \addr_0_RNIMM7F1[5]\ : OR3A - port map(A => N_107, B => N_442, C => N_430_0, Y => N_457); - - \addr_RNI8P811_1[5]\ : OR2A - port map(A => N_478, B => N_438, Y => N_379); - - \addr_0_RNIITGC[5]\ : XNOR2 - port map(A => \addr_0[5]_net_1\, B => \addr[4]_net_1\, Y - => N_149_i_i_0); - - \addr_RNIN7M91[7]\ : AO1C - port map(A => N_122, B => N_112, C => \romdata_i_a19_0[31]\, - Y => N_412); - - \addr_0_RNIRO441[4]\ : OR3B - port map(A => N_124, B => \romdata_0_a19_1_0[28]\, C => - N_448, Y => N_402); - - \addr_RNIJT2B[3]\ : OR2B - port map(A => \addr[4]_net_1\, B => \addr[3]_net_1\, Y => - N_107); - - \addr_0_RNIGGBU4[6]\ : OR2B - port map(A => \romdata_0_o19_0_0[5]\, B => N_496, Y => - N_196); - - \addr_0_RNID67M6[9]\ : OR3C - port map(A => \romdata_0_1[17]\, B => N_310, C => N_267, Y - => hrdata_17); - - \romdata_0[13]\ : NAND2 - port map(A => N_289, B => \romdata_0_8[13]\, Y => hrdata_13); - - \addr_RNIJT2B_0[2]\ : OR2A - port map(A => \addr[2]_net_1\, B => \addr[5]_net_1\, Y => - N_126); - - \romdata_0_a2_0[8]\ : NOR2 - port map(A => N_114, B => N_430_0, Y => N_491_i); - - \addr_RNIJT2B_1[3]\ : OR2 - port map(A => \addr[4]_net_1\, B => \addr[3]_net_1\, Y => - N_108); - - \addr_RNI7R5M[2]\ : NOR2 - port map(A => N_124, B => N_445, Y => - \romdata_0_a19_9_0[25]\); - - \addr_RNI08Q61[5]\ : OR2A - port map(A => N_343_1, B => N_143, Y => N_343); - - \addr_0[2]\ : DFN1 - port map(D => haddr(2), CLK => lclk_c, Q => - \addr_0[2]_net_1\); - - \addr_0_RNIAVE25[2]\ : OR2 - port map(A => \romdata_0_o19_0[14]\, B => N_488, Y => N_185); - - \addr_RNIQCKG_1[8]\ : OR2 - port map(A => \addr[8]_net_1\, B => N_431, Y => N_436); - - \addr_RNIPMPD1[5]\ : OR3 - port map(A => N_108, B => N_430_0, C => N_446, Y => N_344); - - \addr_RNIIDJR2[8]\ : OA1 - port map(A => N_450, B => N_503, C => N_407, Y => - \romdata_0_0[29]\); - - \addr_RNI5LN64[8]\ : NOR3B - port map(A => N_235, B => \romdata_i_9[20]\, C => N_485, Y - => \romdata_i_16[20]\); - - \addr_RNIPMPD1[2]\ : OR2 - port map(A => N_505, B => N_503, Y => N_264); - - \addr_0_RNIKTGC[3]\ : NOR2A - port map(A => \addr_0[3]_net_1\, B => \addr[8]_net_1\, Y - => \romdata_i_a19_4_0[20]\); - - \addr_RNIUP7C3[7]\ : NOR3C - port map(A => N_361, B => N_355, C => N_371, Y => - \romdata_i_6[24]\); - - \addr_RNI8K2OG[3]\ : NOR3C - port map(A => \romdata_i_13[24]\, B => \romdata_i_12[24]\, - C => \romdata_i_14[24]\, Y => N_95_i_0); - - \addr_0_RNIBC2I[2]\ : NOR2A - port map(A => \addr_0[2]_net_1\, B => N_445, Y => - \romdata_0_a19_3_0[8]\); - - \addr_RNIU0382[8]\ : OA1C - port map(A => N_473, B => \addr_RNI2ANR_0[3]_net_1\, C => - N_436, Y => N_240); - - \addr_RNISMBC1_4[8]\ : NOR2 - port map(A => N_473, B => N_438, Y => N_348); - - \addr_0_RNIKTGC[4]\ : XOR2 - port map(A => \addr[7]_net_1\, B => \addr_0[4]_net_1\, Y - => N_198_i); - - \addr_RNINCKG[7]\ : NOR2A - port map(A => \addr[7]_net_1\, B => N_449, Y => - \romdata_i_a19_0[24]\); - - \addr_0_RNIJMLG1_0[6]\ : NOR2 - port map(A => N_470, B => N_130, Y => N_302); - - \addr_RNIBANR[3]\ : OR3A - port map(A => N_132, B => N_110, C => \addr[3]_net_1\, Y - => N_320); - - \addr_RNIE4IR6[3]\ : NOR3C - port map(A => N_345, B => \romdata_0_3[21]\, C => N_336, Y - => \romdata_0_8[21]\); - - \addr_0_RNIL5PK1[5]\ : OR3B - port map(A => N_451, B => N_160, C => \addr_0[5]_net_1\, Y - => N_292); - - \addr_RNITT2B_0[9]\ : NOR2 - port map(A => \addr[9]_net_1\, B => \addr[8]_net_1\, Y => - N_500); - - \addr_RNIOFUH2[8]\ : OA1A - port map(A => \romdata_i_a19_5_0[31]\, B => N_436, C => - N_412, Y => \romdata_i_11[31]\); - - \addr_0[3]\ : DFN1 - port map(D => haddr(3), CLK => lclk_c, Q => - \addr_0[3]_net_1\); - - \addr_RNI41382[2]\ : OA1A - port map(A => N_117_i, B => N_469, C => N_250, Y => - \romdata_0_0[3]\); - - \addr_0_RNISHD52[9]\ : AOI1 - port map(A => \addr_0[9]_net_1\, B => N_516, C => N_270, Y - => \romdata_0_0[8]\); - - \addr_0_RNI8AJU[2]\ : NOR2B - port map(A => N_500, B => \romdata_0_a19_0[25]\, Y => - \romdata_0_a19_1[25]\); - - \addr_0_RNI4PM21[5]\ : OR3 - port map(A => N_108, B => \addr_0[5]_net_1\, C => N_507, Y - => N_295); - - \romdata_0_RNO_6[13]\ : OA1 - port map(A => N_438, B => \romdata_0_a19_2_0[13]\, C => - \romdata_0_1[13]\, Y => \romdata_0_2[13]\); - - \addr_RNIHIMCE[3]\ : OR3C - port map(A => \romdata_0_5[1]\, B => \romdata_0_4[1]\, C - => \romdata_0_7[1]\, Y => hrdata_1); - - \addr_RNIHANR[5]\ : OR2 - port map(A => N_437, B => N_430, Y => N_465); - - \addr_RNIGTGC[2]\ : OR2 - port map(A => \addr_0[5]_net_1\, B => \addr[2]_net_1\, Y - => N_122); - - \addr_RNI5P811[2]\ : NOR2A - port map(A => \addr[2]_net_1\, B => N_472, Y => N_514); - - \addr_0_RNIER1P[4]\ : NOR2A - port map(A => \addr_0[4]_net_1\, B => N_430_0, Y => N_484); - - \addr_RNILF7D7[5]\ : NOR3C - port map(A => \romdata_i_8[20]\, B => N_328, C => N_334, Y - => \romdata_i_15[20]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \addr_0_RNIE9OS5[3]\ : NOR3C - port map(A => \romdata_i_6[24]\, B => \romdata_i_5[24]\, C - => N_519, Y => \romdata_i_12[24]\); - - \addr_RNIUJOR1[9]\ : OA1 - port map(A => \addr_0_RNIP9101_1[6]_net_1\, B => N_463, C - => \addr[9]_net_1\, Y => N_306); - - \addr_0_RNIQ7881[2]\ : OR3B - port map(A => \romdata_i_a19_6_0[31]\, B => N_110, C => - N_116, Y => N_419); - - \addr_0_RNI4PM21[3]\ : OR3A - port map(A => \addr_0[3]_net_1\, B => N_109, C => N_470, Y - => N_399); - - \addr_0_RNI1PM21[3]\ : OR2 - port map(A => N_519, B => N_428, Y => N_285); - - \romdata_0_RNO_6[26]\ : NOR3C - port map(A => N_153_i, B => \romdata_0_1[26]\, C => N_286_i, - Y => \romdata_0_5[26]\); - - \addr_RNI2ANR_0[3]\ : NOR2A - port map(A => N_451, B => N_437, Y => - \addr_RNI2ANR_0[3]_net_1\); - - \addr_RNILT2B[5]\ : OR2 - port map(A => \addr[5]_net_1\, B => \addr[4]_net_1\, Y => - N_166); - - \addr_RNIQT2B_1[6]\ : OR2A - port map(A => \addr[8]_net_1\, B => \addr[6]_net_1\, Y => - N_138); - - \addr_RNIBKSO1[8]\ : OA1A - port map(A => \romdata_i_a19_10_0[24]\, B => N_110, C => - N_368, Y => \romdata_i_5[24]\); - - \addr_0_RNIPFUH2[3]\ : NOR2B - port map(A => N_298, B => N_384, Y => \romdata_0_7[25]\); - - \addr_0_RNIP0DC2[5]\ : OA1A - port map(A => \romdata_i_a19_10_0[31]\, B => N_114, C => - N_415, Y => \romdata_i_0[31]\); - - \addr_0_RNIBCGJ[2]\ : OA1A - port map(A => \addr_0[6]_net_1\, B => \addr[7]_net_1\, C - => \addr_0[2]_net_1\, Y => \romdata_0_a19_0[25]\); - - \addr_RNIMU1M2[8]\ : OA1A - port map(A => N_463, B => N_438, C => N_457, Y => - \romdata_0_o19_0_0[5]\); - - \addr_RNIER5M[7]\ : OR2A - port map(A => N_502, B => \addr[7]_net_1\, Y => N_326); - - \addr_RNI1VF3A[6]\ : OR3 - port map(A => N_263, B => \romdata_0_0[5]\, C => N_196, Y - => hrdata_5); - - \addr_RNI0R1P[2]\ : OR2 - port map(A => N_114, B => N_105, Y => N_450); - - \addr_0_RNIR7881[4]\ : OR3A - port map(A => N_481, B => N_110, C => N_428, Y => N_252); - - \addr_RNIT7M91[4]\ : OR3 - port map(A => N_122, B => N_430_0, C => N_445, Y => N_304); - - \addr_RNI7ANR_0[3]\ : NOR2A - port map(A => N_156, B => N_446, Y => N_410); - - \addr_0_RNIJMLG1[6]\ : OR3A - port map(A => \romdata_0_a19_1_0[21]\, B => N_122, C => - N_430_0, Y => N_338); - - \addr_0_RNIDRJN[4]\ : NOR2A - port map(A => \addr_0[4]_net_1\, B => N_469, Y => N_508); - - \addr_0_RNI6A5T[4]\ : OR3 - port map(A => N_126, B => \addr_0[4]_net_1\, C => N_428, Y - => N_376); - - \romdata_0_RNO_0[13]\ : AND2 - port map(A => \romdata_0_7[13]\, B => - \romdata_0_RNO_2[13]_net_1\, Y => \romdata_0_8[13]\); - - \addr_RNIGN6Q3[4]\ : NOR3C - port map(A => N_300, B => N_303, C => N_241, Y => - \romdata_0_1[15]\); - - \addr_0_RNI3A5T[9]\ : OR3B - port map(A => \addr_0[9]_net_1\, B => N_108, C => N_109, Y - => N_360); - - \addr_RNI0P811[8]\ : OR3B - port map(A => N_116, B => \addr[8]_net_1\, C => N_441, Y - => N_414); - - \romdata_0_RNO_4[13]\ : NOR3C - port map(A => N_286_i, B => N_281, C => N_287, Y => - \romdata_0_5[13]\); - - \addr_RNIRO441[9]\ : NOR2 - port map(A => N_490, B => N_450, Y => N_398); - - \addr_RNIPMPD1[4]\ : AO1A - port map(A => \addr[4]_net_1\, B => \addr[6]_net_1\, C => - N_495, Y => \addr_RNIPMPD1[4]_net_1\); - - \addr_RNIONOO3[3]\ : NOR3A - port map(A => N_495, B => N_259, C => N_342, Y => - \romdata_0_7[1]\); - - \addr_0_RNIV1CN4[3]\ : NOR2A - port map(A => N_278, B => N_134, Y => \romdata_0_0[11]\); - - \addr_0_RNIQO441[3]\ : OR3C - port map(A => N_479, B => \romdata_i_a19_4_0[20]\, C => - N_105, Y => N_323); - - \romdata_0_RNO_11[13]\ : OR3B - port map(A => \addr[9]_net_1\, B => N_162_i_i_0, C => N_109, - Y => N_282); - - \addr_0_RNI5RJN[3]\ : OR2A - port map(A => \addr_0[3]_net_1\, B => N_441, Y => N_519); - - \addr_RNI3PM21[3]\ : OR3A - port map(A => \addr[3]_net_1\, B => N_122, C => N_430, Y - => N_495); - - \addr_0_RNIP9101_1[6]\ : NOR2A - port map(A => \addr_0[6]_net_1\, B => N_450, Y => - \addr_0_RNIP9101_1[6]_net_1\); - - \addr_0_RNIETUD[2]\ : NOR2A - port map(A => \addr_0[6]_net_1\, B => \addr_0[2]_net_1\, Y - => \romdata_0_a19_5_0[1]\); - - \addr_0_RNI9A5T[4]\ : OR3A - port map(A => \addr_0[4]_net_1\, B => N_448, C => N_132, Y - => \romdata_0_a19_1[23]\); - - \addr[4]\ : DFN1 - port map(D => haddr(4), CLK => lclk_c, Q => \addr[4]_net_1\); - - \addr_RNIFH982[9]\ : AO1C - port map(A => N_172, B => N_450, C => \addr[9]_net_1\, Y - => N_301); - - \romdata_0_o19_RNIJDSPD[21]\ : OR3C - port map(A => \romdata_0_7[21]\, B => \romdata_0_6[21]\, C - => \romdata_0_8[21]\, Y => hrdata_21); - - \addr_RNI41382[3]\ : OR2B - port map(A => N_455, B => N_454, Y => N_148); - - \addr_RNIECKG[5]\ : NOR2A - port map(A => \addr[5]_net_1\, B => N_107, Y => N_478); - - \addr_RNIDANR[8]\ : NOR2 - port map(A => N_436, B => N_108, Y => N_492); - - \romdata_0_o19[21]\ : NOR2 - port map(A => N_443, B => N_236, Y => N_133_i); - - \addr_0_RNIP7M91[5]\ : OR3 - port map(A => N_507, B => N_105, C => N_135, Y => - \addr_0_RNIP7M91[5]_net_1\); - - \addr[2]\ : DFN1 - port map(D => haddr(2), CLK => lclk_c, Q => \addr[2]_net_1\); - - \addr_RNIJT2B_0[3]\ : OR2A - port map(A => \addr[3]_net_1\, B => \addr[4]_net_1\, Y => - N_116); - - \romdata_0_RNO_9[26]\ : OR2B - port map(A => N_489, B => N_149_i_i_0, Y => N_387); - - \addr_RNIME455[8]\ : NOR3C - port map(A => \romdata_0_0[23]\, B => N_264, C => N_354, Y - => \romdata_0_3[23]\); - - \addr_0_RNIGTUD[4]\ : OR2 - port map(A => \addr_0[6]_net_1\, B => \addr_0[4]_net_1\, Y - => N_151); - - \addr_0_RNI5L584[4]\ : NOR3B - port map(A => N_313, B => \addr_0_RNIP7M91[5]_net_1\, C => - N_302, Y => \romdata_0_2[19]\); - - \addr_RNICD1T2[3]\ : NOR3C - port map(A => N_323, B => N_330, C => N_320, Y => - \romdata_i_6[20]\); - - \addr_0_RNIETUD[5]\ : XNOR2 - port map(A => \addr_0[3]_net_1\, B => \addr_0[5]_net_1\, Y - => N_135); - - \addr_RNIS12J4[4]\ : NOR3C - port map(A => \romdata_0_0[2]\, B => N_253, C => N_249, Y - => \romdata_0_2[2]\); - - \addr_RNI28Q61[2]\ : NOR2 - port map(A => N_465, B => N_136_i, Y => N_525); - - \addr_RNI33EU1[7]\ : AO1D - port map(A => \romdata_0_a19_0_0[30]\, B => N_442, C => - N_410, Y => \romdata_0_0[30]\); - - \addr_RNI6R5M[2]\ : NOR2 - port map(A => N_131, B => N_107, Y => N_463); - - \addr_0_RNI6S043[4]\ : NOR3B - port map(A => N_403, B => N_402, C => N_508, Y => - \romdata_0_1[28]\); - - \addr_RNI3VJ0A[5]\ : NOR3C - port map(A => \romdata_0_3[0]\, B => \romdata_0_2[0]\, C - => \romdata_0_4[0]\, Y => \romdata_0_6[0]\); - - \addr_RNISMBC1_3[8]\ : NOR2A - port map(A => N_516, B => N_436, Y => N_439); - - \romdata_0_RNO_8[26]\ : OR3 - port map(A => N_114, B => N_428, C => N_109, Y => N_393); - - \addr_RNISMBC1[5]\ : OR2A - port map(A => N_492, B => N_446, Y => N_255); - - \addr_RNIJT2B[2]\ : OR2B - port map(A => \addr[5]_net_1\, B => \addr[2]_net_1\, Y => - N_131); - - \addr_RNIKR5M[4]\ : NOR2 - port map(A => \addr[4]_net_1\, B => N_430, Y => N_512); - - \addr_RNISMBC1[4]\ : OR2A - port map(A => N_525, B => \addr[4]_net_1\, Y => N_266); - - \addr_RNI6CGJ[2]\ : OR2 - port map(A => \addr[2]_net_1\, B => N_114, Y => N_471); - - \addr_0_RNISFGG2[4]\ : OA1 - port map(A => N_156, B => \romdata_0_a19_1[23]\, C => N_252, - Y => \romdata_0_0[23]\); - - \addr_RNI2ANR[5]\ : OR2 - port map(A => N_446, B => N_107, Y => N_452); - - \addr_0_RNIRNSL3[3]\ : OR3 - port map(A => N_270, B => N_439, C => N_262, Y => - \romdata_0_0[5]\); - - \addr_0_RNITS0GA[9]\ : NOR3C - port map(A => \romdata_0_4[23]\, B => \romdata_0_3[23]\, C - => N_316, Y => \romdata_0_7[23]\); - - \addr_0_RNIUOM21[2]\ : OR3C - port map(A => N_110, B => \addr_0[2]_net_1\, C => N_459, Y - => N_234); - - \addr_0_RNIIC2I[4]\ : ZOR3I - port map(A => \addr[7]_net_1\, B => \addr[8]_net_1\, C => - \addr_0[4]_net_1\, Y => \addr_0_RNIIC2I[4]_net_1\); - - \addr_0_RNIDVA55[4]\ : OR3C - port map(A => N_310, B => N_440, C => N_277, Y => hrdata_10); - - \addr_0_RNI4AOS5[6]\ : NOR3C - port map(A => N_299, B => \romdata_0_1[14]\, C => N_298, Y - => \romdata_0_4[14]\); - - \addr_RNIPMPD1[3]\ : OR2A - port map(A => N_127, B => N_495, Y => N_257); - - \addr_0_RNIO74B1[6]\ : OR2B - port map(A => \romdata_0_a19_0[21]\, B => N_484, Y => N_336); - - \addr_RNINT2B[4]\ : NOR2B - port map(A => \addr[7]_net_1\, B => \addr[4]_net_1\, Y => - N_499); - - \addr_RNIBCKG[3]\ : OR2 - port map(A => \addr[3]_net_1\, B => N_105, Y => N_143); - - \addr_0_RNIP8PH3[2]\ : OA1C - port map(A => \romdata_0_a19_5_0[1]\, B => N_472, C => - N_240, Y => \romdata_0_5[1]\); - - \addr_0_RNIU7881[4]\ : OR2B - port map(A => \romdata_0_a19_2_0[28]\, B => - \romdata_0_a19_2_1[28]\, Y => N_403); - - \addr_RNIPMPD1_1[3]\ : OR2A - port map(A => N_485, B => N_116, Y => N_345); - - \addr_RNI18Q61[2]\ : NOR2A - port map(A => N_511, B => N_124, Y => N_262); - - \addr_RNIU7Q61[2]\ : OR3 - port map(A => N_107, B => N_428, C => N_441, Y => N_260); - - \romdata_0_RNO_10[26]\ : OR3A - port map(A => N_114, B => \addr[2]_net_1\, C => N_507, Y - => N_388); - - \addr_RNIHT2B[2]\ : XOR2 - port map(A => \addr[3]_net_1\, B => \addr[2]_net_1\, Y => - N_136_i); - - \addr_RNI0T5EK[8]\ : NOR3C - port map(A => \romdata_i_12[31]\, B => \romdata_i_11[31]\, - C => \romdata_i_15[31]\, Y => N_103_i_0); - - \romdata_0_a19_5_RNO[14]\ : AND2 - port map(A => \addr_0[6]_net_1\, B => \addr_0[2]_net_1\, Y - => \romdata_0_a19_5_0[14]\); - - \addr_RNI48Q61_1[5]\ : OR2A - port map(A => N_492, B => N_110, Y => N_298); - - \addr_RNISMBC1_2[8]\ : OR2 - port map(A => N_473, B => N_436, Y => N_258); - - \addr_RNIGTGC[4]\ : XNOR2 - port map(A => \addr_0[3]_net_1\, B => \addr[4]_net_1\, Y - => N_112); - - \addr_RNIQT2B_0[6]\ : OR2B - port map(A => \addr[8]_net_1\, B => \addr[6]_net_1\, Y => - N_449); - - \addr_RNINT2B_1[5]\ : OR2 - port map(A => \addr[6]_net_1\, B => \addr[5]_net_1\, Y => - N_448); - - \addr_RNIQCKG[9]\ : OR3B - port map(A => \addr[7]_net_1\, B => \addr[8]_net_1\, C => - \addr[9]_net_1\, Y => N_430); - - \addr_0_RNIP74B1[9]\ : OR3A - port map(A => N_109, B => N_114, C => N_430_0, Y => N_374); - - \romdata_0_RNO_1[26]\ : OR2A - port map(A => \addr[3]_net_1\, B => N_465, Y => - \romdata_0_RNO_1[26]_net_1\); - - \addr_0_RNIR7881[5]\ : OR3 - port map(A => N_107, B => N_428, C => N_442, Y => N_253); - - \addr_0_RNII2G82[9]\ : OA1 - port map(A => N_127, B => \romdata_0_a19_1_0[17]\, C => - \addr_0_RNIQ9T21[9]_net_1\, Y => \romdata_0_0[17]\); - - \addr_0_RNI8C2I[4]\ : NOR2B - port map(A => \addr_0[4]_net_1\, B => N_124, Y => - \romdata_0_a19_2_0[28]\); - - \addr[6]\ : DFN1 - port map(D => haddr(6), CLK => lclk_c, Q => \addr[6]_net_1\); - - \addr_0_RNIP7M91[9]\ : NOR2 - port map(A => \romdata_0_a19_5_0[21]\, B => N_505, Y => - N_342); - - \addr_0_RNI7CUK[6]\ : NOR2A - port map(A => \addr_0[6]_net_1\, B => N_114, Y => - \romdata_i_a19_11_0[31]\); - - \addr_0_RNIGM3I1[3]\ : NOR3A - port map(A => N_484, B => N_442, C => \addr_0[3]_net_1\, Y - => N_279); - - \addr_RNISMBC1[6]\ : OR2A - port map(A => N_494, B => N_106_i, Y => N_267); - - \addr_RNIAIH22[6]\ : AO1 - port map(A => N_433, B => N_432, C => N_131, Y => N_440); - - \addr_RNICQPA3[9]\ : NOR3 - port map(A => N_236, B => N_443, C => N_497, Y => N_197_i); - - \addr_0_RNI1AJU[4]\ : OR3 - port map(A => \addr_0[4]_net_1\, B => \addr[8]_net_1\, C - => N_442, Y => N_377); - - \addr_RNI1P811[9]\ : OR2B - port map(A => N_493, B => N_108, Y => N_375); - - \addr_0_RNIDTUD[2]\ : NOR2A - port map(A => \addr_0[5]_net_1\, B => \addr_0[2]_net_1\, Y - => \romdata_i_a19_0_0[24]\); - - \addr_0_RNIAC2I[6]\ : NOR2 - port map(A => \addr_0[6]_net_1\, B => N_136_i, Y => - \romdata_0_a19_0[21]\); - - \addr[3]\ : DFN1 - port map(D => haddr(3), CLK => lclk_c, Q => \addr[3]_net_1\); - - \addr_RNIMM7F1_0[6]\ : AOI1B - port map(A => \romdata_i_a19_1_1[24]\, B => N_131, C => - N_363, Y => \romdata_i_0[24]\); - - \addr_RNI18Q61[8]\ : OR3 - port map(A => N_109, B => N_116, C => N_436, Y => N_354); - - \addr_RNI48Q61_0[5]\ : NOR3 - port map(A => N_107, B => N_437, C => N_438, Y => N_236); - - \addr_0_RNIUFUH2[5]\ : OA1A - port map(A => N_479, B => N_472, C => N_304, Y => - \romdata_0_6[15]\); - - \addr_RNIPCKG[9]\ : OR2 - port map(A => \addr[9]_net_1\, B => N_138, Y => N_507); - - \addr_RNIMM7F1[6]\ : NOR2A - port map(A => N_515, B => \addr[6]_net_1\, Y => N_263); - - \addr_0_RNI1IR62[4]\ : OA1A - port map(A => \romdata_0_a19_1[25]\, B => N_108, C => N_376, - Y => \romdata_0_0[25]\); - - \addr_RNIPMPD1_0[3]\ : NOR3 - port map(A => N_110, B => N_143, C => N_430_0, Y => N_461); - - \addr_RNIOEDK7[8]\ : NOR3C - port map(A => N_414, B => \romdata_i_4[31]\, C => - \romdata_i_8[31]\, Y => \romdata_i_12[31]\); - - \addr_0_RNIPMPD1_0[9]\ : OR2 - port map(A => N_473, B => N_430_0, Y => N_268); - - \addr_0_RNI01VA2[2]\ : NOR3C - port map(A => N_319, B => \addr_RNIGR5M[3]_net_1\, C => - \addr_RNIER5M_0[9]_net_1\, Y => \romdata_i_2[20]\); - - \addr_RNI3A5T[7]\ : OR2B - port map(A => N_481, B => N_480, Y => N_368); - - \addr_0_RNITF2F2[9]\ : OA1A - port map(A => \romdata_0_a19_0[29]\, B => N_436, C => N_397, - Y => \romdata_0_1[29]\); - - \addr_0_RNIGC2I[2]\ : NOR2B - port map(A => \addr_0[2]_net_1\, B => N_468, Y => - \romdata_i_a19_6_0[31]\); - - \addr_RNIJPHG3[6]\ : NOR3C - port map(A => \romdata_i_8[24]\, B => N_364, C => N_369, Y - => \romdata_i_14[24]\); - - \addr_RNIMM7F1[2]\ : OR3B - port map(A => N_136_i, B => N_484, C => N_448, Y => N_274); - - \addr_0_RNIUL4J6[9]\ : OR3C - port map(A => N_273, B => \romdata_0_0[8]\, C => - \romdata_0_1[8]\, Y => hrdata_8); - - \addr_RNI11DC2[5]\ : OA1A - port map(A => N_509, B => N_471, C => N_243, Y => - \romdata_0_6[23]\); - - \addr_0_RNI3QPA3[2]\ : NOR3C - port map(A => N_235, B => N_234, C => N_238, Y => - \romdata_0_4[0]\); - - \addr_RNIER5M_0[6]\ : OR2A - port map(A => N_459, B => \addr[6]_net_1\, Y => N_432); - - \addr_RNICR5M[3]\ : NOR2A - port map(A => N_156, B => N_109, Y => N_460); - - \addr_0_RNI08881[5]\ : OR3A - port map(A => N_479, B => N_105, C => N_438, Y => N_352); - - \addr_0_RNITO441[5]\ : OR2B - port map(A => \romdata_i_a19_15_0[24]\, B => N_481, Y => - N_371); - - \addr_RNI7AFD8[9]\ : OR3B - port map(A => N_310, B => N_440, C => \romdata_0_1[18]\, Y - => hrdata_18); - - \addr_RNI0P811_0[8]\ : OR2A - port map(A => N_516, B => \addr[8]_net_1\, Y => N_369); - - \addr_RNINT2B[2]\ : NOR2A - port map(A => \addr[9]_net_1\, B => \addr[2]_net_1\, Y => - N_291_1); - - \addr_RNIMM7F1[4]\ : OR3A - port map(A => N_112, B => N_122, C => N_503, Y => - \addr_RNIMM7F1[4]_net_1\); - - \romdata_0_o19_RNIFAQ64[21]\ : AND2 - port map(A => N_133_i, B => \romdata_0_4[21]\, Y => - \romdata_0_6[21]\); - - \addr_RNIMH982[8]\ : OA1A - port map(A => \romdata_i_a19_0[20]\, B => N_471, C => N_329, - Y => \romdata_i_9[20]\); - - \addr_RNI6R5M_0[2]\ : NOR2 - port map(A => N_126, B => N_108, Y => N_256_1); - - \addr_RNISON36[6]\ : AO1D - port map(A => N_450, B => N_16427_tz, C => - \romdata_0_1[22]\, Y => hrdata_22); - - \addr_RNISMBC1_1[8]\ : NOR3 - port map(A => N_116, B => N_441, C => N_470, Y => N_462); - - \addr_RNIMDS2F[4]\ : OR3C - port map(A => \addr_RNIPMPD1[4]_net_1\, B => - \romdata_0_6[0]\, C => N_155_i, Y => hrdata_0); - - \addr_RNI8IH22[5]\ : NOR3C - port map(A => N_326, B => N_324, C => N_327, Y => - \romdata_i_4[20]\); - - \addr_0_RNIS9101[9]\ : OR2A - port map(A => \addr_0[9]_net_1\, B => N_450, Y => N_286_i); - - \addr_RNISMBC1_0[3]\ : NOR3 - port map(A => N_110, B => N_143, C => N_436, Y => N_312); - - \addr_RNIIDJR2[6]\ : AOI1B - port map(A => N_494, B => N_138, C => N_271, Y => - \romdata_0_1[8]\); - - \addr_RNI1P811[3]\ : OR3A - port map(A => N_117_i, B => N_469, C => \addr[3]_net_1\, Y - => N_454); - - \addr_0_RNI66K24[9]\ : NOR3C - port map(A => N_362, B => N_323, C => \romdata_i_0[31]\, Y - => \romdata_i_4[31]\); - - \romdata_0_RNO_7[13]\ : OR2A - port map(A => N_492, B => N_131, Y => N_290); - - \addr_RNIIT2B_0[2]\ : OR2 - port map(A => \addr[4]_net_1\, B => \addr[2]_net_1\, Y => - N_105); - - \addr_RNI6ANR[9]\ : OR2A - port map(A => N_459, B => N_109, Y => N_341); - - \addr_RNI2A5T[3]\ : OR3A - port map(A => \addr[7]_net_1\, B => N_442, C => - \addr[3]_net_1\, Y => N_367); - - \romdata_0_a19_5_RNIULR7H[14]\ : OR3B - port map(A => \romdata_0_5[14]\, B => \romdata_0_8[14]\, C - => N_185, Y => hrdata_14); - - \addr_RNI7R5M[3]\ : NOR2 - port map(A => N_109, B => N_108, Y => - \addr_RNI7R5M[3]_net_1\); - - \addr_0_RNIFDJR2[4]\ : NOR3C - port map(A => \addr_0_RNI1PM21[4]_net_1\, B => N_332, C => - N_331, Y => \romdata_i_11[20]\); - - \romdata_0_RNO_8[13]\ : OR2A - port map(A => N_170, B => N_430, Y => N_281); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_bootloader is - - port( haddr : in std_logic_vector(9 downto 2); - hrdata_26 : out std_logic; - hrdata_13 : out std_logic; - hrdata_8 : out std_logic; - hrdata_5 : out std_logic; - hrdata_29 : out std_logic; - hrdata_18 : out std_logic; - hrdata_6 : out std_logic; - hrdata_19 : out std_logic; - hrdata_17 : out std_logic; - hrdata_7 : out std_logic; - hrdata_16 : out std_logic; - hrdata_30 : out std_logic; - hrdata_9 : out std_logic; - hrdata_25 : out std_logic; - hrdata_27 : out std_logic; - hrdata_21 : out std_logic; - hrdata_3 : out std_logic; - hrdata_0 : out std_logic; - hrdata_1 : out std_logic; - hrdata_23 : out std_logic; - hrdata_4 : out std_logic; - hrdata_28 : out std_logic; - hrdata_14 : out std_logic; - hrdata_22 : out std_logic; - hrdata_15 : out std_logic; - hrdata_2 : out std_logic; - hrdata_11 : out std_logic; - hrdata_10 : out std_logic; - hrdata_12 : out std_logic; - prdata : out std_logic_vector(31 downto 0); - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - pwdata_1_0 : in std_logic; - pwdata_31 : in std_logic; - pwdata_30 : in std_logic; - pwdata_29 : in std_logic; - pwdata_28 : in std_logic; - pwdata_27 : in std_logic; - pwdata_26 : in std_logic; - pwdata_25 : in std_logic; - pwdata_24 : in std_logic; - pwdata_23 : in std_logic; - pwdata_22 : in std_logic; - pwdata_21 : in std_logic; - pwdata_20 : in std_logic; - pwdata_19 : in std_logic; - pwdata_18 : in std_logic; - pwdata_17 : in std_logic; - pwdata_16 : in std_logic; - pwdata_15 : in std_logic; - pwdata_14 : in std_logic; - pwdata_13 : in std_logic; - pwdata_12 : in std_logic; - pwdata_11 : in std_logic; - pwdata_10 : in std_logic; - pwdata_9 : in std_logic; - pwdata_8 : in std_logic; - pwdata_7 : in std_logic; - pwdata_6 : in std_logic; - pwdata_5 : in std_logic; - pwdata_2 : in std_logic; - pwdata_0 : in std_logic; - N_103_i_0 : out std_logic; - N_90_i_0 : out std_logic; - N_95_i_0 : out std_logic; - rstraw_c : in std_logic; - lclk_c : in std_logic; - rdata60_4 : in std_logic; - N_6459 : in std_logic; - rdata59_4 : in std_logic; - readdata55_3 : in std_logic; - rdata62_3 : in std_logic; - N_750 : in std_logic; - un1_apbi_0 : in std_logic; - rdata60_4_0 : in std_logic; - N_796 : in std_logic - ); - -end lpp_bootloader; - -architecture DEF_ARCH of lpp_bootloader is - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component ahbrom - port( hrdata_12 : out std_logic; - hrdata_10 : out std_logic; - hrdata_11 : out std_logic; - hrdata_2 : out std_logic; - hrdata_15 : out std_logic; - hrdata_22 : out std_logic; - hrdata_14 : out std_logic; - hrdata_28 : out std_logic; - hrdata_4 : out std_logic; - hrdata_23 : out std_logic; - hrdata_1 : out std_logic; - hrdata_0 : out std_logic; - hrdata_3 : out std_logic; - hrdata_21 : out std_logic; - hrdata_27 : out std_logic; - hrdata_25 : out std_logic; - hrdata_9 : out std_logic; - hrdata_30 : out std_logic; - hrdata_16 : out std_logic; - hrdata_7 : out std_logic; - hrdata_17 : out std_logic; - hrdata_19 : out std_logic; - hrdata_6 : out std_logic; - hrdata_18 : out std_logic; - hrdata_29 : out std_logic; - hrdata_5 : out std_logic; - hrdata_8 : out std_logic; - hrdata_13 : out std_logic; - hrdata_26 : out std_logic; - haddr : in std_logic_vector(9 downto 2) := (others => 'U'); - N_95_i_0 : out std_logic; - N_90_i_0 : out std_logic; - N_103_i_0 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1E1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_6452_0, config_start_execution_1_sqmuxa_0_a2_0_0, - addr_start_execution_1_sqmuxa_0, N_6452, - config_wait_on_boot_0_sqmuxa, N_6440, config_wait_on_boot, - N_6441, config_start_execution, \prdata_8[0]\, N_6442, - addr_start_execution_1_sqmuxa, - config_start_execution_1_sqmuxa, \prdata_8[1]\, - \addr_start_execution[1]\, \prdata_8[2]\, - \addr_start_execution[2]\, \prdata_8[3]\, - \addr_start_execution[3]\, \prdata_8[4]\, - \addr_start_execution[4]\, \prdata_8[5]\, - \addr_start_execution[5]\, \prdata_8[6]\, - \addr_start_execution[6]\, \prdata_8[7]\, - \addr_start_execution[7]\, \prdata_8[8]\, - \addr_start_execution[8]\, \prdata_8[9]\, - \addr_start_execution[9]\, \prdata_8[10]\, - \addr_start_execution[10]\, \prdata_8[11]\, - \addr_start_execution[11]\, \prdata_8[12]\, - \addr_start_execution[12]\, \prdata_8[13]\, - \addr_start_execution[13]\, \prdata_8[14]\, - \addr_start_execution[14]\, \prdata_8[16]\, - \addr_start_execution[16]\, \prdata_8[17]\, - \addr_start_execution[17]\, \prdata_8[18]\, - \addr_start_execution[18]\, \prdata_8[19]\, - \addr_start_execution[19]\, \prdata_8[20]\, - \addr_start_execution[20]\, \prdata_8[21]\, - \addr_start_execution[21]\, \prdata_8[22]\, - \addr_start_execution[22]\, \prdata_8[23]\, - \addr_start_execution[23]\, \prdata_8[24]\, - \addr_start_execution[24]\, \prdata_8[25]\, - \addr_start_execution[25]\, \prdata_8[26]\, - \addr_start_execution[26]\, \prdata_8[27]\, - \addr_start_execution[27]\, \prdata_8[28]\, - \addr_start_execution[28]\, \prdata_8[29]\, - \addr_start_execution[29]\, \prdata_8[30]\, - \addr_start_execution[30]\, \prdata_8[31]\, - \addr_start_execution[31]\, \prdata_8[15]\, - \addr_start_execution[15]\, \addr_start_execution[0]\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : ahbrom - Use entity work.ahbrom(DEF_ARCH); -begin - - - \prdata_RNO[30]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[30]\, C - => rdata60_4, Y => \prdata_8[30]\); - - \prdata_RNO[7]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[7]\, C - => rdata60_4_0, Y => \prdata_8[7]\); - - \prdata_RNO[16]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[16]\, C - => rdata60_4_0, Y => \prdata_8[16]\); - - \prdata_RNO[6]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[6]\, C - => rdata60_4_0, Y => \prdata_8[6]\); - - \reg.addr_start_execution[1]\ : DFN1E1C0 - port map(D => pwdata_1_0, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[1]\); - - \prdata_RNO[24]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[24]\, C - => rdata60_4, Y => \prdata_8[24]\); - - \reg.addr_start_execution[23]\ : DFN1E1C0 - port map(D => pwdata_23, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[23]\); - - \prdata[29]\ : DFN1C0 - port map(D => \prdata_8[29]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(29)); - - \prdata[14]\ : DFN1C0 - port map(D => \prdata_8[14]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(14)); - - \reg.config_start_execution_RNO\ : NOR2A - port map(A => N_6452_0, B => N_6459, Y => - config_start_execution_1_sqmuxa); - - \reg.addr_start_execution[20]\ : DFN1E1C0 - port map(D => pwdata_20, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[20]\); - - \reg.addr_start_execution[29]\ : DFN1E1C0 - port map(D => pwdata_29, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[29]\); - - \reg.addr_start_execution[28]\ : DFN1E1C0 - port map(D => pwdata_28, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[28]\); - - \prdata_RNO[3]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[3]\, C - => rdata60_4_0, Y => \prdata_8[3]\); - - \prdata[4]\ : DFN1C0 - port map(D => \prdata_8[4]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(4)); - - \prdata_RNO[27]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[27]\, C - => rdata60_4, Y => \prdata_8[27]\); - - ahbrom_1 : ahbrom - port map(hrdata_12 => hrdata_12, hrdata_10 => hrdata_10, - hrdata_11 => hrdata_11, hrdata_2 => hrdata_2, hrdata_15 - => hrdata_15, hrdata_22 => hrdata_22, hrdata_14 => - hrdata_14, hrdata_28 => hrdata_28, hrdata_4 => hrdata_4, - hrdata_23 => hrdata_23, hrdata_1 => hrdata_1, hrdata_0 - => hrdata_0, hrdata_3 => hrdata_3, hrdata_21 => - hrdata_21, hrdata_27 => hrdata_27, hrdata_25 => hrdata_25, - hrdata_9 => hrdata_9, hrdata_30 => hrdata_30, hrdata_16 - => hrdata_16, hrdata_7 => hrdata_7, hrdata_17 => - hrdata_17, hrdata_19 => hrdata_19, hrdata_6 => hrdata_6, - hrdata_18 => hrdata_18, hrdata_29 => hrdata_29, hrdata_5 - => hrdata_5, hrdata_8 => hrdata_8, hrdata_13 => - hrdata_13, hrdata_26 => hrdata_26, haddr(9) => haddr(9), - haddr(8) => haddr(8), haddr(7) => haddr(7), haddr(6) => - haddr(6), haddr(5) => haddr(5), haddr(4) => haddr(4), - haddr(3) => haddr(3), haddr(2) => haddr(2), N_95_i_0 => - N_95_i_0, N_90_i_0 => N_90_i_0, N_103_i_0 => N_103_i_0, - lclk_c => lclk_c); - - \reg.config_wait_on_boot_RNO\ : NOR3A - port map(A => N_6452_0, B => un1_apbi_0, C => readdata55_3, - Y => config_wait_on_boot_0_sqmuxa); - - \prdata_RNO[15]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[15]\, C - => rdata60_4, Y => \prdata_8[15]\); - - \reg.addr_start_execution[25]\ : DFN1E1C0 - port map(D => pwdata_25, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[25]\); - - \prdata_RNO[19]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[19]\, C - => rdata60_4, Y => \prdata_8[19]\); - - \prdata[25]\ : DFN1C0 - port map(D => \prdata_8[25]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(25)); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg.addr_start_execution[26]\ : DFN1E1C0 - port map(D => pwdata_26, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[26]\); - - \prdata[10]\ : DFN1C0 - port map(D => \prdata_8[10]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(10)); - - \prdata_RNO[11]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[11]\, C - => rdata60_4_0, Y => \prdata_8[11]\); - - \prdata[2]\ : DFN1C0 - port map(D => \prdata_8[2]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(2)); - - \prdata_RNO[28]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[28]\, C - => rdata60_4, Y => \prdata_8[28]\); - - \reg.addr_start_execution[11]\ : DFN1E1C0 - port map(D => pwdata_11, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[11]\); - - \prdata[31]\ : DFN1C0 - port map(D => \prdata_8[31]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(31)); - - \reg.addr_start_execution[2]\ : DFN1E1C0 - port map(D => pwdata_2, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[2]\); - - \prdata[1]\ : DFN1C0 - port map(D => \prdata_8[1]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(1)); - - \prdata_RNO[4]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[4]\, C - => rdata60_4_0, Y => \prdata_8[4]\); - - \reg.addr_start_execution[9]\ : DFN1E1C0 - port map(D => pwdata_9, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[9]\); - - \prdata[8]\ : DFN1C0 - port map(D => \prdata_8[8]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(8)); - - \reg.addr_start_execution[31]\ : DFN1E1C0 - port map(D => pwdata_31, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[31]\); - - \reg.addr_start_execution[14]\ : DFN1E1C0 - port map(D => pwdata_14, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[14]\); - - \prdata_RNO[2]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[2]\, C - => rdata60_4_0, Y => \prdata_8[2]\); - - \prdata_RNO[10]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[10]\, C - => rdata60_4_0, Y => \prdata_8[10]\); - - \prdata[12]\ : DFN1C0 - port map(D => \prdata_8[12]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(12)); - - \prdata_RNO_2[0]\ : OR3B - port map(A => N_6452, B => \addr_start_execution[0]\, C => - rdata60_4, Y => N_6442); - - \prdata_RNO[12]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[12]\, C - => rdata60_4_0, Y => \prdata_8[12]\); - - \reg.config_start_execution_1_sqmuxa_0_a2_0_RNIS3CH_0\ : - NOR3A - port map(A => N_6452_0, B => rdata60_4_0, C => un1_apbi_0, - Y => addr_start_execution_1_sqmuxa_0); - - \prdata[27]\ : DFN1C0 - port map(D => \prdata_8[27]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(27)); - - \prdata_RNO[13]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[13]\, C - => rdata60_4_0, Y => \prdata_8[13]\); - - \reg.addr_start_execution[8]\ : DFN1E1C0 - port map(D => pwdata_8, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[8]\); - - \reg.addr_start_execution[17]\ : DFN1E1C0 - port map(D => pwdata_17, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[17]\); - - \prdata[19]\ : DFN1C0 - port map(D => \prdata_8[19]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(19)); - - \prdata_RNO[9]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[9]\, C - => rdata60_4_0, Y => \prdata_8[9]\); - - \reg.addr_start_execution[5]\ : DFN1E1C0 - port map(D => pwdata_5, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[5]\); - - \prdata_RNO[1]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[1]\, C - => rdata60_4_0, Y => \prdata_8[1]\); - - \prdata[23]\ : DFN1C0 - port map(D => \prdata_8[23]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(23)); - - \reg.addr_start_execution[6]\ : DFN1E1C0 - port map(D => pwdata_6, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[6]\); - - \prdata_RNO[26]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[26]\, C - => rdata60_4, Y => \prdata_8[26]\); - - \prdata[5]\ : DFN1C0 - port map(D => \prdata_8[5]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(5)); - - \reg.config_start_execution_1_sqmuxa_0_a2_0\ : NOR2 - port map(A => N_796, B => - config_start_execution_1_sqmuxa_0_a2_0_0, Y => N_6452); - - \prdata[26]\ : DFN1C0 - port map(D => \prdata_8[26]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(26)); - - \reg.addr_start_execution[3]\ : DFN1E1C0 - port map(D => pwdata_1_2, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[3]\); - - \prdata_RNO[8]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[8]\, C - => rdata60_4_0, Y => \prdata_8[8]\); - - \reg.addr_start_execution[12]\ : DFN1E1C0 - port map(D => pwdata_12, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[12]\); - - \prdata[30]\ : DFN1C0 - port map(D => \prdata_8[30]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(30)); - - \prdata[15]\ : DFN1C0 - port map(D => \prdata_8[15]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(15)); - - GND_i : GND - port map(Y => \GND\); - - \reg.addr_start_execution[7]\ : DFN1E1C0 - port map(D => pwdata_7, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[7]\); - - \prdata[0]\ : DFN1C0 - port map(D => \prdata_8[0]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(0)); - - \prdata[3]\ : DFN1C0 - port map(D => \prdata_8[3]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(3)); - - \prdata[28]\ : DFN1C0 - port map(D => \prdata_8[28]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(28)); - - \reg.addr_start_execution[21]\ : DFN1E1C0 - port map(D => pwdata_21, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[21]\); - - \prdata_RNO[14]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[14]\, C - => rdata60_4_0, Y => \prdata_8[14]\); - - \reg.config_wait_on_boot\ : DFN1E1P0 - port map(D => pwdata_0, CLK => lclk_c, PRE => rstraw_c, E - => config_wait_on_boot_0_sqmuxa, Q => - config_wait_on_boot); - - \reg.config_start_execution_1_sqmuxa_0_a2_0_0\ : OR2 - port map(A => N_750, B => rdata62_3, Y => - config_start_execution_1_sqmuxa_0_a2_0_0); - - \prdata_RNO[25]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[25]\, C - => rdata60_4, Y => \prdata_8[25]\); - - \prdata_RNO[29]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[29]\, C - => rdata60_4, Y => \prdata_8[29]\); - - \prdata[21]\ : DFN1C0 - port map(D => \prdata_8[21]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(21)); - - \prdata_RNO[21]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[21]\, C - => rdata60_4, Y => \prdata_8[21]\); - - \reg.addr_start_execution[24]\ : DFN1E1C0 - port map(D => pwdata_24, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[24]\); - - \reg.addr_start_execution[13]\ : DFN1E1C0 - port map(D => pwdata_13, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[13]\); - - \prdata[17]\ : DFN1C0 - port map(D => \prdata_8[17]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(17)); - - \reg.config_start_execution_1_sqmuxa_0_a2_0_1_RNIS3CH\ : - NOR3A - port map(A => N_6452_0, B => rdata60_4_0, C => un1_apbi_0, - Y => addr_start_execution_1_sqmuxa); - - \reg.config_start_execution_1_sqmuxa_0_a2_0_1\ : NOR2 - port map(A => N_796, B => - config_start_execution_1_sqmuxa_0_a2_0_0, Y => N_6452_0); - - \reg.addr_start_execution[10]\ : DFN1E1C0 - port map(D => pwdata_10, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[10]\); - - \prdata_RNO[17]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[17]\, C - => rdata60_4_0, Y => \prdata_8[17]\); - - \reg.addr_start_execution[19]\ : DFN1E1C0 - port map(D => pwdata_19, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[19]\); - - \reg.addr_start_execution[18]\ : DFN1E1C0 - port map(D => pwdata_18, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[18]\); - - \prdata_RNO[5]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[5]\, C - => rdata60_4_0, Y => \prdata_8[5]\); - - \prdata[24]\ : DFN1C0 - port map(D => \prdata_8[24]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(24)); - - \prdata_RNO[20]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[20]\, C - => rdata60_4, Y => \prdata_8[20]\); - - \reg.addr_start_execution[27]\ : DFN1E1C0 - port map(D => pwdata_27, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[27]\); - - \prdata[9]\ : DFN1C0 - port map(D => \prdata_8[9]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(9)); - - \prdata_RNO[22]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[22]\, C - => rdata60_4, Y => \prdata_8[22]\); - - \prdata[6]\ : DFN1C0 - port map(D => \prdata_8[6]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(6)); - - \prdata[13]\ : DFN1C0 - port map(D => \prdata_8[13]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(13)); - - \reg.config_start_execution\ : DFN1E1C0 - port map(D => pwdata_0, CLK => lclk_c, CLR => rstraw_c, E - => config_start_execution_1_sqmuxa, Q => - config_start_execution); - - \prdata_RNO_1[0]\ : OR3B - port map(A => N_6452_0, B => config_wait_on_boot, C => - readdata55_3, Y => N_6440); - - \reg.addr_start_execution[30]\ : DFN1E1P0 - port map(D => pwdata_30, CLK => lclk_c, PRE => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[30]\); - - \prdata[16]\ : DFN1C0 - port map(D => \prdata_8[16]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(16)); - - \prdata_RNO[23]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[23]\, C - => rdata60_4, Y => \prdata_8[23]\); - - \prdata_RNO[18]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[18]\, C - => rdata60_4, Y => \prdata_8[18]\); - - \reg.addr_start_execution[15]\ : DFN1E1C0 - port map(D => pwdata_15, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[15]\); - - \reg.addr_start_execution[16]\ : DFN1E1C0 - port map(D => pwdata_16, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[16]\); - - \reg.addr_start_execution[22]\ : DFN1E1C0 - port map(D => pwdata_22, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[22]\); - - \prdata_RNO_0[0]\ : OR3C - port map(A => N_6452_0, B => config_start_execution, C => - rdata59_4, Y => N_6441); - - \prdata[20]\ : DFN1C0 - port map(D => \prdata_8[20]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(20)); - - \prdata_RNO[31]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[31]\, C - => rdata60_4, Y => \prdata_8[31]\); - - \reg.addr_start_execution[0]\ : DFN1E1C0 - port map(D => pwdata_0, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[0]\); - - \prdata_RNO[0]\ : OR3C - port map(A => N_6441, B => N_6440, C => N_6442, Y => - \prdata_8[0]\); - - \prdata[7]\ : DFN1C0 - port map(D => \prdata_8[7]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(7)); - - \prdata[18]\ : DFN1C0 - port map(D => \prdata_8[18]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(18)); - - \reg.addr_start_execution[4]\ : DFN1E1C0 - port map(D => pwdata_1_3, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[4]\); - - \prdata[11]\ : DFN1C0 - port map(D => \prdata_8[11]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(11)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \prdata[22]\ : DFN1C0 - port map(D => \prdata_8[22]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(22)); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_apbreg is - - port( status_full_ack : out std_logic_vector(3 downto 0); - prdata : out std_logic_vector(31 downto 0); - pirq : out std_logic_vector(15 to 15); - pwdata : in std_logic_vector(31 downto 0); - pwdata_1_0 : in std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - paddr_2 : in std_logic_vector(2 to 2); - addr_data_f2 : out std_logic_vector(31 downto 0); - status_new_err_0 : in std_logic_vector(3 downto 0); - status_full_err_0 : in std_logic_vector(3 downto 0); - status_full_0 : in std_logic_vector(3 downto 0); - addr_data_f3 : out std_logic_vector(31 downto 0); - addr_data_f1 : out std_logic_vector(31 downto 0); - nb_burst_available : out std_logic_vector(10 downto 0); - addr_data_f0 : out std_logic_vector(31 downto 0); - nb_snapshot_param : out std_logic_vector(10 downto 0); - delta_snapshot : out std_logic_vector(15 downto 0); - delta_f2_f0 : out std_logic_vector(9 downto 0); - delta_f2_f1 : out std_logic_vector(9 downto 0); - paddr : in std_logic_vector(7 downto 3); - paddr_0 : in std_logic_vector(4 downto 2); - pwdata_0 : in std_logic_vector(11 downto 0); - data_shaping_R0 : out std_logic; - data_shaping_R1 : out std_logic; - un1_apbi_0 : in std_logic; - N_6455 : in std_logic; - rdata61_2 : in std_logic; - burst_f2 : out std_logic; - burst_f0 : out std_logic; - N_232_1 : in std_logic; - enable_f3 : out std_logic; - enable_f2 : out std_logic; - data_shaping_SP1 : out std_logic; - enable_f1 : out std_logic; - N_232_0 : in std_logic; - enable_f0 : out std_logic; - N_769 : in std_logic; - N_116 : in std_logic; - N_749 : in std_logic; - burst_f1 : out std_logic; - data_shaping_SP0 : out std_logic; - Bias_Fails_c : out std_logic; - N_6455_0 : in std_logic; - N_232 : in std_logic; - data_shaping_R1_0 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - data_shaping_R0_0 : out std_logic - ); - -end lpp_top_apbreg; - -architecture DEF_ARCH of lpp_top_apbreg is - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal data_shaping_BW_1_sqmuxa, addr_data_f2_1_sqmuxa_0, - N_168, N_162, prdata_2_sqmuxa_0, N_159, N_69, - prdata_3_sqmuxa_0, prdata_4_sqmuxa_0, - addr_matrix_f1_1_sqmuxa_0_a2_1_0, prdata_5_sqmuxa_0, - prdata_9_sqmuxa_0, N_72, prdata_10_sqmuxa_0, - prdata_12_sqmuxa_0, addr_matrix_f0_0_1_sqmuxa_0, N_71, - addr_matrix_f0_1_1_sqmuxa_0, N_166, - addr_matrix_f1_1_sqmuxa_0, addr_matrix_f2_1_sqmuxa_0, - N_160, addr_data_f0_1_sqmuxa_0, N_168_0, - addr_data_f3_1_sqmuxa_0, addr_data_f1_1_sqmuxa_0, - \delta_f2_f1_m_i[2]\, prdata_15_sqmuxa, - \delta_f2_f0_m_i[2]\, prdata_16_sqmuxa, - \delta_snapshot_m_i[6]\, prdata_14_sqmuxa, - \delta_snapshot_m_i[15]\, \prdata_39_0_iv_2[15]\, - \prdata_39_0_iv_1[15]\, \prdata_39_0_iv_0[15]\, - \prdata_39_0_iv_0[2]\, \prdata_39_0_iv_9[6]\, - \prdata_39_0_iv_6[6]\, \prdata_39_0_iv_4[6]\, - \prdata_39_0_iv_3[6]\, \prdata_39_0_iv_4[15]\, - \prdata_39_0_iv_15[0]\, \addr_data_f1_m_i[0]\, - \addr_data_f0_m_i[0]\, \prdata_39_0_iv_12[0]\, - \prdata_39_0_iv_7[0]\, \prdata_39_0_iv_6[0]\, - \delta_snapshot_m_i[0]\, \prdata_39_0_iv_11[0]\, - \prdata_39_0_iv_5[0]\, \prdata_39_0_iv_4[0]\, - \addr_data_f3_m_i[0]\, \prdata_39_0_iv_10[0]\, - \status_full[0]\, prdata_13_sqmuxa, \addr_data_f2_m_i[0]\, - \addr_matrix_f0_0[0]\, \addr_matrix_f0_1_m_i[0]\, - \addr_matrix_f2[0]\, enable_f0_m_i, prdata_7_sqmuxa, - \addr_matrix_f1_m_i[0]\, \prdata_39_0_iv_1[0]\, - \prdata_39_0_iv_0[0]\, \prdata_39_0_iv_2[0]\, - prdata_18_sqmuxa, status_ready_matrix_f0_0_m_i, - \nb_burst_available_m_i[0]\, prdata_0_sqmuxa, - config_active_interruption_onNewMatrix, - \delta_f2_f0_m_i[0]\, \prdata_39_0_iv_15[1]\, - \addr_data_f1_m_i[1]\, \addr_data_f0_m_i[1]\, - \prdata_39_0_iv_12[1]\, \prdata_39_0_iv_7[1]\, - \prdata_39_0_iv_6[1]\, \delta_snapshot_m_i[1]\, - \prdata_39_0_iv_11[1]\, \prdata_39_0_iv_5[1]\, - \prdata_39_0_iv_4[1]\, \addr_data_f3_m_i[1]\, - \prdata_39_0_iv_10[1]\, \status_full[1]\, - \addr_data_f2_m_i[1]\, \addr_matrix_f0_0[1]\, - \addr_matrix_f0_1_m_i[1]\, \addr_matrix_f2[1]\, - enable_f1_m_i, \addr_matrix_f1_m_i[1]\, - \prdata_39_0_iv_1[1]\, \prdata_39_0_iv_0[1]\, - \prdata_39_0_iv_2[1]\, status_ready_matrix_f0_1_m_i, - \nb_burst_available_m_i[1]\, - config_active_interruption_onError, \delta_f2_f0_m_i[1]\, - \prdata_39_0_iv_13[2]\, \prdata_39_0_iv_7[2]\, - \addr_data_f3_m_i[2]\, \prdata_39_0_iv_9[2]\, - \prdata_39_0_iv_12[2]\, \addr_data_f1_m_i[2]\, - \prdata_39_0_iv_11[2]\, \prdata_39_0_iv_6[2]\, - \prdata_39_0_iv_5[2]\, \delta_snapshot_m_i[2]\, - \status_full[2]\, \addr_data_f2_m_i[2]\, - \prdata_39_0_iv_2[2]\, \prdata_39_0_iv_1[2]\, - \prdata_39_0_iv_4[2]\, \addr_matrix_f0_0[2]\, - \addr_matrix_f0_1_m_i[2]\, \addr_matrix_f2[2]\, - enable_f2_m_i, data_shaping_SP1_m_i, - \addr_matrix_f1_m_i[2]\, status_ready_matrix_f1, - prdata_1_sqmuxa, prdata_17_sqmuxa, - \nb_snapshot_param_m_i[2]\, \prdata_39_0_iv_13[3]\, - \prdata_39_0_iv_7[3]\, \addr_data_f3_m_i[3]\, - \prdata_39_0_iv_9[3]\, \prdata_39_0_iv_12[3]\, - \addr_data_f1_m_i[3]\, \prdata_39_0_iv_11[3]\, - \prdata_39_0_iv_6[3]\, \prdata_39_0_iv_5[3]\, - \delta_snapshot_m_i[3]\, \status_full[3]\, - \addr_data_f2_m_i[3]\, \prdata_39_0_iv_2[3]\, - \prdata_39_0_iv_1[3]\, \prdata_39_0_iv_4[3]\, - \addr_matrix_f0_0[3]\, \addr_matrix_f0_1_m_i[3]\, - \addr_matrix_f2[3]\, enable_f3_m_i, data_shaping_R0_m_i, - \addr_matrix_f1_m_i[3]\, \delta_f2_f1_m_i[3]\, - \delta_f2_f0_m_i[3]\, status_ready_matrix_f2_m_i, - \nb_snapshot_param_m_i[3]\, \prdata_39_0_iv_13[4]\, - \addr_data_f2_m_i[4]\, \status_full_err_m_i[0]\, - \prdata_39_0_iv_10[4]\, \prdata_39_0_iv_12[4]\, - \addr_data_f1_m_i[4]\, \prdata_39_0_iv_11[4]\, - \prdata_39_0_iv_6[4]\, \prdata_39_0_iv_5[4]\, - \delta_snapshot_m_i[4]\, \prdata_39_0_iv_4[4]\, - \prdata_39_0_iv_3[4]\, \addr_data_f3_m_i[4]\, - \addr_matrix_f0_0[4]\, \addr_matrix_f0_1_m_i[4]\, - \addr_matrix_f2[4]\, burst_f0_m_i, \data_shaping_R1_0\, - \addr_matrix_f1_m_i[4]\, \nb_snapshot_param_m_i[4]\, - \nb_burst_available_m_i[4]\, \prdata_39_0_iv_2[4]\, - status_error_anticipating_empty_fifo_m_i, - \prdata_39_0_iv_0[4]\, \delta_f2_f1_m_i[4]\, - \prdata_39_0_iv_12[5]\, \prdata_39_0_iv_9[5]\, - \prdata_39_0_iv_11[5]\, \status_full_err_m_i[1]\, - \prdata_39_0_iv_6[5]\, \addr_data_f0_m_i[5]\, - \prdata_39_0_iv_10[5]\, \prdata_39_0_iv_5[5]\, - \prdata_39_0_iv_4[5]\, \delta_snapshot_m_i[5]\, - \addr_data_f2_m_i[5]\, \prdata_39_0_iv_2[5]\, - \prdata_39_0_iv_1[5]\, \addr_matrix_f0_1_m_i[5]\, - prdata_8_sqmuxa, \addr_matrix_f0_0_m_i[5]\, - \addr_matrix_f1[5]\, \addr_matrix_f2_m_i[5]\, - status_error_bad_component_error_m_i, - \prdata_39_0_iv_0[5]\, \nb_burst_available_m_i[5]\, - \nb_snapshot_param_m_i[5]\, \delta_f2_f1_m_i[5]\, - \prdata_39_0_iv_11[6]\, \addr_data_f3_m_i[6]\, - \addr_data_f2_m_i[6]\, \addr_data_f1_m_i[6]\, - \prdata_39_0_iv_10[6]\, \status_full_err_m_i[2]\, - \prdata_39_0_iv_5[6]\, \addr_data_f0_m_i[6]\, - \addr_matrix_f0_0[6]\, \addr_matrix_f0_1_m_i[6]\, - \addr_matrix_f2[6]\, burst_f2_m_i, \prdata_39_0_iv_1[6]\, - \prdata_39_0_iv_0[6]\, \addr_matrix_f1_m_i[6]\, - \nb_snapshot_param_m_i[6]\, \delta_f2_f1_m_i[6]\, - \prdata_39_0_iv_10[7]\, \prdata_39_0_iv_7[7]\, - \prdata_39_0_iv_9[7]\, \prdata_39_0_iv_6[7]\, - \prdata_39_0_iv_8[7]\, \prdata_39_0_iv_3[7]\, - \addr_matrix_f0_1_m_i[7]\, \delta_snapshot_m_i[7]\, - \addr_data_f2_m_i[7]\, \addr_matrix_f0_0_m_i[7]\, - \addr_matrix_f2_m_i[7]\, \status_full_err_m_i[3]\, - \prdata_39_0_iv_1[7]\, \prdata_39_0_iv_0[7]\, - \addr_matrix_f1_m_i[7]\, \nb_snapshot_param_m_i[7]\, - \delta_f2_f1_m_i[7]\, \prdata_39_0_iv_10[8]\, - \addr_data_f3_m_i[8]\, \addr_data_f2_m_i[8]\, - \addr_data_f1_m_i[8]\, \prdata_39_0_iv_9[8]\, - \prdata_39_0_iv_6[8]\, \prdata_39_0_iv_8[8]\, - \prdata_39_0_iv_3[8]\, \addr_matrix_f0_1_m_i[8]\, - \delta_snapshot_m_i[8]\, \addr_matrix_f0_0_m_i[8]\, - \addr_matrix_f2_m_i[8]\, \status_new_err_m_i[0]\, - \prdata_39_0_iv_1[8]\, \prdata_39_0_iv_0[8]\, - \addr_matrix_f1_m_i[8]\, \nb_burst_available_m_i[8]\, - \nb_snapshot_param_m_i[8]\, \delta_f2_f0_m_i[8]\, - \prdata_39_0_iv_10[9]\, \addr_data_f3_m_i[9]\, - \addr_data_f2_m_i[9]\, \addr_data_f1_m_i[9]\, - \prdata_39_0_iv_9[9]\, \prdata_39_0_iv_6[9]\, - \prdata_39_0_iv_8[9]\, \prdata_39_0_iv_3[9]\, - \addr_matrix_f0_1_m_i[9]\, \delta_snapshot_m_i[9]\, - \addr_matrix_f0_0_m_i[9]\, \addr_matrix_f2_m_i[9]\, - \status_new_err_m_i[1]\, \prdata_39_0_iv_1[9]\, - \prdata_39_0_iv_0[9]\, \addr_matrix_f1_m_i[9]\, - \nb_snapshot_param_m_i[9]\, \delta_f2_f1_m_i[9]\, - \prdata_39_0_iv_8[10]\, \prdata_39_0_iv_5[10]\, - \prdata_39_0_iv_7[10]\, \prdata_39_0_iv_4[10]\, - \prdata_39_0_iv_6[10]\, \prdata_39_0_iv_1[10]\, - \addr_matrix_f0_1_m_i[10]\, \delta_snapshot_m_i[10]\, - \addr_data_f2_m_i[10]\, \addr_matrix_f0_0_m_i[10]\, - \addr_matrix_f2_m_i[10]\, \status_new_err_m_i[2]\, - \nb_snapshot_param_m_i[10]\, \nb_burst_available_m_i[10]\, - \addr_matrix_f1_m_i[10]\, \prdata_39_0_iv_6[11]\, - \addr_data_f2_m_i[11]\, \status_new_err_m_i[3]\, - \addr_data_f1_m_i[11]\, \prdata_39_0_iv_5[11]\, - \prdata_39_0_iv_1[11]\, \prdata_39_0_iv_0[11]\, - \addr_data_f0_m_i[11]\, \prdata_39_0_iv_4[11]\, - \delta_snapshot_m_i[11]\, \addr_matrix_f0_0[11]\, - \addr_matrix_f0_1_m_i[11]\, \addr_matrix_f1[11]\, - \addr_matrix_f2_m_i[11]\, \prdata_39_0_iv_4[30]\, - \prdata_39_0_iv_1[30]\, \prdata_39_0_iv_0[30]\, - \addr_data_f0_m_i[30]\, \prdata_39_0_iv_3[30]\, - \addr_data_f2_m_i[30]\, \addr_matrix_f0_0[30]\, - \addr_matrix_f0_1_m_i[30]\, \addr_matrix_f1[30]\, - \addr_matrix_f2_m_i[30]\, \prdata_39_0_iv_4[20]\, - \prdata_39_0_iv_1[20]\, \prdata_39_0_iv_0[20]\, - \addr_data_f0_m_i[20]\, \prdata_39_0_iv_3[20]\, - \addr_data_f2_m_i[20]\, \addr_matrix_f0_0[20]\, - \addr_matrix_f0_1_m_i[20]\, \addr_matrix_f1[20]\, - \addr_matrix_f2_m_i[20]\, \prdata_39_0_iv_5[12]\, - \addr_data_f1_m_i[12]\, \prdata_39_0_iv_4[12]\, - \prdata_39_0_iv_1[12]\, \prdata_39_0_iv_0[12]\, - \delta_snapshot_m_i[12]\, \prdata_39_0_iv_3[12]\, - \addr_data_f2_m_i[12]\, \addr_matrix_f0_0[12]\, - \addr_matrix_f0_1_m_i[12]\, \addr_matrix_f1[12]\, - \addr_matrix_f2_m_i[12]\, \prdata_39_0_iv_5[13]\, - \addr_data_f1_m_i[13]\, \prdata_39_0_iv_4[13]\, - \prdata_39_0_iv_1[13]\, \prdata_39_0_iv_0[13]\, - \delta_snapshot_m_i[13]\, \prdata_39_0_iv_3[13]\, - \addr_data_f2_m_i[13]\, \addr_matrix_f0_0[13]\, - \addr_matrix_f0_1_m_i[13]\, \addr_matrix_f1[13]\, - \addr_matrix_f2_m_i[13]\, \prdata_39_0_iv_5[14]\, - \addr_data_f1_m_i[14]\, \prdata_39_0_iv_4[14]\, - \prdata_39_0_iv_1[14]\, \prdata_39_0_iv_0[14]\, - \delta_snapshot_m_i[14]\, \prdata_39_0_iv_3[14]\, - \addr_data_f2_m_i[14]\, \addr_matrix_f0_0[14]\, - \addr_matrix_f0_1_m_i[14]\, \addr_matrix_f1[14]\, - \addr_matrix_f2_m_i[14]\, \prdata_39_0_iv_5[15]\, - \addr_data_f1_m_i[15]\, \prdata_39_0_iv_3[15]\, - \addr_data_f2_m_i[15]\, \addr_matrix_f0_0[15]\, - \addr_matrix_f0_1_m_i[15]\, \addr_matrix_f1[15]\, - \addr_matrix_f2_m_i[15]\, \prdata_39_0_iv_4[16]\, - \prdata_39_0_iv_1[16]\, \prdata_39_0_iv_0[16]\, - \addr_data_f0_m_i[16]\, \prdata_39_0_iv_3[16]\, - \addr_data_f2_m_i[16]\, \addr_matrix_f0_0[16]\, - \addr_matrix_f0_1_m_i[16]\, \addr_matrix_f1[16]\, - \addr_matrix_f2_m_i[16]\, \prdata_39_0_iv_4[17]\, - \prdata_39_0_iv_1[17]\, \prdata_39_0_iv_0[17]\, - \addr_data_f0_m_i[17]\, \prdata_39_0_iv_3[17]\, - \addr_data_f2_m_i[17]\, \addr_matrix_f0_0[17]\, - \addr_matrix_f0_1_m_i[17]\, \addr_matrix_f1[17]\, - \addr_matrix_f2_m_i[17]\, \prdata_39_0_iv_4[18]\, - \prdata_39_0_iv_1[18]\, \prdata_39_0_iv_0[18]\, - \addr_data_f0_m_i[18]\, \prdata_39_0_iv_3[18]\, - \addr_data_f2_m_i[18]\, \addr_matrix_f0_0[18]\, - \addr_matrix_f0_1_m_i[18]\, \addr_matrix_f1[18]\, - \addr_matrix_f2_m_i[18]\, \prdata_39_0_iv_4[19]\, - \prdata_39_0_iv_1[19]\, \prdata_39_0_iv_0[19]\, - \addr_data_f0_m_i[19]\, \prdata_39_0_iv_3[19]\, - \addr_data_f2_m_i[19]\, prdata_2_sqmuxa, - \addr_matrix_f0_0[19]\, \addr_matrix_f0_1_m_i[19]\, - \addr_matrix_f1[19]\, \addr_matrix_f2_m_i[19]\, - \prdata_39_0_iv_4[21]\, \prdata_39_0_iv_1[21]\, - \prdata_39_0_iv_0[21]\, \addr_data_f0_m_i[21]\, - \prdata_39_0_iv_3[21]\, \addr_data_f2_m_i[21]\, - \addr_matrix_f0_0[21]\, \addr_matrix_f0_1_m_i[21]\, - \addr_matrix_f1[21]\, \addr_matrix_f2_m_i[21]\, - \prdata_39_0_iv_4[22]\, \prdata_39_0_iv_1[22]\, - \prdata_39_0_iv_0[22]\, \addr_data_f0_m_i[22]\, - \prdata_39_0_iv_3[22]\, \addr_data_f2_m_i[22]\, - \addr_matrix_f0_0[22]\, \addr_matrix_f0_1_m_i[22]\, - \addr_matrix_f1[22]\, \addr_matrix_f2_m_i[22]\, - \prdata_39_0_iv_4[23]\, \prdata_39_0_iv_1[23]\, - \prdata_39_0_iv_0[23]\, \addr_data_f0_m_i[23]\, - \prdata_39_0_iv_3[23]\, prdata_12_sqmuxa, - \addr_data_f2_m_i[23]\, \addr_matrix_f0_0[23]\, - \addr_matrix_f0_1_m_i[23]\, \addr_matrix_f1[23]\, - \addr_matrix_f2_m_i[23]\, \prdata_39_0_iv_4[24]\, - \prdata_39_0_iv_1[24]\, \prdata_39_0_iv_0[24]\, - \addr_data_f0_m_i[24]\, \prdata_39_0_iv_3[24]\, - \addr_data_f2_m_i[24]\, \addr_matrix_f0_0[24]\, - \addr_matrix_f0_1_m_i[24]\, \addr_matrix_f1[24]\, - \addr_matrix_f2_m_i[24]\, \prdata_39_0_iv_4[25]\, - \prdata_39_0_iv_1[25]\, \prdata_39_0_iv_0[25]\, - \addr_data_f0_m_i[25]\, \prdata_39_0_iv_3[25]\, - \addr_data_f2_m_i[25]\, \addr_matrix_f0_0[25]\, - \addr_matrix_f0_1_m_i[25]\, prdata_4_sqmuxa, - \addr_matrix_f1[25]\, \addr_matrix_f2_m_i[25]\, - \prdata_39_0_iv_4[26]\, \prdata_39_0_iv_1[26]\, - \prdata_39_0_iv_0[26]\, \addr_data_f0_m_i[26]\, - \prdata_39_0_iv_3[26]\, \addr_data_f2_m_i[26]\, - \addr_matrix_f0_0[26]\, \addr_matrix_f0_1_m_i[26]\, - \addr_matrix_f1[26]\, \addr_matrix_f2_m_i[26]\, - \prdata_39_0_iv_4[27]\, \prdata_39_0_iv_1[27]\, - \prdata_39_0_iv_0[27]\, \addr_data_f0_m_i[27]\, - \prdata_39_0_iv_3[27]\, \addr_data_f2_m_i[27]\, - \addr_matrix_f0_0[27]\, \addr_matrix_f0_1_m_i[27]\, - \addr_matrix_f1[27]\, \addr_matrix_f2_m_i[27]\, - \prdata_39_0_iv_4[28]\, \prdata_39_0_iv_1[28]\, - \prdata_39_0_iv_0[28]\, \addr_data_f0_m_i[28]\, - \prdata_39_0_iv_3[28]\, \addr_data_f2_m_i[28]\, - \addr_matrix_f0_0[28]\, \addr_matrix_f0_1_m_i[28]\, - \addr_matrix_f1[28]\, \addr_matrix_f2_m_i[28]\, - \prdata_39_0_iv_4[29]\, \prdata_39_0_iv_1[29]\, - \prdata_39_0_iv_0[29]\, \addr_data_f0_m_i[29]\, - \prdata_39_0_iv_3[29]\, \addr_data_f2_m_i[29]\, - \addr_matrix_f0_0[29]\, \addr_matrix_f0_1_m_i[29]\, - \addr_matrix_f1[29]\, \addr_matrix_f2_m_i[29]\, - \prdata_39_0_iv_4[31]\, \prdata_39_0_iv_1[31]\, - \prdata_39_0_iv_0[31]\, \addr_data_f0_m_i[31]\, - \prdata_39_0_iv_3[31]\, \addr_data_f2_m_i[31]\, - \addr_matrix_f0_0[31]\, \addr_matrix_f0_1_m_i[31]\, - \addr_matrix_f1[31]\, \addr_matrix_f2_m_i[31]\, - \status_full_5_i_a2_0[0]\, \status_full_5_i_a2_0[1]\, - \status_full_5_i_a2_0[2]\, \status_full_5_i_a2_0[3]\, - \status_full_err_5_i_a2_0[0]\, \status_full_err[0]\, - \status_full_err_5_i_a2_0[1]\, \status_full_err[1]\, - \status_full_err_5_i_a2_0[2]\, \status_full_err[2]\, - \status_full_err_5_i_a2_0[3]\, \status_full_err[3]\, - \status_new_err_5_i_a2_0[0]\, \status_new_err[0]\, - \status_new_err_5_i_a2_0[1]\, \status_new_err[1]\, - \status_new_err_5_i_a2_0[2]\, \status_new_err[2]\, - \status_new_err_5_i_a2_0[3]\, \status_new_err[3]\, - config_active_interruption_onError_0_sqmuxa_0_o2_0_0, - \pirq_2_i_a2_8[15]\, \pirq_2_i_a2_5[15]\, - \pirq_2_i_a2_7[15]\, \pirq_2_i_a2_3[15]\, - \pirq_2_i_a2_6[15]\, \pirq_2_i_a2_0[15]\, - \pirq_2_i_a2_1[15]\, N_68, N_1016_i_0, \prdata_39[31]\, - \addr_data_f1_m_i[31]\, \prdata_39[29]\, - \addr_data_f1_m_i[29]\, \prdata_39[28]\, - \addr_data_f1_m_i[28]\, \prdata_39[27]\, - \addr_data_f1_m_i[27]\, \prdata_39[26]\, - \addr_data_f1_m_i[26]\, \prdata_39[25]\, - \addr_data_f1_m_i[25]\, \prdata_39[24]\, - \addr_data_f1_m_i[24]\, \prdata_39[23]\, - \addr_data_f1_m_i[23]\, \prdata_39[22]\, - \addr_data_f1_m_i[22]\, \prdata_39[21]\, - \addr_data_f1_m_i[21]\, \prdata_39[19]\, - \addr_data_f1_m_i[19]\, \prdata_39[18]\, - \addr_data_f1_m_i[18]\, \prdata_39[17]\, - \addr_data_f1_m_i[17]\, \prdata_39[16]\, - \addr_data_f1_m_i[16]\, \prdata_39[15]\, \prdata_39[14]\, - \prdata_39[13]\, \prdata_39[12]\, \prdata_39[11]\, - \prdata_39[10]\, \prdata_39[9]\, \prdata_39[8]\, - \prdata_39[7]\, \prdata_39[6]\, \prdata_39[5]\, - \prdata_39[4]\, \prdata_39[3]\, \prdata_39[2]\, - \prdata_39[1]\, \prdata_39[0]\, \prdata_39[20]\, - \addr_data_f1_m_i[20]\, \prdata_39[30]\, - \addr_data_f1_m_i[30]\, status_ready_matrix_f0_0, - \addr_matrix_f0_1[0]\, \addr_matrix_f1[0]\, - status_ready_matrix_f0_1, \addr_matrix_f0_1[1]\, - \addr_matrix_f1[1]\, \addr_matrix_f0_1[2]\, - \addr_matrix_f1[2]\, status_ready_matrix_f2, - \addr_matrix_f0_1[3]\, \addr_matrix_f1[3]\, - \data_shaping_R0_0\, status_error_anticipating_empty_fifo, - status_error_bad_component_error, \addr_matrix_f0_0[5]\, - \addr_matrix_f0_1[5]\, \addr_matrix_f2[5]\, - \addr_matrix_f0_1[6]\, \addr_matrix_f1[6]\, - \addr_matrix_f0_0[7]\, \addr_matrix_f0_1[7]\, - \addr_matrix_f1[7]\, \addr_matrix_f2[7]\, - \addr_matrix_f0_0[8]\, \addr_matrix_f0_1[8]\, - \addr_matrix_f1[8]\, \addr_matrix_f2[8]\, - \addr_matrix_f0_0[9]\, \addr_matrix_f0_1[9]\, - \addr_matrix_f1[9]\, \addr_matrix_f2[9]\, - \addr_matrix_f0_0[10]\, \addr_matrix_f0_1[10]\, - \addr_matrix_f1[10]\, \addr_matrix_f2[10]\, - \addr_matrix_f0_1[11]\, \addr_matrix_f2[11]\, - \addr_matrix_f0_1[12]\, \addr_matrix_f2[12]\, - \addr_matrix_f0_1[13]\, \addr_matrix_f2[13]\, - \addr_matrix_f0_1[14]\, \addr_matrix_f2[14]\, - \addr_matrix_f0_1[15]\, \addr_matrix_f2[15]\, - \addr_matrix_f0_1[16]\, prdata_5_sqmuxa, - \addr_matrix_f2[16]\, prdata_9_sqmuxa, prdata_10_sqmuxa, - prdata_3_sqmuxa, \addr_matrix_f0_1[17]\, - \addr_matrix_f2[17]\, \addr_matrix_f0_1[18]\, - \addr_matrix_f2[18]\, \addr_matrix_f0_1[19]\, - \addr_matrix_f2[19]\, \addr_matrix_f0_1[21]\, - \addr_matrix_f2[21]\, \addr_matrix_f0_1[22]\, - \addr_matrix_f2[22]\, \addr_matrix_f0_1[23]\, - \addr_matrix_f2[23]\, \addr_matrix_f0_1[24]\, - \addr_matrix_f2[24]\, \addr_matrix_f0_1[25]\, - \addr_matrix_f2[25]\, \addr_matrix_f0_1[26]\, - \addr_matrix_f2[26]\, \addr_matrix_f0_1[27]\, - \addr_matrix_f2[27]\, \addr_matrix_f0_1[28]\, - \addr_matrix_f2[28]\, \addr_matrix_f0_1[29]\, - \addr_matrix_f2[29]\, \addr_matrix_f0_1[31]\, - \addr_matrix_f2[31]\, addr_matrix_f0_0_1_sqmuxa, - addr_matrix_f0_1_1_sqmuxa, addr_matrix_f1_1_sqmuxa, - addr_matrix_f2_1_sqmuxa, - config_active_interruption_onError_0_sqmuxa, - status_error_anticipating_empty_fifo_1_sqmuxa, - addr_data_f0_1_sqmuxa, addr_data_f1_1_sqmuxa, - addr_data_f2_1_sqmuxa, addr_data_f3_1_sqmuxa, - burst_f0_1_sqmuxa, N_163, delta_f2_f0_1_sqmuxa, N_158, - delta_f2_f1_1_sqmuxa, delta_snapshot_1_sqmuxa, - nb_snapshot_param_1_sqmuxa, \status_full_ack_8[3]\, N_74, - \status_full_ack_8[2]\, \status_full_ack_8[1]\, - \status_full_ack_8[0]\, N_43, N_45, N_47, N_49, N_51, - N_53, N_55, N_57, N_59, N_61, N_63, N_65, - nb_burst_available_1_sqmuxa, \addr_matrix_f1[4]\, - \addr_matrix_f0_1[4]\, \addr_matrix_f2[30]\, - \addr_matrix_f0_1[30]\, \addr_matrix_f2[20]\, - \addr_matrix_f0_1[20]\, \enable_f3\, \enable_f2\, - \enable_f1\, \enable_f0\, \data_shaping_SP1\, - \data_shaping_SP0\, \Bias_Fails_c\, \burst_f2\, - \burst_f1\, \burst_f0\, \addr_data_f1[0]\, - \addr_data_f1[1]\, \addr_data_f1[2]\, \addr_data_f1[3]\, - \addr_data_f1[4]\, \addr_data_f1[5]\, \addr_data_f1[6]\, - \addr_data_f1[7]\, \addr_data_f1[8]\, \addr_data_f1[9]\, - \addr_data_f1[10]\, \addr_data_f1[11]\, - \addr_data_f1[12]\, \addr_data_f1[13]\, - \addr_data_f1[14]\, \addr_data_f1[15]\, - \addr_data_f1[16]\, \addr_data_f1[17]\, - \addr_data_f1[18]\, \addr_data_f1[19]\, - \addr_data_f1[20]\, \addr_data_f1[21]\, - \addr_data_f1[22]\, \addr_data_f1[23]\, - \addr_data_f1[24]\, \addr_data_f1[25]\, - \addr_data_f1[26]\, \addr_data_f1[27]\, - \addr_data_f1[28]\, \addr_data_f1[29]\, - \addr_data_f1[30]\, \addr_data_f1[31]\, \addr_data_f0[0]\, - \addr_data_f0[1]\, \addr_data_f0[2]\, \addr_data_f0[3]\, - \addr_data_f0[4]\, \addr_data_f0[5]\, \addr_data_f0[6]\, - \addr_data_f0[7]\, \addr_data_f0[8]\, \addr_data_f0[9]\, - \addr_data_f0[10]\, \addr_data_f0[11]\, - \addr_data_f0[12]\, \addr_data_f0[13]\, - \addr_data_f0[14]\, \addr_data_f0[15]\, - \addr_data_f0[16]\, \addr_data_f0[17]\, - \addr_data_f0[18]\, \addr_data_f0[19]\, - \addr_data_f0[20]\, \addr_data_f0[21]\, - \addr_data_f0[22]\, \addr_data_f0[23]\, - \addr_data_f0[24]\, \addr_data_f0[25]\, - \addr_data_f0[26]\, \addr_data_f0[27]\, - \addr_data_f0[28]\, \addr_data_f0[29]\, - \addr_data_f0[30]\, \addr_data_f0[31]\, - \delta_snapshot[0]\, \delta_snapshot[1]\, - \delta_snapshot[2]\, \delta_snapshot[3]\, - \delta_snapshot[4]\, \delta_snapshot[5]\, - \delta_snapshot[6]\, \delta_snapshot[7]\, - \delta_snapshot[8]\, \delta_snapshot[9]\, - \delta_snapshot[10]\, \delta_snapshot[11]\, - \delta_snapshot[12]\, \delta_snapshot[13]\, - \delta_snapshot[14]\, \delta_snapshot[15]\, - \nb_snapshot_param[0]\, \nb_snapshot_param[1]\, - \nb_snapshot_param[2]\, \nb_snapshot_param[3]\, - \nb_snapshot_param[4]\, \nb_snapshot_param[5]\, - \nb_snapshot_param[6]\, \nb_snapshot_param[7]\, - \nb_snapshot_param[8]\, \nb_snapshot_param[9]\, - \nb_snapshot_param[10]\, \nb_burst_available[0]\, - \nb_burst_available[1]\, \nb_burst_available[2]\, - \nb_burst_available[3]\, \nb_burst_available[4]\, - \nb_burst_available[5]\, \nb_burst_available[6]\, - \nb_burst_available[7]\, \nb_burst_available[8]\, - \nb_burst_available[9]\, \nb_burst_available[10]\, - \delta_f2_f1[0]\, \delta_f2_f1[1]\, \delta_f2_f1[2]\, - \delta_f2_f1[3]\, \delta_f2_f1[4]\, \delta_f2_f1[5]\, - \delta_f2_f1[6]\, \delta_f2_f1[7]\, \delta_f2_f1[8]\, - \delta_f2_f1[9]\, \delta_f2_f0[0]\, \delta_f2_f0[1]\, - \delta_f2_f0[2]\, \delta_f2_f0[3]\, \delta_f2_f0[4]\, - \delta_f2_f0[5]\, \delta_f2_f0[6]\, \delta_f2_f0[7]\, - \delta_f2_f0[8]\, \delta_f2_f0[9]\, \addr_data_f3[0]\, - \addr_data_f3[1]\, \addr_data_f3[2]\, \addr_data_f3[3]\, - \addr_data_f3[4]\, \addr_data_f3[5]\, \addr_data_f3[6]\, - \addr_data_f3[7]\, \addr_data_f3[8]\, \addr_data_f3[9]\, - \addr_data_f3[10]\, \addr_data_f3[11]\, - \addr_data_f3[12]\, \addr_data_f3[13]\, - \addr_data_f3[14]\, \addr_data_f3[15]\, - \addr_data_f3[16]\, \addr_data_f3[17]\, - \addr_data_f3[18]\, \addr_data_f3[19]\, - \addr_data_f3[20]\, \addr_data_f3[21]\, - \addr_data_f3[22]\, \addr_data_f3[23]\, - \addr_data_f3[24]\, \addr_data_f3[25]\, - \addr_data_f3[26]\, \addr_data_f3[27]\, - \addr_data_f3[28]\, \addr_data_f3[29]\, - \addr_data_f3[30]\, \addr_data_f3[31]\, \addr_data_f2[0]\, - \addr_data_f2[1]\, \addr_data_f2[2]\, \addr_data_f2[3]\, - \addr_data_f2[4]\, \addr_data_f2[5]\, \addr_data_f2[6]\, - \addr_data_f2[7]\, \addr_data_f2[8]\, \addr_data_f2[9]\, - \addr_data_f2[10]\, \addr_data_f2[11]\, - \addr_data_f2[12]\, \addr_data_f2[13]\, - \addr_data_f2[14]\, \addr_data_f2[15]\, - \addr_data_f2[16]\, \addr_data_f2[17]\, - \addr_data_f2[18]\, \addr_data_f2[19]\, - \addr_data_f2[20]\, \addr_data_f2[21]\, - \addr_data_f2[22]\, \addr_data_f2[23]\, - \addr_data_f2[24]\, \addr_data_f2[25]\, - \addr_data_f2[26]\, \addr_data_f2[27]\, - \addr_data_f2[28]\, \addr_data_f2[29]\, - \addr_data_f2[30]\, \addr_data_f2[31]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - addr_data_f2(31) <= \addr_data_f2[31]\; - addr_data_f2(30) <= \addr_data_f2[30]\; - addr_data_f2(29) <= \addr_data_f2[29]\; - addr_data_f2(28) <= \addr_data_f2[28]\; - addr_data_f2(27) <= \addr_data_f2[27]\; - addr_data_f2(26) <= \addr_data_f2[26]\; - addr_data_f2(25) <= \addr_data_f2[25]\; - addr_data_f2(24) <= \addr_data_f2[24]\; - addr_data_f2(23) <= \addr_data_f2[23]\; - addr_data_f2(22) <= \addr_data_f2[22]\; - addr_data_f2(21) <= \addr_data_f2[21]\; - addr_data_f2(20) <= \addr_data_f2[20]\; - addr_data_f2(19) <= \addr_data_f2[19]\; - addr_data_f2(18) <= \addr_data_f2[18]\; - addr_data_f2(17) <= \addr_data_f2[17]\; - addr_data_f2(16) <= \addr_data_f2[16]\; - addr_data_f2(15) <= \addr_data_f2[15]\; - addr_data_f2(14) <= \addr_data_f2[14]\; - addr_data_f2(13) <= \addr_data_f2[13]\; - addr_data_f2(12) <= \addr_data_f2[12]\; - addr_data_f2(11) <= \addr_data_f2[11]\; - addr_data_f2(10) <= \addr_data_f2[10]\; - addr_data_f2(9) <= \addr_data_f2[9]\; - addr_data_f2(8) <= \addr_data_f2[8]\; - addr_data_f2(7) <= \addr_data_f2[7]\; - addr_data_f2(6) <= \addr_data_f2[6]\; - addr_data_f2(5) <= \addr_data_f2[5]\; - addr_data_f2(4) <= \addr_data_f2[4]\; - addr_data_f2(3) <= \addr_data_f2[3]\; - addr_data_f2(2) <= \addr_data_f2[2]\; - addr_data_f2(1) <= \addr_data_f2[1]\; - addr_data_f2(0) <= \addr_data_f2[0]\; - addr_data_f3(31) <= \addr_data_f3[31]\; - addr_data_f3(30) <= \addr_data_f3[30]\; - addr_data_f3(29) <= \addr_data_f3[29]\; - addr_data_f3(28) <= \addr_data_f3[28]\; - addr_data_f3(27) <= \addr_data_f3[27]\; - addr_data_f3(26) <= \addr_data_f3[26]\; - addr_data_f3(25) <= \addr_data_f3[25]\; - addr_data_f3(24) <= \addr_data_f3[24]\; - addr_data_f3(23) <= \addr_data_f3[23]\; - addr_data_f3(22) <= \addr_data_f3[22]\; - addr_data_f3(21) <= \addr_data_f3[21]\; - addr_data_f3(20) <= \addr_data_f3[20]\; - addr_data_f3(19) <= \addr_data_f3[19]\; - addr_data_f3(18) <= \addr_data_f3[18]\; - addr_data_f3(17) <= \addr_data_f3[17]\; - addr_data_f3(16) <= \addr_data_f3[16]\; - addr_data_f3(15) <= \addr_data_f3[15]\; - addr_data_f3(14) <= \addr_data_f3[14]\; - addr_data_f3(13) <= \addr_data_f3[13]\; - addr_data_f3(12) <= \addr_data_f3[12]\; - addr_data_f3(11) <= \addr_data_f3[11]\; - addr_data_f3(10) <= \addr_data_f3[10]\; - addr_data_f3(9) <= \addr_data_f3[9]\; - addr_data_f3(8) <= \addr_data_f3[8]\; - addr_data_f3(7) <= \addr_data_f3[7]\; - addr_data_f3(6) <= \addr_data_f3[6]\; - addr_data_f3(5) <= \addr_data_f3[5]\; - addr_data_f3(4) <= \addr_data_f3[4]\; - addr_data_f3(3) <= \addr_data_f3[3]\; - addr_data_f3(2) <= \addr_data_f3[2]\; - addr_data_f3(1) <= \addr_data_f3[1]\; - addr_data_f3(0) <= \addr_data_f3[0]\; - addr_data_f1(31) <= \addr_data_f1[31]\; - addr_data_f1(30) <= \addr_data_f1[30]\; - addr_data_f1(29) <= \addr_data_f1[29]\; - addr_data_f1(28) <= \addr_data_f1[28]\; - addr_data_f1(27) <= \addr_data_f1[27]\; - addr_data_f1(26) <= \addr_data_f1[26]\; - addr_data_f1(25) <= \addr_data_f1[25]\; - addr_data_f1(24) <= \addr_data_f1[24]\; - addr_data_f1(23) <= \addr_data_f1[23]\; - addr_data_f1(22) <= \addr_data_f1[22]\; - addr_data_f1(21) <= \addr_data_f1[21]\; - addr_data_f1(20) <= \addr_data_f1[20]\; - addr_data_f1(19) <= \addr_data_f1[19]\; - addr_data_f1(18) <= \addr_data_f1[18]\; - addr_data_f1(17) <= \addr_data_f1[17]\; - addr_data_f1(16) <= \addr_data_f1[16]\; - addr_data_f1(15) <= \addr_data_f1[15]\; - addr_data_f1(14) <= \addr_data_f1[14]\; - addr_data_f1(13) <= \addr_data_f1[13]\; - addr_data_f1(12) <= \addr_data_f1[12]\; - addr_data_f1(11) <= \addr_data_f1[11]\; - addr_data_f1(10) <= \addr_data_f1[10]\; - addr_data_f1(9) <= \addr_data_f1[9]\; - addr_data_f1(8) <= \addr_data_f1[8]\; - addr_data_f1(7) <= \addr_data_f1[7]\; - addr_data_f1(6) <= \addr_data_f1[6]\; - addr_data_f1(5) <= \addr_data_f1[5]\; - addr_data_f1(4) <= \addr_data_f1[4]\; - addr_data_f1(3) <= \addr_data_f1[3]\; - addr_data_f1(2) <= \addr_data_f1[2]\; - addr_data_f1(1) <= \addr_data_f1[1]\; - addr_data_f1(0) <= \addr_data_f1[0]\; - nb_burst_available(10) <= \nb_burst_available[10]\; - nb_burst_available(9) <= \nb_burst_available[9]\; - nb_burst_available(8) <= \nb_burst_available[8]\; - nb_burst_available(7) <= \nb_burst_available[7]\; - nb_burst_available(6) <= \nb_burst_available[6]\; - nb_burst_available(5) <= \nb_burst_available[5]\; - nb_burst_available(4) <= \nb_burst_available[4]\; - nb_burst_available(3) <= \nb_burst_available[3]\; - nb_burst_available(2) <= \nb_burst_available[2]\; - nb_burst_available(1) <= \nb_burst_available[1]\; - nb_burst_available(0) <= \nb_burst_available[0]\; - addr_data_f0(31) <= \addr_data_f0[31]\; - addr_data_f0(30) <= \addr_data_f0[30]\; - addr_data_f0(29) <= \addr_data_f0[29]\; - addr_data_f0(28) <= \addr_data_f0[28]\; - addr_data_f0(27) <= \addr_data_f0[27]\; - addr_data_f0(26) <= \addr_data_f0[26]\; - addr_data_f0(25) <= \addr_data_f0[25]\; - addr_data_f0(24) <= \addr_data_f0[24]\; - addr_data_f0(23) <= \addr_data_f0[23]\; - addr_data_f0(22) <= \addr_data_f0[22]\; - addr_data_f0(21) <= \addr_data_f0[21]\; - addr_data_f0(20) <= \addr_data_f0[20]\; - addr_data_f0(19) <= \addr_data_f0[19]\; - addr_data_f0(18) <= \addr_data_f0[18]\; - addr_data_f0(17) <= \addr_data_f0[17]\; - addr_data_f0(16) <= \addr_data_f0[16]\; - addr_data_f0(15) <= \addr_data_f0[15]\; - addr_data_f0(14) <= \addr_data_f0[14]\; - addr_data_f0(13) <= \addr_data_f0[13]\; - addr_data_f0(12) <= \addr_data_f0[12]\; - addr_data_f0(11) <= \addr_data_f0[11]\; - addr_data_f0(10) <= \addr_data_f0[10]\; - addr_data_f0(9) <= \addr_data_f0[9]\; - addr_data_f0(8) <= \addr_data_f0[8]\; - addr_data_f0(7) <= \addr_data_f0[7]\; - addr_data_f0(6) <= \addr_data_f0[6]\; - addr_data_f0(5) <= \addr_data_f0[5]\; - addr_data_f0(4) <= \addr_data_f0[4]\; - addr_data_f0(3) <= \addr_data_f0[3]\; - addr_data_f0(2) <= \addr_data_f0[2]\; - addr_data_f0(1) <= \addr_data_f0[1]\; - addr_data_f0(0) <= \addr_data_f0[0]\; - nb_snapshot_param(10) <= \nb_snapshot_param[10]\; - nb_snapshot_param(9) <= \nb_snapshot_param[9]\; - nb_snapshot_param(8) <= \nb_snapshot_param[8]\; - nb_snapshot_param(7) <= \nb_snapshot_param[7]\; - nb_snapshot_param(6) <= \nb_snapshot_param[6]\; - nb_snapshot_param(5) <= \nb_snapshot_param[5]\; - nb_snapshot_param(4) <= \nb_snapshot_param[4]\; - nb_snapshot_param(3) <= \nb_snapshot_param[3]\; - nb_snapshot_param(2) <= \nb_snapshot_param[2]\; - nb_snapshot_param(1) <= \nb_snapshot_param[1]\; - nb_snapshot_param(0) <= \nb_snapshot_param[0]\; - delta_snapshot(15) <= \delta_snapshot[15]\; - delta_snapshot(14) <= \delta_snapshot[14]\; - delta_snapshot(13) <= \delta_snapshot[13]\; - delta_snapshot(12) <= \delta_snapshot[12]\; - delta_snapshot(11) <= \delta_snapshot[11]\; - delta_snapshot(10) <= \delta_snapshot[10]\; - delta_snapshot(9) <= \delta_snapshot[9]\; - delta_snapshot(8) <= \delta_snapshot[8]\; - delta_snapshot(7) <= \delta_snapshot[7]\; - delta_snapshot(6) <= \delta_snapshot[6]\; - delta_snapshot(5) <= \delta_snapshot[5]\; - delta_snapshot(4) <= \delta_snapshot[4]\; - delta_snapshot(3) <= \delta_snapshot[3]\; - delta_snapshot(2) <= \delta_snapshot[2]\; - delta_snapshot(1) <= \delta_snapshot[1]\; - delta_snapshot(0) <= \delta_snapshot[0]\; - delta_f2_f0(9) <= \delta_f2_f0[9]\; - delta_f2_f0(8) <= \delta_f2_f0[8]\; - delta_f2_f0(7) <= \delta_f2_f0[7]\; - delta_f2_f0(6) <= \delta_f2_f0[6]\; - delta_f2_f0(5) <= \delta_f2_f0[5]\; - delta_f2_f0(4) <= \delta_f2_f0[4]\; - delta_f2_f0(3) <= \delta_f2_f0[3]\; - delta_f2_f0(2) <= \delta_f2_f0[2]\; - delta_f2_f0(1) <= \delta_f2_f0[1]\; - delta_f2_f0(0) <= \delta_f2_f0[0]\; - delta_f2_f1(9) <= \delta_f2_f1[9]\; - delta_f2_f1(8) <= \delta_f2_f1[8]\; - delta_f2_f1(7) <= \delta_f2_f1[7]\; - delta_f2_f1(6) <= \delta_f2_f1[6]\; - delta_f2_f1(5) <= \delta_f2_f1[5]\; - delta_f2_f1(4) <= \delta_f2_f1[4]\; - delta_f2_f1(3) <= \delta_f2_f1[3]\; - delta_f2_f1(2) <= \delta_f2_f1[2]\; - delta_f2_f1(1) <= \delta_f2_f1[1]\; - delta_f2_f1(0) <= \delta_f2_f1[0]\; - burst_f2 <= \burst_f2\; - burst_f0 <= \burst_f0\; - enable_f3 <= \enable_f3\; - enable_f2 <= \enable_f2\; - data_shaping_SP1 <= \data_shaping_SP1\; - enable_f1 <= \enable_f1\; - enable_f0 <= \enable_f0\; - burst_f1 <= \burst_f1\; - data_shaping_SP0 <= \data_shaping_SP0\; - Bias_Fails_c <= \Bias_Fails_c\; - data_shaping_R1_0 <= \data_shaping_R1_0\; - data_shaping_R0_0 <= \data_shaping_R0_0\; - - \prdata_RNO_7[29]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[29]\, - Y => \addr_matrix_f0_1_m_i[29]\); - - \reg_wp.addr_data_f3[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[17]\); - - \reg_wp.delta_f2_f1[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[1]\); - - \reg_sp.addr_matrix_f1[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[6]\); - - \prdata_RNO_5[14]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[14]\, - Y => \delta_snapshot_m_i[14]\); - - \prdata_RNO_2[14]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[14]\, C - => \addr_data_f1_m_i[14]\, Y => \prdata_39_0_iv_5[14]\); - - \reg_sp.addr_matrix_f0_0[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[2]\); - - \reg_wp.addr_data_f3[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[25]\); - - \prdata_RNO_0[8]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[8]\, C - => \prdata_39_0_iv_6[8]\, Y => \prdata_39_0_iv_9[8]\); - - \reg_wp.addr_data_f3[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[26]\); - - \reg_wp.nb_snapshot_param[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[2]\); - - \reg_wp.delta_f2_f0[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[2]\); - - \reg_wp.addr_data_f3_1_sqmuxa_0_a2\ : NOR2B - port map(A => N_168, B => N_160, Y => addr_data_f3_1_sqmuxa); - - \prdata_RNO_5[7]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[7]\, - Y => \addr_matrix_f0_1_m_i[7]\); - - \reg_wp.addr_data_f2[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[29]\); - - prdata_18_sqmuxa_0_a2 : NOR3C - port map(A => N_158, B => N_159, C => paddr_2(2), Y => - prdata_18_sqmuxa); - - \reg_sp.addr_matrix_f0_1[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[22]\); - - \prdata_RNO_7[3]\ : NOR3C - port map(A => \prdata_39_0_iv_2[3]\, B => - \prdata_39_0_iv_1[3]\, C => \prdata_39_0_iv_4[3]\, Y => - \prdata_39_0_iv_7[3]\); - - \prdata_RNO_8[28]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[28]\, Y - => \addr_matrix_f2_m_i[28]\); - - \prdata_RNO_6[1]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[1]\, C => N_232_0, - Y => \addr_data_f2_m_i[1]\); - - \prdata_RNO_4[29]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[29]\, - C => \addr_matrix_f0_1_m_i[29]\, Y => - \prdata_39_0_iv_1[29]\); - - \reg_wp.nb_snapshot_param[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[9]\); - - \reg_wp.nb_burst_available[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[7]\); - - \prdata_RNO[8]\ : OR3C - port map(A => \prdata_39_0_iv_9[8]\, B => - \prdata_39_0_iv_8[8]\, C => \prdata_39_0_iv_10[8]\, Y => - \prdata_39[8]\); - - \prdata_RNO_1[13]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[13]\, - C => \addr_data_f2_m_i[13]\, Y => \prdata_39_0_iv_3[13]\); - - \prdata_RNO_6[18]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[18]\, Y - => \addr_data_f0_m_i[18]\); - - \prdata[26]\ : DFN1C0 - port map(D => \prdata_39[26]\, CLK => lclk_c, CLR => rstn, - Q => prdata(26)); - - \prdata_RNO_19[0]\ : OR2B - port map(A => status_ready_matrix_f0_0, B => - prdata_1_sqmuxa, Y => status_ready_matrix_f0_0_m_i); - - \reg_sp.addr_matrix_f0_0[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[4]\); - - \prdata_RNO_0[29]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[29]\, C - => \addr_data_f2_m_i[29]\, Y => \prdata_39_0_iv_3[29]\); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2_2\ : NOR2B - port map(A => N_68, B => paddr(6), Y => N_158); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_1_0\ : OR2A - port map(A => paddr_0(4), B => paddr(5), Y => - addr_matrix_f1_1_sqmuxa_0_a2_1_0); - - \reg_wp.addr_data_f0_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_71, B => paddr_0(4), C => N_72, Y => - addr_data_f0_1_sqmuxa); - - \prdata_RNO_7[10]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[10]\, - C => \addr_data_f2_m_i[10]\, Y => \prdata_39_0_iv_5[10]\); - - \reg_wp.addr_data_f2[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[13]\); - - \reg_wp.addr_data_f2[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[10]\); - - \reg_sp.addr_matrix_f0_1[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[2]\); - - \reg_wp.addr_data_f3[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[2]\); - - \reg_wp.addr_data_f3_1_sqmuxa_0_a2_0\ : NOR2B - port map(A => N_168_0, B => N_160, Y => - addr_data_f3_1_sqmuxa_0); - - \reg_sp.addr_matrix_f0_1[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[1]\); - - \prdata_RNO_11[1]\ : AOI1B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[1]\, C - => \nb_burst_available_m_i[1]\, Y => - \prdata_39_0_iv_1[1]\); - - \apbo.pirq_RNO_4[15]\ : NOR2 - port map(A => status_new_err_0(0), B => status_new_err_0(1), - Y => \pirq_2_i_a2_0[15]\); - - \prdata_RNO_4[14]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[14]\, - C => \addr_matrix_f2_m_i[14]\, Y => - \prdata_39_0_iv_0[14]\); - - \reg_sp.addr_matrix_f0_0[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[31]\); - - \prdata_RNO_13[6]\ : NOR3C - port map(A => \prdata_39_0_iv_1[6]\, B => - \prdata_39_0_iv_0[6]\, C => \addr_matrix_f1_m_i[6]\, Y - => \prdata_39_0_iv_3[6]\); - - \prdata_RNO_16[6]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[6]\, C - => \delta_f2_f1_m_i[6]\, Y => \prdata_39_0_iv_0[6]\); - - \reg_sp.addr_matrix_f0_1[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[19]\); - - \reg_sp.status_ready_matrix_f2\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f2); - - \prdata_RNO_6[20]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[20]\, Y - => \addr_data_f0_m_i[20]\); - - \reg_wp.addr_data_f0[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[8]\); - - \prdata_RNO_6[4]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[4]\, Y - => \delta_snapshot_m_i[4]\); - - \prdata_RNO_6[31]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[31]\, Y - => \addr_data_f0_m_i[31]\); - - \apbo.pirq_RNO_0[15]\ : NOR3A - port map(A => \pirq_2_i_a2_3[15]\, B => - status_full_err_0(1), C => status_full_err_0(0), Y => - \pirq_2_i_a2_7[15]\); - - \reg_sp.addr_matrix_f0_1[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[9]\); - - \prdata_RNO_3[6]\ : OR2B - port map(A => \status_full_err[2]\, B => prdata_13_sqmuxa, - Y => \status_full_err_m_i[2]\); - - \prdata_RNO_18[1]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[1]\, Y - => \delta_f2_f0_m_i[1]\); - - \reg_wp.delta_snapshot_1_sqmuxa_0_o2_0\ : OR3B - port map(A => paddr(5), B => paddr(3), C => N_69, Y => N_72); - - \reg_sp.addr_matrix_f0_0[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[24]\); - - \prdata_RNO_11[10]\ : OR2B - port map(A => \nb_snapshot_param[10]\, B => - prdata_18_sqmuxa, Y => \nb_snapshot_param_m_i[10]\); - - \reg_wp.addr_data_f2[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[11]\); - - \reg_sp.addr_matrix_f0_0[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[25]\); - - \reg_sp.addr_matrix_f0_0[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[16]\); - - \prdata_RNO_9[6]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[6]\, C => N_232_1, - Y => \addr_data_f2_m_i[6]\); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2_0\ : NOR2A - port map(A => paddr_2(2), B => un1_apbi_0, Y => N_166); - - \prdata_RNO_9[7]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[7]\, - Y => \addr_matrix_f2_m_i[7]\); - - \prdata_RNO_8[0]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[0]\, Y - => \addr_data_f0_m_i[0]\); - - \prdata_RNO_16[9]\ : OR2B - port map(A => \nb_snapshot_param[9]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[9]\); - - \prdata_RNO[7]\ : OR3C - port map(A => \prdata_39_0_iv_9[7]\, B => - \prdata_39_0_iv_8[7]\, C => \prdata_39_0_iv_10[7]\, Y => - \prdata_39[7]\); - - \prdata_RNO_5[13]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[13]\, - Y => \delta_snapshot_m_i[13]\); - - \prdata_RNO_2[13]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[13]\, C - => \addr_data_f1_m_i[13]\, Y => \prdata_39_0_iv_5[13]\); - - prdata_16_sqmuxa_0_a2 : NOR3A - port map(A => N_158, B => rdata61_2, C => N_6455, Y => - prdata_16_sqmuxa); - - \prdata_RNO_7[1]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[1]\, Y - => \addr_data_f1_m_i[1]\); - - \reg_wp.addr_data_f3[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[5]\); - - \prdata_RNO_9[15]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[15]\, Y => \addr_matrix_f0_1_m_i[15]\); - - \prdata_RNO_7[25]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[25]\, - Y => \addr_matrix_f0_1_m_i[25]\); - - \prdata_RNO_10[2]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[2]\, - Y => \addr_matrix_f0_1_m_i[2]\); - - \reg_wp.addr_data_f3[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[22]\); - - \reg_wp.status_new_err_RNO_0[3]\ : OR2 - port map(A => \status_new_err[3]\, B => status_new_err_0(3), - Y => \status_new_err_5_i_a2_0[3]\); - - \prdata_RNO_8[27]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[27]\, Y - => \addr_matrix_f2_m_i[27]\); - - \reg_sp.addr_matrix_f0_1[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[4]\); - - \reg_wp.burst_f2\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \burst_f2\); - - \reg_sp.addr_matrix_f1[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[0]\); - - \prdata_RNO_11[7]\ : AOI1B - port map(A => \nb_burst_available[7]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[7]\, Y => - \prdata_39_0_iv_1[7]\); - - \reg_wp.status_full_err[3]\ : DFN1C0 - port map(D => N_57, CLK => lclk_c, CLR => rstn, Q => - \status_full_err[3]\); - - \prdata_RNO_20[1]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[1]\, - Y => \addr_matrix_f0_1_m_i[1]\); - - \prdata_RNO_19[4]\ : OR2B - port map(A => status_error_anticipating_empty_fifo, B => - prdata_1_sqmuxa, Y => - status_error_anticipating_empty_fifo_m_i); - - \prdata_RNO_2[24]\ : NOR3C - port map(A => \prdata_39_0_iv_1[24]\, B => - \prdata_39_0_iv_0[24]\, C => \addr_data_f0_m_i[24]\, Y - => \prdata_39_0_iv_4[24]\); - - \prdata_RNO_8[4]\ : OR2B - port map(A => \status_full_err[0]\, B => prdata_13_sqmuxa, - Y => \status_full_err_m_i[0]\); - - \prdata_RNO[18]\ : OR3C - port map(A => \prdata_39_0_iv_3[18]\, B => - \addr_data_f1_m_i[18]\, C => \prdata_39_0_iv_4[18]\, Y - => \prdata_39[18]\); - - \status_full_ack[1]\ : DFN1C0 - port map(D => \status_full_ack_8[1]\, CLK => lclk_c, CLR - => rstn, Q => status_full_ack(1)); - - \prdata_RNO_1[30]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[30]\, Y - => \addr_data_f1_m_i[30]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_o2\ : NOR2 - port map(A => un1_apbi_0, B => paddr_2(2), Y => N_71); - - \prdata_RNO_6[17]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[17]\, Y - => \addr_data_f0_m_i[17]\); - - \reg_sp.addr_matrix_f1[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[8]\); - - \prdata_RNO_14[10]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[10]\, C => - N_232_1, Y => \addr_data_f2_m_i[10]\); - - \prdata_RNO_4[25]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[25]\, - C => \addr_matrix_f0_1_m_i[25]\, Y => - \prdata_39_0_iv_1[25]\); - - \prdata_RNO_1[3]\ : NOR3C - port map(A => \prdata_39_0_iv_6[3]\, B => - \prdata_39_0_iv_5[3]\, C => \delta_snapshot_m_i[3]\, Y - => \prdata_39_0_iv_11[3]\); - - \prdata_RNO_16[8]\ : OR2B - port map(A => \nb_burst_available[8]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[8]\); - - \prdata_RNO_5[21]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[21]\, - C => \addr_matrix_f2_m_i[21]\, Y => - \prdata_39_0_iv_0[21]\); - - \prdata_RNO_5[26]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[26]\, C - => \addr_matrix_f2_m_i[26]\, Y => \prdata_39_0_iv_0[26]\); - - \prdata[7]\ : DFN1C0 - port map(D => \prdata_39[7]\, CLK => lclk_c, CLR => rstn, Q - => prdata(7)); - - \reg_sp.config_active_interruption_onError\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - config_active_interruption_onError_0_sqmuxa, Q => - config_active_interruption_onError); - - \prdata_RNO_21[4]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[4]\, Y - => \delta_f2_f1_m_i[4]\); - - \prdata_RNO_3[19]\ : OR3B - port map(A => N_168, B => \addr_data_f2[19]\, C => N_232_1, - Y => \addr_data_f2_m_i[19]\); - - \prdata_RNO_4[5]\ : NOR3C - port map(A => \prdata_39_0_iv_2[5]\, B => - \prdata_39_0_iv_1[5]\, C => \addr_matrix_f0_1_m_i[5]\, Y - => \prdata_39_0_iv_6[5]\); - - \prdata_RNO_7[28]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[28]\, - Y => \addr_matrix_f0_1_m_i[28]\); - - \reg_wp.delta_f2_f1[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[7]\); - - \prdata_RNO_12[0]\ : AOI1B - port map(A => prdata_0_sqmuxa, B => - config_active_interruption_onNewMatrix, C => - \delta_f2_f0_m_i[0]\, Y => \prdata_39_0_iv_0[0]\); - - \prdata_RNO_0[25]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[25]\, C - => \addr_data_f2_m_i[25]\, Y => \prdata_39_0_iv_3[25]\); - - \prdata[14]\ : DFN1C0 - port map(D => \prdata_39[14]\, CLK => lclk_c, CLR => rstn, - Q => prdata(14)); - - \prdata_RNO_11[3]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f3\, Y => - enable_f3_m_i); - - \prdata_RNO_4[13]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[13]\, - C => \addr_matrix_f2_m_i[13]\, Y => - \prdata_39_0_iv_0[13]\); - - \prdata_RNO_2[9]\ : NOR3C - port map(A => \addr_data_f3_m_i[9]\, B => - \addr_data_f2_m_i[9]\, C => \addr_data_f1_m_i[9]\, Y => - \prdata_39_0_iv_10[9]\); - - prdata_12_sqmuxa_0_a2_0 : NOR2A - port map(A => N_168, B => N_6455_0, Y => prdata_12_sqmuxa_0); - - \reg_wp.status_full_RNO_0[2]\ : OR2 - port map(A => \status_full[2]\, B => status_full_0(2), Y - => \status_full_5_i_a2_0[2]\); - - \prdata_RNO_12[4]\ : AOI1B - port map(A => prdata_7_sqmuxa, B => \data_shaping_R1_0\, C - => \addr_matrix_f1_m_i[4]\, Y => \prdata_39_0_iv_4[4]\); - - \prdata_RNO_5[22]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[22]\, - C => \addr_matrix_f2_m_i[22]\, Y => - \prdata_39_0_iv_0[22]\); - - \reg_wp.addr_data_f2[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[15]\); - - \reg_wp.addr_data_f2[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[16]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_a2\ : - NOR3A - port map(A => N_162, B => rdata61_2, C => N_69, Y => - config_active_interruption_onError_0_sqmuxa); - - \reg_sp.addr_matrix_f2[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[15]\); - - \prdata_RNO[23]\ : OR3C - port map(A => \prdata_39_0_iv_3[23]\, B => - \addr_data_f1_m_i[23]\, C => \prdata_39_0_iv_4[23]\, Y - => \prdata_39[23]\); - - \reg_wp.burst_f0_1_sqmuxa_0_a2\ : NOR2B - port map(A => N_163, B => N_160, Y => burst_f0_1_sqmuxa); - - \reg_wp.addr_data_f0[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[7]\); - - \reg_sp.addr_matrix_f0_0[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[10]\); - - \prdata_RNO_6[0]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[0]\, C => N_232_0, - Y => \addr_data_f2_m_i[0]\); - - \reg_wp.addr_data_f1[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[27]\); - - \reg_wp.nb_burst_available[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[9]\); - - \reg_wp.addr_data_f1[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[8]\); - - \prdata_RNO_4[28]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[28]\, - C => \addr_matrix_f0_1_m_i[28]\, Y => - \prdata_39_0_iv_1[28]\); - - \reg_sp.addr_matrix_f0_0[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[13]\); - - \apbo.pirq_RNO[15]\ : OR3C - port map(A => \pirq_2_i_a2_7[15]\, B => \pirq_2_i_a2_6[15]\, - C => \pirq_2_i_a2_8[15]\, Y => N_1016_i_0); - - \reg_sp.addr_matrix_f2[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[12]\); - - \prdata_RNO_1[10]\ : NOR3C - port map(A => \prdata_39_0_iv_1[10]\, B => - \addr_matrix_f0_1_m_i[10]\, C => \delta_snapshot_m_i[10]\, - Y => \prdata_39_0_iv_6[10]\); - - \reg_wp.addr_data_f1[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[5]\); - - \prdata_RNO_3[21]\ : OR3B - port map(A => N_168, B => \addr_data_f2[21]\, C => N_232_1, - Y => \addr_data_f2_m_i[21]\); - - \prdata_RNO_15[3]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[3]\, C => N_232_1, - Y => \addr_data_f2_m_i[3]\); - - \prdata_RNO_3[26]\ : OR3B - port map(A => N_168, B => \addr_data_f2[26]\, C => N_232, Y - => \addr_data_f2_m_i[26]\); - - \prdata_RNO_8[19]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[19]\, Y - => \addr_matrix_f2_m_i[19]\); - - \prdata_RNO_3[1]\ : AOI1B - port map(A => prdata_7_sqmuxa, B => \data_shaping_SP0\, C - => \addr_matrix_f1_m_i[1]\, Y => \prdata_39_0_iv_5[1]\); - - \prdata_RNO_20[0]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[0]\, - Y => \addr_matrix_f0_1_m_i[0]\); - - \prdata[27]\ : DFN1C0 - port map(D => \prdata_39[27]\, CLK => lclk_c, CLR => rstn, - Q => prdata(27)); - - \prdata_RNO[12]\ : OR3C - port map(A => \prdata_39_0_iv_4[12]\, B => - \prdata_39_0_iv_3[12]\, C => \prdata_39_0_iv_5[12]\, Y - => \prdata_39[12]\); - - \reg_sp.addr_matrix_f2[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[17]\); - - \reg_wp.addr_data_f2[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[4]\); - - \prdata_RNO_2[3]\ : NOR3C - port map(A => \prdata_39_0_iv_7[3]\, B => - \addr_data_f3_m_i[3]\, C => \prdata_39_0_iv_9[3]\, Y => - \prdata_39_0_iv_13[3]\); - - \prdata_RNO_15[4]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[4]\, Y - => \addr_matrix_f1_m_i[4]\); - - \prdata[28]\ : DFN1C0 - port map(D => \prdata_39[28]\, CLK => lclk_c, CLR => rstn, - Q => prdata(28)); - - \prdata_RNO_0[28]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[28]\, C - => \addr_data_f2_m_i[28]\, Y => \prdata_39_0_iv_3[28]\); - - \reg_wp.addr_data_f3[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[13]\); - - \prdata_RNO_2[23]\ : NOR3C - port map(A => \prdata_39_0_iv_1[23]\, B => - \prdata_39_0_iv_0[23]\, C => \addr_data_f0_m_i[23]\, Y - => \prdata_39_0_iv_4[23]\); - - \reg_sp.addr_matrix_f2[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[25]\); - - \reg_wp.addr_data_f3[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[10]\); - - \prdata_RNO_9[8]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[8]\, Y - => \addr_data_f1_m_i[8]\); - - \prdata_RNO_13[0]\ : AOI1B - port map(A => \nb_snapshot_param[0]\, B => prdata_18_sqmuxa, - C => status_ready_matrix_f0_0_m_i, Y => - \prdata_39_0_iv_2[0]\); - - \reg_wp.data_shaping_R0\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => data_shaping_R0); - - \reg_wp.addr_data_f2[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[6]\); - - \prdata_RNO_14[7]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[7]\, C => N_232_1, - Y => \addr_data_f2_m_i[7]\); - - \prdata_RNO[24]\ : OR3C - port map(A => \prdata_39_0_iv_3[24]\, B => - \addr_data_f1_m_i[24]\, C => \prdata_39_0_iv_4[24]\, Y - => \prdata_39[24]\); - - \prdata_RNO_7[0]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[0]\, Y - => \addr_data_f1_m_i[0]\); - - \prdata_RNO[10]\ : OR3C - port map(A => \prdata_39_0_iv_7[10]\, B => - \prdata_39_0_iv_6[10]\, C => \prdata_39_0_iv_8[10]\, Y - => \prdata_39[10]\); - - \reg_sp.addr_matrix_f0_1[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[17]\); - - \reg_wp.data_shaping_SP1\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => \data_shaping_SP1\); - - \reg_sp.addr_matrix_f2[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[22]\); - - \prdata_RNO_3[22]\ : OR3B - port map(A => N_168, B => \addr_data_f2[22]\, C => N_232, Y - => \addr_data_f2_m_i[22]\); - - \reg_wp.status_full_err_RNO[1]\ : MX2 - port map(A => pwdata_0(5), B => - \status_full_err_5_i_a2_0[1]\, S => N_74, Y => N_53); - - \reg_wp.delta_snapshot[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[1]\); - - \reg_sp.addr_matrix_f0_1[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[21]\); - - prdata_2_sqmuxa_0_a2_0 : NOR3A - port map(A => N_159, B => N_69, C => paddr_0(2), Y => - prdata_2_sqmuxa_0); - - \prdata_RNO_0[11]\ : NOR3C - port map(A => \prdata_39_0_iv_1[11]\, B => - \prdata_39_0_iv_0[11]\, C => \addr_data_f0_m_i[11]\, Y - => \prdata_39_0_iv_5[11]\); - - \prdata_RNO_7[27]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[27]\, - Y => \addr_matrix_f0_1_m_i[27]\); - - \prdata_RNO_0[16]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[16]\, - C => \addr_data_f2_m_i[16]\, Y => \prdata_39_0_iv_3[16]\); - - \reg_wp.addr_data_f3[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[11]\); - - \reg_sp.addr_matrix_f2[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[27]\); - - \reg_sp.addr_matrix_f1[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[29]\); - - \reg_wp.delta_f2_f0[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[1]\); - - \reg_wp.burst_f0_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => paddr(5), B => N_69, C => paddr(4), Y => - N_163); - - \reg_wp.addr_data_f1[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[17]\); - - \reg_wp.status_new_err_RNO[3]\ : MX2 - port map(A => pwdata_0(11), B => - \status_new_err_5_i_a2_0[3]\, S => N_74, Y => N_65); - - \prdata_RNO_6[6]\ : NAND2 - port map(A => \delta_snapshot[6]\, B => prdata_14_sqmuxa, Y - => \delta_snapshot_m_i[6]\); - - \reg_sp.addr_matrix_f2[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[4]\); - - \reg_wp.delta_f2_f1[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[2]\); - - \prdata_RNO_5[10]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[10]\, Y => \addr_matrix_f0_1_m_i[10]\); - - \prdata_RNO_2[10]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[10]\, - C => \prdata_39_0_iv_5[10]\, Y => \prdata_39_0_iv_8[10]\); - - \prdata_RNO_16[5]\ : OR2B - port map(A => status_error_bad_component_error, B => - prdata_1_sqmuxa, Y => - status_error_bad_component_error_m_i); - - \prdata_RNO_3[15]\ : AND2 - port map(A => \prdata_39_0_iv_1[15]\, B => - \prdata_39_0_iv_0[15]\, Y => \prdata_39_0_iv_2[15]\); - - \apbo.pirq_RNO_3[15]\ : NOR2 - port map(A => status_full_err_0(2), B => - status_full_err_0(3), Y => \pirq_2_i_a2_3[15]\); - - \prdata_RNO_2[4]\ : NOR3C - port map(A => \addr_data_f2_m_i[4]\, B => - \status_full_err_m_i[0]\, C => \prdata_39_0_iv_10[4]\, Y - => \prdata_39_0_iv_13[4]\); - - \prdata_RNO_16[3]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[3]\, Y - => \delta_f2_f1_m_i[3]\); - - \prdata_RNO_12[9]\ : OR2B - port map(A => \status_new_err[1]\, B => prdata_13_sqmuxa, Y - => \status_new_err_m_i[1]\); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2_0_0\ : NOR3A - port map(A => N_160, B => N_69, C => - addr_matrix_f1_1_sqmuxa_0_a2_1_0, Y => - addr_matrix_f2_1_sqmuxa_0); - - \reg_sp.addr_matrix_f0_1[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[0]\); - - \reg_wp.addr_data_f2[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[0]\); - - \reg_wp.addr_data_f2[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[12]\); - - \reg_sp.addr_matrix_f1[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[23]\); - - \prdata_RNO_4[27]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[27]\, - C => \addr_matrix_f0_1_m_i[27]\, Y => - \prdata_39_0_iv_1[27]\); - - \prdata_RNO_0[1]\ : NOR3C - port map(A => \prdata_39_0_iv_5[1]\, B => - \prdata_39_0_iv_4[1]\, C => \addr_data_f3_m_i[1]\, Y => - \prdata_39_0_iv_11[1]\); - - \prdata[10]\ : DFN1C0 - port map(D => \prdata_39[10]\, CLK => lclk_c, CLR => rstn, - Q => prdata(10)); - - \reg_sp.status_ready_matrix_f1\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f1); - - \prdata_RNO_0[12]\ : NOR3C - port map(A => \prdata_39_0_iv_1[12]\, B => - \prdata_39_0_iv_0[12]\, C => \delta_snapshot_m_i[12]\, Y - => \prdata_39_0_iv_4[12]\); - - \prdata_RNO_2[7]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[7]\, C - => \prdata_39_0_iv_7[7]\, Y => \prdata_39_0_iv_10[7]\); - - \reg_wp.addr_data_f0[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[4]\); - - prdata_2_sqmuxa_0_a2 : NOR3A - port map(A => N_159, B => N_69, C => paddr_2(2), Y => - prdata_2_sqmuxa); - - \prdata_RNO[1]\ : OR3C - port map(A => \prdata_39_0_iv_11[1]\, B => - \prdata_39_0_iv_10[1]\, C => \prdata_39_0_iv_15[1]\, Y - => \prdata_39[1]\); - - \prdata_RNO_1[5]\ : NOR3C - port map(A => \prdata_39_0_iv_5[5]\, B => - \prdata_39_0_iv_4[5]\, C => \delta_snapshot_m_i[5]\, Y - => \prdata_39_0_iv_10[5]\); - - \reg_sp.addr_matrix_f0_1[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[28]\); - - \reg_sp.addr_matrix_f0_0[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[14]\); - - \prdata_RNO_1[2]\ : NOR3C - port map(A => \prdata_39_0_iv_6[2]\, B => - \prdata_39_0_iv_5[2]\, C => \delta_snapshot_m_i[2]\, Y - => \prdata_39_0_iv_11[2]\); - - \reg_sp.addr_matrix_f0_0[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[15]\); - - \reg_sp.addr_matrix_f0_0[1]\ : DFN1E1C0 - port map(D => pwdata_1_0, CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[1]\); - - \prdata_RNO_1[24]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[24]\, Y - => \addr_data_f1_m_i[24]\); - - \reg_sp.addr_matrix_f0_1[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[30]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_162, B => N_69, C => - addr_matrix_f1_1_sqmuxa_0_a2_1_0, Y => - addr_matrix_f1_1_sqmuxa); - - \prdata_RNO_0[27]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[27]\, C - => \addr_data_f2_m_i[27]\, Y => \prdata_39_0_iv_3[27]\); - - \prdata[13]\ : DFN1C0 - port map(D => \prdata_39[13]\, CLK => lclk_c, CLR => rstn, - Q => prdata(13)); - - \reg_wp.delta_f2_f0[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[3]\); - - \reg_wp.enable_f0\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \enable_f0\); - - \reg_sp.addr_matrix_f1[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[15]\); - - \prdata_RNO_8[15]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[15]\, - C => \addr_matrix_f2_m_i[15]\, Y => - \prdata_39_0_iv_0[15]\); - - \prdata_RNO_3[18]\ : OR3B - port map(A => N_168, B => \addr_data_f2[18]\, C => N_232_1, - Y => \addr_data_f2_m_i[18]\); - - \prdata_RNO[15]\ : OR3C - port map(A => \prdata_39_0_iv_4[15]\, B => - \prdata_39_0_iv_3[15]\, C => \prdata_39_0_iv_5[15]\, Y - => \prdata_39[15]\); - - \prdata_RNO_4[10]\ : NOR3C - port map(A => \nb_snapshot_param_m_i[10]\, B => - \nb_burst_available_m_i[10]\, C => - \addr_matrix_f1_m_i[10]\, Y => \prdata_39_0_iv_1[10]\); - - \reg_wp.addr_data_f3[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[0]\); - - \prdata_RNO_7[11]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[11]\, C => - N_232_1, Y => \addr_data_f2_m_i[11]\); - - \reg_wp.addr_data_f0[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[5]\); - - \prdata_RNO_7[16]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[16]\, Y => \addr_matrix_f0_1_m_i[16]\); - - \reg_sp.addr_matrix_f1[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[12]\); - - \prdata[3]\ : DFN1C0 - port map(D => \prdata_39[3]\, CLK => lclk_c, CLR => rstn, Q - => prdata(3)); - - \reg_wp.addr_data_f2[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[27]\); - - \reg_wp.burst_f0\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \burst_f0\); - - \prdata_RNO_10[4]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[4]\, - Y => \addr_matrix_f0_1_m_i[4]\); - - \reg_wp.addr_data_f3[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[15]\); - - \prdata[5]\ : DFN1C0 - port map(D => \prdata_39[5]\, CLK => lclk_c, CLR => rstn, Q - => prdata(5)); - - \reg_sp.addr_matrix_f1[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[17]\); - - \reg_wp.addr_data_f3[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[16]\); - - \prdata_RNO_6[21]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[21]\, Y - => \addr_data_f0_m_i[21]\); - - \prdata_RNO_11[8]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[8]\, - Y => \addr_matrix_f2_m_i[8]\); - - \prdata_RNO_6[26]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[26]\, Y - => \addr_data_f0_m_i[26]\); - - \reg_wp.addr_data_f0[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[24]\); - - \prdata_RNO_15[7]\ : OR2B - port map(A => \nb_snapshot_param[7]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[7]\); - - \reg_sp.addr_matrix_f2[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[9]\); - - \prdata_RNO_7[5]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[5]\, - C => \addr_matrix_f2_m_i[5]\, Y => \prdata_39_0_iv_4[5]\); - - GND_i : GND - port map(Y => \GND\); - - \prdata_RNO_2[1]\ : NOR3C - port map(A => \addr_data_f1_m_i[1]\, B => - \addr_data_f0_m_i[1]\, C => \prdata_39_0_iv_12[1]\, Y => - \prdata_39_0_iv_15[1]\); - - \reg_wp.status_new_err[0]\ : DFN1C0 - port map(D => N_59, CLK => lclk_c, CLR => rstn, Q => - \status_new_err[0]\); - - \reg_wp.status_new_err_RNO[0]\ : MX2 - port map(A => pwdata_0(8), B => - \status_new_err_5_i_a2_0[0]\, S => N_74, Y => N_59); - - \prdata_RNO_7[12]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[12]\, - Y => \addr_data_f1_m_i[12]\); - - \prdata_RNO_9[2]\ : AOI1B - port map(A => \status_full[2]\, B => prdata_13_sqmuxa, C - => \addr_data_f2_m_i[2]\, Y => \prdata_39_0_iv_9[2]\); - - \reg_wp.status_full[1]\ : DFN1C0 - port map(D => N_45, CLK => lclk_c, CLR => rstn, Q => - \status_full[1]\); - - \reg_wp.addr_data_f0[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[0]\); - - \prdata_RNO_8[18]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[18]\, Y - => \addr_matrix_f2_m_i[18]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_o2\ : - OR2A - port map(A => N_68, B => paddr(6), Y => N_69); - - \reg_sp.addr_matrix_f1[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[28]\); - - \prdata_RNO_7[8]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[8]\, Y - => \addr_data_f3_m_i[8]\); - - \reg_wp.addr_data_f0[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[28]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_o2_0_0\ : - OR2 - port map(A => paddr(7), B => N_749, Y => - config_active_interruption_onError_0_sqmuxa_0_o2_0_0); - - \prdata_RNO_14[1]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[1]\, - C => \addr_matrix_f0_1_m_i[1]\, Y => - \prdata_39_0_iv_7[1]\); - - \reg_wp.delta_snapshot[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[5]\); - - \prdata_RNO_2[20]\ : NOR3C - port map(A => \prdata_39_0_iv_1[20]\, B => - \prdata_39_0_iv_0[20]\, C => \addr_data_f0_m_i[20]\, Y - => \prdata_39_0_iv_4[20]\); - - \prdata_RNO_6[22]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[22]\, Y - => \addr_data_f0_m_i[22]\); - - \prdata_RNO_10[11]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[11]\, Y => \addr_matrix_f0_1_m_i[11]\); - - \reg_wp.nb_snapshot_param[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[0]\); - - \prdata_RNO_3[9]\ : NOR3C - port map(A => \addr_matrix_f0_0_m_i[9]\, B => - \addr_matrix_f2_m_i[9]\, C => \status_new_err_m_i[1]\, Y - => \prdata_39_0_iv_6[9]\); - - \reg_wp.addr_data_f0[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[14]\); - - \prdata_RNO_1[31]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[31]\, Y - => \addr_data_f1_m_i[31]\); - - \prdata_RNO_6[8]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[8]\, Y - => \delta_snapshot_m_i[8]\); - - \prdata_RNO_5[30]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[30]\, - C => \addr_matrix_f2_m_i[30]\, Y => - \prdata_39_0_iv_0[30]\); - - \prdata_RNO_4[7]\ : NOR3C - port map(A => \prdata_39_0_iv_1[7]\, B => - \prdata_39_0_iv_0[7]\, C => \addr_matrix_f1_m_i[7]\, Y - => \prdata_39_0_iv_3[7]\); - - \reg_sp.addr_matrix_f0_1[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[16]\); - - \prdata_RNO_5[29]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[29]\, C - => \addr_matrix_f2_m_i[29]\, Y => \prdata_39_0_iv_0[29]\); - - \prdata_RNO_5[4]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[4]\, - C => burst_f0_m_i, Y => \prdata_39_0_iv_5[4]\); - - \prdata_RNO_1[9]\ : NOR3C - port map(A => \prdata_39_0_iv_3[9]\, B => - \addr_matrix_f0_1_m_i[9]\, C => \delta_snapshot_m_i[9]\, - Y => \prdata_39_0_iv_8[9]\); - - \reg_wp.addr_data_f2[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[1]\); - - \reg_wp.delta_f2_f0[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[5]\); - - \prdata_RNO_3[17]\ : OR3B - port map(A => N_168, B => \addr_data_f2[17]\, C => N_232_1, - Y => \addr_data_f2_m_i[17]\); - - \prdata_RNO_1[23]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[23]\, Y - => \addr_data_f1_m_i[23]\); - - \prdata_RNO[2]\ : OR3C - port map(A => \prdata_39_0_iv_12[2]\, B => - \prdata_39_0_iv_11[2]\, C => \prdata_39_0_iv_13[2]\, Y - => \prdata_39[2]\); - - \reg_wp.delta_snapshot[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[6]\); - - \prdata[15]\ : DFN1C0 - port map(D => \prdata_39[15]\, CLK => lclk_c, CLR => rstn, - Q => prdata(15)); - - \reg_wp.delta_snapshot[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[8]\); - - \reg_wp.nb_burst_available[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[6]\); - - \reg_wp.status_full_err_RNO[2]\ : MX2 - port map(A => pwdata_0(6), B => - \status_full_err_5_i_a2_0[2]\, S => N_74, Y => N_55); - - \reg_wp.addr_data_f1[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[23]\); - - \reg_wp.addr_data_f0[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[18]\); - - \reg_wp.addr_data_f1[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[20]\); - - \prdata[6]\ : DFN1C0 - port map(D => \prdata_39[6]\, CLK => lclk_c, CLR => rstn, Q - => prdata(6)); - - \prdata_RNO_4[3]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[3]\, - C => \addr_matrix_f0_1_m_i[3]\, Y => - \prdata_39_0_iv_6[3]\); - - \prdata_RNO_10[9]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[9]\, - Y => \addr_matrix_f0_0_m_i[9]\); - - \reg_wp.status_new_err_RNO[2]\ : MX2 - port map(A => pwdata_0(10), B => - \status_new_err_5_i_a2_0[2]\, S => N_74, Y => N_63); - - \prdata_RNO_11[6]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[6]\, - Y => \addr_matrix_f0_1_m_i[6]\); - - \reg_sp.addr_matrix_f0_0[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[22]\); - - \reg_wp.status_new_err[2]\ : DFN1C0 - port map(D => N_63, CLK => lclk_c, CLR => rstn, Q => - \status_new_err[2]\); - - \prdata_RNO_17[4]\ : OR2B - port map(A => \nb_burst_available[4]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[4]\); - - \prdata_RNO_21[2]\ : NAND2 - port map(A => \delta_f2_f0[2]\, B => prdata_16_sqmuxa, Y - => \delta_f2_f0_m_i[2]\); - - \reg_wp.addr_data_f0[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[3]\); - - \reg_wp.addr_data_f3[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[12]\); - - \prdata_RNO_0[6]\ : NOR3C - port map(A => \status_full_err_m_i[2]\, B => - \prdata_39_0_iv_5[6]\, C => \addr_data_f0_m_i[6]\, Y => - \prdata_39_0_iv_10[6]\); - - prdata_4_sqmuxa_0_a2_0 : NOR3 - port map(A => N_69, B => addr_matrix_f1_1_sqmuxa_0_a2_1_0, - C => N_232, Y => prdata_4_sqmuxa_0); - - \reg_wp.delta_f2_f1[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[3]\); - - \prdata_RNO_8[24]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[24]\, Y - => \addr_matrix_f2_m_i[24]\); - - \reg_wp.addr_data_f1[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[21]\); - - \prdata_RNO_2[0]\ : NOR3C - port map(A => \addr_data_f1_m_i[0]\, B => - \addr_data_f0_m_i[0]\, C => \prdata_39_0_iv_12[0]\, Y => - \prdata_39_0_iv_15[0]\); - - \reg_wp.delta_f2_f0[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[8]\); - - \reg_wp.addr_data_f2[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[9]\); - - \prdata_RNO[27]\ : OR3C - port map(A => \prdata_39_0_iv_3[27]\, B => - \addr_data_f1_m_i[27]\, C => \prdata_39_0_iv_4[27]\, Y - => \prdata_39[27]\); - - \prdata_RNO_8[30]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[30]\, Y - => \addr_matrix_f2_m_i[30]\); - - \prdata_RNO_3[29]\ : OR3B - port map(A => N_168, B => \addr_data_f2[29]\, C => N_232, Y - => \addr_data_f2_m_i[29]\); - - prdata_4_sqmuxa_0_a2 : NOR3 - port map(A => N_69, B => addr_matrix_f1_1_sqmuxa_0_a2_1_0, - C => N_232, Y => prdata_4_sqmuxa); - - \prdata_RNO_8[17]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[17]\, Y - => \addr_matrix_f2_m_i[17]\); - - \reg_wp.status_full_RNO_0[3]\ : OR2 - port map(A => \status_full[3]\, B => status_full_0(3), Y - => \status_full_5_i_a2_0[3]\); - - \prdata_RNO_20[5]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[5]\, Y - => \delta_f2_f1_m_i[5]\); - - \prdata_RNO_18[2]\ : OR2B - port map(A => prdata_7_sqmuxa, B => \data_shaping_SP1\, Y - => data_shaping_SP1_m_i); - - \apbo.pirq_RNO_1[15]\ : NOR2B - port map(A => \pirq_2_i_a2_0[15]\, B => \pirq_2_i_a2_1[15]\, - Y => \pirq_2_i_a2_6[15]\); - - \reg_wp.status_full_err_RNO_0[0]\ : OR2 - port map(A => \status_full_err[0]\, B => - status_full_err_0(0), Y => \status_full_err_5_i_a2_0[0]\); - - \prdata_RNO_6[14]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[14]\, C => - N_232_1, Y => \addr_data_f2_m_i[14]\); - - \prdata_RNO_1[11]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[11]\, - C => \delta_snapshot_m_i[11]\, Y => - \prdata_39_0_iv_4[11]\); - - \prdata_RNO_1[16]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[16]\, Y - => \addr_data_f1_m_i[16]\); - - \apbo.pirq[15]\ : DFN1C0 - port map(D => N_1016_i_0, CLK => lclk_c, CLR => rstn, Q => - pirq(15)); - - \reg_wp.addr_data_f1[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[4]\); - - \prdata_RNO[19]\ : OR3C - port map(A => \prdata_39_0_iv_3[19]\, B => - \addr_data_f1_m_i[19]\, C => \prdata_39_0_iv_4[19]\, Y - => \prdata_39[19]\); - - \reg_wp.data_shaping_BW\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => \Bias_Fails_c\); - - \prdata_RNO_17[1]\ : OR2B - port map(A => \nb_burst_available[1]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[1]\); - - \reg_sp.addr_matrix_f2[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[0]\); - - \prdata_RNO_9[1]\ : NOR3C - port map(A => \prdata_39_0_iv_7[1]\, B => - \prdata_39_0_iv_6[1]\, C => \delta_snapshot_m_i[1]\, Y - => \prdata_39_0_iv_12[1]\); - - \prdata_RNO_1[0]\ : AOI1B - port map(A => \status_full[0]\, B => prdata_13_sqmuxa, C - => \addr_data_f2_m_i[0]\, Y => \prdata_39_0_iv_10[0]\); - - \prdata_RNO_10[1]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[1]\, Y - => \addr_matrix_f1_m_i[1]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_a2_0\ : NOR3B - port map(A => N_159, B => N_71, C => N_69, Y => - addr_matrix_f0_0_1_sqmuxa_0); - - \reg_wp.addr_data_f1[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[13]\); - - \reg_wp.delta_snapshot[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[4]\); - - \reg_wp.addr_data_f1[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[10]\); - - \reg_wp.status_full_RNO_0[0]\ : OR2 - port map(A => \status_full[0]\, B => status_full_0(0), Y - => \status_full_5_i_a2_0[0]\); - - \reg_sp.addr_matrix_f1[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[9]\); - - \reg_wp.delta_f2_f1[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[8]\); - - \reg_sp.addr_matrix_f0_1[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[10]\); - - \prdata_RNO_19[3]\ : OR2B - port map(A => \nb_snapshot_param[3]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[3]\); - - \prdata_RNO_2[5]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[5]\, C - => \prdata_39_0_iv_9[5]\, Y => \prdata_39_0_iv_12[5]\); - - \prdata_RNO_2[6]\ : NOR3C - port map(A => \addr_data_f3_m_i[6]\, B => - \addr_data_f2_m_i[6]\, C => \addr_data_f1_m_i[6]\, Y => - \prdata_39_0_iv_11[6]\); - - prdata_8_sqmuxa_0_a2 : NOR2A - port map(A => N_163, B => N_6455, Y => prdata_8_sqmuxa); - - \prdata_RNO_0[19]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[19]\, - C => \addr_data_f2_m_i[19]\, Y => \prdata_39_0_iv_3[19]\); - - \prdata[12]\ : DFN1C0 - port map(D => \prdata_39[12]\, CLK => lclk_c, CLR => rstn, - Q => prdata(12)); - - \reg_sp.addr_matrix_f0_1[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[13]\); - - \prdata_RNO_1[12]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[12]\, - C => \addr_data_f2_m_i[12]\, Y => \prdata_39_0_iv_3[12]\); - - \reg_sp.addr_matrix_f0_0[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[9]\); - - \reg_wp.addr_data_f1[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[11]\); - - prdata_0_sqmuxa_0_a2 : NOR3 - port map(A => rdata61_2, B => N_69, C => N_232, Y => - prdata_0_sqmuxa); - - \prdata_RNO_5[25]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[25]\, C - => \addr_matrix_f2_m_i[25]\, Y => \prdata_39_0_iv_0[25]\); - - \prdata[19]\ : DFN1C0 - port map(D => \prdata_39[19]\, CLK => lclk_c, CLR => rstn, - Q => prdata(19)); - - \prdata_RNO_11[4]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f0\, Y => - burst_f0_m_i); - - \reg_wp.delta_f2_f0[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[7]\); - - \prdata_RNO_11[11]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[11]\, - Y => \addr_matrix_f2_m_i[11]\); - - \reg_sp.addr_matrix_f0_1[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[29]\); - - \reg_wp.status_full_RNO[1]\ : MX2 - port map(A => pwdata_0(1), B => \status_full_5_i_a2_0[1]\, - S => N_74, Y => N_45); - - \reg_wp.nb_burst_available[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[5]\); - - \prdata_RNO_7[30]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[30]\, - Y => \addr_matrix_f0_1_m_i[30]\); - - \reg_wp.addr_data_f3[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[8]\); - - \prdata_RNO_5[11]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[11]\, Y - => \addr_data_f0_m_i[11]\); - - \reg_wp.addr_data_f0[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[29]\); - - \prdata_RNO_5[16]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[16]\, - C => \addr_matrix_f2_m_i[16]\, Y => - \prdata_39_0_iv_0[16]\); - - \prdata_RNO_2[11]\ : NOR3C - port map(A => \addr_data_f2_m_i[11]\, B => - \status_new_err_m_i[3]\, C => \addr_data_f1_m_i[11]\, Y - => \prdata_39_0_iv_6[11]\); - - \prdata_RNO_2[16]\ : NOR3C - port map(A => \prdata_39_0_iv_1[16]\, B => - \prdata_39_0_iv_0[16]\, C => \addr_data_f0_m_i[16]\, Y - => \prdata_39_0_iv_4[16]\); - - \prdata_RNO_13[10]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[10]\, Y - => \addr_matrix_f1_m_i[10]\); - - \reg_wp.nb_burst_available[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[8]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2\ : NOR2B - port map(A => N_168, B => N_162, Y => addr_data_f2_1_sqmuxa); - - prdata_13_sqmuxa_0_a2 : NOR3A - port map(A => paddr(4), B => N_72, C => paddr_2(2), Y => - prdata_13_sqmuxa); - - \reg_wp.delta_f2_f0[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[0]\); - - \reg_sp.status_error_bad_component_error\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_error_bad_component_error); - - \prdata_RNO_12[10]\ : OR2B - port map(A => \nb_burst_available[10]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[10]\); - - \reg_wp.addr_data_f3[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[24]\); - - \reg_wp.nb_burst_available[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[4]\); - - prdata_10_sqmuxa_0_a2_0 : NOR3A - port map(A => paddr_0(2), B => paddr_0(4), C => N_72, Y => - prdata_10_sqmuxa_0); - - \reg_wp.addr_data_f1[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[25]\); - - \reg_wp.addr_data_f1[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[26]\); - - \prdata_RNO_0[30]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[30]\, - C => \addr_data_f2_m_i[30]\, Y => \prdata_39_0_iv_3[30]\); - - \reg_wp.addr_data_f1[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[1]\); - - \prdata_RNO_8[23]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[23]\, Y - => \addr_matrix_f2_m_i[23]\); - - \reg_sp.addr_matrix_f2[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[3]\); - - \reg_sp.addr_matrix_f2[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[19]\); - - \status_full_ack[0]\ : DFN1C0 - port map(D => \status_full_ack_8[0]\, CLK => lclk_c, CLR - => rstn, Q => status_full_ack(0)); - - \prdata[21]\ : DFN1C0 - port map(D => \prdata_39[21]\, CLK => lclk_c, CLR => rstn, - Q => prdata(21)); - - \prdata_RNO_3[8]\ : NOR3C - port map(A => \addr_matrix_f0_0_m_i[8]\, B => - \addr_matrix_f2_m_i[8]\, C => \status_new_err_m_i[0]\, Y - => \prdata_39_0_iv_6[8]\); - - \prdata_RNO_5[12]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[12]\, - Y => \delta_snapshot_m_i[12]\); - - \reg_wp.addr_data_f3[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[28]\); - - \reg_wp.addr_data_f2[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[23]\); - - \prdata_RNO_5[28]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[28]\, C - => \addr_matrix_f2_m_i[28]\, Y => \prdata_39_0_iv_0[28]\); - - \prdata_RNO_2[12]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[12]\, C - => \addr_data_f1_m_i[12]\, Y => \prdata_39_0_iv_5[12]\); - - \reg_wp.addr_data_f2[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[20]\); - - \prdata_RNO_1[20]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[20]\, Y - => \addr_data_f1_m_i[20]\); - - \prdata_RNO_10[0]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[0]\, Y - => \addr_matrix_f1_m_i[0]\); - - \reg_wp.data_shaping_SP0\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => \data_shaping_SP0\); - - \prdata_RNO_6[13]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[13]\, C => - N_232_1, Y => \addr_data_f2_m_i[13]\); - - \prdata_RNO_3[25]\ : OR3B - port map(A => N_168, B => \addr_data_f2[25]\, C => N_232, Y - => \addr_data_f2_m_i[25]\); - - \reg_wp.addr_data_f0[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[19]\); - - \prdata_RNO_11[9]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[9]\, - Y => \addr_matrix_f2_m_i[9]\); - - \prdata_RNO_17[9]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[9]\, Y - => \delta_f2_f1_m_i[9]\); - - \reg_wp.data_shaping_R1_0\ : DFN1E1C0 - port map(D => pwdata_0(4), CLK => lclk_c, CLR => rstn, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_R1_0\); - - \prdata_RNO_8[5]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[5]\, Y - => \delta_snapshot_m_i[5]\); - - \prdata_RNO_6[3]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[3]\, Y - => \delta_snapshot_m_i[3]\); - - \reg_sp.addr_matrix_f2[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[13]\); - - \prdata_RNO_17[6]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[6]\, Y - => \addr_matrix_f1_m_i[6]\); - - \prdata_RNO_7[19]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[19]\, - Y => \addr_matrix_f0_1_m_i[19]\); - - \prdata_RNO_9[14]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[14]\, - Y => \addr_matrix_f2_m_i[14]\); - - \prdata_RNO_7[24]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[24]\, - Y => \addr_matrix_f0_1_m_i[24]\); - - \prdata_RNO[21]\ : OR3C - port map(A => \prdata_39_0_iv_3[21]\, B => - \addr_data_f1_m_i[21]\, C => \prdata_39_0_iv_4[21]\, Y - => \prdata_39[21]\); - - \prdata[1]\ : DFN1C0 - port map(D => \prdata_39[1]\, CLK => lclk_c, CLR => rstn, Q - => prdata(1)); - - \reg_wp.delta_snapshot[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[10]\); - - \reg_sp.addr_matrix_f2[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[29]\); - - \reg_wp.addr_data_f2[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[21]\); - - \reg_wp.addr_data_f3[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[7]\); - - \prdata_RNO_4[11]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[11]\, - C => \addr_matrix_f2_m_i[11]\, Y => - \prdata_39_0_iv_0[11]\); - - \prdata_RNO_4[16]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[16]\, C => \addr_matrix_f0_1_m_i[16]\, - Y => \prdata_39_0_iv_1[16]\); - - \prdata_RNO_1[7]\ : NOR3C - port map(A => \prdata_39_0_iv_3[7]\, B => - \addr_matrix_f0_1_m_i[7]\, C => \delta_snapshot_m_i[7]\, - Y => \prdata_39_0_iv_8[7]\); - - \prdata_RNO_7[9]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[9]\, Y - => \addr_data_f3_m_i[9]\); - - \prdata_RNO_6[29]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[29]\, Y - => \addr_data_f0_m_i[29]\); - - \prdata_RNO_19[2]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[2]\, Y - => \addr_matrix_f1_m_i[2]\); - - \reg_wp.addr_data_f1[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[15]\); - - \prdata_RNO_16[2]\ : AND2 - port map(A => \delta_f2_f1_m_i[2]\, B => - \delta_f2_f0_m_i[2]\, Y => \prdata_39_0_iv_0[2]\); - - \reg_wp.status_full_err_RNO[0]\ : MX2 - port map(A => pwdata_1_3, B => - \status_full_err_5_i_a2_0[0]\, S => N_74, Y => N_51); - - \reg_wp.addr_data_f1[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[16]\); - - \prdata_RNO_5[9]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[9]\, - Y => \addr_matrix_f0_1_m_i[9]\); - - \reg_sp.addr_matrix_f1[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[26]\); - - prdata_7_sqmuxa_0_a2 : NOR2A - port map(A => N_163, B => N_232, Y => prdata_7_sqmuxa); - - \reg_sp.addr_matrix_f2[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[2]\); - - \reg_sp.addr_matrix_f0_1[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[14]\); - - \reg_sp.addr_matrix_f0_1[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[15]\); - - \prdata_RNO[26]\ : OR3C - port map(A => \prdata_39_0_iv_3[26]\, B => - \addr_data_f1_m_i[26]\, C => \prdata_39_0_iv_4[26]\, Y - => \prdata_39[26]\); - - \prdata_RNO_0[15]\ : AND2 - port map(A => \prdata_39_0_iv_2[15]\, B => - \delta_snapshot_m_i[15]\, Y => \prdata_39_0_iv_4[15]\); - - \prdata[31]\ : DFN1C0 - port map(D => \prdata_39[31]\, CLK => lclk_c, CLR => rstn, - Q => prdata(31)); - - \reg_wp.addr_data_f1_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_166, B => paddr_0(4), C => N_72, Y => - addr_data_f1_1_sqmuxa); - - \reg_wp.addr_data_f2[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[30]\); - - \reg_sp.addr_matrix_f0_1[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[7]\); - - \prdata_RNO_4[24]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[24]\, - C => \addr_matrix_f0_1_m_i[24]\, Y => - \prdata_39_0_iv_1[24]\); - - \reg_sp.addr_matrix_f1[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[21]\); - - \reg_sp.addr_matrix_f2[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[23]\); - - \reg_wp.addr_data_f3[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[3]\); - - \prdata_RNO_3[28]\ : OR3B - port map(A => N_168, B => \addr_data_f2[28]\, C => N_232, Y - => \addr_data_f2_m_i[28]\); - - \reg_sp.addr_matrix_f1[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[20]\); - - prdata_1_sqmuxa_0_a2 : NOR3 - port map(A => rdata61_2, B => N_69, C => N_6455, Y => - prdata_1_sqmuxa); - - \prdata[16]\ : DFN1C0 - port map(D => \prdata_39[16]\, CLK => lclk_c, CLR => rstn, - Q => prdata(16)); - - \prdata_RNO_4[0]\ : NOR3C - port map(A => \prdata_39_0_iv_1[0]\, B => - \prdata_39_0_iv_0[0]\, C => \prdata_39_0_iv_2[0]\, Y => - \prdata_39_0_iv_4[0]\); - - \status_full_ack[2]\ : DFN1C0 - port map(D => \status_full_ack_8[2]\, CLK => lclk_c, CLR - => rstn, Q => status_full_ack(2)); - - \prdata_RNO_4[12]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[12]\, - C => \addr_matrix_f2_m_i[12]\, Y => - \prdata_39_0_iv_0[12]\); - - \prdata_RNO[0]\ : OR3C - port map(A => \prdata_39_0_iv_11[0]\, B => - \prdata_39_0_iv_10[0]\, C => \prdata_39_0_iv_15[0]\, Y - => \prdata_39[0]\); - - \reg_wp.addr_data_f1[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[22]\); - - \prdata_RNO_12[5]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[5]\, - Y => \addr_matrix_f0_1_m_i[5]\); - - \reg_wp.addr_data_f2[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[31]\); - - \reg_wp.nb_snapshot_param[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[3]\); - - \reg_sp.addr_matrix_f0_0[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[12]\); - - \prdata_RNO_0[24]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[24]\, C - => \addr_data_f2_m_i[24]\, Y => \prdata_39_0_iv_3[24]\); - - \reg_sp.status_error_anticipating_empty_fifo\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_error_anticipating_empty_fifo); - - \reg_sp.addr_matrix_f0_0[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[8]\); - - \status_full_ack_RNO[0]\ : NOR3A - port map(A => \status_full[0]\, B => pwdata_0(0), C => N_74, - Y => \status_full_ack_8[0]\); - - \prdata_RNO_2[21]\ : NOR3C - port map(A => \prdata_39_0_iv_1[21]\, B => - \prdata_39_0_iv_0[21]\, C => \addr_data_f0_m_i[21]\, Y - => \prdata_39_0_iv_4[21]\); - - \reg_sp.addr_matrix_f0_0[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[21]\); - - \prdata_RNO_2[26]\ : NOR3C - port map(A => \prdata_39_0_iv_1[26]\, B => - \prdata_39_0_iv_0[26]\, C => \addr_data_f0_m_i[26]\, Y - => \prdata_39_0_iv_4[26]\); - - \prdata_RNO_5[27]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[27]\, C - => \addr_matrix_f2_m_i[27]\, Y => \prdata_39_0_iv_0[27]\); - - \reg_wp.addr_data_f0[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[2]\); - - \reg_sp.addr_matrix_f0_0[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[0]\); - - \prdata_RNO_5[1]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[1]\, Y - => \addr_data_f3_m_i[1]\); - - \prdata_RNO_15[8]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[8]\, Y - => \addr_matrix_f1_m_i[8]\); - - \prdata_RNO_15[6]\ : AOI1B - port map(A => \nb_burst_available[6]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[6]\, Y => - \prdata_39_0_iv_1[6]\); - - \reg_wp.status_full[3]\ : DFN1C0 - port map(D => N_49, CLK => lclk_c, CLR => rstn, Q => - \status_full[3]\); - - \prdata_RNO_16[1]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[1]\, Y - => \delta_snapshot_m_i[1]\); - - \prdata[2]\ : DFN1C0 - port map(D => \prdata_39[2]\, CLK => lclk_c, CLR => rstn, Q - => prdata(2)); - - \reg_wp.delta_snapshot[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[2]\); - - \prdata_RNO_5[31]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[31]\, C - => \addr_matrix_f2_m_i[31]\, Y => \prdata_39_0_iv_0[31]\); - - prdata_9_sqmuxa_0_a2 : NOR3 - port map(A => paddr_0(4), B => N_72, C => paddr_2(2), Y => - prdata_9_sqmuxa); - - \prdata_RNO_5[2]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[2]\, - C => enable_f2_m_i, Y => \prdata_39_0_iv_5[2]\); - - \prdata_RNO_0[18]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[18]\, - C => \addr_data_f2_m_i[18]\, Y => \prdata_39_0_iv_3[18]\); - - \reg_wp.nb_snapshot_param[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[6]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0_1\ : NOR2B - port map(A => N_168, B => N_162, Y => - addr_data_f2_1_sqmuxa_0); - - \reg_sp.addr_matrix_f2[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[18]\); - - \lpp_top_apbreg.reg_wp.status_full_5_i_o2[0]\ : OR3B - port map(A => paddr(4), B => N_71, C => N_72, Y => N_74); - - \reg_wp.status_new_err_RNO_0[0]\ : OR2 - port map(A => \status_new_err[0]\, B => status_new_err_0(0), - Y => \status_new_err_5_i_a2_0[0]\); - - \reg_wp.delta_f2_f1[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[6]\); - - \reg_sp.addr_matrix_f0_1[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[27]\); - - \reg_wp.status_full_err[0]\ : DFN1C0 - port map(D => N_51, CLK => lclk_c, CLR => rstn, Q => - \status_full_err[0]\); - - \prdata_RNO_18[3]\ : OR2B - port map(A => status_ready_matrix_f2, B => prdata_1_sqmuxa, - Y => status_ready_matrix_f2_m_i); - - \reg_sp.addr_matrix_f1[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[4]\); - - \reg_sp.addr_matrix_f1[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[19]\); - - \reg_wp.addr_data_f2[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[25]\); - - \prdata_RNO_9[9]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[9]\, Y - => \addr_data_f1_m_i[9]\); - - \prdata_RNO_9[13]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[13]\, - Y => \addr_matrix_f2_m_i[13]\); - - \prdata_RNO_3[5]\ : OR2B - port map(A => \status_full_err[1]\, B => prdata_13_sqmuxa, - Y => \status_full_err_m_i[1]\); - - \prdata_RNO_0[4]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[4]\, C - => \addr_data_f1_m_i[4]\, Y => \prdata_39_0_iv_12[4]\); - - \prdata_RNO_7[23]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[23]\, - Y => \addr_matrix_f0_1_m_i[23]\); - - \reg_wp.addr_data_f2[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[26]\); - - \prdata_RNO_2[22]\ : NOR3C - port map(A => \prdata_39_0_iv_1[22]\, B => - \prdata_39_0_iv_0[22]\, C => \addr_data_f0_m_i[22]\, Y - => \prdata_39_0_iv_4[22]\); - - \reg_sp.addr_matrix_f0_1[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[8]\); - - \reg_wp.delta_snapshot[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[7]\); - - \reg_sp.addr_matrix_f0_0[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[3]\); - - \prdata_RNO_18[6]\ : OR2B - port map(A => \nb_snapshot_param[6]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[6]\); - - \reg_wp.burst_f1\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \burst_f1\); - - \prdata_RNO_7[15]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[15]\, C => \addr_matrix_f0_1_m_i[15]\, - Y => \prdata_39_0_iv_1[15]\); - - \reg_wp.addr_data_f1[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[12]\); - - \reg_sp.addr_matrix_f1[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[7]\); - - \reg_wp.status_full_RNO[2]\ : MX2 - port map(A => pwdata_0(2), B => \status_full_5_i_a2_0[2]\, - S => N_74, Y => N_47); - - \reg_wp.nb_burst_available[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[1]\); - - \prdata_RNO_8[20]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[20]\, Y - => \addr_matrix_f2_m_i[20]\); - - \prdata_RNO_0[5]\ : NOR3C - port map(A => \status_full_err_m_i[1]\, B => - \prdata_39_0_iv_6[5]\, C => \addr_data_f0_m_i[5]\, Y => - \prdata_39_0_iv_11[5]\); - - \reg_wp.addr_data_f2[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[14]\); - - \reg_sp.addr_matrix_f0_0[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[28]\); - - \reg_wp.addr_data_f3[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[30]\); - - \prdata_RNO_3[27]\ : OR3B - port map(A => N_168, B => \addr_data_f2[27]\, C => N_232, Y - => \addr_data_f2_m_i[27]\); - - \reg_wp.addr_data_f0[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[1]\); - - \reg_sp.addr_matrix_f1[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[13]\); - - \prdata_RNO_6[25]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[25]\, Y - => \addr_data_f0_m_i[25]\); - - \reg_wp.addr_data_f3[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[29]\); - - \reg_sp.addr_matrix_f2[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[28]\); - - \prdata_RNO_12[8]\ : OR2B - port map(A => \status_new_err[0]\, B => prdata_13_sqmuxa, Y - => \status_new_err_m_i[0]\); - - \prdata_RNO_4[23]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[23]\, - C => \addr_matrix_f0_1_m_i[23]\, Y => - \prdata_39_0_iv_1[23]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_0_0\ : NOR3A - port map(A => N_162, B => N_69, C => - addr_matrix_f1_1_sqmuxa_0_a2_1_0, Y => - addr_matrix_f1_1_sqmuxa_0); - - \prdata_RNO_1[19]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[19]\, Y - => \addr_data_f1_m_i[19]\); - - \prdata_RNO_8[31]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[31]\, Y - => \addr_matrix_f2_m_i[31]\); - - \prdata_RNO_7[2]\ : NOR3C - port map(A => \prdata_39_0_iv_2[2]\, B => - \prdata_39_0_iv_1[2]\, C => \prdata_39_0_iv_4[2]\, Y => - \prdata_39_0_iv_7[2]\); - - \prdata_RNO_6[10]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[10]\, - Y => \delta_snapshot_m_i[10]\); - - \reg_sp.addr_matrix_f1[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[24]\); - - \prdata_RNO_7[6]\ : AND2 - port map(A => \prdata_39_0_iv_4[6]\, B => - \prdata_39_0_iv_3[6]\, Y => \prdata_39_0_iv_6[6]\); - - \reg_wp.data_shaping_BW_1_sqmuxa_0_a2\ : NOR2B - port map(A => N_163, B => N_162, Y => - data_shaping_BW_1_sqmuxa); - - \reg_wp.addr_data_f3[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[31]\); - - \reg_wp.addr_data_f2[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[18]\); - - \prdata_RNO[5]\ : OR3C - port map(A => \prdata_39_0_iv_11[5]\, B => - \prdata_39_0_iv_10[5]\, C => \prdata_39_0_iv_12[5]\, Y - => \prdata_39[5]\); - - \prdata_RNO_3[14]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[14]\, C => \addr_matrix_f0_1_m_i[14]\, - Y => \prdata_39_0_iv_1[14]\); - - \reg_wp.status_full[2]\ : DFN1C0 - port map(D => N_47, CLK => lclk_c, CLR => rstn, Q => - \status_full[2]\); - - \prdata_RNO_0[23]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[23]\, C - => \addr_data_f2_m_i[23]\, Y => \prdata_39_0_iv_3[23]\); - - \reg_wp.status_full_RNO[0]\ : MX2 - port map(A => pwdata_0(0), B => \status_full_5_i_a2_0[0]\, - S => N_74, Y => N_43); - - \prdata_RNO_7[18]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[18]\, - Y => \addr_matrix_f0_1_m_i[18]\); - - \prdata_RNO_13[9]\ : AOI1B - port map(A => \nb_burst_available[9]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[9]\, Y => - \prdata_39_0_iv_1[9]\); - - \reg_wp.addr_data_f1[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[2]\); - - \reg_sp.addr_matrix_f2[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[6]\); - - \prdata_RNO_0[17]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[17]\, - C => \addr_data_f2_m_i[17]\, Y => \prdata_39_0_iv_3[17]\); - - \reg_wp.addr_data_f1[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[3]\); - - \prdata_RNO_0[9]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[9]\, C - => \prdata_39_0_iv_6[9]\, Y => \prdata_39_0_iv_9[9]\); - - \reg_sp.addr_matrix_f0_0[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[30]\); - - \prdata_RNO_6[28]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[28]\, Y - => \addr_data_f0_m_i[28]\); - - \reg_wp.addr_data_f2[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[3]\); - - \prdata_RNO[31]\ : OR3C - port map(A => \prdata_39_0_iv_3[31]\, B => - \addr_data_f1_m_i[31]\, C => \prdata_39_0_iv_4[31]\, Y - => \prdata_39[31]\); - - \reg_sp.addr_matrix_f0_0[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[6]\); - - \prdata_RNO_17[5]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[5]\, C - => \delta_f2_f1_m_i[5]\, Y => \prdata_39_0_iv_0[5]\); - - \prdata_RNO_10[7]\ : OR2B - port map(A => \status_full_err[3]\, B => prdata_13_sqmuxa, - Y => \status_full_err_m_i[3]\); - - \prdata_RNO_13[4]\ : NOR3C - port map(A => \nb_snapshot_param_m_i[4]\, B => - \nb_burst_available_m_i[4]\, C => \prdata_39_0_iv_2[4]\, - Y => \prdata_39_0_iv_3[4]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_0\ : NOR2A - port map(A => N_71, B => paddr(3), Y => N_162); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_159, B => N_166, C => N_69, Y => - addr_matrix_f0_1_1_sqmuxa); - - \prdata_RNO_5[19]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[19]\, - C => \addr_matrix_f2_m_i[19]\, Y => - \prdata_39_0_iv_0[19]\); - - \prdata_RNO_2[19]\ : NOR3C - port map(A => \prdata_39_0_iv_1[19]\, B => - \prdata_39_0_iv_0[19]\, C => \addr_data_f0_m_i[19]\, Y - => \prdata_39_0_iv_4[19]\); - - \prdata_RNO_3[2]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[2]\, Y - => \addr_data_f1_m_i[2]\); - - \prdata_RNO_0[7]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[7]\, C - => \prdata_39_0_iv_6[7]\, Y => \prdata_39_0_iv_9[7]\); - - \reg_wp.addr_data_f2[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[22]\); - - \reg_wp.delta_f2_f0[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[9]\); - - \prdata[17]\ : DFN1C0 - port map(D => \prdata_39[17]\, CLK => lclk_c, CLR => rstn, - Q => prdata(17)); - - \reg_wp.addr_data_f0[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[30]\); - - \prdata_RNO_7[31]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[31]\, - Y => \addr_matrix_f0_1_m_i[31]\); - - \prdata_RNO_8[2]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[2]\, Y - => \addr_data_f3_m_i[2]\); - - \reg_wp.status_full_err[2]\ : DFN1C0 - port map(D => N_55, CLK => lclk_c, CLR => rstn, Q => - \status_full_err[2]\); - - \prdata_RNO_11[2]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f2\, Y => - enable_f2_m_i); - - \prdata_RNO_8[14]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[14]\, Y => \addr_matrix_f0_1_m_i[14]\); - - \reg_sp.addr_matrix_f2[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[31]\); - - \prdata_RNO_15[2]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[2]\, C => N_232_0, - Y => \addr_data_f2_m_i[2]\); - - \prdata[18]\ : DFN1C0 - port map(D => \prdata_39[18]\, CLK => lclk_c, CLR => rstn, - Q => prdata(18)); - - \reg_sp.addr_matrix_f2[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[30]\); - - \reg_wp.addr_data_f2[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[7]\); - - \prdata_RNO[13]\ : OR3C - port map(A => \prdata_39_0_iv_4[13]\, B => - \prdata_39_0_iv_3[13]\, C => \prdata_39_0_iv_5[13]\, Y - => \prdata_39[13]\); - - \reg_wp.data_shaping_R0_0\ : DFN1E1C0 - port map(D => pwdata_0(3), CLK => lclk_c, CLR => rstn, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_R0_0\); - - \reg_sp.addr_matrix_f1[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[2]\); - - \reg_sp.addr_matrix_f1[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[18]\); - - \prdata_RNO_9[3]\ : AOI1B - port map(A => \status_full[3]\, B => prdata_13_sqmuxa, C - => \addr_data_f2_m_i[3]\, Y => \prdata_39_0_iv_9[3]\); - - \prdata_RNO_21[0]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f0\, Y => - enable_f0_m_i); - - \prdata_RNO_15[9]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[9]\, Y - => \addr_matrix_f1_m_i[9]\); - - \prdata_RNO_0[31]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[31]\, C - => \addr_data_f2_m_i[31]\, Y => \prdata_39_0_iv_3[31]\); - - \prdata_RNO_0[3]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[3]\, C - => \addr_data_f1_m_i[3]\, Y => \prdata_39_0_iv_12[3]\); - - \prdata_RNO[3]\ : OR3C - port map(A => \prdata_39_0_iv_12[3]\, B => - \prdata_39_0_iv_11[3]\, C => \prdata_39_0_iv_13[3]\, Y - => \prdata_39[3]\); - - \reg_wp.enable_f2\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \enable_f2\); - - \reg_wp.addr_data_f0[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[6]\); - - \reg_wp.addr_data_f0[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[31]\); - - \prdata_RNO[6]\ : OR3C - port map(A => \prdata_39_0_iv_10[6]\, B => - \prdata_39_0_iv_9[6]\, C => \prdata_39_0_iv_11[6]\, Y => - \prdata_39[6]\); - - \reg_wp.status_new_err_RNO_0[1]\ : OR2 - port map(A => \status_new_err[1]\, B => status_new_err_0(1), - Y => \status_new_err_5_i_a2_0[1]\); - - \reg_wp.addr_data_f3[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[9]\); - - \reg_wp.status_new_err[1]\ : DFN1C0 - port map(D => N_61, CLK => lclk_c, CLR => rstn, Q => - \status_new_err[1]\); - - \prdata_RNO_10[5]\ : NOR2B - port map(A => status_error_bad_component_error_m_i, B => - \prdata_39_0_iv_0[5]\, Y => \prdata_39_0_iv_2[5]\); - - \prdata_RNO_16[7]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[7]\, Y - => \delta_f2_f1_m_i[7]\); - - \prdata_RNO_1[1]\ : AOI1B - port map(A => \status_full[1]\, B => prdata_13_sqmuxa, C - => \addr_data_f2_m_i[1]\, Y => \prdata_39_0_iv_10[1]\); - - \reg_wp.status_full_RNO_0[1]\ : OR2 - port map(A => \status_full[1]\, B => status_full_0(1), Y - => \status_full_5_i_a2_0[1]\); - - \prdata_RNO_14[6]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f2\, Y => - burst_f2_m_i); - - \prdata_RNO_1[21]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[21]\, Y - => \addr_data_f1_m_i[21]\); - - \prdata_RNO_1[26]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[26]\, Y - => \addr_data_f1_m_i[26]\); - - \prdata_RNO_1[15]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[15]\, - C => \addr_data_f2_m_i[15]\, Y => \prdata_39_0_iv_3[15]\); - - \prdata_RNO_14[2]\ : NOR2B - port map(A => data_shaping_SP1_m_i, B => - \addr_matrix_f1_m_i[2]\, Y => \prdata_39_0_iv_4[2]\); - - \prdata_RNO_7[17]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[17]\, - Y => \addr_matrix_f0_1_m_i[17]\); - - \prdata_RNO_13[1]\ : AOI1B - port map(A => \nb_snapshot_param[1]\, B => prdata_18_sqmuxa, - C => status_ready_matrix_f0_1_m_i, Y => - \prdata_39_0_iv_2[1]\); - - \reg_sp.addr_matrix_f0_1[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[26]\); - - \prdata_RNO_9[10]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[10]\, - Y => \addr_matrix_f2_m_i[10]\); - - \prdata_RNO_3[13]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[13]\, C => \addr_matrix_f0_1_m_i[13]\, - Y => \prdata_39_0_iv_1[13]\); - - \prdata_RNO_7[20]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[20]\, - Y => \addr_matrix_f0_1_m_i[20]\); - - \status_full_ack_RNO[1]\ : NOR3A - port map(A => \status_full[1]\, B => pwdata_0(1), C => N_74, - Y => \status_full_ack_8[1]\); - - \reg_wp.addr_data_f1[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[9]\); - - \reg_wp.addr_data_f0[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[27]\); - - \prdata_RNO_17[0]\ : OR2B - port map(A => \nb_burst_available[0]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[0]\); - - \reg_wp.delta_snapshot[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[3]\); - - \prdata_RNO_4[19]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[19]\, - C => \addr_matrix_f0_1_m_i[19]\, Y => - \prdata_39_0_iv_1[19]\); - - \prdata_RNO[14]\ : OR3C - port map(A => \prdata_39_0_iv_4[14]\, B => - \prdata_39_0_iv_3[14]\, C => \prdata_39_0_iv_5[14]\, Y - => \prdata_39[14]\); - - \reg_wp.status_full_err_RNO_0[3]\ : OR2 - port map(A => \status_full_err[3]\, B => - status_full_err_0(3), Y => \status_full_err_5_i_a2_0[3]\); - - \prdata_RNO_2[30]\ : NOR3C - port map(A => \prdata_39_0_iv_1[30]\, B => - \prdata_39_0_iv_0[30]\, C => \addr_data_f0_m_i[30]\, Y - => \prdata_39_0_iv_4[30]\); - - \reg_sp.addr_matrix_f1[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[1]\); - - \prdata_RNO_6[27]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[27]\, Y - => \addr_data_f0_m_i[27]\); - - \prdata_RNO_3[30]\ : OR3B - port map(A => N_168, B => \addr_data_f2[30]\, C => N_232, Y - => \addr_data_f2_m_i[30]\); - - \prdata_RNO_6[7]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[7]\, Y - => \delta_snapshot_m_i[7]\); - - \reg_sp.addr_matrix_f0_0[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[11]\); - - \reg_wp.addr_data_f3[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[14]\); - - \prdata_RNO_1[22]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[22]\, Y - => \addr_data_f1_m_i[22]\); - - \prdata_RNO_18[8]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[8]\, Y - => \delta_f2_f0_m_i[8]\); - - \prdata_RNO[28]\ : OR3C - port map(A => \prdata_39_0_iv_3[28]\, B => - \addr_data_f1_m_i[28]\, C => \prdata_39_0_iv_4[28]\, Y - => \prdata_39[28]\); - - \prdata_RNO_4[20]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[20]\, C => \addr_matrix_f0_1_m_i[20]\, - Y => \prdata_39_0_iv_1[20]\); - - \status_full_ack_RNO[3]\ : NOR3A - port map(A => \status_full[3]\, B => pwdata_1_2, C => N_74, - Y => \status_full_ack_8[3]\); - - \reg_wp.nb_burst_available_1_sqmuxa_0_a2_1\ : NOR2A - port map(A => paddr_0(3), B => rdata61_2, Y => N_159); - - \reg_wp.addr_data_f2[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[8]\); - - \prdata_RNO_14[8]\ : AOI1B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[8]\, C - => \delta_f2_f0_m_i[8]\, Y => \prdata_39_0_iv_0[8]\); - - \prdata_RNO_13[7]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[7]\, Y - => \addr_matrix_f1_m_i[7]\); - - \reg_wp.delta_f2_f1[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[5]\); - - \prdata_RNO_19[5]\ : OR2B - port map(A => \nb_snapshot_param[5]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[5]\); - - \reg_wp.nb_snapshot_param[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[5]\); - - \reg_wp.addr_data_f2[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[19]\); - - \prdata_RNO_1[18]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[18]\, Y - => \addr_data_f1_m_i[18]\); - - \reg_wp.addr_data_f0[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[17]\); - - \prdata_RNO_14[4]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[4]\, Y - => \addr_data_f3_m_i[4]\); - - \prdata_RNO_5[15]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[15]\, C => - N_232_1, Y => \addr_data_f2_m_i[15]\); - - \reg_wp.status_full_err_RNO_0[2]\ : OR2 - port map(A => \status_full_err[2]\, B => - status_full_err_0(2), Y => \status_full_err_5_i_a2_0[2]\); - - \prdata_RNO_6[2]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[2]\, Y - => \delta_snapshot_m_i[2]\); - - \prdata_RNO_2[15]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[15]\, C - => \addr_data_f1_m_i[15]\, Y => \prdata_39_0_iv_5[15]\); - - \prdata_RNO_8[13]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[13]\, Y => \addr_matrix_f0_1_m_i[13]\); - - \reg_wp.addr_data_f3[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[18]\); - - prdata_5_sqmuxa_0_a2_0 : NOR3 - port map(A => N_69, B => addr_matrix_f1_1_sqmuxa_0_a2_1_0, - C => N_6455_0, Y => prdata_5_sqmuxa_0); - - \prdata_RNO_4[2]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[2]\, - C => \addr_matrix_f0_1_m_i[2]\, Y => - \prdata_39_0_iv_6[2]\); - - \prdata_RNO_2[29]\ : NOR3C - port map(A => \prdata_39_0_iv_1[29]\, B => - \prdata_39_0_iv_0[29]\, C => \addr_data_f0_m_i[29]\, Y - => \prdata_39_0_iv_4[29]\); - - \prdata_RNO_0[20]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[20]\, - C => \addr_data_f2_m_i[20]\, Y => \prdata_39_0_iv_3[20]\); - - \reg_sp.addr_matrix_f2[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[16]\); - - \reg_wp.delta_f2_f1[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[0]\); - - \prdata_RNO_15[0]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[0]\, - C => enable_f0_m_i, Y => \prdata_39_0_iv_6[0]\); - - \reg_wp.status_new_err_RNO[1]\ : MX2 - port map(A => pwdata_0(9), B => - \status_new_err_5_i_a2_0[1]\, S => N_74, Y => N_61); - - \prdata_RNO_1[6]\ : AND2 - port map(A => \delta_snapshot_m_i[6]\, B => - \prdata_39_0_iv_6[6]\, Y => \prdata_39_0_iv_9[6]\); - - \reg_sp.addr_matrix_f2[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[11]\); - - \reg_sp.addr_matrix_f2[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[10]\); - - \reg_sp.addr_matrix_f0_0[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[18]\); - - \prdata_RNO_20[3]\ : OR2B - port map(A => prdata_7_sqmuxa, B => \data_shaping_R0_0\, Y - => data_shaping_R0_m_i); - - \reg_sp.addr_matrix_f0_0[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[29]\); - - \prdata_RNO_10[8]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[8]\, - Y => \addr_matrix_f0_0_m_i[8]\); - - \prdata_RNO_3[7]\ : NOR3C - port map(A => \addr_matrix_f0_0_m_i[7]\, B => - \addr_matrix_f2_m_i[7]\, C => \status_full_err_m_i[3]\, Y - => \prdata_39_0_iv_6[7]\); - - \reg_wp.delta_f2_f1[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[4]\); - - \reg_sp.addr_matrix_f0_1[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[20]\); - - \prdata_RNO_4[30]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[30]\, C => \addr_matrix_f0_1_m_i[30]\, - Y => \prdata_39_0_iv_1[30]\); - - \reg_sp.addr_matrix_f2[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[26]\); - - \reg_sp.addr_matrix_f0_1[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[23]\); - - \prdata_RNO_5[18]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[18]\, - C => \addr_matrix_f2_m_i[18]\, Y => - \prdata_39_0_iv_0[18]\); - - \reg_wp.delta_snapshot[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[15]\); - - \prdata_RNO_2[18]\ : NOR3C - port map(A => \prdata_39_0_iv_1[18]\, B => - \prdata_39_0_iv_0[18]\, C => \addr_data_f0_m_i[18]\, Y - => \prdata_39_0_iv_4[18]\); - - \reg_wp.data_shaping_R1\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => data_shaping_R1); - - \prdata_RNO_12[6]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[6]\, - C => burst_f2_m_i, Y => \prdata_39_0_iv_4[6]\); - - \reg_sp.addr_matrix_f0_1[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[12]\); - - \reg_wp.delta_snapshot[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[0]\); - - \reg_sp.addr_matrix_f2[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[21]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_159, B => N_71, C => N_69, Y => - addr_matrix_f0_0_1_sqmuxa); - - \prdata_RNO_0[0]\ : NOR3C - port map(A => \prdata_39_0_iv_5[0]\, B => - \prdata_39_0_iv_4[0]\, C => \addr_data_f3_m_i[0]\, Y => - \prdata_39_0_iv_11[0]\); - - \prdata_RNO_8[1]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[1]\, Y - => \addr_data_f0_m_i[1]\); - - \reg_wp.enable_f3\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \enable_f3\); - - \prdata[24]\ : DFN1C0 - port map(D => \prdata_39[24]\, CLK => lclk_c, CLR => rstn, - Q => prdata(24)); - - \prdata_RNO[22]\ : OR3C - port map(A => \prdata_39_0_iv_3[22]\, B => - \addr_data_f1_m_i[22]\, C => \prdata_39_0_iv_4[22]\, Y - => \prdata_39[22]\); - - \apbo.pirq_RNO_6[15]\ : NOR2 - port map(A => status_full_0(2), B => status_full_0(3), Y - => \pirq_2_i_a2_5[15]\); - - \reg_sp.addr_matrix_f2[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[20]\); - - \prdata_RNO_4[15]\ : NAND2 - port map(A => \delta_snapshot[15]\, B => prdata_14_sqmuxa, - Y => \delta_snapshot_m_i[15]\); - - \prdata_RNO_18[0]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[0]\, Y - => \delta_f2_f0_m_i[0]\); - - \prdata_RNO_13[2]\ : AOI1B - port map(A => \nb_burst_available[2]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[2]\, Y => - \prdata_39_0_iv_1[2]\); - - \prdata_RNO_8[8]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[8]\, C => N_232_1, - Y => \addr_data_f2_m_i[8]\); - - \prdata_RNO_8[21]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[21]\, Y - => \addr_matrix_f2_m_i[21]\); - - \prdata_RNO_8[26]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[26]\, Y - => \addr_matrix_f2_m_i[26]\); - - \prdata_RNO_1[17]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[17]\, Y - => \addr_data_f1_m_i[17]\); - - \prdata_RNO_14[9]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[9]\, C - => \delta_f2_f1_m_i[9]\, Y => \prdata_39_0_iv_0[9]\); - - \prdata_RNO[20]\ : OR3C - port map(A => \prdata_39_0_iv_3[20]\, B => - \addr_data_f1_m_i[20]\, C => \prdata_39_0_iv_4[20]\, Y - => \prdata_39[20]\); - - \prdata_RNO_15[5]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[5]\, C => N_232_1, - Y => \addr_data_f2_m_i[5]\); - - \prdata_RNO_12[3]\ : NOR3C - port map(A => \delta_f2_f1_m_i[3]\, B => - \delta_f2_f0_m_i[3]\, C => status_ready_matrix_f2_m_i, Y - => \prdata_39_0_iv_2[3]\); - - \reg_sp.addr_matrix_f0_1[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[31]\); - - \prdata_RNO_5[24]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[24]\, - C => \addr_matrix_f2_m_i[24]\, Y => - \prdata_39_0_iv_0[24]\); - - \reg_sp.addr_matrix_f1[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[5]\); - - prdata_15_sqmuxa_0_a2 : NOR3A - port map(A => N_158, B => rdata61_2, C => N_232, Y => - prdata_15_sqmuxa); - - \reg_wp.delta_snapshot[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[12]\); - - \prdata_RNO_19[1]\ : OR2B - port map(A => status_ready_matrix_f0_1, B => - prdata_1_sqmuxa, Y => status_ready_matrix_f0_1_m_i); - - \reg_wp.status_new_err_RNO_0[2]\ : OR2 - port map(A => \status_new_err[2]\, B => status_new_err_0(2), - Y => \status_new_err_5_i_a2_0[2]\); - - \prdata_RNO_6[11]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[11]\, - Y => \delta_snapshot_m_i[11]\); - - \prdata_RNO_6[16]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[16]\, Y - => \addr_data_f0_m_i[16]\); - - \prdata_RNO_3[10]\ : NOR3C - port map(A => \addr_matrix_f0_0_m_i[10]\, B => - \addr_matrix_f2_m_i[10]\, C => \status_new_err_m_i[2]\, Y - => \prdata_39_0_iv_4[10]\); - - \prdata_RNO_14[5]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[5]\, - Y => \addr_matrix_f2_m_i[5]\); - - \prdata_RNO_19[6]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[6]\, Y - => \delta_f2_f1_m_i[6]\); - - \prdata_RNO_17[3]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[3]\, Y - => \delta_f2_f0_m_i[3]\); - - \prdata_RNO_8[22]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[22]\, Y - => \addr_matrix_f2_m_i[22]\); - - prdata_17_sqmuxa_0_a2 : NOR3B - port map(A => N_158, B => N_159, C => paddr_2(2), Y => - prdata_17_sqmuxa); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2_0_0\ : NOR3B - port map(A => N_159, B => N_166, C => N_69, Y => - addr_matrix_f0_1_1_sqmuxa_0); - - \reg_wp.addr_data_f1[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[30]\); - - \prdata_RNO_2[25]\ : NOR3C - port map(A => \prdata_39_0_iv_1[25]\, B => - \prdata_39_0_iv_0[25]\, C => \addr_data_f0_m_i[25]\, Y - => \prdata_39_0_iv_4[25]\); - - \prdata_RNO_4[18]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[18]\, C => \addr_matrix_f0_1_m_i[18]\, - Y => \prdata_39_0_iv_1[18]\); - - \reg_wp.nb_burst_available[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[2]\); - - \prdata_RNO_8[6]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[6]\, Y - => \addr_data_f3_m_i[6]\); - - \prdata_RNO_3[3]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[3]\, Y - => \addr_data_f1_m_i[3]\); - - \reg_wp.delta_snapshot[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[14]\); - - \reg_wp.delta_f2_f1[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[9]\); - - \reg_sp.addr_matrix_f2[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[14]\); - - \prdata_RNO_6[12]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[12]\, C => - N_232_1, Y => \addr_data_f2_m_i[12]\); - - \prdata_RNO_9[5]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[5]\, C - => \addr_data_f2_m_i[5]\, Y => \prdata_39_0_iv_9[5]\); - - \prdata_RNO_5[0]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[0]\, Y - => \addr_data_f3_m_i[0]\); - - \reg_wp.addr_data_f3[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[27]\); - - \prdata_RNO_5[17]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[17]\, - C => \addr_matrix_f2_m_i[17]\, Y => - \prdata_39_0_iv_0[17]\); - - \prdata_RNO_2[17]\ : NOR3C - port map(A => \prdata_39_0_iv_1[17]\, B => - \prdata_39_0_iv_0[17]\, C => \addr_data_f0_m_i[17]\, Y - => \prdata_39_0_iv_4[17]\); - - \reg_wp.nb_snapshot_param[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[10]\); - - \reg_sp.addr_matrix_f1[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[16]\); - - \reg_wp.delta_snapshot[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[11]\); - - \reg_sp.config_active_interruption_onNewMatrix\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - config_active_interruption_onError_0_sqmuxa, Q => - config_active_interruption_onNewMatrix); - - \reg_wp.addr_data_f1[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[31]\); - - \reg_wp.status_full_RNO[3]\ : MX2 - port map(A => pwdata_1_2, B => \status_full_5_i_a2_0[3]\, S - => N_74, Y => N_49); - - \prdata_RNO_3[24]\ : OR3B - port map(A => N_168, B => \addr_data_f2[24]\, C => N_232, Y - => \addr_data_f2_m_i[24]\); - - \reg_wp.addr_data_f3[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[19]\); - - \prdata_RNO_2[8]\ : NOR3C - port map(A => \addr_data_f3_m_i[8]\, B => - \addr_data_f2_m_i[8]\, C => \addr_data_f1_m_i[8]\, Y => - \prdata_39_0_iv_10[8]\); - - \reg_sp.addr_matrix_f1[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[11]\); - - \status_full_ack_RNO[2]\ : NOR3A - port map(A => \status_full[2]\, B => pwdata_0(2), C => N_74, - Y => \status_full_ack_8[2]\); - - \reg_sp.addr_matrix_f0_1[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[24]\); - - \reg_sp.addr_matrix_f0_1[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[3]\); - - \reg_sp.addr_matrix_f0_1[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[25]\); - - \prdata_RNO_8[10]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[10]\, - Y => \addr_matrix_f0_0_m_i[10]\); - - \reg_sp.addr_matrix_f1[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[10]\); - - \reg_sp.status_error_anticipating_empty_fifo_1_sqmuxa_0_a2\ : - NOR3A - port map(A => N_160, B => rdata61_2, C => N_69, Y => - status_error_anticipating_empty_fifo_1_sqmuxa); - - prdata_3_sqmuxa_0_a2 : NOR3B - port map(A => N_159, B => paddr_2(2), C => N_69, Y => - prdata_3_sqmuxa); - - \prdata_RNO_3[0]\ : AOI1B - port map(A => prdata_7_sqmuxa, B => \Bias_Fails_c\, C => - \addr_matrix_f1_m_i[0]\, Y => \prdata_39_0_iv_5[0]\); - - \prdata_RNO_2[2]\ : NOR3C - port map(A => \prdata_39_0_iv_7[2]\, B => - \addr_data_f3_m_i[2]\, C => \prdata_39_0_iv_9[2]\, Y => - \prdata_39_0_iv_13[2]\); - - \prdata_RNO_7[7]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[7]\, C - => \addr_data_f2_m_i[7]\, Y => \prdata_39_0_iv_7[7]\); - - \prdata_RNO_13[5]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[5]\, - Y => \addr_matrix_f0_0_m_i[5]\); - - \prdata_RNO_3[4]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[4]\, Y - => \addr_data_f1_m_i[4]\); - - \reg_wp.status_full_err_RNO[3]\ : MX2 - port map(A => pwdata_0(7), B => - \status_full_err_5_i_a2_0[3]\, S => N_74, Y => N_57); - - \reg_sp.addr_matrix_f2[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[7]\); - - \reg_sp.addr_matrix_f2[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[24]\); - - \reg_wp.addr_data_f1[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[24]\); - - \prdata_RNO_5[6]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[6]\, Y - => \addr_data_f0_m_i[6]\); - - \prdata_RNO_2[28]\ : NOR3C - port map(A => \prdata_39_0_iv_1[28]\, B => - \prdata_39_0_iv_0[28]\, C => \addr_data_f0_m_i[28]\, Y - => \prdata_39_0_iv_4[28]\); - - \prdata_RNO_16[4]\ : OR2B - port map(A => \nb_snapshot_param[4]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[4]\); - - \prdata_RNO[17]\ : OR3C - port map(A => \prdata_39_0_iv_3[17]\, B => - \addr_data_f1_m_i[17]\, C => \prdata_39_0_iv_4[17]\, Y - => \prdata_39[17]\); - - \reg_wp.addr_data_f0[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[23]\); - - \prdata_RNO[25]\ : OR3C - port map(A => \prdata_39_0_iv_3[25]\, B => - \addr_data_f1_m_i[25]\, C => \prdata_39_0_iv_4[25]\, Y - => \prdata_39[25]\); - - \prdata[20]\ : DFN1C0 - port map(D => \prdata_39[20]\, CLK => lclk_c, CLR => rstn, - Q => prdata(20)); - - \reg_wp.addr_data_f0[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[20]\); - - \prdata_RNO_1[4]\ : NOR3C - port map(A => \prdata_39_0_iv_6[4]\, B => - \prdata_39_0_iv_5[4]\, C => \delta_snapshot_m_i[4]\, Y - => \prdata_39_0_iv_11[4]\); - - \prdata_RNO_21[1]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f1\, Y => - enable_f1_m_i); - - \reg_wp.addr_data_f3[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[1]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \prdata_RNO_8[3]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[3]\, Y - => \addr_data_f3_m_i[3]\); - - \reg_sp.addr_matrix_f0_0[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[27]\); - - \prdata_RNO_1[29]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[29]\, Y - => \addr_data_f1_m_i[29]\); - - \prdata_RNO_5[23]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[23]\, - C => \addr_matrix_f2_m_i[23]\, Y => - \prdata_39_0_iv_0[23]\); - - \prdata_RNO_17[8]\ : OR2B - port map(A => \nb_snapshot_param[8]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[8]\); - - \prdata_RNO_10[6]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[6]\, Y - => \addr_data_f1_m_i[6]\); - - \prdata_RNO_0[14]\ : NOR3C - port map(A => \prdata_39_0_iv_1[14]\, B => - \prdata_39_0_iv_0[14]\, C => \delta_snapshot_m_i[14]\, Y - => \prdata_39_0_iv_4[14]\); - - prdata_14_sqmuxa_0_a2 : NOR3B - port map(A => paddr(4), B => paddr_2(2), C => N_72, Y => - prdata_14_sqmuxa); - - \reg_wp.addr_data_f1[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[28]\); - - \reg_wp.delta_snapshot[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[13]\); - - \prdata_RNO_8[7]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[7]\, - Y => \addr_matrix_f0_0_m_i[7]\); - - \reg_wp.addr_data_f0[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[21]\); - - prdata_3_sqmuxa_0_a2_0 : NOR3B - port map(A => N_159, B => paddr_0(2), C => N_69, Y => - prdata_3_sqmuxa_0); - - \prdata[23]\ : DFN1C0 - port map(D => \prdata_39[23]\, CLK => lclk_c, CLR => rstn, - Q => prdata(23)); - - \prdata_RNO_4[17]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[17]\, C => \addr_matrix_f0_1_m_i[17]\, - Y => \prdata_39_0_iv_1[17]\); - - \reg_wp.delta_f2_f0[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[6]\); - - \prdata_RNO_9[11]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[11]\, - Y => \addr_data_f1_m_i[11]\); - - \prdata_RNO_7[21]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[21]\, - Y => \addr_matrix_f0_1_m_i[21]\); - - \prdata_RNO_7[26]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[26]\, - Y => \addr_matrix_f0_1_m_i[26]\); - - \prdata_RNO[9]\ : OR3C - port map(A => \prdata_39_0_iv_9[9]\, B => - \prdata_39_0_iv_8[9]\, C => \prdata_39_0_iv_10[9]\, Y => - \prdata_39[9]\); - - \reg_wp.addr_data_f0[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[13]\); - - \prdata_RNO_20[2]\ : NAND2 - port map(A => \delta_f2_f1[2]\, B => prdata_15_sqmuxa, Y - => \delta_f2_f1_m_i[2]\); - - \prdata_RNO_12[7]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[7]\, C - => \delta_f2_f1_m_i[7]\, Y => \prdata_39_0_iv_0[7]\); - - \reg_wp.addr_data_f0[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[10]\); - - \prdata_RNO_2[31]\ : NOR3C - port map(A => \prdata_39_0_iv_1[31]\, B => - \prdata_39_0_iv_0[31]\, C => \addr_data_f0_m_i[31]\, Y - => \prdata_39_0_iv_4[31]\); - - \prdata_RNO_13[3]\ : AOI1B - port map(A => \nb_burst_available[3]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[3]\, Y => - \prdata_39_0_iv_1[3]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_o2_0\ : - NOR3B - port map(A => N_116, B => N_769, C => - config_active_interruption_onError_0_sqmuxa_0_o2_0_0, Y - => N_68); - - \prdata_RNO_14[3]\ : NOR2B - port map(A => data_shaping_R0_m_i, B => - \addr_matrix_f1_m_i[3]\, Y => \prdata_39_0_iv_4[3]\); - - \prdata_RNO_3[31]\ : OR3B - port map(A => N_168, B => \addr_data_f2[31]\, C => N_232, Y - => \addr_data_f2_m_i[31]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0\ : NOR3B - port map(A => paddr(5), B => paddr(4), C => N_69, Y => - N_168); - - \prdata_RNO_5[5]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[5]\, Y - => \addr_data_f0_m_i[5]\); - - \reg_wp.addr_data_f1[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[14]\); - - \reg_sp.addr_matrix_f2[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[1]\); - - \reg_wp.delta_snapshot[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[9]\); - - \prdata[30]\ : DFN1C0 - port map(D => \prdata_39[30]\, CLK => lclk_c, CLR => rstn, - Q => prdata(30)); - - \prdata_RNO_13[8]\ : NOR2B - port map(A => \nb_burst_available_m_i[8]\, B => - \nb_snapshot_param_m_i[8]\, Y => \prdata_39_0_iv_1[8]\); - - \reg_wp.status_new_err[3]\ : DFN1C0 - port map(D => N_65, CLK => lclk_c, CLR => rstn, Q => - \status_new_err[3]\); - - \reg_wp.addr_data_f1[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[0]\); - - \prdata_RNO_12[2]\ : AOI1B - port map(A => status_ready_matrix_f1, B => prdata_1_sqmuxa, - C => \prdata_39_0_iv_0[2]\, Y => \prdata_39_0_iv_2[2]\); - - \reg_wp.delta_f2_f0[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[4]\); - - \prdata_RNO_12[1]\ : AOI1B - port map(A => prdata_0_sqmuxa, B => - config_active_interruption_onError, C => - \delta_f2_f0_m_i[1]\, Y => \prdata_39_0_iv_0[1]\); - - \prdata[11]\ : DFN1C0 - port map(D => \prdata_39[11]\, CLK => lclk_c, CLR => rstn, - Q => prdata(11)); - - \reg_sp.addr_matrix_f0_0[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[19]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0_0\ : NOR3B - port map(A => paddr(5), B => paddr_0(4), C => N_69, Y => - N_168_0); - - \reg_wp.addr_data_f0[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[11]\); - - \prdata_RNO_4[21]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[21]\, - C => \addr_matrix_f0_1_m_i[21]\, Y => - \prdata_39_0_iv_1[21]\); - - \prdata_RNO_4[26]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[26]\, - C => \addr_matrix_f0_1_m_i[26]\, Y => - \prdata_39_0_iv_1[26]\); - - \prdata_RNO_9[12]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[12]\, - Y => \addr_matrix_f2_m_i[12]\); - - \prdata_RNO_3[23]\ : OR3B - port map(A => N_168, B => \addr_data_f2[23]\, C => N_232, Y - => \addr_data_f2_m_i[23]\); - - \prdata_RNO_7[22]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[22]\, - Y => \addr_matrix_f0_1_m_i[22]\); - - \reg_sp.addr_matrix_f0_1[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[5]\); - - \reg_wp.addr_data_f1[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[18]\); - - \prdata_RNO_2[27]\ : NOR3C - port map(A => \prdata_39_0_iv_1[27]\, B => - \prdata_39_0_iv_0[27]\, C => \addr_data_f0_m_i[27]\, Y - => \prdata_39_0_iv_4[27]\); - - \prdata_RNO_9[0]\ : NOR3C - port map(A => \prdata_39_0_iv_7[0]\, B => - \prdata_39_0_iv_6[0]\, C => \delta_snapshot_m_i[0]\, Y - => \prdata_39_0_iv_12[0]\); - - \reg_sp.status_ready_matrix_f0_1\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f0_1); - - \reg_sp.addr_matrix_f1[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[14]\); - - \prdata_RNO_5[8]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[8]\, - Y => \addr_matrix_f0_1_m_i[8]\); - - \prdata_RNO[30]\ : OR3C - port map(A => \prdata_39_0_iv_3[30]\, B => - \addr_data_f1_m_i[30]\, C => \prdata_39_0_iv_4[30]\, Y - => \prdata_39[30]\); - - \apbo.pirq_RNO_2[15]\ : NOR3A - port map(A => \pirq_2_i_a2_5[15]\, B => status_full_0(1), C - => status_full_0(0), Y => \pirq_2_i_a2_8[15]\); - - \prdata_RNO_0[21]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[21]\, - C => \addr_data_f2_m_i[21]\, Y => \prdata_39_0_iv_3[21]\); - - \reg_sp.addr_matrix_f0_1[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[11]\); - - \prdata_RNO_7[14]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[14]\, - Y => \addr_data_f1_m_i[14]\); - - \prdata_RNO_11[0]\ : AOI1B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[0]\, C - => \nb_burst_available_m_i[0]\, Y => - \prdata_39_0_iv_1[0]\); - - \prdata_RNO_0[26]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[26]\, C - => \addr_data_f2_m_i[26]\, Y => \prdata_39_0_iv_3[26]\); - - \prdata_RNO_4[8]\ : NOR3C - port map(A => \prdata_39_0_iv_1[8]\, B => - \prdata_39_0_iv_0[8]\, C => \addr_matrix_f1_m_i[8]\, Y - => \prdata_39_0_iv_3[8]\); - - \reg_sp.addr_matrix_f0_0[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[5]\); - - prdata_12_sqmuxa_0_a2 : NOR2A - port map(A => N_168, B => N_6455, Y => prdata_12_sqmuxa); - - \prdata_RNO_21[3]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[3]\, Y - => \addr_matrix_f1_m_i[3]\); - - \prdata_RNO_4[22]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[22]\, - C => \addr_matrix_f0_1_m_i[22]\, Y => - \prdata_39_0_iv_1[22]\); - - \reg_wp.addr_data_f0[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[9]\); - - prdata_5_sqmuxa_0_a2 : NOR3 - port map(A => N_69, B => addr_matrix_f1_1_sqmuxa_0_a2_1_0, - C => N_6455, Y => prdata_5_sqmuxa); - - \reg_wp.addr_data_f2[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[2]\); - - \prdata_RNO_6[30]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[30]\, Y - => \addr_data_f0_m_i[30]\); - - \prdata_RNO_6[24]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[24]\, Y - => \addr_data_f0_m_i[24]\); - - \reg_wp.addr_data_f0[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[25]\); - - \reg_sp.addr_matrix_f0_0[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[7]\); - - \prdata_RNO_17[2]\ : OR2B - port map(A => \nb_snapshot_param[2]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[2]\); - - \prdata_RNO_0[13]\ : NOR3C - port map(A => \prdata_39_0_iv_1[13]\, B => - \prdata_39_0_iv_0[13]\, C => \delta_snapshot_m_i[13]\, Y - => \prdata_39_0_iv_4[13]\); - - \reg_wp.nb_snapshot_param[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[8]\); - - \reg_wp.addr_data_f0[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[26]\); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_160, B => N_69, C => - addr_matrix_f1_1_sqmuxa_0_a2_1_0, Y => - addr_matrix_f2_1_sqmuxa); - - \reg_wp.delta_snapshot_1_sqmuxa_0_a2\ : NOR3B - port map(A => paddr_0(4), B => N_166, C => N_72, Y => - delta_snapshot_1_sqmuxa); - - \reg_sp.addr_matrix_f0_1[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[6]\); - - \prdata_RNO_1[25]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[25]\, Y - => \addr_data_f1_m_i[25]\); - - \reg_wp.addr_data_f1_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_166, B => paddr_0(4), C => N_72, Y => - addr_data_f1_1_sqmuxa_0); - - \prdata_RNO_15[1]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[1]\, - C => enable_f1_m_i, Y => \prdata_39_0_iv_6[1]\); - - \reg_wp.addr_data_f2[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[17]\); - - \prdata_RNO[11]\ : OR3C - port map(A => \prdata_39_0_iv_5[11]\, B => - \prdata_39_0_iv_4[11]\, C => \prdata_39_0_iv_6[11]\, Y - => \prdata_39[11]\); - - \prdata[25]\ : DFN1C0 - port map(D => \prdata_39[25]\, CLK => lclk_c, CLR => rstn, - Q => prdata(25)); - - \prdata_RNO_1[8]\ : NOR3C - port map(A => \prdata_39_0_iv_3[8]\, B => - \addr_matrix_f0_1_m_i[8]\, C => \delta_snapshot_m_i[8]\, - Y => \prdata_39_0_iv_8[8]\); - - \prdata_RNO_0[22]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[22]\, - C => \addr_data_f2_m_i[22]\, Y => \prdata_39_0_iv_3[22]\); - - \prdata_RNO_4[31]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[31]\, - C => \addr_matrix_f0_1_m_i[31]\, Y => - \prdata_39_0_iv_1[31]\); - - \reg_wp.addr_data_f2[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[24]\); - - \reg_wp.status_full_err_RNO_0[1]\ : OR2 - port map(A => \status_full_err[1]\, B => - status_full_err_0(1), Y => \status_full_err_5_i_a2_0[1]\); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2_0\ : NOR2 - port map(A => un1_apbi_0, B => N_6455, Y => N_160); - - \reg_sp.addr_matrix_f2[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[8]\); - - \prdata_RNO_8[9]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[9]\, C => N_232_1, - Y => \addr_data_f2_m_i[9]\); - - \status_full_ack[3]\ : DFN1C0 - port map(D => \status_full_ack_8[3]\, CLK => lclk_c, CLR - => rstn, Q => status_full_ack(3)); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_158, B => N_160, C => rdata61_2, Y => - delta_f2_f0_1_sqmuxa); - - \prdata_RNO[29]\ : OR3C - port map(A => \prdata_39_0_iv_3[29]\, B => - \addr_data_f1_m_i[29]\, C => \prdata_39_0_iv_4[29]\, Y - => \prdata_39[29]\); - - \prdata_RNO_14[0]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[0]\, - C => \addr_matrix_f0_1_m_i[0]\, Y => - \prdata_39_0_iv_7[0]\); - - \prdata_RNO_6[5]\ : AOI1B - port map(A => prdata_8_sqmuxa, B => \burst_f1\, C => - \addr_matrix_f0_0_m_i[5]\, Y => \prdata_39_0_iv_5[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \prdata_RNO_8[29]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[29]\, Y - => \addr_matrix_f2_m_i[29]\); - - \reg_wp.status_full[0]\ : DFN1C0 - port map(D => N_43, CLK => lclk_c, CLR => rstn, Q => - \status_full[0]\); - - \reg_sp.addr_matrix_f0_1[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[18]\); - - \prdata_RNO[16]\ : OR3C - port map(A => \prdata_39_0_iv_3[16]\, B => - \addr_data_f1_m_i[16]\, C => \prdata_39_0_iv_4[16]\, Y - => \prdata_39[16]\); - - \prdata[0]\ : DFN1C0 - port map(D => \prdata_39[0]\, CLK => lclk_c, CLR => rstn, Q - => prdata(0)); - - \apbo.pirq_RNO_5[15]\ : NOR2 - port map(A => status_new_err_0(2), B => status_new_err_0(3), - Y => \pirq_2_i_a2_1[15]\); - - \reg_wp.addr_data_f0_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_71, B => paddr_0(4), C => N_72, Y => - addr_data_f0_1_sqmuxa_0); - - \reg_wp.addr_data_f0[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[15]\); - - prdata_9_sqmuxa_0_a2_0 : NOR3 - port map(A => paddr_0(4), B => N_72, C => paddr_0(2), Y => - prdata_9_sqmuxa_0); - - \reg_wp.addr_data_f3[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[6]\); - - \reg_wp.addr_data_f2[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[28]\); - - \reg_wp.addr_data_f0[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[16]\); - - \reg_wp.status_full_err[1]\ : DFN1C0 - port map(D => N_53, CLK => lclk_c, CLR => rstn, Q => - \status_full_err[1]\); - - \reg_wp.nb_burst_available[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[10]\); - - \reg_wp.nb_snapshot_param[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[1]\); - - \reg_wp.addr_data_f1[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[29]\); - - \reg_sp.addr_matrix_f0_0[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[26]\); - - \prdata_RNO_7[4]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[4]\, C => N_232_1, - Y => \addr_data_f2_m_i[4]\); - - \prdata_RNO_5[20]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[20]\, - C => \addr_matrix_f2_m_i[20]\, Y => - \prdata_39_0_iv_0[20]\); - - \prdata_RNO_6[19]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[19]\, Y - => \addr_data_f0_m_i[19]\); - - \reg_wp.delta_f2_f1_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_158, B => N_162, C => rdata61_2, Y => - delta_f2_f1_1_sqmuxa); - - \reg_wp.addr_data_f2[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[5]\); - - \reg_sp.addr_matrix_f1[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[3]\); - - \prdata_RNO_1[28]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[28]\, Y - => \addr_data_f1_m_i[28]\); - - \reg_sp.addr_matrix_f1[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[25]\); - - \prdata_RNO_16[0]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[0]\, Y - => \delta_snapshot_m_i[0]\); - - \reg_wp.addr_data_f3[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[23]\); - - \reg_wp.addr_data_f3[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[20]\); - - \reg_wp.nb_burst_available[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[0]\); - - \prdata_RNO_3[11]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[11]\, C => \addr_matrix_f0_1_m_i[11]\, - Y => \prdata_39_0_iv_1[11]\); - - \prdata_RNO_3[16]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[16]\, C => - N_232_1, Y => \addr_data_f2_m_i[16]\); - - \reg_wp.addr_data_f3[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[4]\); - - \reg_sp.addr_matrix_f1[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[22]\); - - \prdata_RNO_4[4]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[4]\, - C => \addr_matrix_f0_1_m_i[4]\, Y => - \prdata_39_0_iv_6[4]\); - - \prdata_RNO_7[13]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[13]\, - Y => \addr_data_f1_m_i[13]\); - - \prdata[9]\ : DFN1C0 - port map(D => \prdata_39[9]\, CLK => lclk_c, CLR => rstn, Q - => prdata(9)); - - \prdata[8]\ : DFN1C0 - port map(D => \prdata_39[8]\, CLK => lclk_c, CLR => rstn, Q - => prdata(8)); - - \prdata_RNO_10[3]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[3]\, - Y => \addr_matrix_f0_1_m_i[3]\); - - \reg_sp.addr_matrix_f1[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[27]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg_wp.addr_data_f3[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[21]\); - - \prdata_RNO_6[23]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[23]\, Y - => \addr_data_f0_m_i[23]\); - - \prdata_RNO_18[5]\ : OR2B - port map(A => \nb_burst_available[5]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[5]\); - - \reg_wp.addr_data_f0[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[22]\); - - \prdata[22]\ : DFN1C0 - port map(D => \prdata_39[22]\, CLK => lclk_c, CLR => rstn, - Q => prdata(22)); - - \prdata_RNO_5[3]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[3]\, - C => enable_f3_m_i, Y => \prdata_39_0_iv_5[3]\); - - \prdata_RNO_11[5]\ : NOR2B - port map(A => \nb_burst_available_m_i[5]\, B => - \nb_snapshot_param_m_i[5]\, Y => \prdata_39_0_iv_1[5]\); - - \reg_sp.addr_matrix_f0_0[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[17]\); - - prdata_10_sqmuxa_0_a2 : NOR3A - port map(A => paddr_2(2), B => paddr_0(4), C => N_72, Y => - prdata_10_sqmuxa); - - \prdata[29]\ : DFN1C0 - port map(D => \prdata_39[29]\, CLK => lclk_c, CLR => rstn, - Q => prdata(29)); - - \prdata_RNO_4[6]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[6]\, - C => \addr_matrix_f0_1_m_i[6]\, Y => - \prdata_39_0_iv_5[6]\); - - \reg_wp.nb_snapshot_param[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[4]\); - - \reg_wp.nb_snapshot_param[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[7]\); - - \reg_wp.addr_data_f1[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[19]\); - - \prdata_RNO_3[20]\ : OR3B - port map(A => N_168, B => \addr_data_f2[20]\, C => N_232, Y - => \addr_data_f2_m_i[20]\); - - \prdata_RNO_3[12]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[12]\, C => \addr_matrix_f0_1_m_i[12]\, - Y => \prdata_39_0_iv_1[12]\); - - \reg_sp.addr_matrix_f2[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[5]\); - - \prdata_RNO_9[4]\ : NOR3C - port map(A => \prdata_39_0_iv_4[4]\, B => - \prdata_39_0_iv_3[4]\, C => \addr_data_f3_m_i[4]\, Y => - \prdata_39_0_iv_10[4]\); - - \prdata_RNO[4]\ : OR3C - port map(A => \prdata_39_0_iv_12[4]\, B => - \prdata_39_0_iv_11[4]\, C => \prdata_39_0_iv_13[4]\, Y - => \prdata_39[4]\); - - \prdata_RNO_1[14]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[14]\, - C => \addr_data_f2_m_i[14]\, Y => \prdata_39_0_iv_3[14]\); - - \prdata_RNO_6[9]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[9]\, Y - => \delta_snapshot_m_i[9]\); - - \reg_sp.addr_matrix_f1[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[31]\); - - \prdata_RNO_4[1]\ : NOR3C - port map(A => \prdata_39_0_iv_1[1]\, B => - \prdata_39_0_iv_0[1]\, C => \prdata_39_0_iv_2[1]\, Y => - \prdata_39_0_iv_4[1]\); - - \reg_wp.nb_burst_available[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[3]\); - - \reg_sp.addr_matrix_f1[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[30]\); - - \prdata_RNO_8[11]\ : OR2B - port map(A => \status_new_err[3]\, B => prdata_13_sqmuxa, Y - => \status_new_err_m_i[3]\); - - \prdata_RNO_8[16]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[16]\, Y - => \addr_matrix_f2_m_i[16]\); - - \reg_wp.nb_burst_available_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_158, B => N_159, C => N_71, Y => - nb_burst_available_1_sqmuxa); - - \reg_sp.status_ready_matrix_f0_0\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f0_0); - - \prdata_RNO_0[2]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[2]\, C - => \addr_data_f1_m_i[2]\, Y => \prdata_39_0_iv_12[2]\); - - \reg_wp.addr_data_f1[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[6]\); - - \prdata_RNO_10[10]\ : OR2B - port map(A => \status_new_err[2]\, B => prdata_13_sqmuxa, Y - => \status_new_err_m_i[2]\); - - \reg_wp.addr_data_f1[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[7]\); - - \reg_wp.addr_data_f0[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[12]\); - - \prdata_RNO_8[25]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[25]\, Y - => \addr_matrix_f2_m_i[25]\); - - \prdata_RNO_1[27]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[27]\, Y - => \addr_data_f1_m_i[27]\); - - \reg_sp.addr_matrix_f0_0[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[20]\); - - \prdata_RNO_18[4]\ : NOR2B - port map(A => status_error_anticipating_empty_fifo_m_i, B - => \prdata_39_0_iv_0[4]\, Y => \prdata_39_0_iv_2[4]\); - - \prdata_RNO_20[4]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[4]\, C - => \delta_f2_f1_m_i[4]\, Y => \prdata_39_0_iv_0[4]\); - - \prdata_RNO_0[10]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[10]\, C - => \prdata_39_0_iv_4[10]\, Y => \prdata_39_0_iv_7[10]\); - - \reg_wp.nb_snapshot_param_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_158, B => N_159, C => N_166, Y => - nb_snapshot_param_1_sqmuxa); - - \reg_wp.enable_f1\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \enable_f1\); - - \reg_sp.addr_matrix_f0_0[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[23]\); - - \prdata_RNO_4[9]\ : NOR3C - port map(A => \prdata_39_0_iv_1[9]\, B => - \prdata_39_0_iv_0[9]\, C => \addr_matrix_f1_m_i[9]\, Y - => \prdata_39_0_iv_3[9]\); - - \prdata_RNO_10[15]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[15]\, - Y => \addr_matrix_f2_m_i[15]\); - - \prdata_RNO_8[12]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[12]\, Y => \addr_matrix_f0_1_m_i[12]\); - - \prdata[4]\ : DFN1C0 - port map(D => \prdata_39[4]\, CLK => lclk_c, CLR => rstn, Q - => prdata(4)); - - \prdata_RNO_6[15]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[15]\, - Y => \addr_data_f1_m_i[15]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_2 is - - port( S_0 : in std_logic_vector(8 to 8); - S_i : in std_logic_vector(1 to 1); - alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff : in std_logic_vector(4 downto 2); - S_26 : in std_logic; - S_6 : in std_logic; - S_15 : in std_logic; - S_22 : in std_logic; - S_8 : in std_logic; - S_12 : in std_logic; - S_20 : in std_logic; - S_2 : in std_logic; - S_33 : in std_logic; - S_11 : in std_logic; - S_19 : in std_logic; - S_0_d0 : in std_logic; - S_17 : in std_logic; - S_51 : in std_logic; - S_10 : in std_logic; - S_9 : in std_logic; - S_25 : in std_logic; - S_7 : in std_logic; - S_16 : in std_logic; - S_13 : in std_logic; - S_23 : in std_logic; - S_5 : in std_logic - ); - -end MUXN_9_2; - -architecture DEF_ARCH of MUXN_9_2 is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_47, N_28, N_19, N_43, N_40, N_37, N_25, N_16, N_56, - N_55, N_52, N_53, N_49, N_50, N_48, N_44, N_45, N_42, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \NB_STAGE_2.all_input.6.RES_8_1[6]\ : MX2C - port map(A => S_2, B => S_20, S => alu_sel_coeff(4), Y => - N_52); - - \NB_STAGE_2.all_input.7.RES_6_3[7]\ : MX2 - port map(A => N_55, B => N_37, S => alu_sel_coeff(3), Y => - alu_coef_s(7)); - - \NB_STAGE_2.all_input.7.RES_6_2[7]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_10, Y => N_37); - - \NB_STAGE_2.all_input.4.RES_12_1[4]\ : MX2 - port map(A => S_2, B => S_22, S => alu_sel_coeff(4), Y => - N_48); - - \NB_STAGE_2.all_input.0.RES_20_2[0]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_17, Y => N_16); - - \NB_STAGE_2.all_input.2.RES_16_2[2]\ : MX2C - port map(A => S_15, B => S_33, S => alu_sel_coeff(4), Y => - N_45); - - \NB_STAGE_2.all_input.1.RES_18_1[1]\ : MX2C - port map(A => S_7, B => S_25, S => alu_sel_coeff(4), Y => - N_43); - - GND_i_0 : GND - port map(Y => GND_0); - - \NB_STAGE_2.all_input.2.RES_16_3[2]\ : MX2 - port map(A => N_44, B => N_45, S => alu_sel_coeff(3), Y => - alu_coef_s(2)); - - \NB_STAGE_2.all_input.2.RES_16_1[2]\ : MX2C - port map(A => S_6, B => S_11, S => alu_sel_coeff(4), Y => - N_44); - - VCC_i : VCC - port map(Y => \VCC\); - - \NB_STAGE_2.all_input.6.RES_8_2[6]\ : MX2B - port map(A => S_11, B => S_33, S => alu_sel_coeff(4), Y => - N_53); - - \NB_STAGE_2.all_input.3.RES_14_1[3]\ : MX2C - port map(A => S_5, B => S_23, S => alu_sel_coeff(4), Y => - N_47); - - \NB_STAGE_2.all_input.3.RES_14_2[3]\ : OA1C - port map(A => S_51, B => alu_sel_coeff(2), C => - alu_sel_coeff(4), Y => N_25); - - GND_i : GND - port map(Y => \GND\); - - \NB_STAGE_2.all_input.3.RES_14_3[3]\ : MX2 - port map(A => N_47, B => N_25, S => alu_sel_coeff(3), Y => - alu_coef_s(3)); - - \NB_STAGE_2.all_input.8.RES_4_3[8]\ : MX2 - port map(A => N_56, B => N_40, S => alu_sel_coeff(3), Y => - alu_coef_s(8)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \NB_STAGE_2.all_input.1.RES_18_3[1]\ : MX2 - port map(A => N_43, B => N_19, S => alu_sel_coeff(3), Y => - alu_coef_s(1)); - - \NB_STAGE_2.all_input.6.RES_8_3[6]\ : MX2 - port map(A => N_52, B => N_53, S => alu_sel_coeff(3), Y => - alu_coef_s(6)); - - \NB_STAGE_2.all_input.8.RES_4_1[8]\ : MX2C - port map(A => S_0_d0, B => S_19, S => alu_sel_coeff(4), Y - => N_56); - - \NB_STAGE_2.all_input.4.RES_12_3[4]\ : MX2 - port map(A => N_48, B => N_28, S => alu_sel_coeff(3), Y => - alu_coef_s(4)); - - \NB_STAGE_2.all_input.4.RES_12_2[4]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_13, Y => N_28); - - \NB_STAGE_2.all_input.0.RES_20_3[0]\ : MX2 - port map(A => N_42, B => N_16, S => alu_sel_coeff(3), Y => - alu_coef_s(0)); - - \NB_STAGE_2.all_input.8.RES_4_2[8]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_9, Y => N_40); - - \NB_STAGE_2.all_input.7.RES_6_1[7]\ : MX2C - port map(A => S_i(1), B => S_19, S => alu_sel_coeff(4), Y - => N_55); - - \NB_STAGE_2.all_input.1.RES_18_2[1]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_16, Y => N_19); - - \NB_STAGE_2.all_input.5.RES_10_1[5]\ : MX2C - port map(A => S_5, B => S_8, S => alu_sel_coeff(4), Y => - N_49); - - \NB_STAGE_2.all_input.5.RES_10_2[5]\ : MX2C - port map(A => S_12, B => S_33, S => alu_sel_coeff(4), Y => - N_50); - - \NB_STAGE_2.all_input.5.RES_10_3[5]\ : MX2 - port map(A => N_49, B => N_50, S => alu_sel_coeff(3), Y => - alu_coef_s(5)); - - \NB_STAGE_2.all_input.0.RES_20_1[0]\ : MX2C - port map(A => S_0(8), B => S_26, S => alu_sel_coeff(4), Y - => N_42); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_3 is - - port( S_0 : in std_logic_vector(8 to 8); - alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff : in std_logic_vector(4 downto 0); - S_51 : in std_logic; - S_44 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff_0_2 : in std_logic - ); - -end MUXN_9_3; - -architecture DEF_ARCH of MUXN_9_3 is - - component MUXN_9_2 - port( S_0 : in std_logic_vector(8 to 8) := (others => 'U'); - S_i : in std_logic_vector(1 to 1) := (others => 'U'); - alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff : in std_logic_vector(4 downto 2) := (others => 'U'); - S_26 : in std_logic := 'U'; - S_6 : in std_logic := 'U'; - S_15 : in std_logic := 'U'; - S_22 : in std_logic := 'U'; - S_8 : in std_logic := 'U'; - S_12 : in std_logic := 'U'; - S_20 : in std_logic := 'U'; - S_2 : in std_logic := 'U'; - S_33 : in std_logic := 'U'; - S_11 : in std_logic := 'U'; - S_19 : in std_logic := 'U'; - S_0_d0 : in std_logic := 'U'; - S_17 : in std_logic := 'U'; - S_51 : in std_logic := 'U'; - S_10 : in std_logic := 'U'; - S_9 : in std_logic := 'U'; - S_25 : in std_logic := 'U'; - S_7 : in std_logic := 'U'; - S_16 : in std_logic := 'U'; - S_13 : in std_logic := 'U'; - S_23 : in std_logic := 'U'; - S_5 : in std_logic := 'U' - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO14 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO6 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AO16 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO17 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \S[23]_net_1\, \S[16]_net_1\, \S[25]_net_1\, - \S[13]_net_1\, \S[7]_net_1\, \S[12]_net_1\, \S[2]_net_1\, - \S[33]\, \S[19]\, \S[10]_net_1\, \S[9]_net_1\, \S_i[1]\, - \S[0]_net_1\, \S[22]_net_1\, \S[20]_net_1\, \S[17]_net_1\, - \S[5]\, \S[26]_net_1\, \S[15]_net_1\, \S[11]_net_1\, - \S[8]_net_1\, \S[6]_net_1\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : MUXN_9_2 - Use entity work.MUXN_9_2(DEF_ARCH); -begin - - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_2 - port map(S_0(8) => \S[8]_net_1\, S_i(1) => \S_i[1]\, - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_sel_coeff(4) => alu_sel_coeff(4), alu_sel_coeff(3) - => alu_sel_coeff(3), alu_sel_coeff(2) => - alu_sel_coeff(2), S_26 => \S[26]_net_1\, S_6 => - \S[6]_net_1\, S_15 => \S[15]_net_1\, S_22 => - \S[22]_net_1\, S_8 => S_0(8), S_12 => \S[12]_net_1\, S_20 - => \S[20]_net_1\, S_2 => \S[2]_net_1\, S_33 => \S[33]\, - S_11 => \S[11]_net_1\, S_19 => \S[19]\, S_0_d0 => - \S[0]_net_1\, S_17 => \S[17]_net_1\, S_51 => S_51, S_10 - => \S[10]_net_1\, S_9 => \S[9]_net_1\, S_25 => - \S[25]_net_1\, S_7 => \S[7]_net_1\, S_16 => \S[16]_net_1\, - S_13 => \S[13]_net_1\, S_23 => \S[23]_net_1\, S_5 => - \S[5]\); - - \S[26]\ : AX1B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[26]_net_1\); - - \S[13]\ : XO1A - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[13]_net_1\); - - \S[3]\ : XA1 - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(2), C - => alu_sel_coeff(1), Y => \S[5]\); - - \S[9]\ : AO14 - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[9]_net_1\); - - \S[23]\ : NOR2 - port map(A => alu_sel_coeff_0_2, B => S_44, Y => - \S[23]_net_1\); - - \S[15]\ : AXOI5 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[15]_net_1\); - - \S[11]\ : XA1 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[11]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \S[8]\ : AXO5 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), C - => alu_sel_coeff(2), Y => \S[8]_net_1\); - - \S[6]\ : AXO6 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[6]_net_1\); - - \S[25]\ : AXOI3 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[25]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \S[17]\ : AO16 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[17]_net_1\); - - \S[10]\ : AO17 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[10]_net_1\); - - \S[20]\ : AO1C - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(2), C - => alu_sel_coeff(1), Y => \S[20]_net_1\); - - \S[7]\ : AO16 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_0, C - => alu_sel_coeff_0_2, Y => \S[7]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \S[18]\ : XAI1A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[19]\); - - \S[0]\ : AXO5 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[0]_net_1\); - - \S[29]\ : OR3 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), C - => alu_sel_coeff_0_2, Y => \S[33]\); - - \S[1]\ : XNOR2 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(0), Y - => \S_i[1]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \S[12]\ : AO1A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), C - => alu_sel_coeff_0_2, Y => \S[12]_net_1\); - - \S[22]\ : AXOI5 - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(2), C - => alu_sel_coeff(1), Y => \S[22]_net_1\); - - \S[2]\ : OR3B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[2]_net_1\); - - \S[16]\ : MX2B - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff_0_0, S - => alu_sel_coeff(1), Y => \S[16]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_4 is - - port( alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0); - S_0 : out std_logic; - S_36 : out std_logic - ); - -end MUXN_9_4; - -architecture DEF_ARCH of MUXN_9_4 is - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MUXN_9_3 - port( S_0 : in std_logic_vector(8 to 8) := (others => 'U'); - alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - S_51 : in std_logic := 'U'; - S_44 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : in std_logic := 'U' - ); - end component; - - signal \S[51]\, \S[8]_net_1\, \S[44]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : MUXN_9_3 - Use entity work.MUXN_9_3(DEF_ARCH); -begin - - S_0 <= \S[8]_net_1\; - S_36 <= \S[44]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \S_0[28]\ : XOR2 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_0, Y - => \S[44]\); - - \S[8]\ : OR2B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_0, Y - => \S[8]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \S[23]\ : NOR2A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), Y - => \S[51]\); - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_3 - port map(S_0(8) => \S[8]_net_1\, alu_coef_s(8) => - alu_coef_s(8), alu_coef_s(7) => alu_coef_s(7), - alu_coef_s(6) => alu_coef_s(6), alu_coef_s(5) => - alu_coef_s(5), alu_coef_s(4) => alu_coef_s(4), - alu_coef_s(3) => alu_coef_s(3), alu_coef_s(2) => - alu_coef_s(2), alu_coef_s(1) => alu_coef_s(1), - alu_coef_s(0) => alu_coef_s(0), alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_sel_coeff(2) => alu_sel_coeff(2), alu_sel_coeff(1) - => alu_sel_coeff(1), alu_sel_coeff(0) => - alu_sel_coeff(0), S_51 => \S[51]\, S_44 => \S[44]\, - alu_sel_coeff_0_0 => alu_sel_coeff_0_0, alu_sel_coeff_0_2 - => alu_sel_coeff_0_2); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_5 is - - port( S_36 : out std_logic; - S_0 : out std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0); - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff_0_2 : in std_logic; - alu_coef_s : out std_logic_vector(8 downto 0) - ); - -end MUXN_9_5; - -architecture DEF_ARCH of MUXN_9_5 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MUXN_9_4 - port( alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - S_0 : out std_logic; - S_36 : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : MUXN_9_4 - Use entity work.MUXN_9_4(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_4 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_sel_coeff_0_2 => alu_sel_coeff_0_2, alu_sel_coeff_0_0 - => alu_sel_coeff_0_0, alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_sel_coeff(2) => alu_sel_coeff(2), alu_sel_coeff(1) - => alu_sel_coeff(1), alu_sel_coeff(0) => - alu_sel_coeff(0), S_0 => S_0, S_36 => S_36); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_18 is - - port( alu_sample : in std_logic_vector(17 downto 0); - OP1_2C_D : out std_logic_vector(17 downto 0); - rstn : in std_logic; - lclk_c : in std_logic - ); - -end MAC_REG_18; - -architecture DEF_ARCH of MAC_REG_18 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[6]\ : DFN1C0 - port map(D => alu_sample(6), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(6)); - - \Q[13]\ : DFN1C0 - port map(D => alu_sample(13), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(13)); - - \Q[14]\ : DFN1C0 - port map(D => alu_sample(14), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(14)); - - \Q[15]\ : DFN1C0 - port map(D => alu_sample(15), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(15)); - - \Q[11]\ : DFN1C0 - port map(D => alu_sample(11), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(11)); - - GND_i_0 : GND - port map(Y => GND_0); - - \Q[2]\ : DFN1C0 - port map(D => alu_sample(2), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(2)); - - \Q[4]\ : DFN1C0 - port map(D => alu_sample(4), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(4)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[17]\ : DFN1C0 - port map(D => alu_sample(17), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(17)); - - \Q[10]\ : DFN1C0 - port map(D => alu_sample(10), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(10)); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[3]\ : DFN1C0 - port map(D => alu_sample(3), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(3)); - - \Q[7]\ : DFN1C0 - port map(D => alu_sample(7), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(7)); - - \Q[12]\ : DFN1C0 - port map(D => alu_sample(12), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(12)); - - \Q[8]\ : DFN1C0 - port map(D => alu_sample(8), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(8)); - - \Q[1]\ : DFN1C0 - port map(D => alu_sample(1), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(1)); - - \Q[0]\ : DFN1C0 - port map(D => alu_sample(0), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(0)); - - \Q[9]\ : DFN1C0 - port map(D => alu_sample(9), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(9)); - - \Q[5]\ : DFN1C0 - port map(D => alu_sample(5), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(5)); - - \Q[16]\ : DFN1C0 - port map(D => alu_sample(16), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(16)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_9 is - - port( alu_coef_s : in std_logic_vector(8 downto 0); - OP2_2C_D : out std_logic_vector(8 downto 0); - rstn : in std_logic; - lclk_c : in std_logic - ); - -end MAC_REG_9; - -architecture DEF_ARCH of MAC_REG_9 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[5]\ : DFN1C0 - port map(D => alu_coef_s(5), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(5)); - - \Q[3]\ : DFN1C0 - port map(D => alu_coef_s(3), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(3)); - - \Q[8]\ : DFN1C0 - port map(D => alu_coef_s(8), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(8)); - - \Q[7]\ : DFN1C0 - port map(D => alu_coef_s(7), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(7)); - - \Q[1]\ : DFN1C0 - port map(D => alu_coef_s(1), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(1)); - - \Q[2]\ : DFN1C0 - port map(D => alu_coef_s(2), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(2)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[6]\ : DFN1C0 - port map(D => alu_coef_s(6), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(6)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[0]\ : DFN1C0 - port map(D => alu_coef_s(0), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(0)); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \Q[4]\ : DFN1C0 - port map(D => alu_coef_s(4), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(4)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_4 is - - port( MACMUX2sel_D : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - MACMUX2sel_D_D : out std_logic - ); - -end MAC_REG_1_4; - -architecture DEF_ARCH of MAC_REG_1_4 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[0]\ : DFN1C0 - port map(D => MACMUX2sel_D, CLK => lclk_c, CLR => rstn, Q - => MACMUX2sel_D_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_CONTROLER is - - port( alu_ctrl : in std_logic_vector(1 downto 0); - mult : out std_logic; - N_4 : out std_logic; - MACMUX2sel : out std_logic; - mult_0 : out std_logic - ); - -end MAC_CONTROLER; - -architecture DEF_ARCH of MAC_CONTROLER is - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_mult_i : NOR2B - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => N_4); - - GND_i_0 : GND - port map(Y => GND_0); - - un2_mult_i_x2 : XOR2 - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => mult); - - VCC_i : VCC - port map(Y => \VCC\); - - un2_mult_i_x2_0 : XOR2 - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => mult_0); - - un1_add_0_a2 : NOR2A - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => - MACMUX2sel); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_MUX is - - port( OP1_2C_D : in std_logic_vector(17 downto 0); - MULTout : in std_logic_vector(24 downto 0); - ADDERinB : out std_logic_vector(24 downto 0); - OP2_2C_D : in std_logic_vector(8 downto 0); - ADDERout : in std_logic_vector(24 downto 0); - ADDERinA : out std_logic_vector(24 downto 0); - MACMUXsel_D : in std_logic; - MACMUXsel_D_1 : in std_logic; - MACMUXsel_D_0 : in std_logic - ); - -end MAC_MUX; - -architecture DEF_ARCH of MAC_MUX is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \OUTA[24]\ : MX2C - port map(A => ADDERout(24), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA(24)); - - \OUTB[3]\ : MX2 - port map(A => MULTout(3), B => OP1_2C_D(3), S => - MACMUXsel_D_1, Y => ADDERinB(3)); - - \OUTB[9]\ : MX2 - port map(A => MULTout(9), B => OP1_2C_D(9), S => - MACMUXsel_D_1, Y => ADDERinB(9)); - - \OUTA[0]\ : MX2 - port map(A => ADDERout(0), B => OP2_2C_D(0), S => - MACMUXsel_D_0, Y => ADDERinA(0)); - - \OUTA[3]\ : MX2 - port map(A => ADDERout(3), B => OP2_2C_D(3), S => - MACMUXsel_D_0, Y => ADDERinA(3)); - - \OUTB[11]\ : MX2 - port map(A => MULTout(11), B => OP1_2C_D(11), S => - MACMUXsel_D_1, Y => ADDERinB(11)); - - \OUTB[23]\ : MX2 - port map(A => MULTout(23), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(23)); - - \OUTB[12]\ : MX2 - port map(A => MULTout(12), B => OP1_2C_D(12), S => - MACMUXsel_D_1, Y => ADDERinB(12)); - - \OUTB[20]\ : MX2 - port map(A => MULTout(20), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(20)); - - \OUTB[19]\ : MX2 - port map(A => MULTout(19), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(19)); - - \OUTA[13]\ : MX2 - port map(A => ADDERout(13), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(13)); - - \OUTB[8]\ : MX2 - port map(A => MULTout(8), B => OP1_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinB(8)); - - \OUTA[10]\ : MX2 - port map(A => ADDERout(10), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(10)); - - VCC_i : VCC - port map(Y => \VCC\); - - \OUTB[6]\ : MX2 - port map(A => MULTout(6), B => OP1_2C_D(6), S => - MACMUXsel_D, Y => ADDERinB(6)); - - \OUTA[6]\ : MX2 - port map(A => ADDERout(6), B => OP2_2C_D(6), S => - MACMUXsel_D, Y => ADDERinA(6)); - - \OUTB[24]\ : MX2 - port map(A => MULTout(24), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(24)); - - \OUTA[14]\ : MX2 - port map(A => ADDERout(14), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(14)); - - \OUTB[2]\ : MX2 - port map(A => MULTout(2), B => OP1_2C_D(2), S => - MACMUXsel_D_1, Y => ADDERinB(2)); - - \OUTB[13]\ : MX2 - port map(A => MULTout(13), B => OP1_2C_D(13), S => - MACMUXsel_D_1, Y => ADDERinB(13)); - - \OUTB[10]\ : MX2 - port map(A => MULTout(10), B => OP1_2C_D(10), S => - MACMUXsel_D_1, Y => ADDERinB(10)); - - \OUTA[9]\ : MX2 - port map(A => ADDERout(9), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(9)); - - \OUTA[15]\ : MX2C - port map(A => ADDERout(15), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(15)); - - \OUTA[16]\ : MX2 - port map(A => ADDERout(16), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(16)); - - \OUTA[7]\ : MX2 - port map(A => ADDERout(7), B => OP2_2C_D(7), S => - MACMUXsel_D_0, Y => ADDERinA(7)); - - \OUTB[5]\ : MX2 - port map(A => MULTout(5), B => OP1_2C_D(5), S => - MACMUXsel_D_1, Y => ADDERinB(5)); - - \OUTB[14]\ : MX2 - port map(A => MULTout(14), B => OP1_2C_D(14), S => - MACMUXsel_D_1, Y => ADDERinB(14)); - - GND_i : GND - port map(Y => \GND\); - - \OUTA[18]\ : MX2 - port map(A => ADDERout(18), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(18)); - - \OUTB[4]\ : MX2 - port map(A => MULTout(4), B => OP1_2C_D(4), S => - MACMUXsel_D_1, Y => ADDERinB(4)); - - \OUTB[15]\ : MX2 - port map(A => MULTout(15), B => OP1_2C_D(15), S => - MACMUXsel_D_1, Y => ADDERinB(15)); - - \OUTB[16]\ : MX2 - port map(A => MULTout(16), B => OP1_2C_D(16), S => - MACMUXsel_D, Y => ADDERinB(16)); - - \OUTA[21]\ : MX2 - port map(A => ADDERout(21), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA(21)); - - \OUTA[22]\ : MX2C - port map(A => ADDERout(22), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA(22)); - - \OUTA[17]\ : MX2C - port map(A => ADDERout(17), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA(17)); - - \OUTB[18]\ : MX2 - port map(A => MULTout(18), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(18)); - - \OUTA[4]\ : MX2 - port map(A => ADDERout(4), B => OP2_2C_D(4), S => - MACMUXsel_D_0, Y => ADDERinA(4)); - - \OUTA[1]\ : MX2C - port map(A => ADDERout(1), B => OP2_2C_D(1), S => - MACMUXsel_D, Y => ADDERinA(1)); - - \OUTB[7]\ : MX2 - port map(A => MULTout(7), B => OP1_2C_D(7), S => - MACMUXsel_D_1, Y => ADDERinB(7)); - - \OUTA[2]\ : MX2 - port map(A => ADDERout(2), B => OP2_2C_D(2), S => - MACMUXsel_D_0, Y => ADDERinA(2)); - - \OUTA[23]\ : MX2 - port map(A => ADDERout(23), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA(23)); - - \OUTA[20]\ : MX2 - port map(A => ADDERout(20), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(20)); - - \OUTB[17]\ : MX2 - port map(A => MULTout(17), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(17)); - - \OUTB[21]\ : MX2 - port map(A => MULTout(21), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(21)); - - \OUTA[8]\ : MX2 - port map(A => ADDERout(8), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(8)); - - \OUTB[22]\ : MX2 - port map(A => MULTout(22), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(22)); - - \OUTB[0]\ : MX2 - port map(A => MULTout(0), B => OP1_2C_D(0), S => - MACMUXsel_D_1, Y => ADDERinB(0)); - - \OUTA[11]\ : MX2 - port map(A => ADDERout(11), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(11)); - - \OUTB[1]\ : MX2 - port map(A => MULTout(1), B => OP1_2C_D(1), S => - MACMUXsel_D_1, Y => ADDERinB(1)); - - \OUTA[5]\ : MX2 - port map(A => ADDERout(5), B => OP2_2C_D(5), S => - MACMUXsel_D_0, Y => ADDERinA(5)); - - \OUTA[12]\ : MX2 - port map(A => ADDERout(12), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(12)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \OUTA[19]\ : MX2 - port map(A => ADDERout(19), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA(19)); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_27 is - - port( MULTout : in std_logic_vector(24 downto 7); - MULTout_D : out std_logic_vector(24 downto 7); - rstn : in std_logic; - lclk_c : in std_logic - ); - -end MAC_REG_27; - -architecture DEF_ARCH of MAC_REG_27 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[24]\ : DFN1C0 - port map(D => MULTout(24), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(24)); - - \Q[21]\ : DFN1C0 - port map(D => MULTout(21), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(21)); - - \Q[13]\ : DFN1C0 - port map(D => MULTout(13), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(13)); - - \Q[14]\ : DFN1C0 - port map(D => MULTout(14), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(14)); - - \Q[15]\ : DFN1C0 - port map(D => MULTout(15), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(15)); - - \Q[11]\ : DFN1C0 - port map(D => MULTout(11), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(11)); - - GND_i_0 : GND - port map(Y => GND_0); - - \Q[20]\ : DFN1C0 - port map(D => MULTout(20), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(20)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[17]\ : DFN1C0 - port map(D => MULTout(17), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(17)); - - \Q[10]\ : DFN1C0 - port map(D => MULTout(10), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(10)); - - \Q[19]\ : DFN1C0 - port map(D => MULTout(19), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(19)); - - GND_i : GND - port map(Y => \GND\); - - \Q[18]\ : DFN1C0 - port map(D => MULTout(18), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(18)); - - \Q[22]\ : DFN1C0 - port map(D => MULTout(22), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(22)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[7]\ : DFN1C0 - port map(D => MULTout(7), CLK => lclk_c, CLR => rstn, Q => - MULTout_D(7)); - - \Q[12]\ : DFN1C0 - port map(D => MULTout(12), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(12)); - - \Q[8]\ : DFN1C0 - port map(D => MULTout(8), CLK => lclk_c, CLR => rstn, Q => - MULTout_D(8)); - - \Q[9]\ : DFN1C0 - port map(D => MULTout(9), CLK => lclk_c, CLR => rstn, Q => - MULTout_D(9)); - - \Q[23]\ : DFN1C0 - port map(D => MULTout(23), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(23)); - - \Q[16]\ : DFN1C0 - port map(D => MULTout(16), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(16)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_1 is - - port( alu_ctrl : in std_logic_vector(0 to 0); - add_D : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - add_D_0 : out std_logic - ); - -end MAC_REG_1_1; - -architecture DEF_ARCH of MAC_REG_1_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_0[0]\ : DFN1C0 - port map(D => alu_ctrl(0), CLK => lclk_c, CLR => rstn, Q - => add_D_0); - - \Q[0]\ : DFN1C0 - port map(D => alu_ctrl(0), CLK => lclk_c, CLR => rstn, Q - => add_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_3 is - - port( MACMUX2sel : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - MACMUX2sel_D : out std_logic - ); - -end MAC_REG_1_3; - -architecture DEF_ARCH of MAC_REG_1_3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[0]\ : DFN1C0 - port map(D => MACMUX2sel, CLK => lclk_c, CLR => rstn, Q => - MACMUX2sel_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1 is - - port( alu_ctrl : in std_logic_vector(2 to 2); - clr_MAC_D : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - clr_MAC_D_0 : out std_logic - ); - -end MAC_REG_1; - -architecture DEF_ARCH of MAC_REG_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_0[0]\ : DFN1C0 - port map(D => alu_ctrl(2), CLK => lclk_c, CLR => rstn, Q - => clr_MAC_D_0); - - \Q[0]\ : DFN1C0 - port map(D => alu_ctrl(2), CLK => lclk_c, CLR => rstn, Q - => clr_MAC_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Adder is - - port( ADDERout : out std_logic_vector(24 downto 0); - ADDERinB : in std_logic_vector(24 downto 0); - ADDERinA : in std_logic_vector(24 downto 0); - rstn : in std_logic; - lclk_c : in std_logic; - clr_MAC_D : in std_logic; - add_D : in std_logic; - clr_MAC_D_0 : in std_logic; - MACMUX2sel_D : in std_logic; - add_D_0 : in std_logic - ); - -end Adder; - -architecture DEF_ARCH of Adder is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_clr_1_0\, ADD_27x27_fast_I247_Y_0_0, - ADD_27x27_fast_I253_Y_0_0, ADD_27x27_fast_I254_Y_0_0, - ADD_27x27_fast_I208_Y_3, N534, N519, - ADD_27x27_fast_I208_Y_2, N472, N465, - ADD_27x27_fast_I208_Y_1, N412, N415, - ADD_27x27_fast_I208_Y_0, N388, ADD_27x27_fast_I251_Y_0_0, - ADD_27x27_fast_I243_Y_0_0, ADD_27x27_fast_I207_Y_3, N517, - N532, ADD_27x27_fast_I207_Y_2, N470, N463, - ADD_27x27_fast_I207_Y_1, N413, N410, - ADD_27x27_fast_I207_Y_0, N391, ADD_27x27_fast_I239_Y_0_0, - ADD_27x27_fast_I249_Y_0_0, ADD_27x27_fast_I196_Y_0_0, - N496, N_73, N439, ADD_27x27_fast_I241_Y_0_0, - ADD_27x27_fast_I250_Y_0_0, ADD_27x27_fast_I242_Y_0_0, - ADD_27x27_fast_I252_Y_0_0, ADD_27x27_fast_I212_Y_1, N542, - N527, ADD_27x27_fast_I212_Y_0, N480, N473, - ADD_27x27_fast_I164_Y_i_0, N_58, - ADD_27x27_fast_I248_Y_0_0, ADD_27x27_fast_I211_Y_1, N540, - N525, ADD_27x27_fast_I211_Y_0, N478, N471, - ADD_27x27_fast_I209_Y_2, N536, N521, - ADD_27x27_fast_I209_Y_1, N467_i, N474, - ADD_27x27_fast_I209_Y_0, N417, N414, - ADD_27x27_fast_I240_Y_0_0, ADD_27x27_fast_I213_Y_1, - ADD_27x27_fast_I213_un1_Y_0, N529, - ADD_27x27_fast_I213_Y_0, N482, N475, - ADD_27x27_fast_I236_Y_0_0, N499, N_47, N491, - ADD_27x27_fast_I115_Y_0, N340, ADD_27x27_fast_I99_Y_0, - N364, ADD_27x27_fast_I91_Y_0, N376, - ADD_27x27_fast_I107_Y_0, N352, - ADD_27x27_fast_I115_un1_Y_0, N_108, - ADD_27x27_fast_I116_Y_0, ADD_27x27_fast_I100_Y_0, N362, - I207_un1_Y, N533, N548, I209_un1_Y, N537, N552, - I211_un1_Y_i, N541, N502, N431, N428, N481, N488, N436, - N444, N497, I208_un1_Y, N535, N550, N_33, N_48, - \un1_clr_1\, \un2_resadd[23]\, \un2_resadd[22]\, - \un2_resadd[20]\, \un2_resadd[18]\, I185_un1_Y, - \un2_resadd[16]\, N648, \un2_resadd[15]\, N651, - \un2_resadd[14]\, N654_i, \un2_resadd[13]\, - ADD_27x27_fast_I192_Y_0_a2, N361, \un2_resadd[12]\, - I193_un1_Y, \un2_resadd[11]\, ADD_27x27_fast_I194_un1_Y, - \un2_resadd[10]\, ADD_27x27_fast_I195_un1_Y, N544, - \un2_resadd[9]\, N_78_i, \un2_resadd[8]\, \un2_resadd[7]\, - \un2_resadd[5]\, \un2_resadd[4]\, \un2_resadd[3]\, - \un2_resadd[2]\, \un2_resadd[24]\, \un2_resadd[17]\, N423, - N_98_i, N420, \un2_resadd[1]\, N325, \un2_resadd[6]\, - \un2_resadd[19]\, I212_un1_Y, \un2_resadd[21]\, N_105, - N543, N392, N355, N356, N425, N367, N429, N437, N349, - N441, N343, N445, N_52_i_0, N449, N_72, N450, N422, N421, - N426, N433, N430, N483, N434, N490, N438, N442, N494, - N498, N446, N486, N479, N487, N495, N371, N365, N350, - N344, N341, N418, N346, N370, N489, I162_un1_Y, - I190_un1_Y, N_59, N_50, N_9, N_11, N_16, N_18, N_23, N_30, - \REG_4[1]\, \REG_4[3]\, \REG_4[8]\, \REG_4[10]\, - \REG_4[15]\, \REG_4[22]\, N_8, N_12, N_15, N_19, N_22, - N_26, \REG_4[0]\, \REG_4[4]\, \REG_4[7]\, \REG_4[11]\, - \REG_4[14]\, \REG_4[18]\, N_10, N_13, N_17, N_20, N_21, - N_24, N_28, N_31, \REG_4[2]\, \REG_4[5]\, \REG_4[9]\, - \REG_4[12]\, \REG_4[13]\, \REG_4[16]\, \REG_4[20]\, - \REG_4[23]\, \REG_4[24]\, N_32, N_23_0, \REG_4[17]\, N_25, - N374, N373, N380, N_43, \REG_4[19]\, N_27, \REG_4[6]\, - N_14, \REG_4[21]\, N_29, N386, N382, N385, N379, - I163_un1_Y, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - un2_resadd_ADD_27x27_fast_I8_G0N : NOR2B - port map(A => ADDERinB(8), B => ADDERinA(8), Y => N349); - - un2_resadd_ADD_27x27_fast_I241_Y_0_0 : XOR2 - port map(A => ADDERinA(11), B => ADDERinB(11), Y => - ADD_27x27_fast_I241_Y_0_0); - - un2_resadd_ADD_27x27_fast_I134_Y : NOR2 - port map(A => N475, B => N467_i, Y => N521); - - un2_resadd_ADD_27x27_fast_I208_Y_1 : OA1A - port map(A => N412, B => N415, C => ADD_27x27_fast_I208_Y_0, - Y => ADD_27x27_fast_I208_Y_1); - - un2_resadd_ADD_27x27_fast_I156_Y : NOR2A - port map(A => N497, B => N489, Y => N543); - - un2_resadd_ADD_27x27_fast_I21_G0N : NOR2B - port map(A => ADDERinB(21), B => ADDERinA(21), Y => N388); - - \REG[14]\ : DFN1E0C0 - port map(D => \REG_4[14]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(14)); - - un2_resadd_ADD_27x27_fast_I214_Y_0_a2 : OR2A - port map(A => N651, B => N_23_0, Y => N_98_i); - - un2_resadd_ADD_27x27_fast_I12_G0N : OR2B - port map(A => ADDERinB(12), B => ADDERinA(12), Y => N361); - - un2_resadd_ADD_27x27_fast_I99_Y : AO1B - port map(A => N431, B => N428, C => ADD_27x27_fast_I99_Y_0, - Y => N480); - - un2_resadd_ADD_27x27_fast_I149_Y : AO1A - port map(A => N483, B => N490, C => N482, Y => N536); - - un2_resadd_ADD_27x27_fast_I68_Y : OA1 - port map(A => ADDERinA(4), B => ADDERinB(4), C => N341, Y - => N446); - - un2_resadd_ADD_27x27_fast_I5_P0N : OR2 - port map(A => ADDERinB(5), B => ADDERinA(5), Y => N341); - - un2_resadd_ADD_27x27_fast_I11_G0N_0_o2 : OR2B - port map(A => ADDERinB(11), B => ADDERinA(11), Y => N_50); - - un2_resadd_ADD_27x27_fast_I209_Y_0 : AOI1 - port map(A => N417, B => N414, C => N413, Y => - ADD_27x27_fast_I209_Y_0); - - un2_resadd_ADD_27x27_fast_I132_Y : NOR2B - port map(A => N473, B => N465, Y => N519); - - un2_resadd_ADD_27x27_fast_I122_Y_i_o2 : MAJ3 - port map(A => ADDERinA(2), B => ADDERinB(2), C => N_47, Y - => N_48); - - un2_resadd_ADD_27x27_fast_I93_Y : AOI1 - port map(A => N425, B => N422, C => N421, Y => N474); - - un2_resadd_ADD_27x27_fast_I52_Y : NOR2B - port map(A => N365, B => N362, Y => N430); - - un2_resadd_ADD_27x27_fast_I254_Y_0 : AX1C - port map(A => I207_un1_Y, B => ADD_27x27_fast_I207_Y_3, C - => ADD_27x27_fast_I254_Y_0_0, Y => \un2_resadd[24]\); - - \REG_RNO[11]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_19, Y => \REG_4[11]\); - - \REG[22]\ : DFN1E0C0 - port map(D => \REG_4[22]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1\, Q => ADDERout(22)); - - un2_resadd_ADD_27x27_fast_I51_Y : AO13 - port map(A => ADDERinB(13), B => ADDERinA(13), C => N361, Y - => N429); - - \REG_RNO[20]\ : NOR2 - port map(A => clr_MAC_D, B => N_28, Y => \REG_4[20]\); - - \REG_RNO[15]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_23, Y => \REG_4[15]\); - - \REG_RNO_0[17]\ : MX2C - port map(A => ADDERinB(17), B => \un2_resadd[17]\, S => - add_D, Y => N_25); - - un2_resadd_ADD_27x27_fast_I196_Y_0_a2 : OR2A - port map(A => I162_un1_Y, B => N_73, Y => N_78_i); - - un2_resadd_ADD_27x27_fast_I240_Y_0_0 : XOR2 - port map(A => ADDERinA(10), B => ADDERinB(10), Y => - ADD_27x27_fast_I240_Y_0_0); - - un2_resadd_ADD_27x27_fast_I13_P0N : OR2 - port map(A => ADDERinB(13), B => ADDERinA(13), Y => N365); - - un2_resadd_ADD_27x27_fast_I6_G0N : NOR2B - port map(A => ADDERinB(6), B => ADDERinA(6), Y => N343); - - un2_resadd_ADD_27x27_fast_I163_Y : OR2 - port map(A => N498, B => I163_un1_Y, Y => N552); - - un2_resadd_ADD_27x27_fast_I90_Y : OR2B - port map(A => N422, B => N418, Y => N471); - - un2_resadd_ADD_27x27_fast_I35_Y : MAJ3 - port map(A => ADDERinA(21), B => ADDERinB(21), C => N385, Y - => N413); - - un2_resadd_ADD_27x27_fast_I48_Y : OA1 - port map(A => ADDERinA(14), B => ADDERinB(14), C => N371, Y - => N426); - - \REG_RNO[9]\ : NOR2 - port map(A => clr_MAC_D, B => N_17, Y => \REG_4[9]\); - - \REG_RNO_0[8]\ : MX2C - port map(A => ADDERinB(8), B => \un2_resadd[8]\, S => - add_D_0, Y => N_16); - - \REG[11]\ : DFN1E0C0 - port map(D => \REG_4[11]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(11)); - - un2_resadd_ADD_27x27_fast_I99_Y_0 : MIN3 - port map(A => ADDERinA(14), B => ADDERinB(14), C => N364, Y - => ADD_27x27_fast_I99_Y_0); - - un2_resadd_ADD_27x27_fast_I6_P0N : OR2 - port map(A => ADDERinB(6), B => ADDERinA(6), Y => N344); - - un2_resadd_ADD_27x27_fast_I15_G0N : NOR2A - port map(A => ADDERinB(15), B => ADDERinA(15), Y => N370); - - un2_resadd_ADD_27x27_fast_I207_Y_1 : AOI1B - port map(A => N413, B => N410, C => ADD_27x27_fast_I207_Y_0, - Y => ADD_27x27_fast_I207_Y_1); - - un2_resadd_ADD_27x27_fast_I207_Y_0 : MIN3 - port map(A => ADDERinA(23), B => ADDERinB(23), C => N391, Y - => ADD_27x27_fast_I207_Y_0); - - un2_resadd_ADD_27x27_fast_I116_Y : NOR2B - port map(A => ADD_27x27_fast_I116_Y_0, B => N444, Y => N497); - - un2_resadd_ADD_27x27_fast_I242_Y_0_0 : XOR2 - port map(A => ADDERinA(12), B => ADDERinB(12), Y => - ADD_27x27_fast_I242_Y_0_0); - - un2_resadd_ADD_27x27_fast_I163_un1_Y : NOR2B - port map(A => N_47, B => N499, Y => I163_un1_Y); - - un2_resadd_ADD_27x27_fast_I238_Y_0 : XNOR3 - port map(A => ADDERinB(8), B => ADDERinA(8), C => N548, Y - => \un2_resadd[8]\); - - \REG_RNO[4]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_12, Y => \REG_4[4]\); - - \REG_RNO[12]\ : NOR2 - port map(A => clr_MAC_D, B => N_20, Y => \REG_4[12]\); - - un2_resadd_ADD_27x27_fast_I140_Y : NOR2A - port map(A => N473, B => N481, Y => N527); - - un2_resadd_ADD_27x27_fast_I248_Y_0 : AX1E - port map(A => I185_un1_Y, B => ADD_27x27_fast_I213_Y_1, C - => ADD_27x27_fast_I248_Y_0_0, Y => \un2_resadd[18]\); - - \REG_RNO_0[11]\ : MX2C - port map(A => ADDERinB(11), B => \un2_resadd[11]\, S => - add_D_0, Y => N_19); - - un2_resadd_ADD_27x27_fast_I66_Y : NOR2B - port map(A => N344, B => N341, Y => N444); - - un2_resadd_ADD_27x27_fast_I247_Y_0_0 : XOR2 - port map(A => ADDERinA(17), B => ADDERinB(17), Y => - ADD_27x27_fast_I247_Y_0_0); - - un2_resadd_ADD_27x27_fast_I162_Y : OR2 - port map(A => N496, B => I162_un1_Y, Y => N550); - - un2_resadd_ADD_27x27_fast_I36_Y : OA1 - port map(A => ADDERinA(21), B => ADDERinB(21), C => N386, Y - => N414); - - un2_resadd_ADD_27x27_fast_I209_Y_2 : AOI1B - port map(A => N536, B => N521, C => ADD_27x27_fast_I209_Y_1, - Y => ADD_27x27_fast_I209_Y_2); - - un2_resadd_ADD_27x27_fast_I236_Y_0_0 : XOR2 - port map(A => ADDERinA(6), B => ADDERinB(6), Y => - ADD_27x27_fast_I236_Y_0_0); - - un2_resadd_ADD_27x27_fast_I212_Y_1 : AO1 - port map(A => N542, B => N527, C => ADD_27x27_fast_I212_Y_0, - Y => ADD_27x27_fast_I212_Y_1); - - un2_resadd_ADD_27x27_fast_I19_G0N : NOR2B - port map(A => ADDERinB(19), B => ADDERinA(19), Y => N382); - - \REG_RNO_0[10]\ : MX2C - port map(A => ADDERinB(10), B => \un2_resadd[10]\, S => - add_D_0, Y => N_18); - - \REG[12]\ : DFN1E0C0 - port map(D => \REG_4[12]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(12)); - - un2_resadd_ADD_27x27_fast_I84_Y : NOR2A - port map(A => N412, B => N_43, Y => N465); - - un2_resadd_ADD_27x27_fast_I107_Y_0 : MIN3 - port map(A => ADDERinA(10), B => ADDERinB(10), C => N352, Y - => ADD_27x27_fast_I107_Y_0); - - un2_resadd_ADD_27x27_fast_I185_un1_Y : OR2B - port map(A => N544, B => N529, Y => I185_un1_Y); - - un2_resadd_ADD_27x27_fast_I115_un1_Y_0 : OA1B - port map(A => ADDERinA(4), B => ADDERinB(4), C => N_108, Y - => ADD_27x27_fast_I115_un1_Y_0); - - un2_resadd_ADD_27x27_fast_I207_Y_2 : OA1A - port map(A => N470, B => N463, C => ADD_27x27_fast_I207_Y_1, - Y => ADD_27x27_fast_I207_Y_2); - - un2_resadd_ADD_27x27_fast_I118_Y : NOR2B - port map(A => N450, B => N446, Y => N499); - - un2_resadd_ADD_27x27_fast_I207_Y_3 : OA1A - port map(A => N517, B => N532, C => ADD_27x27_fast_I207_Y_2, - Y => ADD_27x27_fast_I207_Y_3); - - GND_i : GND - port map(Y => \GND\); - - \REG_RNO_0[21]\ : MX2C - port map(A => ADDERinB(21), B => \un2_resadd[21]\, S => - add_D, Y => N_29); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un2_resadd_ADD_27x27_fast_I63_Y : MAJ3 - port map(A => ADDERinA(7), B => ADDERinB(7), C => N343, Y - => N441); - - un2_resadd_ADD_27x27_fast_I236_Y_0 : XOR2 - port map(A => ADD_27x27_fast_I236_Y_0_0, B => N552, Y => - \un2_resadd[6]\); - - un2_resadd_ADD_27x27_fast_I45_Y_0_o2 : AO1 - port map(A => N374, B => N370, C => N373, Y => N423); - - un2_resadd_ADD_27x27_fast_I10_G0N : NOR2B - port map(A => ADDERinB(10), B => ADDERinA(10), Y => N355); - - un2_resadd_ADD_27x27_fast_I246_Y_0 : XOR3 - port map(A => ADDERinB(16), B => ADDERinA(16), C => N648, Y - => \un2_resadd[16]\); - - \REG_RNO[14]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_22, Y => \REG_4[14]\); - - un2_resadd_ADD_27x27_fast_I92_Y : NOR2A - port map(A => N420, B => N_23_0, Y => N473); - - un2_resadd_ADD_27x27_fast_I39_Y : MAJ3 - port map(A => ADDERinA(19), B => ADDERinB(19), C => N379, Y - => N417); - - un2_resadd_ADD_27x27_fast_I150_Y : NOR2 - port map(A => N491, B => N483, Y => N537); - - un2_resadd_ADD_27x27_fast_I235_Y_0 : XNOR3 - port map(A => ADDERinB(5), B => ADDERinA(5), C => N_33, Y - => \un2_resadd[5]\); - - un2_resadd_ADD_27x27_fast_I164_Y_i_0 : MAJ3 - port map(A => ADDERinA(4), B => ADDERinB(4), C => N_58, Y - => ADD_27x27_fast_I164_Y_i_0); - - un2_resadd_ADD_27x27_fast_I212_Y_0 : AO1 - port map(A => N480, B => N473, C => N472, Y => - ADD_27x27_fast_I212_Y_0); - - un2_resadd_ADD_27x27_fast_I196_Y_0_0 : OA1C - port map(A => N496, B => N_73, C => N439, Y => - ADD_27x27_fast_I196_Y_0_0); - - un2_resadd_ADD_27x27_fast_I245_Y_0 : XNOR3 - port map(A => ADDERinB(15), B => ADDERinA(15), C => N651, Y - => \un2_resadd[15]\); - - \REG[0]\ : DFN1E0C0 - port map(D => \REG_4[0]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1_0\, Q => ADDERout(0)); - - \REG_RNO[7]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_15, Y => \REG_4[7]\); - - un2_resadd_ADD_27x27_fast_I9_G0N : NOR2B - port map(A => ADDERinB(9), B => ADDERinA(9), Y => N352); - - un2_resadd_ADD_27x27_fast_I91_Y : AO1B - port map(A => N423, B => N420, C => ADD_27x27_fast_I91_Y_0, - Y => N472); - - \REG_RNO_0[20]\ : MX2C - port map(A => ADDERinB(20), B => \un2_resadd[20]\, S => - add_D, Y => N_28); - - un2_resadd_ADD_27x27_fast_I212_un1_Y : NOR3C - port map(A => N543, B => N527, C => N_48, Y => I212_un1_Y); - - un2_resadd_ADD_27x27_fast_I106_Y : OR2B - port map(A => N438, B => N434, Y => N487); - - un2_resadd_ADD_27x27_fast_I3_G0N_i_o2 : NOR2B - port map(A => ADDERinB(3), B => ADDERinA(3), Y => N_59); - - un2_resadd_ADD_27x27_fast_I60_Y : OA1 - port map(A => ADDERinA(9), B => ADDERinB(9), C => N350, Y - => N438); - - \REG[23]\ : DFN1E0C0 - port map(D => \REG_4[23]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1\, Q => ADDERout(23)); - - un2_resadd_ADD_27x27_fast_I208_Y_0 : AO18 - port map(A => N388, B => ADDERinA(22), C => ADDERinB(22), Y - => ADD_27x27_fast_I208_Y_0); - - \REG_RNO[1]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_9, Y => \REG_4[1]\); - - un2_resadd_ADD_27x27_fast_I43_Y : AO13 - port map(A => N373, B => ADDERinB(17), C => ADDERinA(17), Y - => N421); - - un2_resadd_ADD_27x27_fast_I190_un1_Y : NOR2B - port map(A => N550, B => N535, Y => I190_un1_Y); - - un2_resadd_ADD_27x27_fast_I20_P0N : OR2 - port map(A => ADDERinB(20), B => ADDERinA(20), Y => N386); - - un2_resadd_ADD_27x27_fast_I208_Y_2 : AOI1B - port map(A => N472, B => N465, C => ADD_27x27_fast_I208_Y_1, - Y => ADD_27x27_fast_I208_Y_2); - - un2_resadd_ADD_27x27_fast_I101_Y : AO1 - port map(A => N433, B => N430, C => N429, Y => N482); - - \REG_RNO[21]\ : NOR2 - port map(A => clr_MAC_D, B => N_29, Y => \REG_4[21]\); - - un2_resadd_ADD_27x27_fast_I162_un1_Y : NOR2B - port map(A => N_48, B => N497, Y => I162_un1_Y); - - un2_resadd_ADD_27x27_fast_I16_G0N : NOR2B - port map(A => ADDERinB(16), B => ADDERinA(16), Y => N373); - - VCC_i : VCC - port map(Y => \VCC\); - - un2_resadd_ADD_27x27_fast_I91_Y_0 : MIN3 - port map(A => ADDERinA(18), B => ADDERinB(18), C => N376, Y - => ADD_27x27_fast_I91_Y_0); - - un2_resadd_ADD_27x27_fast_I211_Y_0 : OA1C - port map(A => N478, B => N471, C => N470, Y => - ADD_27x27_fast_I211_Y_0); - - un2_resadd_ADD_27x27_fast_I97_Y : AO1 - port map(A => N429, B => N426, C => N425, Y => N478); - - un2_resadd_ADD_27x27_fast_I40_Y : OA1 - port map(A => ADDERinA(19), B => ADDERinB(19), C => N380, Y - => N418); - - un2_resadd_ADD_27x27_fast_I2_G0N_i_o2 : OR2B - port map(A => ADDERinB(2), B => ADDERinA(2), Y => N_72); - - \REG_RNO[13]\ : NOR2 - port map(A => clr_MAC_D, B => N_21, Y => \REG_4[13]\); - - un2_resadd_ADD_27x27_fast_I145_Y : OA1C - port map(A => N486, B => N479, C => N478, Y => N532); - - un2_resadd_ADD_27x27_fast_I108_Y : OR2A - port map(A => N436, B => N_73, Y => N489); - - \REG_RNO_0[19]\ : MX2C - port map(A => ADDERinB(19), B => \un2_resadd[19]\, S => - add_D, Y => N_27); - - un2_resadd_ADD_27x27_fast_I110_Y : OR2B - port map(A => N442, B => N438, Y => N491); - - \REG_RNO_0[6]\ : MX2C - port map(A => ADDERinB(6), B => \un2_resadd[6]\, S => add_D, - Y => N_14); - - un2_resadd_ADD_27x27_fast_I22_P0N : OR2A - port map(A => ADDERinA(22), B => ADDERinB(22), Y => N392); - - un2_resadd_ADD_27x27_fast_I213_Y_1 : AOI1B - port map(A => ADD_27x27_fast_I213_un1_Y_0, B => N529, C => - ADD_27x27_fast_I213_Y_0, Y => ADD_27x27_fast_I213_Y_1); - - un2_resadd_ADD_27x27_fast_I72_Y : OA1 - port map(A => ADDERinA(2), B => ADDERinB(2), C => N_58, Y - => N450); - - un2_resadd_ADD_27x27_fast_I116_Y_0 : OA1 - port map(A => ADDERinA(4), B => ADDERinB(4), C => N_58, Y - => ADD_27x27_fast_I116_Y_0); - - un2_resadd_ADD_27x27_fast_I109_Y : AO1 - port map(A => N441, B => N438, C => N437, Y => N490); - - \REG[9]\ : DFN1E0C0 - port map(D => \REG_4[9]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(9)); - - un1_clr_1_0 : NOR3 - port map(A => add_D_0, B => MACMUX2sel_D, C => clr_MAC_D_0, - Y => \un1_clr_1_0\); - - un2_resadd_ADD_27x27_fast_I142_Y : NOR2 - port map(A => N483, B => N475, Y => N529); - - \REG_RNO_0[9]\ : MX2C - port map(A => ADDERinB(9), B => \un2_resadd[9]\, S => add_D, - Y => N_17); - - un2_resadd_ADD_27x27_fast_I71_Y : AO13 - port map(A => ADDERinB(3), B => ADDERinA(3), C => N_72, Y - => N449); - - \REG_RNO[22]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_30, Y => \REG_4[22]\); - - \REG[5]\ : DFN1E0C0 - port map(D => \REG_4[5]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(5)); - - un2_resadd_ADD_27x27_fast_I210_Y_0_a2 : AO1D - port map(A => ADD_27x27_fast_I212_Y_1, B => I212_un1_Y, C - => N_43, Y => N_105); - - \REG_RNO[2]\ : NOR2 - port map(A => clr_MAC_D, B => N_10, Y => \REG_4[2]\); - - \REG[13]\ : DFN1E0C0 - port map(D => \REG_4[13]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(13)); - - un2_resadd_ADD_27x27_fast_I153_Y : AO1A - port map(A => N487, B => N494, C => N486, Y => N540); - - un2_resadd_ADD_27x27_fast_I232_Y_0 : XOR3 - port map(A => ADDERinB(2), B => ADDERinA(2), C => N_47, Y - => \un2_resadd[2]\); - - un2_resadd_ADD_27x27_fast_I100_Y_0 : OA1 - port map(A => ADDERinA(11), B => ADDERinB(11), C => N362, Y - => ADD_27x27_fast_I100_Y_0); - - \REG[6]\ : DFN1E0C0 - port map(D => \REG_4[6]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(6)); - - \REG[18]\ : DFN1E0C0 - port map(D => \REG_4[18]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(18)); - - un2_resadd_ADD_27x27_fast_I8_P0N : OR2 - port map(A => ADDERinB(8), B => ADDERinA(8), Y => N350); - - un2_resadd_ADD_27x27_fast_I14_G0N : NOR2B - port map(A => ADDERinB(14), B => ADDERinA(14), Y => N367); - - un2_resadd_ADD_27x27_fast_I242_Y_0 : AX1D - port map(A => I193_un1_Y, B => N540, C => - ADD_27x27_fast_I242_Y_0_0, Y => \un2_resadd[12]\); - - un2_resadd_ADD_27x27_fast_I211_un1_Y : OR3C - port map(A => N525, B => N541, C => N502, Y => I211_un1_Y_i); - - un2_resadd_ADD_27x27_fast_I46_Y_i : OR2B - port map(A => N374, B => N371, Y => N_23_0); - - un2_resadd_ADD_27x27_fast_I239_Y_0_0 : XOR2 - port map(A => ADDERinA(9), B => ADDERinB(9), Y => - ADD_27x27_fast_I239_Y_0_0); - - un2_resadd_ADD_27x27_fast_I155_Y : AO1A - port map(A => N489, B => N496, C => N488, Y => N542); - - un2_resadd_ADD_27x27_fast_I191_Y : AOI1 - port map(A => N552, B => N537, C => N536, Y => N654_i); - - \REG_RNO_0[13]\ : MX2C - port map(A => ADDERinB(13), B => \un2_resadd[13]\, S => - add_D, Y => N_21); - - un2_resadd_ADD_27x27_fast_I249_Y_0_0 : XOR2 - port map(A => ADDERinA(19), B => ADDERinB(19), Y => - ADD_27x27_fast_I249_Y_0_0); - - \REG_RNO_0[18]\ : MX2C - port map(A => ADDERinB(18), B => \un2_resadd[18]\, S => - add_D_0, Y => N_26); - - \REG_RNO[18]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_26, Y => \REG_4[18]\); - - \REG[19]\ : DFN1E0C0 - port map(D => \REG_4[19]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(19)); - - un2_resadd_ADD_27x27_fast_I32_Y : OA1 - port map(A => ADDERinA(23), B => ADDERinB(23), C => N392, Y - => N410); - - un2_resadd_ADD_27x27_fast_I53_Y_0 : AO1C - port map(A => N_50, B => N362, C => N361, Y => N431); - - un2_resadd_ADD_27x27_fast_I209_un1_Y : OR3C - port map(A => N537, B => N521, C => N552, Y => I209_un1_Y); - - un2_resadd_ADD_27x27_fast_I147_Y : AO1A - port map(A => N481, B => N488, C => N480, Y => N534); - - un2_resadd_ADD_27x27_fast_I253_Y_0_0 : XOR2 - port map(A => ADDERinA(23), B => ADDERinB(23), Y => - ADD_27x27_fast_I253_Y_0_0); - - un2_resadd_ADD_27x27_fast_I7_G0N : NOR2B - port map(A => ADDERinB(7), B => ADDERinA(7), Y => N346); - - un2_resadd_ADD_27x27_fast_I5_G0N : NOR2B - port map(A => ADDERinB(5), B => ADDERinA(5), Y => N340); - - un2_resadd_ADD_27x27_fast_I138_Y : NOR2 - port map(A => N479, B => N471, Y => N525); - - un2_resadd_ADD_27x27_fast_I154_Y : NOR2A - port map(A => N495, B => N487, Y => N541); - - un2_resadd_ADD_27x27_fast_I37_Y_0_o2 : AOI1 - port map(A => N386, B => N382, C => N385, Y => N415); - - \REG_RNO[19]\ : NOR2 - port map(A => clr_MAC_D, B => N_27, Y => \REG_4[19]\); - - un2_resadd_ADD_27x27_fast_I58_Y : OA1 - port map(A => ADDERinA(9), B => ADDERinB(9), C => N356, Y - => N436); - - \REG_RNO_0[1]\ : MX2C - port map(A => ADDERinB(1), B => \un2_resadd[1]\, S => - add_D_0, Y => N_9); - - un2_resadd_ADD_27x27_fast_I94_Y : OR2B - port map(A => N426, B => N422, Y => N475); - - un2_resadd_ADD_27x27_fast_I42_Y : OA1A - port map(A => ADDERinA(17), B => ADDERinB(17), C => N380, Y - => N420); - - un2_resadd_ADD_27x27_fast_I86_Y : OR2B - port map(A => N418, B => N414, Y => N467_i); - - un2_resadd_ADD_27x27_fast_I75_Y_i_o2 : AO18 - port map(A => ADDERinA(1), B => ADDERinB(1), C => N325, Y - => N_47); - - un2_resadd_ADD_27x27_fast_I231_Y_0 : XOR3 - port map(A => ADDERinB(1), B => ADDERinA(1), C => N325, Y - => \un2_resadd[1]\); - - \REG[1]\ : DFN1E0C0 - port map(D => \REG_4[1]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1_0\, Q => ADDERout(1)); - - un2_resadd_ADD_27x27_fast_I241_Y_0 : AX1D - port map(A => ADD_27x27_fast_I194_un1_Y, B => N542, C => - ADD_27x27_fast_I241_Y_0_0, Y => \un2_resadd[11]\); - - un2_resadd_ADD_27x27_fast_I17_G0N : NOR2A - port map(A => ADDERinB(17), B => ADDERinA(17), Y => N376); - - un2_resadd_ADD_27x27_fast_I100_Y : OR2B - port map(A => ADD_27x27_fast_I100_Y_0, B => N428, Y => N481); - - \REG_RNO[24]\ : NOR2 - port map(A => clr_MAC_D, B => N_32, Y => \REG_4[24]\); - - un2_resadd_ADD_27x27_fast_I55_Y : MAJ3 - port map(A => ADDERinA(11), B => ADDERinB(11), C => N355, Y - => N433); - - un2_resadd_ADD_27x27_fast_I193_un1_Y : NOR2B - port map(A => N541, B => N502, Y => I193_un1_Y); - - un2_resadd_ADD_27x27_fast_I164_Y_i : AO1C - port map(A => N_48, B => N_108, C => - ADD_27x27_fast_I164_Y_i_0, Y => N_33); - - \REG[20]\ : DFN1E0C0 - port map(D => \REG_4[20]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(20)); - - un2_resadd_ADD_27x27_fast_I252_Y_0 : AX1C - port map(A => I209_un1_Y, B => ADD_27x27_fast_I209_Y_2, C - => ADD_27x27_fast_I252_Y_0_0, Y => \un2_resadd[22]\); - - \REG_RNO[8]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_16, Y => \REG_4[8]\); - - \REG_RNO_0[7]\ : MX2C - port map(A => ADDERinB(7), B => \un2_resadd[7]\, S => - add_D_0, Y => N_15); - - un2_resadd_ADD_27x27_fast_I67_Y : MAJ3 - port map(A => ADDERinA(5), B => ADDERinB(5), C => N_52_i_0, - Y => N445); - - \REG_RNO_0[23]\ : MX2C - port map(A => ADDERinB(23), B => \un2_resadd[23]\, S => - add_D, Y => N_31); - - \REG[3]\ : DFN1E0C0 - port map(D => \REG_4[3]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(3)); - - un2_resadd_ADD_27x27_fast_I248_Y_0_0 : XOR2 - port map(A => ADDERinA(18), B => ADDERinB(18), Y => - ADD_27x27_fast_I248_Y_0_0); - - \REG_RNO[3]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_11, Y => \REG_4[3]\); - - un2_resadd_ADD_27x27_fast_I121_Y : AO1 - port map(A => N_47, B => N450, C => N449, Y => N502); - - un2_resadd_ADD_27x27_fast_I113_Y : AO1 - port map(A => N445, B => N442, C => N441, Y => N494); - - \REG[17]\ : DFN1E0C0 - port map(D => \REG_4[17]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(17)); - - un2_resadd_ADD_27x27_fast_I161_Y : AOI1 - port map(A => N502, B => N495, C => N494, Y => N548); - - un2_resadd_ADD_27x27_fast_I22_G0N : NOR2A - port map(A => ADDERinB(22), B => ADDERinA(22), Y => N391); - - un2_resadd_ADD_27x27_fast_I157_Y : AO1A - port map(A => N491, B => N498, C => N490, Y => N544); - - GND_i_0 : GND - port map(Y => GND_0); - - un2_resadd_ADD_27x27_fast_I195_un1_Y : NOR3B - port map(A => N499, B => N_47, C => N491, Y => - ADD_27x27_fast_I195_un1_Y); - - un2_resadd_ADD_27x27_fast_I115_Y : AO1 - port map(A => ADD_27x27_fast_I115_un1_Y_0, B => N444, C => - ADD_27x27_fast_I115_Y_0, Y => N496); - - un2_resadd_ADD_27x27_fast_I89_Y : AO1 - port map(A => N421, B => N418, C => N417, Y => N470); - - \REG_RNO_0[16]\ : MX2C - port map(A => ADDERinB(16), B => \un2_resadd[16]\, S => - add_D, Y => N_24); - - un2_resadd_ADD_27x27_fast_I213_Y_0 : OA1A - port map(A => N482, B => N475, C => N474, Y => - ADD_27x27_fast_I213_Y_0); - - un2_resadd_ADD_27x27_fast_I16_P0N : OR2 - port map(A => ADDERinB(16), B => ADDERinA(16), Y => N374); - - \REG_RNO[16]\ : NOR2 - port map(A => clr_MAC_D, B => N_24, Y => \REG_4[16]\); - - un2_resadd_ADD_27x27_fast_I115_Y_0 : MAJ3 - port map(A => ADDERinA(6), B => ADDERinB(6), C => N340, Y - => ADD_27x27_fast_I115_Y_0); - - un2_resadd_ADD_27x27_fast_I47_Y : AO13 - port map(A => N367, B => ADDERinB(15), C => ADDERinA(15), Y - => N425); - - \REG_RNO_0[0]\ : AX1E - port map(A => ADDERinA(0), B => add_D_0, C => ADDERinB(0), - Y => N_8); - - un2_resadd_ADD_27x27_fast_I114_Y : NOR2B - port map(A => N446, B => N442, Y => N495); - - un2_resadd_ADD_27x27_fast_I251_Y_0 : AX1E - port map(A => N415, B => N_105, C => - ADD_27x27_fast_I251_Y_0_0, Y => \un2_resadd[21]\); - - \REG_RNO[6]\ : NOR2 - port map(A => clr_MAC_D, B => N_14, Y => \REG_4[6]\); - - \REG_RNO[5]\ : NOR2 - port map(A => clr_MAC_D, B => N_13, Y => \REG_4[5]\); - - un2_resadd_ADD_27x27_fast_I56_Y : OA1 - port map(A => ADDERinA(11), B => ADDERinB(11), C => N356, Y - => N434); - - \REG[2]\ : DFN1E0C0 - port map(D => \REG_4[2]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(2)); - - un2_resadd_ADD_27x27_fast_I254_Y_0_0 : XOR2 - port map(A => ADDERinA(24), B => ADDERinB(24), Y => - ADD_27x27_fast_I254_Y_0_0); - - un2_resadd_ADD_27x27_fast_I10_P0N : OR2 - port map(A => ADDERinB(10), B => ADDERinA(10), Y => N356); - - \REG_RNO[23]\ : NOR2 - port map(A => clr_MAC_D, B => N_31, Y => \REG_4[23]\); - - un2_resadd_ADD_27x27_fast_I130_Y : NOR2 - port map(A => N471, B => N463, Y => N517); - - un2_resadd_ADD_27x27_fast_I209_Y_1 : OA1 - port map(A => N467_i, B => N474, C => - ADD_27x27_fast_I209_Y_0, Y => ADD_27x27_fast_I209_Y_1); - - \REG[7]\ : DFN1E0C0 - port map(D => \REG_4[7]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(7)); - - un2_resadd_ADD_27x27_fast_I211_Y_1 : AOI1B - port map(A => N540, B => N525, C => ADD_27x27_fast_I211_Y_0, - Y => ADD_27x27_fast_I211_Y_1); - - un2_resadd_ADD_27x27_fast_I61_Y_0_o2 : AO1 - port map(A => N350, B => N346, C => N349, Y => N439); - - \REG_RNO[10]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_18, Y => \REG_4[10]\); - - \REG[4]\ : DFN1E0C0 - port map(D => \REG_4[4]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(4)); - - \REG[10]\ : DFN1E0C0 - port map(D => \REG_4[10]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(10)); - - un2_resadd_ADD_27x27_fast_I243_Y_0_0 : XOR2 - port map(A => ADDERinA(13), B => ADDERinB(13), Y => - ADD_27x27_fast_I243_Y_0_0); - - un2_resadd_ADD_27x27_fast_I208_Y_3 : AOI1B - port map(A => N534, B => N519, C => ADD_27x27_fast_I208_Y_2, - Y => ADD_27x27_fast_I208_Y_3); - - un2_resadd_ADD_27x27_fast_I192_Y_0_a2 : OA1 - port map(A => I193_un1_Y, B => N540, C => N362, Y => - ADD_27x27_fast_I192_Y_0_a2); - - un2_resadd_ADD_27x27_fast_I190_Y : OR2 - port map(A => N534, B => I190_un1_Y, Y => N651); - - un2_resadd_ADD_27x27_fast_I18_P0N : OR2 - port map(A => ADDERinB(18), B => ADDERinA(18), Y => N380); - - un2_resadd_ADD_27x27_fast_I207_un1_Y : OR3B - port map(A => N533, B => N517, C => N548, Y => I207_un1_Y); - - un2_resadd_ADD_27x27_fast_I59_Y : MAJ3 - port map(A => ADDERinA(9), B => ADDERinB(9), C => N349, Y - => N437); - - un2_resadd_ADD_27x27_fast_I251_Y_0_0 : XOR2 - port map(A => ADDERinA(21), B => ADDERinB(21), Y => - ADD_27x27_fast_I251_Y_0_0); - - un2_resadd_ADD_27x27_fast_I208_un1_Y : OR3C - port map(A => N519, B => N535, C => N550, Y => I208_un1_Y); - - \REG_RNO[17]\ : NOR2 - port map(A => clr_MAC_D, B => N_25, Y => \REG_4[17]\); - - un1_clr_1 : NOR3 - port map(A => add_D_0, B => MACMUX2sel_D, C => clr_MAC_D_0, - Y => \un1_clr_1\); - - un2_resadd_ADD_27x27_fast_I98_Y : OR2B - port map(A => N430, B => N426, Y => N479); - - un2_resadd_ADD_27x27_fast_I12_P0N : OR2 - port map(A => ADDERinB(12), B => ADDERinA(12), Y => N362); - - un2_resadd_ADD_27x27_fast_I117_Y : AO1 - port map(A => N449, B => N446, C => N445, Y => N498); - - un2_resadd_ADD_27x27_fast_I64_Y : OA1 - port map(A => ADDERinA(7), B => ADDERinB(7), C => N344, Y - => N442); - - \REG[8]\ : DFN1E0C0 - port map(D => \REG_4[8]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(8)); - - un2_resadd_ADD_27x27_fast_I240_Y_0 : AX1D - port map(A => ADD_27x27_fast_I195_un1_Y, B => N544, C => - ADD_27x27_fast_I240_Y_0_0, Y => \un2_resadd[10]\); - - un2_resadd_ADD_27x27_fast_I0_CO1 : OR2B - port map(A => ADDERinB(0), B => ADDERinA(0), Y => N325); - - un2_resadd_ADD_27x27_fast_I38_Y_i : OAI1 - port map(A => ADDERinA(19), B => ADDERinB(19), C => N386, Y - => N_43); - - un2_resadd_ADD_27x27_fast_I34_Y : OA1 - port map(A => ADDERinA(21), B => ADDERinB(21), C => N392, Y - => N412); - - un2_resadd_ADD_27x27_fast_I105_Y : AO1 - port map(A => N437, B => N434, C => N433, Y => N486); - - \REG_RNO_0[3]\ : MX2C - port map(A => ADDERinB(3), B => \un2_resadd[3]\, S => - add_D_0, Y => N_11); - - un2_resadd_ADD_27x27_fast_I50_Y : OA1 - port map(A => ADDERinA(14), B => ADDERinB(14), C => N365, Y - => N428); - - un2_resadd_ADD_27x27_fast_I239_Y_0 : AX1E - port map(A => N_78_i, B => ADD_27x27_fast_I196_Y_0_0, C => - ADD_27x27_fast_I239_Y_0_0, Y => \un2_resadd[9]\); - - \REG[24]\ : DFN1E0C0 - port map(D => \REG_4[24]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1\, Q => ADDERout(24)); - - un2_resadd_ADD_27x27_fast_I3_P0N_i_o2 : OR2 - port map(A => ADDERinB(3), B => ADDERinA(3), Y => N_58); - - un2_resadd_ADD_27x27_fast_I15_P0N : OR2A - port map(A => ADDERinA(15), B => ADDERinB(15), Y => N371); - - un2_resadd_ADD_27x27_fast_I249_Y_0 : AX1D - port map(A => I212_un1_Y, B => ADD_27x27_fast_I212_Y_1, C - => ADD_27x27_fast_I249_Y_0_0, Y => \un2_resadd[19]\); - - un2_resadd_ADD_27x27_fast_I189_Y : AO1C - port map(A => N548, B => N533, C => N532, Y => N648); - - un2_resadd_ADD_27x27_fast_I4_G0N_i_o2 : NOR2B - port map(A => ADDERinB(4), B => ADDERinA(4), Y => N_52_i_0); - - un2_resadd_ADD_27x27_fast_I250_Y_0_0 : XOR2 - port map(A => ADDERinA(20), B => ADDERinB(20), Y => - ADD_27x27_fast_I250_Y_0_0); - - \REG_RNO_0[12]\ : MX2C - port map(A => ADDERinB(12), B => \un2_resadd[12]\, S => - add_D, Y => N_20); - - un2_resadd_ADD_27x27_fast_I44_Y : OA1A - port map(A => ADDERinA(17), B => ADDERinB(17), C => N374, Y - => N422); - - un2_resadd_ADD_27x27_fast_I233_Y_0 : XOR3 - port map(A => ADDERinB(3), B => ADDERinA(3), C => N_48, Y - => \un2_resadd[3]\); - - un2_resadd_ADD_27x27_fast_I194_un1_Y : NOR2B - port map(A => N_48, B => N543, Y => - ADD_27x27_fast_I194_un1_Y); - - un2_resadd_ADD_27x27_fast_I243_Y_0 : AX1A - port map(A => ADD_27x27_fast_I192_Y_0_a2, B => N361, C => - ADD_27x27_fast_I243_Y_0_0, Y => \un2_resadd[13]\); - - un2_resadd_ADD_27x27_fast_I146_Y : NOR2 - port map(A => N487, B => N479, Y => N533); - - \REG_RNO_0[14]\ : MX2C - port map(A => ADDERinB(14), B => \un2_resadd[14]\, S => - add_D_0, Y => N_22); - - \REG[16]\ : DFN1E0C0 - port map(D => \REG_4[16]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(16)); - - un2_resadd_ADD_27x27_fast_I62_Y_i_o2 : OAI1 - port map(A => ADDERinA(7), B => ADDERinB(7), C => N350, Y - => N_73); - - un2_resadd_ADD_27x27_fast_I102_Y : OR2B - port map(A => N434, B => N430, Y => N483); - - \REG_RNO_0[4]\ : MX2C - port map(A => ADDERinB(4), B => \un2_resadd[4]\, S => - add_D_0, Y => N_12); - - un2_resadd_ADD_27x27_fast_I20_G0N : NOR2B - port map(A => ADDERinB(20), B => ADDERinA(20), Y => N385); - - \REG_RNO_0[2]\ : MX2C - port map(A => ADDERinB(2), B => \un2_resadd[2]\, S => add_D, - Y => N_10); - - un2_resadd_ADD_27x27_fast_I82_Y : OR2B - port map(A => N414, B => N410, Y => N463); - - un2_resadd_ADD_27x27_fast_I234_Y_0 : XOR3 - port map(A => ADDERinB(4), B => ADDERinA(4), C => N502, Y - => \un2_resadd[4]\); - - un2_resadd_ADD_27x27_fast_I250_Y_0 : AX1E - port map(A => I211_un1_Y_i, B => ADD_27x27_fast_I211_Y_1, C - => ADD_27x27_fast_I250_Y_0_0, Y => \un2_resadd[20]\); - - un2_resadd_ADD_27x27_fast_I252_Y_0_0 : XOR2 - port map(A => ADDERinA(22), B => ADDERinB(22), Y => - ADD_27x27_fast_I252_Y_0_0); - - un2_resadd_ADD_27x27_fast_I244_Y_0 : XNOR3 - port map(A => ADDERinB(14), B => ADDERinA(14), C => N654_i, - Y => \un2_resadd[14]\); - - un2_resadd_ADD_27x27_fast_I69_Y_i_a2 : NOR2 - port map(A => N_59, B => N_52_i_0, Y => N_108); - - un2_resadd_ADD_27x27_fast_I18_G0N : NOR2B - port map(A => ADDERinB(18), B => ADDERinA(18), Y => N379); - - un2_resadd_ADD_27x27_fast_I13_G0N : NOR2B - port map(A => ADDERinB(13), B => ADDERinA(13), Y => N364); - - \REG_RNO_0[5]\ : MX2C - port map(A => ADDERinB(5), B => \un2_resadd[5]\, S => add_D, - Y => N_13); - - \REG[21]\ : DFN1E0C0 - port map(D => \REG_4[21]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1\, Q => ADDERout(21)); - - un2_resadd_ADD_27x27_fast_I237_Y_0 : XOR3 - port map(A => ADDERinB(7), B => ADDERinA(7), C => N550, Y - => \un2_resadd[7]\); - - \REG_RNO_0[22]\ : MX2C - port map(A => ADDERinB(22), B => \un2_resadd[22]\, S => - add_D_0, Y => N_30); - - un2_resadd_ADD_27x27_fast_I107_Y : AO1B - port map(A => N439, B => N436, C => ADD_27x27_fast_I107_Y_0, - Y => N488); - - un2_resadd_ADD_27x27_fast_I247_Y_0 : AX1 - port map(A => N423, B => N_98_i, C => - ADD_27x27_fast_I247_Y_0_0, Y => \un2_resadd[17]\); - - \REG_RNO[0]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_8, Y => \REG_4[0]\); - - \REG_RNO_0[15]\ : MX2C - port map(A => ADDERinB(15), B => \un2_resadd[15]\, S => - add_D_0, Y => N_23); - - un2_resadd_ADD_27x27_fast_I148_Y : NOR2 - port map(A => N489, B => N481, Y => N535); - - \REG_RNO_0[24]\ : MX2C - port map(A => ADDERinB(24), B => \un2_resadd[24]\, S => - add_D, Y => N_32); - - un2_resadd_ADD_27x27_fast_I253_Y_0 : AX1E - port map(A => I208_un1_Y, B => ADD_27x27_fast_I208_Y_3, C - => ADD_27x27_fast_I253_Y_0_0, Y => \un2_resadd[23]\); - - un2_resadd_ADD_27x27_fast_I213_un1_Y_0 : NOR3B - port map(A => N499, B => N_47, C => N491, Y => - ADD_27x27_fast_I213_un1_Y_0); - - \REG[15]\ : DFN1E0C0 - port map(D => \REG_4[15]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(15)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_MUX2 is - - port( MULTout_D : in std_logic_vector(24 downto 7); - ADDERout : in std_logic_vector(24 downto 7); - sample_out_s : out std_logic_vector(17 downto 0); - MACMUX2sel_D_D : in std_logic - ); - -end MAC_MUX2; - -architecture DEF_ARCH of MAC_MUX2 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \RES[19]\ : MX2 - port map(A => ADDERout(19), B => MULTout_D(19), S => - MACMUX2sel_D_D, Y => sample_out_s(12)); - - \RES[9]\ : MX2 - port map(A => ADDERout(9), B => MULTout_D(9), S => - MACMUX2sel_D_D, Y => sample_out_s(2)); - - GND_i_0 : GND - port map(Y => GND_0); - - \RES[12]\ : MX2 - port map(A => ADDERout(12), B => MULTout_D(12), S => - MACMUX2sel_D_D, Y => sample_out_s(5)); - - VCC_i : VCC - port map(Y => \VCC\); - - \RES[17]\ : MX2 - port map(A => ADDERout(17), B => MULTout_D(17), S => - MACMUX2sel_D_D, Y => sample_out_s(10)); - - \RES[22]\ : MX2 - port map(A => ADDERout(22), B => MULTout_D(22), S => - MACMUX2sel_D_D, Y => sample_out_s(15)); - - \RES[11]\ : MX2 - port map(A => ADDERout(11), B => MULTout_D(11), S => - MACMUX2sel_D_D, Y => sample_out_s(4)); - - \RES[18]\ : MX2 - port map(A => ADDERout(18), B => MULTout_D(18), S => - MACMUX2sel_D_D, Y => sample_out_s(11)); - - \RES[21]\ : MX2 - port map(A => ADDERout(21), B => MULTout_D(21), S => - MACMUX2sel_D_D, Y => sample_out_s(14)); - - \RES[14]\ : MX2 - port map(A => ADDERout(14), B => MULTout_D(14), S => - MACMUX2sel_D_D, Y => sample_out_s(7)); - - GND_i : GND - port map(Y => \GND\); - - \RES[24]\ : MX2 - port map(A => ADDERout(24), B => MULTout_D(24), S => - MACMUX2sel_D_D, Y => sample_out_s(17)); - - \RES[10]\ : MX2 - port map(A => ADDERout(10), B => MULTout_D(10), S => - MACMUX2sel_D_D, Y => sample_out_s(3)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \RES[8]\ : MX2 - port map(A => ADDERout(8), B => MULTout_D(8), S => - MACMUX2sel_D_D, Y => sample_out_s(1)); - - \RES[16]\ : MX2 - port map(A => ADDERout(16), B => MULTout_D(16), S => - MACMUX2sel_D_D, Y => sample_out_s(9)); - - \RES[20]\ : MX2 - port map(A => ADDERout(20), B => MULTout_D(20), S => - MACMUX2sel_D_D, Y => sample_out_s(13)); - - \RES[13]\ : MX2 - port map(A => ADDERout(13), B => MULTout_D(13), S => - MACMUX2sel_D_D, Y => sample_out_s(6)); - - \RES[7]\ : MX2 - port map(A => ADDERout(7), B => MULTout_D(7), S => - MACMUX2sel_D_D, Y => sample_out_s(0)); - - \RES[23]\ : MX2 - port map(A => ADDERout(23), B => MULTout_D(23), S => - MACMUX2sel_D_D, Y => sample_out_s(16)); - - \RES[15]\ : MX2 - port map(A => ADDERout(15), B => MULTout_D(15), S => - MACMUX2sel_D_D, Y => sample_out_s(8)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_2 is - - port( MACMUXsel_D : out std_logic; - MACMUXsel_D_0 : out std_logic; - N_4 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - MACMUXsel_D_1 : out std_logic - ); - -end MAC_REG_1_2; - -architecture DEF_ARCH of MAC_REG_1_2 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_1[0]\ : DFN1C0 - port map(D => N_4, CLK => lclk_c, CLR => rstn, Q => - MACMUXsel_D_1); - - \Q_0[0]\ : DFN1C0 - port map(D => N_4, CLK => lclk_c, CLR => rstn, Q => - MACMUXsel_D_0); - - \Q[0]\ : DFN1C0 - port map(D => N_4, CLK => lclk_c, CLR => rstn, Q => - MACMUXsel_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Multiplier is - - port( MULTout : out std_logic_vector(24 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - mult : in std_logic; - mult_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end Multiplier; - -architecture DEF_ARCH of Multiplier is - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal I118_un1_Y, N398, N405, N397_i, I78_un1_Y_i, N352, - ADD_22x22_fast_I153_Y_0, ADD_22x22_fast_I209_Y_0_2, N_252, - ADD_22x22_fast_I209_Y_0_0, N_254, \a17_b_i[7]\, - ADD_22x22_fast_I207_Y_0_0, madd_583_0, madd_572, - ADD_22x22_fast_I206_Y_0_0, madd_568_0, madd_552, - ADD_22x22_fast_I172_Y_2, N453, N438, - ADD_22x22_fast_I172_Y_1, N399, N392, - ADD_22x22_fast_I172_Y_0, I72_un1_Y, - ADD_22x22_fast_I30_un1_Y, N321, ADD_22x22_fast_I170_Y_2, - I68_un1_Y, ADD_22x22_fast_I170_Y_0, I108_un1_Y, N324, - madd_587, N_253, ADD_22x22_fast_I171_Y_1, N348, N345, - ADD_22x22_fast_I171_Y_0, ADD_22x22_fast_I173_Y_2, N455, - N440, ADD_22x22_fast_I173_Y_1, N401, N394, - ADD_22x22_fast_I173_Y_0, N349, ADD_22x22_fast_I199_Y_0_0, - madd_347_0, madd_311, ADD_22x22_fast_I152_Y_0, N403, N396, - N395, ADD_22x22_fast_I170_Y_3_0, N388, - ADD_22x22_fast_I153_un1_Y_0, N568, N406, - ADD_22x22_fast_I196_Y_0_0, madd_200, madd_236_0, - ADD_22x22_fast_I155_un1_Y_0, N417, I135_un1_Y, N402, - ADD_22x22_fast_I194_Y_0_0, madd_124, madd_157_0, madd_126, - madd_194_0_0, N_81_i, madd_194_12, madd_416_0_0, - madd_416_8, N_179, madd_231_0_0, N_97_i, madd_231_12, - madd_268_0_0, N_113_i, madd_268_12, madd_342_0_0, N_145_i, - madd_342_12, madd_305_0_0, N_129_i, madd_305_12, - madd_194_12_0, madd_194_10, madd_151, madd_231_12_0, - N_82_i, madd_231_10, madd_194_10_0, madd_131, madd_136, - madd_578_0_0, madd_573_0, madd_305_8_0, madd_305_2, - madd_305_4, madd_493_6_0, \a11_b[7]\, \a_i10_b[8]\, - madd_543_2_0, \a16_b[4]\, \a15_b[5]\, madd_342_4_0, - \a11_b[3]\, \a9_b[5]\, madd_305_4_0, \a10_b[3]\, - \a8_b[5]\, madd_305_7_0, \a7_b[6]\, \a6_b[7]\, - madd_268_4_0, \a9_b[3]\, \a7_b[5]\, madd_39_2_0, - \a5_b[0]\, \a3_b[2]\, madd_342_2_0, \a14_b[0]\, - \a12_b[2]\, madd_305_2_0, \a13_b[0]\, \a11_b[2]\, - madd_268_2_0, \a12_b[0]\, \a10_b[2]\, madd_157_7_0, - \a3_b[6]\, \a2_b[7]\, madd_0_s_0, \a2_b[0]\, \a1_b[1]\, - madd_39_4_0, \a2_b[3]\, \a1_b[4]\, N544, I155_un1_Y, N365, - N369, N550, I122_un1_Y, I172_un1_Y, N454, N378, - I173_un1_Y, N456, madd_28, N535, I110_un1_Y, - ADD_22x22_fast_I171_Y_3, I152_un1_Y, N565, N404, N541, - I154_un1_Y, N400, N408, N461, N547, I120_un1_Y, N_251, - \a16_b[7]\, \a_i15_b[8]\, \a17_b_i[6]\, madd_416_0, - madd_378, N_175_i, madd_358, N_154_i, madd_363, madd_368, - madd_373, N_57, \a7_b[2]\, \a9_b[0]\, \a8_b[1]\, N_59_i, - \a4_b[5]\, \a6_b[3]\, \a5_b[4]\, madd_157_11, N_48, - madd_115_0, N_47, N_45_i, madd_82, \a3_b[5]\, \a5_b[3]\, - \a4_b[4]\, \a1_b[7]\, \a2_b[6]\, \a0_b[8]\, madd_39_0, - madd_39_2, N_15, N_8, \a0_b[5]\, N_7_i, \a2_b[2]\, - \a4_b[0]\, \a3_b[1]\, \RESMULT[23]\, \RESMULT[22]\, - \RESMULT[21]\, \RESMULT[20]\, madd_527, madd_548_0, - \RESMULT[19]\, madd_497, madd_523_0, \RESMULT[18]\, - madd_462, madd_493_0, \RESMULT[17]\, madd_458_0, madd_422, - \RESMULT[16]\, madd_385, madd_421_0, N553_i, - \RESMULT[15]\, madd_348, madd_384_0, N556_i, - \RESMULT[14]\, ADD_22x22_fast_I158_un1_Y, \RESMULT[13]\, - madd_274, madd_310_0, N562_i, \RESMULT[12]\, madd_237, - madd_273_0, \RESMULT[11]\, \RESMULT[10]\, madd_163, - madd_199_0, \RESMULT[9]\, \RESMULT[8]\, madd_125_0, - madd_120_0, N419, \RESMULT[7]\, madd_93_0, madd_67, N421, - \RESMULT[6]\, madd_66_0, madd_61_0, \RESMULT[5]\, CO3, - madd_44_0, \RESMULT[24]\, ADD_22x22_fast_I170_Y_3, - madd_577, madd_582, madd_543_4, \a13_b[7]\, \a14_b[6]\, - \a_i12_b[8]\, \a16_b[6]\, \a15_b[7]\, \a17_b_i[5]\, - madd_458_2, \a16_b[1]\, madd_458_14, madd_458_9, - madd_458_10, madd_415, madd_458_13, madd_405, madd_458_7, - madd_410, madd_458_4, madd_400, madd_390, \a_i9_b[8]\, - madd_395, \a10_b[7]\, \a12_b[5]\, \a11_b[6]\, \a13_b[4]\, - \a15_b[2]\, \a14_b[3]\, madd_420, madd_4_0, \a1_b[2]\, - \a3_b[0]\, \a2_b[1]\, madd_9_0, \a0_b[3]\, madd_3, - madd_24_4, \a0_b[4]\, \a1_b[3]\, madd_8, madd_24_0, - madd_13, \a4_b[1]\, madd_61_4, \a1_b[5]\, \a3_b[3]\, - \a2_b[4]\, madd_61_2, \a4_b[2]\, \a6_b[0]\, \a5_b[1]\, - madd_43, madd_56_0, madd_33, \a0_b[6]\, madd_38, - madd_88_8, madd_88_4, madd_88_2, madd_55, madd_88_7, - \a0_b[7]\, \a1_b[6]\, madd_50, \a2_b[5]\, \a4_b[3]\, - \a3_b[4]\, \a5_b[2]\, \a7_b[0]\, \a6_b[1]\, madd_88_0, - madd_60, madd_95_0, \a6_b[2]\, \a8_b[0]\, \a7_b[1]\, - madd_110_0, madd_72, madd_77, N_38_i, madd_92, - madd_157_12, madd_157_9, madd_157_7, madd_114, madd_99, - \a_i0_b[8]\, madd_104, \a_i1_b[8]\, madd_119, madd_146, - madd_141, madd_194_4, madd_194_2, madd_194_7, \a3_b[7]\, - \a4_b[6]\, \a_i2_b[8]\, \a5_b[5]\, \a7_b[3]\, \a6_b[4]\, - \a8_b[2]\, \a10_b[0]\, \a9_b[1]\, madd_183, madd_173, - N_74_i, madd_178, madd_231_4, madd_231_2, madd_231_7, - \a4_b[7]\, \a5_b[6]\, \a_i3_b[8]\, \a6_b[5]\, \a8_b[3]\, - \a7_b[4]\, \a9_b[2]\, \a11_b[0]\, \a10_b[1]\, madd_268_10, - N_98_i, madd_220, madd_210, N_90_i, madd_215, madd_268_4, - madd_268_2, madd_268_7, \a5_b[7]\, \a6_b[6]\, \a_i4_b[8]\, - \a8_b[4]\, \a11_b[1]\, madd_305_10, N_114_i, madd_257, - madd_247, N_106_i, madd_252, madd_305_7, \a_i5_b[8]\, - \a9_b[4]\, \a12_b[1]\, madd_342_10, N_130_i, madd_294, - madd_284, N_122_i, madd_289, madd_342_4, madd_342_2, - madd_342_7, \a7_b[7]\, \a8_b[6]\, \a_i6_b[8]\, \a10_b[4]\, - \a13_b[1]\, madd_379_12, madd_379_10, madd_336, madd_331, - madd_321, N_138_i, madd_326, N_161_i, madd_379_4, - madd_379_2, madd_379_7, \a8_b[7]\, \a9_b[6]\, \a_i7_b[8]\, - \a10_b[5]\, \a12_b[3]\, \a11_b[4]\, \a13_b[2]\, - \a15_b[0]\, \a14_b[1]\, madd_379_0, madd_341, madd_416_4, - madd_416_2, madd_416_7, \a9_b[7]\, \a10_b[6]\, - \a_i8_b[8]\, \a11_b[5]\, \a13_b[3]\, \a12_b[4]\, - \a14_b[2]\, \a16_b[0]\, \a15_b[1]\, madd_493_12, - madd_493_8, madd_493_6, madd_452, madd_493_11, madd_442, - madd_493_4, madd_447, madd_432, madd_493_2, madd_437, - madd_427_1, \a12_b[6]\, \a14_b[4]\, \a13_b[5]\, - \a15_b[3]\, \a16_b[2]\, \a17_b_i[1]\, madd_457, - madd_523_10, madd_482, madd_523_7, madd_487, madd_523_8, - madd_523_4, madd_523_2, madd_477, madd_472, \a_i11_b[8]\, - madd_467, \a12_b[7]\, \a14_b[5]\, \a13_b[6]\, \a15_b[4]\, - \a16_b[3]\, \a17_b_i[2]\, madd_492, madd_543_6, madd_507, - madd_543_2, madd_502, \a17_b_i[3]\, madd_543_0, madd_512, - madd_517, madd_522, madd_568_6, madd_537, madd_568_2, - madd_542, madd_568_4, \a_i13_b[8]\, \a14_b[7]\, madd_532, - \a15_b[6]\, \a16_b[5]\, \a17_b_i[4]\, madd_547, - madd_578_0, madd_557, madd_562, madd_567, - ADD_22x22_fast_I170_un1_Y_0, N449, N390, - ADD_22x22_fast_I171_Y_3_tz, N452, N451, madd_582_0, - madd_582_0_tz, N450, madd_334, madd_383, madd_346, - madd_304, madd_309, madd_267, madd_272, madd_230, - madd_235, madd_193, madd_198, madd_156, madd_161, madd_65, - madd_23, \a0_b[2]\, CO0, \a1_b[0]\, CO2, CO1, - \RESMULT[1]\, \RESMULT[3]\, \RESMULT[4]\, N276, N277, - N319, N322, N350, ADD_22x22_fast_I90_un1_Y, N368, N413, - N372, N376, N373, N418, N377, I101_un1_Y, N364, - I130_un1_Y, I157_un1_Y, N343, I76_un1_Y, N411, N412, N351, - \RESMULT[0]\, N328, \RESMULT[2]\, N416, N375, N371, N295, - N298, N367, N407, N362, I88_un1_Y, N359, N355, N280, N286, - N292, N289, N366, N288, N304, N301, N358, N303, I42_un1_Y, - N310, N307, N316, N313, N415, N374, N370, I38_un1_Y_i, - I80_un1_Y_i, N309, I54_un1_Y_i, N285, N282, N312, N325, - N315, N361, N360, N297, I133_un1_Y, I126_un1_Y, N357, - N356, N353, N274, N273, N279, I48_un1_Y_i, N294, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - RESMULT_madd_606_ADD_22x22_fast_I68_un1_Y : OAI1 - port map(A => ADD_22x22_fast_I30_un1_Y, B => N321, C => - N343, Y => I68_un1_Y); - - RESMULT_madd_120_0 : XOR3 - port map(A => N_38_i, B => madd_110_0, C => madd_92, Y => - madd_120_0); - - RESMULT_madd_452 : MAJ3 - port map(A => madd_458_7, B => madd_405, C => madd_410, Y - => madd_452); - - \RESMULT_a9_b[1]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(1), Y => - \a9_b[1]\); - - RESMULT_madd_65 : MIN3 - port map(A => madd_61_2, B => madd_43, C => madd_61_4, Y - => madd_65); - - RESMULT_madd_420 : MAJ3 - port map(A => madd_416_8, B => madd_378, C => N_179, Y => - madd_420); - - RESMULT_madd_523_0 : XOR3 - port map(A => madd_523_10, B => madd_523_8, C => madd_492, - Y => madd_523_0); - - \RESMULT_a4_b[2]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(2), Y => - \a4_b[2]\); - - RESMULT_madd_552 : MIN3 - port map(A => madd_517, B => madd_522, C => madd_543_0, Y - => madd_552); - - RESMULT_madd_231_0_0 : XOR2 - port map(A => N_97_i, B => madd_231_12, Y => madd_231_0_0); - - \RESMULT_a9_b[4]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(4), Y => - \a9_b[4]\); - - RESMULT_madd_267 : AO13 - port map(A => madd_220, B => N_98_i, C => madd_268_10, Y - => madd_267); - - \RESMULT_a11_b[5]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(5), Y => - \a11_b[5]\); - - \RESMULT_a10_b[7]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(7), Y => - \a10_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I58_Y : MAJ3 - port map(A => madd_67, B => madd_93_0, C => N276, Y => N374); - - RESMULT_madd_606_ADD_22x22_fast_I55_Y : OA1 - port map(A => madd_120_0, B => madd_125_0, C => N286, Y => - N371); - - RESMULT_madd_606_ADD_22x22_fast_I99_Y : OR2B - port map(A => N377, B => N373, Y => N418); - - RESMULT_madd_146 : MAJ3 - port map(A => \a_i0_b[8]\, B => madd_99, C => madd_104, Y - => madd_146); - - RESMULT_madd_378 : MAJ3 - port map(A => madd_336, B => madd_331, C => madd_379_10, Y - => madd_378); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_0 : OA1C - port map(A => N352, B => N349, C => N348, Y => - ADD_22x22_fast_I173_Y_0); - - \RESMULT_a11_b[0]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(0), Y => - \a11_b[0]\); - - \RESMULT_a13_b[7]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(7), Y => - \a13_b[7]\); - - RESMULT_madd_43 : MAJ3 - port map(A => N_15, B => N_8, C => madd_39_2, Y => madd_43); - - RESMULT_madd_310_0 : XNOR3 - port map(A => madd_267, B => madd_305_0_0, C => madd_272, Y - => madd_310_0); - - RESMULT_madd_141 : MAJ3 - port map(A => \a3_b[6]\, B => \a2_b[7]\, C => \a_i1_b[8]\, - Y => madd_141); - - \RESMULT_a7_b[7]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(7), Y => - \a7_b[7]\); - - RESMULT_madd_235 : AO13 - port map(A => madd_193, B => N_97_i, C => madd_231_12, Y - => madd_235); - - RESMULT_madd_38 : MAJ3 - port map(A => \a2_b[3]\, B => \a0_b[5]\, C => \a1_b[4]\, Y - => madd_38); - - \REG[6]\ : DFN1E1C0 - port map(D => \RESMULT[6]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(6)); - - RESMULT_madd_231_12_0 : XOR2 - port map(A => N_82_i, B => madd_231_10, Y => madd_231_12_0); - - RESMULT_madd_200 : XA1B - port map(A => madd_156, B => madd_194_0_0, C => madd_161, Y - => madd_200); - - RESMULT_madd_104 : MAJ3 - port map(A => \a5_b[3]\, B => \a3_b[5]\, C => \a4_b[4]\, Y - => madd_104); - - \RESMULT_a14_b[7]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(7), Y => - \a14_b[7]\); - - \RESMULT_a6_b[7]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(7), Y => - \a6_b[7]\); - - \RESMULT_a0_b[3]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(3), Y => - \a0_b[3]\); - - \RESMULT_a4_b[3]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(3), Y => - \a4_b[3]\); - - \RESMULT_a15_b[4]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(4), Y => - \a15_b[4]\); - - RESMULT_madd_247 : MIN3 - port map(A => \a9_b[3]\, B => \a7_b[5]\, C => \a8_b[4]\, Y - => madd_247); - - RESMULT_madd_93_0 : XNOR2 - port map(A => madd_88_0, B => madd_65, Y => madd_93_0); - - RESMULT_madd_606_ADD_22x22_fast_I122_un1_Y : OAI1 - port map(A => ADD_22x22_fast_I90_un1_Y, B => N364, C => - N402, Y => I122_un1_Y); - - RESMULT_madd_523_8 : XOR3 - port map(A => madd_523_4, B => madd_523_2, C => madd_477, Y - => madd_523_8); - - \RESMULT_a16_b[7]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(7), Y => - \a16_b[7]\); - - RESMULT_madd_458_0 : XOR3 - port map(A => madd_458_14, B => madd_458_13, C => madd_420, - Y => madd_458_0); - - RESMULT_madd_61_0 : XOR3 - port map(A => madd_61_4, B => madd_61_2, C => madd_43, Y - => madd_61_0); - - \RESMULT_a9_b[0]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(0), Y => - \a9_b[0]\); - - \RESMULT_a6_b[1]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(1), Y => - \a6_b[1]\); - - \RESMULT_a13_b[0]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(0), Y => - \a13_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I73_Y : NOR3C - port map(A => N319, B => N322, C => N351, Y => N392); - - RESMULT_madd_507 : MAJ3 - port map(A => \a14_b[5]\, B => \a12_b[7]\, C => \a13_b[6]\, - Y => madd_507); - - RESMULT_madd_606_ADD_22x22_fast_I155_un1_Y : OR3C - port map(A => N365, B => N369, C => - ADD_22x22_fast_I155_un1_Y_0, Y => I155_un1_Y); - - RESMULT_madd_458_10 : XOR3 - port map(A => madd_458_4, B => madd_458_2, C => madd_400, Y - => madd_458_10); - - RESMULT_madd_252 : MIN3 - port map(A => \a6_b[6]\, B => \a5_b[7]\, C => \a_i4_b[8]\, - Y => madd_252); - - RESMULT_madd_472 : MAJ3 - port map(A => \a14_b[4]\, B => \a12_b[6]\, C => \a13_b[5]\, - Y => madd_472); - - RESMULT_madd_67 : NOR3B - port map(A => madd_39_0, B => madd_56_0, C => madd_23, Y - => madd_67); - - RESMULT_madd_95_0 : XOR3 - port map(A => \a6_b[2]\, B => \a8_b[0]\, C => \a7_b[1]\, Y - => madd_95_0); - - \REG[18]\ : DFN1E1C0 - port map(D => \RESMULT[18]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(18)); - - RESMULT_madd_568_4 : XOR3 - port map(A => \a_i13_b[8]\, B => \a14_b[7]\, C => madd_532, - Y => madd_568_4); - - \RESMULT_a1_b[6]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(6), Y => - \a1_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I197_Y_0 : XOR3 - port map(A => madd_237, B => madd_273_0, C => N565, Y => - \RESMULT[12]\); - - RESMULT_madd_572 : MAJ3 - port map(A => madd_568_4, B => madd_547, C => madd_568_6, Y - => madd_572); - - \RESMULT_a7_b[0]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(0), Y => - \a7_b[0]\); - - RESMULT_madd_88_4 : XOR3 - port map(A => \a2_b[5]\, B => \a4_b[3]\, C => \a3_b[4]\, Y - => madd_88_4); - - RESMULT_madd_72 : MAJ3 - port map(A => \a7_b[0]\, B => \a5_b[2]\, C => \a6_b[1]\, Y - => madd_72); - - RESMULT_madd_230 : AO13 - port map(A => madd_183, B => N_82_i, C => madd_231_10, Y - => madd_230); - - RESMULT_madd_88_8 : XOR3 - port map(A => madd_88_4, B => madd_88_2, C => madd_55, Y - => madd_88_8); - - RESMULT_madd_606_ADD_22x22_fast_I80_un1_Y : OR2B - port map(A => N358, B => N355, Y => I80_un1_Y_i); - - RESMULT_madd_66_0 : AX1 - port map(A => madd_23, B => madd_39_0, C => madd_56_0, Y - => madd_66_0); - - RESMULT_madd_606_ADD_22x22_fast_I204_Y_0 : XNOR3 - port map(A => madd_497, B => madd_523_0, C => N544, Y => - \RESMULT[19]\); - - RESMULT_madd_606_ADD_22x22_fast_I131_Y : NOR3B - port map(A => N365, B => N369, C => N418, Y => N456); - - RESMULT_madd_231_12 : XOR2 - port map(A => madd_231_12_0, B => madd_183, Y => - madd_231_12); - - RESMULT_madd_194_4 : XOR3 - port map(A => \a5_b[5]\, B => \a7_b[3]\, C => \a6_b[4]\, Y - => madd_194_4); - - RESMULT_madd_458_2 : AX1E - port map(A => alu_coef_s(0), B => alu_sample(17), C => - \a16_b[1]\, Y => madd_458_2); - - \RESMULT_a_i13_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(13), Y => - \a_i13_b[8]\); - - \REG[19]\ : DFN1E1C0 - port map(D => \RESMULT[19]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(19)); - - \RESMULT_a6_b[0]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(0), Y => - \a6_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I34_Y : AO13 - port map(A => N312, B => madd_523_0, C => madd_497, Y => - N350); - - RESMULT_madd_606_ADD_22x22_fast_I5_P0N : OR2 - port map(A => madd_199_0, B => madd_163, Y => N289); - - RESMULT_madd_606_ADD_22x22_fast_I83_Y : NOR2B - port map(A => N361, B => N357, Y => N402); - - RESMULT_madd_537 : MAJ3 - port map(A => \a14_b[6]\, B => \a13_b[7]\, C => - \a_i12_b[8]\, Y => madd_537); - - RESMULT_madd_606_ADD_22x22_fast_I152_Y_0 : AO1 - port map(A => N403, B => N396, C => N395, Y => - ADD_22x22_fast_I152_Y_0); - - \RESMULT_a13_b[2]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(2), Y => - \a13_b[2]\); - - RESMULT_madd_416_4 : XOR3 - port map(A => \a11_b[5]\, B => \a13_b[3]\, C => \a12_b[4]\, - Y => madd_416_4); - - RESMULT_madd_606_ADD_22x22_fast_I42_Y : OR2 - port map(A => N303, B => I42_un1_Y, Y => N358); - - RESMULT_madd_606_ADD_22x22_fast_I16_G0N : NOR2A - port map(A => madd_568_0, B => madd_552, Y => N321); - - \RESMULT_a_i0_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(0), Y => - \a_i0_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I30_un1_Y : NOR3B - port map(A => madd_548_0, B => N322, C => madd_527, Y => - ADD_22x22_fast_I30_un1_Y); - - RESMULT_madd_437 : MAJ3 - port map(A => \a12_b[5]\, B => \a10_b[7]\, C => \a11_b[6]\, - Y => madd_437); - - RESMULT_madd_606_ADD_22x22_fast_I100_Y : AO1 - port map(A => N378, B => N375, C => N374, Y => N419); - - RESMULT_madd_606_ADD_22x22_fast_I199_Y_0_0 : XOR2 - port map(A => madd_347_0, B => madd_311, Y => - ADD_22x22_fast_I199_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I98_Y : AOI1 - port map(A => N376, B => N373, C => N372, Y => N417); - - \RESMULT_a4_b[7]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(7), Y => - \a4_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I9_P0N : OR2 - port map(A => madd_347_0, B => madd_311, Y => N301); - - RESMULT_madd_304 : AO13 - port map(A => madd_257, B => N_114_i, C => madd_305_10, Y - => madd_304); - - \RESMULT_a_i9_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(9), Y => - \a_i9_b[8]\); - - \REG[1]\ : DFN1E1C0 - port map(D => \RESMULT[1]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(1)); - - \RESMULT_a5_b[1]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(1), Y => - \a5_b[1]\); - - \RESMULT_a1_b[7]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(7), Y => - \a1_b[7]\); - - \RESMULT_a1_b[4]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(4), Y => - \a1_b[4]\); - - RESMULT_madd_39_2_0 : XOR2 - port map(A => \a5_b[0]\, B => \a3_b[2]\, Y => madd_39_2_0); - - RESMULT_madd_606_ADD_22x22_fast_I133_un1_Y : NOR3C - port map(A => N369, B => N373, C => N421, Y => I133_un1_Y); - - RESMULT_madd_583_0 : XOR3 - port map(A => madd_562, B => madd_578_0, C => madd_567, Y - => madd_583_0); - - RESMULT_madd_18 : MAJ3 - port map(A => \a4_b[0]\, B => \a2_b[2]\, C => \a3_b[1]\, Y - => N_8); - - \RESMULT_a9_b[7]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(7), Y => - \a9_b[7]\); - - RESMULT_madd_492 : MAJ3 - port map(A => madd_493_6, B => madd_452, C => madd_493_8, Y - => madd_492); - - \RESMULT_a0_b[5]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(5), Y => - \a0_b[5]\); - - \RESMULT_a2_b[4]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(4), Y => - \a2_b[4]\); - - RESMULT_madd_272 : AO13 - port map(A => madd_230, B => N_113_i, C => madd_268_12, Y - => madd_272); - - \RESMULT_a9_b[5]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(5), Y => - \a9_b[5]\); - - RESMULT_madd_225 : MIN3 - port map(A => madd_231_2, B => madd_231_4, C => madd_231_7, - Y => N_98_i); - - RESMULT_madd_606_ADD_22x22_fast_I194_Y_0 : AX1E - port map(A => I135_un1_Y, B => N417, C => - ADD_22x22_fast_I194_Y_0_0, Y => \RESMULT[9]\); - - RESMULT_madd_592 : MAJ3 - port map(A => \a_i15_b[8]\, B => \a16_b[7]\, C => - \a17_b_i[6]\, Y => N_252); - - RESMULT_madd_194_10_0 : XOR2 - port map(A => madd_131, B => madd_136, Y => madd_194_10_0); - - RESMULT_madd_458_7 : XOR3 - port map(A => \a10_b[7]\, B => \a12_b[5]\, C => \a11_b[6]\, - Y => madd_458_7); - - \RESMULT_a10_b[4]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(4), Y => - \a10_b[4]\); - - \RESMULT_a0_b[7]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(7), Y => - \a0_b[7]\); - - RESMULT_madd_588_0 : XNOR3 - port map(A => \a16_b[7]\, B => \a_i15_b[8]\, C => - \a17_b_i[6]\, Y => N_251); - - \RESMULT_a15_b[1]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(1), Y => - \a15_b[1]\); - - \RESMULT_a0_b[8]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(8), Y => - \a0_b[8]\); - - RESMULT_madd_24_4 : XNOR3 - port map(A => \a0_b[4]\, B => \a1_b[3]\, C => madd_8, Y => - madd_24_4); - - RESMULT_madd_606_ADD_22x22_fast_I198_Y_0 : XNOR3 - port map(A => madd_274, B => madd_310_0, C => N562_i, Y => - \RESMULT[13]\); - - \REG[15]\ : DFN1E1C0 - port map(D => \RESMULT[15]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(15)); - - RESMULT_madd_39_4_0 : XOR2 - port map(A => \a2_b[3]\, B => \a1_b[4]\, Y => madd_39_4_0); - - \RESMULT_a_i5_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(5), Y => - \a_i5_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I134_Y : AO1 - port map(A => N416, B => N378, C => N415, Y => N461); - - RESMULT_madd_606_ADD_22x22_fast_I8_P0N : OR2 - port map(A => madd_310_0, B => madd_274, Y => N298); - - \REG[3]\ : DFN1E1C0 - port map(D => \RESMULT[3]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(3)); - - RESMULT_madd_606_ADD_22x22_fast_I80_Y : OR3B - port map(A => I38_un1_Y_i, B => I80_un1_Y_i, C => N309, Y - => N399); - - RESMULT_madd_606_ADD_22x22_fast_I52_Y : MAJ3 - port map(A => madd_163, B => madd_199_0, C => N285, Y => - N368); - - RESMULT_madd_606_ADD_22x22_fast_I27_Y : NOR2B - port map(A => N328, B => N325, Y => N343); - - \RESMULT_a_i12_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(12), Y => - \a_i12_b[8]\); - - \RESMULT_a16_b[1]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(1), Y => - \a16_b[1]\); - - RESMULT_madd_273_0 : XNOR3 - port map(A => madd_230, B => madd_268_0_0, C => madd_235, Y - => madd_273_0); - - \RESMULT_a10_b[6]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(6), Y => - \a10_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I71_Y : NOR2 - port map(A => N349, B => N345, Y => N390); - - RESMULT_madd_119 : AO18 - port map(A => madd_82, B => N_47, C => N_45_i, Y => - madd_119); - - RESMULT_madd_61_2 : XOR3 - port map(A => \a4_b[2]\, B => \a6_b[0]\, C => \a5_b[1]\, Y - => madd_61_2); - - RESMULT_madd_606_ADD_22x22_fast_I199_Y_0 : AX1D - port map(A => ADD_22x22_fast_I158_un1_Y, B => N453, C => - ADD_22x22_fast_I199_Y_0_0, Y => \RESMULT[14]\); - - \RESMULT_a6_b[5]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(5), Y => - \a6_b[5]\); - - RESMULT_madd_305_2 : XOR2 - port map(A => madd_305_2_0, B => \a12_b[1]\, Y => - madd_305_2); - - \RESMULT_a15_b[3]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(3), Y => - \a15_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I39_Y : NOR2B - port map(A => N310, B => N307, Y => N355); - - \RESMULT_a3_b[6]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(6), Y => - \a3_b[6]\); - - RESMULT_madd_342_2 : XOR2 - port map(A => madd_342_2_0, B => \a13_b[1]\, Y => - madd_342_2); - - \RESMULT_a5_b[6]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(6), Y => - \a5_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_2 : AOI1B - port map(A => N453, B => N438, C => ADD_22x22_fast_I172_Y_1, - Y => ADD_22x22_fast_I172_Y_2); - - RESMULT_madd_331 : MIN3 - port map(A => N_122_i, B => madd_284, C => madd_289, Y => - madd_331); - - RESMULT_madd_606_ADD_22x22_fast_I5_G0N : NOR2B - port map(A => madd_199_0, B => madd_163, Y => N288); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_3 : OR3C - port map(A => N398, B => N390, C => - ADD_22x22_fast_I171_Y_3_tz, Y => ADD_22x22_fast_I171_Y_3); - - RESMULT_madd_410 : MAJ3 - port map(A => madd_416_2, B => madd_416_4, C => madd_416_7, - Y => madd_410); - - RESMULT_madd_220 : MAJ3 - port map(A => N_74_i, B => madd_173, C => madd_178, Y => - madd_220); - - RESMULT_madd_124 : AO13 - port map(A => madd_92, B => N_38_i, C => madd_110_0, Y => - madd_124); - - RESMULT_madd_606_ADD_22x22_fast_I108_un1_Y : OR2B - port map(A => N395, B => N388, Y => I108_un1_Y); - - RESMULT_madd_24_0 : XOR3 - port map(A => madd_24_4, B => N_7_i, C => madd_13, Y => - madd_24_0); - - RESMULT_madd_416_10 : XOR3 - port map(A => madd_358, B => N_154_i, C => madd_363, Y => - N_175_i); - - \RESMULT_a6_b[6]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(6), Y => - \a6_b[6]\); - - RESMULT_madd_363 : MIN3 - port map(A => \a9_b[6]\, B => \a8_b[7]\, C => \a_i7_b[8]\, - Y => madd_363); - - \RESMULT_a17_b_i[3]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(3), Y => - \a17_b_i[3]\); - - \RESMULT_a8_b[2]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(2), Y => - \a8_b[2]\); - - RESMULT_madd_268_2 : XOR2 - port map(A => madd_268_2_0, B => \a11_b[1]\, Y => - madd_268_2); - - RESMULT_madd_606_ADD_22x22_fast_I62_Y : MAJ3 - port map(A => madd_44_0, B => CO3, C => madd_28, Y => N378); - - \REG[10]\ : DFN1E1C0 - port map(D => \RESMULT[10]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(10)); - - RESMULT_madd_606_ADD_22x22_fast_I135_un1_Y : OR2A - port map(A => madd_28, B => N418, Y => I135_un1_Y); - - RESMULT_madd_110_0 : XOR3 - port map(A => madd_72, B => madd_95_0, C => madd_77, Y => - madd_110_0); - - RESMULT_madd_606_ADD_22x22_fast_I81_Y : NOR2B - port map(A => N359, B => N355, Y => N400); - - \RESMULT_a11_b[6]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(6), Y => - \a11_b[6]\); - - \REG[12]\ : DFN1E1C0 - port map(D => \RESMULT[12]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(12)); - - \RESMULT_a11_b[3]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(3), Y => - \a11_b[3]\); - - RESMULT_madd_55 : MAJ3 - port map(A => \a3_b[3]\, B => \a1_b[5]\, C => \a2_b[4]\, Y - => madd_55); - - RESMULT_madd_527 : MIN3 - port map(A => madd_523_8, B => madd_492, C => madd_523_10, - Y => madd_527); - - \RESMULT_a_i4_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(4), Y => - \a_i4_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I6_P0N : OR2 - port map(A => madd_236_0, B => madd_200, Y => N292); - - RESMULT_madd_567 : MAJ3 - port map(A => madd_537, B => madd_542, C => madd_568_2, Y - => madd_567); - - RESMULT_madd_421_0 : XNOR2 - port map(A => madd_416_0, B => madd_383, Y => madd_421_0); - - \RESMULT_a_i11_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(11), Y => - \a_i11_b[8]\); - - RESMULT_madd_342_12 : XOR3 - port map(A => madd_342_10, B => N_130_i, C => madd_294, Y - => madd_342_12); - - RESMULT_madd_467 : MAJ3 - port map(A => \a16_b[2]\, B => \a15_b[3]\, C => - \a17_b_i[1]\, Y => madd_467); - - RESMULT_madd_236_0 : XNOR3 - port map(A => madd_193, B => madd_231_0_0, C => madd_198, Y - => madd_236_0); - - RESMULT_madd_383 : AO13 - port map(A => madd_341, B => N_161_i, C => madd_379_12, Y - => madd_383); - - RESMULT_madd_606_ADD_22x22_fast_I170_un1_Y_0 : NOR2B - port map(A => N450, B => N419, Y => - ADD_22x22_fast_I170_un1_Y_0); - - RESMULT_madd_379_0 : XOR3 - port map(A => madd_379_12, B => N_161_i, C => madd_341, Y - => madd_379_0); - - RESMULT_madd_606_ADD_22x22_fast_I54_un1_Y : OR2B - port map(A => N286, B => N282, Y => I54_un1_Y_i); - - RESMULT_madd_606_ADD_22x22_fast_I46_Y : MAJ3 - port map(A => madd_274, B => madd_310_0, C => N294, Y => - N362); - - RESMULT_madd_194_12_0 : XOR2 - port map(A => madd_194_10, B => madd_151, Y => - madd_194_12_0); - - RESMULT_madd_606_ADD_22x22_fast_I155_Y : OR3B - port map(A => I155_un1_Y, B => I122_un1_Y, C => N401, Y => - N550); - - \REG[11]\ : DFN1E1C0 - port map(D => \RESMULT[11]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(11)); - - RESMULT_madd_587 : MIN3 - port map(A => madd_562, B => madd_567, C => madd_578_0, Y - => madd_587); - - RESMULT_madd_543_2_0 : XOR2 - port map(A => \a16_b[4]\, B => \a15_b[5]\, Y => - madd_543_2_0); - - GND_i : GND - port map(Y => \GND\); - - \RESMULT_a7_b[3]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(3), Y => - \a7_b[3]\); - - \RESMULT_a8_b[6]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(6), Y => - \a8_b[6]\); - - \RESMULT_a3_b[3]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(3), Y => - \a3_b[3]\); - - RESMULT_madd_231_10 : XNOR3 - port map(A => madd_173, B => N_74_i, C => madd_178, Y => - madd_231_10); - - RESMULT_madd_157_4 : XNOR3 - port map(A => \a4_b[5]\, B => \a6_b[3]\, C => \a5_b[4]\, Y - => N_59_i); - - RESMULT_madd_487 : MAJ3 - port map(A => madd_493_4, B => madd_442, C => madd_447, Y - => madd_487); - - RESMULT_madd_385 : NOR2A - port map(A => madd_379_0, B => madd_346, Y => madd_385); - - RESMULT_madd_157_9 : XOR3 - port map(A => madd_99, B => \a_i0_b[8]\, C => madd_104, Y - => madd_157_9); - - RESMULT_madd_606_ADD_22x22_fast_I206_Y_0_0 : XNOR2 - port map(A => madd_568_0, B => madd_552, Y => - ADD_22x22_fast_I206_Y_0_0); - - RESMULT_madd_305_2_0 : XOR2 - port map(A => \a13_b[0]\, B => \a11_b[2]\, Y => - madd_305_2_0); - - RESMULT_madd_606_ADD_22x22_fast_I126_un1_Y : NOR2A - port map(A => N413, B => N406, Y => I126_un1_Y); - - RESMULT_madd_547 : MAJ3 - port map(A => madd_543_4, B => madd_512, C => madd_543_6, Y - => madd_547); - - \RESMULT_a5_b[7]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(7), Y => - \a5_b[7]\); - - \REG[20]\ : DFN1E1C0 - port map(D => \RESMULT[20]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(20)); - - RESMULT_madd_60 : MAJ3 - port map(A => \a0_b[6]\, B => madd_33, C => madd_38, Y => - madd_60); - - \RESMULT_a10_b[0]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(0), Y => - \a10_b[0]\); - - \REG[22]\ : DFN1E1C0 - port map(D => \RESMULT[22]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(22)); - - RESMULT_madd_447 : MAJ3 - port map(A => madd_458_2, B => madd_400, C => madd_458_4, Y - => madd_447); - - RESMULT_madd_502 : MAJ3 - port map(A => \a16_b[3]\, B => \a15_b[4]\, C => - \a17_b_i[2]\, Y => madd_502); - - RESMULT_madd_305_0_0 : XOR2 - port map(A => N_129_i, B => madd_305_12, Y => madd_305_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I92_Y : AO1 - port map(A => N370, B => N367, C => N366, Y => N411); - - RESMULT_madd_606_ADD_22x22_fast_I84_Y : AO1 - port map(A => N362, B => N359, C => N358, Y => N403); - - RESMULT_madd_194_12 : XOR2 - port map(A => madd_194_12_0, B => madd_146, Y => - madd_194_12); - - \RESMULT_a15_b[0]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(0), Y => - \a15_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I190_Y_0 : XOR3 - port map(A => CO3, B => madd_44_0, C => madd_28, Y => - \RESMULT[5]\); - - \RESMULT_a14_b[0]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(0), Y => - \a14_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I201_Y_0 : XNOR3 - port map(A => madd_385, B => madd_421_0, C => N553_i, Y => - \RESMULT[16]\); - - RESMULT_madd_606_ADD_22x22_fast_I155_un1_Y_0 : AOI1B - port map(A => N417, B => I135_un1_Y, C => N402, Y => - ADD_22x22_fast_I155_un1_Y_0); - - \REG[8]\ : DFN1E1C0 - port map(D => \RESMULT[8]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(8)); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_0 : NOR3A - port map(A => I72_un1_Y, B => ADD_22x22_fast_I30_un1_Y, C - => N321, Y => ADD_22x22_fast_I172_Y_0); - - \RESMULT_a16_b[3]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(3), Y => - \a16_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I153_Y : AO1B - port map(A => ADD_22x22_fast_I153_un1_Y_0, B => N398, C => - ADD_22x22_fast_I153_Y_0, Y => N544); - - RESMULT_madd_606_ADD_22x22_fast_I191_Y_0 : XOR3 - port map(A => madd_66_0, B => madd_61_0, C => N378, Y => - \RESMULT[6]\); - - \RESMULT_a5_b[3]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(3), Y => - \a5_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I35_Y : NOR2B - port map(A => N316, B => N313, Y => N351); - - RESMULT_madd_274 : XA1B - port map(A => madd_230, B => madd_268_0_0, C => madd_235, Y - => madd_274); - - RESMULT_madd_606_ADD_22x22_fast_I56_Y : MAJ3 - port map(A => madd_120_0, B => madd_125_0, C => N279, Y => - N372); - - RESMULT_madd_279 : MIN3 - port map(A => \a13_b[0]\, B => \a11_b[2]\, C => \a12_b[1]\, - Y => N_122_i); - - RESMULT_madd_606_ADD_22x22_fast_I10_G0N : NOR2B - port map(A => madd_384_0, B => madd_348, Y => N303); - - \REG[21]\ : DFN1E1C0 - port map(D => \RESMULT[21]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(21)); - - RESMULT_madd_493_12 : XOR3 - port map(A => madd_493_8, B => madd_493_6, C => madd_452, Y - => madd_493_12); - - RESMULT_madd_321 : MIN3 - port map(A => \a11_b[3]\, B => \a9_b[5]\, C => \a10_b[4]\, - Y => madd_321); - - RESMULT_madd_342_7 : XOR3 - port map(A => \a7_b[7]\, B => \a8_b[6]\, C => \a_i6_b[8]\, - Y => madd_342_7); - - RESMULT_madd_432 : MAJ3 - port map(A => \a15_b[2]\, B => \a13_b[4]\, C => \a14_b[3]\, - Y => madd_432); - - RESMULT_madd_268_7 : XOR3 - port map(A => \a5_b[7]\, B => \a6_b[6]\, C => \a_i4_b[8]\, - Y => madd_268_7); - - \REG[16]\ : DFN1E1C0 - port map(D => \RESMULT[16]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(16)); - - RESMULT_madd_23 : MAJ3 - port map(A => \a1_b[3]\, B => madd_8, C => \a0_b[4]\, Y => - madd_23); - - \RESMULT_a14_b[4]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(4), Y => - \a14_b[4]\); - - RESMULT_madd_532 : MAJ3 - port map(A => \a16_b[4]\, B => \a15_b[5]\, C => - \a17_b_i[3]\, Y => madd_532); - - RESMULT_madd_24_2 : XNOR3 - port map(A => \a2_b[2]\, B => \a4_b[0]\, C => \a3_b[1]\, Y - => N_7_i); - - \RESMULT_a16_b[4]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(4), Y => - \a16_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I79_Y : NOR2B - port map(A => N357, B => N353, Y => N398); - - RESMULT_madd_606_ADD_22x22_fast_I17_P0N : OR2 - port map(A => madd_583_0, B => madd_572, Y => N325); - - RESMULT_madd_305_12 : XOR3 - port map(A => madd_305_10, B => N_114_i, C => madd_257, Y - => madd_305_12); - - RESMULT_madd_543_4 : XOR3 - port map(A => \a13_b[7]\, B => \a14_b[6]\, C => - \a_i12_b[8]\, Y => madd_543_4); - - \RESMULT_a14_b[3]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(3), Y => - \a14_b[3]\); - - RESMULT_madd_0_s_0 : XOR2 - port map(A => \a2_b[0]\, B => \a1_b[1]\, Y => madd_0_s_0); - - RESMULT_madd_606_ADD_22x22_fast_I157_Y : NOR2 - port map(A => N451, B => I157_un1_Y, Y => N556_i); - - \RESMULT_a_i6_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(6), Y => - \a_i6_b[8]\); - - \REG[4]\ : DFN1E1C0 - port map(D => \RESMULT[4]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(4)); - - \REG[13]\ : DFN1E1C0 - port map(D => \RESMULT[13]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(13)); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0 : AX1E - port map(A => ADD_22x22_fast_I170_Y_3, B => - ADD_22x22_fast_I170_Y_2, C => ADD_22x22_fast_I209_Y_0_2, - Y => \RESMULT[24]\); - - RESMULT_madd_336 : MAJ3 - port map(A => madd_342_2, B => madd_342_4, C => madd_342_7, - Y => madd_336); - - RESMULT_madd_215 : MIN3 - port map(A => \a5_b[6]\, B => \a4_b[7]\, C => \a_i3_b[8]\, - Y => madd_215); - - RESMULT_madd_305_4_0 : XOR2 - port map(A => \a10_b[3]\, B => \a8_b[5]\, Y => madd_305_4_0); - - RESMULT_madd_416_2 : XOR3 - port map(A => \a14_b[2]\, B => \a16_b[0]\, C => \a15_b[1]\, - Y => madd_416_2); - - RESMULT_madd_44_0 : XNOR2 - port map(A => madd_39_0, B => madd_23, Y => madd_44_0); - - \RESMULT_a16_b[2]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(2), Y => - \a16_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_1 : AOI1B - port map(A => N399, B => N392, C => ADD_22x22_fast_I172_Y_0, - Y => ADD_22x22_fast_I172_Y_1); - - RESMULT_madd_341 : AO13 - port map(A => madd_294, B => N_130_i, C => madd_342_10, Y - => madd_341); - - \RESMULT_a17_b_i[5]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(5), Y => - \a17_b_i[5]\); - - RESMULT_madd_568_2 : XOR3 - port map(A => \a15_b[6]\, B => \a16_b[5]\, C => - \a17_b_i[4]\, Y => madd_568_2); - - \RESMULT_a7_b[6]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(6), Y => - \a7_b[6]\); - - RESMULT_madd_305_7 : XOR2 - port map(A => madd_305_7_0, B => \a_i5_b[8]\, Y => - madd_305_7); - - RESMULT_madd_606_ADD_22x22_fast_I0_P0N : OR2 - port map(A => CO3, B => madd_44_0, Y => N274); - - RESMULT_madd_606_ADD_22x22_fast_I2_G0N : NOR2B - port map(A => madd_93_0, B => madd_67, Y => N279); - - RESMULT_madd_606_ADD_22x22_fast_I89_Y : NOR3C - port map(A => N295, B => N298, C => N367, Y => N408); - - RESMULT_madd_493_6_0 : XOR2 - port map(A => \a11_b[7]\, B => \a_i10_b[8]\, Y => - madd_493_6_0); - - RESMULT_madd_384_0 : XNOR2 - port map(A => madd_379_0, B => madd_346, Y => madd_384_0); - - RESMULT_madd_294 : MAJ3 - port map(A => N_106_i, B => madd_247, C => madd_252, Y => - madd_294); - - RESMULT_madd_231_8 : XNOR3 - port map(A => madd_231_4, B => madd_231_2, C => madd_231_7, - Y => N_97_i); - - RESMULT_madd_268_2_0 : XOR2 - port map(A => \a12_b[0]\, B => \a10_b[2]\, Y => - madd_268_2_0); - - RESMULT_madd_299 : MIN3 - port map(A => madd_305_2, B => madd_305_4, C => madd_305_7, - Y => N_130_i); - - RESMULT_madd_578_0_0 : AX1 - port map(A => alu_sample(14), B => alu_coef_s(8), C => - madd_573_0, Y => madd_578_0_0); - - RESMULT_madd_368 : MAJ3 - port map(A => N_138_i, B => madd_321, C => madd_326, Y => - madd_368); - - \RESMULT_a11_b[1]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(1), Y => - \a11_b[1]\); - - \REG[7]\ : DFN1E1C0 - port map(D => \RESMULT[7]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(7)); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y : OR3C - port map(A => I110_un1_Y, B => ADD_22x22_fast_I171_Y_1, C - => ADD_22x22_fast_I171_Y_3, Y => N535); - - \RESMULT_a5_b[2]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(2), Y => - \a5_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I76_un1_Y : OA1A - port map(A => I38_un1_Y_i, B => N309, C => N351, Y => - I76_un1_Y); - - RESMULT_madd_405 : MIN3 - port map(A => N_154_i, B => madd_358, C => madd_363, Y => - madd_405); - - \RESMULT_a1_b[5]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(5), Y => - \a1_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_un1_Y : OR3C - port map(A => N454, B => N378, C => N438, Y => I172_un1_Y); - - \REG[23]\ : DFN1E1C0 - port map(D => \RESMULT[23]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(23)); - - RESMULT_madd_606_ADD_22x22_fast_I10_P0N : OR2 - port map(A => madd_384_0, B => madd_348, Y => N304); - - RESMULT_madd_210 : MIN3 - port map(A => \a8_b[3]\, B => \a6_b[5]\, C => \a7_b[4]\, Y - => madd_210); - - RESMULT_madd_114 : MAJ3 - port map(A => madd_72, B => madd_77, C => madd_95_0, Y => - madd_114); - - \RESMULT_a12_b[0]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(0), Y => - \a12_b[0]\); - - \RESMULT_a_i15_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(15), Y => - \a_i15_b[8]\); - - \RESMULT_a7_b[5]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(5), Y => - \a7_b[5]\); - - RESMULT_madd_379_10 : XNOR3 - port map(A => madd_321, B => N_138_i, C => madd_326, Y => - madd_379_10); - - RESMULT_madd_39_4 : XOR2 - port map(A => madd_39_4_0, B => \a0_b[5]\, Y => N_15); - - \REG[0]\ : DFN1E1C0 - port map(D => \RESMULT[0]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(0)); - - RESMULT_madd_606_ADD_22x22_fast_I153_un1_Y_0 : NOR2A - port map(A => N568, B => N406, Y => - ADD_22x22_fast_I153_un1_Y_0); - - RESMULT_madd_458_9 : XOR3 - port map(A => madd_390, B => \a_i9_b[8]\, C => madd_395, Y - => madd_458_9); - - RESMULT_madd_606_ADD_22x22_fast_I101_Y : OR2 - port map(A => N376, B => I101_un1_Y, Y => N421); - - RESMULT_madd_157_11 : XOR3 - port map(A => N_57, B => N_59_i, C => N_48, Y => - madd_157_11); - - \REG[5]\ : DFN1E1C0 - port map(D => \RESMULT[5]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(5)); - - RESMULT_madd_606_ADD_22x22_fast_I125_Y : NOR2B - port map(A => N412, B => N404, Y => N450); - - RESMULT_madd_125_0 : AX1 - port map(A => madd_65, B => madd_88_0, C => madd_115_0, Y - => madd_125_0); - - \RESMULT_a8_b[1]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(1), Y => - \a8_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I96_Y : AO1 - port map(A => N374, B => N371, C => N370, Y => N415); - - RESMULT_madd_606_ADD_22x22_fast_I159_Y : AOI1 - port map(A => N456, B => madd_28, C => N455, Y => N562_i); - - RESMULT_madd_493_8 : XOR3 - port map(A => madd_432, B => madd_493_2, C => madd_437, Y - => madd_493_8); - - \RESMULT_a12_b[6]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(6), Y => - \a12_b[6]\); - - RESMULT_madd_348 : XA1B - port map(A => madd_304, B => madd_342_0_0, C => madd_309, Y - => madd_348); - - RESMULT_madd_606_ADD_22x22_fast_I132_Y : AO1 - port map(A => N419, B => N412, C => N411, Y => N565); - - RESMULT_madd_517 : MAJ3 - port map(A => madd_523_2, B => madd_477, C => madd_523_4, Y - => madd_517); - - RESMULT_madd_606_ADD_22x22_fast_I207_Y_0_0 : XOR2 - port map(A => madd_583_0, B => madd_572, Y => - ADD_22x22_fast_I207_Y_0_0); - - \RESMULT_a12_b[7]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(7), Y => - \a12_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_2 : AOI1B - port map(A => N455, B => N440, C => ADD_22x22_fast_I173_Y_1, - Y => ADD_22x22_fast_I173_Y_2); - - \RESMULT_a12_b[3]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(3), Y => - \a12_b[3]\); - - RESMULT_madd_88_2 : XOR3 - port map(A => \a5_b[2]\, B => \a7_b[0]\, C => \a6_b[1]\, Y - => madd_88_2); - - RESMULT_madd_523_7 : XOR3 - port map(A => madd_472, B => \a_i11_b[8]\, C => madd_467, Y - => madd_523_7); - - RESMULT_madd_422 : NOR2A - port map(A => madd_416_0, B => madd_383, Y => madd_422); - - RESMULT_madd_462 : MAJ3 - port map(A => madd_458_13, B => madd_420, C => madd_458_14, - Y => madd_462); - - \RESMULT_a4_b[5]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(5), Y => - \a4_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I42_un1_Y : NOR3C - port map(A => madd_311, B => madd_347_0, C => N304, Y => - I42_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I110_un1_Y : AO1C - port map(A => N352, B => I78_un1_Y_i, C => N390, Y => - I110_un1_Y); - - RESMULT_madd_157_0 : XOR3 - port map(A => madd_157_12, B => madd_157_11, C => madd_119, - Y => madd_157_0); - - RESMULT_madd_606_ADD_22x22_fast_I78_Y : NOR2A - port map(A => I78_un1_Y_i, B => N352, Y => N397_i); - - RESMULT_madd_606_ADD_22x22_fast_I75_Y : NOR2A - port map(A => N353, B => N349, Y => N394); - - RESMULT_madd_522 : MAJ3 - port map(A => madd_482, B => madd_487, C => madd_523_7, Y - => madd_522); - - RESMULT_madd_305_8 : XNOR2 - port map(A => madd_305_8_0, B => madd_305_7, Y => N_129_i); - - RESMULT_madd_562 : MAJ3 - port map(A => \a14_b[7]\, B => madd_532, C => \a_i13_b[8]\, - Y => madd_562); - - \REG[14]\ : DFN1E1C0 - port map(D => \RESMULT[14]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(14)); - - \RESMULT_a2_b[6]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(6), Y => - \a2_b[6]\); - - \RESMULT_a12_b[2]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(2), Y => - \a12_b[2]\); - - RESMULT_madd_157_7 : XOR2 - port map(A => madd_157_7_0, B => \a_i1_b[8]\, Y => - madd_157_7); - - RESMULT_madd_606_ADD_22x22_fast_I11_P0N : OR2 - port map(A => madd_421_0, B => madd_385, Y => N307); - - RESMULT_madd_1_605_SUM3_0 : XOR2 - port map(A => CO2, B => madd_24_0, Y => \RESMULT[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I157_un1_Y : NOR2B - port map(A => N452, B => N421, Y => I157_un1_Y); - - RESMULT_madd_178 : MIN3 - port map(A => \a4_b[6]\, B => \a3_b[7]\, C => \a_i2_b[8]\, - Y => madd_178); - - RESMULT_madd_326 : MIN3 - port map(A => \a8_b[6]\, B => \a7_b[7]\, C => \a_i6_b[8]\, - Y => madd_326); - - RESMULT_madd_482 : MAJ3 - port map(A => madd_432, B => madd_437, C => madd_493_2, Y - => madd_482); - - RESMULT_madd_342_0_0 : XOR2 - port map(A => N_145_i, B => madd_342_12, Y => madd_342_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_3_tz : AO1 - port map(A => N452, B => N421, C => N451, Y => - ADD_22x22_fast_I171_Y_3_tz); - - RESMULT_madd_606_ADD_22x22_fast_I32_Y : AO13 - port map(A => N315, B => madd_548_0, C => madd_527, Y => - N348); - - RESMULT_madd_28 : AO18 - port map(A => madd_13, B => madd_24_4, C => N_7_i, Y => - madd_28); - - RESMULT_madd_582 : OR2 - port map(A => madd_582_0, B => madd_334, Y => madd_582); - - RESMULT_madd_543_2 : XOR2 - port map(A => madd_543_2_0, B => \a17_b_i[3]\, Y => - madd_543_2); - - RESMULT_madd_194_8 : XNOR3 - port map(A => madd_194_4, B => madd_194_2, C => madd_194_7, - Y => N_81_i); - - \RESMULT_a17_b_i[1]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(1), Y => - \a17_b_i[1]\); - - \RESMULT_a0_b[4]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(4), Y => - \a0_b[4]\); - - \RESMULT_a13_b[3]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(3), Y => - \a13_b[3]\); - - RESMULT_madd_442 : MAJ3 - port map(A => \a_i9_b[8]\, B => madd_390, C => madd_395, Y - => madd_442); - - RESMULT_madd_606_ADD_22x22_fast_I90_un1_Y : NOR2B - port map(A => N368, B => N365, Y => - ADD_22x22_fast_I90_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I88_Y : OR2 - port map(A => N362, B => I88_un1_Y, Y => N407); - - RESMULT_madd_606_ADD_22x22_fast_I85_Y : NOR3C - port map(A => N295, B => N298, C => N359, Y => N404); - - RESMULT_madd_542 : MAJ3 - port map(A => madd_507, B => madd_502, C => madd_543_2, Y - => madd_542); - - RESMULT_madd_606_ADD_22x22_fast_I57_Y : OA1 - port map(A => madd_120_0, B => madd_125_0, C => N280, Y => - N373); - - \RESMULT_a4_b[6]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(6), Y => - \a4_b[6]\); - - \RESMULT_a0_b[2]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(2), Y => - \a0_b[2]\); - - RESMULT_madd_157_12 : XOR3 - port map(A => madd_157_9, B => madd_157_7, C => madd_114, Y - => madd_157_12); - - \REG[24]\ : DFN1E1C0 - port map(D => \RESMULT[24]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(24)); - - RESMULT_madd_606_ADD_22x22_fast_I8_G0N : NOR2B - port map(A => madd_310_0, B => madd_274, Y => N297); - - RESMULT_madd_606_ADD_22x22_fast_I127_Y : NOR3B - port map(A => N369, B => N373, C => N406, Y => N452); - - RESMULT_madd_199_0 : XNOR3 - port map(A => madd_156, B => madd_194_0_0, C => madd_161, Y - => madd_199_0); - - RESMULT_madd_50 : MAJ3 - port map(A => \a6_b[0]\, B => \a4_b[2]\, C => \a5_b[1]\, Y - => madd_50); - - RESMULT_madd_8 : MAJ3 - port map(A => \a3_b[0]\, B => \a1_b[2]\, C => \a2_b[1]\, Y - => madd_8); - - RESMULT_madd_346 : AO13 - port map(A => madd_304, B => N_145_i, C => madd_342_12, Y - => madd_346); - - RESMULT_madd_606_ADD_22x22_fast_I72_un1_Y : OR3C - port map(A => N319, B => N322, C => N350, Y => I72_un1_Y); - - RESMULT_madd_262 : MIN3 - port map(A => madd_268_2, B => madd_268_4, C => madd_268_7, - Y => N_114_i); - - RESMULT_madd_231_7 : XOR3 - port map(A => \a4_b[7]\, B => \a5_b[6]\, C => \a_i3_b[8]\, - Y => madd_231_7); - - RESMULT_madd_311 : XA1B - port map(A => madd_267, B => madd_305_0_0, C => madd_272, Y - => madd_311); - - \RESMULT_a3_b[7]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(7), Y => - \a3_b[7]\); - - \RESMULT_a8_b[3]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(3), Y => - \a8_b[3]\); - - RESMULT_madd_173 : MIN3 - port map(A => \a7_b[3]\, B => \a5_b[5]\, C => \a6_b[4]\, Y - => madd_173); - - \RESMULT_a14_b[6]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(6), Y => - \a14_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I4_P0N : XO1A - port map(A => madd_124, B => madd_157_0, C => madd_126, Y - => N286); - - RESMULT_madd_157_7_0 : XOR2 - port map(A => \a3_b[6]\, B => \a2_b[7]\, Y => madd_157_7_0); - - RESMULT_madd_1_605_SUM2_0 : XOR2 - port map(A => CO1, B => madd_9_0, Y => \RESMULT[3]\); - - RESMULT_madd_194_10 : XOR2 - port map(A => madd_194_10_0, B => madd_141, Y => - madd_194_10); - - \RESMULT_a13_b[1]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(1), Y => - \a13_b[1]\); - - \RESMULT_a9_b[2]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(2), Y => - \a9_b[2]\); - - RESMULT_madd_198 : AO13 - port map(A => madd_156, B => N_81_i, C => madd_194_12, Y - => madd_198); - - RESMULT_madd_156 : MIN3 - port map(A => madd_157_7, B => madd_114, C => madd_157_9, Y - => madd_156); - - \RESMULT_a3_b[1]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(1), Y => - \a3_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I88_un1_Y : NOR3C - port map(A => N295, B => N298, C => N366, Y => I88_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_1 : OA1A - port map(A => N348, B => N345, C => ADD_22x22_fast_I171_Y_0, - Y => ADD_22x22_fast_I171_Y_1); - - RESMULT_madd_268_10 : XNOR3 - port map(A => madd_210, B => N_90_i, C => madd_215, Y => - madd_268_10); - - RESMULT_madd_342_4 : XOR2 - port map(A => madd_342_4_0, B => \a10_b[4]\, Y => - madd_342_4); - - RESMULT_madd_606_ADD_22x22_fast_I7_P0N : OR2 - port map(A => madd_273_0, B => madd_237, Y => N295); - - RESMULT_madd_151 : AO18 - port map(A => N_48, B => N_57, C => N_59_i, Y => madd_151); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0_0 : AX1A - port map(A => alu_sample(16), B => alu_coef_s(8), C => - \a17_b_i[7]\, Y => ADD_22x22_fast_I209_Y_0_0); - - \RESMULT_a12_b[5]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(5), Y => - \a12_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I206_Y_0 : AX1E - port map(A => I173_un1_Y, B => ADD_22x22_fast_I173_Y_2, C - => ADD_22x22_fast_I206_Y_0_0, Y => \RESMULT[21]\); - - \RESMULT_a17_b_i[4]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(4), Y => - \a17_b_i[4]\); - - RESMULT_madd_99 : MAJ3 - port map(A => \a8_b[0]\, B => \a6_b[2]\, C => \a7_b[1]\, Y - => madd_99); - - \RESMULT_a16_b[6]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(6), Y => - \a16_b[6]\); - - RESMULT_madd_582_0_tz : OR2 - port map(A => madd_573_0, B => madd_557, Y => madd_582_0_tz); - - RESMULT_madd_242 : MIN3 - port map(A => \a12_b[0]\, B => \a10_b[2]\, C => \a11_b[1]\, - Y => N_106_i); - - \RESMULT_a1_b[3]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(3), Y => - \a1_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_3_0 : NOR2B - port map(A => N388, B => N396, Y => - ADD_22x22_fast_I170_Y_3_0); - - RESMULT_madd_606_ADD_22x22_fast_I13_G0N : NOR2B - port map(A => madd_493_0, B => madd_462, Y => N312); - - RESMULT_madd_568_6 : XOR3 - port map(A => madd_537, B => madd_568_2, C => madd_542, Y - => madd_568_6); - - \RESMULT_a10_b[5]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(5), Y => - \a10_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I205_Y_0 : XOR3 - port map(A => madd_527, B => madd_548_0, C => N541, Y => - \RESMULT[20]\); - - RESMULT_madd_606_ADD_22x22_fast_I154_Y : NOR3 - port map(A => I120_un1_Y, B => N399, C => I154_un1_Y, Y => - N547); - - RESMULT_madd_606_ADD_22x22_fast_I38_un1_Y : OR3C - port map(A => madd_385, B => madd_421_0, C => N310, Y => - I38_un1_Y_i); - - RESMULT_madd_3 : MAJ3 - port map(A => \a2_b[0]\, B => \a0_b[2]\, C => \a1_b[1]\, Y - => madd_3); - - RESMULT_madd_379_4 : XOR3 - port map(A => \a10_b[5]\, B => \a12_b[3]\, C => \a11_b[4]\, - Y => madd_379_4); - - RESMULT_madd_257 : MAJ3 - port map(A => N_90_i, B => madd_210, C => madd_215, Y => - madd_257); - - RESMULT_madd_231_4 : XOR3 - port map(A => \a6_b[5]\, B => \a8_b[3]\, C => \a7_b[4]\, Y - => madd_231_4); - - RESMULT_madd_115_2 : XNOR3 - port map(A => \a3_b[5]\, B => \a5_b[3]\, C => \a4_b[4]\, Y - => N_45_i); - - RESMULT_madd_606_ADD_22x22_fast_I14_P0N : OR2A - port map(A => madd_497, B => madd_523_0, Y => N316); - - RESMULT_madd_606_ADD_22x22_fast_I200_Y_0 : XNOR3 - port map(A => madd_348, B => madd_384_0, C => N556_i, Y => - \RESMULT[15]\); - - \RESMULT_a2_b[1]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(1), Y => - \a2_b[1]\); - - RESMULT_madd_88_7 : XOR3 - port map(A => \a0_b[7]\, B => \a1_b[6]\, C => madd_50, Y - => madd_88_7); - - RESMULT_madd_606_ADD_22x22_fast_I29_Y : OR2B - port map(A => N325, B => N322, Y => N345); - - RESMULT_madd_606_ADD_22x22_fast_I43_Y : NOR2B - port map(A => N304, B => N301, Y => N359); - - RESMULT_madd_606_ADD_22x22_fast_I129_Y : NOR2B - port map(A => N416, B => N408, Y => N454); - - RESMULT_madd_581 : NOR2B - port map(A => madd_573_0, B => madd_557, Y => madd_334); - - RESMULT_madd_606_ADD_22x22_fast_I173_un1_Y : OR3C - port map(A => N456, B => madd_28, C => N440, Y => - I173_un1_Y); - - RESMULT_madd_523_4 : XOR3 - port map(A => \a12_b[7]\, B => \a14_b[5]\, C => \a13_b[6]\, - Y => madd_523_4); - - RESMULT_madd_56_0 : XOR3 - port map(A => madd_33, B => \a0_b[6]\, C => madd_38, Y => - madd_56_0); - - RESMULT_madd_606_ADD_22x22_fast_I13_P0N : OR2 - port map(A => madd_493_0, B => madd_462, Y => N313); - - RESMULT_madd_193 : MIN3 - port map(A => madd_146, B => madd_151, C => madd_194_10, Y - => madd_193); - - RESMULT_madd_87 : MIN3 - port map(A => madd_88_2, B => madd_55, C => madd_88_4, Y - => N_38_i); - - \RESMULT_a8_b[5]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(5), Y => - \a8_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I36_Y : MAJ3 - port map(A => madd_462, B => madd_493_0, C => N309, Y => - N352); - - RESMULT_madd_606_ADD_22x22_fast_I14_G0N : NOR2A - port map(A => madd_523_0, B => madd_497, Y => N315); - - RESMULT_madd_606_ADD_22x22_fast_I193_Y_0 : XOR3 - port map(A => madd_125_0, B => madd_120_0, C => N419, Y => - \RESMULT[8]\); - - RESMULT_madd_1_605_CO2 : NOR2B - port map(A => CO1, B => madd_9_0, Y => CO2); - - RESMULT_madd_606_ADD_22x22_fast_I97_Y : NOR2B - port map(A => N375, B => N371, Y => N416); - - \RESMULT_a_i3_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(3), Y => - \a_i3_b[8]\); - - RESMULT_madd_115_4 : XOR3 - port map(A => \a1_b[7]\, B => \a2_b[6]\, C => \a0_b[8]\, Y - => N_47); - - \RESMULT_a16_b[5]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(5), Y => - \a16_b[5]\); - - \RESMULT_a6_b[3]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(3), Y => - \a6_b[3]\); - - \RESMULT_a11_b[2]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(2), Y => - \a11_b[2]\); - - RESMULT_madd_493_2 : XOR3 - port map(A => \a15_b[3]\, B => \a16_b[2]\, C => - \a17_b_i[1]\, Y => madd_493_2); - - RESMULT_madd_606_ADD_22x22_fast_I130_un1_Y : OR3B - port map(A => N365, B => N369, C => N417, Y => I130_un1_Y); - - RESMULT_madd_268_0_0 : XOR2 - port map(A => N_113_i, B => madd_268_12, Y => madd_268_0_0); - - \RESMULT_a3_b[5]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(5), Y => - \a3_b[5]\); - - \RESMULT_a2_b[5]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(5), Y => - \a2_b[5]\); - - \RESMULT_a16_b[0]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(0), Y => - \a16_b[0]\); - - RESMULT_madd_194_2 : XOR3 - port map(A => \a8_b[2]\, B => \a10_b[0]\, C => \a9_b[1]\, Y - => madd_194_2); - - RESMULT_madd_305_10 : XNOR3 - port map(A => madd_247, B => N_106_i, C => madd_252, Y => - madd_305_10); - - RESMULT_madd_9_0 : XOR3 - port map(A => madd_4_0, B => \a0_b[3]\, C => madd_3, Y => - madd_9_0); - - \REG[2]\ : DFN1E1C0 - port map(D => \RESMULT[2]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(2)); - - \REG[17]\ : DFN1E1C0 - port map(D => \RESMULT[17]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(17)); - - RESMULT_madd_606_ADD_22x22_fast_I53_Y : NOR2B - port map(A => N289, B => N286, Y => N369); - - RESMULT_madd_268_4 : XOR2 - port map(A => madd_268_4_0, B => \a8_b[4]\, Y => madd_268_4); - - RESMULT_madd_512 : MAJ3 - port map(A => \a_i11_b[8]\, B => madd_467, C => madd_472, Y - => madd_512); - - RESMULT_madd_606_ADD_22x22_fast_I40_Y : MAJ3 - port map(A => madd_385, B => madd_421_0, C => N303, Y => - N356); - - RESMULT_madd_606_ADD_22x22_fast_I202_Y_0 : XOR3 - port map(A => madd_458_0, B => madd_422, C => N550, Y => - \RESMULT[17]\); - - RESMULT_madd_606_ADD_22x22_fast_I82_Y : AO1 - port map(A => N360, B => N357, C => N356, Y => N401); - - RESMULT_madd_115_0 : XOR3 - port map(A => N_47, B => N_45_i, C => madd_82, Y => - madd_115_0); - - RESMULT_madd_493_4 : XOR3 - port map(A => \a12_b[6]\, B => \a14_b[4]\, C => \a13_b[5]\, - Y => madd_493_4); - - RESMULT_madd_606_ADD_22x22_fast_I48_un1_Y : OR3C - port map(A => madd_200, B => madd_236_0, C => N295, Y => - I48_un1_Y_i); - - RESMULT_madd_416_7 : XOR3 - port map(A => \a9_b[7]\, B => \a10_b[6]\, C => \a_i8_b[8]\, - Y => madd_416_7); - - RESMULT_madd_458_4 : XOR3 - port map(A => \a13_b[4]\, B => \a15_b[2]\, C => \a14_b[3]\, - Y => madd_458_4); - - \RESMULT_a9_b[6]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(6), Y => - \a9_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I1_P0N : OR2 - port map(A => madd_66_0, B => madd_61_0, Y => N277); - - \RESMULT_a14_b[2]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(2), Y => - \a14_b[2]\); - - RESMULT_madd_523_10 : XOR3 - port map(A => madd_482, B => madd_523_7, C => madd_487, Y - => madd_523_10); - - RESMULT_madd_316 : MIN3 - port map(A => \a14_b[0]\, B => \a12_b[2]\, C => \a13_b[1]\, - Y => N_138_i); - - RESMULT_madd_606_ADD_22x22_fast_I156_Y : AOI1 - port map(A => N450, B => N419, C => N449, Y => N553_i); - - \RESMULT_a14_b[1]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(1), Y => - \a14_b[1]\); - - \RESMULT_a15_b[6]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(6), Y => - \a15_b[6]\); - - RESMULT_madd_342_8 : XNOR3 - port map(A => madd_342_4, B => madd_342_2, C => madd_342_7, - Y => N_145_i); - - \RESMULT_a13_b[4]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(4), Y => - \a13_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I4_G0N : XA1A - port map(A => madd_124, B => madd_157_0, C => madd_126, Y - => N285); - - RESMULT_madd_606_ADD_22x22_fast_I16_P0N : OR2A - port map(A => madd_552, B => madd_568_0, Y => N322); - - \RESMULT_a_i2_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(2), Y => - \a_i2_b[8]\); - - RESMULT_madd_39_2 : XOR2 - port map(A => madd_39_2_0, B => \a4_b[1]\, Y => madd_39_2); - - \RESMULT_a6_b[2]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(2), Y => - \a6_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I41_Y : NOR2B - port map(A => N307, B => N304, Y => N357); - - RESMULT_madd_606_ADD_22x22_fast_I50_Y : MAJ3 - port map(A => madd_200, B => madd_236_0, C => N288, Y => - N366); - - RESMULT_madd_284 : MIN3 - port map(A => \a10_b[3]\, B => \a8_b[5]\, C => \a9_b[4]\, Y - => madd_284); - - RESMULT_madd_289 : MIN3 - port map(A => \a7_b[6]\, B => \a6_b[7]\, C => \a_i5_b[8]\, - Y => madd_289); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0_2 : XOR3 - port map(A => N_252, B => ADD_22x22_fast_I209_Y_0_0, C => - N_254, Y => ADD_22x22_fast_I209_Y_0_2); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_0 : AO18 - port map(A => N324, B => madd_587, C => N_253, Y => - ADD_22x22_fast_I170_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I115_Y : NOR2B - port map(A => N402, B => N394, Y => N440); - - \RESMULT_a3_b[0]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(0), Y => - \a3_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_2 : NOR3C - port map(A => I68_un1_Y, B => ADD_22x22_fast_I170_Y_0, C - => I108_un1_Y, Y => ADD_22x22_fast_I170_Y_2); - - \RESMULT_a7_b[1]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(1), Y => - \a7_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_0 : MIN3 - port map(A => madd_572, B => madd_583_0, C => N321, Y => - ADD_22x22_fast_I171_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I78_un1_Y : OR2B - port map(A => N356, B => N353, Y => I78_un1_Y_i); - - RESMULT_madd_606_ADD_22x22_fast_I124_Y : AO1 - port map(A => N411, B => N404, C => N403, Y => N449); - - \RESMULT_a0_b[6]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(6), Y => - \a0_b[6]\); - - RESMULT_madd_523_2 : XOR3 - port map(A => \a15_b[4]\, B => \a16_b[3]\, C => - \a17_b_i[2]\, Y => madd_523_2); - - RESMULT_madd_77 : MAJ3 - port map(A => \a4_b[3]\, B => \a2_b[5]\, C => \a3_b[4]\, Y - => madd_77); - - RESMULT_madd_606_ADD_22x22_fast_I2_P0N : OR2 - port map(A => madd_93_0, B => madd_67, Y => N280); - - RESMULT_madd_157_2 : XOR3 - port map(A => \a7_b[2]\, B => \a9_b[0]\, C => \a8_b[1]\, Y - => N_57); - - RESMULT_madd_606_ADD_22x22_fast_I120_un1_Y : NOR2B - port map(A => N407, B => N400, Y => I120_un1_Y); - - \RESMULT_a2_b[0]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(0), Y => - \a2_b[0]\); - - RESMULT_madd_379_7 : XOR3 - port map(A => \a8_b[7]\, B => \a9_b[6]\, C => \a_i7_b[8]\, - Y => madd_379_7); - - \RESMULT_a8_b[4]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(4), Y => - \a8_b[4]\); - - \RESMULT_a2_b[3]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(3), Y => - \a2_b[3]\); - - \RESMULT_a17_b_i[6]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(6), Y => - \a17_b_i[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_1 : AOI1B - port map(A => N401, B => N394, C => ADD_22x22_fast_I173_Y_0, - Y => ADD_22x22_fast_I173_Y_1); - - \RESMULT_a12_b[1]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(1), Y => - \a12_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I76_Y : OR2 - port map(A => N350, B => I76_un1_Y, Y => N395); - - RESMULT_madd_309 : AO13 - port map(A => madd_267, B => N_129_i, C => madd_305_12, Y - => madd_309); - - RESMULT_madd_1_605_SUM0_0 : AX1C - port map(A => alu_coef_s(1), B => alu_sample(0), C => - \a1_b[0]\, Y => \RESMULT[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I60_Y : MAJ3 - port map(A => madd_61_0, B => madd_66_0, C => N273, Y => - N376); - - RESMULT_madd_606_ADD_22x22_fast_I154_un1_Y : NOR3C - port map(A => N400, B => N408, C => N461, Y => I154_un1_Y); - - \RESMULT_a2_b[2]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(2), Y => - \a2_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I1_G0N : NOR2B - port map(A => madd_66_0, B => madd_61_0, Y => N276); - - RESMULT_madd_606_ADD_22x22_fast_I113_Y : NOR2B - port map(A => N400, B => N392, Y => N438); - - RESMULT_madd_415 : MIN3 - port map(A => N_175_i, B => madd_368, C => madd_373, Y => - madd_415); - - RESMULT_madd_606_ADD_22x22_fast_I93_Y : NOR2B - port map(A => N371, B => N367, Y => N412); - - RESMULT_madd_606_ADD_22x22_fast_I51_Y : NOR2B - port map(A => N292, B => N289, Y => N367); - - RESMULT_madd_543_0 : XOR3 - port map(A => madd_543_6, B => madd_543_4, C => madd_512, Y - => madd_543_0); - - \RESMULT_a3_b[2]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(2), Y => - \a3_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I118_un1_Y : NAND2 - port map(A => N398, B => N405, Y => I118_un1_Y); - - RESMULT_madd_493_11 : XOR3 - port map(A => madd_442, B => madd_493_4, C => madd_447, Y - => madd_493_11); - - RESMULT_madd_342_4_0 : XOR2 - port map(A => \a11_b[3]\, B => \a9_b[5]\, Y => madd_342_4_0); - - RESMULT_madd_606_ADD_22x22_fast_I44_Y : MAJ3 - port map(A => madd_311, B => madd_347_0, C => N297, Y => - N360); - - \RESMULT_a9_b[3]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(3), Y => - \a9_b[3]\); - - RESMULT_madd_416_0 : XOR2 - port map(A => madd_416_0_0, B => madd_378, Y => madd_416_0); - - RESMULT_madd_548_0 : XOR3 - port map(A => madd_543_0, B => madd_517, C => madd_522, Y - => madd_548_0); - - RESMULT_madd_606_ADD_22x22_fast_I196_Y_0_0 : XOR2 - port map(A => madd_200, B => madd_236_0, Y => - ADD_22x22_fast_I196_Y_0_0); - - \RESMULT_a4_b[4]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(4), Y => - \a4_b[4]\); - - \RESMULT_a15_b[7]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(7), Y => - \a15_b[7]\); - - RESMULT_madd_353 : MIN3 - port map(A => \a15_b[0]\, B => \a13_b[2]\, C => \a14_b[1]\, - Y => N_154_i); - - \RESMULT_a_i10_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(10), Y => - \a_i10_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I86_Y : AO1 - port map(A => N364, B => N361, C => N360, Y => N405); - - RESMULT_madd_268_12 : XOR3 - port map(A => madd_268_10, B => N_98_i, C => madd_220, Y - => madd_268_12); - - RESMULT_madd_1_605_CO1 : XA1 - port map(A => \a0_b[2]\, B => madd_0_s_0, C => CO0, Y => - CO1); - - RESMULT_madd_4_0 : XNOR3 - port map(A => \a1_b[2]\, B => \a3_b[0]\, C => \a2_b[1]\, Y - => madd_4_0); - - \RESMULT_a17_b_i[2]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(2), Y => - \a17_b_i[2]\); - - RESMULT_madd_379_12 : XOR3 - port map(A => madd_379_10, B => madd_336, C => madd_331, Y - => madd_379_12); - - RESMULT_madd_1_605_CO3 : NOR2B - port map(A => CO2, B => madd_24_0, Y => CO3); - - RESMULT_madd_606_ADD_22x22_fast_I158_un1_Y : NOR2B - port map(A => N454, B => N378, Y => - ADD_22x22_fast_I158_un1_Y); - - RESMULT_madd_194_0_0 : XOR2 - port map(A => N_81_i, B => madd_194_12, Y => madd_194_0_0); - - GND_i_0 : GND - port map(Y => GND_0); - - RESMULT_madd_606_ADD_22x22_fast_I37_Y : NOR2B - port map(A => N313, B => N310, Y => N353); - - RESMULT_madd_557 : MAJ3 - port map(A => \a16_b[5]\, B => \a15_b[6]\, C => - \a17_b_i[4]\, Y => madd_557); - - RESMULT_madd_458_13 : XOR3 - port map(A => madd_405, B => madd_458_7, C => madd_410, Y - => madd_458_13); - - RESMULT_madd_606_ADD_22x22_fast_I101_un1_Y : NOR2B - port map(A => N377, B => madd_28, Y => I101_un1_Y); - - \RESMULT_a1_b[0]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(0), Y => - \a1_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I152_un1_Y : NOR3C - port map(A => N565, B => N404, C => N396, Y => I152_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I17_G0N : NOR2B - port map(A => madd_583_0, B => madd_572, Y => N324); - - RESMULT_madd_606_ADD_22x22_fast_I61_Y : NOR2B - port map(A => N277, B => N274, Y => N377); - - RESMULT_madd_457 : MAJ3 - port map(A => madd_458_9, B => madd_415, C => madd_458_10, - Y => madd_457); - - RESMULT_madd_88_0 : XOR3 - port map(A => madd_88_8, B => madd_88_7, C => madd_60, Y - => madd_88_0); - - RESMULT_madd_606_ADD_22x22_fast_I130_Y : OR3A - port map(A => I130_un1_Y, B => ADD_22x22_fast_I90_un1_Y, C - => N364, Y => N455); - - \RESMULT_a4_b[1]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(1), Y => - \a4_b[1]\); - - \RESMULT_a13_b[6]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(6), Y => - \a13_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I54_Y : OR2A - port map(A => I54_un1_Y_i, B => N285, Y => N370); - - \RESMULT_a2_b[7]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(7), Y => - \a2_b[7]\); - - RESMULT_madd_168 : MIN3 - port map(A => \a10_b[0]\, B => \a8_b[2]\, C => \a9_b[1]\, Y - => N_74_i); - - RESMULT_madd_606_ADD_22x22_fast_I152_Y : NOR2 - port map(A => ADD_22x22_fast_I152_Y_0, B => I152_un1_Y, Y - => N541); - - RESMULT_madd_606_ADD_22x22_fast_I196_Y_0 : XOR2 - port map(A => ADD_22x22_fast_I196_Y_0_0, B => N568, Y => - \RESMULT[11]\); - - RESMULT_madd_109 : MIN3 - port map(A => \a2_b[6]\, B => \a0_b[8]\, C => \a1_b[7]\, Y - => N_48); - - \RESMULT_a11_b[7]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(7), Y => - \a11_b[7]\); - - \RESMULT_a10_b[2]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(2), Y => - \a10_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I126_Y : OR2 - port map(A => N405, B => I126_un1_Y, Y => N451); - - \RESMULT_a17_b_i[7]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(7), Y => - \a17_b_i[7]\); - - RESMULT_madd_1_605_CO0 : NOR3C - port map(A => alu_coef_s(1), B => alu_sample(0), C => - \a1_b[0]\, Y => CO0); - - RESMULT_madd_573_0 : XOR3 - port map(A => \a16_b[6]\, B => \a15_b[7]\, C => - \a17_b_i[5]\, Y => madd_573_0); - - \RESMULT_a7_b[2]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(2), Y => - \a7_b[2]\); - - \RESMULT_a6_b[4]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(4), Y => - \a6_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I153_Y_0 : AND2 - port map(A => I118_un1_Y, B => N397_i, Y => - ADD_22x22_fast_I153_Y_0); - - RESMULT_madd_92 : MIN3 - port map(A => madd_88_7, B => madd_60, C => madd_88_8, Y - => madd_92); - - RESMULT_madd_416_0_0 : XOR2 - port map(A => madd_416_8, B => N_179, Y => madd_416_0_0); - - RESMULT_madd_400 : MAJ3 - port map(A => \a10_b[6]\, B => \a9_b[7]\, C => \a_i8_b[8]\, - Y => madd_400); - - RESMULT_madd_390 : MAJ3 - port map(A => \a16_b[0]\, B => \a14_b[2]\, C => \a15_b[1]\, - Y => madd_390); - - \RESMULT_a_i7_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(7), Y => - \a_i7_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I49_Y : NOR2B - port map(A => N295, B => N292, Y => N365); - - RESMULT_madd_606_ADD_22x22_fast_I12_G0N : NOR2B - port map(A => madd_458_0, B => madd_422, Y => N309); - - RESMULT_madd_568_0 : XOR3 - port map(A => madd_568_6, B => madd_568_4, C => madd_547, Y - => madd_568_0); - - RESMULT_madd_427_1 : AOI1B - port map(A => alu_coef_s(0), B => \a16_b[1]\, C => - alu_sample(17), Y => madd_427_1); - - RESMULT_madd_188 : MIN3 - port map(A => madd_194_2, B => madd_194_4, C => madd_194_7, - Y => N_82_i); - - \RESMULT_a8_b[7]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(7), Y => - \a8_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I15_P0N : OR2A - port map(A => madd_527, B => madd_548_0, Y => N319); - - RESMULT_madd_543_6 : XOR3 - port map(A => madd_507, B => madd_543_2, C => madd_502, Y - => madd_543_6); - - RESMULT_madd_136 : MAJ3 - port map(A => \a6_b[3]\, B => \a4_b[5]\, C => \a5_b[4]\, Y - => madd_136); - - \RESMULT_a3_b[4]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(4), Y => - \a3_b[4]\); - - RESMULT_madd_373 : MIN3 - port map(A => madd_379_2, B => madd_379_4, C => madd_379_7, - Y => madd_373); - - RESMULT_madd_578_0 : XOR2 - port map(A => madd_578_0_0, B => madd_557, Y => madd_578_0); - - \RESMULT_a5_b[5]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(5), Y => - \a5_b[5]\); - - \RESMULT_a15_b[5]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(5), Y => - \a15_b[5]\); - - RESMULT_madd_231_2 : XOR3 - port map(A => \a9_b[2]\, B => \a11_b[0]\, C => \a10_b[1]\, - Y => madd_231_2); - - \RESMULT_a5_b[0]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(0), Y => - \a5_b[0]\); - - RESMULT_madd_131 : MAJ3 - port map(A => \a9_b[0]\, B => \a7_b[2]\, C => \a8_b[1]\, Y - => madd_131); - - RESMULT_madd_606_ADD_22x22_fast_I128_Y : AO1 - port map(A => N415, B => N408, C => N407, Y => N453); - - RESMULT_madd_577 : MAJ3 - port map(A => \a15_b[7]\, B => \a16_b[6]\, C => - \a17_b_i[5]\, Y => madd_577); - - RESMULT_madd_342_2_0 : XOR2 - port map(A => \a14_b[0]\, B => \a12_b[2]\, Y => - madd_342_2_0); - - RESMULT_madd_305_4 : XOR2 - port map(A => madd_305_4_0, B => \a9_b[4]\, Y => madd_305_4); - - RESMULT_madd_61_4 : XOR3 - port map(A => \a1_b[5]\, B => \a3_b[3]\, C => \a2_b[4]\, Y - => madd_61_4); - - RESMULT_madd_477 : MAJ3 - port map(A => \a11_b[7]\, B => madd_427_1, C => - \a_i10_b[8]\, Y => madd_477); - - RESMULT_madd_416_12 : XNOR3 - port map(A => madd_368, B => N_175_i, C => madd_373, Y => - N_179); - - RESMULT_madd_606_ADD_22x22_fast_I192_Y_0 : XOR3 - port map(A => madd_93_0, B => madd_67, C => N421, Y => - \RESMULT[7]\); - - RESMULT_madd_305_8_0 : XOR2 - port map(A => madd_305_2, B => madd_305_4, Y => - madd_305_8_0); - - RESMULT_madd_194_7 : XOR3 - port map(A => \a3_b[7]\, B => \a4_b[6]\, C => \a_i2_b[8]\, - Y => madd_194_7); - - RESMULT_madd_163 : NOR2A - port map(A => madd_157_0, B => madd_124, Y => madd_163); - - \RESMULT_a13_b[5]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(5), Y => - \a13_b[5]\); - - \RESMULT_a1_b[1]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(1), Y => - \a1_b[1]\); - - RESMULT_madd_237 : XA1B - port map(A => madd_193, B => madd_231_0_0, C => madd_198, Y - => madd_237); - - RESMULT_madd_606_ADD_22x22_fast_I18_P0N : OR2A - port map(A => madd_587, B => N_253, Y => N328); - - RESMULT_madd_593_0 : XOR3 - port map(A => madd_577, B => N_251, C => madd_582, Y => - N_253); - - RESMULT_madd_268_4_0 : XOR2 - port map(A => \a9_b[3]\, B => \a7_b[5]\, Y => madd_268_4_0); - - RESMULT_madd_379_2 : XOR3 - port map(A => \a13_b[2]\, B => \a15_b[0]\, C => \a14_b[1]\, - Y => madd_379_2); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - RESMULT_madd_606_ADD_22x22_fast_I3_G0N : NOR2B - port map(A => madd_125_0, B => madd_120_0, Y => N282); - - RESMULT_madd_493_0 : XOR3 - port map(A => madd_493_12, B => madd_493_11, C => madd_457, - Y => madd_493_0); - - RESMULT_madd_33 : MAJ3 - port map(A => \a5_b[0]\, B => \a3_b[2]\, C => \a4_b[1]\, Y - => madd_33); - - RESMULT_madd_305_7_0 : XOR2 - port map(A => \a7_b[6]\, B => \a6_b[7]\, Y => madd_305_7_0); - - RESMULT_madd_606_ADD_22x22_fast_I59_Y : NOR2B - port map(A => N280, B => N277, Y => N375); - - \RESMULT_a8_b[0]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(0), Y => - \a8_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I133_Y : OR2 - port map(A => N413, B => I133_un1_Y, Y => N568); - - RESMULT_madd_183 : MIN3 - port map(A => madd_131, B => madd_136, C => madd_141, Y => - madd_183); - - RESMULT_madd_606_ADD_22x22_fast_I0_G0N : NOR2B - port map(A => CO3, B => madd_44_0, Y => N273); - - \RESMULT_a11_b[4]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(4), Y => - \a11_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_3 : OAI1 - port map(A => ADD_22x22_fast_I170_un1_Y_0, B => N449, C => - ADD_22x22_fast_I170_Y_3_0, Y => ADD_22x22_fast_I170_Y_3); - - RESMULT_madd_606_ADD_22x22_fast_I94_Y : AO1 - port map(A => N372, B => N369, C => N368, Y => N413); - - RESMULT_madd_606_ADD_22x22_fast_I77_Y : NOR2B - port map(A => N355, B => N351, Y => N396); - - \RESMULT_a0_b[0]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(0), Y => - \RESMULT[0]\); - - RESMULT_madd_39_0 : XOR3 - port map(A => madd_39_2, B => N_15, C => N_8, Y => - madd_39_0); - - RESMULT_madd_606_ADD_22x22_fast_I33_Y : OR2B - port map(A => N319, B => N316, Y => N349); - - RESMULT_madd_606_ADD_22x22_fast_I208_Y_0 : XNOR3 - port map(A => madd_587, B => N_253, C => N535, Y => - \RESMULT[23]\); - - \RESMULT_a_i1_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(1), Y => - \a_i1_b[8]\); - - RESMULT_madd_458_14 : XOR3 - port map(A => madd_458_9, B => madd_458_10, C => madd_415, - Y => madd_458_14); - - RESMULT_madd_342_10 : XNOR3 - port map(A => madd_284, B => N_122_i, C => madd_289, Y => - madd_342_10); - - VCC_i : VCC - port map(Y => \VCC\); - - RESMULT_madd_597 : MIN3 - port map(A => madd_577, B => madd_582, C => N_251, Y => - N_254); - - RESMULT_madd_582_0 : NOR3B - port map(A => alu_coef_s(8), B => madd_582_0_tz, C => - alu_sample(14), Y => madd_582_0); - - \RESMULT_a7_b[4]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(4), Y => - \a7_b[4]\); - - RESMULT_madd_358 : MIN3 - port map(A => \a12_b[3]\, B => \a10_b[5]\, C => \a11_b[4]\, - Y => madd_358); - - \RESMULT_a10_b[1]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(1), Y => - \a10_b[1]\); - - RESMULT_madd_497 : MIN3 - port map(A => madd_493_11, B => madd_457, C => madd_493_12, - Y => madd_497); - - RESMULT_madd_395 : MAJ3 - port map(A => \a13_b[3]\, B => \a11_b[5]\, C => \a12_b[4]\, - Y => madd_395); - - \RESMULT_a10_b[3]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(3), Y => - \a10_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I69_Y : NOR3C - port map(A => N319, B => N322, C => N343, Y => N388); - - RESMULT_madd_268_8 : XNOR3 - port map(A => madd_268_4, B => madd_268_2, C => madd_268_7, - Y => N_113_i); - - RESMULT_madd_1_605_SUM1_0 : XOR3 - port map(A => \a0_b[2]\, B => madd_0_s_0, C => CO0, Y => - \RESMULT[2]\); - - \REG[9]\ : DFN1E1C0 - port map(D => \RESMULT[9]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(9)); - - RESMULT_madd_606_ADD_22x22_fast_I203_Y_0 : XNOR3 - port map(A => madd_462, B => madd_493_0, C => N547, Y => - \RESMULT[18]\); - - \RESMULT_a15_b[2]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(2), Y => - \a15_b[2]\); - - RESMULT_madd_379_8 : XNOR3 - port map(A => madd_379_4, B => madd_379_2, C => madd_379_7, - Y => N_161_i); - - RESMULT_madd_82 : MIN3 - port map(A => \a1_b[6]\, B => madd_50, C => \a0_b[7]\, Y - => madd_82); - - RESMULT_madd_606_ADD_22x22_fast_I48_Y : OR2A - port map(A => I48_un1_Y_i, B => N294, Y => N364); - - RESMULT_madd_606_ADD_22x22_fast_I45_Y : NOR2B - port map(A => N301, B => N298, Y => N361); - - \RESMULT_a5_b[4]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(4), Y => - \a5_b[4]\); - - RESMULT_madd_416_8 : XOR3 - port map(A => madd_416_4, B => madd_416_2, C => madd_416_7, - Y => madd_416_8); - - RESMULT_madd_606_ADD_22x22_fast_I12_P0N : OR2 - port map(A => madd_458_0, B => madd_422, Y => N310); - - RESMULT_madd_606_ADD_22x22_fast_I195_Y_0 : XOR3 - port map(A => madd_163, B => madd_199_0, C => N461, Y => - \RESMULT[10]\); - - \RESMULT_a1_b[2]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(2), Y => - \a1_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I87_Y : OR2B - port map(A => N365, B => N361, Y => N406); - - RESMULT_madd_126 : NOR3B - port map(A => madd_88_0, B => madd_115_0, C => madd_65, Y - => madd_126); - - RESMULT_madd_493_6 : XOR2 - port map(A => madd_493_6_0, B => madd_427_1, Y => - madd_493_6); - - \RESMULT_a14_b[5]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(5), Y => - \a14_b[5]\); - - RESMULT_madd_161 : MIN3 - port map(A => madd_157_11, B => madd_119, C => madd_157_12, - Y => madd_161); - - RESMULT_madd_606_ADD_22x22_fast_I194_Y_0_0 : XNOR3 - port map(A => madd_124, B => madd_157_0, C => madd_126, Y - => ADD_22x22_fast_I194_Y_0_0); - - \RESMULT_a4_b[0]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(0), Y => - \a4_b[0]\); - - \RESMULT_a12_b[4]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(4), Y => - \a12_b[4]\); - - RESMULT_madd_347_0 : XNOR3 - port map(A => madd_304, B => madd_342_0_0, C => madd_309, Y - => madd_347_0); - - RESMULT_madd_205 : MIN3 - port map(A => \a11_b[0]\, B => \a9_b[2]\, C => \a10_b[1]\, - Y => N_90_i); - - RESMULT_madd_13 : MIN3 - port map(A => \a0_b[3]\, B => madd_3, C => madd_4_0, Y => - madd_13); - - RESMULT_madd_606_ADD_22x22_fast_I207_Y_0 : AX1E - port map(A => I172_un1_Y, B => ADD_22x22_fast_I172_Y_2, C - => ADD_22x22_fast_I207_Y_0_0, Y => \RESMULT[22]\); - - RESMULT_madd_606_ADD_22x22_fast_I7_G0N : NOR2B - port map(A => madd_273_0, B => madd_237, Y => N294); - - \RESMULT_a_i8_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(8), Y => - \a_i8_b[8]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC is - - port( sample_out_s : out std_logic_vector(17 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_ctrl : in std_logic_vector(2 downto 0); - lclk_c : in std_logic; - rstn : in std_logic - ); - -end MAC; - -architecture DEF_ARCH of MAC is - - component MAC_REG_18 - port( alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - OP1_2C_D : out std_logic_vector(17 downto 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MAC_REG_9 - port( alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - OP2_2C_D : out std_logic_vector(8 downto 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MAC_REG_1_4 - port( MACMUX2sel_D : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - MACMUX2sel_D_D : out std_logic - ); - end component; - - component MAC_CONTROLER - port( alu_ctrl : in std_logic_vector(1 downto 0) := (others => 'U'); - mult : out std_logic; - N_4 : out std_logic; - MACMUX2sel : out std_logic; - mult_0 : out std_logic - ); - end component; - - component MAC_MUX - port( OP1_2C_D : in std_logic_vector(17 downto 0) := (others => 'U'); - MULTout : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinB : out std_logic_vector(24 downto 0); - OP2_2C_D : in std_logic_vector(8 downto 0) := (others => 'U'); - ADDERout : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinA : out std_logic_vector(24 downto 0); - MACMUXsel_D : in std_logic := 'U'; - MACMUXsel_D_1 : in std_logic := 'U'; - MACMUXsel_D_0 : in std_logic := 'U' - ); - end component; - - component MAC_REG_27 - port( MULTout : in std_logic_vector(24 downto 7) := (others => 'U'); - MULTout_D : out std_logic_vector(24 downto 7); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component MAC_REG_1_1 - port( alu_ctrl : in std_logic_vector(0 to 0) := (others => 'U'); - add_D : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - add_D_0 : out std_logic - ); - end component; - - component MAC_REG_1_3 - port( MACMUX2sel : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - MACMUX2sel_D : out std_logic - ); - end component; - - component MAC_REG_1 - port( alu_ctrl : in std_logic_vector(2 to 2) := (others => 'U'); - clr_MAC_D : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - clr_MAC_D_0 : out std_logic - ); - end component; - - component Adder - port( ADDERout : out std_logic_vector(24 downto 0); - ADDERinB : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinA : in std_logic_vector(24 downto 0) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - clr_MAC_D : in std_logic := 'U'; - add_D : in std_logic := 'U'; - clr_MAC_D_0 : in std_logic := 'U'; - MACMUX2sel_D : in std_logic := 'U'; - add_D_0 : in std_logic := 'U' - ); - end component; - - component MAC_MUX2 - port( MULTout_D : in std_logic_vector(24 downto 7) := (others => 'U'); - ADDERout : in std_logic_vector(24 downto 7) := (others => 'U'); - sample_out_s : out std_logic_vector(17 downto 0); - MACMUX2sel_D_D : in std_logic := 'U' - ); - end component; - - component MAC_REG_1_2 - port( MACMUXsel_D : out std_logic; - MACMUXsel_D_0 : out std_logic; - N_4 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - MACMUXsel_D_1 : out std_logic - ); - end component; - - component Multiplier - port( MULTout : out std_logic_vector(24 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - mult : in std_logic := 'U'; - mult_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal mult, N_4, MACMUX2sel, mult_0, \MULTout[0]\, - \MULTout[1]\, \MULTout[2]\, \MULTout[3]\, \MULTout[4]\, - \MULTout[5]\, \MULTout[6]\, \MULTout[7]\, \MULTout[8]\, - \MULTout[9]\, \MULTout[10]\, \MULTout[11]\, \MULTout[12]\, - \MULTout[13]\, \MULTout[14]\, \MULTout[15]\, - \MULTout[16]\, \MULTout[17]\, \MULTout[18]\, - \MULTout[19]\, \MULTout[20]\, \MULTout[21]\, - \MULTout[22]\, \MULTout[23]\, \MULTout[24]\, - \ADDERout[0]\, \ADDERout[1]\, \ADDERout[2]\, - \ADDERout[3]\, \ADDERout[4]\, \ADDERout[5]\, - \ADDERout[6]\, \ADDERout[7]\, \ADDERout[8]\, - \ADDERout[9]\, \ADDERout[10]\, \ADDERout[11]\, - \ADDERout[12]\, \ADDERout[13]\, \ADDERout[14]\, - \ADDERout[15]\, \ADDERout[16]\, \ADDERout[17]\, - \ADDERout[18]\, \ADDERout[19]\, \ADDERout[20]\, - \ADDERout[21]\, \ADDERout[22]\, \ADDERout[23]\, - \ADDERout[24]\, \ADDERinB[0]\, \ADDERinB[1]\, - \ADDERinB[2]\, \ADDERinB[3]\, \ADDERinB[4]\, - \ADDERinB[5]\, \ADDERinB[6]\, \ADDERinB[7]\, - \ADDERinB[8]\, \ADDERinB[9]\, \ADDERinB[10]\, - \ADDERinB[11]\, \ADDERinB[12]\, \ADDERinB[13]\, - \ADDERinB[14]\, \ADDERinB[15]\, \ADDERinB[16]\, - \ADDERinB[17]\, \ADDERinB[18]\, \ADDERinB[19]\, - \ADDERinB[20]\, \ADDERinB[21]\, \ADDERinB[22]\, - \ADDERinB[23]\, \ADDERinB[24]\, \ADDERinA[0]\, - \ADDERinA[1]\, \ADDERinA[2]\, \ADDERinA[3]\, - \ADDERinA[4]\, \ADDERinA[5]\, \ADDERinA[6]\, - \ADDERinA[7]\, \ADDERinA[8]\, \ADDERinA[9]\, - \ADDERinA[10]\, \ADDERinA[11]\, \ADDERinA[12]\, - \ADDERinA[13]\, \ADDERinA[14]\, \ADDERinA[15]\, - \ADDERinA[16]\, \ADDERinA[17]\, \ADDERinA[18]\, - \ADDERinA[19]\, \ADDERinA[20]\, \ADDERinA[21]\, - \ADDERinA[22]\, \ADDERinA[23]\, \ADDERinA[24]\, clr_MAC_D, - add_D, clr_MAC_D_0, MACMUX2sel_D, add_D_0, \OP1_2C_D[0]\, - \OP1_2C_D[1]\, \OP1_2C_D[2]\, \OP1_2C_D[3]\, - \OP1_2C_D[4]\, \OP1_2C_D[5]\, \OP1_2C_D[6]\, - \OP1_2C_D[7]\, \OP1_2C_D[8]\, \OP1_2C_D[9]\, - \OP1_2C_D[10]\, \OP1_2C_D[11]\, \OP1_2C_D[12]\, - \OP1_2C_D[13]\, \OP1_2C_D[14]\, \OP1_2C_D[15]\, - \OP1_2C_D[16]\, \OP1_2C_D[17]\, \OP2_2C_D[0]\, - \OP2_2C_D[1]\, \OP2_2C_D[2]\, \OP2_2C_D[3]\, - \OP2_2C_D[4]\, \OP2_2C_D[5]\, \OP2_2C_D[6]\, - \OP2_2C_D[7]\, \OP2_2C_D[8]\, \MULTout_D[7]\, - \MULTout_D[8]\, \MULTout_D[9]\, \MULTout_D[10]\, - \MULTout_D[11]\, \MULTout_D[12]\, \MULTout_D[13]\, - \MULTout_D[14]\, \MULTout_D[15]\, \MULTout_D[16]\, - \MULTout_D[17]\, \MULTout_D[18]\, \MULTout_D[19]\, - \MULTout_D[20]\, \MULTout_D[21]\, \MULTout_D[22]\, - \MULTout_D[23]\, \MULTout_D[24]\, MACMUXsel_D, - MACMUXsel_D_0, MACMUXsel_D_1, MACMUX2sel_D_D, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : MAC_REG_18 - Use entity work.MAC_REG_18(DEF_ARCH); - for all : MAC_REG_9 - Use entity work.MAC_REG_9(DEF_ARCH); - for all : MAC_REG_1_4 - Use entity work.MAC_REG_1_4(DEF_ARCH); - for all : MAC_CONTROLER - Use entity work.MAC_CONTROLER(DEF_ARCH); - for all : MAC_MUX - Use entity work.MAC_MUX(DEF_ARCH); - for all : MAC_REG_27 - Use entity work.MAC_REG_27(DEF_ARCH); - for all : MAC_REG_1_1 - Use entity work.MAC_REG_1_1(DEF_ARCH); - for all : MAC_REG_1_3 - Use entity work.MAC_REG_1_3(DEF_ARCH); - for all : MAC_REG_1 - Use entity work.MAC_REG_1(DEF_ARCH); - for all : Adder - Use entity work.Adder(DEF_ARCH); - for all : MAC_MUX2 - Use entity work.MAC_MUX2(DEF_ARCH); - for all : MAC_REG_1_2 - Use entity work.MAC_REG_1_2(DEF_ARCH); - for all : Multiplier - Use entity work.Multiplier(DEF_ARCH); -begin - - - OP1REG : MAC_REG_18 - port map(alu_sample(17) => alu_sample(17), alu_sample(16) - => alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), - OP1_2C_D(17) => \OP1_2C_D[17]\, OP1_2C_D(16) => - \OP1_2C_D[16]\, OP1_2C_D(15) => \OP1_2C_D[15]\, - OP1_2C_D(14) => \OP1_2C_D[14]\, OP1_2C_D(13) => - \OP1_2C_D[13]\, OP1_2C_D(12) => \OP1_2C_D[12]\, - OP1_2C_D(11) => \OP1_2C_D[11]\, OP1_2C_D(10) => - \OP1_2C_D[10]\, OP1_2C_D(9) => \OP1_2C_D[9]\, OP1_2C_D(8) - => \OP1_2C_D[8]\, OP1_2C_D(7) => \OP1_2C_D[7]\, - OP1_2C_D(6) => \OP1_2C_D[6]\, OP1_2C_D(5) => - \OP1_2C_D[5]\, OP1_2C_D(4) => \OP1_2C_D[4]\, OP1_2C_D(3) - => \OP1_2C_D[3]\, OP1_2C_D(2) => \OP1_2C_D[2]\, - OP1_2C_D(1) => \OP1_2C_D[1]\, OP1_2C_D(0) => - \OP1_2C_D[0]\, rstn => rstn, lclk_c => lclk_c); - - GND_i_0 : GND - port map(Y => GND_0); - - OP2REG : MAC_REG_9 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - OP2_2C_D(8) => \OP2_2C_D[8]\, OP2_2C_D(7) => - \OP2_2C_D[7]\, OP2_2C_D(6) => \OP2_2C_D[6]\, OP2_2C_D(5) - => \OP2_2C_D[5]\, OP2_2C_D(4) => \OP2_2C_D[4]\, - OP2_2C_D(3) => \OP2_2C_D[3]\, OP2_2C_D(2) => - \OP2_2C_D[2]\, OP2_2C_D(1) => \OP2_2C_D[1]\, OP2_2C_D(0) - => \OP2_2C_D[0]\, rstn => rstn, lclk_c => lclk_c); - - VCC_i : VCC - port map(Y => \VCC\); - - MACMUX2selREG2 : MAC_REG_1_4 - port map(MACMUX2sel_D => MACMUX2sel_D, rstn => rstn, lclk_c - => lclk_c, MACMUX2sel_D_D => MACMUX2sel_D_D); - - MAC_CONTROLER1 : MAC_CONTROLER - port map(alu_ctrl(1) => alu_ctrl(1), alu_ctrl(0) => - alu_ctrl(0), mult => mult, N_4 => N_4, MACMUX2sel => - MACMUX2sel, mult_0 => mult_0); - - MACMUX_inst : MAC_MUX - port map(OP1_2C_D(17) => \OP1_2C_D[17]\, OP1_2C_D(16) => - \OP1_2C_D[16]\, OP1_2C_D(15) => \OP1_2C_D[15]\, - OP1_2C_D(14) => \OP1_2C_D[14]\, OP1_2C_D(13) => - \OP1_2C_D[13]\, OP1_2C_D(12) => \OP1_2C_D[12]\, - OP1_2C_D(11) => \OP1_2C_D[11]\, OP1_2C_D(10) => - \OP1_2C_D[10]\, OP1_2C_D(9) => \OP1_2C_D[9]\, OP1_2C_D(8) - => \OP1_2C_D[8]\, OP1_2C_D(7) => \OP1_2C_D[7]\, - OP1_2C_D(6) => \OP1_2C_D[6]\, OP1_2C_D(5) => - \OP1_2C_D[5]\, OP1_2C_D(4) => \OP1_2C_D[4]\, OP1_2C_D(3) - => \OP1_2C_D[3]\, OP1_2C_D(2) => \OP1_2C_D[2]\, - OP1_2C_D(1) => \OP1_2C_D[1]\, OP1_2C_D(0) => - \OP1_2C_D[0]\, MULTout(24) => \MULTout[24]\, MULTout(23) - => \MULTout[23]\, MULTout(22) => \MULTout[22]\, - MULTout(21) => \MULTout[21]\, MULTout(20) => - \MULTout[20]\, MULTout(19) => \MULTout[19]\, MULTout(18) - => \MULTout[18]\, MULTout(17) => \MULTout[17]\, - MULTout(16) => \MULTout[16]\, MULTout(15) => - \MULTout[15]\, MULTout(14) => \MULTout[14]\, MULTout(13) - => \MULTout[13]\, MULTout(12) => \MULTout[12]\, - MULTout(11) => \MULTout[11]\, MULTout(10) => - \MULTout[10]\, MULTout(9) => \MULTout[9]\, MULTout(8) => - \MULTout[8]\, MULTout(7) => \MULTout[7]\, MULTout(6) => - \MULTout[6]\, MULTout(5) => \MULTout[5]\, MULTout(4) => - \MULTout[4]\, MULTout(3) => \MULTout[3]\, MULTout(2) => - \MULTout[2]\, MULTout(1) => \MULTout[1]\, MULTout(0) => - \MULTout[0]\, ADDERinB(24) => \ADDERinB[24]\, - ADDERinB(23) => \ADDERinB[23]\, ADDERinB(22) => - \ADDERinB[22]\, ADDERinB(21) => \ADDERinB[21]\, - ADDERinB(20) => \ADDERinB[20]\, ADDERinB(19) => - \ADDERinB[19]\, ADDERinB(18) => \ADDERinB[18]\, - ADDERinB(17) => \ADDERinB[17]\, ADDERinB(16) => - \ADDERinB[16]\, ADDERinB(15) => \ADDERinB[15]\, - ADDERinB(14) => \ADDERinB[14]\, ADDERinB(13) => - \ADDERinB[13]\, ADDERinB(12) => \ADDERinB[12]\, - ADDERinB(11) => \ADDERinB[11]\, ADDERinB(10) => - \ADDERinB[10]\, ADDERinB(9) => \ADDERinB[9]\, ADDERinB(8) - => \ADDERinB[8]\, ADDERinB(7) => \ADDERinB[7]\, - ADDERinB(6) => \ADDERinB[6]\, ADDERinB(5) => - \ADDERinB[5]\, ADDERinB(4) => \ADDERinB[4]\, ADDERinB(3) - => \ADDERinB[3]\, ADDERinB(2) => \ADDERinB[2]\, - ADDERinB(1) => \ADDERinB[1]\, ADDERinB(0) => - \ADDERinB[0]\, OP2_2C_D(8) => \OP2_2C_D[8]\, OP2_2C_D(7) - => \OP2_2C_D[7]\, OP2_2C_D(6) => \OP2_2C_D[6]\, - OP2_2C_D(5) => \OP2_2C_D[5]\, OP2_2C_D(4) => - \OP2_2C_D[4]\, OP2_2C_D(3) => \OP2_2C_D[3]\, OP2_2C_D(2) - => \OP2_2C_D[2]\, OP2_2C_D(1) => \OP2_2C_D[1]\, - OP2_2C_D(0) => \OP2_2C_D[0]\, ADDERout(24) => - \ADDERout[24]\, ADDERout(23) => \ADDERout[23]\, - ADDERout(22) => \ADDERout[22]\, ADDERout(21) => - \ADDERout[21]\, ADDERout(20) => \ADDERout[20]\, - ADDERout(19) => \ADDERout[19]\, ADDERout(18) => - \ADDERout[18]\, ADDERout(17) => \ADDERout[17]\, - ADDERout(16) => \ADDERout[16]\, ADDERout(15) => - \ADDERout[15]\, ADDERout(14) => \ADDERout[14]\, - ADDERout(13) => \ADDERout[13]\, ADDERout(12) => - \ADDERout[12]\, ADDERout(11) => \ADDERout[11]\, - ADDERout(10) => \ADDERout[10]\, ADDERout(9) => - \ADDERout[9]\, ADDERout(8) => \ADDERout[8]\, ADDERout(7) - => \ADDERout[7]\, ADDERout(6) => \ADDERout[6]\, - ADDERout(5) => \ADDERout[5]\, ADDERout(4) => - \ADDERout[4]\, ADDERout(3) => \ADDERout[3]\, ADDERout(2) - => \ADDERout[2]\, ADDERout(1) => \ADDERout[1]\, - ADDERout(0) => \ADDERout[0]\, ADDERinA(24) => - \ADDERinA[24]\, ADDERinA(23) => \ADDERinA[23]\, - ADDERinA(22) => \ADDERinA[22]\, ADDERinA(21) => - \ADDERinA[21]\, ADDERinA(20) => \ADDERinA[20]\, - ADDERinA(19) => \ADDERinA[19]\, ADDERinA(18) => - \ADDERinA[18]\, ADDERinA(17) => \ADDERinA[17]\, - ADDERinA(16) => \ADDERinA[16]\, ADDERinA(15) => - \ADDERinA[15]\, ADDERinA(14) => \ADDERinA[14]\, - ADDERinA(13) => \ADDERinA[13]\, ADDERinA(12) => - \ADDERinA[12]\, ADDERinA(11) => \ADDERinA[11]\, - ADDERinA(10) => \ADDERinA[10]\, ADDERinA(9) => - \ADDERinA[9]\, ADDERinA(8) => \ADDERinA[8]\, ADDERinA(7) - => \ADDERinA[7]\, ADDERinA(6) => \ADDERinA[6]\, - ADDERinA(5) => \ADDERinA[5]\, ADDERinA(4) => - \ADDERinA[4]\, ADDERinA(3) => \ADDERinA[3]\, ADDERinA(2) - => \ADDERinA[2]\, ADDERinA(1) => \ADDERinA[1]\, - ADDERinA(0) => \ADDERinA[0]\, MACMUXsel_D => MACMUXsel_D, - MACMUXsel_D_1 => MACMUXsel_D_1, MACMUXsel_D_0 => - MACMUXsel_D_0); - - MULToutREG : MAC_REG_27 - port map(MULTout(24) => \MULTout[24]\, MULTout(23) => - \MULTout[23]\, MULTout(22) => \MULTout[22]\, MULTout(21) - => \MULTout[21]\, MULTout(20) => \MULTout[20]\, - MULTout(19) => \MULTout[19]\, MULTout(18) => - \MULTout[18]\, MULTout(17) => \MULTout[17]\, MULTout(16) - => \MULTout[16]\, MULTout(15) => \MULTout[15]\, - MULTout(14) => \MULTout[14]\, MULTout(13) => - \MULTout[13]\, MULTout(12) => \MULTout[12]\, MULTout(11) - => \MULTout[11]\, MULTout(10) => \MULTout[10]\, - MULTout(9) => \MULTout[9]\, MULTout(8) => \MULTout[8]\, - MULTout(7) => \MULTout[7]\, MULTout_D(24) => - \MULTout_D[24]\, MULTout_D(23) => \MULTout_D[23]\, - MULTout_D(22) => \MULTout_D[22]\, MULTout_D(21) => - \MULTout_D[21]\, MULTout_D(20) => \MULTout_D[20]\, - MULTout_D(19) => \MULTout_D[19]\, MULTout_D(18) => - \MULTout_D[18]\, MULTout_D(17) => \MULTout_D[17]\, - MULTout_D(16) => \MULTout_D[16]\, MULTout_D(15) => - \MULTout_D[15]\, MULTout_D(14) => \MULTout_D[14]\, - MULTout_D(13) => \MULTout_D[13]\, MULTout_D(12) => - \MULTout_D[12]\, MULTout_D(11) => \MULTout_D[11]\, - MULTout_D(10) => \MULTout_D[10]\, MULTout_D(9) => - \MULTout_D[9]\, MULTout_D(8) => \MULTout_D[8]\, - MULTout_D(7) => \MULTout_D[7]\, rstn => rstn, lclk_c => - lclk_c); - - GND_i : GND - port map(Y => \GND\); - - addREG : MAC_REG_1_1 - port map(alu_ctrl(0) => alu_ctrl(0), add_D => add_D, rstn - => rstn, lclk_c => lclk_c, add_D_0 => add_D_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - MACMUX2selREG : MAC_REG_1_3 - port map(MACMUX2sel => MACMUX2sel, rstn => rstn, lclk_c => - lclk_c, MACMUX2sel_D => MACMUX2sel_D); - - clr_MACREG1 : MAC_REG_1 - port map(alu_ctrl(2) => alu_ctrl(2), clr_MAC_D => clr_MAC_D, - rstn => rstn, lclk_c => lclk_c, clr_MAC_D_0 => - clr_MAC_D_0); - - adder_inst : Adder - port map(ADDERout(24) => \ADDERout[24]\, ADDERout(23) => - \ADDERout[23]\, ADDERout(22) => \ADDERout[22]\, - ADDERout(21) => \ADDERout[21]\, ADDERout(20) => - \ADDERout[20]\, ADDERout(19) => \ADDERout[19]\, - ADDERout(18) => \ADDERout[18]\, ADDERout(17) => - \ADDERout[17]\, ADDERout(16) => \ADDERout[16]\, - ADDERout(15) => \ADDERout[15]\, ADDERout(14) => - \ADDERout[14]\, ADDERout(13) => \ADDERout[13]\, - ADDERout(12) => \ADDERout[12]\, ADDERout(11) => - \ADDERout[11]\, ADDERout(10) => \ADDERout[10]\, - ADDERout(9) => \ADDERout[9]\, ADDERout(8) => - \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, ADDERout(6) - => \ADDERout[6]\, ADDERout(5) => \ADDERout[5]\, - ADDERout(4) => \ADDERout[4]\, ADDERout(3) => - \ADDERout[3]\, ADDERout(2) => \ADDERout[2]\, ADDERout(1) - => \ADDERout[1]\, ADDERout(0) => \ADDERout[0]\, - ADDERinB(24) => \ADDERinB[24]\, ADDERinB(23) => - \ADDERinB[23]\, ADDERinB(22) => \ADDERinB[22]\, - ADDERinB(21) => \ADDERinB[21]\, ADDERinB(20) => - \ADDERinB[20]\, ADDERinB(19) => \ADDERinB[19]\, - ADDERinB(18) => \ADDERinB[18]\, ADDERinB(17) => - \ADDERinB[17]\, ADDERinB(16) => \ADDERinB[16]\, - ADDERinB(15) => \ADDERinB[15]\, ADDERinB(14) => - \ADDERinB[14]\, ADDERinB(13) => \ADDERinB[13]\, - ADDERinB(12) => \ADDERinB[12]\, ADDERinB(11) => - \ADDERinB[11]\, ADDERinB(10) => \ADDERinB[10]\, - ADDERinB(9) => \ADDERinB[9]\, ADDERinB(8) => - \ADDERinB[8]\, ADDERinB(7) => \ADDERinB[7]\, ADDERinB(6) - => \ADDERinB[6]\, ADDERinB(5) => \ADDERinB[5]\, - ADDERinB(4) => \ADDERinB[4]\, ADDERinB(3) => - \ADDERinB[3]\, ADDERinB(2) => \ADDERinB[2]\, ADDERinB(1) - => \ADDERinB[1]\, ADDERinB(0) => \ADDERinB[0]\, - ADDERinA(24) => \ADDERinA[24]\, ADDERinA(23) => - \ADDERinA[23]\, ADDERinA(22) => \ADDERinA[22]\, - ADDERinA(21) => \ADDERinA[21]\, ADDERinA(20) => - \ADDERinA[20]\, ADDERinA(19) => \ADDERinA[19]\, - ADDERinA(18) => \ADDERinA[18]\, ADDERinA(17) => - \ADDERinA[17]\, ADDERinA(16) => \ADDERinA[16]\, - ADDERinA(15) => \ADDERinA[15]\, ADDERinA(14) => - \ADDERinA[14]\, ADDERinA(13) => \ADDERinA[13]\, - ADDERinA(12) => \ADDERinA[12]\, ADDERinA(11) => - \ADDERinA[11]\, ADDERinA(10) => \ADDERinA[10]\, - ADDERinA(9) => \ADDERinA[9]\, ADDERinA(8) => - \ADDERinA[8]\, ADDERinA(7) => \ADDERinA[7]\, ADDERinA(6) - => \ADDERinA[6]\, ADDERinA(5) => \ADDERinA[5]\, - ADDERinA(4) => \ADDERinA[4]\, ADDERinA(3) => - \ADDERinA[3]\, ADDERinA(2) => \ADDERinA[2]\, ADDERinA(1) - => \ADDERinA[1]\, ADDERinA(0) => \ADDERinA[0]\, rstn => - rstn, lclk_c => lclk_c, clr_MAC_D => clr_MAC_D, add_D => - add_D, clr_MAC_D_0 => clr_MAC_D_0, MACMUX2sel_D => - MACMUX2sel_D, add_D_0 => add_D_0); - - MAC_MUX2_inst : MAC_MUX2 - port map(MULTout_D(24) => \MULTout_D[24]\, MULTout_D(23) - => \MULTout_D[23]\, MULTout_D(22) => \MULTout_D[22]\, - MULTout_D(21) => \MULTout_D[21]\, MULTout_D(20) => - \MULTout_D[20]\, MULTout_D(19) => \MULTout_D[19]\, - MULTout_D(18) => \MULTout_D[18]\, MULTout_D(17) => - \MULTout_D[17]\, MULTout_D(16) => \MULTout_D[16]\, - MULTout_D(15) => \MULTout_D[15]\, MULTout_D(14) => - \MULTout_D[14]\, MULTout_D(13) => \MULTout_D[13]\, - MULTout_D(12) => \MULTout_D[12]\, MULTout_D(11) => - \MULTout_D[11]\, MULTout_D(10) => \MULTout_D[10]\, - MULTout_D(9) => \MULTout_D[9]\, MULTout_D(8) => - \MULTout_D[8]\, MULTout_D(7) => \MULTout_D[7]\, - ADDERout(24) => \ADDERout[24]\, ADDERout(23) => - \ADDERout[23]\, ADDERout(22) => \ADDERout[22]\, - ADDERout(21) => \ADDERout[21]\, ADDERout(20) => - \ADDERout[20]\, ADDERout(19) => \ADDERout[19]\, - ADDERout(18) => \ADDERout[18]\, ADDERout(17) => - \ADDERout[17]\, ADDERout(16) => \ADDERout[16]\, - ADDERout(15) => \ADDERout[15]\, ADDERout(14) => - \ADDERout[14]\, ADDERout(13) => \ADDERout[13]\, - ADDERout(12) => \ADDERout[12]\, ADDERout(11) => - \ADDERout[11]\, ADDERout(10) => \ADDERout[10]\, - ADDERout(9) => \ADDERout[9]\, ADDERout(8) => - \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, - sample_out_s(17) => sample_out_s(17), sample_out_s(16) - => sample_out_s(16), sample_out_s(15) => - sample_out_s(15), sample_out_s(14) => sample_out_s(14), - sample_out_s(13) => sample_out_s(13), sample_out_s(12) - => sample_out_s(12), sample_out_s(11) => - sample_out_s(11), sample_out_s(10) => sample_out_s(10), - sample_out_s(9) => sample_out_s(9), sample_out_s(8) => - sample_out_s(8), sample_out_s(7) => sample_out_s(7), - sample_out_s(6) => sample_out_s(6), sample_out_s(5) => - sample_out_s(5), sample_out_s(4) => sample_out_s(4), - sample_out_s(3) => sample_out_s(3), sample_out_s(2) => - sample_out_s(2), sample_out_s(1) => sample_out_s(1), - sample_out_s(0) => sample_out_s(0), MACMUX2sel_D_D => - MACMUX2sel_D_D); - - MACMUXselREG : MAC_REG_1_2 - port map(MACMUXsel_D => MACMUXsel_D, MACMUXsel_D_0 => - MACMUXsel_D_0, N_4 => N_4, rstn => rstn, lclk_c => lclk_c, - MACMUXsel_D_1 => MACMUXsel_D_1); - - Multiplieri_nst : Multiplier - port map(MULTout(24) => \MULTout[24]\, MULTout(23) => - \MULTout[23]\, MULTout(22) => \MULTout[22]\, MULTout(21) - => \MULTout[21]\, MULTout(20) => \MULTout[20]\, - MULTout(19) => \MULTout[19]\, MULTout(18) => - \MULTout[18]\, MULTout(17) => \MULTout[17]\, MULTout(16) - => \MULTout[16]\, MULTout(15) => \MULTout[15]\, - MULTout(14) => \MULTout[14]\, MULTout(13) => - \MULTout[13]\, MULTout(12) => \MULTout[12]\, MULTout(11) - => \MULTout[11]\, MULTout(10) => \MULTout[10]\, - MULTout(9) => \MULTout[9]\, MULTout(8) => \MULTout[8]\, - MULTout(7) => \MULTout[7]\, MULTout(6) => \MULTout[6]\, - MULTout(5) => \MULTout[5]\, MULTout(4) => \MULTout[4]\, - MULTout(3) => \MULTout[3]\, MULTout(2) => \MULTout[2]\, - MULTout(1) => \MULTout[1]\, MULTout(0) => \MULTout[0]\, - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_sample(17) => alu_sample(17), alu_sample(16) => - alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), mult => - mult, mult_0 => mult_0, rstn => rstn, lclk_c => lclk_c); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ALU is - - port( alu_ctrl : in std_logic_vector(2 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - sample_out_s : out std_logic_vector(17 downto 0); - rstn : in std_logic; - lclk_c : in std_logic - ); - -end ALU; - -architecture DEF_ARCH of ALU is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MAC - port( sample_out_s : out std_logic_vector(17 downto 0); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - lclk_c : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : MAC - Use entity work.MAC(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \arith.MACinst\ : MAC - port map(sample_out_s(17) => sample_out_s(17), - sample_out_s(16) => sample_out_s(16), sample_out_s(15) - => sample_out_s(15), sample_out_s(14) => - sample_out_s(14), sample_out_s(13) => sample_out_s(13), - sample_out_s(12) => sample_out_s(12), sample_out_s(11) - => sample_out_s(11), sample_out_s(10) => - sample_out_s(10), sample_out_s(9) => sample_out_s(9), - sample_out_s(8) => sample_out_s(8), sample_out_s(7) => - sample_out_s(7), sample_out_s(6) => sample_out_s(6), - sample_out_s(5) => sample_out_s(5), sample_out_s(4) => - sample_out_s(4), sample_out_s(3) => sample_out_s(3), - sample_out_s(2) => sample_out_s(2), sample_out_s(1) => - sample_out_s(1), sample_out_s(0) => sample_out_s(0), - alu_sample(17) => alu_sample(17), alu_sample(16) => - alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_ctrl(2) => alu_ctrl(2), alu_ctrl(1) => alu_ctrl(1), - alu_ctrl(0) => alu_ctrl(0), lclk_c => lclk_c, rstn => - rstn); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity generic_syncram_2p is - - port( ram_input : in std_logic_vector(17 downto 0); - counter : in std_logic_vector(7 downto 0); - ram_output : out std_logic_vector(17 downto 0); - ram_write_i : in std_logic; - generic_syncram_2p_VCC : in std_logic; - generic_syncram_2p_GND : in std_logic; - ADD_8x8_medium_area_I30_Y_0 : in std_logic; - ADD_8x8_medium_area_I29_Y_0 : in std_logic; - ADD_8x8_medium_area_I28_Y_0 : in std_logic; - ADD_8x8_medium_area_I27_Y_0 : in std_logic; - ADD_8x8_medium_area_I26_Y_0 : in std_logic; - ADD_8x8_medium_area_I25_Y_0 : in std_logic; - ADD_8x8_medium_area_I24_Y_0 : in std_logic; - ADD_8x8_medium_area_I0_S_0 : in std_logic; - ram_write : in std_logic; - lclk_c : in std_logic - ); - -end generic_syncram_2p; - -architecture DEF_ARCH of generic_syncram_2p is - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component RAM512X18 - generic (MEMORYFILE:string := ""); - - port( RADDR8 : in std_logic := 'U'; - RADDR7 : in std_logic := 'U'; - RADDR6 : in std_logic := 'U'; - RADDR5 : in std_logic := 'U'; - RADDR4 : in std_logic := 'U'; - RADDR3 : in std_logic := 'U'; - RADDR2 : in std_logic := 'U'; - RADDR1 : in std_logic := 'U'; - RADDR0 : in std_logic := 'U'; - WADDR8 : in std_logic := 'U'; - WADDR7 : in std_logic := 'U'; - WADDR6 : in std_logic := 'U'; - WADDR5 : in std_logic := 'U'; - WADDR4 : in std_logic := 'U'; - WADDR3 : in std_logic := 'U'; - WADDR2 : in std_logic := 'U'; - WADDR1 : in std_logic := 'U'; - WADDR0 : in std_logic := 'U'; - WD17 : in std_logic := 'U'; - WD16 : in std_logic := 'U'; - WD15 : in std_logic := 'U'; - WD14 : in std_logic := 'U'; - WD13 : in std_logic := 'U'; - WD12 : in std_logic := 'U'; - WD11 : in std_logic := 'U'; - WD10 : in std_logic := 'U'; - WD9 : in std_logic := 'U'; - WD8 : in std_logic := 'U'; - WD7 : in std_logic := 'U'; - WD6 : in std_logic := 'U'; - WD5 : in std_logic := 'U'; - WD4 : in std_logic := 'U'; - WD3 : in std_logic := 'U'; - WD2 : in std_logic := 'U'; - WD1 : in std_logic := 'U'; - WD0 : in std_logic := 'U'; - RW0 : in std_logic := 'U'; - RW1 : in std_logic := 'U'; - WW0 : in std_logic := 'U'; - WW1 : in std_logic := 'U'; - PIPE : in std_logic := 'U'; - REN : in std_logic := 'U'; - WEN : in std_logic := 'U'; - RCLK : in std_logic := 'U'; - WCLK : in std_logic := 'U'; - RESET : in std_logic := 'U'; - RD17 : out std_logic; - RD16 : out std_logic; - RD15 : out std_logic; - RD14 : out std_logic; - RD13 : out std_logic; - RD12 : out std_logic; - RD11 : out std_logic; - RD10 : out std_logic; - RD9 : out std_logic; - RD8 : out std_logic; - RD7 : out std_logic; - RD6 : out std_logic; - RD5 : out std_logic; - RD4 : out std_logic; - RD3 : out std_logic; - RD2 : out std_logic; - RD1 : out std_logic; - RD0 : out std_logic - ); - end component; - - signal I_5_5, I_4_2_i_0, I_4_1_i_0, I_5_2, I_5_4, - \RADDR_REG1[7]\, \WADDR_REG1[7]\, I_5_0, I_5_3, - \RADDR_REG1[5]\, \WADDR_REG1[5]\, I_4_6_i_0, - \RADDR_REG1[3]\, \WADDR_REG1[3]\, I_4_4_i_0, - \RADDR_REG1[0]\, \WADDR_REG1[0]\, N_5, N_7, - \WADDR_REG1[1]\, \RADDR_REG1[1]\, \WADDR_REG1[2]\, - \RADDR_REG1[2]\, \WADDR_REG1[4]\, \RADDR_REG1[4]\, - \WADDR_REG1[6]\, \RADDR_REG1[6]\, \DOUT_TMP[0]\, - \DIN_REG1[0]\, \DOUT_TMP[3]\, \DIN_REG1[3]\, - \DOUT_TMP[4]\, \DIN_REG1[4]\, \DOUT_TMP[5]\, - \DIN_REG1[5]\, \DOUT_TMP[6]\, \DIN_REG1[6]\, - \DOUT_TMP[7]\, \DIN_REG1[7]\, \DOUT_TMP[8]\, - \DIN_REG1[8]\, \DOUT_TMP[9]\, \DIN_REG1[9]\, - \DOUT_TMP[10]\, \DIN_REG1[10]\, \DOUT_TMP[11]\, - \DIN_REG1[11]\, \DOUT_TMP[12]\, \DIN_REG1[12]\, - \DOUT_TMP[13]\, \DIN_REG1[13]\, \DOUT_TMP[14]\, - \DIN_REG1[14]\, \DOUT_TMP[15]\, \DIN_REG1[15]\, - \DOUT_TMP[16]\, \DIN_REG1[16]\, \DOUT_TMP[17]\, - \DIN_REG1[17]\, \DOUT_TMP[2]\, \DIN_REG1[2]\, - \DOUT_TMP[1]\, \DIN_REG1[1]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \rfd_tile_DIN_REG1[9]\ : DFN1 - port map(D => ram_input(9), CLK => lclk_c, Q => - \DIN_REG1[9]\); - - \rfd_tile_RADDR_REG1[5]\ : DFN1 - port map(D => counter(5), CLK => lclk_c, Q => - \RADDR_REG1[5]\); - - \rfd_tile_WADDR_REG1[6]\ : DFN1 - port map(D => ADD_8x8_medium_area_I29_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[6]\); - - rfd_tile_I_3 : DFN1 - port map(D => ram_write, CLK => lclk_c, Q => N_5); - - \rfd_tile_DIN_REG1_RNI7EOE2[2]\ : MX2 - port map(A => \DOUT_TMP[2]\, B => \DIN_REG1[2]\, S => N_7, - Y => ram_output(2)); - - \rfd_tile_DIN_REG1[10]\ : DFN1 - port map(D => ram_input(10), CLK => lclk_c, Q => - \DIN_REG1[10]\); - - \rfd_tile_WADDR_REG1_RNIGU611[1]\ : NOR3C - port map(A => I_4_2_i_0, B => I_4_1_i_0, C => I_5_2, Y => - I_5_5); - - \rfd_tile_WADDR_REG1[4]\ : DFN1 - port map(D => ADD_8x8_medium_area_I27_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[4]\); - - \rfd_tile_WADDR_REG1_RNIJN98[2]\ : XNOR2 - port map(A => \WADDR_REG1[2]\, B => \RADDR_REG1[2]\, Y => - I_4_2_i_0); - - rfd_tile_I_1_RNINVIJ2 : MX2 - port map(A => \DOUT_TMP[11]\, B => \DIN_REG1[11]\, S => N_7, - Y => ram_output(11)); - - VCC_i : VCC - port map(Y => \VCC\); - - \rfd_tile_DIN_REG1_RNIBEOE2[6]\ : MX2 - port map(A => \DOUT_TMP[6]\, B => \DIN_REG1[6]\, S => N_7, - Y => ram_output(6)); - - \rfd_tile_DIN_REG1_RNIEEOE2[9]\ : MX2 - port map(A => \DOUT_TMP[9]\, B => \DIN_REG1[9]\, S => N_7, - Y => ram_output(9)); - - \rfd_tile_DIN_REG1[0]\ : DFN1 - port map(D => ram_input(0), CLK => lclk_c, Q => - \DIN_REG1[0]\); - - \rfd_tile_DIN_REG1[5]\ : DFN1 - port map(D => ram_input(5), CLK => lclk_c, Q => - \DIN_REG1[5]\); - - \rfd_tile_WADDR_REG1_RNICFJG[3]\ : XA1A - port map(A => \RADDR_REG1[3]\, B => \WADDR_REG1[3]\, C => - I_4_4_i_0, Y => I_5_2); - - \rfd_tile_DIN_REG1[4]\ : DFN1 - port map(D => ram_input(4), CLK => lclk_c, Q => - \DIN_REG1[4]\); - - \rfd_tile_DIN_REG1[3]\ : DFN1 - port map(D => ram_input(3), CLK => lclk_c, Q => - \DIN_REG1[3]\); - - \rfd_tile_DIN_REG1[2]\ : DFN1 - port map(D => ram_input(2), CLK => lclk_c, Q => - \DIN_REG1[2]\); - - \rfd_tile_DIN_REG1_RNICEOE2[7]\ : MX2 - port map(A => \DOUT_TMP[7]\, B => \DIN_REG1[7]\, S => N_7, - Y => ram_output(7)); - - \rfd_tile_DIN_REG1[12]\ : DFN1 - port map(D => ram_input(12), CLK => lclk_c, Q => - \DIN_REG1[12]\); - - \rfd_tile_WADDR_REG1[7]\ : DFN1 - port map(D => ADD_8x8_medium_area_I30_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[7]\); - - rfd_tile_I_1_RNIO3JJ2 : MX2 - port map(A => \DOUT_TMP[12]\, B => \DIN_REG1[12]\, S => N_7, - Y => ram_output(12)); - - rfd_tile_I_1_RNIMRIJ2 : MX2 - port map(A => \DOUT_TMP[10]\, B => \DIN_REG1[10]\, S => N_7, - Y => ram_output(10)); - - \rfd_tile_WADDR_REG1_RNINN98[4]\ : XNOR2 - port map(A => \WADDR_REG1[4]\, B => \RADDR_REG1[4]\, Y => - I_4_4_i_0); - - \rfd_tile_DIN_REG1[15]\ : DFN1 - port map(D => ram_input(15), CLK => lclk_c, Q => - \DIN_REG1[15]\); - - \rfd_tile_RADDR_REG1[0]\ : DFN1 - port map(D => counter(0), CLK => lclk_c, Q => - \RADDR_REG1[0]\); - - rfd_tile_I_1_RNIRFJJ2 : MX2 - port map(A => \DOUT_TMP[15]\, B => \DIN_REG1[15]\, S => N_7, - Y => ram_output(15)); - - \rfd_tile_DIN_REG1_RNI8EOE2[3]\ : MX2 - port map(A => \DOUT_TMP[3]\, B => \DIN_REG1[3]\, S => N_7, - Y => ram_output(3)); - - \rfd_tile_WADDR_REG1_RNIVTTL[7]\ : XA1A - port map(A => \RADDR_REG1[7]\, B => \WADDR_REG1[7]\, C => - I_5_0, Y => I_5_4); - - \rfd_tile_WADDR_REG1[5]\ : DFN1 - port map(D => ADD_8x8_medium_area_I28_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[5]\); - - rfd_tile_I_1_RNITNJJ2 : MX2 - port map(A => \DOUT_TMP[17]\, B => \DIN_REG1[17]\, S => N_7, - Y => ram_output(17)); - - \rfd_tile_DIN_REG1_RNI5EOE2[0]\ : MX2 - port map(A => \DOUT_TMP[0]\, B => \DIN_REG1[0]\, S => N_7, - Y => ram_output(0)); - - \rfd_tile_RADDR_REG1[2]\ : DFN1 - port map(D => counter(2), CLK => lclk_c, Q => - \RADDR_REG1[2]\); - - \rfd_tile_DIN_REG1[1]\ : DFN1 - port map(D => ram_input(1), CLK => lclk_c, Q => - \DIN_REG1[1]\); - - \rfd_tile_RADDR_REG1[3]\ : DFN1 - port map(D => counter(3), CLK => lclk_c, Q => - \RADDR_REG1[3]\); - - \rfd_tile_WADDR_REG1_RNIHN98[1]\ : XNOR2 - port map(A => \WADDR_REG1[1]\, B => \RADDR_REG1[1]\, Y => - I_4_1_i_0); - - \rfd_tile_DIN_REG1_RNIAEOE2[5]\ : MX2 - port map(A => \DOUT_TMP[5]\, B => \DIN_REG1[5]\, S => N_7, - Y => ram_output(5)); - - GND_i : GND - port map(Y => \GND\); - - \rfd_tile_RADDR_REG1[1]\ : DFN1 - port map(D => counter(1), CLK => lclk_c, Q => - \RADDR_REG1[1]\); - - \rfd_tile_DIN_REG1[14]\ : DFN1 - port map(D => ram_input(14), CLK => lclk_c, Q => - \DIN_REG1[14]\); - - rfd_tile_I_1_RNIP7JJ2 : MX2 - port map(A => \DOUT_TMP[13]\, B => \DIN_REG1[13]\, S => N_7, - Y => ram_output(13)); - - \rfd_tile_DIN_REG1_RNI6EOE2[1]\ : MX2 - port map(A => \DOUT_TMP[1]\, B => \DIN_REG1[1]\, S => N_7, - Y => ram_output(1)); - - \rfd_tile_RADDR_REG1[6]\ : DFN1 - port map(D => counter(6), CLK => lclk_c, Q => - \RADDR_REG1[6]\); - - \rfd_tile_DIN_REG1_RNIDEOE2[8]\ : MX2 - port map(A => \DOUT_TMP[8]\, B => \DIN_REG1[8]\, S => N_7, - Y => ram_output(8)); - - \rfd_tile_WADDR_REG1_RNIRN98[6]\ : XNOR2 - port map(A => \WADDR_REG1[6]\, B => \RADDR_REG1[6]\, Y => - I_4_6_i_0); - - \rfd_tile_DIN_REG1_RNI9EOE2[4]\ : MX2 - port map(A => \DOUT_TMP[4]\, B => \DIN_REG1[4]\, S => N_7, - Y => ram_output(4)); - - \rfd_tile_DIN_REG1[8]\ : DFN1 - port map(D => ram_input(8), CLK => lclk_c, Q => - \DIN_REG1[8]\); - - \rfd_tile_WADDR_REG1_RNIKFJG[5]\ : XA1A - port map(A => \RADDR_REG1[5]\, B => \WADDR_REG1[5]\, C => - I_4_6_i_0, Y => I_5_3); - - \rfd_tile_WADDR_REG1[0]\ : DFN1 - port map(D => ADD_8x8_medium_area_I0_S_0, CLK => lclk_c, Q - => \WADDR_REG1[0]\); - - \rfd_tile_RADDR_REG1[4]\ : DFN1 - port map(D => counter(4), CLK => lclk_c, Q => - \RADDR_REG1[4]\); - - \rfd_tile_DIN_REG1[6]\ : DFN1 - port map(D => ram_input(6), CLK => lclk_c, Q => - \DIN_REG1[6]\); - - \rfd_tile_WADDR_REG1[2]\ : DFN1 - port map(D => ADD_8x8_medium_area_I25_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[2]\); - - \rfd_tile_DIN_REG1[11]\ : DFN1 - port map(D => ram_input(11), CLK => lclk_c, Q => - \DIN_REG1[11]\); - - \rfd_tile_WADDR_REG1[3]\ : DFN1 - port map(D => ADD_8x8_medium_area_I26_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[3]\); - - rfd_tile_I_1_RNIQBJJ2 : MX2 - port map(A => \DOUT_TMP[14]\, B => \DIN_REG1[14]\, S => N_7, - Y => ram_output(14)); - - \rfd_tile_DIN_REG1[13]\ : DFN1 - port map(D => ram_input(13), CLK => lclk_c, Q => - \DIN_REG1[13]\); - - \rfd_tile_WADDR_REG1_RNI26KD[0]\ : XA1A - port map(A => \RADDR_REG1[0]\, B => \WADDR_REG1[0]\, C => - N_5, Y => I_5_0); - - rfd_tile_I_1_RNISJJJ2 : MX2 - port map(A => \DOUT_TMP[16]\, B => \DIN_REG1[16]\, S => N_7, - Y => ram_output(16)); - - rfd_tile_I_1 : RAM512X18 - port map(RADDR8 => generic_syncram_2p_GND, RADDR7 => - counter(7), RADDR6 => counter(6), RADDR5 => counter(5), - RADDR4 => counter(4), RADDR3 => counter(3), RADDR2 => - counter(2), RADDR1 => counter(1), RADDR0 => counter(0), - WADDR8 => generic_syncram_2p_GND, WADDR7 => - ADD_8x8_medium_area_I30_Y_0, WADDR6 => - ADD_8x8_medium_area_I29_Y_0, WADDR5 => - ADD_8x8_medium_area_I28_Y_0, WADDR4 => - ADD_8x8_medium_area_I27_Y_0, WADDR3 => - ADD_8x8_medium_area_I26_Y_0, WADDR2 => - ADD_8x8_medium_area_I25_Y_0, WADDR1 => - ADD_8x8_medium_area_I24_Y_0, WADDR0 => - ADD_8x8_medium_area_I0_S_0, WD17 => ram_input(17), WD16 - => ram_input(16), WD15 => ram_input(15), WD14 => - ram_input(14), WD13 => ram_input(13), WD12 => - ram_input(12), WD11 => ram_input(11), WD10 => - ram_input(10), WD9 => ram_input(9), WD8 => ram_input(8), - WD7 => ram_input(7), WD6 => ram_input(6), WD5 => - ram_input(5), WD4 => ram_input(4), WD3 => ram_input(3), - WD2 => ram_input(2), WD1 => ram_input(1), WD0 => - ram_input(0), RW0 => generic_syncram_2p_GND, RW1 => - generic_syncram_2p_VCC, WW0 => generic_syncram_2p_GND, - WW1 => generic_syncram_2p_VCC, PIPE => - generic_syncram_2p_GND, REN => generic_syncram_2p_GND, - WEN => ram_write_i, RCLK => lclk_c, WCLK => lclk_c, RESET - => generic_syncram_2p_VCC, RD17 => \DOUT_TMP[17]\, RD16 - => \DOUT_TMP[16]\, RD15 => \DOUT_TMP[15]\, RD14 => - \DOUT_TMP[14]\, RD13 => \DOUT_TMP[13]\, RD12 => - \DOUT_TMP[12]\, RD11 => \DOUT_TMP[11]\, RD10 => - \DOUT_TMP[10]\, RD9 => \DOUT_TMP[9]\, RD8 => - \DOUT_TMP[8]\, RD7 => \DOUT_TMP[7]\, RD6 => \DOUT_TMP[6]\, - RD5 => \DOUT_TMP[5]\, RD4 => \DOUT_TMP[4]\, RD3 => - \DOUT_TMP[3]\, RD2 => \DOUT_TMP[2]\, RD1 => \DOUT_TMP[1]\, - RD0 => \DOUT_TMP[0]\); - - \rfd_tile_RADDR_REG1[7]\ : DFN1 - port map(D => counter(7), CLK => lclk_c, Q => - \RADDR_REG1[7]\); - - \rfd_tile_DIN_REG1[16]\ : DFN1 - port map(D => ram_input(16), CLK => lclk_c, Q => - \DIN_REG1[16]\); - - \rfd_tile_WADDR_REG1[1]\ : DFN1 - port map(D => ADD_8x8_medium_area_I24_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[1]\); - - \rfd_tile_DIN_REG1[17]\ : DFN1 - port map(D => ram_input(17), CLK => lclk_c, Q => - \DIN_REG1[17]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \rfd_tile_WADDR_REG1_RNI3CO72[5]\ : NOR3C - port map(A => I_5_4, B => I_5_3, C => I_5_5, Y => N_7); - - \rfd_tile_DIN_REG1[7]\ : DFN1 - port map(D => ram_input(7), CLK => lclk_c, Q => - \DIN_REG1[7]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ1 is - - port( ram_output : out std_logic_vector(17 downto 0); - counter : in std_logic_vector(7 downto 0); - ram_input : in std_logic_vector(17 downto 0); - lclk_c : in std_logic; - ram_write : in std_logic; - ADD_8x8_medium_area_I0_S_0 : in std_logic; - ADD_8x8_medium_area_I24_Y_0 : in std_logic; - ADD_8x8_medium_area_I25_Y_0 : in std_logic; - ADD_8x8_medium_area_I26_Y_0 : in std_logic; - ADD_8x8_medium_area_I27_Y_0 : in std_logic; - ADD_8x8_medium_area_I28_Y_0 : in std_logic; - ADD_8x8_medium_area_I29_Y_0 : in std_logic; - ADD_8x8_medium_area_I30_Y_0 : in std_logic; - syncram_2pZ1_GND : in std_logic; - syncram_2pZ1_VCC : in std_logic; - ram_write_i : in std_logic - ); - -end syncram_2pZ1; - -architecture DEF_ARCH of syncram_2pZ1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component generic_syncram_2p - port( ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - counter : in std_logic_vector(7 downto 0) := (others => 'U'); - ram_output : out std_logic_vector(17 downto 0); - ram_write_i : in std_logic := 'U'; - generic_syncram_2p_VCC : in std_logic := 'U'; - generic_syncram_2p_GND : in std_logic := 'U'; - ADD_8x8_medium_area_I30_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I29_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I28_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I27_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I26_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I25_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I24_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I0_S_0 : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : generic_syncram_2p - Use entity work.generic_syncram_2p(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \inf.x0\ : generic_syncram_2p - port map(ram_input(17) => ram_input(17), ram_input(16) => - ram_input(16), ram_input(15) => ram_input(15), - ram_input(14) => ram_input(14), ram_input(13) => - ram_input(13), ram_input(12) => ram_input(12), - ram_input(11) => ram_input(11), ram_input(10) => - ram_input(10), ram_input(9) => ram_input(9), ram_input(8) - => ram_input(8), ram_input(7) => ram_input(7), - ram_input(6) => ram_input(6), ram_input(5) => - ram_input(5), ram_input(4) => ram_input(4), ram_input(3) - => ram_input(3), ram_input(2) => ram_input(2), - ram_input(1) => ram_input(1), ram_input(0) => - ram_input(0), counter(7) => counter(7), counter(6) => - counter(6), counter(5) => counter(5), counter(4) => - counter(4), counter(3) => counter(3), counter(2) => - counter(2), counter(1) => counter(1), counter(0) => - counter(0), ram_output(17) => ram_output(17), - ram_output(16) => ram_output(16), ram_output(15) => - ram_output(15), ram_output(14) => ram_output(14), - ram_output(13) => ram_output(13), ram_output(12) => - ram_output(12), ram_output(11) => ram_output(11), - ram_output(10) => ram_output(10), ram_output(9) => - ram_output(9), ram_output(8) => ram_output(8), - ram_output(7) => ram_output(7), ram_output(6) => - ram_output(6), ram_output(5) => ram_output(5), - ram_output(4) => ram_output(4), ram_output(3) => - ram_output(3), ram_output(2) => ram_output(2), - ram_output(1) => ram_output(1), ram_output(0) => - ram_output(0), ram_write_i => ram_write_i, - generic_syncram_2p_VCC => syncram_2pZ1_VCC, - generic_syncram_2p_GND => syncram_2pZ1_GND, - ADD_8x8_medium_area_I30_Y_0 => - ADD_8x8_medium_area_I30_Y_0, ADD_8x8_medium_area_I29_Y_0 - => ADD_8x8_medium_area_I29_Y_0, - ADD_8x8_medium_area_I28_Y_0 => - ADD_8x8_medium_area_I28_Y_0, ADD_8x8_medium_area_I27_Y_0 - => ADD_8x8_medium_area_I27_Y_0, - ADD_8x8_medium_area_I26_Y_0 => - ADD_8x8_medium_area_I26_Y_0, ADD_8x8_medium_area_I25_Y_0 - => ADD_8x8_medium_area_I25_Y_0, - ADD_8x8_medium_area_I24_Y_0 => - ADD_8x8_medium_area_I24_Y_0, ADD_8x8_medium_area_I0_S_0 - => ADD_8x8_medium_area_I0_S_0, ram_write => ram_write, - lclk_c => lclk_c); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity RAM_CTRLR_v2 is - - port( ram_input : in std_logic_vector(17 downto 0); - ram_output : out std_logic_vector(17 downto 0); - waddr_previous : in std_logic_vector(1 downto 0); - ram_write_i : in std_logic; - RAM_CTRLR_v2_VCC : in std_logic; - RAM_CTRLR_v2_GND : in std_logic; - ram_write : in std_logic; - raddr_add1 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - raddr_rst : in std_logic - ); - -end RAM_CTRLR_v2; - -architecture DEF_ARCH of RAM_CTRLR_v2 is - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component syncram_2pZ1 - port( ram_output : out std_logic_vector(17 downto 0); - counter : in std_logic_vector(7 downto 0) := (others => 'U'); - ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - lclk_c : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - ADD_8x8_medium_area_I0_S_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I24_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I25_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I26_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I27_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I28_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I29_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I30_Y_0 : in std_logic := 'U'; - syncram_2pZ1_GND : in std_logic := 'U'; - syncram_2pZ1_VCC : in std_logic := 'U'; - ram_write_i : in std_logic := 'U' - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_TMP[0]\, \counter[1]_net_1\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, \counter[4]_net_1\, - \DWACT_ADD_CI_0_g_array_12[0]\, \counter[2]_net_1\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, \counter[6]_net_1\, - ADD_8x8_medium_area_I20_Y_0, \counter[5]_net_1\, N_5_i, - ADD_8x8_medium_area_I20_un1_Y_0, - ADD_8x8_medium_area_I13_Y_0, \counter[3]_net_1\, - ADD_8x8_medium_area_I13_un1_Y_0, N145_i, N135_i, N147, - ADD_8x8_medium_area_I24_Y_0, N116, - ADD_8x8_medium_area_I25_Y_0, ADD_8x8_medium_area_I27_Y_0, - ADD_8x8_medium_area_I30_Y_0, \counter[7]_net_1\, N149, - ADD_8x8_medium_area_I29_Y_0, \counter[0]_net_1\, N120, - N124, ADD_8x8_medium_area_I0_S_0, - ADD_8x8_medium_area_I26_Y_0, N121, - ADD_8x8_medium_area_I28_Y_0, N125, \counter_3[7]\, I_34, - \counter_3[6]\, I_30, \counter_3[5]\, I_33, - \counter_3[4]\, I_28, \counter_3[3]\, I_31_9, - \counter_3[2]\, I_32, \counter_3[1]\, I_27, - \counter_3[0]\, \DWACT_ADD_CI_0_partial_sum[0]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : syncram_2pZ1 - Use entity work.syncram_2pZ1(DEF_ARCH); -begin - - - un1_counter_1_ADD_8x8_medium_area_I20_Y_0 : OAI1 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - C => N_5_i, Y => ADD_8x8_medium_area_I20_Y_0); - - un1_counter_I_45 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => - \counter[6]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_2[0]\); - - un1_counter_I_31 : XOR2 - port map(A => \counter[3]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_31_9); - - un1_counter_I_36 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - un1_counter_1_ADD_8x8_medium_area_I12_Y : MX2B - port map(A => N116, B => N_5_i, S => \counter[1]_net_1\, Y - => N135_i); - - un1_counter_1_ADD_8x8_medium_area_I13_Y_0 : OAI1 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - C => N_5_i, Y => ADD_8x8_medium_area_I13_Y_0); - - un1_counter_I_44 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \counter[2]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12[0]\); - - \counter[2]\ : DFN1C0 - port map(D => \counter_3[2]\, CLK => lclk_c, CLR => rstn, Q - => \counter[2]_net_1\); - - \counter[7]\ : DFN1C0 - port map(D => \counter_3[7]\, CLK => lclk_c, CLR => rstn, Q - => \counter[7]_net_1\); - - un1_counter_1_ADD_8x8_medium_area_I29_Y_0 : XOR3 - port map(A => N_5_i, B => \counter[6]_net_1\, C => N147, Y - => ADD_8x8_medium_area_I29_Y_0); - - un1_counter_I_48 : AND2 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - Y => \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - un1_counter_1_ADD_8x8_medium_area_I20_Y : OAI1 - port map(A => N145_i, B => ADD_8x8_medium_area_I20_un1_Y_0, - C => ADD_8x8_medium_area_I20_Y_0, Y => N147); - - \counter_RNO[0]\ : NOR2A - port map(A => \DWACT_ADD_CI_0_partial_sum[0]\, B => - raddr_rst, Y => \counter_3[0]\); - - \counter[6]\ : DFN1C0 - port map(D => \counter_3[6]\, CLK => lclk_c, CLR => rstn, Q - => \counter[6]_net_1\); - - \counter_RNO[4]\ : NOR2A - port map(A => I_28, B => raddr_rst, Y => \counter_3[4]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \memRAM.SRAM\ : syncram_2pZ1 - port map(ram_output(17) => ram_output(17), ram_output(16) - => ram_output(16), ram_output(15) => ram_output(15), - ram_output(14) => ram_output(14), ram_output(13) => - ram_output(13), ram_output(12) => ram_output(12), - ram_output(11) => ram_output(11), ram_output(10) => - ram_output(10), ram_output(9) => ram_output(9), - ram_output(8) => ram_output(8), ram_output(7) => - ram_output(7), ram_output(6) => ram_output(6), - ram_output(5) => ram_output(5), ram_output(4) => - ram_output(4), ram_output(3) => ram_output(3), - ram_output(2) => ram_output(2), ram_output(1) => - ram_output(1), ram_output(0) => ram_output(0), counter(7) - => \counter[7]_net_1\, counter(6) => \counter[6]_net_1\, - counter(5) => \counter[5]_net_1\, counter(4) => - \counter[4]_net_1\, counter(3) => \counter[3]_net_1\, - counter(2) => \counter[2]_net_1\, counter(1) => - \counter[1]_net_1\, counter(0) => \counter[0]_net_1\, - ram_input(17) => ram_input(17), ram_input(16) => - ram_input(16), ram_input(15) => ram_input(15), - ram_input(14) => ram_input(14), ram_input(13) => - ram_input(13), ram_input(12) => ram_input(12), - ram_input(11) => ram_input(11), ram_input(10) => - ram_input(10), ram_input(9) => ram_input(9), ram_input(8) - => ram_input(8), ram_input(7) => ram_input(7), - ram_input(6) => ram_input(6), ram_input(5) => - ram_input(5), ram_input(4) => ram_input(4), ram_input(3) - => ram_input(3), ram_input(2) => ram_input(2), - ram_input(1) => ram_input(1), ram_input(0) => - ram_input(0), lclk_c => lclk_c, ram_write => ram_write, - ADD_8x8_medium_area_I0_S_0 => ADD_8x8_medium_area_I0_S_0, - ADD_8x8_medium_area_I24_Y_0 => - ADD_8x8_medium_area_I24_Y_0, ADD_8x8_medium_area_I25_Y_0 - => ADD_8x8_medium_area_I25_Y_0, - ADD_8x8_medium_area_I26_Y_0 => - ADD_8x8_medium_area_I26_Y_0, ADD_8x8_medium_area_I27_Y_0 - => ADD_8x8_medium_area_I27_Y_0, - ADD_8x8_medium_area_I28_Y_0 => - ADD_8x8_medium_area_I28_Y_0, ADD_8x8_medium_area_I29_Y_0 - => ADD_8x8_medium_area_I29_Y_0, - ADD_8x8_medium_area_I30_Y_0 => - ADD_8x8_medium_area_I30_Y_0, syncram_2pZ1_GND => - RAM_CTRLR_v2_GND, syncram_2pZ1_VCC => RAM_CTRLR_v2_VCC, - ram_write_i => ram_write_i); - - un1_counter_1_ADD_8x8_medium_area_I26_Y_0 : AX1E - port map(A => N120, B => N135_i, C => N121, Y => - ADD_8x8_medium_area_I26_Y_0); - - \counter_RNO[1]\ : NOR2A - port map(A => I_27, B => raddr_rst, Y => \counter_3[1]\); - - un1_counter_1_ADD_8x8_medium_area_I0_CO1 : OR3B - port map(A => waddr_previous(0), B => \counter[0]_net_1\, C - => waddr_previous(1), Y => N116); - - \un2_waddr_0_x2[6]\ : XOR2 - port map(A => waddr_previous(1), B => waddr_previous(0), Y - => N_5_i); - - un1_counter_1_ADD_8x8_medium_area_I4_CO1 : OR2B - port map(A => \counter[4]_net_1\, B => N_5_i, Y => N124); - - un1_counter_I_28 : XOR2 - port map(A => \counter[4]_net_1\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_28); - - un1_counter_1_ADD_8x8_medium_area_I3_S_0 : XOR2 - port map(A => \counter[3]_net_1\, B => N_5_i, Y => N121); - - un1_counter_1_ADD_8x8_medium_area_I25_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[2]_net_1\, C => N135_i, - Y => ADD_8x8_medium_area_I25_Y_0); - - un1_counter_I_42 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \counter[4]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_1[0]\); - - un1_counter_1_ADD_8x8_medium_area_I30_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[7]_net_1\, C => N149, Y - => ADD_8x8_medium_area_I30_Y_0); - - un1_counter_I_35 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => - \counter[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1[0]\); - - \counter[4]\ : DFN1C0 - port map(D => \counter_3[4]\, CLK => lclk_c, CLR => rstn, Q - => \counter[4]_net_1\); - - un1_counter_1_ADD_8x8_medium_area_I20_un1_Y_0 : OR2 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - Y => ADD_8x8_medium_area_I20_un1_Y_0); - - \counter[5]\ : DFN1C0 - port map(D => \counter_3[5]\, CLK => lclk_c, CLR => rstn, Q - => \counter[5]_net_1\); - - un1_counter_I_34 : XOR2 - port map(A => \counter[7]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => I_34); - - un1_counter_1_ADD_8x8_medium_area_I21_Y : MX2C - port map(A => N147, B => N_5_i, S => \counter[6]_net_1\, Y - => N149); - - \counter_RNO[2]\ : NOR2A - port map(A => I_32, B => raddr_rst, Y => \counter_3[2]\); - - GND_i : GND - port map(Y => \GND\); - - un1_counter_I_30 : XOR2 - port map(A => \counter[6]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_30); - - \counter_RNO[5]\ : NOR2A - port map(A => I_33, B => raddr_rst, Y => \counter_3[5]\); - - \counter_RNO[3]\ : NOR2A - port map(A => I_31_9, B => raddr_rst, Y => \counter_3[3]\); - - un1_counter_1_ADD_8x8_medium_area_I13_un1_Y_0 : OR2 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - Y => ADD_8x8_medium_area_I13_un1_Y_0); - - \counter[1]\ : DFN1C0 - port map(D => \counter_3[1]\, CLK => lclk_c, CLR => rstn, Q - => \counter[1]_net_1\); - - \counter[3]\ : DFN1C0 - port map(D => \counter_3[3]\, CLK => lclk_c, CLR => rstn, Q - => \counter[3]_net_1\); - - un1_counter_I_39 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - un1_counter_1_ADD_8x8_medium_area_I0_S_0 : AX1 - port map(A => waddr_previous(1), B => waddr_previous(0), C - => \counter[0]_net_1\, Y => ADD_8x8_medium_area_I0_S_0); - - un1_counter_I_47 : AND2 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - Y => \DWACT_ADD_CI_0_pog_array_1[0]\); - - un1_counter_I_19 : XOR2 - port map(A => \counter[0]_net_1\, B => raddr_add1, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \counter_RNO[6]\ : NOR2A - port map(A => I_30, B => raddr_rst, Y => \counter_3[6]\); - - un1_counter_I_1 : AND2 - port map(A => \counter[0]_net_1\, B => raddr_add1, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - un1_counter_1_ADD_8x8_medium_area_I5_S_0 : XOR2 - port map(A => \counter[5]_net_1\, B => N_5_i, Y => N125); - - un1_counter_1_ADD_8x8_medium_area_I13_Y : OA1 - port map(A => N135_i, B => ADD_8x8_medium_area_I13_un1_Y_0, - C => ADD_8x8_medium_area_I13_Y_0, Y => N145_i); - - un1_counter_I_33 : XOR2 - port map(A => \counter[5]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_33); - - un1_counter_I_32 : XOR2 - port map(A => \counter[2]_net_1\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_32); - - un1_counter_I_27 : XOR2 - port map(A => \counter[1]_net_1\, B => - \DWACT_ADD_CI_0_TMP[0]\, Y => I_27); - - un1_counter_1_ADD_8x8_medium_area_I27_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[4]_net_1\, C => N145_i, - Y => ADD_8x8_medium_area_I27_Y_0); - - un1_counter_1_ADD_8x8_medium_area_I28_Y_0 : AX1E - port map(A => N124, B => N145_i, C => N125, Y => - ADD_8x8_medium_area_I28_Y_0); - - un1_counter_1_ADD_8x8_medium_area_I24_Y_0 : XNOR3 - port map(A => N116, B => \counter[1]_net_1\, C => N_5_i, Y - => ADD_8x8_medium_area_I24_Y_0); - - \counter_RNO[7]\ : NOR2A - port map(A => I_34, B => raddr_rst, Y => \counter_3[7]\); - - un1_counter_1_ADD_8x8_medium_area_I2_CO1 : OR2B - port map(A => \counter[2]_net_1\, B => N_5_i, Y => N120); - - \counter[0]\ : DFN1C0 - port map(D => \counter_3[0]\, CLK => lclk_c, CLR => rstn, Q - => \counter[0]_net_1\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2_DATAFLOW is - - port( alu_ctrl : in std_logic_vector(2 downto 0); - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0); - S_0 : out std_logic; - S_36 : out std_logic; - waddr_previous : in std_logic_vector(1 downto 0); - sample_0 : in std_logic_vector(14 downto 0); - sample_in_buf : in std_logic_vector(143 downto 129); - ram_sel_Wdata : in std_logic_vector(1 downto 0); - sample_out_s_1 : out std_logic; - sample_out_s_2 : out std_logic; - sample_out_s_0 : out std_logic; - sample_out_s_3 : out std_logic; - sample_out_s_15 : out std_logic; - sample_out_s_14 : out std_logic; - sample_out_s_13 : out std_logic; - sample_out_s_12 : out std_logic; - sample_out_s_11 : out std_logic; - sample_out_s_10 : out std_logic; - sample_out_s_9 : out std_logic; - sample_out_s_8 : out std_logic; - sample_out_s_7 : out std_logic; - sample_out_s_6 : out std_logic; - sample_out_s_5 : out std_logic; - sample_out_s_4 : out std_logic; - sample_in_s_1 : in std_logic_vector(17 to 17); - in_sel_src : in std_logic_vector(1 downto 0); - raddr_rst : in std_logic; - raddr_add1 : in std_logic; - ram_write : in std_logic; - IIR_CEL_CTRLR_v2_DATAFLOW_GND : in std_logic; - IIR_CEL_CTRLR_v2_DATAFLOW_VCC : in std_logic; - ram_write_i : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_val_delay_5 : in std_logic; - sample_val_delay_1 : in std_logic; - sample_val_delay_0 : in std_logic; - alu_sel_input : in std_logic - ); - -end IIR_CEL_CTRLR_v2_DATAFLOW; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2_DATAFLOW is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MUXN_9_5 - port( S_36 : out std_logic; - S_0 : out std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_coef_s : out std_logic_vector(8 downto 0) - ); - end component; - - component ALU - port( alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - sample_out_s : out std_logic_vector(17 downto 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component RAM_CTRLR_v2 - port( ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - ram_output : out std_logic_vector(17 downto 0); - waddr_previous : in std_logic_vector(1 downto 0) := (others => 'U'); - ram_write_i : in std_logic := 'U'; - RAM_CTRLR_v2_VCC : in std_logic := 'U'; - RAM_CTRLR_v2_GND : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - raddr_add1 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - raddr_rst : in std_logic := 'U' - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \reg_sample_in6\, N_850, \ram_output[4]\, - \sample_in_s_27[4]\, N_851, \ram_output[5]\, - \sample_in_s_25[5]\, N_852, \ram_output[6]\, - \sample_in_s_23[6]\, N_853, \ram_output[7]\, - \sample_in_s_21[7]\, N_854, \ram_output[8]\, - \sample_in_s_19[8]\, N_855, \ram_output[9]\, - \sample_in_s_17[9]\, N_856, \ram_output[10]\, - \sample_in_s_15[10]\, N_857, \ram_output[11]\, - \sample_in_s_13[11]\, N_858, \ram_output[12]\, - \sample_in_s_11[12]\, N_859, \ram_output[13]\, - \sample_in_s_9[13]\, N_860, \ram_output[14]\, - \sample_in_s_7[14]\, N_861, \ram_output[15]\, N_862, - \ram_output[16]\, N_863, \ram_output[17]\, - \reg_sample_in_5[4]\, reg_sample_in_5_sn_N_2_i, - \reg_sample_in_5[5]\, \reg_sample_in_5[6]\, - \reg_sample_in_5[7]\, \reg_sample_in_5[8]\, - \reg_sample_in_5[9]\, \reg_sample_in_5[10]\, - \reg_sample_in_5[11]\, \reg_sample_in_5[12]\, - \reg_sample_in_5[13]\, \reg_sample_in_5[14]\, - \reg_sample_in_5[15]\, \reg_sample_in_5[16]\, - \sample_out_s[16]\, \reg_sample_in_5[17]\, - \sample_out_s[17]\, N_890, \reg_sample_in[4]_net_1\, - \sample_out_s[4]\, N_891, \reg_sample_in[5]_net_1\, - \sample_out_s[5]\, N_892, \reg_sample_in[6]_net_1\, - \sample_out_s[6]\, N_893, \reg_sample_in[7]_net_1\, - \sample_out_s[7]\, N_894, \reg_sample_in[8]_net_1\, - \sample_out_s[8]\, N_895, \reg_sample_in[9]_net_1\, - \sample_out_s[9]\, N_896, \reg_sample_in[10]_net_1\, - \sample_out_s[10]\, N_897, \reg_sample_in[11]_net_1\, - \sample_out_s[11]\, N_898, \reg_sample_in[12]_net_1\, - \sample_out_s[12]\, N_899, \reg_sample_in[13]_net_1\, - \sample_out_s[13]\, N_900, \reg_sample_in[14]_net_1\, - \sample_out_s[14]\, N_901, \reg_sample_in[15]_net_1\, - \sample_out_s[15]\, N_902, \reg_sample_in[16]_net_1\, - N_903, \reg_sample_in[17]_net_1\, \ram_input[4]\, - \ram_input[5]\, \ram_input[6]\, \ram_input[7]\, - \ram_input[8]\, \ram_input[9]\, \ram_input[10]\, - \ram_input[11]\, \ram_input[12]\, \ram_input[13]\, - \ram_input[14]\, \ram_input[15]\, \ram_input[16]\, - \ram_input[17]\, \alu_sample[0]\, - \reg_sample_in[0]_net_1\, \ram_output[0]\, - \alu_sample[3]\, \reg_sample_in[3]_net_1\, - \ram_output[3]\, \alu_sample[4]\, \alu_sample[5]\, - \alu_sample[6]\, \alu_sample[7]\, \alu_sample[8]\, - \alu_sample[9]\, \alu_sample[10]\, \alu_sample[11]\, - \alu_sample[12]\, \alu_sample[13]\, \alu_sample[14]\, - \alu_sample[15]\, \alu_sample[16]\, \alu_sample[17]\, - N_849, \sample_in_s_29[3]\, \reg_sample_in_5[3]\, N_889, - \sample_out_s[3]\, \ram_input[3]\, N_846, - \sample_in_s_35[0]\, \reg_sample_in_5[0]\, N_886, - \sample_out_s[0]\, \ram_input[0]\, \sample_in_s_33[1]\, - \sample_in_s_31[2]\, \ram_input[2]\, N_888, - \ram_output[2]\, \reg_sample_in[2]_net_1\, - \reg_sample_in_5[2]\, \sample_out_s[2]\, N_848, - \alu_sample[2]\, \ram_input[1]\, N_887, \ram_output[1]\, - \reg_sample_in[1]_net_1\, \reg_sample_in_5[1]\, - \sample_out_s[1]\, N_847, \alu_sample[1]\, - \alu_coef_s[0]\, \alu_coef_s[1]\, \alu_coef_s[2]\, - \alu_coef_s[3]\, \alu_coef_s[4]\, \alu_coef_s[5]\, - \alu_coef_s[6]\, \alu_coef_s[7]\, \alu_coef_s[8]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : MUXN_9_5 - Use entity work.MUXN_9_5(DEF_ARCH); - for all : ALU - Use entity work.ALU(DEF_ARCH); - for all : RAM_CTRLR_v2 - Use entity work.RAM_CTRLR_v2(DEF_ARCH); -begin - - sample_out_s_1 <= \sample_out_s[1]\; - sample_out_s_2 <= \sample_out_s[2]\; - sample_out_s_0 <= \sample_out_s[0]\; - sample_out_s_3 <= \sample_out_s[3]\; - sample_out_s_15 <= \sample_out_s[15]\; - sample_out_s_14 <= \sample_out_s[14]\; - sample_out_s_13 <= \sample_out_s[13]\; - sample_out_s_12 <= \sample_out_s[12]\; - sample_out_s_11 <= \sample_out_s[11]\; - sample_out_s_10 <= \sample_out_s[10]\; - sample_out_s_9 <= \sample_out_s[9]\; - sample_out_s_8 <= \sample_out_s[8]\; - sample_out_s_7 <= \sample_out_s[7]\; - sample_out_s_6 <= \sample_out_s[6]\; - sample_out_s_5 <= \sample_out_s[5]\; - sample_out_s_4 <= \sample_out_s[4]\; - - \reg_sample_in_RNO_1[10]\ : MX2 - port map(A => sample_in_buf(133), B => sample_0(10), S => - sample_val_delay_1, Y => \sample_in_s_15[10]\); - - \reg_sample_in_RNO[2]\ : MX2 - port map(A => \sample_out_s[2]\, B => N_848, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[2]\); - - \reg_sample_in_RNISFS13[10]\ : MX2 - port map(A => N_896, B => \ram_output[10]\, S => - ram_sel_Wdata(1), Y => \ram_input[10]\); - - \reg_sample_in_RNI3APO2[2]\ : MX2 - port map(A => \reg_sample_in[2]_net_1\, B => - \ram_output[2]\, S => alu_sel_input, Y => \alu_sample[2]\); - - \reg_sample_in_RNO_1[1]\ : MX2 - port map(A => sample_in_buf(142), B => sample_0(1), S => - sample_val_delay_1, Y => \sample_in_s_33[1]\); - - \reg_sample_in_RNIAPCV2[2]\ : MX2 - port map(A => N_888, B => \ram_output[2]\, S => - ram_sel_Wdata(1), Y => \ram_input[2]\); - - \reg_sample_in_RNI65PT2[8]\ : MX2 - port map(A => N_894, B => \ram_output[8]\, S => - ram_sel_Wdata(1), Y => \ram_input[8]\); - - \reg_sample_in_RNIFAPO2[8]\ : MX2 - port map(A => \reg_sample_in[8]_net_1\, B => - \ram_output[8]\, S => alu_sel_input, Y => \alu_sample[8]\); - - \reg_sample_in_RNO_0[7]\ : MX2 - port map(A => \ram_output[7]\, B => \sample_in_s_21[7]\, S - => in_sel_src(0), Y => N_853); - - \reg_sample_in[5]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[5]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[5]_net_1\); - - \reg_sample_in_RNIA1VB[12]\ : MX2 - port map(A => \reg_sample_in[12]_net_1\, B => - \sample_out_s[12]\, S => ram_sel_Wdata(0), Y => N_898); - - \reg_sample_in_RNI5APO2[3]\ : MX2 - port map(A => \reg_sample_in[3]_net_1\, B => - \ram_output[3]\, S => alu_sel_input, Y => \alu_sample[3]\); - - \reg_sample_in_RNO_0[0]\ : MX2 - port map(A => \ram_output[0]\, B => \sample_in_s_35[0]\, S - => in_sel_src(0), Y => N_846); - - \reg_sample_in_RNI20U13[15]\ : MX2 - port map(A => N_901, B => \ram_output[15]\, S => - ram_sel_Wdata(1), Y => \ram_input[15]\); - - \reg_sample_in_RNO_0[1]\ : MX2 - port map(A => \ram_output[1]\, B => \sample_in_s_33[1]\, S - => in_sel_src(0), Y => N_847); - - \reg_sample_in_RNI8PVB[16]\ : MX2 - port map(A => \reg_sample_in[16]_net_1\, B => - \sample_out_s[16]\, S => ram_sel_Wdata(0), Y => N_902); - - \reg_sample_in_RNO_0[2]\ : MX2 - port map(A => \ram_output[2]\, B => \sample_in_s_31[2]\, S - => in_sel_src(0), Y => N_848); - - \reg_sample_in_RNI68U13[16]\ : MX2 - port map(A => N_902, B => \ram_output[16]\, S => - ram_sel_Wdata(1), Y => \ram_input[16]\); - - \reg_sample_in_RNIM4PT2[4]\ : MX2 - port map(A => N_890, B => \ram_output[4]\, S => - ram_sel_Wdata(1), Y => \ram_input[4]\); - - \reg_sample_in_RNO[11]\ : MX2 - port map(A => \sample_out_s[11]\, B => N_857, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[11]\); - - \reg_sample_in_RNO_1[2]\ : MX2 - port map(A => sample_in_buf(141), B => sample_0(2), S => - sample_val_delay_1, Y => \sample_in_s_31[2]\); - - \reg_sample_in_RNO_0[11]\ : MX2 - port map(A => \ram_output[11]\, B => \sample_in_s_13[11]\, - S => in_sel_src(0), Y => N_857); - - \reg_sample_in_RNI9LTS2[14]\ : MX2 - port map(A => \reg_sample_in[14]_net_1\, B => - \ram_output[14]\, S => alu_sel_input, Y => - \alu_sample[14]\); - - \reg_sample_in_RNI8RLC[3]\ : MX2 - port map(A => \reg_sample_in[3]_net_1\, B => - \sample_out_s[3]\, S => ram_sel_Wdata(0), Y => N_889); - - \reg_sample_in_RNI7TUB[11]\ : MX2 - port map(A => \reg_sample_in[11]_net_1\, B => - \sample_out_s[11]\, S => ram_sel_Wdata(0), Y => N_897); - - reg_sample_in6 : NOR2 - port map(A => in_sel_src(1), B => in_sel_src(0), Y => - \reg_sample_in6\); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg_sample_in_RNO[13]\ : MX2 - port map(A => \sample_out_s[13]\, B => N_859, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[13]\); - - \reg_sample_in[3]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[3]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[3]_net_1\); - - \reg_sample_in_RNO_1[9]\ : MX2 - port map(A => sample_in_buf(134), B => sample_0(9), S => - sample_val_delay_0, Y => \sample_in_s_17[9]\); - - \reg_sample_in_RNIU79E[1]\ : MX2 - port map(A => \reg_sample_in[1]_net_1\, B => - \sample_out_s[1]\, S => ram_sel_Wdata(0), Y => N_887); - - \reg_sample_in_RNI1APO2[1]\ : MX2 - port map(A => \reg_sample_in[1]_net_1\, B => - \ram_output[1]\, S => alu_sel_input, Y => \alu_sample[1]\); - - \reg_sample_in_RNO[4]\ : MX2 - port map(A => \sample_out_s[4]\, B => N_850, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[4]\); - - \reg_sample_in_RNI0OS13[11]\ : MX2 - port map(A => N_897, B => \ram_output[11]\, S => - ram_sel_Wdata(1), Y => \ram_input[11]\); - - \reg_sample_in[7]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[7]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[7]_net_1\); - - \reg_sample_in_RNI5LVB[15]\ : MX2 - port map(A => \reg_sample_in[15]_net_1\, B => - \sample_out_s[15]\, S => ram_sel_Wdata(0), Y => N_901); - - \reg_sample_in[14]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[14]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[14]_net_1\); - - \reg_sample_in_RNIHRLC[6]\ : MX2 - port map(A => \reg_sample_in[6]_net_1\, B => - \sample_out_s[6]\, S => ram_sel_Wdata(0), Y => N_892); - - \reg_sample_in_RNIKRLC[7]\ : MX2 - port map(A => \reg_sample_in[7]_net_1\, B => - \sample_out_s[7]\, S => ram_sel_Wdata(0), Y => N_893); - - \reg_sample_in_RNI6HCV2[1]\ : MX2 - port map(A => N_887, B => \ram_output[1]\, S => - ram_sel_Wdata(1), Y => \ram_input[1]\); - - \reg_sample_in_RNI1G9E[2]\ : MX2 - port map(A => \reg_sample_in[2]_net_1\, B => - \sample_out_s[2]\, S => ram_sel_Wdata(0), Y => N_888); - - \reg_sample_in_RNO[3]\ : MX2 - port map(A => \sample_out_s[3]\, B => N_849, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[3]\); - - \reg_sample_in_RNIQ4PT2[5]\ : MX2 - port map(A => N_891, B => \ram_output[5]\, S => - ram_sel_Wdata(1), Y => \ram_input[5]\); - - \reg_sample_in_RNO_1[11]\ : MX2 - port map(A => sample_in_buf(132), B => sample_0(11), S => - sample_val_delay_0, Y => \sample_in_s_13[11]\); - - \reg_sample_in_RNO[1]\ : MX2 - port map(A => \sample_out_s[1]\, B => N_847, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[1]\); - - \reg_sample_in_RNI9APO2[5]\ : MX2 - port map(A => \reg_sample_in[5]_net_1\, B => - \ram_output[5]\, S => alu_sel_input, Y => \alu_sample[5]\); - - \reg_sample_in[9]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[9]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[9]_net_1\); - - \reg_sample_in_RNO_0[15]\ : MX2 - port map(A => \ram_output[15]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_861); - - \reg_sample_in_RNIBRLC[4]\ : MX2 - port map(A => \reg_sample_in[4]_net_1\, B => - \sample_out_s[4]\, S => ram_sel_Wdata(0), Y => N_890); - - \reg_sample_in_RNI4PUB[10]\ : MX2 - port map(A => \reg_sample_in[10]_net_1\, B => - \sample_out_s[10]\, S => ram_sel_Wdata(0), Y => N_896); - - \reg_sample_in_RNO[8]\ : MX2 - port map(A => \sample_out_s[8]\, B => N_854, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[8]\); - - \reg_sample_in_RNO[12]\ : MX2 - port map(A => \sample_out_s[12]\, B => N_858, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[12]\); - - \reg_sample_in_RNO_0[16]\ : MX2 - port map(A => \ram_output[16]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_862); - - \reg_sample_in[16]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[16]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[16]_net_1\); - - \reg_sample_in_RNO_1[5]\ : MX2 - port map(A => sample_in_buf(138), B => sample_0(5), S => - sample_val_delay_5, Y => \sample_in_s_25[5]\); - - Coeff_Mux : MUXN_9_5 - port map(S_36 => S_36, S_0 => S_0, alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_sel_coeff(2) => alu_sel_coeff(2), alu_sel_coeff(1) - => alu_sel_coeff(1), alu_sel_coeff(0) => - alu_sel_coeff(0), alu_sel_coeff_0_0 => alu_sel_coeff_0_0, - alu_sel_coeff_0_2 => alu_sel_coeff_0_2, alu_coef_s(8) => - \alu_coef_s[8]\, alu_coef_s(7) => \alu_coef_s[7]\, - alu_coef_s(6) => \alu_coef_s[6]\, alu_coef_s(5) => - \alu_coef_s[5]\, alu_coef_s(4) => \alu_coef_s[4]\, - alu_coef_s(3) => \alu_coef_s[3]\, alu_coef_s(2) => - \alu_coef_s[2]\, alu_coef_s(1) => \alu_coef_s[1]\, - alu_coef_s(0) => \alu_coef_s[0]\); - - ALU_1 : ALU - port map(alu_ctrl(2) => alu_ctrl(2), alu_ctrl(1) => - alu_ctrl(1), alu_ctrl(0) => alu_ctrl(0), alu_coef_s(8) - => \alu_coef_s[8]\, alu_coef_s(7) => \alu_coef_s[7]\, - alu_coef_s(6) => \alu_coef_s[6]\, alu_coef_s(5) => - \alu_coef_s[5]\, alu_coef_s(4) => \alu_coef_s[4]\, - alu_coef_s(3) => \alu_coef_s[3]\, alu_coef_s(2) => - \alu_coef_s[2]\, alu_coef_s(1) => \alu_coef_s[1]\, - alu_coef_s(0) => \alu_coef_s[0]\, alu_sample(17) => - \alu_sample[17]\, alu_sample(16) => \alu_sample[16]\, - alu_sample(15) => \alu_sample[15]\, alu_sample(14) => - \alu_sample[14]\, alu_sample(13) => \alu_sample[13]\, - alu_sample(12) => \alu_sample[12]\, alu_sample(11) => - \alu_sample[11]\, alu_sample(10) => \alu_sample[10]\, - alu_sample(9) => \alu_sample[9]\, alu_sample(8) => - \alu_sample[8]\, alu_sample(7) => \alu_sample[7]\, - alu_sample(6) => \alu_sample[6]\, alu_sample(5) => - \alu_sample[5]\, alu_sample(4) => \alu_sample[4]\, - alu_sample(3) => \alu_sample[3]\, alu_sample(2) => - \alu_sample[2]\, alu_sample(1) => \alu_sample[1]\, - alu_sample(0) => \alu_sample[0]\, sample_out_s(17) => - \sample_out_s[17]\, sample_out_s(16) => - \sample_out_s[16]\, sample_out_s(15) => - \sample_out_s[15]\, sample_out_s(14) => - \sample_out_s[14]\, sample_out_s(13) => - \sample_out_s[13]\, sample_out_s(12) => - \sample_out_s[12]\, sample_out_s(11) => - \sample_out_s[11]\, sample_out_s(10) => - \sample_out_s[10]\, sample_out_s(9) => \sample_out_s[9]\, - sample_out_s(8) => \sample_out_s[8]\, sample_out_s(7) => - \sample_out_s[7]\, sample_out_s(6) => \sample_out_s[6]\, - sample_out_s(5) => \sample_out_s[5]\, sample_out_s(4) => - \sample_out_s[4]\, sample_out_s(3) => \sample_out_s[3]\, - sample_out_s(2) => \sample_out_s[2]\, sample_out_s(1) => - \sample_out_s[1]\, sample_out_s(0) => \sample_out_s[0]\, - rstn => rstn, lclk_c => lclk_c); - - \reg_sample_in_RNIRV8E[0]\ : MX2 - port map(A => \reg_sample_in[0]_net_1\, B => - \sample_out_s[0]\, S => ram_sel_Wdata(0), Y => N_886); - - \reg_sample_in[8]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[8]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[8]_net_1\); - - \reg_sample_in[13]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[13]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[13]_net_1\); - - \reg_sample_in_RNI3TSS2[11]\ : MX2 - port map(A => \reg_sample_in[11]_net_1\, B => - \ram_output[11]\, S => alu_sel_input, Y => - \alu_sample[11]\); - - \reg_sample_in_RNIVCVB[13]\ : MX2 - port map(A => \reg_sample_in[13]_net_1\, B => - \sample_out_s[13]\, S => ram_sel_Wdata(0), Y => N_899); - - \reg_sample_in[12]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[12]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[12]_net_1\); - - \reg_sample_in_RNIBAPO2[6]\ : MX2 - port map(A => \reg_sample_in[6]_net_1\, B => - \ram_output[6]\, S => alu_sel_input, Y => \alu_sample[6]\); - - \reg_sample_in[10]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[10]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[10]_net_1\); - - \reg_sample_in_RNIUNT13[14]\ : MX2 - port map(A => N_900, B => \ram_output[14]\, S => - ram_sel_Wdata(1), Y => \ram_input[14]\); - - \reg_sample_in[6]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[6]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[6]_net_1\); - - \reg_sample_in[1]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[1]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[1]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \reg_sample_in_RNO[10]\ : MX2 - port map(A => \sample_out_s[10]\, B => N_856, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[10]\); - - \reg_sample_in_RNI55TS2[12]\ : MX2 - port map(A => \reg_sample_in[12]_net_1\, B => - \ram_output[12]\, S => alu_sel_input, Y => - \alu_sample[12]\); - - \reg_sample_in_RNI25PT2[7]\ : MX2 - port map(A => N_893, B => \ram_output[7]\, S => - ram_sel_Wdata(1), Y => \ram_input[7]\); - - \reg_sample_in_RNO_0[5]\ : MX2 - port map(A => \ram_output[5]\, B => \sample_in_s_25[5]\, S - => in_sel_src(0), Y => N_851); - - \reg_sample_in[2]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[2]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[2]_net_1\); - - \reg_sample_in_RNO_1[4]\ : MX2 - port map(A => sample_in_buf(139), B => sample_0(4), S => - sample_val_delay_1, Y => \sample_in_s_27[4]\); - - \reg_sample_in_RNIDAPO2[7]\ : MX2 - port map(A => \reg_sample_in[7]_net_1\, B => - \ram_output[7]\, S => alu_sel_input, Y => \alu_sample[7]\); - - \reg_sample_in_RNIA5PT2[9]\ : MX2 - port map(A => N_895, B => \ram_output[9]\, S => - ram_sel_Wdata(1), Y => \ram_input[9]\); - - \reg_sample_in_RNIQRLC[9]\ : MX2 - port map(A => \reg_sample_in[9]_net_1\, B => - \sample_out_s[9]\, S => ram_sel_Wdata(0), Y => N_895); - - \reg_sample_in[17]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[17]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[17]_net_1\); - - \reg_sample_in_RNIV9PO2[0]\ : MX2 - port map(A => \reg_sample_in[0]_net_1\, B => - \ram_output[0]\, S => alu_sel_input, Y => \alu_sample[0]\); - - \reg_sample_in_RNIQFT13[13]\ : MX2 - port map(A => N_899, B => \ram_output[13]\, S => - ram_sel_Wdata(1), Y => \ram_input[13]\); - - \reg_sample_in_RNO[7]\ : MX2 - port map(A => \sample_out_s[7]\, B => N_853, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[7]\); - - \reg_sample_in_RNO[16]\ : MX2 - port map(A => \sample_out_s[16]\, B => N_862, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[16]\); - - \reg_sample_in[4]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[4]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[4]_net_1\); - - \reg_sample_in_RNO_1[7]\ : MX2 - port map(A => sample_in_buf(136), B => sample_0(7), S => - sample_val_delay_0, Y => \sample_in_s_21[7]\); - - \reg_sample_in_RNO_1[3]\ : MX2 - port map(A => sample_in_buf(140), B => sample_0(3), S => - sample_val_delay_1, Y => \sample_in_s_29[3]\); - - \reg_sample_in_RNO_0[12]\ : MX2 - port map(A => \ram_output[12]\, B => \sample_in_s_11[12]\, - S => in_sel_src(0), Y => N_858); - - \reg_sample_in_RNO[6]\ : MX2 - port map(A => \sample_out_s[6]\, B => N_852, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[6]\); - - \reg_sample_in_RNIHAPO2[9]\ : MX2 - port map(A => \reg_sample_in[9]_net_1\, B => - \ram_output[9]\, S => alu_sel_input, Y => \alu_sample[9]\); - - \reg_sample_in[15]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[15]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[15]_net_1\); - - \reg_sample_in_RNO_0[4]\ : MX2 - port map(A => \ram_output[4]\, B => \sample_in_s_27[4]\, S - => in_sel_src(0), Y => N_850); - - \reg_sample_in_RNO_0[3]\ : MX2 - port map(A => \ram_output[3]\, B => \sample_in_s_29[3]\, S - => in_sel_src(0), Y => N_849); - - \reg_sample_in_RNO_0[17]\ : MX2 - port map(A => \ram_output[17]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_863); - - \reg_sample_in_RNO[17]\ : MX2 - port map(A => \sample_out_s[17]\, B => N_863, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[17]\); - - \reg_sample_in_RNO[14]\ : MX2 - port map(A => \sample_out_s[14]\, B => N_860, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[14]\); - - \reg_sample_in_RNINRLC[8]\ : MX2 - port map(A => \reg_sample_in[8]_net_1\, B => - \sample_out_s[8]\, S => ram_sel_Wdata(0), Y => N_894); - - \reg_sample_in_RNI2HVB[14]\ : MX2 - port map(A => \reg_sample_in[14]_net_1\, B => - \sample_out_s[14]\, S => ram_sel_Wdata(0), Y => N_900); - - \reg_sample_in_RNI1LSS2[10]\ : MX2 - port map(A => \reg_sample_in[10]_net_1\, B => - \ram_output[10]\, S => alu_sel_input, Y => - \alu_sample[10]\); - - \reg_sample_in_RNO_1[8]\ : MX2 - port map(A => sample_in_buf(135), B => sample_0(8), S => - sample_val_delay_0, Y => \sample_in_s_19[8]\); - - \reg_sample_in_RNI7DTS2[13]\ : MX2 - port map(A => \reg_sample_in[13]_net_1\, B => - \ram_output[13]\, S => alu_sel_input, Y => - \alu_sample[13]\); - - \reg_sample_in_RNI40T13[12]\ : MX2 - port map(A => N_898, B => \ram_output[12]\, S => - ram_sel_Wdata(1), Y => \ram_input[12]\); - - \reg_sample_in[11]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[11]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[11]_net_1\); - - \reg_sample_in_RNO[5]\ : MX2 - port map(A => \sample_out_s[5]\, B => N_851, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[5]\); - - \reg_sample_in_RNO_0[9]\ : MX2 - port map(A => \ram_output[9]\, B => \sample_in_s_17[9]\, S - => in_sel_src(0), Y => N_855); - - \reg_sample_in_RNO[9]\ : MX2 - port map(A => \sample_out_s[9]\, B => N_855, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[9]\); - - RAM_CTRLR_v2_1 : RAM_CTRLR_v2 - port map(ram_input(17) => \ram_input[17]\, ram_input(16) - => \ram_input[16]\, ram_input(15) => \ram_input[15]\, - ram_input(14) => \ram_input[14]\, ram_input(13) => - \ram_input[13]\, ram_input(12) => \ram_input[12]\, - ram_input(11) => \ram_input[11]\, ram_input(10) => - \ram_input[10]\, ram_input(9) => \ram_input[9]\, - ram_input(8) => \ram_input[8]\, ram_input(7) => - \ram_input[7]\, ram_input(6) => \ram_input[6]\, - ram_input(5) => \ram_input[5]\, ram_input(4) => - \ram_input[4]\, ram_input(3) => \ram_input[3]\, - ram_input(2) => \ram_input[2]\, ram_input(1) => - \ram_input[1]\, ram_input(0) => \ram_input[0]\, - ram_output(17) => \ram_output[17]\, ram_output(16) => - \ram_output[16]\, ram_output(15) => \ram_output[15]\, - ram_output(14) => \ram_output[14]\, ram_output(13) => - \ram_output[13]\, ram_output(12) => \ram_output[12]\, - ram_output(11) => \ram_output[11]\, ram_output(10) => - \ram_output[10]\, ram_output(9) => \ram_output[9]\, - ram_output(8) => \ram_output[8]\, ram_output(7) => - \ram_output[7]\, ram_output(6) => \ram_output[6]\, - ram_output(5) => \ram_output[5]\, ram_output(4) => - \ram_output[4]\, ram_output(3) => \ram_output[3]\, - ram_output(2) => \ram_output[2]\, ram_output(1) => - \ram_output[1]\, ram_output(0) => \ram_output[0]\, - waddr_previous(1) => waddr_previous(1), waddr_previous(0) - => waddr_previous(0), ram_write_i => ram_write_i, - RAM_CTRLR_v2_VCC => IIR_CEL_CTRLR_v2_DATAFLOW_VCC, - RAM_CTRLR_v2_GND => IIR_CEL_CTRLR_v2_DATAFLOW_GND, - ram_write => ram_write, raddr_add1 => raddr_add1, rstn - => rstn, lclk_c => lclk_c, raddr_rst => raddr_rst); - - \reg_sample_in_RNI7APO2[4]\ : MX2 - port map(A => \reg_sample_in[4]_net_1\, B => - \ram_output[4]\, S => alu_sel_input, Y => \alu_sample[4]\); - - \reg_sample_in_RNIFDUS2[17]\ : MX2 - port map(A => \reg_sample_in[17]_net_1\, B => - \ram_output[17]\, S => alu_sel_input, Y => - \alu_sample[17]\); - - \reg_sample_in_RNIBTVB[17]\ : MX2 - port map(A => \reg_sample_in[17]_net_1\, B => - \sample_out_s[17]\, S => ram_sel_Wdata(0), Y => N_903); - - reg_sample_in_5_sn_m1 : OR2B - port map(A => in_sel_src(1), B => in_sel_src(0), Y => - reg_sample_in_5_sn_N_2_i); - - \reg_sample_in_RNO[15]\ : MX2 - port map(A => \sample_out_s[15]\, B => N_861, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[15]\); - - \reg_sample_in_RNO_0[14]\ : MX2 - port map(A => \ram_output[14]\, B => \sample_in_s_7[14]\, S - => in_sel_src(0), Y => N_860); - - \reg_sample_in_RNI29CV2[0]\ : MX2 - port map(A => N_886, B => \ram_output[0]\, S => - ram_sel_Wdata(1), Y => \ram_input[0]\); - - \reg_sample_in_RNO_1[12]\ : MX2 - port map(A => sample_in_buf(131), B => sample_0(12), S => - sample_val_delay_1, Y => \sample_in_s_11[12]\); - - \reg_sample_in_RNII4PT2[3]\ : MX2 - port map(A => N_889, B => \ram_output[3]\, S => - ram_sel_Wdata(1), Y => \ram_input[3]\); - - \reg_sample_in_RNIU4PT2[6]\ : MX2 - port map(A => N_892, B => \ram_output[6]\, S => - ram_sel_Wdata(1), Y => \ram_input[6]\); - - \reg_sample_in_RNO_0[8]\ : MX2 - port map(A => \ram_output[8]\, B => \sample_in_s_19[8]\, S - => in_sel_src(0), Y => N_854); - - \reg_sample_in_RNO_0[13]\ : MX2 - port map(A => \ram_output[13]\, B => \sample_in_s_9[13]\, S - => in_sel_src(0), Y => N_859); - - \reg_sample_in_RNO[0]\ : MX2 - port map(A => \sample_out_s[0]\, B => N_846, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[0]\); - - \reg_sample_in_RNID5US2[16]\ : MX2 - port map(A => \reg_sample_in[16]_net_1\, B => - \ram_output[16]\, S => alu_sel_input, Y => - \alu_sample[16]\); - - \reg_sample_in[0]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[0]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[0]_net_1\); - - \reg_sample_in_RNIAGU13[17]\ : MX2 - port map(A => N_903, B => \ram_output[17]\, S => - ram_sel_Wdata(1), Y => \ram_input[17]\); - - \reg_sample_in_RNO_0[10]\ : MX2 - port map(A => \ram_output[10]\, B => \sample_in_s_15[10]\, - S => in_sel_src(0), Y => N_856); - - \reg_sample_in_RNO_1[14]\ : MX2 - port map(A => sample_in_buf(129), B => sample_0(14), S => - sample_val_delay_1, Y => \sample_in_s_7[14]\); - - \reg_sample_in_RNIERLC[5]\ : MX2 - port map(A => \reg_sample_in[5]_net_1\, B => - \sample_out_s[5]\, S => ram_sel_Wdata(0), Y => N_891); - - \reg_sample_in_RNO_1[6]\ : MX2 - port map(A => sample_in_buf(137), B => sample_0(6), S => - sample_val_delay_1, Y => \sample_in_s_23[6]\); - - \reg_sample_in_RNIBTTS2[15]\ : MX2 - port map(A => \reg_sample_in[15]_net_1\, B => - \ram_output[15]\, S => alu_sel_input, Y => - \alu_sample[15]\); - - \reg_sample_in_RNO_0[6]\ : MX2 - port map(A => \ram_output[6]\, B => \sample_in_s_23[6]\, S - => in_sel_src(0), Y => N_852); - - \reg_sample_in_RNO_1[13]\ : MX2 - port map(A => sample_in_buf(130), B => sample_0(13), S => - sample_val_delay_0, Y => \sample_in_s_9[13]\); - - \reg_sample_in_RNO_1[0]\ : MX2 - port map(A => sample_in_buf(143), B => sample_0(0), S => - sample_val_delay_0, Y => \sample_in_s_35[0]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2_CONTROL is - - port( alu_ctrl : out std_logic_vector(2 downto 0); - ram_sel_Wdata : out std_logic_vector(1 downto 0); - waddr_previous : out std_logic_vector(1 downto 0); - in_sel_src : out std_logic_vector(1 downto 0); - alu_sel_coeff : out std_logic_vector(4 downto 0); - S_36 : in std_logic; - S_0 : in std_logic; - alu_sel_coeff_0_2 : out std_logic; - alu_sel_coeff_0_0 : out std_logic; - sample_out_rot_s : out std_logic; - sample_out_val_s : out std_logic; - raddr_rst : out std_logic; - alu_sel_input : out std_logic; - raddr_add1 : out std_logic; - un1_sample_in_rotate : out std_logic; - sample_val_delay_2 : in std_logic; - sample_val_delay_1 : in std_logic; - ram_write : out std_logic; - ram_write_i : out std_logic; - un1_sample_in_rotate_0 : out std_logic; - un1_sample_in_rotate_1 : out std_logic; - un1_sample_in_rotate_2 : out std_logic; - un1_sample_in_rotate_3 : out std_logic; - sample_val_delay_0 : in std_logic; - un1_sample_in_rotate_4 : out std_logic; - sample_out_rot_s_0 : out std_logic; - sample_out_rot_s_1 : out std_logic; - sample_out_rot_s_2 : out std_logic; - sample_out_rot_s_3 : out std_logic; - sample_out_rot_s_4 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end IIR_CEL_CTRLR_v2_CONTROL; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2_CONTROL is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal Chanel_ongoing_n6_0_i_0_o2_0, - \Chanel_ongoing[6]_net_1\, \Chanel_ongoing[5]_net_1\, - Chanel_ongoing_n29, \Chanel_ongoing[29]_net_1\, N_295, - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Chanel_ongoing_n30, - \Chanel_ongoing[30]_net_1\, N_327, Chanel_ongoing_n31, - \Chanel_ongoing[31]_net_1\, N_335, N_250, - \Chanel_ongoing[0]_net_1\, \Chanel_ongoing[1]_net_1\, - \Chanel_ongoing[2]_net_1\, N_270, - \Chanel_ongoing[13]_net_1\, N_265, N_271, - \Chanel_ongoing[14]_net_1\, N_279, - \Chanel_ongoing[20]_net_1\, N_278, N_290, - \Chanel_ongoing[24]_net_1\, N_288, - \Chanel_ongoing[28]_net_1\, N_293, N_252_i_0, - \Chanel_ongoing[3]_net_1\, \Chanel_ongoing[4]_net_1\, - N_255, \Chanel_ongoing[7]_net_1\, - \Chanel_ongoing[27]_net_1\, N_292, N_291, - \Chanel_ongoing[26]_net_1\, \Chanel_ongoing[25]_net_1\, - \Chanel_ongoing[23]_net_1\, N_286, - \Chanel_ongoing[22]_net_1\, - \Chanel_ongoing_RNIV67U4[21]_net_1\, - \Chanel_ongoing[21]_net_1\, \Chanel_ongoing[19]_net_1\, - N_276, \Chanel_ongoing[18]_net_1\, N_275, - \Chanel_ongoing[17]_net_1\, N_273, - \Chanel_ongoing[16]_net_1\, N_272, - \Chanel_ongoing[15]_net_1\, \Chanel_ongoing[12]_net_1\, - N_264, \Chanel_ongoing[10]_net_1\, N_257, - \Chanel_ongoing[11]_net_1\, \Chanel_ongoing[8]_net_1\, - \Chanel_ongoing[9]_net_1\, alu_selected_coeff_n0, - alu_selected_coeffe, N_713, N_567_i_0, - \IIR_CEL_STATE[8]_net_1\, sample_in_rotate, N_127_0, - N_478, N_480, N_274, - un1_alu_sel_input_0_sqmuxa_1_i_0_s_0_0, N_452, N_480_0, - \IIR_CEL_STATE[4]_net_1\, N_328, N_478_0, N_326, - \DWACT_ADD_CI_0_g_array_4[0]\, - \DWACT_ADD_CI_0_g_array_3[0]\, - \DWACT_ADD_CI_0_pog_array_3[0]\, - \DWACT_ADD_CI_0_g_array_9[0]\, - \DWACT_ADD_CI_0_pog_array_3_1[0]\, - \DWACT_ADD_CI_0_g_array_10[0]\, - \DWACT_ADD_CI_0_pog_array_2_1[0]\, - \DWACT_ADD_CI_0_g_array_10_1[0]\, - \DWACT_ADD_CI_0_pog_array_2_3[0]\, - \DWACT_ADD_CI_0_g_array_11_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_5[0]\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_2[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_11_1[0]\, - \DWACT_ADD_CI_0_pog_array_1_3[0]\, - \DWACT_ADD_CI_0_g_array_10_2[0]\, - \DWACT_ADD_CI_0_pog_array_2_5[0]\, - \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, \Cel_ongoing[6]_net_1\, - \DWACT_ADD_CI_0_g_array_12_9[0]\, \Cel_ongoing[20]_net_1\, - \DWACT_ADD_CI_0_g_array_12_3[0]\, \Cel_ongoing[8]_net_1\, - \DWACT_ADD_CI_0_g_array_12_4[0]\, \Cel_ongoing[10]_net_1\, - \DWACT_ADD_CI_0_g_array_11_3[0]\, - \DWACT_ADD_CI_0_pog_array_1_7[0]\, - \DWACT_ADD_CI_0_g_array_11_4[0]\, - \DWACT_ADD_CI_0_pog_array_1_9[0]\, - \DWACT_ADD_CI_0_g_array_11_5[0]\, - \DWACT_ADD_CI_0_pog_array_1_11[0]\, - \DWACT_ADD_CI_0_g_array_11_6[0]\, - \DWACT_ADD_CI_0_pog_array_1_13[0]\, - \DWACT_ADD_CI_0_g_array_12[0]\, \Cel_ongoing[2]_net_1\, - \DWACT_ADD_CI_0_g_array_12_7[0]\, \Cel_ongoing[16]_net_1\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, \Cel_ongoing[4]_net_1\, - \DWACT_ADD_CI_0_g_array_12_13[0]\, - \Cel_ongoing[28]_net_1\, - \DWACT_ADD_CI_0_g_array_12_14[0]\, - \Cel_ongoing[30]_net_1\, \DWACT_ADD_CI_0_g_array_12_5[0]\, - \Cel_ongoing[12]_net_1\, \DWACT_ADD_CI_0_g_array_12_6[0]\, - \Cel_ongoing[14]_net_1\, \DWACT_ADD_CI_0_g_array_12_8[0]\, - \Cel_ongoing[18]_net_1\, - \DWACT_ADD_CI_0_g_array_12_10[0]\, - \Cel_ongoing[22]_net_1\, - \DWACT_ADD_CI_0_g_array_12_11[0]\, - \Cel_ongoing[24]_net_1\, - \DWACT_ADD_CI_0_g_array_12_12[0]\, - \Cel_ongoing[26]_net_1\, \DWACT_ADD_CI_0_TMP[0]\, - \Cel_ongoing[1]_net_1\, \IIR_CEL_STATE_i_i[9]\, - \IIR_CEL_STATE_i[9]_net_1\, Chanel_ongoing_n8_0_i_0_0, - Chanel_ongoing_n2_0_i_0_0, Chanel_ongoing_n4_0_i_0_0, - Chanel_ongoing_n7_0_i_0_0, Chanel_ongoing_n6_0_i_0_0, - Chanel_ongoing_n5_0_i_0_0, Chanel_ongoing_n1_0_i_0_0, - N_294, N_451_1, N_453, alu_selected_coeff_n2_0_i_0, - \alu_sel_coeff_0[2]\, alu_selected_coeff_n3_0_i_0, N_717, - un1_IIR_CEL_STATE_20_0_0, \IIR_CEL_STATE[0]_net_1\, - \IIR_CEL_STATE[5]_net_1\, raddr_add1_2_i_a2_0_0, - \IIR_CEL_STATE[3]_net_1\, \in_sel_src_8_i_a2_0_a2_0_0[1]\, - \IIR_CEL_STATE[6]_net_1\, \IIR_CEL_STATE[7]_net_1\, - Cel_ongoing_0_sqmuxa_0_a2_0_27, - Cel_ongoing_0_sqmuxa_0_a2_0_16, - Cel_ongoing_0_sqmuxa_0_a2_0_15, - Cel_ongoing_0_sqmuxa_0_a2_0_24, - Cel_ongoing_0_sqmuxa_0_a2_0_26, - Cel_ongoing_0_sqmuxa_0_a2_0_12, - Cel_ongoing_0_sqmuxa_0_a2_0_11, - Cel_ongoing_0_sqmuxa_0_a2_0_22, - Cel_ongoing_0_sqmuxa_0_a2_0_25, - Cel_ongoing_0_sqmuxa_0_a2_0_8, - Cel_ongoing_0_sqmuxa_0_a2_0_7, - Cel_ongoing_0_sqmuxa_0_a2_0_20, N_479, - Cel_ongoing_0_sqmuxa_0_a2_0_4, - Cel_ongoing_0_sqmuxa_0_a2_0_18, - Cel_ongoing_0_sqmuxa_0_a2_0_14, - Cel_ongoing_0_sqmuxa_0_a2_0_10, - Cel_ongoing_0_sqmuxa_0_a2_0_6, - Cel_ongoing_0_sqmuxa_0_a2_0_3, - Cel_ongoing_0_sqmuxa_0_a2_0_1, - \in_sel_src_8_i_a2_0_o2_0_27[1]\, - \in_sel_src_8_i_a2_0_o2_0_18[1]\, - \in_sel_src_8_i_a2_0_o2_0_17[1]\, - \in_sel_src_8_i_a2_0_o2_0_23[1]\, - \in_sel_src_8_i_a2_0_o2_0_26[1]\, - \in_sel_src_8_i_a2_0_o2_0_12[1]\, - \in_sel_src_8_i_a2_0_o2_0_11[1]\, - \in_sel_src_8_i_a2_0_o2_0_22[1]\, - \in_sel_src_8_i_a2_0_o2_0_25[1]\, - \in_sel_src_8_i_a2_0_o2_0_8[1]\, - \in_sel_src_8_i_a2_0_o2_0_7[1]\, - \in_sel_src_8_i_a2_0_o2_0_20[1]\, - \in_sel_src_8_i_a2_0_o2_0_2[1]\, - \in_sel_src_8_i_a2_0_o2_0_1[1]\, - \in_sel_src_8_i_a2_0_o2_0_15[1]\, - \in_sel_src_8_i_a2_0_o2_0_14[1]\, \Cel_ongoing[27]_net_1\, - \in_sel_src_8_i_a2_0_o2_0_10[1]\, \Cel_ongoing[19]_net_1\, - \in_sel_src_8_i_a2_0_o2_0_6[1]\, \Cel_ongoing[11]_net_1\, - \in_sel_src_8_i_a2_0_o2_0_4[1]\, \Cel_ongoing[7]_net_1\, - \Cel_ongoing[0]_net_1\, \Cel_ongoing[31]_net_1\, - \Cel_ongoing[29]_net_1\, \Cel_ongoing[25]_net_1\, - \Cel_ongoing[23]_net_1\, \Cel_ongoing[21]_net_1\, - \Cel_ongoing[17]_net_1\, \Cel_ongoing[15]_net_1\, - \Cel_ongoing[13]_net_1\, \Cel_ongoing[9]_net_1\, - \Cel_ongoing[5]_net_1\, \Cel_ongoing[3]_net_1\, - ram_write_2_0_a2_0, N_736, \raddr_add1_RNO\, N_737, N_735, - N_289, un1_alu_sel_input_0_sqmuxa_1_i_0, N_206, - \Cel_ongoing_6_i_i_0[0]\, N_457, N_454, - un1_IIR_CEL_STATE_20, N_796_i, N_18, N_703, N_714, N_20, - N_22, N_650, N_11, N_325, N_651_i_0, - \Cel_ongoing_6_i_i_a2_0_0[0]\, - \DWACT_ADD_CI_0_partial_sum[0]\, N_216_i, - \Chanel_ongoing_RNO_0[12]_net_1\, sample_in_rot_2, - N_568_i_0, N_334, N_729, N_269, N_332, N_268, N_512_i_0, - N_180, N_569, N_465, I_120, \IIR_CEL_STATE[2]_net_1\, - \IIR_CEL_STATE[1]_net_1\, un1_IIR_CEL_STATE_24, N_523, - un1_IIR_CEL_STATE_22, N_204, N_353, N_227, - \IIR_CEL_STATE_ns[8]\, alu_sel_input_1, - \IIR_CEL_STATE_RNI87UP_1[4]_net_1\, un1_IIR_CEL_STATE_18, - ram_write_2, N_477, N_450, I_121, N_449, I_115_4, N_448, - I_109, N_447, I_116, N_446, I_110, N_445, I_129_4, N_444, - I_125, N_443, I_130, N_442, I_127, N_441, I_126, N_440, - I_124, N_439, I_122_4, N_438, I_128, N_437, I_123, N_436, - I_117, N_435, I_111, \Cel_ongoing_RNO[15]_net_1\, I_118, - \Cel_ongoing_RNO[14]_net_1\, I_112, - \Cel_ongoing_RNO[13]_net_1\, I_106, - \Cel_ongoing_RNO[12]_net_1\, I_101, - \Cel_ongoing_RNO[11]_net_1\, I_107, - \Cel_ongoing_RNO[10]_net_1\, I_105_4, - \Cel_ongoing_RNO[9]_net_1\, I_103, - \Cel_ongoing_RNO[8]_net_1\, I_102, - \Cel_ongoing_RNO[7]_net_1\, I_99, - \Cel_ongoing_RNO[6]_net_1\, I_104, - \Cel_ongoing_RNO[5]_net_1\, I_100, - \Cel_ongoing_RNO[4]_net_1\, I_119, - \Cel_ongoing_RNO[3]_net_1\, I_113, - \Cel_ongoing_RNO[1]_net_1\, I_114, N_127, - Chanel_ongoing_n0, Chanel_ongoing_n20, Chanel_ongoing_n24, - Chanel_ongoing_n28, N_224, N_724, N_336_i_i_0, N_15_i, - \alu_sel_coeff[3]\, N_715, N_712, \alu_sel_coeff_0[0]\, - N_221, N_461, N_373_i, N_374_i, N_372_i, N_232, N_229, - Chanel_ongoing_n27, Chanel_ongoing_n26, - Chanel_ongoing_n25, Chanel_ongoing_n23, - Chanel_ongoing_n22, Chanel_ongoing_n21, - Chanel_ongoing_n19, Chanel_ongoing_n18, - Chanel_ongoing_n17, N_462, N_460, \alu_sel_coeff[4]\, - ram_write_net_1, \DWACT_ADD_CI_0_pog_array_2_4[0]\, - \DWACT_ADD_CI_0_pog_array_1_10[0]\, - \DWACT_ADD_CI_0_pog_array_1_8[0]\, - \DWACT_ADD_CI_0_pog_array_1_4[0]\, - \DWACT_ADD_CI_0_pog_array_1_6[0]\, - \DWACT_ADD_CI_0_pog_array_1_12[0]\, - \DWACT_ADD_CI_0_pog_array_2_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_2[0]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - alu_sel_coeff(4) <= \alu_sel_coeff[4]\; - alu_sel_coeff(3) <= \alu_sel_coeff[3]\; - alu_sel_coeff_0_2 <= \alu_sel_coeff_0[2]\; - alu_sel_coeff_0_0 <= \alu_sel_coeff_0[0]\; - ram_write <= ram_write_net_1; - - un1_Cel_ongoing_1_I_148 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \Cel_ongoing[4]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_1[0]\); - - \IIR_CEL_STATE_i_RNI151I[9]\ : OR2B - port map(A => N_294, B => \IIR_CEL_STATE_i[9]_net_1\, Y => - N_326); - - sample_in_rot_RNO : NOR2A - port map(A => \IIR_CEL_STATE[7]_net_1\, B => N_328, Y => - sample_in_rot_2); - - \Cel_ongoing_RNO[9]\ : NOR3C - port map(A => N_478, B => N_480, C => I_103, Y => - \Cel_ongoing_RNO[9]_net_1\); - - \Chanel_ongoing_RNIV67U4[21]\ : OR2A - port map(A => \Chanel_ongoing[21]_net_1\, B => N_279, Y => - \Chanel_ongoing_RNIV67U4[21]_net_1\); - - \in_sel_src[0]\ : DFN1E0C0 - port map(D => N_268, CLK => lclk_c, CLR => rstn, E => - un1_IIR_CEL_STATE_24, Q => in_sel_src(0)); - - \IIR_CEL_STATE_RNI3IM46_0[4]\ : OR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_328, Y => - N_480_0); - - \Chanel_ongoing[1]\ : DFN1E1C0 - port map(D => N_18, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[1]_net_1\); - - \Cel_ongoing_RNI8SOP5[7]\ : OR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_26[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_25[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_27[1]\, Y => N_325); - - \in_sel_src_RNO_0[1]\ : OR2 - port map(A => \IIR_CEL_STATE[6]_net_1\, B => - \IIR_CEL_STATE[7]_net_1\, Y => - \in_sel_src_8_i_a2_0_a2_0_0[1]\); - - \IIR_CEL_STATE_RNI87UP_0[4]\ : OR2A - port map(A => N_326, B => \IIR_CEL_STATE[4]_net_1\, Y => - N_478_0); - - \Cel_ongoing[23]\ : DFN1C0 - port map(D => N_442, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[23]_net_1\); - - \Cel_ongoing[22]\ : DFN1C0 - port map(D => N_441, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[22]_net_1\); - - \Chanel_ongoing[29]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n29, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[29]_net_1\); - - \Cel_ongoing_RNO[17]\ : NOR3C - port map(A => N_478_0, B => N_480, C => I_117, Y => N_436); - - \IIR_CEL_STATE_i_RNI4P117_0[9]\ : OR3B - port map(A => N_478, B => N_480, C => N_274, Y => N_127); - - un1_Cel_ongoing_1_I_123 : XOR2 - port map(A => \Cel_ongoing[18]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_3[0]\, Y => I_123); - - un1_Cel_ongoing_1_I_109 : XOR2 - port map(A => \Cel_ongoing[29]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_13[0]\, Y => I_109); - - \Cel_ongoing[15]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[15]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[15]_net_1\); - - \Cel_ongoing_RNO[16]\ : NOR3C - port map(A => N_478_0, B => N_480, C => I_111, Y => N_435); - - \Chanel_ongoing_RNO[30]\ : XA1C - port map(A => \Chanel_ongoing[30]_net_1\, B => N_327, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n30); - - \Cel_ongoing_RNO[21]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_124, Y => N_440); - - \alu_selected_coeff[4]\ : DFN1E1C0 - port map(D => N_715, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => \alu_sel_coeff[4]\); - - un1_Cel_ongoing_1_I_187 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - \Cel_ongoing[2]\ : DFN1C0 - port map(D => N_227, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[2]_net_1\); - - \IIR_CEL_STATE_i_RNI8T27D[9]\ : OR2A - port map(A => \IIR_CEL_STATE_ns[8]\, B => N_274, Y => N_452); - - \alu_selected_coeff_RNO[3]\ : NOR3B - port map(A => N_478_0, B => N_480_0, C => - alu_selected_coeff_n3_0_i_0, Y => N_714); - - \Chanel_ongoing_RNO_0[9]\ : AX1A - port map(A => N_255, B => \Chanel_ongoing[8]_net_1\, C => - \Chanel_ongoing[9]_net_1\, Y => N_372_i); - - \alu_selected_coeff_0_RNIU2Q27[2]\ : NOR3B - port map(A => N_478_0, B => N_480_0, C => - alu_selected_coeff_n2_0_i_0, Y => N_713); - - \IIR_CEL_STATE_RNO[2]\ : NOR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_523, Y => - N_477); - - sample_in_rot_RNIVMA4_1 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_1); - - alu_sel_input_RNO : NOR2 - port map(A => \IIR_CEL_STATE[6]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => alu_sel_input_1); - - un1_Cel_ongoing_1_I_146 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \Cel_ongoing[2]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12[0]\); - - \Chanel_ongoing_RNO_0[3]\ : XNOR2 - port map(A => N_250, B => \Chanel_ongoing[3]_net_1\, Y => - N_336_i_i_0); - - \Cel_ongoing_RNO_1[0]\ : OR3B - port map(A => N_294, B => N_274, C => - \IIR_CEL_STATE[4]_net_1\, Y => N_457); - - \Chanel_ongoing[30]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n30, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[30]_net_1\); - - un1_Cel_ongoing_1_I_122 : XOR2 - port map(A => \Cel_ongoing[20]_net_1\, B => - \DWACT_ADD_CI_0_g_array_10_1[0]\, Y => I_122_4); - - \Cel_ongoing_RNO[5]\ : NOR3C - port map(A => N_478, B => N_480, C => I_100, Y => - \Cel_ongoing_RNO[5]_net_1\); - - un1_Cel_ongoing_1_I_99 : XOR2 - port map(A => \Cel_ongoing[7]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => I_99); - - un1_Cel_ongoing_1_I_158 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_2[0]\, B => - \Cel_ongoing[14]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_6[0]\); - - \Cel_ongoing[24]\ : DFN1C0 - port map(D => N_443, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[24]_net_1\); - - \IIR_CEL_STATE_i[9]\ : DFN1 - port map(D => N_512_i_0, CLK => lclk_c, Q => - \IIR_CEL_STATE_i[9]_net_1\); - - un1_Cel_ongoing_1_I_103 : XOR2 - port map(A => \Cel_ongoing[9]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_3[0]\, Y => I_103); - - \Chanel_ongoing_RNIHSTH5[24]\ : OR2A - port map(A => \Chanel_ongoing[24]_net_1\, B => N_288, Y => - N_290); - - \Chanel_ongoing[8]\ : DFN1E1C0 - port map(D => N_651_i_0, CLK => lclk_c, CLR => rstn, E => - N_127, Q => \Chanel_ongoing[8]_net_1\); - - \Chanel_ongoing_RNO[13]\ : XA1C - port map(A => \Chanel_ongoing[13]_net_1\, B => N_265, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_224); - - un1_Cel_ongoing_1_I_162 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_3[0]\, B => - \Cel_ongoing[18]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_8[0]\); - - un1_Cel_ongoing_1_I_131 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => - \Cel_ongoing[6]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_2[0]\); - - \Cel_ongoing_RNO[11]\ : NOR3C - port map(A => N_478, B => N_480, C => I_107, Y => - \Cel_ongoing_RNO[11]_net_1\); - - \alu_selected_coeff_RNO_0[4]\ : AX1E - port map(A => N_717, B => \alu_sel_coeff[3]\, C => - \alu_sel_coeff[4]\, Y => N_15_i); - - \IIR_CEL_STATE_i_RNIF6BBE_0[9]\ : OR2B - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0_s_0_0, B => - N_452, Y => un1_alu_sel_input_0_sqmuxa_1_i_0); - - \Chanel_ongoing[3]\ : DFN1E1C0 - port map(D => N_221, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[3]_net_1\); - - \Chanel_ongoing_RNO_0[6]\ : AX1E - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252_i_0, C - => \Chanel_ongoing[6]_net_1\, Y => - Chanel_ongoing_n6_0_i_0_0); - - \Chanel_ongoing_RNI4AP45[22]\ : OR2A - port map(A => \Chanel_ongoing[22]_net_1\, B => - \Chanel_ongoing_RNIV67U4[21]_net_1\, Y => N_286); - - ram_write_RNO : OAI1 - port map(A => N_451_1, B => ram_write_2_0_a2_0, C => - N_480_0, Y => ram_write_2); - - \IIR_CEL_STATE_RNIEAGK6[0]\ : OR2B - port map(A => un1_IIR_CEL_STATE_20_0_0, B => N_480_0, Y => - un1_IIR_CEL_STATE_20); - - \Cel_ongoing[0]\ : DFN1C0 - port map(D => N_206, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[0]_net_1\); - - un1_Cel_ongoing_1_I_102 : XOR2 - port map(A => \Cel_ongoing[8]_net_1\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, Y => I_102); - - \alu_selected_coeff_0_RNIJ954[2]\ : XOR2 - port map(A => S_0, B => \alu_sel_coeff_0[2]\, Y => - alu_selected_coeff_n2_0_i_0); - - sample_out_rot_3 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_3); - - \Chanel_ongoing_RNIDI4D[23]\ : NOR2 - port map(A => \Chanel_ongoing[23]_net_1\, B => - \Chanel_ongoing[24]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_11); - - un1_Cel_ongoing_1_I_117 : XOR2 - port map(A => \Cel_ongoing[17]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_7[0]\, Y => I_117); - - un1_Cel_ongoing_1_I_156 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10[0]\, B => - \Cel_ongoing[12]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_5[0]\); - - un1_Cel_ongoing_1_I_171 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => - \Cel_ongoing[1]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_1[0]\); - - \Chanel_ongoing_RNI8U3D[31]\ : NOR2 - port map(A => \Chanel_ongoing[11]_net_1\, B => - \Chanel_ongoing[31]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_4); - - \Cel_ongoing_RNISFPS5[2]\ : OR2A - port map(A => \Cel_ongoing[2]_net_1\, B => N_325, Y => - N_328); - - \IIR_CEL_STATE[2]\ : DFN1E1 - port map(D => N_477, CLK => lclk_c, E => rstn, Q => - \IIR_CEL_STATE[2]_net_1\); - - \Chanel_ongoing_RNIQQAT3[16]\ : OR2A - port map(A => \Chanel_ongoing[16]_net_1\, B => N_272, Y => - N_273); - - \Chanel_ongoing[13]\ : DFN1E1C0 - port map(D => N_224, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[13]_net_1\); - - \Chanel_ongoing[12]\ : DFN1E1C0 - port map(D => N_216_i, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[12]_net_1\); - - ram_write_RNO_0 : OR2 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[7]_net_1\, Y => ram_write_2_0_a2_0); - - \Chanel_ongoing_RNIJMNV[2]\ : NOR3B - port map(A => \Chanel_ongoing[3]_net_1\, B => - Cel_ongoing_0_sqmuxa_0_a2_0_1, C => - \Chanel_ongoing[2]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_15); - - un1_Cel_ongoing_1_I_197 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2[0]\); - - \Cel_ongoing_RNO_0[0]\ : AO1B - port map(A => N_326, B => \Cel_ongoing_6_i_i_a2_0_0[0]\, C - => \DWACT_ADD_CI_0_partial_sum[0]\, Y => - \Cel_ongoing_6_i_i_0[0]\); - - \Chanel_ongoing_RNIAHBB5[23]\ : OR2A - port map(A => \Chanel_ongoing[23]_net_1\, B => N_286, Y => - N_288); - - sample_out_rot_1 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_1); - - un1_Cel_ongoing_1_I_144 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_13[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_6[0]\); - - un1_Cel_ongoing_1_I_140 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_9[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_4[0]\); - - \Chanel_ongoing_RNIMOPN[2]\ : OR3C - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, C => \Chanel_ongoing[2]_net_1\, - Y => N_250); - - \Chanel_ongoing_RNIDRRF[6]\ : NOR2B - port map(A => \Chanel_ongoing[6]_net_1\, B => - \Chanel_ongoing[5]_net_1\, Y => - Chanel_ongoing_n6_0_i_0_o2_0); - - \Cel_ongoing_RNO[31]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_121, Y => N_450); - - un1_Cel_ongoing_1_I_200 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_7[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_8[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_3[0]\); - - \Chanel_ongoing_RNO[31]\ : XA1C - port map(A => \Chanel_ongoing[31]_net_1\, B => N_335, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n31); - - un1_Cel_ongoing_1_I_133 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \Cel_ongoing[8]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_3[0]\); - - \IIR_CEL_STATE_RNI9GPF[1]\ : OR2 - port map(A => \IIR_CEL_STATE[2]_net_1\, B => - \IIR_CEL_STATE[1]_net_1\, Y => N_567_i_0); - - \Chanel_ongoing_RNI32KK1[23]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_12, B => - Cel_ongoing_0_sqmuxa_0_a2_0_11, C => - Cel_ongoing_0_sqmuxa_0_a2_0_22, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_26); - - \Chanel_ongoing[11]\ : DFN1E1C0 - port map(D => N_462, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[11]_net_1\); - - \Chanel_ongoing_RNI06133[12]\ : OR2A - port map(A => \Chanel_ongoing[12]_net_1\, B => N_264, Y => - N_265); - - un1_Cel_ongoing_1_I_212 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_9[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_10[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_4[0]\); - - \IIR_CEL_STATE[4]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[3]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[4]_net_1\); - - \alu_selected_coeff_RNO[1]\ : NOR3C - port map(A => N_478, B => N_480, C => S_36, Y => N_712); - - \Cel_ongoing_RNI8ROSC[2]\ : OR2A - port map(A => N_796_i, B => N_328, Y => N_523); - - \Cel_ongoing_RNIF326[5]\ : NOR2 - port map(A => \Cel_ongoing[5]_net_1\, B => - \Cel_ongoing[6]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_2[1]\); - - un1_Cel_ongoing_1_I_132 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10_1[0]\, B => - \Cel_ongoing[20]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_9[0]\); - - \Chanel_ongoing_RNO[20]\ : XA1C - port map(A => \Chanel_ongoing[20]_net_1\, B => N_278, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n20); - - \Chanel_ongoing[20]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n20, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[20]_net_1\); - - \IIR_CEL_STATE_i_RNIV1AA[9]\ : OR3 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay_1, C => \IIR_CEL_STATE[4]_net_1\, Y => - N_453); - - \IIR_CEL_STATE_i_RNIF6BBE[9]\ : OR2B - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0_s_0_0, B => - N_452, Y => un1_alu_sel_input_0_sqmuxa_1_i_0_0); - - \IIR_CEL_STATE_i_RNI1V4A[9]\ : OR2A - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => N_451_1); - - GND_i : GND - port map(Y => \GND\); - - \Chanel_ongoing[27]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n27, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[27]_net_1\); - - \Cel_ongoing_RNO[25]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_125, Y => N_444); - - \Cel_ongoing_RNI4OF62[7]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_18[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_17[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_23[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_27[1]\); - - \Chanel_ongoing_RNO_0[7]\ : AX1E - port map(A => N_252_i_0, B => Chanel_ongoing_n6_0_i_0_o2_0, - C => \Chanel_ongoing[7]_net_1\, Y => - Chanel_ongoing_n7_0_i_0_0); - - \Cel_ongoing_RNISFPS5_0[2]\ : OR2 - port map(A => N_325, B => \Cel_ongoing[2]_net_1\, Y => - N_332); - - \Chanel_ongoing_RNIH25D[25]\ : NOR2 - port map(A => \Chanel_ongoing[25]_net_1\, B => - \Chanel_ongoing[26]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_12); - - un1_Cel_ongoing_1_I_154 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_4[0]\, B => - \DWACT_ADD_CI_0_pog_array_3_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_9[0]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - raddr_add1_RNO_0 : NOR3 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay_1, C => \IIR_CEL_STATE[3]_net_1\, Y => - N_737); - - \IIR_CEL_STATE_i_RNIV76I[9]\ : OAI1 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay_1, C => N_294, Y => un1_IIR_CEL_STATE_18); - - \Chanel_ongoing_RNO_0[12]\ : XOR2 - port map(A => \Chanel_ongoing[12]_net_1\, B => N_264, Y => - \Chanel_ongoing_RNO_0[12]_net_1\); - - sample_out_rot_0 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_0); - - \Chanel_ongoing_RNIGCKO1[31]\ : NOR3C - port map(A => N_479, B => Cel_ongoing_0_sqmuxa_0_a2_0_4, C - => Cel_ongoing_0_sqmuxa_0_a2_0_18, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_24); - - \IIR_CEL_STATE_RNIBOPF[0]\ : NOR2 - port map(A => \IIR_CEL_STATE[0]_net_1\, B => - \IIR_CEL_STATE[5]_net_1\, Y => un1_IIR_CEL_STATE_20_0_0); - - \IIR_CEL_STATE[5]\ : DFN1E1 - port map(D => N_204, CLK => lclk_c, E => rstn, Q => - \IIR_CEL_STATE[5]_net_1\); - - \Cel_ongoing_RNISU7A[9]\ : NOR2 - port map(A => \Cel_ongoing[9]_net_1\, B => - \Cel_ongoing[10]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_4[1]\); - - un1_Cel_ongoing_1_I_172 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - \Cel_ongoing[25]\ : DFN1C0 - port map(D => N_444, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[25]_net_1\); - - ram_write_RNI8DD3 : INV - port map(A => ram_write_net_1, Y => ram_write_i); - - \IIR_CEL_STATE_RNO[5]\ : AO1 - port map(A => N_328, B => \IIR_CEL_STATE[4]_net_1\, C => - N_353, Y => N_204); - - \IIR_CEL_STATE_RNIKNICD[2]\ : AO1 - port map(A => N_523, B => \IIR_CEL_STATE[4]_net_1\, C => - \IIR_CEL_STATE[2]_net_1\, Y => un1_IIR_CEL_STATE_24); - - \Chanel_ongoing[18]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n18, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[18]_net_1\); - - \Chanel_ongoing_RNI2V2V5[26]\ : OR2B - port map(A => N_291, B => \Chanel_ongoing[26]_net_1\, Y => - N_292); - - \Cel_ongoing_RNO_0[2]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_120, Y => N_465); - - \Chanel_ongoing[16]\ : DFN1E1C0 - port map(D => N_232, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[16]_net_1\); - - \alu_selected_coeff[3]\ : DFN1E1C0 - port map(D => N_714, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => \alu_sel_coeff[3]\); - - un1_Cel_ongoing_1_I_127 : XOR2 - port map(A => \Cel_ongoing[23]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_10[0]\, Y => I_127); - - \Cel_ongoing_RNO[15]\ : NOR3C - port map(A => N_478, B => N_480, C => I_118, Y => - \Cel_ongoing_RNO[15]_net_1\); - - \alu_ctrl[0]\ : DFN1E0C0 - port map(D => N_568_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(0)); - - \Chanel_ongoing_RNI5DJ93[13]\ : NOR2A - port map(A => \Chanel_ongoing[13]_net_1\, B => N_265, Y => - N_270); - - un1_Cel_ongoing_1_I_188 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_5[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_6[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_2[0]\); - - raddr_add1_RNO_1 : NOR3A - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - \IIR_CEL_STATE[3]_net_1\, C => N_289, Y => N_735); - - un1_Cel_ongoing_1_I_1 : AND2 - port map(A => \Cel_ongoing[0]_net_1\, B => - \IIR_CEL_STATE_RNI87UP_1[4]_net_1\, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - \Chanel_ongoing[14]\ : DFN1E1C0 - port map(D => N_724, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[14]_net_1\); - - \alu_ctrl[2]\ : DFN1E0C0 - port map(D => \IIR_CEL_STATE_i_i[9]\, CLK => lclk_c, CLR - => rstn, E => \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(2)); - - \Chanel_ongoing_RNO[10]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0, B => - N_373_i, Y => N_461); - - \ram_sel_Wdata[1]\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_20, CLK => lclk_c, CLR => - rstn, E => \IIR_CEL_STATE[8]_net_1\, Q => - ram_sel_Wdata(1)); - - \IIR_CEL_STATE_RNI87UP_1[4]\ : OR2 - port map(A => N_326, B => \IIR_CEL_STATE[4]_net_1\, Y => - \IIR_CEL_STATE_RNI87UP_1[4]_net_1\); - - \Cel_ongoing_RNO[4]\ : NOR3C - port map(A => N_478, B => N_480, C => I_119, Y => - \Cel_ongoing_RNO[4]_net_1\); - - \Cel_ongoing_RNIDUKP1[23]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_12[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_11[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_22[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_26[1]\); - - un1_Cel_ongoing_1_I_107 : XOR2 - port map(A => \Cel_ongoing[11]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_4[0]\, Y => I_107); - - \IIR_CEL_STATE_RNIIKQF[5]\ : NOR2 - port map(A => \IIR_CEL_STATE[7]_net_1\, B => - \IIR_CEL_STATE[5]_net_1\, Y => N_289); - - VCC_i : VCC - port map(Y => \VCC\); - - \IIR_CEL_STATE_RNI78PF[1]\ : NOR2 - port map(A => \IIR_CEL_STATE[1]_net_1\, B => - \IIR_CEL_STATE[0]_net_1\, Y => N_294); - - un1_Cel_ongoing_1_I_211 : AND2 - port map(A => \Cel_ongoing[28]_net_1\, B => - \Cel_ongoing[29]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_13[0]\); - - \Chanel_ongoing_RNO_0[11]\ : AX1E - port map(A => \Chanel_ongoing[10]_net_1\, B => N_257, C => - \Chanel_ongoing[11]_net_1\, Y => N_374_i); - - \Cel_ongoing[4]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[4]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[4]_net_1\); - - \IIR_CEL_STATE_RNIFTL4D[4]\ : NOR2 - port map(A => N_796_i, B => N_480_0, Y => - \IIR_CEL_STATE_ns[8]\); - - un1_Cel_ongoing_1_I_186 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_4[0]\); - - \Chanel_ongoing_RNO[21]\ : XA1C - port map(A => \Chanel_ongoing[21]_net_1\, B => N_279, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n21); - - \Chanel_ongoing_RNO[29]\ : XA1C - port map(A => \Chanel_ongoing[29]_net_1\, B => N_295, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n29); - - \IIR_CEL_STATE_RNIGCQF[2]\ : OR2 - port map(A => \IIR_CEL_STATE[8]_net_1\, B => - \IIR_CEL_STATE[2]_net_1\, Y => N_353); - - \Chanel_ongoing_RNIN8BF2[9]\ : NOR3B - port map(A => \Chanel_ongoing[8]_net_1\, B => - \Chanel_ongoing[9]_net_1\, C => N_255, Y => N_257); - - \IIR_CEL_STATE_i_RNI79841[9]\ : OA1 - port map(A => N_294, B => N_451_1, C => N_453, Y => - un1_alu_sel_input_0_sqmuxa_1_i_0_s_0_0); - - \alu_ctrl[1]\ : DFN1E0C0 - port map(D => N_569, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(1)); - - sample_out_val : DFN1E0C0 - port map(D => \IIR_CEL_STATE[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => N_353, Q => sample_out_val_s); - - \alu_selected_coeff_0_RNIJ954_0[2]\ : NOR2A - port map(A => \alu_sel_coeff_0[2]\, B => S_0, Y => N_717); - - raddr_add1_RNO_3 : NOR2A - port map(A => \IIR_CEL_STATE[3]_net_1\, B => N_274, Y => - raddr_add1_2_i_a2_0_0); - - \Chanel_ongoing[31]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n31, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[31]_net_1\); - - un1_Cel_ongoing_1_I_118 : XOR2 - port map(A => \Cel_ongoing[15]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_6[0]\, Y => I_118); - - un1_Cel_ongoing_1_I_203 : AND2 - port map(A => \Cel_ongoing[20]_net_1\, B => - \Cel_ongoing[21]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_9[0]\); - - sample_out_rot_2 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_2); - - \Chanel_ongoing_RNIS2FS2[11]\ : OR3C - port map(A => \Chanel_ongoing[10]_net_1\, B => N_257, C => - \Chanel_ongoing[11]_net_1\, Y => N_264); - - un1_Cel_ongoing_1_I_202 : AND2 - port map(A => \Cel_ongoing[26]_net_1\, B => - \Cel_ongoing[27]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_12[0]\); - - un1_Cel_ongoing_1_I_198 : AND2 - port map(A => \Cel_ongoing[24]_net_1\, B => - \Cel_ongoing[25]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_11[0]\); - - un1_Cel_ongoing_1_I_151 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10_2[0]\, B => - \Cel_ongoing[28]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_13[0]\); - - \Chanel_ongoing_RNINH8C6[28]\ : OR2A - port map(A => \Chanel_ongoing[28]_net_1\, B => N_293, Y => - N_295); - - \waddr_previous[1]\ : DFN1E0C0 - port map(D => N_729, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => waddr_previous(1)); - - un1_Cel_ongoing_1_I_143 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_3[0]\); - - sample_in_rot_RNIVMA4_2 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_2); - - \Cel_ongoing_RNIFIAG[7]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_4[1]\, B => - \Cel_ongoing[8]_net_1\, C => \Cel_ongoing[7]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_17[1]\); - - \IIR_CEL_STATE_RNI3IM46[4]\ : OR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_328, Y => - N_480); - - raddr_add1_RNO : NOR3 - port map(A => N_737, B => N_735, C => N_736, Y => - \raddr_add1_RNO\); - - \Chanel_ongoing_RNIDKBU[7]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_3, B => - \Chanel_ongoing[8]_net_1\, C => \Chanel_ongoing[7]_net_1\, - Y => Cel_ongoing_0_sqmuxa_0_a2_0_16); - - \Cel_ongoing_RNIBJ16[3]\ : NOR2 - port map(A => \Cel_ongoing[3]_net_1\, B => - \Cel_ongoing[4]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_1[1]\); - - \alu_selected_coeff_0_RNI88QV6[0]\ : NOR3B - port map(A => N_478, B => N_480, C => \alu_sel_coeff_0[0]\, - Y => alu_selected_coeff_n0); - - \Chanel_ongoing_RNIF25D[15]\ : NOR2 - port map(A => \Chanel_ongoing[15]_net_1\, B => - \Chanel_ongoing[16]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_7); - - \Chanel_ongoing_RNINS8Q[20]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_10, B => - \Chanel_ongoing[20]_net_1\, C => - \Chanel_ongoing[19]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_20); - - un1_Cel_ongoing_1_I_116 : XOR2 - port map(A => \Cel_ongoing[28]_net_1\, B => - \DWACT_ADD_CI_0_g_array_10_2[0]\, Y => I_116); - - \IIR_CEL_STATE_i_RNI4P117[9]\ : OR3B - port map(A => N_478, B => N_480, C => N_274, Y => N_127_0); - - \IIR_CEL_STATE[7]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[6]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[7]_net_1\); - - \Cel_ongoing_RNIESPS[11]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_6[1]\, B => - \Cel_ongoing[12]_net_1\, C => \Cel_ongoing[11]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_18[1]\); - - \Cel_ongoing_RNI9UCE[13]\ : NOR2 - port map(A => \Cel_ongoing[13]_net_1\, B => - \Cel_ongoing[14]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_6[1]\); - - \Cel_ongoing[19]\ : DFN1C0 - port map(D => N_438, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[19]_net_1\); - - un1_Cel_ongoing_1_I_142 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_9[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_11[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_5[0]\); - - \Chanel_ongoing_RNO[11]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0, B => - N_374_i, Y => N_462); - - \Chanel_ongoing_RNO[24]\ : XA1C - port map(A => \Chanel_ongoing[24]_net_1\, B => N_288, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n24); - - \Chanel_ongoing_RNO[19]\ : XA1C - port map(A => \Chanel_ongoing[19]_net_1\, B => N_276, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n19); - - un1_Cel_ongoing_1_I_196 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_2_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_3_1[0]\); - - un1_Cel_ongoing_1_I_184 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_4[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_10_1[0]\); - - \Chanel_ongoing[15]\ : DFN1E1C0 - port map(D => N_229, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[15]_net_1\); - - \Cel_ongoing[31]\ : DFN1C0 - port map(D => N_450, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[31]_net_1\); - - \alu_selected_coeff_RNO[4]\ : NOR3B - port map(A => N_478, B => N_480, C => N_15_i, Y => N_715); - - \Cel_ongoing[30]\ : DFN1C0 - port map(D => N_449, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[30]_net_1\); - - \Chanel_ongoing_RNIOC3H4[19]\ : OR2A - port map(A => \Chanel_ongoing[19]_net_1\, B => N_276, Y => - N_278); - - \Chanel_ongoing_RNO_0[5]\ : XNOR2 - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252_i_0, Y - => Chanel_ongoing_n5_0_i_0_0); - - \Chanel_ongoing[6]\ : DFN1E1C0 - port map(D => N_22, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[6]_net_1\); - - \Chanel_ongoing_RNIVJL71[4]\ : NOR3B - port map(A => \Chanel_ongoing[3]_net_1\, B => - \Chanel_ongoing[4]_net_1\, C => N_250, Y => N_252_i_0); - - \alu_selected_coeff_RNO_0[3]\ : XNOR2 - port map(A => N_717, B => \alu_sel_coeff[3]\, Y => - alu_selected_coeff_n3_0_i_0); - - sample_out_rot : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s); - - \Chanel_ongoing[23]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n23, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[23]_net_1\); - - \Chanel_ongoing[22]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n22, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[22]_net_1\); - - un1_Cel_ongoing_1_I_153 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_6[0]\, B => - \Cel_ongoing[30]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_14[0]\); - - sample_out_rot_4 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_4); - - \Cel_ongoing_RNO[7]\ : NOR3C - port map(A => N_478, B => N_480, C => I_99, Y => - \Cel_ongoing_RNO[7]_net_1\); - - sample_in_rot_RNIVMA4_3 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_3); - - un1_Cel_ongoing_1_I_205 : AND2 - port map(A => \Cel_ongoing[16]_net_1\, B => - \Cel_ongoing[17]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_7[0]\); - - \in_sel_src_RNO[0]\ : MX2 - port map(A => N_334, B => N_332, S => - \IIR_CEL_STATE[5]_net_1\, Y => N_268); - - \waddr_previous[0]\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_22, CLK => lclk_c, CLR => - rstn, E => \IIR_CEL_STATE[8]_net_1\, Q => - waddr_previous(0)); - - \Chanel_ongoing_RNIBI4D[13]\ : NOR2 - port map(A => \Chanel_ongoing[13]_net_1\, B => - \Chanel_ongoing[14]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_6); - - \alu_selected_coeff_0[2]\ : DFN1E1C0 - port map(D => N_713, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => \alu_sel_coeff_0[2]\); - - \Chanel_ongoing[21]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n21, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[21]_net_1\); - - \Cel_ongoing_RNIDI7D[31]\ : NOR3A - port map(A => \Cel_ongoing[0]_net_1\, B => - \Cel_ongoing[1]_net_1\, C => \Cel_ongoing[31]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_15[1]\); - - \Chanel_ongoing_RNI3IT34[17]\ : OR2A - port map(A => \Chanel_ongoing[17]_net_1\, B => N_273, Y => - N_275); - - \alu_selected_coeff_0[0]\ : DFN1E1C0 - port map(D => alu_selected_coeff_n0, CLK => lclk_c, CLR => - rstn, E => alu_selected_coeffe, Q => \alu_sel_coeff_0[0]\); - - \Chanel_ongoing_RNIJI5D[17]\ : NOR2 - port map(A => \Chanel_ongoing[17]_net_1\, B => - \Chanel_ongoing[18]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_8); - - un1_Cel_ongoing_1_I_128 : XOR2 - port map(A => \Cel_ongoing[19]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_8[0]\, Y => I_128); - - \Cel_ongoing_RNIKADE[29]\ : NOR2 - port map(A => \Cel_ongoing[29]_net_1\, B => - \Cel_ongoing[30]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_14[1]\); - - \Cel_ongoing_RNO[22]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_126, Y => N_441); - - \Chanel_ongoing_RNIGQ4D[30]\ : NOR2 - port map(A => \Chanel_ongoing[29]_net_1\, B => - \Chanel_ongoing[30]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_14); - - un1_Cel_ongoing_1_I_201 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_2_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_3[0]\); - - un1_Cel_ongoing_1_I_114 : XOR2 - port map(A => \Cel_ongoing[1]_net_1\, B => - \DWACT_ADD_CI_0_TMP[0]\, Y => I_114); - - un1_Cel_ongoing_1_I_110 : XOR2 - port map(A => \Cel_ongoing[27]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_12[0]\, Y => I_110); - - \Chanel_ongoing_RNO[14]\ : XA1B - port map(A => \Chanel_ongoing[14]_net_1\, B => N_270, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => N_724); - - un1_Cel_ongoing_1_I_168 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_9[0]\, B => - \Cel_ongoing[24]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_11[0]\); - - \raddr_rst\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_18, CLK => lclk_c, CLR => - rstn, E => N_353, Q => raddr_rst); - - \Cel_ongoing_RNO[3]\ : NOR3C - port map(A => N_478, B => N_480, C => I_113, Y => - \Cel_ongoing_RNO[3]_net_1\); - - \Cel_ongoing_RNIB6DE[21]\ : NOR2 - port map(A => \Cel_ongoing[21]_net_1\, B => - \Cel_ongoing[22]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_10[1]\); - - un1_Cel_ongoing_1_I_115 : XOR2 - port map(A => \Cel_ongoing[30]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_6[0]\, Y => I_115_4); - - \IIR_CEL_STATE_i_RNO[9]\ : MX2B - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => N_180, S => - rstn, Y => N_512_i_0); - - un1_Cel_ongoing_1_I_190 : AND2 - port map(A => \Cel_ongoing[2]_net_1\, B => - \Cel_ongoing[3]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1[0]\); - - \Chanel_ongoing_RNI3HRI6[29]\ : OR2A - port map(A => \Chanel_ongoing[29]_net_1\, B => N_295, Y => - N_327); - - \Cel_ongoing_RNIJ6DE[25]\ : NOR2 - port map(A => \Cel_ongoing[25]_net_1\, B => - \Cel_ongoing[26]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_12[1]\); - - \Chanel_ongoing_RNO[26]\ : XA1B - port map(A => \Chanel_ongoing[26]_net_1\, B => N_291, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n26); - - \Cel_ongoing[18]\ : DFN1C0 - port map(D => N_437, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[18]_net_1\); - - \Chanel_ongoing_RNICRRF[4]\ : NOR2 - port map(A => \Chanel_ongoing[4]_net_1\, B => - \Chanel_ongoing[6]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_1); - - un1_Cel_ongoing_1_I_195 : AND2 - port map(A => \Cel_ongoing[8]_net_1\, B => - \Cel_ongoing[9]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_3[0]\); - - un1_Cel_ongoing_1_I_209 : AND2 - port map(A => \Cel_ongoing[18]_net_1\, B => - \Cel_ongoing[19]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_8[0]\); - - \Chanel_ongoing_RNIPHJK1[20]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_8, B => - Cel_ongoing_0_sqmuxa_0_a2_0_7, C => - Cel_ongoing_0_sqmuxa_0_a2_0_20, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_25); - - un1_Cel_ongoing_1_I_126 : XOR2 - port map(A => \Cel_ongoing[22]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_4[0]\, Y => I_126); - - \Cel_ongoing_RNO[12]\ : NOR3C - port map(A => N_478, B => N_480, C => I_101, Y => - \Cel_ongoing_RNO[12]_net_1\); - - \alu_selected_coeff[0]\ : DFN1E1C0 - port map(D => alu_selected_coeff_n0, CLK => lclk_c, CLR => - rstn, E => alu_selected_coeffe, Q => alu_sel_coeff(0)); - - \Chanel_ongoing[19]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n19, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[19]_net_1\); - - \Cel_ongoing[16]\ : DFN1C0 - port map(D => N_435, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[16]_net_1\); - - \Chanel_ongoing_RNO[0]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0_0, B => - \Chanel_ongoing[0]_net_1\, Y => Chanel_ongoing_n0); - - sample_in_rot_RNIVMA4 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_4); - - GND_i_0 : GND - port map(Y => GND_0); - - \Chanel_ongoing_RNO[25]\ : XA1C - port map(A => \Chanel_ongoing[25]_net_1\, B => N_290, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n25); - - \Chanel_ongoing_RNIR7LN4[20]\ : OR2A - port map(A => \Chanel_ongoing[20]_net_1\, B => N_278, Y => - N_279); - - \Chanel_ongoing_RNI5DAQ[27]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_14, B => - \Chanel_ongoing[28]_net_1\, C => - \Chanel_ongoing[27]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_22); - - \Cel_ongoing_RNIN5KP1[15]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_8[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_7[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_20[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_25[1]\); - - \in_sel_src_RNO[1]\ : MX2B - port map(A => \in_sel_src_8_i_a2_0_a2_0_0[1]\, B => N_289, - S => N_332, Y => N_269); - - \Cel_ongoing_RNO[23]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_127, Y => N_442); - - un1_Cel_ongoing_1_I_166 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_4[0]\, B => - \Cel_ongoing[22]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_10[0]\); - - \Chanel_ongoing[28]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n28, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[28]_net_1\); - - \Chanel_ongoing[26]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n26, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[26]_net_1\); - - \Chanel_ongoing_RNO[4]\ : NOR2 - port map(A => Chanel_ongoing_n4_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_11); - - \Chanel_ongoing[2]\ : DFN1E1C0 - port map(D => N_703, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[2]_net_1\); - - un1_Cel_ongoing_1_I_106 : XOR2 - port map(A => \Cel_ongoing[13]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_5[0]\, Y => I_106); - - \Chanel_ongoing_RNO[6]\ : NOR2 - port map(A => Chanel_ongoing_n6_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_22); - - \Chanel_ongoing_RNI5JKR[12]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_6, B => - \Chanel_ongoing[12]_net_1\, C => - \Chanel_ongoing[5]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_18); - - \IIR_CEL_STATE[6]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[5]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[6]_net_1\); - - \Cel_ongoing[17]\ : DFN1C0 - port map(D => N_436, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[17]_net_1\); - - \Chanel_ongoing[24]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n24, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[24]_net_1\); - - \Cel_ongoing_RNO[2]\ : OR2 - port map(A => N_465, B => \IIR_CEL_STATE_ns[8]\, Y => N_227); - - sample_in_rot_RNIVMA4_0 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_0); - - \Cel_ongoing[11]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[11]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[11]_net_1\); - - \Chanel_ongoing_RNO[2]\ : NOR2A - port map(A => Chanel_ongoing_n2_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_703); - - \Cel_ongoing[10]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[10]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[10]_net_1\); - - un1_Cel_ongoing_1_I_189 : AND2 - port map(A => \Cel_ongoing[6]_net_1\, B => - \Cel_ongoing[7]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_2[0]\); - - sample_in_rot_RNI1NA4 : OR2 - port map(A => sample_val_delay_2, B => sample_in_rotate, Y - => un1_sample_in_rotate); - - un1_Cel_ongoing_1_I_147 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_4[0]\, B => - \Cel_ongoing[16]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_7[0]\); - - \Cel_ongoing_RNO[13]\ : NOR3C - port map(A => N_478, B => N_480, C => I_106, Y => - \Cel_ongoing_RNO[13]_net_1\); - - \Cel_ongoing_RNO[24]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_130, Y => N_443); - - \Chanel_ongoing_RNO[16]\ : XA1C - port map(A => \Chanel_ongoing[16]_net_1\, B => N_272, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => N_232); - - \Cel_ongoing_RNO[20]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_122_4, Y => - N_439); - - \Cel_ongoing[5]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[5]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[5]_net_1\); - - \Cel_ongoing[29]\ : DFN1C0 - port map(D => N_448, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[29]_net_1\); - - \Chanel_ongoing_RNO_0[1]\ : XNOR2 - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, Y => Chanel_ongoing_n1_0_i_0_0); - - \Chanel_ongoing_RNO[27]\ : XA1C - port map(A => \Chanel_ongoing[27]_net_1\, B => N_292, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n27); - - \waddr_previous_RNO[0]\ : AO1B - port map(A => N_328, B => \IIR_CEL_STATE[4]_net_1\, C => - N_334, Y => un1_IIR_CEL_STATE_22); - - \ram_sel_Wdata[0]\ : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => ram_sel_Wdata(0)); - - un1_Cel_ongoing_1_I_138 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_4[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_7[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_3[0]\); - - \Chanel_ongoing[4]\ : DFN1E1C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[4]_net_1\); - - \Cel_ongoing_RNO[0]\ : OR3C - port map(A => \Cel_ongoing_6_i_i_0[0]\, B => N_457, C => - N_454, Y => N_206); - - \Chanel_ongoing_RNO_0[31]\ : OR2A - port map(A => \Chanel_ongoing[30]_net_1\, B => N_327, Y => - N_335); - - \Chanel_ongoing_RNO_0[10]\ : XNOR2 - port map(A => N_257, B => \Chanel_ongoing[10]_net_1\, Y => - N_373_i); - - \Chanel_ongoing_RNO[8]\ : NOR2A - port map(A => Chanel_ongoing_n8_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_651_i_0); - - \Chanel_ongoing_RNO[15]\ : XA1C - port map(A => \Chanel_ongoing[15]_net_1\, B => N_271, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => N_229); - - \Chanel_ongoing[7]\ : DFN1E1C0 - port map(D => N_650, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[7]_net_1\); - - \Cel_ongoing_RNO[8]\ : NOR3C - port map(A => N_478, B => N_480, C => I_102, Y => - \Cel_ongoing_RNO[8]_net_1\); - - un1_Cel_ongoing_1_I_124 : XOR2 - port map(A => \Cel_ongoing[21]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_9[0]\, Y => I_124); - - un1_Cel_ongoing_1_I_120 : XOR2 - port map(A => \Cel_ongoing[2]_net_1\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_120); - - un1_Cel_ongoing_1_I_111 : XOR2 - port map(A => \Cel_ongoing[16]_net_1\, B => - \DWACT_ADD_CI_0_g_array_4[0]\, Y => I_111); - - \Cel_ongoing[13]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[13]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[13]_net_1\); - - \Cel_ongoing[12]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[12]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[12]_net_1\); - - \Chanel_ongoing_RNO[22]\ : XA1C - port map(A => \Chanel_ongoing[22]_net_1\, B => - \Chanel_ongoing_RNIV67U4[21]_net_1\, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n22); - - un1_Cel_ongoing_1_I_125 : XOR2 - port map(A => \Cel_ongoing[25]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_11[0]\, Y => I_125); - - \Chanel_ongoing_RNO[28]\ : XA1C - port map(A => \Chanel_ongoing[28]_net_1\, B => N_293, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n28); - - \Chanel_ongoing_RNIGNNM3[2]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_16, B => - Cel_ongoing_0_sqmuxa_0_a2_0_15, C => - Cel_ongoing_0_sqmuxa_0_a2_0_24, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_27); - - un1_Cel_ongoing_1_I_178 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_10[0]\); - - \Chanel_ongoing_RNIDDGA4[18]\ : OR2A - port map(A => \Chanel_ongoing[18]_net_1\, B => N_275, Y => - N_276); - - \Cel_ongoing_RNO[14]\ : NOR3C - port map(A => N_478, B => N_480, C => I_112, Y => - \Cel_ongoing_RNO[14]_net_1\); - - \Cel_ongoing_RNO[1]\ : NOR3C - port map(A => N_478, B => N_480, C => I_114, Y => - \Cel_ongoing_RNO[1]_net_1\); - - \Cel_ongoing_RNO[10]\ : NOR3C - port map(A => N_478, B => N_480, C => I_105_4, Y => - \Cel_ongoing_RNO[10]_net_1\); - - un1_Cel_ongoing_1_I_191 : AND2 - port map(A => \Cel_ongoing[12]_net_1\, B => - \Cel_ongoing[13]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_5[0]\); - - \IIR_CEL_STATE_RNIR5FE7[2]\ : OR3C - port map(A => N_478, B => N_480, C => N_353, Y => - alu_selected_coeffe); - - \Chanel_ongoing_RNICBVV6[20]\ : OR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_26, B => - Cel_ongoing_0_sqmuxa_0_a2_0_25, C => - Cel_ongoing_0_sqmuxa_0_a2_0_27, Y => N_796_i); - - un1_Cel_ongoing_1_I_136 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_2[0]\); - - \Chanel_ongoing_RNICML56[27]\ : OR2A - port map(A => \Chanel_ongoing[27]_net_1\, B => N_292, Y => - N_293); - - un1_Cel_ongoing_1_I_182 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_9[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_10_2[0]\); - - un1_Cel_ongoing_1_I_71 : XOR2 - port map(A => \Cel_ongoing[0]_net_1\, B => - \IIR_CEL_STATE_RNI87UP_1[4]_net_1\, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - un1_Cel_ongoing_1_I_119 : XOR2 - port map(A => \Cel_ongoing[4]_net_1\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_119); - - un1_Cel_ongoing_1_I_104 : XOR2 - port map(A => \Cel_ongoing[6]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_104); - - un1_Cel_ongoing_1_I_100 : XOR2 - port map(A => \Cel_ongoing[5]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_100); - - \Chanel_ongoing_RNI3RRF[1]\ : NOR2 - port map(A => \Chanel_ongoing[1]_net_1\, B => - \Chanel_ongoing[0]_net_1\, Y => N_479); - - \Cel_ongoing[6]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[6]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[6]_net_1\); - - \IIR_CEL_STATE[3]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[7]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[3]_net_1\); - - \Cel_ongoing_RNO[29]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_109, Y => N_448); - - raddr_add1_RNO_2 : NOR2B - port map(A => raddr_add1_2_i_a2_0_0, B => N_328, Y => N_736); - - \IIR_CEL_STATE_RNIPMNN[6]\ : NOR3 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[6]_net_1\, C => \IIR_CEL_STATE[7]_net_1\, - Y => N_334); - - \Chanel_ongoing_RNIBO5G3[14]\ : OR2B - port map(A => N_270, B => \Chanel_ongoing[14]_net_1\, Y => - N_271); - - \Chanel_ongoing[0]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n0, CLK => lclk_c, CLR => rstn, - E => N_127_0, Q => \Chanel_ongoing[0]_net_1\); - - \Cel_ongoing_RNO[6]\ : NOR3C - port map(A => N_478, B => N_480, C => I_104, Y => - \Cel_ongoing_RNO[6]_net_1\); - - un1_Cel_ongoing_1_I_206 : AND2 - port map(A => \Cel_ongoing[14]_net_1\, B => - \Cel_ongoing[15]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_6[0]\); - - un1_Cel_ongoing_1_I_105 : XOR2 - port map(A => \Cel_ongoing[10]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_1[0]\, Y => I_105_4); - - \Cel_ongoing[14]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[14]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[14]_net_1\); - - \Cel_ongoing_RNIHUCE[17]\ : NOR2 - port map(A => \Cel_ongoing[17]_net_1\, B => - \Cel_ongoing[18]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_8[1]\); - - \Cel_ongoing[9]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[9]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[9]_net_1\); - - sample_in_rot : DFN1E0C0 - port map(D => sample_in_rot_2, CLK => lclk_c, CLR => rstn, - E => N_353, Q => sample_in_rotate); - - un1_Cel_ongoing_1_I_199 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_11[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_12[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_5[0]\); - - \Chanel_ongoing_RNO[17]\ : XA1C - port map(A => \Chanel_ongoing[17]_net_1\, B => N_273, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n17); - - \alu_selected_coeff[1]\ : DFN1E1C0 - port map(D => N_712, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => alu_sel_coeff(1)); - - \Cel_ongoing_RNI79BP[3]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_2[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_1[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_15[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_23[1]\); - - \Cel_ongoing[8]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[8]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[8]_net_1\); - - \IIR_CEL_STATE[8]\ : DFN1E1 - port map(D => N_274, CLK => lclk_c, E => rstn, Q => - \IIR_CEL_STATE[8]_net_1\); - - \Cel_ongoing_RNIDUCE[15]\ : NOR2 - port map(A => \Cel_ongoing[15]_net_1\, B => - \Cel_ongoing[16]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_7[1]\); - - \raddr_add1\ : DFN1C0 - port map(D => \raddr_add1_RNO\, CLK => lclk_c, CLR => rstn, - Q => raddr_add1); - - \IIR_CEL_STATE[1]\ : DFN1E1 - port map(D => \IIR_CEL_STATE_ns[8]\, CLK => lclk_c, E => - rstn, Q => \IIR_CEL_STATE[1]_net_1\); - - \alu_sel_input\ : DFN1E0C0 - port map(D => alu_sel_input_1, CLK => lclk_c, CLR => rstn, - E => un1_IIR_CEL_STATE_18, Q => alu_sel_input); - - \ram_write\ : DFN1E0C0 - port map(D => ram_write_2, CLK => lclk_c, CLR => rstn, E - => \IIR_CEL_STATE[8]_net_1\, Q => ram_write_net_1); - - \IIR_CEL_STATE_i_RNO_0[9]\ : AO1D - port map(A => sample_val_delay_1, B => - \IIR_CEL_STATE_i[9]_net_1\, C => \IIR_CEL_STATE[0]_net_1\, - Y => N_180); - - \Chanel_ongoing[10]\ : DFN1E1C0 - port map(D => N_461, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[10]_net_1\); - - \in_sel_src[1]\ : DFN1E0C0 - port map(D => N_269, CLK => lclk_c, CLR => rstn, E => - un1_IIR_CEL_STATE_24, Q => in_sel_src(1)); - - un1_Cel_ongoing_1_I_204 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_1[0]\); - - un1_Cel_ongoing_1_I_113 : XOR2 - port map(A => \Cel_ongoing[3]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_113); - - \Chanel_ongoing[17]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n17, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[17]_net_1\); - - \IIR_CEL_STATE_RNI87UP[4]\ : OR2A - port map(A => N_326, B => \IIR_CEL_STATE[4]_net_1\, Y => - N_478); - - \Cel_ongoing[7]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[7]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[7]_net_1\); - - \Cel_ongoing_RNO[30]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_115_4, Y => - N_449); - - \Cel_ongoing[28]\ : DFN1C0 - port map(D => N_447, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[28]_net_1\); - - \Chanel_ongoing_RNO[12]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0_0, B => - \Chanel_ongoing_RNO_0[12]_net_1\, Y => N_216_i); - - \Chanel_ongoing[25]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n25, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[25]_net_1\); - - \Cel_ongoing_RNO[19]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_128, Y => N_438); - - \Cel_ongoing_RNIBHQS[27]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_14[1]\, B => - \Cel_ongoing[28]_net_1\, C => \Cel_ongoing[27]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_22[1]\); - - \Cel_ongoing_RNO[28]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_116, Y => N_447); - - \Cel_ongoing_RNIF6DE[23]\ : NOR2 - port map(A => \Cel_ongoing[23]_net_1\, B => - \Cel_ongoing[24]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_11[1]\); - - \IIR_CEL_STATE_i_RNIPVC2[9]\ : NOR2A - port map(A => sample_val_delay_2, B => - \IIR_CEL_STATE_i[9]_net_1\, Y => N_274); - - \Chanel_ongoing_RNO[18]\ : XA1C - port map(A => \Chanel_ongoing[18]_net_1\, B => N_275, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n18); - - \Chanel_ongoing_RNIPBGO5[25]\ : NOR2A - port map(A => \Chanel_ongoing[25]_net_1\, B => N_290, Y => - N_291); - - un1_Cel_ongoing_1_I_193 : AND2 - port map(A => \Cel_ongoing[4]_net_1\, B => - \Cel_ongoing[5]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - \Cel_ongoing_RNIP8QS[19]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_10[1]\, B => - \Cel_ongoing[20]_net_1\, C => \Cel_ongoing[19]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_20[1]\); - - \Chanel_ongoing_RNO[1]\ : NOR2 - port map(A => Chanel_ongoing_n1_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_18); - - \Chanel_ongoing_RNII7OM3[15]\ : OR2A - port map(A => \Chanel_ongoing[15]_net_1\, B => N_271, Y => - N_272); - - \Cel_ongoing[26]\ : DFN1C0 - port map(D => N_445, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[26]_net_1\); - - un1_Cel_ongoing_1_I_112 : XOR2 - port map(A => \Cel_ongoing[14]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_2[0]\, Y => I_112); - - un1_Cel_ongoing_1_I_207 : AND2 - port map(A => \Cel_ongoing[10]_net_1\, B => - \Cel_ongoing[11]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_4[0]\); - - \Chanel_ongoing_RNISOFE[9]\ : NOR2 - port map(A => \Chanel_ongoing[9]_net_1\, B => - \Chanel_ongoing[10]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_3); - - \Chanel_ongoing[9]\ : DFN1E1C0 - port map(D => N_460, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[9]_net_1\); - - \Chanel_ongoing_RNO[3]\ : AO1A - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0, B => - N_336_i_i_0, C => \IIR_CEL_STATE_ns[8]\, Y => N_221); - - \Chanel_ongoing_RNO[5]\ : NOR2 - port map(A => Chanel_ongoing_n5_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_20); - - un1_Cel_ongoing_1_I_130 : XOR2 - port map(A => \Cel_ongoing[24]_net_1\, B => - \DWACT_ADD_CI_0_g_array_9[0]\, Y => I_130); - - \Chanel_ongoing_RNI924D[21]\ : NOR2 - port map(A => \Chanel_ongoing[21]_net_1\, B => - \Chanel_ongoing[22]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_10); - - \alu_ctrl_RNO[1]\ : OR2 - port map(A => \IIR_CEL_STATE[8]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => N_569); - - \Cel_ongoing[3]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[3]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[3]_net_1\); - - \Chanel_ongoing_RNO_0[2]\ : AX1C - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, C => \Chanel_ongoing[2]_net_1\, - Y => Chanel_ongoing_n2_0_i_0_0); - - \Chanel_ongoing_RNO[9]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0, B => - N_372_i, Y => N_460); - - un1_Cel_ongoing_1_I_121 : XOR2 - port map(A => \Cel_ongoing[31]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_14[0]\, Y => I_121); - - \Cel_ongoing_RNO[18]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_123, Y => N_437); - - un1_Cel_ongoing_1_I_135 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_1[0]\, B => - \Cel_ongoing[10]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_4[0]\); - - \IIR_CEL_STATE[0]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[1]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[0]_net_1\); - - \Cel_ongoing[27]\ : DFN1C0 - port map(D => N_446, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[27]_net_1\); - - \alu_selected_coeff[2]\ : DFN1E1C0 - port map(D => N_713, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => alu_sel_coeff(2)); - - \alu_ctrl_RNO[2]\ : INV - port map(A => \IIR_CEL_STATE_i[9]_net_1\, Y => - \IIR_CEL_STATE_i_i[9]\); - - \Chanel_ongoing_RNI4DFV1[7]\ : OR3C - port map(A => N_252_i_0, B => Chanel_ongoing_n6_0_i_0_o2_0, - C => \Chanel_ongoing[7]_net_1\, Y => N_255); - - \Cel_ongoing[21]\ : DFN1C0 - port map(D => N_440, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[21]_net_1\); - - \Cel_ongoing_RNO_2[0]\ : OR2 - port map(A => un1_IIR_CEL_STATE_18, B => N_480_0, Y => - N_454); - - \Cel_ongoing_RNO[27]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_110, Y => N_446); - - \Cel_ongoing[20]\ : DFN1C0 - port map(D => N_439, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[20]_net_1\); - - un1_Cel_ongoing_1_I_210 : AND2 - port map(A => \Cel_ongoing[22]_net_1\, B => - \Cel_ongoing[23]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_10[0]\); - - \Chanel_ongoing_RNO_0[8]\ : XNOR2 - port map(A => \Chanel_ongoing[8]_net_1\, B => N_255, Y => - Chanel_ongoing_n8_0_i_0_0); - - \Cel_ongoing[1]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[1]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[1]_net_1\); - - un1_Cel_ongoing_1_I_174 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_1[0]\); - - un1_Cel_ongoing_1_I_170 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_5[0]\, B => - \Cel_ongoing[26]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_12[0]\); - - \Cel_ongoing_RNO[26]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_129_4, Y => - N_445); - - un1_Cel_ongoing_1_I_129 : XOR2 - port map(A => \Cel_ongoing[26]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_5[0]\, Y => I_129_4); - - \Chanel_ongoing_RNO_0[4]\ : AX1A - port map(A => N_250, B => \Chanel_ongoing[3]_net_1\, C => - \Chanel_ongoing[4]_net_1\, Y => Chanel_ongoing_n4_0_i_0_0); - - \Chanel_ongoing_RNO[7]\ : NOR2 - port map(A => Chanel_ongoing_n7_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_650); - - \waddr_previous_RNO[1]\ : OR2 - port map(A => un1_IIR_CEL_STATE_20, B => N_567_i_0, Y => - N_729); - - \alu_ctrl_RNO[0]\ : OR3A - port map(A => N_289, B => \IIR_CEL_STATE[3]_net_1\, C => - \IIR_CEL_STATE[6]_net_1\, Y => N_568_i_0); - - \Chanel_ongoing_RNO[23]\ : XA1C - port map(A => \Chanel_ongoing[23]_net_1\, B => N_286, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n23); - - \Chanel_ongoing[5]\ : DFN1E1C0 - port map(D => N_20, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[5]_net_1\); - - un1_Cel_ongoing_1_I_101 : XOR2 - port map(A => \Cel_ongoing[12]_net_1\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, Y => I_101); - - \Cel_ongoing_RNO_3[0]\ : OR2B - port map(A => N_328, B => \IIR_CEL_STATE[4]_net_1\, Y => - \Cel_ongoing_6_i_i_a2_0_0[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2 is - - port( sample_filter_v2_out_0 : out std_logic; - sample_filter_v2_out_1 : out std_logic; - sample_filter_v2_out_2 : out std_logic; - sample_filter_v2_out_3 : out std_logic; - sample_filter_v2_out_4 : out std_logic; - sample_filter_v2_out_5 : out std_logic; - sample_filter_v2_out_6 : out std_logic; - sample_filter_v2_out_7 : out std_logic; - sample_filter_v2_out_8 : out std_logic; - sample_filter_v2_out_9 : out std_logic; - sample_filter_v2_out_10 : out std_logic; - sample_filter_v2_out_11 : out std_logic; - sample_filter_v2_out_12 : out std_logic; - sample_filter_v2_out_13 : out std_logic; - sample_filter_v2_out_14 : out std_logic; - sample_filter_v2_out_15 : out std_logic; - sample_filter_v2_out_18 : out std_logic; - sample_filter_v2_out_19 : out std_logic; - sample_filter_v2_out_20 : out std_logic; - sample_filter_v2_out_21 : out std_logic; - sample_filter_v2_out_22 : out std_logic; - sample_filter_v2_out_23 : out std_logic; - sample_filter_v2_out_24 : out std_logic; - sample_filter_v2_out_25 : out std_logic; - sample_filter_v2_out_26 : out std_logic; - sample_filter_v2_out_27 : out std_logic; - sample_filter_v2_out_28 : out std_logic; - sample_filter_v2_out_29 : out std_logic; - sample_filter_v2_out_30 : out std_logic; - sample_filter_v2_out_31 : out std_logic; - sample_filter_v2_out_32 : out std_logic; - sample_filter_v2_out_33 : out std_logic; - sample_filter_v2_out_36 : out std_logic; - sample_filter_v2_out_37 : out std_logic; - sample_filter_v2_out_38 : out std_logic; - sample_filter_v2_out_39 : out std_logic; - sample_filter_v2_out_40 : out std_logic; - sample_filter_v2_out_41 : out std_logic; - sample_filter_v2_out_42 : out std_logic; - sample_filter_v2_out_43 : out std_logic; - sample_filter_v2_out_44 : out std_logic; - sample_filter_v2_out_45 : out std_logic; - sample_filter_v2_out_46 : out std_logic; - sample_filter_v2_out_47 : out std_logic; - sample_filter_v2_out_48 : out std_logic; - sample_filter_v2_out_49 : out std_logic; - sample_filter_v2_out_50 : out std_logic; - sample_filter_v2_out_51 : out std_logic; - sample_filter_v2_out_54 : out std_logic; - sample_filter_v2_out_55 : out std_logic; - sample_filter_v2_out_56 : out std_logic; - sample_filter_v2_out_57 : out std_logic; - sample_filter_v2_out_58 : out std_logic; - sample_filter_v2_out_59 : out std_logic; - sample_filter_v2_out_60 : out std_logic; - sample_filter_v2_out_61 : out std_logic; - sample_filter_v2_out_62 : out std_logic; - sample_filter_v2_out_63 : out std_logic; - sample_filter_v2_out_64 : out std_logic; - sample_filter_v2_out_65 : out std_logic; - sample_filter_v2_out_66 : out std_logic; - sample_filter_v2_out_67 : out std_logic; - sample_filter_v2_out_68 : out std_logic; - sample_filter_v2_out_69 : out std_logic; - sample_filter_v2_out_90 : out std_logic; - sample_filter_v2_out_91 : out std_logic; - sample_filter_v2_out_92 : out std_logic; - sample_filter_v2_out_93 : out std_logic; - sample_filter_v2_out_94 : out std_logic; - sample_filter_v2_out_95 : out std_logic; - sample_filter_v2_out_96 : out std_logic; - sample_filter_v2_out_97 : out std_logic; - sample_filter_v2_out_98 : out std_logic; - sample_filter_v2_out_99 : out std_logic; - sample_filter_v2_out_100 : out std_logic; - sample_filter_v2_out_101 : out std_logic; - sample_filter_v2_out_102 : out std_logic; - sample_filter_v2_out_103 : out std_logic; - sample_filter_v2_out_104 : out std_logic; - sample_filter_v2_out_105 : out std_logic; - sample_filter_v2_out_108 : out std_logic; - sample_filter_v2_out_126 : out std_logic; - sample_filter_v2_out_109 : out std_logic; - sample_filter_v2_out_127 : out std_logic; - sample_filter_v2_out_110 : out std_logic; - sample_filter_v2_out_128 : out std_logic; - sample_filter_v2_out_111 : out std_logic; - sample_filter_v2_out_129 : out std_logic; - sample_filter_v2_out_112 : out std_logic; - sample_filter_v2_out_130 : out std_logic; - sample_filter_v2_out_113 : out std_logic; - sample_filter_v2_out_131 : out std_logic; - sample_filter_v2_out_114 : out std_logic; - sample_filter_v2_out_132 : out std_logic; - sample_filter_v2_out_115 : out std_logic; - sample_filter_v2_out_133 : out std_logic; - sample_filter_v2_out_116 : out std_logic; - sample_filter_v2_out_134 : out std_logic; - sample_filter_v2_out_117 : out std_logic; - sample_filter_v2_out_135 : out std_logic; - sample_filter_v2_out_118 : out std_logic; - sample_filter_v2_out_136 : out std_logic; - sample_filter_v2_out_119 : out std_logic; - sample_filter_v2_out_137 : out std_logic; - sample_filter_v2_out_120 : out std_logic; - sample_filter_v2_out_138 : out std_logic; - sample_filter_v2_out_121 : out std_logic; - sample_filter_v2_out_139 : out std_logic; - sample_filter_v2_out_122 : out std_logic; - sample_filter_v2_out_140 : out std_logic; - sample_filter_v2_out_123 : out std_logic; - sample_filter_v2_out_141 : out std_logic; - sample_4 : in std_logic_vector(15 downto 0); - sample_5 : in std_logic_vector(15 downto 0); - sample_3 : in std_logic_vector(15 downto 0); - sample_2 : in std_logic_vector(15 downto 0); - sample_6 : in std_logic_vector(15 downto 0); - sample_1 : in std_logic_vector(15 downto 0); - sample_0 : in std_logic_vector(15 downto 0); - sample_7 : in std_logic_vector(15 downto 0); - IIR_CEL_CTRLR_v2_VCC : in std_logic; - IIR_CEL_CTRLR_v2_GND : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_filter_v2_out_val : out std_logic; - sample_val_delay : in std_logic; - sample_val_delay_5 : in std_logic; - sample_val_delay_4 : in std_logic; - sample_val_delay_3 : in std_logic; - sample_val_delay_2 : in std_logic; - sample_val_delay_1 : in std_logic; - sample_val_delay_0 : in std_logic - ); - -end IIR_CEL_CTRLR_v2; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2_DATAFLOW - port( alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - S_0 : out std_logic; - S_36 : out std_logic; - waddr_previous : in std_logic_vector(1 downto 0) := (others => 'U'); - sample_0 : in std_logic_vector(14 downto 0) := (others => 'U'); - sample_in_buf : in std_logic_vector(143 downto 129) := (others => 'U'); - ram_sel_Wdata : in std_logic_vector(1 downto 0) := (others => 'U'); - sample_out_s_1 : out std_logic; - sample_out_s_2 : out std_logic; - sample_out_s_0 : out std_logic; - sample_out_s_3 : out std_logic; - sample_out_s_15 : out std_logic; - sample_out_s_14 : out std_logic; - sample_out_s_13 : out std_logic; - sample_out_s_12 : out std_logic; - sample_out_s_11 : out std_logic; - sample_out_s_10 : out std_logic; - sample_out_s_9 : out std_logic; - sample_out_s_8 : out std_logic; - sample_out_s_7 : out std_logic; - sample_out_s_6 : out std_logic; - sample_out_s_5 : out std_logic; - sample_out_s_4 : out std_logic; - sample_in_s_1 : in std_logic_vector(17 to 17) := (others => 'U'); - in_sel_src : in std_logic_vector(1 downto 0) := (others => 'U'); - raddr_rst : in std_logic := 'U'; - raddr_add1 : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_DATAFLOW_GND : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_DATAFLOW_VCC : in std_logic := 'U'; - ram_write_i : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_val_delay_5 : in std_logic := 'U'; - sample_val_delay_1 : in std_logic := 'U'; - sample_val_delay_0 : in std_logic := 'U'; - alu_sel_input : in std_logic := 'U' - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2_CONTROL - port( alu_ctrl : out std_logic_vector(2 downto 0); - ram_sel_Wdata : out std_logic_vector(1 downto 0); - waddr_previous : out std_logic_vector(1 downto 0); - in_sel_src : out std_logic_vector(1 downto 0); - alu_sel_coeff : out std_logic_vector(4 downto 0); - S_36 : in std_logic := 'U'; - S_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : out std_logic; - alu_sel_coeff_0_0 : out std_logic; - sample_out_rot_s : out std_logic; - sample_out_val_s : out std_logic; - raddr_rst : out std_logic; - alu_sel_input : out std_logic; - raddr_add1 : out std_logic; - un1_sample_in_rotate : out std_logic; - sample_val_delay_2 : in std_logic := 'U'; - sample_val_delay_1 : in std_logic := 'U'; - ram_write : out std_logic; - ram_write_i : out std_logic; - un1_sample_in_rotate_0 : out std_logic; - un1_sample_in_rotate_1 : out std_logic; - un1_sample_in_rotate_2 : out std_logic; - un1_sample_in_rotate_3 : out std_logic; - sample_val_delay_0 : in std_logic := 'U'; - un1_sample_in_rotate_4 : out std_logic; - sample_out_rot_s_0 : out std_logic; - sample_out_rot_s_1 : out std_logic; - sample_out_rot_s_2 : out std_logic; - sample_out_rot_s_3 : out std_logic; - sample_out_rot_s_4 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal \sample_in_buf_581[9]\, \sample_in_buf[135]\, - \sample_in_buf_637[135]\, \sample_in_buf[117]\, - \sample_in_buf_645[10]\, \sample_in_buf[136]\, - \sample_in_buf_701[136]\, \sample_in_buf[118]\, - \sample_in_buf_389[6]\, \sample_in_buf[132]\, - \sample_in_buf_445[132]\, \sample_in_buf[114]\, - \sample_in_buf_261[4]\, \sample_in_buf[130]\, - \sample_in_buf_317[130]\, \sample_in_buf[112]\, - \sample_in_buf_517[8]\, \sample_in_buf[134]\, - \sample_in_buf_573[134]\, \sample_in_buf[116]\, - \sample_in_buf_325[5]\, \sample_in_buf[131]\, - \sample_in_buf_381[131]\, \sample_in_buf[113]\, - \sample_in_buf_837[13]\, \sample_in_buf[139]\, - \sample_in_buf_197[3]\, \sample_in_buf[129]\, - \sample_in_buf_253[129]\, \sample_in_buf[111]\, - \sample_in_buf_1029[16]\, \sample_in_buf[142]\, - \sample_in_buf_1085[142]\, \sample_in_buf[124]\, - \sample_in_buf_709[11]\, \sample_in_buf[137]\, - \sample_in_buf_5[0]\, \sample_in_buf[127]\, - \sample_in_buf_61[126]\, \sample_in_buf[109]\, - \sample_in_s_1[17]\, \sample_in_buf_453[7]\, - \sample_in_buf[133]\, \sample_in_buf_509[133]\, - \sample_in_buf[115]\, \sample_in_buf_1021[141]\, - \sample_in_buf[123]\, \sample_in_buf_1013[123]\, - \sample_in_buf[105]\, \sample_in_buf_973[33]\, - \sample_in_buf[15]\, \sample_in_buf_885[121]\, - \sample_in_buf[103]\, \sample_in_buf_53[108]\, - \sample_in_buf[90]\, \sample_in_buf_685[100]\, - \sample_in_buf[82]\, \sample_in_buf_357[77]\, - \sample_in_buf[59]\, \sample_in_buf_229[75]\, - \sample_in_buf[57]\, \sample_in_buf_1109[53]\, - \sample_in_buf[35]\, \sample_in_buf_661[46]\, - \sample_in_buf[28]\, \sample_in_buf_717[29]\, - \sample_in_buf[11]\, \sample_in_buf_13[18]\, - \sample_in_buf[1]\, \sample_in_buf_1005[105]\, - \sample_in_buf[87]\, \sample_in_buf_413[60]\, - \sample_in_buf[42]\, \sample_in_buf_205[21]\, - \sample_in_buf[3]\, \sample_in_buf_693[118]\, - \sample_in_buf[100]\, \sample_in_buf_629[117]\, - \sample_in_buf[99]\, \sample_in_buf_309[112]\, - \sample_in_buf[94]\, \sample_in_buf_621[99]\, - \sample_in_buf[81]\, \sample_in_buf_557[98]\, - \sample_in_buf[80]\, \sample_in_buf_1061[88]\, - \sample_in_buf[70]\, \sample_in_buf_1053[70]\, - \sample_in_buf[52]\, \sample_in_buf_925[68]\, - \sample_in_buf[50]\, \sample_in_buf_541[62]\, - \sample_in_buf[44]\, \sample_in_buf_597[45]\, - \sample_in_buf[27]\, \sample_in_buf_333[23]\, - \sample_in_buf[5]\, \sample_in_buf_269[22]\, - \sample_in_buf[4]\, \sample_in_buf_765[137]\, - \sample_in_buf[119]\, \sample_in_buf_1077[124]\, - \sample_in_buf[106]\, \sample_in_buf_485[79]\, - \sample_in_buf[61]\, \sample_in_buf_733[65]\, - \sample_in_buf[47]\, \sample_in_buf_397[24]\, - \sample_in_buf[6]\, \sample_in_buf_957[140]\, - \sample_in_buf[122]\, \sample_in_buf_429[96]\, - \sample_in_buf[78]\, \sample_in_buf_1037[34]\, - \sample_in_buf[16]\, \sample_in_buf_461[25]\, - \sample_in_buf[7]\, \sample_in_buf_901[14]\, - \sample_in_buf[140]\, \sample_in_buf_1141[125]\, - \sample_in_buf[107]\, \sample_in_buf_677[82]\, - \sample_in_buf[64]\, \sample_in_buf_797[66]\, - \sample_in_buf[48]\, \sample_in_buf_405[42]\, - \sample_in_buf[24]\, \sample_in_buf_525[26]\, - \sample_in_buf[8]\, \sample_in_buf_565[116]\, - \sample_in_buf[98]\, \sample_in_buf_941[104]\, - \sample_in_buf[86]\, \sample_in_buf_301[94]\, - \sample_in_buf[76]\, \sample_in_buf_45[90]\, - \sample_in_buf[72]\, \sample_in_buf_869[85]\, - \sample_in_buf[67]\, \sample_in_buf_989[69]\, - \sample_in_buf[51]\, \sample_in_buf_861[67]\, - \sample_in_buf[49]\, \sample_in_buf_533[44]\, - \sample_in_buf[26]\, \sample_in_buf_589[27]\, - \sample_in_buf[9]\, \sample_in_buf_893[139]\, - \sample_in_buf[121]\, \sample_in_buf_877[103]\, - \sample_in_buf[85]\, \sample_in_buf_37[72]\, - \sample_in_buf[54]\, \sample_in_buf_469[43]\, - \sample_in_buf[25]\, \sample_in_buf_653[28]\, - \sample_in_buf[10]\, \sample_in_buf_949[122]\, - \sample_in_buf[104]\, \sample_in_buf_365[95]\, - \sample_in_buf[77]\, \sample_in_buf_997[87]\, - \sample_in_buf[69]\, \sample_in_buf_613[81]\, - \sample_in_buf[63]\, \sample_in_buf_549[80]\, - \sample_in_buf[62]\, \sample_in_buf_917[50]\, - \sample_in_buf[32]\, \sample_in_buf_789[48]\, - \sample_in_buf[30]\, \sample_in_buf_781[30]\, - \sample_in_buf[12]\, \sample_in_buf_245[111]\, - \sample_in_buf[93]\, \sample_in_buf_237[93]\, - \sample_in_buf[75]\, \sample_in_buf_1125[89]\, - \sample_in_buf[71]\, \sample_in_buf_933[86]\, - \sample_in_buf[68]\, \sample_in_buf_741[83]\, - \sample_in_buf[65]\, \sample_in_buf_981[51]\, - \sample_in_buf[33]\, \sample_in_buf_909[32]\, - \sample_in_buf[14]\, \sample_in_buf_845[31]\, - \sample_in_buf[13]\, \sample_in_buf_829[138]\, - \sample_in_buf[120]\, \sample_in_buf_1069[106]\, - \sample_in_buf[88]\, \sample_in_buf_477[61]\, - \sample_in_buf[43]\, \sample_in_buf_213[39]\, - \sample_in_buf[21]\, \sample_in_buf_1101[35]\, - \sample_in_buf[17]\, \sample_in_buf_773[12]\, - \sample_in_buf[138]\, \sample_in_buf_1133[107]\, - \sample_in_buf[89]\, \sample_in_buf_749[101]\, - \sample_in_buf[83]\, \sample_in_buf_221[57]\, - \sample_in_buf[39]\, \sample_in_buf_21[36]\, - \sample_in_buf[18]\, \sample_in_buf_1149[143]\, - \sample_in_buf[125]\, \sample_in_buf_373[113]\, - \sample_in_buf[95]\, \sample_in_buf_421[78]\, - \sample_in_buf[60]\, \sample_in_buf_725[47]\, - \sample_in_buf[29]\, \sample_in_buf_277[40]\, - \sample_in_buf[22]\, \sample_in_buf_1093[17]\, - \sample_in_buf[143]\, \sample_in_buf_757[119]\, - \sample_in_buf[101]\, \sample_in_buf_1117[71]\, - \sample_in_buf[53]\, \sample_in_buf_605[63]\, - \sample_in_buf[45]\, \sample_in_buf_341[41]\, - \sample_in_buf[23]\, \sample_in_buf_493[97]\, - \sample_in_buf[79]\, \sample_in_buf_805[84]\, - \sample_in_buf[66]\, \sample_in_buf_1045[52]\, - \sample_in_buf[34]\, \sample_in_buf_853[49]\, - \sample_in_buf[31]\, \sample_in_buf_437[114]\, - \sample_in_buf[96]\, \sample_in_buf_813[102]\, - \sample_in_buf[84]\, \sample_in_buf_285[58]\, - \sample_in_buf[40]\, \sample_in_buf_29[54]\, - \sample_in_buf[36]\, \sample_in_buf_965[15]\, - \sample_in_buf[141]\, \sample_in_buf_821[120]\, - \sample_in_buf[102]\, \sample_in_buf_501[115]\, - \sample_in_buf[97]\, \sample_in_buf_293[76]\, - \sample_in_buf[58]\, \sample_in_buf_669[64]\, - \sample_in_buf[46]\, \sample_in_buf_349[59]\, - \sample_in_buf[41]\, \sample_out_val_s2\, - sample_out_val_s, sample_out_rot_s_0, sample_out_rot_s_1, - \sample_filter_v2_out[125]\, \sample_filter_v2_out[124]\, - \sample_filter_v2_out[123]\, \sample_filter_v2_out[122]\, - \sample_filter_v2_out[121]\, \sample_filter_v2_out[120]\, - \sample_filter_v2_out[119]\, sample_out_rot_s_2, - \sample_filter_v2_out[118]\, \sample_filter_v2_out[117]\, - \sample_filter_v2_out[116]\, \sample_filter_v2_out[115]\, - \sample_filter_v2_out[114]\, \sample_filter_v2_out[113]\, - \sample_filter_v2_out[112]\, \sample_filter_v2_out[111]\, - \sample_filter_v2_out[110]\, \sample_filter_v2_out[107]\, - \sample_filter_v2_out[89]\, \sample_filter_v2_out[106]\, - \sample_filter_v2_out[88]\, \sample_filter_v2_out[105]\, - \sample_filter_v2_out[87]\, \sample_filter_v2_out[104]\, - \sample_filter_v2_out[86]\, \sample_filter_v2_out[103]\, - \sample_filter_v2_out[85]\, \sample_filter_v2_out[102]\, - \sample_filter_v2_out[84]\, \sample_filter_v2_out[101]\, - \sample_filter_v2_out[83]\, \sample_filter_v2_out[100]\, - \sample_filter_v2_out[82]\, \sample_filter_v2_out[99]\, - \sample_filter_v2_out[81]\, \sample_filter_v2_out[98]\, - \sample_filter_v2_out[80]\, \sample_filter_v2_out[97]\, - \sample_filter_v2_out[79]\, \sample_filter_v2_out[96]\, - \sample_filter_v2_out[78]\, \sample_filter_v2_out[95]\, - \sample_filter_v2_out[77]\, \sample_filter_v2_out[94]\, - \sample_filter_v2_out[76]\, \sample_filter_v2_out[93]\, - \sample_filter_v2_out[75]\, \sample_filter_v2_out[92]\, - \sample_filter_v2_out[74]\, sample_out_rot_s_3, - \sample_filter_v2_out[71]\, \sample_filter_v2_out[70]\, - \sample_filter_v2_out[69]\, sample_out_rot_s_4, - \sample_filter_v2_out[68]\, \sample_filter_v2_out[67]\, - \sample_filter_v2_out[66]\, \sample_filter_v2_out[65]\, - \sample_filter_v2_out[64]\, \sample_filter_v2_out[63]\, - \sample_filter_v2_out[62]\, \sample_filter_v2_out[61]\, - \sample_filter_v2_out[60]\, \sample_filter_v2_out[59]\, - \sample_filter_v2_out[58]\, \sample_filter_v2_out[57]\, - \sample_filter_v2_out[56]\, \sample_filter_v2_out[53]\, - \sample_filter_v2_out[52]\, \sample_filter_v2_out[51]\, - \sample_filter_v2_out[50]\, \sample_filter_v2_out[49]\, - \sample_filter_v2_out[48]\, \sample_filter_v2_out[47]\, - \sample_filter_v2_out[46]\, \sample_filter_v2_out[45]\, - sample_out_rot_s, \sample_filter_v2_out[44]\, - \sample_filter_v2_out[43]\, \sample_filter_v2_out[42]\, - \sample_filter_v2_out[41]\, \sample_filter_v2_out[40]\, - \sample_filter_v2_out[39]\, \sample_filter_v2_out[38]\, - un1_sample_in_rotate_0, un1_sample_in_rotate_2, - un1_sample_in_rotate_3, un1_sample_in_rotate_4, - un1_sample_in_rotate, un1_sample_in_rotate_1, - \sample_filter_v2_out[35]\, \sample_filter_v2_out[34]\, - \sample_filter_v2_out[33]\, \sample_filter_v2_out[32]\, - \sample_filter_v2_out[31]\, \sample_filter_v2_out[30]\, - \sample_filter_v2_out[29]\, \sample_filter_v2_out[28]\, - \sample_filter_v2_out[27]\, \sample_filter_v2_out[26]\, - \sample_filter_v2_out[25]\, \sample_filter_v2_out[24]\, - \sample_filter_v2_out[23]\, \sample_filter_v2_out[22]\, - \sample_filter_v2_out[21]\, \sample_filter_v2_out[20]\, - \sample_filter_v2_out[17]\, \sample_out_s[0]\, - \sample_filter_v2_out[16]\, \sample_out_s[1]\, - \sample_filter_v2_out[15]\, \sample_out_s[2]\, - \sample_filter_v2_out[14]\, \sample_out_s[3]\, - \sample_filter_v2_out[13]\, \sample_out_s[4]\, - \sample_filter_v2_out[12]\, \sample_out_s[5]\, - \sample_filter_v2_out[11]\, \sample_out_s[6]\, - \sample_filter_v2_out[10]\, \sample_out_s[7]\, - \sample_filter_v2_out[9]\, \sample_out_s[8]\, - \sample_filter_v2_out[8]\, \sample_out_s[9]\, - \sample_filter_v2_out[7]\, \sample_out_s[10]\, - \sample_filter_v2_out[6]\, \sample_out_s[11]\, - \sample_filter_v2_out[5]\, \sample_out_s[12]\, - \sample_filter_v2_out[4]\, \sample_out_s[13]\, - \sample_filter_v2_out[3]\, \sample_out_s[14]\, - \sample_filter_v2_out[2]\, \sample_out_s[15]\, - \alu_ctrl[0]\, \alu_ctrl[1]\, \alu_ctrl[2]\, - \alu_sel_coeff_0[2]\, \alu_sel_coeff_0[0]\, - \alu_sel_coeff[0]\, \alu_sel_coeff[1]\, - \alu_sel_coeff[2]\, \alu_sel_coeff[3]\, - \alu_sel_coeff[4]\, \S[8]\, \S[44]\, \waddr_previous[0]\, - \waddr_previous[1]\, \ram_sel_Wdata[0]\, - \ram_sel_Wdata[1]\, \in_sel_src[0]\, \in_sel_src[1]\, - raddr_rst, raddr_add1, ram_write, ram_write_i, - alu_sel_input, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : IIR_CEL_CTRLR_v2_DATAFLOW - Use entity work.IIR_CEL_CTRLR_v2_DATAFLOW(DEF_ARCH); - for all : IIR_CEL_CTRLR_v2_CONTROL - Use entity work.IIR_CEL_CTRLR_v2_CONTROL(DEF_ARCH); -begin - - sample_filter_v2_out_0 <= \sample_filter_v2_out[2]\; - sample_filter_v2_out_1 <= \sample_filter_v2_out[3]\; - sample_filter_v2_out_2 <= \sample_filter_v2_out[4]\; - sample_filter_v2_out_3 <= \sample_filter_v2_out[5]\; - sample_filter_v2_out_4 <= \sample_filter_v2_out[6]\; - sample_filter_v2_out_5 <= \sample_filter_v2_out[7]\; - sample_filter_v2_out_6 <= \sample_filter_v2_out[8]\; - sample_filter_v2_out_7 <= \sample_filter_v2_out[9]\; - sample_filter_v2_out_8 <= \sample_filter_v2_out[10]\; - sample_filter_v2_out_9 <= \sample_filter_v2_out[11]\; - sample_filter_v2_out_10 <= \sample_filter_v2_out[12]\; - sample_filter_v2_out_11 <= \sample_filter_v2_out[13]\; - sample_filter_v2_out_12 <= \sample_filter_v2_out[14]\; - sample_filter_v2_out_13 <= \sample_filter_v2_out[15]\; - sample_filter_v2_out_14 <= \sample_filter_v2_out[16]\; - sample_filter_v2_out_15 <= \sample_filter_v2_out[17]\; - sample_filter_v2_out_18 <= \sample_filter_v2_out[20]\; - sample_filter_v2_out_19 <= \sample_filter_v2_out[21]\; - sample_filter_v2_out_20 <= \sample_filter_v2_out[22]\; - sample_filter_v2_out_21 <= \sample_filter_v2_out[23]\; - sample_filter_v2_out_22 <= \sample_filter_v2_out[24]\; - sample_filter_v2_out_23 <= \sample_filter_v2_out[25]\; - sample_filter_v2_out_24 <= \sample_filter_v2_out[26]\; - sample_filter_v2_out_25 <= \sample_filter_v2_out[27]\; - sample_filter_v2_out_26 <= \sample_filter_v2_out[28]\; - sample_filter_v2_out_27 <= \sample_filter_v2_out[29]\; - sample_filter_v2_out_28 <= \sample_filter_v2_out[30]\; - sample_filter_v2_out_29 <= \sample_filter_v2_out[31]\; - sample_filter_v2_out_30 <= \sample_filter_v2_out[32]\; - sample_filter_v2_out_31 <= \sample_filter_v2_out[33]\; - sample_filter_v2_out_32 <= \sample_filter_v2_out[34]\; - sample_filter_v2_out_33 <= \sample_filter_v2_out[35]\; - sample_filter_v2_out_36 <= \sample_filter_v2_out[38]\; - sample_filter_v2_out_37 <= \sample_filter_v2_out[39]\; - sample_filter_v2_out_38 <= \sample_filter_v2_out[40]\; - sample_filter_v2_out_39 <= \sample_filter_v2_out[41]\; - sample_filter_v2_out_40 <= \sample_filter_v2_out[42]\; - sample_filter_v2_out_41 <= \sample_filter_v2_out[43]\; - sample_filter_v2_out_42 <= \sample_filter_v2_out[44]\; - sample_filter_v2_out_43 <= \sample_filter_v2_out[45]\; - sample_filter_v2_out_44 <= \sample_filter_v2_out[46]\; - sample_filter_v2_out_45 <= \sample_filter_v2_out[47]\; - sample_filter_v2_out_46 <= \sample_filter_v2_out[48]\; - sample_filter_v2_out_47 <= \sample_filter_v2_out[49]\; - sample_filter_v2_out_48 <= \sample_filter_v2_out[50]\; - sample_filter_v2_out_49 <= \sample_filter_v2_out[51]\; - sample_filter_v2_out_50 <= \sample_filter_v2_out[52]\; - sample_filter_v2_out_51 <= \sample_filter_v2_out[53]\; - sample_filter_v2_out_54 <= \sample_filter_v2_out[56]\; - sample_filter_v2_out_55 <= \sample_filter_v2_out[57]\; - sample_filter_v2_out_56 <= \sample_filter_v2_out[58]\; - sample_filter_v2_out_57 <= \sample_filter_v2_out[59]\; - sample_filter_v2_out_58 <= \sample_filter_v2_out[60]\; - sample_filter_v2_out_59 <= \sample_filter_v2_out[61]\; - sample_filter_v2_out_60 <= \sample_filter_v2_out[62]\; - sample_filter_v2_out_61 <= \sample_filter_v2_out[63]\; - sample_filter_v2_out_62 <= \sample_filter_v2_out[64]\; - sample_filter_v2_out_63 <= \sample_filter_v2_out[65]\; - sample_filter_v2_out_64 <= \sample_filter_v2_out[66]\; - sample_filter_v2_out_65 <= \sample_filter_v2_out[67]\; - sample_filter_v2_out_66 <= \sample_filter_v2_out[68]\; - sample_filter_v2_out_67 <= \sample_filter_v2_out[69]\; - sample_filter_v2_out_68 <= \sample_filter_v2_out[70]\; - sample_filter_v2_out_69 <= \sample_filter_v2_out[71]\; - sample_filter_v2_out_90 <= \sample_filter_v2_out[92]\; - sample_filter_v2_out_91 <= \sample_filter_v2_out[93]\; - sample_filter_v2_out_92 <= \sample_filter_v2_out[94]\; - sample_filter_v2_out_93 <= \sample_filter_v2_out[95]\; - sample_filter_v2_out_94 <= \sample_filter_v2_out[96]\; - sample_filter_v2_out_95 <= \sample_filter_v2_out[97]\; - sample_filter_v2_out_96 <= \sample_filter_v2_out[98]\; - sample_filter_v2_out_97 <= \sample_filter_v2_out[99]\; - sample_filter_v2_out_98 <= \sample_filter_v2_out[100]\; - sample_filter_v2_out_99 <= \sample_filter_v2_out[101]\; - sample_filter_v2_out_100 <= \sample_filter_v2_out[102]\; - sample_filter_v2_out_101 <= \sample_filter_v2_out[103]\; - sample_filter_v2_out_102 <= \sample_filter_v2_out[104]\; - sample_filter_v2_out_103 <= \sample_filter_v2_out[105]\; - sample_filter_v2_out_104 <= \sample_filter_v2_out[106]\; - sample_filter_v2_out_105 <= \sample_filter_v2_out[107]\; - sample_filter_v2_out_108 <= \sample_filter_v2_out[110]\; - sample_filter_v2_out_109 <= \sample_filter_v2_out[111]\; - sample_filter_v2_out_110 <= \sample_filter_v2_out[112]\; - sample_filter_v2_out_111 <= \sample_filter_v2_out[113]\; - sample_filter_v2_out_112 <= \sample_filter_v2_out[114]\; - sample_filter_v2_out_113 <= \sample_filter_v2_out[115]\; - sample_filter_v2_out_114 <= \sample_filter_v2_out[116]\; - sample_filter_v2_out_115 <= \sample_filter_v2_out[117]\; - sample_filter_v2_out_116 <= \sample_filter_v2_out[118]\; - sample_filter_v2_out_117 <= \sample_filter_v2_out[119]\; - sample_filter_v2_out_118 <= \sample_filter_v2_out[120]\; - sample_filter_v2_out_119 <= \sample_filter_v2_out[121]\; - sample_filter_v2_out_120 <= \sample_filter_v2_out[122]\; - sample_filter_v2_out_121 <= \sample_filter_v2_out[123]\; - sample_filter_v2_out_122 <= \sample_filter_v2_out[124]\; - sample_filter_v2_out_123 <= \sample_filter_v2_out[125]\; - - \loop_all_sample.2.loop_all_chanel.6.sample_in_buf[33]\ : - DFN1E1C0 - port map(D => \sample_in_buf_973[33]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[33]\); - - \loop_all_sample.13.loop_all_chanel.7.sample_in_buf[4]\ : - DFN1E1C0 - port map(D => \sample_in_buf_261[4]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[4]\); - - \loop_all_sample.9.loop_all_chanel.4.sample_in_buf_RNO[62]\ : - MX2 - port map(A => \sample_in_buf[44]\, B => sample_4(9), S => - sample_val_delay_3, Y => \sample_in_buf_541[62]\); - - \loop_all_sample.10.loop_all_chanel.2.sample_in_buf_RNO[97]\ : - MX2 - port map(A => \sample_in_buf[79]\, B => sample_2(10), S => - sample_val_delay, Y => \sample_in_buf_493[97]\); - - \chanel_more.all_chanel.2.all_bit.3.sample_out_s2[122]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[104]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[122]\); - - \loop_all_sample.5.loop_all_chanel.4.sample_in_buf_RNO[66]\ : - MX2 - port map(A => \sample_in_buf[48]\, B => sample_4(5), S => - sample_val_delay_3, Y => \sample_in_buf_797[66]\); - - \loop_all_sample.1.loop_all_chanel.6.sample_in_buf[34]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1037[34]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[34]\); - - \chanel_more.all_chanel.3.all_bit.1.sample_out_s2[106]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[88]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[106]\); - - \loop_all_sample.6.loop_all_chanel.1.sample_in_buf_RNO[119]\ : - MX2 - port map(A => \sample_in_buf[101]\, B => sample_1(6), S => - sample_val_delay_5, Y => \sample_in_buf_757[119]\); - - \loop_all_sample.12.loop_all_chanel.4.sample_in_buf_RNO[59]\ : - MX2 - port map(A => \sample_in_buf[41]\, B => sample_4(12), S => - sample_val_delay, Y => \sample_in_buf_349[59]\); - - \chanel_more.all_chanel.1.all_bit.6.sample_out_s2[137]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[119]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_135); - - \chanel_more.all_chanel.7.all_bit.3.sample_out_s2[32]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[14]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[32]\); - - \chanel_more.all_chanel.5.all_bit.10.sample_out_s2[61]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[43]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[61]\); - - \loop_all_sample.6.loop_all_chanel.0.sample_in_buf_RNO[137]\ : - MX2 - port map(A => \sample_in_buf[119]\, B => sample_0(6), S => - sample_val_delay_3, Y => \sample_in_buf_765[137]\); - - \chanel_more.all_chanel.6.all_bit.0.sample_out_s2[53]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[35]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[53]\); - - \chanel_more.all_chanel.4.all_bit.13.sample_out_s2[76]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[58]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[76]\); - - \loop_all_sample.9.loop_all_chanel.0.sample_in_buf_RNO[134]\ : - MX2 - port map(A => \sample_in_buf[116]\, B => sample_0(9), S => - sample_val_delay_0, Y => \sample_in_buf_573[134]\); - - \loop_all_sample.8.loop_all_chanel.2.sample_in_buf[99]\ : - DFN1E1C0 - port map(D => \sample_in_buf_621[99]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[99]\); - - \chanel_more.all_chanel.3.all_bit.11.sample_out_s2[96]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[78]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[96]\); - - \chanel_more.all_chanel.6.all_bit.2.sample_out_s2[51]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[33]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[51]\); - - \loop_all_sample.12.loop_all_chanel.5.sample_in_buf_RNO[41]\ : - MX2 - port map(A => \sample_in_buf[23]\, B => sample_5(12), S => - sample_val_delay, Y => \sample_in_buf_341[41]\); - - \loop_all_sample.1.loop_all_chanel.2.sample_in_buf[106]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1069[106]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[106]\); - - \loop_all_sample.17.loop_all_chanel.7.sample_in_buf_RNO[0]\ : - MX2 - port map(A => \sample_in_buf[127]\, B => sample_7(15), S - => sample_val_delay_1, Y => \sample_in_buf_5[0]\); - - \loop_all_sample.13.loop_all_chanel.5.sample_in_buf[40]\ : - DFN1E1C0 - port map(D => \sample_in_buf_277[40]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[40]\); - - \loop_all_sample.13.loop_all_chanel.0.sample_in_buf_RNO[130]\ : - MX2 - port map(A => \sample_in_buf[112]\, B => sample_0(13), S - => sample_val_delay_0, Y => \sample_in_buf_317[130]\); - - \loop_all_sample.3.loop_all_chanel.4.sample_in_buf_RNO[68]\ : - MX2 - port map(A => \sample_in_buf[50]\, B => sample_4(3), S => - sample_val_delay_3, Y => \sample_in_buf_925[68]\); - - \chanel_more.all_chanel.1.all_bit.3.sample_out_s2[140]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[122]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_138); - - \loop_all_sample.13.loop_all_chanel.2.sample_in_buf_RNO[94]\ : - MX2 - port map(A => \sample_in_buf[76]\, B => sample_2(13), S => - sample_val_delay_4, Y => \sample_in_buf_301[94]\); - - \loop_all_sample.11.loop_all_chanel.3.sample_in_buf_RNO[78]\ : - MX2 - port map(A => \sample_in_buf[60]\, B => sample_3(11), S => - sample_val_delay_5, Y => \sample_in_buf_421[78]\); - - \chanel_more.all_chanel.4.all_bit.1.sample_out_s2[88]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[70]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[88]\); - - \chanel_more.all_chanel.3.all_bit.4.sample_out_s2[103]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[85]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[103]\); - - \loop_all_sample.7.loop_all_chanel.4.sample_in_buf_RNO[64]\ : - MX2 - port map(A => \sample_in_buf[46]\, B => sample_4(7), S => - sample_val_delay, Y => \sample_in_buf_669[64]\); - - \loop_all_sample.5.loop_all_chanel.3.sample_in_buf[84]\ : - DFN1E1C0 - port map(D => \sample_in_buf_805[84]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[84]\); - - \chanel_more.all_chanel.6.all_bit.15.sample_out_s2[38]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[20]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[38]\); - - \loop_all_sample.12.loop_all_chanel.5.sample_in_buf[41]\ : - DFN1E1C0 - port map(D => \sample_in_buf_341[41]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[41]\); - - \chanel_more.all_chanel.5.all_bit.7.sample_out_s2[64]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[46]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[64]\); - - \chanel_more.all_chanel.5.all_bit.6.sample_out_s2[65]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[47]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[65]\); - - \chanel_more.all_chanel.7.all_bit.2.sample_out_s2[33]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[15]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[33]\); - - \loop_all_sample.9.loop_all_chanel.3.sample_in_buf_RNO[80]\ : - MX2 - port map(A => \sample_in_buf[62]\, B => sample_3(9), S => - sample_val_delay_4, Y => \sample_in_buf_549[80]\); - - \loop_all_sample.2.loop_all_chanel.4.sample_in_buf_RNO[69]\ : - MX2 - port map(A => \sample_in_buf[51]\, B => sample_4(2), S => - sample_val_delay_4, Y => \sample_in_buf_989[69]\); - - \loop_all_sample.14.loop_all_chanel.6.sample_in_buf[21]\ : - DFN1E1C0 - port map(D => \sample_in_buf_205[21]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[21]\); - - \loop_all_sample.9.loop_all_chanel.5.sample_in_buf[44]\ : - DFN1E1C0 - port map(D => \sample_in_buf_533[44]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[44]\); - - \loop_all_sample.11.loop_all_chanel.5.sample_in_buf[42]\ : - DFN1E1C0 - port map(D => \sample_in_buf_405[42]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[42]\); - - \loop_all_sample.9.loop_all_chanel.2.sample_in_buf_RNO[98]\ : - MX2 - port map(A => \sample_in_buf[80]\, B => sample_2(9), S => - sample_val_delay_2, Y => \sample_in_buf_557[98]\); - - \loop_all_sample.10.loop_all_chanel.4.sample_in_buf_RNO[61]\ : - MX2 - port map(A => \sample_in_buf[43]\, B => sample_4(10), S => - sample_val_delay_5, Y => \sample_in_buf_477[61]\); - - \chanel_more.all_chanel.1.all_bit.8.sample_out_s2[135]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[117]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_133); - - \loop_all_sample.9.loop_all_chanel.6.sample_in_buf[26]\ : - DFN1E1C0 - port map(D => \sample_in_buf_525[26]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[26]\); - - \chanel_more.all_chanel.1.all_bit.9.sample_out_s2[134]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[116]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_132); - - \loop_all_sample.11.loop_all_chanel.7.sample_in_buf_RNO[6]\ : - MX2 - port map(A => \sample_in_buf[132]\, B => sample_7(11), S - => sample_val_delay_0, Y => \sample_in_buf_389[6]\); - - \loop_all_sample.1.loop_all_chanel.6.sample_in_buf_RNO[34]\ : - MX2 - port map(A => \sample_in_buf[16]\, B => sample_6(1), S => - sample_val_delay_3, Y => \sample_in_buf_1037[34]\); - - \loop_all_sample.3.loop_all_chanel.3.sample_in_buf[86]\ : - DFN1E1C0 - port map(D => \sample_in_buf_933[86]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[86]\); - - \chanel_more.all_chanel.6.all_bit.1.sample_out_s2[52]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[34]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[52]\); - - \chanel_HIGH.6.sample_out_s2[11]\ : DFN1E1C0 - port map(D => \sample_out_s[6]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[11]\); - - \loop_all_sample.11.loop_all_chanel.2.sample_in_buf_RNO[96]\ : - MX2 - port map(A => \sample_in_buf[78]\, B => sample_2(11), S => - sample_val_delay_3, Y => \sample_in_buf_429[96]\); - - \chanel_more.all_chanel.1.all_bit.5.sample_out_s2[138]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[120]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_136); - - \loop_all_sample.2.loop_all_chanel.7.sample_in_buf_RNO[15]\ : - MX2 - port map(A => \sample_in_buf[141]\, B => sample_7(2), S => - sample_val_delay, Y => \sample_in_buf_965[15]\); - - \loop_all_sample.13.loop_all_chanel.2.sample_in_buf[94]\ : - DFN1E1C0 - port map(D => \sample_in_buf_301[94]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[94]\); - - \loop_all_sample.17.loop_all_chanel.1.sample_in_buf[108]\ : - DFN1E1C0 - port map(D => \sample_in_buf_53[108]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[109]\); - - \loop_all_sample.0.loop_all_chanel.6.sample_in_buf_RNO[35]\ : - MX2 - port map(A => \sample_in_buf[17]\, B => sample_6(0), S => - sample_val_delay_5, Y => \sample_in_buf_1101[35]\); - - \loop_all_sample.4.loop_all_chanel.0.sample_in_buf_RNO[139]\ : - MX2 - port map(A => \sample_in_buf[121]\, B => sample_0(4), S => - sample_val_delay_4, Y => \sample_in_buf_893[139]\); - - \loop_all_sample.0.loop_all_chanel.3.sample_in_buf[89]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1125[89]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[89]\); - - \chanel_more.all_chanel.5.all_bit.9.sample_out_s2[62]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[44]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[62]\); - - \loop_all_sample.11.loop_all_chanel.2.sample_in_buf[96]\ : - DFN1E1C0 - port map(D => \sample_in_buf_429[96]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[96]\); - - \loop_all_sample.1.loop_all_chanel.3.sample_in_buf[88]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1061[88]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[88]\); - - \chanel_more.all_chanel.4.all_bit.11.sample_out_s2[78]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[60]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[78]\); - - \chanel_HIGH.15.sample_out_s2[2]\ : DFN1E1C0 - port map(D => \sample_out_s[15]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[2]\); - - \loop_all_sample.0.loop_all_chanel.5.sample_in_buf_RNO[53]\ : - MX2 - port map(A => \sample_in_buf[35]\, B => sample_5(0), S => - sample_val_delay_2, Y => \sample_in_buf_1109[53]\); - - \loop_all_sample.6.loop_all_chanel.4.sample_in_buf[65]\ : - DFN1E1C0 - port map(D => \sample_in_buf_733[65]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[65]\); - - \loop_all_sample.7.loop_all_chanel.7.sample_in_buf_RNO[10]\ : - MX2 - port map(A => \sample_in_buf[136]\, B => sample_7(7), S => - sample_val_delay_0, Y => \sample_in_buf_645[10]\); - - \loop_all_sample.17.loop_all_chanel.4.sample_in_buf[54]\ : - DFN1E1C0 - port map(D => \sample_in_buf_29[54]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[54]\); - - \loop_all_sample.4.loop_all_chanel.1.sample_in_buf_RNO[121]\ : - MX2 - port map(A => \sample_in_buf[103]\, B => sample_1(4), S => - sample_val_delay_2, Y => \sample_in_buf_885[121]\); - - \loop_all_sample.13.loop_all_chanel.6.sample_in_buf[22]\ : - DFN1E1C0 - port map(D => \sample_in_buf_269[22]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[22]\); - - \loop_all_sample.17.loop_all_chanel.2.sample_in_buf_RNO[90]\ : - MX2 - port map(A => \sample_in_buf[72]\, B => sample_2(15), S => - sample_val_delay_4, Y => \sample_in_buf_45[90]\); - - \loop_all_sample.11.loop_all_chanel.6.sample_in_buf_RNO[24]\ : - MX2 - port map(A => \sample_in_buf[6]\, B => sample_6(11), S => - sample_val_delay_3, Y => \sample_in_buf_397[24]\); - - \loop_all_sample.1.loop_all_chanel.7.sample_in_buf_RNO[16]\ : - MX2 - port map(A => \sample_in_buf[142]\, B => sample_7(1), S => - sample_val_delay_1, Y => \sample_in_buf_1029[16]\); - - \loop_all_sample.6.loop_all_chanel.7.sample_in_buf[11]\ : - DFN1E1C0 - port map(D => \sample_in_buf_709[11]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[11]\); - - \chanel_more.all_chanel.6.all_bit.8.sample_out_s2[45]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[27]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[45]\); - - \loop_all_sample.7.loop_all_chanel.0.sample_in_buf_RNO[136]\ : - MX2 - port map(A => \sample_in_buf[118]\, B => sample_0(7), S => - sample_val_delay_0, Y => \sample_in_buf_701[136]\); - - \chanel_more.all_chanel.3.all_bit.10.sample_out_s2[97]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[79]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[97]\); - - \loop_all_sample.4.loop_all_chanel.5.sample_in_buf_RNO[49]\ : - MX2 - port map(A => \sample_in_buf[31]\, B => sample_5(4), S => - sample_val_delay, Y => \sample_in_buf_853[49]\); - - \chanel_more.all_chanel.1.all_bit.13.sample_out_s2[130]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[112]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_128); - - \loop_all_sample.13.loop_all_chanel.5.sample_in_buf_RNO[40]\ : - MX2 - port map(A => \sample_in_buf[22]\, B => sample_5(13), S => - sample_val_delay_5, Y => \sample_in_buf_277[40]\); - - \loop_all_sample.17.loop_all_chanel.3.sample_in_buf[72]\ : - DFN1E1C0 - port map(D => \sample_in_buf_37[72]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[72]\); - - \chanel_more.all_chanel.6.all_bit.12.sample_out_s2[41]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[23]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[41]\); - - \chanel_more.all_chanel.4.all_bit.4.sample_out_s2[85]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[67]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[85]\); - - \loop_all_sample.5.loop_all_chanel.1.sample_in_buf[120]\ : - DFN1E1C0 - port map(D => \sample_in_buf_821[120]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[120]\); - - \loop_all_sample.11.loop_all_chanel.4.sample_in_buf_RNO[60]\ : - MX2 - port map(A => \sample_in_buf[42]\, B => sample_4(11), S => - sample_val_delay_2, Y => \sample_in_buf_413[60]\); - - \loop_all_sample.0.loop_all_chanel.1.sample_in_buf_RNO[125]\ : - MX2 - port map(A => \sample_in_buf[107]\, B => sample_1(0), S => - sample_val_delay_3, Y => \sample_in_buf_1141[125]\); - - \loop_all_sample.7.loop_all_chanel.2.sample_in_buf[100]\ : - DFN1E1C0 - port map(D => \sample_in_buf_685[100]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[100]\); - - \loop_all_sample.9.loop_all_chanel.7.sample_in_buf[8]\ : - DFN1E1C0 - port map(D => \sample_in_buf_517[8]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[8]\); - - \chanel_more.all_chanel.2.all_bit.7.sample_out_s2[118]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[100]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[118]\); - - \chanel_HIGH.9.sample_out_s2[8]\ : DFN1E1C0 - port map(D => \sample_out_s[9]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[8]\); - - \loop_all_sample.6.loop_all_chanel.5.sample_in_buf[47]\ : - DFN1E1C0 - port map(D => \sample_in_buf_725[47]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[47]\); - - \loop_all_sample.13.loop_all_chanel.4.sample_in_buf[58]\ : - DFN1E1C0 - port map(D => \sample_in_buf_285[58]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[58]\); - - \chanel_more.all_chanel.4.all_bit.5.sample_out_s2[84]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[66]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[84]\); - - \loop_all_sample.4.loop_all_chanel.2.sample_in_buf[103]\ : - DFN1E1C0 - port map(D => \sample_in_buf_877[103]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[103]\); - - \loop_all_sample.1.loop_all_chanel.7.sample_in_buf[16]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1029[16]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[16]\); - - \chanel_HIGH.7.sample_out_s2[10]\ : DFN1E1C0 - port map(D => \sample_out_s[7]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[10]\); - - \loop_all_sample.13.loop_all_chanel.7.sample_in_buf_RNO[4]\ : - MX2 - port map(A => \sample_in_buf[130]\, B => sample_7(13), S - => sample_val_delay_0, Y => \sample_in_buf_261[4]\); - - \loop_all_sample.11.loop_all_chanel.7.sample_in_buf[6]\ : - DFN1E1C0 - port map(D => \sample_in_buf_389[6]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[6]\); - - GND_i : GND - port map(Y => \GND\); - - \loop_all_sample.1.loop_all_chanel.3.sample_in_buf_RNO[88]\ : - MX2 - port map(A => \sample_in_buf[70]\, B => sample_3(1), S => - sample_val_delay_2, Y => \sample_in_buf_1061[88]\); - - \loop_all_sample.13.loop_all_chanel.4.sample_in_buf_RNO[58]\ : - MX2 - port map(A => \sample_in_buf[40]\, B => sample_4(13), S => - sample_val_delay, Y => \sample_in_buf_285[58]\); - - \chanel_more.all_chanel.1.all_bit.4.sample_out_s2[139]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[121]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_137); - - \chanel_more.all_chanel.7.all_bit.6.sample_out_s2[29]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[11]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[29]\); - - \loop_all_sample.2.loop_all_chanel.2.sample_in_buf_RNO[105]\ : - MX2 - port map(A => \sample_in_buf[87]\, B => sample_2(2), S => - sample_val_delay_2, Y => \sample_in_buf_1005[105]\); - - \loop_all_sample.10.loop_all_chanel.2.sample_in_buf[97]\ : - DFN1E1C0 - port map(D => \sample_in_buf_493[97]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[97]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \loop_all_sample.2.loop_all_chanel.5.sample_in_buf_RNO[51]\ : - MX2 - port map(A => \sample_in_buf[33]\, B => sample_5(2), S => - sample_val_delay_5, Y => \sample_in_buf_981[51]\); - - \loop_all_sample.17.loop_all_chanel.5.sample_in_buf[36]\ : - DFN1E1C0 - port map(D => \sample_in_buf_21[36]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[36]\); - - \loop_all_sample.17.loop_all_chanel.3.sample_in_buf_RNO[72]\ : - MX2 - port map(A => \sample_in_buf[54]\, B => sample_3(15), S => - sample_val_delay_4, Y => \sample_in_buf_37[72]\); - - \chanel_more.all_chanel.2.all_bit.9.sample_out_s2[116]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[98]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[116]\); - - \loop_all_sample.7.loop_all_chanel.1.sample_in_buf_RNO[118]\ : - MX2 - port map(A => \sample_in_buf[100]\, B => sample_1(7), S => - sample_val_delay_2, Y => \sample_in_buf_693[118]\); - - \chanel_more.all_chanel.2.all_bit.10.sample_out_s2[115]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[97]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[115]\); - - \chanel_more.all_chanel.3.all_bit.6.sample_out_s2[101]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[83]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[101]\); - - \loop_all_sample.9.loop_all_chanel.4.sample_in_buf[62]\ : - DFN1E1C0 - port map(D => \sample_in_buf_541[62]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[62]\); - - \loop_all_sample.14.loop_all_chanel.0.sample_in_buf[129]\ : - DFN1E1C0 - port map(D => \sample_in_buf_253[129]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[129]\); - - \loop_all_sample.7.loop_all_chanel.0.sample_in_buf[136]\ : - DFN1E1C0 - port map(D => \sample_in_buf_701[136]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[136]\); - - \chanel_more.all_chanel.4.all_bit.0.sample_out_s2[89]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[71]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[89]\); - - \loop_all_sample.3.loop_all_chanel.2.sample_in_buf[104]\ : - DFN1E1C0 - port map(D => \sample_in_buf_941[104]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[104]\); - - \loop_all_sample.5.loop_all_chanel.2.sample_in_buf_RNO[102]\ : - MX2 - port map(A => \sample_in_buf[84]\, B => sample_2(5), S => - sample_val_delay, Y => \sample_in_buf_813[102]\); - - \loop_all_sample.4.loop_all_chanel.1.sample_in_buf[121]\ : - DFN1E1C0 - port map(D => \sample_in_buf_885[121]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[121]\); - - \chanel_more.all_chanel.6.all_bit.11.sample_out_s2[42]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[24]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[42]\); - - \loop_all_sample.10.loop_all_chanel.5.sample_in_buf[43]\ : - DFN1E1C0 - port map(D => \sample_in_buf_469[43]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[43]\); - - \chanel_more.all_chanel.5.all_bit.0.sample_out_s2[71]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[53]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[71]\); - - \loop_all_sample.11.loop_all_chanel.0.sample_in_buf_RNO[132]\ : - MX2 - port map(A => \sample_in_buf[114]\, B => sample_0(11), S - => sample_val_delay_0, Y => \sample_in_buf_445[132]\); - - \chanel_more.all_chanel.6.all_bit.6.sample_out_s2[47]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[29]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[47]\); - - \loop_all_sample.12.loop_all_chanel.2.sample_in_buf[95]\ : - DFN1E1C0 - port map(D => \sample_in_buf_365[95]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[95]\); - - \chanel_more.all_chanel.7.all_bit.1.sample_out_s2[34]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[16]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[34]\); - - \loop_all_sample.6.loop_all_chanel.2.sample_in_buf[101]\ : - DFN1E1C0 - port map(D => \sample_in_buf_749[101]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[101]\); - - \loop_all_sample.9.loop_all_chanel.1.sample_in_buf_RNO[116]\ : - MX2 - port map(A => \sample_in_buf[98]\, B => sample_1(9), S => - sample_val_delay_3, Y => \sample_in_buf_565[116]\); - - \loop_all_sample.4.loop_all_chanel.2.sample_in_buf_RNO[103]\ : - MX2 - port map(A => \sample_in_buf[85]\, B => sample_2(4), S => - sample_val_delay_4, Y => \sample_in_buf_877[103]\); - - \loop_all_sample.10.loop_all_chanel.1.sample_in_buf_RNO[115]\ : - MX2 - port map(A => \sample_in_buf[97]\, B => sample_1(10), S => - sample_val_delay, Y => \sample_in_buf_501[115]\); - - \loop_all_sample.5.loop_all_chanel.5.sample_in_buf_RNO[48]\ : - MX2 - port map(A => \sample_in_buf[30]\, B => sample_5(5), S => - sample_val_delay_4, Y => \sample_in_buf_789[48]\); - - \loop_all_sample.3.loop_all_chanel.2.sample_in_buf_RNO[104]\ : - MX2 - port map(A => \sample_in_buf[86]\, B => sample_2(3), S => - sample_val_delay_3, Y => \sample_in_buf_941[104]\); - - \chanel_more.all_chanel.7.all_bit.15.sample_out_s2[20]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[2]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[20]\); - - \loop_all_sample.2.loop_all_chanel.1.sample_in_buf[123]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1013[123]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[123]\); - - \chanel_HIGH.13.sample_out_s2[4]\ : DFN1E1C0 - port map(D => \sample_out_s[13]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[4]\); - - \loop_all_sample.10.loop_all_chanel.6.sample_in_buf[25]\ : - DFN1E1C0 - port map(D => \sample_in_buf_461[25]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[25]\); - - \chanel_more.all_chanel.3.all_bit.13.sample_out_s2[94]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[76]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[94]\); - - \loop_all_sample.3.loop_all_chanel.1.sample_in_buf_RNO[122]\ : - MX2 - port map(A => \sample_in_buf[104]\, B => sample_1(3), S => - sample_val_delay_4, Y => \sample_in_buf_949[122]\); - - \loop_all_sample.2.loop_all_chanel.1.sample_in_buf_RNO[123]\ : - MX2 - port map(A => \sample_in_buf[105]\, B => sample_1(2), S => - sample_val_delay_2, Y => \sample_in_buf_1013[123]\); - - \loop_all_sample.3.loop_all_chanel.0.sample_in_buf_RNO[140]\ : - MX2 - port map(A => \sample_in_buf[122]\, B => sample_0(3), S => - sample_val_delay_3, Y => \sample_in_buf_957[140]\); - - \loop_all_sample.7.loop_all_chanel.6.sample_in_buf_RNO[28]\ : - MX2 - port map(A => \sample_in_buf[10]\, B => sample_6(7), S => - sample_val_delay_4, Y => \sample_in_buf_653[28]\); - - \loop_all_sample.8.loop_all_chanel.3.sample_in_buf_RNO[81]\ : - MX2 - port map(A => \sample_in_buf[63]\, B => sample_3(8), S => - sample_val_delay_4, Y => \sample_in_buf_613[81]\); - - \loop_all_sample.14.loop_all_chanel.5.sample_in_buf_RNO[39]\ : - MX2 - port map(A => \sample_in_buf[21]\, B => sample_5(14), S => - sample_val_delay_5, Y => \sample_in_buf_213[39]\); - - \loop_all_sample.12.loop_all_chanel.7.sample_in_buf_RNO[5]\ : - MX2 - port map(A => \sample_in_buf[131]\, B => sample_7(12), S - => sample_val_delay_0, Y => \sample_in_buf_325[5]\); - - \loop_all_sample.0.loop_all_chanel.2.sample_in_buf_RNO[107]\ : - MX2 - port map(A => \sample_in_buf[89]\, B => sample_2(0), S => - sample_val_delay_5, Y => \sample_in_buf_1133[107]\); - - \chanel_more.all_chanel.1.all_bit.15.sample_out_s2[128]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[110]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_126); - - \loop_all_sample.8.loop_all_chanel.1.sample_in_buf[117]\ : - DFN1E1C0 - port map(D => \sample_in_buf_629[117]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[117]\); - - \loop_all_sample.11.loop_all_chanel.1.sample_in_buf_RNO[114]\ : - MX2 - port map(A => \sample_in_buf[96]\, B => sample_1(11), S => - sample_val_delay, Y => \sample_in_buf_437[114]\); - - \loop_all_sample.5.loop_all_chanel.3.sample_in_buf_RNO[84]\ : - MX2 - port map(A => \sample_in_buf[66]\, B => sample_3(5), S => - sample_val_delay, Y => \sample_in_buf_805[84]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \chanel_more.all_chanel.6.all_bit.3.sample_out_s2[50]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[32]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[50]\); - - \loop_all_sample.2.loop_all_chanel.5.sample_in_buf[51]\ : - DFN1E1C0 - port map(D => \sample_in_buf_981[51]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[51]\); - - \chanel_more.all_chanel.7.all_bit.7.sample_out_s2[28]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[10]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[28]\); - - \chanel_more.all_chanel.2.all_bit.15.sample_out_s2[110]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[92]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[110]\); - - \loop_all_sample.8.loop_all_chanel.5.sample_in_buf[45]\ : - DFN1E1C0 - port map(D => \sample_in_buf_597[45]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[45]\); - - \loop_all_sample.9.loop_all_chanel.7.sample_in_buf_RNO[8]\ : - MX2 - port map(A => \sample_in_buf[134]\, B => sample_7(9), S => - sample_val_delay_0, Y => \sample_in_buf_517[8]\); - - \loop_all_sample.4.loop_all_chanel.6.sample_in_buf_RNO[31]\ : - MX2 - port map(A => \sample_in_buf[13]\, B => sample_6(4), S => - sample_val_delay_5, Y => \sample_in_buf_845[31]\); - - \loop_all_sample.8.loop_all_chanel.5.sample_in_buf_RNO[45]\ : - MX2 - port map(A => \sample_in_buf[27]\, B => sample_5(8), S => - sample_val_delay_3, Y => \sample_in_buf_597[45]\); - - \loop_all_sample.11.loop_all_chanel.1.sample_in_buf[114]\ : - DFN1E1C0 - port map(D => \sample_in_buf_437[114]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[114]\); - - \loop_all_sample.2.loop_all_chanel.0.sample_in_buf[141]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1021[141]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[141]\); - - \loop_all_sample.14.loop_all_chanel.4.sample_in_buf[57]\ : - DFN1E1C0 - port map(D => \sample_in_buf_221[57]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[57]\); - - IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW - port map(alu_ctrl(2) => \alu_ctrl[2]\, alu_ctrl(1) => - \alu_ctrl[1]\, alu_ctrl(0) => \alu_ctrl[0]\, - alu_sel_coeff_0_2 => \alu_sel_coeff_0[2]\, - alu_sel_coeff_0_0 => \alu_sel_coeff_0[0]\, - alu_sel_coeff(4) => \alu_sel_coeff[4]\, alu_sel_coeff(3) - => \alu_sel_coeff[3]\, alu_sel_coeff(2) => - \alu_sel_coeff[2]\, alu_sel_coeff(1) => - \alu_sel_coeff[1]\, alu_sel_coeff(0) => - \alu_sel_coeff[0]\, S_0 => \S[8]\, S_36 => \S[44]\, - waddr_previous(1) => \waddr_previous[1]\, - waddr_previous(0) => \waddr_previous[0]\, sample_0(14) - => sample_0(14), sample_0(13) => sample_0(13), - sample_0(12) => sample_0(12), sample_0(11) => - sample_0(11), sample_0(10) => sample_0(10), sample_0(9) - => sample_0(9), sample_0(8) => sample_0(8), sample_0(7) - => sample_0(7), sample_0(6) => sample_0(6), sample_0(5) - => sample_0(5), sample_0(4) => sample_0(4), sample_0(3) - => sample_0(3), sample_0(2) => sample_0(2), sample_0(1) - => sample_0(1), sample_0(0) => sample_0(0), - sample_in_buf(143) => \sample_in_buf[143]\, - sample_in_buf(142) => \sample_in_buf[142]\, - sample_in_buf(141) => \sample_in_buf[141]\, - sample_in_buf(140) => \sample_in_buf[140]\, - sample_in_buf(139) => \sample_in_buf[139]\, - sample_in_buf(138) => \sample_in_buf[138]\, - sample_in_buf(137) => \sample_in_buf[137]\, - sample_in_buf(136) => \sample_in_buf[136]\, - sample_in_buf(135) => \sample_in_buf[135]\, - sample_in_buf(134) => \sample_in_buf[134]\, - sample_in_buf(133) => \sample_in_buf[133]\, - sample_in_buf(132) => \sample_in_buf[132]\, - sample_in_buf(131) => \sample_in_buf[131]\, - sample_in_buf(130) => \sample_in_buf[130]\, - sample_in_buf(129) => \sample_in_buf[129]\, - ram_sel_Wdata(1) => \ram_sel_Wdata[1]\, ram_sel_Wdata(0) - => \ram_sel_Wdata[0]\, sample_out_s_1 => - \sample_out_s[1]\, sample_out_s_2 => \sample_out_s[2]\, - sample_out_s_0 => \sample_out_s[0]\, sample_out_s_3 => - \sample_out_s[3]\, sample_out_s_15 => \sample_out_s[15]\, - sample_out_s_14 => \sample_out_s[14]\, sample_out_s_13 - => \sample_out_s[13]\, sample_out_s_12 => - \sample_out_s[12]\, sample_out_s_11 => \sample_out_s[11]\, - sample_out_s_10 => \sample_out_s[10]\, sample_out_s_9 => - \sample_out_s[9]\, sample_out_s_8 => \sample_out_s[8]\, - sample_out_s_7 => \sample_out_s[7]\, sample_out_s_6 => - \sample_out_s[6]\, sample_out_s_5 => \sample_out_s[5]\, - sample_out_s_4 => \sample_out_s[4]\, sample_in_s_1(17) - => \sample_in_s_1[17]\, in_sel_src(1) => \in_sel_src[1]\, - in_sel_src(0) => \in_sel_src[0]\, raddr_rst => raddr_rst, - raddr_add1 => raddr_add1, ram_write => ram_write, - IIR_CEL_CTRLR_v2_DATAFLOW_GND => IIR_CEL_CTRLR_v2_GND, - IIR_CEL_CTRLR_v2_DATAFLOW_VCC => IIR_CEL_CTRLR_v2_VCC, - ram_write_i => ram_write_i, rstn => rstn, lclk_c => - lclk_c, sample_val_delay_5 => sample_val_delay_5, - sample_val_delay_1 => sample_val_delay_1, - sample_val_delay_0 => sample_val_delay_0, alu_sel_input - => alu_sel_input); - - sample_out_val : DFN1C0 - port map(D => \sample_out_val_s2\, CLK => lclk_c, CLR => - rstn, Q => sample_filter_v2_out_val); - - \loop_all_sample.8.loop_all_chanel.3.sample_in_buf[81]\ : - DFN1E1C0 - port map(D => \sample_in_buf_613[81]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[81]\); - - \loop_all_sample.17.loop_all_chanel.4.sample_in_buf_RNO[54]\ : - MX2 - port map(A => \sample_in_buf[36]\, B => sample_4(15), S => - sample_val_delay, Y => \sample_in_buf_29[54]\); - - \loop_all_sample.4.loop_all_chanel.3.sample_in_buf[85]\ : - DFN1E1C0 - port map(D => \sample_in_buf_869[85]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[85]\); - - \loop_all_sample.3.loop_all_chanel.4.sample_in_buf[68]\ : - DFN1E1C0 - port map(D => \sample_in_buf_925[68]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[68]\); - - \loop_all_sample.10.loop_all_chanel.7.sample_in_buf_RNO[7]\ : - MX2 - port map(A => \sample_in_buf[133]\, B => sample_7(10), S - => sample_val_delay_1, Y => \sample_in_buf_453[7]\); - - \loop_all_sample.10.loop_all_chanel.4.sample_in_buf[61]\ : - DFN1E1C0 - port map(D => \sample_in_buf_477[61]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[61]\); - - \loop_all_sample.10.loop_all_chanel.3.sample_in_buf[79]\ : - DFN1E1C0 - port map(D => \sample_in_buf_485[79]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[79]\); - - \chanel_more.all_chanel.4.all_bit.15.sample_out_s2[74]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[56]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[74]\); - - \chanel_more.all_chanel.2.all_bit.5.sample_out_s2[120]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[102]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[120]\); - - \chanel_more.all_chanel.2.all_bit.14.sample_out_s2[111]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[93]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[111]\); - - \chanel_more.all_chanel.2.all_bit.6.sample_out_s2[119]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[101]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[119]\); - - \loop_all_sample.11.loop_all_chanel.0.sample_in_buf[132]\ : - DFN1E1C0 - port map(D => \sample_in_buf_445[132]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[132]\); - - \chanel_more.all_chanel.7.all_bit.13.sample_out_s2[22]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[4]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[22]\); - - \loop_all_sample.6.loop_all_chanel.5.sample_in_buf_RNO[47]\ : - MX2 - port map(A => \sample_in_buf[29]\, B => sample_5(6), S => - sample_val_delay_5, Y => \sample_in_buf_725[47]\); - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf_RNO[126]\ : - MX2 - port map(A => \sample_in_buf[109]\, B => sample_0(15), S - => sample_val_delay_1, Y => \sample_in_buf_61[126]\); - - \loop_all_sample.6.loop_all_chanel.6.sample_in_buf[29]\ : - DFN1E1C0 - port map(D => \sample_in_buf_717[29]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[29]\); - - \loop_all_sample.1.loop_all_chanel.2.sample_in_buf_RNO[106]\ : - MX2 - port map(A => \sample_in_buf[88]\, B => sample_2(1), S => - sample_val_delay_5, Y => \sample_in_buf_1069[106]\); - - \loop_all_sample.0.loop_all_chanel.6.sample_in_buf[35]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1101[35]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[35]\); - - \chanel_more.all_chanel.3.all_bit.0.sample_out_s2[107]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[89]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[107]\); - - \loop_all_sample.4.loop_all_chanel.6.sample_in_buf[31]\ : - DFN1E1C0 - port map(D => \sample_in_buf_845[31]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[31]\); - - \chanel_more.all_chanel.4.all_bit.8.sample_out_s2[81]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[63]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[81]\); - - \chanel_more.all_chanel.6.all_bit.14.sample_out_s2[39]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[21]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[39]\); - - \loop_all_sample.12.loop_all_chanel.3.sample_in_buf_RNO[77]\ : - MX2 - port map(A => \sample_in_buf[59]\, B => sample_3(12), S => - sample_val_delay_2, Y => \sample_in_buf_357[77]\); - - \loop_all_sample.1.loop_all_chanel.5.sample_in_buf_RNO[52]\ : - MX2 - port map(A => \sample_in_buf[34]\, B => sample_5(1), S => - sample_val_delay, Y => \sample_in_buf_1045[52]\); - - \chanel_more.all_chanel.7.all_bit.14.sample_out_s2[21]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[3]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[21]\); - - \loop_all_sample.2.loop_all_chanel.2.sample_in_buf[105]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1005[105]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[105]\); - - \loop_all_sample.10.loop_all_chanel.6.sample_in_buf_RNO[25]\ : - MX2 - port map(A => \sample_in_buf[7]\, B => sample_6(10), S => - sample_val_delay_3, Y => \sample_in_buf_461[25]\); - - \chanel_more.all_chanel.3.all_bit.14.sample_out_s2[93]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[75]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[93]\); - - \loop_all_sample.2.loop_all_chanel.0.sample_in_buf_RNO[141]\ : - MX2 - port map(A => \sample_in_buf[123]\, B => sample_0(2), S => - sample_val_delay_2, Y => \sample_in_buf_1021[141]\); - - \loop_all_sample.3.loop_all_chanel.1.sample_in_buf[122]\ : - DFN1E1C0 - port map(D => \sample_in_buf_949[122]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[122]\); - - \chanel_more.all_chanel.4.all_bit.9.sample_out_s2[80]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[62]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[80]\); - - \chanel_more.all_chanel.4.all_bit.6.sample_out_s2[83]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[65]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[83]\); - - \loop_all_sample.13.loop_all_chanel.6.sample_in_buf_RNO[22]\ : - MX2 - port map(A => \sample_in_buf[4]\, B => sample_6(13), S => - sample_val_delay_3, Y => \sample_in_buf_269[22]\); - - \loop_all_sample.8.loop_all_chanel.6.sample_in_buf[27]\ : - DFN1E1C0 - port map(D => \sample_in_buf_589[27]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[27]\); - - \loop_all_sample.2.loop_all_chanel.3.sample_in_buf[87]\ : - DFN1E1C0 - port map(D => \sample_in_buf_997[87]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[87]\); - - \chanel_more.all_chanel.3.all_bit.15.sample_out_s2[92]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[74]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[92]\); - - \loop_all_sample.3.loop_all_chanel.3.sample_in_buf_RNO[86]\ : - MX2 - port map(A => \sample_in_buf[68]\, B => sample_3(3), S => - sample_val_delay_5, Y => \sample_in_buf_933[86]\); - - \chanel_more.all_chanel.6.all_bit.10.sample_out_s2[43]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[25]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[43]\); - - \loop_all_sample.6.loop_all_chanel.4.sample_in_buf_RNO[65]\ : - MX2 - port map(A => \sample_in_buf[47]\, B => sample_4(6), S => - sample_val_delay_3, Y => \sample_in_buf_733[65]\); - - \loop_all_sample.0.loop_all_chanel.0.sample_in_buf[143]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1149[143]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[143]\); - - \loop_all_sample.3.loop_all_chanel.0.sample_in_buf[140]\ : - DFN1E1C0 - port map(D => \sample_in_buf_957[140]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[140]\); - - \loop_all_sample.1.loop_all_chanel.4.sample_in_buf[70]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1053[70]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[70]\); - - \loop_all_sample.14.loop_all_chanel.2.sample_in_buf[93]\ : - DFN1E1C0 - port map(D => \sample_in_buf_237[93]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[93]\); - - \chanel_HIGH.14.sample_out_s2[3]\ : DFN1E1C0 - port map(D => \sample_out_s[14]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[3]\); - - \loop_all_sample.9.loop_all_chanel.1.sample_in_buf[116]\ : - DFN1E1C0 - port map(D => \sample_in_buf_565[116]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[116]\); - - \loop_all_sample.17.loop_all_chanel.2.sample_in_buf[90]\ : - DFN1E1C0 - port map(D => \sample_in_buf_45[90]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[90]\); - - \loop_all_sample.0.loop_all_chanel.2.sample_in_buf[107]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1133[107]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[107]\); - - \loop_all_sample.4.loop_all_chanel.4.sample_in_buf_RNO[67]\ : - MX2 - port map(A => \sample_in_buf[49]\, B => sample_4(4), S => - sample_val_delay_4, Y => \sample_in_buf_861[67]\); - - \loop_all_sample.8.loop_all_chanel.0.sample_in_buf[135]\ : - DFN1E1C0 - port map(D => \sample_in_buf_637[135]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[135]\); - - \chanel_more.all_chanel.5.all_bit.13.sample_out_s2[58]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[40]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[58]\); - - \chanel_HIGH.2.sample_out_s2[15]\ : DFN1E1C0 - port map(D => \sample_out_s[2]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[15]\); - - \chanel_more.all_chanel.4.all_bit.10.sample_out_s2[79]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[61]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[79]\); - - \loop_all_sample.12.loop_all_chanel.2.sample_in_buf_RNO[95]\ : - MX2 - port map(A => \sample_in_buf[77]\, B => sample_2(12), S => - sample_val_delay_4, Y => \sample_in_buf_365[95]\); - - \loop_all_sample.5.loop_all_chanel.5.sample_in_buf[48]\ : - DFN1E1C0 - port map(D => \sample_in_buf_789[48]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[48]\); - - \loop_all_sample.14.loop_all_chanel.7.sample_in_buf[3]\ : - DFN1E1C0 - port map(D => \sample_in_buf_197[3]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[3]\); - - \chanel_more.all_chanel.7.all_bit.10.sample_out_s2[25]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[7]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[25]\); - - \loop_all_sample.12.loop_all_chanel.3.sample_in_buf[77]\ : - DFN1E1C0 - port map(D => \sample_in_buf_357[77]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[77]\); - - \chanel_more.all_chanel.3.all_bit.3.sample_out_s2[104]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[86]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[104]\); - - sample_out_val_s2 : DFN1C0 - port map(D => sample_out_val_s, CLK => lclk_c, CLR => rstn, - Q => \sample_out_val_s2\); - - \chanel_more.all_chanel.7.all_bit.9.sample_out_s2[26]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[8]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[26]\); - - \loop_all_sample.5.loop_all_chanel.6.sample_in_buf_RNO[30]\ : - MX2 - port map(A => \sample_in_buf[12]\, B => sample_6(5), S => - sample_val_delay_4, Y => \sample_in_buf_781[30]\); - - \loop_all_sample.14.loop_all_chanel.5.sample_in_buf[39]\ : - DFN1E1C0 - port map(D => \sample_in_buf_213[39]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[39]\); - - \chanel_more.all_chanel.2.all_bit.0.sample_out_s2[125]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[107]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[125]\); - - \chanel_more.all_chanel.2.all_bit.2.sample_out_s2[123]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[105]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[123]\); - - \chanel_more.all_chanel.3.all_bit.7.sample_out_s2[100]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[82]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[100]\); - - \loop_all_sample.4.loop_all_chanel.7.sample_in_buf_RNO[13]\ : - MX2 - port map(A => \sample_in_buf[139]\, B => sample_7(4), S => - sample_val_delay_1, Y => \sample_in_buf_837[13]\); - - \loop_all_sample.14.loop_all_chanel.6.sample_in_buf_RNO[21]\ : - MX2 - port map(A => \sample_in_buf[3]\, B => sample_6(14), S => - sample_val_delay_2, Y => \sample_in_buf_205[21]\); - - \chanel_more.all_chanel.2.all_bit.13.sample_out_s2[112]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[94]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[112]\); - - \loop_all_sample.9.loop_all_chanel.6.sample_in_buf_RNO[26]\ : - MX2 - port map(A => \sample_in_buf[8]\, B => sample_6(9), S => - sample_val_delay_3, Y => \sample_in_buf_525[26]\); - - \loop_all_sample.9.loop_all_chanel.3.sample_in_buf[80]\ : - DFN1E1C0 - port map(D => \sample_in_buf_549[80]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[80]\); - - \loop_all_sample.7.loop_all_chanel.7.sample_in_buf[10]\ : - DFN1E1C0 - port map(D => \sample_in_buf_645[10]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[10]\); - - \loop_all_sample.12.loop_all_chanel.1.sample_in_buf_RNO[113]\ : - MX2 - port map(A => \sample_in_buf[95]\, B => sample_1(12), S => - sample_val_delay_5, Y => \sample_in_buf_373[113]\); - - \chanel_HIGH.1.sample_out_s2[16]\ : DFN1E1C0 - port map(D => \sample_out_s[1]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[16]\); - - \loop_all_sample.8.loop_all_chanel.4.sample_in_buf_RNO[63]\ : - MX2 - port map(A => \sample_in_buf[45]\, B => sample_4(8), S => - sample_val_delay, Y => \sample_in_buf_605[63]\); - - \loop_all_sample.6.loop_all_chanel.7.sample_in_buf_RNO[11]\ : - MX2 - port map(A => \sample_in_buf[137]\, B => sample_7(6), S => - sample_val_delay_1, Y => \sample_in_buf_709[11]\); - - \loop_all_sample.14.loop_all_chanel.0.sample_in_buf_RNO[129]\ : - MX2 - port map(A => \sample_in_buf[111]\, B => sample_0(14), S - => sample_val_delay_1, Y => \sample_in_buf_253[129]\); - - \chanel_HIGH.12.sample_out_s2[5]\ : DFN1E1C0 - port map(D => \sample_out_s[12]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[5]\); - - \loop_all_sample.3.loop_all_chanel.6.sample_in_buf[32]\ : - DFN1E1C0 - port map(D => \sample_in_buf_909[32]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[32]\); - - \loop_all_sample.17.loop_all_chanel.5.sample_in_buf_RNO[36]\ : - MX2 - port map(A => \sample_in_buf[18]\, B => sample_5(15), S => - sample_val_delay_5, Y => \sample_in_buf_21[36]\); - - \chanel_more.all_chanel.5.all_bit.8.sample_out_s2[63]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[45]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[63]\); - - \loop_all_sample.8.loop_all_chanel.7.sample_in_buf_RNO[9]\ : - MX2 - port map(A => \sample_in_buf[135]\, B => sample_7(8), S => - sample_val_delay_0, Y => \sample_in_buf_581[9]\); - - \loop_all_sample.5.loop_all_chanel.7.sample_in_buf_RNO[12]\ : - MX2 - port map(A => \sample_in_buf[138]\, B => sample_7(5), S => - sample_val_delay_5, Y => \sample_in_buf_773[12]\); - - \loop_all_sample.1.loop_all_chanel.4.sample_in_buf_RNO[70]\ : - MX2 - port map(A => \sample_in_buf[52]\, B => sample_4(1), S => - sample_val_delay_3, Y => \sample_in_buf_1053[70]\); - - \loop_all_sample.7.loop_all_chanel.6.sample_in_buf[28]\ : - DFN1E1C0 - port map(D => \sample_in_buf_653[28]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[28]\); - - \loop_all_sample.13.loop_all_chanel.3.sample_in_buf[76]\ : - DFN1E1C0 - port map(D => \sample_in_buf_293[76]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[76]\); - - \loop_all_sample.17.loop_all_chanel.6.sample_in_buf[18]\ : - DFN1E1C0 - port map(D => \sample_in_buf_13[18]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[18]\); - - \loop_all_sample.0.loop_all_chanel.3.sample_in_buf_RNO[89]\ : - MX2 - port map(A => \sample_in_buf[71]\, B => sample_3(0), S => - sample_val_delay_4, Y => \sample_in_buf_1125[89]\); - - \chanel_more.all_chanel.2.all_bit.11.sample_out_s2[114]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[96]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[114]\); - - \loop_all_sample.12.loop_all_chanel.1.sample_in_buf[113]\ : - DFN1E1C0 - port map(D => \sample_in_buf_373[113]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[113]\); - - \loop_all_sample.0.loop_all_chanel.4.sample_in_buf_RNO[71]\ : - MX2 - port map(A => \sample_in_buf[53]\, B => sample_4(0), S => - sample_val_delay, Y => \sample_in_buf_1117[71]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \loop_all_sample.13.loop_all_chanel.1.sample_in_buf[112]\ : - DFN1E1C0 - port map(D => \sample_in_buf_309[112]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[112]\); - - \chanel_more.all_chanel.6.all_bit.9.sample_out_s2[44]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[26]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[44]\); - - \chanel_more.all_chanel.2.all_bit.1.sample_out_s2[124]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[106]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[124]\); - - \loop_all_sample.12.loop_all_chanel.4.sample_in_buf[59]\ : - DFN1E1C0 - port map(D => \sample_in_buf_349[59]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[59]\); - - \loop_all_sample.8.loop_all_chanel.7.sample_in_buf[9]\ : - DFN1E1C0 - port map(D => \sample_in_buf_581[9]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[9]\); - - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf_RNIP7V4[126]\ : - MX2 - port map(A => \sample_in_buf[127]\, B => sample_0(15), S - => sample_val_delay_1, Y => \sample_in_s_1[17]\); - - \chanel_HIGH.5.sample_out_s2[12]\ : DFN1E1C0 - port map(D => \sample_out_s[5]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[12]\); - - \loop_all_sample.5.loop_all_chanel.0.sample_in_buf[138]\ : - DFN1E1C0 - port map(D => \sample_in_buf_829[138]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[138]\); - - \loop_all_sample.3.loop_all_chanel.5.sample_in_buf[50]\ : - DFN1E1C0 - port map(D => \sample_in_buf_917[50]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[50]\); - - \loop_all_sample.0.loop_all_chanel.1.sample_in_buf[125]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1141[125]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[125]\); - - \loop_all_sample.9.loop_all_chanel.2.sample_in_buf[98]\ : - DFN1E1C0 - port map(D => \sample_in_buf_557[98]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[98]\); - - \loop_all_sample.6.loop_all_chanel.0.sample_in_buf[137]\ : - DFN1E1C0 - port map(D => \sample_in_buf_765[137]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[137]\); - - \loop_all_sample.3.loop_all_chanel.5.sample_in_buf_RNO[50]\ : - MX2 - port map(A => \sample_in_buf[32]\, B => sample_5(3), S => - sample_val_delay_4, Y => \sample_in_buf_917[50]\); - - \loop_all_sample.1.loop_all_chanel.1.sample_in_buf[124]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1077[124]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[124]\); - - \loop_all_sample.14.loop_all_chanel.3.sample_in_buf_RNO[75]\ : - MX2 - port map(A => \sample_in_buf[57]\, B => sample_3(14), S => - sample_val_delay_2, Y => \sample_in_buf_229[75]\); - - \chanel_HIGH.4.sample_out_s2[13]\ : DFN1E1C0 - port map(D => \sample_out_s[4]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[13]\); - - \chanel_HIGH.0.sample_out_s2[17]\ : DFN1E1C0 - port map(D => \sample_out_s[0]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[17]\); - - \loop_all_sample.7.loop_all_chanel.4.sample_in_buf[64]\ : - DFN1E1C0 - port map(D => \sample_in_buf_669[64]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[64]\); - - \chanel_more.all_chanel.1.all_bit.1.sample_out_s2[142]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[124]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_140); - - \loop_all_sample.6.loop_all_chanel.6.sample_in_buf_RNO[29]\ : - MX2 - port map(A => \sample_in_buf[11]\, B => sample_6(6), S => - sample_val_delay_2, Y => \sample_in_buf_717[29]\); - - \loop_all_sample.14.loop_all_chanel.4.sample_in_buf_RNO[57]\ : - MX2 - port map(A => \sample_in_buf[39]\, B => sample_4(14), S => - sample_val_delay_5, Y => \sample_in_buf_221[57]\); - - \loop_all_sample.12.loop_all_chanel.6.sample_in_buf_RNO[23]\ : - MX2 - port map(A => \sample_in_buf[5]\, B => sample_6(12), S => - sample_val_delay_3, Y => \sample_in_buf_333[23]\); - - \chanel_more.all_chanel.5.all_bit.4.sample_out_s2[67]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[49]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[67]\); - - \chanel_more.all_chanel.3.all_bit.9.sample_out_s2[98]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[80]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[98]\); - - \loop_all_sample.7.loop_all_chanel.5.sample_in_buf[46]\ : - DFN1E1C0 - port map(D => \sample_in_buf_661[46]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[46]\); - - \loop_all_sample.9.loop_all_chanel.0.sample_in_buf[134]\ : - DFN1E1C0 - port map(D => \sample_in_buf_573[134]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[134]\); - - \chanel_more.all_chanel.4.all_bit.3.sample_out_s2[86]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[68]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[86]\); - - \loop_all_sample.5.loop_all_chanel.7.sample_in_buf[12]\ : - DFN1E1C0 - port map(D => \sample_in_buf_773[12]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[12]\); - - \loop_all_sample.4.loop_all_chanel.7.sample_in_buf[13]\ : - DFN1E1C0 - port map(D => \sample_in_buf_837[13]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[13]\); - - \loop_all_sample.2.loop_all_chanel.4.sample_in_buf[69]\ : - DFN1E1C0 - port map(D => \sample_in_buf_989[69]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[69]\); - - \loop_all_sample.12.loop_all_chanel.0.sample_in_buf[131]\ : - DFN1E1C0 - port map(D => \sample_in_buf_381[131]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[131]\); - - \loop_all_sample.4.loop_all_chanel.5.sample_in_buf[49]\ : - DFN1E1C0 - port map(D => \sample_in_buf_853[49]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[49]\); - - \loop_all_sample.11.loop_all_chanel.6.sample_in_buf[24]\ : - DFN1E1C0 - port map(D => \sample_in_buf_397[24]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[24]\); - - \loop_all_sample.3.loop_all_chanel.7.sample_in_buf_RNO[14]\ : - MX2 - port map(A => \sample_in_buf[140]\, B => sample_7(3), S => - sample_val_delay_3, Y => \sample_in_buf_901[14]\); - - \loop_all_sample.1.loop_all_chanel.0.sample_in_buf[142]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1085[142]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[142]\); - - \loop_all_sample.8.loop_all_chanel.4.sample_in_buf[63]\ : - DFN1E1C0 - port map(D => \sample_in_buf_605[63]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[63]\); - - \loop_all_sample.10.loop_all_chanel.1.sample_in_buf[115]\ : - DFN1E1C0 - port map(D => \sample_in_buf_501[115]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[115]\); - - \loop_all_sample.0.loop_all_chanel.4.sample_in_buf[71]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1117[71]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[71]\); - - \loop_all_sample.4.loop_all_chanel.3.sample_in_buf_RNO[85]\ : - MX2 - port map(A => \sample_in_buf[67]\, B => sample_3(4), S => - sample_val_delay_4, Y => \sample_in_buf_869[85]\); - - \loop_all_sample.13.loop_all_chanel.3.sample_in_buf_RNO[76]\ : - MX2 - port map(A => \sample_in_buf[58]\, B => sample_3(13), S => - sample_val_delay, Y => \sample_in_buf_293[76]\); - - \loop_all_sample.14.loop_all_chanel.1.sample_in_buf[111]\ : - DFN1E1C0 - port map(D => \sample_in_buf_245[111]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[111]\); - - \chanel_more.all_chanel.3.all_bit.5.sample_out_s2[102]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[84]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[102]\); - - \loop_all_sample.2.loop_all_chanel.7.sample_in_buf[15]\ : - DFN1E1C0 - port map(D => \sample_in_buf_965[15]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[15]\); - - \loop_all_sample.14.loop_all_chanel.7.sample_in_buf_RNO[3]\ : - MX2 - port map(A => \sample_in_buf[129]\, B => sample_7(14), S - => sample_val_delay_1, Y => \sample_in_buf_197[3]\); - - \chanel_more.all_chanel.7.all_bit.4.sample_out_s2[31]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[13]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[31]\); - - \loop_all_sample.7.loop_all_chanel.2.sample_in_buf_RNO[100]\ : - MX2 - port map(A => \sample_in_buf[82]\, B => sample_2(7), S => - sample_val_delay_2, Y => \sample_in_buf_685[100]\); - - \loop_all_sample.8.loop_all_chanel.0.sample_in_buf_RNO[135]\ : - MX2 - port map(A => \sample_in_buf[117]\, B => sample_0(8), S => - sample_val_delay_0, Y => \sample_in_buf_637[135]\); - - \loop_all_sample.7.loop_all_chanel.5.sample_in_buf_RNO[46]\ : - MX2 - port map(A => \sample_in_buf[28]\, B => sample_5(7), S => - sample_val_delay_2, Y => \sample_in_buf_661[46]\); - - \loop_all_sample.7.loop_all_chanel.1.sample_in_buf[118]\ : - DFN1E1C0 - port map(D => \sample_in_buf_693[118]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[118]\); - - \chanel_more.all_chanel.5.all_bit.3.sample_out_s2[68]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[50]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[68]\); - - \loop_all_sample.11.loop_all_chanel.5.sample_in_buf_RNO[42]\ : - MX2 - port map(A => \sample_in_buf[24]\, B => sample_5(11), S => - sample_val_delay_3, Y => \sample_in_buf_405[42]\); - - \chanel_more.all_chanel.3.all_bit.12.sample_out_s2[95]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[77]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[95]\); - - \loop_all_sample.1.loop_all_chanel.0.sample_in_buf_RNO[142]\ : - MX2 - port map(A => \sample_in_buf[124]\, B => sample_0(1), S => - sample_val_delay_1, Y => \sample_in_buf_1085[142]\); - - \loop_all_sample.12.loop_all_chanel.6.sample_in_buf[23]\ : - DFN1E1C0 - port map(D => \sample_in_buf_333[23]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[23]\); - - \chanel_more.all_chanel.5.all_bit.15.sample_out_s2[56]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[38]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[56]\); - - \loop_all_sample.4.loop_all_chanel.0.sample_in_buf[139]\ : - DFN1E1C0 - port map(D => \sample_in_buf_893[139]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[139]\); - - \chanel_more.all_chanel.6.all_bit.5.sample_out_s2[48]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[30]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[48]\); - - \loop_all_sample.4.loop_all_chanel.4.sample_in_buf[67]\ : - DFN1E1C0 - port map(D => \sample_in_buf_861[67]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[67]\); - - \loop_all_sample.12.loop_all_chanel.0.sample_in_buf_RNO[131]\ : - MX2 - port map(A => \sample_in_buf[113]\, B => sample_0(12), S - => sample_val_delay_0, Y => \sample_in_buf_381[131]\); - - \chanel_more.all_chanel.4.all_bit.2.sample_out_s2[87]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[69]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[87]\); - - \loop_all_sample.5.loop_all_chanel.0.sample_in_buf_RNO[138]\ : - MX2 - port map(A => \sample_in_buf[120]\, B => sample_0(5), S => - sample_val_delay_5, Y => \sample_in_buf_829[138]\); - - \chanel_more.all_chanel.7.all_bit.5.sample_out_s2[30]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[12]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[30]\); - - \chanel_more.all_chanel.5.all_bit.14.sample_out_s2[57]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[39]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[57]\); - - \loop_all_sample.9.loop_all_chanel.5.sample_in_buf_RNO[44]\ : - MX2 - port map(A => \sample_in_buf[26]\, B => sample_5(9), S => - sample_val_delay_4, Y => \sample_in_buf_533[44]\); - - \chanel_more.all_chanel.3.all_bit.2.sample_out_s2[105]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[87]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[105]\); - - \loop_all_sample.5.loop_all_chanel.2.sample_in_buf[102]\ : - DFN1E1C0 - port map(D => \sample_in_buf_813[102]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[102]\); - - \chanel_HIGH.10.sample_out_s2[7]\ : DFN1E1C0 - port map(D => \sample_out_s[10]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[7]\); - - \chanel_more.all_chanel.6.all_bit.13.sample_out_s2[40]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[22]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[40]\); - - \chanel_more.all_chanel.5.all_bit.12.sample_out_s2[59]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[41]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[59]\); - - \loop_all_sample.14.loop_all_chanel.3.sample_in_buf[75]\ : - DFN1E1C0 - port map(D => \sample_in_buf_229[75]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[75]\); - - \loop_all_sample.14.loop_all_chanel.2.sample_in_buf_RNO[93]\ : - MX2 - port map(A => \sample_in_buf[75]\, B => sample_2(14), S => - sample_val_delay_4, Y => \sample_in_buf_237[93]\); - - \loop_all_sample.10.loop_all_chanel.5.sample_in_buf_RNO[43]\ : - MX2 - port map(A => \sample_in_buf[25]\, B => sample_5(10), S => - sample_val_delay_4, Y => \sample_in_buf_469[43]\); - - \loop_all_sample.0.loop_all_chanel.7.sample_in_buf[17]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1093[17]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[17]\); - - \loop_all_sample.6.loop_all_chanel.3.sample_in_buf_RNO[83]\ : - MX2 - port map(A => \sample_in_buf[65]\, B => sample_3(6), S => - sample_val_delay_5, Y => \sample_in_buf_741[83]\); - - \loop_all_sample.5.loop_all_chanel.6.sample_in_buf[30]\ : - DFN1E1C0 - port map(D => \sample_in_buf_781[30]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[30]\); - - \loop_all_sample.13.loop_all_chanel.0.sample_in_buf[130]\ : - DFN1E1C0 - port map(D => \sample_in_buf_317[130]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[130]\); - - \loop_all_sample.10.loop_all_chanel.7.sample_in_buf[7]\ : - DFN1E1C0 - port map(D => \sample_in_buf_453[7]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[7]\); - - \loop_all_sample.0.loop_all_chanel.0.sample_in_buf_RNO[143]\ : - MX2 - port map(A => \sample_in_buf[125]\, B => sample_0(0), S => - sample_val_delay_5, Y => \sample_in_buf_1149[143]\); - - \chanel_more.all_chanel.4.all_bit.12.sample_out_s2[77]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[59]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[77]\); - - \loop_all_sample.2.loop_all_chanel.6.sample_in_buf_RNO[33]\ : - MX2 - port map(A => \sample_in_buf[15]\, B => sample_6(2), S => - sample_val_delay_2, Y => \sample_in_buf_973[33]\); - - \chanel_more.all_chanel.5.all_bit.5.sample_out_s2[66]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[48]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[66]\); - - \loop_all_sample.6.loop_all_chanel.1.sample_in_buf[119]\ : - DFN1E1C0 - port map(D => \sample_in_buf_757[119]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[119]\); - - \loop_all_sample.0.loop_all_chanel.5.sample_in_buf[53]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1109[53]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[53]\); - - \loop_all_sample.17.loop_all_chanel.6.sample_in_buf_RNO[18]\ : - MX2 - port map(A => \sample_in_buf[1]\, B => sample_6(15), S => - sample_val_delay_2, Y => \sample_in_buf_13[18]\); - - \chanel_more.all_chanel.6.all_bit.4.sample_out_s2[49]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[31]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[49]\); - - \chanel_more.all_chanel.5.all_bit.1.sample_out_s2[70]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[52]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[70]\); - - \loop_all_sample.17.loop_all_chanel.7.sample_in_buf[0]\ : - DFN1E1C0 - port map(D => \sample_in_buf_5[0]\, CLK => lclk_c, CLR => - rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[1]\); - - \chanel_more.all_chanel.1.all_bit.14.sample_out_s2[129]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[111]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_127); - - \loop_all_sample.5.loop_all_chanel.1.sample_in_buf_RNO[120]\ : - MX2 - port map(A => \sample_in_buf[102]\, B => sample_1(5), S => - sample_val_delay, Y => \sample_in_buf_821[120]\); - - \loop_all_sample.0.loop_all_chanel.7.sample_in_buf_RNO[17]\ : - MX2 - port map(A => \sample_in_buf[143]\, B => sample_7(0), S => - sample_val_delay_5, Y => \sample_in_buf_1093[17]\); - - \loop_all_sample.12.loop_all_chanel.7.sample_in_buf[5]\ : - DFN1E1C0 - port map(D => \sample_in_buf_325[5]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[5]\); - - \chanel_more.all_chanel.3.all_bit.8.sample_out_s2[99]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[81]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[99]\); - - \chanel_more.all_chanel.4.all_bit.7.sample_out_s2[82]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[64]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[82]\); - - \loop_all_sample.10.loop_all_chanel.0.sample_in_buf[133]\ : - DFN1E1C0 - port map(D => \sample_in_buf_509[133]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[133]\); - - \loop_all_sample.3.loop_all_chanel.7.sample_in_buf[14]\ : - DFN1E1C0 - port map(D => \sample_in_buf_901[14]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[14]\); - - \chanel_HIGH.8.sample_out_s2[9]\ : DFN1E1C0 - port map(D => \sample_out_s[8]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[9]\); - - \chanel_more.all_chanel.5.all_bit.2.sample_out_s2[69]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[51]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[69]\); - - \chanel_more.all_chanel.1.all_bit.0.sample_out_s2[143]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[125]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_141); - - \chanel_more.all_chanel.1.all_bit.12.sample_out_s2[131]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[113]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_129); - - \chanel_HIGH.3.sample_out_s2[14]\ : DFN1E1C0 - port map(D => \sample_out_s[3]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[14]\); - - \chanel_more.all_chanel.7.all_bit.12.sample_out_s2[23]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[5]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[23]\); - - \loop_all_sample.8.loop_all_chanel.1.sample_in_buf_RNO[117]\ : - MX2 - port map(A => \sample_in_buf[99]\, B => sample_1(8), S => - sample_val_delay_2, Y => \sample_in_buf_629[117]\); - - \loop_all_sample.10.loop_all_chanel.0.sample_in_buf_RNO[133]\ : - MX2 - port map(A => \sample_in_buf[115]\, B => sample_0(10), S - => sample_val_delay_1, Y => \sample_in_buf_509[133]\); - - \loop_all_sample.11.loop_all_chanel.3.sample_in_buf[78]\ : - DFN1E1C0 - port map(D => \sample_in_buf_421[78]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[78]\); - - \chanel_HIGH.11.sample_out_s2[6]\ : DFN1E1C0 - port map(D => \sample_out_s[11]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[6]\); - - \loop_all_sample.10.loop_all_chanel.3.sample_in_buf_RNO[79]\ : - MX2 - port map(A => \sample_in_buf[61]\, B => sample_3(10), S => - sample_val_delay_3, Y => \sample_in_buf_485[79]\); - - \chanel_more.all_chanel.1.all_bit.11.sample_out_s2[132]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[114]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_130); - - \chanel_more.all_chanel.1.all_bit.10.sample_out_s2[133]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[115]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_131); - - \loop_all_sample.13.loop_all_chanel.1.sample_in_buf_RNO[112]\ : - MX2 - port map(A => \sample_in_buf[94]\, B => sample_1(13), S => - sample_val_delay_2, Y => \sample_in_buf_309[112]\); - - \loop_all_sample.6.loop_all_chanel.3.sample_in_buf[83]\ : - DFN1E1C0 - port map(D => \sample_in_buf_741[83]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[83]\); - - \loop_all_sample.2.loop_all_chanel.3.sample_in_buf_RNO[87]\ : - MX2 - port map(A => \sample_in_buf[69]\, B => sample_3(2), S => - sample_val_delay_4, Y => \sample_in_buf_997[87]\); - - \loop_all_sample.1.loop_all_chanel.5.sample_in_buf[52]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1045[52]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[52]\); - - \chanel_more.all_chanel.7.all_bit.0.sample_out_s2[35]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[17]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[35]\); - - \chanel_more.all_chanel.4.all_bit.14.sample_out_s2[75]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[57]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[75]\); - - \chanel_more.all_chanel.2.all_bit.4.sample_out_s2[121]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[103]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[121]\); - - \chanel_more.all_chanel.2.all_bit.12.sample_out_s2[113]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[95]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[113]\); - - \chanel_more.all_chanel.1.all_bit.7.sample_out_s2[136]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[118]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_134); - - \chanel_more.all_chanel.1.all_bit.2.sample_out_s2[141]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[123]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_139); - - \loop_all_sample.6.loop_all_chanel.2.sample_in_buf_RNO[101]\ : - MX2 - port map(A => \sample_in_buf[83]\, B => sample_2(6), S => - sample_val_delay_5, Y => \sample_in_buf_749[101]\); - - \chanel_more.all_chanel.5.all_bit.11.sample_out_s2[60]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[42]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[60]\); - - \loop_all_sample.1.loop_all_chanel.1.sample_in_buf_RNO[124]\ : - MX2 - port map(A => \sample_in_buf[106]\, B => sample_1(1), S => - sample_val_delay_3, Y => \sample_in_buf_1077[124]\); - - IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL - port map(alu_ctrl(2) => \alu_ctrl[2]\, alu_ctrl(1) => - \alu_ctrl[1]\, alu_ctrl(0) => \alu_ctrl[0]\, - ram_sel_Wdata(1) => \ram_sel_Wdata[1]\, ram_sel_Wdata(0) - => \ram_sel_Wdata[0]\, waddr_previous(1) => - \waddr_previous[1]\, waddr_previous(0) => - \waddr_previous[0]\, in_sel_src(1) => \in_sel_src[1]\, - in_sel_src(0) => \in_sel_src[0]\, alu_sel_coeff(4) => - \alu_sel_coeff[4]\, alu_sel_coeff(3) => - \alu_sel_coeff[3]\, alu_sel_coeff(2) => - \alu_sel_coeff[2]\, alu_sel_coeff(1) => - \alu_sel_coeff[1]\, alu_sel_coeff(0) => - \alu_sel_coeff[0]\, S_36 => \S[44]\, S_0 => \S[8]\, - alu_sel_coeff_0_2 => \alu_sel_coeff_0[2]\, - alu_sel_coeff_0_0 => \alu_sel_coeff_0[0]\, - sample_out_rot_s => sample_out_rot_s, sample_out_val_s - => sample_out_val_s, raddr_rst => raddr_rst, - alu_sel_input => alu_sel_input, raddr_add1 => raddr_add1, - un1_sample_in_rotate => un1_sample_in_rotate, - sample_val_delay_2 => sample_val_delay_2, - sample_val_delay_1 => sample_val_delay_1, ram_write => - ram_write, ram_write_i => ram_write_i, - un1_sample_in_rotate_0 => un1_sample_in_rotate_0, - un1_sample_in_rotate_1 => un1_sample_in_rotate_1, - un1_sample_in_rotate_2 => un1_sample_in_rotate_2, - un1_sample_in_rotate_3 => un1_sample_in_rotate_3, - sample_val_delay_0 => sample_val_delay_0, - un1_sample_in_rotate_4 => un1_sample_in_rotate_4, - sample_out_rot_s_0 => sample_out_rot_s_0, - sample_out_rot_s_1 => sample_out_rot_s_1, - sample_out_rot_s_2 => sample_out_rot_s_2, - sample_out_rot_s_3 => sample_out_rot_s_3, - sample_out_rot_s_4 => sample_out_rot_s_4, rstn => rstn, - lclk_c => lclk_c); - - \loop_all_sample.7.loop_all_chanel.3.sample_in_buf_RNO[82]\ : - MX2 - port map(A => \sample_in_buf[64]\, B => sample_3(7), S => - sample_val_delay_3, Y => \sample_in_buf_677[82]\); - - \chanel_more.all_chanel.7.all_bit.8.sample_out_s2[27]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[9]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[27]\); - - \chanel_more.all_chanel.6.all_bit.7.sample_out_s2[46]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[28]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[46]\); - - \loop_all_sample.7.loop_all_chanel.3.sample_in_buf[82]\ : - DFN1E1C0 - port map(D => \sample_in_buf_677[82]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[82]\); - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf[126]\ : - DFN1E1C0 - port map(D => \sample_in_buf_61[126]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[127]\); - - \loop_all_sample.11.loop_all_chanel.4.sample_in_buf[60]\ : - DFN1E1C0 - port map(D => \sample_in_buf_413[60]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[60]\); - - \loop_all_sample.3.loop_all_chanel.6.sample_in_buf_RNO[32]\ : - MX2 - port map(A => \sample_in_buf[14]\, B => sample_6(3), S => - sample_val_delay_5, Y => \sample_in_buf_909[32]\); - - \loop_all_sample.17.loop_all_chanel.1.sample_in_buf_RNO[108]\ : - MX2 - port map(A => \sample_in_buf[90]\, B => sample_1(15), S => - sample_val_delay_2, Y => \sample_in_buf_53[108]\); - - \loop_all_sample.8.loop_all_chanel.6.sample_in_buf_RNO[27]\ : - MX2 - port map(A => \sample_in_buf[9]\, B => sample_6(8), S => - sample_val_delay_4, Y => \sample_in_buf_589[27]\); - - \loop_all_sample.5.loop_all_chanel.4.sample_in_buf[66]\ : - DFN1E1C0 - port map(D => \sample_in_buf_797[66]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[66]\); - - \loop_all_sample.14.loop_all_chanel.1.sample_in_buf_RNO[111]\ : - MX2 - port map(A => \sample_in_buf[93]\, B => sample_1(14), S => - sample_val_delay_4, Y => \sample_in_buf_245[111]\); - - \chanel_more.all_chanel.2.all_bit.8.sample_out_s2[117]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[99]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[117]\); - - \chanel_more.all_chanel.7.all_bit.11.sample_out_s2[24]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[6]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[24]\); - - \loop_all_sample.8.loop_all_chanel.2.sample_in_buf_RNO[99]\ : - MX2 - port map(A => \sample_in_buf[81]\, B => sample_2(8), S => - sample_val_delay_2, Y => \sample_in_buf_621[99]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_6_16_256 is - - port( sample_f1 : in std_logic_vector(111 downto 80); - sample_f1_wdata_95 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_0 : in std_logic; - sample_f3_wdata : out std_logic_vector(95 downto 0); - sample_f1_val : in std_logic; - lclk_c : in std_logic; - sample_f3_val : out std_logic; - sample_f1_val_0 : in std_logic; - rstn : in std_logic - ); - -end Downsampling_6_16_256; - -architecture DEF_ARCH of Downsampling_6_16_256 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal sample_out_0_sqmuxa_2, sample_out_val_4, - sample_out_0_sqmuxa_1, sample_out_0_sqmuxa_0, N_137, - \counter[1]_net_1\, \counter[0]_net_1\, N_129, - \counter[3]_net_1\, \DWACT_FDEC_E[0]\, N_106, - \counter[8]_net_1\, \DWACT_FDEC_E[4]\, N_91, - \DWACT_FDEC_E[7]\, \DWACT_FDEC_E[6]\, - un2_sample_in_val_24, un2_sample_in_val_15, - un2_sample_in_val_14, un2_sample_in_val_20, - un2_sample_in_val_23, un2_sample_in_val_9, - un2_sample_in_val_8, un2_sample_in_val_19, - un2_sample_in_val_22, un2_sample_in_val_5, - un2_sample_in_val_4, un2_sample_in_val_17, - un2_sample_in_val_13, \counter[24]_net_1\, - un2_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un2_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un2_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un2_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un2_sample_in_val_i_0, - sample_out_0_sqmuxa, \counter_4[0]\, I_45_9, - \counter_4[1]\, I_52_9, \counter_4[2]\, I_56_10, - \counter_4[4]\, I_73_8, \counter_4[5]\, I_77_8, - \counter_4[7]\, I_91_8, \counter_4[8]\, I_98_8, - \counter_4[10]\, I_115_8, \counter_4[11]\, I_122_8, - \counter_4[13]\, I_136_7, \counter_4[14]\, I_143_7, - \counter_4[3]\, I_66_10, \counter_4[12]\, I_129_8, - \counter_4[15]\, I_156_7, \counter_4[16]\, I_166_7, - \counter_4[17]\, I_173_7, \counter_4[18]\, I_186_7, - \counter_4[19]\, I_196_7, \counter_4[9]\, I_105_8, - \counter_4[6]\, I_84_8, I_4_2, I_5_13, I_9_13, I_13_17, - I_20_13, I_24_14, I_31_13, I_38_10, N_4, - \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val_0, Q => \counter[19]_net_1\); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f1_wdata_73, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(73)); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f1_wdata_75, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(75)); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f1_wdata_82, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(82)); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f1_wdata_94, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(94)); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f1_wdata_76, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(76)); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f1(93), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(34)); - - \sample_out[66]\ : DFN1E1 - port map(D => sample_f1(98), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(29)); - - \sample_out[73]\ : DFN1E1 - port map(D => sample_f1(105), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(22)); - - \sample_out[79]\ : DFN1E1 - port map(D => sample_f1(111), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(16)); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f1_wdata_57, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(57)); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f1_wdata_0, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(0)); - - \counter_RNO[11]\ : NOR2B - port map(A => I_66_10, B => un2_sample_in_val_i_0, Y => - \counter_4[3]\); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f1_wdata_61, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(61)); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_2); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[11]_net_1\); - - \counter_RNIQ01S[12]\ : NOR3C - port map(A => un2_sample_in_val_9, B => un2_sample_in_val_8, - C => un2_sample_in_val_19, Y => un2_sample_in_val_23); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \counter_RNIU2M9[20]\ : NOR3A - port map(A => un2_sample_in_val_3, B => \counter[23]_net_1\, - C => \counter[20]_net_1\, Y => un2_sample_in_val_15); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_7); - - \counter_RNO[15]\ : NOR2B - port map(A => I_91_8, B => un2_sample_in_val_i_0, Y => - \counter_4[7]\); - - \counter_RNITFBJ2_0[10]\ : NOR2B - port map(A => sample_out_val_4, B => rstn, Y => - sample_out_0_sqmuxa_1); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f1(83), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(44)); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f1(88), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(39)); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f1_wdata_95, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(95)); - - \counter[6]\ : DFN1E1C0 - port map(D => I_31_13, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_17); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f1_wdata_14, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(14)); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f1_wdata_9, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(9)); - - \counter[3]\ : DFN1E1C0 - port map(D => I_13_17, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_13, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_8); - - \counter_RNO[8]\ : NOR2B - port map(A => I_45_9, B => un2_sample_in_val_i_0, Y => - \counter_4[0]\); - - \counter_RNO[13]\ : NOR2B - port map(A => I_77_8, B => un2_sample_in_val_i_0, Y => - \counter_4[5]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_9); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f1_wdata_83, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(83)); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f1_wdata_85, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(85)); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f1_wdata_50, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(50)); - - \counter_RNO[12]\ : NOR2B - port map(A => I_73_8, B => un2_sample_in_val_i_0, Y => - \counter_4[4]\); - - \counter_RNIBHB5[12]\ : NOR3A - port map(A => un2_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un2_sample_in_val_19); - - \sample_out[72]\ : DFN1E1 - port map(D => sample_f1(104), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(23)); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f1_wdata_62, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(62)); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f1_wdata_56, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(56)); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[17]_net_1\); - - \sample_out[70]\ : DFN1E1 - port map(D => sample_f1(102), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(25)); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => I_20_13, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_13); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f1_wdata_90, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(90)); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f1_wdata_48, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(48)); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \sample_out[65]\ : DFN1E1 - port map(D => sample_f1(97), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(30)); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f1_wdata_74, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(74)); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f1_wdata_69, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(69)); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f1_wdata_93, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(93)); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[27]_net_1\); - - \counter_RNIK9AB[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un2_sample_in_val_8); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \sample_out[67]\ : DFN1E1 - port map(D => sample_f1(99), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(28)); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f1_wdata_1, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(1)); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_7); - - \counter_RNO[17]\ : NOR2B - port map(A => I_105_8, B => un2_sample_in_val_i_0, Y => - \counter_4[9]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \counter_RNILML2[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un2_sample_in_val_5); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f1(87), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(40)); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \counter_RNI9407[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un2_sample_in_val_3); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_7); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f1_wdata_63, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(63)); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_8); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f1(89), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(38)); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f1_wdata_65, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(65)); - - \counter_RNO[14]\ : NOR2B - port map(A => I_84_8, B => un2_sample_in_val_i_0, Y => - \counter_4[6]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f1_wdata_10, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(10)); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_13, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => I_186_7, B => un2_sample_in_val_i_0, Y => - \counter_4[18]\); - - \counter_RNIR5BB[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un2_sample_in_val_9); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f1_wdata_91, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(91)); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[25]_net_1\); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_4, CLK => lclk_c, CLR => rstn, - Q => sample_f3_val); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f1_wdata_8, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(8)); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_8); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_7); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f1(80), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(47)); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_10); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f1_wdata_2, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(2)); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f1_wdata_84, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(84)); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f1_wdata_79, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(79)); - - \counter[5]\ : DFN1E1C0 - port map(D => I_24_14, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f1_wdata_51, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(51)); - - \sample_out[71]\ : DFN1E1 - port map(D => sample_f1(103), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(24)); - - \sample_out[76]\ : DFN1E1 - port map(D => sample_f1(108), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(19)); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : NOR2B - port map(A => I_56_10, B => un2_sample_in_val_i_0, Y => - \counter_4[2]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_13); - - \counter_RNO[21]\ : NOR2B - port map(A => I_136_7, B => un2_sample_in_val_i_0, Y => - \counter_4[13]\); - - \counter_RNISLA11[20]\ : NOR3C - port map(A => un2_sample_in_val_15, B => - un2_sample_in_val_14, C => un2_sample_in_val_20, Y => - un2_sample_in_val_24); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_13); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[68]\ : DFN1E1 - port map(D => sample_f1(100), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(27)); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f1_wdata_70, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(70)); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_10); - - \counter_RNI3KVH2[10]\ : NOR2A - port map(A => sample_f1_val_0, B => un2_sample_in_val_i_0, - Y => sample_out_val_4); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => I_173_7, B => un2_sample_in_val_i_0, Y => - \counter_4[17]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - \sample_out[64]\ : DFN1E1 - port map(D => sample_f1(96), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(31)); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_13); - - \counter_RNITFBJ2[10]\ : NOR2B - port map(A => sample_out_val_4, B => rstn, Y => - sample_out_0_sqmuxa_2); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_8); - - \counter_RNIEHB5[27]\ : NOR3A - port map(A => un2_sample_in_val_1, B => \counter[11]_net_1\, - C => \counter[27]_net_1\, Y => un2_sample_in_val_14); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f1_wdata_68, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(68)); - - \counter_RNI5OV6[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un2_sample_in_val_7); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_7); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f1(90), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(37)); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_10); - - \counter_RNO[23]\ : NOR2B - port map(A => I_156_7, B => un2_sample_in_val_i_0, Y => - \counter_4[15]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f1(86), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(41)); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f1_wdata_52, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(52)); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f1(81), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(46)); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_9); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_14); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f1_wdata_3, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(3)); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_7); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f1_wdata_7, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(7)); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f1_wdata_5, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(5)); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_8); - - \counter_RNO[22]\ : NOR2B - port map(A => I_143_7, B => un2_sample_in_val_i_0, Y => - \counter_4[14]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f1_wdata_64, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(64)); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f1_wdata_59, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(59)); - - \counter_RNIG19I[24]\ : NOR3A - port map(A => un2_sample_in_val_13, B => \counter[1]_net_1\, - C => \counter[24]_net_1\, Y => un2_sample_in_val_20); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f1_wdata_11, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(11)); - - \counter_RNIMHBJ[10]\ : NOR3C - port map(A => un2_sample_in_val_5, B => un2_sample_in_val_4, - C => un2_sample_in_val_17, Y => un2_sample_in_val_22); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f1(95), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(32)); - - \sample_out[69]\ : DFN1E1 - port map(D => sample_f1(101), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(26)); - - \counter_RNIC8NG2[10]\ : OR3C - port map(A => un2_sample_in_val_23, B => - un2_sample_in_val_22, C => un2_sample_in_val_24, Y => - un2_sample_in_val_i_0); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f1_wdata_80, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(80)); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_8); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[75]\ : DFN1E1 - port map(D => sample_f1(107), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(20)); - - \counter_RNITFBJ2_1[10]\ : NOR2B - port map(A => sample_out_val_4, B => rstn, Y => - sample_out_0_sqmuxa); - - \counter_RNITFBJ2_2[10]\ : NOR2B - port map(A => sample_out_val_4, B => rstn, Y => - sample_out_0_sqmuxa_0); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_8); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f1_wdata_78, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(78)); - - \counter_RNO[18]\ : NOR2B - port map(A => I_115_8, B => un2_sample_in_val_i_0, Y => - \counter_4[10]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[77]\ : DFN1E1 - port map(D => sample_f1(109), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(18)); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f1(85), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(42)); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f1_wdata_67, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(67)); - - \counter_RNO[27]\ : NOR2B - port map(A => I_196_7, B => un2_sample_in_val_i_0, Y => - \counter_4[19]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f1(91), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(36)); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f1_wdata_71, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(71)); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f1_wdata_53, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(53)); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f1_wdata_55, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(55)); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f1_wdata_12, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(12)); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f1_wdata_6, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(6)); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => I_166_7, B => un2_sample_in_val_i_0, Y => - \counter_4[16]\); - - \counter[7]\ : DFN1E1C0 - port map(D => I_38_10, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_8); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f1_wdata_89, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(89)); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f1(94), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(33)); - - \counter_RNIVIL9[19]\ : NOR3A - port map(A => un2_sample_in_val_7, B => \counter[22]_net_1\, - C => \counter[19]_net_1\, Y => un2_sample_in_val_17); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f1(92), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(35)); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f1_wdata_60, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(60)); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f1_wdata_4, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(4)); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : NOR2B - port map(A => I_129_8, B => un2_sample_in_val_i_0, Y => - \counter_4[12]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f1_wdata_58, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(58)); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f1_wdata_72, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(72)); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f1(84), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(43)); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f1_wdata_66, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(66)); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f1(82), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(45)); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f1_wdata_77, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(77)); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f1_wdata_86, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(86)); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f1_wdata_88, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(88)); - - \sample_out[78]\ : DFN1E1 - port map(D => sample_f1(110), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(17)); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f1_wdata_81, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(81)); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f1_wdata_13, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(13)); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val, Q => \counter[9]_net_1\); - - \counter_RNIDD9B[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un2_sample_in_val_13); - - \sample_out[74]\ : DFN1E1 - port map(D => sample_f1(106), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(21)); - - \counter_RNI2807[10]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un2_sample_in_val_4); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f1_wdata_15, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(15)); - - \counter_RNO[19]\ : NOR2B - port map(A => I_122_8, B => un2_sample_in_val_i_0, Y => - \counter_4[11]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNINML2[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un2_sample_in_val_1); - - \counter_RNO[9]\ : NOR2B - port map(A => I_52_9, B => un2_sample_in_val_i_0, Y => - \counter_4[1]\); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[0]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_8); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_7); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val_0, Q => \counter[18]_net_1\); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f1_wdata_87, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(87)); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f1_wdata_54, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(54)); - - \counter_RNO[16]\ : NOR2B - port map(A => I_98_8, B => un2_sample_in_val_i_0, Y => - \counter_4[8]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_2, CLK => lclk_c, CLR => rstn, E => - sample_f1_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f1_wdata_49, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(49)); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f1_wdata_92, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(92)); - - \counter_RNIOQL2[18]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un2_sample_in_val_11); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_6_16_96 is - - port( sample_f0 : in std_logic_vector(111 downto 80); - sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f2_wdata : out std_logic_vector(95 downto 0); - sample_f0_val : in std_logic; - sample_f0_val_2 : in std_logic; - lclk_c : in std_logic; - sample_f2_val : out std_logic; - sample_f0_val_0 : in std_logic; - rstn : in std_logic - ); - -end Downsampling_6_16_96; - -architecture DEF_ARCH of Downsampling_6_16_96 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un6_sample_in_val_0, un6_sample_in_val_23, - un6_sample_in_val_22, un6_sample_in_val_24, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1, - sample_out_0_sqmuxa_0, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un6_sample_in_val_15, - un6_sample_in_val_14, un6_sample_in_val_20, - un6_sample_in_val_9, un6_sample_in_val_8, - un6_sample_in_val_19, un6_sample_in_val_5, - un6_sample_in_val_4, un6_sample_in_val_17, - un6_sample_in_val_13, \counter[24]_net_1\, - un6_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un6_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un6_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un6_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un6_sample_in_val, - sample_out_0_sqmuxa, \counter_4[20]\, I_196_6, - \counter_4[19]\, I_186_6, \counter_4[18]\, I_173_6, - \counter_4[17]\, I_166_6, \counter_4[16]\, I_156_6, - \counter_4[15]\, I_143_6, \counter_4[14]\, I_136_6, - \counter_4[13]\, I_129_7, \counter_4[12]\, I_122_7, - \counter_4[11]\, I_115_7, \counter_4[10]\, I_105_7, - \counter_4[9]\, I_98_7, \counter_4[8]\, I_91_7, - \counter_4[7]\, I_84_7, \counter_4[6]\, I_77_7, - \counter_4[5]\, I_73_7, \counter_4[4]\, I_66_9, - \counter_4[3]\, I_56_9, \counter_4[2]\, I_52_8, - \counter_4[1]\, I_45_8, \counter_4[0]\, I_38_9, - \counter_4_1[5]\, I_24_13, sample_out_val_9, I_4_1, - I_5_12, I_9_12, I_13_16, I_20_12, I_31_12, N_4, - \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_2, Q => \counter[19]_net_1\); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f0_wdata_73, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(73)); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f0_wdata_75, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(75)); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f0_wdata_82, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(82)); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f0_wdata_94, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(94)); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f0_wdata_76, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(76)); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f0(93), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(34)); - - \sample_out[66]\ : DFN1E1 - port map(D => sample_f0(98), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(29)); - - \sample_out[73]\ : DFN1E1 - port map(D => sample_f0(105), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(22)); - - \sample_out[79]\ : DFN1E1 - port map(D => sample_f0(111), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(16)); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f0_wdata_57, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(57)); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f0_wdata_0, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(0)); - - \counter_RNO[11]\ : NOR2B - port map(A => un6_sample_in_val, B => I_66_9, Y => - \counter_4[4]\); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f0_wdata_61, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(61)); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_1); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_6); - - \counter_RNO[15]\ : NOR2B - port map(A => un6_sample_in_val, B => I_91_7, Y => - \counter_4[8]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f0(83), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(44)); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f0(88), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(39)); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f0_wdata_95, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(95)); - - \counter_RNO[7]\ : NOR2B - port map(A => un6_sample_in_val, B => I_38_9, Y => - \counter_4[0]\); - - \counter[6]\ : DFN1E1C0 - port map(D => I_31_12, CLK => lclk_c, CLR => rstn, E => - sample_f0_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_16); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f0_wdata_14, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(14)); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f0_wdata_9, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(9)); - - \counter[3]\ : DFN1E1C0 - port map(D => I_13_16, CLK => lclk_c, CLR => rstn, E => - sample_f0_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_12, CLK => lclk_c, CLR => rstn, E => - sample_f0_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_7); - - \counter_RNO[8]\ : NOR2B - port map(A => un6_sample_in_val, B => I_45_8, Y => - \counter_4[1]\); - - \counter_RNO[13]\ : NOR2B - port map(A => un6_sample_in_val, B => I_77_7, Y => - \counter_4[6]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_8); - - \counter_RNIAMIV[27]\ : NOR3A - port map(A => un6_sample_in_val_1, B => \counter[11]_net_1\, - C => \counter[27]_net_1\, Y => un6_sample_in_val_14); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f0_wdata_83, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(83)); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f0_wdata_85, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(85)); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f0_wdata_50, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(50)); - - \counter_RNO[12]\ : NOR2B - port map(A => un6_sample_in_val, B => I_73_7, Y => - \counter_4[5]\); - - \sample_out[72]\ : DFN1E1 - port map(D => sample_f0(104), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(23)); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f0_wdata_62, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(62)); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f0_wdata_56, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(56)); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_2, Q => \counter[17]_net_1\); - - \sample_out[70]\ : DFN1E1 - port map(D => sample_f0(102), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(25)); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => I_20_12, CLK => lclk_c, CLR => rstn, E => - sample_f0_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_12); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f0_wdata_90, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(90)); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f0_wdata_48, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(48)); - - \counter_RNI812G2[20]\ : NOR3C - port map(A => un6_sample_in_val_15, B => - un6_sample_in_val_14, C => un6_sample_in_val_20, Y => - un6_sample_in_val_24); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \sample_out[65]\ : DFN1E1 - port map(D => sample_f0(97), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(30)); - - \counter_RNISODS5_1[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un6_sample_in_val_0, Y => sample_out_0_sqmuxa_2); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f0_wdata_74, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(74)); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f0_wdata_69, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(69)); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f0_wdata_93, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(93)); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[27]_net_1\); - - \counter_RNIC2EO5_0[4]\ : OR3C - port map(A => un6_sample_in_val_23, B => - un6_sample_in_val_22, C => un6_sample_in_val_24, Y => - un6_sample_in_val); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \sample_out[67]\ : DFN1E1 - port map(D => sample_f0(99), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(28)); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f0_wdata_1, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(1)); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_6); - - \counter_RNO[17]\ : NOR2B - port map(A => un6_sample_in_val, B => I_105_7, Y => - \counter_4[10]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[23]_net_1\); - - \counter_RNI17TR[19]\ : NOR3A - port map(A => un6_sample_in_val_7, B => \counter[22]_net_1\, - C => \counter[19]_net_1\, Y => un6_sample_in_val_17); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f0(87), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(40)); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_6); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f0_wdata_63, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(63)); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_7); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f0(89), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(38)); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f0_wdata_65, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(65)); - - \counter_RNO[14]\ : NOR2B - port map(A => un6_sample_in_val, B => I_84_7, Y => - \counter_4[7]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f0_wdata_10, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(10)); - - \counter_RNISODS5[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un6_sample_in_val_0, Y => sample_out_0_sqmuxa); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_12, CLK => lclk_c, CLR => rstn, E => - sample_f0_val_2, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_186_6, Y => - \counter_4[19]\); - - \counter_RNIQPQN1[7]\ : NOR3C - port map(A => un6_sample_in_val_5, B => un6_sample_in_val_4, - C => un6_sample_in_val_17, Y => un6_sample_in_val_22); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f0_wdata_91, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(91)); - - \counter_RNO[5]\ : NOR2B - port map(A => un6_sample_in_val, B => I_24_13, Y => - \counter_4_1[5]\); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[25]_net_1\); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_9, CLK => lclk_c, CLR => rstn, - Q => sample_f2_val); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f0_wdata_8, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(8)); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_7); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_6); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f0(80), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(47)); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_9); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f0_wdata_2, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(2)); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f0_wdata_84, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(84)); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f0_wdata_79, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(79)); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4_1[5]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f0_wdata_51, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(51)); - - \sample_out[71]\ : DFN1E1 - port map(D => sample_f0(103), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(24)); - - \sample_out[76]\ : DFN1E1 - port map(D => sample_f0(108), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(19)); - - \counter_RNIT54C[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un6_sample_in_val_3); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNI7MIV[12]\ : NOR3A - port map(A => un6_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un6_sample_in_val_19); - - \counter_RNO[10]\ : NOR2B - port map(A => un6_sample_in_val, B => I_56_9, Y => - \counter_4[3]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_12); - - \counter_RNO[21]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_136_6, Y => - \counter_4[14]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_12); - - \counter_RNIC2EO5[4]\ : OR3C - port map(A => un6_sample_in_val_23, B => - un6_sample_in_val_22, C => un6_sample_in_val_24, Y => - un6_sample_in_val_0); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[68]\ : DFN1E1 - port map(D => sample_f0(100), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(27)); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f0_wdata_70, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(70)); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_9); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_173_6, Y => - \counter_4[18]\); - - \counter_RNI6DPF[18]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un6_sample_in_val_11); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - \sample_out[64]\ : DFN1E1 - port map(D => sample_f0(96), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(31)); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_12); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_7); - - \counter_RNISODS5_0[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un6_sample_in_val_0, Y => sample_out_0_sqmuxa_0); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f0_wdata_68, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(68)); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_6); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f0(90), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(37)); - - \counter_RNIEQE8[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un6_sample_in_val_8); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_9); - - \counter_RNO[23]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_156_6, Y => - \counter_4[16]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f0(86), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(41)); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f0_wdata_52, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(52)); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f0(81), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(46)); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_8); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_13); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f0_wdata_3, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(3)); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_6); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f0_wdata_7, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(7)); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f0_wdata_5, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(5)); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_7); - - \counter_RNO[22]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_143_6, Y => - \counter_4[15]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f0_wdata_64, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(64)); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f0_wdata_59, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(59)); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \counter_RNIM94C[7]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un6_sample_in_val_4); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f0_wdata_11, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(11)); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f0(95), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(32)); - - \sample_out[69]\ : DFN1E1 - port map(D => sample_f0(101), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(26)); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f0_wdata_80, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(80)); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_7); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \counter_RNI7UD8[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un6_sample_in_val_13); - - \sample_out[75]\ : DFN1E1 - port map(D => sample_f0(107), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(20)); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_7); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f0_wdata_78, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(78)); - - \counter_RNO[18]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_115_7, Y => - \counter_4[11]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[77]\ : DFN1E1 - port map(D => sample_f0(109), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(18)); - - sample_out_val_RNO : NOR2A - port map(A => sample_f0_val_0, B => un6_sample_in_val, Y - => sample_out_val_9); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f0(85), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(42)); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f0_wdata_67, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(67)); - - \counter_RNO[27]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_196_6, Y => - \counter_4[20]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f0(91), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(36)); - - \counter_RNIPP3C[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un6_sample_in_val_7); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f0_wdata_71, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(71)); - - \counter_RNISODS5_2[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un6_sample_in_val_0, Y => sample_out_0_sqmuxa_1); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f0_wdata_53, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(53)); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f0_wdata_55, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(55)); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f0_wdata_12, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(12)); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f0_wdata_6, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(6)); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_166_6, Y => - \counter_4[17]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[0]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val, Q => \counter[7]_net_1\); - - \counter_RNI59PF[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un6_sample_in_val_1); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_7); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f0_wdata_89, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(89)); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f0(94), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(33)); - - \counter_RNILMF8[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un6_sample_in_val_9); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f0(92), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(35)); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \counter_RNI0NTR[20]\ : NOR3A - port map(A => un6_sample_in_val_3, B => \counter[23]_net_1\, - C => \counter[20]_net_1\, Y => un6_sample_in_val_15); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f0_wdata_60, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(60)); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f0_wdata_4, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(4)); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNIUJHK[24]\ : NOR3A - port map(A => un6_sample_in_val_13, B => \counter[1]_net_1\, - C => \counter[24]_net_1\, Y => un6_sample_in_val_20); - - \counter_RNI39PF[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un6_sample_in_val_5); - - \counter_RNO[20]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_129_7, Y => - \counter_4[13]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f0_wdata_58, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(58)); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f0_wdata_72, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(72)); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f0(84), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(43)); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f0_wdata_66, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(66)); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f0(82), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(45)); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f0_wdata_77, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(77)); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f0_wdata_86, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(86)); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f0_wdata_88, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(88)); - - \sample_out[78]\ : DFN1E1 - port map(D => sample_f0(110), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(17)); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f0_wdata_81, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(81)); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f0_wdata_13, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(13)); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val, Q => \counter[9]_net_1\); - - \sample_out[74]\ : DFN1E1 - port map(D => sample_f0(106), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(21)); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f0_wdata_15, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(15)); - - \counter_RNO[19]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_122_7, Y => - \counter_4[12]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : NOR2B - port map(A => un6_sample_in_val, B => I_52_8, Y => - \counter_4[2]\); - - \counter_RNIA7HG1[4]\ : NOR3C - port map(A => un6_sample_in_val_9, B => un6_sample_in_val_8, - C => un6_sample_in_val_19, Y => un6_sample_in_val_23); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_7); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_6); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_2, Q => \counter[18]_net_1\); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f0_wdata_87, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(87)); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f0_wdata_54, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(54)); - - \counter_RNO[16]\ : NOR2B - port map(A => un6_sample_in_val, B => I_98_7, Y => - \counter_4[9]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_1, CLK => lclk_c, CLR => rstn, E => - sample_f0_val_2, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f0_wdata_49, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(49)); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f0_wdata_92, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(92)); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_12 is - - port( sample_f1_wdata_95 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_0 : in std_logic; - data_f1_out : out std_logic_vector(159 downto 64); - sample_f1_37 : in std_logic; - sample_f1_5 : in std_logic; - sample_f1_38 : in std_logic; - sample_f1_6 : in std_logic; - sample_f1_39 : in std_logic; - sample_f1_7 : in std_logic; - sample_f1_40 : in std_logic; - sample_f1_8 : in std_logic; - sample_f1_41 : in std_logic; - sample_f1_9 : in std_logic; - sample_f1_42 : in std_logic; - sample_f1_10 : in std_logic; - sample_f1_43 : in std_logic; - sample_f1_11 : in std_logic; - sample_f1_61 : in std_logic; - sample_f1_62 : in std_logic; - sample_f1_63 : in std_logic; - sample_f1_32 : in std_logic; - sample_f1_0 : in std_logic; - sample_f1_33 : in std_logic; - sample_f1_1 : in std_logic; - sample_f1_34 : in std_logic; - sample_f1_2 : in std_logic; - sample_f1_35 : in std_logic; - sample_f1_3 : in std_logic; - sample_f1_36 : in std_logic; - sample_f1_4 : in std_logic; - sample_f1_48 : in std_logic; - sample_f1_49 : in std_logic; - sample_f1_50 : in std_logic; - sample_f1_51 : in std_logic; - sample_f1_52 : in std_logic; - sample_f1_53 : in std_logic; - sample_f1_54 : in std_logic; - sample_f1_55 : in std_logic; - sample_f1_56 : in std_logic; - sample_f1_57 : in std_logic; - sample_f1_58 : in std_logic; - sample_f1_59 : in std_logic; - sample_f1_60 : in std_logic; - sample_f1_44 : in std_logic; - sample_f1_12 : in std_logic; - sample_f1_45 : in std_logic; - sample_f1_13 : in std_logic; - sample_f1_46 : in std_logic; - sample_f1_14 : in std_logic; - sample_f1_47 : in std_logic; - sample_f1_15 : in std_logic; - nb_snapshot_param : in std_logic_vector(0 to 0); - rstn : in std_logic; - lclk_c : in std_logic; - data_f1_out_valid : out std_logic; - data_shaping_R1 : in std_logic; - data_shaping_R1_0 : in std_logic; - I_9_31 : in std_logic; - I_45_11 : in std_logic; - I_52_11 : in std_logic; - I_56_12 : in std_logic; - I_24_16 : in std_logic; - N_4 : in std_logic; - I_20_23 : in std_logic; - I_13_35 : in std_logic; - I_38_12 : in std_logic; - I_31_15 : in std_logic; - I_5_31 : in std_logic; - enable_f1 : in std_logic; - burst_f1 : in std_logic; - sample_f1_val_0 : in std_logic; - start_snapshot_f1 : in std_logic - ); - -end lpp_waveform_snapshot_160_12; - -architecture DEF_ARCH of lpp_waveform_snapshot_160_12 is - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal counter_points_snapshot_0_sqmuxa_1_0, N_47_2, - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, N_59, - N_47_1, N_47_0, ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I296_Y_0_0, - \counter_points_snapshot[16]_net_1\, - ADD_32x32_fast_I309_Y_0_0, - \un1_counter_points_snapshot[2]\, - ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, - ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, ADD_32x32_fast_I250_Y_2, - ADD_32x32_fast_I250_Y_0, N479, N546, - \un1_counter_points_snapshot[1]\, - ADD_32x32_fast_I295_Y_0_0, - \counter_points_snapshot[15]_net_1\, - ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I292_Y_0_0, - \counter_points_snapshot[12]_net_1\, - ADD_32x32_fast_I310_Y_0_0, ADD_32x32_fast_I252_Y_1, N550, - N543, ADD_32x32_fast_I252_Y_0, N483_i, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot_i[5]\, - ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I288_Y_0_0, - \un1_counter_points_snapshot_i[23]\, - ADD_32x32_fast_I254_Y_1, N626, N611, - ADD_32x32_fast_I254_Y_0, N547, N554, - ADD_32x32_fast_I256_Y_1, N630, N615, - ADD_32x32_fast_I256_Y_0, N558, N551, - ADD_32x32_fast_I300_Y_0_0, - \un1_counter_points_snapshot[11]\, - ADD_32x32_fast_I251_Y_3, ADD_32x32_fast_I251_Y_2, N620, - N481, ADD_32x32_fast_I251_Y_0, N548, - ADD_32x32_fast_I302_Y_0_0, - \un1_counter_points_snapshot[9]\, - ADD_32x32_fast_I301_Y_0_0, - \un1_counter_points_snapshot[10]\, - ADD_32x32_fast_I255_Y_0, N556, N549, - ADD_32x32_fast_I254_un1_Y_3, ADD_32x32_fast_I254_un1_Y_1, - ADD_32x32_fast_I254_un1_Y_0, N420, N423, N512, N504, N500, - ADD_32x32_fast_I294_Y_0_0, - \counter_points_snapshot[14]_net_1\, - ADD_32x32_fast_I293_Y_0_0, - \counter_points_snapshot[13]_net_1\, - ADD_32x32_fast_I252_un1_Y_0, N496, N567, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot_i[12]\, - ADD_32x32_fast_I256_un1_Y_2, ADD_32x32_fast_I256_un1_Y_0, - \un1_counter_points_snapshot_i[21]\, - \un1_counter_points_snapshot[22]\, - ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I289_Y_0_0, ADD_32x32_fast_I255_un1_Y_7, - ADD_32x32_fast_I255_un1_Y_5, ADD_32x32_fast_I255_un1_Y_4, - N613, ADD_32x32_fast_I255_un1_Y_3, N429, N417, - ADD_32x32_fast_I255_un1_Y_1, - \un1_counter_points_snapshot[20]\, N426, - ADD_32x32_fast_I286_Y_0_0, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I290_Y_0_0, ADD_32x32_fast_I284_Y_0_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I263_Y_0, N533, N644, - ADD_32x32_fast_I283_Y_0_0, - \un1_counter_points_snapshot_i[28]\, - ADD_32x32_fast_I161_Y_1, ADD_32x32_fast_I161_Y_0, - ADD_32x32_fast_I126_Y_1, N419, ADD_32x32_fast_I126_Y_0, - N416, ADD_32x32_fast_I134_Y_1, N401, - ADD_32x32_fast_I134_Y_0, ADD_32x32_fast_I118_Y_1, N425, - ADD_32x32_fast_I118_Y_0, N422, N428, - ADD_32x32_fast_I103_Y_1, ADD_32x32_fast_I103_Y_0, - ADD_32x32_fast_I110_Y_0, data_out_valid_9_i_0, - un1_data_in_validlt30_27, un1_data_in_validlt30_18, - un1_data_in_validlt30_17, un1_data_in_validlt30_23, - un1_data_in_validlt30_26, un1_data_in_validlt30_12, - un1_data_in_validlt30_11, un1_data_in_validlt30_22, - un1_data_in_validlt30_25, un1_data_in_validlt30_8, - un1_data_in_validlt30_7, un1_data_in_validlt30_20, - un1_data_in_validlt30_2, un1_data_in_validlt30_1, - un1_data_in_validlt30_15, un1_data_in_validlt30_14, - \counter_points_snapshot[27]_net_1\, - \counter_points_snapshot[26]_net_1\, - un1_data_in_validlt30_10, - \counter_points_snapshot[19]_net_1\, - \counter_points_snapshot[18]_net_1\, - un1_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un1_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[30]_net_1\, - \counter_points_snapshot[28]_net_1\, - \counter_points_snapshot[29]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[22]_net_1\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[20]_net_1\, - \counter_points_snapshot[21]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, N758, N638, N622, - N654, N740, N774, N756, N636, N652, - \un1_data_out_valid_0_sqmuxa_2[7]\, - \un1_counter_points_snapshot[24]\, N650_i, - \un1_data_out_valid_0_sqmuxa_2[6]\, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, N380, N434, N437, N744, - N485, N752, \un1_data_out_valid_0_sqmuxa_2[3]\, N594, - un1_data_in_validlto30_i, N738, N618, N_57, N766, N646, - N754, N634, N762, N642, - \un1_data_out_valid_0_sqmuxa_2[10]\, - \un1_data_out_valid_0_sqmuxa_2[11]\, N783, N492, N572, - N588, N529, N395, N392, N764, N628, I255_un1_Y, - \un1_data_out_valid_0_sqmuxa_2[8]\, N_52, N_60, N_49, - N_47, counter_points_snapshot_0_sqmuxa_1, N750, - I256_un1_Y_i, N789, N746, N742, I208_un1_Y, - ADD_32x32_fast_I252_un1_Y, N607, N777_i, - \un1_data_out_valid_0_sqmuxa_2[9]\, - \un1_data_out_valid_0_sqmuxa_2[4]\, - \un1_data_out_valid_0_sqmuxa_2[5]\, - \un1_counter_points_snapshot[26]\, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_counter_points_snapshot_i[29]\, N748, I214_un1_Y, - ADD_32x32_fast_I97_Y_0_tz, N484, N499, N495, N566, N503, - N511, N515, N_273, counter_points_snapshot_2_sqmuxa, - N_278, N_279, \counter_points_snapshot_10[1]\, - \counter_points_snapshot_10[6]\, - \counter_points_snapshot_10[7]\, N_9, N_25, N_43, N_23, - N760, N_21, N443, N_39, N446, - \counter_points_snapshot_10[3]\, N_275, N_45, N527, N531, - N582, N_17, N_13, N_11, N578, N570, N487, N488, N449, - N_27, N_31, N_19, \counter_points_snapshot_10[11]\, N_283, - \counter_points_snapshot_10[10]\, N_282, N586, N523_i, - N519_i, \un1_counter_points_snapshot[31]\, - \un1_data_out_valid_0_sqmuxa_2[0]\, N_272, - \counter_points_snapshot_10[0]\, N_280, - \counter_points_snapshot_10[8]\, \sample_f1_wdata[32]\, - \sample_f1_wdata[33]\, \sample_f1_wdata[34]\, - \sample_f1_wdata[35]\, \sample_f1_wdata[19]\, - \sample_f1_wdata[20]\, \sample_f1_wdata[21]\, - \sample_f1_wdata[22]\, \sample_f1_wdata[23]\, - \sample_f1_wdata[24]\, \sample_f1_wdata[25]\, - \sample_f1_wdata[26]\, \sample_f1_wdata[27]\, - \sample_f1_wdata[28]\, \sample_f1_wdata[29]\, - \sample_f1_wdata[30]\, \sample_f1_wdata[31]\, - \sample_f1_wdata[43]\, \sample_f1_wdata[44]\, - \sample_f1_wdata[45]\, \sample_f1_wdata[46]\, - \sample_f1_wdata[47]\, \sample_f1_wdata[16]\, - \sample_f1_wdata[17]\, \sample_f1_wdata[18]\, - \sample_f1_wdata[36]\, \sample_f1_wdata[37]\, - \sample_f1_wdata[38]\, \sample_f1_wdata[39]\, - \sample_f1_wdata[40]\, \sample_f1_wdata[41]\, - \sample_f1_wdata[42]\, N_29, N_37, N_33, N_41, N_15, N768, - N_7, N780_i, N_281, \counter_points_snapshot_10[9]\, - N_276, \counter_points_snapshot_10[4]\, N_277, - \counter_points_snapshot_10[5]\, N_35, - \counter_points_snapshot_10[2]\, N_274, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y : OA1 - port map(A => N533, B => N644, C => - ADD_32x32_fast_I255_un1_Y_7, Y => I255_un1_Y); - - \counter_points_snapshot_RNILOM6[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un1_data_in_validlt30_14); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => N_9, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : AX1A - port map(A => N533, B => N529, C => - ADD_32x32_fast_I284_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - \counter_points_snapshot_RNI6U3D[20]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[20]_net_1\, Y => - \un1_counter_points_snapshot[11]\); - - \data_out[110]\ : DFN1C0 - port map(D => \sample_f1_wdata[46]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(110)); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[10]\, B => - I_56_12, S => counter_points_snapshot_2_sqmuxa, Y => - N_282); - - \counter_points_snapshot_RNO[27]\ : XA1B - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - N_52, Y => N_37); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => N_39, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[28]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y_0 : - OR3 - port map(A => N496, B => N500, C => N567, Y => - ADD_32x32_fast_I252_un1_Y_0); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762, B => ADD_32x32_fast_I299_Y_0_0, C => - N_52, Y => N_21); - - \counter_points_snapshot_RNIF38F3[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_0); - - \data_out_RNO[96]\ : MX2 - port map(A => sample_f1_15, B => sample_f1_47, S => - data_shaping_R1_0, Y => \sample_f1_wdata[32]\); - - \data_out[91]\ : DFN1C0 - port map(D => \sample_f1_wdata[27]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(91)); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f1_wdata_56, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1C - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - N_52, Y => N_31); - - \counter_points_snapshot_RNIG2MI[0]\ : NOR3C - port map(A => un1_data_in_validlt30_2, B => - un1_data_in_validlt30_1, C => un1_data_in_validlt30_15, Y - => un1_data_in_validlt30_23); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : AOI1 - port map(A => ADD_32x32_fast_I254_un1_Y_3, B => N783, C => - ADD_32x32_fast_I254_Y_1, Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : NOR2 - port map(A => N586, B => N578, Y => N642); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I101_Y : OR2A - port map(A => N484, B => N488, Y => N547); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f1_wdata_66, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => \sample_f1_wdata[40]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : OR3C - port map(A => N443, B => N446, C => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => I_20_23, B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => N_60, Y => N_276); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[1]\, B => - I_5_31, S => counter_points_snapshot_2_sqmuxa, Y => N_273); - - \counter_points_snapshot_RNIF38F3_2[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47); - - \counter_points_snapshot_RNI9U3D[23]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - \data_out[102]\ : DFN1C0 - port map(D => \sample_f1_wdata[38]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3C - port map(A => I208_un1_Y, B => ADD_32x32_fast_I252_Y_1, C - => ADD_32x32_fast_I252_un1_Y, Y => N742); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_279, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[2]\, B => N_47_0, - Y => ADD_32x32_fast_I309_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_P0N : AOI1B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[15]_net_1\, C => N_47_2, Y => - N426); - - \counter_points_snapshot_RNO[12]\ : XA1C - port map(A => N780_i, B => ADD_32x32_fast_I292_Y_0_0, C => - N_52, Y => N_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : OR2B - port map(A => N650_i, B => N634, Y => N_57); - - \data_out[93]\ : DFN1C0 - port map(D => \sample_f1_wdata[29]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(93)); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[4]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_5 : - NOR3B - port map(A => N423, B => ADD_32x32_fast_I255_un1_Y_3, C => - N429, Y => ADD_32x32_fast_I255_un1_Y_5); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_1 : - AOI1 - port map(A => \un1_counter_points_snapshot_i[21]\, B => - N_47_1, C => N426, Y => ADD_32x32_fast_I255_un1_Y_1); - - \counter_points_snapshot_RNI20DD[10]\ : NOR3A - port map(A => un1_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un1_data_in_validlt30_18); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - N_47_0, Y => ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f1_wdata_95, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => \sample_f1_wdata[41]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(105)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I16_P0N : AOI1B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[16]_net_1\, C => N_47_2, Y => - N429); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f1_wdata_77, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y_2 : - NOR3A - port map(A => ADD_32x32_fast_I256_un1_Y_0, B => N512, C => - N567, Y => ADD_32x32_fast_I256_un1_Y_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR3C - port map(A => N443, B => N446, C => N495, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2A - port map(A => N523_i, B => N527, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => \sample_f1_wdata[17]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(81)); - - counter_points_snapshot_10_12_i_o2 : OR3B - port map(A => enable_f1, B => N_60, C => burst_f1, Y => - N_52); - - \data_out_RNO[99]\ : MX2 - port map(A => sample_f1_12, B => sample_f1_44, S => - data_shaping_R1_0, Y => \sample_f1_wdata[35]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[1]\, B => N_47_0, - Y => ADD_32x32_fast_I310_Y_0_0); - - \data_out_RNO[104]\ : MX2 - port map(A => sample_f1_7, B => sample_f1_39, S => - data_shaping_R1, Y => \sample_f1_wdata[40]\); - - \counter_points_snapshot_RNISS2K[5]\ : MX2 - port map(A => I_24_16, B => - \counter_points_snapshot[5]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[26]\); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : AOI1 - port map(A => N558, B => N551, C => N550, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - NOR2A - port map(A => N425, B => N_57, Y => N768); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f1_wdata_50, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I97_Y : OA1A - port map(A => N_47_2, B => ADD_32x32_fast_I97_Y_0_tz, C => - N484, Y => N543); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : NOR2 - port map(A => N578, B => N570, Y => N634); - - \counter_points_snapshot_RNIBQ3D[18]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : NOR3C - port map(A => N419, B => N422, C => N503, Y => N566); - - \counter_points_snapshot_RNIT045[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un1_data_in_validlt30_2); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => N_37, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f1_wdata_79, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_4 : - NOR3C - port map(A => N420, B => N417, C => - ADD_32x32_fast_I255_un1_Y_1, Y => - ADD_32x32_fast_I255_un1_Y_4); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : OR3 - port map(A => N527, B => N531, C => N533, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3A - port map(A => ADD_32x32_fast_I110_Y_0, B => N434, C => N437, - Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f1_wdata_48, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f1_wdata_60, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(124)); - - \counter_points_snapshot_RNIJSFH[3]\ : MX2C - port map(A => I_13_35, B => - \counter_points_snapshot[3]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot_i[28]\); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f1_wdata_70, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : OA1B - port map(A => N_47, B => \un1_counter_points_snapshot[25]\, - C => N395, Y => N523_i); - - \counter_points_snapshot_RNO[28]\ : XA1C - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - N_52, Y => N_39); - - \data_out[83]\ : DFN1C0 - port map(D => \sample_f1_wdata[19]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I250_Y_0, B => N479, C => N546, - Y => ADD_32x32_fast_I250_Y_2); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f1_wdata_58, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f1_wdata_51, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(115)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : OA1B - port map(A => N_47_2, B => \un1_counter_points_snapshot[7]\, - C => N449, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : - AO1A - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot_i[5]\, C => N_47_2, Y => - N481); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : NOR2B - port map(A => N422, B => N428, Y => ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f1_wdata_68, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(132)); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => N_43, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[30]_net_1\); - - \counter_points_snapshot_RNI5155[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un1_data_in_validlt30_4); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I69_Y : AO1B - port map(A => \un1_counter_points_snapshot[20]\, B => N_47, - C => N417, Y => N512); - - \data_out[96]\ : DFN1C0 - port map(D => \sample_f1_wdata[32]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(96)); - - \counter_points_snapshot_RNI69QQ[14]\ : NOR3C - port map(A => un1_data_in_validlt30_8, B => - un1_data_in_validlt30_7, C => un1_data_in_validlt30_20, Y - => un1_data_in_validlt30_25); - - \counter_points_snapshot_RNIDCJD[0]\ : MX2A - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : NOR3 - port map(A => I214_un1_Y, B => ADD_32x32_fast_I255_Y_0, C - => I255_un1_Y, Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[14]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f1_wdata_61, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(125)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f1_wdata_71, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(135)); - - \data_out_RNO[87]\ : NOR2B - port map(A => sample_f1_56, B => data_shaping_R1_0, Y => - \sample_f1_wdata[23]\); - - \data_out_RNO[108]\ : MX2 - port map(A => sample_f1_3, B => sample_f1_35, S => - data_shaping_R1, Y => \sample_f1_wdata[44]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_G0N : OR3B - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47_2, Y => - N425); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0_0 : - XOR2 - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[21]\, Y => - ADD_32x32_fast_I290_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : OR3C - port map(A => N481, B => N485, C => N752, Y => N744); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y_1 : - NOR3B - port map(A => N420, B => N423, C => N512, Y => - ADD_32x32_fast_I254_un1_Y_1); - - \counter_points_snapshot_RNIBHF53[31]\ : AO1D - port map(A => un1_data_in_validlto30_i, B => - \counter_points_snapshot[31]_net_1\, C => - start_snapshot_f1, Y => N_59); - - \counter_points_snapshot_RNI924D[30]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[30]_net_1\, Y => - \un1_counter_points_snapshot[1]\); - - data_out_valid : DFN1C0 - port map(D => N_49, CLK => lclk_c, CLR => rstn, Q => - data_f1_out_valid); - - \data_out_RNO[90]\ : NOR2B - port map(A => sample_f1_53, B => data_shaping_R1_0, Y => - \sample_f1_wdata[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : NOR3B - port map(A => N499, B => N503, C => N570, Y => N626); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f1_wdata_7, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f1_wdata_1, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => N_19, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : OR3A - port map(A => N638, B => N622, C => N654, Y => N758); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I45_Y : OA1 - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[8]\, C => N_47, Y => N488); - - \data_out_RNO[98]\ : MX2 - port map(A => sample_f1_13, B => sample_f1_45, S => - data_shaping_R1_0, Y => \sample_f1_wdata[34]\); - - \data_out[86]\ : DFN1C0 - port map(D => \sample_f1_wdata[22]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot_i[23]\, B => - N_47_0, Y => ADD_32x32_fast_I288_Y_0_0); - - \counter_points_snapshot_RNIF38F3_1[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : NOR3B - port map(A => N499, B => N503, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f1_wdata_86, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(150)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_0, Y => ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[16]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f1_wdata_84, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(148)); - - GND_i : GND - port map(Y => \GND\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I49_Y : OA1A - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_counter_points_snapshot[10]\, C => N_47_2, Y => N492); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_7 : - NOR3C - port map(A => ADD_32x32_fast_I255_un1_Y_5, B => - ADD_32x32_fast_I255_un1_Y_4, C => N613, Y => - ADD_32x32_fast_I255_un1_Y_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_G0N : OR3B - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47_2, Y => - N419); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[8]_net_1\); - - \counter_points_snapshot_RNIQGE8[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[30]_net_1\, Y => - un1_data_in_validlt30_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I61_Y : NOR2 - port map(A => N429, B => N426, Y => N504); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : OR3C - port map(A => N511, B => N515, C => N566, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR2B - port map(A => N523_i, B => N519_i, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f1_wdata_9, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot_i[28]\, B => - N_47_1, Y => ADD_32x32_fast_I283_Y_0_0); - - \data_out[92]\ : DFN1C0 - port map(D => \sample_f1_wdata[28]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f1_wdata_3, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => \sample_f1_wdata[43]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I14_G0N : OR3B - port map(A => \counter_points_snapshot[14]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47_2, Y => - N422); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OR2 - port map(A => N533, B => N644, Y => ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_278, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : AX1D - port map(A => N533, B => N644, C => - ADD_32x32_fast_I290_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => N_41, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[29]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_3 : NOR2A - port map(A => ADD_32x32_fast_I251_Y_2, B => N620, Y => - ADD_32x32_fast_I251_Y_3); - - \counter_points_snapshot_RNIS1RQ[22]\ : NOR3C - port map(A => un1_data_in_validlt30_12, B => - un1_data_in_validlt30_11, C => un1_data_in_validlt30_22, - Y => un1_data_in_validlt30_26); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I161_Y_1 : AO1C - port map(A => \un1_counter_points_snapshot[10]\, B => - \un1_counter_points_snapshot[11]\, C => N_47_1, Y => - ADD_32x32_fast_I161_Y_1); - - \data_out_RNO[94]\ : NOR2B - port map(A => sample_f1_49, B => data_shaping_R1_0, Y => - \sample_f1_wdata[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[11]\, B => - N_47_0, Y => ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1C - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - N_52, Y => N_33); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => N_23, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[9]\, B => N_47_0, - Y => ADD_32x32_fast_I302_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y_0 : - AO1C - port map(A => \un1_counter_points_snapshot_i[21]\, B => - \un1_counter_points_snapshot[22]\, C => N_47_0, Y => - ADD_32x32_fast_I256_un1_Y_0); - - \data_out_RNO[95]\ : NOR2B - port map(A => sample_f1_48, B => data_shaping_R1, Y => - \sample_f1_wdata[31]\); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => N_17, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : OR3 - port map(A => N527, B => N531, C => N582, Y => N646); - - \counter_points_snapshot_RNIM4UQ[10]\ : MX2C - port map(A => I_56_12, B => - \counter_points_snapshot[10]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot_i[21]\); - - \counter_points_snapshot_RNI9TLM[7]\ : MX2C - port map(A => I_38_12, B => - \counter_points_snapshot[7]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : OA1C - port map(A => \un1_counter_points_snapshot_i[29]\, B => - \un1_counter_points_snapshot[30]\, C => N_47, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[12]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : OR3B - port map(A => N618, B => ADD_32x32_fast_I250_Y_2, C => N_57, - Y => N738); - - \data_out_RNO[93]\ : NOR2B - port map(A => sample_f1_50, B => data_shaping_R1_0, Y => - \sample_f1_wdata[29]\); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f1_wdata_90, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(154)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - OR3A - port map(A => N764, B => N434, C => N437, Y => N760); - - \data_out[82]\ : DFN1C0 - port map(D => \sample_f1_wdata[18]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f1_wdata_53, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1C - port map(A => N760, B => ADD_32x32_fast_I300_Y_0_0, C => - N_52, Y => N_23); - - \counter_points_snapshot_RNIQV103[6]\ : NOR3C - port map(A => un1_data_in_validlt30_26, B => - un1_data_in_validlt30_25, C => un1_data_in_validlt30_27, - Y => un1_data_in_validlto30_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : AO1A - port map(A => N547, B => N554, C => N546, Y => - ADD_32x32_fast_I254_Y_0); - - \counter_points_snapshot_RNI7GM6[14]\ : NOR2 - port map(A => \counter_points_snapshot[14]_net_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - un1_data_in_validlt30_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I41_Y : AO1C - port map(A => \un1_counter_points_snapshot_i[5]\, B => - \un1_counter_points_snapshot[6]\, C => N_47_2, Y => N484); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f1_wdata_12, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f1_wdata_88, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(152)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_1 : OA1A - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_1, C => N425, Y => ADD_32x32_fast_I118_Y_1); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f1_wdata_85, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(149)); - - \counter_points_snapshot_RNI3GM6[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un1_data_in_validlt30_6); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f1_wdata_63, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : NOR2A - port map(A => N638, B => N654, Y => N777_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : NOR2 - port map(A => N652, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2 - port map(A => N588, B => N533, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f1_wdata_73, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(137)); - - \data_out_RNO[81]\ : NOR2B - port map(A => sample_f1_62, B => data_shaping_R1, Y => - \sample_f1_wdata[17]\); - - \counter_points_snapshot_RNIDOM6[24]\ : NOR2 - port map(A => \counter_points_snapshot[24]_net_1\, B => - \counter_points_snapshot[25]_net_1\, Y => - un1_data_in_validlt30_12); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f1_wdata_91, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(155)); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_277, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1B - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - N_52, Y => N_17); - - data_out_valid_RNO_0 : NOR2B - port map(A => enable_f1, B => sample_f1_val_0, Y => - data_out_valid_9_i_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I121_Y : OR3C - port map(A => N420, B => N423, C => N504, Y => N567); - - \data_out[90]\ : DFN1C0 - port map(D => \sample_f1_wdata[26]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_0 : OA1B - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[21]\, C => N416, Y => - ADD_32x32_fast_I126_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR3C - port map(A => N419, B => N422, C => N511, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR2B - port map(A => ADD_32x32_fast_I251_Y_3, B => N774, Y => N740); - - \counter_points_snapshot_RNO[14]\ : XA1B - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - N_52, Y => N_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR2B - port map(A => N519_i, B => N515, Y => N578); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[29]\, C => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - \data_out_RNO[92]\ : NOR2B - port map(A => sample_f1_51, B => data_shaping_R1_0, Y => - \sample_f1_wdata[28]\); - - counter_points_snapshot_2_sqmuxa_0_a2 : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_60, Y => - counter_points_snapshot_2_sqmuxa); - - \data_out[99]\ : DFN1C0 - port map(D => \sample_f1_wdata[35]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(99)); - - \data_out_RNO[100]\ : MX2 - port map(A => sample_f1_11, B => sample_f1_43, S => - data_shaping_R1, Y => \sample_f1_wdata[36]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I76_Y : OA1B - port map(A => N_47, B => - \un1_counter_points_snapshot_i[23]\, C => N401, Y => - N519_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : OR3C - port map(A => N618, B => N634, C => N650_i, Y => N754); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I12_P0N : AO1B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[12]_net_1\, C => N_47, Y => N417); - - \data_out[106]\ : DFN1C0 - port map(D => \sample_f1_wdata[42]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1B - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - N_52, Y => N_25); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_0 : AO1D - port map(A => \un1_counter_points_snapshot[2]\, B => - \un1_counter_points_snapshot[1]\, C => N_47_0, Y => - ADD_32x32_fast_I250_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y : - OR3C - port map(A => N615, B => ADD_32x32_fast_I256_un1_Y_2, C => - N789, Y => I256_un1_Y_i); - - \data_out_RNO[103]\ : MX2 - port map(A => sample_f1_8, B => sample_f1_40, S => - data_shaping_R1, Y => \sample_f1_wdata[39]\); - - \data_out[98]\ : DFN1C0 - port map(D => \sample_f1_wdata[34]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(98)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y_3 : - NOR3C - port map(A => ADD_32x32_fast_I254_un1_Y_1, B => - ADD_32x32_fast_I254_un1_Y_0, C => N611, Y => - ADD_32x32_fast_I254_un1_Y_3); - - \data_out[80]\ : DFN1C0 - port map(D => \sample_f1_wdata[16]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f1_wdata_8, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : OR2B - port map(A => ADD_32x32_fast_I256_Y_1, B => I256_un1_Y_i, Y - => N750); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_G0N : OR2A - port map(A => \un1_counter_points_snapshot[9]\, B => N_47, - Y => N446); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AO1A - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47_2, Y => N499); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : AX1A - port map(A => N401, B => N650_i, C => - ADD_32x32_fast_I288_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - \data_out_RNO[107]\ : MX2 - port map(A => sample_f1_4, B => sample_f1_36, S => - data_shaping_R1, Y => \sample_f1_wdata[43]\); - - counter_points_snapshot_2_sqmuxa_0_a2_0 : OR2A - port map(A => start_snapshot_f1, B => sample_f1_val_0, Y - => N_60); - - \data_out[89]\ : DFN1C0 - port map(D => \sample_f1_wdata[25]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(89)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : NOR2 - port map(A => ADD_32x32_fast_I263_Y_0, B => N628, Y => N764); - - \counter_points_snapshot_RNICQ3D[19]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot_i[12]\); - - \counter_points_snapshot_RNINCPI[4]\ : MX2C - port map(A => I_20_23, B => - \counter_points_snapshot[4]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[27]\); - - counter_points_snapshot_0_sqmuxa_1_0_a2 : OR3B - port map(A => start_snapshot_f1, B => sample_f1_val_0, C - => burst_f1, Y => counter_points_snapshot_0_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I289_Y_0_0, B => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out_RNO[101]\ : MX2 - port map(A => sample_f1_10, B => sample_f1_42, S => - data_shaping_R1, Y => \sample_f1_wdata[37]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f1_wdata_52, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => N_21, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => I_9_31, B => - \un1_data_out_valid_0_sqmuxa_2[2]\, S => N_60, Y => N_274); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - N_47_1, Y => ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I16_G0N : OR3B - port map(A => \counter_points_snapshot[16]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_2, Y => - N428); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : NOR2 - port map(A => N594, B => N586, Y => N650_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[26]\, C => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1B - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - N_52, Y => N_19); - - \counter_points_snapshot_RNIDU3D[27]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - \data_out[88]\ : DFN1C0 - port map(D => \sample_f1_wdata[24]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XNOR2 - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f1_wdata_62, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => \sample_f1_wdata[30]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f1_wdata_76, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f1_wdata_72, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(136)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I14_P0N : AO1B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[14]_net_1\, C => N_47_2, Y => - N423); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I293_Y_0_0); - - \un1_data_out_valid_0_sqmuxa_1_i_0[31]\ : AOI1B - port map(A => start_snapshot_f1, B => burst_f1, C => - sample_f1_val_0, Y => - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I208_un1_Y : - OR2A - port map(A => N622, B => N607, Y => I208_un1_Y); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => N_27, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[22]_net_1\); - - \data_out_RNO[86]\ : NOR2B - port map(A => sample_f1_57, B => data_shaping_R1_0, Y => - \sample_f1_wdata[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2A - port map(A => N380, B => N531, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => N_47_0, - Y => ADD_32x32_fast_I304_Y_0_0); - - \data_out[101]\ : DFN1C0 - port map(D => \sample_f1_wdata[37]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(101)); - - \counter_points_snapshot_RNI8U3D[22]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[22]_net_1\, Y => - \un1_counter_points_snapshot[9]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I102_Y : OR3B - port map(A => N446, B => N485, C => N449, Y => N548); - - \counter_points_snapshot_RNI9OM6[22]\ : NOR2 - port map(A => \counter_points_snapshot[22]_net_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - un1_data_in_validlt30_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_P0N : AO1B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[13]_net_1\, C => N_47_2, Y => - N420); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I155_Y : OR2B - port map(A => N551, B => N543, Y => N607); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f1_wdata_93, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_276, Y => - \counter_points_snapshot_10[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I163_Y : NOR3A - port map(A => N551, B => N496, C => N500, Y => N615); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot[10]\, C => N_47_1, Y => - ADD_32x32_fast_I110_Y_0); - - \counter_points_snapshot_RNO[30]\ : XA1C - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - N_52, Y => N_43); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[6]_net_1\); - - \counter_points_snapshot_RNIQT8P[9]\ : MX2 - port map(A => I_52_11, B => - \counter_points_snapshot[9]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR3B - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N572, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot_i[23]\, B => - \un1_counter_points_snapshot[25]\, C => N_47_1, Y => - ADD_32x32_fast_I134_Y_0); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f1_wdata_6, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => I_24_16, B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => N_60, Y => N_277); - - \counter_points_snapshot_RNIAU3D[24]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - \data_out[84]\ : DFN1C0 - port map(D => \sample_f1_wdata[20]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => \sample_f1_wdata[39]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I7_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[24]\, B => - N_47_2, Y => N401); - - \counter_points_snapshot_RNIPG35[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un1_data_in_validlt30_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : AOI1 - port map(A => \un1_counter_points_snapshot_i[28]\, B => - \un1_counter_points_snapshot[27]\, C => N_47, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - N_52, Y => N_35); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0_0 : - XOR2 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, Y => - ADD_32x32_fast_I289_Y_0_0); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f1_wdata_15, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(79)); - - \counter_points_snapshot_RNIFU3D[29]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[29]_net_1\, Y => - \un1_counter_points_snapshot[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \counter_points_snapshot_RNIAQ3D[17]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f1_wdata_80, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(144)); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0 : OR3B - port map(A => start_snapshot_f1, B => sample_f1_val_0, C - => burst_f1, Y => counter_points_snapshot_0_sqmuxa_1_0); - - \data_out_RNO[89]\ : NOR2B - port map(A => sample_f1_54, B => data_shaping_R1_0, Y => - \sample_f1_wdata[25]\); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_280, Y => - \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => \sample_f1_wdata[47]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I105_Y : NOR2 - port map(A => N492, B => N488, Y => N551); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2A - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f1_wdata_78, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f1_wdata_14, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - N_52, Y => N_29); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : OR3 - port map(A => ADD_32x32_fast_I134_Y_0, B => - ADD_32x32_fast_I134_Y_1, C => N572, Y => N636); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_1 : AO1A - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, C => N401, Y => - ADD_32x32_fast_I134_Y_1); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => I_13_35, B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => N_60, Y => N_275); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => N_35, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => N_47_0, - Y => ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : AOI1B - port map(A => N550, B => N543, C => ADD_32x32_fast_I252_Y_0, - Y => ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y_1 : AO1B - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_counter_points_snapshot[6]\, C => N_47_1, Y => - ADD_32x32_fast_I103_Y_1); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f1_wdata_57, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : NOR2B - port map(A => N428, B => N425, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_272, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f1_wdata_67, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f1_wdata_49, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(113)); - - \counter_points_snapshot_RNIF38F3_0[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_1); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f1_wdata_81, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(145)); - - \counter_points_snapshot_RNIOKCA1[6]\ : NOR3C - port map(A => un1_data_in_validlt30_18, B => - un1_data_in_validlt30_17, C => un1_data_in_validlt30_23, - Y => un1_data_in_validlt30_27); - - \counter_points_snapshot_RNI6HDD[26]\ : NOR3A - port map(A => un1_data_in_validlt30_14, B => - \counter_points_snapshot[27]_net_1\, C => - \counter_points_snapshot[26]_net_1\, Y => - un1_data_in_validlt30_22); - - \counter_points_snapshot_RNIBGM6[17]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un1_data_in_validlt30_8); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f1_wdata_2, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[1]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_1 : AO1A - port map(A => N626, B => N611, C => ADD_32x32_fast_I254_Y_0, - Y => ADD_32x32_fast_I254_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y_0 : OAI1 - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => N_47_1, Y => - ADD_32x32_fast_I103_Y_0); - - \counter_points_snapshot_RNO[31]\ : XA1B - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - N_52, Y => N_45); - - \data_out_RNO[109]\ : MX2 - port map(A => sample_f1_2, B => sample_f1_34, S => - data_shaping_R1, Y => \sample_f1_wdata[45]\); - - \counter_points_snapshot_RNO_0[0]\ : MX2B - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => N_60, Y => N_272); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N_57, B => ADD_32x32_fast_I295_Y_0_0, C => - N_52, Y => N_13); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f1_wdata_59, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(123)); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f1_wdata_69, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : OR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - N_47_2, Y => N443); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I4_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => N_47, - Y => N392); - - \counter_points_snapshot_RNO[29]\ : XA1C - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - N_52, Y => N_41); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => N_45, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : OA1B - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_counter_points_snapshot[4]\, C => N_47_2, Y => N479); - - \data_out_RNO[97]\ : MX2 - port map(A => sample_f1_14, B => sample_f1_46, S => - data_shaping_R1_0, Y => \sample_f1_wdata[33]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_1 : AOI1B - port map(A => N630, B => N615, C => ADD_32x32_fast_I256_Y_0, - Y => ADD_32x32_fast_I256_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I19_G0N : NOR2 - port map(A => \un1_counter_points_snapshot_i[12]\, B => - N_47_2, Y => N437); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f1_wdata_10, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(74)); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_282, Y => - \counter_points_snapshot_10[10]\); - - \data_out[108]\ : DFN1C0 - port map(D => \sample_f1_wdata[44]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[6]\, B => - I_31_15, S => counter_points_snapshot_2_sqmuxa, Y => - N_278); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f1_wdata_92, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(156)); - - \data_out_RNO[106]\ : MX2 - port map(A => sample_f1_5, B => sample_f1_37, S => - data_shaping_R1, Y => \sample_f1_wdata[42]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_3 : - AO1C - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_counter_points_snapshot[14]\, C => N_47_1, Y => - ADD_32x32_fast_I255_un1_Y_3); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[8]\, B => - I_45_11, S => counter_points_snapshot_2_sqmuxa, Y => - N_280); - - \data_out_RNO[80]\ : NOR2B - port map(A => sample_f1_63, B => data_shaping_R1, Y => - \sample_f1_wdata[16]\); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_273, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_0, - Y => ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : AO1A - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot_i[5]\, C => N_47_2, Y => - N483_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - NOR3A - port map(A => N446, B => N449, C => N756, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - N_52, Y => N_27); - - \data_out_RNO[88]\ : NOR2B - port map(A => sample_f1_55, B => data_shaping_R1_0, Y => - \sample_f1_wdata[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y : NOR2B - port map(A => ADD_32x32_fast_I103_Y_1, B => - ADD_32x32_fast_I103_Y_0, Y => N549); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => N_7, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => N_31, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[24]_net_1\); - - \data_out[95]\ : DFN1C0 - port map(D => \sample_f1_wdata[31]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(95)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_0 : NOR2A - port map(A => N483_i, B => N479, Y => - ADD_32x32_fast_I252_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y : OR3 - port map(A => N607, B => ADD_32x32_fast_I252_un1_Y_0, C => - N777_i, Y => ADD_32x32_fast_I252_un1_Y); - - \counter_points_snapshot_RNI7U3D[21]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[21]_net_1\, Y => - \un1_counter_points_snapshot[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR2B - port map(A => ADD_32x32_fast_I126_Y_1, B => - ADD_32x32_fast_I126_Y_0, Y => N572); - - \data_out_RNO[110]\ : MX2 - port map(A => sample_f1_1, B => sample_f1_33, S => - data_shaping_R1, Y => \sample_f1_wdata[46]\); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => I_52_11, B => - \un1_data_out_valid_0_sqmuxa_2[9]\, S => N_60, Y => N_281); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : OA1 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[20]\, C => N419, Y => - ADD_32x32_fast_I126_Y_1); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_275, Y => - \counter_points_snapshot_10[3]\); - - \counter_points_snapshot_RNIGC6G[2]\ : MX2C - port map(A => I_9_31, B => - \counter_points_snapshot[2]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot_i[29]\); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f1_wdata_54, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(118)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I5_G0N : NOR2A - port map(A => \un1_counter_points_snapshot[26]\, B => N_47, - Y => N395); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR2A - port map(A => N380, B => N646, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot_i[5]\, B => - N_47_0, Y => ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2A - port map(A => N642, B => N594, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[24]\, C => N650_i, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I286_Y_0_0, B => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0 : XOR3 - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N783, Y => - \un1_data_out_valid_0_sqmuxa_2[11]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I23_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_2, - Y => N449); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I100_Y : OR2B - port map(A => N487, B => N483_i, Y => N546); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f1_wdata_64, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(128)); - - \counter_points_snapshot_RNO[11]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_283, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => \sample_f1_wdata[33]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f1_wdata_74, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(138)); - - \data_out_RNO[84]\ : NOR2B - port map(A => sample_f1_59, B => data_shaping_R1_0, Y => - \sample_f1_wdata[20]\); - - \counter_points_snapshot_RNIESSE[1]\ : MX2 - port map(A => I_5_31, B => - \counter_points_snapshot[1]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[30]\); - - \data_out[85]\ : DFN1C0 - port map(D => \sample_f1_wdata[21]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[3]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I18_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => N_47, - Y => N434); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I159_Y : NOR3 - port map(A => N496, B => N492, C => N547, Y => N611); - - \data_out_RNO[85]\ : NOR2B - port map(A => sample_f1_58, B => data_shaping_R1_0, Y => - \sample_f1_wdata[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => \sample_f1_wdata[45]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(109)); - - \counter_points_snapshot_RNIK8DD[18]\ : NOR3A - port map(A => un1_data_in_validlt30_10, B => - \counter_points_snapshot[19]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un1_data_in_validlt30_20); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : OA1B - port map(A => N_47, B => \un1_counter_points_snapshot[20]\, - C => N416, Y => N511); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I192_Y : OR3 - port map(A => ADD_32x32_fast_I134_Y_0, B => - ADD_32x32_fast_I134_Y_1, C => N588, Y => N644); - - \data_out_RNO[111]\ : MX2 - port map(A => sample_f1_0, B => sample_f1_32, S => - data_shaping_R1, Y => \sample_f1_wdata[47]\); - - \counter_points_snapshot_RNICU3D[26]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot_i[5]\); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => N_29, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => N_25, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot_RNI6I9A[6]\ : NOR3A - port map(A => un1_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un1_data_in_validlt30_17); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : AO1 - port map(A => N556, B => N549, C => N548, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f1_wdata_83, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(147)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f1_wdata_87, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(151)); - - \data_out_RNO[83]\ : NOR2B - port map(A => sample_f1_60, B => data_shaping_R1_0, Y => - \sample_f1_wdata[19]\); - - \counter_points_snapshot_RNI2DCL[6]\ : MX2C - port map(A => I_31_15, B => - \counter_points_snapshot[6]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[25]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot_i[12]\, B => - N_47_0, Y => ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => N_47_0, - Y => ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => \sample_f1_wdata[23]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(87)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f1_wdata_89, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(153)); - - \counter_points_snapshot_RNIN4UQ[11]\ : MX2C - port map(A => N_4, B => \counter_points_snapshot[11]_net_1\, - S => counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I283_Y_0_0, B => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR3 - port map(A => N636, B => N620, C => N652, Y => N756); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AO1 - port map(A => \un1_counter_points_snapshot_i[29]\, B => - \un1_counter_points_snapshot_i[28]\, C => N_47, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : OR3A - port map(A => N529, B => N395, C => N392, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => N_47_0, - Y => ADD_32x32_fast_I307_Y_0_0); - - \data_out_RNO[91]\ : NOR2B - port map(A => sample_f1_52, B => data_shaping_R1_0, Y => - \sample_f1_wdata[27]\); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f1_wdata_55, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I53_Y : OA1A - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot_i[12]\, C => N_47_2, Y => - N496); - - \data_out_RNO[102]\ : MX2 - port map(A => sample_f1_9, B => sample_f1_41, S => - data_shaping_R1, Y => \sample_f1_wdata[38]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AO1A - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot_i[21]\, C => N_47, Y => N515); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I161_Y : NOR3C - port map(A => ADD_32x32_fast_I161_Y_1, B => - ADD_32x32_fast_I161_Y_0, C => N549, Y => N613); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[7]\, B => - I_38_12, S => counter_points_snapshot_2_sqmuxa, Y => - N_279); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_281, Y => - \counter_points_snapshot_10[9]\); - - \counter_points_snapshot_RNIHDVN[8]\ : MX2C - port map(A => I_45_11, B => - \counter_points_snapshot[8]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot_i[23]\); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f1_wdata_5, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f1_wdata_65, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I112_Y : OR2B - port map(A => N499, B => N495, Y => N558); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y_0 : - NOR2A - port map(A => N504, B => N500, Y => - ADD_32x32_fast_I254_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : NOR3B - port map(A => N481, B => ADD_32x32_fast_I251_Y_0, C => N548, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f1_wdata_75, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => N_33, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[25]_net_1\); - - \data_out_RNO[82]\ : NOR2B - port map(A => sample_f1_61, B => data_shaping_R1, Y => - \sample_f1_wdata[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I161_Y_0 : OAI1 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot_i[12]\, C => N_47_1, Y => - ADD_32x32_fast_I161_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[20]\, B => N_47, - C => N783, Y => N780_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : AO1C - port map(A => N_47, B => \un1_counter_points_snapshot[30]\, - C => N380, Y => N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : AO1A - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[7]\, C => N_47, Y => N485); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f1_wdata_11, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(75)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I97_Y_0_tz : - NOR2B - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[3]\, Y => - ADD_32x32_fast_I97_Y_0_tz); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => - N_47_1, Y => ADD_32x32_fast_I284_Y_0_0); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f1_wdata_4, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(68)); - - \counter_points_snapshot_RNO_0[11]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[11]\, B => N_4, - S => counter_points_snapshot_2_sqmuxa, Y => N_283); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_0 : AO1D - port map(A => \un1_counter_points_snapshot[2]\, B => - \un1_counter_points_snapshot[3]\, C => N_47_0, Y => - ADD_32x32_fast_I251_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I12_G0N : NOR3B - port map(A => \counter_points_snapshot[12]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N416); - - \counter_points_snapshot_RNIEU3D[28]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : OA1C - port map(A => \un1_counter_points_snapshot[11]\, B => - N_47_2, C => N437, Y => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OR3B - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N556, Y => N620); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : NOR3A - port map(A => N380, B => N646, C => N630, Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768, B => ADD_32x32_fast_I296_Y_0_0, C => - N_52, Y => N_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I57_Y : OA1A - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47_2, Y => N500); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : OR2A - port map(A => N566, B => N558, Y => N622); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I214_un1_Y : - NOR2B - port map(A => N628, B => N613, Y => I214_un1_Y); - - \counter_points_snapshot_RNI5OM6[20]\ : NOR2 - port map(A => \counter_points_snapshot[20]_net_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - un1_data_in_validlt30_10); - - data_out_valid_RNO : OA1 - port map(A => burst_f1, B => N_59, C => - data_out_valid_9_i_0, Y => N_49); - - \data_out[100]\ : DFN1C0 - port map(D => \sample_f1_wdata[36]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : OR3B - port map(A => N642, B => N626, C => N594, Y => N762); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f1_wdata_13, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f1_wdata_82, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_274, Y => - \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : NOR3B - port map(A => N511, B => N515, C => N582, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1B - port map(A => N777_i, B => ADD_32x32_fast_I293_Y_0_0, C => - N_52, Y => N_9); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f1_wdata_94, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(158)); - - \data_out_RNO[105]\ : MX2 - port map(A => sample_f1_6, B => sample_f1_38, S => - data_shaping_R1, Y => \sample_f1_wdata[41]\); - - \counter_points_snapshot_RNIBU3D[25]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f1_wdata_0, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[25]\, B => - N_47_1, Y => ADD_32x32_fast_I286_Y_0_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_controler is - - port( coarse_time_i : in std_logic_vector(0 to 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - coarse_time : in std_logic_vector(0 to 0); - start_snapshot_f2 : out std_logic; - start_snapshot_f1 : out std_logic; - start_snapshot_f0 : out std_logic; - sample_f2_val : in std_logic; - sample_f0_val_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_waveform_snapshot_controler; - -architecture DEF_ARCH of lpp_waveform_snapshot_controler is - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \counter_delta_snapshot_0[26]_net_1\, - counter_delta_snapshot_e26, N_9_0, - counter_delta_f0lde_i_a2_0_1_i, N_57_0, - start_snapshot_f22, \start_snapshot_fothers_temp\, - un2_coarse_time_0_0, coarse_time_0_r_i, N_504_0, N_406, - N_406_0, \counter_delta_snapshot[25]_net_1\, N_405, - start_snapshot_f12, N_322, start_snapshot_f12_0_a2_8, - un1_start_snapshot_f22_i_a2_0_4, - un1_start_snapshot_f22_i_a2_0_5, - start_snapshot_f12_0_a2_7, start_snapshot_f12_0_a2_6, - counter_delta_snapshot_e9_i_0, - \counter_delta_snapshot[9]_net_1\, N_469, - counter_delta_snapshot_e6_i_0, - \counter_delta_snapshot[6]_net_1\, N_455, - counter_delta_snapshot_e2_i_0, - \counter_delta_snapshot[2]_net_1\, N_239, - counter_delta_snapshot_e3_i_0, - \counter_delta_snapshot[3]_net_1\, N_440, - counter_delta_snapshot_e7_i_0, - \counter_delta_snapshot[7]_net_1\, N_460, - counter_delta_snapshot_e8_i_0, - \counter_delta_snapshot[8]_net_1\, N_465, - counter_delta_snapshot_e4_i_0, - \counter_delta_snapshot[4]_net_1\, N_445, - counter_delta_snapshot_e5_i_0, - \counter_delta_snapshot_i[5]\, N_450, - counter_delta_snapshot_e15_i_0_0, - \counter_delta_snapshot_i[15]\, N_478, - counter_delta_snapshot_e14_i_0_0, - \counter_delta_snapshot[14]_net_1\, N_484, - counter_delta_snapshot_e13_i_0_0, - \counter_delta_snapshot[13]_net_1\, N_285, - counter_delta_snapshot_e12_i_0_0, - \counter_delta_snapshot[12]_net_1\, N_493, - counter_delta_snapshot_e11_i_0_0, - \counter_delta_snapshot_i[11]\, N_499, - counter_delta_snapshot_e21_0_0_0, - \counter_delta_snapshot[21]_net_1\, N_183, - counter_delta_snapshot_e10_i_0, - \counter_delta_snapshot[10]_net_1\, un2_coarse_time_0, - N_474, counter_delta_snapshot_e24_0_0_0, - \counter_delta_snapshot[24]_net_1\, N_192, - counter_delta_snapshot_e0_i_0, N_505, N_429, - counter_delta_snapshot_e23_0_0_0, - \counter_delta_snapshot[23]_net_1\, N_189, - counter_delta_snapshot_e19_i_i_0, - \counter_delta_snapshot[19]_net_1\, N_177, - counter_delta_snapshot_e17_i_i_0, - \counter_delta_snapshot[17]_net_1\, N_171, - counter_delta_snapshot_e9_i_a2_0, N_389, - counter_delta_snapshot_e6_i_a2_0, N_386, - counter_delta_snapshot_e2_i_a2_0, N_382, - counter_delta_snapshot_e3_i_a2_0, N_383, - counter_delta_snapshot_e7_i_a2_0, N_387, - counter_delta_snapshot_e8_i_a2_0, N_388, - counter_delta_snapshot_e10_i_a2_0, N_390, - counter_delta_snapshot_e24_0_0_a2_0, N_404, - counter_delta_snapshot_e16_i_i_a2_0, - \counter_delta_snapshot[16]_net_1\, N_396, - counter_delta_snapshot_e17_i_i_a2_0, - counter_delta_snapshot_e18_i_i_a2_0, - \counter_delta_snapshot[18]_net_1\, N_398, - counter_delta_snapshot_e19_i_i_a2_0, - counter_delta_snapshot_e20_i_i_a2_0, - \counter_delta_snapshot[20]_net_1\, N_400, - counter_delta_snapshot_e21_0_0_a2_0, - counter_delta_snapshot_e22_0_0_a2_0, - \counter_delta_snapshot[22]_net_1\, N_402, - counter_delta_snapshot_e23_0_0_a2_0, - counter_delta_snapshot_e4_i_a2_0, N_384, - counter_delta_snapshot_e5_i_a2_0, N_385, - counter_delta_snapshot_e15_i_0_a2_0, N_395, - counter_delta_snapshot_e14_i_0_a2_0, N_394, - counter_delta_snapshot_e13_i_0_a2_0, N_393, - counter_delta_snapshot_e12_i_0_a2_0, - \counter_delta_snapshot_RNI01E2[7]_net_1\, - counter_delta_snapshot_e11_i_0_a2_0, N_391, - counter_delta_f0lde_i_a2_0_1_3, - counter_delta_f0lde_i_a2_0_1_2, N_89, - \counter_delta_f0[3]_net_1\, N_273, - counter_delta_f0_1_0_a2_2_0, counter_delta_f0_1_0_a2_7, - N_108_i_i_0, N_84_i_i_0, start_snapshot_f12_0_a2_5, - N_83_i_i_0, N_274_i_0, start_snapshot_f12_0_a2_2, - N_82_i_i_0, N_81_i_i_0, start_snapshot_f12_0_a2_1, - \counter_delta_f0[4]_net_1\, N_113_i_i_0, - \counter_delta_f0[1]_net_1\, N_111_i_i_0, - start_snapshot_f22_0_a2_1, - start_snapshot_f22_0_a2_11_0_a2_4, - start_snapshot_f22_0_a2_11_0_a2_5, - start_snapshot_f22_0_a2_0, \start_snapshot_f2_temp\, - start_snapshot_f22_10, start_snapshot_f2_temp3_0_a2_0, - counter_delta_snapshot_e12_i_0_o2_m6_e_6, - counter_delta_snapshot_e12_i_0_o2_m6_e_4, - counter_delta_snapshot_e12_i_0_o2_m6_e_5, - counter_delta_snapshot_e12_i_0_o2_m6_e_2, - un12_start_snapshot_fothers_temp_NE_13, - un12_start_snapshot_fothers_temp_NE_5, - un12_start_snapshot_fothers_temp_NE_4, - un12_start_snapshot_fothers_temp_NE_11, - un12_start_snapshot_fothers_temp_NE_12, - un12_start_snapshot_fothers_temp_NE_1, - un12_start_snapshot_fothers_temp_NE_0, - un12_start_snapshot_fothers_temp_NE_9, N_506_i, N_166_i_i, - un12_start_snapshot_fothers_temp_NE_7, N_507_i, N_137_i_i, - un12_start_snapshot_fothers_temp_NE_3, N_509_i, N_164_i_i, - N_510_i, \counter_delta_snapshot_RNIFJ31[15]_net_1\, - N_136_i_i, N_133_i_i, counter_delta_f0_1_0_a2_12, - counter_delta_f0_1_0_a2_3, counter_delta_f0_1_0_a2_8, - counter_delta_f0_1_8, counter_delta_f0_1_0_a2_11, - counter_delta_f0_1_0_a2_6, counter_delta_f0_1_0_a2_5, - counter_delta_f0_1_0_a2_10, counter_delta_f0_1_0_a2_5_0, - counter_delta_f0_1_0_a2_0, N_272, - \counter_delta_f0[0]_net_1\, \counter_delta_f0[2]_net_1\, - \counter_delta_f0[21]_net_1\, - \counter_delta_f0[25]_net_1\, counter_delta_f0_1_0_a2_2, - \counter_delta_f0[14]_net_1\, - \counter_delta_f0[15]_net_1\, - \counter_delta_f0[20]_net_1\, \counter_delta_f0[8]_net_1\, - \counter_delta_f0[9]_net_1\, - start_snapshot_f22_0_a2_11_0_a2_3, - start_snapshot_f22_0_a2_11_0_a2_1, - counter_delta_f0_1_0_a2_8_0, \counter_delta_f0[16]_net_1\, - \counter_delta_f0[17]_net_1\, - \counter_delta_snapshot_RNO[16]_net_1\, N_168, N_169, - N_170, \counter_delta_snapshot_RNO[17]_net_1\, - \counter_delta_snapshot_RNO[18]_net_1\, N_174, N_175, - N_176, N_20, \counter_delta_snapshot_RNO[20]_net_1\, - N_180, N_181, N_182, counter_delta_snapshot_e21, - counter_delta_snapshot_e22, N_186, N_187, N_188, - counter_delta_snapshot_e23, counter_delta_snapshot_e25, - N_421, N_422, N_423, N_19, N_65, - \counter_delta_f0[10]_net_1\, N_275, N_67, - \counter_delta_f0[11]_net_1\, N_34, N_80, - \counter_delta_f0[26]_net_1\, start_snapshot_f2_temp3, - \counter_delta_f0[19]_net_1\, - \counter_delta_f0[18]_net_1\, counter_delta_f0_1, - N_22_i_0, N_501, N_503, N_195_i_0, N_496, N_498, N_26_i_0, - N_287, N_288, N_6_i_0, N_486, N_488, N_8_i_0, N_480, - N_482, \counter_delta_snapshot_RNO[10]_net_1\, N_476, - N_477, \counter_delta_snapshot_RNO[8]_net_1\, N_467, - N_468, \counter_delta_snapshot_RNO[7]_net_1\, N_462, - N_463, N_376_i_0, N_452, N_453, N_375_i_0, N_447, N_448, - \counter_delta_snapshot_RNO[3]_net_1\, N_442, N_443, N_54, - N_437, N_438, \counter_delta_snapshot_RNO[1]_net_1\, - N_433, counter_delta_snapshot_e1_i_0, N_435, - \counter_delta_snapshot_RNO[0]_net_1\, - \counter_delta_snapshot[0]_net_1\, N_472, N_504, - \counter_delta_snapshot[1]_net_1\, - \counter_delta_snapshot[26]_net_1\, N_458, - \counter_delta_snapshot_RNO[6]_net_1\, N_457, - \counter_delta_snapshot_RNO[9]_net_1\, N_471, - counter_delta_snapshot_e24, \counter_delta_f0[7]_net_1\, - \counter_delta_f0[6]_net_1\, \counter_delta_f0[23]_net_1\, - \counter_delta_f0[22]_net_1\, - \counter_delta_f0[24]_net_1\, N_284, N_9, - \counter_delta_f0[13]_net_1\, - \counter_delta_f0[12]_net_1\, \counter_delta_f0[5]_net_1\, - N_21, N_23, N_107_i_i, N_227, N_114_i_i, N_228, N_115_i_i, - N_229, N_116_i_i, N_230, N_117_i_i, counter_delta_f0_n12, - N_98, counter_delta_f0_n13, N_99, counter_delta_f0_n14, - N_100, counter_delta_f0_n15, N_101, counter_delta_f0_n16, - N_102, N_57, counter_delta_f0_n17, N_103, - counter_delta_f0_n18, N_104, counter_delta_f0_n19, N_105, - counter_delta_f0_n20, N_106, N_55, N_13, N_89_i_i, N_15, - N_99_i_i, N_17, N_324_i, N_276, N_58, N_277, N_60, N_28, - N_62, N_30, N_64, N_32, N_66, N_59, N_63, N_87_i_i, N_11, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter_delta_snapshot_RNO_1[11]\ : AOI1B - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot_i[11]\, C => N_499, Y => - counter_delta_snapshot_e11_i_0_0); - - \counter_delta_snapshot_RNO[21]\ : OAI1 - port map(A => N_402, B => N_504_0, C => - counter_delta_snapshot_e21_0_0_0, Y => - counter_delta_snapshot_e21); - - \counter_delta_snapshot[19]\ : DFN1C0 - port map(D => N_20, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[19]_net_1\); - - start_snapshot_f0_RNO_1 : NOR3A - port map(A => counter_delta_f0_1_0_a2_5_0, B => - counter_delta_f0_1_0_a2_0, C => N_272, Y => - counter_delta_f0_1_0_a2_10); - - \counter_delta_f0_RNO[14]\ : XA1A - port map(A => \counter_delta_f0[14]_net_1\, B => N_100, C - => N_57_0, Y => counter_delta_f0_n14); - - \counter_delta_snapshot_RNO_0[17]\ : AOI1B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[17]_net_1\, C => N_171, Y => - counter_delta_snapshot_e17_i_i_0); - - \counter_delta_f0_RNI3797[16]\ : NOR2 - port map(A => \counter_delta_f0[16]_net_1\, B => - \counter_delta_f0[17]_net_1\, Y => - counter_delta_f0_1_0_a2_8_0); - - start_snapshot_fothers_temp_RNISVED5_0 : AOI1B - port map(A => sample_f0_val_0, B => - counter_delta_f0lde_i_a2_0_1_i, C => N_57_0, Y => N_9); - - \op_eq.start_snapshot_f12_0_a2_RNO_2\ : XNOR2 - port map(A => \counter_delta_f0[0]_net_1\, B => - delta_f2_f1(0), Y => N_108_i_i_0); - - \counter_delta_f0_RNIBN261[4]\ : NOR3B - port map(A => N_273, B => counter_delta_f0_1_0_a2_2_0, C - => counter_delta_f0_1_0_a2_7, Y => - counter_delta_f0lde_i_a2_0_1_2); - - \counter_delta_snapshot_RNO[19]\ : OAI1 - port map(A => N_400, B => N_504_0, C => - counter_delta_snapshot_e19_i_i_0, Y => N_20); - - un1_start_snapshot_f22_i_a2_0 : AND2 - port map(A => un1_start_snapshot_f22_i_a2_0_4, B => - un1_start_snapshot_f22_i_a2_0_5, Y => N_322); - - \counter_delta_snapshot_RNO_1[2]\ : AO1A - port map(A => \counter_delta_snapshot[2]_net_1\, B => - un2_coarse_time_0_0, C => N_239, Y => - counter_delta_snapshot_e2_i_0); - - \counter_delta_snapshot_RNIA82J_1[26]\ : AO1A - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => un2_coarse_time_0, Y => N_504); - - \counter_delta_f0_RNO[11]\ : XA1A - port map(A => N_67, B => \counter_delta_f0[11]_net_1\, C - => N_57_0, Y => N_275); - - \counter_delta_f0_RNO_0[4]\ : AX1B - port map(A => N_89, B => \counter_delta_f0[3]_net_1\, C => - \counter_delta_f0[4]_net_1\, Y => N_116_i_i); - - \counter_delta_snapshot_RNO_1[12]\ : OA1A - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[12]_net_1\, C => N_493, Y => - counter_delta_snapshot_e12_i_0_0); - - \counter_delta_f0_RNI2NDI3[23]\ : OR2 - port map(A => \counter_delta_f0[23]_net_1\, B => N_62, Y - => N_64); - - start_snapshot_f2_temp_RNO : NOR3B - port map(A => un12_start_snapshot_fothers_temp_NE_12, B => - un12_start_snapshot_fothers_temp_NE_13, C => - start_snapshot_f2_temp3_0_a2_0, Y => - start_snapshot_f2_temp3); - - \counter_delta_f0_RNO[26]\ : XA1 - port map(A => N_80, B => \counter_delta_f0[26]_net_1\, C - => N_57_0, Y => N_34); - - \counter_delta_snapshot_RNI0R62[10]\ : OR2 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - N_390, Y => N_391); - - \counter_delta_snapshot_RNI01E2[7]\ : OR3B - port map(A => counter_delta_snapshot_e12_i_0_o2_m6_e_6, B - => counter_delta_snapshot_e12_i_0_o2_m6_e_5, C => N_383, - Y => \counter_delta_snapshot_RNI01E2[7]_net_1\); - - \counter_delta_snapshot_RNO_1[19]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e19_i_i_a2_0, Y => - N_177); - - \counter_delta_f0_RNITNMC[8]\ : NOR2 - port map(A => \counter_delta_f0[8]_net_1\, B => - \counter_delta_f0[9]_net_1\, Y => - counter_delta_f0_1_0_a2_2_0); - - \counter_delta_snapshot_RNO[5]\ : OR3C - port map(A => N_452, B => counter_delta_snapshot_e5_i_0, C - => N_453, Y => N_376_i_0); - - \counter_delta_snapshot[16]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[16]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[16]_net_1\); - - \counter_delta_snapshot_RNO_0[20]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e20_i_i_a2_0, Y => - N_180); - - \counter_delta_snapshot_RNO_1[16]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[16]_net_1\, Y => N_169); - - \counter_delta_snapshot_RNO_0[10]\ : NOR2 - port map(A => N_505, B => delta_snapshot(10), Y => N_476); - - \counter_delta_snapshot_RNI5J31[10]\ : XNOR2 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - delta_snapshot(10), Y => N_510_i); - - \counter_delta_snapshot_RNI3T11[7]\ : NOR3A - port map(A => counter_delta_snapshot_e12_i_0_o2_m6_e_4, B - => \counter_delta_snapshot[8]_net_1\, C => - \counter_delta_snapshot[7]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_6); - - \counter_delta_snapshot_0_RNI70LQ[26]\ : AO1A - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406, C => un2_coarse_time_0_0, Y => N_504_0); - - \counter_delta_snapshot[25]\ : DFN1C0 - port map(D => counter_delta_snapshot_e25, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[25]_net_1\); - - \counter_delta_f0_RNO[7]\ : MX2 - port map(A => delta_f2_f0(7), B => N_89_i_i, S => N_57, Y - => N_13); - - \counter_delta_snapshot_RNO_2[13]\ : OR3A - port map(A => \counter_delta_snapshot[13]_net_1\, B => - N_393, C => N_504_0, Y => N_288); - - \counter_delta_snapshot_RNO_3[5]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e5_i_a2_0, Y => - N_450); - - \counter_delta_snapshot[14]\ : DFN1C0 - port map(D => N_6_i_0, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[14]_net_1\); - - \counter_delta_snapshot_RNO_1[17]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e17_i_i_a2_0, Y => - N_171); - - \counter_delta_f0_RNI3UIE[21]\ : NOR3 - port map(A => \counter_delta_f0[21]_net_1\, B => - \counter_delta_f0[25]_net_1\, C => - counter_delta_f0_1_0_a2_2, Y => - counter_delta_f0_1_0_a2_5_0); - - \counter_delta_f0[14]\ : DFN1E0C0 - port map(D => counter_delta_f0_n14, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[14]_net_1\); - - \counter_delta_snapshot_RNO_0[2]\ : NOR2 - port map(A => N_505, B => delta_snapshot(2), Y => N_437); - - \counter_delta_snapshot_RNIQOS[17]\ : NOR3A - port map(A => start_snapshot_f22_0_a2_11_0_a2_1, B => - \counter_delta_snapshot[17]_net_1\, C => - \counter_delta_snapshot[16]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_4); - - \counter_delta_f0_RNO[18]\ : XA1A - port map(A => \counter_delta_f0[18]_net_1\, B => N_104, C - => N_57, Y => counter_delta_f0_n18); - - \counter_delta_snapshot_RNO[17]\ : OAI1 - port map(A => N_398, B => N_504_0, C => - counter_delta_snapshot_e17_i_i_0, Y => - \counter_delta_snapshot_RNO[17]_net_1\); - - \counter_delta_snapshot[2]\ : DFN1C0 - port map(D => N_54, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[2]_net_1\); - - \counter_delta_f0_RNIEKGP[12]\ : NOR3A - port map(A => counter_delta_f0_1_0_a2_3, B => - counter_delta_f0_1_0_a2_0, C => N_272, Y => - un1_start_snapshot_f22_i_a2_0_4); - - \counter_delta_snapshot_RNO_2[15]\ : OR3 - port map(A => N_395, B => \counter_delta_snapshot_i[15]\, C - => N_504_0, Y => N_482); - - \counter_delta_snapshot_RNIA82J[26]\ : OR3A - port map(A => N_406, B => - \counter_delta_snapshot[26]_net_1\, C => - un2_coarse_time_0, Y => N_505); - - \counter_delta_f0_RNIA81P1[8]\ : OR3 - port map(A => N_59, B => \counter_delta_f0[7]_net_1\, C => - \counter_delta_f0[8]_net_1\, Y => N_63); - - \counter_delta_f0_RNI9MCV1[3]\ : NOR3A - port map(A => counter_delta_f0lde_i_a2_0_1_2, B => N_89, C - => \counter_delta_f0[3]_net_1\, Y => - counter_delta_f0lde_i_a2_0_1_3); - - \counter_delta_snapshot_RNO_2[14]\ : OR3A - port map(A => \counter_delta_snapshot[14]_net_1\, B => - N_394, C => N_504_0, Y => N_488); - - \counter_delta_snapshot_RNIJ7B1[6]\ : NOR2 - port map(A => \counter_delta_snapshot[6]_net_1\, B => N_386, - Y => N_387); - - \counter_delta_f0_RNO[20]\ : XA1A - port map(A => \counter_delta_f0[20]_net_1\, B => N_106, C - => N_57, Y => counter_delta_f0_n20); - - \counter_delta_snapshot_RNO_3[7]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e7_i_a2_0, Y => N_460); - - \counter_delta_snapshot_RNI1LV1[9]\ : OR2A - port map(A => N_389, B => \counter_delta_snapshot[9]_net_1\, - Y => N_390); - - \counter_delta_snapshot[21]\ : DFN1C0 - port map(D => counter_delta_snapshot_e21, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[21]_net_1\); - - \counter_delta_snapshot_RNIOJO3[2]\ : XA1A - port map(A => delta_snapshot(2), B => - \counter_delta_snapshot[2]_net_1\, C => N_510_i, Y => - un12_start_snapshot_fothers_temp_NE_4); - - \counter_delta_f0[15]\ : DFN1E0C0 - port map(D => counter_delta_f0_n15, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[15]_net_1\); - - \counter_delta_snapshot_RNO_2[11]\ : OR3 - port map(A => N_391, B => \counter_delta_snapshot_i[11]\, C - => N_504_0, Y => N_503); - - \counter_delta_snapshot_RNIRL41[5]\ : OR2A - port map(A => \counter_delta_snapshot_i[5]\, B => N_385, Y - => N_386); - - \counter_delta_snapshot_RNO[20]\ : OR3C - port map(A => N_180, B => N_181, C => N_182, Y => - \counter_delta_snapshot_RNO[20]_net_1\); - - \counter_delta_snapshot_RNI48U[4]\ : OR2 - port map(A => \counter_delta_snapshot[4]_net_1\, B => N_384, - Y => N_385); - - \counter_delta_snapshot_RNO_1[10]\ : AO1A - port map(A => \counter_delta_snapshot[10]_net_1\, B => - un2_coarse_time_0, C => N_474, Y => - counter_delta_snapshot_e10_i_0); - - \counter_delta_f0_RNIAEIE[18]\ : OR3A - port map(A => counter_delta_f0_1_0_a2_8_0, B => - \counter_delta_f0[19]_net_1\, C => - \counter_delta_f0[18]_net_1\, Y => counter_delta_f0_1_8); - - \counter_delta_snapshot_RNO[25]\ : OR3C - port map(A => N_421, B => N_422, C => N_423, Y => - counter_delta_snapshot_e25); - - \counter_delta_f0_RNIOOKV[4]\ : NOR3 - port map(A => N_89, B => \counter_delta_f0[3]_net_1\, C => - \counter_delta_f0[4]_net_1\, Y => N_55); - - \counter_delta_f0_RNI4JE41[10]\ : NOR3A - port map(A => counter_delta_f0_1_0_a2_5_0, B => - counter_delta_f0_1_8, C => counter_delta_f0_1_0_a2_5, Y - => un1_start_snapshot_f22_i_a2_0_5); - - \counter_delta_snapshot_RNO[4]\ : NOR3C - port map(A => N_447, B => counter_delta_snapshot_e4_i_0, C - => N_448, Y => N_375_i_0); - - \counter_delta_snapshot[23]\ : DFN1C0 - port map(D => counter_delta_snapshot_e23, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[23]_net_1\); - - \counter_delta_snapshot_RNO_4[8]\ : OR2 - port map(A => \counter_delta_snapshot[8]_net_1\, B => N_388, - Y => counter_delta_snapshot_e8_i_a2_0); - - \counter_delta_snapshot_RNO[23]\ : OAI1 - port map(A => N_404, B => N_504_0, C => - counter_delta_snapshot_e23_0_0_0, Y => - counter_delta_snapshot_e23); - - \counter_delta_snapshot[17]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[17]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[17]_net_1\); - - \counter_delta_f0[4]\ : DFN1E0C0 - port map(D => N_229, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[4]_net_1\); - - \counter_delta_snapshot_RNI9KE[23]\ : NOR2 - port map(A => \counter_delta_snapshot[22]_net_1\, B => - \counter_delta_snapshot[23]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_3); - - \counter_delta_f0[13]\ : DFN1E0C0 - port map(D => counter_delta_f0_n13, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[13]_net_1\); - - \counter_delta_snapshot_RNO_2[12]\ : OR3A - port map(A => \counter_delta_snapshot[12]_net_1\, B => - \counter_delta_snapshot_RNI01E2[7]_net_1\, C => N_504_0, - Y => N_498); - - \counter_delta_snapshot_RNO_2[19]\ : OA1 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot[19]_net_1\, Y => - counter_delta_snapshot_e19_i_i_a2_0); - - \counter_delta_f0_RNI9MCV1[9]\ : NOR2 - port map(A => \counter_delta_f0[9]_net_1\, B => N_63, Y => - N_65); - - \counter_delta_f0_RNO_0[3]\ : XNOR2 - port map(A => \counter_delta_f0[3]_net_1\, B => N_89, Y => - N_115_i_i); - - \counter_delta_snapshot_RNI6NO1[8]\ : NOR2A - port map(A => N_388, B => \counter_delta_snapshot[8]_net_1\, - Y => N_389); - - \counter_delta_snapshot_RNO_2[16]\ : OR3 - port map(A => N_396, B => - \counter_delta_snapshot[16]_net_1\, C => N_504, Y => - N_170); - - \counter_delta_snapshot_RNICTH1[7]\ : NOR2A - port map(A => N_387, B => \counter_delta_snapshot[7]_net_1\, - Y => N_388); - - start_snapshot_fothers_temp : DFN1E0C0 - port map(D => start_snapshot_f22, CLK => lclk_c, CLR => - rstn, E => N_284, Q => \start_snapshot_fothers_temp\); - - \counter_delta_snapshot_RNO_1[5]\ : AOI1B - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot_i[5]\, C => N_450, Y => - counter_delta_snapshot_e5_i_0); - - \counter_delta_snapshot_RNINGL2[4]\ : XNOR2 - port map(A => \counter_delta_snapshot[4]_net_1\, B => - delta_snapshot(4), Y => N_507_i); - - \counter_delta_snapshot_RNO_2[17]\ : OA1 - port map(A => N_396, B => - \counter_delta_snapshot[16]_net_1\, C => - \counter_delta_snapshot[17]_net_1\, Y => - counter_delta_snapshot_e17_i_i_a2_0); - - \counter_delta_snapshot_RNO[7]\ : NOR3 - port map(A => N_462, B => counter_delta_snapshot_e7_i_0, C - => N_463, Y => \counter_delta_snapshot_RNO[7]_net_1\); - - \counter_delta_f0_RNI0TL62[11]\ : OR2 - port map(A => \counter_delta_f0[11]_net_1\, B => N_67, Y - => N_98); - - GND_i : GND - port map(Y => \GND\); - - \counter_delta_snapshot[10]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[10]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[10]_net_1\); - - \counter_delta_snapshot_RNO_4[3]\ : OR2A - port map(A => N_383, B => \counter_delta_snapshot[3]_net_1\, - Y => counter_delta_snapshot_e3_i_a2_0); - - \counter_delta_snapshot_RNIEQGD[12]\ : NOR3C - port map(A => un12_start_snapshot_fothers_temp_NE_1, B => - un12_start_snapshot_fothers_temp_NE_0, C => - un12_start_snapshot_fothers_temp_NE_9, Y => - un12_start_snapshot_fothers_temp_NE_12); - - start_snapshot_f2_temp_RNIEAF61 : NOR3B - port map(A => un12_start_snapshot_fothers_temp_NE_12, B => - un12_start_snapshot_fothers_temp_NE_13, C => - start_snapshot_f22_0_a2_1, Y => start_snapshot_f22); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \counter_delta_snapshot_RNO_0[6]\ : NOR2 - port map(A => N_505, B => delta_snapshot(6), Y => N_457); - - \counter_delta_snapshot_RNI3DS2[13]\ : OR2 - port map(A => \counter_delta_snapshot[13]_net_1\, B => - N_393, Y => N_394); - - \counter_delta_snapshot[3]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[3]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[3]_net_1\); - - \counter_delta_f0_RNO_0[7]\ : XNOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => N_59, Y => - N_89_i_i); - - \counter_delta_snapshot_RNO_3[18]\ : NOR2B - port map(A => \counter_delta_snapshot[18]_net_1\, B => - N_398, Y => counter_delta_snapshot_e18_i_i_a2_0); - - \start_snapshot_f0\ : DFN1C0 - port map(D => counter_delta_f0_1, CLK => lclk_c, CLR => - rstn, Q => start_snapshot_f0); - - \counter_delta_snapshot[12]\ : DFN1C0 - port map(D => N_195_i_0, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[12]_net_1\); - - start_snapshot_f0_RNO_0 : NOR3A - port map(A => counter_delta_f0_1_0_a2_6, B => - counter_delta_f0_1_0_a2_7, C => counter_delta_f0_1_0_a2_5, - Y => counter_delta_f0_1_0_a2_11); - - \counter_delta_snapshot_RNO_0[0]\ : AO1D - port map(A => N_505, B => delta_snapshot(0), C => N_429, Y - => counter_delta_snapshot_e0_i_0); - - \counter_delta_snapshot_RNO_2[10]\ : NOR3A - port map(A => \counter_delta_snapshot[10]_net_1\, B => - N_390, C => N_504_0, Y => N_477); - - \counter_delta_f0_RNITHHS2[17]\ : OR2 - port map(A => \counter_delta_f0[17]_net_1\, B => N_103, Y - => N_104); - - \counter_delta_f0_RNO[25]\ : XA1A - port map(A => N_66, B => \counter_delta_f0[25]_net_1\, C - => N_57, Y => N_32); - - \counter_delta_snapshot_RNO[12]\ : NOR3C - port map(A => N_496, B => counter_delta_snapshot_e12_i_0_0, - C => N_498, Y => N_195_i_0); - - start_snapshot_f2_temp : DFN1C0 - port map(D => start_snapshot_f2_temp3, CLK => lclk_c, CLR - => rstn, Q => \start_snapshot_f2_temp\); - - \counter_delta_f0_RNI1F97[22]\ : OR2 - port map(A => \counter_delta_f0[23]_net_1\, B => - \counter_delta_f0[22]_net_1\, Y => - counter_delta_f0_1_0_a2_2); - - \counter_delta_f0[20]\ : DFN1E0C0 - port map(D => counter_delta_f0_n20, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[20]_net_1\); - - \counter_delta_snapshot_RNO_4[13]\ : NOR2A - port map(A => N_393, B => - \counter_delta_snapshot[13]_net_1\, Y => - counter_delta_snapshot_e13_i_0_a2_0); - - \counter_delta_f0_RNIR697[12]\ : OR2 - port map(A => \counter_delta_f0[13]_net_1\, B => - \counter_delta_f0[12]_net_1\, Y => N_272); - - \counter_delta_snapshot_RNO_0[1]\ : NOR2 - port map(A => N_505, B => delta_snapshot(1), Y => N_433); - - \counter_delta_f0_RNIBUSO2[16]\ : OR2 - port map(A => \counter_delta_f0[16]_net_1\, B => N_102, Y - => N_103); - - \counter_delta_f0[17]\ : DFN1E0C0 - port map(D => counter_delta_f0_n17, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[17]_net_1\); - - \counter_delta_f0_RNO_0[26]\ : NOR2 - port map(A => \counter_delta_f0[25]_net_1\, B => N_66, Y - => N_80); - - \counter_delta_snapshot_RNO_4[15]\ : NOR2B - port map(A => \counter_delta_snapshot_i[15]\, B => N_395, Y - => counter_delta_snapshot_e15_i_0_a2_0); - - \counter_delta_snapshot_RNIT8M2[7]\ : XNOR2 - port map(A => \counter_delta_snapshot[7]_net_1\, B => - delta_snapshot(7), Y => N_164_i_i); - - \counter_delta_snapshot_RNIBJ31[13]\ : XNOR2 - port map(A => \counter_delta_snapshot[13]_net_1\, B => - delta_snapshot(13), Y => N_133_i_i); - - \counter_delta_f0[2]\ : DFN1E0C0 - port map(D => N_227, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[2]_net_1\); - - \counter_delta_snapshot_RNO[18]\ : OR3C - port map(A => N_174, B => N_175, C => N_176, Y => - \counter_delta_snapshot_RNO[18]_net_1\); - - \counter_delta_snapshot_RNO_4[14]\ : NOR2A - port map(A => N_394, B => - \counter_delta_snapshot[14]_net_1\, Y => - counter_delta_snapshot_e14_i_0_a2_0); - - \counter_delta_f0[21]\ : DFN1E0C0 - port map(D => N_276, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[21]_net_1\); - - \counter_delta_f0_RNO[1]\ : MX2 - port map(A => delta_f2_f0(1), B => N_107_i_i, S => N_57_0, - Y => N_23); - - \counter_delta_snapshot_RNIAPA3[15]\ : OR2A - port map(A => \counter_delta_snapshot_i[15]\, B => N_395, Y - => N_396); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_delta_snapshot_RNO_1[9]\ : AO1A - port map(A => \counter_delta_snapshot[9]_net_1\, B => - un2_coarse_time_0_0, C => N_469, Y => - counter_delta_snapshot_e9_i_0); - - \counter_delta_snapshot_RNO_4[2]\ : OR2 - port map(A => \counter_delta_snapshot[2]_net_1\, B => N_382, - Y => counter_delta_snapshot_e2_i_a2_0); - - \counter_delta_f0_RNI4PQ33[19]\ : OR2A - port map(A => N_105, B => \counter_delta_f0[19]_net_1\, Y - => N_106); - - start_snapshot_f0_RNO_4 : NOR3B - port map(A => \counter_delta_f0[0]_net_1\, B => - counter_delta_f0_1_0_a2_2_0, C => - \counter_delta_f0[3]_net_1\, Y => - counter_delta_f0_1_0_a2_8); - - \counter_delta_snapshot_RNO_1[3]\ : AO1A - port map(A => \counter_delta_snapshot[3]_net_1\, B => - un2_coarse_time_0_0, C => N_440, Y => - counter_delta_snapshot_e3_i_0); - - \counter_delta_snapshot_RNO_0[3]\ : NOR2 - port map(A => N_505, B => delta_snapshot(3), Y => N_442); - - \counter_delta_snapshot_RNIIQ45[23]\ : OR3 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => - \counter_delta_snapshot[23]_net_1\, Y => N_404); - - \counter_delta_snapshot_RNO_4[11]\ : NOR2B - port map(A => \counter_delta_snapshot_i[11]\, B => N_391, Y - => counter_delta_snapshot_e11_i_0_a2_0); - - \counter_delta_snapshot_RNO_1[23]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e23_0_0_a2_0, Y => - N_189); - - \counter_delta_f0_RNO[16]\ : XA1A - port map(A => \counter_delta_f0[16]_net_1\, B => N_102, C - => N_57, Y => counter_delta_f0_n16); - - \counter_delta_snapshot_RNO_1[0]\ : NOR2A - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[0]_net_1\, Y => N_429); - - \counter_delta_snapshot_RNIFVC[5]\ : NOR2A - port map(A => \counter_delta_snapshot_i[5]\, B => - \counter_delta_snapshot[6]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_2); - - \counter_delta_f0_RNO[8]\ : MX2 - port map(A => delta_f2_f0(8), B => N_99_i_i, S => N_57, Y - => N_15); - - \op_eq.start_snapshot_f12_0_a2_RNO_9\ : XNOR2 - port map(A => \counter_delta_f0[6]_net_1\, B => - delta_f2_f1(6), Y => N_81_i_i_0); - - \counter_delta_snapshot_RNI4BQ[11]\ : NOR3B - port map(A => \counter_delta_snapshot_i[11]\, B => - counter_delta_snapshot_e12_i_0_o2_m6_e_2, C => - \counter_delta_snapshot[3]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_5); - - \counter_delta_snapshot_RNO_1[25]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[25]_net_1\, Y => N_422); - - \counter_delta_snapshot_RNO[2]\ : NOR3 - port map(A => N_437, B => counter_delta_snapshot_e2_i_0, C - => N_438, Y => N_54); - - \counter_delta_snapshot[26]\ : DFN1C0 - port map(D => counter_delta_snapshot_e26, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[26]_net_1\); - - \counter_delta_f0_RNIHVOE3[22]\ : OR2 - port map(A => \counter_delta_f0[22]_net_1\, B => N_60, Y - => N_62); - - \start_snapshot_f1\ : DFN1C0 - port map(D => start_snapshot_f12, CLK => lclk_c, CLR => - rstn, Q => start_snapshot_f1); - - \counter_delta_snapshot_RNIA82J_0[26]\ : OA1A - port map(A => N_406, B => un2_coarse_time_0, C => - \counter_delta_snapshot[26]_net_1\, Y => - counter_delta_snapshot_e26); - - \counter_delta_f0_RNI184B3[21]\ : OR2 - port map(A => \counter_delta_f0[21]_net_1\, B => N_58, Y - => N_60); - - \counter_delta_snapshot_RNO_1[7]\ : AO1A - port map(A => \counter_delta_snapshot[7]_net_1\, B => - un2_coarse_time_0_0, C => N_460, Y => - counter_delta_snapshot_e7_i_0); - - \counter_delta_f0_RNO[5]\ : MX2 - port map(A => delta_f2_f0(5), B => N_117_i_i, S => N_57_0, - Y => N_230); - - \counter_delta_snapshot_RNO_1[24]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e24_0_0_a2_0, Y => - N_192); - - \counter_delta_snapshot_RNO[6]\ : NOR3 - port map(A => N_457, B => counter_delta_snapshot_e6_i_0, C - => N_458, Y => \counter_delta_snapshot_RNO[6]_net_1\); - - \counter_delta_f0_RNIFOAC1[6]\ : OR3A - port map(A => N_55, B => \counter_delta_f0[5]_net_1\, C => - \counter_delta_f0[6]_net_1\, Y => N_59); - - \counter_delta_snapshot_RNO_4[12]\ : NOR2A - port map(A => \counter_delta_snapshot_RNI01E2[7]_net_1\, B - => \counter_delta_snapshot[12]_net_1\, Y => - counter_delta_snapshot_e12_i_0_a2_0); - - \counter_delta_snapshot[24]\ : DFN1C0 - port map(D => counter_delta_snapshot_e24, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[24]_net_1\); - - \op_eq.start_snapshot_f12_0_a2_RNO_6\ : XNOR2 - port map(A => \counter_delta_f0[2]_net_1\, B => - delta_f2_f1(2), Y => N_274_i_0); - - \counter_delta_snapshot_RNO_3[13]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e13_i_0_a2_0, Y => - N_285); - - \counter_delta_f0_RNO[4]\ : MX2 - port map(A => delta_f2_f0(4), B => N_116_i_i, S => N_57_0, - Y => N_229); - - \counter_delta_snapshot_RNO_3[3]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e3_i_a2_0, Y => N_440); - - \counter_delta_snapshot_RNO_1[21]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e21_0_0_a2_0, Y => - N_183); - - \op_eq.start_snapshot_f12_0_a2_RNO_3\ : XNOR2 - port map(A => \counter_delta_f0[9]_net_1\, B => - delta_f2_f1(9), Y => N_84_i_i_0); - - \counter_delta_snapshot_RNIEUN[3]\ : OR2 - port map(A => \counter_delta_snapshot[3]_net_1\, B => N_383, - Y => N_384); - - \counter_delta_f0[12]\ : DFN1E0C0 - port map(D => counter_delta_f0_n12, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[12]_net_1\); - - \counter_delta_snapshot_RNIVEJ5_0[25]\ : NOR2 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - N_405, Y => N_406_0); - - \counter_delta_f0_RNIG5603[18]\ : NOR2 - port map(A => \counter_delta_f0[18]_net_1\, B => N_104, Y - => N_105); - - \counter_delta_snapshot_RNO_3[15]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e15_i_0_a2_0, Y => - N_478); - - \counter_delta_snapshot_RNO_1[6]\ : AO1A - port map(A => \counter_delta_snapshot[6]_net_1\, B => - un2_coarse_time_0_0, C => N_455, Y => - counter_delta_snapshot_e6_i_0); - - \counter_delta_snapshot_RNI96M4[21]\ : OR3 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - \counter_delta_snapshot[21]_net_1\, Y => N_402); - - \counter_delta_f0_RNO[10]\ : XA1 - port map(A => N_65, B => \counter_delta_f0[10]_net_1\, C - => N_57_0, Y => N_19); - - \op_eq.start_snapshot_f12_0_a2_RNO_10\ : XA1A - port map(A => delta_f2_f1(1), B => - \counter_delta_f0[1]_net_1\, C => N_111_i_i_0, Y => - start_snapshot_f12_0_a2_1); - - \counter_delta_snapshot_RNO_3[22]\ : NOR2B - port map(A => \counter_delta_snapshot[22]_net_1\, B => - N_402, Y => counter_delta_snapshot_e22_0_0_a2_0); - - \counter_delta_snapshot_RNO_2[8]\ : NOR3B - port map(A => N_388, B => \counter_delta_snapshot[8]_net_1\, - C => N_504_0, Y => N_468); - - \counter_delta_snapshot_RNIO4C5[24]\ : OR2 - port map(A => \counter_delta_snapshot[24]_net_1\, B => - N_404, Y => N_405); - - \counter_delta_snapshot_RNIHOK2[1]\ : XNOR2 - port map(A => \counter_delta_snapshot[1]_net_1\, B => - delta_snapshot(1), Y => N_137_i_i); - - \counter_delta_snapshot_RNO_3[14]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e14_i_0_a2_0, Y => - N_484); - - \counter_delta_f0[3]\ : DFN1E0C0 - port map(D => N_228, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[3]_net_1\); - - \op_eq.start_snapshot_f12_0_a2_RNO_7\ : XA1A - port map(A => delta_f2_f1(4), B => - \counter_delta_f0[4]_net_1\, C => N_113_i_i_0, Y => - start_snapshot_f12_0_a2_2); - - \counter_delta_snapshot_RNO_0[8]\ : NOR2 - port map(A => N_505, B => delta_snapshot(8), Y => N_467); - - \counter_delta_snapshot_RNO_0[4]\ : OR2 - port map(A => N_505, B => delta_snapshot(4), Y => N_447); - - \counter_delta_f0_RNO_0[8]\ : AX1B - port map(A => N_59, B => \counter_delta_f0[7]_net_1\, C => - \counter_delta_f0[8]_net_1\, Y => N_99_i_i); - - \counter_delta_f0[24]\ : DFN1E0C0 - port map(D => N_30, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[24]_net_1\); - - \counter_delta_snapshot_RNO_1[22]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[22]_net_1\, Y => N_187); - - \counter_delta_f0_RNO[23]\ : XA1A - port map(A => N_62, B => \counter_delta_f0[23]_net_1\, C - => N_57, Y => N_28); - - \counter_delta_snapshot_RNO_3[11]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e11_i_0_a2_0, Y => - N_499); - - \counter_delta_snapshot_RNO_2[1]\ : NOR3A - port map(A => \counter_delta_snapshot[1]_net_1\, B => - \counter_delta_snapshot[0]_net_1\, C => N_504, Y => N_435); - - \counter_delta_f0_RNO_0[6]\ : AX1 - port map(A => \counter_delta_f0[5]_net_1\, B => N_55, C => - \counter_delta_f0[6]_net_1\, Y => N_87_i_i); - - \counter_delta_f0_RNO_0[2]\ : AX1B - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[1]_net_1\, C => - \counter_delta_f0[2]_net_1\, Y => N_114_i_i); - - \counter_delta_snapshot_RNO[22]\ : OR3C - port map(A => N_186, B => N_187, C => N_188, Y => - counter_delta_snapshot_e22); - - \counter_delta_snapshot_RNO[1]\ : NOR3 - port map(A => N_433, B => counter_delta_snapshot_e1_i_0, C - => N_435, Y => \counter_delta_snapshot_RNO[1]_net_1\); - - \counter_delta_snapshot_RNO[14]\ : NOR3C - port map(A => N_486, B => counter_delta_snapshot_e14_i_0_0, - C => N_488, Y => N_6_i_0); - - \counter_delta_f0_RNIQA8L2[15]\ : OR2 - port map(A => \counter_delta_f0[15]_net_1\, B => N_101, Y - => N_102); - - \counter_delta_f0_RNIDUTA[14]\ : NOR3 - port map(A => \counter_delta_f0[14]_net_1\, B => - \counter_delta_f0[15]_net_1\, C => - \counter_delta_f0[20]_net_1\, Y => - counter_delta_f0_1_0_a2_3); - - \counter_delta_snapshot_RNO_2[7]\ : NOR3B - port map(A => N_387, B => \counter_delta_snapshot[7]_net_1\, - C => N_504, Y => N_463); - - \counter_delta_f0_RNO[3]\ : MX2 - port map(A => delta_f2_f0(3), B => N_115_i_i, S => N_57_0, - Y => N_228); - - \counter_delta_snapshot_RNO_2[23]\ : OA1 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => - \counter_delta_snapshot[23]_net_1\, Y => - counter_delta_snapshot_e23_0_0_a2_0); - - \counter_delta_snapshot_RNIL8L2[3]\ : XNOR2 - port map(A => \counter_delta_snapshot[3]_net_1\, B => - delta_snapshot(3), Y => N_506_i); - - \start_snapshot_f2\ : DFN1C0 - port map(D => start_snapshot_f22, CLK => lclk_c, CLR => - rstn, Q => start_snapshot_f2); - - \counter_delta_snapshot_RNIPOH[2]\ : OR2A - port map(A => N_382, B => \counter_delta_snapshot[2]_net_1\, - Y => N_383); - - \counter_delta_snapshot_RNIFGK2[0]\ : XNOR2 - port map(A => \counter_delta_snapshot[0]_net_1\, B => - delta_snapshot(0), Y => N_136_i_i); - - \counter_delta_snapshot_RNO_2[6]\ : NOR3A - port map(A => \counter_delta_snapshot[6]_net_1\, B => N_386, - C => N_504, Y => N_458); - - \counter_delta_snapshot_RNO_4[10]\ : OR2A - port map(A => N_390, B => - \counter_delta_snapshot[10]_net_1\, Y => - counter_delta_snapshot_e10_i_a2_0); - - \op_eq.start_snapshot_f12_0_a2_RNO_5\ : XNOR2 - port map(A => \counter_delta_f0[8]_net_1\, B => - delta_f2_f1(8), Y => N_83_i_i_0); - - \counter_delta_f0[25]\ : DFN1E0C0 - port map(D => N_32, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[25]_net_1\); - - \counter_delta_snapshot_RNIE8T[21]\ : NOR3A - port map(A => start_snapshot_f22_0_a2_11_0_a2_3, B => - \counter_delta_snapshot[21]_net_1\, C => - \counter_delta_snapshot[20]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_5); - - \counter_delta_snapshot_RNO_2[25]\ : OR2A - port map(A => N_406, B => N_504, Y => N_423); - - \counter_delta_snapshot_RNIFCE[19]\ : NOR2 - port map(A => \counter_delta_snapshot[18]_net_1\, B => - \counter_delta_snapshot[19]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_1); - - \counter_delta_snapshot_RNO_3[12]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e12_i_0_a2_0, Y => - N_493); - - coarse_time_0_r_RNI3F7D : OR2B - port map(A => coarse_time_0_r_i, B => coarse_time(0), Y => - un2_coarse_time_0); - - \counter_delta_f0_RNO[9]\ : MX2 - port map(A => delta_f2_f0(9), B => N_324_i, S => N_57, Y - => N_17); - - \counter_delta_f0[16]\ : DFN1E0C0 - port map(D => counter_delta_f0_n16, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[16]_net_1\); - - \counter_delta_snapshot_RNO_2[24]\ : NOR2B - port map(A => \counter_delta_snapshot[24]_net_1\, B => - N_404, Y => counter_delta_snapshot_e24_0_0_a2_0); - - start_snapshot_f0_RNO_3 : NOR3A - port map(A => N_273, B => \counter_delta_f0[2]_net_1\, C - => \counter_delta_f0[1]_net_1\, Y => - counter_delta_f0_1_0_a2_6); - - \counter_delta_snapshot_RNIGJOA[3]\ : NOR3C - port map(A => N_506_i, B => N_166_i_i, C => - un12_start_snapshot_fothers_temp_NE_7, Y => - un12_start_snapshot_fothers_temp_NE_11); - - \counter_delta_snapshot_RNO_3[8]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e8_i_a2_0, Y => N_465); - - \counter_delta_snapshot_RNO_3[20]\ : NOR2B - port map(A => \counter_delta_snapshot[20]_net_1\, B => - N_400, Y => counter_delta_snapshot_e20_i_i_a2_0); - - \counter_delta_snapshot_RNO_3[16]\ : NOR2B - port map(A => \counter_delta_snapshot[16]_net_1\, B => - N_396, Y => counter_delta_snapshot_e16_i_i_a2_0); - - \counter_delta_snapshot_RNO_3[9]\ : OA1C - port map(A => N_406, B => - \counter_delta_snapshot[26]_net_1\, C => - counter_delta_snapshot_e9_i_a2_0, Y => N_469); - - \counter_delta_snapshot_RNO_2[3]\ : NOR3A - port map(A => \counter_delta_snapshot[3]_net_1\, B => N_383, - C => N_504, Y => N_443); - - \counter_delta_f0_RNO[19]\ : XA1 - port map(A => \counter_delta_f0[19]_net_1\, B => N_105, C - => N_57, Y => counter_delta_f0_n19); - - \counter_delta_snapshot_RNI1PM2[9]\ : XNOR2 - port map(A => \counter_delta_snapshot[9]_net_1\, B => - delta_snapshot(9), Y => N_166_i_i); - - \counter_delta_snapshot_RNI17L2[12]\ : OR2 - port map(A => \counter_delta_snapshot_RNI01E2[7]_net_1\, B - => \counter_delta_snapshot[12]_net_1\, Y => N_393); - - \counter_delta_f0_RNO_0[1]\ : XNOR2 - port map(A => \counter_delta_f0[1]_net_1\, B => - \counter_delta_f0[0]_net_1\, Y => N_107_i_i); - - \counter_delta_snapshot_RNO_2[21]\ : OA1 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - \counter_delta_snapshot[21]_net_1\, Y => - counter_delta_snapshot_e21_0_0_a2_0); - - \counter_delta_f0_RNIDGAA2[12]\ : OR2 - port map(A => \counter_delta_f0[12]_net_1\, B => N_98, Y - => N_99); - - \counter_delta_snapshot[20]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[20]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[20]_net_1\); - - \counter_delta_f0[0]\ : DFN1E0C0 - port map(D => N_21, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[0]_net_1\); - - \counter_delta_f0[23]\ : DFN1E0C0 - port map(D => N_28, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[23]_net_1\); - - \counter_delta_f0_RNO[22]\ : XA1A - port map(A => N_60, B => \counter_delta_f0[22]_net_1\, C - => N_57, Y => N_277); - - \counter_delta_f0[8]\ : DFN1E0C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[8]_net_1\); - - coarse_time_0_r_RNI3F7D_0 : OR2B - port map(A => coarse_time_0_r_i, B => coarse_time(0), Y => - un2_coarse_time_0_0); - - \counter_delta_snapshot_RNO_1[20]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[20]_net_1\, Y => N_181); - - \counter_delta_snapshot_RNO_0[9]\ : NOR2 - port map(A => N_505, B => delta_snapshot(9), Y => N_471); - - \counter_delta_f0_RNO[2]\ : MX2 - port map(A => delta_f2_f0(2), B => N_114_i_i, S => N_57_0, - Y => N_227); - - start_snapshot_f0_RNO_2 : NOR3B - port map(A => counter_delta_f0_1_0_a2_3, B => - counter_delta_f0_1_0_a2_8, C => counter_delta_f0_1_8, Y - => counter_delta_f0_1_0_a2_12); - - \counter_delta_snapshot_RNO_1[4]\ : OA1A - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[4]_net_1\, C => N_445, Y => - counter_delta_snapshot_e4_i_0); - - \counter_delta_f0_RNIN697[10]\ : OR2 - port map(A => \counter_delta_f0[11]_net_1\, B => - \counter_delta_f0[10]_net_1\, Y => - counter_delta_f0_1_0_a2_5); - - start_snapshot_fothers_temp_RNISVED5 : AOI1B - port map(A => sample_f0_val_0, B => - counter_delta_f0lde_i_a2_0_1_i, C => N_57_0, Y => N_9_0); - - \counter_delta_snapshot_RNIM1C5[5]\ : XA1 - port map(A => delta_snapshot(5), B => - \counter_delta_snapshot_i[5]\, C => N_164_i_i, Y => - un12_start_snapshot_fothers_temp_NE_5); - - start_snapshot_f0_RNO : NOR3C - port map(A => counter_delta_f0_1_0_a2_11, B => - counter_delta_f0_1_0_a2_10, C => - counter_delta_f0_1_0_a2_12, Y => counter_delta_f0_1); - - \counter_delta_snapshot_RNO_2[22]\ : OR3 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => N_504, Y => - N_188); - - \counter_delta_snapshot_0[26]\ : DFN1C0 - port map(D => counter_delta_snapshot_e26, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot_0[26]_net_1\); - - start_snapshot_f2_temp_RNIQ573 : OR2 - port map(A => \start_snapshot_f2_temp\, B => - start_snapshot_f22_10, Y => start_snapshot_f22_0_a2_0); - - \op_eq.start_snapshot_f12_0_a2_RNO_8\ : XNOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => - delta_f2_f1(7), Y => N_82_i_i_0); - - \counter_delta_snapshot_RNO[9]\ : NOR3 - port map(A => N_471, B => counter_delta_snapshot_e9_i_0, C - => N_472, Y => \counter_delta_snapshot_RNO[9]_net_1\); - - \counter_delta_f0[1]\ : DFN1E0C0 - port map(D => N_23, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[1]_net_1\); - - \counter_delta_snapshot[22]\ : DFN1C0 - port map(D => counter_delta_snapshot_e22, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[22]_net_1\); - - \counter_delta_snapshot_RNIU8TJ[2]\ : NOR3C - port map(A => un12_start_snapshot_fothers_temp_NE_5, B => - un12_start_snapshot_fothers_temp_NE_4, C => - un12_start_snapshot_fothers_temp_NE_11, Y => - un12_start_snapshot_fothers_temp_NE_13); - - \counter_delta_f0_RNO[15]\ : XA1A - port map(A => \counter_delta_f0[15]_net_1\, B => N_101, C - => N_57_0, Y => counter_delta_f0_n15); - - \counter_delta_f0[19]\ : DFN1E0C0 - port map(D => counter_delta_f0_n19, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[19]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \counter_delta_snapshot_RNO_0[5]\ : OR2 - port map(A => N_505, B => delta_snapshot(5), Y => N_452); - - \counter_delta_snapshot_RNILUL[24]\ : OR3 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - \counter_delta_snapshot[24]_net_1\, C => - \counter_delta_snapshot[26]_net_1\, Y => - start_snapshot_f22_10); - - \counter_delta_f0_RNO[24]\ : XA1A - port map(A => N_64, B => \counter_delta_f0[24]_net_1\, C - => N_57, Y => N_30); - - \counter_delta_snapshot_RNO[3]\ : NOR3 - port map(A => N_442, B => counter_delta_snapshot_e3_i_0, C - => N_443, Y => \counter_delta_snapshot_RNO[3]_net_1\); - - start_snapshot_f2_temp_RNO_0 : OR3B - port map(A => start_snapshot_f22_0_a2_11_0_a2_4, B => - start_snapshot_f22_0_a2_11_0_a2_5, C => - start_snapshot_f22_10, Y => - start_snapshot_f2_temp3_0_a2_0); - - \counter_delta_snapshot_RNI6J33[14]\ : OR2 - port map(A => \counter_delta_snapshot[14]_net_1\, B => - N_394, Y => N_395); - - \counter_delta_snapshot[6]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[6]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[6]_net_1\); - - \counter_delta_f0[18]\ : DFN1E0C0 - port map(D => counter_delta_f0_n18, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[18]_net_1\); - - \op_eq.start_snapshot_f12_0_a2_RNO_1\ : NOR3C - port map(A => N_83_i_i_0, B => N_274_i_0, C => - start_snapshot_f12_0_a2_2, Y => start_snapshot_f12_0_a2_6); - - \op_eq.start_snapshot_f12_0_a2_RNO\ : AND2 - port map(A => start_snapshot_f12_0_a2_7, B => - start_snapshot_f12_0_a2_6, Y => start_snapshot_f12_0_a2_8); - - \counter_delta_snapshot_RNO_3[10]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e10_i_a2_0, Y => N_474); - - \counter_delta_f0_RNILNLC[4]\ : NOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => - \counter_delta_f0[4]_net_1\, Y => N_273); - - \counter_delta_snapshot_RNIK672[12]\ : XA1A - port map(A => delta_snapshot(12), B => - \counter_delta_snapshot[12]_net_1\, C => N_133_i_i, Y => - un12_start_snapshot_fothers_temp_NE_0); - - \counter_delta_f0[6]\ : DFN1E0C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[6]_net_1\); - - \counter_delta_snapshot[8]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[8]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[8]_net_1\); - - \counter_delta_snapshot_RNO_0[18]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e18_i_i_a2_0, Y => - N_174); - - \counter_delta_snapshot_RNIQHC5[6]\ : XA1A - port map(A => delta_snapshot(6), B => - \counter_delta_snapshot[6]_net_1\, C => N_509_i, Y => - un12_start_snapshot_fothers_temp_NE_7); - - \counter_delta_f0_RNO[21]\ : XA1A - port map(A => N_58, B => \counter_delta_f0[21]_net_1\, C - => N_57, Y => N_276); - - \counter_delta_snapshot_RNIVGM2[8]\ : XNOR2 - port map(A => \counter_delta_snapshot[8]_net_1\, B => - delta_snapshot(8), Y => N_509_i); - - \counter_delta_snapshot_RNO_4[7]\ : OR2 - port map(A => \counter_delta_snapshot[7]_net_1\, B => N_387, - Y => counter_delta_snapshot_e7_i_a2_0); - - \counter_delta_f0_RNIIGF73[20]\ : OR2 - port map(A => \counter_delta_f0[20]_net_1\, B => N_106, Y - => N_58); - - \counter_delta_snapshot_RNIGDK[4]\ : NOR3 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - \counter_delta_snapshot[4]_net_1\, C => - \counter_delta_snapshot[9]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_4); - - \counter_delta_snapshot[4]\ : DFN1C0 - port map(D => N_375_i_0, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[4]_net_1\); - - \counter_delta_snapshot_RNO[24]\ : OAI1 - port map(A => N_405, B => N_504, C => - counter_delta_snapshot_e24_0_0_0, Y => - counter_delta_snapshot_e24); - - \counter_delta_snapshot[15]\ : DFN1P0 - port map(D => N_8_i_0, CLK => lclk_c, PRE => rstn, Q => - \counter_delta_snapshot_i[15]\); - - \counter_delta_snapshot_RNO_1[1]\ : OA1B - port map(A => \counter_delta_snapshot[0]_net_1\, B => - un2_coarse_time_0, C => \counter_delta_snapshot[1]_net_1\, - Y => counter_delta_snapshot_e1_i_0); - - \counter_delta_snapshot_RNI5NB[1]\ : NOR2 - port map(A => \counter_delta_snapshot[1]_net_1\, B => - \counter_delta_snapshot[0]_net_1\, Y => N_382); - - \counter_delta_snapshot_RNO_3[2]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e2_i_a2_0, Y => N_239); - - \counter_delta_snapshot_RNI4I74[19]\ : OR3 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot[19]_net_1\, Y => N_400); - - \counter_delta_f0[9]\ : DFN1E0C0 - port map(D => N_17, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[9]_net_1\); - - \counter_delta_snapshot_RNO[0]\ : OA1C - port map(A => \counter_delta_snapshot[0]_net_1\, B => - N_504_0, C => counter_delta_snapshot_e0_i_0, Y => - \counter_delta_snapshot_RNO[0]_net_1\); - - \counter_delta_f0_RNIR3VD2[13]\ : OR2 - port map(A => \counter_delta_f0[13]_net_1\, B => N_99, Y - => N_100); - - \counter_delta_f0_RNIANJH2[14]\ : OR2 - port map(A => \counter_delta_f0[14]_net_1\, B => N_100, Y - => N_101); - - \counter_delta_snapshot_RNO_2[20]\ : OR3 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => N_504, Y => - N_182); - - \counter_delta_f0_RNIP7MC[6]\ : OR2 - port map(A => \counter_delta_f0[7]_net_1\, B => - \counter_delta_f0[6]_net_1\, Y => - counter_delta_f0_1_0_a2_7); - - \counter_delta_snapshot_RNO_4[5]\ : NOR2B - port map(A => \counter_delta_snapshot_i[5]\, B => N_385, Y - => counter_delta_snapshot_e5_i_a2_0); - - \counter_delta_snapshot_RNO_1[18]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[18]_net_1\, Y => N_175); - - \op_eq.start_snapshot_f12_0_a2\ : AND2 - port map(A => N_322, B => start_snapshot_f12_0_a2_8, Y => - start_snapshot_f12); - - \counter_delta_f0_RNO_0[9]\ : XNOR2 - port map(A => \counter_delta_f0[9]_net_1\, B => N_63, Y => - N_324_i); - - \counter_delta_snapshot_RNIVEJ5[25]\ : NOR2 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - N_405, Y => N_406); - - \op_eq.start_snapshot_f12_0_a2_RNO_11\ : XNOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => - delta_f2_f1(5), Y => N_113_i_i_0); - - \counter_delta_snapshot[11]\ : DFN1P0 - port map(D => N_22_i_0, CLK => lclk_c, PRE => rstn, Q => - \counter_delta_snapshot_i[11]\); - - \counter_delta_snapshot_RNO_4[9]\ : OR2 - port map(A => \counter_delta_snapshot[9]_net_1\, B => N_389, - Y => counter_delta_snapshot_e9_i_a2_0); - - \counter_delta_f0_RNO_0[5]\ : XOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => N_55, Y => - N_117_i_i); - - \counter_delta_f0_RNIRTBT3[3]\ : OR3C - port map(A => un1_start_snapshot_f22_i_a2_0_4, B => - un1_start_snapshot_f22_i_a2_0_5, C => - counter_delta_f0lde_i_a2_0_1_3, Y => - counter_delta_f0lde_i_a2_0_1_i); - - \counter_delta_snapshot_RNO_1[8]\ : AO1A - port map(A => \counter_delta_snapshot[8]_net_1\, B => - un2_coarse_time_0_0, C => N_465, Y => - counter_delta_snapshot_e8_i_0); - - \counter_delta_f0_RNI59VI[2]\ : OR3 - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[1]_net_1\, C => - \counter_delta_f0[2]_net_1\, Y => N_89); - - \op_eq.start_snapshot_f12_0_a2_RNO_12\ : XNOR2 - port map(A => \counter_delta_f0[3]_net_1\, B => - delta_f2_f1(3), Y => N_111_i_i_0); - - \counter_delta_snapshot_RNO_2[5]\ : OR3 - port map(A => N_385, B => \counter_delta_snapshot_i[5]\, C - => N_504, Y => N_453); - - \counter_delta_snapshot_RNO[11]\ : OR3C - port map(A => N_501, B => counter_delta_snapshot_e11_i_0_0, - C => N_503, Y => N_22_i_0); - - \counter_delta_snapshot[18]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[18]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[18]_net_1\); - - \op_eq.start_snapshot_f12_0_a2_RNO_4\ : NOR3C - port map(A => N_82_i_i_0, B => N_81_i_i_0, C => - start_snapshot_f12_0_a2_1, Y => start_snapshot_f12_0_a2_5); - - \counter_delta_snapshot_RNO_2[2]\ : NOR3B - port map(A => N_382, B => \counter_delta_snapshot[2]_net_1\, - C => N_504, Y => N_438); - - \counter_delta_snapshot[13]\ : DFN1C0 - port map(D => N_26_i_0, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[13]_net_1\); - - \counter_delta_snapshot_RNO_2[4]\ : OR3A - port map(A => \counter_delta_snapshot[4]_net_1\, B => N_384, - C => N_504, Y => N_448); - - \counter_delta_snapshot_RNIL5P3[17]\ : OR3 - port map(A => N_396, B => - \counter_delta_snapshot[16]_net_1\, C => - \counter_delta_snapshot[17]_net_1\, Y => N_398); - - \counter_delta_snapshot_RNIS3O3[14]\ : XA1A - port map(A => delta_snapshot(14), B => - \counter_delta_snapshot[14]_net_1\, C => N_136_i_i, Y => - un12_start_snapshot_fothers_temp_NE_1); - - \counter_delta_f0_RNO[17]\ : XA1A - port map(A => \counter_delta_f0[17]_net_1\, B => N_103, C - => N_57, Y => counter_delta_f0_n17); - - \counter_delta_snapshot_RNO_0[23]\ : AOI1B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[23]_net_1\, C => N_189, Y => - counter_delta_snapshot_e23_0_0_0); - - \counter_delta_f0_RNO[13]\ : XA1A - port map(A => \counter_delta_f0[13]_net_1\, B => N_99, C - => N_57_0, Y => counter_delta_f0_n13); - - \counter_delta_snapshot_RNO_0[13]\ : OR2 - port map(A => N_505, B => delta_snapshot(13), Y => N_287); - - \counter_delta_snapshot_RNO[8]\ : NOR3 - port map(A => N_467, B => counter_delta_snapshot_e8_i_0, C - => N_468, Y => \counter_delta_snapshot_RNO[8]_net_1\); - - \counter_delta_f0_RNO[0]\ : MX2B - port map(A => delta_f2_f0(0), B => - \counter_delta_f0[0]_net_1\, S => N_57_0, Y => N_21); - - \counter_delta_snapshot[1]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[1]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[1]_net_1\); - - \counter_delta_f0[22]\ : DFN1E0C0 - port map(D => N_277, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[22]_net_1\); - - \counter_delta_snapshot_RNO_0[25]\ : OR2B - port map(A => N_405, B => - \counter_delta_snapshot[25]_net_1\, Y => N_421); - - \counter_delta_snapshot_RNO_0[15]\ : OR2 - port map(A => N_505, B => delta_snapshot(15), Y => N_480); - - \counter_delta_snapshot_RNIFJ31[15]\ : XOR2 - port map(A => \counter_delta_snapshot_i[15]\, B => - delta_snapshot(15), Y => - \counter_delta_snapshot_RNIFJ31[15]_net_1\); - - \counter_delta_snapshot_RNO_0[24]\ : AOI1B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[24]_net_1\, C => N_192, Y => - counter_delta_snapshot_e24_0_0_0); - - start_snapshot_f2_temp_RNI2715 : OR3B - port map(A => start_snapshot_f22_0_a2_11_0_a2_4, B => - start_snapshot_f22_0_a2_11_0_a2_5, C => - start_snapshot_f22_0_a2_0, Y => start_snapshot_f22_0_a2_1); - - \counter_delta_snapshot_RNO_0[14]\ : OR2 - port map(A => N_505, B => delta_snapshot(14), Y => N_486); - - start_snapshot_fothers_temp_RNO : NOR2 - port map(A => start_snapshot_f22, B => - counter_delta_f0lde_i_a2_0_1_i, Y => N_284); - - \counter_delta_snapshot_RNIM672[11]\ : XA1 - port map(A => delta_snapshot(11), B => - \counter_delta_snapshot_i[11]\, C => - \counter_delta_snapshot_RNIFJ31[15]_net_1\, Y => - un12_start_snapshot_fothers_temp_NE_3); - - \counter_delta_snapshot_RNIUFH7[1]\ : NOR3C - port map(A => N_507_i, B => N_137_i_i, C => - un12_start_snapshot_fothers_temp_NE_3, Y => - un12_start_snapshot_fothers_temp_NE_9); - - \counter_delta_f0_RNIK9132[10]\ : OR2A - port map(A => N_65, B => \counter_delta_f0[10]_net_1\, Y - => N_67); - - \counter_delta_snapshot_RNO[16]\ : OR3C - port map(A => N_168, B => N_169, C => N_170, Y => - \counter_delta_snapshot_RNO[16]_net_1\); - - \counter_delta_f0[7]\ : DFN1E0C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[7]_net_1\); - - \counter_delta_snapshot_RNO_0[21]\ : AOI1B - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[21]_net_1\, C => N_183, Y => - counter_delta_snapshot_e21_0_0_0); - - \counter_delta_f0[5]\ : DFN1E0C0 - port map(D => N_230, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[5]_net_1\); - - coarse_time_0_r : DFN1P0 - port map(D => coarse_time_i(0), CLK => lclk_c, PRE => rstn, - Q => coarse_time_0_r_i); - - \counter_delta_snapshot_RNO_4[4]\ : NOR2A - port map(A => N_384, B => \counter_delta_snapshot[4]_net_1\, - Y => counter_delta_snapshot_e4_i_a2_0); - - \counter_delta_snapshot_RNO_3[6]\ : OA1C - port map(A => N_406, B => - \counter_delta_snapshot[26]_net_1\, C => - counter_delta_snapshot_e6_i_a2_0, Y => N_455); - - \counter_delta_f0[10]\ : DFN1E0C0 - port map(D => N_19, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[10]_net_1\); - - \counter_delta_snapshot_RNO_0[11]\ : OR2 - port map(A => N_505, B => delta_snapshot(11), Y => N_501); - - \counter_delta_f0_RNO[6]\ : MX2 - port map(A => delta_f2_f0(6), B => N_87_i_i, S => N_57, Y - => N_11); - - \counter_delta_snapshot[5]\ : DFN1P0 - port map(D => N_376_i_0, CLK => lclk_c, PRE => rstn, Q => - \counter_delta_snapshot_i[5]\); - - \counter_delta_snapshot_RNO_3[4]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e4_i_a2_0, Y => - N_445); - - \counter_delta_snapshot_RNO_2[18]\ : OR3 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => N_504, Y => - N_176); - - \counter_delta_snapshot[0]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[0]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[0]_net_1\); - - \counter_delta_f0_RNI6F97[26]\ : OR2 - port map(A => \counter_delta_f0[26]_net_1\, B => - \counter_delta_f0[24]_net_1\, Y => - counter_delta_f0_1_0_a2_0); - - \op_eq.start_snapshot_f12_0_a2_RNO_0\ : NOR3C - port map(A => N_108_i_i_0, B => N_84_i_i_0, C => - start_snapshot_f12_0_a2_5, Y => start_snapshot_f12_0_a2_7); - - \counter_delta_snapshot[7]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[7]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[7]_net_1\); - - \counter_delta_snapshot_RNO_1[13]\ : OA1A - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[13]_net_1\, C => N_285, Y => - counter_delta_snapshot_e13_i_0_0); - - \counter_delta_snapshot_RNO_2[9]\ : NOR3B - port map(A => N_389, B => \counter_delta_snapshot[9]_net_1\, - C => N_504_0, Y => N_472); - - start_snapshot_fothers_temp_RNIB7FD1_0 : OAI1 - port map(A => start_snapshot_f22, B => - \start_snapshot_fothers_temp\, C => sample_f2_val, Y => - N_57_0); - - \counter_delta_f0_RNO[12]\ : XA1A - port map(A => \counter_delta_f0[12]_net_1\, B => N_98, C - => N_57_0, Y => counter_delta_f0_n12); - - \counter_delta_snapshot[9]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[9]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[9]_net_1\); - - \counter_delta_snapshot_RNO_1[15]\ : AOI1B - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot_i[15]\, C => N_478, Y => - counter_delta_snapshot_e15_i_0_0); - - \counter_delta_snapshot_RNO[10]\ : NOR3 - port map(A => N_476, B => counter_delta_snapshot_e10_i_0, C - => N_477, Y => \counter_delta_snapshot_RNO[10]_net_1\); - - \counter_delta_f0[11]\ : DFN1E0C0 - port map(D => N_275, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[11]_net_1\); - - \counter_delta_snapshot_RNO_0[22]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e22_0_0_a2_0, Y => - N_186); - - \counter_delta_f0_RNIKE2M3[24]\ : OR2 - port map(A => \counter_delta_f0[24]_net_1\, B => N_64, Y - => N_66); - - \counter_delta_snapshot_RNO_0[12]\ : OR2 - port map(A => N_505, B => delta_snapshot(12), Y => N_496); - - \counter_delta_snapshot_RNO[15]\ : OR3C - port map(A => N_480, B => counter_delta_snapshot_e15_i_0_0, - C => N_482, Y => N_8_i_0); - - \counter_delta_snapshot_RNO_1[14]\ : OA1A - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[14]_net_1\, C => N_484, Y => - counter_delta_snapshot_e14_i_0_0); - - start_snapshot_fothers_temp_RNIB7FD1 : OAI1 - port map(A => start_snapshot_f22, B => - \start_snapshot_fothers_temp\, C => sample_f2_val, Y => - N_57); - - \counter_delta_snapshot_RNO_0[19]\ : AOI1B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[19]_net_1\, C => N_177, Y => - counter_delta_snapshot_e19_i_i_0); - - \counter_delta_f0[26]\ : DFN1E0C0 - port map(D => N_34, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[26]_net_1\); - - \counter_delta_snapshot_RNO_4[6]\ : OR2A - port map(A => N_386, B => \counter_delta_snapshot[6]_net_1\, - Y => counter_delta_snapshot_e6_i_a2_0); - - \counter_delta_snapshot_RNO[13]\ : NOR3C - port map(A => N_287, B => counter_delta_snapshot_e13_i_0_0, - C => N_288, Y => N_26_i_0); - - \counter_delta_snapshot_RNO_0[7]\ : NOR2 - port map(A => N_505, B => delta_snapshot(7), Y => N_462); - - \counter_delta_snapshot_RNO_0[16]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e16_i_i_a2_0, Y => - N_168); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ is - - port( status_new_err : out std_logic_vector(3 to 3); - valid_ack : in std_logic_vector(3 to 3); - valid_out : out std_logic_vector(3 to 3); - rstn : in std_logic; - lclk_c : in std_logic; - data_f3_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1_i, N_6_i_i_0, \valid_out[3]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(3) <= \valid_out[3]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1_i, CLK => lclk_c, CLR => - rstn, Q => status_new_err(3)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => lclk_c, CLR => rstn, Q => - \valid_out[3]\); - - error_RNO : NOR3B - port map(A => \valid_out[3]\, B => data_f3_out_valid, C => - valid_ack(3), Y => state_1_sqmuxa_1_i); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(3), B => \valid_out[3]\, C => - data_f3_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ is - - port( status_new_err : out std_logic_vector(1 to 1); - valid_out_i : out std_logic_vector(1 to 1); - valid_ack : in std_logic_vector(1 to 1); - rstn : in std_logic; - lclk_c : in std_logic; - data_f1_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out_i[1]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out_i(1) <= \valid_out_i[1]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => lclk_c, CLR => rstn, - Q => status_new_err(1)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1P0 - port map(D => N_6_i_i_0, CLK => lclk_c, PRE => rstn, Q => - \valid_out_i[1]\); - - error_RNO : NOR3A - port map(A => data_f1_out_valid, B => valid_ack(1), C => - \valid_out_i[1]\, Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1D - port map(A => valid_ack(1), B => \valid_out_i[1]\, C => - data_f1_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_burst is - - port( sample_f3_wdata : in std_logic_vector(95 downto 0); - data_f3_out : out std_logic_vector(159 downto 64); - rstn : in std_logic; - lclk_c : in std_logic; - data_f3_out_valid : out std_logic; - enable_f3 : in std_logic; - sample_f3_val : in std_logic - ); - -end lpp_waveform_burst; - -architecture DEF_ARCH of lpp_waveform_burst is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal data_out_valid_3, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \data_out[91]\ : DFN1C0 - port map(D => sample_f3_wdata(27), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(91)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f3_wdata(60), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(124)); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f3_wdata(56), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(120)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f3_wdata(74), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(138)); - - \data_out[105]\ : DFN1C0 - port map(D => sample_f3_wdata(41), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(105)); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f3_wdata(62), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(126)); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f3_wdata(10), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(74)); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f3_wdata(90), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(154)); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f3_wdata(86), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(150)); - - \data_out[102]\ : DFN1C0 - port map(D => sample_f3_wdata(38), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(102)); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f3_wdata(92), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(156)); - - \data_out[93]\ : DFN1C0 - port map(D => sample_f3_wdata(29), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(93)); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f3_wdata(64), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(128)); - - data_out_valid : DFN1C0 - port map(D => data_out_valid_3, CLK => lclk_c, CLR => rstn, - Q => data_f3_out_valid); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f3_wdata(5), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(69)); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f3_wdata(77), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(141)); - - \data_out[99]\ : DFN1C0 - port map(D => sample_f3_wdata(35), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(99)); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f3_wdata(83), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(147)); - - \data_out[87]\ : DFN1C0 - port map(D => sample_f3_wdata(23), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(87)); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f3_wdata(85), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(149)); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_out[86]\ : DFN1C0 - port map(D => sample_f3_wdata(22), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(86)); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f3_wdata(94), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(158)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f3_wdata(49), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(113)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f3_wdata(1), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(65)); - - \data_out[95]\ : DFN1C0 - port map(D => sample_f3_wdata(31), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(95)); - - \data_out[92]\ : DFN1C0 - port map(D => sample_f3_wdata(28), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(92)); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f3_wdata(13), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(77)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f3_wdata(81), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(145)); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f3_wdata(67), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(131)); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f3_wdata(12), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(76)); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f3_wdata(73), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(137)); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f3_wdata(75), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(139)); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f3_wdata(50), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(114)); - - \data_out[80]\ : DFN1C0 - port map(D => sample_f3_wdata(16), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(80)); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f3_wdata(0), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(64)); - - \data_out[110]\ : DFN1C0 - port map(D => sample_f3_wdata(46), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(110)); - - \data_out[103]\ : DFN1C0 - port map(D => sample_f3_wdata(39), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(103)); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f3_wdata(78), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(142)); - - \data_out[94]\ : DFN1C0 - port map(D => sample_f3_wdata(30), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(94)); - - \data_out[88]\ : DFN1C0 - port map(D => sample_f3_wdata(24), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(88)); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f3_wdata(52), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(116)); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f3_wdata(57), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(121)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f3_wdata(63), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(127)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f3_wdata(65), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(129)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f3_wdata(71), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(135)); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f3_wdata(6), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(70)); - - data_out_valid_RNO : NOR2B - port map(A => sample_f3_val, B => enable_f3, Y => - data_out_valid_3); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f3_wdata(54), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(118)); - - \data_out[104]\ : DFN1C0 - port map(D => sample_f3_wdata(40), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(104)); - - \data_out[100]\ : DFN1C0 - port map(D => sample_f3_wdata(36), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(100)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f3_wdata(14), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(78)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f3_wdata(87), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(151)); - - GND_i : GND - port map(Y => \GND\); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f3_wdata(93), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(157)); - - \data_out[106]\ : DFN1C0 - port map(D => sample_f3_wdata(42), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(106)); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f3_wdata(95), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(159)); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f3_wdata(68), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(132)); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f3_wdata(61), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(125)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f3_wdata(3), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(67)); - - \data_out[81]\ : DFN1C0 - port map(D => sample_f3_wdata(17), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(81)); - - \data_out[97]\ : DFN1C0 - port map(D => sample_f3_wdata(33), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(97)); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f3_wdata(2), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(66)); - - \data_out[108]\ : DFN1C0 - port map(D => sample_f3_wdata(44), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(108)); - - \data_out[96]\ : DFN1C0 - port map(D => sample_f3_wdata(32), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(96)); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f3_wdata(79), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(143)); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f3_wdata(58), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(122)); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f3_wdata(91), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(155)); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f3_wdata(7), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(71)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f3_wdata(88), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(152)); - - \data_out[83]\ : DFN1C0 - port map(D => sample_f3_wdata(19), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(83)); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f3_wdata(80), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(144)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f3_wdata(76), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(140)); - - \data_out[111]\ : DFN1C0 - port map(D => sample_f3_wdata(47), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(111)); - - \data_out[90]\ : DFN1C0 - port map(D => sample_f3_wdata(26), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(90)); - - \data_out[89]\ : DFN1C0 - port map(D => sample_f3_wdata(25), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(89)); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f3_wdata(4), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(68)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f3_wdata(53), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(117)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f3_wdata(82), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(146)); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f3_wdata(69), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(133)); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f3_wdata(55), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(119)); - - \data_out[98]\ : DFN1C0 - port map(D => sample_f3_wdata(34), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(98)); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f3_wdata(9), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(73)); - - \data_out[85]\ : DFN1C0 - port map(D => sample_f3_wdata(21), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(85)); - - \data_out[82]\ : DFN1C0 - port map(D => sample_f3_wdata(18), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(82)); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f3_wdata(15), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(79)); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f3_wdata(84), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(148)); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f3_wdata(59), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(123)); - - \data_out[101]\ : DFN1C0 - port map(D => sample_f3_wdata(37), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(101)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f3_wdata(70), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(134)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f3_wdata(51), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(115)); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f3_wdata(66), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(130)); - - \data_out[107]\ : DFN1C0 - port map(D => sample_f3_wdata(43), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(107)); - - \data_out[109]\ : DFN1C0 - port map(D => sample_f3_wdata(45), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(109)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f3_wdata(72), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(136)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[84]\ : DFN1C0 - port map(D => sample_f3_wdata(20), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(84)); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f3_wdata(11), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(75)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f3_wdata(8), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(72)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f3_wdata(89), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(153)); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f3_wdata(48), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(112)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ is - - port( status_new_err : out std_logic_vector(2 to 2); - valid_ack : in std_logic_vector(2 to 2); - valid_out : out std_logic_vector(2 to 2); - rstn : in std_logic; - lclk_c : in std_logic; - data_f2_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out[2]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(2) <= \valid_out[2]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => lclk_c, CLR => rstn, - Q => status_new_err(2)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => lclk_c, CLR => rstn, Q => - \valid_out[2]\); - - error_RNO : NOR3B - port map(A => \valid_out[2]\, B => data_f2_out_valid, C => - valid_ack(2), Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(2), B => \valid_out[2]\, C => - data_f2_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ is - - port( status_new_err : out std_logic_vector(0 to 0); - valid_ack : in std_logic_vector(0 to 0); - valid_out : out std_logic_vector(0 to 0); - rstn : in std_logic; - lclk_c : in std_logic; - data_f0_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out[0]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(0) <= \valid_out[0]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => lclk_c, CLR => rstn, - Q => status_new_err(0)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => lclk_c, CLR => rstn, Q => - \valid_out[0]\); - - error_RNO : NOR3B - port map(A => \valid_out[0]\, B => data_f0_out_valid, C => - valid_ack(0), Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(0), B => \valid_out[0]\, C => - data_f0_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ1 is - - port( ready_i_0_i_0 : out std_logic_vector(1 to 1); - data_mem_wen_i_0 : out std_logic_vector(1 to 1); - data_ren : in std_logic_vector(1 to 1); - data_mem_ren_i_0 : out std_logic_vector(1 to 1); - data_wen : in std_logic_vector(1 to 1); - data_mem_addr_r_1 : out std_logic_vector(4 downto 0); - data_mem_addr_w_1 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - N_158 : in std_logic; - sFull_RNIE8AH1 : out std_logic; - sEmpty_RNI6M6A4J_0 : in std_logic; - sEmpty_RNIU5CB661 : out std_logic; - un20_time_write : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ1; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ1 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, N_4, \DWACT_FINC_E[0]\, N_12_0, N_4_0, - \DWACT_FINC_E_0[0]\, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \data_mem_addr_w_1[3]\, - \un10_raddr_vect_s[3]\, sEmpty_RNO_6_2, - \data_mem_addr_w_1[1]\, \un10_raddr_vect_s[1]\, - sEmpty_RNO_5_1, \data_mem_addr_w_1[0]\, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \data_mem_addr_r_1[3]\, \un8_waddr_vect_s[3]\, - sFull_RNO_8_0, un5_sfull_s_4_1, \data_mem_addr_r_1[1]\, - \un8_waddr_vect_s[1]\, sFull_RNO_5_1, un5_sfull_s_4_0, - \data_mem_addr_r_1[0]\, \un8_waddr_vect_s[0]\, - ADD_7x7_fast_I23_Y_0_o2_0, N165_1, N_89_i, N_73, - ADD_5x5_fast_I17_un1_Y_1, N130, ADD_5x5_fast_I13_Y_0, - ADD_5x5_fast_I17_un1_Y_0, ADD_5x5_fast_I5_un1_Y_0, - ADD_5x5_fast_I11_Y_0, N80, N91, N94, N_84_1, - ADD_7x7_fast_I19_Y_i_o4_1_0, N_72, - ADD_5x5_fast_I9_un1_Y_0, un1_waddr_vect_slto3_0, - \data_mem_addr_w_1[2]\, \data_mem_addr_r_1[2]\, - un2_raddr_vect_slto3_0, I11_un1_Y, N81, N77, N98, - un5_sfull_s_4, N_11, \sEmpty\, Waddr_vect_n4, - Waddr_vect_14_0, un1_waddr_vect_s, Waddr_vect_c2, - Waddr_vect_n3, Waddr_vect_n2, Waddr_vect_c1_i_0, - sFull_RNO_12, \sFull\, I_5_28, I_13_32, I_9_28, I_20_20, - N_71, N165, Waddr_vect_n1_i, Waddr_vect_e1, Waddr_vect_e0, - \data_mem_wen_i_0[1]\, un2_raddr_vect_s, I_5_29, - \un10_raddr_vect_s[2]\, I_9_29, I_13_33, - \un10_raddr_vect_s[4]\, I_20_21, \data_mem_addr_w_1[4]\, - \data_mem_ren_i_0[1]\, un2_raddr_vect_slto1, - \data_mem_addr_r_1[4]\, Waddr_vect_e4, Waddr_vect_e3, - Waddr_vect_e2, sEmpty_RNO_12, un1_sempty_s, N_75_1, - \un75_ready1[4]\, N111, \un75_ready0[4]\, un62_readylto4, - un77_ready, un69_ready, N_166, N107, N161, N_165, - \un75_ready1[5]\, N_16_i_i_0, N_164, N_24, I12_un1_Y, N87, - N102, N_9, N_13, N_12_1, N_11_0, N_8, N_10, N_9_0, N_7, - N_4_1, N_5, N_6, N_9_1, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - data_mem_wen_i_0(1) <= \data_mem_wen_i_0[1]\; - data_mem_ren_i_0(1) <= \data_mem_ren_i_0[1]\; - data_mem_addr_r_1(4) <= \data_mem_addr_r_1[4]\; - data_mem_addr_r_1(3) <= \data_mem_addr_r_1[3]\; - data_mem_addr_r_1(2) <= \data_mem_addr_r_1[2]\; - data_mem_addr_r_1(1) <= \data_mem_addr_r_1[1]\; - data_mem_addr_r_1(0) <= \data_mem_addr_r_1[0]\; - data_mem_addr_w_1(4) <= \data_mem_addr_w_1[4]\; - data_mem_addr_w_1(3) <= \data_mem_addr_w_1[3]\; - data_mem_addr_w_1(2) <= \data_mem_addr_w_1[2]\; - data_mem_addr_w_1(1) <= \data_mem_addr_w_1[1]\; - data_mem_addr_w_1(0) <= \data_mem_addr_w_1[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => N_9_1); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4 : OR2A - port map(A => N165_1, B => N80, Y => N165); - - \Waddr_vect_RNIVSRF[3]\ : NOR2 - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_w_1[2]\, Y => un1_waddr_vect_slto3_0); - - \ready_gen.un69_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_1[4]\, B => - \data_mem_addr_r_1[4]\, Y => N_11_0); - - \ready_gen.un69_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, Y => N_5); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXOI5 - port map(A => N_72, B => \data_mem_addr_r_1[2]\, C => - \data_mem_addr_w_1[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - un60_ready_0_0_ADD_5x5_fast_I1_G0N : OR2A - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_r_1[1]\, Y => N87); - - un60_ready_0_0_ADD_5x5_fast_I17_un1_Y_1 : OA1 - port map(A => N130, B => ADD_5x5_fast_I13_Y_0, C => - ADD_5x5_fast_I17_un1_Y_0, Y => ADD_5x5_fast_I17_un1_Y_1); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, C => \data_mem_addr_r_1[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, Y => N_12); - - un60_ready_0_0_ADD_5x5_fast_I2_P0N : OR2A - port map(A => \data_mem_addr_r_1[2]\, B => - \data_mem_addr_w_1[2]\, Y => N91); - - sEmpty_RNO : AO1A - port map(A => data_ren(1), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_12); - - \Raddr_vect_RNIKT47[4]\ : NOR2B - port map(A => I_20_21, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[3]\); - - un75_ready_0_0_0_ADD_7x7_fast_I20_Y_i_o2_0 : AO13 - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => \data_mem_addr_r_1[1]\, Y - => N_11); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_1[2]\, Y => - I_9_29); - - \Raddr_vect_RNI7MARL[0]\ : MX2 - port map(A => un62_readylto4, B => un77_ready, S => - un69_ready, Y => ready_i_0_i_0(1)); - - \Raddr_vect_RNIAB94[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_1[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Waddr_vect_RNO[4]\ : MX2B - port map(A => \data_mem_addr_w_1[4]\, B => Waddr_vect_n4, S - => \data_mem_wen_i_0[1]\, Y => Waddr_vect_e4); - - un75_ready_1_16_ADD_5x5_fast_I1_P0N : OR2A - port map(A => N_71, B => N_72, Y => N81); - - un75_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : XOR3 - port map(A => N_73, B => N_89_i, C => N165, Y => - \un75_ready0[4]\); - - \sFull_RNIE8AH1\ : OR2A - port map(A => N_158, B => \data_mem_wen_i_0[1]\, Y => - sFull_RNIE8AH1); - - \ready_gen.un69_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, Y => N_4_1); - - un75_ready_1_16_ADD_5x5_fast_I10_Y : AO1B - port map(A => N111, B => N98, C => N_75_1, Y => N107); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_12, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Raddr_vect_RNI5RK8_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_1[4]\, B => - \data_mem_addr_w_1[4]\, Y => N_75_1); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[1]\, - C => \data_mem_addr_w_1[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[2]\); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \data_mem_addr_w_1[1]\, B => Waddr_vect_n1_i, - S => \data_mem_wen_i_0[1]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AO1 - port map(A => N165_1, B => N_89_i, C => N_73, Y => - ADD_7x7_fast_I23_Y_0_o2_0); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : OR2A - port map(A => N165, B => N_89_i, Y => N_24); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_1[2]\, B => - Waddr_vect_c1_i_0, C => un1_waddr_vect_s, Y => - Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, Y => I_5_28); - - \Raddr_vect_RNI01E6[4]\ : NOR2B - port map(A => I_13_33, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - \Waddr_vect_RNIRSRF[0]\ : OR2B - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, Y => Waddr_vect_c1_i_0); - - un75_ready_1_16_ADD_5x5_fast_I1_G0N : NOR2A - port map(A => N_72, B => N_71, Y => N80); - - un60_ready_0_0_ADD_5x5_fast_I0_P0N : NOR2A - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_w_1[0]\, Y => N130); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[3]\); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_1[1]\, B => - \un10_raddr_vect_s[1]\, C => sEmpty_RNO_5_1, Y => - un7_sempty_s_1); - - un75_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO13 - port map(A => N_89_i, B => N_73, C => N80, Y => - ADD_5x5_fast_I11_Y_0); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_1[3]\, Y => - I_13_32); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(1), - Y => sFull_RNO_12); - - \Raddr_vect_RNI5PD1[3]\ : NOR2 - port map(A => \data_mem_addr_r_1[3]\, B => - \data_mem_addr_r_1[2]\, Y => un2_raddr_vect_slto3_0); - - un60_ready_0_0_ADD_5x5_fast_I12_un1_Y : OR3B - port map(A => N91, B => N94, C => N102, Y => I12_un1_Y); - - \ready_gen.un69_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, C => N_5, Y => N_9_0); - - sFull_RNO_4 : OR2B - port map(A => I_5_28, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - un60_ready_0_0_ADD_5x5_fast_I13_Y_0 : OR3C - port map(A => N91, B => N94, C => N_84_1, Y => - ADD_5x5_fast_I13_Y_0); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_1[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_1[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(1), Y => - un7_sempty_s_0); - - un60_ready_0_0_ADD_5x5_fast_I25_Y_0 : AX1E - port map(A => I12_un1_Y, B => ADD_5x5_fast_I17_un1_Y_1, C - => N_89_i, Y => un62_readylto4); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[2]\); - - \ready_gen.un69_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, C => N_6, Y => N_8); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[0]\); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_20, C => - \data_mem_addr_r_1[4]\, Y => sFull_RNO_8_0); - - sFull_RNIDOE8 : NOR2 - port map(A => \sFull\, B => data_wen(1), Y => - \data_mem_wen_i_0[1]\); - - \sEmpty_RNIU5CB661\ : OR2A - port map(A => sEmpty_RNI6M6A4J_0, B => - \data_mem_ren_i_0[1]\, Y => sEmpty_RNIU5CB661); - - \Raddr_vect_RNI5RK8[4]\ : XNOR2 - port map(A => \data_mem_addr_w_1[4]\, B => - \data_mem_addr_r_1[4]\, Y => N_89_i); - - un75_ready_1_16_ADD_5x5_fast_I15_Y_0 : XOR3 - port map(A => N_73, B => N_89_i, C => N111, Y => - \un75_ready1[4]\); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_1[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - \Raddr_vect_RNIIUK5G[0]\ : AOI1 - port map(A => N_165, B => N_164, C => N_166, Y => - un77_ready); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_28, C => - \data_mem_addr_r_1[2]\, Y => sFull_RNO_5_1); - - \Raddr_vect_RNIR705[4]\ : NOR2B - port map(A => I_5_29, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \data_mem_addr_w_1[2]\, B => Waddr_vect_n2, S - => \data_mem_wen_i_0[1]\, Y => Waddr_vect_e2); - - un75_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75_1, Y => N_16_i_i_0); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_1[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_6_2, Y => - un7_sempty_s_2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_1[3]\, Y - => Waddr_vect_14_0); - - \Waddr_vect_RNIBOL71[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => - Waddr_vect_c1_i_0, C => \data_mem_addr_w_1[4]\, Y => - un1_waddr_vect_s); - - \Waddr_vect_RNIARPN[2]\ : NOR2A - port map(A => \data_mem_addr_w_1[2]\, B => - Waddr_vect_c1_i_0, Y => Waddr_vect_c2); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_1[3]\, B => - \un8_waddr_vect_s[3]\, C => sFull_RNO_8_0, Y => - un5_sfull_s_4_2); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - un75_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_89_i, B => N_73, Y => N98); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR3C - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75_1, Y => N161); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1 : OR2B - port map(A => ADD_7x7_fast_I19_Y_i_o4_1_0, B => N_11, Y => - N165_1); - - \Raddr_vect_RNIOQ3P3[0]\ : MX2C - port map(A => \un75_ready1[4]\, B => \un75_ready0[4]\, S - => \data_mem_addr_r_1[0]\, Y => N_164); - - \Raddr_vect_RNI1RK8[2]\ : NOR2A - port map(A => \data_mem_addr_r_1[2]\, B => - \data_mem_addr_w_1[2]\, Y => N_71); - - \ready_gen.un69_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_w_1[0]\, Y => N_6); - - un60_ready_0_0_ADD_5x5_fast_I9_un1_Y_0 : NOR2B - port map(A => \data_mem_addr_w_1[0]\, B => N_84_1, Y => - ADD_5x5_fast_I9_un1_Y_0); - - \Raddr_vect_RNI3RK8[3]\ : XNOR2 - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, Y => N_72); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[0]\); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_r_1[0]\, Y => N_12_0); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_1[2]\, Y => - I_9_28); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_1[3]\, Y => - I_13_33); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, C => \data_mem_addr_r_1[2]\, Y - => N_9); - - un60_ready_0_0_ADD_5x5_fast_I9_Y : OA1A - port map(A => ADD_5x5_fast_I9_un1_Y_0, B => - \data_mem_addr_r_1[0]\, C => N87, Y => N102); - - un60_ready_0_0_ADD_5x5_fast_I3_G0N : OR2A - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, Y => N_73); - - \Raddr_vect_RNINRUK5[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_1[0]\, - Y => N_166); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(1), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_1[4]\, Y => - I_20_21); - - un60_ready_0_0_ADD_5x5_fast_I5_un1_Y_0 : NOR2A - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, Y => ADD_5x5_fast_I5_un1_Y_0); - - \Raddr_vect_RNID4N5[4]\ : NOR2B - port map(A => I_9_29, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - un75_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1 - port map(A => \data_mem_addr_r_1[2]\, B => - \data_mem_addr_w_1[2]\, C => N_84_1, Y => N77); - - un75_ready_1_16_ADD_5x5_fast_I8_Y : AO13 - port map(A => N77, B => N_72, C => N_71, Y => N111); - - un75_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75_1, Y => \un75_ready1[5]\); - - un60_ready_0_0_ADD_5x5_fast_I17_un1_Y_0 : AO18 - port map(A => ADD_5x5_fast_I5_un1_Y_0, B => - \data_mem_addr_r_1[3]\, C => \data_mem_addr_w_1[3]\, Y - => ADD_5x5_fast_I17_un1_Y_0); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_1[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_1, Y => - un5_sfull_s_4_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, Y => I_5_29); - - un75_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - \ready_gen.un69_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_1[4]\, B => - \data_mem_addr_w_1[4]\, Y => N_7); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_1[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[4]\); - - sFull_RNO_7 : OR2B - port map(A => I_13_32, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - un60_ready_0_0_ADD_5x5_fast_I3_P0N : OR2A - port map(A => \data_mem_addr_r_1[3]\, B => - \data_mem_addr_w_1[3]\, Y => N94); - - \Raddr_vect_RNIQEI3[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_1[4]\, Y => - un2_raddr_vect_s); - - \Raddr_vect_RNI1PD1[1]\ : OR2B - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_r_1[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect_RNO[3]\ : MX2B - port map(A => \data_mem_addr_w_1[3]\, B => Waddr_vect_n3, S - => \data_mem_wen_i_0[1]\, Y => Waddr_vect_e3); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_1[4]\, Y => sEmpty_RNO_6_2); - - sEmpty_RNIOF512J : NOR3 - port map(A => un20_time_write, B => \sEmpty\, C => - data_ren_1z, Y => \data_mem_ren_i_0[1]\); - - \Raddr_vect_RNI38IN6[0]\ : MX2C - port map(A => \un75_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_1[0]\, Y => N_165); - - sFull : DFN1C0 - port map(D => sFull_RNO_12, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \ready_gen.un69_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, C => N_4_1, Y => N_10); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_1[4]\, Y => - I_20_20); - - \ready_gen.un69_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13); - - un60_ready_0_0_ADD_5x5_fast_I1_P0N : OR2A - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, Y => N_84_1); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[1]\); - - \ready_gen.un69_ready_0_I_11\ : OA1 - port map(A => N_13, B => N_12_1, C => N_11_0, Y => - un69_ready); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[4]\); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_1[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(1), Y => - un5_sfull_s_4_0); - - \ready_gen.un69_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, C => N_7, Y => N_12_1); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_1[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_1[2]\, Y => sEmpty_RNO_5_1); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_1[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => \DWACT_FINC_E[0]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ7 is - - port( time_mem_wen_i_0 : out std_logic_vector(3 to 3); - time_mem_ren_i_0 : out std_logic_vector(3 to 3); - time_mem_addr_w_3_i_0_3 : out std_logic; - time_mem_addr_w_3_i_0_0 : out std_logic; - time_mem_addr_r_3_i_0_3 : out std_logic; - time_mem_addr_r_3_i_0_0 : out std_logic; - time_wen : in std_logic_vector(3 to 3); - time_ren : in std_logic_vector(3 to 3); - time_mem_addr_w_3_3 : out std_logic; - time_mem_addr_w_3_0 : out std_logic; - time_mem_addr_w_3_1 : out std_logic; - time_mem_addr_r_3_3 : out std_logic; - time_mem_addr_r_3_0 : out std_logic; - time_mem_addr_r_3_1 : out std_logic; - time_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - N_156 : in std_logic; - N_157 : out std_logic; - sFull_RNIODA01_0 : out std_logic; - N_117 : out std_logic; - un5_time_write : in std_logic; - N_89 : out std_logic; - N_88 : in std_logic; - N_37 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ7; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ7 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO6 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_7, N_7_0, \un10_sempty_s_3_0\, - \un10_raddr_vect_s[3]\, \Waddr_vect_i[3]\, - \un2_sfull_s_3_0\, \un8_waddr_vect_s[3]\, - \Raddr_vect_i[3]\, un7_sempty_s_2, un5_sfull_s_2, - un7_sempty_s_3, sEmpty_RNO_3_0, sEmpty_RNO_4_0, - un7_sempty_s_0, \un10_raddr_vect_s[0]\, - \time_mem_addr_w_3[0]\, un5_sfull_s_3, \sFull_RNO_3\, - \sFull_RNO_4\, un5_sfull_s_0, \un8_waddr_vect_s[0]\, - \time_mem_addr_r_3[0]\, un2_raddr_vect_slt3, - \time_mem_addr_r_3[1]\, un1_waddr_vect_slt3, - \time_mem_addr_w_3[1]\, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, - \time_mem_addr_w_3_i_0[2]\, \time_mem_addr_r_3_i_0[2]\, - Raddr_vect_n2, un2_raddr_vect_s, Raddr_vect_n2_tz, - Waddr_vect_n2, un1_waddr_vect_s, Waddr_vect_n2_tz, - \time_mem_ren_i_0[3]\, I_9_15, I_5_15, Raddr_vect_n1_i, - Raddr_vect_e2, Raddr_vect_e1, Raddr_vect_e0, I_13_19, - \sEmpty\, \time_mem_addr_r_3_i_0[5]\, I_9_14, I_5_14, - Waddr_vect_e2, I_13_18, \sFull_RNO\, un8_sfull_s, \sFull\, - \time_mem_addr_w_3_i_0[5]\, \time_mem_wen_i_0[3]\, - sFull_RNIODA01_0_net_1, un2_sempty_s, \sEmpty_RNO\, - Waddr_vect_e0, Waddr_vect_e1, Waddr_vect_n1_i, N_4, N_4_0, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - time_mem_wen_i_0(3) <= \time_mem_wen_i_0[3]\; - time_mem_ren_i_0(3) <= \time_mem_ren_i_0[3]\; - time_mem_addr_w_3_i_0_3 <= \time_mem_addr_w_3_i_0[5]\; - time_mem_addr_w_3_i_0_0 <= \time_mem_addr_w_3_i_0[2]\; - time_mem_addr_r_3_i_0_3 <= \time_mem_addr_r_3_i_0[5]\; - time_mem_addr_r_3_i_0_0 <= \time_mem_addr_r_3_i_0[2]\; - time_mem_addr_w_3_0 <= \time_mem_addr_w_3[0]\; - time_mem_addr_w_3_1 <= \time_mem_addr_w_3[1]\; - time_mem_addr_r_3_0 <= \time_mem_addr_r_3[0]\; - time_mem_addr_r_3_1 <= \time_mem_addr_r_3[1]\; - sFull_RNIODA01_0 <= sFull_RNIODA01_0_net_1; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_3[1]\, B => - \time_mem_addr_w_3[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => N_4); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_3[1]\, B => - \time_mem_addr_r_3[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - sFull_RNIODA01 : OR2B - port map(A => \time_mem_wen_i_0[3]\, B => N_156, Y => N_157); - - un43_mem_addr_ren_1_SUM1_0 : XNOR2 - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \Raddr_vect_i[3]\, Y => time_mem_addr_r_3_3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_3[1]\, B => - \time_mem_addr_w_3[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_3[1]\); - - \Waddr_vect[3]\ : DFN1E0P0 - port map(D => Waddr_vect_n3, CLK => lclk_c, PRE => rstn, E - => \time_mem_wen_i_0[3]\, Q => \Waddr_vect_i[3]\); - - sEmpty_RNI3SGD2 : NOR3A - port map(A => N_88, B => \time_mem_ren_i_0[3]\, C => - \time_mem_addr_r_3_i_0[5]\, Y => N_37); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \time_mem_addr_r_3_i_0[2]\, Y => - I_9_15); - - un2_sfull_s_3_0_RNO : OR2B - port map(A => I_13_18, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO\, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[3]\, - C => \time_mem_addr_w_3[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_3_i_0[2]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_3[1]\, - S => \time_mem_wen_i_0[3]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, Y => I_5_14); - - sFull_RNIK4V7 : OR2 - port map(A => time_wen(3), B => \sFull\, Y => - \time_mem_wen_i_0[3]\); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - \Waddr_vect_RNIQ6UJ[3]\ : OR2A - port map(A => un1_waddr_vect_slt3, B => \Waddr_vect_i[3]\, - Y => un1_waddr_vect_s); - - \Waddr_vect_RNI2LUE[1]\ : OR3 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => un1_waddr_vect_slt3); - - \sFull_RNIODA01_0\ : OR2A - port map(A => N_156, B => \time_mem_wen_i_0[3]\, Y => - sFull_RNIODA01_0_net_1); - - \Raddr_vect[3]\ : DFN1E0P0 - port map(D => Raddr_vect_n3, CLK => lclk_c, PRE => rstn, E - => \time_mem_ren_i_0[3]\, Q => \Raddr_vect_i[3]\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(3), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XNOR2 - port map(A => \Waddr_vect_i[3]\, B => N_4, Y => I_13_18); - - un2_sfull_s_3_0 : XNOR2 - port map(A => \un8_waddr_vect_s[3]\, B => \Raddr_vect_i[3]\, - Y => \un2_sfull_s_3_0\); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[3]\, - C => \time_mem_addr_r_3[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNI6V1N[3]\ : OR2A - port map(A => un2_raddr_vect_slt3, B => \Raddr_vect_i[3]\, - Y => un2_raddr_vect_s); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_3[1]\, - S => \time_mem_ren_i_0[3]\, Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_14, C => - \time_mem_addr_r_3[1]\, Y => \sFull_RNO_4\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_3[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_15, C => - \time_mem_addr_w_3_i_0[2]\, Y => sEmpty_RNO_3_0); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_3_i_0[2]\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_3[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_3[0]\, C => time_wen(3), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => - \time_mem_addr_w_3_i_0[2]\, S => \time_mem_wen_i_0[3]\, Y - => Waddr_vect_e2); - - \Raddr_vect_RNIBF9H[1]\ : OR3 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => un2_raddr_vect_slt3); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_15, C => - \time_mem_addr_w_3[1]\, Y => sEmpty_RNO_4_0); - - un50_mem_addr_wen_1_SUM1_0 : XNOR2 - port map(A => \time_mem_addr_w_3_i_0[2]\, B => - \Waddr_vect_i[3]\, Y => time_mem_addr_w_3_3); - - un10_sempty_s_3_0 : XNOR2 - port map(A => \un10_raddr_vect_s[3]\, B => - \Waddr_vect_i[3]\, Y => \un10_sempty_s_3_0\); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_14, C => - \time_mem_addr_r_3_i_0[2]\, Y => \sFull_RNO_3\); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_0, B => sEmpty_RNO_4_0, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => Waddr_vect_n2_tz); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => Raddr_vect_n2_tz); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => - \time_mem_addr_r_3_i_0[2]\, S => \time_mem_ren_i_0[3]\, Y - => Raddr_vect_e2); - - sFull_RNI7H9A1 : NOR2 - port map(A => \time_mem_addr_w_3_i_0[5]\, B => - sFull_RNIODA01_0_net_1, Y => N_117); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_3[0]\); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_3[1]\, B => - \time_mem_addr_r_3[0]\, Y => N_7); - - un10_sempty_s_3_0_RNO : OR2B - port map(A => I_13_19, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \time_mem_addr_w_3_i_0[2]\, Y => - I_9_14); - - un8_raddr_vect_s_I_13 : XNOR2 - port map(A => \Raddr_vect_i[3]\, B => N_4_0, Y => I_13_19); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => N_4_0); - - sEmpty_RNO_1 : NOR2A - port map(A => \un10_sempty_s_3_0\, B => time_ren(3), Y => - un7_sempty_s_2); - - sEmpty_RNI8S0D : OR3A - port map(A => time_ren_1z, B => un5_time_write, C => - \sEmpty\, Y => \time_mem_ren_i_0[3]\); - - sFull_RNO_1 : AND2 - port map(A => time_ren(3), B => \un2_sfull_s_3_0\, Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, Y => I_5_15); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => Waddr_vect_15_0); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => Raddr_vect_7_0); - - sEmpty_RNIESV12 : OR2B - port map(A => \time_mem_ren_i_0[3]\, B => N_88, Y => N_89); - - \Waddr_vect_RNO[3]\ : AXO6 - port map(A => un1_waddr_vect_slt3, B => \Waddr_vect_i[3]\, - C => Waddr_vect_15_0, Y => Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => \sFull_RNO_3\, B => \sFull_RNO_4\, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_3[0]\, - Y => \un10_raddr_vect_s[0]\); - - un43_mem_addr_ren_1_CO1 : OR2A - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \Raddr_vect_i[3]\, Y => \time_mem_addr_r_3_i_0[5]\); - - sFull : DFN1C0 - port map(D => \sFull_RNO\, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - un50_mem_addr_wen_1_CO1 : OR2A - port map(A => \time_mem_addr_w_3_i_0[2]\, B => - \Waddr_vect_i[3]\, Y => \time_mem_addr_w_3_i_0[5]\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_3[1]\); - - sFull_RNO_2 : OA1A - port map(A => time_ren_1z, B => un5_time_write, C => - \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_3[0]\, C => time_wen(3), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXO6 - port map(A => un2_raddr_vect_slt3, B => \Raddr_vect_i[3]\, - C => Raddr_vect_7_0, Y => Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 is - - port( rclk : in std_logic; - rena : in std_logic; - raddr : in std_logic_vector(6 downto 0); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic; - waddr : in std_logic_vector(6 downto 0); - din : in std_logic_vector(31 downto 0); - write : in std_logic - ); - -end proasic3_syncram_2p_work_leon3mp_wfp_rtl_0; - -architecture DEF_ARCH of - proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ2 is - - port( wdata : in std_logic_vector(31 downto 0); - hwdata : out std_logic_vector(31 downto 0); - Waddr_vect_1 : in std_logic_vector(2 to 2); - Waddr_vect_0 : in std_logic_vector(2 to 2); - time_mem_addr_w_1_0 : in std_logic; - time_mem_addr_w_1_1 : in std_logic; - time_mem_addr_w_1_3 : in std_logic; - time_mem_addr_w_3_0 : in std_logic; - time_mem_addr_w_3_1 : in std_logic; - time_mem_addr_w_3_3 : in std_logic; - DWACT_FINC_E_0 : in std_logic_vector(0 to 0); - data_mem_addr_w_3 : in std_logic_vector(4 downto 0); - data_mem_addr_w_1 : in std_logic_vector(4 downto 0); - time_mem_addr_r_3_3 : in std_logic; - time_mem_addr_r_3_0 : in std_logic; - time_mem_addr_r_3_1 : in std_logic; - Raddr_vect_1 : in std_logic_vector(2 to 2); - Raddr_vect_0 : in std_logic_vector(2 to 2); - time_mem_addr_r_1_1 : in std_logic; - time_mem_addr_r_1_0 : in std_logic; - time_mem_addr_r_1_3 : in std_logic; - data_mem_addr_r_3 : in std_logic_vector(4 downto 0); - data_mem_addr_r_1 : in std_logic_vector(4 downto 0); - DWACT_FINC_E : in std_logic_vector(0 to 0); - Raddr_vect : in std_logic_vector(2 to 2); - time_mem_addr_r_2_0 : in std_logic; - time_mem_addr_r_2_1 : in std_logic; - time_mem_addr_r_2_3 : in std_logic; - time_mem_addr_r_2_4 : in std_logic; - data_mem_ren_i_0 : in std_logic_vector(3 downto 0); - time_mem_addr_r_3_i_0_0 : in std_logic; - time_mem_addr_r_3_i_0_3 : in std_logic; - time_mem_addr_w_3_i_0_0 : in std_logic; - time_mem_addr_w_3_i_0_3 : in std_logic; - data_mem_wen_i_0 : in std_logic_vector(3 downto 0); - Waddr_vect : in std_logic_vector(2 to 2); - data_mem_addr_w_0 : in std_logic_vector(4 downto 0); - time_mem_wen_i_0_1 : in std_logic; - time_mem_wen_i_0_3 : in std_logic; - time_mem_wen_i_0_0 : in std_logic; - time_mem_addr_w_0_1 : in std_logic; - time_mem_addr_w_0_3 : in std_logic; - time_mem_addr_w_0_4 : in std_logic; - time_mem_addr_w_0_0 : in std_logic; - time_mem_addr_w_2_4 : in std_logic; - time_mem_addr_w_2_3 : in std_logic; - time_mem_addr_w_2_1 : in std_logic; - time_mem_addr_w_2_0 : in std_logic; - data_mem_addr_w_2 : in std_logic_vector(4 downto 0); - time_mem_ren_i_0_3 : in std_logic; - time_mem_ren_i_0_1 : in std_logic; - time_mem_ren_i_0_0 : in std_logic; - time_mem_addr_r_0_4 : in std_logic; - time_mem_addr_r_0_3 : in std_logic; - time_mem_addr_r_0_0 : in std_logic; - time_mem_addr_r_0_1 : in std_logic; - data_mem_addr_r_0 : in std_logic_vector(4 downto 0); - data_mem_addr_r_2 : in std_logic_vector(4 downto 0); - N_64_i_0 : in std_logic; - lclk_c : in std_logic; - sFull_RNIODA01_0 : in std_logic; - sFull_RNIKQ9G : in std_logic; - sFull_RNIE8AH1 : in std_logic; - N_158 : in std_logic; - N_4_0 : in std_logic; - N_88 : in std_logic; - sEmpty_RNIU5CB661 : in std_logic; - sEmpty_RNI6M6A4J_0 : in std_logic; - N_4 : in std_logic; - N_115 : in std_logic; - N_117 : in std_logic; - N_93 : in std_logic; - N_35 : in std_logic; - N_37 : in std_logic; - N_157 : in std_logic; - N_162 : in std_logic; - N_161 : in std_logic; - N_165 : in std_logic; - sEmpty_RNI6M6A4J : in std_logic; - sEmpty_RNIPJ7A8P1 : in std_logic - ); - -end syncram_2pZ2; - -architecture DEF_ARCH of syncram_2pZ2 is - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 - port( rclk : in std_logic := 'U'; - rena : in std_logic := 'U'; - raddr : in std_logic_vector(6 downto 0) := (others => 'U'); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic := 'U'; - waddr : in std_logic_vector(6 downto 0) := (others => 'U'); - din : in std_logic_vector(31 downto 0) := (others => 'U'); - write : in std_logic := 'U' - ); - end component; - - signal \data_addr_r_iv_i_4[1]\, x0_RNO_81, N_72, - \data_addr_r_iv_i_0[1]\, \data_addr_r_iv_i_3[1]\, N_77, - \data_addr_r_iv_i_2[1]\, N_75, x0_RNO_108, - \data_addr_w_iv_i_5[0]\, N_151, x0_RNO_76, - \data_addr_w_iv_i_3[0]\, x0_RNO_106, - \data_addr_w_iv_i_1[0]\, x0_RNO_51, - \data_addr_w_iv_i_0[0]\, x0_RNO_62, - \data_addr_r_iv_i_4[0]\, x0_RNO_78, N_80, - \data_addr_r_iv_i_0[0]\, \data_addr_r_iv_i_3[0]\, N_85, - \data_addr_r_iv_i_2[0]\, N_83, x0_RNO_107, - \data_addr_w_iv_i_4[2]\, x0_RNO_94, x0_RNO_95, - \data_addr_w_iv_i_1[2]\, \data_addr_w_iv_i_3[2]\, N_137, - \data_addr_w_iv_i_2[2]\, N_135, x0_RNO_113, - \data_addr_w_iv_i_4[1]\, x0_RNO_91, N_138, - \data_addr_w_iv_i_1[1]\, \data_addr_w_iv_i_3[1]\, N_145, - \data_addr_w_iv_i_2[1]\, N_143, x0_RNO_112, - \data_addr_w_iv_i_4[3]\, x0_RNO_97, x0_RNO_98, - \data_addr_w_iv_i_1[3]\, \data_addr_w_iv_i_3[3]\, N_129, - \data_addr_w_iv_i_2[3]\, N_127, x0_RNO_114, - \data_addr_w_1_iv_i_s_0[6]\, - \data_addr_w_1_iv_i_a2_0_0[6]\, N_106, - \data_addr_w_1_iv_i_a2_1_0[6]\, - \data_addr_r_1_iv_i_a2_0_0[6]\, - \data_addr_w_0_iv_i_a2_3_0[5]\, - \data_addr_r_1_iv_i_a2_1_0[6]\, - \data_addr_r_1_iv_i_s_0[6]\, N_31, - \data_addr_r_iv_i_4[4]\, \data_addr_r_iv_i_1[4]\, - \data_addr_r_iv_i_3[4]\, N_46, \data_addr_r_iv_i_2[4]\, - N_44, x0_RNO_111, \data_addr_r_iv_i_4[3]\, x0_RNO_87, - x0_RNO_88, \data_addr_r_iv_i_0[3]\, - \data_addr_r_iv_i_3[3]\, N_54, \data_addr_r_iv_i_2[3]\, - N_52, x0_RNO_110, \data_addr_r_iv_i_4[2]\, x0_RNO_84, - x0_RNO_85, \data_addr_r_iv_i_0[2]\, - \data_addr_r_iv_i_3[2]\, N_62, \data_addr_r_iv_i_2[2]\, - N_60, x0_RNO_109, \data_addr_w_0_iv_i_2[5]\, - \data_addr_w_0_iv_i_1[5]\, \data_addr_w_0_iv_i_0[5]\, - x0_RNO_63, \data_addr_w_iv_i_4[4]\, x0_RNO_100, - \data_addr_w_iv_i_1[4]\, \data_addr_w_iv_i_3[4]\, N_121, - \data_addr_w_iv_i_2[4]\, N_119, N_101_i_0, N_100_i_0, - N_67_i_0, N_66_i_0, N_65_i_0, x0_RNO_5, N_33, N_108, - x0_RNO_12, N_102_i_0, N_104_i_0, N_103_i_0, N_69_i_0, - N_105_i_0, N_68_i_0, x0_RNO, x0_RNO_13, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_2p_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - \proa3.x0_RNO_28\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(1), - C => N_75, Y => \data_addr_r_iv_i_2[1]\); - - \proa3.x0_RNO_13\ : OR3B - port map(A => data_mem_wen_i_0(2), B => data_mem_wen_i_0(3), - C => sFull_RNIE8AH1, Y => x0_RNO_13); - - \proa3.x0_RNO_80\ : OA1 - port map(A => time_mem_addr_r_0_0, B => time_mem_ren_i_0_0, - C => x0_RNO_107, Y => \data_addr_r_iv_i_0[0]\); - - \proa3.x0_RNO_75\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(0), Y => N_151); - - \proa3.x0_RNO_40\ : NOR3C - port map(A => x0_RNO_78, B => N_80, C => - \data_addr_r_iv_i_0[0]\, Y => \data_addr_r_iv_i_4[0]\); - - \proa3.x0_RNO_9\ : NOR3C - port map(A => \data_addr_w_iv_i_3[3]\, B => - \data_addr_w_iv_i_2[3]\, C => \data_addr_w_iv_i_4[3]\, Y - => N_102_i_0); - - \proa3.x0_RNO_6\ : NOR3C - port map(A => \data_addr_w_iv_i_1[0]\, B => - \data_addr_w_iv_i_0[0]\, C => \data_addr_w_iv_i_5[0]\, Y - => N_105_i_0); - - \proa3.x0_RNO_3\ : NOR3C - port map(A => \data_addr_r_iv_i_3[3]\, B => - \data_addr_r_iv_i_2[3]\, C => \data_addr_r_iv_i_4[3]\, Y - => N_66_i_0); - - \proa3.x0_RNO_12\ : OR3C - port map(A => N_161, B => N_108, C => - \data_addr_w_1_iv_i_s_0[6]\, Y => x0_RNO_12); - - \proa3.x0_RNO_27\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(0), - C => N_83, Y => \data_addr_r_iv_i_2[0]\); - - \proa3.x0_RNO_114\ : OR2 - port map(A => time_mem_addr_w_3_3, B => sFull_RNIODA01_0, Y - => x0_RNO_114); - - \proa3.x0_RNO_91\ : OR2 - port map(A => time_mem_addr_w_1_1, B => sFull_RNIKQ9G, Y - => x0_RNO_91); - - \proa3.x0_RNO_61\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(4), Y => N_121); - - \proa3.x0_RNO_103\ : OR3C - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => DWACT_FINC_E(0), Y => N_31); - - \proa3.x0_RNO_102\ : NOR3B - port map(A => time_mem_ren_i_0_0, B => - time_mem_addr_r_3_i_0_3, C => time_mem_ren_i_0_1, Y => - \data_addr_r_1_iv_i_a2_0_0[6]\); - - \proa3.x0_RNO_79\ : OR2 - port map(A => time_mem_addr_r_2_0, B => N_93, Y => N_80); - - \proa3.x0_RNO_31\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(4), - C => N_44, Y => \data_addr_r_iv_i_2[4]\); - - \proa3.x0_RNO_100\ : OR2 - port map(A => time_mem_wen_i_0_0, B => time_mem_addr_w_0_4, - Y => x0_RNO_100); - - \proa3.x0_RNO_8\ : NOR3C - port map(A => \data_addr_w_iv_i_3[2]\, B => - \data_addr_w_iv_i_2[2]\, C => \data_addr_w_iv_i_4[2]\, Y - => N_103_i_0); - - \proa3.x0_RNO_54\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(1), Y => N_77); - - \proa3.x0_RNO_4\ : NOR3C - port map(A => \data_addr_r_iv_i_3[4]\, B => - \data_addr_r_iv_i_2[4]\, C => \data_addr_r_iv_i_4[4]\, Y - => N_65_i_0); - - \proa3.x0_RNO_101\ : OA1B - port map(A => N_161, B => time_mem_addr_w_2_4, C => N_117, - Y => \data_addr_w_iv_i_1[4]\); - - \proa3.x0_RNO_20\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(4), - C => N_46, Y => \data_addr_r_iv_i_3[4]\); - - \proa3.x0_RNO_81\ : OR3A - port map(A => N_88, B => time_mem_ren_i_0_3, C => - time_mem_addr_r_3_1, Y => x0_RNO_81); - - \proa3.x0_RNO_41\ : NOR3C - port map(A => x0_RNO_81, B => N_72, C => - \data_addr_r_iv_i_0[1]\, Y => \data_addr_r_iv_i_4[1]\); - - \proa3.x0_RNO_14\ : OA1 - port map(A => N_161, B => time_mem_addr_w_2_0, C => - x0_RNO_51, Y => \data_addr_w_iv_i_1[0]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO_58\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(1), Y => N_145); - - \proa3.x0_RNO_95\ : OR2A - port map(A => Waddr_vect_0(2), B => time_mem_wen_i_0_0, Y - => x0_RNO_95); - - \proa3.x0_RNO_65\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(1), Y => N_75); - - \proa3.x0_RNO_76\ : OR2A - port map(A => N_162, B => data_mem_addr_w_0(0), Y => - x0_RNO_76); - - \proa3.x0_RNO_35\ : OA1A - port map(A => N_162, B => data_mem_addr_w_0(4), C => N_119, - Y => \data_addr_w_iv_i_2[4]\); - - \proa3.x0_RNO_2\ : NOR3C - port map(A => \data_addr_r_iv_i_3[2]\, B => - \data_addr_r_iv_i_2[2]\, C => \data_addr_r_iv_i_4[2]\, Y - => N_67_i_0); - - \proa3.x0_RNO_113\ : OR2A - port map(A => time_mem_addr_w_3_i_0_0, B => - sFull_RNIODA01_0, Y => x0_RNO_113); - - \proa3.x0_RNO_112\ : OR2 - port map(A => time_mem_addr_w_3_1, B => sFull_RNIODA01_0, Y - => x0_RNO_112); - - \proa3.x0_RNO_110\ : OR3B - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => time_mem_addr_r_1_3, Y => x0_RNO_110); - - \proa3.x0_RNO_57\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(4), Y => N_46); - - \proa3.x0_RNO_111\ : OR2 - port map(A => time_mem_ren_i_0_0, B => time_mem_addr_r_0_4, - Y => x0_RNO_111); - - \proa3.x0_RNO_105\ : OR2A - port map(A => DWACT_FINC_E_0(0), B => sFull_RNIKQ9G, Y => - N_106); - - \proa3.x0_RNO_73\ : NOR3A - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => data_mem_ren_i_0(0), Y => - \data_addr_r_1_iv_i_a2_1_0[6]\); - - \proa3.x0_RNO_18\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(2), - C => N_62, Y => \data_addr_r_iv_i_3[2]\); - - \proa3.x0_RNO_21\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(1), C => N_145, - Y => \data_addr_w_iv_i_3[1]\); - - \proa3.x0_RNO_99\ : OA1 - port map(A => N_161, B => time_mem_addr_w_2_3, C => - x0_RNO_114, Y => \data_addr_w_iv_i_1[3]\); - - \proa3.x0_RNO_85\ : OR2A - port map(A => Raddr_vect_1(2), B => N_93, Y => x0_RNO_85); - - \proa3.x0_RNO_72\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(4), Y => N_119); - - \proa3.x0_RNO_69\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(1), Y => N_143); - - \proa3.x0_RNO_45\ : NOR3C - port map(A => x0_RNO_91, B => N_138, C => - \data_addr_w_iv_i_1[1]\, Y => \data_addr_w_iv_i_4[1]\); - - \proa3.x0_RNO_39\ : NOR2 - port map(A => N_117, B => N_162, Y => - \data_addr_w_0_iv_i_2[5]\); - - \proa3.x0_RNO_17\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(1), - C => N_77, Y => \data_addr_r_iv_i_3[1]\); - - \proa3.x0_RNO_50\ : OA1A - port map(A => \data_addr_w_1_iv_i_a2_0_0[6]\, B => - time_mem_wen_i_0_3, C => N_106, Y => - \data_addr_w_1_iv_i_s_0[6]\); - - \proa3.x0_RNO_89\ : OA1 - port map(A => time_mem_addr_r_0_3, B => time_mem_ren_i_0_0, - C => x0_RNO_110, Y => \data_addr_r_iv_i_0[3]\); - - \proa3.x0_RNO_49\ : OA1A - port map(A => \data_addr_r_1_iv_i_a2_0_0[6]\, B => - time_mem_ren_i_0_3, C => N_31, Y => - \data_addr_r_1_iv_i_s_0[6]\); - - \proa3.x0_RNO_10\ : NOR3C - port map(A => \data_addr_w_iv_i_3[4]\, B => - \data_addr_w_iv_i_2[4]\, C => \data_addr_w_iv_i_4[4]\, Y - => N_101_i_0); - - \proa3.x0_RNO_25\ : OA1 - port map(A => time_mem_addr_w_0_0, B => time_mem_wen_i_0_0, - C => x0_RNO_62, Y => \data_addr_w_iv_i_0[0]\); - - \proa3.x0_RNO_96\ : OA1A - port map(A => Waddr_vect(2), B => N_161, C => x0_RNO_113, Y - => \data_addr_w_iv_i_1[2]\); - - \proa3.x0_RNO_74\ : NOR3A - port map(A => time_mem_wen_i_0_0, B => time_mem_wen_i_0_1, - C => data_mem_wen_i_0(0), Y => - \data_addr_w_1_iv_i_a2_1_0[6]\); - - \proa3.x0_RNO_66\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(2), Y => N_60); - - \proa3.x0_RNO_5\ : OR3C - port map(A => N_93, B => N_33, C => - \data_addr_r_1_iv_i_s_0[6]\, Y => x0_RNO_5); - - \proa3.x0_RNO_36\ : OR3B - port map(A => time_mem_ren_i_0_3, B => - \data_addr_r_1_iv_i_a2_1_0[6]\, C => data_mem_ren_i_0(1), - Y => N_33); - - \proa3.x0_RNO_108\ : OR3B - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => time_mem_addr_r_1_1, Y => x0_RNO_108); - - \proa3.x0_RNO_93\ : OA1 - port map(A => N_161, B => time_mem_addr_w_2_1, C => - x0_RNO_112, Y => \data_addr_w_iv_i_1[1]\); - - \proa3.x0_RNO_63\ : OR2 - port map(A => time_mem_wen_i_0_0, B => N_4_0, Y => - x0_RNO_63); - - \proa3.x0_RNO_33\ : OA1A - port map(A => N_162, B => data_mem_addr_w_0(2), C => N_135, - Y => \data_addr_w_iv_i_2[2]\); - - GND_i : GND - port map(Y => \GND\); - - \proa3.x0_RNO_51\ : OR2 - port map(A => time_mem_addr_w_3_0, B => sFull_RNIODA01_0, Y - => x0_RNO_51); - - \proa3.x0_RNO_92\ : OR2 - port map(A => time_mem_wen_i_0_0, B => time_mem_addr_w_0_1, - Y => N_138); - - \proa3.x0_RNO_62\ : OR2 - port map(A => time_mem_addr_w_1_0, B => sFull_RNIKQ9G, Y - => x0_RNO_62); - - \proa3.x0_RNO_29\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(2), - C => N_60, Y => \data_addr_r_iv_i_2[2]\); - - \proa3.x0_RNO_1\ : NOR3C - port map(A => \data_addr_r_iv_i_3[1]\, B => - \data_addr_r_iv_i_2[1]\, C => \data_addr_r_iv_i_4[1]\, Y - => N_68_i_0); - - \proa3.x0_RNO_86\ : OA1A - port map(A => Raddr_vect(2), B => time_mem_ren_i_0_0, C => - x0_RNO_109, Y => \data_addr_r_iv_i_0[2]\); - - \proa3.x0_RNO_46\ : NOR3C - port map(A => x0_RNO_94, B => x0_RNO_95, C => - \data_addr_w_iv_i_1[2]\, Y => \data_addr_w_iv_i_4[2]\); - - \proa3.x0_RNO_32\ : OA1A - port map(A => N_162, B => data_mem_addr_w_0(1), C => N_143, - Y => \data_addr_w_iv_i_2[1]\); - - \proa3.x0_RNO_78\ : OR3A - port map(A => N_88, B => time_mem_ren_i_0_3, C => - time_mem_addr_r_3_0, Y => x0_RNO_78); - - \proa3.x0_RNO_83\ : OA1 - port map(A => time_mem_addr_r_0_1, B => time_mem_ren_i_0_0, - C => x0_RNO_108, Y => \data_addr_r_iv_i_0[1]\); - - \proa3.x0_RNO_43\ : NOR3C - port map(A => x0_RNO_87, B => x0_RNO_88, C => - \data_addr_r_iv_i_0[3]\, Y => \data_addr_r_iv_i_4[3]\); - - \proa3.x0_RNO_11\ : NOR3C - port map(A => \data_addr_w_0_iv_i_1[5]\, B => - \data_addr_w_0_iv_i_0[5]\, C => \data_addr_w_0_iv_i_2[5]\, - Y => N_100_i_0); - - \proa3.x0_RNO_82\ : OR2 - port map(A => time_mem_addr_r_2_1, B => N_93, Y => N_72); - - \proa3.x0_RNO_42\ : NOR3C - port map(A => x0_RNO_84, B => x0_RNO_85, C => - \data_addr_r_iv_i_0[2]\, Y => \data_addr_r_iv_i_4[2]\); - - \proa3.x0_RNO_77\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(0), C => - x0_RNO_106, Y => \data_addr_w_iv_i_3[0]\); - - \proa3.x0_RNO_0\ : NOR3C - port map(A => \data_addr_r_iv_i_3[0]\, B => - \data_addr_r_iv_i_2[0]\, C => \data_addr_r_iv_i_4[0]\, Y - => N_69_i_0); - - \proa3.x0\ : proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 - port map(rclk => lclk_c, rena => x0_RNO, raddr(6) => - x0_RNO_5, raddr(5) => N_64_i_0, raddr(4) => N_65_i_0, - raddr(3) => N_66_i_0, raddr(2) => N_67_i_0, raddr(1) => - N_68_i_0, raddr(0) => N_69_i_0, dout(31) => hwdata(31), - dout(30) => hwdata(30), dout(29) => hwdata(29), dout(28) - => hwdata(28), dout(27) => hwdata(27), dout(26) => - hwdata(26), dout(25) => hwdata(25), dout(24) => - hwdata(24), dout(23) => hwdata(23), dout(22) => - hwdata(22), dout(21) => hwdata(21), dout(20) => - hwdata(20), dout(19) => hwdata(19), dout(18) => - hwdata(18), dout(17) => hwdata(17), dout(16) => - hwdata(16), dout(15) => hwdata(15), dout(14) => - hwdata(14), dout(13) => hwdata(13), dout(12) => - hwdata(12), dout(11) => hwdata(11), dout(10) => - hwdata(10), dout(9) => hwdata(9), dout(8) => hwdata(8), - dout(7) => hwdata(7), dout(6) => hwdata(6), dout(5) => - hwdata(5), dout(4) => hwdata(4), dout(3) => hwdata(3), - dout(2) => hwdata(2), dout(1) => hwdata(1), dout(0) => - hwdata(0), wclk => lclk_c, waddr(6) => x0_RNO_12, - waddr(5) => N_100_i_0, waddr(4) => N_101_i_0, waddr(3) - => N_102_i_0, waddr(2) => N_103_i_0, waddr(1) => - N_104_i_0, waddr(0) => N_105_i_0, din(31) => wdata(31), - din(30) => wdata(30), din(29) => wdata(29), din(28) => - wdata(28), din(27) => wdata(27), din(26) => wdata(26), - din(25) => wdata(25), din(24) => wdata(24), din(23) => - wdata(23), din(22) => wdata(22), din(21) => wdata(21), - din(20) => wdata(20), din(19) => wdata(19), din(18) => - wdata(18), din(17) => wdata(17), din(16) => wdata(16), - din(15) => wdata(15), din(14) => wdata(14), din(13) => - wdata(13), din(12) => wdata(12), din(11) => wdata(11), - din(10) => wdata(10), din(9) => wdata(9), din(8) => - wdata(8), din(7) => wdata(7), din(6) => wdata(6), din(5) - => wdata(5), din(4) => wdata(4), din(3) => wdata(3), - din(2) => wdata(2), din(1) => wdata(1), din(0) => - wdata(0), write => x0_RNO_13); - - \proa3.x0_RNO_55\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(2), Y => N_62); - - \proa3.x0_RNO_94\ : OR2A - port map(A => Waddr_vect_1(2), B => sFull_RNIKQ9G, Y => - x0_RNO_94); - - \proa3.x0_RNO_64\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(0), Y => N_83); - - \proa3.x0_RNO_26\ : OA1 - port map(A => N_161, B => N_4, C => x0_RNO_63, Y => - \data_addr_w_0_iv_i_0[5]\); - - \proa3.x0_RNO_34\ : OA1A - port map(A => N_162, B => data_mem_addr_w_0(3), C => N_127, - Y => \data_addr_w_iv_i_2[3]\); - - \proa3.x0_RNO_109\ : OR3C - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => Raddr_vect_0(2), Y => x0_RNO_109); - - \proa3.x0_RNO_107\ : OR3B - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => time_mem_addr_r_1_0, Y => x0_RNO_107); - - \proa3.x0_RNO_70\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(2), Y => N_135); - - \proa3.x0_RNO_23\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(3), C => N_129, - Y => \data_addr_w_iv_i_3[3]\); - - \proa3.x0_RNO_15\ : OA1B - port map(A => data_mem_wen_i_0(2), B => - \data_addr_w_0_iv_i_a2_3_0[5]\, C => N_115, Y => - \data_addr_w_0_iv_i_1[5]\); - - \proa3.x0_RNO_59\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(2), Y => N_137); - - \proa3.x0_RNO_22\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(2), C => N_137, - Y => \data_addr_w_iv_i_3[2]\); - - \proa3.x0_RNO_84\ : OR3B - port map(A => N_88, B => time_mem_addr_r_3_i_0_0, C => - time_mem_ren_i_0_3, Y => x0_RNO_84); - - \proa3.x0_RNO_44\ : NOR3A - port map(A => \data_addr_r_iv_i_1[4]\, B => N_37, C => N_35, - Y => \data_addr_r_iv_i_4[4]\); - - \proa3.x0_RNO_106\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(0), Y => x0_RNO_106); - - \proa3.x0_RNO_98\ : OR2 - port map(A => time_mem_wen_i_0_0, B => time_mem_addr_w_0_3, - Y => x0_RNO_98); - - \proa3.x0_RNO_68\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(4), Y => N_44); - - \proa3.x0_RNO_38\ : NOR3C - port map(A => N_151, B => x0_RNO_76, C => - \data_addr_w_iv_i_3[0]\, Y => \data_addr_w_iv_i_5[0]\); - - \proa3.x0_RNO_7\ : NOR3C - port map(A => \data_addr_w_iv_i_3[1]\, B => - \data_addr_w_iv_i_2[1]\, C => \data_addr_w_iv_i_4[1]\, Y - => N_104_i_0); - - \proa3.x0_RNO_19\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(3), - C => N_54, Y => \data_addr_r_iv_i_3[3]\); - - \proa3.x0_RNO_97\ : OR2 - port map(A => time_mem_addr_w_1_3, B => sFull_RNIKQ9G, Y - => x0_RNO_97); - - \proa3.x0_RNO_67\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(3), Y => N_52); - - \proa3.x0_RNO_37\ : OR3B - port map(A => time_mem_wen_i_0_3, B => - \data_addr_w_1_iv_i_a2_1_0[6]\, C => data_mem_wen_i_0(1), - Y => N_108); - - \proa3.x0_RNO_88\ : OR2 - port map(A => time_mem_addr_r_2_3, B => N_93, Y => - x0_RNO_88); - - \proa3.x0_RNO_71\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(3), Y => N_127); - - \proa3.x0_RNO_48\ : NOR3B - port map(A => x0_RNO_100, B => \data_addr_w_iv_i_1[4]\, C - => N_115, Y => \data_addr_w_iv_i_4[4]\); - - \proa3.x0_RNO_56\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(3), Y => N_54); - - \proa3.x0_RNO_24\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(4), C => N_121, - Y => \data_addr_w_iv_i_3[4]\); - - \proa3.x0_RNO_104\ : NOR3B - port map(A => time_mem_wen_i_0_0, B => - time_mem_addr_w_3_i_0_3, C => time_mem_wen_i_0_1, Y => - \data_addr_w_1_iv_i_a2_0_0[6]\); - - \proa3.x0_RNO_87\ : OR3A - port map(A => N_88, B => time_mem_ren_i_0_3, C => - time_mem_addr_r_3_3, Y => x0_RNO_87); - - \proa3.x0_RNO_47\ : NOR3C - port map(A => x0_RNO_97, B => x0_RNO_98, C => - \data_addr_w_iv_i_1[3]\, Y => \data_addr_w_iv_i_4[3]\); - - \proa3.x0_RNO_90\ : OA1 - port map(A => N_93, B => time_mem_addr_r_2_4, C => - x0_RNO_111, Y => \data_addr_r_iv_i_1[4]\); - - \proa3.x0_RNO_60\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(3), Y => N_129); - - \proa3.x0_RNO_53\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(0), Y => N_85); - - \proa3.x0_RNO\ : OR3A - port map(A => data_mem_ren_i_0(3), B => sEmpty_RNIU5CB661, - C => data_mem_ren_i_0(2), Y => x0_RNO); - - \proa3.x0_RNO_30\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(3), - C => N_52, Y => \data_addr_r_iv_i_2[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0_RNO_52\ : OR2 - port map(A => N_157, B => data_mem_wen_i_0(1), Y => - \data_addr_w_0_iv_i_a2_3_0[5]\); - - \proa3.x0_RNO_16\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(0), - C => N_85, Y => \data_addr_r_iv_i_3[0]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ2 is - - port( ready_i_0 : out std_logic_vector(2 to 2); - data_mem_wen_i_0 : out std_logic_vector(2 to 2); - data_ren : in std_logic_vector(2 to 2); - data_mem_ren_i_0 : out std_logic_vector(2 to 2); - data_wen : in std_logic_vector(2 to 2); - data_mem_addr_r_2 : out std_logic_vector(4 downto 0); - data_mem_addr_w_2 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sFull_RNIE8AH1 : in std_logic; - N_165 : out std_logic; - sEmpty_RNIU5CB661 : in std_logic; - sEmpty_RNIPJ7A8P1 : out std_logic; - un13_time_write : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ2; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ2 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, N_4, \DWACT_FINC_E[0]\, N_12_0, N_4_0, - \DWACT_FINC_E_0[0]\, un7_sempty_s_4, un7_sempty_s_3, - un7_sempty_s_2, un7_sempty_s_1, un7_sempty_s_0, - sEmpty_RNO_6_1, \sEmpty_RNO_7\, \data_mem_addr_w_2[1]\, - \Raddr_vect_RNI0RUI[4]_net_1\, \sEmpty_RNO_8\, - \data_mem_addr_w_2[0]\, \Raddr_vect_RNIS48G[0]_net_1\, - un5_sfull_s_4_2, \data_mem_addr_r_2[3]\, - \un8_waddr_vect_s[3]\, sFull_RNO_8_1, un5_sfull_s_4_1, - \data_mem_addr_r_2[1]\, \un8_waddr_vect_s[1]\, - sFull_RNO_5_2, un5_sfull_s_4_0, \data_mem_addr_r_2[0]\, - \un8_waddr_vect_s[0]\, ADD_7x7_fast_I23_Y_0_o2_0, N_21, - N_89_i, N_73, ADD_5x5_fast_I17_un1_Y_1, N130, - ADD_5x5_fast_I13_Y_0, ADD_5x5_fast_I17_un1_Y_0, - ADD_5x5_fast_I5_un1_Y_0, \data_mem_addr_w_2[3]\, - ADD_7x7_fast_I19_Y_i_o4_0, N_11, N91, N_72_i, - ADD_5x5_fast_I11_Y_0, N80, N94, N88, - ADD_5x5_fast_I9_un1_Y_0, un1_waddr_vect_slto3_0, - \data_mem_addr_w_2[2]\, un2_raddr_vect_slto3_0, - \data_mem_addr_r_2[2]\, I11_un1_Y, N98, N77, N81, - un5_sfull_s_4, \sEmpty\, Waddr_vect_n4, Waddr_vect_14_0, - un1_waddr_vect_s, Waddr_vect_c2, sFull_RNO_11, \sFull\, - Waddr_vect_n3, Waddr_vect_n2, Waddr_vect_c1_i_0, - un2_raddr_vect_s, I_5_27, \Raddr_vect_RNI5HLL[4]_net_1\, - I_9_27, \Raddr_vect_RNIB7CO[4]_net_1\, I_13_31, - \Raddr_vect_RNIIT2R[4]_net_1\, I_20_19, I_5_26, I_9_26, - I_20_18, \data_mem_ren_i_0[2]\, \data_mem_wen_i_0[2]\, - Waddr_vect_n1_i, un2_raddr_vect_slto1, - \data_mem_addr_r_2[4]\, Waddr_vect_e4, - \data_mem_addr_w_2[4]\, Waddr_vect_e3, Waddr_vect_e2, - Waddr_vect_e1, Waddr_vect_e0, I8_un1_Y, N_75, N87, N102, - \un132_ready0_1[4]\, I_13_30, un1_sempty_s, sEmpty_RNO_11, - N96, \un132_ready1_i[5]\, I12_un1_Y, un119_readylto4, - N_24, N_16_i, un134_ready, N_164, N_165_0, - \un132_ready1[4]\, \un132_ready0[4]\, un126_ready, N_9, - N_13, N_12_1, N_11_0, N_8, N_10, N_9_0, N_7, N_4_1, N_5, - N_6, N_9_1, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - data_mem_wen_i_0(2) <= \data_mem_wen_i_0[2]\; - data_mem_ren_i_0(2) <= \data_mem_ren_i_0[2]\; - data_mem_addr_r_2(4) <= \data_mem_addr_r_2[4]\; - data_mem_addr_r_2(3) <= \data_mem_addr_r_2[3]\; - data_mem_addr_r_2(2) <= \data_mem_addr_r_2[2]\; - data_mem_addr_r_2(1) <= \data_mem_addr_r_2[1]\; - data_mem_addr_r_2(0) <= \data_mem_addr_r_2[0]\; - data_mem_addr_w_2(4) <= \data_mem_addr_w_2[4]\; - data_mem_addr_w_2(3) <= \data_mem_addr_w_2[3]\; - data_mem_addr_w_2(2) <= \data_mem_addr_w_2[2]\; - data_mem_addr_w_2(1) <= \data_mem_addr_w_2[1]\; - data_mem_addr_w_2(0) <= \data_mem_addr_w_2[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, C => \data_mem_addr_w_2[2]\, Y - => N_9_1); - - un132_ready_1_16_ADD_5x5_fast_I4_Y : OA1B - port map(A => N_73, B => N_89_i, C => N_75, Y => N96); - - \ready_gen.un126_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_2[4]\, B => - \data_mem_addr_w_2[4]\, Y => N_7); - - sEmpty_RNO_8 : XNOR2 - port map(A => \Raddr_vect_RNI5HLL[4]_net_1\, B => - \data_mem_addr_w_2[2]\, Y => \sEmpty_RNO_8\); - - \Waddr_vect_RNI1GR3[0]\ : OR2B - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, Y => Waddr_vect_c1_i_0); - - un117_ready_0_0_ADD_5x5_fast_I25_Y_0 : AX1E - port map(A => I12_un1_Y, B => ADD_5x5_fast_I17_un1_Y_1, C - => N_89_i, Y => un119_readylto4); - - un132_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO1A - port map(A => N80, B => N_73, C => N_89_i, Y => - ADD_5x5_fast_I11_Y_0); - - \ready_gen.un126_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, C => N_5, Y => N_9_0); - - \Raddr_vect_RNIBEK4_0[4]\ : OR2A - port map(A => \data_mem_addr_r_2[4]\, B => - \data_mem_addr_w_2[4]\, Y => N_75); - - un132_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N98, B => N77, C => N81, Y => I11_un1_Y); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_r_2[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, Y => N_12); - - sEmpty_RNO : AO1A - port map(A => data_ren(2), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_11); - - \ready_gen.un126_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13); - - \Raddr_vect_RNIGUJ86[0]\ : OA1B - port map(A => N_164, B => N_165_0, C => N96, Y => - un134_ready); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNI0RUI[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[3]\); - - \Raddr_vect_RNIPEHD[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_2[4]\, Y => - un2_raddr_vect_s); - - un132_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1B - port map(A => \data_mem_addr_r_2[2]\, B => - \data_mem_addr_w_2[2]\, C => N88, Y => N77); - - \Raddr_vect_RNI9EK4[3]\ : XOR2 - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, Y => N_72_i); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_2[2]\, Y => - I_9_27); - - sFull_RNIVMMP1 : NOR2 - port map(A => \data_mem_wen_i_0[2]\, B => sFull_RNIE8AH1, Y - => N_165); - - \Waddr_vect_RNO[4]\ : MX2A - port map(A => Waddr_vect_n4, B => \data_mem_addr_w_2[4]\, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e4); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_11, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[2]\, - C => \data_mem_addr_w_2[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[2]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \data_mem_addr_w_2[1]\, - S => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_2[2]\, B => - Waddr_vect_c1_i_0, C => un1_waddr_vect_s, Y => - Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, Y => I_5_26); - - sEmpty_RNIRDRU1J : NOR3 - port map(A => un13_time_write, B => \sEmpty\, C => - data_ren_1z, Y => \data_mem_ren_i_0[2]\); - - \Raddr_vect_RNIBCD5[3]\ : NOR2 - port map(A => \data_mem_addr_r_2[3]\, B => - \data_mem_addr_r_2[2]\, Y => un2_raddr_vect_slto3_0); - - \Raddr_vect_RNI9EK4_0[3]\ : OR2A - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, Y => N_73); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIB7CO[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[3]\); - - un117_ready_0_0_ADD_5x5_fast_I1_G0N : OR2A - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_r_2[1]\, Y => N87); - - sEmpty_RNO_2 : AND2 - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, Y => - un7_sempty_s_3); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_2[3]\, Y => - I_13_30); - - un132_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75, Y => \un132_ready1_i[5]\); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(2), - Y => sFull_RNO_11); - - \ready_gen.un126_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_2[4]\, B => - \data_mem_addr_r_2[4]\, Y => N_11_0); - - un117_ready_0_0_ADD_5x5_fast_I5_un1_Y_0 : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => ADD_5x5_fast_I5_un1_Y_0); - - sFull_RNO_4 : OR2B - port map(A => I_5_26, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_2[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AND2 - port map(A => sEmpty_RNO_6_1, B => \sEmpty_RNO_7\, Y => - un7_sempty_s_2); - - un132_ready_0_0_0_ADD_7x7_fast_I20_Y_i_o2_0 : AO18 - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_w_2[0]\, Y - => N_11); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNI5HLL[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[2]\); - - \Waddr_vect_RNI5GR3[3]\ : NOR2 - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_w_2[2]\, Y => un1_waddr_vect_slto3_0); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[0]\); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_18, C => - \data_mem_addr_r_2[4]\, Y => sFull_RNO_8_1); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_2[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - un132_ready_1_16_ADD_5x5_fast_I15_Y_0 : AX1D - port map(A => I8_un1_Y, B => N80, C => \un132_ready0_1[4]\, - Y => \un132_ready1[4]\); - - sFull_RNIHEC8 : OR2 - port map(A => \sFull\, B => data_wen(2), Y => - \data_mem_wen_i_0[2]\); - - \Raddr_vect_RNI0RUI[4]\ : NOR2B - port map(A => I_5_27, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNI0RUI[4]_net_1\); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_26, C => - \data_mem_addr_r_2[2]\, Y => sFull_RNO_5_2); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \data_mem_addr_w_2[2]\, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e2); - - un117_ready_0_0_ADD_5x5_fast_I17_un1_Y_1 : OA1 - port map(A => N130, B => ADD_5x5_fast_I13_Y_0, C => - ADD_5x5_fast_I17_un1_Y_0, Y => ADD_5x5_fast_I17_un1_Y_1); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_2[1]\, B => - \Raddr_vect_RNI0RUI[4]_net_1\, C => \sEmpty_RNO_8\, Y => - un7_sempty_s_1); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_2[3]\, Y - => Waddr_vect_14_0); - - un132_ready_1_16_ADD_5x5_fast_I8_un1_Y : NOR2B - port map(A => N81, B => N77, Y => I8_un1_Y); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_2[3]\, B => - \un8_waddr_vect_s[3]\, C => sFull_RNO_8_1, Y => - un5_sfull_s_4_2); - - sEmpty_RNO_0 : AND2 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, Y => - un7_sempty_s_4); - - un117_ready_0_0_ADD_5x5_fast_I12_un1_Y : OR3B - port map(A => N91, B => N94, C => N102, Y => I12_un1_Y); - - \Raddr_vect_RNIBEK4[4]\ : XNOR2 - port map(A => \data_mem_addr_w_2[4]\, B => - \data_mem_addr_r_2[4]\, Y => N_89_i); - - sEmpty_RNO_7 : XNOR2 - port map(A => \Raddr_vect_RNIB7CO[4]_net_1\, B => - \data_mem_addr_w_2[3]\, Y => \sEmpty_RNO_7\); - - un132_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75, Y => N_16_i); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : AO1D - port map(A => ADD_7x7_fast_I19_Y_i_o4_0, B => N_21, C => - N_89_i, Y => N_24); - - \ready_gen.un126_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, C => N_6, Y => N_8); - - \ready_gen.un126_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, Y => N_4_1); - - GND_i : GND - port map(Y => \GND\); - - un132_ready_1_16_ADD_5x5_fast_I1_G0N : NOR2A - port map(A => N91, B => N_72_i, Y => N80); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIS48G[0]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[0]\); - - \Raddr_vect_RNIPNHE3[0]\ : MX2C - port map(A => \un132_ready1_i[5]\, B => N_16_i, S => - \data_mem_addr_r_2[0]\, Y => N_165_0); - - un132_ready_0_0_0_ADD_7x7_fast_I19_Y_i_a2_0 : NOR3A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, C => N_11, Y => N_21); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_r_2[0]\, Y => N_12_0); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_2[2]\, Y => - I_9_26); - - un132_ready_1_16_ADD_5x5_fast_I1_P0N : OR2A - port map(A => N_72_i, B => N91, Y => N81); - - \ready_gen.un126_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, C => N_7, Y => N_12_1); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_2[3]\, Y => - I_13_31); - - \Raddr_vect_RNIOR4C2[0]\ : MX2 - port map(A => \un132_ready1[4]\, B => \un132_ready0[4]\, S - => \data_mem_addr_r_2[0]\, Y => N_164); - - \Raddr_vect_RNI7CD5[1]\ : OR2B - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_r_2[0]\, Y => un2_raddr_vect_slto1); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_r_2[2]\, Y - => N_9); - - un132_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : AX1D - port map(A => N_21, B => ADD_7x7_fast_I19_Y_i_o4_0, C => - \un132_ready0_1[4]\, Y => \un132_ready0[4]\); - - \Raddr_vect_RNI5HLL[4]\ : NOR2B - port map(A => I_9_27, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNI5HLL[4]_net_1\); - - \ready_gen.un126_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_w_2[0]\, Y => N_6); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(2), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_2[4]\, Y => - I_20_19); - - \Raddr_vect_RNI391A9[0]\ : MX2 - port map(A => un119_readylto4, B => un134_ready, S => - un126_ready, Y => ready_i_0(2)); - - un117_ready_0_0_ADD_5x5_fast_I3_P0N : OR2A - port map(A => \data_mem_addr_r_2[3]\, B => - \data_mem_addr_w_2[3]\, Y => N94); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_2[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_2, Y => - un5_sfull_s_4_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, Y => I_5_27); - - un117_ready_0_0_ADD_5x5_fast_I2_P0N : OR2A - port map(A => \data_mem_addr_r_2[2]\, B => - \data_mem_addr_w_2[2]\, Y => N91); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_2[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[4]\); - - sFull_RNO_7 : OR2B - port map(A => I_13_30, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \ready_gen.un126_ready_0_I_11\ : OA1 - port map(A => N_13, B => N_12_1, C => N_11_0, Y => - un126_ready); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AO1A - port map(A => N_21, B => N_89_i, C => N_73, Y => - ADD_7x7_fast_I23_Y_0_o2_0); - - \Waddr_vect_RNO[3]\ : MX2A - port map(A => Waddr_vect_n3, B => \data_mem_addr_w_2[3]\, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e3); - - \ready_gen.un126_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => N_5); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \Raddr_vect_RNIIT2R[4]_net_1\, B => - \data_mem_addr_w_2[4]\, Y => sEmpty_RNO_6_1); - - \Raddr_vect_RNIS48G[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_2[0]\, - Y => \Raddr_vect_RNIS48G[0]_net_1\); - - \Waddr_vect_RNIAOK9[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => - Waddr_vect_c1_i_0, C => \data_mem_addr_w_2[4]\, Y => - un1_waddr_vect_s); - - sFull : DFN1C0 - port map(D => sFull_RNO_11, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_2[4]\, Y => - I_20_18); - - un132_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_89_i, B => N_73, Y => N98); - - un132_ready_0_0_0_ADD_7x7_fast_I32_Y_0_1 : XOR2 - port map(A => N_89_i, B => N_73, Y => \un132_ready0_1[4]\); - - un117_ready_0_0_ADD_5x5_fast_I0_P0N : NOR2A - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_w_2[0]\, Y => N130); - - \ready_gen.un126_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, C => N_4_1, Y => N_10); - - un132_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_0 : OA1C - port map(A => N_11, B => N91, C => N_72_i, Y => - ADD_7x7_fast_I19_Y_i_o4_0); - - un117_ready_0_0_ADD_5x5_fast_I9_Y : OA1 - port map(A => \data_mem_addr_r_2[0]\, B => - ADD_5x5_fast_I9_un1_Y_0, C => N87, Y => N102); - - \sEmpty_RNIPJ7A8P1\ : NOR2A - port map(A => \data_mem_ren_i_0[2]\, B => sEmpty_RNIU5CB661, - Y => sEmpty_RNIPJ7A8P1); - - \Raddr_vect_RNIIT2R[4]\ : NOR2B - port map(A => I_20_19, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNIIT2R[4]_net_1\); - - un117_ready_0_0_ADD_5x5_fast_I9_un1_Y_0 : OR2A - port map(A => \data_mem_addr_w_2[0]\, B => N88, Y => - ADD_5x5_fast_I9_un1_Y_0); - - un117_ready_0_0_ADD_5x5_fast_I1_P0N : NOR2A - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, Y => N88); - - un117_ready_0_0_ADD_5x5_fast_I17_un1_Y_0 : AO18 - port map(A => ADD_5x5_fast_I5_un1_Y_0, B => - \data_mem_addr_r_2[3]\, C => \data_mem_addr_w_2[3]\, Y - => ADD_5x5_fast_I17_un1_Y_0); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[1]\); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIIT2R[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[4]\); - - \Waddr_vect_RNI38P5[2]\ : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => - Waddr_vect_c1_i_0, Y => Waddr_vect_c2); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_2[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(2), Y => - un5_sfull_s_4_0); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_2[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - sEmpty_RNO_5 : XA1A - port map(A => \data_mem_addr_w_2[0]\, B => - \Raddr_vect_RNIS48G[0]_net_1\, C => data_wen(2), Y => - un7_sempty_s_0); - - \Raddr_vect_RNIB7CO[4]\ : NOR2B - port map(A => I_13_31, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNIB7CO[4]_net_1\); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_2[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, C => \data_mem_addr_w_2[2]\, Y - => \DWACT_FINC_E[0]\); - - un117_ready_0_0_ADD_5x5_fast_I13_Y_0 : OR3B - port map(A => N91, B => N94, C => N88, Y => - ADD_5x5_fast_I13_Y_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ5 is - - port( time_mem_wen_i_0 : inout std_logic_vector(1 downto 0) := (others => 'Z'); - time_mem_ren_i_0 : inout std_logic_vector(1 downto 0) := (others => 'Z'); - time_wen : in std_logic_vector(1 to 1); - time_ren : in std_logic_vector(1 to 1); - time_mem_addr_w_1_3 : out std_logic; - time_mem_addr_w_1_0 : out std_logic; - time_mem_addr_w_1_1 : out std_logic; - time_mem_addr_r_1_3 : out std_logic; - time_mem_addr_r_1_0 : out std_logic; - time_mem_addr_r_1_1 : out std_logic; - DWACT_FINC_E_0 : out std_logic_vector(0 to 0); - Waddr_vect_0 : out std_logic; - DWACT_FINC_E : out std_logic_vector(0 to 0); - Raddr_vect_0 : out std_logic; - time_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - un20_time_write : in std_logic; - sFull_RNIKQ9G : out std_logic; - N_115 : out std_logic; - N_35 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ5; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ5 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \time_mem_addr_r_1[5]\, \Raddr_vect[3]_net_1\, - \Raddr_vect[2]_net_1\, \time_mem_addr_w_1[5]\, - \Waddr_vect[3]_net_1\, \Waddr_vect[2]_net_1\, N_7, N_7_0, - un10_sempty_s_3_0_1, \un10_raddr_vect_s[3]\, - un2_sfull_s_3_0_1, \un8_waddr_vect_s[3]\, un5_sfull_s_2, - un7_sempty_s_2, un5_sfull_s_3, sFull_RNO_3_2, - sFull_RNO_4_2, un5_sfull_s_0, \un8_waddr_vect_s[0]\, - \time_mem_addr_r_1[0]\, un7_sempty_s_3, sEmpty_RNO_3_2, - sEmpty_RNO_4_2, un7_sempty_s_0, \un10_raddr_vect_s[0]\, - \time_mem_addr_w_1[0]\, un1_waddr_vect_slt3, - \time_mem_addr_w_1[1]\, un2_raddr_vect_slt3, - \time_mem_addr_r_1[1]\, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, Raddr_vect_n2, - un2_raddr_vect_s, Raddr_vect_n2_tz, Waddr_vect_n2, - un1_waddr_vect_s, Waddr_vect_n2_tz, sFull_RNIKQ9G_net_1, - I_13_24, I_9_20, I_9_21, I_5_21, Raddr_vect_n1_i, - Raddr_vect_e2, Raddr_vect_e1, Raddr_vect_e0, I_13_25, - \sEmpty_RNO_2\, un2_sempty_s, \sEmpty\, Waddr_vect_e0, - Waddr_vect_e1, Waddr_vect_n1_i, Waddr_vect_e2, \sFull\, - un8_sfull_s, sFull_RNO_7, I_5_20, N_4, N_4_0, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - time_mem_addr_w_1_0 <= \time_mem_addr_w_1[0]\; - time_mem_addr_w_1_1 <= \time_mem_addr_w_1[1]\; - time_mem_addr_r_1_0 <= \time_mem_addr_r_1[0]\; - time_mem_addr_r_1_1 <= \time_mem_addr_r_1[1]\; - Waddr_vect_0 <= \Waddr_vect[2]_net_1\; - Raddr_vect_0 <= \Raddr_vect[2]_net_1\; - sFull_RNIKQ9G <= sFull_RNIKQ9G_net_1; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_1[1]\, B => - \time_mem_addr_w_1[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4); - - \Waddr_vect_RNI2QV3[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_1[1]\, B => - \time_mem_addr_r_1[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - un36_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_1[5]\); - - sFull_RNINN9I : NOR2 - port map(A => \time_mem_addr_w_1[5]\, B => - sFull_RNIKQ9G_net_1, Y => N_115); - - sEmpty_RNI20LH : NOR3A - port map(A => time_ren_1z, B => un20_time_write, C => - \sEmpty\, Y => time_mem_ren_i_0(1)); - - un36_mem_addr_wen_I_16 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => DWACT_FINC_E_0(0)); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_1[1]\, B => - \time_mem_addr_w_1[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_2\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_1[1]\); - - \Waddr_vect[3]\ : DFN1E1C0 - port map(D => Waddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => time_mem_wen_i_0(1), Q => \Waddr_vect[3]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_21); - - un2_sfull_s_3_0_RNO : OR2B - port map(A => I_13_24, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_2\, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => un1_waddr_vect_s, B => time_mem_wen_i_0(1), C - => \time_mem_addr_w_1[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Waddr_vect[2]_net_1\); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \time_mem_addr_w_1[1]\, B => Waddr_vect_n1_i, - S => time_mem_wen_i_0(1), Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, Y => I_5_20); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => Raddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => time_mem_ren_i_0(1), Q => \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(1), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4, B => \Waddr_vect[3]_net_1\, Y => I_13_24); - - un31_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_1_3); - - un2_sfull_s_3_0 : XOR2 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, Y => un2_sfull_s_3_0_1); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => sFull_RNO_7); - - \Raddr_vect_RNO[0]\ : AXOI5 - port map(A => un2_raddr_vect_s, B => time_mem_ren_i_0(1), C - => \time_mem_addr_r_1[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2B - port map(A => \time_mem_addr_r_1[1]\, B => Raddr_vect_n1_i, - S => time_mem_ren_i_0(1), Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_20, C => - \time_mem_addr_r_1[1]\, Y => sFull_RNO_4_2); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_1[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_21, C => - \Waddr_vect[2]_net_1\, Y => sEmpty_RNO_3_2); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Raddr_vect[2]_net_1\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_1[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_1[0]\, C => time_wen(1), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \Waddr_vect[2]_net_1\, B => Waddr_vect_n2, S - => time_mem_wen_i_0(1), Y => Waddr_vect_e2); - - un31_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_1[5]\); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_21, C => - \time_mem_addr_w_1[1]\, Y => sEmpty_RNO_4_2); - - un10_sempty_s_3_0 : XOR2 - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, Y => un10_sempty_s_3_0_1); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_20, C => - \Raddr_vect[2]_net_1\, Y => sFull_RNO_3_2); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_2, B => sEmpty_RNO_4_2, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un36_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_1_3); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2B - port map(A => \Raddr_vect[2]_net_1\, B => Raddr_vect_n2, S - => time_mem_ren_i_0(1), Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_1[0]\); - - sFull_RNICO38 : NOR2 - port map(A => time_wen(1), B => \sFull\, Y => - time_mem_wen_i_0(1)); - - sEmpty_RNIAR591 : NOR3B - port map(A => time_mem_ren_i_0(0), B => time_mem_ren_i_0(1), - C => \time_mem_addr_r_1[5]\, Y => N_35); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_1[1]\, B => - \time_mem_addr_r_1[0]\, Y => N_7); - - un10_sempty_s_3_0_RNO : OR2B - port map(A => I_13_25, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => - I_9_20); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_0, B => \Raddr_vect[3]_net_1\, Y => - I_13_25); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_0); - - sEmpty_RNO_1 : NOR2A - port map(A => un10_sempty_s_3_0_1, B => time_ren(1), Y => - un7_sempty_s_2); - - sFull_RNO_1 : AND2 - port map(A => time_ren(1), B => un2_sfull_s_3_0_1, Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, Y => I_5_21); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - \Waddr_vect_RNIGRV2[1]\ : OR3 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - \sFull_RNIKQ9G\ : OR2B - port map(A => time_mem_wen_i_0(1), B => time_mem_wen_i_0(0), - Y => sFull_RNIKQ9G_net_1); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - \Raddr_vect_RNIPLA5[1]\ : OR3 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - un31_mem_addr_ren_I_16 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => DWACT_FINC_E(0)); - - sFull_RNO_0 : NOR3C - port map(A => sFull_RNO_3_2, B => sFull_RNO_4_2, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_1[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Raddr_vect_RNIEI37[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - sFull : DFN1C0 - port map(D => sFull_RNO_7, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_1[1]\); - - sFull_RNO_2 : OA1A - port map(A => time_ren_1z, B => un20_time_write, C => - \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_1[0]\, C => time_wen(1), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ3 is - - port( ready_i_0 : out std_logic_vector(3 to 3); - data_mem_wen_i_0 : out std_logic_vector(3 to 3); - data_ren : in std_logic_vector(3 to 3); - data_mem_ren_i_0 : out std_logic_vector(3 to 3); - data_wen : in std_logic_vector(3 to 3); - data_mem_addr_r_3 : out std_logic_vector(4 downto 0); - data_mem_addr_w_3 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - un5_time_write : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ3; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ3 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI4 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, N_4, \DWACT_FINC_E[0]\, N_12_0, N_4_0, - \DWACT_FINC_E_0[0]\, I16_un1_Y, N111, N115, N_73_i, - N_74_i, N_71_1, N_72_i, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \data_mem_addr_w_3[3]\, - \un10_raddr_vect_s[3]\, \sEmpty_RNO_6\, - \data_mem_addr_w_3[1]\, \un10_raddr_vect_s[1]\, - \sEmpty_RNO_5\, \data_mem_addr_w_3[0]\, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \data_mem_addr_r_3[3]\, \un8_waddr_vect_s[3]\, - \sFull_RNO_8\, un5_sfull_s_4_1, \data_mem_addr_r_3[1]\, - \un8_waddr_vect_s[1]\, \sFull_RNO_5\, un5_sfull_s_4_0, - \data_mem_addr_r_3[0]\, \un8_waddr_vect_s[0]\, - ADD_7x7_fast_I26_Y_0, N114, ADD_7x7_fast_I27_un1_Y_0, - N151, ADD_5x5_fast_I17_un1_Y_1, I5_un1_Y, N110, - ADD_7x7_fast_I25_un1_Y_0, N135, un1_waddr_vect_slto3_0, - ADD_7x7_fast_I13_un1_Y_0, N101, un2_raddr_vect_slto3_0, - \data_mem_addr_w_3[2]\, N94, \data_mem_addr_r_3[2]\, - \un189_ready_i[4]\, I27_un1_Y, N139, I25_un1_Y, N140, - N146, N_75_1_i_0, un5_sfull_s_4, \sEmpty\, Waddr_vect_n4, - Waddr_vect_14_0, un1_waddr_vect_s, Waddr_vect_c2, - sFull_RNO_9, \sFull\, Waddr_vect_n2, Waddr_vect_c1, - Waddr_vect_n3, sEmpty_RNO_9, un1_sempty_s, - un2_raddr_vect_s, I_5_23, \un10_raddr_vect_s[2]\, I_9_23, - I_13_27, \un10_raddr_vect_s[4]\, I_20_15, - \data_mem_addr_w_3[4]\, I_20_14, I_9_22, I_13_26, I_5_22, - un2_raddr_vect_slto1, \data_mem_addr_r_3[4]\, - un176_readylto4, un191_ready_i_0, un183_ready, - \un189_ready_i[5]\, I12_un1_Y, N99, Waddr_vect_e0, - \data_mem_wen_i_0[3]\, Waddr_vect_e1, Waddr_vect_n1_i, - Waddr_vect_e2, Waddr_vect_e3, Waddr_vect_e4, N141, N100, - \data_mem_ren_i_0[3]\, N_9, N_13, N_12_1, N_11, N_8, N_10, - N_9_0, N_7, N_4_1, N_5, N_6, N_9_1, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - data_mem_wen_i_0(3) <= \data_mem_wen_i_0[3]\; - data_mem_ren_i_0(3) <= \data_mem_ren_i_0[3]\; - data_mem_addr_r_3(4) <= \data_mem_addr_r_3[4]\; - data_mem_addr_r_3(3) <= \data_mem_addr_r_3[3]\; - data_mem_addr_r_3(2) <= \data_mem_addr_r_3[2]\; - data_mem_addr_r_3(1) <= \data_mem_addr_r_3[1]\; - data_mem_addr_r_3(0) <= \data_mem_addr_r_3[0]\; - data_mem_addr_w_3(4) <= \data_mem_addr_w_3[4]\; - data_mem_addr_w_3(3) <= \data_mem_addr_w_3[3]\; - data_mem_addr_w_3(2) <= \data_mem_addr_w_3[2]\; - data_mem_addr_w_3(1) <= \data_mem_addr_w_3[1]\; - data_mem_addr_w_3(0) <= \data_mem_addr_w_3[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, C => \data_mem_addr_w_3[2]\, Y - => N_9_1); - - un189_ready_0_0_ADD_7x7_fast_I1_G0N : NOR2A - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_r_3[1]\, Y => N100); - - \ready_gen.un183_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, C => N_7, Y => N_12_1); - - un189_ready_0_0_ADD_7x7_fast_I35_Y_0 : XOR3 - port map(A => N_74_i, B => N_73_i, C => I27_un1_Y, Y => - \un189_ready_i[4]\); - - un189_ready_0_0_ADD_7x7_fast_I13_un1_Y_0 : NOR2B - port map(A => \data_mem_addr_w_3[0]\, B => N101, Y => - ADD_7x7_fast_I13_un1_Y_0); - - \ready_gen.un183_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_w_3[0]\, Y => N_6); - - \Raddr_vect_RNIGT0F1[4]\ : NOR2B - port map(A => I_20_15, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, C => \data_mem_addr_r_3[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, Y => N_12); - - sEmpty_RNO : AO1A - port map(A => data_ren(3), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_9); - - \ready_gen.un183_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, Y => N_4_1); - - \Raddr_vect_RNIH1K8[4]\ : XNOR2 - port map(A => \data_mem_addr_w_3[4]\, B => - \data_mem_addr_r_3[4]\, Y => N_74_i); - - \Raddr_vect[1]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[3]\); - - \ready_gen.un183_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, Y => N_5); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_3[2]\, Y => - I_9_23); - - un189_ready_0_0_ADD_7x7_fast_I13_Y : OA1C - port map(A => ADD_7x7_fast_I13_un1_Y_0, B => - \data_mem_addr_r_3[0]\, C => N100, Y => N139); - - un174_ready_0_0_ADD_5x5_fast_I13_Y : OR2A - port map(A => N99, B => N140, Y => N110); - - \Waddr_vect_RNO[4]\ : MX2A - port map(A => Waddr_vect_n4, B => \data_mem_addr_w_3[4]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e4); - - un189_ready_0_0_ADD_7x7_fast_I26_Y_0 : NOR2B - port map(A => N114, B => I16_un1_Y, Y => - ADD_7x7_fast_I26_Y_0); - - un189_ready_0_0_ADD_7x7_fast_I25_un1_Y_0 : AOI1B - port map(A => N_74_i, B => N_73_i, C => N135, Y => - ADD_7x7_fast_I25_un1_Y_0); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_9, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[3]\, - C => \data_mem_addr_w_3[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[2]\); - - un189_ready_0_0_ADD_7x7_fast_I0_P0N : OR2A - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_w_3[0]\, Y => N141); - - \ready_gen.un183_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, C => N_5, Y => N_9_0); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \data_mem_addr_w_3[1]\, - S => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - un189_ready_0_0_ADD_7x7_fast_I1_P0N : OR2A - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, Y => N101); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_3[2]\, B => Waddr_vect_c1, C - => un1_waddr_vect_s, Y => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, Y => I_5_22); - - un189_ready_0_0_ADD_7x7_fast_I27_un1_Y : OA1C - port map(A => N135, B => N139, C => - ADD_7x7_fast_I27_un1_Y_0, Y => I27_un1_Y); - - \ready_gen.un183_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, C => N_4_1, Y => N_10); - - \Raddr_vect_RNITTJ51[4]\ : NOR2B - port map(A => I_9_23, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[3]\); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_3[1]\, B => - \un10_raddr_vect_s[1]\, C => \sEmpty_RNO_5\, Y => - un7_sempty_s_1); - - \ready_gen.un183_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_3[4]\, B => - \data_mem_addr_w_3[4]\, Y => N_7); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_3[3]\, Y => - I_13_26); - - un174_ready_0_0_ADD_5x5_fast_I12_un1_Y : OR2A - port map(A => N99, B => N139, Y => I12_un1_Y); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(3), - Y => sFull_RNO_9); - - \Waddr_vect_RNIB3R7[3]\ : NOR2 - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_w_3[2]\, Y => un1_waddr_vect_slto3_0); - - \Raddr_vect_RNIDVC9[0]\ : OR2B - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_r_3[0]\, Y => un2_raddr_vect_slto1); - - sFull_RNO_4 : OR2B - port map(A => I_5_22, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_3[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_3[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(3), Y => - un7_sempty_s_0); - - \ready_gen.un191_readylto6\ : AOI1B - port map(A => \un189_ready_i[4]\, B => \un189_ready_i[5]\, - C => N146, Y => un191_ready_i_0); - - \Raddr_vect[2]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[2]\); - - \Raddr_vect_RNID1K8[2]\ : NOR2A - port map(A => \data_mem_addr_r_3[2]\, B => - \data_mem_addr_w_3[2]\, Y => N_71_1); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[0]\); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_14, C => - \data_mem_addr_r_3[4]\, Y => \sFull_RNO_8\); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_3[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - un174_ready_0_0_ADD_5x5_fast_I3_P0N : OR2A - port map(A => \data_mem_addr_r_3[3]\, B => - \data_mem_addr_w_3[3]\, Y => N94); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_22, C => - \data_mem_addr_r_3[2]\, Y => \sFull_RNO_5\); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \data_mem_addr_w_3[2]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e2); - - un189_ready_0_0_ADD_7x7_fast_I14_Y : OR2B - port map(A => N141, B => N101, Y => N140); - - m2 : MX2 - port map(A => un176_readylto4, B => un191_ready_i_0, S => - un183_ready, Y => ready_i_0(3)); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_3[3]\, B => - \un10_raddr_vect_s[3]\, C => \sEmpty_RNO_6\, Y => - un7_sempty_s_2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_3[3]\, Y - => Waddr_vect_14_0); - - sFull_RNIL4A8 : OR2 - port map(A => \sFull\, B => data_wen(3), Y => - \data_mem_wen_i_0[3]\); - - \Raddr_vect_RNIF1K8_0[3]\ : OR2A - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, Y => N_73_i); - - un189_ready_0_0_ADD_7x7_fast_I3_G0N : OR2 - port map(A => N_74_i, B => N_73_i, Y => N114); - - un189_ready_0_0_ADD_7x7_fast_I21_Y : NOR2A - port map(A => N135, B => N140, Y => N151); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_3[3]\, B => - \un8_waddr_vect_s[3]\, C => \sFull_RNO_8\, Y => - un5_sfull_s_4_2); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - \ready_gen.un183_ready_0_I_11\ : OA1 - port map(A => N_13, B => N_12_1, C => N_11, Y => - un183_ready); - - \Raddr_vect_RNIF1K8[3]\ : XOR2 - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, Y => N_72_i); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNIH1K8_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_3[4]\, B => - \data_mem_addr_w_3[4]\, Y => N_75_1_i_0); - - \Raddr_vect[0]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[0]\); - - un174_ready_0_0_ADD_5x5_fast_I6_Y : NOR2A - port map(A => N94, B => N_71_1, Y => N99); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_r_3[0]\, Y => N_12_0); - - \Waddr_vect_RNI73R7[0]\ : OR2B - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, Y => Waddr_vect_c1); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_3[2]\, Y => - I_9_22); - - \Raddr_vect_RNIOEGN[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_3[4]\, Y => - un2_raddr_vect_s); - - \Raddr_vect_RNIEU6S[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_3[0]\, - Y => \un10_raddr_vect_s[0]\); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_3[3]\, Y => - I_13_27); - - sEmpty_RNIUBH42J : OR3 - port map(A => un5_time_write, B => \sEmpty\, C => - data_ren_1z, Y => \data_mem_ren_i_0[3]\); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, C => \data_mem_addr_r_3[2]\, Y - => N_9); - - \ready_gen.un183_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13); - - \Raddr_vect_RNI5ET01[4]\ : NOR2B - port map(A => I_5_23, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(3), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_3[4]\, Y => - I_20_15); - - un189_ready_0_0_ADD_7x7_fast_I10_Y : AXOI4 - port map(A => N_72_i, B => \data_mem_addr_r_3[2]\, C => - \data_mem_addr_w_3[2]\, Y => N135); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_3[1]\, B => - \un8_waddr_vect_s[1]\, C => \sFull_RNO_5\, Y => - un5_sfull_s_4_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, Y => I_5_23); - - un189_ready_0_0_ADD_7x7_fast_I3_P0N : NAND2 - port map(A => N_73_i, B => N_74_i, Y => N115); - - un189_ready_0_0_ADD_7x7_fast_I16_un1_Y : NAND2 - port map(A => N111, B => N115, Y => I16_un1_Y); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_3[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[4]\); - - un189_ready_0_0_ADD_7x7_fast_I2_G0N : NOR2 - port map(A => N_71_1, B => N_72_i, Y => N111); - - un189_ready_0_0_ADD_7x7_fast_I16_Y : OR3C - port map(A => N114, B => N_75_1_i_0, C => I16_un1_Y, Y => - N146); - - sFull_RNO_7 : OR2B - port map(A => I_13_26, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Waddr_vect_RNI9OJJ[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => Waddr_vect_c1, C - => \data_mem_addr_w_3[4]\, Y => un1_waddr_vect_s); - - \Waddr_vect_RNO[3]\ : MX2A - port map(A => Waddr_vect_n3, B => \data_mem_addr_w_3[3]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e3); - - un174_ready_0_0_ADD_5x5_fast_I5_un1_Y : OR3B - port map(A => \data_mem_addr_w_3[2]\, B => N94, C => - \data_mem_addr_r_3[2]\, Y => I5_un1_Y); - - un174_ready_0_0_ADD_5x5_fast_I25_Y_0 : AX1E - port map(A => I12_un1_Y, B => ADD_5x5_fast_I17_un1_Y_1, C - => N_74_i, Y => un176_readylto4); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_3[4]\, Y => \sEmpty_RNO_6\); - - \Raddr_vect_RNIMDAA1[4]\ : NOR2B - port map(A => I_13_27, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un189_ready_0_0_ADD_7x7_fast_I27_un1_Y_0 : AO1D - port map(A => N_72_i, B => N_71_1, C => N151, Y => - ADD_7x7_fast_I27_un1_Y_0); - - \Raddr_vect_RNIHVC9[3]\ : NOR2 - port map(A => \data_mem_addr_r_3[3]\, B => - \data_mem_addr_r_3[2]\, Y => un2_raddr_vect_slto3_0); - - sFull : DFN1C0 - port map(D => sFull_RNO_9, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_3[4]\, Y => - I_20_14); - - un189_ready_0_0_ADD_7x7_fast_I25_un1_Y : AO1B - port map(A => N140, B => N139, C => - ADD_7x7_fast_I25_un1_Y_0, Y => I25_un1_Y); - - un174_ready_0_0_ADD_5x5_fast_I17_un1_Y_1 : NOR3C - port map(A => I5_un1_Y, B => N_73_i, C => N110, Y => - ADD_5x5_fast_I17_un1_Y_1); - - \ready_gen.un183_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_3[4]\, B => - \data_mem_addr_r_3[4]\, Y => N_11); - - \Waddr_vect_RNISKOB[2]\ : NOR2A - port map(A => \data_mem_addr_w_3[2]\, B => Waddr_vect_c1, Y - => Waddr_vect_c2); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[1]\); - - \ready_gen.un183_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, C => N_6, Y => N_8); - - \Raddr_vect[4]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[4]\); - - un189_ready_0_0_ADD_7x7_fast_I36_Y_0 : AX1C - port map(A => I25_un1_Y, B => ADD_7x7_fast_I26_Y_0, C => - N_75_1_i_0, Y => \un189_ready_i[5]\); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_3[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(3), Y => - un5_sfull_s_4_0); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_3[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_3[2]\, Y => \sEmpty_RNO_5\); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_3[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, C => \data_mem_addr_w_3[2]\, Y - => \DWACT_FINC_E[0]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ0 is - - port( ready_i_0 : out std_logic_vector(0 to 0); - data_mem_wen_i_0 : out std_logic_vector(0 to 0); - data_mem_ren_i_0 : out std_logic_vector(0 to 0); - data_ren : in std_logic_vector(0 to 0); - data_wen : in std_logic_vector(0 to 0); - data_mem_addr_r_0 : out std_logic_vector(4 downto 0); - data_mem_addr_w_0 : out std_logic_vector(4 downto 0); - rstn : in std_logic; - lclk_c : in std_logic; - N_162 : out std_logic; - N_157 : in std_logic; - N_158 : out std_logic; - sEmpty_RNI6M6A4J : out std_logic; - N_89 : in std_logic; - sEmpty_RNI6M6A4J_0 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ0; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ0 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, N_4, \DWACT_FINC_E[0]\, N_12_0, N_4_0, - \DWACT_FINC_E_0[0]\, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \data_mem_addr_w_0[3]\, - \un10_raddr_vect_s[3]\, sEmpty_RNO_6_0, - \data_mem_addr_w_0[1]\, \Raddr_vect_RNIMK1F1[4]_net_1\, - sEmpty_RNO_5_0, \data_mem_addr_w_0[0]\, - \Raddr_vect_RNIOHA81[0]_net_1\, un5_sfull_s_4_3, - sFull_RNO_4_3, sFull_RNO_5_0, un5_sfull_s_4_0, - \data_mem_addr_r_0[0]\, \un8_waddr_vect_s[0]\, - ADD_5x5_fast_I17_un1_Y_1, N130, ADD_5x5_fast_I13_Y_0, - ADD_5x5_fast_I17_un1_Y_0, ADD_5x5_fast_I5_un1_Y_0, - \data_mem_addr_r_0[3]\, ADD_5x5_fast_I11_Y_0, N_89_i, - N_73, N80, ADD_7x7_fast_I19_Y_i_o4_1_0, N_72, N91, N94, - N88, ADD_5x5_fast_I9_un1_Y_0, \data_mem_addr_w_0[2]\, - \data_mem_addr_r_0[2]\, un2_raddr_vect_slto3_0, - un1_waddr_vect_slt4, Waddr_vect_c1, N_11, - \data_mem_addr_r_0[1]\, I11_un1_Y, N81, N77, N98, - un5_sfull_s_4, \sFull_RNO_1\, \sFull_RNO_2\, - Waddr_vect_n4, Waddr_vect_14_0, Waddr_vect_c2, - Waddr_vect_n2, un1_waddr_vect_s, sFull_RNO_10, \sFull\, - un2_raddr_vect_s, I_5_25, \un10_raddr_vect_s[2]\, I_9_25, - I_13_29, \un10_raddr_vect_s[4]\, I_20_17, - \data_mem_addr_w_0[4]\, \data_mem_ren_i_0[0]\, N111, - un2_raddr_vect_slto1, \data_mem_wen_i_0[0]\, - Waddr_vect_e0, Waddr_vect_e1, Waddr_vect_n1_i, - Waddr_vect_e2, Waddr_vect_e3, Waddr_vect_n3_i, - Waddr_vect_e4, N_67, N165, N_14_1_i, N_23, N_75_i_0, - \data_mem_addr_r_0[4]\, N87, N83, \sEmpty\, un1_sempty_s, - sEmpty_RNO_10, I_20_16, I_13_28, I_9_24, I_5_24, - \un18_ready1[4]\, \un18_ready0[4]\, un5_readylto4, - un20_ready, un12_ready, N_166, N107, N161, N_165, - \un18_ready1[5]\, N_16_i_i_0, N_164, I12_un1_Y, N102, N_9, - N_13, N_12_1, N_11_0, N_8, N_10, N_9_0, N_7, N_4_1, N_5, - N_6, N_9_1, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - data_mem_wen_i_0(0) <= \data_mem_wen_i_0[0]\; - data_mem_ren_i_0(0) <= \data_mem_ren_i_0[0]\; - data_mem_addr_r_0(4) <= \data_mem_addr_r_0[4]\; - data_mem_addr_r_0(3) <= \data_mem_addr_r_0[3]\; - data_mem_addr_r_0(2) <= \data_mem_addr_r_0[2]\; - data_mem_addr_r_0(1) <= \data_mem_addr_r_0[1]\; - data_mem_addr_r_0(0) <= \data_mem_addr_r_0[0]\; - data_mem_addr_w_0(4) <= \data_mem_addr_w_0[4]\; - data_mem_addr_w_0(3) <= \data_mem_addr_w_0[3]\; - data_mem_addr_w_0(2) <= \data_mem_addr_w_0[2]\; - data_mem_addr_w_0(1) <= \data_mem_addr_w_0[1]\; - data_mem_addr_w_0(0) <= \data_mem_addr_w_0[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, C => \data_mem_addr_w_0[2]\, Y - => N_9_1); - - un3_ready_0_0_ADD_5x5_fast_I12_un1_Y : OR3B - port map(A => N91, B => N94, C => N102, Y => I12_un1_Y); - - \Waddr_vect_RNIEJON[3]\ : OR3A - port map(A => Waddr_vect_c1, B => \data_mem_addr_w_0[2]\, C - => \data_mem_addr_w_0[3]\, Y => un1_waddr_vect_slt4); - - sEmpty_RNIOP682J : NOR2 - port map(A => \sEmpty\, B => data_ren(0), Y => - \data_mem_ren_i_0[0]\); - - \ready_gen.un12_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, Y => N_5); - - \Raddr_vect_RNI970RU[0]\ : MX2 - port map(A => un5_readylto4, B => un20_ready, S => - un12_ready, Y => ready_i_0(0)); - - un18_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_89_i, B => N_73, Y => N98); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR2B - port map(A => N_14_1_i, B => N_75_i_0, Y => N161); - - \Raddr_vect_RNIV7LC_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_0[4]\, B => - \data_mem_addr_w_0[4]\, Y => N_75_i_0); - - \Raddr_vect_RNIHA7T6[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_0[0]\, - Y => N_166); - - \ready_gen.un12_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, C => N_4_1, Y => N_10); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, C => \data_mem_addr_r_0[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, Y => N_12); - - sEmpty_RNO : AO1A - port map(A => data_ren(0), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_10); - - \Raddr_vect_RNII22HM[0]\ : AOI1 - port map(A => N_165, B => N_164, C => N_166, Y => - un20_ready); - - \ready_gen.un12_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_0[4]\, B => - \data_mem_addr_w_0[4]\, Y => N_7); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIMK1F1[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[3]\); - - \Raddr_vect_RNIMK1F1[4]\ : NOR2B - port map(A => I_5_25, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNIMK1F1[4]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_0[2]\, Y => - I_9_25); - - un18_ready_0_0_0_ADD_7x7_fast_I20_Y_i_o2_0 : AO13 - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, C => \data_mem_addr_r_0[1]\, Y - => N_11); - - \ready_gen.un12_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, C => N_7, Y => N_12_1); - - \Raddr_vect_RNIMT632[4]\ : NOR2B - port map(A => I_20_17, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \sEmpty_RNI6M6A4J\ : NOR2A - port map(A => \data_mem_ren_i_0[0]\, B => N_89, Y => - sEmpty_RNI6M6A4J); - - \Raddr_vect_RNI4E9H5[0]\ : MX2C - port map(A => \un18_ready1[4]\, B => \un18_ready0[4]\, S - => \data_mem_addr_r_0[0]\, Y => N_164); - - un18_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO13 - port map(A => N_89_i, B => N_73, C => N80, Y => - ADD_5x5_fast_I11_Y_0); - - \Waddr_vect_RNO[4]\ : MX2B - port map(A => \data_mem_addr_w_0[4]\, B => Waddr_vect_n4, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e4); - - un3_ready_0_0_ADD_5x5_fast_I1_P0N : OR2A - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, Y => N88); - - \Raddr_vect_RNIREJ11[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_0[4]\, Y => - un2_raddr_vect_s); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_10, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[0]\, - C => \data_mem_addr_w_0[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[2]\); - - un3_ready_0_0_ADD_5x5_fast_I9_Y : OA1A - port map(A => ADD_5x5_fast_I9_un1_Y_0, B => - \data_mem_addr_r_0[0]\, C => N87, Y => N102); - - \Raddr_vect_RNIR5ED[1]\ : OR2B - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_r_0[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \data_mem_addr_w_0[1]\, B => Waddr_vect_n1_i, - S => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - un18_ready_1_16_ADD_5x5_fast_I1_G0N : NOR2B - port map(A => N91, B => N_72, Y => N80); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_c1, C - => un1_waddr_vect_s, Y => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, Y => I_5_24); - - un3_ready_0_0_ADD_5x5_fast_I17_un1_Y_1 : OA1 - port map(A => N130, B => ADD_5x5_fast_I13_Y_0, C => - ADD_5x5_fast_I17_un1_Y_0, Y => ADD_5x5_fast_I17_un1_Y_1); - - \Waddr_vect_RNIHEQH[2]\ : NOR2A - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_c1, Y - => Waddr_vect_c2); - - \Raddr_vect_RNILQFS1[4]\ : NOR2B - port map(A => I_13_29, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un18_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_14_1_i, B => N83, C => N_75_i_0, Y => - N_16_i_i_0); - - \ready_gen.un12_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, C => N_5, Y => N_9_0); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[3]\); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_0[1]\, B => - \Raddr_vect_RNIMK1F1[4]_net_1\, C => sEmpty_RNO_5_0, Y - => un7_sempty_s_1); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_0[3]\, Y => - I_13_28); - - \Raddr_vect_RNIV7LC[4]\ : XNOR2 - port map(A => \data_mem_addr_w_0[4]\, B => - \data_mem_addr_r_0[4]\, Y => N_89_i); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(0), - Y => sFull_RNO_10); - - un18_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4 : AO1 - port map(A => ADD_7x7_fast_I19_Y_i_o4_1_0, B => N_11, C => - N80, Y => N165); - - sFull_RNI92H8 : NOR2 - port map(A => \sFull\, B => data_wen(0), Y => - \data_mem_wen_i_0[0]\); - - \Raddr_vect_RNIT7LC[3]\ : XNOR2 - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, Y => N_72); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_24, C => - \data_mem_addr_r_0[2]\, Y => sFull_RNO_4_3); - - un3_ready_0_0_ADD_5x5_fast_I9_un1_Y_0 : NOR2B - port map(A => \data_mem_addr_w_0[0]\, B => N88, Y => - ADD_5x5_fast_I9_un1_Y_0); - - sFull_RNO_6 : XA1B - port map(A => \data_mem_addr_r_0[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(0), Y => - un5_sfull_s_4_0); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_0[0]\, B => - \Raddr_vect_RNIOHA81[0]_net_1\, C => data_wen(0), Y => - un7_sempty_s_0); - - un18_ready_1_16_ADD_5x5_fast_I2_G0N : OR2 - port map(A => N_89_i, B => N_73, Y => N83); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[2]\); - - sFull_RNI1GR81_0 : NOR2 - port map(A => \data_mem_wen_i_0[0]\, B => N_157, Y => N_158); - - \ready_gen.un12_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_0[4]\, B => - \data_mem_addr_r_0[4]\, Y => N_11_0); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[0]\); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_0[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_24, C => - \data_mem_addr_r_0[1]\, Y => sFull_RNO_5_0); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_n2, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e2); - - un3_ready_0_0_ADD_5x5_fast_I13_Y_0 : OR3C - port map(A => N91, B => N94, C => N88, Y => - ADD_5x5_fast_I13_Y_0); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_0[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_6_0, Y => - un7_sempty_s_2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_0[3]\, Y - => Waddr_vect_14_0); - - \Waddr_vect_RNICOMT[4]\ : OR2B - port map(A => un1_waddr_vect_slt4, B => - \data_mem_addr_w_0[4]\, Y => un1_waddr_vect_s); - - sFull_RNO_3 : NOR3C - port map(A => sFull_RNO_4_3, B => sFull_RNO_5_0, C => - un5_sfull_s_4_0, Y => un5_sfull_s_4_3); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - \ready_gen.un12_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_w_0[0]\, Y => N_6); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4 : OR3B - port map(A => N_11, B => ADD_7x7_fast_I19_Y_i_o4_1_0, C => - N_73, Y => N_23); - - un3_ready_0_0_ADD_5x5_fast_I5_un1_Y_0 : NOR2A - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, Y => ADD_5x5_fast_I5_un1_Y_0); - - GND_i : GND - port map(Y => \GND\); - - \Waddr_vect_RNO_1[3]\ : OR2A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_w_0[4]\, Y => N_67); - - un3_ready_0_0_ADD_5x5_fast_I0_P0N : NOR2A - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_w_0[0]\, Y => N130); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIOHA81[0]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[0]\); - - un18_ready_1_16_ADD_5x5_fast_I8_Y : MIN3 - port map(A => N_72, B => N91, C => N77, Y => N111); - - \sEmpty_RNI6M6A4J_0\ : NOR2 - port map(A => \data_mem_ren_i_0[0]\, B => N_89, Y => - sEmpty_RNI6M6A4J_0); - - \Raddr_vect_RNIT7LC_0[3]\ : OR2A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, Y => N_73); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_r_0[0]\, Y => N_12_0); - - un18_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1 - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N88, Y => N77); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_0[2]\, Y => - I_9_24); - - \Raddr_vect_RNIT9H2A[0]\ : MX2C - port map(A => \un18_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_0[0]\, Y => N_165); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_0[3]\, Y => - I_13_29); - - \Raddr_vect_RNIV5ED[3]\ : NOR2 - port map(A => \data_mem_addr_r_0[3]\, B => - \data_mem_addr_r_0[2]\, Y => un2_raddr_vect_slto3_0); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, C => \data_mem_addr_r_0[2]\, Y - => N_9); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_1 : OA1A - port map(A => N165, B => N_89_i, C => N_23, Y => N_14_1_i); - - sFull_RNI1GR81 : NOR2A - port map(A => \data_mem_wen_i_0[0]\, B => N_157, Y => N_162); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(0), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_0[4]\, Y => - I_20_17); - - un3_ready_0_0_ADD_5x5_fast_I17_un1_Y_0 : AO18 - port map(A => ADD_5x5_fast_I5_un1_Y_0, B => - \data_mem_addr_r_0[3]\, C => \data_mem_addr_w_0[3]\, Y - => ADD_5x5_fast_I17_un1_Y_0); - - un18_ready_1_16_ADD_5x5_fast_I1_P0N : OR2 - port map(A => N91, B => N_72, Y => N81); - - sFull_RNO_1 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_16, C => - \data_mem_addr_r_0[4]\, Y => \sFull_RNO_1\); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, Y => I_5_25); - - un18_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXOI5 - port map(A => N_72, B => \data_mem_addr_r_0[2]\, C => - \data_mem_addr_w_0[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - \Waddr_vect_RNO_0[3]\ : AX1C - port map(A => Waddr_vect_c2, B => un1_waddr_vect_s, C => - N_67, Y => Waddr_vect_n3_i); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[4]\); - - un3_ready_0_0_ADD_5x5_fast_I2_P0N : OR2A - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, Y => N91); - - sFull_RNO_7 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_0[0]\, - Y => \un8_waddr_vect_s[0]\); - - un3_ready_0_0_ADD_5x5_fast_I3_P0N : OR2A - port map(A => \data_mem_addr_r_0[3]\, B => - \data_mem_addr_w_0[3]\, Y => N94); - - un18_ready_1_16_ADD_5x5_fast_I10_Y : OR2B - port map(A => N111, B => N_75_i_0, Y => N107); - - \Raddr_vect_RNILNOL1[4]\ : NOR2B - port map(A => I_9_25, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \Waddr_vect_RNIL9SB[0]\ : OR2B - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, Y => Waddr_vect_c1); - - un3_ready_0_0_ADD_5x5_fast_I25_Y_0 : AX1E - port map(A => I12_un1_Y, B => ADD_5x5_fast_I17_un1_Y_1, C - => N_89_i, Y => un5_readylto4); - - un18_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - \Waddr_vect_RNO[3]\ : MX2B - port map(A => \data_mem_addr_w_0[3]\, B => Waddr_vect_n3_i, - S => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e3); - - un18_ready_1_16_ADD_5x5_fast_I15_Y_0 : XNOR3 - port map(A => N_73, B => N_89_i, C => N111, Y => - \un18_ready1[4]\); - - sFull_RNO_0 : NOR3C - port map(A => \sFull_RNO_1\, B => \sFull_RNO_2\, C => - un5_sfull_s_4_3, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_0[4]\, Y => sEmpty_RNO_6_0); - - \ready_gen.un12_ready_0_I_11\ : OA1 - port map(A => N_13, B => N_12_1, C => N_11_0, Y => - un12_ready); - - \ready_gen.un12_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13); - - sFull : DFN1C0 - port map(D => sFull_RNO_10, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \ready_gen.un12_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, Y => N_4_1); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_0[4]\, Y => - I_20_16); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[1]\); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[4]\); - - sFull_RNO_2 : AX1E - port map(A => un1_waddr_vect_s, B => I_13_28, C => - \data_mem_addr_r_0[3]\, Y => \sFull_RNO_2\); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_0[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - un3_ready_0_0_ADD_5x5_fast_I1_G0N : OR2A - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_r_0[1]\, Y => N87); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_0[2]\, Y => sEmpty_RNO_5_0); - - un18_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75_i_0, Y => \un18_ready1[5]\); - - un18_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : XOR3 - port map(A => N_73, B => N_89_i, C => N165, Y => - \un18_ready0[4]\); - - \Waddr_vect_RNO_0[4]\ : AXO1 - port map(A => un1_waddr_vect_slt4, B => - \data_mem_addr_w_0[4]\, C => Waddr_vect_14_0, Y => - Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, C => \data_mem_addr_w_0[2]\, Y - => \DWACT_FINC_E[0]\); - - \ready_gen.un12_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, C => N_6, Y => N_8); - - \Raddr_vect_RNIOHA81[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_0[0]\, - Y => \Raddr_vect_RNIOHA81[0]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ4 is - - port( time_mem_wen_i_0 : out std_logic_vector(0 to 0); - time_mem_ren_i_0 : out std_logic_vector(0 to 0); - time_wen : in std_logic_vector(0 to 0); - time_ren : in std_logic_vector(0 to 0); - Waddr_vect_0 : out std_logic; - time_mem_addr_w_0_3 : out std_logic; - time_mem_addr_w_0_0 : out std_logic; - time_mem_addr_w_0_1 : out std_logic; - time_mem_addr_w_0_4 : out std_logic; - Raddr_vect_0 : out std_logic; - time_mem_addr_r_0_3 : out std_logic; - time_mem_addr_r_0_0 : out std_logic; - time_mem_addr_r_0_1 : out std_logic; - time_mem_addr_r_0_4 : out std_logic; - time_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - un27_time_write : in std_logic; - N_4_0 : out std_logic; - N_4 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ4; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ4 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \Raddr_vect[3]_net_1\, \Raddr_vect[2]_net_1\, - \Waddr_vect[3]_net_1\, \Waddr_vect[2]_net_1\, N_7, N_7_0, - un2_sfull_s_3_0_0, \un8_waddr_vect_s[3]\, - un10_sempty_s_3_0_0, \un10_raddr_vect_s[3]\, - un5_sfull_s_2, un7_sempty_s_2, un5_sfull_s_3, - sFull_RNO_3_1, sFull_RNO_4_1, un5_sfull_s_0, - \un8_waddr_vect_s[0]\, \time_mem_addr_r_0[0]\, - un7_sempty_s_3, sEmpty_RNO_3_1, sEmpty_RNO_4_1, - un7_sempty_s_0, \un10_raddr_vect_s[0]\, - \time_mem_addr_w_0[0]\, un2_raddr_vect_slt3, - \time_mem_addr_r_0[1]\, un1_waddr_vect_slt3, - \time_mem_addr_w_0[1]\, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, Raddr_vect_n2, - \Raddr_vect_RNI2C4V[3]_net_1\, Raddr_vect_n2_tz, - Waddr_vect_n2, \Waddr_vect_RNIMJ0S[3]_net_1\, - Waddr_vect_n2_tz, I_5_17, I_9_17, I_9_16, I_5_16, - Raddr_vect_n1_i, Raddr_vect_e2, Raddr_vect_e1, - \time_mem_ren_i_0[0]\, Raddr_vect_e0, I_13_20, - \sFull_RNO_0\, un8_sfull_s, \sEmpty_RNO_0\, un2_sempty_s, - \sFull\, \sEmpty\, I_13_21, Waddr_vect_e0, - \time_mem_wen_i_0[0]\, Waddr_vect_e2, Waddr_vect_n1_i, - Waddr_vect_e1, N_4_1, N_4_2, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - time_mem_wen_i_0(0) <= \time_mem_wen_i_0[0]\; - time_mem_ren_i_0(0) <= \time_mem_ren_i_0[0]\; - Waddr_vect_0 <= \Waddr_vect[2]_net_1\; - time_mem_addr_w_0_0 <= \time_mem_addr_w_0[0]\; - time_mem_addr_w_0_1 <= \time_mem_addr_w_0[1]\; - Raddr_vect_0 <= \Raddr_vect[2]_net_1\; - time_mem_addr_r_0_0 <= \time_mem_addr_r_0[0]\; - time_mem_addr_r_0_1 <= \time_mem_addr_r_0[1]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_addr_w_0[0]\, C => - \Waddr_vect_RNIMJ0S[3]_net_1\, Y => Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4_1); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_addr_r_0[0]\, C => - \Raddr_vect_RNI2C4V[3]_net_1\, Y => Raddr_vect_n1_i); - - \Waddr_vect_RNINE0L[1]\ : OR3 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_addr_w_0[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_0\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_0[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => \time_mem_wen_i_0[0]\, Q => \Waddr_vect[3]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_17); - - un2_sfull_s_3_0_RNO : OR2B - port map(A => I_13_20, B => \Waddr_vect_RNIMJ0S[3]_net_1\, - Y => \un8_waddr_vect_s[3]\); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_0\, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => - \time_mem_wen_i_0[0]\, C => \time_mem_addr_w_0[0]\, Y => - Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Waddr_vect[2]_net_1\); - - sFull_RNI8268 : OR2 - port map(A => time_wen(0), B => \sFull\, Y => - \time_mem_wen_i_0[0]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_0[1]\, - S => \time_mem_wen_i_0[0]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => - Waddr_vect_n2_tz, Y => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, Y => I_5_16); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => - Raddr_vect_n2_tz, Y => Raddr_vect_n2); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => \time_mem_ren_i_0[0]\, Q => \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(0), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4_1, B => \Waddr_vect[3]_net_1\, Y => - I_13_20); - - un2_sfull_s_3_0 : XOR2 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, Y => un2_sfull_s_3_0_0); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO_0\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => - \time_mem_ren_i_0[0]\, C => \time_mem_addr_r_0[0]\, Y => - Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_0[1]\, - S => \time_mem_ren_i_0[0]\, Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => I_5_16, C - => \time_mem_addr_r_0[1]\, Y => sFull_RNO_4_1); - - \Raddr_vect_RNI09BN[1]\ : OR3 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - sFull_RNO_6 : OR2A - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => - \time_mem_addr_w_0[0]\, Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => I_9_17, C - => \Waddr_vect[2]_net_1\, Y => sEmpty_RNO_3_1); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Raddr_vect[2]_net_1\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_0[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_0[0]\, C => time_wen(0), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[0]\, Y => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => I_5_17, C - => \time_mem_addr_w_0[1]\, Y => sEmpty_RNO_4_1); - - un10_sempty_s_3_0 : XOR2 - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, Y => un10_sempty_s_3_0_0); - - sFull_RNO_3 : AX1E - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => I_9_16, C - => \Raddr_vect[2]_net_1\, Y => sFull_RNO_3_1); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_1, B => sEmpty_RNO_4_1, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un25_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_0_4); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - un25_mem_addr_ren_I_12 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => N_4); - - GND_i : GND - port map(Y => \GND\); - - \Waddr_vect_RNIMJ0S[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => \Waddr_vect_RNIMJ0S[3]_net_1\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[0]\, Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_0[0]\); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_addr_r_0[0]\, Y => N_7); - - un10_sempty_s_3_0_RNO : OR2B - port map(A => I_13_21, B => \Raddr_vect_RNI2C4V[3]_net_1\, - Y => \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => - I_9_16); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_2, B => \Raddr_vect[3]_net_1\, Y => - I_13_21); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_2); - - sEmpty_RNIV1VJ : OR3A - port map(A => time_ren_1z, B => un27_time_write, C => - \sEmpty\, Y => \time_mem_ren_i_0[0]\); - - sEmpty_RNO_1 : NOR2A - port map(A => un10_sempty_s_3_0_0, B => time_ren(0), Y => - un7_sempty_s_2); - - sFull_RNO_1 : AND2 - port map(A => time_ren(0), B => un2_sfull_s_3_0_0, Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, Y => I_5_17); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - un29_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_0_4); - - un25_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_0_3); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => sFull_RNO_3_1, B => sFull_RNO_4_1, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2A - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => - \time_mem_addr_r_0[0]\, Y => \un10_raddr_vect_s[0]\); - - un29_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_0_3); - - sFull : DFN1C0 - port map(D => \sFull_RNO_0\, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_0[1]\); - - un29_mem_addr_wen_I_12 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => N_4_0); - - sFull_RNO_2 : OA1A - port map(A => time_ren_1z, B => un27_time_write, C => - \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_0[0]\, C => time_wen(0), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - \Raddr_vect_RNI2C4V[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => \Raddr_vect_RNI2C4V[3]_net_1\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ6 is - - port( time_mem_wen_i_0_1 : in std_logic; - time_mem_wen_i_0_0 : in std_logic; - time_mem_ren_i_0_1 : in std_logic; - time_mem_ren_i_0_0 : in std_logic; - time_wen : in std_logic_vector(2 to 2); - time_ren : in std_logic_vector(2 to 2); - Waddr_vect_0 : out std_logic; - time_mem_addr_w_2_3 : out std_logic; - time_mem_addr_w_2_0 : out std_logic; - time_mem_addr_w_2_1 : out std_logic; - time_mem_addr_w_2_4 : out std_logic; - Raddr_vect_0 : out std_logic; - time_mem_addr_r_2_3 : out std_logic; - time_mem_addr_r_2_0 : out std_logic; - time_mem_addr_r_2_1 : out std_logic; - time_mem_addr_r_2_4 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - N_161 : out std_logic; - N_156 : out std_logic; - N_93 : out std_logic; - N_88 : out std_logic; - N_4_0 : out std_logic; - N_4 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ6; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ6 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \Raddr_vect[3]_net_1\, \Raddr_vect[2]_net_1\, - \Waddr_vect[3]_net_1\, \Waddr_vect[2]_net_1\, N_7, N_7_0, - un5_sfull_s_3, sFull_RNO_3_0, sFull_RNO_4_0, - un5_sfull_s_0, un5_sfull_s_2, \un8_waddr_vect_s[3]\, - \un8_waddr_vect_s[0]\, \time_mem_addr_r_2[0]\, - un7_sempty_s_3, \sEmpty_RNO_3\, \sEmpty_RNO_4\, - un7_sempty_s_0, un7_sempty_s_2, \un10_raddr_vect_s[3]\, - \un10_raddr_vect_s[0]\, \time_mem_addr_w_2[0]\, - un1_waddr_vect_slt3, \time_mem_addr_w_2[1]\, - un2_raddr_vect_slt3, \time_mem_addr_r_2[1]\, - Raddr_vect_n3, Raddr_vect_7_0, Waddr_vect_n3, - Waddr_vect_15_0, Raddr_vect_n2, un2_raddr_vect_s, - Raddr_vect_n2_tz, Waddr_vect_n2, un1_waddr_vect_s, - Waddr_vect_n2_tz, \time_mem_ren_i_0[2]\, Raddr_vect_n1_i, - Raddr_vect_e2, Raddr_vect_e1, Raddr_vect_e0, I_9_18, - I_5_18, I_13_22, \sFull_RNO_6\, un8_sfull_s, - \sEmpty_RNO_1\, un2_sempty_s, \sFull\, \sEmpty\, - \time_mem_wen_i_0[2]\, Waddr_vect_e0, Waddr_vect_e1, - Waddr_vect_n1_i, Waddr_vect_e2, I_9_19, I_5_19, I_13_23, - N_4_1, N_4_2, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - Waddr_vect_0 <= \Waddr_vect[2]_net_1\; - time_mem_addr_w_2_0 <= \time_mem_addr_w_2[0]\; - time_mem_addr_w_2_1 <= \time_mem_addr_w_2[1]\; - Raddr_vect_0 <= \Raddr_vect[2]_net_1\; - time_mem_addr_r_2_0 <= \time_mem_addr_r_2[0]\; - time_mem_addr_r_2_1 <= \time_mem_addr_r_2[1]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_2[1]\, B => - \time_mem_addr_w_2[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4_1); - - un37_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_2_4); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_addr_r_2[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - \Waddr_vect_RNI98V8[1]\ : OR3 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - \Raddr_vect_RNII2AB[1]\ : OR3 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_2[1]\, B => - \time_mem_addr_w_2[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_1\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_2[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => \time_mem_wen_i_0[2]\, Q => \Waddr_vect[3]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_19); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_1\, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[2]\, - C => \time_mem_addr_w_2[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Waddr_vect[2]_net_1\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_2[1]\, - S => \time_mem_wen_i_0[2]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, Y => I_5_18); - - sFull_RNI49BO_0 : NOR3B - port map(A => time_mem_wen_i_0_0, B => - \time_mem_wen_i_0[2]\, C => time_mem_wen_i_0_1, Y => - N_156); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => \time_mem_ren_i_0[2]\, Q => \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(2), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4_1, B => \Waddr_vect[3]_net_1\, Y => - I_13_22); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO_6\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[2]\, - C => \time_mem_addr_r_2[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_2[1]\, - S => \time_mem_ren_i_0[2]\, Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_18, C => - \time_mem_addr_r_2[1]\, Y => sFull_RNO_4_0); - - sEmpty_RNI60VK1_0 : NOR3B - port map(A => time_mem_ren_i_0_0, B => - \time_mem_ren_i_0[2]\, C => time_mem_ren_i_0_1, Y => N_88); - - sFull_RNO_6 : OR2B - port map(A => I_13_22, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_19, C => - \Waddr_vect[2]_net_1\, Y => \sEmpty_RNO_3\); - - sEmpty_RNI5UAF : OR2 - port map(A => time_ren(2), B => \sEmpty\, Y => - \time_mem_ren_i_0[2]\); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Raddr_vect[2]_net_1\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_2[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_2[0]\, C => time_wen(2), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[2]\, Y => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_19, C => - \time_mem_addr_w_2[1]\, Y => \sEmpty_RNO_4\); - - un43_mem_addr_wen_I_12 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => N_4_0); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_18, C => - \Raddr_vect[2]_net_1\, Y => sFull_RNO_3_0); - - sEmpty_RNO_0 : NOR3C - port map(A => \sEmpty_RNO_3\, B => \sEmpty_RNO_4\, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - sEmpty_RNI60VK1 : OR3A - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => \time_mem_ren_i_0[2]\, Y => N_93); - - un43_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_2_4); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - sEmpty_RNO_7 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_2[0]\, - Y => \un10_raddr_vect_s[0]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[2]\, Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_2[0]\); - - sFull_RNI49BO : OR3A - port map(A => time_mem_wen_i_0_0, B => time_mem_wen_i_0_1, - C => \time_mem_wen_i_0[2]\, Y => N_161); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_addr_r_2[0]\, Y => N_7); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => - I_9_18); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_2, B => \Raddr_vect[3]_net_1\, Y => - I_13_23); - - \Raddr_vect_RNIQO2F[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_2); - - sEmpty_RNO_1 : XA1B - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, C => time_ren(2), Y => - un7_sempty_s_2); - - sFull_RNIGE18 : OR2 - port map(A => time_wen(2), B => \sFull\, Y => - \time_mem_wen_i_0[2]\); - - sFull_RNO_1 : XA1 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, C => time_ren(2), Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, Y => I_5_19); - - un43_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_2_3); - - un37_mem_addr_ren_I_12 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => N_4); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - sFull_RNO_7 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_2[0]\, - Y => \un8_waddr_vect_s[0]\); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - \Waddr_vect_RNIE0VB[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => sFull_RNO_3_0, B => sFull_RNO_4_0, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2B - port map(A => I_13_23, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un37_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_2_3); - - sFull : DFN1C0 - port map(D => \sFull_RNO_6\, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_2[1]\); - - sFull_RNO_2 : NOR2B - port map(A => time_ren(2), B => \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_2[0]\, C => time_wen(2), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo is - - port( ready_i_0_i_0 : out std_logic_vector(1 to 1); - data_wen : in std_logic_vector(3 downto 0); - data_ren : in std_logic_vector(3 downto 0); - ready_i_0_2 : out std_logic; - ready_i_0_0 : out std_logic; - ready_i_0_3 : out std_logic; - time_ren : in std_logic_vector(3 downto 0); - time_wen : in std_logic_vector(3 downto 0); - hwdata : out std_logic_vector(31 downto 0); - wdata : in std_logic_vector(31 downto 0); - time_ren_1z : in std_logic; - data_ren_1z : in std_logic; - un13_time_write : in std_logic; - un20_time_write : in std_logic; - un27_time_write : in std_logic; - un5_time_write : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_waveform_fifo; - -architecture DEF_ARCH of lpp_waveform_fifo is - - component lpp_waveform_fifo_ctrlZ1 - port( ready_i_0_i_0 : out std_logic_vector(1 to 1); - data_mem_wen_i_0 : out std_logic_vector(1 to 1); - data_ren : in std_logic_vector(1 to 1) := (others => 'U'); - data_mem_ren_i_0 : out std_logic_vector(1 to 1); - data_wen : in std_logic_vector(1 to 1) := (others => 'U'); - data_mem_addr_r_1 : out std_logic_vector(4 downto 0); - data_mem_addr_w_1 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_158 : in std_logic := 'U'; - sFull_RNIE8AH1 : out std_logic; - sEmpty_RNI6M6A4J_0 : in std_logic := 'U'; - sEmpty_RNIU5CB661 : out std_logic; - un20_time_write : in std_logic := 'U' - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ7 - port( time_mem_wen_i_0 : out std_logic_vector(3 to 3); - time_mem_ren_i_0 : out std_logic_vector(3 to 3); - time_mem_addr_w_3_i_0_3 : out std_logic; - time_mem_addr_w_3_i_0_0 : out std_logic; - time_mem_addr_r_3_i_0_3 : out std_logic; - time_mem_addr_r_3_i_0_0 : out std_logic; - time_wen : in std_logic_vector(3 to 3) := (others => 'U'); - time_ren : in std_logic_vector(3 to 3) := (others => 'U'); - time_mem_addr_w_3_3 : out std_logic; - time_mem_addr_w_3_0 : out std_logic; - time_mem_addr_w_3_1 : out std_logic; - time_mem_addr_r_3_3 : out std_logic; - time_mem_addr_r_3_0 : out std_logic; - time_mem_addr_r_3_1 : out std_logic; - time_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_156 : in std_logic := 'U'; - N_157 : out std_logic; - sFull_RNIODA01_0 : out std_logic; - N_117 : out std_logic; - un5_time_write : in std_logic := 'U'; - N_89 : out std_logic; - N_88 : in std_logic := 'U'; - N_37 : out std_logic - ); - end component; - - component syncram_2pZ2 - port( wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - Waddr_vect_1 : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_0 : in std_logic_vector(2 to 2) := (others => 'U'); - time_mem_addr_w_1_0 : in std_logic := 'U'; - time_mem_addr_w_1_1 : in std_logic := 'U'; - time_mem_addr_w_1_3 : in std_logic := 'U'; - time_mem_addr_w_3_0 : in std_logic := 'U'; - time_mem_addr_w_3_1 : in std_logic := 'U'; - time_mem_addr_w_3_3 : in std_logic := 'U'; - DWACT_FINC_E_0 : in std_logic_vector(0 to 0) := (others => 'U'); - data_mem_addr_w_3 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_mem_addr_w_1 : in std_logic_vector(4 downto 0) := (others => 'U'); - time_mem_addr_r_3_3 : in std_logic := 'U'; - time_mem_addr_r_3_0 : in std_logic := 'U'; - time_mem_addr_r_3_1 : in std_logic := 'U'; - Raddr_vect_1 : in std_logic_vector(2 to 2) := (others => 'U'); - Raddr_vect_0 : in std_logic_vector(2 to 2) := (others => 'U'); - time_mem_addr_r_1_1 : in std_logic := 'U'; - time_mem_addr_r_1_0 : in std_logic := 'U'; - time_mem_addr_r_1_3 : in std_logic := 'U'; - data_mem_addr_r_3 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_mem_addr_r_1 : in std_logic_vector(4 downto 0) := (others => 'U'); - DWACT_FINC_E : in std_logic_vector(0 to 0) := (others => 'U'); - Raddr_vect : in std_logic_vector(2 to 2) := (others => 'U'); - time_mem_addr_r_2_0 : in std_logic := 'U'; - time_mem_addr_r_2_1 : in std_logic := 'U'; - time_mem_addr_r_2_3 : in std_logic := 'U'; - time_mem_addr_r_2_4 : in std_logic := 'U'; - data_mem_ren_i_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - time_mem_addr_r_3_i_0_0 : in std_logic := 'U'; - time_mem_addr_r_3_i_0_3 : in std_logic := 'U'; - time_mem_addr_w_3_i_0_0 : in std_logic := 'U'; - time_mem_addr_w_3_i_0_3 : in std_logic := 'U'; - data_mem_wen_i_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - Waddr_vect : in std_logic_vector(2 to 2) := (others => 'U'); - data_mem_addr_w_0 : in std_logic_vector(4 downto 0) := (others => 'U'); - time_mem_wen_i_0_1 : in std_logic := 'U'; - time_mem_wen_i_0_3 : in std_logic := 'U'; - time_mem_wen_i_0_0 : in std_logic := 'U'; - time_mem_addr_w_0_1 : in std_logic := 'U'; - time_mem_addr_w_0_3 : in std_logic := 'U'; - time_mem_addr_w_0_4 : in std_logic := 'U'; - time_mem_addr_w_0_0 : in std_logic := 'U'; - time_mem_addr_w_2_4 : in std_logic := 'U'; - time_mem_addr_w_2_3 : in std_logic := 'U'; - time_mem_addr_w_2_1 : in std_logic := 'U'; - time_mem_addr_w_2_0 : in std_logic := 'U'; - data_mem_addr_w_2 : in std_logic_vector(4 downto 0) := (others => 'U'); - time_mem_ren_i_0_3 : in std_logic := 'U'; - time_mem_ren_i_0_1 : in std_logic := 'U'; - time_mem_ren_i_0_0 : in std_logic := 'U'; - time_mem_addr_r_0_4 : in std_logic := 'U'; - time_mem_addr_r_0_3 : in std_logic := 'U'; - time_mem_addr_r_0_0 : in std_logic := 'U'; - time_mem_addr_r_0_1 : in std_logic := 'U'; - data_mem_addr_r_0 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_mem_addr_r_2 : in std_logic_vector(4 downto 0) := (others => 'U'); - N_64_i_0 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sFull_RNIODA01_0 : in std_logic := 'U'; - sFull_RNIKQ9G : in std_logic := 'U'; - sFull_RNIE8AH1 : in std_logic := 'U'; - N_158 : in std_logic := 'U'; - N_4_0 : in std_logic := 'U'; - N_88 : in std_logic := 'U'; - sEmpty_RNIU5CB661 : in std_logic := 'U'; - sEmpty_RNI6M6A4J_0 : in std_logic := 'U'; - N_4 : in std_logic := 'U'; - N_115 : in std_logic := 'U'; - N_117 : in std_logic := 'U'; - N_93 : in std_logic := 'U'; - N_35 : in std_logic := 'U'; - N_37 : in std_logic := 'U'; - N_157 : in std_logic := 'U'; - N_162 : in std_logic := 'U'; - N_161 : in std_logic := 'U'; - N_165 : in std_logic := 'U'; - sEmpty_RNI6M6A4J : in std_logic := 'U'; - sEmpty_RNIPJ7A8P1 : in std_logic := 'U' - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ2 - port( ready_i_0 : out std_logic_vector(2 to 2); - data_mem_wen_i_0 : out std_logic_vector(2 to 2); - data_ren : in std_logic_vector(2 to 2) := (others => 'U'); - data_mem_ren_i_0 : out std_logic_vector(2 to 2); - data_wen : in std_logic_vector(2 to 2) := (others => 'U'); - data_mem_addr_r_2 : out std_logic_vector(4 downto 0); - data_mem_addr_w_2 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sFull_RNIE8AH1 : in std_logic := 'U'; - N_165 : out std_logic; - sEmpty_RNIU5CB661 : in std_logic := 'U'; - sEmpty_RNIPJ7A8P1 : out std_logic; - un13_time_write : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_ctrlZ5 - port( time_mem_wen_i_0 : inout std_logic_vector(1 downto 0); - time_mem_ren_i_0 : inout std_logic_vector(1 downto 0); - time_wen : in std_logic_vector(1 to 1) := (others => 'U'); - time_ren : in std_logic_vector(1 to 1) := (others => 'U'); - time_mem_addr_w_1_3 : out std_logic; - time_mem_addr_w_1_0 : out std_logic; - time_mem_addr_w_1_1 : out std_logic; - time_mem_addr_r_1_3 : out std_logic; - time_mem_addr_r_1_0 : out std_logic; - time_mem_addr_r_1_1 : out std_logic; - DWACT_FINC_E_0 : out std_logic_vector(0 to 0); - Waddr_vect_0 : out std_logic; - DWACT_FINC_E : out std_logic_vector(0 to 0); - Raddr_vect_0 : out std_logic; - time_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - un20_time_write : in std_logic := 'U'; - sFull_RNIKQ9G : out std_logic; - N_115 : out std_logic; - N_35 : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ3 - port( ready_i_0 : out std_logic_vector(3 to 3); - data_mem_wen_i_0 : out std_logic_vector(3 to 3); - data_ren : in std_logic_vector(3 to 3) := (others => 'U'); - data_mem_ren_i_0 : out std_logic_vector(3 to 3); - data_wen : in std_logic_vector(3 to 3) := (others => 'U'); - data_mem_addr_r_3 : out std_logic_vector(4 downto 0); - data_mem_addr_w_3 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - un5_time_write : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_ctrlZ0 - port( ready_i_0 : out std_logic_vector(0 to 0); - data_mem_wen_i_0 : out std_logic_vector(0 to 0); - data_mem_ren_i_0 : out std_logic_vector(0 to 0); - data_ren : in std_logic_vector(0 to 0) := (others => 'U'); - data_wen : in std_logic_vector(0 to 0) := (others => 'U'); - data_mem_addr_r_0 : out std_logic_vector(4 downto 0); - data_mem_addr_w_0 : out std_logic_vector(4 downto 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_162 : out std_logic; - N_157 : in std_logic := 'U'; - N_158 : out std_logic; - sEmpty_RNI6M6A4J : out std_logic; - N_89 : in std_logic := 'U'; - sEmpty_RNI6M6A4J_0 : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ4 - port( time_mem_wen_i_0 : out std_logic_vector(0 to 0); - time_mem_ren_i_0 : out std_logic_vector(0 to 0); - time_wen : in std_logic_vector(0 to 0) := (others => 'U'); - time_ren : in std_logic_vector(0 to 0) := (others => 'U'); - Waddr_vect_0 : out std_logic; - time_mem_addr_w_0_3 : out std_logic; - time_mem_addr_w_0_0 : out std_logic; - time_mem_addr_w_0_1 : out std_logic; - time_mem_addr_w_0_4 : out std_logic; - Raddr_vect_0 : out std_logic; - time_mem_addr_r_0_3 : out std_logic; - time_mem_addr_r_0_0 : out std_logic; - time_mem_addr_r_0_1 : out std_logic; - time_mem_addr_r_0_4 : out std_logic; - time_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - un27_time_write : in std_logic := 'U'; - N_4_0 : out std_logic; - N_4 : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ6 - port( time_mem_wen_i_0_1 : in std_logic := 'U'; - time_mem_wen_i_0_0 : in std_logic := 'U'; - time_mem_ren_i_0_1 : in std_logic := 'U'; - time_mem_ren_i_0_0 : in std_logic := 'U'; - time_wen : in std_logic_vector(2 to 2) := (others => 'U'); - time_ren : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_0 : out std_logic; - time_mem_addr_w_2_3 : out std_logic; - time_mem_addr_w_2_0 : out std_logic; - time_mem_addr_w_2_1 : out std_logic; - time_mem_addr_w_2_4 : out std_logic; - Raddr_vect_0 : out std_logic; - time_mem_addr_r_2_3 : out std_logic; - time_mem_addr_r_2_0 : out std_logic; - time_mem_addr_r_2_1 : out std_logic; - time_mem_addr_r_2_4 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_161 : out std_logic; - N_156 : out std_logic; - N_93 : out std_logic; - N_88 : out std_logic; - N_4_0 : out std_logic; - N_4 : out std_logic - ); - end component; - - signal N_64_i_0, \data_addr_r_0_iv_i_2[5]\, - \data_addr_r_0_iv_i_3[5]\, \data_addr_r_0_iv_i_1[5]\, - \data_addr_r_0_iv_i_0[5]\, - \data_addr_r_0_iv_i_RNO_2[5]_net_1\, sEmpty_RNI6M6A4J, - N_93, N_4, N_37, N_4_0, \time_mem_ren_i_0[0]\, N_35, - \data_mem_ren_i_0[2]\, \data_mem_ren_i_0[1]\, N_89, - \Waddr_vect[2]\, \Waddr_vect_0[2]\, - \time_mem_addr_w_1[0]\, \time_mem_addr_w_1[1]\, - \time_mem_addr_w_1[3]\, \time_mem_addr_w_3[0]\, - \time_mem_addr_w_3[1]\, \time_mem_addr_w_3[3]\, - \DWACT_FINC_E[0]\, \data_mem_addr_w_3[0]\, - \data_mem_addr_w_3[1]\, \data_mem_addr_w_3[2]\, - \data_mem_addr_w_3[3]\, \data_mem_addr_w_3[4]\, - \data_mem_addr_w_1[0]\, \data_mem_addr_w_1[1]\, - \data_mem_addr_w_1[2]\, \data_mem_addr_w_1[3]\, - \data_mem_addr_w_1[4]\, \time_mem_addr_r_3[3]\, - \time_mem_addr_r_3[0]\, \time_mem_addr_r_3[1]\, - \Raddr_vect[2]\, \Raddr_vect_0[2]\, - \time_mem_addr_r_1[1]\, \time_mem_addr_r_1[0]\, - \time_mem_addr_r_1[3]\, \data_mem_addr_r_3[0]\, - \data_mem_addr_r_3[1]\, \data_mem_addr_r_3[2]\, - \data_mem_addr_r_3[3]\, \data_mem_addr_r_3[4]\, - \data_mem_addr_r_1[0]\, \data_mem_addr_r_1[1]\, - \data_mem_addr_r_1[2]\, \data_mem_addr_r_1[3]\, - \data_mem_addr_r_1[4]\, \DWACT_FINC_E_0[0]\, - \Raddr_vect_1[2]\, \time_mem_addr_r_2[0]\, - \time_mem_addr_r_2[1]\, \time_mem_addr_r_2[3]\, - \time_mem_addr_r_2[4]\, \data_mem_ren_i_0[0]\, - \data_mem_ren_i_0[3]\, \time_mem_addr_r_3_i_0[2]\, - \time_mem_addr_r_3_i_0[5]\, \time_mem_addr_w_3_i_0[2]\, - \time_mem_addr_w_3_i_0[5]\, \data_mem_wen_i_0[0]\, - \data_mem_wen_i_0[1]\, \data_mem_wen_i_0[2]\, - \data_mem_wen_i_0[3]\, \Waddr_vect_1[2]\, - \data_mem_addr_w_0[0]\, \data_mem_addr_w_0[1]\, - \data_mem_addr_w_0[2]\, \data_mem_addr_w_0[3]\, - \data_mem_addr_w_0[4]\, \time_mem_wen_i_0[1]\, - \time_mem_wen_i_0[3]\, \time_mem_wen_i_0[0]\, - \time_mem_addr_w_0[1]\, \time_mem_addr_w_0[3]\, - \time_mem_addr_w_0[4]\, \time_mem_addr_w_0[0]\, - \time_mem_addr_w_2[4]\, \time_mem_addr_w_2[3]\, - \time_mem_addr_w_2[1]\, \time_mem_addr_w_2[0]\, - \data_mem_addr_w_2[0]\, \data_mem_addr_w_2[1]\, - \data_mem_addr_w_2[2]\, \data_mem_addr_w_2[3]\, - \data_mem_addr_w_2[4]\, \time_mem_ren_i_0[3]\, - \time_mem_ren_i_0[1]\, \time_mem_addr_r_0[4]\, - \time_mem_addr_r_0[3]\, \time_mem_addr_r_0[0]\, - \time_mem_addr_r_0[1]\, \data_mem_addr_r_0[0]\, - \data_mem_addr_r_0[1]\, \data_mem_addr_r_0[2]\, - \data_mem_addr_r_0[3]\, \data_mem_addr_r_0[4]\, - \data_mem_addr_r_2[0]\, \data_mem_addr_r_2[1]\, - \data_mem_addr_r_2[2]\, \data_mem_addr_r_2[3]\, - \data_mem_addr_r_2[4]\, sFull_RNIODA01_0, sFull_RNIKQ9G, - sFull_RNIE8AH1, N_158, N_4_1, N_88, sEmpty_RNIU5CB661, - sEmpty_RNI6M6A4J_0, N_4_2, N_115, N_117, N_157, N_162, - N_161, N_165, sEmpty_RNIPJ7A8P1, N_156, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : lpp_waveform_fifo_ctrlZ1 - Use entity work.lpp_waveform_fifo_ctrlZ1(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ7 - Use entity work.lpp_waveform_fifo_ctrlZ7(DEF_ARCH); - for all : syncram_2pZ2 - Use entity work.syncram_2pZ2(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ2 - Use entity work.lpp_waveform_fifo_ctrlZ2(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ5 - Use entity work.lpp_waveform_fifo_ctrlZ5(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ3 - Use entity work.lpp_waveform_fifo_ctrlZ3(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ0 - Use entity work.lpp_waveform_fifo_ctrlZ0(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ4 - Use entity work.lpp_waveform_fifo_ctrlZ4(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ6 - Use entity work.lpp_waveform_fifo_ctrlZ6(DEF_ARCH); -begin - - - \gen_fifo_ctrl_data.1.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ1 - port map(ready_i_0_i_0(1) => ready_i_0_i_0(1), - data_mem_wen_i_0(1) => \data_mem_wen_i_0[1]\, data_ren(1) - => data_ren(1), data_mem_ren_i_0(1) => - \data_mem_ren_i_0[1]\, data_wen(1) => data_wen(1), - data_mem_addr_r_1(4) => \data_mem_addr_r_1[4]\, - data_mem_addr_r_1(3) => \data_mem_addr_r_1[3]\, - data_mem_addr_r_1(2) => \data_mem_addr_r_1[2]\, - data_mem_addr_r_1(1) => \data_mem_addr_r_1[1]\, - data_mem_addr_r_1(0) => \data_mem_addr_r_1[0]\, - data_mem_addr_w_1(4) => \data_mem_addr_w_1[4]\, - data_mem_addr_w_1(3) => \data_mem_addr_w_1[3]\, - data_mem_addr_w_1(2) => \data_mem_addr_w_1[2]\, - data_mem_addr_w_1(1) => \data_mem_addr_w_1[1]\, - data_mem_addr_w_1(0) => \data_mem_addr_w_1[0]\, - data_ren_1z => data_ren_1z, rstn => rstn, lclk_c => - lclk_c, N_158 => N_158, sFull_RNIE8AH1 => sFull_RNIE8AH1, - sEmpty_RNI6M6A4J_0 => sEmpty_RNI6M6A4J_0, - sEmpty_RNIU5CB661 => sEmpty_RNIU5CB661, un20_time_write - => un20_time_write); - - \data_addr_r_0_iv_i_RNO_1[5]\ : OA1B - port map(A => N_93, B => N_4, C => N_37, Y => - \data_addr_r_0_iv_i_1[5]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \gen_fifo_ctrl_time.3.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ7 - port map(time_mem_wen_i_0(3) => \time_mem_wen_i_0[3]\, - time_mem_ren_i_0(3) => \time_mem_ren_i_0[3]\, - time_mem_addr_w_3_i_0_3 => \time_mem_addr_w_3_i_0[5]\, - time_mem_addr_w_3_i_0_0 => \time_mem_addr_w_3_i_0[2]\, - time_mem_addr_r_3_i_0_3 => \time_mem_addr_r_3_i_0[5]\, - time_mem_addr_r_3_i_0_0 => \time_mem_addr_r_3_i_0[2]\, - time_wen(3) => time_wen(3), time_ren(3) => time_ren(3), - time_mem_addr_w_3_3 => \time_mem_addr_w_3[3]\, - time_mem_addr_w_3_0 => \time_mem_addr_w_3[0]\, - time_mem_addr_w_3_1 => \time_mem_addr_w_3[1]\, - time_mem_addr_r_3_3 => \time_mem_addr_r_3[3]\, - time_mem_addr_r_3_0 => \time_mem_addr_r_3[0]\, - time_mem_addr_r_3_1 => \time_mem_addr_r_3[1]\, - time_ren_1z => time_ren_1z, rstn => rstn, lclk_c => - lclk_c, N_156 => N_156, N_157 => N_157, sFull_RNIODA01_0 - => sFull_RNIODA01_0, N_117 => N_117, un5_time_write => - un5_time_write, N_89 => N_89, N_88 => N_88, N_37 => N_37); - - SRAM : syncram_2pZ2 - port map(wdata(31) => wdata(31), wdata(30) => wdata(30), - wdata(29) => wdata(29), wdata(28) => wdata(28), wdata(27) - => wdata(27), wdata(26) => wdata(26), wdata(25) => - wdata(25), wdata(24) => wdata(24), wdata(23) => wdata(23), - wdata(22) => wdata(22), wdata(21) => wdata(21), wdata(20) - => wdata(20), wdata(19) => wdata(19), wdata(18) => - wdata(18), wdata(17) => wdata(17), wdata(16) => wdata(16), - wdata(15) => wdata(15), wdata(14) => wdata(14), wdata(13) - => wdata(13), wdata(12) => wdata(12), wdata(11) => - wdata(11), wdata(10) => wdata(10), wdata(9) => wdata(9), - wdata(8) => wdata(8), wdata(7) => wdata(7), wdata(6) => - wdata(6), wdata(5) => wdata(5), wdata(4) => wdata(4), - wdata(3) => wdata(3), wdata(2) => wdata(2), wdata(1) => - wdata(1), wdata(0) => wdata(0), hwdata(31) => hwdata(31), - hwdata(30) => hwdata(30), hwdata(29) => hwdata(29), - hwdata(28) => hwdata(28), hwdata(27) => hwdata(27), - hwdata(26) => hwdata(26), hwdata(25) => hwdata(25), - hwdata(24) => hwdata(24), hwdata(23) => hwdata(23), - hwdata(22) => hwdata(22), hwdata(21) => hwdata(21), - hwdata(20) => hwdata(20), hwdata(19) => hwdata(19), - hwdata(18) => hwdata(18), hwdata(17) => hwdata(17), - hwdata(16) => hwdata(16), hwdata(15) => hwdata(15), - hwdata(14) => hwdata(14), hwdata(13) => hwdata(13), - hwdata(12) => hwdata(12), hwdata(11) => hwdata(11), - hwdata(10) => hwdata(10), hwdata(9) => hwdata(9), - hwdata(8) => hwdata(8), hwdata(7) => hwdata(7), hwdata(6) - => hwdata(6), hwdata(5) => hwdata(5), hwdata(4) => - hwdata(4), hwdata(3) => hwdata(3), hwdata(2) => hwdata(2), - hwdata(1) => hwdata(1), hwdata(0) => hwdata(0), - Waddr_vect_1(2) => \Waddr_vect[2]\, Waddr_vect_0(2) => - \Waddr_vect_0[2]\, time_mem_addr_w_1_0 => - \time_mem_addr_w_1[0]\, time_mem_addr_w_1_1 => - \time_mem_addr_w_1[1]\, time_mem_addr_w_1_3 => - \time_mem_addr_w_1[3]\, time_mem_addr_w_3_0 => - \time_mem_addr_w_3[0]\, time_mem_addr_w_3_1 => - \time_mem_addr_w_3[1]\, time_mem_addr_w_3_3 => - \time_mem_addr_w_3[3]\, DWACT_FINC_E_0(0) => - \DWACT_FINC_E[0]\, data_mem_addr_w_3(4) => - \data_mem_addr_w_3[4]\, data_mem_addr_w_3(3) => - \data_mem_addr_w_3[3]\, data_mem_addr_w_3(2) => - \data_mem_addr_w_3[2]\, data_mem_addr_w_3(1) => - \data_mem_addr_w_3[1]\, data_mem_addr_w_3(0) => - \data_mem_addr_w_3[0]\, data_mem_addr_w_1(4) => - \data_mem_addr_w_1[4]\, data_mem_addr_w_1(3) => - \data_mem_addr_w_1[3]\, data_mem_addr_w_1(2) => - \data_mem_addr_w_1[2]\, data_mem_addr_w_1(1) => - \data_mem_addr_w_1[1]\, data_mem_addr_w_1(0) => - \data_mem_addr_w_1[0]\, time_mem_addr_r_3_3 => - \time_mem_addr_r_3[3]\, time_mem_addr_r_3_0 => - \time_mem_addr_r_3[0]\, time_mem_addr_r_3_1 => - \time_mem_addr_r_3[1]\, Raddr_vect_1(2) => - \Raddr_vect[2]\, Raddr_vect_0(2) => \Raddr_vect_0[2]\, - time_mem_addr_r_1_1 => \time_mem_addr_r_1[1]\, - time_mem_addr_r_1_0 => \time_mem_addr_r_1[0]\, - time_mem_addr_r_1_3 => \time_mem_addr_r_1[3]\, - data_mem_addr_r_3(4) => \data_mem_addr_r_3[4]\, - data_mem_addr_r_3(3) => \data_mem_addr_r_3[3]\, - data_mem_addr_r_3(2) => \data_mem_addr_r_3[2]\, - data_mem_addr_r_3(1) => \data_mem_addr_r_3[1]\, - data_mem_addr_r_3(0) => \data_mem_addr_r_3[0]\, - data_mem_addr_r_1(4) => \data_mem_addr_r_1[4]\, - data_mem_addr_r_1(3) => \data_mem_addr_r_1[3]\, - data_mem_addr_r_1(2) => \data_mem_addr_r_1[2]\, - data_mem_addr_r_1(1) => \data_mem_addr_r_1[1]\, - data_mem_addr_r_1(0) => \data_mem_addr_r_1[0]\, - DWACT_FINC_E(0) => \DWACT_FINC_E_0[0]\, Raddr_vect(2) => - \Raddr_vect_1[2]\, time_mem_addr_r_2_0 => - \time_mem_addr_r_2[0]\, time_mem_addr_r_2_1 => - \time_mem_addr_r_2[1]\, time_mem_addr_r_2_3 => - \time_mem_addr_r_2[3]\, time_mem_addr_r_2_4 => - \time_mem_addr_r_2[4]\, data_mem_ren_i_0(3) => - \data_mem_ren_i_0[3]\, data_mem_ren_i_0(2) => - \data_mem_ren_i_0[2]\, data_mem_ren_i_0(1) => - \data_mem_ren_i_0[1]\, data_mem_ren_i_0(0) => - \data_mem_ren_i_0[0]\, time_mem_addr_r_3_i_0_0 => - \time_mem_addr_r_3_i_0[2]\, time_mem_addr_r_3_i_0_3 => - \time_mem_addr_r_3_i_0[5]\, time_mem_addr_w_3_i_0_0 => - \time_mem_addr_w_3_i_0[2]\, time_mem_addr_w_3_i_0_3 => - \time_mem_addr_w_3_i_0[5]\, data_mem_wen_i_0(3) => - \data_mem_wen_i_0[3]\, data_mem_wen_i_0(2) => - \data_mem_wen_i_0[2]\, data_mem_wen_i_0(1) => - \data_mem_wen_i_0[1]\, data_mem_wen_i_0(0) => - \data_mem_wen_i_0[0]\, Waddr_vect(2) => \Waddr_vect_1[2]\, - data_mem_addr_w_0(4) => \data_mem_addr_w_0[4]\, - data_mem_addr_w_0(3) => \data_mem_addr_w_0[3]\, - data_mem_addr_w_0(2) => \data_mem_addr_w_0[2]\, - data_mem_addr_w_0(1) => \data_mem_addr_w_0[1]\, - data_mem_addr_w_0(0) => \data_mem_addr_w_0[0]\, - time_mem_wen_i_0_1 => \time_mem_wen_i_0[1]\, - time_mem_wen_i_0_3 => \time_mem_wen_i_0[3]\, - time_mem_wen_i_0_0 => \time_mem_wen_i_0[0]\, - time_mem_addr_w_0_1 => \time_mem_addr_w_0[1]\, - time_mem_addr_w_0_3 => \time_mem_addr_w_0[3]\, - time_mem_addr_w_0_4 => \time_mem_addr_w_0[4]\, - time_mem_addr_w_0_0 => \time_mem_addr_w_0[0]\, - time_mem_addr_w_2_4 => \time_mem_addr_w_2[4]\, - time_mem_addr_w_2_3 => \time_mem_addr_w_2[3]\, - time_mem_addr_w_2_1 => \time_mem_addr_w_2[1]\, - time_mem_addr_w_2_0 => \time_mem_addr_w_2[0]\, - data_mem_addr_w_2(4) => \data_mem_addr_w_2[4]\, - data_mem_addr_w_2(3) => \data_mem_addr_w_2[3]\, - data_mem_addr_w_2(2) => \data_mem_addr_w_2[2]\, - data_mem_addr_w_2(1) => \data_mem_addr_w_2[1]\, - data_mem_addr_w_2(0) => \data_mem_addr_w_2[0]\, - time_mem_ren_i_0_3 => \time_mem_ren_i_0[3]\, - time_mem_ren_i_0_1 => \time_mem_ren_i_0[1]\, - time_mem_ren_i_0_0 => \time_mem_ren_i_0[0]\, - time_mem_addr_r_0_4 => \time_mem_addr_r_0[4]\, - time_mem_addr_r_0_3 => \time_mem_addr_r_0[3]\, - time_mem_addr_r_0_0 => \time_mem_addr_r_0[0]\, - time_mem_addr_r_0_1 => \time_mem_addr_r_0[1]\, - data_mem_addr_r_0(4) => \data_mem_addr_r_0[4]\, - data_mem_addr_r_0(3) => \data_mem_addr_r_0[3]\, - data_mem_addr_r_0(2) => \data_mem_addr_r_0[2]\, - data_mem_addr_r_0(1) => \data_mem_addr_r_0[1]\, - data_mem_addr_r_0(0) => \data_mem_addr_r_0[0]\, - data_mem_addr_r_2(4) => \data_mem_addr_r_2[4]\, - data_mem_addr_r_2(3) => \data_mem_addr_r_2[3]\, - data_mem_addr_r_2(2) => \data_mem_addr_r_2[2]\, - data_mem_addr_r_2(1) => \data_mem_addr_r_2[1]\, - data_mem_addr_r_2(0) => \data_mem_addr_r_2[0]\, N_64_i_0 - => N_64_i_0, lclk_c => lclk_c, sFull_RNIODA01_0 => - sFull_RNIODA01_0, sFull_RNIKQ9G => sFull_RNIKQ9G, - sFull_RNIE8AH1 => sFull_RNIE8AH1, N_158 => N_158, N_4_0 - => N_4_1, N_88 => N_88, sEmpty_RNIU5CB661 => - sEmpty_RNIU5CB661, sEmpty_RNI6M6A4J_0 => - sEmpty_RNI6M6A4J_0, N_4 => N_4_2, N_115 => N_115, N_117 - => N_117, N_93 => N_93, N_35 => N_35, N_37 => N_37, - N_157 => N_157, N_162 => N_162, N_161 => N_161, N_165 => - N_165, sEmpty_RNI6M6A4J => sEmpty_RNI6M6A4J, - sEmpty_RNIPJ7A8P1 => sEmpty_RNIPJ7A8P1); - - \data_addr_r_0_iv_i_RNO_0[5]\ : AND2 - port map(A => \data_addr_r_0_iv_i_1[5]\, B => - \data_addr_r_0_iv_i_0[5]\, Y => \data_addr_r_0_iv_i_3[5]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_addr_r_0_iv_i_RNO[5]\ : NOR2A - port map(A => \data_addr_r_0_iv_i_RNO_2[5]_net_1\, B => - sEmpty_RNI6M6A4J, Y => \data_addr_r_0_iv_i_2[5]\); - - \gen_fifo_ctrl_data.2.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ2 - port map(ready_i_0(2) => ready_i_0_2, data_mem_wen_i_0(2) - => \data_mem_wen_i_0[2]\, data_ren(2) => data_ren(2), - data_mem_ren_i_0(2) => \data_mem_ren_i_0[2]\, data_wen(2) - => data_wen(2), data_mem_addr_r_2(4) => - \data_mem_addr_r_2[4]\, data_mem_addr_r_2(3) => - \data_mem_addr_r_2[3]\, data_mem_addr_r_2(2) => - \data_mem_addr_r_2[2]\, data_mem_addr_r_2(1) => - \data_mem_addr_r_2[1]\, data_mem_addr_r_2(0) => - \data_mem_addr_r_2[0]\, data_mem_addr_w_2(4) => - \data_mem_addr_w_2[4]\, data_mem_addr_w_2(3) => - \data_mem_addr_w_2[3]\, data_mem_addr_w_2(2) => - \data_mem_addr_w_2[2]\, data_mem_addr_w_2(1) => - \data_mem_addr_w_2[1]\, data_mem_addr_w_2(0) => - \data_mem_addr_w_2[0]\, data_ren_1z => data_ren_1z, rstn - => rstn, lclk_c => lclk_c, sFull_RNIE8AH1 => - sFull_RNIE8AH1, N_165 => N_165, sEmpty_RNIU5CB661 => - sEmpty_RNIU5CB661, sEmpty_RNIPJ7A8P1 => sEmpty_RNIPJ7A8P1, - un13_time_write => un13_time_write); - - GND_i : GND - port map(Y => \GND\); - - \gen_fifo_ctrl_time.1.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ5 - port map(time_mem_wen_i_0(1) => \time_mem_wen_i_0[1]\, - time_mem_wen_i_0(0) => \time_mem_wen_i_0[0]\, - time_mem_ren_i_0(1) => \time_mem_ren_i_0[1]\, - time_mem_ren_i_0(0) => \time_mem_ren_i_0[0]\, time_wen(1) - => time_wen(1), time_ren(1) => time_ren(1), - time_mem_addr_w_1_3 => \time_mem_addr_w_1[3]\, - time_mem_addr_w_1_0 => \time_mem_addr_w_1[0]\, - time_mem_addr_w_1_1 => \time_mem_addr_w_1[1]\, - time_mem_addr_r_1_3 => \time_mem_addr_r_1[3]\, - time_mem_addr_r_1_0 => \time_mem_addr_r_1[0]\, - time_mem_addr_r_1_1 => \time_mem_addr_r_1[1]\, - DWACT_FINC_E_0(0) => \DWACT_FINC_E[0]\, Waddr_vect_0 => - \Waddr_vect[2]\, DWACT_FINC_E(0) => \DWACT_FINC_E_0[0]\, - Raddr_vect_0 => \Raddr_vect_0[2]\, time_ren_1z => - time_ren_1z, rstn => rstn, lclk_c => lclk_c, - un20_time_write => un20_time_write, sFull_RNIKQ9G => - sFull_RNIKQ9G, N_115 => N_115, N_35 => N_35); - - \gen_fifo_ctrl_data.3.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ3 - port map(ready_i_0(3) => ready_i_0_3, data_mem_wen_i_0(3) - => \data_mem_wen_i_0[3]\, data_ren(3) => data_ren(3), - data_mem_ren_i_0(3) => \data_mem_ren_i_0[3]\, data_wen(3) - => data_wen(3), data_mem_addr_r_3(4) => - \data_mem_addr_r_3[4]\, data_mem_addr_r_3(3) => - \data_mem_addr_r_3[3]\, data_mem_addr_r_3(2) => - \data_mem_addr_r_3[2]\, data_mem_addr_r_3(1) => - \data_mem_addr_r_3[1]\, data_mem_addr_r_3(0) => - \data_mem_addr_r_3[0]\, data_mem_addr_w_3(4) => - \data_mem_addr_w_3[4]\, data_mem_addr_w_3(3) => - \data_mem_addr_w_3[3]\, data_mem_addr_w_3(2) => - \data_mem_addr_w_3[2]\, data_mem_addr_w_3(1) => - \data_mem_addr_w_3[1]\, data_mem_addr_w_3(0) => - \data_mem_addr_w_3[0]\, data_ren_1z => data_ren_1z, rstn - => rstn, lclk_c => lclk_c, un5_time_write => - un5_time_write); - - \gen_fifo_ctrl_data.0.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ0 - port map(ready_i_0(0) => ready_i_0_0, data_mem_wen_i_0(0) - => \data_mem_wen_i_0[0]\, data_mem_ren_i_0(0) => - \data_mem_ren_i_0[0]\, data_ren(0) => data_ren(0), - data_wen(0) => data_wen(0), data_mem_addr_r_0(4) => - \data_mem_addr_r_0[4]\, data_mem_addr_r_0(3) => - \data_mem_addr_r_0[3]\, data_mem_addr_r_0(2) => - \data_mem_addr_r_0[2]\, data_mem_addr_r_0(1) => - \data_mem_addr_r_0[1]\, data_mem_addr_r_0(0) => - \data_mem_addr_r_0[0]\, data_mem_addr_w_0(4) => - \data_mem_addr_w_0[4]\, data_mem_addr_w_0(3) => - \data_mem_addr_w_0[3]\, data_mem_addr_w_0(2) => - \data_mem_addr_w_0[2]\, data_mem_addr_w_0(1) => - \data_mem_addr_w_0[1]\, data_mem_addr_w_0(0) => - \data_mem_addr_w_0[0]\, rstn => rstn, lclk_c => lclk_c, - N_162 => N_162, N_157 => N_157, N_158 => N_158, - sEmpty_RNI6M6A4J => sEmpty_RNI6M6A4J, N_89 => N_89, - sEmpty_RNI6M6A4J_0 => sEmpty_RNI6M6A4J_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_addr_r_0_iv_i_RNO_2[5]\ : OR3A - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_ren_i_0[1]\, C => N_89, Y => - \data_addr_r_0_iv_i_RNO_2[5]_net_1\); - - \gen_fifo_ctrl_time.0.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ4 - port map(time_mem_wen_i_0(0) => \time_mem_wen_i_0[0]\, - time_mem_ren_i_0(0) => \time_mem_ren_i_0[0]\, time_wen(0) - => time_wen(0), time_ren(0) => time_ren(0), Waddr_vect_0 - => \Waddr_vect_0[2]\, time_mem_addr_w_0_3 => - \time_mem_addr_w_0[3]\, time_mem_addr_w_0_0 => - \time_mem_addr_w_0[0]\, time_mem_addr_w_0_1 => - \time_mem_addr_w_0[1]\, time_mem_addr_w_0_4 => - \time_mem_addr_w_0[4]\, Raddr_vect_0 => \Raddr_vect_1[2]\, - time_mem_addr_r_0_3 => \time_mem_addr_r_0[3]\, - time_mem_addr_r_0_0 => \time_mem_addr_r_0[0]\, - time_mem_addr_r_0_1 => \time_mem_addr_r_0[1]\, - time_mem_addr_r_0_4 => \time_mem_addr_r_0[4]\, - time_ren_1z => time_ren_1z, rstn => rstn, lclk_c => - lclk_c, un27_time_write => un27_time_write, N_4_0 => - N_4_1, N_4 => N_4_0); - - \gen_fifo_ctrl_time.2.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ6 - port map(time_mem_wen_i_0_1 => \time_mem_wen_i_0[1]\, - time_mem_wen_i_0_0 => \time_mem_wen_i_0[0]\, - time_mem_ren_i_0_1 => \time_mem_ren_i_0[1]\, - time_mem_ren_i_0_0 => \time_mem_ren_i_0[0]\, time_wen(2) - => time_wen(2), time_ren(2) => time_ren(2), Waddr_vect_0 - => \Waddr_vect_1[2]\, time_mem_addr_w_2_3 => - \time_mem_addr_w_2[3]\, time_mem_addr_w_2_0 => - \time_mem_addr_w_2[0]\, time_mem_addr_w_2_1 => - \time_mem_addr_w_2[1]\, time_mem_addr_w_2_4 => - \time_mem_addr_w_2[4]\, Raddr_vect_0 => \Raddr_vect[2]\, - time_mem_addr_r_2_3 => \time_mem_addr_r_2[3]\, - time_mem_addr_r_2_0 => \time_mem_addr_r_2[0]\, - time_mem_addr_r_2_1 => \time_mem_addr_r_2[1]\, - time_mem_addr_r_2_4 => \time_mem_addr_r_2[4]\, rstn => - rstn, lclk_c => lclk_c, N_161 => N_161, N_156 => N_156, - N_93 => N_93, N_88 => N_88, N_4_0 => N_4_2, N_4 => N_4); - - \data_addr_r_0_iv_i_RNO_3[5]\ : OA1B - port map(A => N_4_0, B => \time_mem_ren_i_0[0]\, C => N_35, - Y => \data_addr_r_0_iv_i_0[5]\); - - \data_addr_r_0_iv_i[5]\ : AND2 - port map(A => \data_addr_r_0_iv_i_2[5]\, B => - \data_addr_r_0_iv_i_3[5]\, Y => N_64_i_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_11 is - - port( sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - data_f0_out : out std_logic_vector(159 downto 64); - sample_f0_37 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_63 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_0 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_15 : in std_logic; - nb_snapshot_param : in std_logic_vector(10 downto 0); - rstn : in std_logic; - lclk_c : in std_logic; - data_f0_out_valid : out std_logic; - data_shaping_R0 : in std_logic; - data_shaping_R0_0 : in std_logic; - enable_f0 : in std_logic; - start_snapshot_f0 : in std_logic; - sample_f0_val_0 : in std_logic; - burst_f0 : in std_logic - ); - -end lpp_waveform_snapshot_160_11; - -architecture DEF_ARCH of lpp_waveform_snapshot_160_11 is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_data_out_valid_0_sqmuxa_1_3[31]\, - \counter_points_snapshot_0_sqmuxa_1_0\, - data_out_valid_0_sqmuxa_1, - \un1_data_out_valid_0_sqmuxa_1_2[31]\, - \un1_data_out_valid_0_sqmuxa_1_1[31]\, - \un1_data_out_valid_0_sqmuxa_1_0[31]\, - \data_out_valid_0_sqmuxa\, ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, - ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I253_Y_0_0, N_43, N485, N481, - ADD_32x32_fast_I250_Y_3, N603, N618, - ADD_32x32_fast_I250_Y_2, N546, N539, - ADD_32x32_fast_I250_Y_1, N479, N476, - ADD_32x32_fast_I250_Y_0, \un1_counter_points_snapshot[1]\, - I32_un1_Y, ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I300_Y_0_0, - \un1_counter_points_snapshot[11]\, - ADD_32x32_fast_I309_Y_0_0, - \un1_counter_points_snapshot[2]\, - ADD_32x32_fast_I253_Y_0_a2_0, N486, - ADD_32x32_fast_I295_Y_0_0, - \un1_counter_points_snapshot[16]\, - ADD_32x32_fast_I250_un1_Y_0, N619, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I310_Y_0_0, ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, - ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot[5]\, ADD_32x32_fast_I252_Y_2, - N622, N607, ADD_32x32_fast_I252_Y_1, N543, N550, - ADD_32x32_fast_I252_Y_0, N483, ADD_32x32_fast_I301_Y_0_0, - \un1_counter_points_snapshot[10]\, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I251_Y_3, N605, N620, - ADD_32x32_fast_I251_Y_2, N548, N541, - ADD_32x32_fast_I251_Y_1, N464, ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I302_Y_0_0, - \un1_counter_points_snapshot[9]\, ADD_32x32_fast_I254_Y_1, - N626, N611, ADD_32x32_fast_I254_Y_0, N554, N547, - ADD_32x32_fast_I256_Y_1, N630, N615, - ADD_32x32_fast_I256_Y_0, N558, N551, - ADD_32x32_fast_I255_Y_0, N556, N549, - ADD_32x32_fast_I291_Y_0_0, - \un1_counter_points_snapshot[20]\, - ADD_32x32_fast_I293_Y_0_0, - \un1_counter_points_snapshot[18]\, - ADD_32x32_fast_I252_un1_Y_0, N623, - ADD_32x32_fast_I264_Y_0, N646, N631, - ADD_32x32_fast_I294_Y_0_0, - \un1_counter_points_snapshot[17]\, - ADD_32x32_fast_I289_Y_0_0, - \un1_counter_points_snapshot[22]\, - ADD_32x32_fast_I254_un1_Y_0, N627, - ADD_32x32_fast_I251_un1_Y_0, N621, - ADD_32x32_fast_I256_un1_Y_0, ADD_32x32_fast_I290_Y_0_0, - \un1_counter_points_snapshot[21]\, - ADD_32x32_fast_I255_un1_Y_0, N629, N557, - ADD_32x32_fast_I264_un1_Y_0, N583, N528, N380, - ADD_32x32_fast_I285_Y_0_0, - \un1_counter_points_snapshot[26]\, - ADD_32x32_fast_I286_Y_0_0, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I283_Y_0_0, - \un1_counter_points_snapshot[28]\, - ADD_32x32_fast_I126_Y_0, ADD_32x32_fast_I118_Y_0, - ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[23]\, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I119_Y_0, - \counter_points_snapshot[14]_net_1\, - ADD_32x32_fast_I135_Y_0, - \un1_counter_points_snapshot[24]\, ADD_32x32_fast_I95_Y_0, - \counter_points_snapshot[29]_net_1\, - \counter_points_snapshot[28]_net_1\, - data_out_valid_0_sqmuxa_1_1, un4_data_in_validlt30_27, - un4_data_in_validlt30_18, un4_data_in_validlt30_17, - un4_data_in_validlt30_23, un4_data_in_validlt30_26, - un4_data_in_validlt30_12, un4_data_in_validlt30_11, - un4_data_in_validlt30_22, un4_data_in_validlt30_25, - un4_data_in_validlt30_8, un4_data_in_validlt30_7, - un4_data_in_validlt30_20, un4_data_in_validlt30_2, - un4_data_in_validlt30_1, un4_data_in_validlt30_15, - un4_data_in_validlt30_14, - \counter_points_snapshot[26]_net_1\, - \counter_points_snapshot[23]_net_1\, - un4_data_in_validlt30_10, - \counter_points_snapshot[20]_net_1\, - \counter_points_snapshot[19]_net_1\, - un4_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un4_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot_i_0[30]\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[27]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[21]_net_1\, - \counter_points_snapshot[22]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[18]_net_1\, - \counter_points_snapshot[15]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[13]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, N750, N789, N443_i, - I50_un1_Y_i, I110_un1_Y, N744, N752, N756, I222_un1_Y, - I259_un1_Y, N637, N652, N588, N529, N526, N766, N581, - N518, N580, N521, N572, I126_un1_Y, N573, N510, N411, - N414, N444, N441, N_8, N565, N502, N564, N505, N738, N771, - I262_un1_Y, N643, N594, N762, I228_un1_Y, - un4_data_in_validlto30_i, - \un1_data_out_valid_0_sqmuxa_2[7]\, N650, - \un1_data_out_valid_0_sqmuxa_2[5]\, N654, - \un1_data_out_valid_0_sqmuxa_2[9]\, - \un1_data_out_valid_0_sqmuxa_2[10]\, I240_un1_Y, N644, - N746, N783, N740, N774, N748, I255_un1_Y, I214_un1_Y, - N742, N777, \un1_data_out_valid_0_sqmuxa_2[4]\, N592_i, - N754, I220_un1_Y, I258_un1_Y, N635, - \un1_data_out_valid_0_sqmuxa_2[8]\, N648_i, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_counter_points_snapshot[29]\, N533, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, - \un1_data_out_valid_0_sqmuxa_2[3]\, - \un1_data_out_valid_0_sqmuxa_2[6]\, N758, I224_un1_Y, - I260_un1_Y, N639, ADD_32x32_fast_I263_Y_0, - ADD_32x32_fast_I263_un1_Y_0, N589, N764, N628, N516, N559, - N515, N636, \counter_points_snapshot_10[25]\, - un1_counter_points_snapshot_0_sqmuxa_1_i, N480, - \counter_points_snapshot_10[28]\, N489, N484, N487, N488, - N491, N446_i, N_6, N447, \counter_points_snapshot_10[24]\, - N492, I198_un1_Y, I176_un1_Y, N530, N562, N503, N500, - N499, I241_un1_Y, N590, I199_un1_Y, N582, N531, N527, - N496, N495, N504, N563, N555, N524, N520, N523, N519, - N587, N586, N579, N578, \counter_points_snapshot_10[14]\, - N508, N511, N512, N566, N507, N513, - \counter_points_snapshot_RNITNU94_3[31]_net_1\, N760_i, - \counter_points_snapshot_10[20]\, N575, N638, N574, N567, - N571, N570, N642, \un1_data_out_valid_0_sqmuxa_2[0]\, - \un1_counter_points_snapshot[31]\, N_276, - \counter_points_snapshot_2_sqmuxa\, N_281, N_283, - \counter_points_snapshot_10[0]\, - \counter_points_snapshot_10[5]\, - \counter_points_snapshot_10[7]\, - \counter_points_snapshot_10[15]\, - \counter_points_snapshot_10[19]\, - \counter_points_snapshot_10[31]\, \sample_f0_wdata[32]\, - \sample_f0_wdata[33]\, \sample_f0_wdata[34]\, - \sample_f0_wdata[35]\, \sample_f0_wdata[19]\, - \sample_f0_wdata[20]\, \sample_f0_wdata[21]\, - \sample_f0_wdata[22]\, \sample_f0_wdata[23]\, - \sample_f0_wdata[24]\, \sample_f0_wdata[25]\, - \sample_f0_wdata[26]\, \sample_f0_wdata[27]\, - \sample_f0_wdata[28]\, \sample_f0_wdata[29]\, - \sample_f0_wdata[30]\, \sample_f0_wdata[31]\, - \sample_f0_wdata[43]\, \sample_f0_wdata[44]\, - \sample_f0_wdata[45]\, \sample_f0_wdata[46]\, - \sample_f0_wdata[47]\, \sample_f0_wdata[16]\, - \sample_f0_wdata[17]\, \sample_f0_wdata[18]\, - \sample_f0_wdata[36]\, \sample_f0_wdata[37]\, - \sample_f0_wdata[38]\, \sample_f0_wdata[39]\, - \sample_f0_wdata[40]\, \sample_f0_wdata[41]\, - \sample_f0_wdata[42]\, \counter_points_snapshot_10[10]\, - N_286, \counter_points_snapshot_10[9]\, N_285, - \counter_points_snapshot_2_sqmuxa_2\, - \counter_points_snapshot_10[18]\, - \counter_points_snapshot_10[27]\, - \counter_points_snapshot_10[30]\, - counter_points_snapshot_0_sqmuxa_i, - \counter_points_snapshot_3_sqmuxa\, - \counter_points_snapshot_0_sqmuxa_1\, data_out_valid_19, - un1_enable_2, \counter_points_snapshot_10[29]\, - \counter_points_snapshot_10[26]\, - \counter_points_snapshot_10[13]\, - \counter_points_snapshot_10[23]\, - \counter_points_snapshot_10[22]\, - \counter_points_snapshot_10[4]\, N_280, N634, N_277, - N_278, N_279, N_284, \counter_points_snapshot_10[1]\, - \counter_points_snapshot_10[2]\, - \counter_points_snapshot_10[3]\, - \counter_points_snapshot_10[8]\, - \counter_points_snapshot_10[17]\, - \counter_points_snapshot_10[16]\, N768_i, - \counter_points_snapshot_10[6]\, N_282, N780_i, - \counter_points_snapshot_10[11]\, - \counter_points_snapshot_10[21]\, - \counter_points_snapshot_10[12]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - - \counter_points_snapshot_RNIJ1PE[29]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[29]_net_1\, Y => - \un1_counter_points_snapshot[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_0 : - NOR3B - port map(A => N549, B => N629, C => N557, Y => - ADD_32x32_fast_I255_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y : - OAI1 - port map(A => I240_un1_Y, B => N644, C => - ADD_32x32_fast_I255_un1_Y_0, Y => I255_un1_Y); - - \counter_points_snapshot_RNISMQU3[31]\ : NOR2 - port map(A => data_out_valid_0_sqmuxa_1_1, B => - un4_data_in_validlto30_i, Y => data_out_valid_0_sqmuxa_1); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[13]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[27]\, C => N592_i, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I179_Y : NOR2B - port map(A => N575, B => N567, Y => N631); - - \data_out[110]\ : DFN1C0 - port map(D => \sample_f0_wdata[46]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(110)); - - \counter_points_snapshot_RNITNU94[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \un1_data_out_valid_0_sqmuxa_1_0[31]\); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[10]\, B => - nb_snapshot_param(10), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_286); - - \counter_points_snapshot_RNO[27]\ : XA1C - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[27]\); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[28]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[28]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y_0 : - NOR2B - port map(A => N607, B => N623, Y => - ADD_32x32_fast_I252_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_P0N : OR2A - port map(A => \un1_counter_points_snapshot[11]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N441); - - data_out_valid_0_sqmuxa : NOR2B - port map(A => sample_f0_val_0, B => start_snapshot_f0, Y - => \data_out_valid_0_sqmuxa\); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762, B => ADD_32x32_fast_I299_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[19]\); - - \data_out_RNO[96]\ : MX2 - port map(A => sample_f0_15, B => sample_f0_47, S => - data_shaping_R0_0, Y => \sample_f0_wdata[32]\); - - \data_out[91]\ : DFN1C0 - port map(D => \sample_f0_wdata[27]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(91)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I143_Y : OR2B - port map(A => N530, B => N526, Y => N589); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f0_wdata_56, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1B - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I93_Y : NOR2A - port map(A => N476, B => N480, Y => N539); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : OA1B - port map(A => N783, B => ADD_32x32_fast_I254_un1_Y_0, C => - ADD_32x32_fast_I254_Y_1, Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : AO1 - port map(A => N586, B => N579, C => N578, Y => N642); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I101_Y : NOR2B - port map(A => N488, B => N484, Y => N547); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f0_wdata_66, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => \sample_f0_wdata[40]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : NOR2 - port map(A => N491, B => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => nb_snapshot_param(4), B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_280); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I167_Y : NOR2B - port map(A => N563, B => N555, Y => N619); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[1]\, B => - nb_snapshot_param(1), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_277); - - \data_out[102]\ : DFN1C0 - port map(D => \sample_f0_wdata[38]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I64_Y : OA1A - port map(A => \un1_counter_points_snapshot[18]\, B => - \un1_counter_points_snapshot[17]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N507); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : AO1B - port map(A => ADD_32x32_fast_I252_un1_Y_0, B => N777, C => - ADD_32x32_fast_I252_Y_2, Y => N742); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I113_Y : NOR2B - port map(A => N500, B => N496, Y => N559); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_283, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[2]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1B - port map(A => N780_i, B => ADD_32x32_fast_I292_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[12]\); - - \counter_points_snapshot_RNIL0A7[21]\ : NOR2 - port map(A => \counter_points_snapshot[21]_net_1\, B => - \counter_points_snapshot[22]_net_1\, Y => - un4_data_in_validlt30_10); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : AO1 - port map(A => N650, B => N635, C => N634, Y => N771); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I137_Y : NOR2 - port map(A => N524, B => N520, Y => N583); - - \data_out[93]\ : DFN1C0 - port map(D => \sample_f0_wdata[29]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(93)); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[4]_net_1\); - - counter_points_snapshot_2_sqmuxa : OR3B - port map(A => enable_f0, B => - \counter_points_snapshot_2_sqmuxa_2\, C => burst_f0, Y - => \counter_points_snapshot_2_sqmuxa\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I33_Y : AO1A - port map(A => \counter_points_snapshot_i_0[30]\, B => - \counter_points_snapshot[29]_net_1\, C => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N476); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f0_wdata_95, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => \sample_f0_wdata[41]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(105)); - - \counter_points_snapshot_RNIVE7T[15]\ : NOR3C - port map(A => un4_data_in_validlt30_8, B => - un4_data_in_validlt30_7, C => un4_data_in_validlt30_20, Y - => un4_data_in_validlt30_25); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[15]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f0_wdata_77, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_un1_Y_0 : - NOR2B - port map(A => N605, B => N621, Y => - ADD_32x32_fast_I251_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : AO1 - port map(A => N495, B => N492, C => N491, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OAI1 - port map(A => N524, B => N527, C => N523, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => \sample_f0_wdata[17]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(81)); - - \data_out_RNO[99]\ : MX2 - port map(A => sample_f0_12, B => sample_f0_44, S => - data_shaping_R0_0, Y => \sample_f0_wdata[35]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[1]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I310_Y_0_0); - - \data_out_RNO[104]\ : MX2 - port map(A => sample_f0_7, B => sample_f0_39, S => - data_shaping_R0, Y => \sample_f0_wdata[40]\); - - \counter_points_snapshot_RNINCIG[0]\ : MX2 - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[31]\); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : AOI1B - port map(A => N558, B => N551, C => N550, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - AO18 - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[16]\, C => N771, Y => N768_i); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f0_wdata_50, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I97_Y : NOR2A - port map(A => N484, B => N480, Y => N543); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : AO1A - port map(A => N571, B => N578, C => N570, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : AOI1 - port map(A => N507, B => N504, C => N503, Y => N566); - - \counter_points_snapshot_RNIG1PE[26]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot[5]\); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[27]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f0_wdata_79, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : OR2 - port map(A => N590, B => I199_un1_Y, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3B - port map(A => N443_i, B => I50_un1_Y_i, C => I110_un1_Y, Y - => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f0_wdata_48, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f0_wdata_60, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(124)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I65_Y : AO1A - port map(A => \un1_counter_points_snapshot[18]\, B => - \counter_points_snapshot[14]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N508); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f0_wdata_70, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : AO1B - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[25]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N523); - - \counter_points_snapshot_RNO[28]\ : XA1B - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[28]\); - - \data_out[83]\ : DFN1C0 - port map(D => \sample_f0_wdata[19]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : AOI1B - port map(A => N546, B => N539, C => ADD_32x32_fast_I250_Y_1, - Y => ADD_32x32_fast_I250_Y_2); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f0_wdata_58, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f0_wdata_51, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(115)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : AOI1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : - AOI1B - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_counter_points_snapshot[4]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N481); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y : - OR3B - port map(A => N643, B => N594, C => N627, Y => I262_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AO1B - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[15]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f0_wdata_68, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(132)); - - \counter_points_snapshot[30]\ : DFN1P0 - port map(D => \counter_points_snapshot_10[30]\, CLK => - lclk_c, PRE => rstn, Q => - \counter_points_snapshot_i_0[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I37_Y : OA1C - port map(A => \counter_points_snapshot[28]_net_1\, B => - \un1_counter_points_snapshot[4]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N480); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I228_un1_Y : - OR2A - port map(A => N642, B => N627, Y => I228_un1_Y); - - \counter_points_snapshot_RNII1PE[28]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I69_Y : OA1A - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, C => N414, Y => - N512); - - \data_out[96]\ : DFN1C0 - port map(D => \sample_f0_wdata[32]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(96)); - - \counter_points_snapshot_RNIRKIG[2]\ : MX2C - port map(A => nb_snapshot_param(2), B => - \counter_points_snapshot[2]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[29]\); - - \counter_points_snapshot_RNIH1PE[27]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - \counter_points_snapshot_RNIETOE[17]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : OR3C - port map(A => I255_un1_Y, B => ADD_32x32_fast_I255_Y_0, C - => I214_un1_Y, Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f0_wdata_61, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(125)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I185_Y : NOR2 - port map(A => N581, B => N573, Y => N637); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f0_wdata_71, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(135)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I224_un1_Y : - NOR2B - port map(A => N638, B => N623, Y => I224_un1_Y); - - \data_out_RNO[87]\ : NOR2B - port map(A => sample_f0_56, B => data_shaping_R0_0, Y => - \sample_f0_wdata[23]\); - - \data_out_RNO[108]\ : MX2 - port map(A => sample_f0_3, B => sample_f0_35, S => - data_shaping_R0, Y => \sample_f0_wdata[44]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_un1_Y : - OR3C - port map(A => N621, B => N637, C => N652, Y => I259_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I290_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : OA1B - port map(A => N752, B => ADD_32x32_fast_I253_Y_0_a2_0, C - => ADD_32x32_fast_I253_Y_0_0, Y => N744); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I75_Y : AO1D - port map(A => \un1_counter_points_snapshot[23]\, B => - \un1_counter_points_snapshot[22]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N518); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I129_Y : NOR2A - port map(A => N512, B => N516, Y => N575); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y : NOR2B - port map(A => ADD_32x32_fast_I119_Y_0, B => N502, Y => N565); - - \counter_points_snapshot_RNI35JG[6]\ : MX2C - port map(A => nb_snapshot_param(6), B => - \counter_points_snapshot[6]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[25]\); - - \counter_points_snapshot_RNI31A7[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un4_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I171_Y : NOR2B - port map(A => N567, B => N559, Y => N623); - - data_out_valid : DFN1C0 - port map(D => data_out_valid_19, CLK => lclk_c, CLR => rstn, - Q => data_f0_out_valid); - - \data_out_RNO[90]\ : NOR2B - port map(A => sample_f0_53, B => data_shaping_R0_0, Y => - \sample_f0_wdata[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : AOI1 - port map(A => N570, B => N563, C => N562, Y => N626); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I29_G0N : OR2B - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[2]\, Y => I32_un1_Y); - - \counter_points_snapshot_RNID1PE[23]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f0_wdata_7, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f0_wdata_1, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[18]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : NOR3 - port map(A => I224_un1_Y, B => N622, C => I260_un1_Y, Y => - N758); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I45_Y : AO1A - port map(A => \un1_counter_points_snapshot[7]\, B => - \counter_points_snapshot[23]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N488); - - \data_out_RNO[98]\ : MX2 - port map(A => sample_f0_13, B => sample_f0_45, S => - data_shaping_R0_0, Y => \sample_f0_wdata[34]\); - - \data_out[86]\ : DFN1C0 - port map(D => \sample_f0_wdata[22]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : AOI1 - port map(A => N562, B => N555, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f0_wdata_86, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(150)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f0_wdata_84, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(148)); - - GND_i : GND - port map(Y => \GND\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I49_Y : NOR2B - port map(A => N447, B => N444, Y => N492); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[8]_net_1\); - - counter_points_snapshot_2_sqmuxa_2 : NOR2A - port map(A => start_snapshot_f0, B => sample_f0_val_0, Y - => \counter_points_snapshot_2_sqmuxa_2\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I61_Y : AO1D - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[15]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N504); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : AO1B - port map(A => N574, B => N567, C => N566, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR2A - port map(A => N523, B => N519, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f0_wdata_9, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I59_Y : AO1D - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[14]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N502); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I283_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_3 : OA1A - port map(A => N603, B => N618, C => ADD_32x32_fast_I250_Y_2, - Y => ADD_32x32_fast_I250_Y_3); - - \data_out[92]\ : DFN1C0 - port map(D => \sample_f0_wdata[28]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f0_wdata_3, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => \sample_f0_wdata[43]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I83_Y : AO1D - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[26]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N526); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OA1 - port map(A => ADD_32x32_fast_I263_un1_Y_0, B => N644, C => - N629, Y => ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_282, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : AX1B - port map(A => I240_un1_Y, B => N644, C => - ADD_32x32_fast_I290_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I220_un1_Y : - OR2B - port map(A => N634, B => N619, Y => I220_un1_Y); - - \counter_points_snapshot_RNIUGJE[10]\ : NOR3A - port map(A => un4_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un4_data_in_validlt30_18); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[29]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[29]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_3 : OA1A - port map(A => N605, B => N620, C => ADD_32x32_fast_I251_Y_2, - Y => ADD_32x32_fast_I251_Y_3); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I183_Y : NOR2A - port map(A => N579, B => N571, Y => N635); - - \data_out_RNO[94]\ : NOR2B - port map(A => sample_f0_49, B => data_shaping_R0_0, Y => - \sample_f0_wdata[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1C - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[25]\); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[20]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I302_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y_0 : - NOR2B - port map(A => N615, B => N631, Y => - ADD_32x32_fast_I256_un1_Y_0); - - \data_out_RNO[95]\ : NOR2B - port map(A => sample_f0_48, B => data_shaping_R0, Y => - \sample_f0_wdata[31]\); - - \counter_points_snapshot_RNIR7VB[0]\ : NOR3A - port map(A => \counter_points_snapshot_i_0[30]\, B => - \counter_points_snapshot[1]_net_1\, C => - \counter_points_snapshot[0]_net_1\, Y => - un4_data_in_validlt30_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I191_Y : NOR2B - port map(A => N587, B => N579, Y => N643); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_un1_Y : - OR2B - port map(A => N513, B => N510, Y => I126_un1_Y); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[17]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : AO1 - port map(A => N590, B => N583, C => N582, Y => N646); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_un1_Y : - NOR2B - port map(A => N572, B => N565, Y => I176_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : AO1B - port map(A => \un1_counter_points_snapshot[29]\, B => - \un1_counter_points_snapshot[30]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N531); - - \counter_points_snapshot_RNIFTOE[18]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I28_G0N : OR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_2[31]\, B => - \un1_counter_points_snapshot[3]\, Y => N464); - - \counter_points_snapshot_RNIV3C8[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un4_data_in_validlt30_4); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : AO1B - port map(A => ADD_32x32_fast_I250_un1_Y_0, B => N771, C => - ADD_32x32_fast_I250_Y_3, Y => N738); - - \data_out_RNO[93]\ : NOR2B - port map(A => sample_f0_50, B => data_shaping_R0_0, Y => - \sample_f0_wdata[29]\); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f0_wdata_90, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(154)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - AOI1 - port map(A => N_8, B => N764, C => I110_un1_Y, Y => N760_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_un1_Y : - OR3C - port map(A => N619, B => N635, C => N650, Y => I258_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I11_P0N : OR2A - port map(A => \un1_counter_points_snapshot[20]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N414); - - \data_out[82]\ : DFN1C0 - port map(D => \sample_f0_wdata[18]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(82)); - - \counter_points_snapshot_RNIN3B8[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un4_data_in_validlt30_2); - - \counter_points_snapshot_RNID5PE[30]\ : NOR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot_i_0[30]\, Y => - \un1_counter_points_snapshot[1]\); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f0_wdata_53, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1B - port map(A => N760_i, B => ADD_32x32_fast_I300_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : AO1 - port map(A => N554, B => N547, C => N546, Y => - ADD_32x32_fast_I254_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I87_Y : AO1D - port map(A => \un1_counter_points_snapshot[29]\, B => - \un1_counter_points_snapshot[28]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N530); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I41_Y : AO1A - port map(A => \un1_counter_points_snapshot[6]\, B => - \counter_points_snapshot[26]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N484); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f0_wdata_12, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f0_wdata_88, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(152)); - - \counter_points_snapshot_RNIT70S1[10]\ : NOR3C - port map(A => un4_data_in_validlt30_18, B => - un4_data_in_validlt30_17, C => un4_data_in_validlt30_23, - Y => un4_data_in_validlt30_27); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f0_wdata_85, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(149)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I285_Y_0_0); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f0_wdata_63, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : AO1 - port map(A => N654, B => N639, C => N638, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : AO1 - port map(A => N652, B => N637, C => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2B - port map(A => N588, B => I198_un1_Y, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f0_wdata_73, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I141_Y : NOR2 - port map(A => N528, B => N524, Y => N587); - - \data_out_RNO[81]\ : NOR2B - port map(A => sample_f0_62, B => data_shaping_R0, Y => - \sample_f0_wdata[17]\); - - \counter_points_snapshot_RNIJJA8[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un4_data_in_validlt30_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : OAI1 - port map(A => N528, B => N531, C => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f0_wdata_91, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(155)); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNINO97[15]\ : NOR2 - port map(A => \counter_points_snapshot[15]_net_1\, B => - \counter_points_snapshot[16]_net_1\, Y => - un4_data_in_validlt30_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_a2_0_0 : - OR2 - port map(A => N_43, B => N486, Y => - ADD_32x32_fast_I253_Y_0_a2_0); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_281, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1C - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[17]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I177_Y : NOR2A - port map(A => N565, B => N573, Y => N629); - - data_out_valid_RNO_0 : OAI1 - port map(A => \data_out_valid_0_sqmuxa\, B => - data_out_valid_0_sqmuxa_1, C => enable_f0, Y => - un1_enable_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I121_Y : NOR2B - port map(A => N508, B => N504, Y => N567); - - \data_out[90]\ : DFN1C0 - port map(D => \sample_f0_wdata[26]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_0 : AO1B - port map(A => \un1_counter_points_snapshot[18]\, B => - \un1_counter_points_snapshot[19]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I126_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR2 - port map(A => N511, B => N507, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : AO1B - port map(A => ADD_32x32_fast_I251_un1_Y_0, B => N774, C => - ADD_32x32_fast_I251_Y_3, Y => N740); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_un1_Y_0 : - NOR2B - port map(A => N603, B => N619, Y => - ADD_32x32_fast_I250_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I111_Y : OR3C - port map(A => N444, B => N441, C => N_8, Y => N557); - - \counter_points_snapshot_RNO[14]\ : XA1B - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[14]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_G0N : OR2A - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[11]\, Y => I50_un1_Y_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : AO1A - port map(A => N516, B => N519, C => N515, Y => N578); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[29]\, C => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - \data_out_RNO[92]\ : NOR2B - port map(A => sample_f0_51, B => data_shaping_R0_0, Y => - \sample_f0_wdata[28]\); - - \data_out[99]\ : DFN1C0 - port map(D => \sample_f0_wdata[35]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(99)); - - \data_out_RNO[100]\ : MX2 - port map(A => sample_f0_11, B => sample_f0_43, S => - data_shaping_R0, Y => \sample_f0_wdata[36]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I76_Y : AOI1B - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_counter_points_snapshot[23]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N519); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I95_Y : NOR2 - port map(A => ADD_32x32_fast_I95_Y_0, B => N_43, Y => N541); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : OR3C - port map(A => I220_un1_Y, B => N618, C => I258_un1_Y, Y => - N754); - - \data_out[106]\ : DFN1C0 - port map(D => \sample_f0_wdata[42]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(106)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I70_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_counter_points_snapshot[21]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N513); - - \counter_points_snapshot_RNIA1PE[20]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[20]_net_1\, Y => - \un1_counter_points_snapshot[11]\); - - \counter_points_snapshot_RNO[21]\ : XA1B - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[21]\); - - \counter_points_snapshot_RNI9TOE[12]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_0 : AOI1B - port map(A => \un1_data_out_valid_0_sqmuxa_1_0[31]\, B => - \un1_counter_points_snapshot[1]\, C => I32_un1_Y, Y => - ADD_32x32_fast_I250_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y_0 : AOI1 - port map(A => N646, B => N631, C => N630, Y => - ADD_32x32_fast_I264_Y_0); - - \data_out_RNO[103]\ : MX2 - port map(A => sample_f0_8, B => sample_f0_40, S => - data_shaping_R0, Y => \sample_f0_wdata[39]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : AO1 - port map(A => N515, B => N512, C => N511, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => \sample_f0_wdata[34]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(98)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_un1_Y : - NOR3A - port map(A => N583, B => N528, C => N380, Y => I241_un1_Y); - - \counter_points_snapshot_RNIRO97[17]\ : NOR2 - port map(A => \counter_points_snapshot[17]_net_1\, B => - \counter_points_snapshot[18]_net_1\, Y => - un4_data_in_validlt30_8); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y : AO1B - port map(A => N505, B => N502, C => ADD_32x32_fast_I118_Y_0, - Y => N564); - - \data_out[80]\ : DFN1C0 - port map(D => \sample_f0_wdata[16]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f0_wdata_8, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : AO1B - port map(A => ADD_32x32_fast_I256_un1_Y_0, B => N789, C => - ADD_32x32_fast_I256_Y_1, Y => N750); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_G0N : OR2A - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[9]\, Y => N446_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AOI1B - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[14]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N499); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I135_Y : OR2B - port map(A => ADD_32x32_fast_I135_Y_0, B => N518, Y => N581); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[23]\, C => N648_i, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - \data_out_RNO[107]\ : MX2 - port map(A => sample_f0_4, B => sample_f0_36, S => - data_shaping_R0, Y => \sample_f0_wdata[43]\); - - \data_out[89]\ : DFN1C0 - port map(D => \sample_f0_wdata[25]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(89)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : OR2 - port map(A => N628, B => ADD_32x32_fast_I263_Y_0, Y => N764); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I289_Y_0_0, B => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out_RNO[101]\ : MX2 - port map(A => sample_f0_10, B => sample_f0_42, S => - data_shaping_R0, Y => \sample_f0_wdata[37]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f0_wdata_52, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[19]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[2]\, B => - nb_snapshot_param(2), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_278); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : AO1 - port map(A => N594, B => N587, C => N586, Y => N650); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I285_Y_0_0, B => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNIQS97[27]\ : NOR2 - port map(A => \counter_points_snapshot[27]_net_1\, B => - \counter_points_snapshot[14]_net_1\, Y => - un4_data_in_validlt30_12); - - \counter_points_snapshot_RNO[18]\ : XA1C - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[18]\); - - \data_out[88]\ : DFN1C0 - port map(D => \sample_f0_wdata[24]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I10_P0N : OR2A - port map(A => \un1_counter_points_snapshot[21]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N411); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XOR2 - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[31]\, Y => - \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f0_wdata_62, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => \sample_f0_wdata[30]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f0_wdata_76, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f0_wdata_72, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(136)); - - \counter_points_snapshot_RNITNU94_3[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \counter_points_snapshot_RNITNU94_3[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I47_Y_i : OAI1 - port map(A => \counter_points_snapshot[23]_net_1\, B => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, C => N447, Y => - N_6); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[18]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I293_Y_0_0); - - \counter_points_snapshot_RNI8TOE[11]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[11]_net_1\, Y => - \un1_counter_points_snapshot[20]\); - - \counter_points_snapshot_RNIU1KE[23]\ : NOR3A - port map(A => un4_data_in_validlt30_14, B => - \counter_points_snapshot[26]_net_1\, C => - \counter_points_snapshot[23]_net_1\, Y => - un4_data_in_validlt30_22); - - \counter_points_snapshot_RNID0B8[31]\ : OR3A - port map(A => sample_f0_val_0, B => start_snapshot_f0, C - => \counter_points_snapshot[31]_net_1\, Y => - data_out_valid_0_sqmuxa_1_1); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[22]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[22]_net_1\); - - \data_out_RNO[86]\ : NOR2B - port map(A => sample_f0_57, B => data_shaping_R0_0, Y => - \sample_f0_wdata[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2B - port map(A => N531, B => N380, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I304_Y_0_0); - - data_out_valid_RNO_1 : NOR2B - port map(A => enable_f0, B => burst_f0, Y => - counter_points_snapshot_0_sqmuxa_i); - - \data_out[101]\ : DFN1C0 - port map(D => \sample_f0_wdata[37]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(101)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I102_Y : AO1C - port map(A => N486, B => N489, C => N485, Y => N548); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I155_Y : NOR2B - port map(A => N551, B => N543, Y => N607); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f0_wdata_93, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_280, Y => - \counter_points_snapshot_10[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I163_Y : NOR2B - port map(A => N559, B => N551, Y => N615); - - \counter_points_snapshot_RNO[30]\ : XO1A - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[30]\); - - \counter_points_snapshot_RNI7DJG[8]\ : MX2C - port map(A => nb_snapshot_param(8), B => - \counter_points_snapshot[8]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[23]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I222_un1_Y : - OR2B - port map(A => N636, B => N621, Y => I222_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I127_Y : OR3C - port map(A => N510, B => N411, C => N414, Y => N573); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : - OA1A - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => - I110_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR2 - port map(A => N564, B => I176_un1_Y, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[23]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I134_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I117_Y : NOR2B - port map(A => N504, B => N500, Y => N563); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f0_wdata_6, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => nb_snapshot_param(5), B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_281); - - \data_out[84]\ : DFN1C0 - port map(D => \sample_f0_wdata[20]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => \sample_f0_wdata[39]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : AO1B - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[28]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N527); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I135_Y_0 : AO1D - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_counter_points_snapshot[25]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I135_Y_0); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[5]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I133_Y : NOR2 - port map(A => N520, B => N516, Y => N579); - - \counter_points_snapshot_RNITNU94_0[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \un1_data_out_valid_0_sqmuxa_1_1[31]\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I289_Y_0_0); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f0_wdata_15, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_2 : AOI1B - port map(A => N622, B => N607, C => ADD_32x32_fast_I252_Y_1, - Y => ADD_32x32_fast_I252_Y_2); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f0_wdata_80, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(144)); - - \data_out_RNO[89]\ : NOR2B - port map(A => sample_f0_54, B => data_shaping_R0_0, Y => - \sample_f0_wdata[25]\); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_284, Y => - \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => \sample_f0_wdata[47]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I105_Y : NOR2B - port map(A => N492, B => N488, Y => N551); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2B - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[31]\, Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f0_wdata_78, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f0_wdata_14, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1C - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[23]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I39_Y_i_o2 : - OA1C - port map(A => \counter_points_snapshot[26]_net_1\, B => - \un1_counter_points_snapshot[4]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N_43); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : AO1D - port map(A => N580, B => N573, C => N572, Y => N636); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[3]\, B => - nb_snapshot_param(3), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_279); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[26]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : OA1A - port map(A => N543, B => N550, C => ADD_32x32_fast_I252_Y_0, - Y => ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_un1_Y_0 : - NOR3A - port map(A => N533, B => N581, C => N589, Y => - ADD_32x32_fast_I263_un1_Y_0); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f0_wdata_57, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : AOI1B - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[16]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_276, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f0_wdata_67, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f0_wdata_49, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(113)); - - \counter_points_snapshot_RNIATOE[13]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[13]_net_1\, Y => - \un1_counter_points_snapshot[18]\); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f0_wdata_81, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(145)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_un1_Y_0 : - NOR3A - port map(A => N583, B => N528, C => N380, Y => - ADD_32x32_fast_I264_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I85_Y : OA1B - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[28]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N528); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[16]\, B => - \counter_points_snapshot[14]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I119_Y_0); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f0_wdata_2, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[1]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_1 : AO1D - port map(A => N626, B => N611, C => ADD_32x32_fast_I254_Y_0, - Y => ADD_32x32_fast_I254_Y_1); - - \counter_points_snapshot_RNO[31]\ : XA1C - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[31]\); - - \data_out_RNO[109]\ : MX2 - port map(A => sample_f0_2, B => sample_f0_34, S => - data_shaping_R0, Y => \sample_f0_wdata[45]\); - - \counter_points_snapshot_RNO_0[0]\ : MX2C - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_276); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N771, B => ADD_32x32_fast_I295_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[15]\); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f0_wdata_59, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(123)); - - GND_i_0 : GND - port map(Y => GND_0); - - counter_points_snapshot_3_sqmuxa : OR2 - port map(A => start_snapshot_f0, B => burst_f0, Y => - \counter_points_snapshot_3_sqmuxa\); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f0_wdata_69, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : OR2A - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[10]\, Y => N443_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I153_Y : NOR2B - port map(A => N549, B => N541, Y => N605); - - \counter_points_snapshot_RNO[29]\ : XA1B - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[29]\); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[31]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[31]_net_1\); - - \counter_points_snapshot_RNIB1PE[21]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - \un1_counter_points_snapshot[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : AOI1B - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[3]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N479); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I55_Y_i : AO1A - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N_8); - - \data_out_RNO[97]\ : MX2 - port map(A => sample_f0_14, B => sample_f0_46, S => - data_shaping_R0_0, Y => \sample_f0_wdata[33]\); - - \counter_points_snapshot_RNITNU94_2[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \un1_data_out_valid_0_sqmuxa_1_3[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_1 : AOI1B - port map(A => N630, B => N615, C => ADD_32x32_fast_I256_Y_0, - Y => ADD_32x32_fast_I256_Y_1); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f0_wdata_10, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(74)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I169_Y : NOR2A - port map(A => N565, B => N557, Y => N621); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_286, Y => - \counter_points_snapshot_10[10]\); - - \data_out[108]\ : DFN1C0 - port map(D => \sample_f0_wdata[44]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => nb_snapshot_param(6), B => - \un1_data_out_valid_0_sqmuxa_2[6]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_282); - - \counter_points_snapshot_RNIJV7T[23]\ : NOR3C - port map(A => un4_data_in_validlt30_12, B => - un4_data_in_validlt30_11, C => un4_data_in_validlt30_22, - Y => un4_data_in_validlt30_26); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f0_wdata_92, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(156)); - - \data_out_RNO[106]\ : MX2 - port map(A => sample_f0_5, B => sample_f0_37, S => - data_shaping_R0, Y => \sample_f0_wdata[42]\); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[8]\, B => - nb_snapshot_param(8), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_284); - - \data_out_RNO[80]\ : NOR2B - port map(A => sample_f0_63, B => data_shaping_R0, Y => - \sample_f0_wdata[16]\); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_277, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : AOI1B - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[5]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - OA1C - port map(A => N756, B => N_6, C => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[22]\); - - \data_out_RNO[88]\ : NOR2B - port map(A => sample_f0_55, B => data_shaping_R0_0, Y => - \sample_f0_wdata[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_un1_Y : - NOR2 - port map(A => N528, B => N380, Y => I199_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I146_Y : AOI1 - port map(A => N533, B => N530, C => N529, Y => N592_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y : NOR2 - port map(A => N_6, B => N486, Y => N549); - - \counter_points_snapshot_RNIPGIG[1]\ : MX2C - port map(A => nb_snapshot_param(1), B => - \counter_points_snapshot[1]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[30]\); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[12]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot_RNITNU94_1[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \un1_data_out_valid_0_sqmuxa_1_2[31]\); - - \counter_points_snapshot_RNIGTOE[19]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[24]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[24]_net_1\); - - \data_out[95]\ : DFN1C0 - port map(D => \sample_f0_wdata[31]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(95)); - - \counter_points_snapshot_RNITOIG[3]\ : MX2C - port map(A => nb_snapshot_param(3), B => - \counter_points_snapshot[3]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[28]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_0 : NOR2 - port map(A => N483, B => N479, Y => ADD_32x32_fast_I252_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_un1_Y : - NOR3A - port map(A => N533, B => N581, C => N589, Y => I240_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I196_Y_0_o2 : - AO18 - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[24]\, C => N650, Y => N648_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR2B - port map(A => ADD_32x32_fast_I126_Y_0, B => I126_un1_Y, Y - => N572); - - \data_out_RNO[110]\ : MX2 - port map(A => sample_f0_1, B => sample_f0_33, S => - data_shaping_R0, Y => \sample_f0_wdata[46]\); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[9]\, B => - nb_snapshot_param(9), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_285); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I116_Y : AO1 - port map(A => N503, B => N500, C => N499, Y => N562); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_279, Y => - \counter_points_snapshot_10[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[27]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f0_wdata_54, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(118)); - - \counter_points_snapshot_RNIQNNG[6]\ : NOR3A - port map(A => un4_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un4_data_in_validlt30_17); - - counter_points_snapshot_0_sqmuxa_1_0 : OR2A - port map(A => \data_out_valid_0_sqmuxa\, B => burst_f0, Y - => \counter_points_snapshot_0_sqmuxa_1_0\); - - \counter_points_snapshot_RNIE1PE[24]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - \counter_points_snapshot_RNICTOE[15]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - \un1_counter_points_snapshot[16]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR2 - port map(A => N646, B => I241_un1_Y, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I81_Y : OA1B - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_counter_points_snapshot[26]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N524); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : NOR3B - port map(A => N464, B => I32_un1_Y, C => N481, Y => - ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : AOI1 - port map(A => N643, B => N594, C => N642, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I175_Y : OR2A - port map(A => N563, B => N571, Y => N627); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[24]\, C => N650, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I286_Y_0_0, B => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - AO1C - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, C => N446_i, Y => - N489); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I100_Y : AO1 - port map(A => N487, B => N484, C => N483, Y => N546); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f0_wdata_64, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(128)); - - \counter_points_snapshot_RNO[11]\ : XA1B - port map(A => N783, B => ADD_32x32_fast_I291_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => \sample_f0_wdata[33]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f0_wdata_74, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(138)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I78_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_counter_points_snapshot[24]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N521); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I187_Y : NOR2B - port map(A => N583, B => N575, Y => N639); - - \data_out_RNO[84]\ : NOR2B - port map(A => sample_f0_59, B => data_shaping_R0_0, Y => - \sample_f0_wdata[20]\); - - \counter_points_snapshot_RNINELF[10]\ : MX2C - port map(A => nb_snapshot_param(10), B => - \counter_points_snapshot[10]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[21]\); - - \data_out[85]\ : DFN1C0 - port map(D => \sample_f0_wdata[21]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(85)); - - \counter_points_snapshot_RNIHO97[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un4_data_in_validlt30_6); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[3]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I159_Y : OR2B - port map(A => N555, B => N547, Y => N611); - - \counter_points_snapshot_RNIDTOE[16]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - \data_out_RNO[85]\ : NOR2B - port map(A => sample_f0_58, B => data_shaping_R0_0, Y => - \sample_f0_wdata[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => \sample_f0_wdata[45]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(109)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_un1_Y : - OR2A - port map(A => N533, B => N589, Y => I198_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : AOI1B - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_counter_points_snapshot[19]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N511); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I192_Y : OAI1 - port map(A => N581, B => N588, C => N580, Y => N644); - - \data_out_RNO[111]\ : MX2 - port map(A => sample_f0_0, B => sample_f0_32, S => - data_shaping_R0, Y => \sample_f0_wdata[47]\); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[23]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[21]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot_RNIDTJE[19]\ : NOR3A - port map(A => un4_data_in_validlt30_10, B => - \counter_points_snapshot[20]_net_1\, C => - \counter_points_snapshot[19]_net_1\, Y => - un4_data_in_validlt30_20); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[16]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I73_Y : OA1B - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[22]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => N516); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : AOI1 - port map(A => N556, B => N549, C => N548, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f0_wdata_83, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(147)); - - \counter_points_snapshot_RNI11JG[5]\ : MX2C - port map(A => nb_snapshot_param(5), B => - \counter_points_snapshot[5]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[26]\); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f0_wdata_87, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(151)); - - \data_out_RNO[83]\ : NOR2B - port map(A => sample_f0_60, B => data_shaping_R0_0, Y => - \sample_f0_wdata[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I67_Y : AO1D - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[18]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N510); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => \sample_f0_wdata[23]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(87)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I43_Y : OA1B - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[7]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N486); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f0_wdata_89, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(153)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I283_Y_0_0, B => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I109_Y : NOR2B - port map(A => N496, B => N492, Y => N555); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR3C - port map(A => I222_un1_Y, B => N620, C => I259_un1_Y, Y => - N756); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_P0N : OR2A - port map(A => \un1_counter_points_snapshot[10]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N444); - - \counter_points_snapshot_RNI5VKS[0]\ : NOR3C - port map(A => un4_data_in_validlt30_2, B => - un4_data_in_validlt30_1, C => un4_data_in_validlt30_15, Y - => un4_data_in_validlt30_23); - - counter_points_snapshot_0_sqmuxa_1 : OR2A - port map(A => \data_out_valid_0_sqmuxa\, B => burst_f0, Y - => \counter_points_snapshot_0_sqmuxa_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AOI1B - port map(A => \un1_counter_points_snapshot[29]\, B => - \un1_counter_points_snapshot[28]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : AOI1 - port map(A => N529, B => N526, C => ADD_32x32_fast_I142_Y_0, - Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I307_Y_0_0); - - \data_out_RNO[91]\ : NOR2B - port map(A => sample_f0_52, B => data_shaping_R0_0, Y => - \sample_f0_wdata[27]\); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f0_wdata_55, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : AOI1B - port map(A => N479, B => N476, C => ADD_32x32_fast_I250_Y_0, - Y => ADD_32x32_fast_I250_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I53_Y : AO1A - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot[12]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N496); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_un1_Y : - NOR3C - port map(A => N623, B => N639, C => N654, Y => I260_un1_Y); - - \data_out_RNO[102]\ : MX2 - port map(A => sample_f0_9, B => sample_f0_41, S => - data_shaping_R0, Y => \sample_f0_wdata[38]\); - - \counter_points_snapshot_RNIF1PE[25]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AOI1B - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[22]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N515); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => nb_snapshot_param(7), B => - \un1_data_out_valid_0_sqmuxa_2[7]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_283); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_285, Y => - \counter_points_snapshot_10[9]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I291_Y_0_0); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f0_wdata_5, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f0_wdata_65, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I77_Y : OA1B - port map(A => \un1_counter_points_snapshot[23]\, B => - \un1_counter_points_snapshot[24]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N520); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I112_Y : AO1 - port map(A => N499, B => N496, C => N495, Y => N558); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y_0 : - OR2 - port map(A => N611, B => N627, Y => - ADD_32x32_fast_I254_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : AOI1B - port map(A => N548, B => N541, C => ADD_32x32_fast_I251_Y_1, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f0_wdata_75, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[25]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[25]_net_1\); - - \counter_points_snapshot_RNIVSIG[4]\ : MX2C - port map(A => nb_snapshot_param(4), B => - \counter_points_snapshot[4]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[27]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I48_Y : OR2B - port map(A => N446_i, B => N443_i, Y => N491); - - \data_out_RNO[82]\ : NOR2B - port map(A => sample_f0_61, B => data_shaping_R0, Y => - \sample_f0_wdata[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : AOI1 - port map(A => N521, B => N518, C => ADD_32x32_fast_I134_Y_0, - Y => N580); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[20]\, B => N783, - C => \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y - => N780_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : AO1C - port map(A => \un1_counter_points_snapshot[30]\, B => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, C => N380, Y => - N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : AO1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[6]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N485); - - un1_counter_points_snapshot_0_sqmuxa_1 : AO1B - port map(A => \counter_points_snapshot_3_sqmuxa\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => enable_f0, Y - => un1_counter_points_snapshot_0_sqmuxa_1_i); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f0_wdata_11, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(75)); - - \counter_points_snapshot_RNI59JG[7]\ : MX2C - port map(A => nb_snapshot_param(7), B => - \counter_points_snapshot[7]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[24]\); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f0_wdata_4, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(68)); - - \counter_points_snapshot_RNIR0A7[24]\ : NOR2 - port map(A => \counter_points_snapshot[24]_net_1\, B => - \counter_points_snapshot[25]_net_1\, Y => - un4_data_in_validlt30_11); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[14]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : AO1B - port map(A => \un1_data_out_valid_0_sqmuxa_1_3[31]\, B => - \un1_counter_points_snapshot[12]\, C => I50_un1_Y_i, Y - => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OA1C - port map(A => N564, B => N557, C => N556, Y => N620); - - \counter_points_snapshot_RNIFMFM3[10]\ : NOR3C - port map(A => un4_data_in_validlt30_26, B => - un4_data_in_validlt30_25, C => un4_data_in_validlt30_27, - Y => un4_data_in_validlto30_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : AO1B - port map(A => ADD_32x32_fast_I264_un1_Y_0, B => N631, C => - ADD_32x32_fast_I264_Y_0, Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768_i, B => ADD_32x32_fast_I296_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[16]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I57_Y : AO1D - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N500); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_P0N : OR2A - port map(A => \un1_counter_points_snapshot[9]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N447); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : AO1A - port map(A => N566, B => N559, C => N558, Y => N622); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I125_Y : OR2B - port map(A => N512, B => N508, Y => N571); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I214_un1_Y : - OR3B - port map(A => N549, B => N628, C => N557, Y => I214_un1_Y); - - \counter_points_snapshot_RNIC1PE[22]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[22]_net_1\, Y => - \un1_counter_points_snapshot[9]\); - - data_out_valid_RNO : MX2A - port map(A => un1_enable_2, B => sample_f0_val_0, S => - counter_points_snapshot_0_sqmuxa_i, Y => - data_out_valid_19); - - \data_out[100]\ : DFN1C0 - port map(D => \sample_f0_wdata[36]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : OR3C - port map(A => I262_un1_Y, B => N626, C => I228_un1_Y, Y => - N762); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : - AO1D - port map(A => N_43, B => N485, C => N481, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f0_wdata_13, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f0_wdata_82, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_278, Y => - \counter_points_snapshot_10[2]\); - - \counter_points_snapshot_RNI9HJG[9]\ : MX2C - port map(A => nb_snapshot_param(9), B => - \counter_points_snapshot[9]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : AO1 - port map(A => N582, B => N575, C => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1C - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[13]\); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f0_wdata_94, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(158)); - - \data_out_RNO[105]\ : MX2 - port map(A => sample_f0_6, B => sample_f0_38, S => - data_shaping_R0, Y => \sample_f0_wdata[41]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I95_Y_0 : AOI1 - port map(A => \counter_points_snapshot[29]_net_1\, B => - \counter_points_snapshot[28]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I95_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I62_Y_0 : OA1A - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[17]\, C => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N505); - - \counter_points_snapshot_RNIBTOE[14]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[14]_net_1\, Y => - \un1_counter_points_snapshot[17]\); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f0_wdata_0, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I286_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I151_Y : NOR2B - port map(A => N547, B => N539, Y => N603); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_12_1 is - - port( sample_f2_wdata : in std_logic_vector(95 downto 0); - data_f2_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0); - rstn : in std_logic; - lclk_c : in std_logic; - data_f2_out_valid : out std_logic; - I_9_31 : in std_logic; - I_45_11 : in std_logic; - I_52_11 : in std_logic; - I_38_12 : in std_logic; - N_4 : in std_logic; - I_56_12 : in std_logic; - I_24_16 : in std_logic; - I_5_31 : in std_logic; - I_20_23 : in std_logic; - I_13_35 : in std_logic; - I_31_15 : in std_logic; - start_snapshot_f2 : in std_logic; - sample_f2_val : in std_logic; - enable_f2 : in std_logic; - burst_f2 : in std_logic - ); - -end lpp_waveform_snapshot_160_12_1; - -architecture DEF_ARCH of lpp_waveform_snapshot_160_12_1 is - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal counter_points_snapshot_0_sqmuxa_1_0, - \counter_points_snapshot_0_sqmuxa_1_0_a2_0\, N_47_2, - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, N_59, - N_47_1, N_47_0, ADD_32x32_fast_I311_Y_0_0, - \un1_counter_points_snapshot[0]\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I250_Y_3, N618, N603, - ADD_32x32_fast_I250_Y_2, N539, N546, - ADD_32x32_fast_I250_Y_1, N479, N476, - ADD_32x32_fast_I250_Y_0, \un1_counter_points_snapshot[1]\, - \un1_counter_points_snapshot[2]\, - ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, - ADD_32x32_fast_I310_Y_0_0, ADD_32x32_fast_I253_Y_0_0, - N481, N485, ADD_32x32_fast_I295_Y_0_0, - \un1_counter_points_snapshot[16]\, - ADD_32x32_fast_I250_un1_Y_0, N619, - ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, ADD_32x32_fast_I251_Y_2, - N541, N548, ADD_32x32_fast_I251_Y_1, N478, - ADD_32x32_fast_I251_Y_0, ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I253_Y_0_a2_0, N_43, N486, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot[5]\, - ADD_32x32_fast_I309_Y_0_0, ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I300_Y_0_0, - \un1_counter_points_snapshot[11]\, - ADD_32x32_fast_I254_Y_0, N554, N547, - ADD_32x32_fast_I302_Y_0_0, - \un1_counter_points_snapshot[9]\, - ADD_32x32_fast_I294_Y_0_0, - \un1_counter_points_snapshot[17]\, - ADD_32x32_fast_I251_un1_Y_0, N_8, ADD_32x32_fast_I111_Y_0, - N565, ADD_32x32_fast_I255_Y_0, N556, N549, - ADD_32x32_fast_I252_Y_1, N550, N543, - ADD_32x32_fast_I252_Y_0, N483, N480, - ADD_32x32_fast_I256_Y_0, N558, N551, - ADD_32x32_fast_I259_Y_0, N620, N636, - ADD_32x32_fast_I255_un1_Y_3, ADD_32x32_fast_I255_un1_Y_1, - ADD_32x32_fast_I255_un1_Y_0, - \un1_counter_points_snapshot[20]\, - \un1_counter_points_snapshot[21]\, - \un1_counter_points_snapshot[18]\, - ADD_32x32_fast_I301_Y_0_0, - \un1_counter_points_snapshot[10]\, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I256_un1_Y_1, N512, N516, N567, - ADD_32x32_fast_I293_Y_0_0, ADD_32x32_fast_I252_un1_Y_0, - N496, N500, ADD_32x32_fast_I284_Y_0_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I262_un1_Y_0, ADD_32x32_fast_I133_Y_0, - ADD_32x32_fast_I262_un1_Y_2, ADD_32x32_fast_I264_Y_0, - N380, N582, N590, ADD_32x32_fast_I282_Y_0_0, - \un1_counter_points_snapshot[29]\, - ADD_32x32_fast_I103_Y_0, - \un1_counter_points_snapshot[24]\, - \un1_counter_points_snapshot[23]\, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot[26]\, - ADD_32x32_fast_I126_Y_1, N413, ADD_32x32_fast_I134_Y_1, - \un1_counter_points_snapshot[22]\, - ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I119_Y_1, ADD_32x32_fast_I119_Y_0, - ADD_32x32_fast_I118_Y_1, ADD_32x32_fast_I118_Y_0, - ADD_32x32_fast_I262_un1_Y_2_tz_0, - \un1_counter_points_snapshot[28]\, data_out_valid_9_i_0, - un1_data_in_validlt30_27, un1_data_in_validlt30_18, - un1_data_in_validlt30_17, un1_data_in_validlt30_23, - un1_data_in_validlt30_26, un1_data_in_validlt30_12, - un1_data_in_validlt30_11, un1_data_in_validlt30_22, - un1_data_in_validlt30_25, un1_data_in_validlt30_8, - un1_data_in_validlt30_7, un1_data_in_validlt30_20, - un1_data_in_validlt30_2, un1_data_in_validlt30_1, - un1_data_in_validlt30_15, un1_data_in_validlt30_14, - \counter_points_snapshot[28]_net_1\, - \counter_points_snapshot[27]_net_1\, - un1_data_in_validlt30_10, - \counter_points_snapshot[20]_net_1\, - \counter_points_snapshot[19]_net_1\, - un1_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un1_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[18]_net_1\, - \counter_points_snapshot[29]_net_1\, - \counter_points_snapshot[30]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[26]_net_1\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[21]_net_1\, - \counter_points_snapshot[22]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[14]_net_1\, - \counter_points_snapshot[15]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[13]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, - \counter_points_snapshot_10_12_i_o2_0\, N572, N410, N416, - \un1_data_out_valid_0_sqmuxa_2[3]\, N594, - \un1_data_out_valid_0_sqmuxa_2[4]\, N529, N533, N764, - N644, N628, N588, N766, N566, N574, N_63, N652, - \un1_data_out_valid_0_sqmuxa_2[5]\, N654, - \un1_data_out_valid_0_sqmuxa_2[10]\, N786_i, N758, N638, - N622, N443, N440, N497, - \un1_data_out_valid_0_sqmuxa_2[11]\, N783, N580, - \un1_data_out_valid_0_sqmuxa_2[7]\, N650, - \un1_data_out_valid_0_sqmuxa_2[2]\, N738, N771, - I258_un1_Y, N635, N754, I220_un1_Y, I255_un1_Y_i, N613, - N748, I214_un1_Y, \un1_data_out_valid_0_sqmuxa_2[8]\, - N648_i, \un1_data_out_valid_0_sqmuxa_2[6]\, N740, - I206_un1_Y, I251_un1_Y, N605, N774, N750, I216_un1_Y, - I256_un1_Y, N615, N789, un1_data_in_validlto30_i, N_52, - N_60, N_49, counter_points_snapshot_0_sqmuxa_1, - I262_un1_Y, N627, N762_i, N626, I228_un1_Y, N_47, N742, - I208_un1_Y, I252_un1_Y_i, N607, N777, N744, N752, N746, - I212_un1_Y, I254_un1_Y, N611, - \un1_data_out_valid_0_sqmuxa_2[9]\, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, - ADD_32x32_fast_I262_un1_Y_2_tz, N508, N563, N555, N571, - N642, N586, I182_un1_Y, N507, N_11, - \counter_points_snapshot_RNO[18]_net_1\, - \counter_points_snapshot_10[3]\, N_20, - counter_points_snapshot_2_sqmuxa_i, N386, N527, N531, - N383, \counter_points_snapshot_10[4]\, N_21, - \counter_points_snapshot_RNO[17]_net_1\, N504, N499, N492, - N488, N491, N487, N456, N459, N489, N_22, - \counter_points_snapshot_10[5]\, N515, N570, N437, - \counter_points_snapshot_10[10]\, N_27, - \counter_points_snapshot_RNO[21]_net_1\, - \counter_points_snapshot_RNO[22]_net_1\, - \counter_points_snapshot_10[11]\, N_28, N503, N519, N523, - \counter_points_snapshot_10[7]\, N_24, N562, - \un1_counter_points_snapshot[31]\, N634, N760_i, N_23, - N_25, \counter_points_snapshot_10[6]\, - \counter_points_snapshot_10[8]\, - \counter_points_snapshot[31]_net_1\, - \counter_points_snapshot_RNO[20]_net_1\, - \counter_points_snapshot_RNO[23]_net_1\, N_31, N_35, N_45, - N_15, N768_i, N_13, N_43_0, N_33, - \counter_points_snapshot_RNO[19]_net_1\, N_41, N_7, - N780_i, N_39, N_37, N_9, N_26, - \counter_points_snapshot_10[9]\, N_18, - \counter_points_snapshot_10[1]\, - \un1_data_out_valid_0_sqmuxa_2[0]\, N_17, N_19, - \counter_points_snapshot_10[0]\, - \counter_points_snapshot_10[2]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_0 : - AO1C - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[18]\, C => N_47_0, Y => - ADD_32x32_fast_I255_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y : - OR3B - port map(A => N613, B => ADD_32x32_fast_I255_un1_Y_3, C => - N786_i, Y => I255_un1_Y_i); - - \counter_points_snapshot_RNI1G36[25]\ : NOR2 - port map(A => \counter_points_snapshot[25]_net_1\, B => - \counter_points_snapshot[26]_net_1\, Y => - un1_data_in_validlt30_12); - - \counter_points_snapshot_RNIBPKE[24]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => N_9, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : AX1D - port map(A => N529, B => N533, C => - ADD_32x32_fast_I284_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - \counter_points_snapshot_RNIPF36[21]\ : NOR2 - port map(A => \counter_points_snapshot[21]_net_1\, B => - \counter_points_snapshot[22]_net_1\, Y => - un1_data_in_validlt30_10); - - \data_out[110]\ : DFN1C0 - port map(D => sample_f2_wdata(46), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(110)); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => I_56_12, B => - \un1_data_out_valid_0_sqmuxa_2[10]\, S => N_60, Y => N_27); - - \counter_points_snapshot_RNO[27]\ : XA1C - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - N_52, Y => N_37); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => N_39, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[28]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I216_un1_Y : OA1 - port map(A => N566, B => N574, C => N615, Y => I216_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y_0 : - NOR3C - port map(A => N496, B => N500, C => N567, Y => - ADD_32x32_fast_I252_un1_Y_0); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762_i, B => ADD_32x32_fast_I299_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[19]_net_1\); - - \counter_points_snapshot_RNITAJL[6]\ : MX2C - port map(A => I_31_15, B => - \counter_points_snapshot[6]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[25]\); - - \data_out[91]\ : DFN1C0 - port map(D => sample_f2_wdata(27), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(91)); - - \counter_points_snapshot_RNIS7BQ2_0[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_1); - - \counter_points_snapshot_RNICPKE[25]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_a2_0 : - OR2 - port map(A => N_43, B => N486, Y => - ADD_32x32_fast_I253_Y_0_a2_0); - - \counter_points_snapshot_RNI747C[27]\ : NOR3A - port map(A => un1_data_in_validlt30_14, B => - \counter_points_snapshot[28]_net_1\, C => - \counter_points_snapshot[27]_net_1\, Y => - un1_data_in_validlt30_22); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f2_wdata(56), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1B - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - N_52, Y => N_31); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I93_Y : NOR2B - port map(A => N480, B => N476, Y => N539); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : OR3C - port map(A => I212_un1_Y, B => ADD_32x32_fast_I254_Y_0, C - => I254_un1_Y, Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : OR2 - port map(A => N586, B => I182_un1_Y, Y => N642); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I101_Y : NOR3C - port map(A => N456, B => N459, C => N488, Y => N547); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f2_wdata(66), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => sample_f2_wdata(40), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : OR2 - port map(A => N491, B => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => I_20_23, B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_21); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I111_Y_0 : AO1B - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot[10]\, C => N_47_1, Y => - ADD_32x32_fast_I111_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I167_Y : NOR2B - port map(A => N563, B => N555, Y => N619); - - \counter_points_snapshot_RNIS7BQ2[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_0); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => I_5_31, B => - \un1_data_out_valid_0_sqmuxa_2[1]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_18); - - \data_out[102]\ : DFN1C0 - port map(D => sample_f2_wdata(38), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I64_Y : OA1C - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_counter_points_snapshot[18]\, C => N_47_2, Y => N507); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3C - port map(A => I208_un1_Y, B => ADD_32x32_fast_I252_Y_1, C - => I252_un1_Y_i, Y => N742); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[29]\, B => - N_47_1, Y => ADD_32x32_fast_I282_Y_0_0); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_24, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[2]\, B => N_47_0, - Y => ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1B - port map(A => N780_i, B => ADD_32x32_fast_I292_Y_0_0, C => - N_52, Y => N_7); - - \counter_points_snapshot_RNI2K36[29]\ : NOR2 - port map(A => \counter_points_snapshot[29]_net_1\, B => - \counter_points_snapshot[30]_net_1\, Y => - un1_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : AO1 - port map(A => N650, B => N635, C => N634, Y => N771); - - \data_out[93]\ : DFN1C0 - port map(D => sample_f2_wdata(29), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(93)); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[4]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_1 : - OAI1 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[20]\, C => N_47_0, Y => - ADD_32x32_fast_I255_un1_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I33_Y : OAI1 - port map(A => \un1_counter_points_snapshot[1]\, B => - \un1_counter_points_snapshot[2]\, C => N_47_2, Y => N476); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - N_47_0, Y => ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f2_wdata(95), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => sample_f2_wdata(41), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(105)); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f2_wdata(77), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_un1_Y_0 : - NOR3C - port map(A => N_8, B => ADD_32x32_fast_I111_Y_0, C => N565, - Y => ADD_32x32_fast_I251_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR3A - port map(A => N440, B => N437, C => N491, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2 - port map(A => N527, B => N523, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => sample_f2_wdata(17), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(81)); - - counter_points_snapshot_10_12_i_o2 : OR2B - port map(A => \counter_points_snapshot_10_12_i_o2_0\, B => - N_60, Y => N_52); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[1]\, B => N_47_0, - Y => ADD_32x32_fast_I310_Y_0_0); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : AO1 - port map(A => N558, B => N551, C => N550, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[16]\, B => N_47, - C => N771, Y => N768_i); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f2_wdata(50), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I97_Y : NOR3C - port map(A => N456, B => N459, C => N480, Y => N543); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : OR2 - port map(A => N570, B => I182_un1_Y, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : OR2 - port map(A => N507, B => N503, Y => N566); - - \counter_points_snapshot_RNIVDS1[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un1_data_in_validlt30_1); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => N_37, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f2_wdata(79), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : NOR2A - port map(A => N380, B => N590, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3C - port map(A => N443, B => N440, C => N497, Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f2_wdata(48), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f2_wdata(60), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(124)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I65_Y : AO1C - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_counter_points_snapshot[18]\, C => N_47_2, Y => N508); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f2_wdata(70), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : AOI1 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[25]\, C => N_47, Y => N523); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I11_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[20]\, B => N_47, - Y => N413); - - \counter_points_snapshot_RNO[28]\ : XA1B - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - N_52, Y => N_39); - - \data_out[83]\ : DFN1C0 - port map(D => sample_f2_wdata(19), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : OA1A - port map(A => N539, B => N546, C => ADD_32x32_fast_I250_Y_1, - Y => ADD_32x32_fast_I250_Y_2); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f2_wdata(58), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f2_wdata(51), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(115)); - - \counter_points_snapshot_RNIATKE[30]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[30]_net_1\, Y => - \un1_counter_points_snapshot[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : OA1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[8]\, C => N_47_2, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : - OA1C - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[5]\, C => N_47, Y => N481); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y : - NOR3 - port map(A => ADD_32x32_fast_I262_un1_Y_0, B => N594, C => - N627, Y => I262_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[17]\, C => N_47_1, Y => - ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f2_wdata(68), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(132)); - - \counter_points_snapshot_RNI54EO[23]\ : NOR3C - port map(A => un1_data_in_validlt30_12, B => - un1_data_in_validlt30_11, C => un1_data_in_validlt30_22, - Y => un1_data_in_validlt30_26); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => N_43_0, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[30]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I37_Y : AO1C - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[3]\, C => N_47, Y => N480); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I228_un1_Y : - NOR2A - port map(A => N642, B => N627, Y => I228_un1_Y); - - \counter_points_snapshot_RNI7LKE[13]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[13]_net_1\, Y => - \un1_counter_points_snapshot[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_un1_Y : - OR3C - port map(A => N605, B => ADD_32x32_fast_I251_un1_Y_0, C => - N774, Y => I251_un1_Y); - - \counter_points_snapshot_RNIBTKE[31]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[31]_net_1\, Y => - \un1_counter_points_snapshot[0]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I69_Y : OAI1 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[20]\, C => N_47_2, Y => N512); - - \data_out[96]\ : DFN1C0 - port map(D => sample_f2_wdata(32), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(96)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : OR3C - port map(A => I214_un1_Y, B => ADD_32x32_fast_I255_Y_0, C - => I255_un1_Y_i, Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - N_47_0, Y => ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f2_wdata(61), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(125)); - - \counter_points_snapshot_RNIS7BQ2_2[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y_1 : - NOR3C - port map(A => N512, B => N516, C => N567, Y => - ADD_32x32_fast_I256_un1_Y_1); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f2_wdata(71), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(135)); - - \counter_points_snapshot_RNIGPKE[29]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[29]_net_1\, Y => - \un1_counter_points_snapshot[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : OA1B - port map(A => N752, B => ADD_32x32_fast_I253_Y_0_a2_0, C - => ADD_32x32_fast_I253_Y_0_0, Y => N744); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y : NOR2 - port map(A => ADD_32x32_fast_I119_Y_1, B => - ADD_32x32_fast_I119_Y_0, Y => N565); - - data_out_valid : DFN1C0 - port map(D => N_49, CLK => lclk_c, CLR => rstn, Q => - data_f2_out_valid); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : AO1 - port map(A => N570, B => N563, C => N562, Y => N626); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f2_wdata(7), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f2_wdata(1), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[18]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : OR3B - port map(A => N654, B => N638, C => N622, Y => N758); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I45_Y : AO1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => N_47_2, Y => N488); - - \data_out[86]\ : DFN1C0 - port map(D => sample_f2_wdata(22), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(86)); - - \counter_points_snapshot_RNITTM8[0]\ : NOR3C - port map(A => un1_data_in_validlt30_2, B => - un1_data_in_validlt30_1, C => un1_data_in_validlt30_15, Y - => un1_data_in_validlt30_23); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : AO1 - port map(A => N562, B => N555, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f2_wdata(86), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(150)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_0, Y => ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - N_47_0, Y => ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f2_wdata(84), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(148)); - - GND_i : GND - port map(Y => \GND\); - - \counter_points_snapshot_RNI59K92[6]\ : NOR3C - port map(A => un1_data_in_validlt30_26, B => - un1_data_in_validlt30_25, C => un1_data_in_validlt30_27, - Y => un1_data_in_validlto30_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I49_Y : AO1B - port map(A => \un1_counter_points_snapshot[10]\, B => - \un1_counter_points_snapshot[9]\, C => N_47_2, Y => N492); - - \counter_points_snapshot_RNI3US1[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un1_data_in_validlt30_2); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[8]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I61_Y : AO1C - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[15]\, C => N_47_2, Y => N504); - - \counter_points_snapshot_RNICB6O[8]\ : MX2 - port map(A => I_45_11, B => - \counter_points_snapshot[8]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[23]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR2 - port map(A => N523, B => N519, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f2_wdata(9), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(73)); - - \counter_points_snapshot_RNIRHT4[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un1_data_in_validlt30_15); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_3 : AOI1B - port map(A => N618, B => N603, C => ADD_32x32_fast_I250_Y_2, - Y => ADD_32x32_fast_I250_Y_3); - - \data_out[92]\ : DFN1C0 - port map(D => sample_f2_wdata(28), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f2_wdata(3), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => sample_f2_wdata(43), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(107)); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_23, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : XNOR3 - port map(A => \un1_counter_points_snapshot[21]\, B => - N_47_1, C => N786_i, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I220_un1_Y : - NOR2B - port map(A => N634, B => N619, Y => I220_un1_Y); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => N_41, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[29]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I183_Y : NOR3C - port map(A => N516, B => ADD_32x32_fast_I133_Y_0, C => N571, - Y => N635); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[11]\, B => - N_47_0, Y => ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1B - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - N_52, Y => N_33); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[20]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[9]\, B => N_47_0, - Y => ADD_32x32_fast_I302_Y_0_0); - - \counter_points_snapshot_RNIALKE[16]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y_1 : OA1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[16]\, C => N_47_1, Y => - ADD_32x32_fast_I119_Y_1); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[17]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : OR2 - port map(A => N386, B => N383, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - N_47_0, Y => ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : AO1B - port map(A => ADD_32x32_fast_I250_un1_Y_0, B => N771, C => - ADD_32x32_fast_I250_Y_3, Y => N738); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I212_un1_Y : - OR2B - port map(A => N626, B => N611, Y => I212_un1_Y); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f2_wdata(90), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(154)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - AOI1B - port map(A => N_8, B => N764, C => N497, Y => N760_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_un1_Y : - NOR3C - port map(A => N619, B => N635, C => N650, Y => I258_un1_Y); - - \data_out[82]\ : DFN1C0 - port map(D => sample_f2_wdata(18), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f2_wdata(53), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1B - port map(A => N760_i, B => ADD_32x32_fast_I300_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : AOI1B - port map(A => N554, B => N547, C => N546, Y => - ADD_32x32_fast_I254_Y_0); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f2_wdata(12), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f2_wdata(88), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(152)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I133_Y_0 : AO1C - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_counter_points_snapshot[23]\, C => N_47_1, Y => - ADD_32x32_fast_I133_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_1 : OA1C - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[15]\, C => N_47_1, Y => - ADD_32x32_fast_I118_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y : - OR3B - port map(A => N611, B => N783, C => N627, Y => I254_un1_Y); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f2_wdata(85), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(149)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f2_wdata(63), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : OR2B - port map(A => N654, B => N638, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : OR2 - port map(A => N652, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2 - port map(A => N588, B => N533, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f2_wdata(73), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : OR2 - port map(A => N531, B => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f2_wdata(91), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(155)); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_22, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1C - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[17]_net_1\); - - \counter_points_snapshot_RNI9Q3F[1]\ : MX2C - port map(A => I_5_31, B => - \counter_points_snapshot[1]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[30]\); - - data_out_valid_RNO_0 : NOR2B - port map(A => enable_f2, B => sample_f2_val, Y => - data_out_valid_9_i_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I121_Y : NOR2B - port map(A => N508, B => N504, Y => N567); - - \data_out[90]\ : DFN1C0 - port map(D => sample_f2_wdata(26), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR3 - port map(A => N413, B => N416, C => N507, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR3C - port map(A => ADD_32x32_fast_I251_Y_2, B => I206_un1_Y, C - => I251_un1_Y, Y => N740); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_un1_Y_0 : - NOR2B - port map(A => N603, B => N619, Y => - ADD_32x32_fast_I250_un1_Y_0); - - \counter_points_snapshot_RNILRFP[9]\ : MX2 - port map(A => I_52_11, B => - \counter_points_snapshot[9]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[22]\); - - \counter_points_snapshot_RNO[14]\ : XA1C - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - N_52, Y => N_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_G0N : OR2A - port map(A => \un1_counter_points_snapshot[11]\, B => N_47, - Y => N440); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR2 - port map(A => N519, B => N515, Y => I182_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I282_Y_0_0, B => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - counter_points_snapshot_2_sqmuxa_0_a2 : OR3A - port map(A => enable_f2, B => burst_f2, C => N_60, Y => - counter_points_snapshot_2_sqmuxa_i); - - \data_out[99]\ : DFN1C0 - port map(D => sample_f2_wdata(35), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(99)); - - \counter_points_snapshot_RNILR6C[19]\ : NOR3A - port map(A => un1_data_in_validlt30_10, B => - \counter_points_snapshot[20]_net_1\, C => - \counter_points_snapshot[19]_net_1\, Y => - un1_data_in_validlt30_20); - - \counter_points_snapshot_RNI6LKE[12]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I76_Y : OA1C - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_counter_points_snapshot[23]\, C => N_47, Y => N519); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I95_Y : NOR2 - port map(A => N_43, B => N478, Y => N541); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : NOR3 - port map(A => I220_un1_Y, B => N618, C => I258_un1_Y, Y => - N754); - - \data_out[106]\ : DFN1C0 - port map(D => sample_f2_wdata(42), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1C - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[21]_net_1\); - - \counter_points_snapshot_RNIL736[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un1_data_in_validlt30_6); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_0 : AO1 - port map(A => \un1_counter_points_snapshot[1]\, B => - \un1_counter_points_snapshot[2]\, C => N_47_0, Y => - ADD_32x32_fast_I250_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y_0 : NOR3A - port map(A => N380, B => N582, C => N590, Y => - ADD_32x32_fast_I264_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y_2_tz : - NOR3 - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[26]\, C => - ADD_32x32_fast_I262_un1_Y_2_tz_0, Y => - ADD_32x32_fast_I262_un1_Y_2_tz); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y : - NOR3C - port map(A => N615, B => ADD_32x32_fast_I256_un1_Y_1, C => - N789, Y => I256_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : OR3 - port map(A => N413, B => N416, C => N515, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => sample_f2_wdata(34), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(98)); - - \data_out[80]\ : DFN1C0 - port map(D => sample_f2_wdata(16), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f2_wdata(8), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : NOR3 - port map(A => I216_un1_Y, B => ADD_32x32_fast_I256_Y_0, C - => I256_un1_Y, Y => N750); - - \counter_points_snapshot_RNIT736[16]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un1_data_in_validlt30_8); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I35_Y : OA1A - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_counter_points_snapshot[2]\, C => N_47, Y => N478); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AOI1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47_2, Y => N499); - - \counter_points_snapshot_RNIIA0J[4]\ : MX2C - port map(A => I_20_23, B => - \counter_points_snapshot[4]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[27]\); - - \counter_points_snapshot_RNI9LKE[15]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[15]_net_1\, Y => - \un1_counter_points_snapshot[16]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[23]\, C => N648_i, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - counter_points_snapshot_2_sqmuxa_0_a2_0 : OR2A - port map(A => start_snapshot_f2, B => sample_f2_val, Y => - N_60); - - \data_out[89]\ : DFN1C0 - port map(D => sample_f2_wdata(25), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(89)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : OR3 - port map(A => N644, B => N628, C => N533, Y => N764); - - counter_points_snapshot_0_sqmuxa_1_0_a2 : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0_a2_0\, - B => burst_f2, Y => counter_points_snapshot_0_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR3 - port map(A => \un1_counter_points_snapshot[22]\, B => - N_47_1, C => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f2_wdata(52), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(116)); - - \counter_points_snapshot_RNI9PKE[22]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[22]_net_1\, Y => - \un1_counter_points_snapshot[9]\); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[19]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => I_9_31, B => - \un1_data_out_valid_0_sqmuxa_2[2]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_19); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - N_47_0, Y => ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : OR2A - port map(A => N594, B => N586, Y => N650); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[26]\, C => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1B - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[18]_net_1\); - - \data_out[88]\ : DFN1C0 - port map(D => sample_f2_wdata(24), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XNOR2 - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f2_wdata(62), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => sample_f2_wdata(30), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f2_wdata(76), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f2_wdata(72), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(136)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[18]\, B => - N_47_1, Y => ADD_32x32_fast_I293_Y_0_0); - - \un1_data_out_valid_0_sqmuxa_1_i_0[31]\ : AOI1B - port map(A => start_snapshot_f2, B => burst_f2, C => - sample_f2_val, Y => - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\); - - \counter_points_snapshot_RNIP736[14]\ : NOR2 - port map(A => \counter_points_snapshot[14]_net_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - un1_data_in_validlt30_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I208_un1_Y : - OR2B - port map(A => N622, B => N607, Y => I208_un1_Y); - - \counter_points_snapshot_RNIDPKE[26]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot[5]\); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[22]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[22]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : NOR2A - port map(A => N380, B => N531, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => N_47_0, - Y => ADD_32x32_fast_I304_Y_0_0); - - \data_out[101]\ : DFN1C0 - port map(D => sample_f2_wdata(37), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(101)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I102_Y : OA1C - port map(A => N489, B => N486, C => N485, Y => N548); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I155_Y : NOR2B - port map(A => N551, B => N543, Y => N607); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f2_wdata(93), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_21, Y => - \counter_points_snapshot_10[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I163_Y : NOR3C - port map(A => N496, B => N500, C => N551, Y => N615); - - \counter_points_snapshot_RNO[30]\ : XA1C - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - N_52, Y => N_43_0); - - \counter_points_snapshot_RNIOVES[11]\ : MX2C - port map(A => N_4, B => \counter_points_snapshot[11]_net_1\, - S => counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[20]\); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : AO1 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => N_47_2, Y => N497); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR3A - port map(A => N572, B => ADD_32x32_fast_I118_Y_0, C => - ADD_32x32_fast_I118_Y_1, Y => N628); - - \counter_points_snapshot_RNIBBDO[14]\ : NOR3C - port map(A => un1_data_in_validlt30_8, B => - un1_data_in_validlt30_7, C => un1_data_in_validlt30_20, Y - => un1_data_in_validlt30_25); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[23]\, B => - \un1_counter_points_snapshot[25]\, C => N_47_1, Y => - ADD_32x32_fast_I134_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I117_Y : NOR2B - port map(A => N504, B => N500, Y => N563); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f2_wdata(6), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => I_24_16, B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_22); - - \data_out[84]\ : DFN1C0 - port map(D => sample_f2_wdata(20), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => sample_f2_wdata(39), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : AOI1 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[27]\, C => N_47_2, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - N_52, Y => N_35); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f2_wdata(15), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f2_wdata(80), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(144)); - - \counter_points_snapshot_RNINQ9K[5]\ : MX2C - port map(A => I_24_16, B => - \counter_points_snapshot[5]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[26]\); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0 : NOR2B - port map(A => start_snapshot_f2, B => sample_f2_val, Y => - \counter_points_snapshot_0_sqmuxa_1_0_a2_0\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I25_P0N : OR2A - port map(A => N_47_2, B => \un1_counter_points_snapshot[6]\, - Y => N456); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_25, Y => - \counter_points_snapshot_10[8]\); - - \counter_points_snapshot_RNILPOO[6]\ : NOR3C - port map(A => un1_data_in_validlt30_18, B => - un1_data_in_validlt30_17, C => un1_data_in_validlt30_23, - Y => un1_data_in_validlt30_27); - - \data_out[111]\ : DFN1C0 - port map(D => sample_f2_wdata(47), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I105_Y : NOR2B - port map(A => N492, B => N488, Y => N551); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[16]\, B => - N_47_0, Y => ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2A - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f2_wdata(78), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(142)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I26_P0N : OR2A - port map(A => N_47, B => \un1_counter_points_snapshot[5]\, - Y => N459); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f2_wdata(14), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[23]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I39_Y_i_o2 : - AO1B - port map(A => \un1_counter_points_snapshot[4]\, B => N_47, - C => N459, Y => N_43); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : OR2A - port map(A => N572, B => N580, Y => N636); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_1 : AO1A - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[24]\, C => N_47_1, Y => - ADD_32x32_fast_I134_Y_1); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => I_13_35, B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_20); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => N_35, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => N_47_0, - Y => ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : AOI1B - port map(A => N550, B => N543, C => ADD_32x32_fast_I252_Y_0, - Y => ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I206_un1_Y : - OR2B - port map(A => N620, B => N605, Y => I206_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I1_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[30]\, B => - N_47_2, Y => N383); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f2_wdata(57), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : OA1C - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[15]\, C => N_47, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_17, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f2_wdata(67), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f2_wdata(49), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(113)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f2_wdata(81), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(145)); - - \counter_points_snapshot_RNI4RSM[7]\ : MX2C - port map(A => I_38_12, B => - \counter_points_snapshot[7]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y_0 : OA1A - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[17]\, C => N_47_1, Y => - ADD_32x32_fast_I119_Y_0); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f2_wdata(2), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[1]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[9]\, C => N_47_1, Y => - ADD_32x32_fast_I103_Y_0); - - \counter_points_snapshot_RNO[31]\ : XA1B - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - N_52, Y => N_45); - - \counter_points_snapshot_RNO_0[0]\ : MX2B - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_17); - - \counter_points_snapshot_RNO[15]\ : XA1B - port map(A => N771, B => ADD_32x32_fast_I295_Y_0_0, C => - N_52, Y => N_13); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f2_wdata(59), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(123)); - - \counter_points_snapshot_RNI6F6C[10]\ : NOR3A - port map(A => un1_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un1_data_in_validlt30_18); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f2_wdata(69), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : OR2A - port map(A => \un1_counter_points_snapshot[10]\, B => - N_47_2, Y => N443); - - \counter_points_snapshot_RNIAPKE[23]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I153_Y : NOR2B - port map(A => N549, B => N541, Y => N605); - - \counter_points_snapshot_RNO[29]\ : XA1C - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - N_52, Y => N_41); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => N_45, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : OA1C - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[3]\, C => N_47, Y => N479); - - \counter_points_snapshot_RNIEQMH[3]\ : MX2C - port map(A => I_13_35, B => - \counter_points_snapshot[3]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[28]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I55_Y_i : AO1C - port map(A => \un1_counter_points_snapshot[12]\, B => - \counter_points_snapshot[18]_net_1\, C => N_47, Y => N_8); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I19_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - N_47_2, Y => N437); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f2_wdata(10), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(74)); - - \counter_points_snapshot_RNI8LKE[14]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[14]_net_1\, Y => - \un1_counter_points_snapshot[17]\); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_27, Y => - \counter_points_snapshot_10[10]\); - - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y_2_tz_0 : - OR2 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[25]\, Y => - ADD_32x32_fast_I262_un1_Y_2_tz_0); - - \data_out[108]\ : DFN1C0 - port map(D => sample_f2_wdata(44), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => I_31_15, B => - \un1_data_out_valid_0_sqmuxa_2[6]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_23); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f2_wdata(92), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(156)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_Y : NOR2 - port map(A => N644, B => N533, Y => N786_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_3 : - NOR3C - port map(A => ADD_32x32_fast_I255_un1_Y_1, B => - ADD_32x32_fast_I255_un1_Y_0, C => N565, Y => - ADD_32x32_fast_I255_un1_Y_3); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => I_45_11, B => - \un1_data_out_valid_0_sqmuxa_2[8]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_25); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_18, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_0, - Y => ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : OA1B - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_counter_points_snapshot[6]\, C => N_47, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - NOR2 - port map(A => N_63, B => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N_63, B => ADD_32x32_fast_I302_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[22]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y : NOR2 - port map(A => ADD_32x32_fast_I103_Y_0, B => N486, Y => N549); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => N_7, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => N_31, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[24]_net_1\); - - \data_out[95]\ : DFN1C0 - port map(D => sample_f2_wdata(31), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(95)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_0 : AOI1 - port map(A => N483, B => N480, C => N479, Y => - ADD_32x32_fast_I252_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y : - OR3C - port map(A => N607, B => ADD_32x32_fast_I252_un1_Y_0, C => - N777, Y => I252_un1_Y_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I196_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[24]\, B => N_47, - C => N650, Y => N648_i); - - \counter_points_snapshot_RNIBUT1[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un1_data_in_validlt30_4); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : NOR3 - port map(A => N410, B => N416, C => ADD_32x32_fast_I126_Y_1, - Y => N572); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => I_52_11, B => - \un1_data_out_valid_0_sqmuxa_2[9]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_26); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : AO1A - port map(A => N_47_1, B => - \un1_counter_points_snapshot[18]\, C => N413, Y => - ADD_32x32_fast_I126_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I116_Y : OR2 - port map(A => N503, B => N499, Y => N562); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_20, Y => - \counter_points_snapshot_10[3]\); - - \counter_points_snapshot_RNI8AQD[0]\ : MX2A - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[27]\, C => N_47_1, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f2_wdata(54), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(118)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR3A - port map(A => N380, B => N582, C => N590, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[5]\, B => N_47_0, - Y => ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : OA1A - port map(A => N481, B => N478, C => ADD_32x32_fast_I251_Y_0, - Y => ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2A - port map(A => N594, B => N642, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I175_Y : OR2B - port map(A => N571, B => N563, Y => N627); - - \counter_points_snapshot_RNIBLKE[17]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y_0 : - OR3B - port map(A => N516, B => ADD_32x32_fast_I133_Y_0, C => - ADD_32x32_fast_I262_un1_Y_2, Y => - ADD_32x32_fast_I262_un1_Y_0); - - \counter_points_snapshot_RNITF36[23]\ : NOR2 - port map(A => \counter_points_snapshot[23]_net_1\, B => - \counter_points_snapshot[24]_net_1\, Y => - un1_data_in_validlt30_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[24]\, C => N650, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[25]\, C => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - OA1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[9]\, C => N_47_2, Y => N489); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0 : XOR3 - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N783, Y => - \un1_data_out_valid_0_sqmuxa_2[11]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I100_Y : NOR2 - port map(A => N487, B => N483, Y => N546); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f2_wdata(64), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(128)); - - \counter_points_snapshot_RNO[11]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_28, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => sample_f2_wdata(33), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f2_wdata(74), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(138)); - - \counter_points_snapshot_RNIFPKE[28]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - \data_out[85]\ : DFN1C0 - port map(D => sample_f2_wdata(21), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[3]_net_1\); - - \counter_points_snapshot_RNI7PKE[20]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[20]_net_1\, Y => - \un1_counter_points_snapshot[11]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I159_Y : NOR2B - port map(A => N555, B => N547, Y => N611); - - \data_out[109]\ : DFN1C0 - port map(D => sample_f2_wdata(45), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(109)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y_0 : OR2 - port map(A => N620, B => N636, Y => ADD_32x32_fast_I259_Y_0); - - \counter_points_snapshot_RNIICR3[6]\ : NOR3A - port map(A => un1_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un1_data_in_validlt30_17); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I192_Y : OR2 - port map(A => N588, B => N580, Y => N644); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[23]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[21]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[16]_net_1\); - - \counter_points_snapshot_RNIG6OE2[31]\ : AO1D - port map(A => un1_data_in_validlto30_i, B => - \counter_points_snapshot[31]_net_1\, C => - start_snapshot_f2, Y => N_59); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I73_Y : AO1C - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[22]\, C => N_47, Y => N516); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : AOI1B - port map(A => N556, B => N549, C => N548, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f2_wdata(83), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(147)); - - \counter_points_snapshot_RNIDLKE[19]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f2_wdata(87), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(151)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y_2 : - NOR2A - port map(A => N_47_2, B => ADD_32x32_fast_I262_un1_Y_2_tz, - Y => ADD_32x32_fast_I262_un1_Y_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - N_47_0, Y => ADD_32x32_fast_I299_Y_0_0); - - \counter_points_snapshot_RNI8PKE[21]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[21]_net_1\, Y => - \un1_counter_points_snapshot[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => N_47_0, - Y => ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => sample_f2_wdata(23), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(87)); - - counter_points_snapshot_10_12_i_o2_0 : NOR2A - port map(A => enable_f2, B => burst_f2, Y => - \counter_points_snapshot_10_12_i_o2_0\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I43_Y : AOI1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[6]\, C => N_47_2, Y => N486); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f2_wdata(89), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(153)); - - \counter_points_snapshot_RNIBADG[2]\ : MX2 - port map(A => I_9_31, B => - \counter_points_snapshot[2]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[29]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[28]\, C => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I109_Y : NOR2B - port map(A => N496, B => N492, Y => N555); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR2 - port map(A => ADD_32x32_fast_I259_Y_0, B => N652, Y => N_63); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AO1D - port map(A => \un1_counter_points_snapshot[28]\, B => - N_47_2, C => N386, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : OR2 - port map(A => ADD_32x32_fast_I142_Y_0, B => N529, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => N_47_0, - Y => ADD_32x32_fast_I307_Y_0_0); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f2_wdata(55), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : AOI1B - port map(A => N479, B => N476, C => ADD_32x32_fast_I250_Y_0, - Y => ADD_32x32_fast_I250_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I53_Y : AO1C - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_counter_points_snapshot[11]\, C => N_47, Y => N496); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I10_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[21]\, B => - N_47_2, Y => N410); - - \counter_points_snapshot_RNIEPKE[27]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : OA1C - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[22]\, C => N_47, Y => N515); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I161_Y : NOR3C - port map(A => N_8, B => ADD_32x32_fast_I111_Y_0, C => N549, - Y => N613); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => I_38_12, B => - \un1_data_out_valid_0_sqmuxa_2[7]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_24); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_26, Y => - \counter_points_snapshot_10[9]\); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f2_wdata(5), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f2_wdata(65), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I112_Y : OR3A - port map(A => N440, B => N437, C => N499, Y => N558); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[0]\, B => N_47_0, - Y => ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : OA1A - port map(A => N541, B => N548, C => ADD_32x32_fast_I251_Y_1, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f2_wdata(75), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => N_33, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[25]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I48_Y : AO1C - port map(A => N_47_2, B => \un1_counter_points_snapshot[9]\, - C => N443, Y => N491); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0_0 : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0_a2_0\, - B => burst_f2, Y => counter_points_snapshot_0_sqmuxa_1_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : OR2B - port map(A => ADD_32x32_fast_I134_Y_1, B => - ADD_32x32_fast_I134_Y_0, Y => N580); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[20]\, B => N_47, - C => N783, Y => N780_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : OR2A - port map(A => N380, B => N383, Y => N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : OA1B - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[7]\, C => N_47_2, Y => N485); - - \counter_points_snapshot_RNICLKE[18]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f2_wdata(11), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(75)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => - N_47_1, Y => ADD_32x32_fast_I284_Y_0_0); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f2_wdata(4), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(68)); - - \counter_points_snapshot_RNO_0[11]\ : MX2C - port map(A => N_4, B => \un1_data_out_valid_0_sqmuxa_2[11]\, - S => counter_points_snapshot_2_sqmuxa_i, Y => N_28); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_counter_points_snapshot[2]\, C => N_47_0, Y => - ADD_32x32_fast_I251_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I12_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - N_47_2, Y => N416); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OR3 - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N556, Y => N620); - - \counter_points_snapshot_RNINVES[10]\ : MX2C - port map(A => I_56_12, B => - \counter_points_snapshot[10]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[21]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : OR3A - port map(A => ADD_32x32_fast_I264_Y_0, B => N566, C => N574, - Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768_i, B => ADD_32x32_fast_I296_Y_0_0, C => - N_52, Y => N_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I57_Y : AO1C - port map(A => \un1_counter_points_snapshot[14]\, B => - \counter_points_snapshot[18]_net_1\, C => N_47, Y => N500); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : OR2 - port map(A => N566, B => N558, Y => N622); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I125_Y : NOR2B - port map(A => N512, B => N508, Y => N571); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I214_un1_Y : - OR2B - port map(A => N628, B => N613, Y => I214_un1_Y); - - data_out_valid_RNO : OA1 - port map(A => burst_f2, B => N_59, C => - data_out_valid_9_i_0, Y => N_49); - - \data_out[100]\ : DFN1C0 - port map(D => sample_f2_wdata(36), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : NOR3 - port map(A => N626, B => I262_un1_Y, C => I228_un1_Y, Y => - N762_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : OR2 - port map(A => N481, B => N485, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f2_wdata(13), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f2_wdata(82), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_19, Y => - \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : NOR2 - port map(A => N582, B => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1C - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - N_52, Y => N_9); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f2_wdata(94), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(158)); - - \counter_points_snapshot_RNIS7BQ2_1[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I2_G0N : NOR2A - port map(A => \un1_counter_points_snapshot[29]\, B => N_47, - Y => N386); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f2_wdata(0), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I151_Y : NOR2B - port map(A => N547, B => N539, Y => N603); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(2 to 2); - status_full : out std_logic_vector(2 to 2); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - addr_data_f2 : in std_logic_vector(31 downto 0); - update_and_sel_3 : in std_logic_vector(5 downto 4); - status_full_ack : in std_logic_vector(2 to 2); - addr_data_vector_30 : in std_logic; - addr_data_vector_31 : in std_logic; - addr_data_vector_5 : in std_logic; - addr_data_vector_8 : in std_logic; - addr_data_vector_7 : in std_logic; - addr_data_vector_6 : in std_logic; - addr_data_vector_3 : in std_logic; - addr_data_vector_14 : in std_logic; - addr_data_vector_11 : in std_logic; - addr_data_vector_10 : in std_logic; - addr_data_vector_9 : in std_logic; - addr_data_vector_21 : in std_logic; - addr_data_vector_19 : in std_logic; - addr_data_vector_18 : in std_logic; - addr_data_vector_17 : in std_logic; - addr_data_vector_29 : in std_logic; - addr_data_vector_26 : in std_logic; - addr_data_vector_25 : in std_logic; - addr_data_vector_24 : in std_logic; - addr_data_vector_1 : in std_logic; - addr_data_vector_68 : out std_logic; - addr_data_vector_66 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_91 : out std_logic; - addr_data_vector_15 : in std_logic; - addr_data_vector_12 : in std_logic; - addr_data_vector_20 : in std_logic; - addr_data_vector_16 : in std_logic; - addr_data_vector_28 : in std_logic; - addr_data_vector_23 : in std_logic; - addr_data_vector_0 : in std_logic; - addr_data_vector_86 : out std_logic; - N_1365 : out std_logic; - N_1366 : out std_logic; - N_1396 : out std_logic; - N_1399 : out std_logic; - N_1398 : out std_logic; - N_1397 : out std_logic; - N_1394 : out std_logic; - N_1391 : out std_logic; - N_1388 : out std_logic; - N_1387 : out std_logic; - N_1386 : out std_logic; - N_1384 : out std_logic; - N_1382 : out std_logic; - N_1381 : out std_logic; - N_1380 : out std_logic; - N_1378 : out std_logic; - N_1375 : out std_logic; - N_1374 : out std_logic; - N_1373 : out std_logic; - N_1350 : out std_logic; - N_1392 : out std_logic; - N_1389 : out std_logic; - N_1383 : out std_logic; - N_1379 : out std_logic; - N_1377 : out std_logic; - N_1372 : out std_logic; - N_1349 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, \un1_address[24]\, - \addr_data_vector[88]\, N_41, N_42, \un1_state_12_2[4]\, - state7, \state[3]_net_1\, m40_m6_0_a2_7, N_25_0, - \un1_state_12[4]\, \un1_state_12_3_0[4]\, - \update_r[0]_net_1\, \update_r[1]_net_1\, m40_m6_0_a2_6, - m40_m6_0_a2_5, \addr_data_vector[85]\, - \addr_data_vector[84]\, m40_m6_0_a2_4, - \addr_data_vector[81]\, \addr_data_vector[80]\, - m40_m6_0_a2_2, \addr_data_vector[79]\, - \addr_data_vector[87]\, \addr_data_vector[82]\, - \addr_data_vector[83]\, \state_ns_0[0]\, - \state_ns_a3_1_0[0]\, N_129, N_124, un1_state_5_i_0, - \state[4]_net_1\, \state_ns_i_0[3]\, \state[2]_net_1\, - \state[1]_net_1\, N_116, \state_ns[0]\, N_110, - address_0_sqmuxa_i_0, un3_update_r, \un1_address[6]\, - \addr_data_vector[70]\, N_5_0, \un1_address[20]\, N_32_0, - N_36_0, N_47, N_46, \addr_data_vector[93]\, - \un1_address[29]\, un1_state_9, \nb_send_5[0]\, - \nb_send_5[1]\, \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, N_127, N_113, \state_ns[2]\, - un1_state_11, \address_7[20]\, \address_7[29]\, - \addr_data_vector[64]\, \addr_data_vector[92]\, - \addr_data_vector[76]\, \address_7[28]\, - \un1_address[28]\, N_44, \addr_data_vector[91]\, - N_15_0_i_0, N_13_0, \addr_data_vector[71]\, - \addr_data_vector[72]\, N_16_0, N_17_0_i_0, - \addr_data_vector[73]\, N_18_0, N_19_0, - \addr_data_vector[74]\, N_20_0_i_0, - \addr_data_vector[75]\, N_22_0_i_0, N_23_0, - \addr_data_vector[78]\, N_26_0_i_0, N_28_0_i_0, N_29_0, - N_30_0_i_0, \un1_address[19]\, N_37_0, \un1_address[23]\, - \addr_data_vector[86]\, N_40_i_0, N_50_i_0, - \addr_data_vector[66]\, \addr_data_vector[67]\, N_51_i_0, - N_69, N_52_i_0, \addr_data_vector[68]\, - \addr_data_vector[69]\, N_1_i_0, N_54_0_i_0, N_55_0_i_0, - \addr_data_vector[77]\, N_56_0_i_0, \un1_address[18]\, - \un1_address[21]\, \un1_address[22]\, \un1_address[25]\, - \addr_data_vector[89]\, \un1_address[27]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[14]\, \address_7[15]\, - \state[0]_net_1\, \address_7[16]\, \address_7[17]\, - \address_7[18]\, \address_7[19]\, \address_7[21]\, - \address_7[22]\, \address_7[23]\, \address_7[25]\, - \address_7[27]\, \addr_data_vector[65]\, - \addr_data_vector[90]\, \addr_data_vector[95]\, - \addr_data_vector[94]\, \address_7[31]\, N_49_i_0, - \address_7[30]\, \un1_address[30]\, \address_7[26]\, - \un1_address[26]\, \address_7[24]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_68 <= \addr_data_vector[68]\; - addr_data_vector_66 <= \addr_data_vector[66]\; - addr_data_vector_77 <= \addr_data_vector[77]\; - addr_data_vector_91 <= \addr_data_vector[91]\; - addr_data_vector_86 <= \addr_data_vector[86]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[80]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[74]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[94]\); - - \address_RNIHBFB[8]\ : MX2C - port map(A => addr_data_vector_8, B => - \addr_data_vector[72]\, S => sel_data(1), Y => N_1399); - - \address_RNIHSH5[10]\ : MX2C - port map(A => addr_data_vector_10, B => - \addr_data_vector[74]\, S => sel_data_1(1), Y => N_1387); - - un1_address_m45 : NOR3B - port map(A => \addr_data_vector[91]\, B => - \addr_data_vector[92]\, C => N_44, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f2(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : AX1 - port map(A => N_42, B => \addr_data_vector[89]\, C => - \addr_data_vector[90]\, Y => \un1_address[26]\); - - un1_address_m31 : OR3B - port map(A => \addr_data_vector[81]\, B => - \addr_data_vector[82]\, C => N_29_0, Y => N_32_0); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[90]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[84]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3A - port map(A => \state[2]_net_1\, B => N_129, C => - status_full_ack(2), Y => N_127); - - \address_RNIL4I5[21]\ : MX2C - port map(A => addr_data_vector_21, B => - \addr_data_vector[85]\, S => sel_data_1(1), Y => N_1384); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1 - port map(A => N_69, B => \addr_data_vector[68]\, C => - \addr_data_vector[69]\, Y => N_52_i_0); - - \address_RNI35K5[19]\ : MX2C - port map(A => addr_data_vector_19, B => - \addr_data_vector[83]\, S => sel_data_1(1), Y => N_1382); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[76]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNI96K9[31]\ : MX2C - port map(A => addr_data_vector_31, B => - \addr_data_vector[95]\, S => sel_data(1), Y => N_1366); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f2(29), S - => \state_0[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XNOR2 - port map(A => N_19_0, B => \addr_data_vector[75]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[86]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f2(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[66]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \address_RNI1TJ5[18]\ : MX2C - port map(A => addr_data_vector_18, B => - \addr_data_vector[82]\, S => sel_data_1(1), Y => N_1381); - - \address_RNIL9D7[3]\ : MX2C - port map(A => addr_data_vector_3, B => - \addr_data_vector[67]\, S => sel_data_1(1), Y => N_1394); - - un1_address_m43 : OR3B - port map(A => \addr_data_vector[89]\, B => - \addr_data_vector[90]\, C => N_42, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f2(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f2(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_110, Q => status_full_err(2)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : OR2B - port map(A => N_18_0, B => \addr_data_vector[74]\, Y => - N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \address_RNIOKI5[15]\ : MX2C - port map(A => addr_data_vector_15, B => - \addr_data_vector[79]\, S => sel_data_0(1), Y => N_1392); - - \state_RNI7AQ3A_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - \address_RNIPSI5[14]\ : MX2C - port map(A => addr_data_vector_14, B => - \addr_data_vector[78]\, S => sel_data_1(1), Y => N_1391); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f2(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[69]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[79]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[77]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => lclk_c, PRE => rstn, Q - => \state[4]_net_1\); - - \address_RNICPC7[0]\ : MX2C - port map(A => addr_data_vector_0, B => - \addr_data_vector[64]\, S => sel_data_0(1), Y => N_1349); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[83]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[89]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[87]\); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[71]\, C => - \addr_data_vector[72]\, Y => N_15_0_i_0); - - un1_address_m29 : XNOR2 - port map(A => N_29_0, B => \addr_data_vector[81]\, Y => - N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \state_RNO_2[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => N_124); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[93]\); - - \update_r_RNI7DL5[0]\ : OR2A - port map(A => \update_r[1]_net_1\, B => \update_r[0]_net_1\, - Y => un3_update_r); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[82]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f2(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f2(16), S => - \state[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f2(0), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => \addr_data_vector[64]\); - - un1_address_m28 : OR3B - port map(A => \addr_data_vector[79]\, B => - \addr_data_vector[80]\, C => N_25_0, Y => N_29_0); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - \un1_state_12_3[4]\ : NAND2 - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, Y => \un1_state_12[4]\); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : NAND2 - port map(A => \addr_data_vector[88]\, B => N_41, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f2(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[68]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[92]\); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - un1_address_m17 : NOR2A - port map(A => \addr_data_vector[73]\, B => N_16_0, Y => - N_18_0); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OA1A - port map(A => \state_ns_a3_1_0[0]\, B => N_129, C => N_124, - Y => \state_ns_0[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR3 - port map(A => address_0_sqmuxa_i_0, B => - \addr_data_vector[70]\, C => N_5_0, Y => \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f2(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - un1_address_m24 : OR3B - port map(A => \addr_data_vector[77]\, B => - \addr_data_vector[78]\, C => N_23_0, Y => N_25_0); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[7]_net_1\); - - un1_address_m40_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[81]\, B => - \addr_data_vector[80]\, C => m40_m6_0_a2_2, Y => - m40_m6_0_a2_5); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f2(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address_RNIDBFB[6]\ : MX2C - port map(A => addr_data_vector_6, B => - \addr_data_vector[70]\, S => sel_data(1), Y => N_1397); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[78]\); - - \address_RNIFBFB[7]\ : MX2C - port map(A => addr_data_vector_7, B => - \addr_data_vector[71]\, S => sel_data(1), Y => N_1398); - - \state_RNO[1]\ : OA1B - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - un1_address_m40_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[79]\, B => - \addr_data_vector[87]\, C => \addr_data_vector[86]\, Y - => m40_m6_0_a2_4); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => lclk_c, CLR => rstn, - E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f2(14), S => - \state_0[0]_net_1\, Y => \address_7[14]\); - - \address_RNIJ4I5[11]\ : MX2C - port map(A => addr_data_vector_11, B => - \addr_data_vector[75]\, S => sel_data_1(1), Y => N_1388); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \state_RNI5FKD[1]\ : OA1 - port map(A => \state[1]_net_1\, B => \state[2]_net_1\, C - => status_full_ack(2), Y => N_118); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[88]\); - - un1_address_m27 : AX1 - port map(A => N_25_0, B => \addr_data_vector[79]\, C => - \addr_data_vector[80]\, Y => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[89]\, Y => - \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[73]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : AO1B - port map(A => \state[3]_net_1\, B => state7, C => - \state_ns_0[0]\, Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[72]\); - - un1_address_m40_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[82]\, B => - \addr_data_vector[83]\, Y => m40_m6_0_a2_2); - - un1_address_m50 : XNOR2 - port map(A => N_69, B => \addr_data_vector[68]\, Y => - N_51_i_0); - - un1_address_m39 : XNOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[66]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : OR2 - port map(A => update_and_sel_3(5), B => update_and_sel_3(4), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f2(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f2(28), S - => \state_0[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f2(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - \state_ns_a3[0]\ : NOR2B - port map(A => state7, B => \state[3]_net_1\, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1C - port map(A => \addr_data_vector[86]\, B => N_37_0, C => - \addr_data_vector[87]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa_i_0, C => - \addr_data_vector[70]\, Y => N_13_0); - - un1_address_m59 : XOR2 - port map(A => \addr_data_vector[88]\, B => N_41, Y => - \un1_address[24]\); - - \update_r[0]\ : DFN1C0 - port map(D => update_and_sel_3(4), CLK => lclk_c, CLR => - rstn, Q => \update_r[0]_net_1\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[85]\, B => - \addr_data_vector[84]\, C => m40_m6_0_a2_4, Y => - m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f2(17), S => - \state[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f2(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[71]\, B => - \addr_data_vector[72]\, C => N_13_0, Y => N_16_0); - - \address_RNIM4I5[23]\ : MX2C - port map(A => addr_data_vector_23, B => - \addr_data_vector[87]\, S => sel_data_0(1), Y => N_1372); - - un1_address_m58 : XOR2 - port map(A => N_37_0, B => \addr_data_vector[86]\, Y => - \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f2(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[67]\); - - \address_RNI55K5[29]\ : MX2C - port map(A => addr_data_vector_29, B => - \addr_data_vector[93]\, S => sel_data_1(1), Y => N_1378); - - \address_RNIRSI5[24]\ : MX2C - port map(A => addr_data_vector_24, B => - \addr_data_vector[88]\, S => sel_data_1(1), Y => N_1373); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XOR2 - port map(A => N_46, B => \addr_data_vector[93]\, Y => - \un1_address[29]\); - - un1_address_m34 : AX1 - port map(A => N_32_0, B => \addr_data_vector[83]\, C => - \addr_data_vector[84]\, Y => \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f2(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : AO1D - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, C - => status_full_ack(2), Y => \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : XNOR2 - port map(A => N_23_0, B => \addr_data_vector[77]\, Y => - N_55_0_i_0); - - un1_address_m22 : OR3B - port map(A => \addr_data_vector[75]\, B => - \addr_data_vector[76]\, C => N_19_0, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[71]\); - - \address_RNIBBFB[5]\ : MX2C - port map(A => addr_data_vector_5, B => - \addr_data_vector[69]\, S => sel_data(1), Y => N_1396); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - \address_RNIISH5[12]\ : MX2C - port map(A => addr_data_vector_12, B => - \addr_data_vector[76]\, S => sel_data_0(1), Y => N_1389); - - un1_address_m25 : XNOR2 - port map(A => N_25_0, B => \addr_data_vector[79]\, Y => - N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => lclk_c, CLR => rstn, Q => - \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_3(5), CLK => lclk_c, CLR => - rstn, Q => \update_r[1]_net_1\); - - un1_address_m40_m6_0_a2_7 : AND2 - port map(A => m40_m6_0_a2_6, B => m40_m6_0_a2_5, Y => - m40_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - un1_address_m57 : XNOR2 - port map(A => N_36_0, B => \addr_data_vector[85]\, Y => - \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - un1_address_m40_m6_0_a2 : NOR2A - port map(A => m40_m6_0_a2_7, B => N_25_0, Y => N_41); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f2(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[66]\, C => \addr_data_vector[67]\, Y - => N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[73]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f2(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f2(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[94]\, B => N_47, C => - \addr_data_vector[95]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[70]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - status_full_err_RNO : AO1A - port map(A => N_129, B => \state[2]_net_1\, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state_0[0]_net_1\); - - \address_RNIT4J5[25]\ : MX2C - port map(A => addr_data_vector_25, B => - \addr_data_vector[89]\, S => sel_data_1(1), Y => N_1374); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f2(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un1_address_m36 : NOR2A - port map(A => \addr_data_vector[85]\, B => N_36_0, Y => - N_37_0); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[75]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[95]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : AX1 - port map(A => N_29_0, B => \addr_data_vector[81]\, C => - \addr_data_vector[82]\, Y => \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f2(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - \address_RNIEPC7[1]\ : MX2C - port map(A => addr_data_vector_1, B => - \addr_data_vector[65]\, S => sel_data_0(1), Y => N_1350); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f2(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f2(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[85]\); - - \un1_state_12_3_RNO[4]\ : NOR2A - port map(A => \update_r[0]_net_1\, B => \update_r[1]_net_1\, - Y => \un1_state_12_3_0[4]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - \address_RNI0DJ5[28]\ : MX2C - port map(A => addr_data_vector_28, B => - \addr_data_vector[92]\, S => sel_data_0(1), Y => N_1377); - - un1_address_m62 : XNOR2 - port map(A => N_44, B => \addr_data_vector[91]\, Y => - \un1_address[27]\); - - un1_address_m32 : XNOR2 - port map(A => N_32_0, B => \addr_data_vector[83]\, Y => - \un1_address[19]\); - - un1_address_m12_e : OR3B - port map(A => \addr_data_vector[68]\, B => - \addr_data_vector[69]\, C => N_69, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => lclk_c, CLR => rstn, Q => - \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[81]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[94]\, Y => - \un1_address[30]\); - - \address_RNIGCH5[20]\ : MX2C - port map(A => addr_data_vector_20, B => - \addr_data_vector[84]\, S => sel_data_0(1), Y => N_1383); - - un1_address_m35 : OR3B - port map(A => \addr_data_vector[83]\, B => - \addr_data_vector[84]\, C => N_32_0, Y => N_36_0); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[71]\, Y => - N_1_i_0); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[91]\); - - \state_RNO[3]\ : NOR2B - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : AX1 - port map(A => N_19_0, B => \addr_data_vector[75]\, C => - \addr_data_vector[76]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : AX1 - port map(A => N_23_0, B => \addr_data_vector[77]\, C => - \addr_data_vector[78]\, Y => N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f2(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : OR3B - port map(A => \addr_data_vector[66]\, B => - \addr_data_vector[67]\, C => \un1_state_12[4]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f2(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - \address_RNI1AD7[9]\ : MX2C - port map(A => addr_data_vector_9, B => - \addr_data_vector[73]\, S => sel_data_1(1), Y => N_1386); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f2(1), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => \addr_data_vector[65]\); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_11, Q => status_full(2)); - - \state_RNI7AQ3A[3]\ : OR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa_i_0); - - un1_address_m63 : AX1 - port map(A => N_44, B => \addr_data_vector[91]\, C => - \addr_data_vector[92]\, Y => \un1_address[28]\); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f2(20), S - => \state_0[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR2B - port map(A => N_46, B => \addr_data_vector[93]\, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : XOR2 - port map(A => N_18_0, B => \addr_data_vector[74]\, Y => - N_54_0_i_0); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \address_RNI7UJ9[30]\ : MX2C - port map(A => addr_data_vector_30, B => - \addr_data_vector[94]\, S => sel_data(1), Y => N_1365); - - \state_RNO_1[4]\ : NOR3 - port map(A => \state[1]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => \state_ns_a3_1_0[0]\); - - \address_RNIQSI5[16]\ : MX2C - port map(A => addr_data_vector_16, B => - \addr_data_vector[80]\, S => sel_data_0(1), Y => N_1379); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f2(15), S => - \state[0]_net_1\, Y => \address_7[15]\); - - \address_RNIVCJ5[26]\ : MX2C - port map(A => addr_data_vector_26, B => - \addr_data_vector[90]\, S => sel_data_1(1), Y => N_1375); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - \address_RNIVKJ5[17]\ : MX2C - port map(A => addr_data_vector_17, B => - \addr_data_vector[81]\, S => sel_data_1(1), Y => N_1380); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(0 to 0); - status_full : out std_logic_vector(0 to 0); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - update_and_sel_7 : in std_logic_vector(1 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(0 to 0); - addr_data_vector_1 : out std_logic; - addr_data_vector_0 : out std_logic; - addr_data_vector_68 : in std_logic; - addr_data_vector_66 : in std_logic; - addr_data_vector_77 : in std_logic; - addr_data_vector_86 : in std_logic; - addr_data_vector_91 : in std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_30 : out std_logic; - addr_data_vector_5 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_25 : out std_logic; - addr_data_vector_24 : out std_logic; - addr_data_vector_23 : out std_logic; - addr_data_vector_12 : out std_logic; - addr_data_vector_11 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_8 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_3 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_18 : out std_logic; - addr_data_vector_17 : out std_logic; - addr_data_vector_21 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_16 : out std_logic; - addr_data_vector_19 : out std_logic; - addr_data_vector_20 : out std_logic; - N_1395 : out std_logic; - N_1393 : out std_logic; - N_1390 : out std_logic; - N_1385 : out std_logic; - N_1376 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, m37_m6_0_a2_6, m37_m6_0_a2_4, - m37_m6_0_a2_5, m37_m6_0_a2_2, \addr_data_vector[22]\, - ADD_32x32_fast_I164_Y_0_0, address_0_sqmuxa_i_0, - \un1_state_12_3_0[4]\, \update_r[0]_net_1\, - \update_r[1]_net_1\, address_0_sqmuxa_0, \state[3]_net_1\, - un1_state_5_i_0, \state[4]_net_1\, \state_ns_i_0[3]\, - N_131, N_116, N_129, \state[1]_net_1\, \state_ns[0]\, - N_125, N_124, \un1_state_12_2[4]\, N_110, - \state[2]_net_1\, state7, \un1_address[6]\, N_5_0, - N_38_0_i, N_24_0, N_2, \addr_data_vector[2]\, N_4_0, - \addr_data_vector[4]\, N_15_0_i_0, N_13_0_i_0, N_16_0, - \addr_data_vector[7]\, \addr_data_vector[8]\, N_17_0_i_0, - N_19_0, \addr_data_vector[9]\, N_20_0_i_0, N_22_0_i_0, - \addr_data_vector[11]\, N_23_0, \addr_data_vector[12]\, - \addr_data_vector[13]\, N_25_0, \addr_data_vector[14]\, - N_26_0_i_0, \addr_data_vector[15]\, N_28_0_i_0, - \addr_data_vector[16]\, N_29_0, N_30_0_i_0, - \addr_data_vector[17]\, N_32_0, \addr_data_vector[18]\, - \un1_address[19]\, \addr_data_vector[19]\, - \un1_address[20]\, \addr_data_vector[20]\, N_36_0, - \un1_address[23]\, N_40_i_0, N_42, \addr_data_vector[23]\, - N_44, N_45, \addr_data_vector[27]\, N_47, N_50_i_0, - \addr_data_vector[3]\, N_51_i_0, N_52_i_0, N_1_i_0, - N_54_0_i_0, \addr_data_vector[10]\, N_55_0_i_0, - N_56_0_i_0, \un1_address[18]\, \un1_address[21]\, - \addr_data_vector[21]\, \un1_address[22]\, - \un1_address[24]\, \addr_data_vector[24]\, - \un1_address[25]\, \addr_data_vector[25]\, - \un1_address[26]\, \addr_data_vector[26]\, - \un1_address[27]\, \un1_address[28]\, - \addr_data_vector[28]\, \un1_address[29]\, - \addr_data_vector[29]\, \addr_data_vector[5]\, - nb_send_1_sqmuxa, un1_state_9, \nb_send_5[0]\, - \nb_send_5[1]\, \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, N_127, N_113, \state_ns[2]\, - un1_state_11, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[14]\, \address_7[15]\, - \address_7[16]\, \address_7[17]\, \address_7[18]\, - \state[0]_net_1\, \address_7[19]\, \address_7[20]\, - \address_7[21]\, \address_7[22]\, \address_7[23]\, - \address_7[24]\, \address_7[25]\, \address_7[26]\, - \address_7[27]\, \address_7[28]\, \address_7[29]\, - \address_7[31]\, N_49_i_0, \address_7[30]\, - \un1_address[30]\, \addr_data_vector[30]\, - \addr_data_vector[6]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, - \addr_data_vector[31]\, N_4, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[3]\, N_12, N_17, N_22, \DWACT_FINC_E[1]\, - N_27, N_35, \DWACT_COMP0_E[1]\, \DWACT_COMP0_E[2]\, - \DWACT_COMP0_E[0]\, \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_31 <= \addr_data_vector[31]\; - addr_data_vector_30 <= \addr_data_vector[30]\; - addr_data_vector_5 <= \addr_data_vector[5]\; - addr_data_vector_29 <= \addr_data_vector[29]\; - addr_data_vector_28 <= \addr_data_vector[28]\; - addr_data_vector_26 <= \addr_data_vector[26]\; - addr_data_vector_25 <= \addr_data_vector[25]\; - addr_data_vector_24 <= \addr_data_vector[24]\; - addr_data_vector_23 <= \addr_data_vector[23]\; - addr_data_vector_12 <= \addr_data_vector[12]\; - addr_data_vector_11 <= \addr_data_vector[11]\; - addr_data_vector_10 <= \addr_data_vector[10]\; - addr_data_vector_9 <= \addr_data_vector[9]\; - addr_data_vector_8 <= \addr_data_vector[8]\; - addr_data_vector_7 <= \addr_data_vector[7]\; - addr_data_vector_3 <= \addr_data_vector[3]\; - addr_data_vector_6 <= \addr_data_vector[6]\; - addr_data_vector_18 <= \addr_data_vector[18]\; - addr_data_vector_17 <= \addr_data_vector[17]\; - addr_data_vector_21 <= \addr_data_vector[21]\; - addr_data_vector_14 <= \addr_data_vector[14]\; - addr_data_vector_15 <= \addr_data_vector[15]\; - addr_data_vector_16 <= \addr_data_vector[16]\; - addr_data_vector_19 <= \addr_data_vector[19]\; - addr_data_vector_20 <= \addr_data_vector[20]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[16]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[10]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[30]\); - - \update_r_RNIATLE[0]\ : OR3B - port map(A => \update_r[1]_net_1\, B => \state[3]_net_1\, C - => \update_r[0]_net_1\, Y => address_0_sqmuxa_0); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f0(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : AX1 - port map(A => N_42, B => \addr_data_vector[25]\, C => - \addr_data_vector[26]\, Y => \un1_address[26]\); - - un1_address_m37_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[14]\, B => - \addr_data_vector[22]\, C => \addr_data_vector[21]\, Y - => m37_m6_0_a2_4); - - un1_address_m31 : NOR3C - port map(A => \addr_data_vector[17]\, B => N_29_0, C => - \addr_data_vector[18]\, Y => N_32_0); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[26]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[20]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3A - port map(A => \state[2]_net_1\, B => N_129, C => - status_full_ack(0), Y => N_127); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : XOR2 - port map(A => N_4_0, B => \addr_data_vector[5]\, Y => - N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[12]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f0(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XOR2 - port map(A => N_19_0, B => \addr_data_vector[11]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[22]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f0(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[2]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \state_RNIN0L5[1]\ : NOR2A - port map(A => status_full_ack(0), B => N_131, Y => N_118); - - un1_address_m43 : OR3B - port map(A => \addr_data_vector[25]\, B => - \addr_data_vector[26]\, C => N_42, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f0(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f0(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_110, Q => status_full_err(0)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : NOR3C - port map(A => \addr_data_vector[9]\, B => N_16_0, C => - \addr_data_vector[10]\, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - un1_address_ADD_32x32_fast_I164_Y_0_0 : XOR2 - port map(A => \addr_data_vector[6]\, B => - address_0_sqmuxa_i_0, Y => ADD_32x32_fast_I164_Y_0_0); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f0(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[5]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[15]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[13]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => lclk_c, PRE => rstn, Q - => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[19]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[25]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[23]\); - - un1_address_m14 : AX1C - port map(A => \addr_data_vector[7]\, B => N_13_0_i_0, C => - \addr_data_vector[8]\, Y => N_15_0_i_0); - - un1_address_m29 : XOR2 - port map(A => N_29_0, B => \addr_data_vector[17]\, Y => - N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[29]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[18]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f0(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f0(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - \address_RNINKI5[13]\ : MX2C - port map(A => \addr_data_vector[13]\, B => - addr_data_vector_77, S => sel_data_1(1), Y => N_1390); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f0(0), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => addr_data_vector_0); - - un1_address_m28 : NOR3C - port map(A => \addr_data_vector[15]\, B => N_25_0, C => - \addr_data_vector[16]\, Y => N_29_0); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - \update_r_RNI691J01[0]\ : OA1A - port map(A => \update_r[1]_net_1\, B => \update_r[0]_net_1\, - C => state7, Y => nb_send_1_sqmuxa); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : OR3B - port map(A => \addr_data_vector[23]\, B => - \addr_data_vector[24]\, C => N_38_0_i, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f0(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[4]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[28]\); - - un1_address_m1 : NOR3C - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, C => \addr_data_vector[2]\, Y => - N_2); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3A - port map(A => N_131, B => \state[3]_net_1\, C => N_129, Y - => N_125); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I164_Y_0_0, B => N_5_0, Y => - \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f0(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - un1_address_m24 : NOR2A - port map(A => \addr_data_vector[14]\, B => N_24_0, Y => - N_25_0); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f0(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[14]\); - - \state_RNO[1]\ : OA1B - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => lclk_c, CLR => rstn, - E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f0(14), S => - \state_0[0]_net_1\, Y => \address_7[14]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[24]\); - - un1_address_m27 : AX1C - port map(A => \addr_data_vector[15]\, B => N_25_0, C => - \addr_data_vector[16]\, Y => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \address_RNI9BFB[4]\ : MX2C - port map(A => \addr_data_vector[4]\, B => - addr_data_vector_68, S => sel_data(1), Y => N_1395); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[25]\, Y => - \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XOR2 - port map(A => N_16_0, B => \addr_data_vector[9]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \state_RNIAI1701[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3B - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[8]\); - - un1_address_m50 : AX1C - port map(A => \addr_data_vector[3]\, B => N_2, C => - \addr_data_vector[4]\, Y => N_51_i_0); - - un1_address_m39 : AX1C - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, C => \addr_data_vector[2]\, Y => - N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : OR2 - port map(A => update_and_sel_7(1), B => update_and_sel_7(0), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f0(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f0(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f0(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : XNOR2 - port map(A => N_38_0_i, B => \addr_data_vector[23]\, Y => - \un1_address[23]\); - - un1_address_m12 : AO18 - port map(A => N_5_0, B => \addr_data_vector[6]\, C => - address_0_sqmuxa_i_0, Y => N_13_0_i_0); - - un1_address_m59 : AX1 - port map(A => N_38_0_i, B => \addr_data_vector[23]\, C => - \addr_data_vector[24]\, Y => \un1_address[24]\); - - \update_r[0]\ : DFN1C0 - port map(D => update_and_sel_7(0), CLK => lclk_c, CLR => - rstn, Q => \update_r[0]_net_1\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f0(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f0(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : NOR3C - port map(A => \addr_data_vector[7]\, B => N_13_0_i_0, C => - \addr_data_vector[8]\, Y => N_16_0); - - un1_address_m58 : AX1C - port map(A => \addr_data_vector[21]\, B => N_36_0, C => - \addr_data_vector[22]\, Y => \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f0(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[3]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : AX1C - port map(A => \addr_data_vector[28]\, B => N_45, C => - \addr_data_vector[29]\, Y => \un1_address[29]\); - - un1_address_m34 : AX1C - port map(A => \addr_data_vector[19]\, B => N_32_0, C => - \addr_data_vector[20]\, Y => \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f0(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(0), B => N_131, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : XOR2 - port map(A => N_23_0, B => \addr_data_vector[13]\, Y => - N_55_0_i_0); - - un1_address_m22 : NOR3C - port map(A => \addr_data_vector[11]\, B => N_19_0, C => - \addr_data_vector[12]\, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[7]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[5]_net_1\); - - un1_address_m37_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[17]\, B => - \addr_data_vector[18]\, Y => m37_m6_0_a2_2); - - un1_address_m3 : NOR3C - port map(A => \addr_data_vector[3]\, B => N_2, C => - \addr_data_vector[4]\, Y => N_4_0); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - un1_address_m25 : XOR2 - port map(A => N_25_0, B => \addr_data_vector[15]\, Y => - N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => lclk_c, CLR => rstn, Q => - \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_7(1), CLK => lclk_c, CLR => - rstn, Q => \update_r[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - \update_r_RNI3QAD[0]\ : NOR2A - port map(A => \update_r[0]_net_1\, B => \update_r[1]_net_1\, - Y => \un1_state_12_3_0[4]\); - - un1_address_m57 : XOR2 - port map(A => N_36_0, B => \addr_data_vector[21]\, Y => - \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - un1_address_m37_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[16]\, B => - \addr_data_vector[15]\, C => m37_m6_0_a2_2, Y => - m37_m6_0_a2_5); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f0(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : XOR2 - port map(A => N_2, B => \addr_data_vector[3]\, Y => - N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[9]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f0(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f0(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m37_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[20]\, B => - \addr_data_vector[19]\, C => m37_m6_0_a2_4, Y => - m37_m6_0_a2_6); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[30]\, B => N_47, C => - \addr_data_vector[31]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - un1_address_m23 : OR2B - port map(A => N_23_0, B => \addr_data_vector[13]\, Y => - N_24_0); - - status_full_err_RNO : AO1A - port map(A => N_129, B => \state[2]_net_1\, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f0(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[11]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : AX1C - port map(A => \addr_data_vector[17]\, B => N_29_0, C => - \addr_data_vector[18]\, Y => \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f0(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - un1_address_m44 : NOR2A - port map(A => \addr_data_vector[27]\, B => N_44, Y => N_45); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f0(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f0(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[21]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - un1_address_m62 : XNOR2 - port map(A => N_44, B => \addr_data_vector[27]\, Y => - \un1_address[27]\); - - un1_address_m32 : XOR2 - port map(A => N_32_0, B => \addr_data_vector[19]\, Y => - \un1_address[19]\); - - \state_RNIB6M2[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - un1_address_m12_e : OR2B - port map(A => N_4_0, B => \addr_data_vector[5]\, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => lclk_c, CLR => rstn, Q => - \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[17]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[30]\, Y => - \un1_address[30]\); - - un1_address_m35 : NOR3C - port map(A => \addr_data_vector[19]\, B => N_32_0, C => - \addr_data_vector[20]\, Y => N_36_0); - - un1_address_m52 : XOR2 - port map(A => N_13_0_i_0, B => \addr_data_vector[7]\, Y => - N_1_i_0); - - \update_r_RNIDCCK01[0]\ : OR2A - port map(A => state7, B => address_0_sqmuxa_0, Y => - address_0_sqmuxa_i_0); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[27]\); - - un1_address_m37_m6_0_a2 : OR3B - port map(A => m37_m6_0_a2_6, B => m37_m6_0_a2_5, C => - N_24_0, Y => N_38_0_i); - - \state_RNO[3]\ : NOR2B - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : AX1C - port map(A => \addr_data_vector[11]\, B => N_19_0, C => - \addr_data_vector[12]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : XNOR2 - port map(A => N_24_0, B => \addr_data_vector[14]\, Y => - N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f0(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f0(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - \state_RNIDCCK01[3]\ : OR2A - port map(A => \state[3]_net_1\, B => nb_send_1_sqmuxa, Y - => un1_state_9); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f0(1), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => addr_data_vector_1); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_11, Q => status_full(0)); - - un1_address_m63 : XOR2 - port map(A => N_45, B => \addr_data_vector[28]\, Y => - \un1_address[28]\); - - \address_RNINCI5[22]\ : MX2C - port map(A => \addr_data_vector[22]\, B => - addr_data_vector_86, S => sel_data_1(1), Y => N_1385); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f0(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR3C - port map(A => \addr_data_vector[28]\, B => N_45, C => - \addr_data_vector[29]\, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : AX1C - port map(A => \addr_data_vector[9]\, B => N_16_0, C => - \addr_data_vector[10]\, Y => N_54_0_i_0); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f0(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - \address_RNI1LJ5[27]\ : MX2C - port map(A => \addr_data_vector[27]\, B => - addr_data_vector_91, S => sel_data_1(1), Y => N_1376); - - \address_RNIJ9D7[2]\ : MX2C - port map(A => \addr_data_vector[2]\, B => - addr_data_vector_66, S => sel_data_1(1), Y => N_1393); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_dma_send_16word is - - port( un7_dmain : out std_logic_vector(66 to 66); - state_0_0 : in std_logic; - Address_RNIJ4SP : out std_logic_vector(20 to 20); - Address_RNIP8BS : out std_logic_vector(0 to 0); - data_address : in std_logic_vector(31 downto 0); - bco_msb_1_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - bco_msb_1 : in std_logic_vector(1 to 1); - hmaster_0 : in std_logic_vector(1 to 1); - l1_0_m : in std_logic_vector(1 to 1); - nhmaster_1_i : in std_logic_vector(0 to 0); - iosn_0 : in std_logic_vector(93 to 93); - Lock : out std_logic; - Request_0 : in std_logic; - N_1081 : out std_logic; - Store_0 : in std_logic; - N_1082 : out std_logic; - Fault : in std_logic; - N_1022 : out std_logic; - data_send_ok : out std_logic; - data_send_ko : out std_logic; - N_1102 : out std_logic; - N_1027 : out std_logic; - N_1026 : out std_logic; - N_1025 : out std_logic; - N_1024 : out std_logic; - N_1023 : out std_logic; - N_1021 : out std_logic; - N_1034 : out std_logic; - N_1033 : out std_logic; - N_1031 : out std_logic; - N_1030 : out std_logic; - N_1029 : out std_logic; - N_1028 : out std_logic; - N_1041 : out std_logic; - time_select : in std_logic; - N_1040 : out std_logic; - N_1039 : out std_logic; - N_1038 : out std_logic; - N_1036 : out std_logic; - N_1035 : out std_logic; - N_1048 : out std_logic; - N_1047 : out std_logic; - N_1046 : out std_logic; - N_1044 : out std_logic; - N_1043 : out std_logic; - N_1042 : out std_logic; - N_1020 : out std_logic; - N_1019 : out std_logic; - N_1018 : out std_logic; - data_fifo_ren : out std_logic; - N_1032 : out std_logic; - N_1045 : out std_logic; - time_select_0 : in std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - Grant_1_0 : in std_logic; - m19_0_N_15_i_0_li : in std_logic; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - OKAY : in std_logic; - Ready : in std_logic; - data_send : in std_logic; - Grant_0 : in std_logic; - Grant : in std_logic; - m26_m1_e : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_dma_send_16word; - -architecture DEF_ARCH of lpp_dma_send_16word is - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[5]_net_1\, N_4, N_154_0, N_235, - \state[3]_net_1\, N_242, N_202_0, N_200, N_198_0, N_348, - \grant_counter_0_i_0_0[17]\, \grant_counter_0_i_5[17]\, - \data_counter_8_i_0_0[0]\, N_516_2, N_508, - \data_counter_8_i_0[0]\, \grant_counter_0_i_a0_5[17]\, - \grant_counter_0_i_a0_0[17]\, - \grant_counter_0_i_a0_4[17]\, - \grant_counter_0_i_a0_2[17]\, \grant_counter[12]_net_1\, - \grant_counter[11]_net_1\, \grant_counter_0_i_a0_2_0[17]\, - \grant_counter[10]_net_1\, \grant_counter[14]_net_1\, - \grant_counter[16]_net_1\, \grant_counter[17]_net_1\, - ADD_32x32_fast_I129_un1_Y_12, ADD_32x32_fast_I129_un1_Y_9, - ADD_32x32_fast_I129_un1_Y_8, ADD_32x32_fast_I129_un1_Y_10, - ADD_32x32_fast_I129_un1_Y_2, ADD_32x32_fast_I129_un1_Y_1, - m49_m6_0_a2_0, ADD_32x32_fast_I129_un1_Y_0, - ADD_32x32_fast_I129_un1_Y_5, m75_m6_0_a2_1, - \grant_counter[25]_net_1\, \grant_counter[24]_net_1\, - ADD_32x32_fast_I129_un1_Y_4, \grant_counter[23]_net_1\, - \grant_counter[15]_net_1\, \grant_counter[18]_net_1\, - \grant_counter[21]_net_1\, \grant_counter[22]_net_1\, - \grant_counter[29]_net_1\, \grant_counter[19]_net_1\, - \grant_counter[20]_net_1\, \grant_counter[26]_net_1\, - m49_m6_0_a2_5, \grant_counter_0_i_6_tz_1_0[17]\, - m49_m6_0_a2_4, m49_m6_0_a2_2, m45_m6_0_a2_2, - \data_counter_8_i_a4_2_0[0]\, \state[0]_net_1\, m71_0, - \data_counter[28]_net_1\, \data_counter[27]_net_1\, - m63_m6_0_a2_6, m63_m6_0_a2_4, m23_m6_0_a2_4, - m63_m6_0_a2_3, m55_m6_0_a2_4, m63_m6_0_a2_0, - m63_m6_0_a2_1_0, m26_m6_e_0, m63_m6_0_a2_1, - grant_counter_0_i_20_b0_0_o2_4, - grant_counter_0_i_20_b0_0_o2_1, - grant_counter_0_i_20_b0_0_o2_2, - \grant_counter_0_i_6_tz_1[17]\, m45_m6_0_a2_6, - m45_m6_0_a2_4, \m26_m1_e\, \grant_counter[13]_net_1\, - \grant_counter[9]_net_1\, m26_m6_e_3, m26_m6_e_1, N_241, - m26_m6_e_0_0, ADD_32x32_fast_I129_un1_Y_13, - ADD_32x32_fast_I129_un1_Y_8_0, - ADD_32x32_fast_I129_un1_Y_7, - ADD_32x32_fast_I129_un1_Y_12_0, - ADD_32x32_fast_I129_un1_Y_4_0, - ADD_32x32_fast_I129_un1_Y_10_0, m57_m6_0_a2_7_1, - \data_counter[19]_net_1\, \data_counter[16]_net_1\, - ADD_32x32_fast_I129_un1_Y_6, \data_counter[26]_net_1\, - \data_counter[25]_net_1\, ADD_32x32_fast_I129_un1_Y_3, - \data_counter[22]_net_1\, \data_counter[21]_net_1\, - ADD_32x32_fast_I129_un1_Y_1_0, \data_counter[20]_net_1\, - \data_counter[14]_net_1\, \data_counter[15]_net_1\, - \data_counter[29]_net_1\, \data_counter[23]_net_1\, - \data_counter[24]_net_1\, m17_m2_e_3, m17_m2_e_2, - m17_m2_e_0, \grant_counter[1]_net_1\, - \grant_counter[2]_net_1\, \grant_counter[0]_net_1\, m59_0, - m28_m6_0_a2_4, m57_m6_0_a2_7_5, m43_0, un1_state_9_i_a4_0, - N_246, un1_state_2_i_a2_m8_i_2, un1_state_2_i_a2_m8_i_0, - un1_state_2_i_o2_0, \state[4]_net_1\, m19_0_m8_i_1, - m75_m6_0_a2_3, m75_m6_0_a2_2, m75_m6_0_a2_0, - \grant_counter[30]_net_1\, un1_state_5_i_o2_29, - un1_state_5_i_o2_21, un1_state_5_i_o2_20, - un1_state_5_i_o2_27, un1_state_5_i_o2_28, - un1_state_5_i_o2_17, un1_state_5_i_o2_16, - un1_state_5_i_o2_25, un1_state_5_i_o2_13, - un1_state_5_i_o2_12, un1_state_5_i_o2_23, - un1_state_5_i_o2_5, un1_state_5_i_o2_4, - un1_state_5_i_o2_19, \data_counter[1]_net_1\, - \data_counter[0]_net_1\, un1_state_5_i_o2_15, - un1_state_5_i_o2_11, \data_counter[11]_net_1\, - un1_state_5_i_o2_9, un1_state_5_i_o2_7, - \data_counter[18]_net_1\, un1_state_5_i_o2_3, - \data_counter[6]_net_1\, \data_counter[5]_net_1\, - un1_state_5_i_o2_1, \data_counter[13]_net_1\, - \data_counter[31]_net_1\, \data_counter[2]_net_1\, - \data_counter[3]_net_1\, \data_counter[12]_net_1\, - \data_counter[17]_net_1\, \data_counter[9]_net_1\, - \data_counter[10]_net_1\, \data_counter[7]_net_1\, - \data_counter[8]_net_1\, \data_counter[30]_net_1\, - \data_counter[4]_net_1\, m19_a1_6_4, m19_a1_6_3, - m19_a1_6_1, \state_ns_i_a2_i_0_0[0]\, \state[1]_net_1\, - un1_state_7_i_a4_0_1, N_518_1, m67_m6_0_a2_4_4, - m67_m6_0_a2_4_2, m67_m6_0_a2_4_3, m57_m6_0_a2_7_0, - m57_m6_0_a2_7_4, m57_m6_0_a2_7_2, m23_m6_0_a2_4_6, - \grant_counter[7]_net_1\, m23_m6_0_a2_4_4, - m23_m6_0_a2_4_5, \grant_counter[4]_net_1\, - \grant_counter[3]_net_1\, m23_m6_0_a2_4_2, - \grant_counter[8]_net_1\, \grant_counter[5]_net_1\, - \grant_counter[6]_net_1\, \state_ns_i_a2_0_i_o2_28[3]\, - \state_ns_i_a2_0_i_o2_19[3]\, - \state_ns_i_a2_0_i_o2_18[3]\, - \state_ns_i_a2_0_i_o2_24[3]\, - \state_ns_i_a2_0_i_o2_27[3]\, - \state_ns_i_a2_0_i_o2_13[3]\, - \state_ns_i_a2_0_i_o2_12[3]\, - \state_ns_i_a2_0_i_o2_23[3]\, - \state_ns_i_a2_0_i_o2_26[3]\, \state_ns_i_a2_0_i_o2_9[3]\, - \state_ns_i_a2_0_i_o2_8[3]\, \state_ns_i_a2_0_i_o2_21[3]\, - \state_ns_i_a2_0_i_o2_3[3]\, \state_ns_i_a2_0_i_o2_2[3]\, - \state_ns_i_a2_0_i_o2_16[3]\, - \state_ns_i_a2_0_i_o2_15[3]\, - \state_ns_i_a2_0_i_o2_11[3]\, \state_ns_i_a2_0_i_o2_7[3]\, - \state_ns_i_a2_0_i_o2_5[3]\, \grant_counter[27]_net_1\, - \grant_counter[31]_net_1\, \grant_counter[28]_net_1\, - m55_m6_0_a2_4_4, m55_m6_0_a2_4_0, m55_m6_0_a2_4_3, - m28_m6_0_a2_4_6, m28_m6_0_a2_4_4, m28_m6_0_a2_4_5, - m28_m6_0_a2_4_2, m19_a0_6_4, m19_a0_6_3, - \grant_counter_0_i_6_tz_3[17]\, - \grant_counter_0_i_6_tz_2[17]\, I129_un1_Y, N_28_0, N_75, - N_72, I129_un1_Y_0, N623, N_186, - \grant_counter_RNO[0]_net_1\, N_30_0, N_354, N_89, - \un1_hresetn_inv_2_i_i[27]\, N_346, N_526, N_194, N_522, - Burst, m19_0_m8_i, \un1_state_2_i_a2_m8_i_a4\, m26tt_N_7, - \state_RNI6R78T9[4]_net_1\, \state_RNI7ALP[4]_net_1\, - m67_m6_0_a2_4, N_50, m26_m3_e, - \grant_counter_RNO_0[17]_net_1\, N_115, - \grant_counter_RNO_2[17]_net_1\, m75_m6_0_a2, - un1_hresetn_inv_i_0_a2_0, N_28_0_0, N_26_0, N_68, - \un1_state_4_i[31]\, \data_counter_8_i_0_tz[0]\, N_58, - N_20_0, \un1_hresetn_inv_2_i[0]\, - grant_counter_0_i_20_N_14_i, N_121, N_68_0, - un1_state_2_i_a2_N_3_i_0_li, \state_RNITA375[4]_net_1\, - N_24_0, un1_hresetn_inv_i_0, N_56, \state[2]_net_1\, - N_243_i, N_13, N_59, N_75_0, \Address[0]\, \Address[28]\, - \Address[20]\, \Address[15]\, N_49, N_17_0, N_19_0, - N_20_0_0, N_21_0, N_22_0, N_23_0, N_25_0, N_26_0_0, - N_31_0_i_0, N_32_0_i_0, N_33_0_i_0, - \un1_hresetn_inv_2_i[19]\, \un1_hresetn_inv_2_i[18]\, - N_44, \un1_hresetn_inv_2_i[15]\, - \un1_hresetn_inv_2_i[13]\, \un1_hresetn_inv_2_i[12]\, - \un1_hresetn_inv_2_i[10]\, \un1_hresetn_inv_2_i[9]\, N_60, - N_62, \un1_hresetn_inv_2_i[6]\, N_66, - \un1_hresetn_inv_2_i[5]\, \un1_hresetn_inv_2_i[4]\, - \un1_hresetn_inv_2_i[3]\, N_72_0, - \un1_hresetn_inv_2_i_0[17]\, N_17_0_0, N_8, N_19_0_0, - N_22_0_0, N_23_0_0, N_24_0_0, N_25_0_0, N_27_0, - \un1_state_4_i[30]\, \un1_state_4_i[29]\, - \un1_state_4_i[28]\, N_36_0, N_45, N_46, N_48, N_50_0, - N_52, N_54, N_56_0, N_61, N_62_0, N_64, N_66_0, N_70, - N_249, Request_5, N_513, \data_counter_8[4]\, - \data_counter_8[5]\, \data_counter_8[6]\, - \data_counter_8[7]\, \data_counter_8[8]\, - \data_counter_8[9]\, \data_counter_8[10]\, - \data_counter_8[11]\, \data_counter_8[12]\, - \data_counter_8[13]\, \data_counter_8[14]\, - \data_counter_8[15]\, \data_counter_8[16]\, - \data_counter_8[17]\, \data_counter_8[18]\, N_198, - \data_counter_8[19]\, \data_counter_8[20]\, - \data_counter_8[21]\, \data_counter_8[22]\, - \data_counter_8[23]\, \data_counter_8[24]\, - \data_counter_8[25]\, \data_counter_8[26]\, - \data_counter_8[27]\, \data_counter_8[28]\, - \data_counter_8[29]\, \data_counter_8[30]\, - \data_counter_8[31]\, N_509, N_15, N_17, N_19, N_21, N_25, - N_27, N_29, N_31, N_33, N_35, N_43, N_45_0, N_47, N_51, - \state[5]_net_1\, N_53, N_55, N_57, N_61_0, N_63, N_65, - N_67, N_69, N_71, N_73, N_77, N_79, N_81, N_84, - \grant_counter_RNO[1]_net_1\, - \grant_counter_RNO[2]_net_1\, - \grant_counter_RNO[3]_net_1\, N_91, N_93, N_95, N_97, - N_99, N_101, N_103, N_105, N_107, N_109, N_202, N_111, - N_113, N_117, N_119, N_123, N_125, N_127, N_129, N_131, - N_133, N_135, N_137, N_139, N_141, N_143, N_188, N_343, - N_190, N_192, \Address[1]\, \Address[2]\, \Address[3]\, - \Address[25]\, \Address[26]\, \Address[27]\, - \Address[29]\, \Address[30]\, \Address[31]\, - \Address[18]\, \Address[19]\, \Address[21]\, - \Address[22]\, \Address[23]\, \Address[24]\, - \Address[11]\, \Address[12]\, \Address[13]\, - \Address[14]\, \Address[16]\, \Address[17]\, \Address[4]\, - \Address[6]\, \Address[7]\, \Address[8]\, \Address[9]\, - \Address[10]\, N_516, N_151, N_146, \Address[5]\, N_23, - N_523, \state_RNO[0]_net_1\, N_156, N_154, - \state_RNO[3]_net_1\, Store, Request, \data_send_ok\, - \data_send_ko\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - data_send_ok <= \data_send_ok\; - data_send_ko <= \data_send_ko\; - m26_m1_e <= \m26_m1_e\; - - \state_RNIVDV42_0[3]\ : OR2A - port map(A => \state[3]_net_1\, B => Fault, Y => N_522); - - \DMAIn.Address_RNI1PBS[1]\ : MX2 - port map(A => \Address[1]\, B => data_address(1), S => - time_select_0, Y => N_1018); - - un1_hresetn_inv_2_m66 : XOR2 - port map(A => N_66, B => \grant_counter[26]_net_1\, Y => - \un1_hresetn_inv_2_i[5]\); - - \state_RNIT2U41[4]\ : NOR3B - port map(A => un1_state_2_i_a2_m8_i_0, B => Grant_0, C => - un1_state_2_i_o2_0, Y => un1_state_2_i_a2_m8_i_2); - - \state_RNI3LQC[1]\ : OR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => un1_state_2_i_o2_0); - - \grant_counter_RNO_2[17]\ : OA1C - port map(A => \grant_counter[9]_net_1\, B => m26_m3_e, C - => \grant_counter[17]_net_1\, Y => - \grant_counter_RNO_2[17]_net_1\); - - \DMAIn.Address[7]\ : DFN1E1C0 - port map(D => N_27, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[7]\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_6 : NOR2B - port map(A => \data_counter[20]_net_1\, B => - \data_counter[27]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_6); - - \state[0]\ : DFN1C0 - port map(D => \state_RNO[0]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[0]_net_1\); - - \data_counter_RNILKKA[2]\ : NOR2B - port map(A => \data_counter[2]_net_1\, B => - \data_counter[3]_net_1\, Y => un1_state_5_i_o2_15); - - \state_RNI0P0IVI[4]\ : OR2B - port map(A => N_200, B => rstn, Y => N_202); - - \data_counter_RNO[31]\ : XA1C - port map(A => \data_counter[31]_net_1\, B => N_75, C => - N_198, Y => \data_counter_8[31]\); - - un1_hresetn_inv_2_m55_m6_0_a2_4_4 : NOR3B - port map(A => m55_m6_0_a2_4_0, B => - \grant_counter[14]_net_1\, C => m49_m6_0_a2_0, Y => - m55_m6_0_a2_4_4); - - un1_state_4_m51 : OR2B - port map(A => N_50_0, B => \data_counter[18]_net_1\, Y => - N_52); - - \data_counter_RNO[2]\ : AOI1 - port map(A => \un1_state_4_i[29]\, B => N_343, C => N_509, - Y => N_190); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_3 : OR2B - port map(A => \grant_counter[28]_net_1\, B => - \grant_counter[27]_net_1\, Y => m75_m6_0_a2_1); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y : NOR3C - port map(A => \grant_counter[13]_net_1\, B => N_28_0, C => - ADD_32x32_fast_I129_un1_Y_12, Y => I129_un1_Y); - - \data_counter_RNO[18]\ : XA1B - port map(A => \data_counter[18]_net_1\, B => N_50_0, C => - N_198, Y => \data_counter_8[18]\); - - \grant_counter_RNO[5]\ : XA1 - port map(A => \grant_counter[5]_net_1\, B => N_20_0_0, C - => N_202_0, Y => N_91); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_10 : NOR3C - port map(A => \data_counter[19]_net_1\, B => - \data_counter[16]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_6, Y => - ADD_32x32_fast_I129_un1_Y_10_0); - - \state_RNIKOCB2[3]\ : MX2A - port map(A => \state[5]_net_1\, B => Fault, S => - \state[3]_net_1\, Y => N_242); - - un1_state_4_m49 : NOR2B - port map(A => N_48, B => \data_counter[17]_net_1\, Y => - N_50_0); - - \DMAIn.Address_RNI99CS[2]\ : MX2C - port map(A => \Address[2]\, B => data_address(2), S => - time_select_0, Y => N_1019); - - \DMAIn.Address_RNI6BCP[17]\ : MX2C - port map(A => \Address[17]\, B => data_address(17), S => - time_select, Y => N_1034); - - un1_state_4_m19_a0_6_3 : NOR3B - port map(A => \data_counter[0]_net_1\, B => - \data_counter[4]_net_1\, C => \state[3]_net_1\, Y => - m19_a0_6_3); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_5 : OR2B - port map(A => \data_counter[18]_net_1\, B => - \data_counter[17]_net_1\, Y => m57_m6_0_a2_7_1); - - \grant_counter_RNO[26]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[5]\, Y => - N_133); - - \DMAIn.Address_RNINP361[30]\ : MX2C - port map(A => \Address[30]\, B => data_address(30), S => - time_select_0, Y => N_1047); - - \DMAIn.Address_RNO[20]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(20), Y - => N_59); - - un1_state_2_i_a2_m2 : MX2A - port map(A => hmaster_0(1), B => bco_msb_1(1), S => - un1_nhmaster_0_sqmuxa_1, Y => un1_state_2_i_a2_N_3_i_0_li); - - \grant_counter[0]\ : DFN1 - port map(D => \grant_counter_RNO[0]_net_1\, CLK => lclk_c, - Q => \grant_counter[0]_net_1\); - - \DMAIn.Address[6]\ : DFN1E1C0 - port map(D => N_25, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[6]\); - - un1_state_4_m53 : NOR2A - port map(A => \data_counter[19]_net_1\, B => N_52, Y => - N_54); - - un1_hresetn_inv_2_m52 : AX1E - port map(A => \grant_counter[18]_net_1\, B => N_50, C => - \grant_counter[19]_net_1\, Y => \un1_hresetn_inv_2_i[12]\); - - \grant_counter[20]\ : DFN1 - port map(D => N_121, CLK => lclk_c, Q => - \grant_counter[20]_net_1\); - - \DMAIn.Address_RNO[27]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(27), Y - => N_73); - - un1_hresetn_inv_2_m63_m6_0_a2_1 : OR2B - port map(A => \grant_counter[22]_net_1\, B => - \grant_counter[21]_net_1\, Y => m63_m6_0_a2_1); - - send_ko_RNIMB9E : OR3A - port map(A => state_0_0, B => \data_send_ko\, C => - \data_send_ok\, Y => N_1102); - - \data_counter_RNO[14]\ : XA1C - port map(A => \data_counter[14]_net_1\, B => N623, C => - N_198_0, Y => \data_counter_8[14]\); - - \data_counter_RNO[21]\ : XA1C - port map(A => \data_counter[21]_net_1\, B => N_56_0, C => - N_198, Y => \data_counter_8[21]\); - - \state_RNI4LQC[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => \state[0]_net_1\, Y - => un1_state_2_i_a2_m8_i_0); - - \DMAIn.Address[2]\ : DFN1E1C0 - port map(D => N_17, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[2]\); - - \DMAIn.Address[28]\ : DFN1E1C0 - port map(D => N_75_0, CLK => lclk_c, CLR => rstn, E => - N_154, Q => \Address[28]\); - - un1_state_4_m19 : MX2C - port map(A => nhmaster_1_i(0), B => - \state_RNITA375[4]_net_1\, S => m19_0_m8_i, Y => N_20_0); - - \grant_counter[26]\ : DFN1 - port map(D => N_133, CLK => lclk_c, Q => - \grant_counter[26]_net_1\); - - \grant_counter[29]\ : DFN1 - port map(D => N_139, CLK => lclk_c, Q => - \grant_counter[29]_net_1\); - - \grant_counter[1]\ : DFN1 - port map(D => \grant_counter_RNO[1]_net_1\, CLK => lclk_c, - Q => \grant_counter[1]_net_1\); - - \data_counter[16]\ : DFN1C0 - port map(D => \data_counter_8[16]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[16]_net_1\); - - \data_counter[13]\ : DFN1C0 - port map(D => \data_counter_8[13]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[13]_net_1\); - - un1_state_4_m74 : OR3C - port map(A => \data_counter[29]_net_1\, B => - \data_counter[30]_net_1\, C => N_72, Y => N_75); - - \grant_counter_RNISC3J[8]\ : NOR3 - port map(A => \grant_counter[30]_net_1\, B => - \grant_counter[8]_net_1\, C => \grant_counter[9]_net_1\, - Y => \state_ns_i_a2_0_i_o2_13[3]\); - - \state_RNI98EI[1]\ : AO1A - port map(A => data_send, B => \state_0[5]_net_1\, C => - \state[1]_net_1\, Y => \state_ns_i_a2_i_0_0[0]\); - - \state_RNIQDFIVJ_1[3]\ : AOI1 - port map(A => N_235, B => \state[3]_net_1\, C => N_348, Y - => N_198_0); - - un1_hresetn_inv_2_m21 : NOR2B - port map(A => N_21_0, B => \grant_counter[6]_net_1\, Y => - N_22_0); - - \state_0[5]\ : DFN1P0 - port map(D => N_4, CLK => lclk_c, PRE => rstn, Q => - \state_0[5]_net_1\); - - \DMAIn.Address[29]\ : DFN1E1C0 - port map(D => N_77, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[29]\); - - \grant_counter_RNO[3]\ : AO1 - port map(A => N_33_0_i_0, B => N_202_0, C => N_513, Y => - \grant_counter_RNO[3]_net_1\); - - \DMAIn.Address_RNI6E8P[10]\ : MX2C - port map(A => \Address[10]\, B => data_address(10), S => - time_select, Y => N_1027); - - un1_hresetn_inv_2_m20 : NOR2B - port map(A => N_20_0_0, B => \grant_counter[5]_net_1\, Y - => N_21_0); - - \grant_counter_RNI5E6K[31]\ : NOR3 - port map(A => \grant_counter[4]_net_1\, B => - \grant_counter[31]_net_1\, C => \grant_counter[14]_net_1\, - Y => \state_ns_i_a2_0_i_o2_16[3]\); - - un1_state_4_m28_m6_0_a2 : OR2B - port map(A => m28_m6_0_a2_4, B => N_20_0, Y => N623); - - un1_hresetn_inv_2_m26_m6_e_0_0 : NOR2A - port map(A => \grant_counter[10]_net_1\, B => m26_m6_e_0, Y - => m26_m6_e_0_0); - - \grant_counter_RNO[16]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[15]\, Y => - N_113); - - \grant_counter_RNITN6E[19]\ : NOR2 - port map(A => \grant_counter[19]_net_1\, B => - \grant_counter[21]_net_1\, Y => - \state_ns_i_a2_0_i_o2_7[3]\); - - \data_counter[11]\ : DFN1C0 - port map(D => \data_counter_8[11]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[11]_net_1\); - - \DMAIn.Address_RNIDD721[29]\ : MX2C - port map(A => \Address[29]\, B => data_address(29), S => - time_select_0, Y => N_1046); - - un1_hresetn_inv_2_m49_m6_0_a2_4 : NOR2A - port map(A => m45_m6_0_a2_2, B => m49_m6_0_a2_0, Y => - m49_m6_0_a2_4); - - \data_counter[8]\ : DFN1C0 - port map(D => \data_counter_8[8]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[8]_net_1\); - - \grant_counter_RNO[4]\ : NOR3C - port map(A => \un1_hresetn_inv_2_i_i[27]\, B => N_202_0, C - => N_354, Y => N_89); - - \DMAIn.Address[1]\ : DFN1E1C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[1]\); - - \DMAIn.Address[13]\ : DFN1E1C0 - port map(D => N_45_0, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[13]\); - - \data_counter_RNI3BF9[14]\ : NOR2 - port map(A => \data_counter[14]_net_1\, B => - \data_counter[15]_net_1\, Y => un1_state_5_i_o2_11); - - \DMAIn.Address[30]\ : DFN1E1C0 - port map(D => N_79, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[30]\); - - \DMAIn.Address_RNO[0]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(0), Y - => N_13); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \grant_counter[25]_net_1\, B => - \grant_counter[24]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_4, Y => - ADD_32x32_fast_I129_un1_Y_8); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_5 : NOR2B - port map(A => \grant_counter[23]_net_1\, B => - \grant_counter[14]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_5); - - \grant_counter_RNIQ76E[22]\ : NOR2 - port map(A => \grant_counter[22]_net_1\, B => - \grant_counter[24]_net_1\, Y => - \state_ns_i_a2_0_i_o2_8[3]\); - - \DMAIn.Address_RNO[10]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(10), Y - => N_33); - - \data_counter_RNIC7H61[10]\ : NOR3C - port map(A => un1_state_5_i_o2_5, B => un1_state_5_i_o2_4, - C => un1_state_5_i_o2_19, Y => un1_state_5_i_o2_25); - - un1_state_4_ADD_32x32_fast_I129_un1_Y : NOR2A - port map(A => ADD_32x32_fast_I129_un1_Y_13, B => N623, Y - => I129_un1_Y_0); - - \DMAIn.Address_RNO[5]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(5), Y => - N_23); - - un1_hresetn_inv_2_m75_m6_0_a2_3 : NOR2B - port map(A => m75_m6_0_a2_2, B => m23_m6_0_a2_4, Y => - m75_m6_0_a2_3); - - send_ok : DFN1E1C0 - port map(D => \state[0]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_146, Q => \data_send_ok\); - - \grant_counter_RNO[9]\ : XA1A - port map(A => \grant_counter[9]_net_1\, B => N_24_0, C => - N_202_0, Y => N_99); - - \DMAIn.Address_RNIA0321[22]\ : MX2C - port map(A => \Address[22]\, B => data_address(22), S => - time_select_0, Y => N_1039); - - \grant_counter_RNI7OKM1[1]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_9[3]\, B => - \state_ns_i_a2_0_i_o2_8[3]\, C => - \state_ns_i_a2_0_i_o2_21[3]\, Y => - \state_ns_i_a2_0_i_o2_26[3]\); - - \DMAIn.Address[31]\ : DFN1E1C0 - port map(D => N_81, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[31]\); - - \data_counter_RNIVSLA[7]\ : NOR2 - port map(A => \data_counter[7]_net_1\, B => - \data_counter[8]_net_1\, Y => un1_state_5_i_o2_3); - - \grant_counter[25]\ : DFN1 - port map(D => N_131, CLK => lclk_c, Q => - \grant_counter[25]_net_1\); - - \DMAIn.Address_RNO[17]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(17), Y - => N_53); - - un1_state_4_m18 : OR3C - port map(A => \data_counter[2]_net_1\, B => N_17_0_0, C => - \data_counter[3]_net_1\, Y => N_19_0_0); - - un1_state_4_m55 : OR2B - port map(A => N_54, B => \data_counter[20]_net_1\, Y => - N_56_0); - - un1_state_4_m28_m6_0_a2_4_6 : NOR3C - port map(A => \data_counter[12]_net_1\, B => - \data_counter[10]_net_1\, C => m28_m6_0_a2_4_4, Y => - m28_m6_0_a2_4_6); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \data_counter[23]_net_1\, B => - \data_counter[24]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_1_0); - - un1_hresetn_inv_2_m71 : OR3C - port map(A => \grant_counter[27]_net_1\, B => N_68_0, C => - \grant_counter[28]_net_1\, Y => N_72_0); - - \state[4]\ : DFN1C0 - port map(D => N_84, CLK => lclk_c, CLR => rstn, Q => - \state[4]_net_1\); - - \grant_counter_RNO[6]\ : XA1 - port map(A => \grant_counter[6]_net_1\, B => N_21_0, C => - N_202_0, Y => N_93); - - \state_0_RNIOT0C[5]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_send, Y => - Request_5); - - \data_counter_RNO[22]\ : XA1C - port map(A => \data_counter[22]_net_1\, B => N_58, C => - N_198, Y => \data_counter_8[22]\); - - \data_counter_RNI9IEF2[31]\ : NOR3C - port map(A => un1_state_5_i_o2_17, B => un1_state_5_i_o2_16, - C => un1_state_5_i_o2_25, Y => un1_state_5_i_o2_28); - - \data_counter_RNI6P8L[1]\ : NOR3C - port map(A => \data_counter[1]_net_1\, B => - \data_counter[0]_net_1\, C => un1_state_5_i_o2_15, Y => - un1_state_5_i_o2_23); - - un1_hresetn_inv_2_m70 : AX1E - port map(A => \grant_counter[27]_net_1\, B => N_68_0, C => - \grant_counter[28]_net_1\, Y => \un1_hresetn_inv_2_i[3]\); - - \state_RNIQDFIVJ_0[3]\ : AOI1 - port map(A => N_235, B => \state[3]_net_1\, C => N_348, Y - => N_198); - - \grant_counter_RNO_8[17]\ : NOR3C - port map(A => \grant_counter[11]_net_1\, B => - \grant_counter[16]_net_1\, C => \grant_counter[14]_net_1\, - Y => \grant_counter_0_i_6_tz_2[17]\); - - \DMAIn.Request_RNIBSA9\ : MX2 - port map(A => Request, B => Request_0, S => time_select, Y - => N_1081); - - \DMAIn.Address_RNO[28]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(28), Y - => N_75_0); - - \grant_counter_RNO[20]\ : NOR2A - port map(A => N_202_0, B => grant_counter_0_i_20_N_14_i, Y - => N_121); - - un1_state_4_m21 : NOR3C - port map(A => \data_counter[5]_net_1\, B => N_20_0, C => - \data_counter[6]_net_1\, Y => N_22_0_0); - - un1_hresetn_inv_2_m19 : NOR2B - port map(A => N_19_0, B => \grant_counter[4]_net_1\, Y => - N_20_0_0); - - un1_hresetn_inv_2_m59 : NOR3C - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - \grant_counter[22]_net_1\, Y => N_60); - - \DMAIn.Address_RNI35621[27]\ : MX2C - port map(A => \Address[27]\, B => data_address(27), S => - time_select_0, Y => N_1044); - - \grant_counter_RNO[22]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[9]\, Y => - N_125); - - un1_state_4_m22 : NOR2B - port map(A => N_22_0_0, B => \data_counter[7]_net_1\, Y => - N_23_0_0); - - \data_counter[3]\ : DFN1C0 - port map(D => N_192, CLK => lclk_c, CLR => rstn, Q => - \data_counter[3]_net_1\); - - un1_hresetn_inv_2_m67_m6_0_a2_4_2 : NOR2B - port map(A => \grant_counter[11]_net_1\, B => - \grant_counter[10]_net_1\, Y => m67_m6_0_a2_4_2); - - \DMAIn.Address_RNI9L8L[16]\ : MX2C - port map(A => \Address[16]\, B => data_address(16), S => - time_select, Y => N_1033); - - \state[5]\ : DFN1P0 - port map(D => N_4, CLK => lclk_c, PRE => rstn, Q => - \state[5]_net_1\); - - \grant_counter_RNO[30]\ : XA1 - port map(A => \grant_counter[30]_net_1\, B => I129_un1_Y, C - => N_202, Y => N_141); - - \data_counter_RNO[8]\ : XA1B - port map(A => \data_counter[8]_net_1\, B => N_23_0_0, C => - N_198_0, Y => \data_counter_8[8]\); - - \data_counter[28]\ : DFN1C0 - port map(D => \data_counter_8[28]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[28]_net_1\); - - \data_counter[10]\ : DFN1C0 - port map(D => \data_counter_8[10]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[10]_net_1\); - - \data_counter_RNO[13]\ : XA1C - port map(A => \data_counter[13]_net_1\, B => N_28_0_0, C - => N_198_0, Y => \data_counter_8[13]\); - - \data_counter[12]\ : DFN1C0 - port map(D => \data_counter_8[12]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[12]_net_1\); - - \data_counter[24]\ : DFN1C0 - port map(D => \data_counter_8[24]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[24]_net_1\); - - un1_hresetn_inv_2_m23_m6_0_a2_4_2 : NOR2B - port map(A => \grant_counter[5]_net_1\, B => - \grant_counter[6]_net_1\, Y => m23_m6_0_a2_4_2); - - GND_i : GND - port map(Y => \GND\); - - \DMAIn.Address_RNO[26]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(26), Y - => N_71); - - un1_state_4_m23 : NOR2B - port map(A => N_23_0_0, B => \data_counter[8]_net_1\, Y => - N_24_0_0); - - \DMAIn.Address_RNO[23]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(23), Y - => N_65); - - \DMAIn.Address[12]\ : DFN1E1C0 - port map(D => N_43, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[12]\); - - un1_state_4_m28_m6_0_a2_4_2 : NOR2B - port map(A => \data_counter[8]_net_1\, B => - \data_counter[9]_net_1\, Y => m28_m6_0_a2_4_2); - - un1_state_4_m19_a0_6_1 : NOR2B - port map(A => \data_counter[1]_net_1\, B => - \data_counter[2]_net_1\, Y => m19_a1_6_1); - - \data_counter[27]\ : DFN1C0 - port map(D => \data_counter_8[27]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[27]_net_1\); - - un1_hresetn_inv_2_m65 : OR3C - port map(A => un1_hresetn_inv_i_0_a2_0, B => m63_m6_0_a2_6, - C => \grant_counter[25]_net_1\, Y => N_66); - - \grant_counter_RNO[1]\ : AO1 - port map(A => N_31_0_i_0, B => N_202_0, C => N_513, Y => - \grant_counter_RNO[1]_net_1\); - - \DMAIn.Address[5]\ : DFN1E1C0 - port map(D => N_23, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_counter_RNO[10]\ : XA1B - port map(A => \data_counter[10]_net_1\, B => N_25_0_0, C - => N_198_0, Y => \data_counter_8[10]\); - - un1_hresetn_inv_2_m17_m2_e_2 : NOR3B - port map(A => m17_m2_e_0, B => \grant_counter[1]_net_1\, C - => N_241, Y => m17_m2_e_2); - - \grant_counter_RNO_5[17]\ : NOR2B - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[17]_net_1\, Y => - \grant_counter_0_i_a0_0[17]\); - - \grant_counter_RNO[28]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[3]\, Y => - N_137); - - un1_state_4_m19_a1_6_3 : NOR3C - port map(A => \data_counter[0]_net_1\, B => - \data_counter[4]_net_1\, C => m19_a1_6_1, Y => m19_a1_6_3); - - \grant_counter[17]\ : DFN1 - port map(D => N_115, CLK => lclk_c, Q => - \grant_counter[17]_net_1\); - - \DMAIn.Burst_RNILOR3\ : NOR2A - port map(A => Burst, B => time_select, Y => un7_dmain(66)); - - \DMAIn.Address_RNI23NR[4]\ : MX2C - port map(A => \Address[4]\, B => data_address(4), S => - time_select, Y => N_1021); - - un1_state_4_m19_a1_6_4 : NOR3A - port map(A => \data_counter[3]_net_1\, B => - \state[0]_net_1\, C => un1_state_2_i_o2_0, Y => - m19_a1_6_4); - - \DMAIn.Address_RNIR3NR[9]\ : MX2C - port map(A => \Address[9]\, B => data_address(9), S => - time_select, Y => N_1026); - - \data_counter_RNO[27]\ : XA1C - port map(A => \data_counter[27]_net_1\, B => N_68, C => - N_198, Y => \data_counter_8[27]\); - - \grant_counter_RNO[24]\ : XA1A - port map(A => \grant_counter[24]_net_1\, B => N_62, C => - N_202, Y => N_129); - - un1_state_4_m19_0_m8_i_1 : NOR3C - port map(A => Grant_0, B => \state[4]_net_1\, C => - iosn_0(93), Y => m19_0_m8_i_1); - - \data_counter[1]\ : DFN1C0 - port map(D => N_188, CLK => lclk_c, CLR => rstn, Q => - \data_counter[1]_net_1\); - - \grant_counter_RNO[10]\ : XA1 - port map(A => \grant_counter[10]_net_1\, B => N_25_0, C => - N_202_0, Y => N_101); - - \grant_counter[30]\ : DFN1 - port map(D => N_141, CLK => lclk_c, Q => - \grant_counter[30]_net_1\); - - \grant_counter[9]\ : DFN1 - port map(D => N_99, CLK => lclk_c, Q => - \grant_counter[9]_net_1\); - - \data_counter_RNO_1[0]\ : AO1D - port map(A => N_516_2, B => N_508, C => - \data_counter_8_i_0[0]\, Y => \data_counter_8_i_0_0[0]\); - - \data_counter_RNO[6]\ : NOR2 - port map(A => N_36_0, B => N_198_0, Y => - \data_counter_8[6]\); - - \state_RNIB9BF8J[4]\ : NOR2 - port map(A => \state[4]_net_1\, B => N_354, Y => N_513); - - \DMAIn.Address_RNO[30]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(30), Y - => N_79); - - un1_hresetn_inv_2_m26_m6_e_3 : NOR3B - port map(A => m26_m6_e_1, B => \m26_m1_e\, C => N_241, Y - => m26_m6_e_3); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[18]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_4); - - \grant_counter_RNO[12]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[19]\, Y - => N_105); - - \DMAIn.Address_RNO[8]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(8), Y - => N_29); - - \DMAIn.Address[9]\ : DFN1E1C0 - port map(D => N_31, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[9]\); - - un1_state_4_m61 : NOR3C - port map(A => N_20_0, B => m59_0, C => - \data_counter[23]_net_1\, Y => N_62_0); - - un1_state_4_m26 : OR2B - port map(A => N_26_0, B => \data_counter[11]_net_1\, Y => - N_27_0); - - \grant_counter[18]\ : DFN1 - port map(D => N_117, CLK => lclk_c, Q => - \grant_counter[18]_net_1\); - - \data_counter_RNIVD2A[30]\ : NOR2 - port map(A => \data_counter[30]_net_1\, B => - \data_counter[4]_net_1\, Y => un1_state_5_i_o2_1); - - un1_hresetn_inv_2_m75_m6_0_a2_0 : NOR2B - port map(A => \grant_counter[30]_net_1\, B => - \grant_counter[29]_net_1\, Y => m75_m6_0_a2_0); - - \data_counter_RNO[4]\ : XA1C - port map(A => \data_counter[4]_net_1\, B => N_19_0_0, C => - N_198_0, Y => \data_counter_8[4]\); - - \data_counter[29]\ : DFN1C0 - port map(D => \data_counter_8[29]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[29]_net_1\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \grant_counter[29]_net_1\, B => - \grant_counter[19]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_1); - - \state_RNIGSLM7[1]\ : AO1D - port map(A => N_346, B => N_246, C => - \state_ns_i_a2_i_0_0[0]\, Y => N_4); - - \DMAIn.Address_RNO[18]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(18), Y - => N_55); - - \DMAIn.Address_RNIR51Q[28]\ : MX2C - port map(A => \Address[28]\, B => data_address(28), S => - time_select_0, Y => N_1045); - - \DMAIn.Address[10]\ : DFN1E1C0 - port map(D => N_33, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[10]\); - - un1_state_4_m31 : XNOR2 - port map(A => N_17_0_0, B => \data_counter[2]_net_1\, Y => - \un1_state_4_i[29]\); - - \DMAIn.Address_RNO[29]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(29), Y - => N_77); - - un1_state_4_m57_m6_0_a2_7_2 : NOR2B - port map(A => \data_counter[19]_net_1\, B => - \data_counter[20]_net_1\, Y => m57_m6_0_a2_7_2); - - \grant_counter_RNI6OES[26]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_5[3]\, B => - \grant_counter[27]_net_1\, C => \grant_counter[26]_net_1\, - Y => \state_ns_i_a2_0_i_o2_18[3]\); - - un1_state_4_m32 : AX1E - port map(A => \data_counter[2]_net_1\, B => N_17_0_0, C => - \data_counter[3]_net_1\, Y => \un1_state_4_i[28]\); - - \data_counter[2]\ : DFN1C0 - port map(D => N_190, CLK => lclk_c, CLR => rstn, Q => - \data_counter[2]_net_1\); - - \state_RNI9IFTVI[4]\ : AO1 - port map(A => \state[4]_net_1\, B => Grant, C => - un1_state_2_i_o2_0, Y => N_243_i); - - \DMAIn.Address_RNIUG521[26]\ : MX2C - port map(A => \Address[26]\, B => data_address(26), S => - time_select_0, Y => N_1043); - - \DMAIn.Address[11]\ : DFN1E1C0 - port map(D => N_35, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[11]\); - - un1_hresetn_inv_2_m23_m6_0_a2_4_5 : NOR3C - port map(A => \grant_counter[4]_net_1\, B => - \grant_counter[3]_net_1\, C => m23_m6_0_a2_4_2, Y => - m23_m6_0_a2_4_5); - - \grant_counter[21]\ : DFN1 - port map(D => N_123, CLK => lclk_c, Q => - \grant_counter[21]_net_1\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_7 : NOR3C - port map(A => \data_counter[22]_net_1\, B => - \data_counter[21]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_1_0, Y => - ADD_32x32_fast_I129_un1_Y_7); - - \grant_counter[22]\ : DFN1 - port map(D => N_125, CLK => lclk_c, Q => - \grant_counter[22]_net_1\); - - \DMAIn.Address_RNIE74U[18]\ : MX2C - port map(A => \Address[18]\, B => data_address(18), S => - time_select_0, Y => N_1035); - - \DMAIn.Address[14]\ : DFN1E1C0 - port map(D => N_47, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[14]\); - - un1_state_4_m63 : NOR2B - port map(A => N_62_0, B => \data_counter[24]_net_1\, Y => - N_64); - - un1_hresetn_inv_2_m23_m6_0_a2_4 : NOR2B - port map(A => m23_m6_0_a2_4_6, B => m23_m6_0_a2_4_5, Y => - m23_m6_0_a2_4); - - un1_state_4_m44 : AX1E - port map(A => N_20_0, B => m43_0, C => - \data_counter[15]_net_1\, Y => N_45); - - \DMAIn.Address_RNIPS421[25]\ : MX2C - port map(A => \Address[25]\, B => data_address(25), S => - time_select_0, Y => N_1042); - - un1_hresetn_inv_2_m45_m6_0_a2_1 : OR2B - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[11]_net_1\, Y => m49_m6_0_a2_2); - - \state_RNO_0[0]\ : OR2A - port map(A => \state[0]_net_1\, B => Ready, Y => N_523); - - \grant_counter_RNO[18]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[13]\, Y => - N_117); - - \DMAIn.Address_RNINEAP[14]\ : MX2C - port map(A => \Address[14]\, B => data_address(14), S => - time_select, Y => N_1031); - - \data_counter[0]\ : DFN1C0 - port map(D => N_186, CLK => lclk_c, CLR => rstn, Q => - \data_counter[0]_net_1\); - - \grant_counter_RNO[27]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[4]\, Y => - N_135); - - \DMAIn.Address_RNO[16]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(16), Y - => N_51); - - \grant_counter_RNO[14]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i_0[17]\, Y - => N_109); - - \DMAIn.Address_RNIB29P[11]\ : MX2C - port map(A => \Address[11]\, B => data_address(11), S => - time_select, Y => N_1028); - - un1_state_4_m57_m6_0_a2_7_0 : NOR2B - port map(A => \data_counter[21]_net_1\, B => - \data_counter[14]_net_1\, Y => m57_m6_0_a2_7_0); - - un1_hresetn_inv_2_m50 : XNOR2 - port map(A => N_50, B => \grant_counter[18]_net_1\, Y => - \un1_hresetn_inv_2_i[13]\); - - \DMAIn.Address_RNO[13]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(13), Y - => N_45_0); - - un1_state_4_m25 : NOR2B - port map(A => N_25_0_0, B => \data_counter[10]_net_1\, Y - => N_26_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_hresetn_inv_2_m55_m6_0_a2_4 : NOR2B - port map(A => m55_m6_0_a2_4_4, B => m55_m6_0_a2_4_3, Y => - m55_m6_0_a2_4); - - un1_state_4_m59_0 : NOR3C - port map(A => m28_m6_0_a2_4, B => m57_m6_0_a2_7_5, C => - \data_counter[22]_net_1\, Y => m59_0); - - \DMAIn.Address_RNIP8BS[0]\ : MX2 - port map(A => \Address[0]\, B => data_address(0), S => - time_select_0, Y => Address_RNIP8BS(0)); - - \state_RNI9ALP[0]\ : OR2 - port map(A => N_518_1, B => N_516_2, Y => N_516); - - \DMAIn.Address_RNO[7]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(7), Y - => N_27); - - \data_counter_RNO_2[0]\ : NOR2B - port map(A => \un1_state_4_i[31]\, B => - \data_counter_8_i_0_tz[0]\, Y => \data_counter_8_i_0[0]\); - - \data_counter_RNO[16]\ : XA1B - port map(A => \data_counter[16]_net_1\, B => N_46, C => - N_198_0, Y => \data_counter_8[16]\); - - un1_hresetn_inv_2_m68 : XNOR2 - port map(A => N_68_0, B => \grant_counter[27]_net_1\, Y => - \un1_hresetn_inv_2_i[4]\); - - \data_counter_RNO[29]\ : XA1B - port map(A => \data_counter[29]_net_1\, B => N_72, C => - N_198, Y => \data_counter_8[29]\); - - un1_hresetn_inv_2_m16 : OR3C - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => \grant_counter[1]_net_1\, Y => - N_17_0); - - un1_hresetn_inv_2_m56 : XNOR2 - port map(A => N_56, B => \grant_counter[21]_net_1\, Y => - \un1_hresetn_inv_2_i[10]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_2 : NOR2B - port map(A => \grant_counter[21]_net_1\, B => - \grant_counter[22]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_2); - - \state_RNIQDFIVJ[3]\ : OR3A - port map(A => \state[3]_net_1\, B => N_235, C => N_348, Y - => N_343); - - \grant_counter_RNI923D[7]\ : NOR2 - port map(A => \grant_counter[7]_net_1\, B => - \grant_counter[20]_net_1\, Y => - \state_ns_i_a2_0_i_o2_3[3]\); - - \DMAIn.Address[8]\ : DFN1E1C0 - port map(D => N_29, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[8]\); - - \state_RNO[4]\ : AO1 - port map(A => \state[4]_net_1\, B => Grant, C => Request_5, - Y => N_84); - - \grant_counter_RNIQF6E_0[15]\ : OR2B - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[13]_net_1\, Y => - \grant_counter_0_i_6_tz_1[17]\); - - \DMAIn.Address_RNO[19]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(19), Y - => N_57); - - \DMAIn.Address[0]\ : DFN1E1C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[0]\); - - un1_hresetn_inv_2_m25 : OR2B - port map(A => N_25_0, B => \grant_counter[10]_net_1\, Y => - N_26_0_0); - - un1_hresetn_inv_2_m26_m1_e : NOR3 - port map(A => m26tt_N_7, B => Grant_1_0, C => - nhmaster_1_i(0), Y => \m26_m1_e\); - - un1_hresetn_inv_2_m23_m6_0_a2 : OR2B - port map(A => un1_hresetn_inv_i_0, B => m23_m6_0_a2_4, Y - => N_24_0); - - \state_RNI3LQC[0]\ : OR2 - port map(A => \state[3]_net_1\, B => \state[0]_net_1\, Y - => N_516_2); - - \state_RNO[2]\ : AO1C - port map(A => N_346, B => N_246, C => N_522, Y => N_151); - - \grant_counter_RNO[17]\ : NOR3 - port map(A => \grant_counter_RNO_0[17]_net_1\, B => - \grant_counter_0_i_0_0[17]\, C => - \grant_counter_RNO_2[17]_net_1\, Y => N_115); - - \state_RNIBSIG1J[3]\ : NOR2A - port map(A => un1_hresetn_inv_i_0_a2_0, B => Grant, Y => - un1_hresetn_inv_i_0); - - \grant_counter_RNO_1[17]\ : OR2A - port map(A => N_202_0, B => \grant_counter_0_i_5[17]\, Y - => \grant_counter_0_i_0_0[17]\); - - un1_state_4_m71 : NOR2 - port map(A => m71_0, B => N_68, Y => N_72); - - \grant_counter[10]\ : DFN1 - port map(D => N_101, CLK => lclk_c, Q => - \grant_counter[10]_net_1\); - - \DMAIn.Address_RNIVO6L[23]\ : MX2C - port map(A => \Address[23]\, B => data_address(23), S => - time_select, Y => N_1040); - - \data_counter_RNI9BF9[16]\ : NOR2 - port map(A => \data_counter[16]_net_1\, B => - \data_counter[19]_net_1\, Y => un1_state_5_i_o2_12); - - \state_RNI6TKGVI[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => Grant, Y => N_200); - - \data_counter_RNO[28]\ : XA1C - port map(A => \data_counter[28]_net_1\, B => N_70, C => - N_198, Y => \data_counter_8[28]\); - - \grant_counter[24]\ : DFN1 - port map(D => N_129, CLK => lclk_c, Q => - \grant_counter[24]_net_1\); - - \data_counter_RNO[15]\ : NOR2 - port map(A => N_45, B => N_198_0, Y => \data_counter_8[15]\); - - \grant_counter_RNO_3[20]\ : NOR3C - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[19]_net_1\, C => \grant_counter[14]_net_1\, - Y => grant_counter_0_i_20_b0_0_o2_2); - - un1_state_4_m65 : NOR2B - port map(A => N_64, B => \data_counter[25]_net_1\, Y => - N_66_0); - - \grant_counter[16]\ : DFN1 - port map(D => N_113, CLK => lclk_c, Q => - \grant_counter[16]_net_1\); - - \DMAIn.Address[15]\ : DFN1E1C0 - port map(D => N_49, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[15]\); - - un1_state_4_m35 : AX1E - port map(A => \data_counter[5]_net_1\, B => N_20_0, C => - \data_counter[6]_net_1\, Y => N_36_0); - - \grant_counter[19]\ : DFN1 - port map(D => N_119, CLK => lclk_c, Q => - \grant_counter[19]_net_1\); - - \DMAIn.Store_RNIVHK6\ : MX2 - port map(A => Store, B => Store_0, S => time_select, Y => - N_1082); - - un1_hresetn_inv_2_m32 : AX1C - port map(A => rstn, B => m17_m2_e_3, C => - \grant_counter[3]_net_1\, Y => N_33_0_i_0); - - un1_hresetn_inv_2_m27 : NOR3C - port map(A => rstn, B => m26_m6_e_3, C => - \grant_counter[12]_net_1\, Y => N_28_0); - - un1_state_4_m28_m6_0_a2_4_4 : NOR3C - port map(A => \data_counter[5]_net_1\, B => - \data_counter[13]_net_1\, C => \data_counter[11]_net_1\, - Y => m28_m6_0_a2_4_4); - - \state_RNIJH0E9[3]\ : AO1C - port map(A => N_235, B => \state[3]_net_1\, C => N_242, Y - => N_154); - - \data_counter[18]\ : DFN1C0 - port map(D => \data_counter_8[18]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[18]_net_1\); - - un1_state_4_m27 : OR3C - port map(A => \data_counter[11]_net_1\, B => - \data_counter[12]_net_1\, C => N_26_0, Y => N_28_0_0); - - un1_hresetn_inv_2_m75_0 : AX1A - port map(A => rstoutl_RNIGJKSJO, B => m75_m6_0_a2, C => - \grant_counter[31]_net_1\, Y => \un1_hresetn_inv_2_i[0]\); - - \DMAIn.Address_RNO[3]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(3), Y - => N_19); - - \DMAIn.Address_RNIIQ9P[13]\ : MX2C - port map(A => \Address[13]\, B => data_address(13), S => - time_select, Y => N_1030); - - \data_counter_RNO[24]\ : XA1B - port map(A => \data_counter[24]_net_1\, B => N_62_0, C => - N_198, Y => \data_counter_8[24]\); - - un1_state_4_m43_0 : NOR2B - port map(A => \data_counter[14]_net_1\, B => m28_m6_0_a2_4, - Y => m43_0); - - \grant_counter_RNO_7[17]\ : NOR2A - port map(A => \grant_counter_0_i_6_tz_1_0[17]\, B => - \grant_counter_0_i_6_tz_1[17]\, Y => - \grant_counter_0_i_6_tz_3[17]\); - - \data_counter[14]\ : DFN1C0 - port map(D => \data_counter_8[14]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[14]_net_1\); - - \grant_counter_RNO[23]\ : XA1 - port map(A => \grant_counter[23]_net_1\, B => N_60, C => - N_202, Y => N_127); - - \DMAIn.Address_RNO[21]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(21), Y - => N_61_0); - - un1_hresetn_inv_2_m64 : AX1E - port map(A => un1_hresetn_inv_i_0_a2_0, B => m63_m6_0_a2_6, - C => \grant_counter[25]_net_1\, Y => - \un1_hresetn_inv_2_i[6]\); - - \grant_counter_RNO_0[20]\ : AX1E - port map(A => N_28_0, B => grant_counter_0_i_20_b0_0_o2_4, - C => \grant_counter[20]_net_1\, Y => - grant_counter_0_i_20_N_14_i); - - \DMAIn.Address[23]\ : DFN1E1C0 - port map(D => N_65, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[23]\); - - \grant_counter[23]\ : DFN1 - port map(D => N_127, CLK => lclk_c, Q => - \grant_counter[23]_net_1\); - - \data_counter[17]\ : DFN1C0 - port map(D => \data_counter_8[17]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[17]_net_1\); - - un1_state_4_m19_a0_6_4 : NOR3B - port map(A => \data_counter[3]_net_1\, B => m19_a1_6_1, C - => \state[0]_net_1\, Y => m19_a0_6_4); - - \data_counter_RNI31IJ[31]\ : NOR3A - port map(A => un1_state_5_i_o2_1, B => - \data_counter[13]_net_1\, C => \data_counter[31]_net_1\, - Y => un1_state_5_i_o2_16); - - un1_state_2_i_a2_m8_i_a4 : OR2B - port map(A => un1_state_2_i_a2_N_3_i_0_li, B => l1_0_m(1), - Y => \un1_state_2_i_a2_m8_i_a4\); - - \grant_counter_RNO_2[20]\ : NOR2B - port map(A => \grant_counter[17]_net_1\, B => - \grant_counter[18]_net_1\, Y => - grant_counter_0_i_20_b0_0_o2_1); - - \data_counter[31]\ : DFN1C0 - port map(D => \data_counter_8[31]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[31]_net_1\); - - un1_hresetn_inv_2_m17_m2_e_3 : NOR2A - port map(A => m17_m2_e_2, B => Grant, Y => m17_m2_e_3); - - un1_hresetn_inv_2_m26tt_m3_i_a4 : NOR2B - port map(A => nhmaster_1_iv_0(1), B => bco_msb_1_m(1), Y - => m26tt_N_7); - - \grant_counter_RNINUT88J[1]\ : OR2A - port map(A => un1_hresetn_inv_i_0, B => N_246, Y => N_354); - - un1_state_4_m29 : XNOR2 - port map(A => \data_counter[0]_net_1\, B => N_8, Y => - \un1_state_4_i[31]\); - - \DMAIn.Address_RNIEMR31[5]\ : MX2C - port map(A => \Address[5]\, B => data_address(5), S => - time_select, Y => N_1022); - - \data_counter_RNO_0[0]\ : OR2 - port map(A => \state[0]_net_1\, B => N_235, Y => - \data_counter_8_i_a4_2_0[0]\); - - \grant_counter[31]\ : DFN1 - port map(D => N_143, CLK => lclk_c, Q => - \grant_counter[31]_net_1\); - - \grant_counter[15]\ : DFN1 - port map(D => N_111, CLK => lclk_c, Q => - \grant_counter[15]_net_1\); - - \DMAIn.Address_RNO[1]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(1), Y - => N_15); - - un1_hresetn_inv_2_ADD_32x32_fast_I174_Y_0 : AX1E - port map(A => \grant_counter[13]_net_1\, B => N_28_0, C => - \grant_counter[14]_net_1\, Y => - \un1_hresetn_inv_2_i_0[17]\); - - \grant_counter[6]\ : DFN1 - port map(D => N_93, CLK => lclk_c, Q => - \grant_counter[6]_net_1\); - - \DMAIn.Address_RNO[22]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(22), Y - => N_63); - - \data_counter[19]\ : DFN1C0 - port map(D => \data_counter_8[19]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[19]_net_1\); - - \DMAIn.Address[16]\ : DFN1E1C0 - port map(D => N_51, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[16]\); - - un1_state_4_m60 : AX1E - port map(A => N_20_0, B => m59_0, C => - \data_counter[23]_net_1\, Y => N_61); - - \DMAIn.Address_RNI79VP[15]\ : MX2C - port map(A => \Address[15]\, B => data_address(15), S => - time_select_0, Y => N_1032); - - \grant_counter[8]\ : DFN1 - port map(D => N_97, CLK => lclk_c, Q => - \grant_counter[8]_net_1\); - - \state_RNI6R78T9[4]\ : OR3C - port map(A => iosn_0(93), B => un1_state_2_i_a2_m8_i_2, C - => \un1_state_2_i_a2_m8_i_a4\, Y => - \state_RNI6R78T9[4]_net_1\); - - un1_state_4_m30 : AX1E - port map(A => N_8, B => \data_counter[0]_net_1\, C => - \data_counter[1]_net_1\, Y => \un1_state_4_i[30]\); - - \DMAIn.Address_RNO[24]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(24), Y - => N_67); - - \data_counter_RNO[3]\ : AOI1 - port map(A => \un1_state_4_i[28]\, B => N_343, C => N_509, - Y => N_192); - - \DMAIn.Address_RNIEJMR[7]\ : MX2C - port map(A => \Address[7]\, B => data_address(7), S => - time_select, Y => N_1024); - - \DMAIn.Address_RNO[25]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(25), Y - => N_69); - - \data_counter_RNO[5]\ : XA1B - port map(A => \data_counter[5]_net_1\, B => N_20_0, C => - N_198_0, Y => \data_counter_8[5]\); - - un1_state_4_m67 : OR2B - port map(A => N_66_0, B => \data_counter[26]_net_1\, Y => - N_68); - - \grant_counter_RNO[13]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[18]\, Y - => N_107); - - \DMAIn.Address_RNIJ4SP[20]\ : MX2C - port map(A => \Address[20]\, B => data_address(20), S => - time_select_0, Y => Address_RNIJ4SP(20)); - - un1_hresetn_inv_2_m26_m3_e : OR3C - port map(A => \m26_m1_e\, B => m23_m6_0_a2_4, C => - un1_hresetn_inv_i_0_a2_0, Y => m26_m3_e); - - un1_hresetn_inv_2_m42 : XNOR2 - port map(A => N_28_0, B => \grant_counter[13]_net_1\, Y => - \un1_hresetn_inv_2_i[18]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_10 : NOR3B - port map(A => ADD_32x32_fast_I129_un1_Y_2, B => - ADD_32x32_fast_I129_un1_Y_1, C => m49_m6_0_a2_0, Y => - ADD_32x32_fast_I129_un1_Y_10); - - un1_hresetn_inv_2_m49_m6_0_a2_5 : NOR3B - port map(A => \grant_counter_0_i_6_tz_1_0[17]\, B => - m49_m6_0_a2_4, C => m49_m6_0_a2_2, Y => m49_m6_0_a2_5); - - \state_RNIRHSB[0]\ : OR2B - port map(A => \state[0]_net_1\, B => Ready, Y => N_346); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO[3]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[3]_net_1\); - - \DMAIn.Address_RNIH0DT[24]\ : MX2C - port map(A => \Address[24]\, B => data_address(24), S => - time_select, Y => N_1041); - - \data_counter_RNINO5E2[24]\ : NOR3C - port map(A => un1_state_5_i_o2_21, B => un1_state_5_i_o2_20, - C => un1_state_5_i_o2_27, Y => un1_state_5_i_o2_29); - - un1_hresetn_inv_2_m55_m6_0_a2_4_3 : NOR3B - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[18]_net_1\, C => - \grant_counter_0_i_a0_2[17]\, Y => m55_m6_0_a2_4_3); - - \data_counter_RNIAQUI[29]\ : NOR3A - port map(A => un1_state_5_i_o2_11, B => - \data_counter[11]_net_1\, C => \data_counter[29]_net_1\, - Y => un1_state_5_i_o2_21); - - \grant_counter_RNIANBS[11]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_15[3]\, B => - \grant_counter[13]_net_1\, C => \grant_counter[11]_net_1\, - Y => \state_ns_i_a2_0_i_o2_23[3]\); - - \data_counter[7]\ : DFN1C0 - port map(D => \data_counter_8[7]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[7]_net_1\); - - un1_hresetn_inv_2_m75_m6_0_a2_2 : NOR3B - port map(A => m75_m6_0_a2_0, B => \grant_counter[9]_net_1\, - C => m75_m6_0_a2_1, Y => m75_m6_0_a2_2); - - \grant_counter_RNO[21]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[10]\, Y => - N_123); - - \data_counter[5]\ : DFN1C0 - port map(D => \data_counter_8[5]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[5]_net_1\); - - un1_state_4_m28_m6_0_a2_4 : NOR2B - port map(A => m28_m6_0_a2_4_6, B => m28_m6_0_a2_4_5, Y => - m28_m6_0_a2_4); - - un1_state_4_m57_m6_0_a2_7_5 : NOR3B - port map(A => m57_m6_0_a2_7_0, B => m57_m6_0_a2_7_4, C => - m57_m6_0_a2_7_1, Y => m57_m6_0_a2_7_5); - - \DMAIn.Request\ : DFN1E1C0 - port map(D => Request_5, CLK => lclk_c, CLR => rstn, E => - N_156, Q => Request); - - \DMAIn.Address_RNO[11]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(11), Y - => N_35); - - \DMAIn.Address_RNO[6]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(6), Y - => N_25); - - \DMAIn.Address[17]\ : DFN1E1C0 - port map(D => N_53, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[17]\); - - \grant_counter_RNO[31]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[0]\, Y => - N_143); - - \DMAIn.Address[22]\ : DFN1E1C0 - port map(D => N_63, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[22]\); - - \data_counter_RNO[30]\ : XA1B - port map(A => \data_counter[30]_net_1\, B => I129_un1_Y_0, - C => N_198, Y => \data_counter_8[30]\); - - \data_counter[9]\ : DFN1C0 - port map(D => \data_counter_8[9]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[9]_net_1\); - - un1_hresetn_inv_2_m67_m6_0_a2_4_4 : NOR3C - port map(A => \grant_counter[23]_net_1\, B => - \grant_counter[25]_net_1\, C => m67_m6_0_a2_4_2, Y => - m67_m6_0_a2_4_4); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_6 : OR2B - port map(A => \grant_counter[17]_net_1\, B => - \grant_counter[16]_net_1\, Y => m49_m6_0_a2_0); - - \grant_counter_RNI6QAR[1]\ : NOR3B - port map(A => \grant_counter[1]_net_1\, B => - \state_ns_i_a2_0_i_o2_11[3]\, C => - \grant_counter[15]_net_1\, Y => - \state_ns_i_a2_0_i_o2_21[3]\); - - un1_state_4_m69 : OR2A - port map(A => \data_counter[27]_net_1\, B => N_68, Y => - N_70); - - un1_hresetn_inv_2_m63_m6_0_a2_1_0 : NOR2A - port map(A => \grant_counter[10]_net_1\, B => m63_m6_0_a2_1, - Y => m63_m6_0_a2_1_0); - - \state_RNI0P0IVI_0[4]\ : OR2B - port map(A => N_200, B => rstn, Y => N_202_0); - - \data_counter[30]\ : DFN1C0 - port map(D => \data_counter_8[30]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[30]_net_1\); - - un1_state_4_m19_a0_6 : OR3B - port map(A => m19_a0_6_3, B => m19_a0_6_4, C => - un1_state_2_i_o2_0, Y => m19_a0_6_i_0); - - un1_hresetn_inv_2_m23_m6_0_a2_4_6 : NOR3C - port map(A => \grant_counter[0]_net_1\, B => - \grant_counter[7]_net_1\, C => m23_m6_0_a2_4_4, Y => - m23_m6_0_a2_4_6); - - \data_counter_RNO[7]\ : XA1B - port map(A => \data_counter[7]_net_1\, B => N_22_0_0, C => - N_198_0, Y => \data_counter_8[7]\); - - \data_counter_RNO[11]\ : XA1B - port map(A => \data_counter[11]_net_1\, B => N_26_0, C => - N_198_0, Y => \data_counter_8[11]\); - - \grant_counter_RNO[2]\ : AO1 - port map(A => N_32_0_i_0, B => N_202_0, C => N_513, Y => - \grant_counter_RNO[2]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_counter_RNO[23]\ : NOR2 - port map(A => N_61, B => N_198, Y => \data_counter_8[23]\); - - un1_state_4_m19_a1_6 : OR3C - port map(A => m19_a1_6_4, B => m19_a1_6_3, C => OKAY, Y => - m19_a1_6_i_0); - - \grant_counter_RNO_3[17]\ : NOR3B - port map(A => \grant_counter_0_i_a0_0[17]\, B => - \grant_counter_0_i_a0_4[17]\, C => - \grant_counter_0_i_a0_2[17]\, Y => - \grant_counter_0_i_a0_5[17]\); - - un1_hresetn_inv_2_m24 : NOR2A - port map(A => \grant_counter[9]_net_1\, B => N_24_0, Y => - N_25_0); - - \grant_counter_RNIRK0C[5]\ : NOR2 - port map(A => \grant_counter[5]_net_1\, B => - \grant_counter[6]_net_1\, Y => - \state_ns_i_a2_0_i_o2_2[3]\); - - \DMAIn.Address_RNO[12]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(12), Y - => N_43); - - \grant_counter_RNO[25]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[6]\, Y => - N_131); - - \state_RNIHVV86J[3]\ : OR2A - port map(A => un1_state_9_i_a4_0, B => Grant, Y => N_526); - - \DMAIn.Address_RNO[14]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(14), Y - => N_47); - - \grant_counter_RNO[11]\ : XA1A - port map(A => \grant_counter[11]_net_1\, B => N_26_0_0, C - => N_202_0, Y => N_103); - - \DMAIn.Address[20]\ : DFN1E1C0 - port map(D => N_59, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[20]\); - - \data_counter_RNIMN781[16]\ : NOR3C - port map(A => un1_state_5_i_o2_13, B => un1_state_5_i_o2_12, - C => un1_state_5_i_o2_23, Y => un1_state_5_i_o2_27); - - un1_state_4_m57_m6_0_a2_7_4 : NOR3C - port map(A => \data_counter[16]_net_1\, B => - \data_counter[15]_net_1\, C => m57_m6_0_a2_7_2, Y => - m57_m6_0_a2_7_4); - - un1_hresetn_inv_2_m23_m6_0_a2_4_4 : NOR3C - port map(A => \grant_counter[2]_net_1\, B => - \grant_counter[8]_net_1\, C => \grant_counter[1]_net_1\, - Y => m23_m6_0_a2_4_4); - - \DMAIn.Address_RNO[15]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(15), Y - => N_49); - - un1_state_4_m28_m6_0_a2_4_5 : NOR3C - port map(A => \data_counter[7]_net_1\, B => - \data_counter[6]_net_1\, C => m28_m6_0_a2_4_2, Y => - m28_m6_0_a2_4_5); - - \state_RNIPJNA8[3]\ : OAI1 - port map(A => N_246, B => un1_state_7_i_a4_0_1, C => N_516, - Y => N_146); - - \state_RNI47NO[3]\ : OR3A - port map(A => Ready, B => \state[3]_net_1\, C => N_518_1, Y - => un1_state_7_i_a4_0_1); - - \data_counter_RNO[20]\ : XA1B - port map(A => \data_counter[20]_net_1\, B => N_54, C => - N_198, Y => \data_counter_8[20]\); - - \DMAIn.Address[21]\ : DFN1E1C0 - port map(D => N_61_0, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[21]\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_13 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_8_0, B => - ADD_32x32_fast_I129_un1_Y_7, C => - ADD_32x32_fast_I129_un1_Y_12_0, Y => - ADD_32x32_fast_I129_un1_Y_13); - - \grant_counter[5]\ : DFN1 - port map(D => N_91, CLK => lclk_c, Q => - \grant_counter[5]_net_1\); - - \DMAIn.Address_RNO[9]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(9), Y - => N_31); - - \DMAIn.Address[18]\ : DFN1E1C0 - port map(D => N_55, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[18]\); - - \data_counter[25]\ : DFN1C0 - port map(D => \data_counter_8[25]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[25]_net_1\); - - \state_RNIEV8MOJ[3]\ : NOR2 - port map(A => \state[3]_net_1\, B => N_348, Y => N_509); - - \grant_counter_RNIC2BO6[1]\ : OR3C - port map(A => \state_ns_i_a2_0_i_o2_27[3]\, B => - \state_ns_i_a2_0_i_o2_26[3]\, C => - \state_ns_i_a2_0_i_o2_28[3]\, Y => N_246); - - \grant_counter[4]\ : DFN1 - port map(D => N_89, CLK => lclk_c, Q => - \grant_counter[4]_net_1\); - - \grant_counter[11]\ : DFN1 - port map(D => N_103, CLK => lclk_c, Q => - \grant_counter[11]_net_1\); - - un1_hresetn_inv_2_m63_m6_0_a2_4 : NOR2B - port map(A => m63_m6_0_a2_3, B => m55_m6_0_a2_4, Y => - m63_m6_0_a2_4); - - \DMAIn.Address[24]\ : DFN1E1C0 - port map(D => N_67, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[24]\); - - \state_RNILNM4J71[3]\ : AO1A - port map(A => N_348, B => OKAY, C => N_509, Y => N_8); - - \grant_counter[12]\ : DFN1 - port map(D => N_105, CLK => lclk_c, Q => - \grant_counter[12]_net_1\); - - \DMAIn.Burst_RNO\ : NOR3C - port map(A => N_522, B => Burst, C => N_526, Y => N_194); - - un1_hresetn_inv_2_m67_m6_0_a2 : NOR3B - port map(A => \grant_counter[9]_net_1\, B => m67_m6_0_a2_4, - C => m26_m3_e, Y => N_68_0); - - \state_RNI5BKL1J[3]\ : OR2 - port map(A => N_249, B => N_200, Y => data_fifo_ren); - - \grant_counter_RNIQF6E[15]\ : OR2B - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[13]_net_1\, Y => - \grant_counter_0_i_a0_2[17]\); - - \grant_counter_RNI7M3D[25]\ : NOR2A - port map(A => \grant_counter[0]_net_1\, B => - \grant_counter[25]_net_1\, Y => - \state_ns_i_a2_0_i_o2_9[3]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_9 : NOR3B - port map(A => ADD_32x32_fast_I129_un1_Y_0, B => - ADD_32x32_fast_I129_un1_Y_5, C => m75_m6_0_a2_1, Y => - ADD_32x32_fast_I129_un1_Y_9); - - \DMAIn.Address[19]\ : DFN1E1C0 - port map(D => N_57, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[19]\); - - \data_counter_RNO[1]\ : AOI1 - port map(A => \un1_state_4_i[30]\, B => N_343, C => N_509, - Y => N_188); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \data_counter[14]_net_1\, B => - \data_counter[15]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_4_0); - - \data_counter[4]\ : DFN1C0 - port map(D => \data_counter_8[4]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[4]_net_1\); - - un1_hresetn_inv_2_m49_m6_0_a2 : NOR2A - port map(A => m49_m6_0_a2_5, B => m26_m3_e, Y => N_50); - - \state_RNIJH0E9_0[3]\ : AO1C - port map(A => N_235, B => \state[3]_net_1\, C => N_242, Y - => N_154_0); - - \grant_counter_RNO[15]\ : XA1A - port map(A => \grant_counter[15]_net_1\, B => N_44, C => - N_202, Y => N_111); - - un1_state_4_m71_0 : OR2B - port map(A => \data_counter[28]_net_1\, B => - \data_counter[27]_net_1\, Y => m71_0); - - \grant_counter[7]\ : DFN1 - port map(D => N_95, CLK => lclk_c, Q => - \grant_counter[7]_net_1\); - - \DMAIn.Address_RNO[31]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(31), Y - => N_81); - - \data_counter_RNICE6S6[24]\ : OR3C - port map(A => un1_state_5_i_o2_29, B => un1_state_5_i_o2_28, - C => OKAY, Y => N_235); - - \state[2]\ : DFN1C0 - port map(D => N_151, CLK => lclk_c, CLR => rstn, Q => - \state[2]_net_1\); - - un1_hresetn_inv_2_m55_m6_0_a2_4_0 : NOR2B - port map(A => \grant_counter[20]_net_1\, B => - \grant_counter[19]_net_1\, Y => m55_m6_0_a2_4_0); - - un1_hresetn_inv_2_m26_m6_e_1 : NOR2B - port map(A => m26_m6_e_0_0, B => m23_m6_0_a2_4, Y => - m26_m6_e_1); - - send_ko : DFN1E1C0 - port map(D => \state[1]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_146, Q => \data_send_ko\); - - \data_counter_RNO[12]\ : XA1C - port map(A => \data_counter[12]_net_1\, B => N_27_0, C => - N_198_0, Y => \data_counter_8[12]\); - - un1_hresetn_inv_2_m31 : XNOR2 - port map(A => N_17_0, B => \grant_counter[2]_net_1\, Y => - N_32_0_i_0); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_12 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_9, B => - ADD_32x32_fast_I129_un1_Y_8, C => - ADD_32x32_fast_I129_un1_Y_10, Y => - ADD_32x32_fast_I129_un1_Y_12); - - \state_RNIP9B62[3]\ : NOR2A - port map(A => rstn, B => N_241, Y => - un1_hresetn_inv_i_0_a2_0); - - \DMAIn.Store\ : DFN1E1C0 - port map(D => \state[5]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_156, Q => Store); - - \grant_counter_RNO[29]\ : XA1A - port map(A => \grant_counter[29]_net_1\, B => N_72_0, C => - N_202, Y => N_139); - - \DMAIn.Address[3]\ : DFN1E1C0 - port map(D => N_19, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[3]\); - - \state_RNIVDV42_1[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => OKAY, Y => N_249); - - \state_RNIVCOU6[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => N_246, Y => - un1_state_9_i_a4_0); - - \state[1]\ : DFN1C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[1]_net_1\); - - \DMAIn.Address_RNISD461[31]\ : MX2C - port map(A => \Address[31]\, B => data_address(31), S => - time_select_0, Y => N_1048); - - un1_hresetn_inv_2_m30 : AX1C - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => \grant_counter[1]_net_1\, Y => - N_31_0_i_0); - - \DMAIn.Burst\ : DFN1P0 - port map(D => N_194, CLK => lclk_c, PRE => rstn, Q => Burst); - - \DMAIn.Address_RNIJJMR[8]\ : MX2C - port map(A => \Address[8]\, B => data_address(8), S => - time_select, Y => N_1025); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_12 : NOR3B - port map(A => ADD_32x32_fast_I129_un1_Y_4_0, B => - ADD_32x32_fast_I129_un1_Y_10_0, C => m57_m6_0_a2_7_1, Y - => ADD_32x32_fast_I129_un1_Y_12_0); - - un1_hresetn_inv_2_m33 : XOR2 - port map(A => N_19_0, B => \grant_counter[4]_net_1\, Y => - \un1_hresetn_inv_2_i_i[27]\); - - un1_hresetn_inv_2_m18 : NOR3C - port map(A => rstn, B => m17_m2_e_3, C => - \grant_counter[3]_net_1\, Y => N_19_0); - - un1_hresetn_inv_2_m58 : AX1E - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - \grant_counter[22]_net_1\, Y => \un1_hresetn_inv_2_i[9]\); - - \data_counter_RNO[9]\ : XA1B - port map(A => \data_counter[9]_net_1\, B => N_24_0_0, C => - N_198_0, Y => \data_counter_8[9]\); - - \grant_counter_RNO_9[17]\ : NOR2B - port map(A => \grant_counter[10]_net_1\, B => - \grant_counter[14]_net_1\, Y => - \grant_counter_0_i_a0_2_0[17]\); - - \grant_counter_RNIV37E[16]\ : NOR2 - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[17]_net_1\, Y => - \state_ns_i_a2_0_i_o2_11[3]\); - - \grant_counter_RNI5K7E[28]\ : NOR2 - port map(A => \grant_counter[28]_net_1\, B => - \grant_counter[29]_net_1\, Y => - \state_ns_i_a2_0_i_o2_5[3]\); - - \data_counter_RNO[26]\ : XA1B - port map(A => \data_counter[26]_net_1\, B => N_66_0, C => - N_198, Y => \data_counter_8[26]\); - - \state_RNI6LQC[2]\ : OR2 - port map(A => \state[4]_net_1\, B => \state[2]_net_1\, Y - => N_518_1); - - \grant_counter_RNIIC7Q[2]\ : NOR3C - port map(A => \grant_counter[3]_net_1\, B => - \grant_counter[2]_net_1\, C => - \state_ns_i_a2_0_i_o2_7[3]\, Y => - \state_ns_i_a2_0_i_o2_19[3]\); - - un1_hresetn_inv_2_m22 : OR2B - port map(A => N_22_0, B => \grant_counter[7]_net_1\, Y => - N_23_0); - - \DMAIn.Address_RNI5C221[21]\ : MX2C - port map(A => \Address[21]\, B => data_address(21), S => - time_select_0, Y => N_1038); - - \grant_counter_RNIUR6E[23]\ : NOR2 - port map(A => \grant_counter[18]_net_1\, B => - \grant_counter[23]_net_1\, Y => - \state_ns_i_a2_0_i_o2_12[3]\); - - \DMAIn.Address_RNI9JMR[6]\ : MX2C - port map(A => \Address[6]\, B => data_address(6), S => - time_select, Y => N_1023); - - un1_hresetn_inv_2_m63_m6_0_a2_6 : NOR3C - port map(A => m63_m6_0_a2_4, B => m23_m6_0_a2_4, C => - \m26_m1_e\, Y => m63_m6_0_a2_6); - - \state_RNO[3]\ : AO1A - port map(A => N_241, B => N_235, C => N_200, Y => - \state_RNO[3]_net_1\); - - \state_RNO[0]\ : AO1C - port map(A => N_235, B => \state[3]_net_1\, C => N_523, Y - => \state_RNO[0]_net_1\); - - \grant_counter_RNIKN5E_0[12]\ : NOR2 - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[10]_net_1\, Y => - \state_ns_i_a2_0_i_o2_15[3]\); - - \grant_counter[14]\ : DFN1 - port map(D => N_109, CLK => lclk_c, Q => - \grant_counter[14]_net_1\); - - \DMAIn.Address[4]\ : DFN1E1C0 - port map(D => N_21, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[4]\); - - \data_counter_RNIB2VI[18]\ : NOR3A - port map(A => un1_state_5_i_o2_7, B => - \data_counter[21]_net_1\, C => \data_counter[18]_net_1\, - Y => un1_state_5_i_o2_19); - - \grant_counter_RNO_1[20]\ : NOR3B - port map(A => grant_counter_0_i_20_b0_0_o2_1, B => - grant_counter_0_i_20_b0_0_o2_2, C => - \grant_counter_0_i_6_tz_1[17]\, Y => - grant_counter_0_i_20_b0_0_o2_4); - - \grant_counter[2]\ : DFN1 - port map(D => \grant_counter_RNO[2]_net_1\, CLK => lclk_c, - Q => \grant_counter[2]_net_1\); - - \data_counter[26]\ : DFN1C0 - port map(D => \data_counter_8[26]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[26]_net_1\); - - \data_counter[23]\ : DFN1C0 - port map(D => \data_counter_8[23]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[23]_net_1\); - - un1_state_4_m19_0_m8_i : OR3C - port map(A => m19_0_N_15_i_0_li, B => m19_0_m8_i_1, C => - \un1_state_2_i_a2_m8_i_a4\, Y => m19_0_m8_i); - - un1_state_4_m16 : NOR3C - port map(A => N_8, B => \data_counter[0]_net_1\, C => - \data_counter[1]_net_1\, Y => N_17_0_0); - - un1_hresetn_inv_2_m55_m6_0_a2 : NOR3C - port map(A => rstn, B => m26_m6_e_3, C => m55_m6_0_a2_4, Y - => N_56); - - \DMAIn.Address[25]\ : DFN1E1C0 - port map(D => N_69, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[25]\); - - \grant_counter_RNO_4[17]\ : AOI1 - port map(A => \grant_counter_0_i_6_tz_3[17]\, B => - \grant_counter_0_i_6_tz_2[17]\, C => - \grant_counter[17]_net_1\, Y => \grant_counter_0_i_5[17]\); - - \grant_counter_RNI95AD1[5]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_3[3]\, B => - \state_ns_i_a2_0_i_o2_2[3]\, C => - \state_ns_i_a2_0_i_o2_16[3]\, Y => - \state_ns_i_a2_0_i_o2_24[3]\); - - un1_state_4_m45 : NOR3C - port map(A => N_20_0, B => m43_0, C => - \data_counter[15]_net_1\, Y => N_46); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \data_counter[26]_net_1\, B => - \data_counter[25]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_3, Y => - ADD_32x32_fast_I129_un1_Y_8_0); - - \state_RNI7ALP[4]\ : OR3 - port map(A => \state[0]_net_1\, B => \state[4]_net_1\, C - => un1_state_2_i_o2_0, Y => \state_RNI7ALP[4]_net_1\); - - \grant_counter_RNO[19]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[12]\, Y => - N_119); - - \DMAIn.Address_RNO[2]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(2), Y - => N_17); - - \data_counter_RNO[17]\ : XA1B - port map(A => \data_counter[17]_net_1\, B => N_48, C => - N_198_0, Y => \data_counter_8[17]\); - - un1_state_4_m24 : NOR2B - port map(A => N_24_0_0, B => \data_counter[9]_net_1\, Y => - N_25_0_0); - - un1_hresetn_inv_2_m17_m2_e_0 : NOR2B - port map(A => \grant_counter[2]_net_1\, B => - \grant_counter[0]_net_1\, Y => m17_m2_e_0); - - un1_hresetn_inv_2_m67_m6_0_a2_4_3 : NOR3B - port map(A => \grant_counter[24]_net_1\, B => - \grant_counter[26]_net_1\, C => m63_m6_0_a2_1, Y => - m67_m6_0_a2_4_3); - - un1_hresetn_inv_2_m45_m6_0_a2_2 : NOR3C - port map(A => \grant_counter[13]_net_1\, B => - \grant_counter[9]_net_1\, C => \grant_counter[14]_net_1\, - Y => m45_m6_0_a2_2); - - \data_counter_RNO[25]\ : XA1B - port map(A => \data_counter[25]_net_1\, B => N_64, C => - N_198, Y => \data_counter_8[25]\); - - \data_counter[21]\ : DFN1C0 - port map(D => \data_counter_8[21]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[21]_net_1\); - - un1_hresetn_inv_2_m41 : AX1E - port map(A => rstn, B => m26_m6_e_3, C => - \grant_counter[12]_net_1\, Y => \un1_hresetn_inv_2_i[19]\); - - \DMAIn.Address_RNO[4]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(4), Y - => N_21); - - \grant_counter_RNO[7]\ : XA1 - port map(A => \grant_counter[7]_net_1\, B => N_22_0, C => - N_202_0, Y => N_95); - - \DMAIn.Lock\ : DFN1E1C0 - port map(D => data_send, CLK => lclk_c, CLR => rstn, E => - \state[5]_net_1\, Q => Lock); - - \data_counter_RNO_3[0]\ : AO1 - port map(A => \state[3]_net_1\, B => N_235, C => - \state[0]_net_1\, Y => \data_counter_8_i_0_tz[0]\); - - un1_hresetn_inv_2_m63_m6_0_a2_0 : NOR2B - port map(A => \grant_counter[24]_net_1\, B => - \grant_counter[23]_net_1\, Y => m63_m6_0_a2_0); - - \state_RNI5OCK8J[3]\ : OR2B - port map(A => N_526, B => N_242, Y => N_156); - - \grant_counter[3]\ : DFN1 - port map(D => \grant_counter_RNO[3]_net_1\, CLK => lclk_c, - Q => \grant_counter[3]_net_1\); - - \grant_counter_RNO_0[17]\ : NOR3B - port map(A => \grant_counter[9]_net_1\, B => - \grant_counter_0_i_a0_5[17]\, C => m26_m3_e, Y => - \grant_counter_RNO_0[17]_net_1\); - - \grant_counter_RNI40MT1[8]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_13[3]\, B => - \state_ns_i_a2_0_i_o2_12[3]\, C => - \state_ns_i_a2_0_i_o2_23[3]\, Y => - \state_ns_i_a2_0_i_o2_27[3]\); - - \grant_counter[13]\ : DFN1 - port map(D => N_107, CLK => lclk_c, Q => - \grant_counter[13]_net_1\); - - \grant_counter[27]\ : DFN1 - port map(D => N_135, CLK => lclk_c, Q => - \grant_counter[27]_net_1\); - - un1_hresetn_inv_2_m43 : OR3C - port map(A => \grant_counter[13]_net_1\, B => N_28_0, C => - \grant_counter[14]_net_1\, Y => N_44); - - \data_counter_RNI3BF9[12]\ : NOR2 - port map(A => \data_counter[12]_net_1\, B => - \data_counter[17]_net_1\, Y => un1_state_5_i_o2_5); - - un1_state_4_m57_m6_0_a2 : OR3C - port map(A => m28_m6_0_a2_4, B => m57_m6_0_a2_7_5, C => - N_20_0, Y => N_58); - - \data_counter_RNI5JF9[22]\ : NOR2 - port map(A => \data_counter[22]_net_1\, B => - \data_counter[23]_net_1\, Y => un1_state_5_i_o2_7); - - \data_counter_RNIEJF9[26]\ : NOR2 - port map(A => \data_counter[26]_net_1\, B => - \data_counter[28]_net_1\, Y => un1_state_5_i_o2_9); - - \data_counter_RNI7JF9[20]\ : NOR2 - port map(A => \data_counter[20]_net_1\, B => - \data_counter[27]_net_1\, Y => un1_state_5_i_o2_13); - - \DMAIn.Address_RNI8D721[19]\ : MX2C - port map(A => \Address[19]\, B => data_address(19), S => - time_select_0, Y => N_1036); - - un1_hresetn_inv_2_m75_m6_0_a2 : NOR3B - port map(A => m75_m6_0_a2_3, B => m67_m6_0_a2_4, C => N_241, - Y => m75_m6_0_a2); - - \data_counter_RNIQ9BL[6]\ : NOR3A - port map(A => un1_state_5_i_o2_3, B => - \data_counter[6]_net_1\, C => \data_counter[5]_net_1\, Y - => un1_state_5_i_o2_17); - - \DMAIn.Address_RNIL46L[12]\ : MX2C - port map(A => \Address[12]\, B => data_address(12), S => - time_select, Y => N_1029); - - \state_RNITA375[4]\ : OR2A - port map(A => m19_0_N_15_i_0_li, B => \state[4]_net_1\, Y - => \state_RNITA375[4]_net_1\); - - \state_RNIRKRFOJ[4]\ : MX2 - port map(A => nhmaster_1_i(0), B => - \state_RNI7ALP[4]_net_1\, S => \state_RNI6R78T9[4]_net_1\, - Y => N_348); - - \state_RNIRKTDJQ1[5]\ : MX2C - port map(A => \state[5]_net_1\, B => \un1_state_4_i[31]\, S - => N_243_i, Y => N_508); - - \grant_counter_RNI1A043[2]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_19[3]\, B => - \state_ns_i_a2_0_i_o2_18[3]\, C => - \state_ns_i_a2_0_i_o2_24[3]\, Y => - \state_ns_i_a2_0_i_o2_28[3]\); - - \grant_counter[28]\ : DFN1 - port map(D => N_137, CLK => lclk_c, Q => - \grant_counter[28]_net_1\); - - un1_hresetn_inv_2_m46 : AX1E - port map(A => un1_hresetn_inv_i_0_a2_0, B => m45_m6_0_a2_6, - C => \grant_counter[16]_net_1\, Y => - \un1_hresetn_inv_2_i[15]\); - - \data_counter_RNIUP2A[10]\ : NOR2 - port map(A => \data_counter[9]_net_1\, B => - \data_counter[10]_net_1\, Y => un1_state_5_i_o2_4); - - un1_hresetn_inv_2_m63_m6_0_a2_3 : NOR3B - port map(A => m63_m6_0_a2_0, B => m63_m6_0_a2_1_0, C => - m26_m6_e_0, Y => m63_m6_0_a2_3); - - \DMAIn.Address[26]\ : DFN1E1C0 - port map(D => N_71, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[26]\); - - \grant_counter_RNIKN5E[12]\ : NOR2B - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[10]_net_1\, Y => - \grant_counter_0_i_6_tz_1_0[17]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_0 : NOR2B - port map(A => \grant_counter[20]_net_1\, B => - \grant_counter[26]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_0); - - \data_counter_RNO[0]\ : OA1B - port map(A => N_508, B => \data_counter_8_i_a4_2_0[0]\, C - => \data_counter_8_i_0_0[0]\, Y => N_186); - - un1_hresetn_inv_2_m61 : OR2B - port map(A => N_60, B => \grant_counter[23]_net_1\, Y => - N_62); - - \grant_counter_RNO_6[17]\ : NOR3C - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[11]_net_1\, C => - \grant_counter_0_i_a0_2_0[17]\, Y => - \grant_counter_0_i_a0_4[17]\); - - un1_hresetn_inv_2_m26_m6_e_0 : OR2B - port map(A => \grant_counter[11]_net_1\, B => - \grant_counter[9]_net_1\, Y => m26_m6_e_0); - - \state_RNIVDV42[3]\ : OR2B - port map(A => \state[3]_net_1\, B => Fault, Y => N_241); - - \grant_counter_RNO[0]\ : OR3C - port map(A => N_30_0, B => N_202_0, C => N_354, Y => - \grant_counter_RNO[0]_net_1\); - - \data_counter_RNIN6VI[24]\ : NOR3A - port map(A => un1_state_5_i_o2_9, B => - \data_counter[25]_net_1\, C => \data_counter[24]_net_1\, - Y => un1_state_5_i_o2_20); - - \data_counter[6]\ : DFN1C0 - port map(D => \data_counter_8[6]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[6]_net_1\); - - \data_counter[15]\ : DFN1C0 - port map(D => \data_counter_8[15]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[15]_net_1\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_3 : NOR2B - port map(A => \data_counter[28]_net_1\, B => - \data_counter[29]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_3); - - un1_hresetn_inv_2_m29 : XNOR2 - port map(A => un1_hresetn_inv_i_0, B => - \grant_counter[0]_net_1\, Y => N_30_0); - - un1_state_4_m47 : NOR2B - port map(A => N_46, B => \data_counter[16]_net_1\, Y => - N_48); - - un1_hresetn_inv_2_m67_m6_0_a2_4 : NOR3C - port map(A => m67_m6_0_a2_4_4, B => m67_m6_0_a2_4_3, C => - m55_m6_0_a2_4, Y => m67_m6_0_a2_4); - - un1_hresetn_inv_2_m45_m6_0_a2_4 : NOR3B - port map(A => \grant_counter_0_i_6_tz_1_0[17]\, B => - m45_m6_0_a2_2, C => m49_m6_0_a2_2, Y => m45_m6_0_a2_4); - - \DMAIn.Address_RNIE9CS[3]\ : MX2C - port map(A => \Address[3]\, B => data_address(3), S => - time_select_0, Y => N_1020); - - \data_counter_RNO[19]\ : XA1C - port map(A => \data_counter[19]_net_1\, B => N_52, C => - N_198, Y => \data_counter_8[19]\); - - \grant_counter_RNO[8]\ : XA1A - port map(A => \grant_counter[8]_net_1\, B => N_23_0, C => - N_202_0, Y => N_97); - - \data_counter[20]\ : DFN1C0 - port map(D => \data_counter_8[20]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[20]_net_1\); - - \data_counter[22]\ : DFN1C0 - port map(D => \data_counter_8[22]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[22]_net_1\); - - un1_hresetn_inv_2_m45_m6_0_a2_6 : NOR3C - port map(A => m23_m6_0_a2_4, B => m45_m6_0_a2_4, C => - \m26_m1_e\, Y => m45_m6_0_a2_6); - - \DMAIn.Address[27]\ : DFN1E1C0 - port map(D => N_73, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[27]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(1 to 1); - status_full : out std_logic_vector(1 to 1); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - update_and_sel_5 : in std_logic_vector(3 downto 2); - sel_data_0 : in std_logic_vector(1 to 1); - addr_data_f1 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(1 to 1); - addr_data_vector_69 : in std_logic; - addr_data_vector_95 : in std_logic; - addr_data_vector_94 : in std_logic; - addr_data_vector_93 : in std_logic; - addr_data_vector_91 : in std_logic; - addr_data_vector_89 : in std_logic; - addr_data_vector_88 : in std_logic; - addr_data_vector_85 : in std_logic; - addr_data_vector_68 : in std_logic; - addr_data_vector_67 : in std_logic; - addr_data_vector_66 : in std_logic; - addr_data_vector_65 : in std_logic; - addr_data_vector_74 : in std_logic; - addr_data_vector_72 : in std_logic; - addr_data_vector_71 : in std_logic; - addr_data_vector_70 : in std_logic; - addr_data_vector_82 : in std_logic; - addr_data_vector_78 : in std_logic; - addr_data_vector_87 : in std_logic; - addr_data_vector_84 : in std_logic; - addr_data_vector_64 : in std_logic; - addr_data_vector_80 : in std_logic; - addr_data_vector_76 : in std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_13 : out std_logic; - addr_data_vector_11 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_17 : out std_logic; - addr_data_vector_19 : out std_logic; - addr_data_vector_22 : out std_logic; - N_1358 : out std_logic; - N_984 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_980 : out std_logic; - N_978 : out std_logic; - N_977 : out std_logic; - N_974 : out std_logic; - N_1371 : out std_logic; - N_1370 : out std_logic; - N_1369 : out std_logic; - N_1368 : out std_logic; - N_1363 : out std_logic; - N_1361 : out std_logic; - N_1360 : out std_logic; - N_1359 : out std_logic; - N_1357 : out std_logic; - N_1353 : out std_logic; - N_976 : out std_logic; - N_973 : out std_logic; - N_1367 : out std_logic; - N_1355 : out std_logic; - N_1351 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, m40_m6_0_a2_7, m40_m6_0_a2_2, - m40_m6_0_a2_1, m40_m6_0_a2_6, \addr_data_vector[53]\, - \addr_data_vector[52]\, m40_m6_0_a2_4, m40_m6_0_a2_0, - \addr_data_vector[50]\, \addr_data_vector[48]\, - \addr_data_vector[55]\, \un1_state_12_3_0[4]\, - \update_r[0]_net_1\, \update_r[1]_net_1\, un1_state_5_i_0, - \state[4]_net_1\, \state[3]_net_1\, \state_ns_i_0[3]\, - N_131, \un1_address[6]\, address_0_sqmuxa_i_0, - \addr_data_vector[38]\, N_5_0, \un1_state_12[4]\, - \un1_state_12_2[4]\, N_116, N_129, \state[1]_net_1\, - \state_ns[0]\, N_125, N_124, N_110, \state[2]_net_1\, - state7, un3_update_r, N_15_0_i_0, N_13_0, - \addr_data_vector[39]\, \addr_data_vector[40]\, N_16_0, - N_17_0_i_0, N_19_0, \addr_data_vector[41]\, - \addr_data_vector[42]\, N_20_0_i_0, N_22_0_i_0, - \addr_data_vector[43]\, \addr_data_vector[44]\, N_23_0, - N_25_0, \addr_data_vector[46]\, N_26_0_i_0, - \addr_data_vector[47]\, N_28_0_i_0, N_29_0, N_30_0_i_0, - \addr_data_vector[49]\, N_32_0, \un1_address[19]\, - \addr_data_vector[51]\, N_37_0, N_36_0, \un1_address[23]\, - \addr_data_vector[54]\, N_40_i_0, \addr_data_vector[34]\, - N_42, \addr_data_vector[56]\, N_43, - \addr_data_vector[57]\, N_45, \addr_data_vector[59]\, - N_47, \addr_data_vector[61]\, N_49_i_0, - \addr_data_vector[62]\, \addr_data_vector[63]\, N_50_i_0, - \addr_data_vector[35]\, N_51_i_0, N_69, - \addr_data_vector[36]\, N_52_i_0, \addr_data_vector[37]\, - N_1_i_0, N_54_0_i_0, N_55_0_i_0, \addr_data_vector[45]\, - N_56_0_i_0, \un1_address[18]\, \un1_address[21]\, - \un1_address[22]\, \un1_address[24]\, \un1_address[25]\, - \un1_address[26]\, \addr_data_vector[58]\, - \un1_address[27]\, \un1_address[28]\, - \addr_data_vector[60]\, \un1_address[29]\, - \un1_address[30]\, \nb_send_5[0]\, \nb_send_5[1]\, - \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[14]\, \address_7[15]\, - \address_7[16]\, \address_7[17]\, \address_7[18]\, - \state[0]_net_1\, \address_7[19]\, \address_7[21]\, - \address_7[22]\, \address_7[23]\, \address_7[24]\, - \address_7[25]\, \address_7[26]\, \address_7[27]\, - \address_7[28]\, \address_7[29]\, \address_7[30]\, - \address_7[31]\, \addr_data_vector[32]\, \address_7[20]\, - \un1_address[20]\, un1_state_9, \nb_send_5[4]\, - \un2_nb_send_next[4]\, N_127, N_113, \state_ns[2]\, - un1_state_11, \addr_data_vector[33]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_28 <= \addr_data_vector[60]\; - addr_data_vector_26 <= \addr_data_vector[58]\; - addr_data_vector_13 <= \addr_data_vector[45]\; - addr_data_vector_11 <= \addr_data_vector[43]\; - addr_data_vector_9 <= \addr_data_vector[41]\; - addr_data_vector_15 <= \addr_data_vector[47]\; - addr_data_vector_17 <= \addr_data_vector[49]\; - addr_data_vector_19 <= \addr_data_vector[51]\; - addr_data_vector_22 <= \addr_data_vector[54]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[48]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[42]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[62]\); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f1(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : XOR2 - port map(A => N_43, B => \addr_data_vector[58]\, Y => - \un1_address[26]\); - - un1_address_m31 : OR3B - port map(A => \addr_data_vector[49]\, B => - \addr_data_vector[50]\, C => N_29_0, Y => N_32_0); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[58]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[52]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3A - port map(A => \state[2]_net_1\, B => N_129, C => - status_full_ack(1), Y => N_127); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1 - port map(A => N_69, B => \addr_data_vector[36]\, C => - \addr_data_vector[37]\, Y => N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[44]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f1(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - \address_RNI46N9[12]\ : MX2C - port map(A => \addr_data_vector[44]\, B => - addr_data_vector_76, S => sel_data_0(1), Y => N_1351); - - un1_address_m19 : XNOR2 - port map(A => N_19_0, B => \addr_data_vector[43]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[54]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f1(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[34]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f1(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f1(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_110, Q => status_full_err(1)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : OR3B - port map(A => \addr_data_vector[41]\, B => - \addr_data_vector[42]\, C => N_16_0, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f1(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[37]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[47]\); - - \address_RNICRBB[7]\ : MX2C - port map(A => \addr_data_vector[39]\, B => - addr_data_vector_71, S => sel_data_0(1), Y => N_1360); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[45]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => lclk_c, PRE => rstn, Q - => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[51]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[57]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[55]\); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[39]\, C => - \addr_data_vector[40]\, Y => N_15_0_i_0); - - un1_address_m29 : XNOR2 - port map(A => N_29_0, B => \addr_data_vector[49]\, Y => - N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[61]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[50]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f1(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f1(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - \address_RNIRFPD[31]\ : MX2C - port map(A => \addr_data_vector[63]\, B => - addr_data_vector_95, S => sel_data(1), Y => N_984); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f1(0), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => \addr_data_vector[32]\); - - un1_address_m28 : OR3B - port map(A => \addr_data_vector[47]\, B => - \addr_data_vector[48]\, C => N_25_0, Y => N_29_0); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : OR3B - port map(A => m40_m6_0_a2_7, B => \addr_data_vector[56]\, C - => N_25_0, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f1(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[36]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[60]\); - - \state_RNIHPL6[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \address_RNI2MM9[20]\ : MX2C - port map(A => \addr_data_vector[52]\, B => - addr_data_vector_84, S => sel_data_0(1), Y => N_973); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3A - port map(A => N_131, B => \state[3]_net_1\, C => N_129, Y - => N_125); - - \state_RNIUNK9[1]\ : NOR2A - port map(A => status_full_ack(1), B => N_131, Y => N_118); - - \address_RNIERBB[8]\ : MX2C - port map(A => \addr_data_vector[40]\, B => - addr_data_vector_72, S => sel_data_0(1), Y => N_1361); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR3 - port map(A => address_0_sqmuxa_i_0, B => - \addr_data_vector[38]\, C => N_5_0, Y => \un1_address[6]\); - - \address_RNIUQBB[0]\ : MX2C - port map(A => \addr_data_vector[32]\, B => - addr_data_vector_64, S => sel_data_0(1), Y => N_1367); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f1(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - un1_address_m24 : OR3B - port map(A => \addr_data_vector[45]\, B => - \addr_data_vector[46]\, C => N_23_0, Y => N_25_0); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f1(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[46]\); - - \address_RNI8EN9[23]\ : MX2C - port map(A => \addr_data_vector[55]\, B => - addr_data_vector_87, S => sel_data_0(1), Y => N_976); - - \state_RNO[1]\ : OA1B - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - un1_address_m40_m6_0_a2_4 : NOR2B - port map(A => \addr_data_vector[54]\, B => m40_m6_0_a2_0, Y - => m40_m6_0_a2_4); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => lclk_c, CLR => rstn, - E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f1(14), S => - \state_0[0]_net_1\, Y => \address_7[14]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[56]\); - - un1_address_m27 : AX1 - port map(A => N_25_0, B => \addr_data_vector[47]\, C => - \addr_data_vector[48]\, Y => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[57]\, Y => - \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[41]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \address_RNI8MN9[14]\ : MX2C - port map(A => \addr_data_vector[46]\, B => - addr_data_vector_78, S => sel_data_0(1), Y => N_1353); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3B - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[40]\); - - un1_address_m40_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[50]\, B => - \addr_data_vector[51]\, Y => m40_m6_0_a2_2); - - un1_address_m50 : XNOR2 - port map(A => N_69, B => \addr_data_vector[36]\, Y => - N_51_i_0); - - un1_address_m39 : XNOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[34]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : OR2 - port map(A => update_and_sel_5(3), B => update_and_sel_5(2), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f1(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f1(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f1(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - \address_RNIV7QD[24]\ : MX2C - port map(A => \addr_data_vector[56]\, B => - addr_data_vector_88, S => sel_data(1), Y => N_977); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1C - port map(A => \addr_data_vector[54]\, B => N_37_0, C => - \addr_data_vector[55]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa_i_0, C => - \addr_data_vector[38]\, Y => N_13_0); - - un1_address_m59 : AX1 - port map(A => N_25_0, B => m40_m6_0_a2_7, C => - \addr_data_vector[56]\, Y => \un1_address[24]\); - - \update_r[0]\ : DFN1C0 - port map(D => update_and_sel_5(2), CLK => lclk_c, CLR => - rstn, Q => \update_r[0]_net_1\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[53]\, B => - \addr_data_vector[52]\, C => m40_m6_0_a2_4, Y => - m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f1(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f1(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[39]\, B => - \addr_data_vector[40]\, C => N_13_0, Y => N_16_0); - - un1_address_m58 : XOR2 - port map(A => N_37_0, B => \addr_data_vector[54]\, Y => - \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - \update_r_RNIL3G9_0[0]\ : NOR2A - port map(A => \update_r[0]_net_1\, B => \update_r[1]_net_1\, - Y => \un1_state_12_3_0[4]\); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f1(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[35]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : AX1C - port map(A => \addr_data_vector[60]\, B => N_45, C => - \addr_data_vector[61]\, Y => \un1_address[29]\); - - un1_address_m34 : AX1 - port map(A => N_32_0, B => \addr_data_vector[51]\, C => - \addr_data_vector[52]\, Y => \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f1(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \address_RNI7BCB[3]\ : MX2C - port map(A => \addr_data_vector[35]\, B => - addr_data_vector_67, S => sel_data_1(1), Y => N_1370); - - \address_RNI36N9[10]\ : MX2C - port map(A => \addr_data_vector[42]\, B => - addr_data_vector_74, S => sel_data_1(1), Y => N_1363); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(1), B => N_131, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : XNOR2 - port map(A => N_23_0, B => \addr_data_vector[45]\, Y => - N_55_0_i_0); - - un1_address_m22 : OR3B - port map(A => \addr_data_vector[43]\, B => - \addr_data_vector[44]\, C => N_19_0, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[39]\); - - \address_RNITCEF[5]\ : MX2C - port map(A => \addr_data_vector[37]\, B => - addr_data_vector_69, S => sel_data(1), Y => N_1358); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \state_RNIL7JMK[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - \address_RNI9GRD[29]\ : MX2C - port map(A => \addr_data_vector[61]\, B => - addr_data_vector_93, S => sel_data(1), Y => N_982); - - \address_RNIPFPD[21]\ : MX2C - port map(A => \addr_data_vector[53]\, B => - addr_data_vector_85, S => sel_data(1), Y => N_974); - - un1_address_m25 : XNOR2 - port map(A => N_25_0, B => \addr_data_vector[47]\, Y => - N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => lclk_c, CLR => rstn, Q => - \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_5(3), CLK => lclk_c, CLR => - rstn, Q => \update_r[1]_net_1\); - - un1_address_m40_m6_0_a2_7 : NOR3C - port map(A => m40_m6_0_a2_2, B => m40_m6_0_a2_1, C => - m40_m6_0_a2_6, Y => m40_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - un1_address_m57 : XNOR2 - port map(A => N_36_0, B => \addr_data_vector[53]\, Y => - \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - \address_RNIARBB[6]\ : MX2C - port map(A => \addr_data_vector[38]\, B => - addr_data_vector_70, S => sel_data_0(1), Y => N_1359); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f1(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[34]\, C => \addr_data_vector[35]\, Y - => N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[41]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f1(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f1(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - \address_RNI50RD[27]\ : MX2C - port map(A => \addr_data_vector[59]\, B => - addr_data_vector_91, S => sel_data(1), Y => N_980); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[62]\, B => N_47, C => - \addr_data_vector[63]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[38]\); - - \state_RNIAB30L_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - status_full_err_RNO : AO1A - port map(A => N_129, B => \state[2]_net_1\, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f1(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un1_address_m36 : NOR2A - port map(A => \addr_data_vector[53]\, B => N_36_0, Y => - N_37_0); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[43]\); - - \state_RNIAB30L[3]\ : OR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa_i_0); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[63]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : AX1 - port map(A => N_29_0, B => \addr_data_vector[49]\, C => - \addr_data_vector[50]\, Y => \un1_address[18]\); - - \address_RNI9BCB[4]\ : MX2C - port map(A => \addr_data_vector[36]\, B => - addr_data_vector_68, S => sel_data_1(1), Y => N_1371); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f1(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - un1_address_m44 : NOR3C - port map(A => \addr_data_vector[58]\, B => N_43, C => - \addr_data_vector[59]\, Y => N_45); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f1(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f1(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[53]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - un1_address_m62 : AX1C - port map(A => \addr_data_vector[58]\, B => N_43, C => - \addr_data_vector[59]\, Y => \un1_address[27]\); - - un1_address_m32 : XNOR2 - port map(A => N_32_0, B => \addr_data_vector[51]\, Y => - \un1_address[19]\); - - un1_address_m12_e : OR3B - port map(A => \addr_data_vector[36]\, B => - \addr_data_vector[37]\, C => N_69, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \address_RNIC6O9[16]\ : MX2C - port map(A => \addr_data_vector[48]\, B => - addr_data_vector_80, S => sel_data_0(1), Y => N_1355); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => lclk_c, CLR => rstn, Q => - \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[49]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[62]\, Y => - \un1_address[30]\); - - un1_address_m35 : OR3B - port map(A => \addr_data_vector[51]\, B => - \addr_data_vector[52]\, C => N_32_0, Y => N_36_0); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[39]\, Y => - N_1_i_0); - - \address_RNI5BCB[2]\ : MX2C - port map(A => \addr_data_vector[34]\, B => - addr_data_vector_66, S => sel_data_1(1), Y => N_1369); - - \update_r_RNIAB30L[0]\ : OR2B - port map(A => \un1_state_12_3_0[4]\, B => - \un1_state_12_2[4]\, Y => \un1_state_12[4]\); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[59]\); - - \state_RNO[3]\ : NOR2B - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : AX1 - port map(A => N_19_0, B => \addr_data_vector[43]\, C => - \addr_data_vector[44]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : AX1 - port map(A => N_23_0, B => \addr_data_vector[45]\, C => - \addr_data_vector[46]\, Y => N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f1(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : OR3B - port map(A => \addr_data_vector[34]\, B => - \addr_data_vector[35]\, C => \un1_state_12[4]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \address_RNI3BCB[1]\ : MX2C - port map(A => \addr_data_vector[33]\, B => - addr_data_vector_65, S => sel_data_1(1), Y => N_1368); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f1(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - \address_RNIP7PD[30]\ : MX2C - port map(A => \addr_data_vector[62]\, B => - addr_data_vector_94, S => sel_data(1), Y => N_983); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f1(1), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => \addr_data_vector[33]\); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_11, Q => status_full(1)); - - \address_RNIGMO9[18]\ : MX2C - port map(A => \addr_data_vector[50]\, B => - addr_data_vector_82, S => sel_data_0(1), Y => N_1357); - - \address_RNI1GQD[25]\ : MX2C - port map(A => \addr_data_vector[57]\, B => - addr_data_vector_89, S => sel_data(1), Y => N_978); - - un1_address_m63 : XOR2 - port map(A => N_45, B => \addr_data_vector[60]\, Y => - \un1_address[28]\); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f1(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR3C - port map(A => \addr_data_vector[60]\, B => N_45, C => - \addr_data_vector[61]\, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : AX1 - port map(A => N_16_0, B => \addr_data_vector[41]\, C => - \addr_data_vector[42]\, Y => N_54_0_i_0); - - un1_address_m40_m6_0_a2_0 : NOR2B - port map(A => \addr_data_vector[55]\, B => - \addr_data_vector[47]\, Y => m40_m6_0_a2_0); - - un1_address_m40_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[48]\, B => - \addr_data_vector[49]\, Y => m40_m6_0_a2_1); - - \update_r_RNIL3G9[0]\ : OR2A - port map(A => \update_r[1]_net_1\, B => \update_r[0]_net_1\, - Y => un3_update_r); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f1(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - un1_address_m42 : NOR2A - port map(A => \addr_data_vector[57]\, B => N_42, Y => N_43); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_dma_send_1word is - - port( Request : out std_logic; - Store : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - Grant : in std_logic; - un1_time_send_ok : out std_logic; - Fault : in std_logic; - Ready : in std_logic; - time_select_0 : in std_logic; - Lock : in std_logic; - Lock_RNIU86D : out std_logic; - time_send : in std_logic - ); - -end lpp_dma_send_1word; - -architecture DEF_ARCH of lpp_dma_send_1word is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un1_state_4_i_0, \state[1]_net_1\, \state[3]_net_1\, - N_64, \state[2]_net_1\, \state[0]_net_1\, N_58, N_70, - un1_state_2, N_69, \state[4]_net_1\, N_66, Lock_0, - \state_RNO[4]_net_1\, time_send_ok, time_send_ko, - \state_ns[3]\, N_61, \state_ns[1]\, Request_4, - \state_ns[2]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \DMAIn.Lock_RNIU86D\ : MX2 - port map(A => Lock, B => Lock_0, S => time_select_0, Y => - Lock_RNIU86D); - - \state[1]\ : DFN1C0 - port map(D => \state_ns[3]\, CLK => lclk_c, CLR => rstn, Q - => \state[1]_net_1\); - - \state_RNIHJ68[4]\ : NOR2B - port map(A => time_send, B => \state[4]_net_1\, Y => - Request_4); - - GND_i_0 : GND - port map(Y => GND_0); - - \state_RNIRKN62[2]\ : AOI1B - port map(A => Ready, B => Fault, C => \state[2]_net_1\, Y - => N_70); - - \state_RNIO7CM1J[4]\ : OR3 - port map(A => N_69, B => \state[4]_net_1\, C => N_66, Y => - un1_state_2); - - un1_state_2_0_o3 : NOR2A - port map(A => Fault, B => Ready, Y => N_61); - - \state[4]\ : DFN1P0 - port map(D => \state_RNO[4]_net_1\, CLK => lclk_c, PRE => - rstn, Q => \state[4]_net_1\); - - \DMAIn.Request\ : DFN1E1C0 - port map(D => Request_4, CLK => lclk_c, CLR => rstn, E => - un1_state_2, Q => Request); - - VCC_i : VCC - port map(Y => \VCC\); - - \state_RNO[4]\ : NOR2 - port map(A => N_64, B => N_58, Y => \state_RNO[4]_net_1\); - - \state_RNI8KC5[1]\ : OR2 - port map(A => \state[1]_net_1\, B => \state[3]_net_1\, Y - => un1_state_4_i_0); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - send_ok : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_58, Q => time_send_ok); - - \state_RNO[1]\ : NOR2A - port map(A => \state[2]_net_1\, B => Fault, Y => - \state_ns[3]\); - - GND_i : GND - port map(Y => \GND\); - - \state_RNO_0[4]\ : NOR3A - port map(A => time_send, B => \state[2]_net_1\, C => - \state[0]_net_1\, Y => N_64); - - \state_RNIRKN62_0[2]\ : NOR2A - port map(A => \state[2]_net_1\, B => N_61, Y => N_69); - - \DMAIn.Store\ : DFN1E1C0 - port map(D => \state[4]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_2, Q => Store); - - \DMAIn.Lock\ : DFN1E1C0 - port map(D => time_send, CLK => lclk_c, CLR => rstn, E => - \state[4]_net_1\, Q => Lock_0); - - \state_RNO[2]\ : AO1 - port map(A => \state[2]_net_1\, B => N_61, C => N_66, Y => - \state_ns[2]\); - - send_ok_RNIGNLF : OR2 - port map(A => time_send_ok, B => time_send_ko, Y => - un1_time_send_ok); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNI394C2[1]\ : OR2 - port map(A => un1_state_4_i_0, B => N_70, Y => N_58); - - \state_RNO[3]\ : AO1 - port map(A => \state[3]_net_1\, B => Grant, C => Request_4, - Y => \state_ns[1]\); - - \state_RNIN0UCVI[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => Grant, Y => N_66); - - send_ko : DFN1E0C0 - port map(D => \state[0]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_58, Q => time_send_ko); - - \state[0]\ : DFN1C0 - port map(D => \state[1]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[0]_net_1\); - - \state[3]\ : DFN1C0 - port map(D => \state_ns[1]\, CLK => lclk_c, CLR => rstn, Q - => \state[3]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(3 to 3); - status_full : out std_logic_vector(3 to 3); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(3 to 3); - addr_data_vector_56 : out std_logic; - addr_data_vector_55 : out std_logic; - addr_data_vector_17 : in std_logic; - addr_data_vector_13 : in std_logic; - addr_data_vector_10 : in std_logic; - addr_data_vector_2 : in std_logic; - addr_data_vector_0 : in std_logic; - addr_data_vector_8 : in std_logic; - addr_data_vector_4 : in std_logic; - addr_data_vector_63 : out std_logic; - addr_data_vector_6 : in std_logic; - addr_data_vector_19 : in std_logic; - addr_data_vector_62 : out std_logic; - addr_data_vector_60 : out std_logic; - addr_data_vector_59 : out std_logic; - addr_data_vector_58 : out std_logic; - addr_data_vector_86 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_84 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_57 : out std_logic; - addr_data_vector_78 : out std_logic; - addr_data_vector_67 : out std_logic; - addr_data_vector_65 : out std_logic; - addr_data_vector_61 : out std_logic; - addr_data_vector_73 : out std_logic; - addr_data_vector_76 : out std_logic; - addr_data_vector_69 : out std_logic; - addr_data_vector_71 : out std_logic; - addr_data_vector_75 : out std_logic; - update_and_sel_1 : in std_logic_vector(7 downto 6); - N_979 : out std_logic; - N_975 : out std_logic; - N_972 : out std_logic; - N_1364 : out std_logic; - N_1362 : out std_logic; - N_1356 : out std_logic; - N_1352 : out std_logic; - N_1354 : out std_logic; - N_981 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, \state_RNIC6KH[1]_net_1\, N_38, - \nb_send[1]_net_1\, \nb_send[0]_net_1\, N_30, - \nb_send[3]_net_1\, \DWACT_FINC_E[0]\, N_7, - \nb_send[8]_net_1\, \DWACT_FINC_E[4]\, N_129_i, N_125, - \state_ns_a3_1_0[0]\, N_131, \state[3]_net_1\, - m37_m6_0_a2_6, \addr_data_vector[115]\, m37_m6_0_a2_4, - m37_m6_0_a2_5, \addr_data_vector[111]\, m37_m6_0_a2_2, - \addr_data_vector[118]\, \addr_data_vector[113]\, - \un1_state_12_3_0[4]\, \update_r[0]_net_1\, - \update_r[1]_net_1\, \un1_state_12[4]\, - \un1_state_12_2[4]\, \state_RNO[1]_net_1\, N_128, - \state_ns[0]\, N_124, N_110, \state[4]_net_1\, N_130, - \state[2]_net_1\, address_0_sqmuxa, state7, un3_update_r, - \un1_address[6]\, N_5_0, N_38_0_i, N_24_0, N_17_0_i_0, - N_16_0, \addr_data_vector[105]\, N_18_0, N_20_0_i_0, - \addr_data_vector[107]\, N_21_0, \addr_data_vector[106]\, - N_22_0_i_0, \addr_data_vector[108]\, - \addr_data_vector[109]\, N_30_0_i_0, N_27_0, - \addr_data_vector[112]\, N_31_0, N_35_0, N_34_0, - \addr_data_vector[116]\, N_36_0, N_39, N_40_i_0, N_42, - \addr_data_vector[119]\, N_44, \addr_data_vector[122]\, - N_46, \addr_data_vector[124]\, N_47, N_49_i_0, N_50_i_0, - \addr_data_vector[98]\, N_52_i_0, N_69, N_1_i_0, N_13_0, - N_54_0_i_0, N_55_0_i_0, N_56_0_i_0, - \addr_data_vector[110]\, N_57_0, \addr_data_vector[114]\, - N_58_0, \addr_data_vector[117]\, N_59_0, N_60_0, - \addr_data_vector[120]\, N_61_0, \addr_data_vector[121]\, - N_62, N_63_0, \addr_data_vector[123]\, N_64_0, N_65_0, - \addr_data_vector[125]\, N_66_0, \addr_data_vector[126]\, - \addr_data_vector[99]\, \addr_data_vector[100]\, - \addr_data_vector[101]\, \addr_data_vector[102]\, - un1_state_9, \nb_send_5[0]\, \nb_send_5[1]\, I_5_30, - \nb_send_5[2]\, I_9_30, \nb_send_5[3]\, I_13_34, - \nb_send_5[4]\, I_20_22, \nb_send_5[5]\, I_24_15, - \nb_send_5[6]\, I_31_14, \nb_send_5[7]\, I_38_11, - \nb_send_5[8]\, I_45_10, \nb_send_5[9]\, I_52_10, - \nb_send_5[10]\, I_56_11, N_127, \state[1]_net_1\, - \state_RNO_0[3]\, \state_ns[2]\, un1_state_11, - \address_7[2]\, \address_7[3]\, \address_7[4]\, N_51_i_0, - \address_7[5]\, \address_7[6]\, \address_7[7]\, - \address_7[9]\, \address_7[10]\, \address_7[11]\, - \address_7[12]\, \address_7[13]\, \address_7[14]\, - \address_7[17]\, \address_7[18]\, \address_7[20]\, - \address_7[21]\, \address_7[22]\, \state[0]_net_1\, - \address_7[23]\, \address_7[24]\, \address_7[25]\, - \address_7[26]\, \address_7[27]\, \address_7[28]\, - \address_7[29]\, \address_7[30]\, \address_7[31]\, - \address_7[19]\, N_33_0, \address_7[16]\, N_28_0_i_0, - \address_7[15]\, N_26_0_i_0, \address_7[8]\, N_15_0_i_0, - \addr_data_vector[103]\, \addr_data_vector[104]\, - \nb_send[2]_net_1\, \nb_send[4]_net_1\, - \nb_send[5]_net_1\, \nb_send[6]_net_1\, - \nb_send[7]_net_1\, \nb_send[9]_net_1\, - \nb_send[10]_net_1\, \addr_data_vector[127]\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_1, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_63 <= \addr_data_vector[104]\; - addr_data_vector_62 <= \addr_data_vector[103]\; - addr_data_vector_60 <= \addr_data_vector[101]\; - addr_data_vector_59 <= \addr_data_vector[100]\; - addr_data_vector_58 <= \addr_data_vector[99]\; - addr_data_vector_86 <= \addr_data_vector[127]\; - addr_data_vector_85 <= \addr_data_vector[126]\; - addr_data_vector_84 <= \addr_data_vector[125]\; - addr_data_vector_82 <= \addr_data_vector[123]\; - addr_data_vector_80 <= \addr_data_vector[121]\; - addr_data_vector_79 <= \addr_data_vector[120]\; - addr_data_vector_57 <= \addr_data_vector[98]\; - addr_data_vector_78 <= \addr_data_vector[119]\; - addr_data_vector_67 <= \addr_data_vector[108]\; - addr_data_vector_65 <= \addr_data_vector[106]\; - addr_data_vector_61 <= \addr_data_vector[102]\; - addr_data_vector_73 <= \addr_data_vector[114]\; - addr_data_vector_76 <= \addr_data_vector[117]\; - addr_data_vector_69 <= \addr_data_vector[110]\; - addr_data_vector_71 <= \addr_data_vector[112]\; - addr_data_vector_75 <= \addr_data_vector[116]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[112]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[106]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNIC6KH[1]_net_1\, CLK => lclk_c, CLR - => rstn, Q => \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[126]\); - - un1_address_m45 : OR3B - port map(A => \addr_data_vector[123]\, B => - \addr_data_vector[124]\, C => N_44, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => N_62, B => addr_data_f3(26), S => - \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => I_52_10, B => nb_burst_available(9), C => - N_31, Y => N_36); - - un1_address_m61 : AX1 - port map(A => N_42, B => \addr_data_vector[121]\, C => - \addr_data_vector[122]\, Y => N_62); - - un1_address_m37_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[110]\, B => - \addr_data_vector[118]\, C => \addr_data_vector[117]\, Y - => m37_m6_0_a2_4); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[122]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[116]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => I_20_22, B => nb_burst_available(4), C => - I_24_15, Y => \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR2A - port map(A => N_130, B => status_full_ack(3), Y => N_127); - - \address_RNIIMO9[28]\ : MX2C - port map(A => addr_data_vector_19, B => - \addr_data_vector[124]\, S => sel_data_0(1), Y => N_981); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1 - port map(A => N_69, B => \addr_data_vector[100]\, C => - \addr_data_vector[101]\, Y => N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[108]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => I_52_10, B => nb_burst_available(9), C => - N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => N_65_0, B => addr_data_f3(29), S => - \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : AX1 - port map(A => N_18_0, B => \addr_data_vector[106]\, C => - \addr_data_vector[107]\, Y => N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[118]\); - - \address_RNO[23]\ : MX2 - port map(A => N_39, B => addr_data_f3(23), S => - \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[98]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => I_13_34); - - \update_r_RNIPMQ1_0[0]\ : NOR2A - port map(A => \update_r[0]_net_1\, B => \update_r[1]_net_1\, - Y => \un1_state_12_3_0[4]\); - - un1_address_m43 : OR3B - port map(A => \addr_data_vector[121]\, B => - \addr_data_vector[122]\, C => N_42, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => N_60_0, B => addr_data_f3(24), S => - \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f3(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_110, Q => status_full_err(3)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - \nb_send_RNO[1]\ : NOR2B - port map(A => I_5_30, B => state7, Y => \nb_send_5[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => I_31_14); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f3(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[101]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => I_38_11, B => nb_burst_available(7), Y => - \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[111]\); - - \address_RNIAUN9[15]\ : MX2C - port map(A => addr_data_vector_6, B => - \addr_data_vector[111]\, S => sel_data_0(1), Y => N_1354); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[109]\); - - un1_address_m20 : OR3B - port map(A => \addr_data_vector[106]\, B => - \addr_data_vector[107]\, C => N_18_0, Y => N_21_0); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => lclk_c, PRE => rstn, Q - => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => I_52_10, B => state7, Y => \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[115]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[121]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[119]\); - - un1_address_m14 : AX1C - port map(A => \addr_data_vector[103]\, B => N_13_0, C => - \addr_data_vector[104]\, Y => N_15_0_i_0); - - \address_RNIRNPD[22]\ : MX2C - port map(A => addr_data_vector_13, B => - \addr_data_vector[118]\, S => sel_data(1), Y => N_975); - - \address_RNIGRBB[9]\ : MX2C - port map(A => addr_data_vector_0, B => - \addr_data_vector[105]\, S => sel_data_0(1), Y => N_1362); - - un1_address_m29 : AX1 - port map(A => N_27_0, B => \addr_data_vector[112]\, C => - \addr_data_vector[113]\, Y => N_30_0_i_0); - - \address_RNI3OQD[26]\ : MX2C - port map(A => addr_data_vector_17, B => - \addr_data_vector[122]\, S => sel_data(1), Y => N_979); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => I_31_14, Y => - N_30_0); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[125]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[114]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => I_31_14, B => state7, Y => \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => N_58_0, B => addr_data_f3(21), S => - \state_0[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f3(16), S => - \state[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f3(0), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => addr_data_vector_55); - - \state_RNI49HNB1[3]\ : NOR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa); - - GND_i : GND - port map(Y => \GND\); - - \address_RNIEEO9[17]\ : MX2C - port map(A => addr_data_vector_8, B => - \addr_data_vector[113]\, S => sel_data_0(1), Y => N_1356); - - un1_address_m41 : OR3B - port map(A => \addr_data_vector[119]\, B => - \addr_data_vector[120]\, C => N_38_0_i, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => N_63_0, B => addr_data_f3(27), S => - \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[100]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[124]\); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - un1_address_m17 : OR2B - port map(A => N_16_0, B => \addr_data_vector[105]\, Y => - N_18_0); - - \nb_send_RNO[2]\ : NOR2B - port map(A => I_9_30, B => state7, Y => \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => N_124); - - \state_RNIBIMLB1[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => I_9_30, B => nb_burst_available(2), Y => - \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => I_38_11, B => state7, Y => \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => I_24_15); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XNOR3 - port map(A => address_0_sqmuxa, B => - \addr_data_vector[102]\, C => N_5_0, Y => - \un1_address[6]\); - - \state_RNI8OU01[2]\ : NOR3A - port map(A => \state[2]_net_1\, B => update_and_sel_1(6), C - => update_and_sel_1(7), Y => N_130); - - \address_RNO[19]\ : MX2 - port map(A => N_33_0, B => addr_data_f3(19), S => - \state[0]_net_1\, Y => \address_7[19]\); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f3(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[110]\); - - \state_RNO[1]\ : NOR3 - port map(A => N_131, B => status_full_ack(3), C => N_128, Y - => \state_RNO[1]_net_1\); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => I_5_30, Y => - \ACT_LT4_E[2]\); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => lclk_c, CLR => rstn, - E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => I_13_34, Y => - \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f3(14), S => - \state_0[0]_net_1\, Y => \address_7[14]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => I_13_34, B => state7, Y => \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_1, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[120]\); - - un1_address_m27 : XNOR2 - port map(A => N_27_0, B => \addr_data_vector[112]\, Y => - N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[121]\, Y => - N_61_0); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - un1_address_m30 : OR3B - port map(A => \addr_data_vector[112]\, B => - \addr_data_vector[113]\, C => N_27_0, Y => N_31_0); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XOR2 - port map(A => N_16_0, B => \addr_data_vector[105]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => I_45_10); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => I_45_10, B => state7, Y => \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => I_24_15, Y => - \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3B - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => I_52_10, B => nb_burst_available(9), Y => - \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[104]\); - - un1_address_m50 : XNOR2 - port map(A => N_69, B => \addr_data_vector[100]\, Y => - N_51_i_0); - - \state_RNI49HNB1_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - un1_address_m39 : XNOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[98]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => I_56_11, B => nb_burst_available(10), Y => - N_35_1); - - \state_ns_i_a2[1]\ : NOR2 - port map(A => update_and_sel_1(7), B => update_and_sel_1(6), - Y => N_129_i); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f3(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => N_64_0, B => addr_data_f3(28), S => - \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f3(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => I_38_11, C => - N_30_0, Y => N_32); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => I_24_15, B => nb_burst_available(5), Y => - \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => I_31_14, B => nb_burst_available(6), Y => - \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : XNOR2 - port map(A => N_38_0_i, B => \addr_data_vector[119]\, Y => - N_39); - - un1_address_m12 : AO13 - port map(A => address_0_sqmuxa, B => - \addr_data_vector[102]\, C => N_5_0, Y => N_13_0); - - un1_address_m59 : AX1 - port map(A => N_38_0_i, B => \addr_data_vector[119]\, C => - \addr_data_vector[120]\, Y => N_60_0); - - \update_r[0]\ : DFN1C0 - port map(D => update_and_sel_1(6), CLK => lclk_c, CLR => - rstn, Q => \update_r[0]_net_1\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => I_5_30); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f3(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f3(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : NOR3C - port map(A => \addr_data_vector[103]\, B => N_13_0, C => - \addr_data_vector[104]\, Y => N_16_0); - - un1_address_m58 : AX1C - port map(A => \addr_data_vector[117]\, B => N_36_0, C => - \addr_data_vector[118]\, Y => N_59_0); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => I_56_11); - - un1_address_m26 : OR3B - port map(A => \addr_data_vector[110]\, B => - \addr_data_vector[111]\, C => N_24_0, Y => N_27_0); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f3(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[99]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XNOR2 - port map(A => N_46, B => \addr_data_vector[125]\, Y => - N_65_0); - - un1_address_m34 : XNOR2 - port map(A => N_34_0, B => \addr_data_vector[116]\, Y => - N_35_0); - - \address_RNO[30]\ : MX2 - port map(A => N_66_0, B => addr_data_f3(30), S => - \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : NOR3 - port map(A => update_and_sel_1(6), B => update_and_sel_1(7), - C => \state[1]_net_1\, Y => N_128); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[3]_net_1\); - - \update_r_RNI49HNB1[0]\ : OR2B - port map(A => \un1_state_12_3_0[4]\, B => - \un1_state_12_2[4]\, Y => \un1_state_12[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => I_56_11, Y => - N_31); - - un1_address_m54 : AX1 - port map(A => N_21_0, B => \addr_data_vector[108]\, C => - \addr_data_vector[109]\, Y => N_55_0_i_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[103]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => I_38_11); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[5]_net_1\); - - un1_address_m37_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[113]\, B => - \addr_data_vector[114]\, Y => m37_m6_0_a2_2); - - \nb_send_RNO[5]\ : NOR2B - port map(A => I_24_15, B => state7, Y => \nb_send_5[5]\); - - un1_address_m25 : AX1 - port map(A => N_24_0, B => \addr_data_vector[110]\, C => - \addr_data_vector[111]\, Y => N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_0[3]\, CLK => lclk_c, CLR => rstn, - Q => \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_1(7), CLK => lclk_c, CLR => - rstn, Q => \update_r[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => I_38_11, Y => - N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => I_20_22, B => nb_burst_available(4), C => - nb_burst_available(5), Y => \ACT_LT2_E[2]\); - - \state_RNITVKE[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - un1_address_m57 : XOR2 - port map(A => N_36_0, B => \addr_data_vector[117]\, Y => - N_58_0); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - un1_address_m37_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[112]\, B => - \addr_data_vector[111]\, C => m37_m6_0_a2_2, Y => - m37_m6_0_a2_5); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => I_45_10, B => nb_burst_available(8), C => - N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => N_59_0, B => addr_data_f3(22), S => - \state[0]_net_1\, Y => \address_7[22]\); - - \address_RNI5EN9[11]\ : MX2C - port map(A => addr_data_vector_2, B => - \addr_data_vector[107]\, S => sel_data_1(1), Y => N_1364); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[98]\, C => \addr_data_vector[99]\, Y - => N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[105]\); - - \address_RNO[18]\ : MX2 - port map(A => N_57_0, B => addr_data_f3(18), S => - \state_0[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f3(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m37_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[116]\, B => - \addr_data_vector[115]\, C => m37_m6_0_a2_4, Y => - m37_m6_0_a2_6); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[126]\, B => N_47, C => - \addr_data_vector[127]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[102]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => I_13_34, B => nb_burst_available(3), Y => - \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => I_56_11, B => nb_burst_available(10), Y => - \DWACT_BL_EQUAL_0_E[4]\); - - \state_ns_a3_1_RNO[0]\ : NOR2A - port map(A => N_131, B => \state[3]_net_1\, Y => - \state_ns_a3_1_0[0]\); - - un1_address_m23 : OR3B - port map(A => \addr_data_vector[108]\, B => - \addr_data_vector[109]\, C => N_21_0, Y => N_24_0); - - status_full_err_RNO : OR3 - port map(A => \state[3]_net_1\, B => \state[4]_net_1\, C - => N_130, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => \state_RNIC6KH[1]_net_1\, CLK => lclk_c, CLR - => rstn, Q => \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f3(8), S => - \state[0]_net_1\, Y => \address_7[8]\); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => I_52_10); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[107]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[127]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => I_9_30, Y => - \ACT_LT4_E[4]\); - - un1_address_m56 : XNOR2 - port map(A => N_31_0, B => \addr_data_vector[114]\, Y => - N_57_0); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f3(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f3(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => N_61_0, B => addr_data_f3(25), S => - \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[117]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - un1_address_m62 : XNOR2 - port map(A => N_44, B => \addr_data_vector[123]\, Y => - N_63_0); - - un1_address_m32 : AX1 - port map(A => N_31_0, B => \addr_data_vector[114]\, C => - \addr_data_vector[115]\, Y => N_33_0); - - un1_address_m12_e : OR3B - port map(A => \addr_data_vector[100]\, B => - \addr_data_vector[101]\, C => N_69, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => I_9_30); - - \state[1]\ : DFN1C0 - port map(D => \state_RNO[1]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[113]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => I_5_30, Y => - \ACT_LT4_E[1]\); - - \update_r_RNIPMQ1[0]\ : OR2A - port map(A => \update_r[1]_net_1\, B => \update_r[0]_net_1\, - Y => un3_update_r); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[126]\, Y => - N_66_0); - - un1_address_m35 : NOR2A - port map(A => \addr_data_vector[116]\, B => N_34_0, Y => - N_36_0); - - un1_address_m52 : XOR2 - port map(A => N_13_0, B => \addr_data_vector[103]\, Y => - N_1_i_0); - - \address_RNI6EN9[13]\ : MX2C - port map(A => addr_data_vector_4, B => - \addr_data_vector[109]\, S => sel_data_0(1), Y => N_1352); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[123]\); - - un1_address_m37_m6_0_a2 : OR3B - port map(A => m37_m6_0_a2_6, B => m37_m6_0_a2_5, C => - N_24_0, Y => N_38_0_i); - - \address_RNI7GRD[19]\ : MX2C - port map(A => addr_data_vector_10, B => - \addr_data_vector[115]\, S => sel_data(1), Y => N_972); - - \state_RNO[3]\ : OA1 - port map(A => update_and_sel_1(6), B => update_and_sel_1(7), - C => \state[4]_net_1\, Y => \state_RNO_0[3]\); - - un1_address_m21 : XNOR2 - port map(A => N_21_0, B => \addr_data_vector[108]\, Y => - N_22_0_i_0); - - \state_ns_a3_1[0]\ : NAND2 - port map(A => N_129_i, B => \state_ns_a3_1_0[0]\, Y => - N_125); - - \nb_send_RNO[4]\ : NOR2B - port map(A => I_20_22, B => state7, Y => \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => I_56_11, B => state7, Y => \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => I_45_10, B => nb_burst_available(8), Y => - N_29); - - un1_address_m55 : XNOR2 - port map(A => N_24_0, B => \addr_data_vector[110]\, Y => - N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f3(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : OR3B - port map(A => \addr_data_vector[98]\, B => - \addr_data_vector[99]\, C => \un1_state_12[4]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => I_20_22, B => nb_burst_available(4), Y => - \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f3(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => I_45_10, B => nb_burst_available(8), Y => - \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f3(1), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => addr_data_vector_56); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_11, Q => status_full(3)); - - un1_address_m63 : AX1 - port map(A => N_44, B => \addr_data_vector[123]\, C => - \addr_data_vector[124]\, Y => N_64_0); - - un1_address_m33 : OR3B - port map(A => \addr_data_vector[114]\, B => - \addr_data_vector[115]\, C => N_31_0, Y => N_34_0); - - \state_RNIC6KH[1]\ : NOR2A - port map(A => status_full_ack(3), B => N_131, Y => - \state_RNIC6KH[1]_net_1\); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => N_35_0, B => addr_data_f3(20), S => - \state_0[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR2A - port map(A => \addr_data_vector[125]\, B => N_46, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : XNOR2 - port map(A => N_18_0, B => \addr_data_vector[106]\, Y => - N_54_0_i_0); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f3(15), S => - \state[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => I_20_22); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity DMA2AHB is - - port( hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - Address_RNIP8BS : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - Address_RNIJ4SP : in std_logic_vector(20 to 20); - iosn_1 : in std_logic_vector(93 to 93); - nhmaster_1_i : in std_logic_vector(0 to 0); - hsize : out std_logic_vector(1 downto 0); - un7_dmain : in std_logic_vector(66 to 66); - hmaster_0 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - hgrant : in std_logic_vector(3 to 3); - iosn_0 : in std_logic_vector(93 to 93); - Ready : out std_logic; - N_1021 : in std_logic; - N_1032 : in std_logic; - N_1027 : in std_logic; - OKAY : out std_logic; - IdlePhase : out std_logic; - N_1018 : in std_logic; - N_1025 : in std_logic; - N_1042 : in std_logic; - N_1034 : in std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - N_1082 : in std_logic; - N_1048 : in std_logic; - N_1047 : in std_logic; - N_1036 : in std_logic; - N_1035 : in std_logic; - N_1019 : in std_logic; - N_1046 : in std_logic; - N_1044 : in std_logic; - N_1043 : in std_logic; - N_1041 : in std_logic; - N_1040 : in std_logic; - N_1039 : in std_logic; - N_1038 : in std_logic; - N_1033 : in std_logic; - N_1031 : in std_logic; - N_1030 : in std_logic; - N_1029 : in std_logic; - N_1028 : in std_logic; - N_1026 : in std_logic; - N_1024 : in std_logic; - N_1023 : in std_logic; - N_1022 : in std_logic; - N_1020 : in std_logic; - N_1045 : in std_logic; - Grant_0 : out std_logic; - Grant : out std_logic; - arb_1 : in std_logic; - N_1081 : in std_logic; - hbusreq_i_3 : out std_logic; - Grant_1_0 : out std_logic; - Fault : out std_logic; - time_select_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end DMA2AHB; - -architecture DEF_ARCH of DMA2AHB is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \AddressPhase_0\, \AddressPhase_RNIGMGKAH1\, - hsize_0_sqmuxa_0, un5_ahbinhgrantx, - BoundaryPhase_2_sqmuxa_i_0_0, ReDataPhase_0_sqmuxa_i_0_0, - \ReDataPhase\, \un1_dmain_20_0\, - \hburst_11_i_a2_i_a3_0[1]\, hwrite_1_sqmuxa, - un1_AddressPhase_0_sqmuxa_1_0, - un1_AddressPhase_0_sqmuxa_1_0_0_tz, \hburst_11_0_a2_1[0]\, - un77_ahbinhgrantx, hburst_0_sqmuxa, un1_ahbin_3_0, - un1_ActivePhase, WriteAcc_m_0, \WriteAcc\, - un37_ahbinhgrantx, AddressPhase_1_sqmuxa_0, \ReAddrPhase\, - Grant_1_2, Grant_N_15, Grant_1_0_0, Grant_N_13, - Grant_m10_i_a5_1_0, Grant_m10_i_a5_0_0, - BoundaryPhase_0_sqmuxa_0, BoundaryPhase_0_sqmuxa_8_2, - BoundaryPhase_0_sqmuxa_8_1, BoundaryPhase_0_sqmuxa_6_0, - un84_ahbinhgrantx_0, un7_addressphase_0, \DataPhase\, - un46_ahbinhgrantx, AddressPhase_2_sqmuxa_0, - un84_ahbinhgrantx, N_30, hburst_2_sqmuxa_1, - \ReDataPhase_RNO\, \hsize_RNO[0]\, - BoundaryPhase_2_sqmuxa_i_0, N_343, \BoundaryPhase\, - BoundaryPhase_1_sqmuxa_1, un1_dmain_15, un78_ahbinhgrantx, - un1_dmain_20, AddressPhase_1_sqmuxa, un7_addressphase, - un23_ahbinhgrantx, un75_ahbinhgrantx, \ActivePhase\, - WriteAcc_m, BoundaryPhase_0_sqmuxa, - BoundaryPhase_0_sqmuxa_6, AddressSave_0_sqmuxa, - un1_ahbin_3, \hburst_11[0]\, \Grant_1_0\, \Grant_0\, - \EarlyPhase\, N_374, \AddressSave[20]_net_1\, - \AddressSave_4[20]\, N_382, \AddressSave[28]_net_1\, - \AddressSave_4[28]\, N_57_0, N_39, \Address_9[28]\, N_278, - \Address_RNO[28]_net_1\, \haddr[28]\, - \AddressSave_RNO[20]_net_1\, \AddressSave_RNO[28]_net_1\, - N_356, \AddressSave[2]_net_1\, \AddressSave_4[2]\, N_357, - \AddressSave[3]_net_1\, \AddressSave_4[3]\, N_359, - \AddressSave[5]_net_1\, \AddressSave_4[5]\, N_360, - \AddressSave[6]_net_1\, \AddressSave_4[6]\, N_361, - \AddressSave[7]_net_1\, \AddressSave_4[7]\, N_362, - \AddressSave[8]_net_1\, \AddressSave_4[8]\, N_363, - \AddressSave[9]_net_1\, \AddressSave_4[9]\, N_365, - \AddressSave[11]_net_1\, \AddressSave_4[11]\, N_366, - \AddressSave[12]_net_1\, \AddressSave_4[12]\, N_367, - \AddressSave[13]_net_1\, \AddressSave_4[13]\, N_368, - \AddressSave[14]_net_1\, \AddressSave_4[14]\, N_370, - \AddressSave[16]_net_1\, \AddressSave_4[16]\, N_372, - \AddressSave[18]_net_1\, \AddressSave_4[18]\, N_373, - \AddressSave[19]_net_1\, \AddressSave_4[19]\, N_375, - \AddressSave[21]_net_1\, \AddressSave_4[21]\, - hsize_0_sqmuxa, N_376, \AddressSave[22]_net_1\, - \AddressSave_4[22]\, N_377, \AddressSave[23]_net_1\, - \AddressSave_4[23]\, N_378, \AddressSave[24]_net_1\, - \AddressSave_4[24]\, N_380, \AddressSave[26]_net_1\, - \AddressSave_4[26]\, N_381, \AddressSave[27]_net_1\, - \AddressSave_4[27]\, N_383, \AddressSave[29]_net_1\, - \AddressSave_4[29]\, N_384, \AddressSave[30]_net_1\, - \AddressSave_4[30]\, N_385, \AddressSave[31]_net_1\, - \AddressSave_4[31]\, N_4, \haddr[2]\, N_6_0, \haddr[5]\, - N_5_0, N_13_0, N_15_0, N_16_0, N_19_0, N_18_0, N_23_0, - N_22_0, N_25_0, \haddr[18]\, N_26_0, \haddr[19]\, N_28_0, - N_29_0, \haddr[20]\, \haddr[21]\, N_30_0, N_32_0, - \haddr[22]\, N_33_0_i, N_37_i, N_36, \haddr[26]\, N_41, - N_42_i, N_43, \haddr[3]\, N_45, N_46, \haddr[6]\, N_84_i, - N_9_0, \haddr[9]\, N_49_0, \haddr[7]\, N_50_0, - \haddr[10]\, \haddr[11]\, N_51_0, \haddr[12]\, N_52_0, - \haddr[13]\, N_54_0, N_55_0_i, \haddr[23]\, N_56_0_i, - \haddr[27]\, N_58_0_i, \haddr[29]\, N_60_0, \haddr[30]\, - N_253, N_255, \Address_9[3]\, \Address_9[5]\, - \Address_9[6]\, N_256, \Address_9[7]\, N_257, - \Address_9[9]\, N_259, \Address_9[29]\, N_279, - \Address_RNO[3]_net_1\, \Address_RNO[5]_net_1\, - \Address_RNO[6]_net_1\, \Address_RNO[7]_net_1\, - \Address_RNO[9]_net_1\, \Address_RNO[29]_net_1\, N_261, - N_262, N_263, N_264, N_266, N_271, N_272, N_273, N_274, - N_276, N_277, \Address_9[22]\, \Address_9[23]\, - \Address_9[24]\, \Address_9[26]\, \Address_9[27]\, - \Address_9[30]\, N_280, \Address_9[31]\, N_281, - \haddr[14]\, \haddr[16]\, \AddressPhase\, \haddr[24]\, - \haddr[31]\, N_252, N_268, N_269, N_270, \Address_9[2]\, - \Address_9[11]\, \Address_9[12]\, - ReDataPhase_0_sqmuxa_i_0, \Address_9[13]\, - \Address_9[14]\, \Address_9[16]\, \Address_9[18]\, - \Address_9[19]\, \Address_9[20]\, \Address_9[21]\, - \Address_RNO[2]_net_1\, \Address_RNO[11]_net_1\, - \Address_RNO[12]_net_1\, \Address_RNO[13]_net_1\, - \Address_RNO[14]_net_1\, \Address_RNO[16]_net_1\, - \Address_RNO[18]_net_1\, \Address_RNO[19]_net_1\, - \Address_RNO[20]_net_1\, \Address_RNO[21]_net_1\, - \Address_RNO[22]_net_1\, \Address_RNO[23]_net_1\, - \Address_RNO[24]_net_1\, \Address_RNO[26]_net_1\, - \Address_RNO[27]_net_1\, \Address_RNO[30]_net_1\, - \Address_RNO[31]_net_1\, \AddressSave_RNO[6]_net_1\, - \AddressSave_RNO[7]_net_1\, \AddressSave_RNO[13]_net_1\, - \AddressSave_RNO[14]_net_1\, \AddressSave_RNO[21]_net_1\, - \AddressSave_RNO[27]_net_1\, \AddressSave_RNO[5]_net_1\, - \AddressSave_RNO[8]_net_1\, \AddressSave_RNO[12]_net_1\, - \AddressSave_RNO[19]_net_1\, \AddressSave_RNO[22]_net_1\, - \AddressSave_RNO[26]_net_1\, \AddressSave_RNO[29]_net_1\, - \AddressSave_RNO[9]_net_1\, \AddressSave_RNO[11]_net_1\, - \AddressSave_RNO[16]_net_1\, \AddressSave_RNO[18]_net_1\, - \AddressSave_RNO[23]_net_1\, \AddressSave_RNO[30]_net_1\, - \AddressSave_RNO[2]_net_1\, \AddressSave_RNO[3]_net_1\, - N_26, N_28, un45_ahbinhgrantx, un28_ahbinhgrantx_i_0, - BoundaryPhase_0_sqmuxa_1, N_422_i, \htrans_12[0]\, - \htrans_RNO_2[0]\, htrans_4_sqmuxa, hwrite_0_sqmuxa_1, - N_344, hwrite_2_sqmuxa, N_345, N_346, \SingleAcc\, - \SingleAcc_RNO\, \WriteAcc_RNO\, \ActivePhase_RNO\, - htrans_4_sqmuxa_1, htrans_1_sqmuxa, N_341, hwrite_8, - \DataPhase_RNI2ITCNO\, hwrite_RNO, - \AddressSave_RNO[17]_net_1\, N_371, - \AddressSave_RNO[25]_net_1\, N_379, - \AddressSave_RNO[1]_net_1\, N_355, - \Address_RNO[25]_net_1\, \Address_9[25]\, - \Address_RNO[17]_net_1\, \Address_9[17]\, - \Address_RNO[1]_net_1\, \Address_9[1]\, - \AddressSave[17]_net_1\, N_267, \AddressSave[1]_net_1\, - N_251, N_21_0, \AddressSave_4[25]\, \AddressSave_4[17]\, - \haddr[8]\, \AddressSave_4[1]\, \AddressSave[25]_net_1\, - N_275, N_35_i, N_258, N_83_i, \haddr[1]\, - \Address_RNO[8]_net_1\, \Address_9[8]\, \haddr[25]\, - \haddr[17]\, N_350, dataphase10, un1_redataphase21, - hburst_2_sqmuxa, data2, \IdlePhase_RNO\, Data_0_sqmuxa, - \hbusreq_i_3\, N_247, IdlePhase_net_1, N_351, - \EarlyPhase_RNO\, IdlePhase_1_sqmuxa, \Fault\, N_423_i, - N_349, \ReAddrPhase_RNO\, \AddressSave_RNO[10]_net_1\, - N_364, \AddressSave_RNO[15]_net_1\, N_369, - \Address_RNO[15]_net_1\, \Address_9[15]\, - \Address_RNO[10]_net_1\, \Address_9[10]\, - \AddressSave[15]_net_1\, N_265, \AddressSave[10]_net_1\, - N_260, N_11_0, \AddressSave_4[15]\, \AddressSave_4[10]\, - N_53_0, \haddr[15]\, N_354, \AddressSave[0]_net_1\, - \AddressSave_4[0]\, N_250, \haddr[0]\, \Address_9[0]\, - \Address_RNO[0]_net_1\, \AddressSave_RNO[0]_net_1\, - \AddressSave_RNO[4]_net_1\, N_358, \hsize_RNO[1]\, - \AddressSave_4[4]\, \haddr[4]\, \Address_RNO[4]_net_1\, - \Address_9[4]\, \AddressSave[4]_net_1\, N_254, N_44, - \hwrite\, \hsize[0]\, \hsize[1]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - hsize(1) <= \hsize[1]\; - hsize(0) <= \hsize[0]\; - haddr(31) <= \haddr[31]\; - haddr(30) <= \haddr[30]\; - haddr(29) <= \haddr[29]\; - haddr(28) <= \haddr[28]\; - haddr(27) <= \haddr[27]\; - haddr(26) <= \haddr[26]\; - haddr(25) <= \haddr[25]\; - haddr(24) <= \haddr[24]\; - haddr(23) <= \haddr[23]\; - haddr(22) <= \haddr[22]\; - haddr(21) <= \haddr[21]\; - haddr(20) <= \haddr[20]\; - haddr(19) <= \haddr[19]\; - haddr(18) <= \haddr[18]\; - haddr(17) <= \haddr[17]\; - haddr(16) <= \haddr[16]\; - haddr(15) <= \haddr[15]\; - haddr(14) <= \haddr[14]\; - haddr(13) <= \haddr[13]\; - haddr(12) <= \haddr[12]\; - haddr(11) <= \haddr[11]\; - haddr(10) <= \haddr[10]\; - haddr(9) <= \haddr[9]\; - haddr(8) <= \haddr[8]\; - haddr(7) <= \haddr[7]\; - haddr(6) <= \haddr[6]\; - haddr(5) <= \haddr[5]\; - haddr(4) <= \haddr[4]\; - haddr(3) <= \haddr[3]\; - haddr(2) <= \haddr[2]\; - haddr(1) <= \haddr[1]\; - haddr(0) <= \haddr[0]\; - IdlePhase <= IdlePhase_net_1; - hwrite <= \hwrite\; - Grant_0 <= \Grant_0\; - hbusreq_i_3 <= \hbusreq_i_3\; - Grant_1_0 <= \Grant_1_0\; - Fault <= \Fault\; - - \AHBOut.hwrite_RNO_0\ : MX2 - port map(A => hwrite_8, B => \hwrite\, S => - \DataPhase_RNI2ITCNO\, Y => N_341); - - \Address[16]\ : DFN1 - port map(D => \Address_RNO[16]_net_1\, CLK => lclk_c, Q => - \haddr[16]\); - - \Address[10]\ : DFN1 - port map(D => \Address_RNO[10]_net_1\, CLK => lclk_c, Q => - \haddr[10]\); - - \Address_RNO_1[3]\ : MX2C - port map(A => N_1020, B => N_43, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_253); - - \Address[30]\ : DFN1 - port map(D => \Address_RNO[30]_net_1\, CLK => lclk_c, Q => - \haddr[30]\); - - \AddressSave_RNO_0[30]\ : MX2 - port map(A => \AddressSave[30]_net_1\, B => - \AddressSave_4[30]\, S => hsize_0_sqmuxa, Y => N_384); - - \AddressSave[8]\ : DFN1 - port map(D => \AddressSave_RNO[8]_net_1\, CLK => lclk_c, Q - => \AddressSave[8]_net_1\); - - \Address_RNO_1[0]\ : MX2 - port map(A => Address_RNIP8BS(0), B => \haddr[0]\, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_250); - - ActivePhase_RNIEFSN : NOR2A - port map(A => \ActivePhase\, B => un46_ahbinhgrantx, Y => - hwrite_0_sqmuxa_1); - - IdlePhase_RNI439S49 : NOR3C - port map(A => Grant_N_15, B => Grant_1_0_0, C => Grant_N_13, - Y => Grant_1_2); - - \AHBOut.hsize_RNO[1]\ : OA1 - port map(A => \hsize[1]\, B => hsize_0_sqmuxa, C => rstn, Y - => \hsize_RNO[1]\); - - \Address_RNO[26]\ : NOR2A - port map(A => rstn, B => \Address_9[26]\, Y => - \Address_RNO[26]_net_1\); - - \AddressSave_RNO_0[12]\ : MX2 - port map(A => \AddressSave[12]_net_1\, B => - \AddressSave_4[12]\, S => hsize_0_sqmuxa_0, Y => N_366); - - \AddressSave_RNO_1[1]\ : MX2 - port map(A => N_1018, B => \haddr[1]\, S => \AddressPhase\, - Y => \AddressSave_4[1]\); - - un1_AddressSave_0_sqmuxa_1_m55 : AX1E - port map(A => \haddr[26]\, B => N_36, C => \haddr[27]\, Y - => N_56_0_i); - - \Address_RNO[1]\ : NOR2A - port map(A => rstn, B => \Address_9[1]\, Y => - \Address_RNO[1]_net_1\); - - DataPhase_RNI543F1 : OR2B - port map(A => \DataPhase\, B => iosn_2(93), Y => data2); - - \AddressSave_RNO_0[10]\ : MX2 - port map(A => \AddressSave[10]_net_1\, B => - \AddressSave_4[10]\, S => hsize_0_sqmuxa, Y => N_364); - - \AddressSave_RNO_0[27]\ : MX2 - port map(A => \AddressSave[27]_net_1\, B => - \AddressSave_4[27]\, S => hsize_0_sqmuxa, Y => N_381); - - \AddressSave[15]\ : DFN1 - port map(D => \AddressSave_RNO[15]_net_1\, CLK => lclk_c, Q - => \AddressSave[15]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m50 : XNOR2 - port map(A => N_13_0, B => \haddr[12]\, Y => N_51_0); - - \Address[26]\ : DFN1 - port map(D => \Address_RNO[26]_net_1\, CLK => lclk_c, Q => - \haddr[26]\); - - \Address[20]\ : DFN1 - port map(D => \Address_RNO[20]_net_1\, CLK => lclk_c, Q => - \haddr[20]\); - - ReDataPhase_RNIC49RKO : AO1D - port map(A => \ReDataPhase\, B => - un1_AddressPhase_0_sqmuxa_1_0_0_tz, C => hgrant(3), Y => - un1_AddressPhase_0_sqmuxa_1_0); - - \AddressSave[12]\ : DFN1 - port map(D => \AddressSave_RNO[12]_net_1\, CLK => lclk_c, Q - => \AddressSave[12]_net_1\); - - \AddressSave_RNO_1[16]\ : MX2A - port map(A => N_1033, B => \haddr[16]\, S => - \AddressPhase_0\, Y => \AddressSave_4[16]\); - - EarlyPhase_RNIPI2N : OR3B - port map(A => N_1081, B => un7_dmain(66), C => - un37_ahbinhgrantx, Y => un46_ahbinhgrantx); - - \Address_RNO_1[8]\ : MX2C - port map(A => N_1025, B => N_83_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_258); - - un1_dmain_20_0 : OR2B - port map(A => iosn_0(93), B => rstn, Y => \un1_dmain_20_0\); - - DataPhase_RNI6VTV1 : NOR2B - port map(A => un1_redataphase21, B => rstn, Y => - htrans_4_sqmuxa); - - BoundaryPhase_RNO : AOI1B - port map(A => N_343, B => BoundaryPhase_0_sqmuxa_1, C => - rstn, Y => N_422_i); - - un1_AddressSave_0_sqmuxa_1_m31 : NOR3C - port map(A => \haddr[22]\, B => N_29_0, C => \haddr[23]\, Y - => N_32_0); - - IdlePhase_RNO : NOR2B - port map(A => N_350, B => rstn, Y => \IdlePhase_RNO\); - - un1_AddressSave_0_sqmuxa_1_m47 : XOR2 - port map(A => N_9_0, B => \haddr[9]\, Y => N_84_i); - - \AHBOut.hsize[1]\ : DFN1 - port map(D => \hsize_RNO[1]\, CLK => lclk_c, Q => - \hsize[1]\); - - ActivePhase_RNO_2 : OR2 - port map(A => \DataPhase\, B => \AddressPhase_0\, Y => - un7_addressphase_0); - - \AHBOut.hburst_RNO_1[0]\ : OR2B - port map(A => un23_ahbinhgrantx, B => \SingleAcc\, Y => - hburst_0_sqmuxa); - - \Address_RNO_0[11]\ : MX2C - port map(A => \AddressSave[11]_net_1\, B => N_261, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[11]\); - - \Address_RNO_0[8]\ : MX2C - port map(A => \AddressSave[8]_net_1\, B => N_258, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[8]\); - - \Address_RNO_1[21]\ : MX2C - port map(A => N_1038, B => N_28_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_271); - - \AHBOut.hwrite\ : DFN1 - port map(D => hwrite_RNO, CLK => lclk_c, Q => \hwrite\); - - \Address[12]\ : DFN1 - port map(D => \Address_RNO[12]_net_1\, CLK => lclk_c, Q => - \haddr[12]\); - - \AddressSave[23]\ : DFN1 - port map(D => \AddressSave_RNO[23]_net_1\, CLK => lclk_c, Q - => \AddressSave[23]_net_1\); - - ActivePhase_RNIS76QLO : OA1 - port map(A => un84_ahbinhgrantx, B => hwrite_1_sqmuxa, C - => hburst_2_sqmuxa_1, Y => hwrite_2_sqmuxa); - - \AddressSave_RNO_0[8]\ : MX2 - port map(A => \AddressSave[8]_net_1\, B => - \AddressSave_4[8]\, S => hsize_0_sqmuxa_0, Y => N_362); - - \AddressSave_RNO_1[31]\ : MX2A - port map(A => N_1048, B => \haddr[31]\, S => \AddressPhase\, - Y => \AddressSave_4[31]\); - - \AddressSave_RNO[5]\ : NOR2B - port map(A => N_359, B => rstn, Y => - \AddressSave_RNO[5]_net_1\); - - \Address_RNO_1[11]\ : MX2C - port map(A => N_1028, B => N_50_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_261); - - \AddressSave_RNO[18]\ : NOR2B - port map(A => N_372, B => rstn, Y => - \AddressSave_RNO[18]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m41 : XNOR2 - port map(A => N_41, B => \haddr[30]\, Y => N_42_i); - - \Address_RNO[29]\ : NOR2A - port map(A => rstn, B => \Address_9[29]\, Y => - \Address_RNO[29]_net_1\); - - \AddressSave_RNO_1[28]\ : MX2A - port map(A => N_1045, B => \haddr[28]\, S => - \AddressPhase_0\, Y => \AddressSave_4[28]\); - - WriteAcc_RNO : NOR2B - port map(A => N_345, B => rstn, Y => \WriteAcc_RNO\); - - \AddressSave_RNO[11]\ : NOR2B - port map(A => N_365, B => rstn, Y => - \AddressSave_RNO[11]_net_1\); - - SingleAcc_RNO : NOR2B - port map(A => N_346, B => rstn, Y => \SingleAcc_RNO\); - - \Address[22]\ : DFN1 - port map(D => \Address_RNO[22]_net_1\, CLK => lclk_c, Q => - \haddr[22]\); - - \Address_RNO[23]\ : NOR2A - port map(A => rstn, B => \Address_9[23]\, Y => - \Address_RNO[23]_net_1\); - - \Address[2]\ : DFN1 - port map(D => \Address_RNO[2]_net_1\, CLK => lclk_c, Q => - \haddr[2]\); - - \Address_RNO_1[7]\ : MX2C - port map(A => N_1024, B => N_49_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_257); - - ReDataPhase_RNI5DK9 : OR2 - port map(A => N_1081, B => \ReDataPhase\, Y => un1_dmain_6); - - \Address_RNO[24]\ : NOR2A - port map(A => rstn, B => \Address_9[24]\, Y => - \Address_RNO[24]_net_1\); - - \Address_RNO[10]\ : NOR2A - port map(A => rstn, B => \Address_9[10]\, Y => - \Address_RNO[10]_net_1\); - - \AddressSave[20]\ : DFN1 - port map(D => \AddressSave_RNO[20]_net_1\, CLK => lclk_c, Q - => \AddressSave[20]_net_1\); - - \Address_RNO_1[30]\ : MX2C - port map(A => N_1047, B => N_42_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_280); - - \AddressSave_RNO_1[3]\ : MX2A - port map(A => N_1020, B => \haddr[3]\, S => - \AddressPhase_0\, Y => \AddressSave_4[3]\); - - \AddressSave_RNO_1[19]\ : MX2A - port map(A => N_1036, B => \haddr[19]\, S => - \AddressPhase_0\, Y => \AddressSave_4[19]\); - - ActivePhase_RNIEFSN_0 : NOR2 - port map(A => \ActivePhase\, B => un46_ahbinhgrantx, Y => - hwrite_1_sqmuxa); - - EarlyPhase_RNO_1 : OAI1 - port map(A => hgrant(3), B => un37_ahbinhgrantx, C => - un1_ahbin_3_0, Y => un1_ahbin_3); - - \AddressSave_RNO_1[24]\ : MX2A - port map(A => N_1041, B => \haddr[24]\, S => \AddressPhase\, - Y => \AddressSave_4[24]\); - - IdlePhase_RNIL9CU3 : AOI1 - port map(A => Grant_m10_i_a5_1_0, B => - hmaster_0_0_RNIFCVH1_0(1), C => \Grant_1_0\, Y => - Grant_1_0_0); - - \DMAOut.Ready_RNO\ : NOR2A - port map(A => rstn, B => data2, Y => Data_0_sqmuxa); - - \AddressSave_RNO[25]\ : NOR2B - port map(A => N_379, B => rstn, Y => - \AddressSave_RNO[25]_net_1\); - - \AddressSave_RNO_1[23]\ : MX2A - port map(A => N_1040, B => \haddr[23]\, S => \AddressPhase\, - Y => \AddressSave_4[23]\); - - \DMAOut.Grant_m10_i_a5_0_0\ : NOR2B - port map(A => hmaster_0_0_RNIFCVH1_0(1), B => bco_msb_1(1), - Y => Grant_m10_i_a5_0_0); - - \Address_RNO[9]\ : NOR2A - port map(A => rstn, B => \Address_9[9]\, Y => - \Address_RNO[9]_net_1\); - - \Address[5]\ : DFN1 - port map(D => \Address_RNO[5]_net_1\, CLK => lclk_c, Q => - \haddr[5]\); - - \AddressSave[30]\ : DFN1 - port map(D => \AddressSave_RNO[30]_net_1\, CLK => lclk_c, Q - => \AddressSave[30]_net_1\); - - AddressPhase_RNIM1LFIO : OR2A - port map(A => \AddressPhase\, B => AddressPhase_1_sqmuxa, Y - => htrans_1_sqmuxa); - - \Address[15]\ : DFN1 - port map(D => \Address_RNO[15]_net_1\, CLK => lclk_c, Q => - \haddr[15]\); - - ReAddrPhase_RNIBST1 : OR2 - port map(A => \ReDataPhase\, B => \ReAddrPhase\, Y => - un23_ahbinhgrantx); - - \AHBOut.hburst[2]\ : DFN1E0 - port map(D => N_30, CLK => lclk_c, E => - \DataPhase_RNI2ITCNO\, Q => hburst(2)); - - ActivePhase_RNI0PJVIO : OR2A - port map(A => hwrite_0_sqmuxa_1, B => hgrant(3), Y => - htrans_4_sqmuxa_1); - - \Address_RNO_0[9]\ : MX2C - port map(A => \AddressSave[9]_net_1\, B => N_259, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[9]\); - - \Address[13]\ : DFN1 - port map(D => \Address_RNO[13]_net_1\, CLK => lclk_c, Q => - \haddr[13]\); - - \AddressSave_RNO_1[15]\ : MX2A - port map(A => N_1032, B => \haddr[15]\, S => \AddressPhase\, - Y => \AddressSave_4[15]\); - - \AddressSave_RNO_1[11]\ : MX2A - port map(A => N_1028, B => \haddr[11]\, S => - \AddressPhase_0\, Y => \AddressSave_4[11]\); - - \AddressSave_RNO_0[18]\ : MX2 - port map(A => \AddressSave[18]_net_1\, B => - \AddressSave_4[18]\, S => hsize_0_sqmuxa_0, Y => N_372); - - \AddressSave[6]\ : DFN1 - port map(D => \AddressSave_RNO[6]_net_1\, CLK => lclk_c, Q - => \AddressSave[6]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m24 : AX1E - port map(A => \haddr[18]\, B => N_22_0, C => \haddr[19]\, Y - => N_25_0); - - \Address_RNO_1[4]\ : MX2C - port map(A => N_1021, B => N_44, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_254); - - \Address[19]\ : DFN1 - port map(D => \Address_RNO[19]_net_1\, CLK => lclk_c, Q => - \haddr[19]\); - - BoundaryPhase_RNO_0 : OR3B - port map(A => \BoundaryPhase\, B => - BoundaryPhase_2_sqmuxa_i_0_0, C => - BoundaryPhase_1_sqmuxa_1, Y => N_343); - - \Address[25]\ : DFN1 - port map(D => \Address_RNO[25]_net_1\, CLK => lclk_c, Q => - \haddr[25]\); - - \Address_RNIS61N1[9]\ : NOR3C - port map(A => BoundaryPhase_0_sqmuxa_6, B => - BoundaryPhase_0_sqmuxa_8_2, C => BoundaryPhase_0_sqmuxa_0, - Y => BoundaryPhase_0_sqmuxa); - - un1_AddressSave_0_sqmuxa_1_m12 : NOR3C - port map(A => \haddr[10]\, B => BoundaryPhase_0_sqmuxa, C - => \haddr[11]\, Y => N_13_0); - - \Address_RNO_0[27]\ : MX2C - port map(A => \AddressSave[27]_net_1\, B => N_277, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[27]\); - - \AddressSave_RNO[7]\ : NOR2B - port map(A => N_361, B => rstn, Y => - \AddressSave_RNO[7]_net_1\); - - \Address[23]\ : DFN1 - port map(D => \Address_RNO[23]_net_1\, CLK => lclk_c, Q => - \haddr[23]\); - - \AddressSave_RNO_1[7]\ : MX2A - port map(A => N_1024, B => \haddr[7]\, S => - \AddressPhase_0\, Y => \AddressSave_4[7]\); - - \AHBOut.htrans[1]\ : DFN1E0 - port map(D => un1_dmain_20, CLK => lclk_c, E => - htrans_4_sqmuxa, Q => htrans(1)); - - WriteAcc_RNO_0 : MX2 - port map(A => \WriteAcc\, B => N_1082, S => hwrite_2_sqmuxa, - Y => N_345); - - \AddressSave_RNO[29]\ : NOR2B - port map(A => N_383, B => rstn, Y => - \AddressSave_RNO[29]_net_1\); - - \AddressSave_RNO_0[14]\ : MX2 - port map(A => \AddressSave[14]_net_1\, B => - \AddressSave_4[14]\, S => hsize_0_sqmuxa_0, Y => N_368); - - \Address[29]\ : DFN1 - port map(D => \Address_RNO[29]_net_1\, CLK => lclk_c, Q => - \haddr[29]\); - - ReDataPhase_RNIQF9GJO_0 : OR3B - port map(A => \ReDataPhase\, B => iosn_1(93), C => - hgrant(3), Y => ReDataPhase_0_sqmuxa_i_0); - - \Address[18]\ : DFN1 - port map(D => \Address_RNO[18]_net_1\, CLK => lclk_c, Q => - \haddr[18]\); - - \AddressSave_RNO[10]\ : NOR2B - port map(A => N_364, B => rstn, Y => - \AddressSave_RNO[10]_net_1\); - - \AddressSave[16]\ : DFN1 - port map(D => \AddressSave_RNO[16]_net_1\, CLK => lclk_c, Q - => \AddressSave[16]_net_1\); - - \AddressSave_RNO_1[26]\ : MX2A - port map(A => N_1043, B => \haddr[26]\, S => \AddressPhase\, - Y => \AddressSave_4[26]\); - - \AddressSave_RNO_0[13]\ : MX2 - port map(A => \AddressSave[13]_net_1\, B => - \AddressSave_4[13]\, S => hsize_0_sqmuxa_0, Y => N_367); - - ActivePhase_RNO : NOR2B - port map(A => N_344, B => rstn, Y => \ActivePhase_RNO\); - - \Address_RNO[21]\ : NOR2A - port map(A => rstn, B => \Address_9[21]\, Y => - \Address_RNO[21]_net_1\); - - \Address_RNO[16]\ : NOR2A - port map(A => rstn, B => \Address_9[16]\, Y => - \Address_RNO[16]_net_1\); - - \Address_RNO_0[30]\ : MX2C - port map(A => \AddressSave[30]_net_1\, B => N_280, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[30]\); - - \Address_RNO_0[24]\ : MX2C - port map(A => \AddressSave[24]_net_1\, B => N_274, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[24]\); - - ActivePhase_RNIE4351 : OR2A - port map(A => un75_ahbinhgrantx, B => un45_ahbinhgrantx, Y - => un77_ahbinhgrantx); - - \Address_RNO_0[25]\ : MX2C - port map(A => \AddressSave[25]_net_1\, B => N_275, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[25]\); - - \Address[0]\ : DFN1 - port map(D => \Address_RNO[0]_net_1\, CLK => lclk_c, Q => - \haddr[0]\); - - \AddressSave_RNO[22]\ : NOR2B - port map(A => N_376, B => rstn, Y => - \AddressSave_RNO[22]_net_1\); - - BoundaryPhase_RNO_1 : OR2A - port map(A => BoundaryPhase_0_sqmuxa, B => - BoundaryPhase_1_sqmuxa_1, Y => BoundaryPhase_0_sqmuxa_1); - - GND_i : GND - port map(Y => \GND\); - - \AddressSave_RNO_0[6]\ : MX2 - port map(A => \AddressSave[6]_net_1\, B => - \AddressSave_4[6]\, S => hsize_0_sqmuxa_0, Y => N_360); - - \AHBOut.hburst_RNO_0[0]\ : NOR3C - port map(A => un77_ahbinhgrantx, B => hburst_0_sqmuxa, C - => \Fault\, Y => \hburst_11_0_a2_1[0]\); - - DataPhase_RNI2ITCNO : OA1 - port map(A => hburst_2_sqmuxa, B => un1_redataphase21, C - => rstn, Y => \DataPhase_RNI2ITCNO\); - - \AddressSave_RNO[16]\ : NOR2B - port map(A => N_370, B => rstn, Y => - \AddressSave_RNO[16]_net_1\); - - \Address_RNO[27]\ : NOR2A - port map(A => rstn, B => \Address_9[27]\, Y => - \Address_RNO[27]_net_1\); - - \Address[4]\ : DFN1 - port map(D => \Address_RNO[4]_net_1\, CLK => lclk_c, Q => - \haddr[4]\); - - \Address[28]\ : DFN1 - port map(D => \Address_RNO[28]_net_1\, CLK => lclk_c, Q => - \haddr[28]\); - - \AddressSave_RNO[23]\ : NOR2B - port map(A => N_377, B => rstn, Y => - \AddressSave_RNO[23]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m49 : AX1E - port map(A => \haddr[10]\, B => BoundaryPhase_0_sqmuxa, C - => \haddr[11]\, Y => N_50_0); - - un1_AddressSave_0_sqmuxa_1_m35 : NOR3C - port map(A => \haddr[24]\, B => N_32_0, C => \haddr[25]\, Y - => N_36); - - \Address_RNO_0[3]\ : MX2C - port map(A => \AddressSave[3]_net_1\, B => N_253, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_AddressSave_0_sqmuxa_1_m52 : AX1E - port map(A => \haddr[14]\, B => N_15_0, C => \haddr[15]\, Y - => N_53_0); - - EarlyPhase : DFN1 - port map(D => \EarlyPhase_RNO\, CLK => lclk_c, Q => - \EarlyPhase\); - - \Address_RNO_1[31]\ : MX2C - port map(A => N_1048, B => N_60_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_281); - - \Address_RNIL8G2[4]\ : NOR2B - port map(A => \haddr[4]\, B => \haddr[5]\, Y => - BoundaryPhase_0_sqmuxa_8_1); - - \AddressSave_RNO[4]\ : NOR2B - port map(A => N_358, B => rstn, Y => - \AddressSave_RNO[4]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m18 : XNOR2 - port map(A => N_18_0, B => \haddr[16]\, Y => N_19_0); - - \Address_RNO_0[4]\ : MX2C - port map(A => \AddressSave[4]_net_1\, B => N_254, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[4]\); - - \Address_RNO_0[5]\ : MX2C - port map(A => \AddressSave[5]_net_1\, B => N_255, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[5]\); - - \AHBOut.hsize[0]\ : DFN1 - port map(D => \hsize_RNO[0]\, CLK => lclk_c, Q => - \hsize[0]\); - - \Address_RNO_0[17]\ : MX2C - port map(A => \AddressSave[17]_net_1\, B => N_267, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[17]\); - - \AddressSave_RNO_1[2]\ : MX2A - port map(A => N_1019, B => \haddr[2]\, S => - \AddressPhase_0\, Y => \AddressSave_4[2]\); - - ReAddrPhase_RNO : NOR2B - port map(A => N_349, B => rstn, Y => \ReAddrPhase_RNO\); - - \AddressSave_RNO_1[17]\ : MX2A - port map(A => N_1034, B => \haddr[17]\, S => \AddressPhase\, - Y => \AddressSave_4[17]\); - - \Address_RNO_1[27]\ : MX2C - port map(A => N_1044, B => N_56_0_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_277); - - un1_AddressSave_0_sqmuxa_1_m45 : XNOR2 - port map(A => N_6_0, B => \haddr[6]\, Y => N_46); - - \Address_RNO[19]\ : NOR2A - port map(A => rstn, B => \Address_9[19]\, Y => - \Address_RNO[19]_net_1\); - - \AddressSave_RNO_0[16]\ : MX2 - port map(A => \AddressSave[16]_net_1\, B => - \AddressSave_4[16]\, S => hsize_0_sqmuxa_0, Y => N_370); - - \Address_RNO_1[17]\ : MX2C - port map(A => N_1034, B => N_21_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_267); - - \AHBOut.hburst[0]\ : DFN1E0 - port map(D => \hburst_11[0]\, CLK => lclk_c, E => - \DataPhase_RNI2ITCNO\, Q => hburst(0)); - - \AddressSave[9]\ : DFN1 - port map(D => \AddressSave_RNO[9]_net_1\, CLK => lclk_c, Q - => \AddressSave[9]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m40 : NOR3C - port map(A => \haddr[28]\, B => N_39, C => \haddr[29]\, Y - => N_41); - - \AddressSave_RNO_1[29]\ : MX2A - port map(A => N_1046, B => \haddr[29]\, S => \AddressPhase\, - Y => \AddressSave_4[29]\); - - \AddressSave_RNO[2]\ : NOR2B - port map(A => N_356, B => rstn, Y => - \AddressSave_RNO[2]_net_1\); - - \Address_RNO[13]\ : NOR2A - port map(A => rstn, B => \Address_9[13]\, Y => - \Address_RNO[13]_net_1\); - - \Address_RNO_0[14]\ : MX2C - port map(A => \AddressSave[14]_net_1\, B => N_264, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[14]\); - - \Address[14]\ : DFN1 - port map(D => \Address_RNO[14]_net_1\, CLK => lclk_c, Q => - \haddr[14]\); - - \AddressSave[29]\ : DFN1 - port map(D => \AddressSave_RNO[29]_net_1\, CLK => lclk_c, Q - => \AddressSave[29]_net_1\); - - \Address_RNO_0[15]\ : MX2C - port map(A => \AddressSave[15]_net_1\, B => N_265, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[15]\); - - \Address_RNO_1[24]\ : MX2C - port map(A => N_1041, B => N_33_0_i, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_274); - - \AddressSave_RNO_0[1]\ : MX2 - port map(A => \AddressSave[1]_net_1\, B => - \AddressSave_4[1]\, S => hsize_0_sqmuxa, Y => N_355); - - \Address_RNO_1[25]\ : MX2C - port map(A => N_1042, B => N_35_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_275); - - \Address_RNO[14]\ : NOR2A - port map(A => rstn, B => \Address_9[14]\, Y => - \Address_RNO[14]_net_1\); - - AddressPhase_0_RNI040D1 : OR2B - port map(A => \AddressPhase_0\, B => iosn_1(93), Y => - AddressSave_0_sqmuxa); - - \Address_RNO_1[14]\ : MX2C - port map(A => N_1031, B => N_16_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_264); - - ReAddrPhase_RNIT5L9IO : OR2A - port map(A => AddressPhase_1_sqmuxa_0, B => hgrant(3), Y - => AddressPhase_1_sqmuxa); - - \Address_RNO_1[15]\ : MX2C - port map(A => N_1032, B => N_53_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_265); - - \AddressSave[11]\ : DFN1 - port map(D => \AddressSave_RNO[11]_net_1\, CLK => lclk_c, Q - => \AddressSave[11]_net_1\); - - \AddressSave_RNO_1[25]\ : MX2A - port map(A => N_1042, B => \haddr[25]\, S => \AddressPhase\, - Y => \AddressSave_4[25]\); - - \AddressSave_RNO_1[21]\ : MX2A - port map(A => N_1038, B => \haddr[21]\, S => \AddressPhase\, - Y => \AddressSave_4[21]\); - - ActivePhase_RNILH0E : OR3B - port map(A => un7_dmain(66), B => \ActivePhase\, C => - N_1081, Y => un75_ahbinhgrantx); - - \Address[24]\ : DFN1 - port map(D => \Address_RNO[24]_net_1\, CLK => lclk_c, Q => - \haddr[24]\); - - \Address_RNO_0[22]\ : MX2C - port map(A => \AddressSave[22]_net_1\, B => N_272, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[22]\); - - ReAddrPhase_RNI4EHJ1 : OR2B - port map(A => \Grant_0\, B => iosn_0(93), Y => \Grant_1_0\); - - \AddressSave[1]\ : DFN1 - port map(D => \AddressSave_RNO[1]_net_1\, CLK => lclk_c, Q - => \AddressSave[1]_net_1\); - - \AHBOut.hwrite_RNO\ : NOR2B - port map(A => N_341, B => rstn, Y => hwrite_RNO); - - VCC_i : VCC - port map(Y => \VCC\); - - \Address_RNO_0[31]\ : MX2C - port map(A => \AddressSave[31]_net_1\, B => N_281, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[31]\); - - AddressPhase_RNI4GHN6H1 : AOI1B - port map(A => htrans_4_sqmuxa_1, B => htrans_1_sqmuxa, C - => iosn_1(93), Y => BoundaryPhase_1_sqmuxa_1); - - \AddressSave[25]\ : DFN1 - port map(D => \AddressSave_RNO[25]_net_1\, CLK => lclk_c, Q - => \AddressSave[25]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m27 : AX1E - port map(A => \haddr[20]\, B => N_26_0, C => \haddr[21]\, Y - => N_28_0); - - \AddressSave[22]\ : DFN1 - port map(D => \AddressSave_RNO[22]_net_1\, CLK => lclk_c, Q - => \AddressSave[22]_net_1\); - - ReAddrPhase_RNIMO8B : NOR2A - port map(A => N_1081, B => un23_ahbinhgrantx, Y => - \Grant_0\); - - \AddressSave_RNO_0[19]\ : MX2 - port map(A => \AddressSave[19]_net_1\, B => - \AddressSave_4[19]\, S => hsize_0_sqmuxa_0, Y => N_373); - - ActivePhase_RNII2SHIO : OR3A - port map(A => N_1081, B => \ActivePhase\, C => hgrant(3), Y - => un5_ahbinhgrantx); - - \AddressSave_RNO_0[31]\ : MX2 - port map(A => \AddressSave[31]_net_1\, B => - \AddressSave_4[31]\, S => hsize_0_sqmuxa, Y => N_385); - - \AddressSave_RNO[1]\ : NOR2B - port map(A => N_355, B => rstn, Y => - \AddressSave_RNO[1]_net_1\); - - \Address[8]\ : DFN1 - port map(D => \Address_RNO[8]_net_1\, CLK => lclk_c, Q => - \haddr[8]\); - - \Address_RNO_0[1]\ : MX2C - port map(A => \AddressSave[1]_net_1\, B => N_251, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[1]\); - - un1_AddressSave_0_sqmuxa_1_m21 : NOR3C - port map(A => \haddr[16]\, B => N_18_0, C => \haddr[17]\, Y - => N_22_0); - - BoundaryPhase : DFN1 - port map(D => N_422_i, CLK => lclk_c, Q => \BoundaryPhase\); - - \AddressSave_RNO_0[7]\ : MX2 - port map(A => \AddressSave[7]_net_1\, B => - \AddressSave_4[7]\, S => hsize_0_sqmuxa_0, Y => N_361); - - \AddressSave_RNO[24]\ : NOR2B - port map(A => N_378, B => rstn, Y => N_26); - - \DMAOut.Grant_m10_i_a5\ : OR2 - port map(A => hmaster_0(1), B => arb_1, Y => Grant_N_13); - - \AHBOut.htrans_RNO_0[0]\ : OR3C - port map(A => rstn, B => un78_ahbinhgrantx, C => - hburst_2_sqmuxa_1, Y => un1_dmain_15); - - \Address_RNIH8G2[3]\ : OR2B - port map(A => \haddr[3]\, B => \haddr[2]\, Y => - BoundaryPhase_0_sqmuxa_6_0); - - \AddressSave_RNO_1[9]\ : MX2A - port map(A => N_1026, B => \haddr[9]\, S => - \AddressPhase_0\, Y => \AddressSave_4[9]\); - - \AHBOut.hwrite_RNO_3\ : NOR2B - port map(A => \WriteAcc\, B => un37_ahbinhgrantx, Y => - WriteAcc_m_0); - - \Address_RNO[6]\ : NOR2A - port map(A => rstn, B => \Address_9[6]\, Y => - \Address_RNO[6]_net_1\); - - \IdlePhase\ : DFN1 - port map(D => \IdlePhase_RNO\, CLK => lclk_c, Q => - IdlePhase_net_1); - - AddressPhase_0_RNII6SUJO_1 : OA1A - port map(A => un5_ahbinhgrantx, B => \AddressPhase_0\, C - => iosn_0(93), Y => hsize_0_sqmuxa_0); - - \AddressSave_RNO_0[15]\ : MX2 - port map(A => \AddressSave[15]_net_1\, B => - \AddressSave_4[15]\, S => hsize_0_sqmuxa, Y => N_369); - - \AddressSave_RNO_0[11]\ : MX2 - port map(A => \AddressSave[11]_net_1\, B => - \AddressSave_4[11]\, S => hsize_0_sqmuxa_0, Y => N_365); - - ReAddrPhase : DFN1 - port map(D => \ReAddrPhase_RNO\, CLK => lclk_c, Q => - \ReAddrPhase\); - - \Address_RNO[28]\ : NOR2A - port map(A => rstn, B => \Address_9[28]\, Y => - \Address_RNO[28]_net_1\); - - \Address_RNO[11]\ : NOR2A - port map(A => rstn, B => \Address_9[11]\, Y => - \Address_RNO[11]_net_1\); - - \Address_RNO_0[12]\ : MX2C - port map(A => \AddressSave[12]_net_1\, B => N_262, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[12]\); - - \AddressSave_RNO_1[5]\ : MX2A - port map(A => N_1022, B => \haddr[5]\, S => - \AddressPhase_0\, Y => \AddressSave_4[5]\); - - DataPhase_RNO_0 : OR2A - port map(A => dataphase10, B => hresp(0), Y => - IdlePhase_1_sqmuxa); - - ReAddrPhase_RNIBST1_0 : NOR2A - port map(A => \ReAddrPhase\, B => \ReDataPhase\, Y => - AddressPhase_1_sqmuxa_0); - - \Address_RNO_1[22]\ : MX2C - port map(A => N_1039, B => N_30_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_272); - - ActivePhase_RNIEP9I1 : NOR2 - port map(A => un84_ahbinhgrantx_0, B => un77_ahbinhgrantx, - Y => un84_ahbinhgrantx); - - \Address_RNO[17]\ : NOR2A - port map(A => rstn, B => \Address_9[17]\, Y => - \Address_RNO[17]_net_1\); - - \AddressSave_RNO_0[0]\ : MX2 - port map(A => \AddressSave[0]_net_1\, B => - \AddressSave_4[0]\, S => hsize_0_sqmuxa, Y => N_354); - - \AddressSave_RNO[31]\ : NOR2B - port map(A => N_385, B => rstn, Y => N_28); - - \Address_RNO[5]\ : NOR2A - port map(A => rstn, B => \Address_9[5]\, Y => - \Address_RNO[5]_net_1\); - - \AddressSave[17]\ : DFN1 - port map(D => \AddressSave_RNO[17]_net_1\, CLK => lclk_c, Q - => \AddressSave[17]_net_1\); - - \Address_RNO_1[12]\ : MX2C - port map(A => N_1029, B => N_51_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_262); - - \AddressSave_RNO_1[27]\ : MX2A - port map(A => N_1044, B => \haddr[27]\, S => \AddressPhase\, - Y => \AddressSave_4[27]\); - - \AddressSave_RNO[15]\ : NOR2B - port map(A => N_369, B => rstn, Y => - \AddressSave_RNO[15]_net_1\); - - \AddressSave[4]\ : DFN1 - port map(D => \AddressSave_RNO[4]_net_1\, CLK => lclk_c, Q - => \AddressSave[4]_net_1\); - - \AddressSave[14]\ : DFN1 - port map(D => \AddressSave_RNO[14]_net_1\, CLK => lclk_c, Q - => \AddressSave[14]_net_1\); - - \Address_RNO[0]\ : NOR2A - port map(A => rstn, B => \Address_9[0]\, Y => - \Address_RNO[0]_net_1\); - - ActivePhase : DFN1 - port map(D => \ActivePhase_RNO\, CLK => lclk_c, Q => - \ActivePhase\); - - ReAddrPhase_RNO_0 : OA1A - port map(A => iosn_2(93), B => AddressPhase_1_sqmuxa, C => - \ReAddrPhase\, Y => N_349); - - \AddressSave[7]\ : DFN1 - port map(D => \AddressSave_RNO[7]_net_1\, CLK => lclk_c, Q - => \AddressSave[7]_net_1\); - - \DMAOut.Grant_m10_i_a5_0\ : OR2B - port map(A => Grant_m10_i_a5_0_0, B => arb_1, Y => - Grant_N_15); - - \Address_RNO_0[2]\ : MX2C - port map(A => \AddressSave[2]_net_1\, B => N_252, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[2]\); - - \AddressSave_RNO_0[22]\ : MX2 - port map(A => \AddressSave[22]_net_1\, B => - \AddressSave_4[22]\, S => hsize_0_sqmuxa, Y => N_376); - - un1_AddressSave_0_sqmuxa_1_m14 : NOR3C - port map(A => \haddr[12]\, B => N_13_0, C => \haddr[13]\, Y - => N_15_0); - - \AHBOut.hburst_2_sqmuxa_1\ : NOR2A - port map(A => iosn_2(93), B => hgrant(3), Y => - hburst_2_sqmuxa_1); - - \Address_RNO[3]\ : NOR2A - port map(A => rstn, B => \Address_9[3]\, Y => - \Address_RNO[3]_net_1\); - - EarlyPhase_RNIPTR9 : OR2 - port map(A => un23_ahbinhgrantx, B => \EarlyPhase\, Y => - un37_ahbinhgrantx); - - \Address[3]\ : DFN1 - port map(D => \Address_RNO[3]_net_1\, CLK => lclk_c, Q => - \haddr[3]\); - - \AddressSave_RNO_1[6]\ : MX2A - port map(A => N_1023, B => \haddr[6]\, S => - \AddressPhase_0\, Y => \AddressSave_4[6]\); - - ActivePhase_RNO_1 : NOR3 - port map(A => un7_addressphase_0, B => un23_ahbinhgrantx, C - => un7_dmain(66), Y => un7_addressphase); - - un1_AddressSave_0_sqmuxa_1_m32 : XNOR2 - port map(A => N_32_0, B => \haddr[24]\, Y => N_33_0_i); - - \AddressSave_RNO_0[20]\ : MX2 - port map(A => \AddressSave[20]_net_1\, B => - \AddressSave_4[20]\, S => hsize_0_sqmuxa_0, Y => N_374); - - \AddressSave_RNO[0]\ : NOR2B - port map(A => N_354, B => rstn, Y => - \AddressSave_RNO[0]_net_1\); - - \Address_RNO_1[2]\ : MX2C - port map(A => N_1019, B => N_4, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_252); - - \Address_RNO[30]\ : NOR2A - port map(A => rstn, B => \Address_9[30]\, Y => - \Address_RNO[30]_net_1\); - - \AddressSave[0]\ : DFN1 - port map(D => \AddressSave_RNO[0]_net_1\, CLK => lclk_c, Q - => \AddressSave[0]_net_1\); - - AddressPhase : DFN1 - port map(D => \AddressPhase_RNIGMGKAH1\, CLK => lclk_c, Q - => \AddressPhase\); - - \AddressSave_RNO_0[5]\ : MX2 - port map(A => \AddressSave[5]_net_1\, B => - \AddressSave_4[5]\, S => hsize_0_sqmuxa_0, Y => N_359); - - \AddressSave_RNO[3]\ : NOR2B - port map(A => N_357, B => rstn, Y => - \AddressSave_RNO[3]_net_1\); - - ActivePhase_RNIE4351_0 : NOR2 - port map(A => un75_ahbinhgrantx, B => un45_ahbinhgrantx, Y - => un78_ahbinhgrantx); - - IdlePhase_RNI2FRO : NOR2A - port map(A => \hbusreq_i_3\, B => hmaster_0(1), Y => - Grant_m10_i_a5_1_0); - - \AddressSave_RNO[19]\ : NOR2B - port map(A => N_373, B => rstn, Y => - \AddressSave_RNO[19]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m42 : AX1A - port map(A => AddressSave_0_sqmuxa, B => \haddr[2]\, C => - \haddr[3]\, Y => N_43); - - \Address_RNO_0[6]\ : MX2C - port map(A => \AddressSave[6]_net_1\, B => N_256, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[6]\); - - AddressPhase_0_RNII6SUJO : OR3A - port map(A => iosn_0(93), B => \AddressPhase_0\, C => - un5_ahbinhgrantx, Y => BoundaryPhase_2_sqmuxa_i_0_0); - - \AddressSave_RNO_0[17]\ : MX2 - port map(A => \AddressSave[17]_net_1\, B => - \AddressSave_4[17]\, S => hsize_0_sqmuxa, Y => N_371); - - \Address[7]\ : DFN1 - port map(D => \Address_RNO[7]_net_1\, CLK => lclk_c, Q => - \haddr[7]\); - - un1_AddressSave_0_sqmuxa_1_m1 : XOR2 - port map(A => AddressSave_0_sqmuxa, B => \haddr[2]\, Y => - N_4); - - \Address_RNO_0[28]\ : MX2C - port map(A => \AddressSave[28]_net_1\, B => N_278, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[28]\); - - \AddressSave_RNO[27]\ : NOR2B - port map(A => N_381, B => rstn, Y => - \AddressSave_RNO[27]_net_1\); - - \AddressSave_RNO[12]\ : NOR2B - port map(A => N_366, B => rstn, Y => - \AddressSave_RNO[12]_net_1\); - - \AddressSave[26]\ : DFN1 - port map(D => \AddressSave_RNO[26]_net_1\, CLK => lclk_c, Q - => \AddressSave[26]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m54 : AX1E - port map(A => \haddr[22]\, B => N_29_0, C => \haddr[23]\, Y - => N_55_0_i); - - un1_AddressSave_0_sqmuxa_1_m53 : XNOR2 - port map(A => N_26_0, B => \haddr[20]\, Y => N_54_0); - - \DMAOut.Ready\ : DFN1 - port map(D => Data_0_sqmuxa, CLK => lclk_c, Q => Ready); - - \AddressSave[18]\ : DFN1 - port map(D => \AddressSave_RNO[18]_net_1\, CLK => lclk_c, Q - => \AddressSave[18]_net_1\); - - \AddressSave_RNO[30]\ : NOR2B - port map(A => N_384, B => rstn, Y => - \AddressSave_RNO[30]_net_1\); - - \AddressSave_RNO[13]\ : NOR2B - port map(A => N_367, B => rstn, Y => - \AddressSave_RNO[13]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m29 : XNOR2 - port map(A => N_29_0, B => \haddr[22]\, Y => N_30_0); - - IdlePhase_RNIKJKM : OR2 - port map(A => N_247, B => IdlePhase_net_1, Y => - \hbusreq_i_3\); - - \Address_RNIT8G2[9]\ : NOR2B - port map(A => \haddr[9]\, B => \haddr[8]\, Y => - BoundaryPhase_0_sqmuxa_0); - - un1_AddressSave_0_sqmuxa_1_m38 : NOR3C - port map(A => \haddr[26]\, B => N_36, C => \haddr[27]\, Y - => N_39); - - \Address_RNO_0[26]\ : MX2C - port map(A => \AddressSave[26]_net_1\, B => N_276, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[26]\); - - WriteAcc : DFN1 - port map(D => \WriteAcc_RNO\, CLK => lclk_c, Q => - \WriteAcc\); - - EarlyPhase_RNO_0 : MX2 - port map(A => hgrant(3), B => \EarlyPhase\, S => - un1_ahbin_3, Y => N_351); - - \AddressSave_RNO_0[3]\ : MX2 - port map(A => \AddressSave[3]_net_1\, B => - \AddressSave_4[3]\, S => hsize_0_sqmuxa_0, Y => N_357); - - ActivePhase_RNICD7U : NOR2A - port map(A => hwrite_1_sqmuxa, B => time_select_0, Y => - \hburst_11_i_a2_i_a3_0[1]\); - - \Address_RNO_0[29]\ : MX2C - port map(A => \AddressSave[29]_net_1\, B => N_279, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[29]\); - - un1_AddressSave_0_sqmuxa_1_m56 : XNOR2 - port map(A => N_39, B => \haddr[28]\, Y => N_57_0); - - un1_AddressSave_0_sqmuxa_1_m25 : NOR3C - port map(A => \haddr[18]\, B => N_22_0, C => \haddr[19]\, Y - => N_26_0); - - un1_AddressSave_0_sqmuxa_1_m5 : NOR2A - port map(A => \haddr[5]\, B => N_5_0, Y => N_6_0); - - un1_AddressSave_0_sqmuxa_1_m48 : AX1E - port map(A => \haddr[6]\, B => N_6_0, C => \haddr[7]\, Y - => N_49_0); - - \Address_RNIEH05[7]\ : NOR3C - port map(A => \haddr[7]\, B => \haddr[6]\, C => - BoundaryPhase_0_sqmuxa_8_1, Y => - BoundaryPhase_0_sqmuxa_8_2); - - un1_AddressSave_0_sqmuxa_1_m20 : AX1E - port map(A => \haddr[16]\, B => N_18_0, C => \haddr[17]\, Y - => N_21_0); - - EarlyPhase_RNO_2 : AOI1B - port map(A => un1_ActivePhase, B => hgrant(3), C => - iosn_0(93), Y => un1_ahbin_3_0); - - \AHBOut.htrans_RNO_1[0]\ : OR2 - port map(A => BoundaryPhase_0_sqmuxa, B => \BoundaryPhase\, - Y => un28_ahbinhgrantx_i_0); - - \Address_RNO[22]\ : NOR2A - port map(A => rstn, B => \Address_9[22]\, Y => - \Address_RNO[22]_net_1\); - - \Address[9]\ : DFN1 - port map(D => \Address_RNO[9]_net_1\, CLK => lclk_c, Q => - \haddr[9]\); - - DataPhase_RNO : AOI1B - port map(A => IdlePhase_1_sqmuxa, B => AddressSave_0_sqmuxa, - C => rstn, Y => N_423_i); - - \Address_RNO[18]\ : NOR2A - port map(A => rstn, B => \Address_9[18]\, Y => - \Address_RNO[18]_net_1\); - - ReDataPhase_RNIQF9GJO : OR3B - port map(A => \ReDataPhase\, B => iosn_0(93), C => - hgrant(3), Y => ReDataPhase_0_sqmuxa_i_0_0); - - DataPhase_RNIC3IU1_0 : NOR2 - port map(A => data2, B => hresp(0), Y => OKAY); - - \Address_RNO_0[18]\ : MX2C - port map(A => \AddressSave[18]_net_1\, B => N_268, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[18]\); - - \AddressSave_RNO_0[28]\ : MX2 - port map(A => \AddressSave[28]_net_1\, B => - \AddressSave_4[28]\, S => hsize_0_sqmuxa_0, Y => N_382); - - GND_i_0 : GND - port map(Y => GND_0); - - AddressPhase_RNIPJ40KO : OA1A - port map(A => un5_ahbinhgrantx, B => \AddressPhase\, C => - iosn_1(93), Y => hsize_0_sqmuxa); - - \Address_RNO[7]\ : NOR2A - port map(A => rstn, B => \Address_9[7]\, Y => - \Address_RNO[7]_net_1\); - - \Address_RNO_1[28]\ : MX2C - port map(A => N_1045, B => N_57_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_278); - - \Address_RNO_0[7]\ : MX2C - port map(A => \AddressSave[7]_net_1\, B => N_257, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[7]\); - - SingleAcc : DFN1 - port map(D => \SingleAcc_RNO\, CLK => lclk_c, Q => - \SingleAcc\); - - \AddressSave_RNO_0[4]\ : MX2 - port map(A => \AddressSave[4]_net_1\, B => - \AddressSave_4[4]\, S => hsize_0_sqmuxa, Y => N_358); - - \Address_RNO_1[18]\ : MX2C - port map(A => N_1035, B => N_23_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_268); - - \Address[6]\ : DFN1 - port map(D => \Address_RNO[6]_net_1\, CLK => lclk_c, Q => - \haddr[6]\); - - \AddressSave_RNO_1[30]\ : MX2A - port map(A => N_1047, B => \haddr[30]\, S => \AddressPhase\, - Y => \AddressSave_4[30]\); - - \AddressSave_RNO[9]\ : NOR2B - port map(A => N_363, B => rstn, Y => - \AddressSave_RNO[9]_net_1\); - - EarlyPhase_RNO_3 : OAI1 - port map(A => N_1081, B => un7_dmain(66), C => - \ActivePhase\, Y => un1_ActivePhase); - - \AHBMaster.un84_ahbinhgrantx_0\ : OR2A - port map(A => N_1081, B => un7_dmain(66), Y => - un84_ahbinhgrantx_0); - - \Address_RNO_0[16]\ : MX2C - port map(A => \AddressSave[16]_net_1\, B => N_266, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[16]\); - - \AddressSave_RNO_1[0]\ : MX2 - port map(A => Address_RNIP8BS(0), B => \haddr[0]\, S => - \AddressPhase\, Y => \AddressSave_4[0]\); - - \Address_RNO[8]\ : NOR2A - port map(A => rstn, B => \Address_9[8]\, Y => - \Address_RNO[8]_net_1\); - - \AddressSave_RNO_0[24]\ : MX2 - port map(A => \AddressSave[24]_net_1\, B => - \AddressSave_4[24]\, S => hsize_0_sqmuxa, Y => N_378); - - \AddressSave[21]\ : DFN1 - port map(D => \AddressSave_RNO[21]_net_1\, CLK => lclk_c, Q - => \AddressSave[21]_net_1\); - - \Address_RNO_1[26]\ : MX2C - port map(A => N_1043, B => N_37_i, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_276); - - \AddressSave_RNO_0[9]\ : MX2 - port map(A => \AddressSave[9]_net_1\, B => - \AddressSave_4[9]\, S => hsize_0_sqmuxa_0, Y => N_363); - - ActivePhase_RNISIVCLO : OA1 - port map(A => un78_ahbinhgrantx, B => hwrite_0_sqmuxa_1, C - => hburst_2_sqmuxa_1, Y => hburst_2_sqmuxa); - - un1_AddressSave_0_sqmuxa_1_m17 : NOR3C - port map(A => \haddr[14]\, B => N_15_0, C => \haddr[15]\, Y - => N_18_0); - - \AHBOut.htrans_RNO_2[0]\ : NOR2B - port map(A => BoundaryPhase_1_sqmuxa_1, B => rstn, Y => - \htrans_RNO_2[0]\); - - \AddressSave_RNO_0[23]\ : MX2 - port map(A => \AddressSave[23]_net_1\, B => - \AddressSave_4[23]\, S => hsize_0_sqmuxa, Y => N_377); - - SingleAcc_RNO_0 : MX2 - port map(A => \SingleAcc\, B => un84_ahbinhgrantx, S => - hwrite_2_sqmuxa, Y => N_346); - - \Address_RNO_1[16]\ : MX2C - port map(A => N_1033, B => N_19_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_266); - - \Address_RNO_0[19]\ : MX2C - port map(A => \AddressSave[19]_net_1\, B => N_269, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[19]\); - - \Address[11]\ : DFN1 - port map(D => \Address_RNO[11]_net_1\, CLK => lclk_c, Q => - \haddr[11]\); - - \AddressSave[31]\ : DFN1 - port map(D => N_28, CLK => lclk_c, Q => - \AddressSave[31]_net_1\); - - \Address[31]\ : DFN1 - port map(D => \Address_RNO[31]_net_1\, CLK => lclk_c, Q => - \haddr[31]\); - - \Address_RNO_1[29]\ : MX2C - port map(A => N_1046, B => N_58_0_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_279); - - \AddressSave_RNO_0[2]\ : MX2 - port map(A => \AddressSave[2]_net_1\, B => - \AddressSave_4[2]\, S => hsize_0_sqmuxa_0, Y => N_356); - - \AddressSave[13]\ : DFN1 - port map(D => \AddressSave_RNO[13]_net_1\, CLK => lclk_c, Q - => \AddressSave[13]_net_1\); - - ReAddrPhase_RNIBH4F : NOR3 - port map(A => N_1081, B => un7_dmain(66), C => - un23_ahbinhgrantx, Y => N_247); - - \Address_RNO_1[19]\ : MX2C - port map(A => N_1036, B => N_25_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_269); - - \AHBOut.hwrite_RNO_1\ : AO1B - port map(A => N_1082, B => hwrite_2_sqmuxa, C => WriteAcc_m, - Y => hwrite_8); - - \Address_RNO[2]\ : NOR2A - port map(A => rstn, B => \Address_9[2]\, Y => - \Address_RNO[2]_net_1\); - - \Address_RNO_1[5]\ : MX2C - port map(A => N_1022, B => N_45, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_255); - - \Address_RNO[4]\ : NOR2A - port map(A => rstn, B => \Address_9[4]\, Y => - \Address_RNO[4]_net_1\); - - \AddressSave_RNO[14]\ : NOR2B - port map(A => N_368, B => rstn, Y => - \AddressSave_RNO[14]_net_1\); - - EarlyPhase_RNO : NOR2B - port map(A => N_351, B => rstn, Y => \EarlyPhase_RNO\); - - \Address_RNO[25]\ : NOR2A - port map(A => rstn, B => \Address_9[25]\, Y => - \Address_RNO[25]_net_1\); - - \Address[21]\ : DFN1 - port map(D => \Address_RNO[21]_net_1\, CLK => lclk_c, Q => - \haddr[21]\); - - \AddressSave_RNO[28]\ : NOR2B - port map(A => N_382, B => rstn, Y => - \AddressSave_RNO[28]_net_1\); - - \AddressSave_RNO_1[12]\ : MX2A - port map(A => N_1029, B => \haddr[12]\, S => - \AddressPhase_0\, Y => \AddressSave_4[12]\); - - ActivePhase_RNI68JFKO : NOR3C - port map(A => rstn, B => \hburst_11_i_a2_i_a3_0[1]\, C => - hburst_2_sqmuxa_1, Y => N_30); - - ReDataPhase_RNIHRIE8H1 : AOI1 - port map(A => un1_AddressPhase_0_sqmuxa_1_0, B => - AddressPhase_1_sqmuxa, C => \un1_dmain_20_0\, Y => - un1_dmain_20); - - \AddressSave_RNO_1[10]\ : MX2A - port map(A => N_1027, B => \haddr[10]\, S => \AddressPhase\, - Y => \AddressSave_4[10]\); - - ReDataPhase_RNO : NOR3C - port map(A => rstn, B => \ReDataPhase\, C => - ReDataPhase_0_sqmuxa_i_0_0, Y => \ReDataPhase_RNO\); - - \AHBOut.hsize_RNO[0]\ : NOR3B - port map(A => rstn, B => \hsize[0]\, C => hsize_0_sqmuxa_0, - Y => \hsize_RNO[0]\); - - \AddressSave_RNO[21]\ : NOR2B - port map(A => N_375, B => rstn, Y => - \AddressSave_RNO[21]_net_1\); - - IdlePhase_RNO_0 : MX2 - port map(A => dataphase10, B => IdlePhase_net_1, S => - un1_redataphase21, Y => N_350); - - EarlyPhase_RNI0A8J2 : OR3A - port map(A => un46_ahbinhgrantx, B => - AddressPhase_2_sqmuxa_0, C => un84_ahbinhgrantx, Y => - un1_AddressPhase_0_sqmuxa_1_0_0_tz); - - un1_AddressSave_0_sqmuxa_1_m57 : AX1E - port map(A => \haddr[28]\, B => N_39, C => \haddr[29]\, Y - => N_58_0_i); - - \Address[17]\ : DFN1 - port map(D => \Address_RNO[17]_net_1\, CLK => lclk_c, Q => - \haddr[17]\); - - \AddressSave[10]\ : DFN1 - port map(D => \AddressSave_RNO[10]_net_1\, CLK => lclk_c, Q - => \AddressSave[10]_net_1\); - - EarlyPhase_RNIPI2N_0 : AO1 - port map(A => un7_dmain(66), B => N_1081, C => - un37_ahbinhgrantx, Y => un45_ahbinhgrantx); - - \AddressSave_RNO_0[26]\ : MX2 - port map(A => \AddressSave[26]_net_1\, B => - \AddressSave_4[26]\, S => hsize_0_sqmuxa, Y => N_380); - - AddressPhase_0_RNII6SUJO_0 : OR3A - port map(A => iosn_0(93), B => \AddressPhase_0\, C => - un5_ahbinhgrantx, Y => BoundaryPhase_2_sqmuxa_i_0); - - IdlePhase_RNIII7AVI : OR2A - port map(A => Grant_1_2, B => nhmaster_1_i(0), Y => Grant); - - \Address_RNO_1[1]\ : MX2 - port map(A => N_1018, B => \haddr[1]\, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_251); - - \Address_RNO_1[6]\ : MX2C - port map(A => N_1023, B => N_46, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_256); - - un1_AddressSave_0_sqmuxa_1_m51 : AX1E - port map(A => \haddr[12]\, B => N_13_0, C => \haddr[13]\, Y - => N_52_0); - - un1_AddressSave_0_sqmuxa_1_m34 : AX1E - port map(A => \haddr[24]\, B => N_32_0, C => \haddr[25]\, Y - => N_35_i); - - \Address[27]\ : DFN1 - port map(D => \Address_RNO[27]_net_1\, CLK => lclk_c, Q => - \haddr[27]\); - - \AddressSave[3]\ : DFN1 - port map(D => \AddressSave_RNO[3]_net_1\, CLK => lclk_c, Q - => \AddressSave[3]_net_1\); - - DataPhase : DFN1 - port map(D => N_423_i, CLK => lclk_c, Q => \DataPhase\); - - \AddressSave[2]\ : DFN1 - port map(D => \AddressSave_RNO[2]_net_1\, CLK => lclk_c, Q - => \AddressSave[2]_net_1\); - - \AddressSave[27]\ : DFN1 - port map(D => \AddressSave_RNO[27]_net_1\, CLK => lclk_c, Q - => \AddressSave[27]_net_1\); - - AddressPhase_0 : DFN1 - port map(D => \AddressPhase_RNIGMGKAH1\, CLK => lclk_c, Q - => \AddressPhase_0\); - - \Address_RNO_0[20]\ : MX2C - port map(A => \AddressSave[20]_net_1\, B => N_270, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[20]\); - - \AddressSave_RNO[8]\ : NOR2B - port map(A => N_362, B => rstn, Y => - \AddressSave_RNO[8]_net_1\); - - \AddressSave[5]\ : DFN1 - port map(D => \AddressSave_RNO[5]_net_1\, CLK => lclk_c, Q - => \AddressSave[5]_net_1\); - - EarlyPhase_RNIPTR9_0 : NOR2A - port map(A => \EarlyPhase\, B => un23_ahbinhgrantx, Y => - AddressPhase_2_sqmuxa_0); - - \AddressSave[24]\ : DFN1 - port map(D => N_26, CLK => lclk_c, Q => - \AddressSave[24]_net_1\); - - \AddressSave_RNO_1[8]\ : MX2A - port map(A => N_1025, B => \haddr[8]\, S => \AddressPhase\, - Y => \AddressSave_4[8]\); - - \Address_RNO[31]\ : NOR2A - port map(A => rstn, B => \Address_9[31]\, Y => - \Address_RNO[31]_net_1\); - - \Address_RNIHCGF1[3]\ : NOR2 - port map(A => BoundaryPhase_0_sqmuxa_6_0, B => - AddressSave_0_sqmuxa, Y => BoundaryPhase_0_sqmuxa_6); - - \AHBOut.htrans_RNO[0]\ : MX2C - port map(A => un1_dmain_15, B => un28_ahbinhgrantx_i_0, S - => \htrans_RNO_2[0]\, Y => \htrans_12[0]\); - - un1_AddressSave_0_sqmuxa_1_m44 : XOR2 - port map(A => N_5_0, B => \haddr[5]\, Y => N_45); - - un1_AddressSave_0_sqmuxa_1_m43 : XNOR2 - port map(A => BoundaryPhase_0_sqmuxa_6, B => \haddr[4]\, Y - => N_44); - - \Address_RNO[12]\ : NOR2A - port map(A => rstn, B => \Address_9[12]\, Y => - \Address_RNO[12]_net_1\); - - DataPhase_RNIC3IU1 : AOI1 - port map(A => \DataPhase\, B => hresp(0), C => iosn_2(93), - Y => un1_redataphase21); - - un1_AddressSave_0_sqmuxa_1_m36 : XNOR2 - port map(A => N_36, B => \haddr[26]\, Y => N_37_i); - - DataPhase_RNI543F1_0 : NOR2A - port map(A => \DataPhase\, B => iosn_2(93), Y => - dataphase10); - - \Address_RNO_0[23]\ : MX2C - port map(A => \AddressSave[23]_net_1\, B => N_273, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[23]\); - - un1_AddressSave_0_sqmuxa_1_m22 : XNOR2 - port map(A => N_22_0, B => \haddr[18]\, Y => N_23_0); - - \AddressSave_RNO[6]\ : NOR2B - port map(A => N_360, B => rstn, Y => - \AddressSave_RNO[6]_net_1\); - - \AddressSave_RNO_0[29]\ : MX2 - port map(A => \AddressSave[29]_net_1\, B => - \AddressSave_4[29]\, S => hsize_0_sqmuxa, Y => N_383); - - \Address[1]\ : DFN1 - port map(D => \Address_RNO[1]_net_1\, CLK => lclk_c, Q => - \haddr[1]\); - - \AddressSave_RNO[20]\ : NOR2B - port map(A => N_374, B => rstn, Y => - \AddressSave_RNO[20]_net_1\); - - \AddressSave_RNO[17]\ : NOR2B - port map(A => N_371, B => rstn, Y => - \AddressSave_RNO[17]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m46 : AX1E - port map(A => BoundaryPhase_0_sqmuxa_6, B => - BoundaryPhase_0_sqmuxa_8_2, C => \haddr[8]\, Y => N_83_i); - - \AHBOut.hburst[1]\ : DFN1E0 - port map(D => N_30, CLK => lclk_c, E => - \DataPhase_RNI2ITCNO\, Q => hburst(1)); - - un1_AddressSave_0_sqmuxa_1_m4 : OR2B - port map(A => BoundaryPhase_0_sqmuxa_6, B => \haddr[4]\, Y - => N_5_0); - - \AddressSave_RNO_1[18]\ : MX2A - port map(A => N_1035, B => \haddr[18]\, S => - \AddressPhase_0\, Y => \AddressSave_4[18]\); - - \AddressSave_RNO_0[25]\ : MX2 - port map(A => \AddressSave[25]_net_1\, B => - \AddressSave_4[25]\, S => hsize_0_sqmuxa, Y => N_379); - - \AddressSave_RNO_0[21]\ : MX2 - port map(A => \AddressSave[21]_net_1\, B => - \AddressSave_4[21]\, S => hsize_0_sqmuxa, Y => N_375); - - \Address_RNO_0[10]\ : MX2C - port map(A => \AddressSave[10]_net_1\, B => N_260, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[10]\); - - \Address_RNO[20]\ : NOR2A - port map(A => rstn, B => \Address_9[20]\, Y => - \Address_RNO[20]_net_1\); - - ActivePhase_RNO_0 : AO1A - port map(A => un7_addressphase, B => \ActivePhase\, C => - hwrite_2_sqmuxa, Y => N_344); - - \AddressSave_RNO[26]\ : NOR2B - port map(A => N_380, B => rstn, Y => - \AddressSave_RNO[26]_net_1\); - - AddressPhase_RNIGMGKAH1 : AO1 - port map(A => \AddressPhase\, B => htrans_4_sqmuxa, C => - un1_dmain_20, Y => \AddressPhase_RNIGMGKAH1\); - - \Address_RNO_1[20]\ : MX2C - port map(A => Address_RNIJ4SP(20), B => N_54_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_270); - - \AddressSave[28]\ : DFN1 - port map(D => \AddressSave_RNO[28]_net_1\, CLK => lclk_c, Q - => \AddressSave[28]_net_1\); - - \AddressSave_RNO_1[4]\ : MX2A - port map(A => N_1021, B => \haddr[4]\, S => \AddressPhase\, - Y => \AddressSave_4[4]\); - - \Address_RNO_1[10]\ : MX2C - port map(A => N_1027, B => N_11_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_260); - - \AddressSave_RNO_1[22]\ : MX2A - port map(A => N_1039, B => \haddr[22]\, S => \AddressPhase\, - Y => \AddressSave_4[22]\); - - ReDataPhase : DFN1 - port map(D => \ReDataPhase_RNO\, CLK => lclk_c, Q => - \ReDataPhase\); - - \AHBOut.htrans[0]\ : DFN1E0 - port map(D => \htrans_12[0]\, CLK => lclk_c, E => - htrans_4_sqmuxa, Q => htrans(0)); - - un1_AddressSave_0_sqmuxa_1_m15 : XNOR2 - port map(A => N_15_0, B => \haddr[14]\, Y => N_16_0); - - \AddressSave_RNO_1[20]\ : MX2A - port map(A => Address_RNIJ4SP(20), B => \haddr[20]\, S => - \AddressPhase_0\, Y => \AddressSave_4[20]\); - - \AddressSave_RNO_1[14]\ : MX2A - port map(A => N_1031, B => \haddr[14]\, S => - \AddressPhase_0\, Y => \AddressSave_4[14]\); - - un1_AddressSave_0_sqmuxa_1_m8 : OR3C - port map(A => BoundaryPhase_0_sqmuxa_6, B => - BoundaryPhase_0_sqmuxa_8_2, C => \haddr[8]\, Y => N_9_0); - - un1_AddressSave_0_sqmuxa_1_m28 : NOR3C - port map(A => \haddr[20]\, B => N_26_0, C => \haddr[21]\, Y - => N_29_0); - - \Address_RNO_0[13]\ : MX2C - port map(A => \AddressSave[13]_net_1\, B => N_263, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[13]\); - - \Address_RNO[15]\ : NOR2A - port map(A => rstn, B => \Address_9[15]\, Y => - \Address_RNO[15]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m10 : XNOR2 - port map(A => BoundaryPhase_0_sqmuxa, B => \haddr[10]\, Y - => N_11_0); - - \AHBOut.hburst_RNO[0]\ : NOR3B - port map(A => \hburst_11_0_a2_1[0]\, B => rstn, C => - hgrant(3), Y => \hburst_11[0]\); - - \AddressSave_RNO_1[13]\ : MX2A - port map(A => N_1030, B => \haddr[13]\, S => - \AddressPhase_0\, Y => \AddressSave_4[13]\); - - \Address_RNO_1[23]\ : MX2C - port map(A => N_1040, B => N_55_0_i, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_273); - - \Address_RNO_0[21]\ : MX2C - port map(A => \AddressSave[21]_net_1\, B => N_271, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[21]\); - - \AHBOut.hwrite_RNO_2\ : OR3B - port map(A => iosn_0(93), B => WriteAcc_m_0, C => hgrant(3), - Y => WriteAcc_m); - - \AddressSave[19]\ : DFN1 - port map(D => \AddressSave_RNO[19]_net_1\, CLK => lclk_c, Q - => \AddressSave[19]_net_1\); - - \Address_RNO_1[13]\ : MX2C - port map(A => N_1030, B => N_52_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_263); - - un1_AddressSave_0_sqmuxa_1_m59 : AX1E - port map(A => \haddr[30]\, B => N_41, C => \haddr[31]\, Y - => N_60_0); - - \Address_RNO_1[9]\ : MX2C - port map(A => N_1026, B => N_84_i, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_259); - - \Address_RNO_0[0]\ : MX2C - port map(A => \AddressSave[0]_net_1\, B => N_250, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[0]\); - - DataPhase_RNIC3IU1_1 : OR2B - port map(A => dataphase10, B => hresp(0), Y => \Fault\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_dma is - - port( addr_data_f0 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - l1_0_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - bco_msb_1_m : in std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - hgrant : in std_logic_vector(3 to 3); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - bco_msb_1 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - hmaster_0 : in std_logic_vector(1 to 1); - hsize : out std_logic_vector(1 downto 0); - nhmaster_1_i : in std_logic_vector(0 to 0); - iosn_1 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - htrans : out std_logic_vector(1 downto 0); - hburst : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0); - data_ren : out std_logic_vector(3 downto 0); - ready_i_0_i_0 : in std_logic_vector(1 to 1); - ready_i_0_2 : in std_logic; - ready_i_0_0 : in std_logic; - ready_i_0_3 : in std_logic; - time_ren : out std_logic_vector(3 downto 0); - time_ren_1z : out std_logic; - data_ren_1z : out std_logic; - m26_m1_e : out std_logic; - m19_a1_6_i_0 : out std_logic; - m19_a0_6_i_0 : out std_logic; - m19_0_N_15_i_0_li : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - Lock_RNIU86D : out std_logic; - hbusreq_i_3 : out std_logic; - arb_1 : in std_logic; - un1_dmain_6 : out std_logic; - hwrite : out std_logic; - IdlePhase : out std_logic; - un13_time_write : out std_logic; - un5_time_write : out std_logic; - un27_time_write : out std_logic; - un20_time_write : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_waveform_dma; - -architecture DEF_ARCH of lpp_waveform_dma is - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(2 to 2); - status_full : out std_logic_vector(2 to 2); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - update_and_sel_3 : in std_logic_vector(5 downto 4) := (others => 'U'); - status_full_ack : in std_logic_vector(2 to 2) := (others => 'U'); - addr_data_vector_30 : in std_logic := 'U'; - addr_data_vector_31 : in std_logic := 'U'; - addr_data_vector_5 : in std_logic := 'U'; - addr_data_vector_8 : in std_logic := 'U'; - addr_data_vector_7 : in std_logic := 'U'; - addr_data_vector_6 : in std_logic := 'U'; - addr_data_vector_3 : in std_logic := 'U'; - addr_data_vector_14 : in std_logic := 'U'; - addr_data_vector_11 : in std_logic := 'U'; - addr_data_vector_10 : in std_logic := 'U'; - addr_data_vector_9 : in std_logic := 'U'; - addr_data_vector_21 : in std_logic := 'U'; - addr_data_vector_19 : in std_logic := 'U'; - addr_data_vector_18 : in std_logic := 'U'; - addr_data_vector_17 : in std_logic := 'U'; - addr_data_vector_29 : in std_logic := 'U'; - addr_data_vector_26 : in std_logic := 'U'; - addr_data_vector_25 : in std_logic := 'U'; - addr_data_vector_24 : in std_logic := 'U'; - addr_data_vector_1 : in std_logic := 'U'; - addr_data_vector_68 : out std_logic; - addr_data_vector_66 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_91 : out std_logic; - addr_data_vector_15 : in std_logic := 'U'; - addr_data_vector_12 : in std_logic := 'U'; - addr_data_vector_20 : in std_logic := 'U'; - addr_data_vector_16 : in std_logic := 'U'; - addr_data_vector_28 : in std_logic := 'U'; - addr_data_vector_23 : in std_logic := 'U'; - addr_data_vector_0 : in std_logic := 'U'; - addr_data_vector_86 : out std_logic; - N_1365 : out std_logic; - N_1366 : out std_logic; - N_1396 : out std_logic; - N_1399 : out std_logic; - N_1398 : out std_logic; - N_1397 : out std_logic; - N_1394 : out std_logic; - N_1391 : out std_logic; - N_1388 : out std_logic; - N_1387 : out std_logic; - N_1386 : out std_logic; - N_1384 : out std_logic; - N_1382 : out std_logic; - N_1381 : out std_logic; - N_1380 : out std_logic; - N_1378 : out std_logic; - N_1375 : out std_logic; - N_1374 : out std_logic; - N_1373 : out std_logic; - N_1350 : out std_logic; - N_1392 : out std_logic; - N_1389 : out std_logic; - N_1383 : out std_logic; - N_1379 : out std_logic; - N_1377 : out std_logic; - N_1372 : out std_logic; - N_1349 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(0 to 0); - status_full : out std_logic_vector(0 to 0); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_7 : in std_logic_vector(1 downto 0) := (others => 'U'); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(0 to 0) := (others => 'U'); - addr_data_vector_1 : out std_logic; - addr_data_vector_0 : out std_logic; - addr_data_vector_68 : in std_logic := 'U'; - addr_data_vector_66 : in std_logic := 'U'; - addr_data_vector_77 : in std_logic := 'U'; - addr_data_vector_86 : in std_logic := 'U'; - addr_data_vector_91 : in std_logic := 'U'; - addr_data_vector_31 : out std_logic; - addr_data_vector_30 : out std_logic; - addr_data_vector_5 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_25 : out std_logic; - addr_data_vector_24 : out std_logic; - addr_data_vector_23 : out std_logic; - addr_data_vector_12 : out std_logic; - addr_data_vector_11 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_8 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_3 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_18 : out std_logic; - addr_data_vector_17 : out std_logic; - addr_data_vector_21 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_16 : out std_logic; - addr_data_vector_19 : out std_logic; - addr_data_vector_20 : out std_logic; - N_1395 : out std_logic; - N_1393 : out std_logic; - N_1390 : out std_logic; - N_1385 : out std_logic; - N_1376 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_dma_send_16word - port( un7_dmain : out std_logic_vector(66 to 66); - state_0_0 : in std_logic := 'U'; - Address_RNIJ4SP : out std_logic_vector(20 to 20); - Address_RNIP8BS : out std_logic_vector(0 to 0); - data_address : in std_logic_vector(31 downto 0) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - Lock : out std_logic; - Request_0 : in std_logic := 'U'; - N_1081 : out std_logic; - Store_0 : in std_logic := 'U'; - N_1082 : out std_logic; - Fault : in std_logic := 'U'; - N_1022 : out std_logic; - data_send_ok : out std_logic; - data_send_ko : out std_logic; - N_1102 : out std_logic; - N_1027 : out std_logic; - N_1026 : out std_logic; - N_1025 : out std_logic; - N_1024 : out std_logic; - N_1023 : out std_logic; - N_1021 : out std_logic; - N_1034 : out std_logic; - N_1033 : out std_logic; - N_1031 : out std_logic; - N_1030 : out std_logic; - N_1029 : out std_logic; - N_1028 : out std_logic; - N_1041 : out std_logic; - time_select : in std_logic := 'U'; - N_1040 : out std_logic; - N_1039 : out std_logic; - N_1038 : out std_logic; - N_1036 : out std_logic; - N_1035 : out std_logic; - N_1048 : out std_logic; - N_1047 : out std_logic; - N_1046 : out std_logic; - N_1044 : out std_logic; - N_1043 : out std_logic; - N_1042 : out std_logic; - N_1020 : out std_logic; - N_1019 : out std_logic; - N_1018 : out std_logic; - data_fifo_ren : out std_logic; - N_1032 : out std_logic; - N_1045 : out std_logic; - time_select_0 : in std_logic := 'U'; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - Grant_1_0 : in std_logic := 'U'; - m19_0_N_15_i_0_li : in std_logic := 'U'; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - OKAY : in std_logic := 'U'; - Ready : in std_logic := 'U'; - data_send : in std_logic := 'U'; - Grant_0 : in std_logic := 'U'; - Grant : in std_logic := 'U'; - m26_m1_e : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(1 to 1); - status_full : out std_logic_vector(1 to 1); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_5 : in std_logic_vector(3 downto 2) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_vector_69 : in std_logic := 'U'; - addr_data_vector_95 : in std_logic := 'U'; - addr_data_vector_94 : in std_logic := 'U'; - addr_data_vector_93 : in std_logic := 'U'; - addr_data_vector_91 : in std_logic := 'U'; - addr_data_vector_89 : in std_logic := 'U'; - addr_data_vector_88 : in std_logic := 'U'; - addr_data_vector_85 : in std_logic := 'U'; - addr_data_vector_68 : in std_logic := 'U'; - addr_data_vector_67 : in std_logic := 'U'; - addr_data_vector_66 : in std_logic := 'U'; - addr_data_vector_65 : in std_logic := 'U'; - addr_data_vector_74 : in std_logic := 'U'; - addr_data_vector_72 : in std_logic := 'U'; - addr_data_vector_71 : in std_logic := 'U'; - addr_data_vector_70 : in std_logic := 'U'; - addr_data_vector_82 : in std_logic := 'U'; - addr_data_vector_78 : in std_logic := 'U'; - addr_data_vector_87 : in std_logic := 'U'; - addr_data_vector_84 : in std_logic := 'U'; - addr_data_vector_64 : in std_logic := 'U'; - addr_data_vector_80 : in std_logic := 'U'; - addr_data_vector_76 : in std_logic := 'U'; - addr_data_vector_28 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_13 : out std_logic; - addr_data_vector_11 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_17 : out std_logic; - addr_data_vector_19 : out std_logic; - addr_data_vector_22 : out std_logic; - N_1358 : out std_logic; - N_984 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_980 : out std_logic; - N_978 : out std_logic; - N_977 : out std_logic; - N_974 : out std_logic; - N_1371 : out std_logic; - N_1370 : out std_logic; - N_1369 : out std_logic; - N_1368 : out std_logic; - N_1363 : out std_logic; - N_1361 : out std_logic; - N_1360 : out std_logic; - N_1359 : out std_logic; - N_1357 : out std_logic; - N_1353 : out std_logic; - N_976 : out std_logic; - N_973 : out std_logic; - N_1367 : out std_logic; - N_1355 : out std_logic; - N_1351 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_dma_send_1word - port( Request : out std_logic; - Store : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - Grant : in std_logic := 'U'; - un1_time_send_ok : out std_logic; - Fault : in std_logic := 'U'; - Ready : in std_logic := 'U'; - time_select_0 : in std_logic := 'U'; - Lock : in std_logic := 'U'; - Lock_RNIU86D : out std_logic; - time_send : in std_logic := 'U' - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(3 to 3); - status_full : out std_logic_vector(3 to 3); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(3 to 3) := (others => 'U'); - addr_data_vector_56 : out std_logic; - addr_data_vector_55 : out std_logic; - addr_data_vector_17 : in std_logic := 'U'; - addr_data_vector_13 : in std_logic := 'U'; - addr_data_vector_10 : in std_logic := 'U'; - addr_data_vector_2 : in std_logic := 'U'; - addr_data_vector_0 : in std_logic := 'U'; - addr_data_vector_8 : in std_logic := 'U'; - addr_data_vector_4 : in std_logic := 'U'; - addr_data_vector_63 : out std_logic; - addr_data_vector_6 : in std_logic := 'U'; - addr_data_vector_19 : in std_logic := 'U'; - addr_data_vector_62 : out std_logic; - addr_data_vector_60 : out std_logic; - addr_data_vector_59 : out std_logic; - addr_data_vector_58 : out std_logic; - addr_data_vector_86 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_84 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_57 : out std_logic; - addr_data_vector_78 : out std_logic; - addr_data_vector_67 : out std_logic; - addr_data_vector_65 : out std_logic; - addr_data_vector_61 : out std_logic; - addr_data_vector_73 : out std_logic; - addr_data_vector_76 : out std_logic; - addr_data_vector_69 : out std_logic; - addr_data_vector_71 : out std_logic; - addr_data_vector_75 : out std_logic; - update_and_sel_1 : in std_logic_vector(7 downto 6) := (others => 'U'); - N_979 : out std_logic; - N_975 : out std_logic; - N_972 : out std_logic; - N_1364 : out std_logic; - N_1362 : out std_logic; - N_1356 : out std_logic; - N_1352 : out std_logic; - N_1354 : out std_logic; - N_981 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component DMA2AHB - port( hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - Address_RNIP8BS : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - Address_RNIJ4SP : in std_logic_vector(20 to 20) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - un7_dmain : in std_logic_vector(66 to 66) := (others => 'U'); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - Ready : out std_logic; - N_1021 : in std_logic := 'U'; - N_1032 : in std_logic := 'U'; - N_1027 : in std_logic := 'U'; - OKAY : out std_logic; - IdlePhase : out std_logic; - N_1018 : in std_logic := 'U'; - N_1025 : in std_logic := 'U'; - N_1042 : in std_logic := 'U'; - N_1034 : in std_logic := 'U'; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - N_1082 : in std_logic := 'U'; - N_1048 : in std_logic := 'U'; - N_1047 : in std_logic := 'U'; - N_1036 : in std_logic := 'U'; - N_1035 : in std_logic := 'U'; - N_1019 : in std_logic := 'U'; - N_1046 : in std_logic := 'U'; - N_1044 : in std_logic := 'U'; - N_1043 : in std_logic := 'U'; - N_1041 : in std_logic := 'U'; - N_1040 : in std_logic := 'U'; - N_1039 : in std_logic := 'U'; - N_1038 : in std_logic := 'U'; - N_1033 : in std_logic := 'U'; - N_1031 : in std_logic := 'U'; - N_1030 : in std_logic := 'U'; - N_1029 : in std_logic := 'U'; - N_1028 : in std_logic := 'U'; - N_1026 : in std_logic := 'U'; - N_1024 : in std_logic := 'U'; - N_1023 : in std_logic := 'U'; - N_1022 : in std_logic := 'U'; - N_1020 : in std_logic := 'U'; - N_1045 : in std_logic := 'U'; - Grant_0 : out std_logic; - Grant : out std_logic; - arb_1 : in std_logic := 'U'; - N_1081 : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - Grant_1_0 : out std_logic; - Fault : out std_logic; - time_select_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal count_send_time_e30_0_0, count_send_time_e30_0_a2_0, - N_1161, N_1196, count_send_time_e30_0_a2_2_1, N_1216, - \count_send_time[27]_net_1\, count_send_time_e30_0_a2_2_0, - \count_send_time_RNO[28]_net_1\, N_1226, - \count_send_time[28]_net_1\, - \count_send_time_RNO[29]_net_1\, N_1230, - \count_send_time[29]_net_1\, count_send_time_e31, N_1264, - N_1261, N_1263, count_send_time_e30, N_1198, N_1197, - N_1215_0, count_send_time_e25, N_1250, N_1248, N_1247, - N_1231, \count_send_time[31]_net_1\, \state_0[2]_net_1\, - N_1232, N_1213, \count_send_time[25]_net_1\, - \state[2]_net_1\, count_send_time_e30_0_a2_0_0, N_1127, - \count_send_time[11]_net_1\, \count_send_time[12]_net_1\, - N_1229, N_1129, \count_send_time[13]_net_1\, - \count_send_time[14]_net_1\, N_1131, - \count_send_time[15]_net_1\, \count_send_time[16]_net_1\, - N_1133, \count_send_time[17]_net_1\, - \count_send_time[18]_net_1\, N_1136, - \count_send_time[19]_net_1\, \count_send_time[20]_net_1\, - N_1139, \count_send_time[21]_net_1\, - \count_send_time[22]_net_1\, - \count_send_time_RNO[26]_net_1\, N_1233, - \count_send_time[26]_net_1\, - \count_send_time_RNO[27]_net_1\, N_1234, - \count_send_time[23]_net_1\, \count_send_time[24]_net_1\, - N_1215, \count_send_time[9]_net_1\, - \count_send_time[10]_net_1\, N_1295, N_1287, - \count_send_time[0]_net_1\, \count_send_time[1]_net_1\, - \count_send_time[2]_net_1\, N_1289, - \count_send_time[3]_net_1\, \count_send_time[4]_net_1\, - N_1291, \count_send_time[5]_net_1\, N_1293, - \count_send_time[6]_net_1\, \count_send_time[7]_net_1\, - \count_send_time[8]_net_1\, \sel_data_0[0]_net_1\, N_1086, - \state[7]_net_1\, \sel_data_1[1]_net_1\, N_1085, - \sel_data_0[1]_net_1\, \state_RNI9NH4I4[4]_net_1\, - \time_select_0\, time_fifo_ren_1, N_868, - time_fifo_ren_1_i, \time_ren\, count_send_time_e12_0_0, - count_send_time_e12_0_a2_1_0, N_1151, - count_send_time_e18_0_0, N_1207, N_1169, - count_send_time_e20_0_0, count_send_time_e20_0_a2_1_0, - N_1177, count_send_time_e22_0_0, - count_send_time_e22_0_a2_1_0, N_1187, - count_send_time_e24_0_0, count_send_time_e24_0_a2_1_0, - N_1243, count_send_time_e1_0_0, - count_send_time_e1_0_a2_1_0, N_1307, - count_send_time_e8_0_0, count_send_time_e8_0_a2_1_0, - N_1330, count_send_time_e10_0_0, - count_send_time_e10_0_a2_1_0, N_1340, - count_send_time_e16_i_0, count_send_time_e14_i_0, - count_send_time_e2_0_a2_1_0, \count_send_time[30]_net_1\, - \data_data_ren_7_0[0]\, \un27_time_write\, - count_send_time_e24_0_a2_0_0, count_send_time_e22_0_a2_0, - count_send_time_e20_0_a2_0, count_send_time_e18_0_a2_0_0, - \state_ns_i_a2_0_1[5]\, N_899_tz, N_1120, N_1118, - state_tr2_i_0, \send_16_3_time[0]_net_1\, - \state_ns_i_a2_0_a3_0[5]\, \sel_data_3_i_0[0]\, - \send_16_3_time_1_sqmuxa_i_o3_0\, - count_send_time_e12_0_a2_0_0, count_send_time_e10_0_a2_0, - count_send_time_e8_0_a2_0, state_tr13_0_a2_15, - state_tr13_0_a2_9, state_tr13_0_a2_8, state_tr13_0_a2_12, - state_tr13_0_a2_14, state_tr13_0_a2_7, state_tr13_0_a2_10, - state_tr13_0_a2_17_0, state_tr13_0_a2_17_1, - state_tr13_0_a2_11, state_tr13_0_a2_6, state_tr13_0_a2_4, - state_tr13_0_a2_1, \state_ns_i_a2_0_a4_0_19_15[5]\, - N_1117_25, \state_ns_i_a2_0_a4_0_19_14[5]\, - \state_ns_i_a2_0_a4_0_19_11[5]\, N_1117_5, - \state_ns_i_a2_0_a4_0_25_4[5]\, - \state_ns_i_a2_0_a4_0_25_2[5]\, - \state_ns_i_a2_0_a4_0_25_1[5]\, - \state_ns_i_a2_0_a4_0_25_0[5]\, - count_send_time_e2_0_a2_0_0, un1_state_13_0_a4_0_0, - \state[1]_net_1\, \state[3]_net_1\, - \state_ns_i_a2_0_a4_0_19_11_0[5]\, N_1099, - \count_send_time_RNO[14]_net_1\, - \count_send_time_RNO_0[14]_net_1\, - \count_send_time_RNO[15]_net_1\, N_1147, N_1162, - \count_send_time_RNO[16]_net_1\, - \count_send_time_RNO[17]_net_1\, N_1166, - \count_send_time_RNO[6]_net_1\, N_1300, N_1323, - \count_send_time_RNO[7]_net_1\, \state_ns[6]\, - count_send_time_e10, N_1290, count_send_time_e9, N_1338, - N_1335, N_1337, count_send_time_e8, count_send_time_e3, - N_1319, N_1317, N_1316, count_send_time_e2, N_1314, - N_1312, N_1311, count_send_time_e1, count_send_time_e24, - count_send_time_e11, N_1240, N_1237, N_1239, - count_send_time_e23, N_1193, N_1191, N_1192, - count_send_time_e22, count_send_time_e21, N_1184, N_1182, - N_1183, count_send_time_e20, count_send_time_e19, N_1174, - N_1173, N_1172, count_send_time_e18, count_send_time_e13, - N_1157, N_1156, N_1155, count_send_time_e12, N_1106, - N_864, \state[0]_net_1\, \state_RNO[6]_net_1\, - \state[4]_net_1\, N_1096, data_fifo_ren, un7_time_write, - \time_write\, \un5_time_write\, un2_status_full_ack, - \data_ren\, \un13_time_write\, \update_and_sel_1[6]\, - \update[0]_net_1\, \update_and_sel_1[7]\, - \update[1]_net_1\, \update_and_sel_3[4]\, - \update_and_sel_3[5]\, un15_time_write, - un7_status_full_ack, un17_status_full_ack, - un29_time_write, \data_address[0]\, N_1349, N_1367, - \data_address[12]\, N_1389, N_1351, \data_address[16]\, - N_1379, N_1355, \data_address[20]\, N_1383, N_973, - \data_address[23]\, N_1372, N_976, \data_address[28]\, - N_1377, N_981, N_1094, \time_already_send[3]\, - \time_already_send[2]\, N_1095, \time_already_send[1]\, - \time_already_send[0]\, \data_address[15]\, N_1392, - N_1354, \sel_data[1]_net_1\, \un20_time_write\, - un22_time_write, un12_status_full_ack, \time_select\, - \update_and_sel_5[2]\, \update_and_sel_5[3]\, - \update_and_sel_7[0]\, \update_and_sel_7[1]\, - \data_address[1]\, N_1350, N_1368, \data_address[2]\, - N_1393, N_1369, \data_address[3]\, N_1394, N_1370, - \data_address[4]\, N_1395, N_1371, \data_address[6]\, - N_1397, N_1359, \data_address[7]\, N_1398, N_1360, - \data_address[8]\, N_1399, N_1361, \data_address[9]\, - N_1386, N_1362, \sel_data[0]_net_1\, \data_address[10]\, - N_1387, N_1363, \data_address[11]\, N_1388, N_1364, - \data_address[13]\, N_1390, N_1352, \data_address[14]\, - N_1391, N_1353, \data_address[17]\, N_1380, N_1356, - \data_address[18]\, N_1381, N_1357, \data_address[19]\, - N_1382, N_972, \data_address[21]\, N_1384, N_974, - \data_address[22]\, N_1385, N_975, \data_address[24]\, - N_1373, N_977, \data_address[25]\, N_1374, N_978, - \data_address[26]\, N_1375, N_979, \data_address[27]\, - N_1376, N_980, \data_address[29]\, N_1378, N_982, - \data_address[30]\, N_1365, N_983, \data_address[31]\, - N_1366, N_984, un1_state_12, N_1102, \state[6]_net_1\, - \state_RNO_0[0]\, count_send_time_e0, - \count_send_time_RNO[4]_net_1\, N_1297, - \count_send_time_RNO[5]_net_1\, N_1298, \state_RNO_1[3]\, - N_1103, \state_RNO_0[4]_net_1\, N_1114, - \state_RNO[5]_net_1\, N_1112, \state_RNO[7]_net_1\, - N_1109, un1_state_13, N_1084, un1_time_send_ok, - \state[5]_net_1\, data_send_ko, data_send_ok, - time_send_0_sqmuxa, update_0_sqmuxa, \time_fifo_ren\, - \data_address[5]\, N_1396, N_1358, N_867, \time_send\, - \data_send\, \send_16_3_time[2]_net_1\, - \send_16_3_time[1]_net_1\, \Address_RNIP8BS[0]\, - \Address_RNIJ4SP[20]\, \un7_dmain[66]\, Ready, N_1021, - N_1032, N_1027, OKAY, N_1018, N_1025, N_1042, N_1034, - N_1082, N_1048, N_1047, N_1036, N_1035, N_1019, N_1046, - N_1044, N_1043, N_1041, N_1040, N_1039, N_1038, N_1033, - N_1031, N_1030, N_1029, N_1028, N_1026, N_1024, N_1023, - N_1022, N_1020, N_1045, Grant_0, Grant, N_1081, Grant_1_0, - Fault, Request, Store, Lock, \addr_data_vector[97]\, - \addr_data_vector[96]\, \addr_data_vector[58]\, - \addr_data_vector[54]\, \addr_data_vector[51]\, - \addr_data_vector[43]\, \addr_data_vector[41]\, - \addr_data_vector[49]\, \addr_data_vector[45]\, - \addr_data_vector[104]\, \addr_data_vector[47]\, - \addr_data_vector[60]\, \addr_data_vector[103]\, - \addr_data_vector[101]\, \addr_data_vector[100]\, - \addr_data_vector[99]\, \addr_data_vector[127]\, - \addr_data_vector[126]\, \addr_data_vector[125]\, - \addr_data_vector[123]\, \addr_data_vector[121]\, - \addr_data_vector[120]\, \addr_data_vector[98]\, - \addr_data_vector[119]\, \addr_data_vector[108]\, - \addr_data_vector[106]\, \addr_data_vector[102]\, - \addr_data_vector[114]\, \addr_data_vector[117]\, - \addr_data_vector[110]\, \addr_data_vector[112]\, - \addr_data_vector[116]\, \addr_data_vector[30]\, - \addr_data_vector[31]\, \addr_data_vector[5]\, - \addr_data_vector[8]\, \addr_data_vector[7]\, - \addr_data_vector[6]\, \addr_data_vector[3]\, - \addr_data_vector[14]\, \addr_data_vector[11]\, - \addr_data_vector[10]\, \addr_data_vector[9]\, - \addr_data_vector[21]\, \addr_data_vector[19]\, - \addr_data_vector[18]\, \addr_data_vector[17]\, - \addr_data_vector[29]\, \addr_data_vector[26]\, - \addr_data_vector[25]\, \addr_data_vector[24]\, - \addr_data_vector[1]\, \addr_data_vector[68]\, - \addr_data_vector[66]\, \addr_data_vector[77]\, - \addr_data_vector[91]\, \addr_data_vector[15]\, - \addr_data_vector[12]\, \addr_data_vector[20]\, - \addr_data_vector[16]\, \addr_data_vector[28]\, - \addr_data_vector[23]\, \addr_data_vector[0]\, - \addr_data_vector[86]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\(DEF_ARCH); - for all : lpp_dma_send_16word - Use entity work.lpp_dma_send_16word(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\(DEF_ARCH); - for all : lpp_dma_send_1word - Use entity work.lpp_dma_send_1word(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\(DEF_ARCH); - for all : DMA2AHB - Use entity work.DMA2AHB(DEF_ARCH); -begin - - time_ren_1z <= \time_ren\; - data_ren_1z <= \data_ren\; - un13_time_write <= \un13_time_write\; - un5_time_write <= \un5_time_write\; - un27_time_write <= \un27_time_write\; - un20_time_write <= \un20_time_write\; - - \update_RNI42QC_1[0]\ : NOR2A - port map(A => \update[0]_net_1\, B => \un13_time_write\, Y - => \update_and_sel_3[4]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNO_0[0]\, CLK => lclk_c, CLR => rstn, - Q => \state[0]_net_1\); - - \count_send_time_RNO_0[9]\ : OR3 - port map(A => N_1295, B => \count_send_time[9]_net_1\, C - => N_1215_0, Y => N_1338); - - \state_RNI7A1C_0[2]\ : OAI1 - port map(A => \state[2]_net_1\, B => \state[7]_net_1\, C - => rstn, Y => N_1290); - - \count_send_time_RNO_4[30]\ : AOI1B - port map(A => \count_send_time[29]_net_1\, B => - \count_send_time[28]_net_1\, C => - \count_send_time[30]_net_1\, Y => - count_send_time_e30_0_a2_0); - - time_select_RNIC84U1J_0 : OR2 - port map(A => \data_ren\, B => \un20_time_write\, Y => - data_ren(1)); - - \sel_data[0]\ : DFN1E1C0 - port map(D => N_1086, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data[0]_net_1\); - - \gen_select_address.2.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(2) => status_full_err(2), status_full(2) - => status_full(2), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, sel_data_0(1) => - \sel_data_0[1]_net_1\, addr_data_f2(31) => - addr_data_f2(31), addr_data_f2(30) => addr_data_f2(30), - addr_data_f2(29) => addr_data_f2(29), addr_data_f2(28) - => addr_data_f2(28), addr_data_f2(27) => - addr_data_f2(27), addr_data_f2(26) => addr_data_f2(26), - addr_data_f2(25) => addr_data_f2(25), addr_data_f2(24) - => addr_data_f2(24), addr_data_f2(23) => - addr_data_f2(23), addr_data_f2(22) => addr_data_f2(22), - addr_data_f2(21) => addr_data_f2(21), addr_data_f2(20) - => addr_data_f2(20), addr_data_f2(19) => - addr_data_f2(19), addr_data_f2(18) => addr_data_f2(18), - addr_data_f2(17) => addr_data_f2(17), addr_data_f2(16) - => addr_data_f2(16), addr_data_f2(15) => - addr_data_f2(15), addr_data_f2(14) => addr_data_f2(14), - addr_data_f2(13) => addr_data_f2(13), addr_data_f2(12) - => addr_data_f2(12), addr_data_f2(11) => - addr_data_f2(11), addr_data_f2(10) => addr_data_f2(10), - addr_data_f2(9) => addr_data_f2(9), addr_data_f2(8) => - addr_data_f2(8), addr_data_f2(7) => addr_data_f2(7), - addr_data_f2(6) => addr_data_f2(6), addr_data_f2(5) => - addr_data_f2(5), addr_data_f2(4) => addr_data_f2(4), - addr_data_f2(3) => addr_data_f2(3), addr_data_f2(2) => - addr_data_f2(2), addr_data_f2(1) => addr_data_f2(1), - addr_data_f2(0) => addr_data_f2(0), update_and_sel_3(5) - => \update_and_sel_3[5]\, update_and_sel_3(4) => - \update_and_sel_3[4]\, status_full_ack(2) => - status_full_ack(2), addr_data_vector_30 => - \addr_data_vector[30]\, addr_data_vector_31 => - \addr_data_vector[31]\, addr_data_vector_5 => - \addr_data_vector[5]\, addr_data_vector_8 => - \addr_data_vector[8]\, addr_data_vector_7 => - \addr_data_vector[7]\, addr_data_vector_6 => - \addr_data_vector[6]\, addr_data_vector_3 => - \addr_data_vector[3]\, addr_data_vector_14 => - \addr_data_vector[14]\, addr_data_vector_11 => - \addr_data_vector[11]\, addr_data_vector_10 => - \addr_data_vector[10]\, addr_data_vector_9 => - \addr_data_vector[9]\, addr_data_vector_21 => - \addr_data_vector[21]\, addr_data_vector_19 => - \addr_data_vector[19]\, addr_data_vector_18 => - \addr_data_vector[18]\, addr_data_vector_17 => - \addr_data_vector[17]\, addr_data_vector_29 => - \addr_data_vector[29]\, addr_data_vector_26 => - \addr_data_vector[26]\, addr_data_vector_25 => - \addr_data_vector[25]\, addr_data_vector_24 => - \addr_data_vector[24]\, addr_data_vector_1 => - \addr_data_vector[1]\, addr_data_vector_68 => - \addr_data_vector[68]\, addr_data_vector_66 => - \addr_data_vector[66]\, addr_data_vector_77 => - \addr_data_vector[77]\, addr_data_vector_91 => - \addr_data_vector[91]\, addr_data_vector_15 => - \addr_data_vector[15]\, addr_data_vector_12 => - \addr_data_vector[12]\, addr_data_vector_20 => - \addr_data_vector[20]\, addr_data_vector_16 => - \addr_data_vector[16]\, addr_data_vector_28 => - \addr_data_vector[28]\, addr_data_vector_23 => - \addr_data_vector[23]\, addr_data_vector_0 => - \addr_data_vector[0]\, addr_data_vector_86 => - \addr_data_vector[86]\, N_1365 => N_1365, N_1366 => - N_1366, N_1396 => N_1396, N_1399 => N_1399, N_1398 => - N_1398, N_1397 => N_1397, N_1394 => N_1394, N_1391 => - N_1391, N_1388 => N_1388, N_1387 => N_1387, N_1386 => - N_1386, N_1384 => N_1384, N_1382 => N_1382, N_1381 => - N_1381, N_1380 => N_1380, N_1378 => N_1378, N_1375 => - N_1375, N_1374 => N_1374, N_1373 => N_1373, N_1350 => - N_1350, N_1392 => N_1392, N_1389 => N_1389, N_1383 => - N_1383, N_1379 => N_1379, N_1377 => N_1377, N_1372 => - N_1372, N_1349 => N_1349, rstn => rstn, lclk_c => lclk_c); - - \sel_data_RNI1G8O[0]\ : MX2C - port map(A => N_1386, B => N_1362, S => \sel_data[0]_net_1\, - Y => \data_address[9]\); - - \count_send_time_RNO_0[16]\ : AO1C - port map(A => N_1215_0, B => N_1131, C => N_1161, Y => - count_send_time_e16_i_0); - - \count_send_time_RNIN93N3[24]\ : OR3B - port map(A => \count_send_time[23]_net_1\, B => - \count_send_time[24]_net_1\, C => N_1139, Y => N_1213); - - \count_send_time_RNO_2[1]\ : OR3B - port map(A => \count_send_time[1]_net_1\, B => - \state[2]_net_1\, C => \count_send_time[0]_net_1\, Y => - N_1307); - - \count_send_time_RNO[4]\ : XA1A - port map(A => N_1297, B => \count_send_time[4]_net_1\, C - => N_1161, Y => \count_send_time_RNO[4]_net_1\); - - \gen_select_address.0.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(0) => status_full_err(0), status_full(0) - => status_full(0), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, - update_and_sel_7(1) => \update_and_sel_7[1]\, - update_and_sel_7(0) => \update_and_sel_7[0]\, - addr_data_f0(31) => addr_data_f0(31), addr_data_f0(30) - => addr_data_f0(30), addr_data_f0(29) => - addr_data_f0(29), addr_data_f0(28) => addr_data_f0(28), - addr_data_f0(27) => addr_data_f0(27), addr_data_f0(26) - => addr_data_f0(26), addr_data_f0(25) => - addr_data_f0(25), addr_data_f0(24) => addr_data_f0(24), - addr_data_f0(23) => addr_data_f0(23), addr_data_f0(22) - => addr_data_f0(22), addr_data_f0(21) => - addr_data_f0(21), addr_data_f0(20) => addr_data_f0(20), - addr_data_f0(19) => addr_data_f0(19), addr_data_f0(18) - => addr_data_f0(18), addr_data_f0(17) => - addr_data_f0(17), addr_data_f0(16) => addr_data_f0(16), - addr_data_f0(15) => addr_data_f0(15), addr_data_f0(14) - => addr_data_f0(14), addr_data_f0(13) => - addr_data_f0(13), addr_data_f0(12) => addr_data_f0(12), - addr_data_f0(11) => addr_data_f0(11), addr_data_f0(10) - => addr_data_f0(10), addr_data_f0(9) => addr_data_f0(9), - addr_data_f0(8) => addr_data_f0(8), addr_data_f0(7) => - addr_data_f0(7), addr_data_f0(6) => addr_data_f0(6), - addr_data_f0(5) => addr_data_f0(5), addr_data_f0(4) => - addr_data_f0(4), addr_data_f0(3) => addr_data_f0(3), - addr_data_f0(2) => addr_data_f0(2), addr_data_f0(1) => - addr_data_f0(1), addr_data_f0(0) => addr_data_f0(0), - status_full_ack(0) => status_full_ack(0), - addr_data_vector_1 => \addr_data_vector[1]\, - addr_data_vector_0 => \addr_data_vector[0]\, - addr_data_vector_68 => \addr_data_vector[68]\, - addr_data_vector_66 => \addr_data_vector[66]\, - addr_data_vector_77 => \addr_data_vector[77]\, - addr_data_vector_86 => \addr_data_vector[86]\, - addr_data_vector_91 => \addr_data_vector[91]\, - addr_data_vector_31 => \addr_data_vector[31]\, - addr_data_vector_30 => \addr_data_vector[30]\, - addr_data_vector_5 => \addr_data_vector[5]\, - addr_data_vector_29 => \addr_data_vector[29]\, - addr_data_vector_28 => \addr_data_vector[28]\, - addr_data_vector_26 => \addr_data_vector[26]\, - addr_data_vector_25 => \addr_data_vector[25]\, - addr_data_vector_24 => \addr_data_vector[24]\, - addr_data_vector_23 => \addr_data_vector[23]\, - addr_data_vector_12 => \addr_data_vector[12]\, - addr_data_vector_11 => \addr_data_vector[11]\, - addr_data_vector_10 => \addr_data_vector[10]\, - addr_data_vector_9 => \addr_data_vector[9]\, - addr_data_vector_8 => \addr_data_vector[8]\, - addr_data_vector_7 => \addr_data_vector[7]\, - addr_data_vector_3 => \addr_data_vector[3]\, - addr_data_vector_6 => \addr_data_vector[6]\, - addr_data_vector_18 => \addr_data_vector[18]\, - addr_data_vector_17 => \addr_data_vector[17]\, - addr_data_vector_21 => \addr_data_vector[21]\, - addr_data_vector_14 => \addr_data_vector[14]\, - addr_data_vector_15 => \addr_data_vector[15]\, - addr_data_vector_16 => \addr_data_vector[16]\, - addr_data_vector_19 => \addr_data_vector[19]\, - addr_data_vector_20 => \addr_data_vector[20]\, N_1395 => - N_1395, N_1393 => N_1393, N_1390 => N_1390, N_1385 => - N_1385, N_1376 => N_1376, rstn => rstn, lclk_c => lclk_c); - - \count_send_time_RNO[26]\ : XA1A - port map(A => N_1233, B => \count_send_time[26]_net_1\, C - => N_1161, Y => \count_send_time_RNO[26]_net_1\); - - \count_send_time_RNIT30B[16]\ : NOR2 - port map(A => \count_send_time[16]_net_1\, B => - \count_send_time[17]_net_1\, Y => state_tr13_0_a2_1); - - \count_send_time[0]\ : DFN1 - port map(D => count_send_time_e0, CLK => lclk_c, Q => - \count_send_time[0]_net_1\); - - \count_send_time_RNO_3[2]\ : OR3B - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => - \count_send_time[2]_net_1\, Y => - count_send_time_e2_0_a2_1_0); - - \count_send_time_RNO_0[10]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e10_0_a2_1_0, - C => N_1340, Y => count_send_time_e10_0_0); - - \count_send_time_RNO[2]\ : OR3C - port map(A => N_1314, B => N_1312, C => N_1311, Y => - count_send_time_e2); - - \count_send_time_RNIR4B7[6]\ : NOR2 - port map(A => \count_send_time[6]_net_1\, B => - \count_send_time[7]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_1[5]\); - - \sel_data_0_RNI5D5K[0]\ : MX2C - port map(A => N_1349, B => N_1367, S => - \sel_data_0[0]_net_1\, Y => \data_address[0]\); - - \state_RNII50G[4]\ : OR3 - port map(A => \state[4]_net_1\, B => \state[6]_net_1\, C - => \state[2]_net_1\, Y => time_fifo_ren_1); - - \count_send_time_RNIK5324[26]\ : NOR3B - port map(A => \count_send_time[25]_net_1\, B => - \count_send_time[26]_net_1\, C => N_1213, Y => N_1216); - - time_fifo_ren_RNO : INV - port map(A => time_fifo_ren_1, Y => time_fifo_ren_1_i); - - lpp_dma_send_16word_1 : lpp_dma_send_16word - port map(un7_dmain(66) => \un7_dmain[66]\, state_0_0 => - \state[0]_net_1\, Address_RNIJ4SP(20) => - \Address_RNIJ4SP[20]\, Address_RNIP8BS(0) => - \Address_RNIP8BS[0]\, data_address(31) => - \data_address[31]\, data_address(30) => - \data_address[30]\, data_address(29) => - \data_address[29]\, data_address(28) => - \data_address[28]\, data_address(27) => - \data_address[27]\, data_address(26) => - \data_address[26]\, data_address(25) => - \data_address[25]\, data_address(24) => - \data_address[24]\, data_address(23) => - \data_address[23]\, data_address(22) => - \data_address[22]\, data_address(21) => - \data_address[21]\, data_address(20) => - \data_address[20]\, data_address(19) => - \data_address[19]\, data_address(18) => - \data_address[18]\, data_address(17) => - \data_address[17]\, data_address(16) => - \data_address[16]\, data_address(15) => - \data_address[15]\, data_address(14) => - \data_address[14]\, data_address(13) => - \data_address[13]\, data_address(12) => - \data_address[12]\, data_address(11) => - \data_address[11]\, data_address(10) => - \data_address[10]\, data_address(9) => \data_address[9]\, - data_address(8) => \data_address[8]\, data_address(7) => - \data_address[7]\, data_address(6) => \data_address[6]\, - data_address(5) => \data_address[5]\, data_address(4) => - \data_address[4]\, data_address(3) => \data_address[3]\, - data_address(2) => \data_address[2]\, data_address(1) => - \data_address[1]\, data_address(0) => \data_address[0]\, - bco_msb_1_m(1) => bco_msb_1_m(1), nhmaster_1_iv_0(1) => - nhmaster_1_iv_0(1), bco_msb_1(1) => bco_msb_1(1), - hmaster_0(1) => hmaster_0(1), l1_0_m(1) => l1_0_m(1), - nhmaster_1_i(0) => nhmaster_1_i(0), iosn_0(93) => - iosn_0(93), Lock => Lock, Request_0 => Request, N_1081 - => N_1081, Store_0 => Store, N_1082 => N_1082, Fault => - Fault, N_1022 => N_1022, data_send_ok => data_send_ok, - data_send_ko => data_send_ko, N_1102 => N_1102, N_1027 - => N_1027, N_1026 => N_1026, N_1025 => N_1025, N_1024 - => N_1024, N_1023 => N_1023, N_1021 => N_1021, N_1034 - => N_1034, N_1033 => N_1033, N_1031 => N_1031, N_1030 - => N_1030, N_1029 => N_1029, N_1028 => N_1028, N_1041 - => N_1041, time_select => \time_select\, N_1040 => - N_1040, N_1039 => N_1039, N_1038 => N_1038, N_1036 => - N_1036, N_1035 => N_1035, N_1048 => N_1048, N_1047 => - N_1047, N_1046 => N_1046, N_1044 => N_1044, N_1043 => - N_1043, N_1042 => N_1042, N_1020 => N_1020, N_1019 => - N_1019, N_1018 => N_1018, data_fifo_ren => data_fifo_ren, - N_1032 => N_1032, N_1045 => N_1045, time_select_0 => - \time_select_0\, un1_nhmaster_0_sqmuxa_1 => - un1_nhmaster_0_sqmuxa_1, rstoutl_RNIGJKSJO => - rstoutl_RNIGJKSJO, Grant_1_0 => Grant_1_0, - m19_0_N_15_i_0_li => m19_0_N_15_i_0_li, m19_a0_6_i_0 => - m19_a0_6_i_0, m19_a1_6_i_0 => m19_a1_6_i_0, OKAY => OKAY, - Ready => Ready, data_send => \data_send\, Grant_0 => - Grant_0, Grant => Grant, m26_m1_e => m26_m1_e, rstn => - rstn, lclk_c => lclk_c); - - \count_send_time_RNO_0[27]\ : OR2A - port map(A => N_1216, B => N_1215, Y => N_1234); - - \count_send_time_RNO_1[19]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[19]_net_1\, C => N_1133, Y => N_1173); - - \count_send_time[14]\ : DFN1 - port map(D => \count_send_time_RNO[14]_net_1\, CLK => - lclk_c, Q => \count_send_time[14]_net_1\); - - \state[6]\ : DFN1C0 - port map(D => \state_RNO[6]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[6]_net_1\); - - \count_send_time_RNO_2[18]\ : NOR2B - port map(A => \count_send_time[18]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e18_0_a2_0_0); - - \count_send_time[21]\ : DFN1 - port map(D => count_send_time_e21, CLK => lclk_c, Q => - \count_send_time[21]_net_1\); - - \send_16_3_time_RNI8PM9[0]\ : NOR2A - port map(A => \state[7]_net_1\, B => - \send_16_3_time[0]_net_1\, Y => \state_ns_i_a2_0_a3_0[5]\); - - \count_send_time_RNO[14]\ : OA1B - port map(A => \count_send_time_RNO_0[14]_net_1\, B => - \count_send_time[14]_net_1\, C => count_send_time_e14_i_0, - Y => \count_send_time_RNO[14]_net_1\); - - \count_send_time[31]\ : DFN1 - port map(D => count_send_time_e31, CLK => lclk_c, Q => - \count_send_time[31]_net_1\); - - \sel_data_0_RNIDF8O[0]\ : MX2C - port map(A => N_1395, B => N_1371, S => - \sel_data_0[0]_net_1\, Y => \data_address[4]\); - - \sel_data_0_RNIQV7O[0]\ : MX2C - port map(A => N_1399, B => N_1361, S => - \sel_data_0[0]_net_1\, Y => \data_address[8]\); - - \count_send_time_RNO[22]\ : AO1B - port map(A => \count_send_time[22]_net_1\, B => N_1290, C - => count_send_time_e22_0_0, Y => count_send_time_e22); - - time_write_RNO : AO1D - port map(A => un1_state_13_0_a4_0_0, B => \state[7]_net_1\, - C => N_1103, Y => un1_state_13); - - \count_send_time[17]\ : DFN1 - port map(D => \count_send_time_RNO[17]_net_1\, CLK => - lclk_c, Q => \count_send_time[17]_net_1\); - - \sel_data_RNIK0TS[0]\ : MX2C - port map(A => N_1366, B => N_984, S => \sel_data[0]_net_1\, - Y => \data_address[31]\); - - \count_send_time_RNO_0[3]\ : OR3 - port map(A => N_1287, B => \count_send_time[3]_net_1\, C - => N_1215_0, Y => N_1319); - - \sel_data_RNITDRK[0]\ : MX2C - port map(A => N_1380, B => N_1356, S => \sel_data[0]_net_1\, - Y => \data_address[17]\); - - \state_RNICG1QD2[7]\ : OR2B - port map(A => \state[7]_net_1\, B => N_1099, Y => N_1084); - - \count_send_time_RNO_2[8]\ : AO1B - port map(A => \count_send_time[7]_net_1\, B => N_1293, C - => count_send_time_e8_0_a2_0, Y => N_1330); - - \count_send_time_RNIJ4B7[2]\ : NOR2A - port map(A => \count_send_time[3]_net_1\, B => - \count_send_time[2]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_2[5]\); - - \count_send_time_RNO[7]\ : XA1 - port map(A => N_1300, B => \count_send_time[7]_net_1\, C - => N_1161, Y => \count_send_time_RNO[7]_net_1\); - - \all_time_write.0.time_already_send_RNIJMR8U1[0]\ : MX2 - port map(A => N_1095, B => \time_already_send[0]\, S => - ready_i_0_0, Y => N_1096); - - \count_send_time_RNO_2[9]\ : OR2B - port map(A => \count_send_time[9]_net_1\, B => N_1290, Y - => N_1337); - - \count_send_time[25]\ : DFN1 - port map(D => count_send_time_e25, CLK => lclk_c, Q => - \count_send_time[25]_net_1\); - - \count_send_time_RNO_7[30]\ : NOR2B - port map(A => \count_send_time[30]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e30_0_a2_0_0); - - \count_send_time[5]\ : DFN1 - port map(D => \count_send_time_RNO[5]_net_1\, CLK => lclk_c, - Q => \count_send_time[5]_net_1\); - - \update[1]\ : DFN1E0C0 - port map(D => \state[0]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_12, Q => \update[1]_net_1\); - - time_select : DFN1E1C0 - port map(D => time_fifo_ren_1, CLK => lclk_c, CLR => rstn, - E => N_868, Q => \time_select\); - - \count_send_time_RNO_0[2]\ : OR2 - port map(A => count_send_time_e2_0_a2_1_0, B => N_1215_0, Y - => N_1314); - - \count_send_time_RNO[27]\ : XA1A - port map(A => N_1234, B => \count_send_time[27]_net_1\, C - => N_1161, Y => \count_send_time_RNO[27]_net_1\); - - \state_RNIG9BMJ2[2]\ : NOR3C - port map(A => N_899_tz, B => N_1120, C => N_1118, Y => - \state_ns_i_a2_0_1[5]\); - - \count_send_time_RNO_1[10]\ : OR3A - port map(A => \count_send_time[9]_net_1\, B => N_1295, C - => \count_send_time[10]_net_1\, Y => - count_send_time_e10_0_a2_1_0); - - \count_send_time_RNO[0]\ : MX2A - port map(A => N_1215, B => N_1290, S => - \count_send_time[0]_net_1\, Y => count_send_time_e0); - - \count_send_time_RNITRFG[29]\ : NOR3C - port map(A => \count_send_time[28]_net_1\, B => - \count_send_time[29]_net_1\, C => - \count_send_time[30]_net_1\, Y => N_1231); - - \count_send_time_RNO[10]\ : AO1B - port map(A => \count_send_time[10]_net_1\, B => N_1290, C - => count_send_time_e10_0_0, Y => count_send_time_e10); - - \sel_data_0_RNIC84U1J[0]\ : OR2 - port map(A => \data_ren\, B => \un13_time_write\, Y => - data_ren(2)); - - \all_time_write.3.time_already_send[3]\ : DFN1E1C0 - port map(D => un7_time_write, CLK => lclk_c, CLR => rstn, E - => un2_status_full_ack, Q => \time_already_send[3]\); - - \sel_data_0[1]\ : DFN1E1C0 - port map(D => N_1085, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data_0[1]_net_1\); - - \state[4]\ : DFN1C0 - port map(D => \state_RNO_0[4]_net_1\, CLK => lclk_c, CLR - => rstn, Q => \state[4]_net_1\); - - \update_RNI56QC_2[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un27_time_write\, Y - => \update_and_sel_7[1]\); - - time_write : DFN1E0C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_13, Q => \time_write\); - - data_send_RNO : NOR3 - port map(A => \state[0]_net_1\, B => \state[1]_net_1\, C - => \state[7]_net_1\, Y => N_864); - - \sel_data_1[1]\ : DFN1E1C0 - port map(D => N_1085, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data_1[1]_net_1\); - - \count_send_time[28]\ : DFN1 - port map(D => \count_send_time_RNO[28]_net_1\, CLK => - lclk_c, Q => \count_send_time[28]_net_1\); - - \sel_data_0_RNIC7S6[0]\ : OR2B - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => \un5_time_write\); - - \count_send_time_RNIGFVB1[14]\ : NOR3C - port map(A => state_tr13_0_a2_17_0, B => - state_tr13_0_a2_17_1, C => state_tr13_0_a2_7, Y => - \state_ns_i_a2_0_a4_0_19_11[5]\); - - \sel_data_RNI1URK[0]\ : MX2C - port map(A => N_1381, B => N_1357, S => \sel_data[0]_net_1\, - Y => \data_address[18]\); - - \count_send_time_RNIRJVA[24]\ : NOR2 - port map(A => \count_send_time[24]_net_1\, B => - \count_send_time[25]_net_1\, Y => state_tr13_0_a2_17_1); - - \count_send_time_RNIFE5M2[17]\ : OR3C - port map(A => N_1131, B => \count_send_time[17]_net_1\, C - => \count_send_time[18]_net_1\, Y => N_1133); - - \count_send_time[8]\ : DFN1 - port map(D => count_send_time_e8, CLK => lclk_c, Q => - \count_send_time[8]_net_1\); - - \count_send_time_RNO[13]\ : OR3C - port map(A => N_1157, B => N_1156, C => N_1155, Y => - count_send_time_e13); - - \state[7]\ : DFN1P0 - port map(D => \state_RNO[7]_net_1\, CLK => lclk_c, PRE => - rstn, Q => \state[7]_net_1\); - - \state_RNILE0L_0[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => un1_time_send_ok, Y - => N_1103); - - \count_send_time_RNO[3]\ : OR3C - port map(A => N_1319, B => N_1317, C => N_1316, Y => - count_send_time_e3); - - \count_send_time[10]\ : DFN1 - port map(D => count_send_time_e10, CLK => lclk_c, Q => - \count_send_time[10]_net_1\); - - \count_send_time_RNO_2[30]\ : OR2B - port map(A => \count_send_time[30]_net_1\, B => N_1290, Y - => N_1197); - - \sel_data_0_RNITBNG[0]\ : MX2C - port map(A => N_1392, B => N_1354, S => - \sel_data_0[0]_net_1\, Y => \data_address[15]\); - - \state[5]\ : DFN1C0 - port map(D => \state_RNO[5]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[5]_net_1\); - - \count_send_time_RNIBV6A1[10]\ : OR3B - port map(A => \count_send_time[9]_net_1\, B => - \count_send_time[10]_net_1\, C => N_1295, Y => N_1229); - - data_send : DFN1E0C0 - port map(D => \state[1]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_864, Q => \data_send\); - - \count_send_time_RNIUT3C3[22]\ : OR3B - port map(A => \count_send_time[21]_net_1\, B => - \count_send_time[22]_net_1\, C => N_1136, Y => N_1139); - - \count_send_time_RNO_1[2]\ : OR2B - port map(A => count_send_time_e2_0_a2_0_0, B => - \state_0[2]_net_1\, Y => N_1312); - - GND_i : GND - port map(Y => \GND\); - - \count_send_time_RNIMRUA[30]\ : NOR2 - port map(A => \count_send_time[23]_net_1\, B => - \count_send_time[30]_net_1\, Y => state_tr13_0_a2_6); - - time_send_RNO : OA1B - port map(A => \state[4]_net_1\, B => \state[6]_net_1\, C - => N_1096, Y => time_send_0_sqmuxa); - - \state_RNIE50G[5]\ : NOR3 - port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C - => \state[0]_net_1\, Y => N_868); - - \count_send_time_RNO_3[24]\ : NOR2B - port map(A => \count_send_time[24]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e24_0_a2_0_0); - - \count_send_time_RNO_0[25]\ : OR3 - port map(A => N_1213, B => \count_send_time[25]_net_1\, C - => N_1215_0, Y => N_1250); - - \sel_data_RNIMVTO[0]\ : MX2C - port map(A => N_1376, B => N_980, S => \sel_data[0]_net_1\, - Y => \data_address[27]\); - - \count_send_time_RNIGLBC2[15]\ : NOR3B - port map(A => N_1129, B => \count_send_time[15]_net_1\, C - => N_1215, Y => N_1147); - - \count_send_time_RNO_3[12]\ : NOR2B - port map(A => \count_send_time[12]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e12_0_a2_0_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNI4QUO[4]\ : OR3A - port map(A => N_1102, B => \state[4]_net_1\, C => - \state[6]_net_1\, Y => un1_state_12); - - \DMAWriteFSM_p.sel_data_3_i[0]\ : OA1C - port map(A => ready_i_0_2, B => ready_i_0_i_0(1), C => - \sel_data_3_i_0[0]\, Y => N_1086); - - \state_RNO_0[5]\ : OR2A - port map(A => \state[5]_net_1\, B => un1_time_send_ok, Y - => N_1112); - - \state_RNO_0[4]\ : OR2B - port map(A => \state[5]_net_1\, B => un1_time_send_ok, Y - => N_1114); - - \sel_data_0_RNIIV7O[0]\ : MX2C - port map(A => N_1397, B => N_1359, S => - \sel_data_0[0]_net_1\, Y => \data_address[6]\); - - \count_send_time_RNO_3[31]\ : OR3C - port map(A => N_1216, B => \count_send_time[27]_net_1\, C - => N_1231, Y => N_1232); - - \count_send_time_RNO_1[25]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[25]_net_1\, C => N_1213, Y => N_1248); - - \count_send_time_RNO_2[25]\ : OR2B - port map(A => \count_send_time[25]_net_1\, B => N_1290, Y - => N_1247); - - \count_send_time_RNO_6[30]\ : OR3B - port map(A => \count_send_time[28]_net_1\, B => - \count_send_time[29]_net_1\, C => - \count_send_time[30]_net_1\, Y => - count_send_time_e30_0_a2_2_0); - - \state_RNO_0[7]\ : OAI1 - port map(A => data_send_ko, B => data_send_ok, C => - \state[0]_net_1\, Y => N_1109); - - \DMAWriteFSM_p.sel_data_3_i_0[0]\ : AO1D - port map(A => ready_i_0_3, B => ready_i_0_i_0(1), C => - ready_i_0_0, Y => \sel_data_3_i_0[0]\); - - time_write_RNIC7ID_1 : NOR2A - port map(A => \time_write\, B => \un13_time_write\, Y => - un15_time_write); - - \count_send_time_RNIV30B[26]\ : NOR2 - port map(A => \count_send_time[26]_net_1\, B => - \count_send_time[27]_net_1\, Y => state_tr13_0_a2_17_0); - - \count_send_time_RNIKICT[0]\ : NOR3C - port map(A => \state_ns_i_a2_0_a4_0_25_1[5]\, B => - \state_ns_i_a2_0_a4_0_25_0[5]\, C => - \state_ns_i_a2_0_a4_0_25_4[5]\, Y => N_1117_25); - - \count_send_time_RNI2PBI[29]\ : NOR3 - port map(A => \count_send_time[29]_net_1\, B => - \count_send_time[28]_net_1\, C => N_1117_5, Y => - state_tr13_0_a2_8); - - time_write_RNIC7ID : NOR2A - port map(A => \time_write\, B => \un5_time_write\, Y => - un7_time_write); - - \count_send_time[7]\ : DFN1 - port map(D => \count_send_time_RNO[7]_net_1\, CLK => lclk_c, - Q => \count_send_time[7]_net_1\); - - \count_send_time_RNO[25]\ : OR3C - port map(A => N_1250, B => N_1248, C => N_1247, Y => - count_send_time_e25); - - \all_data_ren.1.data_time_ren_5[1]\ : OR2A - port map(A => \time_ren\, B => \un20_time_write\, Y => - time_ren(1)); - - \count_send_time_RNICVTL[22]\ : NOR3A - port map(A => state_tr13_0_a2_6, B => - \count_send_time[22]_net_1\, C => - \count_send_time[13]_net_1\, Y => state_tr13_0_a2_10); - - \count_send_time_RNO_1[9]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[9]_net_1\, C => N_1295, Y => N_1335); - - \sel_data_RNIEVSO[0]\ : MX2C - port map(A => N_1374, B => N_978, S => \sel_data[0]_net_1\, - Y => \data_address[25]\); - - \count_send_time_RNO[31]\ : OR3C - port map(A => N_1264, B => N_1261, C => N_1263, Y => - count_send_time_e31); - - \state_RNO[1]\ : NOR3C - port map(A => state_tr13_0_a2_14, B => N_1117_25, C => - state_tr13_0_a2_15, Y => \state_ns[6]\); - - \count_send_time_RNIN4B7[4]\ : NOR2 - port map(A => \count_send_time[4]_net_1\, B => - \count_send_time[5]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_0[5]\); - - \count_send_time_RNO_3[22]\ : NOR2B - port map(A => \count_send_time[22]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e22_0_a2_0); - - \update_RNI42QC_2[0]\ : NOR2A - port map(A => \update[0]_net_1\, B => \un27_time_write\, Y - => \update_and_sel_7[0]\); - - time_write_RNIC7ID_0 : NOR2A - port map(A => \time_write\, B => \un20_time_write\, Y => - un22_time_write); - - \count_send_time_RNO_0[13]\ : OR3 - port map(A => N_1127, B => \count_send_time[13]_net_1\, C - => N_1215, Y => N_1157); - - time_select_RNIC84U1J : OR2 - port map(A => \data_ren\, B => \un5_time_write\, Y => - data_ren(3)); - - \sel_data_0[0]\ : DFN1E1C0 - port map(D => N_1086, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data_0[0]_net_1\); - - \count_send_time_RNO_0[14]\ : NOR3A - port map(A => \count_send_time[13]_net_1\, B => N_1127, C - => N_1215, Y => \count_send_time_RNO_0[14]_net_1\); - - \count_send_time_RNO[8]\ : AO1B - port map(A => \count_send_time[8]_net_1\, B => N_1290, C - => count_send_time_e8_0_0, Y => count_send_time_e8); - - \count_send_time[26]\ : DFN1 - port map(D => \count_send_time_RNO[26]_net_1\, CLK => - lclk_c, Q => \count_send_time[26]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \count_send_time_RNIK7VL[20]\ : OR3A - port map(A => \state_ns_i_a2_0_a4_0_19_11_0[5]\, B => - \count_send_time[21]_net_1\, C => - \count_send_time[20]_net_1\, Y => state_tr13_0_a2_11); - - \sel_data[1]\ : DFN1E1C0 - port map(D => N_1085, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data[1]_net_1\); - - \all_time_write.0.time_already_send[0]\ : DFN1E1C0 - port map(D => un29_time_write, CLK => lclk_c, CLR => rstn, - E => un17_status_full_ack, Q => \time_already_send[0]\); - - \count_send_time[29]\ : DFN1 - port map(D => \count_send_time_RNO[29]_net_1\, CLK => - lclk_c, Q => \count_send_time[29]_net_1\); - - \send_16_3_time[1]\ : DFN1E0C0 - port map(D => \send_16_3_time[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => N_1084, Q => \send_16_3_time[1]_net_1\); - - \count_send_time_RNI6GAK2[20]\ : NOR3B - port map(A => state_tr13_0_a2_8, B => - \state_ns_i_a2_0_a4_0_19_11[5]\, C => state_tr13_0_a2_11, - Y => \state_ns_i_a2_0_a4_0_19_14[5]\); - - \state_RNO[4]\ : AO1B - port map(A => \state[6]_net_1\, B => N_1096, C => N_1114, Y - => \state_RNO_0[4]_net_1\); - - \count_send_time_RNO[19]\ : OR3C - port map(A => N_1174, B => N_1173, C => N_1172, Y => - count_send_time_e19); - - send_16_3_time_1_sqmuxa_i_o3_0 : NOR3 - port map(A => ready_i_0_i_0(1), B => ready_i_0_3, C => - ready_i_0_2, Y => \send_16_3_time_1_sqmuxa_i_o3_0\); - - \state_RNI7A1C[2]\ : OR3B - port map(A => \state[7]_net_1\, B => rstn, C => - \state[2]_net_1\, Y => N_1161); - - \count_send_time_RNI60NP[6]\ : NOR2B - port map(A => \count_send_time[6]_net_1\, B => N_1291, Y - => N_1293); - - \all_time_write.3.time_already_send_RNO[3]\ : OR2 - port map(A => status_full_ack(3), B => un7_time_write, Y - => un2_status_full_ack); - - \sel_data_RNIHTPK[0]\ : MX2C - port map(A => N_1391, B => N_1353, S => \sel_data[0]_net_1\, - Y => \data_address[14]\); - - \count_send_time_RNO_1[30]\ : AOI1B - port map(A => count_send_time_e30_0_a2_0, B => N_1161, C - => N_1196, Y => count_send_time_e30_0_0); - - \count_send_time[13]\ : DFN1 - port map(D => count_send_time_e13, CLK => lclk_c, Q => - \count_send_time[13]_net_1\); - - \count_send_time[12]\ : DFN1 - port map(D => count_send_time_e12, CLK => lclk_c, Q => - \count_send_time[12]_net_1\); - - \DMAWriteFSM_p.sel_data_3_i[1]\ : NOR3 - port map(A => N_1106, B => ready_i_0_i_0(1), C => - ready_i_0_0, Y => N_1085); - - \count_send_time_RNO_0[12]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e12_0_a2_1_0, - C => N_1151, Y => count_send_time_e12_0_0); - - \count_send_time_RNO[24]\ : AO1B - port map(A => \count_send_time[24]_net_1\, B => N_1290, C - => count_send_time_e24_0_0, Y => count_send_time_e24); - - \count_send_time_RNO_2[3]\ : OR2B - port map(A => \count_send_time[3]_net_1\, B => N_1290, Y - => N_1316); - - \count_send_time_RNO_0[30]\ : OR2 - port map(A => count_send_time_e30_0_a2_2_1, B => N_1215_0, - Y => N_1198); - - \count_send_time_RNO_1[13]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[13]_net_1\, C => N_1127, Y => N_1156); - - \sel_data_RNIDDPK[0]\ : MX2C - port map(A => N_1390, B => N_1352, S => \sel_data[0]_net_1\, - Y => \data_address[13]\); - - \count_send_time_RNO_2[19]\ : OR2B - port map(A => \count_send_time[19]_net_1\, B => N_1290, Y - => N_1172); - - \count_send_time_RNO_1[14]\ : AO1C - port map(A => N_1215_0, B => N_1129, C => N_1161, Y => - count_send_time_e14_i_0); - - \count_send_time_RNO_0[6]\ : OA1C - port map(A => N_1291, B => N_1215, C => - \count_send_time[6]_net_1\, Y => N_1323); - - \count_send_time_RNO_0[11]\ : OR3 - port map(A => N_1229, B => \count_send_time[11]_net_1\, C - => N_1215_0, Y => N_1240); - - \all_time_write.2.time_already_send[2]\ : DFN1E1C0 - port map(D => un15_time_write, CLK => lclk_c, CLR => rstn, - E => un7_status_full_ack, Q => \time_already_send[2]\); - - \count_send_time_RNI35211[7]\ : OR3C - port map(A => N_1293, B => \count_send_time[7]_net_1\, C - => \count_send_time[8]_net_1\, Y => N_1295); - - \count_send_time[4]\ : DFN1 - port map(D => \count_send_time_RNO[4]_net_1\, CLK => lclk_c, - Q => \count_send_time[4]_net_1\); - - \state_RNO[6]\ : NOR2A - port map(A => N_1099, B => state_tr2_i_0, Y => - \state_RNO[6]_net_1\); - - \count_send_time[3]\ : DFN1 - port map(D => count_send_time_e3, CLK => lclk_c, Q => - \count_send_time[3]_net_1\); - - \count_send_time_RNO_0[29]\ : NOR2B - port map(A => \count_send_time[28]_net_1\, B => N_1226, Y - => N_1230); - - \count_send_time_RNO[1]\ : AO1B - port map(A => \count_send_time[1]_net_1\, B => N_1290, C - => count_send_time_e1_0_0, Y => count_send_time_e1); - - \count_send_time_RNO_1[3]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[3]_net_1\, C => N_1287, Y => N_1317); - - \sel_data_0_RNIND6K[0]\ : MX2C - port map(A => N_1394, B => N_1370, S => - \sel_data_0[0]_net_1\, Y => \data_address[3]\); - - \all_data_ren.0.data_time_ren_7[0]\ : OR2A - port map(A => \time_ren\, B => \un27_time_write\, Y => - time_ren(0)); - - \count_send_time_RNO[20]\ : AO1B - port map(A => \count_send_time[20]_net_1\, B => N_1290, C - => count_send_time_e20_0_0, Y => count_send_time_e20); - - \state_RNO[7]\ : AO1C - port map(A => N_1099, B => \state[7]_net_1\, C => N_1109, Y - => \state_RNO[7]_net_1\); - - \count_send_time[2]\ : DFN1 - port map(D => count_send_time_e2, CLK => lclk_c, Q => - \count_send_time[2]_net_1\); - - \count_send_time_RNO_2[10]\ : AO1C - port map(A => N_1295, B => \count_send_time[9]_net_1\, C - => count_send_time_e10_0_a2_0, Y => N_1340); - - \count_send_time_RNIIS9E4[27]\ : NOR3B - port map(A => N_1216, B => \count_send_time[27]_net_1\, C - => N_1215, Y => N_1226); - - \count_send_time_RNO_0[26]\ : OR3A - port map(A => \count_send_time[25]_net_1\, B => N_1213, C - => N_1215, Y => N_1233); - - \count_send_time_RNI61892[31]\ : NOR3C - port map(A => state_tr13_0_a2_10, B => state_tr13_0_a2_9, C - => N_1117_25, Y => \state_ns_i_a2_0_a4_0_19_15[5]\); - - \state_RNI9NH4I4[4]\ : AO1B - port map(A => \state[4]_net_1\, B => N_1096, C => - \state_ns_i_a2_0_1[5]\, Y => \state_RNI9NH4I4[4]_net_1\); - - \count_send_time_RNO[18]\ : AO1B - port map(A => \count_send_time[18]_net_1\, B => N_1290, C - => count_send_time_e18_0_0, Y => count_send_time_e18); - - \state_RNO_0[1]\ : NOR3C - port map(A => \state_0[2]_net_1\, B => state_tr13_0_a2_7, C - => state_tr13_0_a2_10, Y => state_tr13_0_a2_14); - - \state_RNO_2[1]\ : NOR3B - port map(A => state_tr13_0_a2_17_0, B => - state_tr13_0_a2_17_1, C => state_tr13_0_a2_11, Y => - state_tr13_0_a2_12); - - \count_send_time_RNO[6]\ : NOR3A - port map(A => N_1161, B => N_1300, C => N_1323, Y => - \count_send_time_RNO[6]_net_1\); - - \sel_data_0_RNIJD6K[0]\ : MX2C - port map(A => N_1393, B => N_1369, S => - \sel_data_0[0]_net_1\, Y => \data_address[2]\); - - \gen_select_address.1.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(1) => status_full_err(1), status_full(1) - => status_full(1), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, - update_and_sel_5(3) => \update_and_sel_5[3]\, - update_and_sel_5(2) => \update_and_sel_5[2]\, - sel_data_0(1) => \sel_data_0[1]_net_1\, addr_data_f1(31) - => addr_data_f1(31), addr_data_f1(30) => - addr_data_f1(30), addr_data_f1(29) => addr_data_f1(29), - addr_data_f1(28) => addr_data_f1(28), addr_data_f1(27) - => addr_data_f1(27), addr_data_f1(26) => - addr_data_f1(26), addr_data_f1(25) => addr_data_f1(25), - addr_data_f1(24) => addr_data_f1(24), addr_data_f1(23) - => addr_data_f1(23), addr_data_f1(22) => - addr_data_f1(22), addr_data_f1(21) => addr_data_f1(21), - addr_data_f1(20) => addr_data_f1(20), addr_data_f1(19) - => addr_data_f1(19), addr_data_f1(18) => - addr_data_f1(18), addr_data_f1(17) => addr_data_f1(17), - addr_data_f1(16) => addr_data_f1(16), addr_data_f1(15) - => addr_data_f1(15), addr_data_f1(14) => - addr_data_f1(14), addr_data_f1(13) => addr_data_f1(13), - addr_data_f1(12) => addr_data_f1(12), addr_data_f1(11) - => addr_data_f1(11), addr_data_f1(10) => - addr_data_f1(10), addr_data_f1(9) => addr_data_f1(9), - addr_data_f1(8) => addr_data_f1(8), addr_data_f1(7) => - addr_data_f1(7), addr_data_f1(6) => addr_data_f1(6), - addr_data_f1(5) => addr_data_f1(5), addr_data_f1(4) => - addr_data_f1(4), addr_data_f1(3) => addr_data_f1(3), - addr_data_f1(2) => addr_data_f1(2), addr_data_f1(1) => - addr_data_f1(1), addr_data_f1(0) => addr_data_f1(0), - status_full_ack(1) => status_full_ack(1), - addr_data_vector_69 => \addr_data_vector[101]\, - addr_data_vector_95 => \addr_data_vector[127]\, - addr_data_vector_94 => \addr_data_vector[126]\, - addr_data_vector_93 => \addr_data_vector[125]\, - addr_data_vector_91 => \addr_data_vector[123]\, - addr_data_vector_89 => \addr_data_vector[121]\, - addr_data_vector_88 => \addr_data_vector[120]\, - addr_data_vector_85 => \addr_data_vector[117]\, - addr_data_vector_68 => \addr_data_vector[100]\, - addr_data_vector_67 => \addr_data_vector[99]\, - addr_data_vector_66 => \addr_data_vector[98]\, - addr_data_vector_65 => \addr_data_vector[97]\, - addr_data_vector_74 => \addr_data_vector[106]\, - addr_data_vector_72 => \addr_data_vector[104]\, - addr_data_vector_71 => \addr_data_vector[103]\, - addr_data_vector_70 => \addr_data_vector[102]\, - addr_data_vector_82 => \addr_data_vector[114]\, - addr_data_vector_78 => \addr_data_vector[110]\, - addr_data_vector_87 => \addr_data_vector[119]\, - addr_data_vector_84 => \addr_data_vector[116]\, - addr_data_vector_64 => \addr_data_vector[96]\, - addr_data_vector_80 => \addr_data_vector[112]\, - addr_data_vector_76 => \addr_data_vector[108]\, - addr_data_vector_28 => \addr_data_vector[60]\, - addr_data_vector_26 => \addr_data_vector[58]\, - addr_data_vector_13 => \addr_data_vector[45]\, - addr_data_vector_11 => \addr_data_vector[43]\, - addr_data_vector_9 => \addr_data_vector[41]\, - addr_data_vector_15 => \addr_data_vector[47]\, - addr_data_vector_17 => \addr_data_vector[49]\, - addr_data_vector_19 => \addr_data_vector[51]\, - addr_data_vector_22 => \addr_data_vector[54]\, N_1358 => - N_1358, N_984 => N_984, N_983 => N_983, N_982 => N_982, - N_980 => N_980, N_978 => N_978, N_977 => N_977, N_974 => - N_974, N_1371 => N_1371, N_1370 => N_1370, N_1369 => - N_1369, N_1368 => N_1368, N_1363 => N_1363, N_1361 => - N_1361, N_1360 => N_1360, N_1359 => N_1359, N_1357 => - N_1357, N_1353 => N_1353, N_976 => N_976, N_973 => N_973, - N_1367 => N_1367, N_1355 => N_1355, N_1351 => N_1351, - rstn => rstn, lclk_c => lclk_c); - - \count_send_time[24]\ : DFN1 - port map(D => count_send_time_e24, CLK => lclk_c, Q => - \count_send_time[24]_net_1\); - - \all_data_ren.3.data_time_ren_1[3]\ : OR2A - port map(A => \time_ren\, B => \un5_time_write\, Y => - time_ren(3)); - - \count_send_time_RNO_1[12]\ : OR3A - port map(A => \count_send_time[11]_net_1\, B => N_1229, C - => \count_send_time[12]_net_1\, Y => - count_send_time_e12_0_a2_1_0); - - \update_RNO[0]\ : OA1 - port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C - => un1_time_send_ok, Y => update_0_sqmuxa); - - \count_send_time_RNO_0[20]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e20_0_a2_1_0, - C => N_1177, Y => count_send_time_e20_0_0); - - \count_send_time_RNO[23]\ : OR3C - port map(A => N_1193, B => N_1191, C => N_1192, Y => - count_send_time_e23); - - \count_send_time_RNO_1[11]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[11]_net_1\, C => N_1229, Y => N_1237); - - \count_send_time_RNO[11]\ : OR3C - port map(A => N_1240, B => N_1237, C => N_1239, Y => - count_send_time_e11); - - \count_send_time[27]\ : DFN1 - port map(D => \count_send_time_RNO[27]_net_1\, CLK => - lclk_c, Q => \count_send_time[27]_net_1\); - - \count_send_time_RNIV4B7[8]\ : OR2 - port map(A => \count_send_time[9]_net_1\, B => - \count_send_time[8]_net_1\, Y => N_1117_5); - - \count_send_time_RNO_1[20]\ : OR3A - port map(A => \count_send_time[19]_net_1\, B => N_1133, C - => \count_send_time[20]_net_1\, Y => - count_send_time_e20_0_a2_1_0); - - \count_send_time_RNO_4[2]\ : AOI1B - port map(A => \count_send_time[1]_net_1\, B => - \count_send_time[0]_net_1\, C => - \count_send_time[2]_net_1\, Y => - count_send_time_e2_0_a2_0_0); - - \count_send_time_RNO_2[20]\ : AO1C - port map(A => N_1133, B => \count_send_time[19]_net_1\, C - => count_send_time_e20_0_a2_0, Y => N_1177); - - time_fifo_ren_RNI89I5 : NOR2A - port map(A => \time_select\, B => \time_fifo_ren\, Y => - \time_ren\); - - \count_send_time_RNO_0[17]\ : OA1C - port map(A => N_1131, B => N_1215, C => - \count_send_time[17]_net_1\, Y => N_1166); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_1[3]\, CLK => lclk_c, CLR => rstn, - Q => \state[3]_net_1\); - - time_fifo_ren : DFN1E0P0 - port map(D => time_fifo_ren_1_i, CLK => lclk_c, PRE => rstn, - E => \state[0]_net_1\, Q => \time_fifo_ren\); - - time_write_RNO_0 : OR2 - port map(A => \state[1]_net_1\, B => \state[3]_net_1\, Y - => un1_state_13_0_a4_0_0); - - time_select_RNI018N1J : OR2A - port map(A => data_fifo_ren, B => \time_select\, Y => - \data_ren\); - - \count_send_time_RNO_1[1]\ : OR2A - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, Y => - count_send_time_e1_0_a2_1_0); - - time_select_0 : DFN1E1C0 - port map(D => time_fifo_ren_1, CLK => lclk_c, CLR => rstn, - E => N_868, Q => \time_select_0\); - - \sel_data_0_RNIDSOG[0]\ : MX2C - port map(A => N_1377, B => N_981, S => - \sel_data_0[0]_net_1\, Y => \data_address[28]\); - - \count_send_time_RNIDPBN2[17]\ : NOR3B - port map(A => N_1131, B => \count_send_time[17]_net_1\, C - => N_1215, Y => N_1207); - - \count_send_time_RNO_0[18]\ : OA1A - port map(A => N_1207, B => \count_send_time[18]_net_1\, C - => N_1169, Y => count_send_time_e18_0_0); - - lpp_dma_send_1word_1 : lpp_dma_send_1word - port map(Request => Request, Store => Store, rstn => rstn, - lclk_c => lclk_c, Grant => Grant, un1_time_send_ok => - un1_time_send_ok, Fault => Fault, Ready => Ready, - time_select_0 => \time_select_0\, Lock => Lock, - Lock_RNIU86D => Lock_RNIU86D, time_send => \time_send\); - - \all_time_write.1.time_already_send_RNI9NDDV[1]\ : MX2 - port map(A => N_1094, B => \time_already_send[1]\, S => - ready_i_0_i_0(1), Y => N_1095); - - \all_time_write.0.time_already_send_RNO[0]\ : OR2 - port map(A => status_full_ack(0), B => un29_time_write, Y - => un17_status_full_ack); - - \count_send_time_RNIPD1M[5]\ : NOR2B - port map(A => \count_send_time[5]_net_1\, B => N_1289, Y - => N_1291); - - \sel_data_RNIO2D01[0]\ : MX2C - port map(A => N_1396, B => N_1358, S => \sel_data[0]_net_1\, - Y => \data_address[5]\); - - \count_send_time_RNO_2[31]\ : OR2B - port map(A => \count_send_time[31]_net_1\, B => N_1290, Y - => N_1263); - - \count_send_time_RNIG25B2[16]\ : NOR3C - port map(A => N_1129, B => \count_send_time[15]_net_1\, C - => \count_send_time[16]_net_1\, Y => N_1131); - - \count_send_time[11]\ : DFN1 - port map(D => count_send_time_e11, CLK => lclk_c, Q => - \count_send_time[11]_net_1\); - - \state_RNIUIM6[2]\ : OR2B - port map(A => \state[2]_net_1\, B => rstn, Y => N_1215); - - \count_send_time[1]\ : DFN1 - port map(D => count_send_time_e1, CLK => lclk_c, Q => - \count_send_time[1]_net_1\); - - \count_send_time[9]\ : DFN1 - port map(D => count_send_time_e9, CLK => lclk_c, Q => - \count_send_time[9]_net_1\); - - \count_send_time_RNI29ME[0]\ : NOR3B - port map(A => \count_send_time[1]_net_1\, B => - \state_ns_i_a2_0_a4_0_25_2[5]\, C => - \count_send_time[0]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_4[5]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \count_send_time_RNO_1[8]\ : OR3B - port map(A => N_1293, B => \count_send_time[7]_net_1\, C - => \count_send_time[8]_net_1\, Y => - count_send_time_e8_0_a2_1_0); - - time_select_0_RNIA57D : NOR2 - port map(A => \time_select_0\, B => \un27_time_write\, Y - => \data_data_ren_7_0[0]\); - - \sel_data_RNIAFSO[0]\ : MX2C - port map(A => N_1373, B => N_977, S => \sel_data[0]_net_1\, - Y => \data_address[24]\); - - \count_send_time[20]\ : DFN1 - port map(D => count_send_time_e20, CLK => lclk_c, Q => - \count_send_time[20]_net_1\); - - \count_send_time[30]\ : DFN1 - port map(D => count_send_time_e30, CLK => lclk_c, Q => - \count_send_time[30]_net_1\); - - \count_send_time[15]\ : DFN1 - port map(D => \count_send_time_RNO[15]_net_1\, CLK => - lclk_c, Q => \count_send_time[15]_net_1\); - - \count_send_time_RNO[16]\ : OA1B - port map(A => N_1147, B => \count_send_time[16]_net_1\, C - => count_send_time_e16_i_0, Y => - \count_send_time_RNO[16]_net_1\); - - \send_16_3_time_RNIBIDUD2[0]\ : OR2B - port map(A => \state_ns_i_a2_0_a3_0[5]\, B => N_1099, Y => - N_1118); - - \DMAWriteFSM_p.sel_data_3_i_a4[1]\ : NOR2 - port map(A => ready_i_0_3, B => ready_i_0_2, Y => N_1106); - - \state_RNO[5]\ : AO1C - port map(A => N_1096, B => \state[6]_net_1\, C => N_1112, Y - => \state_RNO[5]_net_1\); - - \sel_data_0_RNIHRLG[0]\ : MX2C - port map(A => N_1389, B => N_1351, S => - \sel_data_0[0]_net_1\, Y => \data_address[12]\); - - \state_0_RNILB42[2]\ : OR2B - port map(A => \state_0[2]_net_1\, B => rstn, Y => N_1215_0); - - \sel_data_0_RNIC7S6_2[0]\ : OR2 - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => \un27_time_write\); - - \sel_data_0_RNIC7S6_1[0]\ : OR2A - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => \un13_time_write\); - - \count_send_time_RNO_1[18]\ : AO1B - port map(A => \count_send_time[17]_net_1\, B => N_1131, C - => count_send_time_e18_0_a2_0_0, Y => N_1169); - - \update_RNI56QC_1[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un13_time_write\, Y - => \update_and_sel_3[5]\); - - \sel_data_0_RNIKGEC[0]\ : OR2A - port map(A => \time_ren\, B => \un13_time_write\, Y => - time_ren(2)); - - \sel_data_RNI2FRO[0]\ : MX2C - port map(A => N_1385, B => N_975, S => \sel_data[0]_net_1\, - Y => \data_address[22]\); - - \count_send_time[18]\ : DFN1 - port map(D => count_send_time_e18, CLK => lclk_c, Q => - \count_send_time[18]_net_1\); - - \count_send_time_RNIDRBI[4]\ : NOR3B - port map(A => \count_send_time[3]_net_1\, B => - \count_send_time[4]_net_1\, C => N_1287, Y => N_1289); - - \sel_data_0_RNIMV7O[0]\ : MX2C - port map(A => N_1398, B => N_1360, S => - \sel_data_0[0]_net_1\, Y => \data_address[7]\); - - \count_send_time_RNO_0[15]\ : OA1C - port map(A => N_1129, B => N_1215, C => - \count_send_time[15]_net_1\, Y => N_1162); - - \count_send_time_RNO[12]\ : AO1B - port map(A => \count_send_time[12]_net_1\, B => N_1290, C - => count_send_time_e12_0_0, Y => count_send_time_e12); - - \state[2]\ : DFN1C0 - port map(D => \state_RNI9NH4I4[4]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \state[2]_net_1\); - - \count_send_time_RNO_5[30]\ : AO1B - port map(A => \count_send_time[27]_net_1\, B => N_1216, C - => count_send_time_e30_0_a2_0_0, Y => N_1196); - - \send_16_3_time[0]\ : DFN1E0P0 - port map(D => \send_16_3_time[2]_net_1\, CLK => lclk_c, PRE - => rstn, E => N_1084, Q => \send_16_3_time[0]_net_1\); - - \count_send_time_RNO_3[8]\ : NOR2B - port map(A => \count_send_time[8]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e8_0_a2_0); - - \count_send_time_RNO_0[8]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e8_0_a2_1_0, C - => N_1330, Y => count_send_time_e8_0_0); - - \count_send_time_RNO[29]\ : XA1 - port map(A => N_1230, B => \count_send_time[29]_net_1\, C - => N_1161, Y => \count_send_time_RNO[29]_net_1\); - - \count_send_time_RNI1K0B[18]\ : NOR2 - port map(A => \count_send_time[18]_net_1\, B => - \count_send_time[19]_net_1\, Y => - \state_ns_i_a2_0_a4_0_19_11_0[5]\); - - \count_send_time[6]\ : DFN1 - port map(D => \count_send_time_RNO[6]_net_1\, CLK => lclk_c, - Q => \count_send_time[6]_net_1\); - - \send_16_3_time[2]\ : DFN1E0C0 - port map(D => \send_16_3_time[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => N_1084, Q => \send_16_3_time[2]_net_1\); - - \sel_data_RNIGGSS[0]\ : MX2C - port map(A => N_1365, B => N_983, S => \sel_data[0]_net_1\, - Y => \data_address[30]\); - - \state_0[2]\ : DFN1C0 - port map(D => \state_RNI9NH4I4[4]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \state_0[2]_net_1\); - - \state[1]\ : DFN1C0 - port map(D => \state_ns[6]\, CLK => lclk_c, CLR => rstn, Q - => \state[1]_net_1\); - - send_16_3_time_1_sqmuxa_i_o3 : OR2A - port map(A => \send_16_3_time_1_sqmuxa_i_o3_0\, B => - ready_i_0_0, Y => N_1099); - - \state_RNIG8T25[2]\ : AO1B - port map(A => \state_ns_i_a2_0_a4_0_19_15[5]\, B => - \state_ns_i_a2_0_a4_0_19_14[5]\, C => \state[2]_net_1\, Y - => N_899_tz); - - \sel_data_0_RNICT5K[0]\ : MX2C - port map(A => N_1350, B => N_1368, S => - \sel_data_0[0]_net_1\, Y => \data_address[1]\); - - \count_send_time_RNO[17]\ : NOR3A - port map(A => N_1161, B => N_1207, C => N_1166, Y => - \count_send_time_RNO[17]_net_1\); - - time_send_RNO_0 : NOR2 - port map(A => \state[2]_net_1\, B => \state[0]_net_1\, Y - => N_867); - - \sel_data_0_RNIDRKG[0]\ : MX2C - port map(A => N_1383, B => N_973, S => - \sel_data_0[0]_net_1\, Y => \data_address[20]\); - - \state_RNO_0[6]\ : OR2B - port map(A => \send_16_3_time[0]_net_1\, B => - \state[7]_net_1\, Y => state_tr2_i_0); - - \count_send_time_RNO_2[2]\ : OR2B - port map(A => \count_send_time[2]_net_1\, B => N_1290, Y - => N_1311); - - \all_time_write.1.time_already_send_RNO[1]\ : OR2 - port map(A => status_full_ack(1), B => un22_time_write, Y - => un12_status_full_ack); - - \state_RNO[3]\ : AO1A - port map(A => N_1096, B => \state[4]_net_1\, C => N_1103, Y - => \state_RNO_1[3]\); - - \state_RNO[0]\ : OR2A - port map(A => N_1102, B => \state[1]_net_1\, Y => - \state_RNO_0[0]\); - - \count_send_time_RNIUQ5L1[12]\ : OR3B - port map(A => \count_send_time[11]_net_1\, B => - \count_send_time[12]_net_1\, C => N_1229, Y => N_1127); - - \count_send_time_RNO_2[13]\ : OR2B - port map(A => \count_send_time[13]_net_1\, B => N_1290, Y - => N_1155); - - \state_RNO_1[1]\ : NOR3C - port map(A => state_tr13_0_a2_9, B => state_tr13_0_a2_8, C - => state_tr13_0_a2_12, Y => state_tr13_0_a2_15); - - \count_send_time_RNO_0[4]\ : OR3A - port map(A => \count_send_time[3]_net_1\, B => N_1287, C - => N_1215, Y => N_1297); - - \update_RNI56QC[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un5_time_write\, Y - => \update_and_sel_1[7]\); - - time_select_0_RNIFGR22J : OR2B - port map(A => \data_data_ren_7_0[0]\, B => data_fifo_ren, Y - => data_ren(0)); - - \count_send_time_RNI4JD01[6]\ : NOR2A - port map(A => N_1293, B => N_1215, Y => N_1300); - - time_write_RNIC7ID_2 : NOR2A - port map(A => \time_write\, B => \un27_time_write\, Y => - un29_time_write); - - \sel_data_RNI4DOK[0]\ : MX2C - port map(A => N_1387, B => N_1363, S => \sel_data[0]_net_1\, - Y => \data_address[10]\); - - \count_send_time_RNO_1[31]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[31]_net_1\, C => N_1232, Y => N_1261); - - \count_send_time_RNO_0[5]\ : OR2A - port map(A => N_1289, B => N_1215, Y => N_1298); - - \sel_data_0_RNIPBMG[0]\ : MX2C - port map(A => N_1372, B => N_976, S => - \sel_data_0[0]_net_1\, Y => \data_address[23]\); - - \count_send_time_RNO_3[30]\ : OR3B - port map(A => N_1216, B => \count_send_time[27]_net_1\, C - => count_send_time_e30_0_a2_2_0, Y => - count_send_time_e30_0_a2_2_1); - - \count_send_time_RNO_0[23]\ : OR3 - port map(A => N_1139, B => \count_send_time[23]_net_1\, C - => N_1215_0, Y => N_1193); - - \count_send_time_RNO_0[24]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e24_0_a2_1_0, - C => N_1243, Y => count_send_time_e24_0_0); - - time_send : DFN1E1C0 - port map(D => time_send_0_sqmuxa, CLK => lclk_c, CLR => - rstn, E => N_867, Q => \time_send\); - - \sel_data_RNIQVUO[0]\ : MX2C - port map(A => N_1382, B => N_972, S => \sel_data[0]_net_1\, - Y => \data_address[19]\); - - \count_send_time_RNO_0[31]\ : OR3B - port map(A => N_1231, B => N_1226, C => - \count_send_time[31]_net_1\, Y => N_1264); - - \count_send_time_RNO_3[10]\ : NOR2B - port map(A => \count_send_time[10]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e10_0_a2_0); - - \all_time_write.2.time_already_send_RNINRRD9[2]\ : MX2 - port map(A => \time_already_send[3]\, B => - \time_already_send[2]\, S => ready_i_0_2, Y => N_1094); - - \count_send_time_RNO_0[1]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e1_0_a2_1_0, C - => N_1307, Y => count_send_time_e1_0_0); - - \update_RNI42QC_0[0]\ : NOR2A - port map(A => \update[0]_net_1\, B => \un20_time_write\, Y - => \update_and_sel_5[2]\); - - \update[0]\ : DFN1E0C0 - port map(D => update_0_sqmuxa, CLK => lclk_c, CLR => rstn, - E => un1_state_12, Q => \update[0]_net_1\); - - \count_send_time_RNO_1[23]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[23]_net_1\, C => N_1139, Y => N_1191); - - \count_send_time_RNO[28]\ : XA1 - port map(A => N_1226, B => \count_send_time[28]_net_1\, C - => N_1161, Y => \count_send_time_RNO[28]_net_1\); - - \count_send_time_RNO_2[23]\ : OR2B - port map(A => \count_send_time[23]_net_1\, B => N_1290, Y - => N_1192); - - \count_send_time_RNO_1[24]\ : OR3A - port map(A => \count_send_time[23]_net_1\, B => N_1139, C - => \count_send_time[24]_net_1\, Y => - count_send_time_e24_0_a2_1_0); - - \count_send_time_RNO_2[24]\ : AO1C - port map(A => N_1139, B => \count_send_time[23]_net_1\, C - => count_send_time_e24_0_a2_0_0, Y => N_1243); - - \sel_data_RNIUVUO[0]\ : MX2C - port map(A => N_1378, B => N_982, S => \sel_data[0]_net_1\, - Y => \data_address[29]\); - - \sel_data_RNIUUQO[0]\ : MX2C - port map(A => N_1384, B => N_974, S => \sel_data[0]_net_1\, - Y => \data_address[21]\); - - \count_send_time_RNIJRUA[12]\ : NOR2 - port map(A => \count_send_time[11]_net_1\, B => - \count_send_time[12]_net_1\, Y => state_tr13_0_a2_4); - - \count_send_time_RNI92513[20]\ : OR3B - port map(A => \count_send_time[19]_net_1\, B => - \count_send_time[20]_net_1\, C => N_1133, Y => N_1136); - - \count_send_time[23]\ : DFN1 - port map(D => count_send_time_e23, CLK => lclk_c, Q => - \count_send_time[23]_net_1\); - - \count_send_time[22]\ : DFN1 - port map(D => count_send_time_e22, CLK => lclk_c, Q => - \count_send_time[22]_net_1\); - - \count_send_time_RNIL6502[14]\ : NOR3B - port map(A => \count_send_time[13]_net_1\, B => - \count_send_time[14]_net_1\, C => N_1127, Y => N_1129); - - \sel_data_0_RNIC7S6_0[0]\ : OR2A - port map(A => \sel_data_0[0]_net_1\, B => - \sel_data[1]_net_1\, Y => \un20_time_write\); - - \sel_data_RNI8TOK[0]\ : MX2C - port map(A => N_1388, B => N_1364, S => \sel_data[0]_net_1\, - Y => \data_address[11]\); - - \count_send_time[16]\ : DFN1 - port map(D => \count_send_time_RNO[16]_net_1\, CLK => - lclk_c, Q => \count_send_time[16]_net_1\); - - \count_send_time_RNO[30]\ : OR3C - port map(A => N_1198, B => count_send_time_e30_0_0, C => - N_1197, Y => count_send_time_e30); - - \count_send_time_RNO[21]\ : OR3C - port map(A => N_1184, B => N_1182, C => N_1183, Y => - count_send_time_e21); - - \count_send_time_RNO_2[12]\ : AO1C - port map(A => N_1229, B => \count_send_time[11]_net_1\, C - => count_send_time_e12_0_a2_0_0, Y => N_1151); - - \all_time_write.2.time_already_send_RNO[2]\ : OR2 - port map(A => status_full_ack(2), B => un15_time_write, Y - => un7_status_full_ack); - - \all_time_write.1.time_already_send[1]\ : DFN1E1C0 - port map(D => un22_time_write, CLK => lclk_c, CLR => rstn, - E => un12_status_full_ack, Q => \time_already_send[1]\); - - \gen_select_address.3.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(3) => status_full_err(3), status_full(3) - => status_full(3), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, sel_data_0(1) => - \sel_data_0[1]_net_1\, addr_data_f3(31) => - addr_data_f3(31), addr_data_f3(30) => addr_data_f3(30), - addr_data_f3(29) => addr_data_f3(29), addr_data_f3(28) - => addr_data_f3(28), addr_data_f3(27) => - addr_data_f3(27), addr_data_f3(26) => addr_data_f3(26), - addr_data_f3(25) => addr_data_f3(25), addr_data_f3(24) - => addr_data_f3(24), addr_data_f3(23) => - addr_data_f3(23), addr_data_f3(22) => addr_data_f3(22), - addr_data_f3(21) => addr_data_f3(21), addr_data_f3(20) - => addr_data_f3(20), addr_data_f3(19) => - addr_data_f3(19), addr_data_f3(18) => addr_data_f3(18), - addr_data_f3(17) => addr_data_f3(17), addr_data_f3(16) - => addr_data_f3(16), addr_data_f3(15) => - addr_data_f3(15), addr_data_f3(14) => addr_data_f3(14), - addr_data_f3(13) => addr_data_f3(13), addr_data_f3(12) - => addr_data_f3(12), addr_data_f3(11) => - addr_data_f3(11), addr_data_f3(10) => addr_data_f3(10), - addr_data_f3(9) => addr_data_f3(9), addr_data_f3(8) => - addr_data_f3(8), addr_data_f3(7) => addr_data_f3(7), - addr_data_f3(6) => addr_data_f3(6), addr_data_f3(5) => - addr_data_f3(5), addr_data_f3(4) => addr_data_f3(4), - addr_data_f3(3) => addr_data_f3(3), addr_data_f3(2) => - addr_data_f3(2), addr_data_f3(1) => addr_data_f3(1), - addr_data_f3(0) => addr_data_f3(0), status_full_ack(3) - => status_full_ack(3), addr_data_vector_56 => - \addr_data_vector[97]\, addr_data_vector_55 => - \addr_data_vector[96]\, addr_data_vector_17 => - \addr_data_vector[58]\, addr_data_vector_13 => - \addr_data_vector[54]\, addr_data_vector_10 => - \addr_data_vector[51]\, addr_data_vector_2 => - \addr_data_vector[43]\, addr_data_vector_0 => - \addr_data_vector[41]\, addr_data_vector_8 => - \addr_data_vector[49]\, addr_data_vector_4 => - \addr_data_vector[45]\, addr_data_vector_63 => - \addr_data_vector[104]\, addr_data_vector_6 => - \addr_data_vector[47]\, addr_data_vector_19 => - \addr_data_vector[60]\, addr_data_vector_62 => - \addr_data_vector[103]\, addr_data_vector_60 => - \addr_data_vector[101]\, addr_data_vector_59 => - \addr_data_vector[100]\, addr_data_vector_58 => - \addr_data_vector[99]\, addr_data_vector_86 => - \addr_data_vector[127]\, addr_data_vector_85 => - \addr_data_vector[126]\, addr_data_vector_84 => - \addr_data_vector[125]\, addr_data_vector_82 => - \addr_data_vector[123]\, addr_data_vector_80 => - \addr_data_vector[121]\, addr_data_vector_79 => - \addr_data_vector[120]\, addr_data_vector_57 => - \addr_data_vector[98]\, addr_data_vector_78 => - \addr_data_vector[119]\, addr_data_vector_67 => - \addr_data_vector[108]\, addr_data_vector_65 => - \addr_data_vector[106]\, addr_data_vector_61 => - \addr_data_vector[102]\, addr_data_vector_73 => - \addr_data_vector[114]\, addr_data_vector_76 => - \addr_data_vector[117]\, addr_data_vector_69 => - \addr_data_vector[110]\, addr_data_vector_71 => - \addr_data_vector[112]\, addr_data_vector_75 => - \addr_data_vector[116]\, update_and_sel_1(7) => - \update_and_sel_1[7]\, update_and_sel_1(6) => - \update_and_sel_1[6]\, N_979 => N_979, N_975 => N_975, - N_972 => N_972, N_1364 => N_1364, N_1362 => N_1362, - N_1356 => N_1356, N_1352 => N_1352, N_1354 => N_1354, - N_981 => N_981, rstn => rstn, lclk_c => lclk_c); - - \sel_data_RNIIFTO[0]\ : MX2C - port map(A => N_1375, B => N_979, S => \sel_data[0]_net_1\, - Y => \data_address[26]\); - - \count_send_time_RNI6FTL[31]\ : NOR3A - port map(A => state_tr13_0_a2_4, B => - \count_send_time[10]_net_1\, C => - \count_send_time[31]_net_1\, Y => state_tr13_0_a2_9); - - \count_send_time_RNO_2[11]\ : OR2B - port map(A => \count_send_time[11]_net_1\, B => N_1290, Y - => N_1239); - - \count_send_time_RNO[5]\ : XA1A - port map(A => N_1298, B => \count_send_time[5]_net_1\, C - => N_1161, Y => \count_send_time_RNO[5]_net_1\); - - \count_send_time[19]\ : DFN1 - port map(D => count_send_time_e19, CLK => lclk_c, Q => - \count_send_time[19]_net_1\); - - \update_RNI42QC[0]\ : NOR2A - port map(A => \update[0]_net_1\, B => \un5_time_write\, Y - => \update_and_sel_1[6]\); - - \count_send_time_RNO_3[20]\ : NOR2B - port map(A => \count_send_time[20]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e20_0_a2_0); - - \count_send_time_RNO_0[22]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e22_0_a2_1_0, - C => N_1187, Y => count_send_time_e22_0_0); - - \count_send_time_RNO[15]\ : NOR3A - port map(A => N_1161, B => N_1147, C => N_1162, Y => - \count_send_time_RNO[15]_net_1\); - - \update_RNI56QC_0[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un20_time_write\, Y - => \update_and_sel_5[3]\); - - \sel_data_0_RNI1SNG[0]\ : MX2C - port map(A => N_1379, B => N_1355, S => - \sel_data_0[0]_net_1\, Y => \data_address[16]\); - - \count_send_time_RNIMNVL[14]\ : NOR3A - port map(A => state_tr13_0_a2_1, B => - \count_send_time[15]_net_1\, C => - \count_send_time[14]_net_1\, Y => state_tr13_0_a2_7); - - \count_send_time_RNIOM0B[2]\ : OR3C - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => - \count_send_time[2]_net_1\, Y => N_1287); - - \count_send_time_RNO_0[21]\ : OR3 - port map(A => N_1136, B => \count_send_time[21]_net_1\, C - => N_1215, Y => N_1184); - - \count_send_time_RNO_1[22]\ : OR3A - port map(A => \count_send_time[21]_net_1\, B => N_1136, C - => \count_send_time[22]_net_1\, Y => - count_send_time_e22_0_a2_1_0); - - \count_send_time_RNO_2[22]\ : AO1C - port map(A => N_1136, B => \count_send_time[21]_net_1\, C - => count_send_time_e22_0_a2_0, Y => N_1187); - - DMA2AHB_1 : DMA2AHB - port map(hburst(2) => hburst(2), hburst(1) => hburst(1), - hburst(0) => hburst(0), htrans(1) => htrans(1), htrans(0) - => htrans(0), Address_RNIP8BS(0) => \Address_RNIP8BS[0]\, - iosn_2(93) => iosn_2(93), hresp(0) => hresp(0), - Address_RNIJ4SP(20) => \Address_RNIJ4SP[20]\, iosn_1(93) - => iosn_1(93), nhmaster_1_i(0) => nhmaster_1_i(0), - hsize(1) => hsize(1), hsize(0) => hsize(0), un7_dmain(66) - => \un7_dmain[66]\, hmaster_0(1) => hmaster_0(1), - haddr(31) => haddr(31), haddr(30) => haddr(30), haddr(29) - => haddr(29), haddr(28) => haddr(28), haddr(27) => - haddr(27), haddr(26) => haddr(26), haddr(25) => haddr(25), - haddr(24) => haddr(24), haddr(23) => haddr(23), haddr(22) - => haddr(22), haddr(21) => haddr(21), haddr(20) => - haddr(20), haddr(19) => haddr(19), haddr(18) => haddr(18), - haddr(17) => haddr(17), haddr(16) => haddr(16), haddr(15) - => haddr(15), haddr(14) => haddr(14), haddr(13) => - haddr(13), haddr(12) => haddr(12), haddr(11) => haddr(11), - haddr(10) => haddr(10), haddr(9) => haddr(9), haddr(8) - => haddr(8), haddr(7) => haddr(7), haddr(6) => haddr(6), - haddr(5) => haddr(5), haddr(4) => haddr(4), haddr(3) => - haddr(3), haddr(2) => haddr(2), haddr(1) => haddr(1), - haddr(0) => haddr(0), bco_msb_1(1) => bco_msb_1(1), - hmaster_0_0_RNIFCVH1_0(1) => hmaster_0_0_RNIFCVH1_0(1), - hgrant(3) => hgrant(3), iosn_0(93) => iosn_0(93), Ready - => Ready, N_1021 => N_1021, N_1032 => N_1032, N_1027 => - N_1027, OKAY => OKAY, IdlePhase => IdlePhase, N_1018 => - N_1018, N_1025 => N_1025, N_1042 => N_1042, N_1034 => - N_1034, hwrite => hwrite, un1_dmain_6 => un1_dmain_6, - N_1082 => N_1082, N_1048 => N_1048, N_1047 => N_1047, - N_1036 => N_1036, N_1035 => N_1035, N_1019 => N_1019, - N_1046 => N_1046, N_1044 => N_1044, N_1043 => N_1043, - N_1041 => N_1041, N_1040 => N_1040, N_1039 => N_1039, - N_1038 => N_1038, N_1033 => N_1033, N_1031 => N_1031, - N_1030 => N_1030, N_1029 => N_1029, N_1028 => N_1028, - N_1026 => N_1026, N_1024 => N_1024, N_1023 => N_1023, - N_1022 => N_1022, N_1020 => N_1020, N_1045 => N_1045, - Grant_0 => Grant_0, Grant => Grant, arb_1 => arb_1, - N_1081 => N_1081, hbusreq_i_3 => hbusreq_i_3, Grant_1_0 - => Grant_1_0, Fault => Fault, time_select_0 => - \time_select_0\, rstn => rstn, lclk_c => lclk_c); - - \count_send_time_RNO_1[21]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[21]_net_1\, C => N_1136, Y => N_1182); - - \count_send_time_RNO_0[19]\ : OR3 - port map(A => N_1133, B => \count_send_time[19]_net_1\, C - => N_1215, Y => N_1174); - - \state_RNILE0L[3]\ : OR2B - port map(A => \state[3]_net_1\, B => un1_time_send_ok, Y - => N_1120); - - \count_send_time_RNO_2[21]\ : OR2B - port map(A => \count_send_time[21]_net_1\, B => N_1290, Y - => N_1183); - - \count_send_time_RNO[9]\ : OR3C - port map(A => N_1338, B => N_1335, C => N_1337, Y => - count_send_time_e9); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_arbiter is - - port( wdata : out std_logic_vector(31 downto 0); - data_wen : out std_logic_vector(3 downto 0); - valid_ack : out std_logic_vector(3 downto 0); - time_wen : out std_logic_vector(3 downto 0); - data_f3_out : in std_logic_vector(159 downto 64); - data_f2_out : in std_logic_vector(159 downto 64); - data_f1_out : in std_logic_vector(159 downto 64); - data_f0_out : in std_logic_vector(159 downto 64); - ready_i_0_i_0 : in std_logic_vector(1 to 1); - valid_out_i : in std_logic_vector(1 to 1); - ready_i_0_3 : in std_logic; - ready_i_0_0 : in std_logic; - ready_i_0_2 : in std_logic; - valid_out_3 : in std_logic; - valid_out_0 : in std_logic; - valid_out_2 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_waveform_fifo_arbiter; - -architecture DEF_ARCH of lpp_waveform_fifo_arbiter is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \data_valid_and_ready_3[2]_net_1\, - \data_valid_and_ready_2[2]_net_1\, - \data_valid_and_ready_1[2]_net_1\, - \data_valid_and_ready_0[2]_net_1\, N_863_2, - \data_temp_5_i_a2_0_0[32]_net_1\, N_911, N_863_1, N_863_0, - N_1580_2, \data_valid_and_ready_0[0]_net_1\, - \data_valid_and_ready[1]_net_1\, N_1580_1, N_1580_0, - \data_valid_and_ready_3[0]_net_1\, - \data_valid_and_ready_2[0]_net_1\, - \data_valid_and_ready_1[0]_net_1\, \state[4]_net_1\, - \state_0[4]\, N_857_i, N_857, N_860_i, N_860, - \time_wen_3_i[0]\, \time_wen_3[0]\, N_859_i, N_859, - \data_temp_5_i_0[32]\, N_912_i, N_769, N_864, - \data_temp_5_i_0[33]\, N_770, N_867, - \data_temp_5_i_0[34]\, N_848, N_870, - \data_temp_5_i_0[35]\, N_849, N_873, - \data_temp_5_i_0[36]\, N_850, N_1650, - \data_temp_5_i_0[37]\, N_851, N_1653, - \data_temp_5_i_0[38]\, N_852, N_1656, - \data_temp_5_i_0[39]\, N_853, N_1659, - \data_temp_5_i_0[40]\, N_854, N_1662, - \data_temp_5_i_0[41]\, N_841, N_1665, - \data_temp_5_i_0[42]\, N_842, N_1668, - \data_temp_5_i_0[43]\, N_843, N_897, - \data_valid_and_ready[3]_net_1\, \state_ns_i_i_a2_1[0]\, - \state[2]_net_1\, \state[1]_net_1\, \state[3]_net_1\, - N_239, N_898, N_237, N_1669, N_235, N_1666, N_233, N_1663, - N_231, N_1660, N_229, N_1657, N_227, N_1654, N_225, - N_1651, N_223, N_874, N_221, N_871, N_219, N_868, N_215, - N_865, N_251, N_910, N_909, N_1581, N_249, N_908, N_907, - N_247, N_906, N_905, N_1582, N_245, N_904, N_903, N_1583, - N_243, N_902, N_901, N_241, N_900, N_899, N_863, N_861, - N_1306, \state[0]_net_1\, \data_valid_and_ready[0]_net_1\, - \data_valid_and_ready[2]_net_1\, N_917, N_858, - \data_temp[64]_net_1\, N_1685, \data_temp[65]_net_1\, - N_1686, \data_temp[66]_net_1\, N_1687, - \data_temp[67]_net_1\, N_1688, \data_temp[68]_net_1\, - N_1689, \data_temp[69]_net_1\, N_762, - \data_temp[70]_net_1\, N_763, \data_temp[71]_net_1\, - N_764, \data_temp[72]_net_1\, N_765, - \data_temp[73]_net_1\, N_766, \data_temp[74]_net_1\, - N_767, \data_temp[75]_net_1\, N_768, N_794, N_1731, N_795, - N_1718, N_1681, N_1693, N_1682, N_1694, N_793, N_1730, - N_1680, N_1692, N_916, state_0_sqmuxa_i, N_1580, - \data_temp[123]_net_1\, \data_temp[125]_net_1\, - \data_temp[124]_net_1\, N_1675, N_1676, N_1677, N_1678, - N_1679, N_1683, N_1684, N_1690, N_1691, N_1695, N_1696, - N_1697, N_1698, N_1699, N_1700, N_1701, N_1702, N_1703, - N_1704, N_1705, N_1706, N_1707, N_1708, N_1709, N_1710, - N_1711, N_1712, N_1713, N_1714, N_1715, N_1716, N_1717, - N_1719, N_1720, N_1721, N_1722, N_1723, N_1724, N_1725, - N_1726, N_1727, N_1728, N_1729, N_1732, N_1733, N_1734, - N_1735, N_1736, N_1737, N_1738, N_1739, N_1740, N_729, - N_730, N_731, N_732, N_733, N_734, N_735, N_736, N_737, - N_738, N_739, N_740, N_741, N_742, N_743, N_744, N_745, - N_746, N_747, N_748, N_749, N_750, N_751, N_752, N_753, - N_754, N_755, N_756, N_757, N_758, N_759, N_760, N_761, - N_771, N_772, N_773, N_774, N_775, N_776, N_777, N_778, - N_779, N_780, N_781, N_782, N_783, N_784, N_785, N_786, - N_787, N_788, N_789, N_790, N_791, N_792, N_796, N_797, - N_798, N_799, N_800, N_801, N_802, N_803, N_804, N_805, - N_806, N_807, N_808, N_809, N_810, N_811, N_812, N_813, - N_814, N_815, N_816, N_817, N_818, N_819, N_820, N_821, - N_822, N_823, N_824, N_825, N_826, N_827, N_828, N_829, - N_830, N_831, N_832, N_833, N_834, N_835, N_836, N_837, - N_838, N_839, N_840, N_844, N_845, N_846, N_847, - \data_wen_3[0]\, \time_en_temp[0]_net_1\, \data_wen_3[1]\, - \time_en_temp[1]_net_1\, \data_wen_3[2]\, - \time_en_temp[2]_net_1\, \data_wen_3[3]\, - \time_en_temp[3]_net_1\, \data_selected[127]\, - \data_selected[159]\, N_696, \data_temp[127]_net_1\, - N_728, \data_temp_5[95]\, \data_temp_5[127]\, - \data_temp_5[14]\, \data_temp[46]_net_1\, - \data_temp_5[13]\, \data_temp[45]_net_1\, - \data_temp_5[12]\, \data_temp[44]_net_1\, - \data_temp_5[11]\, \data_temp[43]_net_1\, - \data_temp_5[10]\, \data_temp[42]_net_1\, - \data_temp_5[9]\, \data_temp[41]_net_1\, \data_temp_5[8]\, - \data_temp[40]_net_1\, \data_temp_5[7]\, - \data_temp[39]_net_1\, \data_temp_5[6]\, - \data_temp[38]_net_1\, \data_temp_5[5]\, - \data_temp[37]_net_1\, \data_temp_5[4]\, - \data_temp[36]_net_1\, \data_temp_5[3]\, - \data_temp[35]_net_1\, \data_temp_5[2]\, - \data_temp[34]_net_1\, \data_temp_5[1]\, - \data_temp[33]_net_1\, \data_temp_5[0]\, - \data_temp[32]_net_1\, \data_5[31]\, - \data_temp[31]_net_1\, \data_5[30]\, - \data_temp[30]_net_1\, \data_5[29]\, - \data_temp[29]_net_1\, \data_5[28]\, - \data_temp[28]_net_1\, \data_5[27]\, - \data_temp[27]_net_1\, \data_5[26]\, - \data_temp[26]_net_1\, \data_5[25]\, - \data_temp[25]_net_1\, \data_5[24]\, - \data_temp[24]_net_1\, \data_5[23]\, - \data_temp[23]_net_1\, \data_5[22]\, - \data_temp[22]_net_1\, \data_5[21]\, - \data_temp[21]_net_1\, \data_5[20]\, - \data_temp[20]_net_1\, \data_5[19]\, - \data_temp[19]_net_1\, \data_5[18]\, - \data_temp[18]_net_1\, \data_5[17]\, - \data_temp[17]_net_1\, \data_5[16]\, - \data_temp[16]_net_1\, \data_5[15]\, - \data_temp[15]_net_1\, \data_5[14]\, - \data_temp[14]_net_1\, \data_5[13]\, - \data_temp[13]_net_1\, \data_5[12]\, - \data_temp[12]_net_1\, \data_5[11]\, - \data_temp[11]_net_1\, \data_5[10]\, - \data_temp[10]_net_1\, \data_5[9]\, \data_temp[9]_net_1\, - \data_5[8]\, \data_temp[8]_net_1\, \data_5[7]\, - \data_temp[7]_net_1\, \data_5[6]\, \data_temp[6]_net_1\, - \data_selected[76]\, \data_selected[77]\, - \data_selected[78]\, \data_selected[79]\, - \data_selected[126]\, \data_selected[158]\, N_645, - \data_temp[76]_net_1\, N_646, \data_temp[77]_net_1\, - N_647, \data_temp[78]_net_1\, N_648, - \data_temp[79]_net_1\, N_695, \data_temp[126]_net_1\, - N_727, \data_temp_5[44]\, \data_temp_5[45]\, - \data_temp_5[46]\, \data_temp_5[47]\, \data_temp_5[94]\, - \data_temp_5[126]\, \data_temp_5[31]\, - \data_temp[63]_net_1\, \data_temp_5[30]\, - \data_temp[62]_net_1\, \data_temp_5[29]\, - \data_temp[61]_net_1\, \data_temp_5[28]\, - \data_temp[60]_net_1\, \data_temp_5[27]\, - \data_temp[59]_net_1\, \data_temp_5[26]\, - \data_temp[58]_net_1\, \data_temp_5[25]\, - \data_temp[57]_net_1\, \data_temp_5[24]\, - \data_temp[56]_net_1\, \data_temp_5[23]\, - \data_temp[55]_net_1\, \data_temp_5[22]\, - \data_temp[54]_net_1\, \data_temp_5[21]\, - \data_temp[53]_net_1\, \data_temp_5[20]\, - \data_temp[52]_net_1\, \data_temp_5[19]\, - \data_temp[51]_net_1\, \data_temp_5[18]\, - \data_temp[50]_net_1\, \data_temp_5[17]\, - \data_temp[49]_net_1\, \data_temp_5[16]\, - \data_temp[48]_net_1\, \data_temp_5[15]\, - \data_temp[47]_net_1\, N_928, \data_selected[80]\, - \data_selected[81]\, \data_selected[82]\, - \data_selected[83]\, \data_selected[84]\, - \data_selected[85]\, \data_selected[86]\, - \data_selected[87]\, \data_selected[88]\, - \data_selected[89]\, \data_selected[90]\, - \data_selected[91]\, \data_selected[92]\, - \data_selected[93]\, \data_selected[94]\, - \data_selected[95]\, \data_selected[112]\, - \data_selected[144]\, N_649, \data_temp[80]_net_1\, N_650, - \data_temp[81]_net_1\, N_651, \data_temp[82]_net_1\, - N_652, \data_temp[83]_net_1\, N_653, - \data_temp[84]_net_1\, N_654, \data_temp[85]_net_1\, - N_655, \data_temp[86]_net_1\, N_656, - \data_temp[87]_net_1\, N_657, \data_temp[88]_net_1\, - N_658, \data_temp[89]_net_1\, N_659, - \data_temp[90]_net_1\, N_660, \data_temp[91]_net_1\, - N_661, \data_temp[92]_net_1\, N_662, - \data_temp[93]_net_1\, N_663, \data_temp[94]_net_1\, - N_664, \data_temp[95]_net_1\, N_681, - \data_temp[112]_net_1\, N_713, \data_temp_5[48]\, - \data_temp_5[49]\, \data_temp_5[50]\, \data_temp_5[51]\, - \data_temp_5[52]\, \data_temp_5[53]\, \data_temp_5[54]\, - \data_temp_5[55]\, \data_temp_5[56]\, \data_temp_5[57]\, - \data_temp_5[58]\, \data_temp_5[59]\, \data_temp_5[60]\, - \data_temp_5[61]\, \data_temp_5[62]\, \data_temp_5[63]\, - \data_temp_5[80]\, \data_temp_5[112]\, \data_5[5]\, - \data_temp[5]_net_1\, \data_5[4]\, \data_temp[4]_net_1\, - \data_5[3]\, \data_temp[3]_net_1\, \data_5[2]\, - \data_temp[2]_net_1\, \data_5[1]\, \data_temp[1]_net_1\, - \data_5[0]\, \data_temp[0]_net_1\, \data_selected[108]\, - \data_selected[110]\, \data_selected[140]\, - \data_selected[142]\, N_677, \data_temp[108]_net_1\, - N_679, \data_temp[110]_net_1\, N_709, N_711, - \data_temp_5[76]\, \data_temp_5[78]\, \data_temp_5[108]\, - \data_temp_5[110]\, \data_selected[107]\, - \data_selected[111]\, \data_selected[139]\, - \data_selected[143]\, N_676, \data_temp[107]_net_1\, - N_680, \data_temp[111]_net_1\, N_708, N_712, - \data_temp_5[75]\, \data_temp_5[79]\, \data_temp_5[107]\, - \data_temp_5[111]\, \data_selected[106]\, - \data_selected[113]\, \data_selected[138]\, - \data_selected[145]\, N_675, \data_temp[106]_net_1\, - N_682, \data_temp[113]_net_1\, N_707, N_714, - \data_temp_5[74]\, \data_temp_5[81]\, \data_temp_5[106]\, - \data_temp_5[113]\, \data_selected[105]\, - \data_selected[114]\, \data_selected[137]\, - \data_selected[146]\, N_674, \data_temp[105]_net_1\, - N_683, \data_temp[114]_net_1\, N_706, N_715, - \data_temp_5[73]\, \data_temp_5[82]\, \data_temp_5[105]\, - \data_temp_5[114]\, \data_selected[104]\, - \data_selected[115]\, \data_selected[136]\, - \data_selected[147]\, N_673, \data_temp[104]_net_1\, - N_684, \data_temp[115]_net_1\, N_705, N_716, - \data_temp_5[72]\, \data_temp_5[83]\, \data_temp_5[104]\, - \data_temp_5[115]\, \data_selected[103]\, - \data_selected[116]\, \data_selected[135]\, - \data_selected[148]\, N_672, \data_temp[103]_net_1\, - N_685, \data_temp[116]_net_1\, N_704, N_717, - \data_temp_5[71]\, \data_temp_5[84]\, \data_temp_5[103]\, - \data_temp_5[116]\, \data_selected[102]\, - \data_selected[117]\, \data_selected[134]\, - \data_selected[149]\, N_671, \data_temp[102]_net_1\, - N_686, \data_temp[117]_net_1\, N_703, N_718, - \data_temp_5[70]\, \data_temp_5[85]\, \data_temp_5[102]\, - \data_temp_5[117]\, \data_selected[101]\, - \data_selected[118]\, \data_selected[133]\, - \data_selected[150]\, N_670, \data_temp[101]_net_1\, - N_687, \data_temp[118]_net_1\, N_702, N_719, - \data_temp_5[69]\, \data_temp_5[86]\, \data_temp_5[101]\, - \data_temp_5[118]\, \data_selected[100]\, - \data_selected[119]\, \data_selected[132]\, - \data_selected[151]\, N_669, \data_temp[100]_net_1\, - N_688, \data_temp[119]_net_1\, N_701, N_720, - \data_temp_5[68]\, \data_temp_5[87]\, \data_temp_5[100]\, - \data_temp_5[119]\, \data_selected[99]\, - \data_selected[120]\, \data_selected[131]\, - \data_selected[152]\, N_668, \data_temp[99]_net_1\, N_689, - \data_temp[120]_net_1\, N_700, N_721, \data_temp_5[67]\, - \data_temp_5[88]\, \data_temp_5[99]\, \data_temp_5[120]\, - \data_selected[98]\, \data_selected[121]\, - \data_selected[130]\, \data_selected[153]\, N_667, - \data_temp[98]_net_1\, N_690, \data_temp[121]_net_1\, - N_699, N_722, \data_temp_5[66]\, \data_temp_5[89]\, - \data_temp_5[98]\, \data_temp_5[121]\, - \data_selected[97]\, \data_selected[122]\, - \data_selected[129]\, \data_selected[154]\, N_666, - \data_temp[97]_net_1\, N_691, \data_temp[122]_net_1\, - N_698, N_723, \data_temp_5[65]\, \data_temp_5[90]\, - \data_temp_5[97]\, \data_temp_5[122]\, - \data_selected[96]\, \data_selected[109]\, - \data_selected[128]\, \data_selected[141]\, N_665, - \data_temp[96]_net_1\, N_678, \data_temp[109]_net_1\, - N_697, N_710, \data_temp_5[64]\, \data_temp_5[77]\, - \data_temp_5[96]\, \data_temp_5[109]\, N_929, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \data_temp_RNO_2[65]\ : MX2C - port map(A => data_f2_out(97), B => data_f3_out(97), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_734); - - \data_temp[124]\ : DFN1C0 - port map(D => N_245, CLK => lclk_c, CLR => rstn, Q => - \data_temp[124]_net_1\); - - \data_temp_RNO_4[42]\ : MX2 - port map(A => data_f2_out(74), B => data_f3_out(74), S => - \data_valid_and_ready[2]_net_1\, Y => N_767); - - \data_temp[99]\ : DFN1C0 - port map(D => \data_temp_5[99]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[99]_net_1\); - - \data_temp_RNO_1[76]\ : MX2C - port map(A => N_731, B => N_806, S => N_1580_1, Y => - \data_selected[108]\); - - \data_temp_RNO_0[42]\ : AO1D - port map(A => N_912_i, B => N_842, C => N_1668, Y => - \data_temp_5_i_0[42]\); - - \data[3]\ : DFN1C0 - port map(D => \data_5[3]\, CLK => lclk_c, CLR => rstn, Q - => wdata(3)); - - \data_temp_RNO_2[32]\ : MX2 - port map(A => data_f0_out(64), B => data_f1_out(64), S => - \data_valid_and_ready_0[0]_net_1\, Y => N_769); - - \state_RNITQVJU1[4]\ : OR2 - port map(A => \data_valid_and_ready_0[2]_net_1\, B => N_911, - Y => N_859); - - \data_temp_RNO_2[64]\ : MX2C - port map(A => data_f2_out(96), B => data_f3_out(96), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_747); - - \time_en_temp[1]\ : DFN1E1C0 - port map(D => N_917, CLK => lclk_c, CLR => rstn, E => - state_0_sqmuxa_i, Q => \time_en_temp[1]_net_1\); - - \data_temp[127]\ : DFN1C0 - port map(D => \data_temp_5[127]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[127]_net_1\); - - \time_wen_RNO[1]\ : INV - port map(A => N_857, Y => N_857_i); - - \data_RNO[13]\ : NOR2A - port map(A => \data_temp[13]_net_1\, B => \state[4]_net_1\, - Y => \data_5[13]\); - - \data_temp_RNO_1[86]\ : MX2C - port map(A => N_1725, B => N_802, S => N_1580_2, Y => - \data_selected[118]\); - - \data_temp_RNO_1[73]\ : MX2C - port map(A => N_1740, B => N_817, S => N_1580_2, Y => - \data_selected[105]\); - - \data_temp_RNO_0[103]\ : MX2C - port map(A => \data_temp[103]_net_1\, B => - \data_selected[135]\, S => \state[4]_net_1\, Y => N_704); - - \data_temp_RNO_1[101]\ : MX2C - port map(A => N_1712, B => N_789, S => N_1580_2, Y => - \data_selected[133]\); - - \data_temp_RNO_2[124]\ : MX2 - port map(A => data_f2_out(156), B => data_f3_out(156), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1693); - - \data_temp_RNO_1[96]\ : MX2C - port map(A => N_1721, B => N_798, S => N_1580, Y => - \data_selected[128]\); - - \data_temp_RNO_1[83]\ : MX2C - port map(A => N_1736, B => N_799, S => N_1580_2, Y => - \data_selected[115]\); - - \data_temp[26]\ : DFN1C0 - port map(D => \data_temp_5[26]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[26]_net_1\); - - \data_RNO[17]\ : NOR2A - port map(A => \data_temp[17]_net_1\, B => \state[4]_net_1\, - Y => \data_5[17]\); - - \data_valid_ack[3]\ : DFN1E0C0 - port map(D => N_860_i, CLK => lclk_c, CLR => rstn, E => - N_929, Q => valid_ack(3)); - - \data_temp_RNO_1[39]\ : NOR2 - port map(A => N_911, B => N_764, Y => N_1660); - - \data_temp_RNO_1[93]\ : NOR2 - port map(A => N_912_i, B => N_795, Y => N_901); - - \data_temp[13]\ : DFN1C0 - port map(D => \data_temp_5[13]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[13]_net_1\); - - \data_temp[56]\ : DFN1C0 - port map(D => \data_temp_5[56]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[56]_net_1\); - - \data_temp_RNO_2[127]\ : MX2C - port map(A => data_f2_out(159), B => data_f3_out(159), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1696); - - \data_temp[125]\ : DFN1C0 - port map(D => N_247, CLK => lclk_c, CLR => rstn, Q => - \data_temp[125]_net_1\); - - \data_temp_RNO[65]\ : NOR2 - port map(A => N_863, B => N_666, Y => \data_temp_5[65]\); - - \data_temp_RNO[98]\ : NOR2 - port map(A => N_863, B => N_699, Y => \data_temp_5[98]\); - - \data_RNO[5]\ : NOR2A - port map(A => \data_temp[5]_net_1\, B => \state[4]_net_1\, - Y => \data_5[5]\); - - \data_temp_RNO_2[119]\ : MX2C - port map(A => data_f2_out(151), B => data_f3_out(151), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1702); - - \data_wen[3]\ : DFN1E0P0 - port map(D => \data_wen_3[3]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => data_wen(3)); - - \data_temp[70]\ : DFN1C0 - port map(D => \data_temp_5[70]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[70]_net_1\); - - \data_temp_RNO[39]\ : NOR3 - port map(A => \data_temp_5_i_0[39]\, B => N_1660, C => - N_863_0, Y => N_231); - - \data_temp_RNO[77]\ : NOR2 - port map(A => N_863, B => N_678, Y => \data_temp_5[77]\); - - \state_RNIU3KC[2]\ : NOR2 - port map(A => \state[4]_net_1\, B => \state[2]_net_1\, Y - => N_928); - - \data[13]\ : DFN1C0 - port map(D => \data_5[13]\, CLK => lclk_c, CLR => rstn, Q - => wdata(13)); - - \data_temp_RNO_2[57]\ : MX2C - port map(A => data_f2_out(89), B => data_f3_out(89), S => - \data_valid_and_ready[2]_net_1\, Y => N_754); - - \data_temp[64]\ : DFN1C0 - port map(D => \data_temp_5[64]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[64]_net_1\); - - \data_temp_RNO[93]\ : NOR3 - port map(A => N_902, B => N_901, C => N_1582, Y => N_243); - - \state_RNO_0[4]\ : OR3 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, C - => \state[3]_net_1\, Y => \state_ns_i_i_a2_1[0]\); - - \data_temp_RNO_1[50]\ : MX2C - port map(A => N_761, B => N_836, S => N_1580_0, Y => - \data_selected[82]\); - - \data_temp[6]\ : DFN1C0 - port map(D => \data_temp_5[6]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[6]_net_1\); - - \data[31]\ : DFN1C0 - port map(D => \data_5[31]\, CLK => lclk_c, CLR => rstn, Q - => wdata(31)); - - \data_temp[112]\ : DFN1C0 - port map(D => \data_temp_5[112]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[112]_net_1\); - - \data_temp_RNO[112]\ : NOR2 - port map(A => N_863_1, B => N_713, Y => \data_temp_5[112]\); - - \data_temp[100]\ : DFN1C0 - port map(D => \data_temp_5[100]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[100]_net_1\); - - \data_temp_RNO_2[70]\ : MX2C - port map(A => data_f2_out(102), B => data_f3_out(102), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_739); - - \data_temp_RNO_3[56]\ : MX2C - port map(A => data_f0_out(88), B => data_f1_out(88), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_828); - - \data_temp_RNO_0[37]\ : AO1D - port map(A => N_912_i, B => N_851, C => N_1653, Y => - \data_temp_5_i_0[37]\); - - \data_temp_RNO[36]\ : NOR3 - port map(A => \data_temp_5_i_0[36]\, B => N_1651, C => - N_863_0, Y => N_225); - - \data_temp_RNO_0[59]\ : MX2C - port map(A => \data_temp[91]_net_1\, B => - \data_selected[91]\, S => \state[4]_net_1\, Y => N_660); - - \data_temp_RNO_0[51]\ : MX2C - port map(A => \data_temp[83]_net_1\, B => - \data_selected[83]\, S => \state[4]_net_1\, Y => N_652); - - \data_temp_RNO_3[66]\ : MX2C - port map(A => data_f0_out(98), B => data_f1_out(98), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_824); - - \data_temp_RNO_3[86]\ : MX2C - port map(A => data_f0_out(118), B => data_f1_out(118), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_802); - - \data_temp_RNO_3[49]\ : MX2C - port map(A => data_f0_out(81), B => data_f1_out(81), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_835); - - \data_temp_RNO_3[41]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[73]_net_1\, - Y => N_1665); - - \data_temp_RNO_2[40]\ : MX2 - port map(A => data_f0_out(72), B => data_f1_out(72), S => - \data_valid_and_ready[0]_net_1\, Y => N_854); - - \data_temp_RNO_0[116]\ : MX2C - port map(A => \data_temp[116]_net_1\, B => - \data_selected[148]\, S => \state[4]_net_1\, Y => N_717); - - \data_temp_RNO_1[35]\ : NOR2 - port map(A => N_1688, B => N_911, Y => N_874); - - \data_temp_RNO_3[53]\ : MX2C - port map(A => data_f0_out(85), B => data_f1_out(85), S => - \data_valid_and_ready[0]_net_1\, Y => N_839); - - \data_temp_RNO[49]\ : NOR2 - port map(A => N_863_1, B => N_650, Y => \data_temp_5[49]\); - - \data_temp_RNO_3[63]\ : MX2C - port map(A => data_f0_out(95), B => data_f1_out(95), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_821); - - \data_temp_RNO_3[83]\ : MX2C - port map(A => data_f0_out(115), B => data_f1_out(115), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_799); - - \data_temp_RNO_2[120]\ : MX2C - port map(A => data_f2_out(152), B => data_f3_out(152), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1703); - - \state_RNI02A6[4]\ : CLKINT - port map(A => \state_0[4]\, Y => \state[4]_net_1\); - - \data_temp_RNO_1[52]\ : MX2C - port map(A => N_749, B => N_838, S => N_1580_0, Y => - \data_selected[84]\); - - \data_temp_RNO_1[34]\ : NOR2 - port map(A => N_1687, B => N_911, Y => N_871); - - \state[2]\ : DFN1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[2]_net_1\); - - \data_temp[36]\ : DFN1C0 - port map(D => N_225, CLK => lclk_c, CLR => rstn, Q => - \data_temp[36]_net_1\); - - un5_data_selected_i_i_a2 : OR2B - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_917); - - \data_wen_RNO[0]\ : OR2 - port map(A => \time_en_temp[0]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[0]\); - - \data_temp_RNO_2[72]\ : MX2C - port map(A => data_f2_out(104), B => data_f3_out(104), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1739); - - \data_temp_RNO_1[110]\ : MX2C - port map(A => N_1707, B => N_784, S => N_1580_1, Y => - \data_selected[142]\); - - \data_temp[82]\ : DFN1C0 - port map(D => \data_temp_5[82]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[82]_net_1\); - - \data_temp_RNO[46]\ : NOR2 - port map(A => N_863_0, B => N_647, Y => \data_temp_5[46]\); - - \data_temp[0]\ : DFN1C0 - port map(D => \data_temp_5[0]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[0]_net_1\); - - data_selected_sn_m2_0_o2_2 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_2); - - \data_temp_RNO_2[42]\ : MX2 - port map(A => data_f0_out(74), B => data_f1_out(74), S => - \data_valid_and_ready[0]_net_1\, Y => N_842); - - \data_temp_RNO_1[49]\ : MX2C - port map(A => N_760, B => N_835, S => N_1580_0, Y => - \data_selected[81]\); - - \data_temp_RNO_1[41]\ : NOR2 - port map(A => N_911, B => N_766, Y => N_1666); - - \data_RNO[2]\ : NOR2A - port map(A => \data_temp[2]_net_1\, B => \state[4]_net_1\, - Y => \data_5[2]\); - - \data_temp_RNO_2[86]\ : MX2C - port map(A => data_f2_out(118), B => data_f3_out(118), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1725); - - \data_temp[10]\ : DFN1C0 - port map(D => \data_temp_5[10]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[10]_net_1\); - - \data_temp[111]\ : DFN1C0 - port map(D => \data_temp_5[111]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[111]_net_1\); - - \data_temp_RNO_3[36]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[68]_net_1\, - Y => N_1650); - - \data_temp_RNO_0[55]\ : MX2C - port map(A => \data_temp[87]_net_1\, B => - \data_selected[87]\, S => \state[4]_net_1\, Y => N_656); - - \time_wen[1]\ : DFN1E0P0 - port map(D => N_857_i, CLK => lclk_c, PRE => rstn, E => - N_928, Q => time_wen(1)); - - \data_temp_RNO_1[127]\ : MX2C - port map(A => N_1696, B => N_1684, S => N_1580_0, Y => - \data_selected[159]\); - - \data_temp_RNO[10]\ : NOR2A - port map(A => \data_temp[42]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[10]\); - - \data_temp_RNO_3[45]\ : MX2C - port map(A => data_f0_out(77), B => data_f1_out(77), S => - \data_valid_and_ready[0]_net_1\, Y => N_845); - - \data_temp_RNO_3[108]\ : MX2C - port map(A => data_f0_out(140), B => data_f1_out(140), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_782); - - \data_temp[24]\ : DFN1C0 - port map(D => \data_temp_5[24]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[24]_net_1\); - - \data_temp_RNO_0[115]\ : MX2C - port map(A => \data_temp[115]_net_1\, B => - \data_selected[147]\, S => \state[4]_net_1\, Y => N_716); - - \data_temp_RNO_2[83]\ : MX2C - port map(A => data_f2_out(115), B => data_f3_out(115), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1736); - - \data_temp_RNO_0[54]\ : MX2C - port map(A => \data_temp[86]_net_1\, B => - \data_selected[86]\, S => \state[4]_net_1\, Y => N_655); - - \data_temp_RNO[4]\ : NOR2A - port map(A => \data_temp[36]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[4]\); - - \data_temp[119]\ : DFN1C0 - port map(D => \data_temp_5[119]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[119]_net_1\); - - \data_temp_RNO_3[33]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[65]_net_1\, - Y => N_867); - - \data_temp_RNO_2[66]\ : MX2C - port map(A => data_f2_out(98), B => data_f3_out(98), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_735); - - \data_temp[54]\ : DFN1C0 - port map(D => \data_temp_5[54]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[54]_net_1\); - - \data_temp_RNO_3[44]\ : MX2C - port map(A => data_f0_out(76), B => data_f1_out(76), S => - \data_valid_and_ready[0]_net_1\, Y => N_844); - - \data_temp_RNO[75]\ : NOR2 - port map(A => N_863_1, B => N_676, Y => \data_temp_5[75]\); - - \data_temp[81]\ : DFN1C0 - port map(D => \data_temp_5[81]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[81]_net_1\); - - \data_RNO[11]\ : NOR2A - port map(A => \data_temp[11]_net_1\, B => \state[4]_net_1\, - Y => \data_5[11]\); - - \data_temp_RNO_3[99]\ : MX2C - port map(A => data_f0_out(131), B => data_f1_out(131), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_787); - - \data_temp_RNO_3[91]\ : MX2 - port map(A => data_f0_out(123), B => data_f1_out(123), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_793); - - \state_RNIBMG5L1_1[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_917, Y => N_857); - - \data_temp_RNO[37]\ : NOR3 - port map(A => \data_temp_5_i_0[37]\, B => N_1654, C => - N_863_0, Y => N_227); - - \data_temp_RNO_2[63]\ : MX2C - port map(A => data_f2_out(95), B => data_f3_out(95), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_746); - - \data_RNO[12]\ : NOR2A - port map(A => \data_temp[12]_net_1\, B => \state[4]_net_1\, - Y => \data_5[12]\); - - \data_valid_ack_RNO[0]\ : INV - port map(A => \time_wen_3[0]\, Y => \time_wen_3_i[0]\); - - \data_temp_RNO_3[127]\ : MX2C - port map(A => data_f0_out(159), B => data_f1_out(159), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1684); - - \data_temp_RNO[2]\ : NOR2A - port map(A => \data_temp[34]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[2]\); - - \data_temp_RNO_1[68]\ : MX2C - port map(A => N_737, B => N_826, S => N_1580_2, Y => - \data_selected[100]\); - - \data_temp_RNO_0[120]\ : MX2C - port map(A => \data_temp[120]_net_1\, B => - \data_selected[152]\, S => \state[4]_net_1\, Y => N_721); - - \data_temp_RNO_1[45]\ : MX2C - port map(A => N_756, B => N_845, S => N_1580_0, Y => - \data_selected[77]\); - - \data_temp_RNO_0[98]\ : MX2C - port map(A => \data_temp[98]_net_1\, B => - \data_selected[130]\, S => \state[4]_net_1\, Y => N_699); - - \data_temp_RNO[91]\ : NOR3 - port map(A => N_908, B => N_907, C => N_1581, Y => N_249); - - \data_temp_RNO[115]\ : NOR2 - port map(A => N_863_2, B => N_716, Y => \data_temp_5[115]\); - - \data_temp[76]\ : DFN1C0 - port map(D => \data_temp_5[76]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[76]_net_1\); - - \data_temp_RNO_1[44]\ : MX2C - port map(A => N_755, B => N_844, S => N_1580_0, Y => - \data_selected[76]\); - - \data_RNO[28]\ : NOR2A - port map(A => \data_temp[28]_net_1\, B => \state[4]_net_1\, - Y => \data_5[28]\); - - \data_temp_RNO[68]\ : NOR2 - port map(A => N_863, B => N_669, Y => \data_temp_5[68]\); - - \data_temp_RNO_0[117]\ : MX2C - port map(A => \data_temp[117]_net_1\, B => - \data_selected[149]\, S => \state[4]_net_1\, Y => N_718); - - \data_temp_RNO[92]\ : NOR3 - port map(A => N_900, B => N_899, C => N_1583, Y => N_241); - - \time_en_temp_RNO[2]\ : OR2 - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - N_1580_0, Y => N_858); - - \data_temp_RNO_3[122]\ : MX2C - port map(A => data_f0_out(154), B => data_f1_out(154), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1679); - - \data_temp_RNO_2[50]\ : MX2C - port map(A => data_f2_out(82), B => data_f3_out(82), S => - \data_valid_and_ready[2]_net_1\, Y => N_761); - - \data_temp[88]\ : DFN1C0 - port map(D => \data_temp_5[88]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[88]_net_1\); - - \data[28]\ : DFN1C0 - port map(D => \data_5[28]\, CLK => lclk_c, CLR => rstn, Q - => wdata(28)); - - \data_temp_RNO[20]\ : NOR2A - port map(A => \data_temp[52]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[20]\); - - \data_temp_RNO[63]\ : NOR2 - port map(A => N_863_1, B => N_664, Y => \data_temp_5[63]\); - - \data_temp_RNO[47]\ : NOR2 - port map(A => N_863_0, B => N_648, Y => \data_temp_5[47]\); - - \data_temp_RNO[117]\ : NOR2 - port map(A => N_863_2, B => N_718, Y => \data_temp_5[117]\); - - \data_wen_RNO[1]\ : OR2 - port map(A => \time_en_temp[1]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[1]\); - - \data_temp[93]\ : DFN1C0 - port map(D => N_243, CLK => lclk_c, CLR => rstn, Q => - \data_temp[93]_net_1\); - - \data_temp[49]\ : DFN1C0 - port map(D => \data_temp_5[49]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[49]_net_1\); - - \data_temp_RNO_3[95]\ : MX2C - port map(A => data_f0_out(127), B => data_f1_out(127), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_797); - - \data_temp_RNO_2[109]\ : MX2C - port map(A => data_f2_out(141), B => data_f3_out(141), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1706); - - \data[5]\ : DFN1C0 - port map(D => \data_5[5]\, CLK => lclk_c, CLR => rstn, Q - => wdata(5)); - - \data_temp_RNO_4[41]\ : MX2 - port map(A => data_f2_out(73), B => data_f3_out(73), S => - \data_valid_and_ready[2]_net_1\, Y => N_766); - - \data_temp[34]\ : DFN1C0 - port map(D => N_221, CLK => lclk_c, CLR => rstn, Q => - \data_temp[34]_net_1\); - - \data[16]\ : DFN1C0 - port map(D => \data_5[16]\, CLK => lclk_c, CLR => rstn, Q - => wdata(16)); - - \data_temp_RNO_3[78]\ : MX2C - port map(A => data_f0_out(110), B => data_f1_out(110), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_808); - - \data_temp_RNO_0[49]\ : MX2C - port map(A => \data_temp[81]_net_1\, B => - \data_selected[81]\, S => \state[4]_net_1\, Y => N_650); - - \data_temp_RNO_0[41]\ : AO1D - port map(A => N_912_i, B => N_841, C => N_1665, Y => - \data_temp_5_i_0[41]\); - - \data_temp[62]\ : DFN1C0 - port map(D => \data_temp_5[62]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[62]_net_1\); - - \data_temp_RNO[94]\ : NOR2 - port map(A => N_863_0, B => N_695, Y => \data_temp_5[94]\); - - \data[7]\ : DFN1C0 - port map(D => \data_5[7]\, CLK => lclk_c, CLR => rstn, Q - => wdata(7)); - - \data_temp_RNO_3[114]\ : MX2C - port map(A => data_f0_out(146), B => data_f1_out(146), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_774); - - \data_temp_RNO_2[39]\ : MX2 - port map(A => data_f0_out(71), B => data_f1_out(71), S => - \data_valid_and_ready[0]_net_1\, Y => N_853); - - \data_temp_RNO[122]\ : NOR2 - port map(A => N_863, B => N_723, Y => \data_temp_5[122]\); - - \data_RNO[31]\ : NOR2A - port map(A => \data_temp[31]_net_1\, B => \state[4]_net_1\, - Y => \data_5[31]\); - - \data_temp_RNO_3[94]\ : MX2C - port map(A => data_f0_out(126), B => data_f1_out(126), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_796); - - \data_temp[87]\ : DFN1C0 - port map(D => \data_temp_5[87]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[87]_net_1\); - - \data_temp_RNO_3[126]\ : MX2C - port map(A => data_f0_out(158), B => data_f1_out(158), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1683); - - \data_temp_RNO_0[78]\ : MX2C - port map(A => \data_temp[110]_net_1\, B => - \data_selected[110]\, S => \state[4]_net_1\, Y => N_679); - - \data_temp_RNO_2[52]\ : MX2C - port map(A => data_f2_out(84), B => data_f3_out(84), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_749); - - \data_temp[108]\ : DFN1C0 - port map(D => \data_temp_5[108]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[108]_net_1\); - - \data_temp_RNO_1[112]\ : MX2C - port map(A => N_1709, B => N_772, S => N_1580_1, Y => - \data_selected[144]\); - - \data_temp_RNO_0[106]\ : MX2C - port map(A => \data_temp[106]_net_1\, B => - \data_selected[138]\, S => \state[4]_net_1\, Y => N_707); - - \data_temp_RNO[59]\ : NOR2 - port map(A => N_863_1, B => N_660, Y => \data_temp_5[59]\); - - \data_temp_RNO_0[32]\ : AO1D - port map(A => N_912_i, B => N_769, C => N_864, Y => - \data_temp_5_i_0[32]\); - - \data_temp[61]\ : DFN1C0 - port map(D => \data_temp_5[61]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[61]_net_1\); - - \data_temp_RNO_4[38]\ : MX2 - port map(A => data_f2_out(70), B => data_f3_out(70), S => - \data_valid_and_ready[2]_net_1\, Y => N_763); - - \data_temp[16]\ : DFN1C0 - port map(D => \data_temp_5[16]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[16]_net_1\); - - \data[21]\ : DFN1C0 - port map(D => \data_5[21]\, CLK => lclk_c, CLR => rstn, Q - => wdata(21)); - - \data_temp_RNO_1[36]\ : NOR2 - port map(A => N_1689, B => N_911, Y => N_1651); - - \data_temp_RNO[89]\ : NOR2 - port map(A => N_863, B => N_690, Y => \data_temp_5[89]\); - - \data_temp_RNO[35]\ : NOR3 - port map(A => \data_temp_5_i_0[35]\, B => N_874, C => - N_863_0, Y => N_223); - - \data_temp_RNO[102]\ : NOR2 - port map(A => N_863_2, B => N_703, Y => \data_temp_5[102]\); - - \data_temp_RNO_1[123]\ : NOR2 - port map(A => N_1680, B => N_912_i, Y => N_909); - - \data_temp_RNO_3[110]\ : MX2C - port map(A => data_f0_out(142), B => data_f1_out(142), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_784); - - \data_temp_RNO_2[122]\ : MX2C - port map(A => data_f2_out(154), B => data_f3_out(154), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1691); - - \data_temp_RNO_0[45]\ : MX2C - port map(A => \data_temp[77]_net_1\, B => - \data_selected[77]\, S => \state[4]_net_1\, Y => N_646); - - \data_temp_RNO_2[125]\ : MX2 - port map(A => data_f2_out(157), B => data_f3_out(157), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1694); - - \data[0]\ : DFN1C0 - port map(D => \data_5[0]\, CLK => lclk_c, CLR => rstn, Q - => wdata(0)); - - \data_temp_RNO[56]\ : NOR2 - port map(A => N_863_1, B => N_657, Y => \data_temp_5[56]\); - - \data_temp_RNO_2[35]\ : MX2 - port map(A => data_f0_out(67), B => data_f1_out(67), S => - \data_valid_and_ready[0]_net_1\, Y => N_849); - - \data_valid_ack[0]\ : DFN1E0C0 - port map(D => \time_wen_3_i[0]\, CLK => lclk_c, CLR => rstn, - E => N_929, Q => valid_ack(0)); - - \data_temp_RNO_1[33]\ : NOR2 - port map(A => N_1686, B => N_911, Y => N_868); - - \data_temp_RNO[86]\ : NOR2 - port map(A => N_863_2, B => N_687, Y => \data_temp_5[86]\); - - \data_temp_RNO_1[119]\ : MX2C - port map(A => N_1702, B => N_1676, S => N_1580, Y => - \data_selected[151]\); - - \data_temp_RNO_1[100]\ : MX2C - port map(A => N_1711, B => N_788, S => N_1580, Y => - \data_selected[132]\); - - \data_temp_RNO_1[118]\ : MX2C - port map(A => N_1701, B => N_1675, S => N_1580_2, Y => - \data_selected[150]\); - - GND_i : GND - port map(Y => \GND\); - - \data_temp_RNO_0[44]\ : MX2C - port map(A => \data_temp[76]_net_1\, B => - \data_selected[76]\, S => \state[4]_net_1\, Y => N_645); - - \data_temp_RNO_2[34]\ : MX2 - port map(A => data_f0_out(66), B => data_f1_out(66), S => - \data_valid_and_ready[0]_net_1\, Y => N_848); - - \data_RNO[16]\ : NOR2A - port map(A => \data_temp[16]_net_1\, B => \state[4]_net_1\, - Y => \data_5[16]\); - - \data_temp[74]\ : DFN1C0 - port map(D => \data_temp_5[74]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[74]_net_1\); - - \data_temp[90]\ : DFN1C0 - port map(D => \data_temp_5[90]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[90]_net_1\); - - \data_temp[22]\ : DFN1C0 - port map(D => \data_temp_5[22]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[22]_net_1\); - - \data_temp_RNO_0[56]\ : MX2C - port map(A => \data_temp[88]_net_1\, B => - \data_selected[88]\, S => \state[4]_net_1\, Y => N_657); - - \data_temp_RNO_0[88]\ : MX2C - port map(A => \data_temp[120]_net_1\, B => - \data_selected[120]\, S => \state[4]_net_1\, Y => N_689); - - \data_temp_RNO[78]\ : NOR2 - port map(A => N_863_1, B => N_679, Y => \data_temp_5[78]\); - - \data_temp_RNO_1[67]\ : MX2C - port map(A => N_736, B => N_825, S => N_1580, Y => - \data_selected[99]\); - - \data_temp_RNO[45]\ : NOR2 - port map(A => N_863_0, B => N_646, Y => \data_temp_5[45]\); - - \state_RNIBMG5L1[4]\ : OR2B - port map(A => \state[4]_net_1\, B => N_1580_0, Y => N_912_i); - - \data_temp_RNO_3[46]\ : MX2C - port map(A => data_f0_out(78), B => data_f1_out(78), S => - \data_valid_and_ready[0]_net_1\, Y => N_846); - - \data_temp_RNO_0[112]\ : MX2C - port map(A => \data_temp[112]_net_1\, B => - \data_selected[144]\, S => \state[4]_net_1\, Y => N_713); - - \data_temp[68]\ : DFN1C0 - port map(D => \data_temp_5[68]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[68]_net_1\); - - \time_en_temp[2]\ : DFN1E1C0 - port map(D => N_858, CLK => lclk_c, CLR => rstn, E => - state_0_sqmuxa_i, Q => \time_en_temp[2]_net_1\); - - \data_temp_RNO_2[98]\ : MX2C - port map(A => data_f2_out(130), B => data_f3_out(130), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1723); - - \data_temp_RNO_0[105]\ : MX2C - port map(A => \data_temp[105]_net_1\, B => - \data_selected[137]\, S => \state[4]_net_1\, Y => N_706); - - \data_temp[52]\ : DFN1C0 - port map(D => \data_temp_5[52]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[52]_net_1\); - - \data_temp_RNO_0[97]\ : MX2C - port map(A => \data_temp[97]_net_1\, B => - \data_selected[129]\, S => \state[4]_net_1\, Y => N_698); - - \data_temp_RNO_0[119]\ : MX2C - port map(A => \data_temp[119]_net_1\, B => - \data_selected[151]\, S => \state[4]_net_1\, Y => N_720); - - \data[2]\ : DFN1C0 - port map(D => \data_5[2]\, CLK => lclk_c, CLR => rstn, Q - => wdata(2)); - - \data_temp_RNO[73]\ : NOR2 - port map(A => N_863_2, B => N_674, Y => \data_temp_5[73]\); - - \data_temp[85]\ : DFN1C0 - port map(D => \data_temp_5[85]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[85]_net_1\); - - \data_temp_5_i_a2_0_0[32]\ : OR2A - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - \data_valid_and_ready[3]_net_1\, Y => - \data_temp_5_i_a2_0_0[32]_net_1\); - - \data_valid_and_ready_1[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready_1[2]_net_1\); - - \data_temp_RNO_0[53]\ : MX2C - port map(A => \data_temp[85]_net_1\, B => - \data_selected[85]\, S => \state[4]_net_1\, Y => N_654); - - \data_temp_RNO_3[43]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[75]_net_1\, - Y => N_897); - - \data[22]\ : DFN1C0 - port map(D => \data_5[22]\, CLK => lclk_c, CLR => rstn, Q - => wdata(22)); - - \data_temp_RNO_2[126]\ : MX2C - port map(A => data_f2_out(158), B => data_f3_out(158), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1695); - - \data_temp_RNO[61]\ : NOR2 - port map(A => N_863_1, B => N_662, Y => \data_temp_5[61]\); - - \data_temp_RNO_0[68]\ : MX2C - port map(A => \data_temp[100]_net_1\, B => - \data_selected[100]\, S => \state[4]_net_1\, Y => N_669); - - \data_temp[67]\ : DFN1C0 - port map(D => \data_temp_5[67]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[67]_net_1\); - - \data_temp[21]\ : DFN1C0 - port map(D => \data_temp_5[21]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[21]_net_1\); - - \data_wen[2]\ : DFN1E0P0 - port map(D => \data_wen_3[2]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => data_wen(2)); - - \data_temp[9]\ : DFN1C0 - port map(D => \data_temp_5[9]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[9]_net_1\); - - \data_temp_RNO[62]\ : NOR2 - port map(A => N_863_1, B => N_663, Y => \data_temp_5[62]\); - - \data_temp_RNO[125]\ : NOR3 - port map(A => N_906, B => N_905, C => N_1582, Y => N_247); - - \data_temp_RNO_1[59]\ : MX2C - port map(A => N_742, B => N_831, S => N_1580_1, Y => - \data_selected[91]\); - - \data_temp_RNO_1[51]\ : MX2C - port map(A => N_748, B => N_837, S => N_1580_0, Y => - \data_selected[83]\); - - \data_temp_RNO_1[46]\ : MX2C - port map(A => N_757, B => N_846, S => N_1580_0, Y => - \data_selected[78]\); - - \data_temp[51]\ : DFN1C0 - port map(D => \data_temp_5[51]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[51]_net_1\); - - \data_temp_RNO_2[79]\ : MX2C - port map(A => data_f2_out(111), B => data_f3_out(111), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1732); - - \data_temp_RNO_2[71]\ : MX2C - port map(A => data_f2_out(103), B => data_f3_out(103), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_740); - - \data_temp_RNO_3[77]\ : MX2C - port map(A => data_f0_out(109), B => data_f1_out(109), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_807); - - \data_temp[120]\ : DFN1C0 - port map(D => \data_temp_5[120]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[120]_net_1\); - - \data_temp[106]\ : DFN1C0 - port map(D => \data_temp_5[106]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[106]_net_1\); - - \time_wen[3]\ : DFN1E0P0 - port map(D => N_860, CLK => lclk_c, PRE => rstn, E => N_928, - Q => time_wen(3)); - - \data_temp_RNO_2[49]\ : MX2C - port map(A => data_f2_out(81), B => data_f3_out(81), S => - \data_valid_and_ready[2]_net_1\, Y => N_760); - - \data_temp_RNO_2[41]\ : MX2 - port map(A => data_f0_out(73), B => data_f1_out(73), S => - \data_valid_and_ready[0]_net_1\, Y => N_841); - - \data_temp_RNO[127]\ : NOR2 - port map(A => N_863_0, B => N_728, Y => \data_temp_5[127]\); - - \data_temp_RNO_0[107]\ : MX2C - port map(A => \data_temp[107]_net_1\, B => - \data_selected[139]\, S => \state[4]_net_1\, Y => N_708); - - \data_temp_RNO_0[77]\ : MX2C - port map(A => \data_temp[109]_net_1\, B => - \data_selected[109]\, S => \state[4]_net_1\, Y => N_678); - - \data_temp_RNO_1[43]\ : NOR2 - port map(A => N_911, B => N_768, Y => N_898); - - \data_temp_RNO[57]\ : NOR2 - port map(A => N_863_1, B => N_658, Y => \data_temp_5[57]\); - - \data_temp_RNO[64]\ : NOR2 - port map(A => N_863, B => N_665, Y => \data_temp_5[64]\); - - \data_temp[14]\ : DFN1C0 - port map(D => \data_temp_5[14]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[14]_net_1\); - - \data_temp_RNO[87]\ : NOR2 - port map(A => N_863, B => N_688, Y => \data_temp_5[87]\); - - \data_temp[114]\ : DFN1C0 - port map(D => \data_temp_5[114]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[114]_net_1\); - - \data_temp_RNO_0[124]\ : NOR2 - port map(A => N_1693, B => N_911, Y => N_904); - - \data_temp_RNO[110]\ : NOR2 - port map(A => N_863_1, B => N_711, Y => \data_temp_5[110]\); - - \data_temp_RNO_3[111]\ : MX2C - port map(A => data_f0_out(143), B => data_f1_out(143), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_771); - - \data_temp_RNO_0[121]\ : MX2C - port map(A => \data_temp[121]_net_1\, B => - \data_selected[153]\, S => \state[4]_net_1\, Y => N_722); - - \data_temp_RNO[105]\ : NOR2 - port map(A => N_863_2, B => N_706, Y => \data_temp_5[105]\); - - \data[29]\ : DFN1C0 - port map(D => \data_5[29]\, CLK => lclk_c, CLR => rstn, Q - => wdata(29)); - - \data_temp_RNO_1[78]\ : MX2C - port map(A => N_733, B => N_808, S => N_1580_1, Y => - \data_selected[110]\); - - \data_temp[32]\ : DFN1C0 - port map(D => N_215, CLK => lclk_c, CLR => rstn, Q => - \data_temp[32]_net_1\); - - \data_temp_RNO_0[118]\ : MX2C - port map(A => \data_temp[118]_net_1\, B => - \data_selected[150]\, S => \state[4]_net_1\, Y => N_719); - - \data_temp[28]\ : DFN1C0 - port map(D => \data_temp_5[28]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[28]_net_1\); - - \data_temp_RNO_3[96]\ : MX2C - port map(A => data_f0_out(128), B => data_f1_out(128), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_798); - - \data_temp[117]\ : DFN1C0 - port map(D => \data_temp_5[117]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[117]_net_1\); - - \data_RNO[19]\ : NOR2A - port map(A => \data_temp[19]_net_1\, B => \state[4]_net_1\, - Y => \data_5[19]\); - - \data_temp_RNO_4[37]\ : MX2 - port map(A => data_f2_out(69), B => data_f3_out(69), S => - \data_valid_and_ready[2]_net_1\, Y => N_762); - - data_selected_sn_m2_0_o2 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580); - - \data_temp[58]\ : DFN1C0 - port map(D => \data_temp_5[58]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[58]_net_1\); - - \data_temp_RNO_1[55]\ : MX2C - port map(A => N_752, B => N_827, S => N_1580_0, Y => - \data_selected[87]\); - - \data_temp_RNO_3[104]\ : MX2C - port map(A => data_f0_out(136), B => data_f1_out(136), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_778); - - \data_temp_RNO_1[88]\ : MX2C - port map(A => N_1727, B => N_804, S => N_1580, Y => - \data_selected[120]\); - - \data_temp_RNO[107]\ : NOR2 - port map(A => N_863_1, B => N_708, Y => \data_temp_5[107]\); - - \data[25]\ : DFN1C0 - port map(D => \data_5[25]\, CLK => lclk_c, CLR => rstn, Q - => wdata(25)); - - \data_temp_RNO_3[93]\ : MX2 - port map(A => data_f0_out(125), B => data_f1_out(125), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_795); - - \data_temp_RNO_2[75]\ : MX2C - port map(A => data_f2_out(107), B => data_f3_out(107), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_730); - - \data_valid_and_ready_0[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready_0[2]_net_1\); - - \data_temp_RNO_1[115]\ : MX2C - port map(A => N_1698, B => N_775, S => N_1580_2, Y => - \data_selected[147]\); - - \data_temp[27]\ : DFN1C0 - port map(D => \data_temp_5[27]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[27]_net_1\); - - \data_temp_RNO_1[54]\ : MX2C - port map(A => N_751, B => N_840, S => N_1580_0, Y => - \data_selected[86]\); - - \data_temp_RNO[38]\ : NOR3 - port map(A => \data_temp_5_i_0[38]\, B => N_1657, C => - N_863_0, Y => N_229); - - \data_temp_RNO_2[45]\ : MX2C - port map(A => data_f2_out(77), B => data_f3_out(77), S => - \data_valid_and_ready[2]_net_1\, Y => N_756); - - \data_temp_RNO_1[98]\ : MX2C - port map(A => N_1723, B => N_786, S => N_1580, Y => - \data_selected[130]\); - - \data_temp[31]\ : DFN1C0 - port map(D => \data_temp_5[31]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[31]_net_1\); - - \data_temp_RNO_1[102]\ : MX2C - port map(A => N_1713, B => N_790, S => N_1580_2, Y => - \data_selected[134]\); - - \data_temp[3]\ : DFN1C0 - port map(D => \data_temp_5[3]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[3]_net_1\); - - \data_temp_RNO_2[74]\ : MX2C - port map(A => data_f2_out(106), B => data_f3_out(106), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_729); - - \data_temp[65]\ : DFN1C0 - port map(D => \data_temp_5[65]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[65]_net_1\); - - \data_temp[57]\ : DFN1C0 - port map(D => \data_temp_5[57]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[57]_net_1\); - - \data_temp_RNO_3[115]\ : MX2C - port map(A => data_f0_out(147), B => data_f1_out(147), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_775); - - \data_temp[7]\ : DFN1C0 - port map(D => \data_temp_5[7]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[7]_net_1\); - - \data_temp_RNO[33]\ : NOR3 - port map(A => \data_temp_5_i_0[33]\, B => N_868, C => - N_863_0, Y => N_219); - - \data_temp_RNO_2[44]\ : MX2C - port map(A => data_f2_out(76), B => data_f3_out(76), S => - \data_valid_and_ready[2]_net_1\, Y => N_755); - - \data_temp_RNO_2[118]\ : MX2C - port map(A => data_f2_out(150), B => data_f3_out(150), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1701); - - \data_temp_RNO_1[116]\ : MX2C - port map(A => N_1699, B => N_776, S => N_1580_2, Y => - \data_selected[148]\); - - \data_temp[96]\ : DFN1C0 - port map(D => \data_temp_5[96]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[96]_net_1\); - - \data_temp_RNO_0[87]\ : MX2C - port map(A => \data_temp[119]_net_1\, B => - \data_selected[119]\, S => \state[4]_net_1\, Y => N_688); - - \data_temp[115]\ : DFN1C0 - port map(D => \data_temp_5[115]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[115]_net_1\); - - \data_temp_RNO_3[100]\ : MX2C - port map(A => data_f0_out(132), B => data_f1_out(132), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_788); - - \data[14]\ : DFN1C0 - port map(D => \data_5[14]\, CLK => lclk_c, CLR => rstn, Q - => wdata(14)); - - \data_temp_RNO_2[97]\ : MX2C - port map(A => data_f2_out(129), B => data_f3_out(129), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1722); - - \data_temp_RNO_0[123]\ : NOR2 - port map(A => N_1692, B => N_911, Y => N_910); - - \data_temp_RNO[71]\ : NOR2 - port map(A => N_863_2, B => N_672, Y => \data_temp_5[71]\); - - \data_temp[43]\ : DFN1C0 - port map(D => N_239, CLK => lclk_c, CLR => rstn, Q => - \data_temp[43]_net_1\); - - \data_temp_RNO_0[46]\ : MX2C - port map(A => \data_temp[78]_net_1\, B => - \data_selected[78]\, S => \state[4]_net_1\, Y => N_647); - - \data_temp_RNO_1[60]\ : MX2C - port map(A => N_743, B => N_832, S => N_1580_1, Y => - \data_selected[92]\); - - \data_temp_RNO_1[121]\ : MX2C - port map(A => N_1690, B => N_1678, S => N_1580, Y => - \data_selected[153]\); - - \data_temp_RNO_2[36]\ : MX2 - port map(A => data_f0_out(68), B => data_f1_out(68), S => - \data_valid_and_ready[0]_net_1\, Y => N_850); - - \data_temp_RNO[72]\ : NOR2 - port map(A => N_863_2, B => N_673, Y => \data_temp_5[72]\); - - \data_temp_RNO[116]\ : NOR2 - port map(A => N_863_2, B => N_717, Y => \data_temp_5[116]\); - - \data_temp_RNO_0[90]\ : MX2C - port map(A => \data_temp[122]_net_1\, B => - \data_selected[122]\, S => \state[4]_net_1\, Y => N_691); - - \data_RNO[24]\ : NOR2A - port map(A => \data_temp[24]_net_1\, B => \state[4]_net_1\, - Y => \data_5[24]\); - - \data_temp_RNO_1[109]\ : MX2C - port map(A => N_1706, B => N_783, S => N_1580, Y => - \data_selected[141]\); - - \data_temp_RNO[90]\ : NOR2 - port map(A => N_863, B => N_691, Y => \data_temp_5[90]\); - - \data_temp_RNO[48]\ : NOR2 - port map(A => N_863_0, B => N_649, Y => \data_temp_5[48]\); - - \data_temp_RNO_1[108]\ : MX2C - port map(A => N_1705, B => N_782, S => N_1580_1, Y => - \data_selected[140]\); - - \data_temp[72]\ : DFN1C0 - port map(D => \data_temp_5[72]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[72]_net_1\); - - \data_temp_RNO_2[111]\ : MX2C - port map(A => data_f2_out(143), B => data_f3_out(143), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1708); - - \data_temp_RNO[5]\ : NOR2A - port map(A => \data_temp[37]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[5]\); - - \data_temp_RNO_4[43]\ : MX2 - port map(A => data_f2_out(75), B => data_f3_out(75), S => - \data_valid_and_ready[2]_net_1\, Y => N_768); - - \data_temp_RNO[55]\ : NOR2 - port map(A => N_863_1, B => N_656, Y => \data_temp_5[55]\); - - \data_temp_RNO_0[67]\ : MX2C - port map(A => \data_temp[99]_net_1\, B => - \data_selected[99]\, S => \state[4]_net_1\, Y => N_668); - - \data_temp_RNO_0[43]\ : AO1D - port map(A => N_912_i, B => N_843, C => N_897, Y => - \data_temp_5_i_0[43]\); - - \data_temp[38]\ : DFN1C0 - port map(D => N_229, CLK => lclk_c, CLR => rstn, Q => - \data_temp[38]_net_1\); - - \data_RNO[20]\ : NOR2A - port map(A => \data_temp[20]_net_1\, B => \state[4]_net_1\, - Y => \data_5[20]\); - - \data_temp_RNO[85]\ : NOR2 - port map(A => N_863_2, B => N_686, Y => \data_temp_5[85]\); - - \data_temp_RNO[7]\ : NOR2A - port map(A => \data_temp[39]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[7]\); - - \data_temp_RNO[43]\ : NOR3 - port map(A => \data_temp_5_i_0[43]\, B => N_898, C => - N_863_0, Y => N_239); - - \data_temp[103]\ : DFN1C0 - port map(D => \data_temp_5[103]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[103]_net_1\); - - \data[10]\ : DFN1C0 - port map(D => \data_5[10]\, CLK => lclk_c, CLR => rstn, Q - => wdata(10)); - - \data_temp_RNO_2[33]\ : MX2 - port map(A => data_f0_out(65), B => data_f1_out(65), S => - \data_valid_and_ready_0[0]_net_1\, Y => N_770); - - \data_temp_RNO_3[58]\ : MX2C - port map(A => data_f0_out(90), B => data_f1_out(90), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_830); - - \data_temp_RNO_3[68]\ : MX2C - port map(A => data_f0_out(100), B => data_f1_out(100), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_826); - - \data_temp_RNO_0[102]\ : MX2C - port map(A => \data_temp[102]_net_1\, B => - \data_selected[134]\, S => \state[4]_net_1\, Y => N_703); - - \state[4]\ : DFN1P0 - port map(D => N_861, CLK => lclk_c, PRE => rstn, Q => - \state_0[4]\); - - \data_temp_RNO_3[88]\ : MX2C - port map(A => data_f0_out(120), B => data_f1_out(120), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_804); - - \data_temp_RNO[74]\ : NOR2 - port map(A => N_863_2, B => N_675, Y => \data_temp_5[74]\); - - \data_temp_RNO_2[59]\ : MX2C - port map(A => data_f2_out(91), B => data_f3_out(91), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_742); - - \data_temp_RNO_2[51]\ : MX2C - port map(A => data_f2_out(83), B => data_f3_out(83), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_748); - - \data_temp_RNO_0[109]\ : MX2C - port map(A => \data_temp[109]_net_1\, B => - \data_selected[141]\, S => \state[4]_net_1\, Y => N_710); - - \data_temp_RNO_3[113]\ : MX2C - port map(A => data_f0_out(145), B => data_f1_out(145), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_773); - - \data_temp_RNO_1[62]\ : MX2C - port map(A => N_745, B => N_820, S => N_1580_1, Y => - \data_selected[94]\); - - \data_temp_RNO_1[114]\ : MX2C - port map(A => N_1697, B => N_774, S => N_1580_2, Y => - \data_selected[146]\); - - \data_temp_RNO_0[92]\ : NOR2 - port map(A => N_1731, B => N_911, Y => N_900); - - \data_valid_and_ready[3]\ : NOR2A - port map(A => valid_out_3, B => ready_i_0_3, Y => - \data_valid_and_ready[3]_net_1\); - - \data_temp[37]\ : DFN1C0 - port map(D => N_227, CLK => lclk_c, CLR => rstn, Q => - \data_temp[37]_net_1\); - - \data_temp[71]\ : DFN1C0 - port map(D => \data_temp_5[71]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[71]_net_1\); - - \data_temp_RNO_3[70]\ : MX2C - port map(A => data_f0_out(102), B => data_f1_out(102), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_814); - - \data_temp_RNO_0[39]\ : AO1D - port map(A => N_912_i, B => N_853, C => N_1659, Y => - \data_temp_5_i_0[39]\); - - \data_temp[25]\ : DFN1C0 - port map(D => \data_temp_5[25]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[25]_net_1\); - - \data_temp_RNO[9]\ : NOR2A - port map(A => \data_temp[41]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[9]\); - - \state_RNIT8OCE2_4[4]\ : NOR2 - port map(A => \data_temp_5_i_a2_0_0[32]_net_1\, B => N_911, - Y => N_863); - - \data_RNO[25]\ : NOR2A - port map(A => \data_temp[25]_net_1\, B => \state[4]_net_1\, - Y => \data_5[25]\); - - \data_temp_RNO_0[70]\ : MX2C - port map(A => \data_temp[102]_net_1\, B => - \data_selected[102]\, S => \state[4]_net_1\, Y => N_671); - - \data_temp[55]\ : DFN1C0 - port map(D => \data_temp_5[55]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[55]_net_1\); - - \data_temp_RNO_1[77]\ : MX2C - port map(A => N_732, B => N_807, S => N_1580, Y => - \data_selected[109]\); - - \data_temp_RNO_2[88]\ : MX2C - port map(A => data_f2_out(120), B => data_f3_out(120), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1727); - - \data_temp_RNO_2[113]\ : MX2C - port map(A => data_f2_out(145), B => data_f3_out(145), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1710); - - \data_temp_RNO_3[38]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[70]_net_1\, - Y => N_1656); - - \data_temp[40]\ : DFN1C0 - port map(D => N_233, CLK => lclk_c, CLR => rstn, Q => - \data_temp[40]_net_1\); - - \data_temp_RNO[120]\ : NOR2 - port map(A => N_863, B => N_721, Y => \data_temp_5[120]\); - - \data_temp_RNO_1[87]\ : MX2C - port map(A => N_1726, B => N_803, S => N_1580, Y => - \data_selected[119]\); - - \data_temp[12]\ : DFN1C0 - port map(D => \data_temp_5[12]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[12]_net_1\); - - \data_temp_RNO_2[55]\ : MX2C - port map(A => data_f2_out(87), B => data_f3_out(87), S => - \data_valid_and_ready[2]_net_1\, Y => N_752); - - \data_temp_RNO_3[72]\ : MX2C - port map(A => data_f0_out(104), B => data_f1_out(104), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_816); - - \data_wen[1]\ : DFN1E0P0 - port map(D => \data_wen_3[1]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => data_wen(1)); - - \data_temp_RNO[19]\ : NOR2A - port map(A => \data_temp[51]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[19]\); - - \data_temp[94]\ : DFN1C0 - port map(D => \data_temp_5[94]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[94]_net_1\); - - \data_temp[78]\ : DFN1C0 - port map(D => \data_temp_5[78]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[78]_net_1\); - - \data_temp_RNO_2[68]\ : MX2C - port map(A => data_f2_out(100), B => data_f3_out(100), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_737); - - \data_temp_RNO_3[101]\ : MX2C - port map(A => data_f0_out(133), B => data_f1_out(133), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_789); - - \data_temp_RNO_2[54]\ : MX2C - port map(A => data_f2_out(86), B => data_f3_out(86), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_751); - - \data_temp_RNO_1[97]\ : MX2C - port map(A => N_1722, B => N_785, S => N_1580, Y => - \data_selected[129]\); - - \data_temp_RNO_0[72]\ : MX2C - port map(A => \data_temp[104]_net_1\, B => - \data_selected[104]\, S => \state[4]_net_1\, Y => N_673); - - \data_temp_RNO_0[35]\ : AO1D - port map(A => N_912_i, B => N_849, C => N_873, Y => - \data_temp_5_i_0[35]\); - - \data_RNO[7]\ : NOR2A - port map(A => \data_temp[7]_net_1\, B => \state[4]_net_1\, - Y => \data_5[7]\); - - \data_temp_RNO[31]\ : NOR2A - port map(A => \data_temp[63]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[31]\); - - \data_temp_RNO_0[108]\ : MX2C - port map(A => \data_temp[108]_net_1\, B => - \data_selected[140]\, S => \state[4]_net_1\, Y => N_709); - - \data[27]\ : DFN1C0 - port map(D => \data_5[27]\, CLK => lclk_c, CLR => rstn, Q - => wdata(27)); - - \data_temp[5]\ : DFN1C0 - port map(D => \data_temp_5[5]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[5]_net_1\); - - \data_temp_RNO[32]\ : NOR3 - port map(A => \data_temp_5_i_0[32]\, B => N_865, C => - N_863_0, Y => N_215); - - \data_temp_RNO[16]\ : NOR2A - port map(A => \data_temp[48]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[16]\); - - \data_temp_RNO_0[34]\ : AO1D - port map(A => N_912_i, B => N_848, C => N_870, Y => - \data_temp_5_i_0[34]\); - - \data_temp_RNO[100]\ : NOR2 - port map(A => N_863, B => N_701, Y => \data_temp_5[100]\); - - \state[1]\ : DFN1C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[1]_net_1\); - - \data_temp_RNIVP6OE2[125]\ : AO1D - port map(A => \state[4]_net_1\, B => \data_temp[125]_net_1\, - C => N_863_0, Y => N_1582); - - \data_temp[102]\ : DFN1C0 - port map(D => \data_temp_5[102]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[102]_net_1\); - - \data_temp_RNO_1[56]\ : MX2C - port map(A => N_753, B => N_828, S => N_1580_0, Y => - \data_selected[88]\); - - \data_temp[77]\ : DFN1C0 - port map(D => \data_temp_5[77]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[77]_net_1\); - - \data_temp[11]\ : DFN1C0 - port map(D => \data_temp_5[11]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[11]_net_1\); - - \data_temp[89]\ : DFN1C0 - port map(D => \data_temp_5[89]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[89]_net_1\); - - \data_RNO[0]\ : NOR2A - port map(A => \data_temp[0]_net_1\, B => \state[4]_net_1\, - Y => \data_5[0]\); - - \data_temp_RNO_4[32]\ : MX2 - port map(A => data_f2_out(64), B => data_f3_out(64), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1685); - - \data_temp_RNO[118]\ : NOR2 - port map(A => N_863, B => N_719, Y => \data_temp_5[118]\); - - \data_temp_RNO_2[76]\ : MX2C - port map(A => data_f2_out(108), B => data_f3_out(108), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_731); - - \data_temp_RNO_0[80]\ : MX2C - port map(A => \data_temp[112]_net_1\, B => - \data_selected[112]\, S => \state[4]_net_1\, Y => N_681); - - \data_temp_RNO_1[105]\ : MX2C - port map(A => N_1716, B => N_779, S => N_1580_2, Y => - \data_selected[137]\); - - \data_temp[35]\ : DFN1C0 - port map(D => N_223, CLK => lclk_c, CLR => rstn, Q => - \data_temp[35]_net_1\); - - \data_temp_RNO_2[90]\ : MX2C - port map(A => data_f2_out(122), B => data_f3_out(122), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1729); - - \data_temp_RNO_2[114]\ : MX2C - port map(A => data_f2_out(146), B => data_f3_out(146), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1697); - - data_selected_sn_m2_0_o2_1 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_1); - - \data_temp_RNO_2[46]\ : MX2C - port map(A => data_f2_out(78), B => data_f3_out(78), S => - \data_valid_and_ready[2]_net_1\, Y => N_757); - - \data_valid_and_ready_2[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready_2[0]_net_1\); - - \data_temp_RNO_1[53]\ : MX2C - port map(A => N_750, B => N_839, S => N_1580_0, Y => - \data_selected[85]\); - - \data_temp_RNO[34]\ : NOR3 - port map(A => \data_temp_5_i_0[34]\, B => N_871, C => - N_863_0, Y => N_221); - - \data_temp_RNO[0]\ : NOR2A - port map(A => \data_temp[32]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[0]\); - - \state_RNIM4O5V[4]\ : OR2A - port map(A => \state[4]_net_1\, B => - \data_valid_and_ready_0[0]_net_1\, Y => \time_wen_3[0]\); - - \data_temp_RNO[41]\ : NOR3 - port map(A => \data_temp_5_i_0[41]\, B => N_1666, C => - N_863_0, Y => N_235); - - \data_temp_RNO_3[105]\ : MX2C - port map(A => data_f0_out(137), B => data_f1_out(137), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_779); - - \data[8]\ : DFN1C0 - port map(D => \data_5[8]\, CLK => lclk_c, CLR => rstn, Q - => wdata(8)); - - \data_temp_RNO_2[73]\ : MX2C - port map(A => data_f2_out(105), B => data_f3_out(105), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1740); - - state_0_sqmuxa_i_0_o2_0_a2 : NOR2 - port map(A => \data_valid_and_ready[3]_net_1\, B => N_916, - Y => N_1306); - - \data_temp_RNO_2[108]\ : MX2C - port map(A => data_f2_out(140), B => data_f3_out(140), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1705); - - \data_temp_RNO[60]\ : NOR2 - port map(A => N_863_1, B => N_661, Y => \data_temp_5[60]\); - - \data_temp_RNO_1[106]\ : MX2C - port map(A => N_1717, B => N_780, S => N_1580_1, Y => - \data_selected[138]\); - - \data_temp_RNO[42]\ : NOR3 - port map(A => \data_temp_5_i_0[42]\, B => N_1669, C => - N_863_0, Y => N_237); - - \data_temp_RNO_2[43]\ : MX2 - port map(A => data_f0_out(75), B => data_f1_out(75), S => - \data_valid_and_ready[0]_net_1\, Y => N_843); - - \data_RNO[4]\ : NOR2A - port map(A => \data_temp[4]_net_1\, B => \state[4]_net_1\, - Y => \data_5[4]\); - - \data_temp_RNO_3[57]\ : MX2C - port map(A => data_f0_out(89), B => data_f1_out(89), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_829); - - \data_temp_RNO[126]\ : NOR2 - port map(A => N_863_0, B => N_727, Y => \data_temp_5[126]\); - - \data_temp_RNO_0[60]\ : MX2C - port map(A => \data_temp[92]_net_1\, B => - \data_selected[92]\, S => \state[4]_net_1\, Y => N_661); - - \data_temp_RNO_3[67]\ : MX2C - port map(A => data_f0_out(99), B => data_f1_out(99), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_825); - - \data_temp_RNO_2[117]\ : MX2C - port map(A => data_f2_out(149), B => data_f3_out(149), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1700); - - \data_temp_RNO_3[87]\ : MX2C - port map(A => data_f0_out(119), B => data_f1_out(119), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_803); - - \data_temp_RNO[58]\ : NOR2 - port map(A => N_863_1, B => N_659, Y => \data_temp_5[58]\); - - \data_temp[2]\ : DFN1C0 - port map(D => \data_temp_5[2]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[2]_net_1\); - - \data_temp_RNO[29]\ : NOR2A - port map(A => \data_temp[61]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[29]\); - - \data_temp[18]\ : DFN1C0 - port map(D => \data_temp_5[18]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[18]_net_1\); - - \data_temp_RNO_0[82]\ : MX2C - port map(A => \data_temp[114]_net_1\, B => - \data_selected[114]\, S => \state[4]_net_1\, Y => N_683); - - \data_temp_RNO[88]\ : NOR2 - port map(A => N_863, B => N_689, Y => \data_temp_5[88]\); - - \data_temp_RNO_2[92]\ : MX2 - port map(A => data_f2_out(124), B => data_f3_out(124), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1731); - - \data_temp_RNO[8]\ : NOR2A - port map(A => \data_temp[40]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[8]\); - - \data_temp[101]\ : DFN1C0 - port map(D => \data_temp_5[101]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[101]_net_1\); - - \data_temp_RNO_2[101]\ : MX2C - port map(A => data_f2_out(133), B => data_f3_out(133), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1712); - - \data_temp_RNO[53]\ : NOR2 - port map(A => N_863_1, B => N_654, Y => \data_temp_5[53]\); - - \data_temp_RNO[44]\ : NOR2 - port map(A => N_863_0, B => N_645, Y => \data_temp_5[44]\); - - \data_temp_RNO[83]\ : NOR2 - port map(A => N_863_2, B => N_684, Y => \data_temp_5[83]\); - - \time_en_temp[0]\ : DFN1E1C0 - port map(D => \data_valid_and_ready[0]_net_1\, CLK => - lclk_c, CLR => rstn, E => state_0_sqmuxa_i, Q => - \time_en_temp[0]_net_1\); - - \data_temp_RNO[26]\ : NOR2A - port map(A => \data_temp[58]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[26]\); - - \data_temp[126]\ : DFN1C0 - port map(D => \data_temp_5[126]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[126]_net_1\); - - \data_temp_RNO[106]\ : NOR2 - port map(A => N_863_2, B => N_707, Y => \data_temp_5[106]\); - - \data_temp[17]\ : DFN1C0 - port map(D => \data_temp_5[17]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[17]_net_1\); - - \data_temp[109]\ : DFN1C0 - port map(D => \data_temp_5[109]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[109]_net_1\); - - \data_temp_RNO_0[62]\ : MX2C - port map(A => \data_temp[94]_net_1\, B => - \data_selected[94]\, S => \state[4]_net_1\, Y => N_663); - - \data_RNO[23]\ : NOR2A - port map(A => \data_temp[23]_net_1\, B => \state[4]_net_1\, - Y => \data_5[23]\); - - \data[6]\ : DFN1C0 - port map(D => \data_5[6]\, CLK => lclk_c, CLR => rstn, Q - => wdata(6)); - - \data_temp_RNO[17]\ : NOR2A - port map(A => \data_temp[49]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[17]\); - - un23_data_selected_i_a2 : OR2A - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - N_1580_0, Y => N_916); - - \data_temp_RNO_2[87]\ : MX2C - port map(A => data_f2_out(119), B => data_f3_out(119), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1726); - - \data_temp_RNO[114]\ : NOR2 - port map(A => N_863_2, B => N_715, Y => \data_temp_5[114]\); - - \data_temp_RNO_3[103]\ : MX2C - port map(A => data_f0_out(135), B => data_f1_out(135), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_791); - - \data_temp_RNO_1[70]\ : MX2C - port map(A => N_739, B => N_814, S => N_1580_2, Y => - \data_selected[102]\); - - \data_temp[75]\ : DFN1C0 - port map(D => \data_temp_5[75]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[75]_net_1\); - - \data_temp_RNO_3[37]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[69]_net_1\, - Y => N_1653); - - \data_temp_RNO_1[38]\ : NOR2 - port map(A => N_911, B => N_763, Y => N_1657); - - \data_temp_RNO_1[104]\ : MX2C - port map(A => N_1715, B => N_778, S => N_1580_2, Y => - \data_selected[136]\); - - \data_temp[46]\ : DFN1C0 - port map(D => \data_temp_5[46]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[46]_net_1\); - - \data_temp_RNO[111]\ : NOR2 - port map(A => N_863_2, B => N_712, Y => \data_temp_5[111]\); - - \data_temp_RNO_2[110]\ : MX2C - port map(A => data_f2_out(142), B => data_f3_out(142), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1707); - - \data_temp[69]\ : DFN1C0 - port map(D => \data_temp_5[69]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[69]_net_1\); - - \data_temp_RNO_1[80]\ : MX2C - port map(A => N_1733, B => N_810, S => N_1580_1, Y => - \data_selected[112]\); - - \data_temp_RNO_2[67]\ : MX2C - port map(A => data_f2_out(99), B => data_f3_out(99), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_736); - - \data_RNO[27]\ : NOR2A - port map(A => \data_temp[27]_net_1\, B => \state[4]_net_1\, - Y => \data_5[27]\); - - \data_temp_RNO[6]\ : NOR2A - port map(A => \data_temp[38]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[6]\); - - \data_temp_RNO_0[126]\ : MX2C - port map(A => \data_temp[126]_net_1\, B => - \data_selected[158]\, S => \state[4]_net_1\, Y => N_727); - - \data_temp_RNO_1[90]\ : MX2C - port map(A => N_1729, B => N_792, S => N_1580, Y => - \data_selected[122]\); - - \data[23]\ : DFN1C0 - port map(D => \data_5[23]\, CLK => lclk_c, CLR => rstn, Q - => wdata(23)); - - \data_temp_RNO_2[103]\ : MX2C - port map(A => data_f2_out(135), B => data_f3_out(135), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1714); - - \data_temp_RNO_1[72]\ : MX2C - port map(A => N_1739, B => N_816, S => N_1580_2, Y => - \data_selected[104]\); - - \data_temp_RNO_0[58]\ : MX2C - port map(A => \data_temp[90]_net_1\, B => - \data_selected[90]\, S => \state[4]_net_1\, Y => N_659); - - \data_temp_RNO_1[117]\ : MX2C - port map(A => N_1700, B => N_777, S => N_1580_2, Y => - \data_selected[149]\); - - \data_temp[4]\ : DFN1C0 - port map(D => \data_temp_5[4]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[4]_net_1\); - - \state_RNIBMG5L1_0[4]\ : OR2A - port map(A => \state[4]_net_1\, B => N_1580_0, Y => N_911); - - \data_wen_RNO[2]\ : OR2 - port map(A => \time_en_temp[2]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[2]\); - - \data_temp_RNO_3[48]\ : MX2C - port map(A => data_f0_out(80), B => data_f1_out(80), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_834); - - \data_temp[92]\ : DFN1C0 - port map(D => N_241, CLK => lclk_c, CLR => rstn, Q => - \data_temp[92]_net_1\); - - \data_temp_RNO_2[56]\ : MX2C - port map(A => data_f2_out(88), B => data_f3_out(88), S => - \data_valid_and_ready[2]_net_1\, Y => N_753); - - \data_temp_RNO[70]\ : NOR2 - port map(A => N_863_2, B => N_671, Y => \data_temp_5[70]\); - - \data_temp_RNO_1[82]\ : MX2C - port map(A => N_1735, B => N_812, S => N_1580_2, Y => - \data_selected[114]\); - - \data_RNO[18]\ : NOR2A - port map(A => \data_temp[18]_net_1\, B => \state[4]_net_1\, - Y => \data_5[18]\); - - \time_wen[0]\ : DFN1E0P0 - port map(D => \time_wen_3[0]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => time_wen(0)); - - \data_temp_RNO_1[120]\ : MX2C - port map(A => N_1703, B => N_1677, S => N_1580, Y => - \data_selected[152]\); - - \data_temp_RNO_0[36]\ : AO1D - port map(A => N_912_i, B => N_850, C => N_1650, Y => - \data_temp_5_i_0[36]\); - - \data_temp_RNO_2[53]\ : MX2C - port map(A => data_f2_out(85), B => data_f3_out(85), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_750); - - \data_temp_RNO_1[69]\ : MX2C - port map(A => N_738, B => N_813, S => N_1580_2, Y => - \data_selected[101]\); - - \data_temp_RNO_1[61]\ : MX2C - port map(A => N_744, B => N_833, S => N_1580_1, Y => - \data_selected[93]\); - - \state_RNIV3KC[3]\ : NOR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => N_929); - - \state[0]\ : DFN1C0 - port map(D => \state[1]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[0]_net_1\); - - \data_temp_RNO[27]\ : NOR2A - port map(A => \data_temp[59]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[27]\); - - \data_temp_RNO_1[92]\ : NOR2 - port map(A => N_912_i, B => N_794, Y => N_899); - - \data_temp_RNO_0[99]\ : MX2C - port map(A => \data_temp[99]_net_1\, B => - \data_selected[131]\, S => \state[4]_net_1\, Y => N_700); - - \data_temp_RNO_0[91]\ : NOR2 - port map(A => N_1730, B => N_911, Y => N_908); - - \data_temp[15]\ : DFN1C0 - port map(D => \data_temp_5[15]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[15]_net_1\); - - \data_temp_RNO[119]\ : NOR2 - port map(A => N_863, B => N_720, Y => \data_temp_5[119]\); - - \data_RNO[1]\ : NOR2A - port map(A => \data_temp[1]_net_1\, B => \state[4]_net_1\, - Y => \data_5[1]\); - - \data_temp_RNO_3[117]\ : MX2C - port map(A => data_f0_out(149), B => data_f1_out(149), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_777); - - \state_RNIT8OCE2_0[4]\ : OR3B - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - \data_valid_and_ready[3]_net_1\, C => N_911, Y => N_860); - - \data_temp_RNO_0[33]\ : AO1D - port map(A => N_912_i, B => N_770, C => N_867, Y => - \data_temp_5_i_0[33]\); - - \data_temp[91]\ : DFN1C0 - port map(D => N_249, CLK => lclk_c, CLR => rstn, Q => - \data_temp[91]_net_1\); - - \data_temp_RNO_0[125]\ : NOR2 - port map(A => N_1694, B => N_911, Y => N_906); - - \data_temp_RNO_0[110]\ : MX2C - port map(A => \data_temp[110]_net_1\, B => - \data_selected[142]\, S => \state[4]_net_1\, Y => N_711); - - \state_RNIT8OCE2[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_1306, Y => - state_0_sqmuxa_i); - - \data_temp_RNO_1[48]\ : MX2C - port map(A => N_759, B => N_834, S => N_1580_0, Y => - \data_selected[80]\); - - \data_temp_RNO[15]\ : NOR2A - port map(A => \data_temp[47]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[15]\); - - \data[18]\ : DFN1C0 - port map(D => \data_5[18]\, CLK => lclk_c, CLR => rstn, Q - => wdata(18)); - - \data_temp[29]\ : DFN1C0 - port map(D => \data_temp_5[29]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[29]_net_1\); - - \data_temp_RNO_3[50]\ : MX2C - port map(A => data_f0_out(82), B => data_f1_out(82), S => - \data_valid_and_ready[0]_net_1\, Y => N_836); - - \data_temp[110]\ : DFN1C0 - port map(D => \data_temp_5[110]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[110]_net_1\); - - data_selected_sn_m2_0_o2_0 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_0); - - \data_temp_RNO[51]\ : NOR2 - port map(A => N_863_1, B => N_652, Y => \data_temp_5[51]\); - - \data_temp_RNO[113]\ : NOR2 - port map(A => N_863_2, B => N_714, Y => \data_temp_5[113]\); - - \data_temp_RNO_3[60]\ : MX2C - port map(A => data_f0_out(92), B => data_f1_out(92), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_832); - - \data_temp[123]\ : DFN1C0 - port map(D => N_251, CLK => lclk_c, CLR => rstn, Q => - \data_temp[123]_net_1\); - - \data_temp_RNO_3[80]\ : MX2C - port map(A => data_f0_out(112), B => data_f1_out(112), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_810); - - \data_temp_RNO_2[104]\ : MX2C - port map(A => data_f2_out(136), B => data_f3_out(136), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1715); - - \data_temp_RNO[81]\ : NOR2 - port map(A => N_863_2, B => N_682, Y => \data_temp_5[81]\); - - \data_temp_RNO[1]\ : NOR2A - port map(A => \data_temp[33]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[1]\); - - \data_temp[59]\ : DFN1C0 - port map(D => \data_temp_5[59]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[59]_net_1\); - - \data_temp_RNO[52]\ : NOR2 - port map(A => N_863_1, B => N_653, Y => \data_temp_5[52]\); - - \data_temp_RNO[82]\ : NOR2 - port map(A => N_863_2, B => N_683, Y => \data_temp_5[82]\); - - \data_temp_RNO[108]\ : NOR2 - port map(A => N_863_1, B => N_709, Y => \data_temp_5[108]\); - - \data_temp_RNO_3[112]\ : MX2C - port map(A => data_f0_out(144), B => data_f1_out(144), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_772); - - \data_temp_RNO_3[79]\ : MX2C - port map(A => data_f0_out(111), B => data_f1_out(111), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_809); - - \data_temp_RNO_3[71]\ : MX2C - port map(A => data_f0_out(103), B => data_f1_out(103), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_815); - - \data_temp[44]\ : DFN1C0 - port map(D => \data_temp_5[44]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[44]_net_1\); - - \data_temp_RNO_1[65]\ : MX2C - port map(A => N_734, B => N_823, S => N_1580, Y => - \data_selected[97]\); - - \data_temp_RNO_2[107]\ : MX2C - port map(A => data_f2_out(139), B => data_f3_out(139), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1704); - - \data_temp_RNO_3[98]\ : MX2C - port map(A => data_f0_out(130), B => data_f1_out(130), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_786); - - \data_temp_RNO_0[95]\ : MX2C - port map(A => \data_temp[127]_net_1\, B => - \data_selected[127]\, S => \state[4]_net_1\, Y => N_696); - - \data_temp_RNO_0[79]\ : MX2C - port map(A => \data_temp[111]_net_1\, B => - \data_selected[111]\, S => \state[4]_net_1\, Y => N_680); - - \data_temp_RNO_0[71]\ : MX2C - port map(A => \data_temp[103]_net_1\, B => - \data_selected[103]\, S => \state[4]_net_1\, Y => N_672); - - \data_valid_ack_RNO[3]\ : INV - port map(A => N_860, Y => N_860_i); - - \data_temp_RNO_3[52]\ : MX2C - port map(A => data_f0_out(84), B => data_f1_out(84), S => - \data_valid_and_ready[0]_net_1\, Y => N_838); - - \data_temp[98]\ : DFN1C0 - port map(D => \data_temp_5[98]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[98]_net_1\); - - \data_temp_RNO[54]\ : NOR2 - port map(A => N_863_1, B => N_655, Y => \data_temp_5[54]\); - - \data_valid_and_ready_1[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready_1[0]_net_1\); - - \data_temp_RNO_3[62]\ : MX2C - port map(A => data_f0_out(94), B => data_f1_out(94), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_820); - - \data_temp_RNO_1[37]\ : NOR2 - port map(A => N_911, B => N_762, Y => N_1654); - - \data_temp_RNO_3[82]\ : MX2C - port map(A => data_f0_out(114), B => data_f1_out(114), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_812); - - \data_temp_RNO_1[64]\ : MX2C - port map(A => N_747, B => N_822, S => N_1580, Y => - \data_selected[96]\); - - \data_temp_RNO[84]\ : NOR2 - port map(A => N_863_2, B => N_685, Y => \data_temp_5[84]\); - - \data_temp_RNO_2[80]\ : MX2C - port map(A => data_f2_out(112), B => data_f3_out(112), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1733); - - \data_temp_RNO_0[94]\ : MX2C - port map(A => \data_temp[126]_net_1\, B => - \data_selected[126]\, S => \state[4]_net_1\, Y => N_695); - - \data_temp_RNO_0[127]\ : MX2C - port map(A => \data_temp[127]_net_1\, B => - \data_selected[159]\, S => \state[4]_net_1\, Y => N_728); - - \data_temp[83]\ : DFN1C0 - port map(D => \data_temp_5[83]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[83]_net_1\); - - \data_temp_RNO_3[116]\ : MX2C - port map(A => data_f0_out(148), B => data_f1_out(148), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_776); - - \data[4]\ : DFN1C0 - port map(D => \data_5[4]\, CLK => lclk_c, CLR => rstn, Q - => wdata(4)); - - \data[11]\ : DFN1C0 - port map(D => \data_5[11]\, CLK => lclk_c, CLR => rstn, Q - => wdata(11)); - - \data_temp_RNO[124]\ : NOR3 - port map(A => N_904, B => N_903, C => N_1583, Y => N_245); - - \data_valid_and_ready_3[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready_3[0]_net_1\); - - \data_RNO[21]\ : NOR2A - port map(A => \data_temp[21]_net_1\, B => \state[4]_net_1\, - Y => \data_5[21]\); - - \data_temp_RNO_4[39]\ : MX2 - port map(A => data_f2_out(71), B => data_f3_out(71), S => - \data_valid_and_ready[2]_net_1\, Y => N_764); - - \data_temp[97]\ : DFN1C0 - port map(D => \data_temp_5[97]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[97]_net_1\); - - \data_RNO[22]\ : NOR2A - port map(A => \data_temp[22]_net_1\, B => \state[4]_net_1\, - Y => \data_5[22]\); - - \data_temp_RNO_2[60]\ : MX2C - port map(A => data_f2_out(92), B => data_f3_out(92), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_743); - - \data_temp_RNO[30]\ : NOR2A - port map(A => \data_temp[62]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[30]\); - - \data_temp_RNO[25]\ : NOR2A - port map(A => \data_temp[57]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[25]\); - - \data_temp_RNO[121]\ : NOR2 - port map(A => N_863, B => N_722, Y => \data_temp_5[121]\); - - \time_en_temp[3]\ : DFN1E1C0 - port map(D => N_916, CLK => lclk_c, CLR => rstn, E => - state_0_sqmuxa_i, Q => \time_en_temp[3]_net_1\); - - \data_temp_RNO_3[75]\ : MX2C - port map(A => data_f0_out(107), B => data_f1_out(107), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_819); - - \data_temp_RNO_3[124]\ : MX2 - port map(A => data_f0_out(156), B => data_f1_out(156), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1681); - - \data_temp_RNO_0[57]\ : MX2C - port map(A => \data_temp[89]_net_1\, B => - \data_selected[89]\, S => \state[4]_net_1\, Y => N_658); - - \data_temp[39]\ : DFN1C0 - port map(D => N_231, CLK => lclk_c, CLR => rstn, Q => - \data_temp[39]_net_1\); - - \data_temp_RNO_3[47]\ : MX2C - port map(A => data_f0_out(79), B => data_f1_out(79), S => - \data_valid_and_ready[0]_net_1\, Y => N_847); - - \data_temp_RNO_1[113]\ : MX2C - port map(A => N_1710, B => N_773, S => N_1580_1, Y => - \data_selected[145]\); - - \data_temp_RNO_2[82]\ : MX2C - port map(A => data_f2_out(114), B => data_f3_out(114), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1735); - - \data_temp_RNO_0[75]\ : MX2C - port map(A => \data_temp[107]_net_1\, B => - \data_selected[107]\, S => \state[4]_net_1\, Y => N_676); - - \data_temp_RNO_3[32]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[64]_net_1\, - Y => N_864); - - \data_temp_RNO_3[74]\ : MX2C - port map(A => data_f0_out(106), B => data_f1_out(106), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_818); - - \data_temp_RNO_2[100]\ : MX2C - port map(A => data_f2_out(132), B => data_f3_out(132), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1711); - - \data_temp_RNO_2[112]\ : MX2C - port map(A => data_f2_out(144), B => data_f3_out(144), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1709); - - \data_temp_RNO_0[48]\ : MX2C - port map(A => \data_temp[80]_net_1\, B => - \data_selected[80]\, S => \state[4]_net_1\, Y => N_649); - - \data_temp_RNO_2[115]\ : MX2C - port map(A => data_f2_out(147), B => data_f3_out(147), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1698); - - \data_temp_RNO[104]\ : NOR2 - port map(A => N_863_2, B => N_705, Y => \data_temp_5[104]\); - - \data_temp_RNO_2[38]\ : MX2 - port map(A => data_f0_out(70), B => data_f1_out(70), S => - \data_valid_and_ready[0]_net_1\, Y => N_852); - - \data_temp[122]\ : DFN1C0 - port map(D => \data_temp_5[122]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[122]_net_1\); - - \data_temp[8]\ : DFN1C0 - port map(D => \data_temp_5[8]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[8]_net_1\); - - \data[26]\ : DFN1C0 - port map(D => \data_5[26]\, CLK => lclk_c, CLR => rstn, Q - => wdata(26)); - - \data_temp_RNO_0[74]\ : MX2C - port map(A => \data_temp[106]_net_1\, B => - \data_selected[106]\, S => \state[4]_net_1\, Y => N_675); - - \data_temp_RNO_1[122]\ : MX2C - port map(A => N_1691, B => N_1679, S => N_1580, Y => - \data_selected[154]\); - - \data_temp_RNO_0[89]\ : MX2C - port map(A => \data_temp[121]_net_1\, B => - \data_selected[121]\, S => \state[4]_net_1\, Y => N_690); - - \data_temp_RNO_0[81]\ : MX2C - port map(A => \data_temp[113]_net_1\, B => - \data_selected[113]\, S => \state[4]_net_1\, Y => N_682); - - \data_temp_RNO[101]\ : NOR2 - port map(A => N_863_2, B => N_702, Y => \data_temp_5[101]\); - - \data_temp_RNO_2[99]\ : MX2C - port map(A => data_f2_out(131), B => data_f3_out(131), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1724); - - \data_temp_RNO_2[91]\ : MX2 - port map(A => data_f2_out(123), B => data_f3_out(123), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1730); - - \data_temp_RNO_2[62]\ : MX2C - port map(A => data_f2_out(94), B => data_f3_out(94), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_745); - - \data_temp_RNO_3[119]\ : MX2C - port map(A => data_f0_out(151), B => data_f1_out(151), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1676); - - \data_temp_RNO[40]\ : NOR3 - port map(A => \data_temp_5_i_0[40]\, B => N_1663, C => - N_863_0, Y => N_233); - - \data_temp_RNO[99]\ : NOR2 - port map(A => N_863, B => N_700, Y => \data_temp_5[99]\); - - \data_temp_RNO_4[35]\ : MX2 - port map(A => data_f2_out(67), B => data_f3_out(67), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1688); - - \data[12]\ : DFN1C0 - port map(D => \data_5[12]\, CLK => lclk_c, CLR => rstn, Q - => wdata(12)); - - \data_temp_RNO_1[107]\ : MX2C - port map(A => N_1704, B => N_781, S => N_1580_1, Y => - \data_selected[139]\); - - \data_temp[104]\ : DFN1C0 - port map(D => \data_temp_5[104]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[104]_net_1\); - - \data_temp_RNO_3[120]\ : MX2C - port map(A => data_f0_out(152), B => data_f1_out(152), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1677); - - \data_temp_RNO_1[47]\ : MX2C - port map(A => N_758, B => N_847, S => N_1580_0, Y => - \data_selected[79]\); - - \data_temp_RNO_4[34]\ : MX2 - port map(A => data_f2_out(66), B => data_f3_out(66), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1687); - - \data_temp_RNO_0[69]\ : MX2C - port map(A => \data_temp[101]_net_1\, B => - \data_selected[101]\, S => \state[4]_net_1\, Y => N_670); - - \data_temp_RNO_0[61]\ : MX2C - port map(A => \data_temp[93]_net_1\, B => - \data_selected[93]\, S => \state[4]_net_1\, Y => N_662); - - \data_temp_RNO[96]\ : NOR2 - port map(A => N_863, B => N_697, Y => \data_temp_5[96]\); - - \data_temp[107]\ : DFN1C0 - port map(D => \data_temp_5[107]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[107]_net_1\); - - \data_temp[80]\ : DFN1C0 - port map(D => \data_temp_5[80]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[80]_net_1\); - - \data_temp_RNO_2[116]\ : MX2C - port map(A => data_f2_out(148), B => data_f3_out(148), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1699); - - \data_temp_RNO[18]\ : NOR2A - port map(A => \data_temp[50]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[18]\); - - \data_temp[95]\ : DFN1C0 - port map(D => \data_temp_5[95]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[95]_net_1\); - - \data_temp[63]\ : DFN1C0 - port map(D => \data_temp_5[63]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[63]_net_1\); - - \data_temp_RNO[123]\ : NOR3 - port map(A => N_910, B => N_909, C => N_1581, Y => N_251); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_temp_RNO_0[85]\ : MX2C - port map(A => \data_temp[117]_net_1\, B => - \data_selected[117]\, S => \state[4]_net_1\, Y => N_686); - - \data_temp[121]\ : DFN1C0 - port map(D => \data_temp_5[121]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[121]_net_1\); - - \data_temp[79]\ : DFN1C0 - port map(D => \data_temp_5[79]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[79]_net_1\); - - \data_temp_RNO_3[107]\ : MX2C - port map(A => data_f0_out(139), B => data_f1_out(139), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_781); - - \data[30]\ : DFN1C0 - port map(D => \data_5[30]\, CLK => lclk_c, CLR => rstn, Q - => wdata(30)); - - \data_temp_RNO_0[122]\ : MX2C - port map(A => \data_temp[122]_net_1\, B => - \data_selected[154]\, S => \state[4]_net_1\, Y => N_723); - - \data_temp_RNO_2[95]\ : MX2C - port map(A => data_f2_out(127), B => data_f3_out(127), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1720); - - \data_temp_RNO_0[100]\ : MX2C - port map(A => \data_temp[100]_net_1\, B => - \data_selected[132]\, S => \state[4]_net_1\, Y => N_701); - - \data_temp_RNO[13]\ : NOR2A - port map(A => \data_temp[45]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[13]\); - - \data_valid_and_ready[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready[0]_net_1\); - - \data_temp_RNO_3[97]\ : MX2C - port map(A => data_f0_out(129), B => data_f1_out(129), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_785); - - \data[19]\ : DFN1C0 - port map(D => \data_5[19]\, CLK => lclk_c, CLR => rstn, Q - => wdata(19)); - - \data_temp_RNO_0[84]\ : MX2C - port map(A => \data_temp[116]_net_1\, B => - \data_selected[116]\, S => \state[4]_net_1\, Y => N_685); - - \time_wen[2]\ : DFN1E0P0 - port map(D => N_859, CLK => lclk_c, PRE => rstn, E => N_928, - Q => time_wen(2)); - - \data_temp[118]\ : DFN1C0 - port map(D => \data_temp_5[118]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[118]_net_1\); - - \data_temp_RNO[109]\ : NOR2 - port map(A => N_863, B => N_710, Y => \data_temp_5[109]\); - - \data_temp_RNO_2[94]\ : MX2C - port map(A => data_f2_out(126), B => data_f3_out(126), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1719); - - \data_temp_RNO_1[79]\ : MX2C - port map(A => N_1732, B => N_809, S => N_1580_1, Y => - \data_selected[111]\); - - \data_temp_RNO_1[71]\ : MX2C - port map(A => N_740, B => N_815, S => N_1580_2, Y => - \data_selected[103]\); - - \data_temp[105]\ : DFN1C0 - port map(D => \data_temp_5[105]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[105]_net_1\); - - \data_temp[42]\ : DFN1C0 - port map(D => N_237, CLK => lclk_c, CLR => rstn, Q => - \data_temp[42]_net_1\); - - \data_temp_RNO_0[65]\ : MX2C - port map(A => \data_temp[97]_net_1\, B => - \data_selected[97]\, S => \state[4]_net_1\, Y => N_666); - - \data_temp_RNO[103]\ : NOR2 - port map(A => N_863_2, B => N_704, Y => \data_temp_5[103]\); - - \data_temp_RNO_3[102]\ : MX2C - port map(A => data_f0_out(134), B => data_f1_out(134), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_790); - - \data_temp_RNO_0[114]\ : MX2C - port map(A => \data_temp[114]_net_1\, B => - \data_selected[146]\, S => \state[4]_net_1\, Y => N_715); - - \data[15]\ : DFN1C0 - port map(D => \data_5[15]\, CLK => lclk_c, CLR => rstn, Q - => wdata(15)); - - \data_temp_RNO_0[111]\ : MX2C - port map(A => \data_temp[111]_net_1\, B => - \data_selected[143]\, S => \state[4]_net_1\, Y => N_712); - - \data_RNO[26]\ : NOR2A - port map(A => \data_temp[26]_net_1\, B => \state[4]_net_1\, - Y => \data_5[26]\); - - \data_temp[1]\ : DFN1C0 - port map(D => \data_temp_5[1]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[1]_net_1\); - - \data_temp_RNO_1[66]\ : MX2C - port map(A => N_735, B => N_824, S => N_1580, Y => - \data_selected[98]\); - - \data_temp_RNO_1[89]\ : MX2C - port map(A => N_1728, B => N_805, S => N_1580, Y => - \data_selected[121]\); - - \data_temp_RNO_1[81]\ : MX2C - port map(A => N_1734, B => N_811, S => N_1580_1, Y => - \data_selected[113]\); - - \data_temp_RNO_0[64]\ : MX2C - port map(A => \data_temp[96]_net_1\, B => - \data_selected[96]\, S => \state[4]_net_1\, Y => N_665); - - \data_temp_RNO_0[96]\ : MX2C - port map(A => \data_temp[96]_net_1\, B => - \data_selected[128]\, S => \state[4]_net_1\, Y => N_697); - - \data_temp_RNO_1[58]\ : MX2C - port map(A => N_741, B => N_830, S => N_1580_1, Y => - \data_selected[90]\); - - \data_temp_RNO_1[99]\ : MX2C - port map(A => N_1724, B => N_787, S => N_1580, Y => - \data_selected[131]\); - - \data_temp_RNO_1[91]\ : NOR2 - port map(A => N_912_i, B => N_793, Y => N_907); - - \data_temp_RNO_1[63]\ : MX2C - port map(A => N_746, B => N_821, S => N_1580_1, Y => - \data_selected[95]\); - - \data_temp_RNO_3[106]\ : MX2C - port map(A => data_f0_out(138), B => data_f1_out(138), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_780); - - \data_temp_RNO[28]\ : NOR2A - port map(A => \data_temp[60]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[28]\); - - \data_temp_RNO_1[32]\ : NOR2 - port map(A => N_1685, B => N_911, Y => N_865); - - \data_temp[41]\ : DFN1C0 - port map(D => N_235, CLK => lclk_c, CLR => rstn, Q => - \data_temp[41]_net_1\); - - \data_temp_RNO_2[78]\ : MX2C - port map(A => data_f2_out(110), B => data_f3_out(110), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_733); - - \data_temp_RNO_0[93]\ : NOR2 - port map(A => N_1718, B => N_911, Y => N_902); - - \data_temp_RNO_0[50]\ : MX2C - port map(A => \data_temp[82]_net_1\, B => - \data_selected[82]\, S => \state[4]_net_1\, Y => N_651); - - \data_temp_RNO[97]\ : NOR2 - port map(A => N_863, B => N_698, Y => \data_temp_5[97]\); - - \data_temp_RNO_0[47]\ : MX2C - port map(A => \data_temp[79]_net_1\, B => - \data_selected[79]\, S => \state[4]_net_1\, Y => N_648); - - \data_RNO[14]\ : NOR2A - port map(A => \data_temp[14]_net_1\, B => \state[4]_net_1\, - Y => \data_5[14]\); - - \data_temp_RNO_3[40]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[72]_net_1\, - Y => N_1662); - - \data_temp[23]\ : DFN1C0 - port map(D => \data_temp_5[23]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[23]_net_1\); - - \data_temp_RNO_3[121]\ : MX2C - port map(A => data_f0_out(153), B => data_f1_out(153), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1678); - - \data_temp_RNO_2[37]\ : MX2 - port map(A => data_f0_out(69), B => data_f1_out(69), S => - \data_valid_and_ready[0]_net_1\, Y => N_851); - - \data_temp[19]\ : DFN1C0 - port map(D => \data_temp_5[19]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[19]_net_1\); - - \data_temp_RNO_2[48]\ : MX2C - port map(A => data_f2_out(80), B => data_f3_out(80), S => - \data_valid_and_ready[2]_net_1\, Y => N_759); - - \data_temp_RNO_1[75]\ : MX2C - port map(A => N_730, B => N_819, S => N_1580_1, Y => - \data_selected[107]\); - - \data_valid_and_ready_0[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready_0[0]_net_1\); - - \data_temp_RNO[23]\ : NOR2A - port map(A => \data_temp[55]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[23]\); - - \data_RNO[10]\ : NOR2A - port map(A => \data_temp[10]_net_1\, B => \state[4]_net_1\, - Y => \data_5[10]\); - - \data_temp[60]\ : DFN1C0 - port map(D => \data_temp_5[60]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[60]_net_1\); - - \state_RNIT8OCE2_1[4]\ : NOR2 - port map(A => \data_temp_5_i_a2_0_0[32]_net_1\, B => N_911, - Y => N_863_2); - - \data_temp[53]\ : DFN1C0 - port map(D => \data_temp_5[53]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[53]_net_1\); - - \data_valid_and_ready_3[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready_3[2]_net_1\); - - \data_temp_RNO_3[76]\ : MX2C - port map(A => data_f0_out(108), B => data_f1_out(108), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_806); - - \data_temp_RNO_1[74]\ : MX2C - port map(A => N_729, B => N_818, S => N_1580_1, Y => - \data_selected[106]\); - - \data_temp_RNO_1[85]\ : MX2C - port map(A => N_1738, B => N_801, S => N_1580_2, Y => - \data_selected[117]\); - - \data_wen_RNO[3]\ : OR2 - port map(A => \time_en_temp[3]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[3]\); - - \data_temp_RNO_1[103]\ : MX2C - port map(A => N_1714, B => N_791, S => N_1580_2, Y => - \data_selected[135]\); - - \data_RNO[8]\ : NOR2A - port map(A => \data_temp[8]_net_1\, B => \state[4]_net_1\, - Y => \data_5[8]\); - - \data_temp_RNO_0[113]\ : MX2C - port map(A => \data_temp[113]_net_1\, B => - \data_selected[145]\, S => \state[4]_net_1\, Y => N_714); - - \data_temp_RNO_0[76]\ : MX2C - port map(A => \data_temp[108]_net_1\, B => - \data_selected[108]\, S => \state[4]_net_1\, Y => N_677); - - \data_temp_RNO[69]\ : NOR2 - port map(A => N_863_2, B => N_670, Y => \data_temp_5[69]\); - - \data_temp_RNO_2[102]\ : MX2C - port map(A => data_f2_out(134), B => data_f3_out(134), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1713); - - \data_temp_RNO_0[52]\ : MX2C - port map(A => \data_temp[84]_net_1\, B => - \data_selected[84]\, S => \state[4]_net_1\, Y => N_653); - - \data_temp_RNO_1[125]\ : NOR2 - port map(A => N_1682, B => N_912_i, Y => N_905); - - \data_RNO[9]\ : NOR2A - port map(A => \data_temp[9]_net_1\, B => \state[4]_net_1\, - Y => \data_5[9]\); - - \data_temp_RNO_2[105]\ : MX2C - port map(A => data_f2_out(137), B => data_f3_out(137), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1716); - - \data_temp_RNO_3[42]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[74]_net_1\, - Y => N_1668); - - \data_temp_RNO_1[111]\ : MX2C - port map(A => N_1708, B => N_771, S => N_1580_1, Y => - \data_selected[143]\); - - \data_valid_ack[1]\ : DFN1E0C0 - port map(D => N_857, CLK => lclk_c, CLR => rstn, E => N_929, - Q => valid_ack(1)); - - \data_temp_RNO_3[73]\ : MX2C - port map(A => data_f0_out(105), B => data_f1_out(105), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_817); - - \data_temp_RNO_1[84]\ : MX2C - port map(A => N_1737, B => N_800, S => N_1580_2, Y => - \data_selected[116]\); - - \data_temp_RNO_1[95]\ : MX2C - port map(A => N_1720, B => N_797, S => N_1580_0, Y => - \data_selected[127]\); - - \data_temp_RNO_1[40]\ : NOR2 - port map(A => N_911, B => N_765, Y => N_1663); - - \data_temp[48]\ : DFN1C0 - port map(D => \data_temp_5[48]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[48]_net_1\); - - \data_temp_RNO[50]\ : NOR2 - port map(A => N_863_1, B => N_651, Y => \data_temp_5[50]\); - - \data_temp[86]\ : DFN1C0 - port map(D => \data_temp_5[86]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[86]_net_1\); - - \data_temp_RNO[3]\ : NOR2A - port map(A => \data_temp[35]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[3]\); - - \data_temp_RNO_3[59]\ : MX2C - port map(A => data_f0_out(91), B => data_f1_out(91), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_831); - - \data_temp_RNO_3[51]\ : MX2C - port map(A => data_f0_out(83), B => data_f1_out(83), S => - \data_valid_and_ready[0]_net_1\, Y => N_837); - - \data_temp_RNO[80]\ : NOR2 - port map(A => N_863_1, B => N_681, Y => \data_temp_5[80]\); - - \data_temp_RNO_3[125]\ : MX2 - port map(A => data_f0_out(157), B => data_f1_out(157), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1682); - - \data_temp_RNO_3[69]\ : MX2C - port map(A => data_f0_out(101), B => data_f1_out(101), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_813); - - \data_temp_RNO_3[61]\ : MX2C - port map(A => data_f0_out(93), B => data_f1_out(93), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_833); - - \data_temp_RNO_0[73]\ : MX2C - port map(A => \data_temp[105]_net_1\, B => - \data_selected[105]\, S => \state[4]_net_1\, Y => N_674); - - \data_RNO[15]\ : NOR2A - port map(A => \data_temp[15]_net_1\, B => \state[4]_net_1\, - Y => \data_5[15]\); - - \data_temp_RNO_3[89]\ : MX2C - port map(A => data_f0_out(121), B => data_f1_out(121), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_805); - - \data_temp_RNO_3[81]\ : MX2C - port map(A => data_f0_out(113), B => data_f1_out(113), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_811); - - \data_temp_RNO[66]\ : NOR2 - port map(A => N_863, B => N_667, Y => \data_temp_5[66]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_temp_RNO_3[109]\ : MX2C - port map(A => data_f0_out(141), B => data_f1_out(141), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_783); - - \data_temp[116]\ : DFN1C0 - port map(D => \data_temp_5[116]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[116]_net_1\); - - \data_temp_RNO_1[94]\ : MX2C - port map(A => N_1719, B => N_796, S => N_1580_0, Y => - \data_selected[126]\); - - \data_temp_RNO[11]\ : NOR2A - port map(A => \data_temp[43]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[11]\); - - \data_temp_RNO_1[126]\ : MX2C - port map(A => N_1695, B => N_1683, S => N_1580_0, Y => - \data_selected[158]\); - - \state_RNIT8OCE2_2[4]\ : NOR2 - port map(A => \data_temp_5_i_a2_0_0[32]_net_1\, B => N_911, - Y => N_863_1); - - \data_temp_RNO_4[36]\ : MX2 - port map(A => data_f2_out(68), B => data_f3_out(68), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1689); - - \data_RNO[29]\ : NOR2A - port map(A => \data_temp[29]_net_1\, B => \state[4]_net_1\, - Y => \data_5[29]\); - - \state[3]\ : DFN1C0 - port map(D => state_0_sqmuxa_i, CLK => lclk_c, CLR => rstn, - Q => \state[3]_net_1\); - - \data_temp_RNO[12]\ : NOR2A - port map(A => \data_temp[44]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[12]\); - - \data_temp[47]\ : DFN1C0 - port map(D => \data_temp_5[47]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[47]_net_1\); - - \data_valid_ack_RNO[2]\ : INV - port map(A => N_859, Y => N_859_i); - - \data_RNO[30]\ : NOR2A - port map(A => \data_temp[30]_net_1\, B => \state[4]_net_1\, - Y => \data_5[30]\); - - \data_temp_RNO_4[33]\ : MX2 - port map(A => data_f2_out(65), B => data_f3_out(65), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1686); - - \data_temp_RNO_3[90]\ : MX2C - port map(A => data_f0_out(122), B => data_f1_out(122), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_792); - - \data_temp_RNO_1[42]\ : NOR2 - port map(A => N_911, B => N_767, Y => N_1669); - - \state_RNIT8OCE2_3[4]\ : NOR2 - port map(A => \data_temp_5_i_a2_0_0[32]_net_1\, B => N_911, - Y => N_863_0); - - \data_temp_RNO_2[121]\ : MX2C - port map(A => data_f2_out(153), B => data_f3_out(153), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1690); - - \data_temp[33]\ : DFN1C0 - port map(D => N_219, CLK => lclk_c, CLR => rstn, Q => - \data_temp[33]_net_1\); - - \data_temp[20]\ : DFN1C0 - port map(D => \data_temp_5[20]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[20]_net_1\); - - \data_temp_RNO_2[106]\ : MX2C - port map(A => data_f2_out(138), B => data_f3_out(138), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1717); - - \data[24]\ : DFN1C0 - port map(D => \data_5[24]\, CLK => lclk_c, CLR => rstn, Q - => wdata(24)); - - \data_temp_RNO[95]\ : NOR2 - port map(A => N_863_0, B => N_696, Y => \data_temp_5[95]\); - - \data_temp_RNO[14]\ : NOR2A - port map(A => \data_temp[46]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[14]\); - - \data_temp_RNO_2[89]\ : MX2C - port map(A => data_f2_out(121), B => data_f3_out(121), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1728); - - \data_temp_RNO_2[81]\ : MX2C - port map(A => data_f2_out(113), B => data_f3_out(113), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1734); - - \data_temp_RNO_3[39]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[71]_net_1\, - Y => N_1659); - - \data_temp[50]\ : DFN1C0 - port map(D => \data_temp_5[50]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[50]_net_1\); - - \data_temp_RNO_3[55]\ : MX2C - port map(A => data_f0_out(87), B => data_f1_out(87), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_827); - - \data_temp_RNO_0[86]\ : MX2C - port map(A => \data_temp[118]_net_1\, B => - \data_selected[118]\, S => \state[4]_net_1\, Y => N_687); - - \data[1]\ : DFN1C0 - port map(D => \data_5[1]\, CLK => lclk_c, CLR => rstn, Q - => wdata(1)); - - \data_valid_and_ready_2[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready_2[2]_net_1\); - - \data_temp_RNO_3[65]\ : MX2C - port map(A => data_f0_out(97), B => data_f1_out(97), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_823); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_valid_and_ready[1]\ : NOR2 - port map(A => valid_out_i(1), B => ready_i_0_i_0(1), Y => - \data_valid_and_ready[1]_net_1\); - - \data_temp_RNO_3[85]\ : MX2C - port map(A => data_f0_out(117), B => data_f1_out(117), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_801); - - \state_RNO[4]\ : OA1B - port map(A => N_1306, B => \state[0]_net_1\, C => - \state_ns_i_i_a2_1[0]\, Y => N_861); - - \data_temp_RNO_2[96]\ : MX2C - port map(A => data_f2_out(128), B => data_f3_out(128), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1721); - - \data[9]\ : DFN1C0 - port map(D => \data_5[9]\, CLK => lclk_c, CLR => rstn, Q - => wdata(9)); - - \data_temp_RNO_3[123]\ : MX2 - port map(A => data_f0_out(155), B => data_f1_out(155), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1680); - - \data_valid_and_ready[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready[2]_net_1\); - - \data_temp_RNO_3[54]\ : MX2C - port map(A => data_f0_out(86), B => data_f1_out(86), S => - \data_valid_and_ready[0]_net_1\, Y => N_840); - - \data_temp_RNO_1[124]\ : NOR2 - port map(A => N_1681, B => N_912_i, Y => N_903); - - \data_temp_RNO_3[92]\ : MX2 - port map(A => data_f0_out(124), B => data_f1_out(124), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_794); - - \data_temp_RNO_3[64]\ : MX2C - port map(A => data_f0_out(96), B => data_f1_out(96), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_822); - - \data_temp_RNO_1[57]\ : MX2C - port map(A => N_754, B => N_829, S => N_1580_1, Y => - \data_selected[89]\); - - \data_temp_RNO_2[69]\ : MX2C - port map(A => data_f2_out(101), B => data_f3_out(101), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_738); - - \data_temp_RNO_2[61]\ : MX2C - port map(A => data_f2_out(93), B => data_f3_out(93), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_744); - - \data[17]\ : DFN1C0 - port map(D => \data_5[17]\, CLK => lclk_c, CLR => rstn, Q - => wdata(17)); - - \data_temp_RNO_3[84]\ : MX2C - port map(A => data_f0_out(116), B => data_f1_out(116), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_800); - - \data_temp_RNITP6OE2[123]\ : AO1D - port map(A => \state[4]_net_1\, B => \data_temp[123]_net_1\, - C => N_863_0, Y => N_1581); - - \data_temp_RNO_0[83]\ : MX2C - port map(A => \data_temp[115]_net_1\, B => - \data_selected[115]\, S => \state[4]_net_1\, Y => N_684); - - \data_temp_RNIUP6OE2[124]\ : AO1D - port map(A => \state[4]_net_1\, B => \data_temp[124]_net_1\, - C => N_863_0, Y => N_1583); - - \data_temp_RNO_2[58]\ : MX2C - port map(A => data_f2_out(90), B => data_f3_out(90), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_741); - - \data[20]\ : DFN1C0 - port map(D => \data_5[20]\, CLK => lclk_c, CLR => rstn, Q - => wdata(20)); - - \data_temp_RNO_2[93]\ : MX2 - port map(A => data_f2_out(125), B => data_f3_out(125), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1718); - - \data_RNO[6]\ : NOR2A - port map(A => \data_temp[6]_net_1\, B => \state[4]_net_1\, - Y => \data_5[6]\); - - \data_RNO[3]\ : NOR2A - port map(A => \data_temp[3]_net_1\, B => \state[4]_net_1\, - Y => \data_5[3]\); - - \data_temp_RNO_2[77]\ : MX2C - port map(A => data_f2_out(109), B => data_f3_out(109), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_732); - - \data_temp_RNO_0[66]\ : MX2C - port map(A => \data_temp[98]_net_1\, B => - \data_selected[98]\, S => \state[4]_net_1\, Y => N_667); - - \data_temp_RNO[21]\ : NOR2A - port map(A => \data_temp[53]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[21]\); - - \data_wen[0]\ : DFN1E0P0 - port map(D => \data_wen_3[0]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => data_wen(0)); - - \data_temp_RNO_0[104]\ : MX2C - port map(A => \data_temp[104]_net_1\, B => - \data_selected[136]\, S => \state[4]_net_1\, Y => N_705); - - \data_temp_RNO_4[40]\ : MX2 - port map(A => data_f2_out(72), B => data_f3_out(72), S => - \data_valid_and_ready[2]_net_1\, Y => N_765); - - \data_temp_RNO_2[47]\ : MX2C - port map(A => data_f2_out(79), B => data_f3_out(79), S => - \data_valid_and_ready[2]_net_1\, Y => N_758); - - \data_temp_RNO_0[101]\ : MX2C - port map(A => \data_temp[101]_net_1\, B => - \data_selected[133]\, S => \state[4]_net_1\, Y => N_702); - - \data_temp_RNO_0[40]\ : AO1D - port map(A => N_912_i, B => N_854, C => N_1662, Y => - \data_temp_5_i_0[40]\); - - \data_temp_RNO_0[38]\ : AO1D - port map(A => N_912_i, B => N_852, C => N_1656, Y => - \data_temp_5_i_0[38]\); - - \data_temp_RNO[67]\ : NOR2 - port map(A => N_863, B => N_668, Y => \data_temp_5[67]\); - - \data_temp_RNO[22]\ : NOR2A - port map(A => \data_temp[54]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[22]\); - - \data_temp_RNO[79]\ : NOR2 - port map(A => N_863_1, B => N_680, Y => \data_temp_5[79]\); - - \data_temp[66]\ : DFN1C0 - port map(D => \data_temp_5[66]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[66]_net_1\); - - \data_temp_RNO_2[85]\ : MX2C - port map(A => data_f2_out(117), B => data_f3_out(117), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1738); - - \data_temp_RNO_2[123]\ : MX2 - port map(A => data_f2_out(155), B => data_f3_out(155), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1692); - - \data_temp_RNO_0[63]\ : MX2C - port map(A => \data_temp[95]_net_1\, B => - \data_selected[95]\, S => \state[4]_net_1\, Y => N_664); - - \data_temp_RNO_3[35]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[67]_net_1\, - Y => N_873); - - \data_temp[84]\ : DFN1C0 - port map(D => \data_temp_5[84]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[84]_net_1\); - - \data_temp[45]\ : DFN1C0 - port map(D => \data_temp_5[45]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[45]_net_1\); - - \data_valid_ack[2]\ : DFN1E0C0 - port map(D => N_859_i, CLK => lclk_c, CLR => rstn, E => - N_929, Q => valid_ack(2)); - - \data_temp[73]\ : DFN1C0 - port map(D => \data_temp_5[73]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[73]_net_1\); - - \data_temp_RNO_3[118]\ : MX2C - port map(A => data_f0_out(150), B => data_f1_out(150), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1675); - - \data_temp_RNO_2[84]\ : MX2C - port map(A => data_f2_out(116), B => data_f3_out(116), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1737); - - \data_temp_RNO[76]\ : NOR2 - port map(A => N_863_1, B => N_677, Y => \data_temp_5[76]\); - - \data_temp_RNO_3[34]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[66]_net_1\, - Y => N_870); - - \data_temp[113]\ : DFN1C0 - port map(D => \data_temp_5[113]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[113]_net_1\); - - \data_temp_RNO[24]\ : NOR2A - port map(A => \data_temp[56]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[24]\); - - \data_temp[30]\ : DFN1C0 - port map(D => \data_temp_5[30]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[30]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform is - - port( status_full_ack : in std_logic_vector(3 downto 0); - hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - iosn_1 : in std_logic_vector(93 to 93); - nhmaster_1_i : in std_logic_vector(0 to 0); - hsize : out std_logic_vector(1 downto 0); - hmaster_0 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - hgrant : in std_logic_vector(3 to 3); - iosn_0 : in std_logic_vector(93 to 93); - bco_msb_1_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - l1_0_m : in std_logic_vector(1 to 1); - nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - status_full : out std_logic_vector(3 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - hwdata : out std_logic_vector(31 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - sample_f3_wdata : in std_logic_vector(95 downto 0); - sample_f2_wdata : in std_logic_vector(95 downto 0); - sample_f1_15 : in std_logic; - sample_f1_47 : in std_logic; - sample_f1_14 : in std_logic; - sample_f1_46 : in std_logic; - sample_f1_13 : in std_logic; - sample_f1_45 : in std_logic; - sample_f1_12 : in std_logic; - sample_f1_44 : in std_logic; - sample_f1_60 : in std_logic; - sample_f1_59 : in std_logic; - sample_f1_58 : in std_logic; - sample_f1_57 : in std_logic; - sample_f1_56 : in std_logic; - sample_f1_55 : in std_logic; - sample_f1_54 : in std_logic; - sample_f1_53 : in std_logic; - sample_f1_52 : in std_logic; - sample_f1_51 : in std_logic; - sample_f1_50 : in std_logic; - sample_f1_49 : in std_logic; - sample_f1_48 : in std_logic; - sample_f1_4 : in std_logic; - sample_f1_36 : in std_logic; - sample_f1_3 : in std_logic; - sample_f1_35 : in std_logic; - sample_f1_2 : in std_logic; - sample_f1_34 : in std_logic; - sample_f1_1 : in std_logic; - sample_f1_33 : in std_logic; - sample_f1_0 : in std_logic; - sample_f1_32 : in std_logic; - sample_f1_63 : in std_logic; - sample_f1_62 : in std_logic; - sample_f1_61 : in std_logic; - sample_f1_11 : in std_logic; - sample_f1_43 : in std_logic; - sample_f1_10 : in std_logic; - sample_f1_42 : in std_logic; - sample_f1_9 : in std_logic; - sample_f1_41 : in std_logic; - sample_f1_8 : in std_logic; - sample_f1_40 : in std_logic; - sample_f1_7 : in std_logic; - sample_f1_39 : in std_logic; - sample_f1_6 : in std_logic; - sample_f1_38 : in std_logic; - sample_f1_5 : in std_logic; - sample_f1_37 : in std_logic; - sample_f1_wdata_0 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_95 : in std_logic; - sample_f0_15 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_0 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_63 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_37 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_95 : in std_logic; - coarse_time : in std_logic_vector(0 to 0); - delta_snapshot : in std_logic_vector(15 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - coarse_time_i : in std_logic_vector(0 to 0); - nb_snapshot_param : in std_logic_vector(10 downto 0); - IdlePhase : out std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - arb_1 : in std_logic; - hbusreq_i_3 : out std_logic; - Lock_RNIU86D : out std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - m19_0_N_15_i_0_li : in std_logic; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - m26_m1_e : out std_logic; - sample_f3_val : in std_logic; - enable_f3 : in std_logic; - burst_f2 : in std_logic; - enable_f2 : in std_logic; - sample_f1_val_0 : in std_logic; - burst_f1 : in std_logic; - enable_f1 : in std_logic; - data_shaping_R1_0 : in std_logic; - data_shaping_R1 : in std_logic; - burst_f0 : in std_logic; - enable_f0 : in std_logic; - data_shaping_R0_0 : in std_logic; - data_shaping_R0 : in std_logic; - lclk_c : in std_logic; - rstn : in std_logic; - sample_f0_val_0 : in std_logic; - sample_f2_val : in std_logic - ); - -end lpp_waveform; - -architecture DEF_ARCH of lpp_waveform is - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform_snapshot_160_12 - port( sample_f1_wdata_95 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - data_f1_out : out std_logic_vector(159 downto 64); - sample_f1_37 : in std_logic := 'U'; - sample_f1_5 : in std_logic := 'U'; - sample_f1_38 : in std_logic := 'U'; - sample_f1_6 : in std_logic := 'U'; - sample_f1_39 : in std_logic := 'U'; - sample_f1_7 : in std_logic := 'U'; - sample_f1_40 : in std_logic := 'U'; - sample_f1_8 : in std_logic := 'U'; - sample_f1_41 : in std_logic := 'U'; - sample_f1_9 : in std_logic := 'U'; - sample_f1_42 : in std_logic := 'U'; - sample_f1_10 : in std_logic := 'U'; - sample_f1_43 : in std_logic := 'U'; - sample_f1_11 : in std_logic := 'U'; - sample_f1_61 : in std_logic := 'U'; - sample_f1_62 : in std_logic := 'U'; - sample_f1_63 : in std_logic := 'U'; - sample_f1_32 : in std_logic := 'U'; - sample_f1_0 : in std_logic := 'U'; - sample_f1_33 : in std_logic := 'U'; - sample_f1_1 : in std_logic := 'U'; - sample_f1_34 : in std_logic := 'U'; - sample_f1_2 : in std_logic := 'U'; - sample_f1_35 : in std_logic := 'U'; - sample_f1_3 : in std_logic := 'U'; - sample_f1_36 : in std_logic := 'U'; - sample_f1_4 : in std_logic := 'U'; - sample_f1_48 : in std_logic := 'U'; - sample_f1_49 : in std_logic := 'U'; - sample_f1_50 : in std_logic := 'U'; - sample_f1_51 : in std_logic := 'U'; - sample_f1_52 : in std_logic := 'U'; - sample_f1_53 : in std_logic := 'U'; - sample_f1_54 : in std_logic := 'U'; - sample_f1_55 : in std_logic := 'U'; - sample_f1_56 : in std_logic := 'U'; - sample_f1_57 : in std_logic := 'U'; - sample_f1_58 : in std_logic := 'U'; - sample_f1_59 : in std_logic := 'U'; - sample_f1_60 : in std_logic := 'U'; - sample_f1_44 : in std_logic := 'U'; - sample_f1_12 : in std_logic := 'U'; - sample_f1_45 : in std_logic := 'U'; - sample_f1_13 : in std_logic := 'U'; - sample_f1_46 : in std_logic := 'U'; - sample_f1_14 : in std_logic := 'U'; - sample_f1_47 : in std_logic := 'U'; - sample_f1_15 : in std_logic := 'U'; - nb_snapshot_param : in std_logic_vector(0 to 0) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f1_out_valid : out std_logic; - data_shaping_R1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - I_9_31 : in std_logic := 'U'; - I_45_11 : in std_logic := 'U'; - I_52_11 : in std_logic := 'U'; - I_56_12 : in std_logic := 'U'; - I_24_16 : in std_logic := 'U'; - N_4 : in std_logic := 'U'; - I_20_23 : in std_logic := 'U'; - I_13_35 : in std_logic := 'U'; - I_38_12 : in std_logic := 'U'; - I_31_15 : in std_logic := 'U'; - I_5_31 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U'; - start_snapshot_f1 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_controler - port( coarse_time_i : in std_logic_vector(0 to 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - coarse_time : in std_logic_vector(0 to 0) := (others => 'U'); - start_snapshot_f2 : out std_logic; - start_snapshot_f1 : out std_logic; - start_snapshot_f0 : out std_logic; - sample_f2_val : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - port( status_new_err : out std_logic_vector(3 to 3); - valid_ack : in std_logic_vector(3 to 3) := (others => 'U'); - valid_out : out std_logic_vector(3 to 3); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f3_out_valid : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - port( status_new_err : out std_logic_vector(1 to 1); - valid_out_i : out std_logic_vector(1 to 1); - valid_ack : in std_logic_vector(1 to 1) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f1_out_valid : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_waveform_burst - port( sample_f3_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - data_f3_out : out std_logic_vector(159 downto 64); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f3_out_valid : out std_logic; - enable_f3 : in std_logic := 'U'; - sample_f3_val : in std_logic := 'U' - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - port( status_new_err : out std_logic_vector(2 to 2); - valid_ack : in std_logic_vector(2 to 2) := (others => 'U'); - valid_out : out std_logic_vector(2 to 2); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f2_out_valid : in std_logic := 'U' - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - port( status_new_err : out std_logic_vector(0 to 0); - valid_ack : in std_logic_vector(0 to 0) := (others => 'U'); - valid_out : out std_logic_vector(0 to 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f0_out_valid : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo - port( ready_i_0_i_0 : out std_logic_vector(1 to 1); - data_wen : in std_logic_vector(3 downto 0) := (others => 'U'); - data_ren : in std_logic_vector(3 downto 0) := (others => 'U'); - ready_i_0_2 : out std_logic; - ready_i_0_0 : out std_logic; - ready_i_0_3 : out std_logic; - time_ren : in std_logic_vector(3 downto 0) := (others => 'U'); - time_wen : in std_logic_vector(3 downto 0) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - time_ren_1z : in std_logic := 'U'; - data_ren_1z : in std_logic := 'U'; - un13_time_write : in std_logic := 'U'; - un20_time_write : in std_logic := 'U'; - un27_time_write : in std_logic := 'U'; - un5_time_write : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_160_11 - port( sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - data_f0_out : out std_logic_vector(159 downto 64); - sample_f0_37 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_0 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f0_out_valid : out std_logic; - data_shaping_R0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - start_snapshot_f0 : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_160_12_1 - port( sample_f2_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - data_f2_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f2_out_valid : out std_logic; - I_9_31 : in std_logic := 'U'; - I_45_11 : in std_logic := 'U'; - I_52_11 : in std_logic := 'U'; - I_38_12 : in std_logic := 'U'; - N_4 : in std_logic := 'U'; - I_56_12 : in std_logic := 'U'; - I_24_16 : in std_logic := 'U'; - I_5_31 : in std_logic := 'U'; - I_20_23 : in std_logic := 'U'; - I_13_35 : in std_logic := 'U'; - I_31_15 : in std_logic := 'U'; - start_snapshot_f2 : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_dma - port( addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : out std_logic_vector(1 downto 0); - hburst : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - data_ren : out std_logic_vector(3 downto 0); - ready_i_0_i_0 : in std_logic_vector(1 to 1) := (others => 'U'); - ready_i_0_2 : in std_logic := 'U'; - ready_i_0_0 : in std_logic := 'U'; - ready_i_0_3 : in std_logic := 'U'; - time_ren : out std_logic_vector(3 downto 0); - time_ren_1z : out std_logic; - data_ren_1z : out std_logic; - m26_m1_e : out std_logic; - m19_a1_6_i_0 : out std_logic; - m19_a0_6_i_0 : out std_logic; - m19_0_N_15_i_0_li : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - Lock_RNIU86D : out std_logic; - hbusreq_i_3 : out std_logic; - arb_1 : in std_logic := 'U'; - un1_dmain_6 : out std_logic; - hwrite : out std_logic; - IdlePhase : out std_logic; - un13_time_write : out std_logic; - un5_time_write : out std_logic; - un27_time_write : out std_logic; - un20_time_write : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_arbiter - port( wdata : out std_logic_vector(31 downto 0); - data_wen : out std_logic_vector(3 downto 0); - valid_ack : out std_logic_vector(3 downto 0); - time_wen : out std_logic_vector(3 downto 0); - data_f3_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f2_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f1_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f0_out : in std_logic_vector(159 downto 64) := (others => 'U'); - ready_i_0_i_0 : in std_logic_vector(1 to 1) := (others => 'U'); - valid_out_i : in std_logic_vector(1 to 1) := (others => 'U'); - ready_i_0_3 : in std_logic := 'U'; - ready_i_0_0 : in std_logic := 'U'; - ready_i_0_2 : in std_logic := 'U'; - valid_out_3 : in std_logic := 'U'; - valid_out_0 : in std_logic := 'U'; - valid_out_2 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal N_45, N_37, \DWACT_FINC_E[0]\, N_14, - \DWACT_FINC_E[4]\, N_4, \DWACT_FINC_E[6]\, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[5]\, I_56_12, N_11, - I_52_11, \DWACT_FINC_E[3]\, I_45_11, N_19, I_38_12, N_24, - I_31_15, N_29, \DWACT_FINC_E[1]\, I_24_16, N_34, I_20_23, - I_13_35, N_42, I_9_31, I_5_31, start_snapshot_f2, - start_snapshot_f1, start_snapshot_f0, \data_f0_out[64]\, - \data_f0_out[65]\, \data_f0_out[66]\, \data_f0_out[67]\, - \data_f0_out[68]\, \data_f0_out[69]\, \data_f0_out[70]\, - \data_f0_out[71]\, \data_f0_out[72]\, \data_f0_out[73]\, - \data_f0_out[74]\, \data_f0_out[75]\, \data_f0_out[76]\, - \data_f0_out[77]\, \data_f0_out[78]\, \data_f0_out[79]\, - \data_f0_out[80]\, \data_f0_out[81]\, \data_f0_out[82]\, - \data_f0_out[83]\, \data_f0_out[84]\, \data_f0_out[85]\, - \data_f0_out[86]\, \data_f0_out[87]\, \data_f0_out[88]\, - \data_f0_out[89]\, \data_f0_out[90]\, \data_f0_out[91]\, - \data_f0_out[92]\, \data_f0_out[93]\, \data_f0_out[94]\, - \data_f0_out[95]\, \data_f0_out[96]\, \data_f0_out[97]\, - \data_f0_out[98]\, \data_f0_out[99]\, \data_f0_out[100]\, - \data_f0_out[101]\, \data_f0_out[102]\, - \data_f0_out[103]\, \data_f0_out[104]\, - \data_f0_out[105]\, \data_f0_out[106]\, - \data_f0_out[107]\, \data_f0_out[108]\, - \data_f0_out[109]\, \data_f0_out[110]\, - \data_f0_out[111]\, \data_f0_out[112]\, - \data_f0_out[113]\, \data_f0_out[114]\, - \data_f0_out[115]\, \data_f0_out[116]\, - \data_f0_out[117]\, \data_f0_out[118]\, - \data_f0_out[119]\, \data_f0_out[120]\, - \data_f0_out[121]\, \data_f0_out[122]\, - \data_f0_out[123]\, \data_f0_out[124]\, - \data_f0_out[125]\, \data_f0_out[126]\, - \data_f0_out[127]\, \data_f0_out[128]\, - \data_f0_out[129]\, \data_f0_out[130]\, - \data_f0_out[131]\, \data_f0_out[132]\, - \data_f0_out[133]\, \data_f0_out[134]\, - \data_f0_out[135]\, \data_f0_out[136]\, - \data_f0_out[137]\, \data_f0_out[138]\, - \data_f0_out[139]\, \data_f0_out[140]\, - \data_f0_out[141]\, \data_f0_out[142]\, - \data_f0_out[143]\, \data_f0_out[144]\, - \data_f0_out[145]\, \data_f0_out[146]\, - \data_f0_out[147]\, \data_f0_out[148]\, - \data_f0_out[149]\, \data_f0_out[150]\, - \data_f0_out[151]\, \data_f0_out[152]\, - \data_f0_out[153]\, \data_f0_out[154]\, - \data_f0_out[155]\, \data_f0_out[156]\, - \data_f0_out[157]\, \data_f0_out[158]\, - \data_f0_out[159]\, data_f0_out_valid, \data_f1_out[64]\, - \data_f1_out[65]\, \data_f1_out[66]\, \data_f1_out[67]\, - \data_f1_out[68]\, \data_f1_out[69]\, \data_f1_out[70]\, - \data_f1_out[71]\, \data_f1_out[72]\, \data_f1_out[73]\, - \data_f1_out[74]\, \data_f1_out[75]\, \data_f1_out[76]\, - \data_f1_out[77]\, \data_f1_out[78]\, \data_f1_out[79]\, - \data_f1_out[80]\, \data_f1_out[81]\, \data_f1_out[82]\, - \data_f1_out[83]\, \data_f1_out[84]\, \data_f1_out[85]\, - \data_f1_out[86]\, \data_f1_out[87]\, \data_f1_out[88]\, - \data_f1_out[89]\, \data_f1_out[90]\, \data_f1_out[91]\, - \data_f1_out[92]\, \data_f1_out[93]\, \data_f1_out[94]\, - \data_f1_out[95]\, \data_f1_out[96]\, \data_f1_out[97]\, - \data_f1_out[98]\, \data_f1_out[99]\, \data_f1_out[100]\, - \data_f1_out[101]\, \data_f1_out[102]\, - \data_f1_out[103]\, \data_f1_out[104]\, - \data_f1_out[105]\, \data_f1_out[106]\, - \data_f1_out[107]\, \data_f1_out[108]\, - \data_f1_out[109]\, \data_f1_out[110]\, - \data_f1_out[111]\, \data_f1_out[112]\, - \data_f1_out[113]\, \data_f1_out[114]\, - \data_f1_out[115]\, \data_f1_out[116]\, - \data_f1_out[117]\, \data_f1_out[118]\, - \data_f1_out[119]\, \data_f1_out[120]\, - \data_f1_out[121]\, \data_f1_out[122]\, - \data_f1_out[123]\, \data_f1_out[124]\, - \data_f1_out[125]\, \data_f1_out[126]\, - \data_f1_out[127]\, \data_f1_out[128]\, - \data_f1_out[129]\, \data_f1_out[130]\, - \data_f1_out[131]\, \data_f1_out[132]\, - \data_f1_out[133]\, \data_f1_out[134]\, - \data_f1_out[135]\, \data_f1_out[136]\, - \data_f1_out[137]\, \data_f1_out[138]\, - \data_f1_out[139]\, \data_f1_out[140]\, - \data_f1_out[141]\, \data_f1_out[142]\, - \data_f1_out[143]\, \data_f1_out[144]\, - \data_f1_out[145]\, \data_f1_out[146]\, - \data_f1_out[147]\, \data_f1_out[148]\, - \data_f1_out[149]\, \data_f1_out[150]\, - \data_f1_out[151]\, \data_f1_out[152]\, - \data_f1_out[153]\, \data_f1_out[154]\, - \data_f1_out[155]\, \data_f1_out[156]\, - \data_f1_out[157]\, \data_f1_out[158]\, - \data_f1_out[159]\, data_f1_out_valid, \data_f2_out[64]\, - \data_f2_out[65]\, \data_f2_out[66]\, \data_f2_out[67]\, - \data_f2_out[68]\, \data_f2_out[69]\, \data_f2_out[70]\, - \data_f2_out[71]\, \data_f2_out[72]\, \data_f2_out[73]\, - \data_f2_out[74]\, \data_f2_out[75]\, \data_f2_out[76]\, - \data_f2_out[77]\, \data_f2_out[78]\, \data_f2_out[79]\, - \data_f2_out[80]\, \data_f2_out[81]\, \data_f2_out[82]\, - \data_f2_out[83]\, \data_f2_out[84]\, \data_f2_out[85]\, - \data_f2_out[86]\, \data_f2_out[87]\, \data_f2_out[88]\, - \data_f2_out[89]\, \data_f2_out[90]\, \data_f2_out[91]\, - \data_f2_out[92]\, \data_f2_out[93]\, \data_f2_out[94]\, - \data_f2_out[95]\, \data_f2_out[96]\, \data_f2_out[97]\, - \data_f2_out[98]\, \data_f2_out[99]\, \data_f2_out[100]\, - \data_f2_out[101]\, \data_f2_out[102]\, - \data_f2_out[103]\, \data_f2_out[104]\, - \data_f2_out[105]\, \data_f2_out[106]\, - \data_f2_out[107]\, \data_f2_out[108]\, - \data_f2_out[109]\, \data_f2_out[110]\, - \data_f2_out[111]\, \data_f2_out[112]\, - \data_f2_out[113]\, \data_f2_out[114]\, - \data_f2_out[115]\, \data_f2_out[116]\, - \data_f2_out[117]\, \data_f2_out[118]\, - \data_f2_out[119]\, \data_f2_out[120]\, - \data_f2_out[121]\, \data_f2_out[122]\, - \data_f2_out[123]\, \data_f2_out[124]\, - \data_f2_out[125]\, \data_f2_out[126]\, - \data_f2_out[127]\, \data_f2_out[128]\, - \data_f2_out[129]\, \data_f2_out[130]\, - \data_f2_out[131]\, \data_f2_out[132]\, - \data_f2_out[133]\, \data_f2_out[134]\, - \data_f2_out[135]\, \data_f2_out[136]\, - \data_f2_out[137]\, \data_f2_out[138]\, - \data_f2_out[139]\, \data_f2_out[140]\, - \data_f2_out[141]\, \data_f2_out[142]\, - \data_f2_out[143]\, \data_f2_out[144]\, - \data_f2_out[145]\, \data_f2_out[146]\, - \data_f2_out[147]\, \data_f2_out[148]\, - \data_f2_out[149]\, \data_f2_out[150]\, - \data_f2_out[151]\, \data_f2_out[152]\, - \data_f2_out[153]\, \data_f2_out[154]\, - \data_f2_out[155]\, \data_f2_out[156]\, - \data_f2_out[157]\, \data_f2_out[158]\, - \data_f2_out[159]\, data_f2_out_valid, \data_f3_out[64]\, - \data_f3_out[65]\, \data_f3_out[66]\, \data_f3_out[67]\, - \data_f3_out[68]\, \data_f3_out[69]\, \data_f3_out[70]\, - \data_f3_out[71]\, \data_f3_out[72]\, \data_f3_out[73]\, - \data_f3_out[74]\, \data_f3_out[75]\, \data_f3_out[76]\, - \data_f3_out[77]\, \data_f3_out[78]\, \data_f3_out[79]\, - \data_f3_out[80]\, \data_f3_out[81]\, \data_f3_out[82]\, - \data_f3_out[83]\, \data_f3_out[84]\, \data_f3_out[85]\, - \data_f3_out[86]\, \data_f3_out[87]\, \data_f3_out[88]\, - \data_f3_out[89]\, \data_f3_out[90]\, \data_f3_out[91]\, - \data_f3_out[92]\, \data_f3_out[93]\, \data_f3_out[94]\, - \data_f3_out[95]\, \data_f3_out[96]\, \data_f3_out[97]\, - \data_f3_out[98]\, \data_f3_out[99]\, \data_f3_out[100]\, - \data_f3_out[101]\, \data_f3_out[102]\, - \data_f3_out[103]\, \data_f3_out[104]\, - \data_f3_out[105]\, \data_f3_out[106]\, - \data_f3_out[107]\, \data_f3_out[108]\, - \data_f3_out[109]\, \data_f3_out[110]\, - \data_f3_out[111]\, \data_f3_out[112]\, - \data_f3_out[113]\, \data_f3_out[114]\, - \data_f3_out[115]\, \data_f3_out[116]\, - \data_f3_out[117]\, \data_f3_out[118]\, - \data_f3_out[119]\, \data_f3_out[120]\, - \data_f3_out[121]\, \data_f3_out[122]\, - \data_f3_out[123]\, \data_f3_out[124]\, - \data_f3_out[125]\, \data_f3_out[126]\, - \data_f3_out[127]\, \data_f3_out[128]\, - \data_f3_out[129]\, \data_f3_out[130]\, - \data_f3_out[131]\, \data_f3_out[132]\, - \data_f3_out[133]\, \data_f3_out[134]\, - \data_f3_out[135]\, \data_f3_out[136]\, - \data_f3_out[137]\, \data_f3_out[138]\, - \data_f3_out[139]\, \data_f3_out[140]\, - \data_f3_out[141]\, \data_f3_out[142]\, - \data_f3_out[143]\, \data_f3_out[144]\, - \data_f3_out[145]\, \data_f3_out[146]\, - \data_f3_out[147]\, \data_f3_out[148]\, - \data_f3_out[149]\, \data_f3_out[150]\, - \data_f3_out[151]\, \data_f3_out[152]\, - \data_f3_out[153]\, \data_f3_out[154]\, - \data_f3_out[155]\, \data_f3_out[156]\, - \data_f3_out[157]\, \data_f3_out[158]\, - \data_f3_out[159]\, data_f3_out_valid, \valid_ack[3]\, - \valid_out[3]\, \valid_ack[0]\, \valid_out[0]\, - \valid_out_i[1]\, \valid_ack[1]\, \valid_ack[2]\, - \valid_out[2]\, \wdata[0]\, \wdata[1]\, \wdata[2]\, - \wdata[3]\, \wdata[4]\, \wdata[5]\, \wdata[6]\, - \wdata[7]\, \wdata[8]\, \wdata[9]\, \wdata[10]\, - \wdata[11]\, \wdata[12]\, \wdata[13]\, \wdata[14]\, - \wdata[15]\, \wdata[16]\, \wdata[17]\, \wdata[18]\, - \wdata[19]\, \wdata[20]\, \wdata[21]\, \wdata[22]\, - \wdata[23]\, \wdata[24]\, \wdata[25]\, \wdata[26]\, - \wdata[27]\, \wdata[28]\, \wdata[29]\, \wdata[30]\, - \wdata[31]\, \data_wen[0]\, \data_wen[1]\, \data_wen[2]\, - \data_wen[3]\, \time_wen[0]\, \time_wen[1]\, - \time_wen[2]\, \time_wen[3]\, \ready_i_0_i_0[1]\, - \ready_i_0[3]\, \ready_i_0[0]\, \ready_i_0[2]\, - \data_ren[0]\, \data_ren[1]\, \data_ren[2]\, - \data_ren[3]\, \time_ren[0]\, \time_ren[1]\, - \time_ren[2]\, \time_ren[3]\, time_ren, data_ren, - un13_time_write, un20_time_write, un27_time_write, - un5_time_write, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : lpp_waveform_snapshot_160_12 - Use entity work.lpp_waveform_snapshot_160_12(DEF_ARCH); - for all : lpp_waveform_snapshot_controler - Use entity work.lpp_waveform_snapshot_controler(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\(DEF_ARCH); - for all : lpp_waveform_burst - Use entity work.lpp_waveform_burst(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\(DEF_ARCH); - for all : lpp_waveform_fifo - Use entity work.lpp_waveform_fifo(DEF_ARCH); - for all : lpp_waveform_snapshot_160_11 - Use entity work.lpp_waveform_snapshot_160_11(DEF_ARCH); - for all : lpp_waveform_snapshot_160_12_1 - Use entity work.lpp_waveform_snapshot_160_12_1(DEF_ARCH); - for all : lpp_waveform_dma - Use entity work.lpp_waveform_dma(DEF_ARCH); - for all : lpp_waveform_fifo_arbiter - Use entity work.lpp_waveform_fifo_arbiter(DEF_ARCH); -begin - - - un7_nb_snapshot_param_more_one_I_45 : XOR2 - port map(A => N_19, B => nb_snapshot_param(8), Y => I_45_11); - - un7_nb_snapshot_param_more_one_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => nb_snapshot_param(6), Y => N_24); - - un7_nb_snapshot_param_more_one_I_16 : AND3 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), C => nb_snapshot_param(2), Y => - \DWACT_FINC_E[0]\); - - lpp_waveform_snapshot_f1 : lpp_waveform_snapshot_160_12 - port map(sample_f1_wdata_95 => sample_f1_wdata_95, - sample_f1_wdata_94 => sample_f1_wdata_94, - sample_f1_wdata_93 => sample_f1_wdata_93, - sample_f1_wdata_92 => sample_f1_wdata_92, - sample_f1_wdata_91 => sample_f1_wdata_91, - sample_f1_wdata_90 => sample_f1_wdata_90, - sample_f1_wdata_89 => sample_f1_wdata_89, - sample_f1_wdata_88 => sample_f1_wdata_88, - sample_f1_wdata_87 => sample_f1_wdata_87, - sample_f1_wdata_86 => sample_f1_wdata_86, - sample_f1_wdata_85 => sample_f1_wdata_85, - sample_f1_wdata_84 => sample_f1_wdata_84, - sample_f1_wdata_83 => sample_f1_wdata_83, - sample_f1_wdata_82 => sample_f1_wdata_82, - sample_f1_wdata_81 => sample_f1_wdata_81, - sample_f1_wdata_80 => sample_f1_wdata_80, - sample_f1_wdata_79 => sample_f1_wdata_79, - sample_f1_wdata_78 => sample_f1_wdata_78, - sample_f1_wdata_77 => sample_f1_wdata_77, - sample_f1_wdata_76 => sample_f1_wdata_76, - sample_f1_wdata_75 => sample_f1_wdata_75, - sample_f1_wdata_74 => sample_f1_wdata_74, - sample_f1_wdata_73 => sample_f1_wdata_73, - sample_f1_wdata_72 => sample_f1_wdata_72, - sample_f1_wdata_71 => sample_f1_wdata_71, - sample_f1_wdata_70 => sample_f1_wdata_70, - sample_f1_wdata_69 => sample_f1_wdata_69, - sample_f1_wdata_68 => sample_f1_wdata_68, - sample_f1_wdata_67 => sample_f1_wdata_67, - sample_f1_wdata_66 => sample_f1_wdata_66, - sample_f1_wdata_65 => sample_f1_wdata_65, - sample_f1_wdata_64 => sample_f1_wdata_64, - sample_f1_wdata_63 => sample_f1_wdata_63, - sample_f1_wdata_62 => sample_f1_wdata_62, - sample_f1_wdata_61 => sample_f1_wdata_61, - sample_f1_wdata_60 => sample_f1_wdata_60, - sample_f1_wdata_59 => sample_f1_wdata_59, - sample_f1_wdata_58 => sample_f1_wdata_58, - sample_f1_wdata_57 => sample_f1_wdata_57, - sample_f1_wdata_56 => sample_f1_wdata_56, - sample_f1_wdata_55 => sample_f1_wdata_55, - sample_f1_wdata_54 => sample_f1_wdata_54, - sample_f1_wdata_53 => sample_f1_wdata_53, - sample_f1_wdata_52 => sample_f1_wdata_52, - sample_f1_wdata_51 => sample_f1_wdata_51, - sample_f1_wdata_50 => sample_f1_wdata_50, - sample_f1_wdata_49 => sample_f1_wdata_49, - sample_f1_wdata_48 => sample_f1_wdata_48, - sample_f1_wdata_15 => sample_f1_wdata_15, - sample_f1_wdata_14 => sample_f1_wdata_14, - sample_f1_wdata_13 => sample_f1_wdata_13, - sample_f1_wdata_12 => sample_f1_wdata_12, - sample_f1_wdata_11 => sample_f1_wdata_11, - sample_f1_wdata_10 => sample_f1_wdata_10, - sample_f1_wdata_9 => sample_f1_wdata_9, sample_f1_wdata_8 - => sample_f1_wdata_8, sample_f1_wdata_7 => - sample_f1_wdata_7, sample_f1_wdata_6 => sample_f1_wdata_6, - sample_f1_wdata_5 => sample_f1_wdata_5, sample_f1_wdata_4 - => sample_f1_wdata_4, sample_f1_wdata_3 => - sample_f1_wdata_3, sample_f1_wdata_2 => sample_f1_wdata_2, - sample_f1_wdata_1 => sample_f1_wdata_1, sample_f1_wdata_0 - => sample_f1_wdata_0, data_f1_out(159) => - \data_f1_out[159]\, data_f1_out(158) => - \data_f1_out[158]\, data_f1_out(157) => - \data_f1_out[157]\, data_f1_out(156) => - \data_f1_out[156]\, data_f1_out(155) => - \data_f1_out[155]\, data_f1_out(154) => - \data_f1_out[154]\, data_f1_out(153) => - \data_f1_out[153]\, data_f1_out(152) => - \data_f1_out[152]\, data_f1_out(151) => - \data_f1_out[151]\, data_f1_out(150) => - \data_f1_out[150]\, data_f1_out(149) => - \data_f1_out[149]\, data_f1_out(148) => - \data_f1_out[148]\, data_f1_out(147) => - \data_f1_out[147]\, data_f1_out(146) => - \data_f1_out[146]\, data_f1_out(145) => - \data_f1_out[145]\, data_f1_out(144) => - \data_f1_out[144]\, data_f1_out(143) => - \data_f1_out[143]\, data_f1_out(142) => - \data_f1_out[142]\, data_f1_out(141) => - \data_f1_out[141]\, data_f1_out(140) => - \data_f1_out[140]\, data_f1_out(139) => - \data_f1_out[139]\, data_f1_out(138) => - \data_f1_out[138]\, data_f1_out(137) => - \data_f1_out[137]\, data_f1_out(136) => - \data_f1_out[136]\, data_f1_out(135) => - \data_f1_out[135]\, data_f1_out(134) => - \data_f1_out[134]\, data_f1_out(133) => - \data_f1_out[133]\, data_f1_out(132) => - \data_f1_out[132]\, data_f1_out(131) => - \data_f1_out[131]\, data_f1_out(130) => - \data_f1_out[130]\, data_f1_out(129) => - \data_f1_out[129]\, data_f1_out(128) => - \data_f1_out[128]\, data_f1_out(127) => - \data_f1_out[127]\, data_f1_out(126) => - \data_f1_out[126]\, data_f1_out(125) => - \data_f1_out[125]\, data_f1_out(124) => - \data_f1_out[124]\, data_f1_out(123) => - \data_f1_out[123]\, data_f1_out(122) => - \data_f1_out[122]\, data_f1_out(121) => - \data_f1_out[121]\, data_f1_out(120) => - \data_f1_out[120]\, data_f1_out(119) => - \data_f1_out[119]\, data_f1_out(118) => - \data_f1_out[118]\, data_f1_out(117) => - \data_f1_out[117]\, data_f1_out(116) => - \data_f1_out[116]\, data_f1_out(115) => - \data_f1_out[115]\, data_f1_out(114) => - \data_f1_out[114]\, data_f1_out(113) => - \data_f1_out[113]\, data_f1_out(112) => - \data_f1_out[112]\, data_f1_out(111) => - \data_f1_out[111]\, data_f1_out(110) => - \data_f1_out[110]\, data_f1_out(109) => - \data_f1_out[109]\, data_f1_out(108) => - \data_f1_out[108]\, data_f1_out(107) => - \data_f1_out[107]\, data_f1_out(106) => - \data_f1_out[106]\, data_f1_out(105) => - \data_f1_out[105]\, data_f1_out(104) => - \data_f1_out[104]\, data_f1_out(103) => - \data_f1_out[103]\, data_f1_out(102) => - \data_f1_out[102]\, data_f1_out(101) => - \data_f1_out[101]\, data_f1_out(100) => - \data_f1_out[100]\, data_f1_out(99) => \data_f1_out[99]\, - data_f1_out(98) => \data_f1_out[98]\, data_f1_out(97) => - \data_f1_out[97]\, data_f1_out(96) => \data_f1_out[96]\, - data_f1_out(95) => \data_f1_out[95]\, data_f1_out(94) => - \data_f1_out[94]\, data_f1_out(93) => \data_f1_out[93]\, - data_f1_out(92) => \data_f1_out[92]\, data_f1_out(91) => - \data_f1_out[91]\, data_f1_out(90) => \data_f1_out[90]\, - data_f1_out(89) => \data_f1_out[89]\, data_f1_out(88) => - \data_f1_out[88]\, data_f1_out(87) => \data_f1_out[87]\, - data_f1_out(86) => \data_f1_out[86]\, data_f1_out(85) => - \data_f1_out[85]\, data_f1_out(84) => \data_f1_out[84]\, - data_f1_out(83) => \data_f1_out[83]\, data_f1_out(82) => - \data_f1_out[82]\, data_f1_out(81) => \data_f1_out[81]\, - data_f1_out(80) => \data_f1_out[80]\, data_f1_out(79) => - \data_f1_out[79]\, data_f1_out(78) => \data_f1_out[78]\, - data_f1_out(77) => \data_f1_out[77]\, data_f1_out(76) => - \data_f1_out[76]\, data_f1_out(75) => \data_f1_out[75]\, - data_f1_out(74) => \data_f1_out[74]\, data_f1_out(73) => - \data_f1_out[73]\, data_f1_out(72) => \data_f1_out[72]\, - data_f1_out(71) => \data_f1_out[71]\, data_f1_out(70) => - \data_f1_out[70]\, data_f1_out(69) => \data_f1_out[69]\, - data_f1_out(68) => \data_f1_out[68]\, data_f1_out(67) => - \data_f1_out[67]\, data_f1_out(66) => \data_f1_out[66]\, - data_f1_out(65) => \data_f1_out[65]\, data_f1_out(64) => - \data_f1_out[64]\, sample_f1_37 => sample_f1_37, - sample_f1_5 => sample_f1_5, sample_f1_38 => sample_f1_38, - sample_f1_6 => sample_f1_6, sample_f1_39 => sample_f1_39, - sample_f1_7 => sample_f1_7, sample_f1_40 => sample_f1_40, - sample_f1_8 => sample_f1_8, sample_f1_41 => sample_f1_41, - sample_f1_9 => sample_f1_9, sample_f1_42 => sample_f1_42, - sample_f1_10 => sample_f1_10, sample_f1_43 => - sample_f1_43, sample_f1_11 => sample_f1_11, sample_f1_61 - => sample_f1_61, sample_f1_62 => sample_f1_62, - sample_f1_63 => sample_f1_63, sample_f1_32 => - sample_f1_32, sample_f1_0 => sample_f1_0, sample_f1_33 - => sample_f1_33, sample_f1_1 => sample_f1_1, - sample_f1_34 => sample_f1_34, sample_f1_2 => sample_f1_2, - sample_f1_35 => sample_f1_35, sample_f1_3 => sample_f1_3, - sample_f1_36 => sample_f1_36, sample_f1_4 => sample_f1_4, - sample_f1_48 => sample_f1_48, sample_f1_49 => - sample_f1_49, sample_f1_50 => sample_f1_50, sample_f1_51 - => sample_f1_51, sample_f1_52 => sample_f1_52, - sample_f1_53 => sample_f1_53, sample_f1_54 => - sample_f1_54, sample_f1_55 => sample_f1_55, sample_f1_56 - => sample_f1_56, sample_f1_57 => sample_f1_57, - sample_f1_58 => sample_f1_58, sample_f1_59 => - sample_f1_59, sample_f1_60 => sample_f1_60, sample_f1_44 - => sample_f1_44, sample_f1_12 => sample_f1_12, - sample_f1_45 => sample_f1_45, sample_f1_13 => - sample_f1_13, sample_f1_46 => sample_f1_46, sample_f1_14 - => sample_f1_14, sample_f1_47 => sample_f1_47, - sample_f1_15 => sample_f1_15, nb_snapshot_param(0) => - nb_snapshot_param(0), rstn => rstn, lclk_c => lclk_c, - data_f1_out_valid => data_f1_out_valid, data_shaping_R1 - => data_shaping_R1, data_shaping_R1_0 => - data_shaping_R1_0, I_9_31 => I_9_31, I_45_11 => I_45_11, - I_52_11 => I_52_11, I_56_12 => I_56_12, I_24_16 => - I_24_16, N_4 => N_4, I_20_23 => I_20_23, I_13_35 => - I_13_35, I_38_12 => I_38_12, I_31_15 => I_31_15, I_5_31 - => I_5_31, enable_f1 => enable_f1, burst_f1 => burst_f1, - sample_f1_val_0 => sample_f1_val_0, start_snapshot_f1 => - start_snapshot_f1); - - lpp_waveform_snapshot_controler_1 : - lpp_waveform_snapshot_controler - port map(coarse_time_i(0) => coarse_time_i(0), - delta_f2_f0(9) => delta_f2_f0(9), delta_f2_f0(8) => - delta_f2_f0(8), delta_f2_f0(7) => delta_f2_f0(7), - delta_f2_f0(6) => delta_f2_f0(6), delta_f2_f0(5) => - delta_f2_f0(5), delta_f2_f0(4) => delta_f2_f0(4), - delta_f2_f0(3) => delta_f2_f0(3), delta_f2_f0(2) => - delta_f2_f0(2), delta_f2_f0(1) => delta_f2_f0(1), - delta_f2_f0(0) => delta_f2_f0(0), delta_f2_f1(9) => - delta_f2_f1(9), delta_f2_f1(8) => delta_f2_f1(8), - delta_f2_f1(7) => delta_f2_f1(7), delta_f2_f1(6) => - delta_f2_f1(6), delta_f2_f1(5) => delta_f2_f1(5), - delta_f2_f1(4) => delta_f2_f1(4), delta_f2_f1(3) => - delta_f2_f1(3), delta_f2_f1(2) => delta_f2_f1(2), - delta_f2_f1(1) => delta_f2_f1(1), delta_f2_f1(0) => - delta_f2_f1(0), delta_snapshot(15) => delta_snapshot(15), - delta_snapshot(14) => delta_snapshot(14), - delta_snapshot(13) => delta_snapshot(13), - delta_snapshot(12) => delta_snapshot(12), - delta_snapshot(11) => delta_snapshot(11), - delta_snapshot(10) => delta_snapshot(10), - delta_snapshot(9) => delta_snapshot(9), delta_snapshot(8) - => delta_snapshot(8), delta_snapshot(7) => - delta_snapshot(7), delta_snapshot(6) => delta_snapshot(6), - delta_snapshot(5) => delta_snapshot(5), delta_snapshot(4) - => delta_snapshot(4), delta_snapshot(3) => - delta_snapshot(3), delta_snapshot(2) => delta_snapshot(2), - delta_snapshot(1) => delta_snapshot(1), delta_snapshot(0) - => delta_snapshot(0), coarse_time(0) => coarse_time(0), - start_snapshot_f2 => start_snapshot_f2, start_snapshot_f1 - => start_snapshot_f1, start_snapshot_f0 => - start_snapshot_f0, sample_f2_val => sample_f2_val, - sample_f0_val_0 => sample_f0_val_0, rstn => rstn, lclk_c - => lclk_c); - - un7_nb_snapshot_param_more_one_I_20 : XOR2 - port map(A => N_37, B => nb_snapshot_param(4), Y => I_20_23); - - \all_input_valid.3.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - port map(status_new_err(3) => status_new_err(3), - valid_ack(3) => \valid_ack[3]\, valid_out(3) => - \valid_out[3]\, rstn => rstn, lclk_c => lclk_c, - data_f3_out_valid => data_f3_out_valid); - - un7_nb_snapshot_param_more_one_I_52 : XOR2 - port map(A => N_14, B => nb_snapshot_param(9), Y => I_52_11); - - VCC_i : VCC - port map(Y => \VCC\); - - un7_nb_snapshot_param_more_one_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - un7_nb_snapshot_param_more_one_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => nb_snapshot_param(3), - C => nb_snapshot_param(4), Y => N_34); - - un7_nb_snapshot_param_more_one_I_56 : XOR2 - port map(A => N_11, B => nb_snapshot_param(10), Y => - I_56_12); - - un7_nb_snapshot_param_more_one_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un7_nb_snapshot_param_more_one_I_19 : NOR2B - port map(A => nb_snapshot_param(3), B => \DWACT_FINC_E[0]\, - Y => N_37); - - un7_nb_snapshot_param_more_one_I_24 : XOR2 - port map(A => N_34, B => nb_snapshot_param(5), Y => I_24_16); - - un7_nb_snapshot_param_more_one_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_19); - - \all_input_valid.1.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - port map(status_new_err(1) => status_new_err(1), - valid_out_i(1) => \valid_out_i[1]\, valid_ack(1) => - \valid_ack[1]\, rstn => rstn, lclk_c => lclk_c, - data_f1_out_valid => data_f1_out_valid); - - un7_nb_snapshot_param_more_one_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => nb_snapshot_param(8), - C => nb_snapshot_param(9), Y => N_11); - - un7_nb_snapshot_param_more_one_I_13 : XOR2 - port map(A => N_42, B => nb_snapshot_param(3), Y => I_13_35); - - un7_nb_snapshot_param_more_one_I_9 : XOR2 - port map(A => N_45, B => nb_snapshot_param(2), Y => I_9_31); - - un7_nb_snapshot_param_more_one_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => nb_snapshot_param(9), - C => nb_snapshot_param(10), Y => N_4); - - un7_nb_snapshot_param_more_one_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => nb_snapshot_param(5), Y => N_29); - - GND_i : GND - port map(Y => \GND\); - - un7_nb_snapshot_param_more_one_I_59 : AND3 - port map(A => nb_snapshot_param(6), B => - nb_snapshot_param(7), C => nb_snapshot_param(8), Y => - \DWACT_FINC_E[5]\); - - lpp_waveform_burst_f3 : lpp_waveform_burst - port map(sample_f3_wdata(95) => sample_f3_wdata(95), - sample_f3_wdata(94) => sample_f3_wdata(94), - sample_f3_wdata(93) => sample_f3_wdata(93), - sample_f3_wdata(92) => sample_f3_wdata(92), - sample_f3_wdata(91) => sample_f3_wdata(91), - sample_f3_wdata(90) => sample_f3_wdata(90), - sample_f3_wdata(89) => sample_f3_wdata(89), - sample_f3_wdata(88) => sample_f3_wdata(88), - sample_f3_wdata(87) => sample_f3_wdata(87), - sample_f3_wdata(86) => sample_f3_wdata(86), - sample_f3_wdata(85) => sample_f3_wdata(85), - sample_f3_wdata(84) => sample_f3_wdata(84), - sample_f3_wdata(83) => sample_f3_wdata(83), - sample_f3_wdata(82) => sample_f3_wdata(82), - sample_f3_wdata(81) => sample_f3_wdata(81), - sample_f3_wdata(80) => sample_f3_wdata(80), - sample_f3_wdata(79) => sample_f3_wdata(79), - sample_f3_wdata(78) => sample_f3_wdata(78), - sample_f3_wdata(77) => sample_f3_wdata(77), - sample_f3_wdata(76) => sample_f3_wdata(76), - sample_f3_wdata(75) => sample_f3_wdata(75), - sample_f3_wdata(74) => sample_f3_wdata(74), - sample_f3_wdata(73) => sample_f3_wdata(73), - sample_f3_wdata(72) => sample_f3_wdata(72), - sample_f3_wdata(71) => sample_f3_wdata(71), - sample_f3_wdata(70) => sample_f3_wdata(70), - sample_f3_wdata(69) => sample_f3_wdata(69), - sample_f3_wdata(68) => sample_f3_wdata(68), - sample_f3_wdata(67) => sample_f3_wdata(67), - sample_f3_wdata(66) => sample_f3_wdata(66), - sample_f3_wdata(65) => sample_f3_wdata(65), - sample_f3_wdata(64) => sample_f3_wdata(64), - sample_f3_wdata(63) => sample_f3_wdata(63), - sample_f3_wdata(62) => sample_f3_wdata(62), - sample_f3_wdata(61) => sample_f3_wdata(61), - sample_f3_wdata(60) => sample_f3_wdata(60), - sample_f3_wdata(59) => sample_f3_wdata(59), - sample_f3_wdata(58) => sample_f3_wdata(58), - sample_f3_wdata(57) => sample_f3_wdata(57), - sample_f3_wdata(56) => sample_f3_wdata(56), - sample_f3_wdata(55) => sample_f3_wdata(55), - sample_f3_wdata(54) => sample_f3_wdata(54), - sample_f3_wdata(53) => sample_f3_wdata(53), - sample_f3_wdata(52) => sample_f3_wdata(52), - sample_f3_wdata(51) => sample_f3_wdata(51), - sample_f3_wdata(50) => sample_f3_wdata(50), - sample_f3_wdata(49) => sample_f3_wdata(49), - sample_f3_wdata(48) => sample_f3_wdata(48), - sample_f3_wdata(47) => sample_f3_wdata(47), - sample_f3_wdata(46) => sample_f3_wdata(46), - sample_f3_wdata(45) => sample_f3_wdata(45), - sample_f3_wdata(44) => sample_f3_wdata(44), - sample_f3_wdata(43) => sample_f3_wdata(43), - sample_f3_wdata(42) => sample_f3_wdata(42), - sample_f3_wdata(41) => sample_f3_wdata(41), - sample_f3_wdata(40) => sample_f3_wdata(40), - sample_f3_wdata(39) => sample_f3_wdata(39), - sample_f3_wdata(38) => sample_f3_wdata(38), - sample_f3_wdata(37) => sample_f3_wdata(37), - sample_f3_wdata(36) => sample_f3_wdata(36), - sample_f3_wdata(35) => sample_f3_wdata(35), - sample_f3_wdata(34) => sample_f3_wdata(34), - sample_f3_wdata(33) => sample_f3_wdata(33), - sample_f3_wdata(32) => sample_f3_wdata(32), - sample_f3_wdata(31) => sample_f3_wdata(31), - sample_f3_wdata(30) => sample_f3_wdata(30), - sample_f3_wdata(29) => sample_f3_wdata(29), - sample_f3_wdata(28) => sample_f3_wdata(28), - sample_f3_wdata(27) => sample_f3_wdata(27), - sample_f3_wdata(26) => sample_f3_wdata(26), - sample_f3_wdata(25) => sample_f3_wdata(25), - sample_f3_wdata(24) => sample_f3_wdata(24), - sample_f3_wdata(23) => sample_f3_wdata(23), - sample_f3_wdata(22) => sample_f3_wdata(22), - sample_f3_wdata(21) => sample_f3_wdata(21), - sample_f3_wdata(20) => sample_f3_wdata(20), - sample_f3_wdata(19) => sample_f3_wdata(19), - sample_f3_wdata(18) => sample_f3_wdata(18), - sample_f3_wdata(17) => sample_f3_wdata(17), - sample_f3_wdata(16) => sample_f3_wdata(16), - sample_f3_wdata(15) => sample_f3_wdata(15), - sample_f3_wdata(14) => sample_f3_wdata(14), - sample_f3_wdata(13) => sample_f3_wdata(13), - sample_f3_wdata(12) => sample_f3_wdata(12), - sample_f3_wdata(11) => sample_f3_wdata(11), - sample_f3_wdata(10) => sample_f3_wdata(10), - sample_f3_wdata(9) => sample_f3_wdata(9), - sample_f3_wdata(8) => sample_f3_wdata(8), - sample_f3_wdata(7) => sample_f3_wdata(7), - sample_f3_wdata(6) => sample_f3_wdata(6), - sample_f3_wdata(5) => sample_f3_wdata(5), - sample_f3_wdata(4) => sample_f3_wdata(4), - sample_f3_wdata(3) => sample_f3_wdata(3), - sample_f3_wdata(2) => sample_f3_wdata(2), - sample_f3_wdata(1) => sample_f3_wdata(1), - sample_f3_wdata(0) => sample_f3_wdata(0), - data_f3_out(159) => \data_f3_out[159]\, data_f3_out(158) - => \data_f3_out[158]\, data_f3_out(157) => - \data_f3_out[157]\, data_f3_out(156) => - \data_f3_out[156]\, data_f3_out(155) => - \data_f3_out[155]\, data_f3_out(154) => - \data_f3_out[154]\, data_f3_out(153) => - \data_f3_out[153]\, data_f3_out(152) => - \data_f3_out[152]\, data_f3_out(151) => - \data_f3_out[151]\, data_f3_out(150) => - \data_f3_out[150]\, data_f3_out(149) => - \data_f3_out[149]\, data_f3_out(148) => - \data_f3_out[148]\, data_f3_out(147) => - \data_f3_out[147]\, data_f3_out(146) => - \data_f3_out[146]\, data_f3_out(145) => - \data_f3_out[145]\, data_f3_out(144) => - \data_f3_out[144]\, data_f3_out(143) => - \data_f3_out[143]\, data_f3_out(142) => - \data_f3_out[142]\, data_f3_out(141) => - \data_f3_out[141]\, data_f3_out(140) => - \data_f3_out[140]\, data_f3_out(139) => - \data_f3_out[139]\, data_f3_out(138) => - \data_f3_out[138]\, data_f3_out(137) => - \data_f3_out[137]\, data_f3_out(136) => - \data_f3_out[136]\, data_f3_out(135) => - \data_f3_out[135]\, data_f3_out(134) => - \data_f3_out[134]\, data_f3_out(133) => - \data_f3_out[133]\, data_f3_out(132) => - \data_f3_out[132]\, data_f3_out(131) => - \data_f3_out[131]\, data_f3_out(130) => - \data_f3_out[130]\, data_f3_out(129) => - \data_f3_out[129]\, data_f3_out(128) => - \data_f3_out[128]\, data_f3_out(127) => - \data_f3_out[127]\, data_f3_out(126) => - \data_f3_out[126]\, data_f3_out(125) => - \data_f3_out[125]\, data_f3_out(124) => - \data_f3_out[124]\, data_f3_out(123) => - \data_f3_out[123]\, data_f3_out(122) => - \data_f3_out[122]\, data_f3_out(121) => - \data_f3_out[121]\, data_f3_out(120) => - \data_f3_out[120]\, data_f3_out(119) => - \data_f3_out[119]\, data_f3_out(118) => - \data_f3_out[118]\, data_f3_out(117) => - \data_f3_out[117]\, data_f3_out(116) => - \data_f3_out[116]\, data_f3_out(115) => - \data_f3_out[115]\, data_f3_out(114) => - \data_f3_out[114]\, data_f3_out(113) => - \data_f3_out[113]\, data_f3_out(112) => - \data_f3_out[112]\, data_f3_out(111) => - \data_f3_out[111]\, data_f3_out(110) => - \data_f3_out[110]\, data_f3_out(109) => - \data_f3_out[109]\, data_f3_out(108) => - \data_f3_out[108]\, data_f3_out(107) => - \data_f3_out[107]\, data_f3_out(106) => - \data_f3_out[106]\, data_f3_out(105) => - \data_f3_out[105]\, data_f3_out(104) => - \data_f3_out[104]\, data_f3_out(103) => - \data_f3_out[103]\, data_f3_out(102) => - \data_f3_out[102]\, data_f3_out(101) => - \data_f3_out[101]\, data_f3_out(100) => - \data_f3_out[100]\, data_f3_out(99) => \data_f3_out[99]\, - data_f3_out(98) => \data_f3_out[98]\, data_f3_out(97) => - \data_f3_out[97]\, data_f3_out(96) => \data_f3_out[96]\, - data_f3_out(95) => \data_f3_out[95]\, data_f3_out(94) => - \data_f3_out[94]\, data_f3_out(93) => \data_f3_out[93]\, - data_f3_out(92) => \data_f3_out[92]\, data_f3_out(91) => - \data_f3_out[91]\, data_f3_out(90) => \data_f3_out[90]\, - data_f3_out(89) => \data_f3_out[89]\, data_f3_out(88) => - \data_f3_out[88]\, data_f3_out(87) => \data_f3_out[87]\, - data_f3_out(86) => \data_f3_out[86]\, data_f3_out(85) => - \data_f3_out[85]\, data_f3_out(84) => \data_f3_out[84]\, - data_f3_out(83) => \data_f3_out[83]\, data_f3_out(82) => - \data_f3_out[82]\, data_f3_out(81) => \data_f3_out[81]\, - data_f3_out(80) => \data_f3_out[80]\, data_f3_out(79) => - \data_f3_out[79]\, data_f3_out(78) => \data_f3_out[78]\, - data_f3_out(77) => \data_f3_out[77]\, data_f3_out(76) => - \data_f3_out[76]\, data_f3_out(75) => \data_f3_out[75]\, - data_f3_out(74) => \data_f3_out[74]\, data_f3_out(73) => - \data_f3_out[73]\, data_f3_out(72) => \data_f3_out[72]\, - data_f3_out(71) => \data_f3_out[71]\, data_f3_out(70) => - \data_f3_out[70]\, data_f3_out(69) => \data_f3_out[69]\, - data_f3_out(68) => \data_f3_out[68]\, data_f3_out(67) => - \data_f3_out[67]\, data_f3_out(66) => \data_f3_out[66]\, - data_f3_out(65) => \data_f3_out[65]\, data_f3_out(64) => - \data_f3_out[64]\, rstn => rstn, lclk_c => lclk_c, - data_f3_out_valid => data_f3_out_valid, enable_f3 => - enable_f3, sample_f3_val => sample_f3_val); - - \all_input_valid.2.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - port map(status_new_err(2) => status_new_err(2), - valid_ack(2) => \valid_ack[2]\, valid_out(2) => - \valid_out[2]\, rstn => rstn, lclk_c => lclk_c, - data_f2_out_valid => data_f2_out_valid); - - un7_nb_snapshot_param_more_one_I_41 : AND2 - port map(A => nb_snapshot_param(6), B => - nb_snapshot_param(7), Y => \DWACT_FINC_E[3]\); - - un7_nb_snapshot_param_more_one_I_38 : XOR2 - port map(A => N_24, B => nb_snapshot_param(7), Y => I_38_12); - - \all_input_valid.0.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - port map(status_new_err(0) => status_new_err(0), - valid_ack(0) => \valid_ack[0]\, valid_out(0) => - \valid_out[0]\, rstn => rstn, lclk_c => lclk_c, - data_f0_out_valid => data_f0_out_valid); - - un7_nb_snapshot_param_more_one_I_27 : AND2 - port map(A => nb_snapshot_param(3), B => - nb_snapshot_param(4), Y => \DWACT_FINC_E[1]\); - - un7_nb_snapshot_param_more_one_I_34 : AND3 - port map(A => nb_snapshot_param(3), B => - nb_snapshot_param(4), C => nb_snapshot_param(5), Y => - \DWACT_FINC_E[2]\); - - un7_nb_snapshot_param_more_one_I_8 : NOR2B - port map(A => nb_snapshot_param(1), B => - nb_snapshot_param(0), Y => N_45); - - lpp_waveform_fifo_1 : lpp_waveform_fifo - port map(ready_i_0_i_0(1) => \ready_i_0_i_0[1]\, - data_wen(3) => \data_wen[3]\, data_wen(2) => - \data_wen[2]\, data_wen(1) => \data_wen[1]\, data_wen(0) - => \data_wen[0]\, data_ren(3) => \data_ren[3]\, - data_ren(2) => \data_ren[2]\, data_ren(1) => - \data_ren[1]\, data_ren(0) => \data_ren[0]\, ready_i_0_2 - => \ready_i_0[2]\, ready_i_0_0 => \ready_i_0[0]\, - ready_i_0_3 => \ready_i_0[3]\, time_ren(3) => - \time_ren[3]\, time_ren(2) => \time_ren[2]\, time_ren(1) - => \time_ren[1]\, time_ren(0) => \time_ren[0]\, - time_wen(3) => \time_wen[3]\, time_wen(2) => - \time_wen[2]\, time_wen(1) => \time_wen[1]\, time_wen(0) - => \time_wen[0]\, hwdata(31) => hwdata(31), hwdata(30) - => hwdata(30), hwdata(29) => hwdata(29), hwdata(28) => - hwdata(28), hwdata(27) => hwdata(27), hwdata(26) => - hwdata(26), hwdata(25) => hwdata(25), hwdata(24) => - hwdata(24), hwdata(23) => hwdata(23), hwdata(22) => - hwdata(22), hwdata(21) => hwdata(21), hwdata(20) => - hwdata(20), hwdata(19) => hwdata(19), hwdata(18) => - hwdata(18), hwdata(17) => hwdata(17), hwdata(16) => - hwdata(16), hwdata(15) => hwdata(15), hwdata(14) => - hwdata(14), hwdata(13) => hwdata(13), hwdata(12) => - hwdata(12), hwdata(11) => hwdata(11), hwdata(10) => - hwdata(10), hwdata(9) => hwdata(9), hwdata(8) => - hwdata(8), hwdata(7) => hwdata(7), hwdata(6) => hwdata(6), - hwdata(5) => hwdata(5), hwdata(4) => hwdata(4), hwdata(3) - => hwdata(3), hwdata(2) => hwdata(2), hwdata(1) => - hwdata(1), hwdata(0) => hwdata(0), wdata(31) => - \wdata[31]\, wdata(30) => \wdata[30]\, wdata(29) => - \wdata[29]\, wdata(28) => \wdata[28]\, wdata(27) => - \wdata[27]\, wdata(26) => \wdata[26]\, wdata(25) => - \wdata[25]\, wdata(24) => \wdata[24]\, wdata(23) => - \wdata[23]\, wdata(22) => \wdata[22]\, wdata(21) => - \wdata[21]\, wdata(20) => \wdata[20]\, wdata(19) => - \wdata[19]\, wdata(18) => \wdata[18]\, wdata(17) => - \wdata[17]\, wdata(16) => \wdata[16]\, wdata(15) => - \wdata[15]\, wdata(14) => \wdata[14]\, wdata(13) => - \wdata[13]\, wdata(12) => \wdata[12]\, wdata(11) => - \wdata[11]\, wdata(10) => \wdata[10]\, wdata(9) => - \wdata[9]\, wdata(8) => \wdata[8]\, wdata(7) => - \wdata[7]\, wdata(6) => \wdata[6]\, wdata(5) => - \wdata[5]\, wdata(4) => \wdata[4]\, wdata(3) => - \wdata[3]\, wdata(2) => \wdata[2]\, wdata(1) => - \wdata[1]\, wdata(0) => \wdata[0]\, time_ren_1z => - time_ren, data_ren_1z => data_ren, un13_time_write => - un13_time_write, un20_time_write => un20_time_write, - un27_time_write => un27_time_write, un5_time_write => - un5_time_write, rstn => rstn, lclk_c => lclk_c); - - lpp_waveform_snapshot_f0 : lpp_waveform_snapshot_160_11 - port map(sample_f0_wdata_95 => sample_f0_wdata_95, - sample_f0_wdata_94 => sample_f0_wdata_94, - sample_f0_wdata_93 => sample_f0_wdata_93, - sample_f0_wdata_92 => sample_f0_wdata_92, - sample_f0_wdata_91 => sample_f0_wdata_91, - sample_f0_wdata_90 => sample_f0_wdata_90, - sample_f0_wdata_89 => sample_f0_wdata_89, - sample_f0_wdata_88 => sample_f0_wdata_88, - sample_f0_wdata_87 => sample_f0_wdata_87, - sample_f0_wdata_86 => sample_f0_wdata_86, - sample_f0_wdata_85 => sample_f0_wdata_85, - sample_f0_wdata_84 => sample_f0_wdata_84, - sample_f0_wdata_83 => sample_f0_wdata_83, - sample_f0_wdata_82 => sample_f0_wdata_82, - sample_f0_wdata_81 => sample_f0_wdata_81, - sample_f0_wdata_80 => sample_f0_wdata_80, - sample_f0_wdata_79 => sample_f0_wdata_79, - sample_f0_wdata_78 => sample_f0_wdata_78, - sample_f0_wdata_77 => sample_f0_wdata_77, - sample_f0_wdata_76 => sample_f0_wdata_76, - sample_f0_wdata_75 => sample_f0_wdata_75, - sample_f0_wdata_74 => sample_f0_wdata_74, - sample_f0_wdata_73 => sample_f0_wdata_73, - sample_f0_wdata_72 => sample_f0_wdata_72, - sample_f0_wdata_71 => sample_f0_wdata_71, - sample_f0_wdata_70 => sample_f0_wdata_70, - sample_f0_wdata_69 => sample_f0_wdata_69, - sample_f0_wdata_68 => sample_f0_wdata_68, - sample_f0_wdata_67 => sample_f0_wdata_67, - sample_f0_wdata_66 => sample_f0_wdata_66, - sample_f0_wdata_65 => sample_f0_wdata_65, - sample_f0_wdata_64 => sample_f0_wdata_64, - sample_f0_wdata_63 => sample_f0_wdata_63, - sample_f0_wdata_62 => sample_f0_wdata_62, - sample_f0_wdata_61 => sample_f0_wdata_61, - sample_f0_wdata_60 => sample_f0_wdata_60, - sample_f0_wdata_59 => sample_f0_wdata_59, - sample_f0_wdata_58 => sample_f0_wdata_58, - sample_f0_wdata_57 => sample_f0_wdata_57, - sample_f0_wdata_56 => sample_f0_wdata_56, - sample_f0_wdata_55 => sample_f0_wdata_55, - sample_f0_wdata_54 => sample_f0_wdata_54, - sample_f0_wdata_53 => sample_f0_wdata_53, - sample_f0_wdata_52 => sample_f0_wdata_52, - sample_f0_wdata_51 => sample_f0_wdata_51, - sample_f0_wdata_50 => sample_f0_wdata_50, - sample_f0_wdata_49 => sample_f0_wdata_49, - sample_f0_wdata_48 => sample_f0_wdata_48, - sample_f0_wdata_15 => sample_f0_wdata_15, - sample_f0_wdata_14 => sample_f0_wdata_14, - sample_f0_wdata_13 => sample_f0_wdata_13, - sample_f0_wdata_12 => sample_f0_wdata_12, - sample_f0_wdata_11 => sample_f0_wdata_11, - sample_f0_wdata_10 => sample_f0_wdata_10, - sample_f0_wdata_9 => sample_f0_wdata_9, sample_f0_wdata_8 - => sample_f0_wdata_8, sample_f0_wdata_7 => - sample_f0_wdata_7, sample_f0_wdata_6 => sample_f0_wdata_6, - sample_f0_wdata_5 => sample_f0_wdata_5, sample_f0_wdata_4 - => sample_f0_wdata_4, sample_f0_wdata_3 => - sample_f0_wdata_3, sample_f0_wdata_2 => sample_f0_wdata_2, - sample_f0_wdata_1 => sample_f0_wdata_1, sample_f0_wdata_0 - => sample_f0_wdata_0, data_f0_out(159) => - \data_f0_out[159]\, data_f0_out(158) => - \data_f0_out[158]\, data_f0_out(157) => - \data_f0_out[157]\, data_f0_out(156) => - \data_f0_out[156]\, data_f0_out(155) => - \data_f0_out[155]\, data_f0_out(154) => - \data_f0_out[154]\, data_f0_out(153) => - \data_f0_out[153]\, data_f0_out(152) => - \data_f0_out[152]\, data_f0_out(151) => - \data_f0_out[151]\, data_f0_out(150) => - \data_f0_out[150]\, data_f0_out(149) => - \data_f0_out[149]\, data_f0_out(148) => - \data_f0_out[148]\, data_f0_out(147) => - \data_f0_out[147]\, data_f0_out(146) => - \data_f0_out[146]\, data_f0_out(145) => - \data_f0_out[145]\, data_f0_out(144) => - \data_f0_out[144]\, data_f0_out(143) => - \data_f0_out[143]\, data_f0_out(142) => - \data_f0_out[142]\, data_f0_out(141) => - \data_f0_out[141]\, data_f0_out(140) => - \data_f0_out[140]\, data_f0_out(139) => - \data_f0_out[139]\, data_f0_out(138) => - \data_f0_out[138]\, data_f0_out(137) => - \data_f0_out[137]\, data_f0_out(136) => - \data_f0_out[136]\, data_f0_out(135) => - \data_f0_out[135]\, data_f0_out(134) => - \data_f0_out[134]\, data_f0_out(133) => - \data_f0_out[133]\, data_f0_out(132) => - \data_f0_out[132]\, data_f0_out(131) => - \data_f0_out[131]\, data_f0_out(130) => - \data_f0_out[130]\, data_f0_out(129) => - \data_f0_out[129]\, data_f0_out(128) => - \data_f0_out[128]\, data_f0_out(127) => - \data_f0_out[127]\, data_f0_out(126) => - \data_f0_out[126]\, data_f0_out(125) => - \data_f0_out[125]\, data_f0_out(124) => - \data_f0_out[124]\, data_f0_out(123) => - \data_f0_out[123]\, data_f0_out(122) => - \data_f0_out[122]\, data_f0_out(121) => - \data_f0_out[121]\, data_f0_out(120) => - \data_f0_out[120]\, data_f0_out(119) => - \data_f0_out[119]\, data_f0_out(118) => - \data_f0_out[118]\, data_f0_out(117) => - \data_f0_out[117]\, data_f0_out(116) => - \data_f0_out[116]\, data_f0_out(115) => - \data_f0_out[115]\, data_f0_out(114) => - \data_f0_out[114]\, data_f0_out(113) => - \data_f0_out[113]\, data_f0_out(112) => - \data_f0_out[112]\, data_f0_out(111) => - \data_f0_out[111]\, data_f0_out(110) => - \data_f0_out[110]\, data_f0_out(109) => - \data_f0_out[109]\, data_f0_out(108) => - \data_f0_out[108]\, data_f0_out(107) => - \data_f0_out[107]\, data_f0_out(106) => - \data_f0_out[106]\, data_f0_out(105) => - \data_f0_out[105]\, data_f0_out(104) => - \data_f0_out[104]\, data_f0_out(103) => - \data_f0_out[103]\, data_f0_out(102) => - \data_f0_out[102]\, data_f0_out(101) => - \data_f0_out[101]\, data_f0_out(100) => - \data_f0_out[100]\, data_f0_out(99) => \data_f0_out[99]\, - data_f0_out(98) => \data_f0_out[98]\, data_f0_out(97) => - \data_f0_out[97]\, data_f0_out(96) => \data_f0_out[96]\, - data_f0_out(95) => \data_f0_out[95]\, data_f0_out(94) => - \data_f0_out[94]\, data_f0_out(93) => \data_f0_out[93]\, - data_f0_out(92) => \data_f0_out[92]\, data_f0_out(91) => - \data_f0_out[91]\, data_f0_out(90) => \data_f0_out[90]\, - data_f0_out(89) => \data_f0_out[89]\, data_f0_out(88) => - \data_f0_out[88]\, data_f0_out(87) => \data_f0_out[87]\, - data_f0_out(86) => \data_f0_out[86]\, data_f0_out(85) => - \data_f0_out[85]\, data_f0_out(84) => \data_f0_out[84]\, - data_f0_out(83) => \data_f0_out[83]\, data_f0_out(82) => - \data_f0_out[82]\, data_f0_out(81) => \data_f0_out[81]\, - data_f0_out(80) => \data_f0_out[80]\, data_f0_out(79) => - \data_f0_out[79]\, data_f0_out(78) => \data_f0_out[78]\, - data_f0_out(77) => \data_f0_out[77]\, data_f0_out(76) => - \data_f0_out[76]\, data_f0_out(75) => \data_f0_out[75]\, - data_f0_out(74) => \data_f0_out[74]\, data_f0_out(73) => - \data_f0_out[73]\, data_f0_out(72) => \data_f0_out[72]\, - data_f0_out(71) => \data_f0_out[71]\, data_f0_out(70) => - \data_f0_out[70]\, data_f0_out(69) => \data_f0_out[69]\, - data_f0_out(68) => \data_f0_out[68]\, data_f0_out(67) => - \data_f0_out[67]\, data_f0_out(66) => \data_f0_out[66]\, - data_f0_out(65) => \data_f0_out[65]\, data_f0_out(64) => - \data_f0_out[64]\, sample_f0_37 => sample_f0_37, - sample_f0_5 => sample_f0_5, sample_f0_38 => sample_f0_38, - sample_f0_6 => sample_f0_6, sample_f0_39 => sample_f0_39, - sample_f0_7 => sample_f0_7, sample_f0_40 => sample_f0_40, - sample_f0_8 => sample_f0_8, sample_f0_41 => sample_f0_41, - sample_f0_9 => sample_f0_9, sample_f0_42 => sample_f0_42, - sample_f0_10 => sample_f0_10, sample_f0_43 => - sample_f0_43, sample_f0_11 => sample_f0_11, sample_f0_61 - => sample_f0_61, sample_f0_62 => sample_f0_62, - sample_f0_63 => sample_f0_63, sample_f0_32 => - sample_f0_32, sample_f0_0 => sample_f0_0, sample_f0_33 - => sample_f0_33, sample_f0_1 => sample_f0_1, - sample_f0_34 => sample_f0_34, sample_f0_2 => sample_f0_2, - sample_f0_35 => sample_f0_35, sample_f0_3 => sample_f0_3, - sample_f0_36 => sample_f0_36, sample_f0_4 => sample_f0_4, - sample_f0_48 => sample_f0_48, sample_f0_49 => - sample_f0_49, sample_f0_50 => sample_f0_50, sample_f0_51 - => sample_f0_51, sample_f0_52 => sample_f0_52, - sample_f0_53 => sample_f0_53, sample_f0_54 => - sample_f0_54, sample_f0_55 => sample_f0_55, sample_f0_56 - => sample_f0_56, sample_f0_57 => sample_f0_57, - sample_f0_58 => sample_f0_58, sample_f0_59 => - sample_f0_59, sample_f0_60 => sample_f0_60, sample_f0_44 - => sample_f0_44, sample_f0_12 => sample_f0_12, - sample_f0_45 => sample_f0_45, sample_f0_13 => - sample_f0_13, sample_f0_46 => sample_f0_46, sample_f0_14 - => sample_f0_14, sample_f0_47 => sample_f0_47, - sample_f0_15 => sample_f0_15, nb_snapshot_param(10) => - nb_snapshot_param(10), nb_snapshot_param(9) => - nb_snapshot_param(9), nb_snapshot_param(8) => - nb_snapshot_param(8), nb_snapshot_param(7) => - nb_snapshot_param(7), nb_snapshot_param(6) => - nb_snapshot_param(6), nb_snapshot_param(5) => - nb_snapshot_param(5), nb_snapshot_param(4) => - nb_snapshot_param(4), nb_snapshot_param(3) => - nb_snapshot_param(3), nb_snapshot_param(2) => - nb_snapshot_param(2), nb_snapshot_param(1) => - nb_snapshot_param(1), nb_snapshot_param(0) => - nb_snapshot_param(0), rstn => rstn, lclk_c => lclk_c, - data_f0_out_valid => data_f0_out_valid, data_shaping_R0 - => data_shaping_R0, data_shaping_R0_0 => - data_shaping_R0_0, enable_f0 => enable_f0, - start_snapshot_f0 => start_snapshot_f0, sample_f0_val_0 - => sample_f0_val_0, burst_f0 => burst_f0); - - un7_nb_snapshot_param_more_one_I_31 : XOR2 - port map(A => N_29, B => nb_snapshot_param(6), Y => I_31_15); - - lpp_waveform_snapshot_f2 : lpp_waveform_snapshot_160_12_1 - port map(sample_f2_wdata(95) => sample_f2_wdata(95), - sample_f2_wdata(94) => sample_f2_wdata(94), - sample_f2_wdata(93) => sample_f2_wdata(93), - sample_f2_wdata(92) => sample_f2_wdata(92), - sample_f2_wdata(91) => sample_f2_wdata(91), - sample_f2_wdata(90) => sample_f2_wdata(90), - sample_f2_wdata(89) => sample_f2_wdata(89), - sample_f2_wdata(88) => sample_f2_wdata(88), - sample_f2_wdata(87) => sample_f2_wdata(87), - sample_f2_wdata(86) => sample_f2_wdata(86), - sample_f2_wdata(85) => sample_f2_wdata(85), - sample_f2_wdata(84) => sample_f2_wdata(84), - sample_f2_wdata(83) => sample_f2_wdata(83), - sample_f2_wdata(82) => sample_f2_wdata(82), - sample_f2_wdata(81) => sample_f2_wdata(81), - sample_f2_wdata(80) => sample_f2_wdata(80), - sample_f2_wdata(79) => sample_f2_wdata(79), - sample_f2_wdata(78) => sample_f2_wdata(78), - sample_f2_wdata(77) => sample_f2_wdata(77), - sample_f2_wdata(76) => sample_f2_wdata(76), - sample_f2_wdata(75) => sample_f2_wdata(75), - sample_f2_wdata(74) => sample_f2_wdata(74), - sample_f2_wdata(73) => sample_f2_wdata(73), - sample_f2_wdata(72) => sample_f2_wdata(72), - sample_f2_wdata(71) => sample_f2_wdata(71), - sample_f2_wdata(70) => sample_f2_wdata(70), - sample_f2_wdata(69) => sample_f2_wdata(69), - sample_f2_wdata(68) => sample_f2_wdata(68), - sample_f2_wdata(67) => sample_f2_wdata(67), - sample_f2_wdata(66) => sample_f2_wdata(66), - sample_f2_wdata(65) => sample_f2_wdata(65), - sample_f2_wdata(64) => sample_f2_wdata(64), - sample_f2_wdata(63) => sample_f2_wdata(63), - sample_f2_wdata(62) => sample_f2_wdata(62), - sample_f2_wdata(61) => sample_f2_wdata(61), - sample_f2_wdata(60) => sample_f2_wdata(60), - sample_f2_wdata(59) => sample_f2_wdata(59), - sample_f2_wdata(58) => sample_f2_wdata(58), - sample_f2_wdata(57) => sample_f2_wdata(57), - sample_f2_wdata(56) => sample_f2_wdata(56), - sample_f2_wdata(55) => sample_f2_wdata(55), - sample_f2_wdata(54) => sample_f2_wdata(54), - sample_f2_wdata(53) => sample_f2_wdata(53), - sample_f2_wdata(52) => sample_f2_wdata(52), - sample_f2_wdata(51) => sample_f2_wdata(51), - sample_f2_wdata(50) => sample_f2_wdata(50), - sample_f2_wdata(49) => sample_f2_wdata(49), - sample_f2_wdata(48) => sample_f2_wdata(48), - sample_f2_wdata(47) => sample_f2_wdata(47), - sample_f2_wdata(46) => sample_f2_wdata(46), - sample_f2_wdata(45) => sample_f2_wdata(45), - sample_f2_wdata(44) => sample_f2_wdata(44), - sample_f2_wdata(43) => sample_f2_wdata(43), - sample_f2_wdata(42) => sample_f2_wdata(42), - sample_f2_wdata(41) => sample_f2_wdata(41), - sample_f2_wdata(40) => sample_f2_wdata(40), - sample_f2_wdata(39) => sample_f2_wdata(39), - sample_f2_wdata(38) => sample_f2_wdata(38), - sample_f2_wdata(37) => sample_f2_wdata(37), - sample_f2_wdata(36) => sample_f2_wdata(36), - sample_f2_wdata(35) => sample_f2_wdata(35), - sample_f2_wdata(34) => sample_f2_wdata(34), - sample_f2_wdata(33) => sample_f2_wdata(33), - sample_f2_wdata(32) => sample_f2_wdata(32), - sample_f2_wdata(31) => sample_f2_wdata(31), - sample_f2_wdata(30) => sample_f2_wdata(30), - sample_f2_wdata(29) => sample_f2_wdata(29), - sample_f2_wdata(28) => sample_f2_wdata(28), - sample_f2_wdata(27) => sample_f2_wdata(27), - sample_f2_wdata(26) => sample_f2_wdata(26), - sample_f2_wdata(25) => sample_f2_wdata(25), - sample_f2_wdata(24) => sample_f2_wdata(24), - sample_f2_wdata(23) => sample_f2_wdata(23), - sample_f2_wdata(22) => sample_f2_wdata(22), - sample_f2_wdata(21) => sample_f2_wdata(21), - sample_f2_wdata(20) => sample_f2_wdata(20), - sample_f2_wdata(19) => sample_f2_wdata(19), - sample_f2_wdata(18) => sample_f2_wdata(18), - sample_f2_wdata(17) => sample_f2_wdata(17), - sample_f2_wdata(16) => sample_f2_wdata(16), - sample_f2_wdata(15) => sample_f2_wdata(15), - sample_f2_wdata(14) => sample_f2_wdata(14), - sample_f2_wdata(13) => sample_f2_wdata(13), - sample_f2_wdata(12) => sample_f2_wdata(12), - sample_f2_wdata(11) => sample_f2_wdata(11), - sample_f2_wdata(10) => sample_f2_wdata(10), - sample_f2_wdata(9) => sample_f2_wdata(9), - sample_f2_wdata(8) => sample_f2_wdata(8), - sample_f2_wdata(7) => sample_f2_wdata(7), - sample_f2_wdata(6) => sample_f2_wdata(6), - sample_f2_wdata(5) => sample_f2_wdata(5), - sample_f2_wdata(4) => sample_f2_wdata(4), - sample_f2_wdata(3) => sample_f2_wdata(3), - sample_f2_wdata(2) => sample_f2_wdata(2), - sample_f2_wdata(1) => sample_f2_wdata(1), - sample_f2_wdata(0) => sample_f2_wdata(0), - data_f2_out(159) => \data_f2_out[159]\, data_f2_out(158) - => \data_f2_out[158]\, data_f2_out(157) => - \data_f2_out[157]\, data_f2_out(156) => - \data_f2_out[156]\, data_f2_out(155) => - \data_f2_out[155]\, data_f2_out(154) => - \data_f2_out[154]\, data_f2_out(153) => - \data_f2_out[153]\, data_f2_out(152) => - \data_f2_out[152]\, data_f2_out(151) => - \data_f2_out[151]\, data_f2_out(150) => - \data_f2_out[150]\, data_f2_out(149) => - \data_f2_out[149]\, data_f2_out(148) => - \data_f2_out[148]\, data_f2_out(147) => - \data_f2_out[147]\, data_f2_out(146) => - \data_f2_out[146]\, data_f2_out(145) => - \data_f2_out[145]\, data_f2_out(144) => - \data_f2_out[144]\, data_f2_out(143) => - \data_f2_out[143]\, data_f2_out(142) => - \data_f2_out[142]\, data_f2_out(141) => - \data_f2_out[141]\, data_f2_out(140) => - \data_f2_out[140]\, data_f2_out(139) => - \data_f2_out[139]\, data_f2_out(138) => - \data_f2_out[138]\, data_f2_out(137) => - \data_f2_out[137]\, data_f2_out(136) => - \data_f2_out[136]\, data_f2_out(135) => - \data_f2_out[135]\, data_f2_out(134) => - \data_f2_out[134]\, data_f2_out(133) => - \data_f2_out[133]\, data_f2_out(132) => - \data_f2_out[132]\, data_f2_out(131) => - \data_f2_out[131]\, data_f2_out(130) => - \data_f2_out[130]\, data_f2_out(129) => - \data_f2_out[129]\, data_f2_out(128) => - \data_f2_out[128]\, data_f2_out(127) => - \data_f2_out[127]\, data_f2_out(126) => - \data_f2_out[126]\, data_f2_out(125) => - \data_f2_out[125]\, data_f2_out(124) => - \data_f2_out[124]\, data_f2_out(123) => - \data_f2_out[123]\, data_f2_out(122) => - \data_f2_out[122]\, data_f2_out(121) => - \data_f2_out[121]\, data_f2_out(120) => - \data_f2_out[120]\, data_f2_out(119) => - \data_f2_out[119]\, data_f2_out(118) => - \data_f2_out[118]\, data_f2_out(117) => - \data_f2_out[117]\, data_f2_out(116) => - \data_f2_out[116]\, data_f2_out(115) => - \data_f2_out[115]\, data_f2_out(114) => - \data_f2_out[114]\, data_f2_out(113) => - \data_f2_out[113]\, data_f2_out(112) => - \data_f2_out[112]\, data_f2_out(111) => - \data_f2_out[111]\, data_f2_out(110) => - \data_f2_out[110]\, data_f2_out(109) => - \data_f2_out[109]\, data_f2_out(108) => - \data_f2_out[108]\, data_f2_out(107) => - \data_f2_out[107]\, data_f2_out(106) => - \data_f2_out[106]\, data_f2_out(105) => - \data_f2_out[105]\, data_f2_out(104) => - \data_f2_out[104]\, data_f2_out(103) => - \data_f2_out[103]\, data_f2_out(102) => - \data_f2_out[102]\, data_f2_out(101) => - \data_f2_out[101]\, data_f2_out(100) => - \data_f2_out[100]\, data_f2_out(99) => \data_f2_out[99]\, - data_f2_out(98) => \data_f2_out[98]\, data_f2_out(97) => - \data_f2_out[97]\, data_f2_out(96) => \data_f2_out[96]\, - data_f2_out(95) => \data_f2_out[95]\, data_f2_out(94) => - \data_f2_out[94]\, data_f2_out(93) => \data_f2_out[93]\, - data_f2_out(92) => \data_f2_out[92]\, data_f2_out(91) => - \data_f2_out[91]\, data_f2_out(90) => \data_f2_out[90]\, - data_f2_out(89) => \data_f2_out[89]\, data_f2_out(88) => - \data_f2_out[88]\, data_f2_out(87) => \data_f2_out[87]\, - data_f2_out(86) => \data_f2_out[86]\, data_f2_out(85) => - \data_f2_out[85]\, data_f2_out(84) => \data_f2_out[84]\, - data_f2_out(83) => \data_f2_out[83]\, data_f2_out(82) => - \data_f2_out[82]\, data_f2_out(81) => \data_f2_out[81]\, - data_f2_out(80) => \data_f2_out[80]\, data_f2_out(79) => - \data_f2_out[79]\, data_f2_out(78) => \data_f2_out[78]\, - data_f2_out(77) => \data_f2_out[77]\, data_f2_out(76) => - \data_f2_out[76]\, data_f2_out(75) => \data_f2_out[75]\, - data_f2_out(74) => \data_f2_out[74]\, data_f2_out(73) => - \data_f2_out[73]\, data_f2_out(72) => \data_f2_out[72]\, - data_f2_out(71) => \data_f2_out[71]\, data_f2_out(70) => - \data_f2_out[70]\, data_f2_out(69) => \data_f2_out[69]\, - data_f2_out(68) => \data_f2_out[68]\, data_f2_out(67) => - \data_f2_out[67]\, data_f2_out(66) => \data_f2_out[66]\, - data_f2_out(65) => \data_f2_out[65]\, data_f2_out(64) => - \data_f2_out[64]\, nb_snapshot_param(0) => - nb_snapshot_param(0), rstn => rstn, lclk_c => lclk_c, - data_f2_out_valid => data_f2_out_valid, I_9_31 => I_9_31, - I_45_11 => I_45_11, I_52_11 => I_52_11, I_38_12 => - I_38_12, N_4 => N_4, I_56_12 => I_56_12, I_24_16 => - I_24_16, I_5_31 => I_5_31, I_20_23 => I_20_23, I_13_35 - => I_13_35, I_31_15 => I_31_15, start_snapshot_f2 => - start_snapshot_f2, sample_f2_val => sample_f2_val, - enable_f2 => enable_f2, burst_f2 => burst_f2); - - un7_nb_snapshot_param_more_one_I_12 : AND3 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), C => nb_snapshot_param(2), Y => - N_42); - - un7_nb_snapshot_param_more_one_I_5 : XOR2 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), Y => I_5_31); - - un7_nb_snapshot_param_more_one_I_51 : NOR2B - port map(A => nb_snapshot_param(8), B => \DWACT_FINC_E[4]\, - Y => N_14); - - pp_waveform_dma_1 : lpp_waveform_dma - port map(addr_data_f0(31) => addr_data_f0(31), - addr_data_f0(30) => addr_data_f0(30), addr_data_f0(29) - => addr_data_f0(29), addr_data_f0(28) => - addr_data_f0(28), addr_data_f0(27) => addr_data_f0(27), - addr_data_f0(26) => addr_data_f0(26), addr_data_f0(25) - => addr_data_f0(25), addr_data_f0(24) => - addr_data_f0(24), addr_data_f0(23) => addr_data_f0(23), - addr_data_f0(22) => addr_data_f0(22), addr_data_f0(21) - => addr_data_f0(21), addr_data_f0(20) => - addr_data_f0(20), addr_data_f0(19) => addr_data_f0(19), - addr_data_f0(18) => addr_data_f0(18), addr_data_f0(17) - => addr_data_f0(17), addr_data_f0(16) => - addr_data_f0(16), addr_data_f0(15) => addr_data_f0(15), - addr_data_f0(14) => addr_data_f0(14), addr_data_f0(13) - => addr_data_f0(13), addr_data_f0(12) => - addr_data_f0(12), addr_data_f0(11) => addr_data_f0(11), - addr_data_f0(10) => addr_data_f0(10), addr_data_f0(9) => - addr_data_f0(9), addr_data_f0(8) => addr_data_f0(8), - addr_data_f0(7) => addr_data_f0(7), addr_data_f0(6) => - addr_data_f0(6), addr_data_f0(5) => addr_data_f0(5), - addr_data_f0(4) => addr_data_f0(4), addr_data_f0(3) => - addr_data_f0(3), addr_data_f0(2) => addr_data_f0(2), - addr_data_f0(1) => addr_data_f0(1), addr_data_f0(0) => - addr_data_f0(0), addr_data_f1(31) => addr_data_f1(31), - addr_data_f1(30) => addr_data_f1(30), addr_data_f1(29) - => addr_data_f1(29), addr_data_f1(28) => - addr_data_f1(28), addr_data_f1(27) => addr_data_f1(27), - addr_data_f1(26) => addr_data_f1(26), addr_data_f1(25) - => addr_data_f1(25), addr_data_f1(24) => - addr_data_f1(24), addr_data_f1(23) => addr_data_f1(23), - addr_data_f1(22) => addr_data_f1(22), addr_data_f1(21) - => addr_data_f1(21), addr_data_f1(20) => - addr_data_f1(20), addr_data_f1(19) => addr_data_f1(19), - addr_data_f1(18) => addr_data_f1(18), addr_data_f1(17) - => addr_data_f1(17), addr_data_f1(16) => - addr_data_f1(16), addr_data_f1(15) => addr_data_f1(15), - addr_data_f1(14) => addr_data_f1(14), addr_data_f1(13) - => addr_data_f1(13), addr_data_f1(12) => - addr_data_f1(12), addr_data_f1(11) => addr_data_f1(11), - addr_data_f1(10) => addr_data_f1(10), addr_data_f1(9) => - addr_data_f1(9), addr_data_f1(8) => addr_data_f1(8), - addr_data_f1(7) => addr_data_f1(7), addr_data_f1(6) => - addr_data_f1(6), addr_data_f1(5) => addr_data_f1(5), - addr_data_f1(4) => addr_data_f1(4), addr_data_f1(3) => - addr_data_f1(3), addr_data_f1(2) => addr_data_f1(2), - addr_data_f1(1) => addr_data_f1(1), addr_data_f1(0) => - addr_data_f1(0), addr_data_f2(31) => addr_data_f2(31), - addr_data_f2(30) => addr_data_f2(30), addr_data_f2(29) - => addr_data_f2(29), addr_data_f2(28) => - addr_data_f2(28), addr_data_f2(27) => addr_data_f2(27), - addr_data_f2(26) => addr_data_f2(26), addr_data_f2(25) - => addr_data_f2(25), addr_data_f2(24) => - addr_data_f2(24), addr_data_f2(23) => addr_data_f2(23), - addr_data_f2(22) => addr_data_f2(22), addr_data_f2(21) - => addr_data_f2(21), addr_data_f2(20) => - addr_data_f2(20), addr_data_f2(19) => addr_data_f2(19), - addr_data_f2(18) => addr_data_f2(18), addr_data_f2(17) - => addr_data_f2(17), addr_data_f2(16) => - addr_data_f2(16), addr_data_f2(15) => addr_data_f2(15), - addr_data_f2(14) => addr_data_f2(14), addr_data_f2(13) - => addr_data_f2(13), addr_data_f2(12) => - addr_data_f2(12), addr_data_f2(11) => addr_data_f2(11), - addr_data_f2(10) => addr_data_f2(10), addr_data_f2(9) => - addr_data_f2(9), addr_data_f2(8) => addr_data_f2(8), - addr_data_f2(7) => addr_data_f2(7), addr_data_f2(6) => - addr_data_f2(6), addr_data_f2(5) => addr_data_f2(5), - addr_data_f2(4) => addr_data_f2(4), addr_data_f2(3) => - addr_data_f2(3), addr_data_f2(2) => addr_data_f2(2), - addr_data_f2(1) => addr_data_f2(1), addr_data_f2(0) => - addr_data_f2(0), addr_data_f3(31) => addr_data_f3(31), - addr_data_f3(30) => addr_data_f3(30), addr_data_f3(29) - => addr_data_f3(29), addr_data_f3(28) => - addr_data_f3(28), addr_data_f3(27) => addr_data_f3(27), - addr_data_f3(26) => addr_data_f3(26), addr_data_f3(25) - => addr_data_f3(25), addr_data_f3(24) => - addr_data_f3(24), addr_data_f3(23) => addr_data_f3(23), - addr_data_f3(22) => addr_data_f3(22), addr_data_f3(21) - => addr_data_f3(21), addr_data_f3(20) => - addr_data_f3(20), addr_data_f3(19) => addr_data_f3(19), - addr_data_f3(18) => addr_data_f3(18), addr_data_f3(17) - => addr_data_f3(17), addr_data_f3(16) => - addr_data_f3(16), addr_data_f3(15) => addr_data_f3(15), - addr_data_f3(14) => addr_data_f3(14), addr_data_f3(13) - => addr_data_f3(13), addr_data_f3(12) => - addr_data_f3(12), addr_data_f3(11) => addr_data_f3(11), - addr_data_f3(10) => addr_data_f3(10), addr_data_f3(9) => - addr_data_f3(9), addr_data_f3(8) => addr_data_f3(8), - addr_data_f3(7) => addr_data_f3(7), addr_data_f3(6) => - addr_data_f3(6), addr_data_f3(5) => addr_data_f3(5), - addr_data_f3(4) => addr_data_f3(4), addr_data_f3(3) => - addr_data_f3(3), addr_data_f3(2) => addr_data_f3(2), - addr_data_f3(1) => addr_data_f3(1), addr_data_f3(0) => - addr_data_f3(0), status_full(3) => status_full(3), - status_full(2) => status_full(2), status_full(1) => - status_full(1), status_full(0) => status_full(0), - status_full_err(3) => status_full_err(3), - status_full_err(2) => status_full_err(2), - status_full_err(1) => status_full_err(1), - status_full_err(0) => status_full_err(0), - nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), l1_0_m(1) - => l1_0_m(1), nhmaster_1_iv_0(1) => nhmaster_1_iv_0(1), - bco_msb_1_m(1) => bco_msb_1_m(1), iosn_0(93) => - iosn_0(93), hgrant(3) => hgrant(3), - hmaster_0_0_RNIFCVH1_0(1) => hmaster_0_0_RNIFCVH1_0(1), - bco_msb_1(1) => bco_msb_1(1), haddr(31) => haddr(31), - haddr(30) => haddr(30), haddr(29) => haddr(29), haddr(28) - => haddr(28), haddr(27) => haddr(27), haddr(26) => - haddr(26), haddr(25) => haddr(25), haddr(24) => haddr(24), - haddr(23) => haddr(23), haddr(22) => haddr(22), haddr(21) - => haddr(21), haddr(20) => haddr(20), haddr(19) => - haddr(19), haddr(18) => haddr(18), haddr(17) => haddr(17), - haddr(16) => haddr(16), haddr(15) => haddr(15), haddr(14) - => haddr(14), haddr(13) => haddr(13), haddr(12) => - haddr(12), haddr(11) => haddr(11), haddr(10) => haddr(10), - haddr(9) => haddr(9), haddr(8) => haddr(8), haddr(7) => - haddr(7), haddr(6) => haddr(6), haddr(5) => haddr(5), - haddr(4) => haddr(4), haddr(3) => haddr(3), haddr(2) => - haddr(2), haddr(1) => haddr(1), haddr(0) => haddr(0), - hmaster_0(1) => hmaster_0(1), hsize(1) => hsize(1), - hsize(0) => hsize(0), nhmaster_1_i(0) => nhmaster_1_i(0), - iosn_1(93) => iosn_1(93), hresp(0) => hresp(0), - iosn_2(93) => iosn_2(93), htrans(1) => htrans(1), - htrans(0) => htrans(0), hburst(2) => hburst(2), hburst(1) - => hburst(1), hburst(0) => hburst(0), status_full_ack(3) - => status_full_ack(3), status_full_ack(2) => - status_full_ack(2), status_full_ack(1) => - status_full_ack(1), status_full_ack(0) => - status_full_ack(0), data_ren(3) => \data_ren[3]\, - data_ren(2) => \data_ren[2]\, data_ren(1) => - \data_ren[1]\, data_ren(0) => \data_ren[0]\, - ready_i_0_i_0(1) => \ready_i_0_i_0[1]\, ready_i_0_2 => - \ready_i_0[2]\, ready_i_0_0 => \ready_i_0[0]\, - ready_i_0_3 => \ready_i_0[3]\, time_ren(3) => - \time_ren[3]\, time_ren(2) => \time_ren[2]\, time_ren(1) - => \time_ren[1]\, time_ren(0) => \time_ren[0]\, - time_ren_1z => time_ren, data_ren_1z => data_ren, - m26_m1_e => m26_m1_e, m19_a1_6_i_0 => m19_a1_6_i_0, - m19_a0_6_i_0 => m19_a0_6_i_0, m19_0_N_15_i_0_li => - m19_0_N_15_i_0_li, rstoutl_RNIGJKSJO => rstoutl_RNIGJKSJO, - un1_nhmaster_0_sqmuxa_1 => un1_nhmaster_0_sqmuxa_1, - Lock_RNIU86D => Lock_RNIU86D, hbusreq_i_3 => hbusreq_i_3, - arb_1 => arb_1, un1_dmain_6 => un1_dmain_6, hwrite => - hwrite, IdlePhase => IdlePhase, un13_time_write => - un13_time_write, un5_time_write => un5_time_write, - un27_time_write => un27_time_write, un20_time_write => - un20_time_write, rstn => rstn, lclk_c => lclk_c); - - lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter - port map(wdata(31) => \wdata[31]\, wdata(30) => \wdata[30]\, - wdata(29) => \wdata[29]\, wdata(28) => \wdata[28]\, - wdata(27) => \wdata[27]\, wdata(26) => \wdata[26]\, - wdata(25) => \wdata[25]\, wdata(24) => \wdata[24]\, - wdata(23) => \wdata[23]\, wdata(22) => \wdata[22]\, - wdata(21) => \wdata[21]\, wdata(20) => \wdata[20]\, - wdata(19) => \wdata[19]\, wdata(18) => \wdata[18]\, - wdata(17) => \wdata[17]\, wdata(16) => \wdata[16]\, - wdata(15) => \wdata[15]\, wdata(14) => \wdata[14]\, - wdata(13) => \wdata[13]\, wdata(12) => \wdata[12]\, - wdata(11) => \wdata[11]\, wdata(10) => \wdata[10]\, - wdata(9) => \wdata[9]\, wdata(8) => \wdata[8]\, wdata(7) - => \wdata[7]\, wdata(6) => \wdata[6]\, wdata(5) => - \wdata[5]\, wdata(4) => \wdata[4]\, wdata(3) => - \wdata[3]\, wdata(2) => \wdata[2]\, wdata(1) => - \wdata[1]\, wdata(0) => \wdata[0]\, data_wen(3) => - \data_wen[3]\, data_wen(2) => \data_wen[2]\, data_wen(1) - => \data_wen[1]\, data_wen(0) => \data_wen[0]\, - valid_ack(3) => \valid_ack[3]\, valid_ack(2) => - \valid_ack[2]\, valid_ack(1) => \valid_ack[1]\, - valid_ack(0) => \valid_ack[0]\, time_wen(3) => - \time_wen[3]\, time_wen(2) => \time_wen[2]\, time_wen(1) - => \time_wen[1]\, time_wen(0) => \time_wen[0]\, - data_f3_out(159) => \data_f3_out[159]\, data_f3_out(158) - => \data_f3_out[158]\, data_f3_out(157) => - \data_f3_out[157]\, data_f3_out(156) => - \data_f3_out[156]\, data_f3_out(155) => - \data_f3_out[155]\, data_f3_out(154) => - \data_f3_out[154]\, data_f3_out(153) => - \data_f3_out[153]\, data_f3_out(152) => - \data_f3_out[152]\, data_f3_out(151) => - \data_f3_out[151]\, data_f3_out(150) => - \data_f3_out[150]\, data_f3_out(149) => - \data_f3_out[149]\, data_f3_out(148) => - \data_f3_out[148]\, data_f3_out(147) => - \data_f3_out[147]\, data_f3_out(146) => - \data_f3_out[146]\, data_f3_out(145) => - \data_f3_out[145]\, data_f3_out(144) => - \data_f3_out[144]\, data_f3_out(143) => - \data_f3_out[143]\, data_f3_out(142) => - \data_f3_out[142]\, data_f3_out(141) => - \data_f3_out[141]\, data_f3_out(140) => - \data_f3_out[140]\, data_f3_out(139) => - \data_f3_out[139]\, data_f3_out(138) => - \data_f3_out[138]\, data_f3_out(137) => - \data_f3_out[137]\, data_f3_out(136) => - \data_f3_out[136]\, data_f3_out(135) => - \data_f3_out[135]\, data_f3_out(134) => - \data_f3_out[134]\, data_f3_out(133) => - \data_f3_out[133]\, data_f3_out(132) => - \data_f3_out[132]\, data_f3_out(131) => - \data_f3_out[131]\, data_f3_out(130) => - \data_f3_out[130]\, data_f3_out(129) => - \data_f3_out[129]\, data_f3_out(128) => - \data_f3_out[128]\, data_f3_out(127) => - \data_f3_out[127]\, data_f3_out(126) => - \data_f3_out[126]\, data_f3_out(125) => - \data_f3_out[125]\, data_f3_out(124) => - \data_f3_out[124]\, data_f3_out(123) => - \data_f3_out[123]\, data_f3_out(122) => - \data_f3_out[122]\, data_f3_out(121) => - \data_f3_out[121]\, data_f3_out(120) => - \data_f3_out[120]\, data_f3_out(119) => - \data_f3_out[119]\, data_f3_out(118) => - \data_f3_out[118]\, data_f3_out(117) => - \data_f3_out[117]\, data_f3_out(116) => - \data_f3_out[116]\, data_f3_out(115) => - \data_f3_out[115]\, data_f3_out(114) => - \data_f3_out[114]\, data_f3_out(113) => - \data_f3_out[113]\, data_f3_out(112) => - \data_f3_out[112]\, data_f3_out(111) => - \data_f3_out[111]\, data_f3_out(110) => - \data_f3_out[110]\, data_f3_out(109) => - \data_f3_out[109]\, data_f3_out(108) => - \data_f3_out[108]\, data_f3_out(107) => - \data_f3_out[107]\, data_f3_out(106) => - \data_f3_out[106]\, data_f3_out(105) => - \data_f3_out[105]\, data_f3_out(104) => - \data_f3_out[104]\, data_f3_out(103) => - \data_f3_out[103]\, data_f3_out(102) => - \data_f3_out[102]\, data_f3_out(101) => - \data_f3_out[101]\, data_f3_out(100) => - \data_f3_out[100]\, data_f3_out(99) => \data_f3_out[99]\, - data_f3_out(98) => \data_f3_out[98]\, data_f3_out(97) => - \data_f3_out[97]\, data_f3_out(96) => \data_f3_out[96]\, - data_f3_out(95) => \data_f3_out[95]\, data_f3_out(94) => - \data_f3_out[94]\, data_f3_out(93) => \data_f3_out[93]\, - data_f3_out(92) => \data_f3_out[92]\, data_f3_out(91) => - \data_f3_out[91]\, data_f3_out(90) => \data_f3_out[90]\, - data_f3_out(89) => \data_f3_out[89]\, data_f3_out(88) => - \data_f3_out[88]\, data_f3_out(87) => \data_f3_out[87]\, - data_f3_out(86) => \data_f3_out[86]\, data_f3_out(85) => - \data_f3_out[85]\, data_f3_out(84) => \data_f3_out[84]\, - data_f3_out(83) => \data_f3_out[83]\, data_f3_out(82) => - \data_f3_out[82]\, data_f3_out(81) => \data_f3_out[81]\, - data_f3_out(80) => \data_f3_out[80]\, data_f3_out(79) => - \data_f3_out[79]\, data_f3_out(78) => \data_f3_out[78]\, - data_f3_out(77) => \data_f3_out[77]\, data_f3_out(76) => - \data_f3_out[76]\, data_f3_out(75) => \data_f3_out[75]\, - data_f3_out(74) => \data_f3_out[74]\, data_f3_out(73) => - \data_f3_out[73]\, data_f3_out(72) => \data_f3_out[72]\, - data_f3_out(71) => \data_f3_out[71]\, data_f3_out(70) => - \data_f3_out[70]\, data_f3_out(69) => \data_f3_out[69]\, - data_f3_out(68) => \data_f3_out[68]\, data_f3_out(67) => - \data_f3_out[67]\, data_f3_out(66) => \data_f3_out[66]\, - data_f3_out(65) => \data_f3_out[65]\, data_f3_out(64) => - \data_f3_out[64]\, data_f2_out(159) => \data_f2_out[159]\, - data_f2_out(158) => \data_f2_out[158]\, data_f2_out(157) - => \data_f2_out[157]\, data_f2_out(156) => - \data_f2_out[156]\, data_f2_out(155) => - \data_f2_out[155]\, data_f2_out(154) => - \data_f2_out[154]\, data_f2_out(153) => - \data_f2_out[153]\, data_f2_out(152) => - \data_f2_out[152]\, data_f2_out(151) => - \data_f2_out[151]\, data_f2_out(150) => - \data_f2_out[150]\, data_f2_out(149) => - \data_f2_out[149]\, data_f2_out(148) => - \data_f2_out[148]\, data_f2_out(147) => - \data_f2_out[147]\, data_f2_out(146) => - \data_f2_out[146]\, data_f2_out(145) => - \data_f2_out[145]\, data_f2_out(144) => - \data_f2_out[144]\, data_f2_out(143) => - \data_f2_out[143]\, data_f2_out(142) => - \data_f2_out[142]\, data_f2_out(141) => - \data_f2_out[141]\, data_f2_out(140) => - \data_f2_out[140]\, data_f2_out(139) => - \data_f2_out[139]\, data_f2_out(138) => - \data_f2_out[138]\, data_f2_out(137) => - \data_f2_out[137]\, data_f2_out(136) => - \data_f2_out[136]\, data_f2_out(135) => - \data_f2_out[135]\, data_f2_out(134) => - \data_f2_out[134]\, data_f2_out(133) => - \data_f2_out[133]\, data_f2_out(132) => - \data_f2_out[132]\, data_f2_out(131) => - \data_f2_out[131]\, data_f2_out(130) => - \data_f2_out[130]\, data_f2_out(129) => - \data_f2_out[129]\, data_f2_out(128) => - \data_f2_out[128]\, data_f2_out(127) => - \data_f2_out[127]\, data_f2_out(126) => - \data_f2_out[126]\, data_f2_out(125) => - \data_f2_out[125]\, data_f2_out(124) => - \data_f2_out[124]\, data_f2_out(123) => - \data_f2_out[123]\, data_f2_out(122) => - \data_f2_out[122]\, data_f2_out(121) => - \data_f2_out[121]\, data_f2_out(120) => - \data_f2_out[120]\, data_f2_out(119) => - \data_f2_out[119]\, data_f2_out(118) => - \data_f2_out[118]\, data_f2_out(117) => - \data_f2_out[117]\, data_f2_out(116) => - \data_f2_out[116]\, data_f2_out(115) => - \data_f2_out[115]\, data_f2_out(114) => - \data_f2_out[114]\, data_f2_out(113) => - \data_f2_out[113]\, data_f2_out(112) => - \data_f2_out[112]\, data_f2_out(111) => - \data_f2_out[111]\, data_f2_out(110) => - \data_f2_out[110]\, data_f2_out(109) => - \data_f2_out[109]\, data_f2_out(108) => - \data_f2_out[108]\, data_f2_out(107) => - \data_f2_out[107]\, data_f2_out(106) => - \data_f2_out[106]\, data_f2_out(105) => - \data_f2_out[105]\, data_f2_out(104) => - \data_f2_out[104]\, data_f2_out(103) => - \data_f2_out[103]\, data_f2_out(102) => - \data_f2_out[102]\, data_f2_out(101) => - \data_f2_out[101]\, data_f2_out(100) => - \data_f2_out[100]\, data_f2_out(99) => \data_f2_out[99]\, - data_f2_out(98) => \data_f2_out[98]\, data_f2_out(97) => - \data_f2_out[97]\, data_f2_out(96) => \data_f2_out[96]\, - data_f2_out(95) => \data_f2_out[95]\, data_f2_out(94) => - \data_f2_out[94]\, data_f2_out(93) => \data_f2_out[93]\, - data_f2_out(92) => \data_f2_out[92]\, data_f2_out(91) => - \data_f2_out[91]\, data_f2_out(90) => \data_f2_out[90]\, - data_f2_out(89) => \data_f2_out[89]\, data_f2_out(88) => - \data_f2_out[88]\, data_f2_out(87) => \data_f2_out[87]\, - data_f2_out(86) => \data_f2_out[86]\, data_f2_out(85) => - \data_f2_out[85]\, data_f2_out(84) => \data_f2_out[84]\, - data_f2_out(83) => \data_f2_out[83]\, data_f2_out(82) => - \data_f2_out[82]\, data_f2_out(81) => \data_f2_out[81]\, - data_f2_out(80) => \data_f2_out[80]\, data_f2_out(79) => - \data_f2_out[79]\, data_f2_out(78) => \data_f2_out[78]\, - data_f2_out(77) => \data_f2_out[77]\, data_f2_out(76) => - \data_f2_out[76]\, data_f2_out(75) => \data_f2_out[75]\, - data_f2_out(74) => \data_f2_out[74]\, data_f2_out(73) => - \data_f2_out[73]\, data_f2_out(72) => \data_f2_out[72]\, - data_f2_out(71) => \data_f2_out[71]\, data_f2_out(70) => - \data_f2_out[70]\, data_f2_out(69) => \data_f2_out[69]\, - data_f2_out(68) => \data_f2_out[68]\, data_f2_out(67) => - \data_f2_out[67]\, data_f2_out(66) => \data_f2_out[66]\, - data_f2_out(65) => \data_f2_out[65]\, data_f2_out(64) => - \data_f2_out[64]\, data_f1_out(159) => \data_f1_out[159]\, - data_f1_out(158) => \data_f1_out[158]\, data_f1_out(157) - => \data_f1_out[157]\, data_f1_out(156) => - \data_f1_out[156]\, data_f1_out(155) => - \data_f1_out[155]\, data_f1_out(154) => - \data_f1_out[154]\, data_f1_out(153) => - \data_f1_out[153]\, data_f1_out(152) => - \data_f1_out[152]\, data_f1_out(151) => - \data_f1_out[151]\, data_f1_out(150) => - \data_f1_out[150]\, data_f1_out(149) => - \data_f1_out[149]\, data_f1_out(148) => - \data_f1_out[148]\, data_f1_out(147) => - \data_f1_out[147]\, data_f1_out(146) => - \data_f1_out[146]\, data_f1_out(145) => - \data_f1_out[145]\, data_f1_out(144) => - \data_f1_out[144]\, data_f1_out(143) => - \data_f1_out[143]\, data_f1_out(142) => - \data_f1_out[142]\, data_f1_out(141) => - \data_f1_out[141]\, data_f1_out(140) => - \data_f1_out[140]\, data_f1_out(139) => - \data_f1_out[139]\, data_f1_out(138) => - \data_f1_out[138]\, data_f1_out(137) => - \data_f1_out[137]\, data_f1_out(136) => - \data_f1_out[136]\, data_f1_out(135) => - \data_f1_out[135]\, data_f1_out(134) => - \data_f1_out[134]\, data_f1_out(133) => - \data_f1_out[133]\, data_f1_out(132) => - \data_f1_out[132]\, data_f1_out(131) => - \data_f1_out[131]\, data_f1_out(130) => - \data_f1_out[130]\, data_f1_out(129) => - \data_f1_out[129]\, data_f1_out(128) => - \data_f1_out[128]\, data_f1_out(127) => - \data_f1_out[127]\, data_f1_out(126) => - \data_f1_out[126]\, data_f1_out(125) => - \data_f1_out[125]\, data_f1_out(124) => - \data_f1_out[124]\, data_f1_out(123) => - \data_f1_out[123]\, data_f1_out(122) => - \data_f1_out[122]\, data_f1_out(121) => - \data_f1_out[121]\, data_f1_out(120) => - \data_f1_out[120]\, data_f1_out(119) => - \data_f1_out[119]\, data_f1_out(118) => - \data_f1_out[118]\, data_f1_out(117) => - \data_f1_out[117]\, data_f1_out(116) => - \data_f1_out[116]\, data_f1_out(115) => - \data_f1_out[115]\, data_f1_out(114) => - \data_f1_out[114]\, data_f1_out(113) => - \data_f1_out[113]\, data_f1_out(112) => - \data_f1_out[112]\, data_f1_out(111) => - \data_f1_out[111]\, data_f1_out(110) => - \data_f1_out[110]\, data_f1_out(109) => - \data_f1_out[109]\, data_f1_out(108) => - \data_f1_out[108]\, data_f1_out(107) => - \data_f1_out[107]\, data_f1_out(106) => - \data_f1_out[106]\, data_f1_out(105) => - \data_f1_out[105]\, data_f1_out(104) => - \data_f1_out[104]\, data_f1_out(103) => - \data_f1_out[103]\, data_f1_out(102) => - \data_f1_out[102]\, data_f1_out(101) => - \data_f1_out[101]\, data_f1_out(100) => - \data_f1_out[100]\, data_f1_out(99) => \data_f1_out[99]\, - data_f1_out(98) => \data_f1_out[98]\, data_f1_out(97) => - \data_f1_out[97]\, data_f1_out(96) => \data_f1_out[96]\, - data_f1_out(95) => \data_f1_out[95]\, data_f1_out(94) => - \data_f1_out[94]\, data_f1_out(93) => \data_f1_out[93]\, - data_f1_out(92) => \data_f1_out[92]\, data_f1_out(91) => - \data_f1_out[91]\, data_f1_out(90) => \data_f1_out[90]\, - data_f1_out(89) => \data_f1_out[89]\, data_f1_out(88) => - \data_f1_out[88]\, data_f1_out(87) => \data_f1_out[87]\, - data_f1_out(86) => \data_f1_out[86]\, data_f1_out(85) => - \data_f1_out[85]\, data_f1_out(84) => \data_f1_out[84]\, - data_f1_out(83) => \data_f1_out[83]\, data_f1_out(82) => - \data_f1_out[82]\, data_f1_out(81) => \data_f1_out[81]\, - data_f1_out(80) => \data_f1_out[80]\, data_f1_out(79) => - \data_f1_out[79]\, data_f1_out(78) => \data_f1_out[78]\, - data_f1_out(77) => \data_f1_out[77]\, data_f1_out(76) => - \data_f1_out[76]\, data_f1_out(75) => \data_f1_out[75]\, - data_f1_out(74) => \data_f1_out[74]\, data_f1_out(73) => - \data_f1_out[73]\, data_f1_out(72) => \data_f1_out[72]\, - data_f1_out(71) => \data_f1_out[71]\, data_f1_out(70) => - \data_f1_out[70]\, data_f1_out(69) => \data_f1_out[69]\, - data_f1_out(68) => \data_f1_out[68]\, data_f1_out(67) => - \data_f1_out[67]\, data_f1_out(66) => \data_f1_out[66]\, - data_f1_out(65) => \data_f1_out[65]\, data_f1_out(64) => - \data_f1_out[64]\, data_f0_out(159) => \data_f0_out[159]\, - data_f0_out(158) => \data_f0_out[158]\, data_f0_out(157) - => \data_f0_out[157]\, data_f0_out(156) => - \data_f0_out[156]\, data_f0_out(155) => - \data_f0_out[155]\, data_f0_out(154) => - \data_f0_out[154]\, data_f0_out(153) => - \data_f0_out[153]\, data_f0_out(152) => - \data_f0_out[152]\, data_f0_out(151) => - \data_f0_out[151]\, data_f0_out(150) => - \data_f0_out[150]\, data_f0_out(149) => - \data_f0_out[149]\, data_f0_out(148) => - \data_f0_out[148]\, data_f0_out(147) => - \data_f0_out[147]\, data_f0_out(146) => - \data_f0_out[146]\, data_f0_out(145) => - \data_f0_out[145]\, data_f0_out(144) => - \data_f0_out[144]\, data_f0_out(143) => - \data_f0_out[143]\, data_f0_out(142) => - \data_f0_out[142]\, data_f0_out(141) => - \data_f0_out[141]\, data_f0_out(140) => - \data_f0_out[140]\, data_f0_out(139) => - \data_f0_out[139]\, data_f0_out(138) => - \data_f0_out[138]\, data_f0_out(137) => - \data_f0_out[137]\, data_f0_out(136) => - \data_f0_out[136]\, data_f0_out(135) => - \data_f0_out[135]\, data_f0_out(134) => - \data_f0_out[134]\, data_f0_out(133) => - \data_f0_out[133]\, data_f0_out(132) => - \data_f0_out[132]\, data_f0_out(131) => - \data_f0_out[131]\, data_f0_out(130) => - \data_f0_out[130]\, data_f0_out(129) => - \data_f0_out[129]\, data_f0_out(128) => - \data_f0_out[128]\, data_f0_out(127) => - \data_f0_out[127]\, data_f0_out(126) => - \data_f0_out[126]\, data_f0_out(125) => - \data_f0_out[125]\, data_f0_out(124) => - \data_f0_out[124]\, data_f0_out(123) => - \data_f0_out[123]\, data_f0_out(122) => - \data_f0_out[122]\, data_f0_out(121) => - \data_f0_out[121]\, data_f0_out(120) => - \data_f0_out[120]\, data_f0_out(119) => - \data_f0_out[119]\, data_f0_out(118) => - \data_f0_out[118]\, data_f0_out(117) => - \data_f0_out[117]\, data_f0_out(116) => - \data_f0_out[116]\, data_f0_out(115) => - \data_f0_out[115]\, data_f0_out(114) => - \data_f0_out[114]\, data_f0_out(113) => - \data_f0_out[113]\, data_f0_out(112) => - \data_f0_out[112]\, data_f0_out(111) => - \data_f0_out[111]\, data_f0_out(110) => - \data_f0_out[110]\, data_f0_out(109) => - \data_f0_out[109]\, data_f0_out(108) => - \data_f0_out[108]\, data_f0_out(107) => - \data_f0_out[107]\, data_f0_out(106) => - \data_f0_out[106]\, data_f0_out(105) => - \data_f0_out[105]\, data_f0_out(104) => - \data_f0_out[104]\, data_f0_out(103) => - \data_f0_out[103]\, data_f0_out(102) => - \data_f0_out[102]\, data_f0_out(101) => - \data_f0_out[101]\, data_f0_out(100) => - \data_f0_out[100]\, data_f0_out(99) => \data_f0_out[99]\, - data_f0_out(98) => \data_f0_out[98]\, data_f0_out(97) => - \data_f0_out[97]\, data_f0_out(96) => \data_f0_out[96]\, - data_f0_out(95) => \data_f0_out[95]\, data_f0_out(94) => - \data_f0_out[94]\, data_f0_out(93) => \data_f0_out[93]\, - data_f0_out(92) => \data_f0_out[92]\, data_f0_out(91) => - \data_f0_out[91]\, data_f0_out(90) => \data_f0_out[90]\, - data_f0_out(89) => \data_f0_out[89]\, data_f0_out(88) => - \data_f0_out[88]\, data_f0_out(87) => \data_f0_out[87]\, - data_f0_out(86) => \data_f0_out[86]\, data_f0_out(85) => - \data_f0_out[85]\, data_f0_out(84) => \data_f0_out[84]\, - data_f0_out(83) => \data_f0_out[83]\, data_f0_out(82) => - \data_f0_out[82]\, data_f0_out(81) => \data_f0_out[81]\, - data_f0_out(80) => \data_f0_out[80]\, data_f0_out(79) => - \data_f0_out[79]\, data_f0_out(78) => \data_f0_out[78]\, - data_f0_out(77) => \data_f0_out[77]\, data_f0_out(76) => - \data_f0_out[76]\, data_f0_out(75) => \data_f0_out[75]\, - data_f0_out(74) => \data_f0_out[74]\, data_f0_out(73) => - \data_f0_out[73]\, data_f0_out(72) => \data_f0_out[72]\, - data_f0_out(71) => \data_f0_out[71]\, data_f0_out(70) => - \data_f0_out[70]\, data_f0_out(69) => \data_f0_out[69]\, - data_f0_out(68) => \data_f0_out[68]\, data_f0_out(67) => - \data_f0_out[67]\, data_f0_out(66) => \data_f0_out[66]\, - data_f0_out(65) => \data_f0_out[65]\, data_f0_out(64) => - \data_f0_out[64]\, ready_i_0_i_0(1) => \ready_i_0_i_0[1]\, - valid_out_i(1) => \valid_out_i[1]\, ready_i_0_3 => - \ready_i_0[3]\, ready_i_0_0 => \ready_i_0[0]\, - ready_i_0_2 => \ready_i_0[2]\, valid_out_3 => - \valid_out[3]\, valid_out_0 => \valid_out[0]\, - valid_out_2 => \valid_out[2]\, rstn => rstn, lclk_c => - lclk_c); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_8_16_4 is - - port( sample_f0_0 : out std_logic; - sample_f0_1 : out std_logic; - sample_f0_2 : out std_logic; - sample_f0_3 : out std_logic; - sample_f0_4 : out std_logic; - sample_f0_5 : out std_logic; - sample_f0_6 : out std_logic; - sample_f0_7 : out std_logic; - sample_f0_8 : out std_logic; - sample_f0_9 : out std_logic; - sample_f0_10 : out std_logic; - sample_f0_11 : out std_logic; - sample_f0_12 : out std_logic; - sample_f0_13 : out std_logic; - sample_f0_14 : out std_logic; - sample_f0_15 : out std_logic; - sample_f0_32 : out std_logic; - sample_f0_33 : out std_logic; - sample_f0_34 : out std_logic; - sample_f0_35 : out std_logic; - sample_f0_36 : out std_logic; - sample_f0_37 : out std_logic; - sample_f0_38 : out std_logic; - sample_f0_39 : out std_logic; - sample_f0_40 : out std_logic; - sample_f0_41 : out std_logic; - sample_f0_42 : out std_logic; - sample_f0_43 : out std_logic; - sample_f0_44 : out std_logic; - sample_f0_45 : out std_logic; - sample_f0_46 : out std_logic; - sample_f0_47 : out std_logic; - sample_f0_48 : out std_logic; - sample_f0_49 : out std_logic; - sample_f0_50 : out std_logic; - sample_f0_51 : out std_logic; - sample_f0_52 : out std_logic; - sample_f0_53 : out std_logic; - sample_f0_54 : out std_logic; - sample_f0_55 : out std_logic; - sample_f0_56 : out std_logic; - sample_f0_57 : out std_logic; - sample_f0_58 : out std_logic; - sample_f0_59 : out std_logic; - sample_f0_60 : out std_logic; - sample_f0_61 : out std_logic; - sample_f0_62 : out std_logic; - sample_f0_63 : out std_logic; - sample_data_shaping_out_0 : in std_logic; - sample_data_shaping_out_1 : in std_logic; - sample_data_shaping_out_2 : in std_logic; - sample_data_shaping_out_3 : in std_logic; - sample_data_shaping_out_4 : in std_logic; - sample_data_shaping_out_5 : in std_logic; - sample_data_shaping_out_6 : in std_logic; - sample_data_shaping_out_7 : in std_logic; - sample_data_shaping_out_8 : in std_logic; - sample_data_shaping_out_9 : in std_logic; - sample_data_shaping_out_10 : in std_logic; - sample_data_shaping_out_11 : in std_logic; - sample_data_shaping_out_12 : in std_logic; - sample_data_shaping_out_13 : in std_logic; - sample_data_shaping_out_14 : in std_logic; - sample_data_shaping_out_15 : in std_logic; - sample_data_shaping_out_18 : in std_logic; - sample_data_shaping_out_19 : in std_logic; - sample_data_shaping_out_20 : in std_logic; - sample_data_shaping_out_21 : in std_logic; - sample_data_shaping_out_22 : in std_logic; - sample_data_shaping_out_23 : in std_logic; - sample_data_shaping_out_24 : in std_logic; - sample_data_shaping_out_25 : in std_logic; - sample_data_shaping_out_26 : in std_logic; - sample_data_shaping_out_27 : in std_logic; - sample_data_shaping_out_28 : in std_logic; - sample_data_shaping_out_29 : in std_logic; - sample_data_shaping_out_30 : in std_logic; - sample_data_shaping_out_31 : in std_logic; - sample_data_shaping_out_32 : in std_logic; - sample_data_shaping_out_33 : in std_logic; - sample_data_shaping_out_36 : in std_logic; - sample_data_shaping_out_37 : in std_logic; - sample_data_shaping_out_38 : in std_logic; - sample_data_shaping_out_39 : in std_logic; - sample_data_shaping_out_40 : in std_logic; - sample_data_shaping_out_41 : in std_logic; - sample_data_shaping_out_42 : in std_logic; - sample_data_shaping_out_43 : in std_logic; - sample_data_shaping_out_44 : in std_logic; - sample_data_shaping_out_45 : in std_logic; - sample_data_shaping_out_46 : in std_logic; - sample_data_shaping_out_47 : in std_logic; - sample_data_shaping_out_48 : in std_logic; - sample_data_shaping_out_49 : in std_logic; - sample_data_shaping_out_50 : in std_logic; - sample_data_shaping_out_51 : in std_logic; - sample_data_shaping_out_54 : in std_logic; - sample_data_shaping_out_55 : in std_logic; - sample_data_shaping_out_56 : in std_logic; - sample_data_shaping_out_57 : in std_logic; - sample_data_shaping_out_58 : in std_logic; - sample_data_shaping_out_59 : in std_logic; - sample_data_shaping_out_60 : in std_logic; - sample_data_shaping_out_61 : in std_logic; - sample_data_shaping_out_62 : in std_logic; - sample_data_shaping_out_63 : in std_logic; - sample_data_shaping_out_64 : in std_logic; - sample_data_shaping_out_65 : in std_logic; - sample_data_shaping_out_66 : in std_logic; - sample_data_shaping_out_67 : in std_logic; - sample_data_shaping_out_68 : in std_logic; - sample_data_shaping_out_69 : in std_logic; - sample_data_shaping_out_90 : in std_logic; - sample_data_shaping_out_91 : in std_logic; - sample_data_shaping_out_92 : in std_logic; - sample_data_shaping_out_93 : in std_logic; - sample_data_shaping_out_94 : in std_logic; - sample_data_shaping_out_95 : in std_logic; - sample_data_shaping_out_96 : in std_logic; - sample_data_shaping_out_97 : in std_logic; - sample_data_shaping_out_98 : in std_logic; - sample_data_shaping_out_99 : in std_logic; - sample_data_shaping_out_100 : in std_logic; - sample_data_shaping_out_101 : in std_logic; - sample_data_shaping_out_102 : in std_logic; - sample_data_shaping_out_103 : in std_logic; - sample_data_shaping_out_104 : in std_logic; - sample_data_shaping_out_105 : in std_logic; - sample_data_shaping_out_108 : in std_logic; - sample_data_shaping_out_109 : in std_logic; - sample_data_shaping_out_110 : in std_logic; - sample_data_shaping_out_111 : in std_logic; - sample_data_shaping_out_112 : in std_logic; - sample_data_shaping_out_113 : in std_logic; - sample_data_shaping_out_114 : in std_logic; - sample_data_shaping_out_115 : in std_logic; - sample_data_shaping_out_116 : in std_logic; - sample_data_shaping_out_117 : in std_logic; - sample_data_shaping_out_118 : in std_logic; - sample_data_shaping_out_119 : in std_logic; - sample_data_shaping_out_120 : in std_logic; - sample_data_shaping_out_121 : in std_logic; - sample_data_shaping_out_122 : in std_logic; - sample_data_shaping_out_123 : in std_logic; - sample_data_shaping_out_126 : in std_logic; - sample_data_shaping_out_127 : in std_logic; - sample_data_shaping_out_128 : in std_logic; - sample_data_shaping_out_129 : in std_logic; - sample_data_shaping_out_130 : in std_logic; - sample_data_shaping_out_131 : in std_logic; - sample_data_shaping_out_132 : in std_logic; - sample_data_shaping_out_133 : in std_logic; - sample_data_shaping_out_134 : in std_logic; - sample_data_shaping_out_135 : in std_logic; - sample_data_shaping_out_136 : in std_logic; - sample_data_shaping_out_137 : in std_logic; - sample_data_shaping_out_138 : in std_logic; - sample_data_shaping_out_139 : in std_logic; - sample_data_shaping_out_140 : in std_logic; - sample_data_shaping_out_141 : in std_logic; - sample_f0_wdata_95 : out std_logic; - sample_f0_wdata_94 : out std_logic; - sample_f0_wdata_93 : out std_logic; - sample_f0_wdata_92 : out std_logic; - sample_f0_wdata_91 : out std_logic; - sample_f0_wdata_90 : out std_logic; - sample_f0_wdata_89 : out std_logic; - sample_f0_wdata_88 : out std_logic; - sample_f0_wdata_87 : out std_logic; - sample_f0_wdata_86 : out std_logic; - sample_f0_wdata_85 : out std_logic; - sample_f0_wdata_84 : out std_logic; - sample_f0_wdata_83 : out std_logic; - sample_f0_wdata_82 : out std_logic; - sample_f0_wdata_81 : out std_logic; - sample_f0_wdata_80 : out std_logic; - sample_f0_wdata_79 : out std_logic; - sample_f0_wdata_78 : out std_logic; - sample_f0_wdata_77 : out std_logic; - sample_f0_wdata_76 : out std_logic; - sample_f0_wdata_75 : out std_logic; - sample_f0_wdata_74 : out std_logic; - sample_f0_wdata_73 : out std_logic; - sample_f0_wdata_72 : out std_logic; - sample_f0_wdata_71 : out std_logic; - sample_f0_wdata_70 : out std_logic; - sample_f0_wdata_69 : out std_logic; - sample_f0_wdata_68 : out std_logic; - sample_f0_wdata_67 : out std_logic; - sample_f0_wdata_66 : out std_logic; - sample_f0_wdata_65 : out std_logic; - sample_f0_wdata_64 : out std_logic; - sample_f0_wdata_63 : out std_logic; - sample_f0_wdata_62 : out std_logic; - sample_f0_wdata_61 : out std_logic; - sample_f0_wdata_60 : out std_logic; - sample_f0_wdata_59 : out std_logic; - sample_f0_wdata_58 : out std_logic; - sample_f0_wdata_57 : out std_logic; - sample_f0_wdata_56 : out std_logic; - sample_f0_wdata_55 : out std_logic; - sample_f0_wdata_54 : out std_logic; - sample_f0_wdata_53 : out std_logic; - sample_f0_wdata_52 : out std_logic; - sample_f0_wdata_51 : out std_logic; - sample_f0_wdata_50 : out std_logic; - sample_f0_wdata_49 : out std_logic; - sample_f0_wdata_48 : out std_logic; - sample_f0_wdata_15 : out std_logic; - sample_f0_wdata_14 : out std_logic; - sample_f0_wdata_13 : out std_logic; - sample_f0_wdata_12 : out std_logic; - sample_f0_wdata_11 : out std_logic; - sample_f0_wdata_10 : out std_logic; - sample_f0_wdata_9 : out std_logic; - sample_f0_wdata_8 : out std_logic; - sample_f0_wdata_7 : out std_logic; - sample_f0_wdata_6 : out std_logic; - sample_f0_wdata_5 : out std_logic; - sample_f0_wdata_4 : out std_logic; - sample_f0_wdata_3 : out std_logic; - sample_f0_wdata_2 : out std_logic; - sample_f0_wdata_1 : out std_logic; - sample_f0_wdata_0 : out std_logic; - sample_data_shaping_out_val : in std_logic; - sample_f0_val : out std_logic; - sample_data_shaping_out_val_0 : in std_logic; - sample_f0_val_0 : out std_logic; - sample_f0_val_1 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_f0_val_2 : out std_logic - ); - -end Downsampling_8_16_4; - -architecture DEF_ARCH of Downsampling_8_16_4 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal sample_out_val_19, sample_out_0_sqmuxa_3, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1, - sample_out_0_sqmuxa_0, un14_sample_in_val_i_0_0, - un14_sample_in_val_23, un14_sample_in_val_22, - un14_sample_in_val_24, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un14_sample_in_val_15, - un14_sample_in_val_14, un14_sample_in_val_20, - un14_sample_in_val_9, un14_sample_in_val_8, - un14_sample_in_val_19, un14_sample_in_val_5, - un14_sample_in_val_4, un14_sample_in_val_17, - un14_sample_in_val_13, \counter[24]_net_1\, - un14_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un14_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un14_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un14_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un14_sample_in_val_i_0, - sample_out_0_sqmuxa, \counter_4[0]\, I_9_10, - \counter_4[1]\, I_13_14, \counter_4[2]\, I_20_10, - \counter_4[3]\, I_24_11, \counter_4[4]\, I_31_10, - \counter_4[5]\, I_38_7, \counter_4[6]\, I_45_6, - \counter_4[7]\, I_52_6, \counter_4[8]\, I_56_7, - \counter_4[9]\, I_66_7, \counter_4[10]\, I_73_5, - \counter_4[11]\, I_77_5, \counter_4[12]\, I_84_5, - \counter_4[13]\, I_91_5, \counter_4[14]\, I_98_5, - \counter_4[15]\, I_105_5, \counter_4[16]\, I_115_5, - \counter_4[17]\, I_122_5, \counter_4[18]\, I_129_5, - \counter_4[19]\, I_136_4, \counter_4[20]\, I_143_4, - \counter_4[21]\, I_156_4, \counter_4[22]\, I_166_4, - \counter_4[23]\, I_173_4, \counter_4[24]\, I_186_4, - \counter_4[25]\, I_196_4, I_4, I_5_10, N_4, - \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[19]_net_1\); - - \sample_out[125]\ : DFN1E1 - port map(D => sample_data_shaping_out_139, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_2); - - \sample_out[102]\ : DFN1E1 - port map(D => sample_data_shaping_out_114, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_54); - - \sample_out[122]\ : DFN1E1 - port map(D => sample_data_shaping_out_136, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_5); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_data_shaping_out_24, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_73); - - \sample_out[101]\ : DFN1E1 - port map(D => sample_data_shaping_out_113, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_53); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_data_shaping_out_22, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_75); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_data_shaping_out_13, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_82); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_data_shaping_out_1, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_94); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_data_shaping_out_21, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_76); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_data_shaping_out_67, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_13); - - \sample_out[121]\ : DFN1E1 - port map(D => sample_data_shaping_out_135, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_6); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_data_shaping_out_42, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_57); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_data_shaping_out_105, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_47); - - \counter_RNO[11]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_66_7, Y => - \counter_4[9]\); - - \sample_out[104]\ : DFN1E1 - port map(D => sample_data_shaping_out_116, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_56); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_data_shaping_out_38, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_61); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4); - - \sample_out[124]\ : DFN1E1 - port map(D => sample_data_shaping_out_138, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_3); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val_0, Q => - \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \counter_RNIGPFA3_2[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa_3); - - \sample_out[97]\ : DFN1E1 - port map(D => sample_data_shaping_out_109, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_49); - - \counter_RNIRVM2[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un14_sample_in_val_13); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_4); - - \sample_out[108]\ : DFN1E1 - port map(D => sample_data_shaping_out_120, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_60); - - \counter_RNO[15]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_91_5, Y => - \counter_4[13]\); - - \counter_RNI201K[27]\ : NOR3A - port map(A => un14_sample_in_val_1, B => - \counter[11]_net_1\, C => \counter[27]_net_1\, Y => - un14_sample_in_val_14); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_data_shaping_out_57, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_3); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_data_shaping_out_62, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_8); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_data_shaping_out_0, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_95); - - \counter_RNO[7]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_38_7, Y => - \counter_4[5]\); - - \counter[6]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_14); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_data_shaping_out_91, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_33); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_data_shaping_out_96, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_38); - - \counter_RNIGPFA3[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa_1); - - \counter[3]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => \counter_4[0]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_5); - - \counter_RNO[8]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_45_6, Y => - \counter_4[6]\); - - \counter_RNO[13]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_77_5, Y => - \counter_4[11]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_6); - - \counter_RNICMR73_0[4]\ : OR3C - port map(A => un14_sample_in_val_23, B => - un14_sample_in_val_22, C => un14_sample_in_val_24, Y => - un14_sample_in_val_i_0); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_data_shaping_out_12, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_83); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_data_shaping_out_10, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_85); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_data_shaping_out_49, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_50); - - \counter_RNO[12]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_73_5, Y => - \counter_4[10]\); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_data_shaping_out_37, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_62); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_data_shaping_out_43, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_56); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[17]_net_1\); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_10); - - \counter_RNIUCC6[7]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un14_sample_in_val_4); - - \counter_RNIAKHP[4]\ : NOR3C - port map(A => un14_sample_in_val_9, B => - un14_sample_in_val_8, C => un14_sample_in_val_19, Y => - un14_sample_in_val_23); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val_0, Q => - \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_data_shaping_out_5, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_90); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_data_shaping_out_51, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_48); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[13]_net_1\); - - \counter_RNIGPFA3_1[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa_0); - - \counter_RNI2AP01[7]\ : NOR3C - port map(A => un14_sample_in_val_5, B => - un14_sample_in_val_4, C => un14_sample_in_val_17, Y => - un14_sample_in_val_22); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - \sample_out[115]\ : DFN1E1 - port map(D => sample_data_shaping_out_129, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_data_shaping_out_23, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_74); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_data_shaping_out_28, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_69); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_data_shaping_out_2, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_93); - - \sample_out[98]\ : DFN1E1 - port map(D => sample_data_shaping_out_110, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_50); - - \sample_out[112]\ : DFN1E1 - port map(D => sample_data_shaping_out_126, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_15); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[27]_net_1\); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_data_shaping_out_104, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_46); - - \sample_out[111]\ : DFN1E1 - port map(D => sample_data_shaping_out_123, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_63); - - \counter_RNIVV0K[12]\ : NOR3A - port map(A => un14_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un14_sample_in_val_19); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_4); - - \counter_RNO[17]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_105_5, Y => - \counter_4[15]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \counter_RNIQO29[24]\ : NOR3A - port map(A => un14_sample_in_val_13, B => - \counter[1]_net_1\, C => \counter[24]_net_1\, Y => - un14_sample_in_val_20); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_data_shaping_out_61, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_7); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \sample_out[114]\ : DFN1E1 - port map(D => sample_data_shaping_out_128, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_4); - - \counter_RNI0OGD1[20]\ : NOR3C - port map(A => un14_sample_in_val_15, B => - un14_sample_in_val_14, C => un14_sample_in_val_20, Y => - un14_sample_in_val_24); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_data_shaping_out_36, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_63); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_5); - - \sample_out[118]\ : DFN1E1 - port map(D => sample_data_shaping_out_132, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_9); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_data_shaping_out_63, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_9); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_data_shaping_out_32, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_65); - - \counter_RNO[14]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_84_5, Y => - \counter_4[12]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_data_shaping_out_95, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_37); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_10, CLK => lclk_c, CLR => rstn, E => - sample_data_shaping_out_val_0, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_186_4, Y => - \counter_4[24]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_data_shaping_out_4, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_91); - - \counter_RNO[5]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_24_11, Y => - \counter_4[3]\); - - \sample_out[103]\ : DFN1E1 - port map(D => sample_data_shaping_out_115, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_55); - - \sample_out[100]\ : DFN1E1 - port map(D => sample_data_shaping_out_112, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_52); - - \counter_RNIVD0A[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un14_sample_in_val_5); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[25]_net_1\); - - \sample_out[123]\ : DFN1E1 - port map(D => sample_data_shaping_out_137, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_4); - - \sample_out[120]\ : DFN1E1 - port map(D => sample_data_shaping_out_134, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_7); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_19, CLK => lclk_c, CLR => rstn, - Q => sample_f0_val); - - \counter_RNO[3]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_13_14, Y => - \counter_4[1]\); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_data_shaping_out_97, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_39); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_5); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_4); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_data_shaping_out_54, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_0); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_7); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_data_shaping_out_103, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_45); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_data_shaping_out_11, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_84); - - \sample_out[99]\ : DFN1E1 - port map(D => sample_data_shaping_out_111, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_51); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_data_shaping_out_18, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_79); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_data_shaping_out_48, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_51); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_56_7, Y => - \counter_4[8]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_10); - - \counter_RNO[21]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_136_4, Y => - \counter_4[19]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_10); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_data_shaping_out_27, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_70); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_7); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_173_4, Y => - \counter_4[23]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_10); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_5); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_data_shaping_out_29, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_68); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNO[6]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_31_10, Y => - \counter_4[4]\); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - \counter_RNICMR73[4]\ : OR3C - port map(A => un14_sample_in_val_23, B => - un14_sample_in_val_22, C => un14_sample_in_val_24, Y => - un14_sample_in_val_i_0_0); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_4); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - sample_out_val_2 : DFN1C0 - port map(D => sample_out_val_19, CLK => lclk_c, CLR => rstn, - Q => sample_f0_val_2); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_data_shaping_out_64, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_10); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_7); - - \counter_RNO[23]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_156_4, Y => - \counter_4[21]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_data_shaping_out_60, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_6); - - \counter_RNIGPFA3_0[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa_2); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_data_shaping_out_47, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_52); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_data_shaping_out_55, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_1); - - \counter_RNI1TB6[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un14_sample_in_val_7); - - sample_out_val_0 : DFN1C0 - port map(D => sample_out_val_19, CLK => lclk_c, CLR => rstn, - Q => sample_f0_val_0); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_6); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_11); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_data_shaping_out_102, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_44); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_4); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_data_shaping_out_98, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_40); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_data_shaping_out_100, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_42); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_5); - - \counter_RNO[22]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_143_4, Y => - \counter_4[20]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_data_shaping_out_33, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_64); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_data_shaping_out_40, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_59); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_data_shaping_out_94, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_36); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_data_shaping_out_69, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_15); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_data_shaping_out_15, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_80); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_5); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[113]\ : DFN1E1 - port map(D => sample_data_shaping_out_127, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_14); - - \sample_out[110]\ : DFN1E1 - port map(D => sample_data_shaping_out_122, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_62); - - \counter_RNO[4]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_20_10, Y => - \counter_4[2]\); - - \counter_RNI59C6[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un14_sample_in_val_3); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \sample_out[106]\ : DFN1E1 - port map(D => sample_data_shaping_out_118, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_58); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_5); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_data_shaping_out_19, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_78); - - \sample_out[107]\ : DFN1E1 - port map(D => sample_data_shaping_out_119, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_59); - - \counter_RNO[18]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_115_5, Y => - \counter_4[16]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[126]\ : DFN1E1 - port map(D => sample_data_shaping_out_140, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_1); - - \sample_out[127]\ : DFN1E1 - port map(D => sample_data_shaping_out_141, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_0); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_data_shaping_out_59, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_5); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_data_shaping_out_30, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_67); - - \counter_RNO[27]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_196_4, Y => - \counter_4[25]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_data_shaping_out_65, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_11); - - \sample_out[109]\ : DFN1E1 - port map(D => sample_data_shaping_out_121, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_61); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_data_shaping_out_26, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_71); - - \counter_RNIMT393[4]\ : NOR2A - port map(A => sample_data_shaping_out_val_0, B => - un14_sample_in_val_i_0_0, Y => sample_out_val_19); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_data_shaping_out_46, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_53); - - \counter_RNI4VCG[20]\ : NOR3A - port map(A => un14_sample_in_val_3, B => - \counter[23]_net_1\, C => \counter[20]_net_1\, Y => - un14_sample_in_val_15); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_data_shaping_out_44, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_55); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_data_shaping_out_93, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_35); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_data_shaping_out_99, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_41); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_166_4, Y => - \counter_4[22]\); - - \counter_RNI5FCG[19]\ : NOR3A - port map(A => un14_sample_in_val_7, B => - \counter[22]_net_1\, C => \counter[19]_net_1\, Y => - un14_sample_in_val_17); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_5); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_data_shaping_out_6, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_89); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - \counter_RNI2SN2[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un14_sample_in_val_8); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_data_shaping_out_68, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_14); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_data_shaping_out_66, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_12); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_data_shaping_out_39, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_60); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_data_shaping_out_101, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_43); - - \counter_RNI2I0A[18]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un14_sample_in_val_11); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - \sample_out[96]\ : DFN1E1 - port map(D => sample_data_shaping_out_108, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_48); - - \counter_RNIGPFA3_3[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - \counter_RNI1E0A[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un14_sample_in_val_1); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - sample_out_val_1 : DFN1C0 - port map(D => sample_out_val_19, CLK => lclk_c, CLR => rstn, - Q => sample_f0_val_1); - - \counter_RNO[20]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_129_5, Y => - \counter_4[18]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_data_shaping_out_41, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_58); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_data_shaping_out_25, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_72); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_data_shaping_out_58, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_4); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_data_shaping_out_31, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_66); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_data_shaping_out_56, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_2); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_data_shaping_out_20, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_77); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_data_shaping_out_9, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_wdata_86); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_data_shaping_out_7, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_88); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_data_shaping_out_14, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_81); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_data_shaping_out_92, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_34); - - \counter_RNO[2]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_9_10, Y => - \counter_4[0]\); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[9]_net_1\); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_data_shaping_out_90, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_32); - - \counter_RNO[19]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_122_5, Y => - \counter_4[17]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_52_6, Y => - \counter_4[7]\); - - \counter_RNI9OO2[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un14_sample_in_val_9); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_5); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_4); - - \sample_out[116]\ : DFN1E1 - port map(D => sample_data_shaping_out_130, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_11); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[18]_net_1\); - - \sample_out[117]\ : DFN1E1 - port map(D => sample_data_shaping_out_131, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_10); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_data_shaping_out_8, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_wdata_87); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_data_shaping_out_45, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_54); - - \counter_RNO[16]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_98_5, Y => - \counter_4[14]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4, CLK => lclk_c, CLR => rstn, E => - sample_data_shaping_out_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_data_shaping_out_50, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_49); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_data_shaping_out_3, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_92); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - \sample_out[105]\ : DFN1E1 - port map(D => sample_data_shaping_out_117, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_57); - - \sample_out[119]\ : DFN1E1 - port map(D => sample_data_shaping_out_133, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_8_16_6 is - - port( sample_f0_0 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_15 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_37 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_63 : in std_logic; - sample_f1_0 : out std_logic; - sample_f1_1 : out std_logic; - sample_f1_2 : out std_logic; - sample_f1_3 : out std_logic; - sample_f1_4 : out std_logic; - sample_f1_5 : out std_logic; - sample_f1_6 : out std_logic; - sample_f1_7 : out std_logic; - sample_f1_8 : out std_logic; - sample_f1_9 : out std_logic; - sample_f1_10 : out std_logic; - sample_f1_11 : out std_logic; - sample_f1_12 : out std_logic; - sample_f1_13 : out std_logic; - sample_f1_14 : out std_logic; - sample_f1_15 : out std_logic; - sample_f1_32 : out std_logic; - sample_f1_33 : out std_logic; - sample_f1_34 : out std_logic; - sample_f1_35 : out std_logic; - sample_f1_36 : out std_logic; - sample_f1_37 : out std_logic; - sample_f1_38 : out std_logic; - sample_f1_39 : out std_logic; - sample_f1_40 : out std_logic; - sample_f1_41 : out std_logic; - sample_f1_42 : out std_logic; - sample_f1_43 : out std_logic; - sample_f1_44 : out std_logic; - sample_f1_45 : out std_logic; - sample_f1_46 : out std_logic; - sample_f1_47 : out std_logic; - sample_f1_48 : out std_logic; - sample_f1_49 : out std_logic; - sample_f1_50 : out std_logic; - sample_f1_51 : out std_logic; - sample_f1_52 : out std_logic; - sample_f1_53 : out std_logic; - sample_f1_54 : out std_logic; - sample_f1_55 : out std_logic; - sample_f1_56 : out std_logic; - sample_f1_57 : out std_logic; - sample_f1_58 : out std_logic; - sample_f1_59 : out std_logic; - sample_f1_60 : out std_logic; - sample_f1_61 : out std_logic; - sample_f1_62 : out std_logic; - sample_f1_63 : out std_logic; - sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f1_wdata_95 : out std_logic; - sample_f1_wdata_94 : out std_logic; - sample_f1_wdata_93 : out std_logic; - sample_f1_wdata_92 : out std_logic; - sample_f1_wdata_91 : out std_logic; - sample_f1_wdata_90 : out std_logic; - sample_f1_wdata_89 : out std_logic; - sample_f1_wdata_88 : out std_logic; - sample_f1_wdata_87 : out std_logic; - sample_f1_wdata_86 : out std_logic; - sample_f1_wdata_85 : out std_logic; - sample_f1_wdata_84 : out std_logic; - sample_f1_wdata_83 : out std_logic; - sample_f1_wdata_82 : out std_logic; - sample_f1_wdata_81 : out std_logic; - sample_f1_wdata_80 : out std_logic; - sample_f1_wdata_79 : out std_logic; - sample_f1_wdata_78 : out std_logic; - sample_f1_wdata_77 : out std_logic; - sample_f1_wdata_76 : out std_logic; - sample_f1_wdata_75 : out std_logic; - sample_f1_wdata_74 : out std_logic; - sample_f1_wdata_73 : out std_logic; - sample_f1_wdata_72 : out std_logic; - sample_f1_wdata_71 : out std_logic; - sample_f1_wdata_70 : out std_logic; - sample_f1_wdata_69 : out std_logic; - sample_f1_wdata_68 : out std_logic; - sample_f1_wdata_67 : out std_logic; - sample_f1_wdata_66 : out std_logic; - sample_f1_wdata_65 : out std_logic; - sample_f1_wdata_64 : out std_logic; - sample_f1_wdata_63 : out std_logic; - sample_f1_wdata_62 : out std_logic; - sample_f1_wdata_61 : out std_logic; - sample_f1_wdata_60 : out std_logic; - sample_f1_wdata_59 : out std_logic; - sample_f1_wdata_58 : out std_logic; - sample_f1_wdata_57 : out std_logic; - sample_f1_wdata_56 : out std_logic; - sample_f1_wdata_55 : out std_logic; - sample_f1_wdata_54 : out std_logic; - sample_f1_wdata_53 : out std_logic; - sample_f1_wdata_52 : out std_logic; - sample_f1_wdata_51 : out std_logic; - sample_f1_wdata_50 : out std_logic; - sample_f1_wdata_49 : out std_logic; - sample_f1_wdata_48 : out std_logic; - sample_f1_wdata_15 : out std_logic; - sample_f1_wdata_14 : out std_logic; - sample_f1_wdata_13 : out std_logic; - sample_f1_wdata_12 : out std_logic; - sample_f1_wdata_11 : out std_logic; - sample_f1_wdata_10 : out std_logic; - sample_f1_wdata_9 : out std_logic; - sample_f1_wdata_8 : out std_logic; - sample_f1_wdata_7 : out std_logic; - sample_f1_wdata_6 : out std_logic; - sample_f1_wdata_5 : out std_logic; - sample_f1_wdata_4 : out std_logic; - sample_f1_wdata_3 : out std_logic; - sample_f1_wdata_2 : out std_logic; - sample_f1_wdata_1 : out std_logic; - sample_f1_wdata_0 : out std_logic; - sample_f0_val_2 : in std_logic; - sample_f0_val_1 : in std_logic; - sample_f1_val : out std_logic; - sample_f0_val_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_f1_val_0 : out std_logic - ); - -end Downsampling_8_16_6; - -architecture DEF_ARCH of Downsampling_8_16_6 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal sample_out_val_14, un10_sample_in_val_0, - un10_sample_in_val_23, un10_sample_in_val_22, - un10_sample_in_val_24, sample_out_0_sqmuxa_3, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1, - sample_out_0_sqmuxa_0, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un10_sample_in_val_15, - un10_sample_in_val_14, un10_sample_in_val_20, - un10_sample_in_val_9, un10_sample_in_val_8, - un10_sample_in_val_19, un10_sample_in_val_5, - un10_sample_in_val_4, un10_sample_in_val_17, - un10_sample_in_val_13, \counter[24]_net_1\, - un10_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un10_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un10_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un10_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un10_sample_in_val, \counter_4[0]\, - I_13_15, \counter_4[1]\, I_20_11, \counter_4[2]\, I_24_12, - \counter_4[3]\, I_31_11, \counter_4[4]\, I_38_8, - \counter_4[5]\, I_45_7, \counter_4[6]\, I_52_7, - \counter_4[7]\, I_56_8, \counter_4[8]\, I_66_8, - \counter_4[9]\, I_73_6, \counter_4[10]\, I_77_6, - \counter_4[11]\, I_84_6, \counter_4[12]\, I_91_6, - \counter_4[13]\, I_98_6, \counter_4[14]\, I_105_6, - \counter_4[15]\, I_115_6, \counter_4[16]\, I_122_6, - \counter_4[17]\, I_129_6, \counter_4[18]\, I_136_5, - \counter_4[19]\, I_143_5, \counter_4[20]\, I_156_5, - \counter_4[21]\, I_166_5, \counter_4[22]\, I_173_5, - \counter_4[23]\, I_186_5, \counter_4[24]\, I_196_5, - \counter_4_1[1]\, I_5_11, sample_out_0_sqmuxa, I_4_0, - I_9_11, N_4, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[19]_net_1\); - - \sample_out[125]\ : DFN1E1 - port map(D => sample_f0_wdata_2, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_2); - - \sample_out[102]\ : DFN1E1 - port map(D => sample_f0_54, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_54); - - \counter_RNI8BJ5[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un10_sample_in_val_8); - - \sample_out[122]\ : DFN1E1 - port map(D => sample_f0_wdata_5, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_5); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f0_wdata_73, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_73); - - \sample_out[101]\ : DFN1E1 - port map(D => sample_f0_53, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_53); - - \counter_RNISI4K4_3[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val_0, Y => sample_out_0_sqmuxa_3); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f0_wdata_75, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_75); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f0_wdata_82, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_82); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f0_wdata_94, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_94); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f0_wdata_76, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_76); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f0_13, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_13); - - \sample_out[121]\ : DFN1E1 - port map(D => sample_f0_wdata_6, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_6); - - \counter_RNI2NOI4[4]\ : NOR2A - port map(A => sample_f0_val_0, B => un10_sample_in_val, Y - => sample_out_val_14); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f0_wdata_57, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_57); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f0_47, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_47); - - \counter_RNIU1AC1[7]\ : NOR3C - port map(A => un10_sample_in_val_5, B => - un10_sample_in_val_4, C => un10_sample_in_val_17, Y => - un10_sample_in_val_22); - - \counter_RNO[11]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_66_8, Y => - \counter_4[8]\); - - \sample_out[104]\ : DFN1E1 - port map(D => sample_f0_56, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_56); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f0_wdata_61, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_61); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_0); - - \sample_out[124]\ : DFN1E1 - port map(D => sample_f0_wdata_3, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_3); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_1, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \sample_out[97]\ : DFN1E1 - port map(D => sample_f0_49, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_49); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_5); - - \sample_out[108]\ : DFN1E1 - port map(D => sample_f0_60, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_60); - - \counter_RNO[15]\ : NOR2B - port map(A => un10_sample_in_val, B => I_91_6, Y => - \counter_4[12]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f0_3, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_3); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f0_8, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_8); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \counter_RNIKCPU1[20]\ : NOR3C - port map(A => un10_sample_in_val_15, B => - un10_sample_in_val_14, C => un10_sample_in_val_20, Y => - un10_sample_in_val_24); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f0_wdata_95, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_95); - - \counter_RNO[7]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_38_8, Y => - \counter_4[4]\); - - \counter[6]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_15); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f0_33, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_33); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f0_38, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_38); - - \counter[3]\ : DFN1E1C0 - port map(D => \counter_4[0]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_11, CLK => lclk_c, CLR => rstn, E => - sample_f0_val_1, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_6); - - \counter_RNO[8]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_45_7, Y => - \counter_4[5]\); - - \counter_RNO[13]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_77_6, Y => - \counter_4[10]\); - - \counter_RNI3RPP[12]\ : NOR3A - port map(A => un10_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un10_sample_in_val_19); - - \counter_RNIAB89[7]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un10_sample_in_val_4); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_7); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f0_wdata_83, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_83); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f0_wdata_85, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_85); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f0_wdata_50, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_50); - - \counter_RNO[12]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_73_6, Y => - \counter_4[9]\); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f0_wdata_62, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_62); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f0_wdata_56, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_56); - - \counter_RNO[1]\ : NOR2B - port map(A => un10_sample_in_val, B => I_5_11, Y => - \counter_4_1[1]\); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[17]_net_1\); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_11); - - \counter_RNISI4K4_2[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val_0, Y => sample_out_0_sqmuxa_0); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter_RNI1FI5[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un10_sample_in_val_13); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_0, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f0_wdata_90, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_90); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f0_wdata_48, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_48); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - \sample_out[115]\ : DFN1E1 - port map(D => sample_f0_wdata_12, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f0_wdata_74, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_74); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_1, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f0_wdata_69, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_69); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f0_wdata_93, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_93); - - \sample_out[98]\ : DFN1E1 - port map(D => sample_f0_50, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_50); - - \sample_out[112]\ : DFN1E1 - port map(D => sample_f0_wdata_15, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_15); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[27]_net_1\); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f0_46, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_46); - - \sample_out[111]\ : DFN1E1 - port map(D => sample_f0_63, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_63); - - \counter_RNI3R4M[19]\ : NOR3A - port map(A => un10_sample_in_val_7, B => - \counter[22]_net_1\, C => \counter[19]_net_1\, Y => - un10_sample_in_val_17); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_5); - - \counter_RNIH789[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un10_sample_in_val_3); - - \counter_RNO[17]\ : NOR2B - port map(A => un10_sample_in_val, B => I_105_6, Y => - \counter_4[14]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f0_7, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_7); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \sample_out[114]\ : DFN1E1 - port map(D => sample_f0_wdata_13, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_5); - - \counter_RNIF7K5[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un10_sample_in_val_9); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f0_wdata_63, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_63); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_6); - - \sample_out[118]\ : DFN1E1 - port map(D => sample_f0_wdata_9, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_9); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f0_9, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_9); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f0_wdata_65, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_65); - - \counter_RNO[14]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_84_6, Y => - \counter_4[11]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f0_37, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_37); - - \counter[1]\ : DFN1E1C0 - port map(D => \counter_4_1[1]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => un10_sample_in_val, B => I_186_5, Y => - \counter_4[23]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f0_wdata_91, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_91); - - \counter_RNO[5]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_24_12, Y => - \counter_4[2]\); - - \sample_out[103]\ : DFN1E1 - port map(D => sample_f0_55, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_55); - - \sample_out[100]\ : DFN1E1 - port map(D => sample_f0_52, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_52); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[25]_net_1\); - - \sample_out[123]\ : DFN1E1 - port map(D => sample_f0_wdata_4, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_4); - - \sample_out[120]\ : DFN1E1 - port map(D => sample_f0_wdata_7, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_7); - - \counter_RNIJRSC[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un10_sample_in_val_1); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_14, CLK => lclk_c, CLR => rstn, - Q => sample_f1_val); - - \counter_RNO[3]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_13_15, Y => - \counter_4[0]\); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f0_39, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_39); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_6); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_5); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f0_0, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_0); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_8); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f0_45, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_45); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f0_wdata_84, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_84); - - \sample_out[99]\ : DFN1E1 - port map(D => sample_f0_51, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_51); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f0_wdata_79, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_79); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f0_wdata_51, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_51); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNIKVSC[18]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un10_sample_in_val_11); - - \counter_RNO[10]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_56_8, Y => - \counter_4[7]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_11); - - \counter_RNO[21]\ : NOR2B - port map(A => un10_sample_in_val, B => I_136_5, Y => - \counter_4[18]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_11); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f0_wdata_70, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_70); - - \counter_RNISI4K4[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val, Y => sample_out_0_sqmuxa); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_8); - - \counter_RNIQD151[4]\ : NOR3C - port map(A => un10_sample_in_val_9, B => - un10_sample_in_val_8, C => un10_sample_in_val_19, Y => - un10_sample_in_val_23); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => un10_sample_in_val, B => I_173_5, Y => - \counter_4[22]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_11); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_6); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f0_wdata_68, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_68); - - \counter_RNIHRSC[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un10_sample_in_val_5); - - \counter_RNIC6QE[24]\ : NOR3A - port map(A => un10_sample_in_val_13, B => - \counter[1]_net_1\, C => \counter[24]_net_1\, Y => - un10_sample_in_val_20); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNO[6]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_31_11, Y => - \counter_4[3]\); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_5); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f0_10, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_10); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_8); - - \counter_RNO[23]\ : NOR2B - port map(A => un10_sample_in_val, B => I_156_5, Y => - \counter_4[20]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f0_6, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_6); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f0_wdata_52, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_52); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f0_1, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_1); - - \counter_RNISI4K4_1[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val_0, Y => sample_out_0_sqmuxa_2); - - sample_out_val_0 : DFN1C0 - port map(D => sample_out_val_14, CLK => lclk_c, CLR => rstn, - Q => sample_f1_val_0); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_7); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_12); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f0_44, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_44); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_5); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f0_40, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_40); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f0_42, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_42); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_6); - - \counter_RNO[22]\ : NOR2B - port map(A => un10_sample_in_val, B => I_143_5, Y => - \counter_4[19]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f0_wdata_64, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_64); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f0_wdata_59, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_59); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f0_36, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_36); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f0_15, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_15); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f0_wdata_80, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_80); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_6); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[113]\ : DFN1E1 - port map(D => sample_f0_wdata_14, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_14); - - \sample_out[110]\ : DFN1E1 - port map(D => sample_f0_62, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_62); - - \counter_RNO[4]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_20_11, Y => - \counter_4[1]\); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \sample_out[106]\ : DFN1E1 - port map(D => sample_f0_58, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_58); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_6); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f0_wdata_78, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_78); - - \sample_out[107]\ : DFN1E1 - port map(D => sample_f0_59, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_59); - - \counter_RNO[18]\ : NOR2B - port map(A => un10_sample_in_val, B => I_115_6, Y => - \counter_4[15]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[126]\ : DFN1E1 - port map(D => sample_f0_wdata_1, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_1); - - \sample_out[127]\ : DFN1E1 - port map(D => sample_f0_wdata_0, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_0); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f0_5, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_5); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f0_wdata_67, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_67); - - \counter_RNO[27]\ : NOR2B - port map(A => un10_sample_in_val, B => I_196_5, Y => - \counter_4[24]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f0_11, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_11); - - \counter_RNICS4G4[4]\ : OR3C - port map(A => un10_sample_in_val_23, B => - un10_sample_in_val_22, C => un10_sample_in_val_24, Y => - un10_sample_in_val_0); - - \sample_out[109]\ : DFN1E1 - port map(D => sample_f0_61, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_61); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f0_wdata_71, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_71); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f0_wdata_53, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_53); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \counter_RNISI4K4_0[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val_0, Y => sample_out_0_sqmuxa_1); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f0_wdata_55, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_55); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f0_35, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_35); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f0_41, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_41); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => un10_sample_in_val, B => I_166_5, Y => - \counter_4[21]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[7]_net_1\); - - \counter_RNICS4G4_0[4]\ : OR3C - port map(A => un10_sample_in_val_23, B => - un10_sample_in_val_22, C => un10_sample_in_val_24, Y => - un10_sample_in_val); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_6); - - \counter_RNI2B5M[20]\ : NOR3A - port map(A => un10_sample_in_val_3, B => - \counter[23]_net_1\, C => \counter[20]_net_1\, Y => - un10_sample_in_val_15); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f0_wdata_89, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_89); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f0_14, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_14); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f0_12, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_12); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f0_wdata_60, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_60); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f0_43, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_43); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - \sample_out[96]\ : DFN1E1 - port map(D => sample_f0_48, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_48); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : NOR2B - port map(A => un10_sample_in_val, B => I_129_6, Y => - \counter_4[17]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f0_wdata_58, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_58); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f0_wdata_72, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_72); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f0_4, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_4); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f0_wdata_66, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_66); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f0_2, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_2); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f0_wdata_77, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_77); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f0_wdata_86, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_wdata_86); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f0_wdata_88, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_88); - - \counter_RNI6RPP[27]\ : NOR3A - port map(A => un10_sample_in_val_1, B => - \counter[11]_net_1\, C => \counter[27]_net_1\, Y => - un10_sample_in_val_14); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f0_wdata_81, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_81); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f0_34, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_34); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[9]_net_1\); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f0_32, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_32); - - \counter_RNO[19]\ : NOR2B - port map(A => un10_sample_in_val, B => I_122_6, Y => - \counter_4[16]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNIDR79[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un10_sample_in_val_7); - - \counter_RNO[9]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_52_7, Y => - \counter_4[6]\); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_6); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_5); - - \sample_out[116]\ : DFN1E1 - port map(D => sample_f0_wdata_11, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_11); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[18]_net_1\); - - \sample_out[117]\ : DFN1E1 - port map(D => sample_f0_wdata_10, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_10); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f0_wdata_87, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_wdata_87); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f0_wdata_54, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_54); - - \counter_RNO[16]\ : NOR2B - port map(A => un10_sample_in_val, B => I_98_6, Y => - \counter_4[13]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_0, CLK => lclk_c, CLR => rstn, E => - sample_f0_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f0_wdata_49, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_49); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f0_wdata_92, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_92); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - \sample_out[105]\ : DFN1E1 - port map(D => sample_f0_57, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_57); - - \sample_out[119]\ : DFN1E1 - port map(D => sample_f0_wdata_8, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity SYNC_FF_1 is - - port( sample_bit_counter_0 : in std_logic_vector(0 to 0); - SYNC_FF_1_VCC : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_bit_counter_n0 : out std_logic; - cnv_done_i : in std_logic; - N_36 : out std_logic - ); - -end SYNC_FF_1; - -architecture DEF_ARCH of SYNC_FF_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal cnv_run_sync, \A_temp[1]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sync_loop.0.A_temp_RNI0P5E[0]\ : OR2B - port map(A => cnv_run_sync, B => cnv_done_i, Y => N_36); - - \sync_loop.0.A_temp[0]\ : DFN1C0 - port map(D => \A_temp[1]\, CLK => lclk_c, CLR => rstn, Q - => cnv_run_sync); - - GND_i_0 : GND - port map(Y => GND_0); - - \sync_loop.1.A_temp[1]\ : DFN1C0 - port map(D => SYNC_FF_1_VCC, CLK => lclk_c, CLR => rstn, Q - => \A_temp[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sync_loop.0.A_temp_RNIU1FG[0]\ : AOI1B - port map(A => sample_bit_counter_0(0), B => cnv_done_i, C - => cnv_run_sync, Y => sample_bit_counter_n0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity SYNC_FF is - - port( cnv_ch1_c : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - cnv_sync : out std_logic; - cnv_sync_i : out std_logic - ); - -end SYNC_FF; - -architecture DEF_ARCH of SYNC_FF is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \cnv_sync\, \A_temp[1]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - cnv_sync <= \cnv_sync\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sync_loop.0.A_temp[0]\ : DFN1C0 - port map(D => \A_temp[1]\, CLK => lclk_c, CLR => rstn, Q - => \cnv_sync\); - - GND_i_0 : GND - port map(Y => GND_0); - - \sync_loop.1.A_temp[1]\ : DFN1C0 - port map(D => cnv_ch1_c, CLK => lclk_c, CLR => rstn, Q => - \A_temp[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sync_loop.0.A_temp_RNI61R4[0]\ : INV - port map(A => \cnv_sync\, Y => cnv_sync_i); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity AD7688_drvr is - - port( sample_4 : out std_logic_vector(15 downto 0); - sample_5 : out std_logic_vector(15 downto 0); - sample_6 : out std_logic_vector(15 downto 0); - sample_7 : out std_logic_vector(15 downto 0); - sample_0 : out std_logic_vector(15 downto 0); - sample_1 : out std_logic_vector(15 downto 0); - sample_2 : out std_logic_vector(15 downto 0); - sdo_adc_c : in std_logic_vector(7 downto 0); - sample_3 : out std_logic_vector(15 downto 0); - AD7688_drvr_VCC : in std_logic; - clk49_152MHz_c : in std_logic; - cnv_ch1_c : out std_logic; - sample_val : out std_logic; - sck_ch1_c : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end AD7688_drvr; - -architecture DEF_ARCH of AD7688_drvr is - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component SYNC_FF_1 - port( sample_bit_counter_0 : in std_logic_vector(0 to 0) := (others => 'U'); - SYNC_FF_1_VCC : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_bit_counter_n0 : out std_logic; - cnv_done_i : in std_logic := 'U'; - N_36 : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component SYNC_FF - port( cnv_ch1_c : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - cnv_sync : out std_logic; - cnv_sync_i : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \sample_bit_counter_4[0]_net_1\, - sample_bit_counter_n0, N_6, - \sample_bit_counter_3[0]_net_1\, - \sample_bit_counter_2[0]_net_1\, - \sample_bit_counter_1[0]_net_1\, - \sample_bit_counter_0[0]_net_1\, sample_0_0_sqmuxa_4, - \sample_bit_counter_RNIU4A5[5]_net_1\, - sample_0_0_sqmuxa_3, sample_0_0_sqmuxa_2, - sample_0_0_sqmuxa_1, sample_0_0_sqmuxa_0, - \sample_bit_counter_i[0]\, cnv_cycle_counter_32_0, - \cnv_cycle_counter[7]_net_1\, cnv_s_0_sqmuxa, - sample_bit_counterlde_i_a3_0_1, - \sample_bit_counter[3]_net_1\, - \sample_bit_counter[2]_net_1\, - \sample_bit_counter[4]_net_1\, un3_cnv_runlto8_0, - \cnv_cycle_counter[8]_net_1\, un3_cnv_runlto5_0, - \cnv_cycle_counter[4]_net_1\, - \cnv_cycle_counter[5]_net_1\, un2_cnv_runlto8_2, - \cnv_cycle_counter[2]_net_1\, - \cnv_cycle_counter[3]_net_1\, un2_cnv_runlto8_1, - \cnv_cycle_counter[6]_net_1\, un2_cnv_runlto8_0, N_11, - N_38, N_36, N_20, N_13, N_15, N_21, N_17, N_35, N_23, - N_30, cnv_cycle_counter_n7, cnv_cycle_counter_c6, - cnv_cycle_counter_n6, cnv_cycle_counter_c5, - cnv_cycle_counter_n5, cnv_cycle_counter_c4, - cnv_cycle_counter_n4, cnv_cycle_counter_c3, - cnv_cycle_counter_n3, cnv_cycle_counter_c2, - cnv_cycle_counter_n2, cnv_cycle_counter_c1, - sample_0_0_sqmuxa, \sample_bit_counter[1]_net_1\, - \sample_bit_counter[5]_net_1\, N_19, cnv_cycle_counter_n8, - N_102, cnv_cycle_counter_n1, \cnv_cycle_counter[1]_net_1\, - \cnv_cycle_counter[0]_net_1\, cnv_cycle_counter_n0, - un3_cnv_runlt8, \cnv_s_RNO\, cnv_done_1, cnv_sync_r_i_0, - cnv_sync, cnv_sync_i, cnv_done_i, - \sample_bit_counter[0]_net_1\, \shift_reg_3[0]_net_1\, - \shift_reg_3[1]_net_1\, \shift_reg_3[2]_net_1\, - \shift_reg_3[3]_net_1\, \shift_reg_3[4]_net_1\, - \shift_reg_3[5]_net_1\, \shift_reg_3[6]_net_1\, - \shift_reg_3[7]_net_1\, \shift_reg_3[8]_net_1\, - \shift_reg_3[9]_net_1\, \shift_reg_3[10]_net_1\, - \shift_reg_3[11]_net_1\, \shift_reg_3[12]_net_1\, - \shift_reg_3[13]_net_1\, \shift_reg_3[14]_net_1\, - \shift_reg_2[0]_net_1\, \shift_reg_2[1]_net_1\, - \shift_reg_2[2]_net_1\, \shift_reg_2[3]_net_1\, - \shift_reg_2[4]_net_1\, \shift_reg_2[5]_net_1\, - \shift_reg_2[6]_net_1\, \shift_reg_2[7]_net_1\, - \shift_reg_2[8]_net_1\, \shift_reg_2[9]_net_1\, - \shift_reg_2[10]_net_1\, \shift_reg_2[11]_net_1\, - \shift_reg_2[12]_net_1\, \shift_reg_2[13]_net_1\, - \shift_reg_2[14]_net_1\, \shift_reg_1[0]_net_1\, - \shift_reg_1[1]_net_1\, \shift_reg_1[2]_net_1\, - \shift_reg_1[3]_net_1\, \shift_reg_1[4]_net_1\, - \shift_reg_1[5]_net_1\, \shift_reg_1[6]_net_1\, - \shift_reg_1[7]_net_1\, \shift_reg_1[8]_net_1\, - \shift_reg_1[9]_net_1\, \shift_reg_1[10]_net_1\, - \shift_reg_1[11]_net_1\, \shift_reg_1[12]_net_1\, - \shift_reg_1[13]_net_1\, \shift_reg_1[14]_net_1\, - \shift_reg_0[0]_net_1\, \shift_reg_0[1]_net_1\, - \shift_reg_0[2]_net_1\, \shift_reg_0[3]_net_1\, - \shift_reg_0[4]_net_1\, \shift_reg_0[5]_net_1\, - \shift_reg_0[6]_net_1\, \shift_reg_0[7]_net_1\, - \shift_reg_0[8]_net_1\, \shift_reg_0[9]_net_1\, - \shift_reg_0[10]_net_1\, \shift_reg_0[11]_net_1\, - \shift_reg_0[12]_net_1\, \shift_reg_0[13]_net_1\, - \shift_reg_0[14]_net_1\, \shift_reg_7[0]_net_1\, - \shift_reg_7[1]_net_1\, \shift_reg_7[2]_net_1\, - \shift_reg_7[3]_net_1\, \shift_reg_7[4]_net_1\, - \shift_reg_7[5]_net_1\, \shift_reg_7[6]_net_1\, - \shift_reg_7[7]_net_1\, \shift_reg_7[8]_net_1\, - \shift_reg_7[9]_net_1\, \shift_reg_7[10]_net_1\, - \shift_reg_7[11]_net_1\, \shift_reg_7[12]_net_1\, - \shift_reg_7[13]_net_1\, \shift_reg_7[14]_net_1\, - \shift_reg_6[0]_net_1\, \shift_reg_6[1]_net_1\, - \shift_reg_6[2]_net_1\, \shift_reg_6[3]_net_1\, - \shift_reg_6[4]_net_1\, \shift_reg_6[5]_net_1\, - \shift_reg_6[6]_net_1\, \shift_reg_6[7]_net_1\, - \shift_reg_6[8]_net_1\, \shift_reg_6[9]_net_1\, - \shift_reg_6[10]_net_1\, \shift_reg_6[11]_net_1\, - \shift_reg_6[12]_net_1\, \shift_reg_6[13]_net_1\, - \shift_reg_6[14]_net_1\, \shift_reg_5[0]_net_1\, - \shift_reg_5[1]_net_1\, \shift_reg_5[2]_net_1\, - \shift_reg_5[3]_net_1\, \shift_reg_5[4]_net_1\, - \shift_reg_5[5]_net_1\, \shift_reg_5[6]_net_1\, - \shift_reg_5[7]_net_1\, \shift_reg_5[8]_net_1\, - \shift_reg_5[9]_net_1\, \shift_reg_5[10]_net_1\, - \shift_reg_5[11]_net_1\, \shift_reg_5[12]_net_1\, - \shift_reg_5[13]_net_1\, \shift_reg_5[14]_net_1\, - \shift_reg_4[0]_net_1\, \shift_reg_4[1]_net_1\, - \shift_reg_4[2]_net_1\, \shift_reg_4[3]_net_1\, - \shift_reg_4[4]_net_1\, \shift_reg_4[5]_net_1\, - \shift_reg_4[6]_net_1\, \shift_reg_4[7]_net_1\, - \shift_reg_4[8]_net_1\, \shift_reg_4[9]_net_1\, - \shift_reg_4[10]_net_1\, \shift_reg_4[11]_net_1\, - \shift_reg_4[12]_net_1\, \shift_reg_4[13]_net_1\, - \shift_reg_4[14]_net_1\, \cnv_ch1_c\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : SYNC_FF_1 - Use entity work.SYNC_FF_1(DEF_ARCH); - for all : SYNC_FF - Use entity work.SYNC_FF(DEF_ARCH); -begin - - cnv_ch1_c <= \cnv_ch1_c\; - - \sample_bit_counter_RNIUML11[5]\ : AO1A - port map(A => N_36, B => \sample_bit_counter[5]_net_1\, C - => N_30, Y => N_6); - - \sample_bit_counter[2]\ : DFN1E0C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[2]_net_1\); - - \shift_reg_0[1]\ : DFN1E1C0 - port map(D => \shift_reg_0[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[1]_net_1\); - - \shift_reg_7[14]\ : DFN1E1C0 - port map(D => \shift_reg_7[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[14]_net_1\); - - \sample_6[13]\ : DFN1E1 - port map(D => \shift_reg_6[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(13)); - - \sample_7[11]\ : DFN1E1 - port map(D => \shift_reg_7[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(11)); - - \sample_0[3]\ : DFN1E1 - port map(D => \shift_reg_0[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(3)); - - \cnv_cycle_counter_RNIHA8[5]\ : NOR2B - port map(A => \cnv_cycle_counter[5]_net_1\, B => - \cnv_cycle_counter[6]_net_1\, Y => un2_cnv_runlto8_1); - - \shift_reg_6[12]\ : DFN1E1C0 - port map(D => \shift_reg_6[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[12]_net_1\); - - \sample_1[0]\ : DFN1E1 - port map(D => sdo_adc_c(1), CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(0)); - - \sample_0[12]\ : DFN1E1 - port map(D => \shift_reg_0[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(12)); - - \shift_reg_6[9]\ : DFN1E1C0 - port map(D => \shift_reg_6[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[9]_net_1\); - - \shift_reg_2[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(2), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[0]_net_1\); - - \shift_reg_5[11]\ : DFN1E1C0 - port map(D => \shift_reg_5[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[11]_net_1\); - - \sample_bit_counter_RNISKS2_0[1]\ : NOR2 - port map(A => \sample_bit_counter[1]_net_1\, B => - \sample_bit_counter_0[0]_net_1\, Y => N_38); - - \sample_bit_counter_RNIO0M6_2[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_1); - - cnv_s : DFN1C0 - port map(D => \cnv_s_RNO\, CLK => clk49_152MHz_c, CLR => - rstn, Q => \cnv_ch1_c\); - - \sample_6[11]\ : DFN1E1 - port map(D => \shift_reg_6[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(11)); - - \sample_3[9]\ : DFN1E1 - port map(D => \shift_reg_3[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(9)); - - \shift_reg_0[10]\ : DFN1E1C0 - port map(D => \shift_reg_0[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[10]_net_1\); - - \shift_reg_7[6]\ : DFN1E1C0 - port map(D => \shift_reg_7[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[6]_net_1\); - - \shift_reg_7[2]\ : DFN1E1C0 - port map(D => \shift_reg_7[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[2]_net_1\); - - \sample_2[6]\ : DFN1E1 - port map(D => \shift_reg_2[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_2(6)); - - \cnv_cycle_counter[4]\ : DFN1C0 - port map(D => cnv_cycle_counter_n4, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[4]_net_1\); - - \cnv_cycle_counter_RNO[2]\ : XA1 - port map(A => \cnv_cycle_counter[2]_net_1\, B => - cnv_cycle_counter_c1, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n2); - - \sample_6[2]\ : DFN1E1 - port map(D => \shift_reg_6[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(2)); - - \sample_7[5]\ : DFN1E1 - port map(D => \shift_reg_7[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(5)); - - \shift_reg_5[6]\ : DFN1E1C0 - port map(D => \shift_reg_5[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[6]_net_1\); - - \shift_reg_0[14]\ : DFN1E1C0 - port map(D => \shift_reg_0[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[14]_net_1\); - - \shift_reg_1[7]\ : DFN1E1C0 - port map(D => \shift_reg_1[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[7]_net_1\); - - \sample_0[15]\ : DFN1E1 - port map(D => \shift_reg_0[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(15)); - - \sample_2[4]\ : DFN1E1 - port map(D => \shift_reg_2[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(4)); - - \sample_bit_counter_RNO[3]\ : XA1B - port map(A => N_21, B => \sample_bit_counter[3]_net_1\, C - => N_36, Y => N_15); - - \sample_1[6]\ : DFN1E1 - port map(D => \shift_reg_1[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(6)); - - \cnv_cycle_counter_RNO[8]\ : AX1E - port map(A => cnv_cycle_counter_c6, B => - cnv_cycle_counter_32_0, C => N_102, Y => - cnv_cycle_counter_n8); - - \sample_2[14]\ : DFN1E1 - port map(D => \shift_reg_2[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(14)); - - \sample_5[10]\ : DFN1E1 - port map(D => \shift_reg_5[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(10)); - - \sample_2[0]\ : DFN1E1 - port map(D => sdo_adc_c(2), CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(0)); - - \sample_bit_counter_RNIR0G3[2]\ : NOR2B - port map(A => \sample_bit_counter[2]_net_1\, B => N_20, Y - => N_21); - - \sample_5[1]\ : DFN1E1 - port map(D => \shift_reg_5[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(1)); - - \shift_reg_4[13]\ : DFN1E1C0 - port map(D => \shift_reg_4[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[13]_net_1\); - - \cnv_cycle_counter_RNO[1]\ : XA1 - port map(A => \cnv_cycle_counter[1]_net_1\, B => - \cnv_cycle_counter[0]_net_1\, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n1); - - \shift_reg_7[5]\ : DFN1E1C0 - port map(D => \shift_reg_7[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[5]_net_1\); - - \sample_0[7]\ : DFN1E1 - port map(D => \shift_reg_0[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(7)); - - \sample_0[13]\ : DFN1E1 - port map(D => \shift_reg_0[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(13)); - - \shift_reg_1[10]\ : DFN1E1C0 - port map(D => \shift_reg_1[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_1[10]_net_1\); - - \sample_bit_counter_RNISOM4[4]\ : OR3C - port map(A => N_21, B => \sample_bit_counter[3]_net_1\, C - => \sample_bit_counter[4]_net_1\, Y => N_23); - - \cnv_cycle_counter_RNIIE8[8]\ : NOR2B - port map(A => \cnv_cycle_counter[8]_net_1\, B => - \cnv_cycle_counter[4]_net_1\, Y => un2_cnv_runlto8_0); - - \sample_6[3]\ : DFN1E1 - port map(D => \shift_reg_6[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(3)); - - \shift_reg_1[5]\ : DFN1E1C0 - port map(D => \shift_reg_1[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[5]_net_1\); - - \shift_reg_5[1]\ : DFN1E1C0 - port map(D => \shift_reg_5[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[1]_net_1\); - - \shift_reg_1[14]\ : DFN1E1C0 - port map(D => \shift_reg_1[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[14]_net_1\); - - \sample_bit_counter_RNISHSI[2]\ : NOR3B - port map(A => sample_bit_counterlde_i_a3_0_1, B => N_38, C - => N_36, Y => N_30); - - \sample_bit_counter_RNI04Q1[2]\ : NOR3 - port map(A => \sample_bit_counter[3]_net_1\, B => - \sample_bit_counter[2]_net_1\, C => - \sample_bit_counter[4]_net_1\, Y => - sample_bit_counterlde_i_a3_0_1); - - cnv_done_RNO : OR2 - port map(A => cnv_sync_r_i_0, B => cnv_sync, Y => - cnv_done_1); - - \shift_reg_6[2]\ : DFN1E1C0 - port map(D => \shift_reg_6[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[2]_net_1\); - - \shift_reg_3[5]\ : DFN1E1C0 - port map(D => \shift_reg_3[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[5]_net_1\); - - \sample_7[6]\ : DFN1E1 - port map(D => \shift_reg_7[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(6)); - - \sample_7[10]\ : DFN1E1 - port map(D => \shift_reg_7[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(10)); - - \sample_6[6]\ : DFN1E1 - port map(D => \shift_reg_6[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(6)); - - \sample_0[11]\ : DFN1E1 - port map(D => \shift_reg_0[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(11)); - - \cnv_cycle_counter_RNIOMS[2]\ : OR3C - port map(A => un2_cnv_runlto8_1, B => un2_cnv_runlto8_0, C - => un2_cnv_runlto8_2, Y => cnv_s_0_sqmuxa); - - \shift_reg_0[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(0), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[0]_net_1\); - - \sample_0[0]\ : DFN1E1 - port map(D => sdo_adc_c(0), CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(0)); - - \sample_5[4]\ : DFN1E1 - port map(D => \shift_reg_5[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(4)); - - \sample_7[9]\ : DFN1E1 - port map(D => \shift_reg_7[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(9)); - - \sample_4[9]\ : DFN1E1 - port map(D => \shift_reg_4[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(9)); - - \cnv_cycle_counter[6]\ : DFN1C0 - port map(D => cnv_cycle_counter_n6, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[6]_net_1\); - - \shift_reg_2[12]\ : DFN1E1C0 - port map(D => \shift_reg_2[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[12]_net_1\); - - \sample_bit_counter_1[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_1[0]_net_1\); - - \sample_5[9]\ : DFN1E1 - port map(D => \shift_reg_5[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(9)); - - \shift_reg_7[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(7), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[0]_net_1\); - - SYNC_FF_run : SYNC_FF_1 - port map(sample_bit_counter_0(0) => - \sample_bit_counter_0[0]_net_1\, SYNC_FF_1_VCC => - AD7688_drvr_VCC, rstn => rstn, lclk_c => lclk_c, - sample_bit_counter_n0 => sample_bit_counter_n0, - cnv_done_i => cnv_done_i, N_36 => N_36); - - \shift_reg_1[1]\ : DFN1E1C0 - port map(D => \shift_reg_1[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[1]_net_1\); - - \shift_reg_3[9]\ : DFN1E1C0 - port map(D => \shift_reg_3[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_3[9]_net_1\); - - \sample_5[7]\ : DFN1E1 - port map(D => \shift_reg_5[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(7)); - - \sample_bit_counter[5]\ : DFN1E0C0 - port map(D => N_19, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[5]_net_1\); - - \sample_6[10]\ : DFN1E1 - port map(D => \shift_reg_6[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(10)); - - \sample_3[12]\ : DFN1E1 - port map(D => \shift_reg_3[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(12)); - - \shift_reg_3[6]\ : DFN1E1C0 - port map(D => \shift_reg_3[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[6]_net_1\); - - \sample_5[0]\ : DFN1E1 - port map(D => sdo_adc_c(5), CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(0)); - - \sample_4[7]\ : DFN1E1 - port map(D => \shift_reg_4[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(7)); - - \shift_reg_0[5]\ : DFN1E1C0 - port map(D => \shift_reg_0[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[5]_net_1\); - - \cnv_cycle_counter_RNIAUQ[6]\ : NOR2A - port map(A => \cnv_cycle_counter[6]_net_1\, B => - cnv_cycle_counter_c5, Y => cnv_cycle_counter_c6); - - \sample_bit_counter[4]\ : DFN1E0C0 - port map(D => N_17, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[4]_net_1\); - - \sample_4[12]\ : DFN1E1 - port map(D => \shift_reg_4[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(12)); - - \sample_2[7]\ : DFN1E1 - port map(D => \shift_reg_2[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_2(7)); - - \cnv_cycle_counter_RNO_1[8]\ : OR2B - port map(A => cnv_s_0_sqmuxa, B => - \cnv_cycle_counter[8]_net_1\, Y => N_102); - - \sample_bit_counter_RNIO0M6_0[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_2); - - \shift_reg_7[8]\ : DFN1E1C0 - port map(D => \shift_reg_7[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[8]_net_1\); - - \sample_bit_counter_RNISKS2[1]\ : NOR2B - port map(A => \sample_bit_counter[1]_net_1\, B => - \sample_bit_counter_0[0]_net_1\, Y => N_20); - - GND_i : GND - port map(Y => \GND\); - - \shift_reg_0[3]\ : DFN1E1C0 - port map(D => \shift_reg_0[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[3]_net_1\); - - \shift_reg_6[11]\ : DFN1E1C0 - port map(D => \shift_reg_6[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[11]_net_1\); - - \sample_3[15]\ : DFN1E1 - port map(D => \shift_reg_3[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(15)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \shift_reg_3[8]\ : DFN1E1C0 - port map(D => \shift_reg_3[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[8]_net_1\); - - \shift_reg_4[10]\ : DFN1E1C0 - port map(D => \shift_reg_4[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[10]_net_1\); - - \sample_4[15]\ : DFN1E1 - port map(D => \shift_reg_4[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(15)); - - \shift_reg_5[13]\ : DFN1E1C0 - port map(D => \shift_reg_5[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[13]_net_1\); - - \shift_reg_3[7]\ : DFN1E1C0 - port map(D => \shift_reg_3[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[7]_net_1\); - - \sample_0[2]\ : DFN1E1 - port map(D => \shift_reg_0[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(2)); - - \shift_reg_4[14]\ : DFN1E1C0 - port map(D => \shift_reg_4[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[14]_net_1\); - - \sample_0[5]\ : DFN1E1 - port map(D => \shift_reg_0[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(5)); - - \sample_3[13]\ : DFN1E1 - port map(D => \shift_reg_3[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(13)); - - \sample_2[5]\ : DFN1E1 - port map(D => \shift_reg_2[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(5)); - - \shift_reg_2[5]\ : DFN1E1C0 - port map(D => \shift_reg_2[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[5]_net_1\); - - \sample_4[13]\ : DFN1E1 - port map(D => \shift_reg_4[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(13)); - - \sample_3[1]\ : DFN1E1 - port map(D => \shift_reg_3[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(1)); - - \cnv_cycle_counter_RNILTB[2]\ : OA1 - port map(A => \cnv_cycle_counter[2]_net_1\, B => - \cnv_cycle_counter[3]_net_1\, C => - \cnv_cycle_counter[7]_net_1\, Y => un2_cnv_runlto8_2); - - \cnv_cycle_counter_RNICPA[2]\ : NOR2B - port map(A => cnv_cycle_counter_c1, B => - \cnv_cycle_counter[2]_net_1\, Y => cnv_cycle_counter_c2); - - \sample_0[1]\ : DFN1E1 - port map(D => \shift_reg_0[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(1)); - - \sample_bit_counter_RNIO0M6_3[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_3); - - \sample_0[10]\ : DFN1E1 - port map(D => \shift_reg_0[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(10)); - - \shift_reg_0[2]\ : DFN1E1C0 - port map(D => \shift_reg_0[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[2]_net_1\); - - \sample_2[12]\ : DFN1E1 - port map(D => \shift_reg_2[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(12)); - - \sample_6[0]\ : DFN1E1 - port map(D => sdo_adc_c(6), CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(0)); - - \shift_reg_3[12]\ : DFN1E1C0 - port map(D => \shift_reg_3[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[12]_net_1\); - - \sample_val\ : DFN1C0 - port map(D => \sample_bit_counter_RNIU4A5[5]_net_1\, CLK - => lclk_c, CLR => rstn, Q => sample_val); - - \cnv_cycle_counter_RNO[3]\ : XA1 - port map(A => \cnv_cycle_counter[3]_net_1\, B => - cnv_cycle_counter_c2, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n3); - - \sample_3[11]\ : DFN1E1 - port map(D => \shift_reg_3[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(11)); - - \sample_0[9]\ : DFN1E1 - port map(D => \shift_reg_0[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(9)); - - \shift_reg_5[8]\ : DFN1E1C0 - port map(D => \shift_reg_5[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[8]_net_1\); - - \sample_bit_counter_RNO[4]\ : NOR3B - port map(A => N_35, B => N_23, C => N_36, Y => N_17); - - \cnv_cycle_counter[3]\ : DFN1C0 - port map(D => cnv_cycle_counter_n3, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[3]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_4[11]\ : DFN1E1 - port map(D => \shift_reg_4[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(11)); - - \shift_reg_7[12]\ : DFN1E1C0 - port map(D => \shift_reg_7[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[12]_net_1\); - - \sample_6[7]\ : DFN1E1 - port map(D => \shift_reg_6[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(7)); - - \sample_2[9]\ : DFN1E1 - port map(D => \shift_reg_2[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_2(9)); - - \cnv_cycle_counter_RNO_0[8]\ : NOR2B - port map(A => \cnv_cycle_counter[7]_net_1\, B => - cnv_s_0_sqmuxa, Y => cnv_cycle_counter_32_0); - - \shift_reg_6[1]\ : DFN1E1C0 - port map(D => \shift_reg_6[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[1]_net_1\); - - \shift_reg_7[7]\ : DFN1E1C0 - port map(D => \shift_reg_7[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[7]_net_1\); - - \sample_2[15]\ : DFN1E1 - port map(D => \shift_reg_2[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(15)); - - \sample_bit_counter_0[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_0[0]_net_1\); - - \shift_reg_6[3]\ : DFN1E1C0 - port map(D => \shift_reg_6[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[3]_net_1\); - - \sample_6[4]\ : DFN1E1 - port map(D => \shift_reg_6[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(4)); - - \sample_bit_counter_RNIO0M6[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_0); - - \sample_4[3]\ : DFN1E1 - port map(D => \shift_reg_4[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(3)); - - \sample_1[9]\ : DFN1E1 - port map(D => \shift_reg_1[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(9)); - - \shift_reg_5[5]\ : DFN1E1C0 - port map(D => \shift_reg_5[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[5]_net_1\); - - \cnv_cycle_counter_RNIPJI[4]\ : NOR2B - port map(A => cnv_cycle_counter_c3, B => - \cnv_cycle_counter[4]_net_1\, Y => cnv_cycle_counter_c4); - - \cnv_cycle_counter[7]\ : DFN1C0 - port map(D => cnv_cycle_counter_n7, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[7]_net_1\); - - \sample_1[14]\ : DFN1E1 - port map(D => \shift_reg_1[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(14)); - - \shift_reg_2[11]\ : DFN1E1C0 - port map(D => \shift_reg_2[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[11]_net_1\); - - \shift_reg_7[3]\ : DFN1E1C0 - port map(D => \shift_reg_7[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[3]_net_1\); - - \shift_reg_5[10]\ : DFN1E1C0 - port map(D => \shift_reg_5[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[10]_net_1\); - - \shift_reg_3[4]\ : DFN1E1C0 - port map(D => \shift_reg_3[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[4]_net_1\); - - \sample_2[13]\ : DFN1E1 - port map(D => \shift_reg_2[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(13)); - - \sample_3[0]\ : DFN1E1 - port map(D => sdo_adc_c(3), CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(0)); - - \shift_reg_0[12]\ : DFN1E1C0 - port map(D => \shift_reg_0[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[12]_net_1\); - - \sample_4[2]\ : DFN1E1 - port map(D => \shift_reg_4[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(2)); - - \sample_bit_counter[1]\ : DFN1E0C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[1]_net_1\); - - \shift_reg_5[14]\ : DFN1E1C0 - port map(D => \shift_reg_5[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[14]_net_1\); - - \sample_7[0]\ : DFN1E1 - port map(D => sdo_adc_c(7), CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(0)); - - \sample_2[3]\ : DFN1E1 - port map(D => \shift_reg_2[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(3)); - - \sample_3[7]\ : DFN1E1 - port map(D => \shift_reg_3[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(7)); - - \sample_7[1]\ : DFN1E1 - port map(D => \shift_reg_7[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(1)); - - \sample_2[11]\ : DFN1E1 - port map(D => \shift_reg_2[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(11)); - - cnv_sync_r : DFN1P0 - port map(D => cnv_sync_i, CLK => lclk_c, PRE => rstn, Q => - cnv_sync_r_i_0); - - \shift_reg_1[9]\ : DFN1E1C0 - port map(D => \shift_reg_1[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[9]_net_1\); - - \shift_reg_6[13]\ : DFN1E1C0 - port map(D => \shift_reg_6[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[13]_net_1\); - - \sample_6[1]\ : DFN1E1 - port map(D => \shift_reg_6[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(1)); - - \shift_reg_0[8]\ : DFN1E1C0 - port map(D => \shift_reg_0[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[8]_net_1\); - - \sample_3[10]\ : DFN1E1 - port map(D => \shift_reg_3[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(10)); - - \shift_reg_4[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(4), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[0]_net_1\); - - SYNC_FF_cnv : SYNC_FF - port map(cnv_ch1_c => \cnv_ch1_c\, rstn => rstn, lclk_c => - lclk_c, cnv_sync => cnv_sync, cnv_sync_i => cnv_sync_i); - - \shift_reg_2[2]\ : DFN1E1C0 - port map(D => \shift_reg_2[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[2]_net_1\); - - \shift_reg_1[3]\ : DFN1E1C0 - port map(D => \shift_reg_1[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[3]_net_1\); - - \shift_reg_1[12]\ : DFN1E1C0 - port map(D => \shift_reg_1[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[12]_net_1\); - - \sample_7[2]\ : DFN1E1 - port map(D => \shift_reg_7[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(2)); - - \sample_bit_counter_RNO_0[4]\ : AO1 - port map(A => \sample_bit_counter[3]_net_1\, B => N_21, C - => \sample_bit_counter[4]_net_1\, Y => N_35); - - \sample_4[10]\ : DFN1E1 - port map(D => \shift_reg_4[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_4(10)); - - \sample_3[8]\ : DFN1E1 - port map(D => \shift_reg_3[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(8)); - - \shift_reg_3[3]\ : DFN1E1C0 - port map(D => \shift_reg_3[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[3]_net_1\); - - \shift_reg_1[8]\ : DFN1E1C0 - port map(D => \shift_reg_1[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[8]_net_1\); - - \sample_bit_counter_3[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_3[0]_net_1\); - - \cnv_cycle_counter[8]\ : DFN1C0 - port map(D => cnv_cycle_counter_n8, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[8]_net_1\); - - \sample_bit_counter[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter[0]_net_1\); - - \sample_bit_counter_RNIO0M6_1[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_4); - - \sample_1[1]\ : DFN1E1 - port map(D => \shift_reg_1[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(1)); - - \shift_reg_4[1]\ : DFN1E1C0 - port map(D => \shift_reg_4[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[1]_net_1\); - - \cnv_cycle_counter_RNO[0]\ : NOR2A - port map(A => cnv_s_0_sqmuxa, B => - \cnv_cycle_counter[0]_net_1\, Y => cnv_cycle_counter_n0); - - \sample_5[14]\ : DFN1E1 - port map(D => \shift_reg_5[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(14)); - - \shift_reg_3[1]\ : DFN1E1C0 - port map(D => \shift_reg_3[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[1]_net_1\); - - \shift_reg_2[8]\ : DFN1E1C0 - port map(D => \shift_reg_2[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[8]_net_1\); - - \sample_2[8]\ : DFN1E1 - port map(D => \shift_reg_2[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_2(8)); - - \shift_reg_3[11]\ : DFN1E1C0 - port map(D => \shift_reg_3[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[11]_net_1\); - - \shift_reg_0[4]\ : DFN1E1C0 - port map(D => \shift_reg_0[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[4]_net_1\); - - \sample_4[5]\ : DFN1E1 - port map(D => \shift_reg_4[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(5)); - - \sample_0[4]\ : DFN1E1 - port map(D => \shift_reg_0[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(4)); - - \shift_reg_7[11]\ : DFN1E1C0 - port map(D => \shift_reg_7[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[11]_net_1\); - - \shift_reg_3[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(3), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[0]_net_1\); - - \sample_3[4]\ : DFN1E1 - port map(D => \shift_reg_3[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(4)); - - \sample_5[5]\ : DFN1E1 - port map(D => \shift_reg_5[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(5)); - - \shift_reg_1[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(1), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_1[0]_net_1\); - - \shift_reg_4[9]\ : DFN1E1C0 - port map(D => \shift_reg_4[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[9]_net_1\); - - \shift_reg_1[6]\ : DFN1E1C0 - port map(D => \shift_reg_1[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[6]_net_1\); - - \sample_4[1]\ : DFN1E1 - port map(D => \shift_reg_4[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(1)); - - \shift_reg_2[9]\ : DFN1E1C0 - port map(D => \shift_reg_2[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[9]_net_1\); - - \shift_reg_4[2]\ : DFN1E1C0 - port map(D => \shift_reg_4[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[2]_net_1\); - - \sample_7[8]\ : DFN1E1 - port map(D => \shift_reg_7[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(8)); - - \sample_7[14]\ : DFN1E1 - port map(D => \shift_reg_7[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(14)); - - \sample_2[10]\ : DFN1E1 - port map(D => \shift_reg_2[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(10)); - - \shift_reg_6[10]\ : DFN1E1C0 - port map(D => \shift_reg_6[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[10]_net_1\); - - \shift_reg_3[2]\ : DFN1E1C0 - port map(D => \shift_reg_3[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[2]_net_1\); - - \shift_reg_4[12]\ : DFN1E1C0 - port map(D => \shift_reg_4[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[12]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \shift_reg_7[4]\ : DFN1E1C0 - port map(D => \shift_reg_7[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[4]_net_1\); - - \shift_reg_2[13]\ : DFN1E1C0 - port map(D => \shift_reg_2[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[13]_net_1\); - - \sample_6[5]\ : DFN1E1 - port map(D => \shift_reg_6[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(5)); - - \shift_reg_6[14]\ : DFN1E1C0 - port map(D => \shift_reg_6[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[14]_net_1\); - - \cnv_cycle_counter_RNO[6]\ : XA1A - port map(A => \cnv_cycle_counter[6]_net_1\, B => - cnv_cycle_counter_c5, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n6); - - \sample_bit_counter_2[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_2[0]_net_1\); - - \sample_5[2]\ : DFN1E1 - port map(D => \shift_reg_5[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(2)); - - \sample_bit_counter_RNIU4A5[5]\ : NOR2 - port map(A => \sample_bit_counter[5]_net_1\, B => N_23, Y - => \sample_bit_counter_RNIU4A5[5]_net_1\); - - \sample_5[8]\ : DFN1E1 - port map(D => \shift_reg_5[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(8)); - - \sample_1[12]\ : DFN1E1 - port map(D => \shift_reg_1[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(12)); - - \shift_reg_2[6]\ : DFN1E1C0 - port map(D => \shift_reg_2[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[6]_net_1\); - - \shift_reg_0[11]\ : DFN1E1C0 - port map(D => \shift_reg_0[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[11]_net_1\); - - \sample_6[14]\ : DFN1E1 - port map(D => \shift_reg_6[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(14)); - - cnv_s_RNO_0 : OA1 - port map(A => cnv_cycle_counter_c3, B => un3_cnv_runlto5_0, - C => \cnv_cycle_counter[6]_net_1\, Y => un3_cnv_runlt8); - - \shift_reg_4[8]\ : DFN1E1C0 - port map(D => \shift_reg_4[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[8]_net_1\); - - cnv_s_RNO_1 : OR2 - port map(A => \cnv_cycle_counter[8]_net_1\, B => - \cnv_cycle_counter[7]_net_1\, Y => un3_cnv_runlto8_0); - - \cnv_cycle_counter[2]\ : DFN1C0 - port map(D => cnv_cycle_counter_n2, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[2]_net_1\); - - \sample_7[7]\ : DFN1E1 - port map(D => \shift_reg_7[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(7)); - - \sample_3[5]\ : DFN1E1 - port map(D => \shift_reg_3[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(5)); - - \shift_reg_7[1]\ : DFN1E1C0 - port map(D => \shift_reg_7[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[1]_net_1\); - - \sample_7[3]\ : DFN1E1 - port map(D => \shift_reg_7[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(3)); - - \sample_3[6]\ : DFN1E1 - port map(D => \shift_reg_3[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(6)); - - \cnv_cycle_counter_RNO[5]\ : XA1 - port map(A => \cnv_cycle_counter[5]_net_1\, B => - cnv_cycle_counter_c4, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n5); - - \shift_reg_5[9]\ : DFN1E1C0 - port map(D => \shift_reg_5[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[9]_net_1\); - - \shift_reg_4[6]\ : DFN1E1C0 - port map(D => \shift_reg_4[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[6]_net_1\); - - \shift_reg_1[4]\ : DFN1E1C0 - port map(D => \shift_reg_1[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[4]_net_1\); - - \shift_reg_4[5]\ : DFN1E1C0 - port map(D => \shift_reg_4[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[5]_net_1\); - - \sample_2[1]\ : DFN1E1 - port map(D => \shift_reg_2[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(1)); - - \sample_1[15]\ : DFN1E1 - port map(D => \shift_reg_1[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(15)); - - sck : DFN1P0 - port map(D => \sample_bit_counter_i[0]\, CLK => lclk_c, PRE - => rstn, Q => sck_ch1_c); - - \shift_reg_6[8]\ : DFN1E1C0 - port map(D => \shift_reg_6[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[8]_net_1\); - - \shift_reg_5[4]\ : DFN1E1C0 - port map(D => \shift_reg_5[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[4]_net_1\); - - \cnv_cycle_counter_RNO[4]\ : XA1 - port map(A => \cnv_cycle_counter[4]_net_1\, B => - cnv_cycle_counter_c3, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n4); - - \sample_bit_counter_RNO[2]\ : XA1B - port map(A => N_20, B => \sample_bit_counter[2]_net_1\, C - => N_36, Y => N_13); - - \sample_5[6]\ : DFN1E1 - port map(D => \shift_reg_5[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(6)); - - \sample_bit_counter_4[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_4[0]_net_1\); - - \shift_reg_0[6]\ : DFN1E1C0 - port map(D => \shift_reg_0[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[6]_net_1\); - - \sample_1[3]\ : DFN1E1 - port map(D => \shift_reg_1[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(3)); - - \shift_reg_5[3]\ : DFN1E1C0 - port map(D => \shift_reg_5[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[3]_net_1\); - - \sample_3[2]\ : DFN1E1 - port map(D => \shift_reg_3[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(2)); - - \sample_5[3]\ : DFN1E1 - port map(D => \shift_reg_5[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(3)); - - \shift_reg_1[11]\ : DFN1E1C0 - port map(D => \shift_reg_1[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[11]_net_1\); - - \sample_bit_counter_RNO[5]\ : NOR2 - port map(A => N_36, B => N_23, Y => N_19); - - \cnv_cycle_counter[5]\ : DFN1C0 - port map(D => cnv_cycle_counter_n5, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[5]_net_1\); - - \sample_1[7]\ : DFN1E1 - port map(D => \shift_reg_1[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(7)); - - \sample_1[13]\ : DFN1E1 - port map(D => \shift_reg_1[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(13)); - - sck_RNO : INV - port map(A => \sample_bit_counter_0[0]_net_1\, Y => - \sample_bit_counter_i[0]\); - - \shift_reg_5[2]\ : DFN1E1C0 - port map(D => \shift_reg_5[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[2]_net_1\); - - \sample_bit_counter_RNO[1]\ : NOR3 - port map(A => N_38, B => N_36, C => N_20, Y => N_11); - - \sample_6[8]\ : DFN1E1 - port map(D => \shift_reg_6[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_6(8)); - - \sample_1[2]\ : DFN1E1 - port map(D => \shift_reg_1[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(2)); - - \sample_0[8]\ : DFN1E1 - port map(D => \shift_reg_0[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(8)); - - \sample_0[14]\ : DFN1E1 - port map(D => \shift_reg_0[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(14)); - - \sample_5[12]\ : DFN1E1 - port map(D => \shift_reg_5[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(12)); - - \shift_reg_0[9]\ : DFN1E1C0 - port map(D => \shift_reg_0[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[9]_net_1\); - - \sample_1[11]\ : DFN1E1 - port map(D => \shift_reg_1[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(11)); - - \shift_reg_5[7]\ : DFN1E1C0 - port map(D => \shift_reg_5[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[7]_net_1\); - - \sample_0[6]\ : DFN1E1 - port map(D => \shift_reg_0[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(6)); - - \shift_reg_2[10]\ : DFN1E1C0 - port map(D => \shift_reg_2[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[10]_net_1\); - - \shift_reg_5[12]\ : DFN1E1C0 - port map(D => \shift_reg_5[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[12]_net_1\); - - \shift_reg_3[13]\ : DFN1E1C0 - port map(D => \shift_reg_3[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[13]_net_1\); - - cnv_done : DFN1P0 - port map(D => cnv_done_1, CLK => lclk_c, PRE => rstn, Q => - cnv_done_i); - - \shift_reg_2[1]\ : DFN1E1C0 - port map(D => \shift_reg_2[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[1]_net_1\); - - \sample_7[4]\ : DFN1E1 - port map(D => \shift_reg_7[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(4)); - - \sample_4[6]\ : DFN1E1 - port map(D => \shift_reg_4[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(6)); - - \shift_reg_1[2]\ : DFN1E1C0 - port map(D => \shift_reg_1[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[2]_net_1\); - - \shift_reg_7[13]\ : DFN1E1C0 - port map(D => \shift_reg_7[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[13]_net_1\); - - \shift_reg_2[14]\ : DFN1E1C0 - port map(D => \shift_reg_2[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[14]_net_1\); - - \shift_reg_6[5]\ : DFN1E1C0 - port map(D => \shift_reg_6[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[5]_net_1\); - - \sample_4[8]\ : DFN1E1 - port map(D => \shift_reg_4[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(8)); - - \sample_5[15]\ : DFN1E1 - port map(D => \shift_reg_5[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(15)); - - \shift_reg_2[3]\ : DFN1E1C0 - port map(D => \shift_reg_2[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[3]_net_1\); - - \cnv_cycle_counter_RNI727[1]\ : NOR2B - port map(A => \cnv_cycle_counter[1]_net_1\, B => - \cnv_cycle_counter[0]_net_1\, Y => cnv_cycle_counter_c1); - - cnv_s_RNO : OAI1 - port map(A => un3_cnv_runlt8, B => un3_cnv_runlto8_0, C => - cnv_s_0_sqmuxa, Y => \cnv_s_RNO\); - - \shift_reg_6[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(6), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[0]_net_1\); - - \cnv_cycle_counter[0]\ : DFN1C0 - port map(D => cnv_cycle_counter_n0, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[0]_net_1\); - - \shift_reg_2[7]\ : DFN1E1C0 - port map(D => \shift_reg_2[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[7]_net_1\); - - \shift_reg_6[4]\ : DFN1E1C0 - port map(D => \shift_reg_6[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[4]_net_1\); - - \shift_reg_2[4]\ : DFN1E1C0 - port map(D => \shift_reg_2[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[4]_net_1\); - - \sample_6[9]\ : DFN1E1 - port map(D => \shift_reg_6[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_6(9)); - - \cnv_cycle_counter_RNI1NM[5]\ : OR2B - port map(A => cnv_cycle_counter_c4, B => - \cnv_cycle_counter[5]_net_1\, Y => cnv_cycle_counter_c5); - - \shift_reg_4[4]\ : DFN1E1C0 - port map(D => \shift_reg_4[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[4]_net_1\); - - \sample_7[12]\ : DFN1E1 - port map(D => \shift_reg_7[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(12)); - - \cnv_cycle_counter_RNIIKE[3]\ : NOR2B - port map(A => cnv_cycle_counter_c2, B => - \cnv_cycle_counter[3]_net_1\, Y => cnv_cycle_counter_c3); - - \shift_reg_4[3]\ : DFN1E1C0 - port map(D => \shift_reg_4[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[3]_net_1\); - - \shift_reg_4[11]\ : DFN1E1C0 - port map(D => \shift_reg_4[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[11]_net_1\); - - \sample_bit_counter[3]\ : DFN1E0C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[3]_net_1\); - - \sample_5[13]\ : DFN1E1 - port map(D => \shift_reg_5[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(13)); - - \shift_reg_0[7]\ : DFN1E1C0 - port map(D => \shift_reg_0[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[7]_net_1\); - - cnv_s_RNO_2 : OR2 - port map(A => \cnv_cycle_counter[4]_net_1\, B => - \cnv_cycle_counter[5]_net_1\, Y => un3_cnv_runlto5_0); - - \shift_reg_0[13]\ : DFN1E1C0 - port map(D => \shift_reg_0[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[13]_net_1\); - - \sample_2[2]\ : DFN1E1 - port map(D => \shift_reg_2[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(2)); - - \sample_1[8]\ : DFN1E1 - port map(D => \shift_reg_1[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(8)); - - \sample_1[5]\ : DFN1E1 - port map(D => \shift_reg_1[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(5)); - - \sample_6[12]\ : DFN1E1 - port map(D => \shift_reg_6[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(12)); - - \cnv_cycle_counter_RNO[7]\ : XA1 - port map(A => \cnv_cycle_counter[7]_net_1\, B => - cnv_cycle_counter_c6, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n7); - - \sample_bit_counter_RNIO0M6_4[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa); - - \sample_7[15]\ : DFN1E1 - port map(D => \shift_reg_7[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(15)); - - \sample_4[0]\ : DFN1E1 - port map(D => sdo_adc_c(4), CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_4(0)); - - \shift_reg_5[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(5), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[0]_net_1\); - - \sample_3[3]\ : DFN1E1 - port map(D => \shift_reg_3[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(3)); - - \sample_5[11]\ : DFN1E1 - port map(D => \shift_reg_5[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(11)); - - \shift_reg_4[7]\ : DFN1E1C0 - port map(D => \shift_reg_4[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[7]_net_1\); - - \shift_reg_6[6]\ : DFN1E1C0 - port map(D => \shift_reg_6[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[6]_net_1\); - - \sample_4[4]\ : DFN1E1 - port map(D => \shift_reg_4[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(4)); - - \sample_6[15]\ : DFN1E1 - port map(D => \shift_reg_6[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(15)); - - \shift_reg_3[10]\ : DFN1E1C0 - port map(D => \shift_reg_3[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[10]_net_1\); - - \sample_1[10]\ : DFN1E1 - port map(D => \shift_reg_1[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(10)); - - \sample_3[14]\ : DFN1E1 - port map(D => \shift_reg_3[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(14)); - - \sample_7[13]\ : DFN1E1 - port map(D => \shift_reg_7[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(13)); - - \shift_reg_7[9]\ : DFN1E1C0 - port map(D => \shift_reg_7[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[9]_net_1\); - - \sample_1[4]\ : DFN1E1 - port map(D => \shift_reg_1[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(4)); - - \cnv_cycle_counter[1]\ : DFN1C0 - port map(D => cnv_cycle_counter_n1, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[1]_net_1\); - - \shift_reg_7[10]\ : DFN1E1C0 - port map(D => \shift_reg_7[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[10]_net_1\); - - \sample_4[14]\ : DFN1E1 - port map(D => \shift_reg_4[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(14)); - - \shift_reg_6[7]\ : DFN1E1C0 - port map(D => \shift_reg_6[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[7]_net_1\); - - \shift_reg_3[14]\ : DFN1E1C0 - port map(D => \shift_reg_3[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[14]_net_1\); - - \shift_reg_1[13]\ : DFN1E1C0 - port map(D => \shift_reg_1[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[13]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_lfr_wf_picker_ip is - - port( nb_snapshot_param : in std_logic_vector(10 downto 0); - coarse_time_i : in std_logic_vector(0 to 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - coarse_time : in std_logic_vector(0 to 0); - status_new_err : out std_logic_vector(3 downto 0); - hwdata : out std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - l1_0_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - bco_msb_1_m : in std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - hgrant : in std_logic_vector(3 to 3); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - bco_msb_1 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - hmaster_0 : in std_logic_vector(1 to 1); - hsize : out std_logic_vector(1 downto 0); - nhmaster_1_i : in std_logic_vector(0 to 0); - iosn_1 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - htrans : out std_logic_vector(1 downto 0); - hburst : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0); - sdo_adc_c : in std_logic_vector(7 downto 0); - data_shaping_R0 : in std_logic; - data_shaping_R0_0 : in std_logic; - enable_f0 : in std_logic; - burst_f0 : in std_logic; - data_shaping_R1 : in std_logic; - data_shaping_R1_0 : in std_logic; - enable_f1 : in std_logic; - burst_f1 : in std_logic; - enable_f2 : in std_logic; - burst_f2 : in std_logic; - enable_f3 : in std_logic; - m26_m1_e : out std_logic; - m19_a1_6_i_0 : out std_logic; - m19_a0_6_i_0 : out std_logic; - m19_0_N_15_i_0_li : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - Lock_RNIU86D : out std_logic; - hbusreq_i_3 : out std_logic; - arb_1 : in std_logic; - un1_dmain_6 : out std_logic; - hwrite : out std_logic; - IdlePhase : out std_logic; - lpp_top_lfr_wf_picker_ip_GND : in std_logic; - sck_ch1_c : out std_logic; - cnv_ch1_c : out std_logic; - clk49_152MHz_c : in std_logic; - lpp_top_lfr_wf_picker_ip_VCC : in std_logic; - data_shaping_SP0 : in std_logic; - data_shaping_SP1 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_top_lfr_wf_picker_ip; - -architecture DEF_ARCH of lpp_top_lfr_wf_picker_ip is - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2 - port( sample_filter_v2_out_0 : out std_logic; - sample_filter_v2_out_1 : out std_logic; - sample_filter_v2_out_2 : out std_logic; - sample_filter_v2_out_3 : out std_logic; - sample_filter_v2_out_4 : out std_logic; - sample_filter_v2_out_5 : out std_logic; - sample_filter_v2_out_6 : out std_logic; - sample_filter_v2_out_7 : out std_logic; - sample_filter_v2_out_8 : out std_logic; - sample_filter_v2_out_9 : out std_logic; - sample_filter_v2_out_10 : out std_logic; - sample_filter_v2_out_11 : out std_logic; - sample_filter_v2_out_12 : out std_logic; - sample_filter_v2_out_13 : out std_logic; - sample_filter_v2_out_14 : out std_logic; - sample_filter_v2_out_15 : out std_logic; - sample_filter_v2_out_18 : out std_logic; - sample_filter_v2_out_19 : out std_logic; - sample_filter_v2_out_20 : out std_logic; - sample_filter_v2_out_21 : out std_logic; - sample_filter_v2_out_22 : out std_logic; - sample_filter_v2_out_23 : out std_logic; - sample_filter_v2_out_24 : out std_logic; - sample_filter_v2_out_25 : out std_logic; - sample_filter_v2_out_26 : out std_logic; - sample_filter_v2_out_27 : out std_logic; - sample_filter_v2_out_28 : out std_logic; - sample_filter_v2_out_29 : out std_logic; - sample_filter_v2_out_30 : out std_logic; - sample_filter_v2_out_31 : out std_logic; - sample_filter_v2_out_32 : out std_logic; - sample_filter_v2_out_33 : out std_logic; - sample_filter_v2_out_36 : out std_logic; - sample_filter_v2_out_37 : out std_logic; - sample_filter_v2_out_38 : out std_logic; - sample_filter_v2_out_39 : out std_logic; - sample_filter_v2_out_40 : out std_logic; - sample_filter_v2_out_41 : out std_logic; - sample_filter_v2_out_42 : out std_logic; - sample_filter_v2_out_43 : out std_logic; - sample_filter_v2_out_44 : out std_logic; - sample_filter_v2_out_45 : out std_logic; - sample_filter_v2_out_46 : out std_logic; - sample_filter_v2_out_47 : out std_logic; - sample_filter_v2_out_48 : out std_logic; - sample_filter_v2_out_49 : out std_logic; - sample_filter_v2_out_50 : out std_logic; - sample_filter_v2_out_51 : out std_logic; - sample_filter_v2_out_54 : out std_logic; - sample_filter_v2_out_55 : out std_logic; - sample_filter_v2_out_56 : out std_logic; - sample_filter_v2_out_57 : out std_logic; - sample_filter_v2_out_58 : out std_logic; - sample_filter_v2_out_59 : out std_logic; - sample_filter_v2_out_60 : out std_logic; - sample_filter_v2_out_61 : out std_logic; - sample_filter_v2_out_62 : out std_logic; - sample_filter_v2_out_63 : out std_logic; - sample_filter_v2_out_64 : out std_logic; - sample_filter_v2_out_65 : out std_logic; - sample_filter_v2_out_66 : out std_logic; - sample_filter_v2_out_67 : out std_logic; - sample_filter_v2_out_68 : out std_logic; - sample_filter_v2_out_69 : out std_logic; - sample_filter_v2_out_90 : out std_logic; - sample_filter_v2_out_91 : out std_logic; - sample_filter_v2_out_92 : out std_logic; - sample_filter_v2_out_93 : out std_logic; - sample_filter_v2_out_94 : out std_logic; - sample_filter_v2_out_95 : out std_logic; - sample_filter_v2_out_96 : out std_logic; - sample_filter_v2_out_97 : out std_logic; - sample_filter_v2_out_98 : out std_logic; - sample_filter_v2_out_99 : out std_logic; - sample_filter_v2_out_100 : out std_logic; - sample_filter_v2_out_101 : out std_logic; - sample_filter_v2_out_102 : out std_logic; - sample_filter_v2_out_103 : out std_logic; - sample_filter_v2_out_104 : out std_logic; - sample_filter_v2_out_105 : out std_logic; - sample_filter_v2_out_108 : out std_logic; - sample_filter_v2_out_126 : out std_logic; - sample_filter_v2_out_109 : out std_logic; - sample_filter_v2_out_127 : out std_logic; - sample_filter_v2_out_110 : out std_logic; - sample_filter_v2_out_128 : out std_logic; - sample_filter_v2_out_111 : out std_logic; - sample_filter_v2_out_129 : out std_logic; - sample_filter_v2_out_112 : out std_logic; - sample_filter_v2_out_130 : out std_logic; - sample_filter_v2_out_113 : out std_logic; - sample_filter_v2_out_131 : out std_logic; - sample_filter_v2_out_114 : out std_logic; - sample_filter_v2_out_132 : out std_logic; - sample_filter_v2_out_115 : out std_logic; - sample_filter_v2_out_133 : out std_logic; - sample_filter_v2_out_116 : out std_logic; - sample_filter_v2_out_134 : out std_logic; - sample_filter_v2_out_117 : out std_logic; - sample_filter_v2_out_135 : out std_logic; - sample_filter_v2_out_118 : out std_logic; - sample_filter_v2_out_136 : out std_logic; - sample_filter_v2_out_119 : out std_logic; - sample_filter_v2_out_137 : out std_logic; - sample_filter_v2_out_120 : out std_logic; - sample_filter_v2_out_138 : out std_logic; - sample_filter_v2_out_121 : out std_logic; - sample_filter_v2_out_139 : out std_logic; - sample_filter_v2_out_122 : out std_logic; - sample_filter_v2_out_140 : out std_logic; - sample_filter_v2_out_123 : out std_logic; - sample_filter_v2_out_141 : out std_logic; - sample_4 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_5 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_3 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_2 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_6 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_1 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_7 : in std_logic_vector(15 downto 0) := (others => 'U'); - IIR_CEL_CTRLR_v2_VCC : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_GND : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_filter_v2_out_val : out std_logic; - sample_val_delay : in std_logic := 'U'; - sample_val_delay_5 : in std_logic := 'U'; - sample_val_delay_4 : in std_logic := 'U'; - sample_val_delay_3 : in std_logic := 'U'; - sample_val_delay_2 : in std_logic := 'U'; - sample_val_delay_1 : in std_logic := 'U'; - sample_val_delay_0 : in std_logic := 'U' - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component Downsampling_6_16_256 - port( sample_f1 : in std_logic_vector(111 downto 80) := (others => 'U'); - sample_f1_wdata_95 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - sample_f3_wdata : out std_logic_vector(95 downto 0); - sample_f1_val : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_f3_val : out std_logic; - sample_f1_val_0 : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component Downsampling_6_16_96 - port( sample_f0 : in std_logic_vector(111 downto 80) := (others => 'U'); - sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f2_wdata : out std_logic_vector(95 downto 0); - sample_f0_val : in std_logic := 'U'; - sample_f0_val_2 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_f2_val : out std_logic; - sample_f0_val_0 : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform - port( status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(3 downto 0); - status_full : out std_logic_vector(3 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - sample_f3_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - sample_f2_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - sample_f1_15 : in std_logic := 'U'; - sample_f1_47 : in std_logic := 'U'; - sample_f1_14 : in std_logic := 'U'; - sample_f1_46 : in std_logic := 'U'; - sample_f1_13 : in std_logic := 'U'; - sample_f1_45 : in std_logic := 'U'; - sample_f1_12 : in std_logic := 'U'; - sample_f1_44 : in std_logic := 'U'; - sample_f1_60 : in std_logic := 'U'; - sample_f1_59 : in std_logic := 'U'; - sample_f1_58 : in std_logic := 'U'; - sample_f1_57 : in std_logic := 'U'; - sample_f1_56 : in std_logic := 'U'; - sample_f1_55 : in std_logic := 'U'; - sample_f1_54 : in std_logic := 'U'; - sample_f1_53 : in std_logic := 'U'; - sample_f1_52 : in std_logic := 'U'; - sample_f1_51 : in std_logic := 'U'; - sample_f1_50 : in std_logic := 'U'; - sample_f1_49 : in std_logic := 'U'; - sample_f1_48 : in std_logic := 'U'; - sample_f1_4 : in std_logic := 'U'; - sample_f1_36 : in std_logic := 'U'; - sample_f1_3 : in std_logic := 'U'; - sample_f1_35 : in std_logic := 'U'; - sample_f1_2 : in std_logic := 'U'; - sample_f1_34 : in std_logic := 'U'; - sample_f1_1 : in std_logic := 'U'; - sample_f1_33 : in std_logic := 'U'; - sample_f1_0 : in std_logic := 'U'; - sample_f1_32 : in std_logic := 'U'; - sample_f1_63 : in std_logic := 'U'; - sample_f1_62 : in std_logic := 'U'; - sample_f1_61 : in std_logic := 'U'; - sample_f1_11 : in std_logic := 'U'; - sample_f1_43 : in std_logic := 'U'; - sample_f1_10 : in std_logic := 'U'; - sample_f1_42 : in std_logic := 'U'; - sample_f1_9 : in std_logic := 'U'; - sample_f1_41 : in std_logic := 'U'; - sample_f1_8 : in std_logic := 'U'; - sample_f1_40 : in std_logic := 'U'; - sample_f1_7 : in std_logic := 'U'; - sample_f1_39 : in std_logic := 'U'; - sample_f1_6 : in std_logic := 'U'; - sample_f1_38 : in std_logic := 'U'; - sample_f1_5 : in std_logic := 'U'; - sample_f1_37 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_95 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_0 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_37 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_95 : in std_logic := 'U'; - coarse_time : in std_logic_vector(0 to 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - coarse_time_i : in std_logic_vector(0 to 0) := (others => 'U'); - nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - IdlePhase : out std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - arb_1 : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - Lock_RNIU86D : out std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - m19_0_N_15_i_0_li : in std_logic := 'U'; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - m26_m1_e : out std_logic; - sample_f3_val : in std_logic := 'U'; - enable_f3 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - data_shaping_R0 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - rstn : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U' - ); - end component; - - component Downsampling_8_16_4 - port( sample_f0_0 : out std_logic; - sample_f0_1 : out std_logic; - sample_f0_2 : out std_logic; - sample_f0_3 : out std_logic; - sample_f0_4 : out std_logic; - sample_f0_5 : out std_logic; - sample_f0_6 : out std_logic; - sample_f0_7 : out std_logic; - sample_f0_8 : out std_logic; - sample_f0_9 : out std_logic; - sample_f0_10 : out std_logic; - sample_f0_11 : out std_logic; - sample_f0_12 : out std_logic; - sample_f0_13 : out std_logic; - sample_f0_14 : out std_logic; - sample_f0_15 : out std_logic; - sample_f0_32 : out std_logic; - sample_f0_33 : out std_logic; - sample_f0_34 : out std_logic; - sample_f0_35 : out std_logic; - sample_f0_36 : out std_logic; - sample_f0_37 : out std_logic; - sample_f0_38 : out std_logic; - sample_f0_39 : out std_logic; - sample_f0_40 : out std_logic; - sample_f0_41 : out std_logic; - sample_f0_42 : out std_logic; - sample_f0_43 : out std_logic; - sample_f0_44 : out std_logic; - sample_f0_45 : out std_logic; - sample_f0_46 : out std_logic; - sample_f0_47 : out std_logic; - sample_f0_48 : out std_logic; - sample_f0_49 : out std_logic; - sample_f0_50 : out std_logic; - sample_f0_51 : out std_logic; - sample_f0_52 : out std_logic; - sample_f0_53 : out std_logic; - sample_f0_54 : out std_logic; - sample_f0_55 : out std_logic; - sample_f0_56 : out std_logic; - sample_f0_57 : out std_logic; - sample_f0_58 : out std_logic; - sample_f0_59 : out std_logic; - sample_f0_60 : out std_logic; - sample_f0_61 : out std_logic; - sample_f0_62 : out std_logic; - sample_f0_63 : out std_logic; - sample_data_shaping_out_0 : in std_logic := 'U'; - sample_data_shaping_out_1 : in std_logic := 'U'; - sample_data_shaping_out_2 : in std_logic := 'U'; - sample_data_shaping_out_3 : in std_logic := 'U'; - sample_data_shaping_out_4 : in std_logic := 'U'; - sample_data_shaping_out_5 : in std_logic := 'U'; - sample_data_shaping_out_6 : in std_logic := 'U'; - sample_data_shaping_out_7 : in std_logic := 'U'; - sample_data_shaping_out_8 : in std_logic := 'U'; - sample_data_shaping_out_9 : in std_logic := 'U'; - sample_data_shaping_out_10 : in std_logic := 'U'; - sample_data_shaping_out_11 : in std_logic := 'U'; - sample_data_shaping_out_12 : in std_logic := 'U'; - sample_data_shaping_out_13 : in std_logic := 'U'; - sample_data_shaping_out_14 : in std_logic := 'U'; - sample_data_shaping_out_15 : in std_logic := 'U'; - sample_data_shaping_out_18 : in std_logic := 'U'; - sample_data_shaping_out_19 : in std_logic := 'U'; - sample_data_shaping_out_20 : in std_logic := 'U'; - sample_data_shaping_out_21 : in std_logic := 'U'; - sample_data_shaping_out_22 : in std_logic := 'U'; - sample_data_shaping_out_23 : in std_logic := 'U'; - sample_data_shaping_out_24 : in std_logic := 'U'; - sample_data_shaping_out_25 : in std_logic := 'U'; - sample_data_shaping_out_26 : in std_logic := 'U'; - sample_data_shaping_out_27 : in std_logic := 'U'; - sample_data_shaping_out_28 : in std_logic := 'U'; - sample_data_shaping_out_29 : in std_logic := 'U'; - sample_data_shaping_out_30 : in std_logic := 'U'; - sample_data_shaping_out_31 : in std_logic := 'U'; - sample_data_shaping_out_32 : in std_logic := 'U'; - sample_data_shaping_out_33 : in std_logic := 'U'; - sample_data_shaping_out_36 : in std_logic := 'U'; - sample_data_shaping_out_37 : in std_logic := 'U'; - sample_data_shaping_out_38 : in std_logic := 'U'; - sample_data_shaping_out_39 : in std_logic := 'U'; - sample_data_shaping_out_40 : in std_logic := 'U'; - sample_data_shaping_out_41 : in std_logic := 'U'; - sample_data_shaping_out_42 : in std_logic := 'U'; - sample_data_shaping_out_43 : in std_logic := 'U'; - sample_data_shaping_out_44 : in std_logic := 'U'; - sample_data_shaping_out_45 : in std_logic := 'U'; - sample_data_shaping_out_46 : in std_logic := 'U'; - sample_data_shaping_out_47 : in std_logic := 'U'; - sample_data_shaping_out_48 : in std_logic := 'U'; - sample_data_shaping_out_49 : in std_logic := 'U'; - sample_data_shaping_out_50 : in std_logic := 'U'; - sample_data_shaping_out_51 : in std_logic := 'U'; - sample_data_shaping_out_54 : in std_logic := 'U'; - sample_data_shaping_out_55 : in std_logic := 'U'; - sample_data_shaping_out_56 : in std_logic := 'U'; - sample_data_shaping_out_57 : in std_logic := 'U'; - sample_data_shaping_out_58 : in std_logic := 'U'; - sample_data_shaping_out_59 : in std_logic := 'U'; - sample_data_shaping_out_60 : in std_logic := 'U'; - sample_data_shaping_out_61 : in std_logic := 'U'; - sample_data_shaping_out_62 : in std_logic := 'U'; - sample_data_shaping_out_63 : in std_logic := 'U'; - sample_data_shaping_out_64 : in std_logic := 'U'; - sample_data_shaping_out_65 : in std_logic := 'U'; - sample_data_shaping_out_66 : in std_logic := 'U'; - sample_data_shaping_out_67 : in std_logic := 'U'; - sample_data_shaping_out_68 : in std_logic := 'U'; - sample_data_shaping_out_69 : in std_logic := 'U'; - sample_data_shaping_out_90 : in std_logic := 'U'; - sample_data_shaping_out_91 : in std_logic := 'U'; - sample_data_shaping_out_92 : in std_logic := 'U'; - sample_data_shaping_out_93 : in std_logic := 'U'; - sample_data_shaping_out_94 : in std_logic := 'U'; - sample_data_shaping_out_95 : in std_logic := 'U'; - sample_data_shaping_out_96 : in std_logic := 'U'; - sample_data_shaping_out_97 : in std_logic := 'U'; - sample_data_shaping_out_98 : in std_logic := 'U'; - sample_data_shaping_out_99 : in std_logic := 'U'; - sample_data_shaping_out_100 : in std_logic := 'U'; - sample_data_shaping_out_101 : in std_logic := 'U'; - sample_data_shaping_out_102 : in std_logic := 'U'; - sample_data_shaping_out_103 : in std_logic := 'U'; - sample_data_shaping_out_104 : in std_logic := 'U'; - sample_data_shaping_out_105 : in std_logic := 'U'; - sample_data_shaping_out_108 : in std_logic := 'U'; - sample_data_shaping_out_109 : in std_logic := 'U'; - sample_data_shaping_out_110 : in std_logic := 'U'; - sample_data_shaping_out_111 : in std_logic := 'U'; - sample_data_shaping_out_112 : in std_logic := 'U'; - sample_data_shaping_out_113 : in std_logic := 'U'; - sample_data_shaping_out_114 : in std_logic := 'U'; - sample_data_shaping_out_115 : in std_logic := 'U'; - sample_data_shaping_out_116 : in std_logic := 'U'; - sample_data_shaping_out_117 : in std_logic := 'U'; - sample_data_shaping_out_118 : in std_logic := 'U'; - sample_data_shaping_out_119 : in std_logic := 'U'; - sample_data_shaping_out_120 : in std_logic := 'U'; - sample_data_shaping_out_121 : in std_logic := 'U'; - sample_data_shaping_out_122 : in std_logic := 'U'; - sample_data_shaping_out_123 : in std_logic := 'U'; - sample_data_shaping_out_126 : in std_logic := 'U'; - sample_data_shaping_out_127 : in std_logic := 'U'; - sample_data_shaping_out_128 : in std_logic := 'U'; - sample_data_shaping_out_129 : in std_logic := 'U'; - sample_data_shaping_out_130 : in std_logic := 'U'; - sample_data_shaping_out_131 : in std_logic := 'U'; - sample_data_shaping_out_132 : in std_logic := 'U'; - sample_data_shaping_out_133 : in std_logic := 'U'; - sample_data_shaping_out_134 : in std_logic := 'U'; - sample_data_shaping_out_135 : in std_logic := 'U'; - sample_data_shaping_out_136 : in std_logic := 'U'; - sample_data_shaping_out_137 : in std_logic := 'U'; - sample_data_shaping_out_138 : in std_logic := 'U'; - sample_data_shaping_out_139 : in std_logic := 'U'; - sample_data_shaping_out_140 : in std_logic := 'U'; - sample_data_shaping_out_141 : in std_logic := 'U'; - sample_f0_wdata_95 : out std_logic; - sample_f0_wdata_94 : out std_logic; - sample_f0_wdata_93 : out std_logic; - sample_f0_wdata_92 : out std_logic; - sample_f0_wdata_91 : out std_logic; - sample_f0_wdata_90 : out std_logic; - sample_f0_wdata_89 : out std_logic; - sample_f0_wdata_88 : out std_logic; - sample_f0_wdata_87 : out std_logic; - sample_f0_wdata_86 : out std_logic; - sample_f0_wdata_85 : out std_logic; - sample_f0_wdata_84 : out std_logic; - sample_f0_wdata_83 : out std_logic; - sample_f0_wdata_82 : out std_logic; - sample_f0_wdata_81 : out std_logic; - sample_f0_wdata_80 : out std_logic; - sample_f0_wdata_79 : out std_logic; - sample_f0_wdata_78 : out std_logic; - sample_f0_wdata_77 : out std_logic; - sample_f0_wdata_76 : out std_logic; - sample_f0_wdata_75 : out std_logic; - sample_f0_wdata_74 : out std_logic; - sample_f0_wdata_73 : out std_logic; - sample_f0_wdata_72 : out std_logic; - sample_f0_wdata_71 : out std_logic; - sample_f0_wdata_70 : out std_logic; - sample_f0_wdata_69 : out std_logic; - sample_f0_wdata_68 : out std_logic; - sample_f0_wdata_67 : out std_logic; - sample_f0_wdata_66 : out std_logic; - sample_f0_wdata_65 : out std_logic; - sample_f0_wdata_64 : out std_logic; - sample_f0_wdata_63 : out std_logic; - sample_f0_wdata_62 : out std_logic; - sample_f0_wdata_61 : out std_logic; - sample_f0_wdata_60 : out std_logic; - sample_f0_wdata_59 : out std_logic; - sample_f0_wdata_58 : out std_logic; - sample_f0_wdata_57 : out std_logic; - sample_f0_wdata_56 : out std_logic; - sample_f0_wdata_55 : out std_logic; - sample_f0_wdata_54 : out std_logic; - sample_f0_wdata_53 : out std_logic; - sample_f0_wdata_52 : out std_logic; - sample_f0_wdata_51 : out std_logic; - sample_f0_wdata_50 : out std_logic; - sample_f0_wdata_49 : out std_logic; - sample_f0_wdata_48 : out std_logic; - sample_f0_wdata_15 : out std_logic; - sample_f0_wdata_14 : out std_logic; - sample_f0_wdata_13 : out std_logic; - sample_f0_wdata_12 : out std_logic; - sample_f0_wdata_11 : out std_logic; - sample_f0_wdata_10 : out std_logic; - sample_f0_wdata_9 : out std_logic; - sample_f0_wdata_8 : out std_logic; - sample_f0_wdata_7 : out std_logic; - sample_f0_wdata_6 : out std_logic; - sample_f0_wdata_5 : out std_logic; - sample_f0_wdata_4 : out std_logic; - sample_f0_wdata_3 : out std_logic; - sample_f0_wdata_2 : out std_logic; - sample_f0_wdata_1 : out std_logic; - sample_f0_wdata_0 : out std_logic; - sample_data_shaping_out_val : in std_logic := 'U'; - sample_f0_val : out std_logic; - sample_data_shaping_out_val_0 : in std_logic := 'U'; - sample_f0_val_0 : out std_logic; - sample_f0_val_1 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_f0_val_2 : out std_logic - ); - end component; - - component Downsampling_8_16_6 - port( sample_f0_0 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_37 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f1_0 : out std_logic; - sample_f1_1 : out std_logic; - sample_f1_2 : out std_logic; - sample_f1_3 : out std_logic; - sample_f1_4 : out std_logic; - sample_f1_5 : out std_logic; - sample_f1_6 : out std_logic; - sample_f1_7 : out std_logic; - sample_f1_8 : out std_logic; - sample_f1_9 : out std_logic; - sample_f1_10 : out std_logic; - sample_f1_11 : out std_logic; - sample_f1_12 : out std_logic; - sample_f1_13 : out std_logic; - sample_f1_14 : out std_logic; - sample_f1_15 : out std_logic; - sample_f1_32 : out std_logic; - sample_f1_33 : out std_logic; - sample_f1_34 : out std_logic; - sample_f1_35 : out std_logic; - sample_f1_36 : out std_logic; - sample_f1_37 : out std_logic; - sample_f1_38 : out std_logic; - sample_f1_39 : out std_logic; - sample_f1_40 : out std_logic; - sample_f1_41 : out std_logic; - sample_f1_42 : out std_logic; - sample_f1_43 : out std_logic; - sample_f1_44 : out std_logic; - sample_f1_45 : out std_logic; - sample_f1_46 : out std_logic; - sample_f1_47 : out std_logic; - sample_f1_48 : out std_logic; - sample_f1_49 : out std_logic; - sample_f1_50 : out std_logic; - sample_f1_51 : out std_logic; - sample_f1_52 : out std_logic; - sample_f1_53 : out std_logic; - sample_f1_54 : out std_logic; - sample_f1_55 : out std_logic; - sample_f1_56 : out std_logic; - sample_f1_57 : out std_logic; - sample_f1_58 : out std_logic; - sample_f1_59 : out std_logic; - sample_f1_60 : out std_logic; - sample_f1_61 : out std_logic; - sample_f1_62 : out std_logic; - sample_f1_63 : out std_logic; - sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f1_wdata_95 : out std_logic; - sample_f1_wdata_94 : out std_logic; - sample_f1_wdata_93 : out std_logic; - sample_f1_wdata_92 : out std_logic; - sample_f1_wdata_91 : out std_logic; - sample_f1_wdata_90 : out std_logic; - sample_f1_wdata_89 : out std_logic; - sample_f1_wdata_88 : out std_logic; - sample_f1_wdata_87 : out std_logic; - sample_f1_wdata_86 : out std_logic; - sample_f1_wdata_85 : out std_logic; - sample_f1_wdata_84 : out std_logic; - sample_f1_wdata_83 : out std_logic; - sample_f1_wdata_82 : out std_logic; - sample_f1_wdata_81 : out std_logic; - sample_f1_wdata_80 : out std_logic; - sample_f1_wdata_79 : out std_logic; - sample_f1_wdata_78 : out std_logic; - sample_f1_wdata_77 : out std_logic; - sample_f1_wdata_76 : out std_logic; - sample_f1_wdata_75 : out std_logic; - sample_f1_wdata_74 : out std_logic; - sample_f1_wdata_73 : out std_logic; - sample_f1_wdata_72 : out std_logic; - sample_f1_wdata_71 : out std_logic; - sample_f1_wdata_70 : out std_logic; - sample_f1_wdata_69 : out std_logic; - sample_f1_wdata_68 : out std_logic; - sample_f1_wdata_67 : out std_logic; - sample_f1_wdata_66 : out std_logic; - sample_f1_wdata_65 : out std_logic; - sample_f1_wdata_64 : out std_logic; - sample_f1_wdata_63 : out std_logic; - sample_f1_wdata_62 : out std_logic; - sample_f1_wdata_61 : out std_logic; - sample_f1_wdata_60 : out std_logic; - sample_f1_wdata_59 : out std_logic; - sample_f1_wdata_58 : out std_logic; - sample_f1_wdata_57 : out std_logic; - sample_f1_wdata_56 : out std_logic; - sample_f1_wdata_55 : out std_logic; - sample_f1_wdata_54 : out std_logic; - sample_f1_wdata_53 : out std_logic; - sample_f1_wdata_52 : out std_logic; - sample_f1_wdata_51 : out std_logic; - sample_f1_wdata_50 : out std_logic; - sample_f1_wdata_49 : out std_logic; - sample_f1_wdata_48 : out std_logic; - sample_f1_wdata_15 : out std_logic; - sample_f1_wdata_14 : out std_logic; - sample_f1_wdata_13 : out std_logic; - sample_f1_wdata_12 : out std_logic; - sample_f1_wdata_11 : out std_logic; - sample_f1_wdata_10 : out std_logic; - sample_f1_wdata_9 : out std_logic; - sample_f1_wdata_8 : out std_logic; - sample_f1_wdata_7 : out std_logic; - sample_f1_wdata_6 : out std_logic; - sample_f1_wdata_5 : out std_logic; - sample_f1_wdata_4 : out std_logic; - sample_f1_wdata_3 : out std_logic; - sample_f1_wdata_2 : out std_logic; - sample_f1_wdata_1 : out std_logic; - sample_f1_wdata_0 : out std_logic; - sample_f0_val_2 : in std_logic := 'U'; - sample_f0_val_1 : in std_logic := 'U'; - sample_f1_val : out std_logic; - sample_f0_val_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_f1_val_0 : out std_logic - ); - end component; - - component AD7688_drvr - port( sample_4 : out std_logic_vector(15 downto 0); - sample_5 : out std_logic_vector(15 downto 0); - sample_6 : out std_logic_vector(15 downto 0); - sample_7 : out std_logic_vector(15 downto 0); - sample_0 : out std_logic_vector(15 downto 0); - sample_1 : out std_logic_vector(15 downto 0); - sample_2 : out std_logic_vector(15 downto 0); - sdo_adc_c : in std_logic_vector(7 downto 0) := (others => 'U'); - sample_3 : out std_logic_vector(15 downto 0); - AD7688_drvr_VCC : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - cnv_ch1_c : out std_logic; - sample_val : out std_logic; - sck_ch1_c : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \sample_val_delay_5\, sample_val, - \sample_val_delay_4\, \sample_val_delay_3\, - \sample_val_delay_2\, \sample_val_delay_1\, - \sample_val_delay_0\, \sample_data_shaping_out_val_0\, - sample_filter_v2_out_val, SUB_16x16_medium_area_I57_Y_2, - N244, N229, SUB_16x16_medium_area_I57_Y_1, N254, N212, - SUB_16x16_medium_area_I57_Y_0, N206, - \sample_filter_v2_out[111]\, \sample_filter_v2_out[93]\, - SUB_16x16_medium_area_I57_Y_2_0, N244_0, N229_0, - SUB_16x16_medium_area_I57_Y_1_0, N212_0, N254_0, - SUB_16x16_medium_area_I57_Y_0_0, N206_0, - \sample_filter_v2_out[129]\, - SUB_16x16_medium_area_I57_un1_Y_0, N245, - SUB_16x16_medium_area_I57_un1_Y_0_0, N245_0, - SUB_16x16_medium_area_I56_Y_1, N274, N220, - SUB_16x16_medium_area_I56_Y_0, N190, - \sample_filter_v2_out[119]\, \sample_filter_v2_out[101]\, - SUB_16x16_medium_area_I56_Y_1_0, N274_0, N220_0, - SUB_16x16_medium_area_I56_Y_0_0, N190_0, - \sample_filter_v2_out[137]\, - SUB_16x16_medium_area_I56_un1_Y_0, N275, - SUB_16x16_medium_area_I56_un1_Y_0_0, N275_0, - SUB_16x16_medium_area_I49_Y_0, N198, - \sample_filter_v2_out[115]\, \sample_filter_v2_out[97]\, - SUB_16x16_medium_area_I49_Y_0_0, N198_0, - \sample_filter_v2_out[133]\, - SUB_16x16_medium_area_I53_Y_0, N182, - \sample_filter_v2_out[141]\, \sample_filter_v2_out[123]\, - SUB_16x16_medium_area_I53_Y_0_0, N182_0, - \sample_filter_v2_out[105]\, N264, N216, N240, N268, N278, - N264_0, N216_0, N240_0, N268_0, N278_0, - \sample_data_shaping_f2_f1_s[15]\, - \sample_filter_v2_out[110]\, \sample_filter_v2_out[92]\, - \sample_data_shaping_f1_f0_s[15]\, - \sample_filter_v2_out[128]\, I53_un1_Y, N225, N183, N181, - I53_un1_Y_0, N225_0, N183_0, N181_0, N194, - \sample_filter_v2_out[118]\, \sample_filter_v2_out[136]\, - \sample_filter_v2_out[116]\, \sample_filter_v2_out[134]\, - N202, \sample_filter_v2_out[114]\, - \sample_filter_v2_out[132]\, \sample_filter_v2_out[112]\, - \sample_filter_v2_out[130]\, N205, - \sample_filter_v2_out[131]\, \sample_filter_v2_out[113]\, - N255, N201, N197, \sample_filter_v2_out[117]\, - \sample_filter_v2_out[135]\, N265, N195, N258, N260, N270, - N282_i, N284_i, N286_i, SUB_16x16_medium_area_I89_un1_Y, - \sample_data_shaping_f1_f0_s[7]\, - \sample_data_shaping_f1_f0_s[8]\, - \sample_data_shaping_f1_f0_s[9]\, - \sample_data_shaping_f1_f0_s[10]\, - \sample_data_shaping_f1_f0_s[11]\, - \sample_data_shaping_f1_f0_s[12]\, - \sample_data_shaping_f1_f0_s[13]\, - \sample_data_shaping_f1_f0_s_i[14]\, N186, - \sample_filter_v2_out[122]\, \sample_filter_v2_out[140]\, - \sample_filter_v2_out[120]\, \sample_filter_v2_out[138]\, - N191, N189, \sample_filter_v2_out[121]\, - \sample_filter_v2_out[139]\, N187, N185, I85_un1_Y, - I90_un1_Y, SUB_16x16_medium_area_I91_un1_Y, - \sample_data_shaping_f1_f0_s[3]\, - \sample_data_shaping_f1_f0_s[4]\, - \sample_data_shaping_f1_f0_s[5]\, - \sample_data_shaping_f1_f0_s[6]\, N194_0, - \sample_filter_v2_out[100]\, \sample_filter_v2_out[98]\, - N202_0, \sample_filter_v2_out[96]\, - \sample_filter_v2_out[94]\, N205_0, - \sample_filter_v2_out[95]\, N255_0, N201_0, N197_0, - \sample_filter_v2_out[99]\, N265_0, N195_0, N258_0, - N260_0, N270_0, N282_i_0, N284_i_0, N286_i_0, - SUB_16x16_medium_area_I89_un1_Y_0, - \sample_data_shaping_f2_f1_s[7]\, - \sample_data_shaping_f2_f1_s[8]\, - \sample_data_shaping_f2_f1_s[9]\, - \sample_data_shaping_f2_f1_s[10]\, - \sample_data_shaping_f2_f1_s[11]\, - \sample_data_shaping_f2_f1_s[12]\, - \sample_data_shaping_f2_f1_s[13]\, - \sample_data_shaping_f2_f1_s[14]\, N186_0, - \sample_filter_v2_out[104]\, \sample_filter_v2_out[102]\, - N191_0, N189_0, \sample_filter_v2_out[103]\, N187_0, - N185_0, I85_un1_Y_0, I90_un1_Y_0, - SUB_16x16_medium_area_I91_un1_Y_0, - \sample_data_shaping_f2_f1_s[3]\, - \sample_data_shaping_f2_f1_s[4]\, - \sample_data_shaping_f2_f1_s[5]\, - \sample_data_shaping_f2_f1_s[6]\, - \sample_data_shaping_out_377[92]\, - \sample_data_shaping_out_353[93]\, - \sample_data_shaping_out_329[94]\, - \sample_data_shaping_out_305[95]\, - \sample_data_shaping_out_281[96]\, - \sample_data_shaping_out_257[97]\, - \sample_data_shaping_out_233[98]\, - \sample_data_shaping_out_209[99]\, - \sample_data_shaping_out_185[100]\, - \sample_data_shaping_out_161[101]\, - \sample_data_shaping_out_137[102]\, - \sample_data_shaping_out_113[103]\, - \sample_data_shaping_out_89[104]\, - \sample_data_shaping_out_373[110]\, - \sample_data_shaping_out_349[111]\, - \sample_data_shaping_out_325[112]\, - \sample_data_shaping_out_301[113]\, - \sample_data_shaping_out_277[114]\, - \sample_data_shaping_out_253[115]\, - \sample_data_shaping_out_229[116]\, - \sample_data_shaping_out_205[117]\, - \sample_data_shaping_out_181[118]\, - \sample_data_shaping_out_157[119]\, - \sample_data_shaping_out_133[120]\, - \sample_data_shaping_out_109[121]\, - \sample_data_shaping_out_85[122]\, - \sample_filter_v2_out[143]\, \sample_filter_v2_out[125]\, - \sample_filter_v2_out[107]\, - \sample_data_shaping_out_17[107]\, - \sample_data_shaping_out_13[125]\, - \sample_data_shaping_out_37[124]\, - \sample_filter_v2_out[124]\, - \sample_data_shaping_f1_f0_s[1]\, - \sample_data_shaping_out_61[123]\, - \sample_data_shaping_f1_f0_s[2]\, - \sample_data_shaping_out_41[106]\, - \sample_filter_v2_out[106]\, - \sample_data_shaping_f2_f1_s[1]\, - \sample_data_shaping_out_65[105]\, - \sample_data_shaping_f2_f1_s[2]\, N294_i, I92_un1_Y, - \sample_filter_v2_out[142]\, \sample_val_delay\, - \sample_data_shaping_out_val\, - \sample_data_shaping_out[20]\, \sample_filter_v2_out[20]\, - \sample_data_shaping_out[21]\, \sample_filter_v2_out[21]\, - \sample_data_shaping_out[22]\, \sample_filter_v2_out[22]\, - \sample_data_shaping_out[23]\, \sample_filter_v2_out[23]\, - \sample_data_shaping_out[24]\, \sample_filter_v2_out[24]\, - \sample_data_shaping_out[25]\, \sample_filter_v2_out[25]\, - \sample_data_shaping_out[26]\, \sample_filter_v2_out[26]\, - \sample_data_shaping_out[27]\, \sample_filter_v2_out[27]\, - \sample_data_shaping_out[28]\, \sample_filter_v2_out[28]\, - \sample_data_shaping_out[29]\, \sample_filter_v2_out[29]\, - \sample_data_shaping_out[30]\, \sample_filter_v2_out[30]\, - \sample_data_shaping_out[31]\, \sample_filter_v2_out[31]\, - \sample_data_shaping_out[32]\, \sample_filter_v2_out[32]\, - \sample_data_shaping_out[33]\, \sample_filter_v2_out[33]\, - \sample_data_shaping_out[34]\, \sample_filter_v2_out[34]\, - \sample_data_shaping_out[35]\, \sample_filter_v2_out[35]\, - \sample_data_shaping_out[38]\, \sample_filter_v2_out[38]\, - \sample_data_shaping_out[39]\, \sample_filter_v2_out[39]\, - \sample_data_shaping_out[40]\, \sample_filter_v2_out[40]\, - \sample_data_shaping_out[41]\, \sample_filter_v2_out[41]\, - \sample_data_shaping_out[42]\, \sample_filter_v2_out[42]\, - \sample_data_shaping_out[43]\, \sample_filter_v2_out[43]\, - \sample_data_shaping_out[44]\, \sample_filter_v2_out[44]\, - \sample_data_shaping_out[45]\, \sample_filter_v2_out[45]\, - \sample_data_shaping_out[46]\, \sample_filter_v2_out[46]\, - \sample_data_shaping_out[47]\, \sample_filter_v2_out[47]\, - \sample_data_shaping_out[48]\, \sample_filter_v2_out[48]\, - \sample_data_shaping_out[49]\, \sample_filter_v2_out[49]\, - \sample_data_shaping_out[50]\, \sample_filter_v2_out[50]\, - \sample_data_shaping_out[51]\, \sample_filter_v2_out[51]\, - \sample_data_shaping_out[52]\, \sample_filter_v2_out[52]\, - \sample_data_shaping_out[53]\, \sample_filter_v2_out[53]\, - \sample_data_shaping_out[56]\, \sample_filter_v2_out[56]\, - \sample_data_shaping_out[57]\, \sample_filter_v2_out[57]\, - \sample_data_shaping_out[58]\, \sample_filter_v2_out[58]\, - \sample_data_shaping_out[59]\, \sample_filter_v2_out[59]\, - \sample_data_shaping_out[60]\, \sample_filter_v2_out[60]\, - \sample_data_shaping_out[61]\, \sample_filter_v2_out[61]\, - \sample_data_shaping_out[62]\, \sample_filter_v2_out[62]\, - \sample_data_shaping_out[63]\, \sample_filter_v2_out[63]\, - \sample_data_shaping_out[64]\, \sample_filter_v2_out[64]\, - \sample_data_shaping_out[65]\, \sample_filter_v2_out[65]\, - \sample_data_shaping_out[66]\, \sample_filter_v2_out[66]\, - \sample_data_shaping_out[67]\, \sample_filter_v2_out[67]\, - \sample_data_shaping_out[68]\, \sample_filter_v2_out[68]\, - \sample_data_shaping_out[69]\, \sample_filter_v2_out[69]\, - \sample_data_shaping_out[70]\, \sample_filter_v2_out[70]\, - \sample_data_shaping_out[71]\, \sample_filter_v2_out[71]\, - \sample_data_shaping_out[128]\, - \sample_data_shaping_out[129]\, - \sample_data_shaping_out[130]\, - \sample_data_shaping_out[131]\, - \sample_data_shaping_out[132]\, - \sample_data_shaping_out[133]\, - \sample_data_shaping_out[134]\, - \sample_data_shaping_out[135]\, - \sample_data_shaping_out[136]\, - \sample_data_shaping_out[137]\, - \sample_data_shaping_out[138]\, - \sample_data_shaping_out[139]\, - \sample_data_shaping_out[140]\, - \sample_data_shaping_out[141]\, - \sample_data_shaping_out[142]\, - \sample_data_shaping_out[143]\, - \sample_data_shaping_out[2]\, \sample_filter_v2_out[2]\, - \sample_data_shaping_out[3]\, \sample_filter_v2_out[3]\, - \sample_data_shaping_out[4]\, \sample_filter_v2_out[4]\, - \sample_data_shaping_out[5]\, \sample_filter_v2_out[5]\, - \sample_data_shaping_out[6]\, \sample_filter_v2_out[6]\, - \sample_data_shaping_out[7]\, \sample_filter_v2_out[7]\, - \sample_data_shaping_out[8]\, \sample_filter_v2_out[8]\, - \sample_data_shaping_out[9]\, \sample_filter_v2_out[9]\, - \sample_data_shaping_out[10]\, \sample_filter_v2_out[10]\, - \sample_data_shaping_out[11]\, \sample_filter_v2_out[11]\, - \sample_data_shaping_out[12]\, \sample_filter_v2_out[12]\, - \sample_data_shaping_out[13]\, \sample_filter_v2_out[13]\, - \sample_data_shaping_out[14]\, \sample_filter_v2_out[14]\, - \sample_data_shaping_out[15]\, \sample_filter_v2_out[15]\, - \sample_data_shaping_out[16]\, \sample_filter_v2_out[16]\, - \sample_data_shaping_out[17]\, \sample_filter_v2_out[17]\, - \sample_data_shaping_out[92]\, - \sample_data_shaping_out[93]\, - \sample_data_shaping_out[94]\, - \sample_data_shaping_out[95]\, - \sample_data_shaping_out[96]\, - \sample_data_shaping_out[97]\, - \sample_data_shaping_out[98]\, - \sample_data_shaping_out[99]\, - \sample_data_shaping_out[100]\, - \sample_data_shaping_out[101]\, - \sample_data_shaping_out[102]\, - \sample_data_shaping_out[103]\, - \sample_data_shaping_out[104]\, - \sample_data_shaping_out[105]\, - \sample_data_shaping_out[106]\, - \sample_data_shaping_out[107]\, - \sample_data_shaping_out[110]\, - \sample_data_shaping_out[111]\, - \sample_data_shaping_out[112]\, - \sample_data_shaping_out[113]\, - \sample_data_shaping_out[114]\, - \sample_data_shaping_out[115]\, - \sample_data_shaping_out[116]\, - \sample_data_shaping_out[117]\, - \sample_data_shaping_out[118]\, - \sample_data_shaping_out[119]\, - \sample_data_shaping_out[120]\, - \sample_data_shaping_out[121]\, - \sample_data_shaping_out[122]\, - \sample_data_shaping_out[123]\, - \sample_data_shaping_out[124]\, - \sample_data_shaping_out[125]\, \sample_4[0]\, - \sample_4[1]\, \sample_4[2]\, \sample_4[3]\, - \sample_4[4]\, \sample_4[5]\, \sample_4[6]\, - \sample_4[7]\, \sample_4[8]\, \sample_4[9]\, - \sample_4[10]\, \sample_4[11]\, \sample_4[12]\, - \sample_4[13]\, \sample_4[14]\, \sample_4[15]\, - \sample_5[0]\, \sample_5[1]\, \sample_5[2]\, - \sample_5[3]\, \sample_5[4]\, \sample_5[5]\, - \sample_5[6]\, \sample_5[7]\, \sample_5[8]\, - \sample_5[9]\, \sample_5[10]\, \sample_5[11]\, - \sample_5[12]\, \sample_5[13]\, \sample_5[14]\, - \sample_5[15]\, \sample_6[0]\, \sample_6[1]\, - \sample_6[2]\, \sample_6[3]\, \sample_6[4]\, - \sample_6[5]\, \sample_6[6]\, \sample_6[7]\, - \sample_6[8]\, \sample_6[9]\, \sample_6[10]\, - \sample_6[11]\, \sample_6[12]\, \sample_6[13]\, - \sample_6[14]\, \sample_6[15]\, \sample_7[0]\, - \sample_7[1]\, \sample_7[2]\, \sample_7[3]\, - \sample_7[4]\, \sample_7[5]\, \sample_7[6]\, - \sample_7[7]\, \sample_7[8]\, \sample_7[9]\, - \sample_7[10]\, \sample_7[11]\, \sample_7[12]\, - \sample_7[13]\, \sample_7[14]\, \sample_7[15]\, - \sample_0[0]\, \sample_0[1]\, \sample_0[2]\, - \sample_0[3]\, \sample_0[4]\, \sample_0[5]\, - \sample_0[6]\, \sample_0[7]\, \sample_0[8]\, - \sample_0[9]\, \sample_0[10]\, \sample_0[11]\, - \sample_0[12]\, \sample_0[13]\, \sample_0[14]\, - \sample_0[15]\, \sample_1[0]\, \sample_1[1]\, - \sample_1[2]\, \sample_1[3]\, \sample_1[4]\, - \sample_1[5]\, \sample_1[6]\, \sample_1[7]\, - \sample_1[8]\, \sample_1[9]\, \sample_1[10]\, - \sample_1[11]\, \sample_1[12]\, \sample_1[13]\, - \sample_1[14]\, \sample_1[15]\, \sample_2[0]\, - \sample_2[1]\, \sample_2[2]\, \sample_2[3]\, - \sample_2[4]\, \sample_2[5]\, \sample_2[6]\, - \sample_2[7]\, \sample_2[8]\, \sample_2[9]\, - \sample_2[10]\, \sample_2[11]\, \sample_2[12]\, - \sample_2[13]\, \sample_2[14]\, \sample_2[15]\, - \sample_3[0]\, \sample_3[1]\, \sample_3[2]\, - \sample_3[3]\, \sample_3[4]\, \sample_3[5]\, - \sample_3[6]\, \sample_3[7]\, \sample_3[8]\, - \sample_3[9]\, \sample_3[10]\, \sample_3[11]\, - \sample_3[12]\, \sample_3[13]\, \sample_3[14]\, - \sample_3[15]\, \sample_f0[48]\, \sample_f0[49]\, - \sample_f0[50]\, \sample_f0[51]\, \sample_f0[52]\, - \sample_f0[53]\, \sample_f0[54]\, \sample_f0[55]\, - \sample_f0[56]\, \sample_f0[57]\, \sample_f0[58]\, - \sample_f0[59]\, \sample_f0[60]\, \sample_f0[61]\, - \sample_f0[62]\, \sample_f0[63]\, \sample_f0[80]\, - \sample_f0[81]\, \sample_f0[82]\, \sample_f0[83]\, - \sample_f0[84]\, \sample_f0[85]\, \sample_f0[86]\, - \sample_f0[87]\, \sample_f0[88]\, \sample_f0[89]\, - \sample_f0[90]\, \sample_f0[91]\, \sample_f0[92]\, - \sample_f0[93]\, \sample_f0[94]\, \sample_f0[95]\, - \sample_f0[96]\, \sample_f0[97]\, \sample_f0[98]\, - \sample_f0[99]\, \sample_f0[100]\, \sample_f0[101]\, - \sample_f0[102]\, \sample_f0[103]\, \sample_f0[104]\, - \sample_f0[105]\, \sample_f0[106]\, \sample_f0[107]\, - \sample_f0[108]\, \sample_f0[109]\, \sample_f0[110]\, - \sample_f0[111]\, \sample_f0_wdata[95]\, - \sample_f0_wdata[94]\, \sample_f0_wdata[93]\, - \sample_f0_wdata[92]\, \sample_f0_wdata[91]\, - \sample_f0_wdata[90]\, \sample_f0_wdata[89]\, - \sample_f0_wdata[88]\, \sample_f0_wdata[87]\, - \sample_f0_wdata[86]\, \sample_f0_wdata[85]\, - \sample_f0_wdata[84]\, \sample_f0_wdata[83]\, - \sample_f0_wdata[82]\, \sample_f0_wdata[81]\, - \sample_f0_wdata[80]\, \sample_f0_wdata[79]\, - \sample_f0_wdata[78]\, \sample_f0_wdata[77]\, - \sample_f0_wdata[76]\, \sample_f0_wdata[75]\, - \sample_f0_wdata[74]\, \sample_f0_wdata[73]\, - \sample_f0_wdata[72]\, \sample_f0_wdata[71]\, - \sample_f0_wdata[70]\, \sample_f0_wdata[69]\, - \sample_f0_wdata[68]\, \sample_f0_wdata[67]\, - \sample_f0_wdata[66]\, \sample_f0_wdata[65]\, - \sample_f0_wdata[64]\, \sample_f0_wdata[63]\, - \sample_f0_wdata[62]\, \sample_f0_wdata[61]\, - \sample_f0_wdata[60]\, \sample_f0_wdata[59]\, - \sample_f0_wdata[58]\, \sample_f0_wdata[57]\, - \sample_f0_wdata[56]\, \sample_f0_wdata[55]\, - \sample_f0_wdata[54]\, \sample_f0_wdata[53]\, - \sample_f0_wdata[52]\, \sample_f0_wdata[51]\, - \sample_f0_wdata[50]\, \sample_f0_wdata[49]\, - \sample_f0_wdata[48]\, \sample_f0_wdata[15]\, - \sample_f0_wdata[14]\, \sample_f0_wdata[13]\, - \sample_f0_wdata[12]\, \sample_f0_wdata[11]\, - \sample_f0_wdata[10]\, \sample_f0_wdata[9]\, - \sample_f0_wdata[8]\, \sample_f0_wdata[7]\, - \sample_f0_wdata[6]\, \sample_f0_wdata[5]\, - \sample_f0_wdata[4]\, \sample_f0_wdata[3]\, - \sample_f0_wdata[2]\, \sample_f0_wdata[1]\, - \sample_f0_wdata[0]\, sample_f0_val, sample_f0_val_0, - sample_f0_val_1, sample_f0_val_2, \sample_f1[48]\, - \sample_f1[49]\, \sample_f1[50]\, \sample_f1[51]\, - \sample_f1[52]\, \sample_f1[53]\, \sample_f1[54]\, - \sample_f1[55]\, \sample_f1[56]\, \sample_f1[57]\, - \sample_f1[58]\, \sample_f1[59]\, \sample_f1[60]\, - \sample_f1[61]\, \sample_f1[62]\, \sample_f1[63]\, - \sample_f1[80]\, \sample_f1[81]\, \sample_f1[82]\, - \sample_f1[83]\, \sample_f1[84]\, \sample_f1[85]\, - \sample_f1[86]\, \sample_f1[87]\, \sample_f1[88]\, - \sample_f1[89]\, \sample_f1[90]\, \sample_f1[91]\, - \sample_f1[92]\, \sample_f1[93]\, \sample_f1[94]\, - \sample_f1[95]\, \sample_f1[96]\, \sample_f1[97]\, - \sample_f1[98]\, \sample_f1[99]\, \sample_f1[100]\, - \sample_f1[101]\, \sample_f1[102]\, \sample_f1[103]\, - \sample_f1[104]\, \sample_f1[105]\, \sample_f1[106]\, - \sample_f1[107]\, \sample_f1[108]\, \sample_f1[109]\, - \sample_f1[110]\, \sample_f1[111]\, \sample_f1_wdata[95]\, - \sample_f1_wdata[94]\, \sample_f1_wdata[93]\, - \sample_f1_wdata[92]\, \sample_f1_wdata[91]\, - \sample_f1_wdata[90]\, \sample_f1_wdata[89]\, - \sample_f1_wdata[88]\, \sample_f1_wdata[87]\, - \sample_f1_wdata[86]\, \sample_f1_wdata[85]\, - \sample_f1_wdata[84]\, \sample_f1_wdata[83]\, - \sample_f1_wdata[82]\, \sample_f1_wdata[81]\, - \sample_f1_wdata[80]\, \sample_f1_wdata[79]\, - \sample_f1_wdata[78]\, \sample_f1_wdata[77]\, - \sample_f1_wdata[76]\, \sample_f1_wdata[75]\, - \sample_f1_wdata[74]\, \sample_f1_wdata[73]\, - \sample_f1_wdata[72]\, \sample_f1_wdata[71]\, - \sample_f1_wdata[70]\, \sample_f1_wdata[69]\, - \sample_f1_wdata[68]\, \sample_f1_wdata[67]\, - \sample_f1_wdata[66]\, \sample_f1_wdata[65]\, - \sample_f1_wdata[64]\, \sample_f1_wdata[63]\, - \sample_f1_wdata[62]\, \sample_f1_wdata[61]\, - \sample_f1_wdata[60]\, \sample_f1_wdata[59]\, - \sample_f1_wdata[58]\, \sample_f1_wdata[57]\, - \sample_f1_wdata[56]\, \sample_f1_wdata[55]\, - \sample_f1_wdata[54]\, \sample_f1_wdata[53]\, - \sample_f1_wdata[52]\, \sample_f1_wdata[51]\, - \sample_f1_wdata[50]\, \sample_f1_wdata[49]\, - \sample_f1_wdata[48]\, \sample_f1_wdata[15]\, - \sample_f1_wdata[14]\, \sample_f1_wdata[13]\, - \sample_f1_wdata[12]\, \sample_f1_wdata[11]\, - \sample_f1_wdata[10]\, \sample_f1_wdata[9]\, - \sample_f1_wdata[8]\, \sample_f1_wdata[7]\, - \sample_f1_wdata[6]\, \sample_f1_wdata[5]\, - \sample_f1_wdata[4]\, \sample_f1_wdata[3]\, - \sample_f1_wdata[2]\, \sample_f1_wdata[1]\, - \sample_f1_wdata[0]\, sample_f1_val, sample_f1_val_0, - \sample_f2_wdata[0]\, \sample_f2_wdata[1]\, - \sample_f2_wdata[2]\, \sample_f2_wdata[3]\, - \sample_f2_wdata[4]\, \sample_f2_wdata[5]\, - \sample_f2_wdata[6]\, \sample_f2_wdata[7]\, - \sample_f2_wdata[8]\, \sample_f2_wdata[9]\, - \sample_f2_wdata[10]\, \sample_f2_wdata[11]\, - \sample_f2_wdata[12]\, \sample_f2_wdata[13]\, - \sample_f2_wdata[14]\, \sample_f2_wdata[15]\, - \sample_f2_wdata[16]\, \sample_f2_wdata[17]\, - \sample_f2_wdata[18]\, \sample_f2_wdata[19]\, - \sample_f2_wdata[20]\, \sample_f2_wdata[21]\, - \sample_f2_wdata[22]\, \sample_f2_wdata[23]\, - \sample_f2_wdata[24]\, \sample_f2_wdata[25]\, - \sample_f2_wdata[26]\, \sample_f2_wdata[27]\, - \sample_f2_wdata[28]\, \sample_f2_wdata[29]\, - \sample_f2_wdata[30]\, \sample_f2_wdata[31]\, - \sample_f2_wdata[32]\, \sample_f2_wdata[33]\, - \sample_f2_wdata[34]\, \sample_f2_wdata[35]\, - \sample_f2_wdata[36]\, \sample_f2_wdata[37]\, - \sample_f2_wdata[38]\, \sample_f2_wdata[39]\, - \sample_f2_wdata[40]\, \sample_f2_wdata[41]\, - \sample_f2_wdata[42]\, \sample_f2_wdata[43]\, - \sample_f2_wdata[44]\, \sample_f2_wdata[45]\, - \sample_f2_wdata[46]\, \sample_f2_wdata[47]\, - \sample_f2_wdata[48]\, \sample_f2_wdata[49]\, - \sample_f2_wdata[50]\, \sample_f2_wdata[51]\, - \sample_f2_wdata[52]\, \sample_f2_wdata[53]\, - \sample_f2_wdata[54]\, \sample_f2_wdata[55]\, - \sample_f2_wdata[56]\, \sample_f2_wdata[57]\, - \sample_f2_wdata[58]\, \sample_f2_wdata[59]\, - \sample_f2_wdata[60]\, \sample_f2_wdata[61]\, - \sample_f2_wdata[62]\, \sample_f2_wdata[63]\, - \sample_f2_wdata[64]\, \sample_f2_wdata[65]\, - \sample_f2_wdata[66]\, \sample_f2_wdata[67]\, - \sample_f2_wdata[68]\, \sample_f2_wdata[69]\, - \sample_f2_wdata[70]\, \sample_f2_wdata[71]\, - \sample_f2_wdata[72]\, \sample_f2_wdata[73]\, - \sample_f2_wdata[74]\, \sample_f2_wdata[75]\, - \sample_f2_wdata[76]\, \sample_f2_wdata[77]\, - \sample_f2_wdata[78]\, \sample_f2_wdata[79]\, - \sample_f2_wdata[80]\, \sample_f2_wdata[81]\, - \sample_f2_wdata[82]\, \sample_f2_wdata[83]\, - \sample_f2_wdata[84]\, \sample_f2_wdata[85]\, - \sample_f2_wdata[86]\, \sample_f2_wdata[87]\, - \sample_f2_wdata[88]\, \sample_f2_wdata[89]\, - \sample_f2_wdata[90]\, \sample_f2_wdata[91]\, - \sample_f2_wdata[92]\, \sample_f2_wdata[93]\, - \sample_f2_wdata[94]\, \sample_f2_wdata[95]\, - sample_f2_val, \sample_f3_wdata[0]\, \sample_f3_wdata[1]\, - \sample_f3_wdata[2]\, \sample_f3_wdata[3]\, - \sample_f3_wdata[4]\, \sample_f3_wdata[5]\, - \sample_f3_wdata[6]\, \sample_f3_wdata[7]\, - \sample_f3_wdata[8]\, \sample_f3_wdata[9]\, - \sample_f3_wdata[10]\, \sample_f3_wdata[11]\, - \sample_f3_wdata[12]\, \sample_f3_wdata[13]\, - \sample_f3_wdata[14]\, \sample_f3_wdata[15]\, - \sample_f3_wdata[16]\, \sample_f3_wdata[17]\, - \sample_f3_wdata[18]\, \sample_f3_wdata[19]\, - \sample_f3_wdata[20]\, \sample_f3_wdata[21]\, - \sample_f3_wdata[22]\, \sample_f3_wdata[23]\, - \sample_f3_wdata[24]\, \sample_f3_wdata[25]\, - \sample_f3_wdata[26]\, \sample_f3_wdata[27]\, - \sample_f3_wdata[28]\, \sample_f3_wdata[29]\, - \sample_f3_wdata[30]\, \sample_f3_wdata[31]\, - \sample_f3_wdata[32]\, \sample_f3_wdata[33]\, - \sample_f3_wdata[34]\, \sample_f3_wdata[35]\, - \sample_f3_wdata[36]\, \sample_f3_wdata[37]\, - \sample_f3_wdata[38]\, \sample_f3_wdata[39]\, - \sample_f3_wdata[40]\, \sample_f3_wdata[41]\, - \sample_f3_wdata[42]\, \sample_f3_wdata[43]\, - \sample_f3_wdata[44]\, \sample_f3_wdata[45]\, - \sample_f3_wdata[46]\, \sample_f3_wdata[47]\, - \sample_f3_wdata[48]\, \sample_f3_wdata[49]\, - \sample_f3_wdata[50]\, \sample_f3_wdata[51]\, - \sample_f3_wdata[52]\, \sample_f3_wdata[53]\, - \sample_f3_wdata[54]\, \sample_f3_wdata[55]\, - \sample_f3_wdata[56]\, \sample_f3_wdata[57]\, - \sample_f3_wdata[58]\, \sample_f3_wdata[59]\, - \sample_f3_wdata[60]\, \sample_f3_wdata[61]\, - \sample_f3_wdata[62]\, \sample_f3_wdata[63]\, - \sample_f3_wdata[64]\, \sample_f3_wdata[65]\, - \sample_f3_wdata[66]\, \sample_f3_wdata[67]\, - \sample_f3_wdata[68]\, \sample_f3_wdata[69]\, - \sample_f3_wdata[70]\, \sample_f3_wdata[71]\, - \sample_f3_wdata[72]\, \sample_f3_wdata[73]\, - \sample_f3_wdata[74]\, \sample_f3_wdata[75]\, - \sample_f3_wdata[76]\, \sample_f3_wdata[77]\, - \sample_f3_wdata[78]\, \sample_f3_wdata[79]\, - \sample_f3_wdata[80]\, \sample_f3_wdata[81]\, - \sample_f3_wdata[82]\, \sample_f3_wdata[83]\, - \sample_f3_wdata[84]\, \sample_f3_wdata[85]\, - \sample_f3_wdata[86]\, \sample_f3_wdata[87]\, - \sample_f3_wdata[88]\, \sample_f3_wdata[89]\, - \sample_f3_wdata[90]\, \sample_f3_wdata[91]\, - \sample_f3_wdata[92]\, \sample_f3_wdata[93]\, - \sample_f3_wdata[94]\, \sample_f3_wdata[95]\, - sample_f3_val, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : IIR_CEL_CTRLR_v2 - Use entity work.IIR_CEL_CTRLR_v2(DEF_ARCH); - for all : Downsampling_6_16_256 - Use entity work.Downsampling_6_16_256(DEF_ARCH); - for all : Downsampling_6_16_96 - Use entity work.Downsampling_6_16_96(DEF_ARCH); - for all : lpp_waveform - Use entity work.lpp_waveform(DEF_ARCH); - for all : Downsampling_8_16_4 - Use entity work.Downsampling_8_16_4(DEF_ARCH); - for all : Downsampling_8_16_6 - Use entity work.Downsampling_8_16_6(DEF_ARCH); - for all : AD7688_drvr - Use entity work.AD7688_drvr(DEF_ARCH); -begin - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I78_Y : - AO1 - port map(A => N268_0, B => N265_0, C => N264_0, Y => N270_0); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I91_un1_Y : - NOR2B - port map(A => N278_0, B => N185_0, Y => - SUB_16x16_medium_area_I91_un1_Y_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I27_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[96]\, B => - \sample_filter_v2_out[114]\, Y => N202_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[29]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[29]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[29]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[97]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_257[97]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[97]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out_RNO[120]\ : - MX2 - port map(A => \sample_filter_v2_out[120]\, B => - \sample_data_shaping_f1_f0_s[5]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_133[120]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[138]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[138]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[138]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I86_Y : - AO18 - port map(A => N260, B => \sample_filter_v2_out[130]\, C => - \sample_filter_v2_out[112]\, Y => N282_i); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[117]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_205[117]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[117]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[23]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[23]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[23]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out_RNO[103]\ : - MX2 - port map(A => \sample_filter_v2_out[103]\, B => - \sample_data_shaping_f2_f1_s[4]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_113[103]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I106_Y_0 : - XOR2 - port map(A => N260_0, B => N205_0, Y => - \sample_data_shaping_f2_f1_s[13]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I100_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, C => N268_0, Y => - \sample_data_shaping_f2_f1_s[7]\); - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - port map(sample_filter_v2_out_0 => - \sample_filter_v2_out[2]\, sample_filter_v2_out_1 => - \sample_filter_v2_out[3]\, sample_filter_v2_out_2 => - \sample_filter_v2_out[4]\, sample_filter_v2_out_3 => - \sample_filter_v2_out[5]\, sample_filter_v2_out_4 => - \sample_filter_v2_out[6]\, sample_filter_v2_out_5 => - \sample_filter_v2_out[7]\, sample_filter_v2_out_6 => - \sample_filter_v2_out[8]\, sample_filter_v2_out_7 => - \sample_filter_v2_out[9]\, sample_filter_v2_out_8 => - \sample_filter_v2_out[10]\, sample_filter_v2_out_9 => - \sample_filter_v2_out[11]\, sample_filter_v2_out_10 => - \sample_filter_v2_out[12]\, sample_filter_v2_out_11 => - \sample_filter_v2_out[13]\, sample_filter_v2_out_12 => - \sample_filter_v2_out[14]\, sample_filter_v2_out_13 => - \sample_filter_v2_out[15]\, sample_filter_v2_out_14 => - \sample_filter_v2_out[16]\, sample_filter_v2_out_15 => - \sample_filter_v2_out[17]\, sample_filter_v2_out_18 => - \sample_filter_v2_out[20]\, sample_filter_v2_out_19 => - \sample_filter_v2_out[21]\, sample_filter_v2_out_20 => - \sample_filter_v2_out[22]\, sample_filter_v2_out_21 => - \sample_filter_v2_out[23]\, sample_filter_v2_out_22 => - \sample_filter_v2_out[24]\, sample_filter_v2_out_23 => - \sample_filter_v2_out[25]\, sample_filter_v2_out_24 => - \sample_filter_v2_out[26]\, sample_filter_v2_out_25 => - \sample_filter_v2_out[27]\, sample_filter_v2_out_26 => - \sample_filter_v2_out[28]\, sample_filter_v2_out_27 => - \sample_filter_v2_out[29]\, sample_filter_v2_out_28 => - \sample_filter_v2_out[30]\, sample_filter_v2_out_29 => - \sample_filter_v2_out[31]\, sample_filter_v2_out_30 => - \sample_filter_v2_out[32]\, sample_filter_v2_out_31 => - \sample_filter_v2_out[33]\, sample_filter_v2_out_32 => - \sample_filter_v2_out[34]\, sample_filter_v2_out_33 => - \sample_filter_v2_out[35]\, sample_filter_v2_out_36 => - \sample_filter_v2_out[38]\, sample_filter_v2_out_37 => - \sample_filter_v2_out[39]\, sample_filter_v2_out_38 => - \sample_filter_v2_out[40]\, sample_filter_v2_out_39 => - \sample_filter_v2_out[41]\, sample_filter_v2_out_40 => - \sample_filter_v2_out[42]\, sample_filter_v2_out_41 => - \sample_filter_v2_out[43]\, sample_filter_v2_out_42 => - \sample_filter_v2_out[44]\, sample_filter_v2_out_43 => - \sample_filter_v2_out[45]\, sample_filter_v2_out_44 => - \sample_filter_v2_out[46]\, sample_filter_v2_out_45 => - \sample_filter_v2_out[47]\, sample_filter_v2_out_46 => - \sample_filter_v2_out[48]\, sample_filter_v2_out_47 => - \sample_filter_v2_out[49]\, sample_filter_v2_out_48 => - \sample_filter_v2_out[50]\, sample_filter_v2_out_49 => - \sample_filter_v2_out[51]\, sample_filter_v2_out_50 => - \sample_filter_v2_out[52]\, sample_filter_v2_out_51 => - \sample_filter_v2_out[53]\, sample_filter_v2_out_54 => - \sample_filter_v2_out[56]\, sample_filter_v2_out_55 => - \sample_filter_v2_out[57]\, sample_filter_v2_out_56 => - \sample_filter_v2_out[58]\, sample_filter_v2_out_57 => - \sample_filter_v2_out[59]\, sample_filter_v2_out_58 => - \sample_filter_v2_out[60]\, sample_filter_v2_out_59 => - \sample_filter_v2_out[61]\, sample_filter_v2_out_60 => - \sample_filter_v2_out[62]\, sample_filter_v2_out_61 => - \sample_filter_v2_out[63]\, sample_filter_v2_out_62 => - \sample_filter_v2_out[64]\, sample_filter_v2_out_63 => - \sample_filter_v2_out[65]\, sample_filter_v2_out_64 => - \sample_filter_v2_out[66]\, sample_filter_v2_out_65 => - \sample_filter_v2_out[67]\, sample_filter_v2_out_66 => - \sample_filter_v2_out[68]\, sample_filter_v2_out_67 => - \sample_filter_v2_out[69]\, sample_filter_v2_out_68 => - \sample_filter_v2_out[70]\, sample_filter_v2_out_69 => - \sample_filter_v2_out[71]\, sample_filter_v2_out_90 => - \sample_filter_v2_out[92]\, sample_filter_v2_out_91 => - \sample_filter_v2_out[93]\, sample_filter_v2_out_92 => - \sample_filter_v2_out[94]\, sample_filter_v2_out_93 => - \sample_filter_v2_out[95]\, sample_filter_v2_out_94 => - \sample_filter_v2_out[96]\, sample_filter_v2_out_95 => - \sample_filter_v2_out[97]\, sample_filter_v2_out_96 => - \sample_filter_v2_out[98]\, sample_filter_v2_out_97 => - \sample_filter_v2_out[99]\, sample_filter_v2_out_98 => - \sample_filter_v2_out[100]\, sample_filter_v2_out_99 => - \sample_filter_v2_out[101]\, sample_filter_v2_out_100 => - \sample_filter_v2_out[102]\, sample_filter_v2_out_101 => - \sample_filter_v2_out[103]\, sample_filter_v2_out_102 => - \sample_filter_v2_out[104]\, sample_filter_v2_out_103 => - \sample_filter_v2_out[105]\, sample_filter_v2_out_104 => - \sample_filter_v2_out[106]\, sample_filter_v2_out_105 => - \sample_filter_v2_out[107]\, sample_filter_v2_out_108 => - \sample_filter_v2_out[110]\, sample_filter_v2_out_126 => - \sample_filter_v2_out[128]\, sample_filter_v2_out_109 => - \sample_filter_v2_out[111]\, sample_filter_v2_out_127 => - \sample_filter_v2_out[129]\, sample_filter_v2_out_110 => - \sample_filter_v2_out[112]\, sample_filter_v2_out_128 => - \sample_filter_v2_out[130]\, sample_filter_v2_out_111 => - \sample_filter_v2_out[113]\, sample_filter_v2_out_129 => - \sample_filter_v2_out[131]\, sample_filter_v2_out_112 => - \sample_filter_v2_out[114]\, sample_filter_v2_out_130 => - \sample_filter_v2_out[132]\, sample_filter_v2_out_113 => - \sample_filter_v2_out[115]\, sample_filter_v2_out_131 => - \sample_filter_v2_out[133]\, sample_filter_v2_out_114 => - \sample_filter_v2_out[116]\, sample_filter_v2_out_132 => - \sample_filter_v2_out[134]\, sample_filter_v2_out_115 => - \sample_filter_v2_out[117]\, sample_filter_v2_out_133 => - \sample_filter_v2_out[135]\, sample_filter_v2_out_116 => - \sample_filter_v2_out[118]\, sample_filter_v2_out_134 => - \sample_filter_v2_out[136]\, sample_filter_v2_out_117 => - \sample_filter_v2_out[119]\, sample_filter_v2_out_135 => - \sample_filter_v2_out[137]\, sample_filter_v2_out_118 => - \sample_filter_v2_out[120]\, sample_filter_v2_out_136 => - \sample_filter_v2_out[138]\, sample_filter_v2_out_119 => - \sample_filter_v2_out[121]\, sample_filter_v2_out_137 => - \sample_filter_v2_out[139]\, sample_filter_v2_out_120 => - \sample_filter_v2_out[122]\, sample_filter_v2_out_138 => - \sample_filter_v2_out[140]\, sample_filter_v2_out_121 => - \sample_filter_v2_out[123]\, sample_filter_v2_out_139 => - \sample_filter_v2_out[141]\, sample_filter_v2_out_122 => - \sample_filter_v2_out[124]\, sample_filter_v2_out_140 => - \sample_filter_v2_out[142]\, sample_filter_v2_out_123 => - \sample_filter_v2_out[125]\, sample_filter_v2_out_141 => - \sample_filter_v2_out[143]\, sample_4(15) => - \sample_4[15]\, sample_4(14) => \sample_4[14]\, - sample_4(13) => \sample_4[13]\, sample_4(12) => - \sample_4[12]\, sample_4(11) => \sample_4[11]\, - sample_4(10) => \sample_4[10]\, sample_4(9) => - \sample_4[9]\, sample_4(8) => \sample_4[8]\, sample_4(7) - => \sample_4[7]\, sample_4(6) => \sample_4[6]\, - sample_4(5) => \sample_4[5]\, sample_4(4) => - \sample_4[4]\, sample_4(3) => \sample_4[3]\, sample_4(2) - => \sample_4[2]\, sample_4(1) => \sample_4[1]\, - sample_4(0) => \sample_4[0]\, sample_5(15) => - \sample_5[15]\, sample_5(14) => \sample_5[14]\, - sample_5(13) => \sample_5[13]\, sample_5(12) => - \sample_5[12]\, sample_5(11) => \sample_5[11]\, - sample_5(10) => \sample_5[10]\, sample_5(9) => - \sample_5[9]\, sample_5(8) => \sample_5[8]\, sample_5(7) - => \sample_5[7]\, sample_5(6) => \sample_5[6]\, - sample_5(5) => \sample_5[5]\, sample_5(4) => - \sample_5[4]\, sample_5(3) => \sample_5[3]\, sample_5(2) - => \sample_5[2]\, sample_5(1) => \sample_5[1]\, - sample_5(0) => \sample_5[0]\, sample_3(15) => - \sample_3[15]\, sample_3(14) => \sample_3[14]\, - sample_3(13) => \sample_3[13]\, sample_3(12) => - \sample_3[12]\, sample_3(11) => \sample_3[11]\, - sample_3(10) => \sample_3[10]\, sample_3(9) => - \sample_3[9]\, sample_3(8) => \sample_3[8]\, sample_3(7) - => \sample_3[7]\, sample_3(6) => \sample_3[6]\, - sample_3(5) => \sample_3[5]\, sample_3(4) => - \sample_3[4]\, sample_3(3) => \sample_3[3]\, sample_3(2) - => \sample_3[2]\, sample_3(1) => \sample_3[1]\, - sample_3(0) => \sample_3[0]\, sample_2(15) => - \sample_2[15]\, sample_2(14) => \sample_2[14]\, - sample_2(13) => \sample_2[13]\, sample_2(12) => - \sample_2[12]\, sample_2(11) => \sample_2[11]\, - sample_2(10) => \sample_2[10]\, sample_2(9) => - \sample_2[9]\, sample_2(8) => \sample_2[8]\, sample_2(7) - => \sample_2[7]\, sample_2(6) => \sample_2[6]\, - sample_2(5) => \sample_2[5]\, sample_2(4) => - \sample_2[4]\, sample_2(3) => \sample_2[3]\, sample_2(2) - => \sample_2[2]\, sample_2(1) => \sample_2[1]\, - sample_2(0) => \sample_2[0]\, sample_6(15) => - \sample_6[15]\, sample_6(14) => \sample_6[14]\, - sample_6(13) => \sample_6[13]\, sample_6(12) => - \sample_6[12]\, sample_6(11) => \sample_6[11]\, - sample_6(10) => \sample_6[10]\, sample_6(9) => - \sample_6[9]\, sample_6(8) => \sample_6[8]\, sample_6(7) - => \sample_6[7]\, sample_6(6) => \sample_6[6]\, - sample_6(5) => \sample_6[5]\, sample_6(4) => - \sample_6[4]\, sample_6(3) => \sample_6[3]\, sample_6(2) - => \sample_6[2]\, sample_6(1) => \sample_6[1]\, - sample_6(0) => \sample_6[0]\, sample_1(15) => - \sample_1[15]\, sample_1(14) => \sample_1[14]\, - sample_1(13) => \sample_1[13]\, sample_1(12) => - \sample_1[12]\, sample_1(11) => \sample_1[11]\, - sample_1(10) => \sample_1[10]\, sample_1(9) => - \sample_1[9]\, sample_1(8) => \sample_1[8]\, sample_1(7) - => \sample_1[7]\, sample_1(6) => \sample_1[6]\, - sample_1(5) => \sample_1[5]\, sample_1(4) => - \sample_1[4]\, sample_1(3) => \sample_1[3]\, sample_1(2) - => \sample_1[2]\, sample_1(1) => \sample_1[1]\, - sample_1(0) => \sample_1[0]\, sample_0(15) => - \sample_0[15]\, sample_0(14) => \sample_0[14]\, - sample_0(13) => \sample_0[13]\, sample_0(12) => - \sample_0[12]\, sample_0(11) => \sample_0[11]\, - sample_0(10) => \sample_0[10]\, sample_0(9) => - \sample_0[9]\, sample_0(8) => \sample_0[8]\, sample_0(7) - => \sample_0[7]\, sample_0(6) => \sample_0[6]\, - sample_0(5) => \sample_0[5]\, sample_0(4) => - \sample_0[4]\, sample_0(3) => \sample_0[3]\, sample_0(2) - => \sample_0[2]\, sample_0(1) => \sample_0[1]\, - sample_0(0) => \sample_0[0]\, sample_7(15) => - \sample_7[15]\, sample_7(14) => \sample_7[14]\, - sample_7(13) => \sample_7[13]\, sample_7(12) => - \sample_7[12]\, sample_7(11) => \sample_7[11]\, - sample_7(10) => \sample_7[10]\, sample_7(9) => - \sample_7[9]\, sample_7(8) => \sample_7[8]\, sample_7(7) - => \sample_7[7]\, sample_7(6) => \sample_7[6]\, - sample_7(5) => \sample_7[5]\, sample_7(4) => - \sample_7[4]\, sample_7(3) => \sample_7[3]\, sample_7(2) - => \sample_7[2]\, sample_7(1) => \sample_7[1]\, - sample_7(0) => \sample_7[0]\, IIR_CEL_CTRLR_v2_VCC => - lpp_top_lfr_wf_picker_ip_VCC, IIR_CEL_CTRLR_v2_GND => - lpp_top_lfr_wf_picker_ip_GND, rstn => rstn, lclk_c => - lclk_c, sample_filter_v2_out_val => - sample_filter_v2_out_val, sample_val_delay => - \sample_val_delay\, sample_val_delay_5 => - \sample_val_delay_5\, sample_val_delay_4 => - \sample_val_delay_4\, sample_val_delay_3 => - \sample_val_delay_3\, sample_val_delay_2 => - \sample_val_delay_2\, sample_val_delay_1 => - \sample_val_delay_1\, sample_val_delay_0 => - \sample_val_delay_0\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I101_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I89_un1_Y, B => N194, C - => N195, Y => \sample_data_shaping_f1_f0_s[8]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[103]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_113[103]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[103]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I22_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[137]\, B => - \sample_filter_v2_out[119]\, Y => N191); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[135]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[135]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[135]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I98_Y_0 : - AX1D - port map(A => I85_un1_Y, B => N274_0, C => N189, Y => - \sample_data_shaping_f1_f0_s[5]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I90_un1_Y : - OA1 - port map(A => I85_un1_Y_0, B => N274, C => N189_0, Y => - I90_un1_Y_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I24_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[135]\, B => - \sample_filter_v2_out[117]\, Y => N195); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[28]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[28]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[28]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out_RNO[110]\ : - MX2 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_data_shaping_f1_f0_s[15]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_373[110]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I108_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_filter_v2_out[128]\, C => N240, Y => - \sample_data_shaping_f1_f0_s[15]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I78_Y : - AO1 - port map(A => N268, B => N265, C => N264, Y => N270); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I71_Y : - AO1C - port map(A => N255, B => N258, C => N254_0, Y => N260); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I49_Y_0 : - AO18 - port map(A => N198_0, B => \sample_filter_v2_out[133]\, C - => \sample_filter_v2_out[115]\, Y => - SUB_16x16_medium_area_I49_Y_0_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I17_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[124]\, B => - \sample_filter_v2_out[106]\, Y => N181); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[30]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[30]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[30]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I33_Y : - XAI1A - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[129]\, C => N205, Y => N212_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I17_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[124]\, B => - \sample_filter_v2_out[142]\, Y => N182); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I104_Y_0 : - XOR2 - port map(A => N258, B => N201, Y => - \sample_data_shaping_f1_f0_s[11]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[119]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_157[119]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[119]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I49_Y_0 : - AO18 - port map(A => N198, B => \sample_filter_v2_out[115]\, C => - \sample_filter_v2_out[97]\, Y => - SUB_16x16_medium_area_I49_Y_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out_RNO[101]\ : - MX2 - port map(A => \sample_filter_v2_out[101]\, B => - \sample_data_shaping_f2_f1_s[6]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_161[101]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I29_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[94]\, B => - \sample_filter_v2_out[112]\, Y => N206); - - \SampleLoop_data_shaping.14.sample_data_shaping_out_RNO[93]\ : - MX2 - port map(A => \sample_filter_v2_out[93]\, B => - \sample_data_shaping_f2_f1_s[14]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_353[93]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[47]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[47]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[47]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I19_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[122]\, B => - \sample_filter_v2_out[104]\, Y => N185_0); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[120]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_133[120]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[120]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[13]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[13]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[13]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[32]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[32]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[32]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I21_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[102]\, B => - \sample_filter_v2_out[120]\, Y => N190); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[15]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[15]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[15]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out_RNO[95]\ : - MX2 - port map(A => \sample_filter_v2_out[95]\, B => - \sample_data_shaping_f2_f1_s[12]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_305[95]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[113]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_301[113]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[113]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y_1 : - AOI1B - port map(A => N274_0, B => N220_0, C => - SUB_16x16_medium_area_I56_Y_0_0, Y => - SUB_16x16_medium_area_I56_Y_1_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I20_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[121]\, B => - \sample_filter_v2_out[103]\, Y => N187_0); - - \SampleLoop_data_shaping.2.sample_data_shaping_out_RNO[123]\ : - MX2 - port map(A => \sample_filter_v2_out[123]\, B => - \sample_data_shaping_f1_f0_s[2]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_61[123]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[67]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[67]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[67]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I37_Y : - XA1A - port map(A => \sample_filter_v2_out[97]\, B => - \sample_filter_v2_out[115]\, C => N197_0, Y => N216_0); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[104]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_89[104]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[104]\); - - sample_val_delay : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[35]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[35]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[35]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I48_Y : - NOR2B - port map(A => N255_0, B => N212, Y => N229); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_un1_Y_0 : - NOR2B - port map(A => N229, B => N245, Y => - SUB_16x16_medium_area_I57_un1_Y_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[129]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[129]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[129]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I94_Y_0 : - XOR2 - port map(A => N225_0, B => N181_0, Y => - \sample_data_shaping_f1_f0_s[1]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[107]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_17[107]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[107]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I107_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[129]\, C => N282_i, Y => - \sample_data_shaping_f1_f0_s_i[14]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I19_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[140]\, B => - \sample_filter_v2_out[122]\, Y => N185); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[137]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[137]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[137]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[11]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[11]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[11]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[46]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[46]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[46]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[110]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_373[110]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[110]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[61]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[61]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[61]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I102_Y_0 : - XOR2 - port map(A => N270, B => N197, Y => - \sample_data_shaping_f1_f0_s[9]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[68]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[68]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[68]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I42_Y : - AO13 - port map(A => N186_0, B => \sample_filter_v2_out[103]\, C - => \sample_filter_v2_out[121]\, Y => N274); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[57]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[57]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[57]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I107_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[93]\, B => - \sample_filter_v2_out[111]\, C => N282_i_0, Y => - \sample_data_shaping_f2_f1_s[14]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[49]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[49]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[49]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out_RNO[104]\ : - MX2 - port map(A => \sample_filter_v2_out[104]\, B => - \sample_data_shaping_f2_f1_s[3]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_89[104]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[17]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[17]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[17]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I92_Y : - AO18 - port map(A => N225, B => \sample_filter_v2_out[124]\, C => - \sample_filter_v2_out[106]\, Y => N294_i); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I105_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[131]\, C => N284_i, Y => - \sample_data_shaping_f1_f0_s[12]\); - - \SampleLoop_data_shaping.9.sample_data_shaping_out_RNO[116]\ : - MX2 - port map(A => \sample_filter_v2_out[116]\, B => - \sample_data_shaping_f1_f0_s[9]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_229[116]\); - - Downsampling_f3 : Downsampling_6_16_256 - port map(sample_f1(111) => \sample_f1[111]\, sample_f1(110) - => \sample_f1[110]\, sample_f1(109) => \sample_f1[109]\, - sample_f1(108) => \sample_f1[108]\, sample_f1(107) => - \sample_f1[107]\, sample_f1(106) => \sample_f1[106]\, - sample_f1(105) => \sample_f1[105]\, sample_f1(104) => - \sample_f1[104]\, sample_f1(103) => \sample_f1[103]\, - sample_f1(102) => \sample_f1[102]\, sample_f1(101) => - \sample_f1[101]\, sample_f1(100) => \sample_f1[100]\, - sample_f1(99) => \sample_f1[99]\, sample_f1(98) => - \sample_f1[98]\, sample_f1(97) => \sample_f1[97]\, - sample_f1(96) => \sample_f1[96]\, sample_f1(95) => - \sample_f1[95]\, sample_f1(94) => \sample_f1[94]\, - sample_f1(93) => \sample_f1[93]\, sample_f1(92) => - \sample_f1[92]\, sample_f1(91) => \sample_f1[91]\, - sample_f1(90) => \sample_f1[90]\, sample_f1(89) => - \sample_f1[89]\, sample_f1(88) => \sample_f1[88]\, - sample_f1(87) => \sample_f1[87]\, sample_f1(86) => - \sample_f1[86]\, sample_f1(85) => \sample_f1[85]\, - sample_f1(84) => \sample_f1[84]\, sample_f1(83) => - \sample_f1[83]\, sample_f1(82) => \sample_f1[82]\, - sample_f1(81) => \sample_f1[81]\, sample_f1(80) => - \sample_f1[80]\, sample_f1_wdata_95 => - \sample_f1_wdata[95]\, sample_f1_wdata_94 => - \sample_f1_wdata[94]\, sample_f1_wdata_93 => - \sample_f1_wdata[93]\, sample_f1_wdata_92 => - \sample_f1_wdata[92]\, sample_f1_wdata_91 => - \sample_f1_wdata[91]\, sample_f1_wdata_90 => - \sample_f1_wdata[90]\, sample_f1_wdata_89 => - \sample_f1_wdata[89]\, sample_f1_wdata_88 => - \sample_f1_wdata[88]\, sample_f1_wdata_87 => - \sample_f1_wdata[87]\, sample_f1_wdata_86 => - \sample_f1_wdata[86]\, sample_f1_wdata_85 => - \sample_f1_wdata[85]\, sample_f1_wdata_84 => - \sample_f1_wdata[84]\, sample_f1_wdata_83 => - \sample_f1_wdata[83]\, sample_f1_wdata_82 => - \sample_f1_wdata[82]\, sample_f1_wdata_81 => - \sample_f1_wdata[81]\, sample_f1_wdata_80 => - \sample_f1_wdata[80]\, sample_f1_wdata_79 => - \sample_f1_wdata[79]\, sample_f1_wdata_78 => - \sample_f1_wdata[78]\, sample_f1_wdata_77 => - \sample_f1_wdata[77]\, sample_f1_wdata_76 => - \sample_f1_wdata[76]\, sample_f1_wdata_75 => - \sample_f1_wdata[75]\, sample_f1_wdata_74 => - \sample_f1_wdata[74]\, sample_f1_wdata_73 => - \sample_f1_wdata[73]\, sample_f1_wdata_72 => - \sample_f1_wdata[72]\, sample_f1_wdata_71 => - \sample_f1_wdata[71]\, sample_f1_wdata_70 => - \sample_f1_wdata[70]\, sample_f1_wdata_69 => - \sample_f1_wdata[69]\, sample_f1_wdata_68 => - \sample_f1_wdata[68]\, sample_f1_wdata_67 => - \sample_f1_wdata[67]\, sample_f1_wdata_66 => - \sample_f1_wdata[66]\, sample_f1_wdata_65 => - \sample_f1_wdata[65]\, sample_f1_wdata_64 => - \sample_f1_wdata[64]\, sample_f1_wdata_63 => - \sample_f1_wdata[63]\, sample_f1_wdata_62 => - \sample_f1_wdata[62]\, sample_f1_wdata_61 => - \sample_f1_wdata[61]\, sample_f1_wdata_60 => - \sample_f1_wdata[60]\, sample_f1_wdata_59 => - \sample_f1_wdata[59]\, sample_f1_wdata_58 => - \sample_f1_wdata[58]\, sample_f1_wdata_57 => - \sample_f1_wdata[57]\, sample_f1_wdata_56 => - \sample_f1_wdata[56]\, sample_f1_wdata_55 => - \sample_f1_wdata[55]\, sample_f1_wdata_54 => - \sample_f1_wdata[54]\, sample_f1_wdata_53 => - \sample_f1_wdata[53]\, sample_f1_wdata_52 => - \sample_f1_wdata[52]\, sample_f1_wdata_51 => - \sample_f1_wdata[51]\, sample_f1_wdata_50 => - \sample_f1_wdata[50]\, sample_f1_wdata_49 => - \sample_f1_wdata[49]\, sample_f1_wdata_48 => - \sample_f1_wdata[48]\, sample_f1_wdata_15 => - \sample_f1_wdata[15]\, sample_f1_wdata_14 => - \sample_f1_wdata[14]\, sample_f1_wdata_13 => - \sample_f1_wdata[13]\, sample_f1_wdata_12 => - \sample_f1_wdata[12]\, sample_f1_wdata_11 => - \sample_f1_wdata[11]\, sample_f1_wdata_10 => - \sample_f1_wdata[10]\, sample_f1_wdata_9 => - \sample_f1_wdata[9]\, sample_f1_wdata_8 => - \sample_f1_wdata[8]\, sample_f1_wdata_7 => - \sample_f1_wdata[7]\, sample_f1_wdata_6 => - \sample_f1_wdata[6]\, sample_f1_wdata_5 => - \sample_f1_wdata[5]\, sample_f1_wdata_4 => - \sample_f1_wdata[4]\, sample_f1_wdata_3 => - \sample_f1_wdata[3]\, sample_f1_wdata_2 => - \sample_f1_wdata[2]\, sample_f1_wdata_1 => - \sample_f1_wdata[1]\, sample_f1_wdata_0 => - \sample_f1_wdata[0]\, sample_f3_wdata(95) => - \sample_f3_wdata[95]\, sample_f3_wdata(94) => - \sample_f3_wdata[94]\, sample_f3_wdata(93) => - \sample_f3_wdata[93]\, sample_f3_wdata(92) => - \sample_f3_wdata[92]\, sample_f3_wdata(91) => - \sample_f3_wdata[91]\, sample_f3_wdata(90) => - \sample_f3_wdata[90]\, sample_f3_wdata(89) => - \sample_f3_wdata[89]\, sample_f3_wdata(88) => - \sample_f3_wdata[88]\, sample_f3_wdata(87) => - \sample_f3_wdata[87]\, sample_f3_wdata(86) => - \sample_f3_wdata[86]\, sample_f3_wdata(85) => - \sample_f3_wdata[85]\, sample_f3_wdata(84) => - \sample_f3_wdata[84]\, sample_f3_wdata(83) => - \sample_f3_wdata[83]\, sample_f3_wdata(82) => - \sample_f3_wdata[82]\, sample_f3_wdata(81) => - \sample_f3_wdata[81]\, sample_f3_wdata(80) => - \sample_f3_wdata[80]\, sample_f3_wdata(79) => - \sample_f3_wdata[79]\, sample_f3_wdata(78) => - \sample_f3_wdata[78]\, sample_f3_wdata(77) => - \sample_f3_wdata[77]\, sample_f3_wdata(76) => - \sample_f3_wdata[76]\, sample_f3_wdata(75) => - \sample_f3_wdata[75]\, sample_f3_wdata(74) => - \sample_f3_wdata[74]\, sample_f3_wdata(73) => - \sample_f3_wdata[73]\, sample_f3_wdata(72) => - \sample_f3_wdata[72]\, sample_f3_wdata(71) => - \sample_f3_wdata[71]\, sample_f3_wdata(70) => - \sample_f3_wdata[70]\, sample_f3_wdata(69) => - \sample_f3_wdata[69]\, sample_f3_wdata(68) => - \sample_f3_wdata[68]\, sample_f3_wdata(67) => - \sample_f3_wdata[67]\, sample_f3_wdata(66) => - \sample_f3_wdata[66]\, sample_f3_wdata(65) => - \sample_f3_wdata[65]\, sample_f3_wdata(64) => - \sample_f3_wdata[64]\, sample_f3_wdata(63) => - \sample_f3_wdata[63]\, sample_f3_wdata(62) => - \sample_f3_wdata[62]\, sample_f3_wdata(61) => - \sample_f3_wdata[61]\, sample_f3_wdata(60) => - \sample_f3_wdata[60]\, sample_f3_wdata(59) => - \sample_f3_wdata[59]\, sample_f3_wdata(58) => - \sample_f3_wdata[58]\, sample_f3_wdata(57) => - \sample_f3_wdata[57]\, sample_f3_wdata(56) => - \sample_f3_wdata[56]\, sample_f3_wdata(55) => - \sample_f3_wdata[55]\, sample_f3_wdata(54) => - \sample_f3_wdata[54]\, sample_f3_wdata(53) => - \sample_f3_wdata[53]\, sample_f3_wdata(52) => - \sample_f3_wdata[52]\, sample_f3_wdata(51) => - \sample_f3_wdata[51]\, sample_f3_wdata(50) => - \sample_f3_wdata[50]\, sample_f3_wdata(49) => - \sample_f3_wdata[49]\, sample_f3_wdata(48) => - \sample_f3_wdata[48]\, sample_f3_wdata(47) => - \sample_f3_wdata[47]\, sample_f3_wdata(46) => - \sample_f3_wdata[46]\, sample_f3_wdata(45) => - \sample_f3_wdata[45]\, sample_f3_wdata(44) => - \sample_f3_wdata[44]\, sample_f3_wdata(43) => - \sample_f3_wdata[43]\, sample_f3_wdata(42) => - \sample_f3_wdata[42]\, sample_f3_wdata(41) => - \sample_f3_wdata[41]\, sample_f3_wdata(40) => - \sample_f3_wdata[40]\, sample_f3_wdata(39) => - \sample_f3_wdata[39]\, sample_f3_wdata(38) => - \sample_f3_wdata[38]\, sample_f3_wdata(37) => - \sample_f3_wdata[37]\, sample_f3_wdata(36) => - \sample_f3_wdata[36]\, sample_f3_wdata(35) => - \sample_f3_wdata[35]\, sample_f3_wdata(34) => - \sample_f3_wdata[34]\, sample_f3_wdata(33) => - \sample_f3_wdata[33]\, sample_f3_wdata(32) => - \sample_f3_wdata[32]\, sample_f3_wdata(31) => - \sample_f3_wdata[31]\, sample_f3_wdata(30) => - \sample_f3_wdata[30]\, sample_f3_wdata(29) => - \sample_f3_wdata[29]\, sample_f3_wdata(28) => - \sample_f3_wdata[28]\, sample_f3_wdata(27) => - \sample_f3_wdata[27]\, sample_f3_wdata(26) => - \sample_f3_wdata[26]\, sample_f3_wdata(25) => - \sample_f3_wdata[25]\, sample_f3_wdata(24) => - \sample_f3_wdata[24]\, sample_f3_wdata(23) => - \sample_f3_wdata[23]\, sample_f3_wdata(22) => - \sample_f3_wdata[22]\, sample_f3_wdata(21) => - \sample_f3_wdata[21]\, sample_f3_wdata(20) => - \sample_f3_wdata[20]\, sample_f3_wdata(19) => - \sample_f3_wdata[19]\, sample_f3_wdata(18) => - \sample_f3_wdata[18]\, sample_f3_wdata(17) => - \sample_f3_wdata[17]\, sample_f3_wdata(16) => - \sample_f3_wdata[16]\, sample_f3_wdata(15) => - \sample_f3_wdata[15]\, sample_f3_wdata(14) => - \sample_f3_wdata[14]\, sample_f3_wdata(13) => - \sample_f3_wdata[13]\, sample_f3_wdata(12) => - \sample_f3_wdata[12]\, sample_f3_wdata(11) => - \sample_f3_wdata[11]\, sample_f3_wdata(10) => - \sample_f3_wdata[10]\, sample_f3_wdata(9) => - \sample_f3_wdata[9]\, sample_f3_wdata(8) => - \sample_f3_wdata[8]\, sample_f3_wdata(7) => - \sample_f3_wdata[7]\, sample_f3_wdata(6) => - \sample_f3_wdata[6]\, sample_f3_wdata(5) => - \sample_f3_wdata[5]\, sample_f3_wdata(4) => - \sample_f3_wdata[4]\, sample_f3_wdata(3) => - \sample_f3_wdata[3]\, sample_f3_wdata(2) => - \sample_f3_wdata[2]\, sample_f3_wdata(1) => - \sample_f3_wdata[1]\, sample_f3_wdata(0) => - \sample_f3_wdata[0]\, sample_f1_val => sample_f1_val, - lclk_c => lclk_c, sample_f3_val => sample_f3_val, - sample_f1_val_0 => sample_f1_val_0, rstn => rstn); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I34_Y : - AO18 - port map(A => N202, B => \sample_filter_v2_out[131]\, C => - \sample_filter_v2_out[113]\, Y => N254_0); - - \SampleLoop_data_shaping.10.sample_data_shaping_out_RNO[115]\ : - MX2 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_data_shaping_f1_f0_s[10]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_253[115]\); - - GND_i : GND - port map(Y => \GND\); - - Downsampling_f2 : Downsampling_6_16_96 - port map(sample_f0(111) => \sample_f0[111]\, sample_f0(110) - => \sample_f0[110]\, sample_f0(109) => \sample_f0[109]\, - sample_f0(108) => \sample_f0[108]\, sample_f0(107) => - \sample_f0[107]\, sample_f0(106) => \sample_f0[106]\, - sample_f0(105) => \sample_f0[105]\, sample_f0(104) => - \sample_f0[104]\, sample_f0(103) => \sample_f0[103]\, - sample_f0(102) => \sample_f0[102]\, sample_f0(101) => - \sample_f0[101]\, sample_f0(100) => \sample_f0[100]\, - sample_f0(99) => \sample_f0[99]\, sample_f0(98) => - \sample_f0[98]\, sample_f0(97) => \sample_f0[97]\, - sample_f0(96) => \sample_f0[96]\, sample_f0(95) => - \sample_f0[95]\, sample_f0(94) => \sample_f0[94]\, - sample_f0(93) => \sample_f0[93]\, sample_f0(92) => - \sample_f0[92]\, sample_f0(91) => \sample_f0[91]\, - sample_f0(90) => \sample_f0[90]\, sample_f0(89) => - \sample_f0[89]\, sample_f0(88) => \sample_f0[88]\, - sample_f0(87) => \sample_f0[87]\, sample_f0(86) => - \sample_f0[86]\, sample_f0(85) => \sample_f0[85]\, - sample_f0(84) => \sample_f0[84]\, sample_f0(83) => - \sample_f0[83]\, sample_f0(82) => \sample_f0[82]\, - sample_f0(81) => \sample_f0[81]\, sample_f0(80) => - \sample_f0[80]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_f2_wdata(95) => - \sample_f2_wdata[95]\, sample_f2_wdata(94) => - \sample_f2_wdata[94]\, sample_f2_wdata(93) => - \sample_f2_wdata[93]\, sample_f2_wdata(92) => - \sample_f2_wdata[92]\, sample_f2_wdata(91) => - \sample_f2_wdata[91]\, sample_f2_wdata(90) => - \sample_f2_wdata[90]\, sample_f2_wdata(89) => - \sample_f2_wdata[89]\, sample_f2_wdata(88) => - \sample_f2_wdata[88]\, sample_f2_wdata(87) => - \sample_f2_wdata[87]\, sample_f2_wdata(86) => - \sample_f2_wdata[86]\, sample_f2_wdata(85) => - \sample_f2_wdata[85]\, sample_f2_wdata(84) => - \sample_f2_wdata[84]\, sample_f2_wdata(83) => - \sample_f2_wdata[83]\, sample_f2_wdata(82) => - \sample_f2_wdata[82]\, sample_f2_wdata(81) => - \sample_f2_wdata[81]\, sample_f2_wdata(80) => - \sample_f2_wdata[80]\, sample_f2_wdata(79) => - \sample_f2_wdata[79]\, sample_f2_wdata(78) => - \sample_f2_wdata[78]\, sample_f2_wdata(77) => - \sample_f2_wdata[77]\, sample_f2_wdata(76) => - \sample_f2_wdata[76]\, sample_f2_wdata(75) => - \sample_f2_wdata[75]\, sample_f2_wdata(74) => - \sample_f2_wdata[74]\, sample_f2_wdata(73) => - \sample_f2_wdata[73]\, sample_f2_wdata(72) => - \sample_f2_wdata[72]\, sample_f2_wdata(71) => - \sample_f2_wdata[71]\, sample_f2_wdata(70) => - \sample_f2_wdata[70]\, sample_f2_wdata(69) => - \sample_f2_wdata[69]\, sample_f2_wdata(68) => - \sample_f2_wdata[68]\, sample_f2_wdata(67) => - \sample_f2_wdata[67]\, sample_f2_wdata(66) => - \sample_f2_wdata[66]\, sample_f2_wdata(65) => - \sample_f2_wdata[65]\, sample_f2_wdata(64) => - \sample_f2_wdata[64]\, sample_f2_wdata(63) => - \sample_f2_wdata[63]\, sample_f2_wdata(62) => - \sample_f2_wdata[62]\, sample_f2_wdata(61) => - \sample_f2_wdata[61]\, sample_f2_wdata(60) => - \sample_f2_wdata[60]\, sample_f2_wdata(59) => - \sample_f2_wdata[59]\, sample_f2_wdata(58) => - \sample_f2_wdata[58]\, sample_f2_wdata(57) => - \sample_f2_wdata[57]\, sample_f2_wdata(56) => - \sample_f2_wdata[56]\, sample_f2_wdata(55) => - \sample_f2_wdata[55]\, sample_f2_wdata(54) => - \sample_f2_wdata[54]\, sample_f2_wdata(53) => - \sample_f2_wdata[53]\, sample_f2_wdata(52) => - \sample_f2_wdata[52]\, sample_f2_wdata(51) => - \sample_f2_wdata[51]\, sample_f2_wdata(50) => - \sample_f2_wdata[50]\, sample_f2_wdata(49) => - \sample_f2_wdata[49]\, sample_f2_wdata(48) => - \sample_f2_wdata[48]\, sample_f2_wdata(47) => - \sample_f2_wdata[47]\, sample_f2_wdata(46) => - \sample_f2_wdata[46]\, sample_f2_wdata(45) => - \sample_f2_wdata[45]\, sample_f2_wdata(44) => - \sample_f2_wdata[44]\, sample_f2_wdata(43) => - \sample_f2_wdata[43]\, sample_f2_wdata(42) => - \sample_f2_wdata[42]\, sample_f2_wdata(41) => - \sample_f2_wdata[41]\, sample_f2_wdata(40) => - \sample_f2_wdata[40]\, sample_f2_wdata(39) => - \sample_f2_wdata[39]\, sample_f2_wdata(38) => - \sample_f2_wdata[38]\, sample_f2_wdata(37) => - \sample_f2_wdata[37]\, sample_f2_wdata(36) => - \sample_f2_wdata[36]\, sample_f2_wdata(35) => - \sample_f2_wdata[35]\, sample_f2_wdata(34) => - \sample_f2_wdata[34]\, sample_f2_wdata(33) => - \sample_f2_wdata[33]\, sample_f2_wdata(32) => - \sample_f2_wdata[32]\, sample_f2_wdata(31) => - \sample_f2_wdata[31]\, sample_f2_wdata(30) => - \sample_f2_wdata[30]\, sample_f2_wdata(29) => - \sample_f2_wdata[29]\, sample_f2_wdata(28) => - \sample_f2_wdata[28]\, sample_f2_wdata(27) => - \sample_f2_wdata[27]\, sample_f2_wdata(26) => - \sample_f2_wdata[26]\, sample_f2_wdata(25) => - \sample_f2_wdata[25]\, sample_f2_wdata(24) => - \sample_f2_wdata[24]\, sample_f2_wdata(23) => - \sample_f2_wdata[23]\, sample_f2_wdata(22) => - \sample_f2_wdata[22]\, sample_f2_wdata(21) => - \sample_f2_wdata[21]\, sample_f2_wdata(20) => - \sample_f2_wdata[20]\, sample_f2_wdata(19) => - \sample_f2_wdata[19]\, sample_f2_wdata(18) => - \sample_f2_wdata[18]\, sample_f2_wdata(17) => - \sample_f2_wdata[17]\, sample_f2_wdata(16) => - \sample_f2_wdata[16]\, sample_f2_wdata(15) => - \sample_f2_wdata[15]\, sample_f2_wdata(14) => - \sample_f2_wdata[14]\, sample_f2_wdata(13) => - \sample_f2_wdata[13]\, sample_f2_wdata(12) => - \sample_f2_wdata[12]\, sample_f2_wdata(11) => - \sample_f2_wdata[11]\, sample_f2_wdata(10) => - \sample_f2_wdata[10]\, sample_f2_wdata(9) => - \sample_f2_wdata[9]\, sample_f2_wdata(8) => - \sample_f2_wdata[8]\, sample_f2_wdata(7) => - \sample_f2_wdata[7]\, sample_f2_wdata(6) => - \sample_f2_wdata[6]\, sample_f2_wdata(5) => - \sample_f2_wdata[5]\, sample_f2_wdata(4) => - \sample_f2_wdata[4]\, sample_f2_wdata(3) => - \sample_f2_wdata[3]\, sample_f2_wdata(2) => - \sample_f2_wdata[2]\, sample_f2_wdata(1) => - \sample_f2_wdata[1]\, sample_f2_wdata(0) => - \sample_f2_wdata[0]\, sample_f0_val => sample_f0_val, - sample_f0_val_2 => sample_f0_val_2, lclk_c => lclk_c, - sample_f2_val => sample_f2_val, sample_f0_val_0 => - sample_f0_val_0, rstn => rstn); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I38_Y : - AO13 - port map(A => N194_0, B => \sample_filter_v2_out[99]\, C - => \sample_filter_v2_out[117]\, Y => N264_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I95_Y_0 : - XNOR2 - port map(A => N294_i, B => N183, Y => - \sample_data_shaping_f2_f1_s[2]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[33]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[33]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[33]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_Y : - OR2B - port map(A => SUB_16x16_medium_area_I53_Y_0, B => - I53_un1_Y_0, Y => N278); - - sample_val_delay_4 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_4\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y : - AO1B - port map(A => SUB_16x16_medium_area_I56_un1_Y_0_0, B => - N278, C => SUB_16x16_medium_area_I56_Y_1_0, Y => N268); - - \SampleLoop_data_shaping.14.sample_data_shaping_out_RNO[111]\ : - MX2B - port map(A => \sample_filter_v2_out[111]\, B => - \sample_data_shaping_f1_f0_s_i[14]\, S => - data_shaping_SP0, Y => \sample_data_shaping_out_349[111]\); - - sample_val_delay_0 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_0\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[122]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_85[122]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[122]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[20]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[20]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[20]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_Y : - OR2B - port map(A => SUB_16x16_medium_area_I53_Y_0_0, B => - I53_un1_Y, Y => N278_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I87_Y : - AO18 - port map(A => N258, B => \sample_filter_v2_out[132]\, C => - \sample_filter_v2_out[114]\, Y => N284_i); - - \SampleLoop_data_shaping.11.sample_data_shaping_out_RNO[96]\ : - MX2 - port map(A => \sample_filter_v2_out[96]\, B => - \sample_data_shaping_f2_f1_s[11]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_281[96]\); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[3]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[3]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[3]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_un1_Y_0 : - NOR2B - port map(A => N229_0, B => N245_0, Y => - SUB_16x16_medium_area_I57_un1_Y_0_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I43_Y : - NOR2B - port map(A => N187, B => N185, Y => N275_0); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[58]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[58]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[58]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I46_Y : - OR2A - port map(A => \sample_filter_v2_out[143]\, B => - \sample_filter_v2_out[125]\, Y => N225_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[26]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[26]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[26]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[56]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[56]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[56]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I102_Y_0 : - XOR2 - port map(A => N270_0, B => N197_0, Y => - \sample_data_shaping_f2_f1_s[9]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I21_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[138]\, B => - \sample_filter_v2_out[120]\, Y => N189); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[143]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[143]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[143]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out_RNO[107]\ : - AX1C - port map(A => \sample_filter_v2_out[125]\, B => - data_shaping_SP1, C => \sample_filter_v2_out[107]\, Y => - \sample_data_shaping_out_17[107]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[27]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[27]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[27]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_un1_Y : - OR3C - port map(A => N225, B => N183, C => N181, Y => I53_un1_Y); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I85_un1_Y : - NOR2B - port map(A => N278, B => N275_0, Y => I85_un1_Y); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[136]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[136]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[136]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I39_Y : - XA1A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N195, Y => N265); - - lpp_waveform_1 : lpp_waveform - port map(status_full_ack(3) => status_full_ack(3), - status_full_ack(2) => status_full_ack(2), - status_full_ack(1) => status_full_ack(1), - status_full_ack(0) => status_full_ack(0), hburst(2) => - hburst(2), hburst(1) => hburst(1), hburst(0) => hburst(0), - htrans(1) => htrans(1), htrans(0) => htrans(0), - iosn_2(93) => iosn_2(93), hresp(0) => hresp(0), - iosn_1(93) => iosn_1(93), nhmaster_1_i(0) => - nhmaster_1_i(0), hsize(1) => hsize(1), hsize(0) => - hsize(0), hmaster_0(1) => hmaster_0(1), haddr(31) => - haddr(31), haddr(30) => haddr(30), haddr(29) => haddr(29), - haddr(28) => haddr(28), haddr(27) => haddr(27), haddr(26) - => haddr(26), haddr(25) => haddr(25), haddr(24) => - haddr(24), haddr(23) => haddr(23), haddr(22) => haddr(22), - haddr(21) => haddr(21), haddr(20) => haddr(20), haddr(19) - => haddr(19), haddr(18) => haddr(18), haddr(17) => - haddr(17), haddr(16) => haddr(16), haddr(15) => haddr(15), - haddr(14) => haddr(14), haddr(13) => haddr(13), haddr(12) - => haddr(12), haddr(11) => haddr(11), haddr(10) => - haddr(10), haddr(9) => haddr(9), haddr(8) => haddr(8), - haddr(7) => haddr(7), haddr(6) => haddr(6), haddr(5) => - haddr(5), haddr(4) => haddr(4), haddr(3) => haddr(3), - haddr(2) => haddr(2), haddr(1) => haddr(1), haddr(0) => - haddr(0), bco_msb_1(1) => bco_msb_1(1), - hmaster_0_0_RNIFCVH1_0(1) => hmaster_0_0_RNIFCVH1_0(1), - hgrant(3) => hgrant(3), iosn_0(93) => iosn_0(93), - bco_msb_1_m(1) => bco_msb_1_m(1), nhmaster_1_iv_0(1) => - nhmaster_1_iv_0(1), l1_0_m(1) => l1_0_m(1), - nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(3) => status_full_err(3), - status_full_err(2) => status_full_err(2), - status_full_err(1) => status_full_err(1), - status_full_err(0) => status_full_err(0), status_full(3) - => status_full(3), status_full(2) => status_full(2), - status_full(1) => status_full(1), status_full(0) => - status_full(0), addr_data_f3(31) => addr_data_f3(31), - addr_data_f3(30) => addr_data_f3(30), addr_data_f3(29) - => addr_data_f3(29), addr_data_f3(28) => - addr_data_f3(28), addr_data_f3(27) => addr_data_f3(27), - addr_data_f3(26) => addr_data_f3(26), addr_data_f3(25) - => addr_data_f3(25), addr_data_f3(24) => - addr_data_f3(24), addr_data_f3(23) => addr_data_f3(23), - addr_data_f3(22) => addr_data_f3(22), addr_data_f3(21) - => addr_data_f3(21), addr_data_f3(20) => - addr_data_f3(20), addr_data_f3(19) => addr_data_f3(19), - addr_data_f3(18) => addr_data_f3(18), addr_data_f3(17) - => addr_data_f3(17), addr_data_f3(16) => - addr_data_f3(16), addr_data_f3(15) => addr_data_f3(15), - addr_data_f3(14) => addr_data_f3(14), addr_data_f3(13) - => addr_data_f3(13), addr_data_f3(12) => - addr_data_f3(12), addr_data_f3(11) => addr_data_f3(11), - addr_data_f3(10) => addr_data_f3(10), addr_data_f3(9) => - addr_data_f3(9), addr_data_f3(8) => addr_data_f3(8), - addr_data_f3(7) => addr_data_f3(7), addr_data_f3(6) => - addr_data_f3(6), addr_data_f3(5) => addr_data_f3(5), - addr_data_f3(4) => addr_data_f3(4), addr_data_f3(3) => - addr_data_f3(3), addr_data_f3(2) => addr_data_f3(2), - addr_data_f3(1) => addr_data_f3(1), addr_data_f3(0) => - addr_data_f3(0), addr_data_f2(31) => addr_data_f2(31), - addr_data_f2(30) => addr_data_f2(30), addr_data_f2(29) - => addr_data_f2(29), addr_data_f2(28) => - addr_data_f2(28), addr_data_f2(27) => addr_data_f2(27), - addr_data_f2(26) => addr_data_f2(26), addr_data_f2(25) - => addr_data_f2(25), addr_data_f2(24) => - addr_data_f2(24), addr_data_f2(23) => addr_data_f2(23), - addr_data_f2(22) => addr_data_f2(22), addr_data_f2(21) - => addr_data_f2(21), addr_data_f2(20) => - addr_data_f2(20), addr_data_f2(19) => addr_data_f2(19), - addr_data_f2(18) => addr_data_f2(18), addr_data_f2(17) - => addr_data_f2(17), addr_data_f2(16) => - addr_data_f2(16), addr_data_f2(15) => addr_data_f2(15), - addr_data_f2(14) => addr_data_f2(14), addr_data_f2(13) - => addr_data_f2(13), addr_data_f2(12) => - addr_data_f2(12), addr_data_f2(11) => addr_data_f2(11), - addr_data_f2(10) => addr_data_f2(10), addr_data_f2(9) => - addr_data_f2(9), addr_data_f2(8) => addr_data_f2(8), - addr_data_f2(7) => addr_data_f2(7), addr_data_f2(6) => - addr_data_f2(6), addr_data_f2(5) => addr_data_f2(5), - addr_data_f2(4) => addr_data_f2(4), addr_data_f2(3) => - addr_data_f2(3), addr_data_f2(2) => addr_data_f2(2), - addr_data_f2(1) => addr_data_f2(1), addr_data_f2(0) => - addr_data_f2(0), addr_data_f1(31) => addr_data_f1(31), - addr_data_f1(30) => addr_data_f1(30), addr_data_f1(29) - => addr_data_f1(29), addr_data_f1(28) => - addr_data_f1(28), addr_data_f1(27) => addr_data_f1(27), - addr_data_f1(26) => addr_data_f1(26), addr_data_f1(25) - => addr_data_f1(25), addr_data_f1(24) => - addr_data_f1(24), addr_data_f1(23) => addr_data_f1(23), - addr_data_f1(22) => addr_data_f1(22), addr_data_f1(21) - => addr_data_f1(21), addr_data_f1(20) => - addr_data_f1(20), addr_data_f1(19) => addr_data_f1(19), - addr_data_f1(18) => addr_data_f1(18), addr_data_f1(17) - => addr_data_f1(17), addr_data_f1(16) => - addr_data_f1(16), addr_data_f1(15) => addr_data_f1(15), - addr_data_f1(14) => addr_data_f1(14), addr_data_f1(13) - => addr_data_f1(13), addr_data_f1(12) => - addr_data_f1(12), addr_data_f1(11) => addr_data_f1(11), - addr_data_f1(10) => addr_data_f1(10), addr_data_f1(9) => - addr_data_f1(9), addr_data_f1(8) => addr_data_f1(8), - addr_data_f1(7) => addr_data_f1(7), addr_data_f1(6) => - addr_data_f1(6), addr_data_f1(5) => addr_data_f1(5), - addr_data_f1(4) => addr_data_f1(4), addr_data_f1(3) => - addr_data_f1(3), addr_data_f1(2) => addr_data_f1(2), - addr_data_f1(1) => addr_data_f1(1), addr_data_f1(0) => - addr_data_f1(0), addr_data_f0(31) => addr_data_f0(31), - addr_data_f0(30) => addr_data_f0(30), addr_data_f0(29) - => addr_data_f0(29), addr_data_f0(28) => - addr_data_f0(28), addr_data_f0(27) => addr_data_f0(27), - addr_data_f0(26) => addr_data_f0(26), addr_data_f0(25) - => addr_data_f0(25), addr_data_f0(24) => - addr_data_f0(24), addr_data_f0(23) => addr_data_f0(23), - addr_data_f0(22) => addr_data_f0(22), addr_data_f0(21) - => addr_data_f0(21), addr_data_f0(20) => - addr_data_f0(20), addr_data_f0(19) => addr_data_f0(19), - addr_data_f0(18) => addr_data_f0(18), addr_data_f0(17) - => addr_data_f0(17), addr_data_f0(16) => - addr_data_f0(16), addr_data_f0(15) => addr_data_f0(15), - addr_data_f0(14) => addr_data_f0(14), addr_data_f0(13) - => addr_data_f0(13), addr_data_f0(12) => - addr_data_f0(12), addr_data_f0(11) => addr_data_f0(11), - addr_data_f0(10) => addr_data_f0(10), addr_data_f0(9) => - addr_data_f0(9), addr_data_f0(8) => addr_data_f0(8), - addr_data_f0(7) => addr_data_f0(7), addr_data_f0(6) => - addr_data_f0(6), addr_data_f0(5) => addr_data_f0(5), - addr_data_f0(4) => addr_data_f0(4), addr_data_f0(3) => - addr_data_f0(3), addr_data_f0(2) => addr_data_f0(2), - addr_data_f0(1) => addr_data_f0(1), addr_data_f0(0) => - addr_data_f0(0), hwdata(31) => hwdata(31), hwdata(30) => - hwdata(30), hwdata(29) => hwdata(29), hwdata(28) => - hwdata(28), hwdata(27) => hwdata(27), hwdata(26) => - hwdata(26), hwdata(25) => hwdata(25), hwdata(24) => - hwdata(24), hwdata(23) => hwdata(23), hwdata(22) => - hwdata(22), hwdata(21) => hwdata(21), hwdata(20) => - hwdata(20), hwdata(19) => hwdata(19), hwdata(18) => - hwdata(18), hwdata(17) => hwdata(17), hwdata(16) => - hwdata(16), hwdata(15) => hwdata(15), hwdata(14) => - hwdata(14), hwdata(13) => hwdata(13), hwdata(12) => - hwdata(12), hwdata(11) => hwdata(11), hwdata(10) => - hwdata(10), hwdata(9) => hwdata(9), hwdata(8) => - hwdata(8), hwdata(7) => hwdata(7), hwdata(6) => hwdata(6), - hwdata(5) => hwdata(5), hwdata(4) => hwdata(4), hwdata(3) - => hwdata(3), hwdata(2) => hwdata(2), hwdata(1) => - hwdata(1), hwdata(0) => hwdata(0), status_new_err(3) => - status_new_err(3), status_new_err(2) => status_new_err(2), - status_new_err(1) => status_new_err(1), status_new_err(0) - => status_new_err(0), sample_f3_wdata(95) => - \sample_f3_wdata[95]\, sample_f3_wdata(94) => - \sample_f3_wdata[94]\, sample_f3_wdata(93) => - \sample_f3_wdata[93]\, sample_f3_wdata(92) => - \sample_f3_wdata[92]\, sample_f3_wdata(91) => - \sample_f3_wdata[91]\, sample_f3_wdata(90) => - \sample_f3_wdata[90]\, sample_f3_wdata(89) => - \sample_f3_wdata[89]\, sample_f3_wdata(88) => - \sample_f3_wdata[88]\, sample_f3_wdata(87) => - \sample_f3_wdata[87]\, sample_f3_wdata(86) => - \sample_f3_wdata[86]\, sample_f3_wdata(85) => - \sample_f3_wdata[85]\, sample_f3_wdata(84) => - \sample_f3_wdata[84]\, sample_f3_wdata(83) => - \sample_f3_wdata[83]\, sample_f3_wdata(82) => - \sample_f3_wdata[82]\, sample_f3_wdata(81) => - \sample_f3_wdata[81]\, sample_f3_wdata(80) => - \sample_f3_wdata[80]\, sample_f3_wdata(79) => - \sample_f3_wdata[79]\, sample_f3_wdata(78) => - \sample_f3_wdata[78]\, sample_f3_wdata(77) => - \sample_f3_wdata[77]\, sample_f3_wdata(76) => - \sample_f3_wdata[76]\, sample_f3_wdata(75) => - \sample_f3_wdata[75]\, sample_f3_wdata(74) => - \sample_f3_wdata[74]\, sample_f3_wdata(73) => - \sample_f3_wdata[73]\, sample_f3_wdata(72) => - \sample_f3_wdata[72]\, sample_f3_wdata(71) => - \sample_f3_wdata[71]\, sample_f3_wdata(70) => - \sample_f3_wdata[70]\, sample_f3_wdata(69) => - \sample_f3_wdata[69]\, sample_f3_wdata(68) => - \sample_f3_wdata[68]\, sample_f3_wdata(67) => - \sample_f3_wdata[67]\, sample_f3_wdata(66) => - \sample_f3_wdata[66]\, sample_f3_wdata(65) => - \sample_f3_wdata[65]\, sample_f3_wdata(64) => - \sample_f3_wdata[64]\, sample_f3_wdata(63) => - \sample_f3_wdata[63]\, sample_f3_wdata(62) => - \sample_f3_wdata[62]\, sample_f3_wdata(61) => - \sample_f3_wdata[61]\, sample_f3_wdata(60) => - \sample_f3_wdata[60]\, sample_f3_wdata(59) => - \sample_f3_wdata[59]\, sample_f3_wdata(58) => - \sample_f3_wdata[58]\, sample_f3_wdata(57) => - \sample_f3_wdata[57]\, sample_f3_wdata(56) => - \sample_f3_wdata[56]\, sample_f3_wdata(55) => - \sample_f3_wdata[55]\, sample_f3_wdata(54) => - \sample_f3_wdata[54]\, sample_f3_wdata(53) => - \sample_f3_wdata[53]\, sample_f3_wdata(52) => - \sample_f3_wdata[52]\, sample_f3_wdata(51) => - \sample_f3_wdata[51]\, sample_f3_wdata(50) => - \sample_f3_wdata[50]\, sample_f3_wdata(49) => - \sample_f3_wdata[49]\, sample_f3_wdata(48) => - \sample_f3_wdata[48]\, sample_f3_wdata(47) => - \sample_f3_wdata[47]\, sample_f3_wdata(46) => - \sample_f3_wdata[46]\, sample_f3_wdata(45) => - \sample_f3_wdata[45]\, sample_f3_wdata(44) => - \sample_f3_wdata[44]\, sample_f3_wdata(43) => - \sample_f3_wdata[43]\, sample_f3_wdata(42) => - \sample_f3_wdata[42]\, sample_f3_wdata(41) => - \sample_f3_wdata[41]\, sample_f3_wdata(40) => - \sample_f3_wdata[40]\, sample_f3_wdata(39) => - \sample_f3_wdata[39]\, sample_f3_wdata(38) => - \sample_f3_wdata[38]\, sample_f3_wdata(37) => - \sample_f3_wdata[37]\, sample_f3_wdata(36) => - \sample_f3_wdata[36]\, sample_f3_wdata(35) => - \sample_f3_wdata[35]\, sample_f3_wdata(34) => - \sample_f3_wdata[34]\, sample_f3_wdata(33) => - \sample_f3_wdata[33]\, sample_f3_wdata(32) => - \sample_f3_wdata[32]\, sample_f3_wdata(31) => - \sample_f3_wdata[31]\, sample_f3_wdata(30) => - \sample_f3_wdata[30]\, sample_f3_wdata(29) => - \sample_f3_wdata[29]\, sample_f3_wdata(28) => - \sample_f3_wdata[28]\, sample_f3_wdata(27) => - \sample_f3_wdata[27]\, sample_f3_wdata(26) => - \sample_f3_wdata[26]\, sample_f3_wdata(25) => - \sample_f3_wdata[25]\, sample_f3_wdata(24) => - \sample_f3_wdata[24]\, sample_f3_wdata(23) => - \sample_f3_wdata[23]\, sample_f3_wdata(22) => - \sample_f3_wdata[22]\, sample_f3_wdata(21) => - \sample_f3_wdata[21]\, sample_f3_wdata(20) => - \sample_f3_wdata[20]\, sample_f3_wdata(19) => - \sample_f3_wdata[19]\, sample_f3_wdata(18) => - \sample_f3_wdata[18]\, sample_f3_wdata(17) => - \sample_f3_wdata[17]\, sample_f3_wdata(16) => - \sample_f3_wdata[16]\, sample_f3_wdata(15) => - \sample_f3_wdata[15]\, sample_f3_wdata(14) => - \sample_f3_wdata[14]\, sample_f3_wdata(13) => - \sample_f3_wdata[13]\, sample_f3_wdata(12) => - \sample_f3_wdata[12]\, sample_f3_wdata(11) => - \sample_f3_wdata[11]\, sample_f3_wdata(10) => - \sample_f3_wdata[10]\, sample_f3_wdata(9) => - \sample_f3_wdata[9]\, sample_f3_wdata(8) => - \sample_f3_wdata[8]\, sample_f3_wdata(7) => - \sample_f3_wdata[7]\, sample_f3_wdata(6) => - \sample_f3_wdata[6]\, sample_f3_wdata(5) => - \sample_f3_wdata[5]\, sample_f3_wdata(4) => - \sample_f3_wdata[4]\, sample_f3_wdata(3) => - \sample_f3_wdata[3]\, sample_f3_wdata(2) => - \sample_f3_wdata[2]\, sample_f3_wdata(1) => - \sample_f3_wdata[1]\, sample_f3_wdata(0) => - \sample_f3_wdata[0]\, sample_f2_wdata(95) => - \sample_f2_wdata[95]\, sample_f2_wdata(94) => - \sample_f2_wdata[94]\, sample_f2_wdata(93) => - \sample_f2_wdata[93]\, sample_f2_wdata(92) => - \sample_f2_wdata[92]\, sample_f2_wdata(91) => - \sample_f2_wdata[91]\, sample_f2_wdata(90) => - \sample_f2_wdata[90]\, sample_f2_wdata(89) => - \sample_f2_wdata[89]\, sample_f2_wdata(88) => - \sample_f2_wdata[88]\, sample_f2_wdata(87) => - \sample_f2_wdata[87]\, sample_f2_wdata(86) => - \sample_f2_wdata[86]\, sample_f2_wdata(85) => - \sample_f2_wdata[85]\, sample_f2_wdata(84) => - \sample_f2_wdata[84]\, sample_f2_wdata(83) => - \sample_f2_wdata[83]\, sample_f2_wdata(82) => - \sample_f2_wdata[82]\, sample_f2_wdata(81) => - \sample_f2_wdata[81]\, sample_f2_wdata(80) => - \sample_f2_wdata[80]\, sample_f2_wdata(79) => - \sample_f2_wdata[79]\, sample_f2_wdata(78) => - \sample_f2_wdata[78]\, sample_f2_wdata(77) => - \sample_f2_wdata[77]\, sample_f2_wdata(76) => - \sample_f2_wdata[76]\, sample_f2_wdata(75) => - \sample_f2_wdata[75]\, sample_f2_wdata(74) => - \sample_f2_wdata[74]\, sample_f2_wdata(73) => - \sample_f2_wdata[73]\, sample_f2_wdata(72) => - \sample_f2_wdata[72]\, sample_f2_wdata(71) => - \sample_f2_wdata[71]\, sample_f2_wdata(70) => - \sample_f2_wdata[70]\, sample_f2_wdata(69) => - \sample_f2_wdata[69]\, sample_f2_wdata(68) => - \sample_f2_wdata[68]\, sample_f2_wdata(67) => - \sample_f2_wdata[67]\, sample_f2_wdata(66) => - \sample_f2_wdata[66]\, sample_f2_wdata(65) => - \sample_f2_wdata[65]\, sample_f2_wdata(64) => - \sample_f2_wdata[64]\, sample_f2_wdata(63) => - \sample_f2_wdata[63]\, sample_f2_wdata(62) => - \sample_f2_wdata[62]\, sample_f2_wdata(61) => - \sample_f2_wdata[61]\, sample_f2_wdata(60) => - \sample_f2_wdata[60]\, sample_f2_wdata(59) => - \sample_f2_wdata[59]\, sample_f2_wdata(58) => - \sample_f2_wdata[58]\, sample_f2_wdata(57) => - \sample_f2_wdata[57]\, sample_f2_wdata(56) => - \sample_f2_wdata[56]\, sample_f2_wdata(55) => - \sample_f2_wdata[55]\, sample_f2_wdata(54) => - \sample_f2_wdata[54]\, sample_f2_wdata(53) => - \sample_f2_wdata[53]\, sample_f2_wdata(52) => - \sample_f2_wdata[52]\, sample_f2_wdata(51) => - \sample_f2_wdata[51]\, sample_f2_wdata(50) => - \sample_f2_wdata[50]\, sample_f2_wdata(49) => - \sample_f2_wdata[49]\, sample_f2_wdata(48) => - \sample_f2_wdata[48]\, sample_f2_wdata(47) => - \sample_f2_wdata[47]\, sample_f2_wdata(46) => - \sample_f2_wdata[46]\, sample_f2_wdata(45) => - \sample_f2_wdata[45]\, sample_f2_wdata(44) => - \sample_f2_wdata[44]\, sample_f2_wdata(43) => - \sample_f2_wdata[43]\, sample_f2_wdata(42) => - \sample_f2_wdata[42]\, sample_f2_wdata(41) => - \sample_f2_wdata[41]\, sample_f2_wdata(40) => - \sample_f2_wdata[40]\, sample_f2_wdata(39) => - \sample_f2_wdata[39]\, sample_f2_wdata(38) => - \sample_f2_wdata[38]\, sample_f2_wdata(37) => - \sample_f2_wdata[37]\, sample_f2_wdata(36) => - \sample_f2_wdata[36]\, sample_f2_wdata(35) => - \sample_f2_wdata[35]\, sample_f2_wdata(34) => - \sample_f2_wdata[34]\, sample_f2_wdata(33) => - \sample_f2_wdata[33]\, sample_f2_wdata(32) => - \sample_f2_wdata[32]\, sample_f2_wdata(31) => - \sample_f2_wdata[31]\, sample_f2_wdata(30) => - \sample_f2_wdata[30]\, sample_f2_wdata(29) => - \sample_f2_wdata[29]\, sample_f2_wdata(28) => - \sample_f2_wdata[28]\, sample_f2_wdata(27) => - \sample_f2_wdata[27]\, sample_f2_wdata(26) => - \sample_f2_wdata[26]\, sample_f2_wdata(25) => - \sample_f2_wdata[25]\, sample_f2_wdata(24) => - \sample_f2_wdata[24]\, sample_f2_wdata(23) => - \sample_f2_wdata[23]\, sample_f2_wdata(22) => - \sample_f2_wdata[22]\, sample_f2_wdata(21) => - \sample_f2_wdata[21]\, sample_f2_wdata(20) => - \sample_f2_wdata[20]\, sample_f2_wdata(19) => - \sample_f2_wdata[19]\, sample_f2_wdata(18) => - \sample_f2_wdata[18]\, sample_f2_wdata(17) => - \sample_f2_wdata[17]\, sample_f2_wdata(16) => - \sample_f2_wdata[16]\, sample_f2_wdata(15) => - \sample_f2_wdata[15]\, sample_f2_wdata(14) => - \sample_f2_wdata[14]\, sample_f2_wdata(13) => - \sample_f2_wdata[13]\, sample_f2_wdata(12) => - \sample_f2_wdata[12]\, sample_f2_wdata(11) => - \sample_f2_wdata[11]\, sample_f2_wdata(10) => - \sample_f2_wdata[10]\, sample_f2_wdata(9) => - \sample_f2_wdata[9]\, sample_f2_wdata(8) => - \sample_f2_wdata[8]\, sample_f2_wdata(7) => - \sample_f2_wdata[7]\, sample_f2_wdata(6) => - \sample_f2_wdata[6]\, sample_f2_wdata(5) => - \sample_f2_wdata[5]\, sample_f2_wdata(4) => - \sample_f2_wdata[4]\, sample_f2_wdata(3) => - \sample_f2_wdata[3]\, sample_f2_wdata(2) => - \sample_f2_wdata[2]\, sample_f2_wdata(1) => - \sample_f2_wdata[1]\, sample_f2_wdata(0) => - \sample_f2_wdata[0]\, sample_f1_15 => \sample_f1[63]\, - sample_f1_47 => \sample_f1[95]\, sample_f1_14 => - \sample_f1[62]\, sample_f1_46 => \sample_f1[94]\, - sample_f1_13 => \sample_f1[61]\, sample_f1_45 => - \sample_f1[93]\, sample_f1_12 => \sample_f1[60]\, - sample_f1_44 => \sample_f1[92]\, sample_f1_60 => - \sample_f1[108]\, sample_f1_59 => \sample_f1[107]\, - sample_f1_58 => \sample_f1[106]\, sample_f1_57 => - \sample_f1[105]\, sample_f1_56 => \sample_f1[104]\, - sample_f1_55 => \sample_f1[103]\, sample_f1_54 => - \sample_f1[102]\, sample_f1_53 => \sample_f1[101]\, - sample_f1_52 => \sample_f1[100]\, sample_f1_51 => - \sample_f1[99]\, sample_f1_50 => \sample_f1[98]\, - sample_f1_49 => \sample_f1[97]\, sample_f1_48 => - \sample_f1[96]\, sample_f1_4 => \sample_f1[52]\, - sample_f1_36 => \sample_f1[84]\, sample_f1_3 => - \sample_f1[51]\, sample_f1_35 => \sample_f1[83]\, - sample_f1_2 => \sample_f1[50]\, sample_f1_34 => - \sample_f1[82]\, sample_f1_1 => \sample_f1[49]\, - sample_f1_33 => \sample_f1[81]\, sample_f1_0 => - \sample_f1[48]\, sample_f1_32 => \sample_f1[80]\, - sample_f1_63 => \sample_f1[111]\, sample_f1_62 => - \sample_f1[110]\, sample_f1_61 => \sample_f1[109]\, - sample_f1_11 => \sample_f1[59]\, sample_f1_43 => - \sample_f1[91]\, sample_f1_10 => \sample_f1[58]\, - sample_f1_42 => \sample_f1[90]\, sample_f1_9 => - \sample_f1[57]\, sample_f1_41 => \sample_f1[89]\, - sample_f1_8 => \sample_f1[56]\, sample_f1_40 => - \sample_f1[88]\, sample_f1_7 => \sample_f1[55]\, - sample_f1_39 => \sample_f1[87]\, sample_f1_6 => - \sample_f1[54]\, sample_f1_38 => \sample_f1[86]\, - sample_f1_5 => \sample_f1[53]\, sample_f1_37 => - \sample_f1[85]\, sample_f1_wdata_0 => - \sample_f1_wdata[0]\, sample_f1_wdata_1 => - \sample_f1_wdata[1]\, sample_f1_wdata_2 => - \sample_f1_wdata[2]\, sample_f1_wdata_3 => - \sample_f1_wdata[3]\, sample_f1_wdata_4 => - \sample_f1_wdata[4]\, sample_f1_wdata_5 => - \sample_f1_wdata[5]\, sample_f1_wdata_6 => - \sample_f1_wdata[6]\, sample_f1_wdata_7 => - \sample_f1_wdata[7]\, sample_f1_wdata_8 => - \sample_f1_wdata[8]\, sample_f1_wdata_9 => - \sample_f1_wdata[9]\, sample_f1_wdata_10 => - \sample_f1_wdata[10]\, sample_f1_wdata_11 => - \sample_f1_wdata[11]\, sample_f1_wdata_12 => - \sample_f1_wdata[12]\, sample_f1_wdata_13 => - \sample_f1_wdata[13]\, sample_f1_wdata_14 => - \sample_f1_wdata[14]\, sample_f1_wdata_15 => - \sample_f1_wdata[15]\, sample_f1_wdata_48 => - \sample_f1_wdata[48]\, sample_f1_wdata_49 => - \sample_f1_wdata[49]\, sample_f1_wdata_50 => - \sample_f1_wdata[50]\, sample_f1_wdata_51 => - \sample_f1_wdata[51]\, sample_f1_wdata_52 => - \sample_f1_wdata[52]\, sample_f1_wdata_53 => - \sample_f1_wdata[53]\, sample_f1_wdata_54 => - \sample_f1_wdata[54]\, sample_f1_wdata_55 => - \sample_f1_wdata[55]\, sample_f1_wdata_56 => - \sample_f1_wdata[56]\, sample_f1_wdata_57 => - \sample_f1_wdata[57]\, sample_f1_wdata_58 => - \sample_f1_wdata[58]\, sample_f1_wdata_59 => - \sample_f1_wdata[59]\, sample_f1_wdata_60 => - \sample_f1_wdata[60]\, sample_f1_wdata_61 => - \sample_f1_wdata[61]\, sample_f1_wdata_62 => - \sample_f1_wdata[62]\, sample_f1_wdata_63 => - \sample_f1_wdata[63]\, sample_f1_wdata_64 => - \sample_f1_wdata[64]\, sample_f1_wdata_65 => - \sample_f1_wdata[65]\, sample_f1_wdata_66 => - \sample_f1_wdata[66]\, sample_f1_wdata_67 => - \sample_f1_wdata[67]\, sample_f1_wdata_68 => - \sample_f1_wdata[68]\, sample_f1_wdata_69 => - \sample_f1_wdata[69]\, sample_f1_wdata_70 => - \sample_f1_wdata[70]\, sample_f1_wdata_71 => - \sample_f1_wdata[71]\, sample_f1_wdata_72 => - \sample_f1_wdata[72]\, sample_f1_wdata_73 => - \sample_f1_wdata[73]\, sample_f1_wdata_74 => - \sample_f1_wdata[74]\, sample_f1_wdata_75 => - \sample_f1_wdata[75]\, sample_f1_wdata_76 => - \sample_f1_wdata[76]\, sample_f1_wdata_77 => - \sample_f1_wdata[77]\, sample_f1_wdata_78 => - \sample_f1_wdata[78]\, sample_f1_wdata_79 => - \sample_f1_wdata[79]\, sample_f1_wdata_80 => - \sample_f1_wdata[80]\, sample_f1_wdata_81 => - \sample_f1_wdata[81]\, sample_f1_wdata_82 => - \sample_f1_wdata[82]\, sample_f1_wdata_83 => - \sample_f1_wdata[83]\, sample_f1_wdata_84 => - \sample_f1_wdata[84]\, sample_f1_wdata_85 => - \sample_f1_wdata[85]\, sample_f1_wdata_86 => - \sample_f1_wdata[86]\, sample_f1_wdata_87 => - \sample_f1_wdata[87]\, sample_f1_wdata_88 => - \sample_f1_wdata[88]\, sample_f1_wdata_89 => - \sample_f1_wdata[89]\, sample_f1_wdata_90 => - \sample_f1_wdata[90]\, sample_f1_wdata_91 => - \sample_f1_wdata[91]\, sample_f1_wdata_92 => - \sample_f1_wdata[92]\, sample_f1_wdata_93 => - \sample_f1_wdata[93]\, sample_f1_wdata_94 => - \sample_f1_wdata[94]\, sample_f1_wdata_95 => - \sample_f1_wdata[95]\, sample_f0_15 => \sample_f0[63]\, - sample_f0_47 => \sample_f0[95]\, sample_f0_14 => - \sample_f0[62]\, sample_f0_46 => \sample_f0[94]\, - sample_f0_13 => \sample_f0[61]\, sample_f0_45 => - \sample_f0[93]\, sample_f0_12 => \sample_f0[60]\, - sample_f0_44 => \sample_f0[92]\, sample_f0_60 => - \sample_f0[108]\, sample_f0_59 => \sample_f0[107]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_57 => - \sample_f0[105]\, sample_f0_56 => \sample_f0[104]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_54 => - \sample_f0[102]\, sample_f0_53 => \sample_f0[101]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_51 => - \sample_f0[99]\, sample_f0_50 => \sample_f0[98]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_48 => - \sample_f0[96]\, sample_f0_4 => \sample_f0[52]\, - sample_f0_36 => \sample_f0[84]\, sample_f0_3 => - \sample_f0[51]\, sample_f0_35 => \sample_f0[83]\, - sample_f0_2 => \sample_f0[50]\, sample_f0_34 => - \sample_f0[82]\, sample_f0_1 => \sample_f0[49]\, - sample_f0_33 => \sample_f0[81]\, sample_f0_0 => - \sample_f0[48]\, sample_f0_32 => \sample_f0[80]\, - sample_f0_63 => \sample_f0[111]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_61 => \sample_f0[109]\, - sample_f0_11 => \sample_f0[59]\, sample_f0_43 => - \sample_f0[91]\, sample_f0_10 => \sample_f0[58]\, - sample_f0_42 => \sample_f0[90]\, sample_f0_9 => - \sample_f0[57]\, sample_f0_41 => \sample_f0[89]\, - sample_f0_8 => \sample_f0[56]\, sample_f0_40 => - \sample_f0[88]\, sample_f0_7 => \sample_f0[55]\, - sample_f0_39 => \sample_f0[87]\, sample_f0_6 => - \sample_f0[54]\, sample_f0_38 => \sample_f0[86]\, - sample_f0_5 => \sample_f0[53]\, sample_f0_37 => - \sample_f0[85]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, coarse_time(0) => coarse_time(0), - delta_snapshot(15) => delta_snapshot(15), - delta_snapshot(14) => delta_snapshot(14), - delta_snapshot(13) => delta_snapshot(13), - delta_snapshot(12) => delta_snapshot(12), - delta_snapshot(11) => delta_snapshot(11), - delta_snapshot(10) => delta_snapshot(10), - delta_snapshot(9) => delta_snapshot(9), delta_snapshot(8) - => delta_snapshot(8), delta_snapshot(7) => - delta_snapshot(7), delta_snapshot(6) => delta_snapshot(6), - delta_snapshot(5) => delta_snapshot(5), delta_snapshot(4) - => delta_snapshot(4), delta_snapshot(3) => - delta_snapshot(3), delta_snapshot(2) => delta_snapshot(2), - delta_snapshot(1) => delta_snapshot(1), delta_snapshot(0) - => delta_snapshot(0), delta_f2_f1(9) => delta_f2_f1(9), - delta_f2_f1(8) => delta_f2_f1(8), delta_f2_f1(7) => - delta_f2_f1(7), delta_f2_f1(6) => delta_f2_f1(6), - delta_f2_f1(5) => delta_f2_f1(5), delta_f2_f1(4) => - delta_f2_f1(4), delta_f2_f1(3) => delta_f2_f1(3), - delta_f2_f1(2) => delta_f2_f1(2), delta_f2_f1(1) => - delta_f2_f1(1), delta_f2_f1(0) => delta_f2_f1(0), - delta_f2_f0(9) => delta_f2_f0(9), delta_f2_f0(8) => - delta_f2_f0(8), delta_f2_f0(7) => delta_f2_f0(7), - delta_f2_f0(6) => delta_f2_f0(6), delta_f2_f0(5) => - delta_f2_f0(5), delta_f2_f0(4) => delta_f2_f0(4), - delta_f2_f0(3) => delta_f2_f0(3), delta_f2_f0(2) => - delta_f2_f0(2), delta_f2_f0(1) => delta_f2_f0(1), - delta_f2_f0(0) => delta_f2_f0(0), coarse_time_i(0) => - coarse_time_i(0), nb_snapshot_param(10) => - nb_snapshot_param(10), nb_snapshot_param(9) => - nb_snapshot_param(9), nb_snapshot_param(8) => - nb_snapshot_param(8), nb_snapshot_param(7) => - nb_snapshot_param(7), nb_snapshot_param(6) => - nb_snapshot_param(6), nb_snapshot_param(5) => - nb_snapshot_param(5), nb_snapshot_param(4) => - nb_snapshot_param(4), nb_snapshot_param(3) => - nb_snapshot_param(3), nb_snapshot_param(2) => - nb_snapshot_param(2), nb_snapshot_param(1) => - nb_snapshot_param(1), nb_snapshot_param(0) => - nb_snapshot_param(0), IdlePhase => IdlePhase, hwrite => - hwrite, un1_dmain_6 => un1_dmain_6, arb_1 => arb_1, - hbusreq_i_3 => hbusreq_i_3, Lock_RNIU86D => Lock_RNIU86D, - un1_nhmaster_0_sqmuxa_1 => un1_nhmaster_0_sqmuxa_1, - rstoutl_RNIGJKSJO => rstoutl_RNIGJKSJO, m19_0_N_15_i_0_li - => m19_0_N_15_i_0_li, m19_a0_6_i_0 => m19_a0_6_i_0, - m19_a1_6_i_0 => m19_a1_6_i_0, m26_m1_e => m26_m1_e, - sample_f3_val => sample_f3_val, enable_f3 => enable_f3, - burst_f2 => burst_f2, enable_f2 => enable_f2, - sample_f1_val_0 => sample_f1_val_0, burst_f1 => burst_f1, - enable_f1 => enable_f1, data_shaping_R1_0 => - data_shaping_R1_0, data_shaping_R1 => data_shaping_R1, - burst_f0 => burst_f0, enable_f0 => enable_f0, - data_shaping_R0_0 => data_shaping_R0_0, data_shaping_R0 - => data_shaping_R0, lclk_c => lclk_c, rstn => rstn, - sample_f0_val_0 => sample_f0_val_0, sample_f2_val => - sample_f2_val); - - Downsampling_f0 : Downsampling_8_16_4 - port map(sample_f0_0 => \sample_f0[48]\, sample_f0_1 => - \sample_f0[49]\, sample_f0_2 => \sample_f0[50]\, - sample_f0_3 => \sample_f0[51]\, sample_f0_4 => - \sample_f0[52]\, sample_f0_5 => \sample_f0[53]\, - sample_f0_6 => \sample_f0[54]\, sample_f0_7 => - \sample_f0[55]\, sample_f0_8 => \sample_f0[56]\, - sample_f0_9 => \sample_f0[57]\, sample_f0_10 => - \sample_f0[58]\, sample_f0_11 => \sample_f0[59]\, - sample_f0_12 => \sample_f0[60]\, sample_f0_13 => - \sample_f0[61]\, sample_f0_14 => \sample_f0[62]\, - sample_f0_15 => \sample_f0[63]\, sample_f0_32 => - \sample_f0[80]\, sample_f0_33 => \sample_f0[81]\, - sample_f0_34 => \sample_f0[82]\, sample_f0_35 => - \sample_f0[83]\, sample_f0_36 => \sample_f0[84]\, - sample_f0_37 => \sample_f0[85]\, sample_f0_38 => - \sample_f0[86]\, sample_f0_39 => \sample_f0[87]\, - sample_f0_40 => \sample_f0[88]\, sample_f0_41 => - \sample_f0[89]\, sample_f0_42 => \sample_f0[90]\, - sample_f0_43 => \sample_f0[91]\, sample_f0_44 => - \sample_f0[92]\, sample_f0_45 => \sample_f0[93]\, - sample_f0_46 => \sample_f0[94]\, sample_f0_47 => - \sample_f0[95]\, sample_f0_48 => \sample_f0[96]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_50 => - \sample_f0[98]\, sample_f0_51 => \sample_f0[99]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_53 => - \sample_f0[101]\, sample_f0_54 => \sample_f0[102]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_56 => - \sample_f0[104]\, sample_f0_57 => \sample_f0[105]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_59 => - \sample_f0[107]\, sample_f0_60 => \sample_f0[108]\, - sample_f0_61 => \sample_f0[109]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_63 => \sample_f0[111]\, - sample_data_shaping_out_0 => \sample_data_shaping_out[2]\, - sample_data_shaping_out_1 => \sample_data_shaping_out[3]\, - sample_data_shaping_out_2 => \sample_data_shaping_out[4]\, - sample_data_shaping_out_3 => \sample_data_shaping_out[5]\, - sample_data_shaping_out_4 => \sample_data_shaping_out[6]\, - sample_data_shaping_out_5 => \sample_data_shaping_out[7]\, - sample_data_shaping_out_6 => \sample_data_shaping_out[8]\, - sample_data_shaping_out_7 => \sample_data_shaping_out[9]\, - sample_data_shaping_out_8 => - \sample_data_shaping_out[10]\, sample_data_shaping_out_9 - => \sample_data_shaping_out[11]\, - sample_data_shaping_out_10 => - \sample_data_shaping_out[12]\, sample_data_shaping_out_11 - => \sample_data_shaping_out[13]\, - sample_data_shaping_out_12 => - \sample_data_shaping_out[14]\, sample_data_shaping_out_13 - => \sample_data_shaping_out[15]\, - sample_data_shaping_out_14 => - \sample_data_shaping_out[16]\, sample_data_shaping_out_15 - => \sample_data_shaping_out[17]\, - sample_data_shaping_out_18 => - \sample_data_shaping_out[20]\, sample_data_shaping_out_19 - => \sample_data_shaping_out[21]\, - sample_data_shaping_out_20 => - \sample_data_shaping_out[22]\, sample_data_shaping_out_21 - => \sample_data_shaping_out[23]\, - sample_data_shaping_out_22 => - \sample_data_shaping_out[24]\, sample_data_shaping_out_23 - => \sample_data_shaping_out[25]\, - sample_data_shaping_out_24 => - \sample_data_shaping_out[26]\, sample_data_shaping_out_25 - => \sample_data_shaping_out[27]\, - sample_data_shaping_out_26 => - \sample_data_shaping_out[28]\, sample_data_shaping_out_27 - => \sample_data_shaping_out[29]\, - sample_data_shaping_out_28 => - \sample_data_shaping_out[30]\, sample_data_shaping_out_29 - => \sample_data_shaping_out[31]\, - sample_data_shaping_out_30 => - \sample_data_shaping_out[32]\, sample_data_shaping_out_31 - => \sample_data_shaping_out[33]\, - sample_data_shaping_out_32 => - \sample_data_shaping_out[34]\, sample_data_shaping_out_33 - => \sample_data_shaping_out[35]\, - sample_data_shaping_out_36 => - \sample_data_shaping_out[38]\, sample_data_shaping_out_37 - => \sample_data_shaping_out[39]\, - sample_data_shaping_out_38 => - \sample_data_shaping_out[40]\, sample_data_shaping_out_39 - => \sample_data_shaping_out[41]\, - sample_data_shaping_out_40 => - \sample_data_shaping_out[42]\, sample_data_shaping_out_41 - => \sample_data_shaping_out[43]\, - sample_data_shaping_out_42 => - \sample_data_shaping_out[44]\, sample_data_shaping_out_43 - => \sample_data_shaping_out[45]\, - sample_data_shaping_out_44 => - \sample_data_shaping_out[46]\, sample_data_shaping_out_45 - => \sample_data_shaping_out[47]\, - sample_data_shaping_out_46 => - \sample_data_shaping_out[48]\, sample_data_shaping_out_47 - => \sample_data_shaping_out[49]\, - sample_data_shaping_out_48 => - \sample_data_shaping_out[50]\, sample_data_shaping_out_49 - => \sample_data_shaping_out[51]\, - sample_data_shaping_out_50 => - \sample_data_shaping_out[52]\, sample_data_shaping_out_51 - => \sample_data_shaping_out[53]\, - sample_data_shaping_out_54 => - \sample_data_shaping_out[56]\, sample_data_shaping_out_55 - => \sample_data_shaping_out[57]\, - sample_data_shaping_out_56 => - \sample_data_shaping_out[58]\, sample_data_shaping_out_57 - => \sample_data_shaping_out[59]\, - sample_data_shaping_out_58 => - \sample_data_shaping_out[60]\, sample_data_shaping_out_59 - => \sample_data_shaping_out[61]\, - sample_data_shaping_out_60 => - \sample_data_shaping_out[62]\, sample_data_shaping_out_61 - => \sample_data_shaping_out[63]\, - sample_data_shaping_out_62 => - \sample_data_shaping_out[64]\, sample_data_shaping_out_63 - => \sample_data_shaping_out[65]\, - sample_data_shaping_out_64 => - \sample_data_shaping_out[66]\, sample_data_shaping_out_65 - => \sample_data_shaping_out[67]\, - sample_data_shaping_out_66 => - \sample_data_shaping_out[68]\, sample_data_shaping_out_67 - => \sample_data_shaping_out[69]\, - sample_data_shaping_out_68 => - \sample_data_shaping_out[70]\, sample_data_shaping_out_69 - => \sample_data_shaping_out[71]\, - sample_data_shaping_out_90 => - \sample_data_shaping_out[92]\, sample_data_shaping_out_91 - => \sample_data_shaping_out[93]\, - sample_data_shaping_out_92 => - \sample_data_shaping_out[94]\, sample_data_shaping_out_93 - => \sample_data_shaping_out[95]\, - sample_data_shaping_out_94 => - \sample_data_shaping_out[96]\, sample_data_shaping_out_95 - => \sample_data_shaping_out[97]\, - sample_data_shaping_out_96 => - \sample_data_shaping_out[98]\, sample_data_shaping_out_97 - => \sample_data_shaping_out[99]\, - sample_data_shaping_out_98 => - \sample_data_shaping_out[100]\, - sample_data_shaping_out_99 => - \sample_data_shaping_out[101]\, - sample_data_shaping_out_100 => - \sample_data_shaping_out[102]\, - sample_data_shaping_out_101 => - \sample_data_shaping_out[103]\, - sample_data_shaping_out_102 => - \sample_data_shaping_out[104]\, - sample_data_shaping_out_103 => - \sample_data_shaping_out[105]\, - sample_data_shaping_out_104 => - \sample_data_shaping_out[106]\, - sample_data_shaping_out_105 => - \sample_data_shaping_out[107]\, - sample_data_shaping_out_108 => - \sample_data_shaping_out[110]\, - sample_data_shaping_out_109 => - \sample_data_shaping_out[111]\, - sample_data_shaping_out_110 => - \sample_data_shaping_out[112]\, - sample_data_shaping_out_111 => - \sample_data_shaping_out[113]\, - sample_data_shaping_out_112 => - \sample_data_shaping_out[114]\, - sample_data_shaping_out_113 => - \sample_data_shaping_out[115]\, - sample_data_shaping_out_114 => - \sample_data_shaping_out[116]\, - sample_data_shaping_out_115 => - \sample_data_shaping_out[117]\, - sample_data_shaping_out_116 => - \sample_data_shaping_out[118]\, - sample_data_shaping_out_117 => - \sample_data_shaping_out[119]\, - sample_data_shaping_out_118 => - \sample_data_shaping_out[120]\, - sample_data_shaping_out_119 => - \sample_data_shaping_out[121]\, - sample_data_shaping_out_120 => - \sample_data_shaping_out[122]\, - sample_data_shaping_out_121 => - \sample_data_shaping_out[123]\, - sample_data_shaping_out_122 => - \sample_data_shaping_out[124]\, - sample_data_shaping_out_123 => - \sample_data_shaping_out[125]\, - sample_data_shaping_out_126 => - \sample_data_shaping_out[128]\, - sample_data_shaping_out_127 => - \sample_data_shaping_out[129]\, - sample_data_shaping_out_128 => - \sample_data_shaping_out[130]\, - sample_data_shaping_out_129 => - \sample_data_shaping_out[131]\, - sample_data_shaping_out_130 => - \sample_data_shaping_out[132]\, - sample_data_shaping_out_131 => - \sample_data_shaping_out[133]\, - sample_data_shaping_out_132 => - \sample_data_shaping_out[134]\, - sample_data_shaping_out_133 => - \sample_data_shaping_out[135]\, - sample_data_shaping_out_134 => - \sample_data_shaping_out[136]\, - sample_data_shaping_out_135 => - \sample_data_shaping_out[137]\, - sample_data_shaping_out_136 => - \sample_data_shaping_out[138]\, - sample_data_shaping_out_137 => - \sample_data_shaping_out[139]\, - sample_data_shaping_out_138 => - \sample_data_shaping_out[140]\, - sample_data_shaping_out_139 => - \sample_data_shaping_out[141]\, - sample_data_shaping_out_140 => - \sample_data_shaping_out[142]\, - sample_data_shaping_out_141 => - \sample_data_shaping_out[143]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_data_shaping_out_val => - \sample_data_shaping_out_val\, sample_f0_val => - sample_f0_val, sample_data_shaping_out_val_0 => - \sample_data_shaping_out_val_0\, sample_f0_val_0 => - sample_f0_val_0, sample_f0_val_1 => sample_f0_val_1, rstn - => rstn, lclk_c => lclk_c, sample_f0_val_2 => - sample_f0_val_2); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[51]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[51]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[51]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[141]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[141]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[141]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I95_Y_0 : - AX1D - port map(A => I92_un1_Y, B => N182, C => N183_0, Y => - \sample_data_shaping_f1_f0_s[2]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I37_Y : - XA1A - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[133]\, C => N197, Y => N216); - - \SampleLoop_data_shaping.1.sample_data_shaping_out_RNO[106]\ : - MX2 - port map(A => \sample_filter_v2_out[106]\, B => - \sample_data_shaping_f2_f1_s[1]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_41[106]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I49_Y : - AO1B - port map(A => N264_0, B => N216_0, C => - SUB_16x16_medium_area_I49_Y_0, Y => N244); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_0 : - AO18 - port map(A => N206_0, B => \sample_filter_v2_out[129]\, C - => \sample_filter_v2_out[111]\, Y => - SUB_16x16_medium_area_I57_Y_0_0); - - sample_data_shaping_out_val : DFN1C0 - port map(D => sample_filter_v2_out_val, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out_val\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out_RNO[125]\ : - AX1C - port map(A => \sample_filter_v2_out[143]\, B => - data_shaping_SP0, C => \sample_filter_v2_out[125]\, Y => - \sample_data_shaping_out_13[125]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I103_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[97]\, B => - \sample_filter_v2_out[115]\, C => N286_i_0, Y => - \sample_data_shaping_f2_f1_s[10]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I23_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, Y => N194); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[106]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_41[106]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[106]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[118]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_181[118]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[118]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I99_Y_0 : - AX1D - port map(A => I90_un1_Y_0, B => N190, C => N191_0, Y => - \sample_data_shaping_f2_f1_s[6]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[102]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_137[102]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[102]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I71_Y : - AO1 - port map(A => N258_0, B => N255_0, C => N254, Y => N260_0); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I90_un1_Y : - OA1 - port map(A => I85_un1_Y, B => N274_0, C => N189, Y => - I90_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I46_Y : - OR2A - port map(A => \sample_filter_v2_out[125]\, B => - \sample_filter_v2_out[107]\, Y => N225); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[4]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[4]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[4]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[125]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_13[125]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[125]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I99_Y_0 : - AX1D - port map(A => I90_un1_Y, B => N190_0, C => N191, Y => - \sample_data_shaping_f1_f0_s[6]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I29_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[130]\, B => - \sample_filter_v2_out[112]\, Y => N205); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[6]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[6]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[6]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[69]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[69]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[69]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[25]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[25]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[25]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[121]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_109[121]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[121]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[94]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_329[94]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[94]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_1 : - OA1 - port map(A => N212_0, B => N254_0, C => - SUB_16x16_medium_area_I57_Y_0_0, Y => - SUB_16x16_medium_area_I57_Y_1_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I39_Y : - XA1A - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, C => N195_0, Y => N265_0); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[53]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[53]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[53]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_0 : - AO18 - port map(A => N206, B => \sample_filter_v2_out[111]\, C => - \sample_filter_v2_out[93]\, Y => - SUB_16x16_medium_area_I57_Y_0); - - \SampleLoop_data_shaping.1.sample_data_shaping_out_RNO[124]\ : - MX2 - port map(A => \sample_filter_v2_out[124]\, B => - \sample_data_shaping_f1_f0_s[1]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_37[124]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I108_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_filter_v2_out[92]\, C => N240_0, Y => - \sample_data_shaping_f2_f1_s[15]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I94_Y_0 : - XOR2 - port map(A => N225, B => N181, Y => - \sample_data_shaping_f2_f1_s[1]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I29_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[112]\, B => - \sample_filter_v2_out[130]\, Y => N206_0); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[99]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_209[99]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[99]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I88_Y : - AO18 - port map(A => N270, B => \sample_filter_v2_out[134]\, C => - \sample_filter_v2_out[116]\, Y => N286_i); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[116]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_229[116]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[116]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I50_Y : - NOR2B - port map(A => N265, B => N216, Y => N245_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I24_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[117]\, B => - \sample_filter_v2_out[99]\, Y => N195_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I18_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[141]\, B => - \sample_filter_v2_out[123]\, Y => N183_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out_RNO[119]\ : - MX2 - port map(A => \sample_filter_v2_out[119]\, B => - \sample_data_shaping_f1_f0_s[6]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_157[119]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[139]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[139]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[139]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[70]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[70]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[70]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I27_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[114]\, B => - \sample_filter_v2_out[96]\, Y => N201_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[8]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[8]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[8]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[112]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_325[112]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[112]\); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[98]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_233[98]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[98]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[128]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[128]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[128]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y_0 : - AO18 - port map(A => N190, B => \sample_filter_v2_out[119]\, C => - \sample_filter_v2_out[101]\, Y => - SUB_16x16_medium_area_I56_Y_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[134]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[134]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[134]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I25_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[116]\, B => - \sample_filter_v2_out[98]\, Y => N197_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I29_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[112]\, B => - \sample_filter_v2_out[94]\, Y => N205_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I64_Y : - AO1 - port map(A => N268, B => N245_0, C => N244_0, Y => N258); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y : - AO1B - port map(A => SUB_16x16_medium_area_I57_un1_Y_0_0, B => - N268, C => SUB_16x16_medium_area_I57_Y_2_0, Y => N240); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[59]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[59]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[59]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I34_Y : - AO13 - port map(A => N202_0, B => \sample_filter_v2_out[95]\, C - => \sample_filter_v2_out[113]\, Y => N254); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[10]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[10]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[10]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I96_Y_0 : - XOR2 - port map(A => N278, B => N185, Y => - \sample_data_shaping_f1_f0_s[3]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I21_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[120]\, B => - \sample_filter_v2_out[138]\, Y => N190_0); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[40]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[40]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[40]\); - - Downsampling_f1 : Downsampling_8_16_6 - port map(sample_f0_0 => \sample_f0[48]\, sample_f0_1 => - \sample_f0[49]\, sample_f0_2 => \sample_f0[50]\, - sample_f0_3 => \sample_f0[51]\, sample_f0_4 => - \sample_f0[52]\, sample_f0_5 => \sample_f0[53]\, - sample_f0_6 => \sample_f0[54]\, sample_f0_7 => - \sample_f0[55]\, sample_f0_8 => \sample_f0[56]\, - sample_f0_9 => \sample_f0[57]\, sample_f0_10 => - \sample_f0[58]\, sample_f0_11 => \sample_f0[59]\, - sample_f0_12 => \sample_f0[60]\, sample_f0_13 => - \sample_f0[61]\, sample_f0_14 => \sample_f0[62]\, - sample_f0_15 => \sample_f0[63]\, sample_f0_32 => - \sample_f0[80]\, sample_f0_33 => \sample_f0[81]\, - sample_f0_34 => \sample_f0[82]\, sample_f0_35 => - \sample_f0[83]\, sample_f0_36 => \sample_f0[84]\, - sample_f0_37 => \sample_f0[85]\, sample_f0_38 => - \sample_f0[86]\, sample_f0_39 => \sample_f0[87]\, - sample_f0_40 => \sample_f0[88]\, sample_f0_41 => - \sample_f0[89]\, sample_f0_42 => \sample_f0[90]\, - sample_f0_43 => \sample_f0[91]\, sample_f0_44 => - \sample_f0[92]\, sample_f0_45 => \sample_f0[93]\, - sample_f0_46 => \sample_f0[94]\, sample_f0_47 => - \sample_f0[95]\, sample_f0_48 => \sample_f0[96]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_50 => - \sample_f0[98]\, sample_f0_51 => \sample_f0[99]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_53 => - \sample_f0[101]\, sample_f0_54 => \sample_f0[102]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_56 => - \sample_f0[104]\, sample_f0_57 => \sample_f0[105]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_59 => - \sample_f0[107]\, sample_f0_60 => \sample_f0[108]\, - sample_f0_61 => \sample_f0[109]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_63 => \sample_f0[111]\, - sample_f1_0 => \sample_f1[48]\, sample_f1_1 => - \sample_f1[49]\, sample_f1_2 => \sample_f1[50]\, - sample_f1_3 => \sample_f1[51]\, sample_f1_4 => - \sample_f1[52]\, sample_f1_5 => \sample_f1[53]\, - sample_f1_6 => \sample_f1[54]\, sample_f1_7 => - \sample_f1[55]\, sample_f1_8 => \sample_f1[56]\, - sample_f1_9 => \sample_f1[57]\, sample_f1_10 => - \sample_f1[58]\, sample_f1_11 => \sample_f1[59]\, - sample_f1_12 => \sample_f1[60]\, sample_f1_13 => - \sample_f1[61]\, sample_f1_14 => \sample_f1[62]\, - sample_f1_15 => \sample_f1[63]\, sample_f1_32 => - \sample_f1[80]\, sample_f1_33 => \sample_f1[81]\, - sample_f1_34 => \sample_f1[82]\, sample_f1_35 => - \sample_f1[83]\, sample_f1_36 => \sample_f1[84]\, - sample_f1_37 => \sample_f1[85]\, sample_f1_38 => - \sample_f1[86]\, sample_f1_39 => \sample_f1[87]\, - sample_f1_40 => \sample_f1[88]\, sample_f1_41 => - \sample_f1[89]\, sample_f1_42 => \sample_f1[90]\, - sample_f1_43 => \sample_f1[91]\, sample_f1_44 => - \sample_f1[92]\, sample_f1_45 => \sample_f1[93]\, - sample_f1_46 => \sample_f1[94]\, sample_f1_47 => - \sample_f1[95]\, sample_f1_48 => \sample_f1[96]\, - sample_f1_49 => \sample_f1[97]\, sample_f1_50 => - \sample_f1[98]\, sample_f1_51 => \sample_f1[99]\, - sample_f1_52 => \sample_f1[100]\, sample_f1_53 => - \sample_f1[101]\, sample_f1_54 => \sample_f1[102]\, - sample_f1_55 => \sample_f1[103]\, sample_f1_56 => - \sample_f1[104]\, sample_f1_57 => \sample_f1[105]\, - sample_f1_58 => \sample_f1[106]\, sample_f1_59 => - \sample_f1[107]\, sample_f1_60 => \sample_f1[108]\, - sample_f1_61 => \sample_f1[109]\, sample_f1_62 => - \sample_f1[110]\, sample_f1_63 => \sample_f1[111]\, - sample_f0_wdata_95 => \sample_f0_wdata[95]\, - sample_f0_wdata_94 => \sample_f0_wdata[94]\, - sample_f0_wdata_93 => \sample_f0_wdata[93]\, - sample_f0_wdata_92 => \sample_f0_wdata[92]\, - sample_f0_wdata_91 => \sample_f0_wdata[91]\, - sample_f0_wdata_90 => \sample_f0_wdata[90]\, - sample_f0_wdata_89 => \sample_f0_wdata[89]\, - sample_f0_wdata_88 => \sample_f0_wdata[88]\, - sample_f0_wdata_87 => \sample_f0_wdata[87]\, - sample_f0_wdata_86 => \sample_f0_wdata[86]\, - sample_f0_wdata_85 => \sample_f0_wdata[85]\, - sample_f0_wdata_84 => \sample_f0_wdata[84]\, - sample_f0_wdata_83 => \sample_f0_wdata[83]\, - sample_f0_wdata_82 => \sample_f0_wdata[82]\, - sample_f0_wdata_81 => \sample_f0_wdata[81]\, - sample_f0_wdata_80 => \sample_f0_wdata[80]\, - sample_f0_wdata_79 => \sample_f0_wdata[79]\, - sample_f0_wdata_78 => \sample_f0_wdata[78]\, - sample_f0_wdata_77 => \sample_f0_wdata[77]\, - sample_f0_wdata_76 => \sample_f0_wdata[76]\, - sample_f0_wdata_75 => \sample_f0_wdata[75]\, - sample_f0_wdata_74 => \sample_f0_wdata[74]\, - sample_f0_wdata_73 => \sample_f0_wdata[73]\, - sample_f0_wdata_72 => \sample_f0_wdata[72]\, - sample_f0_wdata_71 => \sample_f0_wdata[71]\, - sample_f0_wdata_70 => \sample_f0_wdata[70]\, - sample_f0_wdata_69 => \sample_f0_wdata[69]\, - sample_f0_wdata_68 => \sample_f0_wdata[68]\, - sample_f0_wdata_67 => \sample_f0_wdata[67]\, - sample_f0_wdata_66 => \sample_f0_wdata[66]\, - sample_f0_wdata_65 => \sample_f0_wdata[65]\, - sample_f0_wdata_64 => \sample_f0_wdata[64]\, - sample_f0_wdata_63 => \sample_f0_wdata[63]\, - sample_f0_wdata_62 => \sample_f0_wdata[62]\, - sample_f0_wdata_61 => \sample_f0_wdata[61]\, - sample_f0_wdata_60 => \sample_f0_wdata[60]\, - sample_f0_wdata_59 => \sample_f0_wdata[59]\, - sample_f0_wdata_58 => \sample_f0_wdata[58]\, - sample_f0_wdata_57 => \sample_f0_wdata[57]\, - sample_f0_wdata_56 => \sample_f0_wdata[56]\, - sample_f0_wdata_55 => \sample_f0_wdata[55]\, - sample_f0_wdata_54 => \sample_f0_wdata[54]\, - sample_f0_wdata_53 => \sample_f0_wdata[53]\, - sample_f0_wdata_52 => \sample_f0_wdata[52]\, - sample_f0_wdata_51 => \sample_f0_wdata[51]\, - sample_f0_wdata_50 => \sample_f0_wdata[50]\, - sample_f0_wdata_49 => \sample_f0_wdata[49]\, - sample_f0_wdata_48 => \sample_f0_wdata[48]\, - sample_f0_wdata_15 => \sample_f0_wdata[15]\, - sample_f0_wdata_14 => \sample_f0_wdata[14]\, - sample_f0_wdata_13 => \sample_f0_wdata[13]\, - sample_f0_wdata_12 => \sample_f0_wdata[12]\, - sample_f0_wdata_11 => \sample_f0_wdata[11]\, - sample_f0_wdata_10 => \sample_f0_wdata[10]\, - sample_f0_wdata_9 => \sample_f0_wdata[9]\, - sample_f0_wdata_8 => \sample_f0_wdata[8]\, - sample_f0_wdata_7 => \sample_f0_wdata[7]\, - sample_f0_wdata_6 => \sample_f0_wdata[6]\, - sample_f0_wdata_5 => \sample_f0_wdata[5]\, - sample_f0_wdata_4 => \sample_f0_wdata[4]\, - sample_f0_wdata_3 => \sample_f0_wdata[3]\, - sample_f0_wdata_2 => \sample_f0_wdata[2]\, - sample_f0_wdata_1 => \sample_f0_wdata[1]\, - sample_f0_wdata_0 => \sample_f0_wdata[0]\, - sample_f1_wdata_95 => \sample_f1_wdata[95]\, - sample_f1_wdata_94 => \sample_f1_wdata[94]\, - sample_f1_wdata_93 => \sample_f1_wdata[93]\, - sample_f1_wdata_92 => \sample_f1_wdata[92]\, - sample_f1_wdata_91 => \sample_f1_wdata[91]\, - sample_f1_wdata_90 => \sample_f1_wdata[90]\, - sample_f1_wdata_89 => \sample_f1_wdata[89]\, - sample_f1_wdata_88 => \sample_f1_wdata[88]\, - sample_f1_wdata_87 => \sample_f1_wdata[87]\, - sample_f1_wdata_86 => \sample_f1_wdata[86]\, - sample_f1_wdata_85 => \sample_f1_wdata[85]\, - sample_f1_wdata_84 => \sample_f1_wdata[84]\, - sample_f1_wdata_83 => \sample_f1_wdata[83]\, - sample_f1_wdata_82 => \sample_f1_wdata[82]\, - sample_f1_wdata_81 => \sample_f1_wdata[81]\, - sample_f1_wdata_80 => \sample_f1_wdata[80]\, - sample_f1_wdata_79 => \sample_f1_wdata[79]\, - sample_f1_wdata_78 => \sample_f1_wdata[78]\, - sample_f1_wdata_77 => \sample_f1_wdata[77]\, - sample_f1_wdata_76 => \sample_f1_wdata[76]\, - sample_f1_wdata_75 => \sample_f1_wdata[75]\, - sample_f1_wdata_74 => \sample_f1_wdata[74]\, - sample_f1_wdata_73 => \sample_f1_wdata[73]\, - sample_f1_wdata_72 => \sample_f1_wdata[72]\, - sample_f1_wdata_71 => \sample_f1_wdata[71]\, - sample_f1_wdata_70 => \sample_f1_wdata[70]\, - sample_f1_wdata_69 => \sample_f1_wdata[69]\, - sample_f1_wdata_68 => \sample_f1_wdata[68]\, - sample_f1_wdata_67 => \sample_f1_wdata[67]\, - sample_f1_wdata_66 => \sample_f1_wdata[66]\, - sample_f1_wdata_65 => \sample_f1_wdata[65]\, - sample_f1_wdata_64 => \sample_f1_wdata[64]\, - sample_f1_wdata_63 => \sample_f1_wdata[63]\, - sample_f1_wdata_62 => \sample_f1_wdata[62]\, - sample_f1_wdata_61 => \sample_f1_wdata[61]\, - sample_f1_wdata_60 => \sample_f1_wdata[60]\, - sample_f1_wdata_59 => \sample_f1_wdata[59]\, - sample_f1_wdata_58 => \sample_f1_wdata[58]\, - sample_f1_wdata_57 => \sample_f1_wdata[57]\, - sample_f1_wdata_56 => \sample_f1_wdata[56]\, - sample_f1_wdata_55 => \sample_f1_wdata[55]\, - sample_f1_wdata_54 => \sample_f1_wdata[54]\, - sample_f1_wdata_53 => \sample_f1_wdata[53]\, - sample_f1_wdata_52 => \sample_f1_wdata[52]\, - sample_f1_wdata_51 => \sample_f1_wdata[51]\, - sample_f1_wdata_50 => \sample_f1_wdata[50]\, - sample_f1_wdata_49 => \sample_f1_wdata[49]\, - sample_f1_wdata_48 => \sample_f1_wdata[48]\, - sample_f1_wdata_15 => \sample_f1_wdata[15]\, - sample_f1_wdata_14 => \sample_f1_wdata[14]\, - sample_f1_wdata_13 => \sample_f1_wdata[13]\, - sample_f1_wdata_12 => \sample_f1_wdata[12]\, - sample_f1_wdata_11 => \sample_f1_wdata[11]\, - sample_f1_wdata_10 => \sample_f1_wdata[10]\, - sample_f1_wdata_9 => \sample_f1_wdata[9]\, - sample_f1_wdata_8 => \sample_f1_wdata[8]\, - sample_f1_wdata_7 => \sample_f1_wdata[7]\, - sample_f1_wdata_6 => \sample_f1_wdata[6]\, - sample_f1_wdata_5 => \sample_f1_wdata[5]\, - sample_f1_wdata_4 => \sample_f1_wdata[4]\, - sample_f1_wdata_3 => \sample_f1_wdata[3]\, - sample_f1_wdata_2 => \sample_f1_wdata[2]\, - sample_f1_wdata_1 => \sample_f1_wdata[1]\, - sample_f1_wdata_0 => \sample_f1_wdata[0]\, - sample_f0_val_2 => sample_f0_val_2, sample_f0_val_1 => - sample_f0_val_1, sample_f1_val => sample_f1_val, - sample_f0_val_0 => sample_f0_val_0, rstn => rstn, lclk_c - => lclk_c, sample_f1_val_0 => sample_f1_val_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I87_Y : - AO18 - port map(A => N258_0, B => \sample_filter_v2_out[114]\, C - => \sample_filter_v2_out[96]\, Y => N284_i_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out_RNO[100]\ : - MX2 - port map(A => \sample_filter_v2_out[100]\, B => - \sample_data_shaping_f2_f1_s[7]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_185[100]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I49_Y : - AO1B - port map(A => N264, B => N216, C => - SUB_16x16_medium_area_I49_Y_0_0, Y => N244_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I41_Y : - NOR2B - port map(A => N191_0, B => N189_0, Y => N220); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y : - AO1B - port map(A => SUB_16x16_medium_area_I57_un1_Y_0, B => - N268_0, C => SUB_16x16_medium_area_I57_Y_2, Y => N240_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I17_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[142]\, B => - \sample_filter_v2_out[124]\, Y => N181_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out_RNO[98]\ : - MX2 - port map(A => \sample_filter_v2_out[98]\, B => - \sample_data_shaping_f2_f1_s[9]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_233[98]\); - - sample_data_shaping_out_val_0 : DFN1C0 - port map(D => sample_filter_v2_out_val, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out_val_0\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I38_Y : - AO13 - port map(A => N194, B => \sample_filter_v2_out[117]\, C => - \sample_filter_v2_out[135]\, Y => N264); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[41]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[41]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[41]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[140]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[140]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[140]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out_RNO[105]\ : - MX2 - port map(A => \sample_filter_v2_out[105]\, B => - \sample_data_shaping_f2_f1_s[2]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_65[105]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_1 : - AOI1B - port map(A => N254, B => N212, C => - SUB_16x16_medium_area_I57_Y_0, Y => - SUB_16x16_medium_area_I57_Y_1); - - \SampleLoop_data_shaping.5.sample_data_shaping_out_RNO[102]\ : - MX2 - port map(A => \sample_filter_v2_out[102]\, B => - \sample_data_shaping_f2_f1_s[5]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_137[102]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_2 : - AOI1B - port map(A => N244_0, B => N229_0, C => - SUB_16x16_medium_area_I57_Y_1_0, Y => - SUB_16x16_medium_area_I57_Y_2_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[39]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[39]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[39]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[130]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[130]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[130]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I97_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I91_un1_Y_0, B => - N186_0, C => N187_0, Y => - \sample_data_shaping_f2_f1_s[4]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I21_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[120]\, B => - \sample_filter_v2_out[102]\, Y => N189_0); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[63]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[63]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[63]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[101]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_161[101]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[101]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I106_Y_0 : - XOR2 - port map(A => N260, B => N205, Y => - \sample_data_shaping_f1_f0_s[13]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[45]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[45]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[45]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[123]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_61[123]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[123]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[24]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[24]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[24]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out_RNO[122]\ : - MX2 - port map(A => \sample_filter_v2_out[122]\, B => - \sample_data_shaping_f1_f0_s[3]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_85[122]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[115]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_253[115]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[115]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[43]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[43]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[43]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[60]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[60]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[60]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I42_Y : - AO13 - port map(A => N186, B => \sample_filter_v2_out[121]\, C => - \sample_filter_v2_out[139]\, Y => N274_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[64]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[64]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[64]\); - - sample_val_delay_3 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_3\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I88_Y : - AO18 - port map(A => N270_0, B => \sample_filter_v2_out[116]\, C - => \sample_filter_v2_out[98]\, Y => N286_i_0); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[133]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[133]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[133]\); - - GND_i_0 : GND - port map(Y => GND_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_2 : - AOI1B - port map(A => N244, B => N229, C => - SUB_16x16_medium_area_I57_Y_1, Y => - SUB_16x16_medium_area_I57_Y_2); - - \SampleLoop_data_shaping.4.sample_data_shaping_out_RNO[121]\ : - MX2 - port map(A => \sample_filter_v2_out[121]\, B => - \sample_data_shaping_f1_f0_s[4]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_109[121]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[142]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[142]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[142]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I96_Y_0 : - XOR2 - port map(A => N278_0, B => N185_0, Y => - \sample_data_shaping_f2_f1_s[3]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_un1_Y : - OR3C - port map(A => N225_0, B => N183_0, C => N181_0, Y => - I53_un1_Y_0); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[14]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[14]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[14]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out_RNO[99]\ : - MX2 - port map(A => \sample_filter_v2_out[99]\, B => - \sample_data_shaping_f2_f1_s[8]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_209[99]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I101_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I89_un1_Y_0, B => - N194_0, C => N195_0, Y => - \sample_data_shaping_f2_f1_s[8]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out_RNO[118]\ : - MX2 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_data_shaping_f1_f0_s[7]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_181[118]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I103_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[133]\, C => N286_i, Y => - \sample_data_shaping_f1_f0_s[10]\); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[93]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_353[93]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[93]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I92_un1_Y : - NOR2B - port map(A => N225_0, B => N181_0, Y => I92_un1_Y); - - sample_val_delay_1 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_1\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out_RNO[117]\ : - MX2 - port map(A => \sample_filter_v2_out[117]\, B => - \sample_data_shaping_f1_f0_s[8]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_205[117]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out_RNO[112]\ : - MX2 - port map(A => \sample_filter_v2_out[112]\, B => - \sample_data_shaping_f1_f0_s[13]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_325[112]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_Y_0 : - AO18 - port map(A => N182_0, B => \sample_filter_v2_out[123]\, C - => \sample_filter_v2_out[105]\, Y => - SUB_16x16_medium_area_I53_Y_0_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[114]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_277[114]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[114]\); - - DIGITAL_acquisition : AD7688_drvr - port map(sample_4(15) => \sample_4[15]\, sample_4(14) => - \sample_4[14]\, sample_4(13) => \sample_4[13]\, - sample_4(12) => \sample_4[12]\, sample_4(11) => - \sample_4[11]\, sample_4(10) => \sample_4[10]\, - sample_4(9) => \sample_4[9]\, sample_4(8) => - \sample_4[8]\, sample_4(7) => \sample_4[7]\, sample_4(6) - => \sample_4[6]\, sample_4(5) => \sample_4[5]\, - sample_4(4) => \sample_4[4]\, sample_4(3) => - \sample_4[3]\, sample_4(2) => \sample_4[2]\, sample_4(1) - => \sample_4[1]\, sample_4(0) => \sample_4[0]\, - sample_5(15) => \sample_5[15]\, sample_5(14) => - \sample_5[14]\, sample_5(13) => \sample_5[13]\, - sample_5(12) => \sample_5[12]\, sample_5(11) => - \sample_5[11]\, sample_5(10) => \sample_5[10]\, - sample_5(9) => \sample_5[9]\, sample_5(8) => - \sample_5[8]\, sample_5(7) => \sample_5[7]\, sample_5(6) - => \sample_5[6]\, sample_5(5) => \sample_5[5]\, - sample_5(4) => \sample_5[4]\, sample_5(3) => - \sample_5[3]\, sample_5(2) => \sample_5[2]\, sample_5(1) - => \sample_5[1]\, sample_5(0) => \sample_5[0]\, - sample_6(15) => \sample_6[15]\, sample_6(14) => - \sample_6[14]\, sample_6(13) => \sample_6[13]\, - sample_6(12) => \sample_6[12]\, sample_6(11) => - \sample_6[11]\, sample_6(10) => \sample_6[10]\, - sample_6(9) => \sample_6[9]\, sample_6(8) => - \sample_6[8]\, sample_6(7) => \sample_6[7]\, sample_6(6) - => \sample_6[6]\, sample_6(5) => \sample_6[5]\, - sample_6(4) => \sample_6[4]\, sample_6(3) => - \sample_6[3]\, sample_6(2) => \sample_6[2]\, sample_6(1) - => \sample_6[1]\, sample_6(0) => \sample_6[0]\, - sample_7(15) => \sample_7[15]\, sample_7(14) => - \sample_7[14]\, sample_7(13) => \sample_7[13]\, - sample_7(12) => \sample_7[12]\, sample_7(11) => - \sample_7[11]\, sample_7(10) => \sample_7[10]\, - sample_7(9) => \sample_7[9]\, sample_7(8) => - \sample_7[8]\, sample_7(7) => \sample_7[7]\, sample_7(6) - => \sample_7[6]\, sample_7(5) => \sample_7[5]\, - sample_7(4) => \sample_7[4]\, sample_7(3) => - \sample_7[3]\, sample_7(2) => \sample_7[2]\, sample_7(1) - => \sample_7[1]\, sample_7(0) => \sample_7[0]\, - sample_0(15) => \sample_0[15]\, sample_0(14) => - \sample_0[14]\, sample_0(13) => \sample_0[13]\, - sample_0(12) => \sample_0[12]\, sample_0(11) => - \sample_0[11]\, sample_0(10) => \sample_0[10]\, - sample_0(9) => \sample_0[9]\, sample_0(8) => - \sample_0[8]\, sample_0(7) => \sample_0[7]\, sample_0(6) - => \sample_0[6]\, sample_0(5) => \sample_0[5]\, - sample_0(4) => \sample_0[4]\, sample_0(3) => - \sample_0[3]\, sample_0(2) => \sample_0[2]\, sample_0(1) - => \sample_0[1]\, sample_0(0) => \sample_0[0]\, - sample_1(15) => \sample_1[15]\, sample_1(14) => - \sample_1[14]\, sample_1(13) => \sample_1[13]\, - sample_1(12) => \sample_1[12]\, sample_1(11) => - \sample_1[11]\, sample_1(10) => \sample_1[10]\, - sample_1(9) => \sample_1[9]\, sample_1(8) => - \sample_1[8]\, sample_1(7) => \sample_1[7]\, sample_1(6) - => \sample_1[6]\, sample_1(5) => \sample_1[5]\, - sample_1(4) => \sample_1[4]\, sample_1(3) => - \sample_1[3]\, sample_1(2) => \sample_1[2]\, sample_1(1) - => \sample_1[1]\, sample_1(0) => \sample_1[0]\, - sample_2(15) => \sample_2[15]\, sample_2(14) => - \sample_2[14]\, sample_2(13) => \sample_2[13]\, - sample_2(12) => \sample_2[12]\, sample_2(11) => - \sample_2[11]\, sample_2(10) => \sample_2[10]\, - sample_2(9) => \sample_2[9]\, sample_2(8) => - \sample_2[8]\, sample_2(7) => \sample_2[7]\, sample_2(6) - => \sample_2[6]\, sample_2(5) => \sample_2[5]\, - sample_2(4) => \sample_2[4]\, sample_2(3) => - \sample_2[3]\, sample_2(2) => \sample_2[2]\, sample_2(1) - => \sample_2[1]\, sample_2(0) => \sample_2[0]\, - sdo_adc_c(7) => sdo_adc_c(7), sdo_adc_c(6) => - sdo_adc_c(6), sdo_adc_c(5) => sdo_adc_c(5), sdo_adc_c(4) - => sdo_adc_c(4), sdo_adc_c(3) => sdo_adc_c(3), - sdo_adc_c(2) => sdo_adc_c(2), sdo_adc_c(1) => - sdo_adc_c(1), sdo_adc_c(0) => sdo_adc_c(0), sample_3(15) - => \sample_3[15]\, sample_3(14) => \sample_3[14]\, - sample_3(13) => \sample_3[13]\, sample_3(12) => - \sample_3[12]\, sample_3(11) => \sample_3[11]\, - sample_3(10) => \sample_3[10]\, sample_3(9) => - \sample_3[9]\, sample_3(8) => \sample_3[8]\, sample_3(7) - => \sample_3[7]\, sample_3(6) => \sample_3[6]\, - sample_3(5) => \sample_3[5]\, sample_3(4) => - \sample_3[4]\, sample_3(3) => \sample_3[3]\, sample_3(2) - => \sample_3[2]\, sample_3(1) => \sample_3[1]\, - sample_3(0) => \sample_3[0]\, AD7688_drvr_VCC => - lpp_top_lfr_wf_picker_ip_VCC, clk49_152MHz_c => - clk49_152MHz_c, cnv_ch1_c => cnv_ch1_c, sample_val => - sample_val, sck_ch1_c => sck_ch1_c, rstn => rstn, lclk_c - => lclk_c); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I64_Y : - AO1 - port map(A => N268_0, B => N245, C => N244, Y => N258_0); - - \SampleLoop_data_shaping.10.sample_data_shaping_out_RNO[97]\ : - MX2 - port map(A => \sample_filter_v2_out[97]\, B => - \sample_data_shaping_f2_f1_s[10]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_257[97]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I85_un1_Y : - NOR2B - port map(A => N278_0, B => N275, Y => I85_un1_Y_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[96]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_281[96]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[96]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I20_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[139]\, B => - \sample_filter_v2_out[121]\, Y => N187); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I19_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[122]\, B => - \sample_filter_v2_out[140]\, Y => N186); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I18_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[123]\, B => - \sample_filter_v2_out[105]\, Y => N183); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[62]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[62]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[62]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I43_Y : - NOR2B - port map(A => N187_0, B => N185_0, Y => N275); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I48_Y : - NOR2 - port map(A => N255, B => N212_0, Y => N229_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I35_Y : - XAI1A - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[131]\, C => N201, Y => N255); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I41_Y : - NOR2B - port map(A => N191, B => N189, Y => N220_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[42]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[42]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[42]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[71]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[71]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[71]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I27_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[132]\, B => - \sample_filter_v2_out[114]\, Y => N201); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I17_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[106]\, B => - \sample_filter_v2_out[124]\, Y => N182_0); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[52]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[52]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[52]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[34]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[34]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[34]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I22_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[119]\, B => - \sample_filter_v2_out[101]\, Y => N191_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I25_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[98]\, B => - \sample_filter_v2_out[116]\, Y => N198); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I25_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[116]\, B => - \sample_filter_v2_out[134]\, Y => N198_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I27_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[114]\, B => - \sample_filter_v2_out[132]\, Y => N202); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[111]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_349[111]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[111]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[9]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[9]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[9]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I105_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[95]\, B => - \sample_filter_v2_out[113]\, C => N284_i_0, Y => - \sample_data_shaping_f2_f1_s[12]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[7]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[7]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[7]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[48]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[48]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[48]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[132]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[132]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[132]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[31]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[31]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[31]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[16]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[16]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[16]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I33_Y : - XA1A - port map(A => \sample_filter_v2_out[93]\, B => - \sample_filter_v2_out[111]\, C => N205_0, Y => N212); - - \SampleLoop_data_shaping.11.sample_data_shaping_out_RNO[114]\ : - MX2 - port map(A => \sample_filter_v2_out[114]\, B => - \sample_data_shaping_f1_f0_s[11]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_277[114]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out_RNO[113]\ : - MX2 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_data_shaping_f1_f0_s[12]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_301[113]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[50]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[50]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[50]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out_RNO[94]\ : - MX2 - port map(A => \sample_filter_v2_out[94]\, B => - \sample_data_shaping_f2_f1_s[13]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_329[94]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[2]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[2]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[2]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[66]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[66]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[66]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I86_Y : - AO18 - port map(A => N260_0, B => \sample_filter_v2_out[112]\, C - => \sample_filter_v2_out[94]\, Y => N282_i_0); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[124]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_37[124]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[124]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I19_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, Y => N186_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I25_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[134]\, B => - \sample_filter_v2_out[116]\, Y => N197); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I89_un1_Y : - XA1A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N268, Y => - SUB_16x16_medium_area_I89_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y : - AO1B - port map(A => SUB_16x16_medium_area_I56_un1_Y_0, B => - N278_0, C => SUB_16x16_medium_area_I56_Y_1, Y => N268_0); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[5]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[5]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[5]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[105]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_65[105]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[105]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I104_Y_0 : - XOR2 - port map(A => N258_0, B => N201_0, Y => - \sample_data_shaping_f2_f1_s[11]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[92]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_377[92]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[92]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I89_un1_Y : - XA1A - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, C => N268_0, Y => - SUB_16x16_medium_area_I89_un1_Y_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[44]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[44]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[44]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y_0 : - AO18 - port map(A => N190_0, B => \sample_filter_v2_out[137]\, C - => \sample_filter_v2_out[119]\, Y => - SUB_16x16_medium_area_I56_Y_0_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[21]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[21]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[21]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I35_Y : - XA1A - port map(A => \sample_filter_v2_out[95]\, B => - \sample_filter_v2_out[113]\, C => N201_0, Y => N255_0); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[38]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[38]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[38]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y_1 : - AOI1B - port map(A => N274, B => N220, C => - SUB_16x16_medium_area_I56_Y_0, Y => - SUB_16x16_medium_area_I56_Y_1); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I50_Y : - NOR2B - port map(A => N265_0, B => N216_0, Y => N245); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_un1_Y_0 : - NOR2B - port map(A => N220_0, B => N275_0, Y => - SUB_16x16_medium_area_I56_un1_Y_0_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[100]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_185[100]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[100]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I98_Y_0 : - AX1D - port map(A => I85_un1_Y_0, B => N274, C => N189_0, Y => - \sample_data_shaping_f2_f1_s[5]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[95]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_305[95]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[95]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[65]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[65]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[65]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_un1_Y_0 : - NOR2B - port map(A => N220, B => N275, Y => - SUB_16x16_medium_area_I56_un1_Y_0); - - \SampleLoop_data_shaping.15.sample_data_shaping_out_RNO[92]\ : - MX2 - port map(A => \sample_filter_v2_out[92]\, B => - \sample_data_shaping_f2_f1_s[15]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_377[92]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[131]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[131]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[131]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[22]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[22]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[22]\); - - sample_val_delay_5 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_5\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I91_un1_Y : - NOR2B - port map(A => N278, B => N185, Y => - SUB_16x16_medium_area_I91_un1_Y); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_Y_0 : - AO18 - port map(A => N182, B => \sample_filter_v2_out[141]\, C => - \sample_filter_v2_out[123]\, Y => - SUB_16x16_medium_area_I53_Y_0); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[12]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[12]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[12]\); - - sample_val_delay_2 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_2\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I23_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, Y => N194_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I97_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I91_un1_Y, B => N186, C - => N187, Y => \sample_data_shaping_f1_f0_s[4]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I100_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N268, Y => - \sample_data_shaping_f1_f0_s[7]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_lfr_wf_picker is - - port( sdo_adc_c : in std_logic_vector(7 downto 0); - hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - iosn_1 : in std_logic_vector(93 to 93); - nhmaster_1_i : in std_logic_vector(0 to 0); - hsize : out std_logic_vector(1 downto 0); - hmaster_0 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - hgrant : in std_logic_vector(3 to 3); - iosn_0 : in std_logic_vector(93 to 93); - bco_msb_1_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - l1_0_m : in std_logic_vector(1 to 1); - hwdata : out std_logic_vector(31 downto 0); - coarse_time : in std_logic_vector(0 to 0); - coarse_time_i : in std_logic_vector(0 to 0); - pwdata_0 : in std_logic_vector(11 downto 0); - paddr_0 : in std_logic_vector(4 downto 2); - paddr : in std_logic_vector(7 downto 3); - paddr_2 : in std_logic_vector(2 to 2); - pwdata_1_2 : in std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_0 : in std_logic; - pwdata : in std_logic_vector(31 downto 0); - pirq : out std_logic_vector(15 to 15); - prdata : out std_logic_vector(31 downto 0); - lpp_top_lfr_wf_picker_VCC : in std_logic; - clk49_152MHz_c : in std_logic; - cnv_ch1_c : out std_logic; - sck_ch1_c : out std_logic; - lpp_top_lfr_wf_picker_GND : in std_logic; - IdlePhase : out std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - arb_1 : in std_logic; - hbusreq_i_3 : out std_logic; - Lock_RNIU86D : out std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - m19_0_N_15_i_0_li : in std_logic; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - m26_m1_e : out std_logic; - lclk_c : in std_logic; - rstn : in std_logic; - N_232 : in std_logic; - N_6455_0 : in std_logic; - Bias_Fails_c : out std_logic; - N_749 : in std_logic; - N_116 : in std_logic; - N_769 : in std_logic; - N_232_0 : in std_logic; - N_232_1 : in std_logic; - rdata61_2 : in std_logic; - N_6455 : in std_logic; - un1_apbi_0 : in std_logic - ); - -end lpp_top_lfr_wf_picker; - -architecture DEF_ARCH of lpp_top_lfr_wf_picker is - - component VCC - port( Y : out std_logic - ); - end component; - - component lpp_top_apbreg - port( status_full_ack : out std_logic_vector(3 downto 0); - prdata : out std_logic_vector(31 downto 0); - pirq : out std_logic_vector(15 to 15); - pwdata : in std_logic_vector(31 downto 0) := (others => 'U'); - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - paddr_2 : in std_logic_vector(2 to 2) := (others => 'U'); - addr_data_f2 : out std_logic_vector(31 downto 0); - status_new_err_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - status_full_err_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - status_full_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - addr_data_f3 : out std_logic_vector(31 downto 0); - addr_data_f1 : out std_logic_vector(31 downto 0); - nb_burst_available : out std_logic_vector(10 downto 0); - addr_data_f0 : out std_logic_vector(31 downto 0); - nb_snapshot_param : out std_logic_vector(10 downto 0); - delta_snapshot : out std_logic_vector(15 downto 0); - delta_f2_f0 : out std_logic_vector(9 downto 0); - delta_f2_f1 : out std_logic_vector(9 downto 0); - paddr : in std_logic_vector(7 downto 3) := (others => 'U'); - paddr_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - pwdata_0 : in std_logic_vector(11 downto 0) := (others => 'U'); - data_shaping_R0 : out std_logic; - data_shaping_R1 : out std_logic; - un1_apbi_0 : in std_logic := 'U'; - N_6455 : in std_logic := 'U'; - rdata61_2 : in std_logic := 'U'; - burst_f2 : out std_logic; - burst_f0 : out std_logic; - N_232_1 : in std_logic := 'U'; - enable_f3 : out std_logic; - enable_f2 : out std_logic; - data_shaping_SP1 : out std_logic; - enable_f1 : out std_logic; - N_232_0 : in std_logic := 'U'; - enable_f0 : out std_logic; - N_769 : in std_logic := 'U'; - N_116 : in std_logic := 'U'; - N_749 : in std_logic := 'U'; - burst_f1 : out std_logic; - data_shaping_SP0 : out std_logic; - Bias_Fails_c : out std_logic; - N_6455_0 : in std_logic := 'U'; - N_232 : in std_logic := 'U'; - data_shaping_R1_0 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_shaping_R0_0 : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_top_lfr_wf_picker_ip - port( nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - coarse_time_i : in std_logic_vector(0 to 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - coarse_time : in std_logic_vector(0 to 0) := (others => 'U'); - status_new_err : out std_logic_vector(3 downto 0); - hwdata : out std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : out std_logic_vector(1 downto 0); - hburst : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - sdo_adc_c : in std_logic_vector(7 downto 0) := (others => 'U'); - data_shaping_R0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - enable_f3 : in std_logic := 'U'; - m26_m1_e : out std_logic; - m19_a1_6_i_0 : out std_logic; - m19_a0_6_i_0 : out std_logic; - m19_0_N_15_i_0_li : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - Lock_RNIU86D : out std_logic; - hbusreq_i_3 : out std_logic; - arb_1 : in std_logic := 'U'; - un1_dmain_6 : out std_logic; - hwrite : out std_logic; - IdlePhase : out std_logic; - lpp_top_lfr_wf_picker_ip_GND : in std_logic := 'U'; - sck_ch1_c : out std_logic; - cnv_ch1_c : out std_logic; - clk49_152MHz_c : in std_logic := 'U'; - lpp_top_lfr_wf_picker_ip_VCC : in std_logic := 'U'; - data_shaping_SP0 : in std_logic := 'U'; - data_shaping_SP1 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal \status_full_ack[0]\, \status_full_ack[1]\, - \status_full_ack[2]\, \status_full_ack[3]\, - \addr_data_f2[0]\, \addr_data_f2[1]\, \addr_data_f2[2]\, - \addr_data_f2[3]\, \addr_data_f2[4]\, \addr_data_f2[5]\, - \addr_data_f2[6]\, \addr_data_f2[7]\, \addr_data_f2[8]\, - \addr_data_f2[9]\, \addr_data_f2[10]\, \addr_data_f2[11]\, - \addr_data_f2[12]\, \addr_data_f2[13]\, - \addr_data_f2[14]\, \addr_data_f2[15]\, - \addr_data_f2[16]\, \addr_data_f2[17]\, - \addr_data_f2[18]\, \addr_data_f2[19]\, - \addr_data_f2[20]\, \addr_data_f2[21]\, - \addr_data_f2[22]\, \addr_data_f2[23]\, - \addr_data_f2[24]\, \addr_data_f2[25]\, - \addr_data_f2[26]\, \addr_data_f2[27]\, - \addr_data_f2[28]\, \addr_data_f2[29]\, - \addr_data_f2[30]\, \addr_data_f2[31]\, - \status_new_err[0]\, \status_new_err[1]\, - \status_new_err[2]\, \status_new_err[3]\, - \status_full_err[0]\, \status_full_err[1]\, - \status_full_err[2]\, \status_full_err[3]\, - \status_full[0]\, \status_full[1]\, \status_full[2]\, - \status_full[3]\, \addr_data_f3[0]\, \addr_data_f3[1]\, - \addr_data_f3[2]\, \addr_data_f3[3]\, \addr_data_f3[4]\, - \addr_data_f3[5]\, \addr_data_f3[6]\, \addr_data_f3[7]\, - \addr_data_f3[8]\, \addr_data_f3[9]\, \addr_data_f3[10]\, - \addr_data_f3[11]\, \addr_data_f3[12]\, - \addr_data_f3[13]\, \addr_data_f3[14]\, - \addr_data_f3[15]\, \addr_data_f3[16]\, - \addr_data_f3[17]\, \addr_data_f3[18]\, - \addr_data_f3[19]\, \addr_data_f3[20]\, - \addr_data_f3[21]\, \addr_data_f3[22]\, - \addr_data_f3[23]\, \addr_data_f3[24]\, - \addr_data_f3[25]\, \addr_data_f3[26]\, - \addr_data_f3[27]\, \addr_data_f3[28]\, - \addr_data_f3[29]\, \addr_data_f3[30]\, - \addr_data_f3[31]\, \addr_data_f1[0]\, \addr_data_f1[1]\, - \addr_data_f1[2]\, \addr_data_f1[3]\, \addr_data_f1[4]\, - \addr_data_f1[5]\, \addr_data_f1[6]\, \addr_data_f1[7]\, - \addr_data_f1[8]\, \addr_data_f1[9]\, \addr_data_f1[10]\, - \addr_data_f1[11]\, \addr_data_f1[12]\, - \addr_data_f1[13]\, \addr_data_f1[14]\, - \addr_data_f1[15]\, \addr_data_f1[16]\, - \addr_data_f1[17]\, \addr_data_f1[18]\, - \addr_data_f1[19]\, \addr_data_f1[20]\, - \addr_data_f1[21]\, \addr_data_f1[22]\, - \addr_data_f1[23]\, \addr_data_f1[24]\, - \addr_data_f1[25]\, \addr_data_f1[26]\, - \addr_data_f1[27]\, \addr_data_f1[28]\, - \addr_data_f1[29]\, \addr_data_f1[30]\, - \addr_data_f1[31]\, \nb_burst_available[0]\, - \nb_burst_available[1]\, \nb_burst_available[2]\, - \nb_burst_available[3]\, \nb_burst_available[4]\, - \nb_burst_available[5]\, \nb_burst_available[6]\, - \nb_burst_available[7]\, \nb_burst_available[8]\, - \nb_burst_available[9]\, \nb_burst_available[10]\, - \addr_data_f0[0]\, \addr_data_f0[1]\, \addr_data_f0[2]\, - \addr_data_f0[3]\, \addr_data_f0[4]\, \addr_data_f0[5]\, - \addr_data_f0[6]\, \addr_data_f0[7]\, \addr_data_f0[8]\, - \addr_data_f0[9]\, \addr_data_f0[10]\, \addr_data_f0[11]\, - \addr_data_f0[12]\, \addr_data_f0[13]\, - \addr_data_f0[14]\, \addr_data_f0[15]\, - \addr_data_f0[16]\, \addr_data_f0[17]\, - \addr_data_f0[18]\, \addr_data_f0[19]\, - \addr_data_f0[20]\, \addr_data_f0[21]\, - \addr_data_f0[22]\, \addr_data_f0[23]\, - \addr_data_f0[24]\, \addr_data_f0[25]\, - \addr_data_f0[26]\, \addr_data_f0[27]\, - \addr_data_f0[28]\, \addr_data_f0[29]\, - \addr_data_f0[30]\, \addr_data_f0[31]\, - \nb_snapshot_param[0]\, \nb_snapshot_param[1]\, - \nb_snapshot_param[2]\, \nb_snapshot_param[3]\, - \nb_snapshot_param[4]\, \nb_snapshot_param[5]\, - \nb_snapshot_param[6]\, \nb_snapshot_param[7]\, - \nb_snapshot_param[8]\, \nb_snapshot_param[9]\, - \nb_snapshot_param[10]\, \delta_snapshot[0]\, - \delta_snapshot[1]\, \delta_snapshot[2]\, - \delta_snapshot[3]\, \delta_snapshot[4]\, - \delta_snapshot[5]\, \delta_snapshot[6]\, - \delta_snapshot[7]\, \delta_snapshot[8]\, - \delta_snapshot[9]\, \delta_snapshot[10]\, - \delta_snapshot[11]\, \delta_snapshot[12]\, - \delta_snapshot[13]\, \delta_snapshot[14]\, - \delta_snapshot[15]\, \delta_f2_f0[0]\, \delta_f2_f0[1]\, - \delta_f2_f0[2]\, \delta_f2_f0[3]\, \delta_f2_f0[4]\, - \delta_f2_f0[5]\, \delta_f2_f0[6]\, \delta_f2_f0[7]\, - \delta_f2_f0[8]\, \delta_f2_f0[9]\, \delta_f2_f1[0]\, - \delta_f2_f1[1]\, \delta_f2_f1[2]\, \delta_f2_f1[3]\, - \delta_f2_f1[4]\, \delta_f2_f1[5]\, \delta_f2_f1[6]\, - \delta_f2_f1[7]\, \delta_f2_f1[8]\, \delta_f2_f1[9]\, - data_shaping_R0, data_shaping_R1, burst_f2, burst_f0, - enable_f3, enable_f2, data_shaping_SP1, enable_f1, - enable_f0, burst_f1, data_shaping_SP0, data_shaping_R1_0, - data_shaping_R0_0, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : lpp_top_apbreg - Use entity work.lpp_top_apbreg(DEF_ARCH); - for all : lpp_top_lfr_wf_picker_ip - Use entity work.lpp_top_lfr_wf_picker_ip(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - lpp_top_apbreg_1 : lpp_top_apbreg - port map(status_full_ack(3) => \status_full_ack[3]\, - status_full_ack(2) => \status_full_ack[2]\, - status_full_ack(1) => \status_full_ack[1]\, - status_full_ack(0) => \status_full_ack[0]\, prdata(31) - => prdata(31), prdata(30) => prdata(30), prdata(29) => - prdata(29), prdata(28) => prdata(28), prdata(27) => - prdata(27), prdata(26) => prdata(26), prdata(25) => - prdata(25), prdata(24) => prdata(24), prdata(23) => - prdata(23), prdata(22) => prdata(22), prdata(21) => - prdata(21), prdata(20) => prdata(20), prdata(19) => - prdata(19), prdata(18) => prdata(18), prdata(17) => - prdata(17), prdata(16) => prdata(16), prdata(15) => - prdata(15), prdata(14) => prdata(14), prdata(13) => - prdata(13), prdata(12) => prdata(12), prdata(11) => - prdata(11), prdata(10) => prdata(10), prdata(9) => - prdata(9), prdata(8) => prdata(8), prdata(7) => prdata(7), - prdata(6) => prdata(6), prdata(5) => prdata(5), prdata(4) - => prdata(4), prdata(3) => prdata(3), prdata(2) => - prdata(2), prdata(1) => prdata(1), prdata(0) => prdata(0), - pirq(15) => pirq(15), pwdata(31) => pwdata(31), - pwdata(30) => pwdata(30), pwdata(29) => pwdata(29), - pwdata(28) => pwdata(28), pwdata(27) => pwdata(27), - pwdata(26) => pwdata(26), pwdata(25) => pwdata(25), - pwdata(24) => pwdata(24), pwdata(23) => pwdata(23), - pwdata(22) => pwdata(22), pwdata(21) => pwdata(21), - pwdata(20) => pwdata(20), pwdata(19) => pwdata(19), - pwdata(18) => pwdata(18), pwdata(17) => pwdata(17), - pwdata(16) => pwdata(16), pwdata(15) => pwdata(15), - pwdata(14) => pwdata(14), pwdata(13) => pwdata(13), - pwdata(12) => pwdata(12), pwdata(11) => pwdata(11), - pwdata(10) => pwdata(10), pwdata(9) => pwdata(9), - pwdata(8) => pwdata(8), pwdata(7) => pwdata(7), pwdata(6) - => pwdata(6), pwdata(5) => pwdata(5), pwdata(4) => - pwdata(4), pwdata(3) => pwdata(3), pwdata(2) => pwdata(2), - pwdata(1) => pwdata(1), pwdata(0) => pwdata(0), - pwdata_1_0 => pwdata_1_0, pwdata_1_3 => pwdata_1_3, - pwdata_1_2 => pwdata_1_2, paddr_2(2) => paddr_2(2), - addr_data_f2(31) => \addr_data_f2[31]\, addr_data_f2(30) - => \addr_data_f2[30]\, addr_data_f2(29) => - \addr_data_f2[29]\, addr_data_f2(28) => - \addr_data_f2[28]\, addr_data_f2(27) => - \addr_data_f2[27]\, addr_data_f2(26) => - \addr_data_f2[26]\, addr_data_f2(25) => - \addr_data_f2[25]\, addr_data_f2(24) => - \addr_data_f2[24]\, addr_data_f2(23) => - \addr_data_f2[23]\, addr_data_f2(22) => - \addr_data_f2[22]\, addr_data_f2(21) => - \addr_data_f2[21]\, addr_data_f2(20) => - \addr_data_f2[20]\, addr_data_f2(19) => - \addr_data_f2[19]\, addr_data_f2(18) => - \addr_data_f2[18]\, addr_data_f2(17) => - \addr_data_f2[17]\, addr_data_f2(16) => - \addr_data_f2[16]\, addr_data_f2(15) => - \addr_data_f2[15]\, addr_data_f2(14) => - \addr_data_f2[14]\, addr_data_f2(13) => - \addr_data_f2[13]\, addr_data_f2(12) => - \addr_data_f2[12]\, addr_data_f2(11) => - \addr_data_f2[11]\, addr_data_f2(10) => - \addr_data_f2[10]\, addr_data_f2(9) => \addr_data_f2[9]\, - addr_data_f2(8) => \addr_data_f2[8]\, addr_data_f2(7) => - \addr_data_f2[7]\, addr_data_f2(6) => \addr_data_f2[6]\, - addr_data_f2(5) => \addr_data_f2[5]\, addr_data_f2(4) => - \addr_data_f2[4]\, addr_data_f2(3) => \addr_data_f2[3]\, - addr_data_f2(2) => \addr_data_f2[2]\, addr_data_f2(1) => - \addr_data_f2[1]\, addr_data_f2(0) => \addr_data_f2[0]\, - status_new_err_0(3) => \status_new_err[3]\, - status_new_err_0(2) => \status_new_err[2]\, - status_new_err_0(1) => \status_new_err[1]\, - status_new_err_0(0) => \status_new_err[0]\, - status_full_err_0(3) => \status_full_err[3]\, - status_full_err_0(2) => \status_full_err[2]\, - status_full_err_0(1) => \status_full_err[1]\, - status_full_err_0(0) => \status_full_err[0]\, - status_full_0(3) => \status_full[3]\, status_full_0(2) - => \status_full[2]\, status_full_0(1) => - \status_full[1]\, status_full_0(0) => \status_full[0]\, - addr_data_f3(31) => \addr_data_f3[31]\, addr_data_f3(30) - => \addr_data_f3[30]\, addr_data_f3(29) => - \addr_data_f3[29]\, addr_data_f3(28) => - \addr_data_f3[28]\, addr_data_f3(27) => - \addr_data_f3[27]\, addr_data_f3(26) => - \addr_data_f3[26]\, addr_data_f3(25) => - \addr_data_f3[25]\, addr_data_f3(24) => - \addr_data_f3[24]\, addr_data_f3(23) => - \addr_data_f3[23]\, addr_data_f3(22) => - \addr_data_f3[22]\, addr_data_f3(21) => - \addr_data_f3[21]\, addr_data_f3(20) => - \addr_data_f3[20]\, addr_data_f3(19) => - \addr_data_f3[19]\, addr_data_f3(18) => - \addr_data_f3[18]\, addr_data_f3(17) => - \addr_data_f3[17]\, addr_data_f3(16) => - \addr_data_f3[16]\, addr_data_f3(15) => - \addr_data_f3[15]\, addr_data_f3(14) => - \addr_data_f3[14]\, addr_data_f3(13) => - \addr_data_f3[13]\, addr_data_f3(12) => - \addr_data_f3[12]\, addr_data_f3(11) => - \addr_data_f3[11]\, addr_data_f3(10) => - \addr_data_f3[10]\, addr_data_f3(9) => \addr_data_f3[9]\, - addr_data_f3(8) => \addr_data_f3[8]\, addr_data_f3(7) => - \addr_data_f3[7]\, addr_data_f3(6) => \addr_data_f3[6]\, - addr_data_f3(5) => \addr_data_f3[5]\, addr_data_f3(4) => - \addr_data_f3[4]\, addr_data_f3(3) => \addr_data_f3[3]\, - addr_data_f3(2) => \addr_data_f3[2]\, addr_data_f3(1) => - \addr_data_f3[1]\, addr_data_f3(0) => \addr_data_f3[0]\, - addr_data_f1(31) => \addr_data_f1[31]\, addr_data_f1(30) - => \addr_data_f1[30]\, addr_data_f1(29) => - \addr_data_f1[29]\, addr_data_f1(28) => - \addr_data_f1[28]\, addr_data_f1(27) => - \addr_data_f1[27]\, addr_data_f1(26) => - \addr_data_f1[26]\, addr_data_f1(25) => - \addr_data_f1[25]\, addr_data_f1(24) => - \addr_data_f1[24]\, addr_data_f1(23) => - \addr_data_f1[23]\, addr_data_f1(22) => - \addr_data_f1[22]\, addr_data_f1(21) => - \addr_data_f1[21]\, addr_data_f1(20) => - \addr_data_f1[20]\, addr_data_f1(19) => - \addr_data_f1[19]\, addr_data_f1(18) => - \addr_data_f1[18]\, addr_data_f1(17) => - \addr_data_f1[17]\, addr_data_f1(16) => - \addr_data_f1[16]\, addr_data_f1(15) => - \addr_data_f1[15]\, addr_data_f1(14) => - \addr_data_f1[14]\, addr_data_f1(13) => - \addr_data_f1[13]\, addr_data_f1(12) => - \addr_data_f1[12]\, addr_data_f1(11) => - \addr_data_f1[11]\, addr_data_f1(10) => - \addr_data_f1[10]\, addr_data_f1(9) => \addr_data_f1[9]\, - addr_data_f1(8) => \addr_data_f1[8]\, addr_data_f1(7) => - \addr_data_f1[7]\, addr_data_f1(6) => \addr_data_f1[6]\, - addr_data_f1(5) => \addr_data_f1[5]\, addr_data_f1(4) => - \addr_data_f1[4]\, addr_data_f1(3) => \addr_data_f1[3]\, - addr_data_f1(2) => \addr_data_f1[2]\, addr_data_f1(1) => - \addr_data_f1[1]\, addr_data_f1(0) => \addr_data_f1[0]\, - nb_burst_available(10) => \nb_burst_available[10]\, - nb_burst_available(9) => \nb_burst_available[9]\, - nb_burst_available(8) => \nb_burst_available[8]\, - nb_burst_available(7) => \nb_burst_available[7]\, - nb_burst_available(6) => \nb_burst_available[6]\, - nb_burst_available(5) => \nb_burst_available[5]\, - nb_burst_available(4) => \nb_burst_available[4]\, - nb_burst_available(3) => \nb_burst_available[3]\, - nb_burst_available(2) => \nb_burst_available[2]\, - nb_burst_available(1) => \nb_burst_available[1]\, - nb_burst_available(0) => \nb_burst_available[0]\, - addr_data_f0(31) => \addr_data_f0[31]\, addr_data_f0(30) - => \addr_data_f0[30]\, addr_data_f0(29) => - \addr_data_f0[29]\, addr_data_f0(28) => - \addr_data_f0[28]\, addr_data_f0(27) => - \addr_data_f0[27]\, addr_data_f0(26) => - \addr_data_f0[26]\, addr_data_f0(25) => - \addr_data_f0[25]\, addr_data_f0(24) => - \addr_data_f0[24]\, addr_data_f0(23) => - \addr_data_f0[23]\, addr_data_f0(22) => - \addr_data_f0[22]\, addr_data_f0(21) => - \addr_data_f0[21]\, addr_data_f0(20) => - \addr_data_f0[20]\, addr_data_f0(19) => - \addr_data_f0[19]\, addr_data_f0(18) => - \addr_data_f0[18]\, addr_data_f0(17) => - \addr_data_f0[17]\, addr_data_f0(16) => - \addr_data_f0[16]\, addr_data_f0(15) => - \addr_data_f0[15]\, addr_data_f0(14) => - \addr_data_f0[14]\, addr_data_f0(13) => - \addr_data_f0[13]\, addr_data_f0(12) => - \addr_data_f0[12]\, addr_data_f0(11) => - \addr_data_f0[11]\, addr_data_f0(10) => - \addr_data_f0[10]\, addr_data_f0(9) => \addr_data_f0[9]\, - addr_data_f0(8) => \addr_data_f0[8]\, addr_data_f0(7) => - \addr_data_f0[7]\, addr_data_f0(6) => \addr_data_f0[6]\, - addr_data_f0(5) => \addr_data_f0[5]\, addr_data_f0(4) => - \addr_data_f0[4]\, addr_data_f0(3) => \addr_data_f0[3]\, - addr_data_f0(2) => \addr_data_f0[2]\, addr_data_f0(1) => - \addr_data_f0[1]\, addr_data_f0(0) => \addr_data_f0[0]\, - nb_snapshot_param(10) => \nb_snapshot_param[10]\, - nb_snapshot_param(9) => \nb_snapshot_param[9]\, - nb_snapshot_param(8) => \nb_snapshot_param[8]\, - nb_snapshot_param(7) => \nb_snapshot_param[7]\, - nb_snapshot_param(6) => \nb_snapshot_param[6]\, - nb_snapshot_param(5) => \nb_snapshot_param[5]\, - nb_snapshot_param(4) => \nb_snapshot_param[4]\, - nb_snapshot_param(3) => \nb_snapshot_param[3]\, - nb_snapshot_param(2) => \nb_snapshot_param[2]\, - nb_snapshot_param(1) => \nb_snapshot_param[1]\, - nb_snapshot_param(0) => \nb_snapshot_param[0]\, - delta_snapshot(15) => \delta_snapshot[15]\, - delta_snapshot(14) => \delta_snapshot[14]\, - delta_snapshot(13) => \delta_snapshot[13]\, - delta_snapshot(12) => \delta_snapshot[12]\, - delta_snapshot(11) => \delta_snapshot[11]\, - delta_snapshot(10) => \delta_snapshot[10]\, - delta_snapshot(9) => \delta_snapshot[9]\, - delta_snapshot(8) => \delta_snapshot[8]\, - delta_snapshot(7) => \delta_snapshot[7]\, - delta_snapshot(6) => \delta_snapshot[6]\, - delta_snapshot(5) => \delta_snapshot[5]\, - delta_snapshot(4) => \delta_snapshot[4]\, - delta_snapshot(3) => \delta_snapshot[3]\, - delta_snapshot(2) => \delta_snapshot[2]\, - delta_snapshot(1) => \delta_snapshot[1]\, - delta_snapshot(0) => \delta_snapshot[0]\, delta_f2_f0(9) - => \delta_f2_f0[9]\, delta_f2_f0(8) => \delta_f2_f0[8]\, - delta_f2_f0(7) => \delta_f2_f0[7]\, delta_f2_f0(6) => - \delta_f2_f0[6]\, delta_f2_f0(5) => \delta_f2_f0[5]\, - delta_f2_f0(4) => \delta_f2_f0[4]\, delta_f2_f0(3) => - \delta_f2_f0[3]\, delta_f2_f0(2) => \delta_f2_f0[2]\, - delta_f2_f0(1) => \delta_f2_f0[1]\, delta_f2_f0(0) => - \delta_f2_f0[0]\, delta_f2_f1(9) => \delta_f2_f1[9]\, - delta_f2_f1(8) => \delta_f2_f1[8]\, delta_f2_f1(7) => - \delta_f2_f1[7]\, delta_f2_f1(6) => \delta_f2_f1[6]\, - delta_f2_f1(5) => \delta_f2_f1[5]\, delta_f2_f1(4) => - \delta_f2_f1[4]\, delta_f2_f1(3) => \delta_f2_f1[3]\, - delta_f2_f1(2) => \delta_f2_f1[2]\, delta_f2_f1(1) => - \delta_f2_f1[1]\, delta_f2_f1(0) => \delta_f2_f1[0]\, - paddr(7) => paddr(7), paddr(6) => paddr(6), paddr(5) => - paddr(5), paddr(4) => paddr(4), paddr(3) => paddr(3), - paddr_0(4) => paddr_0(4), paddr_0(3) => paddr_0(3), - paddr_0(2) => paddr_0(2), pwdata_0(11) => pwdata_0(11), - pwdata_0(10) => pwdata_0(10), pwdata_0(9) => pwdata_0(9), - pwdata_0(8) => pwdata_0(8), pwdata_0(7) => pwdata_0(7), - pwdata_0(6) => pwdata_0(6), pwdata_0(5) => pwdata_0(5), - pwdata_0(4) => pwdata_0(4), pwdata_0(3) => pwdata_0(3), - pwdata_0(2) => pwdata_0(2), pwdata_0(1) => pwdata_0(1), - pwdata_0(0) => pwdata_0(0), data_shaping_R0 => - data_shaping_R0, data_shaping_R1 => data_shaping_R1, - un1_apbi_0 => un1_apbi_0, N_6455 => N_6455, rdata61_2 => - rdata61_2, burst_f2 => burst_f2, burst_f0 => burst_f0, - N_232_1 => N_232_1, enable_f3 => enable_f3, enable_f2 => - enable_f2, data_shaping_SP1 => data_shaping_SP1, - enable_f1 => enable_f1, N_232_0 => N_232_0, enable_f0 => - enable_f0, N_769 => N_769, N_116 => N_116, N_749 => N_749, - burst_f1 => burst_f1, data_shaping_SP0 => - data_shaping_SP0, Bias_Fails_c => Bias_Fails_c, N_6455_0 - => N_6455_0, N_232 => N_232, data_shaping_R1_0 => - data_shaping_R1_0, rstn => rstn, lclk_c => lclk_c, - data_shaping_R0_0 => data_shaping_R0_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip - port map(nb_snapshot_param(10) => \nb_snapshot_param[10]\, - nb_snapshot_param(9) => \nb_snapshot_param[9]\, - nb_snapshot_param(8) => \nb_snapshot_param[8]\, - nb_snapshot_param(7) => \nb_snapshot_param[7]\, - nb_snapshot_param(6) => \nb_snapshot_param[6]\, - nb_snapshot_param(5) => \nb_snapshot_param[5]\, - nb_snapshot_param(4) => \nb_snapshot_param[4]\, - nb_snapshot_param(3) => \nb_snapshot_param[3]\, - nb_snapshot_param(2) => \nb_snapshot_param[2]\, - nb_snapshot_param(1) => \nb_snapshot_param[1]\, - nb_snapshot_param(0) => \nb_snapshot_param[0]\, - coarse_time_i(0) => coarse_time_i(0), delta_f2_f0(9) => - \delta_f2_f0[9]\, delta_f2_f0(8) => \delta_f2_f0[8]\, - delta_f2_f0(7) => \delta_f2_f0[7]\, delta_f2_f0(6) => - \delta_f2_f0[6]\, delta_f2_f0(5) => \delta_f2_f0[5]\, - delta_f2_f0(4) => \delta_f2_f0[4]\, delta_f2_f0(3) => - \delta_f2_f0[3]\, delta_f2_f0(2) => \delta_f2_f0[2]\, - delta_f2_f0(1) => \delta_f2_f0[1]\, delta_f2_f0(0) => - \delta_f2_f0[0]\, delta_f2_f1(9) => \delta_f2_f1[9]\, - delta_f2_f1(8) => \delta_f2_f1[8]\, delta_f2_f1(7) => - \delta_f2_f1[7]\, delta_f2_f1(6) => \delta_f2_f1[6]\, - delta_f2_f1(5) => \delta_f2_f1[5]\, delta_f2_f1(4) => - \delta_f2_f1[4]\, delta_f2_f1(3) => \delta_f2_f1[3]\, - delta_f2_f1(2) => \delta_f2_f1[2]\, delta_f2_f1(1) => - \delta_f2_f1[1]\, delta_f2_f1(0) => \delta_f2_f1[0]\, - delta_snapshot(15) => \delta_snapshot[15]\, - delta_snapshot(14) => \delta_snapshot[14]\, - delta_snapshot(13) => \delta_snapshot[13]\, - delta_snapshot(12) => \delta_snapshot[12]\, - delta_snapshot(11) => \delta_snapshot[11]\, - delta_snapshot(10) => \delta_snapshot[10]\, - delta_snapshot(9) => \delta_snapshot[9]\, - delta_snapshot(8) => \delta_snapshot[8]\, - delta_snapshot(7) => \delta_snapshot[7]\, - delta_snapshot(6) => \delta_snapshot[6]\, - delta_snapshot(5) => \delta_snapshot[5]\, - delta_snapshot(4) => \delta_snapshot[4]\, - delta_snapshot(3) => \delta_snapshot[3]\, - delta_snapshot(2) => \delta_snapshot[2]\, - delta_snapshot(1) => \delta_snapshot[1]\, - delta_snapshot(0) => \delta_snapshot[0]\, coarse_time(0) - => coarse_time(0), status_new_err(3) => - \status_new_err[3]\, status_new_err(2) => - \status_new_err[2]\, status_new_err(1) => - \status_new_err[1]\, status_new_err(0) => - \status_new_err[0]\, hwdata(31) => hwdata(31), hwdata(30) - => hwdata(30), hwdata(29) => hwdata(29), hwdata(28) => - hwdata(28), hwdata(27) => hwdata(27), hwdata(26) => - hwdata(26), hwdata(25) => hwdata(25), hwdata(24) => - hwdata(24), hwdata(23) => hwdata(23), hwdata(22) => - hwdata(22), hwdata(21) => hwdata(21), hwdata(20) => - hwdata(20), hwdata(19) => hwdata(19), hwdata(18) => - hwdata(18), hwdata(17) => hwdata(17), hwdata(16) => - hwdata(16), hwdata(15) => hwdata(15), hwdata(14) => - hwdata(14), hwdata(13) => hwdata(13), hwdata(12) => - hwdata(12), hwdata(11) => hwdata(11), hwdata(10) => - hwdata(10), hwdata(9) => hwdata(9), hwdata(8) => - hwdata(8), hwdata(7) => hwdata(7), hwdata(6) => hwdata(6), - hwdata(5) => hwdata(5), hwdata(4) => hwdata(4), hwdata(3) - => hwdata(3), hwdata(2) => hwdata(2), hwdata(1) => - hwdata(1), hwdata(0) => hwdata(0), addr_data_f0(31) => - \addr_data_f0[31]\, addr_data_f0(30) => - \addr_data_f0[30]\, addr_data_f0(29) => - \addr_data_f0[29]\, addr_data_f0(28) => - \addr_data_f0[28]\, addr_data_f0(27) => - \addr_data_f0[27]\, addr_data_f0(26) => - \addr_data_f0[26]\, addr_data_f0(25) => - \addr_data_f0[25]\, addr_data_f0(24) => - \addr_data_f0[24]\, addr_data_f0(23) => - \addr_data_f0[23]\, addr_data_f0(22) => - \addr_data_f0[22]\, addr_data_f0(21) => - \addr_data_f0[21]\, addr_data_f0(20) => - \addr_data_f0[20]\, addr_data_f0(19) => - \addr_data_f0[19]\, addr_data_f0(18) => - \addr_data_f0[18]\, addr_data_f0(17) => - \addr_data_f0[17]\, addr_data_f0(16) => - \addr_data_f0[16]\, addr_data_f0(15) => - \addr_data_f0[15]\, addr_data_f0(14) => - \addr_data_f0[14]\, addr_data_f0(13) => - \addr_data_f0[13]\, addr_data_f0(12) => - \addr_data_f0[12]\, addr_data_f0(11) => - \addr_data_f0[11]\, addr_data_f0(10) => - \addr_data_f0[10]\, addr_data_f0(9) => \addr_data_f0[9]\, - addr_data_f0(8) => \addr_data_f0[8]\, addr_data_f0(7) => - \addr_data_f0[7]\, addr_data_f0(6) => \addr_data_f0[6]\, - addr_data_f0(5) => \addr_data_f0[5]\, addr_data_f0(4) => - \addr_data_f0[4]\, addr_data_f0(3) => \addr_data_f0[3]\, - addr_data_f0(2) => \addr_data_f0[2]\, addr_data_f0(1) => - \addr_data_f0[1]\, addr_data_f0(0) => \addr_data_f0[0]\, - addr_data_f1(31) => \addr_data_f1[31]\, addr_data_f1(30) - => \addr_data_f1[30]\, addr_data_f1(29) => - \addr_data_f1[29]\, addr_data_f1(28) => - \addr_data_f1[28]\, addr_data_f1(27) => - \addr_data_f1[27]\, addr_data_f1(26) => - \addr_data_f1[26]\, addr_data_f1(25) => - \addr_data_f1[25]\, addr_data_f1(24) => - \addr_data_f1[24]\, addr_data_f1(23) => - \addr_data_f1[23]\, addr_data_f1(22) => - \addr_data_f1[22]\, addr_data_f1(21) => - \addr_data_f1[21]\, addr_data_f1(20) => - \addr_data_f1[20]\, addr_data_f1(19) => - \addr_data_f1[19]\, addr_data_f1(18) => - \addr_data_f1[18]\, addr_data_f1(17) => - \addr_data_f1[17]\, addr_data_f1(16) => - \addr_data_f1[16]\, addr_data_f1(15) => - \addr_data_f1[15]\, addr_data_f1(14) => - \addr_data_f1[14]\, addr_data_f1(13) => - \addr_data_f1[13]\, addr_data_f1(12) => - \addr_data_f1[12]\, addr_data_f1(11) => - \addr_data_f1[11]\, addr_data_f1(10) => - \addr_data_f1[10]\, addr_data_f1(9) => \addr_data_f1[9]\, - addr_data_f1(8) => \addr_data_f1[8]\, addr_data_f1(7) => - \addr_data_f1[7]\, addr_data_f1(6) => \addr_data_f1[6]\, - addr_data_f1(5) => \addr_data_f1[5]\, addr_data_f1(4) => - \addr_data_f1[4]\, addr_data_f1(3) => \addr_data_f1[3]\, - addr_data_f1(2) => \addr_data_f1[2]\, addr_data_f1(1) => - \addr_data_f1[1]\, addr_data_f1(0) => \addr_data_f1[0]\, - addr_data_f2(31) => \addr_data_f2[31]\, addr_data_f2(30) - => \addr_data_f2[30]\, addr_data_f2(29) => - \addr_data_f2[29]\, addr_data_f2(28) => - \addr_data_f2[28]\, addr_data_f2(27) => - \addr_data_f2[27]\, addr_data_f2(26) => - \addr_data_f2[26]\, addr_data_f2(25) => - \addr_data_f2[25]\, addr_data_f2(24) => - \addr_data_f2[24]\, addr_data_f2(23) => - \addr_data_f2[23]\, addr_data_f2(22) => - \addr_data_f2[22]\, addr_data_f2(21) => - \addr_data_f2[21]\, addr_data_f2(20) => - \addr_data_f2[20]\, addr_data_f2(19) => - \addr_data_f2[19]\, addr_data_f2(18) => - \addr_data_f2[18]\, addr_data_f2(17) => - \addr_data_f2[17]\, addr_data_f2(16) => - \addr_data_f2[16]\, addr_data_f2(15) => - \addr_data_f2[15]\, addr_data_f2(14) => - \addr_data_f2[14]\, addr_data_f2(13) => - \addr_data_f2[13]\, addr_data_f2(12) => - \addr_data_f2[12]\, addr_data_f2(11) => - \addr_data_f2[11]\, addr_data_f2(10) => - \addr_data_f2[10]\, addr_data_f2(9) => \addr_data_f2[9]\, - addr_data_f2(8) => \addr_data_f2[8]\, addr_data_f2(7) => - \addr_data_f2[7]\, addr_data_f2(6) => \addr_data_f2[6]\, - addr_data_f2(5) => \addr_data_f2[5]\, addr_data_f2(4) => - \addr_data_f2[4]\, addr_data_f2(3) => \addr_data_f2[3]\, - addr_data_f2(2) => \addr_data_f2[2]\, addr_data_f2(1) => - \addr_data_f2[1]\, addr_data_f2(0) => \addr_data_f2[0]\, - addr_data_f3(31) => \addr_data_f3[31]\, addr_data_f3(30) - => \addr_data_f3[30]\, addr_data_f3(29) => - \addr_data_f3[29]\, addr_data_f3(28) => - \addr_data_f3[28]\, addr_data_f3(27) => - \addr_data_f3[27]\, addr_data_f3(26) => - \addr_data_f3[26]\, addr_data_f3(25) => - \addr_data_f3[25]\, addr_data_f3(24) => - \addr_data_f3[24]\, addr_data_f3(23) => - \addr_data_f3[23]\, addr_data_f3(22) => - \addr_data_f3[22]\, addr_data_f3(21) => - \addr_data_f3[21]\, addr_data_f3(20) => - \addr_data_f3[20]\, addr_data_f3(19) => - \addr_data_f3[19]\, addr_data_f3(18) => - \addr_data_f3[18]\, addr_data_f3(17) => - \addr_data_f3[17]\, addr_data_f3(16) => - \addr_data_f3[16]\, addr_data_f3(15) => - \addr_data_f3[15]\, addr_data_f3(14) => - \addr_data_f3[14]\, addr_data_f3(13) => - \addr_data_f3[13]\, addr_data_f3(12) => - \addr_data_f3[12]\, addr_data_f3(11) => - \addr_data_f3[11]\, addr_data_f3(10) => - \addr_data_f3[10]\, addr_data_f3(9) => \addr_data_f3[9]\, - addr_data_f3(8) => \addr_data_f3[8]\, addr_data_f3(7) => - \addr_data_f3[7]\, addr_data_f3(6) => \addr_data_f3[6]\, - addr_data_f3(5) => \addr_data_f3[5]\, addr_data_f3(4) => - \addr_data_f3[4]\, addr_data_f3(3) => \addr_data_f3[3]\, - addr_data_f3(2) => \addr_data_f3[2]\, addr_data_f3(1) => - \addr_data_f3[1]\, addr_data_f3(0) => \addr_data_f3[0]\, - status_full(3) => \status_full[3]\, status_full(2) => - \status_full[2]\, status_full(1) => \status_full[1]\, - status_full(0) => \status_full[0]\, status_full_err(3) - => \status_full_err[3]\, status_full_err(2) => - \status_full_err[2]\, status_full_err(1) => - \status_full_err[1]\, status_full_err(0) => - \status_full_err[0]\, nb_burst_available(10) => - \nb_burst_available[10]\, nb_burst_available(9) => - \nb_burst_available[9]\, nb_burst_available(8) => - \nb_burst_available[8]\, nb_burst_available(7) => - \nb_burst_available[7]\, nb_burst_available(6) => - \nb_burst_available[6]\, nb_burst_available(5) => - \nb_burst_available[5]\, nb_burst_available(4) => - \nb_burst_available[4]\, nb_burst_available(3) => - \nb_burst_available[3]\, nb_burst_available(2) => - \nb_burst_available[2]\, nb_burst_available(1) => - \nb_burst_available[1]\, nb_burst_available(0) => - \nb_burst_available[0]\, l1_0_m(1) => l1_0_m(1), - nhmaster_1_iv_0(1) => nhmaster_1_iv_0(1), bco_msb_1_m(1) - => bco_msb_1_m(1), iosn_0(93) => iosn_0(93), hgrant(3) - => hgrant(3), hmaster_0_0_RNIFCVH1_0(1) => - hmaster_0_0_RNIFCVH1_0(1), bco_msb_1(1) => bco_msb_1(1), - haddr(31) => haddr(31), haddr(30) => haddr(30), haddr(29) - => haddr(29), haddr(28) => haddr(28), haddr(27) => - haddr(27), haddr(26) => haddr(26), haddr(25) => haddr(25), - haddr(24) => haddr(24), haddr(23) => haddr(23), haddr(22) - => haddr(22), haddr(21) => haddr(21), haddr(20) => - haddr(20), haddr(19) => haddr(19), haddr(18) => haddr(18), - haddr(17) => haddr(17), haddr(16) => haddr(16), haddr(15) - => haddr(15), haddr(14) => haddr(14), haddr(13) => - haddr(13), haddr(12) => haddr(12), haddr(11) => haddr(11), - haddr(10) => haddr(10), haddr(9) => haddr(9), haddr(8) - => haddr(8), haddr(7) => haddr(7), haddr(6) => haddr(6), - haddr(5) => haddr(5), haddr(4) => haddr(4), haddr(3) => - haddr(3), haddr(2) => haddr(2), haddr(1) => haddr(1), - haddr(0) => haddr(0), hmaster_0(1) => hmaster_0(1), - hsize(1) => hsize(1), hsize(0) => hsize(0), - nhmaster_1_i(0) => nhmaster_1_i(0), iosn_1(93) => - iosn_1(93), hresp(0) => hresp(0), iosn_2(93) => - iosn_2(93), htrans(1) => htrans(1), htrans(0) => - htrans(0), hburst(2) => hburst(2), hburst(1) => hburst(1), - hburst(0) => hburst(0), status_full_ack(3) => - \status_full_ack[3]\, status_full_ack(2) => - \status_full_ack[2]\, status_full_ack(1) => - \status_full_ack[1]\, status_full_ack(0) => - \status_full_ack[0]\, sdo_adc_c(7) => sdo_adc_c(7), - sdo_adc_c(6) => sdo_adc_c(6), sdo_adc_c(5) => - sdo_adc_c(5), sdo_adc_c(4) => sdo_adc_c(4), sdo_adc_c(3) - => sdo_adc_c(3), sdo_adc_c(2) => sdo_adc_c(2), - sdo_adc_c(1) => sdo_adc_c(1), sdo_adc_c(0) => - sdo_adc_c(0), data_shaping_R0 => data_shaping_R0, - data_shaping_R0_0 => data_shaping_R0_0, enable_f0 => - enable_f0, burst_f0 => burst_f0, data_shaping_R1 => - data_shaping_R1, data_shaping_R1_0 => data_shaping_R1_0, - enable_f1 => enable_f1, burst_f1 => burst_f1, enable_f2 - => enable_f2, burst_f2 => burst_f2, enable_f3 => - enable_f3, m26_m1_e => m26_m1_e, m19_a1_6_i_0 => - m19_a1_6_i_0, m19_a0_6_i_0 => m19_a0_6_i_0, - m19_0_N_15_i_0_li => m19_0_N_15_i_0_li, rstoutl_RNIGJKSJO - => rstoutl_RNIGJKSJO, un1_nhmaster_0_sqmuxa_1 => - un1_nhmaster_0_sqmuxa_1, Lock_RNIU86D => Lock_RNIU86D, - hbusreq_i_3 => hbusreq_i_3, arb_1 => arb_1, un1_dmain_6 - => un1_dmain_6, hwrite => hwrite, IdlePhase => IdlePhase, - lpp_top_lfr_wf_picker_ip_GND => lpp_top_lfr_wf_picker_GND, - sck_ch1_c => sck_ch1_c, cnv_ch1_c => cnv_ch1_c, - clk49_152MHz_c => clk49_152MHz_c, - lpp_top_lfr_wf_picker_ip_VCC => lpp_top_lfr_wf_picker_VCC, - data_shaping_SP0 => data_shaping_SP0, data_shaping_SP1 - => data_shaping_SP1, rstn => rstn, lclk_c => lclk_c); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity dcom_uart is - - port( data : out std_logic_vector(7 downto 0); - hwdata : in std_logic_vector(31 downto 24); - paddr : in std_logic_vector(3 downto 2); - pwdata_1 : in std_logic_vector(4 to 4); - prdata_5 : out std_logic; - prdata_0 : out std_logic; - state_i : in std_logic_vector(5 to 5); - psel_1 : in std_logic_vector(7 to 7); - pwdata : in std_logic_vector(17 downto 16); - un1_dcom0_16 : out std_logic; - un1_dcom0_13 : out std_logic; - un1_dcom0_12 : out std_logic; - un1_dcom0_11 : out std_logic; - un1_dcom0_15 : out std_logic; - un1_dcom0_14 : out std_logic; - un1_dcom0_17 : out std_logic; - un1_dcom0_10 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 0); - tcnt : out std_logic_vector(1 downto 0); - dsurx_c : in std_logic; - lclk_c : in std_logic; - N_335 : out std_logic; - un1_apbi_2 : in std_logic; - N_769 : in std_logic; - N_330 : out std_logic; - N_127 : out std_logic; - N_6455 : in std_logic; - N_331 : out std_logic; - N_336 : out std_logic; - N_334 : out std_logic; - N_333 : out std_logic; - N_332 : out std_logic; - N_6455_0 : in std_logic; - dsutx_c : out std_logic; - N_85 : out std_logic; - write : in std_logic; - thempty : out std_logic; - N_321 : in std_logic; - rdata60_1 : in std_logic; - N_86 : out std_logic; - rstn : in std_logic; - dready : out std_logic; - un1_apbi_0 : in std_logic; - N_78_0 : in std_logic - ); - -end dcom_uart; - -architecture DEF_ARCH of dcom_uart is - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_61_1, N_61_0, \tcnt[1]\, \tcnt[0]\, N_136, - rxstate_0_sqmuxa, N_677, rxtick_0_0_a5, rxtick_0_0_a5_0, - tick, \rxclk[2]\, \scaler_1_0_iv_0_0[2]\, N_697, N_744, - \scaler_1_0_iv_0_0[12]\, N_716, \scaler_1_0_iv_0_0[11]\, - scaler_2_sqmuxa, \scaler[15]\, N_723, - \scaler_1_0_iv_0_1[10]\, scaler_0_sqmuxa_1, N_725, - \scaler_1_0_iv_0_0[9]\, N_728, \scaler_1_0_iv_0_0[8]\, - N_732, \scaler_1_0_iv_0_0[7]\, N_737, - \scaler_1_0_iv_0_1[5]\, \un1_dcom0[7]\, N_740, - \scaler_1_0_iv_0[0]\, \scaler_i_m_1[4]\, - \scaler_1_0_iv_0[1]\, \scaler[5]\, \apbi_i_m_0[51]\, - \scaler_1_0_iv_0[4]\, \scaler_i_m_1[8]\, - \scaler_1_0_iv_0[6]\, \scaler_i_m_1[10]\, - \scaler_1_0_iv_0[3]\, \scaler_i_m_1[7]\, - \scaler_1_0_iv_0[13]\, \scaler_i_m_0[17]\, - \scaler_1_0_iv_0_0[16]\, \scaler_1_0_iv_1[17]\, - \scaler_i_m[17]\, \brate_1_iv_0[14]\, brate_1_sqmuxa, - brate_3_sqmuxa_i, \brate_1_iv_0[15]\, \brate_1_iv_0[16]\, - \brate_1_iv_0[17]\, \scaler_1_0_iv_0[14]\, - \brate_i_m[14]\, \brate_1_iv_0[0]\, brate_0_sqmuxa_1_i, - \scaler[4]\, \apbi_i_m[50]\, \brate_1_iv_0_0[4]\, N_78, - \brate_1_iv_0_0[8]\, N_706, \brate_1_iv_0_0[10]\, - \scaler[14]\, N_82, \brate_1_iv_0_0[12]\, \scaler[16]\, - N_707, \brate_1_iv_0[3]\, \scaler[7]\, \apbi_i_m[53]\, - \brate_1_iv_0[5]\, \scaler[9]\, \apbi_i_m[55]\, - \brate_1_iv_0[7]\, \scaler[11]\, \apbi_i_m[57]\, - \brate_1_iv_0[9]\, \scaler_i_m[13]\, \brate_1_iv_0[11]\, - \apbi_i_m[61]\, \brate_1_iv_0[13]\, \scaler_i_m_1[17]\, - brate_i_m_14_m1_e_0, \tshift_1_0_0[0]\, txtick, N_138_i, - N_123, txtick_0_i_0, \txclk[2]\, rxen_0_sqmuxa_0, - un1_apbi_1, \rxstate_ns_0_0[0]\, N_640_2, - \rxstate_ns_0_a3_0_0[0]\, N_639, tcnt8_NE_10, tcnt8_NE_1, - tcnt8_NE_0, tcnt8_NE_6, tcnt8_NE_9, tcnt8_6_i, N_56_i_i, - tcnt8_NE_5, tcnt8_NE_8, tcnt8_3_i, tcnt8_1_i, tcnt8_NE_3, - N_58_i_i, tcnt8_9_i, \un1_dcom0[11]\, tcnt8_8_i, - \scaler[8]\, \un1_dcom0[10]\, N_59_i_i, \un1_dcom0[6]\, - N_54_i_i, dready_2_0, thempty_1_sqmuxa_1_i_o2_0, - \txstate[0]\, \txstate[1]\, rshift_0_sqmuxa_0_a2_0_0, - \rxstate[0]\, \rxstate[1]\, \tshift_1_0_a2_6[0]\, - \tshift[9]\, \tshift[8]\, \tshift_1_0_a2_4[0]\, - \tshift_1_0_a2_5[0]\, \tshift[5]\, \tshift[4]\, - \tshift_1_0_a2_2[0]\, \tshift[3]\, \tshift[2]\, - \tshift[6]\, \tshift[7]\, break10_5, break10_3, - \rshift[5]\, \rshift[4]\, break10_4, break10_1, - \rshift[1]\, \rshift[0]\, \rshift[6]\, \rshift[7]\, - \rshift[2]\, \rshift[3]\, rxtick, N_629, - \scaler_1_0_iv[17]\, \apbi_i_m[67]\, \scaler_1_0_iv[14]\, - \scaler_i_m[14]\, \scaler_1_0_iv[13]\, \scaler_i_m_0[13]\, - \brate_i_m[13]\, \scaler_1_0_iv[3]\, \scaler_i_m[3]\, - \brate_i_m[3]\, \scaler_1_0_iv[6]\, \scaler_i_m[6]\, - \brate_i_m[6]\, \scaler_1_0_iv[4]\, \scaler_i_m[4]\, - \brate_i_m[4]\, \scaler_1_0_iv[1]\, \scaler_i_m[1]\, - \brate_i_m[1]\, \scaler_1_0_iv[0]\, \scaler_i_m[0]\, - \brate_i_m[0]\, \scaler_1[2]\, N_742, N_743, - \scaler_1_0_iv[5]\, N_741, N_122, \scaler_1_0_iv[7]\, - N_736, N_738, \scaler_1_0_iv[8]\, N_733, N_734, - \scaler_1_0_iv[9]\, N_729, N_730, \scaler_1_0_iv[10]\, - N_724, N_727, \scaler_1_0_iv[11]\, N_721, N_722, - \scaler_1_0_iv[12]\, N_717, N_718, \scaler_1_0_iv[15]\, - N_715, \scaler_RNO_1[15]\, \scaler_1_0_iv[16]\, N_710, - N_711, \tshift_1[0]\, N_124, \brate_1_iv[13]\, - \scaler[13]\, brate_1_sqmuxa_4, \brate_1_iv[11]\, - \brate_1_iv[9]\, \brate_1_iv[7]\, \brate_1_iv[6]\, - \scaler_i_m[10]\, \apbi_i_m[56]\, \scaler_i_m_0[6]\, - \brate_1_iv[5]\, \brate_1_iv[3]\, \scaler[3]\, - \brate_1_iv[1]\, \scaler_i_m[5]\, \apbi_i_m[51]\, - \scaler_i_m_0[1]\, \brate_1_iv[12]\, \scaler[12]\, - \brate_1_iv[10]\, \scaler[10]\, \brate_1_iv[8]\, - \brate_1_iv[4]\, N_7, break_0_sqmuxa, N_701, - frame_0_sqmuxa, tcnt_1_sqmuxa_3, \tcnt_1_sqmuxa[0]\, - rxen_1_sqmuxa, tcnt_0_sqmuxa_2, \brate_1[17]\, - \scaler[17]\, \brate_1[16]\, \brate_1[15]\, \brate_1[14]\, - tcnt_0_sqmuxa, fedge_0_sqmuxa, scaler_2_sqmuxa_1, rxdb_3, - un1_scaler, rxen_0_sqmuxa_1, brate_0_sqmuxa, enable, - scaler_4_sqmuxa, \scaler7[0]\, tcnt_1_sqmuxa, tcnt9, - brate2, fedge, \rxdb[1]\, \rxdb[0]\, N_650, N_114, N_139, - \tshift_RNO[8]\, N_110, N_109, N_108, \tshift_RNO[7]\, - N_107, N_106, N_105, \tshift_RNO[6]\, N_104, N_103, N_102, - \tshift_RNO[5]\, N_101, N_100, N_99, \tshift_RNO[4]\, - N_98, N_97, N_96, N_31, N_95, N_94, N_93, N_29, N_92, - N_91, N_90, N_690, N_112, txtick_RNO, CO1, N_64, dready_2, - N_628, rsempty_1_sqmuxa, dready_0_sqmuxa, \dready\, - rsempty, N_622, break10_i_0, N_27, N_89, N_88, N_87, - \brate_1_iv[2]\, N_75, N_73, N_74, N_59, \brate_1_iv[0]\, - \scaler[0]\, scaler_0_sqmuxa, \scaler_RNO_3[15]\, - \scaler_0[15]\, \scaler_2_sqmuxa[0]\, \scaler_RNO_2[15]\, - \un1_dcom0[17]\, N_400, fedge_1_sqmuxa, N_419, break, - break_1, N_427, frame, frame_1, N_9, N_428, rxen_1, - rxen_1_sqmuxa_1, N_437, N_560, N_560s, N_561, N_561s, - N_439, rshift_0_sqmuxa, N_440, N_441, N_442, N_443, N_444, - N_445, N_446, N_402, \un1_dcom0[3]\, brate_2_sqmuxa, - N_404, \un1_dcom0[5]\, N_405, N_406, N_407, - \un1_dcom0[8]\, N_408, \un1_dcom0[9]\, N_409, N_410, - N_411, \un1_dcom0[12]\, N_412, \un1_dcom0[13]\, N_413, - N_414, N_415, \un1_dcom0[16]\, N_416, N_417, N_418, - \un1_dcom0[19]\, \un1_dcom0[14]\, N_329, N_77, N_126, - \thold[1]\, \thold[2]\, \thold[3]\, \thold[4]\, - \thold[5]\, \thold[6]\, \thold[7]\, \tshift[1]\, N_8, - \rxf[2]\, \rxf[4]\, \rxf[3]\, \tshift_10_0_iv[9]\, - \rxf_RNO[2]\, \rxf[1]\, N_62, \rxf_RNO[3]\, \rxf_RNO[4]\, - rxdb_1, \brate13[0]\, brate_1_sqmuxa_2, rxen_0_sqmuxa_2, - brate_1_sqmuxa_3, \scaler_0[17]\, tick_2, scaler_1_sqmuxa, - \apbi_m[51]_net_1\, rxen_RNO, frame_RNO, break_RNO, - fedge_RNO, thempty_RNO, \brate_RNO[1]\, \brate_RNO[3]\, - \brate_RNO[4]\, \brate_RNO[5]\, \brate_RNO[6]\, - \brate_RNO[7]\, \brate_RNO[8]\, \brate_RNO[9]\, - \brate_RNO[10]\, \brate_RNO[11]\, \brate_RNO[12]\, - \brate_RNO[13]\, \brate_RNO[14]\, \brate_RNO[15]\, - \brate_RNO[16]\, \brate_RNO[17]\, \scaler_0[16]\, - \un1_dcom0[18]\, \scaler_0[12]\, \scaler_0[11]\, - \scaler_0[10]\, \scaler_0[9]\, \scaler_0[8]\, - \scaler_0[7]\, \scaler_0[5]\, \scaler[6]\, \scaler[2]\, - \un1_dcom0[4]\, N_702_1, \scaler[1]\, \scaler_0[3]\, - \un1_dcom0[15]\, \scaler_0[13]\, \scaler_0[14]\, N_630, - N_328, \un1_dcom0[2]\, ovf, \scaler_0[1]\, \scaler_0[4]\, - \scaler_0[6]\, rxdb_4, \rshift_RNO[0]\, \rshift_RNO[1]\, - \rshift_RNO[2]\, \rshift_RNO[3]\, \rshift_RNO[4]\, - \rshift_RNO[5]\, \rshift_RNO[6]\, \rshift_RNO[7]\, N_15, - N_21_1, N_19, N_680_i_1, \txclk[1]\, N_21, N_23, N_133, - \rxclk_1[1]\, \rxclk[0]\, \rxclk[1]\, \rxclk_1[0]\, - rxclk_1_sqmuxa_1, rsempty_0_sqmuxa_1_1, dready_RNO, - dready_0_sqmuxa_0, ovf_0_sqmuxa, rsempty_2, N_627, - ovf_RNO, N_438, N_642, rxstate_1, \rxstate_nss[1]\, - \rxstate_nss[0]\, N_420, rsempty_1, rsempty_RNO, - rsempty_0_sqmuxa_2, rsempty_RNO_4, \thempty\, - \scaler_0[2]\, \brate_RNO[2]\, N_403, tsempty_RNO, N_447, - \thold[0]\, N_79, tsempty, \N_127\, N_61, \tcnt_RNO[1]\, - \tcnt_0_sqmuxa_1_m[0]\, \tcnt_RNO[0]\, - \tcnt_0_sqmuxa_1_m[1]\, CO0, tcnt_0_sqmuxa_1, N_401, - \brate_RNO[0]\, \dsutx_c\, \rxf[0]\, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, N_21_0, N_20, N_19_0, - N_16, N_18, N_17, N_15_0, N_12, N_13, N_14, - \ACT_LT3_E[3]\, \ACT_LT3_E[4]\, \ACT_LT3_E[5]\, - \ACT_LT3_E[0]\, \ACT_LT3_E[1]\, \ACT_LT3_E[2]\, - \DWACT_BL_EQUAL_0_E[2]\, \DWACT_BL_EQUAL_0_E[1]\, - \DWACT_BL_EQUAL_0_E[0]\, - \DWACT_CMPLE_PO0_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO0_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO0_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E_0[1]\, \DWACT_BL_EQUAL_0_E_0[0]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[3]\, \DWACT_BL_EQUAL_0_E[4]\, - \DWACT_BL_EQUAL_0_E[5]\, \DWACT_BL_EQUAL_0_E_1[0]\, - \DWACT_BL_EQUAL_0_E_1[1]\, \DWACT_BL_EQUAL_0_E_0[2]\, - \DWACT_ADD_CI_0_pog_array_1_6[0]\, - \DWACT_ADD_CI_0_pog_array_0_13[0]\, - \DWACT_ADD_CI_0_pog_array_0_14[0]\, - \DWACT_ADD_CI_0_pog_array_2_1[0]\, - \DWACT_ADD_CI_0_pog_array_1_3[0]\, - \DWACT_ADD_CI_0_pog_array_1_4[0]\, - \DWACT_ADD_CI_0_pog_array_2_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_5[0]\, - \DWACT_ADD_CI_0_pog_array_0_11[0]\, - \DWACT_ADD_CI_0_pog_array_0_12[0]\, - \DWACT_ADD_CI_0_pog_array_1_2[0]\, - \DWACT_ADD_CI_0_pog_array_0_5[0]\, - \DWACT_ADD_CI_0_pog_array_0_6[0]\, - \DWACT_ADD_CI_0_pog_array_0_9[0]\, - \DWACT_ADD_CI_0_pog_array_0_10[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_pog_array_0_3[0]\, - \DWACT_ADD_CI_0_pog_array_0_4[0]\, - \DWACT_ADD_CI_0_pog_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_0_7[0]\, - \DWACT_ADD_CI_0_pog_array_0_8[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_pog_array_0_1[0]\, - \DWACT_ADD_CI_0_pog_array_0_2[0]\, - \DWACT_ADD_CI_0_pog_array_3[0]\, - \DWACT_ADD_CI_0_g_array_12_7[0]\, - \DWACT_ADD_CI_0_pog_array_0_15[0]\, - \DWACT_ADD_CI_0_g_array_4[0]\, - \DWACT_ADD_CI_0_g_array_0_16[0]\, - \DWACT_ADD_CI_0_g_array_11_2[0]\, - \DWACT_ADD_CI_0_g_array_10[0]\, - \DWACT_ADD_CI_0_g_array_1_6[0]\, - \DWACT_ADD_CI_0_g_array_12[0]\, - \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_g_array_0_2[0]\, - \DWACT_ADD_CI_0_g_array_12_5[0]\, - \DWACT_ADD_CI_0_g_array_0_12[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_g_array_1_2[0]\, - \DWACT_ADD_CI_0_g_array_2_1[0]\, - \DWACT_ADD_CI_0_g_array_1_3[0]\, - \DWACT_ADD_CI_0_g_array_12_4[0]\, - \DWACT_ADD_CI_0_g_array_11_1[0]\, - \DWACT_ADD_CI_0_g_array_0_10[0]\, - \DWACT_ADD_CI_0_g_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_3[0]\, - \DWACT_ADD_CI_0_g_array_3_1[0]\, - \DWACT_ADD_CI_0_g_array_12_3[0]\, - \DWACT_ADD_CI_0_g_array_0_8[0]\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, - \DWACT_ADD_CI_0_g_array_0_6[0]\, - \DWACT_ADD_CI_0_g_array_2_2[0]\, - \DWACT_ADD_CI_0_g_array_2_3[0]\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, - \DWACT_ADD_CI_0_g_array_0_4[0]\, - \DWACT_ADD_CI_0_g_array_1_4[0]\, - \DWACT_ADD_CI_0_g_array_1_5[0]\, - \DWACT_ADD_CI_0_g_array_1_7[0]\, - \DWACT_ADD_CI_0_g_array_0_14[0]\, - \DWACT_ADD_CI_0_g_array_0_15[0]\, - \DWACT_ADD_CI_0_g_array_12_6[0]\, - \DWACT_ADD_CI_0_g_array_0_7[0]\, - \DWACT_ADD_CI_0_g_array_0_13[0]\, - \DWACT_ADD_CI_0_g_array_0_5[0]\, - \DWACT_ADD_CI_0_g_array_0_11[0]\, - \DWACT_ADD_CI_0_g_array_0_3[0]\, - \DWACT_ADD_CI_0_g_array_0_9[0]\, - \DWACT_ADD_CI_0_pog_array_0[0]\, - \DWACT_ADD_CI_0_g_array_0_1[0]\, - \DWACT_ADD_CI_0_partial_sum[17]\, - \DWACT_ADD_CI_0_partial_sum[10]\, - \DWACT_ADD_CI_0_partial_sum[3]\, - \DWACT_ADD_CI_0_partial_sum[16]\, - \DWACT_ADD_CI_0_partial_sum[9]\, - \DWACT_ADD_CI_0_partial_sum[8]\, - \DWACT_ADD_CI_0_partial_sum[2]\, - \DWACT_ADD_CI_0_partial_sum[7]\, - \DWACT_ADD_CI_0_partial_sum[15]\, - \DWACT_ADD_CI_0_partial_sum[6]\, - \DWACT_ADD_CI_0_partial_sum[14]\, - \DWACT_ADD_CI_0_partial_sum[5]\, - \DWACT_ADD_CI_0_partial_sum[1]\, - \DWACT_ADD_CI_0_partial_sum[4]\, - \DWACT_ADD_CI_0_partial_sum[12]\, - \DWACT_ADD_CI_0_partial_sum[13]\, - \DWACT_ADD_CI_0_partial_sum[11]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - un1_dcom0_16 <= \un1_dcom0[18]\; - un1_dcom0_13 <= \un1_dcom0[15]\; - un1_dcom0_12 <= \un1_dcom0[14]\; - un1_dcom0_11 <= \un1_dcom0[13]\; - un1_dcom0_15 <= \un1_dcom0[17]\; - un1_dcom0_14 <= \un1_dcom0[16]\; - un1_dcom0_17 <= \un1_dcom0[19]\; - un1_dcom0_10 <= \un1_dcom0[12]\; - tcnt(1) <= \tcnt[1]\; - tcnt(0) <= \tcnt[0]\; - N_127 <= \N_127\; - dsutx_c <= \dsutx_c\; - thempty <= \thempty\; - dready <= \dready\; - - \r.scaler_RNO_3[13]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[17]\, Y => - \scaler_i_m_0[17]\); - - scaler_I_89 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_4[0]\, B => - \DWACT_ADD_CI_0_g_array_1_4[0]\, C => - \DWACT_ADD_CI_0_g_array_1_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_2_2[0]\); - - \r.brate_RNI09O8[17]\ : XNOR2 - port map(A => \un1_dcom0[19]\, B => \scaler[17]\, Y => - N_59_i_i); - - \r.tshift_RNO_0[4]\ : NOR2 - port map(A => \thold[3]\, B => N_64, Y => N_98); - - \r.rsempty_RNO_2\ : OR2B - port map(A => N_629, B => N_622, Y => rxstate_1); - - scaler_I_70 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[9]\, B => - \DWACT_ADD_CI_0_g_array_12_3[0]\, Y => \scaler_0[9]\); - - \r.dready_RNICJV3\ : NOR2B - port map(A => state_i(5), B => \dready\, Y => dready_2_0); - - \r.brate_RNI4Q3D[4]\ : XA1A - port map(A => \scaler[4]\, B => \un1_dcom0[6]\, C => - N_54_i_i, Y => tcnt8_NE_0); - - \uartop.op_gt.v.brate2_0_I_9\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - \r.brate_RNI8UT7[0]\ : MX2 - port map(A => \dready\, B => \un1_dcom0[2]\, S => N_6455_0, - Y => N_328); - - \r.brate_RNO_1[15]\ : AO1C - port map(A => brate_1_sqmuxa_4, B => \scaler[15]\, C => - \brate_1_iv_0[15]\, Y => \brate_1[15]\); - - \r.scaler_RNO[1]\ : NOR3 - port map(A => \scaler_i_m[1]\, B => \brate_i_m[1]\, C => - \scaler_1_0_iv_0[1]\, Y => \scaler_1_0_iv[1]\); - - \r.tshift_RNO_1[6]\ : NOR2 - port map(A => \tshift[7]\, B => N_77, Y => N_103); - - \r.scaler[2]\ : DFN1E0 - port map(D => \scaler_1[2]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler_0[2]\); - - \r.rxf_RNO[4]\ : MX2 - port map(A => \rxf[4]\, B => \rxf[3]\, S => N_62, Y => - \rxf_RNO[4]\); - - scaler_I_9 : AND2 - port map(A => \scaler[3]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_3[0]\); - - \r.brate[9]\ : DFN1 - port map(D => \brate_RNO[9]\, CLK => lclk_c, Q => - \un1_dcom0[11]\); - - \r.rxdb_RNITI9[1]\ : OR2A - port map(A => \rxdb[1]\, B => \rxdb[0]\, Y => N_630); - - \r.txstate_RNO_0[1]\ : AXOI5 - port map(A => N_139, B => txtick, C => \txstate[1]\, Y => - N_561); - - \r.rxdb[1]\ : DFN1 - port map(D => \rxdb[0]\, CLK => lclk_c, Q => \rxdb[1]\); - - \r.scaler_RNO_2[7]\ : AO1D - port map(A => N_697, B => pwdata_0(7), C => N_737, Y => - \scaler_1_0_iv_0_0[7]\); - - \r.tcnt_RNO[1]\ : OA1 - port map(A => \apbi_m[51]_net_1\, B => - \tcnt_0_sqmuxa_1_m[0]\, C => rstn, Y => \tcnt_RNO[1]\); - - \r.break_RNO_2\ : OR3 - port map(A => break_0_sqmuxa, B => N_701, C => - frame_0_sqmuxa, Y => N_7); - - \r.txstate_RNO_0[0]\ : MX2 - port map(A => \txstate[0]\, B => N_650, S => txtick, Y => - N_560); - - scaler_I_40 : XOR2 - port map(A => \scaler[17]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[17]\); - - \r.tcnt_RNI73NE[1]\ : OR2A - port map(A => \tcnt[1]\, B => \tcnt[0]\, Y => - rxen_0_sqmuxa_0); - - \r.brate_RNO_0[12]\ : MX2 - port map(A => \brate_1_iv[12]\, B => \un1_dcom0[14]\, S => - brate_2_sqmuxa, Y => N_413); - - \uartop.op_gt.v.brate2_0_I_52\ : AO1 - port map(A => \DWACT_CMPLE_PO0_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO0_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO0_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[0]\); - - \r.scaler_RNO_3[10]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[10]\, Y => - N_725); - - \r.scaler_RNO[4]\ : NOR3 - port map(A => \scaler_i_m[4]\, B => \brate_i_m[4]\, C => - \scaler_1_0_iv_0[4]\, Y => \scaler_1_0_iv[4]\); - - \r.rxen_RNI4SKBP\ : OR2B - port map(A => scaler_0_sqmuxa, B => brate_0_sqmuxa, Y => - scaler_0_sqmuxa_1); - - \r.brate_RNO_3[12]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(12), Y => N_707); - - \r.brate[10]\ : DFN1 - port map(D => \brate_RNO[10]\, CLK => lclk_c, Q => - \un1_dcom0[12]\); - - \r.rxen_RNI30QL3\ : NOR3B - port map(A => \scaler7[0]\, B => brate_0_sqmuxa, C => - enable, Y => scaler_4_sqmuxa); - - \uartop.op_gt.v.brate2_0_I_38\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \r.brate[4]\ : DFN1 - port map(D => \brate_RNO[4]\, CLK => lclk_c, Q => - \un1_dcom0[6]\); - - scaler_I_110 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_5[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_6[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_2[0]\); - - \r.rshift_RNO_0[1]\ : MX2 - port map(A => \rshift[1]\, B => \rshift[2]\, S => - rshift_0_sqmuxa, Y => N_440); - - \r.brate_RNI84ES[5]\ : NOR3C - port map(A => tcnt8_3_i, B => tcnt8_1_i, C => tcnt8_NE_3, Y - => tcnt8_NE_8); - - \r.scaler_RNO_0[8]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[8]\, Y => - N_733); - - \r.txclk_RNO[1]\ : XA1B - port map(A => N_680_i_1, B => \txclk[1]\, C => N_21_1, Y - => N_19); - - \r.rxen_RNO_0\ : MX2 - port map(A => rxen_1, B => enable, S => rxen_1_sqmuxa_1, Y - => N_428); - - scaler_I_35 : XOR2 - port map(A => \scaler[7]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_6[0]\); - - \r.scaler_RNO[8]\ : NOR3 - port map(A => N_733, B => N_734, C => - \scaler_1_0_iv_0_0[8]\, Y => \scaler_1_0_iv[8]\); - - scaler_I_73 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[10]\, B => - \DWACT_ADD_CI_0_g_array_11_1[0]\, Y => \scaler_0[10]\); - - \r.txstate_RNI6D5T[1]\ : OR2B - port map(A => rstn, B => N_64, Y => N_21_1); - - \r.thempty_RNO_0\ : OA1A - port map(A => N_64, B => \thempty\, C => write, Y => N_437); - - scaler_I_11 : AND2 - port map(A => \scaler[4]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_4[0]\); - - \r.scaler[0]\ : DFN1E0 - port map(D => \scaler_1_0_iv[0]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[0]\); - - \r.rxf[4]\ : DFN1 - port map(D => \rxf_RNO[4]\, CLK => lclk_c, Q => \rxf[4]\); - - scaler_I_80 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_10[0]\, B => - \DWACT_ADD_CI_0_g_array_0_10[0]\, C => - \DWACT_ADD_CI_0_g_array_0_11[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_5[0]\); - - \r.scaler[6]\ : DFN1E0 - port map(D => \scaler_1_0_iv[6]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[6]\); - - \r.brate_RNI02AF[9]\ : XA1A - port map(A => \scaler[9]\, B => \un1_dcom0[11]\, C => - tcnt8_8_i, Y => tcnt8_NE_3); - - \r.brate_RNIOON8[13]\ : XNOR2 - port map(A => \un1_dcom0[15]\, B => \scaler[13]\, Y => - tcnt8_9_i); - - \r.brate_RNIG5H6[5]\ : NOR2B - port map(A => \un1_dcom0[7]\, B => \N_127\, Y => prdata_5); - - \r.brate_RNO_2[0]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[4]\, C => - \apbi_i_m[50]\, Y => \brate_1_iv_0[0]\); - - \r.brate_RNO_1[4]\ : OA1B - port map(A => \scaler[4]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0_0[4]\, Y => \brate_1_iv[4]\); - - \r.brate_RNO_0[9]\ : MX2 - port map(A => \brate_1_iv[9]\, B => \un1_dcom0[11]\, S => - brate_2_sqmuxa, Y => N_410); - - \r.scaler_RNO_3[8]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[12]\, Y => - N_732); - - \r.brate_RNO_2[8]\ : AO1A - port map(A => pwdata_0(8), B => brate_1_sqmuxa, C => N_706, - Y => \brate_1_iv_0_0[8]\); - - \r.tick_RNICIQQ\ : NOR2 - port map(A => tick, B => N_133, Y => rxclk_1_sqmuxa_1); - - \r.brate_RNO_0[8]\ : MX2 - port map(A => \brate_1_iv[8]\, B => \un1_dcom0[10]\, S => - brate_2_sqmuxa, Y => N_409); - - \r.brate_RNO[1]\ : OR2A - port map(A => rstn, B => N_402, Y => \brate_RNO[1]\); - - scaler_I_18 : AND2 - port map(A => \scaler[1]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_1[0]\); - - \r.brate_RNO[17]\ : OR2A - port map(A => rstn, B => N_418, Y => \brate_RNO[17]\); - - \r.tshift_RNO[9]\ : OA1A - port map(A => N_77, B => \tshift[9]\, C => N_64, Y => - \tshift_10_0_iv[9]\); - - \r.brate_RNIOIU21[10]\ : NOR3C - port map(A => tcnt8_6_i, B => N_56_i_i, C => tcnt8_NE_5, Y - => tcnt8_NE_9); - - scaler_I_43 : XOR2 - port map(A => \scaler[13]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[13]\); - - \r.rxdb_RNI18AI[1]\ : NOR2A - port map(A => N_61_0, B => rxdb_1, Y => break_0_sqmuxa); - - \r.scaler_RNO_3[9]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[13]\, Y => - N_728); - - \r.brate_RNI6IUD1[4]\ : NOR3C - port map(A => tcnt8_NE_1, B => tcnt8_NE_0, C => tcnt8_NE_6, - Y => tcnt8_NE_10); - - \r.scaler_RNO_0[9]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[9]\, Y => - N_729); - - \r.brate[6]\ : DFN1 - port map(D => \brate_RNO[6]\, CLK => lclk_c, Q => - \un1_dcom0[8]\); - - \r.rsempty_RNIS9GD\ : OR3 - port map(A => \dready\, B => rsempty, C => N_622, Y => - dready_0_sqmuxa); - - \r.scaler_RNO[10]\ : NOR3 - port map(A => N_724, B => N_727, C => - \scaler_1_0_iv_0_1[10]\, Y => \scaler_1_0_iv[10]\); - - \r.scaler[9]\ : DFN1E0 - port map(D => \scaler_1_0_iv[9]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[9]\); - - \uartop.un1_apbi_1\ : NOR3A - port map(A => psel_1(7), B => N_78_0, C => un1_apbi_0, Y - => un1_apbi_1); - - \r.brate[2]\ : DFN1 - port map(D => \brate_RNO[2]\, CLK => lclk_c, Q => - \un1_dcom0[4]\); - - \r.txtick_RNO\ : NOR3C - port map(A => txtick_0_i_0, B => CO1, C => N_64, Y => - txtick_RNO); - - \v.frame_0_sqmuxa_0_a2\ : NOR3B - port map(A => N_769, B => un1_apbi_1, C => N_6455, Y => - frame_0_sqmuxa); - - scaler_I_7 : AND2 - port map(A => \scaler[16]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_16[0]\); - - scaler_I_19 : AND2 - port map(A => \scaler[8]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_8[0]\); - - \r.scaler_RNI05N2S[16]\ : NOR2A - port map(A => \scaler_0[17]\, B => \scaler[16]\, Y => - un1_scaler); - - scaler_I_66 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[15]\, B => - \DWACT_ADD_CI_0_g_array_12_6[0]\, Y => \scaler_0[15]\); - - scaler_I_34 : XOR2 - port map(A => \scaler[9]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_8[0]\); - - \r.rhold[4]\ : DFN1E1 - port map(D => \rshift[4]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(4)); - - \r.rhold[3]\ : DFN1E1 - port map(D => \rshift[3]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(3)); - - \r.tcnt_RNIKFPA4[1]\ : AO1D - port map(A => rxen_0_sqmuxa_0, B => tcnt9, C => N_61_0, Y - => brate_1_sqmuxa_2); - - \uartop.op_gt.v.brate2_0_I_44\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \r.scaler_RNO_3[5]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[5]\, Y => - N_740); - - \r.scaler_RNO_3[1]\ : NOR2 - port map(A => N_697, B => pwdata_0(1), Y => - \apbi_i_m_0[51]\); - - \r.rxdb_RNIQ4J3[1]\ : OR2B - port map(A => \rxdb[1]\, B => break, Y => rxdb_1); - - \r.scaler_RNO_1[9]\ : NOR2 - port map(A => \un1_dcom0[11]\, B => scaler_0_sqmuxa_1, Y - => N_730); - - \uartop.op_gt.v.brate2_0_I_27\ : AO1A - port map(A => \scaler[16]\, B => \un1_dcom0[18]\, C => - \un1_dcom0[19]\, Y => \ACT_LT2_E[2]\); - - \r.tshift_RNO_0[7]\ : NOR2 - port map(A => \thold[6]\, B => N_64, Y => N_107); - - \r.rsempty_RNO_0\ : MX2 - port map(A => rsempty, B => rsempty_1, S => rxstate_1, Y - => N_420); - - \r.rxdb_RNIACTG3[1]\ : NOR2 - port map(A => tcnt9, B => rxdb_3, Y => tcnt_0_sqmuxa); - - scaler_I_83 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_2[0]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, C => - \DWACT_ADD_CI_0_g_array_2_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_3[0]\); - - scaler_I_22 : XOR2 - port map(A => \scaler[15]\, B => N_61, Y => - \DWACT_ADD_CI_0_pog_array_0_14[0]\); - - \r.txclk_RNO_0[0]\ : OR2B - port map(A => N_680_i_1, B => N_64, Y => N_112); - - scaler_I_52 : XOR2 - port map(A => \scaler[10]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[10]\); - - \r.brate_RNO_2[5]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[9]\, C => - \apbi_i_m[55]\, Y => \brate_1_iv_0[5]\); - - \r.rshift_RNO_0[4]\ : MX2 - port map(A => \rshift[4]\, B => \rshift[5]\, S => - rshift_0_sqmuxa, Y => N_443); - - \r.scaler_RNO_2[6]\ : AO1D - port map(A => N_697, B => pwdata_0(6), C => - \scaler_i_m_1[10]\, Y => \scaler_1_0_iv_0[6]\); - - \r.rshift_RNO[5]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_444, Y => - \rshift_RNO[5]\); - - \un1_v.tcnt_0_sqmuxa_1_1_CO0\ : OR2B - port map(A => tcnt_0_sqmuxa_1, B => \tcnt[0]\, Y => CO0); - - \r.rxstate_RNI7QOB_1[0]\ : OR2 - port map(A => \rxstate[1]\, B => \rxstate[0]\, Y => N_622); - - \r.brate_RNO_2[9]\ : AO1A - port map(A => pwdata_0(9), B => brate_1_sqmuxa, C => - \scaler_i_m[13]\, Y => \brate_1_iv_0[9]\); - - \r.brate_RNI41I6[6]\ : XNOR2 - port map(A => \un1_dcom0[8]\, B => \scaler[6]\, Y => - N_54_i_i); - - \r.scaler_RNO_1[2]\ : OR2A - port map(A => \scaler[2]\, B => scaler_1_sqmuxa, Y => N_743); - - \apbi_m[51]\ : NOR2B - port map(A => rxen_1_sqmuxa, B => pwdata_0(1), Y => - \apbi_m[51]_net_1\); - - \r.txstate_RNO[0]\ : NOR2B - port map(A => rstn, B => N_560, Y => N_560s); - - \r.brate_RNO_3[4]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[8]\, Y => - N_78); - - scaler_I_100 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_11[0]\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, C => - \DWACT_ADD_CI_0_g_array_0_12[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_5[0]\); - - \r.rxstate_RNO[0]\ : AOI1B - port map(A => \rxstate_ns_0_0[0]\, B => rxstate_0_sqmuxa, C - => rstn, Y => \rxstate_nss[0]\); - - \r.scaler_RNO[0]\ : NOR3 - port map(A => \scaler_i_m[0]\, B => \brate_i_m[0]\, C => - \scaler_1_0_iv_0[0]\, Y => \scaler_1_0_iv[0]\); - - \r.frame_RNI2V0A\ : MX2 - port map(A => frame, B => \un1_dcom0[8]\, S => N_6455_0, Y - => N_333); - - \r.tshift_RNO[3]\ : NOR3 - port map(A => N_95, B => N_94, C => N_93, Y => N_31); - - \r.scaler_RNO_1[3]\ : NOR2 - port map(A => \un1_dcom0[5]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[3]\); - - \r.rxdb_RNI2MHSC[1]\ : OR3B - port map(A => tcnt9, B => brate2, C => rxdb_3, Y => - tcnt_1_sqmuxa); - - \r.txstate_RNICHPR[1]\ : OR2A - port map(A => thempty_1_sqmuxa_1_i_o2_0, B => N_59, Y => - N_64); - - \uartop.op_gt.v.brate2_0_I_20\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E_0[1]\, B => - \DWACT_BL_EQUAL_0_E_0[0]\, Y => - \DWACT_CMPLE_PO0_DWACT_COMP0_E[1]\); - - scaler_I_10 : AND2 - port map(A => \scaler[10]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_10[0]\); - - \r.rhold[0]\ : DFN1E1 - port map(D => \rshift[0]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(0)); - - \r.tshift_RNO_2[4]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[4]\, Y => - N_96); - - \r.txclk[2]\ : DFN1E1 - port map(D => N_21, CLK => lclk_c, E => N_15, Q => - \txclk[2]\); - - \r.brate[15]\ : DFN1 - port map(D => \brate_RNO[15]\, CLK => lclk_c, Q => - \un1_dcom0[17]\); - - \r.brate_RNO_4[2]\ : NOR2 - port map(A => brate_1_sqmuxa_4, B => \scaler_0[2]\, Y => - N_74); - - \r.scaler_RNO[14]\ : NOR3A - port map(A => scaler_2_sqmuxa, B => \scaler_1_0_iv_0[14]\, - C => \scaler_i_m[14]\, Y => \scaler_1_0_iv[14]\); - - \r.tshift_RNIUUEJ[2]\ : NOR3C - port map(A => \tshift[3]\, B => \tshift[2]\, C => - \txstate[0]\, Y => \tshift_1_0_a2_4[0]\); - - \r.scaler_RNO_3[7]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[11]\, Y => - N_737); - - \r.fedge_RNI8OIL\ : MX2A - port map(A => fedge, B => rxdb_1, S => N_61_0, Y => - \scaler7[0]\); - - \r.scaler_RNO_2[11]\ : AO1D - port map(A => scaler_2_sqmuxa, B => \scaler[15]\, C => - N_723, Y => \scaler_1_0_iv_0_0[11]\); - - \r.scaler_RNO_0[3]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[3]\, Y => - \scaler_i_m[3]\); - - \r.scaler_RNO_0[13]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[13]\, Y => - \scaler_i_m_0[13]\); - - \uartop.op_gt.v.brate2_0_I_84\ : AO1C - port map(A => \scaler[6]\, B => \un1_dcom0[8]\, C => N_12, - Y => N_18); - - \r.rxen_RNI0C1J\ : MX2C - port map(A => enable, B => N_328, S => rdata60_1, Y => - prdata_0); - - \uartop.op_gt.v.brate2_0_I_2\ : XNOR2 - port map(A => \scaler[15]\, B => \un1_dcom0[17]\, Y => - \DWACT_BL_EQUAL_0_E[3]\); - - \uartop.op_gt.v.brate2_0_I_40\ : NOR2A - port map(A => \un1_dcom0[17]\, B => \scaler[15]\, Y => - \ACT_LT4_E[5]\); - - \uartop.op_gt.v.brate2_0_I_71\ : AOI1A - port map(A => \ACT_LT3_E[3]\, B => \ACT_LT3_E[4]\, C => - \ACT_LT3_E[5]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \r.scaler_RNO_3[12]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[16]\, Y => - N_716); - - \r.brate_RNO_2[6]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[10]\, Y => - \scaler_i_m[10]\); - - \r.brate_RNO[15]\ : OR2A - port map(A => rstn, B => N_416, Y => \brate_RNO[15]\); - - \r.brate_RNO[13]\ : OR2A - port map(A => rstn, B => N_414, Y => \brate_RNO[13]\); - - \r.tsempty_RNO\ : OR2A - port map(A => rstn, B => N_447, Y => tsempty_RNO); - - \r.scaler_RNO_1[0]\ : NOR2 - port map(A => \un1_dcom0[2]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[0]\); - - \r.rhold[5]\ : DFN1E1 - port map(D => \rshift[5]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(5)); - - \uartop.op_gt.v.brate2_0_I_4\ : XNOR2 - port map(A => \scaler[17]\, B => \un1_dcom0[19]\, Y => - \DWACT_BL_EQUAL_0_E[5]\); - - \r.tcnt_RNICPDMD[1]\ : OR2 - port map(A => brate_1_sqmuxa_2, B => brate2, Y => - brate_1_sqmuxa_3); - - \r.scaler_RNO_1[8]\ : NOR2 - port map(A => \un1_dcom0[10]\, B => scaler_0_sqmuxa_1, Y - => N_734); - - \r.brate_RNI8PSD[9]\ : MX2 - port map(A => \tcnt[1]\, B => \un1_dcom0[11]\, S => - N_6455_0, Y => N_336); - - \uartop.op_gt.v.brate2_0_I_87\ : OA1A - port map(A => N_16, B => N_18, C => N_17, Y => N_21_0); - - \r.scaler_RNO_2[4]\ : AO1D - port map(A => N_697, B => pwdata_0(4), C => - \scaler_i_m_1[8]\, Y => \scaler_1_0_iv_0[4]\); - - \r.scaler_RNO_0[10]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[14]\, Y => - N_724); - - \r.scaler_RNO_0[0]\ : NOR2A - port map(A => \scaler[0]\, B => scaler_1_sqmuxa, Y => - \scaler_i_m[0]\); - - \r.rxf_RNO[3]\ : MX2 - port map(A => \rxf[3]\, B => \rxf[2]\, S => N_62, Y => - \rxf_RNO[3]\); - - \r.rxen_RNICNRV6\ : OR3B - port map(A => rxen_0_sqmuxa_1, B => brate_0_sqmuxa, C => - enable, Y => scaler_2_sqmuxa); - - \r.fedge\ : DFN1 - port map(D => fedge_RNO, CLK => lclk_c, Q => fedge); - - scaler_I_13 : AND2 - port map(A => \scaler[9]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_9[0]\); - - \r.ovf_RNO_0\ : MX2 - port map(A => ovf, B => pwdata_1(4), S => frame_0_sqmuxa, Y - => N_438); - - \r.thempty_RNO\ : OR2A - port map(A => rstn, B => N_437, Y => thempty_RNO); - - \r.frame_RNO_1\ : AO1 - port map(A => break10_i_0, B => N_702_1, C => pwdata_0(6), - Y => frame_1); - - \r.brate[8]\ : DFN1 - port map(D => \brate_RNO[8]\, CLK => lclk_c, Q => - \un1_dcom0[10]\); - - \r.rshift[5]\ : DFN1 - port map(D => \rshift_RNO[5]\, CLK => lclk_c, Q => - \rshift[5]\); - - un2_rxclk_1_SUM2_0 : AX1C - port map(A => \rxclk[0]\, B => \rxclk[1]\, C => \rxclk[2]\, - Y => N_677); - - \r.rshift_RNO[6]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_445, Y => - \rshift_RNO[6]\); - - scaler_I_72 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[3]\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => \scaler_0[3]\); - - scaler_I_25 : XOR2 - port map(A => \scaler[13]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_12[0]\); - - \r.rxstate[1]\ : DFN1 - port map(D => \rxstate_nss[1]\, CLK => lclk_c, Q => - \rxstate[1]\); - - \r.brate_RNO_0[5]\ : MX2 - port map(A => \brate_1_iv[5]\, B => \un1_dcom0[7]\, S => - brate_2_sqmuxa, Y => N_406); - - \r.tshift[5]\ : DFN1 - port map(D => \tshift_RNO[5]\, CLK => lclk_c, Q => - \tshift[5]\); - - \r.rxclk_RNO[0]\ : NOR2 - port map(A => \rxclk[0]\, B => N_133, Y => \rxclk_1[0]\); - - scaler_I_55 : XOR2 - port map(A => \scaler[9]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[9]\); - - \r.rsempty_RNO_1\ : MX2C - port map(A => rsempty_2, B => rsempty_0_sqmuxa_2, S => - rsempty_RNO_4, Y => rsempty_1); - - scaler_I_61 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[4]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => \scaler_0[4]\); - - GND_i : GND - port map(Y => \GND\); - - \r.rshift_RNO_0[7]\ : MX2 - port map(A => \rshift[7]\, B => \rxdb[0]\, S => - rshift_0_sqmuxa, Y => N_446); - - \r.brate_RNO_2[7]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[11]\, C => - \apbi_i_m[57]\, Y => \brate_1_iv_0[7]\); - - scaler_I_95 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_3[0]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, C => - \DWACT_ADD_CI_0_g_array_3_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_4[0]\); - - \r.rxf[1]\ : DFN1 - port map(D => \rxf[0]\, CLK => lclk_c, Q => \rxf[1]\); - - \r.tshift_RNO_1[5]\ : NOR2 - port map(A => \tshift[6]\, B => N_77, Y => N_100); - - scaler_I_68 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[2]\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => \scaler[2]\); - - \r.tcnt[0]\ : DFN1 - port map(D => \tcnt_RNO[0]\, CLK => lclk_c, Q => \tcnt[0]\); - - scaler_I_42 : XOR2 - port map(A => \scaler[5]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[5]\); - - \r.scaler_RNO_1[11]\ : NOR2 - port map(A => \un1_dcom0[13]\, B => scaler_0_sqmuxa_1, Y - => N_722); - - \r.rxstate_RNO_1[0]\ : OR2A - port map(A => rxtick, B => \rshift[0]\, Y => - \rxstate_ns_0_a3_0_0[0]\); - - \r.break_RNO_1\ : AO1 - port map(A => frame_0_sqmuxa, B => pwdata_0(3), C => N_701, - Y => break_1); - - \uartop.op_gt.v.brate2_0_I_80\ : NOR2A - port map(A => \un1_dcom0[6]\, B => \scaler[4]\, Y => N_14); - - \r.brate_RNO_3[1]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(1), Y => - \apbi_i_m[51]\); - - \uartop.op_gt.v.brate2_0_I_66\ : OR2A - port map(A => \un1_dcom0[12]\, B => \scaler[10]\, Y => - \ACT_LT3_E[1]\); - - \r.rxtick_RNI0M9D\ : OR3C - port map(A => \rxstate[1]\, B => \rxstate[0]\, C => rxtick, - Y => N_629); - - scaler_I_37 : XOR2 - port map(A => \scaler[8]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_7[0]\); - - \r.brate[11]\ : DFN1 - port map(D => \brate_RNO[11]\, CLK => lclk_c, Q => - \un1_dcom0[13]\); - - \r.frame_RNO_2\ : AO1 - port map(A => break10_i_0, B => N_702_1, C => - frame_0_sqmuxa, Y => N_9); - - \r.tshift[8]\ : DFN1 - port map(D => \tshift_RNO[8]\, CLK => lclk_c, Q => - \tshift[8]\); - - \r.rxclk_RNO[1]\ : XA1B - port map(A => \rxclk[0]\, B => \rxclk[1]\, C => N_133, Y - => \rxclk_1[1]\); - - \r.brate[17]\ : DFN1 - port map(D => \brate_RNO[17]\, CLK => lclk_c, Q => - \un1_dcom0[19]\); - - scaler_I_69 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[8]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, Y => \scaler_0[8]\); - - \r.scaler[7]\ : DFN1E0 - port map(D => \scaler_1_0_iv[7]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[7]\); - - \r.brate_RNO_0[4]\ : MX2 - port map(A => \brate_1_iv[4]\, B => \un1_dcom0[6]\, S => - brate_2_sqmuxa, Y => N_405); - - \uartop.op_gt.v.brate2_0_I_43\ : OR2A - port map(A => \scaler[15]\, B => \un1_dcom0[17]\, Y => - \ACT_LT4_E[8]\); - - \uartop.op_gt.v.brate2_0_I_28\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO0_DWACT_COMP0_E[0]\); - - \r.scaler_RNO_0[7]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[7]\, Y => - N_736); - - \r.brate_RNIQSN8[14]\ : XNOR2 - port map(A => \un1_dcom0[16]\, B => \scaler[14]\, Y => - N_56_i_i); - - scaler_I_24 : XOR2 - port map(A => \scaler[6]\, B => N_61, Y => - \DWACT_ADD_CI_0_pog_array_0_5[0]\); - - \uartop.op_gt.v.brate2_0_I_8\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E[3]\, B => - \DWACT_BL_EQUAL_0_E[4]\, C => \DWACT_BL_EQUAL_0_E[5]\, Y - => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \r.scaler_RNO_3[14]\ : OR2 - port map(A => \un1_dcom0[16]\, B => brate_1_sqmuxa, Y => - brate_i_m_14_m1_e_0); - - scaler_I_54 : XOR2 - port map(A => \scaler[14]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[14]\); - - \r.brate_RNO_0[10]\ : MX2 - port map(A => \brate_1_iv[10]\, B => \un1_dcom0[12]\, S => - brate_2_sqmuxa, Y => N_411); - - \r.txclk[0]\ : DFN1E1 - port map(D => N_690, CLK => lclk_c, E => N_15, Q => - N_680_i_1); - - \r.rsempty_RNO\ : OR2A - port map(A => rstn, B => N_420, Y => rsempty_RNO); - - \r.brate_RNO[10]\ : OR2A - port map(A => rstn, B => N_411, Y => \brate_RNO[10]\); - - \r.scaler_RNO_3[6]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[10]\, Y => - \scaler_i_m_1[10]\); - - \r.scaler_RNO_0[17]\ : NOR2 - port map(A => N_697, B => pwdata(17), Y => \apbi_i_m[67]\); - - \r.brate_RNO_3[10]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(10), Y => N_82); - - \r.rxf[3]\ : DFN1 - port map(D => \rxf_RNO[3]\, CLK => lclk_c, Q => \rxf[3]\); - - scaler_I_82 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, C => - \DWACT_ADD_CI_0_g_array_1_4[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_1[0]\); - - \r.rxtick_0_0_a5_RNO\ : AND2 - port map(A => tick, B => \rxclk[2]\, Y => rxtick_0_0_a5_0); - - \r.rxdb_RNIEDED[0]\ : NOR2 - port map(A => \rxdb[0]\, B => N_629, Y => N_702_1); - - \r.rshift[0]\ : DFN1 - port map(D => \rshift_RNO[0]\, CLK => lclk_c, Q => - \rshift[0]\); - - \r.brate_RNO_1[0]\ : OA1B - port map(A => \scaler[0]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[0]\, Y => \brate_1_iv[0]\); - - \r.tshift[0]\ : DFN1 - port map(D => \tshift_1[0]\, CLK => lclk_c, Q => \dsutx_c\); - - \r.scaler_RNIBB0LS[16]\ : OR3A - port map(A => rxdb_3, B => N_61_0, C => un1_scaler, Y => - scaler_2_sqmuxa_1); - - \r.scaler_RNO_1[1]\ : NOR2 - port map(A => \un1_dcom0[3]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[1]\); - - \uartop.op_gt.v.brate2_0_I_65\ : NOR2A - port map(A => \un1_dcom0[11]\, B => \scaler[9]\, Y => - \ACT_LT3_E[0]\); - - \r.thempty\ : DFN1 - port map(D => thempty_RNO, CLK => lclk_c, Q => \thempty\); - - scaler_I_94 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_7[0]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, C => - \DWACT_ADD_CI_0_g_array_0_8[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_3[0]\); - - \r.rxen_RNIF7L0M1\ : OR2A - port map(A => brate_0_sqmuxa, B => \scaler_2_sqmuxa[0]\, Y - => scaler_1_sqmuxa); - - \r.thold[2]\ : DFN1E0 - port map(D => hwdata(26), CLK => lclk_c, E => write, Q => - \thold[2]\); - - \r.brate_RNO_0[6]\ : MX2 - port map(A => \brate_1_iv[6]\, B => \un1_dcom0[8]\, S => - brate_2_sqmuxa, Y => N_407); - - \r.rhold[6]\ : DFN1E1 - port map(D => \rshift[6]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(6)); - - \r.tshift_RNO_2[5]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[5]\, Y => - N_99); - - \r.brate_RNO_0[14]\ : MX2 - port map(A => \brate_1[14]\, B => \un1_dcom0[16]\, S => - brate_2_sqmuxa, Y => N_415); - - \r.tsempty_RNI6SR6\ : MX2C - port map(A => tsempty, B => \un1_dcom0[3]\, S => N_6455, Y - => N_329); - - \r.rxstate_RNI7QOB[0]\ : OR2A - port map(A => \rxstate[1]\, B => \rxstate[0]\, Y => N_640_2); - - \r.dready\ : DFN1 - port map(D => dready_RNO, CLK => lclk_c, Q => \dready\); - - \r.brate[0]\ : DFN1 - port map(D => \brate_RNO[0]\, CLK => lclk_c, Q => - \un1_dcom0[2]\); - - \r.tcnt_RNI73NE_0[1]\ : NOR2B - port map(A => \tcnt[1]\, B => \tcnt[0]\, Y => N_61_1); - - \r.tshift_RNO_2[6]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[6]\, Y => - N_102); - - \r.brate_RNO[0]\ : OR2A - port map(A => rstn, B => N_401, Y => \brate_RNO[0]\); - - scaler_I_106 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_7[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_8[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_3[0]\); - - \r.rxclk[2]\ : DFN1E0 - port map(D => N_23, CLK => lclk_c, E => rxclk_1_sqmuxa_1, Q - => \rxclk[2]\); - - \r.fedge_RNI7LV5S\ : OR2B - port map(A => un1_scaler, B => fedge, Y => fedge_0_sqmuxa); - - \r.tshift_RNO_2[3]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[3]\, Y => - N_93); - - \r.rxstate_RNO[1]\ : AOI1B - port map(A => N_642, B => N_628, C => rstn, Y => - \rxstate_nss[1]\); - - \r.tshift_RNIUJ6R[4]\ : NOR3C - port map(A => \tshift[5]\, B => \tshift[4]\, C => - \tshift_1_0_a2_2[0]\, Y => \tshift_1_0_a2_5[0]\); - - \r.rshift_RNO[2]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_441, Y => - \rshift_RNO[2]\); - - \r.brate_RNO_2[1]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[5]\, Y => - \scaler_i_m[5]\); - - \r.brate_RNO_1[3]\ : OA1B - port map(A => \scaler[3]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[3]\, Y => \brate_1_iv[3]\); - - \r.brate_RNO_2[11]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[15]\, C => - \apbi_i_m[61]\, Y => \brate_1_iv_0[11]\); - - scaler_I_75 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0[0]\, B => - \scaler[0]\, C => \DWACT_ADD_CI_0_g_array_0_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_1[0]\); - - scaler_I_113 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_1[0]\); - - \r.rxen\ : DFN1 - port map(D => rxen_RNO, CLK => lclk_c, Q => enable); - - \r.rxdb_RNIDCQB3[1]\ : OR2B - port map(A => break_0_sqmuxa, B => brate_0_sqmuxa, Y => - brate_3_sqmuxa_i); - - \r.brate_RNO_0[7]\ : MX2 - port map(A => \brate_1_iv[7]\, B => \un1_dcom0[9]\, S => - brate_2_sqmuxa, Y => N_408); - - \r.txtick\ : DFN1 - port map(D => txtick_RNO, CLK => lclk_c, Q => txtick); - - \r.scaler[10]\ : DFN1E0 - port map(D => \scaler_1_0_iv[10]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[10]\); - - \r.scaler_RNO[5]\ : NOR3 - port map(A => N_741, B => N_122, C => - \scaler_1_0_iv_0_1[5]\, Y => \scaler_1_0_iv[5]\); - - \r.scaler_RNO[13]\ : NOR3 - port map(A => \scaler_i_m_0[13]\, B => \brate_i_m[13]\, C - => \scaler_1_0_iv_0[13]\, Y => \scaler_1_0_iv[13]\); - - \uartop.op_gt.v.brate2_0_I_83\ : OA1A - port map(A => \scaler[7]\, B => \un1_dcom0[9]\, C => N_13, - Y => N_17); - - \r.brate_RNO_0[13]\ : MX2 - port map(A => \brate_1_iv[13]\, B => \un1_dcom0[15]\, S => - brate_2_sqmuxa, Y => N_414); - - \r.tshift_RNO[5]\ : NOR3 - port map(A => N_101, B => N_100, C => N_99, Y => - \tshift_RNO[5]\); - - \r.ovf_RNO_1\ : NOR2A - port map(A => rsempty_2, B => rxstate_0_sqmuxa, Y => - ovf_0_sqmuxa); - - \r.brate_RNO_3[13]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[17]\, Y => - \scaler_i_m_1[17]\); - - \r.brate_RNO_0[2]\ : MX2 - port map(A => \brate_1_iv[2]\, B => \un1_dcom0[4]\, S => - brate_2_sqmuxa, Y => N_403); - - scaler_I_45 : XOR2 - port map(A => \scaler[12]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[12]\); - - \r.rshift[3]\ : DFN1 - port map(D => \rshift_RNO[3]\, CLK => lclk_c, Q => - \rshift[3]\); - - \r.scaler_RNI9KDBM[15]\ : NOR2A - port map(A => \scaler_0[15]\, B => \scaler[15]\, Y => - tick_2); - - \r.tshift[3]\ : DFN1 - port map(D => N_31, CLK => lclk_c, Q => \tshift[3]\); - - \r.brate_RNO_0[15]\ : MX2 - port map(A => \brate_1[15]\, B => \un1_dcom0[17]\, S => - brate_2_sqmuxa, Y => N_416); - - \r.txclk_RNO[0]\ : NOR3C - port map(A => N_112, B => tick, C => rstn, Y => N_690); - - \r.scaler_RNO_1[4]\ : NOR2 - port map(A => \un1_dcom0[6]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[4]\); - - \uartop.op_gt.v.brate2_0_I_88\ : OA1 - port map(A => N_21_0, B => N_20, C => N_19_0, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - \r.rxdb_RNIAKP32[0]\ : NOR2A - port map(A => N_702_1, B => break10_i_0, Y => N_701); - - \r.tshift_RNO_1[1]\ : NOR2 - port map(A => \tshift[2]\, B => N_77, Y => N_88); - - \r.scaler_RNO_0[12]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[12]\, Y => - N_717); - - \r.rsempty_RNILFN1\ : NOR2A - port map(A => \dready\, B => rsempty, Y => rsempty_2); - - \r.tshift_RNO_0[0]\ : OA1A - port map(A => txtick, B => N_138_i, C => N_123, Y => - \tshift_1_0_0[0]\); - - \r.rxen_RNO\ : OA1 - port map(A => N_428, B => rxen_0_sqmuxa_2, C => rstn, Y => - rxen_RNO); - - \r.thold[4]\ : DFN1E0 - port map(D => hwdata(28), CLK => lclk_c, E => write, Q => - \thold[4]\); - - \r.tshift_RNO_0[6]\ : NOR2 - port map(A => \thold[5]\, B => N_64, Y => N_104); - - \r.txclk_RNO[2]\ : XA1B - port map(A => \txclk[2]\, B => CO1, C => N_21_1, Y => N_21); - - \r.rxf_RNO[2]\ : MX2 - port map(A => \rxf[2]\, B => \rxf[1]\, S => N_62, Y => - \rxf_RNO[2]\); - - scaler_I_74 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[17]\, B => - \DWACT_ADD_CI_0_g_array_12_7[0]\, Y => \scaler_0[17]\); - - \r.scaler_RNO_2[13]\ : AO1D - port map(A => N_697, B => pwdata_0(13), C => - \scaler_i_m_0[17]\, Y => \scaler_1_0_iv_0[13]\); - - \r.rhold[1]\ : DFN1E1 - port map(D => \rshift[1]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(1)); - - \r.scaler_RNO_3[2]\ : OR2A - port map(A => \un1_dcom0[4]\, B => scaler_0_sqmuxa_1, Y => - N_744); - - \r.brate_RNO[12]\ : OR2A - port map(A => rstn, B => N_413, Y => \brate_RNO[12]\); - - scaler_I_12 : AND2 - port map(A => \scaler_0[2]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_2[0]\); - - \r.fedge_RNO_0\ : AXO5 - port map(A => un1_scaler, B => fedge, C => fedge_1_sqmuxa, - Y => N_400); - - scaler_I_63 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[5]\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => \scaler_0[5]\); - - \r.scaler_RNO_0[1]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[1]\, Y => - \scaler_i_m[1]\); - - \r.scaler[12]\ : DFN1E0 - port map(D => \scaler_1_0_iv[12]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[12]\); - - scaler_I_85 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_6[0]\, B => - \DWACT_ADD_CI_0_g_array_0_6[0]\, C => - \DWACT_ADD_CI_0_g_array_0_7[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_3[0]\); - - scaler_I_36 : XOR2 - port map(A => \scaler[16]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_15[0]\); - - \r.rxtick_RNIE3OQ\ : OR2B - port map(A => N_628, B => N_627, Y => rshift_0_sqmuxa); - - \r.brate_RNO_1[11]\ : OA1B - port map(A => \scaler[11]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[11]\, Y => \brate_1_iv[11]\); - - \r.rshift_RNO[7]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_446, Y => - \rshift_RNO[7]\); - - \r.brate_RNO_2[16]\ : AOI1B - port map(A => brate_1_sqmuxa, B => pwdata(16), C => - brate_3_sqmuxa_i, Y => \brate_1_iv_0[16]\); - - \r.rxen_RNIDC5K\ : OR2B - port map(A => rstn, B => rxstate_0_sqmuxa, Y => N_133); - - \r.rsempty_RNINR9C1\ : OAI1 - port map(A => N_629, B => rsempty_0_sqmuxa_1_1, C => - dready_0_sqmuxa, Y => dready_0_sqmuxa_0); - - \r.brate_RNO[4]\ : OR2A - port map(A => rstn, B => N_405, Y => \brate_RNO[4]\); - - \r.brate_RNO_2[17]\ : AOI1B - port map(A => brate_1_sqmuxa, B => pwdata(17), C => - brate_3_sqmuxa_i, Y => \brate_1_iv_0[17]\); - - \r.brate_RNI2TH6[5]\ : XNOR2 - port map(A => \un1_dcom0[7]\, B => \scaler[5]\, Y => - tcnt8_1_i); - - \uartop.op_gt.v.brate2_0_I_79\ : OR2A - port map(A => \scaler[6]\, B => \un1_dcom0[8]\, Y => N_13); - - \r.brate_RNO_3[3]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(3), Y => - \apbi_i_m[53]\); - - \r.tcnt[1]\ : DFN1 - port map(D => \tcnt_RNO[1]\, CLK => lclk_c, Q => \tcnt[1]\); - - \r.scaler_RNO[12]\ : NOR3 - port map(A => N_717, B => N_718, C => - \scaler_1_0_iv_0_0[12]\, Y => \scaler_1_0_iv[12]\); - - \r.brate_RNO[8]\ : OR2A - port map(A => rstn, B => N_409, Y => \brate_RNO[8]\); - - \r.rxstate_RNO_0[1]\ : AO1B - port map(A => rxtick, B => \rxstate[0]\, C => \rxstate[1]\, - Y => N_642); - - \r.thold[7]\ : DFN1E0 - port map(D => hwdata(31), CLK => lclk_c, E => write, Q => - \thold[7]\); - - \r.break_RNO\ : NOR2B - port map(A => rstn, B => N_419, Y => break_RNO); - - scaler_I_112 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_5[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_6[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_2[0]\); - - \r.txclk[1]\ : DFN1E1 - port map(D => N_19, CLK => lclk_c, E => N_15, Q => - \txclk[1]\); - - \r.thold[3]\ : DFN1E0 - port map(D => hwdata(27), CLK => lclk_c, E => write, Q => - \thold[3]\); - - \r.scaler_RNO_2[10]\ : AO1D - port map(A => \un1_dcom0[12]\, B => scaler_0_sqmuxa_1, C - => N_725, Y => \scaler_1_0_iv_0_1[10]\); - - \r.fedge_RNO\ : NOR2B - port map(A => rstn, B => N_400, Y => fedge_RNO); - - \r.brate_RNI6LSD[8]\ : MX2 - port map(A => \tcnt[0]\, B => \un1_dcom0[10]\, S => N_6455, - Y => N_335); - - \r.scaler[11]\ : DFN1E0 - port map(D => \scaler_1_0_iv[11]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[11]\); - - \uartop.op_gt.v.brate2_0_I_36\ : OR2A - port map(A => \un1_dcom0[15]\, B => \scaler[13]\, Y => - \ACT_LT4_E[1]\); - - \r.scaler_RNO_3[15]\ : OR3 - port map(A => \scaler_0[15]\, B => brate_1_sqmuxa, C => - \scaler_2_sqmuxa[0]\, Y => \scaler_RNO_3[15]\); - - scaler_I_114 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_13[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_14[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_6[0]\); - - \r.brate_RNIMKN8[12]\ : XNOR2 - port map(A => \un1_dcom0[14]\, B => \scaler[12]\, Y => - tcnt8_8_i); - - \r.scaler_RNO[15]\ : NOR3A - port map(A => scaler_2_sqmuxa, B => N_715, C => - \scaler_RNO_1[15]\, Y => \scaler_1_0_iv[15]\); - - \r.rxdb_RNIT8Q5H[1]\ : AOI1B - port map(A => brate_1_sqmuxa_3, B => \brate13[0]\, C => - brate_0_sqmuxa, Y => brate_2_sqmuxa); - - scaler_I_6 : AND2 - port map(A => \scaler[6]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_6[0]\); - - scaler_I_103 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_15[0]\, B => - \DWACT_ADD_CI_0_g_array_4[0]\, C => - \DWACT_ADD_CI_0_g_array_0_16[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_7[0]\); - - scaler_I_105 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1[0]\); - - \r.scaler_RNO_3[0]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[4]\, Y => - \scaler_i_m_1[4]\); - - scaler_I_27 : XOR2 - port map(A => \scaler[10]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_9[0]\); - - \r.tcnt_RNI73NE_1[1]\ : NOR2B - port map(A => \tcnt[1]\, B => \tcnt[0]\, Y => N_61_0); - - \r.brate_RNI4T9E[2]\ : MX2 - port map(A => \thempty\, B => \un1_dcom0[4]\, S => N_6455, - Y => N_330); - - \r.brate_RNO[5]\ : OR2A - port map(A => rstn, B => N_406, Y => \brate_RNO[5]\); - - \r.rxen_RNICM07\ : NOR2A - port map(A => enable, B => N_630, Y => rxdb_4); - - scaler_I_57 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[11]\, B => - \DWACT_ADD_CI_0_g_array_12_4[0]\, Y => \scaler_0[11]\); - - \uartop.op_gt.v.brate2_0_I_59\ : XNOR2 - port map(A => \scaler[11]\, B => \un1_dcom0[13]\, Y => - \DWACT_BL_EQUAL_0_E[2]\); - - \r.tshift_RNO[6]\ : NOR3 - port map(A => N_104, B => N_103, C => N_102, Y => - \tshift_RNO[6]\); - - scaler_I_84 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_12[0]\, B => - \DWACT_ADD_CI_0_g_array_0_12[0]\, C => - \DWACT_ADD_CI_0_g_array_0_13[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_6[0]\); - - \r.rxdb_RNO[0]\ : MAJ3 - port map(A => \rxf[2]\, B => \rxf[4]\, C => \rxf[3]\, Y => - N_8); - - \r.rshift_RNITHJD[6]\ : NOR2 - port map(A => \rshift[6]\, B => \rshift[7]\, Y => break10_3); - - \r.tshift_RNO_1[7]\ : NOR2 - port map(A => \tshift[8]\, B => N_77, Y => N_106); - - \r.brate_RNO_2[3]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[7]\, C => - \apbi_i_m[53]\, Y => \brate_1_iv_0[3]\); - - \r.brate_RNO_1[9]\ : OA1B - port map(A => \scaler[9]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[9]\, Y => \brate_1_iv[9]\); - - \r.brate_RNO_1[1]\ : NOR3 - port map(A => \scaler_i_m[5]\, B => \apbi_i_m[51]\, C => - \scaler_i_m_0[1]\, Y => \brate_1_iv[1]\); - - \r.rshift_RNO[4]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_443, Y => - \rshift_RNO[4]\); - - \r.ovf_RNO\ : OA1 - port map(A => N_438, B => ovf_0_sqmuxa, C => rstn, Y => - ovf_RNO); - - \r.brate_RNO_1[2]\ : NOR3 - port map(A => N_75, B => N_73, C => N_74, Y => - \brate_1_iv[2]\); - - \r.scaler_RNO_0[14]\ : AO1D - port map(A => N_697, B => pwdata_0(14), C => - \brate_i_m[14]\, Y => \scaler_1_0_iv_0[14]\); - - \r.txstate[0]\ : DFN1 - port map(D => N_560s, CLK => lclk_c, Q => \txstate[0]\); - - \r.tshift_RNO_0[3]\ : NOR2 - port map(A => \thold[2]\, B => N_64, Y => N_95); - - \r.scaler_RNO_1[13]\ : NOR2 - port map(A => \un1_dcom0[15]\, B => scaler_0_sqmuxa_1, Y - => \brate_i_m[13]\); - - \uartop.op_gt.v.brate2_0_I_57\ : XNOR2 - port map(A => \scaler[9]\, B => \un1_dcom0[11]\, Y => - \DWACT_BL_EQUAL_0_E[0]\); - - \v.brate_1_sqmuxa_1_i_o5\ : OR2B - port map(A => rstn, B => brate_1_sqmuxa, Y => N_697); - - scaler_I_97 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_9[0]\, B => - \DWACT_ADD_CI_0_g_array_11_1[0]\, C => - \DWACT_ADD_CI_0_g_array_0_10[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_4[0]\); - - \uartop.op_gt.v.brate2_0_I_35\ : NOR2A - port map(A => \un1_dcom0[14]\, B => \scaler[12]\, Y => - \ACT_LT4_E[0]\); - - \r.rhold[2]\ : DFN1E1 - port map(D => \rshift[2]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(2)); - - \r.thold[0]\ : DFN1E0 - port map(D => hwdata(24), CLK => lclk_c, E => write, Q => - \thold[0]\); - - \r.scaler[13]\ : DFN1E0 - port map(D => \scaler_1_0_iv[13]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[13]\); - - \r.rxdb_RNI3URED[1]\ : MX2C - port map(A => tcnt_1_sqmuxa, B => rxdb_1, S => N_61_0, Y - => \tcnt_1_sqmuxa[0]\); - - \r.brate_RNO_1[16]\ : AO1C - port map(A => brate_1_sqmuxa_4, B => \scaler[16]\, C => - \brate_1_iv_0[16]\, Y => \brate_1[16]\); - - \r.ovf\ : DFN1 - port map(D => ovf_RNO, CLK => lclk_c, Q => ovf); - - \r.brate_RNO_1[17]\ : AO1C - port map(A => brate_1_sqmuxa_4, B => \scaler[17]\, C => - \brate_1_iv_0[17]\, Y => \brate_1[17]\); - - \r.scaler_RNO_3[4]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[8]\, Y => - \scaler_i_m_1[8]\); - - \r.tshift_RNI1IJD[6]\ : NOR2B - port map(A => \tshift[6]\, B => \tshift[7]\, Y => - \tshift_1_0_a2_2[0]\); - - \r.rshift[6]\ : DFN1 - port map(D => \rshift_RNO[6]\, CLK => lclk_c, Q => - \rshift[6]\); - - \uartop.op_gt.v.brate2_0_I_70\ : AND2A - port map(A => \un1_dcom0[13]\, B => \scaler[11]\, Y => - \ACT_LT3_E[5]\); - - \r.tshift[6]\ : DFN1 - port map(D => \tshift_RNO[6]\, CLK => lclk_c, Q => - \tshift[6]\); - - \r.brate_RNO[7]\ : OR2A - port map(A => rstn, B => N_408, Y => \brate_RNO[7]\); - - \r.frame\ : DFN1 - port map(D => frame_RNO, CLK => lclk_c, Q => frame); - - \r.scaler_RNO_0[5]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[9]\, Y => N_741); - - \r.thold[6]\ : DFN1E0 - port map(D => hwdata(30), CLK => lclk_c, E => write, Q => - \thold[6]\); - - \r.scaler_RNO_1[6]\ : NOR2 - port map(A => \un1_dcom0[8]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[6]\); - - \r.tshift_RNO[8]\ : NOR3 - port map(A => N_110, B => N_109, C => N_108, Y => - \tshift_RNO[8]\); - - \r.scaler_RNO_2[17]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[17]\, Y => - \scaler_i_m[17]\); - - \r.rshift[1]\ : DFN1 - port map(D => \rshift_RNO[1]\, CLK => lclk_c, Q => - \rshift[1]\); - - \r.brate_RNO_0[1]\ : MX2 - port map(A => \brate_1_iv[1]\, B => \un1_dcom0[3]\, S => - brate_2_sqmuxa, Y => N_402); - - \r.tshift_RNO_1[0]\ : OR2A - port map(A => \tshift[1]\, B => N_77, Y => N_124); - - \r.txstate_RNI6M9D_0[1]\ : NOR3A - port map(A => txtick, B => \txstate[0]\, C => \txstate[1]\, - Y => thempty_1_sqmuxa_1_i_o2_0); - - \r.brate_RNO_3[0]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(0), Y => - \apbi_i_m[50]\); - - \r.rshift_RNI6J4R[0]\ : NOR3A - port map(A => break10_1, B => \rshift[1]\, C => \rshift[0]\, - Y => break10_4); - - \r.tshift[1]\ : DFN1 - port map(D => N_27, CLK => lclk_c, Q => \tshift[1]\); - - \uartop.op_gt.v.brate2_0_I_7\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_1[0]\, B => - \DWACT_BL_EQUAL_0_E_1[1]\, C => \DWACT_BL_EQUAL_0_E_0[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \r.rshift[2]\ : DFN1 - port map(D => \rshift_RNO[2]\, CLK => lclk_c, Q => - \rshift[2]\); - - scaler_I_15 : AND2 - port map(A => \scaler[15]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_15[0]\); - - \r.scaler_RNO_1[10]\ : NOR2 - port map(A => N_697, B => pwdata_0(10), Y => N_727); - - \r.scaler_RNO_2[9]\ : AO1D - port map(A => N_697, B => pwdata_0(9), C => N_728, Y => - \scaler_1_0_iv_0_0[9]\); - - \r.tshift[2]\ : DFN1 - port map(D => N_29, CLK => lclk_c, Q => \tshift[2]\); - - \r.brate_RNI65I6[7]\ : XNOR2 - port map(A => \un1_dcom0[9]\, B => \scaler[7]\, Y => - tcnt8_3_i); - - \r.rshift_RNO_0[0]\ : MX2 - port map(A => \rshift[0]\, B => \rshift[1]\, S => - rshift_0_sqmuxa, Y => N_439); - - \r.brate_RNI69BD3[4]\ : OR3C - port map(A => tcnt8_NE_9, B => tcnt8_NE_8, C => tcnt8_NE_10, - Y => tcnt9); - - \r.txtick_RNO_0\ : NOR2B - port map(A => \txclk[2]\, B => tick, Y => txtick_0_i_0); - - \r.rshift_RNO_0[6]\ : MX2 - port map(A => \rshift[6]\, B => \rshift[7]\, S => - rshift_0_sqmuxa, Y => N_445); - - \r.thempty_RNI6RFE\ : OR2A - port map(A => enable, B => \thempty\, Y => N_59); - - \r.rxf[2]\ : DFN1 - port map(D => \rxf_RNO[2]\, CLK => lclk_c, Q => \rxf[2]\); - - \uartop.op_gt.v.brate2_0_I_19\ : XNOR2 - port map(A => \scaler[17]\, B => \un1_dcom0[19]\, Y => - \DWACT_BL_EQUAL_0_E_0[1]\); - - scaler_I_111 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_11[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_12[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_5[0]\); - - scaler_I_102 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_5[0]\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, C => - \DWACT_ADD_CI_0_g_array_1_6[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_2[0]\); - - \uartop.op_gt.v.brate2_0_I_95\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - \r.brate_RNO_2[12]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[16]\, C => - N_707, Y => \brate_1_iv_0_0[12]\); - - \r.brate_RNIQ5GH[15]\ : XA1A - port map(A => \scaler[15]\, B => \un1_dcom0[17]\, C => - N_58_i_i, Y => tcnt8_NE_6); - - \r.scaler_RNO[9]\ : NOR3 - port map(A => N_729, B => N_730, C => - \scaler_1_0_iv_0_0[9]\, Y => \scaler_1_0_iv[9]\); - - \r.scaler[17]\ : DFN1E0 - port map(D => \scaler_1_0_iv[17]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[17]\); - - \uartop.op_gt.v.brate2_0_I_5\ : XNOR2 - port map(A => \scaler[12]\, B => \un1_dcom0[14]\, Y => - \DWACT_BL_EQUAL_0_E_1[0]\); - - \r.tsempty_RNIF68B\ : OR2B - port map(A => rdata60_1, B => N_329, Y => N_85); - - scaler_I_31 : XOR2 - port map(A => \scaler[5]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_4[0]\); - - scaler_I_104 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_2_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_3[0]\); - - \r.tshift_RNO_2[2]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[2]\, Y => - N_90); - - \r.rxf[0]\ : DFN1 - port map(D => dsurx_c, CLK => lclk_c, Q => \rxf[0]\); - - \r.brate_RNO[2]\ : OR2A - port map(A => rstn, B => N_403, Y => \brate_RNO[2]\); - - \r.brate_RNO[3]\ : OR2A - port map(A => rstn, B => N_404, Y => \brate_RNO[3]\); - - \r.txstate_RNO_1[0]\ : NOR3 - port map(A => N_114, B => \txstate[1]\, C => N_139, Y => - N_650); - - \r.brate_RNO_4[1]\ : NOR2 - port map(A => brate_1_sqmuxa_4, B => \scaler[1]\, Y => - \scaler_i_m_0[1]\); - - scaler_I_77 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_2[0]\, B => - \DWACT_ADD_CI_0_g_array_0_2[0]\, C => - \DWACT_ADD_CI_0_g_array_0_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_1[0]\); - - scaler_I_14 : AND2 - port map(A => \scaler[14]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_14[0]\); - - \r.tshift_RNO[2]\ : NOR3 - port map(A => N_92, B => N_91, C => N_90, Y => N_29); - - \r.rshift[4]\ : DFN1 - port map(D => \rshift_RNO[4]\, CLK => lclk_c, Q => - \rshift[4]\); - - \r.scaler[14]\ : DFN1E0 - port map(D => \scaler_1_0_iv[14]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[14]\); - - \r.tshift[4]\ : DFN1 - port map(D => \tshift_RNO[4]\, CLK => lclk_c, Q => - \tshift[4]\); - - \r.scaler_RNO_1[7]\ : NOR2 - port map(A => \un1_dcom0[9]\, B => scaler_0_sqmuxa_1, Y => - N_738); - - \r.rxstate_RNO_2[0]\ : OR2A - port map(A => \rxstate[0]\, B => rxtick, Y => N_639); - - scaler_I_62 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[1]\, B => - \scaler[0]\, Y => \scaler_0[1]\); - - \r.tshift[9]\ : DFN1 - port map(D => \tshift_10_0_iv[9]\, CLK => lclk_c, Q => - \tshift[9]\); - - \r.scaler_RNO_1[17]\ : AO1D - port map(A => \un1_dcom0[19]\, B => scaler_0_sqmuxa_1, C - => \scaler_i_m[17]\, Y => \scaler_1_0_iv_1[17]\); - - \r.scaler_RNO[11]\ : NOR3 - port map(A => N_721, B => N_722, C => - \scaler_1_0_iv_0_0[11]\, Y => \scaler_1_0_iv[11]\); - - \r.rxen_RNO_3\ : NOR2 - port map(A => rxen_1_sqmuxa, B => break_0_sqmuxa, Y => - rxen_1_sqmuxa_1); - - \r.brate_RNIC9FH[11]\ : XA1A - port map(A => \scaler[11]\, B => \un1_dcom0[13]\, C => - tcnt8_9_i, Y => tcnt8_NE_5); - - \v.brate_1_sqmuxa\ : NOR3B - port map(A => N_769, B => un1_apbi_1, C => un1_apbi_2, Y - => brate_1_sqmuxa); - - scaler_I_39 : XOR2 - port map(A => \scaler[11]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[11]\); - - \r.tshift_RNO_2[0]\ : AO1B - port map(A => txtick, B => N_126, C => \dsutx_c\, Y => - N_123); - - \r.tshift_RNO_1[4]\ : NOR2 - port map(A => \tshift[5]\, B => N_77, Y => N_97); - - \r.tshift_RNISN232[1]\ : NOR2 - port map(A => \tshift[1]\, B => N_138_i, Y => N_139); - - scaler_I_26 : XOR2 - port map(A => \scaler[1]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0[0]\); - - \r.rxstate_RNO_0[0]\ : OA1 - port map(A => N_640_2, B => \rxstate_ns_0_a3_0_0[0]\, C => - N_639, Y => \rxstate_ns_0_0[0]\); - - \r.dready_RNO\ : OA1A - port map(A => dready_2, B => dready_0_sqmuxa_0, C => rstn, - Y => dready_RNO); - - \r.txstate_RNO_2[0]\ : NOR2A - port map(A => N_59, B => \txstate[0]\, Y => N_114); - - scaler_I_47 : XOR2 - port map(A => \scaler[7]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[7]\); - - \r.scaler_RNO_2[12]\ : AO1D - port map(A => N_697, B => pwdata_0(12), C => N_716, Y => - \scaler_1_0_iv_0_0[12]\); - - \r.scaler[1]\ : DFN1E0 - port map(D => \scaler_1_0_iv[1]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[1]\); - - scaler_I_56 : XOR2 - port map(A => \scaler[6]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[6]\); - - \r.rxtick_RNI7JL1\ : OR2A - port map(A => rxtick, B => \rxdb[0]\, Y => rsempty_1_sqmuxa); - - \r.brate_RNO_3[7]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(7), Y => - \apbi_i_m[57]\); - - \uartop.op_gt.v.brate2_0_I_78\ : OR2A - port map(A => \un1_dcom0[7]\, B => \scaler[5]\, Y => N_12); - - \r.scaler_RNO[17]\ : NOR3A - port map(A => scaler_2_sqmuxa, B => \apbi_i_m[67]\, C => - \scaler_1_0_iv_1[17]\, Y => \scaler_1_0_iv[17]\); - - \r.rshift_RNO_0[3]\ : MX2 - port map(A => \rshift[3]\, B => \rshift[4]\, S => - rshift_0_sqmuxa, Y => N_442); - - \r.rxclk[0]\ : DFN1E0 - port map(D => \rxclk_1[0]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[0]\); - - \r.brate_RNO_1[12]\ : OA1B - port map(A => \scaler[12]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0_0[12]\, Y => \brate_1_iv[12]\); - - \r.brate_RNO_0[3]\ : MX2 - port map(A => \brate_1_iv[3]\, B => \un1_dcom0[5]\, S => - brate_2_sqmuxa, Y => N_404); - - scaler_I_96 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, C => - \DWACT_ADD_CI_0_g_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - \r.brate_RNIPEV9[3]\ : MX2 - port map(A => break, B => \un1_dcom0[5]\, S => N_6455, Y - => N_331); - - \r.txstate_RNO[1]\ : NOR2B - port map(A => rstn, B => N_561, Y => N_561s); - - un3_txclk_1_CO1 : NOR2B - port map(A => \txclk[1]\, B => N_680_i_1, Y => CO1); - - \r.tshift_RNO_1[8]\ : NOR2 - port map(A => \tshift[9]\, B => N_77, Y => N_109); - - \uartop.v.rxclk_1_i_a2[2]\ : NOR2A - port map(A => rxstate_0_sqmuxa, B => N_677, Y => N_136); - - \r.rsempty\ : DFN1 - port map(D => rsempty_RNO, CLK => lclk_c, Q => rsempty); - - \uartop.op_gt.v.brate2_0_I_1\ : XNOR2 - port map(A => \scaler[14]\, B => \un1_dcom0[16]\, Y => - \DWACT_BL_EQUAL_0_E_0[2]\); - - \r.tshift_RNO_0[2]\ : NOR2 - port map(A => \thold[1]\, B => N_64, Y => N_92); - - \r.rxtick_0_0_a5\ : AND2 - port map(A => N_136, B => rxtick_0_0_a5_0, Y => - rxtick_0_0_a5); - - \r.scaler_RNO_0[15]\ : NOR2 - port map(A => N_697, B => pwdata_0(15), Y => N_715); - - \r.scaler_RNO_3[3]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[7]\, Y => - \scaler_i_m_1[7]\); - - \r.scaler_RNO_2[8]\ : AO1D - port map(A => N_697, B => pwdata_0(8), C => N_732, Y => - \scaler_1_0_iv_0_0[8]\); - - scaler_I_87 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_13[0]\, B => - \DWACT_ADD_CI_0_g_array_11_2[0]\, C => - \DWACT_ADD_CI_0_g_array_0_14[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_6[0]\); - - \r.scaler_RNO_0[16]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[16]\, Y => - N_710); - - \uartop.op_gt.v.brate2_0_I_69\ : OR2A - port map(A => \un1_dcom0[13]\, B => \scaler[11]\, Y => - \ACT_LT3_E[4]\); - - \v.brate_0_sqmuxa\ : NOR2A - port map(A => rstn, B => brate_1_sqmuxa, Y => - brate_0_sqmuxa); - - \r.brate[1]\ : DFN1 - port map(D => \brate_RNO[1]\, CLK => lclk_c, Q => - \un1_dcom0[3]\); - - \uartop.op_gt.v.brate2_0_I_58\ : XNOR2 - port map(A => \scaler[10]\, B => \un1_dcom0[12]\, Y => - \DWACT_BL_EQUAL_0_E[1]\); - - \r.tshift_RNO[7]\ : NOR3 - port map(A => N_107, B => N_106, C => N_105, Y => - \tshift_RNO[7]\); - - \uartop.op_gt.v.brate2_0_I_42\ : NOR2A - port map(A => \scaler[14]\, B => \un1_dcom0[16]\, Y => - \ACT_LT4_E[7]\); - - scaler_I_101 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_1[0]\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, C => - \DWACT_ADD_CI_0_g_array_0_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_12[0]\); - - \r.tcnt_RNO_0[1]\ : XA1A - port map(A => \tcnt[1]\, B => CO0, C => tcnt_1_sqmuxa_3, Y - => \tcnt_0_sqmuxa_1_m[0]\); - - \r.rshift_RNO[1]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_440, Y => - \rshift_RNO[1]\); - - \r.brate_RNIU4O8[16]\ : XNOR2 - port map(A => \un1_dcom0[18]\, B => \scaler[16]\, Y => - N_58_i_i); - - \uartop.op_gt.v.brate2_0_I_67\ : AND2A - port map(A => \un1_dcom0[12]\, B => \scaler[10]\, Y => - \ACT_LT3_E[2]\); - - \r.brate_RNO_1[8]\ : OA1B - port map(A => \scaler[8]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0_0[8]\, Y => \brate_1_iv[8]\); - - \r.tcnt_RNI73NE_2[1]\ : NOR2B - port map(A => \tcnt[1]\, B => \tcnt[0]\, Y => N_61); - - \r.tshift_RNO_1[2]\ : NOR2 - port map(A => \tshift[3]\, B => N_77, Y => N_91); - - scaler_I_30 : XOR2 - port map(A => \scaler[12]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_11[0]\); - - \r.rshift_RNO[0]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_439, Y => - \rshift_RNO[0]\); - - \r.scaler_RNO_2[5]\ : AO1D - port map(A => \un1_dcom0[7]\, B => scaler_0_sqmuxa_1, C => - N_740, Y => \scaler_1_0_iv_0_1[5]\); - - \r.rxstate_RNI7QOB_0[0]\ : OR2A - port map(A => \rxstate[0]\, B => \rxstate[1]\, Y => - rshift_0_sqmuxa_0_a2_0_0); - - \r.brate_RNO[16]\ : OR2A - port map(A => rstn, B => N_417, Y => \brate_RNO[16]\); - - \r.brate[14]\ : DFN1 - port map(D => \brate_RNO[14]\, CLK => lclk_c, Q => - \un1_dcom0[16]\); - - \r.txstate[1]\ : DFN1 - port map(D => N_561s, CLK => lclk_c, Q => \txstate[1]\); - - \r.dready_RNID4BH\ : OR2B - port map(A => dready_2_0, B => N_321, Y => dready_2); - - \r.scaler_RNO_1[12]\ : NOR2 - port map(A => \un1_dcom0[14]\, B => scaler_0_sqmuxa_1, Y - => N_718); - - \r.frame_RNO\ : NOR2B - port map(A => rstn, B => N_427, Y => frame_RNO); - - \r.fedge_RNIO4K501\ : NOR3 - port map(A => tcnt_0_sqmuxa, B => N_61_0, C => - fedge_0_sqmuxa, Y => tcnt_0_sqmuxa_2); - - \r.tshift_RNO_2[7]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[7]\, Y => - N_105); - - \r.scaler_RNO[7]\ : NOR3 - port map(A => N_736, B => N_738, C => - \scaler_1_0_iv_0_0[7]\, Y => \scaler_1_0_iv[7]\); - - \r.rshift_RNIMJ6R[4]\ : NOR3A - port map(A => break10_3, B => \rshift[5]\, C => \rshift[4]\, - Y => break10_5); - - \r.scaler_RNO[2]\ : OR3C - port map(A => N_742, B => N_743, C => - \scaler_1_0_iv_0_0[2]\, Y => \scaler_1[2]\); - - \uartop.op_gt.v.brate2_0_I_26\ : AO1C - port map(A => \scaler[16]\, B => \un1_dcom0[18]\, C => - \scaler[17]\, Y => \ACT_LT2_E[1]\); - - \r.brate_RNO_3[8]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[12]\, Y => - N_706); - - \r.scaler_RNO_2[14]\ : NOR3B - port map(A => scaler_0_sqmuxa, B => rstn, C => - brate_i_m_14_m1_e_0, Y => \brate_i_m[14]\); - - \r.rxdb_RNIDBKCG1[1]\ : NOR3 - port map(A => \tcnt_1_sqmuxa[0]\, B => rxen_1_sqmuxa, C => - tcnt_0_sqmuxa_2, Y => tcnt_1_sqmuxa_3); - - scaler_I_65 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[6]\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => \scaler_0[6]\); - - \r.scaler_RNO_0[2]\ : OR2A - port map(A => \scaler[6]\, B => scaler_2_sqmuxa, Y => N_742); - - \r.fedge_RNO_1\ : AO1 - port map(A => fedge_0_sqmuxa, B => N_630, C => N_61_0, Y - => fedge_1_sqmuxa); - - \r.scaler[4]\ : DFN1E0 - port map(D => \scaler_1_0_iv[4]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[4]\); - - \r.tshift_RNO[4]\ : NOR3 - port map(A => N_98, B => N_97, C => N_96, Y => - \tshift_RNO[4]\); - - \r.rxstate_RNIEDED[0]\ : OR2 - port map(A => rshift_0_sqmuxa_0_a2_0_0, B => - rsempty_1_sqmuxa, Y => N_628); - - \r.tick\ : DFN1 - port map(D => scaler_0_sqmuxa, CLK => lclk_c, Q => tick); - - scaler_I_76 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_8[0]\, B => - \DWACT_ADD_CI_0_g_array_0_8[0]\, C => - \DWACT_ADD_CI_0_g_array_0_9[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_4[0]\); - - \uartop.op_gt.v.brate2_0_I_60\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E[2]\, B => - \DWACT_BL_EQUAL_0_E[1]\, C => \DWACT_BL_EQUAL_0_E[0]\, Y - => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - \r.rshift_RNIS6BM1[0]\ : OR2B - port map(A => break10_5, B => break10_4, Y => break10_i_0); - - \r.brate[12]\ : DFN1 - port map(D => \brate_RNO[12]\, CLK => lclk_c, Q => - \un1_dcom0[14]\); - - \r.brate_RNI0TL6[7]\ : MX2 - port map(A => \rxdb[0]\, B => \un1_dcom0[9]\, S => N_6455_0, - Y => N_334); - - \r.break_RNO_0\ : MX2 - port map(A => break, B => break_1, S => N_7, Y => N_419); - - \r.brate_RNI8IAF[8]\ : XA1A - port map(A => \scaler[8]\, B => \un1_dcom0[10]\, C => - N_59_i_i, Y => tcnt8_NE_1); - - scaler_I_33 : XOR2 - port map(A => \scaler[11]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_10[0]\); - - \r.tshift_RNO_0[5]\ : NOR2 - port map(A => \thold[4]\, B => N_64, Y => N_101); - - \r.brate[3]\ : DFN1 - port map(D => \brate_RNO[3]\, CLK => lclk_c, Q => - \un1_dcom0[5]\); - - \r.rxdb_RNIRRFH[0]\ : OR2B - port map(A => dready_2, B => \rxdb[0]\, Y => - rsempty_0_sqmuxa_1_1); - - \r.scaler_RNO_2[2]\ : OA1A - port map(A => pwdata_0(2), B => N_697, C => N_744, Y => - \scaler_1_0_iv_0_0[2]\); - - \r.rxen_RNO_1\ : NOR2A - port map(A => rxen_0_sqmuxa_1, B => rxen_1_sqmuxa, Y => - rxen_0_sqmuxa_2); - - \uartop.op_gt.v.brate2_0_I_18\ : XNOR2 - port map(A => \scaler[16]\, B => \un1_dcom0[18]\, Y => - \DWACT_BL_EQUAL_0_E_0[0]\); - - \uartop.op_gt.v.brate2_0_I_82\ : AO1C - port map(A => \un1_dcom0[7]\, B => \scaler[5]\, C => N_14, - Y => N_16); - - \r.tshift_RNI1L9S1[4]\ : OR2B - port map(A => \tshift_1_0_a2_6[0]\, B => - \tshift_1_0_a2_5[0]\, Y => N_138_i); - - \r.scaler[16]\ : DFN1E0 - port map(D => \scaler_1_0_iv[16]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[16]\); - - \r.rxen_RNO_2\ : NOR2B - port map(A => rxen_1_sqmuxa, B => pwdata_0(0), Y => rxen_1); - - \uartop.op_gt.v.brate2_0_I_6\ : XNOR2 - port map(A => \scaler[13]\, B => \un1_dcom0[15]\, Y => - \DWACT_BL_EQUAL_0_E_1[1]\); - - \uartop.op_gt.v.brate2_0_I_25\ : AND2A - port map(A => \un1_dcom0[19]\, B => \scaler[17]\, Y => - \ACT_LT2_E[0]\); - - \r.thold[5]\ : DFN1E0 - port map(D => hwdata(29), CLK => lclk_c, E => write, Q => - \thold[5]\); - - \r.tsempty\ : DFN1 - port map(D => tsempty_RNO, CLK => lclk_c, Q => tsempty); - - scaler_I_46 : XOR2 - port map(A => \scaler[1]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[1]\); - - \r.rsempty_RNO_3\ : AO1B - port map(A => rsempty_1_sqmuxa, B => rsempty_0_sqmuxa_1_1, - C => \rxstate[1]\, Y => rsempty_0_sqmuxa_2); - - scaler_I_21 : AND2 - port map(A => \scaler[5]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_5[0]\); - - \r.rxdb[0]\ : DFN1 - port map(D => N_8, CLK => lclk_c, Q => \rxdb[0]\); - - scaler_I_17 : AND2 - port map(A => \scaler[7]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_7[0]\); - - \r.scaler_RNO_3[11]\ : NOR2 - port map(A => N_697, B => pwdata_0(11), Y => N_723); - - \r.scaler_RNO_2[1]\ : AO1D - port map(A => scaler_2_sqmuxa, B => \scaler[5]\, C => - \apbi_i_m_0[51]\, Y => \scaler_1_0_iv_0[1]\); - - scaler_I_51 : XOR2 - port map(A => \scaler[15]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[15]\); - - \uartop.op_gt.v.brate2_0_I_45\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO0_DWACT_COMP0_E[2]\); - - scaler_I_64 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[14]\, B => - \DWACT_ADD_CI_0_g_array_11_2[0]\, Y => \scaler_0[14]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.scaler_RNO_1[5]\ : NOR2 - port map(A => N_697, B => pwdata_0(5), Y => N_122); - - \r.rxclk_RNO[2]\ : OA1A - port map(A => rxstate_0_sqmuxa, B => N_677, C => rstn, Y - => N_23); - - \r.brate_RNO_1[5]\ : OA1B - port map(A => \scaler[5]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[5]\, Y => \brate_1_iv[5]\); - - scaler_I_28 : XOR2 - port map(A => \scaler[14]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_13[0]\); - - \r.scaler_RNO_2[0]\ : AO1D - port map(A => N_697, B => pwdata_0(0), C => - \scaler_i_m_1[4]\, Y => \scaler_1_0_iv_0[0]\); - - scaler_I_58 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[13]\, B => - \DWACT_ADD_CI_0_g_array_12_5[0]\, Y => \scaler_0[13]\); - - \r.brate_RNO[11]\ : OR2A - port map(A => rstn, B => N_412, Y => \brate_RNO[11]\); - - scaler_I_91 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_2_2[0]\, B => - \DWACT_ADD_CI_0_g_array_2_2[0]\, C => - \DWACT_ADD_CI_0_g_array_2_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_3_1[0]\); - - \r.rshift_RNO_0[2]\ : MX2 - port map(A => \rshift[2]\, B => \rshift[3]\, S => - rshift_0_sqmuxa, Y => N_441); - - \r.brate_RNO[9]\ : OR2A - port map(A => rstn, B => N_410, Y => \brate_RNO[9]\); - - \r.rxstate[0]\ : DFN1 - port map(D => \rxstate_nss[0]\, CLK => lclk_c, Q => - \rxstate[0]\); - - \r.brate_RNO_1[6]\ : NOR3 - port map(A => \scaler_i_m[10]\, B => \apbi_i_m[56]\, C => - \scaler_i_m_0[6]\, Y => \brate_1_iv[6]\); - - \r.rxtick\ : DFN1 - port map(D => rxtick_0_0_a5, CLK => lclk_c, Q => rxtick); - - \apbo.prdata_5_0_a2\ : XNOR2 - port map(A => paddr(2), B => paddr(3), Y => \N_127\); - - \r.scaler_RNO_1[14]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[14]\, Y => - \scaler_i_m[14]\); - - scaler_I_29 : XOR2 - port map(A => \scaler[3]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_2[0]\); - - scaler_I_59 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[12]\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, Y => \scaler_0[12]\); - - \r.brate_RNO_2[4]\ : AO1A - port map(A => pwdata_0(4), B => brate_1_sqmuxa, C => N_78, - Y => \brate_1_iv_0_0[4]\); - - scaler_I_98 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_2[0]\, B => - \DWACT_ADD_CI_0_g_array_1_2[0]\, C => - \DWACT_ADD_CI_0_g_array_1_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_2_1[0]\); - - \r.tcnt_RNIHFKV3_0[1]\ : NOR2A - port map(A => tcnt_0_sqmuxa, B => N_61_0, Y => - tcnt_0_sqmuxa_1); - - \v.rxen_1_sqmuxa\ : NOR3B - port map(A => N_769, B => un1_apbi_1, C => rdata60_1, Y => - rxen_1_sqmuxa); - - \r.brate_RNO_4[6]\ : NOR2 - port map(A => brate_1_sqmuxa_4, B => \scaler[6]\, Y => - \scaler_i_m_0[6]\); - - \r.rxen_RNION4IM\ : NOR2B - port map(A => enable, B => tick_2, Y => scaler_0_sqmuxa); - - \uartop.op_gt.v.brate2_0_I_86\ : AO1C - port map(A => \scaler[7]\, B => \un1_dcom0[9]\, C => N_15_0, - Y => N_20); - - \r.brate_RNO_0[11]\ : MX2 - port map(A => \brate_1_iv[11]\, B => \un1_dcom0[13]\, S => - brate_2_sqmuxa, Y => N_412); - - \r.brate_RNO_3[11]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(11), Y => - \apbi_i_m[61]\); - - \r.brate_RNO_3[6]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(6), Y => - \apbi_i_m[56]\); - - \r.tshift_RNO_0[8]\ : NOR2 - port map(A => \thold[7]\, B => N_64, Y => N_110); - - \r.scaler[3]\ : DFN1E0 - port map(D => \scaler_1_0_iv[3]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[3]\); - - scaler_I_99 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, C => - \DWACT_ADD_CI_0_g_array_1_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - scaler_I_108 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - \r.brate_RNO_2[10]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[14]\, C => - N_82, Y => \brate_1_iv_0_0[10]\); - - \r.brate[13]\ : DFN1 - port map(D => \brate_RNO[13]\, CLK => lclk_c, Q => - \un1_dcom0[15]\); - - \uartop.op_gt.v.brate2_0_I_39\ : OR2A - port map(A => \un1_dcom0[16]\, B => \scaler[14]\, Y => - \ACT_LT4_E[4]\); - - \r.brate[7]\ : DFN1 - port map(D => \brate_RNO[7]\, CLK => lclk_c, Q => - \un1_dcom0[9]\); - - \r.brate_RNO[6]\ : OR2A - port map(A => rstn, B => N_407, Y => \brate_RNO[6]\); - - \uartop.op_gt.v.brate2_0_I_68\ : AOI1A - port map(A => \ACT_LT3_E[0]\, B => \ACT_LT3_E[1]\, C => - \ACT_LT3_E[2]\, Y => \ACT_LT3_E[3]\); - - \r.rxen_RNIJGPI\ : OR2A - port map(A => rxdb_4, B => N_622, Y => rxstate_0_sqmuxa); - - \uartop.op_gt.v.brate2_0_I_85\ : OR2A - port map(A => \scaler[8]\, B => \un1_dcom0[10]\, Y => - N_19_0); - - \r.rxen_RNI3357J1\ : MX2 - port map(A => scaler_2_sqmuxa_1, B => tick_2, S => enable, - Y => \scaler_2_sqmuxa[0]\); - - \r.rshift_RNILHID[2]\ : NOR2 - port map(A => \rshift[2]\, B => \rshift[3]\, Y => break10_1); - - \uartop.op_gt.v.brate2_0_I_37\ : AND2A - port map(A => \un1_dcom0[15]\, B => \scaler[13]\, Y => - \ACT_LT4_E[2]\); - - \r.scaler[5]\ : DFN1E0 - port map(D => \scaler_1_0_iv[5]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[5]\); - - \r.brate_RNO_2[14]\ : AOI1B - port map(A => brate_1_sqmuxa, B => pwdata_0(14), C => - brate_3_sqmuxa_i, Y => \brate_1_iv_0[14]\); - - \r.rhold[7]\ : DFN1E1 - port map(D => \rshift[7]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(7)); - - \r.tick_RNI5JQ31\ : OR2 - port map(A => tick, B => N_21_1, Y => N_15); - - \r.brate[5]\ : DFN1 - port map(D => \brate_RNO[5]\, CLK => lclk_c, Q => - \un1_dcom0[7]\); - - \r.scaler_RNO_2[15]\ : OR3A - port map(A => scaler_0_sqmuxa, B => brate_1_sqmuxa, C => - \un1_dcom0[17]\, Y => \scaler_RNO_2[15]\); - - \r.rxclk[1]\ : DFN1E0 - port map(D => \rxclk_1[1]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[1]\); - - scaler_I_20 : AND2 - port map(A => \scaler[11]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_11[0]\); - - \r.tshift_RNO_2[8]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[8]\, Y => - N_108); - - \r.rsempty_RNO_4\ : OR2 - port map(A => rxdb_4, B => \rxstate[1]\, Y => rsempty_RNO_4); - - \uartop.op_gt.v.brate2_0_I_41\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - scaler_I_71 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[16]\, B => - \DWACT_ADD_CI_0_g_array_4[0]\, Y => \scaler_0[16]\); - - \r.break\ : DFN1 - port map(D => break_RNO, CLK => lclk_c, Q => break); - - scaler_I_50 : XOR2 - port map(A => \scaler[3]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[3]\); - - \r.scaler_RNO_2[16]\ : OAI1 - port map(A => pwdata(16), B => N_697, C => scaler_2_sqmuxa, - Y => \scaler_1_0_iv_0_0[16]\); - - \r.rshift_RNO_0[5]\ : MX2 - port map(A => \rshift[5]\, B => \rshift[6]\, S => - rshift_0_sqmuxa, Y => N_444); - - \r.tcnt_RNIGD3J[1]\ : OR3 - port map(A => \tcnt[0]\, B => \tcnt[1]\, C => rdata60_1, Y - => N_86); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.brate_RNIICN8[10]\ : XNOR2 - port map(A => \un1_dcom0[12]\, B => \scaler[10]\, Y => - tcnt8_6_i); - - \r.brate_RNO_3[2]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(2), Y => N_73); - - \r.txstate_RNIHL8Q[1]\ : OR3A - port map(A => N_59, B => \txstate[0]\, C => \txstate[1]\, Y - => N_126); - - \r.thold[1]\ : DFN1E0 - port map(D => hwdata(25), CLK => lclk_c, E => write, Q => - \thold[1]\); - - \r.rxtick_RNI0M9D_0\ : OR2A - port map(A => rxtick, B => N_640_2, Y => N_627); - - \r.tcnt_RNI0K947[1]\ : OR2A - port map(A => brate_0_sqmuxa, B => brate_1_sqmuxa_2, Y => - brate_1_sqmuxa_4); - - \r.scaler_RNO[16]\ : NOR3 - port map(A => N_710, B => N_711, C => - \scaler_1_0_iv_0_0[16]\, Y => \scaler_1_0_iv[16]\); - - \r.brate_RNO_0[16]\ : MX2 - port map(A => \brate_1[16]\, B => \un1_dcom0[18]\, S => - brate_2_sqmuxa, Y => N_417); - - \r.brate_RNO_0[17]\ : MX2 - port map(A => \brate_1[17]\, B => \un1_dcom0[19]\, S => - brate_2_sqmuxa, Y => N_418); - - \r.rxdb_RNI5BSL[1]\ : MX2C - port map(A => rxdb_3, B => rxdb_1, S => N_61_0, Y => - \brate13[0]\); - - scaler_I_78 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_2_1[0]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, C => - \DWACT_ADD_CI_0_g_array_2_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_10[0]\); - - scaler_I_109 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_9[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_10[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_4[0]\); - - \r.brate[16]\ : DFN1 - port map(D => \brate_RNO[16]\, CLK => lclk_c, Q => - \un1_dcom0[18]\); - - scaler_I_90 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_3[0]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, C => - \DWACT_ADD_CI_0_g_array_0_4[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_1[0]\); - - \r.tshift_RNO_0[1]\ : NOR2 - port map(A => \thold[0]\, B => N_64, Y => N_89); - - \r.brate_RNO_1[10]\ : OA1B - port map(A => \scaler[10]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0_0[10]\, Y => \brate_1_iv[10]\); - - \r.brate_RNO_2[13]\ : AO1A - port map(A => pwdata_0(13), B => brate_1_sqmuxa, C => - \scaler_i_m_1[17]\, Y => \brate_1_iv_0[13]\); - - scaler_I_41 : XOR2 - port map(A => \scaler[4]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[4]\); - - scaler_I_16 : AND2 - port map(A => \scaler[13]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_13[0]\); - - \r.tshift_RNO[1]\ : NOR3 - port map(A => N_89, B => N_88, C => N_87, Y => N_27); - - \r.brate_RNO_3[5]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(5), Y => - \apbi_i_m[55]\); - - \r.tcnt_RNITJ4P6[1]\ : OR3B - port map(A => rxen_0_sqmuxa_1, B => rstn, C => - brate_1_sqmuxa, Y => brate_0_sqmuxa_1_i); - - scaler_I_79 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_6[0]\, B => - \DWACT_ADD_CI_0_g_array_1_6[0]\, C => - \DWACT_ADD_CI_0_g_array_1_7[0]\, Y => - \DWACT_ADD_CI_0_g_array_2_3[0]\); - - \r.brate_RNO[14]\ : OR2A - port map(A => rstn, B => N_415, Y => \brate_RNO[14]\); - - \r.scaler_RNO_2[3]\ : AO1D - port map(A => N_697, B => pwdata_0(3), C => - \scaler_i_m_1[7]\, Y => \scaler_1_0_iv_0[3]\); - - \r.frame_RNO_0\ : MX2 - port map(A => frame, B => frame_1, S => N_9, Y => N_427); - - \r.rshift_RNO[3]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_442, Y => - \rshift_RNO[3]\); - - \r.brate_RNO_2[15]\ : AOI1B - port map(A => brate_1_sqmuxa, B => pwdata_0(15), C => - brate_3_sqmuxa_i, Y => \brate_1_iv_0[15]\); - - \r.scaler[8]\ : DFN1E0 - port map(D => \scaler_1_0_iv[8]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[8]\); - - \r.tshift_RNO[0]\ : OR3C - port map(A => \tshift_1_0_0[0]\, B => N_124, C => rstn, Y - => \tshift_1[0]\); - - \r.rxdb_RNI43I3[1]\ : OR3B - port map(A => fedge, B => \rxdb[1]\, C => \rxdb[0]\, Y => - rxdb_3); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.brate_RNO_3[9]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[13]\, Y => - \scaler_i_m[13]\); - - scaler_I_48 : XOR2 - port map(A => \scaler[16]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[16]\); - - scaler_I_32 : XOR2 - port map(A => \scaler_0[2]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_1[0]\); - - \r.scaler_RNO_0[6]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[6]\, Y => - \scaler_i_m[6]\); - - \r.scaler_RNO[3]\ : NOR3 - port map(A => \scaler_i_m[3]\, B => \brate_i_m[3]\, C => - \scaler_1_0_iv_0[3]\, Y => \scaler_1_0_iv[3]\); - - \uartop.op_gt.v.brate2_0_I_3\ : XNOR2 - port map(A => \scaler[16]\, B => \un1_dcom0[18]\, Y => - \DWACT_BL_EQUAL_0_E[4]\); - - scaler_I_23 : XOR2 - port map(A => \scaler[4]\, B => N_61, Y => - \DWACT_ADD_CI_0_pog_array_0_3[0]\); - - \r.brate_RNO_1[14]\ : AO1C - port map(A => brate_1_sqmuxa_4, B => \scaler[14]\, C => - \brate_1_iv_0[14]\, Y => \brate_1[14]\); - - scaler_I_53 : XOR2 - port map(A => \scaler_0[2]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[2]\); - - \r.tcnt_RNO_0[0]\ : XA1 - port map(A => \tcnt[0]\, B => tcnt_0_sqmuxa_1, C => - tcnt_1_sqmuxa_3, Y => \tcnt_0_sqmuxa_1_m[1]\); - - \r.rshift[7]\ : DFN1 - port map(D => \rshift_RNO[7]\, CLK => lclk_c, Q => - \rshift[7]\); - - \r.txstate_RNI6M9D[1]\ : OAI1 - port map(A => \txstate[0]\, B => \txstate[1]\, C => txtick, - Y => N_77); - - \r.tshift_RNO_2[1]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[1]\, Y => - N_87); - - \r.tshift_RNO_1[3]\ : NOR2 - port map(A => \tshift[4]\, B => N_77, Y => N_94); - - \uartop.op_gt.v.brate2_0_I_100\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => brate2); - - \r.scaler_RNO[6]\ : NOR3 - port map(A => \scaler_i_m[6]\, B => \brate_i_m[6]\, C => - \scaler_1_0_iv_0[6]\, Y => \scaler_1_0_iv[6]\); - - \r.ovf_RNICG8B\ : MX2 - port map(A => ovf, B => \un1_dcom0[6]\, S => N_6455_0, Y - => N_332); - - \r.tshift[7]\ : DFN1 - port map(D => \tshift_RNO[7]\, CLK => lclk_c, Q => - \tshift[7]\); - - \r.tsempty_RNO_1\ : NOR3A - port map(A => txtick, B => \txstate[0]\, C => \txstate[1]\, - Y => N_79); - - scaler_I_81 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_4[0]\, B => - \DWACT_ADD_CI_0_g_array_0_4[0]\, C => - \DWACT_ADD_CI_0_g_array_0_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_2[0]\); - - scaler_I_49 : XOR2 - port map(A => \scaler[8]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[8]\); - - \r.brate_RNO_1[7]\ : OA1B - port map(A => \scaler[7]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[7]\, Y => \brate_1_iv[7]\); - - scaler_I_67 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[7]\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => \scaler_0[7]\); - - \r.tcnt_RNIHFKV3[1]\ : NOR3 - port map(A => tcnt9, B => rxen_0_sqmuxa_0, C => rxdb_3, Y - => rxen_0_sqmuxa_1); - - \r.brate_RNO_0[0]\ : MX2 - port map(A => \brate_1_iv[0]\, B => \un1_dcom0[2]\, S => - brate_2_sqmuxa, Y => N_401); - - \r.tcnt_RNO[0]\ : OA1 - port map(A => \apbi_m[51]_net_1\, B => - \tcnt_0_sqmuxa_1_m[1]\, C => rstn, Y => \tcnt_RNO[0]\); - - \uartop.op_gt.v.brate2_0_I_81\ : OR2A - port map(A => \un1_dcom0[10]\, B => \scaler[8]\, Y => - N_15_0); - - scaler_I_93 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_5[0]\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, C => - \DWACT_ADD_CI_0_g_array_0_6[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_2[0]\); - - \r.scaler_RNO_1[15]\ : AOI1B - port map(A => \scaler_RNO_2[15]\, B => \scaler_RNO_3[15]\, - C => rstn, Y => \scaler_RNO_1[15]\); - - \r.scaler_RNO_0[11]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[11]\, Y => - N_721); - - \r.tsempty_RNO_0\ : MX2 - port map(A => tsempty, B => N_59, S => N_79, Y => N_447); - - \r.scaler_RNO_0[4]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[4]\, Y => - \scaler_i_m[4]\); - - \r.scaler_RNO_1[16]\ : NOR2 - port map(A => \un1_dcom0[18]\, B => scaler_0_sqmuxa_1, Y - => N_711); - - scaler_I_107 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2[0]\); - - scaler_I_88 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_14[0]\, B => - \DWACT_ADD_CI_0_g_array_0_14[0]\, C => - \DWACT_ADD_CI_0_g_array_0_15[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_7[0]\); - - \r.scaler[15]\ : DFN1E0 - port map(D => \scaler_1_0_iv[15]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[15]\); - - \r.brate_RNO_2[2]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[6]\, Y => - N_75); - - \r.tshift_RNI31311[8]\ : NOR3C - port map(A => \tshift[9]\, B => \tshift[8]\, C => - \tshift_1_0_a2_4[0]\, Y => \tshift_1_0_a2_6[0]\); - - \r.brate_RNO_1[13]\ : OA1B - port map(A => \scaler[13]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[13]\, Y => \brate_1_iv[13]\); - - \r.scaler_RNISMOP[0]\ : MX2 - port map(A => \scaler[0]\, B => tick, S => N_61_0, Y => - N_62); - - scaler_I_5 : AND2 - port map(A => \scaler[12]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_12[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity dcom is - - port( tcnt : in std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93); - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_24 : in std_logic; - hrdata_26 : in std_logic; - hrdata_25 : in std_logic; - hrdata_23 : in std_logic; - hwdata : out std_logic_vector(31 downto 0); - hrdata_0_1 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_0 : in std_logic; - data : in std_logic_vector(7 downto 0); - iosn_0 : in std_logic_vector(93 to 93); - state_i : out std_logic_vector(5 to 5); - haddr : out std_logic_vector(31 downto 0); - rstn : in std_logic; - hbusreq_i_3 : out std_logic; - N_78_0 : in std_logic; - N_262_0 : in std_logic; - thempty : in std_logic; - N_321 : out std_logic; - N_264_0 : in std_logic; - active : in std_logic; - hwrite : out std_logic; - dready : in std_logic; - write : out std_logic; - lclk_c : in std_logic - ); - -end dcom; - -architecture DEF_ARCH of dcom is - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[4]\, \state_i_RNIIHN51[5]\, \state_0[3]\, - \state_0_RNIIOIE4[3]\, data_0_sqmuxa_0, N_438, N_721, - state_4_0, state_4_0_0_0_0, N_680_0, N_308, N_682_0, N_15, - \len[1]\, \len[0]\, N_7, \len[3]\, \DWACT_FDEC_E[0]\, - N_147, N_139, \DWACT_FINC_E[0]\, N_116, \DWACT_FINC_E[4]\, - N_101, \DWACT_FINC_E[7]\, \DWACT_FINC_E[6]\, - \state_srsts_0_0_0_a2_5_0[1]\, N_318, - \state_srsts_0_i_i_0_o2_0[3]\, \state[2]\, - \clen_1_i_0_0[1]\, \clen_1_i_0_a2_0_0[1]\, - \clen_1_i_0_0[0]\, \clen_1_i_0_a2_0_0[0]\, \state_i[5]\, - \state[0]\, N_411_i_1, \clen[1]\, N_634, N_574, N_580, - N_577, N_194, N_425, N_427, N_426, N_30, N_397, N_398, - N_396, \state_i_RNO[5]\, N_405, N_406, \un1_rst_0_o4\, - N_637, N_604, N_610, N_607, N_635, N_583, N_592, N_589, - N_633, N_562, N_571, N_568, N_632, N_550, N_558, N_554, - N_631, N_535, N_546, N_537, N_629, N_487, N_490, N_489, - N_625, N_448, N_456, N_449, N_624, N_445, N_447, N_446, - N_621, N_434, N_436, N_435, N_212, N_431, N_433, N_432, - N_204, N_428, N_430, N_429, N_172, N_422, N_424, N_423, - N_170, N_419, N_421, N_420, N_620, N_416, N_418, N_417, - N_619, N_413, N_415, N_414, N_39, N_410, N_650, N_409, - N_453, N_391, N_392, N_390, N_452, N_388, N_389, N_387, - N_626, N_457, N_459, N_458, N_622, N_439, N_441, N_440, - N_636, N_595, N_601, N_598, N_454, N_394, N_395, N_393, - N_627, N_460, N_652, N_461, N_628, N_653, N_465, N_654, - N_32, N_661, N_662, N_660, \state_RNO[0]\, N_404, N_403, - \state_0_RNIUUDG_0[4]\, N_450, N_668, N_328, N_451, N_664, - N_408, N_407, \state_RNIJ7F62[1]\, \write\, - \state_nsss[4]\, N_402, N_400, N_401, \state[1]\, N_655, - N_325, \state_srsts_0_i_i_0_1[3]\, N_656, N_623, N_442, - N_444, N_443, N_630, N_491, N_532, N_498, - \state_srsts_0_i_i_0_1_tz[3]\, \hwrite\, \state_RNO[2]\, - \state_srsts_0_i_0_i_a2_0[2]\, N_319, N_335, N_351, N_353, - N_354, N_355, N_357, N_363, N_374, N_376, N_377, N_365, - N_349, N_342, \haddr[5]\, I_13_6, I_186_0, \haddr[20]\, - I_115_0, N_358, N_375, N_322, N_720, N_722, N_316, N_320, - I_24_3, \len[5]\, N_343, N_344, I_5_3, N_345, I_9_3, - N_347, I_20_3, N_348, N_356, N_350, \state[3]\, N_346, - I_13_7, write_0_sqmuxa, write_0_sqmuxa_0, write_RNO, - N_215, \haddr[2]\, \haddr[3]\, I_5_2, I_24_2, I_143_0, - I_156_0, I_166_0, I_173_0, I_196_0, I_203_0, I_210_0, - \haddr[10]\, I_45_0, I_52_0, \state[4]\, - \state_RNIBAHA2_0[4]\, I_77_0, \state_RNIBAHA2[4]\, - \haddr[7]\, \haddr[17]\, I_91_0, \haddr[18]\, I_98_0, - \haddr[19]\, I_105_0, \haddr[11]\, \haddr[21]\, I_122_0, - \haddr[23]\, I_136_0, \haddr[15]\, N_338, N_367, N_368, - N_378, \state_RNIGT3N[4]\, N_352, I_56_0, \haddr[12]\, - \N_321\, I_129_0, \haddr[22]\, I_31_2, I_66_0, - \haddr[13]\, I_9_2, \haddr[4]\, I_20_2, \haddr[6]\, - I_73_0, \haddr[14]\, N_327, write_1_sqmuxa, N_339, N_379, - N_640, N_372, N_370, N_639, N_341, N_340, N_337, N_336, - \haddr[8]\, I_84_0, \haddr[16]\, I_38_0, \haddr[9]\, - \haddr[0]\, \haddr[1]\, \haddr[24]\, \haddr[25]\, - \haddr[26]\, \haddr[27]\, \haddr[28]\, \haddr[29]\, - \haddr[30]\, \haddr[31]\, \len[2]\, \len[4]\, \hwdata[0]\, - \hwdata[1]\, \hwdata[2]\, \hwdata[3]\, \hwdata[4]\, - \hwdata[5]\, \hwdata[6]\, \hwdata[7]\, \hwdata[8]\, - \hwdata[9]\, \hwdata[10]\, \hwdata[11]\, \hwdata[12]\, - \hwdata[13]\, \hwdata[14]\, \hwdata[15]\, \hwdata[16]\, - \hwdata[17]\, \hwdata[18]\, \hwdata[19]\, \hwdata[20]\, - \hwdata[21]\, \hwdata[22]\, \hwdata[23]\, N_4, - \DWACT_FINC_E[24]\, \DWACT_FINC_E[23]\, - \DWACT_FINC_E[25]\, N_9, \DWACT_FINC_E[29]\, - \DWACT_FINC_E[30]\, N_14, \DWACT_FINC_E[15]\, - \DWACT_FINC_E[17]\, \DWACT_FINC_E[22]\, N_21, - \DWACT_FINC_E[21]\, \DWACT_FINC_E[9]\, \DWACT_FINC_E[12]\, - \DWACT_FINC_E[20]\, N_30_0, \DWACT_FINC_E[13]\, - \DWACT_FINC_E[19]\, N_35, \DWACT_FINC_E[18]\, N_42, - \DWACT_FINC_E[33]\, \DWACT_FINC_E[34]\, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[5]\, N_51, \DWACT_FINC_E[28]\, - \DWACT_FINC_E[16]\, N_56, N_61, \DWACT_FINC_E[14]\, N_66, - N_71, \DWACT_FINC_E[10]\, N_78, \DWACT_FINC_E[11]\, N_83, - N_88, N_93, \DWACT_FINC_E[8]\, N_98, N_106, N_113, - \DWACT_FINC_E[3]\, N_121, N_126, N_131, \DWACT_FINC_E[1]\, - N_136, N_144, N_4_0, N_12, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - hwdata(23) <= \hwdata[23]\; - hwdata(22) <= \hwdata[22]\; - hwdata(21) <= \hwdata[21]\; - hwdata(20) <= \hwdata[20]\; - hwdata(19) <= \hwdata[19]\; - hwdata(18) <= \hwdata[18]\; - hwdata(17) <= \hwdata[17]\; - hwdata(16) <= \hwdata[16]\; - hwdata(15) <= \hwdata[15]\; - hwdata(14) <= \hwdata[14]\; - hwdata(13) <= \hwdata[13]\; - hwdata(12) <= \hwdata[12]\; - hwdata(11) <= \hwdata[11]\; - hwdata(10) <= \hwdata[10]\; - hwdata(9) <= \hwdata[9]\; - hwdata(8) <= \hwdata[8]\; - hwdata(7) <= \hwdata[7]\; - hwdata(6) <= \hwdata[6]\; - hwdata(5) <= \hwdata[5]\; - hwdata(4) <= \hwdata[4]\; - hwdata(3) <= \hwdata[3]\; - hwdata(2) <= \hwdata[2]\; - hwdata(1) <= \hwdata[1]\; - hwdata(0) <= \hwdata[0]\; - state_i(5) <= \state_i[5]\; - haddr(31) <= \haddr[31]\; - haddr(30) <= \haddr[30]\; - haddr(29) <= \haddr[29]\; - haddr(28) <= \haddr[28]\; - haddr(27) <= \haddr[27]\; - haddr(26) <= \haddr[26]\; - haddr(25) <= \haddr[25]\; - haddr(24) <= \haddr[24]\; - haddr(23) <= \haddr[23]\; - haddr(22) <= \haddr[22]\; - haddr(21) <= \haddr[21]\; - haddr(20) <= \haddr[20]\; - haddr(19) <= \haddr[19]\; - haddr(18) <= \haddr[18]\; - haddr(17) <= \haddr[17]\; - haddr(16) <= \haddr[16]\; - haddr(15) <= \haddr[15]\; - haddr(14) <= \haddr[14]\; - haddr(13) <= \haddr[13]\; - haddr(12) <= \haddr[12]\; - haddr(11) <= \haddr[11]\; - haddr(10) <= \haddr[10]\; - haddr(9) <= \haddr[9]\; - haddr(8) <= \haddr[8]\; - haddr(7) <= \haddr[7]\; - haddr(6) <= \haddr[6]\; - haddr(5) <= \haddr[5]\; - haddr(4) <= \haddr[4]\; - haddr(3) <= \haddr[3]\; - haddr(2) <= \haddr[2]\; - haddr(1) <= \haddr[1]\; - haddr(0) <= \haddr[0]\; - N_321 <= \N_321\; - hwrite <= \hwrite\; - write <= \write\; - - \r.state_RNIGGC11[2]\ : AO1A - port map(A => \state[2]\, B => \N_321\, C => N_327, Y => - N_328); - - un5_newaddr_I_172 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[19]\, Y => N_30_0); - - un5_newaddr_I_114 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[12]\, Y => N_71); - - \r.clen_RNO_1[1]\ : AXOI1 - port map(A => N_322, B => N_411_i_1, C => \clen[1]\, Y => - N_664); - - \r.state_RNIPBR32[0]\ : AO1A - port map(A => \state[0]\, B => N_319, C => N_720, Y => - N_308); - - \r.data[27]\ : DFN1E1 - port map(D => N_354, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(27)); - - \r.addr_RNO_0[10]\ : OR2B - port map(A => N_682_0, B => \haddr[10]\, Y => N_445); - - \r.addr[21]\ : DFN1E1 - port map(D => N_635, CLK => lclk_c, E => state_4_0, Q => - \haddr[21]\); - - \r.state_RNI7EEE_0[2]\ : NOR2A - port map(A => \state[2]\, B => thempty, Y => write_1_sqmuxa); - - \r.addr_RNO_1[22]\ : OR2B - port map(A => \state[4]\, B => \haddr[14]\, Y => N_601); - - un5_newaddr_I_87 : AND3 - port map(A => \haddr[14]\, B => \haddr[15]\, C => - \haddr[16]\, Y => \DWACT_FINC_E[9]\); - - un5_newaddr_I_27 : AND2 - port map(A => \haddr[5]\, B => \haddr[6]\, Y => - \DWACT_FINC_E[1]\); - - \r.data[17]\ : DFN1E1 - port map(D => N_375, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[17]\); - - un5_newaddr_I_115 : XOR2 - port map(A => N_71, B => \haddr[20]\, Y => I_115_0); - - \r.addr_RNO[3]\ : NOR3 - port map(A => N_391, B => N_392, C => N_390, Y => N_453); - - \r.len[2]\ : DFN1E1 - port map(D => N_345, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[2]\); - - \r.addr[15]\ : DFN1E1 - port map(D => N_629, CLK => lclk_c, E => state_4_0, Q => - \haddr[15]\); - - \r.addr_RNO[13]\ : OR3C - port map(A => N_460, B => N_652, C => N_461, Y => N_627); - - \r.addr_RNO_2[29]\ : OR2A - port map(A => I_196_0, B => N_680_0, Y => N_429); - - \r.addr_RNO_1[2]\ : NOR2A - port map(A => \state_0[4]\, B => data(2), Y => N_389); - - \r.state_0_RNISCH52[4]\ : OR2A - port map(A => N_308, B => \state_0[4]\, Y => N_680_0); - - \r.addr_RNO_0[20]\ : OR2B - port map(A => N_682_0, B => \haddr[20]\, Y => N_574); - - un5_newaddr_I_128 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[14]\, Y => N_61); - - \r.data[25]\ : DFN1E1 - port map(D => N_352, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(25)); - - un5_newaddr_I_159 : AND3 - port map(A => \haddr[23]\, B => \haddr[24]\, C => - \haddr[25]\, Y => \DWACT_FINC_E[17]\); - - \r.state_0[3]\ : DFN1 - port map(D => \state_0_RNIIOIE4[3]\, CLK => lclk_c, Q => - \state_0[3]\); - - \r.addr_RNO_2[31]\ : OR2A - port map(A => I_210_0, B => N_680_0, Y => N_435); - - \r.addr_RNO[12]\ : OR3C - port map(A => N_457, B => N_459, C => N_458, Y => N_626); - - un5_newaddr_I_196 : XOR2 - port map(A => N_14, B => \haddr[29]\, Y => I_196_0); - - \r.addr[19]\ : DFN1E1 - port map(D => N_633, CLK => lclk_c, E => state_4_0, Q => - \haddr[19]\); - - \r.data[15]\ : DFN1E1 - port map(D => N_640, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[15]\); - - \r.state_RNO_1[0]\ : AOI1 - port map(A => \state[1]\, B => N_318, C => \state[0]\, Y - => N_403); - - \r.addr_RNO_2[17]\ : OR2A - port map(A => I_91_0, B => \state_RNIBAHA2[4]\, Y => N_537); - - \r.addr_RNO_2[6]\ : NOR2A - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[6]\, Y => - N_660); - - \r.clen_RNO[0]\ : NOR3 - port map(A => N_668, B => \clen_1_i_0_0[0]\, C => N_328, Y - => N_450); - - \r.addr_RNO_2[16]\ : OR2A - port map(A => I_84_0, B => \state_RNIBAHA2[4]\, Y => N_498); - - \r.addr_RNO_1[10]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[2]\, Y => N_447); - - \r.clen_RNIKSR6[1]\ : NOR3C - port map(A => N_411_i_1, B => \clen[1]\, C => dready, Y => - N_318); - - \r.addr_RNO[10]\ : OR3C - port map(A => N_445, B => N_447, C => N_446, Y => N_624); - - \r.addr[28]\ : DFN1E1 - port map(D => N_194, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[28]\); - - \r.addr_RNO_0[9]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[9]\, Y => - N_442); - - un5_newaddr_I_206 : AND2 - port map(A => \haddr[29]\, B => \haddr[30]\, Y => - \DWACT_FINC_E[25]\); - - \r.state_RNI1HBD[1]\ : NOR2 - port map(A => \state[4]\, B => \state[1]\, Y => \N_321\); - - \r.addr_RNO_2[11]\ : OR2A - port map(A => I_52_0, B => N_680_0, Y => N_449); - - un5_newaddr_I_165 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[18]\, Y => N_35); - - \r.addr[5]\ : DFN1E1 - port map(D => N_30, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[5]\); - - un5_newaddr_I_13 : XOR2 - port map(A => N_144, B => \haddr[5]\, Y => I_13_6); - - \r.data_RNO[22]\ : MX2 - port map(A => \hwdata[14]\, B => hrdata_0_22, S => - \state_0[3]\, Y => N_349); - - \r.addr_RNO[14]\ : OR3C - port map(A => N_653, B => N_465, C => N_654, Y => N_628); - - un5_newaddr_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \haddr[11]\, C => - \haddr[12]\, Y => N_106); - - un5_newaddr_I_91 : XOR2 - port map(A => N_88, B => \haddr[17]\, Y => I_91_0); - - \r.addr_RNO_2[24]\ : OR2A - port map(A => I_143_0, B => N_680_0, Y => N_414); - - \r.addr_RNO[19]\ : OR3C - port map(A => N_562, B => N_571, C => N_568, Y => N_633); - - un5_newaddr_I_122 : XOR2 - port map(A => N_66, B => \haddr[21]\, Y => I_122_0); - - \r.data[23]\ : DFN1E1 - port map(D => N_350, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[23]\); - - \r.clen_RNO[1]\ : NOR3 - port map(A => N_328, B => \clen_1_i_0_0[1]\, C => N_664, Y - => N_451); - - un5_newaddr_I_5 : XOR2 - port map(A => \haddr[2]\, B => \haddr[3]\, Y => I_5_2); - - \r.state_RNIV8BD[0]\ : OR2 - port map(A => \state[3]\, B => \state[0]\, Y => N_327); - - un5_newaddr_I_118 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[13]\); - - \r.state_RNIJ7F62[1]\ : OR3C - port map(A => \write\, B => N_438, C => N_721, Y => - \state_RNIJ7F62[1]\); - - \r.data[13]\ : DFN1E1 - port map(D => N_370, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[13]\); - - \r.data[20]\ : DFN1E1 - port map(D => N_378, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[20]\); - - \r.data_RNO[26]\ : MX2 - port map(A => \hwdata[18]\, B => hrdata_0_26, S => - \state_0[3]\, Y => N_353); - - \r.addr_RNO_0[8]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[8]\, Y => - N_439); - - un5_newlen_I_9 : XNOR2 - port map(A => N_15, B => \len[2]\, Y => I_9_3); - - \r.state_RNIU4BD[0]\ : NOR2 - port map(A => \state[0]\, B => \state[2]\, Y => - state_4_0_0_0_0); - - \r.len_RNO[4]\ : MX2 - port map(A => data(4), B => I_20_3, S => \state_i[5]\, Y - => N_347); - - \r.data[26]\ : DFN1E1 - port map(D => N_353, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(26)); - - \r.data_RNO[19]\ : MX2 - port map(A => \hwdata[11]\, B => N_264_0, S => \state_0[3]\, - Y => N_377); - - \r.data[10]\ : DFN1E1 - port map(D => N_365, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[10]\); - - un5_newaddr_I_192 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[22]\, Y => \DWACT_FINC_E[23]\); - - \r.data_RNO[18]\ : MX2 - port map(A => \hwdata[10]\, B => hrdata_0_18, S => - \state_0[3]\, Y => N_376); - - \r.state_RNO_2[1]\ : OR3B - port map(A => N_316, B => N_720, C => \un1_rst_0_o4\, Y => - N_401); - - \r.len_RNO[2]\ : MX2 - port map(A => data(2), B => I_9_3, S => \state_i[5]\, Y => - N_345); - - \r.addr_RNO_1[31]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[23]\, Y => N_436); - - \r.data[16]\ : DFN1E1 - port map(D => N_374, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[16]\); - - \r.addr_RNO_0[30]\ : OR2B - port map(A => N_682_0, B => \haddr[30]\, Y => N_431); - - \r.len_RNIS3A[5]\ : OR2A - port map(A => I_24_3, B => \len[5]\, Y => N_316); - - un5_newlen_I_20 : XNOR2 - port map(A => N_7, B => \len[4]\, Y => I_20_3); - - un5_newaddr_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \haddr[7]\, Y => N_131); - - \r.data_RNO[1]\ : MX2 - port map(A => data(1), B => hrdata_0_1, S => \state[3]\, Y - => N_336); - - \r.addr_RNO_1[23]\ : OR2B - port map(A => \state[4]\, B => \haddr[15]\, Y => N_610); - - \r.state_0_RNIIOIE4[3]\ : OR3C - port map(A => \state_srsts_0_i_i_0_1[3]\, B => N_655, C => - N_656, Y => \state_0_RNIIOIE4[3]\); - - \r.len_RNIRKA41[5]\ : OR3B - port map(A => N_316, B => N_722, C => \un1_rst_0_o4\, Y => - N_656); - - \r.addr_RNO_1[25]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[17]\, Y => N_418); - - un5_newaddr_I_166 : XOR2 - port map(A => N_35, B => \haddr[26]\, Y => I_166_0); - - \r.data[30]\ : DFN1E1 - port map(D => N_357, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(30)); - - \r.addr_RNO_0[6]\ : NOR2 - port map(A => I_20_2, B => \state_RNIBAHA2[4]\, Y => N_661); - - \r.addr_RNO_2[22]\ : OR2A - port map(A => I_129_0, B => \state_RNIBAHA2[4]\, Y => N_598); - - \r.addr_RNO[16]\ : OR3C - port map(A => N_491, B => N_532, C => N_498, Y => N_630); - - \r.addr[14]\ : DFN1E1 - port map(D => N_628, CLK => lclk_c, E => state_4_0, Q => - \haddr[14]\); - - \r.addr_RNO_1[4]\ : NOR2A - port map(A => \state[4]\, B => data(4), Y => N_395); - - un5_newaddr_I_45 : XOR2 - port map(A => N_121, B => \haddr[10]\, Y => I_45_0); - - \r.state_RNO[2]\ : AOI1 - port map(A => \state_srsts_0_i_0_i_a2_0[2]\, B => N_721, C - => \un1_rst_0_o4\, Y => \state_RNO[2]\); - - \r.addr_RNO[2]\ : NOR3 - port map(A => N_388, B => N_389, C => N_387, Y => N_452); - - \r.state[1]\ : DFN1 - port map(D => \state_nsss[4]\, CLK => lclk_c, Q => - \state[1]\); - - \r.addr_RNO[8]\ : OR3C - port map(A => N_439, B => N_441, C => N_440, Y => N_622); - - \r.data_RNO[5]\ : MX2 - port map(A => data(5), B => hrdata_0_d0, S => \state[3]\, Y - => N_340); - - \r.data_RNO[11]\ : MX2 - port map(A => \hwdata[3]\, B => hrdata_0_11, S => - \state[3]\, Y => N_367); - - \r.data_RNO[17]\ : MX2 - port map(A => \hwdata[9]\, B => hrdata_0_17, S => - \state_0[3]\, Y => N_375); - - \r.clen_RNO_0[1]\ : OAI1 - port map(A => dready, B => \clen_1_i_0_a2_0_0[1]\, C => - \state_i[5]\, Y => \clen_1_i_0_0[1]\); - - \r.state[2]\ : DFN1 - port map(D => \state_RNO[2]\, CLK => lclk_c, Q => - \state[2]\); - - \r.addr_RNO_2[19]\ : OR2A - port map(A => I_105_0, B => \state_RNIBAHA2[4]\, Y => N_568); - - \r.addr[2]\ : DFN1E1 - port map(D => N_452, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[2]\); - - \r.state_RNO_0[0]\ : NOR3B - port map(A => active, B => iosn_2(93), C => \state[1]\, Y - => N_404); - - \r.state_RNI7EEE[2]\ : OR2B - port map(A => thempty, B => \state[2]\, Y => \write\); - - \r.addr[17]\ : DFN1E1 - port map(D => N_631, CLK => lclk_c, E => state_4_0, Q => - \haddr[17]\); - - un5_newaddr_I_146 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \haddr[23]\, C => - \haddr[24]\, Y => \DWACT_FINC_E[33]\); - - \r.state_i_RNO_1[5]\ : NOR2 - port map(A => \state_i[5]\, B => N_320, Y => N_406); - - \r.addr[13]\ : DFN1E1 - port map(D => N_627, CLK => lclk_c, E => state_4_0, Q => - \haddr[13]\); - - \r.state_RNO[0]\ : NOR3 - port map(A => N_404, B => N_403, C => \un1_rst_0_o4\, Y => - \state_RNO[0]\); - - un5_newaddr_I_203 : XOR2 - port map(A => N_9, B => \haddr[30]\, Y => I_203_0); - - un5_newaddr_I_94 : AND2 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, Y - => \DWACT_FINC_E[10]\); - - GND_i : GND - port map(Y => \GND\); - - un5_newaddr_I_179 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[20]\, Y => \DWACT_FINC_E[21]\); - - \r.addr_RNO[15]\ : OR3C - port map(A => N_487, B => N_490, C => N_489, Y => N_629); - - \r.write\ : DFN1 - port map(D => write_RNO, CLK => lclk_c, Q => \hwrite\); - - \r.addr[12]\ : DFN1E1 - port map(D => N_626, CLK => lclk_c, E => state_4_0, Q => - \haddr[12]\); - - \r.addr[20]\ : DFN1E1 - port map(D => N_634, CLK => lclk_c, E => state_4_0, Q => - \haddr[20]\); - - un5_newaddr_I_73 : XOR2 - port map(A => N_101, B => \haddr[14]\, Y => I_73_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un5_newlen_I_16 : OR3 - port map(A => \len[0]\, B => \len[1]\, C => \len[2]\, Y => - \DWACT_FDEC_E[0]\); - - \r.data_RNO[3]\ : MX2 - port map(A => data(3), B => hrdata_0_3, S => \state[3]\, Y - => N_338); - - \r.addr_RNO_1[5]\ : NOR2A - port map(A => \state_0[4]\, B => data(5), Y => N_398); - - un5_newaddr_I_162 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - Y => \DWACT_FINC_E[18]\); - - \r.addr[26]\ : DFN1E1 - port map(D => N_170, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[26]\); - - un5_newaddr_I_101 : AND2 - port map(A => \haddr[17]\, B => \haddr[18]\, Y => - \DWACT_FINC_E[11]\); - - \r.addr_RNO[9]\ : OR3C - port map(A => N_442, B => N_444, C => N_443, Y => N_623); - - \r.state_0_RNIUUDG_0[4]\ : AO1B - port map(A => dready, B => \state_0[4]\, C => - state_4_0_0_0_0, Y => \state_0_RNIUUDG_0[4]\); - - \r.addr_RNO_1[20]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[12]\, Y => N_580); - - \r.data[8]\ : DFN1E1 - port map(D => N_363, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[8]\); - - \r.addr_RNO_2[14]\ : OR2A - port map(A => I_73_0, B => \state_RNIBAHA2[4]\, Y => N_654); - - \r.data_RNO[20]\ : MX2 - port map(A => \hwdata[12]\, B => N_262_0, S => \state[3]\, - Y => N_378); - - un5_newaddr_I_142 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[16]\, Y => N_51); - - \r.addr_RNO_2[23]\ : OR2A - port map(A => I_136_0, B => \state_RNIBAHA2[4]\, Y => N_607); - - \r.addr_RNO_2[25]\ : OR2A - port map(A => I_156_0, B => N_680_0, Y => N_417); - - \r.addr_RNO_0[18]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[18]\, Y - => N_550); - - un5_newaddr_I_209 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[25]\, Y => N_4); - - \r.len[0]\ : DFN1E1 - port map(D => N_343, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[0]\); - - un5_newaddr_I_84 : XOR2 - port map(A => N_93, B => \haddr[16]\, Y => I_84_0); - - un5_newaddr_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \haddr[10]\, C => - \haddr[11]\, Y => N_113); - - un5_newaddr_I_24 : XOR2 - port map(A => N_136, B => \haddr[7]\, Y => I_24_2); - - un5_newaddr_I_185 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[21]\, Y => N_21); - - \r.addr[4]\ : DFN1E1 - port map(D => N_454, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[4]\); - - \r.addr_RNO_2[7]\ : NOR2A - port map(A => N_682_0, B => \haddr[7]\, Y => N_409); - - un5_newaddr_I_129 : XOR2 - port map(A => N_61, B => \haddr[22]\, Y => I_129_0); - - \r.data[1]\ : DFN1E1 - port map(D => N_336, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[1]\); - - \r.addr_RNO_2[12]\ : OR2A - port map(A => I_56_0, B => \state_RNIBAHA2[4]\, Y => N_458); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.addr_RNO_0[28]\ : OR2B - port map(A => N_682_0, B => \haddr[28]\, Y => N_425); - - \r.addr[31]\ : DFN1E1 - port map(D => N_621, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[31]\); - - \r.data[0]\ : DFN1E1 - port map(D => N_335, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[0]\); - - \r.addr_RNO[18]\ : OR3C - port map(A => N_550, B => N_558, C => N_554, Y => N_632); - - \r.addr[9]\ : DFN1E1 - port map(D => N_623, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[9]\); - - \r.data[3]\ : DFN1E1 - port map(D => N_338, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[3]\); - - un5_newaddr_I_199 : AND2 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - Y => \DWACT_FINC_E[24]\); - - \r.addr_RNO[7]\ : NOR3 - port map(A => N_410, B => N_650, C => N_409, Y => N_39); - - un5_newlen_I_12 : OR3 - port map(A => \len[0]\, B => \len[1]\, C => \len[2]\, Y => - N_12); - - \r.state_RNI2BKH1[2]\ : OR3C - port map(A => active, B => iosn_0(93), C => - \state_srsts_0_i_i_0_o2_0[3]\, Y => N_325); - - un5_newaddr_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \haddr[8]\, Y => N_126); - - \r.write_RNO_0\ : MX2 - port map(A => data(6), B => \hwrite\, S => write_0_sqmuxa_0, - Y => N_215); - - \r.addr_RNO_1[18]\ : OR2B - port map(A => \state[4]\, B => \haddr[10]\, Y => N_558); - - \r.addr_RNO[5]\ : NOR3 - port map(A => N_397, B => N_398, C => N_396, Y => N_30); - - \r.data_RNO[30]\ : MX2 - port map(A => \hwdata[22]\, B => hrdata_25, S => - \state_0[3]\, Y => N_357); - - \r.addr_RNO_2[8]\ : OR2A - port map(A => I_31_2, B => \state_RNIBAHA2[4]\, Y => N_440); - - \r.addr_RNO_0[17]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[17]\, Y - => N_535); - - \r.data_RNO[13]\ : MX2 - port map(A => \hwdata[5]\, B => hrdata_0_13, S => - \state[3]\, Y => N_370); - - \r.addr_RNO_2[3]\ : NOR2A - port map(A => N_682_0, B => \haddr[3]\, Y => N_390); - - \r.addr[25]\ : DFN1E1 - port map(D => N_620, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[25]\); - - un5_newaddr_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - \r.clen[1]\ : DFN1E0 - port map(D => N_451, CLK => lclk_c, E => write_1_sqmuxa, Q - => \clen[1]\); - - un5_newaddr_I_186 : XOR2 - port map(A => N_21, B => \haddr[28]\, Y => I_186_0); - - \r.addr_RNO_0[16]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[16]\, Y - => N_491); - - un5_newaddr_I_98 : XOR2 - port map(A => N_83, B => \haddr[18]\, Y => I_98_0); - - \r.data_RNO[6]\ : MX2 - port map(A => data(6), B => hrdata_1, S => \state[3]\, Y - => N_341); - - \r.state_RNIJNB8[2]\ : NOR2 - port map(A => \state[2]\, B => \state_0[4]\, Y => - \state_srsts_0_i_i_0_o2_0[3]\); - - \r.addr_RNO_0[11]\ : OR2B - port map(A => N_682_0, B => \haddr[11]\, Y => N_448); - - \r.len_RNO[5]\ : MX2 - port map(A => data(5), B => I_24_3, S => \state_i[5]\, Y - => N_348); - - \r.addr_RNO_0[27]\ : OR2B - port map(A => N_682_0, B => \haddr[27]\, Y => N_422); - - \r.addr[29]\ : DFN1E1 - port map(D => N_204, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[29]\); - - \r.addr_RNO_2[5]\ : NOR2A - port map(A => N_682_0, B => \haddr[5]\, Y => N_396); - - un5_newaddr_I_69 : AND3 - port map(A => \haddr[11]\, B => \haddr[12]\, C => - \haddr[13]\, Y => \DWACT_FINC_E[7]\); - - \r.addr_RNO_2[20]\ : OR2A - port map(A => I_115_0, B => N_680_0, Y => N_577); - - un5_newaddr_I_210 : XOR2 - port map(A => N_4, B => \haddr[31]\, Y => I_210_0); - - \r.addr_RNO_0[26]\ : OR2B - port map(A => N_682_0, B => \haddr[26]\, Y => N_419); - - \r.data[4]\ : DFN1E1 - port map(D => N_339, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[4]\); - - \r.addr_RNO_1[7]\ : NOR2A - port map(A => \state_0[4]\, B => data(7), Y => N_650); - - \r.len_RNO[0]\ : MX2B - port map(A => data(0), B => \len[0]\, S => \state_i[5]\, Y - => N_343); - - \r.addr_RNO_0[2]\ : NOR2A - port map(A => \haddr[2]\, B => N_680_0, Y => N_388); - - \r.addr_RNO_0[21]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[21]\, Y - => N_583); - - \r.addr[3]\ : DFN1E1 - port map(D => N_453, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[3]\); - - \r.state_RNICB28[1]\ : OR2B - port map(A => dready, B => \state[1]\, Y => N_438); - - \r.state_RNIBAHA2[4]\ : OR2A - port map(A => N_308, B => \state[4]\, Y => - \state_RNIBAHA2[4]\); - - \r.addr_RNO_1[9]\ : OR2B - port map(A => \state[4]\, B => \haddr[1]\, Y => N_444); - - un5_newaddr_I_9 : XOR2 - port map(A => N_147, B => \haddr[4]\, Y => I_9_2); - - \r.addr_RNO[27]\ : OR3C - port map(A => N_422, B => N_424, C => N_423, Y => N_172); - - \r.addr_RNO_1[17]\ : OR2B - port map(A => \state[4]\, B => \haddr[9]\, Y => N_546); - - \r.state_0[4]\ : DFN1 - port map(D => \state_i_RNIIHN51[5]\, CLK => lclk_c, Q => - \state_0[4]\); - - \r.data_RNO[0]\ : MX2 - port map(A => data(0), B => hrdata_0_0, S => \state_0[3]\, - Y => N_335); - - un5_newaddr_I_135 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[15]\, Y => N_56); - - \r.addr_RNO_1[16]\ : OR2B - port map(A => \state[4]\, B => \haddr[8]\, Y => N_532); - - \r.addr_RNO[6]\ : NOR3 - port map(A => N_661, B => N_662, C => N_660, Y => N_32); - - un5_newaddr_I_169 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \haddr[26]\, Y => \DWACT_FINC_E[19]\); - - \r.addr_RNO_2[13]\ : OR2A - port map(A => I_66_0, B => \state_RNIBAHA2[4]\, Y => N_461); - - \r.addr_RNO_1[11]\ : OR2B - port map(A => \state[4]\, B => \haddr[3]\, Y => N_456); - - un5_newaddr_I_173 : XOR2 - port map(A => N_30_0, B => \haddr[27]\, Y => I_173_0); - - \r.addr_RNO_2[15]\ : OR2A - port map(A => I_77_0, B => \state_RNIBAHA2[4]\, Y => N_489); - - un5_newaddr_I_12 : AND3 - port map(A => \haddr[2]\, B => \haddr[3]\, C => \haddr[4]\, - Y => N_144); - - \r.state_i_RNIER5C[5]\ : OA1C - port map(A => N_320, B => \state_i[5]\, C => \state[4]\, Y - => N_407); - - \r.data_RNO[29]\ : MX2 - port map(A => \hwdata[21]\, B => hrdata_24, S => - \state_0[3]\, Y => N_356); - - \r.state_RNO_3[1]\ : NOR2B - port map(A => \hwrite\, B => N_318, Y => - \state_srsts_0_0_0_a2_5_0[1]\); - - \r.data_RNO[28]\ : MX2 - port map(A => \hwdata[20]\, B => hrdata_23, S => - \state_0[3]\, Y => N_355); - - \r.addr_RNO[21]\ : OR3C - port map(A => N_583, B => N_592, C => N_589, Y => N_635); - - un5_newaddr_I_182 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[30]\); - - \r.data_RNO[15]\ : MX2 - port map(A => \hwdata[7]\, B => hrdata_0_15, S => - \state[3]\, Y => N_640); - - \r.clen_RNO_0[0]\ : NOR2A - port map(A => N_411_i_1, B => N_322, Y => N_668); - - un5_newaddr_I_104 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \DWACT_FINC_E[11]\, Y => N_78); - - un5_newaddr_I_19 : NOR2B - port map(A => \haddr[5]\, B => \DWACT_FINC_E[0]\, Y => - N_139); - - \r.addr_RNO_2[4]\ : NOR2A - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[4]\, Y => - N_393); - - un5_newaddr_I_77 : XOR2 - port map(A => N_98, B => \haddr[15]\, Y => I_77_0); - - un5_newaddr_I_149 : AND3 - port map(A => \haddr[2]\, B => \haddr[3]\, C => \haddr[4]\, - Y => \DWACT_FINC_E[34]\); - - un5_newaddr_I_105 : XOR2 - port map(A => N_78, B => \haddr[19]\, Y => I_105_0); - - \r.addr_RNO_0[19]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[19]\, Y - => N_562); - - \r.addr[24]\ : DFN1E1 - port map(D => N_619, CLK => lclk_c, E => state_4_0, Q => - \haddr[24]\); - - un5_newaddr_I_66 : XOR2 - port map(A => N_106, B => \haddr[13]\, Y => I_66_0); - - \r.data_RNO[21]\ : MX2 - port map(A => \hwdata[13]\, B => hrdata_0_21, S => - \state[3]\, Y => N_379); - - un5_newaddr_I_41 : AND2 - port map(A => \haddr[8]\, B => \haddr[9]\, Y => - \DWACT_FINC_E[3]\); - - \r.data_RNO[27]\ : MX2 - port map(A => \hwdata[19]\, B => hrdata_0_27, S => - \state_0[3]\, Y => N_354); - - un5_newaddr_I_136 : XOR2 - port map(A => N_56, B => \haddr[23]\, Y => I_136_0); - - \r.len[1]\ : DFN1E1 - port map(D => N_344, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[1]\); - - \r.addr_RNO_0[3]\ : NOR2 - port map(A => I_5_2, B => N_680_0, Y => N_391); - - un5_newaddr_I_8 : NOR2B - port map(A => \haddr[3]\, B => \haddr[2]\, Y => N_147); - - \r.addr_RNO_0[31]\ : OR2B - port map(A => N_682_0, B => \haddr[31]\, Y => N_434); - - \r.addr_RNO[4]\ : NOR3 - port map(A => N_394, B => N_395, C => N_393, Y => N_454); - - \r.data_RNO[14]\ : MX2 - port map(A => \hwdata[6]\, B => hrdata_0_14, S => - \state[3]\, Y => N_372); - - \r.clen_RNO_1[0]\ : OAI1 - port map(A => dready, B => \clen_1_i_0_a2_0_0[0]\, C => - \state_i[5]\, Y => \clen_1_i_0_0[0]\); - - \r.addr_RNO_2[30]\ : OR2A - port map(A => I_203_0, B => N_680_0, Y => N_432); - - \r.state_0_RNI57D32[3]\ : OR3B - port map(A => N_325, B => \state_0[3]\, C => \un1_rst_0_o4\, - Y => N_655); - - \r.addr_RNO_0[29]\ : OR2B - port map(A => N_682_0, B => \haddr[29]\, Y => N_428); - - \r.addr[11]\ : DFN1E1 - port map(D => N_625, CLK => lclk_c, E => state_4_0, Q => - \haddr[11]\); - - un5_newaddr_I_31 : XOR2 - port map(A => N_131, B => \haddr[8]\, Y => I_31_2); - - \r.addr[30]\ : DFN1E1 - port map(D => N_212, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[30]\); - - \r.addr_RNO[23]\ : OR3C - port map(A => N_604, B => N_610, C => N_607, Y => N_637); - - \r.addr[6]\ : DFN1E1 - port map(D => N_32, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[6]\); - - un5_newaddr_I_155 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[33]\, Y => N_42); - - \r.state_RNI07BE[0]\ : OR2A - port map(A => N_327, B => active, Y => hbusreq_i_3); - - \r.addr[27]\ : DFN1E1 - port map(D => N_172, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[27]\); - - \r.data_RNO[7]\ : MX2 - port map(A => data(7), B => hrdata_0_7, S => \state_0[3]\, - Y => N_342); - - \r.addr_RNO_1[8]\ : OR2B - port map(A => \state[4]\, B => \haddr[0]\, Y => N_441); - - \r.addr_RNO_1[28]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[20]\, Y => N_427); - - \r.addr[23]\ : DFN1E1 - port map(D => N_637, CLK => lclk_c, E => state_4_0, Q => - \haddr[23]\); - - \r.data[22]\ : DFN1E1 - port map(D => N_349, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[22]\); - - \r.addr_RNO[22]\ : OR3C - port map(A => N_595, B => N_601, C => N_598, Y => N_636); - - \r.addr[0]\ : DFN1E0 - port map(D => data(0), CLK => lclk_c, E => - \state_RNIGT3N[4]\, Q => \haddr[0]\); - - \r.state[4]\ : DFN1 - port map(D => \state_i_RNIIHN51[5]\, CLK => lclk_c, Q => - \state[4]\); - - \r.data[12]\ : DFN1E1 - port map(D => N_368, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[12]\); - - \r.addr_RNO_2[10]\ : OR2A - port map(A => I_45_0, B => N_680_0, Y => N_446); - - \r.addr[22]\ : DFN1E1 - port map(D => N_636, CLK => lclk_c, E => state_4_0, Q => - \haddr[22]\); - - un5_newaddr_I_121 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \haddr[20]\, Y => N_66); - - \r.addr_RNO_1[19]\ : OR2B - port map(A => \state[4]\, B => \haddr[11]\, Y => N_571); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.addr_RNO_0[14]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[14]\, Y - => N_653); - - un5_newaddr_I_52 : XOR2 - port map(A => N_116, B => \haddr[11]\, Y => I_52_0); - - un5_newaddr_I_90 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[9]\, Y => N_88); - - un5_newlen_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \len[3]\, C => - \len[4]\, Y => N_4_0); - - \r.addr_RNO_2[2]\ : NOR2A - port map(A => N_682_0, B => \haddr[2]\, Y => N_387); - - \r.addr_RNO[20]\ : OR3C - port map(A => N_574, B => N_580, C => N_577, Y => N_634); - - \r.state_0_RNIUUDG[4]\ : AO1B - port map(A => dready, B => \state_0[4]\, C => - state_4_0_0_0_0, Y => state_4_0); - - \r.len_RNO[3]\ : MX2 - port map(A => data(3), B => I_13_7, S => \state_i[5]\, Y - => N_346); - - \r.data_RNO[31]\ : MX2 - port map(A => \hwdata[23]\, B => hrdata_26, S => - \state_0[3]\, Y => N_358); - - \r.addr_RNO_1[6]\ : NOR2A - port map(A => \state[4]\, B => data(6), Y => N_662); - - un5_newaddr_I_108 : AND3 - port map(A => \haddr[17]\, B => \haddr[18]\, C => - \haddr[19]\, Y => \DWACT_FINC_E[12]\); - - un5_newaddr_I_16 : AND3 - port map(A => \haddr[2]\, B => \haddr[3]\, C => \haddr[4]\, - Y => \DWACT_FINC_E[0]\); - - un5_newaddr_I_72 : NOR2B - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y - => N_101); - - \r.addr[18]\ : DFN1E1 - port map(D => N_632, CLK => lclk_c, E => state_4_0, Q => - \haddr[18]\); - - un5_newaddr_I_132 : AND3 - port map(A => \haddr[20]\, B => \haddr[21]\, C => - \haddr[22]\, Y => \DWACT_FINC_E[15]\); - - \r.state_RNIBAHA2_0[4]\ : NOR2 - port map(A => \state[4]\, B => N_308, Y => - \state_RNIBAHA2_0[4]\); - - \r.state[0]\ : DFN1 - port map(D => \state_RNO[0]\, CLK => lclk_c, Q => - \state[0]\); - - \r.addr_RNO[24]\ : OR3C - port map(A => N_413, B => N_415, C => N_414, Y => N_619); - - \r.addr_RNO_0[24]\ : OR2B - port map(A => N_682_0, B => \haddr[24]\, Y => N_413); - - un5_newaddr_I_59 : AND3 - port map(A => \haddr[8]\, B => \haddr[9]\, C => \haddr[10]\, - Y => \DWACT_FINC_E[5]\); - - \r.state_RNO_1[1]\ : OR3A - port map(A => \state[1]\, B => N_318, C => \un1_rst_0_o4\, - Y => N_400); - - un5_newaddr_I_156 : XOR2 - port map(A => N_42, B => \haddr[25]\, Y => I_156_0); - - \r.addr_RNO[29]\ : OR3C - port map(A => N_428, B => N_430, C => N_429, Y => N_204); - - un5_newaddr_I_83 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[8]\, Y => N_93); - - un5_newaddr_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \haddr[5]\, C => - \haddr[6]\, Y => N_136); - - \r.addr_RNO_1[27]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[19]\, Y => N_424); - - un5_newaddr_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_121); - - \r.addr_RNO_1[30]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[22]\, Y => N_433); - - \r.data_RNO[12]\ : MX2 - port map(A => \hwdata[4]\, B => hrdata_0_12, S => - \state[3]\, Y => N_368); - - \r.data[9]\ : DFN1E1 - port map(D => N_639, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[9]\); - - \r.addr_RNO_0[12]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[12]\, Y - => N_457); - - \r.addr_RNO_1[26]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[18]\, Y => N_421); - - \r.addr_RNO_0[7]\ : NOR2 - port map(A => I_24_2, B => N_680_0, Y => N_410); - - \r.state_0_RNISCH52_0[4]\ : NOR2 - port map(A => \state_0[4]\, B => N_308, Y => N_682_0); - - \r.addr_RNO_1[14]\ : OR2B - port map(A => \state[4]\, B => \haddr[6]\, Y => N_465); - - un5_newaddr_I_111 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\); - - un1_rst_0_o4 : OR3C - port map(A => tcnt(0), B => tcnt(1), C => rstn, Y => - \un1_rst_0_o4\); - - \r.len[4]\ : DFN1E1 - port map(D => N_347, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[4]\); - - \r.addr_RNO_1[21]\ : OR2B - port map(A => \state[4]\, B => \haddr[13]\, Y => N_592); - - un5_newaddr_I_34 : AND3 - port map(A => \haddr[5]\, B => \haddr[6]\, C => \haddr[7]\, - Y => \DWACT_FINC_E[2]\); - - \r.clen[0]\ : DFN1E0 - port map(D => N_450, CLK => lclk_c, E => write_1_sqmuxa, Q - => N_411_i_1); - - un5_newaddr_I_51 : NOR2B - port map(A => \haddr[10]\, B => \DWACT_FINC_E[4]\, Y => - N_116); - - \r.data[28]\ : DFN1E1 - port map(D => N_355, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(28)); - - \r.state_RNIGT3N[4]\ : OR2B - port map(A => state_4_0, B => \state[4]\, Y => - \state_RNIGT3N[4]\); - - \r.addr_RNO_0[4]\ : NOR2 - port map(A => I_9_2, B => \state_RNIBAHA2[4]\, Y => N_394); - - \r.addr_RNO_0[22]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[22]\, Y - => N_595); - - \r.addr[1]\ : DFN1E0 - port map(D => data(1), CLK => lclk_c, E => - \state_RNIGT3N[4]\, Q => \haddr[1]\); - - \r.len[3]\ : DFN1E1 - port map(D => N_346, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[3]\); - - \r.data_RNO[16]\ : MX2 - port map(A => \hwdata[8]\, B => hrdata_0_16, S => - \state_0[3]\, Y => N_374); - - \r.data[18]\ : DFN1E1 - port map(D => N_376, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[18]\); - - \r.addr_RNO[26]\ : OR3C - port map(A => N_419, B => N_421, C => N_420, Y => N_170); - - \r.state[3]\ : DFN1 - port map(D => \state_0_RNIIOIE4[3]\, CLK => lclk_c, Q => - \state[3]\); - - un5_newaddr_I_80 : AND2 - port map(A => \haddr[14]\, B => \haddr[15]\, Y => - \DWACT_FINC_E[8]\); - - un5_newaddr_I_20 : XOR2 - port map(A => N_139, B => \haddr[6]\, Y => I_20_2); - - un5_newaddr_I_189 : AND3 - port map(A => \haddr[26]\, B => \haddr[27]\, C => - \haddr[28]\, Y => \DWACT_FINC_E[22]\); - - \r.state_RNIU9OE[1]\ : NOR2 - port map(A => dready, B => \N_321\, Y => N_322); - - \r.addr_RNO_2[9]\ : OR2A - port map(A => I_38_0, B => \state_RNIBAHA2[4]\, Y => N_443); - - \r.state_i_RNIIHN51[5]\ : NOR3 - port map(A => N_408, B => N_407, C => \un1_rst_0_o4\, Y => - \state_i_RNIIHN51[5]\); - - \r.data[29]\ : DFN1E1 - port map(D => N_356, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(29)); - - un5_newlen_I_5 : XNOR2 - port map(A => \len[0]\, B => \len[1]\, Y => I_5_3); - - \r.state_i_RNO[5]\ : NOR3 - port map(A => N_405, B => N_406, C => \un1_rst_0_o4\, Y => - \state_i_RNO[5]\); - - \r.addr_RNO_2[28]\ : OR2A - port map(A => I_186_0, B => N_680_0, Y => N_426); - - \r.data[24]\ : DFN1E1 - port map(D => N_351, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(24)); - - \r.addr_RNO_1[12]\ : OR2B - port map(A => \state[4]\, B => \haddr[4]\, Y => N_459); - - \r.data_RNO[23]\ : MX2 - port map(A => \hwdata[15]\, B => hrdata_0_23, S => - \state[3]\, Y => N_350); - - \r.data[19]\ : DFN1E1 - port map(D => N_377, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[19]\); - - un5_newaddr_I_152 : AND3 - port map(A => \DWACT_FINC_E[34]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[29]\); - - \r.state_RNIT1UF1[0]\ : NOR3C - port map(A => active, B => iosn_2(93), C => \state[0]\, Y - => N_720); - - \r.addr[8]\ : DFN1E1 - port map(D => N_622, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[8]\); - - un5_newlen_I_19 : OR2 - port map(A => \len[3]\, B => \DWACT_FDEC_E[0]\, Y => N_7); - - \r.len[5]\ : DFN1E1 - port map(D => N_348, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[5]\); - - \r.data[14]\ : DFN1E1 - port map(D => N_372, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[14]\); - - \r.addr_RNO[31]\ : OR3C - port map(A => N_434, B => N_436, C => N_435, Y => N_621); - - un5_newlen_I_8 : OR2 - port map(A => \len[1]\, B => \len[0]\, Y => N_15); - - un5_newaddr_I_56 : XOR2 - port map(A => N_113, B => \haddr[12]\, Y => I_56_0); - - \r.data[6]\ : DFN1E1 - port map(D => N_341, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[6]\); - - \r.data[21]\ : DFN1E1 - port map(D => N_379, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[21]\); - - un5_newlen_I_13 : XNOR2 - port map(A => N_12, B => \len[3]\, Y => I_13_7); - - \r.state_RNO_0[2]\ : AO1C - port map(A => \state_0[3]\, B => N_319, C => \state[2]\, Y - => \state_srsts_0_i_0_i_a2_0[2]\); - - \r.state_0_RNIISQ61[4]\ : OR3B - port map(A => \state_0[4]\, B => - \state_srsts_0_i_i_0_1_tz[3]\, C => \un1_rst_0_o4\, Y => - \state_srsts_0_i_i_0_1[3]\); - - \r.state_nsss_i_i_0_0_o2[0]\ : NOR2B - port map(A => dready, B => data(7), Y => N_320); - - \r.addr[7]\ : DFN1E1 - port map(D => N_39, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[7]\); - - \r.write_RNIES1L\ : AO1A - port map(A => \hwrite\, B => N_318, C => \state[2]\, Y => - \state_srsts_0_i_i_0_1_tz[3]\); - - \r.data[11]\ : DFN1E1 - port map(D => N_367, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[11]\); - - \r.state_RNO_0[1]\ : OR3B - port map(A => \state_0[4]\, B => - \state_srsts_0_0_0_a2_5_0[1]\, C => \un1_rst_0_o4\, Y => - N_402); - - \r.state_i_RNI77R72[5]\ : OR3A - port map(A => write_0_sqmuxa_0, B => N_720, C => N_722, Y - => write_0_sqmuxa); - - \r.addr_RNO[25]\ : OR3C - port map(A => N_416, B => N_418, C => N_417, Y => N_620); - - \r.data[2]\ : DFN1E1 - port map(D => N_337, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[2]\); - - un5_newaddr_I_76 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \haddr[14]\, Y => N_98); - - \r.len_RNO[1]\ : MX2 - port map(A => data(1), B => I_5_3, S => \state_i[5]\, Y => - N_344); - - \r.addr_RNO_0[5]\ : NOR2 - port map(A => I_13_6, B => N_680_0, Y => N_397); - - un5_newaddr_I_143 : XOR2 - port map(A => N_51, B => \haddr[24]\, Y => I_143_0); - - \r.data_RNO[2]\ : MX2 - port map(A => data(2), B => hrdata_0_2, S => \state[3]\, Y - => N_337); - - \r.data[31]\ : DFN1E1 - port map(D => N_358, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(31)); - - \r.addr[10]\ : DFN1E1 - port map(D => N_624, CLK => lclk_c, E => state_4_0, Q => - \haddr[10]\); - - \r.addr_RNO_1[29]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[21]\, Y => N_430); - - \r.clen_RNO_2[1]\ : OR2 - port map(A => \clen[1]\, B => \state[2]\, Y => - \clen_1_i_0_a2_0_0[1]\); - - \r.addr_RNO_2[27]\ : OR2A - port map(A => I_173_0, B => N_680_0, Y => N_423); - - \r.addr_RNO_0[13]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[13]\, Y - => N_460); - - \r.state_RNIJ7F62_0[1]\ : OR3C - port map(A => \write\, B => N_438, C => N_721, Y => - data_0_sqmuxa_0); - - \r.addr[16]\ : DFN1E1 - port map(D => N_630, CLK => lclk_c, E => state_4_0, Q => - \haddr[16]\); - - \r.addr_RNO_0[15]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[15]\, Y - => N_487); - - \r.addr_RNO_2[26]\ : OR2A - port map(A => I_166_0, B => N_680_0, Y => N_420); - - un5_newaddr_I_176 : AND2 - port map(A => \haddr[26]\, B => \haddr[27]\, Y => - \DWACT_FINC_E[20]\); - - \r.state_i_RNICJV3[5]\ : OR2A - port map(A => dready, B => \state_i[5]\, Y => - write_0_sqmuxa_0); - - \r.addr_RNO_2[21]\ : OR2A - port map(A => I_122_0, B => \state_RNIBAHA2[4]\, Y => N_589); - - \r.write_RNO\ : NOR2A - port map(A => N_215, B => \un1_rst_0_o4\, Y => write_RNO); - - \r.addr_RNO[17]\ : OR3C - port map(A => N_535, B => N_546, C => N_537, Y => N_631); - - \r.data_RNO[9]\ : MX2 - port map(A => \hwdata[1]\, B => hrdata_0_9, S => \state[3]\, - Y => N_639); - - \r.clen_RNO_2[0]\ : OR2 - port map(A => N_411_i_1, B => \state[2]\, Y => - \clen_1_i_0_a2_0_0[0]\); - - un5_newaddr_I_97 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \haddr[17]\, Y => N_83); - - \r.data[7]\ : DFN1E1 - port map(D => N_342, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[7]\); - - \r.addr_RNO_0[23]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[23]\, Y - => N_604); - - un5_newlen_I_24 : XNOR2 - port map(A => N_4_0, B => \len[5]\, Y => I_24_3); - - \r.addr_RNO_0[25]\ : OR2B - port map(A => N_682_0, B => \haddr[25]\, Y => N_416); - - un5_newaddr_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un5_newaddr_I_202 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \haddr[29]\, Y => N_9); - - \r.state_RNIUHTJ[2]\ : NOR2B - port map(A => \state[2]\, B => N_319, Y => N_722); - - \r.data_RNO[25]\ : MX2 - port map(A => \hwdata[17]\, B => N_78_0, S => \state[3]\, Y - => N_352); - - un5_newaddr_I_139 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \haddr[23]\, Y => - \DWACT_FINC_E[16]\); - - un5_newaddr_I_125 : AND2 - port map(A => \haddr[20]\, B => \haddr[21]\, Y => - \DWACT_FINC_E[14]\); - - \r.data[5]\ : DFN1E1 - port map(D => N_340, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[5]\); - - \r.addr_RNO[30]\ : OR3C - port map(A => N_431, B => N_433, C => N_432, Y => N_212); - - un5_newaddr_I_38 : XOR2 - port map(A => N_126, B => \haddr[9]\, Y => I_38_0); - - \r.state_i_RNO_0[5]\ : OA1B - port map(A => N_720, B => N_722, C => N_316, Y => N_405); - - \r.data_RNO[10]\ : MX2 - port map(A => \hwdata[2]\, B => hrdata_0_10, S => - \state_0[3]\, Y => N_365); - - \r.addr_RNO[11]\ : OR3C - port map(A => N_448, B => N_456, C => N_449, Y => N_625); - - \r.addr_RNO_1[24]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[16]\, Y => N_415); - - \r.addr_RNO_1[13]\ : OR2B - port map(A => \state[4]\, B => \haddr[5]\, Y => N_652); - - \r.state_RNO[1]\ : OR3C - port map(A => N_402, B => N_400, C => N_401, Y => - \state_nsss[4]\); - - \r.data_RNO[4]\ : MX2 - port map(A => data(4), B => hrdata_0_4, S => \state[3]\, Y - => N_339); - - \r.clen_RNIER7D[1]\ : NOR3C - port map(A => N_411_i_1, B => \clen[1]\, C => thempty, Y - => N_319); - - \r.addr_RNO_1[15]\ : OR2B - port map(A => \state[4]\, B => \haddr[7]\, Y => N_490); - - \r.state_i[5]\ : DFN1 - port map(D => \state_i_RNO[5]\, CLK => lclk_c, Q => - \state_i[5]\); - - \r.state_RNI0EUF1[3]\ : OR3C - port map(A => active, B => iosn_2(93), C => \state[3]\, Y - => N_721); - - \r.addr_RNO[28]\ : OR3C - port map(A => N_425, B => N_427, C => N_426, Y => N_194); - - un5_newaddr_I_195 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[23]\, Y => N_14); - - \r.state_i_RNI3NE9[5]\ : NOR2B - port map(A => \state_i[5]\, B => N_318, Y => N_408); - - \r.addr_RNO_1[3]\ : NOR2A - port map(A => \state_0[4]\, B => data(3), Y => N_392); - - \r.addr_RNO_2[18]\ : OR2A - port map(A => I_98_0, B => \state_RNIBAHA2[4]\, Y => N_554); - - \r.data_RNO[8]\ : MX2 - port map(A => \hwdata[0]\, B => hrdata_0_8, S => - \state_0[3]\, Y => N_363); - - \r.data_RNO[24]\ : MX2 - port map(A => \hwdata[16]\, B => hrdata_0_24, S => - \state_0[3]\, Y => N_351); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbmst is - - port( iosn : in std_logic_vector(93 to 93); - hgrant : in std_logic_vector(1 to 1); - htrans : out std_logic_vector(1 to 1); - iosn_2 : in std_logic_vector(93 to 93); - lclk_c : in std_logic; - hbusreq_i_3 : in std_logic; - active : out std_logic; - rstn : in std_logic - ); - -end ahbmst; - -architecture DEF_ARCH of ahbmst is - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal retry_RNO, retry, N_603, \active\, active_2, grant, - \htrans[1]\, active_RNO, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - htrans(1) <= \htrans[1]\; - active <= \active\; - - \r.retry\ : DFN1 - port map(D => retry_RNO, CLK => lclk_c, Q => retry); - - \r.active\ : DFN1 - port map(D => active_RNO, CLK => lclk_c, Q => \active\); - - \r.active_RNO_1\ : NOR2B - port map(A => grant, B => \htrans[1]\, Y => active_2); - - \r.active_RNO\ : NOR2B - port map(A => rstn, B => N_603, Y => active_RNO); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.retry_RNI3F2G\ : NOR2 - port map(A => retry, B => hbusreq_i_3, Y => \htrans[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.retry_RNO\ : NOR3B - port map(A => retry, B => rstn, C => \active\, Y => - retry_RNO); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \r.grant\ : DFN1E1 - port map(D => hgrant(1), CLK => lclk_c, E => iosn(93), Q - => grant); - - \r.active_RNO_0\ : MX2 - port map(A => \active\, B => active_2, S => iosn_2(93), Y - => N_603); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbuart is - - port( haddr : out std_logic_vector(31 downto 0); - iosn_0 : in std_logic_vector(93 to 93); - hrdata_0_0 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_23 : in std_logic; - hrdata_25 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - pwdata_0 : in std_logic_vector(15 downto 0); - un1_dcom0 : out std_logic_vector(19 downto 12); - pwdata : in std_logic_vector(17 downto 16); - psel_1 : in std_logic_vector(7 to 7); - prdata_0 : out std_logic; - prdata_5 : out std_logic; - pwdata_1 : in std_logic_vector(4 to 4); - paddr : in std_logic_vector(3 downto 2); - hwdata : out std_logic_vector(31 downto 0); - iosn_2 : in std_logic_vector(93 to 93); - htrans : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(1 to 1); - iosn : in std_logic_vector(93 to 93); - hwrite : out std_logic; - N_264_0 : in std_logic; - N_262_0 : in std_logic; - N_78_0 : in std_logic; - N_78 : in std_logic; - un1_apbi_0 : in std_logic; - N_86 : out std_logic; - rdata60_1 : in std_logic; - N_85 : out std_logic; - dsutx_c : out std_logic; - N_6455_0 : in std_logic; - N_332 : out std_logic; - N_333 : out std_logic; - N_334 : out std_logic; - N_336 : out std_logic; - N_331 : out std_logic; - N_6455 : in std_logic; - N_127 : out std_logic; - N_330 : out std_logic; - N_769 : in std_logic; - un1_apbi_2 : in std_logic; - N_335 : out std_logic; - dsurx_c : in std_logic; - rstn : in std_logic; - hbusreq_i_3 : out std_logic; - lclk_c : in std_logic - ); - -end ahbuart; - -architecture DEF_ARCH of ahbuart is - - component VCC - port( Y : out std_logic - ); - end component; - - component dcom_uart - port( data : out std_logic_vector(7 downto 0); - hwdata : in std_logic_vector(31 downto 24) := (others => 'U'); - paddr : in std_logic_vector(3 downto 2) := (others => 'U'); - pwdata_1 : in std_logic_vector(4 to 4) := (others => 'U'); - prdata_5 : out std_logic; - prdata_0 : out std_logic; - state_i : in std_logic_vector(5 to 5) := (others => 'U'); - psel_1 : in std_logic_vector(7 to 7) := (others => 'U'); - pwdata : in std_logic_vector(17 downto 16) := (others => 'U'); - un1_dcom0_16 : out std_logic; - un1_dcom0_13 : out std_logic; - un1_dcom0_12 : out std_logic; - un1_dcom0_11 : out std_logic; - un1_dcom0_15 : out std_logic; - un1_dcom0_14 : out std_logic; - un1_dcom0_17 : out std_logic; - un1_dcom0_10 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - tcnt : out std_logic_vector(1 downto 0); - dsurx_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_335 : out std_logic; - un1_apbi_2 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - N_330 : out std_logic; - N_127 : out std_logic; - N_6455 : in std_logic := 'U'; - N_331 : out std_logic; - N_336 : out std_logic; - N_334 : out std_logic; - N_333 : out std_logic; - N_332 : out std_logic; - N_6455_0 : in std_logic := 'U'; - dsutx_c : out std_logic; - N_85 : out std_logic; - write : in std_logic := 'U'; - thempty : out std_logic; - N_321 : in std_logic := 'U'; - rdata60_1 : in std_logic := 'U'; - N_86 : out std_logic; - rstn : in std_logic := 'U'; - dready : out std_logic; - un1_apbi_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component dcom - port( tcnt : in std_logic_vector(1 downto 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_25 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hwdata : out std_logic_vector(31 downto 0); - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - data : in std_logic_vector(7 downto 0) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - state_i : out std_logic_vector(5 to 5); - haddr : out std_logic_vector(31 downto 0); - rstn : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - thempty : in std_logic := 'U'; - N_321 : out std_logic; - N_264_0 : in std_logic := 'U'; - active : in std_logic := 'U'; - hwrite : out std_logic; - dready : in std_logic := 'U'; - write : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component ahbmst - port( iosn : in std_logic_vector(93 to 93) := (others => 'U'); - hgrant : in std_logic_vector(1 to 1) := (others => 'U'); - htrans : out std_logic_vector(1 to 1); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - lclk_c : in std_logic := 'U'; - hbusreq_i_3 : in std_logic := 'U'; - active : out std_logic; - rstn : in std_logic := 'U' - ); - end component; - - signal active, \data[0]\, \data[1]\, \data[2]\, \data[3]\, - \data[4]\, \data[5]\, \data[6]\, \data[7]\, \state_i[5]\, - \tcnt[0]\, \tcnt[1]\, write, thempty, N_321, dready, - \hwdata[24]\, \hwdata[25]\, \hwdata[26]\, \hwdata[27]\, - \hwdata[28]\, \hwdata[29]\, \hwdata[30]\, \hwdata[31]\, - \hbusreq_i_3\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : dcom_uart - Use entity work.dcom_uart(DEF_ARCH); - for all : dcom - Use entity work.dcom(DEF_ARCH); - for all : ahbmst - Use entity work.ahbmst(DEF_ARCH); -begin - - hwdata(31) <= \hwdata[31]\; - hwdata(30) <= \hwdata[30]\; - hwdata(29) <= \hwdata[29]\; - hwdata(28) <= \hwdata[28]\; - hwdata(27) <= \hwdata[27]\; - hwdata(26) <= \hwdata[26]\; - hwdata(25) <= \hwdata[25]\; - hwdata(24) <= \hwdata[24]\; - hbusreq_i_3 <= \hbusreq_i_3\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - dcom_uart0 : dcom_uart - port map(data(7) => \data[7]\, data(6) => \data[6]\, - data(5) => \data[5]\, data(4) => \data[4]\, data(3) => - \data[3]\, data(2) => \data[2]\, data(1) => \data[1]\, - data(0) => \data[0]\, hwdata(31) => \hwdata[31]\, - hwdata(30) => \hwdata[30]\, hwdata(29) => \hwdata[29]\, - hwdata(28) => \hwdata[28]\, hwdata(27) => \hwdata[27]\, - hwdata(26) => \hwdata[26]\, hwdata(25) => \hwdata[25]\, - hwdata(24) => \hwdata[24]\, paddr(3) => paddr(3), - paddr(2) => paddr(2), pwdata_1(4) => pwdata_1(4), - prdata_5 => prdata_5, prdata_0 => prdata_0, state_i(5) - => \state_i[5]\, psel_1(7) => psel_1(7), pwdata(17) => - pwdata(17), pwdata(16) => pwdata(16), un1_dcom0_16 => - un1_dcom0(18), un1_dcom0_13 => un1_dcom0(15), - un1_dcom0_12 => un1_dcom0(14), un1_dcom0_11 => - un1_dcom0(13), un1_dcom0_15 => un1_dcom0(17), - un1_dcom0_14 => un1_dcom0(16), un1_dcom0_17 => - un1_dcom0(19), un1_dcom0_10 => un1_dcom0(12), - pwdata_0(15) => pwdata_0(15), pwdata_0(14) => - pwdata_0(14), pwdata_0(13) => pwdata_0(13), pwdata_0(12) - => pwdata_0(12), pwdata_0(11) => pwdata_0(11), - pwdata_0(10) => pwdata_0(10), pwdata_0(9) => pwdata_0(9), - pwdata_0(8) => pwdata_0(8), pwdata_0(7) => pwdata_0(7), - pwdata_0(6) => pwdata_0(6), pwdata_0(5) => pwdata_0(5), - pwdata_0(4) => pwdata_0(4), pwdata_0(3) => pwdata_0(3), - pwdata_0(2) => pwdata_0(2), pwdata_0(1) => pwdata_0(1), - pwdata_0(0) => pwdata_0(0), tcnt(1) => \tcnt[1]\, tcnt(0) - => \tcnt[0]\, dsurx_c => dsurx_c, lclk_c => lclk_c, - N_335 => N_335, un1_apbi_2 => un1_apbi_2, N_769 => N_769, - N_330 => N_330, N_127 => N_127, N_6455 => N_6455, N_331 - => N_331, N_336 => N_336, N_334 => N_334, N_333 => N_333, - N_332 => N_332, N_6455_0 => N_6455_0, dsutx_c => dsutx_c, - N_85 => N_85, write => write, thempty => thempty, N_321 - => N_321, rdata60_1 => rdata60_1, N_86 => N_86, rstn => - rstn, dready => dready, un1_apbi_0 => un1_apbi_0, N_78_0 - => N_78); - - GND_i_0 : GND - port map(Y => GND_0); - - dcom0 : dcom - port map(tcnt(1) => \tcnt[1]\, tcnt(0) => \tcnt[0]\, - iosn_2(93) => iosn_2(93), hrdata_0_d0 => hrdata_0_d0, - hrdata_1 => hrdata_1, hrdata_24 => hrdata_24, hrdata_26 - => hrdata_26, hrdata_25 => hrdata_25, hrdata_23 => - hrdata_23, hwdata(31) => \hwdata[31]\, hwdata(30) => - \hwdata[30]\, hwdata(29) => \hwdata[29]\, hwdata(28) => - \hwdata[28]\, hwdata(27) => \hwdata[27]\, hwdata(26) => - \hwdata[26]\, hwdata(25) => \hwdata[25]\, hwdata(24) => - \hwdata[24]\, hwdata(23) => hwdata(23), hwdata(22) => - hwdata(22), hwdata(21) => hwdata(21), hwdata(20) => - hwdata(20), hwdata(19) => hwdata(19), hwdata(18) => - hwdata(18), hwdata(17) => hwdata(17), hwdata(16) => - hwdata(16), hwdata(15) => hwdata(15), hwdata(14) => - hwdata(14), hwdata(13) => hwdata(13), hwdata(12) => - hwdata(12), hwdata(11) => hwdata(11), hwdata(10) => - hwdata(10), hwdata(9) => hwdata(9), hwdata(8) => - hwdata(8), hwdata(7) => hwdata(7), hwdata(6) => hwdata(6), - hwdata(5) => hwdata(5), hwdata(4) => hwdata(4), hwdata(3) - => hwdata(3), hwdata(2) => hwdata(2), hwdata(1) => - hwdata(1), hwdata(0) => hwdata(0), hrdata_0_1 => - hrdata_0_1, hrdata_0_2 => hrdata_0_2, hrdata_0_9 => - hrdata_0_9, hrdata_0_13 => hrdata_0_13, hrdata_0_14 => - hrdata_0_14, hrdata_0_15 => hrdata_0_15, hrdata_0_21 => - hrdata_0_21, hrdata_0_4 => hrdata_0_4, hrdata_0_12 => - hrdata_0_12, hrdata_0_11 => hrdata_0_11, hrdata_0_3 => - hrdata_0_3, hrdata_0_23 => hrdata_0_23, hrdata_0_17 => - hrdata_0_17, hrdata_0_7 => hrdata_0_7, hrdata_0_22 => - hrdata_0_22, hrdata_0_10 => hrdata_0_10, hrdata_0_18 => - hrdata_0_18, hrdata_0_16 => hrdata_0_16, hrdata_0_8 => - hrdata_0_8, hrdata_0_27 => hrdata_0_27, hrdata_0_26 => - hrdata_0_26, hrdata_0_24 => hrdata_0_24, hrdata_0_0 => - hrdata_0_0, data(7) => \data[7]\, data(6) => \data[6]\, - data(5) => \data[5]\, data(4) => \data[4]\, data(3) => - \data[3]\, data(2) => \data[2]\, data(1) => \data[1]\, - data(0) => \data[0]\, iosn_0(93) => iosn_0(93), - state_i(5) => \state_i[5]\, haddr(31) => haddr(31), - haddr(30) => haddr(30), haddr(29) => haddr(29), haddr(28) - => haddr(28), haddr(27) => haddr(27), haddr(26) => - haddr(26), haddr(25) => haddr(25), haddr(24) => haddr(24), - haddr(23) => haddr(23), haddr(22) => haddr(22), haddr(21) - => haddr(21), haddr(20) => haddr(20), haddr(19) => - haddr(19), haddr(18) => haddr(18), haddr(17) => haddr(17), - haddr(16) => haddr(16), haddr(15) => haddr(15), haddr(14) - => haddr(14), haddr(13) => haddr(13), haddr(12) => - haddr(12), haddr(11) => haddr(11), haddr(10) => haddr(10), - haddr(9) => haddr(9), haddr(8) => haddr(8), haddr(7) => - haddr(7), haddr(6) => haddr(6), haddr(5) => haddr(5), - haddr(4) => haddr(4), haddr(3) => haddr(3), haddr(2) => - haddr(2), haddr(1) => haddr(1), haddr(0) => haddr(0), - rstn => rstn, hbusreq_i_3 => \hbusreq_i_3\, N_78_0 => - N_78_0, N_262_0 => N_262_0, thempty => thempty, N_321 => - N_321, N_264_0 => N_264_0, active => active, hwrite => - hwrite, dready => dready, write => write, lclk_c => - lclk_c); - - ahbmst0 : ahbmst - port map(iosn(93) => iosn(93), hgrant(1) => hgrant(1), - htrans(1) => htrans(1), iosn_2(93) => iosn_2(93), lclk_c - => lclk_c, hbusreq_i_3 => \hbusreq_i_3\, active => - active, rstn => rstn); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbctrl is - - port( hmbsel : out std_logic_vector(0 to 0); - htrans_3 : in std_logic_vector(1 to 1); - htrans_2 : in std_logic_vector(1 to 1); - htrans_1 : in std_logic_vector(1 to 1); - htrans_0_0 : in std_logic; - bco_msb_1 : out std_logic_vector(1 to 1); - hresp_0 : out std_logic_vector(0 to 0); - nhmaster_1_i : out std_logic_vector(0 to 0); - hgrant_3 : out std_logic; - hgrant_1 : out std_logic; - hgrant_0 : out std_logic; - hsize_5 : in std_logic_vector(1 to 1); - hmbsel_1 : out std_logic_vector(0 to 0); - hburst_0 : in std_logic_vector(2 downto 0); - hsize_0 : in std_logic_vector(1 downto 0); - hsize : out std_logic_vector(1 downto 0); - haddr_3_4 : in std_logic; - haddr_3_5 : in std_logic; - haddr_3_0 : in std_logic; - haddr_3_3 : in std_logic; - haddr_3_8 : in std_logic; - haddr_3_6 : in std_logic; - haddr_3_1 : in std_logic; - haddr_3_7 : in std_logic; - hwdata_m_0_3 : out std_logic; - hwdata_m_0_0 : out std_logic; - hwdata_m_0_2 : out std_logic; - hwdata_m_8 : out std_logic; - hwdata_m_13 : out std_logic; - hwdata_m_5 : out std_logic; - hwdata_m_0_d0 : out std_logic; - hwdata_m_7 : out std_logic; - hwdata_2_15 : out std_logic; - hwdata_2_0 : in std_logic; - hwdata_2_9 : in std_logic; - hwdata_2_3 : in std_logic; - hwdata_2_14 : out std_logic; - hwdata_2_1 : in std_logic; - hwdata_2_28 : in std_logic; - hwdata_2_27 : in std_logic; - hwdata_2_25 : in std_logic; - hwdata_2_23 : in std_logic; - hwdata_2_13 : in std_logic; - hwdata_2_12 : in std_logic; - hwdata_2_11 : in std_logic; - hwdata_2_4 : in std_logic; - hwdata_2_16 : in std_logic; - hwdata_1 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - hwdata_0 : in std_logic_vector(31 downto 0); - hwdata : inout std_logic_vector(31 downto 0) := (others => 'Z'); - haddr_2 : inout std_logic_vector(30 downto 2) := (others => 'Z'); - haddr_1 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - haddr_0 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - hrdata_4_15 : in std_logic; - hrdata_4_13 : in std_logic; - hrdata_4_11 : in std_logic; - hrdata_4_27 : in std_logic; - hrdata_4_26 : in std_logic; - hrdata_4_4 : in std_logic; - hrdata_4_21 : in std_logic; - hrdata_4_1 : in std_logic; - hrdata_4_22 : in std_logic; - hrdata_4_23 : in std_logic; - hrdata_4_0 : in std_logic; - hrdata_4_14 : in std_logic; - hrdata_4_3 : in std_logic; - hrdata_4_2 : in std_logic; - hrdata_4_9 : in std_logic; - hrdata_4_12 : in std_logic; - hrdata_4_10 : in std_logic; - hrdata_4_7 : in std_logic; - hrdata_4_8 : in std_logic; - hrdata_4_16 : in std_logic; - hrdata_4_18 : in std_logic; - hrdata_4_17 : in std_logic; - hrdata_3_15 : in std_logic; - hrdata_3_13 : in std_logic; - hrdata_3_11 : in std_logic; - hrdata_3_28 : in std_logic; - hrdata_3_27 : in std_logic; - hrdata_3_26 : in std_logic; - hrdata_3_4 : in std_logic; - hrdata_3_1 : in std_logic; - hrdata_3_22 : in std_logic; - hrdata_3_23 : in std_logic; - hrdata_3_0 : in std_logic; - hrdata_3_24 : in std_logic; - hrdata_3_21 : in std_logic; - hrdata_3_14 : in std_logic; - hrdata_3_3 : in std_logic; - hrdata_3_2 : in std_logic; - hrdata_3_9 : in std_logic; - hrdata_3_12 : in std_logic; - hrdata_3_10 : in std_logic; - hrdata_3_7 : in std_logic; - hrdata_3_6 : in std_logic; - hrdata_3_8 : in std_logic; - hrdata_3_29 : in std_logic; - hrdata_3_16 : in std_logic; - hrdata_3_5 : in std_logic; - hrdata_3_30 : in std_logic; - hrdata_3_18 : in std_logic; - hrdata_3_17 : in std_logic; - hrdata_2_28 : in std_logic; - hrdata_2_25 : in std_logic; - hrdata_2_15 : out std_logic; - hrdata_2_11 : out std_logic; - hrdata_2_27 : out std_logic; - hrdata_2_26 : out std_logic; - hrdata_2_23 : in std_logic; - hrdata_2_22 : in std_logic; - hrdata_2_21 : in std_logic; - hrdata_2_13 : in std_logic; - hrdata_2_4 : in std_logic; - hrdata_2_1 : in std_logic; - hrdata_2_0 : in std_logic; - hrdata_2_24 : in std_logic; - hrdata_2_14 : in std_logic; - hrdata_2_3 : in std_logic; - hrdata_2_2 : in std_logic; - hrdata_2_31 : in std_logic; - hrdata_2_9 : out std_logic; - hrdata_2_19 : in std_logic; - hrdata_2_10 : out std_logic; - hrdata_2_7 : out std_logic; - hrdata_2_6 : in std_logic; - hrdata_2_29 : in std_logic; - hrdata_2_5 : in std_logic; - hrdata_2_30 : in std_logic; - hrdata_2_18 : in std_logic; - hrdata_2_16 : in std_logic; - hrdata_2_12 : in std_logic; - hrdata_2_8 : in std_logic; - hrdata_2_17 : in std_logic; - bco_msb_1_m : out std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : out std_logic_vector(1 to 1); - l1_0_m : out std_logic_vector(1 to 1); - nhmaster_1_iv_0 : out std_logic_vector(1 to 1); - hresp : in std_logic_vector(0 to 0); - htrans : out std_logic_vector(1 downto 0); - hrdata_1 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - data_0_5 : in std_logic; - data_0_21 : in std_logic; - data_0_16 : in std_logic; - data_0_2 : in std_logic; - data_0_0 : in std_logic; - data_8 : in std_logic; - data_24 : in std_logic; - data_0_d0 : in std_logic; - data_19 : in std_logic; - data_5 : in std_logic; - data_3 : in std_logic; - hrdata : inout std_logic_vector(31 downto 0) := (others => 'Z'); - size : in std_logic_vector(0 to 0); - nbo_5_0 : in std_logic_vector(1 downto 0); - address : in std_logic_vector(1 downto 0); - htrans_tz : in std_logic_vector(1 to 1); - haddr_1_d0 : out std_logic; - haddr_11 : out std_logic; - haddr_31 : in std_logic; - haddr_0_d0 : in std_logic; - haddr_4 : in std_logic; - haddr_15 : out std_logic; - haddr_14 : out std_logic; - haddr_19 : out std_logic; - haddr_18 : out std_logic; - haddr_21 : out std_logic; - haddr_20 : out std_logic; - haddr_23 : out std_logic; - haddr_22 : out std_logic; - haddr_27 : out std_logic; - haddr_26 : out std_logic; - haddr_29 : out std_logic; - haddr_28 : out std_logic; - haddr_12 : out std_logic; - haddr_13 : out std_logic; - haddr_16 : out std_logic; - haddr_17 : out std_logic; - haddr_24 : out std_logic; - haddr_25 : out std_logic; - haddr_30 : out std_logic; - hburst : out std_logic_vector(2 downto 0); - hsel_i : out std_logic_vector(0 to 0); - hrdata_1_0_1_0 : out std_logic; - hrdata_0 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - iosn_0 : out std_logic_vector(93 to 93); - iosn_1_8 : out std_logic; - iosn_1_0 : out std_logic; - iosn_2 : out std_logic_vector(93 to 93); - iosn_8 : out std_logic; - iosn_7 : out std_logic; - iosn_0_d0 : out std_logic; - hmaster_0_1 : out std_logic; - N_5054 : in std_logic; - htrans_0_sqmuxa_2 : in std_logic; - lb_0_sqmuxa_1 : in std_logic; - N_466 : in std_logic; - N_95_i_0 : in std_logic; - bo_5842_d : in std_logic; - rstn : in std_logic; - hbusreq_i_3_0 : in std_logic; - N_90_i_0 : in std_logic; - N_262 : out std_logic; - hwrite_1_m_0 : in std_logic; - werr_2_m_0 : in std_logic; - hwrite_1 : in std_logic; - hwrite_0 : in std_logic; - N_458 : in std_logic; - N_459 : in std_logic; - N_468 : in std_logic; - N_463 : in std_logic; - N_461 : in std_logic; - N_510 : in std_logic; - N_138 : in std_logic; - N_139 : in std_logic; - N_6377 : in std_logic; - N_103_i_0 : in std_logic; - brmw_i : in std_logic; - N_6550 : in std_logic; - N_264 : out std_logic; - N_467 : in std_logic; - N_457 : in std_logic; - N_462 : in std_logic; - un1_nhmaster_0_sqmuxa_1 : out std_logic; - un1_htrans_1_sqmuxa_0 : in std_logic; - un60_nbo : in std_logic; - arb_1 : out std_logic; - hbusreq : in std_logic; - hlock : in std_logic; - hready_1 : in std_logic; - hready_0 : in std_logic; - N_78 : out std_logic; - un315_ioen_NE : out std_logic; - un51_ioen_NE : out std_logic; - un59_nbo : in std_logic; - un91_nbo_i_0 : in std_logic; - hready : in std_logic; - bo_5842_d_0 : in std_logic; - un6_ioen_NE_0 : out std_logic; - brmw_1 : in std_logic; - hwrite : out std_logic; - hwrite_m_0_0 : out std_logic; - hbusreq_i_3 : in std_logic; - IdlePhase : in std_logic; - un1_dmain_6 : in std_logic; - Lock_RNIU86D : in std_logic; - N_546 : out std_logic; - N_264_0 : out std_logic; - N_262_0 : out std_logic; - N_78_0 : out std_logic; - lclk_c : in std_logic - ); - -end ahbctrl; - -architecture DEF_ARCH of ahbctrl is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal cfgsel_0, cfgsel_RNIQIMCBC, N_417_0, N_393, - \hmaster_0[0]\, N_5626_i, \hmaster_2[1]\, N_5627_i, - \hmaster_1[1]\, \hslave_1[0]\, \hslave_RNI6LMVPE[0]\, - \hslave_0[0]\, \hslave_0[2]\, \hslave_RNIQRGJS9[2]\, - \hmasterd_0[0]\, \hmasterd_1[1]\, \hmaster_0[1]\, - \iosn[93]\, \hmasterd_0[1]\, hready_1_iv_0_o2_0, N_660, - \hrdata_i_0_0[25]\, N_628, N_474, N_473, N_5325, N_6336, - N_663, \un34_hready[5]\, N_4876, \un34_hready[6]\, N_6339, - \hrdata_0_1[4]\, N_487, N_581, N_6343, \hrdata_0_0_1[8]\, - N_488, N_489, N_490, N_491, \hrdata_1_0[12]\, N_492, - \hrdata_1_0[13]\, \un34_hready[17]\, N_477, N_493, N_599, - N_6351, \hrdata_1_1[16]\, \un34_hready[20]\, N_4891, - N_6356, \hrdata_0_0[21]\, N_536, N_535, N_534, N_5348, - \un34_hready[27]\, N_478, N_465, N_525, N_475, N_572, - N_6353, \hrdata_0_0[18]\, hmasterlock_2_0, \iosn_0[93]\, - hmastlock, hlock_m, hlock_m_1, defslv_0_sqmuxa_1, - defslv_0_sqmuxa_0, un2_ioarea, \bco_msb_1_i_m_0[0]\, - arb_0_sqmuxa_1_a1_0, \vect[3]\, arb_1_sqmuxa_1_0, - un2_ioarea_17, un2_ioarea_11, un2_ioarea_10, - un2_ioarea_14, un2_ioarea_16, un2_ioarea_5, un2_ioarea_4, - un2_ioarea_13, \hsel_i[0]\, un2_ioarea_8, un2_ioarea_7, - un2_ioarea_3, un2_ioarea_1, un315_ioen_NE_1, - un315_ioen_NE_0, un51_ioen_NE_6, \haddr[29]\, \haddr[28]\, - un51_ioen_NE_1, un51_ioen_NE_0, un51_ioen_NE_10_5, - un51_ioen_NE_10_3, \haddr[25]\, \haddr[24]\, - un51_ioen_NE_10_4, un51_ioen_NE_10_1, \haddr[21]\, - \haddr[20]\, \haddr[26]\, \haddr[27]\, \haddr[22]\, - \haddr[23]\, \haddr[30]\, arb_0_sqmuxa_1_0, - arb_0_sqmuxa_1_a1_1, arb_0_sqmuxa_0, arb_0_sqmuxa_1_a2_0, - N_4617, \un34_haddr_1[5]\, \un34_haddr_1[4]\, - \un34_haddr_0[37]\, \hrdatas[13]\, N_657, N_594, - \hrdatas[12]\, \hrdata_1_1[5]\, N_587, N_585, N_588, - \hrdata_1_0_1[6]\, N_625, N_620, N_626, N_602, N_600, - N_603, N_664, N_576, N_583, N_584, \hrdata_1_0[28]\, - \hrdatas[28]\, N_580, N_460, N_622, N_623, - \hrdata_1_1[29]\, N_606, N_604, N_607, - \hrdatas_0_0_0[12]\, N_25, N_6470, hrdatas6, \hburst[1]\, - \hburst[2]\, hready_1_iv_0_a2_0_0, N_651_2, - hready_RNICLR2, \un1_acdm_3_0_a2_0[55]\, - \un1_acdm_3_0_a2_0[57]\, \un1_acdm_3_0_a3_0_0[71]_net_1\, - \hrdatam_1_0_a5_0[24]\, \haddr[7]\, - \hrdatam_1_0_a5_0[27]\, \haddr[6]\, hrdatas6_0_a5_1, - \haddr[9]\, \haddr[8]\, \haddr[10]\, N_6341, N_6364, - N_6340, N_4611, N_6465, \hrdatas_RNO[12]\, N_48, - \haddr_RNI726O[5]\, N_6469, N_6474, \hrdatam_1[28]\, - N_6467, N_94, N_6406, \hrdatas_RNO[15]\, N_43, N_50, - \hrdatas_RNO[14]\, N_6471, N_49, un271_ioen_NE, - arb_1_sqmuxa_1_i, N_4578_i, N_6404, N_569, N_417, N_476, - N_648, N_643, N_647, N_654, \hrdatam[13]\, cfga11, - \hrdatam[28]\, N_568, \htrans_0[1]\, defslv, N_403, - hready_2, hlock_m_0, \hmaster_3[1]\, \hmaster_3[0]\, - defslv_0_sqmuxa, un5_bnslave, \hmbsel_2[0]\, - \bco_msb_1_i_m[0]\, N_4579_i, \hrdata_1_0_1[1]\, N_547, - N_545, N_548, arb_0_sqmuxa_1, \hmaster_0_0_RNIFG08O[1]\, - \nhmaster_1[1]\, \nhmaster_1_iv_0[1]\, \l1_0_m[1]\, - \arb_1\, \hmaster_0_0_RNIFCVH1_0[1]\, N_5342, - \un34_hready[33]\, N_5355, cfgsel, N_4904, N_5274, N_5287, - N_6342, N_6345, N_6347, N_6352, N_6354, N_6365, - \hrdatas[30]\, \hrdatas[17]\, N_4622, N_4582, N_6286, - N_6494, N_6294, \haddr[18]\, N_4596, N_4604, N_4601, - N_4723, N_6523, N_6553, N_6506, N_6583, N_523, N_650, - \hrdatas[5]\, \hrdatas[16]\, \hrdatas[29]\, \hrdatas[8]\, - N_6551, N_469, N_479, N_481, N_483, N_4607, N_4709, - N_4599, N_4602, N_4603, N_4718, N_6586, N_4732, N_6600, - N_4734, N_6602, N_6344, N_6360, N_6366, N_4588, N_6481, - \haddr[3]\, \haddr[2]\, N_6476, N_44, N_24, \haddr_3[4]\, - \haddr_RNI726O[6]\, N_6461, N_6464, \hrdatam_1[13]\, - \hrdatam_1[14]\, \hrdatas_RNO[30]\, N_6477, - \hrdatas_RNO[28]\, N_6472, N_6466, N_6468, \haddr[5]\, - N_77, \hrdatas_RNO[1]\, \hrdatas_RNO[5]\, - \hrdatas_RNO[6]\, \hrdatas_RNO[13]\, \hrdatas_RNO[16]\, - \hrdatas_RNO[17]\, \hrdatas_RNO[29]\, \hrdatam_1[24]\, - \hrdatas_RNO[31]\, \hrdatas_RNO[24]\, N_4627, N_4587, - N_4621, N_4581, N_6500, N_6492, N_6495, N_6496, - \haddr[12]\, N_4590, N_6483, N_4600, N_6493, N_4626, - N_4586, N_4623, N_6485, N_6486, N_6490, N_6288, N_4583, - N_4598, \haddr[14]\, N_4592, \haddr[15]\, N_4593, - \haddr[19]\, N_4597, N_6577, N_4720, N_6520, N_6552, - N_6524, N_206, N_208, N_6531, N_6529, N_4711, N_6511, - N_4719, N_6519, N_4730, N_6530, N_4735, N_6535, N_6528, - N_6514, N_6305, N_6581, N_6593, N_6594, N_6595, N_4708, - \hmasterd[0]\, N_520, N_521, N_609, \hrdatas[31]\, - \hslave[1]\, N_637, N_639, N_640, N_645, \hmasterd[1]\, - N_494, N_480, N_486, N_6521, N_4721, N_6503, N_4610, - \hwrite\, N_470, N_6355, N_4580, N_4620, \hmaster[0]\, - N_6499, N_4606, N_6484, N_4591, \haddr[13]\, N_4612, - N_4652, N_4574, \haddr[5923]\, \iosn_1[101]\, - \un6_ioen_NE_0\, \un51_ioen_NE\, \hslave_3[2]\, - \hslave_RNO[1]\, \hslave_3[1]\, \un315_ioen_NE\, - \un34_haddr[0]\, N_4573, N_4618, N_6601, N_667, N_423, - N_5557, \iosn_1[93]\, \nhmaster_1_i[0]\, N_4608, N_6501, - N_4609, N_6502, N_5327, N_5328, N_5339, N_5349, N_5259, - N_5260, N_5271, N_5281, N_6335, N_6337, N_6338, N_6346, - N_6348, N_6349, N_6350, \hslave[0]\, N_6357, N_6358, - N_6359, N_6361, N_6362, N_6363, \hslave[2]\, \hrdatas[3]\, - N_4589, N_6482, N_4605, N_6498, N_4625, \hmaster[1]\, - N_4585, N_4624, N_6487, N_6488, N_4584, \haddr[16]\, - N_4594, \haddr[17]\, N_4595, N_6504, N_4710, N_6510, - N_5257, N_5280, N_6512, N_4716, N_6516, N_6573, N_6304, - N_6585, N_4707, \hrdatas[26]\, \hrdatas[1]\, N_556, N_454, - \hrdatas[9]\, \hrdatas[15]\, N_641, N_464, N_471, N_472, - \hrdatam[14]\, \hrdatas[14]\, \hrdatam[24]\, - \hrdatas[24]\, N_482, N_484, N_485, N_6522, N_4722, - hmasterlock_RNO, \htrans_RNO[1]\, N_5556, \htrans[1]\, - defslv_RNO, defslv_RNO_0, \un1_nhmaster_0_sqmuxa_1\, - \bco_msb_1_m[1]\, \bco_msb_1[1]\, \htrans[0]\, N_4576, - N_4616, \hburst[0]\, N_4613, N_4653, N_4577, - \hmbsel_1[0]\, \hslave_3[0]\, \iosn_2[93]\, N_4651, - N_4619, \haddr[11]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - bco_msb_1(1) <= \bco_msb_1[1]\; - nhmaster_1_i(0) <= \nhmaster_1_i[0]\; - hmbsel_1(0) <= \hmbsel_1[0]\; - bco_msb_1_m(1) <= \bco_msb_1_m[1]\; - hmaster_0_0_RNIFCVH1_0(1) <= \hmaster_0_0_RNIFCVH1_0[1]\; - l1_0_m(1) <= \l1_0_m[1]\; - nhmaster_1_iv_0(1) <= \nhmaster_1_iv_0[1]\; - htrans(1) <= \htrans[1]\; - htrans(0) <= \htrans[0]\; - haddr_11 <= \haddr[11]\; - haddr_15 <= \haddr[15]\; - haddr_14 <= \haddr[14]\; - haddr_19 <= \haddr[19]\; - haddr_18 <= \haddr[18]\; - haddr_21 <= \haddr[21]\; - haddr_20 <= \haddr[20]\; - haddr_23 <= \haddr[23]\; - haddr_22 <= \haddr[22]\; - haddr_27 <= \haddr[27]\; - haddr_26 <= \haddr[26]\; - haddr_29 <= \haddr[29]\; - haddr_28 <= \haddr[28]\; - haddr_12 <= \haddr[12]\; - haddr_13 <= \haddr[13]\; - haddr_16 <= \haddr[16]\; - haddr_17 <= \haddr[17]\; - haddr_24 <= \haddr[24]\; - haddr_25 <= \haddr[25]\; - haddr_30 <= \haddr[30]\; - hburst(2) <= \hburst[2]\; - hburst(1) <= \hburst[1]\; - hburst(0) <= \hburst[0]\; - hsel_i(0) <= \hsel_i[0]\; - hrdata_1_0_1_0 <= \hrdata_1_0_1[1]\; - iosn_0(93) <= \iosn_0[93]\; - iosn_1_8 <= \iosn_1[101]\; - iosn_1_0 <= \iosn_1[93]\; - iosn_2(93) <= \iosn_2[93]\; - iosn_0_d0 <= \iosn[93]\; - hmaster_0_1 <= \hmaster_0[1]\; - un1_nhmaster_0_sqmuxa_1 <= \un1_nhmaster_0_sqmuxa_1\; - arb_1 <= \arb_1\; - un315_ioen_NE <= \un315_ioen_NE\; - un51_ioen_NE <= \un51_ioen_NE\; - un6_ioen_NE_0 <= \un6_ioen_NE_0\; - hwrite <= \hwrite\; - - \r.hslave_1_RNIODTNH[0]\ : MX2C - port map(A => hrdata(25), B => hrdata_0(25), S => - \hslave_1[0]\, Y => N_6360); - - \r.cfga11\ : DFN1E1 - port map(D => \haddr[11]\, CLK => lclk_c, E => \iosn_2[93]\, - Q => cfga11); - - \r.hslave_0_0_RNI16LM6[2]\ : AO1C - port map(A => N_417_0, B => N_491, C => \hrdata_1_0[12]\, Y - => hrdata(12)); - - \r.hslave_RNIDBK5[0]\ : MX2C - port map(A => hrdata_3_15, B => hrdata_4_15, S => - \hslave[0]\, Y => N_485); - - \r.hmaster_0_0_RNI35KKE2_0[0]\ : NOR3A - port map(A => un51_ioen_NE_10_3, B => \haddr[25]\, C => - \haddr[24]\, Y => un51_ioen_NE_10_5); - - \r.hmasterd_0_RNIM4M41[0]\ : OR2B - port map(A => hwdata(7), B => N_6377, Y => hwdata_m_0_d0); - - \r.hslave_1_RNI9PVG[0]\ : NOR2B - port map(A => hrdata_4_1, B => N_664, Y => N_548); - - \r.hmaster_2_RNIURLLM[1]\ : AO1 - port map(A => werr_2_m_0, B => hwrite_1_m_0, C => - \hmaster_2[1]\, Y => N_4610); - - \r.hmaster_0_0_RNITCAKK[1]\ : OR2A - port map(A => haddr_2(4), B => \hmaster_0[1]\, Y => N_4582); - - \r.hmaster_2_RNIPK71O[1]\ : AOI1 - port map(A => hsize_5(1), B => un91_nbo_i_0, C => - \hmaster_2[1]\, Y => N_4612); - - \r.hmasterlock_RNO_0\ : NOR3C - port map(A => \hmaster_3[1]\, B => hlock_m_1, C => - \hmaster_3[0]\, Y => hlock_m_0); - - \r.hslave_RNINRK5[0]\ : MX2C - port map(A => hrdata_2_28, B => hrdata_3_28, S => - \hslave[0]\, Y => N_472); - - \r.hmasterd_RNIOTSF1[0]\ : MX2 - port map(A => N_4721, B => N_6521, S => \hmasterd[0]\, Y - => hwdata_2_14); - - \r.hmaster_RNICBB7[1]\ : MX2 - port map(A => haddr_0(6), B => haddr_1(6), S => - \hmaster[1]\, Y => N_4624); - - \r.hmasterd_0_RNI9F2T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6514, C => N_6406, Y - => hwdata(10)); - - \r.haddr_RNI9EDF[2]\ : OR2A - port map(A => N_6466, B => \haddr[2]\, Y => N_6467); - - \r.hmasterd_0_RNII4GI[1]\ : OR3A - port map(A => N_462, B => \hmasterd_0[0]\, C => - \hmasterd_0[1]\, Y => N_523); - - \r.hslave_0_0_RNIE86V7[2]\ : OR2B - port map(A => N_5355, B => N_393, Y => \un34_hready[33]\); - - \r.hmaster_0_0_RNIFG08O[1]\ : OR3B - port map(A => un60_nbo, B => un1_htrans_1_sqmuxa_0, C => - arb_0_sqmuxa_1_a1_1, Y => \hmaster_0_0_RNIFG08O[1]\); - - \r.hrdatas_RNO[16]\ : AO1C - port map(A => N_6470, B => N_25, C => N_6477, Y => - \hrdatas_RNO[16]\); - - \r.hmaster_RNITFB6[1]\ : OR2B - port map(A => \hmaster[1]\, B => hburst_0(0), Y => N_4653); - - \r.cfgsel_0_0_RNI7JIUF\ : NOR3A - port map(A => N_393, B => cfgsel_0, C => N_5325, Y => - hrdata(0)); - - \r.hslave_1_RNIL1PA[0]\ : MX2C - port map(A => hrdata_3_12, B => hrdata_4_12, S => - \hslave_1[0]\, Y => N_483); - - \r.hmaster_2_RNIH90AJ[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(19), Y => N_4597); - - \r.haddr_RNIBTVL[3]\ : OR3C - port map(A => N_6468, B => N_6472, C => N_6466, Y => N_77); - - \r.hmaster_RNII9N7IO[0]\ : OR2A - port map(A => \nhmaster_1[1]\, B => \nhmaster_1_i[0]\, Y - => hgrant_3); - - \r.hmasterd_RNI97GN[0]\ : MX2C - port map(A => N_4708, B => N_6305, S => \hmasterd[0]\, Y - => hwdata_1(4)); - - \r.hmaster_1_RNIAJSB[1]\ : MX2 - port map(A => haddr_1(25), B => haddr_2(25), S => - \hmaster_1[1]\, Y => N_6496); - - \r.hslave_1_RNIHPOA[0]\ : MX2C - port map(A => hrdata_3_10, B => hrdata_4_10, S => - \hslave_1[0]\, Y => N_481); - - \r.hrdatam_RNI2S59[27]\ : OR3B - port map(A => \hrdatam[28]\, B => cfgsel_0, C => cfga11, Y - => N_572); - - \r.hslave_RNI2OB2D[0]\ : MX2C - port map(A => hrdata_0(28), B => hrdata_1(28), S => - \hslave[0]\, Y => N_6363); - - \r.hslave_RNICPAUPE[0]\ : MX2C - port map(A => \hslave[0]\, B => un5_bnslave, S => - \iosn_2[93]\, Y => \hslave_3[0]\); - - \r.hmaster_RNIN8M4R1[0]\ : OR2A - port map(A => \iosn_1[101]\, B => \hsel_i[0]\, Y => iosn_8); - - \r.hslave_RNITTOV6_0[0]\ : OR3C - port map(A => N_536, B => N_535, C => N_534, Y => - hrdata_0(22)); - - \r.hrdatas_RNO[24]\ : AO1D - port map(A => \haddr_3[4]\, B => N_6470, C => - \hrdatam_1[14]\, Y => \hrdatas_RNO[24]\); - - \r.hmaster_0_0_RNISA19[1]\ : MX2 - port map(A => haddr_0(26), B => haddr_1(26), S => - \hmaster_0[1]\, Y => N_6294); - - \r.hmasterd_0_RNILVI7[1]\ : MX2 - port map(A => hwdata_0(2), B => hwdata_1(2), S => - \hmasterd_0[1]\, Y => N_6506); - - \r.hmaster_RNI7U1OJ[1]\ : OR2A - port map(A => N_5054, B => \hmaster[1]\, Y => N_4613); - - \r.hmaster_0_0_RNIS83UE2_1[0]\ : NOR2B - port map(A => un315_ioen_NE_0, B => un51_ioen_NE_6, Y => - un315_ioen_NE_1); - - \r.hslave_RNIR7QVD[0]\ : MX2 - port map(A => hrdata_2_21, B => hrdata_3_21, S => - \hslave[0]\, Y => N_6356); - - \r.hrdatas_RNIUTR6[17]\ : OR2B - port map(A => \hrdatas[17]\, B => cfga11, Y => N_4891); - - \r.hmasterd_1_RNIATM9[1]\ : MX2 - port map(A => hwdata(22), B => hwdata_0(22), S => - \hmasterd_1[1]\, Y => N_6594); - - \r.defslv_RNO_0\ : NOR2A - port map(A => defslv, B => \iosn_1[93]\, Y => defslv_RNO_0); - - \r.hmaster_1_RNIGKEFK[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_3_1, Y => N_4581); - - \r.hmaster_RNIEU9A[1]\ : MX2 - port map(A => haddr_0(16), B => haddr_1(16), S => - \hmaster[1]\, Y => N_6487); - - \r.hmasterd_RNIUK4E[1]\ : MX2 - port map(A => hwdata_1(6), B => hwdata_2_3, S => - \hmasterd[1]\, Y => N_6510); - - \r.hslave_0_0_RNIG0NP7[2]\ : AO1A - port map(A => N_417_0, B => N_488, C => N_581, Y => - hrdata_0(9)); - - \r.hmasterd_1_RNISRTF[1]\ : OR3A - port map(A => N_461, B => \hmasterd[0]\, C => - \hmasterd_1[1]\, Y => N_521); - - \r.hmasterd_0_RNIDUUG[0]\ : MX2 - port map(A => N_4711, B => N_6511, S => \hmasterd_0[0]\, Y - => hwdata(7)); - - \r.hmaster_RNIKUG5PE[1]\ : MX2 - port map(A => \hmaster[1]\, B => \nhmaster_1[1]\, S => - \iosn_1[93]\, Y => \hmaster_3[1]\); - - \r.hmaster_RNII9N7IO_0[0]\ : OR2A - port map(A => \nhmaster_1_i[0]\, B => \nhmaster_1[1]\, Y - => hgrant_0); - - \r.hmaster_0_0_RNI9CME71_0[0]\ : NOR2A - port map(A => \haddr[29]\, B => \haddr[28]\, Y => - un315_ioen_NE_0); - - \r.hmaster_0_0_RNI5T47J[1]\ : OR2A - port map(A => haddr_0(29), B => \hmaster_0[1]\, Y => N_4607); - - \r.haddr[2]\ : DFN1E1 - port map(D => haddr_1(2), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[2]\); - - \r.hmaster_0_0_RNIBIVC71_0[0]\ : NOR2A - port map(A => \haddr[29]\, B => \haddr[30]\, Y => - \iosn_1[101]\); - - \r.hslave_0_0_RNI1PNSA[2]\ : NOR2A - port map(A => N_393, B => N_5328, Y => \un34_hready[6]\); - - \r.hmaster_1_RNI8BSB[1]\ : MX2 - port map(A => haddr_1(24), B => haddr_2(24), S => - \hmaster_1[1]\, Y => N_6495); - - \r.hmasterlock_RNO_2\ : NOR3B - port map(A => Lock_RNIU86D, B => un1_dmain_6, C => - IdlePhase, Y => hlock_m_1); - - \r.hmaster_1_RNIL0U9J[1]\ : OR2A - port map(A => haddr_1(10), B => \hmaster_1[1]\, Y => N_4588); - - \r.hmaster_1_RNIIJTB[1]\ : MX2C - port map(A => haddr_1(29), B => haddr_2(29), S => - \hmaster_1[1]\, Y => N_6500); - - \r.haddr[3]\ : DFN1E1 - port map(D => haddr_2(3), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[3]\); - - \r.hmasterd_0_RNI59M9[1]\ : MX2 - port map(A => hwdata(11), B => hwdata_0(11), S => - \hmasterd_0[1]\, Y => N_6583); - - \r.hslave_RNI31DPH[1]\ : OR2B - port map(A => \hslave[1]\, B => N_6360, Y => N_628); - - \r.hslave_0_0_RNI0VK6[0]\ : OR2A - port map(A => \hslave_0[0]\, B => hready, Y => - hready_1_iv_0_a2_0_0); - - \r.hslave_1_RNIBSG4A[0]\ : MX2 - port map(A => hrdata_3_3, B => hrdata_4_3, S => - \hslave_1[0]\, Y => N_6338); - - \r.hslave_0_0_RNIRT9A[0]\ : OR3A - port map(A => \hslave_0[0]\, B => hready_1, C => N_654, Y - => N_647); - - \r.hmaster_2_RNIR4U9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(20), Y => N_4598); - - \r.hmasterd_RNIJS6O[1]\ : NOR2 - port map(A => hwdata_1(18), B => \hmasterd[1]\, Y => N_4722); - - \r.hmaster_0_0_RNI9CME71_1[0]\ : NOR2 - port map(A => \haddr[29]\, B => \haddr[28]\, Y => - un51_ioen_NE_0); - - \r.hmaster_0_0_RNIKN26[1]\ : MX2C - port map(A => haddr_4, B => haddr_0(4), S => \hmaster_0[1]\, - Y => N_4622); - - \r.hmasterd_RNIMU0F[0]\ : OR2B - port map(A => \hmasterd[0]\, B => N_6581, Y => N_520); - - \r.hmaster_0_0_RNIEO4OJ[0]\ : MX2 - port map(A => N_4597, B => N_6490, S => \hmaster_0[0]\, Y - => \haddr[19]\); - - \r.cfgsel_0_0_RNIQSMT7\ : MX2C - port map(A => \un34_hready[20]\, B => N_4891, S => cfgsel_0, - Y => hrdata_0(17)); - - \r.haddr_RNI726O_1[5]\ : NOR2 - port map(A => N_6471, B => N_25, Y => \hrdatam_1[14]\); - - \r.hmaster_RNII9N7IO_1[0]\ : NOR2 - port map(A => \nhmaster_1_i[0]\, B => \nhmaster_1[1]\, Y - => hgrant_1); - - \r.hmaster_RNINF2RR9[0]\ : NOR2B - port map(A => rstn, B => \hmaster_3[0]\, Y => N_5626_i); - - \r.hmasterd_0_RNIIBLH[1]\ : OR2A - port map(A => hwdata_0(28), B => \hmasterd_0[1]\, Y => - N_4732); - - \r.hmaster_0_0_RNI76CA71_0[0]\ : NOR2 - port map(A => \haddr[22]\, B => \haddr[23]\, Y => - un51_ioen_NE_10_1); - - \r.hmaster_0_0_RNIUVJSK[0]\ : MX2C - port map(A => N_4582, B => N_4622, S => \hmaster_0[0]\, Y - => haddr_1(4)); - - \r.hmasterd_0_RNICSUF1[0]\ : NOR2A - port map(A => hwdata(14), B => N_6550, Y => hwdata_m_7); - - \r.hmaster_0_0_RNIFCVH1[1]\ : OA1C - port map(A => arb_0_sqmuxa_1_a1_0, B => hbusreq_i_3, C => - \vect[3]\, Y => \bco_msb_1_i_m_0[0]\); - - \r.hslave_0_0_RNIR58U7[0]\ : AO1B - port map(A => N_6364, B => N_663, C => \hrdata_1_1[29]\, Y - => hrdata(29)); - - \r.hmaster_0_0_RNI9EIMC7[0]\ : NOR3C - port map(A => un2_ioarea_11, B => un2_ioarea_10, C => - un2_ioarea_14, Y => un2_ioarea_17); - - \r.hmaster_0_0_RNIAA9AC7[0]\ : OR3C - port map(A => un51_ioen_NE_10_4, B => un51_ioen_NE_10_5, C - => un51_ioen_NE_1, Y => \un51_ioen_NE\); - - \r.hrdatas[28]\ : DFN1 - port map(D => \hrdatas_RNO[28]\, CLK => lclk_c, Q => - \hrdatas[28]\); - - \r.haddr_RNIT9C4_2[5]\ : NOR2 - port map(A => \haddr[5]\, B => \haddr_3[4]\, Y => N_6461); - - \r.hmaster_RNIESC8J[1]\ : NOR2 - port map(A => \hmaster[1]\, B => haddr_2(17), Y => N_4595); - - \r.cfgsel_0_0_RNI0VOMI\ : MX2C - port map(A => \un34_hready[17]\, B => N_477, S => cfgsel_0, - Y => hrdata_0(14)); - - \un1_acdm_3_0_o3_0_m2[60]\ : MX2 - port map(A => data_8, B => data_0_5, S => bo_5842_d, Y => - N_454); - - \r.hslave_RNI6LMVPE[0]\ : NOR2A - port map(A => rstn, B => \hslave_3[0]\, Y => - \hslave_RNI6LMVPE[0]\); - - \r.hrdatas_RNO[30]\ : NOR2A - port map(A => \haddr[3]\, B => N_6477, Y => - \hrdatas_RNO[30]\); - - \r.hrdatas_RNO_0[12]\ : OA1C - port map(A => N_25, B => N_6470, C => hrdatas6, Y => - \hrdatas_0_0_0[12]\); - - \r.hslave_1_RNINP8PK[0]\ : MX2C - port map(A => N_103_i_0, B => hrdata(31), S => - \hslave_1[0]\, Y => N_6366); - - \r.hslave_RNI005IS9[2]\ : MX2C - port map(A => \hslave[2]\, B => \hmbsel_2[0]\, S => - \iosn_2[93]\, Y => \hslave_3[2]\); - - \r.hrdatas_RNO[13]\ : AO1C - port map(A => N_6467, B => N_24, C => N_77, Y => - \hrdatas_RNO[13]\); - - \r.hslave_1_RNIP9PA[0]\ : MX2C - port map(A => hrdata_1(14), B => hrdata_2_14, S => - \hslave_1[0]\, Y => N_5271); - - \r.hmaster_RNI71U7O[0]\ : MX2C - port map(A => N_4579_i, B => N_4619, S => \hmaster[0]\, Y - => haddr_1_d0); - - \r.hslave_0_0_RNID26R[0]\ : AOI1 - port map(A => N_648, B => N_647, C => N_403, Y => N_660); - - \r.hmasterd_RNIIRI32[0]\ : OR2A - port map(A => hwdata(12), B => N_6550, Y => hwdata_m_5); - - \r.hslave_1_RNIS6UA[0]\ : OR2B - port map(A => hrdata_4_22, B => N_664, Y => N_536); - - \r.hmasterd_RNIJU8G[1]\ : MX2 - port map(A => hwdata_0(29), B => hwdata_1(29), S => - \hmasterd[1]\, Y => N_6601); - - \r.hmasterd_RNI0NJV[1]\ : OR3A - port map(A => N_454, B => \hmasterd[0]\, C => \hmasterd[1]\, - Y => N_556); - - \r.hmaster_RNIUQ7LK[0]\ : MX2 - port map(A => N_4580, B => N_4620, S => \hmaster[0]\, Y => - haddr_1(2)); - - \r.hrdatam_RNIQUFD[14]\ : MX2C - port map(A => \hrdatam[14]\, B => \hrdatas[14]\, S => - cfga11, Y => N_477); - - \r.hmaster_0_0_RNIBIOHJ[0]\ : MX2 - port map(A => N_4586, B => N_4626, S => \hmaster_0[0]\, Y - => haddr_2(8)); - - \r.hmaster_0_0_RNI74CUN[1]\ : OR3B - port map(A => \un34_haddr_0[37]\, B => un91_nbo_i_0, C => - un59_nbo, Y => N_4611); - - \r.hrdatas_RNISN57[29]\ : OR2B - port map(A => \hrdatas[29]\, B => N_657, Y => N_604); - - \r.hmaster_RNI5TS1K[0]\ : MX2C - port map(A => N_4613, B => N_4653, S => \hmaster[0]\, Y => - \hburst[0]\); - - \r.cfgsel_RNICGMR7\ : MX2C - port map(A => \un34_hready[20]\, B => N_4891, S => cfgsel, - Y => hrdata(17)); - - \r.hmasterd_1_RNIGLN9[1]\ : MX2C - port map(A => hwdata_1(28), B => hwdata_2_25, S => - \hmasterd_1[1]\, Y => N_6600); - - \r.hslave_RNI7A9PF[2]\ : MX2C - port map(A => N_5257, B => N_6335, S => \hslave[2]\, Y => - N_5325); - - \r.hmaster_1_RNI4RRB[1]\ : MX2 - port map(A => haddr_1(22), B => haddr_2(22), S => - \hmaster_1[1]\, Y => N_6493); - - \r.hmaster_0_0_RNIKKIKOE[0]\ : OR2B - port map(A => \un315_ioen_NE\, B => \un51_ioen_NE\, Y => - un5_bnslave); - - \r.hmasterd_RNI1C4H[0]\ : OR2B - port map(A => \hmasterd[0]\, B => N_6594, Y => N_640); - - \r.hmaster_2_RNI59V9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(15), Y => N_4593); - - \r.hmaster_0_0_RNIS5OHJ[0]\ : MX2 - port map(A => N_4583, B => N_4623, S => \hmaster_0[0]\, Y - => haddr_2(5)); - - \r.hmaster[1]\ : DFN1 - port map(D => N_5627_i, CLK => lclk_c, Q => \hmaster[1]\); - - \r.cfgsel_0_0_RNIBQIPG_0\ : NOR3A - port map(A => N_393, B => cfgsel_0, C => N_5348, Y => - hrdata_0(23)); - - \r.hslave_RNI6U06[0]\ : NOR3B - port map(A => \hslave[0]\, B => hrdata_3_1, C => N_650, Y - => N_547); - - \r.hmaster_1_RNIUARB[1]\ : MX2C - port map(A => haddr_2(10), B => haddr_3_8, S => - \hmaster_1[1]\, Y => N_6481); - - \r.hmasterd_0_RNI1FO21[0]\ : MX2 - port map(A => N_6552, B => N_6524, S => \hmasterd_0[0]\, Y - => hwdata(20)); - - \r.hmasterd_RNIRP0F[1]\ : OR2A - port map(A => hwdata_2_0, B => \hmasterd[1]\, Y => N_4707); - - \r.hslave_0_0_RNIH9OU[0]\ : NOR3C - port map(A => N_602, B => N_600, C => N_603, Y => - \hrdata_1_1[16]\); - - \r.hmaster_2_RNI3HU9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_31, Y => N_4609); - - \r.hmasterd_0_RNI467S[0]\ : MX2C - port map(A => N_4735, B => N_6535, S => \hmasterd_0[0]\, Y - => hwdata(31)); - - \un1_acdm_3_0_a3_0_0[71]\ : MX2 - port map(A => data_19, B => data_0_16, S => bo_5842_d_0, Y - => \un1_acdm_3_0_a3_0_0[71]_net_1\); - - \r.hmaster_RNIJSCF71[0]\ : OR2A - port map(A => \haddr[30]\, B => \hsel_i[0]\, Y => iosn_7); - - \r.hslave_RNIQRGJS9[2]\ : NOR2A - port map(A => rstn, B => \hslave_3[2]\, Y => - \hslave_RNIQRGJS9[2]\); - - \r.hslave_1_RNI93839[0]\ : MX2 - port map(A => hrdata_1(4), B => hrdata_2_4, S => - \hslave_1[0]\, Y => N_6339); - - \r.hmasterd_RNI746O[1]\ : NOR2 - port map(A => hwdata_0(12), B => \hmasterd[1]\, Y => N_4716); - - \r.hmaster_RNICG3AO[0]\ : MX2 - port map(A => N_4612, B => N_4652, S => \hmaster[0]\, Y => - hsize(1)); - - \r.hmaster_0_0_RNIBIVC71[0]\ : OR2 - port map(A => \haddr[29]\, B => \haddr[30]\, Y => - \un6_ioen_NE_0\); - - \r.hmaster_RNI28RFJ[0]\ : MX2 - port map(A => N_4585, B => N_4625, S => \hmaster[0]\, Y => - haddr_2(7)); - - \r.hrdatas_RNIB5JV[5]\ : NOR3C - port map(A => N_587, B => N_585, C => N_588, Y => - \hrdata_1_1[5]\); - - \r.hmaster_RNIEQS6PE[1]\ : NOR2B - port map(A => rstn, B => \hmaster_3[1]\, Y => N_5627_i); - - \r.hrdatas_RNO[1]\ : OR2B - port map(A => N_44, B => N_43, Y => \hrdatas_RNO[1]\); - - \r.hmasterd_0_RNI3M7S[0]\ : MX2 - port map(A => N_4718, B => N_6586, S => \hmasterd_0[0]\, Y - => hwdata(14)); - - \r.hmaster_0_0_RNI473TN[1]\ : OR3C - port map(A => nbo_5_0(0), B => \un34_haddr_1[5]\, C => - un91_nbo_i_0, Y => N_4579_i); - - \r.hmaster_RNIJSCF71_0[0]\ : NOR2A - port map(A => \hsel_i[0]\, B => \haddr[30]\, Y => - un51_ioen_NE_6); - - \r.hmasterd_RNIUL6A1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6593, C => N_637, Y => - hwdata_1(21)); - - \r.hmasterd_0[0]\ : DFN1E1 - port map(D => \hmaster_0[0]\, CLK => lclk_c, E => - \iosn[93]\, Q => \hmasterd_0[0]\); - - \r.haddr[10]\ : DFN1E1 - port map(D => haddr_0(10), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[10]\); - - \r.hmaster_0_0_RNI6J2P[0]\ : OA1 - port map(A => \hburst[1]\, B => \hburst[2]\, C => - \hmaster_0[0]\, Y => arb_0_sqmuxa_1_a2_0); - - \r.haddr[8]\ : DFN1E1 - port map(D => haddr_2(8), CLK => lclk_c, E => \iosn[93]\, Q - => \haddr[8]\); - - \r.hmaster_0_0_RNIMI09[1]\ : MX2 - port map(A => haddr_0(23), B => haddr_1(23), S => - \hmaster_0[1]\, Y => N_6494); - - \r.hslave_RNIFHUD8[2]\ : OAI1 - port map(A => N_417, B => N_475, C => N_572, Y => - hrdata_2_27); - - \r.hslave_0_0_RNIAEOPA[2]\ : MX2C - port map(A => N_5260, B => N_6338, S => \hslave_0[2]\, Y - => N_5328); - - \r.hmasterlock_RNITLJU\ : NOR3 - port map(A => \hburst[1]\, B => \hburst[2]\, C => hmastlock, - Y => arb_1_sqmuxa_1_0); - - \r.haddr[9]\ : DFN1E1 - port map(D => haddr_2(9), CLK => lclk_c, E => \iosn[93]\, Q - => \haddr[9]\); - - \r.haddr_RNI8TVL[4]\ : NOR2 - port map(A => \haddr_3[4]\, B => N_6471, Y => - \hrdatam_1[13]\); - - \r.haddr_RNIT9C4_0[5]\ : OR2A - port map(A => \haddr[5]\, B => \haddr_3[4]\, Y => N_25); - - \r.hslave_1_RNI3JVE[0]\ : MX2 - port map(A => hrdata_1(2), B => hrdata_2_2, S => - \hslave_1[0]\, Y => N_5259); - - \r.hmasterd_0_RNIUOGI[1]\ : OR3A - port map(A => N_138, B => \hmasterd_0[0]\, C => - \hmasterd_0[1]\, Y => N_208); - - \r.hmaster_0_0_RNI3DHK19[1]\ : OA1A - port map(A => \hmaster_0[1]\, B => - \un1_nhmaster_0_sqmuxa_1\, C => \l1_0_m[1]\, Y => - \nhmaster_1_iv_0[1]\); - - \r.hrdatam_RNO_0[24]\ : OR2 - port map(A => \haddr[7]\, B => N_25, Y => - \hrdatam_1_0_a5_0[24]\); - - \r.hmasterd_0_RNIGOE8[1]\ : NOR2 - port map(A => \hmasterd_0[1]\, B => N_457, Y => N_6551); - - \r.hslave_RNI1KG3G[0]\ : MX2C - port map(A => hrdata(15), B => hrdata_1(15), S => - \hslave[0]\, Y => N_6350); - - \r.htrans_RNO_0[1]\ : MX2 - port map(A => \htrans_0[1]\, B => \htrans[1]\, S => - \iosn_1[93]\, Y => N_5556); - - \r.hslave_RNI93K5[0]\ : MX2 - port map(A => hrdata_3_13, B => hrdata_4_13, S => - \hslave[0]\, Y => N_484); - - \r.hmaster_RNIBKC8J[1]\ : NOR2 - port map(A => \hmaster[1]\, B => haddr_2(16), Y => N_4594); - - \r.hrdatas[29]\ : DFN1 - port map(D => \hrdatas_RNO[29]\, CLK => lclk_c, Q => - \hrdatas[29]\); - - \r.hrdatas_RNIH7AG[13]\ : AO1B - port map(A => \hrdatas[13]\, B => N_657, C => N_594, Y => - \hrdata_1_0[13]\); - - \r.htrans_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5556, Y => \htrans_RNO[1]\); - - \r.htrans[1]\ : DFN1 - port map(D => \htrans_RNO[1]\, CLK => lclk_c, Q => - \htrans_0[1]\); - - \r.hslave_RNID2VT[2]\ : AO1C - port map(A => N_417, B => N_465, C => N_525, Y => - hrdata_2_26); - - \r.hmaster_0_0_RNIQN2OJ[0]\ : MX2 - port map(A => N_4593, B => N_6486, S => \hmaster_0[0]\, Y - => \haddr[15]\); - - \r.hrdatas_RNO_0[1]\ : OR3B - port map(A => N_24, B => \haddr_3[4]\, C => N_6467, Y => - N_44); - - \r.hrdatam_RNO[24]\ : AO1D - port map(A => \hrdatam_1_0_a5_0[24]\, B => N_6467, C => - \hrdatam_1[13]\, Y => \hrdatam_1[24]\); - - \r.haddr_RNI1AC4_0[6]\ : NOR2B - port map(A => \haddr[7]\, B => \haddr[6]\, Y => N_6469); - - \bco_msb_1_0_a2[1]\ : OR2A - port map(A => hbusreq_i_3, B => hbusreq, Y => - \bco_msb_1[1]\); - - GND_i : GND - port map(Y => \GND\); - - \r.hslave_RNI5RJ5[0]\ : MX2C - port map(A => hrdata_3_11, B => hrdata_4_11, S => - \hslave[0]\, Y => N_482); - - \r.hslave_0_0_RNISAP49[2]\ : MX2C - port map(A => N_479, B => N_6342, S => \hslave_0[2]\, Y => - N_487); - - \r.hmaster_2_RNITRDB[1]\ : NOR2B - port map(A => hburst_0(2), B => \haddr[5923]\, Y => - \hburst[2]\); - - \r.hmaster_RNIUDMNJ[0]\ : MX2C - port map(A => N_4589, B => N_6482, S => \hmaster[0]\, Y => - \haddr[11]\); - - \r.haddr_RNIG41B[8]\ : OR3 - port map(A => \haddr[9]\, B => \haddr[8]\, C => \haddr[10]\, - Y => N_6465); - - \r.hrdatam_RNO[27]\ : NOR3 - port map(A => N_25, B => \hrdatam_1_0_a5_0[27]\, C => - N_6467, Y => \hrdatam_1[28]\); - - \r.haddr_RNID97D[3]\ : NOR2 - port map(A => \haddr[3]\, B => N_6465, Y => N_6466); - - \r.hrdatas_RNO[5]\ : OR2 - port map(A => \haddr_RNI726O[5]\, B => \haddr_RNI726O[6]\, - Y => \hrdatas_RNO[5]\); - - \r.haddr_RNI1AC4[6]\ : XNOR2 - port map(A => \haddr[6]\, B => \haddr[7]\, Y => N_24); - - \r.hslave_0_0_RNIL8HF8[0]\ : MX2C - port map(A => hrdata(7), B => hrdata_1(7), S => - \hslave_0[0]\, Y => N_6342); - - \r.cfgsel_0_0_RNIIVH2B\ : MX2 - port map(A => \un34_hready[6]\, B => N_4876, S => cfgsel_0, - Y => hrdata_0(3)); - - \r.hmaster_0_0_RNIBR6LJ[0]\ : MX2 - port map(A => N_4602, B => N_6495, S => \hmaster_0[0]\, Y - => \haddr[24]\); - - \r.hslave_0_0_RNIAPN1D[0]\ : AO1B - port map(A => N_6341, B => N_663, C => \hrdata_1_0_1[6]\, Y - => hrdata(6)); - - \r.hmasterd_0_RNIRPTG[0]\ : MX2 - port map(A => N_6553, B => N_6506, S => \hmasterd_0[0]\, Y - => hwdata(2)); - - \r.hmasterd_1_RNI7LM9[1]\ : MX2 - port map(A => hwdata_0(10), B => hwdata_1(10), S => - \hmasterd_1[1]\, Y => N_6514); - - \r.hslave_1_RNI3UPA[0]\ : MX2C - port map(A => hrdata_1(19), B => hrdata_2_19, S => - \hslave_1[0]\, Y => N_469); - - \r.hmaster_RNIKBP3[1]\ : OR2B - port map(A => \hmaster[1]\, B => hsize_0(0), Y => N_4651); - - \r.hmaster_0_0_RNIEL59N[0]\ : MX2C - port map(A => N_4610, B => N_6503, S => \hmaster_0[0]\, Y - => \hwrite\); - - \r.hslave_0_0_RNID90B[0]\ : OR3B - port map(A => hresp(0), B => N_651_2, C => \hslave_0[0]\, Y - => N_569); - - \r.hslave_0_0_RNI16LM6_0[2]\ : AO1C - port map(A => N_417_0, B => N_491, C => \hrdata_1_0[12]\, Y - => hrdata_0(12)); - - \r.hslave_0_0_RNI0BKC[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_2_29, C => N_650, - Y => N_606); - - \r.hmasterd_1_RNIAPM9[1]\ : MX2C - port map(A => hwdata_1(31), B => hwdata_2_28, S => - \hmasterd_1[1]\, Y => N_6535); - - \r.haddr_RNI726O[6]\ : NOR3A - port map(A => N_24, B => N_6467, C => N_6474, Y => - \haddr_RNI726O[6]\); - - \r.cfgsel_RNIIIOKI\ : MX2C - port map(A => \un34_hready[17]\, B => N_477, S => cfgsel, Y - => hrdata(14)); - - \r.hslave_0_0_RNIQ8318_0[0]\ : AO1B - port map(A => N_6351, B => N_663, C => \hrdata_1_1[16]\, Y - => hrdata_0(16)); - - \r.hmaster_0_0_RNI87DIJ[0]\ : MX2 - port map(A => N_4596, B => N_6286, S => \hmaster_0[0]\, Y - => \haddr[18]\); - - \r.hslave_1[0]\ : DFN1 - port map(D => \hslave_RNI6LMVPE[0]\, CLK => lclk_c, Q => - \hslave_1[0]\); - - \r.hslave_1_RNILTOA[0]\ : MX2C - port map(A => hrdata(20), B => hrdata_0(20), S => - \hslave_1[0]\, Y => N_470); - - \r.hmaster_0_0_RNIE16CT4[0]\ : NOR3C - port map(A => un2_ioarea_5, B => un2_ioarea_4, C => - un2_ioarea_13, Y => un2_ioarea_16); - - \r.hslave_0_0_RNIBTJG7[2]\ : MX2C - port map(A => N_480, B => N_6344, S => \hslave_0[2]\, Y => - N_488); - - \r.hslave_RNITTOV6[0]\ : OR3C - port map(A => N_536, B => N_535, C => N_534, Y => - hrdata(22)); - - \r.hmasterd_RNIOK4E[1]\ : MX2 - port map(A => hwdata_0(0), B => hwdata_1(0), S => - \hmasterd[1]\, Y => N_6504); - - \r.hmaster_2_RNIKE6V[1]\ : NOR2 - port map(A => hbusreq_i_3_0, B => \haddr[5923]\, Y => - \vect[3]\); - - \r.hrdatam[24]\ : DFN1 - port map(D => \hrdatam_1[24]\, CLK => lclk_c, Q => - \hrdatam[24]\); - - \r.hslave_RNIHFK5[0]\ : MX2C - port map(A => hrdata_1(25), B => hrdata_2_25, S => - \hslave[0]\, Y => N_460); - - \r.hmasterd_0_RNIQJ3T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6528, C => N_94, Y - => hwdata(24)); - - \r.hmasterd_1_RNI9LM9[1]\ : MX2C - port map(A => hwdata_1(30), B => hwdata_2_27, S => - \hmasterd_1[1]\, Y => N_6602); - - \r.hmaster_0_0[1]\ : DFN1 - port map(D => N_5627_i, CLK => lclk_c, Q => \hmaster_0[1]\); - - \r.hmasterd_1_RNIB1N9[1]\ : MX2 - port map(A => hwdata(23), B => hwdata_0(23), S => - \hmasterd_1[1]\, Y => N_6595); - - \r.hmasterd_RNIGJKV[1]\ : OR3A - port map(A => N_423, B => \hmasterd[0]\, C => \hmasterd[1]\, - Y => N_667); - - \r.hmasterd_0_RNI7JA91[0]\ : NOR2B - port map(A => brmw_i, B => hwdata(14), Y => hwdata_m_0_2); - - \r.hslave_RNIH8Q9[0]\ : MX2 - port map(A => hrdata_3_0, B => hrdata_4_0, S => \hslave[0]\, - Y => N_5257); - - \r.cfgsel_0_0_RNIMR2TH\ : MX2C - port map(A => \un34_hready[27]\, B => N_478, S => cfgsel_0, - Y => hrdata_0(24)); - - \r.hmaster_RNI8M8A[1]\ : MX2 - port map(A => haddr_0(31), B => haddr_1(31), S => - \hmaster[1]\, Y => N_6502); - - \r.hmaster_2_RNI18U8[1]\ : MX2 - port map(A => haddr_2(2), B => haddr_3_0, S => - \hmaster_2[1]\, Y => N_4620); - - \r.hmaster_0_0_RNIFCVH1_0[1]\ : AO1C - port map(A => hbusreq_i_3, B => arb_0_sqmuxa_1_a1_0, C => - \vect[3]\, Y => \hmaster_0_0_RNIFCVH1_0[1]\); - - \r.hrdatas[30]\ : DFN1 - port map(D => \hrdatas_RNO[30]\, CLK => lclk_c, Q => - \hrdatas[30]\); - - \r.hslave_0_0_RNIN1N08_0[0]\ : AO1B - port map(A => N_6343, B => N_663, C => \hrdata_0_0_1[8]\, Y - => hrdata_0(8)); - - \r.hslave_0_0_RNIT75O8[0]\ : MX2 - port map(A => hrdata_2_18, B => hrdata_3_18, S => - \hslave_0[0]\, Y => N_6353); - - \r.hmaster_2_RNIGTV9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_0(27), Y => N_4605); - - \r.hmaster_RNITVPPN[0]\ : MX2C - port map(A => N_4576, B => N_4616, S => \hmaster[0]\, Y => - \htrans[0]\); - - \r.hmaster_0_0_RNIUO19[1]\ : NOR2A - port map(A => size(0), B => \hmaster_0[1]\, Y => - \un34_haddr_0[37]\); - - \r.hmasterd_RNIVR0U[0]\ : MX2 - port map(A => N_6551, B => N_6504, S => \hmasterd[0]\, Y - => hwdata(0)); - - \r.hmasterd_RNI4RJV[1]\ : OR3A - port map(A => N_459, B => \hmasterd[0]\, C => \hmasterd[1]\, - Y => N_645); - - \r.hslave_0_0_RNIPLPA[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_2_6, C => N_650, Y - => N_625); - - \r.hslave_RNI3R2LG[2]\ : AO1C - port map(A => N_417, B => N_493, C => N_599, Y => - hrdata_2_15); - - \r.hslave_RNIQJ9AH[2]\ : MX2C - port map(A => N_5281, B => N_6359, S => \hslave[2]\, Y => - N_5349); - - \r.hmasterd_0_RNI6FKH[1]\ : OR2A - port map(A => hwdata_0(30), B => \hmasterd_0[1]\, Y => - N_4734); - - \r.hmasterd_1[1]\ : DFN1E1 - port map(D => \hmaster_0[1]\, CLK => lclk_c, E => - \iosn[93]\, Q => \hmasterd_1[1]\); - - \r.hslave_0_0_RNI6NV3I[2]\ : MX2C - port map(A => N_5271, B => N_6349, S => \hslave_0[2]\, Y - => N_5339); - - \r.hmasterd_RNI6BOG1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6595, C => N_645, Y => - hwdata_1(23)); - - \r.hmasterd_RNIR5TF1[0]\ : MX2 - port map(A => N_4722, B => N_6522, S => \hmasterd[0]\, Y - => hwdata_2_15); - - \r.hslave_0_0[2]\ : DFN1 - port map(D => \hslave_RNIQRGJS9[2]\, CLK => lclk_c, Q => - \hslave_0[2]\); - - \r.hrdatas_RNIOB57[16]\ : OR2B - port map(A => \hrdatas[16]\, B => N_657, Y => N_600); - - \r.defslv_RNO_3\ : NOR2B - port map(A => \iosn_0[93]\, B => \hsel_i[0]\, Y => - defslv_0_sqmuxa_0); - - \r.hmaster_RNI1JVE79[0]\ : OAI1 - port map(A => \hsel_i[0]\, B => \un6_ioen_NE_0\, C => - \un51_ioen_NE\, Y => \hmbsel_1[0]\); - - \r.hrdatas[31]\ : DFN1 - port map(D => \hrdatas_RNO[31]\, CLK => lclk_c, Q => - \hrdatas[31]\); - - \r.hslave_1_RNICPVG[0]\ : OR2B - port map(A => hrdata_4_4, B => N_664, Y => N_584); - - \r.hslave_0_0_RNIN82MC[2]\ : NOR2A - port map(A => N_473, B => N_417, Y => N_264); - - \r.hrdatas_RNO[6]\ : AO1C - port map(A => N_6470, B => \haddr[5]\, C => N_48, Y => - \hrdatas_RNO[6]\); - - \r.hmasterd_1_RNI9PM9[1]\ : MX2 - port map(A => hwdata(21), B => hwdata_0(21), S => - \hmasterd_1[1]\, Y => N_6593); - - \r.haddr_RNIEOPJ_0[8]\ : NOR3B - port map(A => N_6468, B => N_6472, C => N_6465, Y => N_6476); - - \r.hslave_1_RNIDPVG[0]\ : OR2B - port map(A => hrdata_3_5, B => N_664, Y => N_588); - - \r.hmaster_RNIVV36[1]\ : OR2B - port map(A => \hmaster[1]\, B => htrans_0_0, Y => N_4616); - - \r.hmasterd_0_RNI21HI[1]\ : OR3A - port map(A => N_139, B => \hmasterd_0[0]\, C => - \hmasterd_0[1]\, Y => N_206); - - \r.defslv_RNO_1\ : NOR3A - port map(A => defslv_0_sqmuxa_1, B => un5_bnslave, C => - \hmbsel_2[0]\, Y => defslv_0_sqmuxa); - - \un1_acdm_3_0_a2_0_0[57]\ : MX2 - port map(A => data_5, B => data_0_2, S => bo_5842_d_0, Y - => \un1_acdm_3_0_a2_0[57]\); - - \r.hmasterd_0_RNINVI7[1]\ : MX2C - port map(A => hwdata(4), B => hwdata_0(4), S => - \hmasterd_0[1]\, Y => N_6305); - - \r.cfgsel_RNIIS83_0\ : OR2 - port map(A => cfgsel, B => N_643, Y => N_650); - - \r.hslave_RNI2QGJ[2]\ : MX2C - port map(A => N_464, B => N_6361, S => \hslave[2]\, Y => - N_465); - - \r.hmasterd_RNIU30C1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6573, C => N_641, Y => - hwdata_1(1)); - - \r.hmasterlock\ : DFN1 - port map(D => hmasterlock_RNO, CLK => lclk_c, Q => - hmastlock); - - \r.hslave_0_0_RNIRTPA[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_3_8, C => N_650, Y - => N_622); - - \r.hslave_RNIU7LO[2]\ : MX2C - port map(A => N_484, B => N_6348, S => \hslave[2]\, Y => - N_492); - - \r.hmaster_1_RNI0LU9J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_0(22), Y => N_4600); - - \r.hrdatam_RNIS759[12]\ : OR3B - port map(A => \hrdatam[13]\, B => cfgsel_0, C => cfga11, Y - => N_594); - - \r.hmasterd_1_RNIRFJ7[1]\ : MX2 - port map(A => hwdata_0(5), B => hwdata_1(5), S => - \hmasterd_1[1]\, Y => N_6577); - - \r.hrdatas_RNI5QP3[4]\ : NOR2B - port map(A => \hrdatas[9]\, B => N_657, Y => N_581); - - \r.hmasterd_0_RNIGBLH[1]\ : NOR2 - port map(A => hwdata_0(19), B => \hmasterd_0[1]\, Y => - N_4723); - - \r.hmasterd_0[1]\ : DFN1E1 - port map(D => \hmaster_0[1]\, CLK => lclk_c, E => - \iosn[93]\, Q => \hmasterd_0[1]\); - - \r.hmaster_1_RNI8JSB[1]\ : MX2 - port map(A => haddr_0(15), B => haddr_1(15), S => - \hmaster_1[1]\, Y => N_6486); - - \r.hslave_1_RNI8GIRG[0]\ : MX2 - port map(A => hrdata_3_2, B => hrdata_4_2, S => - \hslave_1[0]\, Y => N_6337); - - \r.haddr_RNIT9C4_1[5]\ : NOR2A - port map(A => \haddr_3[4]\, B => \haddr[5]\, Y => N_6472); - - \r.hmaster_0_0[0]\ : DFN1 - port map(D => N_5626_i, CLK => lclk_c, Q => \hmaster_0[0]\); - - \r.hslave_1_RNIAAVDF[0]\ : MX2 - port map(A => hrdata_1(0), B => hrdata_2_0, S => - \hslave_1[0]\, Y => N_6335); - - \r.hrdatas_RNI7QP3[6]\ : OR2B - port map(A => \hrdatas[8]\, B => N_657, Y => N_620); - - \r.hslave_1_RNI5FPNE[0]\ : MX2 - port map(A => hrdata_1(1), B => hrdata_2_1, S => - \hslave_1[0]\, Y => N_6336); - - \r.hslave_0_0_RNI5UPGH[2]\ : MX2C - port map(A => N_5259, B => N_6337, S => \hslave_0[2]\, Y - => N_5327); - - \r.haddr[6]\ : DFN1E1 - port map(D => haddr_2(6), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[6]\); - - \r.hmaster_2_RNI53SB[1]\ : MX2 - port map(A => haddr_0(13), B => haddr_1(13), S => - \hmaster_2[1]\, Y => N_6484); - - \r.hslave_0_0_RNIEL881_1[0]\ : NOR2 - port map(A => hready_1_iv_0_o2_0, B => N_660, Y => - \iosn_0[93]\); - - \r.hmaster[0]\ : DFN1 - port map(D => N_5626_i, CLK => lclk_c, Q => \hmaster[0]\); - - \r.hslave_1_RNIR5PA[0]\ : MX2C - port map(A => hrdata_1(31), B => hrdata_2_31, S => - \hslave_1[0]\, Y => N_486); - - \r.hmaster_0_0_RNIEUKP3[1]\ : NOR3A - port map(A => address(1), B => \hmaster_0[1]\, C => - nbo_5_0(1), Y => \un34_haddr_1[5]\); - - \r.hmasterlock_RNID01N1\ : AOI1 - port map(A => arb_0_sqmuxa_1_a2_0, B => N_4617, C => - hmastlock, Y => arb_0_sqmuxa_0); - - \r.cfgsel_RNIQIMCBC\ : NOR2B - port map(A => rstn, B => N_5557, Y => cfgsel_RNIQIMCBC); - - \r.hslave_1_RNI8TSLF_0[0]\ : AO1B - port map(A => N_6336, B => N_663, C => \hrdata_1_0_1[1]\, Y - => hrdata_0(1)); - - \r.hmaster_RNII6AA[1]\ : MX2 - port map(A => haddr_1(27), B => haddr_2(27), S => - \hmaster[1]\, Y => N_6498); - - \r.hslave_0_0_RNI34T07[0]\ : MX2C - port map(A => hrdata_3_17, B => hrdata_4_17, S => - \hslave_0[0]\, Y => N_6352); - - \r.hmasterd_0_RNIALFM1[0]\ : OR2A - port map(A => hwdata(20), B => N_510, Y => hwdata_m_13); - - \r.hmasterd_RNIHQ8G[1]\ : MX2 - port map(A => hwdata(18), B => hwdata_0(18), S => - \hmasterd[1]\, Y => N_6522); - - \r.hslave_0_0_RNIIK4A6[2]\ : AO1A - port map(A => N_417_0, B => N_489, C => N_581, Y => - hrdata_0(10)); - - \r.hslave_RNIBH9KG[2]\ : MX2C - port map(A => N_5280, B => N_6358, S => \hslave[2]\, Y => - N_5348); - - \r.hmasterd_RNIHO6O[1]\ : NOR2 - port map(A => hwdata_1(17), B => \hmasterd[1]\, Y => N_4721); - - \r.hslave_RNILNK5[0]\ : MX2 - port map(A => hrdata_3_27, B => hrdata_4_27, S => - \hslave[0]\, Y => N_471); - - \r.hmasterd_1_RNIC9N9[1]\ : MX2 - port map(A => hwdata_1(15), B => hwdata_2_12, S => - \hmasterd_1[1]\, Y => N_6519); - - \r.haddr_RNIATVL[2]\ : OR2A - port map(A => N_6476, B => \haddr[2]\, Y => N_6477); - - \r.hmaster_0_0_RNIUQ19[1]\ : MX2 - port map(A => haddr_0(18), B => haddr_1(18), S => - \hmaster_0[1]\, Y => N_6286); - - \r.hslave_RNIFO8E1[2]\ : AO1D - port map(A => N_492, B => N_417_0, C => \hrdata_1_0[13]\, Y - => hrdata_0(13)); - - \r.hslave_0_0_RNIE9JV[0]\ : NOR3C - port map(A => N_625, B => N_620, C => N_626, Y => - \hrdata_1_0_1[6]\); - - \r.hmasterd_RNIDTI41[0]\ : MX2C - port map(A => N_4707, B => N_6304, S => \hmasterd[0]\, Y - => hwdata_1(3)); - - \r.hmasterd_RNI161F[1]\ : NOR2 - port map(A => hwdata_0(6), B => \hmasterd[1]\, Y => N_4710); - - \r.hrdatas_RNO_0[15]\ : OR2A - port map(A => N_25, B => N_6471, Y => N_50); - - \r.hmasterd_RNIDIUS1[0]\ : OR2B - port map(A => brmw_i, B => hwdata(12), Y => hwdata_m_0_0); - - \r.hmaster_RNIEBB7[1]\ : MX2 - port map(A => haddr_0(7), B => haddr_1(7), S => - \hmaster[1]\, Y => N_4625); - - \r.hslave_0_0_RNIBJ5H[2]\ : OA1C - port map(A => N_460, B => \hslave_0[2]\, C => N_417_0, Y - => \hrdata_i_0_0[25]\); - - \r.hmasterd_1_RNID9N9[1]\ : MX2 - port map(A => hwdata_0(25), B => hwdata_1(25), S => - \hmasterd_1[1]\, Y => N_6529); - - \r.haddr_RNI1AC4_1[6]\ : NOR2 - port map(A => \haddr[7]\, B => \haddr[6]\, Y => N_6468); - - \r.defslv_RNO\ : OA1 - port map(A => defslv_RNO_0, B => defslv_0_sqmuxa, C => rstn, - Y => defslv_RNO); - - \r.hslave_0_0_RNISLHH7[2]\ : MX2C - port map(A => N_5274, B => N_6352, S => \hslave_0[2]\, Y - => N_5342); - - \r.hmaster_0_0_RNINFO2AC[0]\ : NOR2B - port map(A => un2_ioarea_17, B => un2_ioarea_16, Y => - un2_ioarea); - - \r.hmasterd_0_RNI8JKH[1]\ : OR2A - port map(A => hwdata_0(31), B => \hmasterd_0[1]\, Y => - N_4735); - - \r.hmaster_0_0_RNIMVHA71[0]\ : NOR2B - port map(A => \haddr[18]\, B => \haddr[19]\, Y => - un2_ioarea_3); - - \r.hmasterd_1_RNIB5N9[1]\ : MX2 - port map(A => hwdata_1(14), B => hwdata_2_11, S => - \hmasterd_1[1]\, Y => N_6586); - - \un1_acdm_3_0_o3_0_m2[76]\ : MX2 - port map(A => data_24, B => data_0_21, S => bo_5842_d, Y - => N_423); - - \r.hmaster_0_0_RNI35KKE2[0]\ : NOR3C - port map(A => \haddr[25]\, B => \haddr[24]\, C => - un2_ioarea_7, Y => un2_ioarea_13); - - \r.hslave_0_0_RNIV5PU[0]\ : NOR3C - port map(A => N_606, B => N_604, C => N_607, Y => - \hrdata_1_1[29]\); - - \r.hslave_0_0_RNIEL881_0[0]\ : NOR2 - port map(A => hready_1_iv_0_o2_0, B => N_660, Y => - \iosn_2[93]\); - - \r.hmaster_RNIQ16MJ[0]\ : MX2 - port map(A => N_4594, B => N_6487, S => \hmaster[0]\, Y => - \haddr[16]\); - - \r.hslave_RNIQFKV7[2]\ : MX2C - port map(A => N_482, B => N_6346, S => \hslave[2]\, Y => - N_490); - - \r.hmasterd_0_RNITR3T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6529, C => N_208, Y - => hwdata(25)); - - \r.hslave_1_RNI5NVE[0]\ : MX2 - port map(A => hrdata_1(3), B => hrdata_2_3, S => - \hslave_1[0]\, Y => N_5260); - - \r.hrdatas_RNI88G3[2]\ : NOR2B - port map(A => \hrdatas[3]\, B => cfga11, Y => N_4876); - - \r.hmasterd_1_RNIVFJ7[1]\ : MX2 - port map(A => hwdata(9), B => hwdata_0(9), S => - \hmasterd_1[1]\, Y => N_6581); - - \r.hmaster_RNI2BB7[1]\ : MX2C - port map(A => haddr_0(1), B => haddr_1(1), S => - \hmaster[1]\, Y => N_4619); - - \r.hmaster_RNI2T0MS[0]\ : MX2 - port map(A => N_4577, B => N_4617, S => \hmaster[0]\, Y => - \htrans[1]\); - - \r.hrdatas[14]\ : DFN1 - port map(D => \hrdatas_RNO[14]\, CLK => lclk_c, Q => - \hrdatas[14]\); - - \r.hmaster_RNI1D75M5[0]\ : OR2A - port map(A => \un1_nhmaster_0_sqmuxa_1\, B => - \bco_msb_1[1]\, Y => \bco_msb_1_m[1]\); - - \r.cfgsel_0_0_RNI0995\ : OR2A - port map(A => N_393, B => cfgsel_0, Y => N_417_0); - - \r.hmasterd_1_RNIUD2P[1]\ : OR3A - port map(A => N_463, B => \hmasterd[0]\, C => - \hmasterd_1[1]\, Y => N_637); - - \r.hrdatas[2]\ : DFN1 - port map(D => hrdatas6, CLK => lclk_c, Q => \hrdatas[3]\); - - \r.hslave_1_RNIJIUIH[0]\ : MX2C - port map(A => hrdata_3_14, B => hrdata_4_14, S => - \hslave_1[0]\, Y => N_6349); - - \r.hmaster_0_0_RNIS83UE2_0[0]\ : NOR2B - port map(A => un51_ioen_NE_0, B => un51_ioen_NE_6, Y => - un51_ioen_NE_1); - - \r.hmaster_RNIFJUME2[0]\ : NOR3C - port map(A => \haddr[17]\, B => \haddr[16]\, C => - un2_ioarea_3, Y => un2_ioarea_11); - - \r.hmaster_0_0_RNI4C9LJ[0]\ : MX2C - port map(A => N_4607, B => N_6500, S => \hmaster_0[0]\, Y - => \haddr[29]\); - - \r.hmaster_1_RNI2JRB[1]\ : MX2 - port map(A => haddr_1(21), B => haddr_2(21), S => - \hmaster_1[1]\, Y => N_6492); - - \r.hslave_1_RNIAET9[0]\ : NOR2 - port map(A => \hslave_1[0]\, B => N_650, Y => N_664); - - \r.hslave_RNO_0[1]\ : MX2C - port map(A => \hslave[1]\, B => \hmbsel_2[0]\, S => - \iosn_2[93]\, Y => \hslave_3[1]\); - - \r.hslave[0]\ : DFN1 - port map(D => \hslave_RNI6LMVPE[0]\, CLK => lclk_c, Q => - \hslave[0]\); - - \r.cfgsel_0_0_RNI7JIUF_0\ : NOR3A - port map(A => N_393, B => cfgsel_0, C => N_5325, Y => - hrdata_0(0)); - - \r.defslv_RNO_2\ : NOR2A - port map(A => defslv_0_sqmuxa_0, B => un2_ioarea, Y => - defslv_0_sqmuxa_1); - - \r.hmaster_2_RNI09U9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_0(30), Y => N_4608); - - \r.hrdatas_RNIP1R6[30]\ : OR2B - port map(A => \hrdatas[30]\, B => cfga11, Y => N_4904); - - \r.hslave_0_0_RNICA1J9_0[0]\ : AO1B - port map(A => N_6353, B => N_663, C => \hrdata_0_0[18]\, Y - => hrdata_0(18)); - - \r.hslave_0_0_RNI1J2D[0]\ : AO1A - port map(A => hready_1_iv_0_a2_0_0, B => N_651_2, C => - hready_RNICLR2, Y => hready_1_iv_0_o2_0); - - \r.hmasterd_0_RNIAVKH[1]\ : NOR2 - port map(A => hwdata_0(16), B => \hmasterd_0[1]\, Y => - N_4720); - - \r.hslave_0_0_RNIIU1HB[0]\ : AO1B - port map(A => N_6340, B => N_663, C => \hrdata_1_1[5]\, Y - => hrdata(5)); - - \r.hmaster_RNI50DPJ[0]\ : MX2 - port map(A => N_4606, B => N_6499, S => \hmaster[0]\, Y => - \haddr[28]\); - - \r.hmaster_1_RNI28U8[1]\ : MX2 - port map(A => haddr_0(3), B => haddr_1(3), S => - \hmaster_1[1]\, Y => N_4621); - - \r.hrdatas_RNO[28]\ : NOR2A - port map(A => N_6472, B => N_6470, Y => \hrdatas_RNO[28]\); - - \r.hmasterd_1_RNIEDN9[1]\ : MX2C - port map(A => hwdata_1(26), B => hwdata_2_23, S => - \hmasterd_1[1]\, Y => N_6530); - - \r.hmasterd_1_RNI0I2P[1]\ : OR3A - port map(A => N_468, B => \hmasterd[0]\, C => - \hmasterd_1[1]\, Y => N_639); - - \r.hmaster_0_0_RNIRMD4[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => \hmaster_0[0]\, Y => - arb_0_sqmuxa_1_a1_0); - - \r.hslave_0_0_RNI2T0G5_0[0]\ : MX2C - port map(A => hrdata(10), B => hrdata_1(10), S => - \hslave_0[0]\, Y => N_6345); - - \r.hmasterd_RNI0L4E[1]\ : MX2 - port map(A => hwdata_0(8), B => hwdata_1(8), S => - \hmasterd[1]\, Y => N_6512); - - \r.hslave_0_0_RNIS8PJH[2]\ : NOR2A - port map(A => N_393, B => N_5327, Y => \un34_hready[5]\); - - \r.hslave_RNIHHQQ[0]\ : NOR3 - port map(A => N_547, B => N_545, C => N_548, Y => - \hrdata_1_0_1[1]\); - - \r.hrdatas[12]\ : DFN1 - port map(D => \hrdatas_RNO[12]\, CLK => lclk_c, Q => - \hrdatas[12]\); - - \r.hmaster_0_0_RNIPS37J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_0(25), Y => N_4603); - - \r.cfgsel_RNIIS83\ : OR2A - port map(A => N_393, B => cfgsel, Y => N_417); - - \r.hrdatas_RNIN757[15]\ : OR2B - port map(A => \hrdatas[15]\, B => N_657, Y => N_599); - - \r.hmaster_2_RNIVOU9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(13), Y => N_4591); - - \r.hmaster_1_RNIIEJ6J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_3_6, Y => N_4586); - - \r.hmaster_RNIT3RFJ[0]\ : MX2 - port map(A => N_4584, B => N_4624, S => \hmaster[0]\, Y => - haddr_2(6)); - - \r.hmasterd_RNI706O[1]\ : NOR2 - port map(A => \hmasterd[1]\, B => N_458, Y => N_6552); - - \r.hmasterd_0_RNIG0GI[1]\ : OR3A - port map(A => \un1_acdm_3_0_a2_0[57]\, B => \hmasterd_0[0]\, - C => \hmasterd_0[1]\, Y => N_6406); - - \r.hslave_RNIQTQQ[0]\ : NOR3B - port map(A => N_583, B => N_584, C => N_581, Y => - \hrdata_0_1[4]\); - - \r.hmaster_RNIJD05J[1]\ : NOR2 - port map(A => \hmaster[1]\, B => haddr_3_5, Y => N_4585); - - \r.hmaster_1_RNIC8U8[1]\ : MX2 - port map(A => haddr_0(8), B => haddr_1(8), S => - \hmaster_1[1]\, Y => N_4626); - - \r.hmaster_2_RNIHBTB[1]\ : MX2 - port map(A => haddr_0(28), B => haddr_1(28), S => - \hmaster_2[1]\, Y => N_6499); - - \r.cfgsel_RNIV2JNH\ : MX2 - port map(A => \un34_hready[5]\, B => N_4876, S => cfgsel, Y - => hrdata(2)); - - \r.hmaster_2_RNIT7U8[1]\ : MX2C - port map(A => haddr_0_d0, B => haddr_0(0), S => - \hmaster_2[1]\, Y => N_4618); - - \r.hmaster_1_RNILIJ6J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_3_7, Y => N_4587); - - \r.hslave_0_0_RNI8P64J[2]\ : NOR2A - port map(A => N_474, B => N_417_0, Y => N_262_0); - - \r.hmasterd_RNI3C9N1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6585, C => N_556, Y => - hwdata_1(13)); - - \r.hrdatas[24]\ : DFN1 - port map(D => \hrdatas_RNO[24]\, CLK => lclk_c, Q => - \hrdatas[24]\); - - \r.hmaster_0_0_RNIGB7LJ[0]\ : MX2 - port map(A => N_4603, B => N_6496, S => \hmaster_0[0]\, Y - => \haddr[25]\); - - \r.hslave_RNIIETLE_0[0]\ : AO1B - port map(A => N_6356, B => N_663, C => \hrdata_0_0[21]\, Y - => hrdata_0(21)); - - \r.hmaster_0_0_RNIHB1OJ[0]\ : MX2 - port map(A => N_4600, B => N_6493, S => \hmaster_0[0]\, Y - => \haddr[22]\); - - \r.hmaster_RNICMMNJ[0]\ : MX2 - port map(A => N_4609, B => N_6502, S => \hmaster[0]\, Y => - \hsel_i[0]\); - - \r.hslave_1_RNID70F[0]\ : MX2C - port map(A => hrdata_3_7, B => hrdata_4_7, S => - \hslave_1[0]\, Y => N_479); - - \r.hmaster_0_0_RNIMQAIJ[0]\ : MX2 - port map(A => N_4601, B => N_6494, S => \hmaster_0[0]\, Y - => \haddr[23]\); - - \r.hmaster_RNI6E8A[1]\ : MX2 - port map(A => haddr_1(30), B => haddr_2(30), S => - \hmaster[1]\, Y => N_6501); - - \r.hmaster_1_RNI0BRB[1]\ : MX2 - port map(A => haddr_0(20), B => haddr_1(20), S => - \hmaster_1[1]\, Y => N_6288); - - \r.hmasterd_RNIGM8G[1]\ : MX2 - port map(A => hwdata(17), B => hwdata_0(17), S => - \hmasterd[1]\, Y => N_6521); - - \r.hslave_RNIII5DG[0]\ : MX2 - port map(A => hrdata_1(23), B => hrdata_2_23, S => - \hslave[0]\, Y => N_6358); - - \r.hslave_RNIMFUC6[0]\ : OR2B - port map(A => N_6357, B => N_663, Y => N_534); - - \r.hslave_1_RNIHF0F[0]\ : MX2C - port map(A => hrdata_3_9, B => hrdata_4_9, S => - \hslave_1[0]\, Y => N_480); - - \r.hrdatas_RNILN47[31]\ : OR2B - port map(A => \hrdatas[31]\, B => N_657, Y => N_609); - - \r.hmasterd_0_RNIEA8S[0]\ : MX2C - port map(A => N_4730, B => N_6530, S => \hmasterd_0[0]\, Y - => hwdata(26)); - - \r.hslave_1_RNI0JBR6[0]\ : MX2C - port map(A => hrdata(9), B => hrdata_1(9), S => - \hslave_1[0]\, Y => N_6344); - - \r.hslave_0_0[0]\ : DFN1 - port map(D => \hslave_RNI6LMVPE[0]\, CLK => lclk_c, Q => - \hslave_0[0]\); - - \r.hmaster_RNI4M8A[1]\ : MX2C - port map(A => haddr_1(11), B => haddr_2(11), S => - \hmaster[1]\, Y => N_6482); - - \r.hmaster_RNI3F6M[1]\ : MX2 - port map(A => htrans_1(1), B => htrans_2(1), S => - \hmaster[1]\, Y => N_4617); - - \un1_acdm_3_0_a2_0_0[55]\ : MX2 - port map(A => data_3, B => data_0_0, S => bo_5842_d_0, Y - => \un1_acdm_3_0_a2_0[55]\); - - \r.hmaster_0_0_RNIDUKP3[1]\ : NOR3A - port map(A => address(0), B => \hmaster_0[1]\, C => - nbo_5_0(1), Y => \un34_haddr_1[4]\); - - \r.hslave_RNI3FCC[0]\ : MX2C - port map(A => hrdata(26), B => hrdata_1(26), S => - \hslave[0]\, Y => N_6361); - - \r.hslave_RNIHU8DH[2]\ : OR2B - port map(A => N_5349, B => N_393, Y => \un34_hready[27]\); - - \r.hslave_0_0_RNILS5EA[0]\ : MX2 - port map(A => hrdata_0(5), B => hrdata_1(5), S => - \hslave_0[0]\, Y => N_6340); - - \r.cfgsel_RNI4JH0B\ : MX2 - port map(A => \un34_hready[6]\, B => N_4876, S => cfgsel, Y - => hrdata(3)); - - \r.hmaster_1_RNIRGU9J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_0(12), Y => N_4590); - - \r.hslave_RNIKN4TD[2]\ : AO1C - port map(A => N_417, B => N_476, C => \hrdata_1_0[28]\, Y - => hrdata(28)); - - \r.cfga11_RNIHMG\ : NOR2B - port map(A => cfgsel, B => cfga11, Y => N_657); - - \r.cfgsel_0_0_RNIDFJPH\ : MX2 - port map(A => \un34_hready[5]\, B => N_4876, S => cfgsel_0, - Y => hrdata_0(2)); - - \r.hslave_1_RNILTB1A[0]\ : AO1B - port map(A => N_6339, B => N_663, C => \hrdata_0_1[4]\, Y - => hrdata(4)); - - \r.hmasterd_RNIE0EM[1]\ : OR3A - port map(A => N_466, B => \hmasterd[0]\, C => \hmasterd[1]\, - Y => N_641); - - \r.hslave_1_RNILTB1A_0[0]\ : AO1B - port map(A => N_6339, B => N_663, C => \hrdata_0_1[4]\, Y - => hrdata_0(4)); - - \r.hmasterlock_RNO\ : OA1 - port map(A => hlock_m_0, B => hmasterlock_2_0, C => rstn, Y - => hmasterlock_RNO); - - \r.hslave_RNINAV2_0[1]\ : OR2B - port map(A => \hslave[2]\, B => \hslave[1]\, Y => N_654); - - \r.hrdatas[16]\ : DFN1 - port map(D => \hrdatas_RNO[16]\, CLK => lclk_c, Q => - \hrdatas[16]\); - - \r.hmaster_1_RNI92J6J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_3_3, Y => N_4583); - - \r.hrdatas_RNI6QP3[5]\ : OR2B - port map(A => \hrdatas[5]\, B => N_657, Y => N_585); - - \r.hmaster_0_0_RNIVNJQK[0]\ : MX2 - port map(A => N_4581, B => N_4621, S => \hmaster_0[0]\, Y - => haddr_2(3)); - - \r.hslave_RNINAV2_1[1]\ : OR2 - port map(A => \hslave[2]\, B => \hslave[1]\, Y => N_643); - - \r.hmaster_1_RNIGJTB[1]\ : MX2 - port map(A => haddr_0(19), B => haddr_1(19), S => - \hmaster_1[1]\, Y => N_6490); - - \r.cfgsel_RNI8F2RH\ : MX2C - port map(A => \un34_hready[27]\, B => N_478, S => cfgsel, Y - => hrdata(24)); - - \r.hmasterlock_RNI4GHMH1\ : NOR3C - port map(A => \hburst[0]\, B => arb_1_sqmuxa_1_0, C => - \htrans[1]\, Y => arb_1_sqmuxa_1_i); - - \r.hslave_0_0_RNIA36S6[0]\ : MX2 - port map(A => hrdata_0(29), B => hrdata_1(29), S => - \hslave_0[0]\, Y => N_6364); - - \r.hrdatam_RNO_0[27]\ : OR2A - port map(A => \haddr[6]\, B => \haddr[7]\, Y => - \hrdatam_1_0_a5_0[27]\); - - \r.hslave_0_0_RNIJ1SB9[2]\ : AO1A - port map(A => N_417, B => N_487, C => N_581, Y => - hrdata_2_7); - - \r.hmaster_0_0_RNI5BCIJ[0]\ : MX2 - port map(A => N_4604, B => N_6294, S => \hmaster_0[0]\, Y - => \haddr[26]\); - - \r.hslave_0_0_RNIP2CA[0]\ : MX2C - port map(A => hrdata_0(30), B => hrdata_1(30), S => - \hslave_0[0]\, Y => N_5287); - - \r.hmaster_2_RNIP8U9J[1]\ : OR2A - port map(A => haddr_0(11), B => \hmaster_2[1]\, Y => N_4589); - - \r.hmaster_0_0_RNITG47J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_2(18), Y => N_4596); - - \r.hmasterd_1_RNI8LM9[1]\ : MX2 - port map(A => hwdata_0(20), B => hwdata_1(20), S => - \hmasterd_1[1]\, Y => N_6524); - - \r.hmasterd_1_RNI1U6A1[1]\ : OR2B - port map(A => N_640, B => N_639, Y => hwdata_1(22)); - - \r.hmaster_2_RNIS3Q8K[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_0(2), Y => N_4580); - - \r.hslave_0_0_RNIN1N08[0]\ : AO1B - port map(A => N_6343, B => N_663, C => \hrdata_0_0_1[8]\, Y - => hrdata(8)); - - \r.cfgsel_0_0_RNIBQIPG\ : NOR3A - port map(A => N_393, B => cfgsel_0, C => N_5348, Y => - hrdata(23)); - - \r.hrdatas_RNO[29]\ : AO1C - port map(A => N_77, B => \haddr[2]\, C => N_6464, Y => - \hrdatas_RNO[29]\); - - \r.hrdatas_RNO[15]\ : OR3C - port map(A => N_6470, B => N_43, C => N_50, Y => - \hrdatas_RNO[15]\); - - \r.hslave_0_0_RNIQC62J[2]\ : NOR2A - port map(A => N_474, B => N_417, Y => N_262); - - \r.hslave_0_0_RNI8JN1C[0]\ : MX2C - port map(A => hrdata(19), B => hrdata_0(19), S => - \hslave_0[0]\, Y => N_6354); - - \r.hslave_0_0_RNIVMCA[0]\ : MX2C - port map(A => hrdata_1(17), B => hrdata_2_17, S => - \hslave_0[0]\, Y => N_5274); - - \r.hmaster_0_0_RNIA71OJ[0]\ : MX2 - port map(A => N_4590, B => N_6483, S => \hmaster_0[0]\, Y - => \haddr[12]\); - - \r.hready\ : DFN1 - port map(D => hready_RNICLR2, CLK => lclk_c, Q => hready_2); - - \r.hmasterd_RNIB28G[1]\ : MX2 - port map(A => hwdata_1(12), B => hwdata_2_9, S => - \hmasterd[1]\, Y => N_6516); - - \r.hslave_RNITTUF8[2]\ : OAI1 - port map(A => N_417_0, B => N_475, C => N_572, Y => - hrdata_0(27)); - - \r.hslave_0_0_RNIQ6KC[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_3_16, C => N_650, - Y => N_602); - - \r.hrdatas_RNITFBG[28]\ : AOI1B - port map(A => \hrdatas[28]\, B => N_657, C => N_572, Y => - \hrdata_1_0[28]\); - - \r.hmaster_2_RNIJ62A1[1]\ : MX2C - port map(A => hbusreq_i_3, B => hbusreq_i_3_0, S => - \hmaster_2[1]\, Y => N_4574); - - \r.hmasterd_1_RNIFHN9[1]\ : MX2 - port map(A => hwdata_0(27), B => hwdata_1(27), S => - \hmasterd_1[1]\, Y => N_6531); - - \r.hmaster_RNIG905J[1]\ : NOR2 - port map(A => \hmaster[1]\, B => haddr_3_4, Y => N_4584); - - \r.hslave_RNIB7S7[0]\ : OR3B - port map(A => \hslave[0]\, B => hrdata_3_22, C => N_650, Y - => N_535); - - \r.hslave_RNIQMKAG[2]\ : MX2C - port map(A => N_485, B => N_6350, S => \hslave[2]\, Y => - N_493); - - \r.hslave_0_0_RNICQ9AL[2]\ : MX2C - port map(A => N_486, B => N_6366, S => \hslave_0[2]\, Y => - N_494); - - \r.haddr[4]\ : DFN1E1 - port map(D => haddr_1(4), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr_3[4]\); - - \r.hmasterd_0_RNIFE8S[0]\ : MX2 - port map(A => N_4723, B => N_6523, S => \hmasterd_0[0]\, Y - => hwdata(19)); - - \r.hslave_RNI5BG9D[2]\ : MX2C - port map(A => N_472, B => N_6363, S => \hslave[2]\, Y => - N_476); - - \r.hslave_0_0_RNIOHPA[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_2_5, C => N_650, Y - => N_587); - - \r.defslv_RNI7VEF\ : OR2B - port map(A => N_569, B => N_568, Y => hresp_0(0)); - - \r.cfgsel_RNIIS83_1\ : NOR2 - port map(A => cfgsel, B => N_654, Y => N_663); - - \r.hmasterlock_RNO_1\ : AO1A - port map(A => \iosn_0[93]\, B => hmastlock, C => hlock_m, Y - => hmasterlock_2_0); - - \r.hrdatas_RNO[14]\ : OR3C - port map(A => N_6471, B => N_43, C => N_49, Y => - \hrdatas_RNO[14]\); - - \r.hmaster_0_0_RNICQIJ44[1]\ : OR2A - port map(A => \arb_1\, B => \hmaster_0_0_RNIFCVH1_0[1]\, Y - => \l1_0_m[1]\); - - \r.hrdatas[26]\ : DFN1 - port map(D => \haddr_RNI726O[5]\, CLK => lclk_c, Q => - \hrdatas[26]\); - - \r.hmasterd_0_RNID9N9[1]\ : MX2 - port map(A => hwdata_1(19), B => hwdata_2_16, S => - \hmasterd_0[1]\, Y => N_6523); - - \r.hmasterd_1_RNITFJ7[1]\ : MX2 - port map(A => hwdata_1(7), B => hwdata_2_4, S => - \hmasterd_1[1]\, Y => N_6511); - - \r.hmaster_RNIUUASR[1]\ : NOR2A - port map(A => htrans_3(1), B => \hmaster[1]\, Y => N_4577); - - \r.hmaster_0_0_RNIL72OJ[0]\ : MX2 - port map(A => N_4592, B => N_6485, S => \hmaster_0[0]\, Y - => \haddr[14]\); - - \r.hslave_0_0_RNI5CPIC[2]\ : MX2C - port map(A => N_469, B => N_6354, S => \hslave_0[2]\, Y => - N_473); - - \r.hslave_0_0_RNI48486[2]\ : AO1A - port map(A => N_417, B => N_489, C => N_581, Y => - hrdata_2_10); - - \r.hmaster_2_RNISRDB[1]\ : NOR2B - port map(A => hburst_0(1), B => \haddr[5923]\, Y => - \hburst[1]\); - - \r.hrdatas_RNO[17]\ : AO1C - port map(A => N_6470, B => \haddr_3[4]\, C => N_6477, Y => - \hrdatas_RNO[17]\); - - \r.hmaster_1[1]\ : DFN1 - port map(D => N_5627_i, CLK => lclk_c, Q => \hmaster_1[1]\); - - \r.hslave_0_0_RNIDH116[2]\ : MX2C - port map(A => N_481, B => N_6345, S => \hslave_0[2]\, Y => - N_489); - - \r.hmasterd_0_RNIARA91[0]\ : OR2B - port map(A => brmw_i, B => hwdata(15), Y => hwdata_m_0_3); - - \r.hmasterd_0_RNI1U6S[0]\ : MX2C - port map(A => N_4734, B => N_6602, S => \hmasterd_0[0]\, Y - => hwdata(30)); - - \r.hslave_0_0_RNIAJRUB[0]\ : MX2 - port map(A => hrdata_0(6), B => hrdata_1(6), S => - \hslave_0[0]\, Y => N_6341); - - \r.hmaster_0_0_RNI8U5A71_0[0]\ : NOR2 - port map(A => \haddr[26]\, B => \haddr[27]\, Y => - un51_ioen_NE_10_3); - - \r.hslave_RNINAV2[1]\ : XNOR2 - port map(A => \hslave[1]\, B => \hslave[2]\, Y => N_393); - - \r.hslave_RNIH73NG[2]\ : AO1C - port map(A => N_417_0, B => N_493, C => N_599, Y => - hrdata_0(15)); - - \r.hslave_0_0_RNIJJQT6[0]\ : MX2 - port map(A => hrdata_1(8), B => hrdata_2_8, S => - \hslave_0[0]\, Y => N_6343); - - \r.hslave_0_0_RNIKG9G[0]\ : OR3 - port map(A => \hslave_0[0]\, B => hready_0, C => N_643, Y - => N_648); - - \r.hslave[1]\ : DFN1 - port map(D => \hslave_RNO[1]\, CLK => lclk_c, Q => - \hslave[1]\); - - \r.hslave_0_0_RNIEL881_2[0]\ : NOR2 - port map(A => hready_1_iv_0_o2_0, B => N_660, Y => - \iosn_1[93]\); - - \r.hmasterd_0_RNI7UP5[1]\ : OA1C - port map(A => bo_5842_d_0, B => data_0_d0, C => - \hmasterd_0[1]\, Y => N_4709); - - \r.cfgsel_0_0\ : DFN1 - port map(D => cfgsel_RNIQIMCBC, CLK => lclk_c, Q => - cfgsel_0); - - \r.hmaster_0_0_RNIS83UE2[0]\ : OR3B - port map(A => \haddr[28]\, B => un51_ioen_NE_6, C => - \haddr[29]\, Y => un271_ioen_NE); - - \r.hslave_RNIHE0UG[0]\ : MX2C - port map(A => N_95_i_0, B => hrdata_3_24, S => \hslave[0]\, - Y => N_6359); - - \r.haddr_RNIEOPJ[8]\ : NOR3B - port map(A => N_6469, B => hrdatas6_0_a5_1, C => N_6474, Y - => hrdatas6); - - \r.hmaster_0_0_RNI4U71R2[0]\ : OR2A - port map(A => \hwrite\, B => brmw_1, Y => hwrite_m_0_0); - - \r.hmasterd_RNIQ0BN1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6601, C => N_667, Y => - hwdata(29)); - - \r.hmaster_RNITJMPR9[0]\ : MX2B - port map(A => \hmaster[0]\, B => \nhmaster_1_i[0]\, S => - \iosn_1[93]\, Y => \hmaster_3[0]\); - - \r.hmaster_2_RNI3U8H[1]\ : MX2C - port map(A => hwrite_0, B => hwrite_1, S => \hmaster_2[1]\, - Y => N_6503); - - \r.hmaster_1_RNI2RRB[1]\ : MX2 - port map(A => haddr_1(12), B => haddr_2(12), S => - \hmaster_1[1]\, Y => N_6483); - - \r.hslave_0_0_RNIQ8318[0]\ : AO1B - port map(A => N_6351, B => N_663, C => \hrdata_1_1[16]\, Y - => hrdata(16)); - - \r.hmasterd_RNIM9J41[0]\ : MX2 - port map(A => N_4710, B => N_6510, S => \hmasterd[0]\, Y - => hwdata(6)); - - \r.hmasterd_0_RNI3C4T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6531, C => N_206, Y - => hwdata(27)); - - \r.hmaster_RNIBGOAQ[0]\ : MX2C - port map(A => N_4573, B => N_4574, S => \hmaster[0]\, Y => - \un34_haddr[0]\); - - \r.hmasterd[0]\ : DFN1E1 - port map(D => \hmaster[0]\, CLK => lclk_c, E => \iosn[93]\, - Q => \hmasterd[0]\); - - \r.hmaster_RNISUK5O[0]\ : MX2C - port map(A => N_4611, B => N_4651, S => \hmaster[0]\, Y => - hsize(0)); - - \r.defslv_RNIQLE4\ : OR3B - port map(A => \htrans_0[1]\, B => defslv, C => cfgsel_0, Y - => N_568); - - \r.hrdatas[1]\ : DFN1 - port map(D => \hrdatas_RNO[1]\, CLK => lclk_c, Q => - \hrdatas[1]\); - - \r.hmaster_0_0_RNIGMOHJ[0]\ : MX2 - port map(A => N_4587, B => N_4627, S => \hmaster_0[0]\, Y - => haddr_2(9)); - - \r.hmaster_1_RNI68U8[1]\ : MX2 - port map(A => haddr_0(5), B => haddr_1(5), S => - \hmaster_1[1]\, Y => N_4623); - - \r.hslave_1_RNIEPVG[0]\ : OR2B - port map(A => hrdata_3_6, B => N_664, Y => N_626); - - \r.hmasterd_0_RNI8RKH[1]\ : NOR2 - port map(A => hwdata_0(15), B => \hmasterd_0[1]\, Y => - N_4719); - - \r.hrdatas[6]\ : DFN1 - port map(D => \hrdatas_RNO[6]\, CLK => lclk_c, Q => - \hrdatas[8]\); - - \r.hslave_0_0_RNI8GTUI[2]\ : MX2C - port map(A => N_470, B => N_6355, S => \hslave_0[2]\, Y => - N_474); - - \r.cfgsel\ : DFN1 - port map(D => cfgsel_RNIQIMCBC, CLK => lclk_c, Q => cfgsel); - - \r.hmaster_RNITG6GN[1]\ : AO1 - port map(A => lb_0_sqmuxa_1, B => htrans_0_sqmuxa_2, C => - \hmaster[1]\, Y => N_4576); - - \r.hslave_1_RNITDPA[0]\ : MX2C - port map(A => hrdata_1(24), B => hrdata_2_24, S => - \hslave_1[0]\, Y => N_5281); - - \r.hmaster_0_0_RNI8U5A71[0]\ : NOR2B - port map(A => \haddr[26]\, B => \haddr[27]\, Y => - un2_ioarea_7); - - \r.hmaster_2_RNIICC5[1]\ : OR2A - port map(A => \hmaster_2[1]\, B => hsize_0(1), Y => N_4652); - - \r.hslave_RNI1C8C1[2]\ : AO1D - port map(A => N_492, B => N_417, C => \hrdata_1_0[13]\, Y - => hrdata(13)); - - \r.hrdatas[5]\ : DFN1 - port map(D => \hrdatas_RNO[5]\, CLK => lclk_c, Q => - \hrdatas[5]\); - - \r.hmaster_2_RNI21V9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(14), Y => N_4592); - - \r.haddr_RNI726O_0[5]\ : OR2 - port map(A => N_6474, B => N_6471, Y => N_48); - - \r.hslave_1_RNIVMUA[0]\ : OR2B - port map(A => hrdata_4_16, B => N_664, Y => N_603); - - \r.hslave_0_0_RNINT6S7[2]\ : MX2C - port map(A => N_5287, B => N_6365, S => \hslave_0[2]\, Y - => N_5355); - - \r.hslave_RNID7K5[0]\ : MX2 - port map(A => hrdata_3_23, B => hrdata_4_23, S => - \hslave[0]\, Y => N_5280); - - \r.hmaster_0_0_RNIKE9R[1]\ : OAI1 - port map(A => \hburst[1]\, B => \hburst[2]\, C => - arb_0_sqmuxa_1_a1_0, Y => arb_0_sqmuxa_1_a1_1); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.hmaster_RNITDJ134[0]\ : MX2 - port map(A => arb_0_sqmuxa_1, B => \un34_haddr[0]\, S => - arb_1_sqmuxa_1_i, Y => \arb_1\); - - \r.hmaster_RNI5BAPJ[0]\ : MX2 - port map(A => N_4591, B => N_6484, S => \hmaster[0]\, Y => - \haddr[13]\); - - \r.hmasterd[1]\ : DFN1E1 - port map(D => \hmaster[1]\, CLK => lclk_c, E => \iosn[93]\, - Q => \hmasterd[1]\); - - \r.haddr_RNI726O[5]\ : NOR2A - port map(A => N_6461, B => N_6471, Y => \haddr_RNI726O[5]\); - - \r.hslave_1_RNIGPVG[0]\ : OR2B - port map(A => hrdata_4_8, B => N_664, Y => N_623); - - \r.hrdatam_RNISUFD[24]\ : MX2C - port map(A => \hrdatam[24]\, B => \hrdatas[24]\, S => - cfga11, Y => N_478); - - \r.hslave_RNIQ9BQ7[0]\ : MX2 - port map(A => hrdata(27), B => hrdata_1(27), S => - \hslave[0]\, Y => N_6362); - - \r.hmaster_1_RNI6BSB[1]\ : MX2 - port map(A => haddr_0(14), B => haddr_1(14), S => - \hmaster_1[1]\, Y => N_6485); - - \r.hrdatam[27]\ : DFN1 - port map(D => \hrdatam_1[28]\, CLK => lclk_c, Q => - \hrdatam[28]\); - - \r.hslave_0_0_RNIT5JN[0]\ : AOI1B - port map(A => hrdata(18), B => N_664, C => N_580, Y => - \hrdata_0_0[18]\); - - \r.hmaster_0_0_RNI4M5D71[0]\ : NOR2B - port map(A => \haddr[20]\, B => \haddr[21]\, Y => - un2_ioarea_4); - - \r.hslave_0_0_RNI5L2OC[2]\ : NOR2A - port map(A => N_473, B => N_417_0, Y => N_264_0); - - \r.hslave_1_RNI8TSLF[0]\ : AO1B - port map(A => N_6336, B => N_663, C => \hrdata_1_0_1[1]\, Y - => hrdata(1)); - - \r.hmaster_RNIED90N1[0]\ : NOR3B - port map(A => \hmaster_0_0_RNIFG08O[1]\, B => - arb_0_sqmuxa_1_0, C => \htrans[0]\, Y => arb_0_sqmuxa_1); - - \r.haddr_RNIAOPJ_0[6]\ : OR2A - port map(A => N_6468, B => N_6467, Y => N_6471); - - \r.hrdatas_RNO_0[29]\ : OR2 - port map(A => N_6474, B => N_6470, Y => N_6464); - - \r.hrdatas_RNIPB57[26]\ : OR2B - port map(A => \hrdatas[26]\, B => N_657, Y => N_525); - - \r.hmaster_RNIS83UE2[0]\ : NOR3C - port map(A => \hsel_i[0]\, B => \haddr[30]\, C => - un2_ioarea_8, Y => un2_ioarea_14); - - \r.hmaster_0_0_RNIJC37J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_2(23), Y => N_4601); - - \r.hmasterd_0_RNIK79E[0]\ : MX2 - port map(A => N_4709, B => N_6577, S => \hmasterd_0[0]\, Y - => hwdata(5)); - - \r.hmasterd_1_RNIROF8[1]\ : OR2A - port map(A => hwdata_2_1, B => \hmasterd_1[1]\, Y => N_4708); - - \r.hmasterd_0_RNIKQ8S[0]\ : MX2C - port map(A => N_4732, B => N_6600, S => \hmasterd_0[0]\, Y - => hwdata(28)); - - \r.hslave_0_0_RNI2KMN7[2]\ : AO1A - port map(A => N_417, B => N_488, C => N_581, Y => - hrdata_2_9); - - \r.hrdatas[4]\ : DFN1 - port map(D => \haddr_RNI726O[6]\, CLK => lclk_c, Q => - \hrdatas[9]\); - - \r.hmaster_0_0_RNI373TN[1]\ : OR3C - port map(A => nbo_5_0(0), B => \un34_haddr_1[4]\, C => - un91_nbo_i_0, Y => N_4578_i); - - \r.hmasterlock_RNI2TEU6\ : OA1 - port map(A => arb_0_sqmuxa_1_a1_1, B => htrans_tz(1), C => - arb_0_sqmuxa_0, Y => arb_0_sqmuxa_1_0); - - \r.hmasterd_0_RNIK0F8[1]\ : NOR2 - port map(A => \hmasterd_0[1]\, B => N_467, Y => N_6553); - - \r.hslave_RNI4JL96[0]\ : MX2 - port map(A => hrdata_1(22), B => hrdata_2_22, S => - \hslave[0]\, Y => N_6357); - - \r.hmaster_0_0_RNIAA9AC7_0[0]\ : OR3C - port map(A => un51_ioen_NE_10_4, B => un51_ioen_NE_10_5, C - => un315_ioen_NE_1, Y => \un315_ioen_NE\); - - \r.hslave_0_0_RNIHP116[2]\ : MX2C - port map(A => N_483, B => N_6347, S => \hslave_0[2]\, Y => - N_491); - - \r.hmasterd_0_RNI968S[0]\ : MX2 - port map(A => N_4720, B => N_6520, S => \hmasterd_0[0]\, Y - => hwdata(16)); - - \r.hmaster_0_0_RNIS447J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_2(26), Y => N_4604); - - \r.hmasterd_0_RNI6U7S[0]\ : MX2 - port map(A => N_4719, B => N_6519, S => \hmasterd_0[0]\, Y - => hwdata(15)); - - \r.hmasterd_0_RNIIIB9[1]\ : OR3A - port map(A => \un1_acdm_3_0_a2_0[55]\, B => \hmasterd_0[0]\, - C => \hmasterd_0[1]\, Y => N_6404); - - \r.defslv\ : DFN1 - port map(D => defslv_RNO, CLK => lclk_c, Q => defslv); - - \r.hmasterd_0_RNIE3LH[1]\ : OR2A - port map(A => hwdata_0(26), B => \hmasterd_0[1]\, Y => - N_4730); - - \r.hrdatas_RNIG3AG[12]\ : AOI1B - port map(A => \hrdatas[12]\, B => N_657, C => N_594, Y => - \hrdata_1_0[12]\); - - \r.hmaster_0_0_RNI9CME71[0]\ : NOR2B - port map(A => \haddr[28]\, B => \haddr[29]\, Y => - un2_ioarea_8); - - \r.haddr[7]\ : DFN1E1 - port map(D => haddr_2(7), CLK => lclk_c, E => \iosn[93]\, Q - => \haddr[7]\); - - \r.hmaster_0_0_RNIUHG1F2[0]\ : NOR3C - port map(A => \haddr[13]\, B => \haddr[12]\, C => - un2_ioarea_1, Y => un2_ioarea_10); - - \r.hslave_1_RNI9DHH[0]\ : MX2 - port map(A => hrdata_1(13), B => hrdata_2_13, S => - \hslave_1[0]\, Y => N_6348); - - \r.hmaster_RNIEFUDQ9[0]\ : OAI1 - port map(A => \un1_nhmaster_0_sqmuxa_1\, B => \hmaster[0]\, - C => \bco_msb_1_i_m[0]\, Y => \nhmaster_1_i[0]\); - - \r.hslave_RNIH6N68[2]\ : AO1A - port map(A => N_417, B => N_490, C => N_581, Y => - hrdata_2_11); - - \r.hmasterd_1_RNIIQUU[1]\ : OR2B - port map(A => N_521, B => N_520, Y => hwdata_1(9)); - - \r.haddr[5]\ : DFN1E1 - port map(D => haddr_2(5), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[5]\); - - \r.hrdatas_RNO[12]\ : OR3B - port map(A => N_48, B => \hrdatas_0_0_0[12]\, C => - \haddr_RNI726O[5]\, Y => \hrdatas_RNO[12]\); - - \r.hmaster_0_0_RNIFV4G71[0]\ : NOR2B - port map(A => \haddr[14]\, B => \haddr[15]\, Y => - un2_ioarea_1); - - \r.haddr_RNIAOPJ[6]\ : OR2A - port map(A => N_6469, B => N_6467, Y => N_6470); - - \r.hslave_RNIREVV[2]\ : AO1C - port map(A => N_417_0, B => N_465, C => N_525, Y => - hrdata_0(26)); - - \r.hslave_0_0_RNI40JB7[0]\ : MX2C - port map(A => hrdata_2_30, B => hrdata_3_30, S => - \hslave_0[0]\, Y => N_6365); - - \r.hslave_0_0_RNI1ESD9[2]\ : AO1A - port map(A => N_417_0, B => N_487, C => N_581, Y => - hrdata_0(7)); - - \r.hmaster_0_0_RNISA5LJ[0]\ : MX2 - port map(A => N_4599, B => N_6492, S => \hmaster_0[0]\, Y - => \haddr[21]\); - - \r.hmaster_0_0_RNI070OJ[0]\ : MX2C - port map(A => N_4588, B => N_6481, S => \hmaster_0[0]\, Y - => haddr_0(10)); - - \r.hrdatas_RNO[31]\ : AO1C - port map(A => N_6470, B => \haddr_3[4]\, C => N_48, Y => - \hrdatas_RNO[31]\); - - \r.hmaster_RNIG6AA[1]\ : MX2 - port map(A => haddr_0(17), B => haddr_1(17), S => - \hmaster[1]\, Y => N_6488); - - \r.hrdatas[13]\ : DFN1 - port map(D => \hrdatas_RNO[13]\, CLK => lclk_c, Q => - \hrdatas[13]\); - - \r.hmaster_0_0_RNI8B0OJ[0]\ : MX2 - port map(A => N_4598, B => N_6288, S => \hmaster_0[0]\, Y - => \haddr[20]\); - - \r.hmaster_0_0_RNIDS27J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_0(21), Y => N_4599); - - \r.hslave_RNIVIN88[2]\ : AO1A - port map(A => N_417_0, B => N_490, C => N_581, Y => - hrdata_0(11)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.hrdatam[14]\ : DFN1 - port map(D => \hrdatam_1[14]\, CLK => lclk_c, Q => - \hrdatam[14]\); - - \r.hmasterlock_RNO_3\ : NOR3 - port map(A => \hmaster_3[1]\, B => hlock, C => - \hmaster_3[0]\, Y => hlock_m); - - \r.hmasterd_0_RNISKGI[1]\ : OR3A - port map(A => \un1_acdm_3_0_a3_0_0[71]_net_1\, B => - \hmasterd_0[0]\, C => \hmasterd_0[1]\, Y => N_94); - - \r.cfgsel_RNI2SA68\ : MX2C - port map(A => \un34_hready[33]\, B => N_4904, S => cfgsel, - Y => hrdata(30)); - - \r.hslave_RNIA7S7[0]\ : OR3B - port map(A => \hslave[0]\, B => hrdata_4_21, C => N_650, Y - => N_576); - - \r.hmaster_RNI9NNUS4[0]\ : OA1A - port map(A => hbusreq_i_3_0, B => \bco_msb_1[1]\, C => - \arb_1\, Y => \un1_nhmaster_0_sqmuxa_1\); - - \r.hslave_0_0_RNIJ0HK7[2]\ : OR2B - port map(A => N_5342, B => N_393, Y => \un34_hready[20]\); - - \r.hrdatas[15]\ : DFN1 - port map(D => \hrdatas_RNO[15]\, CLK => lclk_c, Q => - \hrdatas[15]\); - - \r.hslave[2]\ : DFN1 - port map(D => \hslave_RNIQRGJS9[2]\, CLK => lclk_c, Q => - \hslave[2]\); - - \r.hmaster_RNI1UG9O[0]\ : MX2C - port map(A => N_4578_i, B => N_4618, S => \hmaster[0]\, Y - => haddr_1(0)); - - \r.hmaster_0_0_RNI4QOPNE[1]\ : OR2B - port map(A => \nhmaster_1_iv_0[1]\, B => \bco_msb_1_m[1]\, - Y => \nhmaster_1[1]\); - - \r.hmasterd_0_RNI972T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6583, C => N_523, Y - => hwdata_1(11)); - - \hrdata_1_0_a2_0[1]\ : NAND2 - port map(A => N_663, B => N_6336, Y => N_546); - - \r.hmasterd_1_RNIDDN9[1]\ : MX2 - port map(A => hwdata_1(16), B => hwdata_2_13, S => - \hmasterd_1[1]\, Y => N_6520); - - \r.hslave_RNIJJK5[0]\ : MX2C - port map(A => hrdata_3_26, B => hrdata_4_26, S => - \hslave[0]\, Y => N_464); - - \r.hmaster_2_RNIJ50AJ[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(28), Y => N_4606); - - \r.hmasterd_RNI9LRF1[0]\ : MX2 - port map(A => N_4716, B => N_6516, S => \hmasterd[0]\, Y - => hwdata(12)); - - \r.hmaster_2_RNINQ6TO[1]\ : NOR2A - port map(A => hbusreq, B => \hmaster_2[1]\, Y => N_4573); - - \r.hslave_0_0_RNIN22V6[0]\ : MX2 - port map(A => hrdata_1(16), B => hrdata_2_16, S => - \hslave_0[0]\, Y => N_6351); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.hslave_RNIIETLE[0]\ : AO1B - port map(A => N_6356, B => N_663, C => \hrdata_0_0[21]\, Y - => hrdata_1(21)); - - \r.hmasterd_RNI9MTU[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6512, C => N_6404, Y - => hwdata(8)); - - \r.hmasterd_1_RNIC5N9[1]\ : MX2 - port map(A => hwdata_0(24), B => hwdata_1(24), S => - \hmasterd_1[1]\, Y => N_6528); - - \r.hmaster_RNIVH6MJ[0]\ : MX2 - port map(A => N_4595, B => N_6488, S => \hmaster[0]\, Y => - \haddr[17]\); - - \r.hmaster_RNI76MNJ[0]\ : MX2 - port map(A => N_4608, B => N_6501, S => \hmaster[0]\, Y => - \haddr[30]\); - - \r.hslave_1_RNIPNSDI[0]\ : MX2C - port map(A => N_90_i_0, B => hrdata_1(20), S => - \hslave_1[0]\, Y => N_6355); - - \r.hslave_1_RNI33VA[0]\ : OR2B - port map(A => hrdata_3_29, B => N_664, Y => N_607); - - \r.hrdatam[12]\ : DFN1 - port map(D => \hrdatam_1[13]\, CLK => lclk_c, Q => - \hrdatam[13]\); - - \r.defslv_RNILUH3\ : NOR2 - port map(A => N_643, B => N_403, Y => N_651_2); - - \r.hready_RNICLR2\ : NOR3B - port map(A => \htrans_0[1]\, B => N_403, C => hready_2, Y - => hready_RNICLR2); - - \r.hslave_RNIROF18[2]\ : MX2C - port map(A => N_471, B => N_6362, S => \hslave[2]\, Y => - N_475); - - \r.hslave_RNI5AQI[0]\ : AOI1B - port map(A => hrdata(21), B => N_664, C => N_576, Y => - \hrdata_0_0[21]\); - - \r.hslave_0_0_RNIIHJV[0]\ : NOR3C - port map(A => N_622, B => N_620, C => N_623, Y => - \hrdata_0_0_1[8]\); - - \r.hslave_RNIEKIAI_0[1]\ : NOR2B - port map(A => \hrdata_i_0_0[25]\, B => N_628, Y => N_78_0); - - \r.hslave_RNIEKIAI[1]\ : NOR2B - port map(A => \hrdata_i_0_0[25]\, B => N_628, Y => N_78); - - \r.hslave_1_RNI9TGO7[0]\ : MX2C - port map(A => hrdata(11), B => hrdata_1(11), S => - \hslave_1[0]\, Y => N_6346); - - \r.haddr_RNIG41B_0[8]\ : NOR3C - port map(A => \haddr[9]\, B => \haddr[8]\, C => \haddr[10]\, - Y => hrdatas6_0_a5_1); - - \r.hmaster_0_0_RNI49NBT4[1]\ : OR3C - port map(A => hbusreq, B => \bco_msb_1_i_m_0[0]\, C => - \arb_1\, Y => \bco_msb_1_i_m[0]\); - - \r.hmasterd_RNIC68G[1]\ : MX2 - port map(A => hwdata(13), B => hwdata_0(13), S => - \hmasterd[1]\, Y => N_6585); - - \r.defslv_RNIUJI\ : OR2 - port map(A => defslv, B => cfgsel, Y => N_403); - - \r.hmaster_2_RNI0RH8[1]\ : NOR2B - port map(A => \hmaster_2[1]\, B => \hmaster[0]\, Y => - \haddr[5923]\); - - \r.hmaster_2[1]\ : DFN1 - port map(D => N_5627_i, CLK => lclk_c, Q => \hmaster_2[1]\); - - \r.hslave_0_0_RNICA1J9[0]\ : AO1B - port map(A => N_6353, B => N_663, C => \hrdata_0_0[18]\, Y - => hrdata_1(18)); - - \r.hrdatas_RNI2QP3[1]\ : NOR2B - port map(A => \hrdatas[1]\, B => N_657, Y => N_545); - - \r.hmaster_1_RNIE8U8[1]\ : MX2 - port map(A => haddr_0(9), B => haddr_1(9), S => - \hmaster_1[1]\, Y => N_4627); - - \r.haddr_RNI726O[3]\ : AO1B - port map(A => \haddr[3]\, B => \haddr[2]\, C => N_6476, Y - => N_43); - - \r.hslave_RNO[1]\ : NOR2A - port map(A => rstn, B => \hslave_3[1]\, Y => - \hslave_RNO[1]\); - - \r.hrdatas_RNO_0[14]\ : OR2 - port map(A => N_6470, B => N_6461, Y => N_49); - - \r.hmaster_RNI3JPNJ[0]\ : MX2 - port map(A => N_4605, B => N_6498, S => \hmaster[0]\, Y => - \haddr[27]\); - - \r.hmaster_0_0_RNIMK37J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_0(24), Y => N_4602); - - \r.hslave_0_0_RNIJENKL[2]\ : AO1C - port map(A => N_417, B => N_494, C => N_609, Y => - hrdata_0(31)); - - \r.hmaster_RNI76CN2J[0]\ : NOR2 - port map(A => \hmbsel_2[0]\, B => \hmbsel_1[0]\, Y => - hmbsel(0)); - - \r.hrdatas[17]\ : DFN1 - port map(D => \hrdatas_RNO[17]\, CLK => lclk_c, Q => - \hrdatas[17]\); - - \r.hmasterd_RNIRK4E[1]\ : MX2C - port map(A => hwdata(3), B => hwdata_0(3), S => - \hmasterd[1]\, Y => N_6304); - - \r.hslave_RNI9A16[0]\ : OR3B - port map(A => \hslave[0]\, B => hrdata_3_4, C => N_650, Y - => N_583); - - \r.hslave_0_0_RNIEL881[0]\ : NOR2 - port map(A => hready_1_iv_0_o2_0, B => N_660, Y => - \iosn[93]\); - - \r.hslave_0_0_RNIT1V6I[2]\ : OR2B - port map(A => N_5339, B => N_393, Y => \un34_hready[17]\); - - \r.hmasterd_0_RNIUKF8[1]\ : NOR2 - port map(A => hwdata_0(7), B => \hmasterd_0[1]\, Y => - N_4711); - - \r.hmaster_0_0_RNI6JC8R9[0]\ : OR2B - port map(A => \un315_ioen_NE\, B => un271_ioen_NE, Y => - \hmbsel_2[0]\); - - \r.hmasterd_0_RNI6NKH[1]\ : NOR2 - port map(A => hwdata_0(14), B => \hmasterd_0[1]\, Y => - N_4718); - - \r.hmaster_0_0_RNIBSHNE2[0]\ : NOR3A - port map(A => un51_ioen_NE_10_1, B => \haddr[21]\, C => - \haddr[20]\, Y => un51_ioen_NE_10_4); - - \r.hmasterd_RNIPK4E[1]\ : MX2 - port map(A => hwdata(1), B => hwdata_0(1), S => - \hmasterd[1]\, Y => N_6573); - - \r.hslave_0_0_RNIS6KC[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_4_18, C => N_650, - Y => N_580); - - \r.hmasterd_0_RNIF4VF1[0]\ : OR2A - port map(A => hwdata(15), B => N_6550, Y => hwdata_m_8); - - \r.cfgsel_RNI0NABBC\ : MX2 - port map(A => cfgsel, B => un2_ioarea, S => \iosn_1[93]\, Y - => N_5557); - - \r.hslave_0_0_RNI2T0G5[0]\ : MX2C - port map(A => hrdata_1(12), B => hrdata_2_12, S => - \hslave_0[0]\, Y => N_6347); - - \r.hmaster_0_0_RNI76CA71[0]\ : NOR2B - port map(A => \haddr[22]\, B => \haddr[23]\, Y => - un2_ioarea_5); - - \r.haddr_RNIT9C4[5]\ : OR2B - port map(A => \haddr[5]\, B => \haddr_3[4]\, Y => N_6474); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Clk_divider is - - port( reset_i_0_1 : in std_logic; - clk49_152MHz_c : in std_logic; - reset_i_0_0 : in std_logic; - clk49_152MHz_c_0 : in std_logic; - clk_div_0 : out std_logic; - clk_div_1 : out std_logic; - clk_div_2 : out std_logic; - clk_int : out std_logic; - clk_div_3 : out std_logic - ); - -end Clk_divider; - -architecture DEF_ARCH of Clk_divider is - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component BUFF - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal clk_int_net_1, N_157, \cpt1[1]_net_1\, - \cpt1[0]_net_1\, N_149, \cpt1[3]_net_1\, - \DWACT_FINC_E[0]\, N_126, \cpt1[8]_net_1\, - \DWACT_FINC_E[4]\, N_111, \DWACT_FINC_E[7]\, - \DWACT_FINC_E[6]\, un1_cpt1_28, un1_cpt1_20, un1_cpt1_19, - un1_cpt1_26, un1_cpt1_27, un1_cpt1_18, un1_cpt1_17, - un1_cpt1_23, un1_cpt1_12, un1_cpt1_11, un1_cpt1_22, - un1_cpt1_2, un1_cpt1_1, un1_cpt1_15, un1_cpt1_14, - \cpt1[24]_net_1\, \cpt1[21]_net_1\, \cpt1[6]_net_1\, - \cpt1[4]_net_1\, un1_cpt1_10, un1_cpt1_8, - \cpt1[22]_net_1\, \cpt1[19]_net_1\, un1_cpt1_6, - \cpt1[10]_net_1\, \cpt1[7]_net_1\, un1_cpt1_4, - \cpt1[29]_net_1\, \cpt1[26]_net_1\, \cpt1[11]_net_1\, - \cpt1[31]_net_1\, \cpt1[27]_net_1\, \cpt1[15]_net_1\, - \cpt1[18]_net_1\, \cpt1[9]_net_1\, \cpt1[12]_net_1\, - \cpt1[2]_net_1\, \cpt1[25]_net_1\, \cpt1[28]_net_1\, - \cpt1[13]_net_1\, \cpt1[16]_net_1\, \cpt1[5]_net_1\, - \cpt1[30]_net_1\, \cpt1[20]_net_1\, \cpt1[23]_net_1\, - \cpt1[14]_net_1\, \cpt1[17]_net_1\, \clk_int_RNO\, - \cpt1_3[6]\, I_31_6, \cpt1_3[5]\, I_24_8, \cpt1_3[4]\, - I_20_7, \cpt1_3[3]\, I_13_11, \cpt1_3[0]\, \cpt1_3[8]\, - I_45_3, I_5_7, I_9_7, I_38_4, I_52_3, I_56_3, I_66_3, - I_73_2, I_77_2, I_84_2, I_91_2, I_98_2, I_105_2, I_115_2, - I_122_2, I_129_2, I_136_2, I_143_2, I_156_2, I_166_2, - I_173_2, I_186_2, I_196_2, I_203_2, I_210_2, I_217_0, - I_224_0, N_4, \DWACT_FINC_E[24]\, \DWACT_FINC_E[23]\, - \DWACT_FINC_E[27]\, \DWACT_FINC_E[26]\, N_9, N_14, - \DWACT_FINC_E[25]\, N_19, \DWACT_FINC_E[29]\, - \DWACT_FINC_E[30]\, N_24, \DWACT_FINC_E[15]\, - \DWACT_FINC_E[17]\, \DWACT_FINC_E[22]\, N_31, - \DWACT_FINC_E[21]\, \DWACT_FINC_E[9]\, \DWACT_FINC_E[12]\, - \DWACT_FINC_E[20]\, N_40, \DWACT_FINC_E[13]\, - \DWACT_FINC_E[19]\, N_45, \DWACT_FINC_E[18]\, N_52, - \DWACT_FINC_E[33]\, \DWACT_FINC_E[34]\, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[5]\, N_61, \DWACT_FINC_E[28]\, - \DWACT_FINC_E[16]\, N_66, N_71, \DWACT_FINC_E[14]\, N_76, - N_81, \DWACT_FINC_E[10]\, N_88, \DWACT_FINC_E[11]\, N_93, - N_98, N_103, \DWACT_FINC_E[8]\, N_108, N_116, N_123, - \DWACT_FINC_E[3]\, N_131, N_136, N_141, \DWACT_FINC_E[1]\, - N_146, N_154, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - clk_int <= clk_int_net_1; - - un3_cpt1_I_9 : XOR2 - port map(A => N_157, B => \cpt1[2]_net_1\, Y => I_9_7); - - un3_cpt1_I_220 : AND2 - port map(A => \DWACT_FINC_E[26]\, B => \cpt1[30]_net_1\, Y - => \DWACT_FINC_E[27]\); - - \cpt1[31]\ : DFN1C1 - port map(D => I_224_0, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[31]_net_1\); - - un3_cpt1_I_213 : AND3 - port map(A => \cpt1[27]_net_1\, B => \cpt1[28]_net_1\, C - => \cpt1[29]_net_1\, Y => \DWACT_FINC_E[26]\); - - un3_cpt1_I_128 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[14]\, Y => N_71); - - \cpt1[11]\ : DFN1C1 - port map(D => I_66_3, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[11]_net_1\); - - \cpt1[23]\ : DFN1C1 - port map(D => I_156_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[23]_net_1\); - - un3_cpt1_I_136 : XOR2 - port map(A => N_66, B => \cpt1[21]_net_1\, Y => I_136_2); - - \cpt1[7]\ : DFN1C1 - port map(D => I_38_4, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[7]_net_1\); - - un3_cpt1_I_216 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[26]\, Y => N_9); - - un3_cpt1_I_111 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\); - - \cpt1[0]\ : DFN1C1 - port map(D => \cpt1_3[0]\, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[0]_net_1\); - - \cpt1_RNISQL23[7]\ : NOR3C - port map(A => un1_cpt1_18, B => un1_cpt1_17, C => - un1_cpt1_23, Y => un1_cpt1_27); - - un3_cpt1_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \cpt1[9]_net_1\, C - => \cpt1[10]_net_1\, Y => N_116); - - un3_cpt1_I_66 : XOR2 - port map(A => N_116, B => \cpt1[11]_net_1\, Y => I_66_3); - - un3_cpt1_I_146 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \cpt1[21]_net_1\, C - => \cpt1[22]_net_1\, Y => \DWACT_FINC_E[33]\); - - \cpt1_RNO[3]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_13_11, - Y => \cpt1_3[3]\); - - un3_cpt1_I_202 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \cpt1[27]_net_1\, Y => N_19); - - un3_cpt1_I_139 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \cpt1[21]_net_1\, Y - => \DWACT_FINC_E[16]\); - - \cpt1[29]\ : DFN1C1 - port map(D => I_210_2, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[29]_net_1\); - - clk_int_RNO : AX1C - port map(A => un1_cpt1_27, B => un1_cpt1_28, C => - clk_int_net_1, Y => \clk_int_RNO\); - - \cpt1[13]\ : DFN1C1 - port map(D => I_77_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[13]_net_1\); - - un3_cpt1_I_16 : AND3 - port map(A => \cpt1[0]_net_1\, B => \cpt1[1]_net_1\, C => - \cpt1[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - un3_cpt1_I_149 : AND3 - port map(A => \cpt1[0]_net_1\, B => \cpt1[1]_net_1\, C => - \cpt1[2]_net_1\, Y => \DWACT_FINC_E[34]\); - - \cpt1_RNI57UF[13]\ : NOR2 - port map(A => \cpt1[13]_net_1\, B => \cpt1[16]_net_1\, Y - => un1_cpt1_6); - - un3_cpt1_I_27 : AND2 - port map(A => \cpt1[3]_net_1\, B => \cpt1[4]_net_1\, Y => - \DWACT_FINC_E[1]\); - - \cpt1[5]\ : DFN1C1 - port map(D => \cpt1_3[5]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[5]_net_1\); - - \cpt1[19]\ : DFN1C1 - port map(D => I_122_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[19]_net_1\); - - un3_cpt1_I_20 : XOR2 - port map(A => N_149, B => \cpt1[4]_net_1\, Y => I_20_7); - - un3_cpt1_I_114 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[12]\, Y => N_81); - - \cpt1_RNIPSTO[21]\ : NOR3A - port map(A => un1_cpt1_14, B => \cpt1[24]_net_1\, C => - \cpt1[21]_net_1\, Y => un1_cpt1_22); - - un3_cpt1_I_8 : NOR2B - port map(A => \cpt1[1]_net_1\, B => \cpt1[0]_net_1\, Y => - N_157); - - un3_cpt1_I_72 : NOR2B - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y - => N_111); - - un3_cpt1_I_152 : AND3 - port map(A => \DWACT_FINC_E[34]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[29]\); - - un3_cpt1_I_162 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - Y => \DWACT_FINC_E[18]\); - - clk_int_inferred_clock_RNIIC66_0 : BUFF - port map(A => clk_int_net_1, Y => clk_div_3); - - un3_cpt1_I_155 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[33]\, Y => N_52); - - un3_cpt1_I_165 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[18]\, Y => N_45); - - un3_cpt1_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \cpt1[3]_net_1\, C - => \cpt1[4]_net_1\, Y => N_146); - - GND_i : GND - port map(Y => \GND\); - - un3_cpt1_I_115 : XOR2 - port map(A => N_81, B => \cpt1[18]_net_1\, Y => I_115_2); - - un3_cpt1_I_52 : XOR2 - port map(A => N_126, B => \cpt1[9]_net_1\, Y => I_52_3); - - un3_cpt1_I_203 : XOR2 - port map(A => N_19, B => \cpt1[28]_net_1\, Y => I_203_2); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un3_cpt1_I_206 : AND2 - port map(A => \cpt1[27]_net_1\, B => \cpt1[28]_net_1\, Y - => \DWACT_FINC_E[25]\); - - un3_cpt1_I_101 : AND2 - port map(A => \cpt1[15]_net_1\, B => \cpt1[16]_net_1\, Y - => \DWACT_FINC_E[11]\); - - un3_cpt1_I_24 : XOR2 - port map(A => N_146, B => \cpt1[5]_net_1\, Y => I_24_8); - - \cpt1_RNI4G12[2]\ : NOR2A - port map(A => \cpt1[8]_net_1\, B => \cpt1[2]_net_1\, Y => - un1_cpt1_10); - - un3_cpt1_I_31 : XOR2 - port map(A => N_141, B => \cpt1[6]_net_1\, Y => I_31_6); - - \cpt1[26]\ : DFN1C1 - port map(D => I_186_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[26]_net_1\); - - un3_cpt1_I_129 : XOR2 - port map(A => N_71, B => \cpt1[20]_net_1\, Y => I_129_2); - - \cpt1[4]\ : DFN1C1 - port map(D => \cpt1_3[4]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[4]_net_1\); - - un3_cpt1_I_5 : XOR2 - port map(A => \cpt1[0]_net_1\, B => \cpt1[1]_net_1\, Y => - I_5_7); - - clk_int_inferred_clock_RNIIC66_2 : BUFF - port map(A => clk_int_net_1, Y => clk_div_1); - - \cpt1[25]\ : DFN1C1 - port map(D => I_173_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[25]_net_1\); - - un3_cpt1_I_45 : XOR2 - port map(A => N_131, B => \cpt1[8]_net_1\, Y => I_45_3); - - \cpt1[9]\ : DFN1C1 - port map(D => I_52_3, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[9]_net_1\); - - \cpt1_RNI7FUF[14]\ : NOR2 - port map(A => \cpt1[14]_net_1\, B => \cpt1[17]_net_1\, Y - => un1_cpt1_1); - - \cpt1_RNI9NUF[15]\ : NOR2 - port map(A => \cpt1[15]_net_1\, B => \cpt1[18]_net_1\, Y - => un1_cpt1_12); - - un3_cpt1_I_91 : XOR2 - port map(A => N_98, B => \cpt1[15]_net_1\, Y => I_91_2); - - un3_cpt1_I_59 : AND3 - port map(A => \cpt1[6]_net_1\, B => \cpt1[7]_net_1\, C => - \cpt1[8]_net_1\, Y => \DWACT_FINC_E[5]\); - - \cpt1[16]\ : DFN1C1 - port map(D => I_98_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[16]_net_1\); - - un3_cpt1_I_41 : AND2 - port map(A => \cpt1[6]_net_1\, B => \cpt1[7]_net_1\, Y => - \DWACT_FINC_E[3]\); - - \cpt1[24]\ : DFN1C1 - port map(D => I_166_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[24]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - un3_cpt1_I_182 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[30]\); - - un3_cpt1_I_196 : XOR2 - port map(A => N_24, B => \cpt1[27]_net_1\, Y => I_196_2); - - \cpt1[3]\ : DFN1C1 - port map(D => \cpt1_3[3]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[3]_net_1\); - - \cpt1_RNIJ6TV[22]\ : NOR3A - port map(A => un1_cpt1_8, B => \cpt1[22]_net_1\, C => - \cpt1[19]_net_1\, Y => un1_cpt1_19); - - un3_cpt1_I_185 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[21]\, Y => N_31); - - un3_cpt1_I_172 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[19]\, Y => N_40); - - \cpt1[15]\ : DFN1C1 - port map(D => I_91_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[15]_net_1\); - - un3_cpt1_I_199 : AND2 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - Y => \DWACT_FINC_E[24]\); - - un3_cpt1_I_13 : XOR2 - port map(A => N_154, B => \cpt1[3]_net_1\, Y => I_13_11); - - un3_cpt1_I_104 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \DWACT_FINC_E[11]\, Y => N_88); - - clk_int_inferred_clock_RNIIC66 : BUFF - port map(A => clk_int_net_1, Y => clk_div_0); - - \cpt1[14]\ : DFN1C1 - port map(D => I_84_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[14]_net_1\); - - un3_cpt1_I_38 : XOR2 - port map(A => N_136, B => \cpt1[7]_net_1\, Y => I_38_4); - - un3_cpt1_I_210 : XOR2 - port map(A => N_14, B => \cpt1[29]_net_1\, Y => I_210_2); - - \cpt1[1]\ : DFN1C1 - port map(D => I_5_7, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[1]_net_1\); - - \clk_int\ : DFN1C1 - port map(D => \clk_int_RNO\, CLK => clk49_152MHz_c_0, CLR - => reset_i_0_0, Q => clk_int_net_1); - - un3_cpt1_I_173 : XOR2 - port map(A => N_40, B => \cpt1[25]_net_1\, Y => I_173_2); - - un3_cpt1_I_118 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[13]\); - - \cpt1_RNIM509[27]\ : NOR2A - port map(A => \cpt1[3]_net_1\, B => \cpt1[27]_net_1\, Y => - un1_cpt1_14); - - \cpt1_RNI1FTF[20]\ : NOR2 - port map(A => \cpt1[20]_net_1\, B => \cpt1[23]_net_1\, Y - => un1_cpt1_2); - - un3_cpt1_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \cpt1[6]_net_1\, Y => N_136); - - un3_cpt1_I_105 : XOR2 - port map(A => N_88, B => \cpt1[17]_net_1\, Y => I_105_2); - - un3_cpt1_I_217 : XOR2 - port map(A => N_9, B => \cpt1[30]_net_1\, Y => I_217_0); - - \cpt1_RNIV8UO[26]\ : NOR3A - port map(A => un1_cpt1_4, B => \cpt1[29]_net_1\, C => - \cpt1[26]_net_1\, Y => un1_cpt1_17); - - un3_cpt1_I_98 : XOR2 - port map(A => N_93, B => \cpt1[16]_net_1\, Y => I_98_2); - - un3_cpt1_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un3_cpt1_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \cpt1[5]_net_1\, Y => N_141); - - un3_cpt1_I_132 : AND3 - port map(A => \cpt1[18]_net_1\, B => \cpt1[19]_net_1\, C - => \cpt1[20]_net_1\, Y => \DWACT_FINC_E[15]\); - - \cpt1[22]\ : DFN1C1 - port map(D => I_143_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[22]_net_1\); - - \cpt1_RNO[0]\ : AOI1 - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => - \cpt1[0]_net_1\, Y => \cpt1_3[0]\); - - un3_cpt1_I_135 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[15]\, Y => N_66); - - un3_cpt1_I_97 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \cpt1[15]_net_1\, Y => N_93); - - un3_cpt1_I_223 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[27]\, Y => N_4); - - un3_cpt1_I_142 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[16]\, Y => N_61); - - \cpt1_RNIBNUF[25]\ : NOR2 - port map(A => \cpt1[25]_net_1\, B => \cpt1[28]_net_1\, Y - => un1_cpt1_8); - - un3_cpt1_I_121 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \cpt1[18]_net_1\, Y => N_76); - - un3_cpt1_I_90 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[9]\, Y => N_98); - - un3_cpt1_I_143 : XOR2 - port map(A => N_61, B => \cpt1[22]_net_1\, Y => I_143_2); - - \cpt1[12]\ : DFN1C1 - port map(D => I_73_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[12]_net_1\); - - \cpt1_RNO[6]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_31_6, Y - => \cpt1_3[6]\); - - un3_cpt1_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - un3_cpt1_I_34 : AND3 - port map(A => \cpt1[3]_net_1\, B => \cpt1[4]_net_1\, C => - \cpt1[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un3_cpt1_I_76 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \cpt1[12]_net_1\, Y => N_108); - - GND_i_0 : GND - port map(Y => GND_0); - - \cpt1_RNIMHV8[9]\ : NOR2 - port map(A => \cpt1[9]_net_1\, B => \cpt1[12]_net_1\, Y => - un1_cpt1_11); - - un3_cpt1_I_12 : AND3 - port map(A => \cpt1[0]_net_1\, B => \cpt1[1]_net_1\, C => - \cpt1[2]_net_1\, Y => N_154); - - \cpt1[2]\ : DFN1C1 - port map(D => I_9_7, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[2]_net_1\); - - \cpt1[28]\ : DFN1C1 - port map(D => I_203_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[28]_net_1\); - - \cpt1_RNO[4]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_20_7, Y - => \cpt1_3[4]\); - - un3_cpt1_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \cpt1[8]_net_1\, C - => \cpt1[9]_net_1\, Y => N_123); - - un3_cpt1_I_56 : XOR2 - port map(A => N_123, B => \cpt1[10]_net_1\, Y => I_56_3); - - un3_cpt1_I_156 : XOR2 - port map(A => N_52, B => \cpt1[23]_net_1\, Y => I_156_2); - - un3_cpt1_I_51 : NOR2B - port map(A => \cpt1[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_126); - - un3_cpt1_I_166 : XOR2 - port map(A => N_45, B => \cpt1[24]_net_1\, Y => I_166_2); - - un3_cpt1_I_108 : AND3 - port map(A => \cpt1[15]_net_1\, B => \cpt1[16]_net_1\, C - => \cpt1[17]_net_1\, Y => \DWACT_FINC_E[12]\); - - un3_cpt1_I_94 : AND2 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, Y - => \DWACT_FINC_E[10]\); - - un3_cpt1_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_131); - - un3_cpt1_I_69 : AND3 - port map(A => \cpt1[9]_net_1\, B => \cpt1[10]_net_1\, C => - \cpt1[11]_net_1\, Y => \DWACT_FINC_E[7]\); - - \cpt1_RNINGTO[7]\ : NOR3A - port map(A => un1_cpt1_6, B => \cpt1[10]_net_1\, C => - \cpt1[7]_net_1\, Y => un1_cpt1_18); - - un3_cpt1_I_159 : AND3 - port map(A => \cpt1[21]_net_1\, B => \cpt1[22]_net_1\, C - => \cpt1[23]_net_1\, Y => \DWACT_FINC_E[17]\); - - \cpt1[18]\ : DFN1C1 - port map(D => I_115_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[18]_net_1\); - - \cpt1[6]\ : DFN1C1 - port map(D => \cpt1_3[6]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[6]_net_1\); - - un3_cpt1_I_169 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \cpt1[24]_net_1\, Y => \DWACT_FINC_E[19]\); - - un3_cpt1_I_224 : XOR2 - port map(A => N_4, B => \cpt1[31]_net_1\, Y => I_224_0); - - un3_cpt1_I_87 : AND3 - port map(A => \cpt1[12]_net_1\, B => \cpt1[13]_net_1\, C - => \cpt1[14]_net_1\, Y => \DWACT_FINC_E[9]\); - - un3_cpt1_I_122 : XOR2 - port map(A => N_76, B => \cpt1[19]_net_1\, Y => I_122_2); - - un3_cpt1_I_209 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[25]\, Y => N_14); - - un3_cpt1_I_19 : NOR2B - port map(A => \cpt1[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_149); - - un3_cpt1_I_125 : AND2 - port map(A => \cpt1[18]_net_1\, B => \cpt1[19]_net_1\, Y - => \DWACT_FINC_E[14]\); - - \cpt1_RNI8034[4]\ : NOR3C - port map(A => \cpt1[6]_net_1\, B => \cpt1[4]_net_1\, C => - un1_cpt1_10, Y => un1_cpt1_20); - - un3_cpt1_I_80 : AND2 - port map(A => \cpt1[12]_net_1\, B => \cpt1[13]_net_1\, Y - => \DWACT_FINC_E[8]\); - - \cpt1_RNIU2UG[31]\ : NOR3 - port map(A => \cpt1[11]_net_1\, B => \cpt1[31]_net_1\, C - => \cpt1[1]_net_1\, Y => un1_cpt1_15); - - \cpt1_RNO[8]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_45_3, Y - => \cpt1_3[8]\); - - \cpt1_RNIJCSL2[4]\ : NOR3C - port map(A => un1_cpt1_20, B => un1_cpt1_19, C => - un1_cpt1_26, Y => un1_cpt1_28); - - un3_cpt1_I_77 : XOR2 - port map(A => N_108, B => \cpt1[13]_net_1\, Y => I_77_2); - - un3_cpt1_I_186 : XOR2 - port map(A => N_31, B => \cpt1[26]_net_1\, Y => I_186_2); - - \cpt1[27]\ : DFN1C1 - port map(D => I_196_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[27]_net_1\); - - un3_cpt1_I_83 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[8]\, Y => N_103); - - un3_cpt1_I_192 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[22]\, Y => \DWACT_FINC_E[23]\); - - \cpt1_RNII9V8[30]\ : NOR2A - port map(A => \cpt1[5]_net_1\, B => \cpt1[30]_net_1\, Y => - un1_cpt1_4); - - \cpt1[20]\ : DFN1C1 - port map(D => I_129_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[20]_net_1\); - - un3_cpt1_I_176 : AND2 - port map(A => \cpt1[24]_net_1\, B => \cpt1[25]_net_1\, Y - => \DWACT_FINC_E[20]\); - - un3_cpt1_I_195 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[23]\, Y => N_24); - - un3_cpt1_I_189 : AND3 - port map(A => \cpt1[24]_net_1\, B => \cpt1[25]_net_1\, C - => \cpt1[26]_net_1\, Y => \DWACT_FINC_E[22]\); - - un3_cpt1_I_84 : XOR2 - port map(A => N_103, B => \cpt1[14]_net_1\, Y => I_84_2); - - \cpt1_RNIO5SH1[9]\ : NOR3C - port map(A => un1_cpt1_12, B => un1_cpt1_11, C => - un1_cpt1_22, Y => un1_cpt1_26); - - \cpt1_RNO[5]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_24_8, Y - => \cpt1_3[5]\); - - \cpt1_RNI61QG1[20]\ : NOR3C - port map(A => un1_cpt1_2, B => un1_cpt1_1, C => un1_cpt1_15, - Y => un1_cpt1_23); - - \cpt1[21]\ : DFN1C1 - port map(D => I_136_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[21]_net_1\); - - \cpt1[17]\ : DFN1C1 - port map(D => I_105_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[17]_net_1\); - - clk_int_inferred_clock_RNIIC66_1 : BUFF - port map(A => clk_int_net_1, Y => clk_div_2); - - \cpt1[30]\ : DFN1C1 - port map(D => I_217_0, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[30]_net_1\); - - un3_cpt1_I_179 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[20]\, Y => \DWACT_FINC_E[21]\); - - un3_cpt1_I_73 : XOR2 - port map(A => N_111, B => \cpt1[12]_net_1\, Y => I_73_2); - - \cpt1[10]\ : DFN1C1 - port map(D => I_56_3, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[10]_net_1\); - - \cpt1[8]\ : DFN1C1 - port map(D => \cpt1_3[8]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[8]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lfr_time_management is - - port( pirq : out std_logic_vector(13 downto 12); - coarse_time_load : in std_logic_vector(31 downto 0); - next_commutation : in std_logic_vector(31 downto 0); - coarse_time : out std_logic_vector(31 downto 0); - coarse_time_i : out std_logic_vector(0 to 0); - fine_time : out std_logic_vector(16 downto 0); - clk49_152MHz_c_0 : in std_logic; - clk49_152MHz_c : in std_logic; - lclk_c : in std_logic; - soft_tick : in std_logic; - rstn_i : in std_logic; - soft_tick_3 : in std_logic; - soft_tick_2 : in std_logic; - soft_tick_1 : in std_logic; - soft_tick_0 : in std_logic; - rstn : in std_logic - ); - -end lfr_time_management; - -architecture DEF_ARCH of lfr_time_management is - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1P1C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component Clk_divider - port( reset_i_0_1 : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - reset_i_0_0 : in std_logic := 'U'; - clk49_152MHz_c_0 : in std_logic := 'U'; - clk_div_0 : out std_logic; - clk_div_1 : out std_logic; - clk_div_2 : out std_logic; - clk_int : out std_logic; - clk_div_3 : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - signal reset_i_0_1, reset_i_0_0, \flag_0\, clk_div_0, flag_1, - flag_1_sqmuxa_1, \un1_cpt_1[0]\, N_25, N_24, - \un1_cpt_0[0]\, un1_commutation_timer_3_0, - un1_commutation_timer_3_0_a2_30, s_coarse_time_1_NE, - \commutation_timer[0]_net_1\, s_coarse_time_1_NE_0, - s_coarse_time_1_NE_29, s_coarse_time_1_NE_28, - \DWACT_ADD_CI_0_g_array_4[0]\, - \DWACT_ADD_CI_0_g_array_3[0]\, - \DWACT_ADD_CI_0_pog_array_3[0]\, - \DWACT_ADD_CI_0_g_array_10[0]\, - \DWACT_ADD_CI_0_pog_array_2_1[0]\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_2[0]\, - \DWACT_ADD_CI_0_g_array_11_1[0]\, - \DWACT_ADD_CI_0_pog_array_1_3[0]\, - \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_11_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_5[0]\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, - \cpt_next_commutation[6]_net_1\, - \DWACT_ADD_CI_0_g_array_12[0]\, - \cpt_next_commutation[2]_net_1\, - \DWACT_ADD_CI_0_g_array_12_4[0]\, - \cpt_next_commutation[10]_net_1\, \DWACT_ADD_CI_0_TMP[0]\, - \cpt_next_commutation[1]_net_1\, - \DWACT_ADD_CI_0_g_array_12_5[0]\, - \cpt_next_commutation[12]_net_1\, - \DWACT_ADD_CI_0_g_array_12_6[0]\, - \cpt_next_commutation[14]_net_1\, - \DWACT_ADD_CI_0_g_array_12_3[0]\, - \cpt_next_commutation[8]_net_1\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, - \cpt_next_commutation[4]_net_1\, N_68, N_60, - \DWACT_FINC_E[0]\, N_37, \DWACT_FINC_E[4]\, N_22, - \DWACT_FINC_E[7]\, \DWACT_FINC_E[6]\, N_157, - \s_coarse_time[1]_net_1\, \s_coarse_time[0]_net_1\, N_149, - \s_coarse_time[3]_net_1\, \DWACT_FINC_E_0[0]\, N_126, - \s_coarse_time[8]_net_1\, \DWACT_FINC_E_0[4]\, N_111, - \DWACT_FINC_E_0[7]\, \DWACT_FINC_E_0[6]\, - un1_s_coarse_time_3_m_0, s_coarse_time38, - un1_commutation_timer_3_0_a2_25, - un1_commutation_timer_3_0_a2_24, - un1_commutation_timer_3_0_a2_29, - un1_commutation_timer_3_0_a2_21, - un1_commutation_timer_3_0_a2_20, - un1_commutation_timer_3_0_a2_27, - un1_commutation_timer_3_0_a2_13, - un1_commutation_timer_3_0_a2_12, - un1_commutation_timer_3_0_a2_23, - un1_commutation_timer_3_0_a2_5, - un1_commutation_timer_3_0_a2_4, - un1_commutation_timer_3_0_a2_19, - un1_commutation_timer_3_0_a2_1, - un1_commutation_timer_3_0_a2_0, - un1_commutation_timer_3_0_a2_17, N_139_i_i_0, N_138_i_i_0, - un1_commutation_timer_3_0_a2_15, N_131_i_i_0, N_130_i_i_0, - un1_commutation_timer_3_0_a2_11, N_127_i_i_0, N_126_i_i_0, - un1_commutation_timer_3_0_a2_9, N_123_i_i_0, N_122_i_i_0, - un1_commutation_timer_3_0_a2_7, N_115_i_i_0, N_114_i_i_0, - un1_commutation_timer_3_0_a2_3, - \p_next_commutation[30]_net_1\, N_141_i_i_0, - \p_next_commutation[26]_net_1\, N_137_i_i_0, - \p_next_commutation[24]_net_1\, N_135_i_i_0, - \p_next_commutation[22]_net_1\, N_133_i_i_0, - \p_next_commutation[18]_net_1\, N_129_i_i_0, - \p_next_commutation[14]_net_1\, N_125_i_i_0, - \p_next_commutation[10]_net_1\, N_121_i_i_0, - \p_next_commutation[8]_net_1\, N_119_i_i_0, - \p_next_commutation[6]_net_1\, N_117_i_i_0, - \p_next_commutation[2]_net_1\, N_113_i_i_0, - \p_next_commutation[0]_net_1\, N_111_i_i_0, - secondary_cpt_c12_m6_0_a2_5, \secondary_cpt[10]_net_1\, - \secondary_cpt[9]_net_1\, secondary_cpt_c12_m6_0_a2_3, - secondary_cpt_c12_m6_0_a2_4, \secondary_cpt[6]_net_1\, - \secondary_cpt[12]_net_1\, secondary_cpt_c12_m6_0_a2_1, - \secondary_cpt[11]_net_1\, s_coarse_time38lto5_1, - \secondary_cpt[7]_net_1\, \secondary_cpt[8]_net_1\, - s_coarse_time_1_NE_21, s_coarse_time_1_NE_20, - s_coarse_time_1_NE_27, s_coarse_time_1_NE_17, - s_coarse_time_1_NE_16, s_coarse_time_1_NE_25, - s_coarse_time_1_NE_13, s_coarse_time_1_NE_12, - s_coarse_time_1_NE_23, s_coarse_time_1_NE_5, - s_coarse_time_1_NE_4, s_coarse_time_1_NE_19, - s_coarse_time_1_29_i, s_coarse_time_1_28_i, - s_coarse_time_1_NE_15, s_coarse_time_1_21_i, - s_coarse_time_1_20_i, s_coarse_time_1_NE_11, - s_coarse_time_1_17_i, s_coarse_time_1_16_i, - s_coarse_time_1_NE_9, s_coarse_time_1_13_i, - s_coarse_time_1_12_i, s_coarse_time_1_NE_7, - s_coarse_time_1_5_i, s_coarse_time_1_4_i, - s_coarse_time_1_NE_3, s_coarse_time_1_1_i, - s_coarse_time_1_0_i, s_coarse_time_1_NE_1, - \latched_next_commutation[30]_net_1\, - \s_coarse_time[30]_net_1\, s_coarse_time_1_31_i, - \latched_next_commutation[26]_net_1\, - \s_coarse_time[26]_net_1\, s_coarse_time_1_27_i, - \latched_next_commutation[24]_net_1\, - \s_coarse_time[24]_net_1\, s_coarse_time_1_25_i, - \latched_next_commutation[22]_net_1\, - \s_coarse_time[22]_net_1\, s_coarse_time_1_23_i, - \latched_next_commutation[18]_net_1\, - \s_coarse_time[18]_net_1\, s_coarse_time_1_19_i, - \latched_next_commutation[14]_net_1\, - \s_coarse_time[14]_net_1\, s_coarse_time_1_15_i, - \latched_next_commutation[10]_net_1\, - \s_coarse_time[10]_net_1\, s_coarse_time_1_11_i, - \latched_next_commutation[8]_net_1\, s_coarse_time_1_9_i, - \latched_next_commutation[6]_net_1\, - \s_coarse_time[6]_net_1\, s_coarse_time_1_7_i, - \latched_next_commutation[2]_net_1\, - \s_coarse_time[2]_net_1\, s_coarse_time_1_3_i, - sirq2_1_sqmuxa_i_a2_15, sirq2_1_sqmuxa_i_a2_13, - \cpt_next_commutation[15]_net_1\, sirq2_1_sqmuxa_i_a2_11, - \cpt_next_commutation[13]_net_1\, sirq2_1_sqmuxa_i_a2_9, - \cpt_next_commutation[11]_net_1\, sirq2_1_sqmuxa_i_a2_7, - \cpt_next_commutation[9]_net_1\, sirq2_1_sqmuxa_i_a2_5, - \cpt_next_commutation[7]_net_1\, sirq2_1_sqmuxa_i_a2_2, - sirq2_1_sqmuxa_i_a2_3, \cpt_next_commutation[5]_net_1\, - \cpt_next_commutation[16]_net_1\, - \cpt_next_commutation[0]_net_1\, - \cpt_next_commutation[3]_net_1\, s_coarse_time38lto16_8, - s_coarse_time38lto16_2, s_coarse_time38lto16_1, - s_coarse_time38lto16_5, s_coarse_time38lto16_7, - s_coarse_time38lto16_4, \secondary_cpt[16]_net_1\, - \secondary_cpt[15]_net_1\, \secondary_cpt[13]_net_1\, - \secondary_cpt[14]_net_1\, \un1_cpt_0_a3_15[0]\, - \un1_cpt_0_a3_9[0]\, \un1_cpt_0_a3_8[0]\, - \un1_cpt_0_a3_12[0]\, \fine_time[8]\, \un1_cpt_0_a3_7[0]\, - \un1_cpt_0_a3_11[0]\, \un1_cpt_0_a3_5[0]\, - \un1_cpt_0_a3_10[0]\, \un1_cpt_0_a3_3[0]\, - \un1_cpt_0_a3_1[0]\, \state[0]_net_1\, \fine_time[0]\, - \fine_time[3]\, \fine_time[1]\, - previous_coarse_time_load_1_NE_29, - previous_coarse_time_load_1_NE_21, - previous_coarse_time_load_1_NE_20, - previous_coarse_time_load_1_NE_27, - previous_coarse_time_load_1_NE_28, - previous_coarse_time_load_1_NE_17, - previous_coarse_time_load_1_NE_16, - previous_coarse_time_load_1_NE_25, - previous_coarse_time_load_1_NE_15, - previous_coarse_time_load_1_NE_14, - previous_coarse_time_load_1_NE_22, - previous_coarse_time_load_1_NE_5, - previous_coarse_time_load_1_NE_4, - previous_coarse_time_load_1_NE_19, - previous_coarse_time_load_1_25_i, - previous_coarse_time_load_1_24_i, - previous_coarse_time_load_1_NE_13, - previous_coarse_time_load_1_21_i, - previous_coarse_time_load_1_20_i, - previous_coarse_time_load_1_NE_11, - previous_coarse_time_load_1_17_i, - previous_coarse_time_load_1_16_i, - previous_coarse_time_load_1_NE_9, - previous_coarse_time_load_1_13_i, - previous_coarse_time_load_1_12_i, - previous_coarse_time_load_1_NE_7, - previous_coarse_time_load_1_5_i, - previous_coarse_time_load_1_4_i, - previous_coarse_time_load_1_NE_3, - previous_coarse_time_load_1_1_i, - previous_coarse_time_load_1_0_i, - previous_coarse_time_load_1_NE_1, - \previous_coarse_time_load[30]_net_1\, - previous_coarse_time_load_1_31_i, - \previous_coarse_time_load[28]_net_1\, - previous_coarse_time_load_1_29_i, - \previous_coarse_time_load[26]_net_1\, - previous_coarse_time_load_1_27_i, - \previous_coarse_time_load[22]_net_1\, - previous_coarse_time_load_1_23_i, - \previous_coarse_time_load[18]_net_1\, - previous_coarse_time_load_1_19_i, - \previous_coarse_time_load[14]_net_1\, - previous_coarse_time_load_1_15_i, - \previous_coarse_time_load[10]_net_1\, - previous_coarse_time_load_1_11_i, - \previous_coarse_time_load[8]_net_1\, - previous_coarse_time_load_1_9_i, - \previous_coarse_time_load[6]_net_1\, - previous_coarse_time_load_1_7_i, - \previous_coarse_time_load[2]_net_1\, - previous_coarse_time_load_1_3_i, flag_1_sqmuxa_i_o3_14, - flag_1_sqmuxa_i_o3_6, flag_1_sqmuxa_i_o3_5, - flag_1_sqmuxa_i_o3_12, flag_1_sqmuxa_i_o3_13, - flag_1_sqmuxa_i_o3_2, flag_1_sqmuxa_i_o3_1, - flag_1_sqmuxa_i_o3_10, flag_1_sqmuxa_i_o3_8, - \fine_time[12]\, flag_1_sqmuxa_i_o3_4, \fine_time[10]\, - \fine_time[7]\, \fine_time[16]\, \fine_time[11]\, - \fine_time[9]\, \fine_time[4]\, \fine_time[6]\, - \fine_time[13]\, \fine_time[2]\, \fine_time[5]\, - \fine_time[14]\, \fine_time[15]\, s_coarse_time38lto5_0, - \secondary_cpt[2]_net_1\, \secondary_cpt[3]_net_1\, - s_coarse_time38lt16, s_coarse_time38lto1, N_243, - un1_p_clk_div, \s_coarse_time_i_m[31]\, - \s_coarse_time[31]_net_1\, secondary_cpt_c12, - secondary_cpt_c3, \secondary_cpt[5]_net_1\, - \secondary_cpt[4]_net_1\, \p_clk_div\, reset_i_0, - un1_soft_tick_44_i, \s_coarse_time_4[31]\, un1_resetn_2_i, - \cpt_5[1]\, I_5_9, \cpt_5[16]\, I_98_4, - \s_coarse_time_10_iv[31]\, secondary_cpt_c2, - \secondary_cpt[0]_net_1\, \secondary_cpt[1]_net_1\, - secondary_cpt_c4, secondary_cpt_c6, secondary_cpt_c8, - secondary_cpt_c10, secondary_cpt_c14, I_224_1, - secondary_cpt_n1, \secondary_cpt_RNO[0]_net_1\, - secondary_cpt_n2, secondary_cpt_n3, secondary_cpt_n4, - secondary_cpt_n5, secondary_cpt_n6, secondary_cpt_n7, - secondary_cpt_n8, secondary_cpt_n9, secondary_cpt_n10, - secondary_cpt_n11, secondary_cpt_n12, secondary_cpt_n13, - secondary_cpt_n14, secondary_cpt_n15, secondary_cpt_n16, - \previous_coarse_time_load[31]_net_1\, - \latched_next_commutation[31]_net_1\, un1_soft_tick_16_i, - \s_coarse_time_4[30]\, un1_resetn_7_i, - \s_coarse_time_7[30]\, I_217_1, un1_soft_tick_29_i, - \s_coarse_time_4[29]\, un1_resetn_11_i, - \s_coarse_time_7[29]\, \s_coarse_time[29]_net_1\, I_210_3, - \previous_coarse_time_load[29]_net_1\, - \latched_next_commutation[29]_net_1\, un1_soft_tick_15_i, - \s_coarse_time_4[28]\, un1_resetn_15_i, - \s_coarse_time_7[28]\, \s_coarse_time[28]_net_1\, I_203_3, - \latched_next_commutation[28]_net_1\, un1_soft_tick_21_i, - \s_coarse_time_4[27]\, un1_resetn_20_i, - \s_coarse_time_7[27]\, \s_coarse_time[27]_net_1\, I_196_3, - \previous_coarse_time_load[27]_net_1\, - \latched_next_commutation[27]_net_1\, un1_soft_tick_20_i, - \s_coarse_time_4[26]\, un1_resetn_8_i, - \s_coarse_time_7[26]\, I_186_3, un1_soft_tick_31_i, - \s_coarse_time_4[25]\, un1_resetn_6_i, - \s_coarse_time_7[25]\, \s_coarse_time[25]_net_1\, I_173_3, - \previous_coarse_time_load[25]_net_1\, - \latched_next_commutation[25]_net_1\, un1_soft_tick_9_i, - \s_coarse_time_4[24]\, un1_resetn_19_i, - \s_coarse_time_7[24]\, I_166_3, - \previous_coarse_time_load[24]_net_1\, un1_soft_tick_2_i, - \s_coarse_time_4[23]\, un1_resetn_16_i, - \s_coarse_time_7[23]\, \s_coarse_time[23]_net_1\, I_156_3, - \previous_coarse_time_load[23]_net_1\, un1_soft_tick_24_i, - \s_coarse_time_4[22]\, un1_resetn_5_i, - \s_coarse_time_7[22]\, I_143_3, un1_soft_tick_28_i, - \s_coarse_time_4[21]\, un1_resetn_10_i, - \s_coarse_time_7[21]\, \s_coarse_time[21]_net_1\, I_136_3, - \previous_coarse_time_load[21]_net_1\, - \previous_coarse_time_load[20]_net_1\, un1_soft_tick_1_i, - \s_coarse_time_4[19]\, un1_resetn_12_i, - \s_coarse_time_7[19]\, \s_coarse_time[19]_net_1\, I_122_3, - \previous_coarse_time_load[19]_net_1\, - \latched_next_commutation[19]_net_1\, un1_soft_tick_27_i, - \s_coarse_time_4[18]\, un1_resetn_4_i, - \s_coarse_time_7[18]\, I_115_3, un1_soft_tick_26_i, - \s_coarse_time_4[17]\, un1_resetn_14_i, - \s_coarse_time_7[17]\, \s_coarse_time[17]_net_1\, I_105_3, - \previous_coarse_time_load[17]_net_1\, - \latched_next_commutation[17]_net_1\, un1_soft_tick_17_i, - \s_coarse_time_4[16]\, un1_resetn_27_i, - \s_coarse_time_7[16]\, \s_coarse_time[16]_net_1\, I_98_3, - \previous_coarse_time_load[16]_net_1\, - \latched_next_commutation[16]_net_1\, un1_soft_tick_3_i, - \s_coarse_time_4[15]\, un1_resetn_24_i, - \s_coarse_time_7[15]\, \s_coarse_time[15]_net_1\, I_91_3, - \previous_coarse_time_load[15]_net_1\, - \latched_next_commutation[15]_net_1\, un1_soft_tick_18_i, - \s_coarse_time_4[14]\, un1_resetn_3_i, - \s_coarse_time_7[14]\, I_84_3, \flag\, un1_soft_tick_12_i, - \s_coarse_time_4[13]\, un1_resetn_18_i, - \s_coarse_time_7[13]\, \s_coarse_time[13]_net_1\, I_77_3, - \previous_coarse_time_load[13]_net_1\, - \latched_next_commutation[13]_net_1\, un1_soft_tick_13_i, - \s_coarse_time_4[12]\, un1_resetn_25_i, - \s_coarse_time_7[12]\, \s_coarse_time[12]_net_1\, I_73_3, - \previous_coarse_time_load[12]_net_1\, - \latched_next_commutation[12]_net_1\, un1_soft_tick_7_i, - \s_coarse_time_4[11]\, un1_resetn_28_i, - \s_coarse_time_7[11]\, \s_coarse_time[11]_net_1\, I_66_5, - \previous_coarse_time_load[11]_net_1\, - \latched_next_commutation[11]_net_1\, un1_soft_tick_22_i, - \s_coarse_time_4[10]\, un1_resetn_9_i, - \s_coarse_time_7[10]\, I_56_5, un1_soft_tick_30_i, - \s_coarse_time_4[9]\, un1_resetn_22_i, - \s_coarse_time_7[9]\, \s_coarse_time[9]_net_1\, I_52_4, - \previous_coarse_time_load[9]_net_1\, - \latched_next_commutation[9]_net_1\, un1_soft_tick_i, - \s_coarse_time_4[8]\, un1_resetn_21_i, - \s_coarse_time_7[8]\, I_45_4, un1_soft_tick_11_i, - \s_coarse_time_4[7]\, un1_resetn_32_i, - \s_coarse_time_7[7]\, \s_coarse_time[7]_net_1\, I_38_5, - \previous_coarse_time_load[7]_net_1\, - \latched_next_commutation[7]_net_1\, un1_soft_tick_10_i, - \s_coarse_time_4[6]\, un1_resetn_13_i, - \s_coarse_time_7[6]\, I_31_7, un1_soft_tick_4_i, - \s_coarse_time_4[5]\, un1_resetn_26_i, - \s_coarse_time_7[5]\, \s_coarse_time[5]_net_1\, I_24_9, - \previous_coarse_time_load[5]_net_1\, - \latched_next_commutation[5]_net_1\, un1_soft_tick_5_i, - \s_coarse_time_4[4]\, un1_resetn_17_i, - \s_coarse_time_7[4]\, \s_coarse_time[4]_net_1\, I_20_8, - \previous_coarse_time_load[4]_net_1\, - \latched_next_commutation[4]_net_1\, un1_soft_tick_6_i, - \s_coarse_time_4[3]\, un1_resetn_31_i, - \s_coarse_time_7[3]\, I_13_12, - \previous_coarse_time_load[3]_net_1\, - \latched_next_commutation[3]_net_1\, un1_soft_tick_14_i, - \s_coarse_time_4[2]\, un1_resetn_30_i, - \s_coarse_time_7[2]\, I_9_8, un1_soft_tick_19_i, - \s_coarse_time_4[1]\, un1_resetn_33_i, - \s_coarse_time_7[1]\, I_5_8, - \previous_coarse_time_load[1]_net_1\, - \latched_next_commutation[1]_net_1\, un1_soft_tick_25_i, - \s_coarse_time_4[0]\, un1_resetn_29_i, - \s_coarse_time_7[0]\, - \previous_coarse_time_load[0]_net_1\, - \latched_next_commutation[0]_net_1\, - commutation_timer_0_sqmuxa_1, N_146, N_147, N_148, - N_149_0, N_150, N_151, N_152, N_153, N_154, N_155, N_156, - N_157_0, N_158, N_159, N_160, N_161, N_162, N_163, N_164, - N_165, N_166, N_167, N_168, N_170, N_171, N_172, N_173, - N_174, N_175, N_176, \commutation_timer_RNI3EI8[0]_net_1\, - N_6, un1_commutation_timer_3, N_9, I_70, N_11, - \DWACT_ADD_CI_0_partial_sum[0]\, N_77, - \p_next_commutation[1]_net_1\, - \p_next_commutation[3]_net_1\, - \p_next_commutation[4]_net_1\, - \p_next_commutation[5]_net_1\, - \p_next_commutation[7]_net_1\, - \p_next_commutation[9]_net_1\, - \p_next_commutation[11]_net_1\, - \p_next_commutation[12]_net_1\, - \p_next_commutation[13]_net_1\, - \p_next_commutation[15]_net_1\, - \p_next_commutation[16]_net_1\, - \p_next_commutation[17]_net_1\, - \p_next_commutation[19]_net_1\, - \p_next_commutation[20]_net_1\, - \p_next_commutation[21]_net_1\, - \p_next_commutation[23]_net_1\, - \p_next_commutation[25]_net_1\, - \p_next_commutation[27]_net_1\, - \p_next_commutation[28]_net_1\, - \p_next_commutation[29]_net_1\, - \p_next_commutation[31]_net_1\, N_169, - \s_coarse_time[20]_net_1\, - \latched_next_commutation[20]_net_1\, - \latched_next_commutation[21]_net_1\, - \latched_next_commutation[23]_net_1\, N_7, N_5, - \un1_cpt[0]\, N_177, \s_coarse_time_4[20]\, I_129_3, - \s_coarse_time_7[20]\, un1_resetn_23_i, - un1_soft_tick_23_i, clk_int, clk_div_3, clk_div_2, I_63, - I_68, I_54, I_58, I_60, I_62, I_64, I_66_4, I_69, I_55, - I_56_4, I_57, I_59, I_65, I_67, I_9_9, I_13_13, I_20_9, - I_24_10, I_31_8, I_38_6, I_45_5, I_52_5, I_56_6, I_66_6, - I_73_4, I_77_4, I_84_4, I_91_4, clk_div_1, - \coarse_time[0]_net_1\, N_4, \DWACT_FINC_E[24]\, - \DWACT_FINC_E[23]\, \DWACT_FINC_E[27]\, - \DWACT_FINC_E[26]\, N_9_0, N_14, \DWACT_FINC_E[25]\, N_19, - \DWACT_FINC_E[29]\, \DWACT_FINC_E[30]\, N_24_0, - \DWACT_FINC_E[15]\, \DWACT_FINC_E[17]\, - \DWACT_FINC_E[22]\, N_31, \DWACT_FINC_E[21]\, - \DWACT_FINC_E[9]\, \DWACT_FINC_E[12]\, \DWACT_FINC_E[20]\, - N_40, \DWACT_FINC_E[13]\, \DWACT_FINC_E[19]\, N_45, - \DWACT_FINC_E[18]\, N_52, \DWACT_FINC_E[33]\, - \DWACT_FINC_E[34]\, \DWACT_FINC_E[2]\, \DWACT_FINC_E[5]\, - N_61, \DWACT_FINC_E[28]\, \DWACT_FINC_E[16]\, N_66, N_71, - \DWACT_FINC_E[14]\, N_76, N_81, \DWACT_FINC_E[10]\, N_88, - \DWACT_FINC_E[11]\, N_93, N_98, N_103, \DWACT_FINC_E[8]\, - N_108, N_116, N_123, \DWACT_FINC_E[3]\, N_131, N_136, - N_141, \DWACT_FINC_E[1]\, N_146_0, N_154_0, N_4_0, - \DWACT_FINC_E_0[10]\, \DWACT_FINC_E_0[9]\, N_9_1, N_14_0, - \DWACT_FINC_E_0[8]\, N_19_0, N_27, \DWACT_FINC_E_0[2]\, - \DWACT_FINC_E_0[5]\, N_34, \DWACT_FINC_E_0[3]\, N_42, - N_47, N_52_0, \DWACT_FINC_E_0[1]\, N_57, N_65, - \DWACT_ADD_CI_0_pog_array_2_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_6[0]\, - \DWACT_ADD_CI_0_pog_array_1_4[0]\, - \DWACT_ADD_CI_0_pog_array_1_2[0]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : Clk_divider - Use entity work.Clk_divider(DEF_ARCH); -begin - - coarse_time(0) <= \coarse_time[0]_net_1\; - fine_time(16) <= \fine_time[16]\; - fine_time(15) <= \fine_time[15]\; - fine_time(14) <= \fine_time[14]\; - fine_time(13) <= \fine_time[13]\; - fine_time(12) <= \fine_time[12]\; - fine_time(11) <= \fine_time[11]\; - fine_time(10) <= \fine_time[10]\; - fine_time(9) <= \fine_time[9]\; - fine_time(8) <= \fine_time[8]\; - fine_time(7) <= \fine_time[7]\; - fine_time(6) <= \fine_time[6]\; - fine_time(5) <= \fine_time[5]\; - fine_time(4) <= \fine_time[4]\; - fine_time(3) <= \fine_time[3]\; - fine_time(2) <= \fine_time[2]\; - fine_time(1) <= \fine_time[1]\; - fine_time(0) <= \fine_time[0]\; - - \p_next_commutation_RNIGF5L[14]\ : XA1A - port map(A => \p_next_commutation[14]_net_1\, B => - next_commutation(14), C => N_125_i_i_0, Y => - un1_commutation_timer_3_0_a2_7); - - un4_s_coarse_time_I_105 : XOR2 - port map(A => N_88, B => \s_coarse_time[17]_net_1\, Y => - I_105_3); - - \coarse_time[4]\ : DFN1C0 - port map(D => \s_coarse_time[4]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(4)); - - un4_s_coarse_time_I_23 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => - \s_coarse_time[3]_net_1\, C => \s_coarse_time[4]_net_1\, - Y => N_146_0); - - \s_coarse_time_RNO[0]\ : AO1B - port map(A => soft_tick_3, B => \s_coarse_time_4[0]\, C => - rstn, Y => un1_resetn_29_i); - - \latched_next_commutation_RNIK6O5[10]\ : XA1A - port map(A => \latched_next_commutation[10]_net_1\, B => - \s_coarse_time[10]_net_1\, C => s_coarse_time_1_11_i, Y - => s_coarse_time_1_NE_5); - - un1_cpt_next_commutation_I_60 : XOR2 - port map(A => \cpt_next_commutation[5]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_60); - - \cpt_next_commutation[16]\ : DFN1C0 - port map(D => N_9, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[16]_net_1\); - - \s_coarse_time_RNO_1[3]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[3]\, Y => - un1_soft_tick_6_i); - - sirq1 : DFN1C0 - port map(D => commutation_timer_0_sqmuxa_1, CLK => lclk_c, - CLR => rstn, Q => pirq(12)); - - \latched_next_commutation[11]\ : DFN1E0P0 - port map(D => N_157_0, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[11]_net_1\); - - \previous_coarse_time_load_RNISK4P[20]\ : NOR3C - port map(A => previous_coarse_time_load_1_21_i, B => - previous_coarse_time_load_1_20_i, C => - previous_coarse_time_load_1_NE_11, Y => - previous_coarse_time_load_1_NE_21); - - un4_s_coarse_time_I_176 : AND2 - port map(A => \s_coarse_time[24]_net_1\, B => - \s_coarse_time[25]_net_1\, Y => \DWACT_FINC_E[20]\); - - \cpt_RNI9038[16]\ : NOR3B - port map(A => \fine_time[16]\, B => \fine_time[0]\, C => - \fine_time[11]\, Y => flag_1_sqmuxa_i_o3_8); - - un4_s_coarse_time_I_72 : NOR2B - port map(A => \DWACT_FINC_E_0[7]\, B => \DWACT_FINC_E_0[6]\, - Y => N_111); - - \s_coarse_time_RNO_1[21]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[21]\, Y - => un1_soft_tick_28_i); - - \previous_coarse_time_load[4]\ : DFN1E0C0 - port map(D => coarse_time_load(4), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[4]_net_1\); - - un1_cpt_next_commutation_I_58 : XOR2 - port map(A => \cpt_next_commutation[4]_net_1\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_58); - - un1_cpt_next_commutation_I_56 : XOR2 - port map(A => \cpt_next_commutation[11]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_4[0]\, Y => I_56_4); - - \s_coarse_time_RNO_1[23]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[23]\, Y - => un1_soft_tick_2_i); - - un4_s_coarse_time_I_213 : AND3 - port map(A => \s_coarse_time[27]_net_1\, B => - \s_coarse_time[28]_net_1\, C => \s_coarse_time[29]_net_1\, - Y => \DWACT_FINC_E[26]\); - - \s_coarse_time[19]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[19]\, CLK => clk_div_3, PRE - => un1_soft_tick_1_i, CLR => un1_resetn_12_i, Q => - \s_coarse_time[19]_net_1\); - - \secondary_cpt_RNI1V9P1[14]\ : NOR3C - port map(A => \secondary_cpt[13]_net_1\, B => - secondary_cpt_c12, C => \secondary_cpt[14]_net_1\, Y => - secondary_cpt_c14); - - flag_0_RNIF5RG2 : MX2 - port map(A => I_91_3, B => coarse_time_load(15), S => - \flag_0\, Y => \s_coarse_time_4[15]\); - - un9_cpt_I_31 : XOR2 - port map(A => N_52_0, B => \fine_time[6]\, Y => I_31_8); - - un1_cpt_next_commutation_I_75 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_3[0]\); - - un4_s_coarse_time_I_185 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[21]\, Y => N_31); - - \secondary_cpt_RNICLEB[11]\ : NOR2B - port map(A => \secondary_cpt[11]_net_1\, B => - s_coarse_time38lto5_1, Y => secondary_cpt_c12_m6_0_a2_3); - - \s_coarse_time_RNO_1[31]\ : AO1B - port map(A => soft_tick_0, B => \s_coarse_time_4[31]\, C - => rstn, Y => un1_resetn_2_i); - - \previous_coarse_time_load_RNIAU45[5]\ : XNOR2 - port map(A => coarse_time_load(5), B => - \previous_coarse_time_load[5]_net_1\, Y => - previous_coarse_time_load_1_5_i); - - \previous_coarse_time_load[11]\ : DFN1E0C0 - port map(D => coarse_time_load(11), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[11]_net_1\); - - \p_next_commutation[24]\ : DFN1E1 - port map(D => next_commutation(24), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[24]_net_1\); - - un9_cpt_I_27 : AND2 - port map(A => \fine_time[3]\, B => \fine_time[4]\, Y => - \DWACT_FINC_E_0[1]\); - - \latched_next_commutation_RNO[8]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(8), Y => N_154); - - \p_next_commutation_RNIP8D5[4]\ : XNOR2 - port map(A => next_commutation(4), B => - \p_next_commutation[4]_net_1\, Y => N_114_i_i_0); - - \s_coarse_time_RNO_1[24]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[24]\, Y - => un1_soft_tick_9_i); - - \s_coarse_time_RNO_0[11]\ : MX2 - port map(A => \s_coarse_time_4[11]\, B => - \s_coarse_time[11]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[11]\); - - un4_s_coarse_time_I_90 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E_0[7]\, - C => \DWACT_FINC_E[9]\, Y => N_98); - - \s_coarse_time_RNO[21]\ : AO1C - port map(A => \s_coarse_time_4[21]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_10_i); - - un4_s_coarse_time_I_20 : XOR2 - port map(A => N_149, B => \s_coarse_time[4]_net_1\, Y => - I_20_8); - - \s_coarse_time_RNO_0[13]\ : MX2 - port map(A => \s_coarse_time_4[13]\, B => - \s_coarse_time[13]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[13]\); - - \cpt_next_commutation[13]\ : DFN1C0 - port map(D => I_59, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[13]_net_1\); - - flag_0_RNIGVE03 : MX2 - port map(A => I_196_3, B => coarse_time_load(27), S => - \flag_0\, Y => \s_coarse_time_4[27]\); - - un4_s_coarse_time_I_165 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[18]\, Y => N_45); - - \latched_next_commutation_RNI0VJB[16]\ : NOR3C - port map(A => s_coarse_time_1_17_i, B => - s_coarse_time_1_16_i, C => s_coarse_time_1_NE_9, Y => - s_coarse_time_1_NE_20); - - \cpt_RNIC6G2[5]\ : NOR2B - port map(A => \fine_time[5]\, B => \fine_time[7]\, Y => - \un1_cpt_0_a3_3[0]\); - - \previous_coarse_time_load[31]\ : DFN1E0P0 - port map(D => coarse_time_load(31), CLK => clk_div_2, PRE - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[31]_net_1\); - - \cpt_RNIP61P[0]\ : NOR3C - port map(A => \un1_cpt_0_a3_9[0]\, B => \un1_cpt_0_a3_8[0]\, - C => \un1_cpt_0_a3_12[0]\, Y => \un1_cpt_0_a3_15[0]\); - - \s_coarse_time_RNO_1[25]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[25]\, Y - => un1_soft_tick_31_i); - - un1_cpt_next_commutation_I_101 : AND2 - port map(A => \cpt_next_commutation[4]_net_1\, B => - \cpt_next_commutation[5]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - \previous_coarse_time_load_RNIARLC[28]\ : XA1A - port map(A => \previous_coarse_time_load[28]_net_1\, B => - coarse_time_load(28), C => - previous_coarse_time_load_1_29_i, Y => - previous_coarse_time_load_1_NE_14); - - \p_next_commutation[15]\ : DFN1E1 - port map(D => next_commutation(15), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[15]_net_1\); - - \latched_next_commutation_RNO[20]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(20), - Y => N_166); - - \s_coarse_time_RNO_0[14]\ : MX2 - port map(A => \s_coarse_time_4[14]\, B => - \s_coarse_time[14]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[14]\); - - un9_cpt_I_45 : XOR2 - port map(A => N_42, B => \fine_time[8]\, Y => I_45_5); - - \previous_coarse_time_load_RNI6196[21]\ : XNOR2 - port map(A => coarse_time_load(21), B => - \previous_coarse_time_load[21]_net_1\, Y => - previous_coarse_time_load_1_21_i); - - \previous_coarse_time_load[22]\ : DFN1E0C0 - port map(D => coarse_time_load(22), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[22]_net_1\); - - un4_s_coarse_time_I_98 : XOR2 - port map(A => N_93, B => \s_coarse_time[16]_net_1\, Y => - I_98_3); - - \secondary_cpt[9]\ : DFN1E0C1 - port map(D => secondary_cpt_n9, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[9]_net_1\); - - \previous_coarse_time_load_RNIK1B6[19]\ : XNOR2 - port map(A => coarse_time_load(19), B => - \previous_coarse_time_load[19]_net_1\, Y => - previous_coarse_time_load_1_19_i); - - \p_next_commutation[0]\ : DFN1E1 - port map(D => next_commutation(0), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[0]_net_1\); - - un9_cpt_I_38 : XOR2 - port map(A => N_47, B => \fine_time[7]\, Y => I_38_6); - - \s_coarse_time_RNO_0[15]\ : MX2 - port map(A => \s_coarse_time_4[15]\, B => - \s_coarse_time[15]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[15]\); - - \previous_coarse_time_load_RNI4196[11]\ : XNOR2 - port map(A => coarse_time_load(11), B => - \previous_coarse_time_load[11]_net_1\, Y => - previous_coarse_time_load_1_11_i); - - \latched_next_commutation_RNO[6]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(6), Y => N_152); - - un9_cpt_I_20 : XOR2 - port map(A => N_60, B => \fine_time[4]\, Y => I_20_9); - - \latched_next_commutation_RNO[24]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(24), - Y => N_170); - - \latched_next_commutation[23]\ : DFN1E0P0 - port map(D => N_169, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[23]_net_1\); - - \commutation_timer[0]\ : DFN1C0 - port map(D => N_77, CLK => lclk_c, CLR => rstn, Q => - \commutation_timer[0]_net_1\); - - un4_s_coarse_time_I_8 : NOR2B - port map(A => \s_coarse_time[1]_net_1\, B => - \s_coarse_time[0]_net_1\, Y => N_157); - - un4_s_coarse_time_I_52 : XOR2 - port map(A => N_126, B => \s_coarse_time[9]_net_1\, Y => - I_52_4); - - un4_s_coarse_time_I_199 : AND2 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - Y => \DWACT_FINC_E[24]\); - - \cpt[8]\ : DFN1C1 - port map(D => I_45_5, CLK => clk_div_0, CLR => reset_i_0, Q - => \fine_time[8]\); - - \coarse_time[10]\ : DFN1C0 - port map(D => \s_coarse_time[10]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(10)); - - \secondary_cpt_RNO[5]\ : XOR2 - port map(A => secondary_cpt_c4, B => - \secondary_cpt[5]_net_1\, Y => secondary_cpt_n5); - - \latched_next_commutation_RNI09NR3[10]\ : NOR3C - port map(A => s_coarse_time_1_NE_17, B => - s_coarse_time_1_NE_16, C => s_coarse_time_1_NE_25, Y => - s_coarse_time_1_NE_28); - - \latched_next_commutation[2]\ : DFN1E0P0 - port map(D => N_148, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[2]_net_1\); - - \previous_coarse_time_load_RNIEQHC[30]\ : XA1A - port map(A => \previous_coarse_time_load[30]_net_1\, B => - coarse_time_load(30), C => - previous_coarse_time_load_1_31_i, Y => - previous_coarse_time_load_1_NE_15); - - \previous_coarse_time_load[29]\ : DFN1E0C0 - port map(D => coarse_time_load(29), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[29]_net_1\); - - \s_coarse_time_RNO[25]\ : AO1C - port map(A => \s_coarse_time_4[25]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_6_i); - - \previous_coarse_time_load_RNI4L6P[12]\ : NOR3C - port map(A => previous_coarse_time_load_1_13_i, B => - previous_coarse_time_load_1_12_i, C => - previous_coarse_time_load_1_NE_7, Y => - previous_coarse_time_load_1_NE_19); - - \previous_coarse_time_load_RNIIHA6[27]\ : XNOR2 - port map(A => coarse_time_load(27), B => - \previous_coarse_time_load[27]_net_1\, Y => - previous_coarse_time_load_1_27_i); - - \p_next_commutation[2]\ : DFN1E1 - port map(D => next_commutation(2), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[2]_net_1\); - - \s_coarse_time_RNO[20]\ : AO1C - port map(A => \s_coarse_time_4[20]\, B => soft_tick_3, C - => rstn, Y => un1_resetn_23_i); - - \s_coarse_time_RNO_1[22]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[22]\, Y - => un1_soft_tick_24_i); - - \previous_coarse_time_load_RNI4P86[20]\ : XNOR2 - port map(A => coarse_time_load(20), B => - \previous_coarse_time_load[20]_net_1\, Y => - previous_coarse_time_load_1_20_i); - - \s_coarse_time_RNO[11]\ : AO1C - port map(A => \s_coarse_time_4[11]\, B => soft_tick_2, C - => rstn, Y => un1_resetn_28_i); - - un4_s_coarse_time_I_13 : XOR2 - port map(A => N_154_0, B => \s_coarse_time[3]_net_1\, Y => - I_13_12); - - un4_s_coarse_time_I_192 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[22]\, Y => \DWACT_FINC_E[23]\); - - \s_coarse_time_RNO[1]\ : AO1C - port map(A => \s_coarse_time_4[1]\, B => soft_tick_3, C => - rstn, Y => un1_resetn_33_i); - - un4_s_coarse_time_I_66 : XOR2 - port map(A => N_116, B => \s_coarse_time[11]_net_1\, Y => - I_66_5); - - un4_s_coarse_time_I_84 : XOR2 - port map(A => N_103, B => \s_coarse_time[14]_net_1\, Y => - I_84_3); - - \latched_next_commutation_RNO[26]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(26), - Y => N_172); - - \secondary_cpt_RNIUSF41[14]\ : NOR3C - port map(A => s_coarse_time38lto16_2, B => - s_coarse_time38lto16_1, C => s_coarse_time38lto16_5, Y - => s_coarse_time38lto16_8); - - un9_cpt_I_9 : XOR2 - port map(A => N_68, B => \fine_time[2]\, Y => I_9_9); - - un9_cpt_I_24 : XOR2 - port map(A => N_57, B => \fine_time[5]\, Y => I_24_10); - - \latched_next_commutation[27]\ : DFN1E0P0 - port map(D => N_173, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[27]_net_1\); - - \p_next_commutation[20]\ : DFN1E1 - port map(D => next_commutation(20), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[20]_net_1\); - - \secondary_cpt[12]\ : DFN1E0C1 - port map(D => secondary_cpt_n12, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[12]_net_1\); - - un4_s_coarse_time_I_77 : XOR2 - port map(A => N_108, B => \s_coarse_time[13]_net_1\, Y => - I_77_3); - - \p_next_commutation_RNI06E95[16]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_21, B => - un1_commutation_timer_3_0_a2_20, C => - un1_commutation_timer_3_0_a2_27, Y => - un1_commutation_timer_3_0_a2_29); - - \latched_next_commutation_RNO[5]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(5), Y => N_151); - - \s_coarse_time_RNO_0[12]\ : MX2 - port map(A => \s_coarse_time_4[12]\, B => - \s_coarse_time[12]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[12]\); - - un9_cpt_I_76 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \fine_time[12]\, Y => N_19_0); - - un1_cpt_next_commutation_I_105 : AND2 - port map(A => \cpt_next_commutation[10]_net_1\, B => - \cpt_next_commutation[11]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_4[0]\); - - \s_coarse_time[24]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[24]\, CLK => clk_div_3, PRE - => un1_soft_tick_9_i, CLR => un1_resetn_19_i, Q => - \s_coarse_time[24]_net_1\); - - \latched_next_commutation_RNIB5S2[11]\ : XNOR2 - port map(A => \s_coarse_time[11]_net_1\, B => - \latched_next_commutation[11]_net_1\, Y => - s_coarse_time_1_11_i); - - un1_cpt_next_commutation_I_62 : XOR2 - port map(A => \cpt_next_commutation[6]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_62); - - \coarse_time[23]\ : DFN1C0 - port map(D => \s_coarse_time[23]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(23)); - - \coarse_time[18]\ : DFN1C0 - port map(D => \s_coarse_time[18]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(18)); - - un1_cpt_next_commutation_I_73 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => - \cpt_next_commutation[6]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_2[0]\); - - \secondary_cpt[11]\ : DFN1E0C1 - port map(D => secondary_cpt_n11, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[11]_net_1\); - - \previous_coarse_time_load_RNI4U9P2[10]\ : NOR3C - port map(A => previous_coarse_time_load_1_NE_17, B => - previous_coarse_time_load_1_NE_16, C => - previous_coarse_time_load_1_NE_25, Y => - previous_coarse_time_load_1_NE_28); - - un1_cpt_next_commutation_I_107 : AND2 - port map(A => \cpt_next_commutation[14]_net_1\, B => - \cpt_next_commutation[15]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_6[0]\); - - \previous_coarse_time_load[21]\ : DFN1E0C0 - port map(D => coarse_time_load(21), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[21]_net_1\); - - \latched_next_commutation_RNIJLS2[15]\ : XNOR2 - port map(A => \s_coarse_time[15]_net_1\, B => - \latched_next_commutation[15]_net_1\, Y => - s_coarse_time_1_15_i); - - \previous_coarse_time_load[9]\ : DFN1E0C0 - port map(D => coarse_time_load(9), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[9]_net_1\); - - \state_RNI65DH8[0]\ : NOR2A - port map(A => \un1_cpt_0[0]\, B => flag_1, Y => - flag_1_sqmuxa_1); - - \secondary_cpt[15]\ : DFN1E0C1 - port map(D => secondary_cpt_n15, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[15]_net_1\); - - \latched_next_commutation[12]\ : DFN1E0P0 - port map(D => N_158, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[12]_net_1\); - - \coarse_time[25]\ : DFN1C0 - port map(D => \s_coarse_time[25]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(25)); - - \s_coarse_time[13]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[13]\, CLK => clk_div_2, PRE - => un1_soft_tick_12_i, CLR => un1_resetn_18_i, Q => - \s_coarse_time[13]_net_1\); - - \s_coarse_time[18]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[18]\, CLK => clk_div_2, PRE - => un1_soft_tick_27_i, CLR => un1_resetn_4_i, Q => - \s_coarse_time[18]_net_1\); - - \secondary_cpt_RNO[9]\ : XOR2 - port map(A => secondary_cpt_c8, B => - \secondary_cpt[9]_net_1\, Y => secondary_cpt_n9); - - \s_coarse_time_RNO[15]\ : AO1C - port map(A => \s_coarse_time_4[15]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_24_i); - - \latched_next_commutation_RNIJDS2[31]\ : XNOR2 - port map(A => \s_coarse_time[31]_net_1\, B => - \latched_next_commutation[31]_net_1\, Y => - s_coarse_time_1_31_i); - - \latched_next_commutation_RNO[2]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(2), Y => N_148); - - un4_s_coarse_time_I_195 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[23]\, Y => N_24_0); - - \s_coarse_time_RNO[10]\ : AO1C - port map(A => \s_coarse_time_4[10]\, B => soft_tick_2, C - => rstn, Y => un1_resetn_9_i); - - \secondary_cpt_RNO[8]\ : AX1C - port map(A => \secondary_cpt[7]_net_1\, B => - secondary_cpt_c6, C => \secondary_cpt[8]_net_1\, Y => - secondary_cpt_n8); - - \p_next_commutation_RNIOEAA1[12]\ : NOR3C - port map(A => N_123_i_i_0, B => N_122_i_i_0, C => - un1_commutation_timer_3_0_a2_7, Y => - un1_commutation_timer_3_0_a2_19); - - un4_s_coarse_time_I_31 : XOR2 - port map(A => N_141, B => \s_coarse_time[6]_net_1\, Y => - I_31_7); - - \cpt[4]\ : DFN1C1 - port map(D => I_20_9, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[4]\); - - \p_next_commutation_RNIGV4L[30]\ : XA1A - port map(A => \p_next_commutation[30]_net_1\, B => - next_commutation(30), C => N_141_i_i_0, Y => - un1_commutation_timer_3_0_a2_15); - - \cpt[5]\ : DFN1C1 - port map(D => I_24_10, CLK => clk_div_0, CLR => reset_i_0, - Q => \fine_time[5]\); - - flag_RNI02MA2 : MX2 - port map(A => I_66_5, B => coarse_time_load(11), S => - \flag\, Y => \s_coarse_time_4[11]\); - - \p_next_commutation[7]\ : DFN1E1 - port map(D => next_commutation(7), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[7]_net_1\); - - \secondary_cpt_RNIIVNB[3]\ : NOR2B - port map(A => secondary_cpt_c2, B => - \secondary_cpt[3]_net_1\, Y => secondary_cpt_c3); - - \secondary_cpt[14]\ : DFN1E0C1 - port map(D => secondary_cpt_n14, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[14]_net_1\); - - \p_next_commutation_RNI5EJA[29]\ : XNOR2 - port map(A => next_commutation(29), B => - \p_next_commutation[29]_net_1\, Y => N_139_i_i_0); - - \s_coarse_time[7]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[7]\, CLK => clk_div_3, PRE - => un1_soft_tick_11_i, CLR => un1_resetn_32_i, Q => - \s_coarse_time[7]_net_1\); - - \secondary_cpt_RNIIVHK[5]\ : NOR3C - port map(A => \secondary_cpt[5]_net_1\, B => - secondary_cpt_c4, C => \secondary_cpt[6]_net_1\, Y => - secondary_cpt_c6); - - \p_next_commutation_RNION5L[24]\ : XA1A - port map(A => \p_next_commutation[24]_net_1\, B => - next_commutation(24), C => N_135_i_i_0, Y => - un1_commutation_timer_3_0_a2_12); - - un4_s_coarse_time_I_16 : AND3 - port map(A => \s_coarse_time[0]_net_1\, B => - \s_coarse_time[1]_net_1\, C => \s_coarse_time[2]_net_1\, - Y => \DWACT_FINC_E_0[0]\); - - un4_s_coarse_time_I_34 : AND3 - port map(A => \s_coarse_time[3]_net_1\, B => - \s_coarse_time[4]_net_1\, C => \s_coarse_time[5]_net_1\, - Y => \DWACT_FINC_E[2]\); - - un1_cpt_next_commutation_I_100 : AND2 - port map(A => \cpt_next_commutation[6]_net_1\, B => - \cpt_next_commutation[7]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_2[0]\); - - \p_next_commutation_RNI1AJA[19]\ : XNOR2 - port map(A => next_commutation(19), B => - \p_next_commutation[19]_net_1\, Y => N_129_i_i_0); - - flag_RNI9PC92 : MX2 - port map(A => I_56_5, B => coarse_time_load(10), S => - \flag\, Y => \s_coarse_time_4[10]\); - - un1_cpt_next_commutation_I_82 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_1[0]\, B => - \cpt_next_commutation[10]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_4[0]\); - - un4_s_coarse_time_I_104 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[11]\, Y => N_88); - - \p_next_commutation[27]\ : DFN1E1 - port map(D => next_commutation(27), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[27]_net_1\); - - \s_coarse_time_RNO[22]\ : AO1C - port map(A => \s_coarse_time_4[22]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_5_i); - - \secondary_cpt_RNIHVJH[1]\ : OR3C - port map(A => s_coarse_time38lto5_0, B => - s_coarse_time38lto1, C => s_coarse_time38lto5_1, Y => - s_coarse_time38lt16); - - flag_0_RNI68PK2 : MX2 - port map(A => I_115_3, B => coarse_time_load(18), S => - \flag_0\, Y => \s_coarse_time_4[18]\); - - un9_cpt_I_56 : XOR2 - port map(A => N_34, B => \fine_time[10]\, Y => I_56_6); - - un4_s_coarse_time_I_216 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[26]\, Y => N_9_0); - - \s_coarse_time[3]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[3]\, CLK => clk_div_3, PRE - => un1_soft_tick_6_i, CLR => un1_resetn_31_i, Q => - \s_coarse_time[3]_net_1\); - - \latched_next_commutation_RNIN2LA[9]\ : XNOR2 - port map(A => \s_coarse_time[9]_net_1\, B => - \latched_next_commutation[9]_net_1\, Y => - s_coarse_time_1_9_i); - - \p_next_commutation[19]\ : DFN1E1 - port map(D => next_commutation(19), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[19]_net_1\); - - \cpt_RNIVBOC[12]\ : NOR3A - port map(A => flag_1_sqmuxa_i_o3_8, B => \fine_time[3]\, C - => \fine_time[12]\, Y => flag_1_sqmuxa_i_o3_12); - - \previous_coarse_time_load[5]\ : DFN1E0C0 - port map(D => coarse_time_load(5), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[5]_net_1\); - - flag_0_RNIUJ7R2 : MX2 - port map(A => I_156_3, B => coarse_time_load(23), S => - \flag_0\, Y => \s_coarse_time_4[23]\); - - \s_coarse_time[2]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[2]\, CLK => clk_div_3, PRE - => un1_soft_tick_14_i, CLR => un1_resetn_30_i, Q => - \s_coarse_time[2]_net_1\); - - un9_cpt_I_66 : XOR2 - port map(A => N_27, B => \fine_time[11]\, Y => I_66_6); - - \s_coarse_time_RNO_0[21]\ : MX2 - port map(A => \s_coarse_time_4[21]\, B => - \s_coarse_time[21]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[21]\); - - un4_s_coarse_time_I_69 : AND3 - port map(A => \s_coarse_time[9]_net_1\, B => - \s_coarse_time[10]_net_1\, C => \s_coarse_time[11]_net_1\, - Y => \DWACT_FINC_E_0[7]\); - - \s_coarse_time_RNO_0[23]\ : MX2 - port map(A => \s_coarse_time_4[23]\, B => - \s_coarse_time[23]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[23]\); - - \state_RNICEBF[0]\ : NOR3A - port map(A => \un1_cpt_0_a3_1[0]\, B => \fine_time[16]\, C - => \state[0]_net_1\, Y => \un1_cpt_0_a3_9[0]\); - - \secondary_cpt[13]\ : DFN1E0C1 - port map(D => secondary_cpt_n13, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[13]_net_1\); - - \latched_next_commutation_RNIJHS2[23]\ : XNOR2 - port map(A => \s_coarse_time[23]_net_1\, B => - \latched_next_commutation[23]_net_1\, Y => - s_coarse_time_1_23_i); - - un1_cpt_next_commutation_I_108 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_5[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_6[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_2[0]\); - - \commutation_timer_6_0__m3_i\ : MX2A - port map(A => s_coarse_time_1_NE, B => N_243, S => - \commutation_timer[0]_net_1\, Y => N_77); - - \s_coarse_time_RNO_0[24]\ : MX2 - port map(A => \s_coarse_time_4[24]\, B => - \s_coarse_time[24]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[24]\); - - un4_s_coarse_time_I_121 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \s_coarse_time[18]_net_1\, Y => N_76); - - \latched_next_commutation_RNO[9]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(9), Y => N_155); - - un1_cpt_next_commutation_I_70 : XOR2 - port map(A => \cpt_next_commutation[16]_net_1\, B => - \DWACT_ADD_CI_0_g_array_4[0]\, Y => I_70); - - \previous_coarse_time_load_RNICP96[24]\ : XNOR2 - port map(A => coarse_time_load(24), B => - \previous_coarse_time_load[24]_net_1\, Y => - previous_coarse_time_load_1_24_i); - - sirq1_RNO : NOR2 - port map(A => s_coarse_time_1_NE_0, B => - \commutation_timer[0]_net_1\, Y => - commutation_timer_0_sqmuxa_1); - - \secondary_cpt_RNI7HU21[10]\ : NOR3C - port map(A => \secondary_cpt[9]_net_1\, B => - secondary_cpt_c8, C => \secondary_cpt[10]_net_1\, Y => - secondary_cpt_c10); - - \latched_next_commutation_RNO[4]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(4), Y => N_150); - - \s_coarse_time_RNO_0[25]\ : MX2 - port map(A => \s_coarse_time_4[25]\, B => - \s_coarse_time[25]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[25]\); - - \s_coarse_time_RNO_1[11]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[11]\, Y - => un1_soft_tick_7_i); - - un4_s_coarse_time_I_202 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \s_coarse_time[27]_net_1\, Y => N_19); - - \latched_next_commutation_RNI03CE1[16]\ : NOR3C - port map(A => s_coarse_time_1_NE_21, B => - s_coarse_time_1_NE_20, C => s_coarse_time_1_NE_27, Y => - s_coarse_time_1_NE_29); - - un9_cpt_I_91 : XOR2 - port map(A => N_9_1, B => \fine_time[15]\, Y => I_91_4); - - \latched_next_commutation_RNILPS2[16]\ : XNOR2 - port map(A => \s_coarse_time[16]_net_1\, B => - \latched_next_commutation[16]_net_1\, Y => - s_coarse_time_1_16_i); - - \s_coarse_time_RNO_1[13]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[13]\, Y - => un1_soft_tick_12_i); - - \s_coarse_time[16]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[16]\, CLK => clk_div_2, PRE - => un1_soft_tick_17_i, CLR => un1_resetn_27_i, Q => - \s_coarse_time[16]_net_1\); - - \p_next_commutation[13]\ : DFN1E1 - port map(D => next_commutation(13), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[13]_net_1\); - - \latched_next_commutation[26]\ : DFN1E0P0 - port map(D => N_172, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[26]_net_1\); - - \s_coarse_time_RNO_1[2]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[2]\, Y => - un1_soft_tick_14_i); - - un1_cpt_next_commutation_I_59 : XOR2 - port map(A => \cpt_next_commutation[13]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_5[0]\, Y => I_59); - - \cpt_RNIAJA9[10]\ : NOR3C - port map(A => \fine_time[13]\, B => \fine_time[10]\, C => - \un1_cpt_0_a3_5[0]\, Y => \un1_cpt_0_a3_11[0]\); - - \s_coarse_time_RNO[12]\ : AO1C - port map(A => \s_coarse_time_4[12]\, B => soft_tick_2, C - => rstn, Y => un1_resetn_25_i); - - flag_RNIU3QU1 : MX2 - port map(A => I_45_4, B => coarse_time_load(8), S => \flag\, - Y => \s_coarse_time_4[8]\); - - flag_0_RNIL1RT2 : MX2 - port map(A => I_173_3, B => coarse_time_load(25), S => - \flag_0\, Y => \s_coarse_time_4[25]\); - - \previous_coarse_time_load_RNIE9A6[16]\ : XNOR2 - port map(A => coarse_time_load(16), B => - \previous_coarse_time_load[16]_net_1\, Y => - previous_coarse_time_load_1_16_i); - - un9_cpt_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\, - C => \fine_time[6]\, Y => N_47); - - un4_s_coarse_time_I_108 : AND3 - port map(A => \s_coarse_time[15]_net_1\, B => - \s_coarse_time[16]_net_1\, C => \s_coarse_time[17]_net_1\, - Y => \DWACT_FINC_E[12]\); - - \secondary_cpt_RNINVR5[1]\ : OR2 - port map(A => \secondary_cpt[1]_net_1\, B => - \secondary_cpt[0]_net_1\, Y => s_coarse_time38lto1); - - \latched_next_commutation_RNINPS2[25]\ : XNOR2 - port map(A => \s_coarse_time[25]_net_1\, B => - \latched_next_commutation[25]_net_1\, Y => - s_coarse_time_1_25_i); - - \s_coarse_time_RNO_0[1]\ : MX2 - port map(A => \s_coarse_time_4[1]\, B => - \s_coarse_time[1]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[1]\); - - un9_cpt_I_8 : NOR2B - port map(A => \fine_time[1]\, B => \fine_time[0]\, Y => - N_68); - - \s_coarse_time_RNO_1[14]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[14]\, Y - => un1_soft_tick_18_i); - - \latched_next_commutation_RNIBAKA[3]\ : XNOR2 - port map(A => \s_coarse_time[3]_net_1\, B => - \latched_next_commutation[3]_net_1\, Y => - s_coarse_time_1_3_i); - - \s_coarse_time_RNO_0[5]\ : MX2 - port map(A => \s_coarse_time_4[5]\, B => - \s_coarse_time[5]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[5]\); - - un9_cpt_I_59 : AND3 - port map(A => \fine_time[6]\, B => \fine_time[7]\, C => - \fine_time[8]\, Y => \DWACT_FINC_E_0[5]\); - - \previous_coarse_time_load_RNIAS9A[2]\ : XA1A - port map(A => \previous_coarse_time_load[2]_net_1\, B => - coarse_time_load(2), C => previous_coarse_time_load_1_3_i, - Y => previous_coarse_time_load_1_NE_1); - - un9_cpt_I_69 : AND3 - port map(A => \fine_time[9]\, B => \fine_time[10]\, C => - \fine_time[11]\, Y => \DWACT_FINC_E[7]\); - - \s_coarse_time_RNO_1[15]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[15]\, Y - => un1_soft_tick_3_i); - - \p_next_commutation[1]\ : DFN1E1 - port map(D => next_commutation(1), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[1]_net_1\); - - flag_0_RNIBMKO2 : MX2 - port map(A => I_136_3, B => coarse_time_load(21), S => - \flag_0\, Y => \s_coarse_time_4[21]\); - - \s_coarse_time_RNO_0[22]\ : MX2 - port map(A => \s_coarse_time_4[22]\, B => - \s_coarse_time[22]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[22]\); - - \latched_next_commutation_RNIV9T2[29]\ : XNOR2 - port map(A => \s_coarse_time[29]_net_1\, B => - \latched_next_commutation[29]_net_1\, Y => - s_coarse_time_1_29_i); - - \p_next_commutation_RNIPLIA[23]\ : XNOR2 - port map(A => next_commutation(23), B => - \p_next_commutation[23]_net_1\, Y => N_133_i_i_0); - - un4_s_coarse_time_I_19 : NOR2B - port map(A => \s_coarse_time[3]_net_1\, B => - \DWACT_FINC_E_0[0]\, Y => N_149); - - un1_cpt_next_commutation_I_92 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_2[0]\, B => - \cpt_next_commutation[14]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_6[0]\); - - \s_coarse_time_RNO[27]\ : AO1C - port map(A => \s_coarse_time_4[27]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_20_i); - - un9_cpt_I_98 : XOR2 - port map(A => N_4_0, B => \fine_time[16]\, Y => I_98_4); - - un4_s_coarse_time_I_203 : XOR2 - port map(A => N_19, B => \s_coarse_time[28]_net_1\, Y => - I_203_3); - - un9_cpt_I_41 : AND2 - port map(A => \fine_time[6]\, B => \fine_time[7]\, Y => - \DWACT_FINC_E_0[3]\); - - un9_cpt_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[1]\, - C => \fine_time[5]\, Y => N_52_0); - - \latched_next_commutation_RNIJQKA[7]\ : XNOR2 - port map(A => \s_coarse_time[7]_net_1\, B => - \latched_next_commutation[7]_net_1\, Y => - s_coarse_time_1_7_i); - - un3_grspw_tick_0 : OR2A - port map(A => rstn, B => soft_tick_0, Y => reset_i_0_0); - - GND_i : GND - port map(Y => \GND\); - - \s_coarse_time[4]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[4]\, CLK => clk_div_3, PRE - => un1_soft_tick_5_i, CLR => un1_resetn_17_i, Q => - \s_coarse_time[4]_net_1\); - - un4_s_coarse_time_I_83 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E_0[7]\, - C => \DWACT_FINC_E[8]\, Y => N_103); - - \latched_next_commutation_RNI0UHB[12]\ : NOR3C - port map(A => s_coarse_time_1_13_i, B => - s_coarse_time_1_12_i, C => s_coarse_time_1_NE_7, Y => - s_coarse_time_1_NE_19); - - \s_coarse_time[12]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[12]\, CLK => clk_div_2, PRE - => un1_soft_tick_13_i, CLR => un1_resetn_25_i, Q => - \s_coarse_time[12]_net_1\); - - \secondary_cpt_RNII5H8[15]\ : NOR2 - port map(A => \secondary_cpt[15]_net_1\, B => - \secondary_cpt[6]_net_1\, Y => s_coarse_time38lto16_2); - - \latched_next_commutation_RNI06K61[10]\ : NOR3C - port map(A => s_coarse_time_1_NE_5, B => - s_coarse_time_1_NE_4, C => s_coarse_time_1_NE_19, Y => - s_coarse_time_1_NE_25); - - un1_cpt_next_commutation_I_1 : AND2 - port map(A => \cpt_next_commutation[0]_net_1\, B => - \commutation_timer_RNI3EI8[0]_net_1\, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - \s_coarse_time_RNO_1[12]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[12]\, Y - => un1_soft_tick_13_i); - - \latched_next_commutation[13]\ : DFN1E0P0 - port map(D => N_159, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[13]_net_1\); - - \p_next_commutation_RNI3AJA[28]\ : XNOR2 - port map(A => next_commutation(28), B => - \p_next_commutation[28]_net_1\, Y => N_138_i_i_0); - - \p_next_commutation_RNIG75L[22]\ : XA1A - port map(A => \p_next_commutation[22]_net_1\, B => - next_commutation(22), C => N_133_i_i_0, Y => - un1_commutation_timer_3_0_a2_11); - - un9_cpt_I_72 : NOR2B - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y - => N_22); - - un1_cpt_next_commutation_I_91 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_4[0]\); - - \previous_coarse_time_load_RNI6996[12]\ : XNOR2 - port map(A => coarse_time_load(12), B => - \previous_coarse_time_load[12]_net_1\, Y => - previous_coarse_time_load_1_12_i); - - flag_0_RNIF4P13 : MX2 - port map(A => I_203_3, B => coarse_time_load(28), S => - \flag_0\, Y => \s_coarse_time_4[28]\); - - \secondary_cpt_RNO[13]\ : XOR2 - port map(A => secondary_cpt_c12, B => - \secondary_cpt[13]_net_1\, Y => secondary_cpt_n13); - - un9_cpt_I_34 : AND3 - port map(A => \fine_time[3]\, B => \fine_time[4]\, C => - \fine_time[5]\, Y => \DWACT_FINC_E_0[2]\); - - \coarse_time[7]\ : DFN1C0 - port map(D => \s_coarse_time[7]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(7)); - - un1_cpt_next_commutation_I_57 : XOR2 - port map(A => \cpt_next_commutation[12]_net_1\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, Y => I_57); - - \cpt_next_commutation_RNIMQPB[16]\ : NOR3A - port map(A => \cpt_next_commutation[16]_net_1\, B => - \cpt_next_commutation[0]_net_1\, C => - \cpt_next_commutation[4]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_3); - - \secondary_cpt_RNIKPCE[12]\ : NOR3C - port map(A => \secondary_cpt[6]_net_1\, B => - \secondary_cpt[12]_net_1\, C => - secondary_cpt_c12_m6_0_a2_1, Y => - secondary_cpt_c12_m6_0_a2_4); - - un9_cpt_I_73 : XOR2 - port map(A => N_22, B => \fine_time[12]\, Y => I_73_4); - - flag_RNI73OT : MX2 - port map(A => I_13_12, B => coarse_time_load(3), S => - \flag\, Y => \s_coarse_time_4[3]\); - - \coarse_time[13]\ : DFN1C0 - port map(D => \s_coarse_time[13]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(13)); - - \p_next_commutation[5]\ : DFN1E1 - port map(D => next_commutation(5), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[5]_net_1\); - - \cpt_RNO[1]\ : NOR2B - port map(A => I_5_9, B => \un1_cpt_0[0]\, Y => \cpt_5[1]\); - - \secondary_cpt[8]\ : DFN1E0C1 - port map(D => secondary_cpt_n8, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[8]_net_1\); - - \latched_next_commutation_RNINTS2[17]\ : XNOR2 - port map(A => \s_coarse_time[17]_net_1\, B => - \latched_next_commutation[17]_net_1\, Y => - s_coarse_time_1_17_i); - - un9_cpt_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\, - C => \DWACT_FINC_E_0[3]\, Y => \DWACT_FINC_E[4]\); - - \p_next_commutation[28]\ : DFN1E1 - port map(D => next_commutation(28), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[28]_net_1\); - - \s_coarse_time_RNO[17]\ : AO1C - port map(A => \s_coarse_time_4[17]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_14_i); - - \p_next_commutation_RNIOU9A1[20]\ : NOR3C - port map(A => N_131_i_i_0, B => N_130_i_i_0, C => - un1_commutation_timer_3_0_a2_11, Y => - un1_commutation_timer_3_0_a2_21); - - un4_s_coarse_time_I_80 : AND2 - port map(A => \s_coarse_time[12]_net_1\, B => - \s_coarse_time[13]_net_1\, Y => \DWACT_FINC_E[8]\); - - \s_coarse_time_RNO[23]\ : AO1C - port map(A => \s_coarse_time_4[23]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_16_i); - - \secondary_cpt_RNO[6]\ : AX1C - port map(A => \secondary_cpt[5]_net_1\, B => - secondary_cpt_c4, C => \secondary_cpt[6]_net_1\, Y => - secondary_cpt_n6); - - \latched_next_commutation_RNO[17]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(17), - Y => N_163); - - flag_0_RNI43UP2 : MX2 - port map(A => I_143_3, B => coarse_time_load(22), S => - \flag_0\, Y => \s_coarse_time_4[22]\); - - \latched_next_commutation[17]\ : DFN1E0P0 - port map(D => N_163, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[17]_net_1\); - - \s_coarse_time_RNO_0[8]\ : MX2 - port map(A => \s_coarse_time_4[8]\, B => - \s_coarse_time[8]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[8]\); - - \cpt_next_commutation[5]\ : DFN1C0 - port map(D => I_60, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[5]_net_1\); - - \coarse_time[15]\ : DFN1C0 - port map(D => \s_coarse_time[15]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(15)); - - \latched_next_commutation_RNO[3]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(3), Y => N_149_0); - - \cpt_next_commutation[8]\ : DFN1C0 - port map(D => I_66_4, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[8]_net_1\); - - \s_coarse_time_RNO[3]\ : AO1C - port map(A => \s_coarse_time_4[3]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_31_i); - - \previous_coarse_time_load_RNICPJK[4]\ : NOR3C - port map(A => previous_coarse_time_load_1_5_i, B => - previous_coarse_time_load_1_4_i, C => - previous_coarse_time_load_1_NE_3, Y => - previous_coarse_time_load_1_NE_17); - - \s_coarse_time[5]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[5]\, CLK => clk_div_3, PRE - => un1_soft_tick_4_i, CLR => un1_resetn_26_i, Q => - \s_coarse_time[5]_net_1\); - - un1_cpt_next_commutation_I_40 : XOR2 - port map(A => \cpt_next_commutation[0]_net_1\, B => - \commutation_timer_RNI3EI8[0]_net_1\, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \cpt_RNIVULI[2]\ : NOR3C - port map(A => flag_1_sqmuxa_i_o3_2, B => - flag_1_sqmuxa_i_o3_1, C => flag_1_sqmuxa_i_o3_10, Y => - flag_1_sqmuxa_i_o3_13); - - un1_cpt_next_commutation_I_54 : XOR2 - port map(A => \cpt_next_commutation[3]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_54); - - \s_coarse_time_RNO[29]\ : AO1C - port map(A => \s_coarse_time_4[29]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_11_i); - - \p_next_commutation[14]\ : DFN1E1 - port map(D => next_commutation(14), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[14]_net_1\); - - \latched_next_commutation_RNO[31]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(31), - Y => N_177); - - flag_RNIBKIE2 : MX2 - port map(A => I_84_3, B => coarse_time_load(14), S => - \flag\, Y => \s_coarse_time_4[14]\); - - un4_s_coarse_time_I_146 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => - \s_coarse_time[21]_net_1\, C => \s_coarse_time[22]_net_1\, - Y => \DWACT_FINC_E[33]\); - - un4_s_coarse_time_I_129 : XOR2 - port map(A => N_71, B => \s_coarse_time[20]_net_1\, Y => - I_129_3); - - \cpt_next_commutation[11]\ : DFN1C0 - port map(D => I_56_4, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[11]_net_1\); - - \state_RNIEG3J2_1[0]\ : NOR2 - port map(A => N_25, B => N_24, Y => \un1_cpt[0]\); - - \state_RNIEG3J2[0]\ : NOR2 - port map(A => N_25, B => N_24, Y => \un1_cpt_0[0]\); - - flag_RNIOEVB2 : MX2 - port map(A => I_73_3, B => coarse_time_load(12), S => - \flag\, Y => \s_coarse_time_4[12]\); - - \secondary_cpt_RNI204E1[10]\ : NOR3C - port map(A => secondary_cpt_c12_m6_0_a2_5, B => - secondary_cpt_c12_m6_0_a2_4, C => secondary_cpt_c3, Y => - secondary_cpt_c12); - - \p_next_commutation_RNI4LPA[0]\ : XA1A - port map(A => \p_next_commutation[0]_net_1\, B => - next_commutation(0), C => N_111_i_i_0, Y => - un1_commutation_timer_3_0_a2_0); - - \latched_next_commutation[9]\ : DFN1E0P0 - port map(D => N_155, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[9]_net_1\); - - un4_s_coarse_time_I_122 : XOR2 - port map(A => N_76, B => \s_coarse_time[19]_net_1\, Y => - I_122_3); - - \p_next_commutation_RNI086L[26]\ : XA1A - port map(A => \p_next_commutation[26]_net_1\, B => - next_commutation(26), C => N_137_i_i_0, Y => - un1_commutation_timer_3_0_a2_13); - - \latched_next_commutation[24]\ : DFN1E0P0 - port map(D => N_170, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[24]_net_1\); - - \s_coarse_time_RNO[13]\ : AO1C - port map(A => \s_coarse_time_4[13]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_18_i); - - un9_cpt_I_52 : XOR2 - port map(A => N_37, B => \fine_time[9]\, Y => I_52_5); - - \latched_next_commutation_RNI0M6N[24]\ : NOR3C - port map(A => s_coarse_time_1_NE_13, B => - s_coarse_time_1_NE_12, C => s_coarse_time_1_NE_23, Y => - s_coarse_time_1_NE_27); - - \s_coarse_time[0]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[0]\, CLK => clk_div_2, PRE - => un1_soft_tick_25_i, CLR => un1_resetn_29_i, Q => - \s_coarse_time[0]_net_1\); - - un9_cpt_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\, - C => \DWACT_FINC_E_0[5]\, Y => \DWACT_FINC_E[6]\); - - \coarse_time_RNIGHP5[0]\ : INV - port map(A => \coarse_time[0]_net_1\, Y => coarse_time_i(0)); - - flag_RNIHG6O1 : MX2 - port map(A => I_38_5, B => coarse_time_load(7), S => \flag\, - Y => \s_coarse_time_4[7]\); - - \s_coarse_time_RNO[19]\ : AO1C - port map(A => \s_coarse_time_4[19]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_12_i); - - un4_s_coarse_time_I_30 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[1]\, - C => \s_coarse_time[5]_net_1\, Y => N_141); - - \latched_next_commutation_RNI0C3A5_0[10]\ : OR2B - port map(A => s_coarse_time_1_NE_29, B => - s_coarse_time_1_NE_28, Y => s_coarse_time_1_NE); - - \latched_next_commutation[28]\ : DFN1E0P0 - port map(D => N_174, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[28]_net_1\); - - un9_cpt_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \fine_time[3]\, C => - \fine_time[4]\, Y => N_57); - - sirq2 : DFN1E1C0 - port map(D => \commutation_timer[0]_net_1\, CLK => lclk_c, - CLR => rstn, E => N_6, Q => pirq(13)); - - flag_0_RNIP8HS2 : MX2 - port map(A => I_166_3, B => coarse_time_load(24), S => - \flag_0\, Y => \s_coarse_time_4[24]\); - - \latched_next_commutation[29]\ : DFN1E0P0 - port map(D => N_175, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[29]_net_1\); - - \coarse_time[1]\ : DFN1C0 - port map(D => \s_coarse_time[1]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(1)); - - flag_0_RNIB25I2 : MX2 - port map(A => I_98_3, B => coarse_time_load(16), S => - \flag_0\, Y => \s_coarse_time_4[16]\); - - \s_coarse_time[14]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[14]\, CLK => clk_div_2, PRE - => un1_soft_tick_18_i, CLR => un1_resetn_3_i, Q => - \s_coarse_time[14]_net_1\); - - \s_coarse_time_RNO_1[4]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[4]\, Y => - un1_soft_tick_5_i); - - \previous_coarse_time_load_RNIM1B6[29]\ : XNOR2 - port map(A => coarse_time_load(29), B => - \previous_coarse_time_load[29]_net_1\, Y => - previous_coarse_time_load_1_29_i); - - un4_s_coarse_time_I_125 : AND2 - port map(A => \s_coarse_time[18]_net_1\, B => - \s_coarse_time[19]_net_1\, Y => \DWACT_FINC_E[14]\); - - flag_RNIVF4N : MX2 - port map(A => I_9_8, B => coarse_time_load(2), S => \flag\, - Y => \s_coarse_time_4[2]\); - - un4_s_coarse_time_I_38 : XOR2 - port map(A => N_136, B => \s_coarse_time[7]_net_1\, Y => - I_38_5); - - \cpt[10]\ : DFN1C1 - port map(D => I_56_6, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[10]\); - - \p_next_commutation[10]\ : DFN1E1 - port map(D => next_commutation(10), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[10]_net_1\); - - \latched_next_commutation[20]\ : DFN1E0P0 - port map(D => N_166, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[20]_net_1\); - - \latched_next_commutation_RNIK7Q5[18]\ : XA1A - port map(A => \latched_next_commutation[18]_net_1\, B => - \s_coarse_time[18]_net_1\, C => s_coarse_time_1_19_i, Y - => s_coarse_time_1_NE_9); - - \commutation_timer_RNINQD9E_0[0]\ : AO1 - port map(A => un1_commutation_timer_3_0_a2_30, B => - s_coarse_time_1_NE, C => \commutation_timer[0]_net_1\, Y - => un1_commutation_timer_3); - - \latched_next_commutation_RNO[27]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(27), - Y => N_173); - - \p_next_commutation[30]\ : DFN1E1 - port map(D => next_commutation(30), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[30]_net_1\); - - \s_coarse_time[21]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[21]\, CLK => clk_div_3, PRE - => un1_soft_tick_28_i, CLR => un1_resetn_10_i, Q => - \s_coarse_time[21]_net_1\); - - \p_next_commutation[3]\ : DFN1E1 - port map(D => next_commutation(3), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[3]_net_1\); - - \cpt_next_commutation_RNO[0]\ : OA1A - port map(A => \commutation_timer[0]_net_1\, B => N_243, C - => \DWACT_ADD_CI_0_partial_sum[0]\, Y => N_11); - - \s_coarse_time[27]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[27]\, CLK => clk_div_3, PRE - => un1_soft_tick_21_i, CLR => un1_resetn_20_i, Q => - \s_coarse_time[27]_net_1\); - - \previous_coarse_time_load[14]\ : DFN1E0C0 - port map(D => coarse_time_load(14), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[14]_net_1\); - - \s_coarse_time_RNO_0[3]\ : MX2 - port map(A => \s_coarse_time_4[3]\, B => - \s_coarse_time[3]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[3]\); - - \secondary_cpt_RNIVVR5[4]\ : NOR2B - port map(A => \secondary_cpt[5]_net_1\, B => - \secondary_cpt[4]_net_1\, Y => s_coarse_time38lto5_1); - - \s_coarse_time_RNO_0[30]\ : MX2 - port map(A => \s_coarse_time_4[30]\, B => - \s_coarse_time[30]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[30]\); - - un4_s_coarse_time_I_206 : AND2 - port map(A => \s_coarse_time[27]_net_1\, B => - \s_coarse_time[28]_net_1\, Y => \DWACT_FINC_E[25]\); - - un9_cpt_I_97 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E_0[10]\, - C => \fine_time[15]\, Y => N_4_0); - - \previous_coarse_time_load_RNIKMV43[20]\ : NOR3C - port map(A => previous_coarse_time_load_1_NE_21, B => - previous_coarse_time_load_1_NE_20, C => - previous_coarse_time_load_1_NE_27, Y => - previous_coarse_time_load_1_NE_29); - - flag : DFN1E0C1 - port map(D => flag_1, CLK => clk_div_0, CLR => reset_i_0, E - => flag_1_sqmuxa_1, Q => \flag\); - - un1_cpt_next_commutation_I_55 : XOR2 - port map(A => \cpt_next_commutation[10]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_1[0]\, Y => I_55); - - un4_s_coarse_time_I_179 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[20]\, Y => \DWACT_FINC_E[21]\); - - \secondary_cpt_RNO[7]\ : XOR2 - port map(A => secondary_cpt_c6, B => - \secondary_cpt[7]_net_1\, Y => secondary_cpt_n7); - - \previous_coarse_time_load[6]\ : DFN1E0C0 - port map(D => coarse_time_load(6), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[6]_net_1\); - - \latched_next_commutation[25]\ : DFN1E0P0 - port map(D => N_171, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[25]_net_1\); - - \latched_next_commutation[16]\ : DFN1E0P0 - port map(D => N_162, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[16]_net_1\); - - \secondary_cpt_RNI50S5[8]\ : NOR2B - port map(A => \secondary_cpt[7]_net_1\, B => - \secondary_cpt[8]_net_1\, Y => - secondary_cpt_c12_m6_0_a2_1); - - \s_coarse_time_RNO_0[0]\ : MX2A - port map(A => \s_coarse_time_4[0]\, B => - \s_coarse_time[0]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[0]\); - - \latched_next_commutation_RNO[18]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(18), - Y => N_164); - - \secondary_cpt_RNIVU5B[14]\ : NOR2 - port map(A => \secondary_cpt[13]_net_1\, B => - \secondary_cpt[14]_net_1\, Y => s_coarse_time38lto16_1); - - un4_s_coarse_time_I_172 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[19]\, Y => N_40); - - flag_RNI5TIH1 : MX2 - port map(A => I_31_7, B => coarse_time_load(6), S => \flag\, - Y => \s_coarse_time_4[6]\); - - un1_cpt_next_commutation_I_68 : XOR2 - port map(A => \cpt_next_commutation[2]_net_1\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_68); - - un1_cpt_next_commutation_I_66 : XOR2 - port map(A => \cpt_next_commutation[8]_net_1\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, Y => I_66_4); - - \s_coarse_time_RNO_1[5]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[5]\, Y => - un1_soft_tick_4_i); - - \cpt_RNIDJA9[7]\ : NOR3A - port map(A => flag_1_sqmuxa_i_o3_4, B => \fine_time[10]\, C - => \fine_time[7]\, Y => flag_1_sqmuxa_i_o3_10); - - \coarse_time[21]\ : DFN1C0 - port map(D => \s_coarse_time[21]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(21)); - - un4_s_coarse_time_I_62 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E_0[6]\); - - \previous_coarse_time_load[2]\ : DFN1E0C0 - port map(D => coarse_time_load(2), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[2]_net_1\); - - \latched_next_commutation[30]\ : DFN1E0P0 - port map(D => N_176, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[30]_net_1\); - - \coarse_time[30]\ : DFN1C0 - port map(D => \s_coarse_time[30]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(30)); - - \previous_coarse_time_load_RNI8196[31]\ : XNOR2 - port map(A => coarse_time_load(31), B => - \previous_coarse_time_load[31]_net_1\, Y => - previous_coarse_time_load_1_31_i); - - un4_s_coarse_time_I_51 : NOR2B - port map(A => \s_coarse_time[8]_net_1\, B => - \DWACT_FINC_E_0[4]\, Y => N_126); - - un4_s_coarse_time_I_41 : AND2 - port map(A => \s_coarse_time[6]_net_1\, B => - \s_coarse_time[7]_net_1\, Y => \DWACT_FINC_E[3]\); - - un9_cpt_I_90 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E_0[9]\, Y => N_9_1); - - \latched_next_commutation[5]\ : DFN1E0P0 - port map(D => N_151, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[5]_net_1\); - - \s_coarse_time_RNO_1[20]\ : NOR2B - port map(A => soft_tick_3, B => \s_coarse_time_4[20]\, Y - => un1_soft_tick_23_i); - - un4_s_coarse_time_I_5 : XOR2 - port map(A => \s_coarse_time[0]_net_1\, B => - \s_coarse_time[1]_net_1\, Y => I_5_8); - - \latched_next_commutation_RNO[15]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(15), Y => N_161); - - \cpt_next_commutation_RNO[16]\ : OA1A - port map(A => \commutation_timer[0]_net_1\, B => N_243, C - => I_70, Y => N_9); - - \p_next_commutation_RNISJAA2[8]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_5, B => - un1_commutation_timer_3_0_a2_4, C => - un1_commutation_timer_3_0_a2_19, Y => - un1_commutation_timer_3_0_a2_25); - - \cpt[15]\ : DFN1C1 - port map(D => I_91_4, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[15]\); - - \previous_coarse_time_load[17]\ : DFN1E0C0 - port map(D => coarse_time_load(17), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[17]_net_1\); - - \secondary_cpt_RNO[1]\ : XOR2 - port map(A => \secondary_cpt[1]_net_1\, B => - \secondary_cpt[0]_net_1\, Y => secondary_cpt_n1); - - \previous_coarse_time_load[10]\ : DFN1E0C0 - port map(D => coarse_time_load(10), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[10]_net_1\); - - \p_next_commutation[26]\ : DFN1E1 - port map(D => next_commutation(26), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[26]_net_1\); - - \previous_coarse_time_load_RNIQS9A[6]\ : XA1A - port map(A => \previous_coarse_time_load[6]_net_1\, B => - coarse_time_load(6), C => previous_coarse_time_load_1_7_i, - Y => previous_coarse_time_load_1_NE_3); - - \cpt_next_commutation_RNILU1P[5]\ : NOR3B - port map(A => sirq2_1_sqmuxa_i_a2_2, B => - sirq2_1_sqmuxa_i_a2_3, C => - \cpt_next_commutation[5]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_5); - - \previous_coarse_time_load_RNI8U45[4]\ : XNOR2 - port map(A => coarse_time_load(4), B => - \previous_coarse_time_load[4]_net_1\, Y => - previous_coarse_time_load_1_4_i); - - \p_next_commutation[17]\ : DFN1E1 - port map(D => next_commutation(17), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[17]_net_1\); - - \s_coarse_time_RNO_1[30]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[30]\, Y - => un1_soft_tick_16_i); - - un4_s_coarse_time_I_156 : XOR2 - port map(A => N_52, B => \s_coarse_time[23]_net_1\, Y => - I_156_3); - - un1_cpt_next_commutation_I_106 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_1[0]\); - - \s_coarse_time_RNO_0[10]\ : MX2 - port map(A => \s_coarse_time_4[10]\, B => - \s_coarse_time[10]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[10]\); - - un4_s_coarse_time_I_173 : XOR2 - port map(A => N_40, B => \s_coarse_time[25]_net_1\, Y => - I_173_3); - - \s_coarse_time_RNO_1[7]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[7]\, Y => - un1_soft_tick_11_i); - - \cpt[1]\ : DFN1C1 - port map(D => \cpt_5[1]\, CLK => clk_div_0, CLR => - reset_i_0_1, Q => \fine_time[1]\); - - \latched_next_commutation_RNO[30]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(30), - Y => N_176); - - \cpt[9]\ : DFN1C1 - port map(D => I_52_5, CLK => clk_div_0, CLR => reset_i_0, Q - => \fine_time[9]\); - - un4_s_coarse_time_I_44 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \DWACT_FINC_E[3]\, Y => N_131); - - un9_cpt_I_94 : AND2 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E_0[9]\, - Y => \DWACT_FINC_E_0[10]\); - - \previous_coarse_time_load[30]\ : DFN1E0C0 - port map(D => coarse_time_load(30), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[30]_net_1\); - - \p_next_commutation[4]\ : DFN1E1 - port map(D => next_commutation(4), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[4]_net_1\); - - \previous_coarse_time_load[3]\ : DFN1E0C0 - port map(D => coarse_time_load(3), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[3]_net_1\); - - \p_next_commutation_RNI0M9B1[0]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_1, B => - un1_commutation_timer_3_0_a2_0, C => - un1_commutation_timer_3_0_a2_17, Y => - un1_commutation_timer_3_0_a2_24); - - \latched_next_commutation_RNI0HGA1[0]\ : NOR3C - port map(A => s_coarse_time_1_1_i, B => s_coarse_time_1_0_i, - C => s_coarse_time_1_NE_1, Y => s_coarse_time_1_NE_16); - - \previous_coarse_time_load_RNI6QHC[10]\ : XA1A - port map(A => \previous_coarse_time_load[10]_net_1\, B => - coarse_time_load(10), C => - previous_coarse_time_load_1_11_i, Y => - previous_coarse_time_load_1_NE_5); - - \coarse_time[27]\ : DFN1C0 - port map(D => \s_coarse_time[27]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(27)); - - \p_next_commutation[22]\ : DFN1E1 - port map(D => next_commutation(22), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[22]_net_1\); - - \cpt[13]\ : DFN1C1 - port map(D => I_77_4, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[13]\); - - \cpt_RNIA6G2[4]\ : NOR2 - port map(A => \fine_time[4]\, B => \fine_time[6]\, Y => - flag_1_sqmuxa_i_o3_5); - - \previous_coarse_time_load[24]\ : DFN1E0C0 - port map(D => coarse_time_load(24), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[24]_net_1\); - - \p_next_commutation_RNIOFCA1[16]\ : NOR3C - port map(A => N_127_i_i_0, B => N_126_i_i_0, C => - un1_commutation_timer_3_0_a2_9, Y => - un1_commutation_timer_3_0_a2_20); - - \s_coarse_time[9]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[9]\, CLK => clk_int, PRE => - un1_soft_tick_30_i, CLR => un1_resetn_22_i, Q => - \s_coarse_time[9]_net_1\); - - \p_next_commutation_RNIS5RA[6]\ : XA1A - port map(A => \p_next_commutation[6]_net_1\, B => - next_commutation(6), C => N_117_i_i_0, Y => - un1_commutation_timer_3_0_a2_3); - - un1_cpt_next_commutation_I_88 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - flag_RNIOSGG : MX2 - port map(A => I_5_8, B => coarse_time_load(1), S => \flag\, - Y => \s_coarse_time_4[1]\); - - un4_s_coarse_time_I_209 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[25]\, Y => N_14); - - \p_next_commutation[8]\ : DFN1E1 - port map(D => next_commutation(8), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[8]_net_1\); - - \state_RNI7OH91[0]\ : NOR3C - port map(A => flag_1_sqmuxa_i_o3_13, B => - flag_1_sqmuxa_i_o3_14, C => \state[0]_net_1\, Y => N_24); - - \cpt_next_commutation[10]\ : DFN1C0 - port map(D => I_55, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[10]_net_1\); - - \coarse_time[26]\ : DFN1C0 - port map(D => \s_coarse_time[26]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(26)); - - un4_s_coarse_time_I_136 : XOR2 - port map(A => N_66, B => \s_coarse_time[21]_net_1\, Y => - I_136_3); - - \secondary_cpt_RNO[3]\ : XOR2 - port map(A => secondary_cpt_c2, B => - \secondary_cpt[3]_net_1\, Y => secondary_cpt_n3); - - \cpt[12]\ : DFN1C1 - port map(D => I_73_4, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[12]\); - - un4_s_coarse_time_I_12 : AND3 - port map(A => \s_coarse_time[0]_net_1\, B => - \s_coarse_time[1]_net_1\, C => \s_coarse_time[2]_net_1\, - Y => N_154_0); - - un4_s_coarse_time_I_97 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E[10]\, - C => \s_coarse_time[15]_net_1\, Y => N_93); - - \latched_next_commutation_RNO[13]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(13), Y => N_159); - - un4_s_coarse_time_I_27 : AND2 - port map(A => \s_coarse_time[3]_net_1\, B => - \s_coarse_time[4]_net_1\, Y => \DWACT_FINC_E[1]\); - - p_clk_div_RNI8FA8 : NOR2A - port map(A => clk_div_0, B => \p_clk_div\, Y => - un1_p_clk_div); - - \latched_next_commutation_RNIF9S2[21]\ : XNOR2 - port map(A => \s_coarse_time[21]_net_1\, B => - \latched_next_commutation[21]_net_1\, Y => - s_coarse_time_1_21_i); - - \secondary_cpt_RNI4EG42[8]\ : OR3C - port map(A => s_coarse_time38lt16, B => - s_coarse_time38lto16_7, C => s_coarse_time38lto16_8, Y - => s_coarse_time38); - - \coarse_time[24]\ : DFN1C0 - port map(D => \s_coarse_time[24]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(24)); - - un9_cpt_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\, - C => \DWACT_FINC_E_0[3]\, Y => N_42); - - \s_coarse_time_RNO[2]\ : AO1C - port map(A => \s_coarse_time_4[2]\, B => soft_tick_3, C => - rstn, Y => un1_resetn_30_i); - - flag_RNICND52 : MX2 - port map(A => I_52_4, B => coarse_time_load(9), S => \flag\, - Y => \s_coarse_time_4[9]\); - - \previous_coarse_time_load_RNIIU45[9]\ : XNOR2 - port map(A => coarse_time_load(9), B => - \previous_coarse_time_load[9]_net_1\, Y => - previous_coarse_time_load_1_9_i); - - \latched_next_commutation_RNO[28]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(28), - Y => N_174); - - \s_coarse_time_RNO_1[28]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[28]\, Y - => un1_soft_tick_15_i); - - \p_next_commutation_RNILHIA[13]\ : XNOR2 - port map(A => next_commutation(13), B => - \p_next_commutation[13]_net_1\, Y => N_123_i_i_0); - - \cpt[2]\ : DFN1C1 - port map(D => I_9_9, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[2]\); - - \p_next_commutation_RNIT1JA[17]\ : XNOR2 - port map(A => next_commutation(17), B => - \p_next_commutation[17]_net_1\, Y => N_127_i_i_0); - - \latched_next_commutation[3]\ : DFN1E0P0 - port map(D => N_149_0, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[3]_net_1\); - - \p_next_commutation_RNIPPIA[15]\ : XNOR2 - port map(A => next_commutation(15), B => - \p_next_commutation[15]_net_1\, Y => N_125_i_i_0); - - \latched_next_commutation_RNIFIKA[5]\ : XNOR2 - port map(A => \s_coarse_time[5]_net_1\, B => - \latched_next_commutation[5]_net_1\, Y => - s_coarse_time_1_5_i); - - \previous_coarse_time_load[27]\ : DFN1E0C0 - port map(D => coarse_time_load(27), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[27]_net_1\); - - \s_coarse_time_RNII9T9[0]\ : MX2B - port map(A => \s_coarse_time[0]_net_1\, B => - coarse_time_load(0), S => \flag\, Y => - \s_coarse_time_4[0]\); - - \p_next_commutation_RNIJSC5[1]\ : XNOR2 - port map(A => next_commutation(1), B => - \p_next_commutation[1]_net_1\, Y => N_111_i_i_0); - - \previous_coarse_time_load[20]\ : DFN1E0C0 - port map(D => coarse_time_load(20), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[20]_net_1\); - - un9_cpt_I_87 : AND3 - port map(A => \fine_time[12]\, B => \fine_time[13]\, C => - \fine_time[14]\, Y => \DWACT_FINC_E_0[9]\); - - \s_coarse_time_RNO_0[18]\ : MX2 - port map(A => \s_coarse_time_4[18]\, B => - \s_coarse_time[18]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[18]\); - - \s_coarse_time[20]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[20]\, CLK => clk_div_3, PRE - => un1_soft_tick_23_i, CLR => un1_resetn_23_i, Q => - \s_coarse_time[20]_net_1\); - - \latched_next_commutation_RNO[25]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(25), - Y => N_171); - - flag_0_RNI83FJ2 : MX2 - port map(A => I_105_3, B => coarse_time_load(17), S => - \flag_0\, Y => \s_coarse_time_4[17]\); - - \cpt_next_commutation_RNITPT9[1]\ : NOR3 - port map(A => \cpt_next_commutation[2]_net_1\, B => - \cpt_next_commutation[1]_net_1\, C => - \cpt_next_commutation[3]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_2); - - \latched_next_commutation[14]\ : DFN1E0P0 - port map(D => N_160, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[14]_net_1\); - - \s_coarse_time_RNO[8]\ : AO1C - port map(A => \s_coarse_time_4[8]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_21_i); - - \p_next_commutation_RNIGRLL[4]\ : NOR3C - port map(A => N_115_i_i_0, B => N_114_i_i_0, C => - un1_commutation_timer_3_0_a2_3, Y => - un1_commutation_timer_3_0_a2_17); - - \previous_coarse_time_load[1]\ : DFN1E0C0 - port map(D => coarse_time_load(1), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[1]_net_1\); - - un4_s_coarse_time_I_224 : XOR2 - port map(A => N_4, B => \s_coarse_time[31]_net_1\, Y => - I_224_1); - - \cpt_RNO[0]\ : OA1C - port map(A => \fine_time[0]\, B => N_24, C => N_25, Y => - N_7); - - un4_s_coarse_time_I_186 : XOR2 - port map(A => N_31, B => \s_coarse_time[26]_net_1\, Y => - I_186_3); - - \secondary_cpt_RNO[12]\ : AX1C - port map(A => \secondary_cpt[11]_net_1\, B => - secondary_cpt_c10, C => \secondary_cpt[12]_net_1\, Y => - secondary_cpt_n12); - - un9_cpt_I_16 : AND3 - port map(A => \fine_time[0]\, B => \fine_time[1]\, C => - \fine_time[2]\, Y => \DWACT_FINC_E[0]\); - - \coarse_time[22]\ : DFN1C0 - port map(D => \s_coarse_time[22]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(22)); - - p_clk_div : DFN1E1 - port map(D => clk_div_0, CLK => lclk_c, E => rstn, Q => - \p_clk_div\); - - un4_s_coarse_time_I_220 : AND2 - port map(A => \DWACT_FINC_E[26]\, B => - \s_coarse_time[30]_net_1\, Y => \DWACT_FINC_E[27]\); - - flag_0_RNIU9B43 : MX2 - port map(A => I_217_1, B => coarse_time_load(30), S => - \flag_0\, Y => \s_coarse_time_4[30]\); - - \secondary_cpt_RNIDOOG[16]\ : NOR3 - port map(A => \secondary_cpt[12]_net_1\, B => - \secondary_cpt[16]_net_1\, C => \secondary_cpt[11]_net_1\, - Y => s_coarse_time38lto16_5); - - un4_s_coarse_time_I_111 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\); - - \latched_next_commutation_RNI47P5[14]\ : XA1A - port map(A => \latched_next_commutation[14]_net_1\, B => - \s_coarse_time[14]_net_1\, C => s_coarse_time_1_15_i, Y - => s_coarse_time_1_NE_7); - - \s_coarse_time_RNO_1[27]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[27]\, Y - => un1_soft_tick_21_i); - - un4_s_coarse_time_I_166 : XOR2 - port map(A => N_45, B => \s_coarse_time[24]_net_1\, Y => - I_166_3); - - un1_cpt_next_commutation_I_98 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_2_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_3[0]\); - - un1_cpt_next_commutation_I_96 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_2[0]\); - - \cpt_next_commutation[6]\ : DFN1C0 - port map(D => I_62, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[6]_net_1\); - - \previous_coarse_time_load_RNI6U45[3]\ : XNOR2 - port map(A => coarse_time_load(3), B => - \previous_coarse_time_load[3]_net_1\, Y => - previous_coarse_time_load_1_3_i); - - \latched_next_commutation[18]\ : DFN1E0P0 - port map(D => N_164, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[18]_net_1\); - - \secondary_cpt_RNO[0]\ : XNOR2 - port map(A => \un1_cpt_0[0]\, B => \secondary_cpt[0]_net_1\, - Y => \secondary_cpt_RNO[0]_net_1\); - - un9_cpt_I_80 : AND2 - port map(A => \fine_time[12]\, B => \fine_time[13]\, Y => - \DWACT_FINC_E_0[8]\); - - \latched_next_commutation[19]\ : DFN1E0P0 - port map(D => N_165, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[19]_net_1\); - - \latched_next_commutation[8]\ : DFN1E0P0 - port map(D => N_154, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[8]_net_1\); - - un4_s_coarse_time_I_73 : XOR2 - port map(A => N_111, B => \s_coarse_time[12]_net_1\, Y => - I_73_3); - - \latched_next_commutation_RNO[12]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(12), Y => N_158); - - \cpt_next_commutation[9]\ : DFN1C0 - port map(D => I_69, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[9]_net_1\); - - \s_coarse_time_RNO_0[17]\ : MX2 - port map(A => \s_coarse_time_4[17]\, B => - \s_coarse_time[17]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[17]\); - - \secondary_cpt_RNIS6VJ[10]\ : NOR3C - port map(A => \secondary_cpt[10]_net_1\, B => - \secondary_cpt[9]_net_1\, C => - secondary_cpt_c12_m6_0_a2_3, Y => - secondary_cpt_c12_m6_0_a2_5); - - \s_coarse_time_RNO_1[1]\ : NOR2B - port map(A => soft_tick_3, B => \s_coarse_time_4[1]\, Y => - un1_soft_tick_19_i); - - \p_next_commutation[18]\ : DFN1E1 - port map(D => next_commutation(18), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[18]_net_1\); - - \latched_next_commutation_RNO[19]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(19), - Y => N_165); - - \cpt_next_commutation[0]\ : DFN1C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[0]_net_1\); - - \p_next_commutation_RNI3TD5[9]\ : XNOR2 - port map(A => next_commutation(9), B => - \p_next_commutation[9]_net_1\, Y => N_119_i_i_0); - - \cpt[7]\ : DFN1C1 - port map(D => I_38_6, CLK => clk_div_0, CLR => reset_i_0, Q - => \fine_time[7]\); - - \cpt[0]\ : DFN1C1 - port map(D => N_7, CLK => clk_div_0, CLR => reset_i_0_1, Q - => \fine_time[0]\); - - \latched_next_commutation[10]\ : DFN1E0P0 - port map(D => N_156, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[10]_net_1\); - - \latched_next_commutation[0]\ : DFN1E0P0 - port map(D => N_146, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[0]_net_1\); - - \previous_coarse_time_load_RNICOJK[0]\ : NOR3C - port map(A => previous_coarse_time_load_1_1_i, B => - previous_coarse_time_load_1_0_i, C => - previous_coarse_time_load_1_NE_1, Y => - previous_coarse_time_load_1_NE_16); - - \previous_coarse_time_load_RNI0U45[0]\ : XNOR2 - port map(A => coarse_time_load(0), B => - \previous_coarse_time_load[0]_net_1\, Y => - previous_coarse_time_load_1_0_i); - - \latched_next_commutation_RNO[23]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(23), - Y => N_169); - - sirq2_RNO : OR2B - port map(A => \commutation_timer[0]_net_1\, B => N_243, Y - => N_6); - - un4_s_coarse_time_I_128 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[14]\, Y => N_71); - - un9_cpt_I_84 : XOR2 - port map(A => N_14_0, B => \fine_time[14]\, Y => I_84_4); - - \latched_next_commutation_RNI5UJA[0]\ : XNOR2 - port map(A => \s_coarse_time[0]_net_1\, B => - \latched_next_commutation[0]_net_1\, Y => - s_coarse_time_1_0_i); - - un4_s_coarse_time_I_55 : AND3 - port map(A => \DWACT_FINC_E_0[4]\, B => - \s_coarse_time[8]_net_1\, C => \s_coarse_time[9]_net_1\, - Y => N_123); - - un4_s_coarse_time_I_45 : XOR2 - port map(A => N_131, B => \s_coarse_time[8]_net_1\, Y => - I_45_4); - - \latched_next_commutation_RNO[0]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(0), Y => N_146); - - \s_coarse_time_RNO[9]\ : AO1C - port map(A => \s_coarse_time_4[9]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_22_i); - - \s_coarse_time_RNO_0[20]\ : MX2 - port map(A => \s_coarse_time_4[20]\, B => - \s_coarse_time[20]_net_1\, S => \un1_cpt[0]\, Y => - \s_coarse_time_7[20]\); - - flag_0_RNI5H3M2 : MX2 - port map(A => I_122_3, B => coarse_time_load(19), S => - \flag_0\, Y => \s_coarse_time_4[19]\); - - un9_cpt_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \fine_time[8]\, C => - \fine_time[9]\, Y => N_34); - - \previous_coarse_time_load_RNIMQJC[14]\ : XA1A - port map(A => \previous_coarse_time_load[14]_net_1\, B => - coarse_time_load(14), C => - previous_coarse_time_load_1_15_i, Y => - previous_coarse_time_load_1_NE_7); - - \previous_coarse_time_load_RNI4MAP[16]\ : NOR3C - port map(A => previous_coarse_time_load_1_17_i, B => - previous_coarse_time_load_1_16_i, C => - previous_coarse_time_load_1_NE_9, Y => - previous_coarse_time_load_1_NE_20); - - un9_cpt_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \fine_time[9]\, C => - \fine_time[10]\, Y => N_27); - - \previous_coarse_time_load_RNISL8P[24]\ : NOR3C - port map(A => previous_coarse_time_load_1_25_i, B => - previous_coarse_time_load_1_24_i, C => - previous_coarse_time_load_1_NE_13, Y => - previous_coarse_time_load_1_NE_22); - - \coarse_time[11]\ : DFN1C0 - port map(D => \s_coarse_time[11]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(11)); - - un9_cpt_I_19 : NOR2B - port map(A => \fine_time[3]\, B => \DWACT_FINC_E[0]\, Y => - N_60); - - \s_coarse_time_RNO[7]\ : AO1C - port map(A => \s_coarse_time_4[7]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_32_i); - - un1_cpt_next_commutation_I_78 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \cpt_next_commutation[2]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12[0]\); - - \p_next_commutation_RNI0G6L[18]\ : XA1A - port map(A => \p_next_commutation[18]_net_1\, B => - next_commutation(18), C => N_129_i_i_0, Y => - un1_commutation_timer_3_0_a2_9); - - \cpt_RNI56G2[1]\ : NOR2B - port map(A => \fine_time[1]\, B => \fine_time[4]\, Y => - \un1_cpt_0_a3_5[0]\); - - \latched_next_commutation[15]\ : DFN1E0P0 - port map(D => N_161, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[15]_net_1\); - - \latched_next_commutation_RNI0EHB[20]\ : NOR3C - port map(A => s_coarse_time_1_21_i, B => - s_coarse_time_1_20_i, C => s_coarse_time_1_NE_11, Y => - s_coarse_time_1_NE_21); - - \s_coarse_time[25]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[25]\, CLK => clk_div_3, PRE - => un1_soft_tick_31_i, CLR => un1_resetn_6_i, Q => - \s_coarse_time[25]_net_1\); - - un1_cpt_next_commutation_I_69 : XOR2 - port map(A => \cpt_next_commutation[9]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_3[0]\, Y => I_69); - - \cpt_next_commutation_RNIL94R1[13]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_11, B => - \cpt_next_commutation[12]_net_1\, C => - \cpt_next_commutation[13]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_13); - - \s_coarse_time_RNO_0[2]\ : MX2 - port map(A => \s_coarse_time_4[2]\, B => - \s_coarse_time[2]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[2]\); - - \state[0]\ : DFN1P1C1 - port map(D => N_5, CLK => clk_int, PRE => soft_tick, CLR - => rstn_i, Q => \state[0]_net_1\); - - \s_coarse_time_RNO_1[0]\ : NOR2A - port map(A => soft_tick_3, B => \s_coarse_time_4[0]\, Y => - un1_soft_tick_25_i); - - un4_s_coarse_time_I_223 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[27]\, Y => N_4); - - \state_RNO[0]\ : AOI1B - port map(A => flag_1_sqmuxa_i_o3_14, B => - flag_1_sqmuxa_i_o3_13, C => \state[0]_net_1\, Y => N_5); - - \s_coarse_time[1]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[1]\, CLK => clk_div_3, PRE - => un1_soft_tick_19_i, CLR => un1_resetn_33_i, Q => - \s_coarse_time[1]_net_1\); - - \secondary_cpt[1]\ : DFN1E0C1 - port map(D => secondary_cpt_n1, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[1]_net_1\); - - \cpt_next_commutation[4]\ : DFN1C0 - port map(D => I_58, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[4]_net_1\); - - \commutation_timer_RNINQD9E[0]\ : AO1 - port map(A => un1_commutation_timer_3_0_a2_30, B => - s_coarse_time_1_NE, C => \commutation_timer[0]_net_1\, Y - => un1_commutation_timer_3_0); - - \previous_coarse_time_load[8]\ : DFN1E0C0 - port map(D => coarse_time_load(8), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[8]_net_1\); - - un3_grspw_tick_1 : OR2A - port map(A => rstn, B => soft_tick_0, Y => reset_i_0_1); - - \s_coarse_time_RNO_3[31]\ : NOR3A - port map(A => \un1_cpt_0[0]\, B => s_coarse_time38, C => - \s_coarse_time[31]_net_1\, Y => \s_coarse_time_i_m[31]\); - - \s_coarse_time_RNO_1[10]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[10]\, Y - => un1_soft_tick_22_i); - - \s_coarse_time_RNO_1[26]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[26]\, Y - => un1_soft_tick_20_i); - - \s_coarse_time_RNO_0[9]\ : MX2 - port map(A => \s_coarse_time_4[9]\, B => - \s_coarse_time[9]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[9]\); - - \latched_next_commutation_RNIR1T2[27]\ : XNOR2 - port map(A => \s_coarse_time[27]_net_1\, B => - \latched_next_commutation[27]_net_1\, Y => - s_coarse_time_1_27_i); - - un1_cpt_next_commutation_I_103 : AND2 - port map(A => \cpt_next_commutation[8]_net_1\, B => - \cpt_next_commutation[9]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_3[0]\); - - \latched_next_commutation_RNI72KA[1]\ : XNOR2 - port map(A => \s_coarse_time[1]_net_1\, B => - \latched_next_commutation[1]_net_1\, Y => - s_coarse_time_1_1_i); - - \commutation_timer_RNI3EI8[0]\ : NOR2B - port map(A => un1_p_clk_div, B => - \commutation_timer[0]_net_1\, Y => - \commutation_timer_RNI3EI8[0]_net_1\); - - \s_coarse_time_RNO_1[29]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[29]\, Y - => un1_soft_tick_29_i); - - \secondary_cpt_RNO[4]\ : XOR2 - port map(A => secondary_cpt_c3, B => - \secondary_cpt[4]_net_1\, Y => secondary_cpt_n4); - - \previous_coarse_time_load[0]\ : DFN1E0C0 - port map(D => coarse_time_load(0), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[0]_net_1\); - - un4_s_coarse_time_I_76 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E_0[7]\, - C => \s_coarse_time[12]_net_1\, Y => N_108); - - un4_s_coarse_time_I_196 : XOR2 - port map(A => N_24_0, B => \s_coarse_time[27]_net_1\, Y => - I_196_3); - - \s_coarse_time[8]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[8]\, CLK => clk_div_3, PRE - => un1_soft_tick_i, CLR => un1_resetn_21_i, Q => - \s_coarse_time[8]_net_1\); - - \p_next_commutation[21]\ : DFN1E1 - port map(D => next_commutation(21), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[21]_net_1\); - - \cpt_next_commutation[12]\ : DFN1C0 - port map(D => I_57, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[12]_net_1\); - - \coarse_time[29]\ : DFN1C0 - port map(D => \s_coarse_time[29]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(29)); - - \coarse_time[17]\ : DFN1C0 - port map(D => \s_coarse_time[17]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(17)); - - \s_coarse_time_RNO_0[16]\ : MX2 - port map(A => \s_coarse_time_4[16]\, B => - \s_coarse_time[16]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[16]\); - - un1_cpt_next_commutation_I_102 : AND2 - port map(A => \cpt_next_commutation[2]_net_1\, B => - \cpt_next_commutation[3]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1[0]\); - - \previous_coarse_time_load[13]\ : DFN1E0C0 - port map(D => coarse_time_load(13), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[13]_net_1\); - - \s_coarse_time_RNO[28]\ : AO1C - port map(A => \s_coarse_time_4[28]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_15_i); - - \secondary_cpt_RNO[11]\ : XOR2 - port map(A => secondary_cpt_c10, B => - \secondary_cpt[11]_net_1\, Y => secondary_cpt_n11); - - \p_next_commutation_RNI0F4L[10]\ : XA1A - port map(A => \p_next_commutation[10]_net_1\, B => - next_commutation(10), C => N_121_i_i_0, Y => - un1_commutation_timer_3_0_a2_5); - - \secondary_cpt_RNIKVP8[2]\ : NOR3C - port map(A => \secondary_cpt[0]_net_1\, B => - \secondary_cpt[1]_net_1\, C => \secondary_cpt[2]_net_1\, - Y => secondary_cpt_c2); - - \secondary_cpt[10]\ : DFN1E0C1 - port map(D => secondary_cpt_n10, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[10]_net_1\); - - \s_coarse_time_RNO_0[19]\ : MX2 - port map(A => \s_coarse_time_4[19]\, B => - \s_coarse_time[19]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[19]\); - - \cpt_next_commutation[7]\ : DFN1C0 - port map(D => I_64, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[7]_net_1\); - - \s_coarse_time[11]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[11]\, CLK => clk_div_2, PRE - => un1_soft_tick_7_i, CLR => un1_resetn_28_i, Q => - \s_coarse_time[11]_net_1\); - - \p_next_commutation_RNISF2V8[0]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_25, B => - un1_commutation_timer_3_0_a2_24, C => - un1_commutation_timer_3_0_a2_29, Y => - un1_commutation_timer_3_0_a2_30); - - \s_coarse_time[17]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[17]\, CLK => clk_div_2, PRE - => un1_soft_tick_26_i, CLR => un1_resetn_14_i, Q => - \s_coarse_time[17]_net_1\); - - \secondary_cpt[5]\ : DFN1E0C1 - port map(D => secondary_cpt_n5, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[5]_net_1\); - - \previous_coarse_time_load[7]\ : DFN1E0C0 - port map(D => coarse_time_load(7), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[7]_net_1\); - - \s_coarse_time_RNO_0[28]\ : MX2 - port map(A => \s_coarse_time_4[28]\, B => - \s_coarse_time[28]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[28]\); - - Clk_divider0 : Clk_divider - port map(reset_i_0_1 => reset_i_0_1, clk49_152MHz_c => - clk49_152MHz_c, reset_i_0_0 => reset_i_0_0, - clk49_152MHz_c_0 => clk49_152MHz_c_0, clk_div_0 => - clk_div_0, clk_div_1 => clk_div_1, clk_div_2 => clk_div_2, - clk_int => clk_int, clk_div_3 => clk_div_3); - - \coarse_time[0]\ : DFN1C0 - port map(D => \s_coarse_time[0]_net_1\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time[0]_net_1\); - - un1_cpt_next_commutation_I_89 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10[0]\, B => - \cpt_next_commutation[12]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_5[0]\); - - \latched_next_commutation_RNO[22]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(22), - Y => N_168); - - \coarse_time[16]\ : DFN1C0 - port map(D => \s_coarse_time[16]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(16)); - - \cpt_next_commutation[15]\ : DFN1C0 - port map(D => I_67, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[15]_net_1\); - - \coarse_time[6]\ : DFN1C0 - port map(D => \s_coarse_time[6]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(6)); - - \secondary_cpt[6]\ : DFN1E0C1 - port map(D => secondary_cpt_n6, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[6]_net_1\); - - \latched_next_commutation_RNO[29]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(29), - Y => N_175); - - \latched_next_commutation_RNI0C3A5[10]\ : OR2B - port map(A => s_coarse_time_1_NE_29, B => - s_coarse_time_1_NE_28, Y => s_coarse_time_1_NE_0); - - \cpt_next_commutation_RNI7FC61[9]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_7, B => - \cpt_next_commutation[8]_net_1\, C => - \cpt_next_commutation[9]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_9); - - \cpt_RNI7LQ6[11]\ : NOR2B - port map(A => \fine_time[11]\, B => \fine_time[14]\, Y => - \un1_cpt_0_a3_1[0]\); - - \p_next_commutation_RNIPHIA[31]\ : XNOR2 - port map(A => next_commutation(31), B => - \p_next_commutation[31]_net_1\, Y => N_141_i_i_0); - - un9_cpt_I_5 : XOR2 - port map(A => \fine_time[0]\, B => \fine_time[1]\, Y => - I_5_9); - - \coarse_time[14]\ : DFN1C0 - port map(D => \s_coarse_time[14]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(14)); - - \latched_next_commutation_RNIDEKA[4]\ : XNOR2 - port map(A => \s_coarse_time[4]_net_1\, B => - \latched_next_commutation[4]_net_1\, Y => - s_coarse_time_1_4_i); - - \coarse_time[2]\ : DFN1C0 - port map(D => \s_coarse_time[2]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(2)); - - \secondary_cpt_RNIRVR5[2]\ : NOR2B - port map(A => \secondary_cpt[2]_net_1\, B => - \secondary_cpt[3]_net_1\, Y => s_coarse_time38lto5_0); - - \coarse_time[8]\ : DFN1C0 - port map(D => \s_coarse_time[8]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(8)); - - un1_cpt_next_commutation_I_67 : XOR2 - port map(A => \cpt_next_commutation[15]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_6[0]\, Y => I_67); - - \s_coarse_time_RNO_2[31]\ : OR2 - port map(A => s_coarse_time38, B => \un1_cpt_0[0]\, Y => - un1_s_coarse_time_3_m_0); - - un4_s_coarse_time_I_48 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E_0[4]\); - - flag_RNIHV8D2 : MX2 - port map(A => I_77_3, B => coarse_time_load(13), S => - \flag\, Y => \s_coarse_time_4[13]\); - - \secondary_cpt_RNIHVLE[4]\ : NOR2B - port map(A => secondary_cpt_c3, B => - \secondary_cpt[4]_net_1\, Y => secondary_cpt_c4); - - \cpt_next_commutation_RNISUMV[7]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_5, B => - \cpt_next_commutation[6]_net_1\, C => - \cpt_next_commutation[7]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_7); - - \p_next_commutation_RNI4MRA[8]\ : XA1A - port map(A => \p_next_commutation[8]_net_1\, B => - next_commutation(8), C => N_119_i_i_0, Y => - un1_commutation_timer_3_0_a2_4); - - \latched_next_commutation_RNIC1AL[8]\ : XA1A - port map(A => \latched_next_commutation[8]_net_1\, B => - \s_coarse_time[8]_net_1\, C => s_coarse_time_1_9_i, Y => - s_coarse_time_1_NE_4); - - \secondary_cpt[16]\ : DFN1E0C1 - port map(D => secondary_cpt_n16, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[16]_net_1\); - - \s_coarse_time_RNO_1[18]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[18]\, Y - => un1_soft_tick_27_i); - - \p_next_commutation_RNIJ9IA[20]\ : XNOR2 - port map(A => next_commutation(20), B => - \p_next_commutation[20]_net_1\, Y => N_130_i_i_0); - - un4_s_coarse_time_I_56 : XOR2 - port map(A => N_123, B => \s_coarse_time[10]_net_1\, Y => - I_56_5); - - \s_coarse_time[6]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[6]\, CLK => clk_div_3, PRE - => un1_soft_tick_10_i, CLR => un1_resetn_13_i, Q => - \s_coarse_time[6]_net_1\); - - \s_coarse_time_RNO[18]\ : AO1C - port map(A => \s_coarse_time_4[18]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_4_i); - - \cpt[3]\ : DFN1C1 - port map(D => I_13_13, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[3]\); - - \cpt_RNIQOOH[4]\ : NOR3C - port map(A => flag_1_sqmuxa_i_o3_6, B => - flag_1_sqmuxa_i_o3_5, C => flag_1_sqmuxa_i_o3_12, Y => - flag_1_sqmuxa_i_o3_14); - - un4_s_coarse_time_I_149 : AND3 - port map(A => \s_coarse_time[0]_net_1\, B => - \s_coarse_time[1]_net_1\, C => \s_coarse_time[2]_net_1\, - Y => \DWACT_FINC_E[34]\); - - \cpt_next_commutation[14]\ : DFN1C0 - port map(D => I_65, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[14]_net_1\); - - un1_cpt_next_commutation_I_64 : XOR2 - port map(A => \cpt_next_commutation[7]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => I_64); - - \s_coarse_time_RNO_0[27]\ : MX2 - port map(A => \s_coarse_time_4[27]\, B => - \s_coarse_time[27]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[27]\); - - \secondary_cpt[3]\ : DFN1E0C1 - port map(D => secondary_cpt_n3, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[3]_net_1\); - - un9_cpt_I_12 : AND3 - port map(A => \fine_time[0]\, B => \fine_time[1]\, C => - \fine_time[2]\, Y => N_65); - - \s_coarse_time[29]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[29]\, CLK => clk_div_3, PRE - => un1_soft_tick_29_i, CLR => un1_resetn_11_i, Q => - \s_coarse_time[29]_net_1\); - - flag_0_RNIFD333 : MX2 - port map(A => I_210_3, B => coarse_time_load(29), S => - \flag_0\, Y => \s_coarse_time_4[29]\); - - \cpt_RNILFL4[13]\ : NOR2 - port map(A => \fine_time[13]\, B => \fine_time[1]\, Y => - flag_1_sqmuxa_i_o3_4); - - \secondary_cpt_RNO[2]\ : AX1C - port map(A => \secondary_cpt[0]_net_1\, B => - \secondary_cpt[1]_net_1\, C => \secondary_cpt[2]_net_1\, - Y => secondary_cpt_n2); - - \latched_next_commutation_RNID9S2[12]\ : XNOR2 - port map(A => \s_coarse_time[12]_net_1\, B => - \latched_next_commutation[12]_net_1\, Y => - s_coarse_time_1_12_i); - - \p_next_commutation_RNIH9IA[11]\ : XNOR2 - port map(A => next_commutation(11), B => - \p_next_commutation[11]_net_1\, Y => N_121_i_i_0); - - un4_s_coarse_time_I_142 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[16]\, Y => N_61); - - \secondary_cpt_RNO[15]\ : XOR2 - port map(A => secondary_cpt_c14, B => - \secondary_cpt[15]_net_1\, Y => secondary_cpt_n15); - - un9_cpt_I_13 : XOR2 - port map(A => N_65, B => \fine_time[3]\, Y => I_13_13); - - \p_next_commutation_RNIRCD5[5]\ : XNOR2 - port map(A => next_commutation(5), B => - \p_next_commutation[5]_net_1\, Y => N_115_i_i_0); - - \cpt_next_commutation_RNICCOG1[11]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_9, B => - \cpt_next_commutation[10]_net_1\, C => - \cpt_next_commutation[11]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_11); - - \coarse_time[12]\ : DFN1C0 - port map(D => \s_coarse_time[12]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(12)); - - \cpt_next_commutation_RNIAMQD2[15]\ : OR2B - port map(A => sirq2_1_sqmuxa_i_a2_15, B => un1_p_clk_div, Y - => N_243); - - \latched_next_commutation_RNICFP5[24]\ : XA1A - port map(A => \latched_next_commutation[24]_net_1\, B => - \s_coarse_time[24]_net_1\, C => s_coarse_time_1_25_i, Y - => s_coarse_time_1_NE_12); - - \p_next_commutation[25]\ : DFN1E1 - port map(D => next_commutation(25), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[25]_net_1\); - - \cpt_next_commutation[3]\ : DFN1C0 - port map(D => I_54, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[3]_net_1\); - - \p_next_commutation_RNIJDIA[12]\ : XNOR2 - port map(A => next_commutation(12), B => - \p_next_commutation[12]_net_1\, Y => N_122_i_i_0); - - \s_coarse_time_RNO_0[4]\ : MX2 - port map(A => \s_coarse_time_4[4]\, B => - \s_coarse_time[4]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[4]\); - - \previous_coarse_time_load_RNIGHA6[17]\ : XNOR2 - port map(A => coarse_time_load(17), B => - \previous_coarse_time_load[17]_net_1\, Y => - previous_coarse_time_load_1_17_i); - - \latched_next_commutation_RNI4H9L[6]\ : XA1A - port map(A => \latched_next_commutation[6]_net_1\, B => - \s_coarse_time[6]_net_1\, C => s_coarse_time_1_7_i, Y => - s_coarse_time_1_NE_3); - - \p_next_commutation[16]\ : DFN1E1 - port map(D => next_commutation(16), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[16]_net_1\); - - \previous_coarse_time_load[23]\ : DFN1E0C0 - port map(D => coarse_time_load(23), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[23]_net_1\); - - flag_RNIALCM2 : MX2 - port map(A => I_129_3, B => coarse_time_load(20), S => - \flag\, Y => \s_coarse_time_4[20]\); - - \s_coarse_time_RNO_0[6]\ : MX2 - port map(A => \s_coarse_time_4[6]\, B => - \s_coarse_time[6]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[6]\); - - \latched_next_commutation_RNIT5T2[28]\ : XNOR2 - port map(A => \s_coarse_time[28]_net_1\, B => - \latched_next_commutation[28]_net_1\, Y => - s_coarse_time_1_28_i); - - un1_cpt_next_commutation_I_87 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_1[0]\); - - un4_s_coarse_time_I_115 : XOR2 - port map(A => N_81, B => \s_coarse_time[18]_net_1\, Y => - I_115_3); - - \s_coarse_time_RNO_1[17]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[17]\, Y - => un1_soft_tick_26_i); - - un4_s_coarse_time_I_87 : AND3 - port map(A => \s_coarse_time[12]_net_1\, B => - \s_coarse_time[13]_net_1\, C => \s_coarse_time[14]_net_1\, - Y => \DWACT_FINC_E[9]\); - - \previous_coarse_time_load_RNIEU45[7]\ : XNOR2 - port map(A => coarse_time_load(7), B => - \previous_coarse_time_load[7]_net_1\, Y => - previous_coarse_time_load_1_7_i); - - \cpt_RNI4U57[15]\ : NOR3C - port map(A => \fine_time[2]\, B => \fine_time[15]\, C => - \un1_cpt_0_a3_3[0]\, Y => \un1_cpt_0_a3_10[0]\); - - \previous_coarse_time_load[16]\ : DFN1E0C0 - port map(D => coarse_time_load(16), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[16]_net_1\); - - un1_cpt_next_commutation_I_99 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2[0]\); - - \s_coarse_time_RNO_1[9]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[9]\, Y => - un1_soft_tick_30_i); - - \s_coarse_time_RNO[5]\ : AO1C - port map(A => \s_coarse_time_4[5]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_26_i); - - \s_coarse_time[31]\ : DFN1P1C1 - port map(D => \s_coarse_time_10_iv[31]\, CLK => clk_div_3, - PRE => un1_resetn_2_i, CLR => un1_soft_tick_44_i, Q => - \s_coarse_time[31]_net_1\); - - \coarse_time[5]\ : DFN1C0 - port map(D => \s_coarse_time[5]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(5)); - - \p_next_commutation[6]\ : DFN1E1 - port map(D => next_commutation(6), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[6]_net_1\); - - \s_coarse_time_RNO[6]\ : AO1C - port map(A => \s_coarse_time_4[6]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_13_i); - - \p_next_commutation[12]\ : DFN1E1 - port map(D => next_commutation(12), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[12]_net_1\); - - \latched_next_commutation[1]\ : DFN1E0P0 - port map(D => N_147, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[1]_net_1\); - - \latched_next_commutation_RNIKG8L[2]\ : XA1A - port map(A => \latched_next_commutation[2]_net_1\, B => - \s_coarse_time[2]_net_1\, C => s_coarse_time_1_3_i, Y => - s_coarse_time_1_NE_1); - - un4_s_coarse_time_I_143 : XOR2 - port map(A => N_61, B => \s_coarse_time[22]_net_1\, Y => - I_143_3); - - GND_i_0 : GND - port map(Y => GND_0); - - \previous_coarse_time_load_RNICC2G1[10]\ : NOR3C - port map(A => previous_coarse_time_load_1_NE_5, B => - previous_coarse_time_load_1_NE_4, C => - previous_coarse_time_load_1_NE_19, Y => - previous_coarse_time_load_1_NE_25); - - un1_cpt_next_commutation_I_84 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => - \cpt_next_commutation[1]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_1[0]\); - - \latched_next_commutation_RNO[7]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(7), Y => N_153); - - un4_s_coarse_time_I_91 : XOR2 - port map(A => N_98, B => \s_coarse_time[15]_net_1\, Y => - I_91_3); - - \latched_next_commutation[21]\ : DFN1E0P0 - port map(D => N_167, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[21]_net_1\); - - \cpt_next_commutation[1]\ : DFN1C0 - port map(D => I_63, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[1]_net_1\); - - un4_s_coarse_time_I_9 : XOR2 - port map(A => N_157, B => \s_coarse_time[2]_net_1\, Y => - I_9_8); - - flag_0 : DFN1E0C1 - port map(D => flag_1, CLK => clk_div_0, CLR => reset_i_0_0, - E => flag_1_sqmuxa_1, Q => \flag_0\); - - un4_s_coarse_time_I_101 : AND2 - port map(A => \s_coarse_time[15]_net_1\, B => - \s_coarse_time[16]_net_1\, Y => \DWACT_FINC_E[11]\); - - \latched_next_commutation_RNO[11]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(11), Y => N_157_0); - - \cpt_RNISBL4[9]\ : NOR2B - port map(A => \fine_time[9]\, B => \fine_time[12]\, Y => - \un1_cpt_0_a3_7[0]\); - - un4_s_coarse_time_I_59 : AND3 - port map(A => \s_coarse_time[6]_net_1\, B => - \s_coarse_time[7]_net_1\, C => \s_coarse_time[8]_net_1\, - Y => \DWACT_FINC_E[5]\); - - \s_coarse_time_RNO_0[26]\ : MX2 - port map(A => \s_coarse_time_4[26]\, B => - \s_coarse_time[26]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[26]\); - - \s_coarse_time_RNO[4]\ : AO1C - port map(A => \s_coarse_time_4[4]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_17_i); - - \coarse_time[3]\ : DFN1C0 - port map(D => \s_coarse_time[3]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(3)); - - un9_cpt_I_51 : NOR2B - port map(A => \fine_time[8]\, B => \DWACT_FINC_E[4]\, Y => - N_37); - - \cpt_RNIB5R6[14]\ : NOR2 - port map(A => \fine_time[14]\, B => \fine_time[15]\, Y => - flag_1_sqmuxa_i_o3_1); - - un4_s_coarse_time_I_217 : XOR2 - port map(A => N_9_0, B => \s_coarse_time[30]_net_1\, Y => - I_217_1); - - \latched_next_commutation_RNIKVP5[26]\ : XA1A - port map(A => \latched_next_commutation[26]_net_1\, B => - \s_coarse_time[26]_net_1\, C => s_coarse_time_1_27_i, Y - => s_coarse_time_1_NE_13); - - \secondary_cpt_RNO[16]\ : AX1C - port map(A => \secondary_cpt[15]_net_1\, B => - secondary_cpt_c14, C => \secondary_cpt[16]_net_1\, Y => - secondary_cpt_n16); - - \s_coarse_time_RNO_0[29]\ : MX2 - port map(A => \s_coarse_time_4[29]\, B => - \s_coarse_time[29]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[29]\); - - \s_coarse_time[10]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[10]\, CLK => clk_div_2, PRE - => un1_soft_tick_22_i, CLR => un1_resetn_9_i, Q => - \s_coarse_time[10]_net_1\); - - un4_s_coarse_time_I_94 : AND2 - port map(A => \DWACT_FINC_E_0[7]\, B => \DWACT_FINC_E[9]\, - Y => \DWACT_FINC_E[10]\); - - \latched_next_commutation_RNI07JB[28]\ : NOR3C - port map(A => s_coarse_time_1_29_i, B => - s_coarse_time_1_28_i, C => s_coarse_time_1_NE_15, Y => - s_coarse_time_1_NE_23); - - \cpt_next_commutation_RNI27G52[15]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_13, B => - \cpt_next_commutation[14]_net_1\, C => - \cpt_next_commutation[15]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_15); - - un4_s_coarse_time_I_24 : XOR2 - port map(A => N_146_0, B => \s_coarse_time[5]_net_1\, Y => - I_24_9); - - un3_grspw_tick : OR2A - port map(A => rstn, B => soft_tick_0, Y => reset_i_0); - - un1_cpt_next_commutation_I_65 : XOR2 - port map(A => \cpt_next_commutation[14]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_2[0]\, Y => I_65); - - flag_RNIQ9VA1 : MX2 - port map(A => I_24_9, B => coarse_time_load(5), S => \flag\, - Y => \s_coarse_time_4[5]\); - - \cpt[14]\ : DFN1C1 - port map(D => I_84_4, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[14]\); - - \p_next_commutation_RNI16JA[27]\ : XNOR2 - port map(A => next_commutation(27), B => - \p_next_commutation[27]_net_1\, Y => N_137_i_i_0); - - un4_s_coarse_time_I_37 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \s_coarse_time[6]_net_1\, Y => N_136); - - \s_coarse_time[23]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[23]\, CLK => clk_div_3, PRE - => un1_soft_tick_2_i, CLR => un1_resetn_16_i, Q => - \s_coarse_time[23]_net_1\); - - \s_coarse_time[28]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[28]\, CLK => clk_div_3, PRE - => un1_soft_tick_15_i, CLR => un1_resetn_15_i, Q => - \s_coarse_time[28]_net_1\); - - \s_coarse_time_RNO_1[16]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[16]\, Y - => un1_soft_tick_17_i); - - \cpt[16]\ : DFN1C1 - port map(D => \cpt_5[16]\, CLK => clk_div_0, CLR => - reset_i_0_1, Q => \fine_time[16]\); - - \secondary_cpt[4]\ : DFN1E0C1 - port map(D => secondary_cpt_n4, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[4]_net_1\); - - \latched_next_commutation[31]\ : DFN1E0P0 - port map(D => N_177, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[31]_net_1\); - - un1_cpt_next_commutation_I_97 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \cpt_next_commutation[4]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_1[0]\); - - flag_RNIGMB41 : MX2 - port map(A => I_20_8, B => coarse_time_load(4), S => \flag\, - Y => \s_coarse_time_4[4]\); - - flag_0_RNIIU4V2 : MX2 - port map(A => I_186_3, B => coarse_time_load(26), S => - \flag_0\, Y => \s_coarse_time_4[26]\); - - \s_coarse_time_RNO_1[19]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[19]\, Y - => un1_soft_tick_1_i); - - \coarse_time[19]\ : DFN1C0 - port map(D => \s_coarse_time[19]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(19)); - - \p_next_commutation_RNIRTIA[16]\ : XNOR2 - port map(A => next_commutation(16), B => - \p_next_commutation[16]_net_1\, Y => N_126_i_i_0); - - \previous_coarse_time_load[26]\ : DFN1E0C0 - port map(D => coarse_time_load(26), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[26]_net_1\); - - \previous_coarse_time_load_RNIC1A6[15]\ : XNOR2 - port map(A => coarse_time_load(15), B => - \previous_coarse_time_load[15]_net_1\, Y => - previous_coarse_time_load_1_15_i); - - \secondary_cpt_RNILHCE[8]\ : NOR3A - port map(A => s_coarse_time38lto16_4, B => - \secondary_cpt[8]_net_1\, C => \secondary_cpt[7]_net_1\, - Y => s_coarse_time38lto16_7); - - un4_s_coarse_time_I_159 : AND3 - port map(A => \s_coarse_time[21]_net_1\, B => - \s_coarse_time[22]_net_1\, C => \s_coarse_time[23]_net_1\, - Y => \DWACT_FINC_E[17]\); - - \previous_coarse_time_load_RNI2RKC[26]\ : XA1A - port map(A => \previous_coarse_time_load[26]_net_1\, B => - coarse_time_load(26), C => - previous_coarse_time_load_1_27_i, Y => - previous_coarse_time_load_1_NE_13); - - \latched_next_commutation_RNID5S2[20]\ : XNOR2 - port map(A => \s_coarse_time[20]_net_1\, B => - \latched_next_commutation[20]_net_1\, Y => - s_coarse_time_1_20_i); - - \p_next_commutation[29]\ : DFN1E1 - port map(D => next_commutation(29), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[29]_net_1\); - - un1_cpt_next_commutation_I_94 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - \coarse_time[9]\ : DFN1C0 - port map(D => \s_coarse_time[9]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(9)); - - \previous_coarse_time_load_RNI6RLC[18]\ : XA1A - port map(A => \previous_coarse_time_load[18]_net_1\, B => - coarse_time_load(18), C => - previous_coarse_time_load_1_19_i, Y => - previous_coarse_time_load_1_NE_9); - - \secondary_cpt[0]\ : DFN1C1 - port map(D => \secondary_cpt_RNO[0]_net_1\, CLK => clk_int, - CLR => reset_i_0, Q => \secondary_cpt[0]_net_1\); - - \coarse_time[20]\ : DFN1C0 - port map(D => \s_coarse_time[20]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(20)); - - un4_s_coarse_time_I_152 : AND3 - port map(A => \DWACT_FINC_E[34]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[29]\); - - un9_cpt_I_83 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E_0[8]\, Y => N_14_0); - - \previous_coarse_time_load[18]\ : DFN1E0C0 - port map(D => coarse_time_load(18), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[18]_net_1\); - - \latched_next_commutation_RNIFDS2[13]\ : XNOR2 - port map(A => \s_coarse_time[13]_net_1\, B => - \latched_next_commutation[13]_net_1\, Y => - s_coarse_time_1_13_i); - - \previous_coarse_time_load[15]\ : DFN1E0C0 - port map(D => coarse_time_load(15), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[15]_net_1\); - - \latched_next_commutation_RNI4NO5[30]\ : XA1A - port map(A => \latched_next_commutation[30]_net_1\, B => - \s_coarse_time[30]_net_1\, C => s_coarse_time_1_31_i, Y - => s_coarse_time_1_NE_15); - - \s_coarse_time_RNO[26]\ : AO1C - port map(A => \s_coarse_time_4[26]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_8_i); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \p_next_commutation_RNIVKD5[7]\ : XNOR2 - port map(A => next_commutation(7), B => - \p_next_commutation[7]_net_1\, Y => N_117_i_i_0); - - \s_coarse_time_RNO_1[8]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[8]\, Y => - un1_soft_tick_i); - - flag_0_RNINIK53 : MX2 - port map(A => I_224_1, B => coarse_time_load(31), S => - \flag_0\, Y => \s_coarse_time_4[31]\); - - \p_next_commutation_RNITTIA[25]\ : XNOR2 - port map(A => next_commutation(25), B => - \p_next_commutation[25]_net_1\, Y => N_135_i_i_0); - - \p_next_commutation_RNIGNNK2[24]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_13, B => - un1_commutation_timer_3_0_a2_12, C => - un1_commutation_timer_3_0_a2_23, Y => - un1_commutation_timer_3_0_a2_27); - - \latched_next_commutation_RNO[21]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(21), - Y => N_167); - - un4_s_coarse_time_I_139 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => - \s_coarse_time[21]_net_1\, Y => \DWACT_FINC_E[16]\); - - \s_coarse_time[15]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[15]\, CLK => clk_div_2, PRE - => un1_soft_tick_3_i, CLR => un1_resetn_24_i, Q => - \s_coarse_time[15]_net_1\); - - \latched_next_commutation[22]\ : DFN1E0P0 - port map(D => N_168, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[22]_net_1\); - - un1_cpt_next_commutation_I_63 : XOR2 - port map(A => \cpt_next_commutation[1]_net_1\, B => - \DWACT_ADD_CI_0_TMP[0]\, Y => I_63); - - \p_next_commutation[23]\ : DFN1E1 - port map(D => next_commutation(23), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[23]_net_1\); - - \coarse_time[28]\ : DFN1C0 - port map(D => \s_coarse_time[28]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(28)); - - \cpt_RNIAI57[6]\ : NOR3C - port map(A => \fine_time[8]\, B => \fine_time[6]\, C => - \un1_cpt_0_a3_7[0]\, Y => \un1_cpt_0_a3_12[0]\); - - \s_coarse_time[30]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[30]\, CLK => clk_div_3, PRE - => un1_soft_tick_16_i, CLR => un1_resetn_7_i, Q => - \s_coarse_time[30]_net_1\); - - un1_cpt_next_commutation_I_74 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_10[0]\); - - un4_s_coarse_time_I_132 : AND3 - port map(A => \s_coarse_time[18]_net_1\, B => - \s_coarse_time[19]_net_1\, C => \s_coarse_time[20]_net_1\, - Y => \DWACT_FINC_E[15]\); - - \previous_coarse_time_load_RNIAH96[23]\ : XNOR2 - port map(A => coarse_time_load(23), B => - \previous_coarse_time_load[23]_net_1\, Y => - previous_coarse_time_load_1_23_i); - - \s_coarse_time_RNO_0[7]\ : MX2 - port map(A => \s_coarse_time_4[7]\, B => - \s_coarse_time[7]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[7]\); - - un4_s_coarse_time_I_114 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[12]\, Y => N_81); - - \cpt_RNI36G2[0]\ : NOR2B - port map(A => \fine_time[0]\, B => \fine_time[3]\, Y => - \un1_cpt_0_a3_8[0]\); - - \s_coarse_time_RNO[24]\ : AO1C - port map(A => \s_coarse_time_4[24]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_19_i); - - un4_s_coarse_time_I_155 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[33]\, Y => N_52); - - \latched_next_commutation_RNIR5T2[19]\ : XNOR2 - port map(A => \s_coarse_time[19]_net_1\, B => - \latched_next_commutation[19]_net_1\, Y => - s_coarse_time_1_19_i); - - \secondary_cpt_RNINVDQ[8]\ : NOR3C - port map(A => \secondary_cpt[7]_net_1\, B => - secondary_cpt_c6, C => \secondary_cpt[8]_net_1\, Y => - secondary_cpt_c8); - - \p_next_commutation_RNILDIA[21]\ : XNOR2 - port map(A => next_commutation(21), B => - \p_next_commutation[21]_net_1\, Y => N_131_i_i_0); - - \secondary_cpt_RNO[10]\ : AX1C - port map(A => \secondary_cpt[9]_net_1\, B => - secondary_cpt_c8, C => \secondary_cpt[10]_net_1\, Y => - secondary_cpt_n10); - - \p_next_commutation_RNIN4D5[3]\ : XNOR2 - port map(A => next_commutation(3), B => - \p_next_commutation[3]_net_1\, Y => N_113_i_i_0); - - \s_coarse_time[26]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[26]\, CLK => clk_div_3, PRE - => un1_soft_tick_20_i, CLR => un1_resetn_8_i, Q => - \s_coarse_time[26]_net_1\); - - \cpt[11]\ : DFN1C1 - port map(D => I_66_6, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[11]\); - - \latched_next_commutation_RNI4VO5[22]\ : XA1A - port map(A => \latched_next_commutation[22]_net_1\, B => - \s_coarse_time[22]_net_1\, C => s_coarse_time_1_23_i, Y - => s_coarse_time_1_NE_11); - - VCC_i : VCC - port map(Y => \VCC\); - - \s_coarse_time_RNO[16]\ : AO1C - port map(A => \s_coarse_time_4[16]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_27_i); - - \s_coarse_time_RNO[31]\ : NOR2A - port map(A => soft_tick_0, B => \s_coarse_time_4[31]\, Y - => un1_soft_tick_44_i); - - un4_s_coarse_time_I_210 : XOR2 - port map(A => N_14, B => \s_coarse_time[29]_net_1\, Y => - I_210_3); - - \secondary_cpt_RNIGHG8[10]\ : NOR2 - port map(A => \secondary_cpt[9]_net_1\, B => - \secondary_cpt[10]_net_1\, Y => s_coarse_time38lto16_4); - - un9_cpt_I_77 : XOR2 - port map(A => N_19_0, B => \fine_time[13]\, Y => I_77_4); - - \latched_next_commutation_RNO[1]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(1), Y => N_147); - - \previous_coarse_time_load_RNIE1A6[25]\ : XNOR2 - port map(A => coarse_time_load(25), B => - \previous_coarse_time_load[25]_net_1\, Y => - previous_coarse_time_load_1_25_i); - - \state_RNIEG3J2_0[0]\ : NOR2 - port map(A => N_25, B => N_24, Y => \un1_cpt_1[0]\); - - \secondary_cpt[7]\ : DFN1E0C1 - port map(D => secondary_cpt_n7, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[7]_net_1\); - - \latched_next_commutation_RNO[10]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(10), Y => N_156); - - \s_coarse_time_RNO_1[6]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[6]\, Y => - un1_soft_tick_10_i); - - \latched_next_commutation_RNI0IIA1[4]\ : NOR3C - port map(A => s_coarse_time_1_5_i, B => s_coarse_time_1_4_i, - C => s_coarse_time_1_NE_3, Y => s_coarse_time_1_NE_17); - - \cpt[6]\ : DFN1C1 - port map(D => I_31_8, CLK => clk_div_0, CLR => reset_i_0, Q - => \fine_time[6]\); - - \previous_coarse_time_load_RNIIQIC[22]\ : XA1A - port map(A => \previous_coarse_time_load[22]_net_1\, B => - coarse_time_load(22), C => - previous_coarse_time_load_1_23_i, Y => - previous_coarse_time_load_1_NE_11); - - \previous_coarse_time_load_RNIOK9U5[10]\ : OR2B - port map(A => previous_coarse_time_load_1_NE_29, B => - previous_coarse_time_load_1_NE_28, Y => flag_1); - - \cpt_RNI7OH91[10]\ : NOR3C - port map(A => \un1_cpt_0_a3_11[0]\, B => - \un1_cpt_0_a3_10[0]\, C => \un1_cpt_0_a3_15[0]\, Y => - N_25); - - un4_s_coarse_time_I_189 : AND3 - port map(A => \s_coarse_time[24]_net_1\, B => - \s_coarse_time[25]_net_1\, C => \s_coarse_time[26]_net_1\, - Y => \DWACT_FINC_E[22]\); - - \p_next_commutation[11]\ : DFN1E1 - port map(D => next_commutation(11), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[11]_net_1\); - - \latched_next_commutation[7]\ : DFN1E0P0 - port map(D => N_153, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[7]_net_1\); - - un4_s_coarse_time_I_135 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[15]\, Y => N_66); - - \s_coarse_time_RNO_0[31]\ : OA1B - port map(A => \s_coarse_time_4[31]\, B => - un1_s_coarse_time_3_m_0, C => \s_coarse_time_i_m[31]\, Y - => \s_coarse_time_10_iv[31]\); - - \p_next_commutation[31]\ : DFN1E1 - port map(D => next_commutation(31), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[31]_net_1\); - - \latched_next_commutation[4]\ : DFN1E0P0 - port map(D => N_150, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[4]_net_1\); - - \previous_coarse_time_load[28]\ : DFN1E0C0 - port map(D => coarse_time_load(28), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[28]_net_1\); - - \previous_coarse_time_load_RNI2T9A[8]\ : XA1A - port map(A => \previous_coarse_time_load[8]_net_1\, B => - coarse_time_load(8), C => previous_coarse_time_load_1_9_i, - Y => previous_coarse_time_load_1_NE_4); - - \latched_next_commutation_RNO[14]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(14), Y => N_160); - - \previous_coarse_time_load[12]\ : DFN1E0C0 - port map(D => coarse_time_load(12), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[12]_net_1\); - - \p_next_commutation_RNIONBA1[28]\ : NOR3C - port map(A => N_139_i_i_0, B => N_138_i_i_0, C => - un1_commutation_timer_3_0_a2_15, Y => - un1_commutation_timer_3_0_a2_23); - - \previous_coarse_time_load[25]\ : DFN1E0C0 - port map(D => coarse_time_load(25), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[25]_net_1\); - - un1_cpt_next_commutation_I_95 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \cpt_next_commutation[8]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_3[0]\); - - \previous_coarse_time_load_RNI8H96[13]\ : XNOR2 - port map(A => coarse_time_load(13), B => - \previous_coarse_time_load[13]_net_1\, Y => - previous_coarse_time_load_1_13_i); - - \s_coarse_time_RNO[14]\ : AO1C - port map(A => \s_coarse_time_4[14]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_3_i); - - \latched_next_commutation[6]\ : DFN1E0P0 - port map(D => N_152, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[6]_net_1\); - - un4_s_coarse_time_I_65 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => - \s_coarse_time[9]_net_1\, C => \s_coarse_time[10]_net_1\, - Y => N_116); - - un4_s_coarse_time_I_169 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \s_coarse_time[24]_net_1\, Y => \DWACT_FINC_E[19]\); - - \secondary_cpt_RNO[14]\ : AX1C - port map(A => \secondary_cpt[13]_net_1\, B => - secondary_cpt_c12, C => \secondary_cpt[14]_net_1\, Y => - secondary_cpt_n14); - - un4_s_coarse_time_I_182 : AND3 - port map(A => \DWACT_FINC_E_0[7]\, B => \DWACT_FINC_E[9]\, - C => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[30]\); - - un1_cpt_next_commutation_I_104 : AND2 - port map(A => \cpt_next_commutation[12]_net_1\, B => - \cpt_next_commutation[13]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_5[0]\); - - \p_next_commutation_RNIC5QA[2]\ : XA1A - port map(A => \p_next_commutation[2]_net_1\, B => - next_commutation(2), C => N_113_i_i_0, Y => - un1_commutation_timer_3_0_a2_1); - - \previous_coarse_time_load_RNI2U45[1]\ : XNOR2 - port map(A => coarse_time_load(1), B => - \previous_coarse_time_load[1]_net_1\, Y => - previous_coarse_time_load_1_1_i); - - un4_s_coarse_time_I_118 : AND3 - port map(A => \DWACT_FINC_E_0[7]\, B => \DWACT_FINC_E[9]\, - C => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[13]\); - - \cpt_RNIH6G2[8]\ : NOR2 - port map(A => \fine_time[8]\, B => \fine_time[9]\, Y => - flag_1_sqmuxa_i_o3_6); - - \p_next_commutation[9]\ : DFN1E1 - port map(D => next_commutation(9), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[9]_net_1\); - - \s_coarse_time_RNO[30]\ : AO1C - port map(A => \s_coarse_time_4[30]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_7_i); - - \cpt_next_commutation[2]\ : DFN1C0 - port map(D => I_68, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[2]_net_1\); - - \previous_coarse_time_load_RNIKBGI1[30]\ : NOR3C - port map(A => previous_coarse_time_load_1_NE_15, B => - previous_coarse_time_load_1_NE_14, C => - previous_coarse_time_load_1_NE_22, Y => - previous_coarse_time_load_1_NE_27); - - \previous_coarse_time_load[19]\ : DFN1E0C0 - port map(D => coarse_time_load(19), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[19]_net_1\); - - \s_coarse_time[22]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[22]\, CLK => clk_div_3, PRE - => un1_soft_tick_24_i, CLR => un1_resetn_5_i, Q => - \s_coarse_time[22]_net_1\); - - \cpt_RNO[16]\ : NOR2B - port map(A => I_98_4, B => \un1_cpt_0[0]\, Y => \cpt_5[16]\); - - \cpt_RNI76G2[2]\ : NOR2 - port map(A => \fine_time[2]\, B => \fine_time[5]\, Y => - flag_1_sqmuxa_i_o3_2); - - \latched_next_commutation_RNO[16]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(16), Y => N_162); - - \secondary_cpt[2]\ : DFN1E0C1 - port map(D => secondary_cpt_n2, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[2]_net_1\); - - \coarse_time[31]\ : DFN1P0 - port map(D => \s_coarse_time[31]_net_1\, CLK => lclk_c, PRE - => rstn, Q => coarse_time(31)); - - un4_s_coarse_time_I_162 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - Y => \DWACT_FINC_E[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity apb_lfr_time_management is - - port( coarse_time_i : out std_logic_vector(0 to 0); - pirq : out std_logic_vector(13 downto 12); - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - pwdata_1_0 : in std_logic; - prdata : out std_logic_vector(31 downto 0); - coarse_time_0 : out std_logic; - pwdata_10 : in std_logic; - pwdata_8 : in std_logic; - pwdata_7 : in std_logic; - pwdata_13 : in std_logic; - pwdata_12 : in std_logic; - pwdata_11 : in std_logic; - pwdata_9 : in std_logic; - pwdata_6 : in std_logic; - pwdata_5 : in std_logic; - pwdata_4 : in std_logic; - pwdata_3 : in std_logic; - pwdata_0_d0 : in std_logic; - pwdata_18 : in std_logic; - pwdata_29 : in std_logic; - pwdata_28 : in std_logic; - pwdata_27 : in std_logic; - pwdata_25 : in std_logic; - pwdata_24 : in std_logic; - pwdata_23 : in std_logic; - pwdata_22 : in std_logic; - pwdata_21 : in std_logic; - pwdata_20 : in std_logic; - pwdata_19 : in std_logic; - pwdata_17 : in std_logic; - pwdata_26 : in std_logic; - pwdata_16 : in std_logic; - pwdata_15 : in std_logic; - pwdata_14 : in std_logic; - pwdata_0 : in std_logic_vector(15 downto 0); - paddr : in std_logic_vector(7 downto 3); - psel : in std_logic_vector(15 to 15); - rstn_i : in std_logic; - clk49_152MHz_c : in std_logic; - clk49_152MHz_c_0 : in std_logic; - un1_apbi_7_1 : out std_logic; - rdata60 : out std_logic; - ctrl2 : out std_logic; - rdata59 : out std_logic; - N_232_0 : in std_logic; - un1_apbi_2 : in std_logic; - rdata61_2 : in std_logic; - N_770 : out std_logic; - rdata62_0 : in std_logic; - rdata61 : out std_logic; - un1_apbi_8 : out std_logic; - un1_apbi_7_3 : in std_logic; - un1_apbi_0 : in std_logic; - rdata62 : in std_logic; - rdata60_4 : in std_logic; - rdata59_4 : in std_logic; - readdata55_3 : in std_logic; - rdata62_3 : out std_logic; - pwrite : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end apb_lfr_time_management; - -architecture DEF_ARCH of apb_lfr_time_management is - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lfr_time_management - port( pirq : out std_logic_vector(13 downto 12); - coarse_time_load : in std_logic_vector(31 downto 0) := (others => 'U'); - next_commutation : in std_logic_vector(31 downto 0) := (others => 'U'); - coarse_time : out std_logic_vector(31 downto 0); - coarse_time_i : out std_logic_vector(0 to 0); - fine_time : out std_logic_vector(16 downto 0); - clk49_152MHz_c_0 : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - soft_tick : in std_logic := 'U'; - rstn_i : in std_logic := 'U'; - soft_tick_3 : in std_logic := 'U'; - soft_tick_2 : in std_logic := 'U'; - soft_tick_1 : in std_logic := 'U'; - soft_tick_0 : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - signal \soft_tick_3\, \previous_force_tick_RNIKV47\, - \soft_tick_2\, \soft_tick_1\, \soft_tick_0\, - \Rdata_0_sqmuxa_0\, ctrl2_0, rdata59_0, \rdata62_3\, - rdata60_0, N_380_0, \un1_apbi_4\, - next_commutation_1_sqmuxa_0, \un1_apbi_4_0\, - coarse_time_load_1_sqmuxa_i_0, - coarse_time_load_2_sqmuxa_0_0, \ctrl_m[8]\, \ctrl[8]\, - \coarse_time_load_m[14]\, \coarse_time_load[14]\, - \ctrl_m[14]\, \ctrl[14]\, \coarse_time_load_m[8]\, - \coarse_time_load[8]\, \ctrl_m[15]\, \ctrl[15]\, - \coarse_time_load_m[15]\, \coarse_time_load[15]\, - \ctrl_m[3]\, \ctrl[3]\, \coarse_time_load_m[3]\, - \coarse_time_load[3]\, \ctrl_m[4]\, \ctrl[4]\, - \coarse_time_load_m[4]\, \coarse_time_load[4]\, - \ctrl_m[11]\, \ctrl[11]\, \coarse_time_load_m[11]\, - \coarse_time_load[11]\, \ctrl_1_iv_2[3]\, - \ctrl_1_iv_2[4]\, \ctrl_1_iv_2[11]\, \ctrl_1_iv_2[15]\, - \ctrl_1_iv_2[8]\, \ctrl_1_iv_2[14]\, \ctrl_1_iv_0[8]\, - \fine_time[8]\, \next_commutation_m[8]\, - \ctrl_1_iv_0[14]\, \rdata61\, \fine_time[14]\, - \next_commutation_m[14]\, \ctrl_1_iv_2[1]\, \ctrl[1]\, - \coarse_time_load_m[1]\, \ctrl_1_iv_0[1]\, \fine_time[1]\, - \next_commutation_m[1]\, \ctrl_1_iv_2[2]\, \ctrl[2]\, - \coarse_time_load_m[2]\, \ctrl_1_iv_0[2]\, \fine_time[2]\, - \next_commutation_m[2]\, \ctrl_1_iv_2[0]\, \ctrl[0]\, - \coarse_time_load_m[0]\, \ctrl_1_iv_0[0]\, \fine_time[0]\, - \next_commutation_m[0]\, \ctrl_1_iv_2[6]\, \ctrl[6]\, - \coarse_time_load_m[6]\, \ctrl_1_iv_0[6]\, \fine_time[6]\, - \next_commutation_m[6]\, \ctrl_1_iv_2[7]\, \ctrl[7]\, - \coarse_time_load_m[7]\, \ctrl_1_iv_0[7]\, \fine_time[7]\, - \next_commutation_m[7]\, \ctrl_1_iv_2[9]\, \ctrl[9]\, - \coarse_time_load_m[9]\, \ctrl_1_iv_0[9]\, \fine_time[9]\, - \next_commutation_m[9]\, \ctrl_1_iv_2[12]\, \ctrl[12]\, - \coarse_time_load_m[12]\, \ctrl_1_iv_0[12]\, - \fine_time[12]\, \next_commutation_m[12]\, - \ctrl_1_iv_2[16]\, \ctrl[16]\, \coarse_time_load_m[16]\, - \ctrl_1_iv_0[16]\, \fine_time[16]\, - \next_commutation_m[16]\, \ctrl_1_iv_0[3]\, - \fine_time[3]\, \next_commutation_m[3]\, \ctrl_1_iv_0[4]\, - \fine_time[4]\, \next_commutation_m[4]\, - \ctrl_1_iv_2[10]\, \ctrl[10]\, \coarse_time_load_m[10]\, - \ctrl_1_iv_0[10]\, \fine_time[10]\, - \next_commutation_m[10]\, \ctrl_1_iv_0[11]\, - \fine_time[11]\, \next_commutation_m[11]\, - \ctrl_1_iv_2[5]\, \ctrl[5]\, \coarse_time_load_m[5]\, - \ctrl_1_iv_0[5]\, \fine_time[5]\, \next_commutation_m[5]\, - \ctrl_1_iv_2[13]\, \ctrl[13]\, \coarse_time_load_m[13]\, - \ctrl_1_iv_0[13]\, \fine_time[13]\, - \next_commutation_m[13]\, \ctrl_1_iv_0[15]\, - \fine_time[15]\, \next_commutation_m[15]\, - \ctrl_1_0_iv_0[20]\, \next_commutation[20]\, - \coarse_time_m[20]\, \ctrl_1_0_iv_0[31]\, - \next_commutation[31]\, \coarse_time_m[31]\, - \ctrl_1_0_iv_0[23]\, \next_commutation[23]\, - \coarse_time_m[23]\, \ctrl_1_0_iv_0[25]\, - \next_commutation[25]\, \coarse_time_m[25]\, - \ctrl_1_0_iv_0[26]\, \next_commutation[26]\, - \coarse_time_m[26]\, \ctrl_1_0_iv_0[27]\, - \next_commutation[27]\, \coarse_time_m[27]\, - \ctrl_1_0_iv_0[30]\, \next_commutation[30]\, - \coarse_time_m[30]\, \ctrl_1_0_iv_0[17]\, - \next_commutation[17]\, \coarse_time_m[17]\, - \ctrl_1_0_iv_0[18]\, \next_commutation[18]\, - \coarse_time_m[18]\, \ctrl_1_0_iv_0[19]\, - \next_commutation[19]\, \coarse_time_m[19]\, - \ctrl_1_0_iv_0[21]\, \next_commutation[21]\, - \coarse_time_m[21]\, \ctrl_1_0_iv_0[22]\, - \next_commutation[22]\, \coarse_time_m[22]\, - \ctrl_1_0_iv_0[24]\, \next_commutation[24]\, - \coarse_time_m[24]\, \ctrl_1_0_iv_0[28]\, - \next_commutation[28]\, \coarse_time_m[28]\, - \ctrl_1_0_iv_0[29]\, \next_commutation[29]\, - \coarse_time_m[29]\, coarse_time_load_2_sqmuxa_0, - un1_apbi_8_net_1, \un1_apbi_8_0\, \ctrl_1[15]\, - \coarse_time_m[15]\, \ctrl_1[13]\, \coarse_time_m[13]\, - \ctrl_1[5]\, \coarse_time_m[5]\, \ctrl_1[11]\, - \coarse_time_m[11]\, \ctrl_1[10]\, \coarse_time_m[10]\, - \ctrl_1[4]\, \coarse_time_m[4]\, \ctrl_1[3]\, - \coarse_time_m[3]\, \ctrl_1[29]\, - \coarse_time_load_m[29]\, \ctrl_m[29]\, \ctrl_1[28]\, - \coarse_time_load_m[28]\, \ctrl_m[28]\, \ctrl_1[24]\, - \coarse_time_load_m[24]\, \ctrl_m[24]\, \ctrl_1[22]\, - \coarse_time_load_m[22]\, \ctrl_m[22]\, \ctrl_1[21]\, - \coarse_time_load_m[21]\, \ctrl_m[21]\, \ctrl_1[19]\, - \coarse_time_load_m[19]\, \ctrl_m[19]\, \ctrl_1[18]\, - \coarse_time_load_m[18]\, \ctrl_m[18]\, \ctrl_1[17]\, - \coarse_time_load_m[17]\, \ctrl_m[17]\, \ctrl_1[16]\, - \coarse_time_m[16]\, \ctrl_1[12]\, \coarse_time_m[12]\, - \ctrl_1[9]\, \coarse_time_m[9]\, \ctrl_1[7]\, - \coarse_time_m[7]\, \ctrl_1[6]\, \coarse_time_m[6]\, - \ctrl_1[30]\, \coarse_time_load_m[30]\, \ctrl_m[30]\, - \ctrl_1[27]\, \coarse_time_load_m[27]\, \ctrl_m[27]\, - \ctrl_1[26]\, \coarse_time_load_m[26]\, \ctrl_m[26]\, - \ctrl_1[25]\, \coarse_time_load_m[25]\, \ctrl_m[25]\, - \ctrl_1[23]\, \coarse_time_load_m[23]\, \ctrl_m[23]\, - \ctrl_1[0]\, \coarse_time_m[0]\, \ctrl_1[2]\, - \coarse_time_m[2]\, \ctrl_1[1]\, \coarse_time_m[1]\, - \ctrl_1[14]\, \coarse_time_m[14]\, \ctrl_1[31]\, - \coarse_time_load_m[31]\, \ctrl_m[31]\, \ctrl_1[20]\, - \coarse_time_load_m[20]\, \ctrl_m[20]\, \ctrl_1[8]\, - \coarse_time_m[8]\, \coarse_time_load[5]\, - \coarse_time[5]\, \next_commutation[5]\, - \coarse_time_load[13]\, \coarse_time[13]\, - \next_commutation[13]\, \coarse_time[15]\, - \next_commutation[15]\, N_120, \coarse_time_load[1]\, - N_125, \coarse_time_load[6]\, N_131, - \coarse_time_load[12]\, N_133, \coarse_time_load_3[1]\, - \coarse_time_load_3[6]\, \coarse_time_load_3[12]\, - \coarse_time_load_3[14]\, \coarse_time[3]\, - \next_commutation[3]\, \coarse_time[4]\, - \next_commutation[4]\, \coarse_time_load[10]\, - \coarse_time[10]\, \next_commutation[10]\, - \coarse_time[11]\, \next_commutation[11]\, N_123, N_126, - \coarse_time_load[7]\, N_127, N_128, - \coarse_time_load[9]\, N_129, N_130, - \coarse_time_load_3[4]\, \coarse_time_load_3[7]\, - \coarse_time_load_3[8]\, \coarse_time_load_3[9]\, - \coarse_time_load_3[10]\, \coarse_time_load_3[11]\, - \Rdata_0_sqmuxa\, \coarse_time[6]\, \next_commutation[6]\, - \coarse_time[7]\, \next_commutation[7]\, \coarse_time[9]\, - \next_commutation[9]\, \coarse_time[12]\, - \next_commutation[12]\, \coarse_time_load[16]\, - \coarse_time[16]\, \next_commutation[16]\, \ctrl[17]\, - \ctrl2\, \coarse_time_load[17]\, \coarse_time[17]\, - \ctrl[18]\, \coarse_time_load[18]\, \coarse_time[18]\, - \ctrl[19]\, \coarse_time_load[19]\, \coarse_time[19]\, - \ctrl[21]\, \coarse_time_load[21]\, \rdata59\, - \coarse_time[21]\, \ctrl[22]\, \coarse_time_load[22]\, - \coarse_time[22]\, \ctrl[24]\, \coarse_time_load[24]\, - \coarse_time[24]\, \ctrl[28]\, \coarse_time_load[28]\, - \rdata60\, \coarse_time[28]\, \ctrl[29]\, - \coarse_time_load[29]\, \coarse_time[29]\, N_121, - \coarse_time_load[2]\, N_122, N_135, N_136, N_137, N_147, - \coarse_time_load_3[2]\, \coarse_time_load_3[3]\, - \coarse_time_load_3[16]\, \coarse_time_load_3[17]\, - \coarse_time_load_3[18]\, \coarse_time_load_3[28]\, - \ctrl[23]\, \coarse_time_load[23]\, \coarse_time[23]\, - \ctrl[25]\, \coarse_time_load[25]\, \coarse_time[25]\, - \ctrl[26]\, \coarse_time_load[26]\, \coarse_time[26]\, - \ctrl[27]\, \coarse_time_load[27]\, \coarse_time[27]\, - \ctrl[30]\, \coarse_time_load[30]\, \coarse_time[30]\, - N_119, \coarse_time_load[0]\, coarse_time_load_1_sqmuxa_i, - N_124, N_134, N_138, N_140, N_141, N_142, N_143, N_144, - N_145, N_146, N_148, N_149, \coarse_time_load_3[0]\, - \coarse_time_load_3[5]\, \coarse_time_load_3[15]\, - \coarse_time_load_3[19]\, \coarse_time_load_3[21]\, - \coarse_time_load_3[22]\, \coarse_time_load_3[23]\, - \coarse_time_load_3[24]\, \coarse_time_load_3[25]\, - \coarse_time_load_3[26]\, \coarse_time_load_3[27]\, - \coarse_time_load_3[29]\, \coarse_time_load_3[30]\, - \next_commutation[0]\, \ctrl_0[0]\, - next_commutation_1_sqmuxa, N_380, ctrl_1_sqmuxa, - \next_commutation[2]\, \coarse_time[2]\, - \next_commutation[1]\, \coarse_time[1]\, \N_770\, - \next_commutation[14]\, \coarse_time[14]\, - \coarse_time_load_3[31]\, N_150, \coarse_time_load[31]\, - \coarse_time[31]\, \ctrl[31]\, \coarse_time_load_3[13]\, - N_132, \coarse_time[20]\, \coarse_time_load[20]\, - \ctrl[20]\, \coarse_time_load_3[20]\, N_139, - \next_commutation[8]\, \coarse_time[8]\, \force_tick\, - \previous_force_tick\, \soft_tick\, \coarse_time[0]\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : lfr_time_management - Use entity work.lfr_time_management(DEF_ARCH); -begin - - coarse_time_0 <= \coarse_time[0]\; - rdata60 <= \rdata60\; - ctrl2 <= \ctrl2\; - rdata59 <= \rdata59\; - N_770 <= \N_770\; - rdata61 <= \rdata61\; - un1_apbi_8 <= un1_apbi_8_net_1; - rdata62_3 <= \rdata62_3\; - - \Rdata_RNO_5[11]\ : OR2A - port map(A => \ctrl[11]\, B => ctrl2_0, Y => \ctrl_m[11]\); - - \Rdata_RNO_3[7]\ : OR2A - port map(A => \next_commutation[7]\, B => rdata62, Y => - \next_commutation_m[7]\); - - \r.ctrl_RNO[0]\ : NOR2A - port map(A => pwdata_0(0), B => \un1_apbi_4\, Y => - \ctrl_0[0]\); - - \Rdata_RNO_0[20]\ : OR2A - port map(A => \coarse_time_load[20]\, B => \rdata59\, Y => - \coarse_time_load_m[20]\); - - \r.coarse_time_load[11]\ : DFN1C0 - port map(D => \coarse_time_load_3[11]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[11]\); - - \Rdata_RNO_4[8]\ : OR2A - port map(A => \coarse_time_load[8]\, B => rdata59_0, Y => - \coarse_time_load_m[8]\); - - \r.ctrl[24]\ : DFN1E1C0 - port map(D => pwdata_22, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[24]\); - - \Rdata_RNO_1[30]\ : OR2A - port map(A => \ctrl[30]\, B => \ctrl2\, Y => \ctrl_m[30]\); - - \r.coarse_time_load_RNO_0[19]\ : MX2C - port map(A => pwdata_17, B => \coarse_time_load[19]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_138); - - \Rdata_RNO_3[20]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[20]\, Y => - \coarse_time_m[20]\); - - \r.coarse_time_load_RNO_0[18]\ : MX2C - port map(A => pwdata_16, B => \coarse_time_load[18]\, S => - coarse_time_load_1_sqmuxa_i_0, Y => N_137); - - \Rdata_RNO_3[4]\ : OR2A - port map(A => \next_commutation[4]\, B => rdata62, Y => - \next_commutation_m[4]\); - - \Rdata[15]\ : DFN1E1C0 - port map(D => \ctrl_1[15]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(15)); - - \r.coarse_time_load_RNO[29]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_148, Y => - \coarse_time_load_3[29]\); - - \Rdata[9]\ : DFN1E1C0 - port map(D => \ctrl_1[9]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(9)); - - \Rdata_RNO_0[8]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[8]\, Y => - \coarse_time_m[8]\); - - \r.coarse_time_load_RNO_0[26]\ : MX2C - port map(A => pwdata_24, B => \coarse_time_load[26]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_145); - - \r.coarse_time_load_RNO[7]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_126, Y => - \coarse_time_load_3[7]\); - - \r.coarse_time_load[25]\ : DFN1C0 - port map(D => \coarse_time_load_3[25]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[25]\); - - \Rdata_RNO[31]\ : OR3C - port map(A => \coarse_time_load_m[31]\, B => \ctrl_m[31]\, - C => \ctrl_1_0_iv_0[31]\, Y => \ctrl_1[31]\); - - \r.coarse_time_load_RNO_0[6]\ : MX2C - port map(A => pwdata_0(6), B => \coarse_time_load[6]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_125); - - \Rdata_RNO_1[6]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[6]\, C => - \next_commutation_m[6]\, Y => \ctrl_1_iv_0[6]\); - - \r.coarse_time_load_RNO[1]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_120, Y => - \coarse_time_load_3[1]\); - - \r.coarse_time_load_2_sqmuxa_0_0\ : AO1A - port map(A => paddr(7), B => un1_apbi_7_3, C => - un1_apbi_8_net_1, Y => coarse_time_load_2_sqmuxa_0_0); - - \Rdata_RNO_1[21]\ : OR2A - port map(A => \ctrl[21]\, B => \ctrl2\, Y => \ctrl_m[21]\); - - soft_tick : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick\); - - \Rdata_RNO_0[27]\ : OR2A - port map(A => \coarse_time_load[27]\, B => \rdata59\, Y => - \coarse_time_load_m[27]\); - - \r.coarse_time_load[30]\ : DFN1C0 - port map(D => \coarse_time_load_3[30]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[30]\); - - \Rdata_RNO_5[4]\ : OR2A - port map(A => \ctrl[4]\, B => ctrl2_0, Y => \ctrl_m[4]\); - - \r.next_commutation_1_sqmuxa_0\ : NOR2 - port map(A => rdata62, B => \un1_apbi_4\, Y => - next_commutation_1_sqmuxa_0); - - \Rdata_RNO_4[3]\ : OR2A - port map(A => \coarse_time_load[3]\, B => rdata59_0, Y => - \coarse_time_load_m[3]\); - - \r.coarse_time_load_RNO[17]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_136, Y => - \coarse_time_load_3[17]\); - - \Rdata_RNO_2[25]\ : OA1A - port map(A => \next_commutation[25]\, B => rdata62_0, C => - \coarse_time_m[25]\, Y => \ctrl_1_0_iv_0[25]\); - - \Rdata_RNO_0[13]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[13]\, Y => - \coarse_time_m[13]\); - - \r.ctrl[14]\ : DFN1E1C0 - port map(D => pwdata_12, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[14]\); - - \r.coarse_time_load[31]\ : DFN1P0 - port map(D => \coarse_time_load_3[31]\, CLK => lclk_c, PRE - => rstn, Q => \coarse_time_load[31]\); - - \Rdata[31]\ : DFN1E1C0 - port map(D => \ctrl_1[31]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(31)); - - \Rdata_RNO_3[27]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[27]\, Y => - \coarse_time_m[27]\); - - \Rdata_RNO_1[19]\ : OR2A - port map(A => \ctrl[19]\, B => \ctrl2\, Y => \ctrl_m[19]\); - - \r.coarse_time_load[13]\ : DFN1C0 - port map(D => \coarse_time_load_3[13]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[13]\); - - \Rdata_RNO_0[24]\ : OR2A - port map(A => \coarse_time_load[24]\, B => \rdata59\, Y => - \coarse_time_load_m[24]\); - - \Rdata_RNO_2[28]\ : OA1A - port map(A => \next_commutation[28]\, B => rdata62_0, C => - \coarse_time_m[28]\, Y => \ctrl_1_0_iv_0[28]\); - - \r.next_commutation[7]\ : DFN1E1P0 - port map(D => pwdata_5, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[7]\); - - \r.ctrl2_0\ : OR2 - port map(A => \rdata62_3\, B => readdata55_3, Y => ctrl2_0); - - \Rdata[26]\ : DFN1E1C0 - port map(D => \ctrl_1[26]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(26)); - - \r.coarse_time_load_RNO[16]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_135, Y => - \coarse_time_load_3[16]\); - - \Rdata[6]\ : DFN1E1C0 - port map(D => \ctrl_1[6]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(6)); - - \Rdata_RNO_3[24]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[24]\, Y => - \coarse_time_m[24]\); - - \Rdata[24]\ : DFN1E1C0 - port map(D => \ctrl_1[24]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(24)); - - \r.next_commutation[0]\ : DFN1E1P0 - port map(D => pwdata_0(0), CLK => lclk_c, PRE => rstn, E - => next_commutation_1_sqmuxa_0, Q => - \next_commutation[0]\); - - \Rdata[27]\ : DFN1E1C0 - port map(D => \ctrl_1[27]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(27)); - - \r.ctrl_RNO_0[0]\ : AO1 - port map(A => \un1_apbi_4\, B => \ctrl[0]\, C => N_380_0, Y - => ctrl_1_sqmuxa); - - \Rdata_RNO[29]\ : OR3C - port map(A => \coarse_time_load_m[29]\, B => \ctrl_m[29]\, - C => \ctrl_1_0_iv_0[29]\, Y => \ctrl_1[29]\); - - \un1_apbi_8\ : NOR2 - port map(A => \un1_apbi_8_0\, B => N_232_0, Y => - un1_apbi_8_net_1); - - \r.coarse_time_load_RNO[21]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_140, Y => - \coarse_time_load_3[21]\); - - \Rdata_RNO_2[1]\ : OA1A - port map(A => \ctrl[1]\, B => ctrl2_0, C => - \coarse_time_load_m[1]\, Y => \ctrl_1_iv_2[1]\); - - \Rdata_RNO_3[30]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[30]\, Y => - \coarse_time_m[30]\); - - \r.ctrl[30]\ : DFN1E1C0 - port map(D => pwdata_28, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[30]\); - - \Rdata_RNO_1[4]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[4]\, C => - \next_commutation_m[4]\, Y => \ctrl_1_iv_0[4]\); - - \r.ctrl[28]\ : DFN1E1C0 - port map(D => pwdata_26, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[28]\); - - \r.coarse_time_load_RNO[14]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_133, Y => - \coarse_time_load_3[14]\); - - \Rdata_RNO[23]\ : OR3C - port map(A => \coarse_time_load_m[23]\, B => \ctrl_m[23]\, - C => \ctrl_1_0_iv_0[23]\, Y => \ctrl_1[23]\); - - \r.coarse_time_load_RNO_0[23]\ : MX2C - port map(A => pwdata_21, B => \coarse_time_load[23]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_142); - - \Rdata_RNO_1[22]\ : OR2A - port map(A => \ctrl[22]\, B => \ctrl2\, Y => \ctrl_m[22]\); - - \Rdata_RNO_2[8]\ : AND2 - port map(A => \coarse_time_load_m[8]\, B => \ctrl_m[8]\, Y - => \ctrl_1_iv_2[8]\); - - \Rdata_RNO_2[6]\ : OA1A - port map(A => \ctrl[6]\, B => ctrl2_0, C => - \coarse_time_load_m[6]\, Y => \ctrl_1_iv_2[6]\); - - \Rdata_RNO[20]\ : OR3C - port map(A => \coarse_time_load_m[20]\, B => \ctrl_m[20]\, - C => \ctrl_1_0_iv_0[20]\, Y => \ctrl_1[20]\); - - \Rdata_RNO_2[21]\ : OA1A - port map(A => \next_commutation[21]\, B => rdata62_0, C => - \coarse_time_m[21]\, Y => \ctrl_1_0_iv_0[21]\); - - \Rdata_RNO_2[19]\ : OA1A - port map(A => \next_commutation[19]\, B => rdata62_0, C => - \coarse_time_m[19]\, Y => \ctrl_1_0_iv_0[19]\); - - \Rdata_RNO_0[30]\ : OR2A - port map(A => \coarse_time_load[30]\, B => \rdata59\, Y => - \coarse_time_load_m[30]\); - - \Rdata[5]\ : DFN1E1C0 - port map(D => \ctrl_1[5]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(5)); - - \r.next_commutation[2]\ : DFN1E1P0 - port map(D => pwdata_0_d0, CLK => lclk_c, PRE => rstn, E - => next_commutation_1_sqmuxa, Q => \next_commutation[2]\); - - \Rdata_RNO[24]\ : OR3C - port map(A => \coarse_time_load_m[24]\, B => \ctrl_m[24]\, - C => \ctrl_1_0_iv_0[24]\, Y => \ctrl_1[24]\); - - \Rdata_RNO_1[26]\ : OR2A - port map(A => \ctrl[26]\, B => \ctrl2\, Y => \ctrl_m[26]\); - - \Rdata_RNO_0[0]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[0]\, Y => - \coarse_time_m[0]\); - - \Rdata_RNO_0[15]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[15]\, Y => - \coarse_time_m[15]\); - - \Rdata_RNO[27]\ : OR3C - port map(A => \coarse_time_load_m[27]\, B => \ctrl_m[27]\, - C => \ctrl_1_0_iv_0[27]\, Y => \ctrl_1[27]\); - - \r.ctrl[9]\ : DFN1E1C0 - port map(D => pwdata_0(9), CLK => lclk_c, CLR => rstn, E - => N_380, Q => \ctrl[9]\); - - \Rdata_RNO_0[18]\ : OR2A - port map(A => \coarse_time_load[18]\, B => rdata59_0, Y => - \coarse_time_load_m[18]\); - - \r.coarse_time_load_RNO[0]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0, C => N_119, Y => - \coarse_time_load_3[0]\); - - \r.ctrl[4]\ : DFN1E1C0 - port map(D => pwdata_1_3, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[4]\); - - \Rdata_RNO_1[7]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[7]\, C => - \next_commutation_m[7]\, Y => \ctrl_1_iv_0[7]\); - - \r.coarse_time_load_RNO_0[31]\ : MX2C - port map(A => pwdata_29, B => \coarse_time_load[31]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_150); - - \r.coarse_time_load_RNO[18]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_137, Y => - \coarse_time_load_3[18]\); - - \r.ctrl[18]\ : DFN1E1C0 - port map(D => pwdata_16, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[18]\); - - \r.next_commutation[18]\ : DFN1E1P0 - port map(D => pwdata_16, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[18]\); - - \Rdata_RNO[22]\ : OR3C - port map(A => \coarse_time_load_m[22]\, B => \ctrl_m[22]\, - C => \ctrl_1_0_iv_0[22]\, Y => \ctrl_1[22]\); - - \r.coarse_time_load_RNO[22]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_141, Y => - \coarse_time_load_3[22]\); - - un1_apbi_4_0 : OR2 - port map(A => un1_apbi_0, B => psel(15), Y => - \un1_apbi_4_0\); - - \Rdata_RNO_4[13]\ : OR2A - port map(A => \coarse_time_load[13]\, B => rdata59_0, Y => - \coarse_time_load_m[13]\); - - GND_i : GND - port map(Y => \GND\); - - \Rdata_RNO_2[0]\ : OA1A - port map(A => \ctrl[0]\, B => ctrl2_0, C => - \coarse_time_load_m[0]\, Y => \ctrl_1_iv_2[0]\); - - \r.ctrl[6]\ : DFN1E1C0 - port map(D => pwdata_4, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[6]\); - - \r.coarse_time_load_RNO_0[5]\ : MX2C - port map(A => pwdata_0(5), B => \coarse_time_load[5]\, S - => coarse_time_load_1_sqmuxa_i, Y => N_124); - - \Rdata[22]\ : DFN1E1C0 - port map(D => \ctrl_1[22]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(22)); - - \r.ctrl[0]\ : DFN1E1C0 - port map(D => \ctrl_0[0]\, CLK => lclk_c, CLR => rstn, E - => ctrl_1_sqmuxa, Q => \ctrl[0]\); - - \r.coarse_time_load[5]\ : DFN1C0 - port map(D => \coarse_time_load_3[5]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[5]\); - - \Rdata[3]\ : DFN1E1C0 - port map(D => \ctrl_1[3]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(3)); - - \Rdata[16]\ : DFN1E1C0 - port map(D => \ctrl_1[16]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(16)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Rdata_RNO_2[22]\ : OA1A - port map(A => \next_commutation[22]\, B => rdata62_0, C => - \coarse_time_m[22]\, Y => \ctrl_1_0_iv_0[22]\); - - \Rdata_RNO_3[13]\ : OR2A - port map(A => \next_commutation[13]\, B => rdata62_0, Y => - \next_commutation_m[13]\); - - \r.coarse_time_load_RNO_0[16]\ : MX2C - port map(A => pwdata_14, B => \coarse_time_load[16]\, S => - coarse_time_load_1_sqmuxa_i_0, Y => N_135); - - \Rdata[14]\ : DFN1E1C0 - port map(D => \ctrl_1[14]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(14)); - - \r.coarse_time_load_RNO_0[21]\ : MX2C - port map(A => pwdata_19, B => \coarse_time_load[21]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_140); - - \Rdata_RNO_1[20]\ : OR2A - port map(A => \ctrl[20]\, B => \ctrl2\, Y => \ctrl_m[20]\); - - \r.coarse_time_load_RNO_0[25]\ : MX2C - port map(A => pwdata_23, B => \coarse_time_load[25]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_144); - - \Rdata_RNO_0[29]\ : OR2A - port map(A => \coarse_time_load[29]\, B => \rdata59\, Y => - \coarse_time_load_m[29]\); - - \Rdata[17]\ : DFN1E1C0 - port map(D => \ctrl_1[17]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(17)); - - \Rdata_RNO_0[11]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[11]\, Y => - \coarse_time_m[11]\); - - \Rdata[20]\ : DFN1E1C0 - port map(D => \ctrl_1[20]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(20)); - - \Rdata_RNO_3[29]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[29]\, Y => - \coarse_time_m[29]\); - - \Rdata_RNO_5[14]\ : OR2A - port map(A => \ctrl[14]\, B => ctrl2_0, Y => \ctrl_m[14]\); - - \Rdata_RNO[18]\ : OR3C - port map(A => \coarse_time_load_m[18]\, B => \ctrl_m[18]\, - C => \ctrl_1_0_iv_0[18]\, Y => \ctrl_1[18]\); - - \r.ctrl[29]\ : DFN1E1C0 - port map(D => pwdata_27, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[29]\); - - \Rdata_RNO_2[26]\ : OA1A - port map(A => \next_commutation[26]\, B => rdata62_0, C => - \coarse_time_m[26]\, Y => \ctrl_1_0_iv_0[26]\); - - \Rdata_RNO_1[5]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[5]\, C => - \next_commutation_m[5]\, Y => \ctrl_1_iv_0[5]\); - - \r.coarse_time_load_RNO_0[8]\ : MX2C - port map(A => pwdata_0(8), B => \coarse_time_load[8]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_127); - - \Rdata_RNO_3[1]\ : OR2A - port map(A => \next_commutation[1]\, B => rdata62, Y => - \next_commutation_m[1]\); - - \Rdata_RNO_1[1]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[1]\, C => - \next_commutation_m[1]\, Y => \ctrl_1_iv_0[1]\); - - \r.coarse_time_load[4]\ : DFN1C0 - port map(D => \coarse_time_load_3[4]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[4]\); - - \r.coarse_time_load_RNO[5]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0, C => N_124, Y => - \coarse_time_load_3[5]\); - - \Rdata_RNO[11]\ : OR3C - port map(A => \coarse_time_m[11]\, B => \ctrl_1_iv_0[11]\, - C => \ctrl_1_iv_2[11]\, Y => \ctrl_1[11]\); - - \r.coarse_time_load_RNO[20]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_139, Y => - \coarse_time_load_3[20]\); - - \Rdata_RNO_4[7]\ : OR2A - port map(A => \coarse_time_load[7]\, B => rdata59_0, Y => - \coarse_time_load_m[7]\); - - rdata78 : NOR2 - port map(A => \rdata62_3\, B => rdata60_4, Y => \rdata60\); - - \r.ctrl2\ : OR2 - port map(A => \rdata62_3\, B => readdata55_3, Y => \ctrl2\); - - \Rdata_RNO[5]\ : OR3C - port map(A => \coarse_time_m[5]\, B => \ctrl_1_iv_0[5]\, C - => \ctrl_1_iv_2[5]\, Y => \ctrl_1[5]\); - - rdata78_3 : OR2 - port map(A => paddr(7), B => paddr(6), Y => \rdata62_3\); - - \Rdata_RNO_1[27]\ : OR2A - port map(A => \ctrl[27]\, B => \ctrl2\, Y => \ctrl_m[27]\); - - \r.coarse_time_load_RNO[6]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_125, Y => - \coarse_time_load_3[6]\); - - \r.coarse_time_load[20]\ : DFN1C0 - port map(D => \coarse_time_load_3[20]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[20]\); - - \Rdata_RNO_4[9]\ : OR2A - port map(A => \coarse_time_load[9]\, B => rdata59_0, Y => - \coarse_time_load_m[9]\); - - \Rdata_RNO_4[15]\ : OR2A - port map(A => \coarse_time_load[15]\, B => rdata59_0, Y => - \coarse_time_load_m[15]\); - - \r.coarse_time_load[21]\ : DFN1C0 - port map(D => \coarse_time_load_3[21]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[21]\); - - \r.coarse_time_load[18]\ : DFN1C0 - port map(D => \coarse_time_load_3[18]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[18]\); - - \Rdata_RNO_1[24]\ : OR2A - port map(A => \ctrl[24]\, B => \ctrl2\, Y => \ctrl_m[24]\); - - \r.ctrl[26]\ : DFN1E1C0 - port map(D => pwdata_24, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[26]\); - - \Rdata_RNO_1[9]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[9]\, C => - \next_commutation_m[9]\, Y => \ctrl_1_iv_0[9]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.coarse_time_load_RNO_0[24]\ : MX2C - port map(A => pwdata_22, B => \coarse_time_load[24]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_143); - - \r.coarse_time_load[14]\ : DFN1C0 - port map(D => \coarse_time_load_3[14]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[14]\); - - \r.ctrl[19]\ : DFN1E1C0 - port map(D => pwdata_17, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[19]\); - - soft_tick_0 : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick_0\); - - \r.ctrl_0_sqmuxa_0\ : NOR2 - port map(A => \un1_apbi_4\, B => ctrl2_0, Y => N_380_0); - - \Rdata_RNO_0[12]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[12]\, Y => - \coarse_time_m[12]\); - - \Rdata_RNO_3[15]\ : OR2A - port map(A => \next_commutation[15]\, B => rdata62, Y => - \next_commutation_m[15]\); - - \Rdata_RNO[3]\ : OR3C - port map(A => \coarse_time_m[3]\, B => \ctrl_1_iv_0[3]\, C - => \ctrl_1_iv_2[3]\, Y => \ctrl_1[3]\); - - \r.coarse_time_load_RNO_0[13]\ : MX2C - port map(A => pwdata_0(13), B => \coarse_time_load[13]\, S - => coarse_time_load_1_sqmuxa_i, Y => N_132); - - \Rdata_RNO_1[13]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[13]\, C => - \next_commutation_m[13]\, Y => \ctrl_1_iv_0[13]\); - - \Rdata_RNO_2[20]\ : OA1A - port map(A => \next_commutation[20]\, B => rdata62_0, C => - \coarse_time_m[20]\, Y => \ctrl_1_0_iv_0[20]\); - - \Rdata_RNO_1[3]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[3]\, C => - \next_commutation_m[3]\, Y => \ctrl_1_iv_0[3]\); - - \Rdata_RNO_3[18]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[18]\, Y => - \coarse_time_m[18]\); - - \r.coarse_time_load_2_sqmuxa_0\ : AO1A - port map(A => paddr(7), B => un1_apbi_7_3, C => - un1_apbi_8_net_1, Y => coarse_time_load_2_sqmuxa_0); - - \Rdata_RNO_1[2]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[2]\, C => - \next_commutation_m[2]\, Y => \ctrl_1_iv_0[2]\); - - \r.ctrl[23]\ : DFN1E1C0 - port map(D => pwdata_21, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[23]\); - - \r.next_commutation[28]\ : DFN1E1P0 - port map(D => pwdata_26, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[28]\); - - \r.coarse_time_load_RNO[2]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_121, Y => - \coarse_time_load_3[2]\); - - \Rdata_RNO_3[5]\ : OR2A - port map(A => \next_commutation[5]\, B => rdata62_0, Y => - \next_commutation_m[5]\); - - \Rdata_RNO_0[4]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[4]\, Y => - \coarse_time_m[4]\); - - \r.coarse_time_load[6]\ : DFN1C0 - port map(D => \coarse_time_load_3[6]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[6]\); - - \Rdata_RNO_0[16]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[16]\, Y => - \coarse_time_m[16]\); - - \Rdata[12]\ : DFN1E1C0 - port map(D => \ctrl_1[12]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(12)); - - \r.coarse_time_load[16]\ : DFN1C0 - port map(D => \coarse_time_load_3[16]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[16]\); - - \r.coarse_time_load_RNO[13]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_132, Y => - \coarse_time_load_3[13]\); - - \r.coarse_time_load_RNO_0[7]\ : MX2C - port map(A => pwdata_0(7), B => \coarse_time_load[7]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_126); - - \r.coarse_time_load_RNO[31]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_150, Y => - \coarse_time_load_3[31]\); - - \r.next_commutation[8]\ : DFN1E1P0 - port map(D => pwdata_6, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[8]\); - - \r.coarse_time_load[9]\ : DFN1C0 - port map(D => \coarse_time_load_3[9]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[9]\); - - \r.ctrl[16]\ : DFN1E1C0 - port map(D => pwdata_14, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[16]\); - - \r.coarse_time_load[23]\ : DFN1C0 - port map(D => \coarse_time_load_3[23]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[23]\); - - \un1_apbi_7_1\ : OR2 - port map(A => paddr(4), B => paddr(3), Y => un1_apbi_7_1); - - \r.coarse_time_load_RNO[3]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_122, Y => - \coarse_time_load_3[3]\); - - \Rdata_RNO_4[11]\ : OR2A - port map(A => \coarse_time_load[11]\, B => rdata59_0, Y => - \coarse_time_load_m[11]\); - - \Rdata[10]\ : DFN1E1C0 - port map(D => \ctrl_1[10]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(10)); - - \Rdata_RNO_2[27]\ : OA1A - port map(A => \next_commutation[27]\, B => rdata62_0, C => - \coarse_time_m[27]\, Y => \ctrl_1_0_iv_0[27]\); - - \Rdata_RNO_4[2]\ : OR2A - port map(A => \coarse_time_load[2]\, B => \rdata59\, Y => - \coarse_time_load_m[2]\); - - \Rdata_RNO_3[2]\ : OR2A - port map(A => \next_commutation[2]\, B => rdata62, Y => - \next_commutation_m[2]\); - - \Rdata_RNO_2[7]\ : OA1A - port map(A => \ctrl[7]\, B => ctrl2_0, C => - \coarse_time_load_m[7]\, Y => \ctrl_1_iv_2[7]\); - - \Rdata_RNO_0[7]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[7]\, Y => - \coarse_time_m[7]\); - - \r.ctrl[1]\ : DFN1E1C0 - port map(D => pwdata_1_0, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[1]\); - - \Rdata_RNO_3[11]\ : OR2A - port map(A => \next_commutation[11]\, B => rdata62, Y => - \next_commutation_m[11]\); - - \Rdata_RNO_2[13]\ : OA1A - port map(A => \ctrl[13]\, B => ctrl2_0, C => - \coarse_time_load_m[13]\, Y => \ctrl_1_iv_2[13]\); - - un1_apbi_4 : OR2 - port map(A => un1_apbi_0, B => psel(15), Y => \un1_apbi_4\); - - \Rdata_RNO_2[24]\ : OA1A - port map(A => \next_commutation[24]\, B => rdata62_0, C => - \coarse_time_m[24]\, Y => \ctrl_1_0_iv_0[24]\); - - \r.ctrl[13]\ : DFN1E1C0 - port map(D => pwdata_11, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[13]\); - - \Rdata_RNO[0]\ : OR3C - port map(A => \coarse_time_m[0]\, B => \ctrl_1_iv_0[0]\, C - => \ctrl_1_iv_2[0]\, Y => \ctrl_1[0]\); - - \r.ctrl[27]\ : DFN1E1C0 - port map(D => pwdata_25, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[27]\); - - \r.coarse_time_load_RNO[15]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_134, Y => - \coarse_time_load_3[15]\); - - \Rdata_RNO_2[31]\ : OA1A - port map(A => \next_commutation[31]\, B => rdata62_0, C => - \coarse_time_m[31]\, Y => \ctrl_1_0_iv_0[31]\); - - \Rdata_RNO_0[2]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[2]\, Y => - \coarse_time_m[2]\); - - \r.ctrl[8]\ : DFN1E1C0 - port map(D => pwdata_6, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[8]\); - - \Rdata[2]\ : DFN1E1C0 - port map(D => \ctrl_1[2]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(2)); - - \Rdata_RNO_1[15]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[15]\, C => - \next_commutation_m[15]\, Y => \ctrl_1_iv_0[15]\); - - \r.coarse_time_load_RNO_0[22]\ : MX2C - port map(A => pwdata_20, B => \coarse_time_load[22]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_141); - - \Rdata_RNO_0[10]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[10]\, Y => - \coarse_time_m[10]\); - - \r.next_commutation[6]\ : DFN1E1P0 - port map(D => pwdata_4, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[6]\); - - \r.coarse_time_load[12]\ : DFN1C0 - port map(D => \coarse_time_load_3[12]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[12]\); - - \r.coarse_time_load_RNO_0[11]\ : MX2C - port map(A => pwdata_0(11), B => \coarse_time_load[11]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_130); - - \Rdata_RNO_4[0]\ : OR2A - port map(A => \coarse_time_load[0]\, B => \rdata59\, Y => - \coarse_time_load_m[0]\); - - \Rdata_RNO_1[18]\ : OR2A - port map(A => \ctrl[18]\, B => \ctrl2\, Y => \ctrl_m[18]\); - - \Rdata[4]\ : DFN1E1C0 - port map(D => \ctrl_1[4]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(4)); - - \r.coarse_time_load_RNO_0[15]\ : MX2C - port map(A => pwdata_0(15), B => \coarse_time_load[15]\, S - => coarse_time_load_1_sqmuxa_i, Y => N_134); - - \r.coarse_time_load_RNO[27]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_146, Y => - \coarse_time_load_3[27]\); - - \Rdata_RNO_0[5]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[5]\, Y => - \coarse_time_m[5]\); - - \r.next_commutation[11]\ : DFN1E1P0 - port map(D => pwdata_9, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[11]\); - - \r.next_commutation[15]\ : DFN1E1P0 - port map(D => pwdata_13, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[15]\); - - \Rdata_RNO_2[9]\ : OA1A - port map(A => \ctrl[9]\, B => ctrl2_0, C => - \coarse_time_load_m[9]\, Y => \ctrl_1_iv_2[9]\); - - \r.coarse_time_load_RNO[26]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_145, Y => - \coarse_time_load_3[26]\); - - \Rdata_RNO[8]\ : OR3C - port map(A => \coarse_time_m[8]\, B => \ctrl_1_iv_0[8]\, C - => \ctrl_1_iv_2[8]\, Y => \ctrl_1[8]\); - - \Rdata_RNO_4[12]\ : OR2A - port map(A => \coarse_time_load[12]\, B => rdata59_0, Y => - \coarse_time_load_m[12]\); - - \Rdata_RNO[28]\ : OR3C - port map(A => \coarse_time_load_m[28]\, B => \ctrl_m[28]\, - C => \ctrl_1_0_iv_0[28]\, Y => \ctrl_1[28]\); - - \Rdata_RNO_0[6]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[6]\, Y => - \coarse_time_m[6]\); - - \r.coarse_time_load[19]\ : DFN1C0 - port map(D => \coarse_time_load_3[19]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[19]\); - - \Rdata_RNO_1[29]\ : OR2A - port map(A => \ctrl[29]\, B => \ctrl2\, Y => \ctrl_m[29]\); - - \r.coarse_time_load_RNO[4]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_123, Y => - \coarse_time_load_3[4]\); - - \r.coarse_time_load_RNO_0[2]\ : MX2C - port map(A => pwdata_0(2), B => \coarse_time_load[2]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_121); - - \r.ctrl[17]\ : DFN1E1C0 - port map(D => pwdata_15, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[17]\); - - \Rdata[21]\ : DFN1E1C0 - port map(D => \ctrl_1[21]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(21)); - - \r.next_commutation[10]\ : DFN1E1P0 - port map(D => pwdata_8, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[10]\); - - \Rdata_RNO_3[12]\ : OR2A - port map(A => \next_commutation[12]\, B => rdata62, Y => - \next_commutation_m[12]\); - - \Rdata_RNO[21]\ : OR3C - port map(A => \coarse_time_load_m[21]\, B => \ctrl_m[21]\, - C => \ctrl_1_0_iv_0[21]\, Y => \ctrl_1[21]\); - - \Rdata_RNO_0[17]\ : OR2A - port map(A => \coarse_time_load[17]\, B => rdata59_0, Y => - \coarse_time_load_m[17]\); - - \r.coarse_time_load_RNO_0[27]\ : MX2C - port map(A => pwdata_25, B => \coarse_time_load[27]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_146); - - un1_apbi_8_0 : OR2 - port map(A => paddr(7), B => \N_770\, Y => \un1_apbi_8_0\); - - \r.coarse_time_load_RNO[24]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_143, Y => - \coarse_time_load_3[24]\); - - \Rdata_RNO_0[23]\ : OR2A - port map(A => \coarse_time_load[23]\, B => \rdata59\, Y => - \coarse_time_load_m[23]\); - - \r.coarse_time_load_1_sqmuxa\ : OR2 - port map(A => \rdata59\, B => \un1_apbi_4\, Y => - coarse_time_load_1_sqmuxa_i); - - \Rdata_RNO_4[16]\ : OR2A - port map(A => \coarse_time_load[16]\, B => rdata59_0, Y => - \coarse_time_load_m[16]\); - - \Rdata_RNO_2[15]\ : AND2 - port map(A => \coarse_time_load_m[15]\, B => \ctrl_m[15]\, - Y => \ctrl_1_iv_2[15]\); - - \Rdata_RNO_0[14]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[14]\, Y => - \coarse_time_m[14]\); - - \Rdata_RNO_1[11]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[11]\, C => - \next_commutation_m[11]\, Y => \ctrl_1_iv_0[11]\); - - \Rdata[8]\ : DFN1E1C0 - port map(D => \ctrl_1[8]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(8)); - - \Rdata_RNO_3[23]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[23]\, Y => - \coarse_time_m[23]\); - - \Rdata_RNO_2[18]\ : OA1A - port map(A => \next_commutation[18]\, B => rdata62_0, C => - \coarse_time_m[18]\, Y => \ctrl_1_0_iv_0[18]\); - - \r.coarse_time_load_RNO[19]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_138, Y => - \coarse_time_load_3[19]\); - - \r.coarse_time_load[17]\ : DFN1C0 - port map(D => \coarse_time_load_3[17]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[17]\); - - \r.coarse_time_load_RNO_0[14]\ : MX2C - port map(A => pwdata_0(14), B => \coarse_time_load[14]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_133); - - \Rdata_RNO_3[16]\ : OR2A - port map(A => \next_commutation[16]\, B => rdata62, Y => - \next_commutation_m[16]\); - - \r.next_commutation[3]\ : DFN1E1P0 - port map(D => pwdata_1_2, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[3]\); - - \r.next_commutation[13]\ : DFN1E1P0 - port map(D => pwdata_11, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[13]\); - - \Rdata_RNO_4[5]\ : OR2A - port map(A => \coarse_time_load[5]\, B => rdata59_0, Y => - \coarse_time_load_m[5]\); - - \Rdata_RNO_2[2]\ : OA1A - port map(A => \ctrl[2]\, B => ctrl2_0, C => - \coarse_time_load_m[2]\, Y => \ctrl_1_iv_2[2]\); - - \r.coarse_time_load_RNO[30]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_149, Y => - \coarse_time_load_3[30]\); - - \Rdata_RNO_1[8]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[8]\, C => - \next_commutation_m[8]\, Y => \ctrl_1_iv_0[8]\); - - \r.coarse_time_load_RNO_0[30]\ : MX2C - port map(A => pwdata_28, B => \coarse_time_load[30]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_149); - - \Rdata_RNO_3[3]\ : OR2A - port map(A => \next_commutation[3]\, B => rdata62, Y => - \next_commutation_m[3]\); - - \Rdata[28]\ : DFN1E1C0 - port map(D => \ctrl_1[28]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(28)); - - \Rdata_RNO[16]\ : OR3C - port map(A => \coarse_time_m[16]\, B => \ctrl_1_iv_0[16]\, - C => \ctrl_1_iv_2[16]\, Y => \ctrl_1[16]\); - - \Rdata_RNO_2[5]\ : OA1A - port map(A => \ctrl[5]\, B => ctrl2_0, C => - \coarse_time_load_m[5]\, Y => \ctrl_1_iv_2[5]\); - - \r.coarse_time_load_RNO[28]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_147, Y => - \coarse_time_load_3[28]\); - - \Rdata_RNO[30]\ : OR3C - port map(A => \coarse_time_load_m[30]\, B => \ctrl_m[30]\, - C => \ctrl_1_0_iv_0[30]\, Y => \ctrl_1[30]\); - - \Rdata[29]\ : DFN1E1C0 - port map(D => \ctrl_1[29]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(29)); - - \r.ctrl[25]\ : DFN1E1C0 - port map(D => pwdata_23, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[25]\); - - \r.coarse_time_load_RNO[8]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_127, Y => - \coarse_time_load_3[8]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \Rdata_RNO_3[0]\ : OR2A - port map(A => \next_commutation[0]\, B => rdata62, Y => - \next_commutation_m[0]\); - - \Rdata_RNO_4[10]\ : OR2A - port map(A => \coarse_time_load[10]\, B => rdata59_0, Y => - \coarse_time_load_m[10]\); - - \Rdata_RNO_2[29]\ : OA1A - port map(A => \next_commutation[29]\, B => rdata62_0, C => - \coarse_time_m[29]\, Y => \ctrl_1_0_iv_0[29]\); - - \Rdata_RNO[15]\ : OR3C - port map(A => \coarse_time_m[15]\, B => \ctrl_1_iv_0[15]\, - C => \ctrl_1_iv_2[15]\, Y => \ctrl_1[15]\); - - \Rdata_RNO_4[4]\ : OR2A - port map(A => \coarse_time_load[4]\, B => rdata59_0, Y => - \coarse_time_load_m[4]\); - - \Rdata_RNO_5[8]\ : OR2A - port map(A => \ctrl[8]\, B => ctrl2_0, Y => \ctrl_m[8]\); - - \Rdata_RNO_4[1]\ : OR2A - port map(A => \coarse_time_load[1]\, B => \rdata59\, Y => - \coarse_time_load_m[1]\); - - \Rdata_RNO[9]\ : OR3C - port map(A => \coarse_time_m[9]\, B => \ctrl_1_iv_0[9]\, C - => \ctrl_1_iv_2[9]\, Y => \ctrl_1[9]\); - - \Rdata_RNO_2[11]\ : AND2 - port map(A => \coarse_time_load_m[11]\, B => \ctrl_m[11]\, - Y => \ctrl_1_iv_2[11]\); - - rdata78_0 : NOR2 - port map(A => \rdata62_3\, B => rdata60_4, Y => rdata60_0); - - \r.ctrl[22]\ : DFN1E1C0 - port map(D => pwdata_20, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[22]\); - - \r.coarse_time_load[15]\ : DFN1C0 - port map(D => \coarse_time_load_3[15]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[15]\); - - \Rdata_RNO_1[12]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[12]\, C => - \next_commutation_m[12]\, Y => \ctrl_1_iv_0[12]\); - - \Rdata_RNO_3[10]\ : OR2A - port map(A => \next_commutation[10]\, B => rdata62, Y => - \next_commutation_m[10]\); - - \Rdata_RNO_0[25]\ : OR2A - port map(A => \coarse_time_load[25]\, B => \rdata59\, Y => - \coarse_time_load_m[25]\); - - \r.coarse_time_load_RNO[11]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_130, Y => - \coarse_time_load_3[11]\); - - \r.coarse_time_load_RNO_0[20]\ : MX2C - port map(A => pwdata_18, B => \coarse_time_load[20]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_139); - - \r.coarse_time_load[0]\ : DFN1C0 - port map(D => \coarse_time_load_3[0]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[0]\); - - \r.next_commutation[5]\ : DFN1E1P0 - port map(D => pwdata_3, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[5]\); - - \r.next_commutation[21]\ : DFN1E1P0 - port map(D => pwdata_19, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[21]\); - - \Rdata_RNO_0[28]\ : OR2A - port map(A => \coarse_time_load[28]\, B => \rdata59\, Y => - \coarse_time_load_m[28]\); - - Rdata_0_sqmuxa : NOR2 - port map(A => pwrite, B => psel(15), Y => \Rdata_0_sqmuxa\); - - \r.next_commutation[25]\ : DFN1E1P0 - port map(D => pwdata_23, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[25]\); - - \Rdata_RNO_2[30]\ : OA1A - port map(A => \next_commutation[30]\, B => rdata62_0, C => - \coarse_time_m[30]\, Y => \ctrl_1_0_iv_0[30]\); - - \Rdata_RNO_3[25]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[25]\, Y => - \coarse_time_m[25]\); - - \Rdata_RNO_2[4]\ : AND2 - port map(A => \coarse_time_load_m[4]\, B => \ctrl_m[4]\, Y - => \ctrl_1_iv_2[4]\); - - \r.next_commutation[19]\ : DFN1E1P0 - port map(D => pwdata_17, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[19]\); - - \r.ctrl[21]\ : DFN1E1C0 - port map(D => pwdata_19, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[21]\); - - \r.coarse_time_load_RNO[9]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_128, Y => - \coarse_time_load_3[9]\); - - \r.coarse_time_load[28]\ : DFN1C0 - port map(D => \coarse_time_load_3[28]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[28]\); - - \Rdata_RNO_3[28]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[28]\, Y => - \coarse_time_m[28]\); - - \Rdata_RNO_1[16]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[16]\, C => - \next_commutation_m[16]\, Y => \ctrl_1_iv_0[16]\); - - \Rdata[11]\ : DFN1E1C0 - port map(D => \ctrl_1[11]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(11)); - - \r.ctrl[15]\ : DFN1E1C0 - port map(D => pwdata_13, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[15]\); - - \r.coarse_time_load_RNO_0[0]\ : MX2C - port map(A => pwdata_0(0), B => \coarse_time_load[0]\, S - => coarse_time_load_1_sqmuxa_i, Y => N_119); - - \r.coarse_time_load[24]\ : DFN1C0 - port map(D => \coarse_time_load_3[24]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[24]\); - - \Rdata_RNO[2]\ : OR3C - port map(A => \coarse_time_m[2]\, B => \ctrl_1_iv_0[2]\, C - => \ctrl_1_iv_2[2]\, Y => \ctrl_1[2]\); - - \r.next_commutation[31]\ : DFN1E1P0 - port map(D => pwdata_29, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[31]\); - - \r.coarse_time_load_RNO_0[12]\ : MX2C - port map(A => pwdata_0(12), B => \coarse_time_load[12]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_131); - - \r.ctrl3_0\ : OR2A - port map(A => rdata59_4, B => \rdata62_3\, Y => rdata59_0); - - \r.next_commutation[14]\ : DFN1E1P0 - port map(D => pwdata_12, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[14]\); - - \r.next_commutation[20]\ : DFN1E1P0 - port map(D => pwdata_18, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[20]\); - - \Rdata_RNO_4[6]\ : OR2A - port map(A => \coarse_time_load[6]\, B => rdata59_0, Y => - \coarse_time_load_m[6]\); - - \r.ctrl[2]\ : DFN1E1C0 - port map(D => pwdata_0_d0, CLK => lclk_c, CLR => rstn, E - => N_380, Q => \ctrl[2]\); - - \Rdata_RNO_4[14]\ : OR2A - port map(A => \coarse_time_load[14]\, B => rdata59_0, Y => - \coarse_time_load_m[14]\); - - Rdata_0_sqmuxa_0 : NOR2 - port map(A => pwrite, B => psel(15), Y => - \Rdata_0_sqmuxa_0\); - - \r.ctrl[12]\ : DFN1E1C0 - port map(D => pwdata_0(12), CLK => lclk_c, CLR => rstn, E - => N_380_0, Q => \ctrl[12]\); - - \Rdata_RNO_3[17]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[17]\, Y => - \coarse_time_m[17]\); - - \r.next_commutation[16]\ : DFN1E1P0 - port map(D => pwdata_14, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[16]\); - - \Rdata_RNO_1[0]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[0]\, C => - \next_commutation_m[0]\, Y => \ctrl_1_iv_0[0]\); - - \r.ctrl_0_sqmuxa\ : NOR2 - port map(A => \un1_apbi_4\, B => \ctrl2\, Y => N_380); - - \r.coarse_time_load_RNO_0[3]\ : MX2C - port map(A => pwdata_0(3), B => \coarse_time_load[3]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_122); - - \Rdata_RNO_2[12]\ : OA1A - port map(A => \ctrl[12]\, B => ctrl2_0, C => - \coarse_time_load_m[12]\, Y => \ctrl_1_iv_2[12]\); - - \r.next_commutation[12]\ : DFN1E1P0 - port map(D => pwdata_10, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[12]\); - - \r.coarse_time_load_RNO_0[4]\ : MX2C - port map(A => pwdata_0(4), B => \coarse_time_load[4]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_123); - - rdata79 : NOR3 - port map(A => rdata61_2, B => \rdata62_3\, C => un1_apbi_2, - Y => \rdata61\); - - previous_force_tick : DFN1C0 - port map(D => \force_tick\, CLK => lclk_c, CLR => rstn, Q - => \previous_force_tick\); - - \r.ctrl[7]\ : DFN1E1C0 - port map(D => pwdata_5, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[7]\); - - \r.coarse_time_load[26]\ : DFN1C0 - port map(D => \coarse_time_load_3[26]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[26]\); - - \Rdata_RNO_3[14]\ : OR2A - port map(A => \next_commutation[14]\, B => rdata62, Y => - \next_commutation_m[14]\); - - \Rdata_RNO_0[19]\ : OR2A - port map(A => \coarse_time_load[19]\, B => rdata59_0, Y => - \coarse_time_load_m[19]\); - - un1_apbi_7_2 : OR2 - port map(A => paddr(6), B => paddr(5), Y => \N_770\); - - \Rdata[1]\ : DFN1E1C0 - port map(D => \ctrl_1[1]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(1)); - - \r.next_commutation[30]\ : DFN1E1P0 - port map(D => pwdata_28, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[30]\); - - \r.coarse_time_load_RNO_0[29]\ : MX2C - port map(A => pwdata_27, B => \coarse_time_load[29]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_148); - - \Rdata_RNO_0[21]\ : OR2A - port map(A => \coarse_time_load[21]\, B => \rdata59\, Y => - \coarse_time_load_m[21]\); - - \r.coarse_time_load_RNO_0[28]\ : MX2C - port map(A => pwdata_26, B => \coarse_time_load[28]\, S => - coarse_time_load_1_sqmuxa_i_0, Y => N_147); - - \r.next_commutation[17]\ : DFN1E1P0 - port map(D => pwdata_15, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[17]\); - - \r.ctrl[11]\ : DFN1E1C0 - port map(D => pwdata_9, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[11]\); - - \r.next_commutation[9]\ : DFN1E1P0 - port map(D => pwdata_7, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[9]\); - - \Rdata_RNO_1[31]\ : OR2A - port map(A => \ctrl[31]\, B => \ctrl2\, Y => \ctrl_m[31]\); - - \r.coarse_time_load[7]\ : DFN1C0 - port map(D => \coarse_time_load_3[7]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[7]\); - - \Rdata_RNO_0[1]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[1]\, Y => - \coarse_time_m[1]\); - - \r.next_commutation_1_sqmuxa\ : NOR2 - port map(A => rdata62, B => \un1_apbi_4\, Y => - next_commutation_1_sqmuxa); - - \Rdata_RNO_3[21]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[21]\, Y => - \coarse_time_m[21]\); - - \Rdata[18]\ : DFN1E1C0 - port map(D => \ctrl_1[18]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(18)); - - \r.coarse_time_load_RNO[12]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_131, Y => - \coarse_time_load_3[12]\); - - \Rdata[30]\ : DFN1E1C0 - port map(D => \ctrl_1[30]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(30)); - - \r.next_commutation[23]\ : DFN1E1P0 - port map(D => pwdata_21, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[23]\); - - \Rdata_RNO_1[10]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[10]\, C => - \next_commutation_m[10]\, Y => \ctrl_1_iv_0[10]\); - - \Rdata[23]\ : DFN1E1C0 - port map(D => \ctrl_1[23]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(23)); - - soft_tick_1 : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick_1\); - - \r.coarse_time_load_RNO_0[17]\ : MX2C - port map(A => pwdata_15, B => \coarse_time_load[17]\, S => - coarse_time_load_1_sqmuxa_i_0, Y => N_136); - - \Rdata_RNO_2[16]\ : OA1A - port map(A => \ctrl[16]\, B => ctrl2_0, C => - \coarse_time_load_m[16]\, Y => \ctrl_1_iv_2[16]\); - - \Rdata_RNO[1]\ : OR3C - port map(A => \coarse_time_m[1]\, B => \ctrl_1_iv_0[1]\, C - => \ctrl_1_iv_2[1]\, Y => \ctrl_1[1]\); - - \Rdata[19]\ : DFN1E1C0 - port map(D => \ctrl_1[19]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(19)); - - \r.next_commutation[1]\ : DFN1E1P0 - port map(D => pwdata_1_0, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[1]\); - - soft_tick_2 : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick_2\); - - \r.ctrl[3]\ : DFN1E1C0 - port map(D => pwdata_1_2, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[3]\); - - \Rdata_RNO_3[8]\ : OR2A - port map(A => \next_commutation[8]\, B => rdata62, Y => - \next_commutation_m[8]\); - - \Rdata[0]\ : DFN1E1C0 - port map(D => \ctrl_1[0]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(0)); - - force_tick : DFN1C0 - port map(D => \ctrl[0]\, CLK => lclk_c, CLR => rstn, Q => - \force_tick\); - - \Rdata_RNO_3[6]\ : OR2A - port map(A => \next_commutation[6]\, B => rdata62, Y => - \next_commutation_m[6]\); - - \Rdata_RNO_0[3]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[3]\, Y => - \coarse_time_m[3]\); - - \r.coarse_time_load[8]\ : DFN1C0 - port map(D => \coarse_time_load_3[8]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[8]\); - - \Rdata_RNO_1[23]\ : OR2A - port map(A => \ctrl[23]\, B => \ctrl2\, Y => \ctrl_m[23]\); - - \Rdata_RNO[7]\ : OR3C - port map(A => \coarse_time_m[7]\, B => \ctrl_1_iv_0[7]\, C - => \ctrl_1_iv_2[7]\, Y => \ctrl_1[7]\); - - \r.coarse_time_load_RNO[23]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_142, Y => - \coarse_time_load_3[23]\); - - \r.coarse_time_load[22]\ : DFN1C0 - port map(D => \coarse_time_load_3[22]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[22]\); - - \Rdata[25]\ : DFN1E1C0 - port map(D => \ctrl_1[25]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(25)); - - \r.coarse_time_load_1_sqmuxa_0\ : OR2 - port map(A => rdata59_0, B => \un1_apbi_4_0\, Y => - coarse_time_load_1_sqmuxa_i_0); - - \Rdata_RNO_3[9]\ : OR2A - port map(A => \next_commutation[9]\, B => rdata62, Y => - \next_commutation_m[9]\); - - \Rdata_RNO_1[17]\ : OR2A - port map(A => \ctrl[17]\, B => \ctrl2\, Y => \ctrl_m[17]\); - - \Rdata_RNO_0[22]\ : OR2A - port map(A => \coarse_time_load[22]\, B => \rdata59\, Y => - \coarse_time_load_m[22]\); - - lfrtimemanagement0 : lfr_time_management - port map(pirq(13) => pirq(13), pirq(12) => pirq(12), - coarse_time_load(31) => \coarse_time_load[31]\, - coarse_time_load(30) => \coarse_time_load[30]\, - coarse_time_load(29) => \coarse_time_load[29]\, - coarse_time_load(28) => \coarse_time_load[28]\, - coarse_time_load(27) => \coarse_time_load[27]\, - coarse_time_load(26) => \coarse_time_load[26]\, - coarse_time_load(25) => \coarse_time_load[25]\, - coarse_time_load(24) => \coarse_time_load[24]\, - coarse_time_load(23) => \coarse_time_load[23]\, - coarse_time_load(22) => \coarse_time_load[22]\, - coarse_time_load(21) => \coarse_time_load[21]\, - coarse_time_load(20) => \coarse_time_load[20]\, - coarse_time_load(19) => \coarse_time_load[19]\, - coarse_time_load(18) => \coarse_time_load[18]\, - coarse_time_load(17) => \coarse_time_load[17]\, - coarse_time_load(16) => \coarse_time_load[16]\, - coarse_time_load(15) => \coarse_time_load[15]\, - coarse_time_load(14) => \coarse_time_load[14]\, - coarse_time_load(13) => \coarse_time_load[13]\, - coarse_time_load(12) => \coarse_time_load[12]\, - coarse_time_load(11) => \coarse_time_load[11]\, - coarse_time_load(10) => \coarse_time_load[10]\, - coarse_time_load(9) => \coarse_time_load[9]\, - coarse_time_load(8) => \coarse_time_load[8]\, - coarse_time_load(7) => \coarse_time_load[7]\, - coarse_time_load(6) => \coarse_time_load[6]\, - coarse_time_load(5) => \coarse_time_load[5]\, - coarse_time_load(4) => \coarse_time_load[4]\, - coarse_time_load(3) => \coarse_time_load[3]\, - coarse_time_load(2) => \coarse_time_load[2]\, - coarse_time_load(1) => \coarse_time_load[1]\, - coarse_time_load(0) => \coarse_time_load[0]\, - next_commutation(31) => \next_commutation[31]\, - next_commutation(30) => \next_commutation[30]\, - next_commutation(29) => \next_commutation[29]\, - next_commutation(28) => \next_commutation[28]\, - next_commutation(27) => \next_commutation[27]\, - next_commutation(26) => \next_commutation[26]\, - next_commutation(25) => \next_commutation[25]\, - next_commutation(24) => \next_commutation[24]\, - next_commutation(23) => \next_commutation[23]\, - next_commutation(22) => \next_commutation[22]\, - next_commutation(21) => \next_commutation[21]\, - next_commutation(20) => \next_commutation[20]\, - next_commutation(19) => \next_commutation[19]\, - next_commutation(18) => \next_commutation[18]\, - next_commutation(17) => \next_commutation[17]\, - next_commutation(16) => \next_commutation[16]\, - next_commutation(15) => \next_commutation[15]\, - next_commutation(14) => \next_commutation[14]\, - next_commutation(13) => \next_commutation[13]\, - next_commutation(12) => \next_commutation[12]\, - next_commutation(11) => \next_commutation[11]\, - next_commutation(10) => \next_commutation[10]\, - next_commutation(9) => \next_commutation[9]\, - next_commutation(8) => \next_commutation[8]\, - next_commutation(7) => \next_commutation[7]\, - next_commutation(6) => \next_commutation[6]\, - next_commutation(5) => \next_commutation[5]\, - next_commutation(4) => \next_commutation[4]\, - next_commutation(3) => \next_commutation[3]\, - next_commutation(2) => \next_commutation[2]\, - next_commutation(1) => \next_commutation[1]\, - next_commutation(0) => \next_commutation[0]\, - coarse_time(31) => \coarse_time[31]\, coarse_time(30) => - \coarse_time[30]\, coarse_time(29) => \coarse_time[29]\, - coarse_time(28) => \coarse_time[28]\, coarse_time(27) => - \coarse_time[27]\, coarse_time(26) => \coarse_time[26]\, - coarse_time(25) => \coarse_time[25]\, coarse_time(24) => - \coarse_time[24]\, coarse_time(23) => \coarse_time[23]\, - coarse_time(22) => \coarse_time[22]\, coarse_time(21) => - \coarse_time[21]\, coarse_time(20) => \coarse_time[20]\, - coarse_time(19) => \coarse_time[19]\, coarse_time(18) => - \coarse_time[18]\, coarse_time(17) => \coarse_time[17]\, - coarse_time(16) => \coarse_time[16]\, coarse_time(15) => - \coarse_time[15]\, coarse_time(14) => \coarse_time[14]\, - coarse_time(13) => \coarse_time[13]\, coarse_time(12) => - \coarse_time[12]\, coarse_time(11) => \coarse_time[11]\, - coarse_time(10) => \coarse_time[10]\, coarse_time(9) => - \coarse_time[9]\, coarse_time(8) => \coarse_time[8]\, - coarse_time(7) => \coarse_time[7]\, coarse_time(6) => - \coarse_time[6]\, coarse_time(5) => \coarse_time[5]\, - coarse_time(4) => \coarse_time[4]\, coarse_time(3) => - \coarse_time[3]\, coarse_time(2) => \coarse_time[2]\, - coarse_time(1) => \coarse_time[1]\, coarse_time(0) => - \coarse_time[0]\, coarse_time_i(0) => coarse_time_i(0), - fine_time(16) => \fine_time[16]\, fine_time(15) => - \fine_time[15]\, fine_time(14) => \fine_time[14]\, - fine_time(13) => \fine_time[13]\, fine_time(12) => - \fine_time[12]\, fine_time(11) => \fine_time[11]\, - fine_time(10) => \fine_time[10]\, fine_time(9) => - \fine_time[9]\, fine_time(8) => \fine_time[8]\, - fine_time(7) => \fine_time[7]\, fine_time(6) => - \fine_time[6]\, fine_time(5) => \fine_time[5]\, - fine_time(4) => \fine_time[4]\, fine_time(3) => - \fine_time[3]\, fine_time(2) => \fine_time[2]\, - fine_time(1) => \fine_time[1]\, fine_time(0) => - \fine_time[0]\, clk49_152MHz_c_0 => clk49_152MHz_c_0, - clk49_152MHz_c => clk49_152MHz_c, lclk_c => lclk_c, - soft_tick => \soft_tick\, rstn_i => rstn_i, soft_tick_3 - => \soft_tick_3\, soft_tick_2 => \soft_tick_2\, - soft_tick_1 => \soft_tick_1\, soft_tick_0 => - \soft_tick_0\, rstn => rstn); - - \Rdata_RNO[19]\ : OR3C - port map(A => \coarse_time_load_m[19]\, B => \ctrl_m[19]\, - C => \ctrl_1_0_iv_0[19]\, Y => \ctrl_1[19]\); - - \r.ctrl3\ : OR2A - port map(A => rdata59_4, B => \rdata62_3\, Y => \rdata59\); - - \Rdata_RNO[26]\ : OR3C - port map(A => \coarse_time_load_m[26]\, B => \ctrl_m[26]\, - C => \ctrl_1_0_iv_0[26]\, Y => \ctrl_1[26]\); - - \r.ctrl[5]\ : DFN1E1C0 - port map(D => pwdata_3, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[5]\); - - \r.coarse_time_load_RNO[10]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_129, Y => - \coarse_time_load_3[10]\); - - \Rdata_RNO_3[22]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[22]\, Y => - \coarse_time_m[22]\); - - \Rdata_RNO_2[10]\ : OA1A - port map(A => \ctrl[10]\, B => ctrl2_0, C => - \coarse_time_load_m[10]\, Y => \ctrl_1_iv_2[10]\); - - \Rdata_RNO_1[14]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[14]\, C => - \next_commutation_m[14]\, Y => \ctrl_1_iv_0[14]\); - - \Rdata_RNO[6]\ : OR3C - port map(A => \coarse_time_m[6]\, B => \ctrl_1_iv_0[6]\, C - => \ctrl_1_iv_2[6]\, Y => \ctrl_1[6]\); - - \Rdata[7]\ : DFN1E1C0 - port map(D => \ctrl_1[7]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(7)); - - \r.coarse_time_load_RNO_0[9]\ : MX2C - port map(A => pwdata_0(9), B => \coarse_time_load[9]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_128); - - \r.next_commutation[29]\ : DFN1E1P0 - port map(D => pwdata_27, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[29]\); - - \Rdata_RNO_5[15]\ : OR2A - port map(A => \ctrl[15]\, B => ctrl2_0, Y => \ctrl_m[15]\); - - \Rdata_RNO[13]\ : OR3C - port map(A => \coarse_time_m[13]\, B => \ctrl_1_iv_0[13]\, - C => \ctrl_1_iv_2[13]\, Y => \ctrl_1[13]\); - - \r.ctrl[20]\ : DFN1E1C0 - port map(D => pwdata_18, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[20]\); - - \r.coarse_time_load[29]\ : DFN1C0 - port map(D => \coarse_time_load_3[29]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[29]\); - - \Rdata_RNO[25]\ : OR3C - port map(A => \coarse_time_load_m[25]\, B => \ctrl_m[25]\, - C => \ctrl_1_0_iv_0[25]\, Y => \ctrl_1[25]\); - - \r.coarse_time_load[3]\ : DFN1C0 - port map(D => \coarse_time_load_3[3]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[3]\); - - \r.coarse_time_load[2]\ : DFN1C0 - port map(D => \coarse_time_load_3[2]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[2]\); - - \Rdata_RNO_0[9]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[9]\, Y => - \coarse_time_m[9]\); - - \Rdata_RNO_0[26]\ : OR2A - port map(A => \coarse_time_load[26]\, B => \rdata59\, Y => - \coarse_time_load_m[26]\); - - \Rdata_RNO_3[31]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[31]\, Y => - \coarse_time_m[31]\); - - \r.coarse_time_load_RNO[25]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_144, Y => - \coarse_time_load_3[25]\); - - \Rdata_RNO[10]\ : OR3C - port map(A => \coarse_time_m[10]\, B => \ctrl_1_iv_0[10]\, - C => \ctrl_1_iv_2[10]\, Y => \ctrl_1[10]\); - - \r.coarse_time_load_RNO_0[10]\ : MX2C - port map(A => pwdata_0(10), B => \coarse_time_load[10]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_129); - - \r.next_commutation[24]\ : DFN1E1P0 - port map(D => pwdata_22, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[24]\); - - \Rdata_RNO_3[26]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[26]\, Y => - \coarse_time_m[26]\); - - \r.next_commutation[4]\ : DFN1E1P0 - port map(D => pwdata_1_3, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[4]\); - - \Rdata_RNO[14]\ : OR3C - port map(A => \coarse_time_m[14]\, B => \ctrl_1_iv_0[14]\, - C => \ctrl_1_iv_2[14]\, Y => \ctrl_1[14]\); - - \r.next_commutation[26]\ : DFN1E1P0 - port map(D => pwdata_24, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[26]\); - - \r.ctrl[31]\ : DFN1E1C0 - port map(D => pwdata_29, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[31]\); - - \Rdata_RNO[17]\ : OR3C - port map(A => \coarse_time_load_m[17]\, B => \ctrl_m[17]\, - C => \ctrl_1_0_iv_0[17]\, Y => \ctrl_1[17]\); - - \Rdata_RNO_5[3]\ : OR2A - port map(A => \ctrl[3]\, B => ctrl2_0, Y => \ctrl_m[3]\); - - \r.next_commutation[22]\ : DFN1E1P0 - port map(D => pwdata_20, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[22]\); - - \r.coarse_time_load[27]\ : DFN1C0 - port map(D => \coarse_time_load_3[27]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[27]\); - - \r.coarse_time_load[1]\ : DFN1C0 - port map(D => \coarse_time_load_3[1]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[1]\); - - \Rdata_RNO_2[17]\ : OA1A - port map(A => \next_commutation[17]\, B => rdata62_0, C => - \coarse_time_m[17]\, Y => \ctrl_1_0_iv_0[17]\); - - \Rdata_RNO_0[31]\ : OR2A - port map(A => \coarse_time_load[31]\, B => \rdata59\, Y => - \coarse_time_load_m[31]\); - - \Rdata_RNO_2[3]\ : AND2 - port map(A => \coarse_time_load_m[3]\, B => \ctrl_m[3]\, Y - => \ctrl_1_iv_2[3]\); - - \r.coarse_time_load_RNO_0[1]\ : MX2C - port map(A => pwdata_0(1), B => \coarse_time_load[1]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_120); - - \Rdata_RNO_3[19]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[19]\, Y => - \coarse_time_m[19]\); - - \Rdata_RNO_2[23]\ : OA1A - port map(A => \next_commutation[23]\, B => rdata62_0, C => - \coarse_time_m[23]\, Y => \ctrl_1_0_iv_0[23]\); - - \Rdata_RNO_1[25]\ : OR2A - port map(A => \ctrl[25]\, B => \ctrl2\, Y => \ctrl_m[25]\); - - previous_force_tick_RNIKV47 : NOR2A - port map(A => \force_tick\, B => \previous_force_tick\, Y - => \previous_force_tick_RNIKV47\); - - \Rdata[13]\ : DFN1E1C0 - port map(D => \ctrl_1[13]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(13)); - - \r.next_commutation[27]\ : DFN1E1P0 - port map(D => pwdata_25, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[27]\); - - \Rdata_RNO[4]\ : OR3C - port map(A => \coarse_time_m[4]\, B => \ctrl_1_iv_0[4]\, C - => \ctrl_1_iv_2[4]\, Y => \ctrl_1[4]\); - - \Rdata_RNO_1[28]\ : OR2A - port map(A => \ctrl[28]\, B => \ctrl2\, Y => \ctrl_m[28]\); - - \Rdata_RNO_2[14]\ : AND2 - port map(A => \coarse_time_load_m[14]\, B => \ctrl_m[14]\, - Y => \ctrl_1_iv_2[14]\); - - \r.ctrl[10]\ : DFN1E1C0 - port map(D => pwdata_0(10), CLK => lclk_c, CLR => rstn, E - => N_380_0, Q => \ctrl[10]\); - - \r.coarse_time_load[10]\ : DFN1C0 - port map(D => \coarse_time_load_3[10]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[10]\); - - \Rdata_RNO[12]\ : OR3C - port map(A => \coarse_time_m[12]\, B => \ctrl_1_iv_0[12]\, - C => \ctrl_1_iv_2[12]\, Y => \ctrl_1[12]\); - - soft_tick_3 : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick_3\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity rstgen is - - port( rstgen_VCC : in std_logic; - rstraw_c : in std_logic; - lclk_c : in std_logic; - m26_m1_e : in std_logic; - rstoutl_RNIGJKSJO : out std_logic; - rstn_i : out std_logic; - rstn : out std_logic - ); - -end rstgen; - -architecture DEF_ARCH of rstgen is - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \rstoutl\, \rstn\, rstoutl_1, \r[2]_net_1\, - \r[4]_net_1\, \r[3]_net_1\, \r[0]_net_1\, \r[1]_net_1\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - rstn <= \rstn\; - - rstoutl_RNIQRB1_0 : INV - port map(A => \rstn\, Y => rstn_i); - - \rstoutl_RNIGJKSJO\ : OR2B - port map(A => m26_m1_e, B => \rstn\, Y => rstoutl_RNIGJKSJO); - - \r[2]\ : DFN1C0 - port map(D => \r[1]_net_1\, CLK => lclk_c, CLR => rstraw_c, - Q => \r[2]_net_1\); - - \r[0]\ : DFN1C0 - port map(D => rstgen_VCC, CLK => lclk_c, CLR => rstraw_c, Q - => \r[0]_net_1\); - - rstoutl_RNO : NOR3C - port map(A => \r[2]_net_1\, B => \r[4]_net_1\, C => - \r[3]_net_1\, Y => rstoutl_1); - - rstoutl : DFN1C0 - port map(D => rstoutl_1, CLK => lclk_c, CLR => rstraw_c, Q - => \rstoutl\); - - rstoutl_RNIQRB1 : CLKINT - port map(A => \rstoutl\, Y => \rstn\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \r[4]\ : DFN1C0 - port map(D => \r[3]_net_1\, CLK => lclk_c, CLR => rstraw_c, - Q => \r[4]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \r[3]\ : DFN1C0 - port map(D => \r[2]_net_1\, CLK => lclk_c, CLR => rstraw_c, - Q => \r[3]_net_1\); - - \r[1]\ : DFN1C0 - port map(D => \r[0]_net_1\, CLK => lclk_c, CLR => rstraw_c, - Q => \r[1]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mctrl is - - port( data_in : in std_logic_vector(31 downto 0); - hresp : out std_logic_vector(0 to 0); - address : out std_logic_vector(31 downto 28); - romsn_c : out std_logic_vector(1 downto 0); - ramoen_c : out std_logic_vector(3 downto 0); - hmbsel_1 : in std_logic_vector(0 to 0); - hburst_0 : in std_logic_vector(2 downto 0); - hmbsel : in std_logic_vector(0 to 0); - ramrws_1 : out std_logic; - ramwws : out std_logic_vector(1 downto 0); - pwdata_1_3 : in std_logic; - pwdata_1_0 : in std_logic; - pwdata_1_2 : in std_logic; - rwen_c : out std_logic_vector(3 downto 0); - iosn_1_8 : in std_logic; - iosn_1_0 : in std_logic; - ramsn_c : out std_logic_vector(3 downto 0); - rambanksz_0 : out std_logic; - rambanksz_1 : out std_logic; - rambanksz_3 : out std_logic; - paddr_2 : in std_logic_vector(2 to 2); - iows_3 : out std_logic; - iows_2 : out std_logic; - pwdata_23 : in std_logic; - pwdata_22 : in std_logic; - pwdata_0_d0 : in std_logic; - pwdata_7 : in std_logic; - pwdata_6 : in std_logic; - pwdata_5 : in std_logic; - pwdata_4 : in std_logic; - pwdata_1_d0 : in std_logic; - pwdata_18 : in std_logic; - pwdata_17 : in std_logic; - pwdata_16 : in std_logic; - pwdata_15 : in std_logic; - pwdata_20 : in std_logic; - pwdata_21 : in std_logic; - pwdata_14 : in std_logic; - pwdata_0_5 : in std_logic; - pwdata_0_7 : in std_logic; - pwdata_0_8 : in std_logic; - pwdata_0_9 : in std_logic; - pwdata_0_2 : in std_logic; - pwdata_0_1 : in std_logic; - pwdata_0_0 : in std_logic; - pwdata_0_6 : in std_logic; - pwdata_0_11 : in std_logic; - hsize : in std_logic_vector(1 downto 0); - romrws_1 : out std_logic; - romrws_3 : out std_logic; - romrws_2 : out std_logic; - hwdata_m_0_3 : in std_logic; - hwdata_m_0_2 : in std_logic; - hwdata_m_0_0 : in std_logic; - psel : in std_logic_vector(0 to 0); - romwidth : out std_logic_vector(1 downto 0); - iosn_100 : in std_logic; - iosn_99 : in std_logic; - address_c : out std_logic_vector(27 downto 0); - hwdata_m_8 : in std_logic; - hwdata_m_7 : in std_logic; - hwdata_m_5 : in std_logic; - hwdata_m_0_d0 : in std_logic; - hwdata_m_13 : in std_logic; - data : out std_logic_vector(31 downto 0); - haddr : in std_logic_vector(30 downto 0); - ramwidth : out std_logic_vector(1 downto 0); - htrans : in std_logic_vector(1 downto 0); - iosn_0 : in std_logic_vector(93 to 93); - hsel_i : in std_logic_vector(0 to 0); - romwws : out std_logic_vector(3 downto 0); - prdata_0 : out std_logic; - prdata_1 : out std_logic; - prdata_8 : out std_logic; - prdata_7 : out std_logic; - hrdata : out std_logic_vector(31 downto 0); - hwdata_4 : in std_logic; - hwdata_3 : in std_logic; - hwdata_8 : in std_logic; - hwdata_13 : in std_logic; - hwdata_24 : in std_logic; - hwdata_23 : in std_logic; - hwdata_22 : in std_logic; - hwdata_20 : in std_logic; - hwdata_10 : in std_logic; - hwdata_26 : in std_logic; - hwdata_9 : in std_logic; - hwdata_16 : in std_logic; - hwdata_17 : in std_logic; - hwdata_7 : in std_logic; - hwdata_30 : in std_logic; - hwdata_28 : in std_logic; - hwdata_5 : in std_logic; - hwdata_31 : in std_logic; - hwdata_1 : in std_logic; - hwdata_19 : in std_logic; - hwdata_29 : in std_logic; - hwdata_21 : in std_logic; - hwdata_18 : in std_logic; - hwdata_0 : in std_logic; - hwdata_6 : in std_logic; - hwdata_2 : in std_logic; - hwdata_27 : in std_logic; - hwdata_11 : in std_logic; - hwdata_25 : in std_logic; - bdrive_i : out std_logic_vector(3 downto 0); - paddr : in std_logic_vector(3 downto 2); - iosn_c : out std_logic; - lclk_c : in std_logic; - N_6455 : out std_logic; - N_5062 : out std_logic; - un6_ioen_NE_0 : in std_logic; - N_510 : out std_logic; - N_6459 : in std_logic; - N_5070 : out std_logic; - bexcen : out std_logic; - brdyen : out std_logic; - ioen : out std_logic; - writen_c : out std_logic; - hwrite_m_0_0 : in std_logic; - hwrite : in std_logic; - brmw_1 : out std_logic; - N_6550 : out std_logic; - oen_c : out std_logic; - rdata61_2 : in std_logic; - un1_apbi_0 : in std_logic; - brmw_i : out std_logic; - N_6377 : out std_logic; - rmw : out std_logic; - rstn : in std_logic; - read_c : out std_logic; - hready : out std_logic; - N_232_0 : in std_logic; - N_6455_0 : out std_logic - ); - -end mctrl; - -architecture DEF_ARCH of mctrl is - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal writedata_0_sqmuxa_0, \bstate[7]\, \bdrive[0]\, - N_36_0, ws, address_1_sqmuxa_i_a2_1, srhsel_0_sqmuxa, - \bdrive[1]\, \bdrive[2]\, \bdrive[3]\, N_185, N_111, - N_187, \address_RNI96NJ_5[0]\, \iowidth[0]\, \iowidth[1]\, - \iows[1]\, ws_0_sqmuxa, \bstate[5]\, \un1_wsnew_0_sqmuxa\, - \wsnew_0_sqmuxa\, \iows[0]\, \writedata_12_iv_0_0[25]\, - \ws_0_0_0[3]\, \ws_0_0_a2_0[3]\, N_6449, \ws_0_0_1[2]\, - \ws_0_0_a2_2_0[2]\, N_6457, N_6444, N_6458, N90_i, - ADD_4x4_fast_I13_Y_0_0, bstate_3, ready_0_0_o2_0, N_419, - ramoen_0_sqmuxa, ready_0_0_a2_0_1, ws_1_sqmuxa, - ready_0_0_a2_0_0, brmw, N_413, \iosn_1_iv_0_a2_0[1]\, - \iosn[1]\, \un1_romsn_0_sqmuxa_1_0[0]_net_1\, bstate16, - bstate_0_sqmuxa_1, bstate_0_sqmuxa_0, \hready\, - ramoen10_i_a2_1, hburst_i_0, \area[1]\, brmw_1_1, - \writedata_12_iv_i_2[24]\, N_440, \writedata[8]\, - \writedata_12_iv_i_1[24]\, N_190, \writedata_RNO_3[24]\, - N_193, \writedata_12_0_iv_0[23]\, \writedata[23]\, - N_123_i, \data_m[23]\, \writedata_12_0_iv_0_0[16]\, - N_5160, N_532, \writedata_12_iv_1[31]\, \writedata[15]\, - \writedata_12_iv_0[31]\, \writedata[31]\, - \writedata_m_0[23]\, \writedata_12_0_iv_0[20]\, - \writedata_m[4]\, \writedata_12_iv_0[28]\, \writedata[4]\, - N_46_i_0, \writedata_m[28]\, \writedata_12_iv_0[30]\, - \writedata[6]\, \writedata_m[30]\, - \writedata_12_iv_0_1[27]\, \writedata_12_iv_0_0[27]\, - N_182, \writedata_12_iv_0[26]\, \writedata_m[10]\, - wrn_5_sqmuxa_s6_0_1, N_394, wrn35, wrn_5_sqmuxa_s6_0_0, - N_126_i, N_6547, wrn_4_sqmuxa_s5_0_1, wrn_4_sqmuxa_s5_0_0, - N_117, wrn_3_sqmuxa_s4_0_1, wrn_3_sqmuxa_s4_0_0, wrn8, - wrn_2_sqmuxa_s3_0_1, wrn_2_sqmuxa_s3_0_0, N_425, - \writedata_12_iv_0_2[25]\, N_186, N_188, - \writedata_0_iv_1[20]\, \hrdata_m[20]\, \hrdata_m_0[20]\, - \writedata_12_0_iv_i_i_0[22]\, N_632, - \writedata_1_iv_0[0]\, \hrdata_m[0]\, - \writedata_1_iv_0[7]\, N_5112, - \writedata_12_0_iv_i_1[18]\, N_16464_tz, N_106, - \writedata_12_0_iv_i_0[18]\, \writedata_RNO_3[18]\, N_160, - \writedata_12_iv_0_0_1[29]\, writedata_1_sqmuxa, N_555, - \writedata_12_iv_0_0_0[29]\, - \writedata_12_iv_0_0_a2_0[29]\, N_552, - wrn_2_sqmuxa_s3_0_6_1, \busw[1]\, N_424, - \writedata_m_1[19]\, N_439, \writedata_m_0[19]\, - \writedata_0_iv_i_a2_0[19]\, \writedata_1_iv_i_0[2]\, - \writedata_1_iv_i_a2_2_0[2]\, N_150, - \writedata_12_0_iv_0_0[17]\, N_514, \writedata_4_m_0[20]\, - \brmw_i\, \writedata_m_0_0[18]\, - \writedata_12_0_iv_i_a3_i_0[21]\, N_539, - \writedata_1_iv_0[28]\, N_6555_i_0, N_38_i, - \writedata_1_iv_0[30]\, \writedata_1_iv_0[26]\, - \writedata_1_iv_0[31]\, \ws_3_iv_3[1]\, \ws_3_iv_1[1]\, - \ramrws_m[1]\, \iows_m[1]\, \ramwws_m[1]\, \romwws_m[1]\, - \romrws_m[1]\, \ws[3]\, \A_i[0]\, \ws_3_iv_3[0]\, - \ws_3_iv_1[0]\, \ramrws_m[0]\, \iows_m[0]\, \ramwws_m[0]\, - \romwws_m[0]\, \romrws_m[0]\, bexcen_0_sqmuxa_0_a2_0, - ADD_4x4_fast_I12_Y_0_0, \ws[2]\, ADD_4x4_fast_I11_Y_0_0, - \ws[1]\, \writedata_12_0_iv_i_a3_i_2_0_tz_0[21]\, N_6563, - wrn_6_sqmuxa_0_i_1, \size[0]\, \size[1]\, - \writedata_1_iv_0_a2_1_0[3]\, N_108, N_122_i_i_o2_1, - \busw[0]\, N_122_i_i_o2_0, \address_c[1]\, - \writedata_12_0_iv_i_a2_4_0[18]\, bstate_2_sqmuxa_1_0, - srhsel, \read_c\, ws_1, ws_0, \ws[0]\, N_155, - \writedata_12[30]\, \writedata_m[14]\, - \writedata_m_0[22]\, \writedata_12[28]\, - \writedata_m[12]\, \writedata_m_0[20]\, \romwidth_m[1]\, - \ws_RNO[2]\, N_6445, N_6443, bexcen_0_sqmuxa, - \writedata_m_0[18]\, N_448, \writedata_12[31]\, - \writedata[7]\, \writedata_12[26]\, \writedata_m[26]\, - \writedata_4_m[20]\, \writedata_4[20]\, \writedata[20]\, - \wrn_RNO[0]\, \wrn_90[0]\, \wrn_RNO[1]\, \wrn_90[1]\, - \wrn_RNO[2]\, \wrn_90[2]\, \wrn_RNO[3]\, \wrn_90[3]\, - wrn_1_sqmuxa_s2_0_3, un1_wrn35_1, wrn_5_sqmuxa_s6_0_6, - writen_0_sqmuxa_1_0, N_45, N_149, N_148, N_671, N_649, - N_6554, \writedata_12_0_iv_i_a3_i_2_0[21]\, N_543, - \writedata_12[16]\, N_530, N_531, N_6549, N_438, N_661, - N_6568_i_0, N_6565, N_6567_i_0, N_634, \writedata[12]\, - \hrdata_m[12]\, N_152, \writedata_12[23]\, - \writedata_10[7]\, \busw_1[1]\, \iowidth_m[1]\, - \ramwidth_m[1]\, \writedata[14]\, \hrdata_m[14]\, N_6450, - \ws_RNO[3]\, N_6448, N_538, bstate_0_sqmuxa, N_195, - bstate_2_sqmuxa, N_412, \hburst[1]\, \hburst[0]\, - \hburst[2]\, ramoen_0_sqmuxa_1, un1_iosn, bstate_4, - oen_1_sqmuxa, N_451, N_431, \oen_c\, N_297, N_619, N_618, - N_446, N_295, N_616, N_617, \iosn_i_m[1]\, - iosn_1_sqmuxa_1, bstate_5_1, \ws_1_sqmuxa_2[1]\, N_4, - N_16, \writedata_m[19]\, N_82_i_0, \writedata[0]\, - \writedata_12[25]\, \writedata[1]\, \writedata_12[27]\, - N_183, N_184, N_308, N_630, N_515, \writedata_12[29]\, - N_554, \writedata_12[17]\, N_511, N_513, - \writedata_12[20]\, \hrdata_m[15]\, \writedata_12[19]\, - \data_m[19]\, \writedata_m[3]\, \N_6550\, - \writedata_10[0]\, N_62_i_0, N_163, \busw_1[0]\, - \iowidth_m[0]\, \romwidth_m[0]\, \ramwidth_m[0]\, - hresp2_i_0, \area[0]\, romwrite, \ramsn_1[3]\, - \adec_2[0]\, \adec_2[1]\, \ramsn_1[2]\, \ramsn_1[1]\, - \ramsn_1[0]\, N_420, read_8_iv_0_tz, N_669, - un1_rws_0_sqmuxa, un18_srhsel, hwrite_0, iosn_0_sqmuxa_1, - \writedata[11]\, \address_RNI96NJ_3[0]\, N_5425, - iosn_0_sqmuxa, N_280, N_5525, N_5526, N_5527, N_5528, - N_5503, \romwws[2]\, N_5505, \romrws[0]\, N_5506, N_5507, - \romrws[2]\, N_5509, N_5510, N_5511, \hwdata_m[28]\, - \hwdata_m[30]\, N_6564, \rambanksz[2]\, N_5082, N_5084, - N_5107, N_5088, N_5106, N_5091, N_5097, N_5098, N_5094, - N_5100, N_5101, N_5103, \rambanksz[3]\, \rambanksz[1]\, - N_5108, N_5109, N_5110, \rambanksz[0]\, \ramwidth[1]\, - rmw_1_sqmuxa, rws_1_sqmuxa, N_5085, N_5086, N_5176, - ramoen_1_sqmuxa_1, N_5177, N_5179, \ramoen_1[0]\, - ramoen_2_sqmuxa, \ramoen_1[1]\, \ramoen_1[3]\, - \romrws_RNO[2]\, \romwws_RNO[2]\, \hrdata[7]\, - \hrdata[2]\, N_199, \writedata[9]\, N_517, \address_c[0]\, - \hwdata_m[26]\, \writedata[10]\, N_6385, N_112, - \romwidth_1[1]\, writen_RNO, \hrdata[20]\, N_435, N_5194, - N_5195, N_5196, N_5197, N_5200, N_5201, N_5202, N_5203, - \rmw\, \area[2]\, N_633, N_558, N_559, N_564, N_565, - N_566, N_396, N_449, N_635, N_636, N_6539, bexcen_RNO, - brdyen_RNO, ioen_RNO, romwrite_RNO, \N_6377\, N_610, - N_286, N_288, N_290, N_292, \brdyen\, rws_0_sqmuxa, - \iows[2]\, N_560, \romwws_RNO[3]\, N_5504, - \romrws_RNO[3]\, N_5508, \romrws[3]\, \romwws[3]\, - romsn_1_sqmuxa, N_442, \bstate[4]\, \bstate[6]\, - \hresp_6[0]\, N_500, \bstate_RNO[6]\, N_36, ready10, - \ioen\, N_653, writedata_0_sqmuxa, read_RNO_0, - \romwws_RNO[1]\, N_5502, un1_ahbsi_1, \ramsn_1_0[3]\, - bstate16_1, ramoen_2_sqmuxa_1, \ramsn_1_0[1]\, N_5178, - \ramoen_1[2]\, \iosn_1_iv[1]\, \ramsn_1_0[2]\, - \ramsn_1_0[0]\, iosn_1_sqmuxa, bstate_2_sqmuxa_1, - iosn_1_sqmuxa_1_0, \bstate_RNO[7]\, N_5512, \iows[3]\, - N_5518, N_14, N_563, N_567, \ramrws_RNO[0]\, N_5519, - N_562, N_5517, N_561, N_5520, \ws_RNO[1]\, - \ws_1_sqmuxa_2_m[2]\, \romwws[1]\, \ramwws[1]\, - \romrws[1]\, \romwws_RNO[0]\, N_5501, \ws_RNO[0]\, - \ws_1_sqmuxa_2_m[3]\, \ramrws[0]\, \ramrws[1]\, - \ramwws[0]\, \romwws[0]\, \writedata[3]\, \hrdata[0]\, - N_6410, N_6411, \writedata[13]\, romsn_0_sqmuxa_1, N_506, - N_507, N_549, N_550, \writedata[5]\, \romsn_1[0]\, - \romsn_1[1]\, N_80, srhsel_RNO_0, ready_RNO, \brmw_1\, - \writen_c\, \bexcen\, \rwen_c[0]\, \rwen_c[1]\, - \rwen_c[2]\, \rwen_c[3]\, \ramwidth[0]\, \ramsn_c[0]\, - \ramsn_c[1]\, \ramsn_c[2]\, \ramsn_c[3]\, \data[16]\, - \data[17]\, \data[18]\, \data[19]\, \data[20]\, - \data[21]\, \data[22]\, \data[23]\, \romwidth[0]\, - \romwidth[1]\, \hrdata[1]\, \hrdata[3]\, \hrdata[4]\, - \hrdata[5]\, \hrdata[6]\, \hrdata[8]\, \hrdata[9]\, - \hrdata[10]\, \hrdata[11]\, \hrdata[12]\, \hrdata[13]\, - \hrdata[14]\, \hrdata[15]\, \hrdata[16]\, \hrdata[17]\, - \hrdata[18]\, \hrdata[19]\, \hrdata[21]\, \hrdata[22]\, - \hrdata[23]\, \hrdata[24]\, \hrdata[25]\, \hrdata[26]\, - \hrdata[27]\, \hrdata[28]\, \hrdata[29]\, \hrdata[30]\, - \hrdata[31]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - ramrws_1 <= \ramrws[1]\; - ramwws(1) <= \ramwws[1]\; - ramwws(0) <= \ramwws[0]\; - rwen_c(3) <= \rwen_c[3]\; - rwen_c(2) <= \rwen_c[2]\; - rwen_c(1) <= \rwen_c[1]\; - rwen_c(0) <= \rwen_c[0]\; - ramsn_c(3) <= \ramsn_c[3]\; - ramsn_c(2) <= \ramsn_c[2]\; - ramsn_c(1) <= \ramsn_c[1]\; - ramsn_c(0) <= \ramsn_c[0]\; - rambanksz_0 <= \rambanksz[0]\; - rambanksz_1 <= \rambanksz[1]\; - rambanksz_3 <= \rambanksz[3]\; - iows_3 <= \iows[3]\; - iows_2 <= \iows[2]\; - romrws_1 <= \romrws[1]\; - romrws_3 <= \romrws[3]\; - romrws_2 <= \romrws[2]\; - romwidth(1) <= \romwidth[1]\; - romwidth(0) <= \romwidth[0]\; - address_c(1) <= \address_c[1]\; - address_c(0) <= \address_c[0]\; - data(23) <= \data[23]\; - data(22) <= \data[22]\; - data(21) <= \data[21]\; - data(20) <= \data[20]\; - data(19) <= \data[19]\; - data(18) <= \data[18]\; - data(17) <= \data[17]\; - data(16) <= \data[16]\; - ramwidth(1) <= \ramwidth[1]\; - ramwidth(0) <= \ramwidth[0]\; - romwws(3) <= \romwws[3]\; - romwws(2) <= \romwws[2]\; - romwws(1) <= \romwws[1]\; - romwws(0) <= \romwws[0]\; - hrdata(31) <= \hrdata[31]\; - hrdata(30) <= \hrdata[30]\; - hrdata(29) <= \hrdata[29]\; - hrdata(28) <= \hrdata[28]\; - hrdata(27) <= \hrdata[27]\; - hrdata(26) <= \hrdata[26]\; - hrdata(25) <= \hrdata[25]\; - hrdata(24) <= \hrdata[24]\; - hrdata(23) <= \hrdata[23]\; - hrdata(22) <= \hrdata[22]\; - hrdata(21) <= \hrdata[21]\; - hrdata(20) <= \hrdata[20]\; - hrdata(19) <= \hrdata[19]\; - hrdata(18) <= \hrdata[18]\; - hrdata(17) <= \hrdata[17]\; - hrdata(16) <= \hrdata[16]\; - hrdata(15) <= \hrdata[15]\; - hrdata(14) <= \hrdata[14]\; - hrdata(13) <= \hrdata[13]\; - hrdata(12) <= \hrdata[12]\; - hrdata(11) <= \hrdata[11]\; - hrdata(10) <= \hrdata[10]\; - hrdata(9) <= \hrdata[9]\; - hrdata(8) <= \hrdata[8]\; - hrdata(7) <= \hrdata[7]\; - hrdata(6) <= \hrdata[6]\; - hrdata(5) <= \hrdata[5]\; - hrdata(4) <= \hrdata[4]\; - hrdata(3) <= \hrdata[3]\; - hrdata(2) <= \hrdata[2]\; - hrdata(1) <= \hrdata[1]\; - hrdata(0) <= \hrdata[0]\; - bexcen <= \bexcen\; - brdyen <= \brdyen\; - ioen <= \ioen\; - writen_c <= \writen_c\; - brmw_1 <= \brmw_1\; - N_6550 <= \N_6550\; - oen_c <= \oen_c\; - brmw_i <= \brmw_i\; - N_6377 <= \N_6377\; - rmw <= \rmw\; - read_c <= \read_c\; - hready <= \hready\; - - \v.mcfg1.bexcen_0_sqmuxa_0_a2_0\ : NOR2 - port map(A => un1_apbi_0, B => rdata61_2, Y => - bexcen_0_sqmuxa_0_a2_0); - - \r.ws_RNO[2]\ : OR3C - port map(A => N_6445, B => N_6443, C => \ws_0_0_1[2]\, Y - => \ws_RNO[2]\); - - \r.writedata_RNO_3[26]\ : OAI1 - port map(A => N_6555_i_0, B => N_38_i, C => \hrdata[26]\, Y - => \writedata_1_iv_0[26]\); - - \r.address[23]\ : DFN1E1 - port map(D => haddr(23), CLK => lclk_c, E => N_36_0, Q => - address_c(23)); - - \r.mcfg1.romwidth[1]\ : DFN1E0 - port map(D => \romwidth_1[1]\, CLK => lclk_c, E => N_560, Q - => \romwidth[1]\); - - \r.mcfg1.romrws_RNO[1]\ : OR2A - port map(A => rstn, B => N_5506, Y => N_559); - - \r.data[26]\ : DFN1 - port map(D => data_in(26), CLK => lclk_c, Q => \hrdata[26]\); - - \r.writedata_RNO_4[2]\ : NOR2 - port map(A => \hrdata[2]\, B => N_5112, Y => N_150); - - \r.wrn_RNO_4[0]\ : OR2 - port map(A => N_425, B => N_6547, Y => wrn_2_sqmuxa_s3_0_0); - - \r.ramoen_RNO[0]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => ramoen_2_sqmuxa, C => - N_5176, Y => \ramoen_1[0]\); - - \r.writedata_RNO_2[25]\ : OR2A - port map(A => hwdata_9, B => N_440, Y => N_186); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I8_Y_0\ : NOR3 - port map(A => N_4, B => N_16, C => N_14, Y => N90_i); - - \r.wrn_RNO_0[0]\ : MX2C - port map(A => N_5194, B => N_5200, S => writen_0_sqmuxa_1_0, - Y => \wrn_90[0]\); - - \r.writedata_RNO_4[26]\ : OR2B - port map(A => hwdata_26, B => \address_RNI96NJ_5[0]\, Y => - \hwdata_m[26]\); - - \apbo.prdata_10_0_a2_0\ : OR2A - port map(A => paddr(2), B => paddr(3), Y => N_6455); - - \r.mcfg1.iows_RNO[0]\ : NOR2B - port map(A => rstn, B => N_5509, Y => N_564); - - \r.mcfg1.romwws[1]\ : DFN1 - port map(D => \romwws_RNO[1]\, CLK => lclk_c, Q => - \romwws[1]\); - - \r.busw_RNO_0[0]\ : OR2B - port map(A => \iowidth[0]\, B => iosn_1_8, Y => - \iowidth_m[0]\); - - \r.wrn_RNO[3]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => \wrn_90[3]\, C => rstn, - Y => \wrn_RNO[3]\); - - \r.ramoen_RNO_0[2]\ : MX2C - port map(A => \ramsn_1[2]\, B => \ramsn_c[2]\, S => - un1_iosn, Y => N_5178); - - \r.brmw_RNIPQ7A1\ : OR2 - port map(A => \brmw_i\, B => N_439, Y => N_448); - - \r.ws_RNO_0[0]\ : NOR3C - port map(A => \ws_3_iv_1[0]\, B => \ramrws_m[0]\, C => - \iows_m[0]\, Y => \ws_3_iv_3[0]\); - - \r.writedata[31]\ : DFN1E1 - port map(D => \writedata_12[31]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(31)); - - \r.romsn[0]\ : DFN1E0P0 - port map(D => \romsn_1[0]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => romsn_c(0)); - - \r.ws_RNO_5[0]\ : OR3A - port map(A => \romwws[0]\, B => N_6458, C => rws_1_sqmuxa, - Y => \romwws_m[0]\); - - \v.ramoen_0_sqmuxa\ : OR2B - port map(A => iosn_1_0, B => bstate16, Y => ramoen_0_sqmuxa); - - \r.ramsn[2]\ : DFN1E0P0 - port map(D => \ramsn_1_0[2]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => \ramsn_c[2]\); - - \r.data[1]\ : DFN1 - port map(D => data_in(1), CLK => lclk_c, Q => \hrdata[1]\); - - \un1_v.ws_1_sqmuxa_2_m[3]\ : XAI1A - port map(A => \ws[0]\, B => \A_i[0]\, C => bstate_3, Y => - \ws_1_sqmuxa_2_m[3]\); - - \r.writedata_RNO_0[24]\ : OA1 - port map(A => N_440, B => \writedata[8]\, C => - \writedata_12_iv_i_1[24]\, Y => \writedata_12_iv_i_2[24]\); - - \r.bstate_RNI8E2SK1[6]\ : NOR3A - port map(A => ramoen_0_sqmuxa, B => N_419, C => N_438, Y - => N_6567_i_0); - - \r.size[0]\ : DFN1E1 - port map(D => hsize(0), CLK => lclk_c, E => un1_ahbsi_1, Q - => \size[0]\); - - \r.mcfg2.rambanksz_RNI4PTI71[3]\ : MX2 - port map(A => haddr(17), B => haddr(25), S => - \rambanksz[3]\, Y => N_5107); - - \r.writedata_RNO_1[16]\ : AO1B - port map(A => N_669, B => N_420, C => hwdata_16, Y => N_530); - - \r.mcfg1.romwws_RNO_0[3]\ : MX2 - port map(A => \romwws[3]\, B => pwdata_0_7, S => - bexcen_0_sqmuxa, Y => N_5504); - - \r.wrn_RNO_0[2]\ : MX2C - port map(A => N_5196, B => N_5202, S => writen_0_sqmuxa_1_0, - Y => \wrn_90[2]\); - - \r.bdrive_RNITBR7[1]\ : INV - port map(A => \bdrive[1]\, Y => bdrive_i(1)); - - \r.area_RNI4DTB1[0]\ : OA1C - port map(A => N_412, B => N_653, C => N_424, Y => N_6565); - - \r.mcfg1.brdyen_RNII5OD\ : NOR2B - port map(A => \brdyen\, B => \area[1]\, Y => N_413); - - \r.busw_RNO_1[0]\ : OR3A - port map(A => \romwidth[0]\, B => hsel_i(0), C => - un6_ioen_NE_0, Y => \romwidth_m[0]\); - - \r.area_RNI2L73O[1]\ : NOR3B - port map(A => hburst_i_0, B => htrans(0), C => \area[1]\, Y - => ramoen10_i_a2_1); - - \r.mcfg1.romrws_RNO[3]\ : OR2A - port map(A => rstn, B => N_5508, Y => \romrws_RNO[3]\); - - \r.area_RNISN3H[0]\ : OA1C - port map(A => \area[0]\, B => romwrite, C => \read_c\, Y - => hresp2_i_0); - - \r.bdrive_RNO[0]\ : OA1C - port map(A => N_6568_i_0, B => \bdrive[0]\, C => N_6567_i_0, - Y => N_286); - - \r.srhsel_RNI5PCD\ : OR2B - port map(A => srhsel, B => \bstate[7]\, Y => N_424); - - \r.mcfg1.romrws_RNO[0]\ : OR2A - port map(A => rstn, B => N_5505, Y => N_558); - - \r.writedata_RNO_2[24]\ : OR2A - port map(A => N_111, B => hwdata_24, Y => N_190); - - \r.writen_RNO\ : OR2A - port map(A => rstn, B => N_5425, Y => writen_RNO); - - \r.wrn_RNO_0[3]\ : MX2C - port map(A => N_5197, B => N_5203, S => writen_0_sqmuxa_1_0, - Y => \wrn_90[3]\); - - \r.srhsel_RNIR3LD1\ : AOI1B - port map(A => bstate_2_sqmuxa, B => srhsel, C => - \bstate[7]\, Y => bstate_2_sqmuxa_1); - - \r.mcfg2.rambanksz_RNIMHVL71[3]\ : MX2 - port map(A => haddr(13), B => haddr(21), S => - \rambanksz[3]\, Y => N_5082); - - \r.writedata_RNO_3[27]\ : AOI1B - port map(A => hwdata_27, B => N_111, C => N_182, Y => - \writedata_12_iv_0_0[27]\); - - \r.mcfg1.iows_RNO[2]\ : NOR2B - port map(A => rstn, B => N_5511, Y => N_566); - - \r.writedata_RNO[31]\ : AO1B - port map(A => \writedata[7]\, B => N_46_i_0, C => - \writedata_12_iv_1[31]\, Y => \writedata_12[31]\); - - \r.ws_RNO_1[2]\ : OR3C - port map(A => \ws_1_sqmuxa_2[1]\, B => bstate_3, C => rstn, - Y => N_6443); - - \r.size[1]\ : DFN1E1 - port map(D => hsize(1), CLK => lclk_c, E => un1_ahbsi_1, Q - => \size[1]\); - - \r.writedata_RNO_4[27]\ : OR2A - port map(A => \hrdata[27]\, B => \address_RNI96NJ_5[0]\, Y - => N_182); - - \r.address_RNITD6J[0]\ : OR2A - port map(A => N_394, B => \address_c[0]\, Y => N_108); - - \r.data[23]\ : DFN1 - port map(D => data_in(23), CLK => lclk_c, Q => \hrdata[23]\); - - \r.mcfg2.ramwidth_RNIM82O32[1]\ : NOR3B - port map(A => hwrite, B => brmw_1_1, C => hsize(1), Y => - \brmw_1\); - - \r.wrn_RNO_0[1]\ : MX2C - port map(A => N_5195, B => N_5201, S => writen_0_sqmuxa_1_0, - Y => \wrn_90[1]\); - - \r.mcfg1.bexcen_RNO\ : NOR2B - port map(A => rstn, B => N_5528, Y => bexcen_RNO); - - \r.mcfg2.ramwidth[1]\ : DFN1E1 - port map(D => pwdata_0_d0, CLK => lclk_c, E => rmw_1_sqmuxa, - Q => \ramwidth[1]\); - - \r.brmw_RNIF8931\ : NOR2A - port map(A => brmw, B => N_439, Y => N_449); - - \r.writedata[8]\ : DFN1E1 - port map(D => \writedata[8]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(8)); - - \r.writedata[0]\ : DFN1E1 - port map(D => \writedata[0]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(0)); - - \r.bdrive_RNO[3]\ : OA1C - port map(A => N_6568_i_0, B => \bdrive[3]\, C => N_6567_i_0, - Y => N_292); - - \r.writedata_RNO_1[17]\ : OR2A - port map(A => \hrdata[17]\, B => N_448, Y => N_513); - - \un1_romsn_0_sqmuxa_1_0[0]\ : OR2A - port map(A => iosn_0(93), B => bstate16, Y => - \un1_romsn_0_sqmuxa_1_0[0]_net_1\); - - \r.data_RNIFM1E3[14]\ : OR3 - port map(A => hwdata_m_7, B => \hrdata_m[14]\, C => - hwdata_m_0_2, Y => \writedata[14]\); - - \r.data[28]\ : DFN1 - port map(D => data_in(28), CLK => lclk_c, Q => \hrdata[28]\); - - \r.writedata[26]\ : DFN1E1 - port map(D => \writedata_12[26]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(26)); - - \r.mcfg2.ramrws_RNO_0[0]\ : MX2 - port map(A => \ramrws[0]\, B => pwdata_0_0, S => - rmw_1_sqmuxa, Y => N_5519); - - \r.data[8]\ : DFN1 - port map(D => data_in(8), CLK => lclk_c, Q => \hrdata[8]\); - - \r.writedata_RNO_0[22]\ : AO1A - port map(A => N_440, B => hwdata_6, C => N_632, Y => - \writedata_12_0_iv_i_i_0[22]\); - - \r.mcfg1.iows_RNO_0[3]\ : MX2 - port map(A => \iows[3]\, B => pwdata_18, S => - bexcen_0_sqmuxa, Y => N_5512); - - \r.writedata[23]\ : DFN1E1 - port map(D => \writedata_12[23]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[23]\); - - \r.wrn_RNO_4[3]\ : OR2 - port map(A => N_126_i, B => N_6547, Y => - wrn_5_sqmuxa_s6_0_0); - - \r.address[14]\ : DFN1E1 - port map(D => haddr(14), CLK => lclk_c, E => N_36_0, Q => - address_c(14)); - - \r.mcfg2.ramrws_RNO[0]\ : NOR2B - port map(A => rstn, B => N_5519, Y => \ramrws_RNO[0]\); - - \r.writedata_RNO_3[29]\ : OR2B - port map(A => N_46_i_0, B => hwdata_5, Y => N_555); - - \r.writedata[7]\ : DFN1E1 - port map(D => \writedata[7]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(7)); - - \r.hwrite\ : DFN1E1 - port map(D => hwrite, CLK => lclk_c, E => un1_ahbsi_1, Q - => hwrite_0); - - \r.ws_RNIVJ8E[3]\ : NOR2 - port map(A => \ws[3]\, B => \ws[0]\, Y => ws_0); - - \r.data_RNIR5AH1[4]\ : OR2B - port map(A => \hrdata[4]\, B => N_671, Y => N_550); - - \r.bdrive_RNISBR7[0]\ : INV - port map(A => \bdrive[0]\, Y => bdrive_i(0)); - - \r.writedata_RNO[25]\ : AO1B - port map(A => \writedata[1]\, B => N_46_i_0, C => - \writedata_12_iv_0_2[25]\, Y => \writedata_12[25]\); - - \r.busw_RNO[0]\ : OR3C - port map(A => \iowidth_m[0]\, B => \romwidth_m[0]\, C => - \ramwidth_m[0]\, Y => \busw_1[0]\); - - \r.address_RNI96NJ_0[0]\ : NOR2A - port map(A => wrn8, B => \brmw_i\, Y => N_510); - - \r.writedata[1]\ : DFN1E1 - port map(D => \writedata[1]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(1)); - - \r.mcfg2.rambanksz_RNI67EN71[3]\ : MX2 - port map(A => haddr(19), B => haddr(27), S => - \rambanksz[3]\, Y => N_5086); - - \r.data_RNIS2VV2[20]\ : NOR3C - port map(A => \hrdata_m[20]\, B => \hrdata_m_0[20]\, C => - hwdata_m_13, Y => \writedata_0_iv_1[20]\); - - \r.writedata_RNO_4[29]\ : NOR2B - port map(A => \address_RNI96NJ_5[0]\, B => N_123_i, Y => - \writedata_12_iv_0_0_a2_0[29]\); - - \r.writedata_RNO_2[18]\ : AO1A - port map(A => N_16464_tz, B => N_106, C => hwdata_18, Y => - \writedata_12_0_iv_i_1[18]\); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I12_Y_0\ : AX1B - port map(A => N_4, B => N_16, C => ADD_4x4_fast_I12_Y_0_0, - Y => \ws_1_sqmuxa_2[1]\); - - \r.data_RNIS6OK[14]\ : NOR2A - port map(A => \hrdata[14]\, B => \address_RNI96NJ_3[0]\, Y - => \hrdata_m[14]\); - - \r.address[9]\ : DFN1E1 - port map(D => haddr(9), CLK => lclk_c, E => N_36, Q => - address_c(9)); - - \r.mcfg1.romwws[3]\ : DFN1 - port map(D => \romwws_RNO[3]\, CLK => lclk_c, Q => - \romwws[3]\); - - \r.iosn_RNI6PIF1[1]\ : OR2 - port map(A => \iosn[1]\, B => iosn_0(93), Y => - \iosn_1_iv_0_a2_0[1]\); - - \r.writedata_RNO_2[22]\ : NOR2A - port map(A => \data[22]\, B => N_5160, Y => N_632); - - \r.bstate_RNI9O4Q1[4]\ : OA1C - port map(A => \bstate[4]\, B => ready10, C => \bstate[7]\, - Y => bstate_5_1); - - \r.mcfg2.rambanksz_RNIU17O4L_0[0]\ : OR3A - port map(A => \adec_2[0]\, B => \adec_2[1]\, C => iosn_99, - Y => \ramsn_1[3]\); - - \r.address[13]\ : DFN1E1 - port map(D => haddr(13), CLK => lclk_c, E => N_36_0, Q => - address_c(13)); - - \r.data[4]\ : DFN1 - port map(D => data_in(4), CLK => lclk_c, Q => \hrdata[4]\); - - \r.writedata_RNO_1[19]\ : OR2A - port map(A => \data[19]\, B => N_5160, Y => \data_m[19]\); - - \r.writedata_RNO_3[21]\ : OA1A - port map(A => \busw[1]\, B => wrn8, C => N_6563, Y => - \writedata_12_0_iv_i_a3_i_2_0_tz_0[21]\); - - \r.bstate_RNIHU8AA2[5]\ : OR2B - port map(A => bstate_0_sqmuxa, B => \bstate[5]\, Y => - iosn_0_sqmuxa_1); - - \r.data[15]\ : DFN1 - port map(D => data_in(15), CLK => lclk_c, Q => \hrdata[15]\); - - \r.ws_RNO_4[3]\ : OR3C - port map(A => \un1_wsnew_0_sqmuxa\, B => \romrws[3]\, C => - N_6457, Y => N_6449); - - \r.bstate_RNIHU8AA2_0[5]\ : OR2A - port map(A => \bstate[5]\, B => bstate_0_sqmuxa, Y => - iosn_1_sqmuxa_1); - - \apbo.prdata[27]\ : NOR2A - port map(A => \iowidth[0]\, B => N_232_0, Y => prdata_7); - - \r.romsn[1]\ : DFN1E0P0 - port map(D => \romsn_1[1]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => romsn_c(1)); - - \r.bstate_RNO_0[5]\ : NOR2 - port map(A => iosn_1_sqmuxa, B => N_451, Y => N_616); - - \r.writedata_RNO[18]\ : NOR3C - port map(A => \writedata_12_0_iv_i_0[18]\, B => N_163, C - => \writedata_12_0_iv_i_1[18]\, Y => N_62_i_0); - - \r.mcfg1.romwidth_RNO[0]\ : NOR2B - port map(A => rstn, B => pwdata_0_8, Y => N_6539); - - \r.data[2]\ : DFN1 - port map(D => data_in(2), CLK => lclk_c, Q => \hrdata[2]\); - - \r.wrn_RNO_1[2]\ : OA1B - port map(A => wrn_5_sqmuxa_s6_0_6, B => wrn_4_sqmuxa_s5_0_1, - C => wrn_1_sqmuxa_s2_0_3, Y => N_5196); - - \r.writedata_RNO_2[2]\ : NOR3B - port map(A => N_108, B => \address_c[1]\, C => hwdata_2, Y - => N_148); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I11_Y_0_0\ : XOR2 - port map(A => \ws[1]\, B => \A_i[0]\, Y => - ADD_4x4_fast_I11_Y_0_0); - - \r.data_RNIACH52[10]\ : OR2B - port map(A => N_6385, B => N_112, Y => \writedata[10]\); - - \r.ws_RNO[3]\ : OR3C - port map(A => N_6448, B => N_6450, C => \ws_0_0_0[3]\, Y - => \ws_RNO[3]\); - - \r.writedata_RNO_4[21]\ : OR3A - port map(A => \hrdata[21]\, B => \brmw_i\, C => N_439, Y - => N_539); - - \r.writedata_RNO[11]\ : AO1B - port map(A => hwdata_11, B => \address_RNI96NJ_3[0]\, C => - N_155, Y => \writedata[11]\); - - \r.size_RNI3PDH2[0]\ : OR3A - port map(A => wrn_6_sqmuxa_0_i_1, B => wrn35, C => N_438, Y - => N_6549); - - \r.area_RNIHHBD_0[2]\ : OR2 - port map(A => \area[2]\, B => \area[1]\, Y => rws_1_sqmuxa); - - \r.data_RNIOEQN3[7]\ : AO1C - port map(A => \N_6550\, B => \writedata_10[7]\, C => - \writedata_1_iv_0[7]\, Y => \writedata[7]\); - - \r.writedata_RNO_1[26]\ : AO1C - port map(A => hwdata_18, B => N_448, C => - \writedata_m_0_0[18]\, Y => \writedata_m_0[18]\); - - \r.ws_RNO_3[2]\ : NOR2A - port map(A => \romwws[2]\, B => N_6458, Y => - \ws_0_0_a2_2_0[2]\); - - \r.address[30]\ : DFN1E1 - port map(D => haddr(30), CLK => lclk_c, E => N_36, Q => - address(30)); - - \r.size_RNIA6IT[1]\ : NOR3A - port map(A => \busw[1]\, B => \size[1]\, C => wrn35, Y => - un1_wrn35_1); - - \r.data_RNIJFTL2[6]\ : MX2 - port map(A => hwdata_6, B => \hrdata[6]\, S => N_671, Y => - \writedata[6]\); - - \r.ramsn_RNO[1]\ : OR2 - port map(A => srhsel_0_sqmuxa, B => \ramsn_1[1]\, Y => - \ramsn_1_0[1]\); - - \r.ramoen_RNO_0[1]\ : MX2C - port map(A => \ramsn_c[1]\, B => \ramsn_1[1]\, S => - ramoen_1_sqmuxa_1, Y => N_5177); - - \r.data[3]\ : DFN1 - port map(D => data_in(3), CLK => lclk_c, Q => \hrdata[3]\); - - \r.data[22]\ : DFN1 - port map(D => data_in(22), CLK => lclk_c, Q => \hrdata[22]\); - - \r.data[20]\ : DFN1 - port map(D => data_in(20), CLK => lclk_c, Q => \hrdata[20]\); - - \r.oen_RNIJERI\ : NOR3C - port map(A => srhsel, B => \oen_c\, C => \read_c\, Y => - bstate_2_sqmuxa_1_0); - - \r.bstate_RNIR27I1[4]\ : OR2B - port map(A => \bstate[4]\, B => ready10, Y => N_610); - - \r.bstate_RNIM6SV2[4]\ : OA1C - port map(A => \bstate[4]\, B => ready10, C => - bstate_2_sqmuxa_1, Y => iosn_1_sqmuxa_1_0); - - \r.ramoen_RNO_0[3]\ : MX2C - port map(A => \ramsn_c[3]\, B => \ramsn_1[3]\, S => - ramoen_1_sqmuxa_1, Y => N_5179); - - \r.writedata_RNO[30]\ : OR3C - port map(A => \writedata_m[14]\, B => - \writedata_12_iv_0[30]\, C => \writedata_m_0[22]\, Y => - \writedata_12[30]\); - - \r.mcfg1.iows_RNO[3]\ : NOR2B - port map(A => rstn, B => N_5512, Y => N_567); - - \r.wrn_RNO[2]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => \wrn_90[2]\, C => rstn, - Y => \wrn_RNO[2]\); - - \r.data[7]\ : DFN1 - port map(D => data_in(7), CLK => lclk_c, Q => \hrdata[7]\); - - \r.mcfg1.romwws_RNO[1]\ : OR2A - port map(A => rstn, B => N_5502, Y => \romwws_RNO[1]\); - - \r.wrn_RNO_3[0]\ : OR3A - port map(A => N_394, B => wrn35, C => wrn_2_sqmuxa_s3_0_0, - Y => wrn_2_sqmuxa_s3_0_1); - - \r.mcfg2.rambanksz_RNILIUH71[3]\ : MX2 - port map(A => haddr(21), B => haddr(29), S => - \rambanksz[3]\, Y => N_5108); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I13_Y_0_0\ : XOR2 - port map(A => \ws[3]\, B => \A_i[0]\, Y => - ADD_4x4_fast_I13_Y_0_0); - - \r.ws_RNO_6[0]\ : OR3B - port map(A => \un1_wsnew_0_sqmuxa\, B => \romrws[0]\, C => - rws_1_sqmuxa, Y => \romrws_m[0]\); - - \r.bstate_RNI7RCR1[6]\ : OR2A - port map(A => N_500, B => \bstate[6]\, Y => \A_i[0]\); - - \r.busw[1]\ : DFN1E0 - port map(D => \busw_1[1]\, CLK => lclk_c, E => - srhsel_0_sqmuxa, Q => \busw[1]\); - - \r.busw_RNIIOLQ[0]\ : OR2B - port map(A => N_122_i_i_o2_1, B => N_122_i_i_o2_0, Y => - N_440); - - \r.writedata[25]\ : DFN1E1 - port map(D => \writedata_12[25]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(25)); - - \r.oen\ : DFN1E0P0 - port map(D => ramoen_2_sqmuxa_1, CLK => lclk_c, PRE => rstn, - E => ramoen_0_sqmuxa_1, Q => \oen_c\); - - \r.writedata[28]\ : DFN1E1 - port map(D => \writedata_12[28]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(28)); - - \r.mcfg2.rmw\ : DFN1E1 - port map(D => pwdata_1_d0, CLK => lclk_c, E => rmw_1_sqmuxa, - Q => \rmw\); - - \r.writedata_RNO_4[19]\ : OA1 - port map(A => N_439, B => \writedata_0_iv_i_a2_0[19]\, C - => N_123_i, Y => \writedata_m_0[19]\); - - \r.hwrite_RNI0B0398\ : AO1C - port map(A => bstate16, B => un18_srhsel, C => iosn_1_0, Y - => un1_iosn); - - \r.mcfg1.romwws[2]\ : DFN1 - port map(D => \romwws_RNO[2]\, CLK => lclk_c, Q => - \romwws[2]\); - - \r.writedata_RNO_0[9]\ : OR3B - port map(A => N_117, B => \hrdata[9]\, C => \brmw_i\, Y => - N_152); - - \r.mcfg1.bexcen\ : DFN1 - port map(D => bexcen_RNO, CLK => lclk_c, Q => \bexcen\); - - \r.data_RNI8IVK1[0]\ : MX2 - port map(A => hwdata_0, B => \hrdata[0]\, S => N_394, Y => - \writedata_10[0]\); - - \r.ws_RNO_6[1]\ : OR3B - port map(A => \un1_wsnew_0_sqmuxa\, B => \romrws[1]\, C => - rws_1_sqmuxa, Y => \romrws_m[1]\); - - \r.writedata_RNO_1[27]\ : OR2B - port map(A => writedata_1_sqmuxa, B => hwdata_19, Y => - N_183); - - \r.mcfg2.rambanksz_RNIU17O4L_1[0]\ : OR3 - port map(A => \adec_2[1]\, B => iosn_99, C => \adec_2[0]\, - Y => \ramsn_1[2]\); - - \r.hburst[1]\ : DFN1E1 - port map(D => hburst_0(1), CLK => lclk_c, E => un1_ahbsi_1, - Q => \hburst[1]\); - - \r.mcfg2.ramrws_RNI9JIA[0]\ : MX2 - port map(A => \romrws[0]\, B => \ramrws[0]\, S => paddr(2), - Y => N_5062); - - \r.mcfg1.ioen_RNO_0\ : MX2 - port map(A => \ioen\, B => pwdata_14, S => bexcen_0_sqmuxa, - Y => N_5526); - - \r.ws_RNO_3[3]\ : XA1 - port map(A => N90_i, B => ADD_4x4_fast_I13_Y_0_0, C => - bstate_3, Y => \ws_0_0_a2_0[3]\); - - \r.ws_RNO_2[2]\ : AOI1B - port map(A => \ws_0_0_a2_2_0[2]\, B => N_6457, C => N_6444, - Y => \ws_0_0_1[2]\); - - \r.data_RNIIJ5S1[7]\ : OA1A - port map(A => \hrdata[7]\, B => N_5112, C => hwdata_m_0_d0, - Y => \writedata_1_iv_0[7]\); - - \r.ws[1]\ : DFN1 - port map(D => \ws_RNO[1]\, CLK => lclk_c, Q => \ws[1]\); - - \r.data[31]\ : DFN1 - port map(D => data_in(31), CLK => lclk_c, Q => \hrdata[31]\); - - \r.address_RNI96NJ[0]\ : NOR2A - port map(A => \address_c[0]\, B => N_5112, Y => N_38_i); - - GND_i : GND - port map(Y => \GND\); - - \r.address[31]\ : DFN1E1 - port map(D => hsel_i(0), CLK => lclk_c, E => N_36, Q => - address(31)); - - \r.writedata_RNO[22]\ : OR3 - port map(A => \writedata_12_0_iv_i_i_0[22]\, B => N_630, C - => N_515, Y => N_308); - - \r.mcfg2.ramwws_RNO[0]\ : NOR2B - port map(A => rstn, B => N_5517, Y => N_562); - - \r.mcfg1.romwws_RNO[3]\ : OR2A - port map(A => rstn, B => N_5504, Y => \romwws_RNO[3]\); - - \r.hresp_RNO[0]\ : OR2 - port map(A => \bstate[6]\, B => N_6565, Y => \hresp_6[0]\); - - \r.writedata[14]\ : DFN1E1 - port map(D => \writedata[14]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(14)); - - \r.mcfg1.bexcen_RNO_0\ : MX2 - port map(A => \bexcen\, B => pwdata_20, S => - bexcen_0_sqmuxa, Y => N_5528); - - \r.busw_RNIRAK11[1]\ : OR2 - port map(A => \busw[1]\, B => N_396, Y => N_123_i); - - \r.ws_RNO_3[0]\ : OR2B - port map(A => un1_rws_0_sqmuxa, B => \iows[0]\, Y => - \iows_m[0]\); - - \r.brmw_RNICGSJ\ : NOR2 - port map(A => brmw, B => N_413, Y => ready_0_0_a2_0_0); - - \r.ws_RNO_5[1]\ : OR3A - port map(A => \romwws[1]\, B => N_6458, C => rws_1_sqmuxa, - Y => \romwws_m[1]\); - - \r.mcfg2.rambanksz_RNI27TO71[3]\ : MX2 - port map(A => haddr(20), B => haddr(28), S => - \rambanksz[3]\, Y => N_5101); - - \r.brmw_RNILLO71\ : MX2A - port map(A => N_396, B => brmw, S => \busw[1]\, Y => N_420); - - \r.mcfg2.ramwidth[0]\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => rmw_1_sqmuxa, - Q => \ramwidth[0]\); - - \r.mcfg1.romwws_RNO_0[0]\ : MX2 - port map(A => \romwws[0]\, B => pwdata_1_3, S => - bexcen_0_sqmuxa, Y => N_5501); - - \r.mcfg2.rambanksz_RNI2E9C71[3]\ : MX2 - port map(A => haddr(18), B => haddr(26), S => - \rambanksz[3]\, Y => N_5098); - - \r.srhsel\ : DFN1 - port map(D => N_80, CLK => lclk_c, Q => srhsel); - - \r.address_RNI96NJ_6[0]\ : NOR2 - port map(A => N_425, B => \brmw_i\, Y => - \writedata_4_m_0[20]\); - - \r.writedata_RNO_1[29]\ : AOI1B - port map(A => \writedata_12_iv_0_0_a2_0[29]\, B => - hwdata_29, C => N_552, Y => \writedata_12_iv_0_0_0[29]\); - - \r.iosn[0]\ : DFN1P0 - port map(D => \iosn_i_m[1]\, CLK => lclk_c, PRE => rstn, Q - => iosn_c); - - \r.data_RNITAOK[15]\ : OR2A - port map(A => \hrdata[15]\, B => \address_RNI96NJ_3[0]\, Y - => \hrdata_m[15]\); - - \r.address_RNI6OQE2[0]\ : OR2A - port map(A => hwdata_3, B => N_671, Y => N_506); - - \r.address[25]\ : DFN1E1 - port map(D => haddr(25), CLK => lclk_c, E => N_36, Q => - address_c(25)); - - \r.mcfg2.rambanksz[1]\ : DFN1E1 - port map(D => pwdata_5, CLK => lclk_c, E => rmw_1_sqmuxa, Q - => \rambanksz[1]\); - - \r.address_RNIPQ7A1[0]\ : NOR2 - port map(A => \writedata_1_iv_0_a2_1_0[3]\, B => N_649, Y - => N_671); - - \r.busw_RNITO8A[1]\ : NOR2A - port map(A => \address_c[1]\, B => \busw[1]\, Y => - N_122_i_i_o2_0); - - \r.address_RNI59K6[0]\ : OR2B - port map(A => \address_c[1]\, B => \address_c[0]\, Y => - N_126_i); - - \r.writedata_RNO_3[28]\ : AO1B - port map(A => \writedata_1_iv_0[28]\, B => \hwdata_m[28]\, - C => N_123_i, Y => \writedata_m[28]\); - - \r.writedata[10]\ : DFN1E1 - port map(D => \writedata[10]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(10)); - - \r.busw_RNIBG5H1[1]\ : NOR2A - port map(A => hwdata_22, B => \busw[1]\, Y => N_6564); - - \r.hburst_RNIDSN2[0]\ : OR3 - port map(A => \hburst[1]\, B => \hburst[0]\, C => - \hburst[2]\, Y => hburst_i_0); - - \r.writedata_RNO_4[28]\ : OAI1 - port map(A => N_6555_i_0, B => N_38_i, C => \hrdata[28]\, Y - => \writedata_1_iv_0[28]\); - - \r.ramoen_RNO[2]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => ramoen_2_sqmuxa, C => - N_5178, Y => \ramoen_1[2]\); - - \r.bstate_RNO[7]\ : XO1A - port map(A => \bstate[7]\, B => iosn_1_sqmuxa, C => N_446, - Y => \bstate_RNO[7]\); - - \r.address_RNIGKGM_0[0]\ : OR2 - port map(A => N_425, B => N_394, Y => N_6563); - - \r.address[26]\ : DFN1E1 - port map(D => haddr(26), CLK => lclk_c, E => N_36, Q => - address_c(26)); - - \apbo.prdata_10_0_a2_0_0\ : OR2A - port map(A => paddr(2), B => paddr(3), Y => N_6455_0); - - \r.mcfg2.ramrws_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5520, Y => N_561); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I0_CO1_i\ : NOR2A - port map(A => \ws[0]\, B => \A_i[0]\, Y => N_4); - - \r.writedata_RNO_1[21]\ : OA1A - port map(A => \data[21]\, B => N_5160, C => N_539, Y => - \writedata_12_0_iv_i_a3_i_0[21]\); - - \r.srhsel_RNO\ : OA1A - port map(A => srhsel_0_sqmuxa, B => srhsel_RNO_0, C => rstn, - Y => N_80); - - \r.busw_RNO_0[1]\ : OR2A - port map(A => \iowidth[1]\, B => iosn_100, Y => - \iowidth_m[1]\); - - \r.ramsn[0]\ : DFN1E0P0 - port map(D => \ramsn_1_0[0]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => \ramsn_c[0]\); - - \r.data_RNITG792[0]\ : AOI1B - port map(A => hwdata_0, B => \N_6377\, C => \hrdata_m[0]\, - Y => \writedata_1_iv_0[0]\); - - \r.writedata[6]\ : DFN1E1 - port map(D => \writedata[6]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(6)); - - \r.writedata_RNO_1[18]\ : OR2 - port map(A => hwdata_2, B => N_440, Y => N_163); - - \r.ws_RNIU7HS[1]\ : OR2B - port map(A => ws_1, B => ws_0, Y => ws); - - \r.mcfg1.romrws[1]\ : DFN1 - port map(D => N_559, CLK => lclk_c, Q => \romrws[1]\); - - \r.bstate[5]\ : DFN1 - port map(D => N_295, CLK => lclk_c, Q => \bstate[5]\); - - \r.address[28]\ : DFN1E1 - port map(D => haddr(28), CLK => lclk_c, E => N_36, Q => - address(28)); - - \r.writedata[29]\ : DFN1E1 - port map(D => \writedata_12[29]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(29)); - - \r.address_RNI96NJ_4[0]\ : OR2 - port map(A => \brmw_i\, B => N_117, Y => \N_6550\); - - wsnew_0_sqmuxa : NAND2 - port map(A => \read_c\, B => \bstate[7]\, Y => - \wsnew_0_sqmuxa\); - - \r.mcfg2.ramwws_RNO_0[0]\ : MX2 - port map(A => \ramwws[0]\, B => pwdata_0_2, S => - rmw_1_sqmuxa, Y => N_5517); - - \r.address[29]\ : DFN1E1 - port map(D => haddr(29), CLK => lclk_c, E => N_36, Q => - address(29)); - - \r.wrn_RNO_1[1]\ : OA1B - port map(A => wrn_5_sqmuxa_s6_0_6, B => wrn_3_sqmuxa_s4_0_1, - C => wrn_1_sqmuxa_s2_0_3, Y => N_5195); - - \r.mcfg1.romrws_RNO_0[1]\ : MX2 - port map(A => \romrws[1]\, B => pwdata_0_1, S => - bexcen_0_sqmuxa, Y => N_5506); - - \r.ws_RNO_4[1]\ : OR3A - port map(A => \ramwws[1]\, B => N_6458, C => rws_0_sqmuxa, - Y => \ramwws_m[1]\); - - un1_wsnew_0_sqmuxa : NAND2 - port map(A => ws_0_sqmuxa, B => \wsnew_0_sqmuxa\, Y => - \un1_wsnew_0_sqmuxa\); - - \r.bdrive_RNO[1]\ : OA1C - port map(A => N_6568_i_0, B => \bdrive[1]\, C => N_6567_i_0, - Y => N_288); - - \r.busw[0]\ : DFN1E0 - port map(D => \busw_1[0]\, CLK => lclk_c, E => - srhsel_0_sqmuxa, Q => \busw[0]\); - - \r.ramoen_RNO[1]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => ramoen_2_sqmuxa, C => - N_5177, Y => \ramoen_1[1]\); - - \r.writedata_RNO_1[20]\ : OR2A - port map(A => \writedata[4]\, B => N_440, Y => - \writedata_m[4]\); - - \r.writedata[9]\ : DFN1E1 - port map(D => \writedata[9]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(9)); - - \r.writedata[21]\ : DFN1E1 - port map(D => N_6554, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[21]\); - - \r.area_RNITSBEJ1_0[1]\ : AO1C - port map(A => ws, B => address_1_sqmuxa_i_a2_1, C => - srhsel_0_sqmuxa, Y => N_36); - - \r.area_RNIHHBD[2]\ : OR2A - port map(A => \area[2]\, B => \area[1]\, Y => rws_0_sqmuxa); - - \r.bstate_RNI40681[7]\ : NOR2A - port map(A => \bstate[7]\, B => bstate_2_sqmuxa, Y => - oen_1_sqmuxa); - - \un1_v.ws_1_sqmuxa_2_m[2]\ : XAI1A - port map(A => N_4, B => ADD_4x4_fast_I11_Y_0_0, C => - bstate_3, Y => \ws_1_sqmuxa_2_m[2]\); - - \r.data_RNIPMNK_0[20]\ : OR2A - port map(A => \hrdata[20]\, B => \N_6550\, Y => - \hrdata_m[20]\); - - \r.ws[2]\ : DFN1 - port map(D => \ws_RNO[2]\, CLK => lclk_c, Q => \ws[2]\); - - \r.wrn[2]\ : DFN1 - port map(D => \wrn_RNO[2]\, CLK => lclk_c, Q => \rwen_c[2]\); - - \r.address_RNI59K6_1[0]\ : OR2A - port map(A => \address_c[0]\, B => \address_c[1]\, Y => - wrn8); - - \r.ws_RNO_2[0]\ : OR3B - port map(A => \un1_wsnew_0_sqmuxa\, B => \ramrws[0]\, C => - rws_0_sqmuxa, Y => \ramrws_m[0]\); - - \r.ready_RNINOQK\ : OR2 - port map(A => \hready\, B => N_413, Y => bstate_0_sqmuxa_0); - - \r.address[0]\ : DFN1E1 - port map(D => haddr(0), CLK => lclk_c, E => N_36_0, Q => - \address_c[0]\); - - \r.ready_RNO\ : OR3A - port map(A => rstn, B => N_661, C => ready_0_0_o2_0, Y => - ready_RNO); - - \r.mcfg2.rambanksz_RNI6IDMU9[0]\ : MX2 - port map(A => N_5088, B => N_5103, S => \rambanksz[0]\, Y - => \adec_2[0]\); - - \r.data[25]\ : DFN1 - port map(D => data_in(25), CLK => lclk_c, Q => \hrdata[25]\); - - \r.mcfg2.rambanksz_RNI5ETH71[3]\ : MX2 - port map(A => haddr(15), B => haddr(23), S => - \rambanksz[3]\, Y => N_5085); - - \r.busw_RNILVCG[0]\ : MX2C - port map(A => \address_c[0]\, B => brmw, S => \busw[0]\, Y - => N_122_i_i_o2_1); - - \r.area[0]\ : DFN1E0 - port map(D => hmbsel_1(0), CLK => lclk_c, E => - srhsel_0_sqmuxa, Q => \area[0]\); - - \r.mcfg2.rambanksz_RNIGN9JF2[2]\ : MX2C - port map(A => N_5100, B => N_5101, S => \rambanksz[2]\, Y - => N_5094); - - \r.data[11]\ : DFN1 - port map(D => data_in(11), CLK => lclk_c, Q => \hrdata[11]\); - - \r.srhsel_RNI8LPQ\ : NOR2A - port map(A => N_412, B => N_424, Y => N_431); - - \r.data_RNI11A41[22]\ : OR3B - port map(A => brmw, B => \hrdata[22]\, C => N_439, Y => - N_634); - - \r.wrn[0]\ : DFN1 - port map(D => \wrn_RNO[0]\, CLK => lclk_c, Q => \rwen_c[0]\); - - \r.mcfg2.rambanksz_RNIKV56V4[1]\ : MX2C - port map(A => N_5091, B => N_5094, S => \rambanksz[1]\, Y - => N_5103); - - \r.writedata_RNO[28]\ : OR3C - port map(A => \writedata_12_iv_0[28]\, B => - \writedata_m[12]\, C => \writedata_m_0[20]\, Y => - \writedata_12[28]\); - - \r.data_RNI7LOV2[13]\ : OR2B - port map(A => N_6411, B => N_6410, Y => \writedata[13]\); - - \r.writedata_RNO[21]\ : OR3C - port map(A => \writedata_12_0_iv_i_a3_i_2_0[21]\, B => - \writedata_12_0_iv_i_a3_i_0[21]\, C => N_543, Y => N_6554); - - \r.ready_RNIL0CH1\ : OR2 - port map(A => ws, B => bstate_0_sqmuxa_0, Y => - bstate_0_sqmuxa_1); - - \r.area_RNI59B2A2[1]\ : NOR2 - port map(A => bstate_0_sqmuxa_1, B => N_195, Y => - bstate_0_sqmuxa); - - \r.writedata[12]\ : DFN1E1 - port map(D => \writedata[12]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(12)); - - \r.writedata_RNO_3[16]\ : OR2A - port map(A => \hrdata[16]\, B => N_448, Y => N_532); - - \r.mcfg2.ramwidth_RNIS2P4K[1]\ : NOR3C - port map(A => \rmw\, B => \ramwidth[1]\, C => haddr(30), Y - => brmw_1_1); - - \r.writedata_RNO_4[18]\ : OAI1 - port map(A => N_425, B => \busw[1]\, C => N_669, Y => - N_16464_tz); - - \r.writedata_RNO_0[16]\ : OA1A - port map(A => \data[16]\, B => N_5160, C => N_532, Y => - \writedata_12_0_iv_0_0[16]\); - - \r.mcfg2.rambanksz_RNIV3N4V4[1]\ : MX2C - port map(A => N_5106, B => N_5109, S => \rambanksz[1]\, Y - => N_5110); - - \r.writedata_RNO_0[2]\ : NOR2A - port map(A => \brmw_i\, B => hwdata_2, Y => N_149); - - \r.brmw_RNI4JE41\ : OA1B - port map(A => N_517, B => \writedata_12_0_iv_i_a2_4_0[18]\, - C => N_199, Y => N_106); - - \r.wrn_RNO_2[3]\ : MX2A - port map(A => \address_c[1]\, B => \rwen_c[3]\, S => N_6549, - Y => N_5203); - - \r.wrn_RNO_3[3]\ : OR3A - port map(A => N_394, B => wrn35, C => wrn_5_sqmuxa_s6_0_0, - Y => wrn_5_sqmuxa_s6_0_1); - - \r.area_RNIVJGU[0]\ : OR2B - port map(A => hresp2_i_0, B => N_412, Y => N_6547); - - \r.bstate_RNI2NQID2[5]\ : AOI1 - port map(A => romsn_1_sqmuxa, B => bstate_5_1, C => - iosn_1_0, Y => romsn_0_sqmuxa_1); - - \r.bstate_0_i_o2[5]\ : OR2B - port map(A => ramoen_0_sqmuxa, B => rstn, Y => N_446); - - \r.address[20]\ : DFN1E1 - port map(D => haddr(20), CLK => lclk_c, E => N_36_0, Q => - address_c(20)); - - \r.busw_RNI3T2D[0]\ : NOR2B - port map(A => \busw[0]\, B => brmw, Y => N_635); - - \r.address[15]\ : DFN1E1 - port map(D => haddr(15), CLK => lclk_c, E => N_36_0, Q => - address_c(15)); - - \r.data_RNISALJ1[20]\ : MX2 - port map(A => hwdata_20, B => \hrdata[20]\, S => N_394, Y - => \writedata_4[20]\); - - \r.area_RNISN3H_0[0]\ : NOR3A - port map(A => \area[0]\, B => romwrite, C => \read_c\, Y - => N_653); - - \r.data_RNIQUNK[12]\ : OR2A - port map(A => \hrdata[12]\, B => \address_RNI96NJ_3[0]\, Y - => \hrdata_m[12]\); - - \r.data[17]\ : DFN1 - port map(D => data_in(17), CLK => lclk_c, Q => \hrdata[17]\); - - \r.data_RNIR2OK[13]\ : OR2A - port map(A => \hrdata[13]\, B => \address_RNI96NJ_3[0]\, Y - => N_6410); - - \r.busw_RNIVF341[1]\ : OR2B - port map(A => \busw[1]\, B => N_439, Y => N_669); - - \r.data_RNIPMNK[20]\ : OR3A - port map(A => \hrdata[20]\, B => N_126_i, C => \brmw_i\, Y - => \hrdata_m_0[20]\); - - \r.mcfg1.romwws_RNO[0]\ : OR2A - port map(A => rstn, B => N_5501, Y => \romwws_RNO[0]\); - - \r.mcfg1.iowidth[0]\ : DFN1E1 - port map(D => pwdata_22, CLK => lclk_c, E => - bexcen_0_sqmuxa, Q => \iowidth[0]\); - - \r.data[9]\ : DFN1 - port map(D => data_in(9), CLK => lclk_c, Q => \hrdata[9]\); - - \r.writedata_RNO[19]\ : OR3C - port map(A => \writedata_m[19]\, B => \data_m[19]\, C => - \writedata_m[3]\, Y => \writedata_12[19]\); - - \r.writedata[27]\ : DFN1E1 - port map(D => \writedata_12[27]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(27)); - - \r.mcfg1.iows_RNO_0[2]\ : MX2 - port map(A => \iows[2]\, B => pwdata_17, S => - bexcen_0_sqmuxa, Y => N_5511); - - \r.address[16]\ : DFN1E1 - port map(D => haddr(16), CLK => lclk_c, E => N_36_0, Q => - address_c(16)); - - \r.romsn_RNO[1]\ : OR3A - port map(A => haddr(28), B => hmbsel(0), C => - \un1_romsn_0_sqmuxa_1_0[0]_net_1\, Y => \romsn_1[1]\); - - \r.ramsn[1]\ : DFN1E0P0 - port map(D => \ramsn_1_0[1]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => \ramsn_c[1]\); - - \r.writedata_RNO_3[25]\ : OR2B - port map(A => writedata_1_sqmuxa, B => hwdata_17, Y => - N_188); - - \r.writedata_RNO_1[28]\ : OR2A - port map(A => \writedata[12]\, B => N_440, Y => - \writedata_m[12]\); - - \r.ramoen_RNO[3]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => ramoen_2_sqmuxa, C => - N_5179, Y => \ramoen_1[3]\); - - \r.mcfg1.iows[3]\ : DFN1 - port map(D => N_567, CLK => lclk_c, Q => \iows[3]\); - - \r.iosn_RNO[1]\ : OA1A - port map(A => iosn_1_8, B => srhsel_0_sqmuxa, C => - \iosn_i_m[1]\, Y => \iosn_1_iv[1]\); - - \r.writedata_RNO_3[17]\ : OR2A - port map(A => \data[17]\, B => N_5160, Y => N_514); - - \apbo.prdata[28]\ : NOR2A - port map(A => \iowidth[1]\, B => N_232_0, Y => prdata_8); - - \r.mcfg1.romwws_RNO_0[1]\ : MX2 - port map(A => \romwws[1]\, B => pwdata_0_5, S => - bexcen_0_sqmuxa, Y => N_5502); - - \r.mcfg1.romwws_RNO[2]\ : OR2A - port map(A => rstn, B => N_5503, Y => \romwws_RNO[2]\); - - \r.address[18]\ : DFN1E1 - port map(D => haddr(18), CLK => lclk_c, E => N_36_0, Q => - address_c(18)); - - \r.address_RNI96NJ_2[0]\ : OR2A - port map(A => N_126_i, B => \brmw_i\, Y => - \writedata_1_iv_0_a2_1_0[3]\); - - \r.writedata_RNO_0[17]\ : AO1B - port map(A => N_669, B => N_420, C => hwdata_17, Y => N_511); - - \r.brmw_RNI4T2D_0\ : NOR2A - port map(A => \busw[1]\, B => brmw, Y => N_199); - - \r.busw_RNO[1]\ : OR3C - port map(A => \iowidth_m[1]\, B => \ramwidth_m[1]\, C => - \romwidth_m[1]\, Y => \busw_1[1]\); - - \r.address[19]\ : DFN1E1 - port map(D => haddr(19), CLK => lclk_c, E => N_36_0, Q => - address_c(19)); - - \r.writedata_RNO_5[30]\ : OR2B - port map(A => hwdata_30, B => \address_RNI96NJ_5[0]\, Y => - \hwdata_m[30]\); - - \r.busw_RNI577H[0]\ : OR3A - port map(A => \address_c[0]\, B => \busw[0]\, C => - \busw[1]\, Y => N_5160); - - \r.data_RNITKT71[7]\ : MX2 - port map(A => hwdata_7, B => \hrdata[7]\, S => N_394, Y => - \writedata_10[7]\); - - \r.writedata_RNO_0[31]\ : OA1A - port map(A => \writedata[15]\, B => N_440, C => - \writedata_12_iv_0[31]\, Y => \writedata_12_iv_1[31]\); - - \r.bdrive_RNIA1PF[0]\ : NOR2B - port map(A => \bstate[7]\, B => \bdrive[0]\, Y => - writedata_0_sqmuxa_0); - - \r.mcfg2.rambanksz_RNIU17O4L_2[0]\ : NOR3A - port map(A => \adec_2[1]\, B => iosn_99, C => \adec_2[0]\, - Y => \ramsn_1[0]\); - - \r.ws_RNO_4[2]\ : OR3C - port map(A => rstn, B => un1_rws_0_sqmuxa, C => \iows[2]\, - Y => N_6444); - - \r.data_RNIO7NP1[8]\ : MX2 - port map(A => \hrdata[8]\, B => hwdata_8, S => - \address_RNI96NJ_3[0]\, Y => \writedata[8]\); - - \r.writedata_RNO[23]\ : AO1C - port map(A => N_440, B => \writedata[7]\, C => - \writedata_12_0_iv_0[23]\, Y => \writedata_12[23]\); - - \r.writedata_RNO_5[26]\ : NOR2B - port map(A => writedata_1_sqmuxa, B => N_160, Y => - \writedata_m_0_0[18]\); - - \r.ramsn_RNO[0]\ : OR2A - port map(A => \ramsn_1[0]\, B => srhsel_0_sqmuxa, Y => - \ramsn_1_0[0]\); - - \r.writedata_RNO_0[26]\ : AO1B - port map(A => \writedata_1_iv_0[26]\, B => \hwdata_m[26]\, - C => N_123_i, Y => \writedata_m[26]\); - - \r.data_RNIPC9L4[12]\ : OR3C - port map(A => hwdata_m_5, B => \hrdata_m[12]\, C => - hwdata_m_0_0, Y => \writedata[12]\); - - \r.size_RNIEJF92[1]\ : NOR3 - port map(A => un1_wrn35_1, B => N_424, C => N_6547, Y => - wrn_1_sqmuxa_s2_0_3); - - \r.ramoen[0]\ : DFN1E0P0 - port map(D => \ramoen_1[0]\, CLK => lclk_c, PRE => rstn, E - => ramoen_0_sqmuxa_1, Q => ramoen_c(0)); - - \r.size_RNIBBSF[0]\ : NOR2 - port map(A => \size[1]\, B => \size[0]\, Y => N_394); - - \r.bstate[6]\ : DFN1 - port map(D => \bstate_RNO[6]\, CLK => lclk_c, Q => - \bstate[6]\); - - \r.address[27]\ : DFN1E1 - port map(D => haddr(27), CLK => lclk_c, E => N_36, Q => - address_c(27)); - - \r.wrn_RNO_1[0]\ : OA1B - port map(A => wrn_5_sqmuxa_s6_0_6, B => wrn_2_sqmuxa_s3_0_1, - C => wrn_1_sqmuxa_s2_0_3, Y => N_5194); - - \r.writedata_RNO[20]\ : AO1B - port map(A => \writedata[20]\, B => N_123_i, C => - \writedata_12_0_iv_0[20]\, Y => \writedata_12[20]\); - - \r.writedata_RNO_3[24]\ : OR2 - port map(A => \hrdata[24]\, B => \address_RNI96NJ_5[0]\, Y - => \writedata_RNO_3[24]\); - - \r.bstate_RNO_1[4]\ : NOR2A - port map(A => N_438, B => iosn_1_sqmuxa, Y => N_618); - - \r.mcfg1.romrws[0]\ : DFN1 - port map(D => N_558, CLK => lclk_c, Q => \romrws[0]\); - - \r.writedata[4]\ : DFN1E1 - port map(D => \writedata[4]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(4)); - - \r.mcfg2.rambanksz_RNIVCRGF2[2]\ : MX2C - port map(A => N_5085, B => N_5086, S => \rambanksz[2]\, Y - => N_5106); - - \r.mcfg2.ramrws[0]\ : DFN1 - port map(D => \ramrws_RNO[0]\, CLK => lclk_c, Q => - \ramrws[0]\); - - \r.address[21]\ : DFN1E1 - port map(D => haddr(21), CLK => lclk_c, E => N_36_0, Q => - address_c(21)); - - \r.writedata_RNO_3[19]\ : OA1A - port map(A => N_439, B => hwdata_19, C => - \writedata_m_0[19]\, Y => \writedata_m_1[19]\); - - \r.mcfg1.brdyen_RNO\ : NOR2B - port map(A => rstn, B => N_5527, Y => brdyen_RNO); - - \r.bstate[7]\ : DFN1 - port map(D => \bstate_RNO[7]\, CLK => lclk_c, Q => - \bstate[7]\); - - \r.writedata_RNO_0[30]\ : OR2A - port map(A => \writedata[14]\, B => N_440, Y => - \writedata_m[14]\); - - \r.writedata[16]\ : DFN1E1 - port map(D => \writedata_12[16]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[16]\); - - \r.writedata_RNO_1[23]\ : OR2A - port map(A => \data[23]\, B => N_5160, Y => \data_m[23]\); - - \r.writedata_RNO[16]\ : OR3C - port map(A => \writedata_12_0_iv_0_0[16]\, B => N_530, C - => N_531, Y => \writedata_12[16]\); - - \r.ramoen[3]\ : DFN1E0P0 - port map(D => \ramoen_1[3]\, CLK => lclk_c, PRE => rstn, E - => ramoen_0_sqmuxa_1, Q => ramoen_c(3)); - - \r.writedata_RNO_5[19]\ : OR2 - port map(A => \hrdata[19]\, B => \brmw_i\, Y => - \writedata_0_iv_i_a2_0[19]\); - - \r.mcfg2.ramwws_RNO_0[1]\ : MX2 - port map(A => \ramwws[1]\, B => pwdata_1_2, S => - rmw_1_sqmuxa, Y => N_5518); - - \r.writedata_RNO_4[24]\ : OR2A - port map(A => writedata_1_sqmuxa, B => hwdata_16, Y => - N_193); - - \r.writedata[13]\ : DFN1E1 - port map(D => \writedata[13]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(13)); - - \ctrl.v.writedata_12_iv_0_a2[25]\ : NAND2 - port map(A => N_111, B => hwdata_25, Y => N_185); - - \r.writedata_RNO_0[19]\ : AO1C - port map(A => hwdata_19, B => \brmw_i\, C => - \writedata_m_1[19]\, Y => \writedata_m[19]\); - - \r.data_RNILEFN[0]\ : OR2A - port map(A => \hrdata[0]\, B => N_5112, Y => \hrdata_m[0]\); - - \r.area[2]\ : DFN1E0 - port map(D => haddr(30), CLK => lclk_c, E => - srhsel_0_sqmuxa, Q => \area[2]\); - - \r.writedata_RNO_2[26]\ : AOI1B - port map(A => hwdata_2, B => N_46_i_0, C => - \writedata_m[10]\, Y => \writedata_12_iv_0[26]\); - - \r.bstate_RNO_1[5]\ : NOR2 - port map(A => iosn_1_sqmuxa_1_0, B => \bstate[5]\, Y => - N_617); - - \r.address[22]\ : DFN1E1 - port map(D => haddr(22), CLK => lclk_c, E => N_36_0, Q => - address_c(22)); - - \r.area_RNIAELE[2]\ : NOR2B - port map(A => \rmw\, B => \area[2]\, Y => wrn35); - - \r.address[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => N_36, Q => - address_c(2)); - - \r.writen\ : DFN1 - port map(D => writen_RNO, CLK => lclk_c, Q => \writen_c\); - - \r.mcfg1.romwrite_RNO\ : NOR2B - port map(A => rstn, B => N_5525, Y => romwrite_RNO); - - \r.writedata[30]\ : DFN1E1 - port map(D => \writedata_12[30]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(30)); - - \r.mcfg2.rambanksz_RNIU17O4L[0]\ : OR3B - port map(A => \adec_2[1]\, B => \adec_2[0]\, C => iosn_99, - Y => \ramsn_1[1]\); - - \r.data_RNICN8B1[23]\ : OR3A - port map(A => \hrdata[23]\, B => \brmw_i\, C => N_439, Y - => N_538); - - \r.writen_RNO_2\ : OR2A - port map(A => ramoen_0_sqmuxa, B => N_435, Y => N_280); - - \r.wrn_RNO_2[2]\ : MX2A - port map(A => \address_c[1]\, B => \rwen_c[2]\, S => N_6549, - Y => N_5202); - - \r.mcfg2.ramrws[1]\ : DFN1 - port map(D => N_561, CLK => lclk_c, Q => \ramrws[1]\); - - \r.bstate_RNI29IF5[4]\ : OR2B - port map(A => N_6549, B => N_435, Y => writen_0_sqmuxa_1_0); - - \r.mcfg2.ramwws[0]\ : DFN1 - port map(D => N_562, CLK => lclk_c, Q => \ramwws[0]\); - - \ctrl.v.writedata_12_iv_0_a2_1[25]\ : OR2A - port map(A => \hrdata[25]\, B => \address_RNI96NJ_5[0]\, Y - => N_187); - - \r.read\ : DFN1 - port map(D => read_RNO_0, CLK => lclk_c, Q => \read_c\); - - \r.bstate_RNI4B6BA8[7]\ : OR2B - port map(A => oen_1_sqmuxa, B => un1_iosn, Y => - ramoen_1_sqmuxa_1); - - \r.bstate[4]\ : DFN1 - port map(D => N_297, CLK => lclk_c, Q => \bstate[4]\); - - \r.writedata_RNO_0[11]\ : OR3B - port map(A => N_117, B => \hrdata[11]\, C => \brmw_i\, Y - => N_155); - - \r.iosn_RNI0G0KD2[1]\ : AO1 - port map(A => iosn_1_sqmuxa_1, B => bstate_5_1, C => - \iosn_1_iv_0_a2_0[1]\, Y => \iosn_i_m[1]\); - - \r.address_RNICI0B2[0]\ : OR2B - port map(A => hwdata_13, B => \address_RNI96NJ_3[0]\, Y => - N_6411); - - \r.writedata_RNO_0[27]\ : OA1A - port map(A => hwdata_11, B => N_440, C => - \writedata_12_iv_0_0[27]\, Y => \writedata_12_iv_0_1[27]\); - - \r.ws_RNO_0[2]\ : OR3C - port map(A => \un1_wsnew_0_sqmuxa\, B => \romrws[2]\, C => - N_6457, Y => N_6445); - - \r.bdrive_RNIA1PF_0[0]\ : NOR2B - port map(A => \bstate[7]\, B => \bdrive[0]\, Y => - writedata_0_sqmuxa); - - \r.ws_RNO[1]\ : AOI1B - port map(A => \ws_3_iv_3[1]\, B => \ws_1_sqmuxa_2_m[2]\, C - => rstn, Y => \ws_RNO[1]\); - - \r.writedata[3]\ : DFN1E1 - port map(D => \writedata[3]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(3)); - - \r.address[10]\ : DFN1E1 - port map(D => haddr(10), CLK => lclk_c, E => N_36_0, Q => - address_c(10)); - - \r.ws_RNO_3[1]\ : OR2B - port map(A => un1_rws_0_sqmuxa, B => \iows[1]\, Y => - \iows_m[1]\); - - \r.read_RNO\ : OR2B - port map(A => un18_srhsel, B => rstn, Y => read_RNO_0); - - \r.mcfg1.iows[0]\ : DFN1 - port map(D => N_564, CLK => lclk_c, Q => \iows[0]\); - - \r.address[7]\ : DFN1E1 - port map(D => haddr(7), CLK => lclk_c, E => N_36, Q => - address_c(7)); - - \r.data_RNIBT864[23]\ : AO1B - port map(A => hwdata_23, B => N_448, C => N_538, Y => - \writedata[23]\); - - \r.mcfg1.romwidth_RNO[1]\ : OR2A - port map(A => rstn, B => pwdata_0_9, Y => \romwidth_1[1]\); - - \r.mcfg1.romrws_RNO_0[0]\ : MX2 - port map(A => \romrws[0]\, B => pwdata_0_0, S => - bexcen_0_sqmuxa, Y => N_5505); - - \r.ws_RNO_1[0]\ : NOR3C - port map(A => \ramwws_m[0]\, B => \romwws_m[0]\, C => - \romrws_m[0]\, Y => \ws_3_iv_1[0]\); - - \r.data_RNI1KB75[20]\ : OR2B - port map(A => \writedata_0_iv_1[20]\, B => - \writedata_4_m[20]\, Y => \writedata[20]\); - - \r.hresp[0]\ : DFN1 - port map(D => \hresp_6[0]\, CLK => lclk_c, Q => hresp(0)); - - \r.bdrive[1]\ : DFN1P0 - port map(D => N_288, CLK => lclk_c, PRE => rstn, Q => - \bdrive[1]\); - - \r.data[14]\ : DFN1 - port map(D => data_in(14), CLK => lclk_c, Q => \hrdata[14]\); - - \r.busw_RNO_2[0]\ : OR2A - port map(A => \ramwidth[0]\, B => iosn_99, Y => - \ramwidth_m[0]\); - - \r.wrn_RNO[1]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => \wrn_90[1]\, C => rstn, - Y => \wrn_RNO[1]\); - - \r.writedata_RNO_3[2]\ : OR2 - port map(A => \hrdata[2]\, B => N_108, Y => - \writedata_1_iv_i_a2_2_0[2]\); - - \r.writedata_RNO_2[27]\ : OR2B - port map(A => \writedata[3]\, B => N_46_i_0, Y => N_184); - - \r.data[21]\ : DFN1 - port map(D => data_in(21), CLK => lclk_c, Q => \hrdata[21]\); - - \r.mcfg2.rambanksz_RNI03O8V4[1]\ : MX2C - port map(A => N_5084, B => N_5106, S => \rambanksz[1]\, Y - => N_5088); - - \r.mcfg1.iows_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5510, Y => N_565); - - \r.brmw_RNI4T2D\ : OR2B - port map(A => \busw[1]\, B => brmw, Y => \brmw_i\); - - \r.mcfg1.ioen_RNI3SCD\ : OR2A - port map(A => \area[1]\, B => \ioen\, Y => N_412); - - \r.writedata_RNO_5[29]\ : OR3B - port map(A => N_425, B => \hrdata[29]\, C => \brmw_i\, Y - => N_552); - - \r.writedata_RNO_0[29]\ : AOI1B - port map(A => writedata_1_sqmuxa, B => hwdata_21, C => - N_555, Y => \writedata_12_iv_0_0_1[29]\); - - \apbo.prdata[21]\ : NOR2A - port map(A => \iows[1]\, B => N_232_0, Y => prdata_1); - - \r.bdrive[2]\ : DFN1P0 - port map(D => N_290, CLK => lclk_c, PRE => rstn, Q => - \bdrive[2]\); - - \r.mcfg2.rambanksz_RNIREJN71[3]\ : MX2 - port map(A => haddr(14), B => haddr(22), S => - \rambanksz[3]\, Y => N_5097); - - \r.mcfg2.rambanksz_RNIE2DGF2[2]\ : MX2C - port map(A => N_5082, B => N_5107, S => \rambanksz[2]\, Y - => N_5084); - - \r.data_RNIE9UH4[0]\ : AO1C - port map(A => \N_6550\, B => \writedata_10[0]\, C => - \writedata_1_iv_0[0]\, Y => \writedata[0]\); - - \r.ready\ : DFN1 - port map(D => ready_RNO, CLK => lclk_c, Q => \hready\); - - \r.ws_RNIVJ8E[1]\ : NOR2 - port map(A => \ws[1]\, B => \ws[2]\, Y => ws_1); - - \r.brmw_RNIG6GD2\ : OR2A - port map(A => hwdata_22, B => N_449, Y => N_633); - - \r.writedata[15]\ : DFN1E1 - port map(D => \writedata[15]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(15)); - - \r.address_RNILT4T[0]\ : OR2B - port map(A => wrn8, B => N_6563, Y => N_439); - - \r.writedata_RNO_1[25]\ : AND2 - port map(A => N_185, B => N_187, Y => - \writedata_12_iv_0_0[25]\); - - \r.mcfg1.iowidth[1]\ : DFN1E1 - port map(D => pwdata_23, CLK => lclk_c, E => - bexcen_0_sqmuxa, Q => \iowidth[1]\); - - \r.writedata[18]\ : DFN1E1 - port map(D => N_62_i_0, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[18]\); - - \r.address[6]\ : DFN1E1 - port map(D => haddr(6), CLK => lclk_c, E => N_36, Q => - address_c(6)); - - \r.bstate_RNIVF4U2[4]\ : OR2B - port map(A => N_610, B => N_438, Y => N_435); - - \r.writedata_RNO_2[29]\ : OR2A - port map(A => \writedata[13]\, B => N_440, Y => N_554); - - \r.busw_RNIERID[0]\ : OA1C - port map(A => \address_c[0]\, B => \busw[0]\, C => - \address_c[1]\, Y => N_636); - - \r.bstate_RNISTTM[4]\ : OR2 - port map(A => ws_1_sqmuxa, B => \bstate[4]\, Y => N_442); - - \r.ramoen[1]\ : DFN1E0P0 - port map(D => \ramoen_1[1]\, CLK => lclk_c, PRE => rstn, E - => ramoen_0_sqmuxa_1, Q => ramoen_c(1)); - - \r.address[17]\ : DFN1E1 - port map(D => haddr(17), CLK => lclk_c, E => N_36_0, Q => - address_c(17)); - - \r.writedata_RNO_0[21]\ : AO1B - port map(A => \writedata_12_0_iv_i_a3_i_2_0_tz_0[21]\, B - => N_420, C => hwdata_21, Y => - \writedata_12_0_iv_i_a3_i_2_0[21]\); - - \r.srhsel_RNO_0\ : NOR3A - port map(A => srhsel, B => N_661, C => ready_0_0_o2_0, Y - => srhsel_RNO_0); - - \r.ws_RNO_1[1]\ : NOR3C - port map(A => \ramwws_m[1]\, B => \romwws_m[1]\, C => - \romrws_m[1]\, Y => \ws_3_iv_1[1]\); - - \r.writedata_RNO_2[31]\ : AO1B - port map(A => hwdata_31, B => \address_RNI96NJ_5[0]\, C => - \writedata_1_iv_0[31]\, Y => \writedata[31]\); - - \r.bstate_RNO_2[5]\ : NOR3B - port map(A => \read_c\, B => N_431, C => \oen_c\, Y => - N_451); - - \r.mcfg1.romwrite_RNO_0\ : MX2 - port map(A => romwrite, B => pwdata_0_11, S => - bexcen_0_sqmuxa, Y => N_5525); - - \r.data[27]\ : DFN1 - port map(D => data_in(27), CLK => lclk_c, Q => \hrdata[27]\); - - \r.address_RNIILPG1[0]\ : OR2B - port map(A => hwdata_10, B => \address_RNI96NJ_3[0]\, Y => - N_6385); - - \r.address[11]\ : DFN1E1 - port map(D => haddr(11), CLK => lclk_c, E => N_36_0, Q => - address_c(11)); - - \r.data[19]\ : DFN1 - port map(D => data_in(19), CLK => lclk_c, Q => \hrdata[19]\); - - \r.data_RNIT72J3[4]\ : OR2B - port map(A => N_550, B => N_549, Y => \writedata[4]\); - - \r.data_RNIGB9B1[18]\ : OR2 - port map(A => \hrdata[18]\, B => N_448, Y => N_160); - - \r.oen_RNIMA801\ : OR2B - port map(A => bstate_2_sqmuxa_1_0, B => N_412, Y => - bstate_2_sqmuxa); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I12_Y_0_0\ : XOR2 - port map(A => \ws[2]\, B => \A_i[0]\, Y => - ADD_4x4_fast_I12_Y_0_0); - - \r.address[12]\ : DFN1E1 - port map(D => haddr(12), CLK => lclk_c, E => N_36_0, Q => - address_c(12)); - - \r.address_RNI96NJ_1[0]\ : OR2A - port map(A => N_126_i, B => \brmw_i\, Y => \N_6377\); - - \r.mcfg2.rambanksz[2]\ : DFN1E1 - port map(D => pwdata_6, CLK => lclk_c, E => rmw_1_sqmuxa, Q - => \rambanksz[2]\); - - \r.writedata_RNO[29]\ : OR3C - port map(A => \writedata_12_iv_0_0_1[29]\, B => - \writedata_12_iv_0_0_0[29]\, C => N_554, Y => - \writedata_12[29]\); - - \r.mcfg1.romrws_RNO[2]\ : OR2A - port map(A => rstn, B => N_5507, Y => \romrws_RNO[2]\); - - \r.writedata_RNO_1[24]\ : NOR3C - port map(A => N_190, B => \writedata_RNO_3[24]\, C => N_193, - Y => \writedata_12_iv_i_1[24]\); - - \r.writedata_RNO_2[21]\ : OR2A - port map(A => hwdata_5, B => N_440, Y => N_543); - - \r.ramoen_RNO_0[0]\ : MX2A - port map(A => \ramsn_c[0]\, B => \ramsn_1[0]\, S => - ramoen_1_sqmuxa_1, Y => N_5176); - - \r.writedata_RNO_0[20]\ : OA1A - port map(A => \data[20]\, B => N_5160, C => - \writedata_m[4]\, Y => \writedata_12_0_iv_0[20]\); - - \r.address[4]\ : DFN1E1 - port map(D => haddr(4), CLK => lclk_c, E => N_36, Q => - address_c(4)); - - \r.wrn_RNO_1[3]\ : OA1B - port map(A => wrn_5_sqmuxa_s6_0_6, B => wrn_5_sqmuxa_s6_0_1, - C => wrn_1_sqmuxa_s2_0_3, Y => N_5197); - - \r.area_RNITSBEJ1[1]\ : AO1C - port map(A => ws, B => address_1_sqmuxa_i_a2_1, C => - srhsel_0_sqmuxa, Y => N_36_0); - - \r.writedata_RNO_2[30]\ : OAI1 - port map(A => N_515, B => N_6564, C => writedata_1_sqmuxa, - Y => \writedata_m_0[22]\); - - \r.mcfg2.rambanksz[3]\ : DFN1E1 - port map(D => pwdata_7, CLK => lclk_c, E => rmw_1_sqmuxa, Q - => \rambanksz[3]\); - - \r.writedata_RNO[17]\ : OR3C - port map(A => N_511, B => N_513, C => - \writedata_12_0_iv_0_0[17]\, Y => \writedata_12[17]\); - - \r.writen_RNO_1\ : OR2B - port map(A => ramoen_0_sqmuxa, B => N_610, Y => - iosn_0_sqmuxa); - - \r.writedata_RNO_3[18]\ : OR2 - port map(A => \data[18]\, B => N_5160, Y => - \writedata_RNO_3[18]\); - - \r.oen_RNO\ : AO1C - port map(A => bstate16_1, B => iosn_1_0, C => - ramoen_2_sqmuxa, Y => ramoen_2_sqmuxa_1); - - \r.mcfg2.rambanksz[0]\ : DFN1E1 - port map(D => pwdata_4, CLK => lclk_c, E => rmw_1_sqmuxa, Q - => \rambanksz[0]\); - - \r.area_RNIBDNE[2]\ : NOR2A - port map(A => rstn, B => rws_1_sqmuxa, Y => N_6457); - - \r.writedata_RNO_3[31]\ : OR2B - port map(A => \writedata[23]\, B => writedata_1_sqmuxa, Y - => \writedata_m_0[23]\); - - \r.writedata_RNO_0[18]\ : NOR2B - port map(A => \writedata_RNO_3[18]\, B => N_160, Y => - \writedata_12_0_iv_i_0[18]\); - - \r.mcfg1.romwws_RNO_0[2]\ : MX2 - port map(A => \romwws[2]\, B => pwdata_0_6, S => - bexcen_0_sqmuxa, Y => N_5503); - - \r.busw_RNIFBBK[1]\ : OR2A - port map(A => \busw[1]\, B => N_424, Y => - wrn_2_sqmuxa_s3_0_6_1); - - \r.bdrive_RNIUBR7[2]\ : INV - port map(A => \bdrive[2]\, Y => bdrive_i(2)); - - \r.bstate_RNIUU6LJA[6]\ : OR2B - port map(A => bstate_4, B => un1_iosn, Y => ramoen_2_sqmuxa); - - \r.address_RNI59K6_2[0]\ : OR2 - port map(A => \address_c[1]\, B => \address_c[0]\, Y => - N_425); - - \r.writedata_RNO[5]\ : MX2 - port map(A => hwdata_5, B => \hrdata[5]\, S => N_671, Y => - \writedata[5]\); - - \r.busw_RNIHOLQ[0]\ : OR2 - port map(A => N_636, B => N_635, Y => N_396); - - \r.address_RNI22O12[0]\ : OR2A - port map(A => hwdata_4, B => N_671, Y => N_549); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I6_Y_0_a3_0\ : NOR2A - port map(A => \ws[1]\, B => \A_i[0]\, Y => N_16); - - \r.busw_RNIHKT36[1]\ : OR2 - port map(A => wrn_2_sqmuxa_s3_0_6_1, B => - writen_0_sqmuxa_1_0, Y => wrn_5_sqmuxa_s6_0_6); - - \r.ramoen[2]\ : DFN1E0P0 - port map(D => \ramoen_1[2]\, CLK => lclk_c, PRE => rstn, E - => ramoen_0_sqmuxa_1, Q => ramoen_c(2)); - - \r.mcfg1.iows[2]\ : DFN1 - port map(D => N_566, CLK => lclk_c, Q => \iows[2]\); - - \r.mcfg1.ioen_RNO\ : NOR2B - port map(A => rstn, B => N_5526, Y => ioen_RNO); - - \r.data_RNIMA2E3[15]\ : OR3C - port map(A => hwdata_m_8, B => \hrdata_m[15]\, C => - hwdata_m_0_3, Y => \writedata[15]\); - - \r.area_RNI3CQR[1]\ : NOR3A - port map(A => ws_1_sqmuxa, B => brmw, C => \area[1]\, Y => - address_1_sqmuxa_i_a2_1); - - \r.mcfg1.iows_RNO_0[0]\ : MX2 - port map(A => \iows[0]\, B => pwdata_15, S => - bexcen_0_sqmuxa, Y => N_5509); - - \r.busw_RNIRPOO3[1]\ : AOI1B - port map(A => N_634, B => N_633, C => \busw[1]\, Y => N_515); - - \v.mcfg1.bexcen_1_sqmuxa_i_i_a2\ : NOR2A - port map(A => rstn, B => bexcen_0_sqmuxa, Y => N_560); - - \r.address_RNI96NJ_3[0]\ : OR2A - port map(A => N_117, B => \brmw_i\, Y => - \address_RNI96NJ_3[0]\); - - \r.brmw\ : DFN1E0 - port map(D => \brmw_1\, CLK => lclk_c, E => srhsel_0_sqmuxa, - Q => brmw); - - \r.writedata_RNO[9]\ : AO1B - port map(A => hwdata_9, B => \address_RNI96NJ_3[0]\, C => - N_152, Y => \writedata[9]\); - - \r.wrn[1]\ : DFN1 - port map(D => \wrn_RNO[1]\, CLK => lclk_c, Q => \rwen_c[1]\); - - \r.writedata_RNO_3[30]\ : AO1B - port map(A => \writedata_1_iv_0[30]\, B => \hwdata_m[30]\, - C => N_123_i, Y => \writedata_m[30]\); - - \r.brmw_RNIDHE9\ : NOR2A - port map(A => \address_c[1]\, B => brmw, Y => N_517); - - \r.ready_RNIFGHB1\ : NOR2A - port map(A => ws_1_sqmuxa, B => ws, Y => ready_0_0_a2_0_1); - - \r.hburst[2]\ : DFN1E1 - port map(D => hburst_0(2), CLK => lclk_c, E => un1_ahbsi_1, - Q => \hburst[2]\); - - \r.writedata[19]\ : DFN1E1 - port map(D => \writedata_12[19]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[19]\); - - \r.mcfg2.rambanksz_RNID3CCF2[2]\ : MX2C - port map(A => N_5107, B => N_5108, S => \rambanksz[2]\, Y - => N_5109); - - \r.mcfg1.brdyen_RNIGD9A1\ : NOR2 - port map(A => ws, B => N_413, Y => ready10); - - \r.writen_RNO_0\ : MX2 - port map(A => \writen_c\, B => iosn_0_sqmuxa, S => N_280, Y - => N_5425); - - \r.read_RNIU1JTC4\ : MX2 - port map(A => hwrite_m_0_0, B => \read_c\, S => - srhsel_0_sqmuxa, Y => read_8_iv_0_tz); - - \r.mcfg1.romrws[2]\ : DFN1 - port map(D => \romrws_RNO[2]\, CLK => lclk_c, Q => - \romrws[2]\); - - \r.bdrive[3]\ : DFN1P0 - port map(D => N_292, CLK => lclk_c, PRE => rstn, Q => - \bdrive[3]\); - - \r.writedata_RNO[26]\ : OR3C - port map(A => \writedata_m[26]\, B => \writedata_m_0[18]\, - C => \writedata_12_iv_0[26]\, Y => \writedata_12[26]\); - - \r.address_RNI96NJ_5[0]\ : OR2A - port map(A => N_425, B => \brmw_i\, Y => - \address_RNI96NJ_5[0]\); - - \r.busw_RNO_1[1]\ : OR2A - port map(A => \ramwidth[1]\, B => iosn_99, Y => - \ramwidth_m[1]\); - - \r.address[5]\ : DFN1E1 - port map(D => haddr(5), CLK => lclk_c, E => N_36, Q => - address_c(5)); - - \r.writedata_RNO_1[22]\ : NOR2B - port map(A => N_6564, B => N_396, Y => N_630); - - \r.mcfg2.ramwws[1]\ : DFN1 - port map(D => N_563, CLK => lclk_c, Q => \ramwws[1]\); - - \r.mcfg2.ramrws_RNO_0[1]\ : MX2 - port map(A => \ramrws[1]\, B => pwdata_1_0, S => - rmw_1_sqmuxa, Y => N_5520); - - \r.ws_RNO_4[0]\ : OR3A - port map(A => \ramwws[0]\, B => N_6458, C => rws_0_sqmuxa, - Y => \ramwws_m[0]\); - - \r.data_RNIM9AT2[1]\ : MX2 - port map(A => hwdata_1, B => \hrdata[1]\, S => N_671, Y => - \writedata[1]\); - - \r.ready_RNIH80F\ : NOR2A - port map(A => \bstate[5]\, B => \hready\, Y => ws_1_sqmuxa); - - \r.ramsn_RNO[3]\ : OR2 - port map(A => srhsel_0_sqmuxa, B => \ramsn_1[3]\, Y => - \ramsn_1_0[3]\); - - \r.data[16]\ : DFN1 - port map(D => data_in(16), CLK => lclk_c, Q => \hrdata[16]\); - - \v.mcfg2.rmw_1_sqmuxa_0_a2\ : NOR2 - port map(A => psel(0), B => N_6459, Y => rmw_1_sqmuxa); - - \r.writedata[11]\ : DFN1E1 - port map(D => \writedata[11]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(11)); - - \r.wrn_RNO_2[0]\ : MX2 - port map(A => \address_c[1]\, B => \rwen_c[0]\, S => N_6549, - Y => N_5200); - - \r.mcfg1.romwrite\ : DFN1 - port map(D => romwrite_RNO, CLK => lclk_c, Q => romwrite); - - \v.mcfg1.bexcen_0_sqmuxa_0_a2\ : NOR3A - port map(A => bexcen_0_sqmuxa_0_a2_0, B => psel(0), C => - N_232_0, Y => bexcen_0_sqmuxa); - - \r.area[1]\ : DFN1E0 - port map(D => iosn_1_8, CLK => lclk_c, E => srhsel_0_sqmuxa, - Q => \area[1]\); - - \r.busw_RNO_2[1]\ : OR3C - port map(A => iosn_99, B => \romwidth[1]\, C => iosn_100, Y - => \romwidth_m[1]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.address_RNIN3DG_0[1]\ : NOR2A - port map(A => \address_c[1]\, B => \brmw_i\, Y => - N_6555_i_0); - - \r.ramsn[3]\ : DFN1E0P0 - port map(D => \ramsn_1_0[3]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => \ramsn_c[3]\); - - \r.romsn_RNO[0]\ : OR3 - port map(A => hmbsel(0), B => - \un1_romsn_0_sqmuxa_1_0[0]_net_1\, C => haddr(28), Y => - \romsn_1[0]\); - - \r.mcfg1.romwidth[0]\ : DFN1E0 - port map(D => N_6539, CLK => lclk_c, E => N_560, Q => - \romwidth[0]\); - - \r.wrn[3]\ : DFN1 - port map(D => \wrn_RNO[3]\, CLK => lclk_c, Q => \rwen_c[3]\); - - \r.mcfg1.romwws[0]\ : DFN1 - port map(D => \romwws_RNO[0]\, CLK => lclk_c, Q => - \romwws[0]\); - - \r.data_RNI5HC72[20]\ : OR2B - port map(A => \writedata_4_m_0[20]\, B => \writedata_4[20]\, - Y => \writedata_4_m[20]\); - - \r.writedata_RNO_6[26]\ : OR2A - port map(A => \writedata[10]\, B => N_440, Y => - \writedata_m[10]\); - - \r.bstate_RNO[6]\ : NOR2A - port map(A => N_6565, B => N_446, Y => \bstate_RNO[6]\); - - \r.writedata_RNO_5[28]\ : OR2B - port map(A => hwdata_28, B => \address_RNI96NJ_5[0]\, Y => - \hwdata_m[28]\); - - \r.writedata_RNO_0[28]\ : AOI1B - port map(A => \writedata[4]\, B => N_46_i_0, C => - \writedata_m[28]\, Y => \writedata_12_iv_0[28]\); - - \r.mcfg1.romwrite_RNIGG9C\ : MX2 - port map(A => romwrite, B => \rambanksz[2]\, S => - paddr_2(2), Y => N_5070); - - \r.data_RNIOMNK[10]\ : OR2A - port map(A => \hrdata[10]\, B => \address_RNI96NJ_3[0]\, Y - => N_112); - - \r.bdrive[0]\ : DFN1P0 - port map(D => N_286, CLK => lclk_c, PRE => rstn, Q => - \bdrive[0]\); - - \r.oen_RNO_0\ : OA1C - port map(A => iosn_1_8, B => un18_srhsel, C => bstate16, Y - => bstate16_1); - - \r.data[24]\ : DFN1 - port map(D => data_in(24), CLK => lclk_c, Q => \hrdata[24]\); - - \r.mcfg1.romrws_RNO_0[3]\ : MX2 - port map(A => \romrws[3]\, B => pwdata_1_2, S => - bexcen_0_sqmuxa, Y => N_5508); - - \r.ws[0]\ : DFN1 - port map(D => \ws_RNO[0]\, CLK => lclk_c, Q => \ws[0]\); - - \r.bstate_RNI3PAI2[4]\ : OR2 - port map(A => \A_i[0]\, B => N_442, Y => bstate_3); - - \r.writedata_RNO_2[16]\ : OR2A - port map(A => \writedata[0]\, B => N_440, Y => N_531); - - \r.mcfg1.ioen\ : DFN1 - port map(D => ioen_RNO, CLK => lclk_c, Q => \ioen\); - - \r.bstate_RNI2VCTKA[6]\ : NOR3A - port map(A => un1_iosn, B => bstate_4, C => oen_1_sqmuxa, Y - => ramoen_0_sqmuxa_1); - - \r.data[30]\ : DFN1 - port map(D => data_in(30), CLK => lclk_c, Q => \hrdata[30]\); - - \r.read_RNICG8E\ : OR2A - port map(A => \bstate[7]\, B => \read_c\, Y => N_6458); - - \r.writedata[5]\ : DFN1E1 - port map(D => \writedata[5]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(5)); - - \r.data_RNI0U404[3]\ : OR2B - port map(A => N_507, B => N_506, Y => \writedata[3]\); - - \r.data[0]\ : DFN1 - port map(D => data_in(0), CLK => lclk_c, Q => \hrdata[0]\); - - \r.wrn_RNO_3[2]\ : OR3A - port map(A => N_394, B => wrn35, C => wrn_4_sqmuxa_s5_0_0, - Y => wrn_4_sqmuxa_s5_0_1); - - \r.wrn_RNO_3[1]\ : OR3A - port map(A => N_394, B => wrn35, C => wrn_3_sqmuxa_s4_0_0, - Y => wrn_3_sqmuxa_s4_0_1); - - \r.writedata_RNO_2[28]\ : OR2B - port map(A => \writedata[20]\, B => writedata_1_sqmuxa, Y - => \writedata_m_0[20]\); - - \r.writedata[2]\ : DFN1E1 - port map(D => N_45, CLK => lclk_c, E => writedata_0_sqmuxa, - Q => data(2)); - - \r.writedata[24]\ : DFN1E1 - port map(D => N_82_i_0, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(24)); - - \r.address_RNIN3DG[1]\ : OR2 - port map(A => \brmw_i\, B => \address_c[1]\, Y => N_5112); - - \r.hwrite_RNI420DN6\ : MX2B - port map(A => hwrite_0, B => read_8_iv_0_tz, S => - iosn_0_sqmuxa_1, Y => un18_srhsel); - - \r.mcfg2.rambanksz_RNI5JCIU9[0]\ : MX2C - port map(A => N_5103, B => N_5110, S => \rambanksz[0]\, Y - => \adec_2[1]\); - - \apbo.prdata[20]\ : NOR2A - port map(A => \iows[0]\, B => N_232_0, Y => prdata_0); - - \r.bstate_RNO[5]\ : NOR3 - port map(A => N_616, B => N_617, C => N_446, Y => N_295); - - \r.bdrive_RNIVBR7[3]\ : INV - port map(A => \bdrive[3]\, Y => bdrive_i(3)); - - \r.data[5]\ : DFN1 - port map(D => data_in(5), CLK => lclk_c, Q => \hrdata[5]\); - - \r.bstate_RNI8O4Q1[6]\ : OR2A - port map(A => N_610, B => \bstate[6]\, Y => N_419); - - \r.bstate_RNIB9DGA2[5]\ : AO1C - port map(A => brmw, B => bstate_0_sqmuxa, C => \bstate[5]\, - Y => romsn_1_sqmuxa); - - \r.address[1]\ : DFN1E1 - port map(D => haddr(1), CLK => lclk_c, E => N_36_0, Q => - \address_c[1]\); - - \ctrl.v.bstate16\ : OR2A - port map(A => htrans(1), B => hsel_i(0), Y => bstate16); - - \r.data[13]\ : DFN1 - port map(D => data_in(13), CLK => lclk_c, Q => \hrdata[13]\); - - \r.writedata_RNO_0[23]\ : AOI1B - port map(A => \writedata[23]\, B => N_123_i, C => - \data_m[23]\, Y => \writedata_12_0_iv_0[23]\); - - \r.ws_RNO_0[1]\ : NOR3C - port map(A => \ws_3_iv_1[1]\, B => \ramrws_m[1]\, C => - \iows_m[1]\, Y => \ws_3_iv_3[1]\); - - \r.mcfg1.brdyen\ : DFN1 - port map(D => brdyen_RNO, CLK => lclk_c, Q => \brdyen\); - - un1_wsnew_0_sqmuxa_RNI8N8F : OA1 - port map(A => \bstate[7]\, B => \un1_wsnew_0_sqmuxa\, C => - \area[1]\, Y => un1_rws_0_sqmuxa); - - \r.writedata[17]\ : DFN1E1 - port map(D => \writedata_12[17]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[17]\); - - \v.ws_0_sqmuxa\ : NAND2 - port map(A => \hready\, B => \bstate[5]\, Y => ws_0_sqmuxa); - - \r.ramsn_RNO[2]\ : OR2 - port map(A => srhsel_0_sqmuxa, B => \ramsn_1[2]\, Y => - \ramsn_1_0[2]\); - - \r.ws_RNO_0[3]\ : OR3C - port map(A => rstn, B => un1_rws_0_sqmuxa, C => \iows[3]\, - Y => N_6448); - - \r.data[18]\ : DFN1 - port map(D => data_in(18), CLK => lclk_c, Q => \hrdata[18]\); - - \r.writedata[20]\ : DFN1E1 - port map(D => \writedata_12[20]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[20]\); - - \r.size_RNILTQM[0]\ : NOR3B - port map(A => \size[0]\, B => \busw[1]\, C => \size[1]\, Y - => wrn_6_sqmuxa_0_i_1); - - \ctrl.un1_ahbsi_1\ : NOR2A - port map(A => iosn_1_0, B => hsel_i(0), Y => un1_ahbsi_1); - - \r.mcfg1.romrws[3]\ : DFN1 - port map(D => \romrws_RNO[3]\, CLK => lclk_c, Q => - \romrws[3]\); - - \r.bstate_RNO_0[4]\ : NOR2A - port map(A => iosn_1_sqmuxa, B => \bstate[4]\, Y => N_619); - - \r.ws_RNO_2[3]\ : AOI1B - port map(A => \ws_0_0_a2_0[3]\, B => rstn, C => N_6449, Y - => \ws_0_0_0[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.area_RNIG8VG82[1]\ : NOR3B - port map(A => ramoen10_i_a2_1, B => htrans(1), C => - hsel_i(0), Y => N_195); - - \r.wrn_RNO[0]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => \wrn_90[0]\, C => rstn, - Y => \wrn_RNO[0]\); - - \r.writedata_RNO_2[17]\ : OA1A - port map(A => hwdata_1, B => N_440, C => N_514, Y => - \writedata_12_0_iv_0_0[17]\); - - \r.data[29]\ : DFN1 - port map(D => data_in(29), CLK => lclk_c, Q => \hrdata[29]\); - - \r.address_RNI59K6_0[0]\ : OR2A - port map(A => \address_c[1]\, B => \address_c[0]\, Y => - N_117); - - \r.mcfg1.iows_RNO_0[1]\ : MX2 - port map(A => \iows[1]\, B => pwdata_16, S => - bexcen_0_sqmuxa, Y => N_5510); - - \r.ws[3]\ : DFN1 - port map(D => \ws_RNO[3]\, CLK => lclk_c, Q => \ws[3]\); - - \r.mcfg1.brdyen_RNO_0\ : MX2 - port map(A => \brdyen\, B => pwdata_21, S => - bexcen_0_sqmuxa, Y => N_5527); - - \r.address[8]\ : DFN1E1 - port map(D => haddr(8), CLK => lclk_c, E => N_36, Q => - address_c(8)); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I8_Y_0_a2_0\ : NOR2A - port map(A => \ws[2]\, B => \A_i[0]\, Y => N_14); - - \r.address[3]\ : DFN1E1 - port map(D => haddr(3), CLK => lclk_c, E => N_36, Q => - address_c(3)); - - \r.ws_RNO_1[3]\ : OR3B - port map(A => \romwws[3]\, B => N_6457, C => N_6458, Y => - N_6450); - - \r.bdrive_RNO[2]\ : OA1C - port map(A => N_6568_i_0, B => \bdrive[2]\, C => N_6567_i_0, - Y => N_290); - - \r.ws_RNO[0]\ : AOI1B - port map(A => \ws_3_iv_3[0]\, B => \ws_1_sqmuxa_2_m[3]\, C - => rstn, Y => \ws_RNO[0]\); - - \r.address_RNIODHK[1]\ : NOR2A - port map(A => \address_c[1]\, B => N_5160, Y => N_46_i_0); - - \r.writedata_RNO[2]\ : NOR3 - port map(A => N_149, B => \writedata_1_iv_i_0[2]\, C => - N_148, Y => N_45); - - \r.writedata_RNO_4[31]\ : OAI1 - port map(A => N_6555_i_0, B => N_38_i, C => \hrdata[31]\, Y - => \writedata_1_iv_0[31]\); - - \r.bstate_RNIQ5FJ1[4]\ : OR2A - port map(A => N_442, B => ws, Y => N_500); - - \r.writedata_RNO_1[31]\ : AOI1B - port map(A => \writedata[31]\, B => N_123_i, C => - \writedata_m_0[23]\, Y => \writedata_12_iv_0[31]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.address_RNIGKGM[0]\ : NOR2 - port map(A => N_394, B => N_117, Y => N_649); - - \r.address_RNIODHK_0[1]\ : NOR2 - port map(A => \address_c[1]\, B => N_5160, Y => - writedata_1_sqmuxa); - - \r.writedata_RNO[27]\ : OR3C - port map(A => \writedata_12_iv_0_1[27]\, B => N_183, C => - N_184, Y => \writedata_12[27]\); - - \r.data_RNIQ5AH1[3]\ : OR2B - port map(A => \hrdata[3]\, B => N_671, Y => N_507); - - \r.mcfg1.iows[1]\ : DFN1 - port map(D => N_565, CLK => lclk_c, Q => \iows[1]\); - - \r.ws_RNO_2[1]\ : OR3B - port map(A => \un1_wsnew_0_sqmuxa\, B => \ramrws[1]\, C => - rws_0_sqmuxa, Y => \ramrws_m[1]\); - - \r.writedata_RNO_2[19]\ : OR2A - port map(A => \writedata[3]\, B => N_440, Y => - \writedata_m[3]\); - - \r.writedata_RNO[24]\ : OA1A - port map(A => N_46_i_0, B => \writedata[0]\, C => - \writedata_12_iv_i_2[24]\, Y => N_82_i_0); - - \v.srhsel_0_sqmuxa\ : OR2B - port map(A => un1_ahbsi_1, B => htrans(1), Y => - srhsel_0_sqmuxa); - - \r.busw_RNIJ4TD[0]\ : OR2A - port map(A => \busw[0]\, B => \busw[1]\, Y => - \writedata_12_0_iv_i_a2_4_0[18]\); - - \r.data[6]\ : DFN1 - port map(D => data_in(6), CLK => lclk_c, Q => \hrdata[6]\); - - \r.mcfg2.rambanksz_RNIQOSI71[3]\ : MX2 - port map(A => haddr(16), B => haddr(24), S => - \rambanksz[3]\, Y => N_5100); - - \r.mcfg1.romrws_RNO_0[2]\ : MX2 - port map(A => \romrws[2]\, B => pwdata_0_2, S => - bexcen_0_sqmuxa, Y => N_5507); - - \r.data[12]\ : DFN1 - port map(D => data_in(12), CLK => lclk_c, Q => \hrdata[12]\); - - \r.data[10]\ : DFN1 - port map(D => data_in(10), CLK => lclk_c, Q => \hrdata[10]\); - - \r.bstate_RNO[4]\ : NOR3 - port map(A => N_619, B => N_618, C => N_446, Y => N_297); - - \r.bstate_RNIUJ6IA2[6]\ : OR2A - port map(A => iosn_0_sqmuxa_1, B => \bstate[6]\, Y => - bstate_4); - - \r.brmw_RNIN9ELJ1\ : NOR3C - port map(A => ready_0_0_a2_0_1, B => ready_0_0_a2_0_0, C - => ramoen_0_sqmuxa, Y => N_661); - - \r.writedata_RNO_4[30]\ : OAI1 - port map(A => N_6555_i_0, B => N_38_i, C => \hrdata[30]\, Y - => \writedata_1_iv_0[30]\); - - \r.writedata_RNO_1[2]\ : AO1D - port map(A => \writedata_1_iv_i_a2_2_0[2]\, B => \brmw_i\, - C => N_150, Y => \writedata_1_iv_i_0[2]\); - - \r.wrn_RNO_4[1]\ : OR2 - port map(A => wrn8, B => N_6547, Y => wrn_3_sqmuxa_s4_0_0); - - \r.bstate_RNI755AD2[4]\ : OR2B - port map(A => iosn_1_sqmuxa_1, B => iosn_1_sqmuxa_1_0, Y - => iosn_1_sqmuxa); - - \r.address[24]\ : DFN1E1 - port map(D => haddr(24), CLK => lclk_c, E => N_36, Q => - address_c(24)); - - \r.writedata_RNO_1[30]\ : AOI1B - port map(A => \writedata[6]\, B => N_46_i_0, C => - \writedata_m[30]\, Y => \writedata_12_iv_0[30]\); - - \r.iosn[1]\ : DFN1P0 - port map(D => \iosn_1_iv[1]\, CLK => lclk_c, PRE => rstn, Q - => \iosn[1]\); - - \r.hburst[0]\ : DFN1E1 - port map(D => hburst_0(0), CLK => lclk_c, E => un1_ahbsi_1, - Q => \hburst[0]\); - - \r.address_RNI9S2B1[0]\ : OR2B - port map(A => N_425, B => N_106, Y => N_111); - - \r.wrn_RNO_2[1]\ : MX2 - port map(A => \address_c[1]\, B => \rwen_c[1]\, S => N_6549, - Y => N_5201); - - \r.bstate_RNIGNR772[6]\ : MX2A - port map(A => hsel_i(0), B => N_419, S => ramoen_0_sqmuxa, - Y => ready_0_0_o2_0); - - \r.mcfg2.rambanksz_RNIHKCBF2[2]\ : MX2C - port map(A => N_5097, B => N_5098, S => \rambanksz[2]\, Y - => N_5091); - - \r.writedata_RNO_0[25]\ : NOR3C - port map(A => \writedata_12_iv_0_0[25]\, B => N_186, C => - N_188, Y => \writedata_12_iv_0_2[25]\); - - \r.area_RNI4DTB1_0[0]\ : OR2B - port map(A => hresp2_i_0, B => N_431, Y => N_438); - - \r.mcfg2.ramwws_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5518, Y => N_563); - - \r.writedata[22]\ : DFN1E1 - port map(D => N_308, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[22]\); - - \r.wrn_RNO_4[2]\ : OR2 - port map(A => N_117, B => N_6547, Y => wrn_4_sqmuxa_s5_0_0); - - \r.bstate_RNI8E2SK1_0[6]\ : NOR3A - port map(A => ramoen_0_sqmuxa, B => N_419, C => N_6565, Y - => N_6568_i_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity grgpio is - - port( un1_grgpio0_7 : out std_logic; - un1_grgpio0_5 : out std_logic; - gpio_in : in std_logic_vector(7 downto 0); - pwdata_i : in std_logic_vector(7 downto 0); - paddr : in std_logic_vector(5 downto 2); - readdata_2_m : out std_logic_vector(5 to 5); - pwdata_1_0 : in std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - pwdata_0_5 : in std_logic; - pwdata_0_7 : in std_logic; - pwdata_0_6 : in std_logic; - pwdata_0_2 : in std_logic; - pwdata_0_0 : in std_logic; - dout : out std_logic_vector(7 downto 0); - psel : in std_logic_vector(11 to 11); - prdata_iv_0_0_d0 : out std_logic; - prdata_iv_0_2 : out std_logic; - prdata_iv_0_0 : out std_logic_vector(2 to 2); - oen_7 : out std_logic; - oen_i : out std_logic_vector(7 downto 0); - paddr_0 : in std_logic_vector(3 downto 2); - lclk_c : in std_logic; - N_232_2 : out std_logic; - rdata61_2 : out std_logic; - N_6432 : out std_logic; - rstn : in std_logic; - N_6439 : out std_logic; - N_6437 : out std_logic; - N_6436 : out std_logic; - N_6435 : out std_logic; - N_6434 : out std_logic; - rdata60_4 : in std_logic; - N_6430 : out std_logic; - rdata59_4 : in std_logic; - N_6429 : out std_logic; - N_6428 : out std_logic; - N_6459 : out std_logic; - readdata55_3 : in std_logic; - un1_apbi_0 : in std_logic; - rdata60_4_0 : in std_logic; - N_232_0 : out std_logic; - N_232_1 : out std_logic - ); - -end grgpio; - -architecture DEF_ARCH of grgpio is - - component DFN1E1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \oen[4]\, \oen[5]\, \oen[6]\, \oen[0]\, \oen[1]\, - \oen[2]\, \oen[3]\, N_6431, \un1_grgpio0_m[67]\, - \un1_grgpio0_m[65]\, dir_1_sqmuxa, N_5412, dout_1_sqmuxa, - N_5414, N_5415, N_5416, N_5418, N_5419, \un1_grgpio0[65]\, - \un1_grgpio0[64]\, \dout[0]\, \un1_grgpio0[68]\, - \dout[4]\, \un1_grgpio0[70]\, \N_6459\, N_87, N_90, N_224, - N_228, N_230, N_232, \dout[2]\, \un1_grgpio0[66]\, - \un1_grgpio0[67]\, N_234, N_5417, N_226, N_5413, - \dout[1]\, \dout[3]\, \dout[5]\, \dout[6]\, \dout[7]\, - \oen[7]\, \din1[0]\, \din1[1]\, \din1[2]\, \din1[3]\, - \din1[4]\, \din1[5]\, \din1[6]\, \din1[7]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - dout(7) <= \dout[7]\; - dout(6) <= \dout[6]\; - dout(5) <= \dout[5]\; - dout(4) <= \dout[4]\; - dout(3) <= \dout[3]\; - dout(2) <= \dout[2]\; - dout(1) <= \dout[1]\; - dout(0) <= \dout[0]\; - oen_7 <= \oen[7]\; - N_6459 <= \N_6459\; - - \r.dir[3]\ : DFN1E1P0 - port map(D => pwdata_i(3), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[3]\); - - \r.din2[3]\ : DFN1 - port map(D => \din1[3]\, CLK => lclk_c, Q => - \un1_grgpio0[67]\); - - \r.dout_RNO[5]\ : NOR2B - port map(A => rstn, B => N_5417, Y => N_234); - - \r.din2_RNICS37[6]\ : OR2A - port map(A => \un1_grgpio0[70]\, B => readdata55_3, Y => - N_6437); - - \r.dout_RNIHH6A[2]\ : OR2B - port map(A => rdata59_4, B => \dout[2]\, Y => N_6432); - - \v.dout_1_sqmuxa_0_a2\ : NOR2 - port map(A => psel(11), B => \N_6459\, Y => dout_1_sqmuxa); - - \r.dout_RNO_0[6]\ : MX2 - port map(A => \dout[6]\, B => pwdata_0_6, S => - dout_1_sqmuxa, Y => N_5418); - - \r.din2_RNI6S37[0]\ : OR2A - port map(A => \un1_grgpio0[64]\, B => readdata55_3, Y => - N_6428); - - \r.dir_RNICB4G[2]\ : OA1 - port map(A => \oen[2]\, B => rdata60_4_0, C => N_6431, Y - => prdata_iv_0_0(2)); - - \r.dir_RNIIA8[6]\ : INV - port map(A => \oen[6]\, Y => oen_i(6)); - - \r.dir[6]\ : DFN1E1P0 - port map(D => pwdata_i(6), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[6]\); - - \r.dir[5]\ : DFN1E1P0 - port map(D => pwdata_i(5), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[5]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.dout[4]\ : DFN1 - port map(D => N_232, CLK => lclk_c, Q => \dout[4]\); - - \r.dout_RNO[7]\ : NOR2B - port map(A => rstn, B => N_5419, Y => N_90); - - \r.dout_RNO[6]\ : NOR2B - port map(A => rstn, B => N_5418, Y => N_87); - - \r.dout_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5413, Y => N_226); - - \r.dout[0]\ : DFN1 - port map(D => N_224, CLK => lclk_c, Q => \dout[0]\); - - \r.dir_RNIJE8[7]\ : INV - port map(A => \oen[7]\, Y => oen_i(7)); - - \r.din2[7]\ : DFN1 - port map(D => \din1[7]\, CLK => lclk_c, Q => un1_grgpio0_7); - - \r.din1[0]\ : DFN1 - port map(D => gpio_in(0), CLK => lclk_c, Q => \din1[0]\); - - \r.dir_RNI7R09[5]\ : OR2 - port map(A => rdata60_4, B => \oen[5]\, Y => - readdata_2_m(5)); - - \r.din2[2]\ : DFN1 - port map(D => \din1[2]\, CLK => lclk_c, Q => - \un1_grgpio0[66]\); - - \r.dout[7]\ : DFN1 - port map(D => N_90, CLK => lclk_c, Q => \dout[7]\); - - \r.dir[4]\ : DFN1E1P0 - port map(D => pwdata_i(4), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[4]\); - - \r.din2[0]\ : DFN1 - port map(D => \din1[0]\, CLK => lclk_c, Q => - \un1_grgpio0[64]\); - - \r.dout[5]\ : DFN1 - port map(D => N_234, CLK => lclk_c, Q => \dout[5]\); - - \r.dir[0]\ : DFN1E1P0 - port map(D => pwdata_i(0), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[0]\); - - \r.dout_RNO_0[5]\ : MX2 - port map(A => \dout[5]\, B => pwdata_0_5, S => - dout_1_sqmuxa, Y => N_5417); - - \r.dout_RNO[3]\ : NOR2B - port map(A => rstn, B => N_5415, Y => N_230); - - \r.dout_RNO[0]\ : NOR2B - port map(A => rstn, B => N_5412, Y => N_224); - - \r.dir[7]\ : DFN1E1P0 - port map(D => pwdata_i(7), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[7]\); - - \r.dout_RNO_0[1]\ : MX2 - port map(A => \dout[1]\, B => pwdata_1_0, S => - dout_1_sqmuxa, Y => N_5413); - - \r.din1[7]\ : DFN1 - port map(D => gpio_in(7), CLK => lclk_c, Q => \din1[7]\); - - \r.dir_RNI2709[0]\ : OR2 - port map(A => rdata60_4, B => \oen[0]\, Y => N_6430); - - \r.dir_RNICI7[0]\ : INV - port map(A => \oen[0]\, Y => oen_i(0)); - - \comb.readdata16_0_a2_0\ : OR2 - port map(A => paddr(5), B => paddr(4), Y => rdata61_2); - - \r.dout_RNO[4]\ : NOR2B - port map(A => rstn, B => N_5416, Y => N_232); - - \r.dir[2]\ : DFN1E1P0 - port map(D => pwdata_i(2), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[2]\); - - \r.dout[3]\ : DFN1 - port map(D => N_230, CLK => lclk_c, Q => \dout[3]\); - - GND_i : GND - port map(Y => \GND\); - - \r.dir_RNIDM7[1]\ : INV - port map(A => \oen[1]\, Y => oen_i(1)); - - \r.din1[4]\ : DFN1 - port map(D => gpio_in(4), CLK => lclk_c, Q => \din1[4]\); - - \r.dout_RNO_0[0]\ : MX2 - port map(A => \dout[0]\, B => pwdata_0_0, S => - dout_1_sqmuxa, Y => N_5412); - - \r.dout[1]\ : DFN1 - port map(D => N_226, CLK => lclk_c, Q => \dout[1]\); - - \r.dir_RNIEF4G[3]\ : OA1 - port map(A => \oen[3]\, B => rdata60_4_0, C => - \un1_grgpio0_m[67]\, Y => prdata_iv_0_2); - - \r.dir_RNI8V09[6]\ : OR2 - port map(A => rdata60_4, B => \oen[6]\, Y => N_6439); - - \r.dir[1]\ : DFN1E1P0 - port map(D => pwdata_i(1), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[1]\); - - \r.din2_RNI8S37[2]\ : OR2A - port map(A => \un1_grgpio0[66]\, B => readdata55_3, Y => - N_6431); - - \comb.readdata15_1_0\ : OR2 - port map(A => paddr_0(3), B => paddr_0(2), Y => N_232_0); - - \r.din2_RNI7S37[1]\ : OR2A - port map(A => \un1_grgpio0[65]\, B => readdata55_3, Y => - \un1_grgpio0_m[65]\); - - \r.din1[2]\ : DFN1 - port map(D => gpio_in(2), CLK => lclk_c, Q => \din1[2]\); - - \r.din2_RNI9S37[3]\ : OR2A - port map(A => \un1_grgpio0[67]\, B => readdata55_3, Y => - \un1_grgpio0_m[67]\); - - \r.din2[4]\ : DFN1 - port map(D => \din1[4]\, CLK => lclk_c, Q => - \un1_grgpio0[68]\); - - \r.dir_RNIEQ7[2]\ : INV - port map(A => \oen[2]\, Y => oen_i(2)); - - \r.din1[1]\ : DFN1 - port map(D => gpio_in(1), CLK => lclk_c, Q => \din1[1]\); - - \r.din1[3]\ : DFN1 - port map(D => gpio_in(3), CLK => lclk_c, Q => \din1[3]\); - - \r.dout_RNO_0[7]\ : MX2 - port map(A => \dout[7]\, B => pwdata_0_7, S => - dout_1_sqmuxa, Y => N_5419); - - \r.dout_RNIFH6A[0]\ : OR2B - port map(A => rdata59_4, B => \dout[0]\, Y => N_6429); - - \r.dout_RNO_0[2]\ : MX2 - port map(A => \dout[2]\, B => pwdata_0_2, S => - dout_1_sqmuxa, Y => N_5414); - - \r.dir_RNIA74G[1]\ : OA1 - port map(A => \oen[1]\, B => rdata60_4_0, C => - \un1_grgpio0_m[65]\, Y => prdata_iv_0_0_d0); - - \r.dout_RNO[2]\ : NOR2B - port map(A => rstn, B => N_5414, Y => N_228); - - \v.dout_1_sqmuxa_0_a2_0\ : OR2A - port map(A => rdata59_4, B => un1_apbi_0, Y => \N_6459\); - - \r.din2_RNIAS37[4]\ : OR2A - port map(A => \un1_grgpio0[68]\, B => readdata55_3, Y => - N_6434); - - \r.din1[6]\ : DFN1 - port map(D => gpio_in(6), CLK => lclk_c, Q => \din1[6]\); - - \r.dir_RNI6N09[4]\ : OR2 - port map(A => rdata60_4, B => \oen[4]\, Y => N_6436); - - \r.din2[6]\ : DFN1 - port map(D => \din1[6]\, CLK => lclk_c, Q => - \un1_grgpio0[70]\); - - \v.dir_1_sqmuxa_0_a2\ : NOR3 - port map(A => psel(11), B => un1_apbi_0, C => rdata60_4_0, - Y => dir_1_sqmuxa); - - \r.dout[6]\ : DFN1 - port map(D => N_87, CLK => lclk_c, Q => \dout[6]\); - - \r.dir_RNIG28[4]\ : INV - port map(A => \oen[4]\, Y => oen_i(4)); - - \comb.readdata15_1\ : OR2 - port map(A => paddr(3), B => paddr(2), Y => N_232_2); - - \r.din2[5]\ : DFN1 - port map(D => \din1[5]\, CLK => lclk_c, Q => un1_grgpio0_5); - - \r.dout_RNO_0[3]\ : MX2 - port map(A => \dout[3]\, B => pwdata_1_2, S => - dout_1_sqmuxa, Y => N_5415); - - \r.dout[2]\ : DFN1 - port map(D => N_228, CLK => lclk_c, Q => \dout[2]\); - - \r.dout_RNO_0[4]\ : MX2 - port map(A => \dout[4]\, B => pwdata_1_3, S => - dout_1_sqmuxa, Y => N_5416); - - \r.dout_RNIJH6A[4]\ : OR2B - port map(A => rdata59_4, B => \dout[4]\, Y => N_6435); - - \r.din1[5]\ : DFN1 - port map(D => gpio_in(5), CLK => lclk_c, Q => \din1[5]\); - - \comb.readdata15_1_1\ : OR2 - port map(A => paddr_0(3), B => paddr_0(2), Y => N_232_1); - - \r.dir_RNIH68[5]\ : INV - port map(A => \oen[5]\, Y => oen_i(5)); - - \r.dir_RNIFU7[3]\ : INV - port map(A => \oen[3]\, Y => oen_i(3)); - - \r.din2[1]\ : DFN1 - port map(D => \din1[1]\, CLK => lclk_c, Q => - \un1_grgpio0[65]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity leon3mp_wfp is - - port( resetn : in std_logic; - clk : in std_logic; - pllref : in std_logic; - errorn : out std_logic; - address : out std_logic_vector(27 downto 0); - data : inout std_logic_vector(31 downto 0) := (others => 'Z'); - dsutx : out std_logic; - dsurx : in std_logic; - dsuen : in std_logic; - dsubre : in std_logic; - dsuact : out std_logic; - txd1 : out std_logic; - rxd1 : in std_logic; - txd2 : out std_logic; - rxd2 : in std_logic; - ramsn : out std_logic_vector(4 downto 0); - ramoen : out std_logic_vector(4 downto 0); - rwen : out std_logic_vector(3 downto 0); - oen : out std_logic; - writen : out std_logic; - read : out std_logic; - iosn : out std_logic; - romsn : out std_logic_vector(1 downto 0); - gpio : inout std_logic_vector(7 downto 0) := (others => 'Z'); - emddis : out std_logic; - epwrdwn : out std_logic; - ereset : out std_logic; - esleep : out std_logic; - epause : out std_logic; - pci_rst : out std_logic; - pci_clk : in std_logic; - pci_gnt : in std_logic; - pci_idsel : in std_logic; - pci_lock : out std_logic; - pci_ad : out std_logic_vector(31 downto 0); - pci_cbe : out std_logic_vector(3 downto 0); - pci_frame : out std_logic; - pci_irdy : out std_logic; - pci_trdy : out std_logic; - pci_devsel : out std_logic; - pci_stop : out std_logic; - pci_perr : out std_logic; - pci_par : out std_logic; - pci_req : out std_logic; - pci_serr : out std_logic; - pci_host : in std_logic; - pci_66 : in std_logic; - pci_arb_req : in std_logic_vector(0 to 3); - pci_arb_gnt : out std_logic_vector(0 to 3); - spw_clk : in std_logic; - spw_rxd : in std_logic_vector(0 to 2); - spw_rxdn : in std_logic_vector(0 to 2); - spw_rxs : in std_logic_vector(0 to 2); - spw_rxsn : in std_logic_vector(0 to 2); - spw_txd : out std_logic_vector(0 to 2); - spw_txdn : out std_logic_vector(0 to 2); - spw_txs : out std_logic_vector(0 to 2); - spw_txsn : out std_logic_vector(0 to 2); - ramclk : out std_logic; - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; - tck : in std_logic; - tms : in std_logic; - tdi : in std_logic; - tdo : out std_logic; - clk49_152MHz : in std_logic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic - ); - -end leon3mp_wfp; - -architecture DEF_ARCH of leon3mp_wfp is - - component OUTBUF - port( D : in std_logic := 'U'; - PAD : out std_logic - ); - end component; - - component BIBUF - port( PAD : inout std_logic; - D : in std_logic := 'U'; - E : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component gptimer - port( scaler_4 : out std_logic; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - paddr : in std_logic_vector(6 downto 2) := (others => 'U'); - value_6 : out std_logic; - value_0 : out std_logic; - paddr_2 : in std_logic_vector(2 to 2) := (others => 'U'); - pirq : out std_logic_vector(9 downto 8); - readdata_9_5 : out std_logic; - readdata_9_0 : out std_logic; - readdata_9_27 : out std_logic; - readdata_9_4 : out std_logic; - paddr_1 : in std_logic_vector(2 to 2) := (others => 'U'); - reload_RNIRDRG : out std_logic_vector(1 to 1); - value_RNIBAHH : out std_logic_vector(1 to 1); - reload_RNI6SNI : out std_logic_vector(1 to 1); - scaler_i_m : out std_logic_vector(1 to 1); - reload_m_0_2 : out std_logic; - reload_m_0_3 : out std_logic; - reload_m_0_0 : out std_logic; - scaler_m_5 : out std_logic; - scaler_m_7 : out std_logic; - scaler_m_6 : out std_logic; - scaler_m_0 : out std_logic; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_25 : in std_logic := 'U'; - pwdata_12 : in std_logic := 'U'; - pwdata_24 : in std_logic := 'U'; - pwdata_23 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_19 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_13 : in std_logic := 'U'; - pwdata_11 : in std_logic := 'U'; - pwdata_10 : in std_logic := 'U'; - reload_28 : out std_logic; - reload_12 : out std_logic; - reload_11 : out std_logic; - reload_10 : out std_logic; - reload_8 : out std_logic; - reload_7 : out std_logic; - reload_6 : out std_logic; - reload_5 : out std_logic; - reload_0_7 : out std_logic; - reload_0_6 : out std_logic; - reload_0_4 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - prdata_17 : out std_logic; - prdata_0 : out std_logic; - prdata_2 : out std_logic; - prdata_4 : out std_logic; - prdata_16 : out std_logic; - prdata_3 : out std_logic; - prdata_5 : out std_logic; - prdata_11 : out std_logic; - prdata_15 : out std_logic; - prdata_9 : out std_logic; - readdata_9_i_m : out std_logic_vector(1 to 1); - readdata_1_iv_0_0 : out std_logic; - readdata_1_iv_0_2 : out std_logic; - readdata_1_iv_0_11 : out std_logic; - readdata_1_iv_0_13 : out std_logic; - readdata_1_iv_0_9 : out std_logic; - readdata_iv_3 : out std_logic_vector(3 downto 2); - reload_m_20 : out std_logic; - reload_m_5 : out std_logic; - reload_m_9 : out std_logic; - reload_m_21 : out std_logic; - reload_m_0_d0 : out std_logic; - reload_m_27 : out std_logic; - reload_m_4 : out std_logic; - value_m_1 : out std_logic; - value_m_9 : out std_logic; - value_m_5 : out std_logic; - value_m_23 : out std_logic; - value_m_17 : out std_logic; - value_m_11 : out std_logic; - value_m_3 : out std_logic; - value_m_20 : out std_logic; - value_m_6 : out std_logic; - value_m_4 : out std_logic; - value_m_7 : out std_logic; - value_m_0 : out std_logic; - value_m_24 : out std_logic; - value_m_22 : out std_logic; - value_m_18 : out std_logic; - value_m_8 : out std_logic; - value_m_16 : out std_logic; - paddr_0 : in std_logic_vector(3 downto 2) := (others => 'U'); - N_228 : out std_logic; - readdata51_1 : out std_logic; - N_6455 : in std_logic := 'U'; - chain_m : out std_logic; - rdata60_1 : out std_logic; - rdata60_4 : in std_logic := 'U'; - enable_m : out std_logic; - rdata59_4 : in std_logic := 'U'; - N_217 : out std_logic; - N_229 : out std_logic; - N_215 : out std_logic; - rdata61_2 : in std_logic := 'U'; - readdata55_3 : out std_logic; - N_218 : out std_logic; - N_216 : out std_logic; - N_214 : out std_logic; - irqpen_m : out std_logic; - N_219 : out std_logic; - N_236 : out std_logic; - N_220 : out std_logic; - rstn : in std_logic := 'U'; - restart_RNIIKBB : out std_logic; - N_240 : out std_logic; - readdata55 : out std_logic; - dishlt : out std_logic; - penable : in std_logic := 'U'; - pwrite : in std_logic := 'U'; - N_773 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - readdata57 : out std_logic; - un1_apbi_0 : out std_logic; - N_78 : in std_logic := 'U'; - un1_apbi_7_3 : in std_logic := 'U'; - un1_apbi_2 : out std_logic; - readdata56 : out std_logic; - N_232_0 : in std_logic := 'U'; - N_240_0 : out std_logic; - readdata_1_sqmuxa_1_0 : out std_logic; - N_232 : in std_logic := 'U'; - value_0_sqmuxa_0 : out std_logic; - N_6455_0 : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component INBUF - port( PAD : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component ssram_plugin - port( state_RNIFS55 : out std_logic_vector(4 to 4); - ramsn_c : in std_logic_vector(0 to 0) := (others => 'U'); - rwen_c : in std_logic_vector(3 downto 0) := (others => 'U'); - address_c : in std_logic_vector(27 downto 20) := (others => 'U'); - address : in std_logic_vector(31 downto 28) := (others => 'U'); - state_i : out std_logic_vector(3 to 3); - ssram_plugin_GND : in std_logic := 'U'; - clk_c : in std_logic := 'U'; - writen_c : in std_logic := 'U'; - nBWE_c : out std_logic; - nBWd_c : out std_logic; - nBWc_c : out std_logic; - nBWb_c : out std_logic; - nBWa_c : out std_logic; - nCE1_c : out std_logic; - nCE3_c : out std_logic; - CE2_c : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component TRIBUFF - port( D : in std_logic := 'U'; - E : in std_logic := 'U'; - PAD : out std_logic - ); - end component; - - component leon3s - port( irl_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - irl : out std_logic_vector(3 downto 0); - hrdata_1_0_1 : in std_logic_vector(1 to 1) := (others => 'U'); - data_0_21 : out std_logic; - data_0_16 : out std_logic; - data_0_5 : out std_logic; - data_0_2 : out std_logic; - data_0_0 : out std_logic; - nbo_5_0 : out std_logic_vector(1 downto 0); - htrans : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans_tz : out std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 2); - hwdata_16 : out std_logic; - hwdata_3 : out std_logic; - hwdata_9 : out std_logic; - hwdata_11 : out std_logic; - hwdata_25 : out std_logic; - hwdata_27 : out std_logic; - hwdata_13 : out std_logic; - hwdata_4 : out std_logic; - hwdata_12 : out std_logic; - hwdata_23 : out std_logic; - hwdata_28 : out std_logic; - hwdata_1 : out std_logic; - hwdata_14 : out std_logic; - hwdata_0 : out std_logic; - hwdata_15 : out std_logic; - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hsize_5 : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(0 to 0) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - address : out std_logic_vector(1 downto 0); - size : out std_logic_vector(0 to 0); - data_0_d0 : out std_logic; - data_5 : out std_logic; - data_3 : out std_logic; - data_8 : out std_logic; - data_19 : out std_logic; - data_24 : out std_logic; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - error_i_2 : out std_logic; - intack : out std_logic; - N_546 : in std_logic := 'U'; - leon3s_VCC : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - bo_5842_d_0 : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - hlock : out std_logic; - N_5054 : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - hbusreq : out std_logic; - un60_nbo : out std_logic; - N_457 : out std_logic; - N_462 : out std_logic; - N_467 : out std_logic; - werr_2_m_0 : out std_logic; - un91_nbo_i_0 : out std_logic; - N_138 : out std_logic; - N_139 : out std_logic; - bo_5842_d : out std_logic; - N_458 : out std_logic; - N_459 : out std_logic; - N_461 : out std_logic; - N_463 : out std_logic; - N_468 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_466 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - un59_nbo : out std_logic; - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component irqmp - port( irl_2 : out std_logic_vector(2 to 2); - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - irl_3 : in std_logic := 'U'; - irl_1 : in std_logic := 'U'; - irl_0_d0 : in std_logic := 'U'; - irl_0 : inout std_logic_vector(3 downto 0); - ipend_10 : out std_logic; - pwdata_4 : in std_logic := 'U'; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_23 : in std_logic := 'U'; - pwdata_26 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_25 : in std_logic := 'U'; - pwdata_27 : in std_logic := 'U'; - pwdata_28 : in std_logic := 'U'; - pwdata_29 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_19 : in std_logic := 'U'; - pwdata_24 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - iforce_0_11 : out std_logic; - iforce_0_5 : out std_logic; - iforce_0_9 : out std_logic; - iforce_0_4 : out std_logic; - iforce_0_6 : out std_logic; - ipend_m : out std_logic_vector(4 to 4); - prdata_0 : out std_logic; - prdata_13 : out std_logic; - prdata_1 : out std_logic; - iforce_0_m : out std_logic_vector(4 to 4); - ilevel_5 : out std_logic; - ilevel_4 : out std_logic; - ilevel_6 : out std_logic; - ilevel_3 : out std_logic; - ilevel_11 : out std_logic; - ilevel_7 : out std_logic; - ilevel_9 : out std_logic; - prdata_11_m_1_0 : out std_logic_vector(4 to 4); - prdata_13_m_1_0 : out std_logic_vector(4 to 4); - paddr : in std_logic_vector(7 downto 3) := (others => 'U'); - prdata_0_iv_0_0_0_12 : out std_logic; - prdata_0_iv_0_0_0_0 : out std_logic; - prdata_0_iv_0_0_0_13 : out std_logic; - prdata_0_iv_0_0_1_12 : out std_logic; - prdata_0_iv_0_0_1_0 : out std_logic; - prdata_0_iv_0_0_1_13 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 1) := (others => 'U'); - pirq_10 : in std_logic := 'U'; - pirq_11 : in std_logic := 'U'; - pirq_13 : in std_logic := 'U'; - pirq_7 : in std_logic := 'U'; - pirq_6 : in std_logic := 'U'; - pirq_0 : in std_logic := 'U'; - paddr_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - lclk_c : in std_logic := 'U'; - N_365 : out std_logic; - N_367 : out std_logic; - N_863 : out std_logic; - intack : in std_logic := 'U'; - N_865 : out std_logic; - N_861 : out std_logic; - N_859 : out std_logic; - N_478 : out std_logic; - N_476 : out std_logic; - N_474 : out std_logic; - N_473 : out std_logic; - N_472 : out std_logic; - N_471 : out std_logic; - N_470 : out std_logic; - N_468 : out std_logic; - N_467 : out std_logic; - N_842 : out std_logic; - N_841 : out std_logic; - N_839 : out std_logic; - N_363 : out std_logic; - N_361 : out std_logic; - N_773 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - N_749 : in std_logic := 'U'; - prdata_0_sqmuxa : out std_logic; - N_898 : out std_logic; - prdata_1_sqmuxa : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component apbuart - port( pwdata_12 : in std_logic := 'U'; - pwdata_13 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_2 : in std_logic := 'U'; - pwdata_5 : in std_logic := 'U'; - pwdata_6 : in std_logic := 'U'; - pwdata_7 : in std_logic := 'U'; - pwdata_8 : in std_logic := 'U'; - pwdata_9 : in std_logic := 'U'; - pwdata_10 : in std_logic := 'U'; - pwdata_11 : in std_logic := 'U'; - pirq : out std_logic_vector(2 to 2); - rcnt_RNI8FBM3 : out std_logic_vector(1 to 1); - rdata_2_0 : out std_logic; - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - paddr : in std_logic_vector(4 to 4) := (others => 'U'); - rdata_2_m_3 : out std_logic; - rdata_2_m_4 : out std_logic; - rdata_2_m_2 : out std_logic; - brate_0 : out std_logic; - brate_10 : out std_logic; - brate_9 : out std_logic; - brate_8 : out std_logic; - brate_7 : out std_logic; - brate_6 : out std_logic; - brate_m_3 : out std_logic; - brate_m_2 : out std_logic; - brate_m_9 : out std_logic; - pwdata_0 : in std_logic_vector(11 downto 0) := (others => 'U'); - rcnt_0 : out std_logic; - rcnt_1 : out std_logic; - rdata_17_m_0_d0 : out std_logic; - rdata_17_m_5 : out std_logic; - rdata_17_m_4 : out std_logic; - un1_uart1_34 : out std_logic; - rdata_17_m_0_4 : out std_logic; - rdata_iv_0_a2_3_0 : out std_logic_vector(7 to 7); - tcnt_0 : out std_logic; - tcnt_1 : out std_logic; - rdata_iv_2 : out std_logic_vector(3 downto 2); - rdata_iv_0_2 : out std_logic_vector(1 to 1); - prdata_6 : out std_logic; - prdata_0 : out std_logic; - prdata_9 : out std_logic; - paddr_0 : in std_logic_vector(4 to 4) := (others => 'U'); - apbuart_VCC : in std_logic := 'U'; - apbuart_GND : in std_logic := 'U'; - rxd1_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - txd1_c : out std_logic; - N_227 : out std_logic; - thempty_1_m : out std_logic; - debug_m : out std_logic; - N_232 : in std_logic := 'U'; - rdata60 : in std_logic := 'U'; - frame : out std_logic; - rdata59 : in std_logic := 'U'; - parerr_m : out std_logic; - rdata60_4 : out std_logic; - rdata62 : out std_logic; - N_6455_0 : in std_logic := 'U'; - rdata59_4 : out std_logic; - parsel_m_0 : out std_logic; - ovf_m : out std_logic; - break_m : out std_logic; - N_223 : out std_logic; - N_220 : out std_logic; - rfifoirqen_m : out std_logic; - tfifoirqen_m : out std_logic; - N_156 : out std_logic; - rhalffull_1_m : out std_logic; - rdata_3_sqmuxa : out std_logic; - ctrl2 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - tsemptyirqen_0 : out std_logic; - N_773 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - paren : out std_logic; - N_750 : in std_logic := 'U'; - penable : in std_logic := 'U'; - breakirqen : out std_logic; - delayirqen : out std_logic; - rdata_4_sqmuxa : out std_logic; - rdata_0_sqmuxa : out std_logic; - tcnt_i : out std_logic; - flow_m : out std_logic; - extclken_m : out std_logic; - rdata61 : in std_logic := 'U'; - pwrite : in std_logic := 'U'; - un1_apbi_8 : in std_logic := 'U'; - rdata62_0 : out std_logic; - rdata60_1 : in std_logic := 'U'; - rdata61_2 : in std_logic := 'U'; - rdata60_4_0 : out std_logic - ); - end component; - - component apbctrl - port( hrdata : out std_logic_vector(31 downto 0); - pwdata : out std_logic_vector(31 downto 0); - psel_1 : out std_logic_vector(7 to 7); - prdata_4 : in std_logic_vector(31 to 31) := (others => 'U'); - rdata_iv_0_2 : in std_logic_vector(1 to 1) := (others => 'U'); - prdata_iv_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - ramrws : in std_logic_vector(1 to 1) := (others => 'U'); - ramwws : in std_logic_vector(1 downto 0) := (others => 'U'); - romrws : in std_logic_vector(3 downto 1) := (others => 'U'); - prdata_iv_0_2 : in std_logic := 'U'; - prdata_iv_0_0_d0 : in std_logic := 'U'; - un1_grgpio0_0 : in std_logic := 'U'; - un1_grgpio0_2 : in std_logic := 'U'; - ramwidth : in std_logic_vector(1 downto 0) := (others => 'U'); - rdata_iv_2 : in std_logic_vector(3 downto 2) := (others => 'U'); - readdata_iv_3 : in std_logic_vector(3 downto 2) := (others => 'U'); - tcnt : in std_logic_vector(1 downto 0) := (others => 'U'); - prdata_3_29 : in std_logic := 'U'; - prdata_3_12 : in std_logic := 'U'; - prdata_3_0 : in std_logic := 'U'; - prdata_3_1 : in std_logic := 'U'; - prdata_3_14 : in std_logic := 'U'; - prdata_3_13 : in std_logic := 'U'; - prdata_3_26 : in std_logic := 'U'; - prdata_3_23 : in std_logic := 'U'; - prdata_3_16 : in std_logic := 'U'; - prdata_3_28 : in std_logic := 'U'; - prdata_3_27 : in std_logic := 'U'; - prdata_3_17 : in std_logic := 'U'; - prdata_3_15 : in std_logic := 'U'; - romwws : in std_logic_vector(3 downto 0) := (others => 'U'); - romwidth : in std_logic_vector(1 downto 0) := (others => 'U'); - rambanksz_0 : in std_logic := 'U'; - rambanksz_1 : in std_logic := 'U'; - rambanksz_3 : in std_logic := 'U'; - prdata_0_iv_0_0_0_13 : in std_logic := 'U'; - prdata_0_iv_0_0_0_0 : in std_logic := 'U'; - prdata_0_iv_0_0_0_12 : in std_logic := 'U'; - prdata_0_iv_0_0_1_13 : in std_logic := 'U'; - prdata_0_iv_0_0_1_0 : in std_logic := 'U'; - prdata_0_iv_0_0_1_12 : in std_logic := 'U'; - readdata_1_iv_0_13 : in std_logic := 'U'; - readdata_1_iv_0_2 : in std_logic := 'U'; - readdata_1_iv_0_0 : in std_logic := 'U'; - readdata_1_iv_0_9 : in std_logic := 'U'; - readdata_1_iv_0_11 : in std_logic := 'U'; - prdata_2_20 : in std_logic := 'U'; - prdata_2_31 : in std_logic := 'U'; - prdata_2_14 : in std_logic := 'U'; - prdata_2_1 : in std_logic := 'U'; - prdata_2_2 : in std_logic := 'U'; - prdata_2_5 : in std_logic := 'U'; - prdata_2_0 : in std_logic := 'U'; - prdata_2_3 : in std_logic := 'U'; - prdata_2_16 : in std_logic := 'U'; - prdata_2_21 : in std_logic := 'U'; - prdata_2_23 : in std_logic := 'U'; - prdata_2_15 : in std_logic := 'U'; - prdata_2_27 : in std_logic := 'U'; - prdata_2_28 : in std_logic := 'U'; - prdata_2_25 : in std_logic := 'U'; - prdata_2_18 : in std_logic := 'U'; - prdata_2_30 : in std_logic := 'U'; - prdata_2_29 : in std_logic := 'U'; - prdata_2_19 : in std_logic := 'U'; - prdata_2_17 : in std_logic := 'U'; - prdata_2_9 : in std_logic := 'U'; - prdata_2_13 : in std_logic := 'U'; - prdata_2_22 : in std_logic := 'U'; - prdata_2_24 : in std_logic := 'U'; - prdata_2_26 : in std_logic := 'U'; - prdata_11_m_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - prdata_13_m_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - psel_0 : out std_logic; - psel_15 : out std_logic; - psel_11 : out std_logic; - reload_RNI6SNI : in std_logic_vector(1 to 1) := (others => 'U'); - readdata_9_i_m : in std_logic_vector(1 to 1) := (others => 'U'); - un1_uart1 : in std_logic_vector(36 to 36) := (others => 'U'); - reload_m_0 : in std_logic_vector(0 to 0) := (others => 'U'); - reload_0 : in std_logic_vector(7 downto 6) := (others => 'U'); - un1_dcom0 : in std_logic_vector(19 downto 12) := (others => 'U'); - iows : in std_logic_vector(3 downto 2) := (others => 'U'); - ipend : in std_logic_vector(11 to 11) := (others => 'U'); - iforce_0_m : in std_logic_vector(4 to 4) := (others => 'U'); - ipend_m : in std_logic_vector(4 to 4) := (others => 'U'); - iforce_0_5 : in std_logic := 'U'; - iforce_0_2 : in std_logic := 'U'; - iforce_0_1 : in std_logic := 'U'; - iforce_0_7 : in std_logic := 'U'; - iforce_0_0 : in std_logic := 'U'; - ilevel_6 : in std_logic := 'U'; - ilevel_4 : in std_logic := 'U'; - ilevel_3 : in std_logic := 'U'; - ilevel_2 : in std_logic := 'U'; - ilevel_0 : in std_logic := 'U'; - ilevel_8 : in std_logic := 'U'; - ilevel_1 : in std_logic := 'U'; - oen : in std_logic_vector(7 to 7) := (others => 'U'); - readdata_2_m : in std_logic_vector(5 to 5) := (others => 'U'); - dout_2 : in std_logic := 'U'; - dout_0 : in std_logic := 'U'; - dout_6 : in std_logic := 'U'; - dout_5 : in std_logic := 'U'; - dout_4 : in std_logic := 'U'; - value_RNIBAHH : in std_logic_vector(1 to 1) := (others => 'U'); - reload_RNIRDRG : in std_logic_vector(1 to 1) := (others => 'U'); - scaler_i_m : in std_logic_vector(1 to 1) := (others => 'U'); - scaler : in std_logic_vector(4 to 4) := (others => 'U'); - value_6 : in std_logic := 'U'; - value_0 : in std_logic := 'U'; - reload_8 : in std_logic := 'U'; - reload_7 : in std_logic := 'U'; - reload_6 : in std_logic := 'U'; - reload_24 : in std_logic := 'U'; - reload_4 : in std_logic := 'U'; - reload_3 : in std_logic := 'U'; - reload_2 : in std_logic := 'U'; - reload_0_d0 : in std_logic := 'U'; - reload_1 : in std_logic := 'U'; - scaler_m_7 : in std_logic := 'U'; - scaler_m_6 : in std_logic := 'U'; - scaler_m_0 : in std_logic := 'U'; - scaler_m_5 : in std_logic := 'U'; - rcnt : in std_logic_vector(1 downto 0) := (others => 'U'); - rdata_2 : in std_logic_vector(0 to 0) := (others => 'U'); - rcnt_RNI8FBM3 : in std_logic_vector(1 to 1) := (others => 'U'); - rdata_iv_0_a2_3_0 : in std_logic_vector(7 to 7) := (others => 'U'); - brate_9 : in std_logic := 'U'; - brate_8 : in std_logic := 'U'; - brate_0 : in std_logic := 'U'; - brate_10 : in std_logic := 'U'; - brate_7 : in std_logic := 'U'; - brate_6 : in std_logic := 'U'; - rdata_17_m_0 : in std_logic_vector(6 to 6) := (others => 'U'); - brate_m_7 : in std_logic := 'U'; - brate_m_0 : in std_logic := 'U'; - brate_m_1 : in std_logic := 'U'; - rdata_17_m_0_d0 : in std_logic := 'U'; - rdata_17_m_4 : in std_logic := 'U'; - rdata_17_m_5 : in std_logic := 'U'; - rdata_2_m : in std_logic_vector(6 downto 4) := (others => 'U'); - prdata_1_20 : in std_logic := 'U'; - prdata_1_5 : in std_logic := 'U'; - prdata_1_12 : in std_logic := 'U'; - prdata_1_21 : in std_logic := 'U'; - prdata_1_23 : in std_logic := 'U'; - prdata_1_27 : in std_logic := 'U'; - prdata_1_0 : in std_logic := 'U'; - prdata_1_4 : in std_logic := 'U'; - prdata_1_6 : in std_logic := 'U'; - prdata_1_7 : in std_logic := 'U'; - prdata_1_8 : in std_logic := 'U'; - prdata_1_9 : in std_logic := 'U'; - prdata_1_10 : in std_logic := 'U'; - prdata_1_11 : in std_logic := 'U'; - prdata_1_22 : in std_logic := 'U'; - prdata_1_28 : in std_logic := 'U'; - paddr_5 : out std_logic; - paddr_2_d0 : out std_logic; - paddr_0_d0 : out std_logic; - paddr_1_d0 : out std_logic; - paddr_3 : out std_logic; - paddr_4 : out std_logic; - htrans : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - readdata_9_4 : in std_logic := 'U'; - readdata_9_0 : in std_logic := 'U'; - readdata_9_5 : in std_logic := 'U'; - readdata_9_27 : in std_logic := 'U'; - reload_m_2 : in std_logic := 'U'; - reload_m_3 : in std_logic := 'U'; - reload_m_21 : in std_logic := 'U'; - reload_m_9 : in std_logic := 'U'; - reload_m_0_d0 : in std_logic := 'U'; - reload_m_5 : in std_logic := 'U'; - reload_m_27 : in std_logic := 'U'; - reload_m_20 : in std_logic := 'U'; - reload_m_4 : in std_logic := 'U'; - value_m_22 : in std_logic := 'U'; - value_m_11 : in std_logic := 'U'; - value_m_9 : in std_logic := 'U'; - value_m_18 : in std_logic := 'U'; - value_m_20 : in std_logic := 'U'; - value_m_17 : in std_logic := 'U'; - value_m_4 : in std_logic := 'U'; - value_m_5 : in std_logic := 'U'; - value_m_3 : in std_logic := 'U'; - value_m_0 : in std_logic := 'U'; - value_m_1 : in std_logic := 'U'; - value_m_8 : in std_logic := 'U'; - value_m_7 : in std_logic := 'U'; - value_m_6 : in std_logic := 'U'; - value_m_23 : in std_logic := 'U'; - value_m_24 : in std_logic := 'U'; - value_m_16 : in std_logic := 'U'; - prdata_0_1 : in std_logic := 'U'; - prdata_0_23 : in std_logic := 'U'; - prdata_0_18 : in std_logic := 'U'; - prdata_0_30 : in std_logic := 'U'; - prdata_0_29 : in std_logic := 'U'; - prdata_0_0 : in std_logic := 'U'; - prdata_0_8 : in std_logic := 'U'; - prdata_0_10 : in std_logic := 'U'; - prdata_0_11 : in std_logic := 'U'; - prdata_0_12 : in std_logic := 'U'; - prdata_0_13 : in std_logic := 'U'; - prdata_0_24 : in std_logic := 'U'; - prdata_0_26 : in std_logic := 'U'; - prdata_0_17 : in std_logic := 'U'; - prdata_0_19 : in std_logic := 'U'; - prdata_0_25 : in std_logic := 'U'; - prdata_0_16 : in std_logic := 'U'; - prdata_0_22 : in std_logic := 'U'; - prdata_0_15 : in std_logic := 'U'; - prdata_0_31 : in std_logic := 'U'; - prdata_0_14 : in std_logic := 'U'; - prdata_0_21 : in std_logic := 'U'; - prdata_0_27 : in std_logic := 'U'; - prdata_0_20 : in std_logic := 'U'; - prdata_0_4 : in std_logic := 'U'; - prdata_0_6 : in std_logic := 'U'; - prdata_0_7 : in std_logic := 'U'; - prdata_0_5 : in std_logic := 'U'; - prdata_0_3 : in std_logic := 'U'; - prdata_0_2 : in std_logic := 'U'; - prdata_0_28 : in std_logic := 'U'; - prdata : in std_logic_vector(31 downto 0) := (others => 'U'); - pwdata_i : out std_logic_vector(7 downto 0); - pwdata_1_3 : out std_logic; - pwdata_1_2 : out std_logic; - pwdata_1_0 : out std_logic; - hwdata : in std_logic_vector(31 downto 0) := (others => 'U'); - pwdata_0 : out std_logic_vector(15 downto 0); - paddr_0 : out std_logic_vector(4 downto 2); - paddr_1 : out std_logic_vector(2 to 2); - haddr : in std_logic_vector(19 downto 2) := (others => 'U'); - paddr_2 : out std_logic_vector(2 to 2); - hready : out std_logic; - readdata51_1 : in std_logic := 'U'; - N_227 : in std_logic := 'U'; - thempty_1_m : in std_logic := 'U'; - N_6432 : in std_logic := 'U'; - rmw : in std_logic := 'U'; - penable : out std_logic; - un1_apbi_2 : in std_logic := 'U'; - N_5062 : in std_logic := 'U'; - break_m : in std_logic := 'U'; - N_332 : in std_logic := 'U'; - N_333 : in std_logic := 'U'; - N_334 : in std_logic := 'U'; - N_335 : in std_logic := 'U'; - N_336 : in std_logic := 'U'; - N_5070 : in std_logic := 'U'; - breakirqen : in std_logic := 'U'; - N_6455_0 : in std_logic := 'U'; - N_773 : out std_logic; - hwrite : in std_logic := 'U'; - un1_apbi_7_3 : out std_logic; - N_330 : in std_logic := 'U'; - parerr_m : in std_logic := 'U'; - rdata60_1 : in std_logic := 'U'; - N_331 : in std_logic := 'U'; - N_86 : in std_logic := 'U'; - N_85 : in std_logic := 'U'; - un1_apbi_7_1 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - bexcen : in std_logic := 'U'; - ioen : in std_logic := 'U'; - ovf_m : in std_logic := 'U'; - parsel_m_0 : in std_logic := 'U'; - frame : in std_logic := 'U'; - tcnt_i : in std_logic := 'U'; - N_156 : in std_logic := 'U'; - readdata56 : in std_logic := 'U'; - tfifoirqen_m : in std_logic := 'U'; - rfifoirqen_m : in std_logic := 'U'; - debug_m : in std_logic := 'U'; - delayirqen : in std_logic := 'U'; - N_127 : in std_logic := 'U'; - N_78 : out std_logic; - N_232_0 : in std_logic := 'U'; - brdyen : in std_logic := 'U'; - N_839 : in std_logic := 'U'; - prdata_1_sqmuxa : in std_logic := 'U'; - N_842 : in std_logic := 'U'; - N_841 : in std_logic := 'U'; - N_476 : in std_logic := 'U'; - N_478 : in std_logic := 'U'; - N_474 : in std_logic := 'U'; - N_473 : in std_logic := 'U'; - N_471 : in std_logic := 'U'; - N_472 : in std_logic := 'U'; - N_470 : in std_logic := 'U'; - N_467 : in std_logic := 'U'; - N_468 : in std_logic := 'U'; - N_859 : in std_logic := 'U'; - N_861 : in std_logic := 'U'; - N_361 : in std_logic := 'U'; - N_363 : in std_logic := 'U'; - readdata55_3 : in std_logic := 'U'; - N_863 : in std_logic := 'U'; - N_865 : in std_logic := 'U'; - N_365 : in std_logic := 'U'; - N_898 : in std_logic := 'U'; - N_367 : in std_logic := 'U'; - prdata_0_sqmuxa : in std_logic := 'U'; - rdata60_4_0 : in std_logic := 'U'; - N_6437 : in std_logic := 'U'; - N_6439 : in std_logic := 'U'; - N_6435 : in std_logic := 'U'; - N_6436 : in std_logic := 'U'; - N_6434 : in std_logic := 'U'; - N_6429 : in std_logic := 'U'; - N_6430 : in std_logic := 'U'; - N_6428 : in std_logic := 'U'; - rdata59_4 : in std_logic := 'U'; - N_220_0 : in std_logic := 'U'; - N_219 : in std_logic := 'U'; - N_240 : in std_logic := 'U'; - N_218 : in std_logic := 'U'; - N_236 : in std_logic := 'U'; - N_229 : in std_logic := 'U'; - N_228 : in std_logic := 'U'; - N_216 : in std_logic := 'U'; - N_217 : in std_logic := 'U'; - dishlt : in std_logic := 'U'; - restart_RNIIKBB : in std_logic := 'U'; - N_215 : in std_logic := 'U'; - N_214 : in std_logic := 'U'; - N_240_0 : in std_logic := 'U'; - readdata57 : in std_logic := 'U'; - irqpen_m : in std_logic := 'U'; - readdata55 : in std_logic := 'U'; - enable_m : in std_logic := 'U'; - value_0_sqmuxa_0 : in std_logic := 'U'; - chain_m : in std_logic := 'U'; - readdata_1_sqmuxa_1_0 : in std_logic := 'U'; - tsemptyirqen : in std_logic := 'U'; - rdata_0_sqmuxa : in std_logic := 'U'; - N_223 : in std_logic := 'U'; - N_220 : in std_logic := 'U'; - rdata_3_sqmuxa : in std_logic := 'U'; - rdata_4_sqmuxa : in std_logic := 'U'; - paren : in std_logic := 'U'; - N_770 : in std_logic := 'U'; - rhalffull_1_m : in std_logic := 'U'; - flow_m : in std_logic := 'U'; - extclken_m : in std_logic := 'U'; - N_769 : out std_logic; - N_116 : out std_logic; - N_796 : out std_logic; - N_750 : out std_logic; - N_749 : out std_logic; - lclk_c : in std_logic := 'U'; - pwrite : out std_logic; - un51_ioen_NE : in std_logic := 'U' - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component ahbram - port( hwdata : in std_logic_vector(31 downto 0) := (others => 'U'); - hrdata : out std_logic_vector(31 downto 0); - hsize : in std_logic_vector(1 downto 0) := (others => 'U'); - iosn : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - haddr : in std_logic_vector(9 downto 0) := (others => 'U'); - lclk_c : in std_logic := 'U'; - un315_ioen_NE : in std_logic := 'U'; - hready : out std_logic; - hwrite_1 : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - component CLKBUF - port( PAD : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_bootloader - port( haddr : in std_logic_vector(9 downto 2) := (others => 'U'); - hrdata_26 : out std_logic; - hrdata_13 : out std_logic; - hrdata_8 : out std_logic; - hrdata_5 : out std_logic; - hrdata_29 : out std_logic; - hrdata_18 : out std_logic; - hrdata_6 : out std_logic; - hrdata_19 : out std_logic; - hrdata_17 : out std_logic; - hrdata_7 : out std_logic; - hrdata_16 : out std_logic; - hrdata_30 : out std_logic; - hrdata_9 : out std_logic; - hrdata_25 : out std_logic; - hrdata_27 : out std_logic; - hrdata_21 : out std_logic; - hrdata_3 : out std_logic; - hrdata_0 : out std_logic; - hrdata_1 : out std_logic; - hrdata_23 : out std_logic; - hrdata_4 : out std_logic; - hrdata_28 : out std_logic; - hrdata_14 : out std_logic; - hrdata_22 : out std_logic; - hrdata_15 : out std_logic; - hrdata_2 : out std_logic; - hrdata_11 : out std_logic; - hrdata_10 : out std_logic; - hrdata_12 : out std_logic; - prdata : out std_logic_vector(31 downto 0); - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - pwdata_31 : in std_logic := 'U'; - pwdata_30 : in std_logic := 'U'; - pwdata_29 : in std_logic := 'U'; - pwdata_28 : in std_logic := 'U'; - pwdata_27 : in std_logic := 'U'; - pwdata_26 : in std_logic := 'U'; - pwdata_25 : in std_logic := 'U'; - pwdata_24 : in std_logic := 'U'; - pwdata_23 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_19 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_13 : in std_logic := 'U'; - pwdata_12 : in std_logic := 'U'; - pwdata_11 : in std_logic := 'U'; - pwdata_10 : in std_logic := 'U'; - pwdata_9 : in std_logic := 'U'; - pwdata_8 : in std_logic := 'U'; - pwdata_7 : in std_logic := 'U'; - pwdata_6 : in std_logic := 'U'; - pwdata_5 : in std_logic := 'U'; - pwdata_2 : in std_logic := 'U'; - pwdata_0 : in std_logic := 'U'; - N_103_i_0 : out std_logic; - N_90_i_0 : out std_logic; - N_95_i_0 : out std_logic; - rstraw_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - rdata60_4 : in std_logic := 'U'; - N_6459 : in std_logic := 'U'; - rdata59_4 : in std_logic := 'U'; - readdata55_3 : in std_logic := 'U'; - rdata62_3 : in std_logic := 'U'; - N_750 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - rdata60_4_0 : in std_logic := 'U'; - N_796 : in std_logic := 'U' - ); - end component; - - component lpp_top_lfr_wf_picker - port( sdo_adc_c : in std_logic_vector(7 downto 0) := (others => 'U'); - hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - coarse_time : in std_logic_vector(0 to 0) := (others => 'U'); - coarse_time_i : in std_logic_vector(0 to 0) := (others => 'U'); - pwdata_0 : in std_logic_vector(11 downto 0) := (others => 'U'); - paddr_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - paddr : in std_logic_vector(7 downto 3) := (others => 'U'); - paddr_2 : in std_logic_vector(2 to 2) := (others => 'U'); - pwdata_1_2 : in std_logic := 'U'; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - pwdata : in std_logic_vector(31 downto 0) := (others => 'U'); - pirq : out std_logic_vector(15 to 15); - prdata : out std_logic_vector(31 downto 0); - lpp_top_lfr_wf_picker_VCC : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - cnv_ch1_c : out std_logic; - sck_ch1_c : out std_logic; - lpp_top_lfr_wf_picker_GND : in std_logic := 'U'; - IdlePhase : out std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - arb_1 : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - Lock_RNIU86D : out std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - m19_0_N_15_i_0_li : in std_logic := 'U'; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - m26_m1_e : out std_logic; - lclk_c : in std_logic := 'U'; - rstn : in std_logic := 'U'; - N_232 : in std_logic := 'U'; - N_6455_0 : in std_logic := 'U'; - Bias_Fails_c : out std_logic; - N_749 : in std_logic := 'U'; - N_116 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - N_232_0 : in std_logic := 'U'; - N_232_1 : in std_logic := 'U'; - rdata61_2 : in std_logic := 'U'; - N_6455 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U' - ); - end component; - - component ahbuart - port( haddr : out std_logic_vector(31 downto 0); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_25 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - pwdata_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - un1_dcom0 : out std_logic_vector(19 downto 12); - pwdata : in std_logic_vector(17 downto 16) := (others => 'U'); - psel_1 : in std_logic_vector(7 to 7) := (others => 'U'); - prdata_0 : out std_logic; - prdata_5 : out std_logic; - pwdata_1 : in std_logic_vector(4 to 4) := (others => 'U'); - paddr : in std_logic_vector(3 downto 2) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(1 to 1) := (others => 'U'); - iosn : in std_logic_vector(93 to 93) := (others => 'U'); - hwrite : out std_logic; - N_264_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - N_86 : out std_logic; - rdata60_1 : in std_logic := 'U'; - N_85 : out std_logic; - dsutx_c : out std_logic; - N_6455_0 : in std_logic := 'U'; - N_332 : out std_logic; - N_333 : out std_logic; - N_334 : out std_logic; - N_336 : out std_logic; - N_331 : out std_logic; - N_6455 : in std_logic := 'U'; - N_127 : out std_logic; - N_330 : out std_logic; - N_769 : in std_logic := 'U'; - un1_apbi_2 : in std_logic := 'U'; - N_335 : out std_logic; - dsurx_c : in std_logic := 'U'; - rstn : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component ahbctrl - port( hmbsel : out std_logic_vector(0 to 0); - htrans_3 : in std_logic_vector(1 to 1) := (others => 'U'); - htrans_2 : in std_logic_vector(1 to 1) := (others => 'U'); - htrans_1 : in std_logic_vector(1 to 1) := (others => 'U'); - htrans_0_0 : in std_logic := 'U'; - bco_msb_1 : out std_logic_vector(1 to 1); - hresp_0 : out std_logic_vector(0 to 0); - nhmaster_1_i : out std_logic_vector(0 to 0); - hgrant_3 : out std_logic; - hgrant_1 : out std_logic; - hgrant_0 : out std_logic; - hsize_5 : in std_logic_vector(1 to 1) := (others => 'U'); - hmbsel_1 : out std_logic_vector(0 to 0); - hburst_0 : in std_logic_vector(2 downto 0) := (others => 'U'); - hsize_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - haddr_3_4 : in std_logic := 'U'; - haddr_3_5 : in std_logic := 'U'; - haddr_3_0 : in std_logic := 'U'; - haddr_3_3 : in std_logic := 'U'; - haddr_3_8 : in std_logic := 'U'; - haddr_3_6 : in std_logic := 'U'; - haddr_3_1 : in std_logic := 'U'; - haddr_3_7 : in std_logic := 'U'; - hwdata_m_0_3 : out std_logic; - hwdata_m_0_0 : out std_logic; - hwdata_m_0_2 : out std_logic; - hwdata_m_8 : out std_logic; - hwdata_m_13 : out std_logic; - hwdata_m_5 : out std_logic; - hwdata_m_0_d0 : out std_logic; - hwdata_m_7 : out std_logic; - hwdata_2_15 : out std_logic; - hwdata_2_0 : in std_logic := 'U'; - hwdata_2_9 : in std_logic := 'U'; - hwdata_2_3 : in std_logic := 'U'; - hwdata_2_14 : out std_logic; - hwdata_2_1 : in std_logic := 'U'; - hwdata_2_28 : in std_logic := 'U'; - hwdata_2_27 : in std_logic := 'U'; - hwdata_2_25 : in std_logic := 'U'; - hwdata_2_23 : in std_logic := 'U'; - hwdata_2_13 : in std_logic := 'U'; - hwdata_2_12 : in std_logic := 'U'; - hwdata_2_11 : in std_logic := 'U'; - hwdata_2_4 : in std_logic := 'U'; - hwdata_2_16 : in std_logic := 'U'; - hwdata_1 : inout std_logic_vector(31 downto 0); - hwdata_0 : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata : inout std_logic_vector(31 downto 0); - haddr_2 : inout std_logic_vector(30 downto 2); - haddr_1 : inout std_logic_vector(31 downto 0); - haddr_0 : inout std_logic_vector(31 downto 0); - hrdata_4_15 : in std_logic := 'U'; - hrdata_4_13 : in std_logic := 'U'; - hrdata_4_11 : in std_logic := 'U'; - hrdata_4_27 : in std_logic := 'U'; - hrdata_4_26 : in std_logic := 'U'; - hrdata_4_4 : in std_logic := 'U'; - hrdata_4_21 : in std_logic := 'U'; - hrdata_4_1 : in std_logic := 'U'; - hrdata_4_22 : in std_logic := 'U'; - hrdata_4_23 : in std_logic := 'U'; - hrdata_4_0 : in std_logic := 'U'; - hrdata_4_14 : in std_logic := 'U'; - hrdata_4_3 : in std_logic := 'U'; - hrdata_4_2 : in std_logic := 'U'; - hrdata_4_9 : in std_logic := 'U'; - hrdata_4_12 : in std_logic := 'U'; - hrdata_4_10 : in std_logic := 'U'; - hrdata_4_7 : in std_logic := 'U'; - hrdata_4_8 : in std_logic := 'U'; - hrdata_4_16 : in std_logic := 'U'; - hrdata_4_18 : in std_logic := 'U'; - hrdata_4_17 : in std_logic := 'U'; - hrdata_3_15 : in std_logic := 'U'; - hrdata_3_13 : in std_logic := 'U'; - hrdata_3_11 : in std_logic := 'U'; - hrdata_3_28 : in std_logic := 'U'; - hrdata_3_27 : in std_logic := 'U'; - hrdata_3_26 : in std_logic := 'U'; - hrdata_3_4 : in std_logic := 'U'; - hrdata_3_1 : in std_logic := 'U'; - hrdata_3_22 : in std_logic := 'U'; - hrdata_3_23 : in std_logic := 'U'; - hrdata_3_0 : in std_logic := 'U'; - hrdata_3_24 : in std_logic := 'U'; - hrdata_3_21 : in std_logic := 'U'; - hrdata_3_14 : in std_logic := 'U'; - hrdata_3_3 : in std_logic := 'U'; - hrdata_3_2 : in std_logic := 'U'; - hrdata_3_9 : in std_logic := 'U'; - hrdata_3_12 : in std_logic := 'U'; - hrdata_3_10 : in std_logic := 'U'; - hrdata_3_7 : in std_logic := 'U'; - hrdata_3_6 : in std_logic := 'U'; - hrdata_3_8 : in std_logic := 'U'; - hrdata_3_29 : in std_logic := 'U'; - hrdata_3_16 : in std_logic := 'U'; - hrdata_3_5 : in std_logic := 'U'; - hrdata_3_30 : in std_logic := 'U'; - hrdata_3_18 : in std_logic := 'U'; - hrdata_3_17 : in std_logic := 'U'; - hrdata_2_28 : in std_logic := 'U'; - hrdata_2_25 : in std_logic := 'U'; - hrdata_2_15 : out std_logic; - hrdata_2_11 : out std_logic; - hrdata_2_27 : out std_logic; - hrdata_2_26 : out std_logic; - hrdata_2_23 : in std_logic := 'U'; - hrdata_2_22 : in std_logic := 'U'; - hrdata_2_21 : in std_logic := 'U'; - hrdata_2_13 : in std_logic := 'U'; - hrdata_2_4 : in std_logic := 'U'; - hrdata_2_1 : in std_logic := 'U'; - hrdata_2_0 : in std_logic := 'U'; - hrdata_2_24 : in std_logic := 'U'; - hrdata_2_14 : in std_logic := 'U'; - hrdata_2_3 : in std_logic := 'U'; - hrdata_2_2 : in std_logic := 'U'; - hrdata_2_31 : in std_logic := 'U'; - hrdata_2_9 : out std_logic; - hrdata_2_19 : in std_logic := 'U'; - hrdata_2_10 : out std_logic; - hrdata_2_7 : out std_logic; - hrdata_2_6 : in std_logic := 'U'; - hrdata_2_29 : in std_logic := 'U'; - hrdata_2_5 : in std_logic := 'U'; - hrdata_2_30 : in std_logic := 'U'; - hrdata_2_18 : in std_logic := 'U'; - hrdata_2_16 : in std_logic := 'U'; - hrdata_2_12 : in std_logic := 'U'; - hrdata_2_8 : in std_logic := 'U'; - hrdata_2_17 : in std_logic := 'U'; - bco_msb_1_m : out std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : out std_logic_vector(1 to 1); - l1_0_m : out std_logic_vector(1 to 1); - nhmaster_1_iv_0 : out std_logic_vector(1 to 1); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - htrans : out std_logic_vector(1 downto 0); - hrdata_1 : inout std_logic_vector(31 downto 0); - data_0_5 : in std_logic := 'U'; - data_0_21 : in std_logic := 'U'; - data_0_16 : in std_logic := 'U'; - data_0_2 : in std_logic := 'U'; - data_0_0 : in std_logic := 'U'; - data_8 : in std_logic := 'U'; - data_24 : in std_logic := 'U'; - data_0_d0 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - data_5 : in std_logic := 'U'; - data_3 : in std_logic := 'U'; - hrdata : inout std_logic_vector(31 downto 0); - size : in std_logic_vector(0 to 0) := (others => 'U'); - nbo_5_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - address : in std_logic_vector(1 downto 0) := (others => 'U'); - htrans_tz : in std_logic_vector(1 to 1) := (others => 'U'); - haddr_1_d0 : out std_logic; - haddr_11 : out std_logic; - haddr_31 : in std_logic := 'U'; - haddr_0_d0 : in std_logic := 'U'; - haddr_4 : in std_logic := 'U'; - haddr_15 : out std_logic; - haddr_14 : out std_logic; - haddr_19 : out std_logic; - haddr_18 : out std_logic; - haddr_21 : out std_logic; - haddr_20 : out std_logic; - haddr_23 : out std_logic; - haddr_22 : out std_logic; - haddr_27 : out std_logic; - haddr_26 : out std_logic; - haddr_29 : out std_logic; - haddr_28 : out std_logic; - haddr_12 : out std_logic; - haddr_13 : out std_logic; - haddr_16 : out std_logic; - haddr_17 : out std_logic; - haddr_24 : out std_logic; - haddr_25 : out std_logic; - haddr_30 : out std_logic; - hburst : out std_logic_vector(2 downto 0); - hsel_i : out std_logic_vector(0 to 0); - hrdata_1_0_1_0 : out std_logic; - hrdata_0 : inout std_logic_vector(31 downto 0); - iosn_0 : out std_logic_vector(93 to 93); - iosn_1_8 : out std_logic; - iosn_1_0 : out std_logic; - iosn_2 : out std_logic_vector(93 to 93); - iosn_8 : out std_logic; - iosn_7 : out std_logic; - iosn_0_d0 : out std_logic; - hmaster_0_1 : out std_logic; - N_5054 : in std_logic := 'U'; - htrans_0_sqmuxa_2 : in std_logic := 'U'; - lb_0_sqmuxa_1 : in std_logic := 'U'; - N_466 : in std_logic := 'U'; - N_95_i_0 : in std_logic := 'U'; - bo_5842_d : in std_logic := 'U'; - rstn : in std_logic := 'U'; - hbusreq_i_3_0 : in std_logic := 'U'; - N_90_i_0 : in std_logic := 'U'; - N_262 : out std_logic; - hwrite_1_m_0 : in std_logic := 'U'; - werr_2_m_0 : in std_logic := 'U'; - hwrite_1 : in std_logic := 'U'; - hwrite_0 : in std_logic := 'U'; - N_458 : in std_logic := 'U'; - N_459 : in std_logic := 'U'; - N_468 : in std_logic := 'U'; - N_463 : in std_logic := 'U'; - N_461 : in std_logic := 'U'; - N_510 : in std_logic := 'U'; - N_138 : in std_logic := 'U'; - N_139 : in std_logic := 'U'; - N_6377 : in std_logic := 'U'; - N_103_i_0 : in std_logic := 'U'; - brmw_i : in std_logic := 'U'; - N_6550 : in std_logic := 'U'; - N_264 : out std_logic; - N_467 : in std_logic := 'U'; - N_457 : in std_logic := 'U'; - N_462 : in std_logic := 'U'; - un1_nhmaster_0_sqmuxa_1 : out std_logic; - un1_htrans_1_sqmuxa_0 : in std_logic := 'U'; - un60_nbo : in std_logic := 'U'; - arb_1 : out std_logic; - hbusreq : in std_logic := 'U'; - hlock : in std_logic := 'U'; - hready_1 : in std_logic := 'U'; - hready_0 : in std_logic := 'U'; - N_78 : out std_logic; - un315_ioen_NE : out std_logic; - un51_ioen_NE : out std_logic; - un59_nbo : in std_logic := 'U'; - un91_nbo_i_0 : in std_logic := 'U'; - hready : in std_logic := 'U'; - bo_5842_d_0 : in std_logic := 'U'; - un6_ioen_NE_0 : out std_logic; - brmw_1 : in std_logic := 'U'; - hwrite : out std_logic; - hwrite_m_0_0 : out std_logic; - hbusreq_i_3 : in std_logic := 'U'; - IdlePhase : in std_logic := 'U'; - un1_dmain_6 : in std_logic := 'U'; - Lock_RNIU86D : in std_logic := 'U'; - N_546 : out std_logic; - N_264_0 : out std_logic; - N_262_0 : out std_logic; - N_78_0 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component apb_lfr_time_management - port( coarse_time_i : out std_logic_vector(0 to 0); - pirq : out std_logic_vector(13 downto 12); - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - prdata : out std_logic_vector(31 downto 0); - coarse_time_0 : out std_logic; - pwdata_10 : in std_logic := 'U'; - pwdata_8 : in std_logic := 'U'; - pwdata_7 : in std_logic := 'U'; - pwdata_13 : in std_logic := 'U'; - pwdata_12 : in std_logic := 'U'; - pwdata_11 : in std_logic := 'U'; - pwdata_9 : in std_logic := 'U'; - pwdata_6 : in std_logic := 'U'; - pwdata_5 : in std_logic := 'U'; - pwdata_4 : in std_logic := 'U'; - pwdata_3 : in std_logic := 'U'; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_29 : in std_logic := 'U'; - pwdata_28 : in std_logic := 'U'; - pwdata_27 : in std_logic := 'U'; - pwdata_25 : in std_logic := 'U'; - pwdata_24 : in std_logic := 'U'; - pwdata_23 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_19 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_26 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - paddr : in std_logic_vector(7 downto 3) := (others => 'U'); - psel : in std_logic_vector(15 to 15) := (others => 'U'); - rstn_i : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - clk49_152MHz_c_0 : in std_logic := 'U'; - un1_apbi_7_1 : out std_logic; - rdata60 : out std_logic; - ctrl2 : out std_logic; - rdata59 : out std_logic; - N_232_0 : in std_logic := 'U'; - un1_apbi_2 : in std_logic := 'U'; - rdata61_2 : in std_logic := 'U'; - N_770 : out std_logic; - rdata62_0 : in std_logic := 'U'; - rdata61 : out std_logic; - un1_apbi_8 : out std_logic; - un1_apbi_7_3 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - rdata62 : in std_logic := 'U'; - rdata60_4 : in std_logic := 'U'; - rdata59_4 : in std_logic := 'U'; - readdata55_3 : in std_logic := 'U'; - rdata62_3 : out std_logic; - pwrite : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component BUFF - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component rstgen - port( rstgen_VCC : in std_logic := 'U'; - rstraw_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - m26_m1_e : in std_logic := 'U'; - rstoutl_RNIGJKSJO : out std_logic; - rstn_i : out std_logic; - rstn : out std_logic - ); - end component; - - component mctrl - port( data_in : in std_logic_vector(31 downto 0) := (others => 'U'); - hresp : out std_logic_vector(0 to 0); - address : out std_logic_vector(31 downto 28); - romsn_c : out std_logic_vector(1 downto 0); - ramoen_c : out std_logic_vector(3 downto 0); - hmbsel_1 : in std_logic_vector(0 to 0) := (others => 'U'); - hburst_0 : in std_logic_vector(2 downto 0) := (others => 'U'); - hmbsel : in std_logic_vector(0 to 0) := (others => 'U'); - ramrws_1 : out std_logic; - ramwws : out std_logic_vector(1 downto 0); - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - rwen_c : out std_logic_vector(3 downto 0); - iosn_1_8 : in std_logic := 'U'; - iosn_1_0 : in std_logic := 'U'; - ramsn_c : out std_logic_vector(3 downto 0); - rambanksz_0 : out std_logic; - rambanksz_1 : out std_logic; - rambanksz_3 : out std_logic; - paddr_2 : in std_logic_vector(2 to 2) := (others => 'U'); - iows_3 : out std_logic; - iows_2 : out std_logic; - pwdata_23 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_7 : in std_logic := 'U'; - pwdata_6 : in std_logic := 'U'; - pwdata_5 : in std_logic := 'U'; - pwdata_4 : in std_logic := 'U'; - pwdata_1_d0 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_0_5 : in std_logic := 'U'; - pwdata_0_7 : in std_logic := 'U'; - pwdata_0_8 : in std_logic := 'U'; - pwdata_0_9 : in std_logic := 'U'; - pwdata_0_2 : in std_logic := 'U'; - pwdata_0_1 : in std_logic := 'U'; - pwdata_0_0 : in std_logic := 'U'; - pwdata_0_6 : in std_logic := 'U'; - pwdata_0_11 : in std_logic := 'U'; - hsize : in std_logic_vector(1 downto 0) := (others => 'U'); - romrws_1 : out std_logic; - romrws_3 : out std_logic; - romrws_2 : out std_logic; - hwdata_m_0_3 : in std_logic := 'U'; - hwdata_m_0_2 : in std_logic := 'U'; - hwdata_m_0_0 : in std_logic := 'U'; - psel : in std_logic_vector(0 to 0) := (others => 'U'); - romwidth : out std_logic_vector(1 downto 0); - iosn_100 : in std_logic := 'U'; - iosn_99 : in std_logic := 'U'; - address_c : out std_logic_vector(27 downto 0); - hwdata_m_8 : in std_logic := 'U'; - hwdata_m_7 : in std_logic := 'U'; - hwdata_m_5 : in std_logic := 'U'; - hwdata_m_0_d0 : in std_logic := 'U'; - hwdata_m_13 : in std_logic := 'U'; - data : out std_logic_vector(31 downto 0); - haddr : in std_logic_vector(30 downto 0) := (others => 'U'); - ramwidth : out std_logic_vector(1 downto 0); - htrans : in std_logic_vector(1 downto 0) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - hsel_i : in std_logic_vector(0 to 0) := (others => 'U'); - romwws : out std_logic_vector(3 downto 0); - prdata_0 : out std_logic; - prdata_1 : out std_logic; - prdata_8 : out std_logic; - prdata_7 : out std_logic; - hrdata : out std_logic_vector(31 downto 0); - hwdata_4 : in std_logic := 'U'; - hwdata_3 : in std_logic := 'U'; - hwdata_8 : in std_logic := 'U'; - hwdata_13 : in std_logic := 'U'; - hwdata_24 : in std_logic := 'U'; - hwdata_23 : in std_logic := 'U'; - hwdata_22 : in std_logic := 'U'; - hwdata_20 : in std_logic := 'U'; - hwdata_10 : in std_logic := 'U'; - hwdata_26 : in std_logic := 'U'; - hwdata_9 : in std_logic := 'U'; - hwdata_16 : in std_logic := 'U'; - hwdata_17 : in std_logic := 'U'; - hwdata_7 : in std_logic := 'U'; - hwdata_30 : in std_logic := 'U'; - hwdata_28 : in std_logic := 'U'; - hwdata_5 : in std_logic := 'U'; - hwdata_31 : in std_logic := 'U'; - hwdata_1 : in std_logic := 'U'; - hwdata_19 : in std_logic := 'U'; - hwdata_29 : in std_logic := 'U'; - hwdata_21 : in std_logic := 'U'; - hwdata_18 : in std_logic := 'U'; - hwdata_0 : in std_logic := 'U'; - hwdata_6 : in std_logic := 'U'; - hwdata_2 : in std_logic := 'U'; - hwdata_27 : in std_logic := 'U'; - hwdata_11 : in std_logic := 'U'; - hwdata_25 : in std_logic := 'U'; - bdrive_i : out std_logic_vector(3 downto 0); - paddr : in std_logic_vector(3 downto 2) := (others => 'U'); - iosn_c : out std_logic; - lclk_c : in std_logic := 'U'; - N_6455 : out std_logic; - N_5062 : out std_logic; - un6_ioen_NE_0 : in std_logic := 'U'; - N_510 : out std_logic; - N_6459 : in std_logic := 'U'; - N_5070 : out std_logic; - bexcen : out std_logic; - brdyen : out std_logic; - ioen : out std_logic; - writen_c : out std_logic; - hwrite_m_0_0 : in std_logic := 'U'; - hwrite : in std_logic := 'U'; - brmw_1 : out std_logic; - N_6550 : out std_logic; - oen_c : out std_logic; - rdata61_2 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - brmw_i : out std_logic; - N_6377 : out std_logic; - rmw : out std_logic; - rstn : in std_logic := 'U'; - read_c : out std_logic; - hready : out std_logic; - N_232_0 : in std_logic := 'U'; - N_6455_0 : out std_logic - ); - end component; - - component grgpio - port( un1_grgpio0_7 : out std_logic; - un1_grgpio0_5 : out std_logic; - gpio_in : in std_logic_vector(7 downto 0) := (others => 'U'); - pwdata_i : in std_logic_vector(7 downto 0) := (others => 'U'); - paddr : in std_logic_vector(5 downto 2) := (others => 'U'); - readdata_2_m : out std_logic_vector(5 to 5); - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - pwdata_0_5 : in std_logic := 'U'; - pwdata_0_7 : in std_logic := 'U'; - pwdata_0_6 : in std_logic := 'U'; - pwdata_0_2 : in std_logic := 'U'; - pwdata_0_0 : in std_logic := 'U'; - dout : out std_logic_vector(7 downto 0); - psel : in std_logic_vector(11 to 11) := (others => 'U'); - prdata_iv_0_0_d0 : out std_logic; - prdata_iv_0_2 : out std_logic; - prdata_iv_0_0 : out std_logic_vector(2 to 2); - oen_7 : out std_logic; - oen_i : out std_logic_vector(7 downto 0); - paddr_0 : in std_logic_vector(3 downto 2) := (others => 'U'); - lclk_c : in std_logic := 'U'; - N_232_2 : out std_logic; - rdata61_2 : out std_logic; - N_6432 : out std_logic; - rstn : in std_logic := 'U'; - N_6439 : out std_logic; - N_6437 : out std_logic; - N_6436 : out std_logic; - N_6435 : out std_logic; - N_6434 : out std_logic; - rdata60_4 : in std_logic := 'U'; - N_6430 : out std_logic; - rdata59_4 : in std_logic := 'U'; - N_6429 : out std_logic; - N_6428 : out std_logic; - N_6459 : out std_logic; - readdata55_3 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - rdata60_4_0 : in std_logic := 'U'; - N_232_0 : out std_logic; - N_232_1 : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal rstn, \apbi.pirq[2]\, \apbi.pirq[12]\, - \apbi.pirq[13]\, \apbi.pirq[15]\, \ahbsi.haddr[2]\, - \ahbsi.haddr[3]\, \ahbsi.haddr[4]\, \ahbsi.haddr[5]\, - \ahbsi.haddr[6]\, \ahbsi.haddr[7]\, \ahbsi.haddr[8]\, - \ahbsi.haddr[9]\, \ahbsi.haddr[16]\, \ahbsi.haddr[17]\, - \ahbsi.haddr[18]\, \ahbsi.haddr[20]\, \ahbsi.haddr[21]\, - \ahbsi.haddr[22]\, \ahbsi.haddr[23]\, \ahbsi.haddr[26]\, - \ahbsi.haddr[27]\, \ahbsi.haddr[28]\, \ahbsi.haddr[30]\, - \ahbsi.hsel_i[0]\, \ahbsi.htrans[0]\, \ahbsi.htrans[1]\, - \ahbsi.hsize[1]\, \ahbsi.hburst[0]\, \ahbsi.hwdata[0]\, - \ahbsi.hwdata[1]\, \ahbsi.hwdata[2]\, \ahbsi.hwdata[3]\, - \ahbsi.hwdata[4]\, \ahbsi.hwdata[5]\, \ahbsi.hwdata[6]\, - \ahbsi.hwdata[7]\, \ahbsi.hwdata[8]\, \ahbsi.hwdata[9]\, - \ahbsi.hwdata[10]\, \ahbsi.hwdata[11]\, - \ahbsi.hwdata[12]\, \ahbsi.hwdata[13]\, - \ahbsi.hwdata[14]\, \ahbsi.hwdata[15]\, - \ahbsi.hwdata[16]\, \ahbsi.hwdata[17]\, - \ahbsi.hwdata[18]\, \ahbsi.hwdata[19]\, - \ahbsi.hwdata[20]\, \ahbsi.hwdata[21]\, - \ahbsi.hwdata[22]\, \ahbsi.hwdata[23]\, - \ahbsi.hwdata[24]\, \ahbsi.hwdata[25]\, - \ahbsi.hwdata[26]\, \ahbsi.hwdata[27]\, - \ahbsi.hwdata[28]\, \ahbsi.hwdata[29]\, - \ahbsi.hwdata[30]\, \ahbsi.hwdata[31]\, \ahbmo_0.hbusreq\, - \irqo_0.irl[0]\, \irqo_0.irl[1]\, \irqo_0.irl[2]\, - \irqo_0.irl[3]\, \dcomgen.un1_dcom0[12]\, - \dcomgen.un1_dcom0[13]\, \dcomgen.un1_dcom0[14]\, - \dcomgen.un1_dcom0[15]\, \dcomgen.un1_dcom0[16]\, - \dcomgen.un1_dcom0[17]\, \dcomgen.un1_dcom0[18]\, - \dcomgen.un1_dcom0[19]\, \ahbmo_1.haddr[0]\, - \ahbmo_1.haddr[1]\, \ahbmo_1.haddr[2]\, - \ahbmo_1.haddr[3]\, \ahbmo_1.haddr[4]\, - \ahbmo_1.haddr[5]\, \ahbmo_1.haddr[6]\, - \ahbmo_1.haddr[7]\, \ahbmo_1.haddr[8]\, - \ahbmo_1.haddr[9]\, \ahbmo_1.haddr[10]\, - \ahbmo_1.haddr[11]\, \ahbmo_1.haddr[12]\, - \ahbmo_1.haddr[13]\, \ahbmo_1.haddr[14]\, - \ahbmo_1.haddr[15]\, \ahbmo_1.haddr[16]\, - \ahbmo_1.haddr[17]\, \ahbmo_1.haddr[18]\, - \ahbmo_1.haddr[19]\, \ahbmo_1.haddr[20]\, - \ahbmo_1.haddr[21]\, \ahbmo_1.haddr[22]\, - \ahbmo_1.haddr[23]\, \ahbmo_1.haddr[24]\, - \ahbmo_1.haddr[25]\, \ahbmo_1.haddr[26]\, - \ahbmo_1.haddr[27]\, \ahbmo_1.haddr[28]\, - \ahbmo_1.haddr[29]\, \ahbmo_1.haddr[30]\, - \ahbmo_1.haddr[31]\, \ahbmo_1.hwrite\, - \ahbmo_1.hwdata[0]\, \ahbmo_1.hwdata[1]\, - \ahbmo_1.hwdata[2]\, \ahbmo_1.hwdata[3]\, - \ahbmo_1.hwdata[4]\, \ahbmo_1.hwdata[5]\, - \ahbmo_1.hwdata[6]\, \ahbmo_1.hwdata[7]\, - \ahbmo_1.hwdata[8]\, \ahbmo_1.hwdata[9]\, - \ahbmo_1.hwdata[10]\, \ahbmo_1.hwdata[11]\, - \ahbmo_1.hwdata[12]\, \ahbmo_1.hwdata[13]\, - \ahbmo_1.hwdata[14]\, \ahbmo_1.hwdata[15]\, - \ahbmo_1.hwdata[16]\, \ahbmo_1.hwdata[17]\, - \ahbmo_1.hwdata[18]\, \ahbmo_1.hwdata[19]\, - \ahbmo_1.hwdata[20]\, \ahbmo_1.hwdata[21]\, - \ahbmo_1.hwdata[22]\, \ahbmo_1.hwdata[23]\, - \ahbmo_1.hwdata[24]\, \ahbmo_1.hwdata[25]\, - \ahbmo_1.hwdata[26]\, \ahbmo_1.hwdata[27]\, - \ahbmo_1.hwdata[28]\, \ahbmo_1.hwdata[29]\, - \ahbmo_1.hwdata[30]\, \ahbmo_1.hwdata[31]\, - \memo.address[28]\, \memo.address[29]\, - \memo.address[30]\, \memo.address[31]\, \memo.data[0]\, - \memo.data[1]\, \memo.data[2]\, \memo.data[3]\, - \memo.data[4]\, \memo.data[5]\, \memo.data[6]\, - \memo.data[7]\, \memo.data[8]\, \memo.data[9]\, - \memo.data[10]\, \memo.data[11]\, \memo.data[12]\, - \memo.data[13]\, \memo.data[14]\, \memo.data[15]\, - \memo.data[16]\, \memo.data[17]\, \memo.data[18]\, - \memo.data[19]\, \memo.data[20]\, \memo.data[21]\, - \memo.data[22]\, \memo.data[23]\, \memo.data[24]\, - \memo.data[25]\, \memo.data[26]\, \memo.data[27]\, - \memo.data[28]\, \memo.data[29]\, \memo.data[30]\, - \memo.data[31]\, \ahbso_0.hready\, \ahbso_0.hresp[0]\, - \ahbso_0.hrdata[0]\, \ahbso_0.hrdata[1]\, - \ahbso_0.hrdata[2]\, \ahbso_0.hrdata[3]\, - \ahbso_0.hrdata[4]\, \ahbso_0.hrdata[5]\, - \ahbso_0.hrdata[6]\, \ahbso_0.hrdata[7]\, - \ahbso_0.hrdata[8]\, \ahbso_0.hrdata[9]\, - \ahbso_0.hrdata[10]\, \ahbso_0.hrdata[11]\, - \ahbso_0.hrdata[12]\, \ahbso_0.hrdata[13]\, - \ahbso_0.hrdata[14]\, \ahbso_0.hrdata[15]\, - \ahbso_0.hrdata[16]\, \ahbso_0.hrdata[17]\, - \ahbso_0.hrdata[18]\, \ahbso_0.hrdata[19]\, - \ahbso_0.hrdata[20]\, \ahbso_0.hrdata[21]\, - \ahbso_0.hrdata[22]\, \ahbso_0.hrdata[23]\, - \ahbso_0.hrdata[24]\, \ahbso_0.hrdata[25]\, - \ahbso_0.hrdata[26]\, \ahbso_0.hrdata[27]\, - \ahbso_0.hrdata[28]\, \ahbso_0.hrdata[29]\, - \ahbso_0.hrdata[30]\, \ahbso_0.hrdata[31]\, - \ahbso_1.hready\, \ahbso_1.hrdata[0]\, - \ahbso_1.hrdata[1]\, \ahbso_1.hrdata[2]\, - \ahbso_1.hrdata[3]\, \ahbso_1.hrdata[4]\, - \ahbso_1.hrdata[5]\, \ahbso_1.hrdata[6]\, - \ahbso_1.hrdata[7]\, \ahbso_1.hrdata[8]\, - \ahbso_1.hrdata[9]\, \ahbso_1.hrdata[10]\, - \ahbso_1.hrdata[11]\, \ahbso_1.hrdata[12]\, - \ahbso_1.hrdata[13]\, \ahbso_1.hrdata[14]\, - \ahbso_1.hrdata[15]\, \ahbso_1.hrdata[16]\, - \ahbso_1.hrdata[17]\, \ahbso_1.hrdata[18]\, - \ahbso_1.hrdata[19]\, \ahbso_1.hrdata[20]\, - \ahbso_1.hrdata[21]\, \ahbso_1.hrdata[22]\, - \ahbso_1.hrdata[23]\, \ahbso_1.hrdata[24]\, - \ahbso_1.hrdata[25]\, \ahbso_1.hrdata[26]\, - \ahbso_1.hrdata[27]\, \ahbso_1.hrdata[28]\, - \ahbso_1.hrdata[29]\, \ahbso_1.hrdata[30]\, - \ahbso_1.hrdata[31]\, \apbi.penable\, \apbi.paddr[2]\, - \apbi.paddr[3]\, \apbi.paddr[4]\, \apbi.paddr[5]\, - \apbi.paddr[6]\, \apbi.paddr[7]\, \apbi.pwrite\, - \apbi.pwdata[0]\, \apbi.pwdata[1]\, \apbi.pwdata[2]\, - \apbi.pwdata[3]\, \apbi.pwdata[4]\, \apbi.pwdata[5]\, - \apbi.pwdata[6]\, \apbi.pwdata[7]\, \apbi.pwdata[8]\, - \apbi.pwdata[9]\, \apbi.pwdata[10]\, \apbi.pwdata[11]\, - \apbi.pwdata[12]\, \apbi.pwdata[13]\, \apbi.pwdata[14]\, - \apbi.pwdata[15]\, \apbi.pwdata[16]\, \apbi.pwdata[17]\, - \apbi.pwdata[18]\, \apbi.pwdata[19]\, \apbi.pwdata[20]\, - \apbi.pwdata[21]\, \apbi.pwdata[22]\, \apbi.pwdata[23]\, - \apbi.pwdata[24]\, \apbi.pwdata[25]\, \apbi.pwdata[26]\, - \apbi.pwdata[27]\, \apbi.pwdata[28]\, \apbi.pwdata[29]\, - \apbi.pwdata[30]\, \apbi.pwdata[31]\, \ua1.un1_uart1[36]\, - \irqi_0.irl[0]\, \irqi_0.irl[1]\, \irqi_0.irl[2]\, - \irqi_0.irl[3]\, \gpioo.dout[0]\, \gpioo.dout[1]\, - \gpioo.dout[2]\, \gpioo.dout[3]\, \gpioo.dout[4]\, - \gpioo.dout[5]\, \gpioo.dout[6]\, \gpioo.dout[7]\, - \gpioo.oen[7]\, \gpio0.un1_grgpio0[69]\, - \gpio0.un1_grgpio0[71]\, \ahbso_7.hready\, - \ahbso_7.hrdata[0]\, \ahbso_7.hrdata[1]\, - \ahbso_7.hrdata[2]\, \ahbso_7.hrdata[3]\, - \ahbso_7.hrdata[4]\, \ahbso_7.hrdata[5]\, - \ahbso_7.hrdata[6]\, \ahbso_7.hrdata[7]\, - \ahbso_7.hrdata[8]\, \ahbso_7.hrdata[9]\, - \ahbso_7.hrdata[10]\, \ahbso_7.hrdata[11]\, - \ahbso_7.hrdata[12]\, \ahbso_7.hrdata[13]\, - \ahbso_7.hrdata[14]\, \ahbso_7.hrdata[15]\, - \ahbso_7.hrdata[16]\, \ahbso_7.hrdata[17]\, - \ahbso_7.hrdata[18]\, \ahbso_7.hrdata[19]\, - \ahbso_7.hrdata[20]\, \ahbso_7.hrdata[21]\, - \ahbso_7.hrdata[22]\, \ahbso_7.hrdata[23]\, - \ahbso_7.hrdata[24]\, \ahbso_7.hrdata[25]\, - \ahbso_7.hrdata[26]\, \ahbso_7.hrdata[27]\, - \ahbso_7.hrdata[28]\, \ahbso_7.hrdata[29]\, - \ahbso_7.hrdata[30]\, \ahbso_7.hrdata[31]\, - \apbo_13.prdata[0]\, \apbo_13.prdata[1]\, - \apbo_13.prdata[2]\, \apbo_13.prdata[3]\, - \apbo_13.prdata[4]\, \apbo_13.prdata[5]\, - \apbo_13.prdata[6]\, \apbo_13.prdata[7]\, - \apbo_13.prdata[8]\, \apbo_13.prdata[9]\, - \apbo_13.prdata[10]\, \apbo_13.prdata[11]\, - \apbo_13.prdata[12]\, \apbo_13.prdata[13]\, - \apbo_13.prdata[14]\, \apbo_13.prdata[15]\, - \apbo_13.prdata[16]\, \apbo_13.prdata[17]\, - \apbo_13.prdata[18]\, \apbo_13.prdata[19]\, - \apbo_13.prdata[20]\, \apbo_13.prdata[21]\, - \apbo_13.prdata[22]\, \apbo_13.prdata[23]\, - \apbo_13.prdata[24]\, \apbo_13.prdata[25]\, - \apbo_13.prdata[26]\, \apbo_13.prdata[27]\, - \apbo_13.prdata[28]\, \apbo_13.prdata[29]\, - \apbo_13.prdata[30]\, \apbo_13.prdata[31]\, - \apbo_15.prdata[0]\, \apbo_15.prdata[1]\, - \apbo_15.prdata[2]\, \apbo_15.prdata[3]\, - \apbo_15.prdata[4]\, \apbo_15.prdata[5]\, - \apbo_15.prdata[6]\, \apbo_15.prdata[7]\, - \apbo_15.prdata[8]\, \apbo_15.prdata[9]\, - \apbo_15.prdata[10]\, \apbo_15.prdata[11]\, - \apbo_15.prdata[12]\, \apbo_15.prdata[13]\, - \apbo_15.prdata[14]\, \apbo_15.prdata[15]\, - \apbo_15.prdata[16]\, \apbo_15.prdata[17]\, - \apbo_15.prdata[18]\, \apbo_15.prdata[19]\, - \apbo_15.prdata[20]\, \apbo_15.prdata[21]\, - \apbo_15.prdata[22]\, \apbo_15.prdata[23]\, - \apbo_15.prdata[24]\, \apbo_15.prdata[25]\, - \apbo_15.prdata[26]\, \apbo_15.prdata[27]\, - \apbo_15.prdata[28]\, \apbo_15.prdata[29]\, - \apbo_15.prdata[30]\, \apbo_15.prdata[31]\, - \coarse_time[0]\, \apbo_14.prdata[0]\, - \apbo_14.prdata[1]\, \apbo_14.prdata[2]\, - \apbo_14.prdata[3]\, \apbo_14.prdata[4]\, - \apbo_14.prdata[5]\, \apbo_14.prdata[6]\, - \apbo_14.prdata[7]\, \apbo_14.prdata[8]\, - \apbo_14.prdata[9]\, \apbo_14.prdata[10]\, - \apbo_14.prdata[11]\, \apbo_14.prdata[12]\, - \apbo_14.prdata[13]\, \apbo_14.prdata[14]\, - \apbo_14.prdata[15]\, \apbo_14.prdata[16]\, - \apbo_14.prdata[17]\, \apbo_14.prdata[18]\, - \apbo_14.prdata[19]\, \apbo_14.prdata[20]\, - \apbo_14.prdata[21]\, \apbo_14.prdata[22]\, - \apbo_14.prdata[23]\, \apbo_14.prdata[24]\, - \apbo_14.prdata[25]\, \apbo_14.prdata[26]\, - \apbo_14.prdata[27]\, \apbo_14.prdata[28]\, - \apbo_14.prdata[29]\, \apbo_14.prdata[30]\, - \apbo_14.prdata[31]\, \ahbmo_3.htrans[0]\, - \ahbmo_3.htrans[1]\, \ahbmo_3.haddr[0]\, - \ahbmo_3.haddr[1]\, \ahbmo_3.haddr[2]\, - \ahbmo_3.haddr[3]\, \ahbmo_3.haddr[4]\, - \ahbmo_3.haddr[5]\, \ahbmo_3.haddr[6]\, - \ahbmo_3.haddr[7]\, \ahbmo_3.haddr[8]\, - \ahbmo_3.haddr[9]\, \ahbmo_3.haddr[10]\, - \ahbmo_3.haddr[11]\, \ahbmo_3.haddr[12]\, - \ahbmo_3.haddr[13]\, \ahbmo_3.haddr[14]\, - \ahbmo_3.haddr[15]\, \ahbmo_3.haddr[16]\, - \ahbmo_3.haddr[17]\, \ahbmo_3.haddr[18]\, - \ahbmo_3.haddr[19]\, \ahbmo_3.haddr[20]\, - \ahbmo_3.haddr[21]\, \ahbmo_3.haddr[22]\, - \ahbmo_3.haddr[23]\, \ahbmo_3.haddr[24]\, - \ahbmo_3.haddr[25]\, \ahbmo_3.haddr[26]\, - \ahbmo_3.haddr[27]\, \ahbmo_3.haddr[28]\, - \ahbmo_3.haddr[29]\, \ahbmo_3.haddr[30]\, - \ahbmo_3.haddr[31]\, \ahbmo_3.hwrite\, \ahbmo_3.hsize[0]\, - \ahbmo_3.hsize[1]\, \ahbmo_3.hburst[0]\, - \ahbmo_3.hburst[1]\, \ahbmo_3.hburst[2]\, - \sr1.r.mcfg1.ioen\, \sr1.r.mcfg1.brdyen\, - \sr1.r.mcfg2.rmw\, \sr1.r.mcfg1.bexcen\, - \sr1.r.mcfg2.rambanksz[0]\, \sr1.r.mcfg2.rambanksz[1]\, - \sr1.r.mcfg2.rambanksz[3]\, \sr1.r.mcfg2.ramwidth[1]\, - \sr1.r.mcfg1.iows[2]\, \sr1.r.mcfg1.iows[3]\, - \sr1.r.mcfg2.ramwidth[0]\, \sr1.r.mcfg2.ramrws[1]\, - \sr1.r.mcfg2.ramwws[0]\, \sr1.r.mcfg2.ramwws[1]\, - \sr1.r.mcfg1.romrws[1]\, \sr1.r.mcfg1.romrws[2]\, - \sr1.r.mcfg1.romrws[3]\, \sr1.r.mcfg1.romwws[0]\, - \sr1.r.mcfg1.romwws[1]\, \sr1.r.mcfg1.romwws[2]\, - \sr1.r.mcfg1.romwws[3]\, \sr1.r.mcfg1.romwidth[0]\, - \sr1.r.mcfg1.romwidth[1]\, \irqo_0.intack\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.address[0]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.address[1]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[5]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[8]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[10]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[13]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[24]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[29]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.size[0]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[8]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[10]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[13]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[24]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[29]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un59_nbo\, - \ahb0.comb.arb_1\, lclk_i, \sr1.iosn[93]\, - \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d\, \state_RNIFS55[4]\, - \sr1.ctrl.un1_r.brmw_i\, N_78, N_262, N_264, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.v.werr_2_m_0\, N_6377, - \ahbmo_0.hwdata[6]\, N_6550, \ahbmo_0.hwdata[12]\, - \ahbmo_3.hwdata[0]\, \ahbmo_3.hwdata[1]\, - \ahbmo_3.hwdata[2]\, \ahbmo_3.hwdata[3]\, - \ahbmo_3.hwdata[4]\, \ahbmo_3.hwdata[5]\, - \ahbmo_3.hwdata[6]\, \ahbmo_3.hwdata[7]\, - \ahbmo_3.hwdata[8]\, \ahbmo_3.hwdata[9]\, - \ahbmo_3.hwdata[10]\, \ahbmo_3.hwdata[11]\, - \ahbmo_3.hwdata[12]\, \ahbmo_3.hwdata[13]\, - \ahbmo_3.hwdata[14]\, \ahbmo_3.hwdata[15]\, - \ahbmo_3.hwdata[16]\, \ahbmo_3.hwdata[17]\, - \ahbmo_3.hwdata[18]\, \ahbmo_3.hwdata[19]\, - \ahbmo_3.hwdata[20]\, \ahbmo_3.hwdata[21]\, - \ahbmo_3.hwdata[22]\, \ahbmo_3.hwdata[23]\, - \ahbmo_3.hwdata[24]\, \ahbmo_3.hwdata[25]\, - \ahbmo_3.hwdata[26]\, \ahbmo_3.hwdata[27]\, - \ahbmo_3.hwdata[28]\, \ahbmo_3.hwdata[29]\, - \ahbmo_3.hwdata[30]\, \ahbmo_3.hwdata[31]\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.IdlePhase\, - \apb0.N_770\, \gpt.timer0.r.timers_2.value[0]\, - \gpt.timer0.r.timers_2.value[6]\, \gpt.timer0.r.dishlt\, - \gpt.timer0.r.reload[6]\, \gpt.timer0.r.reload[7]\, - \gpt.timer0.r.timers_2.reload[4]\, - \gpt.timer0.r.timers_2.reload[5]\, - \gpt.timer0.r.timers_2.reload[6]\, - \gpt.timer0.r.timers_2.reload[7]\, - \gpt.timer0.r.timers_2.reload[8]\, - \gpt.timer0.r.timers_2.reload[10]\, - \gpt.timer0.r.timers_2.reload[11]\, - \gpt.timer0.r.timers_2.reload[12]\, - \gpt.timer0.r.timers_2.reload[28]\, - \gpt.timer0.r.scaler[4]\, \irqctrl.irqctrl0.r.ilevel[4]\, - \irqctrl.irqctrl0.r.ilevel[5]\, - \irqctrl.irqctrl0.r.ilevel[6]\, - \irqctrl.irqctrl0.r.ilevel[7]\, - \irqctrl.irqctrl0.r.ilevel[8]\, - \irqctrl.irqctrl0.r.ilevel[10]\, - \irqctrl.irqctrl0.r.ilevel[12]\, - \irqctrl.irqctrl0.r.iforce_0[5]\, - \irqctrl.irqctrl0.r.iforce_0[6]\, - \irqctrl.irqctrl0.r.iforce_0[7]\, - \irqctrl.irqctrl0.r.iforce_0[10]\, - \irqctrl.irqctrl0.r.iforce_0[12]\, - \irqctrl.irqctrl0.r.ipend[11]\, \ua1.uart1.r.tcnt[0]\, - \ua1.uart1.r.tcnt[1]\, \ua1.uart1.r.rcnt[0]\, - \ua1.uart1.r.rcnt[1]\, \ua1.uart1.r.paren\, - \ua1.uart1.r.delayirqen\, \ua1.uart1.r.breakirqen\, - \ua1.uart1.r.tsemptyirqen\, \ua1.uart1.r.brate[0]\, - \ua1.uart1.r.brate[6]\, \ua1.uart1.r.brate[7]\, - \ua1.uart1.r.brate[8]\, \ua1.uart1.r.brate[9]\, - \ua1.uart1.r.brate[10]\, \ua1.uart1.r.frame\, - \ua1.uart1.N_156\, \ahbmo_1.hbusreq_i_3\, - \ahbmi.hrdata[0]\, \ahbmi.hrdata[1]\, \ahbmi.hrdata[2]\, - \ahbmi.hrdata[3]\, \ahbmi.hrdata[4]\, \ahbmi.hrdata[5]\, - \ahbmi.hrdata[7]\, \ahbmi.hrdata[8]\, \ahbmi.hrdata[9]\, - \ahbmi.hrdata[10]\, \ahbmi.hrdata[11]\, - \ahbmi.hrdata[12]\, \ahbmi.hrdata[13]\, - \ahbmi.hrdata[14]\, \ahbmi.hrdata[15]\, - \ahbmi.hrdata[16]\, \ahbmi.hrdata[17]\, - \ahbmi.hrdata[21]\, \ahbmi.hrdata[22]\, - \ahbmi.hrdata[23]\, \ahbmi.hrdata[24]\, - \ahbmi.hrdata[26]\, \ahbmi.hrdata[27]\, - \ahbmi.hrdata[28]\, \ahbmi.hrdata[29]\, - \ahbmi.hrdata[31]\, \ahbmi.hrdata[6]\, \dbgo_0.error_i_2\, - \data_in[0]\, \data_in[1]\, \data_in[2]\, \data_in[3]\, - \data_in[4]\, \data_in[5]\, \data_in[6]\, \data_in[7]\, - \data_in[8]\, \data_in[9]\, \data_in[10]\, \data_in[11]\, - \data_in[12]\, \data_in[13]\, \data_in[14]\, - \data_in[15]\, \data_in[16]\, \data_in[17]\, - \data_in[18]\, \data_in[19]\, \data_in[20]\, - \data_in[21]\, \data_in[22]\, \data_in[23]\, - \data_in[24]\, \data_in[25]\, \data_in[26]\, - \data_in[27]\, \data_in[28]\, \data_in[29]\, - \data_in[30]\, \data_in[31]\, \gpio_in[0]\, \gpio_in[1]\, - \gpio_in[2]\, \gpio_in[3]\, \gpio_in[4]\, \gpio_in[5]\, - \gpio_in[6]\, \gpio_in[7]\, rstraw_c, clk_c, - \address_c[0]\, \address_c[1]\, \address_c[2]\, - \address_c[3]\, \address_c[4]\, \address_c[5]\, - \address_c[6]\, \address_c[7]\, \address_c[8]\, - \address_c[9]\, \address_c[10]\, \address_c[11]\, - \address_c[12]\, \address_c[13]\, \address_c[14]\, - \address_c[15]\, \address_c[16]\, \address_c[17]\, - \address_c[18]\, \address_c[19]\, \address_c[20]\, - \address_c[21]\, \address_c[22]\, \address_c[23]\, - \address_c[24]\, \address_c[25]\, \address_c[26]\, - \address_c[27]\, dsutx_c, dsurx_c, txd1_c, rxd1_c, - \ramsn_c[0]\, \ramsn_c[1]\, \ramsn_c[2]\, \ramsn_c[3]\, - \ramoen_c[0]\, \ramoen_c[1]\, \ramoen_c[2]\, - \ramoen_c[3]\, \rwen_c[0]\, \rwen_c[1]\, \rwen_c[2]\, - \rwen_c[3]\, oen_c, writen_c, read_c, iosn_c, - \romsn_c[0]\, \romsn_c[1]\, lclk_c, nBWa_c, nBWb_c, - nBWc_c, nBWd_c, nBWE_c, \VCC\, nCE1_c, CE2_c, nCE3_c, - \GND\, clk49_152MHz_c, \sdo_adc_c[0]\, \sdo_adc_c[1]\, - \sdo_adc_c[2]\, \sdo_adc_c[3]\, \sdo_adc_c[4]\, - \sdo_adc_c[5]\, \sdo_adc_c[6]\, \sdo_adc_c[7]\, cnv_ch1_c, - sck_ch1_c, Bias_Fails_c, \ahbsi.hsize[0]\, - \ahbsi.haddr[0]\, \ahbmo_3.hbusreq_i_3\, \sr1.iosn[100]\, - \sr1.iosn_1[101]\, \ahbsi.hmbsel_1[0]\, \ahbsi.haddr[1]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un60_nbo\, N_5054, - \ahbmo_0.htrans[1]\, \ahbsi.hmbsel[0]\, - \ahbmo_1.htrans[1]\, \ahbmi.hgrant[3]\, - \l3.cpu.0.u0.p0.c0mmu.a0.htrans_0_sqmuxa_2\, - \l3.cpu.0.u0.p0.c0mmu.a0.v.lb_0_sqmuxa_1\, - \ahbmi.hresp[0]\, \ahb0.bco_msb_1[1]\, - \ahb0.bco_msb_1_m[1]\, \ahb0.l1_0_m[1]\, - \ahb0.un1_nhmaster_0_sqmuxa_1\, - \ahb0.comb.nhmaster_1_i[0]\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.un1_dmain_6\, - \ahbmo_0.hlock\, \ahbmo_0.hwdata[18]\, - \ahbso_6.hrdata[26]\, \ahbso_6.hrdata[11]\, - \ahbsi.hwdata_m_0[15]\, \ahbsi.hwdata_m[15]\, N_546, - N_466, \ahbmo_0.hwdata[3]\, \ahbmo_0.haddr[17]\, - \ahbmo_0.haddr[16]\, \ahbmo_0.haddr[6]\, - \ahbmo_0.haddr[7]\, \ahbmo_0.haddr[27]\, - \ahbmo_0.haddr[11]\, \ahbsi.haddr[11]\, \ahbmi.hgrant[0]\, - \ahbso_6.hrdata[28]\, \ahbso_6.hrdata[27]\, - \ahbso_6.hrdata[23]\, \ahbso_6.hrdata[22]\, - \ahbso_6.hrdata[21]\, \ahbso_6.hrdata[15]\, - \ahbso_6.hrdata[14]\, \ahbso_6.hrdata[13]\, - \ahbso_6.hrdata[4]\, \ahbso_6.hrdata[3]\, - \ahbso_6.hrdata[2]\, \ahbso_6.hrdata[1]\, - \ahbso_6.hrdata[0]\, \ahbmo_0.haddr[31]\, - \ahbmo_0.haddr[30]\, \ahbmi.hgrant[1]\, - \l3.cpu.0.u0.p0.c0mmu.a0.hsize_5[1]\, \apbo_0.prdata[20]\, - \apb0.N_78\, \apb0.N_749\, \apb0.N_750\, \apb0.N_769\, - \apb0.N_773\, \apb0.N_796\, \apb0.N_116\, - \gpt.timer0.N_228\, \gpt.timer0.r.timers_2.value_m[20]\, - \gpt.timer0.r.timers_2.reload_m[20]\, \gpt.timer0.N_240\, - \lfrtimemanagement_0.r.ctrl2\, \ua1.uart1.uartop.rdata59\, - \ua1.uart1.uartop.rdata60\, \ua1.uart1.uartop.rdata61\, - \ua1.uart1.N_232\, \apbi.psel_1[7]\, \apbi.psel[11]\, - N_6455, \apbo_3.prdata[31]\, - \dcomgen.dcom0.dcom_uart0.N_127\, \apbo_3.prdata[14]\, - \lfrtimemanagement_0.un1_apbi_7_1\, \apbo_1.prdata[31]\, - \irqctrl.irqctrl0.N_898\, - \irqctrl.irqctrl0.prdata_1_sqmuxa\, - \irqctrl.irqctrl0.prdata_0_sqmuxa\, - \gpt.timer0.comb.readdata55\, - \gpt.timer0.comb.readdata55_3\, - \gpt.timer0.comb.2.readdata51_1\, - \ua1.uart1.uartop.rdata61_2\, - \dcomgen.dcom0.dcom_uart0.N_335\, \ua1.uart1.N_227\, - \ua1.uart1.uartop.rdata60_1\, - \gpt.timer0.comb.1.un1_apbi_2\, - \ua1.uart1.uartop.rdata62_3\, - \ua1.uart1.uartop.rdata59_4\, \ua1.uart1.rdata_3_sqmuxa\, - \ua1.uart1.uartop.thempty_1_m\, - \ua1.uart1.rdata_4_sqmuxa\, - \dcomgen.dcom0.dcom_uart0.N_330\, \apbo_1.prdata[28]\, - \apbo_1.prdata[22]\, \ua1.uart1.rdata_0_sqmuxa\, - \ua1.uart1.uartop.un1_r.tcnt_i\, - \ua1.uart1.uartop.rdata_2[0]\, \ua1.uart1.r.debug_m\, - \ua1.uart1.uartop.rdata_17_m[0]\, N_5062, - \ahb0.comb.1.4.un51_ioen_NE\, \sr1.ctrl.brmw_1\, - \ahb0.comb.7.4.un315_ioen_NE\, \sr1.iosn[101]\, - \ahbsi.hwrite\, \ahbsi.haddr[29]\, \ahbsi.hburst[2]\, - \ahbsi.hburst[1]\, \apbo_7.prdata[5]\, - \ua1.uart1.uartop.rdata_2_m[5]\, \ua1.uart1.r.parerr_m\, - \ua1.uart1.r.brate_m[5]\, - \ua1.uart1.uartop.rdata_17_m[5]\, - \irqctrl.irqctrl0.N_365\, \irqctrl.irqctrl0.N_367\, - \gpt.timer0.comb.1.readdata_9[5]\, - \gpt.timer0.r.scaler_m[5]\, \gpt.timer0.r.reload_m[5]\, - \gpt.timer0.comb.readdata56\, - \gpt.timer0.r.timers_2.value_m[5]\, - \gpt.timer0.r.timers_2.chain_m\, - \gpio0.grgpio0.comb.readdata_2_m[5]\, \ahbsi.haddr[13]\, - \ahbmo_0.haddr[13]\, \lfrtimemanagement_0.un1_apbi_8\, - \ahbmo_0.haddr[28]\, \ahbmo_0.haddr[2]\, - \dcomgen.dcom0.dcom_uart0.N_331\, - \ua1.uart1.uartop.rdata60_4\, \gpt.timer0.r.reload_m[3]\, - \gpt.timer0.comb.readdata57\, \ua1.uart1.uartop.rdata62\, - \irqctrl.irqctrl0.N_863\, \irqctrl.irqctrl0.N_865\, - \gpt.timer0.r.reload_m[2]\, N_6432, - \gpt.timer0.comb.1.readdata_9[0]\, - \gpt.timer0.r.timers_2.enable_m\, - \gpt.timer0.r.reload_m[0]\, \gpt.timer0.r.scaler_m[0]\, - \gpt.timer0.r.timers_2.reload_m[0]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.hwrite_1_m_0\, - \ahbmo_0.hwdata[17]\, \dcomgen.dcom0.dcom_uart0.N_86\, - \ua1.uart1.uartop.rhalffull_1_m\, - \ua1.uart1.r.extclken_m\, \ua1.uart1.r.tfifoirqen_m\, - \ua1.uart1.r.rfifoirqen_m\, - \ua1.uart1.uartop.rdata_17_m[4]\, \apbi.pirq[8]\, - \apbi.pirq[9]\, \gpt.timer0.r.timers_2.value_m[12]\, - \apbo_3.prdata[16]\, \apbo_3.prdata[18]\, - \gpt.timer0.r.timers_2.value_m[22]\, - \gpt.timer0.r.timers_2.value_m[26]\, - \gpt.timer0.r.timers_2.value_m[28]\, \apbo_3.prdata[30]\, - \gpt.timer0.r.timers_2.value_m[11]\, \apbo_3.prdata[17]\, - \apbo_3.prdata[19]\, \apbo_3.prdata[25]\, - \apbo_3.prdata[29]\, \gpt.timer0.r.timers_2.value_m[10]\, - \gpt.timer0.r.timers_2.value_m[24]\, - \gpt.timer0.r.timers_2.value_m[15]\, - \gpt.timer0.r.timers_2.value_m[21]\, - \gpt.timer0.r.timers_2.reload_m[21]\, - \gpt.timer0.comb.1.readdata_9[27]\, - \gpt.timer0.r.timers_2.value_m[27]\, - \gpt.timer0.r.timers_2.reload_m[27]\, - \gpt.timer0.r.timers_2.value_m[13]\, \apbo_3.prdata[23]\, - \apbi.psel[15]\, \ahbsi.hwdata_m_0[14]\, - \ahbsi.hwdata_m[14]\, N_6430, N_6428, N_6429, N_6436, - N_6434, N_6435, N_6439, N_6437, \ahbsi.hwdata_m[7]\, - \ahbsi.hwdata_m_0[12]\, \ahbsi.hwdata_m[12]\, N_468, - N_463, N_461, N_459, N_458, N_510, \ahbmo_0.hwdata[4]\, - \ahbsi.hwdata_m[20]\, \ahbmo_0.hwdata[31]\, - \ahbmo_0.hwdata[26]\, \ahbmo_0.hwdata[15]\, - \ahbmo_0.hwdata[7]\, N_139, N_138, \ahbmo_0.hwdata[16]\, - \apbi.psel[0]\, \ahbmo_0.haddr[19]\, \ahbsi.haddr[19]\, - \ahbsi.haddr[15]\, \ahbmo_0.haddr[15]\, - \ahbmo_0.haddr[14]\, \ahbsi.haddr[14]\, - \ahbmo_0.haddr[20]\, \ahbmo_0.haddr[5]\, N_6459, - \ahbmo_0.haddr[8]\, \apbo_0.prdata[21]\, - \apbo_0.prdata[28]\, \apbo_0.prdata[27]\, - \ahbsi.haddr[25]\, \ahbsi.haddr[24]\, \ahbmo_0.haddr[22]\, - \ahbmo_0.haddr[12]\, \ahbsi.haddr[12]\, N_5070, - \ahbmo_0.haddr[3]\, \ahbmo_0.haddr[9]\, - \ahbmo_0.haddr[10]\, \ahbsi.haddr[10]\, - \ahbmo_0.hwdata[30]\, \ahbmo_0.hwdata[28]\, - \ahbmo_0.hwdata[14]\, \ahbso_6.hrdata[25]\, - \ahbso_6.hrdata[9]\, \ahbmo_0.haddr[25]\, - \ahbmo_0.haddr[24]\, \ahbmo_0.haddr[21]\, - \ahbmo_0.haddr[29]\, \gpt.timer0.r.timers_2.reload_m[9]\, - \gpt.timer0.r.timers_2.value_m[9]\, \gpt.timer0.N_217\, - \gpt.timer0.r.timers_2.value_m[7]\, - \gpt.timer0.r.scaler_m[7]\, \gpt.timer0.N_229\, - \gpt.timer0.N_215\, \gpt.timer0.N_218\, - \gpt.timer0.r.scaler_m[6]\, - \gpt.timer0.r.timers_2.value_m[8]\, \gpt.timer0.N_216\, - \gpt.timer0.N_214\, \gpt.timer0.r.timers_2.irqpen_m\, - \gpt.timer0.comb.1.readdata_9[4]\, - \gpt.timer0.r.timers_2.value_m[4]\, - \gpt.timer0.r.reload_m[4]\, \gpt.timer0.N_219\, - \gpt.timer0.N_236\, \gpt.timer0.N_220\, - \gpt.timer0.comb.1.readdata_9_i_m[1]\, - \gpt.timer0.r.scaler_i_m[1]\, \irqctrl.irqctrl0.N_363\, - \irqctrl.irqctrl0.N_361\, \irqctrl.irqctrl0.N_841\, - \irqctrl.irqctrl0.N_842\, \irqctrl.irqctrl0.N_839\, - \apbo_2.prdata[2]\, \irqctrl.irqctrl0.N_470\, - \irqctrl.irqctrl0.N_467\, \irqctrl.irqctrl0.N_468\, - \irqctrl.irqctrl0.N_473\, \irqctrl.irqctrl0.N_474\, - \irqctrl.irqctrl0.N_471\, \irqctrl.irqctrl0.N_472\, - \irqctrl.irqctrl0.N_478\, \irqctrl.irqctrl0.N_476\, - \apbo_2.prdata[15]\, \apbo_2.prdata[3]\, - \irqctrl.irqctrl0.N_861\, \irqctrl.irqctrl0.N_859\, - \irqctrl.irqctrl0.r.iforce_0_m[4]\, - \irqctrl.irqctrl0.r.ipend_m[4]\, \ua1.uart1.N_223\, - \ua1.uart1.N_220\, \ua1.uart1.r.break_m\, - \ua1.uart1.r.parsel_m_0\, \ua1.uart1.r.brate_m[4]\, - \ua1.uart1.uartop.rdata_2_m[4]\, \ua1.uart1.r.ovf_m\, - \ua1.uart1.r.flow_m\, \ua1.uart1.uartop.rdata_2_m[6]\, - \ua1.uart1.r.brate_m[11]\, \apbo_7.prdata[0]\, - \dcomgen.dcom0.dcom_uart0.N_336\, - \dcomgen.dcom0.dcom_uart0.N_334\, - \dcomgen.dcom0.dcom_uart0.N_333\, - \dcomgen.dcom0.dcom_uart0.N_332\, - \dcomgen.dcom0.dcom_uart0.N_85\, \ahbmi.hrdata[18]\, - \ahbso_6.hrdata[30]\, \ahbso_6.hrdata[16]\, N_467, N_462, - N_457, \ahbmo_0.hwdata[19]\, \ahbmo_0.haddr[23]\, - \ahbmo_0.haddr[26]\, \ahbmo_0.haddr[18]\, - \ahbmo_0.haddr[4]\, \ahbso_6.hrdata[29]\, - \ahbso_6.hrdata[19]\, \ahbso_6.hrdata[18]\, - \ahbso_6.hrdata[17]\, \ahbso_6.hrdata[12]\, - \ahbso_6.hrdata[10]\, \ahbso_6.hrdata[8]\, - \ahbso_6.hrdata[7]\, \ahbso_6.hrdata[6]\, - \ahbso_6.hrdata[5]\, \ahbmi.hrdata[30]\, - \r.hmaster_0_0_RNIFCVH1_0[1]\, \ahb0.hrdata_1_0_1[1]\, - \ahb0.comb.nhmaster_1_iv_0[1]\, \ahbmo_0.htrans_tz[1]\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_0_N_15_i_0_li\, - m26_m1_e, rstoutl_RNIGJKSJO, - \lfrtimemanagement_0.un1_apbi_7_3\, - \gpt.timer0.comb.un1_apbi_0\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un91_nbo_i_0\, - \lpp_bootloader_1.ahbrom_1.N_95_i_0\, - \lpp_bootloader_1.ahbrom_1.N_90_i_0\, - \lpp_bootloader_1.ahbrom_1.N_103_i_0\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a0_6_i_0\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a1_6_i_0\, - \DMAIn.Lock_RNIU86D\, \r.timers_2.value_RNIBAHH[1]\, - \r.timers_2.restart_RNIIKBB\, - \r.timers_2.reload_RNIRDRG[1]\, \r.reload_RNI6SNI[1]\, - \r.rcnt_RNI8FBM3[1]\, - \irqctrl.irqctrl0.prdata_11_m_1_0[4]\, - \irqctrl.irqctrl0.prdata_13_m_1_0[4]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[13]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[13]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[1]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[1]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[14]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[14]\, - \gpio0.grgpio0.apbo.prdata_iv_0[1]\, - \gpio0.grgpio0.apbo.prdata_iv_0[3]\, - \gpio0.grgpio0.apbo.prdata_iv_0_0[2]\, - \gpt.timer0.readdata_1_iv_0[13]\, - \gpt.timer0.readdata_1_iv_0[15]\, - \gpt.timer0.readdata_1_iv_0[24]\, - \gpt.timer0.readdata_1_iv_0[26]\, - \gpt.timer0.readdata_1_iv_0[22]\, - \ua1.uart1.uartop.rdata_17_m_0[6]\, - \ua1.uart1.rdata_iv_0_a2_3_0[7]\, - \gpt.timer0.readdata_iv_3[3]\, - \gpt.timer0.readdata_iv_3[2]\, - \l3.cpu.0.u0.p0.c0mmu.a0.un1_htrans_1_sqmuxa_0\, - \ua1.uart1.rdata_iv_2[3]\, \ua1.uart1.rdata_iv_2[2]\, - \ua1.uart1.rdata_iv_0_2[1]\, - \ahb0.comb.0.4.un6_ioen_NE_0\, \ahbsi.hwrite_m_0_0\, - clk_c_i, \SSRAM_0.state_i[3]\, lclk_i_i, - \coarse_time_i[0]\, \gpioo.oen_i[7]\, \gpioo.oen_i[6]\, - \gpioo.oen_i[5]\, \gpioo.oen_i[4]\, \gpioo.oen_i[3]\, - \gpioo.oen_i[2]\, \gpioo.oen_i[1]\, \gpioo.oen_i[0]\, - \apbi.pwdata_i[7]\, \apbi.pwdata_i[6]\, - \apbi.pwdata_i[5]\, \apbi.pwdata_i[4]\, - \apbi.pwdata_i[3]\, \apbi.pwdata_i[2]\, - \apbi.pwdata_i[1]\, \apbi.pwdata_i[0]\, - \memo.bdrive_i[3]\, \memo.bdrive_i[2]\, - \memo.bdrive_i[1]\, \memo.bdrive_i[0]\, rstn_i, - \ahbmi.hrdata_0[18]\, \ua1.uart1.uartop.rdata62_0\, - \ua1.uart1.uartop.rdata60_4_0\, \ua1.uart1.N_232_0\, - \ua1.uart1.N_232_1\, \gpt.timer0.N_240_0\, - \gpt.timer0.readdata_1_sqmuxa_1_0\, - \gpt.timer0.v.timers_2.value_0_sqmuxa_0\, - clk49_152MHz_c_0, \ahbmi.hrdata_0[27]\, - \ahbmi.hrdata_0[26]\, \ahbmi.hrdata_0[24]\, - \ahbmi.hrdata_0[23]\, \ahbmi.hrdata_0[22]\, - \ahbmi.hrdata_0[21]\, \ahbmi.hrdata_0[17]\, - \ahbmi.hrdata_0[16]\, \ahbmi.hrdata_0[15]\, - \ahbmi.hrdata_0[14]\, \ahbmi.hrdata_0[13]\, - \ahbmi.hrdata_0[12]\, \ahbmi.hrdata_0[11]\, - \ahbmi.hrdata_0[10]\, \ahbmi.hrdata_0[9]\, - \ahbmi.hrdata_0[8]\, \ahbmi.hrdata_0[7]\, - \ahbmi.hrdata_0[4]\, \ahbmi.hrdata_0[3]\, - \ahbmi.hrdata_0[2]\, \ahbmi.hrdata_0[1]\, - \ahbmi.hrdata_0[0]\, N_264_0, N_262_0, N_78_0, - \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d_0\, \sr1.iosn_0[93]\, - \sr1.iosn_1[93]\, \sr1.iosn_2[93]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[1]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[0]\, - \apbi.pwdata_0[15]\, \apbi.pwdata_0[14]\, - \apbi.pwdata_0[13]\, \apbi.pwdata_0[12]\, - \apbi.pwdata_0[11]\, \apbi.pwdata_0[10]\, - \apbi.pwdata_0[9]\, \apbi.pwdata_0[8]\, - \apbi.pwdata_0[7]\, \apbi.pwdata_0[6]\, - \apbi.pwdata_0[5]\, \apbi.pwdata_0[4]\, - \apbi.pwdata_1[4]\, \apbi.pwdata_0[3]\, - \apbi.pwdata_1[3]\, \apbi.pwdata_0[2]\, - \apbi.pwdata_0[1]\, \apbi.pwdata_1[1]\, - \apbi.pwdata_0[0]\, \apbi.paddr_0[4]\, \apbi.paddr_0[3]\, - \apbi.paddr_0[2]\, \apbi.paddr_1[2]\, \apbi.paddr_2[2]\, - \ahbsi.hmaster_0[1]\, N_6455_0, GND_0, VCC_0 : std_logic; - - for all : gptimer - Use entity work.gptimer(DEF_ARCH); - for all : ssram_plugin - Use entity work.ssram_plugin(DEF_ARCH); - for all : leon3s - Use entity work.leon3s(DEF_ARCH); - for all : irqmp - Use entity work.irqmp(DEF_ARCH); - for all : apbuart - Use entity work.apbuart(DEF_ARCH); - for all : apbctrl - Use entity work.apbctrl(DEF_ARCH); - for all : ahbram - Use entity work.ahbram(DEF_ARCH); - for all : lpp_bootloader - Use entity work.lpp_bootloader(DEF_ARCH); - for all : lpp_top_lfr_wf_picker - Use entity work.lpp_top_lfr_wf_picker(DEF_ARCH); - for all : ahbuart - Use entity work.ahbuart(DEF_ARCH); - for all : ahbctrl - Use entity work.ahbctrl(DEF_ARCH); - for all : apb_lfr_time_management - Use entity work.apb_lfr_time_management(DEF_ARCH); - for all : rstgen - Use entity work.rstgen(DEF_ARCH); - for all : mctrl - Use entity work.mctrl(DEF_ARCH); - for all : grgpio - Use entity work.grgpio(DEF_ARCH); -begin - - - writen_pad : OUTBUF - port map(D => writen_c, PAD => writen); - - \spw_txsn_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => spw_txsn(1)); - - \spw_txdn_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => spw_txdn(1)); - - \rwen_pad[2]\ : OUTBUF - port map(D => \rwen_c[2]\, PAD => rwen(2)); - - \pci_ad_pad[20]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(20)); - - \address_pad[16]\ : OUTBUF - port map(D => \address_c[16]\, PAD => address(16)); - - \data_pad[20]\ : BIBUF - port map(PAD => data(20), D => \memo.data[20]\, E => - \memo.bdrive_i[1]\, Y => \data_in[20]\); - - \spw_txsn_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => spw_txsn(0)); - - \spw_txdn_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => spw_txdn(0)); - - \gpt.timer0\ : gptimer - port map(scaler_4 => \gpt.timer0.r.scaler[4]\, pwdata_1_3 - => \apbi.pwdata_1[4]\, pwdata_1_0 => \apbi.pwdata_1[1]\, - pwdata_1_2 => \apbi.pwdata_1[3]\, paddr(6) => - \apbi.paddr[6]\, paddr(5) => \apbi.paddr[5]\, paddr(4) - => \apbi.paddr[4]\, paddr(3) => \apbi.paddr[3]\, - paddr(2) => \apbi.paddr[2]\, value_6 => - \gpt.timer0.r.timers_2.value[6]\, value_0 => - \gpt.timer0.r.timers_2.value[0]\, paddr_2(2) => - \apbi.paddr_2[2]\, pirq(9) => \apbi.pirq[9]\, pirq(8) => - \apbi.pirq[8]\, readdata_9_5 => - \gpt.timer0.comb.1.readdata_9[5]\, readdata_9_0 => - \gpt.timer0.comb.1.readdata_9[0]\, readdata_9_27 => - \gpt.timer0.comb.1.readdata_9[27]\, readdata_9_4 => - \gpt.timer0.comb.1.readdata_9[4]\, paddr_1(2) => - \apbi.paddr_1[2]\, reload_RNIRDRG(1) => - \r.timers_2.reload_RNIRDRG[1]\, value_RNIBAHH(1) => - \r.timers_2.value_RNIBAHH[1]\, reload_RNI6SNI(1) => - \r.reload_RNI6SNI[1]\, scaler_i_m(1) => - \gpt.timer0.r.scaler_i_m[1]\, reload_m_0_2 => - \gpt.timer0.r.reload_m[2]\, reload_m_0_3 => - \gpt.timer0.r.reload_m[3]\, reload_m_0_0 => - \gpt.timer0.r.timers_2.reload_m[0]\, scaler_m_5 => - \gpt.timer0.r.scaler_m[5]\, scaler_m_7 => - \gpt.timer0.r.scaler_m[7]\, scaler_m_6 => - \gpt.timer0.r.scaler_m[6]\, scaler_m_0 => - \gpt.timer0.r.scaler_m[0]\, pwdata_0_d0 => - \apbi.pwdata[6]\, pwdata_14 => \apbi.pwdata[20]\, - pwdata_25 => \apbi.pwdata[31]\, pwdata_12 => - \apbi.pwdata[18]\, pwdata_24 => \apbi.pwdata[30]\, - pwdata_23 => \apbi.pwdata[29]\, pwdata_22 => - \apbi.pwdata[28]\, pwdata_21 => \apbi.pwdata[27]\, - pwdata_20 => \apbi.pwdata[26]\, pwdata_19 => - \apbi.pwdata[25]\, pwdata_18 => \apbi.pwdata[24]\, - pwdata_17 => \apbi.pwdata[23]\, pwdata_16 => - \apbi.pwdata[22]\, pwdata_15 => \apbi.pwdata[21]\, - pwdata_13 => \apbi.pwdata[19]\, pwdata_11 => - \apbi.pwdata[17]\, pwdata_10 => \apbi.pwdata[16]\, - reload_28 => \gpt.timer0.r.timers_2.reload[28]\, - reload_12 => \gpt.timer0.r.timers_2.reload[12]\, - reload_11 => \gpt.timer0.r.timers_2.reload[11]\, - reload_10 => \gpt.timer0.r.timers_2.reload[10]\, reload_8 - => \gpt.timer0.r.timers_2.reload[8]\, reload_7 => - \gpt.timer0.r.timers_2.reload[7]\, reload_6 => - \gpt.timer0.r.timers_2.reload[6]\, reload_5 => - \gpt.timer0.r.timers_2.reload[5]\, reload_0_7 => - \gpt.timer0.r.reload[7]\, reload_0_6 => - \gpt.timer0.r.reload[6]\, reload_0_4 => - \gpt.timer0.r.timers_2.reload[4]\, pwdata_0(15) => - \apbi.pwdata_0[15]\, pwdata_0(14) => \apbi.pwdata_0[14]\, - pwdata_0(13) => \apbi.pwdata_0[13]\, pwdata_0(12) => - \apbi.pwdata_0[12]\, pwdata_0(11) => \apbi.pwdata_0[11]\, - pwdata_0(10) => \apbi.pwdata_0[10]\, pwdata_0(9) => - \apbi.pwdata_0[9]\, pwdata_0(8) => \apbi.pwdata_0[8]\, - pwdata_0(7) => \apbi.pwdata_0[7]\, pwdata_0(6) => - \apbi.pwdata_0[6]\, pwdata_0(5) => \apbi.pwdata_0[5]\, - pwdata_0(4) => \apbi.pwdata_0[4]\, pwdata_0(3) => - \apbi.pwdata_0[3]\, pwdata_0(2) => \apbi.pwdata_0[2]\, - pwdata_0(1) => \apbi.pwdata_0[1]\, pwdata_0(0) => - \apbi.pwdata_0[0]\, prdata_17 => \apbo_3.prdata[31]\, - prdata_0 => \apbo_3.prdata[14]\, prdata_2 => - \apbo_3.prdata[16]\, prdata_4 => \apbo_3.prdata[18]\, - prdata_16 => \apbo_3.prdata[30]\, prdata_3 => - \apbo_3.prdata[17]\, prdata_5 => \apbo_3.prdata[19]\, - prdata_11 => \apbo_3.prdata[25]\, prdata_15 => - \apbo_3.prdata[29]\, prdata_9 => \apbo_3.prdata[23]\, - readdata_9_i_m(1) => - \gpt.timer0.comb.1.readdata_9_i_m[1]\, readdata_1_iv_0_0 - => \gpt.timer0.readdata_1_iv_0[13]\, readdata_1_iv_0_2 - => \gpt.timer0.readdata_1_iv_0[15]\, readdata_1_iv_0_11 - => \gpt.timer0.readdata_1_iv_0[24]\, readdata_1_iv_0_13 - => \gpt.timer0.readdata_1_iv_0[26]\, readdata_1_iv_0_9 - => \gpt.timer0.readdata_1_iv_0[22]\, readdata_iv_3(3) - => \gpt.timer0.readdata_iv_3[3]\, readdata_iv_3(2) => - \gpt.timer0.readdata_iv_3[2]\, reload_m_20 => - \gpt.timer0.r.timers_2.reload_m[20]\, reload_m_5 => - \gpt.timer0.r.reload_m[5]\, reload_m_9 => - \gpt.timer0.r.timers_2.reload_m[9]\, reload_m_21 => - \gpt.timer0.r.timers_2.reload_m[21]\, reload_m_0_d0 => - \gpt.timer0.r.reload_m[0]\, reload_m_27 => - \gpt.timer0.r.timers_2.reload_m[27]\, reload_m_4 => - \gpt.timer0.r.reload_m[4]\, value_m_1 => - \gpt.timer0.r.timers_2.value_m[5]\, value_m_9 => - \gpt.timer0.r.timers_2.value_m[13]\, value_m_5 => - \gpt.timer0.r.timers_2.value_m[9]\, value_m_23 => - \gpt.timer0.r.timers_2.value_m[27]\, value_m_17 => - \gpt.timer0.r.timers_2.value_m[21]\, value_m_11 => - \gpt.timer0.r.timers_2.value_m[15]\, value_m_3 => - \gpt.timer0.r.timers_2.value_m[7]\, value_m_20 => - \gpt.timer0.r.timers_2.value_m[24]\, value_m_6 => - \gpt.timer0.r.timers_2.value_m[10]\, value_m_4 => - \gpt.timer0.r.timers_2.value_m[8]\, value_m_7 => - \gpt.timer0.r.timers_2.value_m[11]\, value_m_0 => - \gpt.timer0.r.timers_2.value_m[4]\, value_m_24 => - \gpt.timer0.r.timers_2.value_m[28]\, value_m_22 => - \gpt.timer0.r.timers_2.value_m[26]\, value_m_18 => - \gpt.timer0.r.timers_2.value_m[22]\, value_m_8 => - \gpt.timer0.r.timers_2.value_m[12]\, value_m_16 => - \gpt.timer0.r.timers_2.value_m[20]\, paddr_0(3) => - \apbi.paddr_0[3]\, paddr_0(2) => \apbi.paddr_0[2]\, N_228 - => \gpt.timer0.N_228\, readdata51_1 => - \gpt.timer0.comb.2.readdata51_1\, N_6455 => N_6455, - chain_m => \gpt.timer0.r.timers_2.chain_m\, rdata60_1 => - \ua1.uart1.uartop.rdata60_1\, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, enable_m => - \gpt.timer0.r.timers_2.enable_m\, rdata59_4 => - \ua1.uart1.uartop.rdata59_4\, N_217 => \gpt.timer0.N_217\, - N_229 => \gpt.timer0.N_229\, N_215 => \gpt.timer0.N_215\, - rdata61_2 => \ua1.uart1.uartop.rdata61_2\, readdata55_3 - => \gpt.timer0.comb.readdata55_3\, N_218 => - \gpt.timer0.N_218\, N_216 => \gpt.timer0.N_216\, N_214 - => \gpt.timer0.N_214\, irqpen_m => - \gpt.timer0.r.timers_2.irqpen_m\, N_219 => - \gpt.timer0.N_219\, N_236 => \gpt.timer0.N_236\, N_220 - => \gpt.timer0.N_220\, rstn => rstn, restart_RNIIKBB => - \r.timers_2.restart_RNIIKBB\, N_240 => \gpt.timer0.N_240\, - readdata55 => \gpt.timer0.comb.readdata55\, dishlt => - \gpt.timer0.r.dishlt\, penable => \apbi.penable\, pwrite - => \apbi.pwrite\, N_773 => \apb0.N_773\, N_769 => - \apb0.N_769\, readdata57 => \gpt.timer0.comb.readdata57\, - un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\, N_78 => - \apb0.N_78\, un1_apbi_7_3 => - \lfrtimemanagement_0.un1_apbi_7_3\, un1_apbi_2 => - \gpt.timer0.comb.1.un1_apbi_2\, readdata56 => - \gpt.timer0.comb.readdata56\, N_232_0 => - \ua1.uart1.N_232_0\, N_240_0 => \gpt.timer0.N_240_0\, - readdata_1_sqmuxa_1_0 => - \gpt.timer0.readdata_1_sqmuxa_1_0\, N_232 => - \ua1.uart1.N_232\, value_0_sqmuxa_0 => - \gpt.timer0.v.timers_2.value_0_sqmuxa_0\, N_6455_0 => - N_6455_0, lclk_c => lclk_c); - - \sdo_adc_pad[5]\ : INBUF - port map(PAD => sdo_adc(5), Y => \sdo_adc_c[5]\); - - \spw_txs_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => spw_txs(0)); - - \spw_txs_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => spw_txs(2)); - - lclk : DFN1 - port map(D => lclk_i_i, CLK => clk_c, Q => lclk_i); - - \ramsn_pad[3]\ : OUTBUF - port map(D => \ramsn_c[3]\, PAD => ramsn(3)); - - \data_pad[29]\ : BIBUF - port map(PAD => data(29), D => \memo.data[29]\, E => - \memo.bdrive_i[0]\, Y => \data_in[29]\); - - MODE_pad : OUTBUF - port map(D => \GND\, PAD => MODE); - - \ramoen_pad[0]\ : OUTBUF - port map(D => \ramoen_c[0]\, PAD => ramoen(0)); - - pci_irdy_pad : OUTBUF - port map(D => \GND\, PAD => pci_irdy); - - SSRAM_0 : ssram_plugin - port map(state_RNIFS55(4) => \state_RNIFS55[4]\, ramsn_c(0) - => \ramsn_c[0]\, rwen_c(3) => \rwen_c[3]\, rwen_c(2) => - \rwen_c[2]\, rwen_c(1) => \rwen_c[1]\, rwen_c(0) => - \rwen_c[0]\, address_c(27) => \address_c[27]\, - address_c(26) => \address_c[26]\, address_c(25) => - \address_c[25]\, address_c(24) => \address_c[24]\, - address_c(23) => \address_c[23]\, address_c(22) => - \address_c[22]\, address_c(21) => \address_c[21]\, - address_c(20) => \address_c[20]\, address(31) => - \memo.address[31]\, address(30) => \memo.address[30]\, - address(29) => \memo.address[29]\, address(28) => - \memo.address[28]\, state_i(3) => \SSRAM_0.state_i[3]\, - ssram_plugin_GND => \GND\, clk_c => clk_c, writen_c => - writen_c, nBWE_c => nBWE_c, nBWd_c => nBWd_c, nBWc_c => - nBWc_c, nBWb_c => nBWb_c, nBWa_c => nBWa_c, nCE1_c => - nCE1_c, nCE3_c => nCE3_c, CE2_c => CE2_c); - - pci_devsel_pad : OUTBUF - port map(D => \GND\, PAD => pci_devsel); - - \data_pad[1]\ : BIBUF - port map(PAD => data(1), D => \memo.data[1]\, E => - \memo.bdrive_i[3]\, Y => \data_in[1]\); - - \address_pad[23]\ : OUTBUF - port map(D => \address_c[23]\, PAD => address(23)); - - ereset_pad : OUTBUF - port map(D => \GND\, PAD => ereset); - - \address_pad[8]\ : OUTBUF - port map(D => \address_c[8]\, PAD => address(8)); - - \address_pad[21]\ : OUTBUF - port map(D => \address_c[21]\, PAD => address(21)); - - lclk_RNO : INV - port map(A => lclk_i, Y => lclk_i_i); - - \pci_ad_pad[23]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(23)); - - \pci_cbe_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => pci_cbe(2)); - - \gpio_pad[6]\ : BIBUF - port map(PAD => gpio(6), D => \gpioo.dout[6]\, E => - \gpioo.oen_i[6]\, Y => \gpio_in[6]\); - - \pci_ad_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(2)); - - \spw_txd_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => spw_txd(1)); - - \data_pad[27]\ : BIBUF - port map(PAD => data(27), D => \memo.data[27]\, E => - \memo.bdrive_i[0]\, Y => \data_in[27]\); - - \ramsn_pad[4]\ : OUTBUF - port map(D => \VCC\, PAD => ramsn(4)); - - errorn_pad : TRIBUFF - port map(D => \GND\, E => \dbgo_0.error_i_2\, PAD => errorn); - - \data_pad[13]\ : BIBUF - port map(PAD => data(13), D => \memo.data[13]\, E => - \memo.bdrive_i[2]\, Y => \data_in[13]\); - - \ramoen_pad[2]\ : OUTBUF - port map(D => \ramoen_c[2]\, PAD => ramoen(2)); - - \sdo_adc_pad[2]\ : INBUF - port map(PAD => sdo_adc(2), Y => \sdo_adc_c[2]\); - - read_pad : OUTBUF - port map(D => read_c, PAD => read); - - nBWa_pad : OUTBUF - port map(D => nBWa_c, PAD => nBWa); - - \address_pad[19]\ : OUTBUF - port map(D => \address_c[19]\, PAD => address(19)); - - \rwen_pad[3]\ : OUTBUF - port map(D => \rwen_c[3]\, PAD => rwen(3)); - - nADV_pad : OUTBUF - port map(D => \VCC\, PAD => nADV); - - \l3.cpu.0.u0\ : leon3s - port map(irl_0(3) => \irqi_0.irl[3]\, irl_0(2) => - \irqi_0.irl[2]\, irl_0(1) => \irqi_0.irl[1]\, irl_0(0) - => \irqi_0.irl[0]\, irl(3) => \irqo_0.irl[3]\, irl(2) - => \irqo_0.irl[2]\, irl(1) => \irqo_0.irl[1]\, irl(0) - => \irqo_0.irl[0]\, hrdata_1_0_1(1) => - \ahb0.hrdata_1_0_1[1]\, data_0_21 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[29]\, data_0_16 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[24]\, data_0_5 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[13]\, data_0_2 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[10]\, data_0_0 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[8]\, nbo_5_0(1) => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[1]\, nbo_5_0(0) => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[0]\, htrans(1) => - \ahbmo_0.htrans[1]\, iosn_0(93) => \sr1.iosn_0[93]\, - htrans_tz(1) => \ahbmo_0.htrans_tz[1]\, haddr(31) => - \ahbmo_0.haddr[31]\, haddr(30) => \ahbmo_0.haddr[30]\, - haddr(29) => \ahbmo_0.haddr[29]\, haddr(28) => - \ahbmo_0.haddr[28]\, haddr(27) => \ahbmo_0.haddr[27]\, - haddr(26) => \ahbmo_0.haddr[26]\, haddr(25) => - \ahbmo_0.haddr[25]\, haddr(24) => \ahbmo_0.haddr[24]\, - haddr(23) => \ahbmo_0.haddr[23]\, haddr(22) => - \ahbmo_0.haddr[22]\, haddr(21) => \ahbmo_0.haddr[21]\, - haddr(20) => \ahbmo_0.haddr[20]\, haddr(19) => - \ahbmo_0.haddr[19]\, haddr(18) => \ahbmo_0.haddr[18]\, - haddr(17) => \ahbmo_0.haddr[17]\, haddr(16) => - \ahbmo_0.haddr[16]\, haddr(15) => \ahbmo_0.haddr[15]\, - haddr(14) => \ahbmo_0.haddr[14]\, haddr(13) => - \ahbmo_0.haddr[13]\, haddr(12) => \ahbmo_0.haddr[12]\, - haddr(11) => \ahbmo_0.haddr[11]\, haddr(10) => - \ahbmo_0.haddr[10]\, haddr(9) => \ahbmo_0.haddr[9]\, - haddr(8) => \ahbmo_0.haddr[8]\, haddr(7) => - \ahbmo_0.haddr[7]\, haddr(6) => \ahbmo_0.haddr[6]\, - haddr(5) => \ahbmo_0.haddr[5]\, haddr(4) => - \ahbmo_0.haddr[4]\, haddr(3) => \ahbmo_0.haddr[3]\, - haddr(2) => \ahbmo_0.haddr[2]\, hwdata_16 => - \ahbmo_0.hwdata[19]\, hwdata_3 => \ahbmo_0.hwdata[6]\, - hwdata_9 => \ahbmo_0.hwdata[12]\, hwdata_11 => - \ahbmo_0.hwdata[14]\, hwdata_25 => \ahbmo_0.hwdata[28]\, - hwdata_27 => \ahbmo_0.hwdata[30]\, hwdata_13 => - \ahbmo_0.hwdata[16]\, hwdata_4 => \ahbmo_0.hwdata[7]\, - hwdata_12 => \ahbmo_0.hwdata[15]\, hwdata_23 => - \ahbmo_0.hwdata[26]\, hwdata_28 => \ahbmo_0.hwdata[31]\, - hwdata_1 => \ahbmo_0.hwdata[4]\, hwdata_14 => - \ahbmo_0.hwdata[17]\, hwdata_0 => \ahbmo_0.hwdata[3]\, - hwdata_15 => \ahbmo_0.hwdata[18]\, iosn_1(93) => - \sr1.iosn_1[93]\, hsize_5(1) => - \l3.cpu.0.u0.p0.c0mmu.a0.hsize_5[1]\, hgrant(0) => - \ahbmi.hgrant[0]\, hresp(0) => \ahbmi.hresp[0]\, - iosn_2(93) => \sr1.iosn_2[93]\, address(1) => - \l3.cpu.0.u0.p0.c0mmu.mcdi.address[1]\, address(0) => - \l3.cpu.0.u0.p0.c0mmu.mcdi.address[0]\, size(0) => - \l3.cpu.0.u0.p0.c0mmu.mcdi.size[0]\, data_0_d0 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[5]\, data_5 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[10]\, data_3 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[8]\, data_8 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[13]\, data_19 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[24]\, data_24 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[29]\, hrdata_0_15 => - \ahbmi.hrdata_0[15]\, hrdata_0_0 => \ahbmi.hrdata_0[0]\, - hrdata_0_26 => \ahbmi.hrdata_0[26]\, hrdata_0_2 => - \ahbmi.hrdata_0[2]\, hrdata_0_1 => \ahbmi.hrdata_0[1]\, - hrdata_0_7 => \ahbmi.hrdata_0[7]\, hrdata_0_10 => - \ahbmi.hrdata_0[10]\, hrdata_0_11 => \ahbmi.hrdata_0[11]\, - hrdata_0_12 => \ahbmi.hrdata_0[12]\, hrdata_0_27 => - \ahbmi.hrdata_0[27]\, hrdata_0_21 => \ahbmi.hrdata_0[21]\, - hrdata_0_8 => \ahbmi.hrdata_0[8]\, hrdata_0_9 => - \ahbmi.hrdata_0[9]\, hrdata_0_13 => \ahbmi.hrdata_0[13]\, - hrdata_0_14 => \ahbmi.hrdata_0[14]\, hrdata_0_22 => - \ahbmi.hrdata_0[22]\, hrdata_0_23 => \ahbmi.hrdata_0[23]\, - hrdata_0_16 => \ahbmi.hrdata_0[16]\, hrdata_0_17 => - \ahbmi.hrdata_0[17]\, hrdata_0_18 => \ahbmi.hrdata_0[18]\, - hrdata_0_4 => \ahbmi.hrdata_0[4]\, hrdata_0_24 => - \ahbmi.hrdata_0[24]\, hrdata_0_3 => \ahbmi.hrdata_0[3]\, - hrdata_9 => \ahbmi.hrdata[9]\, hrdata_10 => - \ahbmi.hrdata[10]\, hrdata_11 => \ahbmi.hrdata[11]\, - hrdata_13 => \ahbmi.hrdata[13]\, hrdata_14 => - \ahbmi.hrdata[14]\, hrdata_17 => \ahbmi.hrdata[17]\, - hrdata_24 => \ahbmi.hrdata[24]\, hrdata_0_d0 => - \ahbmi.hrdata[0]\, hrdata_1 => \ahbmi.hrdata[1]\, - hrdata_8 => \ahbmi.hrdata[8]\, hrdata_12 => - \ahbmi.hrdata[12]\, hrdata_15 => \ahbmi.hrdata[15]\, - hrdata_16 => \ahbmi.hrdata[16]\, hrdata_18 => - \ahbmi.hrdata[18]\, hrdata_21 => \ahbmi.hrdata[21]\, - hrdata_22 => \ahbmi.hrdata[22]\, hrdata_23 => - \ahbmi.hrdata[23]\, hrdata_26 => \ahbmi.hrdata[26]\, - hrdata_27 => \ahbmi.hrdata[27]\, hrdata_2 => - \ahbmi.hrdata[2]\, hrdata_3 => \ahbmi.hrdata[3]\, - hrdata_4 => \ahbmi.hrdata[4]\, hrdata_7 => - \ahbmi.hrdata[7]\, hrdata_5 => \ahbmi.hrdata[5]\, - hrdata_6 => \ahbmi.hrdata[6]\, hrdata_28 => - \ahbmi.hrdata[28]\, hrdata_29 => \ahbmi.hrdata[29]\, - hrdata_30 => \ahbmi.hrdata[30]\, hrdata_31 => - \ahbmi.hrdata[31]\, error_i_2 => \dbgo_0.error_i_2\, - intack => \irqo_0.intack\, N_546 => N_546, leon3s_VCC => - \VCC\, N_264 => N_264, N_262 => N_262, N_78 => N_78, - bo_5842_d_0 => \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d_0\, - un1_htrans_1_sqmuxa_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.un1_htrans_1_sqmuxa_0\, hlock - => \ahbmo_0.hlock\, N_5054 => N_5054, lb_0_sqmuxa_1 => - \l3.cpu.0.u0.p0.c0mmu.a0.v.lb_0_sqmuxa_1\, hbusreq => - \ahbmo_0.hbusreq\, un60_nbo => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un60_nbo\, N_457 => N_457, - N_462 => N_462, N_467 => N_467, werr_2_m_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.v.werr_2_m_0\, un91_nbo_i_0 - => \l3.cpu.0.u0.p0.c0mmu.a0.comb.un91_nbo_i_0\, N_138 - => N_138, N_139 => N_139, bo_5842_d => - \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d\, N_458 => N_458, - N_459 => N_459, N_461 => N_461, N_463 => N_463, N_468 => - N_468, hwrite_1_m_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.hwrite_1_m_0\, N_466 => - N_466, htrans_0_sqmuxa_2 => - \l3.cpu.0.u0.p0.c0mmu.a0.htrans_0_sqmuxa_2\, un59_nbo => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un59_nbo\, N_78_0 => N_78_0, - N_262_0 => N_262_0, N_264_0 => N_264_0, rstn => rstn, - lclk_c => lclk_c); - - \data_pad[9]\ : BIBUF - port map(PAD => data(9), D => \memo.data[9]\, E => - \memo.bdrive_i[2]\, Y => \data_in[9]\); - - \address_pad[13]\ : OUTBUF - port map(D => \address_c[13]\, PAD => address(13)); - - \data_pad[30]\ : BIBUF - port map(PAD => data(30), D => \memo.data[30]\, E => - \memo.bdrive_i[0]\, Y => \data_in[30]\); - - \ramsn_pad[2]\ : OUTBUF - port map(D => \ramsn_c[2]\, PAD => ramsn(2)); - - \address_pad[11]\ : OUTBUF - port map(D => \address_c[11]\, PAD => address(11)); - - \pci_ad_pad[15]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(15)); - - nADSP_pad : OUTBUF - port map(D => \SSRAM_0.state_i[3]\, PAD => nADSP); - - \romsn_pad[0]\ : OUTBUF - port map(D => \romsn_c[0]\, PAD => romsn(0)); - - \address_pad[1]\ : OUTBUF - port map(D => \address_c[1]\, PAD => address(1)); - - \pci_cbe_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => pci_cbe(0)); - - \ramoen_pad[1]\ : OUTBUF - port map(D => \ramoen_c[1]\, PAD => ramoen(1)); - - ZZ_pad : OUTBUF - port map(D => \GND\, PAD => ZZ); - - pci_frame_pad : OUTBUF - port map(D => \GND\, PAD => pci_frame); - - \irqctrl.irqctrl0\ : irqmp - port map(irl_2(2) => \irqi_0.irl[2]\, pwdata_1_3 => - \apbi.pwdata_1[4]\, pwdata_1_2 => \apbi.pwdata_1[3]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, irl_3 => - \irqo_0.irl[3]\, irl_1 => \irqo_0.irl[1]\, irl_0_d0 => - \irqo_0.irl[0]\, irl_0(3) => \irqi_0.irl[3]\, irl_0(2) - => \irqo_0.irl[2]\, irl_0(1) => \irqi_0.irl[1]\, - irl_0(0) => \irqi_0.irl[0]\, ipend_10 => - \irqctrl.irqctrl0.r.ipend[11]\, pwdata_4 => - \apbi.pwdata[6]\, pwdata_0_d0 => \apbi.pwdata[2]\, - pwdata_17 => \apbi.pwdata[19]\, pwdata_21 => - \apbi.pwdata[23]\, pwdata_23 => \apbi.pwdata[25]\, - pwdata_26 => \apbi.pwdata[28]\, pwdata_16 => - \apbi.pwdata[18]\, pwdata_18 => \apbi.pwdata[20]\, - pwdata_15 => \apbi.pwdata[17]\, pwdata_25 => - \apbi.pwdata[27]\, pwdata_27 => \apbi.pwdata[29]\, - pwdata_28 => \apbi.pwdata[30]\, pwdata_29 => - \apbi.pwdata[31]\, pwdata_20 => \apbi.pwdata[22]\, - pwdata_19 => \apbi.pwdata[21]\, pwdata_24 => - \apbi.pwdata[26]\, pwdata_22 => \apbi.pwdata[24]\, - iforce_0_11 => \irqctrl.irqctrl0.r.iforce_0[12]\, - iforce_0_5 => \irqctrl.irqctrl0.r.iforce_0[6]\, - iforce_0_9 => \irqctrl.irqctrl0.r.iforce_0[10]\, - iforce_0_4 => \irqctrl.irqctrl0.r.iforce_0[5]\, - iforce_0_6 => \irqctrl.irqctrl0.r.iforce_0[7]\, - ipend_m(4) => \irqctrl.irqctrl0.r.ipend_m[4]\, prdata_0 - => \apbo_2.prdata[2]\, prdata_13 => \apbo_2.prdata[15]\, - prdata_1 => \apbo_2.prdata[3]\, iforce_0_m(4) => - \irqctrl.irqctrl0.r.iforce_0_m[4]\, ilevel_5 => - \irqctrl.irqctrl0.r.ilevel[6]\, ilevel_4 => - \irqctrl.irqctrl0.r.ilevel[5]\, ilevel_6 => - \irqctrl.irqctrl0.r.ilevel[7]\, ilevel_3 => - \irqctrl.irqctrl0.r.ilevel[4]\, ilevel_11 => - \irqctrl.irqctrl0.r.ilevel[12]\, ilevel_7 => - \irqctrl.irqctrl0.r.ilevel[8]\, ilevel_9 => - \irqctrl.irqctrl0.r.ilevel[10]\, prdata_11_m_1_0(4) => - \irqctrl.irqctrl0.prdata_11_m_1_0[4]\, prdata_13_m_1_0(4) - => \irqctrl.irqctrl0.prdata_13_m_1_0[4]\, paddr(7) => - \apbi.paddr[7]\, paddr(6) => \apbi.paddr[6]\, paddr(5) - => \apbi.paddr[5]\, paddr(4) => \apbi.paddr[4]\, - paddr(3) => \apbi.paddr[3]\, prdata_0_iv_0_0_0_12 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[13]\, - prdata_0_iv_0_0_0_0 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[1]\, - prdata_0_iv_0_0_0_13 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[14]\, - prdata_0_iv_0_0_1_12 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[13]\, - prdata_0_iv_0_0_1_0 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[1]\, - prdata_0_iv_0_0_1_13 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[14]\, pwdata_0(15) - => \apbi.pwdata_0[15]\, pwdata_0(14) => - \apbi.pwdata_0[14]\, pwdata_0(13) => \apbi.pwdata_0[13]\, - pwdata_0(12) => \apbi.pwdata_0[12]\, pwdata_0(11) => - \apbi.pwdata_0[11]\, pwdata_0(10) => \apbi.pwdata_0[10]\, - pwdata_0(9) => \apbi.pwdata_0[9]\, pwdata_0(8) => - \apbi.pwdata_0[8]\, pwdata_0(7) => \apbi.pwdata_0[7]\, - pwdata_0(6) => \apbi.pwdata_0[6]\, pwdata_0(5) => - \apbi.pwdata_0[5]\, pwdata_0(4) => \apbi.pwdata_0[4]\, - pwdata_0(3) => \apbi.pwdata_0[3]\, pwdata_0(2) => - \apbi.pwdata_0[2]\, pwdata_0(1) => \apbi.pwdata_0[1]\, - pirq_10 => \apbi.pirq[12]\, pirq_11 => \apbi.pirq[13]\, - pirq_13 => \apbi.pirq[15]\, pirq_7 => \apbi.pirq[9]\, - pirq_6 => \apbi.pirq[8]\, pirq_0 => \apbi.pirq[2]\, - paddr_0(4) => \apbi.paddr_0[4]\, paddr_0(3) => - \apbi.paddr_0[3]\, paddr_0(2) => \apbi.paddr_0[2]\, - lclk_c => lclk_c, N_365 => \irqctrl.irqctrl0.N_365\, - N_367 => \irqctrl.irqctrl0.N_367\, N_863 => - \irqctrl.irqctrl0.N_863\, intack => \irqo_0.intack\, - N_865 => \irqctrl.irqctrl0.N_865\, N_861 => - \irqctrl.irqctrl0.N_861\, N_859 => - \irqctrl.irqctrl0.N_859\, N_478 => - \irqctrl.irqctrl0.N_478\, N_476 => - \irqctrl.irqctrl0.N_476\, N_474 => - \irqctrl.irqctrl0.N_474\, N_473 => - \irqctrl.irqctrl0.N_473\, N_472 => - \irqctrl.irqctrl0.N_472\, N_471 => - \irqctrl.irqctrl0.N_471\, N_470 => - \irqctrl.irqctrl0.N_470\, N_468 => - \irqctrl.irqctrl0.N_468\, N_467 => - \irqctrl.irqctrl0.N_467\, N_842 => - \irqctrl.irqctrl0.N_842\, N_841 => - \irqctrl.irqctrl0.N_841\, N_839 => - \irqctrl.irqctrl0.N_839\, N_363 => - \irqctrl.irqctrl0.N_363\, N_361 => - \irqctrl.irqctrl0.N_361\, N_773 => \apb0.N_773\, N_769 - => \apb0.N_769\, rstn => rstn, un1_apbi_0 => - \gpt.timer0.comb.un1_apbi_0\, N_749 => \apb0.N_749\, - prdata_0_sqmuxa => \irqctrl.irqctrl0.prdata_0_sqmuxa\, - N_898 => \irqctrl.irqctrl0.N_898\, prdata_1_sqmuxa => - \irqctrl.irqctrl0.prdata_1_sqmuxa\); - - \gpio_pad[7]\ : BIBUF - port map(PAD => gpio(7), D => \gpioo.dout[7]\, E => - \gpioo.oen_i[7]\, Y => \gpio_in[7]\); - - \rwen_pad[1]\ : OUTBUF - port map(D => \rwen_c[1]\, PAD => rwen(1)); - - Bias_Fails_pad : OUTBUF - port map(D => Bias_Fails_c, PAD => Bias_Fails); - - \pci_ad_pad[22]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(22)); - - \address_pad[4]\ : OUTBUF - port map(D => \address_c[4]\, PAD => address(4)); - - GND_i : GND - port map(Y => \GND\); - - \pci_ad_pad[14]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(14)); - - \address_pad[3]\ : OUTBUF - port map(D => \address_c[3]\, PAD => address(3)); - - \pci_ad_pad[19]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(19)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \pci_ad_pad[5]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(5)); - - \address_pad[24]\ : OUTBUF - port map(D => \address_c[24]\, PAD => address(24)); - - \spw_txd_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => spw_txd(0)); - - \pci_ad_pad[30]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(30)); - - \ua1.uart1\ : apbuart - port map(pwdata_12 => \apbi.pwdata[12]\, pwdata_13 => - \apbi.pwdata[13]\, pwdata_14 => \apbi.pwdata[14]\, - pwdata_0_d0 => \apbi.pwdata[0]\, pwdata_2 => - \apbi.pwdata[2]\, pwdata_5 => \apbi.pwdata[5]\, pwdata_6 - => \apbi.pwdata[6]\, pwdata_7 => \apbi.pwdata[7]\, - pwdata_8 => \apbi.pwdata[8]\, pwdata_9 => - \apbi.pwdata[9]\, pwdata_10 => \apbi.pwdata[10]\, - pwdata_11 => \apbi.pwdata[11]\, pirq(2) => \apbi.pirq[2]\, - rcnt_RNI8FBM3(1) => \r.rcnt_RNI8FBM3[1]\, rdata_2_0 => - \ua1.uart1.uartop.rdata_2[0]\, pwdata_1_0 => - \apbi.pwdata_1[1]\, pwdata_1_3 => \apbi.pwdata_1[4]\, - pwdata_1_2 => \apbi.pwdata_1[3]\, paddr(4) => - \apbi.paddr[4]\, rdata_2_m_3 => - \ua1.uart1.uartop.rdata_2_m[5]\, rdata_2_m_4 => - \ua1.uart1.uartop.rdata_2_m[6]\, rdata_2_m_2 => - \ua1.uart1.uartop.rdata_2_m[4]\, brate_0 => - \ua1.uart1.r.brate[0]\, brate_10 => - \ua1.uart1.r.brate[10]\, brate_9 => - \ua1.uart1.r.brate[9]\, brate_8 => \ua1.uart1.r.brate[8]\, - brate_7 => \ua1.uart1.r.brate[7]\, brate_6 => - \ua1.uart1.r.brate[6]\, brate_m_3 => - \ua1.uart1.r.brate_m[5]\, brate_m_2 => - \ua1.uart1.r.brate_m[4]\, brate_m_9 => - \ua1.uart1.r.brate_m[11]\, pwdata_0(11) => - \apbi.pwdata_0[11]\, pwdata_0(10) => \apbi.pwdata_0[10]\, - pwdata_0(9) => \apbi.pwdata_0[9]\, pwdata_0(8) => - \apbi.pwdata_0[8]\, pwdata_0(7) => \apbi.pwdata_0[7]\, - pwdata_0(6) => \apbi.pwdata_0[6]\, pwdata_0(5) => - \apbi.pwdata_0[5]\, pwdata_0(4) => \apbi.pwdata_0[4]\, - pwdata_0(3) => \apbi.pwdata_0[3]\, pwdata_0(2) => - \apbi.pwdata_0[2]\, pwdata_0(1) => \apbi.pwdata_0[1]\, - pwdata_0(0) => \apbi.pwdata_0[0]\, rcnt_0 => - \ua1.uart1.r.rcnt[0]\, rcnt_1 => \ua1.uart1.r.rcnt[1]\, - rdata_17_m_0_d0 => \ua1.uart1.uartop.rdata_17_m[0]\, - rdata_17_m_5 => \ua1.uart1.uartop.rdata_17_m[5]\, - rdata_17_m_4 => \ua1.uart1.uartop.rdata_17_m[4]\, - un1_uart1_34 => \ua1.un1_uart1[36]\, rdata_17_m_0_4 => - \ua1.uart1.uartop.rdata_17_m_0[6]\, rdata_iv_0_a2_3_0(7) - => \ua1.uart1.rdata_iv_0_a2_3_0[7]\, tcnt_0 => - \ua1.uart1.r.tcnt[0]\, tcnt_1 => \ua1.uart1.r.tcnt[1]\, - rdata_iv_2(3) => \ua1.uart1.rdata_iv_2[3]\, rdata_iv_2(2) - => \ua1.uart1.rdata_iv_2[2]\, rdata_iv_0_2(1) => - \ua1.uart1.rdata_iv_0_2[1]\, prdata_6 => - \apbo_1.prdata[28]\, prdata_0 => \apbo_1.prdata[22]\, - prdata_9 => \apbo_1.prdata[31]\, paddr_0(4) => - \apbi.paddr_0[4]\, apbuart_VCC => \VCC\, apbuart_GND => - \GND\, rxd1_c => rxd1_c, lclk_c => lclk_c, txd1_c => - txd1_c, N_227 => \ua1.uart1.N_227\, thempty_1_m => - \ua1.uart1.uartop.thempty_1_m\, debug_m => - \ua1.uart1.r.debug_m\, N_232 => \ua1.uart1.N_232\, - rdata60 => \ua1.uart1.uartop.rdata60\, frame => - \ua1.uart1.r.frame\, rdata59 => - \ua1.uart1.uartop.rdata59\, parerr_m => - \ua1.uart1.r.parerr_m\, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, rdata62 => - \ua1.uart1.uartop.rdata62\, N_6455_0 => N_6455_0, - rdata59_4 => \ua1.uart1.uartop.rdata59_4\, parsel_m_0 => - \ua1.uart1.r.parsel_m_0\, ovf_m => \ua1.uart1.r.ovf_m\, - break_m => \ua1.uart1.r.break_m\, N_223 => - \ua1.uart1.N_223\, N_220 => \ua1.uart1.N_220\, - rfifoirqen_m => \ua1.uart1.r.rfifoirqen_m\, tfifoirqen_m - => \ua1.uart1.r.tfifoirqen_m\, N_156 => - \ua1.uart1.N_156\, rhalffull_1_m => - \ua1.uart1.uartop.rhalffull_1_m\, rdata_3_sqmuxa => - \ua1.uart1.rdata_3_sqmuxa\, ctrl2 => - \lfrtimemanagement_0.r.ctrl2\, rstn => rstn, - tsemptyirqen_0 => \ua1.uart1.r.tsemptyirqen\, N_773 => - \apb0.N_773\, N_769 => \apb0.N_769\, paren => - \ua1.uart1.r.paren\, N_750 => \apb0.N_750\, penable => - \apbi.penable\, breakirqen => \ua1.uart1.r.breakirqen\, - delayirqen => \ua1.uart1.r.delayirqen\, rdata_4_sqmuxa - => \ua1.uart1.rdata_4_sqmuxa\, rdata_0_sqmuxa => - \ua1.uart1.rdata_0_sqmuxa\, tcnt_i => - \ua1.uart1.uartop.un1_r.tcnt_i\, flow_m => - \ua1.uart1.r.flow_m\, extclken_m => - \ua1.uart1.r.extclken_m\, rdata61 => - \ua1.uart1.uartop.rdata61\, pwrite => \apbi.pwrite\, - un1_apbi_8 => \lfrtimemanagement_0.un1_apbi_8\, rdata62_0 - => \ua1.uart1.uartop.rdata62_0\, rdata60_1 => - \ua1.uart1.uartop.rdata60_1\, rdata61_2 => - \ua1.uart1.uartop.rdata61_2\, rdata60_4_0 => - \ua1.uart1.uartop.rdata60_4_0\); - - \pci_ad_pad[11]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(11)); - - \address_pad[22]\ : OUTBUF - port map(D => \address_c[22]\, PAD => address(22)); - - sck_ch1_pad : OUTBUF - port map(D => sck_ch1_c, PAD => sck_ch1); - - \pci_ad_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(1)); - - dsurx_pad : INBUF - port map(PAD => dsurx, Y => dsurx_c); - - \ramsn_pad[0]\ : OUTBUF - port map(D => \ramsn_c[0]\, PAD => ramsn(0)); - - \pci_ad_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(0)); - - apb0 : apbctrl - port map(hrdata(31) => \ahbso_1.hrdata[31]\, hrdata(30) => - \ahbso_1.hrdata[30]\, hrdata(29) => \ahbso_1.hrdata[29]\, - hrdata(28) => \ahbso_1.hrdata[28]\, hrdata(27) => - \ahbso_1.hrdata[27]\, hrdata(26) => \ahbso_1.hrdata[26]\, - hrdata(25) => \ahbso_1.hrdata[25]\, hrdata(24) => - \ahbso_1.hrdata[24]\, hrdata(23) => \ahbso_1.hrdata[23]\, - hrdata(22) => \ahbso_1.hrdata[22]\, hrdata(21) => - \ahbso_1.hrdata[21]\, hrdata(20) => \ahbso_1.hrdata[20]\, - hrdata(19) => \ahbso_1.hrdata[19]\, hrdata(18) => - \ahbso_1.hrdata[18]\, hrdata(17) => \ahbso_1.hrdata[17]\, - hrdata(16) => \ahbso_1.hrdata[16]\, hrdata(15) => - \ahbso_1.hrdata[15]\, hrdata(14) => \ahbso_1.hrdata[14]\, - hrdata(13) => \ahbso_1.hrdata[13]\, hrdata(12) => - \ahbso_1.hrdata[12]\, hrdata(11) => \ahbso_1.hrdata[11]\, - hrdata(10) => \ahbso_1.hrdata[10]\, hrdata(9) => - \ahbso_1.hrdata[9]\, hrdata(8) => \ahbso_1.hrdata[8]\, - hrdata(7) => \ahbso_1.hrdata[7]\, hrdata(6) => - \ahbso_1.hrdata[6]\, hrdata(5) => \ahbso_1.hrdata[5]\, - hrdata(4) => \ahbso_1.hrdata[4]\, hrdata(3) => - \ahbso_1.hrdata[3]\, hrdata(2) => \ahbso_1.hrdata[2]\, - hrdata(1) => \ahbso_1.hrdata[1]\, hrdata(0) => - \ahbso_1.hrdata[0]\, pwdata(31) => \apbi.pwdata[31]\, - pwdata(30) => \apbi.pwdata[30]\, pwdata(29) => - \apbi.pwdata[29]\, pwdata(28) => \apbi.pwdata[28]\, - pwdata(27) => \apbi.pwdata[27]\, pwdata(26) => - \apbi.pwdata[26]\, pwdata(25) => \apbi.pwdata[25]\, - pwdata(24) => \apbi.pwdata[24]\, pwdata(23) => - \apbi.pwdata[23]\, pwdata(22) => \apbi.pwdata[22]\, - pwdata(21) => \apbi.pwdata[21]\, pwdata(20) => - \apbi.pwdata[20]\, pwdata(19) => \apbi.pwdata[19]\, - pwdata(18) => \apbi.pwdata[18]\, pwdata(17) => - \apbi.pwdata[17]\, pwdata(16) => \apbi.pwdata[16]\, - pwdata(15) => \apbi.pwdata[15]\, pwdata(14) => - \apbi.pwdata[14]\, pwdata(13) => \apbi.pwdata[13]\, - pwdata(12) => \apbi.pwdata[12]\, pwdata(11) => - \apbi.pwdata[11]\, pwdata(10) => \apbi.pwdata[10]\, - pwdata(9) => \apbi.pwdata[9]\, pwdata(8) => - \apbi.pwdata[8]\, pwdata(7) => \apbi.pwdata[7]\, - pwdata(6) => \apbi.pwdata[6]\, pwdata(5) => - \apbi.pwdata[5]\, pwdata(4) => \apbi.pwdata[4]\, - pwdata(3) => \apbi.pwdata[3]\, pwdata(2) => - \apbi.pwdata[2]\, pwdata(1) => \apbi.pwdata[1]\, - pwdata(0) => \apbi.pwdata[0]\, psel_1(7) => - \apbi.psel_1[7]\, prdata_4(31) => \apbo_15.prdata[31]\, - rdata_iv_0_2(1) => \ua1.uart1.rdata_iv_0_2[1]\, - prdata_iv_0_0(2) => \gpio0.grgpio0.apbo.prdata_iv_0_0[2]\, - ramrws(1) => \sr1.r.mcfg2.ramrws[1]\, ramwws(1) => - \sr1.r.mcfg2.ramwws[1]\, ramwws(0) => - \sr1.r.mcfg2.ramwws[0]\, romrws(3) => - \sr1.r.mcfg1.romrws[3]\, romrws(2) => - \sr1.r.mcfg1.romrws[2]\, romrws(1) => - \sr1.r.mcfg1.romrws[1]\, prdata_iv_0_2 => - \gpio0.grgpio0.apbo.prdata_iv_0[3]\, prdata_iv_0_0_d0 => - \gpio0.grgpio0.apbo.prdata_iv_0[1]\, un1_grgpio0_0 => - \gpio0.un1_grgpio0[69]\, un1_grgpio0_2 => - \gpio0.un1_grgpio0[71]\, ramwidth(1) => - \sr1.r.mcfg2.ramwidth[1]\, ramwidth(0) => - \sr1.r.mcfg2.ramwidth[0]\, rdata_iv_2(3) => - \ua1.uart1.rdata_iv_2[3]\, rdata_iv_2(2) => - \ua1.uart1.rdata_iv_2[2]\, readdata_iv_3(3) => - \gpt.timer0.readdata_iv_3[3]\, readdata_iv_3(2) => - \gpt.timer0.readdata_iv_3[2]\, tcnt(1) => - \ua1.uart1.r.tcnt[1]\, tcnt(0) => \ua1.uart1.r.tcnt[0]\, - prdata_3_29 => \apbo_14.prdata[31]\, prdata_3_12 => - \apbo_15.prdata[14]\, prdata_3_0 => \apbo_15.prdata[2]\, - prdata_3_1 => \apbo_13.prdata[3]\, prdata_3_14 => - \apbo_13.prdata[16]\, prdata_3_13 => \apbo_13.prdata[15]\, - prdata_3_26 => \apbo_14.prdata[28]\, prdata_3_23 => - \apbo_13.prdata[25]\, prdata_3_16 => \apbo_13.prdata[18]\, - prdata_3_28 => \apbo_13.prdata[30]\, prdata_3_27 => - \apbo_13.prdata[29]\, prdata_3_17 => \apbo_13.prdata[19]\, - prdata_3_15 => \apbo_14.prdata[17]\, romwws(3) => - \sr1.r.mcfg1.romwws[3]\, romwws(2) => - \sr1.r.mcfg1.romwws[2]\, romwws(1) => - \sr1.r.mcfg1.romwws[1]\, romwws(0) => - \sr1.r.mcfg1.romwws[0]\, romwidth(1) => - \sr1.r.mcfg1.romwidth[1]\, romwidth(0) => - \sr1.r.mcfg1.romwidth[0]\, rambanksz_0 => - \sr1.r.mcfg2.rambanksz[0]\, rambanksz_1 => - \sr1.r.mcfg2.rambanksz[1]\, rambanksz_3 => - \sr1.r.mcfg2.rambanksz[3]\, prdata_0_iv_0_0_0_13 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[14]\, - prdata_0_iv_0_0_0_0 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[1]\, - prdata_0_iv_0_0_0_12 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[13]\, - prdata_0_iv_0_0_1_13 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[14]\, - prdata_0_iv_0_0_1_0 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[1]\, - prdata_0_iv_0_0_1_12 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[13]\, - readdata_1_iv_0_13 => \gpt.timer0.readdata_1_iv_0[26]\, - readdata_1_iv_0_2 => \gpt.timer0.readdata_1_iv_0[15]\, - readdata_1_iv_0_0 => \gpt.timer0.readdata_1_iv_0[13]\, - readdata_1_iv_0_9 => \gpt.timer0.readdata_1_iv_0[22]\, - readdata_1_iv_0_11 => \gpt.timer0.readdata_1_iv_0[24]\, - prdata_2_20 => \apbo_15.prdata[20]\, prdata_2_31 => - \apbo_13.prdata[31]\, prdata_2_14 => \apbo_13.prdata[14]\, - prdata_2_1 => \apbo_13.prdata[1]\, prdata_2_2 => - \apbo_13.prdata[2]\, prdata_2_5 => \apbo_7.prdata[5]\, - prdata_2_0 => \apbo_15.prdata[0]\, prdata_2_3 => - \apbo_15.prdata[3]\, prdata_2_16 => \apbo_15.prdata[16]\, - prdata_2_21 => \apbo_14.prdata[21]\, prdata_2_23 => - \apbo_13.prdata[23]\, prdata_2_15 => \apbo_15.prdata[15]\, - prdata_2_27 => \apbo_14.prdata[27]\, prdata_2_28 => - \apbo_15.prdata[28]\, prdata_2_25 => \apbo_15.prdata[25]\, - prdata_2_18 => \apbo_14.prdata[18]\, prdata_2_30 => - \apbo_14.prdata[30]\, prdata_2_29 => \apbo_14.prdata[29]\, - prdata_2_19 => \apbo_14.prdata[19]\, prdata_2_17 => - \apbo_15.prdata[17]\, prdata_2_9 => \apbo_13.prdata[9]\, - prdata_2_13 => \apbo_13.prdata[13]\, prdata_2_22 => - \apbo_13.prdata[22]\, prdata_2_24 => \apbo_13.prdata[24]\, - prdata_2_26 => \apbo_13.prdata[26]\, prdata_11_m_1_0(4) - => \irqctrl.irqctrl0.prdata_11_m_1_0[4]\, - prdata_13_m_1_0(4) => - \irqctrl.irqctrl0.prdata_13_m_1_0[4]\, psel_0 => - \apbi.psel[0]\, psel_15 => \apbi.psel[15]\, psel_11 => - \apbi.psel[11]\, reload_RNI6SNI(1) => - \r.reload_RNI6SNI[1]\, readdata_9_i_m(1) => - \gpt.timer0.comb.1.readdata_9_i_m[1]\, un1_uart1(36) => - \ua1.un1_uart1[36]\, reload_m_0(0) => - \gpt.timer0.r.reload_m[0]\, reload_0(7) => - \gpt.timer0.r.reload[7]\, reload_0(6) => - \gpt.timer0.r.reload[6]\, un1_dcom0(19) => - \dcomgen.un1_dcom0[19]\, un1_dcom0(18) => - \dcomgen.un1_dcom0[18]\, un1_dcom0(17) => - \dcomgen.un1_dcom0[17]\, un1_dcom0(16) => - \dcomgen.un1_dcom0[16]\, un1_dcom0(15) => - \dcomgen.un1_dcom0[15]\, un1_dcom0(14) => - \dcomgen.un1_dcom0[14]\, un1_dcom0(13) => - \dcomgen.un1_dcom0[13]\, un1_dcom0(12) => - \dcomgen.un1_dcom0[12]\, iows(3) => \sr1.r.mcfg1.iows[3]\, - iows(2) => \sr1.r.mcfg1.iows[2]\, ipend(11) => - \irqctrl.irqctrl0.r.ipend[11]\, iforce_0_m(4) => - \irqctrl.irqctrl0.r.iforce_0_m[4]\, ipend_m(4) => - \irqctrl.irqctrl0.r.ipend_m[4]\, iforce_0_5 => - \irqctrl.irqctrl0.r.iforce_0[10]\, iforce_0_2 => - \irqctrl.irqctrl0.r.iforce_0[7]\, iforce_0_1 => - \irqctrl.irqctrl0.r.iforce_0[6]\, iforce_0_7 => - \irqctrl.irqctrl0.r.iforce_0[12]\, iforce_0_0 => - \irqctrl.irqctrl0.r.iforce_0[5]\, ilevel_6 => - \irqctrl.irqctrl0.r.ilevel[10]\, ilevel_4 => - \irqctrl.irqctrl0.r.ilevel[8]\, ilevel_3 => - \irqctrl.irqctrl0.r.ilevel[7]\, ilevel_2 => - \irqctrl.irqctrl0.r.ilevel[6]\, ilevel_0 => - \irqctrl.irqctrl0.r.ilevel[4]\, ilevel_8 => - \irqctrl.irqctrl0.r.ilevel[12]\, ilevel_1 => - \irqctrl.irqctrl0.r.ilevel[5]\, oen(7) => \gpioo.oen[7]\, - readdata_2_m(5) => \gpio0.grgpio0.comb.readdata_2_m[5]\, - dout_2 => \gpioo.dout[3]\, dout_0 => \gpioo.dout[1]\, - dout_6 => \gpioo.dout[7]\, dout_5 => \gpioo.dout[6]\, - dout_4 => \gpioo.dout[5]\, value_RNIBAHH(1) => - \r.timers_2.value_RNIBAHH[1]\, reload_RNIRDRG(1) => - \r.timers_2.reload_RNIRDRG[1]\, scaler_i_m(1) => - \gpt.timer0.r.scaler_i_m[1]\, scaler(4) => - \gpt.timer0.r.scaler[4]\, value_6 => - \gpt.timer0.r.timers_2.value[6]\, value_0 => - \gpt.timer0.r.timers_2.value[0]\, reload_8 => - \gpt.timer0.r.timers_2.reload[12]\, reload_7 => - \gpt.timer0.r.timers_2.reload[11]\, reload_6 => - \gpt.timer0.r.timers_2.reload[10]\, reload_24 => - \gpt.timer0.r.timers_2.reload[28]\, reload_4 => - \gpt.timer0.r.timers_2.reload[8]\, reload_3 => - \gpt.timer0.r.timers_2.reload[7]\, reload_2 => - \gpt.timer0.r.timers_2.reload[6]\, reload_0_d0 => - \gpt.timer0.r.timers_2.reload[4]\, reload_1 => - \gpt.timer0.r.timers_2.reload[5]\, scaler_m_7 => - \gpt.timer0.r.scaler_m[7]\, scaler_m_6 => - \gpt.timer0.r.scaler_m[6]\, scaler_m_0 => - \gpt.timer0.r.scaler_m[0]\, scaler_m_5 => - \gpt.timer0.r.scaler_m[5]\, rcnt(1) => - \ua1.uart1.r.rcnt[1]\, rcnt(0) => \ua1.uart1.r.rcnt[0]\, - rdata_2(0) => \ua1.uart1.uartop.rdata_2[0]\, - rcnt_RNI8FBM3(1) => \r.rcnt_RNI8FBM3[1]\, - rdata_iv_0_a2_3_0(7) => \ua1.uart1.rdata_iv_0_a2_3_0[7]\, - brate_9 => \ua1.uart1.r.brate[9]\, brate_8 => - \ua1.uart1.r.brate[8]\, brate_0 => \ua1.uart1.r.brate[0]\, - brate_10 => \ua1.uart1.r.brate[10]\, brate_7 => - \ua1.uart1.r.brate[7]\, brate_6 => \ua1.uart1.r.brate[6]\, - rdata_17_m_0(6) => \ua1.uart1.uartop.rdata_17_m_0[6]\, - brate_m_7 => \ua1.uart1.r.brate_m[11]\, brate_m_0 => - \ua1.uart1.r.brate_m[4]\, brate_m_1 => - \ua1.uart1.r.brate_m[5]\, rdata_17_m_0_d0 => - \ua1.uart1.uartop.rdata_17_m[0]\, rdata_17_m_4 => - \ua1.uart1.uartop.rdata_17_m[4]\, rdata_17_m_5 => - \ua1.uart1.uartop.rdata_17_m[5]\, rdata_2_m(6) => - \ua1.uart1.uartop.rdata_2_m[6]\, rdata_2_m(5) => - \ua1.uart1.uartop.rdata_2_m[5]\, rdata_2_m(4) => - \ua1.uart1.uartop.rdata_2_m[4]\, prdata_1_20 => - \apbo_14.prdata[20]\, prdata_1_5 => \apbo_13.prdata[5]\, - prdata_1_12 => \apbo_13.prdata[12]\, prdata_1_21 => - \apbo_15.prdata[21]\, prdata_1_23 => \apbo_14.prdata[23]\, - prdata_1_27 => \apbo_15.prdata[27]\, prdata_1_0 => - \apbo_13.prdata[0]\, prdata_1_4 => \apbo_13.prdata[4]\, - prdata_1_6 => \apbo_13.prdata[6]\, prdata_1_7 => - \apbo_13.prdata[7]\, prdata_1_8 => \apbo_13.prdata[8]\, - prdata_1_9 => \apbo_15.prdata[9]\, prdata_1_10 => - \apbo_13.prdata[10]\, prdata_1_11 => \apbo_13.prdata[11]\, - prdata_1_22 => \apbo_15.prdata[22]\, prdata_1_28 => - \apbo_13.prdata[28]\, paddr_5 => \apbi.paddr[7]\, - paddr_2_d0 => \apbi.paddr[4]\, paddr_0_d0 => - \apbi.paddr[2]\, paddr_1_d0 => \apbi.paddr[3]\, paddr_3 - => \apbi.paddr[5]\, paddr_4 => \apbi.paddr[6]\, - htrans(1) => \ahbsi.htrans[1]\, iosn_0(93) => - \sr1.iosn_0[93]\, readdata_9_4 => - \gpt.timer0.comb.1.readdata_9[4]\, readdata_9_0 => - \gpt.timer0.comb.1.readdata_9[0]\, readdata_9_5 => - \gpt.timer0.comb.1.readdata_9[5]\, readdata_9_27 => - \gpt.timer0.comb.1.readdata_9[27]\, reload_m_2 => - \gpt.timer0.r.reload_m[2]\, reload_m_3 => - \gpt.timer0.r.reload_m[3]\, reload_m_21 => - \gpt.timer0.r.timers_2.reload_m[21]\, reload_m_9 => - \gpt.timer0.r.timers_2.reload_m[9]\, reload_m_0_d0 => - \gpt.timer0.r.timers_2.reload_m[0]\, reload_m_5 => - \gpt.timer0.r.reload_m[5]\, reload_m_27 => - \gpt.timer0.r.timers_2.reload_m[27]\, reload_m_20 => - \gpt.timer0.r.timers_2.reload_m[20]\, reload_m_4 => - \gpt.timer0.r.reload_m[4]\, value_m_22 => - \gpt.timer0.r.timers_2.value_m[26]\, value_m_11 => - \gpt.timer0.r.timers_2.value_m[15]\, value_m_9 => - \gpt.timer0.r.timers_2.value_m[13]\, value_m_18 => - \gpt.timer0.r.timers_2.value_m[22]\, value_m_20 => - \gpt.timer0.r.timers_2.value_m[24]\, value_m_17 => - \gpt.timer0.r.timers_2.value_m[21]\, value_m_4 => - \gpt.timer0.r.timers_2.value_m[8]\, value_m_5 => - \gpt.timer0.r.timers_2.value_m[9]\, value_m_3 => - \gpt.timer0.r.timers_2.value_m[7]\, value_m_0 => - \gpt.timer0.r.timers_2.value_m[4]\, value_m_1 => - \gpt.timer0.r.timers_2.value_m[5]\, value_m_8 => - \gpt.timer0.r.timers_2.value_m[12]\, value_m_7 => - \gpt.timer0.r.timers_2.value_m[11]\, value_m_6 => - \gpt.timer0.r.timers_2.value_m[10]\, value_m_23 => - \gpt.timer0.r.timers_2.value_m[27]\, value_m_24 => - \gpt.timer0.r.timers_2.value_m[28]\, value_m_16 => - \gpt.timer0.r.timers_2.value_m[20]\, prdata_0_1 => - \apbo_15.prdata[1]\, prdata_0_23 => \apbo_15.prdata[23]\, - prdata_0_18 => \apbo_15.prdata[18]\, prdata_0_30 => - \apbo_15.prdata[30]\, prdata_0_29 => \apbo_15.prdata[29]\, - prdata_0_0 => \apbo_7.prdata[0]\, prdata_0_8 => - \apbo_14.prdata[8]\, prdata_0_10 => \apbo_15.prdata[10]\, - prdata_0_11 => \apbo_15.prdata[11]\, prdata_0_12 => - \apbo_15.prdata[12]\, prdata_0_13 => \apbo_15.prdata[13]\, - prdata_0_24 => \apbo_15.prdata[24]\, prdata_0_26 => - \apbo_15.prdata[26]\, prdata_0_17 => \apbo_3.prdata[17]\, - prdata_0_19 => \apbo_3.prdata[19]\, prdata_0_25 => - \apbo_3.prdata[25]\, prdata_0_16 => \apbo_3.prdata[16]\, - prdata_0_22 => \apbo_1.prdata[22]\, prdata_0_15 => - \apbo_14.prdata[15]\, prdata_0_31 => \apbo_3.prdata[31]\, - prdata_0_14 => \apbo_14.prdata[14]\, prdata_0_21 => - \apbo_13.prdata[21]\, prdata_0_27 => \apbo_13.prdata[27]\, - prdata_0_20 => \apbo_13.prdata[20]\, prdata_0_4 => - \apbo_15.prdata[4]\, prdata_0_6 => \apbo_15.prdata[6]\, - prdata_0_7 => \apbo_15.prdata[7]\, prdata_0_5 => - \apbo_15.prdata[5]\, prdata_0_3 => \apbo_14.prdata[3]\, - prdata_0_2 => \apbo_14.prdata[2]\, prdata_0_28 => - \apbo_1.prdata[28]\, prdata(31) => \apbo_1.prdata[31]\, - prdata(30) => \apbo_3.prdata[30]\, prdata(29) => - \apbo_3.prdata[29]\, prdata(28) => \apbo_0.prdata[28]\, - prdata(27) => \apbo_0.prdata[27]\, prdata(26) => - \apbo_14.prdata[26]\, prdata(25) => \apbo_14.prdata[25]\, - prdata(24) => \apbo_14.prdata[24]\, prdata(23) => - \apbo_3.prdata[23]\, prdata(22) => \apbo_14.prdata[22]\, - prdata(21) => \apbo_0.prdata[21]\, prdata(20) => - \apbo_0.prdata[20]\, prdata(19) => \apbo_15.prdata[19]\, - prdata(18) => \apbo_3.prdata[18]\, prdata(17) => - \apbo_13.prdata[17]\, prdata(16) => \apbo_14.prdata[16]\, - prdata(15) => \apbo_2.prdata[15]\, prdata(14) => - \apbo_3.prdata[14]\, prdata(13) => \apbo_14.prdata[13]\, - prdata(12) => \apbo_14.prdata[12]\, prdata(11) => - \apbo_14.prdata[11]\, prdata(10) => \apbo_14.prdata[10]\, - prdata(9) => \apbo_14.prdata[9]\, prdata(8) => - \apbo_15.prdata[8]\, prdata(7) => \apbo_14.prdata[7]\, - prdata(6) => \apbo_14.prdata[6]\, prdata(5) => - \apbo_14.prdata[5]\, prdata(4) => \apbo_14.prdata[4]\, - prdata(3) => \apbo_2.prdata[3]\, prdata(2) => - \apbo_2.prdata[2]\, prdata(1) => \apbo_14.prdata[1]\, - prdata(0) => \apbo_14.prdata[0]\, pwdata_i(7) => - \apbi.pwdata_i[7]\, pwdata_i(6) => \apbi.pwdata_i[6]\, - pwdata_i(5) => \apbi.pwdata_i[5]\, pwdata_i(4) => - \apbi.pwdata_i[4]\, pwdata_i(3) => \apbi.pwdata_i[3]\, - pwdata_i(2) => \apbi.pwdata_i[2]\, pwdata_i(1) => - \apbi.pwdata_i[1]\, pwdata_i(0) => \apbi.pwdata_i[0]\, - pwdata_1_3 => \apbi.pwdata_1[4]\, pwdata_1_2 => - \apbi.pwdata_1[3]\, pwdata_1_0 => \apbi.pwdata_1[1]\, - hwdata(31) => \ahbsi.hwdata[31]\, hwdata(30) => - \ahbsi.hwdata[30]\, hwdata(29) => \ahbsi.hwdata[29]\, - hwdata(28) => \ahbsi.hwdata[28]\, hwdata(27) => - \ahbsi.hwdata[27]\, hwdata(26) => \ahbsi.hwdata[26]\, - hwdata(25) => \ahbsi.hwdata[25]\, hwdata(24) => - \ahbsi.hwdata[24]\, hwdata(23) => \ahbsi.hwdata[23]\, - hwdata(22) => \ahbsi.hwdata[22]\, hwdata(21) => - \ahbsi.hwdata[21]\, hwdata(20) => \ahbsi.hwdata[20]\, - hwdata(19) => \ahbsi.hwdata[19]\, hwdata(18) => - \ahbsi.hwdata[18]\, hwdata(17) => \ahbsi.hwdata[17]\, - hwdata(16) => \ahbsi.hwdata[16]\, hwdata(15) => - \ahbsi.hwdata[15]\, hwdata(14) => \ahbsi.hwdata[14]\, - hwdata(13) => \ahbsi.hwdata[13]\, hwdata(12) => - \ahbsi.hwdata[12]\, hwdata(11) => \ahbsi.hwdata[11]\, - hwdata(10) => \ahbsi.hwdata[10]\, hwdata(9) => - \ahbsi.hwdata[9]\, hwdata(8) => \ahbsi.hwdata[8]\, - hwdata(7) => \ahbsi.hwdata[7]\, hwdata(6) => - \ahbsi.hwdata[6]\, hwdata(5) => \ahbsi.hwdata[5]\, - hwdata(4) => \ahbsi.hwdata[4]\, hwdata(3) => - \ahbsi.hwdata[3]\, hwdata(2) => \ahbsi.hwdata[2]\, - hwdata(1) => \ahbsi.hwdata[1]\, hwdata(0) => - \ahbsi.hwdata[0]\, pwdata_0(15) => \apbi.pwdata_0[15]\, - pwdata_0(14) => \apbi.pwdata_0[14]\, pwdata_0(13) => - \apbi.pwdata_0[13]\, pwdata_0(12) => \apbi.pwdata_0[12]\, - pwdata_0(11) => \apbi.pwdata_0[11]\, pwdata_0(10) => - \apbi.pwdata_0[10]\, pwdata_0(9) => \apbi.pwdata_0[9]\, - pwdata_0(8) => \apbi.pwdata_0[8]\, pwdata_0(7) => - \apbi.pwdata_0[7]\, pwdata_0(6) => \apbi.pwdata_0[6]\, - pwdata_0(5) => \apbi.pwdata_0[5]\, pwdata_0(4) => - \apbi.pwdata_0[4]\, pwdata_0(3) => \apbi.pwdata_0[3]\, - pwdata_0(2) => \apbi.pwdata_0[2]\, pwdata_0(1) => - \apbi.pwdata_0[1]\, pwdata_0(0) => \apbi.pwdata_0[0]\, - paddr_0(4) => \apbi.paddr_0[4]\, paddr_0(3) => - \apbi.paddr_0[3]\, paddr_0(2) => \apbi.paddr_0[2]\, - paddr_1(2) => \apbi.paddr_1[2]\, haddr(19) => - \ahbsi.haddr[19]\, haddr(18) => \ahbsi.haddr[18]\, - haddr(17) => \ahbsi.haddr[17]\, haddr(16) => - \ahbsi.haddr[16]\, haddr(15) => \ahbsi.haddr[15]\, - haddr(14) => \ahbsi.haddr[14]\, haddr(13) => - \ahbsi.haddr[13]\, haddr(12) => \ahbsi.haddr[12]\, - haddr(11) => \ahbsi.haddr[11]\, haddr(10) => - \ahbsi.haddr[10]\, haddr(9) => \ahbsi.haddr[9]\, haddr(8) - => \ahbsi.haddr[8]\, haddr(7) => \ahbsi.haddr[7]\, - haddr(6) => \ahbsi.haddr[6]\, haddr(5) => - \ahbsi.haddr[5]\, haddr(4) => \ahbsi.haddr[4]\, haddr(3) - => \ahbsi.haddr[3]\, haddr(2) => \ahbsi.haddr[2]\, - paddr_2(2) => \apbi.paddr_2[2]\, hready => - \ahbso_1.hready\, readdata51_1 => - \gpt.timer0.comb.2.readdata51_1\, N_227 => - \ua1.uart1.N_227\, thempty_1_m => - \ua1.uart1.uartop.thempty_1_m\, N_6432 => N_6432, rmw => - \sr1.r.mcfg2.rmw\, penable => \apbi.penable\, un1_apbi_2 - => \gpt.timer0.comb.1.un1_apbi_2\, N_5062 => N_5062, - break_m => \ua1.uart1.r.break_m\, N_332 => - \dcomgen.dcom0.dcom_uart0.N_332\, N_333 => - \dcomgen.dcom0.dcom_uart0.N_333\, N_334 => - \dcomgen.dcom0.dcom_uart0.N_334\, N_335 => - \dcomgen.dcom0.dcom_uart0.N_335\, N_336 => - \dcomgen.dcom0.dcom_uart0.N_336\, N_5070 => N_5070, - breakirqen => \ua1.uart1.r.breakirqen\, N_6455_0 => - N_6455_0, N_773 => \apb0.N_773\, hwrite => \ahbsi.hwrite\, - un1_apbi_7_3 => \lfrtimemanagement_0.un1_apbi_7_3\, N_330 - => \dcomgen.dcom0.dcom_uart0.N_330\, parerr_m => - \ua1.uart1.r.parerr_m\, rdata60_1 => - \ua1.uart1.uartop.rdata60_1\, N_331 => - \dcomgen.dcom0.dcom_uart0.N_331\, N_86 => - \dcomgen.dcom0.dcom_uart0.N_86\, N_85 => - \dcomgen.dcom0.dcom_uart0.N_85\, un1_apbi_7_1 => - \lfrtimemanagement_0.un1_apbi_7_1\, rstn => rstn, bexcen - => \sr1.r.mcfg1.bexcen\, ioen => \sr1.r.mcfg1.ioen\, - ovf_m => \ua1.uart1.r.ovf_m\, parsel_m_0 => - \ua1.uart1.r.parsel_m_0\, frame => \ua1.uart1.r.frame\, - tcnt_i => \ua1.uart1.uartop.un1_r.tcnt_i\, N_156 => - \ua1.uart1.N_156\, readdata56 => - \gpt.timer0.comb.readdata56\, tfifoirqen_m => - \ua1.uart1.r.tfifoirqen_m\, rfifoirqen_m => - \ua1.uart1.r.rfifoirqen_m\, debug_m => - \ua1.uart1.r.debug_m\, delayirqen => - \ua1.uart1.r.delayirqen\, N_127 => - \dcomgen.dcom0.dcom_uart0.N_127\, N_78 => \apb0.N_78\, - N_232_0 => \ua1.uart1.N_232_0\, brdyen => - \sr1.r.mcfg1.brdyen\, N_839 => \irqctrl.irqctrl0.N_839\, - prdata_1_sqmuxa => \irqctrl.irqctrl0.prdata_1_sqmuxa\, - N_842 => \irqctrl.irqctrl0.N_842\, N_841 => - \irqctrl.irqctrl0.N_841\, N_476 => - \irqctrl.irqctrl0.N_476\, N_478 => - \irqctrl.irqctrl0.N_478\, N_474 => - \irqctrl.irqctrl0.N_474\, N_473 => - \irqctrl.irqctrl0.N_473\, N_471 => - \irqctrl.irqctrl0.N_471\, N_472 => - \irqctrl.irqctrl0.N_472\, N_470 => - \irqctrl.irqctrl0.N_470\, N_467 => - \irqctrl.irqctrl0.N_467\, N_468 => - \irqctrl.irqctrl0.N_468\, N_859 => - \irqctrl.irqctrl0.N_859\, N_861 => - \irqctrl.irqctrl0.N_861\, N_361 => - \irqctrl.irqctrl0.N_361\, N_363 => - \irqctrl.irqctrl0.N_363\, readdata55_3 => - \gpt.timer0.comb.readdata55_3\, N_863 => - \irqctrl.irqctrl0.N_863\, N_865 => - \irqctrl.irqctrl0.N_865\, N_365 => - \irqctrl.irqctrl0.N_365\, N_898 => - \irqctrl.irqctrl0.N_898\, N_367 => - \irqctrl.irqctrl0.N_367\, prdata_0_sqmuxa => - \irqctrl.irqctrl0.prdata_0_sqmuxa\, rdata60_4_0 => - \ua1.uart1.uartop.rdata60_4_0\, N_6437 => N_6437, N_6439 - => N_6439, N_6435 => N_6435, N_6436 => N_6436, N_6434 - => N_6434, N_6429 => N_6429, N_6430 => N_6430, N_6428 - => N_6428, rdata59_4 => \ua1.uart1.uartop.rdata59_4\, - N_220_0 => \gpt.timer0.N_220\, N_219 => - \gpt.timer0.N_219\, N_240 => \gpt.timer0.N_240\, N_218 - => \gpt.timer0.N_218\, N_236 => \gpt.timer0.N_236\, - N_229 => \gpt.timer0.N_229\, N_228 => \gpt.timer0.N_228\, - N_216 => \gpt.timer0.N_216\, N_217 => \gpt.timer0.N_217\, - dishlt => \gpt.timer0.r.dishlt\, restart_RNIIKBB => - \r.timers_2.restart_RNIIKBB\, N_215 => \gpt.timer0.N_215\, - N_214 => \gpt.timer0.N_214\, N_240_0 => - \gpt.timer0.N_240_0\, readdata57 => - \gpt.timer0.comb.readdata57\, irqpen_m => - \gpt.timer0.r.timers_2.irqpen_m\, readdata55 => - \gpt.timer0.comb.readdata55\, enable_m => - \gpt.timer0.r.timers_2.enable_m\, value_0_sqmuxa_0 => - \gpt.timer0.v.timers_2.value_0_sqmuxa_0\, chain_m => - \gpt.timer0.r.timers_2.chain_m\, readdata_1_sqmuxa_1_0 - => \gpt.timer0.readdata_1_sqmuxa_1_0\, tsemptyirqen => - \ua1.uart1.r.tsemptyirqen\, rdata_0_sqmuxa => - \ua1.uart1.rdata_0_sqmuxa\, N_223 => \ua1.uart1.N_223\, - N_220 => \ua1.uart1.N_220\, rdata_3_sqmuxa => - \ua1.uart1.rdata_3_sqmuxa\, rdata_4_sqmuxa => - \ua1.uart1.rdata_4_sqmuxa\, paren => \ua1.uart1.r.paren\, - N_770 => \apb0.N_770\, rhalffull_1_m => - \ua1.uart1.uartop.rhalffull_1_m\, flow_m => - \ua1.uart1.r.flow_m\, extclken_m => - \ua1.uart1.r.extclken_m\, N_769 => \apb0.N_769\, N_116 - => \apb0.N_116\, N_796 => \apb0.N_796\, N_750 => - \apb0.N_750\, N_749 => \apb0.N_749\, lclk_c => lclk_c, - pwrite => \apbi.pwrite\, un51_ioen_NE => - \ahb0.comb.1.4.un51_ioen_NE\); - - \address_pad[0]\ : OUTBUF - port map(D => \address_c[0]\, PAD => address(0)); - - \pci_ad_pad[26]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(26)); - - lclk_RNIU342 : CLKINT - port map(A => lclk_i, Y => lclk_c); - - nOE_pad : OUTBUF - port map(D => \state_RNIFS55[4]\, PAD => nOE); - - \data_pad[16]\ : BIBUF - port map(PAD => data(16), D => \memo.data[16]\, E => - \memo.bdrive_i[1]\, Y => \data_in[16]\); - - nBWb_pad : OUTBUF - port map(D => nBWb_c, PAD => nBWb); - - cnv_ch1_pad : OUTBUF - port map(D => cnv_ch1_c, PAD => cnv_ch1); - - \address_pad[14]\ : OUTBUF - port map(D => \address_c[14]\, PAD => address(14)); - - \ocram.ahbram0\ : ahbram - port map(hwdata(31) => \ahbsi.hwdata[31]\, hwdata(30) => - \ahbsi.hwdata[30]\, hwdata(29) => \ahbsi.hwdata[29]\, - hwdata(28) => \ahbsi.hwdata[28]\, hwdata(27) => - \ahbsi.hwdata[27]\, hwdata(26) => \ahbsi.hwdata[26]\, - hwdata(25) => \ahbsi.hwdata[25]\, hwdata(24) => - \ahbsi.hwdata[24]\, hwdata(23) => \ahbsi.hwdata[23]\, - hwdata(22) => \ahbsi.hwdata[22]\, hwdata(21) => - \ahbsi.hwdata[21]\, hwdata(20) => \ahbsi.hwdata[20]\, - hwdata(19) => \ahbsi.hwdata[19]\, hwdata(18) => - \ahbsi.hwdata[18]\, hwdata(17) => \ahbsi.hwdata[17]\, - hwdata(16) => \ahbsi.hwdata[16]\, hwdata(15) => - \ahbsi.hwdata[15]\, hwdata(14) => \ahbsi.hwdata[14]\, - hwdata(13) => \ahbsi.hwdata[13]\, hwdata(12) => - \ahbsi.hwdata[12]\, hwdata(11) => \ahbsi.hwdata[11]\, - hwdata(10) => \ahbsi.hwdata[10]\, hwdata(9) => - \ahbsi.hwdata[9]\, hwdata(8) => \ahbsi.hwdata[8]\, - hwdata(7) => \ahbsi.hwdata[7]\, hwdata(6) => - \ahbsi.hwdata[6]\, hwdata(5) => \ahbsi.hwdata[5]\, - hwdata(4) => \ahbsi.hwdata[4]\, hwdata(3) => - \ahbsi.hwdata[3]\, hwdata(2) => \ahbsi.hwdata[2]\, - hwdata(1) => \ahbsi.hwdata[1]\, hwdata(0) => - \ahbsi.hwdata[0]\, hrdata(31) => \ahbso_7.hrdata[31]\, - hrdata(30) => \ahbso_7.hrdata[30]\, hrdata(29) => - \ahbso_7.hrdata[29]\, hrdata(28) => \ahbso_7.hrdata[28]\, - hrdata(27) => \ahbso_7.hrdata[27]\, hrdata(26) => - \ahbso_7.hrdata[26]\, hrdata(25) => \ahbso_7.hrdata[25]\, - hrdata(24) => \ahbso_7.hrdata[24]\, hrdata(23) => - \ahbso_7.hrdata[23]\, hrdata(22) => \ahbso_7.hrdata[22]\, - hrdata(21) => \ahbso_7.hrdata[21]\, hrdata(20) => - \ahbso_7.hrdata[20]\, hrdata(19) => \ahbso_7.hrdata[19]\, - hrdata(18) => \ahbso_7.hrdata[18]\, hrdata(17) => - \ahbso_7.hrdata[17]\, hrdata(16) => \ahbso_7.hrdata[16]\, - hrdata(15) => \ahbso_7.hrdata[15]\, hrdata(14) => - \ahbso_7.hrdata[14]\, hrdata(13) => \ahbso_7.hrdata[13]\, - hrdata(12) => \ahbso_7.hrdata[12]\, hrdata(11) => - \ahbso_7.hrdata[11]\, hrdata(10) => \ahbso_7.hrdata[10]\, - hrdata(9) => \ahbso_7.hrdata[9]\, hrdata(8) => - \ahbso_7.hrdata[8]\, hrdata(7) => \ahbso_7.hrdata[7]\, - hrdata(6) => \ahbso_7.hrdata[6]\, hrdata(5) => - \ahbso_7.hrdata[5]\, hrdata(4) => \ahbso_7.hrdata[4]\, - hrdata(3) => \ahbso_7.hrdata[3]\, hrdata(2) => - \ahbso_7.hrdata[2]\, hrdata(1) => \ahbso_7.hrdata[1]\, - hrdata(0) => \ahbso_7.hrdata[0]\, hsize(1) => - \ahbsi.hsize[1]\, hsize(0) => \ahbsi.hsize[0]\, iosn(93) - => \sr1.iosn[93]\, htrans(1) => \ahbsi.htrans[1]\, - iosn_1(93) => \sr1.iosn_1[93]\, haddr(9) => - \ahbsi.haddr[9]\, haddr(8) => \ahbsi.haddr[8]\, haddr(7) - => \ahbsi.haddr[7]\, haddr(6) => \ahbsi.haddr[6]\, - haddr(5) => \ahbsi.haddr[5]\, haddr(4) => - \ahbsi.haddr[4]\, haddr(3) => \ahbsi.haddr[3]\, haddr(2) - => \ahbsi.haddr[2]\, haddr(1) => \ahbsi.haddr[1]\, - haddr(0) => \ahbsi.haddr[0]\, lclk_c => lclk_c, - un315_ioen_NE => \ahb0.comb.7.4.un315_ioen_NE\, hready - => \ahbso_7.hready\, hwrite_1 => \ahbsi.hwrite\, rstn - => rstn); - - \gpio_pad[4]\ : BIBUF - port map(PAD => gpio(4), D => \gpioo.dout[4]\, E => - \gpioo.oen_i[4]\, Y => \gpio_in[4]\); - - \data_pad[21]\ : BIBUF - port map(PAD => data(21), D => \memo.data[21]\, E => - \memo.bdrive_i[1]\, Y => \data_in[21]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \address_pad[12]\ : OUTBUF - port map(D => \address_c[12]\, PAD => address(12)); - - resetn_pad : CLKBUF - port map(PAD => resetn, Y => rstraw_c); - - dsuact_pad : OUTBUF - port map(D => \GND\, PAD => dsuact); - - txd1_pad : OUTBUF - port map(D => txd1_c, PAD => txd1); - - SSRAM_CLK_pad : OUTBUF - port map(D => clk_c_i, PAD => SSRAM_CLK); - - esleep_pad : OUTBUF - port map(D => \GND\, PAD => esleep); - - \data_pad[28]\ : BIBUF - port map(PAD => data(28), D => \memo.data[28]\, E => - \memo.bdrive_i[0]\, Y => \data_in[28]\); - - pci_serr_pad : OUTBUF - port map(D => \GND\, PAD => pci_serr); - - pci_par_pad : OUTBUF - port map(D => \GND\, PAD => pci_par); - - lpp_bootloader_1 : lpp_bootloader - port map(haddr(9) => \ahbsi.haddr[9]\, haddr(8) => - \ahbsi.haddr[8]\, haddr(7) => \ahbsi.haddr[7]\, haddr(6) - => \ahbsi.haddr[6]\, haddr(5) => \ahbsi.haddr[5]\, - haddr(4) => \ahbsi.haddr[4]\, haddr(3) => - \ahbsi.haddr[3]\, haddr(2) => \ahbsi.haddr[2]\, hrdata_26 - => \ahbso_6.hrdata[26]\, hrdata_13 => - \ahbso_6.hrdata[13]\, hrdata_8 => \ahbso_6.hrdata[8]\, - hrdata_5 => \ahbso_6.hrdata[5]\, hrdata_29 => - \ahbso_6.hrdata[29]\, hrdata_18 => \ahbso_6.hrdata[18]\, - hrdata_6 => \ahbso_6.hrdata[6]\, hrdata_19 => - \ahbso_6.hrdata[19]\, hrdata_17 => \ahbso_6.hrdata[17]\, - hrdata_7 => \ahbso_6.hrdata[7]\, hrdata_16 => - \ahbso_6.hrdata[16]\, hrdata_30 => \ahbso_6.hrdata[30]\, - hrdata_9 => \ahbso_6.hrdata[9]\, hrdata_25 => - \ahbso_6.hrdata[25]\, hrdata_27 => \ahbso_6.hrdata[27]\, - hrdata_21 => \ahbso_6.hrdata[21]\, hrdata_3 => - \ahbso_6.hrdata[3]\, hrdata_0 => \ahbso_6.hrdata[0]\, - hrdata_1 => \ahbso_6.hrdata[1]\, hrdata_23 => - \ahbso_6.hrdata[23]\, hrdata_4 => \ahbso_6.hrdata[4]\, - hrdata_28 => \ahbso_6.hrdata[28]\, hrdata_14 => - \ahbso_6.hrdata[14]\, hrdata_22 => \ahbso_6.hrdata[22]\, - hrdata_15 => \ahbso_6.hrdata[15]\, hrdata_2 => - \ahbso_6.hrdata[2]\, hrdata_11 => \ahbso_6.hrdata[11]\, - hrdata_10 => \ahbso_6.hrdata[10]\, hrdata_12 => - \ahbso_6.hrdata[12]\, prdata(31) => \apbo_13.prdata[31]\, - prdata(30) => \apbo_13.prdata[30]\, prdata(29) => - \apbo_13.prdata[29]\, prdata(28) => \apbo_13.prdata[28]\, - prdata(27) => \apbo_13.prdata[27]\, prdata(26) => - \apbo_13.prdata[26]\, prdata(25) => \apbo_13.prdata[25]\, - prdata(24) => \apbo_13.prdata[24]\, prdata(23) => - \apbo_13.prdata[23]\, prdata(22) => \apbo_13.prdata[22]\, - prdata(21) => \apbo_13.prdata[21]\, prdata(20) => - \apbo_13.prdata[20]\, prdata(19) => \apbo_13.prdata[19]\, - prdata(18) => \apbo_13.prdata[18]\, prdata(17) => - \apbo_13.prdata[17]\, prdata(16) => \apbo_13.prdata[16]\, - prdata(15) => \apbo_13.prdata[15]\, prdata(14) => - \apbo_13.prdata[14]\, prdata(13) => \apbo_13.prdata[13]\, - prdata(12) => \apbo_13.prdata[12]\, prdata(11) => - \apbo_13.prdata[11]\, prdata(10) => \apbo_13.prdata[10]\, - prdata(9) => \apbo_13.prdata[9]\, prdata(8) => - \apbo_13.prdata[8]\, prdata(7) => \apbo_13.prdata[7]\, - prdata(6) => \apbo_13.prdata[6]\, prdata(5) => - \apbo_13.prdata[5]\, prdata(4) => \apbo_13.prdata[4]\, - prdata(3) => \apbo_13.prdata[3]\, prdata(2) => - \apbo_13.prdata[2]\, prdata(1) => \apbo_13.prdata[1]\, - prdata(0) => \apbo_13.prdata[0]\, pwdata_1_3 => - \apbi.pwdata_1[4]\, pwdata_1_2 => \apbi.pwdata_1[3]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, pwdata_31 => - \apbi.pwdata[31]\, pwdata_30 => \apbi.pwdata[30]\, - pwdata_29 => \apbi.pwdata[29]\, pwdata_28 => - \apbi.pwdata[28]\, pwdata_27 => \apbi.pwdata[27]\, - pwdata_26 => \apbi.pwdata[26]\, pwdata_25 => - \apbi.pwdata[25]\, pwdata_24 => \apbi.pwdata[24]\, - pwdata_23 => \apbi.pwdata[23]\, pwdata_22 => - \apbi.pwdata[22]\, pwdata_21 => \apbi.pwdata[21]\, - pwdata_20 => \apbi.pwdata[20]\, pwdata_19 => - \apbi.pwdata[19]\, pwdata_18 => \apbi.pwdata[18]\, - pwdata_17 => \apbi.pwdata[17]\, pwdata_16 => - \apbi.pwdata[16]\, pwdata_15 => \apbi.pwdata[15]\, - pwdata_14 => \apbi.pwdata[14]\, pwdata_13 => - \apbi.pwdata[13]\, pwdata_12 => \apbi.pwdata[12]\, - pwdata_11 => \apbi.pwdata[11]\, pwdata_10 => - \apbi.pwdata[10]\, pwdata_9 => \apbi.pwdata[9]\, pwdata_8 - => \apbi.pwdata[8]\, pwdata_7 => \apbi.pwdata[7]\, - pwdata_6 => \apbi.pwdata[6]\, pwdata_5 => - \apbi.pwdata[5]\, pwdata_2 => \apbi.pwdata[2]\, pwdata_0 - => \apbi.pwdata[0]\, N_103_i_0 => - \lpp_bootloader_1.ahbrom_1.N_103_i_0\, N_90_i_0 => - \lpp_bootloader_1.ahbrom_1.N_90_i_0\, N_95_i_0 => - \lpp_bootloader_1.ahbrom_1.N_95_i_0\, rstraw_c => - rstraw_c, lclk_c => lclk_c, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, N_6459 => N_6459, rdata59_4 - => \ua1.uart1.uartop.rdata59_4\, readdata55_3 => - \gpt.timer0.comb.readdata55_3\, rdata62_3 => - \ua1.uart1.uartop.rdata62_3\, N_750 => \apb0.N_750\, - un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\, rdata60_4_0 - => \ua1.uart1.uartop.rdata60_4_0\, N_796 => \apb0.N_796\); - - \pci_ad_pad[18]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(18)); - - \gpio_pad[5]\ : BIBUF - port map(PAD => gpio(5), D => \gpioo.dout[5]\, E => - \gpioo.oen_i[5]\, Y => \gpio_in[5]\); - - \sdo_adc_pad[7]\ : INBUF - port map(PAD => sdo_adc(7), Y => \sdo_adc_c[7]\); - - \data_pad[25]\ : BIBUF - port map(PAD => data(25), D => \memo.data[25]\, E => - \memo.bdrive_i[0]\, Y => \data_in[25]\); - - nBWd_pad : OUTBUF - port map(D => nBWd_c, PAD => nBWd); - - emddis_pad : OUTBUF - port map(D => \GND\, PAD => emddis); - - \address_pad[18]\ : OUTBUF - port map(D => \address_c[18]\, PAD => address(18)); - - \pci_ad_pad[7]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(7)); - - \data_pad[14]\ : BIBUF - port map(PAD => data(14), D => \memo.data[14]\, E => - \memo.bdrive_i[2]\, Y => \data_in[14]\); - - nCE1_pad : OUTBUF - port map(D => nCE1_c, PAD => nCE1); - - nGW_pad : OUTBUF - port map(D => \VCC\, PAD => nGW); - - \data_pad[7]\ : BIBUF - port map(PAD => data(7), D => \memo.data[7]\, E => - \memo.bdrive_i[3]\, Y => \data_in[7]\); - - nCE3_pad : OUTBUF - port map(D => nCE3_c, PAD => nCE3); - - iosn_pad : OUTBUF - port map(D => iosn_c, PAD => iosn); - - waveform_picker0 : lpp_top_lfr_wf_picker - port map(sdo_adc_c(7) => \sdo_adc_c[7]\, sdo_adc_c(6) => - \sdo_adc_c[6]\, sdo_adc_c(5) => \sdo_adc_c[5]\, - sdo_adc_c(4) => \sdo_adc_c[4]\, sdo_adc_c(3) => - \sdo_adc_c[3]\, sdo_adc_c(2) => \sdo_adc_c[2]\, - sdo_adc_c(1) => \sdo_adc_c[1]\, sdo_adc_c(0) => - \sdo_adc_c[0]\, hburst(2) => \ahbmo_3.hburst[2]\, - hburst(1) => \ahbmo_3.hburst[1]\, hburst(0) => - \ahbmo_3.hburst[0]\, htrans(1) => \ahbmo_3.htrans[1]\, - htrans(0) => \ahbmo_3.htrans[0]\, iosn_2(93) => - \sr1.iosn_2[93]\, hresp(0) => \ahbmi.hresp[0]\, - iosn_1(93) => \sr1.iosn_1[93]\, nhmaster_1_i(0) => - \ahb0.comb.nhmaster_1_i[0]\, hsize(1) => - \ahbmo_3.hsize[1]\, hsize(0) => \ahbmo_3.hsize[0]\, - hmaster_0(1) => \ahbsi.hmaster_0[1]\, haddr(31) => - \ahbmo_3.haddr[31]\, haddr(30) => \ahbmo_3.haddr[30]\, - haddr(29) => \ahbmo_3.haddr[29]\, haddr(28) => - \ahbmo_3.haddr[28]\, haddr(27) => \ahbmo_3.haddr[27]\, - haddr(26) => \ahbmo_3.haddr[26]\, haddr(25) => - \ahbmo_3.haddr[25]\, haddr(24) => \ahbmo_3.haddr[24]\, - haddr(23) => \ahbmo_3.haddr[23]\, haddr(22) => - \ahbmo_3.haddr[22]\, haddr(21) => \ahbmo_3.haddr[21]\, - haddr(20) => \ahbmo_3.haddr[20]\, haddr(19) => - \ahbmo_3.haddr[19]\, haddr(18) => \ahbmo_3.haddr[18]\, - haddr(17) => \ahbmo_3.haddr[17]\, haddr(16) => - \ahbmo_3.haddr[16]\, haddr(15) => \ahbmo_3.haddr[15]\, - haddr(14) => \ahbmo_3.haddr[14]\, haddr(13) => - \ahbmo_3.haddr[13]\, haddr(12) => \ahbmo_3.haddr[12]\, - haddr(11) => \ahbmo_3.haddr[11]\, haddr(10) => - \ahbmo_3.haddr[10]\, haddr(9) => \ahbmo_3.haddr[9]\, - haddr(8) => \ahbmo_3.haddr[8]\, haddr(7) => - \ahbmo_3.haddr[7]\, haddr(6) => \ahbmo_3.haddr[6]\, - haddr(5) => \ahbmo_3.haddr[5]\, haddr(4) => - \ahbmo_3.haddr[4]\, haddr(3) => \ahbmo_3.haddr[3]\, - haddr(2) => \ahbmo_3.haddr[2]\, haddr(1) => - \ahbmo_3.haddr[1]\, haddr(0) => \ahbmo_3.haddr[0]\, - bco_msb_1(1) => \ahb0.bco_msb_1[1]\, - hmaster_0_0_RNIFCVH1_0(1) => - \r.hmaster_0_0_RNIFCVH1_0[1]\, hgrant(3) => - \ahbmi.hgrant[3]\, iosn_0(93) => \sr1.iosn_0[93]\, - bco_msb_1_m(1) => \ahb0.bco_msb_1_m[1]\, - nhmaster_1_iv_0(1) => \ahb0.comb.nhmaster_1_iv_0[1]\, - l1_0_m(1) => \ahb0.l1_0_m[1]\, hwdata(31) => - \ahbmo_3.hwdata[31]\, hwdata(30) => \ahbmo_3.hwdata[30]\, - hwdata(29) => \ahbmo_3.hwdata[29]\, hwdata(28) => - \ahbmo_3.hwdata[28]\, hwdata(27) => \ahbmo_3.hwdata[27]\, - hwdata(26) => \ahbmo_3.hwdata[26]\, hwdata(25) => - \ahbmo_3.hwdata[25]\, hwdata(24) => \ahbmo_3.hwdata[24]\, - hwdata(23) => \ahbmo_3.hwdata[23]\, hwdata(22) => - \ahbmo_3.hwdata[22]\, hwdata(21) => \ahbmo_3.hwdata[21]\, - hwdata(20) => \ahbmo_3.hwdata[20]\, hwdata(19) => - \ahbmo_3.hwdata[19]\, hwdata(18) => \ahbmo_3.hwdata[18]\, - hwdata(17) => \ahbmo_3.hwdata[17]\, hwdata(16) => - \ahbmo_3.hwdata[16]\, hwdata(15) => \ahbmo_3.hwdata[15]\, - hwdata(14) => \ahbmo_3.hwdata[14]\, hwdata(13) => - \ahbmo_3.hwdata[13]\, hwdata(12) => \ahbmo_3.hwdata[12]\, - hwdata(11) => \ahbmo_3.hwdata[11]\, hwdata(10) => - \ahbmo_3.hwdata[10]\, hwdata(9) => \ahbmo_3.hwdata[9]\, - hwdata(8) => \ahbmo_3.hwdata[8]\, hwdata(7) => - \ahbmo_3.hwdata[7]\, hwdata(6) => \ahbmo_3.hwdata[6]\, - hwdata(5) => \ahbmo_3.hwdata[5]\, hwdata(4) => - \ahbmo_3.hwdata[4]\, hwdata(3) => \ahbmo_3.hwdata[3]\, - hwdata(2) => \ahbmo_3.hwdata[2]\, hwdata(1) => - \ahbmo_3.hwdata[1]\, hwdata(0) => \ahbmo_3.hwdata[0]\, - coarse_time(0) => \coarse_time[0]\, coarse_time_i(0) => - \coarse_time_i[0]\, pwdata_0(11) => \apbi.pwdata_0[11]\, - pwdata_0(10) => \apbi.pwdata_0[10]\, pwdata_0(9) => - \apbi.pwdata_0[9]\, pwdata_0(8) => \apbi.pwdata_0[8]\, - pwdata_0(7) => \apbi.pwdata_0[7]\, pwdata_0(6) => - \apbi.pwdata_0[6]\, pwdata_0(5) => \apbi.pwdata_0[5]\, - pwdata_0(4) => \apbi.pwdata_0[4]\, pwdata_0(3) => - \apbi.pwdata_0[3]\, pwdata_0(2) => \apbi.pwdata_0[2]\, - pwdata_0(1) => \apbi.pwdata_0[1]\, pwdata_0(0) => - \apbi.pwdata_0[0]\, paddr_0(4) => \apbi.paddr_0[4]\, - paddr_0(3) => \apbi.paddr_0[3]\, paddr_0(2) => - \apbi.paddr_0[2]\, paddr(7) => \apbi.paddr[7]\, paddr(6) - => \apbi.paddr[6]\, paddr(5) => \apbi.paddr[5]\, - paddr(4) => \apbi.paddr[4]\, paddr(3) => \apbi.paddr[3]\, - paddr_2(2) => \apbi.paddr_2[2]\, pwdata_1_2 => - \apbi.pwdata_1[3]\, pwdata_1_3 => \apbi.pwdata_1[4]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, pwdata(31) => - \apbi.pwdata[31]\, pwdata(30) => \apbi.pwdata[30]\, - pwdata(29) => \apbi.pwdata[29]\, pwdata(28) => - \apbi.pwdata[28]\, pwdata(27) => \apbi.pwdata[27]\, - pwdata(26) => \apbi.pwdata[26]\, pwdata(25) => - \apbi.pwdata[25]\, pwdata(24) => \apbi.pwdata[24]\, - pwdata(23) => \apbi.pwdata[23]\, pwdata(22) => - \apbi.pwdata[22]\, pwdata(21) => \apbi.pwdata[21]\, - pwdata(20) => \apbi.pwdata[20]\, pwdata(19) => - \apbi.pwdata[19]\, pwdata(18) => \apbi.pwdata[18]\, - pwdata(17) => \apbi.pwdata[17]\, pwdata(16) => - \apbi.pwdata[16]\, pwdata(15) => \apbi.pwdata[15]\, - pwdata(14) => \apbi.pwdata[14]\, pwdata(13) => - \apbi.pwdata[13]\, pwdata(12) => \apbi.pwdata[12]\, - pwdata(11) => \apbi.pwdata[11]\, pwdata(10) => - \apbi.pwdata[10]\, pwdata(9) => \apbi.pwdata[9]\, - pwdata(8) => \apbi.pwdata[8]\, pwdata(7) => - \apbi.pwdata[7]\, pwdata(6) => \apbi.pwdata[6]\, - pwdata(5) => \apbi.pwdata[5]\, pwdata(4) => - \apbi.pwdata[4]\, pwdata(3) => \apbi.pwdata[3]\, - pwdata(2) => \apbi.pwdata[2]\, pwdata(1) => - \apbi.pwdata[1]\, pwdata(0) => \apbi.pwdata[0]\, pirq(15) - => \apbi.pirq[15]\, prdata(31) => \apbo_14.prdata[31]\, - prdata(30) => \apbo_14.prdata[30]\, prdata(29) => - \apbo_14.prdata[29]\, prdata(28) => \apbo_14.prdata[28]\, - prdata(27) => \apbo_14.prdata[27]\, prdata(26) => - \apbo_14.prdata[26]\, prdata(25) => \apbo_14.prdata[25]\, - prdata(24) => \apbo_14.prdata[24]\, prdata(23) => - \apbo_14.prdata[23]\, prdata(22) => \apbo_14.prdata[22]\, - prdata(21) => \apbo_14.prdata[21]\, prdata(20) => - \apbo_14.prdata[20]\, prdata(19) => \apbo_14.prdata[19]\, - prdata(18) => \apbo_14.prdata[18]\, prdata(17) => - \apbo_14.prdata[17]\, prdata(16) => \apbo_14.prdata[16]\, - prdata(15) => \apbo_14.prdata[15]\, prdata(14) => - \apbo_14.prdata[14]\, prdata(13) => \apbo_14.prdata[13]\, - prdata(12) => \apbo_14.prdata[12]\, prdata(11) => - \apbo_14.prdata[11]\, prdata(10) => \apbo_14.prdata[10]\, - prdata(9) => \apbo_14.prdata[9]\, prdata(8) => - \apbo_14.prdata[8]\, prdata(7) => \apbo_14.prdata[7]\, - prdata(6) => \apbo_14.prdata[6]\, prdata(5) => - \apbo_14.prdata[5]\, prdata(4) => \apbo_14.prdata[4]\, - prdata(3) => \apbo_14.prdata[3]\, prdata(2) => - \apbo_14.prdata[2]\, prdata(1) => \apbo_14.prdata[1]\, - prdata(0) => \apbo_14.prdata[0]\, - lpp_top_lfr_wf_picker_VCC => \VCC\, clk49_152MHz_c => - clk49_152MHz_c, cnv_ch1_c => cnv_ch1_c, sck_ch1_c => - sck_ch1_c, lpp_top_lfr_wf_picker_GND => \GND\, IdlePhase - => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.IdlePhase\, - hwrite => \ahbmo_3.hwrite\, un1_dmain_6 => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.un1_dmain_6\, - arb_1 => \ahb0.comb.arb_1\, hbusreq_i_3 => - \ahbmo_3.hbusreq_i_3\, Lock_RNIU86D => - \DMAIn.Lock_RNIU86D\, un1_nhmaster_0_sqmuxa_1 => - \ahb0.un1_nhmaster_0_sqmuxa_1\, rstoutl_RNIGJKSJO => - rstoutl_RNIGJKSJO, m19_0_N_15_i_0_li => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_0_N_15_i_0_li\, - m19_a0_6_i_0 => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a0_6_i_0\, - m19_a1_6_i_0 => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a1_6_i_0\, - m26_m1_e => m26_m1_e, lclk_c => lclk_c, rstn => rstn, - N_232 => \ua1.uart1.N_232\, N_6455_0 => N_6455_0, - Bias_Fails_c => Bias_Fails_c, N_749 => \apb0.N_749\, - N_116 => \apb0.N_116\, N_769 => \apb0.N_769\, N_232_0 => - \ua1.uart1.N_232_0\, N_232_1 => \ua1.uart1.N_232_1\, - rdata61_2 => \ua1.uart1.uartop.rdata61_2\, N_6455 => - N_6455, un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\); - - nBWc_pad : OUTBUF - port map(D => nBWc_c, PAD => nBWc); - - \gpio_pad[0]\ : BIBUF - port map(PAD => gpio(0), D => \gpioo.dout[0]\, E => - \gpioo.oen_i[0]\, Y => \gpio_in[0]\); - - clk49_152MHz_pad : INBUF - port map(PAD => clk49_152MHz, Y => clk49_152MHz_c); - - \sdo_adc_pad[0]\ : INBUF - port map(PAD => sdo_adc(0), Y => \sdo_adc_c[0]\); - - \address_pad[9]\ : OUTBUF - port map(D => \address_c[9]\, PAD => address(9)); - - \data_pad[12]\ : BIBUF - port map(PAD => data(12), D => \memo.data[12]\, E => - \memo.bdrive_i[2]\, Y => \data_in[12]\); - - txd2_pad : OUTBUF - port map(D => \GND\, PAD => txd2); - - \pci_ad_pad[9]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(9)); - - \pci_ad_pad[17]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(17)); - - \pci_ad_pad[8]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(8)); - - pci_lock_pad : OUTBUF - port map(D => \GND\, PAD => pci_lock); - - \ramoen_pad[3]\ : OUTBUF - port map(D => \ramoen_c[3]\, PAD => ramoen(3)); - - \gpio_pad[1]\ : BIBUF - port map(PAD => gpio(1), D => \gpioo.dout[1]\, E => - \gpioo.oen_i[1]\, Y => \gpio_in[1]\); - - \sdo_adc_pad[3]\ : INBUF - port map(PAD => sdo_adc(3), Y => \sdo_adc_c[3]\); - - \romsn_pad[1]\ : OUTBUF - port map(D => \romsn_c[1]\, PAD => romsn(1)); - - \data_pad[31]\ : BIBUF - port map(PAD => data(31), D => \memo.data[31]\, E => - \memo.bdrive_i[0]\, Y => \data_in[31]\); - - \dcomgen.dcom0\ : ahbuart - port map(haddr(31) => \ahbmo_1.haddr[31]\, haddr(30) => - \ahbmo_1.haddr[30]\, haddr(29) => \ahbmo_1.haddr[29]\, - haddr(28) => \ahbmo_1.haddr[28]\, haddr(27) => - \ahbmo_1.haddr[27]\, haddr(26) => \ahbmo_1.haddr[26]\, - haddr(25) => \ahbmo_1.haddr[25]\, haddr(24) => - \ahbmo_1.haddr[24]\, haddr(23) => \ahbmo_1.haddr[23]\, - haddr(22) => \ahbmo_1.haddr[22]\, haddr(21) => - \ahbmo_1.haddr[21]\, haddr(20) => \ahbmo_1.haddr[20]\, - haddr(19) => \ahbmo_1.haddr[19]\, haddr(18) => - \ahbmo_1.haddr[18]\, haddr(17) => \ahbmo_1.haddr[17]\, - haddr(16) => \ahbmo_1.haddr[16]\, haddr(15) => - \ahbmo_1.haddr[15]\, haddr(14) => \ahbmo_1.haddr[14]\, - haddr(13) => \ahbmo_1.haddr[13]\, haddr(12) => - \ahbmo_1.haddr[12]\, haddr(11) => \ahbmo_1.haddr[11]\, - haddr(10) => \ahbmo_1.haddr[10]\, haddr(9) => - \ahbmo_1.haddr[9]\, haddr(8) => \ahbmo_1.haddr[8]\, - haddr(7) => \ahbmo_1.haddr[7]\, haddr(6) => - \ahbmo_1.haddr[6]\, haddr(5) => \ahbmo_1.haddr[5]\, - haddr(4) => \ahbmo_1.haddr[4]\, haddr(3) => - \ahbmo_1.haddr[3]\, haddr(2) => \ahbmo_1.haddr[2]\, - haddr(1) => \ahbmo_1.haddr[1]\, haddr(0) => - \ahbmo_1.haddr[0]\, iosn_0(93) => \sr1.iosn_0[93]\, - hrdata_0_0 => \ahbmi.hrdata_0[0]\, hrdata_0_24 => - \ahbmi.hrdata_0[24]\, hrdata_0_26 => \ahbmi.hrdata_0[26]\, - hrdata_0_27 => \ahbmi.hrdata_0[27]\, hrdata_0_8 => - \ahbmi.hrdata_0[8]\, hrdata_0_16 => \ahbmi.hrdata_0[16]\, - hrdata_0_18 => \ahbmi.hrdata_0[18]\, hrdata_0_10 => - \ahbmi.hrdata_0[10]\, hrdata_0_22 => \ahbmi.hrdata_0[22]\, - hrdata_0_7 => \ahbmi.hrdata_0[7]\, hrdata_0_17 => - \ahbmi.hrdata_0[17]\, hrdata_0_23 => \ahbmi.hrdata_0[23]\, - hrdata_0_3 => \ahbmi.hrdata_0[3]\, hrdata_0_11 => - \ahbmi.hrdata_0[11]\, hrdata_0_12 => \ahbmi.hrdata_0[12]\, - hrdata_0_4 => \ahbmi.hrdata_0[4]\, hrdata_0_21 => - \ahbmi.hrdata_0[21]\, hrdata_0_15 => \ahbmi.hrdata_0[15]\, - hrdata_0_14 => \ahbmi.hrdata_0[14]\, hrdata_0_13 => - \ahbmi.hrdata_0[13]\, hrdata_0_9 => \ahbmi.hrdata_0[9]\, - hrdata_0_2 => \ahbmi.hrdata_0[2]\, hrdata_0_1 => - \ahbmi.hrdata_0[1]\, hrdata_23 => \ahbmi.hrdata[28]\, - hrdata_25 => \ahbmi.hrdata[30]\, hrdata_26 => - \ahbmi.hrdata[31]\, hrdata_24 => \ahbmi.hrdata[29]\, - hrdata_1 => \ahbmi.hrdata[6]\, hrdata_0_d0 => - \ahbmi.hrdata[5]\, pwdata_0(15) => \apbi.pwdata_0[15]\, - pwdata_0(14) => \apbi.pwdata_0[14]\, pwdata_0(13) => - \apbi.pwdata_0[13]\, pwdata_0(12) => \apbi.pwdata_0[12]\, - pwdata_0(11) => \apbi.pwdata_0[11]\, pwdata_0(10) => - \apbi.pwdata_0[10]\, pwdata_0(9) => \apbi.pwdata_0[9]\, - pwdata_0(8) => \apbi.pwdata_0[8]\, pwdata_0(7) => - \apbi.pwdata_0[7]\, pwdata_0(6) => \apbi.pwdata_0[6]\, - pwdata_0(5) => \apbi.pwdata_0[5]\, pwdata_0(4) => - \apbi.pwdata_0[4]\, pwdata_0(3) => \apbi.pwdata_0[3]\, - pwdata_0(2) => \apbi.pwdata_0[2]\, pwdata_0(1) => - \apbi.pwdata_0[1]\, pwdata_0(0) => \apbi.pwdata_0[0]\, - un1_dcom0(19) => \dcomgen.un1_dcom0[19]\, un1_dcom0(18) - => \dcomgen.un1_dcom0[18]\, un1_dcom0(17) => - \dcomgen.un1_dcom0[17]\, un1_dcom0(16) => - \dcomgen.un1_dcom0[16]\, un1_dcom0(15) => - \dcomgen.un1_dcom0[15]\, un1_dcom0(14) => - \dcomgen.un1_dcom0[14]\, un1_dcom0(13) => - \dcomgen.un1_dcom0[13]\, un1_dcom0(12) => - \dcomgen.un1_dcom0[12]\, pwdata(17) => \apbi.pwdata[17]\, - pwdata(16) => \apbi.pwdata[16]\, psel_1(7) => - \apbi.psel_1[7]\, prdata_0 => \apbo_7.prdata[0]\, - prdata_5 => \apbo_7.prdata[5]\, pwdata_1(4) => - \apbi.pwdata_1[4]\, paddr(3) => \apbi.paddr[3]\, paddr(2) - => \apbi.paddr[2]\, hwdata(31) => \ahbmo_1.hwdata[31]\, - hwdata(30) => \ahbmo_1.hwdata[30]\, hwdata(29) => - \ahbmo_1.hwdata[29]\, hwdata(28) => \ahbmo_1.hwdata[28]\, - hwdata(27) => \ahbmo_1.hwdata[27]\, hwdata(26) => - \ahbmo_1.hwdata[26]\, hwdata(25) => \ahbmo_1.hwdata[25]\, - hwdata(24) => \ahbmo_1.hwdata[24]\, hwdata(23) => - \ahbmo_1.hwdata[23]\, hwdata(22) => \ahbmo_1.hwdata[22]\, - hwdata(21) => \ahbmo_1.hwdata[21]\, hwdata(20) => - \ahbmo_1.hwdata[20]\, hwdata(19) => \ahbmo_1.hwdata[19]\, - hwdata(18) => \ahbmo_1.hwdata[18]\, hwdata(17) => - \ahbmo_1.hwdata[17]\, hwdata(16) => \ahbmo_1.hwdata[16]\, - hwdata(15) => \ahbmo_1.hwdata[15]\, hwdata(14) => - \ahbmo_1.hwdata[14]\, hwdata(13) => \ahbmo_1.hwdata[13]\, - hwdata(12) => \ahbmo_1.hwdata[12]\, hwdata(11) => - \ahbmo_1.hwdata[11]\, hwdata(10) => \ahbmo_1.hwdata[10]\, - hwdata(9) => \ahbmo_1.hwdata[9]\, hwdata(8) => - \ahbmo_1.hwdata[8]\, hwdata(7) => \ahbmo_1.hwdata[7]\, - hwdata(6) => \ahbmo_1.hwdata[6]\, hwdata(5) => - \ahbmo_1.hwdata[5]\, hwdata(4) => \ahbmo_1.hwdata[4]\, - hwdata(3) => \ahbmo_1.hwdata[3]\, hwdata(2) => - \ahbmo_1.hwdata[2]\, hwdata(1) => \ahbmo_1.hwdata[1]\, - hwdata(0) => \ahbmo_1.hwdata[0]\, iosn_2(93) => - \sr1.iosn_2[93]\, htrans(1) => \ahbmo_1.htrans[1]\, - hgrant(1) => \ahbmi.hgrant[1]\, iosn(93) => - \sr1.iosn[93]\, hwrite => \ahbmo_1.hwrite\, N_264_0 => - N_264_0, N_262_0 => N_262_0, N_78_0 => N_78_0, N_78 => - \apb0.N_78\, un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\, - N_86 => \dcomgen.dcom0.dcom_uart0.N_86\, rdata60_1 => - \ua1.uart1.uartop.rdata60_1\, N_85 => - \dcomgen.dcom0.dcom_uart0.N_85\, dsutx_c => dsutx_c, - N_6455_0 => N_6455_0, N_332 => - \dcomgen.dcom0.dcom_uart0.N_332\, N_333 => - \dcomgen.dcom0.dcom_uart0.N_333\, N_334 => - \dcomgen.dcom0.dcom_uart0.N_334\, N_336 => - \dcomgen.dcom0.dcom_uart0.N_336\, N_331 => - \dcomgen.dcom0.dcom_uart0.N_331\, N_6455 => N_6455, N_127 - => \dcomgen.dcom0.dcom_uart0.N_127\, N_330 => - \dcomgen.dcom0.dcom_uart0.N_330\, N_769 => \apb0.N_769\, - un1_apbi_2 => \gpt.timer0.comb.1.un1_apbi_2\, N_335 => - \dcomgen.dcom0.dcom_uart0.N_335\, dsurx_c => dsurx_c, - rstn => rstn, hbusreq_i_3 => \ahbmo_1.hbusreq_i_3\, - lclk_c => lclk_c); - - \address_pad[2]\ : OUTBUF - port map(D => \address_c[2]\, PAD => address(2)); - - \sdo_adc_pad[1]\ : INBUF - port map(PAD => sdo_adc(1), Y => \sdo_adc_c[1]\); - - \pci_ad_pad[10]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(10)); - - \data_pad[10]\ : BIBUF - port map(PAD => data(10), D => \memo.data[10]\, E => - \memo.bdrive_i[2]\, Y => \data_in[10]\); - - ahb0 : ahbctrl - port map(hmbsel(0) => \ahbsi.hmbsel[0]\, htrans_3(1) => - \ahbmo_0.htrans[1]\, htrans_2(1) => \ahbmo_3.htrans[1]\, - htrans_1(1) => \ahbmo_1.htrans[1]\, htrans_0_0 => - \ahbmo_3.htrans[0]\, bco_msb_1(1) => \ahb0.bco_msb_1[1]\, - hresp_0(0) => \ahbmi.hresp[0]\, nhmaster_1_i(0) => - \ahb0.comb.nhmaster_1_i[0]\, hgrant_3 => - \ahbmi.hgrant[3]\, hgrant_1 => \ahbmi.hgrant[1]\, - hgrant_0 => \ahbmi.hgrant[0]\, hsize_5(1) => - \l3.cpu.0.u0.p0.c0mmu.a0.hsize_5[1]\, hmbsel_1(0) => - \ahbsi.hmbsel_1[0]\, hburst_0(2) => \ahbmo_3.hburst[2]\, - hburst_0(1) => \ahbmo_3.hburst[1]\, hburst_0(0) => - \ahbmo_3.hburst[0]\, hsize_0(1) => \ahbmo_3.hsize[1]\, - hsize_0(0) => \ahbmo_3.hsize[0]\, hsize(1) => - \ahbsi.hsize[1]\, hsize(0) => \ahbsi.hsize[0]\, haddr_3_4 - => \ahbmo_0.haddr[6]\, haddr_3_5 => \ahbmo_0.haddr[7]\, - haddr_3_0 => \ahbmo_3.haddr[2]\, haddr_3_3 => - \ahbmo_0.haddr[5]\, haddr_3_8 => \ahbmo_3.haddr[10]\, - haddr_3_6 => \ahbmo_0.haddr[8]\, haddr_3_1 => - \ahbmo_0.haddr[3]\, haddr_3_7 => \ahbmo_0.haddr[9]\, - hwdata_m_0_3 => \ahbsi.hwdata_m_0[15]\, hwdata_m_0_0 => - \ahbsi.hwdata_m_0[12]\, hwdata_m_0_2 => - \ahbsi.hwdata_m_0[14]\, hwdata_m_8 => - \ahbsi.hwdata_m[15]\, hwdata_m_13 => \ahbsi.hwdata_m[20]\, - hwdata_m_5 => \ahbsi.hwdata_m[12]\, hwdata_m_0_d0 => - \ahbsi.hwdata_m[7]\, hwdata_m_7 => \ahbsi.hwdata_m[14]\, - hwdata_2_15 => \ahbsi.hwdata[18]\, hwdata_2_0 => - \ahbmo_0.hwdata[3]\, hwdata_2_9 => \ahbmo_3.hwdata[12]\, - hwdata_2_3 => \ahbmo_3.hwdata[6]\, hwdata_2_14 => - \ahbsi.hwdata[17]\, hwdata_2_1 => \ahbmo_0.hwdata[4]\, - hwdata_2_28 => \ahbmo_3.hwdata[31]\, hwdata_2_27 => - \ahbmo_3.hwdata[30]\, hwdata_2_25 => \ahbmo_3.hwdata[28]\, - hwdata_2_23 => \ahbmo_3.hwdata[26]\, hwdata_2_13 => - \ahbmo_3.hwdata[16]\, hwdata_2_12 => \ahbmo_3.hwdata[15]\, - hwdata_2_11 => \ahbmo_3.hwdata[14]\, hwdata_2_4 => - \ahbmo_3.hwdata[7]\, hwdata_2_16 => \ahbmo_3.hwdata[19]\, - hwdata_1(31) => \ahbmo_1.hwdata[31]\, hwdata_1(30) => - \ahbmo_1.hwdata[30]\, hwdata_1(29) => - \ahbmo_3.hwdata[29]\, hwdata_1(28) => - \ahbmo_1.hwdata[28]\, hwdata_1(27) => - \ahbmo_3.hwdata[27]\, hwdata_1(26) => - \ahbmo_1.hwdata[26]\, hwdata_1(25) => - \ahbmo_3.hwdata[25]\, hwdata_1(24) => - \ahbmo_3.hwdata[24]\, hwdata_1(23) => \ahbsi.hwdata[23]\, - hwdata_1(22) => \ahbsi.hwdata[22]\, hwdata_1(21) => - \ahbsi.hwdata[21]\, hwdata_1(20) => \ahbmo_3.hwdata[20]\, - hwdata_1(19) => \ahbmo_1.hwdata[19]\, hwdata_1(18) => - \ahbmo_0.hwdata[18]\, hwdata_1(17) => - \ahbmo_0.hwdata[17]\, hwdata_1(16) => - \ahbmo_1.hwdata[16]\, hwdata_1(15) => - \ahbmo_1.hwdata[15]\, hwdata_1(14) => - \ahbmo_1.hwdata[14]\, hwdata_1(13) => \ahbsi.hwdata[13]\, - hwdata_1(12) => \ahbmo_1.hwdata[12]\, hwdata_1(11) => - \ahbsi.hwdata[11]\, hwdata_1(10) => \ahbmo_3.hwdata[10]\, - hwdata_1(9) => \ahbsi.hwdata[9]\, hwdata_1(8) => - \ahbmo_3.hwdata[8]\, hwdata_1(7) => \ahbmo_1.hwdata[7]\, - hwdata_1(6) => \ahbmo_1.hwdata[6]\, hwdata_1(5) => - \ahbmo_3.hwdata[5]\, hwdata_1(4) => \ahbsi.hwdata[4]\, - hwdata_1(3) => \ahbsi.hwdata[3]\, hwdata_1(2) => - \ahbmo_3.hwdata[2]\, hwdata_1(1) => \ahbsi.hwdata[1]\, - hwdata_1(0) => \ahbmo_3.hwdata[0]\, hwdata_0(31) => - \ahbmo_0.hwdata[31]\, hwdata_0(30) => - \ahbmo_0.hwdata[30]\, hwdata_0(29) => - \ahbmo_1.hwdata[29]\, hwdata_0(28) => - \ahbmo_0.hwdata[28]\, hwdata_0(27) => - \ahbmo_1.hwdata[27]\, hwdata_0(26) => - \ahbmo_0.hwdata[26]\, hwdata_0(25) => - \ahbmo_1.hwdata[25]\, hwdata_0(24) => - \ahbmo_1.hwdata[24]\, hwdata_0(23) => - \ahbmo_3.hwdata[23]\, hwdata_0(22) => - \ahbmo_3.hwdata[22]\, hwdata_0(21) => - \ahbmo_3.hwdata[21]\, hwdata_0(20) => - \ahbmo_1.hwdata[20]\, hwdata_0(19) => - \ahbmo_0.hwdata[19]\, hwdata_0(18) => - \ahbmo_3.hwdata[18]\, hwdata_0(17) => - \ahbmo_3.hwdata[17]\, hwdata_0(16) => - \ahbmo_0.hwdata[16]\, hwdata_0(15) => - \ahbmo_0.hwdata[15]\, hwdata_0(14) => - \ahbmo_0.hwdata[14]\, hwdata_0(13) => - \ahbmo_3.hwdata[13]\, hwdata_0(12) => - \ahbmo_0.hwdata[12]\, hwdata_0(11) => - \ahbmo_3.hwdata[11]\, hwdata_0(10) => - \ahbmo_1.hwdata[10]\, hwdata_0(9) => \ahbmo_3.hwdata[9]\, - hwdata_0(8) => \ahbmo_1.hwdata[8]\, hwdata_0(7) => - \ahbmo_0.hwdata[7]\, hwdata_0(6) => \ahbmo_0.hwdata[6]\, - hwdata_0(5) => \ahbmo_1.hwdata[5]\, hwdata_0(4) => - \ahbmo_3.hwdata[4]\, hwdata_0(3) => \ahbmo_3.hwdata[3]\, - hwdata_0(2) => \ahbmo_1.hwdata[2]\, hwdata_0(1) => - \ahbmo_3.hwdata[1]\, hwdata_0(0) => \ahbmo_1.hwdata[0]\, - hwdata(31) => \ahbsi.hwdata[31]\, hwdata(30) => - \ahbsi.hwdata[30]\, hwdata(29) => \ahbsi.hwdata[29]\, - hwdata(28) => \ahbsi.hwdata[28]\, hwdata(27) => - \ahbsi.hwdata[27]\, hwdata(26) => \ahbsi.hwdata[26]\, - hwdata(25) => \ahbsi.hwdata[25]\, hwdata(24) => - \ahbsi.hwdata[24]\, hwdata(23) => \ahbmo_1.hwdata[23]\, - hwdata(22) => \ahbmo_1.hwdata[22]\, hwdata(21) => - \ahbmo_1.hwdata[21]\, hwdata(20) => \ahbsi.hwdata[20]\, - hwdata(19) => \ahbsi.hwdata[19]\, hwdata(18) => - \ahbmo_1.hwdata[18]\, hwdata(17) => \ahbmo_1.hwdata[17]\, - hwdata(16) => \ahbsi.hwdata[16]\, hwdata(15) => - \ahbsi.hwdata[15]\, hwdata(14) => \ahbsi.hwdata[14]\, - hwdata(13) => \ahbmo_1.hwdata[13]\, hwdata(12) => - \ahbsi.hwdata[12]\, hwdata(11) => \ahbmo_1.hwdata[11]\, - hwdata(10) => \ahbsi.hwdata[10]\, hwdata(9) => - \ahbmo_1.hwdata[9]\, hwdata(8) => \ahbsi.hwdata[8]\, - hwdata(7) => \ahbsi.hwdata[7]\, hwdata(6) => - \ahbsi.hwdata[6]\, hwdata(5) => \ahbsi.hwdata[5]\, - hwdata(4) => \ahbmo_1.hwdata[4]\, hwdata(3) => - \ahbmo_1.hwdata[3]\, hwdata(2) => \ahbsi.hwdata[2]\, - hwdata(1) => \ahbmo_1.hwdata[1]\, hwdata(0) => - \ahbsi.hwdata[0]\, haddr_2(30) => \ahbmo_3.haddr[30]\, - haddr_2(29) => \ahbmo_3.haddr[29]\, haddr_2(28) => - \ahbmo_0.haddr[28]\, haddr_2(27) => \ahbmo_3.haddr[27]\, - haddr_2(26) => \ahbmo_0.haddr[26]\, haddr_2(25) => - \ahbmo_3.haddr[25]\, haddr_2(24) => \ahbmo_3.haddr[24]\, - haddr_2(23) => \ahbmo_0.haddr[23]\, haddr_2(22) => - \ahbmo_3.haddr[22]\, haddr_2(21) => \ahbmo_3.haddr[21]\, - haddr_2(20) => \ahbmo_0.haddr[20]\, haddr_2(19) => - \ahbmo_0.haddr[19]\, haddr_2(18) => \ahbmo_0.haddr[18]\, - haddr_2(17) => \ahbmo_0.haddr[17]\, haddr_2(16) => - \ahbmo_0.haddr[16]\, haddr_2(15) => \ahbmo_0.haddr[15]\, - haddr_2(14) => \ahbmo_0.haddr[14]\, haddr_2(13) => - \ahbmo_0.haddr[13]\, haddr_2(12) => \ahbmo_3.haddr[12]\, - haddr_2(11) => \ahbmo_3.haddr[11]\, haddr_2(10) => - \ahbmo_1.haddr[10]\, haddr_2(9) => \ahbsi.haddr[9]\, - haddr_2(8) => \ahbsi.haddr[8]\, haddr_2(7) => - \ahbsi.haddr[7]\, haddr_2(6) => \ahbsi.haddr[6]\, - haddr_2(5) => \ahbsi.haddr[5]\, haddr_2(4) => - \ahbmo_0.haddr[4]\, haddr_2(3) => \ahbsi.haddr[3]\, - haddr_2(2) => \ahbmo_1.haddr[2]\, haddr_1(31) => - \ahbmo_3.haddr[31]\, haddr_1(30) => \ahbmo_1.haddr[30]\, - haddr_1(29) => \ahbmo_1.haddr[29]\, haddr_1(28) => - \ahbmo_3.haddr[28]\, haddr_1(27) => \ahbmo_1.haddr[27]\, - haddr_1(26) => \ahbmo_3.haddr[26]\, haddr_1(25) => - \ahbmo_1.haddr[25]\, haddr_1(24) => \ahbmo_1.haddr[24]\, - haddr_1(23) => \ahbmo_3.haddr[23]\, haddr_1(22) => - \ahbmo_1.haddr[22]\, haddr_1(21) => \ahbmo_1.haddr[21]\, - haddr_1(20) => \ahbmo_3.haddr[20]\, haddr_1(19) => - \ahbmo_3.haddr[19]\, haddr_1(18) => \ahbmo_3.haddr[18]\, - haddr_1(17) => \ahbmo_3.haddr[17]\, haddr_1(16) => - \ahbmo_3.haddr[16]\, haddr_1(15) => \ahbmo_3.haddr[15]\, - haddr_1(14) => \ahbmo_3.haddr[14]\, haddr_1(13) => - \ahbmo_3.haddr[13]\, haddr_1(12) => \ahbmo_1.haddr[12]\, - haddr_1(11) => \ahbmo_1.haddr[11]\, haddr_1(10) => - \ahbmo_0.haddr[10]\, haddr_1(9) => \ahbmo_3.haddr[9]\, - haddr_1(8) => \ahbmo_3.haddr[8]\, haddr_1(7) => - \ahbmo_3.haddr[7]\, haddr_1(6) => \ahbmo_3.haddr[6]\, - haddr_1(5) => \ahbmo_3.haddr[5]\, haddr_1(4) => - \ahbsi.haddr[4]\, haddr_1(3) => \ahbmo_3.haddr[3]\, - haddr_1(2) => \ahbsi.haddr[2]\, haddr_1(1) => - \ahbmo_3.haddr[1]\, haddr_1(0) => \ahbsi.haddr[0]\, - haddr_0(31) => \ahbmo_1.haddr[31]\, haddr_0(30) => - \ahbmo_0.haddr[30]\, haddr_0(29) => \ahbmo_0.haddr[29]\, - haddr_0(28) => \ahbmo_1.haddr[28]\, haddr_0(27) => - \ahbmo_0.haddr[27]\, haddr_0(26) => \ahbmo_1.haddr[26]\, - haddr_0(25) => \ahbmo_0.haddr[25]\, haddr_0(24) => - \ahbmo_0.haddr[24]\, haddr_0(23) => \ahbmo_1.haddr[23]\, - haddr_0(22) => \ahbmo_0.haddr[22]\, haddr_0(21) => - \ahbmo_0.haddr[21]\, haddr_0(20) => \ahbmo_1.haddr[20]\, - haddr_0(19) => \ahbmo_1.haddr[19]\, haddr_0(18) => - \ahbmo_1.haddr[18]\, haddr_0(17) => \ahbmo_1.haddr[17]\, - haddr_0(16) => \ahbmo_1.haddr[16]\, haddr_0(15) => - \ahbmo_1.haddr[15]\, haddr_0(14) => \ahbmo_1.haddr[14]\, - haddr_0(13) => \ahbmo_1.haddr[13]\, haddr_0(12) => - \ahbmo_0.haddr[12]\, haddr_0(11) => \ahbmo_0.haddr[11]\, - haddr_0(10) => \ahbsi.haddr[10]\, haddr_0(9) => - \ahbmo_1.haddr[9]\, haddr_0(8) => \ahbmo_1.haddr[8]\, - haddr_0(7) => \ahbmo_1.haddr[7]\, haddr_0(6) => - \ahbmo_1.haddr[6]\, haddr_0(5) => \ahbmo_1.haddr[5]\, - haddr_0(4) => \ahbmo_3.haddr[4]\, haddr_0(3) => - \ahbmo_1.haddr[3]\, haddr_0(2) => \ahbmo_0.haddr[2]\, - haddr_0(1) => \ahbmo_1.haddr[1]\, haddr_0(0) => - \ahbmo_3.haddr[0]\, hrdata_4_15 => \ahbso_1.hrdata[15]\, - hrdata_4_13 => \ahbso_1.hrdata[13]\, hrdata_4_11 => - \ahbso_1.hrdata[11]\, hrdata_4_27 => \ahbso_1.hrdata[27]\, - hrdata_4_26 => \ahbso_1.hrdata[26]\, hrdata_4_4 => - \ahbso_0.hrdata[4]\, hrdata_4_21 => \ahbso_1.hrdata[21]\, - hrdata_4_1 => \ahbso_0.hrdata[1]\, hrdata_4_22 => - \ahbso_0.hrdata[22]\, hrdata_4_23 => \ahbso_1.hrdata[23]\, - hrdata_4_0 => \ahbso_1.hrdata[0]\, hrdata_4_14 => - \ahbso_7.hrdata[14]\, hrdata_4_3 => \ahbso_7.hrdata[3]\, - hrdata_4_2 => \ahbso_7.hrdata[2]\, hrdata_4_9 => - \ahbso_1.hrdata[9]\, hrdata_4_12 => \ahbso_1.hrdata[12]\, - hrdata_4_10 => \ahbso_1.hrdata[10]\, hrdata_4_7 => - \ahbso_1.hrdata[7]\, hrdata_4_8 => \ahbso_0.hrdata[8]\, - hrdata_4_16 => \ahbso_0.hrdata[16]\, hrdata_4_18 => - \ahbso_1.hrdata[18]\, hrdata_4_17 => \ahbso_7.hrdata[17]\, - hrdata_3_15 => \ahbso_0.hrdata[15]\, hrdata_3_13 => - \ahbso_0.hrdata[13]\, hrdata_3_11 => \ahbso_0.hrdata[11]\, - hrdata_3_28 => \ahbso_1.hrdata[28]\, hrdata_3_27 => - \ahbso_0.hrdata[27]\, hrdata_3_26 => \ahbso_0.hrdata[26]\, - hrdata_3_4 => \ahbso_1.hrdata[4]\, hrdata_3_1 => - \ahbso_1.hrdata[1]\, hrdata_3_22 => \ahbso_1.hrdata[22]\, - hrdata_3_23 => \ahbso_0.hrdata[23]\, hrdata_3_0 => - \ahbso_0.hrdata[0]\, hrdata_3_24 => \ahbso_7.hrdata[24]\, - hrdata_3_21 => \ahbso_7.hrdata[21]\, hrdata_3_14 => - \ahbso_6.hrdata[14]\, hrdata_3_3 => \ahbso_6.hrdata[3]\, - hrdata_3_2 => \ahbso_6.hrdata[2]\, hrdata_3_9 => - \ahbso_0.hrdata[9]\, hrdata_3_12 => \ahbso_0.hrdata[12]\, - hrdata_3_10 => \ahbso_0.hrdata[10]\, hrdata_3_7 => - \ahbso_0.hrdata[7]\, hrdata_3_6 => \ahbso_0.hrdata[6]\, - hrdata_3_8 => \ahbso_1.hrdata[8]\, hrdata_3_29 => - \ahbso_0.hrdata[29]\, hrdata_3_16 => \ahbso_1.hrdata[16]\, - hrdata_3_5 => \ahbso_0.hrdata[5]\, hrdata_3_30 => - \ahbso_7.hrdata[30]\, hrdata_3_18 => \ahbso_7.hrdata[18]\, - hrdata_3_17 => \ahbso_6.hrdata[17]\, hrdata_2_28 => - \ahbso_0.hrdata[28]\, hrdata_2_25 => \ahbso_1.hrdata[25]\, - hrdata_2_15 => \ahbmi.hrdata[15]\, hrdata_2_11 => - \ahbmi.hrdata[11]\, hrdata_2_27 => \ahbmi.hrdata[27]\, - hrdata_2_26 => \ahbmi.hrdata[26]\, hrdata_2_23 => - \ahbso_7.hrdata[23]\, hrdata_2_22 => \ahbso_7.hrdata[22]\, - hrdata_2_21 => \ahbso_6.hrdata[21]\, hrdata_2_13 => - \ahbso_7.hrdata[13]\, hrdata_2_4 => \ahbso_7.hrdata[4]\, - hrdata_2_1 => \ahbso_7.hrdata[1]\, hrdata_2_0 => - \ahbso_7.hrdata[0]\, hrdata_2_24 => \ahbso_1.hrdata[24]\, - hrdata_2_14 => \ahbso_1.hrdata[14]\, hrdata_2_3 => - \ahbso_1.hrdata[3]\, hrdata_2_2 => \ahbso_1.hrdata[2]\, - hrdata_2_31 => \ahbso_1.hrdata[31]\, hrdata_2_9 => - \ahbmi.hrdata[9]\, hrdata_2_19 => \ahbso_1.hrdata[19]\, - hrdata_2_10 => \ahbmi.hrdata[10]\, hrdata_2_7 => - \ahbmi.hrdata[7]\, hrdata_2_6 => \ahbso_1.hrdata[6]\, - hrdata_2_29 => \ahbso_1.hrdata[29]\, hrdata_2_5 => - \ahbso_1.hrdata[5]\, hrdata_2_30 => \ahbso_6.hrdata[30]\, - hrdata_2_18 => \ahbso_6.hrdata[18]\, hrdata_2_16 => - \ahbso_7.hrdata[16]\, hrdata_2_12 => \ahbso_7.hrdata[12]\, - hrdata_2_8 => \ahbso_7.hrdata[8]\, hrdata_2_17 => - \ahbso_1.hrdata[17]\, bco_msb_1_m(1) => - \ahb0.bco_msb_1_m[1]\, hmaster_0_0_RNIFCVH1_0(1) => - \r.hmaster_0_0_RNIFCVH1_0[1]\, l1_0_m(1) => - \ahb0.l1_0_m[1]\, nhmaster_1_iv_0(1) => - \ahb0.comb.nhmaster_1_iv_0[1]\, hresp(0) => - \ahbso_0.hresp[0]\, htrans(1) => \ahbsi.htrans[1]\, - htrans(0) => \ahbsi.htrans[0]\, hrdata_1(31) => - \ahbso_0.hrdata[31]\, hrdata_1(30) => - \ahbso_1.hrdata[30]\, hrdata_1(29) => - \ahbso_7.hrdata[29]\, hrdata_1(28) => - \ahbso_7.hrdata[28]\, hrdata_1(27) => - \ahbso_7.hrdata[27]\, hrdata_1(26) => - \ahbso_7.hrdata[26]\, hrdata_1(25) => - \ahbso_0.hrdata[25]\, hrdata_1(24) => - \ahbso_0.hrdata[24]\, hrdata_1(23) => - \ahbso_6.hrdata[23]\, hrdata_1(22) => - \ahbso_6.hrdata[22]\, hrdata_1(21) => \ahbmi.hrdata[21]\, - hrdata_1(20) => \ahbso_7.hrdata[20]\, hrdata_1(19) => - \ahbso_0.hrdata[19]\, hrdata_1(18) => \ahbmi.hrdata[18]\, - hrdata_1(17) => \ahbso_0.hrdata[17]\, hrdata_1(16) => - \ahbso_6.hrdata[16]\, hrdata_1(15) => - \ahbso_7.hrdata[15]\, hrdata_1(14) => - \ahbso_0.hrdata[14]\, hrdata_1(13) => - \ahbso_6.hrdata[13]\, hrdata_1(12) => - \ahbso_6.hrdata[12]\, hrdata_1(11) => - \ahbso_7.hrdata[11]\, hrdata_1(10) => - \ahbso_7.hrdata[10]\, hrdata_1(9) => \ahbso_7.hrdata[9]\, - hrdata_1(8) => \ahbso_6.hrdata[8]\, hrdata_1(7) => - \ahbso_7.hrdata[7]\, hrdata_1(6) => \ahbso_7.hrdata[6]\, - hrdata_1(5) => \ahbso_7.hrdata[5]\, hrdata_1(4) => - \ahbso_6.hrdata[4]\, hrdata_1(3) => \ahbso_0.hrdata[3]\, - hrdata_1(2) => \ahbso_0.hrdata[2]\, hrdata_1(1) => - \ahbso_6.hrdata[1]\, hrdata_1(0) => \ahbso_6.hrdata[0]\, - data_0_5 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[13]\, - data_0_21 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[29]\, - data_0_16 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[24]\, - data_0_2 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[10]\, - data_0_0 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[8]\, data_8 - => \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[13]\, data_24 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[29]\, data_0_d0 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[5]\, data_19 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[24]\, data_5 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[10]\, data_3 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[8]\, hrdata(31) => - \ahbso_7.hrdata[31]\, hrdata(30) => \ahbmi.hrdata[30]\, - hrdata(29) => \ahbmi.hrdata[29]\, hrdata(28) => - \ahbmi.hrdata[28]\, hrdata(27) => \ahbso_6.hrdata[27]\, - hrdata(26) => \ahbso_6.hrdata[26]\, hrdata(25) => - \ahbso_6.hrdata[25]\, hrdata(24) => \ahbmi.hrdata[24]\, - hrdata(23) => \ahbmi.hrdata[23]\, hrdata(22) => - \ahbmi.hrdata[22]\, hrdata(21) => \ahbso_0.hrdata[21]\, - hrdata(20) => \ahbso_0.hrdata[20]\, hrdata(19) => - \ahbso_6.hrdata[19]\, hrdata(18) => \ahbso_0.hrdata[18]\, - hrdata(17) => \ahbmi.hrdata[17]\, hrdata(16) => - \ahbmi.hrdata[16]\, hrdata(15) => \ahbso_6.hrdata[15]\, - hrdata(14) => \ahbmi.hrdata[14]\, hrdata(13) => - \ahbmi.hrdata[13]\, hrdata(12) => \ahbmi.hrdata[12]\, - hrdata(11) => \ahbso_6.hrdata[11]\, hrdata(10) => - \ahbso_6.hrdata[10]\, hrdata(9) => \ahbso_6.hrdata[9]\, - hrdata(8) => \ahbmi.hrdata[8]\, hrdata(7) => - \ahbso_6.hrdata[7]\, hrdata(6) => \ahbmi.hrdata[6]\, - hrdata(5) => \ahbmi.hrdata[5]\, hrdata(4) => - \ahbmi.hrdata[4]\, hrdata(3) => \ahbmi.hrdata[3]\, - hrdata(2) => \ahbmi.hrdata[2]\, hrdata(1) => - \ahbmi.hrdata[1]\, hrdata(0) => \ahbmi.hrdata[0]\, - size(0) => \l3.cpu.0.u0.p0.c0mmu.mcdi.size[0]\, - nbo_5_0(1) => \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[1]\, - nbo_5_0(0) => \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[0]\, - address(1) => \l3.cpu.0.u0.p0.c0mmu.mcdi.address[1]\, - address(0) => \l3.cpu.0.u0.p0.c0mmu.mcdi.address[0]\, - htrans_tz(1) => \ahbmo_0.htrans_tz[1]\, haddr_1_d0 => - \ahbsi.haddr[1]\, haddr_11 => \ahbsi.haddr[11]\, haddr_31 - => \ahbmo_0.haddr[31]\, haddr_0_d0 => \ahbmo_1.haddr[0]\, - haddr_4 => \ahbmo_1.haddr[4]\, haddr_15 => - \ahbsi.haddr[15]\, haddr_14 => \ahbsi.haddr[14]\, - haddr_19 => \ahbsi.haddr[19]\, haddr_18 => - \ahbsi.haddr[18]\, haddr_21 => \ahbsi.haddr[21]\, - haddr_20 => \ahbsi.haddr[20]\, haddr_23 => - \ahbsi.haddr[23]\, haddr_22 => \ahbsi.haddr[22]\, - haddr_27 => \ahbsi.haddr[27]\, haddr_26 => - \ahbsi.haddr[26]\, haddr_29 => \ahbsi.haddr[29]\, - haddr_28 => \ahbsi.haddr[28]\, haddr_12 => - \ahbsi.haddr[12]\, haddr_13 => \ahbsi.haddr[13]\, - haddr_16 => \ahbsi.haddr[16]\, haddr_17 => - \ahbsi.haddr[17]\, haddr_24 => \ahbsi.haddr[24]\, - haddr_25 => \ahbsi.haddr[25]\, haddr_30 => - \ahbsi.haddr[30]\, hburst(2) => \ahbsi.hburst[2]\, - hburst(1) => \ahbsi.hburst[1]\, hburst(0) => - \ahbsi.hburst[0]\, hsel_i(0) => \ahbsi.hsel_i[0]\, - hrdata_1_0_1_0 => \ahb0.hrdata_1_0_1[1]\, hrdata_0(31) - => \ahbmi.hrdata[31]\, hrdata_0(30) => - \ahbso_0.hrdata[30]\, hrdata_0(29) => - \ahbso_6.hrdata[29]\, hrdata_0(28) => - \ahbso_6.hrdata[28]\, hrdata_0(27) => - \ahbmi.hrdata_0[27]\, hrdata_0(26) => - \ahbmi.hrdata_0[26]\, hrdata_0(25) => - \ahbso_7.hrdata[25]\, hrdata_0(24) => - \ahbmi.hrdata_0[24]\, hrdata_0(23) => - \ahbmi.hrdata_0[23]\, hrdata_0(22) => - \ahbmi.hrdata_0[22]\, hrdata_0(21) => - \ahbmi.hrdata_0[21]\, hrdata_0(20) => - \ahbso_1.hrdata[20]\, hrdata_0(19) => - \ahbso_7.hrdata[19]\, hrdata_0(18) => - \ahbmi.hrdata_0[18]\, hrdata_0(17) => - \ahbmi.hrdata_0[17]\, hrdata_0(16) => - \ahbmi.hrdata_0[16]\, hrdata_0(15) => - \ahbmi.hrdata_0[15]\, hrdata_0(14) => - \ahbmi.hrdata_0[14]\, hrdata_0(13) => - \ahbmi.hrdata_0[13]\, hrdata_0(12) => - \ahbmi.hrdata_0[12]\, hrdata_0(11) => - \ahbmi.hrdata_0[11]\, hrdata_0(10) => - \ahbmi.hrdata_0[10]\, hrdata_0(9) => \ahbmi.hrdata_0[9]\, - hrdata_0(8) => \ahbmi.hrdata_0[8]\, hrdata_0(7) => - \ahbmi.hrdata_0[7]\, hrdata_0(6) => \ahbso_6.hrdata[6]\, - hrdata_0(5) => \ahbso_6.hrdata[5]\, hrdata_0(4) => - \ahbmi.hrdata_0[4]\, hrdata_0(3) => \ahbmi.hrdata_0[3]\, - hrdata_0(2) => \ahbmi.hrdata_0[2]\, hrdata_0(1) => - \ahbmi.hrdata_0[1]\, hrdata_0(0) => \ahbmi.hrdata_0[0]\, - iosn_0(93) => \sr1.iosn_0[93]\, iosn_1_8 => - \sr1.iosn_1[101]\, iosn_1_0 => \sr1.iosn_1[93]\, - iosn_2(93) => \sr1.iosn_2[93]\, iosn_8 => \sr1.iosn[101]\, - iosn_7 => \sr1.iosn[100]\, iosn_0_d0 => \sr1.iosn[93]\, - hmaster_0_1 => \ahbsi.hmaster_0[1]\, N_5054 => N_5054, - htrans_0_sqmuxa_2 => - \l3.cpu.0.u0.p0.c0mmu.a0.htrans_0_sqmuxa_2\, - lb_0_sqmuxa_1 => - \l3.cpu.0.u0.p0.c0mmu.a0.v.lb_0_sqmuxa_1\, N_466 => N_466, - N_95_i_0 => \lpp_bootloader_1.ahbrom_1.N_95_i_0\, - bo_5842_d => \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d\, rstn - => rstn, hbusreq_i_3_0 => \ahbmo_3.hbusreq_i_3\, - N_90_i_0 => \lpp_bootloader_1.ahbrom_1.N_90_i_0\, N_262 - => N_262, hwrite_1_m_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.hwrite_1_m_0\, werr_2_m_0 - => \l3.cpu.0.u0.p0.c0mmu.a0.comb.v.werr_2_m_0\, hwrite_1 - => \ahbmo_3.hwrite\, hwrite_0 => \ahbmo_1.hwrite\, N_458 - => N_458, N_459 => N_459, N_468 => N_468, N_463 => N_463, - N_461 => N_461, N_510 => N_510, N_138 => N_138, N_139 => - N_139, N_6377 => N_6377, N_103_i_0 => - \lpp_bootloader_1.ahbrom_1.N_103_i_0\, brmw_i => - \sr1.ctrl.un1_r.brmw_i\, N_6550 => N_6550, N_264 => N_264, - N_467 => N_467, N_457 => N_457, N_462 => N_462, - un1_nhmaster_0_sqmuxa_1 => \ahb0.un1_nhmaster_0_sqmuxa_1\, - un1_htrans_1_sqmuxa_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.un1_htrans_1_sqmuxa_0\, un60_nbo - => \l3.cpu.0.u0.p0.c0mmu.a0.comb.un60_nbo\, arb_1 => - \ahb0.comb.arb_1\, hbusreq => \ahbmo_0.hbusreq\, hlock - => \ahbmo_0.hlock\, hready_1 => \ahbso_7.hready\, - hready_0 => \ahbso_0.hready\, N_78 => N_78, un315_ioen_NE - => \ahb0.comb.7.4.un315_ioen_NE\, un51_ioen_NE => - \ahb0.comb.1.4.un51_ioen_NE\, un59_nbo => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un59_nbo\, un91_nbo_i_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un91_nbo_i_0\, hready => - \ahbso_1.hready\, bo_5842_d_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d_0\, un6_ioen_NE_0 - => \ahb0.comb.0.4.un6_ioen_NE_0\, brmw_1 => - \sr1.ctrl.brmw_1\, hwrite => \ahbsi.hwrite\, hwrite_m_0_0 - => \ahbsi.hwrite_m_0_0\, hbusreq_i_3 => - \ahbmo_1.hbusreq_i_3\, IdlePhase => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.IdlePhase\, - un1_dmain_6 => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.un1_dmain_6\, - Lock_RNIU86D => \DMAIn.Lock_RNIU86D\, N_546 => N_546, - N_264_0 => N_264_0, N_262_0 => N_262_0, N_78_0 => N_78_0, - lclk_c => lclk_c); - - \data_pad[19]\ : BIBUF - port map(PAD => data(19), D => \memo.data[19]\, E => - \memo.bdrive_i[1]\, Y => \data_in[19]\); - - clk_pad : INBUF - port map(PAD => clk, Y => clk_c); - - \pci_arb_gnt_pad[3]\ : OUTBUF - port map(D => \GND\, PAD => pci_arb_gnt(3)); - - \data_pad[23]\ : BIBUF - port map(PAD => data(23), D => \memo.data[23]\, E => - \memo.bdrive_i[1]\, Y => \data_in[23]\); - - \ramsn_pad[1]\ : OUTBUF - port map(D => \ramsn_c[1]\, PAD => ramsn(1)); - - \address_pad[20]\ : OUTBUF - port map(D => \address_c[20]\, PAD => address(20)); - - \data_pad[5]\ : BIBUF - port map(PAD => data(5), D => \memo.data[5]\, E => - \memo.bdrive_i[3]\, Y => \data_in[5]\); - - lfrtimemanagement_0 : apb_lfr_time_management - port map(coarse_time_i(0) => \coarse_time_i[0]\, pirq(13) - => \apbi.pirq[13]\, pirq(12) => \apbi.pirq[12]\, - pwdata_1_3 => \apbi.pwdata_1[4]\, pwdata_1_2 => - \apbi.pwdata_1[3]\, pwdata_1_0 => \apbi.pwdata_1[1]\, - prdata(31) => \apbo_15.prdata[31]\, prdata(30) => - \apbo_15.prdata[30]\, prdata(29) => \apbo_15.prdata[29]\, - prdata(28) => \apbo_15.prdata[28]\, prdata(27) => - \apbo_15.prdata[27]\, prdata(26) => \apbo_15.prdata[26]\, - prdata(25) => \apbo_15.prdata[25]\, prdata(24) => - \apbo_15.prdata[24]\, prdata(23) => \apbo_15.prdata[23]\, - prdata(22) => \apbo_15.prdata[22]\, prdata(21) => - \apbo_15.prdata[21]\, prdata(20) => \apbo_15.prdata[20]\, - prdata(19) => \apbo_15.prdata[19]\, prdata(18) => - \apbo_15.prdata[18]\, prdata(17) => \apbo_15.prdata[17]\, - prdata(16) => \apbo_15.prdata[16]\, prdata(15) => - \apbo_15.prdata[15]\, prdata(14) => \apbo_15.prdata[14]\, - prdata(13) => \apbo_15.prdata[13]\, prdata(12) => - \apbo_15.prdata[12]\, prdata(11) => \apbo_15.prdata[11]\, - prdata(10) => \apbo_15.prdata[10]\, prdata(9) => - \apbo_15.prdata[9]\, prdata(8) => \apbo_15.prdata[8]\, - prdata(7) => \apbo_15.prdata[7]\, prdata(6) => - \apbo_15.prdata[6]\, prdata(5) => \apbo_15.prdata[5]\, - prdata(4) => \apbo_15.prdata[4]\, prdata(3) => - \apbo_15.prdata[3]\, prdata(2) => \apbo_15.prdata[2]\, - prdata(1) => \apbo_15.prdata[1]\, prdata(0) => - \apbo_15.prdata[0]\, coarse_time_0 => \coarse_time[0]\, - pwdata_10 => \apbi.pwdata[12]\, pwdata_8 => - \apbi.pwdata[10]\, pwdata_7 => \apbi.pwdata[9]\, - pwdata_13 => \apbi.pwdata[15]\, pwdata_12 => - \apbi.pwdata[14]\, pwdata_11 => \apbi.pwdata[13]\, - pwdata_9 => \apbi.pwdata[11]\, pwdata_6 => - \apbi.pwdata[8]\, pwdata_5 => \apbi.pwdata[7]\, pwdata_4 - => \apbi.pwdata[6]\, pwdata_3 => \apbi.pwdata[5]\, - pwdata_0_d0 => \apbi.pwdata[2]\, pwdata_18 => - \apbi.pwdata[20]\, pwdata_29 => \apbi.pwdata[31]\, - pwdata_28 => \apbi.pwdata[30]\, pwdata_27 => - \apbi.pwdata[29]\, pwdata_25 => \apbi.pwdata[27]\, - pwdata_24 => \apbi.pwdata[26]\, pwdata_23 => - \apbi.pwdata[25]\, pwdata_22 => \apbi.pwdata[24]\, - pwdata_21 => \apbi.pwdata[23]\, pwdata_20 => - \apbi.pwdata[22]\, pwdata_19 => \apbi.pwdata[21]\, - pwdata_17 => \apbi.pwdata[19]\, pwdata_26 => - \apbi.pwdata[28]\, pwdata_16 => \apbi.pwdata[18]\, - pwdata_15 => \apbi.pwdata[17]\, pwdata_14 => - \apbi.pwdata[16]\, pwdata_0(15) => \apbi.pwdata_0[15]\, - pwdata_0(14) => \apbi.pwdata_0[14]\, pwdata_0(13) => - \apbi.pwdata_0[13]\, pwdata_0(12) => \apbi.pwdata_0[12]\, - pwdata_0(11) => \apbi.pwdata_0[11]\, pwdata_0(10) => - \apbi.pwdata_0[10]\, pwdata_0(9) => \apbi.pwdata_0[9]\, - pwdata_0(8) => \apbi.pwdata_0[8]\, pwdata_0(7) => - \apbi.pwdata_0[7]\, pwdata_0(6) => \apbi.pwdata_0[6]\, - pwdata_0(5) => \apbi.pwdata_0[5]\, pwdata_0(4) => - \apbi.pwdata_0[4]\, pwdata_0(3) => \apbi.pwdata_0[3]\, - pwdata_0(2) => \apbi.pwdata_0[2]\, pwdata_0(1) => - \apbi.pwdata_0[1]\, pwdata_0(0) => \apbi.pwdata_0[0]\, - paddr(7) => \apbi.paddr[7]\, paddr(6) => \apbi.paddr[6]\, - paddr(5) => \apbi.paddr[5]\, paddr(4) => \apbi.paddr[4]\, - paddr(3) => \apbi.paddr[3]\, psel(15) => \apbi.psel[15]\, - rstn_i => rstn_i, clk49_152MHz_c => clk49_152MHz_c, - clk49_152MHz_c_0 => clk49_152MHz_c_0, un1_apbi_7_1 => - \lfrtimemanagement_0.un1_apbi_7_1\, rdata60 => - \ua1.uart1.uartop.rdata60\, ctrl2 => - \lfrtimemanagement_0.r.ctrl2\, rdata59 => - \ua1.uart1.uartop.rdata59\, N_232_0 => - \ua1.uart1.N_232_0\, un1_apbi_2 => - \gpt.timer0.comb.1.un1_apbi_2\, rdata61_2 => - \ua1.uart1.uartop.rdata61_2\, N_770 => \apb0.N_770\, - rdata62_0 => \ua1.uart1.uartop.rdata62_0\, rdata61 => - \ua1.uart1.uartop.rdata61\, un1_apbi_8 => - \lfrtimemanagement_0.un1_apbi_8\, un1_apbi_7_3 => - \lfrtimemanagement_0.un1_apbi_7_3\, un1_apbi_0 => - \gpt.timer0.comb.un1_apbi_0\, rdata62 => - \ua1.uart1.uartop.rdata62\, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, rdata59_4 => - \ua1.uart1.uartop.rdata59_4\, readdata55_3 => - \gpt.timer0.comb.readdata55_3\, rdata62_3 => - \ua1.uart1.uartop.rdata62_3\, pwrite => \apbi.pwrite\, - rstn => rstn, lclk_c => lclk_c); - - \spw_txd_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => spw_txd(2)); - - \pci_ad_pad[3]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(3)); - - epwrdwn_pad : OUTBUF - port map(D => \GND\, PAD => epwrdwn); - - \pci_ad_pad[25]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(25)); - - \ramoen_pad[4]\ : OUTBUF - port map(D => \VCC\, PAD => ramoen(4)); - - \gpio_pad[3]\ : BIBUF - port map(PAD => gpio(3), D => \gpioo.dout[3]\, E => - \gpioo.oen_i[3]\, Y => \gpio_in[3]\); - - GND_i_0 : GND - port map(Y => GND_0); - - pci_stop_pad : OUTBUF - port map(D => \GND\, PAD => pci_stop); - - \gpio_pad[2]\ : BIBUF - port map(PAD => gpio(2), D => \gpioo.dout[2]\, E => - \gpioo.oen_i[2]\, Y => \gpio_in[2]\); - - \address_pad[25]\ : OUTBUF - port map(D => \address_c[25]\, PAD => address(25)); - - pci_req_pad : OUTBUF - port map(D => \GND\, PAD => pci_req); - - ramclk_pad : OUTBUF - port map(D => lclk_c, PAD => ramclk); - - \pci_ad_pad[13]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(13)); - - \spw_txsn_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => spw_txsn(2)); - - \spw_txdn_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => spw_txdn(2)); - - \pci_cbe_pad[3]\ : OUTBUF - port map(D => \GND\, PAD => pci_cbe(3)); - - nBWE_pad : OUTBUF - port map(D => nBWE_c, PAD => nBWE); - - \pci_ad_pad[24]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(24)); - - \pci_ad_pad[29]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(29)); - - pci_rst_pad : OUTBUF - port map(D => \GND\, PAD => pci_rst); - - \data_pad[17]\ : BIBUF - port map(PAD => data(17), D => \memo.data[17]\, E => - \memo.bdrive_i[1]\, Y => \data_in[17]\); - - \address_pad[10]\ : OUTBUF - port map(D => \address_c[10]\, PAD => address(10)); - - rxd1_pad : INBUF - port map(PAD => rxd1, Y => rxd1_c); - - \data_pad[4]\ : BIBUF - port map(PAD => data(4), D => \memo.data[4]\, E => - \memo.bdrive_i[3]\, Y => \data_in[4]\); - - clk49_152MHz_pad_RNIB5E4 : BUFF - port map(A => clk49_152MHz_c, Y => clk49_152MHz_c_0); - - \pci_ad_pad[21]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(21)); - - nADSC_pad : OUTBUF - port map(D => \VCC\, PAD => nADSC); - - tdo_pad : OUTBUF - port map(D => \GND\, PAD => tdo); - - \pci_arb_gnt_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => pci_arb_gnt(2)); - - \data_pad[3]\ : BIBUF - port map(PAD => data(3), D => \memo.data[3]\, E => - \memo.bdrive_i[3]\, Y => \data_in[3]\); - - \address_pad[7]\ : OUTBUF - port map(D => \address_c[7]\, PAD => address(7)); - - \address_pad[15]\ : OUTBUF - port map(D => \address_c[15]\, PAD => address(15)); - - \spw_txs_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => spw_txs(1)); - - \data_pad[6]\ : BIBUF - port map(PAD => data(6), D => \memo.data[6]\, E => - \memo.bdrive_i[3]\, Y => \data_in[6]\); - - \pci_arb_gnt_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => pci_arb_gnt(0)); - - rst0 : rstgen - port map(rstgen_VCC => \VCC\, rstraw_c => rstraw_c, lclk_c - => lclk_c, m26_m1_e => m26_m1_e, rstoutl_RNIGJKSJO => - rstoutl_RNIGJKSJO, rstn_i => rstn_i, rstn => rstn); - - \data_pad[26]\ : BIBUF - port map(PAD => data(26), D => \memo.data[26]\, E => - \memo.bdrive_i[0]\, Y => \data_in[26]\); - - dsutx_pad : OUTBUF - port map(D => dsutx_c, PAD => dsutx); - - sr1 : mctrl - port map(data_in(31) => \data_in[31]\, data_in(30) => - \data_in[30]\, data_in(29) => \data_in[29]\, data_in(28) - => \data_in[28]\, data_in(27) => \data_in[27]\, - data_in(26) => \data_in[26]\, data_in(25) => - \data_in[25]\, data_in(24) => \data_in[24]\, data_in(23) - => \data_in[23]\, data_in(22) => \data_in[22]\, - data_in(21) => \data_in[21]\, data_in(20) => - \data_in[20]\, data_in(19) => \data_in[19]\, data_in(18) - => \data_in[18]\, data_in(17) => \data_in[17]\, - data_in(16) => \data_in[16]\, data_in(15) => - \data_in[15]\, data_in(14) => \data_in[14]\, data_in(13) - => \data_in[13]\, data_in(12) => \data_in[12]\, - data_in(11) => \data_in[11]\, data_in(10) => - \data_in[10]\, data_in(9) => \data_in[9]\, data_in(8) => - \data_in[8]\, data_in(7) => \data_in[7]\, data_in(6) => - \data_in[6]\, data_in(5) => \data_in[5]\, data_in(4) => - \data_in[4]\, data_in(3) => \data_in[3]\, data_in(2) => - \data_in[2]\, data_in(1) => \data_in[1]\, data_in(0) => - \data_in[0]\, hresp(0) => \ahbso_0.hresp[0]\, address(31) - => \memo.address[31]\, address(30) => \memo.address[30]\, - address(29) => \memo.address[29]\, address(28) => - \memo.address[28]\, romsn_c(1) => \romsn_c[1]\, - romsn_c(0) => \romsn_c[0]\, ramoen_c(3) => \ramoen_c[3]\, - ramoen_c(2) => \ramoen_c[2]\, ramoen_c(1) => - \ramoen_c[1]\, ramoen_c(0) => \ramoen_c[0]\, hmbsel_1(0) - => \ahbsi.hmbsel_1[0]\, hburst_0(2) => \ahbsi.hburst[2]\, - hburst_0(1) => \ahbsi.hburst[1]\, hburst_0(0) => - \ahbsi.hburst[0]\, hmbsel(0) => \ahbsi.hmbsel[0]\, - ramrws_1 => \sr1.r.mcfg2.ramrws[1]\, ramwws(1) => - \sr1.r.mcfg2.ramwws[1]\, ramwws(0) => - \sr1.r.mcfg2.ramwws[0]\, pwdata_1_3 => \apbi.pwdata_1[4]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, pwdata_1_2 => - \apbi.pwdata_1[3]\, rwen_c(3) => \rwen_c[3]\, rwen_c(2) - => \rwen_c[2]\, rwen_c(1) => \rwen_c[1]\, rwen_c(0) => - \rwen_c[0]\, iosn_1_8 => \sr1.iosn_1[101]\, iosn_1_0 => - \sr1.iosn_1[93]\, ramsn_c(3) => \ramsn_c[3]\, ramsn_c(2) - => \ramsn_c[2]\, ramsn_c(1) => \ramsn_c[1]\, ramsn_c(0) - => \ramsn_c[0]\, rambanksz_0 => - \sr1.r.mcfg2.rambanksz[0]\, rambanksz_1 => - \sr1.r.mcfg2.rambanksz[1]\, rambanksz_3 => - \sr1.r.mcfg2.rambanksz[3]\, paddr_2(2) => - \apbi.paddr_2[2]\, iows_3 => \sr1.r.mcfg1.iows[3]\, - iows_2 => \sr1.r.mcfg1.iows[2]\, pwdata_23 => - \apbi.pwdata[28]\, pwdata_22 => \apbi.pwdata[27]\, - pwdata_0_d0 => \apbi.pwdata[5]\, pwdata_7 => - \apbi.pwdata[12]\, pwdata_6 => \apbi.pwdata[11]\, - pwdata_5 => \apbi.pwdata[10]\, pwdata_4 => - \apbi.pwdata[9]\, pwdata_1_d0 => \apbi.pwdata[6]\, - pwdata_18 => \apbi.pwdata[23]\, pwdata_17 => - \apbi.pwdata[22]\, pwdata_16 => \apbi.pwdata[21]\, - pwdata_15 => \apbi.pwdata[20]\, pwdata_20 => - \apbi.pwdata[25]\, pwdata_21 => \apbi.pwdata[26]\, - pwdata_14 => \apbi.pwdata[19]\, pwdata_0_5 => - \apbi.pwdata_0[5]\, pwdata_0_7 => \apbi.pwdata_0[7]\, - pwdata_0_8 => \apbi.pwdata_0[8]\, pwdata_0_9 => - \apbi.pwdata_0[9]\, pwdata_0_2 => \apbi.pwdata_0[2]\, - pwdata_0_1 => \apbi.pwdata_0[1]\, pwdata_0_0 => - \apbi.pwdata_0[0]\, pwdata_0_6 => \apbi.pwdata_0[6]\, - pwdata_0_11 => \apbi.pwdata_0[11]\, hsize(1) => - \ahbsi.hsize[1]\, hsize(0) => \ahbsi.hsize[0]\, romrws_1 - => \sr1.r.mcfg1.romrws[1]\, romrws_3 => - \sr1.r.mcfg1.romrws[3]\, romrws_2 => - \sr1.r.mcfg1.romrws[2]\, hwdata_m_0_3 => - \ahbsi.hwdata_m_0[15]\, hwdata_m_0_2 => - \ahbsi.hwdata_m_0[14]\, hwdata_m_0_0 => - \ahbsi.hwdata_m_0[12]\, psel(0) => \apbi.psel[0]\, - romwidth(1) => \sr1.r.mcfg1.romwidth[1]\, romwidth(0) => - \sr1.r.mcfg1.romwidth[0]\, iosn_100 => \sr1.iosn[101]\, - iosn_99 => \sr1.iosn[100]\, address_c(27) => - \address_c[27]\, address_c(26) => \address_c[26]\, - address_c(25) => \address_c[25]\, address_c(24) => - \address_c[24]\, address_c(23) => \address_c[23]\, - address_c(22) => \address_c[22]\, address_c(21) => - \address_c[21]\, address_c(20) => \address_c[20]\, - address_c(19) => \address_c[19]\, address_c(18) => - \address_c[18]\, address_c(17) => \address_c[17]\, - address_c(16) => \address_c[16]\, address_c(15) => - \address_c[15]\, address_c(14) => \address_c[14]\, - address_c(13) => \address_c[13]\, address_c(12) => - \address_c[12]\, address_c(11) => \address_c[11]\, - address_c(10) => \address_c[10]\, address_c(9) => - \address_c[9]\, address_c(8) => \address_c[8]\, - address_c(7) => \address_c[7]\, address_c(6) => - \address_c[6]\, address_c(5) => \address_c[5]\, - address_c(4) => \address_c[4]\, address_c(3) => - \address_c[3]\, address_c(2) => \address_c[2]\, - address_c(1) => \address_c[1]\, address_c(0) => - \address_c[0]\, hwdata_m_8 => \ahbsi.hwdata_m[15]\, - hwdata_m_7 => \ahbsi.hwdata_m[14]\, hwdata_m_5 => - \ahbsi.hwdata_m[12]\, hwdata_m_0_d0 => - \ahbsi.hwdata_m[7]\, hwdata_m_13 => \ahbsi.hwdata_m[20]\, - data(31) => \memo.data[31]\, data(30) => \memo.data[30]\, - data(29) => \memo.data[29]\, data(28) => \memo.data[28]\, - data(27) => \memo.data[27]\, data(26) => \memo.data[26]\, - data(25) => \memo.data[25]\, data(24) => \memo.data[24]\, - data(23) => \memo.data[23]\, data(22) => \memo.data[22]\, - data(21) => \memo.data[21]\, data(20) => \memo.data[20]\, - data(19) => \memo.data[19]\, data(18) => \memo.data[18]\, - data(17) => \memo.data[17]\, data(16) => \memo.data[16]\, - data(15) => \memo.data[15]\, data(14) => \memo.data[14]\, - data(13) => \memo.data[13]\, data(12) => \memo.data[12]\, - data(11) => \memo.data[11]\, data(10) => \memo.data[10]\, - data(9) => \memo.data[9]\, data(8) => \memo.data[8]\, - data(7) => \memo.data[7]\, data(6) => \memo.data[6]\, - data(5) => \memo.data[5]\, data(4) => \memo.data[4]\, - data(3) => \memo.data[3]\, data(2) => \memo.data[2]\, - data(1) => \memo.data[1]\, data(0) => \memo.data[0]\, - haddr(30) => \ahbsi.haddr[30]\, haddr(29) => - \ahbsi.haddr[29]\, haddr(28) => \ahbsi.haddr[28]\, - haddr(27) => \ahbsi.haddr[27]\, haddr(26) => - \ahbsi.haddr[26]\, haddr(25) => \ahbsi.haddr[25]\, - haddr(24) => \ahbsi.haddr[24]\, haddr(23) => - \ahbsi.haddr[23]\, haddr(22) => \ahbsi.haddr[22]\, - haddr(21) => \ahbsi.haddr[21]\, haddr(20) => - \ahbsi.haddr[20]\, haddr(19) => \ahbsi.haddr[19]\, - haddr(18) => \ahbsi.haddr[18]\, haddr(17) => - \ahbsi.haddr[17]\, haddr(16) => \ahbsi.haddr[16]\, - haddr(15) => \ahbsi.haddr[15]\, haddr(14) => - \ahbsi.haddr[14]\, haddr(13) => \ahbsi.haddr[13]\, - haddr(12) => \ahbsi.haddr[12]\, haddr(11) => - \ahbsi.haddr[11]\, haddr(10) => \ahbsi.haddr[10]\, - haddr(9) => \ahbsi.haddr[9]\, haddr(8) => - \ahbsi.haddr[8]\, haddr(7) => \ahbsi.haddr[7]\, haddr(6) - => \ahbsi.haddr[6]\, haddr(5) => \ahbsi.haddr[5]\, - haddr(4) => \ahbsi.haddr[4]\, haddr(3) => - \ahbsi.haddr[3]\, haddr(2) => \ahbsi.haddr[2]\, haddr(1) - => \ahbsi.haddr[1]\, haddr(0) => \ahbsi.haddr[0]\, - ramwidth(1) => \sr1.r.mcfg2.ramwidth[1]\, ramwidth(0) => - \sr1.r.mcfg2.ramwidth[0]\, htrans(1) => \ahbsi.htrans[1]\, - htrans(0) => \ahbsi.htrans[0]\, iosn_0(93) => - \sr1.iosn_0[93]\, hsel_i(0) => \ahbsi.hsel_i[0]\, - romwws(3) => \sr1.r.mcfg1.romwws[3]\, romwws(2) => - \sr1.r.mcfg1.romwws[2]\, romwws(1) => - \sr1.r.mcfg1.romwws[1]\, romwws(0) => - \sr1.r.mcfg1.romwws[0]\, prdata_0 => \apbo_0.prdata[20]\, - prdata_1 => \apbo_0.prdata[21]\, prdata_8 => - \apbo_0.prdata[28]\, prdata_7 => \apbo_0.prdata[27]\, - hrdata(31) => \ahbso_0.hrdata[31]\, hrdata(30) => - \ahbso_0.hrdata[30]\, hrdata(29) => \ahbso_0.hrdata[29]\, - hrdata(28) => \ahbso_0.hrdata[28]\, hrdata(27) => - \ahbso_0.hrdata[27]\, hrdata(26) => \ahbso_0.hrdata[26]\, - hrdata(25) => \ahbso_0.hrdata[25]\, hrdata(24) => - \ahbso_0.hrdata[24]\, hrdata(23) => \ahbso_0.hrdata[23]\, - hrdata(22) => \ahbso_0.hrdata[22]\, hrdata(21) => - \ahbso_0.hrdata[21]\, hrdata(20) => \ahbso_0.hrdata[20]\, - hrdata(19) => \ahbso_0.hrdata[19]\, hrdata(18) => - \ahbso_0.hrdata[18]\, hrdata(17) => \ahbso_0.hrdata[17]\, - hrdata(16) => \ahbso_0.hrdata[16]\, hrdata(15) => - \ahbso_0.hrdata[15]\, hrdata(14) => \ahbso_0.hrdata[14]\, - hrdata(13) => \ahbso_0.hrdata[13]\, hrdata(12) => - \ahbso_0.hrdata[12]\, hrdata(11) => \ahbso_0.hrdata[11]\, - hrdata(10) => \ahbso_0.hrdata[10]\, hrdata(9) => - \ahbso_0.hrdata[9]\, hrdata(8) => \ahbso_0.hrdata[8]\, - hrdata(7) => \ahbso_0.hrdata[7]\, hrdata(6) => - \ahbso_0.hrdata[6]\, hrdata(5) => \ahbso_0.hrdata[5]\, - hrdata(4) => \ahbso_0.hrdata[4]\, hrdata(3) => - \ahbso_0.hrdata[3]\, hrdata(2) => \ahbso_0.hrdata[2]\, - hrdata(1) => \ahbso_0.hrdata[1]\, hrdata(0) => - \ahbso_0.hrdata[0]\, hwdata_4 => \ahbsi.hwdata[4]\, - hwdata_3 => \ahbsi.hwdata[3]\, hwdata_8 => - \ahbsi.hwdata[8]\, hwdata_13 => \ahbsi.hwdata[13]\, - hwdata_24 => \ahbsi.hwdata[24]\, hwdata_23 => - \ahbsi.hwdata[23]\, hwdata_22 => \ahbsi.hwdata[22]\, - hwdata_20 => \ahbsi.hwdata[20]\, hwdata_10 => - \ahbsi.hwdata[10]\, hwdata_26 => \ahbsi.hwdata[26]\, - hwdata_9 => \ahbsi.hwdata[9]\, hwdata_16 => - \ahbsi.hwdata[16]\, hwdata_17 => \ahbsi.hwdata[17]\, - hwdata_7 => \ahbsi.hwdata[7]\, hwdata_30 => - \ahbsi.hwdata[30]\, hwdata_28 => \ahbsi.hwdata[28]\, - hwdata_5 => \ahbsi.hwdata[5]\, hwdata_31 => - \ahbsi.hwdata[31]\, hwdata_1 => \ahbsi.hwdata[1]\, - hwdata_19 => \ahbsi.hwdata[19]\, hwdata_29 => - \ahbsi.hwdata[29]\, hwdata_21 => \ahbsi.hwdata[21]\, - hwdata_18 => \ahbsi.hwdata[18]\, hwdata_0 => - \ahbsi.hwdata[0]\, hwdata_6 => \ahbsi.hwdata[6]\, - hwdata_2 => \ahbsi.hwdata[2]\, hwdata_27 => - \ahbsi.hwdata[27]\, hwdata_11 => \ahbsi.hwdata[11]\, - hwdata_25 => \ahbsi.hwdata[25]\, bdrive_i(3) => - \memo.bdrive_i[3]\, bdrive_i(2) => \memo.bdrive_i[2]\, - bdrive_i(1) => \memo.bdrive_i[1]\, bdrive_i(0) => - \memo.bdrive_i[0]\, paddr(3) => \apbi.paddr[3]\, paddr(2) - => \apbi.paddr[2]\, iosn_c => iosn_c, lclk_c => lclk_c, - N_6455 => N_6455, N_5062 => N_5062, un6_ioen_NE_0 => - \ahb0.comb.0.4.un6_ioen_NE_0\, N_510 => N_510, N_6459 => - N_6459, N_5070 => N_5070, bexcen => \sr1.r.mcfg1.bexcen\, - brdyen => \sr1.r.mcfg1.brdyen\, ioen => - \sr1.r.mcfg1.ioen\, writen_c => writen_c, hwrite_m_0_0 - => \ahbsi.hwrite_m_0_0\, hwrite => \ahbsi.hwrite\, - brmw_1 => \sr1.ctrl.brmw_1\, N_6550 => N_6550, oen_c => - oen_c, rdata61_2 => \ua1.uart1.uartop.rdata61_2\, - un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\, brmw_i => - \sr1.ctrl.un1_r.brmw_i\, N_6377 => N_6377, rmw => - \sr1.r.mcfg2.rmw\, rstn => rstn, read_c => read_c, hready - => \ahbso_0.hready\, N_232_0 => \ua1.uart1.N_232_0\, - N_6455_0 => N_6455_0); - - SSRAM_CLK_pad_RNO : INV - port map(A => clk_c, Y => clk_c_i); - - \pci_ad_pad[12]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(12)); - - \gpio0.grgpio0\ : grgpio - port map(un1_grgpio0_7 => \gpio0.un1_grgpio0[71]\, - un1_grgpio0_5 => \gpio0.un1_grgpio0[69]\, gpio_in(7) => - \gpio_in[7]\, gpio_in(6) => \gpio_in[6]\, gpio_in(5) => - \gpio_in[5]\, gpio_in(4) => \gpio_in[4]\, gpio_in(3) => - \gpio_in[3]\, gpio_in(2) => \gpio_in[2]\, gpio_in(1) => - \gpio_in[1]\, gpio_in(0) => \gpio_in[0]\, pwdata_i(7) => - \apbi.pwdata_i[7]\, pwdata_i(6) => \apbi.pwdata_i[6]\, - pwdata_i(5) => \apbi.pwdata_i[5]\, pwdata_i(4) => - \apbi.pwdata_i[4]\, pwdata_i(3) => \apbi.pwdata_i[3]\, - pwdata_i(2) => \apbi.pwdata_i[2]\, pwdata_i(1) => - \apbi.pwdata_i[1]\, pwdata_i(0) => \apbi.pwdata_i[0]\, - paddr(5) => \apbi.paddr[5]\, paddr(4) => \apbi.paddr[4]\, - paddr(3) => \apbi.paddr[3]\, paddr(2) => \apbi.paddr[2]\, - readdata_2_m(5) => \gpio0.grgpio0.comb.readdata_2_m[5]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, pwdata_1_3 => - \apbi.pwdata_1[4]\, pwdata_1_2 => \apbi.pwdata_1[3]\, - pwdata_0_5 => \apbi.pwdata_0[5]\, pwdata_0_7 => - \apbi.pwdata_0[7]\, pwdata_0_6 => \apbi.pwdata_0[6]\, - pwdata_0_2 => \apbi.pwdata_0[2]\, pwdata_0_0 => - \apbi.pwdata_0[0]\, dout(7) => \gpioo.dout[7]\, dout(6) - => \gpioo.dout[6]\, dout(5) => \gpioo.dout[5]\, dout(4) - => \gpioo.dout[4]\, dout(3) => \gpioo.dout[3]\, dout(2) - => \gpioo.dout[2]\, dout(1) => \gpioo.dout[1]\, dout(0) - => \gpioo.dout[0]\, psel(11) => \apbi.psel[11]\, - prdata_iv_0_0_d0 => \gpio0.grgpio0.apbo.prdata_iv_0[1]\, - prdata_iv_0_2 => \gpio0.grgpio0.apbo.prdata_iv_0[3]\, - prdata_iv_0_0(2) => \gpio0.grgpio0.apbo.prdata_iv_0_0[2]\, - oen_7 => \gpioo.oen[7]\, oen_i(7) => \gpioo.oen_i[7]\, - oen_i(6) => \gpioo.oen_i[6]\, oen_i(5) => - \gpioo.oen_i[5]\, oen_i(4) => \gpioo.oen_i[4]\, oen_i(3) - => \gpioo.oen_i[3]\, oen_i(2) => \gpioo.oen_i[2]\, - oen_i(1) => \gpioo.oen_i[1]\, oen_i(0) => - \gpioo.oen_i[0]\, paddr_0(3) => \apbi.paddr_0[3]\, - paddr_0(2) => \apbi.paddr_0[2]\, lclk_c => lclk_c, - N_232_2 => \ua1.uart1.N_232\, rdata61_2 => - \ua1.uart1.uartop.rdata61_2\, N_6432 => N_6432, rstn => - rstn, N_6439 => N_6439, N_6437 => N_6437, N_6436 => - N_6436, N_6435 => N_6435, N_6434 => N_6434, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, N_6430 => N_6430, rdata59_4 - => \ua1.uart1.uartop.rdata59_4\, N_6429 => N_6429, - N_6428 => N_6428, N_6459 => N_6459, readdata55_3 => - \gpt.timer0.comb.readdata55_3\, un1_apbi_0 => - \gpt.timer0.comb.un1_apbi_0\, rdata60_4_0 => - \ua1.uart1.uartop.rdata60_4_0\, N_232_0 => - \ua1.uart1.N_232_0\, N_232_1 => \ua1.uart1.N_232_1\); - - \data_pad[2]\ : BIBUF - port map(PAD => data(2), D => \memo.data[2]\, E => - \memo.bdrive_i[3]\, Y => \data_in[2]\); - - \sdo_adc_pad[4]\ : INBUF - port map(PAD => sdo_adc(4), Y => \sdo_adc_c[4]\); - - pci_perr_pad : OUTBUF - port map(D => \GND\, PAD => pci_perr); - - \rwen_pad[0]\ : OUTBUF - port map(D => \rwen_c[0]\, PAD => rwen(0)); - - \pci_ad_pad[28]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(28)); - - \address_pad[27]\ : OUTBUF - port map(D => \address_c[27]\, PAD => address(27)); - - \pci_ad_pad[4]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(4)); - - \pci_ad_pad[16]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(16)); - - \address_pad[6]\ : OUTBUF - port map(D => \address_c[6]\, PAD => address(6)); - - \address_pad[5]\ : OUTBUF - port map(D => \address_c[5]\, PAD => address(5)); - - d_m2_e : OR2B - port map(A => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a1_6_i_0\, - B => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a0_6_i_0\, - Y => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_0_N_15_i_0_li\); - - \data_pad[24]\ : BIBUF - port map(PAD => data(24), D => \memo.data[24]\, E => - \memo.bdrive_i[0]\, Y => \data_in[24]\); - - \pci_arb_gnt_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => pci_arb_gnt(1)); - - \data_pad[11]\ : BIBUF - port map(PAD => data(11), D => \memo.data[11]\, E => - \memo.bdrive_i[2]\, Y => \data_in[11]\); - - CE2_pad : OUTBUF - port map(D => CE2_c, PAD => CE2); - - \data_pad[8]\ : BIBUF - port map(PAD => data(8), D => \memo.data[8]\, E => - \memo.bdrive_i[2]\, Y => \data_in[8]\); - - \address_pad[26]\ : OUTBUF - port map(D => \address_c[26]\, PAD => address(26)); - - epause_pad : OUTBUF - port map(D => \GND\, PAD => epause); - - pci_trdy_pad : OUTBUF - port map(D => \GND\, PAD => pci_trdy); - - \pci_ad_pad[27]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(27)); - - oen_pad : OUTBUF - port map(D => oen_c, PAD => oen); - - \data_pad[22]\ : BIBUF - port map(PAD => data(22), D => \memo.data[22]\, E => - \memo.bdrive_i[1]\, Y => \data_in[22]\); - - \sdo_adc_pad[6]\ : INBUF - port map(PAD => sdo_adc(6), Y => \sdo_adc_c[6]\); - - \address_pad[17]\ : OUTBUF - port map(D => \address_c[17]\, PAD => address(17)); - - \data_pad[18]\ : BIBUF - port map(PAD => data(18), D => \memo.data[18]\, E => - \memo.bdrive_i[1]\, Y => \data_in[18]\); - - \data_pad[15]\ : BIBUF - port map(PAD => data(15), D => \memo.data[15]\, E => - \memo.bdrive_i[2]\, Y => \data_in[15]\); - - \pci_cbe_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => pci_cbe(1)); - - \data_pad[0]\ : BIBUF - port map(PAD => data(0), D => \memo.data[0]\, E => - \memo.bdrive_i[3]\, Y => \data_in[0]\); - - \pci_ad_pad[31]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(31)); - - \pci_ad_pad[6]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(6)); - - -end DEF_ARCH; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/lpp-dm-sheldon-a3pe3000/config.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/lpp-dm-sheldon-a3pe3000/config.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/lpp-dm-sheldon-a3pe3000/config.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3e; - constant CFG_MEMTECH : integer := apa3e; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - --constant CFG_NWIN : integer := (7); -- PLE - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist - --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (3); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/lpp-dm-sheldon-a3pe3000/leon3mp.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/lpp-dm-sheldon-a3pe3000/leon3mp.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/lpp-dm-sheldon-a3pe3000/leon3mp.vhd +++ /dev/null @@ -1,508 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -library techmap; -use techmap.gencomp.all; -library gaisler; -use gaisler.memctrl.all; -use gaisler.leon3.all; -use gaisler.uart.all; -use gaisler.misc.all; -use gaisler.spacewire.all; -- PLE -library esa; -use esa.memoryctrl.all; -use work.config.all; -library lpp; ---use lpp.lpp_amba.all; -use lpp.lpp_memory.all; ---use lpp.lpp_uart.all; ---use lpp.lpp_matrix.all; ---use lpp.lpp_delay.all; ---use lpp.lpp_fft.all; ---use lpp.fft_components.all; ---use lpp.lpp_ad_conv.all; ---use lpp.iir_filter.all; -use lpp.general_purpose.all; ---use lpp.Filtercfg.all; -use lpp.lpp_lfr_time_management.all; -- PLE -use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE -use lpp.lpp_top_lfr_pkg.all; - -entity leon3mp is - generic ( - fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console - pclow : integer := CFG_PCLOW - ); - port ( - clk100MHz : in std_ulogic; - clk49_152MHz : in std_ulogic; - reset : in std_ulogic; - ramclk : out std_logic; - - ahbrxd : in std_ulogic; -- DSU rx data - ahbtxd : out std_ulogic; -- DSU tx data - dsubre : in std_ulogic; - dsuact : out std_ulogic; - urxd1 : in std_ulogic; -- UART1 rx data - utxd1 : out std_ulogic; -- UART1 tx data - errorn : out std_ulogic; - - address : out std_logic_vector(18 downto 0); - data : inout std_logic_vector(31 downto 0); - gpio : inout std_logic_vector(6 downto 0); -- I/O port - - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------In/Out----------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - led : out std_logic_vector(1 downto 0); - - -- waveform picker------ - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic; - - -- SPACEWIRE ----------- - spw1_din : in std_logic; -- PLE - spw1_sin : in std_logic; -- PLE - spw1_dout : out std_logic; -- PLE - spw1_sout : out std_logic; -- PLE - spw1_en_bar : out std_logic; - spw2_en_bar : out std_logic - ); -end; - -architecture Behavioral of leon3mp is - ---constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ --- CFG_GRETH+CFG_AHB_JTAG; -constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+1 -- 1 is for the SpaceWire module grspw2, which is a master - +1; -- 1 is for the waveform picker top -constant maxahbm : integer := maxahbmsp; - ---Clk & Rst géné -signal vcc : std_logic_vector(4 downto 0); -signal gnd : std_logic_vector(4 downto 0); -signal resetnl : std_ulogic; -signal clk2x : std_ulogic; -signal lclk2x : std_ulogic; -signal lclk25MHz : std_ulogic; -signal lclk50MHz : std_ulogic; -signal lclk100MHz : std_ulogic; -signal clkm : std_ulogic; -signal rstn : std_ulogic; -signal rstraw : std_ulogic; -signal pciclk : std_ulogic; -signal sdclkl : std_ulogic; -signal cgi : clkgen_in_type; -signal cgo : clkgen_out_type; ---- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); ---UART -signal ahbuarti : uart_in_type; -signal ahbuarto : uart_out_type; -signal apbuarti : uart_in_type; -signal apbuarto : uart_out_type; ---MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal wpo : wprot_out_type; -signal sdo : sdram_out_type; ---IRQ -signal irqi : irq_in_vector(0 to CFG_NCPU-1); -signal irqo : irq_out_vector(0 to CFG_NCPU-1); ---Timer -signal gpti : gptimer_in_type; -signal gpto : gptimer_out_type; ---GPIO -signal gpioi : gpio_in_type; -signal gpioo : gpio_out_type; ---DSU -signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); -signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); -signal dsui : dsu_in_type; -signal dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- -constant IOAEN : integer := CFG_CAN; -constant boardfreq : integer := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - signal coarse_time : std_logic_vector(31 downto 0); - signal fine_time : std_logic_vector(31 downto 0); - --- Spacewire signals - signal dtmp : std_ulogic; -- PLE - signal stmp : std_ulogic; -- PLE - signal rxclko : std_ulogic; -- PLE - signal swni : grspw_in_type; -- PLE - signal swno : grspw_out_type; -- PLE - signal clkmn : std_ulogic; -- PLE - signal txclk : std_ulogic; -- PLE 2013 02 14 - --- ahb status signals - signal stati : ahbstat_in_type; - -begin - ---------------------------------------------------------------------- ---- AJOUT TEST -------------------------------------IPs------------- ---------------------------------------------------------------------- - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (others => '1'); gnd <= (others => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad generic map (tech => padtech) port map (clk100MHz, lclk100MHz); - - -- IT SEEMS THAT THE PLL IS NOT INSTANTIATED AND THAT lclk2x is a 50 MHz CLOCK - clkgen0 : clkgen -- clock generator - generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - --port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); -- PLE - port map (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); -- PLE - - ramclk <= clkm; - -process(lclk100MHz) -begin - if lclk100MHz'event and lclk100MHz = '1' then - lclk50MHz <= not lclk50MHz; - end if; -end process; - -process(lclk50MHz) -begin - if lclk50MHz'event and lclk50MHz = '1' then - lclk25MHz <= not lclk25MHz; - end if; -end process; - -lclk2x <= lclk50MHz; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : if CFG_LEON3 = 1 generate - cpu : for i in 0 to CFG_NCPU-1 generate - u0 : leon3s -- LEON3 processor - generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - end generate; - errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); - - dsugen : if CFG_DSU = 1 generate - dsu0 : dsu3 -- LEON3 Debug Support Unit - generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); --- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); - dsui.enable <= '1'; - dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); - dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); - end generate; - end generate; - - nodsu : if CFG_DSU = 0 generate - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - end generate; - - irqctrl : if CFG_IRQ3_ENABLE /= 0 generate - irqctrl0 : irqmp -- interrupt controller - generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - port map (rstn, clkm, apbi, apbo(2), irqo, irqi); - end generate; - irq3 : if CFG_IRQ3_ENABLE = 0 generate - x : for i in 0 to CFG_NCPU-1 generate - irqi(i).irl <= "0000"; - end generate; - apbo(2) <= apb_none; - end generate; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - - memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - bdr : for i in 0 to 3 generate - data_pad : iopadv generic map (tech => padtech, width => 8) - port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), - memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); - end generate; - - - addr_pad : outpadv generic map (width => 19, tech => padtech) - port map (address, memo.address(20 downto 2)); - - - SSRAM_0:entity ssram_plugin - generic map (tech => padtech) - port map - (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - dcomgen : if CFG_AHB_UART = 1 generate - dcom0: ahbuart -- Debug UART - generic map (hindex => 3, pindex => 4, paddr => 4) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); - dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); - led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; - end generate; - nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR) - port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - - gpt : if CFG_GPT_ENABLE /= 0 generate - timer0 : gptimer -- timer unit - generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - port map (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; --- led(4) <= gpto.wdog; - end generate; - notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - ua1 : if CFG_UART1_ENABLE /= 0 generate - uart1 : apbuart -- UART 1 - generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; --- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; - end generate; - noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit - grgpio0: grgpio - generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) - port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : for i in 0 to 6 generate - pio_pad : iopad generic map (tech => padtech) - port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - end generate; - end generate; - --------------------------- --- APB_LFR_TIME_MANAGEMENT --------------------------- - lfrtimemanagement0 : apb_lfr_time_management - generic map(pindex => 6, paddr => 6, pmask => 16#fff#, - masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536, - pirq => 12) -- the IP uses 2 consecutive IRQ lines - port map(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6), - coarse_time, fine_time); - --------------------------------- --- APB_LFR_SPECTRAL_MATRICES_DMA --------------------------------- --- lfrspectralmatricesdma0 : apb_lfr_spectral_matrices_DMA --- generic map(pindex => 7, paddr =>7, pmask => 16#fff#) --- port map(clkm, rstn, apbi, apbo(7)); - ------------------------------- ---- AHB STATUS --------------- ------------------------------- - ---astat0 : ahbstat generic map(pindex => 13, paddr => 13, pirq => 14, nftslv => 3) --- port map(rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13)); --- stati.cerror(3 to NAHBSLV-1) <= (others => '0'); - ------------------- --- WAVEFORM PICKER ------------------- - -waveform_picker0 : lpp_top_lfr_wf_picker generic map( - hindex => 2, - pindex => 8, - paddr => 8, - pmask => 16#fff#, - pirq => 15, - tech => CFG_FABTECH, - nb_burst_available_size => 11, -- size of the register holding the nb of burst - nb_snapshot_param_size => 11, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 10, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 10 -- nb f0 ticks before starting the f1 snapshot - ) - port map( - -- ADS7886 - cnv_run => '1', -- stop the sampling request - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(8), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(2), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => Bias_Fails - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - -spw_phy0 : grspw2_phy generic map( - scantest => 0, - tech => memtech, - input_type => 0) -- self_clocking mode - port map( - rstn => rstn, - rxclki => clkm, rxclkin => clkmn, nrxclki => clkm, -- not used in self-clocking - di => dtmp, - si => stmp, - do => swni.d(1 downto 0), - dov => swni.dv(1 downto 0), - dconnect => swni.dconnect(1 downto 0), - rxclko => rxclko); - -sw0 : grspwm generic map(tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, usegen => 1, -- sysfreq not used by the core version 2? usegen? - nsync => 1, -- nsync not used by the core version 2? - rmap => 1, rmapcrc => 1, - fifosize1 => 16, fifosize2 => 16, - rxclkbuftype => 2, rxunaligned => 0, - spwcore => 2, - memtech => apa3e, - nodeaddr => 254, destkey => 2, - rmapbufs => 4, netlist => 0, ft => 0, ports => 2) - port map(rstn, clkm, rxclko, rxclko, txclk, txclk, - ahbmi, ahbmo(1), apbi, apbo(5), swni, swno); - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00001001"; -- divisor to get a 10M Hz tx clock from the txclk input - - - spw1_dout <= swno.d(0); - spw1_sout <= swno.s(0); - dtmp <= not(spw1_din); - stmp <= not(spw1_sin); - spw1_en_bar <= '0'; -- V16, connected to spw2_en - spw2_en_bar <= '1'; -- T18, connected to spw1_en - - txclk <= lclk100MHz; - -end Behavioral; \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/testbench.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/testbench.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/testbench.vhd +++ /dev/null @@ -1,589 +0,0 @@ ------------------------------------------------------------------------------- --- LEON3 Demonstration design test bench --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2010, Aeroflex Gaisler --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; ---LIBRARY micron; ---USE micron.components.ALL; -USE work.debug.ALL; - -USE work.config.ALL; -- configuration - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -ENTITY testbench IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW; - - clkperiod : INTEGER := 20; -- system clock period - romwidth : INTEGER := 32; -- rom data width (8/32) - romdepth : INTEGER := 16; -- rom address depth - sramwidth : INTEGER := 32; -- ram data width (8/16/32) - sramdepth : INTEGER := 21; -- ram address depth - srambanks : INTEGER := 2 -- number of ram banks - ); - PORT ( - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC - ); -END; - -ARCHITECTURE behav OF testbench IS - - CONSTANT promfile : STRING := "prom.srec"; -- rom contents - CONSTANT sramfile : STRING := "sram.srec"; -- ram contents - CONSTANT sdramfile : STRING := "sdram.srec"; -- sdram contents - - COMPONENT leon3mp - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - resetn : IN STD_ULOGIC; - clk : IN STD_ULOGIC; - pllref : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dsutx : OUT STD_ULOGIC; -- DSU tx data - dsurx : IN STD_ULOGIC; -- DSU rx data - dsuen : IN STD_ULOGIC; - dsubre : IN STD_ULOGIC; - dsuact : OUT STD_ULOGIC; - txd1 : OUT STD_ULOGIC; -- UART1 tx data - rxd1 : IN STD_ULOGIC; -- UART1 rx data - txd2 : OUT STD_ULOGIC; -- UART1 tx data - rxd2 : IN STD_ULOGIC; -- UART1 rx datax - ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - oen : OUT STD_ULOGIC; - writen : OUT STD_ULOGIC; - read : OUT STD_ULOGIC; - iosn : OUT STD_ULOGIC; - romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - - emddis : OUT STD_LOGIC; - epwrdwn : OUT STD_LOGIC; - ereset : OUT STD_LOGIC; - esleep : OUT STD_LOGIC; - epause : OUT STD_LOGIC; - - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC; - pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - spw_clk : IN STD_ULOGIC; - spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - ramclk : OUT STD_LOGIC; - - nBWa : OUT STD_LOGIC; - nBWb : OUT STD_LOGIC; - nBWc : OUT STD_LOGIC; - nBWd : OUT STD_LOGIC; - nBWE : OUT STD_LOGIC; - nADSC : OUT STD_LOGIC; - nADSP : OUT STD_LOGIC; - nADV : OUT STD_LOGIC; - nGW : OUT STD_LOGIC; - nCE1 : OUT STD_LOGIC; - CE2 : OUT STD_LOGIC; - nCE3 : OUT STD_LOGIC; - nOE : OUT STD_LOGIC; - MODE : OUT STD_LOGIC; - SSRAM_CLK : OUT STD_LOGIC; - ZZ : OUT STD_LOGIC; - - tck, tms, tdi : IN STD_ULOGIC; - tdo : OUT STD_ULOGIC; - -- waveform picker------ - clk49_152MHz : in std_ulogic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic - - - - ); - END COMPONENT; - - COMPONENT CY7C1360C - GENERIC ( - addr_bits : INTEGER; - data_bits : INTEGER; - Cyp_tCO : TIME; - Cyp_tCYC : TIME; - Cyp_tCH : TIME; - Cyp_tCL : TIME; - Cyp_tCHZ : TIME; - Cyp_tCLZ : TIME; - Cyp_tOEHZ : TIME; - Cyp_tOELZ : TIME; - Cyp_tOEV : TIME; - Cyp_tAS : TIME; - Cyp_tADS : TIME; - Cyp_tADVS : TIME; - Cyp_tWES : TIME; - Cyp_tDS : TIME; - Cyp_tCES : TIME; - Cyp_tAH : TIME; - Cyp_tADH : TIME; - Cyp_tADVH : TIME; - Cyp_tWEH : TIME; - Cyp_tDH : TIME; - Cyp_tCEH : TIME); - PORT ( - iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) DOWNTO 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) DOWNTO 0); - iCLK : IN STD_LOGIC); - END COMPONENT; - - - SIGNAL clk : STD_LOGIC := '0'; - SIGNAL Rst : STD_LOGIC := '0'; -- Reset - CONSTANT ct : INTEGER := clkperiod/2; - - SIGNAL address : STD_LOGIC_VECTOR(27 DOWNTO 0); - SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL ioData : STD_LOGIC_VECTOR(35 DOWNTO 0); - - SIGNAL ramsn : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL ramoen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL rwen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL rwenx : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL romsn : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL iosn : STD_ULOGIC; - SIGNAL oen : STD_ULOGIC; - SIGNAL read : STD_ULOGIC; - SIGNAL writen : STD_ULOGIC; - SIGNAL brdyn : STD_ULOGIC; - SIGNAL bexcn : STD_ULOGIC; - SIGNAL wdog : STD_ULOGIC; - SIGNAL dsuen, dsutx, dsurx, dsubre, dsuact : STD_ULOGIC; - SIGNAL dsurst : STD_ULOGIC; - SIGNAL test : STD_ULOGIC; - SIGNAL error : STD_LOGIC; - SIGNAL gpio : STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); - SIGNAL GND : STD_ULOGIC := '0'; - SIGNAL VCC : STD_ULOGIC := '1'; - SIGNAL NC : STD_ULOGIC := 'Z'; - SIGNAL clk2 : STD_ULOGIC := '1'; - - SIGNAL sdcke : STD_LOGIC_VECTOR (1 DOWNTO 0); -- clk en - SIGNAL sdcsn : STD_LOGIC_VECTOR (1 DOWNTO 0); -- chip sel - SIGNAL sdwen : STD_ULOGIC; -- write en - SIGNAL sdrasn : STD_ULOGIC; -- row addr stb - SIGNAL sdcasn : STD_ULOGIC; -- col addr stb - SIGNAL sddqm : STD_LOGIC_VECTOR (7 DOWNTO 0); -- data i/o mask - SIGNAL sdclk : STD_ULOGIC; - SIGNAL plllock : STD_ULOGIC; - SIGNAL txd1, rxd1 : STD_ULOGIC; - SIGNAL txd2, rxd2 : STD_ULOGIC; - - SIGNAL etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : STD_LOGIC := '0'; - SIGNAL erxd, etxd : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); - SIGNAL erxdt, etxdt : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); - SIGNAL emdc : STD_LOGIC; - SIGNAL gtx_clk : STD_ULOGIC; - - SIGNAL emddis : STD_LOGIC; - SIGNAL epwrdwn : STD_LOGIC; - SIGNAL ereset : STD_LOGIC; - SIGNAL esleep : STD_LOGIC; - SIGNAL epause : STD_LOGIC; - - CONSTANT lresp : BOOLEAN := false; - - SIGNAL sa : STD_LOGIC_VECTOR(14 DOWNTO 0); - SIGNAL sd : STD_LOGIC_VECTOR(63 DOWNTO 0); - - SIGNAL pci_arb_req, pci_arb_gnt : STD_LOGIC_VECTOR(0 TO 3); - - - SIGNAL spw_clk : STD_ULOGIC := '0'; - SIGNAL spw_rxd : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxdn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxs : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxsn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_txd : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txdn : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txs : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txsn : STD_LOGIC_VECTOR(0 TO 2); - - SIGNAL tck, tms, tdi, tdo : STD_ULOGIC; - - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - CONSTANT CFG_SD64 : INTEGER := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64; - - ----------------------------------------------------------------------------- - - SIGNAL ramclk : STD_LOGIC; - - SIGNAL nBWa : STD_LOGIC; - SIGNAL nBWb : STD_LOGIC; - SIGNAL nBWc : STD_LOGIC; - SIGNAL nBWd : STD_LOGIC; - SIGNAL nBWE : STD_LOGIC; - SIGNAL nADSC : STD_LOGIC; - SIGNAL nADSP : STD_LOGIC; - SIGNAL nADV : STD_LOGIC; - SIGNAL nGW : STD_LOGIC; - SIGNAL nCE1 : STD_LOGIC; - SIGNAL CE2 : STD_LOGIC; - SIGNAL nCE3 : STD_LOGIC; - SIGNAL nOE : STD_LOGIC; - SIGNAL MODE : STD_LOGIC; - SIGNAL SSRAM_CLK : STD_LOGIC; - SIGNAL ZZ : STD_LOGIC; - - -- - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - - SIGNAL clk49_152MHz : STD_LOGIC := '0'; - SIGNAL sdo_adc : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL cnv_ch1 : STD_LOGIC; - SIGNAL sck_ch1 : STD_LOGIC; - SIGNAL Bias_Fails : STD_LOGIC; - -BEGIN - --- clock and reset - - spw_clk <= NOT spw_clk AFTER 20 ns; - spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0); - spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0); - spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1); - spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1); - spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2); - spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2); - clk <= NOT clk AFTER ct * 1 ns; - clk49_152MHz <= NOT clk49_152MHz AFTER 203 * 100 ps; - rst <= dsurst; - dsuen <= '1'; dsubre <= '0'; rxd1 <= '1'; - - d3 : leon3mp - GENERIC MAP (fabtech, - memtech, - padtech, - clktech, - disas, - dbguart, - pclow) - PORT MAP (rst, clk, sdclk, error, address(27 DOWNTO 0), data, - dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2, - ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio, - - emddis, epwrdwn, ereset, esleep, epause, - pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par, - pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt, - spw_clk, spw_rxd, spw_rxdn, spw_rxs, - spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, - - - ramclk , - nBWa , - nBWb , - nBWc , - nBWd , - nBWE , - nADSC , - nADSP , - nADV , - nGW , - nCE1 , - CE2 , - nCE3 , - nOE , - MODE , - SSRAM_CLK , - ZZ , - - tck, tms, tdi, tdo, - clk49_152MHz, - sdo_adc , - cnv_ch1 , - sck_ch1 , - Bias_Fails); - - - -- component instantiation - ----------------------------------------------------------------------------- - - MODULE_ADS7886 : FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => '1', - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => '1', - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc(7)); - - - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - - prom0 : FOR i IN 0 TO (romwidth/8)-1 GENERATE - sr0 : sram GENERIC MAP (index => i, abits => romdepth, fname => promfile) - PORT MAP (address(romdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), romsn(0), - rwen(i), oen); - END GENERATE; - - ----------------------------------------------------------------------------- - CY7C1360C_2 : CY7C1360C - GENERIC MAP ( - - - addr_bits => 19, - data_bits => 36, - - Cyp_tCO => 3.5 ns, -- Data Output Valid After CLK Rise - Cyp_tCYC => 6.0 ns, -- Clock cycle time - Cyp_tCH => 2.4 ns, -- Clock HIGH time - Cyp_tCL => 2.4 ns, -- Clock LOW time - Cyp_tCHZ => 3.5 ns, -- Clock to High-Z - Cyp_tCLZ => 1.25 ns, -- Clock to Low-Z - Cyp_tOEHZ => 3.5 ns, -- OE# HIGH to Output High-Z - Cyp_tOELZ => 0.0 ns, -- OE# LOW to Output Low-Z - Cyp_tOEV => 3.5 ns, -- OE# LOW to Output Valid - Cyp_tAS => 1.5 ns, -- Address Set-up Before CLK Rise - Cyp_tADS => 1.5 ns, -- ADSC#, ADSP# Set-up Before CLK Rise - Cyp_tADVS => 1.5 ns, -- ADV# Set-up Before CLK Rise - Cyp_tWES => 1.5 ns, -- BWx#, GW#, BWE# Set-up Before CLK Rise - Cyp_tDS => 1.5 ns, -- Data Input Set-up Before CLK Rise - Cyp_tCES => 1.5 ns, -- Chip Enable Set-up - Cyp_tAH => 0.5 ns, -- Address Hold After CLK Rise - Cyp_tADH => 0.5 ns, -- ADSC#, ADSP# Hold After CLK Rise - Cyp_tADVH => 0.5 ns, -- ADV# Hold After CLK Rise - Cyp_tWEH => 0.5 ns, -- BWx#, GW#, BWE# Hold After CLK Rise - Cyp_tDH => 0.5 ns, -- Data Input Hold After CLK Rise - Cyp_tCEH => 0.5 ns -- Chip Enable Hold After CLK Rise - - - --Cyp_tCO => 2.8 ns, - --Cyp_tCYC => 4.0 ns, - --Cyp_tCH => 1.8 ns, - --Cyp_tCL => 1.8 ns, - --Cyp_tCHZ => 2.8 ns, - --Cyp_tCLZ => 1.25 ns, - --Cyp_tOEHZ => 2.8 ns, - --Cyp_tOELZ => 0.0 ns, - --Cyp_tOEV => 2.8 ns, - --Cyp_tAS => 1.4 ns, - --Cyp_tADS => 1.4 ns, - --Cyp_tADVS => 1.4 ns, - --Cyp_tWES => 1.4 ns, - --Cyp_tDS => 1.4 ns, - --Cyp_tCES => 1.4 ns, - --Cyp_tAH => 0.4 ns, - --Cyp_tADH => 0.4 ns, - --Cyp_tADVH => 0.4 ns, - --Cyp_tWEH => 0.4 ns, - --Cyp_tDH => 0.4 ns, - --Cyp_tCEH => 0.4 ns - ) - PORT MAP ( - iZZ => ZZ, - iMode => MODE, - iADDR => address(20 DOWNTO 2), - inGW => nGW, - inBWE => nBWE, - inBWd => nBWd, - inBWc => nBWc, - inBWb => nBWb, - inBWa => nBWa, - inCE1 => nCE1, - iCE2 => CE2, - inCE3 => nCE3, - inADSP => nADSP, - inADSC => nADSC, - inADV => nADV, - inOE => nOE, - ioDQ => ioData, -- - iCLK => SSRAM_CLK); -- ?? - - - ioData <= "0" & data(31 DOWNTO 24) & - "0" & data(23 DOWNTO 16) & - "0" & data(15 DOWNTO 8) & - "0" & data(7 DOWNTO 0); - - --sbanks : FOR k IN 0 TO srambanks-1 GENERATE - -- sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE - -- sr0 : sram GENERIC MAP (index => i, abits => sramdepth, fname => sramfile) - -- PORT MAP (address(sramdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), - -- ramsn(k), rwen(i), ramoen(k)); - -- END GENERATE; - --END GENERATE; - - error <= 'H'; -- ERROR pull-up - - iuerr : PROCESS - BEGIN - WAIT FOR 2500 ns; - IF to_x01(error) = '1' THEN WAIT ON error; END IF; - ASSERT (to_x01(error) = '1') - REPORT "*** IU in error mode, simulation halted ***" - SEVERITY failure; - END PROCESS; - - data <= buskeep(data), (OTHERS => 'H') AFTER 250 ns; - sd <= buskeep(sd), (OTHERS => 'H') AFTER 250 ns; - - test0 : grtestmod - PORT MAP (rst, clk, error, address(21 DOWNTO 2), data, iosn, oen, writen, brdyn); - - - dsucom : PROCESS - PROCEDURE dsucfg(SIGNAL dsurx : IN STD_ULOGIC; SIGNAL dsutx : OUT STD_ULOGIC) IS - VARIABLE w32 : STD_LOGIC_VECTOR(31 DOWNTO 0); - VARIABLE c8 : STD_LOGIC_VECTOR(7 DOWNTO 0); - CONSTANT txp : TIME := 160 * 1 ns; - BEGIN - dsutx <= '1'; - dsurst <= '0'; - WAIT FOR 500 ns; - dsurst <= '1'; - WAIT; - WAIT FOR 5000 ns; - END; - BEGIN - - dsucfg(dsutx, dsurx); - WAIT; - - END PROCESS; - -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/testbench_post.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/testbench_post.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-header/testbench_post.vhd +++ /dev/null @@ -1,770 +0,0 @@ ------------------------------------------------------------------------------- --- LEON3 Demonstration design test bench --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2010, Aeroflex Gaisler --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; ---LIBRARY micron; ---USE micron.components.ALL; -USE work.debug.ALL; - -USE work.config.ALL; -- configuration - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -ENTITY testbench IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW; - - clkperiod : INTEGER := 20; -- system clock period - romwidth : INTEGER := 32; -- rom data width (8/32) - romdepth : INTEGER := 16; -- rom address depth - sramwidth : INTEGER := 32; -- ram data width (8/16/32) - sramdepth : INTEGER := 21; -- ram address depth - srambanks : INTEGER := 2 -- number of ram banks - ); - PORT ( - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC - ); -END; - -ARCHITECTURE behav OF testbench IS - - CONSTANT promfile : STRING := "prom.srec"; -- rom contents - CONSTANT sramfile : STRING := "sram.srec"; -- ram contents - CONSTANT sdramfile : STRING := "sdram.srec"; -- sdram contents - - COMPONENT leon3mp_wfp - PORT ( - resetn : in std_logic; - clk : in std_logic; - pllref : in std_logic; - errorn : out std_logic; - address : out std_logic_vector(27 downto 0); - data : inout std_logic_vector(31 downto 0) := (others => 'Z'); - dsutx : out std_logic; - dsurx : in std_logic; - dsuen : in std_logic; - dsubre : in std_logic; - dsuact : out std_logic; - txd1 : out std_logic; - rxd1 : in std_logic; - txd2 : out std_logic; - rxd2 : in std_logic; - ramsn : out std_logic_vector(4 downto 0); - ramoen : out std_logic_vector(4 downto 0); - rwen : out std_logic_vector(3 downto 0); - oen : out std_logic; - writen : out std_logic; - read : out std_logic; - iosn : out std_logic; - romsn : out std_logic_vector(1 downto 0); - gpio : inout std_logic_vector(7 downto 0) := (others => 'Z'); - emddis : out std_logic; - epwrdwn : out std_logic; - ereset : out std_logic; - esleep : out std_logic; - epause : out std_logic; - pci_rst : out std_logic; - pci_clk : in std_logic; - pci_gnt : in std_logic; - pci_idsel : in std_logic; - pci_lock : out std_logic; - pci_ad : out std_logic_vector(31 downto 0); - pci_cbe : out std_logic_vector(3 downto 0); - pci_frame : out std_logic; - pci_irdy : out std_logic; - pci_trdy : out std_logic; - pci_devsel : out std_logic; - pci_stop : out std_logic; - pci_perr : out std_logic; - pci_par : out std_logic; - pci_req : out std_logic; - pci_serr : out std_logic; - pci_host : in std_logic; - pci_66 : in std_logic; - pci_arb_req : in std_logic_vector(0 to 3); - pci_arb_gnt : out std_logic_vector(0 to 3); - spw_clk : in std_logic; - spw_rxd : in std_logic_vector(0 to 2); - spw_rxdn : in std_logic_vector(0 to 2); - spw_rxs : in std_logic_vector(0 to 2); - spw_rxsn : in std_logic_vector(0 to 2); - spw_txd : out std_logic_vector(0 to 2); - spw_txdn : out std_logic_vector(0 to 2); - spw_txs : out std_logic_vector(0 to 2); - spw_txsn : out std_logic_vector(0 to 2); - ramclk : out std_logic; - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; - tck : in std_logic; - tms : in std_logic; - tdi : in std_logic; - tdo : out std_logic; - clk49_152MHz : in std_logic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic); - END COMPONENT; - - - - --COMPONENT leon3mp - -- GENERIC ( - -- fabtech : INTEGER := CFG_FABTECH; - -- memtech : INTEGER := CFG_MEMTECH; - -- padtech : INTEGER := CFG_PADTECH; - -- clktech : INTEGER := CFG_CLKTECH; - -- disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - -- dbguart : INTEGER := CFG_DUART; -- Print UART on console - -- pclow : INTEGER := CFG_PCLOW - -- ); - -- PORT ( - -- resetn : IN STD_ULOGIC; - -- clk : IN STD_ULOGIC; - -- pllref : IN STD_ULOGIC; - -- errorn : OUT STD_ULOGIC; - -- address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - -- data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - -- dsutx : OUT STD_ULOGIC; -- DSU tx data - -- dsurx : IN STD_ULOGIC; -- DSU rx data - -- dsuen : IN STD_ULOGIC; - -- dsubre : IN STD_ULOGIC; - -- dsuact : OUT STD_ULOGIC; - -- txd1 : OUT STD_ULOGIC; -- UART1 tx data - -- rxd1 : IN STD_ULOGIC; -- UART1 rx data - -- txd2 : OUT STD_ULOGIC; -- UART1 tx data - -- rxd2 : IN STD_ULOGIC; -- UART1 rx datax - -- ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - -- ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - -- rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - -- oen : OUT STD_ULOGIC; - -- writen : OUT STD_ULOGIC; - -- read : OUT STD_ULOGIC; - -- iosn : OUT STD_ULOGIC; - -- romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - -- gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - - -- emddis : OUT STD_LOGIC; - -- epwrdwn : OUT STD_LOGIC; - -- ereset : OUT STD_LOGIC; - -- esleep : OUT STD_LOGIC; - -- epause : OUT STD_LOGIC; - - -- pci_rst : INOUT STD_LOGIC; -- PCI bus - -- pci_clk : IN STD_ULOGIC; - -- pci_gnt : IN STD_ULOGIC; - -- pci_idsel : IN STD_ULOGIC; - -- pci_lock : INOUT STD_ULOGIC; - -- pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - -- pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- pci_frame : INOUT STD_ULOGIC; - -- pci_irdy : INOUT STD_ULOGIC; - -- pci_trdy : INOUT STD_ULOGIC; - -- pci_devsel : INOUT STD_ULOGIC; - -- pci_stop : INOUT STD_ULOGIC; - -- pci_perr : INOUT STD_ULOGIC; - -- pci_par : INOUT STD_ULOGIC; - -- pci_req : INOUT STD_ULOGIC; - -- pci_serr : INOUT STD_ULOGIC; - -- pci_host : IN STD_ULOGIC; - -- pci_66 : IN STD_ULOGIC; - -- pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - -- pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - -- spw_clk : IN STD_ULOGIC; - -- spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - -- spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - -- spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - -- spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - -- spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - -- spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - -- spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - -- spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - -- ramclk : OUT STD_LOGIC; - - -- nBWa : OUT STD_LOGIC; - -- nBWb : OUT STD_LOGIC; - -- nBWc : OUT STD_LOGIC; - -- nBWd : OUT STD_LOGIC; - -- nBWE : OUT STD_LOGIC; - -- nADSC : OUT STD_LOGIC; - -- nADSP : OUT STD_LOGIC; - -- nADV : OUT STD_LOGIC; - -- nGW : OUT STD_LOGIC; - -- nCE1 : OUT STD_LOGIC; - -- CE2 : OUT STD_LOGIC; - -- nCE3 : OUT STD_LOGIC; - -- nOE : OUT STD_LOGIC; - -- MODE : OUT STD_LOGIC; - -- SSRAM_CLK : OUT STD_LOGIC; - -- ZZ : OUT STD_LOGIC; - - -- tck, tms, tdi : IN STD_ULOGIC; - -- tdo : OUT STD_ULOGIC; - -- -- waveform picker------ - -- clk49_152MHz : in std_ulogic; - -- sdo_adc : in std_logic_vector(7 downto 0); - -- cnv_ch1 : out std_logic; - -- sck_ch1 : out std_logic; - -- Bias_Fails : out std_logic - - - - -- ); - --END COMPONENT; - - COMPONENT CY7C1360C - GENERIC ( - addr_bits : INTEGER; - data_bits : INTEGER; - Cyp_tCO : TIME; - Cyp_tCYC : TIME; - Cyp_tCH : TIME; - Cyp_tCL : TIME; - Cyp_tCHZ : TIME; - Cyp_tCLZ : TIME; - Cyp_tOEHZ : TIME; - Cyp_tOELZ : TIME; - Cyp_tOEV : TIME; - Cyp_tAS : TIME; - Cyp_tADS : TIME; - Cyp_tADVS : TIME; - Cyp_tWES : TIME; - Cyp_tDS : TIME; - Cyp_tCES : TIME; - Cyp_tAH : TIME; - Cyp_tADH : TIME; - Cyp_tADVH : TIME; - Cyp_tWEH : TIME; - Cyp_tDH : TIME; - Cyp_tCEH : TIME); - PORT ( - iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) DOWNTO 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) DOWNTO 0); - iCLK : IN STD_LOGIC); - END COMPONENT; - - - SIGNAL clk : STD_LOGIC := '0'; - SIGNAL Rst : STD_LOGIC := '0'; -- Reset - CONSTANT ct : INTEGER := clkperiod/2; - - SIGNAL address : STD_LOGIC_VECTOR(27 DOWNTO 0); - SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL ioData : STD_LOGIC_VECTOR(35 DOWNTO 0); - - SIGNAL ramsn : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL ramoen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL rwen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL rwenx : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL romsn : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL iosn : STD_ULOGIC; - SIGNAL oen : STD_ULOGIC; - SIGNAL read : STD_ULOGIC; - SIGNAL writen : STD_ULOGIC; - SIGNAL brdyn : STD_ULOGIC; - SIGNAL bexcn : STD_ULOGIC; - SIGNAL wdog : STD_ULOGIC; - SIGNAL dsuen, dsutx, dsurx, dsubre, dsuact : STD_ULOGIC; - SIGNAL dsurst : STD_ULOGIC; - SIGNAL test : STD_ULOGIC; - SIGNAL error : STD_LOGIC; - SIGNAL gpio : STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); - SIGNAL GND : STD_ULOGIC := '0'; - SIGNAL VCC : STD_ULOGIC := '1'; - SIGNAL NC : STD_ULOGIC := 'Z'; - SIGNAL clk2 : STD_ULOGIC := '1'; - - SIGNAL sdcke : STD_LOGIC_VECTOR (1 DOWNTO 0); -- clk en - SIGNAL sdcsn : STD_LOGIC_VECTOR (1 DOWNTO 0); -- chip sel - SIGNAL sdwen : STD_ULOGIC; -- write en - SIGNAL sdrasn : STD_ULOGIC; -- row addr stb - SIGNAL sdcasn : STD_ULOGIC; -- col addr stb - SIGNAL sddqm : STD_LOGIC_VECTOR (7 DOWNTO 0); -- data i/o mask - SIGNAL sdclk : STD_ULOGIC; - SIGNAL plllock : STD_ULOGIC; - SIGNAL txd1, rxd1 : STD_ULOGIC; - SIGNAL txd2, rxd2 : STD_ULOGIC; - - SIGNAL etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : STD_LOGIC := '0'; - SIGNAL erxd, etxd : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); - SIGNAL erxdt, etxdt : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); - SIGNAL emdc : STD_LOGIC; - SIGNAL gtx_clk : STD_ULOGIC; - - SIGNAL emddis : STD_LOGIC; - SIGNAL epwrdwn : STD_LOGIC; - SIGNAL ereset : STD_LOGIC; - SIGNAL esleep : STD_LOGIC; - SIGNAL epause : STD_LOGIC; - - CONSTANT lresp : BOOLEAN := false; - - SIGNAL sa : STD_LOGIC_VECTOR(14 DOWNTO 0); - SIGNAL sd : STD_LOGIC_VECTOR(63 DOWNTO 0); - - SIGNAL pci_arb_req, pci_arb_gnt : STD_LOGIC_VECTOR(0 TO 3); - - - SIGNAL spw_clk : STD_ULOGIC := '0'; - SIGNAL spw_rxd : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxdn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxs : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxsn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_txd : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txdn : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txs : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txsn : STD_LOGIC_VECTOR(0 TO 2); - - SIGNAL tck, tms, tdi, tdo : STD_ULOGIC; - - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - CONSTANT CFG_SD64 : INTEGER := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64; - - ----------------------------------------------------------------------------- - - SIGNAL ramclk : STD_LOGIC; - - SIGNAL nBWa : STD_LOGIC; - SIGNAL nBWb : STD_LOGIC; - SIGNAL nBWc : STD_LOGIC; - SIGNAL nBWd : STD_LOGIC; - SIGNAL nBWE : STD_LOGIC; - SIGNAL nADSC : STD_LOGIC; - SIGNAL nADSP : STD_LOGIC; - SIGNAL nADV : STD_LOGIC; - SIGNAL nGW : STD_LOGIC; - SIGNAL nCE1 : STD_LOGIC; - SIGNAL CE2 : STD_LOGIC; - SIGNAL nCE3 : STD_LOGIC; - SIGNAL nOE : STD_LOGIC; - SIGNAL MODE : STD_LOGIC; - SIGNAL SSRAM_CLK : STD_LOGIC; - SIGNAL ZZ : STD_LOGIC; - - -- - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - - SIGNAL clk49_152MHz : STD_LOGIC := '0'; - SIGNAL sdo_adc : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL cnv_ch1 : STD_LOGIC; - SIGNAL sck_ch1 : STD_LOGIC; - SIGNAL Bias_Fails : STD_LOGIC; - -BEGIN - --- clock and reset - - spw_clk <= NOT spw_clk AFTER 20 ns; - spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0); - spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0); - spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1); - spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1); - spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2); - spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2); - clk <= NOT clk AFTER ct * 1 ns; - clk49_152MHz <= NOT clk49_152MHz AFTER 203 * 100 ps; - rst <= dsurst; - dsuen <= '1'; dsubre <= '0'; rxd1 <= '1'; - - --d3 : leon3mp - -- GENERIC MAP (fabtech, - -- memtech, - -- padtech, - -- clktech, - -- disas, - -- dbguart, - -- pclow) - -- PORT MAP (rst, clk, sdclk, error, address(27 DOWNTO 0), data, - -- dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2, - -- ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio, - - -- emddis, epwrdwn, ereset, esleep, epause, - -- pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - -- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par, - -- pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt, - -- spw_clk, spw_rxd, spw_rxdn, spw_rxs, - -- spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, - - - -- ramclk , - -- nBWa , - -- nBWb , - -- nBWc , - -- nBWd , - -- nBWE , - -- nADSC , - -- nADSP , - -- nADV , - -- nGW , - -- nCE1 , - -- CE2 , - -- nCE3 , - -- nOE , - -- MODE , - -- SSRAM_CLK , - -- ZZ , - - -- tck, tms, tdi, tdo, - -- clk49_152MHz, - -- sdo_adc , - -- cnv_ch1 , - -- sck_ch1 , - -- Bias_Fails); - - - leon3mp_wfp_1: ENTITY work.leon3mp_wfp - PORT MAP ( - resetn => rst, - clk => clk, - pllref => sdclk, - errorn => error, - address => address(27 DOWNTO 0), - data => data(31 DOWNTO 0), - dsutx => dsutx, - dsurx => dsurx, - dsuen => dsuen, - dsubre => dsubre, - dsuact => dsuact, - txd1 => txd1, - rxd1 => rxd1, - txd2 => txd2, - rxd2 => rxd2, - ramsn => ramsn, - ramoen => ramoen, - rwen => rwen, - oen => oen, - writen => writen, - read => read, - iosn => iosn, - romsn => romsn, - gpio => gpio, - emddis => emddis, - epwrdwn => epwrdwn, - ereset => ereset, - esleep => esleep, - epause => epause, - - pci_rst => pci_rst, - pci_clk => pci_clk, - pci_gnt => pci_gnt, - pci_idsel => pci_idsel, - pci_lock => pci_lock, - pci_ad => pci_ad, - pci_cbe => pci_cbe, - pci_frame => pci_frame, - pci_irdy => pci_irdy, - pci_trdy => pci_trdy, - pci_devsel => pci_devsel, - pci_stop => pci_stop, - pci_perr => pci_perr, - pci_par => pci_par, - pci_req => pci_req, - pci_serr => pci_serr, - pci_host => pci_host, - pci_66 => pci_66, - pci_arb_req => pci_arb_req, - pci_arb_gnt => pci_arb_gnt, - spw_clk => spw_clk, - spw_rxd => spw_rxd, - spw_rxdn => spw_rxdn, - spw_rxs => spw_rxs, - spw_rxsn => spw_rxsn, - spw_txd => spw_txd, - spw_txdn => spw_txdn, - spw_txs => spw_txs, - spw_txsn => spw_txsn, - - ramclk => ramclk, - nBWa => nBWa, - nBWb => nBWb, - nBWc => nBWc, - nBWd => nBWd, - nBWE => nBWE, - nADSC => nADSC, - nADSP => nADSP, - nADV => nADV, - nGW => nGW, - nCE1 => nCE1, - CE2 => CE2, - nCE3 => nCE3, - nOE => nOE, - MODE => MODE, - SSRAM_CLK => SSRAM_CLK, - ZZ => ZZ, - - tck => tck, - tms => tms, - tdi => tdi, - tdo => tdo, - - clk49_152MHz => clk49_152MHz, - sdo_adc => sdo_adc, - cnv_ch1 => cnv_ch1, - sck_ch1 => sck_ch1, - Bias_Fails => Bias_Fails); - - -- component instantiation - ----------------------------------------------------------------------------- - - MODULE_ADS7886 : FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => '1', - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => '1', - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc(7)); - - - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - - prom0 : FOR i IN 0 TO (romwidth/8)-1 GENERATE - sr0 : sram GENERIC MAP (index => i, abits => romdepth, fname => promfile) - PORT MAP (address(romdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), romsn(0), - rwen(i), oen); - END GENERATE; - - ----------------------------------------------------------------------------- - CY7C1360C_2 : CY7C1360C - GENERIC MAP ( - - - addr_bits => 19, - data_bits => 36, - - Cyp_tCO => 3.5 ns, -- Data Output Valid After CLK Rise - Cyp_tCYC => 6.0 ns, -- Clock cycle time - Cyp_tCH => 2.4 ns, -- Clock HIGH time - Cyp_tCL => 2.4 ns, -- Clock LOW time - Cyp_tCHZ => 3.5 ns, -- Clock to High-Z - Cyp_tCLZ => 1.25 ns, -- Clock to Low-Z - Cyp_tOEHZ => 3.5 ns, -- OE# HIGH to Output High-Z - Cyp_tOELZ => 0.0 ns, -- OE# LOW to Output Low-Z - Cyp_tOEV => 3.5 ns, -- OE# LOW to Output Valid - Cyp_tAS => 1.5 ns, -- Address Set-up Before CLK Rise - Cyp_tADS => 1.5 ns, -- ADSC#, ADSP# Set-up Before CLK Rise - Cyp_tADVS => 1.5 ns, -- ADV# Set-up Before CLK Rise - Cyp_tWES => 1.5 ns, -- BWx#, GW#, BWE# Set-up Before CLK Rise - Cyp_tDS => 1.5 ns, -- Data Input Set-up Before CLK Rise - Cyp_tCES => 1.5 ns, -- Chip Enable Set-up - Cyp_tAH => 0.5 ns, -- Address Hold After CLK Rise - Cyp_tADH => 0.5 ns, -- ADSC#, ADSP# Hold After CLK Rise - Cyp_tADVH => 0.5 ns, -- ADV# Hold After CLK Rise - Cyp_tWEH => 0.5 ns, -- BWx#, GW#, BWE# Hold After CLK Rise - Cyp_tDH => 0.5 ns, -- Data Input Hold After CLK Rise - Cyp_tCEH => 0.5 ns -- Chip Enable Hold After CLK Rise - - - --Cyp_tCO => 2.8 ns, - --Cyp_tCYC => 4.0 ns, - --Cyp_tCH => 1.8 ns, - --Cyp_tCL => 1.8 ns, - --Cyp_tCHZ => 2.8 ns, - --Cyp_tCLZ => 1.25 ns, - --Cyp_tOEHZ => 2.8 ns, - --Cyp_tOELZ => 0.0 ns, - --Cyp_tOEV => 2.8 ns, - --Cyp_tAS => 1.4 ns, - --Cyp_tADS => 1.4 ns, - --Cyp_tADVS => 1.4 ns, - --Cyp_tWES => 1.4 ns, - --Cyp_tDS => 1.4 ns, - --Cyp_tCES => 1.4 ns, - --Cyp_tAH => 0.4 ns, - --Cyp_tADH => 0.4 ns, - --Cyp_tADVH => 0.4 ns, - --Cyp_tWEH => 0.4 ns, - --Cyp_tDH => 0.4 ns, - --Cyp_tCEH => 0.4 ns - ) - PORT MAP ( - iZZ => ZZ, - iMode => MODE, - iADDR => address(20 DOWNTO 2), - inGW => nGW, - inBWE => nBWE, - inBWd => nBWd, - inBWc => nBWc, - inBWb => nBWb, - inBWa => nBWa, - inCE1 => nCE1, - iCE2 => CE2, - inCE3 => nCE3, - inADSP => nADSP, - inADSC => nADSC, - inADV => nADV, - inOE => nOE, - ioDQ => ioData, -- - iCLK => SSRAM_CLK); -- ?? - - - ioData <= "0" & data(31 DOWNTO 24) & - "0" & data(23 DOWNTO 16) & - "0" & data(15 DOWNTO 8) & - "0" & data(7 DOWNTO 0); - - --sbanks : FOR k IN 0 TO srambanks-1 GENERATE - -- sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE - -- sr0 : sram GENERIC MAP (index => i, abits => sramdepth, fname => sramfile) - -- PORT MAP (address(sramdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), - -- ramsn(k), rwen(i), ramoen(k)); - -- END GENERATE; - --END GENERATE; - - error <= 'H'; -- ERROR pull-up - - iuerr : PROCESS - BEGIN - WAIT FOR 2500 ns; - IF to_x01(error) = '1' THEN WAIT ON error; END IF; - ASSERT (to_x01(error) = '1') - REPORT "*** IU in error mode, simulation halted ***" - SEVERITY failure; - END PROCESS; - - data <= buskeep(data), (OTHERS => 'H') AFTER 250 ns; - sd <= buskeep(sd), (OTHERS => 'H') AFTER 250 ns; - - test0 : grtestmod - PORT MAP (rst, clk, error, address(21 DOWNTO 2), data, iosn, oen, writen, brdyn); - - - dsucom : PROCESS - PROCEDURE dsucfg(SIGNAL dsurx : IN STD_ULOGIC; SIGNAL dsutx : OUT STD_ULOGIC) IS - VARIABLE w32 : STD_LOGIC_VECTOR(31 DOWNTO 0); - VARIABLE c8 : STD_LOGIC_VECTOR(7 DOWNTO 0); - CONSTANT txp : TIME := 160 * 1 ns; - BEGIN - dsutx <= '1'; - dsurst <= '0'; - WAIT FOR 500 ns; - dsurst <= '1'; - WAIT; - WAIT FOR 5000 ns; - END; - BEGIN - - dsucfg(dsutx, dsurx); - WAIT; - - END PROCESS; - -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/CY7C1360C.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/CY7C1360C.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/CY7C1360C.vhd +++ /dev/null @@ -1,561 +0,0 @@ ---*************************************************************************************** --- --- File Name: CY7C1360C.vhd --- Version: 1.0 --- Date: Aug 8th, 2005 --- Model: BUS Functional --- Simulator: Modelsim --- --- --- Queries: MPD Applications --- Website: www.cypress.com/support --- Company: Cypress Semiconductor --- Part #: CY7C1360C (256K x 36) --- --- Description: Cypress 9Mb Synburst SRAM (Pipelined SCD) --- --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright(c) Cypress Semiconductor, 2004 --- All rights reserved --- --- Rev Date Changes --- --- ---------- --------------------------------------- --- 1.0 12/22/2004 - New Model --- - New Test Bench --- - New Test Vectors --- ---*************************************************************************************** - --- Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz - -LIBRARY ieee,work; - USE ieee.std_logic_1164.all; - USE ieee.std_logic_unsigned.all; - Use IEEE.Std_Logic_Arith.all; - USE work.package_utility.all; - -entity CY7C1360C is - GENERIC ( - -- Constant Parameters - addr_bits : INTEGER := 18; -- This is external address - data_bits : INTEGER := 36; - - ---Clock timings for 250Mhz - Cyp_tCO : TIME := 2.8 ns; -- Data Output Valid After CLK Rise - - Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time - Cyp_tCH : TIME := 1.8 ns; -- Clock HIGH time - Cyp_tCL : TIME := 1.8 ns; -- Clock LOW time - - Cyp_tCHZ : TIME := 2.8 ns; -- Clock to High-Z - Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z - Cyp_tOEHZ: TIME := 2.8 ns; -- OE# HIGH to Output High-Z - Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z - Cyp_tOEV : TIME := 2.8 ns; -- OE# LOW to Output Valid - - Cyp_tAS : TIME := 1.4 ns; -- Address Set-up Before CLK Rise - Cyp_tADS : TIME := 1.4 ns; -- ADSC#, ADSP# Set-up Before CLK Rise - Cyp_tADVS: TIME := 1.4 ns; -- ADV# Set-up Before CLK Rise - Cyp_tWES : TIME := 1.4 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise - Cyp_tDS : TIME := 1.4 ns; -- Data Input Set-up Before CLK Rise - Cyp_tCES : TIME := 1.4 ns; -- Chip Enable Set-up - - Cyp_tAH : TIME := 0.4 ns; -- Address Hold After CLK Rise - Cyp_tADH : TIME := 0.4 ns; -- ADSC#, ADSP# Hold After CLK Rise - Cyp_tADVH: TIME := 0.4 ns; -- ADV# Hold After CLK Rise - Cyp_tWEH : TIME := 0.4 ns; -- BWx#, GW#, BWE# Hold After CLK Rise - Cyp_tDH : TIME := 0.4 ns; -- Data Input Hold After CLK Rise - Cyp_tCEH : TIME := 0.4 ns -- Chip Enable Hold After CLK Rise - ---Clock timings for 200Mhz --- Cyp_tCO : TIME := 3.0 ns; -- Data Output Valid After CLK Rise - --- Cyp_tCYC : TIME := 5.0 ns; -- Clock cycle time --- Cyp_tCH : TIME := 2.0 ns; -- Clock HIGH time --- Cyp_tCL : TIME := 2.0 ns; -- Clock LOW time - --- Cyp_tCHZ : TIME := 3.0 ns; -- Clock to High-Z --- Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z --- Cyp_tOEHZ: TIME := 3.0 ns; -- OE# HIGH to Output High-Z --- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z --- Cyp_tOEV : TIME := 3.0 ns; -- OE# LOW to Output Valid - --- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise --- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise --- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise --- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise --- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise --- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up - --- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise --- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise --- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise --- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise --- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise --- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise - ---Clock timings for 166Mhz --- Cyp_tCO : TIME := 3.5 ns; -- Data Output Valid After CLK Rise - --- Cyp_tCYC : TIME := 6.0 ns; -- Clock cycle time --- Cyp_tCH : TIME := 2.4 ns; -- Clock HIGH time --- Cyp_tCL : TIME := 2.4 ns; -- Clock LOW time - --- Cyp_tCHZ : TIME := 3.5 ns; -- Clock to High-Z --- Cyp_tCLZ : TIME := 1.25 ns; -- Clock to Low-Z --- Cyp_tOEHZ: TIME := 3.5 ns; -- OE# HIGH to Output High-Z --- Cyp_tOELZ: TIME := 0.0 ns; -- OE# LOW to Output Low-Z --- Cyp_tOEV : TIME := 3.5 ns; -- OE# LOW to Output Valid - --- Cyp_tAS : TIME := 1.5 ns; -- Address Set-up Before CLK Rise --- Cyp_tADS : TIME := 1.5 ns; -- ADSC#, ADSP# Set-up Before CLK Rise --- Cyp_tADVS: TIME := 1.5 ns; -- ADV# Set-up Before CLK Rise --- Cyp_tWES : TIME := 1.5 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise --- Cyp_tDS : TIME := 1.5 ns; -- Data Input Set-up Before CLK Rise --- Cyp_tCES : TIME := 1.5 ns; -- Chip Enable Set-up - --- Cyp_tAH : TIME := 0.5 ns; -- Address Hold After CLK Rise --- Cyp_tADH : TIME := 0.5 ns; -- ADSC#, ADSP# Hold After CLK Rise --- Cyp_tADVH: TIME := 0.5 ns; -- ADV# Hold After CLK Rise --- Cyp_tWEH : TIME := 0.5 ns; -- BWx#, GW#, BWE# Hold After CLK Rise --- Cyp_tDH : TIME := 0.5 ns; -- Data Input Hold After CLK Rise --- Cyp_tCEH : TIME := 0.5 ns -- Chip Enable Hold After CLK Rise - - ); - PORT (iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0); - iCLK : IN STD_LOGIC); - -end CY7C1360C; -ARCHITECTURE CY7C1360C_arch OF CY7C1360C IS - - - - signal Read_reg_o1, Read_reg1 : STD_LOGIC; - signal WrN_reg1 : STD_LOGIC; - signal ADSP_N_o : STD_LOGIC; - signal pipe_reg1, ce_reg1,pcsr_write1, ctlr_write1 : STD_LOGIC; - signal Sys_clk : STD_LOGIC := '0'; - signal test : STD_LOGIC; - signal dout, din1 : STD_LOGIC_VECTOR (data_bits-1 downto 0); - signal ce : STD_LOGIC; - signal Write_n : STD_LOGIC; - signal Read : STD_LOGIC; - - signal bwa_n1 : STD_LOGIC; - signal bwb_n1 : STD_LOGIC; - signal bwc_n1 : STD_LOGIC; - signal bwd_n1 : STD_LOGIC; - - signal latch_addr : STD_LOGIC; - signal addr_reg_read1,addr_reg_write1,addr_reg_in1 : STD_LOGIC_VECTOR (addr_bits-1 downto 0); - - signal OeN_HZ : STD_LOGIC; - signal OeN_DataValid : STD_LOGIC; - signal OeN_efct : STD_LOGIC; - - signal WR_HZ : STD_LOGIC; - signal WR_LZ : STD_LOGIC; - signal WR_efct : STD_LOGIC; - - signal CE_HZ : STD_LOGIC; - signal CE_LZ : STD_LOGIC; - signal Pipe_efct : STD_LOGIC; - - signal RD_HZ : STD_LOGIC; - signal RD_LZ : STD_LOGIC; - signal RD_efct : STD_LOGIC; - -begin - - ce <= ((not inCE1) and (iCE2) and (not inCE3)); - Write_n <= not((((not inBWa) OR (not inBWb) OR (not inBWc) OR (not inBWd)) AND (not inBWE)) OR (not inGW)); - Read <= (((inBWa AND inBWb AND inBWc AND inBWd) AND (not inBWE)) OR (inGW AND inBWE) OR (( not inADSP) AND ce)); - bwa_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWa)))); - bwb_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWb)))); - bwc_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWc)))); - bwd_n1 <= not((not Write_n) AND ((not inGW) OR ((not inBWE) AND (not inBWd)))); - latch_addr <= ((not inADSC) OR ((not inADSP) AND (not inCE1))); - OeN_efct <= OeN_DataValid when (inOE = '0') else OeN_HZ; - WR_efct <= WR_LZ when (WrN_reg1 = '0') else WR_HZ; - Pipe_efct <= CE_LZ when ((ce_reg1 = '1') and (pipe_reg1 = '1')) else CE_HZ; - RD_efct <= CE_LZ when (Read_reg_o1 = '1') else CE_HZ ; - - - Process (Read_reg_o1) - begin - if (Read_reg_o1 = '0') then - RD_HZ <= '0' after Cyp_tCHZ; - RD_LZ <= '0' after Cyp_tCLZ; - elsif (Read_reg_o1 = '1') then - RD_HZ <= '1' after Cyp_tCHZ; - RD_LZ <= '1' after Cyp_tCLZ; - else - RD_HZ <= 'X' after Cyp_tCHZ; - RD_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - - - Process (pipe_reg1) - begin - if (pipe_reg1 = '1') then - CE_LZ <= '1' after Cyp_tCLZ; - elsif (pipe_reg1 = '0') then - CE_LZ <= '0' after Cyp_tCLZ; - else - CE_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - -- System Clock Decode - Process (iclk) - variable Sys_clk1 : std_logic := '0'; - begin - if (rising_edge (iclk)) then - Sys_clk1 := not iZZ; - end if; - if (falling_edge (iCLK)) then - Sys_clk1 := '0'; - end if; - Sys_clk <= Sys_clk1; - end process; - - - - Process (WrN_reg1) - begin - if (WrN_reg1 = '1') then - WR_HZ <= '1' after Cyp_tCHZ; - WR_LZ <= '1' after Cyp_tCLZ; - elsif (WrN_reg1 = '0') then - WR_HZ <= '0' after Cyp_tCHZ; - WR_LZ <= '0' after Cyp_tCLZ; - else - WR_HZ <= 'X' after Cyp_tCHZ; - WR_LZ <= 'X' after Cyp_tCLZ; - end if; - end process; - - Process (inOE) - begin - if (inOE = '1') then - OeN_HZ <= '1' after Cyp_tOEHZ; - OeN_DataValid <= '1' after Cyp_tOEV; - elsif (inOE = '0') then - OeN_HZ <= '0' after Cyp_tOEHZ; - OeN_DataValid <= '0' after Cyp_tOEV; - else - OeN_HZ <= 'X' after Cyp_tOEHZ; - OeN_DataValid <= 'X' after Cyp_tOEV; - end if; - end process; - - process (ce_reg1, pipe_reg1) - begin - if ((ce_reg1 = '0') or (pipe_reg1 = '0')) then - CE_HZ <= '0' after Cyp_tCHZ; - elsif ((ce_reg1 = '1') and (pipe_reg1 = '1')) then - CE_HZ <= '1' after Cyp_tCHZ; - else - CE_HZ <= 'X' after Cyp_tCHZ; - end if; - end process; - - Process (Sys_clk) - TYPE memory_array IS ARRAY ((2**addr_bits -1) DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits/4) - 1 DOWNTO 0); - variable Read_reg_o : std_logic; - variable Read_reg : std_logic; - variable pcsr_write, ctlr_write : std_logic; - variable WrN_reg : std_logic; - variable latch_addr_old, latch_addr_current : std_logic; - variable addr_reg_in, addr_reg_read, addr_reg_write : std_logic_vector (addr_bits -1 downto 0) := (others => '0'); - variable bcount, first_addr : std_logic_vector (1 downto 0) := "00"; - variable bwa_reg,bwb_reg,bwc_reg,bwd_reg, pipe_reg, ce_reg : std_logic; - variable din : std_logic_vector (data_bits-1 downto 0); - variable first_addr_int : integer; - variable bank0 : memory_array; - variable bank1 : memory_array; - variable bank2 : memory_array; - variable bank3 : memory_array; - - begin - if rising_edge (Sys_clk) then - - if (Write_n = '0') then - Read_reg_o := '0'; - else - Read_reg_o := Read_reg; - end if; - - if (Write_n = '0') then - Read_reg := '0'; - else - Read_reg := Read; - end if; - Read_reg1 <= Read_reg; - Read_reg_o1 <= Read_reg_o; - - if (Read_reg = '1') then - pcsr_write := '0'; - ctlr_write := '0'; - end if; - - -- Write Register - - if (Read_reg_o = '1') then - WrN_reg := '1'; - else - WrN_reg := Write_n; - end if; - WrN_reg1 <= WrN_reg; - - latch_addr_old := latch_addr_current; - latch_addr_current := latch_addr; - - if (latch_addr_old = '1' and (Write_n = '0') and ADSP_N_o = '0') then - pcsr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1; - - elsif (latch_addr_current = '1' and (Write_n = '0') and inADSP = '1' and inADSC = '0') then - ctlr_write := '1'; --Ctlr Write = 0; Pcsr Write = 1; - end if; - -- ADDRess Register - if (latch_addr = '1') then - addr_reg_in := iADDR; - bcount := iADDR (1 downto 0); - first_addr := iADDR (1 downto 0); - end if; - addr_reg_in1 <= addr_reg_in; - -- ADSP_N Previous-Cycle Register - ADSP_N_o <= inADSP; - pcsr_write1 <= pcsr_write; - ctlr_write1 <= ctlr_write; - first_addr_int := CONV_INTEGER1 (first_addr); - -- Binary Counter and Logic - - if ((iMode = '0') and (inADV = '0') and (latch_addr = '0')) then -- Linear Burst - bcount := (bcount + '1'); -- Advance Counter - - elsif ((iMode = '1') and (inADV = '0') and (latch_addr = '0')) then -- Interleaved Burst - if ((first_addr_int REM 2) = 0) then - bcount := (bcount + '1'); -- Increment Counter - elsif ((first_addr_int REM 2) = 1) then - bcount := (bcount - '1'); -- Decrement Counter - end if; - end if; - - -- Read ADDRess - addr_reg_read := addr_reg_write; - addr_reg_read1 <= addr_reg_read; - - -- Write ADDRess - addr_reg_write := addr_reg_in ((addr_bits - 1) downto 2) & bcount(1) & bcount(0); - addr_reg_write1 <= addr_reg_write; - -- Byte Write Register - bwa_reg := not bwa_n1; - bwb_reg := not bwb_n1; - bwc_reg := not bwc_n1; - bwd_reg := not bwd_n1; - - -- Enable Register - pipe_reg := ce_reg; - - -- Enable Register - if (latch_addr = '1') then - ce_reg := ce; - end if; - - pipe_reg1 <= pipe_reg; - ce_reg1 <= ce_reg; - - -- Input Register - if ((ce_reg = '1') and ((bwa_n1 ='0') or (bwb_n1 = '0') or (bwc_n1 = '0') or (bwd_n1 = '0')) and - ((pcsr_write = '1') or (ctlr_write = '1'))) then - din := ioDQ; - end if; - din1 <= din; - - -- Byte Write Driver - if ((ce_reg = '1') and (bwa_reg = '1')) then - bank0 (CONV_INTEGER1 (addr_reg_write)) := din (8 downto 0); - end if; - if ((ce_reg = '1') and (bwb_reg = '1')) then - bank1 (CONV_INTEGER1 (addr_reg_write)) := din (17 downto 9); - end if; - if ((ce_reg = '1') and (bwc_reg = '1')) then - bank2 (CONV_INTEGER1 (addr_reg_write)) := din (26 downto 18); - end if; - if ((ce_reg = '1') and (bwd_reg = '1')) then - bank3 (CONV_INTEGER1 (addr_reg_write)) := din (35 downto 27); - end if; - - -- Output Registers - - if ((Write_n = '0') or (pipe_reg = '0')) then - dout (35 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after Cyp_tCHZ; - elsif (Read_reg_o = '1') then - dout ( 8 downto 0) <= bank0 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (17 downto 9) <= bank1 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (26 downto 18) <= bank2 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - dout (35 downto 27) <= bank3 (CONV_INTEGER1 (addr_reg_read)) after Cyp_tCO; - end if; - - end if; - end process; - - -- Output Buffers - ioDQ <= dout when ((inOE ='0') and (iZZ='0') and (Pipe_efct='1') and (RD_efct='1') and (WR_efct='1')) - else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; - - - clk_check : PROCESS - VARIABLE clk_high, clk_low : TIME := 0 ns; - BEGIN - WAIT ON iClk; - IF iClk = '1' AND NOW >= Cyp_tCYC THEN - ASSERT (NOW - clk_low >= Cyp_tCH) - REPORT "Clk width low - tCH violation" - SEVERITY ERROR; - ASSERT (NOW - clk_high >= Cyp_tCYC) - REPORT "Clk period high - tCYC violation" - SEVERITY ERROR; - clk_high := NOW; - ELSIF iClk = '0' AND NOW /= 0 ns THEN - ASSERT (NOW - clk_high >= Cyp_tCL) - REPORT "Clk width high - tCL violation" - SEVERITY ERROR; - ASSERT (NOW - clk_low >= Cyp_tCYC) - REPORT "Clk period low - tCYC violation" - SEVERITY ERROR; - clk_low := NOW; - END IF; - END PROCESS; - - -- Check for Setup Timing Violation - setup_check : PROCESS - BEGIN - WAIT ON iClk; - IF iClk = '1' THEN - ASSERT (iAddr'LAST_EVENT >= Cyp_tAS) - REPORT "Addr - tAS violation" - SEVERITY ERROR; - ASSERT (inGW'LAST_EVENT >= Cyp_tWES) - REPORT "GW# - tWES violation" - SEVERITY ERROR; - ASSERT (inBWE'LAST_EVENT >= Cyp_tWES) - REPORT "BWE# - tWES violation" - SEVERITY ERROR; - ASSERT (inCe1'LAST_EVENT >= Cyp_tWES) - REPORT "CE1# - tWES violation" - SEVERITY ERROR; - ASSERT (iCe2'LAST_EVENT >= Cyp_tWES) - REPORT "CE2 - tWES violation" - SEVERITY ERROR; - ASSERT (inCe3'LAST_EVENT >= Cyp_tWES) - REPORT "CE3# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdv'LAST_EVENT >= Cyp_tADVS) - REPORT "ADV# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdsp'LAST_EVENT >= Cyp_tADVS) - REPORT "ADSP# - tWES violation" - SEVERITY ERROR; - ASSERT (inAdsc'LAST_EVENT >= Cyp_tADVS) - REPORT "ADSC# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwa'LAST_EVENT >= Cyp_tWES) - REPORT "BWa# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwb'LAST_EVENT >= Cyp_tWES) - REPORT "BWb# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwc'LAST_EVENT >= Cyp_tWES) - REPORT "BWc# - tWES violation" - SEVERITY ERROR; - ASSERT (inBwd'LAST_EVENT >= Cyp_tWES) - REPORT "BWd# - tWES violation" - SEVERITY ERROR; - ASSERT (ioDq'LAST_EVENT >= Cyp_tDS) - REPORT "Dq - tDS violation" - SEVERITY ERROR; - END IF; - END PROCESS; - - -- Check for Hold Timing Violation - hold_check : PROCESS - BEGIN - WAIT ON iClk'DELAYED(Cyp_tAH), iClk'DELAYED(Cyp_tWEH), iClk'DELAYED(Cyp_tDH); - IF iClk'DELAYED(Cyp_tAH) = '1' THEN - ASSERT (iAddr'LAST_EVENT > Cyp_tAH) - REPORT "Addr - tAH violation" - SEVERITY ERROR; - END IF; - IF iClk'DELAYED(Cyp_tDH) = '1' THEN - ASSERT (ioDq'LAST_EVENT > Cyp_tDH) - REPORT "Dq - tDH violation" - SEVERITY ERROR; - END IF; - IF iClk'DELAYED(Cyp_tWEH) = '1' THEN - ASSERT (inCe1'LAST_EVENT > Cyp_tWEH) - REPORT "CE1# - tWEH violation" - SEVERITY ERROR; - ASSERT (iCe2'LAST_EVENT > Cyp_tWEH) - REPORT "CE2 - tWEH violation" - SEVERITY ERROR; - ASSERT (inCe3'LAST_EVENT > Cyp_tWEH) - REPORT "CE3 - tWEH violation" - SEVERITY ERROR; - ASSERT (inAdv'LAST_EVENT > Cyp_tWEH) - REPORT "ADV# - tWEH violation" - SEVERITY ERROR; - ASSERT (inADSP'LAST_EVENT > Cyp_tWEH) - REPORT "ADSP# - tWEH violation" - SEVERITY ERROR; - ASSERT (inADSC'LAST_EVENT > Cyp_tWEH) - REPORT "ADSC# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwa'LAST_EVENT > Cyp_tWEH) - REPORT "BWa# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwb'LAST_EVENT > Cyp_tWEH) - REPORT "BWb# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwc'LAST_EVENT > Cyp_tWEH) - REPORT "BWc# - tWEH violation" - SEVERITY ERROR; - ASSERT (inBwd'LAST_EVENT > Cyp_tWEH) - REPORT "BWd# - tWEH violation" - SEVERITY ERROR; - END IF; - - END PROCESS; -end CY7C1360C_arch; - - - - - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/package_utility.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/package_utility.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/package_utility.vhd +++ /dev/null @@ -1,73 +0,0 @@ ---**************************************************************** ---** MODEL : package_utility ** ---** COMPANY : Cypress Semiconductor ** ---** REVISION: 1.0 Created new package utility model ** ---** ** ---**************************************************************** -Library ieee,work; - Use ieee.std_logic_1164.all; - Use IEEE.Std_Logic_Arith.all; - Use IEEE.std_logic_TextIO.all; - --- Use work.package_timing.all; - -Library Std; - Use STD.TextIO.all; - -Package package_utility is - -FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR; -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER; - -End; -- package package_utility - -Package body package_utility is - - ------------------------------------------------------------------------------------------------- ---Converts string into std_logic_vector ------------------------------------------------------------------------------------------------- - -FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS - VARIABLE result : STD_LOGIC_VECTOR(S'RANGE); - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '0' THEN - result(i) := '0'; - ELSIF S(i) = '1' THEN - result(i) := '1'; - ELSIF S(i) = 'X' THEN - result(i) := 'X'; - ELSE - result(i) := 'Z'; - END IF; - END LOOP; - RETURN result; -END convert_string; - ------------------------------------------------------------------------------------------------- ---Converts std_logic_vector into integer ------------------------------------------------------------------------------------------------- - -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS - VARIABLE result : INTEGER := 0; - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '1' THEN - result := result + (2**i); - ELSIF S(i) = '0' THEN - result := result; - ELSE - result := 0; - END IF; - END LOOP; - RETURN result; - END CONV_INTEGER1; - - - - -end package_utility; - - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/tb.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/tb.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/CY7C1360C/tb.vhd +++ /dev/null @@ -1,369 +0,0 @@ ---*************************************************************************************** --- --- File Name: tb.vhd --- Version: 1.0 --- Date: Aug 8th, 2005 --- Simulator: Modelsim --- --- --- Queries: MPD Applications --- Website: www.cypress.com/support --- Company: Cypress Semiconductor --- Part #: testbench for CY7C1360C (256K x 36) --- --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright(c) Cypress Semiconductor, 2004 --- All rights reserved --- --- Rev Date Changes --- --- ---------- --------------------------------------- --- 1.0 12/22/2004 - New Model --- - New Test Bench --- - New Test Vectors --- ---*************************************************************************************** - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE std.textio.ALL; -USE ieee.std_logic_textio.ALL; - - -ENTITY tb IS -END tb; - -architecture tb_arch of tb is - - CONSTANT addr_bits : INTEGER := 18; - CONSTANT data_bits : INTEGER := 36; - - CONSTANT tx01 : TIME := 2.2 ns; -- 0.0 ns to 1.8 ns - - - COMPONENT CY7C1360C - PORT (iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0); - iCLK : IN STD_LOGIC); - END COMPONENT; - --------------------------------------------------------------------------- --- Function: to_slv --- --- Description: Converts string to std_logic_vector --------------------------------------------------------------------------- -function to_slv(value : in string) return std_logic_vector is -variable outvec : std_logic_vector(value'length -1 downto 0); -variable i : integer; -variable temp : character; -begin - for i in 1 to value'length loop - - temp := value(i); - - case temp is - when '0' => outvec(i-1) := '0'; - when '1' => outvec(i-1) := '1'; - when 'X' => outvec(i-1) := 'X'; - when 'Z' => outvec(i-1) := 'Z'; - when others => - assert false report "Illegal characters" severity note; - - end case; - end loop; - return outvec; -end to_slv; - --------------------------------------------------------------------------- --- Function: to_slv_char --- --- Description: Converts character to std_logic_vector --------------------------------------------------------------------------- -function to_slv_char(value : in character) return std_logic is -variable outvec_char : std_logic; - -begin - - case value is - when '0' => outvec_char := '0'; - when '1' => outvec_char := '1'; - when 'X' => outvec_char := 'X'; - when 'Z' => outvec_char := 'Z'; - when others => - assert false report "Illegal characters" severity note; - - end case; - - return outvec_char; -end to_slv_char; --------------------------------------------------------------------------- - --------------------------------------------------------------------------- --- Function: to_string --- --- Description: Converts time to string --------------------------------------------------------------------------- -function to_string (value : in integer) return string is -variable L : line; - -begin - write(L, value, RIGHT, 10); - return L.all; -end to_string; --------------------------------------------------------------------------- - - - FOR ALL: CY7C1360C USE ENTITY WORK.CY7C1360C(CY7C1360C_arch); - - SIGNAL DQ : STD_LOGIC_VECTOR((data_bits-1) DOWNTO 0); - SIGNAL Addr : STD_LOGIC_VECTOR((addr_bits-1) DOWNTO 0) := (OTHERS => '0'); - SIGNAL ZZ, clk : STD_LOGIC := '0'; - SIGNAL Mode : STD_LOGIC := '0'; - SIGNAL BWE_n : STD_LOGIC := '1'; - SIGNAL BWd_n : STD_LOGIC := '1'; - SIGNAL BWc_n : STD_LOGIC := '1'; - SIGNAL BWb_n : STD_LOGIC := '1'; - SIGNAL BWa_n : STD_LOGIC := '1'; - SIGNAL GW_n : STD_LOGIC := '1'; - signal CE1_n : STD_LOGIC := '1'; - signal CE2 : STD_LOGIC := '0'; - SIGNAL CE3_n : STD_LOGIC := '1'; - signal ADSP_n : STD_LOGIC := '1'; - signal ADSC_n : STD_LOGIC := '1'; - signal ADV_n : STD_LOGIC := '1'; - signal OE_n : STD_LOGIC := '1'; - signal count : integer := 0; - signal chkout : std_logic := '0'; - signal testin_tmp_slv : std_logic_vector ((data_bits-1) downto 0) := (others => '0'); - signal strb : std_logic := '0'; - signal temp : std_logic := '1'; - signal D : STD_LOGIC_VECTOR((data_bits-1) DOWNTO 0) := (OTHERS => '0'); - signal read_write : std_logic; - signal trigger : std_logic := '0'; -begin - - - - - -- Unit Under Test port map - UUT : CY7C1360C - PORT MAP (ioDq => Dq, - iAddr => Addr, - iClk => Clk, - iMode => Mode, - inAdv => Adv_n, - inBwa => Bwa_n, - inBwb => Bwb_n, - inBwc => Bwc_n, - inBwd => Bwd_n, - inOE => OE_n, - inCE1 => CE1_n, - inCE3 => CE3_n, - iCE2 => CE2, - inADSP => ADSP_n, - inADSC => ADSC_n, - inGW => GW_n, - inBWE => BWE_n, - iZZ => Zz - ); - -Process - begin - trigger <= '1' after 4 ns; - wait; -end process; - - with trigger select - strb <= not strb after 4.4 ns when '1', - '0' when others; --clock - -process(strb) - begin - clk <= strb after tx01; - end process; - -process - -variable l : line; -variable A_tmp : string (5 downto 1); -variable zz_tmp : character; -variable mode_tmp : character; -variable gw_tmp : character; -variable bwe_tmp : character; -variable bw_tmp : string (4 downto 1); -variable ce1_n_tmp : character; -variable ce2_tmp : character; -variable ce3_n_tmp : character; -variable adsp_n_tmp : character; -variable adsc_n_tmp : character; -variable adv_n_tmp : character; -variable oeb_tmp : character; -variable testout_tmp1, testout_tmp2, testout_tmp3, testout_tmp4 : string (9 downto 1); -variable testin_tmp1, testin_tmp2, testin_tmp3, testin_tmp4 : string (9 downto 1); -variable A_tmp_slv : STD_LOGIC_VECTOR (4 downto 0); -variable zz_tmp_slv : STD_LOGIC; -variable mode_tmp_slv : STD_LOGIC; -variable gw_tmp_slv : STD_LOGIC; -variable bwe_tmp_slv : STD_LOGIC; -variable bw_tmp_slv : STD_LOGIC_VECTOR (3 downto 0); -variable ce1_n_tmp_slv : STD_LOGIC; -variable ce2_tmp_slv : STD_LOGIC; -variable ce3_n_tmp_slv : STD_LOGIC; -variable adsp_n_tmp_slv : STD_LOGIC; -variable adsc_n_tmp_slv : STD_LOGIC; -variable adv_n_tmp_slv : STD_LOGIC; -variable oeb_tmp_slv : STD_LOGIC; -variable testout_tmp1_slv,testout_tmp2_slv,testout_tmp3_slv,testout_tmp4_slv : STD_LOGIC_VECTOR (8 downto 0); -variable US: character; -variable linecount: integer; -FILE test_vectors : text is in "SS_PL_SCD_X36_vect.txt"; -- preload file - - -begin - while not endfile(test_vectors) loop - assert false report "Line no" &to_string(count) severity note; - wait until strb = '1'; - readline (test_vectors,l); - read(l,zz_tmp); - read(l,US); - read(l,mode_tmp); - read(l,US); - read(l,A_tmp); - read(l,US); - read(l,gw_tmp); - read(l,US); - read(l,bwe_tmp); - read(l,US); - read(l,bw_tmp); - read(l,US); - read(l,ce1_n_tmp); - read(l,US); - read(l,ce2_tmp); - read(l,US); - read(l,ce3_n_tmp); - read(l,US); - read(l,ADSP_n_tmp); - read(l,US); - read(l,ADSC_n_tmp); - read(l,US); - read(l,ADV_n_tmp); - read(l,US); - read(l,oeb_tmp); - read(l,US); - read(l,testout_tmp1); - read(l,US); - read(l,testout_tmp2); - read(l,US); - read(l,testout_tmp3); - read(l,US); - read(l,testout_tmp4); - read(l,US); - read(l,testin_tmp1); - read(l,US); - read(l,testin_tmp2); - read(l,US); - read(l,testin_tmp3); - read(l,US); - read(l,testin_tmp4); - - - A_tmp_slv (4 downto 0) := to_slv(A_tmp); - zz_tmp_slv := to_slv_char(zz_tmp); - mode_tmp_slv := to_slv_char(mode_tmp); - gw_tmp_slv := to_slv_char(gw_tmp); - bwe_tmp_slv := to_slv_char(bwe_tmp); - bw_tmp_slv (3 downto 0) := to_slv(bw_tmp); - ce1_n_tmp_slv := to_slv_char(ce1_n_tmp); - ce2_tmp_slv := to_slv_char(ce2_tmp); - ce3_n_tmp_slv := to_slv_char(ce3_n_tmp); - ADSP_n_tmp_slv := to_slv_char(ADSP_n_tmp); - ADSC_n_tmp_slv := to_slv_char(ADSC_n_tmp); - ADV_n_tmp_slv := to_slv_char(ADV_n_tmp); - oeb_tmp_slv := to_slv_char(oeb_tmp); - testin_tmp_slv (8 downto 0) <= to_slv(testin_tmp4); - testout_tmp1_slv (8 downto 0) := to_slv(testout_tmp1); - testin_tmp_slv (17 downto 9) <= to_slv(testin_tmp3); - testout_tmp2_slv (8 downto 0) := to_slv(testout_tmp2); - testin_tmp_slv (26 downto 18) <= to_slv(testin_tmp2); - testout_tmp3_slv (8 downto 0) := to_slv(testout_tmp3); - testin_tmp_slv (35 downto 27) <= to_slv(testin_tmp1); - testout_tmp4_slv (8 downto 0) := to_slv(testout_tmp4); - - - Addr <= "0000000000000" & A_tmp_slv; - Mode <= mode_tmp_slv; - Adv_n <= Adv_n_tmp_slv; - Bwa_n <= Bw_tmp_slv (0); - Bwb_n <= Bw_tmp_slv (1); - Bwc_n <= Bw_tmp_slv (2); - Bwd_n <= Bw_tmp_slv (3); - OE_n <= OEb_tmp_slv; - CE1_n <= CE1_n_tmp_slv; - CE3_n <= CE3_n_tmp_slv; - CE2 <= CE2_tmp_slv; - ADSP_n <= ADSP_n_tmp_slv; - ADSC_n <= ADSC_n_tmp_slv; - GW_n <= GW_tmp_slv; - BWE_n <= BWE_tmp_slv; - ZZ <= zz_tmp_slv; - - D (35 downto 27) <= testout_tmp1_slv; - D (26 downto 18) <= testout_tmp2_slv; - D (17 downto 9) <= testout_tmp3_slv; - D (8 downto 0) <= testout_tmp4_slv; - - count <= count +1; - - - end loop; - chkout <= '1'; - wait; -end process; - - -read_write <= '0' when D = "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" else '1'; --1 means write -DQ <= D when read_write = '1' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; - -Process (clk) -begin - if rising_edge (clk) then - if (chkout = '0') then - if (D /= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ") then - assert false report "Write Cycle" severity note; - else - if (DQ(35 downto 0) = testin_tmp_slv(35 downto 0)) then - assert false report "OK" severity note; - else - assert false report "ERROR" severity note; - end if; - end if; - else - assert false report "TEST COMPLETE" severity note; - end if; - end if; -end process; - - -end tb_arch; - - - diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/TB_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/TB_Data_Acquisition.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/TB_Data_Acquisition.vhd +++ /dev/null @@ -1,348 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -------------------------------------------------------------------------------- - -ENTITY TB_Data_Acquisition IS - -END TB_Data_Acquisition; - -------------------------------------------------------------------------------- - -ARCHITECTURE tb OF TB_Data_Acquisition IS - - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - --COMPONENT Top_Data_Acquisition - -- GENERIC ( - -- hindex : INTEGER; - -- nb_burst_available_size : INTEGER := 11; - -- nb_snapshot_param_size : INTEGER := 11; - -- delta_snapshot_size : INTEGER := 16; - -- delta_f2_f0_size : INTEGER := 10; - -- delta_f2_f1_size : INTEGER := 10; - -- tech : integer); - -- PORT ( - -- cnv_run : IN STD_LOGIC; - -- cnv : OUT STD_LOGIC; - -- sck : OUT STD_LOGIC; - -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- cnv_clk : IN STD_LOGIC; - -- cnv_rstn : IN STD_LOGIC; - -- clk : IN STD_LOGIC; - -- rstn : IN STD_LOGIC; - -- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- AHB_Master_In : IN AHB_Mst_In_Type; - -- AHB_Master_Out : OUT AHB_Mst_Out_Type; - -- coarse_time_0 : IN STD_LOGIC; - -- data_shaping_SP0 : IN STD_LOGIC; - -- data_shaping_SP1 : IN STD_LOGIC; - -- data_shaping_R0 : IN STD_LOGIC; - -- data_shaping_R1 : IN STD_LOGIC; - -- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - -- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - -- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - -- enable_f0 : IN STD_LOGIC; - -- enable_f1 : IN STD_LOGIC; - -- enable_f2 : IN STD_LOGIC; - -- enable_f3 : IN STD_LOGIC; - -- burst_f0 : IN STD_LOGIC; - -- burst_f1 : IN STD_LOGIC; - -- burst_f2 : IN STD_LOGIC; - -- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - -- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - -- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - -- component ports - SIGNAL cnv_rstn : STD_LOGIC; - SIGNAL cnv : STD_LOGIC; - SIGNAL rstn : STD_LOGIC; - SIGNAL sck : STD_LOGIC; - SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL run_cnv : STD_LOGIC; - - - -- clock - signal Clk : STD_LOGIC := '1'; - SIGNAL cnv_clk : STD_LOGIC := '1'; - - ----------------------------------------------------------------------------- - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - ----------------------------------------------------------------------------- - CONSTANT nb_burst_available_size : INTEGER := 11; - CONSTANT nb_snapshot_param_size : INTEGER := 11; - CONSTANT delta_snapshot_size : INTEGER := 16; - CONSTANT delta_f2_f0_size : INTEGER := 10; - CONSTANT delta_f2_f1_size : INTEGER := 10; - - SIGNAL AHB_Master_In : AHB_Mst_In_Type; - SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; - - SIGNAL coarse_time_0 : STD_LOGIC; - SIGNAL coarse_time_0_t : STD_LOGIC := '0'; - SIGNAL coarse_time_0_t2 : STD_LOGIC := '0'; - - SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - SIGNAL enable_f0 : STD_LOGIC; - SIGNAL enable_f1 : STD_LOGIC; - SIGNAL enable_f2 : STD_LOGIC; - SIGNAL enable_f3 : STD_LOGIC; - - SIGNAL burst_f0 : STD_LOGIC; - SIGNAL burst_f1 : STD_LOGIC; - SIGNAL burst_f2 : STD_LOGIC; - - SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - - SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - - SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); - - - SIGNAL data_shaping_SP0 : STD_LOGIC; - SIGNAL data_shaping_SP1 : STD_LOGIC; - SIGNAL data_shaping_R0 : STD_LOGIC; - SIGNAL data_shaping_R1 : STD_LOGIC; -BEGIN -- tb - - MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(7)); - - - -- clock generation - Clk <= not Clk after 20 ns; -- 25 Mhz - cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz - - -- waveform generation - WaveGen_Proc: process - begin - -- insert signal assignments here - wait until Clk = '1'; - rstn <= '0'; - cnv_rstn <= '0'; - run_cnv <= '0'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - rstn <= '1'; - cnv_rstn <= '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - run_cnv <= '1'; - wait; - - end process WaveGen_Proc; - - ----------------------------------------------------------------------------- - - Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip - GENERIC MAP ( - hindex => 2, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size =>16, - delta_f2_f0_size =>10, - delta_f2_f1_size =>10, - tech => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo, - cnv_clk => cnv_clk, - cnv_rstn => cnv_rstn, - clk => clk, - rstn => rstn, - sample_f0_wen => sample_f0_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wen => sample_f1_wen, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wen => sample_f2_wen, - sample_f2_wdata => sample_f2_wdata, - sample_f3_wen => sample_f3_wen, - sample_f3_wdata => sample_f3_wdata, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - coarse_time_0 => coarse_time_0, - data_shaping_SP0 => data_shaping_SP0, - data_shaping_SP1 => data_shaping_SP1, - data_shaping_R0 => data_shaping_R0, - data_shaping_R1 => data_shaping_R1, - delta_snapshot => delta_snapshot, - delta_f2_f1 => delta_f2_f1, - delta_f2_f0 => delta_f2_f0, - enable_f0 => enable_f0, - enable_f1 => enable_f1, - enable_f2 => enable_f2, - enable_f3 => enable_f3, - burst_f0 => burst_f0, - burst_f1 => burst_f1, - burst_f2 => burst_f2, - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - status_new_err => status_new_err, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3); - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - enable_f0 <= '0'; - enable_f1 <= '0'; - enable_f2 <= '0'; - enable_f3 <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - enable_f0 <= '1'; --TODO test - enable_f1 <= '1'; - enable_f2 <= '1'; - enable_f3 <= '1'; - END IF; - END PROCESS; - - burst_f0 <= '0'; --TODO test - burst_f1 <= '0'; --TODO test - burst_f2 <= '0'; - - data_shaping_SP0 <= '0'; - data_shaping_SP1 <= '0'; - data_shaping_R0 <= '1'; - data_shaping_R1 <= '1'; - - delta_snapshot <= "0000000000000001"; - --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 - --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2 - --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4 - - -- A redefinir car ca ne tombe pas correctement ... ??? - nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34 - nb_snapshot_param <= "00000001111"; -- x+1 = 16 - delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2 - delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4 - - addr_data_f0 <= "00000000000000000000000000000000"; - addr_data_f1 <= "00010000000000000000000000000000"; - addr_data_f2 <= "00100000000000000000000000000000"; - addr_data_f3 <= "00110000000000000000000000000000"; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - status_full_ack <= (OTHERS => '0'); - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - status_full_ack <= status_full; - END IF; - END PROCESS; - - - coarse_time_0_t <= not coarse_time_0_t after 50 ms; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - coarse_time_0_t2 <= '0'; - coarse_time_0 <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - coarse_time_0_t2 <= coarse_time_0_t; - coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2); - END IF; - END PROCESS; - - - AHB_Master_In.HGRANT(2) <= '1'; - AHB_Master_In.HREADY <= '1'; - - - AHB_Master_In.HRESP <= HRESP_OKAY; - - -END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/TB_Data_Acquisition_2.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/TB_Data_Acquisition_2.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/TB_Data_Acquisition_2.vhd +++ /dev/null @@ -1,544 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.lpp_waveform_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -------------------------------------------------------------------------------- - -ENTITY TB_Data_Acquisition IS - -END TB_Data_Acquisition; - -------------------------------------------------------------------------------- - -ARCHITECTURE tb OF TB_Data_Acquisition IS - - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - --COMPONENT Top_Data_Acquisition - -- GENERIC ( - -- hindex : INTEGER; - -- nb_burst_available_size : INTEGER := 11; - -- nb_snapshot_param_size : INTEGER := 11; - -- delta_snapshot_size : INTEGER := 16; - -- delta_f2_f0_size : INTEGER := 10; - -- delta_f2_f1_size : INTEGER := 10; - -- tech : integer); - -- PORT ( - -- cnv_run : IN STD_LOGIC; - -- cnv : OUT STD_LOGIC; - -- sck : OUT STD_LOGIC; - -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- cnv_clk : IN STD_LOGIC; - -- cnv_rstn : IN STD_LOGIC; - -- clk : IN STD_LOGIC; - -- rstn : IN STD_LOGIC; - -- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - -- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- AHB_Master_In : IN AHB_Mst_In_Type; - -- AHB_Master_Out : OUT AHB_Mst_Out_Type; - -- coarse_time_0 : IN STD_LOGIC; - -- data_shaping_SP0 : IN STD_LOGIC; - -- data_shaping_SP1 : IN STD_LOGIC; - -- data_shaping_R0 : IN STD_LOGIC; - -- data_shaping_R1 : IN STD_LOGIC; - -- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - -- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - -- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - -- enable_f0 : IN STD_LOGIC; - -- enable_f1 : IN STD_LOGIC; - -- enable_f2 : IN STD_LOGIC; - -- enable_f3 : IN STD_LOGIC; - -- burst_f0 : IN STD_LOGIC; - -- burst_f1 : IN STD_LOGIC; - -- burst_f2 : IN STD_LOGIC; - -- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - -- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - -- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - -- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - -- component ports - SIGNAL cnv_rstn : STD_LOGIC; - SIGNAL cnv : STD_LOGIC; - SIGNAL rstn : STD_LOGIC; - SIGNAL sck : STD_LOGIC; - SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL run_cnv : STD_LOGIC; - - - -- clock - signal Clk : STD_LOGIC := '1'; - SIGNAL cnv_clk : STD_LOGIC := '1'; - - ----------------------------------------------------------------------------- - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - ----------------------------------------------------------------------------- - CONSTANT nb_burst_available_size : INTEGER := 12; - CONSTANT nb_snapshot_param_size : INTEGER := 12; - CONSTANT delta_snapshot_size : INTEGER := 16; - CONSTANT delta_f2_f0_size : INTEGER := 20; - CONSTANT delta_f2_f1_size : INTEGER := 16; - - SIGNAL AHB_Master_In : AHB_Mst_In_Type; - SIGNAL AHB_Master_Out : AHB_Mst_Out_Type; - - SIGNAL coarse_time_0 : STD_LOGIC := '0'; - SIGNAL coarse_time_0_t : STD_LOGIC := '0'; - SIGNAL coarse_time_0_t2 : STD_LOGIC := '0'; - - SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - SIGNAL enable_f0 : STD_LOGIC; - SIGNAL enable_f1 : STD_LOGIC; - SIGNAL enable_f2 : STD_LOGIC; - SIGNAL enable_f3 : STD_LOGIC; - - SIGNAL burst_f0 : STD_LOGIC; - SIGNAL burst_f1 : STD_LOGIC; - SIGNAL burst_f2 : STD_LOGIC; - - SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - - SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - - SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); - - - SIGNAL data_shaping_SP0 : STD_LOGIC; - SIGNAL data_shaping_SP1 : STD_LOGIC; - SIGNAL data_shaping_R0 : STD_LOGIC; - SIGNAL data_shaping_R1 : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_type; - ----------------------------------------------------------------------------- - SIGNAL ready_matrix_f0_0 : STD_LOGIC; - SIGNAL ready_matrix_f0_1 : STD_LOGIC; - SIGNAL ready_matrix_f1 : STD_LOGIC; - SIGNAL ready_matrix_f2 : STD_LOGIC; - SIGNAL error_anticipating_empty_fifo : STD_LOGIC; - SIGNAL error_bad_component_error : STD_LOGIC; - SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; - SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; - SIGNAL status_ready_matrix_f1 : STD_LOGIC; - SIGNAL status_ready_matrix_f2 : STD_LOGIC; - SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; - SIGNAL status_error_bad_component_error : STD_LOGIC; - SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; - SIGNAL config_active_interruption_onError : STD_LOGIC; - SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - -BEGIN -- tb - - MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u: TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo(7)); - - - -- clock generation - Clk <= not Clk after 25 ns; -- 20 Mhz - --cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz - cnv_clk <= not cnv_clk after 20346 ps; -- 49.152/2 MHz - - - --type apb_slv_in_type is record - -- psel : std_logic_vector(0 to NAPBSLV-1); -- slave select - -- penable : std_ulogic; -- strobe - -- paddr : std_logic_vector(31 downto 0); -- address bus (byte) - -- pwrite : std_ulogic; -- write - -- pwdata : std_logic_vector(31 downto 0); -- write data bus - -- pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus - -- testen : std_ulogic; -- scan test enable - -- testrst : std_ulogic; -- scan test reset - -- scanen : std_ulogic; -- scan enable - -- testoen : std_ulogic; -- test output enable - --end record; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - - END IF; - END PROCESS; - - -- waveform generation - WaveGen_Proc: process - begin - -- insert signal assignments here - wait until Clk = '1'; - apbi <= apb_slv_in_none; - rstn <= '0'; - cnv_rstn <= '0'; - run_cnv <= '0'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - rstn <= '1'; - cnv_rstn <= '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - run_cnv <= '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - apbi.psel(15) <= '1'; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - -- 765432 - apbi.paddr(7 DOWNTO 2) <= "001000"; - apbi.pwdata(4 DOWNTO 0) <= "00000"; - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "001001"; - apbi.pwdata(6 DOWNTO 0) <= "0000000"; - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "001010"; - apbi.pwdata <= "10000000000000000000000000000000"; - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "001011"; - apbi.pwdata <= "10010000000000000000000000000000"; - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "001100"; - apbi.pwdata <= "10100000000000000000000000000000"; - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "001101"; - apbi.pwdata <= "10110000000000000000000000000000"; - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "001110"; - apbi.pwdata(11 DOWNTO 0) <= "000000000000"; - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "001111"; - apbi.pwdata(15 DOWNTO 0) <= "0000000000000001"; -- A => 1 * 100 ms - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "010000"; -- delta_f2_f1 - apbi.pwdata(15 DOWNTO 0) <= "0000000001111000"; -- 0x78 = 120 - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "010001"; -- delta_f2_f0 - apbi.pwdata(19 DOWNTO 0) <= "00000000001011111000"; -- 0x2f8 = 760 - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "010010"; -- nb_burst_available - apbi.pwdata(11 DOWNTO 0) <= "000000001100"; -- 12 = 0xC - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "010011"; -- nb_snapshot_param - apbi.pwdata(11 DOWNTO 0) <= "000000001111"; -- 15 (+ 1) - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - wait until Clk = '1'; - apbi.paddr(7 DOWNTO 2) <= "001001"; - apbi.pwdata(6 DOWNTO 0) <= "0000111"; - wait until Clk = '1'; - apbi.psel(15) <= '1'; - apbi.penable <= '0'; - apbi.pwrite <= '0'; - wait until Clk = '1'; - - wait; - - end process WaveGen_Proc; - - ----------------------------------------------------------------------------- - - Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip - GENERIC MAP ( - hindex => 2, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size => delta_snapshot_size, - delta_f2_f0_size => delta_f2_f0_size, - delta_f2_f1_size => delta_f2_f1_size, - tech => 0, - Mem_use => use_CEL - ) - PORT MAP ( - cnv_run => run_cnv, - cnv => cnv, - sck => sck, - sdo => sdo, - cnv_clk => cnv_clk, - cnv_rstn => cnv_rstn, - clk => clk, - rstn => rstn, - sample_f0_wen => sample_f0_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wen => sample_f1_wen, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wen => sample_f2_wen, - sample_f2_wdata => sample_f2_wdata, - sample_f3_wen => sample_f3_wen, - sample_f3_wdata => sample_f3_wdata, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - coarse_time_0 => coarse_time_0, - data_shaping_SP0 => data_shaping_SP0, - data_shaping_SP1 => data_shaping_SP1, - data_shaping_R0 => data_shaping_R0, - data_shaping_R1 => data_shaping_R1, - delta_snapshot => delta_snapshot, - delta_f2_f1 => delta_f2_f1, - delta_f2_f0 => delta_f2_f0, - enable_f0 => enable_f0, - enable_f1 => enable_f1, - enable_f2 => enable_f2, - enable_f3 => enable_f3, - burst_f0 => burst_f0, - burst_f1 => burst_f1, - burst_f2 => burst_f2, - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - status_new_err => status_new_err, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3); - - ready_matrix_f0_0 <= '0'; - ready_matrix_f0_1 <= '0'; - ready_matrix_f1 <= '0'; - ready_matrix_f2 <= '0'; - error_anticipating_empty_fifo <= '0'; - error_bad_component_error <= '0'; - debug_reg <= (OTHERS => '0'); - - - lpp_top_apbreg_1: lpp_top_apbreg - GENERIC MAP ( - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size => delta_snapshot_size, - delta_f2_f0_size => delta_f2_f0_size, - delta_f2_f1_size => delta_f2_f1_size, - - pindex => 15, -- todo - paddr => 15, -- todo - pmask => 16#fff#, -- todo - pirq => 15) -- todo - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - apbi => apbi, -- todo - apbo => apbo, -- todo - - ready_matrix_f0_0 => ready_matrix_f0_0, - ready_matrix_f0_1 => ready_matrix_f0_1, - ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, - error_anticipating_empty_fifo => error_anticipating_empty_fifo, - error_bad_component_error => error_bad_component_error, - debug_reg => debug_reg, - status_ready_matrix_f0_0 => OPEN, - status_ready_matrix_f0_1 => OPEN, - status_ready_matrix_f1 => OPEN, - status_ready_matrix_f2 => OPEN, - status_error_anticipating_empty_fifo => OPEN, - status_error_bad_component_error => OPEN, - config_active_interruption_onNewMatrix => OPEN, - config_active_interruption_onError => OPEN, - addr_matrix_f0_0 => OPEN, - addr_matrix_f0_1 => OPEN, - addr_matrix_f1 => OPEN, - addr_matrix_f2 => OPEN, - - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - status_new_err => status_new_err, - - data_shaping_BW => OPEN, - data_shaping_SP0 => data_shaping_SP0, - data_shaping_SP1 => data_shaping_SP1, - data_shaping_R0 => data_shaping_R0, - data_shaping_R1 => data_shaping_R1, - - delta_snapshot => delta_snapshot, - delta_f2_f1 => delta_f2_f1, - delta_f2_f0 => delta_f2_f0, - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - enable_f0 => enable_f0, - enable_f1 => enable_f1, - enable_f2 => enable_f2, - enable_f3 => enable_f3, - burst_f0 => burst_f0, - burst_f1 => burst_f1, - burst_f2 => burst_f2, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3); - - - - - - - --PROCESS (clk, rstn) - --BEGIN -- PROCESS - -- IF rstn = '0' THEN -- asynchronous reset (active low) - -- enable_f0 <= '0'; - -- enable_f1 <= '0'; - -- enable_f2 <= '0'; - -- enable_f3 <= '0'; - -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge - -- enable_f0 <= '1'; --TODO test - -- enable_f1 <= '1'; - -- enable_f2 <= '1'; - -- enable_f3 <= '1'; - -- END IF; - --END PROCESS; - - --burst_f0 <= '0'; --TODO test - --burst_f1 <= '0'; --TODO test - --burst_f2 <= '0'; - - --data_shaping_SP0 <= '0'; - --data_shaping_SP1 <= '0'; - --data_shaping_R0 <= '1'; - --data_shaping_R1 <= '1'; - - --delta_snapshot <= "0000000000000001"; - --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 - --delta_f2_f0 <= "10 1001 1001";--665 = 14/2*96 -14/2 - --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4 - - -- A redefinir car ca ne tombe pas correctement ... ??? - --nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34 - --nb_snapshot_param <= "00000001111"; -- x+1 = 16 - --delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2 - --delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4 - - --addr_data_f0 <= "00000000000000000000000000000000"; - --addr_data_f1 <= "00010000000000000000000000000000"; - --addr_data_f2 <= "00100000000000000000000000000000"; - --addr_data_f3 <= "00110000000000000000000000000000"; - - --PROCESS (clk, rstn) - --BEGIN -- PROCESS - -- IF rstn = '0' THEN -- asynchronous reset (active low) - -- status_full_ack <= (OTHERS => '0'); - -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge - -- status_full_ack <= status_full; - -- END IF; - --END PROCESS; - - - coarse_time_0 <= not coarse_time_0 AFTER 100 ms; - - --PROCESS (clk, rstn) - --BEGIN -- PROCESS - -- IF rstn = '0' THEN -- asynchronous reset (active low) - -- coarse_time_0_t2 <= '0'; - -- coarse_time_0 <= '0'; - -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge - -- coarse_time_0_t2 <= coarse_time_0_t; - -- coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2); - -- END IF; - --END PROCESS; - - - AHB_Master_In.HGRANT(2) <= '1'; - AHB_Master_In.HREADY <= '1'; - AHB_Master_In.HRESP <= HRESP_OKAY; - - -END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/Top_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/Top_Data_Acquisition.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/Top_Data_Acquisition.vhd +++ /dev/null @@ -1,498 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -ENTITY Top_Data_Acquisition IS - GENERIC( - hindex : INTEGER := 2; - nb_burst_available_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_snapshot_size : INTEGER := 16; - delta_f2_f0_size : INTEGER := 10; - delta_f2_f1_size : INTEGER := 10; - tech : INTEGER := 0 - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - -- - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - -- - sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - -- - sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - - coarse_time_0 : IN STD_LOGIC; - - --config - data_shaping_SP0 : IN STD_LOGIC; - data_shaping_SP1 : IN STD_LOGIC; - data_shaping_R0 : IN STD_LOGIC; - data_shaping_R1 : IN STD_LOGIC; - - delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - enable_f0 : IN STD_LOGIC; - enable_f1 : IN STD_LOGIC; - enable_f2 : IN STD_LOGIC; - enable_f3 : IN STD_LOGIC; - - burst_f0 : IN STD_LOGIC; - burst_f1 : IN STD_LOGIC; - burst_f2 : IN STD_LOGIC; - - nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma - - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END Top_Data_Acquisition; - -ARCHITECTURE tb OF Top_Data_Acquisition IS - - COMPONENT Downsampling - GENERIC ( - ChanelCount : INTEGER; - SampleSize : INTEGER; - DivideParam : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); - sample_out_val : OUT STD_LOGIC; - sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); - END COMPONENT; - - ----------------------------------------------------------------------------- - CONSTANT ChanelCount : INTEGER := 8; - CONSTANT ncycle_cnv_high : INTEGER := 79; - CONSTANT ncycle_cnv : INTEGER := 500; - - ----------------------------------------------------------------------------- - SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL sample_val_delay : STD_LOGIC; - ----------------------------------------------------------------------------- - CONSTANT Coef_SZ : INTEGER := 9; - CONSTANT CoefCntPerCel : INTEGER := 6; - CONSTANT CoefPerCel : INTEGER := 5; - CONSTANT Cels_count : INTEGER := 5; - - SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_val : STD_LOGIC; - SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_data_shaping_out_val : STD_LOGIC; - SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; - SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); - SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - ----------------------------------------------------------------------------- - - SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -BEGIN - - -- component instantiation - ----------------------------------------------------------------------------- - DIGITAL_acquisition : AD7688_drvr - GENERIC MAP ( - ChanelCount => ChanelCount, - ncycle_cnv_high => ncycle_cnv_high, - ncycle_cnv => ncycle_cnv) - PORT MAP ( - cnv_clk => cnv_clk, -- - cnv_rstn => cnv_rstn, -- - cnv_run => cnv_run, -- - cnv => cnv, -- - clk => clk, -- - rstn => rstn, -- - sck => sck, -- - sdo => sdo(ChanelCount-1 DOWNTO 0), -- - sample => sample, - sample_val => sample_val); - - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_val_delay <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_val_delay <= sample_val; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE - SampleLoop : FOR j IN 0 TO 15 GENERATE - sample_filter_in(i, j) <= sample(i)(j); - END GENERATE; - - sample_filter_in(i, 16) <= sample(i)(15); - sample_filter_in(i, 17) <= sample(i)(15); - END GENERATE; - - coefs_v2 <= CoefsInitValCst_v2; - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => 0, - Mem_use => use_CEL, -- use_RAM - Sample_SZ => 18, - Coef_SZ => Coef_SZ, - Coef_Nb => 25, - Coef_sel_SZ => 5, - Cels_count => Cels_count, - ChanelsCount => ChanelCount) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => 7, - coefs => coefs_v2, - sample_in_val => sample_val_delay, - sample_in => sample_filter_in, - sample_out_val => sample_filter_v2_out_val, - sample_out => sample_filter_v2_out); - - ----------------------------------------------------------------------------- - -- DATA_SHAPING - ----------------------------------------------------------------------------- - all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE - sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); - sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); - sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); - END GENERATE all_data_shaping_in_loop; - - sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; - sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_data_shaping_out_val <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - sample_data_shaping_out_val <= sample_filter_v2_out_val; - END IF; - END PROCESS; - - SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - sample_data_shaping_out(0,j) <= '0'; - sample_data_shaping_out(1,j) <= '0'; - sample_data_shaping_out(2,j) <= '0'; - sample_data_shaping_out(3,j) <= '0'; - sample_data_shaping_out(4,j) <= '0'; - sample_data_shaping_out(5,j) <= '0'; - sample_data_shaping_out(6,j) <= '0'; - sample_data_shaping_out(7,j) <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); - IF data_shaping_SP0 = '1' THEN - sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); - ELSE - sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); - END IF; - IF data_shaping_SP1 = '1' THEN - sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); - ELSE - sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); - END IF; - sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); - sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); - sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); - sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); - END IF; - END PROCESS; - END GENERATE; - - sample_filter_v2_out_val_s <= sample_data_shaping_out_val; - ChanelLoopOut : FOR i IN 0 TO 7 GENERATE - SampleLoopOut : FOR j IN 0 TO 15 GENERATE - sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); - END GENERATE; - END GENERATE; - ----------------------------------------------------------------------------- - -- F0 -- @24.576 kHz - ----------------------------------------------------------------------------- - Downsampling_f0 : Downsampling - GENERIC MAP ( - ChanelCount => 8, - SampleSize => 16, - DivideParam => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_filter_v2_out_val_s, - sample_in => sample_filter_v2_out_s, - sample_out_val => sample_f0_val, - sample_out => sample_f0); - - all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_wdata_s(I) <= sample_f0(0, I); -- V - sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 - sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 - sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 - sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 - sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 - END GENERATE all_bit_sample_f0; - - sample_f0_wen <= NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val); - - ----------------------------------------------------------------------------- - -- F1 -- @4096 Hz - ----------------------------------------------------------------------------- - Downsampling_f1 : Downsampling - GENERIC MAP ( - ChanelCount => 8, - SampleSize => 16, - DivideParam => 6) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f1_val, - sample_out => sample_f1); - - all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_wdata_s(I) <= sample_f1(0, I); -- V - sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 - sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 - sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 - sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 - sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 - END GENERATE all_bit_sample_f1; - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); - - ----------------------------------------------------------------------------- - -- F2 -- @256 Hz - ----------------------------------------------------------------------------- - all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_s(0, I) <= sample_f0(0, I); -- V - sample_f0_s(1, I) <= sample_f0(1, I); -- E1 - sample_f0_s(2, I) <= sample_f0(2, I); -- E2 - sample_f0_s(3, I) <= sample_f0(5, I); -- B1 - sample_f0_s(4, I) <= sample_f0(6, I); -- B2 - sample_f0_s(5, I) <= sample_f0(7, I); -- B3 - END GENERATE all_bit_sample_f0_s; - - Downsampling_f2 : Downsampling - GENERIC MAP ( - ChanelCount => 6, - SampleSize => 16, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0_s, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - sample_f2_wen <= NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val); - - all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f2_wdata_s(I) <= sample_f2(0, I); - sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); - sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); - sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); - sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); - sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); - END GENERATE all_bit_sample_f2; - - ----------------------------------------------------------------------------- - -- F3 -- @16 Hz - ----------------------------------------------------------------------------- - all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_s(0, I) <= sample_f1(0, I); -- V - sample_f1_s(1, I) <= sample_f1(1, I); -- E1 - sample_f1_s(2, I) <= sample_f1(2, I); -- E2 - sample_f1_s(3, I) <= sample_f1(5, I); -- B1 - sample_f1_s(4, I) <= sample_f1(6, I); -- B2 - sample_f1_s(5, I) <= sample_f1(7, I); -- B3 - END GENERATE all_bit_sample_f1_s; - - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => 6, - SampleSize => 16, - DivideParam => 256) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f1_val , - sample_in => sample_f1_s, - sample_out_val => sample_f3_val, - sample_out => sample_f3); - - sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); - - all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f3_wdata_s(I) <= sample_f3(0, I); - sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); - sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); - sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); - sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); - sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); - END GENERATE all_bit_sample_f3; - - lpp_waveform_1 : lpp_waveform - GENERIC MAP ( - hindex => hindex, - tech => tech, - data_size => 160, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size => delta_snapshot_size, - delta_f2_f0_size => delta_f2_f0_size, - delta_f2_f1_size => delta_f2_f1_size) - PORT MAP ( - clk => clk, - rstn => rstn, - - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - - coarse_time_0 => coarse_time_0, -- IN - delta_snapshot => delta_snapshot, -- IN - delta_f2_f1 => delta_f2_f1, -- IN - delta_f2_f0 => delta_f2_f0, -- IN - enable_f0 => enable_f0, -- IN - enable_f1 => enable_f1, -- IN - enable_f2 => enable_f2, -- IN - enable_f3 => enable_f3, -- IN - burst_f0 => burst_f0, -- IN - burst_f1 => burst_f1, -- IN - burst_f2 => burst_f2, -- IN - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, -- IN - status_full_err => status_full_err, - status_new_err => status_new_err, - - addr_data_f0 => addr_data_f0, -- IN - addr_data_f1 => addr_data_f1, -- IN - addr_data_f2 => addr_data_f2, -- IN - addr_data_f3 => addr_data_f3, -- IN - - data_f0_in => data_f0_in_valid, - data_f1_in => data_f1_in_valid, - data_f2_in => data_f2_in_valid, - data_f3_in => data_f3_in_valid, - data_f0_in_valid => sample_f0_val, - data_f1_in_valid => sample_f1_val, - data_f2_in_valid => sample_f2_val, - data_f3_in_valid => sample_f3_val); - - data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; - data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; - data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; - data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; - - sample_f0_wdata <= sample_f0_wdata_s; - sample_f1_wdata <= sample_f1_wdata_s; - sample_f2_wdata <= sample_f2_wdata_s; - sample_f3_wdata <= sample_f3_wdata_s; - -END tb; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/config.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/config.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/config.vhd +++ /dev/null @@ -1,218 +0,0 @@ - - - - ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------- - - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -PACKAGE config IS --- Technology and synthesis options - CONSTANT CFG_FABTECH : INTEGER := inferred; - CONSTANT CFG_MEMTECH : INTEGER := inferred; - --constant CFG_FABTECH : integer := apa3; --inferred; - --constant CFG_MEMTECH : integer := apa3; --inferred; - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT CFG_NOASYNC : INTEGER := 0; - CONSTANT CFG_SCAN : INTEGER := 0; --- Clock generator - CONSTANT CFG_CLKTECH : INTEGER := inferred; - CONSTANT CFG_CLKMUL : INTEGER := 2; - CONSTANT CFG_CLKDIV : INTEGER := 2; - CONSTANT CFG_OCLKDIV : INTEGER := 1; - CONSTANT CFG_OCLKBDIV : INTEGER := 0; - CONSTANT CFG_OCLKCDIV : INTEGER := 0; - CONSTANT CFG_PCIDLL : INTEGER := 0; - CONSTANT CFG_PCISYSCLK : INTEGER := 0; - CONSTANT CFG_CLK_NOFB : INTEGER := 0; --- LEON3 processor core - CONSTANT CFG_LEON3 : INTEGER := 1; - CONSTANT CFG_NCPU : INTEGER := (1); - CONSTANT CFG_NWIN : INTEGER := (8); - CONSTANT CFG_V8 : INTEGER := 0 + 4*0; - CONSTANT CFG_MAC : INTEGER := 0; - CONSTANT CFG_BP : INTEGER := 0; - CONSTANT CFG_SVT : INTEGER := 0; - CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; - CONSTANT CFG_LDDEL : INTEGER := (1); - CONSTANT CFG_NOTAG : INTEGER := 0; - CONSTANT CFG_NWP : INTEGER := (0); - CONSTANT CFG_PWD : INTEGER := 0*2; - CONSTANT CFG_FPU : INTEGER := 0 + 16*0 + 32*0; - CONSTANT CFG_GRFPUSH : INTEGER := 0; - CONSTANT CFG_ICEN : INTEGER := 1; - CONSTANT CFG_ISETS : INTEGER := 1; - CONSTANT CFG_ISETSZ : INTEGER := 4; - CONSTANT CFG_ILINE : INTEGER := 8; - CONSTANT CFG_IREPL : INTEGER := 0; - CONSTANT CFG_ILOCK : INTEGER := 0; - CONSTANT CFG_ILRAMEN : INTEGER := 0; - CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; - CONSTANT CFG_ILRAMSZ : INTEGER := 1; - CONSTANT CFG_DCEN : INTEGER := 1; - CONSTANT CFG_DSETS : INTEGER := 1; - CONSTANT CFG_DSETSZ : INTEGER := 4; - CONSTANT CFG_DLINE : INTEGER := 8; - CONSTANT CFG_DREPL : INTEGER := 0; - CONSTANT CFG_DLOCK : INTEGER := 0; - CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; - CONSTANT CFG_DFIXED : INTEGER := 16#0#; - CONSTANT CFG_DLRAMEN : INTEGER := 0; - CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; - CONSTANT CFG_DLRAMSZ : INTEGER := 1; - CONSTANT CFG_MMUEN : INTEGER := 1; - CONSTANT CFG_ITLBNUM : INTEGER := 8; - CONSTANT CFG_DTLBNUM : INTEGER := 8; - CONSTANT CFG_TLB_TYPE : INTEGER := 0 + 1*2; - CONSTANT CFG_TLB_REP : INTEGER := 1; - CONSTANT CFG_MMU_PAGE : INTEGER := 0; - CONSTANT CFG_DSU : INTEGER := 0; - CONSTANT CFG_ITBSZ : INTEGER := 0; - CONSTANT CFG_ATBSZ : INTEGER := 0; - CONSTANT CFG_LEON3FT_EN : INTEGER := 0; - CONSTANT CFG_IUFT_EN : INTEGER := 0; - CONSTANT CFG_FPUFT_EN : INTEGER := 0; - CONSTANT CFG_RF_ERRINJ : INTEGER := 0; - CONSTANT CFG_CACHE_FT_EN : INTEGER := 0; - CONSTANT CFG_CACHE_ERRINJ : INTEGER := 0; - CONSTANT CFG_LEON3_NETLIST : INTEGER := 0; - CONSTANT CFG_DISAS : INTEGER := 0 + 0; - CONSTANT CFG_PCLOW : INTEGER := 2; --- AMBA settings - CONSTANT CFG_DEFMST : INTEGER := (0); - CONSTANT CFG_RROBIN : INTEGER := 1; - CONSTANT CFG_SPLIT : INTEGER := 0; - CONSTANT CFG_FPNPEN : INTEGER := 0; - CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; - CONSTANT CFG_APBADDR : INTEGER := 16#800#; - CONSTANT CFG_AHB_MON : INTEGER := 0; - CONSTANT CFG_AHB_MONERR : INTEGER := 0; - CONSTANT CFG_AHB_MONWAR : INTEGER := 0; - CONSTANT CFG_AHB_DTRACE : INTEGER := 0; --- DSU UART - CONSTANT CFG_AHB_UART : INTEGER := 1; --- JTAG based DSU interface - CONSTANT CFG_AHB_JTAG : INTEGER := 0; --- Ethernet DSU - CONSTANT CFG_DSU_ETH : INTEGER := 0 + 0 + 0; - CONSTANT CFG_ETH_BUF : INTEGER := 1; - CONSTANT CFG_ETH_IPM : INTEGER := 16#C0A8#; - CONSTANT CFG_ETH_IPL : INTEGER := 16#0033#; - CONSTANT CFG_ETH_ENM : INTEGER := 16#020000#; - CONSTANT CFG_ETH_ENL : INTEGER := 16#000009#; --- PROM/SRAM controller - CONSTANT CFG_SRCTRL : INTEGER := 0; - CONSTANT CFG_SRCTRL_PROMWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_RAMWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_IOWS : INTEGER := 0; - CONSTANT CFG_SRCTRL_RMW : INTEGER := 0; - CONSTANT CFG_SRCTRL_8BIT : INTEGER := 0; - CONSTANT CFG_SRCTRL_SRBANKS : INTEGER := 1; - CONSTANT CFG_SRCTRL_BANKSZ : INTEGER := 0; - CONSTANT CFG_SRCTRL_ROMASEL : INTEGER := 0; --- LEON2 memory controller - CONSTANT CFG_MCTRL_LEON2 : INTEGER := 1; - CONSTANT CFG_MCTRL_RAM8BIT : INTEGER := 0; - CONSTANT CFG_MCTRL_RAM16BIT : INTEGER := 0; - CONSTANT CFG_MCTRL_5CS : INTEGER := 0; - CONSTANT CFG_MCTRL_SDEN : INTEGER := 1; - CONSTANT CFG_MCTRL_SEPBUS : INTEGER := 0; - CONSTANT CFG_MCTRL_INVCLK : INTEGER := 0; - CONSTANT CFG_MCTRL_SD64 : INTEGER := 0; - CONSTANT CFG_MCTRL_PAGE : INTEGER := 1 + 0; --- SDRAM controller - CONSTANT CFG_SDCTRL : INTEGER := 0; - CONSTANT CFG_SDCTRL_INVCLK : INTEGER := 0; - CONSTANT CFG_SDCTRL_SD64 : INTEGER := 0; - CONSTANT CFG_SDCTRL_PAGE : INTEGER := 0 + 0; --- AHB ROM - CONSTANT CFG_AHBROMEN : INTEGER := 0; - CONSTANT CFG_AHBROPIP : INTEGER := 0; - CONSTANT CFG_AHBRODDR : INTEGER := 16#000#; - CONSTANT CFG_ROMADDR : INTEGER := 16#000#; - CONSTANT CFG_ROMMASK : INTEGER := 16#E00# + 16#000#; --- AHB RAM - CONSTANT CFG_AHBRAMEN : INTEGER := 1; - CONSTANT CFG_AHBRSZ : INTEGER := 1; - CONSTANT CFG_AHBRADDR : INTEGER := 16#A00#; --- Gaisler Ethernet core - CONSTANT CFG_GRETH : INTEGER := 0; - CONSTANT CFG_GRETH1G : INTEGER := 0; - CONSTANT CFG_ETH_FIFO : INTEGER := 8; - --- CAN 2.0 interface - CONSTANT CFG_CAN : INTEGER := 0; - CONSTANT CFG_CANIO : INTEGER := 16#0#; - CONSTANT CFG_CANIRQ : INTEGER := 0; - CONSTANT CFG_CANLOOP : INTEGER := 0; - CONSTANT CFG_CAN_SYNCRST : INTEGER := 0; - CONSTANT CFG_CANFT : INTEGER := 0; - --- PCI interface - CONSTANT CFG_PCI : INTEGER := 0; - CONSTANT CFG_PCIVID : INTEGER := 16#0#; - CONSTANT CFG_PCIDID : INTEGER := 16#0#; - CONSTANT CFG_PCIDEPTH : INTEGER := 8; - CONSTANT CFG_PCI_MTF : INTEGER := 1; - --- PCI arbiter - CONSTANT CFG_PCI_ARB : INTEGER := 0; - CONSTANT CFG_PCI_ARBAPB : INTEGER := 0; - CONSTANT CFG_PCI_ARB_NGNT : INTEGER := 4; - --- PCI trace buffer - CONSTANT CFG_PCITBUFEN : INTEGER := 0; - CONSTANT CFG_PCITBUF : INTEGER := 256; - --- Spacewire interface - CONSTANT CFG_SPW_EN : INTEGER := 0; - CONSTANT CFG_SPW_NUM : INTEGER := 1; - CONSTANT CFG_SPW_AHBFIFO : INTEGER := 4; - CONSTANT CFG_SPW_RXFIFO : INTEGER := 16; - CONSTANT CFG_SPW_RMAP : INTEGER := 0; - CONSTANT CFG_SPW_RMAPBUF : INTEGER := 4; - CONSTANT CFG_SPW_RMAPCRC : INTEGER := 0; - CONSTANT CFG_SPW_NETLIST : INTEGER := 0; - CONSTANT CFG_SPW_FT : INTEGER := 0; - CONSTANT CFG_SPW_GRSPW : INTEGER := 2; - CONSTANT CFG_SPW_RXUNAL : INTEGER := 0; - CONSTANT CFG_SPW_DMACHAN : INTEGER := 1; - CONSTANT CFG_SPW_PORTS : INTEGER := 1; - CONSTANT CFG_SPW_INPUT : INTEGER := 2; - CONSTANT CFG_SPW_OUTPUT : INTEGER := 0; - CONSTANT CFG_SPW_RTSAME : INTEGER := 0; --- UART 1 - CONSTANT CFG_UART1_ENABLE : INTEGER := 1; - CONSTANT CFG_UART1_FIFO : INTEGER := 4; - --- UART 2 - CONSTANT CFG_UART2_ENABLE : INTEGER := 0; - CONSTANT CFG_UART2_FIFO : INTEGER := 1; - --- LEON3 interrupt controller - CONSTANT CFG_IRQ3_ENABLE : INTEGER := 1; - CONSTANT CFG_IRQ3_NSEC : INTEGER := 0; - --- Modular timer - CONSTANT CFG_GPT_ENABLE : INTEGER := 1; - CONSTANT CFG_GPT_NTIM : INTEGER := (2); - CONSTANT CFG_GPT_SW : INTEGER := (8); - CONSTANT CFG_GPT_TW : INTEGER := (32); - CONSTANT CFG_GPT_IRQ : INTEGER := (8); - CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; - CONSTANT CFG_GPT_WDOGEN : INTEGER := 1; - CONSTANT CFG_GPT_WDOG : INTEGER := 16#FFFF#; - --- GPIO port - CONSTANT CFG_GRGPIO_ENABLE : INTEGER := 1; - CONSTANT CFG_GRGPIO_IMASK : INTEGER := 16#0000#; - CONSTANT CFG_GRGPIO_WIDTH : INTEGER := (8); - --- GRLIB debugging - CONSTANT CFG_DUART : INTEGER := 1; -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/ip_synthesis/lpp_top_lfr_wf_picker.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/ip_synthesis/lpp_top_lfr_wf_picker.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/ip_synthesis/lpp_top_lfr_wf_picker.vhd +++ /dev/null @@ -1,71110 +0,0 @@ --- Version: 9.1 SP5 9.1.5.1 - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_apbreg is - - port( status_full_ack : out std_logic_vector(3 downto 0); - prdata_c : out std_logic_vector(31 downto 0); - pirq_c : out std_logic_vector(15 to 15); - addr_data_f2 : out std_logic_vector(31 downto 0); - status_new_err_3 : in std_logic; - status_new_err_0_2 : in std_logic; - status_new_err_0_0 : in std_logic; - status_new_err_0_1 : in std_logic; - status_full_err_0 : in std_logic_vector(3 downto 0); - status_full : in std_logic_vector(3 downto 0); - addr_data_f3 : out std_logic_vector(31 downto 0); - nb_burst_available : out std_logic_vector(10 downto 0); - addr_data_f1 : out std_logic_vector(31 downto 0); - delta_f2_f1 : out std_logic_vector(9 downto 0); - addr_data_f0 : out std_logic_vector(31 downto 0); - delta_f2_f0 : out std_logic_vector(9 downto 0); - delta_snapshot : out std_logic_vector(15 downto 0); - nb_snapshot_param : out std_logic_vector(10 downto 0); - apbi_c_81 : in std_logic; - apbi_c_80 : in std_logic; - apbi_c_79 : in std_logic; - apbi_c_78 : in std_logic; - apbi_c_77 : in std_logic; - apbi_c_76 : in std_logic; - apbi_c_75 : in std_logic; - apbi_c_74 : in std_logic; - apbi_c_73 : in std_logic; - apbi_c_72 : in std_logic; - apbi_c_71 : in std_logic; - apbi_c_70 : in std_logic; - apbi_c_69 : in std_logic; - apbi_c_68 : in std_logic; - apbi_c_67 : in std_logic; - apbi_c_66 : in std_logic; - apbi_c_65 : in std_logic; - apbi_c_64 : in std_logic; - apbi_c_63 : in std_logic; - apbi_c_62 : in std_logic; - apbi_c_61 : in std_logic; - apbi_c_60 : in std_logic; - apbi_c_59 : in std_logic; - apbi_c_58 : in std_logic; - apbi_c_57 : in std_logic; - apbi_c_56 : in std_logic; - apbi_c_55 : in std_logic; - apbi_c_24 : in std_logic; - apbi_c_23 : in std_logic; - apbi_c_0 : in std_logic; - apbi_c_50 : in std_logic; - apbi_c_51 : in std_logic; - apbi_c_52 : in std_logic; - apbi_c_16 : in std_logic; - apbi_c_49 : in std_logic; - apbi_c_22 : in std_logic; - apbi_c_20 : in std_logic; - apbi_c_19 : in std_logic; - apbi_c_21 : in std_logic; - apbi_c_54 : in std_logic; - apbi_c_53 : in std_logic; - data_shaping_R0 : out std_logic; - data_shaping_R1 : out std_logic; - enable_f0 : out std_logic; - data_shaping_BW_c : out std_logic; - burst_f2 : out std_logic; - burst_f1 : out std_logic; - burst_f0 : out std_logic; - enable_f3 : out std_logic; - enable_f2 : out std_logic; - data_shaping_SP1 : out std_logic; - enable_f1 : out std_logic; - data_shaping_SP0 : out std_logic; - data_shaping_R1_0 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_shaping_R0_0 : out std_logic - ); - -end lpp_top_apbreg; - -architecture DEF_ARCH of lpp_top_apbreg is - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal data_shaping_BW_1_sqmuxa, prdata_9_sqmuxa_0, N_931, - prdata_10_sqmuxa_0, prdata_12_sqmuxa_0, N_168, N_157, - N_933_0, N_930, addr_matrix_f0_0_1_sqmuxa_0, N_159, N_928, - addr_matrix_f0_1_1_sqmuxa_0, N_166, - addr_matrix_f1_1_sqmuxa_0, N_172, - addr_matrix_f2_1_sqmuxa_0, un1_apbi_2, - addr_data_f0_1_sqmuxa_0, addr_data_f1_1_sqmuxa_0, - addr_data_f2_1_sqmuxa_0, addr_data_f3_1_sqmuxa_0, N_161_0, - prdata_2_sqmuxa_0, prdata_3_sqmuxa_0, prdata_4_sqmuxa_0, - prdata_5_sqmuxa_0, N_168_0, \prdata_39_0_iv_14[4]\, - \nb_burst_available_m_i[4]\, \prdata_39_0_iv_9[4]\, - data_shaping_R1_m_i, \prdata_39_0_iv_11[4]\, - \prdata_39_0_iv_3[4]\, burst_f0_m_i, - \prdata_39_0_iv_7[4]\, \prdata_39_0_iv_10[4]\, - prdata_18_sqmuxa, \prdata_39_0_iv_6[4]\, - \addr_data_f3_m_i[4]\, \addr_data_f2_m_i[4]\, - \prdata_39_0_iv_5[4]\, prdata_14_sqmuxa, - \prdata_39_0_iv_2[4]\, \addr_matrix_f0_1_m_i[4]\, - \addr_matrix_f0_0_m_i[4]\, \prdata_39_0_iv_1[4]\, - prdata_16_sqmuxa, \delta_f2_f1_m_i[4]\, - \addr_data_f1_m_i[4]\, \status_full_err[0]\, - prdata_13_sqmuxa, - status_error_anticipating_empty_fifo_m_i, - \addr_matrix_f1[4]\, \addr_matrix_f2_m_i[4]\, - \prdata_39_0_iv_13[3]\, \nb_snapshot_param_m_i[3]\, - \prdata_39_0_iv_6[3]\, \prdata_39_0_iv_11[3]\, - \prdata_39_0_iv_12[3]\, \prdata_39_0_iv_3[3]\, - \prdata_39_0_iv_2[3]\, \prdata_39_0_iv_9[3]\, - \delta_snapshot_m_i[3]\, \prdata_39_0_iv_1[3]\, - \nb_burst_available_m_i[3]\, \delta_f2_f0_m_i[3]\, - \addr_data_f3_m_i[3]\, \prdata_39_0_iv_5[3]\, - \addr_matrix_f0_1_m_i[3]\, \addr_matrix_f0_0_m_i[3]\, - \status_full_m_i[3]\, prdata_15_sqmuxa, enable_f3_m_i, - \addr_data_f2_m_i[3]\, status_ready_matrix_f2_m_i, - \addr_matrix_f1[3]\, \addr_matrix_f2_m_i[3]\, - \prdata_39_0_iv_14[1]\, \prdata_39_0_iv_7[1]\, - \prdata_39_0_iv_6[1]\, \prdata_39_0_iv_10[1]\, - \prdata_39_0_iv_13[1]\, \prdata_39_0_iv_4[1]\, - \prdata_39_0_iv_3[1]\, data_shaping_SP0_m_i, - \prdata_39_0_iv_12[1]\, prdata_17_sqmuxa, - \prdata_39_0_iv_8[1]\, \prdata_39_0_iv_5[1]\, - enable_f1_m_i, \addr_matrix_f2_m_i[1]\, - \addr_matrix_f1_m_i[1]\, \prdata_39_0_iv_2[1]\, - \addr_matrix_f0_1_m_i[1]\, \addr_matrix_f0_0_m_i[1]\, - \status_full_m_i[1]\, \delta_f2_f1_m_i[1]\, - \addr_data_f2_m_i[1]\, \addr_data_f1_m_i[1]\, - prdata_0_sqmuxa, config_active_interruption_onError, - status_ready_matrix_f0_1_m_i, \prdata_39_0_iv_13[2]\, - \prdata_39_0_iv_6[2]\, \nb_snapshot_param_m_i[2]\, - data_shaping_SP1_m_i, \prdata_39_0_iv_12[2]\, - \prdata_39_0_iv_3[2]\, \prdata_39_0_iv_2[2]\, - \prdata_39_0_iv_9[2]\, \prdata_39_0_iv_11[2]\, - \prdata_39_0_iv_7[2]\, \status_full_m_i[2]\, - \delta_f2_f1_m_i[2]\, \prdata_39_0_iv_4[2]\, - enable_f2_m_i, \addr_matrix_f0_1_m_i[2]\, - \addr_matrix_f0_0_m_i[2]\, \prdata_39_0_iv_1[2]\, - \delta_f2_f0_m_i[2]\, \addr_data_f2_m_i[2]\, - status_ready_matrix_f1_m_i, \addr_matrix_f1[2]\, - \addr_matrix_f2_m_i[2]\, \prdata_39_0_iv_12[5]\, - \prdata_39_0_iv_5[5]\, \prdata_39_0_iv_4[5]\, - \nb_burst_available_m_i[5]\, \prdata_39_0_iv_11[5]\, - \prdata_39_0_iv_3[5]\, burst_f1_m_i, - \prdata_39_0_iv_7[5]\, \prdata_39_0_iv_10[5]\, - \prdata_39_0_iv_6[5]\, \prdata_39_0_iv_2[5]\, - \addr_matrix_f0_1_m_i[5]\, \addr_matrix_f0_0_m_i[5]\, - \prdata_39_0_iv_1[5]\, \delta_f2_f1_m_i[5]\, - \addr_data_f2_m_i[5]\, \addr_data_f1_m_i[5]\, - \status_full_err[1]\, - status_error_bad_component_error_m_i, \addr_matrix_f1[5]\, - \addr_matrix_f2_m_i[5]\, \prdata_39_0_iv_10[8]\, - \prdata_39_0_iv_3[8]\, \prdata_39_0_iv_2[8]\, - \nb_burst_available_m_i[8]\, \prdata_39_0_iv_9[8]\, - \prdata_39_0_iv_0[8]\, \delta_f2_f1_m_i[8]\, - \prdata_39_0_iv_6[8]\, \prdata_39_0_iv_8[8]\, - \delta_f2_f0_m_i[8]\, \addr_data_f3_m_i[8]\, - \nb_snapshot_param_m_i[8]\, \addr_matrix_f2_m_i[8]\, - \addr_matrix_f1_m_i[8]\, \delta_snapshot_m_i[8]\, - \addr_data_f2_m_i[8]\, \status_new_err[0]\, - \addr_data_f0_m_i[8]\, \addr_matrix_f0_0[8]\, - \addr_matrix_f0_1_m_i[8]\, \prdata_39_0_iv_14[0]\, - \prdata_39_0_iv_4[0]\, \prdata_39_0_iv_3[0]\, - \prdata_39_0_iv_11[0]\, \prdata_39_0_iv_13[0]\, - \delta_snapshot_m_i[0]\, \prdata_39_0_iv_2[0]\, - \prdata_39_0_iv_9[0]\, \prdata_39_0_iv_12[0]\, - \prdata_39_0_iv_7[0]\, \status_full_m_i[0]\, - \delta_f2_f1_m_i[0]\, \prdata_39_0_iv_5[0]\, - enable_f0_m_i, \addr_matrix_f0_1_m_i[0]\, - \addr_matrix_f0_0_m_i[0]\, \prdata_39_0_iv_1[0]\, - data_shaping_BW_m_i, \addr_data_f2_m_i[0]\, - \addr_data_f1_m_i[0]\, - config_active_interruption_onNewMatrix, - status_ready_matrix_f0_0_m_i, \addr_matrix_f1[0]\, - \addr_matrix_f2_m_i[0]\, \prdata_39_0_iv_11[6]\, - \prdata_39_0_iv_3[6]\, \prdata_39_0_iv_2[6]\, - \prdata_39_0_iv_8[6]\, \prdata_39_0_iv_10[6]\, - \prdata_39_0_iv_6[6]\, \prdata_39_0_iv_9[6]\, - \prdata_39_0_iv_5[6]\, \delta_f2_f0_m_i[6]\, - \addr_data_f3_m_i[6]\, burst_f2_m_i, - \addr_matrix_f2_m_i[6]\, \addr_matrix_f1_m_i[6]\, - \delta_snapshot_m_i[6]\, \addr_matrix_f0_1_m_i[6]\, - \addr_matrix_f0_0_m_i[6]\, \delta_f2_f1_m_i[6]\, - \addr_data_f2_m_i[6]\, \status_full_err[2]\, - \addr_data_f0_m_i[6]\, \prdata_39_0_iv_10[7]\, - \prdata_39_0_iv_3[7]\, \prdata_39_0_iv_2[7]\, - \nb_burst_available_m_i[7]\, \prdata_39_0_iv_9[7]\, - \delta_snapshot_m_i[7]\, \prdata_39_0_iv_1[7]\, - \prdata_39_0_iv_5[7]\, \prdata_39_0_iv_8[7]\, - \delta_f2_f0_m_i[7]\, \addr_data_f3_m_i[7]\, - \nb_snapshot_param_m_i[7]\, \addr_matrix_f0_1_m_i[7]\, - \addr_matrix_f0_0_m_i[7]\, \delta_f2_f1_m_i[7]\, - \addr_data_f2_m_i[7]\, \status_full_err[3]\, - \addr_data_f0_m_i[7]\, \addr_matrix_f1[7]\, - \addr_matrix_f2_m_i[7]\, \prdata_39_0_iv_10[9]\, - \prdata_39_0_iv_3[9]\, \prdata_39_0_iv_2[9]\, - \nb_burst_available_m_i[9]\, \prdata_39_0_iv_9[9]\, - \delta_snapshot_m_i[9]\, \prdata_39_0_iv_1[9]\, - \prdata_39_0_iv_5[9]\, \prdata_39_0_iv_8[9]\, - \delta_f2_f0_m_i[9]\, \addr_data_f3_m_i[9]\, - \nb_snapshot_param_m_i[9]\, \addr_matrix_f0_1_m_i[9]\, - \addr_matrix_f0_0_m_i[9]\, \delta_f2_f1_m_i[9]\, - \addr_data_f2_m_i[9]\, \status_new_err[1]\, - \addr_data_f0_m_i[9]\, \addr_matrix_f1[9]\, - \addr_matrix_f2_m_i[9]\, \prdata_39_0_iv_8[10]\, - \prdata_39_0_iv_2[10]\, \nb_snapshot_param_m_i[10]\, - \prdata_39_0_iv_5[10]\, \prdata_39_0_iv_7[10]\, - \prdata_39_0_iv_0[10]\, \addr_data_f3_m_i[10]\, - \prdata_39_0_iv_3[10]\, \prdata_39_0_iv_1[10]\, - \addr_data_f2_m_i[10]\, \status_new_err[2]\, - \addr_data_f0_m_i[10]\, \addr_matrix_f1[10]\, - \addr_matrix_f2_m_i[10]\, \addr_matrix_f0_0[10]\, - \addr_matrix_f0_1_m_i[10]\, \prdata_39_0_iv_6[11]\, - \addr_data_f0_m_i[11]\, \status_new_err_m_i[3]\, - \prdata_39_0_iv_3[11]\, \prdata_39_0_iv_5[11]\, - \prdata_39_0_iv_1[11]\, \prdata_39_0_iv_4[11]\, - \addr_matrix_f0_1_m_i[11]\, \addr_matrix_f0_0_m_i[11]\, - \addr_data_f3_m_i[11]\, \addr_data_f2_m_i[11]\, - \addr_matrix_f1[11]\, \addr_matrix_f2_m_i[11]\, - \prdata_39_0_iv_6[12]\, \prdata_39_0_iv_1[12]\, - \prdata_39_0_iv_0[12]\, \prdata_39_0_iv_3[12]\, - \addr_data_f2_m_i[12]\, \prdata_39_0_iv_2[12]\, - \addr_data_f1_m_i[12]\, \addr_matrix_f1[12]\, - \addr_matrix_f2_m_i[12]\, \addr_matrix_f0_0[12]\, - \addr_matrix_f0_1_m_i[12]\, \prdata_39_0_iv_6[13]\, - \prdata_39_0_iv_1[13]\, \prdata_39_0_iv_0[13]\, - \prdata_39_0_iv_3[13]\, \addr_data_f2_m_i[13]\, - \prdata_39_0_iv_2[13]\, \addr_data_f1_m_i[13]\, - \addr_matrix_f1[13]\, \addr_matrix_f2_m_i[13]\, - \addr_matrix_f0_0[13]\, \addr_matrix_f0_1_m_i[13]\, - \prdata_39_0_iv_6[14]\, \prdata_39_0_iv_1[14]\, - \prdata_39_0_iv_0[14]\, \prdata_39_0_iv_3[14]\, - \addr_data_f2_m_i[14]\, \prdata_39_0_iv_2[14]\, - \addr_data_f1_m_i[14]\, \addr_matrix_f1[14]\, - \addr_matrix_f2_m_i[14]\, \addr_matrix_f0_0[14]\, - \addr_matrix_f0_1_m_i[14]\, \prdata_39_0_iv_5[15]\, - \addr_data_f1_m_i[15]\, \addr_data_f0_m_i[15]\, - \delta_snapshot_m_i[15]\, \prdata_39_0_iv_4[15]\, - \addr_matrix_f0_1_m_i[15]\, \addr_matrix_f0_0_m_i[15]\, - \prdata_39_0_iv_1[15]\, \prdata_39_0_iv_3[15]\, - \addr_data_f2_m_i[15]\, \addr_matrix_f1[15]\, - \addr_matrix_f2_m_i[15]\, \prdata_39_0_iv_4[16]\, - \addr_matrix_f0_1_m_i[16]\, \addr_matrix_f0_0_m_i[16]\, - \prdata_39_0_iv_1[16]\, \prdata_39_0_iv_3[16]\, - \addr_data_f2_m_i[16]\, \prdata_39_0_iv_2[16]\, - \addr_data_f1_m_i[16]\, \addr_matrix_f1[16]\, - \addr_matrix_f2_m_i[16]\, \prdata_39_0_iv_4[17]\, - \addr_matrix_f0_1_m_i[17]\, \addr_matrix_f0_0_m_i[17]\, - \prdata_39_0_iv_1[17]\, \prdata_39_0_iv_3[17]\, - \addr_data_f2_m_i[17]\, \prdata_39_0_iv_2[17]\, - \addr_data_f1_m_i[17]\, \addr_matrix_f1[17]\, - \addr_matrix_f2_m_i[17]\, \prdata_39_0_iv_5[18]\, - \addr_data_f3_m_i[18]\, \addr_data_f2_m_i[18]\, - \prdata_39_0_iv_2[18]\, \addr_data_f1_m_i[18]\, - \prdata_39_0_iv_1[18]\, \addr_matrix_f1[18]\, - \addr_matrix_f2_m_i[18]\, \prdata_39_0_iv_0[18]\, - \addr_matrix_f0_0[18]\, \addr_matrix_f0_1_m_i[18]\, - \prdata_39_0_iv_4[19]\, \addr_matrix_f0_1_m_i[19]\, - \addr_matrix_f0_0_m_i[19]\, \prdata_39_0_iv_1[19]\, - \prdata_39_0_iv_3[19]\, \addr_data_f2_m_i[19]\, - \prdata_39_0_iv_2[19]\, \addr_data_f1_m_i[19]\, - prdata_4_sqmuxa, \addr_matrix_f1[19]\, - \addr_matrix_f2_m_i[19]\, \prdata_39_0_iv_4[20]\, - \addr_matrix_f0_1_m_i[20]\, \addr_matrix_f0_0_m_i[20]\, - \prdata_39_0_iv_1[20]\, \prdata_39_0_iv_3[20]\, - \addr_data_f2_m_i[20]\, \prdata_39_0_iv_2[20]\, - \addr_data_f1_m_i[20]\, \addr_matrix_f1[20]\, - \addr_matrix_f2_m_i[20]\, \prdata_39_0_iv_5[21]\, - \addr_data_f3_m_i[21]\, \addr_data_f2_m_i[21]\, - \prdata_39_0_iv_2[21]\, \addr_data_f1_m_i[21]\, - \prdata_39_0_iv_1[21]\, \addr_matrix_f1[21]\, - \addr_matrix_f2_m_i[21]\, \prdata_39_0_iv_0[21]\, - \addr_matrix_f0_0[21]\, \addr_matrix_f0_1_m_i[21]\, - \prdata_39_0_iv_4[22]\, \addr_matrix_f0_1_m_i[22]\, - \addr_matrix_f0_0_m_i[22]\, \prdata_39_0_iv_1[22]\, - \prdata_39_0_iv_3[22]\, \addr_data_f2_m_i[22]\, - \prdata_39_0_iv_2[22]\, \addr_data_f1_m_i[22]\, - \addr_matrix_f1[22]\, \addr_matrix_f2_m_i[22]\, - \prdata_39_0_iv_5[23]\, \addr_data_f3_m_i[23]\, - \addr_data_f2_m_i[23]\, \prdata_39_0_iv_2[23]\, - prdata_9_sqmuxa, \addr_data_f1_m_i[23]\, - \prdata_39_0_iv_1[23]\, \addr_matrix_f1[23]\, - \addr_matrix_f2_m_i[23]\, \prdata_39_0_iv_0[23]\, - \addr_matrix_f0_0[23]\, \addr_matrix_f0_1_m_i[23]\, - \prdata_39_0_iv_4[24]\, \addr_matrix_f0_1_m_i[24]\, - \addr_matrix_f0_0_m_i[24]\, \prdata_39_0_iv_1[24]\, - \prdata_39_0_iv_3[24]\, \addr_data_f2_m_i[24]\, - \prdata_39_0_iv_2[24]\, \addr_data_f1_m_i[24]\, - \addr_matrix_f1[24]\, \addr_matrix_f2_m_i[24]\, - \prdata_39_0_iv_4[25]\, \addr_matrix_f0_1_m_i[25]\, - \addr_matrix_f0_0_m_i[25]\, \prdata_39_0_iv_1[25]\, - \prdata_39_0_iv_3[25]\, \addr_data_f2_m_i[25]\, - \prdata_39_0_iv_2[25]\, \addr_data_f1_m_i[25]\, - \addr_matrix_f1[25]\, \addr_matrix_f2_m_i[25]\, - \prdata_39_0_iv_4[26]\, \addr_matrix_f0_1_m_i[26]\, - \addr_matrix_f0_0_m_i[26]\, \prdata_39_0_iv_1[26]\, - \prdata_39_0_iv_3[26]\, \addr_data_f2_m_i[26]\, - \prdata_39_0_iv_2[26]\, \addr_data_f1_m_i[26]\, - \addr_matrix_f1[26]\, \addr_matrix_f2_m_i[26]\, - \prdata_39_0_iv_4[27]\, \addr_matrix_f0_1_m_i[27]\, - \addr_matrix_f0_0_m_i[27]\, \prdata_39_0_iv_1[27]\, - \prdata_39_0_iv_3[27]\, prdata_12_sqmuxa, - \addr_data_f2_m_i[27]\, \prdata_39_0_iv_2[27]\, - \addr_data_f1_m_i[27]\, \addr_matrix_f1[27]\, - \addr_matrix_f2_m_i[27]\, \prdata_39_0_iv_4[28]\, - \addr_matrix_f0_1_m_i[28]\, \addr_matrix_f0_0_m_i[28]\, - \prdata_39_0_iv_1[28]\, \prdata_39_0_iv_3[28]\, - \addr_data_f2_m_i[28]\, \prdata_39_0_iv_2[28]\, - \addr_data_f1_m_i[28]\, \addr_matrix_f1[28]\, - \addr_matrix_f2_m_i[28]\, \prdata_39_0_iv_4[29]\, - \addr_matrix_f0_1_m_i[29]\, \addr_matrix_f0_0_m_i[29]\, - \prdata_39_0_iv_1[29]\, \prdata_39_0_iv_3[29]\, - \addr_data_f2_m_i[29]\, \prdata_39_0_iv_2[29]\, - \addr_data_f1_m_i[29]\, \addr_matrix_f1[29]\, - \addr_matrix_f2_m_i[29]\, \prdata_39_0_iv_4[30]\, - \addr_matrix_f0_1_m_i[30]\, \addr_matrix_f0_0_m_i[30]\, - \prdata_39_0_iv_1[30]\, \prdata_39_0_iv_3[30]\, - \addr_data_f2_m_i[30]\, \prdata_39_0_iv_2[30]\, - \addr_data_f1_m_i[30]\, \addr_matrix_f1[30]\, - \addr_matrix_f2_m_i[30]\, \prdata_39_0_iv_4[31]\, - \addr_matrix_f0_1_m_i[31]\, \addr_matrix_f0_0_m_i[31]\, - \prdata_39_0_iv_1[31]\, \prdata_39_0_iv_3[31]\, - \addr_data_f2_m_i[31]\, \prdata_39_0_iv_2[31]\, - \addr_data_f1_m_i[31]\, \addr_matrix_f1[31]\, - \addr_matrix_f2_m_i[31]\, \pirq_2_i_a2_8[15]\, - \pirq_2_i_a2_5[15]\, \pirq_2_i_a2_7[15]\, - \pirq_2_i_a2_3[15]\, \pirq_2_i_a2_6[15]\, - \pirq_2_i_a2_1[15]\, N_153, \status_new_err_0[3]\, N_151, - N_149, N_147, N_145, N_143, N_141, N_139, N_137, - \status_full_0[2]\, N_136, \status_full_0[1]\, N_135, - \status_full_0[0]\, \prdata_39[31]\, \prdata_39[30]\, - \prdata_39[29]\, \prdata_39[28]\, \prdata_39[27]\, - \prdata_39[26]\, \prdata_39[25]\, \prdata_39[24]\, - \prdata_39[23]\, \prdata_39[22]\, \prdata_39[21]\, - \prdata_39[20]\, \prdata_39[19]\, \prdata_39[18]\, - \prdata_39[17]\, \prdata_39[16]\, \prdata_39[15]\, - \prdata_39[14]\, \delta_snapshot_m_i[14]\, - \prdata_39[13]\, \delta_snapshot_m_i[13]\, - \prdata_39[11]\, \prdata_39[10]\, - \nb_burst_available_m_i[10]\, \prdata_39[9]\, - \prdata_39[8]\, \prdata_39[7]\, \prdata_39[6]\, - \prdata_39[5]\, \prdata_39[4]\, \prdata_39[3]\, - data_shaping_R0_m_i, \prdata_39[2]\, \prdata_39[1]\, - \prdata_39[0]\, \prdata_39[12]\, \delta_snapshot_m_i[12]\, - N_155_i_0, N_138, \status_full_0[3]\, - status_ready_matrix_f0_1, N_169, \addr_matrix_f0_0[1]\, - \addr_matrix_f0_1[1]\, \addr_matrix_f1[1]\, - \addr_matrix_f2[1]\, N_163, prdata_8_sqmuxa, - status_ready_matrix_f1, \addr_matrix_f0_0[2]\, - \addr_matrix_f0_1[2]\, \addr_matrix_f2[2]\, - status_ready_matrix_f2, \addr_matrix_f0_0[3]\, - \addr_matrix_f0_1[3]\, \addr_matrix_f2[3]\, - \data_shaping_R0_0\, status_error_anticipating_empty_fifo, - \addr_matrix_f0_0[4]\, \addr_matrix_f0_1[4]\, - \addr_matrix_f2[4]\, \data_shaping_R1_0\, - status_error_bad_component_error, \addr_matrix_f0_0[5]\, - \addr_matrix_f0_1[5]\, \addr_matrix_f2[5]\, - \addr_matrix_f0_0[6]\, \addr_matrix_f0_1[6]\, - \addr_matrix_f1[6]\, \addr_matrix_f2[6]\, - \addr_matrix_f0_0[7]\, \addr_matrix_f0_1[7]\, - \addr_matrix_f2[7]\, \addr_matrix_f0_1[8]\, - \addr_matrix_f1[8]\, \addr_matrix_f2[8]\, - \addr_matrix_f0_0[9]\, \addr_matrix_f0_1[9]\, - \addr_matrix_f2[9]\, \addr_matrix_f0_1[10]\, - \addr_matrix_f2[10]\, prdata_2_sqmuxa, - \addr_matrix_f0_0[11]\, \addr_matrix_f0_1[11]\, - \addr_matrix_f2[11]\, \addr_matrix_f0_1[12]\, - \addr_matrix_f2[12]\, \addr_matrix_f0_1[13]\, - \addr_matrix_f2[13]\, \addr_matrix_f0_1[14]\, - \addr_matrix_f2[14]\, \addr_matrix_f0_0[15]\, - \addr_matrix_f0_1[15]\, \addr_matrix_f2[15]\, - \addr_matrix_f0_0[16]\, \addr_matrix_f0_1[16]\, - \addr_matrix_f2[16]\, \addr_matrix_f0_0[17]\, - prdata_3_sqmuxa, \addr_matrix_f0_1[17]\, prdata_5_sqmuxa, - \addr_matrix_f2[17]\, N_161, \addr_matrix_f0_1[18]\, - \addr_matrix_f2[18]\, prdata_10_sqmuxa, - \addr_matrix_f0_0[19]\, \addr_matrix_f0_1[19]\, - \addr_matrix_f2[19]\, \addr_matrix_f0_0[20]\, - \addr_matrix_f0_1[20]\, \addr_matrix_f2[20]\, - \addr_matrix_f0_1[21]\, \addr_matrix_f2[21]\, - \addr_matrix_f0_0[22]\, \addr_matrix_f0_1[22]\, - \addr_matrix_f2[22]\, \addr_matrix_f0_1[23]\, - \addr_matrix_f2[23]\, \addr_matrix_f0_0[24]\, - \addr_matrix_f0_1[24]\, \addr_matrix_f2[24]\, - \addr_matrix_f0_0[25]\, \addr_matrix_f0_1[25]\, - \addr_matrix_f2[25]\, \addr_matrix_f0_0[26]\, - \addr_matrix_f0_1[26]\, \addr_matrix_f2[26]\, - \addr_matrix_f0_0[27]\, \addr_matrix_f0_1[27]\, - \addr_matrix_f2[27]\, \addr_matrix_f0_0[28]\, - \addr_matrix_f0_1[28]\, \addr_matrix_f2[28]\, - \addr_matrix_f0_0[29]\, \addr_matrix_f0_1[29]\, - \addr_matrix_f2[29]\, \addr_matrix_f0_0[30]\, - \addr_matrix_f0_1[30]\, \addr_matrix_f2[30]\, - \addr_matrix_f0_0[31]\, \addr_matrix_f0_1[31]\, - \addr_matrix_f2[31]\, addr_matrix_f0_0_1_sqmuxa, - addr_matrix_f0_1_1_sqmuxa, addr_matrix_f1_1_sqmuxa, - addr_matrix_f2_1_sqmuxa, addr_data_f0_1_sqmuxa, - addr_data_f1_1_sqmuxa, addr_data_f2_1_sqmuxa, - addr_data_f3_1_sqmuxa, burst_f0_1_sqmuxa, - delta_f2_f0_1_sqmuxa, N_164, delta_f2_f1_1_sqmuxa, - delta_snapshot_1_sqmuxa, nb_burst_available_1_sqmuxa, - N_158, nb_snapshot_param_1_sqmuxa, \status_full_ack_8[2]\, - \status_full_ack_8[1]\, \status_full_ack_8[0]\, - \status_full_5_i_o2[0]\, \status_full_RNO[0]\, - \status_full_RNO[1]\, \status_full_RNO[2]\, - \status_full_err_RNO[0]\, \status_full_err_RNO[1]\, - \status_full_err_RNO[2]\, \status_full_err_RNO[3]\, - \status_new_err_RNO[0]\, \status_new_err_RNO[1]\, - \status_new_err_RNO[2]\, \status_new_err_RNO[3]\, - status_error_anticipating_empty_fifo_1_sqmuxa, - config_active_interruption_onError_0_sqmuxa, - \addr_matrix_f2[0]\, \addr_matrix_f0_1[0]\, - \addr_matrix_f0_0[0]\, status_ready_matrix_f0_0, - \status_full_ack_8[3]\, \status_full_RNO[3]\, \enable_f3\, - \enable_f2\, \enable_f1\, \enable_f0\, \data_shaping_SP1\, - \data_shaping_SP0\, \data_shaping_BW_c\, \burst_f2\, - \burst_f1\, \burst_f0\, \addr_data_f1[0]\, - \addr_data_f1[1]\, \addr_data_f1[2]\, \addr_data_f1[3]\, - \addr_data_f1[4]\, \addr_data_f1[5]\, \addr_data_f1[6]\, - \addr_data_f1[7]\, \addr_data_f1[8]\, \addr_data_f1[9]\, - \addr_data_f1[10]\, \addr_data_f1[11]\, - \addr_data_f1[12]\, \addr_data_f1[13]\, - \addr_data_f1[14]\, \addr_data_f1[15]\, - \addr_data_f1[16]\, \addr_data_f1[17]\, - \addr_data_f1[18]\, \addr_data_f1[19]\, - \addr_data_f1[20]\, \addr_data_f1[21]\, - \addr_data_f1[22]\, \addr_data_f1[23]\, - \addr_data_f1[24]\, \addr_data_f1[25]\, - \addr_data_f1[26]\, \addr_data_f1[27]\, - \addr_data_f1[28]\, \addr_data_f1[29]\, - \addr_data_f1[30]\, \addr_data_f1[31]\, \addr_data_f0[0]\, - \addr_data_f0[1]\, \addr_data_f0[2]\, \addr_data_f0[3]\, - \addr_data_f0[4]\, \addr_data_f0[5]\, \addr_data_f0[6]\, - \addr_data_f0[7]\, \addr_data_f0[8]\, \addr_data_f0[9]\, - \addr_data_f0[10]\, \addr_data_f0[11]\, - \addr_data_f0[12]\, \addr_data_f0[13]\, - \addr_data_f0[14]\, \addr_data_f0[15]\, - \addr_data_f0[16]\, \addr_data_f0[17]\, - \addr_data_f0[18]\, \addr_data_f0[19]\, - \addr_data_f0[20]\, \addr_data_f0[21]\, - \addr_data_f0[22]\, \addr_data_f0[23]\, - \addr_data_f0[24]\, \addr_data_f0[25]\, - \addr_data_f0[26]\, \addr_data_f0[27]\, - \addr_data_f0[28]\, \addr_data_f0[29]\, - \addr_data_f0[30]\, \addr_data_f0[31]\, - \delta_snapshot[0]\, \delta_snapshot[1]\, - \delta_snapshot[2]\, \delta_snapshot[3]\, - \delta_snapshot[4]\, \delta_snapshot[5]\, - \delta_snapshot[6]\, \delta_snapshot[7]\, - \delta_snapshot[8]\, \delta_snapshot[9]\, - \delta_snapshot[10]\, \delta_snapshot[11]\, - \delta_snapshot[12]\, \delta_snapshot[13]\, - \delta_snapshot[14]\, \delta_snapshot[15]\, - \nb_snapshot_param[0]\, \nb_snapshot_param[1]\, - \nb_snapshot_param[2]\, \nb_snapshot_param[3]\, - \nb_snapshot_param[4]\, \nb_snapshot_param[5]\, - \nb_snapshot_param[6]\, \nb_snapshot_param[7]\, - \nb_snapshot_param[8]\, \nb_snapshot_param[9]\, - \nb_snapshot_param[10]\, \nb_burst_available[0]\, - \nb_burst_available[1]\, \nb_burst_available[2]\, - \nb_burst_available[3]\, \nb_burst_available[4]\, - \nb_burst_available[5]\, \nb_burst_available[6]\, - \nb_burst_available[7]\, \nb_burst_available[8]\, - \nb_burst_available[9]\, \nb_burst_available[10]\, - \delta_f2_f1[0]\, \delta_f2_f1[1]\, \delta_f2_f1[2]\, - \delta_f2_f1[3]\, \delta_f2_f1[4]\, \delta_f2_f1[5]\, - \delta_f2_f1[6]\, \delta_f2_f1[7]\, \delta_f2_f1[8]\, - \delta_f2_f1[9]\, \delta_f2_f0[0]\, \delta_f2_f0[1]\, - \delta_f2_f0[2]\, \delta_f2_f0[3]\, \delta_f2_f0[4]\, - \delta_f2_f0[5]\, \delta_f2_f0[6]\, \delta_f2_f0[7]\, - \delta_f2_f0[8]\, \delta_f2_f0[9]\, \addr_data_f3[0]\, - \addr_data_f3[1]\, \addr_data_f3[2]\, \addr_data_f3[3]\, - \addr_data_f3[4]\, \addr_data_f3[5]\, \addr_data_f3[6]\, - \addr_data_f3[7]\, \addr_data_f3[8]\, \addr_data_f3[9]\, - \addr_data_f3[10]\, \addr_data_f3[11]\, - \addr_data_f3[12]\, \addr_data_f3[13]\, - \addr_data_f3[14]\, \addr_data_f3[15]\, - \addr_data_f3[16]\, \addr_data_f3[17]\, - \addr_data_f3[18]\, \addr_data_f3[19]\, - \addr_data_f3[20]\, \addr_data_f3[21]\, - \addr_data_f3[22]\, \addr_data_f3[23]\, - \addr_data_f3[24]\, \addr_data_f3[25]\, - \addr_data_f3[26]\, \addr_data_f3[27]\, - \addr_data_f3[28]\, \addr_data_f3[29]\, - \addr_data_f3[30]\, \addr_data_f3[31]\, \addr_data_f2[0]\, - \addr_data_f2[1]\, \addr_data_f2[2]\, \addr_data_f2[3]\, - \addr_data_f2[4]\, \addr_data_f2[5]\, \addr_data_f2[6]\, - \addr_data_f2[7]\, \addr_data_f2[8]\, \addr_data_f2[9]\, - \addr_data_f2[10]\, \addr_data_f2[11]\, - \addr_data_f2[12]\, \addr_data_f2[13]\, - \addr_data_f2[14]\, \addr_data_f2[15]\, - \addr_data_f2[16]\, \addr_data_f2[17]\, - \addr_data_f2[18]\, \addr_data_f2[19]\, - \addr_data_f2[20]\, \addr_data_f2[21]\, - \addr_data_f2[22]\, \addr_data_f2[23]\, - \addr_data_f2[24]\, \addr_data_f2[25]\, - \addr_data_f2[26]\, \addr_data_f2[27]\, - \addr_data_f2[28]\, \addr_data_f2[29]\, - \addr_data_f2[30]\, \addr_data_f2[31]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - addr_data_f2(31) <= \addr_data_f2[31]\; - addr_data_f2(30) <= \addr_data_f2[30]\; - addr_data_f2(29) <= \addr_data_f2[29]\; - addr_data_f2(28) <= \addr_data_f2[28]\; - addr_data_f2(27) <= \addr_data_f2[27]\; - addr_data_f2(26) <= \addr_data_f2[26]\; - addr_data_f2(25) <= \addr_data_f2[25]\; - addr_data_f2(24) <= \addr_data_f2[24]\; - addr_data_f2(23) <= \addr_data_f2[23]\; - addr_data_f2(22) <= \addr_data_f2[22]\; - addr_data_f2(21) <= \addr_data_f2[21]\; - addr_data_f2(20) <= \addr_data_f2[20]\; - addr_data_f2(19) <= \addr_data_f2[19]\; - addr_data_f2(18) <= \addr_data_f2[18]\; - addr_data_f2(17) <= \addr_data_f2[17]\; - addr_data_f2(16) <= \addr_data_f2[16]\; - addr_data_f2(15) <= \addr_data_f2[15]\; - addr_data_f2(14) <= \addr_data_f2[14]\; - addr_data_f2(13) <= \addr_data_f2[13]\; - addr_data_f2(12) <= \addr_data_f2[12]\; - addr_data_f2(11) <= \addr_data_f2[11]\; - addr_data_f2(10) <= \addr_data_f2[10]\; - addr_data_f2(9) <= \addr_data_f2[9]\; - addr_data_f2(8) <= \addr_data_f2[8]\; - addr_data_f2(7) <= \addr_data_f2[7]\; - addr_data_f2(6) <= \addr_data_f2[6]\; - addr_data_f2(5) <= \addr_data_f2[5]\; - addr_data_f2(4) <= \addr_data_f2[4]\; - addr_data_f2(3) <= \addr_data_f2[3]\; - addr_data_f2(2) <= \addr_data_f2[2]\; - addr_data_f2(1) <= \addr_data_f2[1]\; - addr_data_f2(0) <= \addr_data_f2[0]\; - addr_data_f3(31) <= \addr_data_f3[31]\; - addr_data_f3(30) <= \addr_data_f3[30]\; - addr_data_f3(29) <= \addr_data_f3[29]\; - addr_data_f3(28) <= \addr_data_f3[28]\; - addr_data_f3(27) <= \addr_data_f3[27]\; - addr_data_f3(26) <= \addr_data_f3[26]\; - addr_data_f3(25) <= \addr_data_f3[25]\; - addr_data_f3(24) <= \addr_data_f3[24]\; - addr_data_f3(23) <= \addr_data_f3[23]\; - addr_data_f3(22) <= \addr_data_f3[22]\; - addr_data_f3(21) <= \addr_data_f3[21]\; - addr_data_f3(20) <= \addr_data_f3[20]\; - addr_data_f3(19) <= \addr_data_f3[19]\; - addr_data_f3(18) <= \addr_data_f3[18]\; - addr_data_f3(17) <= \addr_data_f3[17]\; - addr_data_f3(16) <= \addr_data_f3[16]\; - addr_data_f3(15) <= \addr_data_f3[15]\; - addr_data_f3(14) <= \addr_data_f3[14]\; - addr_data_f3(13) <= \addr_data_f3[13]\; - addr_data_f3(12) <= \addr_data_f3[12]\; - addr_data_f3(11) <= \addr_data_f3[11]\; - addr_data_f3(10) <= \addr_data_f3[10]\; - addr_data_f3(9) <= \addr_data_f3[9]\; - addr_data_f3(8) <= \addr_data_f3[8]\; - addr_data_f3(7) <= \addr_data_f3[7]\; - addr_data_f3(6) <= \addr_data_f3[6]\; - addr_data_f3(5) <= \addr_data_f3[5]\; - addr_data_f3(4) <= \addr_data_f3[4]\; - addr_data_f3(3) <= \addr_data_f3[3]\; - addr_data_f3(2) <= \addr_data_f3[2]\; - addr_data_f3(1) <= \addr_data_f3[1]\; - addr_data_f3(0) <= \addr_data_f3[0]\; - nb_burst_available(10) <= \nb_burst_available[10]\; - nb_burst_available(9) <= \nb_burst_available[9]\; - nb_burst_available(8) <= \nb_burst_available[8]\; - nb_burst_available(7) <= \nb_burst_available[7]\; - nb_burst_available(6) <= \nb_burst_available[6]\; - nb_burst_available(5) <= \nb_burst_available[5]\; - nb_burst_available(4) <= \nb_burst_available[4]\; - nb_burst_available(3) <= \nb_burst_available[3]\; - nb_burst_available(2) <= \nb_burst_available[2]\; - nb_burst_available(1) <= \nb_burst_available[1]\; - nb_burst_available(0) <= \nb_burst_available[0]\; - addr_data_f1(31) <= \addr_data_f1[31]\; - addr_data_f1(30) <= \addr_data_f1[30]\; - addr_data_f1(29) <= \addr_data_f1[29]\; - addr_data_f1(28) <= \addr_data_f1[28]\; - addr_data_f1(27) <= \addr_data_f1[27]\; - addr_data_f1(26) <= \addr_data_f1[26]\; - addr_data_f1(25) <= \addr_data_f1[25]\; - addr_data_f1(24) <= \addr_data_f1[24]\; - addr_data_f1(23) <= \addr_data_f1[23]\; - addr_data_f1(22) <= \addr_data_f1[22]\; - addr_data_f1(21) <= \addr_data_f1[21]\; - addr_data_f1(20) <= \addr_data_f1[20]\; - addr_data_f1(19) <= \addr_data_f1[19]\; - addr_data_f1(18) <= \addr_data_f1[18]\; - addr_data_f1(17) <= \addr_data_f1[17]\; - addr_data_f1(16) <= \addr_data_f1[16]\; - addr_data_f1(15) <= \addr_data_f1[15]\; - addr_data_f1(14) <= \addr_data_f1[14]\; - addr_data_f1(13) <= \addr_data_f1[13]\; - addr_data_f1(12) <= \addr_data_f1[12]\; - addr_data_f1(11) <= \addr_data_f1[11]\; - addr_data_f1(10) <= \addr_data_f1[10]\; - addr_data_f1(9) <= \addr_data_f1[9]\; - addr_data_f1(8) <= \addr_data_f1[8]\; - addr_data_f1(7) <= \addr_data_f1[7]\; - addr_data_f1(6) <= \addr_data_f1[6]\; - addr_data_f1(5) <= \addr_data_f1[5]\; - addr_data_f1(4) <= \addr_data_f1[4]\; - addr_data_f1(3) <= \addr_data_f1[3]\; - addr_data_f1(2) <= \addr_data_f1[2]\; - addr_data_f1(1) <= \addr_data_f1[1]\; - addr_data_f1(0) <= \addr_data_f1[0]\; - delta_f2_f1(9) <= \delta_f2_f1[9]\; - delta_f2_f1(8) <= \delta_f2_f1[8]\; - delta_f2_f1(7) <= \delta_f2_f1[7]\; - delta_f2_f1(6) <= \delta_f2_f1[6]\; - delta_f2_f1(5) <= \delta_f2_f1[5]\; - delta_f2_f1(4) <= \delta_f2_f1[4]\; - delta_f2_f1(3) <= \delta_f2_f1[3]\; - delta_f2_f1(2) <= \delta_f2_f1[2]\; - delta_f2_f1(1) <= \delta_f2_f1[1]\; - delta_f2_f1(0) <= \delta_f2_f1[0]\; - addr_data_f0(31) <= \addr_data_f0[31]\; - addr_data_f0(30) <= \addr_data_f0[30]\; - addr_data_f0(29) <= \addr_data_f0[29]\; - addr_data_f0(28) <= \addr_data_f0[28]\; - addr_data_f0(27) <= \addr_data_f0[27]\; - addr_data_f0(26) <= \addr_data_f0[26]\; - addr_data_f0(25) <= \addr_data_f0[25]\; - addr_data_f0(24) <= \addr_data_f0[24]\; - addr_data_f0(23) <= \addr_data_f0[23]\; - addr_data_f0(22) <= \addr_data_f0[22]\; - addr_data_f0(21) <= \addr_data_f0[21]\; - addr_data_f0(20) <= \addr_data_f0[20]\; - addr_data_f0(19) <= \addr_data_f0[19]\; - addr_data_f0(18) <= \addr_data_f0[18]\; - addr_data_f0(17) <= \addr_data_f0[17]\; - addr_data_f0(16) <= \addr_data_f0[16]\; - addr_data_f0(15) <= \addr_data_f0[15]\; - addr_data_f0(14) <= \addr_data_f0[14]\; - addr_data_f0(13) <= \addr_data_f0[13]\; - addr_data_f0(12) <= \addr_data_f0[12]\; - addr_data_f0(11) <= \addr_data_f0[11]\; - addr_data_f0(10) <= \addr_data_f0[10]\; - addr_data_f0(9) <= \addr_data_f0[9]\; - addr_data_f0(8) <= \addr_data_f0[8]\; - addr_data_f0(7) <= \addr_data_f0[7]\; - addr_data_f0(6) <= \addr_data_f0[6]\; - addr_data_f0(5) <= \addr_data_f0[5]\; - addr_data_f0(4) <= \addr_data_f0[4]\; - addr_data_f0(3) <= \addr_data_f0[3]\; - addr_data_f0(2) <= \addr_data_f0[2]\; - addr_data_f0(1) <= \addr_data_f0[1]\; - addr_data_f0(0) <= \addr_data_f0[0]\; - delta_f2_f0(9) <= \delta_f2_f0[9]\; - delta_f2_f0(8) <= \delta_f2_f0[8]\; - delta_f2_f0(7) <= \delta_f2_f0[7]\; - delta_f2_f0(6) <= \delta_f2_f0[6]\; - delta_f2_f0(5) <= \delta_f2_f0[5]\; - delta_f2_f0(4) <= \delta_f2_f0[4]\; - delta_f2_f0(3) <= \delta_f2_f0[3]\; - delta_f2_f0(2) <= \delta_f2_f0[2]\; - delta_f2_f0(1) <= \delta_f2_f0[1]\; - delta_f2_f0(0) <= \delta_f2_f0[0]\; - delta_snapshot(15) <= \delta_snapshot[15]\; - delta_snapshot(14) <= \delta_snapshot[14]\; - delta_snapshot(13) <= \delta_snapshot[13]\; - delta_snapshot(12) <= \delta_snapshot[12]\; - delta_snapshot(11) <= \delta_snapshot[11]\; - delta_snapshot(10) <= \delta_snapshot[10]\; - delta_snapshot(9) <= \delta_snapshot[9]\; - delta_snapshot(8) <= \delta_snapshot[8]\; - delta_snapshot(7) <= \delta_snapshot[7]\; - delta_snapshot(6) <= \delta_snapshot[6]\; - delta_snapshot(5) <= \delta_snapshot[5]\; - delta_snapshot(4) <= \delta_snapshot[4]\; - delta_snapshot(3) <= \delta_snapshot[3]\; - delta_snapshot(2) <= \delta_snapshot[2]\; - delta_snapshot(1) <= \delta_snapshot[1]\; - delta_snapshot(0) <= \delta_snapshot[0]\; - nb_snapshot_param(10) <= \nb_snapshot_param[10]\; - nb_snapshot_param(9) <= \nb_snapshot_param[9]\; - nb_snapshot_param(8) <= \nb_snapshot_param[8]\; - nb_snapshot_param(7) <= \nb_snapshot_param[7]\; - nb_snapshot_param(6) <= \nb_snapshot_param[6]\; - nb_snapshot_param(5) <= \nb_snapshot_param[5]\; - nb_snapshot_param(4) <= \nb_snapshot_param[4]\; - nb_snapshot_param(3) <= \nb_snapshot_param[3]\; - nb_snapshot_param(2) <= \nb_snapshot_param[2]\; - nb_snapshot_param(1) <= \nb_snapshot_param[1]\; - nb_snapshot_param(0) <= \nb_snapshot_param[0]\; - enable_f0 <= \enable_f0\; - data_shaping_BW_c <= \data_shaping_BW_c\; - burst_f2 <= \burst_f2\; - burst_f1 <= \burst_f1\; - burst_f0 <= \burst_f0\; - enable_f3 <= \enable_f3\; - enable_f2 <= \enable_f2\; - data_shaping_SP1 <= \data_shaping_SP1\; - enable_f1 <= \enable_f1\; - data_shaping_SP0 <= \data_shaping_SP0\; - data_shaping_R1_0 <= \data_shaping_R1_0\; - data_shaping_R0_0 <= \data_shaping_R0_0\; - - \prdata_RNO_7[29]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[29]\, C - => \addr_matrix_f2_m_i[29]\, Y => \prdata_39_0_iv_1[29]\); - - \reg_wp.addr_data_f3[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[17]\); - - \reg_wp.delta_f2_f1[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[1]\); - - \reg_sp.addr_matrix_f1[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[6]\); - - \prdata_RNO_5[14]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[14]\, C => \addr_matrix_f0_1_m_i[14]\, - Y => \prdata_39_0_iv_0[14]\); - - \prdata_RNO_2[14]\ : NOR3C - port map(A => \prdata_39_0_iv_1[14]\, B => - \prdata_39_0_iv_0[14]\, C => \prdata_39_0_iv_3[14]\, Y - => \prdata_39_0_iv_6[14]\); - - \reg_sp.addr_matrix_f0_0[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[2]\); - - \reg_wp.addr_data_f3[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[25]\); - - \prdata_RNO_0[8]\ : NOR3C - port map(A => \prdata_39_0_iv_0[8]\, B => - \delta_f2_f1_m_i[8]\, C => \prdata_39_0_iv_6[8]\, Y => - \prdata_39_0_iv_9[8]\); - - \reg_wp.addr_data_f3[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[26]\); - - \reg_wp.nb_snapshot_param[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[2]\); - - \reg_wp.delta_f2_f0[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[2]\); - - \reg_wp.addr_data_f3_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_168, B => N_157, C => un1_apbi_2, Y => - addr_data_f3_1_sqmuxa); - - \prdata_RNO_5[7]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[7]\, B => - \addr_matrix_f0_0_m_i[7]\, C => \delta_f2_f1_m_i[7]\, Y - => \prdata_39_0_iv_5[7]\); - - \reg_wp.addr_data_f2[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[29]\); - - prdata_18_sqmuxa_0_a2 : NOR3C - port map(A => N_158, B => N_159, C => apbi_c_19, Y => - prdata_18_sqmuxa); - - \reg_sp.addr_matrix_f0_1[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[22]\); - - \prdata_RNO_7[3]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[3]\, B => - \addr_matrix_f0_0_m_i[3]\, C => \status_full_m_i[3]\, Y - => \prdata_39_0_iv_6[3]\); - - \prdata_RNO_8[28]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[28]\, Y - => \addr_matrix_f2_m_i[28]\); - - \prdata_RNO_6[1]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[1]\, C - => enable_f1_m_i, Y => \prdata_39_0_iv_8[1]\); - - \prdata_RNO_4[29]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[29]\, Y - => \addr_data_f1_m_i[29]\); - - \reg_wp.nb_snapshot_param[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[9]\); - - \reg_wp.nb_burst_available[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[7]\); - - \prdata_RNO[8]\ : OR3C - port map(A => \prdata_39_0_iv_9[8]\, B => - \prdata_39_0_iv_8[8]\, C => \prdata_39_0_iv_10[8]\, Y => - \prdata_39[8]\); - - \prdata_RNO_1[13]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[13]\, - Y => \delta_snapshot_m_i[13]\); - - \prdata_RNO_6[18]\ : OR3C - port map(A => N_161, B => N_168_0, C => \addr_data_f2[18]\, - Y => \addr_data_f2_m_i[18]\); - - \prdata[26]\ : DFN1C0 - port map(D => \prdata_39[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(26)); - - \prdata_RNO_19[0]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[0]\, C - => data_shaping_BW_m_i, Y => \prdata_39_0_iv_5[0]\); - - \reg_sp.addr_matrix_f0_0[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[4]\); - - \prdata_RNO_0[29]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[29]\, C - => \addr_data_f2_m_i[29]\, Y => \prdata_39_0_iv_3[29]\); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2_2\ : NOR3B - port map(A => apbi_c_0, B => apbi_c_23, C => apbi_c_24, Y - => N_158); - - \reg_wp.addr_data_f0_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_930, B => apbi_c_21, C => N_931, Y => - addr_data_f0_1_sqmuxa); - - \prdata_RNO_7[10]\ : OR2B - port map(A => \nb_snapshot_param[10]\, B => - prdata_18_sqmuxa, Y => \nb_snapshot_param_m_i[10]\); - - \reg_wp.addr_data_f2[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[13]\); - - \reg_wp.addr_data_f2[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[10]\); - - \reg_sp.addr_matrix_f0_1[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[2]\); - - \reg_wp.addr_data_f3[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[2]\); - - \reg_wp.addr_data_f3_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_168, B => N_157, C => un1_apbi_2, Y => - addr_data_f3_1_sqmuxa_0); - - \reg_sp.addr_matrix_f0_1[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[1]\); - - \prdata_RNO_11[1]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[1]\, Y - => \addr_data_f1_m_i[1]\); - - \apbo.pirq_RNO_4[15]\ : NOR2 - port map(A => status_new_err_0_2, B => status_new_err_3, Y - => \pirq_2_i_a2_1[15]\); - - \prdata_RNO_4[14]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[14]\, - C => \addr_matrix_f2_m_i[14]\, Y => - \prdata_39_0_iv_1[14]\); - - \reg_sp.addr_matrix_f0_0[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[31]\); - - \prdata_RNO_13[6]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[6]\, Y - => \delta_f2_f1_m_i[6]\); - - \prdata_RNO_16[6]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[6]\, Y - => \delta_f2_f0_m_i[6]\); - - \reg_sp.addr_matrix_f0_1[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[19]\); - - \reg_sp.status_ready_matrix_f2\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f2); - - \prdata_RNO_6[20]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[20]\, - Y => \addr_matrix_f0_0_m_i[20]\); - - \reg_wp.addr_data_f0[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[8]\); - - \prdata_RNO_6[4]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[4]\, B => - \addr_matrix_f0_0_m_i[4]\, C => \prdata_39_0_iv_1[4]\, Y - => \prdata_39_0_iv_6[4]\); - - \prdata_RNO_6[31]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[31]\, - Y => \addr_matrix_f0_0_m_i[31]\); - - \apbo.pirq_RNO_0[15]\ : NOR3A - port map(A => \pirq_2_i_a2_3[15]\, B => - status_full_err_0(1), C => status_full_err_0(0), Y => - \pirq_2_i_a2_7[15]\); - - \reg_sp.addr_matrix_f0_1[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[9]\); - - \prdata_RNO_3[6]\ : NOR3C - port map(A => \addr_matrix_f2_m_i[6]\, B => - \addr_matrix_f1_m_i[6]\, C => \delta_snapshot_m_i[6]\, Y - => \prdata_39_0_iv_6[6]\); - - \prdata_RNO_18[1]\ : OR2B - port map(A => \status_full_0[1]\, B => prdata_13_sqmuxa, Y - => \status_full_m_i[1]\); - - \reg_wp.delta_snapshot_1_sqmuxa_0_o2_0\ : OR3C - port map(A => apbi_c_22, B => N_928, C => apbi_c_20, Y => - N_931); - - \reg_sp.addr_matrix_f0_0[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[24]\); - - \prdata_RNO_11[10]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[10]\, Y - => \addr_data_f0_m_i[10]\); - - \reg_wp.addr_data_f2[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[11]\); - - \reg_sp.addr_matrix_f0_0[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[25]\); - - \reg_sp.addr_matrix_f0_0[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[16]\); - - \prdata_RNO_9[6]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[6]\, Y - => \addr_matrix_f1_m_i[6]\); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2_0\ : NOR2A - port map(A => apbi_c_19, B => un1_apbi_2, Y => N_166); - - \prdata_RNO_9[7]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[7]\, C - => \addr_data_f2_m_i[7]\, Y => \prdata_39_0_iv_3[7]\); - - \prdata_RNO_8[0]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[0]\, C - => \addr_data_f1_m_i[0]\, Y => \prdata_39_0_iv_3[0]\); - - \prdata_RNO_16[9]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[9]\, - Y => \addr_data_f2_m_i[9]\); - - \prdata_RNO[7]\ : OR3C - port map(A => \prdata_39_0_iv_9[7]\, B => - \prdata_39_0_iv_8[7]\, C => \prdata_39_0_iv_10[7]\, Y => - \prdata_39[7]\); - - \prdata_RNO_5[13]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[13]\, C => \addr_matrix_f0_1_m_i[13]\, - Y => \prdata_39_0_iv_0[13]\); - - \prdata_RNO_2[13]\ : NOR3C - port map(A => \prdata_39_0_iv_1[13]\, B => - \prdata_39_0_iv_0[13]\, C => \prdata_39_0_iv_3[13]\, Y - => \prdata_39_0_iv_6[13]\); - - prdata_16_sqmuxa_0_a2 : NOR2A - port map(A => N_164, B => N_157, Y => prdata_16_sqmuxa); - - \prdata_RNO_7[1]\ : NOR3C - port map(A => \addr_matrix_f2_m_i[1]\, B => - \addr_matrix_f1_m_i[1]\, C => \prdata_39_0_iv_2[1]\, Y - => \prdata_39_0_iv_7[1]\); - - \reg_wp.addr_data_f3[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[5]\); - - \prdata_RNO_9[15]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[15]\, - Y => \delta_snapshot_m_i[15]\); - - \prdata_RNO_7[25]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[25]\, C - => \addr_matrix_f2_m_i[25]\, Y => \prdata_39_0_iv_1[25]\); - - \prdata_RNO_10[2]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[2]\, - Y => \addr_data_f2_m_i[2]\); - - \reg_wp.addr_data_f3[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[22]\); - - \reg_wp.status_new_err_RNO_0[3]\ : NOR3A - port map(A => N_933_0, B => \status_new_err_0[3]\, C => - status_new_err_3, Y => N_153); - - \prdata_RNO_8[27]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[27]\, Y - => \addr_matrix_f2_m_i[27]\); - - \reg_sp.addr_matrix_f0_1[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[4]\); - - \reg_wp.burst_f2\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \burst_f2\); - - \reg_sp.addr_matrix_f1[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[0]\); - - \prdata_RNO_11[7]\ : OR2B - port map(A => \nb_burst_available[7]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[7]\); - - \reg_wp.status_full_err[3]\ : DFN1C0 - port map(D => \status_full_err_RNO[3]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_full_err[3]\); - - \prdata_RNO_20[1]\ : OR3A - port map(A => status_ready_matrix_f0_1, B => N_157, C => - N_169, Y => status_ready_matrix_f0_1_m_i); - - \prdata_RNO_19[4]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[4]\, - Y => \addr_matrix_f2_m_i[4]\); - - \prdata_RNO_2[24]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[24]\, B => - \addr_matrix_f0_0_m_i[24]\, C => \prdata_39_0_iv_1[24]\, - Y => \prdata_39_0_iv_4[24]\); - - \prdata_RNO_8[4]\ : NOR3C - port map(A => \addr_data_f3_m_i[4]\, B => - \addr_data_f2_m_i[4]\, C => \prdata_39_0_iv_5[4]\, Y => - \prdata_39_0_iv_9[4]\); - - \prdata_RNO[18]\ : OR3C - port map(A => \prdata_39_0_iv_1[18]\, B => - \prdata_39_0_iv_0[18]\, C => \prdata_39_0_iv_5[18]\, Y - => \prdata_39[18]\); - - \status_full_ack[1]\ : DFN1C0 - port map(D => \status_full_ack_8[1]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => status_full_ack(1)); - - \prdata_RNO_1[30]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[30]\, C - => \addr_data_f1_m_i[30]\, Y => \prdata_39_0_iv_2[30]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_o2\ : NOR2 - port map(A => un1_apbi_2, B => apbi_c_19, Y => N_930); - - \prdata_RNO_6[17]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[17]\, - Y => \addr_matrix_f0_0_m_i[17]\); - - \reg_sp.addr_matrix_f1[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[8]\); - - \prdata_RNO_4[25]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[25]\, Y - => \addr_data_f1_m_i[25]\); - - \prdata_RNO_1[3]\ : NOR3C - port map(A => \prdata_39_0_iv_3[3]\, B => - \prdata_39_0_iv_2[3]\, C => \prdata_39_0_iv_9[3]\, Y => - \prdata_39_0_iv_12[3]\); - - \prdata_RNO_16[8]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[8]\, - Y => \addr_data_f2_m_i[8]\); - - \prdata_RNO_5[21]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[21]\, Y - => \addr_data_f3_m_i[21]\); - - \prdata_RNO_5[26]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[26]\, - Y => \addr_matrix_f0_1_m_i[26]\); - - prdata_0_sqmuxa_0_a2_0 : NOR2 - port map(A => apbi_c_20, B => apbi_c_19, Y => N_161); - - \prdata[7]\ : DFN1C0 - port map(D => \prdata_39[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(7)); - - \reg_sp.config_active_interruption_onError\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => config_active_interruption_onError_0_sqmuxa, Q => - config_active_interruption_onError); - - \prdata_RNO_3[19]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[19]\, Y - => \addr_data_f2_m_i[19]\); - - \prdata_RNO_4[5]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f1\, Y => - burst_f1_m_i); - - \prdata_RNO_7[28]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[28]\, C - => \addr_matrix_f2_m_i[28]\, Y => \prdata_39_0_iv_1[28]\); - - \reg_wp.delta_f2_f1[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[7]\); - - \prdata_RNO_12[0]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[0]\, - Y => \addr_matrix_f0_1_m_i[0]\); - - \prdata_RNO_0[25]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[25]\, - C => \addr_data_f2_m_i[25]\, Y => \prdata_39_0_iv_3[25]\); - - \prdata[14]\ : DFN1C0 - port map(D => \prdata_39[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(14)); - - \prdata_RNO_11[3]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[3]\, Y - => \delta_f2_f0_m_i[3]\); - - \prdata_RNO_4[13]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[13]\, - C => \addr_matrix_f2_m_i[13]\, Y => - \prdata_39_0_iv_1[13]\); - - \prdata_RNO_2[9]\ : NOR3C - port map(A => \prdata_39_0_iv_3[9]\, B => - \prdata_39_0_iv_2[9]\, C => \nb_burst_available_m_i[9]\, - Y => \prdata_39_0_iv_10[9]\); - - prdata_12_sqmuxa_0_a2_0 : NOR2A - port map(A => N_168, B => N_157, Y => prdata_12_sqmuxa_0); - - \reg_wp.status_full_RNO_0[2]\ : NOR3A - port map(A => N_933_0, B => \status_full_0[2]\, C => - status_full(2), Y => N_137); - - \prdata_RNO_12[4]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[4]\, - Y => \addr_matrix_f0_1_m_i[4]\); - - \prdata_RNO_5[22]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[22]\, - Y => \addr_matrix_f0_1_m_i[22]\); - - \reg_wp.addr_data_f2[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[15]\); - - \reg_wp.addr_data_f2[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[16]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_a2\ : - NOR3A - port map(A => N_930, B => apbi_c_20, C => N_169, Y => - config_active_interruption_onError_0_sqmuxa); - - \reg_sp.addr_matrix_f2[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[15]\); - - \prdata_RNO[23]\ : OR3C - port map(A => \prdata_39_0_iv_1[23]\, B => - \prdata_39_0_iv_0[23]\, C => \prdata_39_0_iv_5[23]\, Y - => \prdata_39[23]\); - - \reg_wp.burst_f0_1_sqmuxa_0_a2\ : NOR3 - port map(A => N_157, B => un1_apbi_2, C => N_163, Y => - burst_f0_1_sqmuxa); - - \reg_wp.addr_data_f0[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[7]\); - - \reg_sp.addr_matrix_f0_0[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[10]\); - - \prdata_RNO_6[0]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[0]\, B => - \addr_matrix_f0_0_m_i[0]\, C => \prdata_39_0_iv_1[0]\, Y - => \prdata_39_0_iv_7[0]\); - - \reg_wp.addr_data_f1[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[27]\); - - \reg_wp.nb_burst_available[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[9]\); - - \reg_wp.addr_data_f1[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[8]\); - - \prdata_RNO_4[28]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[28]\, Y - => \addr_data_f1_m_i[28]\); - - \reg_sp.addr_matrix_f0_0[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[13]\); - - \apbo.pirq_RNO[15]\ : OR3C - port map(A => \pirq_2_i_a2_7[15]\, B => \pirq_2_i_a2_6[15]\, - C => \pirq_2_i_a2_8[15]\, Y => N_155_i_0); - - \reg_sp.addr_matrix_f2[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[12]\); - - \prdata_RNO_1[10]\ : OR2B - port map(A => \nb_burst_available[10]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[10]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_a2_0\ : - OR3A - port map(A => N_928, B => apbi_c_21, C => apbi_c_22, Y => - N_169); - - \reg_wp.addr_data_f1[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[5]\); - - \prdata_RNO_3[21]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[21]\, Y - => \addr_matrix_f2_m_i[21]\); - - \prdata_RNO_15[3]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[3]\, - Y => \addr_matrix_f0_0_m_i[3]\); - - \prdata_RNO_3[26]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[26]\, Y - => \addr_data_f2_m_i[26]\); - - \prdata_RNO_8[19]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[19]\, Y - => \addr_matrix_f2_m_i[19]\); - - \prdata_RNO_3[1]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[1]\, C - => \addr_data_f2_m_i[1]\, Y => \prdata_39_0_iv_4[1]\); - - \prdata_RNO_20[0]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[0]\, Y - => \addr_matrix_f2_m_i[0]\); - - \prdata[27]\ : DFN1C0 - port map(D => \prdata_39[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(27)); - - \prdata_RNO[12]\ : OR3C - port map(A => \prdata_39_0_iv_2[12]\, B => - \delta_snapshot_m_i[12]\, C => \prdata_39_0_iv_6[12]\, Y - => \prdata_39[12]\); - - \reg_sp.addr_matrix_f2[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[17]\); - - \reg_wp.addr_data_f2[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[4]\); - - \prdata_RNO_2[3]\ : NOR3C - port map(A => \nb_snapshot_param_m_i[3]\, B => - \prdata_39_0_iv_6[3]\, C => \prdata_39_0_iv_11[3]\, Y => - \prdata_39_0_iv_13[3]\); - - \prdata_RNO_15[4]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[4]\, Y - => \addr_data_f3_m_i[4]\); - - \prdata[28]\ : DFN1C0 - port map(D => \prdata_39[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(28)); - - \prdata_RNO_0[28]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[28]\, C - => \addr_data_f2_m_i[28]\, Y => \prdata_39_0_iv_3[28]\); - - \reg_wp.addr_data_f3[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[13]\); - - \prdata_RNO_2[23]\ : NOR3C - port map(A => \addr_data_f3_m_i[23]\, B => - \addr_data_f2_m_i[23]\, C => \prdata_39_0_iv_2[23]\, Y - => \prdata_39_0_iv_5[23]\); - - \reg_sp.addr_matrix_f2[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[25]\); - - \reg_wp.addr_data_f3[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[10]\); - - \prdata_RNO_9[8]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[8]\, C - => \addr_data_f2_m_i[8]\, Y => \prdata_39_0_iv_3[8]\); - - \prdata_RNO_13[0]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[0]\, - Y => \addr_matrix_f0_0_m_i[0]\); - - \reg_wp.data_shaping_R0\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => data_shaping_R0); - - \reg_wp.addr_data_f2[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[6]\); - - \prdata_RNO_14[7]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[7]\, - Y => \addr_matrix_f0_0_m_i[7]\); - - \prdata_RNO[24]\ : OR3C - port map(A => \prdata_39_0_iv_3[24]\, B => - \prdata_39_0_iv_2[24]\, C => \prdata_39_0_iv_4[24]\, Y - => \prdata_39[24]\); - - \prdata_RNO_7[0]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[0]\, C - => \addr_data_f2_m_i[0]\, Y => \prdata_39_0_iv_4[0]\); - - \prdata_RNO[10]\ : OR3C - port map(A => \prdata_39_0_iv_7[10]\, B => - \nb_burst_available_m_i[10]\, C => \prdata_39_0_iv_8[10]\, - Y => \prdata_39[10]\); - - \reg_sp.addr_matrix_f0_1[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[17]\); - - \reg_wp.data_shaping_SP1\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_SP1\); - - \reg_sp.addr_matrix_f2[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[22]\); - - \prdata_RNO_3[22]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[22]\, Y - => \addr_data_f2_m_i[22]\); - - \reg_wp.status_full_err_RNO[1]\ : OA1B - port map(A => apbi_c_55, B => \status_full_5_i_o2[0]\, C - => N_141, Y => \status_full_err_RNO[1]\); - - \reg_wp.delta_snapshot[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[1]\); - - \reg_sp.addr_matrix_f0_1[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[21]\); - - prdata_2_sqmuxa_0_a2_0 : NOR3B - port map(A => N_159, B => N_928, C => apbi_c_19, Y => - prdata_2_sqmuxa_0); - - \prdata_RNO_0[11]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[11]\, - C => \prdata_39_0_iv_1[11]\, Y => \prdata_39_0_iv_5[11]\); - - \prdata_RNO_7[27]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[27]\, C - => \addr_matrix_f2_m_i[27]\, Y => \prdata_39_0_iv_1[27]\); - - \prdata_RNO_0[16]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[16]\, - C => \addr_data_f2_m_i[16]\, Y => \prdata_39_0_iv_3[16]\); - - \reg_wp.addr_data_f3[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[11]\); - - \reg_sp.addr_matrix_f2[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[27]\); - - \reg_sp.addr_matrix_f1[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[29]\); - - \reg_wp.delta_f2_f0[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[1]\); - - \reg_wp.burst_f0_1_sqmuxa_0_a2_0\ : OR3B - port map(A => apbi_c_22, B => N_928, C => apbi_c_21, Y => - N_163); - - \reg_wp.addr_data_f1[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[17]\); - - \reg_wp.status_new_err_RNO[3]\ : OA1B - port map(A => apbi_c_61, B => \status_full_5_i_o2[0]\, C - => N_153, Y => \status_new_err_RNO[3]\); - - \prdata_RNO_6[6]\ : AOI1B - port map(A => \status_full_err[2]\, B => prdata_13_sqmuxa, - C => \addr_data_f0_m_i[6]\, Y => \prdata_39_0_iv_2[6]\); - - \reg_sp.addr_matrix_f2[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[4]\); - - \reg_wp.delta_f2_f1[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[2]\); - - \prdata_RNO_5[10]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[10]\, - C => \addr_data_f2_m_i[10]\, Y => \prdata_39_0_iv_3[10]\); - - \prdata_RNO_2[10]\ : NOR3C - port map(A => \prdata_39_0_iv_2[10]\, B => - \nb_snapshot_param_m_i[10]\, C => \prdata_39_0_iv_5[10]\, - Y => \prdata_39_0_iv_8[10]\); - - \prdata_RNO_16[5]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[5]\, - Y => \addr_data_f2_m_i[5]\); - - \prdata_RNO_3[15]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[15]\, Y => \addr_matrix_f0_1_m_i[15]\); - - \apbo.pirq_RNO_3[15]\ : NOR2 - port map(A => status_full_err_0(2), B => - status_full_err_0(3), Y => \pirq_2_i_a2_3[15]\); - - \prdata_RNO_2[4]\ : NOR3C - port map(A => \nb_burst_available_m_i[4]\, B => - \prdata_39_0_iv_9[4]\, C => data_shaping_R1_m_i, Y => - \prdata_39_0_iv_14[4]\); - - \prdata_RNO_16[3]\ : OR2B - port map(A => \status_full_0[3]\, B => prdata_13_sqmuxa, Y - => \status_full_m_i[3]\); - - \prdata_RNO_12[9]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[9]\, - Y => \addr_matrix_f2_m_i[9]\); - - \reg_sp.addr_matrix_f0_1[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[0]\); - - \reg_wp.addr_data_f2[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[0]\); - - \reg_wp.addr_data_f2[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[12]\); - - \reg_sp.addr_matrix_f1[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[23]\); - - \prdata_RNO_4[27]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[27]\, Y - => \addr_data_f1_m_i[27]\); - - \prdata_RNO_0[1]\ : NOR3C - port map(A => \prdata_39_0_iv_4[1]\, B => - \prdata_39_0_iv_3[1]\, C => data_shaping_SP0_m_i, Y => - \prdata_39_0_iv_13[1]\); - - \prdata[10]\ : DFN1C0 - port map(D => \prdata_39[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(10)); - - \reg_sp.status_ready_matrix_f1\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f1); - - \prdata_RNO_0[12]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[12]\, C - => \addr_data_f1_m_i[12]\, Y => \prdata_39_0_iv_2[12]\); - - \prdata_RNO_2[7]\ : NOR3C - port map(A => \prdata_39_0_iv_3[7]\, B => - \prdata_39_0_iv_2[7]\, C => \nb_burst_available_m_i[7]\, - Y => \prdata_39_0_iv_10[7]\); - - \reg_wp.addr_data_f0[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[4]\); - - prdata_2_sqmuxa_0_a2 : NOR3B - port map(A => N_159, B => N_928, C => apbi_c_19, Y => - prdata_2_sqmuxa); - - \prdata_RNO[1]\ : OR3C - port map(A => \prdata_39_0_iv_13[1]\, B => - \prdata_39_0_iv_12[1]\, C => \prdata_39_0_iv_14[1]\, Y - => \prdata_39[1]\); - - \prdata_RNO_1[5]\ : AOI1B - port map(A => \nb_snapshot_param[5]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_6[5]\, Y => \prdata_39_0_iv_10[5]\); - - \reg_sp.addr_matrix_f0_1[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[28]\); - - \reg_sp.addr_matrix_f0_0[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[14]\); - - \prdata_RNO_1[2]\ : AOI1B - port map(A => \nb_burst_available[2]\, B => - prdata_17_sqmuxa, C => \prdata_39_0_iv_7[2]\, Y => - \prdata_39_0_iv_11[2]\); - - \reg_sp.addr_matrix_f0_0[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[15]\); - - \reg_sp.addr_matrix_f0_0[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[1]\); - - \prdata_RNO_1[24]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[24]\, C - => \addr_data_f1_m_i[24]\, Y => \prdata_39_0_iv_2[24]\); - - \reg_sp.addr_matrix_f0_1[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[30]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_930, B => N_172, C => apbi_c_20, Y => - addr_matrix_f1_1_sqmuxa); - - \prdata_RNO_0[27]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[27]\, C - => \addr_data_f2_m_i[27]\, Y => \prdata_39_0_iv_3[27]\); - - \prdata[13]\ : DFN1C0 - port map(D => \prdata_39[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(13)); - - \reg_wp.delta_f2_f0[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[3]\); - - \reg_wp.enable_f0\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \enable_f0\); - - \reg_sp.addr_matrix_f1[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[15]\); - - \prdata_RNO_8[15]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[15]\, Y - => \addr_data_f0_m_i[15]\); - - \prdata_RNO_3[18]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[18]\, Y - => \addr_matrix_f2_m_i[18]\); - - \prdata_RNO[15]\ : OR3C - port map(A => \prdata_39_0_iv_4[15]\, B => - \prdata_39_0_iv_3[15]\, C => \prdata_39_0_iv_5[15]\, Y - => \prdata_39[15]\); - - \prdata_RNO_4[10]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[10]\, Y - => \addr_data_f3_m_i[10]\); - - \reg_wp.addr_data_f3[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[0]\); - - \prdata_RNO_7[11]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[11]\, Y - => \addr_data_f0_m_i[11]\); - - \reg_wp.addr_data_f0[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[5]\); - - \prdata_RNO_7[16]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[16]\, - C => \addr_matrix_f2_m_i[16]\, Y => - \prdata_39_0_iv_1[16]\); - - \reg_sp.addr_matrix_f1[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[12]\); - - \prdata[3]\ : DFN1C0 - port map(D => \prdata_39[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(3)); - - \reg_wp.addr_data_f2[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[27]\); - - \reg_wp.burst_f0\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \burst_f0\); - - \prdata_RNO_10[4]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[4]\, Y - => \addr_data_f1_m_i[4]\); - - \reg_wp.addr_data_f3[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[15]\); - - \prdata[5]\ : DFN1C0 - port map(D => \prdata_39[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(5)); - - \reg_sp.addr_matrix_f1[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[17]\); - - \reg_wp.addr_data_f3[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[16]\); - - \prdata_RNO_6[21]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[21]\, Y - => \addr_data_f2_m_i[21]\); - - \prdata_RNO_11[8]\ : OR2B - port map(A => \nb_burst_available[8]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[8]\); - - \prdata_RNO_6[26]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[26]\, - Y => \addr_matrix_f0_0_m_i[26]\); - - \reg_wp.addr_data_f0[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[24]\); - - \prdata_RNO_15[7]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[7]\, Y - => \delta_f2_f1_m_i[7]\); - - \reg_sp.addr_matrix_f2[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[9]\); - - \prdata_RNO_7[5]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[5]\, C - => \delta_f2_f1_m_i[5]\, Y => \prdata_39_0_iv_5[5]\); - - GND_i : GND - port map(Y => \GND\); - - \prdata_RNO_2[1]\ : NOR3C - port map(A => \prdata_39_0_iv_7[1]\, B => - \prdata_39_0_iv_6[1]\, C => \prdata_39_0_iv_10[1]\, Y => - \prdata_39_0_iv_14[1]\); - - \reg_wp.status_new_err[0]\ : DFN1C0 - port map(D => \status_new_err_RNO[0]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_new_err[0]\); - - \reg_wp.status_new_err_RNO[0]\ : OA1B - port map(A => apbi_c_58, B => \status_full_5_i_o2[0]\, C - => N_147, Y => \status_new_err_RNO[0]\); - - \prdata_RNO_7[12]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[12]\, - Y => \addr_matrix_f2_m_i[12]\); - - \prdata_RNO_9[2]\ : OR3B - port map(A => N_161_0, B => \data_shaping_SP1\, C => N_163, - Y => data_shaping_SP1_m_i); - - \reg_wp.status_full[1]\ : DFN1C0 - port map(D => \status_full_RNO[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \status_full_0[1]\); - - \reg_wp.addr_data_f0[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[0]\); - - \prdata_RNO_8[18]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[18]\, Y - => \addr_data_f1_m_i[18]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_o2\ : - NOR3A - port map(A => apbi_c_0, B => apbi_c_24, C => apbi_c_23, Y - => N_928); - - \reg_sp.addr_matrix_f1[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[28]\); - - \prdata_RNO_7[8]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[8]\, Y - => \addr_data_f3_m_i[8]\); - - \reg_wp.addr_data_f0[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[28]\); - - \prdata_RNO_14[1]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[1]\, Y - => \addr_matrix_f1_m_i[1]\); - - \reg_wp.delta_snapshot[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[5]\); - - \prdata_RNO_2[20]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[20]\, B => - \addr_matrix_f0_0_m_i[20]\, C => \prdata_39_0_iv_1[20]\, - Y => \prdata_39_0_iv_4[20]\); - - \prdata_RNO_6[22]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[22]\, - Y => \addr_matrix_f0_0_m_i[22]\); - - \prdata_RNO_10[11]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[11]\, - Y => \addr_matrix_f2_m_i[11]\); - - \reg_wp.nb_snapshot_param[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[0]\); - - \prdata_RNO_3[9]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[9]\, Y - => \delta_snapshot_m_i[9]\); - - \reg_wp.addr_data_f0[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[14]\); - - \prdata_RNO_1[31]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[31]\, C - => \addr_data_f1_m_i[31]\, Y => \prdata_39_0_iv_2[31]\); - - \prdata_RNO_6[8]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[8]\, Y - => \delta_f2_f0_m_i[8]\); - - \prdata_RNO_5[30]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[30]\, - Y => \addr_matrix_f0_1_m_i[30]\); - - \prdata_RNO_4[7]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[7]\, - C => \addr_matrix_f2_m_i[7]\, Y => \prdata_39_0_iv_1[7]\); - - \reg_sp.addr_matrix_f0_1[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[16]\); - - \prdata_RNO_5[29]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[29]\, - Y => \addr_matrix_f0_1_m_i[29]\); - - \prdata_RNO_5[4]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[4]\, C - => \prdata_39_0_iv_2[4]\, Y => \prdata_39_0_iv_7[4]\); - - \prdata_RNO_1[9]\ : NOR3C - port map(A => \delta_f2_f0_m_i[9]\, B => - \addr_data_f3_m_i[9]\, C => \nb_snapshot_param_m_i[9]\, Y - => \prdata_39_0_iv_8[9]\); - - \reg_wp.addr_data_f2[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[1]\); - - \reg_wp.delta_f2_f0[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[5]\); - - \prdata_RNO_3[17]\ : OR3C - port map(A => N_161, B => N_168_0, C => \addr_data_f2[17]\, - Y => \addr_data_f2_m_i[17]\); - - \prdata_RNO_1[23]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[23]\, C => \addr_matrix_f0_1_m_i[23]\, - Y => \prdata_39_0_iv_0[23]\); - - \prdata_RNO[2]\ : OR3C - port map(A => \prdata_39_0_iv_12[2]\, B => - \prdata_39_0_iv_11[2]\, C => \prdata_39_0_iv_13[2]\, Y - => \prdata_39[2]\); - - \reg_wp.delta_snapshot[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[6]\); - - \prdata[15]\ : DFN1C0 - port map(D => \prdata_39[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(15)); - - \reg_wp.delta_snapshot[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[8]\); - - \reg_wp.nb_burst_available[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[6]\); - - \reg_wp.status_full_err_RNO[2]\ : OA1B - port map(A => apbi_c_56, B => \status_full_5_i_o2[0]\, C - => N_143, Y => \status_full_err_RNO[2]\); - - \reg_wp.addr_data_f1[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[23]\); - - \reg_wp.addr_data_f0[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[18]\); - - \reg_wp.addr_data_f1[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[20]\); - - \prdata[6]\ : DFN1C0 - port map(D => \prdata_39[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(6)); - - \prdata_RNO_4[3]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[3]\, C - => status_ready_matrix_f2_m_i, Y => - \prdata_39_0_iv_2[3]\); - - \prdata_RNO_10[9]\ : AOI1B - port map(A => \status_new_err[1]\, B => prdata_13_sqmuxa, C - => \addr_data_f0_m_i[9]\, Y => \prdata_39_0_iv_2[9]\); - - \reg_wp.status_new_err_RNO[2]\ : OA1B - port map(A => apbi_c_60, B => \status_full_5_i_o2[0]\, C - => N_151, Y => \status_new_err_RNO[2]\); - - \prdata_RNO_11[6]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[6]\, - Y => \addr_matrix_f0_1_m_i[6]\); - - \reg_sp.addr_matrix_f0_0[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[22]\); - - \reg_wp.status_new_err[2]\ : DFN1C0 - port map(D => \status_new_err_RNO[2]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_new_err[2]\); - - \prdata_RNO_17[4]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[4]\, C - => \delta_f2_f1_m_i[4]\, Y => \prdata_39_0_iv_5[4]\); - - \reg_wp.addr_data_f0[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[3]\); - - \reg_wp.addr_data_f3[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[12]\); - - \prdata_RNO_0[6]\ : AOI1B - port map(A => \nb_burst_available[6]\, B => - prdata_17_sqmuxa, C => \prdata_39_0_iv_6[6]\, Y => - \prdata_39_0_iv_10[6]\); - - prdata_4_sqmuxa_0_a2_0 : NOR2B - port map(A => N_172, B => N_161_0, Y => prdata_4_sqmuxa_0); - - \reg_wp.delta_f2_f1[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[3]\); - - \prdata_RNO_8[24]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[24]\, Y - => \addr_matrix_f2_m_i[24]\); - - \reg_wp.addr_data_f1[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[21]\); - - \prdata_RNO_2[0]\ : NOR3C - port map(A => \prdata_39_0_iv_4[0]\, B => - \prdata_39_0_iv_3[0]\, C => \prdata_39_0_iv_11[0]\, Y => - \prdata_39_0_iv_14[0]\); - - \reg_wp.delta_f2_f0[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[8]\); - - \reg_wp.addr_data_f2[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[9]\); - - \prdata_RNO[27]\ : OR3C - port map(A => \prdata_39_0_iv_3[27]\, B => - \prdata_39_0_iv_2[27]\, C => \prdata_39_0_iv_4[27]\, Y - => \prdata_39[27]\); - - \prdata_RNO_8[30]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[30]\, Y - => \addr_matrix_f2_m_i[30]\); - - \prdata_RNO_3[29]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[29]\, Y - => \addr_data_f2_m_i[29]\); - - prdata_4_sqmuxa_0_a2 : NOR2B - port map(A => N_172, B => N_161, Y => prdata_4_sqmuxa); - - \prdata_RNO_8[17]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[17]\, Y - => \addr_matrix_f2_m_i[17]\); - - \reg_wp.status_full_RNO_0[3]\ : NOR3A - port map(A => N_933_0, B => \status_full_0[3]\, C => - status_full(3), Y => N_138); - - \prdata_RNO_18[2]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[2]\, - C => \addr_matrix_f2_m_i[2]\, Y => \prdata_39_0_iv_1[2]\); - - \apbo.pirq_RNO_1[15]\ : NOR3A - port map(A => \pirq_2_i_a2_1[15]\, B => status_new_err_0_1, - C => status_new_err_0_0, Y => \pirq_2_i_a2_6[15]\); - - \reg_wp.status_full_err_RNO_0[0]\ : NOR3A - port map(A => N_933_0, B => \status_full_err[0]\, C => - status_full_err_0(0), Y => N_139); - - \prdata_RNO_6[14]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[14]\, - C => \addr_data_f2_m_i[14]\, Y => \prdata_39_0_iv_3[14]\); - - \prdata_RNO_1[11]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[11]\, B => - \addr_matrix_f0_0_m_i[11]\, C => \addr_data_f3_m_i[11]\, - Y => \prdata_39_0_iv_4[11]\); - - \prdata_RNO_1[16]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[16]\, C - => \addr_data_f1_m_i[16]\, Y => \prdata_39_0_iv_2[16]\); - - \apbo.pirq[15]\ : DFN1C0 - port map(D => N_155_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => pirq_c(15)); - - \reg_wp.addr_data_f1[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[4]\); - - \prdata_RNO[19]\ : OR3C - port map(A => \prdata_39_0_iv_3[19]\, B => - \prdata_39_0_iv_2[19]\, C => \prdata_39_0_iv_4[19]\, Y - => \prdata_39[19]\); - - \reg_wp.data_shaping_BW\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_BW_c\); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_158, B => apbi_c_21, C => apbi_c_22, Y => - N_164); - - \prdata_RNO_17[1]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[1]\, - Y => \addr_matrix_f0_0_m_i[1]\); - - \reg_sp.addr_matrix_f2[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[0]\); - - \prdata_RNO_9[1]\ : AOI1B - port map(A => \nb_snapshot_param[1]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_5[1]\, Y => \prdata_39_0_iv_10[1]\); - - \prdata_RNO_1[0]\ : AOI1B - port map(A => \nb_snapshot_param[0]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_7[0]\, Y => \prdata_39_0_iv_12[0]\); - - \prdata_RNO_10[1]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[1]\, - Y => \addr_data_f2_m_i[1]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_a2_0\ : NOR3C - port map(A => N_159, B => N_928, C => N_930, Y => - addr_matrix_f0_0_1_sqmuxa_0); - - \reg_wp.addr_data_f1[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[13]\); - - \reg_wp.delta_snapshot[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[4]\); - - \reg_wp.addr_data_f1[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[10]\); - - \reg_wp.status_full_RNO_0[0]\ : NOR3A - port map(A => N_933_0, B => \status_full_0[0]\, C => - status_full(0), Y => N_135); - - \reg_sp.addr_matrix_f1[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[9]\); - - \reg_wp.delta_f2_f1[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[8]\); - - \reg_sp.addr_matrix_f0_1[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[10]\); - - \prdata_RNO_19[3]\ : OR2B - port map(A => \nb_burst_available[3]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[3]\); - - \prdata_RNO_2[5]\ : NOR3C - port map(A => \prdata_39_0_iv_5[5]\, B => - \prdata_39_0_iv_4[5]\, C => \nb_burst_available_m_i[5]\, - Y => \prdata_39_0_iv_12[5]\); - - \prdata_RNO_2[6]\ : NOR3C - port map(A => \prdata_39_0_iv_3[6]\, B => - \prdata_39_0_iv_2[6]\, C => \prdata_39_0_iv_8[6]\, Y => - \prdata_39_0_iv_11[6]\); - - prdata_8_sqmuxa_0_a2 : NOR2 - port map(A => N_163, B => N_157, Y => prdata_8_sqmuxa); - - \prdata_RNO_0[19]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[19]\, - C => \addr_data_f2_m_i[19]\, Y => \prdata_39_0_iv_3[19]\); - - \prdata[12]\ : DFN1C0 - port map(D => \prdata_39[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(12)); - - \reg_sp.addr_matrix_f0_1[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[13]\); - - \prdata_RNO_1[12]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[12]\, - Y => \delta_snapshot_m_i[12]\); - - \reg_sp.addr_matrix_f0_0[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[9]\); - - \reg_wp.addr_data_f1[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[11]\); - - prdata_0_sqmuxa_0_a2 : NOR2A - port map(A => N_161, B => N_169, Y => prdata_0_sqmuxa); - - \prdata_RNO_5[25]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[25]\, - Y => \addr_matrix_f0_1_m_i[25]\); - - \prdata[19]\ : DFN1C0 - port map(D => \prdata_39[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(19)); - - \prdata_RNO_11[4]\ : AOI1B - port map(A => \status_full_err[0]\, B => prdata_13_sqmuxa, - C => status_error_anticipating_empty_fifo_m_i, Y => - \prdata_39_0_iv_2[4]\); - - \reg_wp.delta_f2_f0[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[7]\); - - \prdata_RNO_11[11]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[11]\, Y => \addr_data_f2_m_i[11]\); - - \reg_sp.addr_matrix_f0_1[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[29]\); - - \reg_wp.status_full_RNO[1]\ : OA1B - port map(A => apbi_c_51, B => \status_full_5_i_o2[0]\, C - => N_136, Y => \status_full_RNO[1]\); - - \reg_wp.nb_burst_available[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[5]\); - - \prdata_RNO_7[30]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[30]\, C - => \addr_matrix_f2_m_i[30]\, Y => \prdata_39_0_iv_1[30]\); - - \reg_wp.addr_data_f3[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[8]\); - - \prdata_RNO_5[11]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[11]\, - Y => \addr_matrix_f0_0_m_i[11]\); - - \reg_wp.addr_data_f0[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[29]\); - - \prdata_RNO_5[16]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[16]\, Y => \addr_matrix_f0_1_m_i[16]\); - - \prdata_RNO_2[11]\ : NOR3C - port map(A => \addr_data_f0_m_i[11]\, B => - \status_new_err_m_i[3]\, C => \prdata_39_0_iv_3[11]\, Y - => \prdata_39_0_iv_6[11]\); - - \prdata_RNO_2[16]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[16]\, B => - \addr_matrix_f0_0_m_i[16]\, C => \prdata_39_0_iv_1[16]\, - Y => \prdata_39_0_iv_4[16]\); - - \prdata_RNO_13[10]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[10]\, - Y => \addr_matrix_f2_m_i[10]\); - - \reg_wp.nb_burst_available[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[8]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_930, B => N_168, C => apbi_c_20, Y => - addr_data_f2_1_sqmuxa); - - prdata_13_sqmuxa_0_a2 : NOR3A - port map(A => apbi_c_21, B => N_931, C => apbi_c_19, Y => - prdata_13_sqmuxa); - - \reg_wp.delta_f2_f0[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[0]\); - - \reg_sp.status_error_bad_component_error\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_error_bad_component_error); - - \prdata_RNO_12[10]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[10]\, - C => \addr_matrix_f2_m_i[10]\, Y => - \prdata_39_0_iv_1[10]\); - - \reg_wp.addr_data_f3[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[24]\); - - \reg_wp.nb_burst_available[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[4]\); - - prdata_10_sqmuxa_0_a2_0 : NOR3A - port map(A => apbi_c_19, B => apbi_c_21, C => N_931, Y => - prdata_10_sqmuxa_0); - - \reg_wp.addr_data_f1[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[25]\); - - \lpp_top_apbreg.reg_wp.status_full_5_i_o2_0[0]\ : OR3B - port map(A => apbi_c_21, B => N_930, C => N_931, Y => - N_933_0); - - \reg_wp.addr_data_f1[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[26]\); - - \prdata_RNO_0[30]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[30]\, C - => \addr_data_f2_m_i[30]\, Y => \prdata_39_0_iv_3[30]\); - - \reg_wp.addr_data_f1[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[1]\); - - \prdata_RNO_8[23]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[23]\, Y - => \addr_data_f1_m_i[23]\); - - \reg_sp.addr_matrix_f2[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[3]\); - - \reg_sp.addr_matrix_f2[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[19]\); - - \status_full_ack[0]\ : DFN1C0 - port map(D => \status_full_ack_8[0]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => status_full_ack(0)); - - \prdata[21]\ : DFN1C0 - port map(D => \prdata_39[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(21)); - - \prdata_RNO_3[8]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[8]\, - C => \addr_matrix_f0_1_m_i[8]\, Y => - \prdata_39_0_iv_0[8]\); - - \prdata_RNO_5[12]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[12]\, C => \addr_matrix_f0_1_m_i[12]\, - Y => \prdata_39_0_iv_0[12]\); - - \reg_wp.addr_data_f3[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[28]\); - - \reg_wp.addr_data_f2[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[23]\); - - \prdata_RNO_5[28]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[28]\, - Y => \addr_matrix_f0_1_m_i[28]\); - - \prdata_RNO_2[12]\ : NOR3C - port map(A => \prdata_39_0_iv_1[12]\, B => - \prdata_39_0_iv_0[12]\, C => \prdata_39_0_iv_3[12]\, Y - => \prdata_39_0_iv_6[12]\); - - \reg_wp.addr_data_f2[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[20]\); - - \prdata_RNO_1[20]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[20]\, C - => \addr_data_f1_m_i[20]\, Y => \prdata_39_0_iv_2[20]\); - - \prdata_RNO_10[0]\ : OR3A - port map(A => status_ready_matrix_f0_0, B => N_157, C => - N_169, Y => status_ready_matrix_f0_0_m_i); - - \reg_wp.data_shaping_SP0\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_SP0\); - - \prdata_RNO_6[13]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[13]\, - C => \addr_data_f2_m_i[13]\, Y => \prdata_39_0_iv_3[13]\); - - \prdata_RNO_3[25]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[25]\, Y - => \addr_data_f2_m_i[25]\); - - \reg_wp.addr_data_f0[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[19]\); - - \prdata_RNO_11[9]\ : OR2B - port map(A => \nb_burst_available[9]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[9]\); - - \prdata_RNO_17[9]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[9]\, Y - => \addr_data_f0_m_i[9]\); - - \reg_wp.data_shaping_R1_0\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_R1_0\); - - \prdata_RNO_8[5]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[5]\, C - => \addr_data_f2_m_i[5]\, Y => \prdata_39_0_iv_4[5]\); - - \prdata_RNO_6[3]\ : OR2B - port map(A => \nb_snapshot_param[3]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[3]\); - - \reg_sp.addr_matrix_f2[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[13]\); - - \prdata_RNO_17[6]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[6]\, Y - => \addr_data_f3_m_i[6]\); - - \prdata_RNO_7[19]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[19]\, C - => \addr_matrix_f2_m_i[19]\, Y => \prdata_39_0_iv_1[19]\); - - \prdata_RNO_9[14]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[14]\, Y - => \addr_data_f2_m_i[14]\); - - \prdata_RNO_7[24]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[24]\, C - => \addr_matrix_f2_m_i[24]\, Y => \prdata_39_0_iv_1[24]\); - - \prdata_RNO[21]\ : OR3C - port map(A => \prdata_39_0_iv_1[21]\, B => - \prdata_39_0_iv_0[21]\, C => \prdata_39_0_iv_5[21]\, Y - => \prdata_39[21]\); - - \prdata[1]\ : DFN1C0 - port map(D => \prdata_39[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(1)); - - \reg_wp.delta_snapshot[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[10]\); - - \reg_sp.addr_matrix_f2[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[29]\); - - \reg_wp.addr_data_f2[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[21]\); - - \reg_wp.addr_data_f3[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[7]\); - - \prdata_RNO_4[11]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[11]\, Y => \addr_matrix_f0_1_m_i[11]\); - - \prdata_RNO_4[16]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[16]\, - Y => \addr_data_f1_m_i[16]\); - - \prdata_RNO_1[7]\ : NOR3C - port map(A => \delta_f2_f0_m_i[7]\, B => - \addr_data_f3_m_i[7]\, C => \nb_snapshot_param_m_i[7]\, Y - => \prdata_39_0_iv_8[7]\); - - \prdata_RNO_7[9]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[9]\, Y - => \addr_data_f3_m_i[9]\); - - \prdata_RNO_6[29]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[29]\, - Y => \addr_matrix_f0_0_m_i[29]\); - - \prdata_RNO_19[2]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[2]\, Y - => \delta_f2_f0_m_i[2]\); - - \reg_wp.addr_data_f1[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[15]\); - - \prdata_RNO_16[2]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[2]\, - Y => \addr_matrix_f0_1_m_i[2]\); - - \reg_wp.status_full_err_RNO[0]\ : OA1B - port map(A => apbi_c_54, B => \status_full_5_i_o2[0]\, C - => N_139, Y => \status_full_err_RNO[0]\); - - \reg_wp.addr_data_f1[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[16]\); - - \prdata_RNO_5[9]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[9]\, B => - \addr_matrix_f0_0_m_i[9]\, C => \delta_f2_f1_m_i[9]\, Y - => \prdata_39_0_iv_5[9]\); - - \reg_sp.addr_matrix_f1[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[26]\); - - \reg_sp.addr_matrix_f2[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[2]\); - - \reg_sp.addr_matrix_f0_1[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[14]\); - - \reg_sp.addr_matrix_f0_1[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[15]\); - - \prdata_RNO[26]\ : OR3C - port map(A => \prdata_39_0_iv_3[26]\, B => - \prdata_39_0_iv_2[26]\, C => \prdata_39_0_iv_4[26]\, Y - => \prdata_39[26]\); - - \prdata_RNO_0[15]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[15]\, B => - \addr_matrix_f0_0_m_i[15]\, C => \prdata_39_0_iv_1[15]\, - Y => \prdata_39_0_iv_4[15]\); - - \prdata[31]\ : DFN1C0 - port map(D => \prdata_39[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(31)); - - \reg_wp.addr_data_f1_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_166, B => apbi_c_21, C => N_931, Y => - addr_data_f1_1_sqmuxa); - - \reg_wp.addr_data_f2[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[30]\); - - \reg_sp.addr_matrix_f0_1[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[7]\); - - \prdata_RNO_4[24]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[24]\, Y - => \addr_data_f1_m_i[24]\); - - \reg_sp.addr_matrix_f1[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[21]\); - - \reg_sp.addr_matrix_f2[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[23]\); - - \reg_wp.addr_data_f3[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[3]\); - - \prdata_RNO_3[28]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[28]\, Y - => \addr_data_f2_m_i[28]\); - - \reg_sp.addr_matrix_f1[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[20]\); - - \prdata[16]\ : DFN1C0 - port map(D => \prdata_39[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(16)); - - \prdata_RNO_4[0]\ : AOI1B - port map(A => prdata_0_sqmuxa, B => - config_active_interruption_onNewMatrix, C => - status_ready_matrix_f0_0_m_i, Y => \prdata_39_0_iv_2[0]\); - - \status_full_ack[2]\ : DFN1C0 - port map(D => \status_full_ack_8[2]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => status_full_ack(2)); - - \prdata_RNO_4[12]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[12]\, - C => \addr_matrix_f2_m_i[12]\, Y => - \prdata_39_0_iv_1[12]\); - - \prdata_RNO[0]\ : OR3C - port map(A => \prdata_39_0_iv_13[0]\, B => - \prdata_39_0_iv_12[0]\, C => \prdata_39_0_iv_14[0]\, Y - => \prdata_39[0]\); - - \reg_wp.addr_data_f1[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[22]\); - - \prdata_RNO_12[5]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[5]\, - Y => \addr_matrix_f0_1_m_i[5]\); - - \reg_wp.addr_data_f2[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[31]\); - - \reg_wp.nb_snapshot_param[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[3]\); - - \reg_sp.addr_matrix_f0_0[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[12]\); - - \prdata_RNO_0[24]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[24]\, - C => \addr_data_f2_m_i[24]\, Y => \prdata_39_0_iv_3[24]\); - - \reg_sp.status_error_anticipating_empty_fifo\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_error_anticipating_empty_fifo); - - \reg_sp.addr_matrix_f0_0[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[8]\); - - \status_full_ack_RNO[0]\ : NOR3A - port map(A => \status_full_0[0]\, B => apbi_c_50, C => - \status_full_5_i_o2[0]\, Y => \status_full_ack_8[0]\); - - \prdata_RNO_2[21]\ : NOR3C - port map(A => \addr_data_f3_m_i[21]\, B => - \addr_data_f2_m_i[21]\, C => \prdata_39_0_iv_2[21]\, Y - => \prdata_39_0_iv_5[21]\); - - \reg_sp.addr_matrix_f0_0[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[21]\); - - \prdata_RNO_2[26]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[26]\, B => - \addr_matrix_f0_0_m_i[26]\, C => \prdata_39_0_iv_1[26]\, - Y => \prdata_39_0_iv_4[26]\); - - \prdata_RNO_5[27]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[27]\, - Y => \addr_matrix_f0_1_m_i[27]\); - - \reg_wp.addr_data_f0[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[2]\); - - \reg_sp.addr_matrix_f0_0[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[0]\); - - \prdata_RNO_5[1]\ : OR3B - port map(A => N_161_0, B => \data_shaping_SP0\, C => N_163, - Y => data_shaping_SP0_m_i); - - \prdata_RNO_15[8]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[8]\, Y - => \delta_snapshot_m_i[8]\); - - \prdata_RNO_15[6]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[6]\, Y - => \addr_data_f0_m_i[6]\); - - \reg_wp.status_full[3]\ : DFN1C0 - port map(D => \status_full_RNO[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \status_full_0[3]\); - - \prdata_RNO_16[1]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[1]\, - Y => \addr_matrix_f0_1_m_i[1]\); - - \prdata[2]\ : DFN1C0 - port map(D => \prdata_39[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(2)); - - \reg_wp.delta_snapshot[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[2]\); - - \prdata_RNO_5[31]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[31]\, - Y => \addr_matrix_f0_1_m_i[31]\); - - prdata_9_sqmuxa_0_a2 : NOR3 - port map(A => apbi_c_21, B => N_931, C => apbi_c_19, Y => - prdata_9_sqmuxa); - - \prdata_RNO_5[2]\ : NOR3C - port map(A => \status_full_m_i[2]\, B => - \delta_f2_f1_m_i[2]\, C => \prdata_39_0_iv_4[2]\, Y => - \prdata_39_0_iv_9[2]\); - - \prdata_RNO_0[18]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[18]\, - C => \addr_matrix_f2_m_i[18]\, Y => - \prdata_39_0_iv_1[18]\); - - \reg_wp.nb_snapshot_param[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[6]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0_1\ : NOR3B - port map(A => N_930, B => N_168, C => apbi_c_20, Y => - addr_data_f2_1_sqmuxa_0); - - \reg_sp.addr_matrix_f2[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[18]\); - - \lpp_top_apbreg.reg_wp.status_full_5_i_o2[0]\ : OR3B - port map(A => apbi_c_21, B => N_930, C => N_931, Y => - \status_full_5_i_o2[0]\); - - \reg_wp.status_new_err_RNO_0[0]\ : NOR3A - port map(A => N_933_0, B => \status_new_err[0]\, C => - status_new_err_0_0, Y => N_147); - - \reg_wp.delta_f2_f1[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[6]\); - - \reg_sp.addr_matrix_f0_1[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[27]\); - - \reg_wp.status_full_err[0]\ : DFN1C0 - port map(D => \status_full_err_RNO[0]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_full_err[0]\); - - \prdata_RNO_18[3]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[3]\, - C => \addr_matrix_f2_m_i[3]\, Y => \prdata_39_0_iv_1[3]\); - - \reg_sp.addr_matrix_f1[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[4]\); - - \reg_sp.addr_matrix_f1[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[19]\); - - \reg_wp.addr_data_f2[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[25]\); - - \prdata_RNO_9[9]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[9]\, C - => \addr_data_f2_m_i[9]\, Y => \prdata_39_0_iv_3[9]\); - - \prdata_RNO_9[13]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[13]\, Y => \addr_data_f2_m_i[13]\); - - \prdata_RNO_3[5]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[5]\, C - => \addr_data_f1_m_i[5]\, Y => \prdata_39_0_iv_3[5]\); - - \prdata_RNO_0[4]\ : NOR3C - port map(A => \prdata_39_0_iv_3[4]\, B => burst_f0_m_i, C - => \prdata_39_0_iv_7[4]\, Y => \prdata_39_0_iv_11[4]\); - - \prdata_RNO_7[23]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[23]\, C - => \addr_data_f1_m_i[23]\, Y => \prdata_39_0_iv_2[23]\); - - \reg_wp.addr_data_f2[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[26]\); - - \prdata_RNO_2[22]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[22]\, B => - \addr_matrix_f0_0_m_i[22]\, C => \prdata_39_0_iv_1[22]\, - Y => \prdata_39_0_iv_4[22]\); - - \reg_sp.addr_matrix_f0_1[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[8]\); - - \reg_wp.delta_snapshot[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[7]\); - - \reg_sp.addr_matrix_f0_0[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[3]\); - - \prdata_RNO_18[6]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f2\, Y => - burst_f2_m_i); - - \reg_wp.burst_f1\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \burst_f1\); - - \prdata_RNO_7[15]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[15]\, - Y => \addr_data_f1_m_i[15]\); - - \reg_wp.addr_data_f1[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[12]\); - - \reg_sp.addr_matrix_f1[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[7]\); - - \reg_wp.status_full_RNO[2]\ : OA1B - port map(A => apbi_c_52, B => \status_full_5_i_o2[0]\, C - => N_137, Y => \status_full_RNO[2]\); - - \reg_wp.nb_burst_available[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[1]\); - - \prdata_RNO_8[20]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[20]\, Y - => \addr_matrix_f2_m_i[20]\); - - \prdata_RNO_0[5]\ : NOR3C - port map(A => \prdata_39_0_iv_3[5]\, B => burst_f1_m_i, C - => \prdata_39_0_iv_7[5]\, Y => \prdata_39_0_iv_11[5]\); - - \reg_wp.addr_data_f2[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[14]\); - - \reg_sp.addr_matrix_f0_0[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[28]\); - - \reg_wp.addr_data_f3[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[30]\); - - \prdata_RNO_3[27]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[27]\, Y - => \addr_data_f2_m_i[27]\); - - \reg_wp.addr_data_f0[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[1]\); - - \reg_sp.addr_matrix_f1[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[13]\); - - \prdata_RNO_6[25]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[25]\, - Y => \addr_matrix_f0_0_m_i[25]\); - - \reg_wp.addr_data_f3[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[29]\); - - \reg_sp.addr_matrix_f2[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[28]\); - - \prdata_RNO_12[8]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[8]\, - Y => \addr_matrix_f0_1_m_i[8]\); - - \prdata_RNO_4[23]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[23]\, - Y => \addr_matrix_f0_1_m_i[23]\); - - \prdata_RNO_1[19]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[19]\, C - => \addr_data_f1_m_i[19]\, Y => \prdata_39_0_iv_2[19]\); - - \prdata_RNO_8[31]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[31]\, Y - => \addr_matrix_f2_m_i[31]\); - - \prdata_RNO_7[2]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[2]\, B => - \addr_matrix_f0_0_m_i[2]\, C => \prdata_39_0_iv_1[2]\, Y - => \prdata_39_0_iv_6[2]\); - - \prdata_RNO_6[10]\ : AOI1B - port map(A => \status_new_err[2]\, B => prdata_13_sqmuxa, C - => \addr_data_f0_m_i[10]\, Y => \prdata_39_0_iv_2[10]\); - - \reg_sp.addr_matrix_f1[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[24]\); - - \prdata_RNO_7[6]\ : NOR3C - port map(A => \delta_f2_f0_m_i[6]\, B => - \addr_data_f3_m_i[6]\, C => burst_f2_m_i, Y => - \prdata_39_0_iv_8[6]\); - - \reg_wp.data_shaping_BW_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_930, B => apbi_c_20, C => N_163, Y => - data_shaping_BW_1_sqmuxa); - - \reg_wp.addr_data_f3[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[31]\); - - \reg_wp.addr_data_f2[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[18]\); - - \prdata_RNO[5]\ : OR3C - port map(A => \prdata_39_0_iv_11[5]\, B => - \prdata_39_0_iv_10[5]\, C => \prdata_39_0_iv_12[5]\, Y - => \prdata_39[5]\); - - \prdata_RNO_3[14]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[14]\, Y - => \addr_data_f1_m_i[14]\); - - \reg_wp.status_full[2]\ : DFN1C0 - port map(D => \status_full_RNO[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \status_full_0[2]\); - - \prdata_RNO_0[23]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[23]\, C - => \addr_matrix_f2_m_i[23]\, Y => \prdata_39_0_iv_1[23]\); - - \reg_wp.status_full_RNO[0]\ : OA1B - port map(A => apbi_c_50, B => \status_full_5_i_o2[0]\, C - => N_135, Y => \status_full_RNO[0]\); - - \prdata_RNO_7[18]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[18]\, C - => \addr_data_f1_m_i[18]\, Y => \prdata_39_0_iv_2[18]\); - - \prdata_RNO_13[9]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[9]\, - Y => \addr_matrix_f0_1_m_i[9]\); - - \reg_wp.addr_data_f1[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[2]\); - - \reg_sp.addr_matrix_f2[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[6]\); - - \prdata_RNO_0[17]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[17]\, - C => \addr_data_f2_m_i[17]\, Y => \prdata_39_0_iv_3[17]\); - - prdata_0_sqmuxa_0_a2_0_0 : NOR2 - port map(A => apbi_c_20, B => apbi_c_19, Y => N_161_0); - - \reg_wp.addr_data_f1[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[3]\); - - \prdata_RNO_0[9]\ : NOR3C - port map(A => \delta_snapshot_m_i[9]\, B => - \prdata_39_0_iv_1[9]\, C => \prdata_39_0_iv_5[9]\, Y => - \prdata_39_0_iv_9[9]\); - - \reg_sp.addr_matrix_f0_0[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[30]\); - - \prdata_RNO_6[28]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[28]\, - Y => \addr_matrix_f0_0_m_i[28]\); - - \reg_wp.addr_data_f2[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[3]\); - - \prdata_RNO[31]\ : OR3C - port map(A => \prdata_39_0_iv_3[31]\, B => - \prdata_39_0_iv_2[31]\, C => \prdata_39_0_iv_4[31]\, Y - => \prdata_39[31]\); - - \reg_sp.addr_matrix_f0_0[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[6]\); - - \prdata_RNO_17[5]\ : OR3A - port map(A => status_error_bad_component_error, B => N_157, - C => N_169, Y => status_error_bad_component_error_m_i); - - \prdata_RNO_10[7]\ : AOI1B - port map(A => \status_full_err[3]\, B => prdata_13_sqmuxa, - C => \addr_data_f0_m_i[7]\, Y => \prdata_39_0_iv_2[7]\); - - \prdata_RNO_13[4]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[4]\, - Y => \addr_matrix_f0_0_m_i[4]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_0\ : NOR3B - port map(A => N_930, B => N_172, C => apbi_c_20, Y => - addr_matrix_f1_1_sqmuxa_0); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_159, B => N_928, C => N_166, Y => - addr_matrix_f0_1_1_sqmuxa); - - \prdata_RNO_5[19]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[19]\, - Y => \addr_matrix_f0_1_m_i[19]\); - - \prdata_RNO_2[19]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[19]\, B => - \addr_matrix_f0_0_m_i[19]\, C => \prdata_39_0_iv_1[19]\, - Y => \prdata_39_0_iv_4[19]\); - - \prdata_RNO_3[2]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[2]\, C - => \addr_data_f2_m_i[2]\, Y => \prdata_39_0_iv_3[2]\); - - \prdata_RNO_0[7]\ : NOR3C - port map(A => \delta_snapshot_m_i[7]\, B => - \prdata_39_0_iv_1[7]\, C => \prdata_39_0_iv_5[7]\, Y => - \prdata_39_0_iv_9[7]\); - - \reg_wp.addr_data_f2[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[22]\); - - \reg_wp.delta_f2_f0[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[9]\); - - \prdata[17]\ : DFN1C0 - port map(D => \prdata_39[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(17)); - - \reg_wp.addr_data_f0[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[30]\); - - \prdata_RNO_7[31]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[31]\, C - => \addr_matrix_f2_m_i[31]\, Y => \prdata_39_0_iv_1[31]\); - - \prdata_RNO_8[2]\ : OR2B - port map(A => \nb_snapshot_param[2]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[2]\); - - \reg_wp.status_full_err[2]\ : DFN1C0 - port map(D => \status_full_err_RNO[2]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_full_err[2]\); - - \prdata_RNO_11[2]\ : OR3A - port map(A => status_ready_matrix_f1, B => N_157, C => - N_169, Y => status_ready_matrix_f1_m_i); - - \prdata_RNO_8[14]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[14]\, Y => \addr_matrix_f0_1_m_i[14]\); - - \reg_sp.addr_matrix_f2[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[31]\); - - \prdata_RNO_15[2]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f2\, Y => - enable_f2_m_i); - - \prdata[18]\ : DFN1C0 - port map(D => \prdata_39[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(18)); - - \reg_sp.addr_matrix_f2[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[30]\); - - \reg_wp.addr_data_f2[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[7]\); - - \prdata_RNO[13]\ : OR3C - port map(A => \prdata_39_0_iv_2[13]\, B => - \delta_snapshot_m_i[13]\, C => \prdata_39_0_iv_6[13]\, Y - => \prdata_39[13]\); - - \reg_wp.data_shaping_R0_0\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_R0_0\); - - \reg_sp.addr_matrix_f1[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[2]\); - - \reg_sp.addr_matrix_f1[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[18]\); - - \prdata_RNO_9[3]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[3]\, - Y => \addr_data_f2_m_i[3]\); - - \prdata_RNO_21[0]\ : OR3B - port map(A => N_161, B => \data_shaping_BW_c\, C => N_163, - Y => data_shaping_BW_m_i); - - \prdata_RNO_15[9]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[9]\, Y - => \delta_f2_f1_m_i[9]\); - - \prdata_RNO_0[31]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[31]\, C - => \addr_data_f2_m_i[31]\, Y => \prdata_39_0_iv_3[31]\); - - \prdata_RNO_0[3]\ : OR3B - port map(A => N_161_0, B => \data_shaping_R0_0\, C => N_163, - Y => data_shaping_R0_m_i); - - \prdata_RNO[3]\ : OR3C - port map(A => data_shaping_R0_m_i, B => - \prdata_39_0_iv_12[3]\, C => \prdata_39_0_iv_13[3]\, Y - => \prdata_39[3]\); - - \reg_wp.enable_f2\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \enable_f2\); - - \reg_wp.addr_data_f0[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[6]\); - - \reg_wp.addr_data_f0[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[31]\); - - \prdata_RNO[6]\ : OR3C - port map(A => \prdata_39_0_iv_10[6]\, B => - \prdata_39_0_iv_9[6]\, C => \prdata_39_0_iv_11[6]\, Y => - \prdata_39[6]\); - - \reg_wp.status_new_err_RNO_0[1]\ : NOR3A - port map(A => N_933_0, B => \status_new_err[1]\, C => - status_new_err_0_1, Y => N_149); - - \reg_wp.addr_data_f3[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[9]\); - - \reg_wp.status_new_err[1]\ : DFN1C0 - port map(D => \status_new_err_RNO[1]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_new_err[1]\); - - \prdata_RNO_10[5]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[5]\, Y - => \addr_data_f1_m_i[5]\); - - \prdata_RNO_16[7]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[7]\, - Y => \addr_data_f2_m_i[7]\); - - \prdata_RNO_1[1]\ : AOI1B - port map(A => \nb_burst_available[1]\, B => - prdata_17_sqmuxa, C => \prdata_39_0_iv_8[1]\, Y => - \prdata_39_0_iv_12[1]\); - - \reg_wp.status_full_RNO_0[1]\ : NOR3A - port map(A => N_933_0, B => \status_full_0[1]\, C => - status_full(1), Y => N_136); - - \prdata_RNO_14[6]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[6]\, - Y => \addr_data_f2_m_i[6]\); - - \prdata_RNO_1[21]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[21]\, C => \addr_matrix_f0_1_m_i[21]\, - Y => \prdata_39_0_iv_0[21]\); - - \prdata_RNO_1[26]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[26]\, C - => \addr_data_f1_m_i[26]\, Y => \prdata_39_0_iv_2[26]\); - - \prdata_RNO_1[15]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[15]\, - C => \addr_data_f2_m_i[15]\, Y => \prdata_39_0_iv_3[15]\); - - \prdata_RNO_14[2]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[2]\, C - => \delta_f2_f0_m_i[2]\, Y => \prdata_39_0_iv_4[2]\); - - \prdata_RNO_7[17]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[17]\, - C => \addr_matrix_f2_m_i[17]\, Y => - \prdata_39_0_iv_1[17]\); - - \prdata_RNO_13[1]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[1]\, - Y => \addr_matrix_f2_m_i[1]\); - - \reg_sp.addr_matrix_f0_1[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[26]\); - - \prdata_RNO_9[10]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[10]\, Y => \addr_matrix_f0_1_m_i[10]\); - - \prdata_RNO_3[13]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[13]\, - Y => \addr_data_f1_m_i[13]\); - - \prdata_RNO_7[20]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[20]\, C - => \addr_matrix_f2_m_i[20]\, Y => \prdata_39_0_iv_1[20]\); - - \status_full_ack_RNO[1]\ : NOR3A - port map(A => \status_full_0[1]\, B => apbi_c_51, C => - N_933_0, Y => \status_full_ack_8[1]\); - - \reg_wp.addr_data_f1[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[9]\); - - \reg_wp.addr_data_f0[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[27]\); - - \prdata_RNO_17[0]\ : OR2B - port map(A => \status_full_0[0]\, B => prdata_13_sqmuxa, Y - => \status_full_m_i[0]\); - - \reg_wp.delta_snapshot[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[3]\); - - \prdata_RNO_4[19]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[19]\, Y - => \addr_data_f1_m_i[19]\); - - \prdata_RNO[14]\ : OR3C - port map(A => \prdata_39_0_iv_2[14]\, B => - \delta_snapshot_m_i[14]\, C => \prdata_39_0_iv_6[14]\, Y - => \prdata_39[14]\); - - \reg_wp.status_full_err_RNO_0[3]\ : NOR3A - port map(A => N_933_0, B => \status_full_err[3]\, C => - status_full_err_0(3), Y => N_145); - - \prdata_RNO_2[30]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[30]\, B => - \addr_matrix_f0_0_m_i[30]\, C => \prdata_39_0_iv_1[30]\, - Y => \prdata_39_0_iv_4[30]\); - - \reg_sp.addr_matrix_f1[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[1]\); - - \prdata_RNO_6[27]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[27]\, - Y => \addr_matrix_f0_0_m_i[27]\); - - \prdata_RNO_3[30]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[30]\, Y - => \addr_data_f2_m_i[30]\); - - \prdata_RNO_6[7]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[7]\, Y - => \delta_f2_f0_m_i[7]\); - - \reg_sp.addr_matrix_f0_0[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[11]\); - - \reg_wp.addr_data_f3[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[14]\); - - \prdata_RNO_1[22]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[22]\, C - => \addr_data_f1_m_i[22]\, Y => \prdata_39_0_iv_2[22]\); - - \prdata_RNO[28]\ : OR3C - port map(A => \prdata_39_0_iv_3[28]\, B => - \prdata_39_0_iv_2[28]\, C => \prdata_39_0_iv_4[28]\, Y - => \prdata_39[28]\); - - \prdata_RNO_4[20]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[20]\, Y - => \addr_data_f1_m_i[20]\); - - \status_full_ack_RNO[3]\ : NOR3A - port map(A => \status_full_0[3]\, B => apbi_c_53, C => - \status_full_5_i_o2[0]\, Y => \status_full_ack_8[3]\); - - \reg_wp.nb_burst_available_1_sqmuxa_0_a2_1\ : NOR3A - port map(A => apbi_c_20, B => apbi_c_21, C => apbi_c_22, Y - => N_159); - - \reg_wp.addr_data_f2[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[8]\); - - \prdata_RNO_14[8]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[8]\, Y - => \addr_matrix_f1_m_i[8]\); - - \prdata_RNO_13[7]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[7]\, - Y => \addr_matrix_f0_1_m_i[7]\); - - \reg_wp.delta_f2_f1[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[5]\); - - \reg_wp.nb_snapshot_param[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[5]\); - - \reg_wp.addr_data_f2[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[19]\); - - \prdata_RNO_1[18]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[18]\, C => \addr_matrix_f0_1_m_i[18]\, - Y => \prdata_39_0_iv_0[18]\); - - \reg_wp.addr_data_f0[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[17]\); - - \prdata_RNO_14[4]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[4]\, - C => \addr_matrix_f2_m_i[4]\, Y => \prdata_39_0_iv_1[4]\); - - \prdata_RNO_5[15]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[15]\, - C => \addr_matrix_f2_m_i[15]\, Y => - \prdata_39_0_iv_1[15]\); - - \reg_wp.status_full_err_RNO_0[2]\ : NOR3A - port map(A => N_933_0, B => \status_full_err[2]\, C => - status_full_err_0(2), Y => N_143); - - \prdata_RNO_6[2]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[2]\, C - => enable_f2_m_i, Y => \prdata_39_0_iv_7[2]\); - - \prdata_RNO_2[15]\ : NOR3C - port map(A => \addr_data_f1_m_i[15]\, B => - \addr_data_f0_m_i[15]\, C => \delta_snapshot_m_i[15]\, Y - => \prdata_39_0_iv_5[15]\); - - \prdata_RNO_8[13]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[13]\, Y => \addr_matrix_f0_1_m_i[13]\); - - \reg_wp.addr_data_f3[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[18]\); - - prdata_5_sqmuxa_0_a2_0 : NOR2A - port map(A => N_172, B => N_157, Y => prdata_5_sqmuxa_0); - - \prdata_RNO_4[2]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[2]\, C - => status_ready_matrix_f1_m_i, Y => - \prdata_39_0_iv_2[2]\); - - \prdata_RNO_2[29]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[29]\, B => - \addr_matrix_f0_0_m_i[29]\, C => \prdata_39_0_iv_1[29]\, - Y => \prdata_39_0_iv_4[29]\); - - \prdata_RNO_0[20]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[20]\, - C => \addr_data_f2_m_i[20]\, Y => \prdata_39_0_iv_3[20]\); - - \reg_sp.addr_matrix_f2[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[16]\); - - \reg_wp.delta_f2_f1[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[0]\); - - \prdata_RNO_15[0]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[0]\, - Y => \addr_data_f2_m_i[0]\); - - \reg_wp.status_new_err_RNO[1]\ : OA1B - port map(A => apbi_c_59, B => \status_full_5_i_o2[0]\, C - => N_149, Y => \status_new_err_RNO[1]\); - - \prdata_RNO_1[6]\ : AOI1B - port map(A => \nb_snapshot_param[6]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_5[6]\, Y => \prdata_39_0_iv_9[6]\); - - \reg_sp.addr_matrix_f2[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[11]\); - - \reg_sp.addr_matrix_f2[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[10]\); - - \reg_sp.addr_matrix_f0_0[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[18]\); - - \prdata_RNO_20[3]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f3\, Y => - enable_f3_m_i); - - \reg_sp.addr_matrix_f0_0[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[29]\); - - \prdata_RNO_10[8]\ : AOI1B - port map(A => \status_new_err[0]\, B => prdata_13_sqmuxa, C - => \addr_data_f0_m_i[8]\, Y => \prdata_39_0_iv_2[8]\); - - \prdata_RNO_3[7]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[7]\, Y - => \delta_snapshot_m_i[7]\); - - \reg_wp.delta_f2_f1[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[4]\); - - \reg_sp.addr_matrix_f0_1[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[20]\); - - \prdata_RNO_4[30]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[30]\, Y - => \addr_data_f1_m_i[30]\); - - \reg_sp.addr_matrix_f2[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[26]\); - - \reg_sp.addr_matrix_f0_1[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[23]\); - - \prdata_RNO_5[18]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[18]\, Y - => \addr_data_f3_m_i[18]\); - - \reg_wp.delta_snapshot[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[15]\); - - \prdata_RNO_2[18]\ : NOR3C - port map(A => \addr_data_f3_m_i[18]\, B => - \addr_data_f2_m_i[18]\, C => \prdata_39_0_iv_2[18]\, Y - => \prdata_39_0_iv_5[18]\); - - \reg_wp.data_shaping_R1\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => data_shaping_BW_1_sqmuxa, Q => data_shaping_R1); - - \prdata_RNO_12[6]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[6]\, - Y => \addr_matrix_f0_0_m_i[6]\); - - \reg_sp.addr_matrix_f0_1[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[12]\); - - \reg_wp.delta_snapshot[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[0]\); - - \reg_sp.addr_matrix_f2[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[21]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_159, B => N_928, C => N_930, Y => - addr_matrix_f0_0_1_sqmuxa); - - \prdata_RNO_0[0]\ : NOR3C - port map(A => \delta_snapshot_m_i[0]\, B => - \prdata_39_0_iv_2[0]\, C => \prdata_39_0_iv_9[0]\, Y => - \prdata_39_0_iv_13[0]\); - - \prdata_RNO_8[1]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[1]\, B => - \addr_matrix_f0_0_m_i[1]\, C => \status_full_m_i[1]\, Y - => \prdata_39_0_iv_6[1]\); - - \reg_wp.enable_f3\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \enable_f3\); - - \prdata[24]\ : DFN1C0 - port map(D => \prdata_39[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(24)); - - \prdata_RNO[22]\ : OR3C - port map(A => \prdata_39_0_iv_3[22]\, B => - \prdata_39_0_iv_2[22]\, C => \prdata_39_0_iv_4[22]\, Y - => \prdata_39[22]\); - - \reg_sp.addr_matrix_f2[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[20]\); - - \prdata_RNO_4[15]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[15]\, - Y => \addr_matrix_f0_0_m_i[15]\); - - \prdata_RNO_18[0]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[0]\, Y - => \delta_f2_f1_m_i[0]\); - - \prdata_RNO_13[2]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[2]\, Y - => \delta_f2_f1_m_i[2]\); - - \prdata_RNO_8[8]\ : OR2B - port map(A => \nb_snapshot_param[8]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[8]\); - - \prdata_RNO_8[21]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[21]\, Y - => \addr_data_f1_m_i[21]\); - - \prdata_RNO_8[26]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[26]\, Y - => \addr_matrix_f2_m_i[26]\); - - \prdata_RNO_1[17]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[17]\, C - => \addr_data_f1_m_i[17]\, Y => \prdata_39_0_iv_2[17]\); - - \prdata_RNO_14[9]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[9]\, - Y => \addr_matrix_f0_0_m_i[9]\); - - \prdata_RNO[20]\ : OR3C - port map(A => \prdata_39_0_iv_3[20]\, B => - \prdata_39_0_iv_2[20]\, C => \prdata_39_0_iv_4[20]\, Y - => \prdata_39[20]\); - - \prdata_RNO_15[5]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[5]\, Y - => \delta_f2_f1_m_i[5]\); - - \prdata_RNO_12[3]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[3]\, Y - => \addr_data_f3_m_i[3]\); - - \reg_sp.addr_matrix_f0_1[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[31]\); - - \prdata_RNO_5[24]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[24]\, - Y => \addr_matrix_f0_1_m_i[24]\); - - \reg_sp.addr_matrix_f1[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[5]\); - - prdata_15_sqmuxa_0_a2 : NOR2B - port map(A => N_164, B => N_161, Y => prdata_15_sqmuxa); - - \reg_wp.delta_snapshot[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[12]\); - - \prdata_RNO_19[1]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[1]\, C - => \delta_f2_f1_m_i[1]\, Y => \prdata_39_0_iv_5[1]\); - - \reg_wp.status_new_err_RNO_0[2]\ : NOR3A - port map(A => N_933_0, B => \status_new_err[2]\, C => - status_new_err_0_2, Y => N_151); - - \prdata_RNO_6[11]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[11]\, Y - => \addr_data_f3_m_i[11]\); - - \prdata_RNO_6[16]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[16]\, - Y => \addr_matrix_f0_0_m_i[16]\); - - \prdata_RNO_3[10]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[10]\, C => \addr_matrix_f0_1_m_i[10]\, - Y => \prdata_39_0_iv_0[10]\); - - \prdata_RNO_14[5]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[5]\, - C => \addr_matrix_f2_m_i[5]\, Y => \prdata_39_0_iv_1[5]\); - - \prdata_RNO_17[3]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[3]\, Y - => \delta_snapshot_m_i[3]\); - - \prdata_RNO_8[22]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[22]\, Y - => \addr_matrix_f2_m_i[22]\); - - prdata_17_sqmuxa_0_a2 : NOR3B - port map(A => N_158, B => N_159, C => apbi_c_19, Y => - prdata_17_sqmuxa); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2_0_0\ : NOR3C - port map(A => N_159, B => N_928, C => N_166, Y => - addr_matrix_f0_1_1_sqmuxa_0); - - \reg_wp.addr_data_f1[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[30]\); - - \prdata_RNO_2[25]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[25]\, B => - \addr_matrix_f0_0_m_i[25]\, C => \prdata_39_0_iv_1[25]\, - Y => \prdata_39_0_iv_4[25]\); - - \prdata_RNO_4[18]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[18]\, - Y => \addr_matrix_f0_1_m_i[18]\); - - \reg_wp.nb_burst_available[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[2]\); - - \prdata_RNO_8[6]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[6]\, - Y => \addr_matrix_f2_m_i[6]\); - - \prdata_RNO_3[3]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[3]\, C - => \addr_data_f2_m_i[3]\, Y => \prdata_39_0_iv_3[3]\); - - \reg_wp.delta_snapshot[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[14]\); - - \reg_wp.delta_f2_f1[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[9]\); - - \reg_sp.addr_matrix_f2[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[14]\); - - \prdata_RNO_6[12]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[12]\, - C => \addr_data_f2_m_i[12]\, Y => \prdata_39_0_iv_3[12]\); - - \prdata_RNO_9[5]\ : OR2B - port map(A => \nb_burst_available[5]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[5]\); - - \prdata_RNO_5[0]\ : AOI1B - port map(A => \nb_burst_available[0]\, B => - prdata_17_sqmuxa, C => enable_f0_m_i, Y => - \prdata_39_0_iv_9[0]\); - - \reg_wp.addr_data_f3[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[27]\); - - \prdata_RNO_5[17]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[17]\, - Y => \addr_matrix_f0_1_m_i[17]\); - - \prdata_RNO_17[7]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[7]\, Y - => \addr_data_f0_m_i[7]\); - - \prdata_RNO_2[17]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[17]\, B => - \addr_matrix_f0_0_m_i[17]\, C => \prdata_39_0_iv_1[17]\, - Y => \prdata_39_0_iv_4[17]\); - - \reg_wp.nb_snapshot_param[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[10]\); - - \reg_sp.addr_matrix_f1[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[16]\); - - \reg_wp.delta_snapshot[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[11]\); - - \reg_sp.config_active_interruption_onNewMatrix\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => config_active_interruption_onError_0_sqmuxa, Q => - config_active_interruption_onNewMatrix); - - \reg_wp.addr_data_f1[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[31]\); - - \reg_wp.status_full_RNO[3]\ : OA1B - port map(A => apbi_c_53, B => \status_full_5_i_o2[0]\, C - => N_138, Y => \status_full_RNO[3]\); - - \prdata_RNO_3[24]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[24]\, Y - => \addr_data_f2_m_i[24]\); - - \reg_wp.addr_data_f3[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[19]\); - - \prdata_RNO_2[8]\ : NOR3C - port map(A => \prdata_39_0_iv_3[8]\, B => - \prdata_39_0_iv_2[8]\, C => \nb_burst_available_m_i[8]\, - Y => \prdata_39_0_iv_10[8]\); - - \reg_sp.addr_matrix_f1[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[11]\); - - \status_full_ack_RNO[2]\ : NOR3A - port map(A => \status_full_0[2]\, B => apbi_c_52, C => - N_933_0, Y => \status_full_ack_8[2]\); - - \reg_sp.addr_matrix_f0_1[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[24]\); - - \reg_sp.addr_matrix_f0_1[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[3]\); - - \reg_sp.addr_matrix_f0_1[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => - \addr_matrix_f0_1[25]\); - - \prdata_RNO_8[10]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[10]\, - C => \prdata_39_0_iv_1[10]\, Y => \prdata_39_0_iv_5[10]\); - - \reg_sp.addr_matrix_f1[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[10]\); - - \reg_sp.status_error_anticipating_empty_fifo_1_sqmuxa_0_a2\ : - NOR3 - port map(A => N_157, B => un1_apbi_2, C => N_169, Y => - status_error_anticipating_empty_fifo_1_sqmuxa); - - prdata_3_sqmuxa_0_a2 : NOR3C - port map(A => N_159, B => N_928, C => apbi_c_19, Y => - prdata_3_sqmuxa); - - \prdata_RNO_3[0]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[0]\, Y - => \delta_snapshot_m_i[0]\); - - \prdata_RNO_2[2]\ : NOR3C - port map(A => \prdata_39_0_iv_6[2]\, B => - \nb_snapshot_param_m_i[2]\, C => data_shaping_SP1_m_i, Y - => \prdata_39_0_iv_13[2]\); - - \prdata_RNO_7[7]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[7]\, Y - => \addr_data_f3_m_i[7]\); - - \prdata_RNO_13[5]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[5]\, - Y => \addr_matrix_f0_0_m_i[5]\); - - \prdata_RNO_3[4]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[4]\, C - => \addr_data_f1_m_i[4]\, Y => \prdata_39_0_iv_3[4]\); - - \lpp_top_apbreg.un1_apbi_2\ : OR2B - port map(A => apbi_c_49, B => apbi_c_16, Y => un1_apbi_2); - - \reg_wp.status_full_err_RNO[3]\ : OA1B - port map(A => apbi_c_57, B => \status_full_5_i_o2[0]\, C - => N_145, Y => \status_full_err_RNO[3]\); - - \reg_sp.addr_matrix_f2[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[7]\); - - \reg_sp.addr_matrix_f2[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[24]\); - - \reg_wp.addr_data_f1[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[24]\); - - \prdata_RNO_5[6]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[6]\, C - => \addr_data_f2_m_i[6]\, Y => \prdata_39_0_iv_3[6]\); - - \prdata_RNO_2[28]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[28]\, B => - \addr_matrix_f0_0_m_i[28]\, C => \prdata_39_0_iv_1[28]\, - Y => \prdata_39_0_iv_4[28]\); - - \prdata_RNO_16[4]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => \addr_data_f2[4]\, - Y => \addr_data_f2_m_i[4]\); - - \prdata_RNO[17]\ : OR3C - port map(A => \prdata_39_0_iv_3[17]\, B => - \prdata_39_0_iv_2[17]\, C => \prdata_39_0_iv_4[17]\, Y - => \prdata_39[17]\); - - \reg_wp.addr_data_f0[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[23]\); - - \prdata_RNO[25]\ : OR3C - port map(A => \prdata_39_0_iv_3[25]\, B => - \prdata_39_0_iv_2[25]\, C => \prdata_39_0_iv_4[25]\, Y - => \prdata_39[25]\); - - \prdata[20]\ : DFN1C0 - port map(D => \prdata_39[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(20)); - - \reg_wp.addr_data_f0[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[20]\); - - \prdata_RNO_1[4]\ : AOI1B - port map(A => \nb_snapshot_param[4]\, B => prdata_18_sqmuxa, - C => \prdata_39_0_iv_6[4]\, Y => \prdata_39_0_iv_10[4]\); - - \prdata_RNO_21[1]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[1]\, Y - => \delta_f2_f1_m_i[1]\); - - \reg_wp.addr_data_f3[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[1]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \prdata_RNO_8[3]\ : NOR3C - port map(A => \delta_snapshot_m_i[3]\, B => - \prdata_39_0_iv_1[3]\, C => \nb_burst_available_m_i[3]\, - Y => \prdata_39_0_iv_11[3]\); - - \reg_sp.addr_matrix_f0_0[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[27]\); - - \prdata_RNO_1[29]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[29]\, C - => \addr_data_f1_m_i[29]\, Y => \prdata_39_0_iv_2[29]\); - - \prdata_RNO_5[23]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[23]\, Y - => \addr_data_f3_m_i[23]\); - - \prdata_RNO_17[8]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[8]\, Y - => \addr_data_f0_m_i[8]\); - - \prdata_RNO_10[6]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[6]\, Y - => \delta_snapshot_m_i[6]\); - - \prdata_RNO_0[14]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[14]\, C - => \addr_data_f1_m_i[14]\, Y => \prdata_39_0_iv_2[14]\); - - prdata_14_sqmuxa_0_a2 : NOR3B - port map(A => apbi_c_21, B => apbi_c_19, C => N_931, Y => - prdata_14_sqmuxa); - - \reg_wp.addr_data_f1[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[28]\); - - \reg_wp.delta_snapshot[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[13]\); - - \prdata_RNO_8[7]\ : OR2B - port map(A => \nb_snapshot_param[7]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[7]\); - - \reg_wp.addr_data_f0[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[21]\); - - prdata_3_sqmuxa_0_a2_0 : NOR3C - port map(A => N_159, B => N_928, C => apbi_c_19, Y => - prdata_3_sqmuxa_0); - - \prdata[23]\ : DFN1C0 - port map(D => \prdata_39[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(23)); - - \prdata_RNO_4[17]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[17]\, - Y => \addr_data_f1_m_i[17]\); - - \reg_wp.delta_f2_f0[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[6]\); - - \prdata_RNO_9[11]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[11]\, - C => \addr_data_f2_m_i[11]\, Y => \prdata_39_0_iv_3[11]\); - - \prdata_RNO_7[21]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[21]\, C - => \addr_data_f1_m_i[21]\, Y => \prdata_39_0_iv_2[21]\); - - \prdata_RNO_7[26]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[26]\, C - => \addr_matrix_f2_m_i[26]\, Y => \prdata_39_0_iv_1[26]\); - - \prdata_RNO[9]\ : OR3C - port map(A => \prdata_39_0_iv_9[9]\, B => - \prdata_39_0_iv_8[9]\, C => \prdata_39_0_iv_10[9]\, Y => - \prdata_39[9]\); - - \reg_wp.addr_data_f0[13]\ : DFN1E1C0 - port map(D => apbi_c_63, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[13]\); - - \prdata_RNO_20[2]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[2]\, - Y => \addr_matrix_f2_m_i[2]\); - - \prdata_RNO_12[7]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[7]\, - Y => \addr_matrix_f2_m_i[7]\); - - \reg_wp.addr_data_f0[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[10]\); - - \prdata_RNO_2[31]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[31]\, B => - \addr_matrix_f0_0_m_i[31]\, C => \prdata_39_0_iv_1[31]\, - Y => \prdata_39_0_iv_4[31]\); - - \prdata_RNO_13[3]\ : AOI1B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[3]\, C - => enable_f3_m_i, Y => \prdata_39_0_iv_5[3]\); - - \prdata_RNO_14[3]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[3]\, - Y => \addr_matrix_f0_1_m_i[3]\); - - \prdata_RNO_3[31]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[31]\, Y - => \addr_data_f2_m_i[31]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0\ : NOR3C - port map(A => apbi_c_22, B => N_928, C => apbi_c_21, Y => - N_168); - - \prdata_RNO_5[5]\ : AOI1B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[5]\, C - => \prdata_39_0_iv_2[5]\, Y => \prdata_39_0_iv_7[5]\); - - \reg_wp.addr_data_f1[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[14]\); - - \reg_sp.addr_matrix_f2[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[1]\); - - \reg_wp.delta_snapshot[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_snapshot_1_sqmuxa, Q => \delta_snapshot[9]\); - - \prdata[30]\ : DFN1C0 - port map(D => \prdata_39[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(30)); - - \prdata_RNO_13[8]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[8]\, - Y => \addr_matrix_f2_m_i[8]\); - - \reg_wp.status_new_err[3]\ : DFN1C0 - port map(D => \status_new_err_RNO[3]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_new_err_0[3]\); - - \reg_wp.addr_data_f1[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[0]\); - - \prdata_RNO_12[2]\ : OR2B - port map(A => \status_full_0[2]\, B => prdata_13_sqmuxa, Y - => \status_full_m_i[2]\); - - \reg_wp.delta_f2_f0[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[4]\); - - \prdata_RNO_12[1]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f1\, Y => - enable_f1_m_i); - - \prdata[11]\ : DFN1C0 - port map(D => \prdata_39[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(11)); - - \reg_sp.addr_matrix_f0_0[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[19]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0_0\ : NOR3C - port map(A => apbi_c_22, B => N_928, C => apbi_c_21, Y => - N_168_0); - - \reg_wp.addr_data_f0[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[11]\); - - \prdata_RNO_4[21]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[21]\, - Y => \addr_matrix_f0_1_m_i[21]\); - - \prdata_RNO_4[26]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[26]\, Y - => \addr_data_f1_m_i[26]\); - - \prdata_RNO_9[12]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[12]\, Y => \addr_data_f2_m_i[12]\); - - \prdata_RNO_3[23]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[23]\, Y - => \addr_matrix_f2_m_i[23]\); - - \prdata_RNO_7[22]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[22]\, C - => \addr_matrix_f2_m_i[22]\, Y => \prdata_39_0_iv_1[22]\); - - \reg_sp.addr_matrix_f0_1[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[5]\); - - \reg_wp.addr_data_f1[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[18]\); - - \prdata_RNO_2[27]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[27]\, B => - \addr_matrix_f0_0_m_i[27]\, C => \prdata_39_0_iv_1[27]\, - Y => \prdata_39_0_iv_4[27]\); - - \prdata_RNO_9[0]\ : NOR3C - port map(A => \status_full_m_i[0]\, B => - \delta_f2_f1_m_i[0]\, C => \prdata_39_0_iv_5[0]\, Y => - \prdata_39_0_iv_11[0]\); - - \reg_sp.status_ready_matrix_f0_1\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f0_1); - - \reg_sp.addr_matrix_f1[14]\ : DFN1E1C0 - port map(D => apbi_c_64, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[14]\); - - \prdata_RNO_5[8]\ : NOR3C - port map(A => \addr_matrix_f2_m_i[8]\, B => - \addr_matrix_f1_m_i[8]\, C => \delta_snapshot_m_i[8]\, Y - => \prdata_39_0_iv_6[8]\); - - \prdata_RNO[30]\ : OR3C - port map(A => \prdata_39_0_iv_3[30]\, B => - \prdata_39_0_iv_2[30]\, C => \prdata_39_0_iv_4[30]\, Y - => \prdata_39[30]\); - - \apbo.pirq_RNO_2[15]\ : NOR3A - port map(A => \pirq_2_i_a2_5[15]\, B => status_full(1), C - => status_full(0), Y => \pirq_2_i_a2_8[15]\); - - \prdata_RNO_0[21]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[21]\, C - => \addr_matrix_f2_m_i[21]\, Y => \prdata_39_0_iv_1[21]\); - - \reg_sp.addr_matrix_f0_1[11]\ : DFN1E1C0 - port map(D => apbi_c_61, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[11]\); - - \prdata_RNO_7[14]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[14]\, - Y => \addr_matrix_f2_m_i[14]\); - - \prdata_RNO_11[0]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f0\, Y => - enable_f0_m_i); - - \prdata_RNO_0[26]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[26]\, - C => \addr_data_f2_m_i[26]\, Y => \prdata_39_0_iv_3[26]\); - - \prdata_RNO_4[8]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[8]\, Y - => \delta_f2_f1_m_i[8]\); - - \reg_sp.addr_matrix_f0_0[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[5]\); - - prdata_12_sqmuxa_0_a2 : NOR2A - port map(A => N_168, B => N_157, Y => prdata_12_sqmuxa); - - \prdata_RNO_21[3]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[3]\, - Y => \addr_matrix_f2_m_i[3]\); - - \prdata_RNO_4[22]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[22]\, Y - => \addr_data_f1_m_i[22]\); - - \reg_wp.addr_data_f0[9]\ : DFN1E1C0 - port map(D => apbi_c_59, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[9]\); - - prdata_5_sqmuxa_0_a2 : NOR2A - port map(A => N_172, B => N_157, Y => prdata_5_sqmuxa); - - \reg_wp.addr_data_f2[2]\ : DFN1E1C0 - port map(D => apbi_c_52, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[2]\); - - \prdata_RNO_6[30]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[30]\, - Y => \addr_matrix_f0_0_m_i[30]\); - - \prdata_RNO_6[24]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[24]\, - Y => \addr_matrix_f0_0_m_i[24]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_1\ : NOR3B - port map(A => apbi_c_21, B => N_928, C => apbi_c_22, Y => - N_172); - - \reg_wp.addr_data_f0[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[25]\); - - \reg_sp.addr_matrix_f0_0[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[7]\); - - \prdata_RNO_17[2]\ : OR2B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[2]\, - Y => \addr_matrix_f0_0_m_i[2]\); - - \prdata_RNO_0[13]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[13]\, C - => \addr_data_f1_m_i[13]\, Y => \prdata_39_0_iv_2[13]\); - - \reg_wp.nb_snapshot_param[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[8]\); - - \reg_wp.addr_data_f0[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa, Q => \addr_data_f0[26]\); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_172, B => N_157, C => un1_apbi_2, Y => - addr_matrix_f2_1_sqmuxa); - - \reg_wp.delta_snapshot_1_sqmuxa_0_a2\ : NOR3B - port map(A => apbi_c_21, B => N_166, C => N_931, Y => - delta_snapshot_1_sqmuxa); - - \reg_sp.addr_matrix_f0_1[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[6]\); - - \prdata_RNO_1[25]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[25]\, C - => \addr_data_f1_m_i[25]\, Y => \prdata_39_0_iv_2[25]\); - - \reg_wp.addr_data_f1_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_166, B => apbi_c_21, C => N_931, Y => - addr_data_f1_1_sqmuxa_0); - - \prdata_RNO_15[1]\ : AOI1B - port map(A => prdata_0_sqmuxa, B => - config_active_interruption_onError, C => - status_ready_matrix_f0_1_m_i, Y => \prdata_39_0_iv_2[1]\); - - \reg_wp.addr_data_f2[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[17]\); - - \prdata_RNO[11]\ : OR3C - port map(A => \prdata_39_0_iv_5[11]\, B => - \prdata_39_0_iv_4[11]\, C => \prdata_39_0_iv_6[11]\, Y - => \prdata_39[11]\); - - \prdata[25]\ : DFN1C0 - port map(D => \prdata_39[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(25)); - - \prdata_RNO_1[8]\ : NOR3C - port map(A => \delta_f2_f0_m_i[8]\, B => - \addr_data_f3_m_i[8]\, C => \nb_snapshot_param_m_i[8]\, Y - => \prdata_39_0_iv_8[8]\); - - \prdata_RNO_0[22]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[22]\, - C => \addr_data_f2_m_i[22]\, Y => \prdata_39_0_iv_3[22]\); - - \prdata_RNO_4[31]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[31]\, Y - => \addr_data_f1_m_i[31]\); - - \reg_wp.addr_data_f2[24]\ : DFN1E1C0 - port map(D => apbi_c_74, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[24]\); - - \reg_wp.status_full_err_RNO_0[1]\ : NOR3A - port map(A => N_933_0, B => \status_full_err[1]\, C => - status_full_err_0(1), Y => N_141); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_172, B => N_157, C => un1_apbi_2, Y => - addr_matrix_f2_1_sqmuxa_0); - - \reg_sp.addr_matrix_f2[8]\ : DFN1E1C0 - port map(D => apbi_c_58, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[8]\); - - \prdata_RNO_8[9]\ : OR2B - port map(A => \nb_snapshot_param[9]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[9]\); - - \status_full_ack[3]\ : DFN1C0 - port map(D => \status_full_ack_8[3]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => status_full_ack(3)); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_164, B => N_157, C => un1_apbi_2, Y => - delta_f2_f0_1_sqmuxa); - - \prdata_RNO[29]\ : OR3C - port map(A => \prdata_39_0_iv_3[29]\, B => - \prdata_39_0_iv_2[29]\, C => \prdata_39_0_iv_4[29]\, Y - => \prdata_39[29]\); - - \prdata_RNO_14[0]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[0]\, - C => \addr_matrix_f2_m_i[0]\, Y => \prdata_39_0_iv_1[0]\); - - \prdata_RNO_6[5]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[5]\, B => - \addr_matrix_f0_0_m_i[5]\, C => \prdata_39_0_iv_1[5]\, Y - => \prdata_39_0_iv_6[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \prdata_RNO_8[29]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[29]\, Y - => \addr_matrix_f2_m_i[29]\); - - \reg_wp.status_full[0]\ : DFN1C0 - port map(D => \status_full_RNO[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \status_full_0[0]\); - - \reg_sp.addr_matrix_f0_1[18]\ : DFN1E1C0 - port map(D => apbi_c_68, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_1_1_sqmuxa_0, Q => - \addr_matrix_f0_1[18]\); - - \prdata_RNO[16]\ : OR3C - port map(A => \prdata_39_0_iv_3[16]\, B => - \prdata_39_0_iv_2[16]\, C => \prdata_39_0_iv_4[16]\, Y - => \prdata_39[16]\); - - \prdata[0]\ : DFN1C0 - port map(D => \prdata_39[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(0)); - - \apbo.pirq_RNO_5[15]\ : NOR2 - port map(A => status_full(2), B => status_full(3), Y => - \pirq_2_i_a2_5[15]\); - - \reg_wp.addr_data_f0_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_930, B => apbi_c_21, C => N_931, Y => - addr_data_f0_1_sqmuxa_0); - - \reg_wp.addr_data_f0[15]\ : DFN1E1C0 - port map(D => apbi_c_65, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[15]\); - - prdata_9_sqmuxa_0_a2_0 : NOR3 - port map(A => apbi_c_21, B => N_931, C => apbi_c_19, Y => - prdata_9_sqmuxa_0); - - \reg_wp.addr_data_f3[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[6]\); - - \reg_wp.addr_data_f2[28]\ : DFN1E1C0 - port map(D => apbi_c_78, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[28]\); - - \reg_wp.addr_data_f0[16]\ : DFN1E1C0 - port map(D => apbi_c_66, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[16]\); - - \reg_wp.status_full_err[1]\ : DFN1C0 - port map(D => \status_full_err_RNO[1]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \status_full_err[1]\); - - \reg_wp.nb_burst_available[10]\ : DFN1E1C0 - port map(D => apbi_c_60, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[10]\); - - \reg_wp.nb_snapshot_param[1]\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[1]\); - - \reg_wp.addr_data_f1[29]\ : DFN1E1C0 - port map(D => apbi_c_79, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[29]\); - - \reg_sp.addr_matrix_f0_0[26]\ : DFN1E1C0 - port map(D => apbi_c_76, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa, Q => - \addr_matrix_f0_0[26]\); - - \prdata_RNO_7[4]\ : OR2B - port map(A => \nb_burst_available[4]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[4]\); - - \prdata_RNO_5[20]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[20]\, - Y => \addr_matrix_f0_1_m_i[20]\); - - \prdata_RNO_6[19]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[19]\, - Y => \addr_matrix_f0_0_m_i[19]\); - - prdata_1_sqmuxa_0_a2_0 : OR2A - port map(A => apbi_c_19, B => apbi_c_20, Y => N_157); - - \reg_wp.delta_f2_f1_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_930, B => N_164, C => apbi_c_20, Y => - delta_f2_f1_1_sqmuxa); - - \reg_wp.addr_data_f2[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f2_1_sqmuxa, Q => \addr_data_f2[5]\); - - \reg_sp.addr_matrix_f1[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[3]\); - - \prdata_RNO_1[28]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[28]\, C - => \addr_data_f1_m_i[28]\, Y => \prdata_39_0_iv_2[28]\); - - \reg_sp.addr_matrix_f1[25]\ : DFN1E1C0 - port map(D => apbi_c_75, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[25]\); - - \prdata_RNO_16[0]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[0]\, Y - => \addr_data_f1_m_i[0]\); - - \reg_wp.addr_data_f3[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[23]\); - - \reg_wp.addr_data_f3[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[20]\); - - \reg_wp.nb_burst_available[0]\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[0]\); - - \prdata_RNO_3[11]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[11]\, - C => \addr_matrix_f2_m_i[11]\, Y => - \prdata_39_0_iv_1[11]\); - - \prdata_RNO_3[16]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[16]\, Y => \addr_data_f2_m_i[16]\); - - \reg_wp.addr_data_f3[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa, Q => \addr_data_f3[4]\); - - \reg_sp.addr_matrix_f1[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[22]\); - - \prdata_RNO_4[4]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f0\, Y => - burst_f0_m_i); - - \prdata_RNO_7[13]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[13]\, - Y => \addr_matrix_f2_m_i[13]\); - - \prdata[9]\ : DFN1C0 - port map(D => \prdata_39[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(9)); - - \prdata[8]\ : DFN1C0 - port map(D => \prdata_39[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(8)); - - \prdata_RNO_10[3]\ : OR3A - port map(A => status_ready_matrix_f2, B => N_157, C => - N_169, Y => status_ready_matrix_f2_m_i); - - \reg_sp.addr_matrix_f1[27]\ : DFN1E1C0 - port map(D => apbi_c_77, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[27]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg_wp.addr_data_f3[21]\ : DFN1E1C0 - port map(D => apbi_c_71, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[21]\); - - \prdata_RNO_6[23]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[23]\, Y - => \addr_data_f2_m_i[23]\); - - \prdata_RNO_18[5]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[5]\, - Y => \addr_matrix_f2_m_i[5]\); - - \reg_wp.addr_data_f0[22]\ : DFN1E1C0 - port map(D => apbi_c_72, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[22]\); - - \prdata[22]\ : DFN1C0 - port map(D => \prdata_39[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(22)); - - \prdata_RNO_5[3]\ : NOR3C - port map(A => \delta_f2_f0_m_i[3]\, B => - \addr_data_f3_m_i[3]\, C => \prdata_39_0_iv_5[3]\, Y => - \prdata_39_0_iv_9[3]\); - - \prdata_RNO_11[5]\ : AOI1B - port map(A => \status_full_err[1]\, B => prdata_13_sqmuxa, - C => status_error_bad_component_error_m_i, Y => - \prdata_39_0_iv_2[5]\); - - \reg_sp.addr_matrix_f0_0[17]\ : DFN1E1C0 - port map(D => apbi_c_67, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[17]\); - - prdata_10_sqmuxa_0_a2 : NOR3A - port map(A => apbi_c_19, B => apbi_c_21, C => N_931, Y => - prdata_10_sqmuxa); - - \prdata[29]\ : DFN1C0 - port map(D => \prdata_39[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(29)); - - \prdata_RNO_4[6]\ : NOR3C - port map(A => \addr_matrix_f0_1_m_i[6]\, B => - \addr_matrix_f0_0_m_i[6]\, C => \delta_f2_f1_m_i[6]\, Y - => \prdata_39_0_iv_5[6]\); - - \reg_wp.nb_snapshot_param[4]\ : DFN1E1C0 - port map(D => apbi_c_54, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[4]\); - - \reg_wp.nb_snapshot_param[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_snapshot_param_1_sqmuxa, Q => - \nb_snapshot_param[7]\); - - \reg_wp.addr_data_f1[19]\ : DFN1E1C0 - port map(D => apbi_c_69, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[19]\); - - \prdata_RNO_3[20]\ : OR3C - port map(A => N_161, B => N_168, C => \addr_data_f2[20]\, Y - => \addr_data_f2_m_i[20]\); - - \prdata_RNO_3[12]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[12]\, - Y => \addr_data_f1_m_i[12]\); - - \reg_sp.addr_matrix_f2[5]\ : DFN1E1C0 - port map(D => apbi_c_55, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[5]\); - - \prdata_RNO_9[4]\ : OR3B - port map(A => N_161_0, B => \data_shaping_R1_0\, C => N_163, - Y => data_shaping_R1_m_i); - - \prdata_RNO[4]\ : OR3C - port map(A => \prdata_39_0_iv_11[4]\, B => - \prdata_39_0_iv_10[4]\, C => \prdata_39_0_iv_14[4]\, Y - => \prdata_39[4]\); - - \prdata_RNO_1[14]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[14]\, - Y => \delta_snapshot_m_i[14]\); - - \prdata_RNO_6[9]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[9]\, Y - => \delta_f2_f0_m_i[9]\); - - \reg_sp.addr_matrix_f1[31]\ : DFN1E1C0 - port map(D => apbi_c_81, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[31]\); - - \prdata_RNO_4[1]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[1]\, C - => \addr_data_f1_m_i[1]\, Y => \prdata_39_0_iv_3[1]\); - - \reg_wp.nb_burst_available[3]\ : DFN1E1C0 - port map(D => apbi_c_53, CLK => HCLK_c, CLR => HRESETn_c, E - => nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[3]\); - - \reg_sp.addr_matrix_f1[30]\ : DFN1E1C0 - port map(D => apbi_c_80, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[30]\); - - \prdata_RNO_8[11]\ : OR2B - port map(A => \status_new_err_0[3]\, B => prdata_13_sqmuxa, - Y => \status_new_err_m_i[3]\); - - \prdata_RNO_8[16]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[16]\, - Y => \addr_matrix_f2_m_i[16]\); - - \reg_wp.nb_burst_available_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_158, B => N_159, C => N_930, Y => - nb_burst_available_1_sqmuxa); - - \reg_sp.status_ready_matrix_f0_0\ : DFN1E1C0 - port map(D => apbi_c_50, CLK => HCLK_c, CLR => HRESETn_c, E - => status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f0_0); - - \prdata_RNO_0[2]\ : NOR3C - port map(A => \prdata_39_0_iv_3[2]\, B => - \prdata_39_0_iv_2[2]\, C => \prdata_39_0_iv_9[2]\, Y => - \prdata_39_0_iv_12[2]\); - - \reg_wp.addr_data_f1[6]\ : DFN1E1C0 - port map(D => apbi_c_56, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[6]\); - - \prdata_RNO_10[10]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[10]\, Y => \addr_data_f2_m_i[10]\); - - \reg_wp.addr_data_f1[7]\ : DFN1E1C0 - port map(D => apbi_c_57, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f1_1_sqmuxa, Q => \addr_data_f1[7]\); - - \reg_wp.addr_data_f0[12]\ : DFN1E1C0 - port map(D => apbi_c_62, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[12]\); - - \prdata_RNO_8[25]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[25]\, Y - => \addr_matrix_f2_m_i[25]\); - - \prdata_RNO_1[27]\ : AOI1B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[27]\, C - => \addr_data_f1_m_i[27]\, Y => \prdata_39_0_iv_2[27]\); - - \reg_sp.addr_matrix_f0_0[20]\ : DFN1E1C0 - port map(D => apbi_c_70, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[20]\); - - \prdata_RNO_18[4]\ : OR3A - port map(A => status_error_anticipating_empty_fifo, B => - N_157, C => N_169, Y => - status_error_anticipating_empty_fifo_m_i); - - \prdata_RNO_20[4]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[4]\, Y - => \delta_f2_f1_m_i[4]\); - - \prdata_RNO_0[10]\ : NOR3C - port map(A => \prdata_39_0_iv_0[10]\, B => - \addr_data_f3_m_i[10]\, C => \prdata_39_0_iv_3[10]\, Y - => \prdata_39_0_iv_7[10]\); - - \reg_wp.nb_snapshot_param_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_158, B => N_159, C => N_166, Y => - nb_snapshot_param_1_sqmuxa); - - \reg_wp.enable_f1\ : DFN1E1C0 - port map(D => apbi_c_51, CLK => HCLK_c, CLR => HRESETn_c, E - => burst_f0_1_sqmuxa, Q => \enable_f1\); - - \reg_sp.addr_matrix_f0_0[23]\ : DFN1E1C0 - port map(D => apbi_c_73, CLK => HCLK_c, CLR => HRESETn_c, E - => addr_matrix_f0_0_1_sqmuxa_0, Q => - \addr_matrix_f0_0[23]\); - - \prdata_RNO_4[9]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[9]\, - C => \addr_matrix_f2_m_i[9]\, Y => \prdata_39_0_iv_1[9]\); - - \prdata_RNO_10[15]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[15]\, - Y => \addr_matrix_f2_m_i[15]\); - - \prdata_RNO_8[12]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[12]\, Y => \addr_matrix_f0_1_m_i[12]\); - - \prdata[4]\ : DFN1C0 - port map(D => \prdata_39[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => prdata_c(4)); - - \prdata_RNO_6[15]\ : OR3C - port map(A => N_161_0, B => N_168_0, C => - \addr_data_f2[15]\, Y => \addr_data_f2_m_i[15]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_2 is - - port( S_0_18 : in std_logic; - S_0_0 : in std_logic; - S_i : in std_logic_vector(1 to 1); - alu_sel_coeff_0 : in std_logic_vector(2 to 2); - S_25 : in std_logic; - S_7 : in std_logic; - S_6 : in std_logic; - S_15 : in std_logic; - S_20 : in std_logic; - S_11 : in std_logic; - S_17 : in std_logic; - S_10 : in std_logic; - S_9 : in std_logic; - S_13 : in std_logic; - S_26 : in std_logic; - S_16 : in std_logic; - S_19 : in std_logic; - S_0_d0 : in std_logic; - S_33 : in std_logic; - S_12 : in std_logic; - S_8 : in std_logic; - S_22 : in std_logic; - S_2 : in std_logic; - S_23 : in std_logic; - S_5 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 3); - alu_coef_s : out std_logic_vector(8 downto 0) - ); - -end MUXN_9_2; - -architecture DEF_ARCH of MUXN_9_2 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_43, N_19, N_47, N_25, N_48, N_28, N_49, N_50, N_56, - N_40, N_37, N_16, N_55, N_52, N_53, N_44, N_45, N_42, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \NB_STAGE_2.all_input.6.RES_8_1[6]\ : MX2 - port map(A => S_2, B => S_20, S => alu_sel_coeff(4), Y => - N_52); - - \NB_STAGE_2.all_input.7.RES_6_3[7]\ : MX2 - port map(A => N_55, B => N_37, S => alu_sel_coeff(3), Y => - alu_coef_s(7)); - - \NB_STAGE_2.all_input.7.RES_6_2[7]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_10, Y => N_37); - - \NB_STAGE_2.all_input.4.RES_12_1[4]\ : MX2C - port map(A => S_2, B => S_22, S => alu_sel_coeff(4), Y => - N_48); - - \NB_STAGE_2.all_input.0.RES_20_2[0]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_17, Y => N_16); - - \NB_STAGE_2.all_input.2.RES_16_2[2]\ : MX2C - port map(A => S_15, B => S_33, S => alu_sel_coeff(4), Y => - N_45); - - \NB_STAGE_2.all_input.1.RES_18_1[1]\ : MX2C - port map(A => S_7, B => S_25, S => alu_sel_coeff(4), Y => - N_43); - - GND_i_0 : GND - port map(Y => GND_0); - - \NB_STAGE_2.all_input.2.RES_16_3[2]\ : MX2 - port map(A => N_44, B => N_45, S => alu_sel_coeff(3), Y => - alu_coef_s(2)); - - \NB_STAGE_2.all_input.2.RES_16_1[2]\ : MX2 - port map(A => S_6, B => S_11, S => alu_sel_coeff(4), Y => - N_44); - - VCC_i : VCC - port map(Y => \VCC\); - - \NB_STAGE_2.all_input.6.RES_8_2[6]\ : MX2C - port map(A => S_11, B => S_33, S => alu_sel_coeff(4), Y => - N_53); - - \NB_STAGE_2.all_input.3.RES_14_1[3]\ : MX2C - port map(A => S_5, B => S_23, S => alu_sel_coeff(4), Y => - N_47); - - \NB_STAGE_2.all_input.3.RES_14_2[3]\ : OA1C - port map(A => S_26, B => alu_sel_coeff_0(2), C => - alu_sel_coeff(4), Y => N_25); - - GND_i : GND - port map(Y => \GND\); - - \NB_STAGE_2.all_input.3.RES_14_3[3]\ : MX2 - port map(A => N_47, B => N_25, S => alu_sel_coeff(3), Y => - alu_coef_s(3)); - - \NB_STAGE_2.all_input.8.RES_4_3[8]\ : MX2 - port map(A => N_56, B => N_40, S => alu_sel_coeff(3), Y => - alu_coef_s(8)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \NB_STAGE_2.all_input.1.RES_18_3[1]\ : MX2 - port map(A => N_43, B => N_19, S => alu_sel_coeff(3), Y => - alu_coef_s(1)); - - \NB_STAGE_2.all_input.6.RES_8_3[6]\ : MX2 - port map(A => N_52, B => N_53, S => alu_sel_coeff(3), Y => - alu_coef_s(6)); - - \NB_STAGE_2.all_input.8.RES_4_1[8]\ : MX2C - port map(A => S_0_d0, B => S_19, S => alu_sel_coeff(4), Y - => N_56); - - \NB_STAGE_2.all_input.4.RES_12_3[4]\ : MX2 - port map(A => N_48, B => N_28, S => alu_sel_coeff(3), Y => - alu_coef_s(4)); - - \NB_STAGE_2.all_input.4.RES_12_2[4]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_13, Y => N_28); - - \NB_STAGE_2.all_input.0.RES_20_3[0]\ : MX2 - port map(A => N_42, B => N_16, S => alu_sel_coeff(3), Y => - alu_coef_s(0)); - - \NB_STAGE_2.all_input.8.RES_4_2[8]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_9, Y => N_40); - - \NB_STAGE_2.all_input.7.RES_6_1[7]\ : MX2C - port map(A => S_i(1), B => S_19, S => alu_sel_coeff(4), Y - => N_55); - - \NB_STAGE_2.all_input.1.RES_18_2[1]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_16, Y => N_19); - - \NB_STAGE_2.all_input.5.RES_10_1[5]\ : MX2C - port map(A => S_5, B => S_8, S => alu_sel_coeff(4), Y => - N_49); - - \NB_STAGE_2.all_input.5.RES_10_2[5]\ : MX2C - port map(A => S_12, B => S_33, S => alu_sel_coeff(4), Y => - N_50); - - \NB_STAGE_2.all_input.5.RES_10_3[5]\ : MX2 - port map(A => N_49, B => N_50, S => alu_sel_coeff(3), Y => - alu_coef_s(5)); - - \NB_STAGE_2.all_input.0.RES_20_1[0]\ : MX2C - port map(A => S_0_0, B => S_0_18, S => alu_sel_coeff(4), Y - => N_42); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_3 is - - port( alu_coef_s : out std_logic_vector(8 downto 0); - S_0_0 : in std_logic; - S_0_18 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0) - ); - -end MUXN_9_3; - -architecture DEF_ARCH of MUXN_9_3 is - - component MUXN_9_2 - port( S_0_18 : in std_logic := 'U'; - S_0_0 : in std_logic := 'U'; - S_i : in std_logic_vector(1 to 1) := (others => 'U'); - alu_sel_coeff_0 : in std_logic_vector(2 to 2) := (others => 'U'); - S_25 : in std_logic := 'U'; - S_7 : in std_logic := 'U'; - S_6 : in std_logic := 'U'; - S_15 : in std_logic := 'U'; - S_20 : in std_logic := 'U'; - S_11 : in std_logic := 'U'; - S_17 : in std_logic := 'U'; - S_10 : in std_logic := 'U'; - S_9 : in std_logic := 'U'; - S_13 : in std_logic := 'U'; - S_26 : in std_logic := 'U'; - S_16 : in std_logic := 'U'; - S_19 : in std_logic := 'U'; - S_0_d0 : in std_logic := 'U'; - S_33 : in std_logic := 'U'; - S_12 : in std_logic := 'U'; - S_8 : in std_logic := 'U'; - S_22 : in std_logic := 'U'; - S_2 : in std_logic := 'U'; - S_23 : in std_logic := 'U'; - S_5 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 3) := (others => 'U'); - alu_coef_s : out std_logic_vector(8 downto 0) - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO14 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI4 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AO16 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO17 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \S[0]_net_1\, \S[9]_net_1\, \S[13]_net_1\, - \S[16]_net_1\, \S[22]_net_1\, \S[26]_net_1\, \S[33]\, - \S[23]_net_1\, \S_i[1]\, \S[5]\, \S[19]\, \S[12]_net_1\, - \S[2]_net_1\, \S[20]_net_1\, \S[17]_net_1\, \S[10]_net_1\, - \S[25]_net_1\, \S[15]_net_1\, \S[11]_net_1\, \S[8]_net_1\, - \S[7]_net_1\, \S[6]_net_1\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : MUXN_9_2 - Use entity work.MUXN_9_2(DEF_ARCH); -begin - - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_2 - port map(S_0_18 => \S[26]_net_1\, S_0_0 => \S[8]_net_1\, - S_i(1) => \S_i[1]\, alu_sel_coeff_0(2) => - alu_sel_coeff_0_2, S_25 => \S[25]_net_1\, S_7 => - \S[7]_net_1\, S_6 => \S[6]_net_1\, S_15 => \S[15]_net_1\, - S_20 => \S[20]_net_1\, S_11 => \S[11]_net_1\, S_17 => - \S[17]_net_1\, S_10 => \S[10]_net_1\, S_9 => \S[9]_net_1\, - S_13 => \S[13]_net_1\, S_26 => S_0_18, S_16 => - \S[16]_net_1\, S_19 => \S[19]\, S_0_d0 => \S[0]_net_1\, - S_33 => \S[33]\, S_12 => \S[12]_net_1\, S_8 => S_0_0, - S_22 => \S[22]_net_1\, S_2 => \S[2]_net_1\, S_23 => - \S[23]_net_1\, S_5 => \S[5]\, alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0)); - - \S[26]\ : AX1B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[26]_net_1\); - - \S[13]\ : XO1A - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[13]_net_1\); - - \S[3]\ : XA1 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[5]\); - - \S[9]\ : AO14 - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff(1), C - => alu_sel_coeff_0_0, Y => \S[9]_net_1\); - - \S[23]\ : XA1C - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_0, C - => alu_sel_coeff_0_2, Y => \S[23]_net_1\); - - \S[15]\ : AXOI5 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[15]_net_1\); - - \S[11]\ : XAI1 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[11]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \S[8]\ : AXO5 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), C - => alu_sel_coeff(2), Y => \S[8]_net_1\); - - \S[6]\ : AXOI4 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), C - => alu_sel_coeff(2), Y => \S[6]_net_1\); - - \S[25]\ : AXOI3 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[25]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \S[17]\ : AO16 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[17]_net_1\); - - \S[10]\ : AO17 - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(2), C - => alu_sel_coeff(1), Y => \S[10]_net_1\); - - \S[20]\ : OA1A - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(0), C - => alu_sel_coeff(1), Y => \S[20]_net_1\); - - \S[7]\ : AO16 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), C - => alu_sel_coeff(2), Y => \S[7]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \S[18]\ : XAI1A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[19]\); - - \S[0]\ : AXO5 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[0]_net_1\); - - \S[29]\ : OR3 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), C - => alu_sel_coeff_0_2, Y => \S[33]\); - - \S[1]\ : XNOR2 - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff_0_0, Y - => \S_i[1]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \S[12]\ : AO1A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), C - => alu_sel_coeff(2), Y => \S[12]_net_1\); - - \S[22]\ : AXO5 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[22]_net_1\); - - \S[2]\ : NOR3B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[2]_net_1\); - - \S[16]\ : MX2B - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff_0_0, S - => alu_sel_coeff(1), Y => \S[16]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_4 is - - port( alu_coef_s : out std_logic_vector(8 downto 0); - S_0 : out std_logic; - S_i_0 : out std_logic_vector(33 to 33); - alu_sel_coeff : in std_logic_vector(4 downto 0); - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff_0_0 : in std_logic - ); - -end MUXN_9_4; - -architecture DEF_ARCH of MUXN_9_4 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MUXN_9_3 - port( alu_coef_s : out std_logic_vector(8 downto 0); - S_0_0 : in std_logic := 'U'; - S_0_18 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U') - ); - end component; - - signal \S[26]\, \S[8]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : MUXN_9_3 - Use entity work.MUXN_9_3(DEF_ARCH); -begin - - S_0 <= \S[8]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \S[20]\ : OR2B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), Y - => \S[8]\); - - \S[18]\ : XOR2 - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(1), Y - => S_i_0(33)); - - VCC_i : VCC - port map(Y => \VCC\); - - \S[23]\ : NOR2A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), Y - => \S[26]\); - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_3 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), S_0_0 => - \S[8]\, S_0_18 => \S[26]\, alu_sel_coeff_0_0 => - alu_sel_coeff_0_0, alu_sel_coeff_0_2 => alu_sel_coeff_0_2, - alu_sel_coeff(4) => alu_sel_coeff(4), alu_sel_coeff(3) - => alu_sel_coeff(3), alu_sel_coeff(2) => - alu_sel_coeff(2), alu_sel_coeff(1) => alu_sel_coeff(1), - alu_sel_coeff(0) => alu_sel_coeff(0)); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_5 is - - port( alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0); - S_i_0 : out std_logic_vector(33 to 33); - S : out std_logic_vector(8 to 8); - alu_coef_s : out std_logic_vector(8 downto 0) - ); - -end MUXN_9_5; - -architecture DEF_ARCH of MUXN_9_5 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MUXN_9_4 - port( alu_coef_s : out std_logic_vector(8 downto 0); - S_0 : out std_logic; - S_i_0 : out std_logic_vector(33 to 33); - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : MUXN_9_4 - Use entity work.MUXN_9_4(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_4 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), S_0 => - S(8), S_i_0(33) => S_i_0(33), alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_sel_coeff(2) => alu_sel_coeff(2), alu_sel_coeff(1) - => alu_sel_coeff(1), alu_sel_coeff(0) => - alu_sel_coeff(0), alu_sel_coeff_0_2 => alu_sel_coeff_0_2, - alu_sel_coeff_0_0 => alu_sel_coeff_0_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_18 is - - port( alu_sample : in std_logic_vector(17 downto 0); - OP1_2C_D : out std_logic_vector(17 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end MAC_REG_18; - -architecture DEF_ARCH of MAC_REG_18 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[6]\ : DFN1C0 - port map(D => alu_sample(6), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(6)); - - \Q[13]\ : DFN1C0 - port map(D => alu_sample(13), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(13)); - - \Q[14]\ : DFN1C0 - port map(D => alu_sample(14), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(14)); - - \Q[15]\ : DFN1C0 - port map(D => alu_sample(15), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(15)); - - \Q[11]\ : DFN1C0 - port map(D => alu_sample(11), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(11)); - - GND_i_0 : GND - port map(Y => GND_0); - - \Q[2]\ : DFN1C0 - port map(D => alu_sample(2), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(2)); - - \Q[4]\ : DFN1C0 - port map(D => alu_sample(4), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(4)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[17]\ : DFN1C0 - port map(D => alu_sample(17), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(17)); - - \Q[10]\ : DFN1C0 - port map(D => alu_sample(10), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(10)); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[3]\ : DFN1C0 - port map(D => alu_sample(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(3)); - - \Q[7]\ : DFN1C0 - port map(D => alu_sample(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(7)); - - \Q[12]\ : DFN1C0 - port map(D => alu_sample(12), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(12)); - - \Q[8]\ : DFN1C0 - port map(D => alu_sample(8), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(8)); - - \Q[1]\ : DFN1C0 - port map(D => alu_sample(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(1)); - - \Q[0]\ : DFN1C0 - port map(D => alu_sample(0), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(0)); - - \Q[9]\ : DFN1C0 - port map(D => alu_sample(9), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(9)); - - \Q[5]\ : DFN1C0 - port map(D => alu_sample(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(5)); - - \Q[16]\ : DFN1C0 - port map(D => alu_sample(16), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP1_2C_D(16)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_9 is - - port( alu_coef_s : in std_logic_vector(8 downto 0); - OP2_2C_D : out std_logic_vector(8 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end MAC_REG_9; - -architecture DEF_ARCH of MAC_REG_9 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[5]\ : DFN1C0 - port map(D => alu_coef_s(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(5)); - - \Q[3]\ : DFN1C0 - port map(D => alu_coef_s(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(3)); - - \Q[8]\ : DFN1C0 - port map(D => alu_coef_s(8), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(8)); - - \Q[7]\ : DFN1C0 - port map(D => alu_coef_s(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(7)); - - \Q[1]\ : DFN1C0 - port map(D => alu_coef_s(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(1)); - - \Q[2]\ : DFN1C0 - port map(D => alu_coef_s(2), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(2)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[6]\ : DFN1C0 - port map(D => alu_coef_s(6), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(6)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[0]\ : DFN1C0 - port map(D => alu_coef_s(0), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(0)); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \Q[4]\ : DFN1C0 - port map(D => alu_coef_s(4), CLK => HCLK_c, CLR => - HRESETn_c, Q => OP2_2C_D(4)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_4 is - - port( MACMUX2sel_D : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - MACMUX2sel_D_D : out std_logic - ); - -end MAC_REG_1_4; - -architecture DEF_ARCH of MAC_REG_1_4 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[0]\ : DFN1C0 - port map(D => MACMUX2sel_D, CLK => HCLK_c, CLR => HRESETn_c, - Q => MACMUX2sel_D_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_CONTROLER is - - port( alu_ctrl : in std_logic_vector(1 downto 0); - MACMUX2sel : out std_logic; - N_4 : out std_logic; - mult : out std_logic; - mult_0 : out std_logic - ); - -end MAC_CONTROLER; - -architecture DEF_ARCH of MAC_CONTROLER is - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_mult_i : NOR2B - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => N_4); - - GND_i_0 : GND - port map(Y => GND_0); - - un2_mult_i_x2 : XOR2 - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => mult); - - VCC_i : VCC - port map(Y => \VCC\); - - un2_mult_i_x2_0 : XOR2 - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => mult_0); - - un1_add_0_a2 : NOR2A - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => - MACMUX2sel); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_MUX is - - port( OP1_2C_D : in std_logic_vector(17 downto 0); - MULTout : in std_logic_vector(24 downto 0); - ADDERinB : out std_logic_vector(24 downto 0); - ADDERinA_i : out std_logic_vector(18 to 18); - OP2_2C_D : in std_logic_vector(8 downto 0); - ADDERout : in std_logic_vector(24 downto 0); - ADDERinA_17 : out std_logic; - ADDERinA_24 : out std_logic; - ADDERinA_23 : out std_logic; - ADDERinA_22 : out std_logic; - ADDERinA_21 : out std_logic; - ADDERinA_20 : out std_logic; - ADDERinA_19 : out std_logic; - ADDERinA_16 : out std_logic; - ADDERinA_15 : out std_logic; - ADDERinA_14 : out std_logic; - ADDERinA_13 : out std_logic; - ADDERinA_12 : out std_logic; - ADDERinA_11 : out std_logic; - ADDERinA_10 : out std_logic; - ADDERinA_9 : out std_logic; - ADDERinA_8 : out std_logic; - ADDERinA_7 : out std_logic; - ADDERinA_6 : out std_logic; - ADDERinA_5 : out std_logic; - ADDERinA_4 : out std_logic; - ADDERinA_3 : out std_logic; - ADDERinA_2 : out std_logic; - ADDERinA_1 : out std_logic; - ADDERinA_0 : out std_logic; - MACMUXsel_D : in std_logic; - MACMUXsel_D_1 : in std_logic; - MACMUXsel_D_0 : in std_logic - ); - -end MAC_MUX; - -architecture DEF_ARCH of MAC_MUX is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \OUTA[24]\ : MX2C - port map(A => ADDERout(24), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_24); - - \OUTB[3]\ : MX2 - port map(A => MULTout(3), B => OP1_2C_D(3), S => - MACMUXsel_D_1, Y => ADDERinB(3)); - - \OUTB[9]\ : MX2 - port map(A => MULTout(9), B => OP1_2C_D(9), S => - MACMUXsel_D_1, Y => ADDERinB(9)); - - \OUTA[0]\ : MX2 - port map(A => ADDERout(0), B => OP2_2C_D(0), S => - MACMUXsel_D_0, Y => ADDERinA_0); - - \OUTA[3]\ : MX2 - port map(A => ADDERout(3), B => OP2_2C_D(3), S => - MACMUXsel_D_0, Y => ADDERinA_3); - - \OUTB[11]\ : MX2 - port map(A => MULTout(11), B => OP1_2C_D(11), S => - MACMUXsel_D, Y => ADDERinB(11)); - - \OUTB[23]\ : MX2 - port map(A => MULTout(23), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(23)); - - \OUTB[12]\ : MX2 - port map(A => MULTout(12), B => OP1_2C_D(12), S => - MACMUXsel_D, Y => ADDERinB(12)); - - \OUTB[20]\ : MX2 - port map(A => MULTout(20), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(20)); - - \OUTB[19]\ : MX2 - port map(A => MULTout(19), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(19)); - - \OUTA[13]\ : MX2 - port map(A => ADDERout(13), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_13); - - \OUTB[8]\ : MX2 - port map(A => MULTout(8), B => OP1_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinB(8)); - - \OUTA[10]\ : MX2 - port map(A => ADDERout(10), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_10); - - VCC_i : VCC - port map(Y => \VCC\); - - \OUTB[6]\ : MX2 - port map(A => MULTout(6), B => OP1_2C_D(6), S => - MACMUXsel_D_1, Y => ADDERinB(6)); - - \OUTA[6]\ : MX2 - port map(A => ADDERout(6), B => OP2_2C_D(6), S => - MACMUXsel_D_0, Y => ADDERinA_6); - - \OUTB[24]\ : MX2 - port map(A => MULTout(24), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(24)); - - \OUTA[14]\ : MX2C - port map(A => ADDERout(14), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_14); - - \OUTB[2]\ : MX2 - port map(A => MULTout(2), B => OP1_2C_D(2), S => - MACMUXsel_D_1, Y => ADDERinB(2)); - - \OUTB[13]\ : MX2 - port map(A => MULTout(13), B => OP1_2C_D(13), S => - MACMUXsel_D, Y => ADDERinB(13)); - - \OUTB[10]\ : MX2 - port map(A => MULTout(10), B => OP1_2C_D(10), S => - MACMUXsel_D, Y => ADDERinB(10)); - - \OUTA[9]\ : MX2 - port map(A => ADDERout(9), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_9); - - \OUTA[15]\ : MX2C - port map(A => ADDERout(15), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_15); - - \OUTA[16]\ : MX2 - port map(A => ADDERout(16), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_16); - - \OUTA[7]\ : MX2 - port map(A => ADDERout(7), B => OP2_2C_D(7), S => - MACMUXsel_D_0, Y => ADDERinA_7); - - \OUTB[5]\ : MX2 - port map(A => MULTout(5), B => OP1_2C_D(5), S => - MACMUXsel_D_1, Y => ADDERinB(5)); - - \OUTB[14]\ : MX2 - port map(A => MULTout(14), B => OP1_2C_D(14), S => - MACMUXsel_D, Y => ADDERinB(14)); - - GND_i : GND - port map(Y => \GND\); - - \OUTA[18]\ : MX2C - port map(A => ADDERout(18), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_i(18)); - - \OUTB[4]\ : MX2 - port map(A => MULTout(4), B => OP1_2C_D(4), S => - MACMUXsel_D_1, Y => ADDERinB(4)); - - \OUTB[15]\ : MX2 - port map(A => MULTout(15), B => OP1_2C_D(15), S => - MACMUXsel_D, Y => ADDERinB(15)); - - \OUTB[16]\ : MX2 - port map(A => MULTout(16), B => OP1_2C_D(16), S => - MACMUXsel_D, Y => ADDERinB(16)); - - \OUTA[21]\ : MX2 - port map(A => ADDERout(21), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_21); - - \OUTA[22]\ : MX2C - port map(A => ADDERout(22), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_22); - - \OUTA[17]\ : MX2 - port map(A => ADDERout(17), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA_17); - - \OUTB[18]\ : MX2 - port map(A => MULTout(18), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(18)); - - \OUTA[4]\ : MX2 - port map(A => ADDERout(4), B => OP2_2C_D(4), S => - MACMUXsel_D_0, Y => ADDERinA_4); - - \OUTA[1]\ : MX2C - port map(A => ADDERout(1), B => OP2_2C_D(1), S => - MACMUXsel_D_0, Y => ADDERinA_1); - - \OUTB[7]\ : MX2 - port map(A => MULTout(7), B => OP1_2C_D(7), S => - MACMUXsel_D_1, Y => ADDERinB(7)); - - \OUTA[2]\ : MX2 - port map(A => ADDERout(2), B => OP2_2C_D(2), S => - MACMUXsel_D_0, Y => ADDERinA_2); - - \OUTA[23]\ : MX2 - port map(A => ADDERout(23), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_23); - - \OUTA[20]\ : MX2 - port map(A => ADDERout(20), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_20); - - \OUTB[17]\ : MX2 - port map(A => MULTout(17), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(17)); - - \OUTB[21]\ : MX2 - port map(A => MULTout(21), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(21)); - - \OUTA[8]\ : MX2 - port map(A => ADDERout(8), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_8); - - \OUTB[22]\ : MX2 - port map(A => MULTout(22), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(22)); - - \OUTB[0]\ : MX2 - port map(A => MULTout(0), B => OP1_2C_D(0), S => - MACMUXsel_D_1, Y => ADDERinB(0)); - - \OUTA[11]\ : MX2 - port map(A => ADDERout(11), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_11); - - \OUTB[1]\ : MX2 - port map(A => MULTout(1), B => OP1_2C_D(1), S => - MACMUXsel_D_1, Y => ADDERinB(1)); - - \OUTA[5]\ : MX2 - port map(A => ADDERout(5), B => OP2_2C_D(5), S => - MACMUXsel_D_0, Y => ADDERinA_5); - - \OUTA[12]\ : MX2 - port map(A => ADDERout(12), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \OUTA[19]\ : MX2 - port map(A => ADDERout(19), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA_19); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_27 is - - port( MULTout : in std_logic_vector(24 downto 7); - MULTout_D : out std_logic_vector(24 downto 7); - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end MAC_REG_27; - -architecture DEF_ARCH of MAC_REG_27 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[24]\ : DFN1C0 - port map(D => MULTout(24), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(24)); - - \Q[21]\ : DFN1C0 - port map(D => MULTout(21), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(21)); - - \Q[13]\ : DFN1C0 - port map(D => MULTout(13), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(13)); - - \Q[14]\ : DFN1C0 - port map(D => MULTout(14), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(14)); - - \Q[15]\ : DFN1C0 - port map(D => MULTout(15), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(15)); - - \Q[11]\ : DFN1C0 - port map(D => MULTout(11), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(11)); - - GND_i_0 : GND - port map(Y => GND_0); - - \Q[20]\ : DFN1C0 - port map(D => MULTout(20), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(20)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[17]\ : DFN1C0 - port map(D => MULTout(17), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(17)); - - \Q[10]\ : DFN1C0 - port map(D => MULTout(10), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(10)); - - \Q[19]\ : DFN1C0 - port map(D => MULTout(19), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(19)); - - GND_i : GND - port map(Y => \GND\); - - \Q[18]\ : DFN1C0 - port map(D => MULTout(18), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(18)); - - \Q[22]\ : DFN1C0 - port map(D => MULTout(22), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(22)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[7]\ : DFN1C0 - port map(D => MULTout(7), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(7)); - - \Q[12]\ : DFN1C0 - port map(D => MULTout(12), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(12)); - - \Q[8]\ : DFN1C0 - port map(D => MULTout(8), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(8)); - - \Q[9]\ : DFN1C0 - port map(D => MULTout(9), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(9)); - - \Q[23]\ : DFN1C0 - port map(D => MULTout(23), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(23)); - - \Q[16]\ : DFN1C0 - port map(D => MULTout(16), CLK => HCLK_c, CLR => HRESETn_c, - Q => MULTout_D(16)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_1 is - - port( alu_ctrl : in std_logic_vector(0 to 0); - add_D : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - add_D_0 : out std_logic - ); - -end MAC_REG_1_1; - -architecture DEF_ARCH of MAC_REG_1_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_0[0]\ : DFN1C0 - port map(D => alu_ctrl(0), CLK => HCLK_c, CLR => HRESETn_c, - Q => add_D_0); - - \Q[0]\ : DFN1C0 - port map(D => alu_ctrl(0), CLK => HCLK_c, CLR => HRESETn_c, - Q => add_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_3 is - - port( MACMUX2sel : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - MACMUX2sel_D : out std_logic - ); - -end MAC_REG_1_3; - -architecture DEF_ARCH of MAC_REG_1_3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[0]\ : DFN1C0 - port map(D => MACMUX2sel, CLK => HCLK_c, CLR => HRESETn_c, - Q => MACMUX2sel_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1 is - - port( alu_ctrl : in std_logic_vector(2 to 2); - clr_MAC_D : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - clr_MAC_D_0 : out std_logic - ); - -end MAC_REG_1; - -architecture DEF_ARCH of MAC_REG_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_0[0]\ : DFN1C0 - port map(D => alu_ctrl(2), CLK => HCLK_c, CLR => HRESETn_c, - Q => clr_MAC_D_0); - - \Q[0]\ : DFN1C0 - port map(D => alu_ctrl(2), CLK => HCLK_c, CLR => HRESETn_c, - Q => clr_MAC_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Adder is - - port( ADDERout : out std_logic_vector(24 downto 0); - ADDERinA_i : in std_logic_vector(18 to 18); - ADDERinB : in std_logic_vector(24 downto 0); - ADDERinA_0 : in std_logic; - ADDERinA_1 : in std_logic; - ADDERinA_3 : in std_logic; - ADDERinA_5 : in std_logic; - ADDERinA_7 : in std_logic; - ADDERinA_8 : in std_logic; - ADDERinA_15 : in std_logic; - ADDERinA_16 : in std_logic; - ADDERinA_2 : in std_logic; - ADDERinA_14 : in std_logic; - ADDERinA_6 : in std_logic; - ADDERinA_10 : in std_logic; - ADDERinA_4 : in std_logic; - ADDERinA_12 : in std_logic; - ADDERinA_20 : in std_logic; - ADDERinA_11 : in std_logic; - ADDERinA_19 : in std_logic; - ADDERinA_9 : in std_logic; - ADDERinA_13 : in std_logic; - ADDERinA_21 : in std_logic; - ADDERinA_22 : in std_logic; - ADDERinA_24 : in std_logic; - ADDERinA_23 : in std_logic; - ADDERinA_17 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - clr_MAC_D : in std_logic; - add_D : in std_logic; - clr_MAC_D_0 : in std_logic; - MACMUX2sel_D : in std_logic; - add_D_0 : in std_logic - ); - -end Adder; - -architecture DEF_ARCH of Adder is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_clr_1_0\, ADD_27x27_fast_I247_Y_0_0, - ADD_27x27_fast_I253_Y_0_0, ADD_27x27_fast_I254_Y_0_0, - ADD_27x27_fast_I208_Y_3, N534, N519, - ADD_27x27_fast_I208_Y_2, N472, N465, - ADD_27x27_fast_I208_Y_1, N415, N412, - ADD_27x27_fast_I208_Y_0, N388, ADD_27x27_fast_I251_Y_0_0, - ADD_27x27_fast_I207_Y_3, N532, N517, - ADD_27x27_fast_I207_Y_2, N470, N463, - ADD_27x27_fast_I207_Y_1, N413, N410, - ADD_27x27_fast_I207_Y_0, N391, ADD_27x27_fast_I243_Y_0_0, - ADD_27x27_fast_I239_Y_0_0, ADD_27x27_fast_I249_Y_0_0, - ADD_27x27_fast_I196_Y_0_0, N496, N_73, N439, - ADD_27x27_fast_I241_Y_0_0, ADD_27x27_fast_I250_Y_0_0, - ADD_27x27_fast_I242_Y_0_0, ADD_27x27_fast_I252_Y_0_0, - ADD_27x27_fast_I212_Y_1, N542, N527, - ADD_27x27_fast_I212_Y_0, N480, N473, - ADD_27x27_fast_I164_Y_i_0, N_58, - ADD_27x27_fast_I248_Y_0_0, ADD_27x27_fast_I211_Y_1, N540, - N525, ADD_27x27_fast_I211_Y_0, N478, N471, - ADD_27x27_fast_I209_Y_2, N536, N521, - ADD_27x27_fast_I209_Y_1, N474, N467, - ADD_27x27_fast_I209_Y_0, N417, N414, - ADD_27x27_fast_I240_Y_0_0, ADD_27x27_fast_I213_Y_1, - ADD_27x27_fast_I213_un1_Y_0, N529, - ADD_27x27_fast_I213_Y_0, N475, N482, - ADD_27x27_fast_I236_Y_0_0, N499, N_47, N491, - ADD_27x27_fast_I99_Y_0, N364, ADD_27x27_fast_I91_Y_0, - N376, ADD_27x27_fast_I107_Y_0, N352, - ADD_27x27_fast_I115_Y_0, N340, - ADD_27x27_fast_I115_un1_Y_0, N_108, - ADD_27x27_fast_I116_Y_0, ADD_27x27_fast_I100_Y_0, N362, - I207_un1_Y, N533, N548, I209_un1_Y, N537, N552, - I211_un1_Y, N541, N502, N431, N428, N481, N488, N436, - N444, N497, I208_un1_Y, N535, N550, I212_un1_Y, N543, - N_48, N_33, \un1_clr_1\, \un2_resadd[24]\, - \un2_resadd[23]\, \un2_resadd[22]\, \un2_resadd[21]\, - ADD_27x27_fast_I210_Y_0_a2, \un2_resadd[20]\, - \un2_resadd[19]\, \un2_resadd[18]\, I185_un1_Y, - \un2_resadd[16]\, N648_i, \un2_resadd[15]\, N651, - \un2_resadd[14]\, N654_i, \un2_resadd[13]\, - ADD_27x27_fast_I192_Y_0_a2, N361, \un2_resadd[12]\, - I193_un1_Y, \un2_resadd[11]\, I194_un1_Y_i, - \un2_resadd[10]\, N544, I195_un1_Y_i, \un2_resadd[9]\, - N_78_i, \un2_resadd[8]\, \un2_resadd[7]\, \un2_resadd[6]\, - \un2_resadd[5]\, \un2_resadd[4]\, \un2_resadd[3]\, - \un2_resadd[2]\, \un2_resadd[1]\, N325, \un2_resadd[17]\, - N423, N_98_i, N420, N392, N355, N356, N379, N380, N385, - N386, N429, N437, N349, N441, N343, N445, N_52_i_0, N449, - N_72, N450, N418, N433, N430, N483, N434, N490, N438, - N442, N494, N498, N446, N487, N479, N495, I163_un1_Y, - N383, N350, N344, N341, N486, N346, N382, N367, N368, - N_105_1, N489, I190_un1_Y, N_59, N_50, N_9, N_11, N_16, - N_18, N_23, N_30, N_32, \REG_4[1]\, \REG_4[3]\, - \REG_4[8]\, \REG_4[10]\, \REG_4[15]\, \REG_4[22]\, - \REG_4[24]\, N_8, N_12, N_15, N_19, N_22, N_26, N_29, - \REG_4[0]\, \REG_4[4]\, \REG_4[7]\, \REG_4[11]\, - \REG_4[14]\, \REG_4[18]\, \REG_4[21]\, N_10, N_13, N_14, - N_17, N_20, N_21, N_24, N_27, N_28, N_31, \REG_4[2]\, - \REG_4[5]\, \REG_4[6]\, \REG_4[9]\, \REG_4[12]\, - \REG_4[13]\, \REG_4[16]\, \REG_4[19]\, \REG_4[20]\, - \REG_4[23]\, N_23_0, \REG_4[17]\, N_25, N374, N370, N373, - N371, N426, N422, N421, N425, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - un2_resadd_ADD_27x27_fast_I8_G0N : NOR2B - port map(A => ADDERinB(8), B => ADDERinA_8, Y => N349); - - un2_resadd_ADD_27x27_fast_I241_Y_0_0 : XOR2 - port map(A => ADDERinA_11, B => ADDERinB(11), Y => - ADD_27x27_fast_I241_Y_0_0); - - un2_resadd_ADD_27x27_fast_I134_Y : NOR2 - port map(A => N475, B => N467, Y => N521); - - un2_resadd_ADD_27x27_fast_I208_Y_1 : AOI1B - port map(A => N415, B => N412, C => ADD_27x27_fast_I208_Y_0, - Y => ADD_27x27_fast_I208_Y_1); - - un2_resadd_ADD_27x27_fast_I156_Y : NOR2A - port map(A => N497, B => N489, Y => N543); - - un2_resadd_ADD_27x27_fast_I19_P0N : OR2 - port map(A => ADDERinB(19), B => ADDERinA_19, Y => N383); - - un2_resadd_ADD_27x27_fast_I21_G0N : NOR2B - port map(A => ADDERinB(21), B => ADDERinA_21, Y => N388); - - \REG[14]\ : DFN1E0C0 - port map(D => \REG_4[14]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(14)); - - un2_resadd_ADD_27x27_fast_I214_Y_0_a2 : OR2A - port map(A => N651, B => N_23_0, Y => N_98_i); - - un2_resadd_ADD_27x27_fast_I12_G0N : OR2B - port map(A => ADDERinB(12), B => ADDERinA_12, Y => N361); - - un2_resadd_ADD_27x27_fast_I99_Y : AOI1 - port map(A => N431, B => N428, C => ADD_27x27_fast_I99_Y_0, - Y => N480); - - un2_resadd_ADD_27x27_fast_I149_Y : AO1A - port map(A => N483, B => N490, C => N482, Y => N536); - - un2_resadd_ADD_27x27_fast_I68_Y : OA1 - port map(A => ADDERinA_4, B => ADDERinB(4), C => N341, Y - => N446); - - un2_resadd_ADD_27x27_fast_I5_P0N : OR2 - port map(A => ADDERinB(5), B => ADDERinA_5, Y => N341); - - un2_resadd_ADD_27x27_fast_I11_G0N_0_o2 : OR2B - port map(A => ADDERinB(11), B => ADDERinA_11, Y => N_50); - - un2_resadd_ADD_27x27_fast_I209_Y_0 : AOI1 - port map(A => N417, B => N414, C => N413, Y => - ADD_27x27_fast_I209_Y_0); - - un2_resadd_ADD_27x27_fast_I132_Y : NOR2 - port map(A => N473, B => N465, Y => N519); - - un2_resadd_ADD_27x27_fast_I122_Y_i_o2 : MAJ3 - port map(A => ADDERinA_2, B => ADDERinB(2), C => N_47, Y - => N_48); - - un2_resadd_ADD_27x27_fast_I93_Y : AO1 - port map(A => N425, B => N422, C => N421, Y => N474); - - un2_resadd_ADD_27x27_fast_I52_Y : OA1 - port map(A => ADDERinA_13, B => ADDERinB(13), C => N362, Y - => N430); - - un2_resadd_ADD_27x27_fast_I254_Y_0 : AX1C - port map(A => I207_un1_Y, B => ADD_27x27_fast_I207_Y_3, C - => ADD_27x27_fast_I254_Y_0_0, Y => \un2_resadd[24]\); - - \REG_RNO[11]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_19, Y => \REG_4[11]\); - - \REG[22]\ : DFN1E0C0 - port map(D => \REG_4[22]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(22)); - - un2_resadd_ADD_27x27_fast_I51_Y : AO13 - port map(A => ADDERinB(13), B => ADDERinA_13, C => N361, Y - => N429); - - \REG_RNO[20]\ : NOR2 - port map(A => clr_MAC_D, B => N_28, Y => \REG_4[20]\); - - \REG_RNO[15]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_23, Y => \REG_4[15]\); - - \REG_RNO_0[17]\ : MX2C - port map(A => ADDERinB(17), B => \un2_resadd[17]\, S => - add_D, Y => N_25); - - un2_resadd_ADD_27x27_fast_I196_Y_0_a2 : OR3B - port map(A => N497, B => N_48, C => N_73, Y => N_78_i); - - un2_resadd_ADD_27x27_fast_I240_Y_0_0 : XOR2 - port map(A => ADDERinA_10, B => ADDERinB(10), Y => - ADD_27x27_fast_I240_Y_0_0); - - un2_resadd_ADD_27x27_fast_I6_G0N : NOR2B - port map(A => ADDERinB(6), B => ADDERinA_6, Y => N343); - - un2_resadd_ADD_27x27_fast_I163_Y : OR2 - port map(A => N498, B => I163_un1_Y, Y => N552); - - un2_resadd_ADD_27x27_fast_I90_Y : OR2B - port map(A => N422, B => N418, Y => N471); - - un2_resadd_ADD_27x27_fast_I35_Y : MAJ3 - port map(A => ADDERinA_21, B => ADDERinB(21), C => N385, Y - => N413); - - un2_resadd_ADD_27x27_fast_I48_Y : NOR2B - port map(A => N371, B => N368, Y => N426); - - \REG_RNO[9]\ : NOR2 - port map(A => clr_MAC_D, B => N_17, Y => \REG_4[9]\); - - \REG_RNO_0[8]\ : MX2C - port map(A => ADDERinB(8), B => \un2_resadd[8]\, S => - add_D_0, Y => N_16); - - \REG[11]\ : DFN1E0C0 - port map(D => \REG_4[11]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(11)); - - un2_resadd_ADD_27x27_fast_I99_Y_0 : AO18 - port map(A => N364, B => ADDERinB(14), C => ADDERinA_14, Y - => ADD_27x27_fast_I99_Y_0); - - un2_resadd_ADD_27x27_fast_I6_P0N : OR2 - port map(A => ADDERinB(6), B => ADDERinA_6, Y => N344); - - un2_resadd_ADD_27x27_fast_I15_G0N : NOR2A - port map(A => ADDERinB(15), B => ADDERinA_15, Y => N370); - - un2_resadd_ADD_27x27_fast_I207_Y_1 : AOI1B - port map(A => N413, B => N410, C => ADD_27x27_fast_I207_Y_0, - Y => ADD_27x27_fast_I207_Y_1); - - un2_resadd_ADD_27x27_fast_I207_Y_0 : MIN3 - port map(A => ADDERinA_23, B => ADDERinB(23), C => N391, Y - => ADD_27x27_fast_I207_Y_0); - - un2_resadd_ADD_27x27_fast_I116_Y : NOR2B - port map(A => ADD_27x27_fast_I116_Y_0, B => N444, Y => N497); - - un2_resadd_ADD_27x27_fast_I242_Y_0_0 : XOR2 - port map(A => ADDERinA_12, B => ADDERinB(12), Y => - ADD_27x27_fast_I242_Y_0_0); - - un2_resadd_ADD_27x27_fast_I163_un1_Y : NOR2B - port map(A => N_47, B => N499, Y => I163_un1_Y); - - un2_resadd_ADD_27x27_fast_I238_Y_0 : XOR3 - port map(A => ADDERinB(8), B => ADDERinA_8, C => N548, Y - => \un2_resadd[8]\); - - \REG_RNO[4]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_12, Y => \REG_4[4]\); - - \REG_RNO[12]\ : NOR2 - port map(A => clr_MAC_D, B => N_20, Y => \REG_4[12]\); - - un2_resadd_ADD_27x27_fast_I140_Y : NOR2 - port map(A => N481, B => N473, Y => N527); - - un2_resadd_ADD_27x27_fast_I248_Y_0 : AX1B - port map(A => I185_un1_Y, B => ADD_27x27_fast_I213_Y_1, C - => ADD_27x27_fast_I248_Y_0_0, Y => \un2_resadd[18]\); - - \REG_RNO_0[11]\ : MX2C - port map(A => ADDERinB(11), B => \un2_resadd[11]\, S => - add_D_0, Y => N_19); - - un2_resadd_ADD_27x27_fast_I66_Y : NOR2B - port map(A => N344, B => N341, Y => N444); - - un2_resadd_ADD_27x27_fast_I247_Y_0_0 : XOR2 - port map(A => ADDERinA_17, B => ADDERinB(17), Y => - ADD_27x27_fast_I247_Y_0_0); - - un2_resadd_ADD_27x27_fast_I162_Y : AO1 - port map(A => N_48, B => N497, C => N496, Y => N550); - - un2_resadd_ADD_27x27_fast_I36_Y : OA1 - port map(A => ADDERinA_21, B => ADDERinB(21), C => N386, Y - => N414); - - un2_resadd_ADD_27x27_fast_I209_Y_2 : AOI1B - port map(A => N536, B => N521, C => ADD_27x27_fast_I209_Y_1, - Y => ADD_27x27_fast_I209_Y_2); - - un2_resadd_ADD_27x27_fast_I236_Y_0_0 : XOR2 - port map(A => ADDERinA_6, B => ADDERinB(6), Y => - ADD_27x27_fast_I236_Y_0_0); - - un2_resadd_ADD_27x27_fast_I212_Y_1 : AO1 - port map(A => N542, B => N527, C => ADD_27x27_fast_I212_Y_0, - Y => ADD_27x27_fast_I212_Y_1); - - un2_resadd_ADD_27x27_fast_I19_G0N : NOR2B - port map(A => ADDERinB(19), B => ADDERinA_19, Y => N382); - - \REG_RNO_0[10]\ : MX2C - port map(A => ADDERinB(10), B => \un2_resadd[10]\, S => - add_D_0, Y => N_18); - - \REG[12]\ : DFN1E0C0 - port map(D => \REG_4[12]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(12)); - - un2_resadd_ADD_27x27_fast_I84_Y : OR2B - port map(A => N_105_1, B => N412, Y => N465); - - un2_resadd_ADD_27x27_fast_I107_Y_0 : MIN3 - port map(A => ADDERinA_10, B => ADDERinB(10), C => N352, Y - => ADD_27x27_fast_I107_Y_0); - - un2_resadd_ADD_27x27_fast_I185_un1_Y : NOR2B - port map(A => N544, B => N529, Y => I185_un1_Y); - - un2_resadd_ADD_27x27_fast_I115_un1_Y_0 : OA1B - port map(A => ADDERinA_4, B => ADDERinB(4), C => N_108, Y - => ADD_27x27_fast_I115_un1_Y_0); - - un2_resadd_ADD_27x27_fast_I207_Y_2 : OA1A - port map(A => N470, B => N463, C => ADD_27x27_fast_I207_Y_1, - Y => ADD_27x27_fast_I207_Y_2); - - un2_resadd_ADD_27x27_fast_I118_Y : NOR2B - port map(A => N450, B => N446, Y => N499); - - un2_resadd_ADD_27x27_fast_I207_Y_3 : AOI1B - port map(A => N532, B => N517, C => ADD_27x27_fast_I207_Y_2, - Y => ADD_27x27_fast_I207_Y_3); - - GND_i : GND - port map(Y => \GND\); - - \REG_RNO_0[21]\ : MX2C - port map(A => ADDERinB(21), B => \un2_resadd[21]\, S => - add_D, Y => N_29); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un2_resadd_ADD_27x27_fast_I63_Y : MAJ3 - port map(A => ADDERinA_7, B => ADDERinB(7), C => N343, Y - => N441); - - un2_resadd_ADD_27x27_fast_I236_Y_0 : XOR2 - port map(A => ADD_27x27_fast_I236_Y_0_0, B => N552, Y => - \un2_resadd[6]\); - - un2_resadd_ADD_27x27_fast_I45_Y_0_o2 : AO1 - port map(A => N374, B => N370, C => N373, Y => N423); - - un2_resadd_ADD_27x27_fast_I10_G0N : NOR2B - port map(A => ADDERinB(10), B => ADDERinA_10, Y => N355); - - un2_resadd_ADD_27x27_fast_I246_Y_0 : XNOR3 - port map(A => ADDERinB(16), B => ADDERinA_16, C => N648_i, - Y => \un2_resadd[16]\); - - \REG_RNO[14]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_22, Y => \REG_4[14]\); - - un2_resadd_ADD_27x27_fast_I92_Y : OR2A - port map(A => N420, B => N_23_0, Y => N473); - - un2_resadd_ADD_27x27_fast_I39_Y : MAJ3 - port map(A => ADDERinA_19, B => ADDERinB(19), C => N379, Y - => N417); - - un2_resadd_ADD_27x27_fast_I150_Y : NOR2 - port map(A => N491, B => N483, Y => N537); - - un2_resadd_ADD_27x27_fast_I235_Y_0 : XNOR3 - port map(A => ADDERinB(5), B => ADDERinA_5, C => N_33, Y - => \un2_resadd[5]\); - - un2_resadd_ADD_27x27_fast_I164_Y_i_0 : MAJ3 - port map(A => ADDERinA_4, B => ADDERinB(4), C => N_58, Y - => ADD_27x27_fast_I164_Y_i_0); - - un2_resadd_ADD_27x27_fast_I212_Y_0 : AO1D - port map(A => N480, B => N473, C => N472, Y => - ADD_27x27_fast_I212_Y_0); - - un2_resadd_ADD_27x27_fast_I196_Y_0_0 : OA1C - port map(A => N496, B => N_73, C => N439, Y => - ADD_27x27_fast_I196_Y_0_0); - - un2_resadd_ADD_27x27_fast_I245_Y_0 : XNOR3 - port map(A => ADDERinB(15), B => ADDERinA_15, C => N651, Y - => \un2_resadd[15]\); - - \REG[0]\ : DFN1E0C0 - port map(D => \REG_4[0]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(0)); - - \REG_RNO[7]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_15, Y => \REG_4[7]\); - - un2_resadd_ADD_27x27_fast_I9_G0N : NOR2B - port map(A => ADDERinB(9), B => ADDERinA_9, Y => N352); - - un2_resadd_ADD_27x27_fast_I91_Y : AO1 - port map(A => N423, B => N420, C => ADD_27x27_fast_I91_Y_0, - Y => N472); - - \REG_RNO_0[20]\ : MX2C - port map(A => ADDERinB(20), B => \un2_resadd[20]\, S => - add_D, Y => N_28); - - un2_resadd_ADD_27x27_fast_I212_un1_Y : NOR3C - port map(A => N543, B => N527, C => N_48, Y => I212_un1_Y); - - un2_resadd_ADD_27x27_fast_I106_Y : OR2B - port map(A => N438, B => N434, Y => N487); - - un2_resadd_ADD_27x27_fast_I3_G0N_i_o2 : NOR2B - port map(A => ADDERinB(3), B => ADDERinA_3, Y => N_59); - - un2_resadd_ADD_27x27_fast_I60_Y : OA1 - port map(A => ADDERinA_9, B => ADDERinB(9), C => N350, Y - => N438); - - \REG[23]\ : DFN1E0C0 - port map(D => \REG_4[23]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(23)); - - un2_resadd_ADD_27x27_fast_I208_Y_0 : AO18 - port map(A => N388, B => ADDERinA_22, C => ADDERinB(22), Y - => ADD_27x27_fast_I208_Y_0); - - \REG_RNO[1]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_9, Y => \REG_4[1]\); - - un2_resadd_ADD_27x27_fast_I43_Y : MAJ3 - port map(A => ADDERinA_17, B => ADDERinB(17), C => N373, Y - => N421); - - un2_resadd_ADD_27x27_fast_I190_un1_Y : NOR2B - port map(A => N550, B => N535, Y => I190_un1_Y); - - un2_resadd_ADD_27x27_fast_I20_P0N : OR2 - port map(A => ADDERinB(20), B => ADDERinA_20, Y => N386); - - un2_resadd_ADD_27x27_fast_I208_Y_2 : OA1A - port map(A => N472, B => N465, C => ADD_27x27_fast_I208_Y_1, - Y => ADD_27x27_fast_I208_Y_2); - - un2_resadd_ADD_27x27_fast_I101_Y : AO1 - port map(A => N433, B => N430, C => N429, Y => N482); - - \REG_RNO[21]\ : NOR2 - port map(A => clr_MAC_D, B => N_29, Y => \REG_4[21]\); - - un2_resadd_ADD_27x27_fast_I16_G0N : NOR2B - port map(A => ADDERinB(16), B => ADDERinA_16, Y => N373); - - VCC_i : VCC - port map(Y => \VCC\); - - un2_resadd_ADD_27x27_fast_I91_Y_0 : AO13 - port map(A => N376, B => ADDERinB(18), C => ADDERinA_i(18), - Y => ADD_27x27_fast_I91_Y_0); - - un2_resadd_ADD_27x27_fast_I211_Y_0 : OA1C - port map(A => N478, B => N471, C => N470, Y => - ADD_27x27_fast_I211_Y_0); - - un2_resadd_ADD_27x27_fast_I97_Y : AO1 - port map(A => N429, B => N426, C => N425, Y => N478); - - un2_resadd_ADD_27x27_fast_I40_Y : NOR2B - port map(A => N383, B => N380, Y => N418); - - un2_resadd_ADD_27x27_fast_I2_G0N_i_o2 : OR2B - port map(A => ADDERinB(2), B => ADDERinA_2, Y => N_72); - - \REG_RNO[13]\ : NOR2 - port map(A => clr_MAC_D, B => N_21, Y => \REG_4[13]\); - - un2_resadd_ADD_27x27_fast_I145_Y : AO1A - port map(A => N479, B => N486, C => N478, Y => N532); - - un2_resadd_ADD_27x27_fast_I108_Y : OR2A - port map(A => N436, B => N_73, Y => N489); - - \REG_RNO_0[19]\ : MX2C - port map(A => ADDERinB(19), B => \un2_resadd[19]\, S => - add_D, Y => N_27); - - un2_resadd_ADD_27x27_fast_I110_Y : OR2B - port map(A => N442, B => N438, Y => N491); - - \REG_RNO_0[6]\ : MX2C - port map(A => ADDERinB(6), B => \un2_resadd[6]\, S => add_D, - Y => N_14); - - un2_resadd_ADD_27x27_fast_I22_P0N : OR2A - port map(A => ADDERinA_22, B => ADDERinB(22), Y => N392); - - un2_resadd_ADD_27x27_fast_I213_Y_1 : AO1 - port map(A => ADD_27x27_fast_I213_un1_Y_0, B => N529, C => - ADD_27x27_fast_I213_Y_0, Y => ADD_27x27_fast_I213_Y_1); - - un2_resadd_ADD_27x27_fast_I72_Y : OA1 - port map(A => ADDERinA_2, B => ADDERinB(2), C => N_58, Y - => N450); - - un2_resadd_ADD_27x27_fast_I116_Y_0 : OA1 - port map(A => ADDERinA_4, B => ADDERinB(4), C => N_58, Y - => ADD_27x27_fast_I116_Y_0); - - un2_resadd_ADD_27x27_fast_I109_Y : AO1 - port map(A => N441, B => N438, C => N437, Y => N490); - - \REG[9]\ : DFN1E0C0 - port map(D => \REG_4[9]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(9)); - - un1_clr_1_0 : NOR3 - port map(A => add_D_0, B => MACMUX2sel_D, C => clr_MAC_D_0, - Y => \un1_clr_1_0\); - - un2_resadd_ADD_27x27_fast_I142_Y : NOR2 - port map(A => N483, B => N475, Y => N529); - - \REG_RNO_0[9]\ : MX2C - port map(A => ADDERinB(9), B => \un2_resadd[9]\, S => add_D, - Y => N_17); - - un2_resadd_ADD_27x27_fast_I71_Y : AO13 - port map(A => ADDERinB(3), B => ADDERinA_3, C => N_72, Y - => N449); - - \REG_RNO[22]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_30, Y => \REG_4[22]\); - - \REG[5]\ : DFN1E0C0 - port map(D => \REG_4[5]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(5)); - - un2_resadd_ADD_27x27_fast_I210_Y_0_a2 : OA1 - port map(A => I212_un1_Y, B => ADD_27x27_fast_I212_Y_1, C - => N_105_1, Y => ADD_27x27_fast_I210_Y_0_a2); - - \REG_RNO[2]\ : NOR2 - port map(A => clr_MAC_D, B => N_10, Y => \REG_4[2]\); - - \REG[13]\ : DFN1E0C0 - port map(D => \REG_4[13]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(13)); - - un2_resadd_ADD_27x27_fast_I153_Y : AO1A - port map(A => N487, B => N494, C => N486, Y => N540); - - un2_resadd_ADD_27x27_fast_I232_Y_0 : XOR3 - port map(A => ADDERinB(2), B => ADDERinA_2, C => N_47, Y - => \un2_resadd[2]\); - - un2_resadd_ADD_27x27_fast_I100_Y_0 : OA1 - port map(A => ADDERinA_11, B => ADDERinB(11), C => N362, Y - => ADD_27x27_fast_I100_Y_0); - - \REG[6]\ : DFN1E0C0 - port map(D => \REG_4[6]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(6)); - - \REG[18]\ : DFN1E0C0 - port map(D => \REG_4[18]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(18)); - - un2_resadd_ADD_27x27_fast_I8_P0N : OR2 - port map(A => ADDERinB(8), B => ADDERinA_8, Y => N350); - - un2_resadd_ADD_27x27_fast_I14_G0N : NOR2A - port map(A => ADDERinB(14), B => ADDERinA_14, Y => N367); - - un2_resadd_ADD_27x27_fast_I242_Y_0 : AX1D - port map(A => I193_un1_Y, B => N540, C => - ADD_27x27_fast_I242_Y_0_0, Y => \un2_resadd[12]\); - - un2_resadd_ADD_27x27_fast_I211_un1_Y : OR3C - port map(A => N525, B => N541, C => N502, Y => I211_un1_Y); - - un2_resadd_ADD_27x27_fast_I46_Y_i : OR2B - port map(A => N374, B => N371, Y => N_23_0); - - un2_resadd_ADD_27x27_fast_I239_Y_0_0 : XOR2 - port map(A => ADDERinA_9, B => ADDERinB(9), Y => - ADD_27x27_fast_I239_Y_0_0); - - un2_resadd_ADD_27x27_fast_I155_Y : AO1A - port map(A => N489, B => N496, C => N488, Y => N542); - - un2_resadd_ADD_27x27_fast_I191_Y : AOI1 - port map(A => N552, B => N537, C => N536, Y => N654_i); - - \REG_RNO_0[13]\ : MX2C - port map(A => ADDERinB(13), B => \un2_resadd[13]\, S => - add_D, Y => N_21); - - un2_resadd_ADD_27x27_fast_I249_Y_0_0 : XOR2 - port map(A => ADDERinA_19, B => ADDERinB(19), Y => - ADD_27x27_fast_I249_Y_0_0); - - \REG_RNO_0[18]\ : MX2C - port map(A => ADDERinB(18), B => \un2_resadd[18]\, S => - add_D, Y => N_26); - - \REG_RNO[18]\ : NOR2 - port map(A => clr_MAC_D, B => N_26, Y => \REG_4[18]\); - - \REG[19]\ : DFN1E0C0 - port map(D => \REG_4[19]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(19)); - - un2_resadd_ADD_27x27_fast_I32_Y : OA1 - port map(A => ADDERinA_23, B => ADDERinB(23), C => N392, Y - => N410); - - un2_resadd_ADD_27x27_fast_I53_Y_0 : AO1C - port map(A => N_50, B => N362, C => N361, Y => N431); - - un2_resadd_ADD_27x27_fast_I209_un1_Y : OR3C - port map(A => N537, B => N521, C => N552, Y => I209_un1_Y); - - un2_resadd_ADD_27x27_fast_I147_Y : AO1C - port map(A => N481, B => N488, C => N480, Y => N534); - - un2_resadd_ADD_27x27_fast_I253_Y_0_0 : XOR2 - port map(A => ADDERinA_23, B => ADDERinB(23), Y => - ADD_27x27_fast_I253_Y_0_0); - - un2_resadd_ADD_27x27_fast_I7_G0N : NOR2B - port map(A => ADDERinB(7), B => ADDERinA_7, Y => N346); - - un2_resadd_ADD_27x27_fast_I5_G0N : NOR2B - port map(A => ADDERinB(5), B => ADDERinA_5, Y => N340); - - un2_resadd_ADD_27x27_fast_I138_Y : NOR2 - port map(A => N479, B => N471, Y => N525); - - un2_resadd_ADD_27x27_fast_I154_Y : NOR2A - port map(A => N495, B => N487, Y => N541); - - un2_resadd_ADD_27x27_fast_I37_Y_0_o2 : AO1 - port map(A => N386, B => N382, C => N385, Y => N415); - - \REG_RNO[19]\ : NOR2 - port map(A => clr_MAC_D, B => N_27, Y => \REG_4[19]\); - - un2_resadd_ADD_27x27_fast_I58_Y : OA1 - port map(A => ADDERinA_9, B => ADDERinB(9), C => N356, Y - => N436); - - \REG_RNO_0[1]\ : MX2C - port map(A => ADDERinB(1), B => \un2_resadd[1]\, S => - add_D_0, Y => N_9); - - un2_resadd_ADD_27x27_fast_I94_Y : OR2B - port map(A => N426, B => N422, Y => N475); - - un2_resadd_ADD_27x27_fast_I42_Y : OA1 - port map(A => ADDERinA_17, B => ADDERinB(17), C => N380, Y - => N420); - - un2_resadd_ADD_27x27_fast_I86_Y : OR2B - port map(A => N418, B => N414, Y => N467); - - un2_resadd_ADD_27x27_fast_I75_Y_i_o2 : AO18 - port map(A => ADDERinA_1, B => ADDERinB(1), C => N325, Y - => N_47); - - un2_resadd_ADD_27x27_fast_I231_Y_0 : XOR3 - port map(A => ADDERinB(1), B => ADDERinA_1, C => N325, Y - => \un2_resadd[1]\); - - \REG[1]\ : DFN1E0C0 - port map(D => \REG_4[1]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(1)); - - un2_resadd_ADD_27x27_fast_I241_Y_0 : AX1A - port map(A => N542, B => I194_un1_Y_i, C => - ADD_27x27_fast_I241_Y_0_0, Y => \un2_resadd[11]\); - - un2_resadd_ADD_27x27_fast_I17_G0N : NOR2B - port map(A => ADDERinB(17), B => ADDERinA_17, Y => N376); - - un2_resadd_ADD_27x27_fast_I100_Y : OR2B - port map(A => ADD_27x27_fast_I100_Y_0, B => N428, Y => N481); - - \REG_RNO[24]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_32, Y => \REG_4[24]\); - - un2_resadd_ADD_27x27_fast_I55_Y : MAJ3 - port map(A => ADDERinA_11, B => ADDERinB(11), C => N355, Y - => N433); - - un2_resadd_ADD_27x27_fast_I193_un1_Y : NOR2B - port map(A => N541, B => N502, Y => I193_un1_Y); - - un2_resadd_ADD_27x27_fast_I164_Y_i : AO1C - port map(A => N_48, B => N_108, C => - ADD_27x27_fast_I164_Y_i_0, Y => N_33); - - \REG[20]\ : DFN1E0C0 - port map(D => \REG_4[20]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(20)); - - un2_resadd_ADD_27x27_fast_I252_Y_0 : AX1C - port map(A => I209_un1_Y, B => ADD_27x27_fast_I209_Y_2, C - => ADD_27x27_fast_I252_Y_0_0, Y => \un2_resadd[22]\); - - \REG_RNO[8]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_16, Y => \REG_4[8]\); - - \REG_RNO_0[7]\ : MX2C - port map(A => ADDERinB(7), B => \un2_resadd[7]\, S => - add_D_0, Y => N_15); - - un2_resadd_ADD_27x27_fast_I67_Y : MAJ3 - port map(A => ADDERinA_5, B => ADDERinB(5), C => N_52_i_0, - Y => N445); - - \REG_RNO_0[23]\ : MX2C - port map(A => ADDERinB(23), B => \un2_resadd[23]\, S => - add_D, Y => N_31); - - \REG[3]\ : DFN1E0C0 - port map(D => \REG_4[3]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(3)); - - un2_resadd_ADD_27x27_fast_I248_Y_0_0 : XOR2 - port map(A => ADDERinA_i(18), B => ADDERinB(18), Y => - ADD_27x27_fast_I248_Y_0_0); - - \REG_RNO[3]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_11, Y => \REG_4[3]\); - - un2_resadd_ADD_27x27_fast_I121_Y : AO1 - port map(A => N_47, B => N450, C => N449, Y => N502); - - un2_resadd_ADD_27x27_fast_I113_Y : AO1 - port map(A => N445, B => N442, C => N441, Y => N494); - - \REG[17]\ : DFN1E0C0 - port map(D => \REG_4[17]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(17)); - - un2_resadd_ADD_27x27_fast_I161_Y : AO1 - port map(A => N502, B => N495, C => N494, Y => N548); - - un2_resadd_ADD_27x27_fast_I22_G0N : NOR2A - port map(A => ADDERinB(22), B => ADDERinA_22, Y => N391); - - un2_resadd_ADD_27x27_fast_I157_Y : AO1A - port map(A => N491, B => N498, C => N490, Y => N544); - - GND_i_0 : GND - port map(Y => GND_0); - - un2_resadd_ADD_27x27_fast_I195_un1_Y : OR3B - port map(A => N499, B => N_47, C => N491, Y => I195_un1_Y_i); - - un2_resadd_ADD_27x27_fast_I115_Y : AO1B - port map(A => ADD_27x27_fast_I115_un1_Y_0, B => N444, C => - ADD_27x27_fast_I115_Y_0, Y => N496); - - un2_resadd_ADD_27x27_fast_I89_Y : AO1 - port map(A => N421, B => N418, C => N417, Y => N470); - - \REG_RNO_0[16]\ : MX2C - port map(A => ADDERinB(16), B => \un2_resadd[16]\, S => - add_D, Y => N_24); - - un2_resadd_ADD_27x27_fast_I213_Y_0 : AO1A - port map(A => N475, B => N482, C => N474, Y => - ADD_27x27_fast_I213_Y_0); - - un2_resadd_ADD_27x27_fast_I16_P0N : OR2 - port map(A => ADDERinB(16), B => ADDERinA_16, Y => N374); - - \REG_RNO[16]\ : NOR2 - port map(A => clr_MAC_D, B => N_24, Y => \REG_4[16]\); - - un2_resadd_ADD_27x27_fast_I115_Y_0 : MIN3 - port map(A => ADDERinA_6, B => ADDERinB(6), C => N340, Y - => ADD_27x27_fast_I115_Y_0); - - un2_resadd_ADD_27x27_fast_I47_Y : AO13 - port map(A => N367, B => ADDERinB(15), C => ADDERinA_15, Y - => N425); - - \REG_RNO_0[0]\ : AX1E - port map(A => ADDERinA_0, B => add_D_0, C => ADDERinB(0), Y - => N_8); - - un2_resadd_ADD_27x27_fast_I114_Y : NOR2B - port map(A => N446, B => N442, Y => N495); - - un2_resadd_ADD_27x27_fast_I251_Y_0 : AX1D - port map(A => N415, B => ADD_27x27_fast_I210_Y_0_a2, C => - ADD_27x27_fast_I251_Y_0_0, Y => \un2_resadd[21]\); - - \REG_RNO[6]\ : NOR2 - port map(A => clr_MAC_D, B => N_14, Y => \REG_4[6]\); - - \REG_RNO[5]\ : NOR2 - port map(A => clr_MAC_D, B => N_13, Y => \REG_4[5]\); - - un2_resadd_ADD_27x27_fast_I56_Y : OA1 - port map(A => ADDERinA_11, B => ADDERinB(11), C => N356, Y - => N434); - - \REG[2]\ : DFN1E0C0 - port map(D => \REG_4[2]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(2)); - - un2_resadd_ADD_27x27_fast_I254_Y_0_0 : XOR2 - port map(A => ADDERinA_24, B => ADDERinB(24), Y => - ADD_27x27_fast_I254_Y_0_0); - - un2_resadd_ADD_27x27_fast_I10_P0N : OR2 - port map(A => ADDERinB(10), B => ADDERinA_10, Y => N356); - - \REG_RNO[23]\ : NOR2 - port map(A => clr_MAC_D, B => N_31, Y => \REG_4[23]\); - - un2_resadd_ADD_27x27_fast_I130_Y : NOR2 - port map(A => N471, B => N463, Y => N517); - - un2_resadd_ADD_27x27_fast_I209_Y_1 : OA1A - port map(A => N474, B => N467, C => ADD_27x27_fast_I209_Y_0, - Y => ADD_27x27_fast_I209_Y_1); - - \REG[7]\ : DFN1E0C0 - port map(D => \REG_4[7]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(7)); - - un2_resadd_ADD_27x27_fast_I211_Y_1 : AOI1B - port map(A => N540, B => N525, C => ADD_27x27_fast_I211_Y_0, - Y => ADD_27x27_fast_I211_Y_1); - - un2_resadd_ADD_27x27_fast_I61_Y_0_o2 : AO1 - port map(A => N350, B => N346, C => N349, Y => N439); - - \REG_RNO[10]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_18, Y => \REG_4[10]\); - - \REG[4]\ : DFN1E0C0 - port map(D => \REG_4[4]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(4)); - - \REG[10]\ : DFN1E0C0 - port map(D => \REG_4[10]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(10)); - - un2_resadd_ADD_27x27_fast_I243_Y_0_0 : XOR2 - port map(A => ADDERinA_13, B => ADDERinB(13), Y => - ADD_27x27_fast_I243_Y_0_0); - - un2_resadd_ADD_27x27_fast_I208_Y_3 : AOI1B - port map(A => N534, B => N519, C => ADD_27x27_fast_I208_Y_2, - Y => ADD_27x27_fast_I208_Y_3); - - un2_resadd_ADD_27x27_fast_I192_Y_0_a2 : OA1 - port map(A => I193_un1_Y, B => N540, C => N362, Y => - ADD_27x27_fast_I192_Y_0_a2); - - un2_resadd_ADD_27x27_fast_I190_Y : OR2 - port map(A => N534, B => I190_un1_Y, Y => N651); - - un2_resadd_ADD_27x27_fast_I18_P0N : OR2A - port map(A => ADDERinA_i(18), B => ADDERinB(18), Y => N380); - - un2_resadd_ADD_27x27_fast_I207_un1_Y : OR3C - port map(A => N533, B => N517, C => N548, Y => I207_un1_Y); - - un2_resadd_ADD_27x27_fast_I59_Y : MAJ3 - port map(A => ADDERinA_9, B => ADDERinB(9), C => N349, Y - => N437); - - un2_resadd_ADD_27x27_fast_I251_Y_0_0 : XOR2 - port map(A => ADDERinA_21, B => ADDERinB(21), Y => - ADD_27x27_fast_I251_Y_0_0); - - un2_resadd_ADD_27x27_fast_I208_un1_Y : OR3C - port map(A => N519, B => N535, C => N550, Y => I208_un1_Y); - - \REG_RNO[17]\ : NOR2 - port map(A => clr_MAC_D, B => N_25, Y => \REG_4[17]\); - - un1_clr_1 : NOR3 - port map(A => add_D_0, B => MACMUX2sel_D, C => clr_MAC_D_0, - Y => \un1_clr_1\); - - un2_resadd_ADD_27x27_fast_I98_Y : OR2B - port map(A => N430, B => N426, Y => N479); - - un2_resadd_ADD_27x27_fast_I12_P0N : OR2 - port map(A => ADDERinB(12), B => ADDERinA_12, Y => N362); - - un2_resadd_ADD_27x27_fast_I117_Y : AO1 - port map(A => N449, B => N446, C => N445, Y => N498); - - un2_resadd_ADD_27x27_fast_I64_Y : OA1 - port map(A => ADDERinA_7, B => ADDERinB(7), C => N344, Y - => N442); - - \REG[8]\ : DFN1E0C0 - port map(D => \REG_4[8]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(8)); - - un2_resadd_ADD_27x27_fast_I240_Y_0 : AX1A - port map(A => N544, B => I195_un1_Y_i, C => - ADD_27x27_fast_I240_Y_0_0, Y => \un2_resadd[10]\); - - un2_resadd_ADD_27x27_fast_I0_CO1 : OR2B - port map(A => ADDERinB(0), B => ADDERinA_0, Y => N325); - - un2_resadd_ADD_27x27_fast_I34_Y : OA1 - port map(A => ADDERinA_21, B => ADDERinB(21), C => N392, Y - => N412); - - un2_resadd_ADD_27x27_fast_I105_Y : AO1 - port map(A => N437, B => N434, C => N433, Y => N486); - - \REG_RNO_0[3]\ : MX2C - port map(A => ADDERinB(3), B => \un2_resadd[3]\, S => - add_D_0, Y => N_11); - - un2_resadd_ADD_27x27_fast_I50_Y : OA1 - port map(A => ADDERinA_13, B => ADDERinB(13), C => N368, Y - => N428); - - un2_resadd_ADD_27x27_fast_I239_Y_0 : AX1E - port map(A => N_78_i, B => ADD_27x27_fast_I196_Y_0_0, C => - ADD_27x27_fast_I239_Y_0_0, Y => \un2_resadd[9]\); - - \REG[24]\ : DFN1E0C0 - port map(D => \REG_4[24]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(24)); - - un2_resadd_ADD_27x27_fast_I3_P0N_i_o2 : OR2 - port map(A => ADDERinB(3), B => ADDERinA_3, Y => N_58); - - un2_resadd_ADD_27x27_fast_I15_P0N : OR2A - port map(A => ADDERinA_15, B => ADDERinB(15), Y => N371); - - un2_resadd_ADD_27x27_fast_I249_Y_0 : AX1D - port map(A => I212_un1_Y, B => ADD_27x27_fast_I212_Y_1, C - => ADD_27x27_fast_I249_Y_0_0, Y => \un2_resadd[19]\); - - un2_resadd_ADD_27x27_fast_I189_Y : AOI1 - port map(A => N548, B => N533, C => N532, Y => N648_i); - - un2_resadd_ADD_27x27_fast_I4_G0N_i_o2 : NOR2B - port map(A => ADDERinB(4), B => ADDERinA_4, Y => N_52_i_0); - - un2_resadd_ADD_27x27_fast_I250_Y_0_0 : XOR2 - port map(A => ADDERinA_20, B => ADDERinB(20), Y => - ADD_27x27_fast_I250_Y_0_0); - - \REG_RNO_0[12]\ : MX2C - port map(A => ADDERinB(12), B => \un2_resadd[12]\, S => - add_D, Y => N_20); - - un2_resadd_ADD_27x27_fast_I44_Y : OA1 - port map(A => ADDERinA_17, B => ADDERinB(17), C => N374, Y - => N422); - - un2_resadd_ADD_27x27_fast_I233_Y_0 : XOR3 - port map(A => ADDERinB(3), B => ADDERinA_3, C => N_48, Y - => \un2_resadd[3]\); - - un2_resadd_ADD_27x27_fast_I194_un1_Y : OR2B - port map(A => N_48, B => N543, Y => I194_un1_Y_i); - - un2_resadd_ADD_27x27_fast_I14_P0N : OR2A - port map(A => ADDERinA_14, B => ADDERinB(14), Y => N368); - - un2_resadd_ADD_27x27_fast_I243_Y_0 : AX1A - port map(A => ADD_27x27_fast_I192_Y_0_a2, B => N361, C => - ADD_27x27_fast_I243_Y_0_0, Y => \un2_resadd[13]\); - - un2_resadd_ADD_27x27_fast_I146_Y : NOR2 - port map(A => N487, B => N479, Y => N533); - - \REG_RNO_0[14]\ : MX2C - port map(A => ADDERinB(14), B => \un2_resadd[14]\, S => - add_D_0, Y => N_22); - - \REG[16]\ : DFN1E0C0 - port map(D => \REG_4[16]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(16)); - - un2_resadd_ADD_27x27_fast_I62_Y_i_o2 : OAI1 - port map(A => ADDERinA_7, B => ADDERinB(7), C => N350, Y - => N_73); - - un2_resadd_ADD_27x27_fast_I210_Y_0_a2_1 : NOR2B - port map(A => N386, B => N383, Y => N_105_1); - - un2_resadd_ADD_27x27_fast_I102_Y : OR2B - port map(A => N434, B => N430, Y => N483); - - \REG_RNO_0[4]\ : MX2C - port map(A => ADDERinB(4), B => \un2_resadd[4]\, S => - add_D_0, Y => N_12); - - un2_resadd_ADD_27x27_fast_I20_G0N : NOR2B - port map(A => ADDERinB(20), B => ADDERinA_20, Y => N385); - - \REG_RNO_0[2]\ : MX2C - port map(A => ADDERinB(2), B => \un2_resadd[2]\, S => add_D, - Y => N_10); - - un2_resadd_ADD_27x27_fast_I82_Y : OR2B - port map(A => N414, B => N410, Y => N463); - - un2_resadd_ADD_27x27_fast_I234_Y_0 : XOR3 - port map(A => ADDERinB(4), B => ADDERinA_4, C => N502, Y - => \un2_resadd[4]\); - - un2_resadd_ADD_27x27_fast_I250_Y_0 : AX1E - port map(A => I211_un1_Y, B => ADD_27x27_fast_I211_Y_1, C - => ADD_27x27_fast_I250_Y_0_0, Y => \un2_resadd[20]\); - - un2_resadd_ADD_27x27_fast_I252_Y_0_0 : XOR2 - port map(A => ADDERinA_22, B => ADDERinB(22), Y => - ADD_27x27_fast_I252_Y_0_0); - - un2_resadd_ADD_27x27_fast_I244_Y_0 : XOR3 - port map(A => ADDERinB(14), B => ADDERinA_14, C => N654_i, - Y => \un2_resadd[14]\); - - un2_resadd_ADD_27x27_fast_I69_Y_i_a2 : NOR2 - port map(A => N_59, B => N_52_i_0, Y => N_108); - - un2_resadd_ADD_27x27_fast_I18_G0N : NOR2A - port map(A => ADDERinB(18), B => ADDERinA_i(18), Y => N379); - - un2_resadd_ADD_27x27_fast_I13_G0N : OR2B - port map(A => ADDERinB(13), B => ADDERinA_13, Y => N364); - - \REG_RNO_0[5]\ : MX2C - port map(A => ADDERinB(5), B => \un2_resadd[5]\, S => add_D, - Y => N_13); - - \REG[21]\ : DFN1E0C0 - port map(D => \REG_4[21]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1\, Q => ADDERout(21)); - - un2_resadd_ADD_27x27_fast_I237_Y_0 : XOR3 - port map(A => ADDERinB(7), B => ADDERinA_7, C => N550, Y - => \un2_resadd[7]\); - - \REG_RNO_0[22]\ : MX2C - port map(A => ADDERinB(22), B => \un2_resadd[22]\, S => - add_D_0, Y => N_30); - - un2_resadd_ADD_27x27_fast_I107_Y : AO1B - port map(A => N439, B => N436, C => ADD_27x27_fast_I107_Y_0, - Y => N488); - - un2_resadd_ADD_27x27_fast_I247_Y_0 : AX1A - port map(A => N423, B => N_98_i, C => - ADD_27x27_fast_I247_Y_0_0, Y => \un2_resadd[17]\); - - \REG_RNO[0]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_8, Y => \REG_4[0]\); - - \REG_RNO_0[15]\ : MX2C - port map(A => ADDERinB(15), B => \un2_resadd[15]\, S => - add_D_0, Y => N_23); - - un2_resadd_ADD_27x27_fast_I148_Y : NOR2 - port map(A => N489, B => N481, Y => N535); - - \REG_RNO_0[24]\ : MX2C - port map(A => ADDERinB(24), B => \un2_resadd[24]\, S => - add_D_0, Y => N_32); - - un2_resadd_ADD_27x27_fast_I253_Y_0 : AX1E - port map(A => I208_un1_Y, B => ADD_27x27_fast_I208_Y_3, C - => ADD_27x27_fast_I253_Y_0_0, Y => \un2_resadd[23]\); - - un2_resadd_ADD_27x27_fast_I213_un1_Y_0 : NOR3B - port map(A => N499, B => N_47, C => N491, Y => - ADD_27x27_fast_I213_un1_Y_0); - - \REG[15]\ : DFN1E0C0 - port map(D => \REG_4[15]\, CLK => HCLK_c, CLR => HRESETn_c, - E => \un1_clr_1_0\, Q => ADDERout(15)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_MUX2 is - - port( MULTout_D : in std_logic_vector(24 downto 7); - ADDERout : in std_logic_vector(24 downto 7); - sample_out_s : out std_logic_vector(17 downto 0); - MACMUX2sel_D_D : in std_logic - ); - -end MAC_MUX2; - -architecture DEF_ARCH of MAC_MUX2 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \RES[19]\ : MX2 - port map(A => ADDERout(19), B => MULTout_D(19), S => - MACMUX2sel_D_D, Y => sample_out_s(12)); - - \RES[9]\ : MX2 - port map(A => ADDERout(9), B => MULTout_D(9), S => - MACMUX2sel_D_D, Y => sample_out_s(2)); - - GND_i_0 : GND - port map(Y => GND_0); - - \RES[12]\ : MX2 - port map(A => ADDERout(12), B => MULTout_D(12), S => - MACMUX2sel_D_D, Y => sample_out_s(5)); - - VCC_i : VCC - port map(Y => \VCC\); - - \RES[17]\ : MX2 - port map(A => ADDERout(17), B => MULTout_D(17), S => - MACMUX2sel_D_D, Y => sample_out_s(10)); - - \RES[22]\ : MX2 - port map(A => ADDERout(22), B => MULTout_D(22), S => - MACMUX2sel_D_D, Y => sample_out_s(15)); - - \RES[11]\ : MX2 - port map(A => ADDERout(11), B => MULTout_D(11), S => - MACMUX2sel_D_D, Y => sample_out_s(4)); - - \RES[18]\ : MX2 - port map(A => ADDERout(18), B => MULTout_D(18), S => - MACMUX2sel_D_D, Y => sample_out_s(11)); - - \RES[21]\ : MX2 - port map(A => ADDERout(21), B => MULTout_D(21), S => - MACMUX2sel_D_D, Y => sample_out_s(14)); - - \RES[14]\ : MX2 - port map(A => ADDERout(14), B => MULTout_D(14), S => - MACMUX2sel_D_D, Y => sample_out_s(7)); - - GND_i : GND - port map(Y => \GND\); - - \RES[24]\ : MX2 - port map(A => ADDERout(24), B => MULTout_D(24), S => - MACMUX2sel_D_D, Y => sample_out_s(17)); - - \RES[10]\ : MX2 - port map(A => ADDERout(10), B => MULTout_D(10), S => - MACMUX2sel_D_D, Y => sample_out_s(3)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \RES[8]\ : MX2 - port map(A => ADDERout(8), B => MULTout_D(8), S => - MACMUX2sel_D_D, Y => sample_out_s(1)); - - \RES[16]\ : MX2 - port map(A => ADDERout(16), B => MULTout_D(16), S => - MACMUX2sel_D_D, Y => sample_out_s(9)); - - \RES[20]\ : MX2 - port map(A => ADDERout(20), B => MULTout_D(20), S => - MACMUX2sel_D_D, Y => sample_out_s(13)); - - \RES[13]\ : MX2 - port map(A => ADDERout(13), B => MULTout_D(13), S => - MACMUX2sel_D_D, Y => sample_out_s(6)); - - \RES[7]\ : MX2 - port map(A => ADDERout(7), B => MULTout_D(7), S => - MACMUX2sel_D_D, Y => sample_out_s(0)); - - \RES[23]\ : MX2 - port map(A => ADDERout(23), B => MULTout_D(23), S => - MACMUX2sel_D_D, Y => sample_out_s(16)); - - \RES[15]\ : MX2 - port map(A => ADDERout(15), B => MULTout_D(15), S => - MACMUX2sel_D_D, Y => sample_out_s(8)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_2 is - - port( MACMUXsel_D : out std_logic; - MACMUXsel_D_0 : out std_logic; - N_4 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - MACMUXsel_D_1 : out std_logic - ); - -end MAC_REG_1_2; - -architecture DEF_ARCH of MAC_REG_1_2 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_1[0]\ : DFN1C0 - port map(D => N_4, CLK => HCLK_c, CLR => HRESETn_c, Q => - MACMUXsel_D_1); - - \Q_0[0]\ : DFN1C0 - port map(D => N_4, CLK => HCLK_c, CLR => HRESETn_c, Q => - MACMUXsel_D_0); - - \Q[0]\ : DFN1C0 - port map(D => N_4, CLK => HCLK_c, CLR => HRESETn_c, Q => - MACMUXsel_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Multiplier is - - port( MULTout : out std_logic_vector(24 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - mult : in std_logic; - mult_0 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end Multiplier; - -architecture DEF_ARCH of Multiplier is - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N399, ADD_22x22_fast_I80_un1_Y, N354, I120_un1_Y, - N407, N400, ADD_22x22_fast_I154_Y_0, - ADD_22x22_fast_I208_Y_0_0, N_253, N_250, - ADD_22x22_fast_I209_Y_0_2, N_252, - ADD_22x22_fast_I209_Y_0_0, N_254, \a17_b_i[7]\, - ADD_22x22_fast_I207_Y_0_0, N_249, N_244, - ADD_22x22_fast_I171_Y_2, I70_un1_Y, - ADD_22x22_fast_I171_Y_0, I110_un1_Y, N321, - ADD_22x22_fast_I206_Y_0_0, N_243, N_236, - ADD_22x22_fast_I170_Y_2, N395, N388, - ADD_22x22_fast_I170_Y_1, N346, N343, - ADD_22x22_fast_I170_Y_0, N324, ADD_22x22_fast_I205_Y_0_0, - madd_301, madd_527_0, N_235, ADD_22x22_fast_I172_Y_2, - I112_un1_Y, ADD_22x22_fast_I172_Y_0, I148_un1_Y, N350, - N347, ADD_22x22_fast_I200_Y_0_0, N_167, N_152, - ADD_22x22_fast_I203_Y_0_0, madd_262, madd_462_0, N_213, - ADD_22x22_fast_I173_Y_2, ADD_22x22_fast_I114_un1_Y, - ADD_22x22_fast_I173_Y_0, I173_un1_Y_i, - ADD_22x22_fast_I74_un1_Y, ADD_22x22_fast_I32_un1_Y, N318, - ADD_22x22_fast_I199_Y_0_0, N_134, N_149, N_136, - ADD_22x22_fast_I201_Y_0_0, N_150, N_165, N_183, - ADD_22x22_fast_I152_Y_0, N403, N396, - ADD_22x22_fast_I202_Y_0_0, N_182, madd_458_0_0, N_184, - ADD_22x22_fast_I198_Y_0_0, N_118, N_133, N_120, - ADD_22x22_fast_I172_un1_Y_0, N408, N416, N378, - ADD_22x22_fast_I153_un1_Y_0, N361, N398, N365, - ADD_22x22_fast_I155_Y_0, I82_un1_Y, N356, I155_un1_Y_i, - ADD_22x22_fast_I196_Y_0_0, N_86, N_101, N_88, - ADD_22x22_fast_I173_un1_Y_0, N410, N418, N_12, - ADD_22x22_fast_I152_un1_Y_0, I132_un1_Y_i, N411, N404, - ADD_22x22_fast_I197_Y_0_0, N_104, N_119, - ADD_22x22_fast_I157_un1_Y_0, N373, N421, N369, - ADD_22x22_fast_I155_un1_Y_0, I135_un1_Y_i, N417, - ADD_22x22_fast_I195_Y_0_0, N_72, N_87, - ADD_22x22_fast_I194_Y_0_0, N_69, madd_124_m6, N_56, - ADD_22x22_fast_I192_Y_0_0, N_28, N_39, N_30, N_180, - madd_458_14_0, N_195, madd_548_0_0, N_222, N_233, - ADD_22x22_fast_I190_Y_0_0, N_11_i, CO2, N_19, - madd_416_0_0, N_177_i, N_164, madd_268_0_0, N_113_i, - N_115, madd_522_0_tz_0, N_192, N_194, N_219, - madd_198_0_tz_0, N_61_i, N_63, N_50, madd_235_0_tz_0, - N_64_i, N_79, N_66, madd_24_0_0, N_7_i, N_9, - madd_120_0_0_1, N_32_i, N_43, N_34, madd_457_m5_0, N_185, - N_187, madd_39_0_0, N_15_i, N_13, madd_24_4_0, \a1_b[3]\, - \a0_b[4]\, madd_88_8_0, N_33_i, N_31, madd_268_8_0, - N_105_i, N_109, madd_115_0_0_1, \a0_b[8]\, \a2_b[6]\, - \a1_b[7]\, madd_493_6_0, \a_i10_b[8]\, madd_39_2_0, - \a5_b[0]\, \a3_b[2]\, madd_231_2_0, \a11_b[0]\, \a9_b[2]\, - madd_268_2_0, \a12_b[0]\, \a10_b[2]\, madd_523_4_0, - \a14_b[5]\, \a12_b[7]\, madd_458_2_0, madd_24_2_0, - \a2_b[2]\, \a4_b[0]\, madd_268_7_0, \a6_b[6]\, \a5_b[7]\, - madd_88_4_0, \a2_b[5]\, \a4_b[3]\, I157_un1_Y, I130_un1_Y, - ADD_22x22_fast_I171_un1_Y_0, madd_235_0_tz, N_99, N_174, - N_191, N402, I172_un1_Y, N392, ADD_22x22_fast_I115_Y_0, - I152_un1_Y, I154_un1_Y, N461, N_246_i, N_251, N_248, - \a16_b[7]\, \a_i15_b[8]\, \a17_b_i[6]\, N_240_i, N_247, - N_242, N_245, \a_i14_b[8]\, N_238, \a16_b[6]\, \a15_b[7]\, - \a17_b_i[5]\, N_241, N_239_i, N_234, N_237, \a16_b[5]\, - \a15_b[6]\, \a17_b_i[4]\, \a_i13_b[8]\, \a14_b[7]\, N_228, - N_230_i, N_232, N_224, N_231, N_229_i, N_220, N_227_i, - \a16_b[4]\, \a15_b[5]\, \a17_b_i[3]\, \a13_b[7]\, - \a14_b[6]\, \a_i12_b[8]\, N_218, N_216, N_225, N_223, - N_221, N_212, N_215, \a16_b[3]\, \a15_b[4]\, \a17_b_i[2]\, - N_217, \a13_b[6]\, N_204, \a_i11_b[8]\, N_202, N_208, - N_210, madd_457_m6, N_209_i, N_211, N_201, \a16_b[2]\, - \a15_b[3]\, \a17_b_i[1]\, N_203_i, \a12_b[6]\, \a14_b[4]\, - \a13_b[5]\, N_207, N_188_i, N_190, N_205, N_196, N_169_i, - \a15_b[1]\, \a16_b[0]\, \a14_b[2]\, N_171, \a11_b[5]\, - \a13_b[3]\, \a12_b[4]\, N_173, \a9_b[7]\, \a10_b[6]\, - \a_i8_b[8]\, N_175_i_0, N_156, N_154_i, N_158, N_163, - N_161_i, N_148, N_153_i, \a13_b[2]\, \a15_b[0]\, - \a14_b[1]\, N_155, \a10_b[5]\, \a12_b[3]\, \a11_b[4]\, - N_157, \a8_b[7]\, \a9_b[6]\, \a_i7_b[8]\, N_159_i, N_142, - N_138_i, N_140, N_146, N_144, N_147, N_145_i, N_132, - N_137_i, \a12_b[2]\, \a14_b[0]\, \a13_b[1]\, N_139, - \a9_b[5]\, \a11_b[3]\, \a10_b[4]\, N_141, \a_i6_b[8]\, - \a8_b[6]\, \a7_b[7]\, N_143_i, N_126, N_122_i, N_124, - N_130, N_128, N_131, N_129_i, N_116, N_121_i, \a11_b[2]\, - \a13_b[0]\, \a12_b[1]\, N_123, \a8_b[5]\, \a10_b[3]\, - \a9_b[4]\, N_125, \a6_b[7]\, \a7_b[6]\, \a_i5_b[8]\, - N_127_i, N_108, N_106_i, N_110, N_114, N_112, \a11_b[1]\, - N_107, \a7_b[5]\, \a9_b[3]\, \a8_b[4]\, \a_i4_b[8]\, - N_111_i, N_92, N_90_i, N_94, N_98, N_96, N_97, N_84, - N_89_i, \a10_b[1]\, N_91, \a6_b[5]\, \a8_b[3]\, \a7_b[4]\, - N_93, \a4_b[7]\, \a5_b[6]\, \a_i3_b[8]\, N_95_i, N_76, - N_74_i, N_78, N_82, N_80, N_85, N_83, N_81, N_68, N_73_i, - \a8_b[2]\, \a10_b[0]\, \a9_b[1]\, N_75, \a5_b[5]\, - \a7_b[3]\, \a6_b[4]\, N_77, \a4_b[6]\, \a_i2_b[8]\, - \a3_b[7]\, N_60, N_58_i, N_62, madd_119_m6, N_65_i, N_67, - N_57, \a7_b[2]\, \a9_b[0]\, \a8_b[1]\, N_59_i, \a5_b[4]\, - \a6_b[3]\, \a4_b[5]\, \a3_b[6]\, \a2_b[7]\, \a_i1_b[8]\, - N_44, \a_i0_b[8]\, N_46, N_48, N_45, \a3_b[5]\, \a5_b[3]\, - \a4_b[4]\, \a6_b[2]\, \a8_b[0]\, \a7_b[1]\, \a5_b[2]\, - \a7_b[0]\, \a6_b[1]\, \a3_b[4]\, N_37, N_24, N_25, N_14, - \a0_b[6]\, N_16, N_27, N_21_i, N_23, N_18, \a3_b[3]\, - \a2_b[4]\, \a1_b[5]\, N_17, N_8, \a4_b[1]\, \a0_b[5]\, - \a2_b[3]\, \a1_b[4]\, N_6, \a3_b[1]\, N_4, N_5, N_3, - \a0_b[3]\, N_2, \a3_b[0]\, \a2_b[1]\, \a1_b[2]\, N_1_i, - \a0_b[2]\, \a2_b[0]\, \a1_b[1]\, \a13_b[4]\, \a15_b[2]\, - \a14_b[3]\, N_189_i, \a10_b[7]\, \a12_b[5]\, \a11_b[6]\, - N_170, \a_i9_b[8]\, N_172, N_178, N_176, \RESMULT[24]\, - ADD_22x22_fast_I170_Y_3, \RESMULT[23]\, - ADD_22x22_fast_I171_Y_3, \RESMULT[22]\, \RESMULT[21]\, - I150_un1_Y, \RESMULT[20]\, \RESMULT[18]\, \RESMULT[17]\, - I122_un1_Y, \RESMULT[16]\, N449, I156_un1_Y_i, - \RESMULT[15]\, N451, \RESMULT[14]\, I158_un1_Y, N453, - \RESMULT[13]\, N455, I159_un1_Y_i, \RESMULT[12]\, - \RESMULT[10]\, \RESMULT[9]\, \RESMULT[8]\, N_53, N_55, - N419, \RESMULT[7]\, \RESMULT[6]\, N_29, \RESMULT[5]\, - \RESMULT[11]\, N413, I133_un1_Y_i, \RESMULT[19]\, N_214, - N544, \a17_b_i[0]\, N_186_1, N_206, I118_un1_Y, N397, - I153_un1_Y, N390, ADD_22x22_fast_I171_Y_3_tz, - ADD_22x22_fast_I170_Y_3_tz, N319, N313, N353, N349, - madd_61_2_0, \a6_b[0]\, \a5_b[1]\, N316, \a4_b[2]\, N_35, - \a0_b[7]\, \a1_b[6]\, N_22, madd_88_0_0, N_26, N_38, - N_40_i, N_51, N_36, N_179, N_162, N_160, madd_457_N_4, - madd_457tt_m3, madd_119_N_4, madd_119tt_m3, madd_124_N_4, - madd_124tt_m3, ADD_22x22_fast_I170_un1_Y_0, madd_462_0_tz, - madd_522_0, madd_487_0, madd_198_0, madd_477_0, - madd_477_0_tz, N412, madd_271, N_10, N_70, madd_112, - N_100, N_102, madd_133, N_166, madd_298, CO1, \a0_b[1]\, - \a1_b[0]\, \RESMULT[1]\, \RESMULT[2]\, \RESMULT[3]\, - \RESMULT[4]\, N273, N274, N276, N277, N279, N280, N288, - N289, N291, N292, N294, N295, N297, N298, N300, N301, - N303, N304, N306, N307, N352, N309, N312, N310, N357, - N362, N363, N364, N368, N285, N286, N372, N283, N376, - N377, N360, I90_un1_Y, N409, I101_un1_Y, N415, N345, N325, - N405, N282, N370, N374, N351, N358, N359, I92_un1_Y, N366, - N371, N375, I124_un1_Y, I134_un1_Y, madd_240, I126_un1_Y, - \RESMULT[0]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - RESMULT_madd_120_0 : XNOR3 - port map(A => N_38, B => madd_120_0_0_1, C => N_40_i, Y => - N_53); - - RESMULT_madd_452 : MIN3 - port map(A => N_189_i, B => N_176, C => N_178, Y => N_196); - - \RESMULT_a9_b[1]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(1), Y => - \a9_b[1]\); - - RESMULT_madd_65 : AO13 - port map(A => N_18, B => N_21_i, C => N_23, Y => N_28); - - RESMULT_madd_420 : AO18 - port map(A => N_164, B => N_179, C => N_177_i, Y => N_182); - - RESMULT_madd_606_ADD_22x22_fast_I3_P0N : OR2 - port map(A => N_55, B => N_53, Y => N283); - - RESMULT_madd_523_0 : XOR3 - port map(A => N_223, B => N_221, C => N_212, Y => N_225); - - \RESMULT_a4_b[2]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(2), Y => - \a4_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I124_un1_Y : NOR2B - port map(A => N411, B => N404, Y => I124_un1_Y); - - RESMULT_madd_552 : MIN3 - port map(A => N_222, B => N_224, C => N_233, Y => N_236); - - \RESMULT_a9_b[4]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(4), Y => - \a9_b[4]\); - - RESMULT_madd_267 : MAJ3 - port map(A => N_111_i, B => N_96, C => N_98, Y => N_116); - - \RESMULT_a11_b[5]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(5), Y => - \a11_b[5]\); - - \RESMULT_a10_b[7]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(7), Y => - \a10_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I58_Y : AO1 - port map(A => N280, B => N276, C => N279, Y => N374); - - RESMULT_madd_606_ADD_22x22_fast_I55_Y : NOR2B - port map(A => N286, B => N283, Y => N371); - - RESMULT_madd_606_ADD_22x22_fast_I99_Y : NOR2B - port map(A => N377, B => N373, Y => N418); - - RESMULT_madd_606_ADD_22x22_fast_I156_un1_Y : OR3C - port map(A => N404, B => N412, C => N419, Y => I156_un1_Y_i); - - RESMULT_madd_146 : MAJ3 - port map(A => \a_i0_b[8]\, B => N_44, C => N_46, Y => - N_64_i); - - RESMULT_madd_61_2_0 : XOR2 - port map(A => \a6_b[0]\, B => \a5_b[1]\, Y => madd_61_2_0); - - RESMULT_madd_378 : MAJ3 - port map(A => N_159_i, B => N_144, C => N_146, Y => N_164); - - RESMULT_madd_231_0 : XNOR3 - port map(A => N_99, B => N_97, C => N_84, Y => N_101); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_0 : NOR3A - port map(A => ADD_22x22_fast_I74_un1_Y, B => - ADD_22x22_fast_I32_un1_Y, C => N318, Y => - ADD_22x22_fast_I173_Y_0); - - \RESMULT_a11_b[0]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(0), Y => - \a11_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I9_G0N : XA1A - port map(A => N_134, B => N_149, C => N_136, Y => N300); - - \RESMULT_a13_b[7]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(7), Y => - \a13_b[7]\); - - RESMULT_madd_457_m5 : XOR3 - port map(A => N_174, B => madd_457_m5_0, C => N_191, Y => - madd_458_14_0); - - RESMULT_madd_43 : AO13 - port map(A => N_8, B => N_15_i, C => N_13, Y => N_18); - - RESMULT_madd_141 : MAJ3 - port map(A => \a3_b[6]\, B => \a2_b[7]\, C => \a_i1_b[8]\, - Y => N_62); - - \RESMULT_a7_b[7]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(7), Y => - \a7_b[7]\); - - RESMULT_madd_235 : AO1 - port map(A => madd_235_0_tz, B => N_97, C => madd_133, Y - => N_102); - - RESMULT_madd_197 : NOR2A - port map(A => N_83, B => N_68, Y => madd_112); - - RESMULT_madd_606_ADD_22x22_fast_I200_Y_0_0 : XOR2 - port map(A => N_167, B => N_152, Y => - ADD_22x22_fast_I200_Y_0_0); - - RESMULT_madd_38 : MIN3 - port map(A => \a2_b[3]\, B => \a0_b[5]\, C => \a1_b[4]\, Y - => N_16); - - \REG[6]\ : DFN1E1C0 - port map(D => \RESMULT[6]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(6)); - - RESMULT_madd_200 : NOR2A - port map(A => N_85, B => N_70, Y => N_88); - - RESMULT_madd_104 : MAJ3 - port map(A => \a5_b[3]\, B => \a3_b[5]\, C => \a4_b[4]\, Y - => N_46); - - \RESMULT_a14_b[7]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(7), Y => - \a14_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I31_Y : AO1C - port map(A => N_243, B => N_236, C => N319, Y => N347); - - \RESMULT_a6_b[7]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(7), Y => - \a6_b[7]\); - - \RESMULT_a0_b[3]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(3), Y => - \a0_b[3]\); - - \RESMULT_a4_b[3]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(3), Y => - \a4_b[3]\); - - \RESMULT_a15_b[4]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(4), Y => - \a15_b[4]\); - - RESMULT_madd_247 : MAJ3 - port map(A => \a9_b[3]\, B => \a7_b[5]\, C => \a8_b[4]\, Y - => N_108); - - RESMULT_madd_606_ADD_22x22_fast_I172_un1_Y_0 : NOR3C - port map(A => N408, B => N416, C => N378, Y => - ADD_22x22_fast_I172_un1_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I122_un1_Y : OR2A - port map(A => N409, B => N402, Y => I122_un1_Y); - - RESMULT_madd_523_8 : XOR3 - port map(A => N_217, B => N_215, C => N_206, Y => N_221); - - \RESMULT_a16_b[7]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(7), Y => - \a16_b[7]\); - - RESMULT_madd_457_m5_0 : XOR2 - port map(A => N_185, B => N_187, Y => madd_457_m5_0); - - RESMULT_madd_235_0_tz : OR2 - port map(A => madd_235_0_tz_0, B => N_99, Y => - madd_235_0_tz); - - RESMULT_madd_61_0 : XOR3 - port map(A => N_21_i, B => N_23, C => N_18, Y => N_27); - - \RESMULT_a9_b[0]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(0), Y => - \a9_b[0]\); - - \RESMULT_a6_b[1]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(1), Y => - \a6_b[1]\); - - \RESMULT_a13_b[0]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(0), Y => - \a13_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I73_Y : OR2A - port map(A => N351, B => N347, Y => N392); - - RESMULT_madd_507 : MAJ3 - port map(A => \a14_b[5]\, B => \a12_b[7]\, C => \a13_b[6]\, - Y => N_218); - - RESMULT_madd_606_ADD_22x22_fast_I155_un1_Y : OR2A - port map(A => ADD_22x22_fast_I155_un1_Y_0, B => N402, Y => - I155_un1_Y_i); - - RESMULT_madd_252 : MAJ3 - port map(A => \a6_b[6]\, B => \a5_b[7]\, C => \a_i4_b[8]\, - Y => N_110); - - RESMULT_madd_472 : MAJ3 - port map(A => \a14_b[4]\, B => \a12_b[6]\, C => \a13_b[5]\, - Y => N_204); - - RESMULT_madd_67 : NOR3B - port map(A => N_17, B => N_25, C => N_10, Y => N_30); - - RESMULT_madd_95_0 : XNOR3 - port map(A => \a6_b[2]\, B => \a8_b[0]\, C => \a7_b[1]\, Y - => N_43); - - \REG[18]\ : DFN1E1C0 - port map(D => \RESMULT[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(18)); - - RESMULT_madd_568_4 : XOR3 - port map(A => \a_i13_b[8]\, B => \a14_b[7]\, C => N_228, Y - => N_239_i); - - \RESMULT_a1_b[6]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(6), Y => - \a1_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I197_Y_0 : AX1A - port map(A => N411, B => I132_un1_Y_i, C => - ADD_22x22_fast_I197_Y_0_0, Y => \RESMULT[12]\); - - RESMULT_madd_572 : AO18 - port map(A => N_234, B => N_241, C => N_239_i, Y => N_244); - - \RESMULT_a7_b[0]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(0), Y => - \a7_b[0]\); - - RESMULT_madd_88_4 : XOR2 - port map(A => madd_88_4_0, B => \a3_b[4]\, Y => N_33_i); - - RESMULT_madd_72 : MAJ3 - port map(A => \a7_b[0]\, B => \a5_b[2]\, C => \a6_b[1]\, Y - => N_32_i); - - RESMULT_madd_230 : MAJ3 - port map(A => N_95_i, B => N_80, C => N_82, Y => N_100); - - RESMULT_madd_88_8 : XOR2 - port map(A => madd_88_8_0, B => N_24, Y => N_37); - - RESMULT_madd_606_ADD_22x22_fast_I80_un1_Y : NOR3C - port map(A => N307, B => N310, C => N358, Y => - ADD_22x22_fast_I80_un1_Y); - - RESMULT_madd_458_0_0 : XNOR3 - port map(A => N_180, B => madd_458_14_0, C => N_195, Y => - madd_458_0_0); - - RESMULT_madd_66_0 : AX1 - port map(A => N_10, B => N_17, C => N_25, Y => N_29); - - RESMULT_madd_606_ADD_22x22_fast_I204_Y_0 : XOR3 - port map(A => N_225, B => N_214, C => N544, Y => - \RESMULT[19]\); - - RESMULT_madd_231_12 : XNOR3 - port map(A => N_82, B => N_95_i, C => N_80, Y => N_99); - - RESMULT_madd_194_4 : XNOR3 - port map(A => \a5_b[5]\, B => \a7_b[3]\, C => \a6_b[4]\, Y - => N_75); - - RESMULT_madd_458_2 : XOR2 - port map(A => madd_458_2_0, B => \a17_b_i[0]\, Y => N_185); - - \RESMULT_a_i13_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(13), Y => - \a_i13_b[8]\); - - \REG[19]\ : DFN1E1C0 - port map(D => \RESMULT[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(19)); - - \RESMULT_a6_b[0]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(0), Y => - \a6_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I34_Y : AO13 - port map(A => N312, B => N_225, C => N_214, Y => N350); - - RESMULT_madd_606_ADD_22x22_fast_I5_P0N : OR2 - port map(A => N_87, B => N_72, Y => N289); - - RESMULT_madd_606_ADD_22x22_fast_I197_Y_0_0 : XOR2 - port map(A => N_104, B => N_119, Y => - ADD_22x22_fast_I197_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I83_Y : OR2A - port map(A => N361, B => N357, Y => N402); - - RESMULT_madd_537 : MAJ3 - port map(A => \a14_b[6]\, B => \a13_b[7]\, C => - \a_i12_b[8]\, Y => N_230_i); - - RESMULT_madd_606_ADD_22x22_fast_I152_Y_0 : AO1 - port map(A => N403, B => N396, C => N395, Y => - ADD_22x22_fast_I152_Y_0); - - \RESMULT_a13_b[2]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(2), Y => - \a13_b[2]\); - - RESMULT_madd_416_4 : XNOR3 - port map(A => \a11_b[5]\, B => \a13_b[3]\, C => \a12_b[4]\, - Y => N_171); - - RESMULT_madd_606_ADD_22x22_fast_I42_Y : MAJ3 - port map(A => N_152, B => N_167, C => N300, Y => N358); - - RESMULT_madd_606_ADD_22x22_fast_I16_G0N : NOR2A - port map(A => N_243, B => N_236, Y => N321); - - \RESMULT_a_i0_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(0), Y => - \a_i0_b[8]\); - - RESMULT_madd_437 : MAJ3 - port map(A => \a12_b[5]\, B => \a10_b[7]\, C => \a11_b[6]\, - Y => N_190); - - RESMULT_madd_606_ADD_22x22_fast_I100_Y : AO1 - port map(A => N378, B => N375, C => N374, Y => N419); - - RESMULT_madd_606_ADD_22x22_fast_I199_Y_0_0 : XNOR3 - port map(A => N_134, B => N_149, C => N_136, Y => - ADD_22x22_fast_I199_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I98_Y : AO1 - port map(A => N376, B => N373, C => N372, Y => N417); - - \RESMULT_a4_b[7]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(7), Y => - \a4_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I9_P0N : XO1A - port map(A => N_134, B => N_149, C => N_136, Y => N301); - - RESMULT_madd_304 : MAJ3 - port map(A => N_127_i, B => N_112, C => N_114, Y => N_132); - - \RESMULT_a_i9_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(9), Y => - \a_i9_b[8]\); - - \REG[1]\ : DFN1E1C0 - port map(D => \RESMULT[1]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult_0, Q => MULTout(1)); - - \RESMULT_a5_b[1]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(1), Y => - \a5_b[1]\); - - \RESMULT_a1_b[7]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(7), Y => - \a1_b[7]\); - - \RESMULT_a1_b[4]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(4), Y => - \a1_b[4]\); - - RESMULT_madd_476 : NOR2B - port map(A => \a_i10_b[8]\, B => N_186_1, Y => madd_271); - - RESMULT_madd_39_2_0 : XOR2 - port map(A => \a5_b[0]\, B => \a3_b[2]\, Y => madd_39_2_0); - - RESMULT_madd_119_m6 : AO18 - port map(A => N_45, B => madd_115_0_0_1, C => madd_119_N_4, - Y => madd_119_m6); - - RESMULT_madd_606_ADD_22x22_fast_I133_un1_Y : OR3B - port map(A => N373, B => N421, C => N369, Y => I133_un1_Y_i); - - RESMULT_madd_583_0 : XOR3 - port map(A => N_240_i, B => N_247, C => N_242, Y => N_249); - - RESMULT_madd_18 : MAJ3 - port map(A => \a4_b[0]\, B => \a2_b[2]\, C => \a3_b[1]\, Y - => N_8); - - \RESMULT_a9_b[7]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(7), Y => - \a9_b[7]\); - - RESMULT_madd_492 : MAJ3 - port map(A => N_205, B => N_196, C => N_207, Y => N_212); - - \RESMULT_a0_b[5]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(5), Y => - \a0_b[5]\); - - \RESMULT_a2_b[4]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(4), Y => - \a2_b[4]\); - - RESMULT_madd_462_0 : NOR2B - port map(A => madd_462_0_tz, B => N_195, Y => madd_462_0); - - RESMULT_madd_272 : AO13 - port map(A => N_100, B => N_113_i, C => N_115, Y => N_118); - - \RESMULT_a9_b[5]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(5), Y => - \a9_b[5]\); - - RESMULT_madd_225 : AO18 - port map(A => N_93, B => N_89_i, C => N_91, Y => N_98); - - RESMULT_madd_606_ADD_22x22_fast_I194_Y_0 : AX1A - port map(A => N417, B => I135_un1_Y_i, C => - ADD_22x22_fast_I194_Y_0_0, Y => \RESMULT[9]\); - - RESMULT_madd_592 : MAJ3 - port map(A => \a_i15_b[8]\, B => \a16_b[7]\, C => - \a17_b_i[6]\, Y => N_252); - - RESMULT_madd_458_7 : XOR3 - port map(A => \a10_b[7]\, B => \a12_b[5]\, C => \a11_b[6]\, - Y => N_189_i); - - \RESMULT_a10_b[4]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(4), Y => - \a10_b[4]\); - - \RESMULT_a0_b[7]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(7), Y => - \a0_b[7]\); - - RESMULT_madd_588_0 : XNOR3 - port map(A => \a16_b[7]\, B => \a_i15_b[8]\, C => - \a17_b_i[6]\, Y => N_251); - - \RESMULT_a15_b[1]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(1), Y => - \a15_b[1]\); - - \RESMULT_a0_b[8]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(8), Y => - \a0_b[8]\); - - RESMULT_madd_24_4 : XNOR2 - port map(A => madd_24_4_0, B => N_4, Y => N_9); - - RESMULT_madd_606_ADD_22x22_fast_I198_Y_0 : AX1A - port map(A => N455, B => I159_un1_Y_i, C => - ADD_22x22_fast_I198_Y_0_0, Y => \RESMULT[13]\); - - \REG[15]\ : DFN1E1C0 - port map(D => \RESMULT[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(15)); - - RESMULT_madd_124_m2 : XOR2 - port map(A => N_37, B => N_35, Y => madd_88_0_0); - - \RESMULT_a_i5_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(5), Y => - \a_i5_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I134_Y : OR2 - port map(A => N415, B => I134_un1_Y, Y => N461); - - RESMULT_madd_606_ADD_22x22_fast_I8_P0N : XO1A - port map(A => N_118, B => N_133, C => N_120, Y => N298); - - \REG[3]\ : DFN1E1C0 - port map(D => \RESMULT[3]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(3)); - - RESMULT_madd_606_ADD_22x22_fast_I80_Y : OR2 - port map(A => ADD_22x22_fast_I80_un1_Y, B => N354, Y => - N399); - - RESMULT_madd_606_ADD_22x22_fast_I52_Y : MAJ3 - port map(A => N_72, B => N_87, C => N285, Y => N368); - - RESMULT_madd_606_ADD_22x22_fast_I27_Y : OA1 - port map(A => N_250, B => N_253, C => N325, Y => N343); - - \RESMULT_a_i12_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(12), Y => - \a_i12_b[8]\); - - RESMULT_madd_273_0 : XOR3 - port map(A => N_100, B => madd_268_0_0, C => N_102, Y => - N_119); - - \RESMULT_a10_b[6]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(6), Y => - \a10_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I71_Y : NOR2 - port map(A => N349, B => N345, Y => N390); - - RESMULT_madd_61_2 : XOR2 - port map(A => madd_61_2_0, B => \a4_b[2]\, Y => N_21_i); - - RESMULT_madd_606_ADD_22x22_fast_I199_Y_0 : AX1D - port map(A => I158_un1_Y, B => N453, C => - ADD_22x22_fast_I199_Y_0_0, Y => \RESMULT[14]\); - - \RESMULT_a6_b[5]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(5), Y => - \a6_b[5]\); - - RESMULT_madd_305_2 : XOR3 - port map(A => \a11_b[2]\, B => \a13_b[0]\, C => \a12_b[1]\, - Y => N_121_i); - - \RESMULT_a15_b[3]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(3), Y => - \a15_b[3]\); - - \RESMULT_a3_b[6]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(6), Y => - \a3_b[6]\); - - RESMULT_madd_342_2 : XOR3 - port map(A => \a12_b[2]\, B => \a14_b[0]\, C => \a13_b[1]\, - Y => N_137_i); - - \RESMULT_a5_b[6]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(6), Y => - \a5_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_2 : NOR3C - port map(A => I112_un1_Y, B => ADD_22x22_fast_I172_Y_0, C - => I148_un1_Y, Y => ADD_22x22_fast_I172_Y_2); - - RESMULT_madd_331 : MAJ3 - port map(A => N_122_i, B => N_124, C => N_126, Y => N_144); - - RESMULT_madd_606_ADD_22x22_fast_I5_G0N : NOR2B - port map(A => N_87, B => N_72, Y => N288); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_3 : OR3C - port map(A => N398, B => N390, C => - ADD_22x22_fast_I171_Y_3_tz, Y => ADD_22x22_fast_I171_Y_3); - - RESMULT_madd_606_ADD_22x22_fast_I155_Y_0 : NOR3C - port map(A => I82_un1_Y, B => N356, C => I155_un1_Y_i, Y - => ADD_22x22_fast_I155_Y_0); - - RESMULT_madd_410 : AO18 - port map(A => N_173, B => N_169_i, C => N_171, Y => N_178); - - RESMULT_madd_220 : MAJ3 - port map(A => N_74_i, B => N_76, C => N_78, Y => N_96); - - RESMULT_madd_24_0 : XNOR2 - port map(A => madd_24_0_0, B => N_6, Y => N_11_i); - - RESMULT_madd_606_ADD_22x22_fast_I6_G0N : XA1 - port map(A => N_86, B => N_101, C => N_88, Y => N291); - - RESMULT_madd_416_10 : XOR3 - port map(A => N_156, B => N_154_i, C => N_158, Y => - N_175_i_0); - - \RESMULT_a6_b[6]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(6), Y => - \a6_b[6]\); - - RESMULT_madd_363 : MAJ3 - port map(A => \a9_b[6]\, B => \a8_b[7]\, C => \a_i7_b[8]\, - Y => N_158); - - \RESMULT_a17_b_i[3]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(3), Y => - \a17_b_i[3]\); - - \RESMULT_a8_b[2]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(2), Y => - \a8_b[2]\); - - RESMULT_madd_268_2 : XOR2 - port map(A => madd_268_2_0, B => \a11_b[1]\, Y => N_105_i); - - RESMULT_madd_606_ADD_22x22_fast_I62_Y : AO1 - port map(A => N274, B => N_12, C => N273, Y => N378); - - \REG[10]\ : DFN1E1C0 - port map(D => \RESMULT[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(10)); - - RESMULT_madd_606_ADD_22x22_fast_I135_un1_Y : OR2B - port map(A => N418, B => N_12, Y => I135_un1_Y_i); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_3_tz : OR2 - port map(A => N449, B => ADD_22x22_fast_I170_un1_Y_0, Y => - ADD_22x22_fast_I170_Y_3_tz); - - RESMULT_madd_194_0 : XNOR3 - port map(A => N_83, B => N_81, C => N_68, Y => N_85); - - RESMULT_madd_606_ADD_22x22_fast_I81_Y : OR3C - port map(A => N307, B => N310, C => N359, Y => N400); - - \RESMULT_a11_b[6]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(6), Y => - \a11_b[6]\); - - \REG[12]\ : DFN1E1C0 - port map(D => \RESMULT[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(12)); - - \RESMULT_a11_b[3]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(3), Y => - \a11_b[3]\); - - RESMULT_madd_55 : MAJ3 - port map(A => \a3_b[3]\, B => \a1_b[5]\, C => \a2_b[4]\, Y - => N_24); - - \RESMULT_a_i4_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(4), Y => - \a_i4_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I6_P0N : XO1 - port map(A => N_86, B => N_101, C => N_88, Y => N292); - - RESMULT_madd_567 : AO13 - port map(A => N_232, B => N_230_i, C => N_237, Y => N_242); - - RESMULT_madd_421_0 : XOR3 - port map(A => N_179, B => madd_416_0_0, C => N_166, Y => - N_183); - - \RESMULT_a_i11_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(11), Y => - \a_i11_b[8]\); - - RESMULT_madd_342_12 : XNOR3 - port map(A => N_130, B => N_143_i, C => N_128, Y => N_147); - - RESMULT_madd_467 : MAJ3 - port map(A => \a15_b[3]\, B => \a16_b[2]\, C => - \a17_b_i[1]\, Y => N_202); - - RESMULT_madd_383 : AO13 - port map(A => N_148, B => N_161_i, C => N_163, Y => N_166); - - RESMULT_madd_606_ADD_22x22_fast_I170_un1_Y_0 : NOR3C - port map(A => N404, B => N412, C => N419, Y => - ADD_22x22_fast_I170_un1_Y_0); - - RESMULT_madd_379_0 : XOR3 - port map(A => N_163, B => N_161_i, C => N_148, Y => N_165); - - RESMULT_madd_606_ADD_22x22_fast_I46_Y : AO1 - port map(A => N298, B => N294, C => N297, Y => N362); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_1 : AOI1B - port map(A => N346, B => N343, C => ADD_22x22_fast_I170_Y_0, - Y => ADD_22x22_fast_I170_Y_1); - - RESMULT_madd_606_ADD_22x22_fast_I157_un1_Y_0 : NOR3B - port map(A => N373, B => N421, C => N369, Y => - ADD_22x22_fast_I157_un1_Y_0); - - \REG[11]\ : DFN1E1C0 - port map(D => \RESMULT[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(11)); - - RESMULT_madd_587 : AO18 - port map(A => N_242, B => N_247, C => N_240_i, Y => N_250); - - GND_i : GND - port map(Y => \GND\); - - \RESMULT_a7_b[3]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(3), Y => - \a7_b[3]\); - - \RESMULT_a8_b[6]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(6), Y => - \a8_b[6]\); - - \RESMULT_a3_b[3]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(3), Y => - \a3_b[3]\); - - RESMULT_madd_231_10 : XOR3 - port map(A => N_76, B => N_74_i, C => N_78, Y => N_95_i); - - RESMULT_madd_157_4 : XOR3 - port map(A => \a5_b[4]\, B => \a6_b[3]\, C => \a4_b[5]\, Y - => N_59_i); - - RESMULT_madd_487 : MAJ3 - port map(A => N_203_i, B => N_192, C => N_194, Y => N_210); - - RESMULT_madd_157_9 : XNOR3 - port map(A => N_44, B => \a_i0_b[8]\, C => N_46, Y => N_63); - - RESMULT_madd_606_ADD_22x22_fast_I206_Y_0_0 : XNOR2 - port map(A => N_243, B => N_236, Y => - ADD_22x22_fast_I206_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I126_un1_Y : NOR3B - port map(A => N361, B => N413, C => N365, Y => I126_un1_Y); - - RESMULT_madd_547 : AO13 - port map(A => N_220, B => N_229_i, C => N_231, Y => N_234); - - \RESMULT_a5_b[7]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(7), Y => - \a5_b[7]\); - - \REG[20]\ : DFN1E1C0 - port map(D => \RESMULT[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(20)); - - RESMULT_madd_606_ADD_22x22_fast_I70_un1_Y : AO1D - port map(A => N318, B => ADD_22x22_fast_I32_un1_Y, C => - N345, Y => I70_un1_Y); - - RESMULT_madd_60 : AO18 - port map(A => N_16, B => \a0_b[6]\, C => N_14, Y => N_26); - - \RESMULT_a10_b[0]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(0), Y => - \a10_b[0]\); - - \REG[22]\ : DFN1E1C0 - port map(D => \RESMULT[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult, Q => MULTout(22)); - - RESMULT_madd_447 : MIN3 - port map(A => N_187, B => N_174, C => N_185, Y => N_194); - - RESMULT_madd_502 : MIN3 - port map(A => \a15_b[4]\, B => \a16_b[3]\, C => - \a17_b_i[2]\, Y => N_216); - - \RESMULT_a17_b_i[0]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(0), Y => - \a17_b_i[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I92_Y : OR2 - port map(A => N366, B => I92_un1_Y, Y => N411); - - RESMULT_madd_606_ADD_22x22_fast_I205_Y_0_0 : AX1B - port map(A => madd_301, B => madd_527_0, C => N_235, Y => - ADD_22x22_fast_I205_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I84_Y : AO1 - port map(A => N362, B => N359, C => N358, Y => N403); - - RESMULT_madd_194_12 : XOR3 - port map(A => N_79, B => N_64_i, C => N_66, Y => N_83); - - \RESMULT_a15_b[0]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(0), Y => - \a15_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I190_Y_0 : XOR2 - port map(A => ADD_22x22_fast_I190_Y_0_0, B => N_12, Y => - \RESMULT[5]\); - - \RESMULT_a14_b[0]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(0), Y => - \a14_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I201_Y_0 : AX1A - port map(A => N449, B => I156_un1_Y_i, C => - ADD_22x22_fast_I201_Y_0_0, Y => \RESMULT[16]\); - - RESMULT_madd_606_ADD_22x22_fast_I155_un1_Y_0 : OA1A - port map(A => I135_un1_Y_i, B => N417, C => N410, Y => - ADD_22x22_fast_I155_un1_Y_0); - - \REG[8]\ : DFN1E1C0 - port map(D => \RESMULT[8]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(8)); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_0 : OA1C - port map(A => N350, B => N347, C => N346, Y => - ADD_22x22_fast_I172_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I11_G0N : NOR3B - port map(A => N_165, B => N_183, C => N_150, Y => N306); - - \RESMULT_a16_b[3]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(3), Y => - \a16_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I153_Y : NOR3 - port map(A => I118_un1_Y, B => N397, C => I153_un1_Y, Y => - N544); - - RESMULT_madd_606_ADD_22x22_fast_I191_Y_0 : XOR3 - port map(A => N_29, B => N_27, C => N378, Y => \RESMULT[6]\); - - \RESMULT_a5_b[3]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(3), Y => - \a5_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I38_Y : AO1 - port map(A => N310, B => N306, C => N309, Y => N354); - - RESMULT_madd_606_ADD_22x22_fast_I35_Y : NOR2B - port map(A => N316, B => N313, Y => N351); - - RESMULT_madd_274 : XA1 - port map(A => N_100, B => madd_268_0_0, C => N_102, Y => - N_120); - - RESMULT_madd_606_ADD_22x22_fast_I56_Y : MAJ3 - port map(A => N_53, B => N_55, C => N279, Y => N372); - - RESMULT_madd_279 : MAJ3 - port map(A => \a13_b[0]\, B => \a11_b[2]\, C => \a12_b[1]\, - Y => N_122_i); - - RESMULT_madd_606_ADD_22x22_fast_I10_G0N : NOR2B - port map(A => N_167, B => N_152, Y => N303); - - \REG[21]\ : DFN1E1C0 - port map(D => \RESMULT[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult, Q => MULTout(21)); - - RESMULT_madd_606_ADD_22x22_fast_I15_G0N : OA1 - port map(A => madd_301, B => madd_527_0, C => N_235, Y => - N318); - - RESMULT_madd_493_12 : XOR3 - port map(A => N_207, B => N_205, C => N_196, Y => N_211); - - RESMULT_madd_321 : MIN3 - port map(A => \a11_b[3]\, B => \a9_b[5]\, C => \a10_b[4]\, - Y => N_140); - - RESMULT_madd_342_7 : XNOR3 - port map(A => \a_i6_b[8]\, B => \a8_b[6]\, C => \a7_b[7]\, - Y => N_141); - - RESMULT_madd_432 : MAJ3 - port map(A => \a15_b[2]\, B => \a13_b[4]\, C => \a14_b[3]\, - Y => N_188_i); - - RESMULT_madd_268_7 : XNOR2 - port map(A => madd_268_7_0, B => \a_i4_b[8]\, Y => N_109); - - \REG[16]\ : DFN1E1C0 - port map(D => \RESMULT[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(16)); - - RESMULT_madd_23 : MAJ3 - port map(A => \a1_b[3]\, B => N_4, C => \a0_b[4]\, Y => - N_10); - - \RESMULT_a14_b[4]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(4), Y => - \a14_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I82_un1_Y : OR2 - port map(A => N360, B => N357, Y => I82_un1_Y); - - RESMULT_madd_532 : MIN3 - port map(A => \a15_b[5]\, B => \a16_b[4]\, C => - \a17_b_i[3]\, Y => N_228); - - RESMULT_madd_24_2 : XOR2 - port map(A => madd_24_2_0, B => \a3_b[1]\, Y => N_7_i); - - \RESMULT_a16_b[4]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(4), Y => - \a16_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I79_Y : NOR2 - port map(A => N357, B => N353, Y => N398); - - RESMULT_madd_606_ADD_22x22_fast_I17_P0N : OR2 - port map(A => N_249, B => N_244, Y => N325); - - RESMULT_madd_305_12 : XNOR3 - port map(A => N_114, B => N_127_i, C => N_112, Y => N_131); - - RESMULT_madd_543_4 : XOR3 - port map(A => \a13_b[7]\, B => \a14_b[6]\, C => - \a_i12_b[8]\, Y => N_229_i); - - \RESMULT_a14_b[3]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(3), Y => - \a14_b[3]\); - - \RESMULT_a_i6_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(6), Y => - \a_i6_b[8]\); - - \REG[4]\ : DFN1E1C0 - port map(D => \RESMULT[4]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(4)); - - \REG[13]\ : DFN1E1C0 - port map(D => \RESMULT[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(13)); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0 : AX1E - port map(A => ADD_22x22_fast_I170_Y_3, B => - ADD_22x22_fast_I170_Y_2, C => ADD_22x22_fast_I209_Y_0_2, - Y => \RESMULT[24]\); - - RESMULT_madd_336 : AO18 - port map(A => N_141, B => N_137_i, C => N_139, Y => N_146); - - RESMULT_madd_215 : MAJ3 - port map(A => \a5_b[6]\, B => \a4_b[7]\, C => \a_i3_b[8]\, - Y => N_94); - - RESMULT_madd_416_2 : XOR3 - port map(A => \a15_b[1]\, B => \a16_b[0]\, C => \a14_b[2]\, - Y => N_169_i); - - RESMULT_madd_606_ADD_22x22_fast_I32_un1_Y : NOR3B - port map(A => N_225, B => N319, C => N_214, Y => - ADD_22x22_fast_I32_un1_Y); - - RESMULT_madd_44_0 : XNOR2 - port map(A => N_17, B => N_10, Y => N_19); - - \RESMULT_a16_b[2]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(2), Y => - \a16_b[2]\); - - RESMULT_madd_341 : MAJ3 - port map(A => N_143_i, B => N_128, C => N_130, Y => N_148); - - \RESMULT_a17_b_i[5]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(5), Y => - \a17_b_i[5]\); - - RESMULT_madd_568_2 : XOR3 - port map(A => \a16_b[5]\, B => \a15_b[6]\, C => - \a17_b_i[4]\, Y => N_237); - - \RESMULT_a7_b[6]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(6), Y => - \a7_b[6]\); - - RESMULT_madd_305_7 : XNOR3 - port map(A => \a6_b[7]\, B => \a7_b[6]\, C => \a_i5_b[8]\, - Y => N_125); - - RESMULT_madd_606_ADD_22x22_fast_I0_P0N : AO1D - port map(A => CO2, B => N_11_i, C => N_19, Y => N274); - - RESMULT_madd_606_ADD_22x22_fast_I2_G0N : XA1A - port map(A => N_28, B => N_39, C => N_30, Y => N279); - - RESMULT_madd_606_ADD_22x22_fast_I89_Y : NOR3C - port map(A => N289, B => N292, C => N363, Y => N408); - - RESMULT_madd_493_6_0 : AX1C - port map(A => alu_coef_s(7), B => alu_sample(11), C => - \a_i10_b[8]\, Y => madd_493_6_0); - - RESMULT_madd_384_0 : XNOR2 - port map(A => N_165, B => N_150, Y => N_167); - - RESMULT_madd_305_0 : XOR3 - port map(A => N_131, B => N_129_i, C => N_116, Y => N_133); - - RESMULT_madd_294 : MAJ3 - port map(A => N_106_i, B => N_108, C => N_110, Y => N_128); - - RESMULT_madd_231_8 : XNOR3 - port map(A => N_91, B => N_89_i, C => N_93, Y => N_97); - - RESMULT_madd_268_2_0 : XOR2 - port map(A => \a12_b[0]\, B => \a10_b[2]\, Y => - madd_268_2_0); - - RESMULT_madd_299 : AO18 - port map(A => N_125, B => N_121_i, C => N_123, Y => N_130); - - RESMULT_madd_368 : AO18 - port map(A => N_142, B => N_138_i, C => N_140, Y => N_160); - - \RESMULT_a11_b[1]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(1), Y => - \a11_b[1]\); - - \REG[7]\ : DFN1E1C0 - port map(D => \RESMULT[7]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(7)); - - RESMULT_madd_24_4_0 : XOR2 - port map(A => \a1_b[3]\, B => \a0_b[4]\, Y => madd_24_4_0); - - RESMULT_madd_606_ADD_22x22_fast_I154_Y_0 : OR2 - port map(A => I120_un1_Y, B => N399, Y => - ADD_22x22_fast_I154_Y_0); - - \RESMULT_a5_b[2]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(2), Y => - \a5_b[2]\); - - RESMULT_madd_405 : MAJ3 - port map(A => N_154_i, B => N_156, C => N_158, Y => N_176); - - \RESMULT_a1_b[5]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(5), Y => - \a1_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_un1_Y : OR3A - port map(A => ADD_22x22_fast_I172_un1_Y_0, B => N392, C => - N400, Y => I172_un1_Y); - - \REG[23]\ : DFN1E1C0 - port map(D => \RESMULT[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult, Q => MULTout(23)); - - RESMULT_madd_606_ADD_22x22_fast_I10_P0N : OR2 - port map(A => N_167, B => N_152, Y => N304); - - RESMULT_madd_210 : MAJ3 - port map(A => \a8_b[3]\, B => \a6_b[5]\, C => \a7_b[4]\, Y - => N_92); - - RESMULT_madd_114 : AO13 - port map(A => N_34, B => N_32_i, C => N_43, Y => N_50); - - \RESMULT_a12_b[0]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(0), Y => - \a12_b[0]\); - - \RESMULT_a_i15_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(15), Y => - \a_i15_b[8]\); - - \RESMULT_a7_b[5]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(5), Y => - \a7_b[5]\); - - RESMULT_madd_379_10 : XOR3 - port map(A => N_142, B => N_138_i, C => N_140, Y => N_159_i); - - RESMULT_madd_39_4 : XOR3 - port map(A => \a0_b[5]\, B => \a2_b[3]\, C => \a1_b[4]\, Y - => N_15_i); - - \REG[0]\ : DFN1E1C0 - port map(D => \RESMULT[0]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult_0, Q => MULTout(0)); - - RESMULT_madd_606_ADD_22x22_fast_I153_un1_Y_0 : NOR3B - port map(A => N361, B => N398, C => N365, Y => - ADD_22x22_fast_I153_un1_Y_0); - - RESMULT_madd_458_9 : XNOR3 - port map(A => N_170, B => \a_i9_b[8]\, C => N_172, Y => - N_191); - - RESMULT_madd_606_ADD_22x22_fast_I101_Y : OR2 - port map(A => N376, B => I101_un1_Y, Y => N421); - - RESMULT_madd_157_11 : XNOR3 - port map(A => N_57, B => N_59_i, C => N_48, Y => N_65_i); - - \REG[5]\ : DFN1E1C0 - port map(D => \RESMULT[5]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(5)); - - RESMULT_madd_606_ADD_22x22_fast_I114_un1_Y_0 : OR2 - port map(A => N353, B => N349, Y => ADD_22x22_fast_I115_Y_0); - - RESMULT_madd_125_0 : AX1 - port map(A => N_28, B => N_39, C => N_51, Y => N_55); - - \RESMULT_a8_b[1]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(1), Y => - \a8_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I96_Y : AO1 - port map(A => N374, B => N371, C => N370, Y => N415); - - RESMULT_madd_124tt_m3 : AO13 - port map(A => N_16, B => N_14, C => \a0_b[6]\, Y => - madd_124tt_m3); - - RESMULT_madd_493_8 : XOR3 - port map(A => N_188_i, B => N_201, C => N_190, Y => N_207); - - \RESMULT_a12_b[6]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(6), Y => - \a12_b[6]\); - - RESMULT_madd_348 : NOR2A - port map(A => N_149, B => N_134, Y => N_152); - - RESMULT_madd_517 : MAJ3 - port map(A => N_215, B => N_206, C => N_217, Y => N_222); - - RESMULT_madd_606_ADD_22x22_fast_I207_Y_0_0 : XOR2 - port map(A => N_249, B => N_244, Y => - ADD_22x22_fast_I207_Y_0_0); - - \RESMULT_a12_b[7]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(7), Y => - \a12_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_2 : NOR3C - port map(A => ADD_22x22_fast_I114_un1_Y, B => - ADD_22x22_fast_I173_Y_0, C => I173_un1_Y_i, Y => - ADD_22x22_fast_I173_Y_2); - - \RESMULT_a12_b[3]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(3), Y => - \a12_b[3]\); - - RESMULT_madd_88_2 : XNOR3 - port map(A => \a5_b[2]\, B => \a7_b[0]\, C => \a6_b[1]\, Y - => N_31); - - RESMULT_madd_523_7 : XNOR3 - port map(A => N_204, B => \a_i11_b[8]\, C => N_202, Y => - N_219); - - RESMULT_madd_422 : XO1 - port map(A => N_179, B => madd_416_0_0, C => N_166, Y => - N_184); - - RESMULT_madd_606_ADD_22x22_fast_I198_Y_0_0 : XNOR3 - port map(A => N_118, B => N_133, C => N_120, Y => - ADD_22x22_fast_I198_Y_0_0); - - RESMULT_madd_523_4_0 : XOR2 - port map(A => \a14_b[5]\, B => \a12_b[7]\, Y => - madd_523_4_0); - - \RESMULT_a4_b[5]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(5), Y => - \a4_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I47_Y : NOR2B - port map(A => N298, B => N295, Y => N363); - - RESMULT_madd_606_ADD_22x22_fast_I110_un1_Y : OR2B - port map(A => N397, B => N390, Y => I110_un1_Y); - - RESMULT_madd_548_0_0 : XOR2 - port map(A => N_222, B => N_233, Y => madd_548_0_0); - - RESMULT_madd_157_0 : XOR3 - port map(A => madd_119_m6, B => N_65_i, C => N_67, Y => - N_69); - - RESMULT_madd_606_ADD_22x22_fast_I78_Y : OAI1 - port map(A => N353, B => N356, C => N352, Y => N397); - - RESMULT_madd_522 : OR2 - port map(A => madd_522_0, B => madd_298, Y => N_224); - - RESMULT_madd_305_8 : XOR3 - port map(A => N_125, B => N_121_i, C => N_123, Y => N_129_i); - - RESMULT_madd_562 : MAJ3 - port map(A => \a14_b[7]\, B => N_228, C => \a_i13_b[8]\, Y - => N_240_i); - - \REG[14]\ : DFN1E1C0 - port map(D => \RESMULT[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(14)); - - \RESMULT_a2_b[6]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(6), Y => - \a2_b[6]\); - - \RESMULT_a0_b[1]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(1), Y => - \a0_b[1]\); - - \RESMULT_a12_b[2]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(2), Y => - \a12_b[2]\); - - RESMULT_madd_157_7 : XOR3 - port map(A => \a3_b[6]\, B => \a2_b[7]\, C => \a_i1_b[8]\, - Y => N_61_i); - - RESMULT_madd_606_ADD_22x22_fast_I11_P0N : AO1A - port map(A => N_150, B => N_165, C => N_183, Y => N307); - - RESMULT_madd_1_605_SUM3_0 : XOR2 - port map(A => CO2, B => N_11_i, Y => \RESMULT[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I157_un1_Y : OR3B - port map(A => N361, B => ADD_22x22_fast_I157_un1_Y_0, C => - N365, Y => I157_un1_Y); - - RESMULT_madd_178 : MAJ3 - port map(A => \a4_b[6]\, B => \a3_b[7]\, C => \a_i2_b[8]\, - Y => N_78); - - RESMULT_madd_326 : MIN3 - port map(A => \a8_b[6]\, B => \a7_b[7]\, C => \a_i6_b[8]\, - Y => N_142); - - RESMULT_madd_482 : AO18 - port map(A => N_190, B => N_201, C => N_188_i, Y => N_208); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_3_tz : OR2B - port map(A => N451, B => ADD_22x22_fast_I171_un1_Y_0, Y => - ADD_22x22_fast_I171_Y_3_tz); - - RESMULT_madd_28 : AO18 - port map(A => N_6, B => N_9, C => N_7_i, Y => N_12); - - RESMULT_madd_606_ADD_22x22_fast_I150_un1_Y : OR3A - port map(A => N455, B => ADD_22x22_fast_I115_Y_0, C => N402, - Y => I150_un1_Y); - - RESMULT_madd_582 : AO13 - port map(A => N_238, B => \a_i14_b[8]\, C => N_245, Y => - N_248); - - RESMULT_madd_543_2 : XNOR3 - port map(A => \a16_b[4]\, B => \a15_b[5]\, C => - \a17_b_i[3]\, Y => N_227_i); - - RESMULT_madd_194_8 : XNOR3 - port map(A => N_77, B => N_73_i, C => N_75, Y => N_81); - - \RESMULT_a17_b_i[1]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(1), Y => - \a17_b_i[1]\); - - \RESMULT_a0_b[4]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(4), Y => - \a0_b[4]\); - - RESMULT_madd_0_s : XOR3 - port map(A => \a0_b[2]\, B => \a2_b[0]\, C => \a1_b[1]\, Y - => N_1_i); - - \RESMULT_a13_b[3]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(3), Y => - \a13_b[3]\); - - RESMULT_madd_442 : MAJ3 - port map(A => \a_i9_b[8]\, B => N_170, C => N_172, Y => - N_192); - - RESMULT_madd_606_ADD_22x22_fast_I90_un1_Y : NOR2A - port map(A => N368, B => N365, Y => I90_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I88_Y : AO1 - port map(A => N366, B => N363, C => N362, Y => N407); - - RESMULT_madd_606_ADD_22x22_fast_I85_Y : NOR2B - port map(A => N363, B => N359, Y => N404); - - RESMULT_madd_542 : MAJ3 - port map(A => N_227_i, B => N_216, C => N_218, Y => N_232); - - RESMULT_madd_522_0_tz_0 : OA1B - port map(A => N_192, B => N_194, C => N_219, Y => - madd_522_0_tz_0); - - RESMULT_madd_606_ADD_22x22_fast_I57_Y : NOR2B - port map(A => N283, B => N280, Y => N373); - - \RESMULT_a4_b[6]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(6), Y => - \a4_b[6]\); - - \RESMULT_a0_b[2]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(2), Y => - \a0_b[2]\); - - RESMULT_madd_157_12 : XOR3 - port map(A => N_63, B => N_61_i, C => N_50, Y => N_67); - - \REG[24]\ : DFN1E1C0 - port map(D => \RESMULT[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult, Q => MULTout(24)); - - RESMULT_madd_606_ADD_22x22_fast_I8_G0N : XA1A - port map(A => N_118, B => N_133, C => N_120, Y => N297); - - RESMULT_madd_199_0 : XNOR2 - port map(A => N_85, B => N_70, Y => N_87); - - RESMULT_madd_50 : MAJ3 - port map(A => \a6_b[0]\, B => \a4_b[2]\, C => \a5_b[1]\, Y - => N_22); - - RESMULT_madd_8 : MAJ3 - port map(A => \a3_b[0]\, B => \a1_b[2]\, C => \a2_b[1]\, Y - => N_4); - - RESMULT_madd_477_0 : NOR3C - port map(A => alu_coef_s(7), B => alu_sample(11), C => - madd_477_0_tz, Y => madd_477_0); - - RESMULT_madd_346 : AO13 - port map(A => N_132, B => N_145_i, C => N_147, Y => N_150); - - RESMULT_madd_262 : AO18 - port map(A => N_109, B => N_105_i, C => N_107, Y => N_114); - - RESMULT_madd_231_7 : XNOR3 - port map(A => \a4_b[7]\, B => \a5_b[6]\, C => \a_i3_b[8]\, - Y => N_93); - - RESMULT_madd_311 : NOR2A - port map(A => N_133, B => N_118, Y => N_136); - - \RESMULT_a3_b[7]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(7), Y => - \a3_b[7]\); - - \RESMULT_a8_b[3]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(3), Y => - \a8_b[3]\); - - RESMULT_madd_173 : MAJ3 - port map(A => \a7_b[3]\, B => \a5_b[5]\, C => \a6_b[4]\, Y - => N_76); - - \RESMULT_a14_b[6]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(6), Y => - \a14_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I4_P0N : XO1 - port map(A => N_69, B => madd_124_m6, C => N_56, Y => N286); - - RESMULT_madd_1_605_SUM2_0 : XOR2 - port map(A => CO1, B => N_5, Y => \RESMULT[3]\); - - RESMULT_madd_194_10 : XNOR3 - port map(A => N_60, B => N_58_i, C => N_62, Y => N_79); - - \RESMULT_a13_b[1]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(1), Y => - \a13_b[1]\); - - \RESMULT_a9_b[2]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(2), Y => - \a9_b[2]\); - - RESMULT_madd_198 : OR2 - port map(A => madd_198_0, B => madd_112, Y => N_86); - - RESMULT_madd_606_ADD_22x22_fast_I201_Y_0_0 : AX1 - port map(A => N_150, B => N_165, C => N_183, Y => - ADD_22x22_fast_I201_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I190_Y_0_0 : AX1B - port map(A => N_11_i, B => CO2, C => N_19, Y => - ADD_22x22_fast_I190_Y_0_0); - - RESMULT_madd_156 : AO13 - port map(A => N_50, B => N_61_i, C => N_63, Y => N_68); - - RESMULT_madd_268_7_0 : XOR2 - port map(A => \a6_b[6]\, B => \a5_b[7]\, Y => madd_268_7_0); - - \RESMULT_a3_b[1]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(1), Y => - \a3_b[1]\); - - RESMULT_madd_268_10 : XOR3 - port map(A => N_92, B => N_90_i, C => N_94, Y => N_111_i); - - RESMULT_madd_342_4 : XNOR3 - port map(A => \a9_b[5]\, B => \a11_b[3]\, C => \a10_b[4]\, - Y => N_139); - - RESMULT_madd_606_ADD_22x22_fast_I7_P0N : OR2 - port map(A => N_119, B => N_104, Y => N295); - - RESMULT_madd_151 : AO13 - port map(A => N_48, B => N_59_i, C => N_57, Y => N_66); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0_0 : AX1A - port map(A => alu_sample(16), B => alu_coef_s(8), C => - \a17_b_i[7]\, Y => ADD_22x22_fast_I209_Y_0_0); - - \RESMULT_a12_b[5]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(5), Y => - \a12_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I206_Y_0 : AX1E - port map(A => I150_un1_Y, B => ADD_22x22_fast_I173_Y_2, C - => ADD_22x22_fast_I206_Y_0_0, Y => \RESMULT[21]\); - - \RESMULT_a17_b_i[4]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(4), Y => - \a17_b_i[4]\); - - RESMULT_madd_234 : NOR2A - port map(A => N_99, B => N_84, Y => madd_133); - - RESMULT_madd_99 : MAJ3 - port map(A => \a8_b[0]\, B => \a6_b[2]\, C => \a7_b[1]\, Y - => N_44); - - RESMULT_madd_425 : NOR3C - port map(A => alu_coef_s(1), B => alu_sample(16), C => - alu_sample(17), Y => madd_240); - - \RESMULT_a16_b[6]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(6), Y => - \a16_b[6]\); - - RESMULT_madd_242 : MAJ3 - port map(A => \a12_b[0]\, B => \a10_b[2]\, C => \a11_b[1]\, - Y => N_106_i); - - \RESMULT_a1_b[3]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(3), Y => - \a1_b[3]\); - - RESMULT_madd_521 : NOR2A - port map(A => N_219, B => N_210, Y => madd_298); - - RESMULT_madd_606_ADD_22x22_fast_I13_G0N : OA1 - port map(A => madd_262, B => madd_462_0, C => N_213, Y => - N312); - - RESMULT_madd_568_6 : XOR3 - port map(A => N_237, B => N_230_i, C => N_232, Y => N_241); - - \RESMULT_a10_b[5]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(5), Y => - \a10_b[5]\); - - RESMULT_madd_124_m6 : MIN3 - port map(A => madd_120_0_0_1, B => madd_124_N_4, C => N_38, - Y => madd_124_m6); - - RESMULT_madd_606_ADD_22x22_fast_I205_Y_0 : AX1B - port map(A => I152_un1_Y, B => ADD_22x22_fast_I152_Y_0, C - => ADD_22x22_fast_I205_Y_0_0, Y => \RESMULT[20]\); - - RESMULT_madd_3 : MAJ3 - port map(A => \a2_b[0]\, B => \a0_b[2]\, C => \a1_b[1]\, Y - => N_2); - - RESMULT_madd_379_4 : XNOR3 - port map(A => \a10_b[5]\, B => \a12_b[3]\, C => \a11_b[4]\, - Y => N_155); - - RESMULT_madd_257 : MAJ3 - port map(A => N_90_i, B => N_92, C => N_94, Y => N_112); - - RESMULT_madd_231_4 : XNOR3 - port map(A => \a6_b[5]\, B => \a8_b[3]\, C => \a7_b[4]\, Y - => N_91); - - RESMULT_madd_115_2 : XNOR3 - port map(A => \a3_b[5]\, B => \a5_b[3]\, C => \a4_b[4]\, Y - => N_45); - - RESMULT_madd_606_ADD_22x22_fast_I14_P0N : OR2A - port map(A => N_214, B => N_225, Y => N316); - - RESMULT_madd_606_ADD_22x22_fast_I200_Y_0 : AX1E - port map(A => I157_un1_Y, B => N451, C => - ADD_22x22_fast_I200_Y_0_0, Y => \RESMULT[15]\); - - \RESMULT_a2_b[1]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(1), Y => - \a2_b[1]\); - - RESMULT_madd_88_7 : XNOR3 - port map(A => \a0_b[7]\, B => \a1_b[6]\, C => N_22, Y => - N_35); - - RESMULT_madd_606_ADD_22x22_fast_I29_Y : AO1C - port map(A => N_243, B => N_236, C => N325, Y => N345); - - RESMULT_madd_606_ADD_22x22_fast_I74_un1_Y : OR2 - port map(A => N352, B => N349, Y => - ADD_22x22_fast_I74_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I43_Y : NOR2B - port map(A => N304, B => N301, Y => N359); - - RESMULT_madd_606_ADD_22x22_fast_I203_Y_0_0 : AX1B - port map(A => madd_262, B => madd_462_0, C => N_213, Y => - ADD_22x22_fast_I203_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I173_un1_Y : OR3A - port map(A => ADD_22x22_fast_I173_un1_Y_0, B => - ADD_22x22_fast_I115_Y_0, C => N402, Y => I173_un1_Y_i); - - RESMULT_madd_523_4 : XNOR2 - port map(A => madd_523_4_0, B => \a13_b[6]\, Y => N_217); - - RESMULT_madd_56_0 : XNOR3 - port map(A => N_14, B => \a0_b[6]\, C => N_16, Y => N_25); - - RESMULT_madd_606_ADD_22x22_fast_I13_P0N : OR3 - port map(A => madd_262, B => N_213, C => madd_462_0, Y => - N313); - - RESMULT_madd_193 : AO13 - port map(A => N_66, B => N_64_i, C => N_79, Y => N_84); - - RESMULT_madd_87 : AO13 - port map(A => N_24, B => N_33_i, C => N_31, Y => N_38); - - \RESMULT_a8_b[5]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(5), Y => - \a8_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I36_Y : AOI1 - port map(A => N313, B => N309, C => N312, Y => N352); - - RESMULT_madd_606_ADD_22x22_fast_I193_Y_0 : XOR3 - port map(A => N_53, B => N_55, C => N419, Y => \RESMULT[8]\); - - RESMULT_madd_1_605_CO2 : OR2B - port map(A => CO1, B => N_5, Y => CO2); - - RESMULT_madd_606_ADD_22x22_fast_I97_Y : NOR2B - port map(A => N375, B => N371, Y => N416); - - \RESMULT_a_i3_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(3), Y => - \a_i3_b[8]\); - - RESMULT_madd_124_m3 : MIN3 - port map(A => N_35, B => madd_124tt_m3, C => N_37, Y => - madd_124_N_4); - - \RESMULT_a16_b[5]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(5), Y => - \a16_b[5]\); - - \RESMULT_a6_b[3]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(3), Y => - \a6_b[3]\); - - \RESMULT_a11_b[2]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(2), Y => - \a11_b[2]\); - - RESMULT_madd_462_0_tz : XO1A - port map(A => N_180, B => madd_458_14_0, C => N_182, Y => - madd_462_0_tz); - - RESMULT_madd_493_2 : XNOR3 - port map(A => \a16_b[2]\, B => \a15_b[3]\, C => - \a17_b_i[1]\, Y => N_201); - - RESMULT_madd_606_ADD_22x22_fast_I130_un1_Y : NOR3A - port map(A => N417, B => N369, C => N365, Y => I130_un1_Y); - - RESMULT_madd_268_0_0 : XOR2 - port map(A => N_113_i, B => N_115, Y => madd_268_0_0); - - \RESMULT_a3_b[5]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(5), Y => - \a3_b[5]\); - - \RESMULT_a2_b[5]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(5), Y => - \a2_b[5]\); - - \RESMULT_a16_b[0]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(0), Y => - \a16_b[0]\); - - RESMULT_madd_457tt_m3 : AO18 - port map(A => N_140, B => N_138_i, C => N_142, Y => - madd_457tt_m3); - - RESMULT_madd_194_2 : XOR3 - port map(A => \a8_b[2]\, B => \a10_b[0]\, C => \a9_b[1]\, Y - => N_73_i); - - RESMULT_madd_457_m6 : MX2C - port map(A => N_191, B => madd_457_N_4, S => madd_458_14_0, - Y => madd_457_m6); - - RESMULT_madd_305_10 : XOR3 - port map(A => N_108, B => N_106_i, C => N_110, Y => N_127_i); - - RESMULT_madd_9_0 : XOR3 - port map(A => N_3, B => \a0_b[3]\, C => N_2, Y => N_5); - - \REG[2]\ : DFN1E1C0 - port map(D => \RESMULT[2]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(2)); - - RESMULT_madd_606_ADD_22x22_fast_I148_un1_Y : OR3A - port map(A => N453, B => N392, C => N400, Y => I148_un1_Y); - - \REG[17]\ : DFN1E1C0 - port map(D => \RESMULT[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => mult_0, Q => MULTout(17)); - - RESMULT_madd_606_ADD_22x22_fast_I53_Y : OR2B - port map(A => N289, B => N286, Y => N369); - - RESMULT_madd_268_4 : XNOR3 - port map(A => \a7_b[5]\, B => \a9_b[3]\, C => \a8_b[4]\, Y - => N_107); - - RESMULT_madd_231_2_0 : XOR2 - port map(A => \a11_b[0]\, B => \a9_b[2]\, Y => madd_231_2_0); - - RESMULT_madd_606_ADD_22x22_fast_I195_Y_0_0 : XOR2 - port map(A => N_72, B => N_87, Y => - ADD_22x22_fast_I195_Y_0_0); - - RESMULT_madd_512 : MAJ3 - port map(A => \a_i11_b[8]\, B => N_202, C => N_204, Y => - N_220); - - RESMULT_madd_198_0_tz_0 : AO18 - port map(A => N_61_i, B => N_63, C => N_50, Y => - madd_198_0_tz_0); - - RESMULT_madd_606_ADD_22x22_fast_I40_Y : AOI1 - port map(A => N307, B => N303, C => N306, Y => N356); - - RESMULT_madd_606_ADD_22x22_fast_I202_Y_0 : AX1E - port map(A => I122_un1_Y, B => ADD_22x22_fast_I155_Y_0, C - => ADD_22x22_fast_I202_Y_0_0, Y => \RESMULT[17]\); - - RESMULT_madd_120_0_0_1 : XNOR3 - port map(A => N_32_i, B => N_43, C => N_34, Y => - madd_120_0_0_1); - - RESMULT_madd_115_0 : XOR3 - port map(A => N_45, B => madd_115_0_0_1, C => N_36, Y => - N_51); - - RESMULT_madd_115_0_0_1 : XOR3 - port map(A => \a0_b[8]\, B => \a2_b[6]\, C => \a1_b[7]\, Y - => madd_115_0_0_1); - - RESMULT_madd_493_4 : XOR3 - port map(A => \a12_b[6]\, B => \a14_b[4]\, C => \a13_b[5]\, - Y => N_203_i); - - RESMULT_madd_342_0 : XOR3 - port map(A => N_147, B => N_145_i, C => N_132, Y => N_149); - - RESMULT_madd_416_7 : XNOR3 - port map(A => \a9_b[7]\, B => \a10_b[6]\, C => \a_i8_b[8]\, - Y => N_173); - - RESMULT_madd_458_4 : XNOR3 - port map(A => \a13_b[4]\, B => \a15_b[2]\, C => \a14_b[3]\, - Y => N_187); - - \RESMULT_a9_b[6]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(6), Y => - \a9_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I1_P0N : OR2 - port map(A => N_29, B => N_27, Y => N277); - - \RESMULT_a14_b[2]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(2), Y => - \a14_b[2]\); - - RESMULT_madd_119_m3 : MIN3 - port map(A => \a0_b[7]\, B => madd_119tt_m3, C => \a1_b[6]\, - Y => madd_119_N_4); - - RESMULT_madd_523_10 : XNOR3 - port map(A => N_219, B => N_208, C => N_210, Y => N_223); - - RESMULT_madd_316 : MAJ3 - port map(A => \a14_b[0]\, B => \a12_b[2]\, C => \a13_b[1]\, - Y => N_138_i); - - RESMULT_madd_606_ADD_22x22_fast_I192_Y_0_0 : XNOR3 - port map(A => N_28, B => N_39, C => N_30, Y => - ADD_22x22_fast_I192_Y_0_0); - - RESMULT_madd_88_8_0 : XOR2 - port map(A => N_33_i, B => N_31, Y => madd_88_8_0); - - \RESMULT_a14_b[1]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(1), Y => - \a14_b[1]\); - - \RESMULT_a15_b[6]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(6), Y => - \a15_b[6]\); - - RESMULT_madd_342_8 : XOR3 - port map(A => N_141, B => N_137_i, C => N_139, Y => N_145_i); - - \RESMULT_a13_b[4]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(4), Y => - \a13_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I4_G0N : XA1 - port map(A => N_69, B => madd_124_m6, C => N_56, Y => N285); - - \RESMULT_a_i2_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(2), Y => - \a_i2_b[8]\); - - RESMULT_madd_39_2 : XNOR2 - port map(A => madd_39_2_0, B => \a4_b[1]\, Y => N_13); - - \RESMULT_a6_b[2]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(2), Y => - \a6_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I41_Y : OR2B - port map(A => N307, B => N304, Y => N357); - - RESMULT_madd_606_ADD_22x22_fast_I50_Y : AO1 - port map(A => N292, B => N288, C => N291, Y => N366); - - RESMULT_madd_284 : MAJ3 - port map(A => \a10_b[3]\, B => \a8_b[5]\, C => \a9_b[4]\, Y - => N_124); - - RESMULT_madd_606_ADD_22x22_fast_I152_un1_Y_0 : OA1A - port map(A => I132_un1_Y_i, B => N411, C => N404, Y => - ADD_22x22_fast_I152_un1_Y_0); - - RESMULT_madd_289 : MAJ3 - port map(A => \a7_b[6]\, B => \a6_b[7]\, C => \a_i5_b[8]\, - Y => N_126); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0_2 : XOR3 - port map(A => N_252, B => ADD_22x22_fast_I209_Y_0_0, C => - N_254, Y => ADD_22x22_fast_I209_Y_0_2); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_0 : MIN3 - port map(A => N_250, B => N_253, C => N324, Y => - ADD_22x22_fast_I170_Y_0); - - \RESMULT_a3_b[0]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(0), Y => - \a3_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I171_un1_Y_0 : OR3B - port map(A => N361, B => ADD_22x22_fast_I157_un1_Y_0, C => - N365, Y => ADD_22x22_fast_I171_un1_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_2 : AOI1B - port map(A => N395, B => N388, C => ADD_22x22_fast_I170_Y_1, - Y => ADD_22x22_fast_I170_Y_2); - - \RESMULT_a7_b[1]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(1), Y => - \a7_b[1]\); - - RESMULT_madd_24_2_0 : XOR2 - port map(A => \a2_b[2]\, B => \a4_b[0]\, Y => madd_24_2_0); - - RESMULT_madd_606_ADD_22x22_fast_I92_un1_Y : NOR3C - port map(A => N289, B => N292, C => N370, Y => I92_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I114_un1_Y : AO1 - port map(A => N356, B => I82_un1_Y, C => - ADD_22x22_fast_I115_Y_0, Y => ADD_22x22_fast_I114_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_0 : MIN3 - port map(A => N_244, B => N_249, C => N321, Y => - ADD_22x22_fast_I171_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I124_Y : OR2 - port map(A => N403, B => I124_un1_Y, Y => N449); - - \RESMULT_a0_b[6]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(6), Y => - \a0_b[6]\); - - RESMULT_madd_523_2 : XOR3 - port map(A => \a16_b[3]\, B => \a15_b[4]\, C => - \a17_b_i[2]\, Y => N_215); - - RESMULT_madd_77 : MAJ3 - port map(A => \a4_b[3]\, B => \a2_b[5]\, C => \a3_b[4]\, Y - => N_34); - - RESMULT_madd_606_ADD_22x22_fast_I2_P0N : XO1A - port map(A => N_28, B => N_39, C => N_30, Y => N280); - - RESMULT_madd_157_2 : XNOR3 - port map(A => \a7_b[2]\, B => \a9_b[0]\, C => \a8_b[1]\, Y - => N_57); - - RESMULT_madd_606_ADD_22x22_fast_I120_un1_Y : NOR2A - port map(A => N407, B => N400, Y => I120_un1_Y); - - \RESMULT_a2_b[0]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(0), Y => - \a2_b[0]\); - - RESMULT_madd_379_7 : XNOR3 - port map(A => \a8_b[7]\, B => \a9_b[6]\, C => \a_i7_b[8]\, - Y => N_157); - - \RESMULT_a8_b[4]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(4), Y => - \a8_b[4]\); - - RESMULT_madd_461 : XA1A - port map(A => N_180, B => madd_458_14_0, C => N_182, Y => - madd_262); - - \RESMULT_a2_b[3]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(3), Y => - \a2_b[3]\); - - \RESMULT_a17_b_i[6]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(6), Y => - \a17_b_i[6]\); - - \RESMULT_a12_b[1]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(1), Y => - \a12_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I76_Y : AO1 - port map(A => N354, B => N351, C => N350, Y => N395); - - RESMULT_madd_309 : AO13 - port map(A => N_116, B => N_129_i, C => N_131, Y => N_134); - - RESMULT_madd_1_605_SUM0_0 : XOR2 - port map(A => \a1_b[0]\, B => \a0_b[1]\, Y => \RESMULT[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I60_Y : MAJ3 - port map(A => N_27, B => N_29, C => N273, Y => N376); - - RESMULT_madd_606_ADD_22x22_fast_I154_un1_Y : NOR3B - port map(A => N408, B => N461, C => N400, Y => I154_un1_Y); - - \RESMULT_a2_b[2]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(2), Y => - \a2_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I1_G0N : NOR2B - port map(A => N_29, B => N_27, Y => N276); - - RESMULT_madd_415 : MAJ3 - port map(A => N_175_i_0, B => N_160, C => N_162, Y => N_180); - - RESMULT_madd_606_ADD_22x22_fast_I93_Y : NOR3C - port map(A => N289, B => N292, C => N371, Y => N412); - - RESMULT_madd_543_0 : XOR3 - port map(A => N_231, B => N_229_i, C => N_220, Y => N_233); - - RESMULT_madd_119tt_m3 : MAJ3 - port map(A => \a6_b[0]\, B => \a4_b[2]\, C => \a5_b[1]\, Y - => madd_119tt_m3); - - \RESMULT_a3_b[2]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(2), Y => - \a3_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I118_un1_Y : NOR2B - port map(A => N405, B => N398, Y => I118_un1_Y); - - RESMULT_madd_493_11 : XOR3 - port map(A => N_192, B => N_203_i, C => N_194, Y => N_209_i); - - RESMULT_madd_606_ADD_22x22_fast_I44_Y : AOI1 - port map(A => N301, B => N297, C => N300, Y => N360); - - RESMULT_madd_88_4_0 : XOR2 - port map(A => \a2_b[5]\, B => \a4_b[3]\, Y => madd_88_4_0); - - RESMULT_madd_606_ADD_22x22_fast_I173_un1_Y_0 : NOR3C - port map(A => N410, B => N418, C => N_12, Y => - ADD_22x22_fast_I173_un1_Y_0); - - \RESMULT_a9_b[3]\ : OR2B - port map(A => alu_sample(9), B => alu_coef_s(3), Y => - \a9_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_2 : NOR3C - port map(A => I70_un1_Y, B => ADD_22x22_fast_I171_Y_0, C - => I110_un1_Y, Y => ADD_22x22_fast_I171_Y_2); - - RESMULT_madd_606_ADD_22x22_fast_I112_un1_Y : AO1D - port map(A => N354, B => ADD_22x22_fast_I80_un1_Y, C => - N392, Y => I112_un1_Y); - - RESMULT_madd_548_0 : XOR2 - port map(A => madd_548_0_0, B => N_224, Y => N_235); - - RESMULT_madd_606_ADD_22x22_fast_I196_Y_0_0 : XOR3 - port map(A => N_86, B => N_101, C => N_88, Y => - ADD_22x22_fast_I196_Y_0_0); - - \RESMULT_a4_b[4]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(4), Y => - \a4_b[4]\); - - \RESMULT_a15_b[7]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(7), Y => - \a15_b[7]\); - - RESMULT_madd_353 : MAJ3 - port map(A => \a15_b[0]\, B => \a13_b[2]\, C => \a14_b[1]\, - Y => N_154_i); - - \RESMULT_a_i10_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(10), Y => - \a_i10_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I86_Y : AO1B - port map(A => N364, B => N361, C => N360, Y => N405); - - RESMULT_madd_268_12 : XNOR3 - port map(A => N_98, B => N_111_i, C => N_96, Y => N_115); - - RESMULT_madd_1_605_CO1 : NOR3B - port map(A => \a0_b[1]\, B => \a1_b[0]\, C => N_1_i, Y => - CO1); - - RESMULT_madd_4_0 : XNOR3 - port map(A => \a3_b[0]\, B => \a2_b[1]\, C => \a1_b[2]\, Y - => N_3); - - \RESMULT_a17_b_i[2]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(2), Y => - \a17_b_i[2]\); - - RESMULT_madd_379_12 : XNOR3 - port map(A => N_146, B => N_159_i, C => N_144, Y => N_163); - - RESMULT_madd_606_ADD_22x22_fast_I158_un1_Y : NOR3C - port map(A => N408, B => N416, C => N378, Y => I158_un1_Y); - - GND_i_0 : GND - port map(Y => GND_0); - - RESMULT_madd_606_ADD_22x22_fast_I37_Y : OR2B - port map(A => N313, B => N310, Y => N353); - - RESMULT_madd_557 : MIN3 - port map(A => \a15_b[6]\, B => \a16_b[5]\, C => - \a17_b_i[4]\, Y => N_238); - - RESMULT_madd_458_13 : XNOR3 - port map(A => N_178, B => N_189_i, C => N_176, Y => N_195); - - RESMULT_madd_606_ADD_22x22_fast_I101_un1_Y : NOR2B - port map(A => N377, B => N_12, Y => I101_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I159_un1_Y : OR3C - port map(A => N410, B => N418, C => N_12, Y => I159_un1_Y_i); - - RESMULT_madd_457_m3 : MIN3 - port map(A => N_162, B => madd_457tt_m3, C => N_175_i_0, Y - => madd_457_N_4); - - \RESMULT_a1_b[0]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(0), Y => - \a1_b[0]\); - - RESMULT_madd_24_0_0 : XOR2 - port map(A => N_7_i, B => N_9, Y => madd_24_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I152_un1_Y : NOR2B - port map(A => ADD_22x22_fast_I152_un1_Y_0, B => N396, Y => - I152_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I17_G0N : NOR2B - port map(A => N_249, B => N_244, Y => N324); - - RESMULT_madd_606_ADD_22x22_fast_I61_Y : NOR2B - port map(A => N277, B => N274, Y => N377); - - RESMULT_madd_88_0 : XNOR2 - port map(A => madd_88_0_0, B => N_26, Y => N_39); - - RESMULT_madd_606_ADD_22x22_fast_I130_Y : OR2 - port map(A => N409, B => I130_un1_Y, Y => N455); - - RESMULT_madd_522_0 : OA1A - port map(A => madd_522_0_tz_0, B => madd_487_0, C => N_208, - Y => madd_522_0); - - RESMULT_madd_487_0 : AOI1 - port map(A => N_194, B => N_192, C => N_203_i, Y => - madd_487_0); - - \RESMULT_a4_b[1]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(1), Y => - \a4_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I90_Y : OR2 - port map(A => N364, B => I90_un1_Y, Y => N409); - - \RESMULT_a13_b[6]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(6), Y => - \a13_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I54_Y : AO1 - port map(A => N286, B => N282, C => N285, Y => N370); - - \RESMULT_a2_b[7]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(7), Y => - \a2_b[7]\); - - RESMULT_madd_198_0 : OA1 - port map(A => N_83, B => madd_198_0_tz_0, C => N_81, Y => - madd_198_0); - - RESMULT_madd_168 : MAJ3 - port map(A => \a10_b[0]\, B => \a8_b[2]\, C => \a9_b[1]\, Y - => N_74_i); - - RESMULT_madd_606_ADD_22x22_fast_I196_Y_0 : AX1A - port map(A => N413, B => I133_un1_Y_i, C => - ADD_22x22_fast_I196_Y_0_0, Y => \RESMULT[11]\); - - RESMULT_madd_109 : MAJ3 - port map(A => \a2_b[6]\, B => \a0_b[8]\, C => \a1_b[7]\, Y - => N_48); - - \RESMULT_a10_b[2]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(2), Y => - \a10_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I126_Y : NOR2 - port map(A => N405, B => I126_un1_Y, Y => N451); - - \RESMULT_a17_b_i[7]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(7), Y => - \a17_b_i[7]\); - - RESMULT_madd_268_8_0 : XOR2 - port map(A => N_105_i, B => N_109, Y => madd_268_8_0); - - RESMULT_madd_573_0 : XNOR3 - port map(A => \a16_b[6]\, B => \a15_b[7]\, C => - \a17_b_i[5]\, Y => N_245); - - \RESMULT_a7_b[2]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(2), Y => - \a7_b[2]\); - - \RESMULT_a6_b[4]\ : OR2B - port map(A => alu_sample(6), B => alu_coef_s(4), Y => - \a6_b[4]\); - - RESMULT_madd_92 : AO18 - port map(A => N_35, B => N_26, C => N_37, Y => N_40_i); - - RESMULT_madd_416_0_0 : XNOR2 - port map(A => N_177_i, B => N_164, Y => madd_416_0_0); - - RESMULT_madd_400 : MIN3 - port map(A => \a10_b[6]\, B => \a9_b[7]\, C => \a_i8_b[8]\, - Y => N_174); - - RESMULT_madd_390 : MAJ3 - port map(A => \a16_b[0]\, B => \a14_b[2]\, C => \a15_b[1]\, - Y => N_170); - - \RESMULT_a_i7_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(7), Y => - \a_i7_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I49_Y : OR2B - port map(A => N295, B => N292, Y => N365); - - RESMULT_madd_606_ADD_22x22_fast_I12_G0N : XA1B - port map(A => N_182, B => madd_458_0_0, C => N_184, Y => - N309); - - RESMULT_madd_458_2_0 : AX1E - port map(A => alu_coef_s(1), B => alu_sample(16), C => - alu_sample(17), Y => madd_458_2_0); - - RESMULT_madd_568_0 : XOR3 - port map(A => N_241, B => N_239_i, C => N_234, Y => N_243); - - RESMULT_madd_527_0 : OA1 - port map(A => N_212, B => N_223, C => N_221, Y => - madd_527_0); - - RESMULT_madd_526 : NOR2B - port map(A => N_223, B => N_212, Y => madd_301); - - RESMULT_madd_427_1 : OR2A - port map(A => \a17_b_i[0]\, B => madd_240, Y => N_186_1); - - RESMULT_madd_188 : AO18 - port map(A => N_77, B => N_73_i, C => N_75, Y => N_82); - - \RESMULT_a8_b[7]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(7), Y => - \a8_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I15_P0N : OR3 - port map(A => N_235, B => madd_301, C => madd_527_0, Y => - N319); - - RESMULT_madd_543_6 : XNOR3 - port map(A => N_218, B => N_227_i, C => N_216, Y => N_231); - - RESMULT_madd_136 : MAJ3 - port map(A => \a6_b[3]\, B => \a4_b[5]\, C => \a5_b[4]\, Y - => N_60); - - \RESMULT_a3_b[4]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(4), Y => - \a3_b[4]\); - - RESMULT_madd_373 : AO18 - port map(A => N_157, B => N_153_i, C => N_155, Y => N_162); - - RESMULT_madd_578_0 : XOR3 - port map(A => N_245, B => \a_i14_b[8]\, C => N_238, Y => - N_247); - - \RESMULT_a5_b[5]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(5), Y => - \a5_b[5]\); - - \RESMULT_a15_b[5]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(5), Y => - \a15_b[5]\); - - RESMULT_madd_231_2 : XOR2 - port map(A => madd_231_2_0, B => \a10_b[1]\, Y => N_89_i); - - \RESMULT_a5_b[0]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(0), Y => - \a5_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I91_Y : NOR2 - port map(A => N369, B => N365, Y => N410); - - RESMULT_madd_477_0_tz : OR2 - port map(A => \a_i10_b[8]\, B => N_186_1, Y => - madd_477_0_tz); - - RESMULT_madd_131 : MAJ3 - port map(A => \a9_b[0]\, B => \a7_b[2]\, C => \a8_b[1]\, Y - => N_58_i); - - RESMULT_madd_606_ADD_22x22_fast_I128_Y : AO1 - port map(A => N415, B => N408, C => N407, Y => N453); - - RESMULT_madd_577 : MAJ3 - port map(A => \a15_b[7]\, B => \a16_b[6]\, C => - \a17_b_i[5]\, Y => N_246_i); - - RESMULT_madd_305_4 : XNOR3 - port map(A => \a8_b[5]\, B => \a10_b[3]\, C => \a9_b[4]\, Y - => N_123); - - RESMULT_madd_61_4 : XNOR3 - port map(A => \a3_b[3]\, B => \a2_b[4]\, C => \a1_b[5]\, Y - => N_23); - - RESMULT_madd_477 : OR2 - port map(A => madd_477_0, B => madd_271, Y => N_206); - - RESMULT_madd_416_12 : XNOR3 - port map(A => N_162, B => N_175_i_0, C => N_160, Y => N_179); - - RESMULT_madd_606_ADD_22x22_fast_I192_Y_0 : XOR2 - port map(A => ADD_22x22_fast_I192_Y_0_0, B => N421, Y => - \RESMULT[7]\); - - RESMULT_madd_194_7 : XNOR3 - port map(A => \a4_b[6]\, B => \a_i2_b[8]\, C => \a3_b[7]\, - Y => N_77); - - RESMULT_madd_163 : NOR2B - port map(A => madd_124_m6, B => N_69, Y => N_72); - - \RESMULT_a13_b[5]\ : OR2B - port map(A => alu_sample(13), B => alu_coef_s(5), Y => - \a13_b[5]\); - - \RESMULT_a1_b[1]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(1), Y => - \a1_b[1]\); - - RESMULT_madd_237 : NOR2B - port map(A => N_101, B => N_86, Y => N_104); - - RESMULT_madd_593_0 : XOR3 - port map(A => N_246_i, B => N_251, C => N_248, Y => N_253); - - RESMULT_madd_379_2 : XOR3 - port map(A => \a13_b[2]\, B => \a15_b[0]\, C => \a14_b[1]\, - Y => N_153_i); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - RESMULT_madd_606_ADD_22x22_fast_I3_G0N : NOR2B - port map(A => N_55, B => N_53, Y => N282); - - RESMULT_madd_606_ADD_22x22_fast_I134_un1_Y : NOR2B - port map(A => N416, B => N378, Y => I134_un1_Y); - - RESMULT_madd_493_0 : XOR3 - port map(A => madd_457_m6, B => N_209_i, C => N_211, Y => - N_213); - - RESMULT_madd_33 : MIN3 - port map(A => \a5_b[0]\, B => \a3_b[2]\, C => \a4_b[1]\, Y - => N_14); - - RESMULT_madd_606_ADD_22x22_fast_I59_Y : NOR2B - port map(A => N280, B => N277, Y => N375); - - \RESMULT_a8_b[0]\ : OR2B - port map(A => alu_sample(8), B => alu_coef_s(0), Y => - \a8_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I202_Y_0_0 : XNOR3 - port map(A => N_182, B => madd_458_0_0, C => N_184, Y => - ADD_22x22_fast_I202_Y_0_0); - - RESMULT_madd_183 : MAJ3 - port map(A => N_58_i, B => N_60, C => N_62, Y => N_80); - - RESMULT_madd_606_ADD_22x22_fast_I0_G0N : NOR3A - port map(A => N_19, B => N_11_i, C => CO2, Y => N273); - - \RESMULT_a11_b[4]\ : OR2B - port map(A => alu_sample(11), B => alu_coef_s(4), Y => - \a11_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_3 : OR3C - port map(A => N396, B => N388, C => - ADD_22x22_fast_I170_Y_3_tz, Y => ADD_22x22_fast_I170_Y_3); - - RESMULT_madd_606_ADD_22x22_fast_I94_Y : AO1A - port map(A => N369, B => N372, C => N368, Y => N413); - - RESMULT_madd_606_ADD_22x22_fast_I77_Y : NOR3C - port map(A => N307, B => N310, C => N351, Y => N396); - - \RESMULT_a0_b[0]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(0), Y => - \RESMULT[0]\); - - RESMULT_madd_39_0 : XOR2 - port map(A => madd_39_0_0, B => N_8, Y => N_17); - - RESMULT_madd_606_ADD_22x22_fast_I33_Y : OR2B - port map(A => N319, B => N316, Y => N349); - - RESMULT_madd_606_ADD_22x22_fast_I208_Y_0 : AX1E - port map(A => ADD_22x22_fast_I171_Y_3, B => - ADD_22x22_fast_I171_Y_2, C => ADD_22x22_fast_I208_Y_0_0, - Y => \RESMULT[23]\); - - \RESMULT_a_i1_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(1), Y => - \a_i1_b[8]\); - - RESMULT_madd_39_0_0 : XOR2 - port map(A => N_15_i, B => N_13, Y => madd_39_0_0); - - RESMULT_madd_342_10 : XOR3 - port map(A => N_126, B => N_122_i, C => N_124, Y => N_143_i); - - VCC_i : VCC - port map(Y => \VCC\); - - RESMULT_madd_597 : AO13 - port map(A => N_248, B => N_246_i, C => N_251, Y => N_254); - - \RESMULT_a7_b[4]\ : OR2B - port map(A => alu_sample(7), B => alu_coef_s(4), Y => - \a7_b[4]\); - - RESMULT_madd_358 : MAJ3 - port map(A => \a12_b[3]\, B => \a10_b[5]\, C => \a11_b[4]\, - Y => N_156); - - RESMULT_madd_235_0_tz_0 : AO18 - port map(A => N_64_i, B => N_79, C => N_66, Y => - madd_235_0_tz_0); - - \RESMULT_a10_b[1]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(1), Y => - \a10_b[1]\); - - RESMULT_madd_497 : AO13 - port map(A => madd_457_m6, B => N_209_i, C => N_211, Y => - N_214); - - RESMULT_madd_395 : MAJ3 - port map(A => \a13_b[3]\, B => \a11_b[5]\, C => \a12_b[4]\, - Y => N_172); - - \RESMULT_a10_b[3]\ : OR2B - port map(A => alu_sample(10), B => alu_coef_s(3), Y => - \a10_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I208_Y_0_0 : XOR2 - port map(A => N_253, B => N_250, Y => - ADD_22x22_fast_I208_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I69_Y : NOR2A - port map(A => N343, B => N347, Y => N388); - - RESMULT_madd_606_ADD_22x22_fast_I132_un1_Y : OR2B - port map(A => N419, B => N412, Y => I132_un1_Y_i); - - RESMULT_madd_268_8 : XOR2 - port map(A => madd_268_8_0, B => N_107, Y => N_113_i); - - RESMULT_madd_1_605_SUM1_0 : AX1E - port map(A => \a0_b[1]\, B => \a1_b[0]\, C => N_1_i, Y => - \RESMULT[2]\); - - \REG[9]\ : DFN1E1C0 - port map(D => \RESMULT[9]\, CLK => HCLK_c, CLR => HRESETn_c, - E => mult, Q => MULTout(9)); - - RESMULT_madd_606_ADD_22x22_fast_I203_Y_0 : AX1B - port map(A => I154_un1_Y, B => ADD_22x22_fast_I154_Y_0, C - => ADD_22x22_fast_I203_Y_0_0, Y => \RESMULT[18]\); - - \RESMULT_a15_b[2]\ : OR2B - port map(A => alu_sample(15), B => alu_coef_s(2), Y => - \a15_b[2]\); - - RESMULT_madd_379_8 : XOR3 - port map(A => N_155, B => N_153_i, C => N_157, Y => N_161_i); - - RESMULT_madd_82 : MAJ3 - port map(A => \a1_b[6]\, B => N_22, C => \a0_b[7]\, Y => - N_36); - - RESMULT_madd_606_ADD_22x22_fast_I48_Y : MAJ3 - port map(A => N_104, B => N_119, C => N291, Y => N364); - - RESMULT_madd_606_ADD_22x22_fast_I45_Y : NOR2B - port map(A => N301, B => N298, Y => N361); - - \RESMULT_a5_b[4]\ : OR2B - port map(A => alu_sample(5), B => alu_coef_s(4), Y => - \a5_b[4]\); - - RESMULT_madd_416_8 : XOR3 - port map(A => N_171, B => N_169_i, C => N_173, Y => N_177_i); - - RESMULT_madd_606_ADD_22x22_fast_I12_P0N : XAI1A - port map(A => N_182, B => madd_458_0_0, C => N_184, Y => - N310); - - RESMULT_madd_606_ADD_22x22_fast_I195_Y_0 : XOR2 - port map(A => ADD_22x22_fast_I195_Y_0_0, B => N461, Y => - \RESMULT[10]\); - - \RESMULT_a1_b[2]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(2), Y => - \a1_b[2]\); - - RESMULT_madd_126 : NOR3B - port map(A => N_39, B => N_51, C => N_28, Y => N_56); - - \RESMULT_a_i14_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(14), Y => - \a_i14_b[8]\); - - RESMULT_madd_493_6 : XOR2 - port map(A => madd_493_6_0, B => N_186_1, Y => N_205); - - \RESMULT_a14_b[5]\ : OR2B - port map(A => alu_sample(14), B => alu_coef_s(5), Y => - \a14_b[5]\); - - RESMULT_madd_161 : AO13 - port map(A => madd_119_m6, B => N_65_i, C => N_67, Y => - N_70); - - RESMULT_madd_606_ADD_22x22_fast_I194_Y_0_0 : XOR3 - port map(A => N_69, B => madd_124_m6, C => N_56, Y => - ADD_22x22_fast_I194_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I153_un1_Y : OA1A - port map(A => I133_un1_Y_i, B => N413, C => - ADD_22x22_fast_I153_un1_Y_0, Y => I153_un1_Y); - - \RESMULT_a4_b[0]\ : OR2B - port map(A => alu_sample(4), B => alu_coef_s(0), Y => - \a4_b[0]\); - - \RESMULT_a12_b[4]\ : OR2B - port map(A => alu_sample(12), B => alu_coef_s(4), Y => - \a12_b[4]\); - - RESMULT_madd_205 : MAJ3 - port map(A => \a11_b[0]\, B => \a9_b[2]\, C => \a10_b[1]\, - Y => N_90_i); - - RESMULT_madd_13 : AO13 - port map(A => N_2, B => \a0_b[3]\, C => N_3, Y => N_6); - - RESMULT_madd_606_ADD_22x22_fast_I207_Y_0 : AX1E - port map(A => I172_un1_Y, B => ADD_22x22_fast_I172_Y_2, C - => ADD_22x22_fast_I207_Y_0_0, Y => \RESMULT[22]\); - - RESMULT_madd_606_ADD_22x22_fast_I7_G0N : NOR2B - port map(A => N_119, B => N_104, Y => N294); - - RESMULT_madd_606_ADD_22x22_fast_I30_Y : AO13 - port map(A => N318, B => N_243, C => N_236, Y => N346); - - \RESMULT_a_i8_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(8), Y => - \a_i8_b[8]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC is - - port( sample_out_s : out std_logic_vector(17 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_ctrl : in std_logic_vector(2 downto 0); - HCLK_c : in std_logic; - HRESETn_c : in std_logic - ); - -end MAC; - -architecture DEF_ARCH of MAC is - - component MAC_REG_18 - port( alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - OP1_2C_D : out std_logic_vector(17 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MAC_REG_9 - port( alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - OP2_2C_D : out std_logic_vector(8 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MAC_REG_1_4 - port( MACMUX2sel_D : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - MACMUX2sel_D_D : out std_logic - ); - end component; - - component MAC_CONTROLER - port( alu_ctrl : in std_logic_vector(1 downto 0) := (others => 'U'); - MACMUX2sel : out std_logic; - N_4 : out std_logic; - mult : out std_logic; - mult_0 : out std_logic - ); - end component; - - component MAC_MUX - port( OP1_2C_D : in std_logic_vector(17 downto 0) := (others => 'U'); - MULTout : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinB : out std_logic_vector(24 downto 0); - ADDERinA_i : out std_logic_vector(18 to 18); - OP2_2C_D : in std_logic_vector(8 downto 0) := (others => 'U'); - ADDERout : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinA_17 : out std_logic; - ADDERinA_24 : out std_logic; - ADDERinA_23 : out std_logic; - ADDERinA_22 : out std_logic; - ADDERinA_21 : out std_logic; - ADDERinA_20 : out std_logic; - ADDERinA_19 : out std_logic; - ADDERinA_16 : out std_logic; - ADDERinA_15 : out std_logic; - ADDERinA_14 : out std_logic; - ADDERinA_13 : out std_logic; - ADDERinA_12 : out std_logic; - ADDERinA_11 : out std_logic; - ADDERinA_10 : out std_logic; - ADDERinA_9 : out std_logic; - ADDERinA_8 : out std_logic; - ADDERinA_7 : out std_logic; - ADDERinA_6 : out std_logic; - ADDERinA_5 : out std_logic; - ADDERinA_4 : out std_logic; - ADDERinA_3 : out std_logic; - ADDERinA_2 : out std_logic; - ADDERinA_1 : out std_logic; - ADDERinA_0 : out std_logic; - MACMUXsel_D : in std_logic := 'U'; - MACMUXsel_D_1 : in std_logic := 'U'; - MACMUXsel_D_0 : in std_logic := 'U' - ); - end component; - - component MAC_REG_27 - port( MULTout : in std_logic_vector(24 downto 7) := (others => 'U'); - MULTout_D : out std_logic_vector(24 downto 7); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component MAC_REG_1_1 - port( alu_ctrl : in std_logic_vector(0 to 0) := (others => 'U'); - add_D : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - add_D_0 : out std_logic - ); - end component; - - component MAC_REG_1_3 - port( MACMUX2sel : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - MACMUX2sel_D : out std_logic - ); - end component; - - component MAC_REG_1 - port( alu_ctrl : in std_logic_vector(2 to 2) := (others => 'U'); - clr_MAC_D : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - clr_MAC_D_0 : out std_logic - ); - end component; - - component Adder - port( ADDERout : out std_logic_vector(24 downto 0); - ADDERinA_i : in std_logic_vector(18 to 18) := (others => 'U'); - ADDERinB : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinA_0 : in std_logic := 'U'; - ADDERinA_1 : in std_logic := 'U'; - ADDERinA_3 : in std_logic := 'U'; - ADDERinA_5 : in std_logic := 'U'; - ADDERinA_7 : in std_logic := 'U'; - ADDERinA_8 : in std_logic := 'U'; - ADDERinA_15 : in std_logic := 'U'; - ADDERinA_16 : in std_logic := 'U'; - ADDERinA_2 : in std_logic := 'U'; - ADDERinA_14 : in std_logic := 'U'; - ADDERinA_6 : in std_logic := 'U'; - ADDERinA_10 : in std_logic := 'U'; - ADDERinA_4 : in std_logic := 'U'; - ADDERinA_12 : in std_logic := 'U'; - ADDERinA_20 : in std_logic := 'U'; - ADDERinA_11 : in std_logic := 'U'; - ADDERinA_19 : in std_logic := 'U'; - ADDERinA_9 : in std_logic := 'U'; - ADDERinA_13 : in std_logic := 'U'; - ADDERinA_21 : in std_logic := 'U'; - ADDERinA_22 : in std_logic := 'U'; - ADDERinA_24 : in std_logic := 'U'; - ADDERinA_23 : in std_logic := 'U'; - ADDERinA_17 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - clr_MAC_D : in std_logic := 'U'; - add_D : in std_logic := 'U'; - clr_MAC_D_0 : in std_logic := 'U'; - MACMUX2sel_D : in std_logic := 'U'; - add_D_0 : in std_logic := 'U' - ); - end component; - - component MAC_MUX2 - port( MULTout_D : in std_logic_vector(24 downto 7) := (others => 'U'); - ADDERout : in std_logic_vector(24 downto 7) := (others => 'U'); - sample_out_s : out std_logic_vector(17 downto 0); - MACMUX2sel_D_D : in std_logic := 'U' - ); - end component; - - component MAC_REG_1_2 - port( MACMUXsel_D : out std_logic; - MACMUXsel_D_0 : out std_logic; - N_4 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - MACMUXsel_D_1 : out std_logic - ); - end component; - - component Multiplier - port( MULTout : out std_logic_vector(24 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - mult : in std_logic := 'U'; - mult_0 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal MACMUX2sel, N_4, mult, mult_0, \MULTout[0]\, - \MULTout[1]\, \MULTout[2]\, \MULTout[3]\, \MULTout[4]\, - \MULTout[5]\, \MULTout[6]\, \MULTout[7]\, \MULTout[8]\, - \MULTout[9]\, \MULTout[10]\, \MULTout[11]\, \MULTout[12]\, - \MULTout[13]\, \MULTout[14]\, \MULTout[15]\, - \MULTout[16]\, \MULTout[17]\, \MULTout[18]\, - \MULTout[19]\, \MULTout[20]\, \MULTout[21]\, - \MULTout[22]\, \MULTout[23]\, \MULTout[24]\, - \ADDERout[0]\, \ADDERout[1]\, \ADDERout[2]\, - \ADDERout[3]\, \ADDERout[4]\, \ADDERout[5]\, - \ADDERout[6]\, \ADDERout[7]\, \ADDERout[8]\, - \ADDERout[9]\, \ADDERout[10]\, \ADDERout[11]\, - \ADDERout[12]\, \ADDERout[13]\, \ADDERout[14]\, - \ADDERout[15]\, \ADDERout[16]\, \ADDERout[17]\, - \ADDERout[18]\, \ADDERout[19]\, \ADDERout[20]\, - \ADDERout[21]\, \ADDERout[22]\, \ADDERout[23]\, - \ADDERout[24]\, \ADDERinA_i[18]\, \ADDERinB[0]\, - \ADDERinB[1]\, \ADDERinB[2]\, \ADDERinB[3]\, - \ADDERinB[4]\, \ADDERinB[5]\, \ADDERinB[6]\, - \ADDERinB[7]\, \ADDERinB[8]\, \ADDERinB[9]\, - \ADDERinB[10]\, \ADDERinB[11]\, \ADDERinB[12]\, - \ADDERinB[13]\, \ADDERinB[14]\, \ADDERinB[15]\, - \ADDERinB[16]\, \ADDERinB[17]\, \ADDERinB[18]\, - \ADDERinB[19]\, \ADDERinB[20]\, \ADDERinB[21]\, - \ADDERinB[22]\, \ADDERinB[23]\, \ADDERinB[24]\, - \ADDERinA[0]\, \ADDERinA[1]\, \ADDERinA[3]\, - \ADDERinA[5]\, \ADDERinA[7]\, \ADDERinA[8]\, - \ADDERinA[15]\, \ADDERinA[16]\, \ADDERinA[2]\, - \ADDERinA[14]\, \ADDERinA[6]\, \ADDERinA[10]\, - \ADDERinA[4]\, \ADDERinA[12]\, \ADDERinA[20]\, - \ADDERinA[11]\, \ADDERinA[19]\, \ADDERinA[9]\, - \ADDERinA[13]\, \ADDERinA[21]\, \ADDERinA[22]\, - \ADDERinA[24]\, \ADDERinA[23]\, \ADDERinA[17]\, clr_MAC_D, - add_D, clr_MAC_D_0, MACMUX2sel_D, add_D_0, \OP1_2C_D[0]\, - \OP1_2C_D[1]\, \OP1_2C_D[2]\, \OP1_2C_D[3]\, - \OP1_2C_D[4]\, \OP1_2C_D[5]\, \OP1_2C_D[6]\, - \OP1_2C_D[7]\, \OP1_2C_D[8]\, \OP1_2C_D[9]\, - \OP1_2C_D[10]\, \OP1_2C_D[11]\, \OP1_2C_D[12]\, - \OP1_2C_D[13]\, \OP1_2C_D[14]\, \OP1_2C_D[15]\, - \OP1_2C_D[16]\, \OP1_2C_D[17]\, \OP2_2C_D[0]\, - \OP2_2C_D[1]\, \OP2_2C_D[2]\, \OP2_2C_D[3]\, - \OP2_2C_D[4]\, \OP2_2C_D[5]\, \OP2_2C_D[6]\, - \OP2_2C_D[7]\, \OP2_2C_D[8]\, \MULTout_D[7]\, - \MULTout_D[8]\, \MULTout_D[9]\, \MULTout_D[10]\, - \MULTout_D[11]\, \MULTout_D[12]\, \MULTout_D[13]\, - \MULTout_D[14]\, \MULTout_D[15]\, \MULTout_D[16]\, - \MULTout_D[17]\, \MULTout_D[18]\, \MULTout_D[19]\, - \MULTout_D[20]\, \MULTout_D[21]\, \MULTout_D[22]\, - \MULTout_D[23]\, \MULTout_D[24]\, MACMUXsel_D, - MACMUXsel_D_0, MACMUXsel_D_1, MACMUX2sel_D_D, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : MAC_REG_18 - Use entity work.MAC_REG_18(DEF_ARCH); - for all : MAC_REG_9 - Use entity work.MAC_REG_9(DEF_ARCH); - for all : MAC_REG_1_4 - Use entity work.MAC_REG_1_4(DEF_ARCH); - for all : MAC_CONTROLER - Use entity work.MAC_CONTROLER(DEF_ARCH); - for all : MAC_MUX - Use entity work.MAC_MUX(DEF_ARCH); - for all : MAC_REG_27 - Use entity work.MAC_REG_27(DEF_ARCH); - for all : MAC_REG_1_1 - Use entity work.MAC_REG_1_1(DEF_ARCH); - for all : MAC_REG_1_3 - Use entity work.MAC_REG_1_3(DEF_ARCH); - for all : MAC_REG_1 - Use entity work.MAC_REG_1(DEF_ARCH); - for all : Adder - Use entity work.Adder(DEF_ARCH); - for all : MAC_MUX2 - Use entity work.MAC_MUX2(DEF_ARCH); - for all : MAC_REG_1_2 - Use entity work.MAC_REG_1_2(DEF_ARCH); - for all : Multiplier - Use entity work.Multiplier(DEF_ARCH); -begin - - - OP1REG : MAC_REG_18 - port map(alu_sample(17) => alu_sample(17), alu_sample(16) - => alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), - OP1_2C_D(17) => \OP1_2C_D[17]\, OP1_2C_D(16) => - \OP1_2C_D[16]\, OP1_2C_D(15) => \OP1_2C_D[15]\, - OP1_2C_D(14) => \OP1_2C_D[14]\, OP1_2C_D(13) => - \OP1_2C_D[13]\, OP1_2C_D(12) => \OP1_2C_D[12]\, - OP1_2C_D(11) => \OP1_2C_D[11]\, OP1_2C_D(10) => - \OP1_2C_D[10]\, OP1_2C_D(9) => \OP1_2C_D[9]\, OP1_2C_D(8) - => \OP1_2C_D[8]\, OP1_2C_D(7) => \OP1_2C_D[7]\, - OP1_2C_D(6) => \OP1_2C_D[6]\, OP1_2C_D(5) => - \OP1_2C_D[5]\, OP1_2C_D(4) => \OP1_2C_D[4]\, OP1_2C_D(3) - => \OP1_2C_D[3]\, OP1_2C_D(2) => \OP1_2C_D[2]\, - OP1_2C_D(1) => \OP1_2C_D[1]\, OP1_2C_D(0) => - \OP1_2C_D[0]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c); - - GND_i_0 : GND - port map(Y => GND_0); - - OP2REG : MAC_REG_9 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - OP2_2C_D(8) => \OP2_2C_D[8]\, OP2_2C_D(7) => - \OP2_2C_D[7]\, OP2_2C_D(6) => \OP2_2C_D[6]\, OP2_2C_D(5) - => \OP2_2C_D[5]\, OP2_2C_D(4) => \OP2_2C_D[4]\, - OP2_2C_D(3) => \OP2_2C_D[3]\, OP2_2C_D(2) => - \OP2_2C_D[2]\, OP2_2C_D(1) => \OP2_2C_D[1]\, OP2_2C_D(0) - => \OP2_2C_D[0]\, HRESETn_c => HRESETn_c, HCLK_c => - HCLK_c); - - VCC_i : VCC - port map(Y => \VCC\); - - MACMUX2selREG2 : MAC_REG_1_4 - port map(MACMUX2sel_D => MACMUX2sel_D, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, MACMUX2sel_D_D => - MACMUX2sel_D_D); - - MAC_CONTROLER1 : MAC_CONTROLER - port map(alu_ctrl(1) => alu_ctrl(1), alu_ctrl(0) => - alu_ctrl(0), MACMUX2sel => MACMUX2sel, N_4 => N_4, mult - => mult, mult_0 => mult_0); - - MACMUX_inst : MAC_MUX - port map(OP1_2C_D(17) => \OP1_2C_D[17]\, OP1_2C_D(16) => - \OP1_2C_D[16]\, OP1_2C_D(15) => \OP1_2C_D[15]\, - OP1_2C_D(14) => \OP1_2C_D[14]\, OP1_2C_D(13) => - \OP1_2C_D[13]\, OP1_2C_D(12) => \OP1_2C_D[12]\, - OP1_2C_D(11) => \OP1_2C_D[11]\, OP1_2C_D(10) => - \OP1_2C_D[10]\, OP1_2C_D(9) => \OP1_2C_D[9]\, OP1_2C_D(8) - => \OP1_2C_D[8]\, OP1_2C_D(7) => \OP1_2C_D[7]\, - OP1_2C_D(6) => \OP1_2C_D[6]\, OP1_2C_D(5) => - \OP1_2C_D[5]\, OP1_2C_D(4) => \OP1_2C_D[4]\, OP1_2C_D(3) - => \OP1_2C_D[3]\, OP1_2C_D(2) => \OP1_2C_D[2]\, - OP1_2C_D(1) => \OP1_2C_D[1]\, OP1_2C_D(0) => - \OP1_2C_D[0]\, MULTout(24) => \MULTout[24]\, MULTout(23) - => \MULTout[23]\, MULTout(22) => \MULTout[22]\, - MULTout(21) => \MULTout[21]\, MULTout(20) => - \MULTout[20]\, MULTout(19) => \MULTout[19]\, MULTout(18) - => \MULTout[18]\, MULTout(17) => \MULTout[17]\, - MULTout(16) => \MULTout[16]\, MULTout(15) => - \MULTout[15]\, MULTout(14) => \MULTout[14]\, MULTout(13) - => \MULTout[13]\, MULTout(12) => \MULTout[12]\, - MULTout(11) => \MULTout[11]\, MULTout(10) => - \MULTout[10]\, MULTout(9) => \MULTout[9]\, MULTout(8) => - \MULTout[8]\, MULTout(7) => \MULTout[7]\, MULTout(6) => - \MULTout[6]\, MULTout(5) => \MULTout[5]\, MULTout(4) => - \MULTout[4]\, MULTout(3) => \MULTout[3]\, MULTout(2) => - \MULTout[2]\, MULTout(1) => \MULTout[1]\, MULTout(0) => - \MULTout[0]\, ADDERinB(24) => \ADDERinB[24]\, - ADDERinB(23) => \ADDERinB[23]\, ADDERinB(22) => - \ADDERinB[22]\, ADDERinB(21) => \ADDERinB[21]\, - ADDERinB(20) => \ADDERinB[20]\, ADDERinB(19) => - \ADDERinB[19]\, ADDERinB(18) => \ADDERinB[18]\, - ADDERinB(17) => \ADDERinB[17]\, ADDERinB(16) => - \ADDERinB[16]\, ADDERinB(15) => \ADDERinB[15]\, - ADDERinB(14) => \ADDERinB[14]\, ADDERinB(13) => - \ADDERinB[13]\, ADDERinB(12) => \ADDERinB[12]\, - ADDERinB(11) => \ADDERinB[11]\, ADDERinB(10) => - \ADDERinB[10]\, ADDERinB(9) => \ADDERinB[9]\, ADDERinB(8) - => \ADDERinB[8]\, ADDERinB(7) => \ADDERinB[7]\, - ADDERinB(6) => \ADDERinB[6]\, ADDERinB(5) => - \ADDERinB[5]\, ADDERinB(4) => \ADDERinB[4]\, ADDERinB(3) - => \ADDERinB[3]\, ADDERinB(2) => \ADDERinB[2]\, - ADDERinB(1) => \ADDERinB[1]\, ADDERinB(0) => - \ADDERinB[0]\, ADDERinA_i(18) => \ADDERinA_i[18]\, - OP2_2C_D(8) => \OP2_2C_D[8]\, OP2_2C_D(7) => - \OP2_2C_D[7]\, OP2_2C_D(6) => \OP2_2C_D[6]\, OP2_2C_D(5) - => \OP2_2C_D[5]\, OP2_2C_D(4) => \OP2_2C_D[4]\, - OP2_2C_D(3) => \OP2_2C_D[3]\, OP2_2C_D(2) => - \OP2_2C_D[2]\, OP2_2C_D(1) => \OP2_2C_D[1]\, OP2_2C_D(0) - => \OP2_2C_D[0]\, ADDERout(24) => \ADDERout[24]\, - ADDERout(23) => \ADDERout[23]\, ADDERout(22) => - \ADDERout[22]\, ADDERout(21) => \ADDERout[21]\, - ADDERout(20) => \ADDERout[20]\, ADDERout(19) => - \ADDERout[19]\, ADDERout(18) => \ADDERout[18]\, - ADDERout(17) => \ADDERout[17]\, ADDERout(16) => - \ADDERout[16]\, ADDERout(15) => \ADDERout[15]\, - ADDERout(14) => \ADDERout[14]\, ADDERout(13) => - \ADDERout[13]\, ADDERout(12) => \ADDERout[12]\, - ADDERout(11) => \ADDERout[11]\, ADDERout(10) => - \ADDERout[10]\, ADDERout(9) => \ADDERout[9]\, ADDERout(8) - => \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, - ADDERout(6) => \ADDERout[6]\, ADDERout(5) => - \ADDERout[5]\, ADDERout(4) => \ADDERout[4]\, ADDERout(3) - => \ADDERout[3]\, ADDERout(2) => \ADDERout[2]\, - ADDERout(1) => \ADDERout[1]\, ADDERout(0) => - \ADDERout[0]\, ADDERinA_17 => \ADDERinA[17]\, ADDERinA_24 - => \ADDERinA[24]\, ADDERinA_23 => \ADDERinA[23]\, - ADDERinA_22 => \ADDERinA[22]\, ADDERinA_21 => - \ADDERinA[21]\, ADDERinA_20 => \ADDERinA[20]\, - ADDERinA_19 => \ADDERinA[19]\, ADDERinA_16 => - \ADDERinA[16]\, ADDERinA_15 => \ADDERinA[15]\, - ADDERinA_14 => \ADDERinA[14]\, ADDERinA_13 => - \ADDERinA[13]\, ADDERinA_12 => \ADDERinA[12]\, - ADDERinA_11 => \ADDERinA[11]\, ADDERinA_10 => - \ADDERinA[10]\, ADDERinA_9 => \ADDERinA[9]\, ADDERinA_8 - => \ADDERinA[8]\, ADDERinA_7 => \ADDERinA[7]\, - ADDERinA_6 => \ADDERinA[6]\, ADDERinA_5 => \ADDERinA[5]\, - ADDERinA_4 => \ADDERinA[4]\, ADDERinA_3 => \ADDERinA[3]\, - ADDERinA_2 => \ADDERinA[2]\, ADDERinA_1 => \ADDERinA[1]\, - ADDERinA_0 => \ADDERinA[0]\, MACMUXsel_D => MACMUXsel_D, - MACMUXsel_D_1 => MACMUXsel_D_1, MACMUXsel_D_0 => - MACMUXsel_D_0); - - MULToutREG : MAC_REG_27 - port map(MULTout(24) => \MULTout[24]\, MULTout(23) => - \MULTout[23]\, MULTout(22) => \MULTout[22]\, MULTout(21) - => \MULTout[21]\, MULTout(20) => \MULTout[20]\, - MULTout(19) => \MULTout[19]\, MULTout(18) => - \MULTout[18]\, MULTout(17) => \MULTout[17]\, MULTout(16) - => \MULTout[16]\, MULTout(15) => \MULTout[15]\, - MULTout(14) => \MULTout[14]\, MULTout(13) => - \MULTout[13]\, MULTout(12) => \MULTout[12]\, MULTout(11) - => \MULTout[11]\, MULTout(10) => \MULTout[10]\, - MULTout(9) => \MULTout[9]\, MULTout(8) => \MULTout[8]\, - MULTout(7) => \MULTout[7]\, MULTout_D(24) => - \MULTout_D[24]\, MULTout_D(23) => \MULTout_D[23]\, - MULTout_D(22) => \MULTout_D[22]\, MULTout_D(21) => - \MULTout_D[21]\, MULTout_D(20) => \MULTout_D[20]\, - MULTout_D(19) => \MULTout_D[19]\, MULTout_D(18) => - \MULTout_D[18]\, MULTout_D(17) => \MULTout_D[17]\, - MULTout_D(16) => \MULTout_D[16]\, MULTout_D(15) => - \MULTout_D[15]\, MULTout_D(14) => \MULTout_D[14]\, - MULTout_D(13) => \MULTout_D[13]\, MULTout_D(12) => - \MULTout_D[12]\, MULTout_D(11) => \MULTout_D[11]\, - MULTout_D(10) => \MULTout_D[10]\, MULTout_D(9) => - \MULTout_D[9]\, MULTout_D(8) => \MULTout_D[8]\, - MULTout_D(7) => \MULTout_D[7]\, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c); - - GND_i : GND - port map(Y => \GND\); - - addREG : MAC_REG_1_1 - port map(alu_ctrl(0) => alu_ctrl(0), add_D => add_D, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, add_D_0 => - add_D_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - MACMUX2selREG : MAC_REG_1_3 - port map(MACMUX2sel => MACMUX2sel, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, MACMUX2sel_D => MACMUX2sel_D); - - clr_MACREG1 : MAC_REG_1 - port map(alu_ctrl(2) => alu_ctrl(2), clr_MAC_D => clr_MAC_D, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, clr_MAC_D_0 => - clr_MAC_D_0); - - adder_inst : Adder - port map(ADDERout(24) => \ADDERout[24]\, ADDERout(23) => - \ADDERout[23]\, ADDERout(22) => \ADDERout[22]\, - ADDERout(21) => \ADDERout[21]\, ADDERout(20) => - \ADDERout[20]\, ADDERout(19) => \ADDERout[19]\, - ADDERout(18) => \ADDERout[18]\, ADDERout(17) => - \ADDERout[17]\, ADDERout(16) => \ADDERout[16]\, - ADDERout(15) => \ADDERout[15]\, ADDERout(14) => - \ADDERout[14]\, ADDERout(13) => \ADDERout[13]\, - ADDERout(12) => \ADDERout[12]\, ADDERout(11) => - \ADDERout[11]\, ADDERout(10) => \ADDERout[10]\, - ADDERout(9) => \ADDERout[9]\, ADDERout(8) => - \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, ADDERout(6) - => \ADDERout[6]\, ADDERout(5) => \ADDERout[5]\, - ADDERout(4) => \ADDERout[4]\, ADDERout(3) => - \ADDERout[3]\, ADDERout(2) => \ADDERout[2]\, ADDERout(1) - => \ADDERout[1]\, ADDERout(0) => \ADDERout[0]\, - ADDERinA_i(18) => \ADDERinA_i[18]\, ADDERinB(24) => - \ADDERinB[24]\, ADDERinB(23) => \ADDERinB[23]\, - ADDERinB(22) => \ADDERinB[22]\, ADDERinB(21) => - \ADDERinB[21]\, ADDERinB(20) => \ADDERinB[20]\, - ADDERinB(19) => \ADDERinB[19]\, ADDERinB(18) => - \ADDERinB[18]\, ADDERinB(17) => \ADDERinB[17]\, - ADDERinB(16) => \ADDERinB[16]\, ADDERinB(15) => - \ADDERinB[15]\, ADDERinB(14) => \ADDERinB[14]\, - ADDERinB(13) => \ADDERinB[13]\, ADDERinB(12) => - \ADDERinB[12]\, ADDERinB(11) => \ADDERinB[11]\, - ADDERinB(10) => \ADDERinB[10]\, ADDERinB(9) => - \ADDERinB[9]\, ADDERinB(8) => \ADDERinB[8]\, ADDERinB(7) - => \ADDERinB[7]\, ADDERinB(6) => \ADDERinB[6]\, - ADDERinB(5) => \ADDERinB[5]\, ADDERinB(4) => - \ADDERinB[4]\, ADDERinB(3) => \ADDERinB[3]\, ADDERinB(2) - => \ADDERinB[2]\, ADDERinB(1) => \ADDERinB[1]\, - ADDERinB(0) => \ADDERinB[0]\, ADDERinA_0 => \ADDERinA[0]\, - ADDERinA_1 => \ADDERinA[1]\, ADDERinA_3 => \ADDERinA[3]\, - ADDERinA_5 => \ADDERinA[5]\, ADDERinA_7 => \ADDERinA[7]\, - ADDERinA_8 => \ADDERinA[8]\, ADDERinA_15 => - \ADDERinA[15]\, ADDERinA_16 => \ADDERinA[16]\, ADDERinA_2 - => \ADDERinA[2]\, ADDERinA_14 => \ADDERinA[14]\, - ADDERinA_6 => \ADDERinA[6]\, ADDERinA_10 => - \ADDERinA[10]\, ADDERinA_4 => \ADDERinA[4]\, ADDERinA_12 - => \ADDERinA[12]\, ADDERinA_20 => \ADDERinA[20]\, - ADDERinA_11 => \ADDERinA[11]\, ADDERinA_19 => - \ADDERinA[19]\, ADDERinA_9 => \ADDERinA[9]\, ADDERinA_13 - => \ADDERinA[13]\, ADDERinA_21 => \ADDERinA[21]\, - ADDERinA_22 => \ADDERinA[22]\, ADDERinA_24 => - \ADDERinA[24]\, ADDERinA_23 => \ADDERinA[23]\, - ADDERinA_17 => \ADDERinA[17]\, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, clr_MAC_D => clr_MAC_D, add_D => add_D, - clr_MAC_D_0 => clr_MAC_D_0, MACMUX2sel_D => MACMUX2sel_D, - add_D_0 => add_D_0); - - MAC_MUX2_inst : MAC_MUX2 - port map(MULTout_D(24) => \MULTout_D[24]\, MULTout_D(23) - => \MULTout_D[23]\, MULTout_D(22) => \MULTout_D[22]\, - MULTout_D(21) => \MULTout_D[21]\, MULTout_D(20) => - \MULTout_D[20]\, MULTout_D(19) => \MULTout_D[19]\, - MULTout_D(18) => \MULTout_D[18]\, MULTout_D(17) => - \MULTout_D[17]\, MULTout_D(16) => \MULTout_D[16]\, - MULTout_D(15) => \MULTout_D[15]\, MULTout_D(14) => - \MULTout_D[14]\, MULTout_D(13) => \MULTout_D[13]\, - MULTout_D(12) => \MULTout_D[12]\, MULTout_D(11) => - \MULTout_D[11]\, MULTout_D(10) => \MULTout_D[10]\, - MULTout_D(9) => \MULTout_D[9]\, MULTout_D(8) => - \MULTout_D[8]\, MULTout_D(7) => \MULTout_D[7]\, - ADDERout(24) => \ADDERout[24]\, ADDERout(23) => - \ADDERout[23]\, ADDERout(22) => \ADDERout[22]\, - ADDERout(21) => \ADDERout[21]\, ADDERout(20) => - \ADDERout[20]\, ADDERout(19) => \ADDERout[19]\, - ADDERout(18) => \ADDERout[18]\, ADDERout(17) => - \ADDERout[17]\, ADDERout(16) => \ADDERout[16]\, - ADDERout(15) => \ADDERout[15]\, ADDERout(14) => - \ADDERout[14]\, ADDERout(13) => \ADDERout[13]\, - ADDERout(12) => \ADDERout[12]\, ADDERout(11) => - \ADDERout[11]\, ADDERout(10) => \ADDERout[10]\, - ADDERout(9) => \ADDERout[9]\, ADDERout(8) => - \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, - sample_out_s(17) => sample_out_s(17), sample_out_s(16) - => sample_out_s(16), sample_out_s(15) => - sample_out_s(15), sample_out_s(14) => sample_out_s(14), - sample_out_s(13) => sample_out_s(13), sample_out_s(12) - => sample_out_s(12), sample_out_s(11) => - sample_out_s(11), sample_out_s(10) => sample_out_s(10), - sample_out_s(9) => sample_out_s(9), sample_out_s(8) => - sample_out_s(8), sample_out_s(7) => sample_out_s(7), - sample_out_s(6) => sample_out_s(6), sample_out_s(5) => - sample_out_s(5), sample_out_s(4) => sample_out_s(4), - sample_out_s(3) => sample_out_s(3), sample_out_s(2) => - sample_out_s(2), sample_out_s(1) => sample_out_s(1), - sample_out_s(0) => sample_out_s(0), MACMUX2sel_D_D => - MACMUX2sel_D_D); - - MACMUXselREG : MAC_REG_1_2 - port map(MACMUXsel_D => MACMUXsel_D, MACMUXsel_D_0 => - MACMUXsel_D_0, N_4 => N_4, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c, MACMUXsel_D_1 => MACMUXsel_D_1); - - Multiplieri_nst : Multiplier - port map(MULTout(24) => \MULTout[24]\, MULTout(23) => - \MULTout[23]\, MULTout(22) => \MULTout[22]\, MULTout(21) - => \MULTout[21]\, MULTout(20) => \MULTout[20]\, - MULTout(19) => \MULTout[19]\, MULTout(18) => - \MULTout[18]\, MULTout(17) => \MULTout[17]\, MULTout(16) - => \MULTout[16]\, MULTout(15) => \MULTout[15]\, - MULTout(14) => \MULTout[14]\, MULTout(13) => - \MULTout[13]\, MULTout(12) => \MULTout[12]\, MULTout(11) - => \MULTout[11]\, MULTout(10) => \MULTout[10]\, - MULTout(9) => \MULTout[9]\, MULTout(8) => \MULTout[8]\, - MULTout(7) => \MULTout[7]\, MULTout(6) => \MULTout[6]\, - MULTout(5) => \MULTout[5]\, MULTout(4) => \MULTout[4]\, - MULTout(3) => \MULTout[3]\, MULTout(2) => \MULTout[2]\, - MULTout(1) => \MULTout[1]\, MULTout(0) => \MULTout[0]\, - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_sample(17) => alu_sample(17), alu_sample(16) => - alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), mult => - mult, mult_0 => mult_0, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ALU is - - port( alu_ctrl : in std_logic_vector(2 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - sample_out_s : out std_logic_vector(17 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end ALU; - -architecture DEF_ARCH of ALU is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MAC - port( sample_out_s : out std_logic_vector(17 downto 0); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - HCLK_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : MAC - Use entity work.MAC(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \arith.MACinst\ : MAC - port map(sample_out_s(17) => sample_out_s(17), - sample_out_s(16) => sample_out_s(16), sample_out_s(15) - => sample_out_s(15), sample_out_s(14) => - sample_out_s(14), sample_out_s(13) => sample_out_s(13), - sample_out_s(12) => sample_out_s(12), sample_out_s(11) - => sample_out_s(11), sample_out_s(10) => - sample_out_s(10), sample_out_s(9) => sample_out_s(9), - sample_out_s(8) => sample_out_s(8), sample_out_s(7) => - sample_out_s(7), sample_out_s(6) => sample_out_s(6), - sample_out_s(5) => sample_out_s(5), sample_out_s(4) => - sample_out_s(4), sample_out_s(3) => sample_out_s(3), - sample_out_s(2) => sample_out_s(2), sample_out_s(1) => - sample_out_s(1), sample_out_s(0) => sample_out_s(0), - alu_sample(17) => alu_sample(17), alu_sample(16) => - alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_ctrl(2) => alu_ctrl(2), alu_ctrl(1) => alu_ctrl(1), - alu_ctrl(0) => alu_ctrl(0), HCLK_c => HCLK_c, HRESETn_c - => HRESETn_c); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity generic_syncram_2p_8_18_0 is - - port( ram_input : in std_logic_vector(17 downto 0); - counter : in std_logic_vector(7 downto 0); - DIN_REG1_15 : out std_logic; - ram_output_16 : out std_logic; - ram_output_0 : out std_logic; - ram_output_17 : out std_logic; - ram_output_15 : out std_logic; - ram_output_14 : out std_logic; - ram_output_13 : out std_logic; - ram_output_12 : out std_logic; - ram_output_11 : out std_logic; - ram_output_10 : out std_logic; - ram_output_9 : out std_logic; - ram_output_8 : out std_logic; - ram_output_7 : out std_logic; - ram_output_6 : out std_logic; - ram_output_5 : out std_logic; - ram_output_4 : out std_logic; - ram_output_3 : out std_logic; - ram_output_1 : out std_logic; - reg_sample_in : in std_logic_vector(6 downto 5); - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15); - alu_sample_1 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_10 : out std_logic; - ram_write_i : in std_logic; - generic_syncram_2p_8_18_0_VCC : in std_logic; - generic_syncram_2p_8_18_0_GND : in std_logic; - ADD_8x8_medium_area_I30_Y_0 : in std_logic; - ADD_8x8_medium_area_I29_Y_0 : in std_logic; - ADD_8x8_medium_area_I28_Y_0 : in std_logic; - ADD_8x8_medium_area_I27_Y_0 : in std_logic; - ADD_8x8_medium_area_I26_Y_0 : in std_logic; - ADD_8x8_medium_area_I25_Y_0 : in std_logic; - ADD_8x8_medium_area_I24_Y_0 : in std_logic; - ADD_8x8_medium_area_I0_S_0 : in std_logic; - ram_write : in std_logic; - HCLK_c : in std_logic; - alu_sel_input : in std_logic; - I_1_RNI3I3E3 : out std_logic - ); - -end generic_syncram_2p_8_18_0; - -architecture DEF_ARCH of generic_syncram_2p_8_18_0 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component RAM512X18 - generic (MEMORYFILE:string := ""); - - port( RADDR8 : in std_logic := 'U'; - RADDR7 : in std_logic := 'U'; - RADDR6 : in std_logic := 'U'; - RADDR5 : in std_logic := 'U'; - RADDR4 : in std_logic := 'U'; - RADDR3 : in std_logic := 'U'; - RADDR2 : in std_logic := 'U'; - RADDR1 : in std_logic := 'U'; - RADDR0 : in std_logic := 'U'; - WADDR8 : in std_logic := 'U'; - WADDR7 : in std_logic := 'U'; - WADDR6 : in std_logic := 'U'; - WADDR5 : in std_logic := 'U'; - WADDR4 : in std_logic := 'U'; - WADDR3 : in std_logic := 'U'; - WADDR2 : in std_logic := 'U'; - WADDR1 : in std_logic := 'U'; - WADDR0 : in std_logic := 'U'; - WD17 : in std_logic := 'U'; - WD16 : in std_logic := 'U'; - WD15 : in std_logic := 'U'; - WD14 : in std_logic := 'U'; - WD13 : in std_logic := 'U'; - WD12 : in std_logic := 'U'; - WD11 : in std_logic := 'U'; - WD10 : in std_logic := 'U'; - WD9 : in std_logic := 'U'; - WD8 : in std_logic := 'U'; - WD7 : in std_logic := 'U'; - WD6 : in std_logic := 'U'; - WD5 : in std_logic := 'U'; - WD4 : in std_logic := 'U'; - WD3 : in std_logic := 'U'; - WD2 : in std_logic := 'U'; - WD1 : in std_logic := 'U'; - WD0 : in std_logic := 'U'; - RW0 : in std_logic := 'U'; - RW1 : in std_logic := 'U'; - WW0 : in std_logic := 'U'; - WW1 : in std_logic := 'U'; - PIPE : in std_logic := 'U'; - REN : in std_logic := 'U'; - WEN : in std_logic := 'U'; - RCLK : in std_logic := 'U'; - WCLK : in std_logic := 'U'; - RESET : in std_logic := 'U'; - RD17 : out std_logic; - RD16 : out std_logic; - RD15 : out std_logic; - RD14 : out std_logic; - RD13 : out std_logic; - RD12 : out std_logic; - RD11 : out std_logic; - RD10 : out std_logic; - RD9 : out std_logic; - RD8 : out std_logic; - RD7 : out std_logic; - RD6 : out std_logic; - RD5 : out std_logic; - RD4 : out std_logic; - RD3 : out std_logic; - RD2 : out std_logic; - RD1 : out std_logic; - RD0 : out std_logic - ); - end component; - - signal I_5_1, I_4_0_i_0, I_4_1_i_0, I_4_3, I_5_0, - \RADDR_REG1[2]\, \WADDR_REG1[2]\, N_5, I_5_2, I_5_5_0, - I_5_5_1, \RADDR_REG1[6]\, \WADDR_REG1[6]\, I_4_7_i_0, - \RADDR_REG1[4]\, \WADDR_REG1[4]\, I_4_5_i_0, N_7_i_0, - \DIN_REG1[2]\, \DOUT_TMP[2]\, \DOUT_TMP[15]\, - I_3_RNI91FA3, \DOUT_TMP[5]\, \DIN_REG1_RNIVQEG[5]\, - \DIN_REG1[5]\, \DOUT_TMP[6]\, \DIN_REG1_RNI13FG[6]\, - \DIN_REG1[6]\, \WADDR_REG1[0]\, \RADDR_REG1[0]\, - \WADDR_REG1[1]\, \RADDR_REG1[1]\, \WADDR_REG1[3]\, - \RADDR_REG1[3]\, \WADDR_REG1[5]\, \RADDR_REG1[5]\, - \WADDR_REG1[7]\, \RADDR_REG1[7]\, \DIN_REG1[1]\, - \DOUT_TMP[1]\, \DIN_REG1[3]\, \DOUT_TMP[3]\, - \DIN_REG1[4]\, \DOUT_TMP[4]\, \DIN_REG1[7]\, - \DOUT_TMP[7]\, \DIN_REG1[8]\, \DOUT_TMP[8]\, - \DIN_REG1[9]\, \DOUT_TMP[9]\, \DIN_REG1[10]\, - \DOUT_TMP[10]\, \DIN_REG1[11]\, \DOUT_TMP[11]\, - \DIN_REG1[12]\, \DOUT_TMP[12]\, \DIN_REG1[13]\, - \DOUT_TMP[13]\, \DIN_REG1[14]\, \DOUT_TMP[14]\, - \DIN_REG1[17]\, \DOUT_TMP[17]\, \DIN_REG1[0]\, - \DOUT_TMP[0]\, \DIN_REG1[16]\, \DOUT_TMP[16]\, - \DIN_REG1[15]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - DIN_REG1_15 <= \DIN_REG1[15]\; - - rfd_tile_I_1_RNIAE4E3 : MX2 - port map(A => \DIN_REG1[9]\, B => \DOUT_TMP[9]\, S => - N_7_i_0, Y => ram_output_9); - - rfd_tile_I_1_RNI038F3 : MX2 - port map(A => \DIN_REG1[12]\, B => \DOUT_TMP[12]\, S => - N_7_i_0, Y => ram_output_12); - - \rfd_tile_DIN_REG1_RNI13FG[6]\ : MX2 - port map(A => reg_sample_in(6), B => \DIN_REG1[6]\, S => - alu_sel_input, Y => \DIN_REG1_RNI13FG[6]\); - - \rfd_tile_DIN_REG1[9]\ : DFN1 - port map(D => ram_input(9), CLK => HCLK_c, Q => - \DIN_REG1[9]\); - - rfd_tile_I_1_RNI4M3E3 : MX2 - port map(A => \DIN_REG1[3]\, B => \DOUT_TMP[3]\, S => - N_7_i_0, Y => ram_output_3); - - \rfd_tile_RADDR_REG1[5]\ : DFN1 - port map(D => counter(5), CLK => HCLK_c, Q => - \RADDR_REG1[5]\); - - \rfd_tile_WADDR_REG1[6]\ : DFN1 - port map(D => ADD_8x8_medium_area_I29_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[6]\); - - rfd_tile_I_3 : DFN1 - port map(D => ram_write, CLK => HCLK_c, Q => N_5); - - rfd_tile_I_1_RNI2E3E3 : MX2 - port map(A => \DIN_REG1[1]\, B => \DOUT_TMP[1]\, S => - N_7_i_0, Y => ram_output_1); - - rfd_tile_I_1_RNI5Q3E3 : MX2 - port map(A => \DIN_REG1[4]\, B => \DOUT_TMP[4]\, S => - N_7_i_0, Y => ram_output_4); - - \rfd_tile_DIN_REG1[10]\ : DFN1 - port map(D => ram_input(10), CLK => HCLK_c, Q => - \DIN_REG1[10]\); - - \rfd_tile_WADDR_REG1[4]\ : DFN1 - port map(D => ADD_8x8_medium_area_I27_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[4]\); - - \rfd_tile_RADDR_REG1_RNIL9AC[1]\ : XNOR2 - port map(A => \WADDR_REG1[1]\, B => \RADDR_REG1[1]\, Y => - I_4_1_i_0); - - rfd_tile_I_1_RNI1A3E3 : MX2 - port map(A => \DIN_REG1[0]\, B => \DOUT_TMP[0]\, S => - N_7_i_0, Y => ram_output_0); - - rfd_tile_I_3_RNI91FA3 : OR2B - port map(A => alu_sel_input, B => N_7_i_0, Y => - I_3_RNI91FA3); - - VCC_i : VCC - port map(Y => \VCC\); - - \rfd_tile_DIN_REG1[0]\ : DFN1 - port map(D => ram_input(0), CLK => HCLK_c, Q => - \DIN_REG1[0]\); - - \rfd_tile_DIN_REG1[5]\ : DFN1 - port map(D => ram_input(5), CLK => HCLK_c, Q => - \DIN_REG1[5]\); - - \rfd_tile_DIN_REG1[4]\ : DFN1 - port map(D => ram_input(4), CLK => HCLK_c, Q => - \DIN_REG1[4]\); - - \rfd_tile_DIN_REG1[3]\ : DFN1 - port map(D => ram_input(3), CLK => HCLK_c, Q => - \DIN_REG1[3]\); - - \rfd_tile_DIN_REG1[2]\ : DFN1 - port map(D => ram_input(2), CLK => HCLK_c, Q => - \DIN_REG1[2]\); - - \rfd_tile_DIN_REG1[12]\ : DFN1 - port map(D => ram_input(12), CLK => HCLK_c, Q => - \DIN_REG1[12]\); - - \rfd_tile_WADDR_REG1[7]\ : DFN1 - port map(D => ADD_8x8_medium_area_I30_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[7]\); - - rfd_tile_I_3_RNIVS763 : OR2B - port map(A => I_5_2, B => I_5_1, Y => N_7_i_0); - - rfd_tile_I_3_RNI60RF : XA1A - port map(A => \RADDR_REG1[2]\, B => \WADDR_REG1[2]\, C => - N_5, Y => I_5_0); - - rfd_tile_I_1_RNI864E3 : MX2 - port map(A => \DIN_REG1[7]\, B => \DOUT_TMP[7]\, S => - N_7_i_0, Y => ram_output_7); - - \rfd_tile_RADDR_REG1_RNIOBMO[4]\ : XA1A - port map(A => \RADDR_REG1[4]\, B => \WADDR_REG1[4]\, C => - I_4_5_i_0, Y => I_5_5_0); - - rfd_tile_I_1_RNIV28F3 : MX2 - port map(A => \DIN_REG1[11]\, B => \DOUT_TMP[11]\, S => - N_7_i_0, Y => ram_output_11); - - \rfd_tile_DIN_REG1[15]\ : DFN1 - port map(D => ram_input(15), CLK => HCLK_c, Q => - \DIN_REG1[15]\); - - \rfd_tile_RADDR_REG1[0]\ : DFN1 - port map(D => counter(0), CLK => HCLK_c, Q => - \RADDR_REG1[0]\); - - \rfd_tile_WADDR_REG1[5]\ : DFN1 - port map(D => ADD_8x8_medium_area_I28_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[5]\); - - rfd_tile_I_1_RNINIEU3 : MX2 - port map(A => \DOUT_TMP[6]\, B => \DIN_REG1_RNI13FG[6]\, S - => I_3_RNI91FA3, Y => alu_sample_1); - - rfd_tile_I_1_RNI3I3E3 : MX2 - port map(A => \DIN_REG1[2]\, B => \DOUT_TMP[2]\, S => - N_7_i_0, Y => I_1_RNI3I3E3); - - \rfd_tile_RADDR_REG1[2]\ : DFN1 - port map(D => counter(2), CLK => HCLK_c, Q => - \RADDR_REG1[2]\); - - \rfd_tile_DIN_REG1[1]\ : DFN1 - port map(D => ram_input(1), CLK => HCLK_c, Q => - \DIN_REG1[1]\); - - rfd_tile_I_1_RNI5Q2Q3 : MX2 - port map(A => \DOUT_TMP[15]\, B => - reg_sample_in_RNIFA3C(15), S => I_3_RNI91FA3, Y => - alu_sample_10); - - \rfd_tile_RADDR_REG1[3]\ : DFN1 - port map(D => counter(3), CLK => HCLK_c, Q => - \RADDR_REG1[3]\); - - rfd_tile_I_3_RNIUN812 : NOR3C - port map(A => I_5_5_0, B => I_5_5_1, C => I_5_0, Y => I_5_2); - - GND_i : GND - port map(Y => \GND\); - - rfd_tile_I_1_RNI338F3 : MX2 - port map(A => \DIN_REG1[15]\, B => \DOUT_TMP[15]\, S => - N_7_i_0, Y => ram_output_15); - - \rfd_tile_RADDR_REG1_RNIT9BC[5]\ : XNOR2 - port map(A => \WADDR_REG1[5]\, B => \RADDR_REG1[5]\, Y => - I_4_5_i_0); - - \rfd_tile_RADDR_REG1[1]\ : DFN1 - port map(D => counter(1), CLK => HCLK_c, Q => - \RADDR_REG1[1]\); - - \rfd_tile_DIN_REG1_RNIVQEG[5]\ : MX2 - port map(A => reg_sample_in(5), B => \DIN_REG1[5]\, S => - alu_sel_input, Y => \DIN_REG1_RNIVQEG[5]\); - - rfd_tile_I_1_RNI9A4E3 : MX2 - port map(A => \DIN_REG1[8]\, B => \DOUT_TMP[8]\, S => - N_7_i_0, Y => ram_output_8); - - \rfd_tile_DIN_REG1[14]\ : DFN1 - port map(D => ram_input(14), CLK => HCLK_c, Q => - \DIN_REG1[14]\); - - \rfd_tile_RADDR_REG1_RNI15V41[0]\ : NOR3B - port map(A => I_4_0_i_0, B => I_4_1_i_0, C => I_4_3, Y => - I_5_1); - - \rfd_tile_RADDR_REG1_RNIJ1AC[0]\ : XNOR2 - port map(A => \WADDR_REG1[0]\, B => \RADDR_REG1[0]\, Y => - I_4_0_i_0); - - rfd_tile_I_1_RNIU28F3 : MX2 - port map(A => \DIN_REG1[10]\, B => \DOUT_TMP[10]\, S => - N_7_i_0, Y => ram_output_10); - - \rfd_tile_RADDR_REG1[6]\ : DFN1 - port map(D => counter(6), CLK => HCLK_c, Q => - \RADDR_REG1[6]\); - - rfd_tile_I_1_RNI724E3 : MX2C - port map(A => \DIN_REG1[6]\, B => \DOUT_TMP[6]\, S => - N_7_i_0, Y => ram_output_6); - - \rfd_tile_RADDR_REG1_RNI1QBC[7]\ : XNOR2 - port map(A => \WADDR_REG1[7]\, B => \RADDR_REG1[7]\, Y => - I_4_7_i_0); - - \rfd_tile_RADDR_REG1_RNIPPAC[3]\ : XOR2 - port map(A => \WADDR_REG1[3]\, B => \RADDR_REG1[3]\, Y => - I_4_3); - - \rfd_tile_DIN_REG1[8]\ : DFN1 - port map(D => ram_input(8), CLK => HCLK_c, Q => - \DIN_REG1[8]\); - - \rfd_tile_WADDR_REG1[0]\ : DFN1 - port map(D => ADD_8x8_medium_area_I0_S_0, CLK => HCLK_c, Q - => \WADDR_REG1[0]\); - - \rfd_tile_RADDR_REG1[4]\ : DFN1 - port map(D => counter(4), CLK => HCLK_c, Q => - \RADDR_REG1[4]\); - - rfd_tile_I_1_RNI138F3 : MX2 - port map(A => \DIN_REG1[13]\, B => \DOUT_TMP[13]\, S => - N_7_i_0, Y => ram_output_13); - - \rfd_tile_DIN_REG1[6]\ : DFN1 - port map(D => ram_input(6), CLK => HCLK_c, Q => - \DIN_REG1[6]\); - - \rfd_tile_WADDR_REG1[2]\ : DFN1 - port map(D => ADD_8x8_medium_area_I25_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[2]\); - - \rfd_tile_DIN_REG1[11]\ : DFN1 - port map(D => ram_input(11), CLK => HCLK_c, Q => - \DIN_REG1[11]\); - - rfd_tile_I_1_RNILAEU3 : MX2 - port map(A => \DOUT_TMP[5]\, B => \DIN_REG1_RNIVQEG[5]\, S - => I_3_RNI91FA3, Y => alu_sample_0); - - \rfd_tile_WADDR_REG1[3]\ : DFN1 - port map(D => ADD_8x8_medium_area_I26_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[3]\); - - rfd_tile_I_1_RNI438F3 : MX2 - port map(A => \DIN_REG1[16]\, B => \DOUT_TMP[16]\, S => - N_7_i_0, Y => ram_output_16); - - rfd_tile_I_1_RNI238F3 : MX2 - port map(A => \DIN_REG1[14]\, B => \DOUT_TMP[14]\, S => - N_7_i_0, Y => ram_output_14); - - \rfd_tile_DIN_REG1[13]\ : DFN1 - port map(D => ram_input(13), CLK => HCLK_c, Q => - \DIN_REG1[13]\); - - \rfd_tile_RADDR_REG1_RNI0CNO[6]\ : XA1A - port map(A => \RADDR_REG1[6]\, B => \WADDR_REG1[6]\, C => - I_4_7_i_0, Y => I_5_5_1); - - rfd_tile_I_1_RNI538F3 : MX2 - port map(A => \DIN_REG1[17]\, B => \DOUT_TMP[17]\, S => - N_7_i_0, Y => ram_output_17); - - rfd_tile_I_1 : RAM512X18 - port map(RADDR8 => generic_syncram_2p_8_18_0_GND, RADDR7 - => counter(7), RADDR6 => counter(6), RADDR5 => - counter(5), RADDR4 => counter(4), RADDR3 => counter(3), - RADDR2 => counter(2), RADDR1 => counter(1), RADDR0 => - counter(0), WADDR8 => generic_syncram_2p_8_18_0_GND, - WADDR7 => ADD_8x8_medium_area_I30_Y_0, WADDR6 => - ADD_8x8_medium_area_I29_Y_0, WADDR5 => - ADD_8x8_medium_area_I28_Y_0, WADDR4 => - ADD_8x8_medium_area_I27_Y_0, WADDR3 => - ADD_8x8_medium_area_I26_Y_0, WADDR2 => - ADD_8x8_medium_area_I25_Y_0, WADDR1 => - ADD_8x8_medium_area_I24_Y_0, WADDR0 => - ADD_8x8_medium_area_I0_S_0, WD17 => ram_input(17), WD16 - => ram_input(16), WD15 => ram_input(15), WD14 => - ram_input(14), WD13 => ram_input(13), WD12 => - ram_input(12), WD11 => ram_input(11), WD10 => - ram_input(10), WD9 => ram_input(9), WD8 => ram_input(8), - WD7 => ram_input(7), WD6 => ram_input(6), WD5 => - ram_input(5), WD4 => ram_input(4), WD3 => ram_input(3), - WD2 => ram_input(2), WD1 => ram_input(1), WD0 => - ram_input(0), RW0 => generic_syncram_2p_8_18_0_GND, RW1 - => generic_syncram_2p_8_18_0_VCC, WW0 => - generic_syncram_2p_8_18_0_GND, WW1 => - generic_syncram_2p_8_18_0_VCC, PIPE => - generic_syncram_2p_8_18_0_GND, REN => - generic_syncram_2p_8_18_0_GND, WEN => ram_write_i, RCLK - => HCLK_c, WCLK => HCLK_c, RESET => - generic_syncram_2p_8_18_0_VCC, RD17 => \DOUT_TMP[17]\, - RD16 => \DOUT_TMP[16]\, RD15 => \DOUT_TMP[15]\, RD14 => - \DOUT_TMP[14]\, RD13 => \DOUT_TMP[13]\, RD12 => - \DOUT_TMP[12]\, RD11 => \DOUT_TMP[11]\, RD10 => - \DOUT_TMP[10]\, RD9 => \DOUT_TMP[9]\, RD8 => - \DOUT_TMP[8]\, RD7 => \DOUT_TMP[7]\, RD6 => \DOUT_TMP[6]\, - RD5 => \DOUT_TMP[5]\, RD4 => \DOUT_TMP[4]\, RD3 => - \DOUT_TMP[3]\, RD2 => \DOUT_TMP[2]\, RD1 => \DOUT_TMP[1]\, - RD0 => \DOUT_TMP[0]\); - - \rfd_tile_RADDR_REG1[7]\ : DFN1 - port map(D => counter(7), CLK => HCLK_c, Q => - \RADDR_REG1[7]\); - - \rfd_tile_DIN_REG1[16]\ : DFN1 - port map(D => ram_input(16), CLK => HCLK_c, Q => - \DIN_REG1[16]\); - - \rfd_tile_WADDR_REG1[1]\ : DFN1 - port map(D => ADD_8x8_medium_area_I24_Y_0, CLK => HCLK_c, Q - => \WADDR_REG1[1]\); - - rfd_tile_I_1_RNI6U3E3 : MX2C - port map(A => \DIN_REG1[5]\, B => \DOUT_TMP[5]\, S => - N_7_i_0, Y => ram_output_5); - - \rfd_tile_DIN_REG1[17]\ : DFN1 - port map(D => ram_input(17), CLK => HCLK_c, Q => - \DIN_REG1[17]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \rfd_tile_DIN_REG1[7]\ : DFN1 - port map(D => ram_input(7), CLK => HCLK_c, Q => - \DIN_REG1[7]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ0 is - - port( alu_sample_10 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_1 : out std_logic; - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15); - reg_sample_in : in std_logic_vector(6 downto 5); - ram_output_1 : out std_logic; - ram_output_3 : out std_logic; - ram_output_4 : out std_logic; - ram_output_5 : out std_logic; - ram_output_6 : out std_logic; - ram_output_7 : out std_logic; - ram_output_8 : out std_logic; - ram_output_9 : out std_logic; - ram_output_10 : out std_logic; - ram_output_11 : out std_logic; - ram_output_12 : out std_logic; - ram_output_13 : out std_logic; - ram_output_14 : out std_logic; - ram_output_15 : out std_logic; - ram_output_17 : out std_logic; - ram_output_0 : out std_logic; - ram_output_16 : out std_logic; - DIN_REG1 : out std_logic_vector(15 to 15); - counter : in std_logic_vector(7 downto 0); - ram_input : in std_logic_vector(17 downto 0); - I_1_RNI3I3E3 : out std_logic; - alu_sel_input : in std_logic; - HCLK_c : in std_logic; - ram_write : in std_logic; - ADD_8x8_medium_area_I0_S_0 : in std_logic; - ADD_8x8_medium_area_I24_Y_0 : in std_logic; - ADD_8x8_medium_area_I25_Y_0 : in std_logic; - ADD_8x8_medium_area_I26_Y_0 : in std_logic; - ADD_8x8_medium_area_I27_Y_0 : in std_logic; - ADD_8x8_medium_area_I28_Y_0 : in std_logic; - ADD_8x8_medium_area_I29_Y_0 : in std_logic; - ADD_8x8_medium_area_I30_Y_0 : in std_logic; - syncram_2pZ0_GND : in std_logic; - syncram_2pZ0_VCC : in std_logic; - ram_write_i : in std_logic - ); - -end syncram_2pZ0; - -architecture DEF_ARCH of syncram_2pZ0 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component generic_syncram_2p_8_18_0 - port( ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - counter : in std_logic_vector(7 downto 0) := (others => 'U'); - DIN_REG1_15 : out std_logic; - ram_output_16 : out std_logic; - ram_output_0 : out std_logic; - ram_output_17 : out std_logic; - ram_output_15 : out std_logic; - ram_output_14 : out std_logic; - ram_output_13 : out std_logic; - ram_output_12 : out std_logic; - ram_output_11 : out std_logic; - ram_output_10 : out std_logic; - ram_output_9 : out std_logic; - ram_output_8 : out std_logic; - ram_output_7 : out std_logic; - ram_output_6 : out std_logic; - ram_output_5 : out std_logic; - ram_output_4 : out std_logic; - ram_output_3 : out std_logic; - ram_output_1 : out std_logic; - reg_sample_in : in std_logic_vector(6 downto 5) := (others => 'U'); - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15) := (others => 'U'); - alu_sample_1 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_10 : out std_logic; - ram_write_i : in std_logic := 'U'; - generic_syncram_2p_8_18_0_VCC : in std_logic := 'U'; - generic_syncram_2p_8_18_0_GND : in std_logic := 'U'; - ADD_8x8_medium_area_I30_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I29_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I28_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I27_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I26_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I25_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I24_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I0_S_0 : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - alu_sel_input : in std_logic := 'U'; - I_1_RNI3I3E3 : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : generic_syncram_2p_8_18_0 - Use entity work.generic_syncram_2p_8_18_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \inf.x0\ : generic_syncram_2p_8_18_0 - port map(ram_input(17) => ram_input(17), ram_input(16) => - ram_input(16), ram_input(15) => ram_input(15), - ram_input(14) => ram_input(14), ram_input(13) => - ram_input(13), ram_input(12) => ram_input(12), - ram_input(11) => ram_input(11), ram_input(10) => - ram_input(10), ram_input(9) => ram_input(9), ram_input(8) - => ram_input(8), ram_input(7) => ram_input(7), - ram_input(6) => ram_input(6), ram_input(5) => - ram_input(5), ram_input(4) => ram_input(4), ram_input(3) - => ram_input(3), ram_input(2) => ram_input(2), - ram_input(1) => ram_input(1), ram_input(0) => - ram_input(0), counter(7) => counter(7), counter(6) => - counter(6), counter(5) => counter(5), counter(4) => - counter(4), counter(3) => counter(3), counter(2) => - counter(2), counter(1) => counter(1), counter(0) => - counter(0), DIN_REG1_15 => DIN_REG1(15), ram_output_16 - => ram_output_16, ram_output_0 => ram_output_0, - ram_output_17 => ram_output_17, ram_output_15 => - ram_output_15, ram_output_14 => ram_output_14, - ram_output_13 => ram_output_13, ram_output_12 => - ram_output_12, ram_output_11 => ram_output_11, - ram_output_10 => ram_output_10, ram_output_9 => - ram_output_9, ram_output_8 => ram_output_8, ram_output_7 - => ram_output_7, ram_output_6 => ram_output_6, - ram_output_5 => ram_output_5, ram_output_4 => - ram_output_4, ram_output_3 => ram_output_3, ram_output_1 - => ram_output_1, reg_sample_in(6) => reg_sample_in(6), - reg_sample_in(5) => reg_sample_in(5), - reg_sample_in_RNIFA3C(15) => reg_sample_in_RNIFA3C(15), - alu_sample_1 => alu_sample_1, alu_sample_0 => - alu_sample_0, alu_sample_10 => alu_sample_10, ram_write_i - => ram_write_i, generic_syncram_2p_8_18_0_VCC => - syncram_2pZ0_VCC, generic_syncram_2p_8_18_0_GND => - syncram_2pZ0_GND, ADD_8x8_medium_area_I30_Y_0 => - ADD_8x8_medium_area_I30_Y_0, ADD_8x8_medium_area_I29_Y_0 - => ADD_8x8_medium_area_I29_Y_0, - ADD_8x8_medium_area_I28_Y_0 => - ADD_8x8_medium_area_I28_Y_0, ADD_8x8_medium_area_I27_Y_0 - => ADD_8x8_medium_area_I27_Y_0, - ADD_8x8_medium_area_I26_Y_0 => - ADD_8x8_medium_area_I26_Y_0, ADD_8x8_medium_area_I25_Y_0 - => ADD_8x8_medium_area_I25_Y_0, - ADD_8x8_medium_area_I24_Y_0 => - ADD_8x8_medium_area_I24_Y_0, ADD_8x8_medium_area_I0_S_0 - => ADD_8x8_medium_area_I0_S_0, ram_write => ram_write, - HCLK_c => HCLK_c, alu_sel_input => alu_sel_input, - I_1_RNI3I3E3 => I_1_RNI3I3E3); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity RAM_CTRLR_v2 is - - port( ram_input : in std_logic_vector(17 downto 0); - DIN_REG1 : out std_logic_vector(15 to 15); - ram_output_16 : out std_logic; - ram_output_0 : out std_logic; - ram_output_17 : out std_logic; - ram_output_15 : out std_logic; - ram_output_14 : out std_logic; - ram_output_13 : out std_logic; - ram_output_12 : out std_logic; - ram_output_11 : out std_logic; - ram_output_10 : out std_logic; - ram_output_9 : out std_logic; - ram_output_8 : out std_logic; - ram_output_7 : out std_logic; - ram_output_6 : out std_logic; - ram_output_5 : out std_logic; - ram_output_4 : out std_logic; - ram_output_3 : out std_logic; - ram_output_1 : out std_logic; - reg_sample_in : in std_logic_vector(6 downto 5); - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15); - alu_sample_1 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_10 : out std_logic; - waddr_previous : in std_logic_vector(1 downto 0); - ram_write_i : in std_logic; - RAM_CTRLR_v2_VCC : in std_logic; - RAM_CTRLR_v2_GND : in std_logic; - ram_write : in std_logic; - alu_sel_input : in std_logic; - I_1_RNI3I3E3 : out std_logic; - raddr_add1 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - raddr_rst : in std_logic - ); - -end RAM_CTRLR_v2; - -architecture DEF_ARCH of RAM_CTRLR_v2 is - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component syncram_2pZ0 - port( alu_sample_10 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_1 : out std_logic; - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15) := (others => 'U'); - reg_sample_in : in std_logic_vector(6 downto 5) := (others => 'U'); - ram_output_1 : out std_logic; - ram_output_3 : out std_logic; - ram_output_4 : out std_logic; - ram_output_5 : out std_logic; - ram_output_6 : out std_logic; - ram_output_7 : out std_logic; - ram_output_8 : out std_logic; - ram_output_9 : out std_logic; - ram_output_10 : out std_logic; - ram_output_11 : out std_logic; - ram_output_12 : out std_logic; - ram_output_13 : out std_logic; - ram_output_14 : out std_logic; - ram_output_15 : out std_logic; - ram_output_17 : out std_logic; - ram_output_0 : out std_logic; - ram_output_16 : out std_logic; - DIN_REG1 : out std_logic_vector(15 to 15); - counter : in std_logic_vector(7 downto 0) := (others => 'U'); - ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - I_1_RNI3I3E3 : out std_logic; - alu_sel_input : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - ADD_8x8_medium_area_I0_S_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I24_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I25_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I26_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I27_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I28_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I29_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I30_Y_0 : in std_logic := 'U'; - syncram_2pZ0_GND : in std_logic := 'U'; - syncram_2pZ0_VCC : in std_logic := 'U'; - ram_write_i : in std_logic := 'U' - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_TMP[0]\, \counter[1]_net_1\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, \counter[4]_net_1\, - \DWACT_ADD_CI_0_g_array_12[0]\, \counter[2]_net_1\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, \counter[6]_net_1\, - ADD_8x8_medium_area_I20_Y_0, \counter[5]_net_1\, N_5_i, - ADD_8x8_medium_area_I20_un1_Y_0, N125_i, - ADD_8x8_medium_area_I13_Y_0, \counter[3]_net_1\, - ADD_8x8_medium_area_I13_un1_Y_0, - ADD_8x8_medium_area_I30_Y_0, \counter[7]_net_1\, N149, - ADD_8x8_medium_area_I29_Y_0, N147, - ADD_8x8_medium_area_I27_Y_0, N145_i, N135_i, - ADD_8x8_medium_area_I24_Y_0, N116, - ADD_8x8_medium_area_I25_Y_0, ADD_8x8_medium_area_I28_Y_0, - N124, \counter[0]_net_1\, N120, - ADD_8x8_medium_area_I0_S_0, ADD_8x8_medium_area_I26_Y_0, - N121, \counter_3[7]\, I_34, \counter_3[6]\, I_30, - \counter_3[5]\, I_33, \counter_3[4]\, I_28, - \counter_3[3]\, I_31, \counter_3[2]\, I_32, - \counter_3[1]\, I_27, \counter_3[0]\, - \DWACT_ADD_CI_0_partial_sum[0]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : syncram_2pZ0 - Use entity work.syncram_2pZ0(DEF_ARCH); -begin - - - un1_counter_1_ADD_8x8_medium_area_I20_Y_0 : OA1 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - C => N_5_i, Y => ADD_8x8_medium_area_I20_Y_0); - - un1_counter_I_45 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => - \counter[6]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_2[0]\); - - un1_counter_I_31 : XOR2 - port map(A => \counter[3]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_31); - - un1_counter_I_36 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - un1_counter_1_ADD_8x8_medium_area_I12_Y : MX2B - port map(A => N116, B => N_5_i, S => \counter[1]_net_1\, Y - => N135_i); - - un1_counter_1_ADD_8x8_medium_area_I13_Y_0 : OAI1 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - C => N_5_i, Y => ADD_8x8_medium_area_I13_Y_0); - - un1_counter_I_44 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \counter[2]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12[0]\); - - \counter[2]\ : DFN1C0 - port map(D => \counter_3[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[2]_net_1\); - - \counter[7]\ : DFN1C0 - port map(D => \counter_3[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[7]_net_1\); - - un1_counter_1_ADD_8x8_medium_area_I29_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[6]_net_1\, C => N147, Y - => ADD_8x8_medium_area_I29_Y_0); - - un1_counter_I_48 : AND2 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - Y => \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - un1_counter_1_ADD_8x8_medium_area_I20_Y : OA1B - port map(A => N145_i, B => ADD_8x8_medium_area_I20_un1_Y_0, - C => ADD_8x8_medium_area_I20_Y_0, Y => N147); - - \counter_RNO[0]\ : NOR2A - port map(A => \DWACT_ADD_CI_0_partial_sum[0]\, B => - raddr_rst, Y => \counter_3[0]\); - - \counter[6]\ : DFN1C0 - port map(D => \counter_3[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[6]_net_1\); - - \counter_RNO[4]\ : NOR2A - port map(A => I_28, B => raddr_rst, Y => \counter_3[4]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \memRAM.SRAM\ : syncram_2pZ0 - port map(alu_sample_10 => alu_sample_10, alu_sample_0 => - alu_sample_0, alu_sample_1 => alu_sample_1, - reg_sample_in_RNIFA3C(15) => reg_sample_in_RNIFA3C(15), - reg_sample_in(6) => reg_sample_in(6), reg_sample_in(5) - => reg_sample_in(5), ram_output_1 => ram_output_1, - ram_output_3 => ram_output_3, ram_output_4 => - ram_output_4, ram_output_5 => ram_output_5, ram_output_6 - => ram_output_6, ram_output_7 => ram_output_7, - ram_output_8 => ram_output_8, ram_output_9 => - ram_output_9, ram_output_10 => ram_output_10, - ram_output_11 => ram_output_11, ram_output_12 => - ram_output_12, ram_output_13 => ram_output_13, - ram_output_14 => ram_output_14, ram_output_15 => - ram_output_15, ram_output_17 => ram_output_17, - ram_output_0 => ram_output_0, ram_output_16 => - ram_output_16, DIN_REG1(15) => DIN_REG1(15), counter(7) - => \counter[7]_net_1\, counter(6) => \counter[6]_net_1\, - counter(5) => \counter[5]_net_1\, counter(4) => - \counter[4]_net_1\, counter(3) => \counter[3]_net_1\, - counter(2) => \counter[2]_net_1\, counter(1) => - \counter[1]_net_1\, counter(0) => \counter[0]_net_1\, - ram_input(17) => ram_input(17), ram_input(16) => - ram_input(16), ram_input(15) => ram_input(15), - ram_input(14) => ram_input(14), ram_input(13) => - ram_input(13), ram_input(12) => ram_input(12), - ram_input(11) => ram_input(11), ram_input(10) => - ram_input(10), ram_input(9) => ram_input(9), ram_input(8) - => ram_input(8), ram_input(7) => ram_input(7), - ram_input(6) => ram_input(6), ram_input(5) => - ram_input(5), ram_input(4) => ram_input(4), ram_input(3) - => ram_input(3), ram_input(2) => ram_input(2), - ram_input(1) => ram_input(1), ram_input(0) => - ram_input(0), I_1_RNI3I3E3 => I_1_RNI3I3E3, alu_sel_input - => alu_sel_input, HCLK_c => HCLK_c, ram_write => - ram_write, ADD_8x8_medium_area_I0_S_0 => - ADD_8x8_medium_area_I0_S_0, ADD_8x8_medium_area_I24_Y_0 - => ADD_8x8_medium_area_I24_Y_0, - ADD_8x8_medium_area_I25_Y_0 => - ADD_8x8_medium_area_I25_Y_0, ADD_8x8_medium_area_I26_Y_0 - => ADD_8x8_medium_area_I26_Y_0, - ADD_8x8_medium_area_I27_Y_0 => - ADD_8x8_medium_area_I27_Y_0, ADD_8x8_medium_area_I28_Y_0 - => ADD_8x8_medium_area_I28_Y_0, - ADD_8x8_medium_area_I29_Y_0 => - ADD_8x8_medium_area_I29_Y_0, ADD_8x8_medium_area_I30_Y_0 - => ADD_8x8_medium_area_I30_Y_0, syncram_2pZ0_GND => - RAM_CTRLR_v2_GND, syncram_2pZ0_VCC => RAM_CTRLR_v2_VCC, - ram_write_i => ram_write_i); - - un1_counter_1_ADD_8x8_medium_area_I26_Y_0 : AX1E - port map(A => N120, B => N135_i, C => N121, Y => - ADD_8x8_medium_area_I26_Y_0); - - \counter_RNO[1]\ : NOR2A - port map(A => I_27, B => raddr_rst, Y => \counter_3[1]\); - - un1_counter_1_ADD_8x8_medium_area_I0_CO1 : OR3B - port map(A => waddr_previous(0), B => \counter[0]_net_1\, C - => waddr_previous(1), Y => N116); - - \un2_waddr_0_x2[6]\ : XOR2 - port map(A => waddr_previous(1), B => waddr_previous(0), Y - => N_5_i); - - un1_counter_1_ADD_8x8_medium_area_I4_CO1 : OR2B - port map(A => \counter[4]_net_1\, B => N_5_i, Y => N124); - - un1_counter_I_28 : XOR2 - port map(A => \counter[4]_net_1\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_28); - - un1_counter_1_ADD_8x8_medium_area_I3_S_0 : XOR2 - port map(A => \counter[3]_net_1\, B => N_5_i, Y => N121); - - un1_counter_1_ADD_8x8_medium_area_I25_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[2]_net_1\, C => N135_i, - Y => ADD_8x8_medium_area_I25_Y_0); - - un1_counter_I_42 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \counter[4]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_1[0]\); - - un1_counter_1_ADD_8x8_medium_area_I30_Y_0 : XOR3 - port map(A => N_5_i, B => \counter[7]_net_1\, C => N149, Y - => ADD_8x8_medium_area_I30_Y_0); - - un1_counter_I_35 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => - \counter[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1[0]\); - - \counter[4]\ : DFN1C0 - port map(D => \counter_3[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[4]_net_1\); - - un1_counter_1_ADD_8x8_medium_area_I20_un1_Y_0 : OR2 - port map(A => \counter[4]_net_1\, B => N125_i, Y => - ADD_8x8_medium_area_I20_un1_Y_0); - - \counter[5]\ : DFN1C0 - port map(D => \counter_3[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[5]_net_1\); - - un1_counter_I_34 : XOR2 - port map(A => \counter[7]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => I_34); - - un1_counter_1_ADD_8x8_medium_area_I21_Y : MX2A - port map(A => N147, B => N_5_i, S => \counter[6]_net_1\, Y - => N149); - - \counter_RNO[2]\ : NOR2A - port map(A => I_32, B => raddr_rst, Y => \counter_3[2]\); - - GND_i : GND - port map(Y => \GND\); - - un1_counter_I_30 : XOR2 - port map(A => \counter[6]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_30); - - \counter_RNO[5]\ : NOR2A - port map(A => I_33, B => raddr_rst, Y => \counter_3[5]\); - - \counter_RNO[3]\ : NOR2A - port map(A => I_31, B => raddr_rst, Y => \counter_3[3]\); - - un1_counter_1_ADD_8x8_medium_area_I13_un1_Y_0 : OR2 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - Y => ADD_8x8_medium_area_I13_un1_Y_0); - - \counter[1]\ : DFN1C0 - port map(D => \counter_3[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[1]_net_1\); - - \counter[3]\ : DFN1C0 - port map(D => \counter_3[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[3]_net_1\); - - un1_counter_I_39 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - un1_counter_1_ADD_8x8_medium_area_I0_S_0 : AX1 - port map(A => waddr_previous(1), B => waddr_previous(0), C - => \counter[0]_net_1\, Y => ADD_8x8_medium_area_I0_S_0); - - un1_counter_I_47 : AND2 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - Y => \DWACT_ADD_CI_0_pog_array_1[0]\); - - un1_counter_I_19 : XOR2 - port map(A => \counter[0]_net_1\, B => raddr_add1, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \counter_RNO[6]\ : NOR2A - port map(A => I_30, B => raddr_rst, Y => \counter_3[6]\); - - un1_counter_I_1 : AND2 - port map(A => \counter[0]_net_1\, B => raddr_add1, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - un1_counter_1_ADD_8x8_medium_area_I5_S_0 : XNOR2 - port map(A => \counter[5]_net_1\, B => N_5_i, Y => N125_i); - - un1_counter_1_ADD_8x8_medium_area_I13_Y : OA1 - port map(A => N135_i, B => ADD_8x8_medium_area_I13_un1_Y_0, - C => ADD_8x8_medium_area_I13_Y_0, Y => N145_i); - - un1_counter_I_33 : XOR2 - port map(A => \counter[5]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_33); - - un1_counter_I_32 : XOR2 - port map(A => \counter[2]_net_1\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_32); - - un1_counter_I_27 : XOR2 - port map(A => \counter[1]_net_1\, B => - \DWACT_ADD_CI_0_TMP[0]\, Y => I_27); - - un1_counter_1_ADD_8x8_medium_area_I27_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[4]_net_1\, C => N145_i, - Y => ADD_8x8_medium_area_I27_Y_0); - - un1_counter_1_ADD_8x8_medium_area_I28_Y_0 : AX1C - port map(A => N124, B => N145_i, C => N125_i, Y => - ADD_8x8_medium_area_I28_Y_0); - - un1_counter_1_ADD_8x8_medium_area_I24_Y_0 : XNOR3 - port map(A => N116, B => \counter[1]_net_1\, C => N_5_i, Y - => ADD_8x8_medium_area_I24_Y_0); - - \counter_RNO[7]\ : NOR2A - port map(A => I_34, B => raddr_rst, Y => \counter_3[7]\); - - un1_counter_1_ADD_8x8_medium_area_I2_CO1 : OR2B - port map(A => \counter[2]_net_1\, B => N_5_i, Y => N120); - - \counter[0]\ : DFN1C0 - port map(D => \counter_3[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \counter[0]_net_1\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2_DATAFLOW is - - port( alu_ctrl : in std_logic_vector(2 downto 0); - S : out std_logic_vector(8 to 8); - S_i_0 : out std_logic_vector(33 to 33); - alu_sel_coeff : in std_logic_vector(4 downto 0); - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - waddr_previous : in std_logic_vector(1 downto 0); - sample_0 : in std_logic_vector(14 downto 0); - sample_in_buf : in std_logic_vector(143 downto 129); - ram_sel_Wdata : in std_logic_vector(1 downto 0); - sample_out_s_0 : out std_logic; - sample_out_s_1 : out std_logic; - sample_out_s_3 : out std_logic; - sample_out_s_2 : out std_logic; - sample_out_s_10 : out std_logic; - sample_out_s_15 : out std_logic; - sample_out_s_14 : out std_logic; - sample_out_s_13 : out std_logic; - sample_out_s_12 : out std_logic; - sample_out_s_11 : out std_logic; - sample_out_s_9 : out std_logic; - sample_out_s_8 : out std_logic; - sample_out_s_7 : out std_logic; - sample_out_s_6 : out std_logic; - sample_out_s_5 : out std_logic; - sample_out_s_4 : out std_logic; - sample_in_s_1 : in std_logic_vector(17 to 17); - in_sel_src : in std_logic_vector(1 downto 0); - raddr_rst : in std_logic; - raddr_add1 : in std_logic; - ram_write : in std_logic; - IIR_CEL_CTRLR_v2_DATAFLOW_GND : in std_logic; - IIR_CEL_CTRLR_v2_DATAFLOW_VCC : in std_logic; - ram_write_i : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_val_delay : in std_logic; - alu_sel_input : in std_logic - ); - -end IIR_CEL_CTRLR_v2_DATAFLOW; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2_DATAFLOW is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MUXN_9_5 - port( alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - S_i_0 : out std_logic_vector(33 to 33); - S : out std_logic_vector(8 to 8); - alu_coef_s : out std_logic_vector(8 downto 0) - ); - end component; - - component ALU - port( alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - sample_out_s : out std_logic_vector(17 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component RAM_CTRLR_v2 - port( ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - DIN_REG1 : out std_logic_vector(15 to 15); - ram_output_16 : out std_logic; - ram_output_0 : out std_logic; - ram_output_17 : out std_logic; - ram_output_15 : out std_logic; - ram_output_14 : out std_logic; - ram_output_13 : out std_logic; - ram_output_12 : out std_logic; - ram_output_11 : out std_logic; - ram_output_10 : out std_logic; - ram_output_9 : out std_logic; - ram_output_8 : out std_logic; - ram_output_7 : out std_logic; - ram_output_6 : out std_logic; - ram_output_5 : out std_logic; - ram_output_4 : out std_logic; - ram_output_3 : out std_logic; - ram_output_1 : out std_logic; - reg_sample_in : in std_logic_vector(6 downto 5) := (others => 'U'); - reg_sample_in_RNIFA3C : in std_logic_vector(15 to 15) := (others => 'U'); - alu_sample_1 : out std_logic; - alu_sample_0 : out std_logic; - alu_sample_10 : out std_logic; - waddr_previous : in std_logic_vector(1 downto 0) := (others => 'U'); - ram_write_i : in std_logic := 'U'; - RAM_CTRLR_v2_VCC : in std_logic := 'U'; - RAM_CTRLR_v2_GND : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - alu_sel_input : in std_logic := 'U'; - I_1_RNI3I3E3 : out std_logic; - raddr_add1 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - raddr_rst : in std_logic := 'U' - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \reg_sample_in_RNIFA3C[15]_net_1\, - \reg_sample_in[15]_net_1\, \DIN_REG1[15]\, - \reg_sample_in6\, N_318, \ram_output[4]\, - \sample_in_s_27[4]\, N_319, \ram_output[5]\, - \sample_in_s_25[5]\, N_320, \ram_output[6]\, - \sample_in_s_23[6]\, N_321, \ram_output[7]\, - \sample_in_s_21[7]\, N_322, \ram_output[8]\, - \sample_in_s_19[8]\, N_323, \ram_output[9]\, - \sample_in_s_17[9]\, N_324, \ram_output[10]\, - \sample_in_s_15[10]\, N_325, \ram_output[11]\, - \sample_in_s_13[11]\, N_326, \ram_output[12]\, - \sample_in_s_11[12]\, N_327, \ram_output[13]\, - \sample_in_s_9[13]\, N_328, \ram_output[14]\, - \sample_in_s_7[14]\, N_329, \ram_output[15]\, N_331, - \ram_output[17]\, \reg_sample_in_5[4]\, - reg_sample_in_5_sn_N_2_i, \reg_sample_in_5[5]\, - \reg_sample_in_5[6]\, \reg_sample_in_5[7]\, - \reg_sample_in_5[8]\, \reg_sample_in_5[9]\, - \reg_sample_in_5[11]\, \reg_sample_in_5[12]\, - \reg_sample_in_5[13]\, \reg_sample_in_5[14]\, - \reg_sample_in_5[15]\, \reg_sample_in_5[17]\, - \sample_out_s[17]\, N_358, \reg_sample_in[4]_net_1\, - \sample_out_s[4]\, N_359, \reg_sample_in[5]_net_1\, - \sample_out_s[5]\, N_360, \reg_sample_in[6]_net_1\, - \sample_out_s[6]\, N_361, \reg_sample_in[7]_net_1\, - \sample_out_s[7]\, N_362, \reg_sample_in[8]_net_1\, - \sample_out_s[8]\, N_363, \reg_sample_in[9]_net_1\, - \sample_out_s[9]\, N_364, \reg_sample_in[10]_net_1\, - N_365, \reg_sample_in[11]_net_1\, \sample_out_s[11]\, - N_366, \reg_sample_in[12]_net_1\, \sample_out_s[12]\, - N_367, \reg_sample_in[13]_net_1\, \sample_out_s[13]\, - N_368, \reg_sample_in[14]_net_1\, \sample_out_s[14]\, - N_369, \sample_out_s[15]\, N_371, - \reg_sample_in[17]_net_1\, \ram_input[4]\, \ram_input[5]\, - \ram_input[6]\, \ram_input[7]\, \ram_input[8]\, - \ram_input[9]\, \ram_input[10]\, \ram_input[11]\, - \ram_input[12]\, \ram_input[13]\, \ram_input[14]\, - \ram_input[15]\, \ram_input[17]\, \alu_sample[1]\, - \reg_sample_in[1]_net_1\, \ram_output[1]\, - \alu_sample[2]\, \reg_sample_in[2]_net_1\, I_1_RNI3I3E3, - \alu_sample[3]\, \reg_sample_in[3]_net_1\, - \ram_output[3]\, \alu_sample[4]\, \alu_sample[7]\, - \alu_sample[8]\, \alu_sample[9]\, \alu_sample[11]\, - \alu_sample[12]\, \alu_sample[13]\, \alu_sample[14]\, - \alu_sample[17]\, N_316, \sample_in_s_31[2]\, N_317, - \sample_in_s_29[3]\, \reg_sample_in_5[2]\, - \reg_sample_in_5[3]\, N_356, \sample_out_s[2]\, N_357, - \sample_out_s[3]\, \ram_input[2]\, \ram_input[3]\, N_315, - \sample_in_s_33[1]\, \reg_sample_in_5[1]\, N_355, - \sample_out_s[1]\, \ram_input[1]\, \alu_sample[10]\, - \reg_sample_in_5[10]\, \sample_out_s[10]\, - \sample_in_s_35[0]\, \ram_input[0]\, N_354, - \ram_output[0]\, \reg_sample_in[0]_net_1\, - \reg_sample_in_5[0]\, \sample_out_s[0]\, N_314, - \alu_sample[0]\, \alu_sample[16]\, - \reg_sample_in[16]_net_1\, \ram_output[16]\, - \ram_input[16]\, N_370, \sample_out_s[16]\, - \reg_sample_in_5[16]\, N_330, \alu_sample[6]\, - \alu_sample[5]\, \alu_sample[15]\, \alu_coef_s[0]\, - \alu_coef_s[1]\, \alu_coef_s[2]\, \alu_coef_s[3]\, - \alu_coef_s[4]\, \alu_coef_s[5]\, \alu_coef_s[6]\, - \alu_coef_s[7]\, \alu_coef_s[8]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : MUXN_9_5 - Use entity work.MUXN_9_5(DEF_ARCH); - for all : ALU - Use entity work.ALU(DEF_ARCH); - for all : RAM_CTRLR_v2 - Use entity work.RAM_CTRLR_v2(DEF_ARCH); -begin - - sample_out_s_0 <= \sample_out_s[0]\; - sample_out_s_1 <= \sample_out_s[1]\; - sample_out_s_3 <= \sample_out_s[3]\; - sample_out_s_2 <= \sample_out_s[2]\; - sample_out_s_10 <= \sample_out_s[10]\; - sample_out_s_15 <= \sample_out_s[15]\; - sample_out_s_14 <= \sample_out_s[14]\; - sample_out_s_13 <= \sample_out_s[13]\; - sample_out_s_12 <= \sample_out_s[12]\; - sample_out_s_11 <= \sample_out_s[11]\; - sample_out_s_9 <= \sample_out_s[9]\; - sample_out_s_8 <= \sample_out_s[8]\; - sample_out_s_7 <= \sample_out_s[7]\; - sample_out_s_6 <= \sample_out_s[6]\; - sample_out_s_5 <= \sample_out_s[5]\; - sample_out_s_4 <= \sample_out_s[4]\; - - \reg_sample_in_RNO_1[10]\ : MX2 - port map(A => sample_in_buf(133), B => sample_0(10), S => - sample_val_delay, Y => \sample_in_s_15[10]\); - - \reg_sample_in_RNO[2]\ : MX2 - port map(A => \sample_out_s[2]\, B => N_316, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[2]\); - - \reg_sample_in_RNIO8MA4[8]\ : MX2 - port map(A => N_362, B => \ram_output[8]\, S => - ram_sel_Wdata(1), Y => \ram_input[8]\); - - \reg_sample_in_RNO_1[1]\ : MX2 - port map(A => sample_in_buf(142), B => sample_0(1), S => - sample_val_delay, Y => \sample_in_s_33[1]\); - - \reg_sample_in_RNIUJBJ[12]\ : MX2 - port map(A => \reg_sample_in[12]_net_1\, B => - \sample_out_s[12]\, S => ram_sel_Wdata(0), Y => N_366); - - \reg_sample_in_RNIJLRL3[11]\ : MX2 - port map(A => \reg_sample_in[11]_net_1\, B => - \ram_output[11]\, S => alu_sel_input, Y => - \alu_sample[11]\); - - \reg_sample_in_RNO_0[7]\ : MX2 - port map(A => \ram_output[7]\, B => \sample_in_s_21[7]\, S - => in_sel_src(0), Y => N_321); - - \reg_sample_in_RNIPLRL3[14]\ : MX2 - port map(A => \reg_sample_in[14]_net_1\, B => - \ram_output[14]\, S => alu_sel_input, Y => - \alu_sample[14]\); - - \reg_sample_in_RNII1984[2]\ : MX2 - port map(A => N_356, B => I_1_RNI3I3E3, S => - ram_sel_Wdata(1), Y => \ram_input[2]\); - - \reg_sample_in[5]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[5]_net_1\); - - \reg_sample_in_RNI0HPO[5]\ : MX2C - port map(A => \reg_sample_in[5]_net_1\, B => - \sample_out_s[5]\, S => ram_sel_Wdata(0), Y => N_359); - - \reg_sample_in_RNISOMA4[9]\ : MX2 - port map(A => N_363, B => \ram_output[9]\, S => - ram_sel_Wdata(1), Y => \ram_input[9]\); - - \reg_sample_in_RNI1U5Q3[0]\ : MX2 - port map(A => \reg_sample_in[0]_net_1\, B => - \ram_output[0]\, S => alu_sel_input, Y => \alu_sample[0]\); - - \reg_sample_in_RNIJ68Q3[9]\ : MX2 - port map(A => \reg_sample_in[9]_net_1\, B => - \ram_output[9]\, S => alu_sel_input, Y => \alu_sample[9]\); - - \reg_sample_in_RNI4OJA4[3]\ : MX2 - port map(A => N_357, B => \ram_output[3]\, S => - ram_sel_Wdata(1), Y => \ram_input[3]\); - - \reg_sample_in_RNO_0[0]\ : MX2 - port map(A => \ram_output[0]\, B => \sample_in_s_35[0]\, S - => in_sel_src(0), Y => N_314); - - \reg_sample_in_RNO_0[1]\ : MX2 - port map(A => \ram_output[1]\, B => \sample_in_s_33[1]\, S - => in_sel_src(0), Y => N_315); - - \reg_sample_in_RNI3TPO[6]\ : MX2C - port map(A => \reg_sample_in[6]_net_1\, B => - \sample_out_s[6]\, S => ram_sel_Wdata(0), Y => N_360); - - \reg_sample_in_RNO_0[2]\ : MX2 - port map(A => I_1_RNI3I3E3, B => \sample_in_s_31[2]\, S => - in_sel_src(0), Y => N_316); - - \reg_sample_in_RNIT4PO[4]\ : MX2 - port map(A => \reg_sample_in[4]_net_1\, B => - \sample_out_s[4]\, S => ram_sel_Wdata(0), Y => N_358); - - \reg_sample_in_RNO[11]\ : MX2 - port map(A => \sample_out_s[11]\, B => N_325, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[11]\); - - \reg_sample_in_RNO_1[2]\ : MX2 - port map(A => sample_in_buf(141), B => sample_0(2), S => - sample_val_delay, Y => \sample_in_s_31[2]\); - - \reg_sample_in_RNO_0[11]\ : MX2 - port map(A => \ram_output[11]\, B => \sample_in_s_13[11]\, - S => in_sel_src(0), Y => N_325); - - \reg_sample_in_RNIU7964[15]\ : MX2 - port map(A => N_369, B => \ram_output[15]\, S => - ram_sel_Wdata(1), Y => \ram_input[15]\); - - reg_sample_in6 : NOR2 - port map(A => in_sel_src(1), B => in_sel_src(0), Y => - \reg_sample_in6\); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg_sample_in_RNO[13]\ : MX2 - port map(A => \sample_out_s[13]\, B => N_327, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[13]\); - - \reg_sample_in[3]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[3]_net_1\); - - \reg_sample_in_RNO_1[9]\ : MX2 - port map(A => sample_in_buf(134), B => sample_0(9), S => - sample_val_delay, Y => \sample_in_s_17[9]\); - - \reg_sample_in_RNO[4]\ : MX2 - port map(A => \sample_out_s[4]\, B => N_318, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[4]\); - - \reg_sample_in[7]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[7]_net_1\); - - \reg_sample_in[14]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[14]_net_1\); - - \reg_sample_in_RNILLRL3[12]\ : MX2 - port map(A => \reg_sample_in[12]_net_1\, B => - \ram_output[12]\, S => alu_sel_input, Y => - \alu_sample[12]\); - - \reg_sample_in_RNIEP884[1]\ : MX2 - port map(A => N_355, B => \ram_output[1]\, S => - ram_sel_Wdata(1), Y => \ram_input[1]\); - - \reg_sample_in_RNO[3]\ : MX2 - port map(A => \sample_out_s[3]\, B => N_317, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[3]\); - - \reg_sample_in_RNI5E6Q3[2]\ : MX2 - port map(A => \reg_sample_in[2]_net_1\, B => I_1_RNI3I3E3, - S => alu_sel_input, Y => \alu_sample[2]\); - - \reg_sample_in_RNO_1[11]\ : MX2 - port map(A => sample_in_buf(132), B => sample_0(11), S => - sample_val_delay, Y => \sample_in_s_13[11]\); - - \reg_sample_in_RNO[1]\ : MX2 - port map(A => \sample_out_s[1]\, B => N_315, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[1]\); - - \reg_sample_in_RNI9U6Q3[4]\ : MX2 - port map(A => \reg_sample_in[4]_net_1\, B => - \ram_output[4]\, S => alu_sel_input, Y => \alu_sample[4]\); - - \reg_sample_in[9]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[9]_net_1\); - - \reg_sample_in_RNO_0[15]\ : MX2 - port map(A => \ram_output[15]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_329); - - \reg_sample_in_RNO[8]\ : MX2 - port map(A => \sample_out_s[8]\, B => N_322, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[8]\); - - \reg_sample_in_RNO[12]\ : MX2 - port map(A => \sample_out_s[12]\, B => N_326, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[12]\); - - \reg_sample_in_RNI6O964[17]\ : MX2 - port map(A => N_371, B => \ram_output[17]\, S => - ram_sel_Wdata(1), Y => \ram_input[17]\); - - \reg_sample_in_RNIFB9J[13]\ : MX2 - port map(A => \reg_sample_in[13]_net_1\, B => - \sample_out_s[13]\, S => ram_sel_Wdata(0), Y => N_367); - - \reg_sample_in_RNIRBBJ[11]\ : MX2 - port map(A => \reg_sample_in[11]_net_1\, B => - \sample_out_s[11]\, S => ram_sel_Wdata(0), Y => N_365); - - \reg_sample_in_RNIQOOO[3]\ : MX2 - port map(A => \reg_sample_in[3]_net_1\, B => - \sample_out_s[3]\, S => ram_sel_Wdata(0), Y => N_357); - - \reg_sample_in_RNIFA3C[15]\ : MX2 - port map(A => \reg_sample_in[15]_net_1\, B => - \DIN_REG1[15]\, S => alu_sel_input, Y => - \reg_sample_in_RNIFA3C[15]_net_1\); - - \reg_sample_in_RNI0OA64[11]\ : MX2 - port map(A => N_365, B => \ram_output[11]\, S => - ram_sel_Wdata(1), Y => \ram_input[11]\); - - \reg_sample_in_RNO_0[16]\ : MX2 - port map(A => \ram_output[16]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_330); - - \reg_sample_in_RNIIJ9J[14]\ : MX2 - port map(A => \reg_sample_in[14]_net_1\, B => - \sample_out_s[14]\, S => ram_sel_Wdata(0), Y => N_368); - - \reg_sample_in[16]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[16]_net_1\); - - \reg_sample_in_RNO_1[5]\ : MX2C - port map(A => sample_in_buf(138), B => sample_0(5), S => - sample_val_delay, Y => \sample_in_s_25[5]\); - - \reg_sample_in_RNIVLRL3[17]\ : MX2 - port map(A => \reg_sample_in[17]_net_1\, B => - \ram_output[17]\, S => alu_sel_input, Y => - \alu_sample[17]\); - - \reg_sample_in_RNIFM7Q3[7]\ : MX2 - port map(A => \reg_sample_in[7]_net_1\, B => - \ram_output[7]\, S => alu_sel_input, Y => \alu_sample[7]\); - - Coeff_Mux : MUXN_9_5 - port map(alu_sel_coeff_0_0 => alu_sel_coeff_0_0, - alu_sel_coeff_0_2 => alu_sel_coeff_0_2, alu_sel_coeff(4) - => alu_sel_coeff(4), alu_sel_coeff(3) => - alu_sel_coeff(3), alu_sel_coeff(2) => alu_sel_coeff(2), - alu_sel_coeff(1) => alu_sel_coeff(1), alu_sel_coeff(0) - => alu_sel_coeff(0), S_i_0(33) => S_i_0(33), S(8) => - S(8), alu_coef_s(8) => \alu_coef_s[8]\, alu_coef_s(7) => - \alu_coef_s[7]\, alu_coef_s(6) => \alu_coef_s[6]\, - alu_coef_s(5) => \alu_coef_s[5]\, alu_coef_s(4) => - \alu_coef_s[4]\, alu_coef_s(3) => \alu_coef_s[3]\, - alu_coef_s(2) => \alu_coef_s[2]\, alu_coef_s(1) => - \alu_coef_s[1]\, alu_coef_s(0) => \alu_coef_s[0]\); - - ALU_1 : ALU - port map(alu_ctrl(2) => alu_ctrl(2), alu_ctrl(1) => - alu_ctrl(1), alu_ctrl(0) => alu_ctrl(0), alu_coef_s(8) - => \alu_coef_s[8]\, alu_coef_s(7) => \alu_coef_s[7]\, - alu_coef_s(6) => \alu_coef_s[6]\, alu_coef_s(5) => - \alu_coef_s[5]\, alu_coef_s(4) => \alu_coef_s[4]\, - alu_coef_s(3) => \alu_coef_s[3]\, alu_coef_s(2) => - \alu_coef_s[2]\, alu_coef_s(1) => \alu_coef_s[1]\, - alu_coef_s(0) => \alu_coef_s[0]\, alu_sample(17) => - \alu_sample[17]\, alu_sample(16) => \alu_sample[16]\, - alu_sample(15) => \alu_sample[15]\, alu_sample(14) => - \alu_sample[14]\, alu_sample(13) => \alu_sample[13]\, - alu_sample(12) => \alu_sample[12]\, alu_sample(11) => - \alu_sample[11]\, alu_sample(10) => \alu_sample[10]\, - alu_sample(9) => \alu_sample[9]\, alu_sample(8) => - \alu_sample[8]\, alu_sample(7) => \alu_sample[7]\, - alu_sample(6) => \alu_sample[6]\, alu_sample(5) => - \alu_sample[5]\, alu_sample(4) => \alu_sample[4]\, - alu_sample(3) => \alu_sample[3]\, alu_sample(2) => - \alu_sample[2]\, alu_sample(1) => \alu_sample[1]\, - alu_sample(0) => \alu_sample[0]\, sample_out_s(17) => - \sample_out_s[17]\, sample_out_s(16) => - \sample_out_s[16]\, sample_out_s(15) => - \sample_out_s[15]\, sample_out_s(14) => - \sample_out_s[14]\, sample_out_s(13) => - \sample_out_s[13]\, sample_out_s(12) => - \sample_out_s[12]\, sample_out_s(11) => - \sample_out_s[11]\, sample_out_s(10) => - \sample_out_s[10]\, sample_out_s(9) => \sample_out_s[9]\, - sample_out_s(8) => \sample_out_s[8]\, sample_out_s(7) => - \sample_out_s[7]\, sample_out_s(6) => \sample_out_s[6]\, - sample_out_s(5) => \sample_out_s[5]\, sample_out_s(4) => - \sample_out_s[4]\, sample_out_s(3) => \sample_out_s[3]\, - sample_out_s(2) => \sample_out_s[2]\, sample_out_s(1) => - \sample_out_s[1]\, sample_out_s(0) => \sample_out_s[0]\, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c); - - \reg_sample_in_RNI7M6Q3[3]\ : MX2 - port map(A => \reg_sample_in[3]_net_1\, B => - \ram_output[3]\, S => alu_sel_input, Y => \alu_sample[3]\); - - \reg_sample_in[8]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[8]_net_1\); - - \reg_sample_in[13]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[13]_net_1\); - - \reg_sample_in[12]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[12]_net_1\); - - \reg_sample_in_RNISFA64[10]\ : MX2 - port map(A => N_364, B => \ram_output[10]\, S => - ram_sel_Wdata(1), Y => \ram_input[10]\); - - \reg_sample_in_RNIHLRL3[10]\ : MX2 - port map(A => \reg_sample_in[10]_net_1\, B => - \ram_output[10]\, S => alu_sel_input, Y => - \alu_sample[10]\); - - \reg_sample_in_RNI88KA4[4]\ : MX2 - port map(A => N_358, B => \ram_output[4]\, S => - ram_sel_Wdata(1), Y => \ram_input[4]\); - - \reg_sample_in_RNI62EM[1]\ : MX2 - port map(A => \reg_sample_in[1]_net_1\, B => - \sample_out_s[1]\, S => ram_sel_Wdata(0), Y => N_355); - - \reg_sample_in[10]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[10]_net_1\); - - \reg_sample_in[6]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[6]_net_1\); - - \reg_sample_in[1]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[1]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \reg_sample_in_RNO[10]\ : MX2 - port map(A => \sample_out_s[10]\, B => N_324, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[10]\); - - \reg_sample_in_RNIC1RO[9]\ : MX2 - port map(A => \reg_sample_in[9]_net_1\, B => - \sample_out_s[9]\, S => ram_sel_Wdata(0), Y => N_363); - - \reg_sample_in_RNIQV864[14]\ : MX2 - port map(A => N_368, B => \ram_output[14]\, S => - ram_sel_Wdata(1), Y => \ram_input[14]\); - - \reg_sample_in_RNIO3AJ[16]\ : MX2 - port map(A => \reg_sample_in[16]_net_1\, B => - \sample_out_s[16]\, S => ram_sel_Wdata(0), Y => N_370); - - \reg_sample_in_RNO_0[5]\ : MX2C - port map(A => \ram_output[5]\, B => \sample_in_s_25[5]\, S - => in_sel_src(0), Y => N_319); - - \reg_sample_in_RNIAH884[0]\ : MX2 - port map(A => N_354, B => \ram_output[0]\, S => - ram_sel_Wdata(1), Y => \ram_input[0]\); - - \reg_sample_in[2]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[2]_net_1\); - - \reg_sample_in_RNO_1[4]\ : MX2 - port map(A => sample_in_buf(139), B => sample_0(4), S => - sample_val_delay, Y => \sample_in_s_27[4]\); - - \reg_sample_in_RNI40B64[12]\ : MX2 - port map(A => N_366, B => \ram_output[12]\, S => - ram_sel_Wdata(1), Y => \ram_input[12]\); - - \reg_sample_in_RNIO3BJ[10]\ : MX2 - port map(A => \reg_sample_in[10]_net_1\, B => - \sample_out_s[10]\, S => ram_sel_Wdata(0), Y => N_364); - - \reg_sample_in[17]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[17]_net_1\); - - \reg_sample_in_RNO[7]\ : MX2 - port map(A => \sample_out_s[7]\, B => N_321, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[7]\); - - \reg_sample_in_RNO[16]\ : MX2 - port map(A => \sample_out_s[16]\, B => N_330, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[16]\); - - \reg_sample_in_RNI9LQO[8]\ : MX2 - port map(A => \reg_sample_in[8]_net_1\, B => - \sample_out_s[8]\, S => ram_sel_Wdata(0), Y => N_362); - - \reg_sample_in[4]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[4]_net_1\); - - \reg_sample_in_RNO_1[7]\ : MX2 - port map(A => sample_in_buf(136), B => sample_0(7), S => - sample_val_delay, Y => \sample_in_s_21[7]\); - - \reg_sample_in_RNO_1[3]\ : MX2 - port map(A => sample_in_buf(140), B => sample_0(3), S => - sample_val_delay, Y => \sample_in_s_29[3]\); - - \reg_sample_in_RNO_0[12]\ : MX2 - port map(A => \ram_output[12]\, B => \sample_in_s_11[12]\, - S => in_sel_src(0), Y => N_326); - - \reg_sample_in_RNO[6]\ : MX2 - port map(A => \sample_out_s[6]\, B => N_320, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[6]\); - - \reg_sample_in[15]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[15]_net_1\); - - \reg_sample_in_RNO_0[4]\ : MX2 - port map(A => \ram_output[4]\, B => \sample_in_s_27[4]\, S - => in_sel_src(0), Y => N_318); - - \reg_sample_in_RNO_0[3]\ : MX2 - port map(A => \ram_output[3]\, B => \sample_in_s_29[3]\, S - => in_sel_src(0), Y => N_317); - - \reg_sample_in_RNO_0[17]\ : MX2 - port map(A => \ram_output[17]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_331); - - \reg_sample_in_RNO[17]\ : MX2 - port map(A => \sample_out_s[17]\, B => N_331, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[17]\); - - \reg_sample_in_RNO[14]\ : MX2 - port map(A => \sample_out_s[14]\, B => N_328, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[14]\); - - \reg_sample_in_RNIRBAJ[17]\ : MX2 - port map(A => \reg_sample_in[17]_net_1\, B => - \sample_out_s[17]\, S => ram_sel_Wdata(0), Y => N_371); - - \reg_sample_in_RNO_1[8]\ : MX2 - port map(A => sample_in_buf(135), B => sample_0(8), S => - sample_val_delay, Y => \sample_in_s_19[8]\); - - \reg_sample_in_RNI3UDM[0]\ : MX2 - port map(A => \reg_sample_in[0]_net_1\, B => - \sample_out_s[0]\, S => ram_sel_Wdata(0), Y => N_354); - - \reg_sample_in[11]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[11]_net_1\); - - \reg_sample_in_RNO[5]\ : MX2 - port map(A => \sample_out_s[5]\, B => N_319, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[5]\); - - \reg_sample_in_RNO_0[9]\ : MX2 - port map(A => \ram_output[9]\, B => \sample_in_s_17[9]\, S - => in_sel_src(0), Y => N_323); - - \reg_sample_in_RNO[9]\ : MX2 - port map(A => \sample_out_s[9]\, B => N_323, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[9]\); - - RAM_CTRLR_v2_1 : RAM_CTRLR_v2 - port map(ram_input(17) => \ram_input[17]\, ram_input(16) - => \ram_input[16]\, ram_input(15) => \ram_input[15]\, - ram_input(14) => \ram_input[14]\, ram_input(13) => - \ram_input[13]\, ram_input(12) => \ram_input[12]\, - ram_input(11) => \ram_input[11]\, ram_input(10) => - \ram_input[10]\, ram_input(9) => \ram_input[9]\, - ram_input(8) => \ram_input[8]\, ram_input(7) => - \ram_input[7]\, ram_input(6) => \ram_input[6]\, - ram_input(5) => \ram_input[5]\, ram_input(4) => - \ram_input[4]\, ram_input(3) => \ram_input[3]\, - ram_input(2) => \ram_input[2]\, ram_input(1) => - \ram_input[1]\, ram_input(0) => \ram_input[0]\, - DIN_REG1(15) => \DIN_REG1[15]\, ram_output_16 => - \ram_output[16]\, ram_output_0 => \ram_output[0]\, - ram_output_17 => \ram_output[17]\, ram_output_15 => - \ram_output[15]\, ram_output_14 => \ram_output[14]\, - ram_output_13 => \ram_output[13]\, ram_output_12 => - \ram_output[12]\, ram_output_11 => \ram_output[11]\, - ram_output_10 => \ram_output[10]\, ram_output_9 => - \ram_output[9]\, ram_output_8 => \ram_output[8]\, - ram_output_7 => \ram_output[7]\, ram_output_6 => - \ram_output[6]\, ram_output_5 => \ram_output[5]\, - ram_output_4 => \ram_output[4]\, ram_output_3 => - \ram_output[3]\, ram_output_1 => \ram_output[1]\, - reg_sample_in(6) => \reg_sample_in[6]_net_1\, - reg_sample_in(5) => \reg_sample_in[5]_net_1\, - reg_sample_in_RNIFA3C(15) => - \reg_sample_in_RNIFA3C[15]_net_1\, alu_sample_1 => - \alu_sample[6]\, alu_sample_0 => \alu_sample[5]\, - alu_sample_10 => \alu_sample[15]\, waddr_previous(1) => - waddr_previous(1), waddr_previous(0) => waddr_previous(0), - ram_write_i => ram_write_i, RAM_CTRLR_v2_VCC => - IIR_CEL_CTRLR_v2_DATAFLOW_VCC, RAM_CTRLR_v2_GND => - IIR_CEL_CTRLR_v2_DATAFLOW_GND, ram_write => ram_write, - alu_sel_input => alu_sel_input, I_1_RNI3I3E3 => - I_1_RNI3I3E3, raddr_add1 => raddr_add1, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, raddr_rst => raddr_rst); - - reg_sample_in_5_sn_m1 : OR2B - port map(A => in_sel_src(1), B => in_sel_src(0), Y => - reg_sample_in_5_sn_N_2_i); - - \reg_sample_in_RNO[15]\ : MX2 - port map(A => \sample_out_s[15]\, B => N_329, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[15]\); - - \reg_sample_in_RNO_0[14]\ : MX2 - port map(A => \ram_output[14]\, B => \sample_in_s_7[14]\, S - => in_sel_src(0), Y => N_328); - - \reg_sample_in_RNI96EM[2]\ : MX2 - port map(A => \reg_sample_in[2]_net_1\, B => - \sample_out_s[2]\, S => ram_sel_Wdata(0), Y => N_356); - - \reg_sample_in_RNO_1[12]\ : MX2 - port map(A => sample_in_buf(131), B => sample_0(12), S => - sample_val_delay, Y => \sample_in_s_11[12]\); - - \reg_sample_in_RNI366Q3[1]\ : MX2 - port map(A => \reg_sample_in[1]_net_1\, B => - \ram_output[1]\, S => alu_sel_input, Y => \alu_sample[1]\); - - \reg_sample_in_RNI69QO[7]\ : MX2 - port map(A => \reg_sample_in[7]_net_1\, B => - \sample_out_s[7]\, S => ram_sel_Wdata(0), Y => N_361); - - \reg_sample_in_RNIG8LA4[6]\ : MX2C - port map(A => N_360, B => \ram_output[6]\, S => - ram_sel_Wdata(1), Y => \ram_input[6]\); - - \reg_sample_in_RNO_0[8]\ : MX2 - port map(A => \ram_output[8]\, B => \sample_in_s_19[8]\, S - => in_sel_src(0), Y => N_322); - - \reg_sample_in_RNO_0[13]\ : MX2 - port map(A => \ram_output[13]\, B => \sample_in_s_9[13]\, S - => in_sel_src(0), Y => N_327); - - \reg_sample_in_RNO[0]\ : MX2 - port map(A => \sample_out_s[0]\, B => N_314, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[0]\); - - \reg_sample_in_RNITLRL3[16]\ : MX2 - port map(A => \reg_sample_in[16]_net_1\, B => - \ram_output[16]\, S => alu_sel_input, Y => - \alu_sample[16]\); - - \reg_sample_in_RNILR9J[15]\ : MX2 - port map(A => \reg_sample_in[15]_net_1\, B => - \sample_out_s[15]\, S => ram_sel_Wdata(0), Y => N_369); - - \reg_sample_in[0]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => \reg_sample_in6\, Q => - \reg_sample_in[0]_net_1\); - - \reg_sample_in_RNO_0[10]\ : MX2 - port map(A => \ram_output[10]\, B => \sample_in_s_15[10]\, - S => in_sel_src(0), Y => N_324); - - \reg_sample_in_RNIKOLA4[7]\ : MX2 - port map(A => N_361, B => \ram_output[7]\, S => - ram_sel_Wdata(1), Y => \ram_input[7]\); - - \reg_sample_in_RNI2G964[16]\ : MX2 - port map(A => N_370, B => \ram_output[16]\, S => - ram_sel_Wdata(1), Y => \ram_input[16]\); - - \reg_sample_in_RNINLRL3[13]\ : MX2 - port map(A => \reg_sample_in[13]_net_1\, B => - \ram_output[13]\, S => alu_sel_input, Y => - \alu_sample[13]\); - - \reg_sample_in_RNO_1[14]\ : MX2 - port map(A => sample_in_buf(129), B => sample_0(14), S => - sample_val_delay, Y => \sample_in_s_7[14]\); - - \reg_sample_in_RNO_1[6]\ : MX2C - port map(A => sample_in_buf(137), B => sample_0(6), S => - sample_val_delay, Y => \sample_in_s_23[6]\); - - \reg_sample_in_RNIHU7Q3[8]\ : MX2 - port map(A => \reg_sample_in[8]_net_1\, B => - \ram_output[8]\, S => alu_sel_input, Y => \alu_sample[8]\); - - \reg_sample_in_RNO_0[6]\ : MX2C - port map(A => \ram_output[6]\, B => \sample_in_s_23[6]\, S - => in_sel_src(0), Y => N_320); - - \reg_sample_in_RNO_1[13]\ : MX2 - port map(A => sample_in_buf(130), B => sample_0(13), S => - sample_val_delay, Y => \sample_in_s_9[13]\); - - \reg_sample_in_RNO_1[0]\ : MX2 - port map(A => sample_in_buf(143), B => sample_0(0), S => - sample_val_delay, Y => \sample_in_s_35[0]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \reg_sample_in_RNIMN864[13]\ : MX2 - port map(A => N_367, B => \ram_output[13]\, S => - ram_sel_Wdata(1), Y => \ram_input[13]\); - - \reg_sample_in_RNICOKA4[5]\ : MX2C - port map(A => N_359, B => \ram_output[5]\, S => - ram_sel_Wdata(1), Y => \ram_input[5]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2_CONTROL is - - port( alu_ctrl : out std_logic_vector(2 downto 0); - ram_sel_Wdata : out std_logic_vector(1 downto 0); - waddr_previous : out std_logic_vector(1 downto 0); - in_sel_src : out std_logic_vector(1 downto 0); - S_i_0 : in std_logic_vector(33 to 33); - S : in std_logic_vector(8 to 8); - alu_sel_coeff : out std_logic_vector(4 downto 0); - alu_sel_coeff_0_2 : out std_logic; - alu_sel_coeff_0_0 : out std_logic; - sample_out_rot_s : out std_logic; - sample_out_val_s : out std_logic; - raddr_rst : out std_logic; - alu_sel_input : out std_logic; - raddr_add1 : out std_logic; - sample_val_delay : in std_logic; - ram_write : out std_logic; - ram_write_i : out std_logic; - un1_sample_in_rotate : out std_logic; - sample_out_rot_s_0 : out std_logic; - sample_out_rot_s_1 : out std_logic; - sample_out_rot_s_2 : out std_logic; - sample_out_rot_s_3 : out std_logic; - sample_out_rot_s_4 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end IIR_CEL_CTRLR_v2_CONTROL; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2_CONTROL is - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \Chanel_ongoing_RNISG5D[13]_net_1\, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_7, N_270, - Chanel_ongoing_n20, \Chanel_ongoing[20]_net_1\, N_278, - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Chanel_ongoing_n21, - \Chanel_ongoing[21]_net_1\, N_279, Chanel_ongoing_n22, - \Chanel_ongoing[22]_net_1\, N_725, Chanel_ongoing_n28, - \Chanel_ongoing[28]_net_1\, N_293, - un1_alu_sel_input_0_sqmuxa_2_i_0, Chanel_ongoing_n29, - \Chanel_ongoing[29]_net_1\, N_295, Chanel_ongoing_n30, - \Chanel_ongoing[30]_net_1\, N_327, Chanel_ongoing_n31, - \Chanel_ongoing[31]_net_1\, N_335, N_250, - \Chanel_ongoing[0]_net_1\, \Chanel_ongoing[1]_net_1\, - \Chanel_ongoing[2]_net_1\, N_256, - \Chanel_ongoing[7]_net_1\, N_254, - \Chanel_ongoing[8]_net_1\, N_265, - \Chanel_ongoing[11]_net_1\, N_258, - \Chanel_ongoing[12]_net_1\, \Chanel_ongoing[13]_net_1\, - N_271, \Chanel_ongoing[14]_net_1\, N_272, - \Chanel_ongoing[15]_net_1\, N_273, - \Chanel_ongoing[16]_net_1\, N_275, - \Chanel_ongoing[17]_net_1\, N_276, - \Chanel_ongoing[18]_net_1\, \Chanel_ongoing[19]_net_1\, - N_288, \Chanel_ongoing[23]_net_1\, N_290, - \Chanel_ongoing[24]_net_1\, N_292, N_291, - \Chanel_ongoing[26]_net_1\, \Chanel_ongoing[27]_net_1\, - \Chanel_ongoing[9]_net_1\, \Chanel_ongoing[10]_net_1\, - \Chanel_ongoing[25]_net_1\, \Chanel_ongoing[5]_net_1\, - N_252, \Chanel_ongoing[6]_net_1\, - \Chanel_ongoing[3]_net_1\, \Chanel_ongoing[4]_net_1\, - N_75, \Cel_ongoing[29]_net_1\, \Cel_ongoing[30]_net_1\, - N_72, I129_un1_Y, \Cel_ongoing[13]_net_1\, N_28_0, - ADD_32x32_fast_I129_un1_Y_14, N_20_0, - \Cel_ongoing[3]_net_1\, N_18_0, \Cel_ongoing[4]_net_1\, - N_22_0, \Cel_ongoing[5]_net_1\, \Cel_ongoing[6]_net_1\, - N_24_0, \Cel_ongoing[7]_net_1\, \Cel_ongoing[8]_net_1\, - N_26_0, \Cel_ongoing[9]_net_1\, \Cel_ongoing[10]_net_1\, - \Cel_ongoing[11]_net_1\, \Cel_ongoing[12]_net_1\, N_44, - \Cel_ongoing[14]_net_1\, N_47, \Cel_ongoing[15]_net_1\, - \Cel_ongoing[16]_net_1\, N_48, N_51, - \Cel_ongoing[17]_net_1\, \Cel_ongoing[18]_net_1\, N_52, - N_55, \Cel_ongoing[19]_net_1\, \Cel_ongoing[20]_net_1\, - N_56, N_59, \Cel_ongoing[21]_net_1\, - \Cel_ongoing[22]_net_1\, N_60, N_63, - \Cel_ongoing[23]_net_1\, \Cel_ongoing[24]_net_1\, N_64, - N_66, \Cel_ongoing[25]_net_1\, N_68, - \Cel_ongoing[26]_net_1\, N_70, \Cel_ongoing[27]_net_1\, - \Cel_ongoing[28]_net_1\, \un1_IIR_CEL_STATE_17_i[17]\, - \Cel_ongoing_RNO[14]_net_1\, N_371_0, - \Cel_ongoing_RNO[15]_net_1\, N_435, N_436, N_437, N_438, - N_439, N_440, N_371, N_441, N_442, N_443, N_444, N_445, - N_446, N_447, N_448, N_449, N_450, - \Cel_ongoing[31]_net_1\, \Cel_ongoing[1]_net_1\, N_16_0, - \Cel_ongoing[2]_net_1\, \Cel_ongoing[0]_net_1\, N_566, - N_6, \IIR_CEL_STATE[4]_net_1\, \IIR_CEL_STATE_i[9]_net_1\, - \IIR_CEL_STATE[0]_net_1\, \IIR_CEL_STATE[1]_net_1\, - alu_selected_coeff_n0, alu_selected_coeffe, N_713, - N_567_i_0, \IIR_CEL_STATE[8]_net_1\, N_127_0, N_274, - un1_alu_sel_input_0_sqmuxa_2_i_0_s_0_0, N_452, N_248, - \sample_in_rot_RNI6EV7\, \IIR_CEL_STATE_i_i[9]\, - ADD_32x32_fast_I129_un1_Y_9, ADD_32x32_fast_I129_un1_Y_8, - ADD_32x32_fast_I129_un1_Y_13, ADD_32x32_fast_I129_un1_Y_5, - ADD_32x32_fast_I129_un1_Y_4, ADD_32x32_fast_I129_un1_Y_11, - ADD_32x32_fast_I129_un1_Y_7, ADD_32x32_fast_I129_un1_Y_3, - ADD_32x32_fast_I129_un1_Y_1, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_2, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_1, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_6, - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_4, - Chanel_ongoing_n2_0_i_0_0, Chanel_ongoing_n7_0_i_0_0, - Chanel_ongoing_n6_0_i_0_0, Chanel_ongoing_n4_0_i_0_0, - Chanel_ongoing_n8_0_i_0_0, Chanel_ongoing_n5_0_i_0_0, - Chanel_ongoing_n1_0_i_0_0, alu_selected_coeff_n3_0_i_0, - N_717, N_733_1, N_294, N_453, alu_selected_coeff_n2_0_i_0, - \alu_sel_coeff_0[2]\, \Cel_ongoing_6_i_i_1[0]\, - \Cel_ongoing_6_i_i_a2_0_0[0]\, N_328, - \Cel_ongoing_6_i_i_0[0]\, - \un1_IIR_CEL_STATE_17_i_1_i_0[31]\, N_457, - un1_IIR_CEL_STATE_22_0_0, \IIR_CEL_STATE[5]_net_1\, - raddr_add1_2_i_a2_0_0, \IIR_CEL_STATE[3]_net_1\, - \in_sel_src_8_i_a2_0_a2_0_0[1]\, \IIR_CEL_STATE[6]_net_1\, - \IIR_CEL_STATE[7]_net_1\, Cel_ongoing_0_sqmuxa_0_a2_0_27, - Cel_ongoing_0_sqmuxa_0_a2_0_16, - Cel_ongoing_0_sqmuxa_0_a2_0_15, - Cel_ongoing_0_sqmuxa_0_a2_0_24, - Cel_ongoing_0_sqmuxa_0_a2_0_26, - Cel_ongoing_0_sqmuxa_0_a2_0_12, - Cel_ongoing_0_sqmuxa_0_a2_0_11, - Cel_ongoing_0_sqmuxa_0_a2_0_22, - Cel_ongoing_0_sqmuxa_0_a2_0_25, - Cel_ongoing_0_sqmuxa_0_a2_0_8, - Cel_ongoing_0_sqmuxa_0_a2_0_7, - Cel_ongoing_0_sqmuxa_0_a2_0_20, N_479, - Cel_ongoing_0_sqmuxa_0_a2_0_4, - Cel_ongoing_0_sqmuxa_0_a2_0_18, - Cel_ongoing_0_sqmuxa_0_a2_0_14, - Cel_ongoing_0_sqmuxa_0_a2_0_10, - Cel_ongoing_0_sqmuxa_0_a2_0_6, - Cel_ongoing_0_sqmuxa_0_a2_0_3, - Cel_ongoing_0_sqmuxa_0_a2_0_1, - \in_sel_src_8_i_a2_0_o2_0_27[1]\, - \in_sel_src_8_i_a2_0_o2_0_18[1]\, - \in_sel_src_8_i_a2_0_o2_0_17[1]\, - \in_sel_src_8_i_a2_0_o2_0_23[1]\, - \in_sel_src_8_i_a2_0_o2_0_26[1]\, - \in_sel_src_8_i_a2_0_o2_0_12[1]\, - \in_sel_src_8_i_a2_0_o2_0_11[1]\, - \in_sel_src_8_i_a2_0_o2_0_22[1]\, - \in_sel_src_8_i_a2_0_o2_0_25[1]\, - \in_sel_src_8_i_a2_0_o2_0_8[1]\, - \in_sel_src_8_i_a2_0_o2_0_7[1]\, - \in_sel_src_8_i_a2_0_o2_0_20[1]\, - \in_sel_src_8_i_a2_0_o2_0_2[1]\, - \in_sel_src_8_i_a2_0_o2_0_1[1]\, - \in_sel_src_8_i_a2_0_o2_0_15[1]\, - \in_sel_src_8_i_a2_0_o2_0_14[1]\, - \in_sel_src_8_i_a2_0_o2_0_10[1]\, - \in_sel_src_8_i_a2_0_o2_0_6[1]\, - \in_sel_src_8_i_a2_0_o2_0_4[1]\, ram_write_2_0_a2_0, N_18, - N_20, N_650, N_651, N_703, N_206, N_480, - un1_IIR_CEL_STATE_20, N_325_i, N_714, - un1_IIR_CEL_STATE_22, N_796_i, N_736, N_723_i_0, N_737, - N_735, N_289, N_11, N_22, N_216, N_216_tz, N_33_0, N_34_0, - N_35_0, N_36_0, N_38, N_40, N_42, Chanel_ongoing_n0, - \Cel_ongoing_RNO[3]_net_1\, \Cel_ongoing_RNO[4]_net_1\, - \Cel_ongoing_RNO[5]_net_1\, \Cel_ongoing_RNO[6]_net_1\, - \Cel_ongoing_RNO[7]_net_1\, \Cel_ongoing_RNO[8]_net_1\, - \Cel_ongoing_RNO[9]_net_1\, \Cel_ongoing_RNO[10]_net_1\, - \Cel_ongoing_RNO[11]_net_1\, \Cel_ongoing_RNO[12]_net_1\, - N_462, N_374_i, N_269, N_332, Chanel_ongoing_n17, - Chanel_ongoing_n18, Chanel_ongoing_n19, - Chanel_ongoing_n23, Chanel_ongoing_n24, - Chanel_ongoing_n26, Chanel_ongoing_n27, N_224, N_724, - N_229, N_232, sample_in_rotate, N_373_i, N_372_i, N_127, - N_461, N_460, \IIR_CEL_STATE_ns[8]\, N_336_i_i_0, N_221, - \Cel_ongoing_RNO[13]_net_1\, \Cel_ongoing_RNO[1]_net_1\, - N_31_0, N_32_0_i_0, N_715, N_15_i, \alu_sel_coeff[3]\, - N_353, N_712, \IIR_CEL_STATE[2]_net_1\, N_227, N_729, - N_523, N_568_i_0, ram_write_2, un1_IIR_CEL_STATE_27, - N_477, N_569, N_334, N_180, N_204, Chanel_ongoing_n25, - un1_IIR_CEL_STATE_25, N_268_i_0, alu_sel_input_1, - sample_in_rot_2, N_512_i_0, \alu_sel_coeff[0]\, - \alu_sel_coeff[2]\, \alu_sel_coeff[4]\, ram_write_net_1, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - alu_sel_coeff(4) <= \alu_sel_coeff[4]\; - alu_sel_coeff(3) <= \alu_sel_coeff[3]\; - alu_sel_coeff(2) <= \alu_sel_coeff[2]\; - alu_sel_coeff(0) <= \alu_sel_coeff[0]\; - alu_sel_coeff_0_2 <= \alu_sel_coeff_0[2]\; - ram_write <= ram_write_net_1; - - sample_in_rot_RNO : NOR2A - port map(A => \IIR_CEL_STATE[7]_net_1\, B => N_328, Y => - sample_in_rot_2); - - \Cel_ongoing_RNIP2TO[8]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_4[1]\, B => - \Cel_ongoing[8]_net_1\, C => \Cel_ongoing[7]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_17[1]\); - - un1_IIR_CEL_STATE_17_m17 : NOR3C - port map(A => \Cel_ongoing[1]_net_1\, B => N_16_0, C => - \Cel_ongoing[2]_net_1\, Y => N_18_0); - - \IIR_CEL_STATE_RNIU1T5[5]\ : OR2 - port map(A => \IIR_CEL_STATE[7]_net_1\, B => - \IIR_CEL_STATE[5]_net_1\, Y => N_289); - - \Cel_ongoing_RNO[9]\ : XA1 - port map(A => \Cel_ongoing[9]_net_1\, B => N_24_0, C => - N_371_0, Y => \Cel_ongoing_RNO[9]_net_1\); - - \in_sel_src[0]\ : DFN1E0C0 - port map(D => N_268_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => un1_IIR_CEL_STATE_27, Q => in_sel_src(0)); - - \Chanel_ongoing_RNIFMU9[17]\ : NOR2A - port map(A => \Chanel_ongoing[17]_net_1\, B => N_273, Y => - N_275); - - \Chanel_ongoing[1]\ : DFN1E1C0 - port map(D => N_18, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[1]_net_1\); - - \in_sel_src_RNO_0[1]\ : OR2 - port map(A => \IIR_CEL_STATE[6]_net_1\, B => - \IIR_CEL_STATE[7]_net_1\, Y => - \in_sel_src_8_i_a2_0_a2_0_0[1]\); - - \Chanel_ongoing_RNI3OA4[8]\ : NOR3C - port map(A => \Chanel_ongoing[7]_net_1\, B => N_254, C => - \Chanel_ongoing[8]_net_1\, Y => N_256); - - \Chanel_ongoing_RNIO3D1[2]\ : OR3C - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, C => \Chanel_ongoing[2]_net_1\, - Y => N_250); - - \Cel_ongoing[23]\ : DFN1C0 - port map(D => N_442, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[23]_net_1\); - - \Cel_ongoing[22]\ : DFN1C0 - port map(D => N_441, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[22]_net_1\); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_7 : NOR2B - port map(A => \Cel_ongoing[28]_net_1\, B => - \Cel_ongoing[29]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_7); - - \Chanel_ongoing_RNO_0[22]\ : OR2A - port map(A => \Chanel_ongoing[21]_net_1\, B => N_279, Y => - N_725); - - \Chanel_ongoing[29]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n29, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[29]_net_1\); - - \Cel_ongoing_RNO[17]\ : XA1 - port map(A => \Cel_ongoing[17]_net_1\, B => N_48, C => - N_371_0, Y => N_436); - - \Chanel_ongoing_RNIPNC7[13]\ : OR2A - port map(A => \Chanel_ongoing[13]_net_1\, B => N_265, Y => - N_270); - - \Chanel_ongoing_RNIIB91[29]\ : NOR2 - port map(A => \Chanel_ongoing[29]_net_1\, B => - \Chanel_ongoing[30]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_10); - - \IIR_CEL_STATE_i_RNILN7F[9]\ : AOI1B - port map(A => N_733_1, B => N_294, C => N_453, Y => - un1_alu_sel_input_0_sqmuxa_2_i_0_s_0_0); - - \Cel_ongoing[15]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[15]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[15]_net_1\); - - \Cel_ongoing_RNO[16]\ : NOR2A - port map(A => N_371_0, B => N_47, Y => N_435); - - \Chanel_ongoing_RNO[30]\ : XA1C - port map(A => \Chanel_ongoing[30]_net_1\, B => N_327, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n30); - - \Cel_ongoing_RNO[21]\ : XA1 - port map(A => \Cel_ongoing[21]_net_1\, B => N_56, C => - N_371, Y => N_440); - - \alu_selected_coeff[4]\ : DFN1E1C0 - port map(D => N_715, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => \alu_sel_coeff[4]\); - - \Cel_ongoing[2]\ : DFN1C0 - port map(D => N_227, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[2]_net_1\); - - \alu_selected_coeff_RNIH4TI5[0]\ : NOR2A - port map(A => N_371, B => \alu_sel_coeff[0]\, Y => - alu_selected_coeff_n0); - - \Cel_ongoing_RNIT33B[0]\ : NOR2A - port map(A => \Cel_ongoing[0]_net_1\, B => - \Cel_ongoing[14]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_7[1]\); - - \alu_selected_coeff_RNO[3]\ : NOR2A - port map(A => N_371_0, B => alu_selected_coeff_n3_0_i_0, Y - => N_714); - - \Chanel_ongoing_RNO_0[9]\ : XNOR2 - port map(A => N_256, B => \Chanel_ongoing[9]_net_1\, Y => - N_372_i); - - \IIR_CEL_STATE_RNO[2]\ : NOR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_523, Y => - N_477); - - \Chanel_ongoing_RNIQVNF[26]\ : OR2B - port map(A => N_291, B => \Chanel_ongoing[26]_net_1\, Y => - N_292); - - alu_sel_input_RNO : NOR2 - port map(A => \IIR_CEL_STATE[6]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => alu_sel_input_1); - - \Chanel_ongoing_RNO_0[3]\ : XNOR2 - port map(A => N_250, B => \Chanel_ongoing[3]_net_1\, Y => - N_336_i_i_0); - - \Cel_ongoing_RNO_1[0]\ : NOR2B - port map(A => \IIR_CEL_STATE[4]_net_1\, B => - \un1_IIR_CEL_STATE_17_i_1_i_0[31]\, Y => - \Cel_ongoing_6_i_i_a2_0_0[0]\); - - \Chanel_ongoing[30]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n30, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[30]_net_1\); - - \IIR_CEL_STATE_RNI5V1J5[2]\ : OR2B - port map(A => N_371, B => N_353, Y => alu_selected_coeffe); - - \Cel_ongoing_RNO[5]\ : NOR2A - port map(A => N_371_0, B => N_35_0, Y => - \Cel_ongoing_RNO[5]_net_1\); - - \Cel_ongoing_RNIDJOG[18]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_10[1]\, B => - \Cel_ongoing[18]_net_1\, C => \Cel_ongoing[17]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_20[1]\); - - \Cel_ongoing[24]\ : DFN1C0 - port map(D => N_443, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[24]_net_1\); - - un1_IIR_CEL_STATE_17_m54 : AX1E - port map(A => \Cel_ongoing[19]_net_1\, B => N_52, C => - \Cel_ongoing[20]_net_1\, Y => N_55); - - \Chanel_ongoing_RNIDQB2[4]\ : NOR3B - port map(A => \Chanel_ongoing[3]_net_1\, B => - \Chanel_ongoing[4]_net_1\, C => N_250, Y => N_252); - - \IIR_CEL_STATE_i[9]\ : DFN1 - port map(D => N_512_i_0, CLK => HCLK_c, Q => - \IIR_CEL_STATE_i[9]_net_1\); - - \Chanel_ongoing_RNI61B3[6]\ : NOR3C - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252, C => - \Chanel_ongoing[6]_net_1\, Y => N_254); - - \Chanel_ongoing[8]\ : DFN1E1C0 - port map(D => N_651, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[8]_net_1\); - - \Chanel_ongoing_RNO[13]\ : XA1C - port map(A => \Chanel_ongoing[13]_net_1\, B => N_265, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => N_224); - - \Chanel_ongoing_RNIKIU[2]\ : NOR2 - port map(A => \Chanel_ongoing[2]_net_1\, B => - \Chanel_ongoing[4]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_1); - - \Cel_ongoing_RNO[11]\ : XA1 - port map(A => \Cel_ongoing[11]_net_1\, B => N_26_0, C => - N_371_0, Y => \Cel_ongoing_RNO[11]_net_1\); - - \Cel_ongoing_RNIKMF11[22]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_12[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_11[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_22[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_26[1]\); - - \IIR_CEL_STATE_RNIRIR8[6]\ : OR3 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[6]_net_1\, C => \IIR_CEL_STATE[7]_net_1\, - Y => N_334); - - \alu_selected_coeff_RNO_0[4]\ : AX1A - port map(A => N_717, B => \alu_sel_coeff[3]\, C => - \alu_sel_coeff[4]\, Y => N_15_i); - - \Chanel_ongoing[3]\ : DFN1E1C0 - port map(D => N_221, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[3]_net_1\); - - \Chanel_ongoing_RNO_0[6]\ : AX1E - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252, C => - \Chanel_ongoing[6]_net_1\, Y => Chanel_ongoing_n6_0_i_0_0); - - ram_write_RNO : AO1B - port map(A => ram_write_2_0_a2_0, B => N_733_1, C => N_480, - Y => ram_write_2); - - \Cel_ongoing_RNICE615_0[2]\ : OR2A - port map(A => N_325_i, B => \Cel_ongoing[2]_net_1\, Y => - N_332); - - \Cel_ongoing[0]\ : DFN1C0 - port map(D => N_206, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[0]_net_1\); - - sample_out_rot_3 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_3); - - \IIR_CEL_STATE_RNISQ2Q5[2]\ : AO1 - port map(A => N_523, B => \IIR_CEL_STATE[4]_net_1\, C => - \IIR_CEL_STATE[2]_net_1\, Y => un1_IIR_CEL_STATE_27); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_13 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_5, B => - ADD_32x32_fast_I129_un1_Y_4, C => - ADD_32x32_fast_I129_un1_Y_11, Y => - ADD_32x32_fast_I129_un1_Y_13); - - \Chanel_ongoing_RNIE545[14]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_12, B => - Cel_ongoing_0_sqmuxa_0_a2_0_11, C => - Cel_ongoing_0_sqmuxa_0_a2_0_22, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_26); - - \IIR_CEL_STATE_RNI9V445[4]\ : OR2B - port map(A => N_328, B => \IIR_CEL_STATE[4]_net_1\, Y => - N_248); - - \IIR_CEL_STATE_i_RNILP76[9]\ : OR3 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay, C => \IIR_CEL_STATE[4]_net_1\, Y => - N_453); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \Cel_ongoing[22]_net_1\, B => - \Cel_ongoing[23]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_4); - - un1_IIR_CEL_STATE_17_m50 : AX1E - port map(A => \Cel_ongoing[17]_net_1\, B => N_48, C => - \Cel_ongoing[18]_net_1\, Y => N_51); - - \IIR_CEL_STATE_i_RNIEAL96[9]\ : OR2B - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_s_0_0, B => - N_452, Y => un1_alu_sel_input_0_sqmuxa_2_i_0_0); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y : NOR3C - port map(A => \Cel_ongoing[13]_net_1\, B => N_28_0, C => - ADD_32x32_fast_I129_un1_Y_14, Y => I129_un1_Y); - - \IIR_CEL_STATE[2]\ : DFN1E1 - port map(D => N_477, CLK => HCLK_c, E => HRESETn_c, Q => - \IIR_CEL_STATE[2]_net_1\); - - \Chanel_ongoing[13]\ : DFN1E1C0 - port map(D => N_224, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[13]_net_1\); - - \Chanel_ongoing[12]\ : DFN1E1C0 - port map(D => N_216, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[12]_net_1\); - - ram_write_RNO_0 : NOR2 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[7]_net_1\, Y => ram_write_2_0_a2_0); - - un1_IIR_CEL_STATE_17_m34 : XNOR2 - port map(A => N_20_0, B => \Cel_ongoing[5]_net_1\, Y => - N_35_0); - - \IIR_CEL_STATE_i_RNIEAL96_0[9]\ : OR2B - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_s_0_0, B => - N_452, Y => un1_alu_sel_input_0_sqmuxa_2_i_0); - - \Cel_ongoing_RNO_0[0]\ : AOI1B - port map(A => \Cel_ongoing_6_i_i_a2_0_0[0]\, B => N_328, C - => \Cel_ongoing_6_i_i_0[0]\, Y => - \Cel_ongoing_6_i_i_1[0]\); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \Cel_ongoing[15]_net_1\, B => - \Cel_ongoing[14]_net_1\, C => ADD_32x32_fast_I129_un1_Y_1, - Y => ADD_32x32_fast_I129_un1_Y_8); - - sample_out_rot_1 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_1); - - \Chanel_ongoing_RNI9OEE[24]\ : OR2A - port map(A => \Chanel_ongoing[24]_net_1\, B => N_288, Y => - N_290); - - \Cel_ongoing_RNO[31]\ : XA1 - port map(A => \Cel_ongoing[31]_net_1\, B => N_75, C => - N_371, Y => N_450); - - \Cel_ongoing_RNIRLC8[27]\ : NOR2 - port map(A => \Cel_ongoing[27]_net_1\, B => - \Cel_ongoing[28]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_14[1]\); - - \Chanel_ongoing_RNO[31]\ : XA1C - port map(A => \Chanel_ongoing[31]_net_1\, B => N_335, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n31); - - \Chanel_ongoing_RNIH791[25]\ : NOR2 - port map(A => \Chanel_ongoing[25]_net_1\, B => - \Chanel_ongoing[26]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_8); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_11 : NOR3C - port map(A => \Cel_ongoing[27]_net_1\, B => - \Cel_ongoing[26]_net_1\, C => ADD_32x32_fast_I129_un1_Y_7, - Y => ADD_32x32_fast_I129_un1_Y_11); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_14 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_9, B => - ADD_32x32_fast_I129_un1_Y_8, C => - ADD_32x32_fast_I129_un1_Y_13, Y => - ADD_32x32_fast_I129_un1_Y_14); - - \Chanel_ongoing[11]\ : DFN1E1C0 - port map(D => N_462, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[11]_net_1\); - - \IIR_CEL_STATE[4]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[3]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[4]_net_1\); - - \Chanel_ongoing_RNI3PO5[15]\ : NOR3C - port map(A => Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_2, B => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_1, C => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_6, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_7); - - un1_IIR_CEL_STATE_17_m21 : NOR3C - port map(A => \Cel_ongoing[5]_net_1\, B => N_20_0, C => - \Cel_ongoing[6]_net_1\, Y => N_22_0); - - \IIR_CEL_STATE_i_RNI16EG5[9]\ : OR2A - port map(A => N_371, B => N_274, Y => N_127_0); - - \alu_selected_coeff_RNO[1]\ : NOR2B - port map(A => S_i_0(33), B => N_371, Y => N_712); - - \IIR_CEL_STATE_RNI3D16[1]\ : NOR3A - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - \IIR_CEL_STATE[0]_net_1\, C => \IIR_CEL_STATE[1]_net_1\, - Y => N_6); - - \Cel_ongoing_RNIJEQD[6]\ : NOR2 - port map(A => \Cel_ongoing[5]_net_1\, B => - \Cel_ongoing[6]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_2[1]\); - - un1_IIR_CEL_STATE_17_m30 : XNOR2 - port map(A => N_16_0, B => \Cel_ongoing[1]_net_1\, Y => - N_31_0); - - \Chanel_ongoing_RNO[20]\ : XA1C - port map(A => \Chanel_ongoing[20]_net_1\, B => N_278, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n20); - - \Chanel_ongoing[20]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n20, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[20]_net_1\); - - \Chanel_ongoing_RNIUQV[7]\ : NOR2 - port map(A => \Chanel_ongoing[7]_net_1\, B => - \Chanel_ongoing[9]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_3); - - \Chanel_ongoing_RNIFUT[1]\ : NOR2 - port map(A => \Chanel_ongoing[1]_net_1\, B => - \Chanel_ongoing[0]_net_1\, Y => N_479); - - GND_i : GND - port map(Y => \GND\); - - \Chanel_ongoing[27]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n27, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[27]_net_1\); - - \Cel_ongoing_RNO[25]\ : XA1 - port map(A => \Cel_ongoing[25]_net_1\, B => N_64, C => - N_371, Y => N_444); - - \Chanel_ongoing_RNO_0[7]\ : XOR2 - port map(A => \Chanel_ongoing[7]_net_1\, B => N_254, Y => - Chanel_ongoing_n7_0_i_0_0); - - un1_IIR_CEL_STATE_17_m71 : NOR2B - port map(A => N_70, B => \Cel_ongoing[28]_net_1\, Y => N_72); - - \Chanel_ongoing_RNII4QD[23]\ : OR2A - port map(A => \Chanel_ongoing[23]_net_1\, B => - \Chanel_ongoing_RNISG5D[13]_net_1\, Y => N_288); - - \alu_selected_coeff_RNIR19H[2]\ : OR2A - port map(A => \alu_sel_coeff[2]\, B => S(8), Y => N_717); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - raddr_add1_RNO_0 : OR3 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay, C => \IIR_CEL_STATE[3]_net_1\, Y => - N_737); - - \Chanel_ongoing_RNO_0[12]\ : AX1E - port map(A => \Chanel_ongoing[11]_net_1\, B => N_258, C => - \Chanel_ongoing[12]_net_1\, Y => N_216_tz); - - \Chanel_ongoing_RNI9Q63[19]\ : NOR3C - port map(A => \Chanel_ongoing[20]_net_1\, B => - \Chanel_ongoing[19]_net_1\, C => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_4, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_6); - - sample_out_rot_0 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_0); - - \Chanel_ongoing_RNIF71H[28]\ : OR2A - port map(A => \Chanel_ongoing[28]_net_1\, B => N_293, Y => - N_295); - - \IIR_CEL_STATE[5]\ : DFN1E1 - port map(D => N_204, CLK => HCLK_c, E => HRESETn_c, Q => - \IIR_CEL_STATE[5]_net_1\); - - \Cel_ongoing[25]\ : DFN1C0 - port map(D => N_444, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[25]_net_1\); - - \IIR_CEL_STATE_RNO[5]\ : OR2A - port map(A => N_248, B => N_353, Y => N_204); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_5 : NOR2B - port map(A => \Cel_ongoing[24]_net_1\, B => - \Cel_ongoing[25]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_5); - - \Chanel_ongoing[18]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n18, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[18]_net_1\); - - \Chanel_ongoing[16]\ : DFN1E1C0 - port map(D => N_232, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[16]_net_1\); - - \alu_selected_coeff[3]\ : DFN1E1C0 - port map(D => N_714, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => \alu_sel_coeff[3]\); - - \Chanel_ongoing_RNITMT1[22]\ : NOR3C - port map(A => \Chanel_ongoing[14]_net_1\, B => - \Chanel_ongoing[22]_net_1\, C => - \Chanel_ongoing[21]_net_1\, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_4); - - \Cel_ongoing_RNO[15]\ : XA1 - port map(A => \Cel_ongoing[15]_net_1\, B => N_44, C => - N_371_0, Y => \Cel_ongoing_RNO[15]_net_1\); - - un1_IIR_CEL_STATE_17_m67 : NOR2B - port map(A => N_66, B => \Cel_ongoing[26]_net_1\, Y => N_68); - - \alu_ctrl[0]\ : DFN1E0C0 - port map(D => N_568_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(0)); - - raddr_add1_RNO_1 : OR3B - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => N_289, C => - \IIR_CEL_STATE[3]_net_1\, Y => N_735); - - \Chanel_ongoing_RNI7791[20]\ : NOR2 - port map(A => \Chanel_ongoing[20]_net_1\, B => - \Chanel_ongoing[21]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_14); - - \Cel_ongoing_RNIU5UA1[31]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_2[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_1[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_15[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_23[1]\); - - un1_IIR_CEL_STATE_17_m23 : NOR3C - port map(A => \Cel_ongoing[7]_net_1\, B => N_22_0, C => - \Cel_ongoing[8]_net_1\, Y => N_24_0); - - \Chanel_ongoing_RNI2NL8[15]\ : OR2A - port map(A => \Chanel_ongoing[15]_net_1\, B => N_271, Y => - N_272); - - \Chanel_ongoing[14]\ : DFN1E1C0 - port map(D => N_724, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[14]_net_1\); - - \IIR_CEL_STATE_i_RNIO893[9]\ : NOR2A - port map(A => sample_val_delay, B => - \IIR_CEL_STATE_i[9]_net_1\, Y => N_274); - - \alu_ctrl[2]\ : DFN1E0C0 - port map(D => \IIR_CEL_STATE_i_i[9]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \IIR_CEL_STATE[2]_net_1\, Q => - alu_ctrl(2)); - - \Chanel_ongoing_RNO[10]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0, B => - N_373_i, Y => N_461); - - \ram_sel_Wdata[1]\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_22, CLK => HCLK_c, CLR => - HRESETn_c, E => \IIR_CEL_STATE[8]_net_1\, Q => - ram_sel_Wdata(1)); - - \IIR_CEL_STATE_RNIN1T5[5]\ : NOR2 - port map(A => \IIR_CEL_STATE[0]_net_1\, B => - \IIR_CEL_STATE[5]_net_1\, Y => un1_IIR_CEL_STATE_22_0_0); - - \Chanel_ongoing_RNIBV81[15]\ : NOR2B - port map(A => \Chanel_ongoing[15]_net_1\, B => - \Chanel_ongoing[16]_net_1\, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_1); - - \Cel_ongoing_RNO[4]\ : NOR2A - port map(A => N_371_0, B => N_34_0, Y => - \Cel_ongoing_RNO[4]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \Chanel_ongoing_RNO_0[11]\ : XNOR2 - port map(A => N_258, B => \Chanel_ongoing[11]_net_1\, Y => - N_374_i); - - \Chanel_ongoing_RNID791[23]\ : NOR2 - port map(A => \Chanel_ongoing[23]_net_1\, B => - \Chanel_ongoing[24]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_7); - - \Cel_ongoing[4]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[4]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[4]_net_1\); - - \Chanel_ongoing_RNO[21]\ : XA1C - port map(A => \Chanel_ongoing[21]_net_1\, B => N_279, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n21); - - \Chanel_ongoing_RNI76JA[18]\ : OR2B - port map(A => N_275, B => \Chanel_ongoing[18]_net_1\, Y => - N_276); - - \Chanel_ongoing_RNO[29]\ : XA1C - port map(A => \Chanel_ongoing[29]_net_1\, B => N_295, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n29); - - \Chanel_ongoing_RNIJ9SB[20]\ : OR2A - port map(A => \Chanel_ongoing[20]_net_1\, B => N_278, Y => - N_279); - - \alu_ctrl[1]\ : DFN1E0C0 - port map(D => N_569, CLK => HCLK_c, CLR => HRESETn_c, E => - \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(1)); - - sample_out_val : DFN1E0C0 - port map(D => \IIR_CEL_STATE[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => N_353, Q => sample_out_val_s); - - raddr_add1_RNO_3 : OR2A - port map(A => \IIR_CEL_STATE[3]_net_1\, B => N_274, Y => - raddr_add1_2_i_a2_0_0); - - \Chanel_ongoing[31]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n31, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[31]_net_1\); - - un1_IIR_CEL_STATE_17_m29 : XNOR2 - port map(A => N_566, B => \Cel_ongoing[0]_net_1\, Y => - \un1_IIR_CEL_STATE_17_i_1_i_0[31]\); - - \IIR_CEL_STATE_RNI0UV8[4]\ : NOR2A - port map(A => N_6, B => \IIR_CEL_STATE[4]_net_1\, Y => - N_566); - - \Cel_ongoing_RNI679Q4[12]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_26[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_25[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_27[1]\, Y => N_325_i); - - sample_out_rot_2 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_2); - - \Chanel_ongoing_RNI53M8[6]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_16, B => - Cel_ongoing_0_sqmuxa_0_a2_0_15, C => - Cel_ongoing_0_sqmuxa_0_a2_0_24, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_27); - - \Chanel_ongoing_RNIO6I2[18]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_14, B => - \Chanel_ongoing[19]_net_1\, C => - \Chanel_ongoing[18]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_22); - - \Chanel_ongoing_RNI1C3F[25]\ : NOR2A - port map(A => \Chanel_ongoing[25]_net_1\, B => N_290, Y => - N_291); - - un1_IIR_CEL_STATE_17_m19 : NOR3C - port map(A => \Cel_ongoing[3]_net_1\, B => N_18_0, C => - \Cel_ongoing[4]_net_1\, Y => N_20_0); - - \IIR_CEL_STATE_RNI9T4D5[4]\ : OR2A - port map(A => N_248, B => N_566, Y => N_371_0); - - un1_IIR_CEL_STATE_17_m46 : AX1E - port map(A => \Cel_ongoing[15]_net_1\, B => N_44, C => - \Cel_ongoing[16]_net_1\, Y => N_47); - - \Chanel_ongoing_RNIKJCG[27]\ : OR2A - port map(A => \Chanel_ongoing[27]_net_1\, B => N_292, Y => - N_293); - - \Chanel_ongoing_RNI39F5[10]\ : NOR3C - port map(A => \Chanel_ongoing[9]_net_1\, B => N_256, C => - \Chanel_ongoing[10]_net_1\, Y => N_258); - - \waddr_previous[1]\ : DFN1E0C0 - port map(D => N_729, CLK => HCLK_c, CLR => HRESETn_c, E => - \IIR_CEL_STATE[8]_net_1\, Q => waddr_previous(1)); - - un1_IIR_CEL_STATE_17_m37 : AX1E - port map(A => \Cel_ongoing[7]_net_1\, B => N_22_0, C => - \Cel_ongoing[8]_net_1\, Y => N_38); - - un1_IIR_CEL_STATE_17_m25 : NOR3C - port map(A => \Cel_ongoing[9]_net_1\, B => N_24_0, C => - \Cel_ongoing[10]_net_1\, Y => N_26_0); - - \Cel_ongoing_RNIF5B8[22]\ : NOR2 - port map(A => \Cel_ongoing[21]_net_1\, B => - \Cel_ongoing[22]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_11[1]\); - - raddr_add1_RNO : NOR3C - port map(A => N_737, B => N_735, C => N_736, Y => N_723_i_0); - - un1_IIR_CEL_STATE_17_m15 : NOR2A - port map(A => \Cel_ongoing[0]_net_1\, B => N_566, Y => - N_16_0); - - \IIR_CEL_STATE_RNI1A4N5[4]\ : NOR2 - port map(A => N_796_i, B => N_480, Y => - \IIR_CEL_STATE_ns[8]\); - - \IIR_CEL_STATE[7]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[6]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[7]_net_1\); - - \IIR_CEL_STATE_RNIL1T5[1]\ : OR2 - port map(A => \IIR_CEL_STATE[2]_net_1\, B => - \IIR_CEL_STATE[1]_net_1\, Y => N_567_i_0); - - \Cel_ongoing[19]\ : DFN1C0 - port map(D => N_438, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[19]_net_1\); - - \Chanel_ongoing_RNO[11]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_0, B => - N_374_i, Y => N_462); - - \Chanel_ongoing_RNO[24]\ : XA1C - port map(A => \Chanel_ongoing[24]_net_1\, B => N_288, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n24); - - \Chanel_ongoing_RNO[19]\ : XA1C - port map(A => \Chanel_ongoing[19]_net_1\, B => N_276, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n19); - - \Chanel_ongoing_RNIN1V1[6]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_3, B => - \Chanel_ongoing[6]_net_1\, C => \Chanel_ongoing[5]_net_1\, - Y => Cel_ongoing_0_sqmuxa_0_a2_0_16); - - \Chanel_ongoing[15]\ : DFN1E1C0 - port map(D => N_229, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[15]_net_1\); - - \Cel_ongoing[31]\ : DFN1C0 - port map(D => N_450, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[31]_net_1\); - - \IIR_CEL_STATE_i_RNIPIDQ5[9]\ : OR2A - port map(A => \IIR_CEL_STATE_ns[8]\, B => N_274, Y => N_452); - - \Cel_ongoing_RNIJLB8[24]\ : NOR2 - port map(A => \Cel_ongoing[23]_net_1\, B => - \Cel_ongoing[24]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_12[1]\); - - \alu_selected_coeff_RNO[4]\ : NOR2A - port map(A => N_371, B => N_15_i, Y => N_715); - - \Cel_ongoing[30]\ : DFN1C0 - port map(D => N_449, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[30]_net_1\); - - \Chanel_ongoing_RNO_0[5]\ : XNOR2 - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252, Y => - Chanel_ongoing_n5_0_i_0_0); - - \Chanel_ongoing[6]\ : DFN1E1C0 - port map(D => N_22, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[6]_net_1\); - - \alu_selected_coeff_RNO_0[3]\ : XOR2 - port map(A => N_717, B => \alu_sel_coeff[3]\, Y => - alu_selected_coeff_n3_0_i_0); - - sample_out_rot : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s); - - \Chanel_ongoing[23]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n23, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[23]_net_1\); - - \Chanel_ongoing[22]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n22, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[22]_net_1\); - - sample_out_rot_4 : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_4); - - \Cel_ongoing_RNO[7]\ : XA1 - port map(A => \Cel_ongoing[7]_net_1\, B => N_22_0, C => - N_371_0, Y => \Cel_ongoing_RNO[7]_net_1\); - - ram_write_RNI0IG : INV - port map(A => ram_write_net_1, Y => ram_write_i); - - \IIR_CEL_STATE_RNI012A5[5]\ : OR2B - port map(A => un1_IIR_CEL_STATE_22_0_0, B => N_480, Y => - un1_IIR_CEL_STATE_22); - - \in_sel_src_RNO[0]\ : MX2A - port map(A => N_334, B => N_332, S => - \IIR_CEL_STATE[5]_net_1\, Y => N_268_i_0); - - \waddr_previous[0]\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_25, CLK => HCLK_c, CLR => - HRESETn_c, E => \IIR_CEL_STATE[8]_net_1\, Q => - waddr_previous(0)); - - \Chanel_ongoing_RNI68O6[12]\ : OR3C - port map(A => \Chanel_ongoing[11]_net_1\, B => N_258, C => - \Chanel_ongoing[12]_net_1\, Y => N_265); - - \alu_selected_coeff_0[2]\ : DFN1E1C0 - port map(D => N_713, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => \alu_sel_coeff_0[2]\); - - \Chanel_ongoing[21]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n21, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[21]_net_1\); - - \alu_selected_coeff_0[0]\ : DFN1E1C0 - port map(D => alu_selected_coeff_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => alu_selected_coeffe, Q => - alu_sel_coeff_0_0); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_9 : NOR3C - port map(A => \Cel_ongoing[19]_net_1\, B => - \Cel_ongoing[18]_net_1\, C => ADD_32x32_fast_I129_un1_Y_3, - Y => ADD_32x32_fast_I129_un1_Y_9); - - \Cel_ongoing_RNO[22]\ : NOR2A - port map(A => N_371, B => N_59, Y => N_441); - - \Chanel_ongoing_RNIDPT1[8]\ : NOR3B - port map(A => \Chanel_ongoing[3]_net_1\, B => - Cel_ongoing_0_sqmuxa_0_a2_0_1, C => - \Chanel_ongoing[8]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_15); - - un1_IIR_CEL_STATE_17_m51 : NOR3C - port map(A => \Cel_ongoing[17]_net_1\, B => N_48, C => - \Cel_ongoing[18]_net_1\, Y => N_52); - - \Chanel_ongoing_RNO[14]\ : XA1C - port map(A => \Chanel_ongoing[14]_net_1\, B => N_270, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => N_724); - - \Cel_ongoing_RNISAMG[12]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_6[1]\, B => - \Cel_ongoing[12]_net_1\, C => \Cel_ongoing[11]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_18[1]\); - - \Cel_ongoing_RNIKTB8[20]\ : NOR2 - port map(A => \Cel_ongoing[19]_net_1\, B => - \Cel_ongoing[20]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_10[1]\); - - \raddr_rst\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_20, CLK => HCLK_c, CLR => - HRESETn_c, E => N_353, Q => raddr_rst); - - \Chanel_ongoing_RNIO6A9[16]\ : OR2A - port map(A => \Chanel_ongoing[16]_net_1\, B => N_272, Y => - N_273); - - \Cel_ongoing_RNO[3]\ : NOR2A - port map(A => N_371_0, B => N_33_0, Y => - \Cel_ongoing_RNO[3]_net_1\); - - \Chanel_ongoing_RNI18P4[1]\ : NOR3C - port map(A => N_479, B => Cel_ongoing_0_sqmuxa_0_a2_0_4, C - => Cel_ongoing_0_sqmuxa_0_a2_0_18, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_24); - - \IIR_CEL_STATE_i_RNO[9]\ : MX2B - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => N_180, S => - HRESETn_c, Y => N_512_i_0); - - \Chanel_ongoing_RNISG5D[13]\ : OR2A - port map(A => Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_7, B => - N_270, Y => \Chanel_ongoing_RNISG5D[13]_net_1\); - - un1_IIR_CEL_STATE_17_m47 : NOR3C - port map(A => \Cel_ongoing[15]_net_1\, B => N_44, C => - \Cel_ongoing[16]_net_1\, Y => N_48); - - \Chanel_ongoing_RNO[26]\ : XA1B - port map(A => \Chanel_ongoing[26]_net_1\, B => N_291, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n26); - - \Cel_ongoing[18]\ : DFN1C0 - port map(D => N_437, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[18]_net_1\); - - \alu_selected_coeff_0_RNIF4EQ5[2]\ : NOR2B - port map(A => alu_selected_coeff_n2_0_i_0, B => N_371_0, Y - => N_713); - - \Chanel_ongoing_RNIHAI2[31]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_6, B => - \Chanel_ongoing[12]_net_1\, C => - \Chanel_ongoing[31]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_18); - - \Cel_ongoing_RNO[12]\ : NOR2A - port map(A => N_371_0, B => N_42, Y => - \Cel_ongoing_RNO[12]_net_1\); - - \Cel_ongoing_RNI2K2B[10]\ : NOR2 - port map(A => \Cel_ongoing[9]_net_1\, B => - \Cel_ongoing[10]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_4[1]\); - - \alu_selected_coeff[0]\ : DFN1E1C0 - port map(D => alu_selected_coeff_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => alu_selected_coeffe, Q => - \alu_sel_coeff[0]\); - - \Chanel_ongoing[19]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n19, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[19]_net_1\); - - \Cel_ongoing_RNI4P5K5[2]\ : OR2A - port map(A => N_796_i, B => N_328, Y => N_523); - - \Cel_ongoing[16]\ : DFN1C0 - port map(D => N_435, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[16]_net_1\); - - un1_IIR_CEL_STATE_17_m63 : NOR3C - port map(A => \Cel_ongoing[23]_net_1\, B => N_60, C => - \Cel_ongoing[24]_net_1\, Y => N_64); - - \Chanel_ongoing_RNO[0]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_0, B => - \Chanel_ongoing[0]_net_1\, Y => Chanel_ongoing_n0); - - GND_i_0 : GND - port map(Y => GND_0); - - \Chanel_ongoing_RNO[25]\ : XA1C - port map(A => \Chanel_ongoing[25]_net_1\, B => N_290, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n25); - - \in_sel_src_RNO[1]\ : MX2 - port map(A => \in_sel_src_8_i_a2_0_a2_0_0[1]\, B => N_289, - S => N_332, Y => N_269); - - \Cel_ongoing_RNO[23]\ : XA1 - port map(A => \Cel_ongoing[23]_net_1\, B => N_60, C => - N_371, Y => N_442); - - \Chanel_ongoing[28]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n28, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[28]_net_1\); - - un1_IIR_CEL_STATE_17_m31 : AX1C - port map(A => \Cel_ongoing[1]_net_1\, B => N_16_0, C => - \Cel_ongoing[2]_net_1\, Y => N_32_0_i_0); - - \Chanel_ongoing[26]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n26, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[26]_net_1\); - - \Chanel_ongoing_RNO[4]\ : NOR2 - port map(A => Chanel_ongoing_n4_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_11); - - \Cel_ongoing_RNIF5B8[30]\ : NOR2 - port map(A => \Cel_ongoing[13]_net_1\, B => - \Cel_ongoing[30]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_6[1]\); - - \Chanel_ongoing[2]\ : DFN1E1C0 - port map(D => N_703, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[2]_net_1\); - - \Chanel_ongoing_RNI1V81[10]\ : NOR2 - port map(A => \Chanel_ongoing[10]_net_1\, B => - \Chanel_ongoing[11]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_4); - - \Chanel_ongoing_RNO[6]\ : NOR2 - port map(A => Chanel_ongoing_n6_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_22); - - \IIR_CEL_STATE[6]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[5]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[6]_net_1\); - - \Cel_ongoing[17]\ : DFN1C0 - port map(D => N_436, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[17]_net_1\); - - \Chanel_ongoing[24]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n24, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[24]_net_1\); - - \Cel_ongoing_RNO[2]\ : AO1 - port map(A => N_32_0_i_0, B => N_371, C => - \IIR_CEL_STATE_ns[8]\, Y => N_227); - - \Cel_ongoing_RNIS89F[31]\ : NOR3 - port map(A => \Cel_ongoing[1]_net_1\, B => - \Cel_ongoing[31]_net_1\, C => \Cel_ongoing[29]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_15[1]\); - - \Cel_ongoing[11]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[11]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[11]_net_1\); - - un1_IIR_CEL_STATE_17_m62 : AX1E - port map(A => \Cel_ongoing[23]_net_1\, B => N_60, C => - \Cel_ongoing[24]_net_1\, Y => N_63); - - \Chanel_ongoing_RNO[2]\ : NOR2A - port map(A => Chanel_ongoing_n2_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_703); - - \Cel_ongoing[10]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[10]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[10]_net_1\); - - \IIR_CEL_STATE_i_RNI16EG5_0[9]\ : OR2A - port map(A => N_371, B => N_274, Y => N_127); - - \Cel_ongoing_RNO[13]\ : XA1 - port map(A => \Cel_ongoing[13]_net_1\, B => N_28_0, C => - N_371, Y => \Cel_ongoing_RNO[13]_net_1\); - - \Cel_ongoing_RNO[24]\ : NOR2A - port map(A => N_371, B => N_63, Y => N_443); - - \Chanel_ongoing_RNO[16]\ : XA1C - port map(A => \Chanel_ongoing[16]_net_1\, B => N_272, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => N_232); - - \Chanel_ongoing_RNI0M7B[19]\ : OR2A - port map(A => \Chanel_ongoing[19]_net_1\, B => N_276, Y => - N_278); - - \Cel_ongoing_RNO[20]\ : NOR2A - port map(A => N_371_0, B => N_55, Y => N_439); - - \Cel_ongoing[5]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[5]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[5]_net_1\); - - \Cel_ongoing[29]\ : DFN1C0 - port map(D => N_448, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[29]_net_1\); - - \IIR_CEL_STATE_i_RNIBA69[9]\ : AO1D - port map(A => sample_val_delay, B => - \IIR_CEL_STATE_i[9]_net_1\, C => N_294, Y => - un1_IIR_CEL_STATE_20); - - \Chanel_ongoing_RNO_0[1]\ : XNOR2 - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, Y => Chanel_ongoing_n1_0_i_0_0); - - \Chanel_ongoing_RNO[27]\ : XA1C - port map(A => \Chanel_ongoing[27]_net_1\, B => N_292, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n27); - - \waddr_previous_RNO[0]\ : OR2A - port map(A => N_248, B => N_334, Y => un1_IIR_CEL_STATE_25); - - un1_IIR_CEL_STATE_17_m69 : NOR2B - port map(A => N_68, B => \Cel_ongoing[27]_net_1\, Y => N_70); - - \ram_sel_Wdata[0]\ : DFN1E0C0 - port map(D => N_567_i_0, CLK => HCLK_c, CLR => HRESETn_c, E - => \IIR_CEL_STATE[8]_net_1\, Q => ram_sel_Wdata(0)); - - un1_IIR_CEL_STATE_17_m74 : NOR3C - port map(A => \Cel_ongoing[29]_net_1\, B => - \Cel_ongoing[30]_net_1\, C => N_72, Y => N_75); - - \Chanel_ongoing[4]\ : DFN1E1C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[4]_net_1\); - - \Cel_ongoing_RNO[0]\ : OAI1 - port map(A => N_480, B => un1_IIR_CEL_STATE_20, C => - \Cel_ongoing_6_i_i_1[0]\, Y => N_206); - - \IIR_CEL_STATE_RNI9V445_0[4]\ : OR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_328, Y => - N_480); - - \Chanel_ongoing_RNO_0[31]\ : OR2A - port map(A => \Chanel_ongoing[30]_net_1\, B => N_327, Y => - N_335); - - \Chanel_ongoing_RNI8391[13]\ : NOR2 - port map(A => \Chanel_ongoing[13]_net_1\, B => - \Chanel_ongoing[22]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_6); - - \Chanel_ongoing_RNO_0[10]\ : AX1E - port map(A => \Chanel_ongoing[9]_net_1\, B => N_256, C => - \Chanel_ongoing[10]_net_1\, Y => N_373_i); - - \Chanel_ongoing_RNO[8]\ : NOR2 - port map(A => Chanel_ongoing_n8_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_651); - - \IIR_CEL_STATE_RNIJ1T5[1]\ : OR2 - port map(A => \IIR_CEL_STATE[1]_net_1\, B => - \IIR_CEL_STATE[0]_net_1\, Y => N_294); - - \Chanel_ongoing_RNO[15]\ : XA1C - port map(A => \Chanel_ongoing[15]_net_1\, B => N_271, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => N_229); - - \Chanel_ongoing[7]\ : DFN1E1C0 - port map(D => N_650, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[7]_net_1\); - - \Cel_ongoing_RNO[8]\ : NOR2A - port map(A => N_371_0, B => N_38, Y => - \Cel_ongoing_RNO[8]_net_1\); - - \Cel_ongoing[13]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[13]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[13]_net_1\); - - \Cel_ongoing[12]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[12]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[12]_net_1\); - - \Chanel_ongoing_RNO[22]\ : XA1C - port map(A => \Chanel_ongoing[22]_net_1\, B => N_725, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n22); - - un1_IIR_CEL_STATE_17_m65 : NOR2B - port map(A => N_64, B => \Cel_ongoing[25]_net_1\, Y => N_66); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \Cel_ongoing[16]_net_1\, B => - \Cel_ongoing[17]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_1); - - \Chanel_ongoing_RNO[28]\ : XA1C - port map(A => \Chanel_ongoing[28]_net_1\, B => N_293, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n28); - - \Cel_ongoing_RNO[14]\ : NOR2A - port map(A => N_371_0, B => \un1_IIR_CEL_STATE_17_i[17]\, Y - => \Cel_ongoing_RNO[14]_net_1\); - - \Cel_ongoing_RNO[1]\ : NOR2A - port map(A => N_371, B => N_31_0, Y => - \Cel_ongoing_RNO[1]_net_1\); - - un1_IIR_CEL_STATE_17_m33 : AX1E - port map(A => \Cel_ongoing[3]_net_1\, B => N_18_0, C => - \Cel_ongoing[4]_net_1\, Y => N_34_0); - - \Cel_ongoing_RNO[10]\ : NOR2A - port map(A => N_371_0, B => N_40, Y => - \Cel_ongoing_RNO[10]_net_1\); - - \Cel_ongoing_RNICE615[2]\ : OR2B - port map(A => N_325_i, B => \Cel_ongoing[2]_net_1\, Y => - N_328); - - un1_IIR_CEL_STATE_17_m59 : NOR3C - port map(A => \Cel_ongoing[21]_net_1\, B => N_56, C => - \Cel_ongoing[22]_net_1\, Y => N_60); - - \Chanel_ongoing_RNI7JI2[27]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_10, B => - \Chanel_ongoing[28]_net_1\, C => - \Chanel_ongoing[27]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_20); - - \IIR_CEL_STATE_i_RNIDS23[9]\ : NOR2A - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => N_733_1); - - \Chanel_ongoing_RNI5255[23]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_8, B => - Cel_ongoing_0_sqmuxa_0_a2_0_7, C => - Cel_ongoing_0_sqmuxa_0_a2_0_20, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_25); - - \Cel_ongoing_RNIL5C8[16]\ : NOR2 - port map(A => \Cel_ongoing[15]_net_1\, B => - \Cel_ongoing[16]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_8[1]\); - - \Cel_ongoing[6]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[6]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[6]_net_1\); - - \IIR_CEL_STATE[3]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[7]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[3]_net_1\); - - \Cel_ongoing_RNO[29]\ : XA1 - port map(A => \Cel_ongoing[29]_net_1\, B => N_72, C => - N_371, Y => N_448); - - raddr_add1_RNO_2 : OR2A - port map(A => N_328, B => raddr_add1_2_i_a2_0_0, Y => N_736); - - \Chanel_ongoing_RNI9V81[14]\ : NOR2 - port map(A => \Chanel_ongoing[14]_net_1\, B => - \Chanel_ongoing[15]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_11); - - \Chanel_ongoing[0]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[0]_net_1\); - - \Cel_ongoing_RNO[6]\ : NOR2A - port map(A => N_371_0, B => N_36_0, Y => - \Cel_ongoing_RNO[6]_net_1\); - - \Cel_ongoing[14]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[14]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[14]_net_1\); - - \alu_selected_coeff_0_RNI679D[2]\ : XNOR2 - port map(A => S(8), B => \alu_sel_coeff_0[2]\, Y => - alu_selected_coeff_n2_0_i_0); - - un1_IIR_CEL_STATE_17_m55 : NOR3C - port map(A => \Cel_ongoing[19]_net_1\, B => N_52, C => - \Cel_ongoing[20]_net_1\, Y => N_56); - - \Cel_ongoing[9]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[9]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[9]_net_1\); - - sample_in_rot : DFN1E0C0 - port map(D => sample_in_rot_2, CLK => HCLK_c, CLR => - HRESETn_c, E => N_353, Q => sample_in_rotate); - - \Chanel_ongoing_RNO[17]\ : XA1C - port map(A => \Chanel_ongoing[17]_net_1\, B => N_273, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n17); - - \alu_selected_coeff[1]\ : DFN1E1C0 - port map(D => N_712, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => alu_sel_coeff(1)); - - \Cel_ongoing[8]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[8]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[8]_net_1\); - - un1_IIR_CEL_STATE_17_m32 : XNOR2 - port map(A => N_18_0, B => \Cel_ongoing[3]_net_1\, Y => - N_33_0); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I174_Y_0 : AX1E - port map(A => \Cel_ongoing[13]_net_1\, B => N_28_0, C => - \Cel_ongoing[14]_net_1\, Y => - \un1_IIR_CEL_STATE_17_i[17]\); - - \IIR_CEL_STATE[8]\ : DFN1E1 - port map(D => N_274, CLK => HCLK_c, E => HRESETn_c, Q => - \IIR_CEL_STATE[8]_net_1\); - - un1_IIR_CEL_STATE_17_m41 : AX1E - port map(A => \Cel_ongoing[11]_net_1\, B => N_26_0, C => - \Cel_ongoing[12]_net_1\, Y => N_42); - - \raddr_add1\ : DFN1C0 - port map(D => N_723_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => raddr_add1); - - \IIR_CEL_STATE[1]\ : DFN1E1 - port map(D => \IIR_CEL_STATE_ns[8]\, CLK => HCLK_c, E => - HRESETn_c, Q => \IIR_CEL_STATE[1]_net_1\); - - \alu_sel_input\ : DFN1E0C0 - port map(D => alu_sel_input_1, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_IIR_CEL_STATE_20, Q => alu_sel_input); - - un1_IIR_CEL_STATE_17_m58 : AX1E - port map(A => \Cel_ongoing[21]_net_1\, B => N_56, C => - \Cel_ongoing[22]_net_1\, Y => N_59); - - \ram_write\ : DFN1E0C0 - port map(D => ram_write_2, CLK => HCLK_c, CLR => HRESETn_c, - E => \IIR_CEL_STATE[8]_net_1\, Q => ram_write_net_1); - - \IIR_CEL_STATE_i_RNO_0[9]\ : AO1D - port map(A => sample_val_delay, B => - \IIR_CEL_STATE_i[9]_net_1\, C => \IIR_CEL_STATE[0]_net_1\, - Y => N_180); - - \Chanel_ongoing[10]\ : DFN1E1C0 - port map(D => N_461, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127_0, Q => \Chanel_ongoing[10]_net_1\); - - \in_sel_src[1]\ : DFN1E0C0 - port map(D => N_269, CLK => HCLK_c, CLR => HRESETn_c, E => - un1_IIR_CEL_STATE_27, Q => in_sel_src(1)); - - \IIR_CEL_STATE_RNI9T4D5_0[4]\ : OR2A - port map(A => N_248, B => N_566, Y => N_371); - - \Chanel_ongoing[17]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n17, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127_0, Q => \Chanel_ongoing[17]_net_1\); - - \Cel_ongoing[7]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[7]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[7]_net_1\); - - \Cel_ongoing_RNO[30]\ : XA1 - port map(A => \Cel_ongoing[30]_net_1\, B => I129_un1_Y, C - => N_371, Y => N_449); - - \Cel_ongoing[28]\ : DFN1C0 - port map(D => N_447, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[28]_net_1\); - - un1_IIR_CEL_STATE_17_m39 : AX1E - port map(A => \Cel_ongoing[9]_net_1\, B => N_24_0, C => - \Cel_ongoing[10]_net_1\, Y => N_40); - - \Chanel_ongoing_RNO[12]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0_0, B => - N_216_tz, Y => N_216); - - \Chanel_ongoing[25]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n25, CLK => HCLK_c, CLR => - HRESETn_c, E => N_127, Q => \Chanel_ongoing[25]_net_1\); - - \Cel_ongoing_RNO[19]\ : XA1 - port map(A => \Cel_ongoing[19]_net_1\, B => N_52, C => - N_371_0, Y => N_438); - - \Chanel_ongoing_RNIOAVI[6]\ : OR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_26, B => - Cel_ongoing_0_sqmuxa_0_a2_0_25, C => - Cel_ongoing_0_sqmuxa_0_a2_0_27, Y => N_796_i); - - \Cel_ongoing_RNO[28]\ : XA1 - port map(A => \Cel_ongoing[28]_net_1\, B => N_70, C => - N_371, Y => N_447); - - \Chanel_ongoing_RNO[18]\ : XA1B - port map(A => \Chanel_ongoing[18]_net_1\, B => N_275, C => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => - Chanel_ongoing_n18); - - \Cel_ongoing_RNIFEQD[4]\ : NOR2 - port map(A => \Cel_ongoing[3]_net_1\, B => - \Cel_ongoing[4]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_1[1]\); - - \Cel_ongoing_RNIVS741[16]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_8[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_7[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_20[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_25[1]\); - - \Chanel_ongoing_RNO[1]\ : NOR2 - port map(A => Chanel_ongoing_n1_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_18); - - \Cel_ongoing[26]\ : DFN1C0 - port map(D => N_445, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[26]_net_1\); - - \Cel_ongoing_RNIIROG[25]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_14[1]\, B => - \Cel_ongoing[26]_net_1\, C => \Cel_ongoing[25]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_22[1]\); - - sample_in_rot_RNI6EV7_0 : CLKINT - port map(A => \sample_in_rot_RNI6EV7\, Y => - un1_sample_in_rotate); - - \Chanel_ongoing[9]\ : DFN1E1C0 - port map(D => N_460, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[9]_net_1\); - - un1_IIR_CEL_STATE_17_m35 : AX1E - port map(A => \Cel_ongoing[5]_net_1\, B => N_20_0, C => - \Cel_ongoing[6]_net_1\, Y => N_36_0); - - \IIR_CEL_STATE_RNIS1T5[2]\ : OR2 - port map(A => \IIR_CEL_STATE[8]_net_1\, B => - \IIR_CEL_STATE[2]_net_1\, Y => N_353); - - \Chanel_ongoing_RNO[3]\ : AO1A - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0, B => - N_336_i_i_0, C => \IIR_CEL_STATE_ns[8]\, Y => N_221); - - \Chanel_ongoing_RNO[5]\ : NOR2 - port map(A => Chanel_ongoing_n5_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_20); - - \Cel_ongoing_RNIJJHK2[12]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_18[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_17[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_23[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_27[1]\); - - \alu_ctrl_RNO[1]\ : OR2 - port map(A => \IIR_CEL_STATE[8]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => N_569); - - \Cel_ongoing[3]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[3]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[3]_net_1\); - - \Chanel_ongoing_RNO_0[2]\ : AX1C - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, C => \Chanel_ongoing[2]_net_1\, - Y => Chanel_ongoing_n2_0_i_0_0); - - \Chanel_ongoing_RNO[9]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_2_i_0, B => - N_372_i, Y => N_460); - - \Cel_ongoing_RNO[18]\ : NOR2A - port map(A => N_371_0, B => N_51, Y => N_437); - - \IIR_CEL_STATE[0]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[1]_net_1\, CLK => HCLK_c, E - => HRESETn_c, Q => \IIR_CEL_STATE[0]_net_1\); - - \Cel_ongoing[27]\ : DFN1C0 - port map(D => N_446, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[27]_net_1\); - - \alu_selected_coeff[2]\ : DFN1E1C0 - port map(D => N_713, CLK => HCLK_c, CLR => HRESETn_c, E => - alu_selected_coeffe, Q => \alu_sel_coeff[2]\); - - \alu_ctrl_RNO[2]\ : INV - port map(A => \IIR_CEL_STATE_i[9]_net_1\, Y => - \IIR_CEL_STATE_i_i[9]\); - - un1_IIR_CEL_STATE_17_ADD_32x32_fast_I129_un1_Y_3 : NOR2B - port map(A => \Cel_ongoing[20]_net_1\, B => - \Cel_ongoing[21]_net_1\, Y => ADD_32x32_fast_I129_un1_Y_3); - - \Cel_ongoing[21]\ : DFN1C0 - port map(D => N_440, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[21]_net_1\); - - \Chanel_ongoing_RNIBRLH[29]\ : OR2A - port map(A => \Chanel_ongoing[29]_net_1\, B => N_295, Y => - N_327); - - sample_in_rot_RNI6EV7 : OR2 - port map(A => sample_val_delay, B => sample_in_rotate, Y - => \sample_in_rot_RNI6EV7\); - - \Cel_ongoing_RNO_2[0]\ : AOI1B - port map(A => \un1_IIR_CEL_STATE_17_i_1_i_0[31]\, B => N_6, - C => N_457, Y => \Cel_ongoing_6_i_i_0[0]\); - - \Cel_ongoing_RNO[27]\ : XA1 - port map(A => \Cel_ongoing[27]_net_1\, B => N_68, C => - N_371, Y => N_446); - - \Cel_ongoing[20]\ : DFN1C0 - port map(D => N_439, CLK => HCLK_c, CLR => HRESETn_c, Q => - \Cel_ongoing[20]_net_1\); - - \Chanel_ongoing_RNID718[14]\ : OR2A - port map(A => \Chanel_ongoing[14]_net_1\, B => N_270, Y => - N_271); - - un1_IIR_CEL_STATE_17_m43 : NOR3C - port map(A => \Cel_ongoing[13]_net_1\, B => N_28_0, C => - \Cel_ongoing[14]_net_1\, Y => N_44); - - \Chanel_ongoing_RNO_0[8]\ : AX1E - port map(A => \Chanel_ongoing[7]_net_1\, B => N_254, C => - \Chanel_ongoing[8]_net_1\, Y => Chanel_ongoing_n8_0_i_0_0); - - \Cel_ongoing[1]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[1]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \Cel_ongoing[1]_net_1\); - - \Chanel_ongoing_RNIDV81[16]\ : NOR2 - port map(A => \Chanel_ongoing[16]_net_1\, B => - \Chanel_ongoing[17]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_12); - - \Cel_ongoing_RNO[26]\ : XA1 - port map(A => \Cel_ongoing[26]_net_1\, B => N_66, C => - N_371, Y => N_445); - - \Chanel_ongoing_RNO_0[4]\ : AX1A - port map(A => N_250, B => \Chanel_ongoing[3]_net_1\, C => - \Chanel_ongoing[4]_net_1\, Y => Chanel_ongoing_n4_0_i_0_0); - - \Chanel_ongoing_RNO[7]\ : NOR2A - port map(A => Chanel_ongoing_n7_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_2_i_0_0, Y => N_650); - - \waddr_previous_RNO[1]\ : OR2 - port map(A => un1_IIR_CEL_STATE_22, B => N_567_i_0, Y => - N_729); - - un1_IIR_CEL_STATE_17_m27 : NOR3C - port map(A => \Cel_ongoing[11]_net_1\, B => N_26_0, C => - \Cel_ongoing[12]_net_1\, Y => N_28_0); - - \Chanel_ongoing_RNIFV81[17]\ : NOR2B - port map(A => \Chanel_ongoing[17]_net_1\, B => - \Chanel_ongoing[18]_net_1\, Y => - Chanel_ongoing_n23_0_0_0_o2_m6_0_a2_2); - - \alu_ctrl_RNO[0]\ : OR3 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[6]_net_1\, C => N_289, Y => N_568_i_0); - - \Chanel_ongoing_RNO[23]\ : XA1C - port map(A => \Chanel_ongoing[23]_net_1\, B => - \Chanel_ongoing_RNISG5D[13]_net_1\, C => - un1_alu_sel_input_0_sqmuxa_2_i_0, Y => Chanel_ongoing_n23); - - \Chanel_ongoing[5]\ : DFN1E1C0 - port map(D => N_20, CLK => HCLK_c, CLR => HRESETn_c, E => - N_127, Q => \Chanel_ongoing[5]_net_1\); - - \Cel_ongoing_RNO_3[0]\ : OR3A - port map(A => N_274, B => N_294, C => - \IIR_CEL_STATE[4]_net_1\, Y => N_457); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2 is - - port( sample_filter_v2_out_0 : out std_logic; - sample_filter_v2_out_1 : out std_logic; - sample_filter_v2_out_2 : out std_logic; - sample_filter_v2_out_3 : out std_logic; - sample_filter_v2_out_4 : out std_logic; - sample_filter_v2_out_5 : out std_logic; - sample_filter_v2_out_6 : out std_logic; - sample_filter_v2_out_7 : out std_logic; - sample_filter_v2_out_8 : out std_logic; - sample_filter_v2_out_9 : out std_logic; - sample_filter_v2_out_10 : out std_logic; - sample_filter_v2_out_11 : out std_logic; - sample_filter_v2_out_12 : out std_logic; - sample_filter_v2_out_13 : out std_logic; - sample_filter_v2_out_14 : out std_logic; - sample_filter_v2_out_15 : out std_logic; - sample_filter_v2_out_18 : out std_logic; - sample_filter_v2_out_19 : out std_logic; - sample_filter_v2_out_20 : out std_logic; - sample_filter_v2_out_21 : out std_logic; - sample_filter_v2_out_22 : out std_logic; - sample_filter_v2_out_23 : out std_logic; - sample_filter_v2_out_24 : out std_logic; - sample_filter_v2_out_25 : out std_logic; - sample_filter_v2_out_26 : out std_logic; - sample_filter_v2_out_27 : out std_logic; - sample_filter_v2_out_28 : out std_logic; - sample_filter_v2_out_29 : out std_logic; - sample_filter_v2_out_30 : out std_logic; - sample_filter_v2_out_31 : out std_logic; - sample_filter_v2_out_32 : out std_logic; - sample_filter_v2_out_33 : out std_logic; - sample_filter_v2_out_36 : out std_logic; - sample_filter_v2_out_37 : out std_logic; - sample_filter_v2_out_38 : out std_logic; - sample_filter_v2_out_39 : out std_logic; - sample_filter_v2_out_40 : out std_logic; - sample_filter_v2_out_41 : out std_logic; - sample_filter_v2_out_42 : out std_logic; - sample_filter_v2_out_43 : out std_logic; - sample_filter_v2_out_44 : out std_logic; - sample_filter_v2_out_45 : out std_logic; - sample_filter_v2_out_46 : out std_logic; - sample_filter_v2_out_47 : out std_logic; - sample_filter_v2_out_48 : out std_logic; - sample_filter_v2_out_49 : out std_logic; - sample_filter_v2_out_50 : out std_logic; - sample_filter_v2_out_51 : out std_logic; - sample_filter_v2_out_54 : out std_logic; - sample_filter_v2_out_55 : out std_logic; - sample_filter_v2_out_56 : out std_logic; - sample_filter_v2_out_57 : out std_logic; - sample_filter_v2_out_58 : out std_logic; - sample_filter_v2_out_59 : out std_logic; - sample_filter_v2_out_60 : out std_logic; - sample_filter_v2_out_61 : out std_logic; - sample_filter_v2_out_62 : out std_logic; - sample_filter_v2_out_63 : out std_logic; - sample_filter_v2_out_64 : out std_logic; - sample_filter_v2_out_65 : out std_logic; - sample_filter_v2_out_66 : out std_logic; - sample_filter_v2_out_67 : out std_logic; - sample_filter_v2_out_68 : out std_logic; - sample_filter_v2_out_69 : out std_logic; - sample_filter_v2_out_90 : out std_logic; - sample_filter_v2_out_91 : out std_logic; - sample_filter_v2_out_92 : out std_logic; - sample_filter_v2_out_93 : out std_logic; - sample_filter_v2_out_94 : out std_logic; - sample_filter_v2_out_95 : out std_logic; - sample_filter_v2_out_96 : out std_logic; - sample_filter_v2_out_97 : out std_logic; - sample_filter_v2_out_98 : out std_logic; - sample_filter_v2_out_99 : out std_logic; - sample_filter_v2_out_100 : out std_logic; - sample_filter_v2_out_101 : out std_logic; - sample_filter_v2_out_102 : out std_logic; - sample_filter_v2_out_103 : out std_logic; - sample_filter_v2_out_104 : out std_logic; - sample_filter_v2_out_105 : out std_logic; - sample_filter_v2_out_108 : out std_logic; - sample_filter_v2_out_126 : out std_logic; - sample_filter_v2_out_109 : out std_logic; - sample_filter_v2_out_127 : out std_logic; - sample_filter_v2_out_110 : out std_logic; - sample_filter_v2_out_128 : out std_logic; - sample_filter_v2_out_111 : out std_logic; - sample_filter_v2_out_129 : out std_logic; - sample_filter_v2_out_112 : out std_logic; - sample_filter_v2_out_130 : out std_logic; - sample_filter_v2_out_113 : out std_logic; - sample_filter_v2_out_131 : out std_logic; - sample_filter_v2_out_114 : out std_logic; - sample_filter_v2_out_132 : out std_logic; - sample_filter_v2_out_115 : out std_logic; - sample_filter_v2_out_133 : out std_logic; - sample_filter_v2_out_116 : out std_logic; - sample_filter_v2_out_134 : out std_logic; - sample_filter_v2_out_117 : out std_logic; - sample_filter_v2_out_135 : out std_logic; - sample_filter_v2_out_118 : out std_logic; - sample_filter_v2_out_136 : out std_logic; - sample_filter_v2_out_119 : out std_logic; - sample_filter_v2_out_137 : out std_logic; - sample_filter_v2_out_120 : out std_logic; - sample_filter_v2_out_138 : out std_logic; - sample_filter_v2_out_121 : out std_logic; - sample_filter_v2_out_139 : out std_logic; - sample_filter_v2_out_122 : out std_logic; - sample_filter_v2_out_140 : out std_logic; - sample_filter_v2_out_123 : out std_logic; - sample_filter_v2_out_141 : out std_logic; - sample_6 : in std_logic_vector(15 downto 0); - sample_5 : in std_logic_vector(15 downto 0); - sample_2 : in std_logic_vector(15 downto 0); - sample_0 : in std_logic_vector(15 downto 0); - sample_1 : in std_logic_vector(15 downto 0); - sample_3 : in std_logic_vector(15 downto 0); - sample_4 : in std_logic_vector(15 downto 0); - sample_7 : in std_logic_vector(15 downto 0); - IIR_CEL_CTRLR_v2_VCC : in std_logic; - IIR_CEL_CTRLR_v2_GND : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_filter_v2_out_val : out std_logic; - sample_val_delay : in std_logic - ); - -end IIR_CEL_CTRLR_v2; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2_DATAFLOW - port( alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - S : out std_logic_vector(8 to 8); - S_i_0 : out std_logic_vector(33 to 33); - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - waddr_previous : in std_logic_vector(1 downto 0) := (others => 'U'); - sample_0 : in std_logic_vector(14 downto 0) := (others => 'U'); - sample_in_buf : in std_logic_vector(143 downto 129) := (others => 'U'); - ram_sel_Wdata : in std_logic_vector(1 downto 0) := (others => 'U'); - sample_out_s_0 : out std_logic; - sample_out_s_1 : out std_logic; - sample_out_s_3 : out std_logic; - sample_out_s_2 : out std_logic; - sample_out_s_10 : out std_logic; - sample_out_s_15 : out std_logic; - sample_out_s_14 : out std_logic; - sample_out_s_13 : out std_logic; - sample_out_s_12 : out std_logic; - sample_out_s_11 : out std_logic; - sample_out_s_9 : out std_logic; - sample_out_s_8 : out std_logic; - sample_out_s_7 : out std_logic; - sample_out_s_6 : out std_logic; - sample_out_s_5 : out std_logic; - sample_out_s_4 : out std_logic; - sample_in_s_1 : in std_logic_vector(17 to 17) := (others => 'U'); - in_sel_src : in std_logic_vector(1 downto 0) := (others => 'U'); - raddr_rst : in std_logic := 'U'; - raddr_add1 : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_DATAFLOW_GND : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_DATAFLOW_VCC : in std_logic := 'U'; - ram_write_i : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_val_delay : in std_logic := 'U'; - alu_sel_input : in std_logic := 'U' - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2_CONTROL - port( alu_ctrl : out std_logic_vector(2 downto 0); - ram_sel_Wdata : out std_logic_vector(1 downto 0); - waddr_previous : out std_logic_vector(1 downto 0); - in_sel_src : out std_logic_vector(1 downto 0); - S_i_0 : in std_logic_vector(33 to 33) := (others => 'U'); - S : in std_logic_vector(8 to 8) := (others => 'U'); - alu_sel_coeff : out std_logic_vector(4 downto 0); - alu_sel_coeff_0_2 : out std_logic; - alu_sel_coeff_0_0 : out std_logic; - sample_out_rot_s : out std_logic; - sample_out_val_s : out std_logic; - raddr_rst : out std_logic; - alu_sel_input : out std_logic; - raddr_add1 : out std_logic; - sample_val_delay : in std_logic := 'U'; - ram_write : out std_logic; - ram_write_i : out std_logic; - un1_sample_in_rotate : out std_logic; - sample_out_rot_s_0 : out std_logic; - sample_out_rot_s_1 : out std_logic; - sample_out_rot_s_2 : out std_logic; - sample_out_rot_s_3 : out std_logic; - sample_out_rot_s_4 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal \sample_in_buf_581[9]\, \sample_in_buf[135]\, - \sample_in_buf_349[59]\, \sample_in_buf[41]\, - \sample_in_buf_669[64]\, \sample_in_buf[46]\, - \sample_in_buf_293[76]\, \sample_in_buf[58]\, - \sample_in_buf_501[115]\, \sample_in_buf[97]\, - \sample_in_buf_821[120]\, \sample_in_buf[102]\, - \sample_in_buf_637[135]\, \sample_in_buf[117]\, - \sample_in_buf_965[15]\, \sample_in_buf[141]\, - \sample_in_buf_29[54]\, \sample_in_buf[36]\, - \sample_in_buf_285[58]\, \sample_in_buf[40]\, - \sample_in_buf_813[102]\, \sample_in_buf[84]\, - \sample_in_buf_437[114]\, \sample_in_buf[96]\, - \sample_in_buf_1021[141]\, \sample_in_buf[123]\, - \sample_in_buf_645[10]\, \sample_in_buf[136]\, - \sample_in_buf_853[49]\, \sample_in_buf[31]\, - \sample_in_buf_1045[52]\, \sample_in_buf[34]\, - \sample_in_buf_805[84]\, \sample_in_buf[66]\, - \sample_in_buf_493[97]\, \sample_in_buf[79]\, - \sample_in_buf_701[136]\, \sample_in_buf[118]\, - \sample_in_buf_389[6]\, \sample_in_buf[132]\, - \sample_in_buf_341[41]\, \sample_in_buf[23]\, - \sample_in_buf_605[63]\, \sample_in_buf[45]\, - \sample_in_buf_1117[71]\, \sample_in_buf[53]\, - \sample_in_buf_757[119]\, \sample_in_buf[101]\, - \sample_in_buf_445[132]\, \sample_in_buf[114]\, - \sample_in_buf_277[40]\, \sample_in_buf[22]\, - \sample_in_buf_725[47]\, \sample_in_buf[29]\, - \sample_in_buf_421[78]\, \sample_in_buf[60]\, - \sample_in_buf_373[113]\, \sample_in_buf[95]\, - \sample_in_buf_1013[123]\, \sample_in_buf[105]\, - \sample_in_buf_261[4]\, \sample_in_buf[130]\, - \sample_in_buf_21[36]\, \sample_in_buf[18]\, - \sample_in_buf_221[57]\, \sample_in_buf[39]\, - \sample_in_buf_749[101]\, \sample_in_buf[83]\, - \sample_in_buf_1133[107]\, \sample_in_buf[89]\, - \sample_in_buf_317[130]\, \sample_in_buf[112]\, - \sample_in_buf_517[8]\, \sample_in_buf[134]\, - \sample_in_buf_773[12]\, \sample_in_buf[138]\, - \sample_in_buf_1101[35]\, \sample_in_buf[17]\, - \sample_in_buf_213[39]\, \sample_in_buf[21]\, - \sample_in_buf_477[61]\, \sample_in_buf[43]\, - \sample_in_buf_1069[106]\, \sample_in_buf[88]\, - \sample_in_buf_573[134]\, \sample_in_buf[116]\, - \sample_in_buf_829[138]\, \sample_in_buf[120]\, - \sample_in_buf_325[5]\, \sample_in_buf[131]\, - \sample_in_buf_845[31]\, \sample_in_buf[13]\, - \sample_in_buf_909[32]\, \sample_in_buf[14]\, - \sample_in_buf_981[51]\, \sample_in_buf[33]\, - \sample_in_buf_741[83]\, \sample_in_buf[65]\, - \sample_in_buf_933[86]\, \sample_in_buf[68]\, - \sample_in_buf_1125[89]\, \sample_in_buf[71]\, - \sample_in_buf_237[93]\, \sample_in_buf[75]\, - \sample_in_buf_245[111]\, \sample_in_buf[93]\, - \sample_in_buf_381[131]\, \sample_in_buf[113]\, - \sample_in_buf_781[30]\, \sample_in_buf[12]\, - \sample_in_buf_789[48]\, \sample_in_buf[30]\, - \sample_in_buf_917[50]\, \sample_in_buf[32]\, - \sample_in_buf_549[80]\, \sample_in_buf[62]\, - \sample_in_buf_613[81]\, \sample_in_buf[63]\, - \sample_in_buf_997[87]\, \sample_in_buf[69]\, - \sample_in_buf_365[95]\, \sample_in_buf[77]\, - \sample_in_buf_949[122]\, \sample_in_buf[104]\, - \sample_in_buf_837[13]\, \sample_in_buf[139]\, - \sample_in_buf_653[28]\, \sample_in_buf[10]\, - \sample_in_buf_469[43]\, \sample_in_buf[25]\, - \sample_in_buf_37[72]\, \sample_in_buf[54]\, - \sample_in_buf_877[103]\, \sample_in_buf[85]\, - \sample_in_buf_893[139]\, \sample_in_buf[121]\, - \sample_in_buf_589[27]\, \sample_in_buf[9]\, - \sample_in_buf_973[33]\, \sample_in_buf[15]\, - \sample_in_buf_533[44]\, \sample_in_buf[26]\, - \sample_in_buf_861[67]\, \sample_in_buf[49]\, - \sample_in_buf_989[69]\, \sample_in_buf[51]\, - \sample_in_buf_869[85]\, \sample_in_buf[67]\, - \sample_in_buf_45[90]\, \sample_in_buf[72]\, - \sample_in_buf_301[94]\, \sample_in_buf[76]\, - \sample_in_buf_941[104]\, \sample_in_buf[86]\, - \sample_in_buf_565[116]\, \sample_in_buf[98]\, - \sample_in_buf_197[3]\, \sample_in_buf[129]\, - \sample_in_buf_525[26]\, \sample_in_buf[8]\, - \sample_in_buf_405[42]\, \sample_in_buf[24]\, - \sample_in_buf_797[66]\, \sample_in_buf[48]\, - \sample_in_buf_677[82]\, \sample_in_buf[64]\, - \sample_in_buf_1141[125]\, \sample_in_buf[107]\, - \sample_in_buf_253[129]\, \sample_in_buf[111]\, - \sample_in_buf_901[14]\, \sample_in_buf[140]\, - \sample_in_buf_1029[16]\, \sample_in_buf[142]\, - \sample_in_buf_461[25]\, \sample_in_buf[7]\, - \sample_in_buf_1037[34]\, \sample_in_buf[16]\, - \sample_in_buf_429[96]\, \sample_in_buf[78]\, - \sample_in_buf_957[140]\, \sample_in_buf[122]\, - \sample_in_buf_1085[142]\, \sample_in_buf[124]\, - \sample_in_buf_709[11]\, \sample_in_buf[137]\, - \sample_in_buf_397[24]\, \sample_in_buf[6]\, - \sample_in_buf_733[65]\, \sample_in_buf[47]\, - \sample_in_buf_485[79]\, \sample_in_buf[61]\, - \sample_in_buf_1077[124]\, \sample_in_buf[106]\, - \sample_in_buf_765[137]\, \sample_in_buf[119]\, - \sample_in_buf_269[22]\, \sample_in_buf[4]\, - \sample_in_buf_333[23]\, \sample_in_buf[5]\, - \sample_in_buf_597[45]\, \sample_in_buf[27]\, - \sample_in_buf_541[62]\, \sample_in_buf[44]\, - \sample_in_buf_925[68]\, \sample_in_buf[50]\, - \sample_in_buf_1053[70]\, \sample_in_buf[52]\, - \sample_in_buf_1061[88]\, \sample_in_buf[70]\, - \sample_in_buf_557[98]\, \sample_in_buf[80]\, - \sample_in_buf_621[99]\, \sample_in_buf[81]\, - \sample_in_buf_309[112]\, \sample_in_buf[94]\, - \sample_in_buf_629[117]\, \sample_in_buf[99]\, - \sample_in_buf_693[118]\, \sample_in_buf[100]\, - \sample_in_buf_5[0]\, \sample_in_buf[128]\, - \sample_in_buf_205[21]\, \sample_in_buf[3]\, - \sample_in_buf_413[60]\, \sample_in_buf[42]\, - \sample_in_buf_1005[105]\, \sample_in_buf[87]\, - \sample_in_buf_61[126]\, \sample_in_buf[108]\, - \sample_in_s_1[17]\, \sample_in_buf_453[7]\, - \sample_in_buf[133]\, \sample_in_buf_13[18]\, - \sample_in_buf[0]\, \sample_in_buf_717[29]\, - \sample_in_buf[11]\, \sample_in_buf_661[46]\, - \sample_in_buf[28]\, \sample_in_buf_1109[53]\, - \sample_in_buf[35]\, \sample_in_buf_229[75]\, - \sample_in_buf[57]\, \sample_in_buf_357[77]\, - \sample_in_buf[59]\, \sample_in_buf_685[100]\, - \sample_in_buf[82]\, \sample_in_buf_53[108]\, - \sample_in_buf[90]\, \sample_in_buf_885[121]\, - \sample_in_buf[103]\, \sample_in_buf_509[133]\, - \sample_in_buf[115]\, \sample_in_buf_1149[143]\, - \sample_in_buf[125]\, \sample_in_buf_1093[17]\, - \sample_in_buf[143]\, \sample_out_val_s2\, - sample_out_val_s, sample_out_rot_s_0, sample_out_rot_s_1, - \sample_filter_v2_out[125]\, \sample_filter_v2_out[124]\, - \sample_filter_v2_out[123]\, \sample_filter_v2_out[122]\, - \sample_filter_v2_out[121]\, \sample_filter_v2_out[120]\, - \sample_filter_v2_out[119]\, sample_out_rot_s_2, - \sample_filter_v2_out[118]\, \sample_filter_v2_out[117]\, - \sample_filter_v2_out[116]\, \sample_filter_v2_out[115]\, - \sample_filter_v2_out[114]\, \sample_filter_v2_out[113]\, - \sample_filter_v2_out[112]\, \sample_filter_v2_out[111]\, - \sample_filter_v2_out[110]\, \sample_filter_v2_out[107]\, - \sample_filter_v2_out[89]\, \sample_filter_v2_out[106]\, - \sample_filter_v2_out[88]\, \sample_filter_v2_out[105]\, - \sample_filter_v2_out[87]\, \sample_filter_v2_out[104]\, - \sample_filter_v2_out[86]\, \sample_filter_v2_out[103]\, - \sample_filter_v2_out[85]\, \sample_filter_v2_out[102]\, - \sample_filter_v2_out[84]\, \sample_filter_v2_out[101]\, - \sample_filter_v2_out[83]\, \sample_filter_v2_out[100]\, - \sample_filter_v2_out[82]\, \sample_filter_v2_out[99]\, - \sample_filter_v2_out[81]\, \sample_filter_v2_out[98]\, - \sample_filter_v2_out[80]\, \sample_filter_v2_out[97]\, - \sample_filter_v2_out[79]\, \sample_filter_v2_out[96]\, - \sample_filter_v2_out[78]\, \sample_filter_v2_out[95]\, - \sample_filter_v2_out[77]\, \sample_filter_v2_out[94]\, - \sample_filter_v2_out[76]\, \sample_filter_v2_out[93]\, - \sample_filter_v2_out[75]\, \sample_filter_v2_out[92]\, - \sample_filter_v2_out[74]\, sample_out_rot_s_3, - \sample_filter_v2_out[71]\, \sample_filter_v2_out[70]\, - \sample_filter_v2_out[69]\, sample_out_rot_s_4, - \sample_filter_v2_out[68]\, \sample_filter_v2_out[67]\, - \sample_filter_v2_out[66]\, \sample_filter_v2_out[65]\, - \sample_filter_v2_out[64]\, \sample_filter_v2_out[63]\, - \sample_filter_v2_out[62]\, \sample_filter_v2_out[61]\, - \sample_filter_v2_out[60]\, \sample_filter_v2_out[59]\, - \sample_filter_v2_out[58]\, \sample_filter_v2_out[57]\, - \sample_filter_v2_out[56]\, \sample_filter_v2_out[53]\, - \sample_filter_v2_out[52]\, \sample_filter_v2_out[51]\, - \sample_filter_v2_out[50]\, \sample_filter_v2_out[49]\, - \sample_filter_v2_out[48]\, \sample_filter_v2_out[47]\, - \sample_filter_v2_out[46]\, \sample_filter_v2_out[45]\, - sample_out_rot_s, \sample_filter_v2_out[44]\, - \sample_filter_v2_out[43]\, \sample_filter_v2_out[42]\, - \sample_filter_v2_out[41]\, \sample_filter_v2_out[40]\, - \sample_filter_v2_out[39]\, \sample_filter_v2_out[38]\, - un1_sample_in_rotate, \sample_filter_v2_out[35]\, - \sample_filter_v2_out[34]\, \sample_filter_v2_out[33]\, - \sample_filter_v2_out[32]\, \sample_filter_v2_out[31]\, - \sample_filter_v2_out[30]\, \sample_filter_v2_out[29]\, - \sample_filter_v2_out[28]\, \sample_filter_v2_out[27]\, - \sample_filter_v2_out[26]\, \sample_filter_v2_out[25]\, - \sample_filter_v2_out[24]\, \sample_filter_v2_out[23]\, - \sample_filter_v2_out[22]\, \sample_filter_v2_out[21]\, - \sample_filter_v2_out[20]\, \sample_filter_v2_out[17]\, - \sample_out_s[0]\, \sample_filter_v2_out[16]\, - \sample_out_s[1]\, \sample_filter_v2_out[15]\, - \sample_out_s[2]\, \sample_filter_v2_out[14]\, - \sample_out_s[3]\, \sample_filter_v2_out[13]\, - \sample_out_s[4]\, \sample_filter_v2_out[12]\, - \sample_out_s[5]\, \sample_filter_v2_out[11]\, - \sample_out_s[6]\, \sample_filter_v2_out[10]\, - \sample_out_s[7]\, \sample_filter_v2_out[9]\, - \sample_out_s[8]\, \sample_filter_v2_out[8]\, - \sample_out_s[9]\, \sample_filter_v2_out[7]\, - \sample_out_s[10]\, \sample_filter_v2_out[6]\, - \sample_out_s[11]\, \sample_filter_v2_out[5]\, - \sample_out_s[12]\, \sample_filter_v2_out[4]\, - \sample_out_s[13]\, \sample_filter_v2_out[3]\, - \sample_out_s[14]\, \sample_filter_v2_out[2]\, - \sample_out_s[15]\, \alu_ctrl[0]\, \alu_ctrl[1]\, - \alu_ctrl[2]\, \S[8]\, \S_i_0[33]\, \alu_sel_coeff[0]\, - \alu_sel_coeff[1]\, \alu_sel_coeff[2]\, - \alu_sel_coeff[3]\, \alu_sel_coeff[4]\, - \alu_sel_coeff_0[2]\, \alu_sel_coeff_0[0]\, - \waddr_previous[0]\, \waddr_previous[1]\, - \ram_sel_Wdata[0]\, \ram_sel_Wdata[1]\, \in_sel_src[0]\, - \in_sel_src[1]\, raddr_rst, raddr_add1, ram_write, - ram_write_i, alu_sel_input, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : IIR_CEL_CTRLR_v2_DATAFLOW - Use entity work.IIR_CEL_CTRLR_v2_DATAFLOW(DEF_ARCH); - for all : IIR_CEL_CTRLR_v2_CONTROL - Use entity work.IIR_CEL_CTRLR_v2_CONTROL(DEF_ARCH); -begin - - sample_filter_v2_out_0 <= \sample_filter_v2_out[2]\; - sample_filter_v2_out_1 <= \sample_filter_v2_out[3]\; - sample_filter_v2_out_2 <= \sample_filter_v2_out[4]\; - sample_filter_v2_out_3 <= \sample_filter_v2_out[5]\; - sample_filter_v2_out_4 <= \sample_filter_v2_out[6]\; - sample_filter_v2_out_5 <= \sample_filter_v2_out[7]\; - sample_filter_v2_out_6 <= \sample_filter_v2_out[8]\; - sample_filter_v2_out_7 <= \sample_filter_v2_out[9]\; - sample_filter_v2_out_8 <= \sample_filter_v2_out[10]\; - sample_filter_v2_out_9 <= \sample_filter_v2_out[11]\; - sample_filter_v2_out_10 <= \sample_filter_v2_out[12]\; - sample_filter_v2_out_11 <= \sample_filter_v2_out[13]\; - sample_filter_v2_out_12 <= \sample_filter_v2_out[14]\; - sample_filter_v2_out_13 <= \sample_filter_v2_out[15]\; - sample_filter_v2_out_14 <= \sample_filter_v2_out[16]\; - sample_filter_v2_out_15 <= \sample_filter_v2_out[17]\; - sample_filter_v2_out_18 <= \sample_filter_v2_out[20]\; - sample_filter_v2_out_19 <= \sample_filter_v2_out[21]\; - sample_filter_v2_out_20 <= \sample_filter_v2_out[22]\; - sample_filter_v2_out_21 <= \sample_filter_v2_out[23]\; - sample_filter_v2_out_22 <= \sample_filter_v2_out[24]\; - sample_filter_v2_out_23 <= \sample_filter_v2_out[25]\; - sample_filter_v2_out_24 <= \sample_filter_v2_out[26]\; - sample_filter_v2_out_25 <= \sample_filter_v2_out[27]\; - sample_filter_v2_out_26 <= \sample_filter_v2_out[28]\; - sample_filter_v2_out_27 <= \sample_filter_v2_out[29]\; - sample_filter_v2_out_28 <= \sample_filter_v2_out[30]\; - sample_filter_v2_out_29 <= \sample_filter_v2_out[31]\; - sample_filter_v2_out_30 <= \sample_filter_v2_out[32]\; - sample_filter_v2_out_31 <= \sample_filter_v2_out[33]\; - sample_filter_v2_out_32 <= \sample_filter_v2_out[34]\; - sample_filter_v2_out_33 <= \sample_filter_v2_out[35]\; - sample_filter_v2_out_36 <= \sample_filter_v2_out[38]\; - sample_filter_v2_out_37 <= \sample_filter_v2_out[39]\; - sample_filter_v2_out_38 <= \sample_filter_v2_out[40]\; - sample_filter_v2_out_39 <= \sample_filter_v2_out[41]\; - sample_filter_v2_out_40 <= \sample_filter_v2_out[42]\; - sample_filter_v2_out_41 <= \sample_filter_v2_out[43]\; - sample_filter_v2_out_42 <= \sample_filter_v2_out[44]\; - sample_filter_v2_out_43 <= \sample_filter_v2_out[45]\; - sample_filter_v2_out_44 <= \sample_filter_v2_out[46]\; - sample_filter_v2_out_45 <= \sample_filter_v2_out[47]\; - sample_filter_v2_out_46 <= \sample_filter_v2_out[48]\; - sample_filter_v2_out_47 <= \sample_filter_v2_out[49]\; - sample_filter_v2_out_48 <= \sample_filter_v2_out[50]\; - sample_filter_v2_out_49 <= \sample_filter_v2_out[51]\; - sample_filter_v2_out_50 <= \sample_filter_v2_out[52]\; - sample_filter_v2_out_51 <= \sample_filter_v2_out[53]\; - sample_filter_v2_out_54 <= \sample_filter_v2_out[56]\; - sample_filter_v2_out_55 <= \sample_filter_v2_out[57]\; - sample_filter_v2_out_56 <= \sample_filter_v2_out[58]\; - sample_filter_v2_out_57 <= \sample_filter_v2_out[59]\; - sample_filter_v2_out_58 <= \sample_filter_v2_out[60]\; - sample_filter_v2_out_59 <= \sample_filter_v2_out[61]\; - sample_filter_v2_out_60 <= \sample_filter_v2_out[62]\; - sample_filter_v2_out_61 <= \sample_filter_v2_out[63]\; - sample_filter_v2_out_62 <= \sample_filter_v2_out[64]\; - sample_filter_v2_out_63 <= \sample_filter_v2_out[65]\; - sample_filter_v2_out_64 <= \sample_filter_v2_out[66]\; - sample_filter_v2_out_65 <= \sample_filter_v2_out[67]\; - sample_filter_v2_out_66 <= \sample_filter_v2_out[68]\; - sample_filter_v2_out_67 <= \sample_filter_v2_out[69]\; - sample_filter_v2_out_68 <= \sample_filter_v2_out[70]\; - sample_filter_v2_out_69 <= \sample_filter_v2_out[71]\; - sample_filter_v2_out_90 <= \sample_filter_v2_out[92]\; - sample_filter_v2_out_91 <= \sample_filter_v2_out[93]\; - sample_filter_v2_out_92 <= \sample_filter_v2_out[94]\; - sample_filter_v2_out_93 <= \sample_filter_v2_out[95]\; - sample_filter_v2_out_94 <= \sample_filter_v2_out[96]\; - sample_filter_v2_out_95 <= \sample_filter_v2_out[97]\; - sample_filter_v2_out_96 <= \sample_filter_v2_out[98]\; - sample_filter_v2_out_97 <= \sample_filter_v2_out[99]\; - sample_filter_v2_out_98 <= \sample_filter_v2_out[100]\; - sample_filter_v2_out_99 <= \sample_filter_v2_out[101]\; - sample_filter_v2_out_100 <= \sample_filter_v2_out[102]\; - sample_filter_v2_out_101 <= \sample_filter_v2_out[103]\; - sample_filter_v2_out_102 <= \sample_filter_v2_out[104]\; - sample_filter_v2_out_103 <= \sample_filter_v2_out[105]\; - sample_filter_v2_out_104 <= \sample_filter_v2_out[106]\; - sample_filter_v2_out_105 <= \sample_filter_v2_out[107]\; - sample_filter_v2_out_108 <= \sample_filter_v2_out[110]\; - sample_filter_v2_out_109 <= \sample_filter_v2_out[111]\; - sample_filter_v2_out_110 <= \sample_filter_v2_out[112]\; - sample_filter_v2_out_111 <= \sample_filter_v2_out[113]\; - sample_filter_v2_out_112 <= \sample_filter_v2_out[114]\; - sample_filter_v2_out_113 <= \sample_filter_v2_out[115]\; - sample_filter_v2_out_114 <= \sample_filter_v2_out[116]\; - sample_filter_v2_out_115 <= \sample_filter_v2_out[117]\; - sample_filter_v2_out_116 <= \sample_filter_v2_out[118]\; - sample_filter_v2_out_117 <= \sample_filter_v2_out[119]\; - sample_filter_v2_out_118 <= \sample_filter_v2_out[120]\; - sample_filter_v2_out_119 <= \sample_filter_v2_out[121]\; - sample_filter_v2_out_120 <= \sample_filter_v2_out[122]\; - sample_filter_v2_out_121 <= \sample_filter_v2_out[123]\; - sample_filter_v2_out_122 <= \sample_filter_v2_out[124]\; - sample_filter_v2_out_123 <= \sample_filter_v2_out[125]\; - - \loop_all_sample.2.loop_all_chanel.6.sample_in_buf[33]\ : - DFN1E1C0 - port map(D => \sample_in_buf_973[33]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[33]\); - - \loop_all_sample.13.loop_all_chanel.7.sample_in_buf[4]\ : - DFN1E1C0 - port map(D => \sample_in_buf_261[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[4]\); - - \loop_all_sample.9.loop_all_chanel.4.sample_in_buf_RNO[62]\ : - MX2 - port map(A => \sample_in_buf[44]\, B => sample_4(9), S => - sample_val_delay, Y => \sample_in_buf_541[62]\); - - \loop_all_sample.10.loop_all_chanel.2.sample_in_buf_RNO[97]\ : - MX2 - port map(A => \sample_in_buf[79]\, B => sample_2(10), S => - sample_val_delay, Y => \sample_in_buf_493[97]\); - - \chanel_more.all_chanel.2.all_bit.3.sample_out_s2[122]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[104]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[122]\); - - \loop_all_sample.5.loop_all_chanel.4.sample_in_buf_RNO[66]\ : - MX2 - port map(A => \sample_in_buf[48]\, B => sample_4(5), S => - sample_val_delay, Y => \sample_in_buf_797[66]\); - - \loop_all_sample.1.loop_all_chanel.6.sample_in_buf[34]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1037[34]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[34]\); - - \chanel_more.all_chanel.3.all_bit.1.sample_out_s2[106]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[88]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[106]\); - - \loop_all_sample.6.loop_all_chanel.1.sample_in_buf_RNO[119]\ : - MX2 - port map(A => \sample_in_buf[101]\, B => sample_1(6), S => - sample_val_delay, Y => \sample_in_buf_757[119]\); - - \loop_all_sample.12.loop_all_chanel.4.sample_in_buf_RNO[59]\ : - MX2 - port map(A => \sample_in_buf[41]\, B => sample_4(12), S => - sample_val_delay, Y => \sample_in_buf_349[59]\); - - \chanel_more.all_chanel.1.all_bit.6.sample_out_s2[137]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[119]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_135); - - \chanel_more.all_chanel.7.all_bit.3.sample_out_s2[32]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[14]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[32]\); - - \chanel_more.all_chanel.5.all_bit.10.sample_out_s2[61]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[43]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[61]\); - - \loop_all_sample.6.loop_all_chanel.0.sample_in_buf_RNO[137]\ : - MX2 - port map(A => \sample_in_buf[119]\, B => sample_0(6), S => - sample_val_delay, Y => \sample_in_buf_765[137]\); - - \chanel_more.all_chanel.6.all_bit.0.sample_out_s2[53]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[35]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[53]\); - - \chanel_more.all_chanel.4.all_bit.13.sample_out_s2[76]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[58]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[76]\); - - \loop_all_sample.9.loop_all_chanel.0.sample_in_buf_RNO[134]\ : - MX2 - port map(A => \sample_in_buf[116]\, B => sample_0(9), S => - sample_val_delay, Y => \sample_in_buf_573[134]\); - - \loop_all_sample.8.loop_all_chanel.2.sample_in_buf[99]\ : - DFN1E1C0 - port map(D => \sample_in_buf_621[99]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[99]\); - - \chanel_more.all_chanel.3.all_bit.11.sample_out_s2[96]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[78]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[96]\); - - \chanel_more.all_chanel.6.all_bit.2.sample_out_s2[51]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[33]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[51]\); - - \loop_all_sample.12.loop_all_chanel.5.sample_in_buf_RNO[41]\ : - MX2 - port map(A => \sample_in_buf[23]\, B => sample_5(12), S => - sample_val_delay, Y => \sample_in_buf_341[41]\); - - \loop_all_sample.1.loop_all_chanel.2.sample_in_buf[106]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1069[106]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[106]\); - - \loop_all_sample.17.loop_all_chanel.7.sample_in_buf_RNO[0]\ : - MX2 - port map(A => \sample_in_buf[128]\, B => sample_7(15), S - => sample_val_delay, Y => \sample_in_buf_5[0]\); - - \loop_all_sample.13.loop_all_chanel.5.sample_in_buf[40]\ : - DFN1E1C0 - port map(D => \sample_in_buf_277[40]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[40]\); - - \loop_all_sample.13.loop_all_chanel.0.sample_in_buf_RNO[130]\ : - MX2 - port map(A => \sample_in_buf[112]\, B => sample_0(13), S - => sample_val_delay, Y => \sample_in_buf_317[130]\); - - \loop_all_sample.3.loop_all_chanel.4.sample_in_buf_RNO[68]\ : - MX2 - port map(A => \sample_in_buf[50]\, B => sample_4(3), S => - sample_val_delay, Y => \sample_in_buf_925[68]\); - - \chanel_more.all_chanel.1.all_bit.3.sample_out_s2[140]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[122]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_138); - - \loop_all_sample.13.loop_all_chanel.2.sample_in_buf_RNO[94]\ : - MX2 - port map(A => \sample_in_buf[76]\, B => sample_2(13), S => - sample_val_delay, Y => \sample_in_buf_301[94]\); - - \loop_all_sample.11.loop_all_chanel.3.sample_in_buf_RNO[78]\ : - MX2 - port map(A => \sample_in_buf[60]\, B => sample_3(11), S => - sample_val_delay, Y => \sample_in_buf_421[78]\); - - \chanel_more.all_chanel.4.all_bit.1.sample_out_s2[88]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[70]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[88]\); - - \chanel_more.all_chanel.3.all_bit.4.sample_out_s2[103]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[85]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[103]\); - - \loop_all_sample.7.loop_all_chanel.4.sample_in_buf_RNO[64]\ : - MX2 - port map(A => \sample_in_buf[46]\, B => sample_4(7), S => - sample_val_delay, Y => \sample_in_buf_669[64]\); - - \loop_all_sample.5.loop_all_chanel.3.sample_in_buf[84]\ : - DFN1E1C0 - port map(D => \sample_in_buf_805[84]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[84]\); - - \chanel_more.all_chanel.6.all_bit.15.sample_out_s2[38]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[20]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[38]\); - - \loop_all_sample.12.loop_all_chanel.5.sample_in_buf[41]\ : - DFN1E1C0 - port map(D => \sample_in_buf_341[41]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[41]\); - - \chanel_more.all_chanel.5.all_bit.7.sample_out_s2[64]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[46]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[64]\); - - \chanel_more.all_chanel.5.all_bit.6.sample_out_s2[65]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[47]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[65]\); - - \chanel_more.all_chanel.7.all_bit.2.sample_out_s2[33]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[15]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[33]\); - - \loop_all_sample.9.loop_all_chanel.3.sample_in_buf_RNO[80]\ : - MX2 - port map(A => \sample_in_buf[62]\, B => sample_3(9), S => - sample_val_delay, Y => \sample_in_buf_549[80]\); - - \loop_all_sample.2.loop_all_chanel.4.sample_in_buf_RNO[69]\ : - MX2 - port map(A => \sample_in_buf[51]\, B => sample_4(2), S => - sample_val_delay, Y => \sample_in_buf_989[69]\); - - \loop_all_sample.14.loop_all_chanel.6.sample_in_buf[21]\ : - DFN1E1C0 - port map(D => \sample_in_buf_205[21]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[21]\); - - \loop_all_sample.9.loop_all_chanel.5.sample_in_buf[44]\ : - DFN1E1C0 - port map(D => \sample_in_buf_533[44]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[44]\); - - \loop_all_sample.11.loop_all_chanel.5.sample_in_buf[42]\ : - DFN1E1C0 - port map(D => \sample_in_buf_405[42]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[42]\); - - \loop_all_sample.9.loop_all_chanel.2.sample_in_buf_RNO[98]\ : - MX2 - port map(A => \sample_in_buf[80]\, B => sample_2(9), S => - sample_val_delay, Y => \sample_in_buf_557[98]\); - - \loop_all_sample.10.loop_all_chanel.4.sample_in_buf_RNO[61]\ : - MX2 - port map(A => \sample_in_buf[43]\, B => sample_4(10), S => - sample_val_delay, Y => \sample_in_buf_477[61]\); - - \chanel_more.all_chanel.1.all_bit.8.sample_out_s2[135]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[117]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_133); - - \loop_all_sample.9.loop_all_chanel.6.sample_in_buf[26]\ : - DFN1E1C0 - port map(D => \sample_in_buf_525[26]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[26]\); - - \chanel_more.all_chanel.1.all_bit.9.sample_out_s2[134]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[116]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_132); - - \loop_all_sample.11.loop_all_chanel.7.sample_in_buf_RNO[6]\ : - MX2 - port map(A => \sample_in_buf[132]\, B => sample_7(11), S - => sample_val_delay, Y => \sample_in_buf_389[6]\); - - \loop_all_sample.1.loop_all_chanel.6.sample_in_buf_RNO[34]\ : - MX2 - port map(A => \sample_in_buf[16]\, B => sample_6(1), S => - sample_val_delay, Y => \sample_in_buf_1037[34]\); - - \loop_all_sample.3.loop_all_chanel.3.sample_in_buf[86]\ : - DFN1E1C0 - port map(D => \sample_in_buf_933[86]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[86]\); - - \chanel_more.all_chanel.6.all_bit.1.sample_out_s2[52]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[34]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[52]\); - - \chanel_HIGH.6.sample_out_s2[11]\ : DFN1E1C0 - port map(D => \sample_out_s[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[11]\); - - \loop_all_sample.11.loop_all_chanel.2.sample_in_buf_RNO[96]\ : - MX2 - port map(A => \sample_in_buf[78]\, B => sample_2(11), S => - sample_val_delay, Y => \sample_in_buf_429[96]\); - - \chanel_more.all_chanel.1.all_bit.5.sample_out_s2[138]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[120]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_136); - - \loop_all_sample.2.loop_all_chanel.7.sample_in_buf_RNO[15]\ : - MX2 - port map(A => \sample_in_buf[141]\, B => sample_7(2), S => - sample_val_delay, Y => \sample_in_buf_965[15]\); - - \loop_all_sample.13.loop_all_chanel.2.sample_in_buf[94]\ : - DFN1E1C0 - port map(D => \sample_in_buf_301[94]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[94]\); - - \loop_all_sample.17.loop_all_chanel.1.sample_in_buf[108]\ : - DFN1E1C0 - port map(D => \sample_in_buf_53[108]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[108]\); - - \loop_all_sample.0.loop_all_chanel.6.sample_in_buf_RNO[35]\ : - MX2 - port map(A => \sample_in_buf[17]\, B => sample_6(0), S => - sample_val_delay, Y => \sample_in_buf_1101[35]\); - - \loop_all_sample.4.loop_all_chanel.0.sample_in_buf_RNO[139]\ : - MX2 - port map(A => \sample_in_buf[121]\, B => sample_0(4), S => - sample_val_delay, Y => \sample_in_buf_893[139]\); - - \loop_all_sample.0.loop_all_chanel.3.sample_in_buf[89]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1125[89]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[89]\); - - \chanel_more.all_chanel.5.all_bit.9.sample_out_s2[62]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[44]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[62]\); - - \loop_all_sample.11.loop_all_chanel.2.sample_in_buf[96]\ : - DFN1E1C0 - port map(D => \sample_in_buf_429[96]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[96]\); - - \loop_all_sample.1.loop_all_chanel.3.sample_in_buf[88]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1061[88]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[88]\); - - \chanel_more.all_chanel.4.all_bit.11.sample_out_s2[78]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[60]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[78]\); - - \chanel_HIGH.15.sample_out_s2[2]\ : DFN1E1C0 - port map(D => \sample_out_s[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[2]\); - - \loop_all_sample.0.loop_all_chanel.5.sample_in_buf_RNO[53]\ : - MX2 - port map(A => \sample_in_buf[35]\, B => sample_5(0), S => - sample_val_delay, Y => \sample_in_buf_1109[53]\); - - \loop_all_sample.6.loop_all_chanel.4.sample_in_buf[65]\ : - DFN1E1C0 - port map(D => \sample_in_buf_733[65]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[65]\); - - \loop_all_sample.7.loop_all_chanel.7.sample_in_buf_RNO[10]\ : - MX2 - port map(A => \sample_in_buf[136]\, B => sample_7(7), S => - sample_val_delay, Y => \sample_in_buf_645[10]\); - - \loop_all_sample.17.loop_all_chanel.4.sample_in_buf[54]\ : - DFN1E1C0 - port map(D => \sample_in_buf_29[54]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[54]\); - - \loop_all_sample.4.loop_all_chanel.1.sample_in_buf_RNO[121]\ : - MX2 - port map(A => \sample_in_buf[103]\, B => sample_1(4), S => - sample_val_delay, Y => \sample_in_buf_885[121]\); - - \loop_all_sample.13.loop_all_chanel.6.sample_in_buf[22]\ : - DFN1E1C0 - port map(D => \sample_in_buf_269[22]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[22]\); - - \loop_all_sample.17.loop_all_chanel.2.sample_in_buf_RNO[90]\ : - MX2 - port map(A => \sample_in_buf[72]\, B => sample_2(15), S => - sample_val_delay, Y => \sample_in_buf_45[90]\); - - \loop_all_sample.11.loop_all_chanel.6.sample_in_buf_RNO[24]\ : - MX2 - port map(A => \sample_in_buf[6]\, B => sample_6(11), S => - sample_val_delay, Y => \sample_in_buf_397[24]\); - - \loop_all_sample.1.loop_all_chanel.7.sample_in_buf_RNO[16]\ : - MX2 - port map(A => \sample_in_buf[142]\, B => sample_7(1), S => - sample_val_delay, Y => \sample_in_buf_1029[16]\); - - \loop_all_sample.6.loop_all_chanel.7.sample_in_buf[11]\ : - DFN1E1C0 - port map(D => \sample_in_buf_709[11]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[11]\); - - \chanel_more.all_chanel.6.all_bit.8.sample_out_s2[45]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[27]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[45]\); - - \loop_all_sample.7.loop_all_chanel.0.sample_in_buf_RNO[136]\ : - MX2 - port map(A => \sample_in_buf[118]\, B => sample_0(7), S => - sample_val_delay, Y => \sample_in_buf_701[136]\); - - \chanel_more.all_chanel.3.all_bit.10.sample_out_s2[97]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[79]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[97]\); - - \loop_all_sample.4.loop_all_chanel.5.sample_in_buf_RNO[49]\ : - MX2 - port map(A => \sample_in_buf[31]\, B => sample_5(4), S => - sample_val_delay, Y => \sample_in_buf_853[49]\); - - \chanel_more.all_chanel.1.all_bit.13.sample_out_s2[130]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[112]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_128); - - \loop_all_sample.13.loop_all_chanel.5.sample_in_buf_RNO[40]\ : - MX2 - port map(A => \sample_in_buf[22]\, B => sample_5(13), S => - sample_val_delay, Y => \sample_in_buf_277[40]\); - - \loop_all_sample.17.loop_all_chanel.3.sample_in_buf[72]\ : - DFN1E1C0 - port map(D => \sample_in_buf_37[72]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[72]\); - - \chanel_more.all_chanel.6.all_bit.12.sample_out_s2[41]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[23]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[41]\); - - \chanel_more.all_chanel.4.all_bit.4.sample_out_s2[85]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[67]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[85]\); - - \loop_all_sample.5.loop_all_chanel.1.sample_in_buf[120]\ : - DFN1E1C0 - port map(D => \sample_in_buf_821[120]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[120]\); - - \loop_all_sample.11.loop_all_chanel.4.sample_in_buf_RNO[60]\ : - MX2 - port map(A => \sample_in_buf[42]\, B => sample_4(11), S => - sample_val_delay, Y => \sample_in_buf_413[60]\); - - \loop_all_sample.0.loop_all_chanel.1.sample_in_buf_RNO[125]\ : - MX2 - port map(A => \sample_in_buf[107]\, B => sample_1(0), S => - sample_val_delay, Y => \sample_in_buf_1141[125]\); - - \loop_all_sample.7.loop_all_chanel.2.sample_in_buf[100]\ : - DFN1E1C0 - port map(D => \sample_in_buf_685[100]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[100]\); - - \loop_all_sample.9.loop_all_chanel.7.sample_in_buf[8]\ : - DFN1E1C0 - port map(D => \sample_in_buf_517[8]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[8]\); - - \chanel_more.all_chanel.2.all_bit.7.sample_out_s2[118]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[100]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[118]\); - - \chanel_HIGH.9.sample_out_s2[8]\ : DFN1E1C0 - port map(D => \sample_out_s[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[8]\); - - \loop_all_sample.6.loop_all_chanel.5.sample_in_buf[47]\ : - DFN1E1C0 - port map(D => \sample_in_buf_725[47]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[47]\); - - \loop_all_sample.13.loop_all_chanel.4.sample_in_buf[58]\ : - DFN1E1C0 - port map(D => \sample_in_buf_285[58]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[58]\); - - \chanel_more.all_chanel.4.all_bit.5.sample_out_s2[84]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[66]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[84]\); - - \loop_all_sample.4.loop_all_chanel.2.sample_in_buf[103]\ : - DFN1E1C0 - port map(D => \sample_in_buf_877[103]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[103]\); - - \loop_all_sample.1.loop_all_chanel.7.sample_in_buf[16]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1029[16]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[16]\); - - \chanel_HIGH.7.sample_out_s2[10]\ : DFN1E1C0 - port map(D => \sample_out_s[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[10]\); - - \loop_all_sample.13.loop_all_chanel.7.sample_in_buf_RNO[4]\ : - MX2 - port map(A => \sample_in_buf[130]\, B => sample_7(13), S - => sample_val_delay, Y => \sample_in_buf_261[4]\); - - \loop_all_sample.11.loop_all_chanel.7.sample_in_buf[6]\ : - DFN1E1C0 - port map(D => \sample_in_buf_389[6]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[6]\); - - GND_i : GND - port map(Y => \GND\); - - \loop_all_sample.1.loop_all_chanel.3.sample_in_buf_RNO[88]\ : - MX2 - port map(A => \sample_in_buf[70]\, B => sample_3(1), S => - sample_val_delay, Y => \sample_in_buf_1061[88]\); - - \loop_all_sample.13.loop_all_chanel.4.sample_in_buf_RNO[58]\ : - MX2 - port map(A => \sample_in_buf[40]\, B => sample_4(13), S => - sample_val_delay, Y => \sample_in_buf_285[58]\); - - \chanel_more.all_chanel.1.all_bit.4.sample_out_s2[139]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[121]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_137); - - \chanel_more.all_chanel.7.all_bit.6.sample_out_s2[29]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[11]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[29]\); - - \loop_all_sample.2.loop_all_chanel.2.sample_in_buf_RNO[105]\ : - MX2 - port map(A => \sample_in_buf[87]\, B => sample_2(2), S => - sample_val_delay, Y => \sample_in_buf_1005[105]\); - - \loop_all_sample.10.loop_all_chanel.2.sample_in_buf[97]\ : - DFN1E1C0 - port map(D => \sample_in_buf_493[97]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[97]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \loop_all_sample.2.loop_all_chanel.5.sample_in_buf_RNO[51]\ : - MX2 - port map(A => \sample_in_buf[33]\, B => sample_5(2), S => - sample_val_delay, Y => \sample_in_buf_981[51]\); - - \loop_all_sample.17.loop_all_chanel.5.sample_in_buf[36]\ : - DFN1E1C0 - port map(D => \sample_in_buf_21[36]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[36]\); - - \loop_all_sample.17.loop_all_chanel.3.sample_in_buf_RNO[72]\ : - MX2 - port map(A => \sample_in_buf[54]\, B => sample_3(15), S => - sample_val_delay, Y => \sample_in_buf_37[72]\); - - \chanel_more.all_chanel.2.all_bit.9.sample_out_s2[116]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[98]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[116]\); - - \loop_all_sample.7.loop_all_chanel.1.sample_in_buf_RNO[118]\ : - MX2 - port map(A => \sample_in_buf[100]\, B => sample_1(7), S => - sample_val_delay, Y => \sample_in_buf_693[118]\); - - \chanel_more.all_chanel.2.all_bit.10.sample_out_s2[115]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[97]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[115]\); - - \chanel_more.all_chanel.3.all_bit.6.sample_out_s2[101]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[83]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[101]\); - - \loop_all_sample.9.loop_all_chanel.4.sample_in_buf[62]\ : - DFN1E1C0 - port map(D => \sample_in_buf_541[62]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[62]\); - - \loop_all_sample.14.loop_all_chanel.0.sample_in_buf[129]\ : - DFN1E1C0 - port map(D => \sample_in_buf_253[129]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[129]\); - - \loop_all_sample.7.loop_all_chanel.0.sample_in_buf[136]\ : - DFN1E1C0 - port map(D => \sample_in_buf_701[136]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[136]\); - - \chanel_more.all_chanel.4.all_bit.0.sample_out_s2[89]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[71]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[89]\); - - \loop_all_sample.3.loop_all_chanel.2.sample_in_buf[104]\ : - DFN1E1C0 - port map(D => \sample_in_buf_941[104]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[104]\); - - \loop_all_sample.5.loop_all_chanel.2.sample_in_buf_RNO[102]\ : - MX2 - port map(A => \sample_in_buf[84]\, B => sample_2(5), S => - sample_val_delay, Y => \sample_in_buf_813[102]\); - - \loop_all_sample.4.loop_all_chanel.1.sample_in_buf[121]\ : - DFN1E1C0 - port map(D => \sample_in_buf_885[121]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[121]\); - - \chanel_more.all_chanel.6.all_bit.11.sample_out_s2[42]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[24]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[42]\); - - \loop_all_sample.10.loop_all_chanel.5.sample_in_buf[43]\ : - DFN1E1C0 - port map(D => \sample_in_buf_469[43]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[43]\); - - \chanel_more.all_chanel.5.all_bit.0.sample_out_s2[71]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[53]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[71]\); - - \loop_all_sample.11.loop_all_chanel.0.sample_in_buf_RNO[132]\ : - MX2 - port map(A => \sample_in_buf[114]\, B => sample_0(11), S - => sample_val_delay, Y => \sample_in_buf_445[132]\); - - \chanel_more.all_chanel.6.all_bit.6.sample_out_s2[47]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[29]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[47]\); - - \loop_all_sample.12.loop_all_chanel.2.sample_in_buf[95]\ : - DFN1E1C0 - port map(D => \sample_in_buf_365[95]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[95]\); - - \chanel_more.all_chanel.7.all_bit.1.sample_out_s2[34]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[16]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[34]\); - - \loop_all_sample.6.loop_all_chanel.2.sample_in_buf[101]\ : - DFN1E1C0 - port map(D => \sample_in_buf_749[101]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[101]\); - - \loop_all_sample.9.loop_all_chanel.1.sample_in_buf_RNO[116]\ : - MX2 - port map(A => \sample_in_buf[98]\, B => sample_1(9), S => - sample_val_delay, Y => \sample_in_buf_565[116]\); - - \loop_all_sample.4.loop_all_chanel.2.sample_in_buf_RNO[103]\ : - MX2 - port map(A => \sample_in_buf[85]\, B => sample_2(4), S => - sample_val_delay, Y => \sample_in_buf_877[103]\); - - \loop_all_sample.10.loop_all_chanel.1.sample_in_buf_RNO[115]\ : - MX2 - port map(A => \sample_in_buf[97]\, B => sample_1(10), S => - sample_val_delay, Y => \sample_in_buf_501[115]\); - - \loop_all_sample.5.loop_all_chanel.5.sample_in_buf_RNO[48]\ : - MX2 - port map(A => \sample_in_buf[30]\, B => sample_5(5), S => - sample_val_delay, Y => \sample_in_buf_789[48]\); - - \loop_all_sample.3.loop_all_chanel.2.sample_in_buf_RNO[104]\ : - MX2 - port map(A => \sample_in_buf[86]\, B => sample_2(3), S => - sample_val_delay, Y => \sample_in_buf_941[104]\); - - \chanel_more.all_chanel.7.all_bit.15.sample_out_s2[20]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[20]\); - - \loop_all_sample.2.loop_all_chanel.1.sample_in_buf[123]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1013[123]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[123]\); - - \chanel_HIGH.13.sample_out_s2[4]\ : DFN1E1C0 - port map(D => \sample_out_s[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[4]\); - - \loop_all_sample.10.loop_all_chanel.6.sample_in_buf[25]\ : - DFN1E1C0 - port map(D => \sample_in_buf_461[25]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[25]\); - - \chanel_more.all_chanel.3.all_bit.13.sample_out_s2[94]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[76]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[94]\); - - \loop_all_sample.3.loop_all_chanel.1.sample_in_buf_RNO[122]\ : - MX2 - port map(A => \sample_in_buf[104]\, B => sample_1(3), S => - sample_val_delay, Y => \sample_in_buf_949[122]\); - - \loop_all_sample.2.loop_all_chanel.1.sample_in_buf_RNO[123]\ : - MX2 - port map(A => \sample_in_buf[105]\, B => sample_1(2), S => - sample_val_delay, Y => \sample_in_buf_1013[123]\); - - \loop_all_sample.3.loop_all_chanel.0.sample_in_buf_RNO[140]\ : - MX2 - port map(A => \sample_in_buf[122]\, B => sample_0(3), S => - sample_val_delay, Y => \sample_in_buf_957[140]\); - - \loop_all_sample.7.loop_all_chanel.6.sample_in_buf_RNO[28]\ : - MX2 - port map(A => \sample_in_buf[10]\, B => sample_6(7), S => - sample_val_delay, Y => \sample_in_buf_653[28]\); - - \loop_all_sample.8.loop_all_chanel.3.sample_in_buf_RNO[81]\ : - MX2 - port map(A => \sample_in_buf[63]\, B => sample_3(8), S => - sample_val_delay, Y => \sample_in_buf_613[81]\); - - \loop_all_sample.14.loop_all_chanel.5.sample_in_buf_RNO[39]\ : - MX2 - port map(A => \sample_in_buf[21]\, B => sample_5(14), S => - sample_val_delay, Y => \sample_in_buf_213[39]\); - - \loop_all_sample.12.loop_all_chanel.7.sample_in_buf_RNO[5]\ : - MX2 - port map(A => \sample_in_buf[131]\, B => sample_7(12), S - => sample_val_delay, Y => \sample_in_buf_325[5]\); - - \loop_all_sample.0.loop_all_chanel.2.sample_in_buf_RNO[107]\ : - MX2 - port map(A => \sample_in_buf[89]\, B => sample_2(0), S => - sample_val_delay, Y => \sample_in_buf_1133[107]\); - - \chanel_more.all_chanel.1.all_bit.15.sample_out_s2[128]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[110]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_126); - - \loop_all_sample.8.loop_all_chanel.1.sample_in_buf[117]\ : - DFN1E1C0 - port map(D => \sample_in_buf_629[117]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[117]\); - - \loop_all_sample.11.loop_all_chanel.1.sample_in_buf_RNO[114]\ : - MX2 - port map(A => \sample_in_buf[96]\, B => sample_1(11), S => - sample_val_delay, Y => \sample_in_buf_437[114]\); - - \loop_all_sample.5.loop_all_chanel.3.sample_in_buf_RNO[84]\ : - MX2 - port map(A => \sample_in_buf[66]\, B => sample_3(5), S => - sample_val_delay, Y => \sample_in_buf_805[84]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \chanel_more.all_chanel.6.all_bit.3.sample_out_s2[50]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[32]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[50]\); - - \loop_all_sample.2.loop_all_chanel.5.sample_in_buf[51]\ : - DFN1E1C0 - port map(D => \sample_in_buf_981[51]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[51]\); - - \chanel_more.all_chanel.7.all_bit.7.sample_out_s2[28]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[10]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[28]\); - - \chanel_more.all_chanel.2.all_bit.15.sample_out_s2[110]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[92]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[110]\); - - \loop_all_sample.8.loop_all_chanel.5.sample_in_buf[45]\ : - DFN1E1C0 - port map(D => \sample_in_buf_597[45]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[45]\); - - \loop_all_sample.9.loop_all_chanel.7.sample_in_buf_RNO[8]\ : - MX2 - port map(A => \sample_in_buf[134]\, B => sample_7(9), S => - sample_val_delay, Y => \sample_in_buf_517[8]\); - - \loop_all_sample.4.loop_all_chanel.6.sample_in_buf_RNO[31]\ : - MX2 - port map(A => \sample_in_buf[13]\, B => sample_6(4), S => - sample_val_delay, Y => \sample_in_buf_845[31]\); - - \loop_all_sample.8.loop_all_chanel.5.sample_in_buf_RNO[45]\ : - MX2 - port map(A => \sample_in_buf[27]\, B => sample_5(8), S => - sample_val_delay, Y => \sample_in_buf_597[45]\); - - \loop_all_sample.11.loop_all_chanel.1.sample_in_buf[114]\ : - DFN1E1C0 - port map(D => \sample_in_buf_437[114]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[114]\); - - \loop_all_sample.2.loop_all_chanel.0.sample_in_buf[141]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1021[141]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[141]\); - - \loop_all_sample.14.loop_all_chanel.4.sample_in_buf[57]\ : - DFN1E1C0 - port map(D => \sample_in_buf_221[57]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[57]\); - - IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW - port map(alu_ctrl(2) => \alu_ctrl[2]\, alu_ctrl(1) => - \alu_ctrl[1]\, alu_ctrl(0) => \alu_ctrl[0]\, S(8) => - \S[8]\, S_i_0(33) => \S_i_0[33]\, alu_sel_coeff(4) => - \alu_sel_coeff[4]\, alu_sel_coeff(3) => - \alu_sel_coeff[3]\, alu_sel_coeff(2) => - \alu_sel_coeff[2]\, alu_sel_coeff(1) => - \alu_sel_coeff[1]\, alu_sel_coeff(0) => - \alu_sel_coeff[0]\, alu_sel_coeff_0_2 => - \alu_sel_coeff_0[2]\, alu_sel_coeff_0_0 => - \alu_sel_coeff_0[0]\, waddr_previous(1) => - \waddr_previous[1]\, waddr_previous(0) => - \waddr_previous[0]\, sample_0(14) => sample_0(14), - sample_0(13) => sample_0(13), sample_0(12) => - sample_0(12), sample_0(11) => sample_0(11), sample_0(10) - => sample_0(10), sample_0(9) => sample_0(9), sample_0(8) - => sample_0(8), sample_0(7) => sample_0(7), sample_0(6) - => sample_0(6), sample_0(5) => sample_0(5), sample_0(4) - => sample_0(4), sample_0(3) => sample_0(3), sample_0(2) - => sample_0(2), sample_0(1) => sample_0(1), sample_0(0) - => sample_0(0), sample_in_buf(143) => - \sample_in_buf[143]\, sample_in_buf(142) => - \sample_in_buf[142]\, sample_in_buf(141) => - \sample_in_buf[141]\, sample_in_buf(140) => - \sample_in_buf[140]\, sample_in_buf(139) => - \sample_in_buf[139]\, sample_in_buf(138) => - \sample_in_buf[138]\, sample_in_buf(137) => - \sample_in_buf[137]\, sample_in_buf(136) => - \sample_in_buf[136]\, sample_in_buf(135) => - \sample_in_buf[135]\, sample_in_buf(134) => - \sample_in_buf[134]\, sample_in_buf(133) => - \sample_in_buf[133]\, sample_in_buf(132) => - \sample_in_buf[132]\, sample_in_buf(131) => - \sample_in_buf[131]\, sample_in_buf(130) => - \sample_in_buf[130]\, sample_in_buf(129) => - \sample_in_buf[129]\, ram_sel_Wdata(1) => - \ram_sel_Wdata[1]\, ram_sel_Wdata(0) => - \ram_sel_Wdata[0]\, sample_out_s_0 => \sample_out_s[0]\, - sample_out_s_1 => \sample_out_s[1]\, sample_out_s_3 => - \sample_out_s[3]\, sample_out_s_2 => \sample_out_s[2]\, - sample_out_s_10 => \sample_out_s[10]\, sample_out_s_15 - => \sample_out_s[15]\, sample_out_s_14 => - \sample_out_s[14]\, sample_out_s_13 => \sample_out_s[13]\, - sample_out_s_12 => \sample_out_s[12]\, sample_out_s_11 - => \sample_out_s[11]\, sample_out_s_9 => - \sample_out_s[9]\, sample_out_s_8 => \sample_out_s[8]\, - sample_out_s_7 => \sample_out_s[7]\, sample_out_s_6 => - \sample_out_s[6]\, sample_out_s_5 => \sample_out_s[5]\, - sample_out_s_4 => \sample_out_s[4]\, sample_in_s_1(17) - => \sample_in_s_1[17]\, in_sel_src(1) => \in_sel_src[1]\, - in_sel_src(0) => \in_sel_src[0]\, raddr_rst => raddr_rst, - raddr_add1 => raddr_add1, ram_write => ram_write, - IIR_CEL_CTRLR_v2_DATAFLOW_GND => IIR_CEL_CTRLR_v2_GND, - IIR_CEL_CTRLR_v2_DATAFLOW_VCC => IIR_CEL_CTRLR_v2_VCC, - ram_write_i => ram_write_i, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, sample_val_delay => sample_val_delay, - alu_sel_input => alu_sel_input); - - sample_out_val : DFN1C0 - port map(D => \sample_out_val_s2\, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_filter_v2_out_val); - - \loop_all_sample.8.loop_all_chanel.3.sample_in_buf[81]\ : - DFN1E1C0 - port map(D => \sample_in_buf_613[81]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[81]\); - - \loop_all_sample.17.loop_all_chanel.4.sample_in_buf_RNO[54]\ : - MX2 - port map(A => \sample_in_buf[36]\, B => sample_4(15), S => - sample_val_delay, Y => \sample_in_buf_29[54]\); - - \loop_all_sample.4.loop_all_chanel.3.sample_in_buf[85]\ : - DFN1E1C0 - port map(D => \sample_in_buf_869[85]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[85]\); - - \loop_all_sample.3.loop_all_chanel.4.sample_in_buf[68]\ : - DFN1E1C0 - port map(D => \sample_in_buf_925[68]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[68]\); - - \loop_all_sample.10.loop_all_chanel.7.sample_in_buf_RNO[7]\ : - MX2 - port map(A => \sample_in_buf[133]\, B => sample_7(10), S - => sample_val_delay, Y => \sample_in_buf_453[7]\); - - \loop_all_sample.10.loop_all_chanel.4.sample_in_buf[61]\ : - DFN1E1C0 - port map(D => \sample_in_buf_477[61]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[61]\); - - \loop_all_sample.10.loop_all_chanel.3.sample_in_buf[79]\ : - DFN1E1C0 - port map(D => \sample_in_buf_485[79]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[79]\); - - \chanel_more.all_chanel.4.all_bit.15.sample_out_s2[74]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[56]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[74]\); - - \chanel_more.all_chanel.2.all_bit.5.sample_out_s2[120]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[102]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[120]\); - - \chanel_more.all_chanel.2.all_bit.14.sample_out_s2[111]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[93]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[111]\); - - \chanel_more.all_chanel.2.all_bit.6.sample_out_s2[119]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[101]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[119]\); - - \loop_all_sample.11.loop_all_chanel.0.sample_in_buf[132]\ : - DFN1E1C0 - port map(D => \sample_in_buf_445[132]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[132]\); - - \chanel_more.all_chanel.7.all_bit.13.sample_out_s2[22]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[22]\); - - \loop_all_sample.6.loop_all_chanel.5.sample_in_buf_RNO[47]\ : - MX2 - port map(A => \sample_in_buf[29]\, B => sample_5(6), S => - sample_val_delay, Y => \sample_in_buf_725[47]\); - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf_RNO[126]\ : - MX2 - port map(A => \sample_in_buf[108]\, B => sample_0(15), S - => sample_val_delay, Y => \sample_in_buf_61[126]\); - - \loop_all_sample.6.loop_all_chanel.6.sample_in_buf[29]\ : - DFN1E1C0 - port map(D => \sample_in_buf_717[29]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[29]\); - - \loop_all_sample.1.loop_all_chanel.2.sample_in_buf_RNO[106]\ : - MX2 - port map(A => \sample_in_buf[88]\, B => sample_2(1), S => - sample_val_delay, Y => \sample_in_buf_1069[106]\); - - \loop_all_sample.0.loop_all_chanel.6.sample_in_buf[35]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1101[35]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[35]\); - - \chanel_more.all_chanel.3.all_bit.0.sample_out_s2[107]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[89]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[107]\); - - \loop_all_sample.4.loop_all_chanel.6.sample_in_buf[31]\ : - DFN1E1C0 - port map(D => \sample_in_buf_845[31]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[31]\); - - \chanel_more.all_chanel.4.all_bit.8.sample_out_s2[81]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[63]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[81]\); - - \chanel_more.all_chanel.6.all_bit.14.sample_out_s2[39]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[21]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[39]\); - - \loop_all_sample.12.loop_all_chanel.3.sample_in_buf_RNO[77]\ : - MX2 - port map(A => \sample_in_buf[59]\, B => sample_3(12), S => - sample_val_delay, Y => \sample_in_buf_357[77]\); - - \loop_all_sample.1.loop_all_chanel.5.sample_in_buf_RNO[52]\ : - MX2 - port map(A => \sample_in_buf[34]\, B => sample_5(1), S => - sample_val_delay, Y => \sample_in_buf_1045[52]\); - - \chanel_more.all_chanel.7.all_bit.14.sample_out_s2[21]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[21]\); - - \loop_all_sample.2.loop_all_chanel.2.sample_in_buf[105]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1005[105]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[105]\); - - \loop_all_sample.10.loop_all_chanel.6.sample_in_buf_RNO[25]\ : - MX2 - port map(A => \sample_in_buf[7]\, B => sample_6(10), S => - sample_val_delay, Y => \sample_in_buf_461[25]\); - - \chanel_more.all_chanel.3.all_bit.14.sample_out_s2[93]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[75]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[93]\); - - \loop_all_sample.2.loop_all_chanel.0.sample_in_buf_RNO[141]\ : - MX2 - port map(A => \sample_in_buf[123]\, B => sample_0(2), S => - sample_val_delay, Y => \sample_in_buf_1021[141]\); - - \loop_all_sample.3.loop_all_chanel.1.sample_in_buf[122]\ : - DFN1E1C0 - port map(D => \sample_in_buf_949[122]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[122]\); - - \chanel_more.all_chanel.4.all_bit.9.sample_out_s2[80]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[62]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[80]\); - - \chanel_more.all_chanel.4.all_bit.6.sample_out_s2[83]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[65]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[83]\); - - \loop_all_sample.13.loop_all_chanel.6.sample_in_buf_RNO[22]\ : - MX2 - port map(A => \sample_in_buf[4]\, B => sample_6(13), S => - sample_val_delay, Y => \sample_in_buf_269[22]\); - - \loop_all_sample.8.loop_all_chanel.6.sample_in_buf[27]\ : - DFN1E1C0 - port map(D => \sample_in_buf_589[27]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[27]\); - - \loop_all_sample.2.loop_all_chanel.3.sample_in_buf[87]\ : - DFN1E1C0 - port map(D => \sample_in_buf_997[87]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[87]\); - - \chanel_more.all_chanel.3.all_bit.15.sample_out_s2[92]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[74]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[92]\); - - \loop_all_sample.3.loop_all_chanel.3.sample_in_buf_RNO[86]\ : - MX2 - port map(A => \sample_in_buf[68]\, B => sample_3(3), S => - sample_val_delay, Y => \sample_in_buf_933[86]\); - - \chanel_more.all_chanel.6.all_bit.10.sample_out_s2[43]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[25]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[43]\); - - \loop_all_sample.6.loop_all_chanel.4.sample_in_buf_RNO[65]\ : - MX2 - port map(A => \sample_in_buf[47]\, B => sample_4(6), S => - sample_val_delay, Y => \sample_in_buf_733[65]\); - - \loop_all_sample.0.loop_all_chanel.0.sample_in_buf[143]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1149[143]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[143]\); - - \loop_all_sample.3.loop_all_chanel.0.sample_in_buf[140]\ : - DFN1E1C0 - port map(D => \sample_in_buf_957[140]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[140]\); - - \loop_all_sample.1.loop_all_chanel.4.sample_in_buf[70]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1053[70]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[70]\); - - \loop_all_sample.14.loop_all_chanel.2.sample_in_buf[93]\ : - DFN1E1C0 - port map(D => \sample_in_buf_237[93]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[93]\); - - \chanel_HIGH.14.sample_out_s2[3]\ : DFN1E1C0 - port map(D => \sample_out_s[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[3]\); - - \loop_all_sample.9.loop_all_chanel.1.sample_in_buf[116]\ : - DFN1E1C0 - port map(D => \sample_in_buf_565[116]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[116]\); - - \loop_all_sample.17.loop_all_chanel.2.sample_in_buf[90]\ : - DFN1E1C0 - port map(D => \sample_in_buf_45[90]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[90]\); - - \loop_all_sample.0.loop_all_chanel.2.sample_in_buf[107]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1133[107]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[107]\); - - \loop_all_sample.4.loop_all_chanel.4.sample_in_buf_RNO[67]\ : - MX2 - port map(A => \sample_in_buf[49]\, B => sample_4(4), S => - sample_val_delay, Y => \sample_in_buf_861[67]\); - - \loop_all_sample.8.loop_all_chanel.0.sample_in_buf[135]\ : - DFN1E1C0 - port map(D => \sample_in_buf_637[135]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[135]\); - - \chanel_more.all_chanel.5.all_bit.13.sample_out_s2[58]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[40]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[58]\); - - \chanel_HIGH.2.sample_out_s2[15]\ : DFN1E1C0 - port map(D => \sample_out_s[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[15]\); - - \chanel_more.all_chanel.4.all_bit.10.sample_out_s2[79]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[61]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[79]\); - - \loop_all_sample.12.loop_all_chanel.2.sample_in_buf_RNO[95]\ : - MX2 - port map(A => \sample_in_buf[77]\, B => sample_2(12), S => - sample_val_delay, Y => \sample_in_buf_365[95]\); - - \loop_all_sample.5.loop_all_chanel.5.sample_in_buf[48]\ : - DFN1E1C0 - port map(D => \sample_in_buf_789[48]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[48]\); - - \loop_all_sample.14.loop_all_chanel.7.sample_in_buf[3]\ : - DFN1E1C0 - port map(D => \sample_in_buf_197[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[3]\); - - \chanel_more.all_chanel.7.all_bit.10.sample_out_s2[25]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[7]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[25]\); - - \loop_all_sample.12.loop_all_chanel.3.sample_in_buf[77]\ : - DFN1E1C0 - port map(D => \sample_in_buf_357[77]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[77]\); - - \chanel_more.all_chanel.3.all_bit.3.sample_out_s2[104]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[86]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[104]\); - - sample_out_val_s2 : DFN1C0 - port map(D => sample_out_val_s, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sample_out_val_s2\); - - \chanel_more.all_chanel.7.all_bit.9.sample_out_s2[26]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[8]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[26]\); - - \loop_all_sample.5.loop_all_chanel.6.sample_in_buf_RNO[30]\ : - MX2 - port map(A => \sample_in_buf[12]\, B => sample_6(5), S => - sample_val_delay, Y => \sample_in_buf_781[30]\); - - \loop_all_sample.14.loop_all_chanel.5.sample_in_buf[39]\ : - DFN1E1C0 - port map(D => \sample_in_buf_213[39]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[39]\); - - \chanel_more.all_chanel.2.all_bit.0.sample_out_s2[125]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[107]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[125]\); - - \chanel_more.all_chanel.2.all_bit.2.sample_out_s2[123]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[105]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[123]\); - - \chanel_more.all_chanel.3.all_bit.7.sample_out_s2[100]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[82]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[100]\); - - \loop_all_sample.4.loop_all_chanel.7.sample_in_buf_RNO[13]\ : - MX2 - port map(A => \sample_in_buf[139]\, B => sample_7(4), S => - sample_val_delay, Y => \sample_in_buf_837[13]\); - - \loop_all_sample.14.loop_all_chanel.6.sample_in_buf_RNO[21]\ : - MX2 - port map(A => \sample_in_buf[3]\, B => sample_6(14), S => - sample_val_delay, Y => \sample_in_buf_205[21]\); - - \chanel_more.all_chanel.2.all_bit.13.sample_out_s2[112]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[94]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[112]\); - - \loop_all_sample.9.loop_all_chanel.6.sample_in_buf_RNO[26]\ : - MX2 - port map(A => \sample_in_buf[8]\, B => sample_6(9), S => - sample_val_delay, Y => \sample_in_buf_525[26]\); - - \loop_all_sample.9.loop_all_chanel.3.sample_in_buf[80]\ : - DFN1E1C0 - port map(D => \sample_in_buf_549[80]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[80]\); - - \loop_all_sample.7.loop_all_chanel.7.sample_in_buf[10]\ : - DFN1E1C0 - port map(D => \sample_in_buf_645[10]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[10]\); - - \loop_all_sample.12.loop_all_chanel.1.sample_in_buf_RNO[113]\ : - MX2 - port map(A => \sample_in_buf[95]\, B => sample_1(12), S => - sample_val_delay, Y => \sample_in_buf_373[113]\); - - \chanel_HIGH.1.sample_out_s2[16]\ : DFN1E1C0 - port map(D => \sample_out_s[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[16]\); - - \loop_all_sample.8.loop_all_chanel.4.sample_in_buf_RNO[63]\ : - MX2 - port map(A => \sample_in_buf[45]\, B => sample_4(8), S => - sample_val_delay, Y => \sample_in_buf_605[63]\); - - \loop_all_sample.6.loop_all_chanel.7.sample_in_buf_RNO[11]\ : - MX2 - port map(A => \sample_in_buf[137]\, B => sample_7(6), S => - sample_val_delay, Y => \sample_in_buf_709[11]\); - - \loop_all_sample.14.loop_all_chanel.0.sample_in_buf_RNO[129]\ : - MX2 - port map(A => \sample_in_buf[111]\, B => sample_0(14), S - => sample_val_delay, Y => \sample_in_buf_253[129]\); - - \chanel_HIGH.12.sample_out_s2[5]\ : DFN1E1C0 - port map(D => \sample_out_s[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[5]\); - - \loop_all_sample.3.loop_all_chanel.6.sample_in_buf[32]\ : - DFN1E1C0 - port map(D => \sample_in_buf_909[32]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[32]\); - - \loop_all_sample.17.loop_all_chanel.5.sample_in_buf_RNO[36]\ : - MX2 - port map(A => \sample_in_buf[18]\, B => sample_5(15), S => - sample_val_delay, Y => \sample_in_buf_21[36]\); - - \chanel_more.all_chanel.5.all_bit.8.sample_out_s2[63]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[45]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[63]\); - - \loop_all_sample.8.loop_all_chanel.7.sample_in_buf_RNO[9]\ : - MX2 - port map(A => \sample_in_buf[135]\, B => sample_7(8), S => - sample_val_delay, Y => \sample_in_buf_581[9]\); - - \loop_all_sample.5.loop_all_chanel.7.sample_in_buf_RNO[12]\ : - MX2 - port map(A => \sample_in_buf[138]\, B => sample_7(5), S => - sample_val_delay, Y => \sample_in_buf_773[12]\); - - \loop_all_sample.1.loop_all_chanel.4.sample_in_buf_RNO[70]\ : - MX2 - port map(A => \sample_in_buf[52]\, B => sample_4(1), S => - sample_val_delay, Y => \sample_in_buf_1053[70]\); - - \loop_all_sample.7.loop_all_chanel.6.sample_in_buf[28]\ : - DFN1E1C0 - port map(D => \sample_in_buf_653[28]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[28]\); - - \loop_all_sample.13.loop_all_chanel.3.sample_in_buf[76]\ : - DFN1E1C0 - port map(D => \sample_in_buf_293[76]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[76]\); - - \loop_all_sample.17.loop_all_chanel.6.sample_in_buf[18]\ : - DFN1E1C0 - port map(D => \sample_in_buf_13[18]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[18]\); - - \loop_all_sample.0.loop_all_chanel.3.sample_in_buf_RNO[89]\ : - MX2 - port map(A => \sample_in_buf[71]\, B => sample_3(0), S => - sample_val_delay, Y => \sample_in_buf_1125[89]\); - - \chanel_more.all_chanel.2.all_bit.11.sample_out_s2[114]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[96]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[114]\); - - \loop_all_sample.12.loop_all_chanel.1.sample_in_buf[113]\ : - DFN1E1C0 - port map(D => \sample_in_buf_373[113]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[113]\); - - \loop_all_sample.0.loop_all_chanel.4.sample_in_buf_RNO[71]\ : - MX2 - port map(A => \sample_in_buf[53]\, B => sample_4(0), S => - sample_val_delay, Y => \sample_in_buf_1117[71]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \loop_all_sample.13.loop_all_chanel.1.sample_in_buf[112]\ : - DFN1E1C0 - port map(D => \sample_in_buf_309[112]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[112]\); - - \chanel_more.all_chanel.6.all_bit.9.sample_out_s2[44]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[26]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[44]\); - - \chanel_more.all_chanel.2.all_bit.1.sample_out_s2[124]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[106]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[124]\); - - \loop_all_sample.12.loop_all_chanel.4.sample_in_buf[59]\ : - DFN1E1C0 - port map(D => \sample_in_buf_349[59]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[59]\); - - \loop_all_sample.8.loop_all_chanel.7.sample_in_buf[9]\ : - DFN1E1C0 - port map(D => \sample_in_buf_581[9]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[9]\); - - \chanel_HIGH.5.sample_out_s2[12]\ : DFN1E1C0 - port map(D => \sample_out_s[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[12]\); - - \loop_all_sample.5.loop_all_chanel.0.sample_in_buf[138]\ : - DFN1E1C0 - port map(D => \sample_in_buf_829[138]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[138]\); - - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf_RNIF75G[126]\ : - MX2 - port map(A => \sample_in_buf[128]\, B => sample_0(15), S - => sample_val_delay, Y => \sample_in_s_1[17]\); - - \loop_all_sample.3.loop_all_chanel.5.sample_in_buf[50]\ : - DFN1E1C0 - port map(D => \sample_in_buf_917[50]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[50]\); - - \loop_all_sample.0.loop_all_chanel.1.sample_in_buf[125]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1141[125]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[125]\); - - \loop_all_sample.9.loop_all_chanel.2.sample_in_buf[98]\ : - DFN1E1C0 - port map(D => \sample_in_buf_557[98]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[98]\); - - \loop_all_sample.6.loop_all_chanel.0.sample_in_buf[137]\ : - DFN1E1C0 - port map(D => \sample_in_buf_765[137]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[137]\); - - \loop_all_sample.3.loop_all_chanel.5.sample_in_buf_RNO[50]\ : - MX2 - port map(A => \sample_in_buf[32]\, B => sample_5(3), S => - sample_val_delay, Y => \sample_in_buf_917[50]\); - - \loop_all_sample.1.loop_all_chanel.1.sample_in_buf[124]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1077[124]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[124]\); - - \loop_all_sample.14.loop_all_chanel.3.sample_in_buf_RNO[75]\ : - MX2 - port map(A => \sample_in_buf[57]\, B => sample_3(14), S => - sample_val_delay, Y => \sample_in_buf_229[75]\); - - \chanel_HIGH.4.sample_out_s2[13]\ : DFN1E1C0 - port map(D => \sample_out_s[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[13]\); - - \chanel_HIGH.0.sample_out_s2[17]\ : DFN1E1C0 - port map(D => \sample_out_s[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[17]\); - - \loop_all_sample.7.loop_all_chanel.4.sample_in_buf[64]\ : - DFN1E1C0 - port map(D => \sample_in_buf_669[64]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[64]\); - - \chanel_more.all_chanel.1.all_bit.1.sample_out_s2[142]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[124]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_140); - - \loop_all_sample.6.loop_all_chanel.6.sample_in_buf_RNO[29]\ : - MX2 - port map(A => \sample_in_buf[11]\, B => sample_6(6), S => - sample_val_delay, Y => \sample_in_buf_717[29]\); - - \loop_all_sample.14.loop_all_chanel.4.sample_in_buf_RNO[57]\ : - MX2 - port map(A => \sample_in_buf[39]\, B => sample_4(14), S => - sample_val_delay, Y => \sample_in_buf_221[57]\); - - \loop_all_sample.12.loop_all_chanel.6.sample_in_buf_RNO[23]\ : - MX2 - port map(A => \sample_in_buf[5]\, B => sample_6(12), S => - sample_val_delay, Y => \sample_in_buf_333[23]\); - - \chanel_more.all_chanel.5.all_bit.4.sample_out_s2[67]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[49]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[67]\); - - \chanel_more.all_chanel.3.all_bit.9.sample_out_s2[98]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[80]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[98]\); - - \loop_all_sample.7.loop_all_chanel.5.sample_in_buf[46]\ : - DFN1E1C0 - port map(D => \sample_in_buf_661[46]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[46]\); - - \loop_all_sample.9.loop_all_chanel.0.sample_in_buf[134]\ : - DFN1E1C0 - port map(D => \sample_in_buf_573[134]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[134]\); - - \chanel_more.all_chanel.4.all_bit.3.sample_out_s2[86]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[68]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[86]\); - - \loop_all_sample.5.loop_all_chanel.7.sample_in_buf[12]\ : - DFN1E1C0 - port map(D => \sample_in_buf_773[12]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[12]\); - - \loop_all_sample.4.loop_all_chanel.7.sample_in_buf[13]\ : - DFN1E1C0 - port map(D => \sample_in_buf_837[13]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[13]\); - - \loop_all_sample.2.loop_all_chanel.4.sample_in_buf[69]\ : - DFN1E1C0 - port map(D => \sample_in_buf_989[69]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[69]\); - - \loop_all_sample.12.loop_all_chanel.0.sample_in_buf[131]\ : - DFN1E1C0 - port map(D => \sample_in_buf_381[131]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[131]\); - - \loop_all_sample.4.loop_all_chanel.5.sample_in_buf[49]\ : - DFN1E1C0 - port map(D => \sample_in_buf_853[49]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[49]\); - - \loop_all_sample.11.loop_all_chanel.6.sample_in_buf[24]\ : - DFN1E1C0 - port map(D => \sample_in_buf_397[24]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[24]\); - - \loop_all_sample.3.loop_all_chanel.7.sample_in_buf_RNO[14]\ : - MX2 - port map(A => \sample_in_buf[140]\, B => sample_7(3), S => - sample_val_delay, Y => \sample_in_buf_901[14]\); - - \loop_all_sample.1.loop_all_chanel.0.sample_in_buf[142]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1085[142]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[142]\); - - \loop_all_sample.8.loop_all_chanel.4.sample_in_buf[63]\ : - DFN1E1C0 - port map(D => \sample_in_buf_605[63]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[63]\); - - \loop_all_sample.10.loop_all_chanel.1.sample_in_buf[115]\ : - DFN1E1C0 - port map(D => \sample_in_buf_501[115]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[115]\); - - \loop_all_sample.0.loop_all_chanel.4.sample_in_buf[71]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1117[71]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[71]\); - - \loop_all_sample.4.loop_all_chanel.3.sample_in_buf_RNO[85]\ : - MX2 - port map(A => \sample_in_buf[67]\, B => sample_3(4), S => - sample_val_delay, Y => \sample_in_buf_869[85]\); - - \loop_all_sample.13.loop_all_chanel.3.sample_in_buf_RNO[76]\ : - MX2 - port map(A => \sample_in_buf[58]\, B => sample_3(13), S => - sample_val_delay, Y => \sample_in_buf_293[76]\); - - \loop_all_sample.14.loop_all_chanel.1.sample_in_buf[111]\ : - DFN1E1C0 - port map(D => \sample_in_buf_245[111]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[111]\); - - \chanel_more.all_chanel.3.all_bit.5.sample_out_s2[102]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[84]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[102]\); - - \loop_all_sample.2.loop_all_chanel.7.sample_in_buf[15]\ : - DFN1E1C0 - port map(D => \sample_in_buf_965[15]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[15]\); - - \loop_all_sample.14.loop_all_chanel.7.sample_in_buf_RNO[3]\ : - MX2 - port map(A => \sample_in_buf[129]\, B => sample_7(14), S - => sample_val_delay, Y => \sample_in_buf_197[3]\); - - \chanel_more.all_chanel.7.all_bit.4.sample_out_s2[31]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[13]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[31]\); - - \loop_all_sample.7.loop_all_chanel.2.sample_in_buf_RNO[100]\ : - MX2 - port map(A => \sample_in_buf[82]\, B => sample_2(7), S => - sample_val_delay, Y => \sample_in_buf_685[100]\); - - \loop_all_sample.8.loop_all_chanel.0.sample_in_buf_RNO[135]\ : - MX2 - port map(A => \sample_in_buf[117]\, B => sample_0(8), S => - sample_val_delay, Y => \sample_in_buf_637[135]\); - - \loop_all_sample.7.loop_all_chanel.5.sample_in_buf_RNO[46]\ : - MX2 - port map(A => \sample_in_buf[28]\, B => sample_5(7), S => - sample_val_delay, Y => \sample_in_buf_661[46]\); - - \loop_all_sample.7.loop_all_chanel.1.sample_in_buf[118]\ : - DFN1E1C0 - port map(D => \sample_in_buf_693[118]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[118]\); - - \chanel_more.all_chanel.5.all_bit.3.sample_out_s2[68]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[50]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[68]\); - - \loop_all_sample.11.loop_all_chanel.5.sample_in_buf_RNO[42]\ : - MX2 - port map(A => \sample_in_buf[24]\, B => sample_5(11), S => - sample_val_delay, Y => \sample_in_buf_405[42]\); - - \chanel_more.all_chanel.3.all_bit.12.sample_out_s2[95]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[77]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[95]\); - - \loop_all_sample.1.loop_all_chanel.0.sample_in_buf_RNO[142]\ : - MX2 - port map(A => \sample_in_buf[124]\, B => sample_0(1), S => - sample_val_delay, Y => \sample_in_buf_1085[142]\); - - \loop_all_sample.12.loop_all_chanel.6.sample_in_buf[23]\ : - DFN1E1C0 - port map(D => \sample_in_buf_333[23]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[23]\); - - \chanel_more.all_chanel.5.all_bit.15.sample_out_s2[56]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[38]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[56]\); - - \loop_all_sample.4.loop_all_chanel.0.sample_in_buf[139]\ : - DFN1E1C0 - port map(D => \sample_in_buf_893[139]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[139]\); - - \chanel_more.all_chanel.6.all_bit.5.sample_out_s2[48]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[30]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[48]\); - - \loop_all_sample.4.loop_all_chanel.4.sample_in_buf[67]\ : - DFN1E1C0 - port map(D => \sample_in_buf_861[67]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[67]\); - - \loop_all_sample.12.loop_all_chanel.0.sample_in_buf_RNO[131]\ : - MX2 - port map(A => \sample_in_buf[113]\, B => sample_0(12), S - => sample_val_delay, Y => \sample_in_buf_381[131]\); - - \chanel_more.all_chanel.4.all_bit.2.sample_out_s2[87]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[69]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[87]\); - - \loop_all_sample.5.loop_all_chanel.0.sample_in_buf_RNO[138]\ : - MX2 - port map(A => \sample_in_buf[120]\, B => sample_0(5), S => - sample_val_delay, Y => \sample_in_buf_829[138]\); - - \chanel_more.all_chanel.7.all_bit.5.sample_out_s2[30]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[12]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[30]\); - - \chanel_more.all_chanel.5.all_bit.14.sample_out_s2[57]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[39]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[57]\); - - \loop_all_sample.9.loop_all_chanel.5.sample_in_buf_RNO[44]\ : - MX2 - port map(A => \sample_in_buf[26]\, B => sample_5(9), S => - sample_val_delay, Y => \sample_in_buf_533[44]\); - - \chanel_more.all_chanel.3.all_bit.2.sample_out_s2[105]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[87]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[105]\); - - \loop_all_sample.5.loop_all_chanel.2.sample_in_buf[102]\ : - DFN1E1C0 - port map(D => \sample_in_buf_813[102]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[102]\); - - \chanel_HIGH.10.sample_out_s2[7]\ : DFN1E1C0 - port map(D => \sample_out_s[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[7]\); - - \chanel_more.all_chanel.6.all_bit.13.sample_out_s2[40]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[22]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[40]\); - - \chanel_more.all_chanel.5.all_bit.12.sample_out_s2[59]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[41]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[59]\); - - \loop_all_sample.14.loop_all_chanel.3.sample_in_buf[75]\ : - DFN1E1C0 - port map(D => \sample_in_buf_229[75]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[75]\); - - \loop_all_sample.14.loop_all_chanel.2.sample_in_buf_RNO[93]\ : - MX2 - port map(A => \sample_in_buf[75]\, B => sample_2(14), S => - sample_val_delay, Y => \sample_in_buf_237[93]\); - - \loop_all_sample.10.loop_all_chanel.5.sample_in_buf_RNO[43]\ : - MX2 - port map(A => \sample_in_buf[25]\, B => sample_5(10), S => - sample_val_delay, Y => \sample_in_buf_469[43]\); - - \loop_all_sample.0.loop_all_chanel.7.sample_in_buf[17]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1093[17]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[17]\); - - \loop_all_sample.6.loop_all_chanel.3.sample_in_buf_RNO[83]\ : - MX2 - port map(A => \sample_in_buf[65]\, B => sample_3(6), S => - sample_val_delay, Y => \sample_in_buf_741[83]\); - - \loop_all_sample.5.loop_all_chanel.6.sample_in_buf[30]\ : - DFN1E1C0 - port map(D => \sample_in_buf_781[30]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[30]\); - - \loop_all_sample.13.loop_all_chanel.0.sample_in_buf[130]\ : - DFN1E1C0 - port map(D => \sample_in_buf_317[130]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[130]\); - - \loop_all_sample.10.loop_all_chanel.7.sample_in_buf[7]\ : - DFN1E1C0 - port map(D => \sample_in_buf_453[7]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[7]\); - - \loop_all_sample.0.loop_all_chanel.0.sample_in_buf_RNO[143]\ : - MX2 - port map(A => \sample_in_buf[125]\, B => sample_0(0), S => - sample_val_delay, Y => \sample_in_buf_1149[143]\); - - \chanel_more.all_chanel.4.all_bit.12.sample_out_s2[77]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[59]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[77]\); - - \loop_all_sample.2.loop_all_chanel.6.sample_in_buf_RNO[33]\ : - MX2 - port map(A => \sample_in_buf[15]\, B => sample_6(2), S => - sample_val_delay, Y => \sample_in_buf_973[33]\); - - \chanel_more.all_chanel.5.all_bit.5.sample_out_s2[66]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[48]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[66]\); - - \loop_all_sample.6.loop_all_chanel.1.sample_in_buf[119]\ : - DFN1E1C0 - port map(D => \sample_in_buf_757[119]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[119]\); - - \loop_all_sample.0.loop_all_chanel.5.sample_in_buf[53]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1109[53]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[53]\); - - \loop_all_sample.17.loop_all_chanel.6.sample_in_buf_RNO[18]\ : - MX2 - port map(A => \sample_in_buf[0]\, B => sample_6(15), S => - sample_val_delay, Y => \sample_in_buf_13[18]\); - - \chanel_more.all_chanel.6.all_bit.4.sample_out_s2[49]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[31]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[49]\); - - \chanel_more.all_chanel.5.all_bit.1.sample_out_s2[70]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[52]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[70]\); - - \loop_all_sample.17.loop_all_chanel.7.sample_in_buf[0]\ : - DFN1E1C0 - port map(D => \sample_in_buf_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[0]\); - - \chanel_more.all_chanel.1.all_bit.14.sample_out_s2[129]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[111]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_127); - - \loop_all_sample.5.loop_all_chanel.1.sample_in_buf_RNO[120]\ : - MX2 - port map(A => \sample_in_buf[102]\, B => sample_1(5), S => - sample_val_delay, Y => \sample_in_buf_821[120]\); - - \loop_all_sample.0.loop_all_chanel.7.sample_in_buf_RNO[17]\ : - MX2 - port map(A => \sample_in_buf[143]\, B => sample_7(0), S => - sample_val_delay, Y => \sample_in_buf_1093[17]\); - - \loop_all_sample.12.loop_all_chanel.7.sample_in_buf[5]\ : - DFN1E1C0 - port map(D => \sample_in_buf_325[5]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[5]\); - - \chanel_more.all_chanel.3.all_bit.8.sample_out_s2[99]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[81]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[99]\); - - \chanel_more.all_chanel.4.all_bit.7.sample_out_s2[82]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[64]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[82]\); - - \loop_all_sample.10.loop_all_chanel.0.sample_in_buf[133]\ : - DFN1E1C0 - port map(D => \sample_in_buf_509[133]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[133]\); - - \loop_all_sample.3.loop_all_chanel.7.sample_in_buf[14]\ : - DFN1E1C0 - port map(D => \sample_in_buf_901[14]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[14]\); - - \chanel_HIGH.8.sample_out_s2[9]\ : DFN1E1C0 - port map(D => \sample_out_s[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[9]\); - - \chanel_more.all_chanel.5.all_bit.2.sample_out_s2[69]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[51]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[69]\); - - \chanel_more.all_chanel.1.all_bit.0.sample_out_s2[143]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[125]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_141); - - \chanel_more.all_chanel.1.all_bit.12.sample_out_s2[131]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[113]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_129); - - \chanel_HIGH.3.sample_out_s2[14]\ : DFN1E1C0 - port map(D => \sample_out_s[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[14]\); - - \chanel_more.all_chanel.7.all_bit.12.sample_out_s2[23]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[5]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[23]\); - - \loop_all_sample.8.loop_all_chanel.1.sample_in_buf_RNO[117]\ : - MX2 - port map(A => \sample_in_buf[99]\, B => sample_1(8), S => - sample_val_delay, Y => \sample_in_buf_629[117]\); - - \loop_all_sample.10.loop_all_chanel.0.sample_in_buf_RNO[133]\ : - MX2 - port map(A => \sample_in_buf[115]\, B => sample_0(10), S - => sample_val_delay, Y => \sample_in_buf_509[133]\); - - \loop_all_sample.11.loop_all_chanel.3.sample_in_buf[78]\ : - DFN1E1C0 - port map(D => \sample_in_buf_421[78]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[78]\); - - \chanel_HIGH.11.sample_out_s2[6]\ : DFN1E1C0 - port map(D => \sample_out_s[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[6]\); - - \loop_all_sample.10.loop_all_chanel.3.sample_in_buf_RNO[79]\ : - MX2 - port map(A => \sample_in_buf[61]\, B => sample_3(10), S => - sample_val_delay, Y => \sample_in_buf_485[79]\); - - \chanel_more.all_chanel.1.all_bit.11.sample_out_s2[132]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[114]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_130); - - \chanel_more.all_chanel.1.all_bit.10.sample_out_s2[133]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[115]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_131); - - \loop_all_sample.13.loop_all_chanel.1.sample_in_buf_RNO[112]\ : - MX2 - port map(A => \sample_in_buf[94]\, B => sample_1(13), S => - sample_val_delay, Y => \sample_in_buf_309[112]\); - - \loop_all_sample.6.loop_all_chanel.3.sample_in_buf[83]\ : - DFN1E1C0 - port map(D => \sample_in_buf_741[83]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[83]\); - - \loop_all_sample.2.loop_all_chanel.3.sample_in_buf_RNO[87]\ : - MX2 - port map(A => \sample_in_buf[69]\, B => sample_3(2), S => - sample_val_delay, Y => \sample_in_buf_997[87]\); - - \loop_all_sample.1.loop_all_chanel.5.sample_in_buf[52]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1045[52]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[52]\); - - \chanel_more.all_chanel.7.all_bit.0.sample_out_s2[35]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[17]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[35]\); - - \chanel_more.all_chanel.4.all_bit.14.sample_out_s2[75]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[57]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[75]\); - - \chanel_more.all_chanel.2.all_bit.4.sample_out_s2[121]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[103]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[121]\); - - \chanel_more.all_chanel.2.all_bit.12.sample_out_s2[113]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[95]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[113]\); - - \chanel_more.all_chanel.1.all_bit.7.sample_out_s2[136]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[118]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_134); - - \chanel_more.all_chanel.1.all_bit.2.sample_out_s2[141]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[123]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_139); - - \loop_all_sample.6.loop_all_chanel.2.sample_in_buf_RNO[101]\ : - MX2 - port map(A => \sample_in_buf[83]\, B => sample_2(6), S => - sample_val_delay, Y => \sample_in_buf_749[101]\); - - \chanel_more.all_chanel.5.all_bit.11.sample_out_s2[60]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[42]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[60]\); - - \loop_all_sample.1.loop_all_chanel.1.sample_in_buf_RNO[124]\ : - MX2 - port map(A => \sample_in_buf[106]\, B => sample_1(1), S => - sample_val_delay, Y => \sample_in_buf_1077[124]\); - - IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL - port map(alu_ctrl(2) => \alu_ctrl[2]\, alu_ctrl(1) => - \alu_ctrl[1]\, alu_ctrl(0) => \alu_ctrl[0]\, - ram_sel_Wdata(1) => \ram_sel_Wdata[1]\, ram_sel_Wdata(0) - => \ram_sel_Wdata[0]\, waddr_previous(1) => - \waddr_previous[1]\, waddr_previous(0) => - \waddr_previous[0]\, in_sel_src(1) => \in_sel_src[1]\, - in_sel_src(0) => \in_sel_src[0]\, S_i_0(33) => - \S_i_0[33]\, S(8) => \S[8]\, alu_sel_coeff(4) => - \alu_sel_coeff[4]\, alu_sel_coeff(3) => - \alu_sel_coeff[3]\, alu_sel_coeff(2) => - \alu_sel_coeff[2]\, alu_sel_coeff(1) => - \alu_sel_coeff[1]\, alu_sel_coeff(0) => - \alu_sel_coeff[0]\, alu_sel_coeff_0_2 => - \alu_sel_coeff_0[2]\, alu_sel_coeff_0_0 => - \alu_sel_coeff_0[0]\, sample_out_rot_s => - sample_out_rot_s, sample_out_val_s => sample_out_val_s, - raddr_rst => raddr_rst, alu_sel_input => alu_sel_input, - raddr_add1 => raddr_add1, sample_val_delay => - sample_val_delay, ram_write => ram_write, ram_write_i => - ram_write_i, un1_sample_in_rotate => un1_sample_in_rotate, - sample_out_rot_s_0 => sample_out_rot_s_0, - sample_out_rot_s_1 => sample_out_rot_s_1, - sample_out_rot_s_2 => sample_out_rot_s_2, - sample_out_rot_s_3 => sample_out_rot_s_3, - sample_out_rot_s_4 => sample_out_rot_s_4, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \loop_all_sample.7.loop_all_chanel.3.sample_in_buf_RNO[82]\ : - MX2 - port map(A => \sample_in_buf[64]\, B => sample_3(7), S => - sample_val_delay, Y => \sample_in_buf_677[82]\); - - \chanel_more.all_chanel.7.all_bit.8.sample_out_s2[27]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[9]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[27]\); - - \chanel_more.all_chanel.6.all_bit.7.sample_out_s2[46]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[28]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[46]\); - - \loop_all_sample.7.loop_all_chanel.3.sample_in_buf[82]\ : - DFN1E1C0 - port map(D => \sample_in_buf_677[82]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[82]\); - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf[126]\ : - DFN1E1C0 - port map(D => \sample_in_buf_61[126]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[128]\); - - \loop_all_sample.11.loop_all_chanel.4.sample_in_buf[60]\ : - DFN1E1C0 - port map(D => \sample_in_buf_413[60]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[60]\); - - \loop_all_sample.3.loop_all_chanel.6.sample_in_buf_RNO[32]\ : - MX2 - port map(A => \sample_in_buf[14]\, B => sample_6(3), S => - sample_val_delay, Y => \sample_in_buf_909[32]\); - - \loop_all_sample.17.loop_all_chanel.1.sample_in_buf_RNO[108]\ : - MX2 - port map(A => \sample_in_buf[90]\, B => sample_1(15), S => - sample_val_delay, Y => \sample_in_buf_53[108]\); - - \loop_all_sample.8.loop_all_chanel.6.sample_in_buf_RNO[27]\ : - MX2 - port map(A => \sample_in_buf[9]\, B => sample_6(8), S => - sample_val_delay, Y => \sample_in_buf_589[27]\); - - \loop_all_sample.5.loop_all_chanel.4.sample_in_buf[66]\ : - DFN1E1C0 - port map(D => \sample_in_buf_797[66]\, CLK => HCLK_c, CLR - => HRESETn_c, E => un1_sample_in_rotate, Q => - \sample_in_buf[66]\); - - \loop_all_sample.14.loop_all_chanel.1.sample_in_buf_RNO[111]\ : - MX2 - port map(A => \sample_in_buf[93]\, B => sample_1(14), S => - sample_val_delay, Y => \sample_in_buf_245[111]\); - - \chanel_more.all_chanel.2.all_bit.8.sample_out_s2[117]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[99]\, CLK => HCLK_c, - CLR => HRESETn_c, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[117]\); - - \chanel_more.all_chanel.7.all_bit.11.sample_out_s2[24]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[6]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sample_out_rot_s, Q => - \sample_filter_v2_out[24]\); - - \loop_all_sample.8.loop_all_chanel.2.sample_in_buf_RNO[99]\ : - MX2 - port map(A => \sample_in_buf[81]\, B => sample_2(8), S => - sample_val_delay, Y => \sample_in_buf_621[99]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_6_16_256 is - - port( sample_f1 : in std_logic_vector(111 downto 80); - sample_f1_wdata_95 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_0 : in std_logic; - sample_f3_wdata : out std_logic_vector(95 downto 0); - sample_f1_val : in std_logic; - HCLK_c : in std_logic; - sample_f3_val : out std_logic; - HRESETn_c : in std_logic; - sample_f1_val_0 : in std_logic - ); - -end Downsampling_6_16_256; - -architecture DEF_ARCH of Downsampling_6_16_256 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un2_sample_in_val_0, un2_sample_in_val_23, - un2_sample_in_val_22, un2_sample_in_val_24, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1, - sample_out_0_sqmuxa_0, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un2_sample_in_val_15, - un2_sample_in_val_14, un2_sample_in_val_20, - un2_sample_in_val_9, un2_sample_in_val_8, - un2_sample_in_val_19, un2_sample_in_val_5, - un2_sample_in_val_4, un2_sample_in_val_17, - un2_sample_in_val_13, \counter[24]_net_1\, - un2_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un2_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un2_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un2_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un2_sample_in_val, - sample_out_0_sqmuxa, \counter_4[8]\, I_45_2, - \counter_4[9]\, I_52_2, \counter_4[10]\, I_56_2, - \counter_4[11]\, I_66_2, \counter_4[12]\, I_73_2, - \counter_4[13]\, I_77_2, \counter_4[14]\, I_84_2, - \counter_4[15]\, I_91_2, \counter_4[16]\, I_98_2, - \counter_4[17]\, I_105_2, \counter_4[18]\, I_115_2, - \counter_4[19]\, I_122_2, \counter_4[20]\, I_129_2, - \counter_4[21]\, I_136_2, \counter_4[22]\, I_143_2, - \counter_4[23]\, I_156_2, \counter_4[24]\, I_166_2, - \counter_4[25]\, I_173_2, \counter_4[26]\, I_186_2, - \counter_4[27]\, I_196_2, sample_out_val_4, I_4_2, I_5_2, - I_9_2, I_13_2, I_20_2, I_24_2, I_31_3, I_38_2, N_4, - \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[19]_net_1\); - - \counter_RNI8DTE[12]\ : NOR3C - port map(A => un2_sample_in_val_9, B => un2_sample_in_val_8, - C => un2_sample_in_val_19, Y => un2_sample_in_val_23); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f1_wdata_73, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(73)); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f1_wdata_75, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(75)); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f1_wdata_82, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(82)); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f1_wdata_94, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(94)); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f1_wdata_76, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(76)); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f1(93), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(34)); - - \sample_out[66]\ : DFN1E1 - port map(D => sample_f1(98), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(29)); - - \sample_out[73]\ : DFN1E1 - port map(D => sample_f1(105), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(22)); - - \sample_out[79]\ : DFN1E1 - port map(D => sample_f1(111), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(16)); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f1_wdata_57, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(57)); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f1_wdata_0, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(0)); - - \counter_RNO[11]\ : NOR2B - port map(A => I_66_2, B => un2_sample_in_val_0, Y => - \counter_4[11]\); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f1_wdata_61, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(61)); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_2); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_2); - - \counter_RNO[15]\ : NOR2B - port map(A => I_91_2, B => un2_sample_in_val_0, Y => - \counter_4[15]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f1(83), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(44)); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f1(88), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(39)); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f1_wdata_95, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(95)); - - \counter[6]\ : DFN1E1C0 - port map(D => I_31_3, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_2); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f1_wdata_14, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(14)); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f1_wdata_9, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(9)); - - \counter[3]\ : DFN1E1C0 - port map(D => I_13_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_2, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f1_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_2); - - \counter_RNO[8]\ : NOR2B - port map(A => I_45_2, B => un2_sample_in_val_0, Y => - \counter_4[8]\); - - \counter_RNO[13]\ : NOR2B - port map(A => I_77_2, B => un2_sample_in_val_0, Y => - \counter_4[13]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_2); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f1_wdata_83, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(83)); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f1_wdata_85, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(85)); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f1_wdata_50, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(50)); - - \counter_RNO[12]\ : NOR2B - port map(A => I_73_2, B => un2_sample_in_val_0, Y => - \counter_4[12]\); - - \sample_out[72]\ : DFN1E1 - port map(D => sample_f1(104), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(23)); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f1_wdata_62, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(62)); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f1_wdata_56, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(56)); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[17]_net_1\); - - \sample_out[70]\ : DFN1E1 - port map(D => sample_f1(102), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(25)); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => I_20_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_2); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f1_wdata_90, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(90)); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f1_wdata_48, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(48)); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \counter_RNIPKE[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un2_sample_in_val_5); - - \sample_out[65]\ : DFN1E1 - port map(D => sample_f1(97), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(30)); - - \counter_RNIBJN3[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un2_sample_in_val_3); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f1_wdata_74, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(74)); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f1_wdata_69, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(69)); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f1_wdata_93, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(93)); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[27]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[27]_net_1\); - - \counter_RNI2SB8[10]\ : NOR3C - port map(A => un2_sample_in_val_5, B => un2_sample_in_val_4, - C => un2_sample_in_val_17, Y => un2_sample_in_val_22); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \sample_out[67]\ : DFN1E1 - port map(D => sample_f1(99), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(28)); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f1_wdata_1, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(1)); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_2); - - \counter_RNO[17]\ : NOR2B - port map(A => I_105_2, B => un2_sample_in_val, Y => - \counter_4[17]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f1(87), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(40)); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \counter_RNIH507[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un2_sample_in_val_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_2); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f1_wdata_63, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(63)); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_2); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f1(89), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(38)); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f1_wdata_65, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(65)); - - \counter_RNO[14]\ : NOR2B - port map(A => I_84_2, B => un2_sample_in_val_0, Y => - \counter_4[14]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f1_wdata_10, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(10)); - - \counter_RNIO507[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un2_sample_in_val_8); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_2, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f1_val, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => I_186_2, B => un2_sample_in_val, Y => - \counter_4[26]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f1_wdata_91, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(91)); - - \counter_RNI0MBF1_2[10]\ : NOR3B - port map(A => sample_f1_val_0, B => HRESETn_c, C => - un2_sample_in_val_0, Y => sample_out_0_sqmuxa_1); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[25]_net_1\); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_4, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f3_val); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f1_wdata_8, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(8)); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_2); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_2); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f1(80), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(47)); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_2); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f1_wdata_2, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(2)); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f1_wdata_84, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(84)); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f1_wdata_79, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(79)); - - \counter[5]\ : DFN1E1C0 - port map(D => I_24_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f1_wdata_51, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(51)); - - \sample_out[71]\ : DFN1E1 - port map(D => sample_f1(103), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(24)); - - \sample_out[76]\ : DFN1E1 - port map(D => sample_f1(108), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(19)); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : NOR2B - port map(A => I_56_2, B => un2_sample_in_val_0, Y => - \counter_4[10]\); - - \counter_RNIRSE[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un2_sample_in_val_1); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_2); - - \counter_RNO[21]\ : NOR2B - port map(A => I_136_2, B => un2_sample_in_val, Y => - \counter_4[21]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_2); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[68]\ : DFN1E1 - port map(D => sample_f1(100), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(27)); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f1_wdata_70, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(70)); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_2); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => I_173_2, B => un2_sample_in_val, Y => - \counter_4[25]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - \sample_out[64]\ : DFN1E1 - port map(D => sample_f1(96), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(31)); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_3); - - \counter_RNIH1T[12]\ : NOR3A - port map(A => un2_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un2_sample_in_val_19); - - \counter_RNI0G54[20]\ : NOR3A - port map(A => un2_sample_in_val_3, B => \counter[23]_net_1\, - C => \counter[20]_net_1\, Y => un2_sample_in_val_15); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_2); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f1_wdata_68, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(68)); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - \counter_RNI6RM3[10]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un2_sample_in_val_4); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_2); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f1(90), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(37)); - - \counter_RNI7FN3[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un2_sample_in_val_7); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[26]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_2); - - \counter_RNO[23]\ : NOR2B - port map(A => I_156_2, B => un2_sample_in_val, Y => - \counter_4[23]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f1(86), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(41)); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f1_wdata_52, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(52)); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f1(81), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(46)); - - \counter_RNI0MBF1_0[10]\ : NOR3B - port map(A => sample_f1_val_0, B => HRESETn_c, C => - un2_sample_in_val_0, Y => sample_out_0_sqmuxa_0); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_2); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_2); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f1_wdata_3, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(3)); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val_0, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_2); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f1_wdata_7, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(7)); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f1_wdata_5, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(5)); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_2); - - \counter_RNO[22]\ : NOR2B - port map(A => I_143_2, B => un2_sample_in_val, Y => - \counter_4[22]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f1_wdata_64, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(64)); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f1_wdata_59, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(59)); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f1_wdata_11, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(11)); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f1(95), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(32)); - - \sample_out[69]\ : DFN1E1 - port map(D => sample_f1(101), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(26)); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f1_wdata_80, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(80)); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_2); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[75]\ : DFN1E1 - port map(D => sample_f1(107), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(20)); - - \counter_RNIMGNA[24]\ : NOR3A - port map(A => un2_sample_in_val_13, B => \counter[1]_net_1\, - C => \counter[24]_net_1\, Y => un2_sample_in_val_20); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \counter_RNIKN371[10]\ : OR3C - port map(A => un2_sample_in_val_23, B => - un2_sample_in_val_22, C => un2_sample_in_val_24, Y => - un2_sample_in_val_0); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_2); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f1_wdata_78, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(78)); - - \counter_RNO[18]\ : NOR2B - port map(A => I_115_2, B => un2_sample_in_val, Y => - \counter_4[18]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[77]\ : DFN1E1 - port map(D => sample_f1(109), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(18)); - - \counter_RNI0MBF1[10]\ : NOR3B - port map(A => sample_f1_val_0, B => HRESETn_c, C => - un2_sample_in_val_0, Y => sample_out_0_sqmuxa); - - sample_out_val_RNO : NOR2A - port map(A => sample_f1_val_0, B => un2_sample_in_val, Y - => sample_out_val_4); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f1(85), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(42)); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f1_wdata_67, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(67)); - - \counter_RNO[27]\ : NOR2B - port map(A => I_196_2, B => un2_sample_in_val, Y => - \counter_4[27]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f1(91), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(36)); - - \counter_RNI0MBF1_1[10]\ : NOR3B - port map(A => sample_f1_val_0, B => HRESETn_c, C => - un2_sample_in_val_0, Y => sample_out_0_sqmuxa_2); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f1_wdata_71, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(71)); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f1_wdata_53, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(53)); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f1_wdata_55, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(55)); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f1_wdata_12, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(12)); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f1_wdata_6, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(6)); - - \counter_RNIV507[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un2_sample_in_val_9); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => I_166_2, B => un2_sample_in_val, Y => - \counter_4[24]\); - - \counter[7]\ : DFN1E1C0 - port map(D => I_38_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f1_val, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_2); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f1_wdata_89, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(89)); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f1(94), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(33)); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f1(92), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(35)); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f1_wdata_60, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(60)); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f1_wdata_4, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(4)); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - \counter_RNIAEQF[20]\ : NOR3C - port map(A => un2_sample_in_val_15, B => - un2_sample_in_val_14, C => un2_sample_in_val_20, Y => - un2_sample_in_val_24); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : NOR2B - port map(A => I_129_2, B => un2_sample_in_val, Y => - \counter_4[20]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f1_wdata_58, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(58)); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f1_wdata_72, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(72)); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f1(84), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(43)); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f1_wdata_66, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(66)); - - \counter_RNI3C64[22]\ : NOR3A - port map(A => un2_sample_in_val_7, B => \counter[22]_net_1\, - C => \counter[19]_net_1\, Y => un2_sample_in_val_17); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f1(82), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(45)); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f1_wdata_77, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(77)); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f1_wdata_86, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(86)); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f1_wdata_88, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(88)); - - \sample_out[78]\ : DFN1E1 - port map(D => sample_f1(110), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(17)); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f1_wdata_81, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(81)); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f1_wdata_13, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(13)); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[9]_net_1\); - - \sample_out[74]\ : DFN1E1 - port map(D => sample_f1(106), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(21)); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f1_wdata_15, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(15)); - - \counter_RNIKN371_0[10]\ : OR3C - port map(A => un2_sample_in_val_23, B => - un2_sample_in_val_22, C => un2_sample_in_val_24, Y => - un2_sample_in_val); - - \counter_RNO[19]\ : NOR2B - port map(A => I_122_2, B => un2_sample_in_val, Y => - \counter_4[19]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : NOR2B - port map(A => I_52_2, B => un2_sample_in_val_0, Y => - \counter_4[9]\); - - \counter_RNIQKE[21]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un2_sample_in_val_11); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_2); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_2); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f1_val, Q => \counter[18]_net_1\); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f1_wdata_87, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(87)); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f1_wdata_54, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(54)); - - \counter_RNO[16]\ : NOR2B - port map(A => I_98_2, B => un2_sample_in_val_0, Y => - \counter_4[16]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_2, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f1_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f1_wdata_49, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(49)); - - \counter_RNIKDT[27]\ : NOR3A - port map(A => un2_sample_in_val_1, B => \counter[11]_net_1\, - C => \counter[27]_net_1\, Y => un2_sample_in_val_14); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f1_wdata_92, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(92)); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_6_16_96 is - - port( sample_f0 : in std_logic_vector(111 downto 80); - sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f2_wdata : out std_logic_vector(95 downto 0); - sample_f0_val : in std_logic; - sample_f0_val_1 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_f2_val : out std_logic; - sample_f0_val_0 : in std_logic; - sample_out_0_sqmuxa_1 : in std_logic - ); - -end Downsampling_6_16_96; - -architecture DEF_ARCH of Downsampling_6_16_96 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - signal un6_sample_in_val_24_0, un6_sample_in_val_15, - un6_sample_in_val_14, un6_sample_in_val_20, - un6_sample_in_val_25_0, un6_sample_in_val_17, - un6_sample_in_val_16, un6_sample_in_val_23, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1_0, - sample_out_0_sqmuxa_0, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un6_sample_in_val_25, - un6_sample_in_val_24, un6_sample_in_val_9, - un6_sample_in_val_8, un6_sample_in_val_19, - un6_sample_in_val_13, \counter[24]_net_1\, - un6_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un6_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un6_sample_in_val_5, \counter[10]_net_1\, - \counter[7]_net_1\, un6_sample_in_val_3, - \counter[23]_net_1\, \counter[20]_net_1\, - un6_sample_in_val_1, \counter[11]_net_1\, - \counter[27]_net_1\, \counter[18]_net_1\, - \counter[21]_net_1\, \counter[9]_net_1\, - \counter[4]_net_1\, \counter[6]_net_1\, - \counter[25]_net_1\, \counter[2]_net_1\, - \counter[13]_net_1\, \counter[16]_net_1\, - \counter[26]_net_1\, \counter[5]_net_1\, - \counter[14]_net_1\, \counter[17]_net_1\, - sample_out_val_9, \counter_4[5]\, I_24_1, \counter_4[7]\, - I_38_1, \counter_4[8]\, I_45_1, \counter_4[9]\, I_52_1, - \counter_4[10]\, I_56_1, \counter_4[11]\, I_66_1, - \counter_4[12]\, I_73_1, \counter_4[13]\, I_77_1, - \counter_4[14]\, I_84_1, \counter_4[15]\, I_91_1, - \counter_4[16]\, I_98_1, \counter_4[17]\, I_105_1, - \counter_4[18]\, I_115_1, \counter_4[19]\, I_122_1, - \counter_4[20]\, I_129_1, \counter_4[21]\, I_136_1, - \counter_4[22]\, I_143_1, \counter_4[23]\, I_156_1, - \counter_4[24]\, I_166_1, \counter_4[25]\, I_173_1, - \counter_4[26]\, I_186_1, \counter_4[27]\, I_196_1, - sample_out_0_sqmuxa, I_4_1, I_5_1, I_9_1, I_13_1, I_20_1, - I_31_2, N_4, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[19]_net_1\); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f0_wdata_73, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(73)); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f0_wdata_75, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(75)); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f0_wdata_82, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(82)); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f0_wdata_94, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(94)); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f0_wdata_76, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(76)); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f0(93), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(34)); - - \sample_out[66]\ : DFN1E1 - port map(D => sample_f0(98), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(29)); - - \sample_out[73]\ : DFN1E1 - port map(D => sample_f0(105), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(22)); - - \sample_out[79]\ : DFN1E1 - port map(D => sample_f0(111), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(16)); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f0_wdata_57, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(57)); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f0_wdata_0, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(0)); - - \counter_RNO[11]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_66_1, Y => \counter_4[11]\); - - \counter_RNISF54[20]\ : NOR3A - port map(A => un6_sample_in_val_3, B => \counter[23]_net_1\, - C => \counter[20]_net_1\, Y => un6_sample_in_val_15); - - \counter_RNID1T[12]\ : NOR3A - port map(A => un6_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un6_sample_in_val_19); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f0_wdata_61, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(61)); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_1); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_1); - - \counter_RNO[15]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_91_1, Y => \counter_4[15]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f0(83), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(44)); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f0(88), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(39)); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f0_wdata_95, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(95)); - - \counter_RNO[7]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_38_1, Y => \counter_4[7]\); - - \counter[6]\ : DFN1E1C0 - port map(D => I_31_2, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f0_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter_RNIPSE[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un6_sample_in_val_1); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_1); - - \counter_RNIF507[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un6_sample_in_val_13); - - \counter_RNI3LBF1_1[10]\ : NOR3C - port map(A => un6_sample_in_val_24_0, B => - un6_sample_in_val_25_0, C => sample_out_0_sqmuxa_1, Y => - sample_out_0_sqmuxa_2); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f0_wdata_14, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(14)); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f0_wdata_9, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(9)); - - \counter_RNIOKE[21]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un6_sample_in_val_11); - - \counter[3]\ : DFN1E1C0 - port map(D => I_13_1, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f0_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_1, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_1); - - \counter_RNO[8]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_45_1, Y => \counter_4[8]\); - - \counter_RNIUDQF[20]\ : NOR3C - port map(A => un6_sample_in_val_15, B => - un6_sample_in_val_14, C => un6_sample_in_val_20, Y => - un6_sample_in_val_24_0); - - \counter_RNO[13]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_77_1, Y => \counter_4[13]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_1); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f0_wdata_83, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(83)); - - \counter_RNIQ89N[10]\ : NOR3C - port map(A => un6_sample_in_val_17, B => - un6_sample_in_val_16, C => un6_sample_in_val_23, Y => - un6_sample_in_val_25_0); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f0_wdata_85, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(85)); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f0_wdata_50, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(50)); - - \counter_RNO[12]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_73_1, Y => \counter_4[12]\); - - \counter_RNIT507[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un6_sample_in_val_9); - - \sample_out[72]\ : DFN1E1 - port map(D => sample_f0(104), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(23)); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f0_wdata_62, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(62)); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f0_wdata_56, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(56)); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[17]_net_1\); - - \sample_out[70]\ : DFN1E1 - port map(D => sample_f0(102), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(25)); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => I_20_1, CLK => HCLK_c, CLR => HRESETn_c, E - => sample_f0_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_1); - - \counter_RNIGDT[27]\ : NOR3A - port map(A => un6_sample_in_val_1, B => \counter[11]_net_1\, - C => \counter[27]_net_1\, Y => un6_sample_in_val_14); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f0_wdata_90, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(90)); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f0_wdata_48, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(48)); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \sample_out[65]\ : DFN1E1 - port map(D => sample_f0(97), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(30)); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f0_wdata_74, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(74)); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f0_wdata_69, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(69)); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f0_wdata_93, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(93)); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[27]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[27]_net_1\); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \sample_out[67]\ : DFN1E1 - port map(D => sample_f0(99), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(28)); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f0_wdata_1, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(1)); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_1); - - \counter_RNO[17]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_105_1, Y => \counter_4[17]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f0(87), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(40)); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_1); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f0_wdata_63, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(63)); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_1); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f0(89), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(38)); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f0_wdata_65, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(65)); - - \counter_RNO[14]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_84_1, Y => \counter_4[14]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f0_wdata_10, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(10)); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_1, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_186_1, Y => \counter_4[26]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f0_wdata_91, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(91)); - - \counter_RNO[5]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_24_1, Y => \counter_4[5]\); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[25]_net_1\); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_9, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f2_val); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f0_wdata_8, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(8)); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_1); - - \counter_RNIUDQF_0[20]\ : NOR3C - port map(A => un6_sample_in_val_15, B => - un6_sample_in_val_14, C => un6_sample_in_val_20, Y => - un6_sample_in_val_24); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_1); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f0(80), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(47)); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_1); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f0_wdata_2, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(2)); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f0_wdata_84, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(84)); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f0_wdata_79, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(79)); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f0_wdata_51, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(51)); - - \sample_out[71]\ : DFN1E1 - port map(D => sample_f0(103), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(24)); - - \counter_RNI0DTE[12]\ : NOR3C - port map(A => un6_sample_in_val_9, B => un6_sample_in_val_8, - C => un6_sample_in_val_19, Y => un6_sample_in_val_23); - - \sample_out[76]\ : DFN1E1 - port map(D => sample_f0(108), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(19)); - - \counter_RNI3LBF1_0[10]\ : NOR3C - port map(A => un6_sample_in_val_24_0, B => - un6_sample_in_val_25_0, C => sample_out_0_sqmuxa_1, Y => - sample_out_0_sqmuxa_0); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_56_1, Y => \counter_4[10]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_1); - - \counter_RNO[21]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_136_1, Y => \counter_4[21]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_1); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[68]\ : DFN1E1 - port map(D => sample_f0(100), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(27)); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f0_wdata_70, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(70)); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_1); - - \counter_RNIM507[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un6_sample_in_val_8); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_173_1, Y => \counter_4[25]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - \sample_out[64]\ : DFN1E1 - port map(D => sample_f0(96), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(31)); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_2); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_1); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f0_wdata_68, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(68)); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNI3LBF1_2[10]\ : NOR3C - port map(A => un6_sample_in_val_24_0, B => - un6_sample_in_val_25_0, C => sample_out_0_sqmuxa_1, Y => - sample_out_0_sqmuxa_1_0); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_1); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - \counter_RNIRF54[10]\ : NOR3A - port map(A => un6_sample_in_val_5, B => \counter[10]_net_1\, - C => \counter[7]_net_1\, Y => un6_sample_in_val_16); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f0(90), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(37)); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[26]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_1); - - \counter_RNO[23]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_156_1, Y => \counter_4[23]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f0(86), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(41)); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f0_wdata_52, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(52)); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f0(81), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(46)); - - \counter_RNI3LBF1[10]\ : NOR3C - port map(A => un6_sample_in_val_24, B => - un6_sample_in_val_25, C => sample_out_0_sqmuxa_1, Y => - sample_out_0_sqmuxa); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_1); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_1); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f0_wdata_3, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(3)); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_1); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f0_wdata_7, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(7)); - - \counter_RNIVB64[22]\ : NOR3A - port map(A => un6_sample_in_val_7, B => \counter[22]_net_1\, - C => \counter[19]_net_1\, Y => un6_sample_in_val_17); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f0_wdata_5, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(5)); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_1); - - \counter_RNO[22]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_143_1, Y => \counter_4[22]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f0_wdata_64, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(64)); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f0_wdata_59, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(59)); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f0_wdata_11, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(11)); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f0(95), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(32)); - - \sample_out[69]\ : DFN1E1 - port map(D => sample_f0(101), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(26)); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f0_wdata_80, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(80)); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_1); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[75]\ : DFN1E1 - port map(D => sample_f0(107), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(20)); - - \counter_RNIIGNA[24]\ : NOR3A - port map(A => un6_sample_in_val_13, B => \counter[1]_net_1\, - C => \counter[24]_net_1\, Y => un6_sample_in_val_20); - - \counter_RNI9JN3[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un6_sample_in_val_3); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \counter_RNIQ89N_0[10]\ : NOR3C - port map(A => un6_sample_in_val_17, B => - un6_sample_in_val_16, C => un6_sample_in_val_23, Y => - un6_sample_in_val_25); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_1); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f0_wdata_78, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(78)); - - \counter_RNO[18]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_115_1, Y => \counter_4[18]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[77]\ : DFN1E1 - port map(D => sample_f0(109), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(18)); - - sample_out_val_RNO : NOR3C - port map(A => un6_sample_in_val_24_0, B => - un6_sample_in_val_25_0, C => sample_f0_val_0, Y => - sample_out_val_9); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f0(85), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(42)); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f0_wdata_67, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(67)); - - \counter_RNO[27]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_196_1, Y => \counter_4[27]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f0(91), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(36)); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f0_wdata_71, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(71)); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f0_wdata_53, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(53)); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f0_wdata_55, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(55)); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f0_wdata_12, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(12)); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f0_wdata_6, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(6)); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_166_1, Y => \counter_4[24]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_1); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f0_wdata_89, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(89)); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f0(94), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(33)); - - \counter_RNINKE[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un6_sample_in_val_5); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f0(92), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(35)); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f0_wdata_60, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(60)); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f0_wdata_4, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(4)); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_129_1, Y => \counter_4[20]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f0_wdata_58, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(58)); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f0_wdata_72, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(72)); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f0(84), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(43)); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f0_wdata_66, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(66)); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f0(82), CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(45)); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f0_wdata_77, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(77)); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f0_wdata_86, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(86)); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f0_wdata_88, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(88)); - - \sample_out[78]\ : DFN1E1 - port map(D => sample_f0(110), CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(17)); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f0_wdata_81, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(81)); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f0_wdata_13, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(13)); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[9]_net_1\); - - \sample_out[74]\ : DFN1E1 - port map(D => sample_f0(106), CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(21)); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f0_wdata_15, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(15)); - - \counter_RNO[19]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_122_1, Y => \counter_4[19]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : AOI1B - port map(A => un6_sample_in_val_25_0, B => - un6_sample_in_val_24_0, C => I_52_1, Y => \counter_4[9]\); - - \counter_RNI5FN3[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un6_sample_in_val_7); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_1); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_1); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val, Q => \counter[18]_net_1\); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f0_wdata_87, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(87)); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f0_wdata_54, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(54)); - - \counter_RNO[16]\ : AOI1B - port map(A => un6_sample_in_val_25, B => - un6_sample_in_val_24, C => I_98_1, Y => \counter_4[16]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_1, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val_1, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f0_wdata_49, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(49)); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f0_wdata_92, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f2_wdata(92)); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 is - - port( sample_f1_wdata_95 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_0 : in std_logic; - data_f1_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0); - sample_f1_37 : in std_logic; - sample_f1_5 : in std_logic; - sample_f1_38 : in std_logic; - sample_f1_6 : in std_logic; - sample_f1_39 : in std_logic; - sample_f1_7 : in std_logic; - sample_f1_40 : in std_logic; - sample_f1_8 : in std_logic; - sample_f1_41 : in std_logic; - sample_f1_9 : in std_logic; - sample_f1_42 : in std_logic; - sample_f1_10 : in std_logic; - sample_f1_43 : in std_logic; - sample_f1_11 : in std_logic; - sample_f1_61 : in std_logic; - sample_f1_62 : in std_logic; - sample_f1_63 : in std_logic; - sample_f1_32 : in std_logic; - sample_f1_0 : in std_logic; - sample_f1_33 : in std_logic; - sample_f1_1 : in std_logic; - sample_f1_34 : in std_logic; - sample_f1_2 : in std_logic; - sample_f1_35 : in std_logic; - sample_f1_3 : in std_logic; - sample_f1_36 : in std_logic; - sample_f1_4 : in std_logic; - sample_f1_48 : in std_logic; - sample_f1_49 : in std_logic; - sample_f1_50 : in std_logic; - sample_f1_51 : in std_logic; - sample_f1_52 : in std_logic; - sample_f1_53 : in std_logic; - sample_f1_54 : in std_logic; - sample_f1_55 : in std_logic; - sample_f1_56 : in std_logic; - sample_f1_57 : in std_logic; - sample_f1_58 : in std_logic; - sample_f1_59 : in std_logic; - sample_f1_60 : in std_logic; - sample_f1_44 : in std_logic; - sample_f1_12 : in std_logic; - sample_f1_45 : in std_logic; - sample_f1_13 : in std_logic; - sample_f1_46 : in std_logic; - sample_f1_14 : in std_logic; - sample_f1_47 : in std_logic; - sample_f1_15 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f1_out_valid : out std_logic; - N_4 : in std_logic; - I_38_4 : in std_logic; - I_24_4 : in std_logic; - I_20_12 : in std_logic; - I_13_20 : in std_logic; - I_45_4 : in std_logic; - I_9_20 : in std_logic; - I_5_20 : in std_logic; - I_52_4 : in std_logic; - data_shaping_R1 : in std_logic; - data_shaping_R1_0 : in std_logic; - I_56_4 : in std_logic; - I_31_5 : in std_logic; - enable_f1 : in std_logic; - burst_f1 : in std_logic; - sample_f1_val_0 : in std_logic; - start_snapshot_f1 : in std_logic - ); - -end lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1; - -architecture DEF_ARCH of - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_47_1, \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - N_59, N_47_0, counter_points_snapshot_0_sqmuxa_1_0, - ADD_32x32_fast_I308_Y_0_0, - \counter_points_snapshot[28]_net_1\, - ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I310_Y_0_0, - \counter_points_snapshot[30]_net_1\, - ADD_32x32_fast_I309_Y_0_0, - \counter_points_snapshot[29]_net_1\, - ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I253_Y_0_0, N481, N485, - ADD_32x32_fast_I250_Y_2, ADD_32x32_fast_I250_Y_1, N483, - N487, N467, N470, N479, ADD_32x32_fast_I295_Y_0_0, - \counter_points_snapshot[15]_net_1\, - ADD_32x32_fast_I251_Y_2, ADD_32x32_fast_I251_Y_1, N489, - N464, ADD_32x32_fast_I302_Y_0_0, - \counter_points_snapshot[22]_net_1\, - ADD_32x32_fast_I252_Y_1, N550, ADD_32x32_fast_I294_Y_0_0, - \counter_points_snapshot[14]_net_1\, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, - ADD_32x32_fast_I301_Y_0_0, - \counter_points_snapshot[21]_net_1\, - ADD_32x32_fast_I288_Y_0_0, - \un1_counter_points_snapshot[23]\, - ADD_32x32_fast_I293_Y_0_0, - \counter_points_snapshot[13]_net_1\, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I300_Y_0_0, - \counter_points_snapshot[20]_net_1\, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot[5]\, - ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I254_Y_0, N554, ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I255_Y_0, N556, ADD_32x32_fast_I256_Y_0, - I112_un1_Y, N495, ADD_32x32_fast_I263_Y_0, N580, N588, - N533, ADD_32x32_fast_I282_Y_0_0, - \un1_counter_points_snapshot[29]\, - ADD_32x32_fast_I134_Y_1, N401, ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[22]\, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot[26]\, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I126_Y_1, - \un1_counter_points_snapshot[20]\, N419, - ADD_32x32_fast_I126_Y_0, - \un1_counter_points_snapshot[21]\, - ADD_32x32_fast_I118_Y_1, N425, ADD_32x32_fast_I118_Y_0, - N422, data_out_valid_9_i_0, un1_data_in_validlt30_27, - un1_data_in_validlt30_18, un1_data_in_validlt30_17, - un1_data_in_validlt30_23, un1_data_in_validlt30_26, - un1_data_in_validlt30_12, un1_data_in_validlt30_11, - un1_data_in_validlt30_22, un1_data_in_validlt30_25, - un1_data_in_validlt30_8, un1_data_in_validlt30_7, - un1_data_in_validlt30_20, un1_data_in_validlt30_2, - un1_data_in_validlt30_1, un1_data_in_validlt30_15, - un1_data_in_validlt30_14, - \counter_points_snapshot[27]_net_1\, - \counter_points_snapshot[26]_net_1\, - un1_data_in_validlt30_10, - \counter_points_snapshot[19]_net_1\, - \counter_points_snapshot[18]_net_1\, - un1_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un1_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, N758, N638, N622_i, - N654, N748, N628, N786, - \un1_data_out_valid_0_sqmuxa_2[10]\, - \un1_data_out_valid_0_sqmuxa_2[6]\, N652, - \un1_data_out_valid_0_sqmuxa_2[9]\, N789, N750_i, N630, - N744, N752, N_49, N_52, N_60, un1_data_in_validlto30_i, - N_47, counter_points_snapshot_0_sqmuxa_1, N740, N774, - N620, N738, N771_i, N618, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, N380, N756, N636, N529, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_data_out_valid_0_sqmuxa_2[8]\, N650, - \un1_data_out_valid_0_sqmuxa_2[4]\, N592, - \un1_data_out_valid_0_sqmuxa_2[3]\, - \un1_counter_points_snapshot[28]\, N594, - \un1_data_out_valid_0_sqmuxa_2[5]\, N766, N646, N443, - N440, N497, \un1_data_out_valid_0_sqmuxa_2[7]\, - \un1_counter_points_snapshot[24]\, N754, N634, N572, - \un1_data_out_valid_0_sqmuxa_2[11]\, N783, N742, N777, - N762, N642, N626, N764, N746, N574, N515, N511, N566, - N582, N_90, counter_points_snapshot_2_sqmuxa, N_94, - \counter_points_snapshot_10[6]\, - \counter_points_snapshot_10[10]\, N_25, N_35, - \sample_f1_wdata[32]\, \sample_f1_wdata[33]\, - \sample_f1_wdata[34]\, \sample_f1_wdata[35]\, - \sample_f1_wdata[19]\, \sample_f1_wdata[20]\, - \sample_f1_wdata[21]\, \sample_f1_wdata[22]\, - \sample_f1_wdata[23]\, \sample_f1_wdata[24]\, - \sample_f1_wdata[25]\, \sample_f1_wdata[26]\, - \sample_f1_wdata[27]\, \sample_f1_wdata[28]\, - \sample_f1_wdata[29]\, \sample_f1_wdata[30]\, - \sample_f1_wdata[31]\, \sample_f1_wdata[43]\, - \sample_f1_wdata[44]\, \sample_f1_wdata[45]\, - \sample_f1_wdata[46]\, \sample_f1_wdata[47]\, - \sample_f1_wdata[16]\, \sample_f1_wdata[17]\, - \sample_f1_wdata[18]\, \sample_f1_wdata[36]\, - \sample_f1_wdata[37]\, \sample_f1_wdata[38]\, - \sample_f1_wdata[39]\, \sample_f1_wdata[40]\, - \sample_f1_wdata[41]\, \sample_f1_wdata[42]\, N_9, N_7, - N780, N503, N570, N_27, \counter_points_snapshot_10[9]\, - N_93, N446, N_39, \counter_points_snapshot_10[1]\, N_85, - N_45, N_43, N_13, N_11, \counter_points_snapshot_10[2]\, - N_86, N_92, \counter_points_snapshot_10[8]\, N590, N531, - N527, N386, N383, \un1_counter_points_snapshot[31]\, - \un1_data_out_valid_0_sqmuxa_2[0]\, N_84, - \counter_points_snapshot_10[0]\, N586, N523, N_87, N_88, - \counter_points_snapshot_10[3]\, - \counter_points_snapshot_10[4]\, N_17, - \counter_points_snapshot_10[5]\, N_89, N519, N_31, N_29, - \counter_points_snapshot_10[7]\, N_91, N_33, N_41, - \counter_points_snapshot_10[11]\, N_95, N_21, N768, N_15, - N_37, N_23, N760, N_19, N578, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => N_9, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[27]\, C => N592, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - \counter_points_snapshot_RNI7ND9[16]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un1_data_in_validlt30_8); - - \data_out[110]\ : DFN1C0 - port map(D => \sample_f1_wdata[46]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(110)); - - \counter_points_snapshot_RNI9G66[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un1_data_in_validlt30_4); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[10]\, B => - I_56_4, S => counter_points_snapshot_2_sqmuxa, Y => N_94); - - \counter_points_snapshot_RNO[27]\ : XA1C - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - N_52, Y => N_37); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => N_39, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[28]_net_1\); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762, B => ADD_32x32_fast_I299_Y_0_0, C => - N_52, Y => N_21); - - \data_out_RNO[96]\ : MX2 - port map(A => sample_f1_15, B => sample_f1_47, S => - data_shaping_R1_0, Y => \sample_f1_wdata[32]\); - - \data_out[91]\ : DFN1C0 - port map(D => \sample_f1_wdata[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(91)); - - \counter_points_snapshot_RNISSL51[23]\ : NOR3C - port map(A => un1_data_in_validlt30_12, B => - un1_data_in_validlt30_11, C => un1_data_in_validlt30_22, - Y => un1_data_in_validlt30_26); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f1_wdata_56, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1C - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - N_52, Y => N_31); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : OR3A - port map(A => ADD_32x32_fast_I254_Y_0, B => N626, C => N783, - Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : NOR2 - port map(A => N586, B => N578, Y => N642); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f1_wdata_66, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => \sample_f1_wdata[40]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : OR3B - port map(A => N443, B => N446, C => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => I_20_12, B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => N_60, Y => N_88); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[1]\, B => - I_5_20, S => counter_points_snapshot_2_sqmuxa, Y => N_85); - - \data_out[102]\ : DFN1C0 - port map(D => \sample_f1_wdata[38]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3B - port map(A => N622_i, B => ADD_32x32_fast_I252_Y_1, C => - N777, Y => N742); - - \counter_points_snapshot_RNIHVMR1[11]\ : MX2 - port map(A => N_4, B => \counter_points_snapshot[11]_net_1\, - S => counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[29]\, B => - N_47_0, Y => ADD_32x32_fast_I282_Y_0_0); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_91, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[29]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1C - port map(A => N780, B => ADD_32x32_fast_I292_Y_0_0, C => - N_52, Y => N_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : NOR2 - port map(A => N650, B => N634, Y => N771_i); - - \data_out[93]\ : DFN1C0 - port map(D => \sample_f1_wdata[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(93)); - - \counter_points_snapshot_RNIHME71[4]\ : MX2C - port map(A => I_20_12, B => - \counter_points_snapshot[4]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[27]\); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[4]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[21]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f1_wdata_95, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => \sample_f1_wdata[41]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(105)); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f1_wdata_77, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR3B - port map(A => N443, B => N446, C => N495, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2B - port map(A => N527, B => N523, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => \sample_f1_wdata[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(81)); - - \counter_points_snapshot_RNIU5411[2]\ : MX2C - port map(A => I_9_20, B => - \counter_points_snapshot[2]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[29]\); - - counter_points_snapshot_10_12_i_o2 : OR3B - port map(A => enable_f1, B => N_60, C => burst_f1, Y => - N_52); - - \data_out_RNO[99]\ : MX2 - port map(A => sample_f1_12, B => sample_f1_44, S => - data_shaping_R1_0, Y => \sample_f1_wdata[35]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[30]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I310_Y_0_0); - - \data_out_RNO[104]\ : MX2 - port map(A => sample_f1_7, B => sample_f1_39, S => - data_shaping_R1, Y => \sample_f1_wdata[40]\); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : OR3 - port map(A => I112_un1_Y, B => N495, C => N550, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - OR2A - port map(A => N771_i, B => N425, Y => N768); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f1_wdata_50, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : OR2 - port map(A => N578, B => N570, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : NOR3 - port map(A => N419, B => N422, C => N503, Y => N566); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => N_37, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f1_wdata_79, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(143)); - - \counter_points_snapshot_RNI319P[27]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : OR2 - port map(A => N590, B => N533, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3C - port map(A => N443, B => N440, C => N497, Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f1_wdata_48, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f1_wdata_60, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(124)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f1_wdata_70, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : AO1 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[25]\, C => N_47, Y => N523); - - \counter_points_snapshot_RNO[28]\ : XA1B - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - N_52, Y => N_39); - - \data_out[83]\ : DFN1C0 - port map(D => \sample_f1_wdata[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I250_Y_1, B => N483, C => N487, - Y => ADD_32x32_fast_I250_Y_2); - - \counter_points_snapshot_RNIMURI[26]\ : NOR3A - port map(A => un1_data_in_validlt30_14, B => - \counter_points_snapshot[27]_net_1\, C => - \counter_points_snapshot[26]_net_1\, Y => - un1_data_in_validlt30_22); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f1_wdata_58, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f1_wdata_51, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(115)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : OA1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[8]\, C => N_47, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : - OA1C - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_counter_points_snapshot[4]\, C => N_47, Y => N481); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AO1D - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_1, C => N422, Y => ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f1_wdata_68, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(132)); - - \counter_points_snapshot_RNIM3VT[1]\ : MX2C - port map(A => I_5_20, B => - \counter_points_snapshot[1]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[30]\); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => N_43, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[30]_net_1\); - - \data_out[96]\ : DFN1C0 - port map(D => \sample_f1_wdata[32]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(96)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : NOR3 - port map(A => N628, B => ADD_32x32_fast_I255_Y_0, C => N786, - Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[14]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f1_wdata_61, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(125)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f1_wdata_71, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(135)); - - \data_out_RNO[87]\ : NOR2B - port map(A => sample_f1_56, B => data_shaping_R1_0, Y => - \sample_f1_wdata[23]\); - - \data_out_RNO[108]\ : MX2 - port map(A => sample_f1_3, B => sample_f1_35, S => - data_shaping_R1, Y => \sample_f1_wdata[44]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_G0N : NOR3B - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N425); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : NOR2 - port map(A => ADD_32x32_fast_I253_Y_0_0, B => N752, Y => - N744); - - data_out_valid : DFN1C0 - port map(D => N_49, CLK => HCLK_c, CLR => HRESETn_c, Q => - data_f1_out_valid); - - \data_out_RNO[90]\ : NOR2B - port map(A => sample_f1_53, B => data_shaping_R1_0, Y => - \sample_f1_wdata[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : OR3 - port map(A => I112_un1_Y, B => N503, C => N570, Y => N626); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I29_G0N : OR3B - port map(A => \counter_points_snapshot[29]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N467); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f1_wdata_7, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f1_wdata_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => N_19, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : OR3B - port map(A => N638, B => N622_i, C => N654, Y => N758); - - \data_out_RNO[98]\ : MX2 - port map(A => sample_f1_13, B => sample_f1_45, S => - data_shaping_R1_0, Y => \sample_f1_wdata[34]\); - - \data_out[86]\ : DFN1C0 - port map(D => \sample_f1_wdata[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[23]\, B => - N_47_0, Y => ADD_32x32_fast_I288_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : OR3 - port map(A => I112_un1_Y, B => N503, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f1_wdata_86, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(150)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_0, Y => ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - N_47_0, Y => ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f1_wdata_84, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(148)); - - GND_i : GND - port map(Y => \GND\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_G0N : NOR3B - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N419); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[8]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : OR2A - port map(A => N566, B => N574, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR2B - port map(A => N523, B => N519, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f1_wdata_9, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_out[92]\ : DFN1C0 - port map(D => \sample_f1_wdata[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f1_wdata_3, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => \sample_f1_wdata[43]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I14_G0N : NOR3B - port map(A => \counter_points_snapshot[14]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N422); - - \counter_points_snapshot_RNISOQ14[6]\ : NOR3C - port map(A => un1_data_in_validlt30_26, B => - un1_data_in_validlt30_25, C => un1_data_in_validlt30_27, - Y => un1_data_in_validlto30_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OR3B - port map(A => N580, B => N588, C => N533, Y => - ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_90, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[21]\, C => N786, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => N_41, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[29]_net_1\); - - \data_out_RNO[94]\ : NOR2B - port map(A => sample_f1_49, B => data_shaping_R1_0, Y => - \sample_f1_wdata[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[20]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1C - port map(A => N750_i, B => ADD_32x32_fast_I305_Y_0_0, C => - N_52, Y => N_33); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => N_23, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[22]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I302_Y_0_0); - - \counter_points_snapshot_RNI2T8P[26]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot[5]\); - - \data_out_RNO[95]\ : NOR2B - port map(A => sample_f1_48, B => data_shaping_R1, Y => - \sample_f1_wdata[31]\); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => N_17, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : OR2 - port map(A => N590, B => N582, Y => N646); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : NOR2 - port map(A => N386, B => N383, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - N_47_0, Y => ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I28_G0N : OR3B - port map(A => \counter_points_snapshot[28]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N464); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : OR3B - port map(A => ADD_32x32_fast_I250_Y_2, B => N771_i, C => - N618, Y => N738); - - \data_out_RNO[93]\ : NOR2B - port map(A => sample_f1_50, B => data_shaping_R1_0, Y => - \sample_f1_wdata[29]\); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f1_wdata_90, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(154)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - OR2B - port map(A => N764, B => N497, Y => N760); - - \data_out[82]\ : DFN1C0 - port map(D => \sample_f1_wdata[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f1_wdata_53, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1C - port map(A => N760, B => ADD_32x32_fast_I300_Y_0_0, C => - N_52, Y => N_23); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : NOR3 - port map(A => N483, B => N487, C => N554, Y => - ADD_32x32_fast_I254_Y_0); - - \counter_points_snapshot_RNIICL51[14]\ : NOR3C - port map(A => un1_data_in_validlt30_8, B => - un1_data_in_validlt30_7, C => un1_data_in_validlt30_20, Y - => un1_data_in_validlt30_25); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f1_wdata_12, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(76)); - - \counter_points_snapshot_RNI1G66[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un1_data_in_validlt30_2); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f1_wdata_88, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(152)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_1 : AO1A - port map(A => N_47_1, B => - \un1_counter_points_snapshot[15]\, C => N425, Y => - ADD_32x32_fast_I118_Y_1); - - \counter_points_snapshot_RNIE0DC[6]\ : NOR3A - port map(A => un1_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un1_data_in_validlt30_17); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f1_wdata_85, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(149)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f1_wdata_63, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : OR2A - port map(A => N638, B => N654, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : NOR2 - port map(A => N652, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2A - port map(A => N588, B => N533, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f1_wdata_73, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I30_G0N : OR3B - port map(A => \counter_points_snapshot[30]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N470); - - \data_out_RNO[81]\ : NOR2B - port map(A => sample_f1_62, B => data_shaping_R1, Y => - \sample_f1_wdata[17]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : OR2B - port map(A => N531, B => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f1_wdata_91, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(155)); - - \counter_points_snapshot_RNI1T8P[16]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_89, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1C - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - N_52, Y => N_17); - - data_out_valid_RNO_0 : NOR2B - port map(A => enable_f1, B => sample_f1_val_0, Y => - data_out_valid_9_i_0); - - \data_out[90]\ : DFN1C0 - port map(D => \sample_f1_wdata[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_0 : AO1 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[21]\, C => N_47_1, Y => - ADD_32x32_fast_I126_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR3 - port map(A => N419, B => N422, C => N511, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR3B - port map(A => ADD_32x32_fast_I251_Y_2, B => N774, C => N620, - Y => N740); - - \counter_points_snapshot_RNO[14]\ : XA1C - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - N_52, Y => N_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_G0N : OR3B - port map(A => \counter_points_snapshot[20]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N440); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR2A - port map(A => N519, B => N515, Y => N578); - - \counter_points_snapshot_RNI385K1[8]\ : MX2 - port map(A => I_45_4, B => - \counter_points_snapshot[8]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[23]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I282_Y_0_0, B => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - \data_out_RNO[92]\ : NOR2B - port map(A => sample_f1_51, B => data_shaping_R1_0, Y => - \sample_f1_wdata[28]\); - - counter_points_snapshot_2_sqmuxa_0_a2 : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_60, Y => - counter_points_snapshot_2_sqmuxa); - - \data_out[99]\ : DFN1C0 - port map(D => \sample_f1_wdata[35]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(99)); - - \counter_points_snapshot_RNI359P[18]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - \counter_points_snapshot_RNI219P[17]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - \data_out_RNO[100]\ : MX2 - port map(A => sample_f1_11, B => sample_f1_43, S => - data_shaping_R1, Y => \sample_f1_wdata[36]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I76_Y : OA1C - port map(A => \un1_counter_points_snapshot[23]\, B => N_47, - C => N401, Y => N519); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : NOR3 - port map(A => N634, B => N618, C => N650, Y => N754); - - \data_out[106]\ : DFN1C0 - port map(D => \sample_f1_wdata[42]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1C - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - N_52, Y => N_25); - - \data_out_RNO[103]\ : MX2 - port map(A => sample_f1_8, B => sample_f1_40, S => - data_shaping_R1, Y => \sample_f1_wdata[39]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : OR2 - port map(A => N515, B => N511, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => \sample_f1_wdata[34]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(98)); - - \counter_points_snapshot_RNIEFFM1[6]\ : NOR3C - port map(A => un1_data_in_validlt30_18, B => - un1_data_in_validlt30_17, C => un1_data_in_validlt30_23, - Y => un1_data_in_validlt30_27); - - \counter_points_snapshot_RNI1NC9[23]\ : NOR2 - port map(A => \counter_points_snapshot[22]_net_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - un1_data_in_validlt30_11); - - \data_out[80]\ : DFN1C0 - port map(D => \sample_f1_wdata[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f1_wdata_8, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : NOR3 - port map(A => N630, B => ADD_32x32_fast_I256_Y_0, C => N789, - Y => N750_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_G0N : OR3B - port map(A => \counter_points_snapshot[22]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N446); - - \counter_points_snapshot_RNITF66[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un1_data_in_validlt30_1); - - \counter_points_snapshot_RNI7C941[3]\ : MX2C - port map(A => I_13_20, B => - \counter_points_snapshot[3]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[28]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AOI1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47, Y => - I112_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : AX1B - port map(A => N401, B => N650, C => - ADD_32x32_fast_I288_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - \data_out_RNO[107]\ : MX2 - port map(A => sample_f1_4, B => sample_f1_36, S => - data_shaping_R1, Y => \sample_f1_wdata[43]\); - - counter_points_snapshot_2_sqmuxa_0_a2_0 : OR2A - port map(A => start_snapshot_f1, B => sample_f1_val_0, Y - => N_60); - - \data_out[89]\ : DFN1C0 - port map(D => \sample_f1_wdata[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(89)); - - \counter_points_snapshot_RNIGRMR1[10]\ : MX2C - port map(A => I_56_4, B => - \counter_points_snapshot[10]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[21]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : NOR2 - port map(A => ADD_32x32_fast_I263_Y_0, B => N628, Y => N764); - - counter_points_snapshot_0_sqmuxa_1_0_a2 : OR3B - port map(A => start_snapshot_f1, B => sample_f1_val_0, C - => burst_f1, Y => counter_points_snapshot_0_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, C => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out_RNO[101]\ : MX2 - port map(A => sample_f1_10, B => sample_f1_42, S => - data_shaping_R1, Y => \sample_f1_wdata[37]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f1_wdata_52, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => N_21, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[2]\, B => - I_9_20, S => counter_points_snapshot_2_sqmuxa, Y => N_86); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - N_47_0, Y => ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : OR2 - port map(A => N594, B => N586, Y => N650); - - \counter_points_snapshot_RNI0L8P[24]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[26]\, C => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1C - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - N_52, Y => N_19); - - \data_out[88]\ : DFN1C0 - port map(D => \sample_f1_wdata[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XNOR2 - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f1_wdata_62, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => \sample_f1_wdata[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f1_wdata_76, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f1_wdata_72, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(136)); - - \counter_points_snapshot_RNI8HSA[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[30]_net_1\, Y => - un1_data_in_validlt30_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I293_Y_0_0); - - \un1_data_out_valid_0_sqmuxa_1_i_0[31]\ : AOI1B - port map(A => start_snapshot_f1, B => burst_f1, C => - sample_f1_val_0, Y => - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\); - - \counter_points_snapshot_RNI8EQI[18]\ : NOR3A - port map(A => un1_data_in_validlt30_10, B => - \counter_points_snapshot[19]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un1_data_in_validlt30_20); - - \counter_points_snapshot_RNII6BN1[9]\ : MX2C - port map(A => I_52_4, B => - \counter_points_snapshot[9]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[22]\); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => N_27, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[22]_net_1\); - - \counter_points_snapshot_RNI57D9[24]\ : NOR2 - port map(A => \counter_points_snapshot[24]_net_1\, B => - \counter_points_snapshot[25]_net_1\, Y => - un1_data_in_validlt30_12); - - \data_out_RNO[86]\ : NOR2B - port map(A => sample_f1_57, B => data_shaping_R1_0, Y => - \sample_f1_wdata[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2B - port map(A => N531, B => N380, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => N_47_0, - Y => ADD_32x32_fast_I304_Y_0_0); - - \data_out[101]\ : DFN1C0 - port map(D => \sample_f1_wdata[37]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(101)); - - \counter_points_snapshot_RNINKBE4[31]\ : OA1B - port map(A => \counter_points_snapshot[31]_net_1\, B => - un1_data_in_validlto30_i, C => start_snapshot_f1, Y => - N_59); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f1_wdata_93, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_88, Y => - \counter_points_snapshot_10[4]\); - - \counter_points_snapshot_RNI37D9[14]\ : NOR2 - port map(A => \counter_points_snapshot[14]_net_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - un1_data_in_validlt30_7); - - \counter_points_snapshot_RNO[30]\ : XA1C - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - N_52, Y => N_43); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : AO1 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => N_47, Y => N497); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR3 - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N572, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[25]\, C => N_47_1, Y => - ADD_32x32_fast_I134_Y_0); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f1_wdata_6, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => I_24_4, B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => N_60, Y => N_89); - - \data_out[84]\ : DFN1C0 - port map(D => \sample_f1_wdata[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => \sample_f1_wdata[39]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I7_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[24]\, B => N_47, - Y => N401); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : AO1 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[27]\, C => N_47, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - N_52, Y => N_35); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f1_wdata_15, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \counter_points_snapshot_RNITC8P[12]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f1_wdata_80, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(144)); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0 : OR3B - port map(A => start_snapshot_f1, B => sample_f1_val_0, C - => burst_f1, Y => counter_points_snapshot_0_sqmuxa_1_0); - - \data_out_RNO[89]\ : NOR2B - port map(A => sample_f1_54, B => data_shaping_R1_0, Y => - \sample_f1_wdata[25]\); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_92, Y => - \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => \sample_f1_wdata[47]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(111)); - - \counter_points_snapshot_RNID7E9[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un1_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2A - port map(A => \un1_counter_points_snapshot[31]\, B => - N_47_1, Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f1_wdata_78, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f1_wdata_14, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - N_52, Y => N_29); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : OR2A - port map(A => N580, B => N572, Y => N636); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_1 : AO1A - port map(A => N_47_0, B => - \un1_counter_points_snapshot[23]\, C => N401, Y => - ADD_32x32_fast_I134_Y_1); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => I_13_20, B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => N_60, Y => N_87); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => N_35, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => N_47_0, - Y => ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : NOR3 - port map(A => N479, B => N483, C => N550, Y => - ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I1_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[30]\, B => - N_47_1, Y => N383); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f1_wdata_57, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : AO1A - port map(A => N_47_1, B => - \un1_counter_points_snapshot[15]\, C => N425, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_84, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f1_wdata_67, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f1_wdata_49, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(113)); - - \counter_points_snapshot_RNIS4KA1[5]\ : MX2C - port map(A => I_24_4, B => - \counter_points_snapshot[5]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[26]\); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f1_wdata_81, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(145)); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f1_wdata_2, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[1]_net_1\); - - \counter_points_snapshot_RNO[31]\ : XA1B - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - N_52, Y => N_45); - - \data_out_RNO[109]\ : MX2 - port map(A => sample_f1_2, B => sample_f1_34, S => - data_shaping_R1, Y => \sample_f1_wdata[45]\); - - \counter_points_snapshot_RNO_0[0]\ : MX2B - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => N_60, Y => N_84); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N771_i, B => ADD_32x32_fast_I295_Y_0_0, C => - N_52, Y => N_13); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f1_wdata_59, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(123)); - - GND_i_0 : GND - port map(Y => GND_0); - - \counter_points_snapshot_RNILDVG1[7]\ : MX2C - port map(A => I_38_4, B => - \counter_points_snapshot[7]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[24]\); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f1_wdata_69, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : OR3B - port map(A => \counter_points_snapshot[21]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N443); - - \counter_points_snapshot_RNO[29]\ : XA1C - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - N_52, Y => N_41); - - \counter_points_snapshot_RNI5OT25_1[31]\ : OR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => N_45, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : AO1C - port map(A => N_47, B => \un1_counter_points_snapshot[4]\, - C => N464, Y => N479); - - \counter_points_snapshot_RNI1P8P[25]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - \data_out_RNO[97]\ : MX2 - port map(A => sample_f1_14, B => sample_f1_46, S => - data_shaping_R1_0, Y => \sample_f1_wdata[33]\); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f1_wdata_10, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(74)); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_94, Y => - \counter_points_snapshot_10[10]\); - - \data_out[108]\ : DFN1C0 - port map(D => \sample_f1_wdata[44]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[6]\, B => - I_31_5, S => counter_points_snapshot_2_sqmuxa, Y => N_90); - - \counter_points_snapshot_RNIF5QQ[0]\ : MX2A - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[31]\); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f1_wdata_92, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(156)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_Y : OR3B - port map(A => N580, B => N588, C => N533, Y => N786); - - \data_out_RNO[106]\ : MX2 - port map(A => sample_f1_5, B => sample_f1_37, S => - data_shaping_R1, Y => \sample_f1_wdata[42]\); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => I_45_4, B => - \un1_data_out_valid_0_sqmuxa_2[8]\, S => N_60, Y => N_92); - - \data_out_RNO[80]\ : NOR2B - port map(A => sample_f1_63, B => data_shaping_R1, Y => - \sample_f1_wdata[16]\); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_85, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_0, - Y => ADD_32x32_fast_I303_Y_0_0); - - \counter_points_snapshot_RNIT6C9[20]\ : NOR2 - port map(A => \counter_points_snapshot[20]_net_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - un1_data_in_validlt30_10); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : AOI1 - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[5]\, C => N_47, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - OR2 - port map(A => N756, B => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - N_52, Y => N_27); - - \data_out_RNO[88]\ : NOR2B - port map(A => sample_f1_55, B => data_shaping_R1_0, Y => - \sample_f1_wdata[24]\); - - \counter_points_snapshot_RNIQTOI[10]\ : NOR3A - port map(A => un1_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un1_data_in_validlt30_18); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I146_Y : NOR2 - port map(A => N533, B => N529, Y => N592); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => N_7, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => N_31, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[24]_net_1\); - - \counter_points_snapshot_RNI6H9N[0]\ : NOR3C - port map(A => un1_data_in_validlt30_2, B => - un1_data_in_validlt30_1, C => un1_data_in_validlt30_15, Y - => un1_data_in_validlt30_23); - - \data_out[95]\ : DFN1C0 - port map(D => \sample_f1_wdata[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(95)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR2B - port map(A => ADD_32x32_fast_I126_Y_1, B => - ADD_32x32_fast_I126_Y_0, Y => N572); - - \data_out_RNO[110]\ : MX2 - port map(A => sample_f1_1, B => sample_f1_33, S => - data_shaping_R1, Y => \sample_f1_wdata[46]\); - - \counter_points_snapshot_RNIVMC9[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un1_data_in_validlt30_6); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[9]\, B => - I_52_4, S => counter_points_snapshot_2_sqmuxa, Y => N_93); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : OA1C - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N419, Y => ADD_32x32_fast_I126_Y_1); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_87, Y => - \counter_points_snapshot_10[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[27]\, C => N_47_1, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f1_wdata_54, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(118)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR2A - port map(A => N380, B => N646, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[5]\, B => N_47_0, - Y => ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : NOR3B - port map(A => N467, B => N464, C => N481, Y => - ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2A - port map(A => N642, B => N594, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[24]\, C => N650, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[25]\, C => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - AO1C - port map(A => N_47, B => \un1_counter_points_snapshot[8]\, - C => N446, Y => N489); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[20]\, C => N783, Y => - \un1_data_out_valid_0_sqmuxa_2[11]\); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f1_wdata_64, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(128)); - - \counter_points_snapshot_RNO[11]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_95, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => \sample_f1_wdata[33]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f1_wdata_74, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(138)); - - \data_out_RNO[84]\ : NOR2B - port map(A => sample_f1_59, B => data_shaping_R1_0, Y => - \sample_f1_wdata[20]\); - - \data_out[85]\ : DFN1C0 - port map(D => \sample_f1_wdata[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[3]_net_1\); - - \data_out_RNO[85]\ : NOR2B - port map(A => sample_f1_58, B => data_shaping_R1_0, Y => - \sample_f1_wdata[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => \sample_f1_wdata[45]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(109)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : OA1C - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[20]\, C => N_47, Y => N511); - - \data_out_RNO[111]\ : MX2 - port map(A => sample_f1_0, B => sample_f1_32, S => - data_shaping_R1, Y => \sample_f1_wdata[47]\); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => N_29, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => N_25, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : OR3 - port map(A => N485, B => N489, C => N556, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f1_wdata_83, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(147)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f1_wdata_87, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(151)); - - \data_out_RNO[83]\ : NOR2B - port map(A => sample_f1_60, B => data_shaping_R1_0, Y => - \sample_f1_wdata[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - N_47_0, Y => ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[28]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => \sample_f1_wdata[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(87)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f1_wdata_89, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(153)); - - \counter_points_snapshot_RNI499P[19]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[28]\, C => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR3 - port map(A => N636, B => N620, C => N652, Y => N756); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AO1D - port map(A => \un1_counter_points_snapshot[28]\, B => N_47, - C => N386, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : NOR2 - port map(A => ADD_32x32_fast_I142_Y_0, B => N529, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => N_47_0, - Y => ADD_32x32_fast_I307_Y_0_0); - - \data_out_RNO[91]\ : NOR2B - port map(A => sample_f1_52, B => data_shaping_R1_0, Y => - \sample_f1_wdata[27]\); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f1_wdata_55, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : NOR3B - port map(A => N467, B => N470, C => N479, Y => - ADD_32x32_fast_I250_Y_1); - - \counter_points_snapshot_RNI5OT25[31]\ : OR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_1); - - \data_out_RNO[102]\ : MX2 - port map(A => sample_f1_9, B => sample_f1_41, S => - data_shaping_R1, Y => \sample_f1_wdata[38]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AOI1 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[21]\, C => N_47, Y => N515); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[7]\, B => - I_38_4, S => counter_points_snapshot_2_sqmuxa, Y => N_91); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_93, Y => - \counter_points_snapshot_10[9]\); - - \counter_points_snapshot_RNI5OT25_0[31]\ : OR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_0); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f1_wdata_5, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f1_wdata_65, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I251_Y_1, B => N485, C => N489, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f1_wdata_75, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => N_33, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[25]_net_1\); - - \data_out_RNO[82]\ : NOR2B - port map(A => sample_f1_61, B => data_shaping_R1, Y => - \sample_f1_wdata[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : NOR2 - port map(A => ADD_32x32_fast_I134_Y_1, B => - ADD_32x32_fast_I134_Y_0, Y => N580); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - OA1C - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N783, Y => N780); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : OR2A - port map(A => N380, B => N383, Y => N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : OA1C - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[7]\, C => N_47, Y => N485); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f1_wdata_11, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(75)); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f1_wdata_4, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(68)); - - \counter_points_snapshot_RNO_0[11]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[11]\, B => N_4, - S => counter_points_snapshot_2_sqmuxa, Y => N_95); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : OAI1 - port map(A => N_47, B => \un1_counter_points_snapshot[12]\, - C => N440, Y => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OR3 - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N556, Y => N620); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : NOR3A - port map(A => N380, B => N646, C => N630, Y => N766); - - \counter_points_snapshot_RNIVG8P[23]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - \counter_points_snapshot_RNO[16]\ : XA1C - port map(A => N768, B => ADD_32x32_fast_I296_Y_0_0, C => - N_52, Y => N_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : NOR3A - port map(A => N566, B => I112_un1_Y, C => N495, Y => N622_i); - - \counter_points_snapshot_RNI8NPD1[6]\ : MX2C - port map(A => I_31_5, B => - \counter_points_snapshot[6]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[25]\); - - data_out_valid_RNO : OA1A - port map(A => N_59, B => burst_f1, C => - data_out_valid_9_i_0, Y => N_49); - - \data_out[100]\ : DFN1C0 - port map(D => \sample_f1_wdata[36]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : OR3A - port map(A => N642, B => N594, C => N626, Y => N762); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : OR2 - port map(A => N481, B => N485, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f1_wdata_13, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f1_wdata_82, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_86, Y => - \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : NOR2 - port map(A => N582, B => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1B - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - N_52, Y => N_9); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f1_wdata_94, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(158)); - - \data_out_RNO[105]\ : MX2 - port map(A => sample_f1_6, B => sample_f1_38, S => - data_shaping_R1, Y => \sample_f1_wdata[41]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I2_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[29]\, B => N_47, - Y => N386); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f1_wdata_0, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f1_out(64)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_controler is - - port( delta_f2_f0 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - start_snapshot_f2 : out std_logic; - start_snapshot_f1 : out std_logic; - start_snapshot_f0 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_f0_val_0 : in std_logic; - sample_f2_val : in std_logic; - coarse_time_0_c : in std_logic - ); - -end lpp_waveform_snapshot_controler; - -architecture DEF_ARCH of lpp_waveform_snapshot_controler is - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AXOI2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_34, N_80, \counter_delta_f0[26]_net_1\, N_57_0, - N_265, \counter_delta_f0[19]_net_1\, N_105, - counter_delta_f0_n19, N_106, N_57, counter_delta_f0_n20, - \counter_delta_f0[20]_net_1\, N_89, - \counter_delta_f0[0]_net_1\, \counter_delta_f0[1]_net_1\, - \counter_delta_f0[2]_net_1\, N_99, N_67, - \counter_delta_f0[11]_net_1\, - \counter_delta_f0[12]_net_1\, N_101, - \counter_delta_f0[13]_net_1\, - \counter_delta_f0[14]_net_1\, N_103, - \counter_delta_f0[15]_net_1\, - \counter_delta_f0[16]_net_1\, - \counter_delta_f0[17]_net_1\, - \counter_delta_f0[18]_net_1\, N_276, N_58, - \counter_delta_f0[21]_net_1\, N_277, N_86_i, N_28, N_62, - \counter_delta_f0[23]_net_1\, N_30, N_98_i, N_32, N_66, - \counter_delta_f0[25]_net_1\, - \counter_delta_f0[22]_net_1\, - \counter_delta_f0[24]_net_1\, N_63, - \counter_delta_f0[9]_net_1\, \counter_delta_f0[10]_net_1\, - N_59, \counter_delta_f0[7]_net_1\, - \counter_delta_f0[8]_net_1\, N_55, - \counter_delta_f0[5]_net_1\, \counter_delta_f0[6]_net_1\, - \counter_delta_f0[3]_net_1\, \counter_delta_f0[4]_net_1\, - un2_coarse_time_0_0, \coarse_time_0_r\, N_504_0, - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, N_9_0, - N_9_tz, N_7, \start_snapshot_fothers_temp\, - counter_delta_snapshot_e27_0_0_o2_N_7_0, - \counter_delta_snapshot_e27_0_0_o2_m6_e_3\, - counter_delta_snapshot_e27_0_0_o2_m6_e_2, N_398, - start_snapshot_f22_0_a2_11_0_a2_3_i, - \counter_delta_snapshot[23]_net_1\, - \counter_delta_snapshot[22]_net_1\, - start_snapshot_f22_0_a2_11_0_a2_2_i, - \counter_delta_snapshot[19]_net_1\, - \counter_delta_snapshot[18]_net_1\, N_495, - \counter_delta_snapshot[12]_net_1\, - start_snapshot_f2_temp3_0_a2_0, start_snapshot_f22_11_i, - start_snapshot_f22_10, start_snapshot_f22_0_a2_1, - start_snapshot_f22_0_a2_0, - start_snapshot_f22_0_a2_11_0_a2_2_0, - un12_start_snapshot_fothers_temp_NE, - un12_start_snapshot_fothers_temp_NE_12, - un12_start_snapshot_fothers_temp_NE_13, N_493, - \counter_delta_snapshot_e12_i_0_a2_0\, - start_snapshot_f2_temp3, counter_delta_snapshot_e12_i_0_0, - counter_delta_snapshot_e25_0_0_0, - \counter_delta_snapshot[25]_net_1\, N_421, - counter_delta_snapshot_e25_0_0_a2_0, - counter_delta_snapshot_e23_0_0_0, N_189, - counter_delta_snapshot_e8_i_0, - counter_delta_snapshot_e8_i_a2_0, N_466, - counter_delta_snapshot_e2_i_0, - counter_delta_snapshot_e2_i_a2_0, N_436, - counter_delta_snapshot_e3_i_0, - \counter_delta_snapshot[3]_net_1\, N_440, - counter_delta_snapshot_e6_i_0, - \counter_delta_snapshot[6]_net_1\, N_455, - counter_delta_snapshot_e7_i_0, - \counter_delta_snapshot[7]_net_1\, N_460, - counter_delta_snapshot_e9_i_0, - counter_delta_snapshot_e9_i_a2_0, N_470, - counter_delta_snapshot_e15_i_0_0, - \counter_delta_snapshot[15]_net_1\, N_478, - counter_delta_snapshot_e14_i_0_0, - \counter_delta_snapshot[14]_net_1\, N_484, - counter_delta_snapshot_e13_i_0_0, - \counter_delta_snapshot[13]_net_1\, N_285, - counter_delta_snapshot_e4_i_0, - \counter_delta_snapshot[4]_net_1\, N_445, - counter_delta_snapshot_e5_i_0, - \counter_delta_snapshot_i[5]\, N_450, - counter_delta_snapshot_e11_i_0_0, - counter_delta_snapshot_e11_i_0_a2_0, N_294, - counter_delta_snapshot_e0_i_0, - \counter_delta_snapshot[0]_net_1\, - counter_delta_snapshot_e10_i_0, - \counter_delta_snapshot[10]_net_1\, N_474, - counter_delta_f0_n18_0_0_a2_0, - counter_delta_snapshot_e16_i_i_0, - \counter_delta_snapshot[16]_net_1\, N_168, - counter_delta_snapshot_e19_i_i_0, - counter_delta_snapshot_e19_i_i_a2_0, N_178, - counter_delta_snapshot_e21_0_0_0, - \counter_delta_snapshot[21]_net_1\, un2_coarse_time_0, - N_183, counter_delta_snapshot_e13_i_0_a2_2_0, N_393, - counter_delta_snapshot_e23_0_0_a2_0, - counter_delta_f0_n16_0_0_a2_0, - counter_delta_snapshot_e21_0_0_a2_0, - \counter_delta_snapshot_RNI0DDG1[7]_net_1\, - \counter_delta_snapshot[8]_net_1\, N_388, - \counter_delta_snapshot[2]_net_1\, N_382, - counter_delta_snapshot_e6_i_a2_0, N_386, - counter_delta_snapshot_e7_i_a2_0, N_387, - \counter_delta_snapshot[9]_net_1\, N_389, - counter_delta_snapshot_e15_i_0_a2_0, N_395, - counter_delta_snapshot_e14_i_0_a2_0, N_394, - counter_delta_snapshot_e13_i_0_a2_0, - counter_delta_snapshot_e16_i_i_a2_0, N_396, - counter_delta_snapshot_e4_i_a2_0, N_384, - counter_delta_snapshot_e5_i_a2_0, N_385, - \counter_delta_snapshot_i[11]\, N_391, - counter_delta_f0_n14_0_0_a2_0, - \counter_delta_snapshot_e27_0_0_o2_m6_e_1\, - start_snapshot_f22_0_a2_11_0_a2_1, - \counter_delta_snapshot[26]_net_1\, - \counter_delta_snapshot[24]_net_1\, - counter_delta_f0_n12_0_0_a2_0, counter_delta_f0_n10_0_i_0, - counter_delta_f0lde_i_a2_0_1_3, - counter_delta_f0lde_i_a2_0_1_2, counter_delta_f0_1_0_a2_7, - N_273, counter_delta_f0_1_0_a2_2_0, - start_snapshot_f12_0_a2_7, start_snapshot_f12_0_a2_1, - start_snapshot_f12_0_a2_0, start_snapshot_f12_0_a2_4, - start_snapshot_f12_0_a2_6, N_113_i_i_0, N_112_i_i_0, - start_snapshot_f12_0_a2_3, N_108_i_i_0, N_83_i_i_0, - N_111_i_i_0, N_82_i_i_0, \start_snapshot_f2_temp\, - counter_delta_snapshot_e12_i_0_o2_m6_e_6, - counter_delta_snapshot_e12_i_0_o2_m6_e_4, - counter_delta_snapshot_e12_i_0_o2_m6_e_5, - counter_delta_snapshot_e12_i_0_o2_m6_e_2, - un12_start_snapshot_fothers_temp_NE_5, - un12_start_snapshot_fothers_temp_NE_4, - un12_start_snapshot_fothers_temp_NE_11, - un12_start_snapshot_fothers_temp_NE_1, - un12_start_snapshot_fothers_temp_NE_0, - un12_start_snapshot_fothers_temp_NE_9, N_506_i, N_166_i_i, - un12_start_snapshot_fothers_temp_NE_7, N_133_i_i, - N_132_i_i, un12_start_snapshot_fothers_temp_NE_3, N_509_i, - N_164_i_i, N_510_i, N_135_i_i, - un12_start_snapshot_fothers_temp_NE_RNO_8, N_137_i_i, - counter_delta_f0_1_0_a2_12, counter_delta_f0_1_0_a2_1_0, - counter_delta_f0_1_0_a2_9, counter_delta_f0_1_0_a2_11, - counter_delta_f0_1_0_a2_6, counter_delta_f0_1_0_a2_5, - counter_delta_f0_1_0_a2_10, counter_delta_f0_1_0_a2_5_0, - counter_delta_f0_1_0_a2_0, N_272, - counter_delta_f0_1_0_a2_8_0, counter_delta_f0_1_0_a2_8_1, - counter_delta_f0_1_0_a2_3, counter_delta_f0_1_0_a2_2, - un1_start_snapshot_f22_i_a2_0_4, - un1_start_snapshot_f22_i_a2_0_3, - start_snapshot_f22_0_a2_11_0_a2_0, - \counter_delta_snapshot[17]_net_1\, start_snapshot_f12, - N_322, N_19, N_275, N_22_i_0, N_503, N_501, N_26, N_287, - N_288, N_6, N_486, N_488, N_8, N_480, N_482, - \counter_delta_snapshot_RNO[10]_net_1\, N_476, N_477, - \counter_delta_snapshot_RNO[9]_net_1\, N_471, N_472, - \counter_delta_snapshot_RNO[7]_net_1\, N_462, N_463, - \counter_delta_snapshot_RNO[6]_net_1\, N_457, N_458, - N_376_i_0, N_453, N_452, N_375_i_0, N_448, N_447, - \counter_delta_snapshot_RNO[3]_net_1\, N_442, N_443, N_54, - N_437, N_438, \counter_delta_snapshot_RNO[1]_net_1\, - N_433, counter_delta_snapshot_e1_i_0, N_435, N_263, N_259, - N_255, N_252, \counter_delta_snapshot_RNO[0]_net_1\, - N_505, counter_delta_snapshot_e24, N_192, N_193, N_194, - counter_delta_snapshot_e23, N_404, - counter_delta_snapshot_e22, N_186, N_187, N_188, - counter_delta_snapshot_e21, N_402, - \counter_delta_snapshot_RNO[20]_net_1\, N_180, N_181, - N_182, N_20, N_400, - \counter_delta_snapshot_RNO[17]_net_1\, N_171, N_172, - N_173, \counter_delta_snapshot_RNO[16]_net_1\, N_397, - N_390, N_504, N_383, \counter_delta_snapshot[1]_net_1\, - \counter_delta_snapshot[20]_net_1\, counter_delta_f0_1, - N_174, N_405, N_468, N_498, - \counter_delta_snapshot_RNO[18]_net_1\, N_175, N_176, - counter_delta_snapshot_e25, N_406, - \counter_delta_snapshot_RNO[8]_net_1\, N_467, - \counter_delta_snapshot_RNO[12]_net_1\, N_496, N_284, - counter_delta_snapshot_e26_0_0_0_tz, N_9, - counter_delta_snapshot_e26, N_425, N_21, N_23, N_107_i_i, - N_227, N_114_i_i, N_228, N_115_i_i, counter_delta_f0_n12, - counter_delta_f0_n13, counter_delta_f0_n14, - counter_delta_f0_n15, counter_delta_f0_n16, - counter_delta_f0_n17, counter_delta_f0_n18, N_11, - N_87_i_i, N_17, N_324_i, N_99_i_i, N_89_i_i, N_15, N_13, - N_117_i_i, N_116_i_i, N_230, N_229, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - - \counter_delta_snapshot_RNO_1[11]\ : AOI1B - port map(A => counter_delta_snapshot_e11_i_0_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_294, Y - => counter_delta_snapshot_e11_i_0_0); - - \counter_delta_snapshot_RNO[21]\ : OAI1 - port map(A => N_402, B => N_504_0, C => - counter_delta_snapshot_e21_0_0_0, Y => - counter_delta_snapshot_e21); - - \counter_delta_snapshot[19]\ : DFN1C0 - port map(D => N_20, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[19]_net_1\); - - start_snapshot_f0_RNO_1 : NOR3A - port map(A => counter_delta_f0_1_0_a2_5_0, B => - counter_delta_f0_1_0_a2_0, C => N_272, Y => - counter_delta_f0_1_0_a2_10); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_6\ : NOR3C - port map(A => N_133_i_i, B => N_132_i_i, C => - un12_start_snapshot_fothers_temp_NE_3, Y => - un12_start_snapshot_fothers_temp_NE_9); - - \counter_delta_f0_RNO[14]\ : AO1C - port map(A => N_101, B => N_57_0, C => N_255, Y => - counter_delta_f0_n14); - - \op_eq.start_snapshot_f2_temp3_0_a2_RNO\ : OR2 - port map(A => start_snapshot_f22_11_i, B => - start_snapshot_f22_10, Y => - start_snapshot_f2_temp3_0_a2_0); - - \counter_delta_snapshot_RNO_0[17]\ : OR3C - port map(A => N_397, B => - \counter_delta_snapshot[17]_net_1\, C => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_171); - - \counter_delta_snapshot_RNIP067[1]\ : NOR2 - port map(A => \counter_delta_snapshot[1]_net_1\, B => - \counter_delta_snapshot[0]_net_1\, Y => N_382); - - \counter_delta_f0_RNITCA8[6]\ : NOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => - \counter_delta_f0[6]_net_1\, Y => - counter_delta_f0_1_0_a2_7); - - \counter_delta_snapshot_RNO_5[13]\ : OR2 - port map(A => \counter_delta_snapshot[13]_net_1\, B => - N_393, Y => counter_delta_snapshot_e13_i_0_a2_0); - - \counter_delta_snapshot_RNIKDF23[19]\ : OR3 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot[19]_net_1\, Y => N_400); - - coarse_time_0_r_RNIGJTR4_0 : OR2B - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => un2_coarse_time_0, Y => N_504); - - \counter_delta_snapshot_RNIV4TS1[13]\ : NOR2A - port map(A => N_393, B => - \counter_delta_snapshot[13]_net_1\, Y => N_394); - - \counter_delta_snapshot_RNO[19]\ : OAI1 - port map(A => N_400, B => N_504_0, C => - counter_delta_snapshot_e19_i_i_0, Y => N_20); - - \counter_delta_snapshot_RNO_1[2]\ : AO1A - port map(A => counter_delta_snapshot_e2_i_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_436, Y - => counter_delta_snapshot_e2_i_0); - - \counter_delta_f0_RNO[11]\ : XA1A - port map(A => N_67, B => \counter_delta_f0[11]_net_1\, C - => N_57_0, Y => N_275); - - \counter_delta_f0_RNO_0[4]\ : AX1B - port map(A => N_89, B => \counter_delta_f0[3]_net_1\, C => - \counter_delta_f0[4]_net_1\, Y => N_116_i_i); - - \counter_delta_f0_RNILJOA[20]\ : NOR3 - port map(A => \counter_delta_f0[14]_net_1\, B => - \counter_delta_f0[15]_net_1\, C => - \counter_delta_f0[20]_net_1\, Y => - counter_delta_f0_1_0_a2_3); - - \counter_delta_snapshot_RNO_1[12]\ : OR2 - port map(A => N_493, B => N_495, Y => - counter_delta_snapshot_e12_i_0_0); - - \counter_delta_snapshot_RNIIDER3[23]\ : OR3 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => - \counter_delta_snapshot[23]_net_1\, Y => N_404); - - \counter_delta_f0_RNO[26]\ : XA1 - port map(A => N_80, B => \counter_delta_f0[26]_net_1\, C - => N_57_0, Y => N_34); - - \counter_delta_snapshot_RNO_1[19]\ : OA1 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot[19]_net_1\, Y => - counter_delta_snapshot_e19_i_i_a2_0); - - coarse_time_0_r_RNILJMD : NOR2A - port map(A => coarse_time_0_c, B => \coarse_time_0_r\, Y - => un2_coarse_time_0); - - \counter_delta_snapshot_RNO[5]\ : OR3C - port map(A => N_453, B => counter_delta_snapshot_e5_i_0, C - => N_452, Y => N_376_i_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_11\ : XNOR2 - port map(A => \counter_delta_snapshot[3]_net_1\, B => - delta_snapshot(3), Y => N_506_i); - - \counter_delta_snapshot[16]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[16]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[16]_net_1\); - - \counter_delta_snapshot_RNIRV6E4_0[23]\ : OR3B - port map(A => \counter_delta_snapshot_e27_0_0_o2_m6_e_3\, B - => counter_delta_snapshot_e27_0_0_o2_m6_e_2, C => N_398, - Y => counter_delta_snapshot_e27_0_0_o2_N_7_0); - - \counter_delta_snapshot_RNO_0[20]\ : OR3C - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_180); - - \counter_delta_snapshot_RNIS3OS[7]\ : NOR2A - port map(A => N_387, B => \counter_delta_snapshot[7]_net_1\, - Y => N_388); - - start_snapshot_f22_0_a2_RNO : OR2 - port map(A => start_snapshot_f22_0_a2_0, B => - start_snapshot_f22_11_i, Y => start_snapshot_f22_0_a2_1); - - \counter_delta_snapshot_RNO_1[16]\ : OR2B - port map(A => counter_delta_snapshot_e16_i_i_a2_0, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_168); - - \counter_delta_snapshot_RNO_0[10]\ : NOR2 - port map(A => N_505, B => delta_snapshot(10), Y => N_476); - - \counter_delta_snapshot[25]\ : DFN1C0 - port map(D => counter_delta_snapshot_e25, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[25]_net_1\); - - \counter_delta_f0_RNO[7]\ : MX2 - port map(A => delta_f2_f0(7), B => N_89_i_i, S => N_57, Y - => N_13); - - \counter_delta_snapshot_RNO_2[13]\ : NOR2A - port map(A => counter_delta_snapshot_e13_i_0_a2_2_0, B => - N_504_0, Y => N_288); - - \counter_delta_snapshot_RNO_3[5]\ : OR2B - port map(A => counter_delta_snapshot_e5_i_a2_0, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_450); - - counter_delta_snapshot_e12_i_0_a2 : NOR2A - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => \counter_delta_snapshot_e12_i_0_a2_0\, Y => N_493); - - \counter_delta_snapshot[14]\ : DFN1C0 - port map(D => N_6, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[14]_net_1\); - - \counter_delta_snapshot_RNO_1[17]\ : OR2A - port map(A => \counter_delta_snapshot[17]_net_1\, B => - un2_coarse_time_0, Y => N_172); - - \counter_delta_f0[14]\ : DFN1E0C0 - port map(D => counter_delta_f0_n14, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[14]_net_1\); - - \counter_delta_snapshot_RNO_0[2]\ : NOR2 - port map(A => N_505, B => delta_snapshot(2), Y => N_437); - - \counter_delta_f0_RNO[18]\ : AO1B - port map(A => N_105, B => N_57, C => N_263, Y => - counter_delta_f0_n18); - - \counter_delta_snapshot_RNO[26]\ : AO1B - port map(A => counter_delta_snapshot_e26_0_0_0_tz, B => - \counter_delta_snapshot[26]_net_1\, C => N_425, Y => - counter_delta_snapshot_e26); - - \counter_delta_snapshot_RNO[17]\ : OR3C - port map(A => N_171, B => N_172, C => N_173, Y => - \counter_delta_snapshot_RNO[17]_net_1\); - - \counter_delta_snapshot[2]\ : DFN1C0 - port map(D => N_54, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[2]_net_1\); - - \counter_delta_f0_RNITVJ91[3]\ : NOR3A - port map(A => counter_delta_f0lde_i_a2_0_1_2, B => N_89, C - => \counter_delta_f0[3]_net_1\, Y => - counter_delta_f0lde_i_a2_0_1_3); - - \counter_delta_f0_RNIIVPK[4]\ : OR3 - port map(A => N_89, B => \counter_delta_f0[3]_net_1\, C => - \counter_delta_f0[4]_net_1\, Y => N_55); - - \counter_delta_snapshot_RNO_2[15]\ : NOR3B - port map(A => N_395, B => - \counter_delta_snapshot[15]_net_1\, C => N_504_0, Y => - N_482); - - \counter_delta_snapshot_RNI5NLF2[16]\ : OR2 - port map(A => \counter_delta_snapshot[16]_net_1\, B => - N_396, Y => N_397); - - \counter_delta_f0_RNIU25H2[20]\ : OR2 - port map(A => \counter_delta_f0[20]_net_1\, B => N_106, Y - => N_58); - - \counter_delta_snapshot_RNI71PA[2]\ : OR2A - port map(A => N_382, B => \counter_delta_snapshot[2]_net_1\, - Y => N_383); - - \counter_delta_snapshot_RNO_2[14]\ : NOR3B - port map(A => N_394, B => - \counter_delta_snapshot[14]_net_1\, C => N_504_0, Y => - N_488); - - \counter_delta_f0_RNO[20]\ : XA1A - port map(A => \counter_delta_f0[20]_net_1\, B => N_106, C - => N_57, Y => counter_delta_f0_n20); - - \counter_delta_snapshot_RNO_3[7]\ : NOR2A - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => counter_delta_snapshot_e7_i_a2_0, Y => N_460); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_5\ : NOR3C - port map(A => N_506_i, B => N_166_i_i, C => - un12_start_snapshot_fothers_temp_NE_7, Y => - un12_start_snapshot_fothers_temp_NE_11); - - \counter_delta_snapshot[21]\ : DFN1C0 - port map(D => counter_delta_snapshot_e21, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[21]_net_1\); - - \counter_delta_f0_RNIPJ57[22]\ : OR2 - port map(A => \counter_delta_f0[23]_net_1\, B => - \counter_delta_f0[22]_net_1\, Y => - counter_delta_f0_1_0_a2_2); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_15\ : XNOR2 - port map(A => \counter_delta_snapshot[12]_net_1\, B => - delta_snapshot(12), Y => N_132_i_i); - - \counter_delta_f0[15]\ : DFN1E0C0 - port map(D => counter_delta_f0_n15, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[15]_net_1\); - - \counter_delta_snapshot_RNO_2[11]\ : OR2 - port map(A => N_505, B => delta_snapshot(11), Y => N_501); - - \counter_delta_f0_RNIBRBK1[12]\ : OR3 - port map(A => N_67, B => \counter_delta_f0[11]_net_1\, C - => \counter_delta_f0[12]_net_1\, Y => N_99); - - \counter_delta_f0_RNI4JID2[19]\ : OR2A - port map(A => N_105, B => \counter_delta_f0[19]_net_1\, Y - => N_106); - - \counter_delta_snapshot_RNO[20]\ : OR3C - port map(A => N_180, B => N_181, C => N_182, Y => - \counter_delta_snapshot_RNO[20]_net_1\); - - \counter_delta_snapshot_RNO_1[10]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[10]_net_1\, C => N_474, Y => - counter_delta_snapshot_e10_i_0); - - \counter_delta_snapshot_RNO[25]\ : OAI1 - port map(A => N_406, B => N_504, C => - counter_delta_snapshot_e25_0_0_0, Y => - counter_delta_snapshot_e25); - - \op_eq.start_snapshot_f2_temp3_0_a2\ : NOR2 - port map(A => un12_start_snapshot_fothers_temp_NE, B => - start_snapshot_f2_temp3_0_a2_0, Y => - start_snapshot_f2_temp3); - - \counter_delta_f0_RNIDC4T[6]\ : OR3 - port map(A => N_55, B => \counter_delta_f0[5]_net_1\, C => - \counter_delta_f0[6]_net_1\, Y => N_59); - - \counter_delta_f0_RNO_0[14]\ : OAI1 - port map(A => N_99, B => \counter_delta_f0[13]_net_1\, C - => counter_delta_f0_n14_0_0_a2_0, Y => N_255); - - \counter_delta_snapshot_RNO[4]\ : NOR3C - port map(A => N_448, B => counter_delta_snapshot_e4_i_0, C - => N_447, Y => N_375_i_0); - - \counter_delta_snapshot[23]\ : DFN1C0 - port map(D => counter_delta_snapshot_e23, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[23]_net_1\); - - \counter_delta_snapshot_RNO_4[8]\ : NOR2 - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[8]_net_1\, Y => N_466); - - \counter_delta_snapshot_RNO[23]\ : OAI1 - port map(A => N_404, B => N_504_0, C => - counter_delta_snapshot_e23_0_0_0, Y => - counter_delta_snapshot_e23); - - \counter_delta_snapshot[17]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[17]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[17]_net_1\); - - \counter_delta_f0[4]\ : DFN1E0C0 - port map(D => N_229, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[4]_net_1\); - - \counter_delta_f0_RNIVJ67[16]\ : NOR2 - port map(A => \counter_delta_f0[16]_net_1\, B => - \counter_delta_f0[17]_net_1\, Y => - counter_delta_f0_1_0_a2_8_0); - - counter_delta_snapshot_e27_0_0_o2_m6_e_3 : NOR2 - port map(A => \counter_delta_snapshot[23]_net_1\, B => - \counter_delta_snapshot[22]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_3_i); - - \counter_delta_f0[13]\ : DFN1E0C0 - port map(D => counter_delta_f0_n13, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[13]_net_1\); - - \counter_delta_snapshot_RNO_2[12]\ : NOR3A - port map(A => \counter_delta_snapshot[12]_net_1\, B => - \counter_delta_snapshot_RNI0DDG1[7]_net_1\, C => N_504, Y - => N_498); - - \counter_delta_f0_RNO_0[10]\ : AX1D - port map(A => N_63, B => \counter_delta_f0[9]_net_1\, C => - \counter_delta_f0[10]_net_1\, Y => - counter_delta_f0_n10_0_i_0); - - \counter_delta_snapshot_RNO_2[19]\ : OR2A - port map(A => \counter_delta_snapshot[19]_net_1\, B => - un2_coarse_time_0, Y => N_178); - - \counter_delta_f0_RNO_0[3]\ : XNOR2 - port map(A => \counter_delta_f0[3]_net_1\, B => N_89, Y => - N_115_i_i); - - \counter_delta_f0_RNI4NHR1[14]\ : OR3 - port map(A => N_99, B => \counter_delta_f0[13]_net_1\, C - => \counter_delta_f0[14]_net_1\, Y => N_101); - - \counter_delta_snapshot_RNO_2[16]\ : NOR2B - port map(A => \counter_delta_snapshot[16]_net_1\, B => - N_396, Y => counter_delta_snapshot_e16_i_i_a2_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_13\ : XA1A - port map(A => delta_snapshot(6), B => - \counter_delta_snapshot[6]_net_1\, C => N_509_i, Y => - un12_start_snapshot_fothers_temp_NE_7); - - start_snapshot_fothers_temp : DFN1E0C0 - port map(D => N_7, CLK => HCLK_c, CLR => HRESETn_c, E => - N_284, Q => \start_snapshot_fothers_temp\); - - \counter_delta_snapshot_RNO_1[5]\ : OA1A - port map(A => \counter_delta_snapshot_i[5]\, B => - un2_coarse_time_0_0, C => N_450, Y => - counter_delta_snapshot_e5_i_0); - - \counter_delta_snapshot_RNO_2[17]\ : OR2 - port map(A => N_504, B => N_398, Y => N_173); - - \counter_delta_snapshot_RNO[7]\ : NOR3 - port map(A => N_462, B => counter_delta_snapshot_e7_i_0, C - => N_463, Y => \counter_delta_snapshot_RNO[7]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \counter_delta_snapshot[10]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[10]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[10]_net_1\); - - \counter_delta_f0_RNICPE51[8]\ : OR3 - port map(A => N_59, B => \counter_delta_f0[7]_net_1\, C => - \counter_delta_f0[8]_net_1\, Y => N_63); - - start_snapshot_f1_RNO_6 : XNOR2 - port map(A => \counter_delta_f0[4]_net_1\, B => - delta_f2_f1(4), Y => N_112_i_i_0); - - counter_delta_snapshot_e27_0_0_o2_m6_e_1_RNI4AT3 : AND2 - port map(A => start_snapshot_f22_0_a2_11_0_a2_3_i, B => - start_snapshot_f22_0_a2_11_0_a2_2_i, Y => - start_snapshot_f22_0_a2_11_0_a2_2_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_7\ : XNOR2 - port map(A => \counter_delta_snapshot[7]_net_1\, B => - delta_snapshot(7), Y => N_164_i_i); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \counter_delta_snapshot_RNO_0[6]\ : NOR2 - port map(A => N_505, B => delta_snapshot(6), Y => N_457); - - \counter_delta_f0_RNI3477[18]\ : NOR2 - port map(A => \counter_delta_f0[18]_net_1\, B => - \counter_delta_f0[19]_net_1\, Y => - counter_delta_f0_1_0_a2_8_1); - - \counter_delta_f0_RNI1DA8[8]\ : NOR2 - port map(A => \counter_delta_f0[8]_net_1\, B => - \counter_delta_f0[9]_net_1\, Y => - counter_delta_f0_1_0_a2_2_0); - - \counter_delta_snapshot[3]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[3]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[3]_net_1\); - - \counter_delta_f0_RNO_0[7]\ : XNOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => N_59, Y => - N_89_i_i); - - \counter_delta_f0_RNIU767[26]\ : OR2 - port map(A => \counter_delta_f0[26]_net_1\, B => - \counter_delta_f0[24]_net_1\, Y => - counter_delta_f0_1_0_a2_0); - - \counter_delta_snapshot_RNI2DD92[15]\ : OR2A - port map(A => N_395, B => - \counter_delta_snapshot[15]_net_1\, Y => N_396); - - \start_snapshot_f0\ : DFN1C0 - port map(D => counter_delta_f0_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => start_snapshot_f0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_3\ : XA1A - port map(A => delta_snapshot(2), B => - \counter_delta_snapshot[2]_net_1\, C => N_510_i, Y => - un12_start_snapshot_fothers_temp_NE_4); - - \counter_delta_snapshot[12]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[12]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[12]_net_1\); - - start_snapshot_f0_RNO_0 : NOR3B - port map(A => counter_delta_f0_1_0_a2_7, B => - counter_delta_f0_1_0_a2_6, C => counter_delta_f0_1_0_a2_5, - Y => counter_delta_f0_1_0_a2_11); - - \counter_delta_snapshot_RNO_0[0]\ : AXOI2 - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => un2_coarse_time_0_0, C => - \counter_delta_snapshot[0]_net_1\, Y => - counter_delta_snapshot_e0_i_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE\ : NAND2 - port map(A => un12_start_snapshot_fothers_temp_NE_12, B => - un12_start_snapshot_fothers_temp_NE_13, Y => - un12_start_snapshot_fothers_temp_NE); - - \counter_delta_snapshot_RNO_2[10]\ : NOR3A - port map(A => \counter_delta_snapshot[10]_net_1\, B => - N_390, C => N_504_0, Y => N_477); - - \counter_delta_snapshot_RNI0DDG1[7]\ : OR3B - port map(A => counter_delta_snapshot_e12_i_0_o2_m6_e_6, B - => counter_delta_snapshot_e12_i_0_o2_m6_e_5, C => N_383, - Y => \counter_delta_snapshot_RNI0DDG1[7]_net_1\); - - \counter_delta_f0_RNO[25]\ : XA1A - port map(A => N_66, B => \counter_delta_f0[25]_net_1\, C - => N_57, Y => N_32); - - \counter_delta_snapshot_RNO[12]\ : NOR3 - port map(A => N_496, B => counter_delta_snapshot_e12_i_0_0, - C => N_498, Y => \counter_delta_snapshot_RNO[12]_net_1\); - - start_snapshot_f2_temp : DFN1C0 - port map(D => start_snapshot_f2_temp3, CLK => HCLK_c, CLR - => HRESETn_c, Q => \start_snapshot_f2_temp\); - - \counter_delta_f0[20]\ : DFN1E0C0 - port map(D => counter_delta_f0_n20, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[20]_net_1\); - - start_snapshot_f1_RNO_7 : XA1A - port map(A => delta_f2_f1(2), B => - \counter_delta_f0[2]_net_1\, C => N_83_i_i_0, Y => - start_snapshot_f12_0_a2_3); - - \counter_delta_snapshot_RNO_4[13]\ : NOR2B - port map(A => \counter_delta_snapshot[13]_net_1\, B => - N_393, Y => counter_delta_snapshot_e13_i_0_a2_2_0); - - \counter_delta_snapshot_RNO_0[1]\ : NOR2 - port map(A => N_505, B => delta_snapshot(1), Y => N_433); - - \counter_delta_f0[17]\ : DFN1E0C0 - port map(D => counter_delta_f0_n17, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[17]_net_1\); - - \counter_delta_f0_RNO_0[26]\ : NOR2 - port map(A => \counter_delta_f0[25]_net_1\, B => N_66, Y - => N_80); - - \counter_delta_snapshot_RNO_4[15]\ : OR2 - port map(A => \counter_delta_snapshot[15]_net_1\, B => - N_395, Y => counter_delta_snapshot_e15_i_0_a2_0); - - counter_delta_snapshot_e12_i_0_a2_0 : NOR2 - port map(A => \counter_delta_snapshot[12]_net_1\, B => - un2_coarse_time_0_0, Y => N_495); - - \counter_delta_f0[2]\ : DFN1E0C0 - port map(D => N_227, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[2]_net_1\); - - \counter_delta_snapshot_RNO[18]\ : OR3C - port map(A => N_174, B => N_175, C => N_176, Y => - \counter_delta_snapshot_RNO[18]_net_1\); - - \counter_delta_snapshot_RNINLU74[25]\ : OR2A - port map(A => N_405, B => - \counter_delta_snapshot[25]_net_1\, Y => N_406); - - counter_delta_snapshot_e12_i_0_a2_RNO : OR2A - port map(A => \counter_delta_snapshot_RNI0DDG1[7]_net_1\, B - => \counter_delta_snapshot[12]_net_1\, Y => - \counter_delta_snapshot_e12_i_0_a2_0\); - - \counter_delta_f0_RNIJBBE[25]\ : NOR3 - port map(A => \counter_delta_f0[21]_net_1\, B => - \counter_delta_f0[25]_net_1\, C => - counter_delta_f0_1_0_a2_2, Y => - counter_delta_f0_1_0_a2_5_0); - - start_snapshot_f1_RNO_2 : XA1A - port map(A => delta_f2_f1(1), B => - \counter_delta_f0[1]_net_1\, C => N_111_i_i_0, Y => - start_snapshot_f12_0_a2_1); - - \counter_delta_snapshot_RNO_4[14]\ : OR2 - port map(A => \counter_delta_snapshot[14]_net_1\, B => - N_394, Y => counter_delta_snapshot_e14_i_0_a2_0); - - \counter_delta_f0[21]\ : DFN1E0C0 - port map(D => N_276, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[21]_net_1\); - - \counter_delta_f0_RNO[1]\ : MX2 - port map(A => delta_f2_f0(1), B => N_107_i_i, S => N_57_0, - Y => N_23); - - \counter_delta_snapshot_RNI9IOI_0[26]\ : NOR3 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - \counter_delta_snapshot[26]_net_1\, C => - \counter_delta_snapshot[24]_net_1\, Y => - \counter_delta_snapshot_e27_0_0_o2_m6_e_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_delta_snapshot_RNO_1[9]\ : AO1A - port map(A => counter_delta_snapshot_e9_i_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_470, Y - => counter_delta_snapshot_e9_i_0); - - \counter_delta_snapshot_RNO_4[2]\ : NOR2 - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[2]_net_1\, Y => N_436); - - start_snapshot_f0_RNO_4 : NOR2A - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[3]_net_1\, Y => - counter_delta_f0_1_0_a2_1_0); - - \counter_delta_snapshot_RNO_1[3]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[3]_net_1\, C => N_440, Y => - counter_delta_snapshot_e3_i_0); - - \counter_delta_snapshot_RNO_0[3]\ : NOR2 - port map(A => N_505, B => delta_snapshot(3), Y => N_442); - - \counter_delta_snapshot_RNI7OGC[16]\ : NOR2 - port map(A => \counter_delta_snapshot[16]_net_1\, B => - \counter_delta_snapshot[17]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_0); - - \counter_delta_snapshot_RNO_4[11]\ : OR2A - port map(A => \counter_delta_snapshot_i[11]\, B => - un2_coarse_time_0, Y => N_294); - - \counter_delta_snapshot_RNO_1[23]\ : OAI1 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => - counter_delta_snapshot_e23_0_0_a2_0, Y => N_189); - - \counter_delta_f0_RNIMF6D1[10]\ : OR3 - port map(A => N_63, B => \counter_delta_f0[9]_net_1\, C => - \counter_delta_f0[10]_net_1\, Y => N_67); - - \counter_delta_snapshot_RNIKFM14[24]\ : NOR2 - port map(A => \counter_delta_snapshot[24]_net_1\, B => - N_404, Y => N_405); - - \counter_delta_f0_RNO[16]\ : AO1C - port map(A => N_103, B => N_57, C => N_259, Y => - counter_delta_f0_n16); - - \counter_delta_f0_RNIRALB3[3]\ : AO1B - port map(A => counter_delta_f0lde_i_a2_0_1_3, B => N_322, C - => sample_f0_val_0, Y => N_9_tz); - - \counter_delta_f0_RNO[8]\ : MX2 - port map(A => delta_f2_f0(8), B => N_99_i_i, S => N_57, Y - => N_15); - - \counter_delta_snapshot_RNO_1[25]\ : OR2 - port map(A => counter_delta_snapshot_e25_0_0_a2_0, B => - N_405, Y => N_421); - - start_snapshot_f1_RNO_8 : XNOR2 - port map(A => \counter_delta_f0[3]_net_1\, B => - delta_f2_f1(3), Y => N_111_i_i_0); - - \counter_delta_snapshot_RNO[2]\ : NOR3 - port map(A => N_437, B => counter_delta_snapshot_e2_i_0, C - => N_438, Y => N_54); - - \counter_delta_snapshot[26]\ : DFN1C0 - port map(D => counter_delta_snapshot_e26, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[26]_net_1\); - - \start_snapshot_f1\ : DFN1C0 - port map(D => start_snapshot_f12, CLK => HCLK_c, CLR => - HRESETn_c, Q => start_snapshot_f1); - - \counter_delta_snapshot_RNIM1CE[3]\ : OR2 - port map(A => \counter_delta_snapshot[3]_net_1\, B => N_383, - Y => N_384); - - \counter_delta_snapshot_RNO_1[7]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[7]_net_1\, C => N_460, Y => - counter_delta_snapshot_e7_i_0); - - \counter_delta_snapshot_RNIV6LM1[12]\ : NOR2 - port map(A => \counter_delta_snapshot_RNI0DDG1[7]_net_1\, B - => \counter_delta_snapshot[12]_net_1\, Y => N_393); - - \counter_delta_f0_RNO[5]\ : MX2 - port map(A => delta_f2_f0(5), B => N_117_i_i, S => N_57, Y - => N_230); - - \counter_delta_snapshot_RNO_1[24]\ : OR2A - port map(A => \counter_delta_snapshot[24]_net_1\, B => - un2_coarse_time_0, Y => N_193); - - \counter_delta_snapshot_RNO[6]\ : NOR3 - port map(A => N_457, B => counter_delta_snapshot_e6_i_0, C - => N_458, Y => \counter_delta_snapshot_RNO[6]_net_1\); - - \counter_delta_snapshot[24]\ : DFN1C0 - port map(D => counter_delta_snapshot_e24, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[24]_net_1\); - - \counter_delta_snapshot_RNO_3[13]\ : NOR2A - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => counter_delta_snapshot_e13_i_0_a2_0, Y => N_285); - - \counter_delta_f0_RNO[4]\ : MX2 - port map(A => delta_f2_f0(4), B => N_116_i_i, S => N_57, Y - => N_229); - - \counter_delta_snapshot_RNO_3[3]\ : NOR3B - port map(A => N_383, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, C => - \counter_delta_snapshot[3]_net_1\, Y => N_440); - - \counter_delta_snapshot_RNI55U31[9]\ : OR2A - port map(A => N_389, B => \counter_delta_snapshot[9]_net_1\, - Y => N_390); - - \counter_delta_snapshot_RNO_1[21]\ : OAI1 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - counter_delta_snapshot_e21_0_0_a2_0, Y => N_183); - - start_snapshot_f1_RNO_9 : XNOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => - delta_f2_f1(7), Y => N_82_i_i_0); - - \counter_delta_snapshot_RNIG4B01[8]\ : NOR2A - port map(A => N_388, B => \counter_delta_snapshot[8]_net_1\, - Y => N_389); - - \counter_delta_f0[12]\ : DFN1E0C0 - port map(D => counter_delta_f0_n12, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[12]_net_1\); - - \counter_delta_f0_RNO_1[16]\ : NOR2B - port map(A => \counter_delta_f0[16]_net_1\, B => N_57_0, Y - => counter_delta_f0_n16_0_0_a2_0); - - \counter_delta_snapshot_RNO_3[15]\ : NOR2A - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => counter_delta_snapshot_e15_i_0_a2_0, Y => N_478); - - \counter_delta_snapshot_RNO_1[6]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[6]_net_1\, C => N_455, Y => - counter_delta_snapshot_e6_i_0); - - \counter_delta_f0_RNO[10]\ : NOR2A - port map(A => N_57_0, B => counter_delta_f0_n10_0_i_0, Y - => N_19); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_12\ : XNOR2 - port map(A => \counter_delta_snapshot[9]_net_1\, B => - delta_snapshot(9), Y => N_166_i_i); - - \counter_delta_snapshot_RNO_2[8]\ : NOR3B - port map(A => N_388, B => \counter_delta_snapshot[8]_net_1\, - C => N_504, Y => N_468); - - \counter_delta_f0_RNILRIL[10]\ : NOR3B - port map(A => counter_delta_f0_1_0_a2_8_0, B => - counter_delta_f0_1_0_a2_8_1, C => - counter_delta_f0_1_0_a2_5, Y => - un1_start_snapshot_f22_i_a2_0_3); - - \counter_delta_snapshot_RNO_3[14]\ : NOR2A - port map(A => counter_delta_snapshot_e27_0_0_o2_N_7_0, B - => counter_delta_snapshot_e14_i_0_a2_0, Y => N_484); - - counter_delta_snapshot_e26_0_0_a2_1 : VCC - port map(Y => N_425); - - \counter_delta_f0[3]\ : DFN1E0C0 - port map(D => N_228, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[3]_net_1\); - - \counter_delta_snapshot_RNO_0[8]\ : NOR2 - port map(A => N_505, B => delta_snapshot(8), Y => N_467); - - \counter_delta_f0_RNI2VU92[18]\ : NOR3 - port map(A => N_103, B => \counter_delta_f0[17]_net_1\, C - => \counter_delta_f0[18]_net_1\, Y => N_105); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_10\ : XNOR2 - port map(A => \counter_delta_snapshot[1]_net_1\, B => - delta_snapshot(1), Y => N_137_i_i); - - \counter_delta_snapshot_RNO_0[4]\ : OR3A - port map(A => \counter_delta_snapshot[4]_net_1\, B => N_384, - C => N_504, Y => N_448); - - \counter_delta_f0_RNO_0[8]\ : AX1B - port map(A => N_59, B => \counter_delta_f0[7]_net_1\, C => - \counter_delta_f0[8]_net_1\, Y => N_99_i_i); - - \counter_delta_f0[24]\ : DFN1E0C0 - port map(D => N_30, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[24]_net_1\); - - \counter_delta_snapshot_RNO_1[22]\ : OR2A - port map(A => \counter_delta_snapshot[22]_net_1\, B => - un2_coarse_time_0, Y => N_187); - - \counter_delta_f0_RNO[23]\ : XA1A - port map(A => N_62, B => \counter_delta_f0[23]_net_1\, C - => N_57, Y => N_28); - - \counter_delta_snapshot_RNO_3[11]\ : NOR2B - port map(A => \counter_delta_snapshot_i[11]\, B => N_391, Y - => counter_delta_snapshot_e11_i_0_a2_0); - - \counter_delta_snapshot_RNO_2[1]\ : NOR3A - port map(A => \counter_delta_snapshot[1]_net_1\, B => - \counter_delta_snapshot[0]_net_1\, C => N_504, Y => N_435); - - \counter_delta_f0_RNO_0[6]\ : AX1B - port map(A => N_55, B => \counter_delta_f0[5]_net_1\, C => - \counter_delta_f0[6]_net_1\, Y => N_87_i_i); - - \counter_delta_f0_RNIAF4P[20]\ : NOR3A - port map(A => counter_delta_f0_1_0_a2_3, B => - counter_delta_f0_1_0_a2_0, C => N_272, Y => - un1_start_snapshot_f22_i_a2_0_4); - - start_snapshot_f0_RNO_5 : NOR3C - port map(A => counter_delta_f0_1_0_a2_8_0, B => - counter_delta_f0_1_0_a2_8_1, C => - counter_delta_f0_1_0_a2_3, Y => counter_delta_f0_1_0_a2_9); - - \counter_delta_f0_RNO_0[2]\ : AX1B - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[1]_net_1\, C => - \counter_delta_f0[2]_net_1\, Y => N_114_i_i); - - \counter_delta_snapshot_RNO[22]\ : OR3C - port map(A => N_186, B => N_187, C => N_188, Y => - counter_delta_snapshot_e22); - - \counter_delta_snapshot_RNO[1]\ : NOR3 - port map(A => N_433, B => counter_delta_snapshot_e1_i_0, C - => N_435, Y => \counter_delta_snapshot_RNO[1]_net_1\); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_4\ : XA1A - port map(A => delta_snapshot(0), B => - \counter_delta_snapshot[0]_net_1\, C => N_137_i_i, Y => - un12_start_snapshot_fothers_temp_NE_0); - - \counter_delta_snapshot_RNO[14]\ : NOR3 - port map(A => N_486, B => counter_delta_snapshot_e14_i_0_0, - C => N_488, Y => N_6); - - start_snapshot_fothers_temp_RNI1HGO3 : NOR2B - port map(A => N_57_0, B => N_9_tz, Y => N_9_0); - - \counter_delta_snapshot_RNO_2[7]\ : NOR3B - port map(A => N_387, B => \counter_delta_snapshot[7]_net_1\, - C => N_504_0, Y => N_463); - - \counter_delta_f0_RNO[3]\ : MX2 - port map(A => delta_f2_f0(3), B => N_115_i_i, S => N_57_0, - Y => N_228); - - \counter_delta_snapshot_RNO_2[23]\ : NOR2B - port map(A => \counter_delta_snapshot[23]_net_1\, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, Y => - counter_delta_snapshot_e23_0_0_a2_0); - - \start_snapshot_f2\ : DFN1C0 - port map(D => N_7, CLK => HCLK_c, CLR => HRESETn_c, Q => - start_snapshot_f2); - - start_snapshot_fothers_temp_RNI66RC : OAI1 - port map(A => N_7, B => \start_snapshot_fothers_temp\, C - => sample_f2_val, Y => N_57_0); - - \counter_delta_snapshot_RNO_2[6]\ : NOR3A - port map(A => \counter_delta_snapshot[6]_net_1\, B => N_386, - C => N_504_0, Y => N_458); - - \counter_delta_f0_RNILEAO2[22]\ : OR3 - port map(A => N_58, B => \counter_delta_f0[21]_net_1\, C - => \counter_delta_f0[22]_net_1\, Y => N_62); - - \counter_delta_f0[25]\ : DFN1E0C0 - port map(D => N_32, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[25]_net_1\); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_1\ : XA1 - port map(A => delta_snapshot(5), B => - \counter_delta_snapshot_i[5]\, C => N_164_i_i, Y => - un12_start_snapshot_fothers_temp_NE_5); - - \counter_delta_snapshot_RNIRV6E4[23]\ : OR3B - port map(A => \counter_delta_snapshot_e27_0_0_o2_m6_e_3\, B - => counter_delta_snapshot_e27_0_0_o2_m6_e_2, C => N_398, - Y => \counter_delta_snapshot_RNIRV6E4[23]_net_1\); - - \counter_delta_snapshot_RNO_2[25]\ : OR2B - port map(A => \counter_delta_snapshot[25]_net_1\, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, Y => - counter_delta_snapshot_e25_0_0_a2_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_9\ : XNOR2 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - delta_snapshot(10), Y => N_510_i); - - \counter_delta_f0_RNO[9]\ : MX2 - port map(A => delta_f2_f0(9), B => N_324_i, S => N_57, Y - => N_17); - - \counter_delta_f0_RNINJ57[12]\ : OR2 - port map(A => \counter_delta_f0[13]_net_1\, B => - \counter_delta_f0[12]_net_1\, Y => N_272); - - \counter_delta_f0[16]\ : DFN1E0C0 - port map(D => counter_delta_f0_n16, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[16]_net_1\); - - \counter_delta_snapshot_RNO_2[24]\ : OR2A - port map(A => N_405, B => N_504, Y => N_194); - - \counter_delta_snapshot_RNIT7FC[21]\ : OR2 - port map(A => \counter_delta_snapshot[21]_net_1\, B => - \counter_delta_snapshot[20]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_1); - - start_snapshot_f0_RNO_3 : NOR3A - port map(A => N_273, B => \counter_delta_f0[2]_net_1\, C - => \counter_delta_f0[1]_net_1\, Y => - counter_delta_f0_1_0_a2_6); - - \counter_delta_snapshot_RNO_3[8]\ : OR2 - port map(A => \counter_delta_snapshot[8]_net_1\, B => N_388, - Y => counter_delta_snapshot_e8_i_a2_0); - - \counter_delta_snapshot_RNIN2IL[5]\ : OR2A - port map(A => \counter_delta_snapshot_i[5]\, B => N_385, Y - => N_386); - - \counter_delta_snapshot_RNO_3[9]\ : OR2 - port map(A => \counter_delta_snapshot[9]_net_1\, B => N_389, - Y => counter_delta_snapshot_e9_i_a2_0); - - \counter_delta_snapshot_RNO_2[3]\ : NOR3A - port map(A => \counter_delta_snapshot[3]_net_1\, B => N_383, - C => N_504, Y => N_443); - - \counter_delta_f0_RNO[19]\ : AO1C - port map(A => N_106, B => N_57, C => N_265, Y => - counter_delta_f0_n19); - - start_snapshot_f1_RNO_11 : XNOR2 - port map(A => \counter_delta_f0[8]_net_1\, B => - delta_f2_f1(8), Y => N_83_i_i_0); - - \counter_delta_f0_RNO_0[1]\ : XNOR2 - port map(A => \counter_delta_f0[1]_net_1\, B => - \counter_delta_f0[0]_net_1\, Y => N_107_i_i); - - \counter_delta_f0_RNIRIFC[2]\ : OR3 - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[1]_net_1\, C => - \counter_delta_f0[2]_net_1\, Y => N_89); - - \counter_delta_snapshot_RNO_2[21]\ : NOR2B - port map(A => \counter_delta_snapshot[21]_net_1\, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, Y => - counter_delta_snapshot_e21_0_0_a2_0); - - \counter_delta_snapshot[20]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[20]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[20]_net_1\); - - \counter_delta_f0_RNO_0[22]\ : AX1D - port map(A => N_58, B => \counter_delta_f0[21]_net_1\, C - => \counter_delta_f0[22]_net_1\, Y => N_86_i); - - \counter_delta_f0[0]\ : DFN1E0C0 - port map(D => N_21, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[0]_net_1\); - - \counter_delta_f0[23]\ : DFN1E0C0 - port map(D => N_28, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[23]_net_1\); - - \counter_delta_snapshot_RNI9KJK[7]\ : NOR3A - port map(A => counter_delta_snapshot_e12_i_0_o2_m6_e_4, B - => \counter_delta_snapshot[8]_net_1\, C => - \counter_delta_snapshot[7]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_6); - - \counter_delta_f0_RNO[22]\ : NOR2A - port map(A => N_57, B => N_86_i, Y => N_277); - - \counter_delta_f0[8]\ : DFN1E0C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[8]_net_1\); - - \counter_delta_snapshot_RNO_1[20]\ : OR2A - port map(A => \counter_delta_snapshot[20]_net_1\, B => - un2_coarse_time_0, Y => N_181); - - \counter_delta_snapshot_RNO_0[9]\ : NOR2 - port map(A => N_505, B => delta_snapshot(9), Y => N_471); - - \counter_delta_f0_RNO_1[18]\ : NOR2B - port map(A => \counter_delta_f0[18]_net_1\, B => N_57_0, Y - => counter_delta_f0_n18_0_0_a2_0); - - start_snapshot_f1_RNO : NOR3C - port map(A => start_snapshot_f12_0_a2_7, B => - start_snapshot_f12_0_a2_6, C => N_322, Y => - start_snapshot_f12); - - \counter_delta_f0_RNO[2]\ : MX2 - port map(A => delta_f2_f0(2), B => N_114_i_i, S => N_57_0, - Y => N_227); - - start_snapshot_f0_RNO_2 : NOR3C - port map(A => counter_delta_f0_1_0_a2_2_0, B => - counter_delta_f0_1_0_a2_1_0, C => - counter_delta_f0_1_0_a2_9, Y => - counter_delta_f0_1_0_a2_12); - - \counter_delta_snapshot_RNO_1[4]\ : OA1 - port map(A => \counter_delta_snapshot[4]_net_1\, B => - un2_coarse_time_0_0, C => N_445, Y => - counter_delta_snapshot_e4_i_0); - - \counter_delta_snapshot_RNIGN0H[11]\ : NOR3B - port map(A => \counter_delta_snapshot_i[11]\, B => - counter_delta_snapshot_e12_i_0_o2_m6_e_2, C => - \counter_delta_snapshot[3]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_5); - - \counter_delta_snapshot_RNIAA8V[23]\ : NOR3A - port map(A => \counter_delta_snapshot_e27_0_0_o2_m6_e_1\, B - => \counter_delta_snapshot[22]_net_1\, C => - \counter_delta_snapshot[23]_net_1\, Y => - \counter_delta_snapshot_e27_0_0_o2_m6_e_3\); - - coarse_time_0_r_RNIGJTR4 : OR2B - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => un2_coarse_time_0_0, Y => N_504_0); - - start_snapshot_f0_RNO : NOR3C - port map(A => counter_delta_f0_1_0_a2_11, B => - counter_delta_f0_1_0_a2_10, C => - counter_delta_f0_1_0_a2_12, Y => counter_delta_f0_1); - - \counter_delta_snapshot_RNO_2[22]\ : OR3 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => N_504, Y => - N_188); - - \counter_delta_snapshot_RNO[9]\ : NOR3 - port map(A => N_471, B => counter_delta_snapshot_e9_i_0, C - => N_472, Y => \counter_delta_snapshot_RNO[9]_net_1\); - - start_snapshot_f1_RNO_5 : XNOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => - delta_f2_f1(5), Y => N_113_i_i_0); - - \counter_delta_f0[1]\ : DFN1E0C0 - port map(D => N_23, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[1]_net_1\); - - \counter_delta_snapshot_RNI95UL2[17]\ : OR2 - port map(A => \counter_delta_snapshot[17]_net_1\, B => - N_397, Y => N_398); - - \counter_delta_snapshot[22]\ : DFN1C0 - port map(D => counter_delta_snapshot_e22, CLK => HCLK_c, - CLR => HRESETn_c, Q => \counter_delta_snapshot[22]_net_1\); - - \counter_delta_f0_RNO[15]\ : XA1A - port map(A => \counter_delta_f0[15]_net_1\, B => N_101, C - => N_57_0, Y => counter_delta_f0_n15); - - \counter_delta_f0[19]\ : DFN1E0C0 - port map(D => counter_delta_f0_n19, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[19]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \counter_delta_snapshot_RNO_0[5]\ : OR3 - port map(A => N_385, B => \counter_delta_snapshot_i[5]\, C - => N_504_0, Y => N_453); - - \counter_delta_f0_RNO[24]\ : NOR2A - port map(A => N_57, B => N_98_i, Y => N_30); - - \counter_delta_snapshot_RNO[3]\ : NOR3 - port map(A => N_442, B => counter_delta_snapshot_e3_i_0, C - => N_443, Y => \counter_delta_snapshot_RNO[3]_net_1\); - - \counter_delta_f0_RNO_0[16]\ : OAI1 - port map(A => N_101, B => \counter_delta_f0[15]_net_1\, C - => counter_delta_f0_n16_0_0_a2_0, Y => N_259); - - \counter_delta_snapshot[6]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[6]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[6]_net_1\); - - \counter_delta_f0[18]\ : DFN1E0C0 - port map(D => counter_delta_f0_n18, CLK => HCLK_c, CLR => - HRESETn_c, E => N_9_0, Q => \counter_delta_f0[18]_net_1\); - - \counter_delta_snapshot_RNO_3[10]\ : NOR3B - port map(A => N_390, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => - \counter_delta_snapshot[10]_net_1\, Y => N_474); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_8\ : XOR2 - port map(A => \counter_delta_snapshot_i[11]\, B => - delta_snapshot(11), Y => - un12_start_snapshot_fothers_temp_NE_RNO_8); - - start_snapshot_fothers_temp_RNI66RC_0 : OAI1 - port map(A => N_7, B => \start_snapshot_fothers_temp\, C - => sample_f2_val, Y => N_57); - - \counter_delta_f0[6]\ : DFN1E0C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[6]_net_1\); - - \counter_delta_snapshot[8]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[8]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[8]_net_1\); - - \counter_delta_snapshot_RNO_0[18]\ : OR3C - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_174); - - counter_delta_snapshot_e27_0_0_o2_m6_e_1_RNI8ATS : OR3B - port map(A => start_snapshot_f22_0_a2_11_0_a2_0, B => - start_snapshot_f22_0_a2_11_0_a2_2_0, C => - start_snapshot_f22_0_a2_11_0_a2_1, Y => - start_snapshot_f22_11_i); - - \counter_delta_snapshot_RNI2JDD[4]\ : NOR3 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - \counter_delta_snapshot[4]_net_1\, C => - \counter_delta_snapshot[9]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_4); - - start_snapshot_f1_RNO_0 : NOR3C - port map(A => start_snapshot_f12_0_a2_1, B => - start_snapshot_f12_0_a2_0, C => start_snapshot_f12_0_a2_4, - Y => start_snapshot_f12_0_a2_7); - - \counter_delta_f0_RNO[21]\ : XA1A - port map(A => N_58, B => \counter_delta_f0[21]_net_1\, C - => N_57, Y => N_276); - - \counter_delta_snapshot_RNO_4[7]\ : OR2 - port map(A => \counter_delta_snapshot[7]_net_1\, B => N_387, - Y => counter_delta_snapshot_e7_i_a2_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_17\ : XNOR2 - port map(A => \counter_delta_snapshot[8]_net_1\, B => - delta_snapshot(8), Y => N_509_i); - - \counter_delta_f0_RNIIM2T1[25]\ : NOR3C - port map(A => un1_start_snapshot_f22_i_a2_0_3, B => - counter_delta_f0_1_0_a2_5_0, C => - un1_start_snapshot_f22_i_a2_0_4, Y => N_322); - - \counter_delta_snapshot[4]\ : DFN1C0 - port map(D => N_375_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => \counter_delta_snapshot[4]_net_1\); - - \counter_delta_snapshot_RNI935P[6]\ : NOR2 - port map(A => \counter_delta_snapshot[6]_net_1\, B => N_386, - Y => N_387); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_0\ : NOR3C - port map(A => un12_start_snapshot_fothers_temp_NE_5, B => - un12_start_snapshot_fothers_temp_NE_4, C => - un12_start_snapshot_fothers_temp_NE_11, Y => - un12_start_snapshot_fothers_temp_NE_13); - - \counter_delta_snapshot_RNO[24]\ : OR3C - port map(A => N_192, B => N_193, C => N_194, Y => - counter_delta_snapshot_e24); - - \counter_delta_f0_RNO_1[12]\ : NOR2B - port map(A => \counter_delta_f0[12]_net_1\, B => N_57_0, Y - => counter_delta_f0_n12_0_0_a2_0); - - \counter_delta_f0_RNIJ357[10]\ : OR2 - port map(A => \counter_delta_f0[11]_net_1\, B => - \counter_delta_f0[10]_net_1\, Y => - counter_delta_f0_1_0_a2_5); - - \counter_delta_snapshot[15]\ : DFN1C0 - port map(D => N_8, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[15]_net_1\); - - \counter_delta_snapshot_RNO_1[1]\ : OA1C - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[0]_net_1\, C => - \counter_delta_snapshot[1]_net_1\, Y => - counter_delta_snapshot_e1_i_0); - - \counter_delta_snapshot_RNO_3[2]\ : OR2 - port map(A => \counter_delta_snapshot[2]_net_1\, B => N_382, - Y => counter_delta_snapshot_e2_i_a2_0); - - start_snapshot_fothers_temp_RNI1HGO3_0 : NOR2B - port map(A => N_57_0, B => N_9_tz, Y => N_9); - - \counter_delta_f0[9]\ : DFN1E0C0 - port map(D => N_17, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[9]_net_1\); - - \counter_delta_snapshot_RNO[0]\ : OA1B - port map(A => delta_snapshot(0), B => N_505, C => - counter_delta_snapshot_e0_i_0, Y => - \counter_delta_snapshot_RNO[0]_net_1\); - - start_snapshot_f1_RNO_10 : XNOR2 - port map(A => \counter_delta_f0[0]_net_1\, B => - delta_f2_f1(0), Y => N_108_i_i_0); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO\ : NOR3C - port map(A => un12_start_snapshot_fothers_temp_NE_1, B => - un12_start_snapshot_fothers_temp_NE_0, C => - un12_start_snapshot_fothers_temp_NE_9, Y => - un12_start_snapshot_fothers_temp_NE_12); - - \counter_delta_snapshot_RNO_2[20]\ : OR3 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => N_504, Y => - N_182); - - \counter_delta_snapshot_RNO_4[5]\ : NOR2B - port map(A => \counter_delta_snapshot_i[5]\, B => N_385, Y - => counter_delta_snapshot_e5_i_a2_0); - - \counter_delta_snapshot_RNO_1[18]\ : OR2A - port map(A => \counter_delta_snapshot[18]_net_1\, B => - un2_coarse_time_0, Y => N_175); - - \counter_delta_f0_RNO_0[9]\ : XNOR2 - port map(A => \counter_delta_f0[9]_net_1\, B => N_63, Y => - N_324_i); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_2\ : XA1A - port map(A => delta_snapshot(4), B => - \counter_delta_snapshot[4]_net_1\, C => - un12_start_snapshot_fothers_temp_NE_RNO_8, Y => - un12_start_snapshot_fothers_temp_NE_1); - - \counter_delta_snapshot_RNI62VH[4]\ : OR2 - port map(A => \counter_delta_snapshot[4]_net_1\, B => N_384, - Y => N_385); - - \counter_delta_snapshot[11]\ : DFN1P0 - port map(D => N_22_i_0, CLK => HCLK_c, PRE => HRESETn_c, Q - => \counter_delta_snapshot_i[11]\); - - \counter_delta_snapshot_RNO_4[9]\ : NOR2 - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[9]_net_1\, Y => N_470); - - \counter_delta_f0_RNO_0[5]\ : XNOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => N_55, Y => - N_117_i_i); - - \counter_delta_snapshot_RNI07532[14]\ : NOR2A - port map(A => N_394, B => - \counter_delta_snapshot[14]_net_1\, Y => N_395); - - \counter_delta_snapshot_RNO_1[8]\ : AO1A - port map(A => counter_delta_snapshot_e8_i_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_466, Y - => counter_delta_snapshot_e8_i_0); - - \counter_delta_snapshot_RNO_2[5]\ : OR2 - port map(A => N_505, B => delta_snapshot(5), Y => N_452); - - \counter_delta_snapshot_RNO[11]\ : OR3C - port map(A => N_503, B => counter_delta_snapshot_e11_i_0_0, - C => N_501, Y => N_22_i_0); - - \counter_delta_snapshot[18]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[18]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[18]_net_1\); - - \counter_delta_f0_RNO_0[19]\ : OR3B - port map(A => N_57_0, B => \counter_delta_f0[19]_net_1\, C - => N_105, Y => N_265); - - \counter_delta_f0_RNO_0[18]\ : OAI1 - port map(A => N_103, B => \counter_delta_f0[17]_net_1\, C - => counter_delta_f0_n18_0_0_a2_0, Y => N_263); - - \counter_delta_snapshot_RNO_2[2]\ : NOR3B - port map(A => N_382, B => \counter_delta_snapshot[2]_net_1\, - C => N_504, Y => N_438); - - \counter_delta_snapshot[13]\ : DFN1C0 - port map(D => N_26, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[13]_net_1\); - - \counter_delta_snapshot_RNO_2[4]\ : OR2 - port map(A => N_505, B => delta_snapshot(4), Y => N_447); - - \counter_delta_snapshot_RNI9IOI[26]\ : OR3 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - \counter_delta_snapshot[26]_net_1\, C => - \counter_delta_snapshot[24]_net_1\, Y => - start_snapshot_f22_10); - - \counter_delta_snapshot_RNI2N5A1[10]\ : OR2 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - N_390, Y => N_391); - - \counter_delta_f0_RNO[17]\ : XA1A - port map(A => \counter_delta_f0[17]_net_1\, B => N_103, C - => N_57, Y => counter_delta_f0_n17); - - \counter_delta_snapshot_RNI3167[5]\ : NOR2A - port map(A => \counter_delta_snapshot_i[5]\, B => - \counter_delta_snapshot[6]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_2); - - \counter_delta_snapshot_RNO_0[23]\ : OA1A - port map(A => \counter_delta_snapshot[23]_net_1\, B => - un2_coarse_time_0_0, C => N_189, Y => - counter_delta_snapshot_e23_0_0_0); - - \counter_delta_f0_RNO[13]\ : XA1A - port map(A => \counter_delta_f0[13]_net_1\, B => N_99, C - => N_57_0, Y => counter_delta_f0_n13); - - \counter_delta_snapshot_RNO_0[13]\ : NOR2 - port map(A => N_505, B => delta_snapshot(13), Y => N_287); - - \counter_delta_snapshot_RNO[8]\ : NOR3 - port map(A => N_467, B => counter_delta_snapshot_e8_i_0, C - => N_468, Y => \counter_delta_snapshot_RNO[8]_net_1\); - - \counter_delta_f0_RNO_0[24]\ : AX1D - port map(A => N_62, B => \counter_delta_f0[23]_net_1\, C - => \counter_delta_f0[24]_net_1\, Y => N_98_i); - - coarse_time_0_r_RNILJMD_0 : NOR2A - port map(A => coarse_time_0_c, B => \coarse_time_0_r\, Y - => un2_coarse_time_0_0); - - start_snapshot_f22_0_a2_RNO_0 : OR2 - port map(A => \start_snapshot_f2_temp\, B => - start_snapshot_f22_10, Y => start_snapshot_f22_0_a2_0); - - \counter_delta_f0_RNO[0]\ : MX2B - port map(A => delta_f2_f0(0), B => - \counter_delta_f0[0]_net_1\, S => N_57_0, Y => N_21); - - coarse_time_0_r_RNIGJTR4_1 : OR2A - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_505); - - \counter_delta_snapshot[1]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[1]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[1]_net_1\); - - \counter_delta_f0[22]\ : DFN1E0C0 - port map(D => N_277, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[22]_net_1\); - - \counter_delta_snapshot_RNO_0[25]\ : OA1A - port map(A => \counter_delta_snapshot[25]_net_1\, B => - un2_coarse_time_0_0, C => N_421, Y => - counter_delta_snapshot_e25_0_0_0); - - \counter_delta_f0_RNI13O22[16]\ : OR3 - port map(A => N_101, B => \counter_delta_f0[15]_net_1\, C - => \counter_delta_f0[16]_net_1\, Y => N_103); - - \counter_delta_snapshot_RNO_0[15]\ : NOR2 - port map(A => N_505, B => delta_snapshot(15), Y => N_480); - - \counter_delta_snapshot_RNO_0[24]\ : OR3C - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => \counter_delta_snapshot[24]_net_1\, C => N_404, Y - => N_192); - - \counter_delta_snapshot_RNO_0[14]\ : NOR2 - port map(A => N_505, B => delta_snapshot(14), Y => N_486); - - start_snapshot_fothers_temp_RNO : NOR3B - port map(A => N_322, B => counter_delta_f0lde_i_a2_0_1_3, C - => N_7, Y => N_284); - - \counter_delta_snapshot_RNIHLUE3[21]\ : OR3 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - \counter_delta_snapshot[21]_net_1\, Y => N_402); - - \counter_delta_snapshot_RNI8G0P[19]\ : NOR3 - port map(A => \counter_delta_snapshot[18]_net_1\, B => - \counter_delta_snapshot[19]_net_1\, C => - start_snapshot_f22_0_a2_11_0_a2_1, Y => - counter_delta_snapshot_e27_0_0_o2_m6_e_2); - - \counter_delta_snapshot_RNO[16]\ : OAI1 - port map(A => N_397, B => N_504_0, C => - counter_delta_snapshot_e16_i_i_0, Y => - \counter_delta_snapshot_RNO[16]_net_1\); - - \counter_delta_f0_RNIN6VO[4]\ : NOR3C - port map(A => counter_delta_f0_1_0_a2_7, B => N_273, C => - counter_delta_f0_1_0_a2_2_0, Y => - counter_delta_f0lde_i_a2_0_1_2); - - \counter_delta_f0[7]\ : DFN1E0C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[7]_net_1\); - - \counter_delta_snapshot_RNO_0[21]\ : OA1A - port map(A => \counter_delta_snapshot[21]_net_1\, B => - un2_coarse_time_0, C => N_183, Y => - counter_delta_snapshot_e21_0_0_0); - - \counter_delta_f0[5]\ : DFN1E0C0 - port map(D => N_230, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[5]_net_1\); - - coarse_time_0_r : DFN1C0 - port map(D => coarse_time_0_c, CLK => HCLK_c, CLR => - HRESETn_c, Q => \coarse_time_0_r\); - - \counter_delta_snapshot_RNO_4[4]\ : NOR2A - port map(A => N_384, B => \counter_delta_snapshot[4]_net_1\, - Y => counter_delta_snapshot_e4_i_a2_0); - - \counter_delta_snapshot_RNO_3[6]\ : NOR2A - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => counter_delta_snapshot_e6_i_a2_0, Y => N_455); - - counter_delta_snapshot_e27_0_0_o2_m6_e_1 : NOR2 - port map(A => \counter_delta_snapshot[19]_net_1\, B => - \counter_delta_snapshot[18]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_2_i); - - \counter_delta_f0[10]\ : DFN1E0C0 - port map(D => N_19, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[10]_net_1\); - - \counter_delta_snapshot_RNO_0[11]\ : OR3 - port map(A => N_391, B => \counter_delta_snapshot_i[11]\, C - => N_504_0, Y => N_503); - - \counter_delta_f0_RNO[6]\ : MX2 - port map(A => delta_f2_f0(6), B => N_87_i_i, S => N_57, Y - => N_11); - - start_snapshot_f22_0_a2 : NOR2 - port map(A => un12_start_snapshot_fothers_temp_NE, B => - start_snapshot_f22_0_a2_1, Y => N_7); - - \counter_delta_snapshot[5]\ : DFN1P0 - port map(D => N_376_i_0, CLK => HCLK_c, PRE => HRESETn_c, Q - => \counter_delta_snapshot_i[5]\); - - \counter_delta_f0_RNO_0[12]\ : OAI1 - port map(A => N_67, B => \counter_delta_f0[11]_net_1\, C - => counter_delta_f0_n12_0_0_a2_0, Y => N_252); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_14\ : XNOR2 - port map(A => \counter_delta_snapshot[13]_net_1\, B => - delta_snapshot(13), Y => N_133_i_i); - - \counter_delta_snapshot_RNO_3[4]\ : OR2B - port map(A => counter_delta_snapshot_e4_i_a2_0, B => - \counter_delta_snapshot_RNIRV6E4[23]_net_1\, Y => N_445); - - \counter_delta_snapshot_RNO_2[18]\ : OR3 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => N_504, Y => - N_176); - - \counter_delta_snapshot[0]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[0]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[0]_net_1\); - - \counter_delta_snapshot[7]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[7]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[7]_net_1\); - - \counter_delta_snapshot_RNO_1[13]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[13]_net_1\, C => N_285, Y => - counter_delta_snapshot_e13_i_0_0); - - start_snapshot_f1_RNO_1 : NOR3C - port map(A => N_113_i_i_0, B => N_112_i_i_0, C => - start_snapshot_f12_0_a2_3, Y => start_snapshot_f12_0_a2_6); - - \counter_delta_f0_RNIGAGV2[24]\ : OR3 - port map(A => N_62, B => \counter_delta_f0[23]_net_1\, C - => \counter_delta_f0[24]_net_1\, Y => N_66); - - \counter_delta_snapshot_RNO_2[9]\ : NOR3B - port map(A => N_389, B => \counter_delta_snapshot[9]_net_1\, - C => N_504_0, Y => N_472); - - \counter_delta_f0_RNIPCA8[4]\ : NOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => - \counter_delta_f0[4]_net_1\, Y => N_273); - - \counter_delta_f0_RNO[12]\ : AO1C - port map(A => N_99, B => N_57_0, C => N_252, Y => - counter_delta_f0_n12); - - \counter_delta_snapshot[9]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[9]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_delta_snapshot[9]_net_1\); - - \counter_delta_snapshot_RNO_1[15]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[15]_net_1\, C => N_478, Y => - counter_delta_snapshot_e15_i_0_0); - - \counter_delta_snapshot_RNO[10]\ : NOR3 - port map(A => N_476, B => counter_delta_snapshot_e10_i_0, C - => N_477, Y => \counter_delta_snapshot_RNO[10]_net_1\); - - \counter_delta_f0[11]\ : DFN1E0C0 - port map(D => N_275, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9_0, Q => \counter_delta_f0[11]_net_1\); - - \counter_delta_snapshot_RNO_0[22]\ : OR3C - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => \counter_delta_snapshot[22]_net_1\, C => N_402, Y - => N_186); - - start_snapshot_f1_RNO_4 : XA1A - port map(A => delta_f2_f1(9), B => - \counter_delta_f0[9]_net_1\, C => N_108_i_i_0, Y => - start_snapshot_f12_0_a2_4); - - \counter_delta_snapshot_RNO_0[12]\ : NOR2 - port map(A => N_505, B => delta_snapshot(12), Y => N_496); - - \counter_delta_snapshot_RNO[15]\ : NOR3 - port map(A => N_480, B => counter_delta_snapshot_e15_i_0_0, - C => N_482, Y => N_8); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_18\ : XNOR2 - port map(A => \counter_delta_snapshot[15]_net_1\, B => - delta_snapshot(15), Y => N_135_i_i); - - \counter_delta_snapshot_RNO_1[14]\ : AO1D - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[14]_net_1\, C => N_484, Y => - counter_delta_snapshot_e14_i_0_0); - - \counter_delta_f0_RNO_1[14]\ : NOR2B - port map(A => \counter_delta_f0[14]_net_1\, B => N_57_0, Y - => counter_delta_f0_n14_0_0_a2_0); - - \counter_delta_snapshot_RNO_0[19]\ : AOI1B - port map(A => counter_delta_snapshot_e19_i_i_a2_0, B => - counter_delta_snapshot_e27_0_0_o2_N_7_0, C => N_178, Y - => counter_delta_snapshot_e19_i_i_0); - - \counter_delta_f0[26]\ : DFN1E0C0 - port map(D => N_34, CLK => HCLK_c, CLR => HRESETn_c, E => - N_9, Q => \counter_delta_f0[26]_net_1\); - - \counter_delta_snapshot_RNO_4[6]\ : OR2A - port map(A => N_386, B => \counter_delta_snapshot[6]_net_1\, - Y => counter_delta_snapshot_e6_i_a2_0); - - \counter_delta_snapshot_RNO[13]\ : NOR3 - port map(A => N_287, B => counter_delta_snapshot_e13_i_0_0, - C => N_288, Y => N_26); - - \counter_delta_snapshot_RNO_0[7]\ : NOR2 - port map(A => N_505, B => delta_snapshot(7), Y => N_462); - - \counter_delta_snapshot_RNO_0[26]\ : AO1B - port map(A => \counter_delta_snapshot_RNIRV6E4[23]_net_1\, - B => N_406, C => un2_coarse_time_0, Y => - counter_delta_snapshot_e26_0_0_0_tz); - - \op_eq.un12_start_snapshot_fothers_temp_NE_RNO_16\ : XA1A - port map(A => delta_snapshot(14), B => - \counter_delta_snapshot[14]_net_1\, C => N_135_i_i, Y => - un12_start_snapshot_fothers_temp_NE_3); - - \counter_delta_snapshot_RNO_0[16]\ : OA1A - port map(A => \counter_delta_snapshot[16]_net_1\, B => - un2_coarse_time_0_0, C => N_168, Y => - counter_delta_snapshot_e16_i_i_0); - - start_snapshot_f1_RNO_3 : XA1A - port map(A => delta_f2_f1(6), B => - \counter_delta_f0[6]_net_1\, C => N_82_i_i_0, Y => - start_snapshot_f12_0_a2_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ is - - port( status_new_err : out std_logic_vector(3 to 3); - valid_ack : in std_logic_vector(3 to 3); - valid_out : out std_logic_vector(3 to 3); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f3_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1_i, N_6_i_i_0, \valid_out[3]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(3) <= \valid_out[3]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1_i, CLK => HCLK_c, CLR => - HRESETn_c, Q => status_new_err(3)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => \valid_out[3]\); - - error_RNO : NOR3B - port map(A => \valid_out[3]\, B => data_f3_out_valid, C => - valid_ack(3), Y => state_1_sqmuxa_1_i); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(3), B => \valid_out[3]\, C => - data_f3_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ is - - port( status_new_err : out std_logic_vector(1 to 1); - valid_out_i : out std_logic_vector(1 to 1); - valid_ack : in std_logic_vector(1 to 1); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f1_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out_i[1]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out_i(1) <= \valid_out_i[1]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => status_new_err(1)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1P0 - port map(D => N_6_i_i_0, CLK => HCLK_c, PRE => HRESETn_c, Q - => \valid_out_i[1]\); - - error_RNO : NOR3A - port map(A => data_f1_out_valid, B => valid_ack(1), C => - \valid_out_i[1]\, Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1D - port map(A => valid_ack(1), B => \valid_out_i[1]\, C => - data_f1_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_burst is - - port( sample_f3_wdata : in std_logic_vector(95 downto 0); - data_f3_out : out std_logic_vector(159 downto 64); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f3_out_valid : out std_logic; - enable_f3 : in std_logic; - sample_f3_val : in std_logic - ); - -end lpp_waveform_burst; - -architecture DEF_ARCH of lpp_waveform_burst is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal data_out_valid_3, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \data_out[91]\ : DFN1C0 - port map(D => sample_f3_wdata(27), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(91)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f3_wdata(60), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(124)); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f3_wdata(56), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(120)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f3_wdata(74), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(138)); - - \data_out[105]\ : DFN1C0 - port map(D => sample_f3_wdata(41), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(105)); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f3_wdata(62), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(126)); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f3_wdata(10), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(74)); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f3_wdata(90), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(154)); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f3_wdata(86), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(150)); - - \data_out[102]\ : DFN1C0 - port map(D => sample_f3_wdata(38), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(102)); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f3_wdata(92), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(156)); - - \data_out[93]\ : DFN1C0 - port map(D => sample_f3_wdata(29), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(93)); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f3_wdata(64), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(128)); - - data_out_valid : DFN1C0 - port map(D => data_out_valid_3, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out_valid); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f3_wdata(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(69)); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f3_wdata(77), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(141)); - - \data_out[99]\ : DFN1C0 - port map(D => sample_f3_wdata(35), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(99)); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f3_wdata(83), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(147)); - - \data_out[87]\ : DFN1C0 - port map(D => sample_f3_wdata(23), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(87)); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f3_wdata(85), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(149)); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_out[86]\ : DFN1C0 - port map(D => sample_f3_wdata(22), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(86)); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f3_wdata(94), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(158)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f3_wdata(49), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(113)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f3_wdata(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(65)); - - \data_out[95]\ : DFN1C0 - port map(D => sample_f3_wdata(31), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(95)); - - \data_out[92]\ : DFN1C0 - port map(D => sample_f3_wdata(28), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(92)); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f3_wdata(13), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(77)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f3_wdata(81), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(145)); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f3_wdata(67), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(131)); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f3_wdata(12), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(76)); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f3_wdata(73), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(137)); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f3_wdata(75), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(139)); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f3_wdata(50), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(114)); - - \data_out[80]\ : DFN1C0 - port map(D => sample_f3_wdata(16), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(80)); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f3_wdata(0), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(64)); - - \data_out[110]\ : DFN1C0 - port map(D => sample_f3_wdata(46), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(110)); - - \data_out[103]\ : DFN1C0 - port map(D => sample_f3_wdata(39), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(103)); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f3_wdata(78), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(142)); - - \data_out[94]\ : DFN1C0 - port map(D => sample_f3_wdata(30), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(94)); - - \data_out[88]\ : DFN1C0 - port map(D => sample_f3_wdata(24), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(88)); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f3_wdata(52), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(116)); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f3_wdata(57), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(121)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f3_wdata(63), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(127)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f3_wdata(65), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(129)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f3_wdata(71), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(135)); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f3_wdata(6), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(70)); - - data_out_valid_RNO : NOR2B - port map(A => sample_f3_val, B => enable_f3, Y => - data_out_valid_3); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f3_wdata(54), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(118)); - - \data_out[104]\ : DFN1C0 - port map(D => sample_f3_wdata(40), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(104)); - - \data_out[100]\ : DFN1C0 - port map(D => sample_f3_wdata(36), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(100)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f3_wdata(14), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(78)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f3_wdata(87), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(151)); - - GND_i : GND - port map(Y => \GND\); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f3_wdata(93), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(157)); - - \data_out[106]\ : DFN1C0 - port map(D => sample_f3_wdata(42), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(106)); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f3_wdata(95), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(159)); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f3_wdata(68), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(132)); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f3_wdata(61), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(125)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f3_wdata(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(67)); - - \data_out[81]\ : DFN1C0 - port map(D => sample_f3_wdata(17), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(81)); - - \data_out[97]\ : DFN1C0 - port map(D => sample_f3_wdata(33), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(97)); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f3_wdata(2), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(66)); - - \data_out[108]\ : DFN1C0 - port map(D => sample_f3_wdata(44), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(108)); - - \data_out[96]\ : DFN1C0 - port map(D => sample_f3_wdata(32), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(96)); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f3_wdata(79), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(143)); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f3_wdata(58), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(122)); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f3_wdata(91), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(155)); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f3_wdata(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(71)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f3_wdata(88), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(152)); - - \data_out[83]\ : DFN1C0 - port map(D => sample_f3_wdata(19), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(83)); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f3_wdata(80), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(144)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f3_wdata(76), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(140)); - - \data_out[111]\ : DFN1C0 - port map(D => sample_f3_wdata(47), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(111)); - - \data_out[90]\ : DFN1C0 - port map(D => sample_f3_wdata(26), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(90)); - - \data_out[89]\ : DFN1C0 - port map(D => sample_f3_wdata(25), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(89)); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f3_wdata(4), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(68)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f3_wdata(53), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(117)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f3_wdata(82), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(146)); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f3_wdata(69), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(133)); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f3_wdata(55), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(119)); - - \data_out[98]\ : DFN1C0 - port map(D => sample_f3_wdata(34), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(98)); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f3_wdata(9), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(73)); - - \data_out[85]\ : DFN1C0 - port map(D => sample_f3_wdata(21), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(85)); - - \data_out[82]\ : DFN1C0 - port map(D => sample_f3_wdata(18), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(82)); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f3_wdata(15), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(79)); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f3_wdata(84), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(148)); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f3_wdata(59), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(123)); - - \data_out[101]\ : DFN1C0 - port map(D => sample_f3_wdata(37), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(101)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f3_wdata(70), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(134)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f3_wdata(51), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(115)); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f3_wdata(66), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(130)); - - \data_out[107]\ : DFN1C0 - port map(D => sample_f3_wdata(43), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(107)); - - \data_out[109]\ : DFN1C0 - port map(D => sample_f3_wdata(45), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(109)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f3_wdata(72), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(136)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[84]\ : DFN1C0 - port map(D => sample_f3_wdata(20), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(84)); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f3_wdata(11), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(75)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f3_wdata(8), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(72)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f3_wdata(89), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(153)); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f3_wdata(48), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f3_out(112)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ is - - port( status_new_err : out std_logic_vector(2 to 2); - valid_ack : in std_logic_vector(2 to 2); - valid_out : out std_logic_vector(2 to 2); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f2_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out[2]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(2) <= \valid_out[2]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => status_new_err(2)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => \valid_out[2]\); - - error_RNO : NOR3B - port map(A => \valid_out[2]\, B => data_f2_out_valid, C => - valid_ack(2), Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(2), B => \valid_out[2]\, C => - data_f2_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ is - - port( status_new_err : out std_logic_vector(0 to 0); - valid_ack : in std_logic_vector(0 to 0); - valid_out : out std_logic_vector(0 to 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f0_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out[0]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(0) <= \valid_out[0]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => status_new_err(0)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => HCLK_c, CLR => HRESETn_c, Q - => \valid_out[0]\); - - error_RNO : NOR3B - port map(A => \valid_out[0]\, B => data_f0_out_valid, C => - valid_ack(0), Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(0), B => \valid_out[0]\, C => - data_f0_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ1 is - - port( ready_i_0 : out std_logic_vector(1 to 1); - Raddr_vect_RNICA1PH : out std_logic_vector(1 to 1); - data_mem_wen_i_0 : inout std_logic_vector(2 downto 1) := (others => 'Z'); - Raddr_vect_RNIIMQ5I : out std_logic_vector(4 to 4); - Raddr_vect_RNIE6Q5I : out std_logic_vector(3 to 3); - Raddr_vect_RNIKA2PH : out std_logic_vector(2 to 2); - data_addr_r_iv_i_3 : in std_logic_vector(4 downto 0); - Raddr_vect_RNI4A0PH : out std_logic_vector(0 to 0); - data_addr_r_iv_i_a2_2 : in std_logic_vector(4 to 4); - data_wen : in std_logic_vector(1 to 1); - data_mem_ren_i_0 : inout std_logic_vector(1 downto 0) := (others => 'Z'); - data_ren : in std_logic_vector(1 to 1); - data_ren_1z : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_166 : out std_logic; - N_126 : out std_logic; - N_150 : out std_logic; - N_134 : out std_logic; - N_142 : out std_logic; - N_165 : in std_logic; - N_158 : out std_logic; - un20_time_write : in std_logic; - N_68 : in std_logic; - N_164 : in std_logic; - N_120_i : out std_logic; - N_44 : in std_logic; - N_52 : in std_logic; - N_60 : in std_logic; - N_76 : in std_logic; - N_86 : out std_logic; - N_75 : in std_logic; - N_59 : in std_logic; - N_51 : in std_logic; - N_43 : in std_logic; - N_67 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ1; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ1 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \data_mem_addr_w_1[1]\, \data_mem_addr_w_1[0]\, - N_4, \data_mem_addr_w_1[3]\, \DWACT_FINC_E[0]\, N_12_0, - \data_mem_addr_r_1[1]\, \data_mem_addr_r_1[0]\, N_4_0, - \data_mem_addr_r_1[3]\, \DWACT_FINC_E_0[0]\, - \un26_sfull_s\, \un26_sfull_s_tz\, \sFull\, un5_sfull_s_4, - \data_addr_r_iv_i_4[1]\, \data_addr_r_iv_i_4[4]\, - \data_mem_addr_r_1[4]\, \data_addr_r_iv_i_4[3]\, - \data_addr_r_iv_i_4[2]\, \data_mem_addr_r_1[2]\, - \data_addr_r_iv_i_4[0]\, \data_addr_r_iv_i_a2_3[4]\, - un7_sempty_s_4, un7_sempty_s_1, un7_sempty_s_0, - un7_sempty_s_2, \un10_raddr_vect_s[3]\, sEmpty_RNO_7_0, - \un10_raddr_vect_s[1]\, sEmpty_RNO_6_2, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \un8_waddr_vect_s[3]\, \un26_sfull_s_tz_RNO_7\, - un5_sfull_s_4_1, \un8_waddr_vect_s[1]\, - \un26_sfull_s_tz_RNO_4\, un5_sfull_s_4_0, - \un8_waddr_vect_s[0]\, ADD_5x5_fast_I11_Y_i_a2_0, - \data_mem_addr_w_1[2]\, N_109, ADD_5x5_fast_I11_Y_0, - N_89_i, N80, SUM2_0_0, ADD_5x5_fast_I11_un1_Y_0, N81, - N_85_i, N_105_1, ADD_7x7_fast_I19_Y_i_o4_1_0, N_87, - un1_waddr_vect_slto3_0, un2_raddr_vect_slto3_0, - un1_waddr_vect_slt4, \un60_ready1[4]\, CO1_tz, N_12_1, - N_17, N_18, I11_un1_Y, un7_sempty_s, Waddr_vect_n4, - \data_mem_addr_w_1[4]\, Waddr_vect_14_0, Waddr_vect_c2, - Waddr_vect_n2, un1_waddr_vect_s, Waddr_vect_n2_tz, - Waddr_vect_n3, N_9, N165, N_14_1, N_23, N_75_i_0, - \un75_ready1[4]\, ADD_5x5_fast_I8_un1_Y_0, - \un75_ready0_1[4]\, \un60_ready0[4]\, N_13, - \un75_ready0[4]\, un62_readylto4, un77_ready, un69_ready, - N_198, N107, N161, N_197, \un75_ready1[5]\, N_16_i_i_0, - N_196, N83, un2_raddr_vect_slto1, un2_raddr_vect_s, - Waddr_vect_e0, Waddr_vect_e1, Waddr_vect_n1_i, - Waddr_vect_e4, Waddr_vect_e2, I_20_9, I_9_17, - \un10_raddr_vect_s[4]\, \un10_raddr_vect_s[2]\, - Waddr_vect_e3, I_13_17, I_5_17, I_20_10, I_13_18, I_9_18, - I_5_18, sEmpty_RNO_11, un1_sempty_s, \sEmpty\, N_9_0, - N_13_0, N_12_2, N_11, N_8, N_10, N_9_1, N_7, N_4_1, N_5, - N_6, N_9_2, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - sFull : DFN1C0 - port map(D => \un26_sfull_s\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Raddr_vect_RNICA1PH[1]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[1]\, B => - data_addr_r_iv_i_3(1), C => N_68, Y => - Raddr_vect_RNICA1PH(1)); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => data_mem_wen_i_0(1), C - => \data_mem_addr_w_1[0]\, Y => Waddr_vect_e0); - - \Raddr_vect_RNIA2FB1[0]\ : MX2 - port map(A => \un60_ready1[4]\, B => \un60_ready0[4]\, S - => \data_mem_addr_r_1[0]\, Y => un62_readylto4); - - un75_ready_1_16_ADD_5x5_fast_I8_un1_Y : NOR3A - port map(A => N81, B => N_85_i, C => N_105_1, Y => - ADD_5x5_fast_I8_un1_Y_0); - - \Raddr_vect_RNI7873[3]\ : XNOR2 - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, Y => N_87); - - \Waddr_vect_RNIIOD6[0]\ : AO1B - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => un1_waddr_vect_slto3_0, Y - => un1_waddr_vect_slt4); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[0]\); - - sEmpty_RNIANF32 : NOR3A - port map(A => data_ren_1z, B => un20_time_write, C => - \sEmpty\, Y => data_mem_ren_i_0(1)); - - \Waddr_vect_RNO[3]\ : MX2A - port map(A => Waddr_vect_n3, B => \data_mem_addr_w_1[3]\, S - => data_mem_wen_i_0(1), Y => Waddr_vect_e3); - - un26_sfull_s_tz_RNO_5 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_1[0]\, - Y => \un8_waddr_vect_s[0]\); - - \Raddr_vect_RNI3O63[1]\ : NOR2A - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, Y => N_105_1); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_r_1[0]\, Y => N_12_0); - - un26_sfull_s_tz_RNO_3 : OR2B - port map(A => I_5_17, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - \ready_gen.un69_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_1[4]\, B => - \data_mem_addr_r_1[4]\, Y => N_11); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, Y => I_5_17); - - sEmpty_RNO_0 : NOR3B - port map(A => data_ren_1z, B => un7_sempty_s_4, C => - un20_time_write, Y => un7_sempty_s); - - \Waddr_vect_RNIE4CV[3]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[3]\, Y => N_134); - - un60_ready_1_1_0_SUM2_0 : AX1C - port map(A => N_87, B => CO1_tz, C => SUM2_0_0, Y => - \un60_ready1[4]\); - - \Raddr_vect_RNIU7FE[4]\ : NOR2B - port map(A => I_13_18, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un26_sfull_s_tz_RNO_6 : OR2B - port map(A => I_13_17, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Raddr_vect_RNI0G18[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_1[4]\, Y => - un2_raddr_vect_s); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, C => \data_mem_addr_r_1[2]\, Y - => N_9_0); - - \Raddr_vect_RNIB44A2[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_1[0]\, - Y => N_198); - - \ready_gen.un69_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, Y => N_5); - - \ready_gen.un69_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, C => N_4_1, Y => N_10); - - \Raddr_vect_RNIK66A4[1]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[1]\, C => N_67, Y => - \data_addr_r_iv_i_4[1]\); - - \Waddr_vect_RNO[4]\ : MX2A - port map(A => Waddr_vect_n4, B => \data_mem_addr_w_1[4]\, S - => data_mem_wen_i_0(1), Y => Waddr_vect_e4); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[1]\); - - un75_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : XOR2 - port map(A => N165, B => \un75_ready0_1[4]\, Y => - \un75_ready0[4]\); - - un60_ready_0_0_0_ADD_5x5_fast_I9_Y_i_o2 : AO13 - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => \data_mem_addr_r_1[1]\, Y - => N_9); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_2, B => \data_mem_addr_w_1[3]\, Y => - I_13_17); - - sFull_RNI8GOT : OR2B - port map(A => data_mem_wen_i_0(1), B => N_165, Y => N_166); - - GND_i : GND - port map(Y => \GND\); - - sEmpty_RNO_7 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_1[4]\, Y => sEmpty_RNO_7_0); - - sEmpty_RNIGNUI8 : NOR2B - port map(A => \data_addr_r_iv_i_a2_3[4]\, B => - data_addr_r_iv_i_a2_2(4), Y => N_86); - - \Raddr_vect_RNIT38B[4]\ : NOR2B - port map(A => I_5_18, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - un26_sfull_s_tz_RNO_0 : XA1 - port map(A => \data_mem_addr_r_1[1]\, B => - \un8_waddr_vect_s[1]\, C => \un26_sfull_s_tz_RNO_4\, Y - => un5_sfull_s_4_1); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => N_9_2); - - \Raddr_vect_RNI5073[2]\ : XNOR2 - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, Y => N_85_i); - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[2]\); - - un60_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0 : OR2A - port map(A => \data_mem_addr_r_1[3]\, B => - \data_mem_addr_w_1[3]\, Y => N_13); - - sEmpty_RNIJEV64 : NOR2 - port map(A => data_mem_ren_i_0(1), B => data_mem_ren_i_0(0), - Y => \data_addr_r_iv_i_a2_3[4]\); - - \ready_gen.un69_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_1[4]\, B => - \data_mem_addr_w_1[4]\, Y => N_7); - - un75_ready_1_16_ADD_5x5_fast_I1_P0N : OR2A - port map(A => \data_mem_addr_r_1[2]\, B => N_87, Y => N81); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_1 : OA1C - port map(A => N165, B => N_89_i, C => N_23, Y => N_14_1); - - un60_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3_0 : NOR2B - port map(A => N_9, B => \data_mem_addr_w_1[2]\, Y => N_18); - - \Waddr_vect_RNO_0[4]\ : AXO1 - port map(A => un1_waddr_vect_slt4, B => - \data_mem_addr_w_1[4]\, C => Waddr_vect_14_0, Y => - Waddr_vect_n4); - - sFull_RNIBVR9 : OR2 - port map(A => \sFull\, B => data_wen(1), Y => - data_mem_wen_i_0(1)); - - \Raddr_vect_RNIT3LC6[0]\ : AOI1 - port map(A => N_197, B => N_196, C => N_198, Y => - un77_ready); - - \Raddr_vect_RNI9G73_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_1[4]\, B => - \data_mem_addr_w_1[4]\, Y => N_75_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR2B - port map(A => N_14_1, B => N_75_i_0, Y => N161); - - un75_ready_1_16_ADD_5x5_fast_I2_G0N : OR2 - port map(A => N_109, B => N_89_i, Y => N83); - - sEmpty_RNO : OR2 - port map(A => un7_sempty_s, B => un1_sempty_s, Y => - sEmpty_RNO_11); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[3]\); - - un26_sfull_s : AND2 - port map(A => data_ren(1), B => \un26_sfull_s_tz\, Y => - \un26_sfull_s\); - - \Waddr_vect_RNIB473[3]\ : NOR2 - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_w_1[2]\, Y => un1_waddr_vect_slto3_0); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, Y => N_12); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_1[1]\, B => - \un10_raddr_vect_s[1]\, C => sEmpty_RNO_6_2, Y => - un7_sempty_s_1); - - un26_sfull_s_tz_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_17, C => - \data_mem_addr_r_1[2]\, Y => \un26_sfull_s_tz_RNO_4\); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4 : AO1B - port map(A => ADD_7x7_fast_I19_Y_i_o4_1_0, B => N_9, C => - N80, Y => N165); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_1[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[4]\); - - \ready_gen.un69_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, C => N_6, Y => N_8); - - \Raddr_vect_RNIOM6A4[3]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[3]\, C => N_51, Y => - \data_addr_r_iv_i_4[3]\); - - \Raddr_vect_RNIE6Q5I[3]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[3]\, B => - data_addr_r_iv_i_3(3), C => N_52, Y => - Raddr_vect_RNIE6Q5I(3)); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - \Raddr_vect_RNI003G[4]\ : NOR2B - port map(A => I_20_10, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXOI5 - port map(A => N_87, B => \data_mem_addr_r_1[2]\, C => - \data_mem_addr_w_1[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - \ready_gen.un69_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, C => N_7, Y => N_12_2); - - un26_sfull_s_tz : OR2 - port map(A => \sFull\, B => un5_sfull_s_4, Y => - \un26_sfull_s_tz\); - - un75_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_14_1, B => N83, C => N_75_i_0, Y => - N_16_i_i_0); - - \Waddr_vect_RNID0CV[2]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[2]\, Y => N_142); - - \Raddr_vect_RNIKA2PH[2]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[2]\, B => - data_addr_r_iv_i_3(2), C => N_60, Y => - Raddr_vect_RNIKA2PH(2)); - - \Raddr_vect_RNIUNK9[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_1[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[0]\); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_1[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Raddr_vect_RNI9G73[4]\ : XNOR2 - port map(A => \data_mem_addr_w_1[4]\, B => - \data_mem_addr_r_1[4]\, Y => N_89_i); - - \Waddr_vect_RNIF8CV[4]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[4]\, Y => N_126); - - \Raddr_vect_RNIIU5A4[0]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[0]\, C => N_75, Y => - \data_addr_r_iv_i_4[0]\); - - \Raddr_vect_RNION3L8[0]\ : MX2 - port map(A => un62_readylto4, B => un77_ready, S => - un69_ready, Y => ready_i_0(1)); - - un60_ready_1_1_0_SUM2_0_0 : XNOR2 - port map(A => N_109, B => N_89_i, Y => SUM2_0_0); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_1[2]\, Y => - I_9_18); - - \ready_gen.un69_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, Y => N_4_1); - - \Raddr_vect_RNITJ63[1]\ : OR2B - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_r_1[0]\, Y => un2_raddr_vect_slto1); - - un75_ready_0_0_0_ADD_7x7_fast_I32_Y_0_1 : XOR2 - port map(A => N_109, B => N_89_i, Y => \un75_ready0_1[4]\); - - un60_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2 : OR3 - port map(A => N_17, B => ADD_5x5_fast_I11_Y_i_a2_0, C => - N_18, Y => N_12_1); - - un75_ready_1_16_ADD_5x5_fast_I10_Y : OR3A - port map(A => N_75_i_0, B => I11_un1_Y, C => - ADD_5x5_fast_I11_Y_0, Y => N107); - - \Waddr_vect_RNICSBV[1]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[1]\, Y => N_150); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4 : NOR3B - port map(A => N_9, B => ADD_7x7_fast_I19_Y_i_o4_1_0, C => - N_109, Y => N_23); - - un26_sfull_s_tz_RNO : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, C => \data_mem_addr_r_1[2]\, Y - => \DWACT_FINC_E_0[0]\); - - \Raddr_vect_RNIN2UH1[0]\ : MX2C - port map(A => \un75_ready1[4]\, B => \un75_ready0[4]\, S - => \data_mem_addr_r_1[0]\, Y => N_196); - - \Waddr_vect_RNIC4Q4[0]\ : NOR3C - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => Waddr_vect_c2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_1[3]\, Y - => Waddr_vect_14_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \Waddr_vect_RNIPG18[4]\ : OR2B - port map(A => un1_waddr_vect_slt4, B => - \data_mem_addr_w_1[4]\, Y => un1_waddr_vect_s); - - un75_ready_1_16_ADD_5x5_fast_I11_un1_Y_0 : NOR3A - port map(A => N81, B => N_85_i, C => N_105_1, Y => - ADD_5x5_fast_I11_un1_Y_0); - - un26_sfull_s_tz_RNO_7 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_9, C => - \data_mem_addr_r_1[4]\, Y => \un26_sfull_s_tz_RNO_7\); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_1[4]\, Y => I_20_9); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[1]\); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_1[2]\, Y => sEmpty_RNO_6_2); - - \Raddr_vect_RNIQU6A4[4]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[4]\, C => N_43, Y => - \data_addr_r_iv_i_4[4]\); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9_0, B => \data_mem_addr_r_1[3]\, Y => - I_13_18); - - un26_sfull_s_tz_RNO_1 : XA1B - port map(A => \data_mem_addr_r_1[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(1), Y => - un5_sfull_s_4_0); - - \ready_gen.un69_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_1, Y => N_13_0); - - \ready_gen.un69_ready_0_I_11\ : OA1 - port map(A => N_13_0, B => N_12_2, C => N_11, Y => - un69_ready); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \data_mem_addr_w_1[2]\, S - => data_mem_wen_i_0(1), Y => Waddr_vect_e2); - - un60_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0_0 : AO1C - port map(A => \data_mem_addr_r_1[2]\, B => - \data_mem_addr_w_1[2]\, C => N_109, Y => - ADD_5x5_fast_I11_Y_i_a2_0); - - \Waddr_vect_RNIBOBV[0]\ : OR3A - port map(A => N_165, B => data_mem_wen_i_0(1), C => - \data_mem_addr_w_1[0]\, Y => N_158); - - sEmpty_RNO_2 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - un60_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3 : NOR2A - port map(A => N_9, B => \data_mem_addr_r_1[2]\, Y => N_17); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_1[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(1), Y => - un7_sempty_s_0); - - un75_ready_1_16_ADD_5x5_fast_I11_un1_Y : AOI1B - port map(A => N_109, B => N_89_i, C => - ADD_5x5_fast_I11_un1_Y_0, Y => I11_un1_Y); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, Y => I_5_18); - - \Raddr_vect_RNITJRC[4]\ : NOR2B - port map(A => I_9_18, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \ready_gen.un69_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, C => N_5, Y => N_9_1); - - un26_sfull_s_tz_RNO_2 : XA1 - port map(A => \data_mem_addr_r_1[3]\, B => - \un8_waddr_vect_s[3]\, C => \un26_sfull_s_tz_RNO_7\, Y - => un5_sfull_s_4_2); - - un60_ready_1_1_0_CO1_tz : AO18 - port map(A => N_105_1, B => \data_mem_addr_w_1[2]\, C => - \data_mem_addr_r_1[2]\, Y => CO1_tz); - - \ready_gen.un69_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_w_1[0]\, Y => N_6); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_11, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Raddr_vect_RNIRSIG2[0]\ : MX2C - port map(A => \un75_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_1[0]\, Y => N_197); - - \Raddr_vect_RNI4A0PH[0]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[0]\, B => - data_addr_r_iv_i_3(0), C => N_76, Y => - Raddr_vect_RNI4A0PH(0)); - - un75_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1D - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75_i_0, Y => \un75_ready1[5]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \data_mem_addr_w_1[1]\, - S => data_mem_wen_i_0(1), Y => Waddr_vect_e1); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_1[2]\); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => \DWACT_FINC_E[0]\); - - \Raddr_vect_RNI7873_0[3]\ : OR2A - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, Y => N_109); - - \Raddr_vect_RNI1473[3]\ : NOR2 - port map(A => \data_mem_addr_r_1[3]\, B => - \data_mem_addr_r_1[2]\, Y => un2_raddr_vect_slto3_0); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[3]\); - - \Raddr_vect_RNIIMQ5I[4]\ : NOR3C - port map(A => \data_addr_r_iv_i_4[4]\, B => - data_addr_r_iv_i_3(4), C => N_44, Y => - Raddr_vect_RNIIMQ5I(4)); - - sEmpty_RNO_5 : XA1A - port map(A => \data_mem_addr_w_1[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_7_0, Y => - un7_sempty_s_2); - - un75_ready_1_16_ADD_5x5_fast_I1_G0N : AO1C - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, C => N_87, Y => N80); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_1[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - un60_ready_0_0_0_ADD_5x5_fast_I18_Y_0 : AX1C - port map(A => N_12_1, B => N_13, C => N_89_i, Y => - \un60_ready0[4]\); - - un75_ready_1_16_ADD_5x5_fast_I15_Y_0 : AX1A - port map(A => ADD_5x5_fast_I8_un1_Y_0, B => N80, C => - \un75_ready0_1[4]\, Y => \un75_ready1[4]\); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => data_mem_ren_i_0(1), Q => - \data_mem_addr_r_1[4]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_1[2]\, Y => - I_9_17); - - un75_ready_1_16_ADD_5x5_fast_I11_Y_0 : MIN3 - port map(A => N_89_i, B => N_109, C => N80, Y => - ADD_5x5_fast_I11_Y_0); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(1), Y => un1_sempty_s); - - sFull_RNICGOT : OR3B - port map(A => data_mem_wen_i_0(1), B => data_mem_wen_i_0(2), - C => N_164, Y => N_120_i); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => Waddr_vect_n2_tz); - - \Raddr_vect_RNIME6A4[2]\ : OA1A - port map(A => data_mem_ren_i_0(1), B => - \data_mem_addr_r_1[2]\, C => N_59, Y => - \data_addr_r_iv_i_4[2]\); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_1[4]\, Y => - I_20_10); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ7 is - - port( time_mem_addr_w_3_i_0_1 : out std_logic; - data_addr_w_1_iv_i_a2_1_1_0 : in std_logic_vector(6 to 6); - data_addr_w_1_iv_i_s_0_0 : out std_logic_vector(6 to 6); - time_wen : in std_logic_vector(3 to 3); - time_ren : in std_logic_vector(3 to 3); - data_mem_ren_i_0 : in std_logic_vector(1 to 1); - time_mem_ren_i_0 : out std_logic_vector(3 to 3); - data_addr_r_1_iv_i_a9_1_1 : out std_logic_vector(6 to 6); - time_mem_addr_w_3 : out std_logic_vector(1 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_124 : out std_logic; - N_64 : out std_logic; - N_140 : out std_logic; - N_30_1 : out std_logic; - N_89 : out std_logic; - N_163 : in std_logic; - N_164 : out std_logic; - N_72 : out std_logic; - N_56 : out std_logic; - N_48 : out std_logic; - N_35 : out std_logic; - N_113 : in std_logic; - N_162 : in std_logic; - N_77 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ7; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ7 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_7, \time_mem_addr_r_3[1]\, \time_mem_addr_r_3[0]\, - N_7_0, un5_sfull_s_3, sFull_RNO_3_0, sFull_RNO_4_0, - un5_sfull_s_0, un5_sfull_s_2, \Raddr_vect[3]_net_1\, - \un8_waddr_vect_s[3]\, \un8_waddr_vect_s[0]\, - un7_sempty_s_3, sEmpty_RNO_3_2, sEmpty_RNO_4_2, - un7_sempty_s_0, un7_sempty_s_2, \Waddr_vect[3]_net_1\, - \un10_raddr_vect_s[3]\, \un10_raddr_vect_s[0]\, - \time_mem_addr_w_3[0]\, \data_addr_w_1_iv_i_s_0_tz[6]\, - un2_raddr_vect_slt3, \time_mem_addr_r_3_i_0[2]\, - un1_waddr_vect_slt3, \time_mem_addr_w_3[1]\, - \time_mem_addr_w_3_i_0[2]\, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, - \time_mem_addr_w_3_i_0[5]\, \time_mem_wen_i_0[3]\, - Raddr_vect_n2, un2_raddr_vect_s, Raddr_vect_n2_tz, - Waddr_vect_n2, un1_waddr_vect_s, Waddr_vect_n2_tz, I_13_3, - I_5_3, I_9_3, \time_mem_addr_r_3_i_0[5]\, - \time_mem_ren_i_0[3]\, \time_mem_addr_r_3_i_0[3]\, - Raddr_vect_n1_i, Raddr_vect_e2, Raddr_vect_e1, - Raddr_vect_e0, \N_89\, Waddr_vect_e2, Waddr_vect_e0, - Waddr_vect_e1, Waddr_vect_n1_i, I_13_4, I_5_4, I_9_4, - \sFull_RNO\, un8_sfull_s, \sEmpty_RNO\, un2_sempty_s, - \sFull\, \sEmpty\, N_4, N_4_0, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - time_mem_ren_i_0(3) <= \time_mem_ren_i_0[3]\; - time_mem_addr_w_3(1) <= \time_mem_addr_w_3[1]\; - time_mem_addr_w_3(0) <= \time_mem_addr_w_3[0]\; - N_89 <= \N_89\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_3[1]\, B => - \time_mem_addr_w_3[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => N_4); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_3[1]\, B => - \time_mem_addr_r_3[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - \Raddr_vect_RNICJ9L[2]\ : OR2A - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \time_mem_ren_i_0[3]\, Y => N_56); - - sFull_RNIR3CG : OR2B - port map(A => \time_mem_addr_w_3_i_0[5]\, B => \N_89\, Y - => N_124); - - sEmpty_RNIBEFO_1 : OR2 - port map(A => \time_mem_ren_i_0[3]\, B => - \time_mem_addr_r_3_i_0[5]\, Y => N_30_1); - - \Waddr_vect_RNI6PG9[1]\ : OR3 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => un1_waddr_vect_slt3); - - un43_mem_addr_ren_1_SUM1_0 : XNOR2 - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_3_i_0[3]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_3[1]\, B => - \time_mem_addr_w_3[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_3[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_wen_i_0[3]\, Q => - \Waddr_vect[3]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \time_mem_addr_r_3_i_0[2]\, Y => - I_9_4); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO\, CLK => HCLK_c, PRE => HRESETn_c, - Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[3]\, - C => \time_mem_addr_w_3[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_3_i_0[2]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_3[1]\, - S => \time_mem_wen_i_0[3]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, Y => I_5_3); - - \Raddr_vect_RNIMJMC[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - sEmpty_RNIFCRP3 : NOR3B - port map(A => N_77, B => \time_mem_ren_i_0[3]\, C => - data_mem_ren_i_0(1), Y => data_addr_r_1_iv_i_a9_1_1(6)); - - \Waddr_vect_RNIN86D[2]\ : OR2B - port map(A => \time_mem_addr_w_3_i_0[2]\, B => \N_89\, Y - => N_140); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_ren_i_0[3]\, Q => - \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(3), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4, B => \Waddr_vect[3]_net_1\, Y => I_13_3); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[3]\, - C => \time_mem_addr_r_3[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_3[1]\, - S => \time_mem_ren_i_0[3]\, Y => Raddr_vect_e1); - - sFull_RNIKH0A_0 : NOR2A - port map(A => N_163, B => \time_mem_wen_i_0[3]\, Y => - \N_89\); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_3, C => - \time_mem_addr_r_3[1]\, Y => sFull_RNO_4_0); - - sFull_RNO_6 : OR2B - port map(A => I_13_3, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_4, C => - \time_mem_addr_w_3_i_0[2]\, Y => sEmpty_RNO_3_2); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_3_i_0[2]\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_3[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_3[0]\, C => time_wen(3), Y => - un5_sfull_s_0); - - sFull_RNIQOVC1 : OA1 - port map(A => N_162, B => \data_addr_w_1_iv_i_s_0_tz[6]\, C - => N_113, Y => data_addr_w_1_iv_i_s_0_0(6)); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => - \time_mem_addr_w_3_i_0[2]\, S => \time_mem_wen_i_0[3]\, Y - => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_4, C => - \time_mem_addr_w_3[1]\, Y => sEmpty_RNO_4_2); - - un50_mem_addr_wen_1_SUM1_0 : XNOR2 - port map(A => \time_mem_addr_w_3_i_0[2]\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_3_i_0_1); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_3, C => - \time_mem_addr_r_3_i_0[2]\, Y => sFull_RNO_3_0); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_2, B => sEmpty_RNO_4_2, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => Waddr_vect_n2_tz); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => Raddr_vect_n2_tz); - - sEmpty_RNO_7 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_3[0]\, - Y => \un10_raddr_vect_s[0]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => - \time_mem_addr_r_3_i_0[2]\, S => \time_mem_ren_i_0[3]\, Y - => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_3[0]\); - - sEmpty_RNIBEFO_0 : OR2A - port map(A => \time_mem_addr_r_3_i_0[3]\, B => - \time_mem_ren_i_0[3]\, Y => N_48); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_3[1]\, B => - \time_mem_addr_r_3[0]\, Y => N_7); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \time_mem_addr_w_3_i_0[2]\, Y => - I_9_3); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_0, B => \Raddr_vect[3]_net_1\, Y => - I_13_4); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => N_4_0); - - sFull_RNIBLJS : MX2B - port map(A => \time_mem_addr_w_3_i_0[5]\, B => - data_addr_w_1_iv_i_a2_1_1_0(6), S => - \time_mem_wen_i_0[3]\, Y => - \data_addr_w_1_iv_i_s_0_tz[6]\); - - sFull_RNIG4G2 : OR2 - port map(A => time_wen(3), B => \sFull\, Y => - \time_mem_wen_i_0[3]\); - - \Raddr_vect_RNINOG9[1]\ : OR3 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => un2_raddr_vect_slt3); - - sEmpty_RNO_1 : XA1B - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, C => time_ren(3), Y => - un7_sempty_s_2); - - sFull_RNO_1 : XA1 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, C => time_ren(3), Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, Y => I_5_4); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => Waddr_vect_15_0); - - sFull_RNO_7 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_3[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNIBEFO : OR2A - port map(A => \time_mem_addr_r_3_i_0[5]\, B => - \time_mem_ren_i_0[3]\, Y => N_35); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => Raddr_vect_7_0); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => sFull_RNO_3_0, B => sFull_RNO_4_0, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2B - port map(A => I_13_4, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un43_mem_addr_ren_1_CO1 : NOR2B - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_3_i_0[5]\); - - sFull : DFN1C0 - port map(D => \sFull_RNO\, CLK => HCLK_c, CLR => HRESETn_c, - Q => \sFull\); - - \Waddr_vect_RNIAKMC[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - un50_mem_addr_wen_1_CO1 : NOR2B - port map(A => \time_mem_addr_w_3_i_0[2]\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_3_i_0[5]\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_3[1]\); - - sEmpty_RNIES3I : OR2 - port map(A => time_ren(3), B => \sEmpty\, Y => - \time_mem_ren_i_0[3]\); - - \Raddr_vect_RNIBF9L[1]\ : OR2 - port map(A => \time_mem_ren_i_0[3]\, B => - \time_mem_addr_r_3[1]\, Y => N_64); - - sFull_RNO_2 : NOR2B - port map(A => time_ren(3), B => \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_3[0]\, C => time_wen(3), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - \Raddr_vect_RNIAB9L[0]\ : OR2 - port map(A => \time_mem_ren_i_0[3]\, B => - \time_mem_addr_r_3[0]\, Y => N_72); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - sFull_RNIKH0A : OR2B - port map(A => \time_mem_wen_i_0[3]\, B => N_163, Y => N_164); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity generic_syncram_2p_7_32_0 is - - port( wdata : in std_logic_vector(31 downto 0); - Waddr_vect_RNILLSP5 : in std_logic_vector(4 to 4); - Waddr_vect_RNIJTNE5 : in std_logic_vector(3 to 3); - Waddr_vect_RNI394D5 : in std_logic_vector(2 to 2); - Waddr_vect_RNI0O455 : in std_logic_vector(1 to 1); - Waddr_vect_RNION355 : in std_logic_vector(0 to 0); - Raddr_vect_RNIIMQ5I : in std_logic_vector(4 to 4); - Raddr_vect_RNIE6Q5I : in std_logic_vector(3 to 3); - Raddr_vect_RNIKA2PH : in std_logic_vector(2 to 2); - Raddr_vect_RNICA1PH : in std_logic_vector(1 to 1); - Raddr_vect_RNI4A0PH : in std_logic_vector(0 to 0); - hwdata_c : out std_logic_vector(31 downto 0); - N_1_i_1_i : in std_logic; - generic_syncram_2p_7_32_0_VCC : in std_logic; - generic_syncram_2p_7_32_0_GND : in std_logic; - sFull_RNIU5GK1 : in std_logic; - sFull_RNIHL443 : in std_logic; - sEmpty_RNILSD08 : in std_logic; - sEmpty_RNIE7T87 : in std_logic; - N_1_i_1 : in std_logic; - HCLK_c : in std_logic - ); - -end generic_syncram_2p_7_32_0; - -architecture DEF_ARCH of generic_syncram_2p_7_32_0 is - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component RAM512X18 - generic (MEMORYFILE:string := ""); - - port( RADDR8 : in std_logic := 'U'; - RADDR7 : in std_logic := 'U'; - RADDR6 : in std_logic := 'U'; - RADDR5 : in std_logic := 'U'; - RADDR4 : in std_logic := 'U'; - RADDR3 : in std_logic := 'U'; - RADDR2 : in std_logic := 'U'; - RADDR1 : in std_logic := 'U'; - RADDR0 : in std_logic := 'U'; - WADDR8 : in std_logic := 'U'; - WADDR7 : in std_logic := 'U'; - WADDR6 : in std_logic := 'U'; - WADDR5 : in std_logic := 'U'; - WADDR4 : in std_logic := 'U'; - WADDR3 : in std_logic := 'U'; - WADDR2 : in std_logic := 'U'; - WADDR1 : in std_logic := 'U'; - WADDR0 : in std_logic := 'U'; - WD17 : in std_logic := 'U'; - WD16 : in std_logic := 'U'; - WD15 : in std_logic := 'U'; - WD14 : in std_logic := 'U'; - WD13 : in std_logic := 'U'; - WD12 : in std_logic := 'U'; - WD11 : in std_logic := 'U'; - WD10 : in std_logic := 'U'; - WD9 : in std_logic := 'U'; - WD8 : in std_logic := 'U'; - WD7 : in std_logic := 'U'; - WD6 : in std_logic := 'U'; - WD5 : in std_logic := 'U'; - WD4 : in std_logic := 'U'; - WD3 : in std_logic := 'U'; - WD2 : in std_logic := 'U'; - WD1 : in std_logic := 'U'; - WD0 : in std_logic := 'U'; - RW0 : in std_logic := 'U'; - RW1 : in std_logic := 'U'; - WW0 : in std_logic := 'U'; - WW1 : in std_logic := 'U'; - PIPE : in std_logic := 'U'; - REN : in std_logic := 'U'; - WEN : in std_logic := 'U'; - RCLK : in std_logic := 'U'; - WCLK : in std_logic := 'U'; - RESET : in std_logic := 'U'; - RD17 : out std_logic; - RD16 : out std_logic; - RD15 : out std_logic; - RD14 : out std_logic; - RD13 : out std_logic; - RD12 : out std_logic; - RD11 : out std_logic; - RD10 : out std_logic; - RD9 : out std_logic; - RD8 : out std_logic; - RD7 : out std_logic; - RD6 : out std_logic; - RD5 : out std_logic; - RD4 : out std_logic; - RD3 : out std_logic; - RD2 : out std_logic; - RD1 : out std_logic; - RD0 : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal N_7_0, I_5_1, I_5_0, I_5_5, I_4_5_i_0, I_4_4_i_0, - I_5_3, \RADDR_REG1[6]\, \WADDR_REG1[6]\, N_5, - \RADDR_REG1[2]\, \WADDR_REG1[2]\, I_4_3_i_0, - \RADDR_REG1[0]\, \WADDR_REG1[0]\, I_4_1_i_0, N_7, - \DOUT_TMP[13]\, \DIN_REG1[13]\, \DOUT_TMP[12]\, - \DIN_REG1[12]\, \DOUT_TMP[11]\, \DIN_REG1[11]\, - \DOUT_TMP[10]\, \DIN_REG1[10]\, \DOUT_TMP[9]\, - \DIN_REG1[9]\, \DOUT_TMP[8]\, \DIN_REG1[8]\, - \DOUT_TMP[7]\, \DIN_REG1[7]\, \DOUT_TMP[6]\, - \DIN_REG1[6]\, \DOUT_TMP[5]\, \DIN_REG1[5]\, - \DOUT_TMP[4]\, \DIN_REG1[4]\, \DOUT_TMP[3]\, - \DIN_REG1[3]\, \DOUT_TMP[2]\, \DIN_REG1[2]\, - \DOUT_TMP[1]\, \DIN_REG1[1]\, \DOUT_TMP[0]\, - \DIN_REG1[0]\, \DOUT_TMP[17]\, \DIN_REG1[17]\, - \DOUT_TMP[16]\, \DIN_REG1[16]\, \DOUT_TMP[15]\, - \DIN_REG1[15]\, \DOUT_TMP[14]\, \DIN_REG1[14]\, - \DOUT_TMP_0[13]\, \DIN_REG1_0[13]\, \DOUT_TMP_0[12]\, - \DIN_REG1_0[12]\, \DOUT_TMP_0[11]\, \DIN_REG1_0[11]\, - \DOUT_TMP_0[10]\, \DIN_REG1_0[10]\, \DOUT_TMP_0[9]\, - \DIN_REG1_0[9]\, \DOUT_TMP_0[8]\, \DIN_REG1_0[8]\, - \DOUT_TMP_0[7]\, \DIN_REG1_0[7]\, \DOUT_TMP_0[6]\, - \DIN_REG1_0[6]\, \DOUT_TMP_0[5]\, \DIN_REG1_0[5]\, - \DOUT_TMP_0[4]\, \DIN_REG1_0[4]\, \DOUT_TMP_0[3]\, - \DIN_REG1_0[3]\, \DOUT_TMP_0[2]\, \DIN_REG1_0[2]\, - \DOUT_TMP_0[1]\, \DIN_REG1_0[1]\, \DOUT_TMP_0[0]\, - \DIN_REG1_0[0]\, \WADDR_REG1[5]\, \RADDR_REG1[5]\, - \WADDR_REG1[4]\, \RADDR_REG1[4]\, \WADDR_REG1[3]\, - \RADDR_REG1[3]\, \WADDR_REG1[1]\, \RADDR_REG1[1]\, - \DOUT_TMP_0[14]\, \DOUT_TMP_0[15]\, \DOUT_TMP_0[16]\, - \DOUT_TMP_0[17]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \rfd_tile_RADDR_REG1_RNIG9I4[2]\ : XA1A - port map(A => \RADDR_REG1[2]\, B => \WADDR_REG1[2]\, C => - I_4_3_i_0, Y => I_5_1); - - \rfd_tile_DIN_REG1[9]\ : DFN1 - port map(D => wdata(9), CLK => HCLK_c, Q => \DIN_REG1_0[9]\); - - \rfd_tile_0_DIN_REG1[0]\ : DFN1 - port map(D => wdata(18), CLK => HCLK_c, Q => \DIN_REG1[0]\); - - \rfd_tile_RADDR_REG1[5]\ : DFN1 - port map(D => sEmpty_RNIE7T87, CLK => HCLK_c, Q => - \RADDR_REG1[5]\); - - \rfd_tile_0_DIN_REG1[12]\ : DFN1 - port map(D => wdata(30), CLK => HCLK_c, Q => \DIN_REG1[12]\); - - \rfd_tile_WADDR_REG1[6]\ : DFN1 - port map(D => sFull_RNIU5GK1, CLK => HCLK_c, Q => - \WADDR_REG1[6]\); - - rfd_tile_I_3 : DFN1 - port map(D => N_1_i_1, CLK => HCLK_c, Q => N_5); - - \rfd_tile_RADDR_REG1_RNI89H4[0]\ : XA1A - port map(A => \RADDR_REG1[0]\, B => \WADDR_REG1[0]\, C => - I_4_1_i_0, Y => I_5_0); - - rfd_tile_0_I_1_RNIK6BO : MX2 - port map(A => \DOUT_TMP[6]\, B => \DIN_REG1[6]\, S => N_7_0, - Y => hwdata_c(24)); - - rfd_tile_I_1_RNI83001 : MX2 - port map(A => \DOUT_TMP_0[13]\, B => \DIN_REG1_0[13]\, S - => N_7, Y => hwdata_c(13)); - - \rfd_tile_0_DIN_REG1[11]\ : DFN1 - port map(D => wdata(29), CLK => HCLK_c, Q => \DIN_REG1[11]\); - - \rfd_tile_DIN_REG1[10]\ : DFN1 - port map(D => wdata(10), CLK => HCLK_c, Q => - \DIN_REG1_0[10]\); - - rfd_tile_0_I_1_RNIGMAO : MX2 - port map(A => \DOUT_TMP[2]\, B => \DIN_REG1[2]\, S => N_7_0, - Y => hwdata_c(20)); - - rfd_tile_I_1_RNIA3001 : MX2 - port map(A => \DOUT_TMP[15]\, B => \DIN_REG1[15]\, S => N_7, - Y => hwdata_c(15)); - - \rfd_tile_DIN_REG1_RNIROBR[7]\ : MX2 - port map(A => \DOUT_TMP_0[7]\, B => \DIN_REG1_0[7]\, S => - N_7, Y => hwdata_c(7)); - - \rfd_tile_WADDR_REG1[4]\ : DFN1 - port map(D => Waddr_vect_RNILLSP5(4), CLK => HCLK_c, Q => - \WADDR_REG1[4]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \rfd_tile_DIN_REG1_RNIM4BR[2]\ : MX2 - port map(A => \DOUT_TMP_0[2]\, B => \DIN_REG1_0[2]\, S => - N_7, Y => hwdata_c(2)); - - \rfd_tile_DIN_REG1[0]\ : DFN1 - port map(D => wdata(0), CLK => HCLK_c, Q => \DIN_REG1_0[0]\); - - \rfd_tile_DIN_REG1[5]\ : DFN1 - port map(D => wdata(5), CLK => HCLK_c, Q => \DIN_REG1_0[5]\); - - \rfd_tile_0_DIN_REG1[6]\ : DFN1 - port map(D => wdata(24), CLK => HCLK_c, Q => \DIN_REG1[6]\); - - \rfd_tile_0_DIN_REG1[1]\ : DFN1 - port map(D => wdata(19), CLK => HCLK_c, Q => \DIN_REG1[1]\); - - \rfd_tile_RADDR_REG1_RNILO82[1]\ : XNOR2 - port map(A => \WADDR_REG1[1]\, B => \RADDR_REG1[1]\, Y => - I_4_1_i_0); - - \rfd_tile_DIN_REG1[4]\ : DFN1 - port map(D => wdata(4), CLK => HCLK_c, Q => \DIN_REG1_0[4]\); - - \rfd_tile_DIN_REG1[3]\ : DFN1 - port map(D => wdata(3), CLK => HCLK_c, Q => \DIN_REG1_0[3]\); - - \rfd_tile_DIN_REG1[2]\ : DFN1 - port map(D => wdata(2), CLK => HCLK_c, Q => \DIN_REG1_0[2]\); - - rfd_tile_0_I_1_RNIHQAO : MX2 - port map(A => \DOUT_TMP[3]\, B => \DIN_REG1[3]\, S => N_7_0, - Y => hwdata_c(21)); - - \rfd_tile_0_DIN_REG1[2]\ : DFN1 - port map(D => wdata(20), CLK => HCLK_c, Q => \DIN_REG1[2]\); - - rfd_tile_0_I_1 : RAM512X18 - port map(RADDR8 => generic_syncram_2p_7_32_0_GND, RADDR7 - => generic_syncram_2p_7_32_0_GND, RADDR6 => - sEmpty_RNILSD08, RADDR5 => sEmpty_RNIE7T87, RADDR4 => - Raddr_vect_RNIIMQ5I(4), RADDR3 => Raddr_vect_RNIE6Q5I(3), - RADDR2 => Raddr_vect_RNIKA2PH(2), RADDR1 => - Raddr_vect_RNICA1PH(1), RADDR0 => Raddr_vect_RNI4A0PH(0), - WADDR8 => generic_syncram_2p_7_32_0_GND, WADDR7 => - generic_syncram_2p_7_32_0_GND, WADDR6 => sFull_RNIU5GK1, - WADDR5 => sFull_RNIHL443, WADDR4 => - Waddr_vect_RNILLSP5(4), WADDR3 => Waddr_vect_RNIJTNE5(3), - WADDR2 => Waddr_vect_RNI394D5(2), WADDR1 => - Waddr_vect_RNI0O455(1), WADDR0 => Waddr_vect_RNION355(0), - WD17 => generic_syncram_2p_7_32_0_GND, WD16 => - generic_syncram_2p_7_32_0_GND, WD15 => - generic_syncram_2p_7_32_0_GND, WD14 => - generic_syncram_2p_7_32_0_GND, WD13 => wdata(31), WD12 - => wdata(30), WD11 => wdata(29), WD10 => wdata(28), WD9 - => wdata(27), WD8 => wdata(26), WD7 => wdata(25), WD6 - => wdata(24), WD5 => wdata(23), WD4 => wdata(22), WD3 - => wdata(21), WD2 => wdata(20), WD1 => wdata(19), WD0 - => wdata(18), RW0 => generic_syncram_2p_7_32_0_GND, RW1 - => generic_syncram_2p_7_32_0_VCC, WW0 => - generic_syncram_2p_7_32_0_GND, WW1 => - generic_syncram_2p_7_32_0_VCC, PIPE => - generic_syncram_2p_7_32_0_GND, REN => - generic_syncram_2p_7_32_0_GND, WEN => N_1_i_1_i, RCLK => - HCLK_c, WCLK => HCLK_c, RESET => - generic_syncram_2p_7_32_0_VCC, RD17 => \DOUT_TMP_0[17]\, - RD16 => \DOUT_TMP_0[16]\, RD15 => \DOUT_TMP_0[15]\, RD14 - => \DOUT_TMP_0[14]\, RD13 => \DOUT_TMP[13]\, RD12 => - \DOUT_TMP[12]\, RD11 => \DOUT_TMP[11]\, RD10 => - \DOUT_TMP[10]\, RD9 => \DOUT_TMP[9]\, RD8 => - \DOUT_TMP[8]\, RD7 => \DOUT_TMP[7]\, RD6 => \DOUT_TMP[6]\, - RD5 => \DOUT_TMP[5]\, RD4 => \DOUT_TMP[4]\, RD3 => - \DOUT_TMP[3]\, RD2 => \DOUT_TMP[2]\, RD1 => \DOUT_TMP[1]\, - RD0 => \DOUT_TMP[0]\); - - \rfd_tile_DIN_REG1[12]\ : DFN1 - port map(D => wdata(12), CLK => HCLK_c, Q => - \DIN_REG1_0[12]\); - - \rfd_tile_0_DIN_REG1[5]\ : DFN1 - port map(D => wdata(23), CLK => HCLK_c, Q => \DIN_REG1[5]\); - - rfd_tile_0_I_1_RNIMEBO : MX2 - port map(A => \DOUT_TMP[8]\, B => \DIN_REG1[8]\, S => N_7_0, - Y => hwdata_c(26)); - - \rfd_tile_0_DIN_REG1[3]\ : DFN1 - port map(D => wdata(21), CLK => HCLK_c, Q => \DIN_REG1[3]\); - - \rfd_tile_RADDR_REG1_RNIRG92[4]\ : XNOR2 - port map(A => \WADDR_REG1[4]\, B => \RADDR_REG1[4]\, Y => - I_4_4_i_0); - - rfd_tile_0_I_1_RNIIUAO : MX2 - port map(A => \DOUT_TMP[4]\, B => \DIN_REG1[4]\, S => N_7_0, - Y => hwdata_c(22)); - - \rfd_tile_DIN_REG1_RNIPGBR[5]\ : MX2 - port map(A => \DOUT_TMP_0[5]\, B => \DIN_REG1_0[5]\, S => - N_7, Y => hwdata_c(5)); - - rfd_tile_I_1_RNI53001 : MX2 - port map(A => \DOUT_TMP_0[10]\, B => \DIN_REG1_0[10]\, S - => N_7, Y => hwdata_c(10)); - - \rfd_tile_DIN_REG1[15]\ : DFN1 - port map(D => wdata(15), CLK => HCLK_c, Q => \DIN_REG1[15]\); - - rfd_tile_0_I_1_RNIB01O : MX2 - port map(A => \DOUT_TMP[12]\, B => \DIN_REG1[12]\, S => - N_7_0, Y => hwdata_c(30)); - - \rfd_tile_RADDR_REG1[0]\ : DFN1 - port map(D => Raddr_vect_RNI4A0PH(0), CLK => HCLK_c, Q => - \RADDR_REG1[0]\); - - \rfd_tile_WADDR_REG1[5]\ : DFN1 - port map(D => sFull_RNIHL443, CLK => HCLK_c, Q => - \WADDR_REG1[5]\); - - \rfd_tile_RADDR_REG1[2]\ : DFN1 - port map(D => Raddr_vect_RNIKA2PH(2), CLK => HCLK_c, Q => - \RADDR_REG1[2]\); - - rfd_tile_0_I_1_RNILABO : MX2 - port map(A => \DOUT_TMP[7]\, B => \DIN_REG1[7]\, S => N_7_0, - Y => hwdata_c(25)); - - rfd_tile_0_I_1_RNIFIAO : MX2 - port map(A => \DOUT_TMP[1]\, B => \DIN_REG1[1]\, S => N_7_0, - Y => hwdata_c(19)); - - \rfd_tile_0_DIN_REG1[9]\ : DFN1 - port map(D => wdata(27), CLK => HCLK_c, Q => \DIN_REG1[9]\); - - \rfd_tile_DIN_REG1[1]\ : DFN1 - port map(D => wdata(1), CLK => HCLK_c, Q => \DIN_REG1_0[1]\); - - \rfd_tile_RADDR_REG1_RNIP892[3]\ : XNOR2 - port map(A => \WADDR_REG1[3]\, B => \RADDR_REG1[3]\, Y => - I_4_3_i_0); - - rfd_tile_I_1_RNI63001 : MX2 - port map(A => \DOUT_TMP_0[11]\, B => \DIN_REG1_0[11]\, S - => N_7, Y => hwdata_c(11)); - - \rfd_tile_RADDR_REG1_RNIQS1L[0]\ : NOR3C - port map(A => I_5_1, B => I_5_0, C => I_5_5, Y => N_7_0); - - \rfd_tile_RADDR_REG1[3]\ : DFN1 - port map(D => Raddr_vect_RNIE6Q5I(3), CLK => HCLK_c, Q => - \RADDR_REG1[3]\); - - \rfd_tile_DIN_REG1_RNIQKBR[6]\ : MX2 - port map(A => \DOUT_TMP_0[6]\, B => \DIN_REG1_0[6]\, S => - N_7, Y => hwdata_c(6)); - - rfd_tile_0_I_1_RNIJ2BO : MX2 - port map(A => \DOUT_TMP[5]\, B => \DIN_REG1[5]\, S => N_7_0, - Y => hwdata_c(23)); - - \rfd_tile_RADDR_REG1_RNI2AUB[4]\ : NOR3C - port map(A => I_4_5_i_0, B => I_4_4_i_0, C => I_5_3, Y => - I_5_5); - - GND_i : GND - port map(Y => \GND\); - - \rfd_tile_RADDR_REG1_RNITO92[5]\ : XNOR2 - port map(A => \WADDR_REG1[5]\, B => \RADDR_REG1[5]\, Y => - I_4_5_i_0); - - \rfd_tile_RADDR_REG1[1]\ : DFN1 - port map(D => Raddr_vect_RNICA1PH(1), CLK => HCLK_c, Q => - \RADDR_REG1[1]\); - - \rfd_tile_RADDR_REG1_RNIA0B7[6]\ : XA1A - port map(A => \RADDR_REG1[6]\, B => \WADDR_REG1[6]\, C => - N_5, Y => I_5_3); - - rfd_tile_0_I_1_RNINIBO : MX2 - port map(A => \DOUT_TMP[9]\, B => \DIN_REG1[9]\, S => N_7_0, - Y => hwdata_c(27)); - - \rfd_tile_DIN_REG1[14]\ : DFN1 - port map(D => wdata(14), CLK => HCLK_c, Q => \DIN_REG1[14]\); - - \rfd_tile_0_DIN_REG1[10]\ : DFN1 - port map(D => wdata(28), CLK => HCLK_c, Q => \DIN_REG1[10]\); - - \rfd_tile_DIN_REG1_RNISSBR[8]\ : MX2 - port map(A => \DOUT_TMP_0[8]\, B => \DIN_REG1_0[8]\, S => - N_7, Y => hwdata_c(8)); - - \rfd_tile_RADDR_REG1[6]\ : DFN1 - port map(D => sEmpty_RNILSD08, CLK => HCLK_c, Q => - \RADDR_REG1[6]\); - - rfd_tile_0_I_1_RNIC01O : MX2 - port map(A => \DOUT_TMP[13]\, B => \DIN_REG1[13]\, S => - N_7_0, Y => hwdata_c(31)); - - rfd_tile_0_I_1_RNIA01O : MX2 - port map(A => \DOUT_TMP[11]\, B => \DIN_REG1[11]\, S => - N_7_0, Y => hwdata_c(29)); - - \rfd_tile_DIN_REG1_RNIKSAR[0]\ : MX2 - port map(A => \DOUT_TMP_0[0]\, B => \DIN_REG1_0[0]\, S => - N_7, Y => hwdata_c(0)); - - \rfd_tile_DIN_REG1_RNIOCBR[4]\ : MX2 - port map(A => \DOUT_TMP_0[4]\, B => \DIN_REG1_0[4]\, S => - N_7, Y => hwdata_c(4)); - - \rfd_tile_DIN_REG1_RNIT0CR[9]\ : MX2 - port map(A => \DOUT_TMP_0[9]\, B => \DIN_REG1_0[9]\, S => - N_7, Y => hwdata_c(9)); - - \rfd_tile_0_DIN_REG1[7]\ : DFN1 - port map(D => wdata(25), CLK => HCLK_c, Q => \DIN_REG1[7]\); - - \rfd_tile_0_DIN_REG1[13]\ : DFN1 - port map(D => wdata(31), CLK => HCLK_c, Q => \DIN_REG1[13]\); - - \rfd_tile_DIN_REG1[8]\ : DFN1 - port map(D => wdata(8), CLK => HCLK_c, Q => \DIN_REG1_0[8]\); - - rfd_tile_0_I_1_RNIEEAO : MX2 - port map(A => \DOUT_TMP[0]\, B => \DIN_REG1[0]\, S => N_7_0, - Y => hwdata_c(18)); - - \rfd_tile_WADDR_REG1[0]\ : DFN1 - port map(D => Waddr_vect_RNION355(0), CLK => HCLK_c, Q => - \WADDR_REG1[0]\); - - \rfd_tile_DIN_REG1_RNIN8BR[3]\ : MX2 - port map(A => \DOUT_TMP_0[3]\, B => \DIN_REG1_0[3]\, S => - N_7, Y => hwdata_c(3)); - - \rfd_tile_RADDR_REG1[4]\ : DFN1 - port map(D => Raddr_vect_RNIIMQ5I(4), CLK => HCLK_c, Q => - \RADDR_REG1[4]\); - - \rfd_tile_DIN_REG1[6]\ : DFN1 - port map(D => wdata(6), CLK => HCLK_c, Q => \DIN_REG1_0[6]\); - - \rfd_tile_0_DIN_REG1[8]\ : DFN1 - port map(D => wdata(26), CLK => HCLK_c, Q => \DIN_REG1[8]\); - - \rfd_tile_WADDR_REG1[2]\ : DFN1 - port map(D => Waddr_vect_RNI394D5(2), CLK => HCLK_c, Q => - \WADDR_REG1[2]\); - - \rfd_tile_DIN_REG1_RNIL0BR[1]\ : MX2 - port map(A => \DOUT_TMP_0[1]\, B => \DIN_REG1_0[1]\, S => - N_7, Y => hwdata_c(1)); - - \rfd_tile_DIN_REG1[11]\ : DFN1 - port map(D => wdata(11), CLK => HCLK_c, Q => - \DIN_REG1_0[11]\); - - rfd_tile_I_1_RNI93001 : MX2 - port map(A => \DOUT_TMP[14]\, B => \DIN_REG1[14]\, S => N_7, - Y => hwdata_c(14)); - - \rfd_tile_WADDR_REG1[3]\ : DFN1 - port map(D => Waddr_vect_RNIJTNE5(3), CLK => HCLK_c, Q => - \WADDR_REG1[3]\); - - \rfd_tile_DIN_REG1[13]\ : DFN1 - port map(D => wdata(13), CLK => HCLK_c, Q => - \DIN_REG1_0[13]\); - - rfd_tile_0_I_1_RNI901O : MX2 - port map(A => \DOUT_TMP[10]\, B => \DIN_REG1[10]\, S => - N_7_0, Y => hwdata_c(28)); - - rfd_tile_I_1 : RAM512X18 - port map(RADDR8 => generic_syncram_2p_7_32_0_GND, RADDR7 - => generic_syncram_2p_7_32_0_GND, RADDR6 => - sEmpty_RNILSD08, RADDR5 => sEmpty_RNIE7T87, RADDR4 => - Raddr_vect_RNIIMQ5I(4), RADDR3 => Raddr_vect_RNIE6Q5I(3), - RADDR2 => Raddr_vect_RNIKA2PH(2), RADDR1 => - Raddr_vect_RNICA1PH(1), RADDR0 => Raddr_vect_RNI4A0PH(0), - WADDR8 => generic_syncram_2p_7_32_0_GND, WADDR7 => - generic_syncram_2p_7_32_0_GND, WADDR6 => sFull_RNIU5GK1, - WADDR5 => sFull_RNIHL443, WADDR4 => - Waddr_vect_RNILLSP5(4), WADDR3 => Waddr_vect_RNIJTNE5(3), - WADDR2 => Waddr_vect_RNI394D5(2), WADDR1 => - Waddr_vect_RNI0O455(1), WADDR0 => Waddr_vect_RNION355(0), - WD17 => wdata(17), WD16 => wdata(16), WD15 => wdata(15), - WD14 => wdata(14), WD13 => wdata(13), WD12 => wdata(12), - WD11 => wdata(11), WD10 => wdata(10), WD9 => wdata(9), - WD8 => wdata(8), WD7 => wdata(7), WD6 => wdata(6), WD5 - => wdata(5), WD4 => wdata(4), WD3 => wdata(3), WD2 => - wdata(2), WD1 => wdata(1), WD0 => wdata(0), RW0 => - generic_syncram_2p_7_32_0_GND, RW1 => - generic_syncram_2p_7_32_0_VCC, WW0 => - generic_syncram_2p_7_32_0_GND, WW1 => - generic_syncram_2p_7_32_0_VCC, PIPE => - generic_syncram_2p_7_32_0_GND, REN => - generic_syncram_2p_7_32_0_GND, WEN => N_1_i_1_i, RCLK => - HCLK_c, WCLK => HCLK_c, RESET => - generic_syncram_2p_7_32_0_VCC, RD17 => \DOUT_TMP[17]\, - RD16 => \DOUT_TMP[16]\, RD15 => \DOUT_TMP[15]\, RD14 => - \DOUT_TMP[14]\, RD13 => \DOUT_TMP_0[13]\, RD12 => - \DOUT_TMP_0[12]\, RD11 => \DOUT_TMP_0[11]\, RD10 => - \DOUT_TMP_0[10]\, RD9 => \DOUT_TMP_0[9]\, RD8 => - \DOUT_TMP_0[8]\, RD7 => \DOUT_TMP_0[7]\, RD6 => - \DOUT_TMP_0[6]\, RD5 => \DOUT_TMP_0[5]\, RD4 => - \DOUT_TMP_0[4]\, RD3 => \DOUT_TMP_0[3]\, RD2 => - \DOUT_TMP_0[2]\, RD1 => \DOUT_TMP_0[1]\, RD0 => - \DOUT_TMP_0[0]\); - - rfd_tile_I_1_RNIB3001 : MX2 - port map(A => \DOUT_TMP[16]\, B => \DIN_REG1[16]\, S => - N_7_0, Y => hwdata_c(16)); - - \rfd_tile_DIN_REG1[16]\ : DFN1 - port map(D => wdata(16), CLK => HCLK_c, Q => \DIN_REG1[16]\); - - \rfd_tile_WADDR_REG1[1]\ : DFN1 - port map(D => Waddr_vect_RNI0O455(1), CLK => HCLK_c, Q => - \WADDR_REG1[1]\); - - rfd_tile_I_1_RNIC3001 : MX2 - port map(A => \DOUT_TMP[17]\, B => \DIN_REG1[17]\, S => - N_7_0, Y => hwdata_c(17)); - - \rfd_tile_RADDR_REG1_RNIQS1L_0[0]\ : NOR3C - port map(A => I_5_1, B => I_5_0, C => I_5_5, Y => N_7); - - \rfd_tile_DIN_REG1[17]\ : DFN1 - port map(D => wdata(17), CLK => HCLK_c, Q => \DIN_REG1[17]\); - - \rfd_tile_0_DIN_REG1[4]\ : DFN1 - port map(D => wdata(22), CLK => HCLK_c, Q => \DIN_REG1[4]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - rfd_tile_I_1_RNI73001 : MX2 - port map(A => \DOUT_TMP_0[12]\, B => \DIN_REG1_0[12]\, S - => N_7, Y => hwdata_c(12)); - - \rfd_tile_DIN_REG1[7]\ : DFN1 - port map(D => wdata(7), CLK => HCLK_c, Q => \DIN_REG1_0[7]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ1 is - - port( hwdata_c : out std_logic_vector(31 downto 0); - Raddr_vect_RNI4A0PH : in std_logic_vector(0 to 0); - Raddr_vect_RNICA1PH : in std_logic_vector(1 to 1); - Raddr_vect_RNIKA2PH : in std_logic_vector(2 to 2); - Raddr_vect_RNIE6Q5I : in std_logic_vector(3 to 3); - Raddr_vect_RNIIMQ5I : in std_logic_vector(4 to 4); - Waddr_vect_RNION355 : in std_logic_vector(0 to 0); - Waddr_vect_RNI0O455 : in std_logic_vector(1 to 1); - Waddr_vect_RNI394D5 : in std_logic_vector(2 to 2); - Waddr_vect_RNIJTNE5 : in std_logic_vector(3 to 3); - Waddr_vect_RNILLSP5 : in std_logic_vector(4 to 4); - wdata : in std_logic_vector(31 downto 0); - HCLK_c : in std_logic; - N_1_i_1 : in std_logic; - sEmpty_RNIE7T87 : in std_logic; - sEmpty_RNILSD08 : in std_logic; - sFull_RNIHL443 : in std_logic; - sFull_RNIU5GK1 : in std_logic; - syncram_2pZ1_GND : in std_logic; - syncram_2pZ1_VCC : in std_logic; - N_1_i_1_i : in std_logic - ); - -end syncram_2pZ1; - -architecture DEF_ARCH of syncram_2pZ1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component generic_syncram_2p_7_32_0 - port( wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - Waddr_vect_RNILLSP5 : in std_logic_vector(4 to 4) := (others => 'U'); - Waddr_vect_RNIJTNE5 : in std_logic_vector(3 to 3) := (others => 'U'); - Waddr_vect_RNI394D5 : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_RNI0O455 : in std_logic_vector(1 to 1) := (others => 'U'); - Waddr_vect_RNION355 : in std_logic_vector(0 to 0) := (others => 'U'); - Raddr_vect_RNIIMQ5I : in std_logic_vector(4 to 4) := (others => 'U'); - Raddr_vect_RNIE6Q5I : in std_logic_vector(3 to 3) := (others => 'U'); - Raddr_vect_RNIKA2PH : in std_logic_vector(2 to 2) := (others => 'U'); - Raddr_vect_RNICA1PH : in std_logic_vector(1 to 1) := (others => 'U'); - Raddr_vect_RNI4A0PH : in std_logic_vector(0 to 0) := (others => 'U'); - hwdata_c : out std_logic_vector(31 downto 0); - N_1_i_1_i : in std_logic := 'U'; - generic_syncram_2p_7_32_0_VCC : in std_logic := 'U'; - generic_syncram_2p_7_32_0_GND : in std_logic := 'U'; - sFull_RNIU5GK1 : in std_logic := 'U'; - sFull_RNIHL443 : in std_logic := 'U'; - sEmpty_RNILSD08 : in std_logic := 'U'; - sEmpty_RNIE7T87 : in std_logic := 'U'; - N_1_i_1 : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : generic_syncram_2p_7_32_0 - Use entity work.generic_syncram_2p_7_32_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \inf.x0\ : generic_syncram_2p_7_32_0 - port map(wdata(31) => wdata(31), wdata(30) => wdata(30), - wdata(29) => wdata(29), wdata(28) => wdata(28), wdata(27) - => wdata(27), wdata(26) => wdata(26), wdata(25) => - wdata(25), wdata(24) => wdata(24), wdata(23) => wdata(23), - wdata(22) => wdata(22), wdata(21) => wdata(21), wdata(20) - => wdata(20), wdata(19) => wdata(19), wdata(18) => - wdata(18), wdata(17) => wdata(17), wdata(16) => wdata(16), - wdata(15) => wdata(15), wdata(14) => wdata(14), wdata(13) - => wdata(13), wdata(12) => wdata(12), wdata(11) => - wdata(11), wdata(10) => wdata(10), wdata(9) => wdata(9), - wdata(8) => wdata(8), wdata(7) => wdata(7), wdata(6) => - wdata(6), wdata(5) => wdata(5), wdata(4) => wdata(4), - wdata(3) => wdata(3), wdata(2) => wdata(2), wdata(1) => - wdata(1), wdata(0) => wdata(0), Waddr_vect_RNILLSP5(4) - => Waddr_vect_RNILLSP5(4), Waddr_vect_RNIJTNE5(3) => - Waddr_vect_RNIJTNE5(3), Waddr_vect_RNI394D5(2) => - Waddr_vect_RNI394D5(2), Waddr_vect_RNI0O455(1) => - Waddr_vect_RNI0O455(1), Waddr_vect_RNION355(0) => - Waddr_vect_RNION355(0), Raddr_vect_RNIIMQ5I(4) => - Raddr_vect_RNIIMQ5I(4), Raddr_vect_RNIE6Q5I(3) => - Raddr_vect_RNIE6Q5I(3), Raddr_vect_RNIKA2PH(2) => - Raddr_vect_RNIKA2PH(2), Raddr_vect_RNICA1PH(1) => - Raddr_vect_RNICA1PH(1), Raddr_vect_RNI4A0PH(0) => - Raddr_vect_RNI4A0PH(0), hwdata_c(31) => hwdata_c(31), - hwdata_c(30) => hwdata_c(30), hwdata_c(29) => - hwdata_c(29), hwdata_c(28) => hwdata_c(28), hwdata_c(27) - => hwdata_c(27), hwdata_c(26) => hwdata_c(26), - hwdata_c(25) => hwdata_c(25), hwdata_c(24) => - hwdata_c(24), hwdata_c(23) => hwdata_c(23), hwdata_c(22) - => hwdata_c(22), hwdata_c(21) => hwdata_c(21), - hwdata_c(20) => hwdata_c(20), hwdata_c(19) => - hwdata_c(19), hwdata_c(18) => hwdata_c(18), hwdata_c(17) - => hwdata_c(17), hwdata_c(16) => hwdata_c(16), - hwdata_c(15) => hwdata_c(15), hwdata_c(14) => - hwdata_c(14), hwdata_c(13) => hwdata_c(13), hwdata_c(12) - => hwdata_c(12), hwdata_c(11) => hwdata_c(11), - hwdata_c(10) => hwdata_c(10), hwdata_c(9) => hwdata_c(9), - hwdata_c(8) => hwdata_c(8), hwdata_c(7) => hwdata_c(7), - hwdata_c(6) => hwdata_c(6), hwdata_c(5) => hwdata_c(5), - hwdata_c(4) => hwdata_c(4), hwdata_c(3) => hwdata_c(3), - hwdata_c(2) => hwdata_c(2), hwdata_c(1) => hwdata_c(1), - hwdata_c(0) => hwdata_c(0), N_1_i_1_i => N_1_i_1_i, - generic_syncram_2p_7_32_0_VCC => syncram_2pZ1_VCC, - generic_syncram_2p_7_32_0_GND => syncram_2pZ1_GND, - sFull_RNIU5GK1 => sFull_RNIU5GK1, sFull_RNIHL443 => - sFull_RNIHL443, sEmpty_RNILSD08 => sEmpty_RNILSD08, - sEmpty_RNIE7T87 => sEmpty_RNIE7T87, N_1_i_1 => N_1_i_1, - HCLK_c => HCLK_c); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ2 is - - port( ready_i_0 : out std_logic_vector(2 to 2); - data_mem_wen_i_0 : out std_logic_vector(2 to 2); - data_ren : in std_logic_vector(2 to 2); - Waddr_vect_RNI0O455 : out std_logic_vector(1 to 1); - Waddr_vect_RNILLSP5 : out std_logic_vector(4 to 4); - Waddr_vect_RNIJTNE5 : out std_logic_vector(3 to 3); - Waddr_vect_RNI394D5 : out std_logic_vector(2 to 2); - data_mem_ren_i_0_0 : in std_logic; - data_addr_r_0_iv_i_2 : in std_logic_vector(5 to 5); - data_addr_w_iv_i_4 : in std_logic_vector(4 downto 0); - Waddr_vect_RNION355 : out std_logic_vector(0 to 0); - data_wen : in std_logic_vector(2 to 2); - data_addr_r_iv_i_a2_0 : in std_logic_vector(4 to 4); - data_addr_r_iv_i_a2_2 : out std_logic_vector(4 to 4); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_67 : out std_logic; - N_166 : in std_logic; - N_75 : out std_logic; - N_59 : out std_logic; - N_51 : out std_logic; - N_43 : out std_logic; - N_152 : in std_logic; - N_128 : in std_logic; - N_136 : in std_logic; - N_144 : in std_logic; - sEmpty_RNIE7T87 : out std_logic; - N_160 : in std_logic; - N_77 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ2; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ2 is - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \data_mem_addr_w_2[1]\, \data_mem_addr_w_2[0]\, - N_4, \data_mem_addr_w_2[3]\, \DWACT_FINC_E[0]\, N_12_0, - \data_mem_addr_r_2[1]\, \data_mem_addr_r_2[0]\, N_4_0, - \data_mem_addr_r_2[3]\, \DWACT_FINC_E_0[0]\, - \data_mem_ren_i_0[2]\, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \sEmpty_RNO_6\, - \sEmpty_RNO_7\, \un10_raddr_vect_s[1]\, \sEmpty_RNO_5\, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \un8_waddr_vect_s[3]\, sFull_RNO_8_0, un5_sfull_s_4_1, - \un8_waddr_vect_s[1]\, sFull_RNO_5_2, un5_sfull_s_4_0, - \un8_waddr_vect_s[0]\, ADD_7x7_fast_I23_Y_0_o2_0, N165_1, - N_89_i, N_109, ADD_5x5_fast_I11_Y_i_a2_1, - ADD_5x5_fast_I11_Y_i_a2_0, N_17, \data_mem_addr_r_2[2]\, - \data_mem_addr_w_2[2]\, SUM2_0_0, ADD_5x5_fast_I11_Y_0, - N80, un1_waddr_vect_slto3_0, un2_raddr_vect_slto3_0, - N_159, N_143, N_135, N_127, N_151, \un117_ready1[4]\, - N_87, CO1_tz, N_12_1, N_18, I11_un1_Y, N81, N77, N98, - un5_sfull_s_4, Waddr_vect_n4, \data_mem_addr_w_2[4]\, - Waddr_vect_14_0, N_58_i_0, Waddr_vect_c2, Waddr_vect_n3, - sFull_RNO_9, \sFull\, ADD_7x7_fast_I19_Y_i_a2_0_206, - N_9_i, N_105_1, Waddr_vect_n2, Waddr_vect_c1_i_0, - \sEmpty\, un1_sempty_s, sEmpty_RNO_10, un2_raddr_vect_s, - I_5_16, \un10_raddr_vect_s[2]\, I_9_16, - \un10_raddr_vect_s[3]\, I_13_16, \un10_raddr_vect_s[4]\, - I_20_8, I_5_15, I_13_15, \data_mem_addr_r_2[4]\, - \data_mem_wen_i_0[2]\, Waddr_vect_e1, Waddr_vect_n1_i, - Waddr_vect_e4, I_20_7, I_9_15, Waddr_vect_e3, - Waddr_vect_e0, N_85_i, N_24, N_75_0, \un132_ready1[4]\, - I8_un1_Y, \un132_ready0_1[4]\, \un117_ready0[4]\, N_6, - \un132_ready0[4]\, un119_readylto4, un134_ready, - un126_ready, N_198, N107, N161, N_197, \un132_ready1[5]\, - N_16_i_i_0, N_196, N_13, un2_raddr_vect_slto1, - Waddr_vect_e2, N_9, N_13_0, N_12_2, N_11, N_8, N_10, - N_9_0, N_7, N_4_1, N_5, N_6_0, N_9_1, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - data_mem_wen_i_0(2) <= \data_mem_wen_i_0[2]\; - - un117_ready_1_1_0_CO1_tz : AO18 - port map(A => N_105_1, B => \data_mem_addr_w_2[2]\, C => - \data_mem_addr_r_2[2]\, Y => CO1_tz); - - sFull : DFN1C0 - port map(D => sFull_RNO_9, CLK => HCLK_c, CLR => HRESETn_c, - Q => \sFull\); - - un117_ready_1_1_0_SUM2_0 : AX1C - port map(A => N_87, B => CO1_tz, C => SUM2_0_0, Y => - \un117_ready1[4]\); - - \ready_gen.un126_ready_0_I_11\ : OA1 - port map(A => N_13_0, B => N_12_2, C => N_11, Y => - un126_ready); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => N_58_i_0, B => \data_mem_wen_i_0[2]\, C => - \data_mem_addr_w_2[0]\, Y => Waddr_vect_e0); - - sFull_RNO_8 : AX1E - port map(A => N_58_i_0, B => I_20_7, C => - \data_mem_addr_r_2[4]\, Y => sFull_RNO_8_0); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0_0 : AO1C - port map(A => \data_mem_addr_r_2[2]\, B => - \data_mem_addr_w_2[2]\, C => N_109, Y => - ADD_5x5_fast_I11_Y_i_a2_0); - - sFull_RNO_6 : OR2A - port map(A => N_58_i_0, B => \data_mem_addr_w_2[0]\, Y => - \un8_waddr_vect_s[0]\); - - \Raddr_vect_RNIVJ63[1]\ : OR2B - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_r_2[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[0]\); - - \Raddr_vect_RNI53FB1[0]\ : MX2 - port map(A => \un117_ready1[4]\, B => \un117_ready0[4]\, S - => \data_mem_addr_r_2[0]\, Y => un119_readylto4); - - un132_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO1 - port map(A => N80, B => N_109, C => N_89_i, Y => - ADD_5x5_fast_I11_Y_0); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AO1A - port map(A => N165_1, B => N_89_i, C => N_109, Y => - ADD_7x7_fast_I23_Y_0_o2_0); - - \Waddr_vect_RNO[3]\ : MX2B - port map(A => \data_mem_addr_w_2[3]\, B => Waddr_vect_n3, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e3); - - \Waddr_vect_RNI394D5[2]\ : NOR3C - port map(A => data_addr_w_iv_i_4(2), B => N_143, C => N_144, - Y => Waddr_vect_RNI394D5(2)); - - \Raddr_vect_RNI8ULN5[0]\ : AOI1 - port map(A => N_197, B => N_196, C => N_198, Y => - un134_ready); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_r_2[0]\, Y => N_12_0); - - \Waddr_vect_RNION355[0]\ : NOR3C - port map(A => data_addr_w_iv_i_4(0), B => N_159, C => N_160, - Y => Waddr_vect_RNION355(0)); - - \Waddr_vect_RNIPN791[0]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[0]\, Y => N_159); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, Y => I_5_15); - - un132_ready_1_16_ADD_5x5_fast_I8_un1_Y : NOR2B - port map(A => N81, B => N77, Y => I8_un1_Y); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - un132_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75_0, Y => N_16_i_i_0); - - \Raddr_vect_RNI5KRC[4]\ : NOR2B - port map(A => I_9_16, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \Waddr_vect_RNIT7891[4]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[4]\, Y => N_127); - - un117_ready_0_0_0_ADD_5x5_fast_I18_Y_0 : XNOR2 - port map(A => N_6, B => N_89_i, Y => \un117_ready0[4]\); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_r_2[2]\, Y - => N_9); - - un117_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3 : NOR2 - port map(A => N_9_i, B => \data_mem_addr_r_2[2]\, Y => N_17); - - \Raddr_vect_RNI7073[2]\ : XNOR2 - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => N_85_i); - - \ready_gen.un126_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_2[4]\, B => - \data_mem_addr_w_2[4]\, Y => N_7); - - \Waddr_vect_RNO[4]\ : MX2B - port map(A => \data_mem_addr_w_2[4]\, B => Waddr_vect_n4, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e4); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[1]\); - - sFull_RNO_7 : OR2B - port map(A => I_13_15, B => N_58_i_0, Y => - \un8_waddr_vect_s[3]\); - - \Raddr_vect_RNIB3352[1]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[1]\, Y => N_67); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_2[3]\, Y => - I_13_15); - - GND_i : GND - port map(Y => \GND\); - - sEmpty_RNO_7 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_2[4]\, Y => \sEmpty_RNO_7\); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i : OR2B - port map(A => N_13, B => N_12_1, Y => N_6); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Raddr_vect_RNI5O63[1]\ : NOR2A - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, Y => N_105_1); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, C => \data_mem_addr_w_2[2]\, Y - => N_9_1); - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, C => N_58_i_0, Y => - Waddr_vect_n1_i); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_1 : OR2 - port map(A => ADD_5x5_fast_I11_Y_i_a2_0, B => N_17, Y => - ADD_5x5_fast_I11_Y_i_a2_1); - - \Raddr_vect[2]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[2]\); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2 : OR2 - port map(A => ADD_5x5_fast_I11_Y_i_a2_1, B => N_18, Y => - N_12_1); - - un132_ready_1_16_ADD_5x5_fast_I1_G0N : AO1C - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, C => N_87, Y => N80); - - \Waddr_vect_RNIS3891[3]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[3]\, Y => N_135); - - \Raddr_vect_RNIGJ408[0]\ : MX2 - port map(A => un119_readylto4, B => un134_ready, S => - un126_ready, Y => ready_i_0(2)); - - \Raddr_vect_RNI9873_0[3]\ : OR2A - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, Y => N_109); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_2[4]\, B => Waddr_vect_14_0, - C => N_58_i_0, Y => Waddr_vect_n4); - - un132_ready_1_16_ADD_5x5_fast_I0_CO1 : NOR2 - port map(A => N_105_1, B => N_85_i, Y => N77); - - VCC_i : VCC - port map(Y => \VCC\); - - sEmpty_RNIT8VB4 : NOR3C - port map(A => N_77, B => data_addr_r_iv_i_a2_0(4), C => - \data_mem_ren_i_0[2]\, Y => data_addr_r_iv_i_a2_2(4)); - - sEmpty_RNO : AO1A - port map(A => data_ren(2), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_10); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[3]\); - - \Raddr_vect_RNIAV252[0]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[0]\, Y => N_75); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, Y => N_12); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_2[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(2), Y => - un7_sempty_s_0); - - \Waddr_vect_RNIUG18[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => - Waddr_vect_c1_i_0, C => \data_mem_addr_w_2[4]\, Y => - N_58_i_0); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_2[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - \Raddr_vect_RNI5G18[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_2[4]\, Y => - un2_raddr_vect_s); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[4]\); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(2), - Y => sFull_RNO_9); - - \Raddr_vect_RNIA03G[4]\ : NOR2B - port map(A => I_20_8, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \ready_gen.un126_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, C => N_7, Y => N_12_2); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_2[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(2), Y => - un5_sfull_s_4_0); - - \ready_gen.un126_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, C => N_4_1, Y => N_10); - - un132_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : AX1A - port map(A => N165_1, B => N80, C => \un132_ready0_1[4]\, Y - => \un132_ready0[4]\); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_2[2]\, B => - Waddr_vect_c1_i_0, C => N_58_i_0, Y => Waddr_vect_n2); - - \ready_gen.un126_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, C => N_6_0, Y => N_8); - - \ready_gen.un126_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_w_2[0]\, Y => N_6_0); - - un132_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75_0, Y => \un132_ready1[5]\); - - \Raddr_vect[0]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[0]\); - - sFull_RNIDVR9 : NOR2 - port map(A => \sFull\, B => data_wen(2), Y => - \data_mem_wen_i_0[2]\); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_2[3]\, B => Waddr_vect_c2, C - => N_58_i_0, Y => Waddr_vect_n3); - - \ready_gen.un126_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, C => N_5, Y => N_9_0); - - \Waddr_vect_RNI0O455[1]\ : NOR3C - port map(A => data_addr_w_iv_i_4(1), B => N_151, C => N_152, - Y => Waddr_vect_RNI0O455(1)); - - un132_ready_1_16_ADD_5x5_fast_I1_P0N : OR3A - port map(A => \data_mem_addr_r_2[2]\, B => - \data_mem_addr_w_2[2]\, C => N_87, Y => N81); - - sEmpty_RNIBNF32 : OR2 - port map(A => \sEmpty\, B => data_ren(2), Y => - \data_mem_ren_i_0[2]\); - - \Raddr_vect_RNI4OK9[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_2[0]\, - Y => \un10_raddr_vect_s[0]\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_2[2]\, Y => - I_9_16); - - \sEmpty_RNIE7T87\ : NOR3B - port map(A => \data_mem_ren_i_0[2]\, B => - data_addr_r_0_iv_i_2(5), C => data_mem_ren_i_0_0, Y => - sEmpty_RNIE7T87); - - \Raddr_vect_RNIBG73[4]\ : XNOR2 - port map(A => \data_mem_addr_w_2[4]\, B => - \data_mem_addr_r_2[4]\, Y => N_89_i); - - \Waddr_vect_RNIRV791[2]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[2]\, Y => N_143); - - \Waddr_vect_RNIQR791[1]\ : OR3A - port map(A => \data_mem_wen_i_0[2]\, B => N_166, C => - \data_mem_addr_w_2[1]\, Y => N_151); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_2[3]\, B => - \un8_waddr_vect_s[3]\, C => sFull_RNO_8_0, Y => - un5_sfull_s_4_2); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_r_2[2]\, Y - => \DWACT_FINC_E_0[0]\); - - \ready_gen.un126_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, Y => N_4_1); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_2[3]\, Y - => Waddr_vect_14_0); - - \Raddr_vect_RNIC7352[2]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[2]\, Y => N_59); - - GND_i_0 : GND - port map(Y => GND_0); - - \Raddr_vect_RNI9873[3]\ : XNOR2 - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, Y => N_87); - - \Raddr_vect_RNI3473[3]\ : NOR2 - port map(A => \data_mem_addr_r_2[3]\, B => - \data_mem_addr_r_2[2]\, Y => un2_raddr_vect_slto3_0); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR2A - port map(A => N_75_0, B => \un117_ready0[4]\, Y => N161); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_2[4]\, Y => I_20_7); - - \Raddr_vect[1]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[1]\); - - un132_ready_0_0_0_ADD_7x7_fast_I19_Y_i_a2_0_206 : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => - ADD_7x7_fast_I19_Y_i_a2_0_206); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[3]\, B => - \data_mem_addr_w_2[3]\, Y => \sEmpty_RNO_6\); - - \Raddr_vect_RNIBG73_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_2[4]\, B => - \data_mem_addr_w_2[4]\, Y => N_75_0); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_2[3]\, Y => - I_13_16); - - \ready_gen.un126_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_2[4]\, B => - \data_mem_addr_r_2[4]\, Y => N_11); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \data_mem_addr_w_2[2]\, B => Waddr_vect_n2, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e2); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_2[1]\, B => - \un10_raddr_vect_s[1]\, C => \sEmpty_RNO_5\, Y => - un7_sempty_s_1); - - \Raddr_vect_RNISJHJ1[0]\ : MX2C - port map(A => \un132_ready1[4]\, B => \un132_ready0[4]\, S - => \data_mem_addr_r_2[0]\, Y => N_196); - - sEmpty_RNO_4 : NOR2B - port map(A => \sEmpty_RNO_6\, B => \sEmpty_RNO_7\, Y => - un7_sempty_s_2); - - sFull_RNO_5 : AX1E - port map(A => N_58_i_0, B => I_9_15, C => - \data_mem_addr_r_2[2]\, Y => sFull_RNO_5_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, Y => I_5_16); - - \Waddr_vect_RNIJTNE5[3]\ : NOR3C - port map(A => data_addr_w_iv_i_4(3), B => N_135, C => N_136, - Y => Waddr_vect_RNIJTNE5(3)); - - un117_ready_1_1_0_SUM2_0_0 : XNOR2 - port map(A => N_109, B => N_89_i, Y => SUM2_0_0); - - \Waddr_vect_RNI9K63[0]\ : OR2B - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, Y => Waddr_vect_c1_i_0); - - un132_ready_1_16_ADD_5x5_fast_I15_Y_0 : AX1A - port map(A => I8_un1_Y, B => N80, C => \un132_ready0_1[4]\, - Y => \un132_ready1[4]\); - - \ready_gen.un126_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13_0); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_10, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \data_mem_addr_w_2[1]\, B => Waddr_vect_n1_i, - S => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e1); - - \Raddr_vect_RNI448B[4]\ : NOR2B - port map(A => I_5_16, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_2[2]\); - - un132_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1 : OA1B - port map(A => ADD_7x7_fast_I19_Y_i_a2_0_206, B => N_87, C - => N_9_i, Y => N165_1); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, C => \data_mem_addr_w_2[2]\, Y - => \DWACT_FINC_E[0]\); - - un117_ready_0_0_0_ADD_5x5_fast_I9_Y_i_o2 : AO18 - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_w_2[0]\, Y - => N_9_i); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : AO1A - port map(A => N165_1, B => N80, C => N_89_i, Y => N_24); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_2[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_2, Y => - un5_sfull_s_4_1); - - \Waddr_vect_RNILLSP5[4]\ : NOR3C - port map(A => data_addr_w_iv_i_4(4), B => N_127, C => N_128, - Y => Waddr_vect_RNILLSP5(4)); - - un132_ready_1_16_ADD_5x5_fast_I10_Y : OR2B - port map(A => I11_un1_Y, B => N_75_0, Y => N107); - - un132_ready_0_0_0_ADD_7x7_fast_I32_Y_0_1 : XOR2 - port map(A => N_109, B => N_89_i, Y => \un132_ready0_1[4]\); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[3]\); - - sFull_RNO_4 : OR2B - port map(A => I_5_15, B => N_58_i_0, Y => - \un8_waddr_vect_s[1]\); - - \Raddr_vect_RNI78FE[4]\ : NOR2B - port map(A => I_13_16, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_2[2]\, Y => \sEmpty_RNO_5\); - - \Waddr_vect_RNID473[3]\ : NOR2 - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_w_2[2]\, Y => un1_waddr_vect_slto3_0); - - un117_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3_0 : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => N_9_i, Y => N_18); - - un132_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - \ready_gen.un126_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => N_5); - - \Raddr_vect_RNI245L1[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_2[0]\, - Y => N_198); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_2[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - \Waddr_vect_RNIF4Q4[2]\ : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => - Waddr_vect_c1_i_0, Y => Waddr_vect_c2); - - \Raddr_vect_RNIA6VE2[0]\ : MX2C - port map(A => \un132_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_2[0]\, Y => N_197); - - \Raddr_vect[4]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[4]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_2[2]\, Y => - I_9_15); - - un117_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0 : OR2A - port map(A => \data_mem_addr_r_2[3]\, B => - \data_mem_addr_w_2[3]\, Y => N_13); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(2), Y => un1_sempty_s); - - \Raddr_vect_RNIDB352[3]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[3]\, Y => N_51); - - \Raddr_vect_RNIEF352[4]\ : OR2 - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_addr_r_2[4]\, Y => N_43); - - un132_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_109, B => N_89_i, Y => N98); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_2[4]\, Y => - I_20_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ5 is - - port( time_mem_wen_i_0_0 : in std_logic; - Waddr_vect_RNINV58 : out std_logic_vector(2 to 2); - Waddr_vect_RNILN58 : out std_logic_vector(0 to 0); - Raddr_vect_RNI8J9L : out std_logic_vector(2 to 2); - time_mem_ren_i_0 : out std_logic_vector(1 to 1); - time_wen : in std_logic_vector(1 to 1); - time_ren : in std_logic_vector(1 to 1); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_146 : out std_logic; - N_162 : out std_logic; - N_113 : out std_logic; - N_122 : out std_logic; - sFull_RNIPQBB_0 : out std_logic; - N_62 : out std_logic; - N_70 : out std_logic; - sEmpty_RNI5EFO_0 : out std_logic; - N_33 : out std_logic; - N_29 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ5; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ5 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \time_mem_addr_r_1[5]\, \Raddr_vect[2]_net_1\, - \Raddr_vect[3]_net_1\, \DWACT_FINC_E[0]\, - \time_mem_addr_w_1[5]\, \Waddr_vect[2]_net_1\, - \Waddr_vect[3]_net_1\, \DWACT_FINC_E_0[0]\, N_7, - \time_mem_addr_r_1[1]\, \time_mem_addr_r_1[0]\, N_7_0, - \time_mem_addr_w_1[1]\, \time_mem_addr_w_1[0]\, - un5_sfull_s_2, \un8_waddr_vect_s[3]\, un5_sfull_s_1, - \un8_waddr_vect_s[1]\, sFull_RNO_5_0, un5_sfull_s_0, - \un8_waddr_vect_s[0]\, un7_sempty_s_3, sEmpty_RNO_3_1, - sEmpty_RNO_4_1, un7_sempty_s_0, un7_sempty_s_2, - \un10_raddr_vect_s[3]\, \un10_raddr_vect_s[0]\, - un1_waddr_vect_slt3, un5_sfull_s, un2_raddr_vect_slt3, - Raddr_vect_n3, Raddr_vect_7_0, Waddr_vect_n3, - Waddr_vect_15_0, Raddr_vect_n2, un2_raddr_vect_s, - Raddr_vect_n2_tz, Waddr_vect_n2, un1_waddr_vect_s, - Waddr_vect_n2_tz, \time_mem_ren_i_0[1]\, - \time_mem_addr_r_1[3]\, N_167, I_9_10, Raddr_vect_n1_i, - Raddr_vect_e2, Raddr_vect_e1, Raddr_vect_e0, I_13_10, - I_9_9, I_5_10, Waddr_vect_n1_i, Waddr_vect_e2, - \time_mem_wen_i_0[1]\, Waddr_vect_e1, Waddr_vect_e0, - I_13_9, I_5_9, \sFull_RNO_2\, \sFull\, \sEmpty_RNO_2\, - un2_sempty_s, \sEmpty\, \time_mem_addr_w_1[3]\, N_4, - N_4_0, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - time_mem_ren_i_0(1) <= \time_mem_ren_i_0[1]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_1[1]\, B => - \time_mem_addr_w_1[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4); - - sFull_RNIPQBB_1 : NOR2 - port map(A => \time_mem_addr_w_1[5]\, B => N_167, Y => - N_122); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_1[1]\, B => - \time_mem_addr_r_1[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - sEmpty_RNI5EFO_1 : NOR2 - port map(A => \time_mem_ren_i_0[1]\, B => - \time_mem_addr_r_1[5]\, Y => N_33); - - un36_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_1[5]\); - - un36_mem_addr_wen_I_16 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => \DWACT_FINC_E_0[0]\); - - \Waddr_vect_RNI0PG9[1]\ : OR3 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_1[1]\, B => - \time_mem_addr_w_1[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_2\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_1[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_wen_i_0[1]\, Q => - \Waddr_vect[3]_net_1\); - - sEmpty_RNI5EFO : OR2A - port map(A => \DWACT_FINC_E[0]\, B => \time_mem_ren_i_0[1]\, - Y => N_29); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_10); - - \Raddr_vect_RNI7F9L[1]\ : OR2 - port map(A => \time_mem_ren_i_0[1]\, B => - \time_mem_addr_r_1[1]\, Y => N_62); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_2\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[1]\, - C => \time_mem_addr_w_1[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Waddr_vect[2]_net_1\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_1[1]\, - S => \time_mem_wen_i_0[1]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, Y => I_5_9); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - sFull_RNIM805_0 : OR2A - port map(A => time_mem_wen_i_0_0, B => - \time_mem_wen_i_0[1]\, Y => N_167); - - sFull_RNIPQBB : OR2A - port map(A => \DWACT_FINC_E_0[0]\, B => N_167, Y => N_113); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_ren_i_0[1]\, Q => - \Raddr_vect[3]_net_1\); - - \sFull_RNIPQBB_0\ : OR2 - port map(A => \time_mem_addr_w_1[3]\, B => N_167, Y => - sFull_RNIPQBB_0); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(1), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4, B => \Waddr_vect[3]_net_1\, Y => I_13_9); - - un31_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_1[3]\); - - sFull_RNO : AO1 - port map(A => time_ren(1), B => \sFull\, C => un5_sfull_s, - Y => \sFull_RNO_2\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[1]\, - C => \time_mem_addr_r_1[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_1[1]\, - S => \time_mem_ren_i_0[1]\, Y => Raddr_vect_e1); - - sFull_RNIM805 : OR2B - port map(A => \time_mem_wen_i_0[1]\, B => - time_mem_wen_i_0_0, Y => N_162); - - sFull_RNO_4 : OR2B - port map(A => I_5_9, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_1[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_10, C => - \Waddr_vect[2]_net_1\, Y => sEmpty_RNO_3_1); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Raddr_vect[2]_net_1\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_1[0]\); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_9, C => - \Raddr_vect[2]_net_1\, Y => sFull_RNO_5_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[1]\, Y => Waddr_vect_e2); - - un31_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_1[5]\); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_10, C => - \time_mem_addr_w_1[1]\, Y => sEmpty_RNO_4_1); - - sFull_RNO_3 : XA1 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, C => time_ren(1), Y => - un5_sfull_s_2); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_1, B => sEmpty_RNO_4_1, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un36_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_1[3]\); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - sEmpty_RNO_7 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_1[0]\, - Y => \un10_raddr_vect_s[0]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[1]\, Y => Raddr_vect_e2); - - \Raddr_vect_RNIEJMC[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_1[0]\); - - \sEmpty_RNI5EFO_0\ : OR2 - port map(A => \time_mem_ren_i_0[1]\, B => - \time_mem_addr_r_1[3]\, Y => sEmpty_RNI5EFO_0); - - \Raddr_vect_RNIHOG9[1]\ : OR3 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - \Waddr_vect_RNINV58[2]\ : OR2A - port map(A => \Waddr_vect[2]_net_1\, B => N_167, Y => - Waddr_vect_RNINV58(2)); - - \Raddr_vect_RNI8J9L[2]\ : OR2A - port map(A => \Raddr_vect[2]_net_1\, B => - \time_mem_ren_i_0[1]\, Y => Raddr_vect_RNI8J9L(2)); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_1[1]\, B => - \time_mem_addr_r_1[0]\, Y => N_7); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => I_9_9); - - sFull_RNIC4G2 : OR2 - port map(A => time_wen(1), B => \sFull\, Y => - \time_mem_wen_i_0[1]\); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_0, B => \Raddr_vect[3]_net_1\, Y => - I_13_10); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_0); - - sEmpty_RNO_1 : XA1B - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, C => time_ren(1), Y => - un7_sempty_s_2); - - sFull_RNO_1 : XA1 - port map(A => \un8_waddr_vect_s[1]\, B => - \time_mem_addr_r_1[1]\, C => sFull_RNO_5_0, Y => - un5_sfull_s_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, Y => I_5_10); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - sFull_RNO_7 : OR2B - port map(A => I_13_9, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - \Raddr_vect_RNI6B9L[0]\ : OR2 - port map(A => \time_mem_ren_i_0[1]\, B => - \time_mem_addr_r_1[0]\, Y => N_70); - - \Waddr_vect_RNIMR58[1]\ : OR2 - port map(A => \time_mem_addr_w_1[1]\, B => N_167, Y => - N_146); - - \Waddr_vect_RNILN58[0]\ : OR2 - port map(A => \time_mem_addr_w_1[0]\, B => N_167, Y => - Waddr_vect_RNILN58(0)); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - un31_mem_addr_ren_I_16 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_1, B => un5_sfull_s_0, C => - un5_sfull_s_2, Y => un5_sfull_s); - - sEmpty_RNO_6 : OR2B - port map(A => I_13_10, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - sFull : DFN1C0 - port map(D => \sFull_RNO_2\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Waddr_vect_RNI2KMC[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_1[1]\); - - sFull_RNO_2 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_1[0]\, C => time_wen(1), Y => - un5_sfull_s_0); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_1[0]\, C => time_wen(1), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - sEmpty_RNICS3I : OR2 - port map(A => time_ren(1), B => \sEmpty\, Y => - \time_mem_ren_i_0[1]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ3 is - - port( ready_i_0 : out std_logic_vector(3 to 3); - data_mem_wen_i_0_0 : in std_logic; - data_ren : in std_logic_vector(3 to 3); - data_wen : in std_logic_vector(3 to 3); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_128 : out std_logic; - N_152 : out std_logic; - N_136 : out std_logic; - N_68 : out std_logic; - N_144 : out std_logic; - N_166 : in std_logic; - N_160 : out std_logic; - N_76 : out std_logic; - N_60 : out std_logic; - N_52 : out std_logic; - N_86 : in std_logic; - N_44 : out std_logic; - N_1_i_1 : out std_logic; - N_1_i_1_i : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ3; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ3 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \data_mem_addr_w_3[1]\, \data_mem_addr_w_3[0]\, - N_4, \data_mem_addr_w_3[3]\, \DWACT_FINC_E[0]\, N_12_0, - \data_mem_addr_r_3[1]\, \data_mem_addr_r_3[0]\, N_4_0, - \data_mem_addr_r_3[3]\, \DWACT_FINC_E_0[0]\, - un7_sempty_s_4, un7_sempty_s_1, un7_sempty_s_0, - un7_sempty_s_2, \un10_raddr_vect_s[3]\, sEmpty_RNO_6_0, - \un10_raddr_vect_s[1]\, sEmpty_RNO_5_0, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \un8_waddr_vect_s[3]\, \sFull_RNO_8\, un5_sfull_s_4_1, - \un8_waddr_vect_s[1]\, sFull_RNO_5_1, un5_sfull_s_4_0, - \un8_waddr_vect_s[0]\, ADD_7x7_fast_I23_Y_0_o2_0, N165_1, - \un174_ready0_1[4]\, N_11, ADD_5x5_fast_I11_Y_0, N80, - ADD_5x5_fast_I11_Y_i_a2_0, \data_mem_addr_w_3[2]\, - \data_mem_addr_r_3[2]\, \un189_ready0_1[4]\, - ADD_7x7_fast_I19_Y_i_o4_1_0, N_87, un1_waddr_vect_slto3_0, - un2_raddr_vect_slto3_0, I11_un1_Y, N81, N77, N98, N_12_1, - N_17, N_18, \un174_ready1[4]\, CO1_tz, un5_sfull_s_4, N_9, - Waddr_vect_n4, \data_mem_addr_w_3[4]\, Waddr_vect_14_0, - un1_waddr_vect_s, Waddr_vect_c2, Waddr_vect_n2, - Waddr_vect_c1, Waddr_vect_n3, N_105, \sFull_RNO_6\, - \sFull\, un1_sempty_s, \sEmpty\, sEmpty_RNO_8, I_5_11, - I_13_11, un2_raddr_vect_s, un2_raddr_vect_slto1, - \data_mem_addr_r_3[4]\, \un10_raddr_vect_s[2]\, - \un10_raddr_vect_s[4]\, \N_1_i_1\, \data_mem_wen_i_0[3]\, - N_75, N_24, N165, Waddr_vect_e2, Waddr_vect_e3, - Waddr_vect_e4, N111, N107, \un189_ready1_i[5]\, N_13, - N161, N_16_i, un191_ready, N_197_i, N_196_i, N_198, - \un189_ready1[4]\, \un189_ready0[4]\, un176_readylto4_i_0, - \un174_ready0[4]\, un183_ready, Waddr_vect_e0, - Waddr_vect_e1, Waddr_vect_n1_i, I_20_3, I_9_11, I_20_4, - I_13_12, I_9_12, I_5_12, sREN, N_9_0, N_13_0, N_12_2, - N_11_0, N_8, N_10, N_9_1, N_7, N_4_1, N_5, N_6, N_9_2, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - N_1_i_1 <= \N_1_i_1\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, C => \data_mem_addr_w_3[2]\, Y - => N_9_2); - - un189_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR3A - port map(A => N_75, B => N_24, C => - ADD_7x7_fast_I23_Y_0_o2_0, Y => N161); - - \ready_gen.un183_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, C => N_7, Y => N_12_2); - - un189_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4 : OR2B - port map(A => N80, B => N165_1, Y => N165); - - \ready_gen.un183_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_w_3[0]\, Y => N_6); - - \Raddr_vect_RNIDKRC[4]\ : NOR2B - port map(A => I_9_12, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \Raddr_vect_RNI3FG82[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_3[0]\, - Y => N_198); - - un189_ready_1_16_ADD_5x5_fast_I11_Y_0 : MIN3 - port map(A => \un174_ready0_1[4]\, B => N_11, C => N80, Y - => ADD_5x5_fast_I11_Y_0); - - un189_ready_1_16_ADD_5x5_fast_I1_G0N : AO1C - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, C => N_87, Y => N80); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, C => \data_mem_addr_r_3[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, Y => N_12); - - sEmpty_RNO : AO1A - port map(A => data_ren(3), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_8); - - \Raddr_vect_RNIJBIK8[3]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[3]\, Y => N_52); - - \ready_gen.un183_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, Y => N_4_1); - - \Raddr_vect[1]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[3]\); - - un189_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : NOR2A - port map(A => N165, B => \un174_ready0_1[4]\, Y => N_24); - - \ready_gen.un183_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, Y => N_5); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_3[2]\, Y => - I_9_12); - - \Raddr_vect_RNIAG18[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_3[4]\, Y => - un2_raddr_vect_s); - - \Raddr_vect_RNISKHJ1[0]\ : MX2C - port map(A => \un189_ready1[4]\, B => \un189_ready0[4]\, S - => \data_mem_addr_r_3[0]\, Y => N_196_i); - - \Waddr_vect_RNO[4]\ : MX2A - port map(A => Waddr_vect_n4, B => \data_mem_addr_w_3[4]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e4); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_8, CLK => HCLK_c, PRE => HRESETn_c, - Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[3]\, - C => \data_mem_addr_w_3[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[2]\); - - \ready_gen.un183_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, C => N_5, Y => N_9_1); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \data_mem_addr_w_3[1]\, - S => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - un174_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0_0 : OA1A - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, C => N_11, Y => - ADD_5x5_fast_I11_Y_i_a2_0); - - \Raddr_vect_RNIK03G[4]\ : NOR2B - port map(A => I_20_4, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_3[2]\, B => Waddr_vect_c1, C - => un1_waddr_vect_s, Y => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, Y => I_5_11); - - \Raddr_vect_RNIGVHK8[0]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[0]\, Y => N_76); - - un174_ready_1_1_0_CO1_tz : AO18 - port map(A => N_105, B => \data_mem_addr_w_3[2]\, C => - \data_mem_addr_r_3[2]\, Y => CO1_tz); - - \Waddr_vect_RNIRR791[1]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[1]\, Y => N_152); - - \ready_gen.un183_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, C => N_4_1, Y => N_10); - - un189_ready_1_16_ADD_5x5_fast_I15_Y_0 : XOR2 - port map(A => N111, B => \un189_ready0_1[4]\, Y => - \un189_ready1[4]\); - - \Raddr_vect_RNIR7VE2[0]\ : MX2 - port map(A => \un189_ready1_i[5]\, B => N_16_i, S => - \data_mem_addr_r_3[0]\, Y => N_197_i); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[3]\); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_3[1]\, B => - \un10_raddr_vect_s[1]\, C => sEmpty_RNO_5_0, Y => - un7_sempty_s_1); - - \ready_gen.un183_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_3[4]\, B => - \data_mem_addr_w_3[4]\, Y => N_7); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_2, B => \data_mem_addr_w_3[3]\, Y => - I_13_11); - - un174_ready_1_1_0_SUM2_0_0 : XOR2 - port map(A => N_11, B => \un174_ready0_1[4]\, Y => - \un189_ready0_1[4]\); - - \Waddr_vect_RNIBK63[0]\ : OR2B - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, Y => Waddr_vect_c1); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(3), - Y => \sFull_RNO_6\); - - un189_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1B - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75, Y => N_16_i); - - un189_ready_1_16_ADD_5x5_fast_I11_un1_Y : NOR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - un189_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : XOR2 - port map(A => N165, B => \un189_ready0_1[4]\, Y => - \un189_ready0[4]\); - - \Raddr_vect_RNII7IK8[2]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[2]\, Y => N_60); - - sFull_RNO_4 : OR2B - port map(A => I_5_11, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_3[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_3[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(3), Y => - un7_sempty_s_0); - - \Raddr_vect[2]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[2]\); - - \Raddr_vect_RNIQB1B6[0]\ : AO1 - port map(A => N_197_i, B => N_196_i, C => N_198, Y => - un191_ready); - - un189_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1 : OR2B - port map(A => ADD_7x7_fast_I19_Y_i_o4_1_0, B => N_9, Y => - N165_1); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[0]\); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_3, C => - \data_mem_addr_r_3[4]\, Y => \sFull_RNO_8\); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_3[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - un174_ready_0_0_0_ADD_5x5_fast_I11_Y_i_o2 : OR2A - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, Y => N_11); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_11, C => - \data_mem_addr_r_3[2]\, Y => sFull_RNO_5_1); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \data_mem_addr_w_3[2]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e2); - - \Raddr_vect_RNI5473[3]\ : NOR2 - port map(A => \data_mem_addr_r_3[3]\, B => - \data_mem_addr_r_3[2]\, Y => un2_raddr_vect_slto3_0); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_3[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_6_0, Y => - un7_sempty_s_2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_3[3]\, Y - => Waddr_vect_14_0); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_3[3]\, B => - \un8_waddr_vect_s[3]\, C => \sFull_RNO_8\, Y => - un5_sfull_s_4_2); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - sEmpty_RNICNF32 : OR2 - port map(A => \sEmpty\, B => data_ren(3), Y => sREN); - - \ready_gen.un183_ready_0_I_11\ : OA1 - port map(A => N_13_0, B => N_12_2, C => N_11_0, Y => - un183_ready); - - \Raddr_vect_RNIAOK9[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_3[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Raddr_vect_RNIB48B[4]\ : NOR2B - port map(A => I_5_12, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNIDG73[4]\ : NOR2A - port map(A => \data_mem_addr_r_3[4]\, B => - \data_mem_addr_w_3[4]\, Y => N_75); - - \Raddr_vect_RNIF2GJ8[0]\ : MX2 - port map(A => un176_readylto4_i_0, B => un191_ready, S => - un183_ready, Y => ready_i_0(3)); - - un174_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3 : OR2A - port map(A => N_9, B => \data_mem_addr_r_3[2]\, Y => N_17); - - \Raddr_vect[0]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[0]\); - - un189_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_11, B => \un174_ready0_1[4]\, Y => N98); - - un174_ready_0_0_0_ADD_5x5_fast_I18_Y_0_1 : XNOR2 - port map(A => \data_mem_addr_w_3[4]\, B => - \data_mem_addr_r_3[4]\, Y => \un174_ready0_1[4]\); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_r_3[0]\, Y => N_12_0); - - un189_ready_1_16_ADD_5x5_fast_I8_Y : AO1B - port map(A => N81, B => N77, C => N80, Y => N111); - - un189_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1B - port map(A => \data_mem_addr_r_3[2]\, B => - \data_mem_addr_w_3[2]\, C => N_105, Y => N77); - - \Waddr_vect_RNI3H18[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => Waddr_vect_c1, C - => \data_mem_addr_w_3[4]\, Y => un1_waddr_vect_s); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_3[2]\, Y => - I_9_11); - - sFull_RNI4FGH1_0 : INV - port map(A => \N_1_i_1\, Y => N_1_i_1_i); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9_0, B => \data_mem_addr_r_3[3]\, Y => - I_13_12); - - un174_ready_0_0_0_ADD_5x5_fast_I18_Y_0 : AX1C - port map(A => N_12_1, B => N_13, C => \un174_ready0_1[4]\, - Y => \un174_ready0[4]\); - - \Raddr_vect_RNI04FB1[0]\ : MX2C - port map(A => \un174_ready1[4]\, B => \un174_ready0[4]\, S - => \data_mem_addr_r_3[0]\, Y => un176_readylto4_i_0); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, C => \data_mem_addr_r_3[2]\, Y - => N_9_0); - - un189_ready_1_16_ADD_5x5_fast_I10_Y : AO1B - port map(A => N111, B => N98, C => N_75, Y => N107); - - \ready_gen.un183_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_1, Y => N_13_0); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(3), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_3[4]\, Y => - I_20_4); - - \Raddr_vect_RNIB873[3]\ : XNOR2 - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, Y => N_87); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_3[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_1, Y => - un5_sfull_s_4_1); - - \Waddr_vect_RNIT3891[3]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[3]\, Y => N_136); - - \Waddr_vect_RNII4Q4[2]\ : NOR2A - port map(A => \data_mem_addr_w_3[2]\, B => Waddr_vect_c1, Y - => Waddr_vect_c2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, Y => I_5_12); - - un189_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AOI1 - port map(A => N165_1, B => \un174_ready0_1[4]\, C => N_11, - Y => ADD_7x7_fast_I23_Y_0_o2_0); - - un174_ready_0_0_0_ADD_5x5_fast_I9_Y_i_o2 : AO13 - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, C => \data_mem_addr_r_3[1]\, Y - => N_9); - - \Waddr_vect_RNIF473[3]\ : NOR2 - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_w_3[2]\, Y => un1_waddr_vect_slto3_0); - - un189_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1B - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75, Y => \un189_ready1_i[5]\); - - \Raddr_vect_RNI7O63[1]\ : NOR2A - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, Y => N_105); - - \Raddr_vect_RNI1K63[1]\ : OR2B - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_r_3[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_3[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[4]\); - - sFull_RNO_7 : OR2B - port map(A => I_13_11, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Waddr_vect_RNIU7891[4]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[4]\, Y => N_128); - - \Waddr_vect_RNIQN791[0]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[0]\, Y => N_160); - - un174_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3_0 : OR2B - port map(A => N_9, B => \data_mem_addr_w_3[2]\, Y => N_18); - - sFull_RNI4FGH1 : OR3A - port map(A => \data_mem_wen_i_0[3]\, B => N_166, C => - data_mem_wen_i_0_0, Y => \N_1_i_1\); - - \Waddr_vect_RNO[3]\ : MX2A - port map(A => Waddr_vect_n3, B => \data_mem_addr_w_3[3]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e3); - - un189_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXOI5 - port map(A => N_87, B => \data_mem_addr_r_3[2]\, C => - \data_mem_addr_w_3[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - un174_ready_1_1_0_SUM2_0 : AX1E - port map(A => N_87, B => CO1_tz, C => \un189_ready0_1[4]\, - Y => \un174_ready1[4]\); - - un174_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2 : OR3C - port map(A => N_17, B => ADD_5x5_fast_I11_Y_i_a2_0, C => - N_18, Y => N_12_1); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_3[4]\, Y => sEmpty_RNO_6_0); - - \Waddr_vect_RNISV791[2]\ : OR3 - port map(A => N_166, B => data_mem_wen_i_0_0, C => - \data_mem_addr_w_3[2]\, Y => N_144); - - sFull : DFN1C0 - port map(D => \sFull_RNO_6\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Raddr_vect_RNIG8FE[4]\ : NOR2B - port map(A => I_13_12, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_3[4]\, Y => I_20_3); - - \ready_gen.un183_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_3[4]\, B => - \data_mem_addr_r_3[4]\, Y => N_11_0); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_3[1]\); - - \ready_gen.un183_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, C => N_6, Y => N_8); - - \Raddr_vect[4]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => sREN, Q => \data_mem_addr_r_3[4]\); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_3[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(3), Y => - un5_sfull_s_4_0); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_3[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - un174_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0 : OR2A - port map(A => \data_mem_addr_r_3[3]\, B => - \data_mem_addr_w_3[3]\, Y => N_13); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_3[2]\, Y => sEmpty_RNO_5_0); - - \Raddr_vect_RNIKFIK8[4]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[4]\, Y => N_44); - - \Raddr_vect_RNIH3IK8[1]\ : OR2A - port map(A => N_86, B => \data_mem_addr_r_3[1]\, Y => N_68); - - sFull_RNIFVR9 : OR2 - port map(A => \sFull\, B => data_wen(3), Y => - \data_mem_wen_i_0[3]\); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_3[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, C => \data_mem_addr_w_3[2]\, Y - => \DWACT_FINC_E[0]\); - - un189_ready_1_16_ADD_5x5_fast_I1_P0N : OR3A - port map(A => \data_mem_addr_r_3[2]\, B => - \data_mem_addr_w_3[2]\, C => N_87, Y => N81); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ0 is - - port( ready_i_0 : out std_logic_vector(0 to 0); - data_ren : in std_logic_vector(0 to 0); - data_addr_w_0_iv_i_1 : in std_logic_vector(5 to 5); - data_addr_r_1_iv_i_s_1 : in std_logic_vector(6 to 6); - data_addr_r_1_iv_i_a9_1_1 : in std_logic_vector(6 to 6); - data_mem_ren_i_0 : out std_logic_vector(0 to 0); - data_mem_wen_i_0_1 : in std_logic; - data_addr_w_1_iv_i_a2_1_1_0 : out std_logic_vector(6 to 6); - data_addr_w_iv_i_2 : in std_logic_vector(4 downto 0); - data_addr_w_iv_i_4 : out std_logic_vector(4 downto 0); - data_wen : in std_logic_vector(0 to 0); - data_addr_r_iv_i_0 : in std_logic_vector(4 downto 0); - data_addr_r_iv_i_1 : in std_logic_vector(4 downto 0); - data_addr_r_iv_i_3 : out std_logic_vector(4 downto 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_165 : out std_logic; - N_120_i : in std_logic; - sFull_RNIHL443 : out std_logic; - sEmpty_RNILSD08 : out std_logic; - N_124 : in std_logic; - N_164 : in std_logic; - N_158 : in std_logic; - N_142 : in std_logic; - N_134 : in std_logic; - N_126 : in std_logic; - N_150 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ0; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ0 is - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \data_mem_addr_w_0[1]\, \data_mem_addr_w_0[0]\, - N_4, \data_mem_addr_w_0[3]\, \DWACT_FINC_E[0]\, N_12_0, - \data_mem_addr_r_0[1]\, \data_mem_addr_r_0[0]\, N_4_0, - \data_mem_addr_r_0[3]\, \DWACT_FINC_E_0[0]\, N_65, N_41, - N_49, N_57, N_73, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \un10_raddr_vect_s[3]\, - sEmpty_RNO_6_1, \un10_raddr_vect_s[1]\, sEmpty_RNO_5_1, - \un10_raddr_vect_s[0]\, N_149, N_125, N_133, N_141, N_157, - un5_sfull_s_4_2, \un8_waddr_vect_s[3]\, sFull_RNO_8_1, - un5_sfull_s_4_1, \un8_waddr_vect_s[1]\, sFull_RNO_5_3, - un5_sfull_s_4_0, \un8_waddr_vect_s[0]\, - \data_addr_w_0_iv_i_3[5]\, \data_mem_wen_i_0[0]\, - ADD_7x7_fast_I23_Y_0_o2_0, N165_1, N_89_i, N_109, - ADD_5x5_fast_I11_Y_0, N80, ADD_5x5_fast_I11_Y_i_a2_0, - \data_mem_addr_r_0[2]\, \data_mem_addr_w_0[2]\, SUM2_0_0, - ADD_7x7_fast_I19_Y_i_o4_1_0, N_87, un1_waddr_vect_slto3_0, - un2_raddr_vect_slto3_0, I11_un1_Y, N81, N77, N98, - \un3_ready1[4]\, CO1_tz, N_12_1, N_17, N_18, - un5_sfull_s_4, ADD_5x5_fast_I9_Y_i_o2_0, Waddr_vect_c1, - Waddr_vect_n4, \data_mem_addr_w_0[4]\, Waddr_vect_14_0, - un1_waddr_vect_s, Waddr_vect_c2, \sFull_RNO_7\, \sFull\, - Waddr_vect_n2, Waddr_vect_n3, N_84_1, - \data_mem_ren_i_0[0]\, \sEmpty\, un2_raddr_vect_s, I_5_14, - \un10_raddr_vect_s[2]\, I_9_14, I_13_14, - \un10_raddr_vect_s[4]\, I_20_6, un2_raddr_vect_slto1, - \data_mem_addr_r_0[4]\, I_9_13, ADD_5x5_fast_I8_un1_Y, - sEmpty_RNO_9, un1_sempty_s, N_75, Waddr_vect_e0, - Waddr_vect_e1, Waddr_vect_n1_i, Waddr_vect_e2, - Waddr_vect_e3, Waddr_vect_e4, \un18_ready1[4]\, - \un18_ready0_1[4]\, \un3_ready0[4]\, N_6, - \un18_ready0[4]\, un5_readylto4, un20_ready, un12_ready, - N_198, N107, N161, N_197, \un18_ready1[5]\, N_16_i_i_0, - N_196, N_24, N_13, I_20_5, I_13_13, I_5_13, N_9, N_13_0, - N_12_2, N_11, N_8, N_10, N_9_0, N_7, N_4_1, N_5, N_6_0, - N_9_1, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - data_mem_ren_i_0(0) <= \data_mem_ren_i_0[0]\; - - un3_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0_0 : AO1A - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N_109, Y => - ADD_5x5_fast_I11_Y_i_a2_0); - - sFull : DFN1C0 - port map(D => \sFull_RNO_7\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[0]\, - C => \data_mem_addr_w_0[0]\, Y => Waddr_vect_e0); - - un3_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2_0 : OR2A - port map(A => \data_mem_addr_r_0[3]\, B => - \data_mem_addr_w_0[3]\, Y => N_13); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_5, C => - \data_mem_addr_r_0[4]\, Y => sFull_RNO_8_1); - - \Waddr_vect_RNI11GL[2]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[2]\, Y => N_141); - - \Waddr_vect_RNIC9KQ2[2]\ : NOR3C - port map(A => N_141, B => data_addr_w_iv_i_2(2), C => N_142, - Y => data_addr_w_iv_i_4(2)); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_0[0]\, - Y => \un8_waddr_vect_s[0]\); - - \Raddr_vect_RNI73352[1]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[1]\, Y => N_65); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[0]\); - - \Waddr_vect_RNO[3]\ : MX2B - port map(A => \data_mem_addr_w_0[3]\, B => Waddr_vect_n3, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e3); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_r_0[0]\, Y => N_12_0); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : AO1D - port map(A => N80, B => N165_1, C => N_89_i, Y => N_24); - - \Waddr_vect_RNIKG18[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => Waddr_vect_c1, C - => \data_mem_addr_w_0[4]\, Y => un1_waddr_vect_s); - - \Raddr_vect_RNILJRC[4]\ : NOR2B - port map(A => I_9_14, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, Y => I_5_13); - - \ready_gen.un12_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13_0); - - \Raddr_vect_RNI5873[3]\ : XNOR2 - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, Y => N_87); - - \Raddr_vect_RNIV373[3]\ : NOR2 - port map(A => \data_mem_addr_r_0[3]\, B => - \data_mem_addr_r_0[2]\, Y => un2_raddr_vect_slto3_0); - - \sFull_RNIHL443\ : NOR3C - port map(A => data_addr_w_0_iv_i_1(5), B => N_120_i, C => - \data_addr_w_0_iv_i_3[5]\, Y => sFull_RNIHL443); - - \Raddr_vect_RNI87352[2]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[2]\, Y => N_57); - - un18_ready_1_16_ADD_5x5_fast_I10_Y : OR3A - port map(A => N_75, B => ADD_5x5_fast_I8_un1_Y, C => N80, Y - => N107); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - \ready_gen.un12_ready_0_I_11\ : OA1 - port map(A => N_13_0, B => N_12_2, C => N_11, Y => - un12_ready); - - un18_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXO5 - port map(A => N_87, B => \data_mem_addr_r_0[2]\, C => - \data_mem_addr_w_0[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AO1C - port map(A => N165_1, B => N_89_i, C => N_109, Y => - ADD_7x7_fast_I23_Y_0_o2_0); - - \Waddr_vect_RNI94Q4[2]\ : NOR2A - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_c1, Y - => Waddr_vect_c2); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, C => \data_mem_addr_r_0[2]\, Y - => N_9); - - un18_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO18 - port map(A => N80, B => N_89_i, C => N_109, Y => - ADD_5x5_fast_I11_Y_0); - - \Waddr_vect_RNO[4]\ : MX2B - port map(A => \data_mem_addr_w_0[4]\, B => Waddr_vect_n4, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e4); - - un3_ready_1_1_0_SUM2_0 : AX1C - port map(A => N_87, B => CO1_tz, C => SUM2_0_0, Y => - \un3_ready1[4]\); - - \Waddr_vect_RNI5K63[0]\ : OR2B - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, Y => Waddr_vect_c1); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[1]\); - - \ready_gen.un12_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, C => N_7, Y => N_12_2); - - sFull_RNO_7 : OR2B - port map(A => I_13_13, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_0[3]\, Y => - I_13_13); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \ready_gen.un12_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, Y => N_5); - - \Waddr_vect_RNI0TFL[1]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[1]\, Y => N_149); - - sFull_RNITGSJ : NOR2 - port map(A => \data_mem_wen_i_0[0]\, B => N_164, Y => N_165); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, C => \data_mem_addr_w_0[2]\, Y - => N_9_1); - - un18_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75, Y => \un18_ready1[5]\); - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - \Raddr_vect_RNIMV2G[4]\ : NOR2B - port map(A => I_20_6, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[2]\); - - \Raddr_vect_RNI48175[4]\ : NOR3C - port map(A => data_addr_r_iv_i_1(4), B => - data_addr_r_iv_i_0(4), C => N_41, Y => - data_addr_r_iv_i_3(4)); - - sFull_RNIKUNJ : NOR2A - port map(A => data_mem_wen_i_0_1, B => - \data_mem_wen_i_0[0]\, Y => - data_addr_w_1_iv_i_a2_1_1_0(6)); - - \Raddr_vect_RNI6V252[0]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[0]\, Y => N_73); - - sFull_RNI9VR9 : NOR2 - port map(A => \sFull\, B => data_wen(0), Y => - \data_mem_wen_i_0[0]\); - - un18_ready_1_16_ADD_5x5_fast_I1_G0N : OA1A - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N_87, Y => N80); - - \ready_gen.un12_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, C => N_4_1, Y => N_10); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_0[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i : VCC - port map(Y => \VCC\); - - un3_ready_0_0_0_ADD_5x5_fast_I11_Y_i : OR2B - port map(A => N_13, B => N_12_1, Y => N_6); - - un18_ready_1_16_ADD_5x5_fast_I2_P0N : OR2A - port map(A => N_89_i, B => N_109, Y => N98); - - sEmpty_RNO : AO1A - port map(A => data_ren(0), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_9); - - \Raddr_vect_RNIONK9[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_0[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Raddr_vect_RNI6QHR1[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_0[0]\, - Y => N_198); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[3]\); - - un3_ready_1_1_0_CO1_tz : AO18 - port map(A => N_84_1, B => \data_mem_addr_w_0[2]\, C => - \data_mem_addr_r_0[2]\, Y => CO1_tz); - - un3_ready_0_0_0_ADD_5x5_fast_I9_Y_i_o2_0 : AO1D - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, C => \data_mem_addr_r_0[1]\, Y - => ADD_5x5_fast_I9_Y_i_o2_0); - - un18_ready_1_16_ADD_5x5_fast_I8_un1_Y : NOR2B - port map(A => N81, B => N77, Y => ADD_5x5_fast_I8_un1_Y); - - un18_ready_1_16_ADD_5x5_fast_I15_Y_0 : AX1D - port map(A => ADD_5x5_fast_I8_un1_Y, B => N80, C => - \un18_ready0_1[4]\, Y => \un18_ready1[4]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, Y => N_12); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_0[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(0), Y => - un7_sempty_s_0); - - \sEmpty_RNILSD08\ : AO1C - port map(A => \data_mem_ren_i_0[0]\, B => - data_addr_r_1_iv_i_a9_1_1(6), C => - data_addr_r_1_iv_i_s_1(6), Y => sEmpty_RNILSD08); - - \Raddr_vect_RNIRF18[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_0[4]\, Y => - un2_raddr_vect_s); - - \Raddr_vect_RNIPBM76[0]\ : AOI1 - port map(A => N_197, B => N_196, C => N_198, Y => - un20_ready); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_0[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - \Waddr_vect_RNI39GL[4]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[4]\, Y => N_125); - - un3_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3_0 : AOI1B - port map(A => ADD_5x5_fast_I9_Y_i_o2_0, B => Waddr_vect_c1, - C => \data_mem_addr_w_0[2]\, Y => N_18); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[4]\); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(0), - Y => \sFull_RNO_7\); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_0[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(0), Y => - un5_sfull_s_4_0); - - un3_ready_0_0_0_ADD_5x5_fast_I11_Y_i_a2 : OR3 - port map(A => N_17, B => ADD_5x5_fast_I11_Y_i_a2_0, C => - N_18, Y => N_12_1); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_c1, C - => un1_waddr_vect_s, Y => Waddr_vect_n2); - - \Raddr_vect_RNIRJ63[1]\ : OR2B - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_r_0[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect_RNIQ5C73[4]\ : NOR3C - port map(A => N_125, B => data_addr_w_iv_i_2(4), C => N_126, - Y => data_addr_w_iv_i_4(4)); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[0]\); - - \Waddr_vect_RNIQL7S2[3]\ : NOR3C - port map(A => N_133, B => data_addr_w_iv_i_2(3), C => N_134, - Y => data_addr_w_iv_i_4(3)); - - \Raddr_vect_RNI16OM1[0]\ : MX2C - port map(A => \un18_ready1[4]\, B => \un18_ready0[4]\, S - => \data_mem_addr_r_0[0]\, Y => N_196); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_0[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Raddr_vect_RNIIBCL2[0]\ : MX2C - port map(A => \un18_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_0[0]\, Y => N_197); - - \Raddr_vect_RNIL7FE[4]\ : NOR2B - port map(A => I_13_14, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - \Raddr_vect_RNI5873_0[3]\ : NOR2A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, Y => N_109); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_0[2]\, Y => - I_9_14); - - un18_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75, Y => N_16_i_i_0); - - un18_ready_1_16_ADD_5x5_fast_I1_P0N : OR3A - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N_87, Y => N81); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_0[3]\, B => - \un8_waddr_vect_s[3]\, C => sFull_RNO_8_1, Y => - un5_sfull_s_4_2); - - sEmpty_RNI9NF32 : NOR2 - port map(A => \sEmpty\, B => data_ren(0), Y => - \data_mem_ren_i_0[0]\); - - \ready_gen.un12_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, C => N_5, Y => N_9_0); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, C => \data_mem_addr_r_0[2]\, Y - => \DWACT_FINC_E_0[0]\); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_0[3]\, Y - => Waddr_vect_14_0); - - GND_i_0 : GND - port map(Y => GND_0); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR2A - port map(A => N_75, B => \un3_ready0[4]\, Y => N161); - - \Raddr_vect_RNI34175[3]\ : NOR3C - port map(A => data_addr_r_iv_i_1(3), B => - data_addr_r_iv_i_0(3), C => N_49, Y => - data_addr_r_iv_i_3(3)); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_0[4]\, Y => I_20_5); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[1]\); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_0[4]\, Y => sEmpty_RNO_6_1); - - sFull_RNIOK841 : OA1A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => N_124, - Y => \data_addr_w_0_iv_i_3[5]\); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_0[3]\, Y => - I_13_14); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_n2, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e2); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - \Raddr_vect_RNIAF352[4]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[4]\, Y => N_41); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_0[1]\, B => - \un10_raddr_vect_s[1]\, C => sEmpty_RNO_5_1, Y => - un7_sempty_s_1); - - \Raddr_vect_RNIP9SH1[0]\ : MX2 - port map(A => \un3_ready1[4]\, B => \un3_ready0[4]\, S => - \data_mem_addr_r_0[0]\, Y => un5_readylto4); - - \Raddr_vect_RNI1O63[1]\ : NOR2A - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, Y => N_84_1); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_0[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_6_1, Y => - un7_sempty_s_2); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_13, C => - \data_mem_addr_r_0[2]\, Y => sFull_RNO_5_3); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, Y => I_5_14); - - un18_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1 : AOI1 - port map(A => ADD_5x5_fast_I9_Y_i_o2_0, B => Waddr_vect_c1, - C => ADD_7x7_fast_I19_Y_i_o4_1_0, Y => N165_1); - - \ready_gen.un12_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_0[4]\, B => - \data_mem_addr_r_0[4]\, Y => N_11); - - \Raddr_vect_RNIH6IM8[0]\ : MX2 - port map(A => un5_readylto4, B => un20_ready, S => - un12_ready, Y => ready_i_0(0)); - - \Waddr_vect_RNI25GL[3]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[3]\, Y => N_133); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_9, CLK => HCLK_c, PRE => HRESETn_c, - Q => \sEmpty\); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \data_mem_addr_w_0[1]\, B => Waddr_vect_n1_i, - S => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e1); - - un18_ready_0_0_0_ADD_7x7_fast_I32_Y_0_1 : XNOR2 - port map(A => N_109, B => N_89_i, Y => \un18_ready0_1[4]\); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_mem_addr_w_0[2]\); - - \Waddr_vect_RNI58KI2[0]\ : NOR3C - port map(A => N_157, B => data_addr_w_iv_i_2(0), C => N_158, - Y => data_addr_w_iv_i_4(0)); - - \Raddr_vect_RNI2C8Q4[0]\ : NOR3C - port map(A => data_addr_r_iv_i_1(0), B => - data_addr_r_iv_i_0(0), C => N_73, Y => - data_addr_r_iv_i_3(0)); - - un18_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : AX1D - port map(A => N165_1, B => N80, C => \un18_ready0_1[4]\, Y - => \un18_ready0[4]\); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, C => \data_mem_addr_w_0[2]\, Y - => \DWACT_FINC_E[0]\); - - un3_ready_0_0_0_ADD_5x5_fast_I18_Y_0 : XNOR2 - port map(A => N_6, B => N_89_i, Y => \un3_ready0[4]\); - - un18_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - \Waddr_vect_RNIVOFL[0]\ : OR3A - port map(A => \data_mem_wen_i_0[0]\, B => N_164, C => - \data_mem_addr_w_0[0]\, Y => N_157); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_0[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_3, Y => - un5_sfull_s_4_1); - - \ready_gen.un12_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_w_0[0]\, Y => N_6_0); - - \Waddr_vect_RNIB0LI2[1]\ : NOR3C - port map(A => N_149, B => data_addr_w_iv_i_2(1), C => N_150, - Y => data_addr_w_iv_i_4(1)); - - un18_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1B - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N_84_1, Y => N77); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[3]\); - - sFull_RNO_4 : OR2B - port map(A => I_5_13, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - \Raddr_vect_RNI7G73_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_0[4]\, B => - \data_mem_addr_w_0[4]\, Y => N_75); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_0[2]\, Y => sEmpty_RNO_5_1); - - \Raddr_vect_RNI9B352[3]\ : OR2A - port map(A => \data_mem_ren_i_0[0]\, B => - \data_mem_addr_r_0[3]\, Y => N_49); - - un3_ready_0_0_0_ADD_5x5_fast_I12_Y_i_a3 : AOI1 - port map(A => ADD_5x5_fast_I9_Y_i_o2_0, B => Waddr_vect_c1, - C => \data_mem_addr_r_0[2]\, Y => N_17); - - \Raddr_vect_RNI7G73[4]\ : XNOR2 - port map(A => \data_mem_addr_w_0[4]\, B => - \data_mem_addr_r_0[4]\, Y => N_89_i); - - \Raddr_vect_RNIM38B[4]\ : NOR2B - port map(A => I_5_14, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_0[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - un3_ready_1_1_0_SUM2_0_0 : XOR2 - port map(A => N_89_i, B => N_109, Y => SUM2_0_0); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => HCLK_c, CLR - => HRESETn_c, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[4]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_0[2]\, Y => - I_9_13); - - \ready_gen.un12_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, C => N_6_0, Y => N_8); - - \ready_gen.un12_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, Y => N_4_1); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(0), Y => un1_sempty_s); - - \Raddr_vect_RNICK9Q4[2]\ : NOR3C - port map(A => data_addr_r_iv_i_1(2), B => - data_addr_r_iv_i_0(2), C => N_57, Y => - data_addr_r_iv_i_3(2)); - - \Waddr_vect_RNI9473[3]\ : NOR2 - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_w_0[2]\, Y => un1_waddr_vect_slto3_0); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_0[4]\, Y => - I_20_6); - - \ready_gen.un12_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_0[4]\, B => - \data_mem_addr_w_0[4]\, Y => N_7); - - \Raddr_vect_RNI709Q4[1]\ : NOR3C - port map(A => data_addr_r_iv_i_1(1), B => - data_addr_r_iv_i_0(1), C => N_65, Y => - data_addr_r_iv_i_3(1)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ4 is - - port( time_mem_ren_i_0_1 : in std_logic; - time_wen : in std_logic_vector(0 to 0); - time_ren : in std_logic_vector(0 to 0); - data_addr_w_0_iv_i_1 : out std_logic_vector(5 to 5); - Waddr_vect_RNILN58 : in std_logic_vector(0 to 0); - Waddr_vect_RNINV58 : in std_logic_vector(2 to 2); - Waddr_vect_RNI64MA : in std_logic_vector(2 to 2); - data_addr_w_iv_i_2_0 : out std_logic; - data_addr_w_iv_i_2_2 : out std_logic; - time_mem_wen_i_0 : out std_logic_vector(0 to 0); - data_addr_r_0_iv_i_1 : in std_logic_vector(5 to 5); - data_addr_r_0_iv_i_2 : out std_logic_vector(5 to 5); - Raddr_vect_RNI8J9L : in std_logic_vector(2 to 2); - data_addr_r_iv_i_0 : out std_logic_vector(4 downto 0); - data_addr_w_iv_i_1_0 : out std_logic; - data_addr_w_iv_i_1_3 : out std_logic; - data_addr_w_iv_i_1_1 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - N_77 : out std_logic; - sFull_RNI9VRD : in std_logic; - N_140 : in std_logic; - sFull_RNIPQBB_0 : in std_logic; - N_122 : in std_logic; - N_124 : in std_logic; - sFull_RNI9VRD_0 : in std_logic; - N_146 : in std_logic; - N_70 : in std_logic; - sEmpty_RNI5EFO_0 : in std_logic; - N_33 : in std_logic; - N_62 : in std_logic; - N_155 : in std_logic; - sFull_RNI9VRD_1 : in std_logic; - N_147 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ4; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ4 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \time_mem_addr_r_0[4]\, \Raddr_vect[2]_net_1\, - \Raddr_vect[3]_net_1\, N_4, \time_mem_addr_w_0[4]\, - \Waddr_vect[2]_net_1\, \Waddr_vect[3]_net_1\, N_4_0, N_7, - \time_mem_addr_r_0[1]\, \time_mem_addr_r_0[0]\, N_7_0, - \time_mem_addr_w_0[1]\, \time_mem_addr_w_0[0]\, - \data_addr_w_iv_i_0[1]\, \data_addr_w_iv_i_0[3]\, - \data_addr_w_iv_i_0[0]\, \time_mem_ren_i_0[0]\, - \time_mem_addr_r_0[3]\, \sEmpty_RNI2EFO\, - \data_addr_w_iv_i_0[4]\, \time_mem_wen_i_0[0]\, - \time_mem_addr_w_0[3]\, \data_addr_w_iv_i_0[2]\, - \sFull_RNIBMR8\, un7_sempty_s_3, \sEmpty_RNO_3\, - \sEmpty_RNO_4\, un7_sempty_s_0, un7_sempty_s_2, - \un10_raddr_vect_s[3]\, \un10_raddr_vect_s[0]\, - un5_sfull_s_2, \un8_waddr_vect_s[3]\, un5_sfull_s_1, - \un8_waddr_vect_s[1]\, \sFull_RNO_5\, un5_sfull_s_0, - \un8_waddr_vect_s[0]\, un2_raddr_vect_slt3, - un1_waddr_vect_slt3, un5_sfull_s, Raddr_vect_n3, - Raddr_vect_7_0, Waddr_vect_n3, Waddr_vect_15_0, - Raddr_vect_n2, un2_raddr_vect_s, Raddr_vect_n2_tz, - Waddr_vect_n2, un1_waddr_vect_s, Waddr_vect_n2_tz, - \sEmpty\, un2_sempty_s, \sFull\, \sEmpty_RNO_0\, - \sFull_RNO_0\, I_13_6, I_5_5, I_13_5, I_5_6, I_9_6, I_9_5, - Raddr_vect_n1_i, Raddr_vect_e2, Raddr_vect_e1, - Raddr_vect_e0, Waddr_vect_n1_i, Waddr_vect_e2, - Waddr_vect_e1, Waddr_vect_e0, N_4_1, N_4_2, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - time_mem_wen_i_0(0) <= \time_mem_wen_i_0[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_addr_w_0[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4_1); - - sFull_RNI8KFI1 : NOR3C - port map(A => sFull_RNI9VRD_0, B => \data_addr_w_iv_i_0[4]\, - C => N_124, Y => data_addr_w_iv_i_2_2); - - \Waddr_vect_RNI4JHO[1]\ : AND2 - port map(A => N_147, B => \data_addr_w_iv_i_0[1]\, Y => - data_addr_w_iv_i_1_1); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_addr_r_0[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - sEmpty_RNI2EFO : OR2 - port map(A => \time_mem_ren_i_0[0]\, B => N_4, Y => - \sEmpty_RNI2EFO\); - - \Waddr_vect_RNITOG9[1]\ : OR3 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_addr_w_0[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_0\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_0[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_wen_i_0[0]\, Q => - \Waddr_vect[3]_net_1\); - - sFull_RNIBMR8 : OR2 - port map(A => \time_mem_wen_i_0[0]\, B => N_4_0, Y => - \sFull_RNIBMR8\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_6); - - \Raddr_vect_RNICUIA1[1]\ : OA1 - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_ren_i_0[0]\, C => N_62, Y => - data_addr_r_iv_i_0(1)); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_0\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[0]\, - C => \time_mem_addr_w_0[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Waddr_vect[2]_net_1\); - - sFull_RNIA4G2 : OR2 - port map(A => time_wen(0), B => \sFull\, Y => - \time_mem_wen_i_0[0]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_0[1]\, - S => \time_mem_wen_i_0[0]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, Y => I_5_5); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - sEmpty_RNINO741 : NOR2B - port map(A => time_mem_ren_i_0_1, B => - \time_mem_ren_i_0[0]\, Y => N_77); - - \Waddr_vect_RNIVIRD[1]\ : OA1 - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_wen_i_0[0]\, C => N_146, Y => - \data_addr_w_iv_i_0[1]\); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_ren_i_0[0]\, Q => - \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(0), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4_1, B => \Waddr_vect[3]_net_1\, Y => - I_13_5); - - sFull_RNO : AO1 - port map(A => time_ren(0), B => \sFull\, C => un5_sfull_s, - Y => \sFull_RNO_0\); - - sEmpty_RNIBS3I : OR2 - port map(A => time_ren(0), B => \sEmpty\, Y => - \time_mem_ren_i_0[0]\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[0]\, - C => \time_mem_addr_r_0[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_0[1]\, - S => \time_mem_ren_i_0[0]\, Y => Raddr_vect_e1); - - \Raddr_vect_RNIAMIA1[0]\ : OA1 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_ren_i_0[0]\, C => N_70, Y => - data_addr_r_iv_i_0(0)); - - sFull_RNO_4 : OR2B - port map(A => I_5_5, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_0[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_6, C => - \Waddr_vect[2]_net_1\, Y => \sEmpty_RNO_3\); - - sEmpty_RNI7SUG1_0 : OA1 - port map(A => \time_mem_addr_r_0[3]\, B => - \time_mem_ren_i_0[0]\, C => sEmpty_RNI5EFO_0, Y => - data_addr_r_iv_i_0(3)); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Raddr_vect[2]_net_1\); - - \Raddr_vect_RNIE6JA1[2]\ : OA1A - port map(A => \Raddr_vect[2]_net_1\, B => - \time_mem_ren_i_0[0]\, C => Raddr_vect_RNI8J9L(2), Y => - data_addr_r_iv_i_0(2)); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_0[0]\); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_5, C => - \Raddr_vect[2]_net_1\, Y => \sFull_RNO_5\); - - sFull_RNI4H7K : OA1B - port map(A => \time_mem_addr_w_0[4]\, B => - \time_mem_wen_i_0[0]\, C => N_122, Y => - \data_addr_w_iv_i_0[4]\); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[0]\, Y => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_6, C => - \time_mem_addr_w_0[1]\, Y => \sEmpty_RNO_4\); - - sFull_RNO_3 : XA1 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, C => time_ren(0), Y => - un5_sfull_s_2); - - sEmpty_RNO_0 : NOR3C - port map(A => \sEmpty_RNO_3\, B => \sEmpty_RNO_4\, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un25_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_0[4]\); - - sFull_RNIDG321 : NOR3B - port map(A => \sFull_RNIBMR8\, B => sFull_RNI9VRD, C => - N_122, Y => data_addr_w_0_iv_i_1(5)); - - \Waddr_vect_RNI1RRD[2]\ : OA1A - port map(A => \Waddr_vect[2]_net_1\, B => - \time_mem_wen_i_0[0]\, C => Waddr_vect_RNINV58(2), Y => - \data_addr_w_iv_i_0[2]\); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - un25_mem_addr_ren_I_12 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => N_4); - - sEmpty_RNO_7 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_0[0]\, - Y => \un10_raddr_vect_s[0]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[0]\, Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_0[0]\); - - sEmpty_RNI7SUG1 : OA1B - port map(A => \time_mem_addr_r_0[4]\, B => - \time_mem_ren_i_0[0]\, C => N_33, Y => - data_addr_r_iv_i_0(4)); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_addr_r_0[0]\, Y => N_7); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => I_9_5); - - \Waddr_vect_RNIU7O51[2]\ : NOR3C - port map(A => Waddr_vect_RNI64MA(2), B => - \data_addr_w_iv_i_0[2]\, C => N_140, Y => - data_addr_w_iv_i_2_0); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_2, B => \Raddr_vect[3]_net_1\, Y => - I_13_6); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_2); - - sFull_RNIDG321_0 : AND2 - port map(A => sFull_RNI9VRD_1, B => \data_addr_w_iv_i_0[3]\, - Y => data_addr_w_iv_i_1_3); - - sEmpty_RNO_1 : XA1B - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, C => time_ren(0), Y => - un7_sempty_s_2); - - sFull_RNO_1 : XA1 - port map(A => \un8_waddr_vect_s[1]\, B => - \time_mem_addr_r_0[1]\, C => \sFull_RNO_5\, Y => - un5_sfull_s_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, Y => I_5_6); - - \Raddr_vect_RNIEOG9[1]\ : OR3 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - sFull_RNO_7 : OR2B - port map(A => I_13_5, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Waddr_vect_RNIUJMC[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - sEmpty_RNIQOT13 : NOR3B - port map(A => \sEmpty_RNI2EFO\, B => - data_addr_r_0_iv_i_1(5), C => N_33, Y => - data_addr_r_0_iv_i_2(5)); - - un29_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_0[4]\); - - un25_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_0[3]\); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_1, B => un5_sfull_s_0, C => - un5_sfull_s_2, Y => un5_sfull_s); - - sEmpty_RNO_6 : OR2B - port map(A => I_13_6, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un29_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_0[3]\); - - sFull : DFN1C0 - port map(D => \sFull_RNO_0\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \Waddr_vect_RNITARD[0]\ : OA1 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_wen_i_0[0]\, C => Waddr_vect_RNILN58(0), Y => - \data_addr_w_iv_i_0[0]\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_0[1]\); - - un29_mem_addr_wen_I_12 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => N_4_0); - - sFull_RNO_2 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_0[0]\, C => time_wen(0), Y => - un5_sfull_s_0); - - sFull_RNI4H7K_0 : OA1 - port map(A => \time_mem_addr_w_0[3]\, B => - \time_mem_wen_i_0[0]\, C => sFull_RNIPQBB_0, Y => - \data_addr_w_iv_i_0[3]\); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_0[0]\, C => time_wen(0), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - \Raddr_vect_RNIAJMC[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - \Waddr_vect_RNI17HO[0]\ : AND2 - port map(A => N_155, B => \data_addr_w_iv_i_0[0]\, Y => - data_addr_w_iv_i_1_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ6 is - - port( Waddr_vect_RNI64MA : out std_logic_vector(2 to 2); - data_addr_w_1_iv_i_s_0_0 : in std_logic_vector(6 to 6); - time_wen : in std_logic_vector(2 to 2); - data_addr_r_0_iv_i_1 : out std_logic_vector(5 to 5); - data_addr_r_1_iv_i_s_1 : out std_logic_vector(6 to 6); - time_mem_ren_i_0_1 : in std_logic; - data_addr_r_iv_i_a2_0 : out std_logic_vector(4 to 4); - data_addr_r_iv_i_1 : out std_logic_vector(4 downto 0); - time_ren : in std_logic_vector(2 to 2); - time_ren_1z : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sFull_RNI9VRD_0 : out std_logic; - N_147 : out std_logic; - sFull_RNI9VRD_1 : out std_logic; - sFull_RNI9VRD : out std_logic; - un13_time_write : in std_logic; - N_163 : out std_logic; - N_155 : out std_logic; - N_162 : in std_logic; - sFull_RNIU5GK1 : out std_logic; - N_29 : in std_logic; - N_30_1 : in std_logic; - N_72 : in std_logic; - N_56 : in std_logic; - N_48 : in std_logic; - N_35 : in std_logic; - N_64 : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ6; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ6 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \time_mem_addr_r_2[4]\, \Raddr_vect[2]_net_1\, - \Raddr_vect[3]_net_1\, N_4, \time_mem_addr_w_2[4]\, - \Waddr_vect[2]_net_1\, \Waddr_vect[3]_net_1\, N_4_0, N_7, - \time_mem_addr_r_2[1]\, \time_mem_addr_r_2[0]\, N_7_0, - \time_mem_addr_w_2[1]\, \time_mem_addr_w_2[0]\, - \un2_sfull_s_3_0\, \un8_waddr_vect_s[3]\, - \un10_sempty_s_3_0\, \un10_raddr_vect_s[3]\, - un5_sfull_s_2, un7_sempty_s_2, \time_mem_ren_i_0[2]\, - \time_mem_addr_r_2[3]\, un5_sfull_s_3, \sFull_RNO_3\, - \sFull_RNO_4\, un5_sfull_s_0, \un8_waddr_vect_s[0]\, - un7_sempty_s_3, sEmpty_RNO_3_0, sEmpty_RNO_4_0, - un7_sempty_s_0, \un10_raddr_vect_s[0]\, - un2_raddr_vect_slt3, \time_mem_wen_i_0[2]\, - un1_waddr_vect_slt3, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, Raddr_vect_c1, - Raddr_vect_n2, un2_raddr_vect_s, Waddr_vect_n2, - un1_waddr_vect_s, Waddr_vect_n2_tz, I_13_7, I_9_7, I_5_7, - I_9_8, I_5_8, Raddr_vect_n1_i, N_50, Raddr_vect_e2, - Raddr_vect_e1, Raddr_vect_e0, I_13_8, \sFull_RNO_1\, - un8_sfull_s, \sEmpty_RNO_1\, un2_sempty_s, \sFull\, - \sEmpty\, Waddr_vect_n1_i, Waddr_vect_e2, Waddr_vect_e1, - Waddr_vect_e0, \time_mem_addr_w_2[3]\, N_4_1, N_4_2, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_2[1]\, B => - \time_mem_addr_w_2[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4_1); - - un37_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_2[4]\); - - sEmpty_RNITO232 : NOR3C - port map(A => N_30_1, B => \time_mem_ren_i_0[2]\, C => N_29, - Y => data_addr_r_1_iv_i_s_1(6)); - - \Raddr_vect_RNO_0[1]\ : AX1C - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_2[1]\, - C => N_50, Y => Raddr_vect_n1_i); - - \Waddr_vect_RNI4SLA[0]\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - \time_mem_addr_w_2[0]\, Y => N_155); - - \sFull_RNI9VRD_1\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - \time_mem_addr_w_2[3]\, Y => sFull_RNI9VRD_1); - - \sFull_RNI9VRD_0\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - \time_mem_addr_w_2[4]\, Y => sFull_RNI9VRD_0); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_2[1]\, B => - \time_mem_addr_w_2[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_1\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_2[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_wen_i_0[2]\, Q => - \Waddr_vect[3]_net_1\); - - \Raddr_vect_RNIKOG9[1]\ : OR3 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_8); - - un2_sfull_s_3_0_RNO : OR2B - port map(A => I_13_7, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_1\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[2]\, - C => \time_mem_addr_w_2[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Waddr_vect[2]_net_1\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_2[1]\, - S => \time_mem_wen_i_0[2]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, Y => I_5_7); - - \sFull_RNI9VRD\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => N_4_0, - Y => sFull_RNI9VRD); - - \Raddr_vect_RNO_0[2]\ : XAI1 - port map(A => \Raddr_vect[2]_net_1\, B => Raddr_vect_c1, C - => un2_raddr_vect_s, Y => Raddr_vect_n2); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => HCLK_c, CLR => - HRESETn_c, E => \time_mem_ren_i_0[2]\, Q => - \Raddr_vect[3]_net_1\); - - \Waddr_vect_RNI64MA[2]\ : OR3A - port map(A => \Waddr_vect[2]_net_1\, B => N_162, C => - \time_mem_wen_i_0[2]\, Y => Waddr_vect_RNI64MA(2)); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(2), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4_1, B => \Waddr_vect[3]_net_1\, Y => - I_13_7); - - un2_sfull_s_3_0 : XOR2 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, Y => \un2_sfull_s_3_0\); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO_1\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[2]\, - C => \time_mem_addr_r_2[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_2[1]\, - S => \time_mem_ren_i_0[2]\, Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_7, C => - \time_mem_addr_r_2[1]\, Y => \sFull_RNO_4\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_2[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_8, C => - \Waddr_vect[2]_net_1\, Y => sEmpty_RNO_3_0); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => HCLK_c, CLR => - HRESETn_c, Q => \Raddr_vect[2]_net_1\); - - sEmpty_RNIJSUG1_0 : OA1 - port map(A => N_4, B => \time_mem_ren_i_0[2]\, C => N_35, Y - => data_addr_r_0_iv_i_1(5)); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_2[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_2[0]\, C => time_wen(2), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[2]\, Y => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_8, C => - \time_mem_addr_w_2[1]\, Y => sEmpty_RNO_4_0); - - \Raddr_vect_RNIN1B6[1]\ : NOR2B - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_addr_r_2[0]\, Y => Raddr_vect_c1); - - \Waddr_vect_RNI3PG9[1]\ : OR3 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - un10_sempty_s_3_0 : XOR2 - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, Y => \un10_sempty_s_3_0\); - - \Raddr_vect_RNIIMIA1[0]\ : OA1 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_ren_i_0[2]\, C => N_72, Y => - data_addr_r_iv_i_1(0)); - - un43_mem_addr_wen_I_12 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => N_4_0); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_7, C => - \Raddr_vect[2]_net_1\, Y => \sFull_RNO_3\); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_0, B => sEmpty_RNO_4_0, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un43_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_2[4]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[2]\, Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_r_2[0]\); - - \Waddr_vect_RNI50MA[1]\ : OR3 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - \time_mem_addr_w_2[1]\, Y => N_147); - - sEmpty_RNIRO741 : NOR2B - port map(A => time_mem_ren_i_0_1, B => - \time_mem_ren_i_0[2]\, Y => data_addr_r_iv_i_a2_0(4)); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_addr_r_2[0]\, Y => N_7); - - un10_sempty_s_3_0_RNO : OR2B - port map(A => I_13_8, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => I_9_7); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_2, B => \Raddr_vect[3]_net_1\, Y => - I_13_8); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_2); - - \Raddr_vect_RNIKUIA1[1]\ : OA1 - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_ren_i_0[2]\, C => N_64, Y => - data_addr_r_iv_i_1(1)); - - sEmpty_RNO_1 : NOR2A - port map(A => \un10_sempty_s_3_0\, B => time_ren(2), Y => - un7_sempty_s_2); - - \Raddr_vect_RNIM6JA1[2]\ : OA1A - port map(A => \Raddr_vect[2]_net_1\, B => - \time_mem_ren_i_0[2]\, C => N_56, Y => - data_addr_r_iv_i_1(2)); - - sEmpty_RNIDS3I : OR3A - port map(A => time_ren_1z, B => un13_time_write, C => - \sEmpty\, Y => \time_mem_ren_i_0[2]\); - - sFull_RNO_1 : AND2 - port map(A => time_ren(2), B => \un2_sfull_s_3_0\, Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, Y => I_5_8); - - un43_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_2[3]\); - - \Waddr_vect_RNI6KMC[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - un37_mem_addr_ren_I_12 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => N_4); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - \Raddr_vect_RNO_0[3]\ : OR2B - port map(A => Raddr_vect_c1, B => \Raddr_vect[2]_net_1\, Y - => Raddr_vect_7_0); - - \Raddr_vect_RNIIJMC[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNI4DG7 : NOR2A - port map(A => \time_mem_wen_i_0[2]\, B => N_162, Y => N_163); - - sFull_RNO_0 : NOR3C - port map(A => \sFull_RNO_3\, B => \sFull_RNO_4\, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_2[0]\, - Y => \un10_raddr_vect_s[0]\); - - un37_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_2[3]\); - - sEmpty_RNIJSUG1_1 : OA1 - port map(A => \time_mem_addr_r_2[4]\, B => - \time_mem_ren_i_0[2]\, C => N_35, Y => - data_addr_r_iv_i_1(4)); - - \Raddr_vect_RNO_1[1]\ : OR2B - port map(A => \time_mem_addr_r_2[0]\, B => un2_raddr_vect_s, - Y => N_50); - - sFull : DFN1C0 - port map(D => \sFull_RNO_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \sFull\); - - \sFull_RNIU5GK1\ : OAI1 - port map(A => N_162, B => \time_mem_wen_i_0[2]\, C => - data_addr_w_1_iv_i_s_0_0(6), Y => sFull_RNIU5GK1); - - sFull_RNIE4G2 : OR2 - port map(A => time_wen(2), B => \sFull\, Y => - \time_mem_wen_i_0[2]\); - - sEmpty_RNIJSUG1 : OA1 - port map(A => \time_mem_addr_r_2[3]\, B => - \time_mem_ren_i_0[2]\, C => N_48, Y => - data_addr_r_iv_i_1(3)); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => HCLK_c, CLR => - HRESETn_c, Q => \time_mem_addr_w_2[1]\); - - sFull_RNO_2 : OA1A - port map(A => time_ren_1z, B => un13_time_write, C => - \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_2[0]\, C => time_wen(2), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo is - - port( data_wen : in std_logic_vector(3 downto 0); - data_ren : in std_logic_vector(3 downto 0); - ready_i_0 : out std_logic_vector(3 downto 0); - time_ren : in std_logic_vector(3 downto 0); - time_wen : in std_logic_vector(3 downto 0); - wdata : in std_logic_vector(31 downto 0); - hwdata_c : out std_logic_vector(31 downto 0); - time_ren_1z : in std_logic; - data_ren_1z : in std_logic; - un20_time_write : in std_logic; - un13_time_write : in std_logic; - HRESETn_c : in std_logic; - lpp_waveform_fifo_VCC : in std_logic; - lpp_waveform_fifo_GND : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_waveform_fifo; - -architecture DEF_ARCH of lpp_waveform_fifo is - - component lpp_waveform_fifo_ctrlZ1 - port( ready_i_0 : out std_logic_vector(1 to 1); - Raddr_vect_RNICA1PH : out std_logic_vector(1 to 1); - data_mem_wen_i_0 : inout std_logic_vector(2 downto 1); - Raddr_vect_RNIIMQ5I : out std_logic_vector(4 to 4); - Raddr_vect_RNIE6Q5I : out std_logic_vector(3 to 3); - Raddr_vect_RNIKA2PH : out std_logic_vector(2 to 2); - data_addr_r_iv_i_3 : in std_logic_vector(4 downto 0) := (others => 'U'); - Raddr_vect_RNI4A0PH : out std_logic_vector(0 to 0); - data_addr_r_iv_i_a2_2 : in std_logic_vector(4 to 4) := (others => 'U'); - data_wen : in std_logic_vector(1 to 1) := (others => 'U'); - data_mem_ren_i_0 : inout std_logic_vector(1 downto 0); - data_ren : in std_logic_vector(1 to 1) := (others => 'U'); - data_ren_1z : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_166 : out std_logic; - N_126 : out std_logic; - N_150 : out std_logic; - N_134 : out std_logic; - N_142 : out std_logic; - N_165 : in std_logic := 'U'; - N_158 : out std_logic; - un20_time_write : in std_logic := 'U'; - N_68 : in std_logic := 'U'; - N_164 : in std_logic := 'U'; - N_120_i : out std_logic; - N_44 : in std_logic := 'U'; - N_52 : in std_logic := 'U'; - N_60 : in std_logic := 'U'; - N_76 : in std_logic := 'U'; - N_86 : out std_logic; - N_75 : in std_logic := 'U'; - N_59 : in std_logic := 'U'; - N_51 : in std_logic := 'U'; - N_43 : in std_logic := 'U'; - N_67 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ7 - port( time_mem_addr_w_3_i_0_1 : out std_logic; - data_addr_w_1_iv_i_a2_1_1_0 : in std_logic_vector(6 to 6) := (others => 'U'); - data_addr_w_1_iv_i_s_0_0 : out std_logic_vector(6 to 6); - time_wen : in std_logic_vector(3 to 3) := (others => 'U'); - time_ren : in std_logic_vector(3 to 3) := (others => 'U'); - data_mem_ren_i_0 : in std_logic_vector(1 to 1) := (others => 'U'); - time_mem_ren_i_0 : out std_logic_vector(3 to 3); - data_addr_r_1_iv_i_a9_1_1 : out std_logic_vector(6 to 6); - time_mem_addr_w_3 : out std_logic_vector(1 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_124 : out std_logic; - N_64 : out std_logic; - N_140 : out std_logic; - N_30_1 : out std_logic; - N_89 : out std_logic; - N_163 : in std_logic := 'U'; - N_164 : out std_logic; - N_72 : out std_logic; - N_56 : out std_logic; - N_48 : out std_logic; - N_35 : out std_logic; - N_113 : in std_logic := 'U'; - N_162 : in std_logic := 'U'; - N_77 : in std_logic := 'U' - ); - end component; - - component syncram_2pZ1 - port( hwdata_c : out std_logic_vector(31 downto 0); - Raddr_vect_RNI4A0PH : in std_logic_vector(0 to 0) := (others => 'U'); - Raddr_vect_RNICA1PH : in std_logic_vector(1 to 1) := (others => 'U'); - Raddr_vect_RNIKA2PH : in std_logic_vector(2 to 2) := (others => 'U'); - Raddr_vect_RNIE6Q5I : in std_logic_vector(3 to 3) := (others => 'U'); - Raddr_vect_RNIIMQ5I : in std_logic_vector(4 to 4) := (others => 'U'); - Waddr_vect_RNION355 : in std_logic_vector(0 to 0) := (others => 'U'); - Waddr_vect_RNI0O455 : in std_logic_vector(1 to 1) := (others => 'U'); - Waddr_vect_RNI394D5 : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_RNIJTNE5 : in std_logic_vector(3 to 3) := (others => 'U'); - Waddr_vect_RNILLSP5 : in std_logic_vector(4 to 4) := (others => 'U'); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - HCLK_c : in std_logic := 'U'; - N_1_i_1 : in std_logic := 'U'; - sEmpty_RNIE7T87 : in std_logic := 'U'; - sEmpty_RNILSD08 : in std_logic := 'U'; - sFull_RNIHL443 : in std_logic := 'U'; - sFull_RNIU5GK1 : in std_logic := 'U'; - syncram_2pZ1_GND : in std_logic := 'U'; - syncram_2pZ1_VCC : in std_logic := 'U'; - N_1_i_1_i : in std_logic := 'U' - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ2 - port( ready_i_0 : out std_logic_vector(2 to 2); - data_mem_wen_i_0 : out std_logic_vector(2 to 2); - data_ren : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_RNI0O455 : out std_logic_vector(1 to 1); - Waddr_vect_RNILLSP5 : out std_logic_vector(4 to 4); - Waddr_vect_RNIJTNE5 : out std_logic_vector(3 to 3); - Waddr_vect_RNI394D5 : out std_logic_vector(2 to 2); - data_mem_ren_i_0_0 : in std_logic := 'U'; - data_addr_r_0_iv_i_2 : in std_logic_vector(5 to 5) := (others => 'U'); - data_addr_w_iv_i_4 : in std_logic_vector(4 downto 0) := (others => 'U'); - Waddr_vect_RNION355 : out std_logic_vector(0 to 0); - data_wen : in std_logic_vector(2 to 2) := (others => 'U'); - data_addr_r_iv_i_a2_0 : in std_logic_vector(4 to 4) := (others => 'U'); - data_addr_r_iv_i_a2_2 : out std_logic_vector(4 to 4); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_67 : out std_logic; - N_166 : in std_logic := 'U'; - N_75 : out std_logic; - N_59 : out std_logic; - N_51 : out std_logic; - N_43 : out std_logic; - N_152 : in std_logic := 'U'; - N_128 : in std_logic := 'U'; - N_136 : in std_logic := 'U'; - N_144 : in std_logic := 'U'; - sEmpty_RNIE7T87 : out std_logic; - N_160 : in std_logic := 'U'; - N_77 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_ctrlZ5 - port( time_mem_wen_i_0_0 : in std_logic := 'U'; - Waddr_vect_RNINV58 : out std_logic_vector(2 to 2); - Waddr_vect_RNILN58 : out std_logic_vector(0 to 0); - Raddr_vect_RNI8J9L : out std_logic_vector(2 to 2); - time_mem_ren_i_0 : out std_logic_vector(1 to 1); - time_wen : in std_logic_vector(1 to 1) := (others => 'U'); - time_ren : in std_logic_vector(1 to 1) := (others => 'U'); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_146 : out std_logic; - N_162 : out std_logic; - N_113 : out std_logic; - N_122 : out std_logic; - sFull_RNIPQBB_0 : out std_logic; - N_62 : out std_logic; - N_70 : out std_logic; - sEmpty_RNI5EFO_0 : out std_logic; - N_33 : out std_logic; - N_29 : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ3 - port( ready_i_0 : out std_logic_vector(3 to 3); - data_mem_wen_i_0_0 : in std_logic := 'U'; - data_ren : in std_logic_vector(3 to 3) := (others => 'U'); - data_wen : in std_logic_vector(3 to 3) := (others => 'U'); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_128 : out std_logic; - N_152 : out std_logic; - N_136 : out std_logic; - N_68 : out std_logic; - N_144 : out std_logic; - N_166 : in std_logic := 'U'; - N_160 : out std_logic; - N_76 : out std_logic; - N_60 : out std_logic; - N_52 : out std_logic; - N_86 : in std_logic := 'U'; - N_44 : out std_logic; - N_1_i_1 : out std_logic; - N_1_i_1_i : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ0 - port( ready_i_0 : out std_logic_vector(0 to 0); - data_ren : in std_logic_vector(0 to 0) := (others => 'U'); - data_addr_w_0_iv_i_1 : in std_logic_vector(5 to 5) := (others => 'U'); - data_addr_r_1_iv_i_s_1 : in std_logic_vector(6 to 6) := (others => 'U'); - data_addr_r_1_iv_i_a9_1_1 : in std_logic_vector(6 to 6) := (others => 'U'); - data_mem_ren_i_0 : out std_logic_vector(0 to 0); - data_mem_wen_i_0_1 : in std_logic := 'U'; - data_addr_w_1_iv_i_a2_1_1_0 : out std_logic_vector(6 to 6); - data_addr_w_iv_i_2 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_addr_w_iv_i_4 : out std_logic_vector(4 downto 0); - data_wen : in std_logic_vector(0 to 0) := (others => 'U'); - data_addr_r_iv_i_0 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_addr_r_iv_i_1 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_addr_r_iv_i_3 : out std_logic_vector(4 downto 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_165 : out std_logic; - N_120_i : in std_logic := 'U'; - sFull_RNIHL443 : out std_logic; - sEmpty_RNILSD08 : out std_logic; - N_124 : in std_logic := 'U'; - N_164 : in std_logic := 'U'; - N_158 : in std_logic := 'U'; - N_142 : in std_logic := 'U'; - N_134 : in std_logic := 'U'; - N_126 : in std_logic := 'U'; - N_150 : in std_logic := 'U' - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ4 - port( time_mem_ren_i_0_1 : in std_logic := 'U'; - time_wen : in std_logic_vector(0 to 0) := (others => 'U'); - time_ren : in std_logic_vector(0 to 0) := (others => 'U'); - data_addr_w_0_iv_i_1 : out std_logic_vector(5 to 5); - Waddr_vect_RNILN58 : in std_logic_vector(0 to 0) := (others => 'U'); - Waddr_vect_RNINV58 : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_RNI64MA : in std_logic_vector(2 to 2) := (others => 'U'); - data_addr_w_iv_i_2_0 : out std_logic; - data_addr_w_iv_i_2_2 : out std_logic; - time_mem_wen_i_0 : out std_logic_vector(0 to 0); - data_addr_r_0_iv_i_1 : in std_logic_vector(5 to 5) := (others => 'U'); - data_addr_r_0_iv_i_2 : out std_logic_vector(5 to 5); - Raddr_vect_RNI8J9L : in std_logic_vector(2 to 2) := (others => 'U'); - data_addr_r_iv_i_0 : out std_logic_vector(4 downto 0); - data_addr_w_iv_i_1_0 : out std_logic; - data_addr_w_iv_i_1_3 : out std_logic; - data_addr_w_iv_i_1_1 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - N_77 : out std_logic; - sFull_RNI9VRD : in std_logic := 'U'; - N_140 : in std_logic := 'U'; - sFull_RNIPQBB_0 : in std_logic := 'U'; - N_122 : in std_logic := 'U'; - N_124 : in std_logic := 'U'; - sFull_RNI9VRD_0 : in std_logic := 'U'; - N_146 : in std_logic := 'U'; - N_70 : in std_logic := 'U'; - sEmpty_RNI5EFO_0 : in std_logic := 'U'; - N_33 : in std_logic := 'U'; - N_62 : in std_logic := 'U'; - N_155 : in std_logic := 'U'; - sFull_RNI9VRD_1 : in std_logic := 'U'; - N_147 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_ctrlZ6 - port( Waddr_vect_RNI64MA : out std_logic_vector(2 to 2); - data_addr_w_1_iv_i_s_0_0 : in std_logic_vector(6 to 6) := (others => 'U'); - time_wen : in std_logic_vector(2 to 2) := (others => 'U'); - data_addr_r_0_iv_i_1 : out std_logic_vector(5 to 5); - data_addr_r_1_iv_i_s_1 : out std_logic_vector(6 to 6); - time_mem_ren_i_0_1 : in std_logic := 'U'; - data_addr_r_iv_i_a2_0 : out std_logic_vector(4 to 4); - data_addr_r_iv_i_1 : out std_logic_vector(4 downto 0); - time_ren : in std_logic_vector(2 to 2) := (others => 'U'); - time_ren_1z : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sFull_RNI9VRD_0 : out std_logic; - N_147 : out std_logic; - sFull_RNI9VRD_1 : out std_logic; - sFull_RNI9VRD : out std_logic; - un13_time_write : in std_logic := 'U'; - N_163 : out std_logic; - N_155 : out std_logic; - N_162 : in std_logic := 'U'; - sFull_RNIU5GK1 : out std_logic; - N_29 : in std_logic := 'U'; - N_30_1 : in std_logic := 'U'; - N_72 : in std_logic := 'U'; - N_56 : in std_logic := 'U'; - N_48 : in std_logic := 'U'; - N_35 : in std_logic := 'U'; - N_64 : in std_logic := 'U' - ); - end component; - - signal N_156, N_89, \time_mem_addr_w_3[0]\, N_132, - \time_mem_addr_w_3_i_0[3]\, N_148, \time_mem_addr_w_3[1]\, - \data_addr_w_iv_i_2[3]\, \data_addr_w_iv_i_1[3]\, - \data_addr_w_iv_i_2[0]\, \data_addr_w_iv_i_1[0]\, - \data_addr_w_iv_i_2[1]\, \data_addr_w_iv_i_1[1]\, - \Raddr_vect_RNI4A0PH[0]\, \Raddr_vect_RNICA1PH[1]\, - \Raddr_vect_RNIKA2PH[2]\, \Raddr_vect_RNIE6Q5I[3]\, - \Raddr_vect_RNIIMQ5I[4]\, \Waddr_vect_RNION355[0]\, - \Waddr_vect_RNI0O455[1]\, \Waddr_vect_RNI394D5[2]\, - \Waddr_vect_RNIJTNE5[3]\, \Waddr_vect_RNILLSP5[4]\, - N_1_i_1, sEmpty_RNIE7T87, sEmpty_RNILSD08, sFull_RNIHL443, - sFull_RNIU5GK1, N_1_i_1_i, - \data_addr_w_1_iv_i_a2_1_1_0[6]\, - \data_addr_w_1_iv_i_s_0_0[6]\, \data_mem_ren_i_0[1]\, - \time_mem_ren_i_0[3]\, \data_addr_r_1_iv_i_a9_1_1[6]\, - N_124, N_64, N_140, N_30_1, N_163, N_164, N_72, N_56, - N_48, N_35, N_113, N_162, N_77, \time_mem_ren_i_0[1]\, - \data_addr_w_0_iv_i_1[5]\, \Waddr_vect_RNILN58[0]\, - \Waddr_vect_RNINV58[2]\, \Waddr_vect_RNI64MA[2]\, - \data_addr_w_iv_i_2[2]\, \data_addr_w_iv_i_2[4]\, - \time_mem_wen_i_0[0]\, \data_addr_r_0_iv_i_1[5]\, - \data_addr_r_0_iv_i_2[5]\, \Raddr_vect_RNI8J9L[2]\, - \data_addr_r_iv_i_0[0]\, \data_addr_r_iv_i_0[1]\, - \data_addr_r_iv_i_0[2]\, \data_addr_r_iv_i_0[3]\, - \data_addr_r_iv_i_0[4]\, sFull_RNI9VRD, sFull_RNIPQBB_0, - N_122, sFull_RNI9VRD_0, N_146, N_70, sEmpty_RNI5EFO_0, - N_33, N_62, N_155, sFull_RNI9VRD_1, N_147, - \data_addr_r_1_iv_i_s_1[6]\, \data_addr_r_iv_i_a2_0[4]\, - \data_addr_r_iv_i_1[0]\, \data_addr_r_iv_i_1[1]\, - \data_addr_r_iv_i_1[2]\, \data_addr_r_iv_i_1[3]\, - \data_addr_r_iv_i_1[4]\, N_29, \data_mem_wen_i_0[2]\, - N_128, N_152, N_136, N_68, N_144, N_166, N_160, N_76, - N_60, N_52, N_86, N_44, \data_mem_ren_i_0[0]\, - \data_mem_wen_i_0[1]\, \data_addr_w_iv_i_4[0]\, - \data_addr_w_iv_i_4[1]\, \data_addr_w_iv_i_4[2]\, - \data_addr_w_iv_i_4[3]\, \data_addr_w_iv_i_4[4]\, - \data_addr_r_iv_i_3[0]\, \data_addr_r_iv_i_3[1]\, - \data_addr_r_iv_i_3[2]\, \data_addr_r_iv_i_3[3]\, - \data_addr_r_iv_i_3[4]\, N_165, N_120_i, N_158, N_142, - N_134, N_126, N_150, \data_addr_r_iv_i_a2_2[4]\, N_67, - N_75, N_59, N_51, N_43, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : lpp_waveform_fifo_ctrlZ1 - Use entity work.lpp_waveform_fifo_ctrlZ1(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ7 - Use entity work.lpp_waveform_fifo_ctrlZ7(DEF_ARCH); - for all : syncram_2pZ1 - Use entity work.syncram_2pZ1(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ2 - Use entity work.lpp_waveform_fifo_ctrlZ2(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ5 - Use entity work.lpp_waveform_fifo_ctrlZ5(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ3 - Use entity work.lpp_waveform_fifo_ctrlZ3(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ0 - Use entity work.lpp_waveform_fifo_ctrlZ0(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ4 - Use entity work.lpp_waveform_fifo_ctrlZ4(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ6 - Use entity work.lpp_waveform_fifo_ctrlZ6(DEF_ARCH); -begin - - - \gen_fifo_ctrl_data.1.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ1 - port map(ready_i_0(1) => ready_i_0(1), - Raddr_vect_RNICA1PH(1) => \Raddr_vect_RNICA1PH[1]\, - data_mem_wen_i_0(2) => \data_mem_wen_i_0[2]\, - data_mem_wen_i_0(1) => \data_mem_wen_i_0[1]\, - Raddr_vect_RNIIMQ5I(4) => \Raddr_vect_RNIIMQ5I[4]\, - Raddr_vect_RNIE6Q5I(3) => \Raddr_vect_RNIE6Q5I[3]\, - Raddr_vect_RNIKA2PH(2) => \Raddr_vect_RNIKA2PH[2]\, - data_addr_r_iv_i_3(4) => \data_addr_r_iv_i_3[4]\, - data_addr_r_iv_i_3(3) => \data_addr_r_iv_i_3[3]\, - data_addr_r_iv_i_3(2) => \data_addr_r_iv_i_3[2]\, - data_addr_r_iv_i_3(1) => \data_addr_r_iv_i_3[1]\, - data_addr_r_iv_i_3(0) => \data_addr_r_iv_i_3[0]\, - Raddr_vect_RNI4A0PH(0) => \Raddr_vect_RNI4A0PH[0]\, - data_addr_r_iv_i_a2_2(4) => \data_addr_r_iv_i_a2_2[4]\, - data_wen(1) => data_wen(1), data_mem_ren_i_0(1) => - \data_mem_ren_i_0[1]\, data_mem_ren_i_0(0) => - \data_mem_ren_i_0[0]\, data_ren(1) => data_ren(1), - data_ren_1z => data_ren_1z, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, N_166 => N_166, N_126 => N_126, N_150 - => N_150, N_134 => N_134, N_142 => N_142, N_165 => N_165, - N_158 => N_158, un20_time_write => un20_time_write, N_68 - => N_68, N_164 => N_164, N_120_i => N_120_i, N_44 => - N_44, N_52 => N_52, N_60 => N_60, N_76 => N_76, N_86 => - N_86, N_75 => N_75, N_59 => N_59, N_51 => N_51, N_43 => - N_43, N_67 => N_67); - - GND_i_0 : GND - port map(Y => GND_0); - - \gen_fifo_ctrl_time.3.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ7 - port map(time_mem_addr_w_3_i_0_1 => - \time_mem_addr_w_3_i_0[3]\, - data_addr_w_1_iv_i_a2_1_1_0(6) => - \data_addr_w_1_iv_i_a2_1_1_0[6]\, - data_addr_w_1_iv_i_s_0_0(6) => - \data_addr_w_1_iv_i_s_0_0[6]\, time_wen(3) => time_wen(3), - time_ren(3) => time_ren(3), data_mem_ren_i_0(1) => - \data_mem_ren_i_0[1]\, time_mem_ren_i_0(3) => - \time_mem_ren_i_0[3]\, data_addr_r_1_iv_i_a9_1_1(6) => - \data_addr_r_1_iv_i_a9_1_1[6]\, time_mem_addr_w_3(1) => - \time_mem_addr_w_3[1]\, time_mem_addr_w_3(0) => - \time_mem_addr_w_3[0]\, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c, N_124 => N_124, N_64 => N_64, N_140 => N_140, - N_30_1 => N_30_1, N_89 => N_89, N_163 => N_163, N_164 => - N_164, N_72 => N_72, N_56 => N_56, N_48 => N_48, N_35 => - N_35, N_113 => N_113, N_162 => N_162, N_77 => N_77); - - SRAM : syncram_2pZ1 - port map(hwdata_c(31) => hwdata_c(31), hwdata_c(30) => - hwdata_c(30), hwdata_c(29) => hwdata_c(29), hwdata_c(28) - => hwdata_c(28), hwdata_c(27) => hwdata_c(27), - hwdata_c(26) => hwdata_c(26), hwdata_c(25) => - hwdata_c(25), hwdata_c(24) => hwdata_c(24), hwdata_c(23) - => hwdata_c(23), hwdata_c(22) => hwdata_c(22), - hwdata_c(21) => hwdata_c(21), hwdata_c(20) => - hwdata_c(20), hwdata_c(19) => hwdata_c(19), hwdata_c(18) - => hwdata_c(18), hwdata_c(17) => hwdata_c(17), - hwdata_c(16) => hwdata_c(16), hwdata_c(15) => - hwdata_c(15), hwdata_c(14) => hwdata_c(14), hwdata_c(13) - => hwdata_c(13), hwdata_c(12) => hwdata_c(12), - hwdata_c(11) => hwdata_c(11), hwdata_c(10) => - hwdata_c(10), hwdata_c(9) => hwdata_c(9), hwdata_c(8) => - hwdata_c(8), hwdata_c(7) => hwdata_c(7), hwdata_c(6) => - hwdata_c(6), hwdata_c(5) => hwdata_c(5), hwdata_c(4) => - hwdata_c(4), hwdata_c(3) => hwdata_c(3), hwdata_c(2) => - hwdata_c(2), hwdata_c(1) => hwdata_c(1), hwdata_c(0) => - hwdata_c(0), Raddr_vect_RNI4A0PH(0) => - \Raddr_vect_RNI4A0PH[0]\, Raddr_vect_RNICA1PH(1) => - \Raddr_vect_RNICA1PH[1]\, Raddr_vect_RNIKA2PH(2) => - \Raddr_vect_RNIKA2PH[2]\, Raddr_vect_RNIE6Q5I(3) => - \Raddr_vect_RNIE6Q5I[3]\, Raddr_vect_RNIIMQ5I(4) => - \Raddr_vect_RNIIMQ5I[4]\, Waddr_vect_RNION355(0) => - \Waddr_vect_RNION355[0]\, Waddr_vect_RNI0O455(1) => - \Waddr_vect_RNI0O455[1]\, Waddr_vect_RNI394D5(2) => - \Waddr_vect_RNI394D5[2]\, Waddr_vect_RNIJTNE5(3) => - \Waddr_vect_RNIJTNE5[3]\, Waddr_vect_RNILLSP5(4) => - \Waddr_vect_RNILLSP5[4]\, wdata(31) => wdata(31), - wdata(30) => wdata(30), wdata(29) => wdata(29), wdata(28) - => wdata(28), wdata(27) => wdata(27), wdata(26) => - wdata(26), wdata(25) => wdata(25), wdata(24) => wdata(24), - wdata(23) => wdata(23), wdata(22) => wdata(22), wdata(21) - => wdata(21), wdata(20) => wdata(20), wdata(19) => - wdata(19), wdata(18) => wdata(18), wdata(17) => wdata(17), - wdata(16) => wdata(16), wdata(15) => wdata(15), wdata(14) - => wdata(14), wdata(13) => wdata(13), wdata(12) => - wdata(12), wdata(11) => wdata(11), wdata(10) => wdata(10), - wdata(9) => wdata(9), wdata(8) => wdata(8), wdata(7) => - wdata(7), wdata(6) => wdata(6), wdata(5) => wdata(5), - wdata(4) => wdata(4), wdata(3) => wdata(3), wdata(2) => - wdata(2), wdata(1) => wdata(1), wdata(0) => wdata(0), - HCLK_c => HCLK_c, N_1_i_1 => N_1_i_1, sEmpty_RNIE7T87 => - sEmpty_RNIE7T87, sEmpty_RNILSD08 => sEmpty_RNILSD08, - sFull_RNIHL443 => sFull_RNIHL443, sFull_RNIU5GK1 => - sFull_RNIU5GK1, syncram_2pZ1_GND => lpp_waveform_fifo_GND, - syncram_2pZ1_VCC => lpp_waveform_fifo_VCC, N_1_i_1_i => - N_1_i_1_i); - - \data_addr_w_iv_i_a2_2[0]\ : OR2A - port map(A => N_89, B => \time_mem_addr_w_3[0]\, Y => N_156); - - \data_addr_w_iv_i_a2_2_RNIRMOT[0]\ : AND2 - port map(A => \data_addr_w_iv_i_1[0]\, B => N_156, Y => - \data_addr_w_iv_i_2[0]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \gen_fifo_ctrl_data.2.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ2 - port map(ready_i_0(2) => ready_i_0(2), data_mem_wen_i_0(2) - => \data_mem_wen_i_0[2]\, data_ren(2) => data_ren(2), - Waddr_vect_RNI0O455(1) => \Waddr_vect_RNI0O455[1]\, - Waddr_vect_RNILLSP5(4) => \Waddr_vect_RNILLSP5[4]\, - Waddr_vect_RNIJTNE5(3) => \Waddr_vect_RNIJTNE5[3]\, - Waddr_vect_RNI394D5(2) => \Waddr_vect_RNI394D5[2]\, - data_mem_ren_i_0_0 => \data_mem_ren_i_0[0]\, - data_addr_r_0_iv_i_2(5) => \data_addr_r_0_iv_i_2[5]\, - data_addr_w_iv_i_4(4) => \data_addr_w_iv_i_4[4]\, - data_addr_w_iv_i_4(3) => \data_addr_w_iv_i_4[3]\, - data_addr_w_iv_i_4(2) => \data_addr_w_iv_i_4[2]\, - data_addr_w_iv_i_4(1) => \data_addr_w_iv_i_4[1]\, - data_addr_w_iv_i_4(0) => \data_addr_w_iv_i_4[0]\, - Waddr_vect_RNION355(0) => \Waddr_vect_RNION355[0]\, - data_wen(2) => data_wen(2), data_addr_r_iv_i_a2_0(4) => - \data_addr_r_iv_i_a2_0[4]\, data_addr_r_iv_i_a2_2(4) => - \data_addr_r_iv_i_a2_2[4]\, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, N_67 => N_67, N_166 => N_166, N_75 => - N_75, N_59 => N_59, N_51 => N_51, N_43 => N_43, N_152 => - N_152, N_128 => N_128, N_136 => N_136, N_144 => N_144, - sEmpty_RNIE7T87 => sEmpty_RNIE7T87, N_160 => N_160, N_77 - => N_77); - - GND_i : GND - port map(Y => \GND\); - - \gen_fifo_ctrl_time.1.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ5 - port map(time_mem_wen_i_0_0 => \time_mem_wen_i_0[0]\, - Waddr_vect_RNINV58(2) => \Waddr_vect_RNINV58[2]\, - Waddr_vect_RNILN58(0) => \Waddr_vect_RNILN58[0]\, - Raddr_vect_RNI8J9L(2) => \Raddr_vect_RNI8J9L[2]\, - time_mem_ren_i_0(1) => \time_mem_ren_i_0[1]\, time_wen(1) - => time_wen(1), time_ren(1) => time_ren(1), HRESETn_c - => HRESETn_c, HCLK_c => HCLK_c, N_146 => N_146, N_162 - => N_162, N_113 => N_113, N_122 => N_122, - sFull_RNIPQBB_0 => sFull_RNIPQBB_0, N_62 => N_62, N_70 - => N_70, sEmpty_RNI5EFO_0 => sEmpty_RNI5EFO_0, N_33 => - N_33, N_29 => N_29); - - \gen_fifo_ctrl_data.3.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ3 - port map(ready_i_0(3) => ready_i_0(3), data_mem_wen_i_0_0 - => \data_mem_wen_i_0[2]\, data_ren(3) => data_ren(3), - data_wen(3) => data_wen(3), HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, N_128 => N_128, N_152 => N_152, N_136 - => N_136, N_68 => N_68, N_144 => N_144, N_166 => N_166, - N_160 => N_160, N_76 => N_76, N_60 => N_60, N_52 => N_52, - N_86 => N_86, N_44 => N_44, N_1_i_1 => N_1_i_1, N_1_i_1_i - => N_1_i_1_i); - - \gen_fifo_ctrl_data.0.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ0 - port map(ready_i_0(0) => ready_i_0(0), data_ren(0) => - data_ren(0), data_addr_w_0_iv_i_1(5) => - \data_addr_w_0_iv_i_1[5]\, data_addr_r_1_iv_i_s_1(6) => - \data_addr_r_1_iv_i_s_1[6]\, data_addr_r_1_iv_i_a9_1_1(6) - => \data_addr_r_1_iv_i_a9_1_1[6]\, data_mem_ren_i_0(0) - => \data_mem_ren_i_0[0]\, data_mem_wen_i_0_1 => - \data_mem_wen_i_0[1]\, data_addr_w_1_iv_i_a2_1_1_0(6) => - \data_addr_w_1_iv_i_a2_1_1_0[6]\, data_addr_w_iv_i_2(4) - => \data_addr_w_iv_i_2[4]\, data_addr_w_iv_i_2(3) => - \data_addr_w_iv_i_2[3]\, data_addr_w_iv_i_2(2) => - \data_addr_w_iv_i_2[2]\, data_addr_w_iv_i_2(1) => - \data_addr_w_iv_i_2[1]\, data_addr_w_iv_i_2(0) => - \data_addr_w_iv_i_2[0]\, data_addr_w_iv_i_4(4) => - \data_addr_w_iv_i_4[4]\, data_addr_w_iv_i_4(3) => - \data_addr_w_iv_i_4[3]\, data_addr_w_iv_i_4(2) => - \data_addr_w_iv_i_4[2]\, data_addr_w_iv_i_4(1) => - \data_addr_w_iv_i_4[1]\, data_addr_w_iv_i_4(0) => - \data_addr_w_iv_i_4[0]\, data_wen(0) => data_wen(0), - data_addr_r_iv_i_0(4) => \data_addr_r_iv_i_0[4]\, - data_addr_r_iv_i_0(3) => \data_addr_r_iv_i_0[3]\, - data_addr_r_iv_i_0(2) => \data_addr_r_iv_i_0[2]\, - data_addr_r_iv_i_0(1) => \data_addr_r_iv_i_0[1]\, - data_addr_r_iv_i_0(0) => \data_addr_r_iv_i_0[0]\, - data_addr_r_iv_i_1(4) => \data_addr_r_iv_i_1[4]\, - data_addr_r_iv_i_1(3) => \data_addr_r_iv_i_1[3]\, - data_addr_r_iv_i_1(2) => \data_addr_r_iv_i_1[2]\, - data_addr_r_iv_i_1(1) => \data_addr_r_iv_i_1[1]\, - data_addr_r_iv_i_1(0) => \data_addr_r_iv_i_1[0]\, - data_addr_r_iv_i_3(4) => \data_addr_r_iv_i_3[4]\, - data_addr_r_iv_i_3(3) => \data_addr_r_iv_i_3[3]\, - data_addr_r_iv_i_3(2) => \data_addr_r_iv_i_3[2]\, - data_addr_r_iv_i_3(1) => \data_addr_r_iv_i_3[1]\, - data_addr_r_iv_i_3(0) => \data_addr_r_iv_i_3[0]\, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_165 => N_165, - N_120_i => N_120_i, sFull_RNIHL443 => sFull_RNIHL443, - sEmpty_RNILSD08 => sEmpty_RNILSD08, N_124 => N_124, N_164 - => N_164, N_158 => N_158, N_142 => N_142, N_134 => N_134, - N_126 => N_126, N_150 => N_150); - - \data_addr_w_iv_i_a2_2_RNIACB71[3]\ : AND2 - port map(A => N_132, B => \data_addr_w_iv_i_1[3]\, Y => - \data_addr_w_iv_i_2[3]\); - - \data_addr_w_iv_i_a2_2[3]\ : NAND2 - port map(A => N_89, B => \time_mem_addr_w_3_i_0[3]\, Y => - N_132); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \gen_fifo_ctrl_time.0.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ4 - port map(time_mem_ren_i_0_1 => \time_mem_ren_i_0[1]\, - time_wen(0) => time_wen(0), time_ren(0) => time_ren(0), - data_addr_w_0_iv_i_1(5) => \data_addr_w_0_iv_i_1[5]\, - Waddr_vect_RNILN58(0) => \Waddr_vect_RNILN58[0]\, - Waddr_vect_RNINV58(2) => \Waddr_vect_RNINV58[2]\, - Waddr_vect_RNI64MA(2) => \Waddr_vect_RNI64MA[2]\, - data_addr_w_iv_i_2_0 => \data_addr_w_iv_i_2[2]\, - data_addr_w_iv_i_2_2 => \data_addr_w_iv_i_2[4]\, - time_mem_wen_i_0(0) => \time_mem_wen_i_0[0]\, - data_addr_r_0_iv_i_1(5) => \data_addr_r_0_iv_i_1[5]\, - data_addr_r_0_iv_i_2(5) => \data_addr_r_0_iv_i_2[5]\, - Raddr_vect_RNI8J9L(2) => \Raddr_vect_RNI8J9L[2]\, - data_addr_r_iv_i_0(4) => \data_addr_r_iv_i_0[4]\, - data_addr_r_iv_i_0(3) => \data_addr_r_iv_i_0[3]\, - data_addr_r_iv_i_0(2) => \data_addr_r_iv_i_0[2]\, - data_addr_r_iv_i_0(1) => \data_addr_r_iv_i_0[1]\, - data_addr_r_iv_i_0(0) => \data_addr_r_iv_i_0[0]\, - data_addr_w_iv_i_1_0 => \data_addr_w_iv_i_1[0]\, - data_addr_w_iv_i_1_3 => \data_addr_w_iv_i_1[3]\, - data_addr_w_iv_i_1_1 => \data_addr_w_iv_i_1[1]\, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_77 => N_77, - sFull_RNI9VRD => sFull_RNI9VRD, N_140 => N_140, - sFull_RNIPQBB_0 => sFull_RNIPQBB_0, N_122 => N_122, N_124 - => N_124, sFull_RNI9VRD_0 => sFull_RNI9VRD_0, N_146 => - N_146, N_70 => N_70, sEmpty_RNI5EFO_0 => sEmpty_RNI5EFO_0, - N_33 => N_33, N_62 => N_62, N_155 => N_155, - sFull_RNI9VRD_1 => sFull_RNI9VRD_1, N_147 => N_147); - - \data_addr_w_iv_i_a2_2[1]\ : OR2A - port map(A => N_89, B => \time_mem_addr_w_3[1]\, Y => N_148); - - \gen_fifo_ctrl_time.2.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ6 - port map(Waddr_vect_RNI64MA(2) => \Waddr_vect_RNI64MA[2]\, - data_addr_w_1_iv_i_s_0_0(6) => - \data_addr_w_1_iv_i_s_0_0[6]\, time_wen(2) => time_wen(2), - data_addr_r_0_iv_i_1(5) => \data_addr_r_0_iv_i_1[5]\, - data_addr_r_1_iv_i_s_1(6) => \data_addr_r_1_iv_i_s_1[6]\, - time_mem_ren_i_0_1 => \time_mem_ren_i_0[3]\, - data_addr_r_iv_i_a2_0(4) => \data_addr_r_iv_i_a2_0[4]\, - data_addr_r_iv_i_1(4) => \data_addr_r_iv_i_1[4]\, - data_addr_r_iv_i_1(3) => \data_addr_r_iv_i_1[3]\, - data_addr_r_iv_i_1(2) => \data_addr_r_iv_i_1[2]\, - data_addr_r_iv_i_1(1) => \data_addr_r_iv_i_1[1]\, - data_addr_r_iv_i_1(0) => \data_addr_r_iv_i_1[0]\, - time_ren(2) => time_ren(2), time_ren_1z => time_ren_1z, - HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, sFull_RNI9VRD_0 - => sFull_RNI9VRD_0, N_147 => N_147, sFull_RNI9VRD_1 => - sFull_RNI9VRD_1, sFull_RNI9VRD => sFull_RNI9VRD, - un13_time_write => un13_time_write, N_163 => N_163, N_155 - => N_155, N_162 => N_162, sFull_RNIU5GK1 => - sFull_RNIU5GK1, N_29 => N_29, N_30_1 => N_30_1, N_72 => - N_72, N_56 => N_56, N_48 => N_48, N_35 => N_35, N_64 => - N_64); - - \data_addr_w_iv_i_a2_2_RNIV6PT[1]\ : AND2 - port map(A => \data_addr_w_iv_i_1[1]\, B => N_148, Y => - \data_addr_w_iv_i_2[1]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_11 is - - port( sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - data_f0_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(10 downto 0); - sample_f0_37 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_63 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_0 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_15 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f0_out_valid : out std_logic; - enable_f0 : in std_logic; - data_shaping_R0 : in std_logic; - data_shaping_R0_0 : in std_logic; - start_snapshot_f0 : in std_logic; - sample_f0_val_0 : in std_logic; - burst_f0 : in std_logic - ); - -end lpp_waveform_snapshot_160_11; - -architecture DEF_ARCH of lpp_waveform_snapshot_160_11 is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_data_out_valid_0_sqmuxa_1_1[31]\, - data_out_valid_0_sqmuxa_1, - \counter_points_snapshot_0_sqmuxa_1_0\, - \un1_data_out_valid_0_sqmuxa_1_0[31]\, - \data_out_valid_0_sqmuxa\, ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I310_Y_0_0, - \counter_points_snapshot[30]_net_1\, - ADD_32x32_fast_I250_Y_2, ADD_32x32_fast_I250_Y_1, N483, - N487, N467, N470, N479, ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I253_Y_0_0, I94_un1_Y, N485, - ADD_32x32_fast_I295_Y_0_0, - \un1_counter_points_snapshot[16]\, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I288_Y_0_0, - \un1_counter_points_snapshot[23]\, - ADD_32x32_fast_I251_Y_2, ADD_32x32_fast_I251_Y_1, N489, - N464, ADD_32x32_fast_I302_Y_0_0, - \un1_counter_points_snapshot[9]\, - ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, - ADD_32x32_fast_I294_Y_0_0, - \un1_counter_points_snapshot[17]\, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I309_Y_0_0, - \counter_points_snapshot[29]_net_1\, - ADD_32x32_fast_I300_Y_0_0, - \un1_counter_points_snapshot[11]\, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot[5]\, - ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I287_Y_0_0, - \un1_counter_points_snapshot[24]\, - ADD_32x32_fast_I291_Y_0_0, - \un1_counter_points_snapshot[20]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I301_Y_0_0, - \un1_counter_points_snapshot[10]\, - ADD_32x32_fast_I254_Y_0, N554, ADD_32x32_fast_I259_Y_0, - N636, N620, ADD_32x32_fast_I297_Y_0_0, - \counter_points_snapshot[17]_net_1\, - ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I252_Y_1, ADD_32x32_fast_I252_Y_0, N491, - ADD_32x32_fast_I289_Y_0_0, - \un1_counter_points_snapshot[22]\, - ADD_32x32_fast_I255_Y_0, N556, ADD_32x32_fast_I293_Y_0_0, - \un1_counter_points_snapshot[18]\, - ADD_32x32_fast_I256_Y_0, N558, ADD_32x32_fast_I284_Y_0_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I263_Y_0, N644, N628, - ADD_32x32_fast_I283_Y_0_0, - \un1_counter_points_snapshot[28]\, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot[26]\, - ADD_32x32_fast_I118_Y_0, ADD_32x32_fast_I110_Y_0, - ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I126_Y_1, - \un1_counter_points_snapshot[21]\, - data_out_valid_0_sqmuxa_1_1, un4_data_in_validlt30_27, - un4_data_in_validlt30_18, un4_data_in_validlt30_17, - un4_data_in_validlt30_23, un4_data_in_validlt30_26, - un4_data_in_validlt30_12, un4_data_in_validlt30_11, - un4_data_in_validlt30_22, un4_data_in_validlt30_25, - un4_data_in_validlt30_8, un4_data_in_validlt30_7, - un4_data_in_validlt30_20, un4_data_in_validlt30_2, - un4_data_in_validlt30_1, un4_data_in_validlt30_15, - un4_data_in_validlt30_14, - \counter_points_snapshot[27]_net_1\, - \counter_points_snapshot[26]_net_1\, - un4_data_in_validlt30_10, - \counter_points_snapshot[19]_net_1\, - \counter_points_snapshot[18]_net_1\, - un4_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un4_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[28]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[22]_net_1\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[20]_net_1\, - \counter_points_snapshot[21]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[14]_net_1\, - \counter_points_snapshot[15]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[13]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, - \un1_data_out_valid_0_sqmuxa_2[4]\, N533, N529, N754, - N634, N618, N650, un4_data_in_validlto30_i, N740, N774, - N764, N738, N771, N744, N752, - \un1_data_out_valid_0_sqmuxa_2[6]\, N652_i, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, N380, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_counter_points_snapshot[29]\, - \un1_data_out_valid_0_sqmuxa_2[5]\, N654, - \un1_data_out_valid_0_sqmuxa_2[8]\, N401, - \un1_data_out_valid_0_sqmuxa_2[10]\, N786, N750, N630, - N789, \un1_data_out_valid_0_sqmuxa_2[9]\, N756, N748, - N497, N766, N646, N746, N626, N783, N572, N419, I66_un1_Y, - N580, N407, N588, \un1_data_out_valid_0_sqmuxa_2[3]\, - N594, \un1_data_out_valid_0_sqmuxa_2[7]\, N762, N642, - N564, I60_un1_Y, N431, N758, N622, N638, N742, N777, - \sample_f0_wdata[32]\, \sample_f0_wdata[33]\, - \sample_f0_wdata[34]\, \sample_f0_wdata[35]\, - \sample_f0_wdata[19]\, \sample_f0_wdata[20]\, - \sample_f0_wdata[21]\, \sample_f0_wdata[22]\, - \sample_f0_wdata[23]\, \sample_f0_wdata[24]\, - \sample_f0_wdata[25]\, \sample_f0_wdata[26]\, - \sample_f0_wdata[27]\, \sample_f0_wdata[28]\, - \sample_f0_wdata[29]\, \sample_f0_wdata[30]\, - \sample_f0_wdata[31]\, \sample_f0_wdata[43]\, - \sample_f0_wdata[44]\, \sample_f0_wdata[45]\, - \sample_f0_wdata[46]\, \sample_f0_wdata[47]\, - \sample_f0_wdata[16]\, \sample_f0_wdata[17]\, - \sample_f0_wdata[18]\, \sample_f0_wdata[36]\, - \sample_f0_wdata[37]\, \sample_f0_wdata[38]\, - \sample_f0_wdata[39]\, \sample_f0_wdata[40]\, - \sample_f0_wdata[41]\, \sample_f0_wdata[42]\, - \counter_points_snapshot_10[4]\, N_90, - \counter_points_snapshot_2_sqmuxa\, - \counter_points_snapshot_10[23]\, - un1_counter_points_snapshot_0_sqmuxa_1_i, N461, - \counter_points_snapshot_3_sqmuxa\, - \un1_data_out_valid_0_sqmuxa_1[31]\, - counter_points_snapshot_0_sqmuxa_i, data_out_valid_19, - un1_enable_2, \counter_points_snapshot_10[30]\, - \counter_points_snapshot_0_sqmuxa_1\, - \counter_points_snapshot_10[31]\, - \counter_points_snapshot_10[22]\, - \counter_points_snapshot_10[24]\, - \counter_points_snapshot_10[28]\, N760, - \counter_points_snapshot_10[18]\, N590, N582, N_92, - \counter_points_snapshot_2_sqmuxa_2\, - \counter_points_snapshot_10[6]\, N507, N511, N578, N586, - I74_un1_Y, \un1_counter_points_snapshot[31]\, - \counter_points_snapshot_10[10]\, N_96, - \counter_points_snapshot_10[8]\, N_94, - \counter_points_snapshot_10[5]\, N_91, - \counter_points_snapshot_10[2]\, N_88, - \counter_points_snapshot_10[1]\, N_87, N562, - \counter_points_snapshot_10[25]\, N_95, - \counter_points_snapshot_10[9]\, - \counter_points_snapshot_10[27]\, - \counter_points_snapshot_10[26]\, - \counter_points_snapshot_10[17]\, - \counter_points_snapshot_10[14]\, - \counter_points_snapshot_10[15]\, - \counter_points_snapshot_10[11]\, N515, - \counter_points_snapshot_10[16]\, N768, N523, N531, N527, - \un1_data_out_valid_0_sqmuxa_2[0]\, N_86, - \counter_points_snapshot_10[0]\, - \counter_points_snapshot_10[19]\, - \counter_points_snapshot_10[7]\, N_93, - \counter_points_snapshot_10[3]\, N_89, - \counter_points_snapshot_10[20]\, N434, N780, - \counter_points_snapshot_10[12]\, - \counter_points_snapshot_10[29]\, - \counter_points_snapshot_10[21]\, - \counter_points_snapshot_10[13]\, N574, N566, N503, N495, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter_points_snapshot_RNIV49P[18]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - \counter_points_snapshot_RNIRF66[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un4_data_in_validlt30_1); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[13]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : AX1A - port map(A => N533, B => N529, C => - ADD_32x32_fast_I284_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - \data_out[110]\ : DFN1C0 - port map(D => \sample_f0_wdata[46]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(110)); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[10]\, B => - nb_snapshot_param(10), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_96); - - \counter_points_snapshot_RNO[27]\ : XA1C - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[27]\); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[28]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[28]_net_1\); - - \counter_points_snapshot_RNIVG9N[0]\ : NOR3C - port map(A => un4_data_in_validlt30_2, B => - un4_data_in_validlt30_1, C => un4_data_in_validlt30_15, Y - => un4_data_in_validlt30_23); - - \counter_points_snapshot_RNI37D9[24]\ : NOR2 - port map(A => \counter_points_snapshot[24]_net_1\, B => - \counter_points_snapshot[25]_net_1\, Y => - un4_data_in_validlt30_12); - - data_out_valid_0_sqmuxa : OR2B - port map(A => sample_f0_val_0, B => start_snapshot_f0, Y - => \data_out_valid_0_sqmuxa\); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762, B => ADD_32x32_fast_I299_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[19]\); - - \data_out_RNO[96]\ : MX2 - port map(A => sample_f0_15, B => sample_f0_47, S => - data_shaping_R0_0, Y => \sample_f0_wdata[32]\); - - \data_out[91]\ : DFN1C0 - port map(D => \sample_f0_wdata[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(91)); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f0_wdata_56, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1C - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : NOR3 - port map(A => N626, B => ADD_32x32_fast_I254_Y_0, C => N783, - Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : OR2 - port map(A => N586, B => N578, Y => N642); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f0_wdata_66, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => \sample_f0_wdata[40]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(104)); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => nb_snapshot_param(4), B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_90); - - \counter_points_snapshot_RNIRK8P[14]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[14]_net_1\, Y => - \un1_counter_points_snapshot[17]\); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[1]\, B => - nb_snapshot_param(1), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_87); - - \counter_points_snapshot_RNIHHQQ[3]\ : MX2 - port map(A => nb_snapshot_param(3), B => - \counter_points_snapshot[3]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[28]\); - - \data_out[102]\ : DFN1C0 - port map(D => \sample_f0_wdata[38]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I64_Y : AO1A - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_data_out_valid_0_sqmuxa_1[31]\, C => N419, Y => N507); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3B - port map(A => ADD_32x32_fast_I252_Y_1, B => N777, C => N622, - Y => N742); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_93, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[29]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1B - port map(A => N780, B => ADD_32x32_fast_I292_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[12]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : OR2 - port map(A => N650, B => N634, Y => N771); - - \data_out[93]\ : DFN1C0 - port map(D => \sample_f0_wdata[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(93)); - - \counter_points_snapshot_RNISO8P[15]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - \un1_counter_points_snapshot[16]\); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[4]_net_1\); - - counter_points_snapshot_2_sqmuxa : OR3B - port map(A => enable_f0, B => - \counter_points_snapshot_2_sqmuxa_2\, C => burst_f0, Y - => \counter_points_snapshot_2_sqmuxa\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f0_wdata_95, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => \sample_f0_wdata[41]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(105)); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[15]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f0_wdata_77, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR2 - port map(A => N495, B => N491, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2 - port map(A => N527, B => N523, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => \sample_f0_wdata[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(81)); - - \data_out_RNO[99]\ : MX2 - port map(A => sample_f0_12, B => sample_f0_44, S => - data_shaping_R0_0, Y => \sample_f0_wdata[35]\); - - \counter_points_snapshot_RNIB5QQ[0]\ : MX2 - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[30]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I310_Y_0_0); - - \data_out_RNO[104]\ : MX2 - port map(A => sample_f0_7, B => sample_f0_39, S => - data_shaping_R0, Y => \sample_f0_wdata[40]\); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : OR3 - port map(A => N487, B => N491, C => N558, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - NOR2 - port map(A => N771, B => I60_un1_Y, Y => N768); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f0_wdata_50, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(114)); - - \counter_points_snapshot_RNIR5RQ[8]\ : MX2C - port map(A => nb_snapshot_param(8), B => - \counter_points_snapshot[8]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[23]\); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : OR3 - port map(A => N507, B => N511, C => N578, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : OR2 - port map(A => N507, B => N503, Y => N566); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[27]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f0_wdata_79, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : OR2 - port map(A => N590, B => N380, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR2 - port map(A => ADD_32x32_fast_I110_Y_0, B => N497, Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f0_wdata_48, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(112)); - - \counter_points_snapshot_RNIP88P[21]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - \un1_counter_points_snapshot[10]\); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f0_wdata_60, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(124)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f0_wdata_70, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : OA1A - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_counter_points_snapshot[26]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N523); - - \counter_points_snapshot_RNO[28]\ : XA1C - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[28]\); - - \data_out[83]\ : DFN1C0 - port map(D => \sample_f0_wdata[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I250_Y_1, B => N483, C => N487, - Y => ADD_32x32_fast_I250_Y_2); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f0_wdata_58, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f0_wdata_51, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(115)); - - \counter_points_snapshot_RNID01S[10]\ : MX2C - port map(A => nb_snapshot_param(10), B => - \counter_points_snapshot[10]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[21]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : AOI1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : OA1 - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[5]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => I94_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[17]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f0_wdata_68, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(132)); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[30]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[30]_net_1\); - - \data_out[96]\ : DFN1C0 - port map(D => \sample_f0_wdata[32]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(96)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : NOR3 - port map(A => N628, B => ADD_32x32_fast_I255_Y_0, C => N786, - Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f0_wdata_61, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(125)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f0_wdata_71, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(135)); - - \data_out_RNO[87]\ : NOR2B - port map(A => sample_f0_56, B => data_shaping_R0_0, Y => - \sample_f0_wdata[23]\); - - \data_out_RNO[108]\ : MX2 - port map(A => sample_f0_3, B => sample_f0_35, S => - data_shaping_R0, Y => \sample_f0_wdata[44]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_G0N : NOR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[16]\, Y => I60_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : NOR2 - port map(A => ADD_32x32_fast_I253_Y_0_0, B => N752, Y => - N744); - - \counter_points_snapshot_RNID9QQ[1]\ : MX2C - port map(A => nb_snapshot_param(1), B => - \counter_points_snapshot[1]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[30]\); - - data_out_valid : DFN1C0 - port map(D => data_out_valid_19, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out_valid); - - \data_out_RNO[90]\ : NOR2B - port map(A => sample_f0_53, B => data_shaping_R0_0, Y => - \sample_f0_wdata[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : OR3 - port map(A => N507, B => N511, C => N562, Y => N626); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I29_G0N : OR3B - port map(A => \counter_points_snapshot[29]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1\, C => - data_out_valid_0_sqmuxa_1, Y => N467); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f0_wdata_7, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f0_wdata_1, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(65)); - - \counter_points_snapshot_RNIUS8P[26]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot[5]\); - - \counter_points_snapshot_RNIO88P[11]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[11]_net_1\, Y => - \un1_counter_points_snapshot[20]\); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[18]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : NOR3 - port map(A => N622, B => N638, C => N654, Y => N758); - - \data_out_RNO[98]\ : MX2 - port map(A => sample_f0_13, B => sample_f0_45, S => - data_shaping_R0_0, Y => \sample_f0_wdata[34]\); - - \data_out[86]\ : DFN1C0 - port map(D => \sample_f0_wdata[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[23]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I288_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : OR2 - port map(A => N562, B => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f0_wdata_86, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(150)); - - \counter_points_snapshot_RNIQC8P[22]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[22]_net_1\, Y => - \un1_counter_points_snapshot[9]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[17]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f0_wdata_84, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(148)); - - GND_i : GND - port map(Y => \GND\); - - \counter_points_snapshot_RNIPC8P[12]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - \counter_points_snapshot_RNIB7E9[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un4_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_G0N : NOR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[18]\, Y => N419); - - \counter_points_snapshot_RNIA0DC[6]\ : NOR3A - port map(A => un4_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un4_data_in_validlt30_17); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[8]_net_1\); - - counter_points_snapshot_2_sqmuxa_2 : NOR2A - port map(A => start_snapshot_f0, B => sample_f0_val_0, Y - => \counter_points_snapshot_2_sqmuxa_2\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : OR2 - port map(A => N574, B => N566, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR3 - port map(A => I74_un1_Y, B => N401, C => N523, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f0_wdata_9, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I283_Y_0_0); - - \data_out[92]\ : DFN1C0 - port map(D => \sample_f0_wdata[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f0_wdata_3, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => \sample_f0_wdata[43]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OR2 - port map(A => N644, B => N628, Y => ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_92, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[21]\, C => N786, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[29]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[29]_net_1\); - - \counter_points_snapshot_RNIDBS75_1[31]\ : OR2B - port map(A => data_out_valid_0_sqmuxa_1, B => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_data_out_valid_0_sqmuxa_1[31]\); - - \counter_points_snapshot_RNI28AJ4[31]\ : OR2 - port map(A => data_out_valid_0_sqmuxa_1_1, B => - un4_data_in_validlto30_i, Y => data_out_valid_0_sqmuxa_1); - - \data_out_RNO[94]\ : NOR2B - port map(A => sample_f0_49, B => data_shaping_R0_0, Y => - \sample_f0_wdata[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1B - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[25]\); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[20]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I302_Y_0_0); - - \counter_points_snapshot_RNIR6C9[20]\ : NOR2 - port map(A => \counter_points_snapshot[20]_net_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - un4_data_in_validlt30_10); - - \data_out_RNO[95]\ : NOR2B - port map(A => sample_f0_48, B => data_shaping_R0, Y => - \sample_f0_wdata[31]\); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[17]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : OR2 - port map(A => N590, B => N582, Y => N646); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : AOI1B - port map(A => \un1_counter_points_snapshot[30]\, B => - \un1_counter_points_snapshot[29]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I28_G0N : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[3]\, Y => N464); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : OR3A - port map(A => ADD_32x32_fast_I250_Y_2, B => N618, C => N771, - Y => N738); - - \data_out_RNO[93]\ : NOR2B - port map(A => sample_f0_50, B => data_shaping_R0_0, Y => - \sample_f0_wdata[29]\); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f0_wdata_90, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(154)); - - \counter_points_snapshot_RNITMC9[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un4_data_in_validlt30_6); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - OR2A - port map(A => N764, B => N497, Y => N760); - - \data_out[82]\ : DFN1C0 - port map(D => \sample_f0_wdata[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f0_wdata_53, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1C - port map(A => N760, B => ADD_32x32_fast_I300_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : OR3 - port map(A => N483, B => N487, C => N554, Y => - ADD_32x32_fast_I254_Y_0); - - \counter_points_snapshot_RNIT9RQ[9]\ : MX2C - port map(A => nb_snapshot_param(9), B => - \counter_points_snapshot[9]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[22]\); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f0_wdata_12, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f0_wdata_88, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(152)); - - \counter_points_snapshot_RNIVMC9[22]\ : NOR2 - port map(A => \counter_points_snapshot[22]_net_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - un4_data_in_validlt30_11); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f0_wdata_85, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(149)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f0_wdata_63, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : NOR2 - port map(A => N654, B => N638, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : OR2B - port map(A => N652_i, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : NOR2 - port map(A => N588, B => N533, Y => N652_i); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f0_wdata_73, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I30_G0N : OR3B - port map(A => \counter_points_snapshot[30]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - data_out_valid_0_sqmuxa_1, Y => N470); - - \data_out_RNO[81]\ : NOR2B - port map(A => sample_f0_62, B => data_shaping_R0, Y => - \sample_f0_wdata[17]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : OR2 - port map(A => N531, B => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f0_wdata_91, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(155)); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_91, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1B - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[17]\); - - \counter_points_snapshot_RNI099P[19]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - data_out_valid_RNO_0 : AO1B - port map(A => data_out_valid_0_sqmuxa_1, B => - \data_out_valid_0_sqmuxa\, C => enable_f0, Y => - un1_enable_2); - - \data_out[90]\ : DFN1C0 - port map(D => \sample_f0_wdata[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(90)); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR3B - port map(A => N620, B => ADD_32x32_fast_I251_Y_2, C => N774, - Y => N740); - - \counter_points_snapshot_RNO[14]\ : XA1C - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[14]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR3 - port map(A => I74_un1_Y, B => N401, C => N515, Y => N578); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[29]\, C => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - \data_out_RNO[92]\ : NOR2B - port map(A => sample_f0_51, B => data_shaping_R0_0, Y => - \sample_f0_wdata[28]\); - - \counter_points_snapshot_RNIO48P[20]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[20]_net_1\, Y => - \un1_counter_points_snapshot[11]\); - - \data_out[99]\ : DFN1C0 - port map(D => \sample_f0_wdata[35]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(99)); - - \data_out_RNO[100]\ : MX2 - port map(A => sample_f0_11, B => sample_f0_43, S => - data_shaping_R0, Y => \sample_f0_wdata[36]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : NOR3 - port map(A => N634, B => N618, C => N650, Y => N754); - - \counter_points_snapshot_RNISK8P[24]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - \data_out[106]\ : DFN1C0 - port map(D => \sample_f0_wdata[42]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1C - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[21]\); - - \counter_points_snapshot_RNITO8P[25]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - \counter_points_snapshot_RNITNQ14[6]\ : NOR3C - port map(A => un4_data_in_validlt30_26, B => - un4_data_in_validlt30_25, C => un4_data_in_validlt30_27, - Y => un4_data_in_validlto30_i); - - \data_out_RNO[103]\ : MX2 - port map(A => sample_f0_8, B => sample_f0_40, S => - data_shaping_R0, Y => \sample_f0_wdata[39]\); - - \counter_points_snapshot_RNIVEFM1[6]\ : NOR3C - port map(A => un4_data_in_validlt30_18, B => - un4_data_in_validlt30_17, C => un4_data_in_validlt30_23, - Y => un4_data_in_validlt30_27); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : OR2 - port map(A => N515, B => N511, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => \sample_f0_wdata[34]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(98)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y : NOR3 - port map(A => I60_un1_Y, B => N431, C => - ADD_32x32_fast_I118_Y_0, Y => N564); - - \counter_points_snapshot_RNIFDQQ[2]\ : MX2C - port map(A => nb_snapshot_param(2), B => - \counter_points_snapshot[2]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[29]\); - - \data_out[80]\ : DFN1C0 - port map(D => \sample_f0_wdata[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f0_wdata_8, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : NOR3 - port map(A => N630, B => ADD_32x32_fast_I256_Y_0, C => N789, - Y => N750); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : AX1B - port map(A => N401, B => N650, C => - ADD_32x32_fast_I288_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - \data_out_RNO[107]\ : MX2 - port map(A => sample_f0_4, B => sample_f0_36, S => - data_shaping_R0, Y => \sample_f0_wdata[43]\); - - \data_out[89]\ : DFN1C0 - port map(D => \sample_f0_wdata[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(89)); - - \counter_points_snapshot_RNI059P[28]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : NOR2 - port map(A => ADD_32x32_fast_I263_Y_0, B => N533, Y => N764); - - \counter_points_snapshot_RNIQG8P[13]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - \un1_counter_points_snapshot[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I289_Y_0_0, B => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out_RNO[101]\ : MX2 - port map(A => sample_f0_10, B => sample_f0_42, S => - data_shaping_R0, Y => \sample_f0_wdata[37]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f0_wdata_52, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[19]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[2]\, B => - nb_snapshot_param(2), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_88); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : OR2 - port map(A => N594, B => N586, Y => N650); - - \counter_points_snapshot_RNITS8P[16]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[26]\, C => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1C - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[18]\); - - \data_out[88]\ : DFN1C0 - port map(D => \sample_f0_wdata[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XOR2 - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[31]\, Y => - \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f0_wdata_62, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => \sample_f0_wdata[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f0_wdata_76, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f0_wdata_72, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(136)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I27_G0N : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[4]\, Y => N461); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[18]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I293_Y_0_0); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[22]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[22]_net_1\); - - \data_out_RNO[86]\ : NOR2B - port map(A => sample_f0_57, B => data_shaping_R0_0, Y => - \sample_f0_wdata[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2 - port map(A => N531, B => N380, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I304_Y_0_0); - - data_out_valid_RNO_1 : NOR2B - port map(A => enable_f0, B => burst_f0, Y => - counter_points_snapshot_0_sqmuxa_i); - - \data_out[101]\ : DFN1C0 - port map(D => \sample_f0_wdata[37]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(101)); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f0_wdata_93, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_90, Y => - \counter_points_snapshot_10[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y_0 : OA1A - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot[10]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I110_Y_0); - - \counter_points_snapshot_RNO[30]\ : XA1B - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[30]\); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : - AO1C - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_data_out_valid_0_sqmuxa_1[31]\, C => N434, Y => N497); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR2A - port map(A => N564, B => N572, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AO1B - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_counter_points_snapshot[23]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I134_Y_0); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f0_wdata_6, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[5]\, B => - nb_snapshot_param(5), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_91); - - \data_out[84]\ : DFN1C0 - port map(D => \sample_f0_wdata[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => \sample_f0_wdata[39]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I7_G0N : NOR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[24]\, Y => N401); - - \counter_points_snapshot_RNIRG8P[23]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : OA1 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[27]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I8_G0N : NOR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[23]\, Y => I74_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I289_Y_0_0); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f0_wdata_15, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f0_wdata_80, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(144)); - - \data_out_RNO[89]\ : NOR2B - port map(A => sample_f0_54, B => data_shaping_R0_0, Y => - \sample_f0_wdata[25]\); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_94, Y => - \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => \sample_f0_wdata[47]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : NOR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[31]\, Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f0_wdata_78, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f0_wdata_14, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[23]\); - - \counter_points_snapshot_RNIDBS75[31]\ : OR2B - port map(A => data_out_valid_0_sqmuxa_1, B => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_data_out_valid_0_sqmuxa_1_0[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : NOR2 - port map(A => N580, B => N572, Y => N636); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => nb_snapshot_param(3), B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_89); - - \counter_points_snapshot_RNI5HSA[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[30]_net_1\, Y => - un4_data_in_validlt30_15); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[26]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : NOR3A - port map(A => ADD_32x32_fast_I252_Y_0, B => N487, C => N491, - Y => ADD_32x32_fast_I252_Y_1); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f0_wdata_57, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : AO1A - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_data_out_valid_0_sqmuxa_1[31]\, C => I60_un1_Y, Y - => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_86, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f0_wdata_67, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f0_wdata_49, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(113)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f0_wdata_81, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(145)); - - \counter_points_snapshot_RNI5ND9[16]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un4_data_in_validlt30_8); - - \counter_points_snapshot_RNIIURI[26]\ : NOR3A - port map(A => un4_data_in_validlt30_14, B => - \counter_points_snapshot[27]_net_1\, C => - \counter_points_snapshot[26]_net_1\, Y => - un4_data_in_validlt30_22); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f0_wdata_2, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[1]_net_1\); - - \counter_points_snapshot_RNO[31]\ : XA1C - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[31]\); - - \data_out_RNO[109]\ : MX2 - port map(A => sample_f0_2, B => sample_f0_34, S => - data_shaping_R0, Y => \sample_f0_wdata[45]\); - - \counter_points_snapshot_RNO_0[0]\ : MX2C - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_86); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N771, B => ADD_32x32_fast_I295_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[15]\); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f0_wdata_59, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(123)); - - \counter_points_snapshot_RNIKSL51[22]\ : NOR3C - port map(A => un4_data_in_validlt30_12, B => - un4_data_in_validlt30_11, C => un4_data_in_validlt30_22, - Y => un4_data_in_validlt30_26); - - GND_i_0 : GND - port map(Y => GND_0); - - counter_points_snapshot_3_sqmuxa : OR2 - port map(A => start_snapshot_f0, B => burst_f0, Y => - \counter_points_snapshot_3_sqmuxa\); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f0_wdata_69, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(133)); - - \counter_points_snapshot_RNIACL51[14]\ : NOR3C - port map(A => un4_data_in_validlt30_8, B => - un4_data_in_validlt30_7, C => un4_data_in_validlt30_20, Y - => un4_data_in_validlt30_25); - - \counter_points_snapshot_RNO[29]\ : XA1B - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[29]\); - - \counter_points_snapshot_RNIVF66[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un4_data_in_validlt30_2); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[31]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : OR2B - port map(A => N464, B => N461, Y => N479); - - \data_out_RNO[97]\ : MX2 - port map(A => sample_f0_14, B => sample_f0_46, S => - data_shaping_R0_0, Y => \sample_f0_wdata[33]\); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f0_wdata_10, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(74)); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_96, Y => - \counter_points_snapshot_10[10]\); - - \data_out[108]\ : DFN1C0 - port map(D => \sample_f0_wdata[44]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[6]\, B => - nb_snapshot_param(6), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_92); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f0_wdata_92, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(156)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_Y : OR2 - port map(A => N644, B => N533, Y => N786); - - \data_out_RNO[106]\ : MX2 - port map(A => sample_f0_5, B => sample_f0_37, S => - data_shaping_R0, Y => \sample_f0_wdata[42]\); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[8]\, B => - nb_snapshot_param(8), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_94); - - \data_out_RNO[80]\ : NOR2B - port map(A => sample_f0_63, B => data_shaping_R0, Y => - \sample_f0_wdata[16]\); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_87, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : OA1A - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[5]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - OR2 - port map(A => N756, B => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[22]\); - - \data_out_RNO[88]\ : NOR2B - port map(A => sample_f0_55, B => data_shaping_R0_0, Y => - \sample_f0_wdata[24]\); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[12]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[24]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[24]_net_1\); - - \data_out[95]\ : DFN1C0 - port map(D => \sample_f0_wdata[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(95)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_0 : NOR2 - port map(A => N479, B => N483, Y => ADD_32x32_fast_I252_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR3A - port map(A => ADD_32x32_fast_I126_Y_1, B => N419, C => - I66_un1_Y, Y => N572); - - \data_out_RNO[110]\ : MX2 - port map(A => sample_f0_1, B => sample_f0_33, S => - data_shaping_R0, Y => \sample_f0_wdata[46]\); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => nb_snapshot_param(9), B => - \un1_data_out_valid_0_sqmuxa_2[9]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_95); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : AO1C - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_counter_points_snapshot[21]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I126_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I116_Y : OR3A - port map(A => N434, B => N431, C => N503, Y => N562); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_89, Y => - \counter_points_snapshot_10[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : OAI1 - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[26]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f0_wdata_54, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(118)); - - counter_points_snapshot_0_sqmuxa_1_0 : OR2 - port map(A => \data_out_valid_0_sqmuxa\, B => burst_f0, Y - => \counter_points_snapshot_0_sqmuxa_1_0\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR2 - port map(A => N646, B => N380, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : NOR3B - port map(A => N467, B => N464, C => I94_un1_Y, Y => - ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2 - port map(A => N642, B => N594, Y => N783); - - \counter_points_snapshot_RNIDBS75_0[31]\ : OR2B - port map(A => data_out_valid_0_sqmuxa_1, B => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_data_out_valid_0_sqmuxa_1_1[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I287_Y_0_0, B => N650, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[25]\, C => N652_i, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - \counter_points_snapshot_RNIV09P[27]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - AOI1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[9]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => N489); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f0_wdata_64, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(128)); - - \counter_points_snapshot_RNO[11]\ : XA1B - port map(A => N783, B => ADD_32x32_fast_I291_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => \sample_f0_wdata[33]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f0_wdata_74, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(138)); - - \data_out_RNO[84]\ : NOR2B - port map(A => sample_f0_59, B => data_shaping_R0_0, Y => - \sample_f0_wdata[20]\); - - \data_out[85]\ : DFN1C0 - port map(D => \sample_f0_wdata[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[3]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I18_G0N : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[13]\, Y => N434); - - \data_out_RNO[85]\ : NOR2B - port map(A => sample_f0_58, B => data_shaping_R0_0, Y => - \sample_f0_wdata[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => \sample_f0_wdata[45]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(109)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y_0 : NOR2B - port map(A => N636, B => N620, Y => ADD_32x32_fast_I259_Y_0); - - \counter_points_snapshot_RNI4EQI[18]\ : NOR3A - port map(A => un4_data_in_validlt30_10, B => - \counter_points_snapshot[19]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un4_data_in_validlt30_20); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : AO1 - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[20]\, C => I66_un1_Y, Y => - N511); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I192_Y : OR2 - port map(A => N588, B => N580, Y => N644); - - \data_out_RNO[111]\ : MX2 - port map(A => sample_f0_0, B => sample_f0_32, S => - data_shaping_R0, Y => \sample_f0_wdata[47]\); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[23]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[21]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[16]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : OR3 - port map(A => N485, B => N489, C => N556, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f0_wdata_83, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(147)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f0_wdata_87, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(151)); - - \data_out_RNO[83]\ : NOR2B - port map(A => sample_f0_60, B => data_shaping_R0_0, Y => - \sample_f0_wdata[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => \sample_f0_wdata[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(87)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f0_wdata_89, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(153)); - - \counter_points_snapshot_RNIP1RQ[7]\ : MX2 - port map(A => nb_snapshot_param(7), B => - \counter_points_snapshot[7]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I283_Y_0_0, B => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - \counter_points_snapshot_RNI17D9[14]\ : NOR2 - port map(A => \counter_points_snapshot[14]_net_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - un4_data_in_validlt30_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR2B - port map(A => ADD_32x32_fast_I259_Y_0, B => N652_i, Y => - N756); - - counter_points_snapshot_0_sqmuxa_1 : OR2 - port map(A => \data_out_valid_0_sqmuxa\, B => burst_f0, Y - => \counter_points_snapshot_0_sqmuxa_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AO1C - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[29]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : OR2B - port map(A => ADD_32x32_fast_I142_Y_0, B => N529, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I307_Y_0_0); - - \data_out_RNO[91]\ : NOR2B - port map(A => sample_f0_52, B => data_shaping_R0_0, Y => - \sample_f0_wdata[27]\); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f0_wdata_55, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : NOR3B - port map(A => N467, B => N470, C => N479, Y => - ADD_32x32_fast_I250_Y_1); - - \data_out_RNO[102]\ : MX2 - port map(A => sample_f0_9, B => sample_f0_41, S => - data_shaping_R0, Y => \sample_f0_wdata[38]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AO1A - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_data_out_valid_0_sqmuxa_1[31]\, C => N407, Y => N515); - - \counter_points_snapshot_RNILPQQ[5]\ : MX2 - port map(A => nb_snapshot_param(5), B => - \counter_points_snapshot[5]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[26]\); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => nb_snapshot_param(7), B => - \un1_data_out_valid_0_sqmuxa_2[7]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_93); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_95, Y => - \counter_points_snapshot_10[9]\); - - \counter_points_snapshot_RNI5GFH[31]\ : OR3A - port map(A => sample_f0_val_0, B => start_snapshot_f0, C - => \counter_points_snapshot[31]_net_1\, Y => - data_out_valid_0_sqmuxa_1_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I291_Y_0_0); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f0_wdata_5, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f0_wdata_65, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I112_Y : OR3A - port map(A => N434, B => N431, C => N495, Y => N558); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I251_Y_1, B => N485, C => N489, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f0_wdata_75, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[25]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[25]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I48_Y : OA1A - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_counter_points_snapshot[10]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => N491); - - \data_out_RNO[82]\ : NOR2B - port map(A => sample_f0_61, B => data_shaping_R0, Y => - \sample_f0_wdata[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : OR3A - port map(A => ADD_32x32_fast_I134_Y_0, B => N401, C => N407, - Y => N580); - - \counter_points_snapshot_RNIMTOI[10]\ : NOR3A - port map(A => un4_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un4_data_in_validlt30_18); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - AO1 - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[20]\, C => N783, Y => N780); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : AO1A - port map(A => \un1_counter_points_snapshot[30]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, C => N380, Y => - N533); - - \counter_points_snapshot_RNIJLQQ[4]\ : MX2 - port map(A => nb_snapshot_param(4), B => - \counter_points_snapshot[4]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[27]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : AOI1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[6]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N485); - - \counter_points_snapshot_RNI7G66[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un4_data_in_validlt30_4); - - un1_counter_points_snapshot_0_sqmuxa_1 : AO1B - port map(A => \counter_points_snapshot_3_sqmuxa\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => enable_f0, Y - => un1_counter_points_snapshot_0_sqmuxa_1_i); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f0_wdata_11, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(75)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I284_Y_0_0); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f0_wdata_4, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(68)); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[14]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I12_G0N : NOR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1[31]\, B => - \un1_counter_points_snapshot[19]\, Y => I66_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : AOI1B - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_counter_points_snapshot[11]\, C => - \un1_data_out_valid_0_sqmuxa_1[31]\, Y => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : NOR2A - port map(A => N564, B => N556, Y => N620); - - \counter_points_snapshot_RNINTQQ[6]\ : MX2C - port map(A => nb_snapshot_param(6), B => - \counter_points_snapshot[6]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[25]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : NOR3 - port map(A => N646, B => N380, C => N630, Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768, B => ADD_32x32_fast_I296_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[16]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : OR2 - port map(A => N566, B => N558, Y => N622); - - data_out_valid_RNO : MX2A - port map(A => un1_enable_2, B => sample_f0_val_0, S => - counter_points_snapshot_0_sqmuxa_i, Y => - data_out_valid_19); - - \data_out[100]\ : DFN1C0 - port map(D => \sample_f0_wdata[36]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I9_G0N : NOR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[22]\, Y => N407); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : NOR3 - port map(A => N642, B => N594, C => N626, Y => N762); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : OR2 - port map(A => I94_un1_Y, B => N485, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f0_wdata_13, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f0_wdata_82, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_88, Y => - \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : OR2 - port map(A => N582, B => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1C - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[13]\); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f0_wdata_94, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(158)); - - \data_out_RNO[105]\ : MX2 - port map(A => sample_f0_6, B => sample_f0_38, S => - data_shaping_R0, Y => \sample_f0_wdata[41]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I17_G0N : NOR3B - port map(A => \counter_points_snapshot[17]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1\, C => - data_out_valid_0_sqmuxa_1, Y => N431); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f0_wdata_0, CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f0_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I287_Y_0_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 is - - port( sample_f2_wdata : in std_logic_vector(95 downto 0); - data_f2_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0); - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - data_f2_out_valid : out std_logic; - I_13_20 : in std_logic; - I_9_20 : in std_logic; - I_5_20 : in std_logic; - I_38_4 : in std_logic; - I_31_5 : in std_logic; - N_4 : in std_logic; - I_45_4 : in std_logic; - I_56_4 : in std_logic; - I_52_4 : in std_logic; - I_24_4 : in std_logic; - I_20_12 : in std_logic; - enable_f2 : in std_logic; - burst_f2 : in std_logic; - start_snapshot_f2 : in std_logic; - sample_f2_val : in std_logic - ); - -end lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1; - -architecture DEF_ARCH of - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal counter_points_snapshot_0_sqmuxa_1_0, N_47_1, - un1_data_in_valid, - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, N_47_0, - ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I250_Y_3, ADD_32x32_fast_I250_Y_1, N618, - N546, I32_un1_Y, N470, N479, ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, - ADD_32x32_fast_I295_Y_0_0, - \counter_points_snapshot[15]_net_1\, - ADD_32x32_fast_I310_Y_0_0, - \counter_points_snapshot[30]_net_1\, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I253_Y_0_0, N461, N458, N485, - ADD_32x32_fast_I307_Y_0_0, - \counter_points_snapshot[27]_net_1\, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I309_Y_0_0, - \counter_points_snapshot[29]_net_1\, - ADD_32x32_fast_I300_Y_0_0, - \counter_points_snapshot[20]_net_1\, - ADD_32x32_fast_I287_Y_0_0, - \un1_counter_points_snapshot[24]\, - ADD_32x32_fast_I251_Y_2, ADD_32x32_fast_I251_Y_1, N489, - ADD_32x32_fast_I251_Y_0, ADD_32x32_fast_I305_Y_0_0, - \counter_points_snapshot[25]_net_1\, - ADD_32x32_fast_I302_Y_0_0, - \counter_points_snapshot[22]_net_1\, - ADD_32x32_fast_I294_Y_0_0, - \un1_counter_points_snapshot[17]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I306_Y_0_0, - \counter_points_snapshot[26]_net_1\, - ADD_32x32_fast_I254_Y_0, N554, ADD_32x32_fast_I301_Y_0_0, - \counter_points_snapshot[21]_net_1\, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I252_Y_1, N483, N550, - ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I293_Y_0_0, - \counter_points_snapshot[13]_net_1\, - ADD_32x32_fast_I256_Y_0, N495, N499, - ADD_32x32_fast_I255_Y_0, N556, ADD_32x32_fast_I284_Y_0_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I263_Y_0, N580, N588, N533, - ADD_32x32_fast_I283_Y_0_0, - \un1_counter_points_snapshot[28]\, - ADD_32x32_fast_I126_Y_1, - \un1_counter_points_snapshot[20]\, N419, - ADD_32x32_fast_I126_Y_0, - \un1_counter_points_snapshot[21]\, - ADD_32x32_fast_I134_Y_1, - \un1_counter_points_snapshot[22]\, N401, - ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[25]\, N404, - ADD_32x32_fast_I118_Y_1, N425, ADD_32x32_fast_I118_Y_0, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot_i[26]\, - \counter_points_snapshot_10_12_i_o2_0\, - un1_data_in_validlt30_28, un1_data_in_validlt30_20, - un1_data_in_validlt30_19, un1_data_in_validlt30_26, - un1_data_in_validlt30_27, un1_data_in_validlt30_16, - un1_data_in_validlt30_15, un1_data_in_validlt30_24, - un1_data_in_validlt30_12, un1_data_in_validlt30_11, - un1_data_in_validlt30_22, un1_data_in_validlt30_4, - un1_data_in_validlt30_3, un1_data_in_validlt30_18, - un1_data_in_validlt30_14, un1_data_in_validlt30_10, - \counter_points_snapshot[19]_net_1\, - \counter_points_snapshot[18]_net_1\, - un1_data_in_validlt30_8, - \counter_points_snapshot[14]_net_1\, - un1_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un1_data_in_validlt30_2, - \counter_points_snapshot[3]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[28]_net_1\, - \counter_points_snapshot_i_0[24]\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, N738, N771, N742, - N622, N777, \un1_data_out_valid_0_sqmuxa_2[10]\, N786, - \un1_data_out_valid_0_sqmuxa_2[9]\, N789_i, - \un1_data_out_valid_0_sqmuxa_2[5]\, N654_i, - \un1_data_out_valid_0_sqmuxa_2[4]\, N529, - \un1_data_out_valid_0_sqmuxa_2[8]\, - \un1_counter_points_snapshot[23]\, N648, - \un1_data_out_valid_0_sqmuxa_2[11]\, N783, N758, N638, - N740, N774, N620, N744, N752, N750, N630, N754, N634, - N650_i, N746, N626, N762_i, N594, N642, N764, N628, N748, - N766, N380, N646, N443, N440, N497, N_49, N_57, N_52, - N_60, counter_points_snapshot_0_sqmuxa_1, N_47, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_counter_points_snapshot_i[29]\, - \un1_data_out_valid_0_sqmuxa_2[6]\, N652, N756, N636, - N572, \un1_data_out_valid_0_sqmuxa_2[3]\, - \un1_data_out_valid_0_sqmuxa_2[7]\, N578, N515, N586, - N523, N527, N503, N570, N590, N531, N566, N582, N574, - N383, N768, N_20, counter_points_snapshot_2_sqmuxa_i, - N_21, N_25, N_26, \counter_points_snapshot_10[4]\, - counter_points_snapshot_2_sqmuxa_1, - \counter_points_snapshot_10[5]\, - \counter_points_snapshot_10[9]\, - \counter_points_snapshot_10[10]\, N_9, N_13, N_15, N_41, - N_45, \un1_counter_points_snapshot[31]\, - \counter_points_snapshot_10[0]\, N_16, - \un1_data_out_valid_0_sqmuxa_2[0]\, - \counter_points_snapshot_10[8]\, N_24, N_7, N780, - \counter_points_snapshot_10[11]\, N_27, N487, N_43, - \counter_points_snapshot_10[6]\, N_22, N422, N455, N_39, - N_37, N_33, N_29, \counter_points_snapshot_RNO[19]_net_1\, - N_35, \counter_points_snapshot_RNO[18]_net_1\, - \counter_points_snapshot_RNO[17]_net_1\, - \counter_points_snapshot_RNO[22]_net_1\, N446, N_11, N760, - \counter_points_snapshot_RNO[20]_net_1\, - \counter_points_snapshot_RNO[21]_net_1\, N_17, - \counter_points_snapshot_10[1]\, N386, - \counter_points_snapshot_10[2]\, N_18, N_31, N511, N_19, - \counter_points_snapshot_10[3]\, N_23, - \counter_points_snapshot_10[7]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - - \counter_points_snapshot_RNI58FP[1]\ : MX2 - port map(A => I_5_20, B => - \counter_points_snapshot[1]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[30]\); - - \counter_points_snapshot_RNIUTOI[10]\ : NOR3A - port map(A => un1_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un1_data_in_validlt30_18); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => N_9, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : AX1 - port map(A => N533, B => N529, C => - ADD_32x32_fast_I284_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I26_G0N : NOR3B - port map(A => \counter_points_snapshot[26]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N458); - - \data_out[110]\ : DFN1C0 - port map(D => sample_f2_wdata(46), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(110)); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => I_56_4, B => - \un1_data_out_valid_0_sqmuxa_2[10]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_26); - - \counter_points_snapshot_RNO[27]\ : XA1B - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - N_52, Y => N_37); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => N_39, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[28]_net_1\); - - \counter_points_snapshot_RNO[19]\ : XA1C - port map(A => N762_i, B => ADD_32x32_fast_I299_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[19]_net_1\); - - \counter_points_snapshot_RNI1NC9[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un1_data_in_validlt30_6); - - \data_out[91]\ : DFN1C0 - port map(D => sample_f2_wdata(27), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(91)); - - \counter_points_snapshot_RNIB9461[5]\ : MX2C - port map(A => I_24_4, B => - \counter_points_snapshot[5]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot_i[26]\); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f2_wdata(56), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(120)); - - \counter_points_snapshot_RNO[24]\ : XO1 - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - N_52, Y => N_31); - - \counter_points_snapshot_RNIU9BB2[14]\ : NOR3C - port map(A => un1_data_in_validlt30_20, B => - un1_data_in_validlt30_19, C => un1_data_in_validlt30_26, - Y => un1_data_in_validlt30_28); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : NOR3 - port map(A => N626, B => ADD_32x32_fast_I254_Y_0, C => N783, - Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : OR2 - port map(A => N586, B => N578, Y => N642); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f2_wdata(66), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => sample_f2_wdata(40), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : NOR3 - port map(A => N443, B => N446, C => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => I_20_12, B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_20); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => I_5_20, B => - \un1_data_out_valid_0_sqmuxa_2[1]\, S => N_60, Y => N_17); - - \counter_points_snapshot_RNIJDPK[19]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - \data_out[102]\ : DFN1C0 - port map(D => sample_f2_wdata(38), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3B - port map(A => N622, B => ADD_32x32_fast_I252_Y_1, C => N777, - Y => N742); - - \counter_points_snapshot_RNO[7]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_23, - Y => \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[29]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1C - port map(A => N780, B => ADD_32x32_fast_I292_Y_0_0, C => - N_52, Y => N_7); - - \counter_points_snapshot_RNIKTDU4_0[31]\ : AO1C - port map(A => start_snapshot_f2, B => un1_data_in_valid, C - => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, Y => - N_47_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : NOR2B - port map(A => N650_i, B => N634, Y => N771); - - \data_out[93]\ : DFN1C0 - port map(D => sample_f2_wdata(29), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(93)); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[4]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[21]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f2_wdata(95), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => sample_f2_wdata(41), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(105)); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f2_wdata(77), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR3 - port map(A => N443, B => N446, C => N495, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2A - port map(A => N523, B => N527, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => sample_f2_wdata(17), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(81)); - - counter_points_snapshot_10_12_i_o2 : OR2B - port map(A => \counter_points_snapshot_10_12_i_o2_0\, B => - N_60, Y => N_52); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[30]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I310_Y_0_0); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : NOR3A - port map(A => N550, B => N495, C => N499, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - OR2A - port map(A => N771, B => N425, Y => N768); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f2_wdata(50), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : NOR2 - port map(A => N578, B => N570, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : OR3 - port map(A => N419, B => N422, C => N503, Y => N566); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => N_37, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f2_wdata(79), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : NOR2B - port map(A => N590, B => N380, Y => N654_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3 - port map(A => N443, B => N440, C => N497, Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f2_wdata(48), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f2_wdata(60), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(124)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f2_wdata(70), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(134)); - - \counter_points_snapshot_RNIMGPV[3]\ : MX2 - port map(A => I_13_20, B => - \counter_points_snapshot[3]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[28]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : AO1 - port map(A => \un1_counter_points_snapshot_i[26]\, B => - \un1_counter_points_snapshot[25]\, C => N_47, Y => N523); - - \counter_points_snapshot_RNO[28]\ : XA1B - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - N_52, Y => N_39); - - \data_out[83]\ : DFN1C0 - port map(D => sample_f2_wdata(19), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(83)); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f2_wdata(58), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f2_wdata(51), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(115)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : OA1C - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => N_47, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AO1 - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[17]\, C => N_47_1, Y => - ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f2_wdata(68), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(132)); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => N_43, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[30]_net_1\); - - \data_out[96]\ : DFN1C0 - port map(D => sample_f2_wdata(32), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(96)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : NOR3 - port map(A => N628, B => ADD_32x32_fast_I255_Y_0, C => N786, - Y => N748); - - \counter_points_snapshot_RNI20DC[2]\ : NOR3A - port map(A => un1_data_in_validlt30_2, B => - \counter_points_snapshot[3]_net_1\, C => - \counter_points_snapshot[2]_net_1\, Y => - un1_data_in_validlt30_16); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - N_47_0, Y => ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f2_wdata(61), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(125)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f2_wdata(71), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(135)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_G0N : NOR3B - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N425); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : NOR2 - port map(A => ADD_32x32_fast_I253_Y_0_0, B => N752, Y => - N744); - - \counter_points_snapshot_RNICVG64[31]\ : AO1 - port map(A => un1_data_in_validlt30_28, B => - un1_data_in_validlt30_27, C => - \counter_points_snapshot[31]_net_1\, Y => - un1_data_in_valid); - - data_out_valid : DFN1C0 - port map(D => N_49, CLK => HCLK_c, CLR => HRESETn_c, Q => - data_f2_out_valid); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : OR3 - port map(A => N499, B => N503, C => N570, Y => N626); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I29_G0N : OR3B - port map(A => \counter_points_snapshot[29]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - I32_un1_Y); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f2_wdata(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f2_wdata(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[18]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : OR3C - port map(A => N638, B => N622, C => N654_i, Y => N758); - - \data_out[86]\ : DFN1C0 - port map(D => sample_f2_wdata(22), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : NOR3 - port map(A => N499, B => N503, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f2_wdata(86), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(150)); - - \counter_points_snapshot_RNINR991[6]\ : MX2C - port map(A => I_31_5, B => - \counter_points_snapshot[6]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[25]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_0, Y => ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - N_47_0, Y => ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f2_wdata(84), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(148)); - - GND_i : GND - port map(Y => \GND\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_G0N : NOR3B - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N419); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[8]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : OR2 - port map(A => N574, B => N566, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR3B - port map(A => N401, B => N523, C => N404, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f2_wdata(9), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[28]\, B => - N_47_0, Y => ADD_32x32_fast_I283_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_3 : NOR3B - port map(A => ADD_32x32_fast_I250_Y_1, B => N618, C => N546, - Y => ADD_32x32_fast_I250_Y_3); - - \data_out[92]\ : DFN1C0 - port map(D => sample_f2_wdata(28), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f2_wdata(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => sample_f2_wdata(43), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I14_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - N_47_1, Y => N422); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OR3 - port map(A => N580, B => N588, C => N533, Y => - ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_22, - Y => \counter_points_snapshot_10[6]\); - - \counter_points_snapshot_RNIQURI[26]\ : NOR3A - port map(A => un1_data_in_validlt30_14, B => - \counter_points_snapshot[27]_net_1\, C => - \counter_points_snapshot[26]_net_1\, Y => - un1_data_in_validlt30_22); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[21]\, C => N786, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => N_41, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[29]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[20]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1B - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - N_52, Y => N_33); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[20]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[22]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I302_Y_0_0); - - \counter_points_snapshot_RNIICLF1[8]\ : MX2C - port map(A => I_45_4, B => - \counter_points_snapshot[8]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[23]\); - - \counter_points_snapshot_RNIG1PK[16]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[17]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : OR2A - port map(A => N590, B => N582, Y => N646); - - \counter_points_snapshot_RNI9ND9[16]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un1_data_in_validlt30_8); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : OR2A - port map(A => N383, B => N386, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - N_47_0, Y => ADD_32x32_fast_I292_Y_0_0); - - \counter_points_snapshot_RNITFFM1[0]\ : NOR3C - port map(A => un1_data_in_validlt30_16, B => - un1_data_in_validlt30_15, C => un1_data_in_validlt30_24, - Y => un1_data_in_validlt30_27); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : OR2B - port map(A => ADD_32x32_fast_I250_Y_3, B => N771, Y => N738); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f2_wdata(90), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(154)); - - \counter_points_snapshot_RNI047N1[11]\ : MX2 - port map(A => N_4, B => \counter_points_snapshot[11]_net_1\, - S => counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - OR2 - port map(A => N764, B => N497, Y => N760); - - \data_out[82]\ : DFN1C0 - port map(D => sample_f2_wdata(18), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f2_wdata(53), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1C - port map(A => N760, B => ADD_32x32_fast_I300_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : OR2 - port map(A => N554, B => N546, Y => ADD_32x32_fast_I254_Y_0); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f2_wdata(12), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f2_wdata(88), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(152)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_1 : OA1B - port map(A => N_47_1, B => - \un1_counter_points_snapshot[14]\, C => N425, Y => - ADD_32x32_fast_I118_Y_1); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f2_wdata(85), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(149)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f2_wdata(63), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : OR2B - port map(A => N654_i, B => N638, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : NOR2 - port map(A => N652, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2 - port map(A => N588, B => N533, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f2_wdata(73), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I30_G0N : OR3B - port map(A => \counter_points_snapshot[30]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N470); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : NOR2 - port map(A => N531, B => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f2_wdata(91), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(155)); - - \counter_points_snapshot_RNIV6C9[20]\ : NOR2 - port map(A => \counter_points_snapshot[20]_net_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - un1_data_in_validlt30_10); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_21, - Y => \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1C - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[17]_net_1\); - - data_out_valid_RNO_0 : OR3A - port map(A => un1_data_in_valid, B => start_snapshot_f2, C - => burst_f2, Y => N_57); - - \data_out[90]\ : DFN1C0 - port map(D => sample_f2_wdata(26), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_0 : AO1 - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[19]\, C => N_47_1, Y => - ADD_32x32_fast_I126_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR3 - port map(A => N419, B => N422, C => N511, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR3B - port map(A => ADD_32x32_fast_I251_Y_2, B => N774, C => N620, - Y => N740); - - \counter_points_snapshot_RNO[14]\ : XA1C - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - N_52, Y => N_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_G0N : NOR3B - port map(A => \counter_points_snapshot[20]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N440); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR3A - port map(A => N401, B => N404, C => N515, Y => N578); - - \counter_points_snapshot_RNIF7E9[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un1_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[29]\, C => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - counter_points_snapshot_2_sqmuxa_0_a2 : OR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_60, - Y => counter_points_snapshot_2_sqmuxa_i); - - \data_out[99]\ : DFN1C0 - port map(D => sample_f2_wdata(35), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(99)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : OR3C - port map(A => N634, B => N618, C => N650_i, Y => N754); - - \data_out[106]\ : DFN1C0 - port map(D => sample_f2_wdata(42), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1C - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[21]_net_1\); - - \counter_points_snapshot_RNI77D9[24]\ : NOR2A - port map(A => \counter_points_snapshot_i_0[24]\, B => - \counter_points_snapshot[25]_net_1\, Y => - un1_data_in_validlt30_12); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : OR2 - port map(A => N515, B => N511, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => sample_f2_wdata(34), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(98)); - - \data_out[80]\ : DFN1C0 - port map(D => sample_f2_wdata(16), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f2_wdata(8), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : OR3B - port map(A => ADD_32x32_fast_I256_Y_0, B => N789_i, C => - N630, Y => N750); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_G0N : NOR3B - port map(A => \counter_points_snapshot[22]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N446); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AOI1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47, Y => N499); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[23]\, C => N648, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - counter_points_snapshot_2_sqmuxa_0_a2_0 : OR2A - port map(A => start_snapshot_f2, B => sample_f2_val, Y => - N_60); - - \data_out[89]\ : DFN1C0 - port map(D => sample_f2_wdata(25), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(89)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : OR2 - port map(A => ADD_32x32_fast_I263_Y_0, B => N628, Y => N764); - - counter_points_snapshot_0_sqmuxa_1_0_a2 : OR3B - port map(A => sample_f2_val, B => start_snapshot_f2, C => - burst_f2, Y => counter_points_snapshot_0_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, C => N789_i, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f2_wdata(52), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[19]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => I_9_20, B => - \un1_data_out_valid_0_sqmuxa_2[2]\, S => N_60, Y => N_18); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - N_47_0, Y => ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : NOR2 - port map(A => N594, B => N586, Y => N650_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[26]\, C => N654_i, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1B - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[18]_net_1\); - - \data_out[88]\ : DFN1C0 - port map(D => sample_f2_wdata(24), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XNOR2 - port map(A => \un1_counter_points_snapshot[31]\, B => - N_47_1, Y => \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f2_wdata(62), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => sample_f2_wdata(30), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f2_wdata(76), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f2_wdata(72), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(136)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I27_G0N : OR3B - port map(A => \counter_points_snapshot[27]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_1, Y => - N461); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I293_Y_0_0); - - \un1_data_out_valid_0_sqmuxa_1_i_0[31]\ : AOI1B - port map(A => start_snapshot_f2, B => burst_f2, C => - sample_f2_val, Y => - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\); - - \counter_points_snapshot_RNIH5PK[17]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[22]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[22]_net_1\); - - \counter_points_snapshot_RNIEUQI[14]\ : NOR3A - port map(A => un1_data_in_validlt30_8, B => - \counter_points_snapshot[15]_net_1\, C => - \counter_points_snapshot[14]_net_1\, Y => - un1_data_in_validlt30_19); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2A - port map(A => N380, B => N531, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => N_47_0, - Y => ADD_32x32_fast_I304_Y_0_0); - - \data_out[101]\ : DFN1C0 - port map(D => sample_f2_wdata(37), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(101)); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f2_wdata(93), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_20, - Y => \counter_points_snapshot_10[4]\); - - \counter_points_snapshot_RNO[30]\ : XA1C - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - N_52, Y => N_43); - - \counter_points_snapshot_RNIEPOK[14]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[14]_net_1\, Y => - \un1_counter_points_snapshot[17]\); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : - AOI1 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => N_47, Y => N497); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR3B - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N572, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : OA1B - port map(A => N_47_1, B => - \un1_counter_points_snapshot[25]\, C => N404, Y => - ADD_32x32_fast_I134_Y_0); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f2_wdata(6), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => I_24_4, B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_21); - - \data_out[84]\ : DFN1C0 - port map(D => sample_f2_wdata(20), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => sample_f2_wdata(39), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I7_G0N : OR2A - port map(A => \un1_counter_points_snapshot[24]\, B => N_47, - Y => N401); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : OA1B - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[28]\, C => N_47, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1B - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - N_52, Y => N_35); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I8_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[23]\, B => - N_47_1, Y => N404); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f2_wdata(15), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f2_wdata(80), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(144)); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0 : OR3B - port map(A => sample_f2_val, B => start_snapshot_f2, C => - burst_f2, Y => counter_points_snapshot_0_sqmuxa_1_0); - - \counter_points_snapshot_RNI1BRI1[9]\ : MX2C - port map(A => I_52_4, B => - \counter_points_snapshot[9]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[22]\); - - \counter_points_snapshot_RNO[8]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_24, - Y => \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => sample_f2_wdata(47), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2A - port map(A => \un1_counter_points_snapshot[31]\, B => - N_47_1, Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f2_wdata(78), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f2_wdata(14), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - N_52, Y => N_29); - - \counter_points_snapshot_RNIKTDU4[31]\ : AO1C - port map(A => start_snapshot_f2, B => un1_data_in_valid, C - => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, Y => - N_47_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : OR2 - port map(A => N580, B => N572, Y => N636); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_1 : OA1 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, C => N401, Y => - ADD_32x32_fast_I134_Y_1); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => I_13_20, B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_19); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => N_35, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[25]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : NOR3B - port map(A => N483, B => N550, C => N479, Y => - ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I1_G0N : OR2A - port map(A => \un1_counter_points_snapshot[30]\, B => N_47, - Y => N383); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f2_wdata(57), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : AO1D - port map(A => \un1_counter_points_snapshot[15]\, B => N_47, - C => N425, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_16, - Y => \counter_points_snapshot_10[0]\); - - \counter_points_snapshot_RNI4IFC1[7]\ : MX2 - port map(A => I_38_4, B => - \counter_points_snapshot[7]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[24]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f2_wdata(67), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f2_wdata(49), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(113)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f2_wdata(81), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(145)); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f2_wdata(2), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[1]_net_1\); - - \counter_points_snapshot_RNO[31]\ : XA1B - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - N_52, Y => N_45); - - \counter_points_snapshot_RNO_0[0]\ : MX2B - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_16); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N771, B => ADD_32x32_fast_I295_Y_0_0, C => - N_52, Y => N_13); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f2_wdata(59), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(123)); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f2_wdata(69), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : NOR3B - port map(A => \counter_points_snapshot[21]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N443); - - \counter_points_snapshot_RNO[29]\ : XA1C - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - N_52, Y => N_41); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => N_45, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : AO1C - port map(A => N_47_1, B => \un1_counter_points_snapshot[3]\, - C => N461, Y => N479); - - \counter_points_snapshot_RNI0RU21[4]\ : MX2 - port map(A => I_20_12, B => - \counter_points_snapshot[4]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[27]\); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f2_wdata(10), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(74)); - - \counter_points_snapshot_RNO[10]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_26, - Y => \counter_points_snapshot_10[10]\); - - \counter_points_snapshot_RNI7G66[6]\ : NOR2 - port map(A => \counter_points_snapshot[6]_net_1\, B => - \counter_points_snapshot[7]_net_1\, Y => - un1_data_in_validlt30_3); - - \data_out[108]\ : DFN1C0 - port map(D => sample_f2_wdata(44), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => I_31_5, B => - \un1_data_out_valid_0_sqmuxa_2[6]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_22); - - \counter_points_snapshot_RNI3NC9[23]\ : NOR2 - port map(A => \counter_points_snapshot[22]_net_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - un1_data_in_validlt30_11); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f2_wdata(92), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(156)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_Y : OR3 - port map(A => N580, B => N588, C => N533, Y => N786); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => I_45_4, B => - \un1_data_out_valid_0_sqmuxa_2[8]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_24); - - \counter_points_snapshot_RNO[1]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_17, - Y => \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_0, - Y => ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I25_G0N : NOR3B - port map(A => \counter_points_snapshot[25]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N455); - - \counter_points_snapshot_RNIGU5V[6]\ : NOR3C - port map(A => un1_data_in_validlt30_4, B => - un1_data_in_validlt30_3, C => un1_data_in_validlt30_18, Y - => un1_data_in_validlt30_24); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : NOR2 - port map(A => N458, B => N455, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - OR2 - port map(A => N756, B => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[22]_net_1\); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => N_7, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1P0 - port map(D => N_31, CLK => HCLK_c, PRE => HRESETn_c, Q => - \counter_points_snapshot_i_0[24]\); - - \counter_points_snapshot_RNIKTDU4_1[31]\ : AO1C - port map(A => start_snapshot_f2, B => un1_data_in_valid, C - => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, Y => - N_47); - - \data_out[95]\ : DFN1C0 - port map(D => sample_f2_wdata(31), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(95)); - - \counter_points_snapshot_RNIJ9PK[28]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I196_Y_0_o2 : - OR2B - port map(A => N650_i, B => N401, Y => N648); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR2B - port map(A => ADD_32x32_fast_I126_Y_1, B => - ADD_32x32_fast_I126_Y_0, Y => N572); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => I_52_4, B => - \un1_data_out_valid_0_sqmuxa_2[9]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_25); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : OA1C - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N419, Y => ADD_32x32_fast_I126_Y_1); - - \counter_points_snapshot_RNO[3]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_19, - Y => \counter_points_snapshot_10[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot_i[26]\, C => N_47_1, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f2_wdata(54), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(118)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : NOR2A - port map(A => N380, B => N646, Y => N789_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[26]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I306_Y_0_0); - - \counter_points_snapshot_RNICEQI[18]\ : NOR3A - port map(A => un1_data_in_validlt30_10, B => - \counter_points_snapshot[19]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un1_data_in_validlt30_20); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : NOR3B - port map(A => N461, B => ADD_32x32_fast_I251_Y_0, C => N458, - Y => ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2 - port map(A => N642, B => N594, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I287_Y_0_0, B => N650_i, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[25]\, C => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - AO1D - port map(A => \un1_counter_points_snapshot[8]\, B => N_47, - C => N446, Y => N489); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[20]\, C => N783, Y => - \un1_data_out_valid_0_sqmuxa_2[11]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I100_Y : OR2A - port map(A => N483, B => N487, Y => N546); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f2_wdata(64), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(128)); - - \counter_points_snapshot_RNO[11]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_27, - Y => \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => sample_f2_wdata(33), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f2_wdata(74), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(138)); - - \counter_points_snapshot_RNII9PK[18]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - \counter_points_snapshot_RNIDAKS[2]\ : MX2C - port map(A => I_9_20, B => - \counter_points_snapshot[2]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot_i[29]\); - - \counter_points_snapshot_RNIU9AM[0]\ : MX2A - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[31]\); - - \data_out[85]\ : DFN1C0 - port map(D => sample_f2_wdata(21), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[3]_net_1\); - - \counter_points_snapshot_RNIVV6N1[10]\ : MX2C - port map(A => I_56_4, B => - \counter_points_snapshot[10]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => sample_f2_wdata(45), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(109)); - - \counter_points_snapshot_RNI4TL51[23]\ : NOR3C - port map(A => un1_data_in_validlt30_12, B => - un1_data_in_validlt30_11, C => un1_data_in_validlt30_22, - Y => un1_data_in_validlt30_26); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : OA1C - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[20]\, C => N_47, Y => N511); - - \counter_points_snapshot_RNIBHSA[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[30]_net_1\, Y => - un1_data_in_validlt30_15); - - \counter_points_snapshot_RNIBG66[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un1_data_in_validlt30_4); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => N_29, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[21]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : OR3 - port map(A => N485, B => N489, C => N556, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f2_wdata(83), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(147)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f2_wdata(87), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(151)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - N_47_0, Y => ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => N_47_0, - Y => ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => sample_f2_wdata(23), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(87)); - - counter_points_snapshot_10_12_i_o2_0 : NOR2A - port map(A => enable_f2, B => burst_f2, Y => - \counter_points_snapshot_10_12_i_o2_0\); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f2_wdata(89), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(153)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I283_Y_0_0, B => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR3 - port map(A => N636, B => N620, C => N652, Y => N756); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : OA1C - port map(A => \un1_counter_points_snapshot[28]\, B => N_47, - C => N386, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : OR2B - port map(A => ADD_32x32_fast_I142_Y_0, B => N529, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[27]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I307_Y_0_0); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f2_wdata(55), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : NOR3B - port map(A => I32_un1_Y, B => N470, C => N479, Y => - ADD_32x32_fast_I250_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AOI1 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[21]\, C => N_47, Y => N515); - - \counter_points_snapshot_RNIELOK[23]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => I_38_4, B => - \un1_data_out_valid_0_sqmuxa_2[7]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_23); - - \counter_points_snapshot_RNO[9]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_25, - Y => \counter_points_snapshot_10[9]\); - - \counter_points_snapshot_RNIFPOK[24]\ : NOR2A - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot_i_0[24]\, Y => - \un1_counter_points_snapshot[7]\); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f2_wdata(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f2_wdata(65), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I251_Y_1, B => N485, C => N489, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f2_wdata(75), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => N_33, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[25]_net_1\); - - counter_points_snapshot_2_sqmuxa_0_a2_1 : OR2A - port map(A => enable_f2, B => burst_f2, Y => - counter_points_snapshot_2_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : OR2B - port map(A => ADD_32x32_fast_I134_Y_1, B => - ADD_32x32_fast_I134_Y_0, Y => N580); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - OA1C - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N783, Y => N780); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : OR2B - port map(A => N383, B => N380, Y => N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : AO1A - port map(A => N_47, B => \un1_counter_points_snapshot[7]\, - C => N455, Y => N485); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f2_wdata(11), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(75)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => - N_47_0, Y => ADD_32x32_fast_I284_Y_0_0); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f2_wdata(4), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(68)); - - \counter_points_snapshot_RNICHOK[12]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - \counter_points_snapshot_RNI3G66[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un1_data_in_validlt30_2); - - \counter_points_snapshot_RNO_0[11]\ : MX2C - port map(A => N_4, B => \un1_data_out_valid_0_sqmuxa_2[11]\, - S => counter_points_snapshot_2_sqmuxa_i, Y => N_27); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_0 : OA1A - port map(A => \un1_counter_points_snapshot[3]\, B => N_47_0, - C => I32_un1_Y, Y => ADD_32x32_fast_I251_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : AO1D - port map(A => \un1_counter_points_snapshot[12]\, B => N_47, - C => N440, Y => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OR3B - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N556, Y => N620); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : NOR3A - port map(A => N380, B => N646, C => N630, Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768, B => ADD_32x32_fast_I296_Y_0_0, C => - N_52, Y => N_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : NOR3 - port map(A => N495, B => N499, C => N566, Y => N622); - - data_out_valid_RNO : NOR3C - port map(A => sample_f2_val, B => enable_f2, C => N_57, Y - => N_49); - - \data_out[100]\ : DFN1C0 - port map(D => sample_f2_wdata(36), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : NOR3 - port map(A => N626, B => N594, C => N642, Y => N762_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : - OR3A - port map(A => N461, B => N458, C => N485, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f2_wdata(13), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f2_wdata(82), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR2 - port map(A => counter_points_snapshot_2_sqmuxa_1, B => N_18, - Y => \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : NOR2 - port map(A => N582, B => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1B - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - N_52, Y => N_9); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f2_wdata(94), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(158)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I2_G0N : NOR2 - port map(A => \un1_counter_points_snapshot_i[29]\, B => - N_47, Y => N386); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f2_wdata(0), CLK => HCLK_c, CLR => - HRESETn_c, Q => data_f2_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[24]\, B => - N_47_0, Y => ADD_32x32_fast_I287_Y_0_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(2 to 2); - status_full : out std_logic_vector(2 to 2); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - update_and_sel_3 : in std_logic_vector(5 downto 4); - addr_data_f2 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(2 to 2); - addr_data_vector_62 : out std_logic; - addr_data_vector_61 : out std_logic; - addr_data_vector_5 : in std_logic; - addr_data_vector_4 : in std_logic; - addr_data_vector_3 : in std_logic; - addr_data_vector_0 : in std_logic; - addr_data_vector_12 : in std_logic; - addr_data_vector_11 : in std_logic; - addr_data_vector_9 : in std_logic; - addr_data_vector_7 : in std_logic; - addr_data_vector_6 : in std_logic; - addr_data_vector_26 : in std_logic; - addr_data_vector_24 : in std_logic; - addr_data_vector_22 : in std_logic; - addr_data_vector_28 : in std_logic; - addr_data_vector_66 : out std_logic; - addr_data_vector_65 : out std_logic; - addr_data_vector_91 : out std_logic; - addr_data_vector_89 : out std_logic; - addr_data_vector_87 : out std_logic; - addr_data_vector_63 : out std_logic; - addr_data_vector_72 : out std_logic; - addr_data_vector_74 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_78 : out std_logic; - addr_data_vector_81 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_84 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_83 : out std_logic; - N_1329 : out std_logic; - N_1328 : out std_logic; - N_1327 : out std_logic; - N_1324 : out std_logic; - N_1322 : out std_logic; - N_1321 : out std_logic; - N_1319 : out std_logic; - N_1317 : out std_logic; - N_1316 : out std_logic; - N_1308 : out std_logic; - N_1306 : out std_logic; - N_1304 : out std_logic; - N_1296 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, m41_m6_0_a2_7, m41_m6_0_a2_2, - m41_m6_0_a2_1, m41_m6_0_a2_6, m41_m6_0_a2_4, - m26_m6_0_a2_6, \addr_data_vector[76]\, m26_m6_0_a2_4, - m26_m6_0_a2_5, \addr_data_vector[73]\, - \addr_data_vector[72]\, m26_m6_0_a2_2, - \addr_data_vector[71]\, \addr_data_vector[79]\, - \addr_data_vector[78]\, \addr_data_vector[74]\, - \un1_state_12_3_0[4]\, \update_r_i[0]\, - \update_r[1]_net_1\, \state_ns_i_0[3]\, N_131, - \un1_state_12[4]\, \un1_state_12_2[4]\, \un1_address[6]\, - address_0_sqmuxa, \addr_data_vector[70]\, N_5_0, N_116, - N_129, \state[1]_net_1\, \state_ns[0]\, N_125, N_124, - N_110, \state[3]_net_1\, \state[4]_net_1\, N_130, - \state[2]_net_1\, state7, un3_update_r, N_27_0_i_0, - N_13_0, N_15_0_i_0, N_16_0, N_17_0_i_0, N_19_0, - N_20_0_i_0, \addr_data_vector[75]\, N_22_0_i_0, N_23_0, - N_26_0_i_0, N_25_0, N_28_0_i_0, \addr_data_vector[80]\, - N_30_0_i_0, \addr_data_vector[81]\, N_31_0, - \un1_address[19]\, \addr_data_vector[82]\, - \addr_data_vector[83]\, N_34_0, \un1_address[20]\, - \addr_data_vector[84]\, N_37_0, \addr_data_vector[85]\, - \un1_address[23]\, \addr_data_vector[86]\, - \addr_data_vector[87]\, N_40_i_0, N_41, N_43, - \addr_data_vector[89]\, N_45, \addr_data_vector[91]\, - N_47, \addr_data_vector[93]\, N_49_i_0, - \addr_data_vector[95]\, N_50_i_0, \addr_data_vector[66]\, - \addr_data_vector[67]\, N_51_i_0, N_69, N_52_i_0, - \addr_data_vector[68]\, N_1_i_0, N_54_0_i_0, N_55_0_i_0, - \addr_data_vector[77]\, \un1_address[18]\, - \un1_address[21]\, \un1_address[22]\, \un1_address[24]\, - \addr_data_vector[88]\, \un1_address[25]\, - \un1_address[26]\, \addr_data_vector[90]\, - \un1_address[27]\, \un1_address[28]\, - \addr_data_vector[92]\, \un1_address[29]\, - \un1_address[30]\, \addr_data_vector[94]\, - \addr_data_vector[69]\, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[15]\, \address_7[16]\, - \address_7[17]\, \address_7[18]\, \address_7[19]\, - \state[0]_net_1\, \address_7[20]\, \address_7[21]\, - \address_7[22]\, \address_7[23]\, \address_7[24]\, - \address_7[25]\, \address_7[26]\, \address_7[27]\, - \address_7[28]\, \address_7[29]\, \address_7[30]\, - \address_7[31]\, N_56_0_i_0, un1_state_9, \nb_send_5[0]\, - \nb_send_5[1]\, \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, N_126, N_113, \state_ns[2]\, - un1_state_11, \address_7[14]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_66 <= \addr_data_vector[69]\; - addr_data_vector_65 <= \addr_data_vector[68]\; - addr_data_vector_91 <= \addr_data_vector[94]\; - addr_data_vector_89 <= \addr_data_vector[92]\; - addr_data_vector_87 <= \addr_data_vector[90]\; - addr_data_vector_63 <= \addr_data_vector[66]\; - addr_data_vector_72 <= \addr_data_vector[75]\; - addr_data_vector_74 <= \addr_data_vector[77]\; - addr_data_vector_79 <= \addr_data_vector[82]\; - addr_data_vector_78 <= \addr_data_vector[81]\; - addr_data_vector_81 <= \addr_data_vector[84]\; - addr_data_vector_80 <= \addr_data_vector[83]\; - addr_data_vector_84 <= \addr_data_vector[87]\; - addr_data_vector_85 <= \addr_data_vector[88]\; - addr_data_vector_77 <= \addr_data_vector[80]\; - addr_data_vector_82 <= \addr_data_vector[85]\; - addr_data_vector_83 <= \addr_data_vector[86]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[80]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[74]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[94]\); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f2(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : XOR2 - port map(A => N_43, B => \addr_data_vector[90]\, Y => - \un1_address[26]\); - - \address_RNILG94[25]\ : MX2C - port map(A => addr_data_vector_22, B => - \addr_data_vector[89]\, S => sel_data_1(1), Y => N_1304); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[90]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[84]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \address_RNI5894[10]\ : MX2C - port map(A => addr_data_vector_7, B => - \addr_data_vector[74]\, S => sel_data_1(1), Y => N_1317); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1C - port map(A => \addr_data_vector[68]\, B => N_69, C => - \addr_data_vector[69]\, Y => N_52_i_0); - - un1_address_m26_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[77]\, B => - \addr_data_vector[76]\, C => m26_m6_0_a2_4, Y => - m26_m6_0_a2_6); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[76]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - un1_address_m26_m6_0_a2 : OR3B - port map(A => m26_m6_0_a2_6, B => m26_m6_0_a2_5, C => - N_13_0, Y => N_27_0_i_0); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f2(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - un1_address_m41_m6_0_a2_7 : NOR3C - port map(A => m41_m6_0_a2_2, B => m41_m6_0_a2_1, C => - m41_m6_0_a2_6, Y => m41_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XNOR2 - port map(A => N_19_0, B => \addr_data_vector[75]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[86]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f2(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[66]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f2(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f2(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_110, Q => status_full_err(2)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : OR3B - port map(A => \addr_data_vector[73]\, B => - \addr_data_vector[74]\, C => N_16_0, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - \address_RNIPNMA[3]\ : MX2C - port map(A => addr_data_vector_0, B => - \addr_data_vector[67]\, S => sel_data_1(1), Y => N_1324); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f2(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[69]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[79]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[77]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[83]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[89]\); - - \address_RNIT9IB[7]\ : MX2C - port map(A => addr_data_vector_4, B => - \addr_data_vector[71]\, S => sel_data(1), Y => N_1328); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \state_RNIV5SU8[3]\ : OR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa); - - \address_RNIR1IB[6]\ : MX2C - port map(A => addr_data_vector_3, B => - \addr_data_vector[70]\, S => sel_data(1), Y => N_1327); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[87]\); - - un1_address_m26_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[73]\, B => - \addr_data_vector[72]\, C => m26_m6_0_a2_2, Y => - m26_m6_0_a2_5); - - \state_RNISHSP8_0[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => state7, Y => N_126); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[71]\, C => - \addr_data_vector[72]\, Y => N_15_0_i_0); - - un1_address_m29 : AX1 - port map(A => N_27_0_i_0, B => \addr_data_vector[80]\, C - => \addr_data_vector[81]\, Y => N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[93]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[82]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f2(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f2(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f2(0), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - addr_data_vector_61); - - \address_RNITG94[29]\ : MX2C - port map(A => addr_data_vector_26, B => - \addr_data_vector[93]\, S => sel_data_1(1), Y => N_1308); - - \state_RNIV5SU8_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - GND_i : GND - port map(Y => \GND\); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f2(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[68]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[92]\); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3B - port map(A => N_131, B => N_129, C => \state[3]_net_1\, Y - => N_125); - - \address_RNI9894[12]\ : MX2C - port map(A => addr_data_vector_9, B => - \addr_data_vector[76]\, S => sel_data_1(1), Y => N_1319); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR3 - port map(A => address_0_sqmuxa, B => \addr_data_vector[70]\, - C => N_5_0, Y => \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f2(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - un1_address_m24 : OR3B - port map(A => \addr_data_vector[77]\, B => - \addr_data_vector[78]\, C => N_23_0, Y => N_25_0); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[7]_net_1\); - - \update_r_RNIV5SU8[0]\ : NOR2 - port map(A => \un1_state_12_3_0[4]\, B => - \un1_state_12_2[4]\, Y => \un1_state_12[4]\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f2(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[78]\); - - \state_RNO[1]\ : OA1C - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f2(14), S => - \state[0]_net_1\, Y => \address_7[14]\); - - \address_RNIPG94[27]\ : MX2C - port map(A => addr_data_vector_24, B => - \addr_data_vector[91]\, S => sel_data_1(1), Y => N_1306); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[88]\); - - un1_address_m27 : XNOR2 - port map(A => N_27_0_i_0, B => \addr_data_vector[80]\, Y - => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : AX1 - port map(A => N_27_0_i_0, B => m41_m6_0_a2_7, C => - \addr_data_vector[89]\, Y => \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - un1_address_m30 : OR3B - port map(A => \addr_data_vector[80]\, B => - \addr_data_vector[81]\, C => N_27_0_i_0, Y => N_31_0); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[73]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3C - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[72]\); - - un1_address_m50 : XOR2 - port map(A => N_69, B => \addr_data_vector[68]\, Y => - N_51_i_0); - - un1_address_m39 : XOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[66]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : NOR2A - port map(A => update_and_sel_3(4), B => update_and_sel_3(5), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f2(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => status_full_ack(2), B => N_130, C => N_126, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f2(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f2(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1 - port map(A => N_37_0, B => \addr_data_vector[86]\, C => - \addr_data_vector[87]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa, C => - \addr_data_vector[70]\, Y => N_13_0); - - un1_address_m59 : XNOR2 - port map(A => N_41, B => \addr_data_vector[88]\, Y => - \un1_address[24]\); - - \update_r[0]\ : DFN1P0 - port map(D => update_and_sel_3(4), CLK => HCLK_c, PRE => - HRESETn_c, Q => \update_r_i[0]\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f2(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f2(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[71]\, B => - \addr_data_vector[72]\, C => N_13_0, Y => N_16_0); - - un1_address_m58 : XNOR2 - port map(A => N_37_0, B => \addr_data_vector[86]\, Y => - \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - \address_RNID894[14]\ : MX2C - port map(A => addr_data_vector_11, B => - \addr_data_vector[78]\, S => sel_data_1(1), Y => N_1321); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - un1_address_m41_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[86]\, B => - \addr_data_vector[85]\, C => m41_m6_0_a2_4, Y => - m41_m6_0_a2_6); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f2(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[67]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : AX1C - port map(A => \addr_data_vector[92]\, B => N_45, C => - \addr_data_vector[93]\, Y => \un1_address[29]\); - - \address_RNI58OA[9]\ : MX2C - port map(A => addr_data_vector_6, B => - \addr_data_vector[73]\, S => sel_data_1(1), Y => N_1316); - - un1_address_m34 : XNOR2 - port map(A => N_34_0, B => \addr_data_vector[84]\, Y => - \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f2(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - un1_address_m26_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[74]\, B => - \addr_data_vector[75]\, Y => m26_m6_0_a2_2); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(2), B => N_131, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : XNOR2 - port map(A => N_23_0, B => \addr_data_vector[77]\, Y => - N_55_0_i_0); - - un1_address_m22 : OR3B - port map(A => \addr_data_vector[75]\, B => - \addr_data_vector[76]\, C => N_19_0, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[71]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - \address_RNIF894[15]\ : MX2C - port map(A => addr_data_vector_12, B => - \addr_data_vector[79]\, S => sel_data_1(1), Y => N_1322); - - un1_address_m25 : XNOR2 - port map(A => N_25_0, B => \addr_data_vector[79]\, Y => - N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[3]_net_1\); - - \update_r_RNI3KV4[0]\ : OR2B - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => un3_update_r); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_3(5), CLK => HCLK_c, CLR => - HRESETn_c, Q => \update_r[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - \update_r_RNI3KV4_0[0]\ : OR2 - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => \un1_state_12_3_0[4]\); - - un1_address_m40 : OR3B - port map(A => \addr_data_vector[86]\, B => - \addr_data_vector[87]\, C => N_37_0, Y => N_41); - - \address_RNIIO94[31]\ : MX2C - port map(A => addr_data_vector_28, B => - \addr_data_vector[95]\, S => sel_data_0(1), Y => N_1296); - - un1_address_m57 : AX1 - port map(A => N_34_0, B => \addr_data_vector[84]\, C => - \addr_data_vector[85]\, Y => \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f2(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1C - port map(A => \addr_data_vector[66]\, B => - \un1_state_12[4]\, C => \addr_data_vector[67]\, Y => - N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[73]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f2(18), S - => \state_0[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f2(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[94]\, B => N_47, C => - \addr_data_vector[95]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[70]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - status_full_err_RNO : OR3 - port map(A => \state[3]_net_1\, B => \state[4]_net_1\, C - => N_130, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f2(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un1_address_m36 : OR3B - port map(A => \addr_data_vector[84]\, B => - \addr_data_vector[85]\, C => N_34_0, Y => N_37_0); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[75]\); - - \state_RNIHABE[1]\ : NOR2A - port map(A => status_full_ack(2), B => N_131, Y => N_118); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[95]\); - - \state_RNISHSP8[3]\ : OR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : XNOR2 - port map(A => N_31_0, B => \addr_data_vector[82]\, Y => - \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f2(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - un1_address_m44 : NOR3C - port map(A => \addr_data_vector[90]\, B => N_43, C => - \addr_data_vector[91]\, Y => N_45); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f2(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f2(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[85]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - un1_address_m62 : AX1C - port map(A => \addr_data_vector[90]\, B => N_43, C => - \addr_data_vector[91]\, Y => \un1_address[27]\); - - un1_address_m32 : AX1 - port map(A => N_31_0, B => \addr_data_vector[82]\, C => - \addr_data_vector[83]\, Y => \un1_address[19]\); - - un1_address_m12_e : OR3C - port map(A => \addr_data_vector[68]\, B => N_69, C => - \addr_data_vector[69]\, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[81]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[94]\, Y => - \un1_address[30]\); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[71]\, Y => - N_1_i_0); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[91]\); - - \state_RNO[3]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : AX1 - port map(A => N_19_0, B => \addr_data_vector[75]\, C => - \addr_data_vector[76]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : AX1 - port map(A => N_23_0, B => \addr_data_vector[77]\, C => - \addr_data_vector[78]\, Y => N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f2(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : NOR3C - port map(A => \addr_data_vector[66]\, B => - \un1_state_12[4]\, C => \addr_data_vector[67]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f2(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : OR2 - port map(A => \state[2]_net_1\, B => N_126, Y => - un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f2(1), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - addr_data_vector_62); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_11, Q => status_full(2)); - - un1_address_m63 : XOR2 - port map(A => N_45, B => \addr_data_vector[92]\, Y => - \un1_address[28]\); - - un1_address_m33 : OR3B - port map(A => \addr_data_vector[82]\, B => - \addr_data_vector[83]\, C => N_31_0, Y => N_34_0); - - un1_address_m26_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[71]\, B => - \addr_data_vector[79]\, C => \addr_data_vector[78]\, Y - => m26_m6_0_a2_4); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un1_address_m41_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[83]\, B => - \addr_data_vector[84]\, Y => m41_m6_0_a2_2); - - un1_address_m41_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[81]\, B => - \addr_data_vector[82]\, Y => m41_m6_0_a2_1); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f2(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR3C - port map(A => \addr_data_vector[92]\, B => N_45, C => - \addr_data_vector[93]\, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : AX1 - port map(A => N_16_0, B => \addr_data_vector[73]\, C => - \addr_data_vector[74]\, Y => N_54_0_i_0); - - \state_RNIVJCD[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - un1_address_m41_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[80]\, B => - \addr_data_vector[88]\, C => \addr_data_vector[87]\, Y - => m41_m6_0_a2_4); - - \state_RNIH9F11[2]\ : NOR2B - port map(A => \state[2]_net_1\, B => N_129, Y => N_130); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[3]_net_1\, C - => \state[2]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f2(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - un1_address_m42 : NOR3B - port map(A => m41_m6_0_a2_7, B => \addr_data_vector[89]\, C - => N_27_0_i_0, Y => N_43); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - \address_RNIVHIB[8]\ : MX2C - port map(A => addr_data_vector_5, B => - \addr_data_vector[72]\, S => sel_data(1), Y => N_1329); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(0 to 0); - status_full : out std_logic_vector(0 to 0); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - update_and_sel_7 : in std_logic_vector(1 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(0 to 0); - addr_data_vector_69 : in std_logic; - addr_data_vector_68 : in std_logic; - addr_data_vector_66 : in std_logic; - addr_data_vector_77 : in std_logic; - addr_data_vector_75 : in std_logic; - addr_data_vector_86 : in std_logic; - addr_data_vector_85 : in std_logic; - addr_data_vector_84 : in std_logic; - addr_data_vector_83 : in std_logic; - addr_data_vector_82 : in std_logic; - addr_data_vector_81 : in std_logic; - addr_data_vector_80 : in std_logic; - addr_data_vector_92 : in std_logic; - addr_data_vector_90 : in std_logic; - addr_data_vector_88 : in std_logic; - addr_data_vector_87 : in std_logic; - addr_data_vector_94 : in std_logic; - addr_data_vector_65 : in std_logic; - addr_data_vector_64 : in std_logic; - addr_data_vector_3 : out std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_27 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_25 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_8 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_12 : out std_logic; - N_1326 : out std_logic; - N_1325 : out std_logic; - N_1323 : out std_logic; - N_1320 : out std_logic; - N_1318 : out std_logic; - N_1315 : out std_logic; - N_1314 : out std_logic; - N_1313 : out std_logic; - N_1312 : out std_logic; - N_1311 : out std_logic; - N_1310 : out std_logic; - N_1309 : out std_logic; - N_1307 : out std_logic; - N_1305 : out std_logic; - N_1303 : out std_logic; - N_1302 : out std_logic; - N_1295 : out std_logic; - N_1280 : out std_logic; - N_1279 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, \state_RNIBABE[1]_net_1\, N_38, - \nb_send[1]_net_1\, \nb_send[0]_net_1\, N_30, - \nb_send[3]_net_1\, \DWACT_FINC_E[0]\, N_7, - \nb_send[8]_net_1\, \DWACT_FINC_E[4]\, m40_m6_0_a2_7, - m40_m6_0_a2_6, m37_m6_0_a2_4_i, m40_m6_0_a2_3, - m40_m6_0_a2_2, m40_m6_0_a2_4, \addr_data_vector[13]\, - \addr_data_vector[23]\, m40_m6_0_a2_1, - \addr_data_vector[11]\, m23_m7_i_5, m23_m7_i_2, - m23_m7_i_1, m23_m7_i_3, \addr_data_vector[7]\, - \addr_data_vector[12]\, \addr_data_vector[10]\, - \addr_data_vector[8]\, \addr_data_vector[9]\, - ADD_32x32_fast_I164_Y_0_0, address_0_sqmuxa, - \un1_state_12_3_0[4]\, \update_r_i[0]\, - \update_r[1]_net_1\, address_0_sqmuxa_0, \state[3]_net_1\, - un3_update_r, un1_state_5_i_0, \state[4]_net_1\, - \state_ns_i_0[3]\, N_85, address_7_31_m6_e_3, - \addr_data_vector[30]\, address_7_31_m6_e_1, - address_7_31_m6_e_2, \addr_data_vector[28]\, - \addr_data_vector[26]\, m37_m6_0_a2_4_6, - \addr_data_vector[20]\, \addr_data_vector[19]\, - m37_m6_0_a2_4_4, m37_m6_0_a2_4_5, \addr_data_vector[16]\, - m37_m6_0_a2_4_2, \addr_data_vector[22]\, - \addr_data_vector[21]\, \addr_data_vector[17]\, - \addr_data_vector[18]\, \un1_address[6]\, N_5_0, - \state_RNO_0[1]_net_1\, N_83_i, \state[1]_net_1\, - \state_ns[0]\, N_79, N_78, \un1_state_12_2[4]\, N_64, - N_84, \state[2]_net_1\, state7, \address_RNO_2_0[31]\, - m23_m7_i, m23_N_10, m23_m7_i_a5, \addr_data_vector[6]\, - \address_7[31]\, \address_RNO_0_0[31]\, - \address_RNO_1_0[31]\, N_42, \addr_data_vector[31]\, N_2, - \addr_data_vector[2]\, N_4_0, \addr_data_vector[4]\, - N_15_0_i_0, N_13_0, N_16_0, N_17_0_i_0, N_19_0, - N_20_0_i_0, N_21_0, N_22_0_i_0, N_26_0_i_0, - \addr_data_vector[14]\, \addr_data_vector[15]\, N_27_0, - N_28_0_i_0, N_30_0_i_0, N_31_0, \un1_address[19]\, N_34_0, - \un1_address[20]\, N_36_0, \un1_address[23]\, N_40_i_0, - \addr_data_vector[24]\, N_44, \addr_data_vector[25]\, - N_46, \addr_data_vector[27]\, N_50_i_0, - \addr_data_vector[3]\, N_51_i_0, N_52_i_0, - \addr_data_vector[5]\, N_1_i_0, N_54_0_i_0, N_55_0_i_0, - \un1_address[18]\, \un1_address[21]\, \un1_address[22]\, - \un1_address[24]\, \un1_address[25]\, \un1_address[26]\, - \un1_address[27]\, \un1_address[28]\, \un1_address[29]\, - \addr_data_vector[29]\, \un1_address[30]\, \address_7[2]\, - \address_7[3]\, \address_7[4]\, \address_7[5]\, - \address_7[6]\, \address_7[7]\, \address_7[8]\, - \address_7[9]\, \address_7[10]\, \address_7[11]\, - \address_7[12]\, \address_7[13]\, \address_7[15]\, - \address_7[16]\, \address_7[17]\, \state[0]_net_1\, - \address_7[18]\, \address_7[19]\, \address_7[20]\, - \address_7[21]\, \address_7[22]\, \address_7[23]\, - \address_7[24]\, \address_7[25]\, \address_7[26]\, - \address_7[27]\, \address_7[28]\, \address_7[29]\, - \address_7[30]\, N_56_0_i_0, un1_state_9, \nb_send_5[0]\, - \nb_send_5[1]\, \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, N_80, \state_RNO_1[3]\, - \state_ns[2]\, un1_state_11, \address_7[14]\, - \addr_data_vector[0]\, \addr_data_vector[1]\, - \nb_send[2]_net_1\, \nb_send[4]_net_1\, - \nb_send[5]_net_1\, \nb_send[6]_net_1\, - \nb_send[7]_net_1\, \nb_send[9]_net_1\, - \nb_send[10]_net_1\, N_4, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[3]\, N_12, N_17, N_22, \DWACT_FINC_E[1]\, - N_27, N_35, \DWACT_COMP0_E[1]\, \DWACT_COMP0_E[2]\, - \DWACT_COMP0_E[0]\, \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_3 <= \addr_data_vector[3]\; - addr_data_vector_31 <= \addr_data_vector[31]\; - addr_data_vector_14 <= \addr_data_vector[14]\; - addr_data_vector_15 <= \addr_data_vector[15]\; - addr_data_vector_27 <= \addr_data_vector[27]\; - addr_data_vector_29 <= \addr_data_vector[29]\; - addr_data_vector_25 <= \addr_data_vector[25]\; - addr_data_vector_6 <= \addr_data_vector[6]\; - addr_data_vector_8 <= \addr_data_vector[8]\; - addr_data_vector_7 <= \addr_data_vector[7]\; - addr_data_vector_10 <= \addr_data_vector[10]\; - addr_data_vector_9 <= \addr_data_vector[9]\; - addr_data_vector_12 <= \addr_data_vector[12]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[16]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[10]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNIBABE[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[30]\); - - un1_address_m45 : NOR3C - port map(A => \addr_data_vector[27]\, B => N_44, C => - \addr_data_vector[28]\, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f0(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : AX1C - port map(A => \addr_data_vector[25]\, B => N_42, C => - \addr_data_vector[26]\, Y => \un1_address[26]\); - - \address_RNIN894[19]\ : MX2C - port map(A => \addr_data_vector[19]\, B => - addr_data_vector_83, S => sel_data_1(1), Y => N_1312); - - un1_address_m37_m6_0_a2_4_6 : NOR3C - port map(A => \addr_data_vector[20]\, B => - \addr_data_vector[19]\, C => m37_m6_0_a2_4_4, Y => - m37_m6_0_a2_4_6); - - un1_address_m37_m6_0_a2_4 : OR2B - port map(A => m37_m6_0_a2_4_6, B => m37_m6_0_a2_4_5, Y => - m37_m6_0_a2_4_i); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[26]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[20]\); - - \address_RNIK7MA[1]\ : MX2C - port map(A => \addr_data_vector[1]\, B => - addr_data_vector_65, S => sel_data_0(1), Y => N_1280); - - \state_RNI9QRU8_0[3]\ : OR2B - port map(A => address_0_sqmuxa_0, B => state7, Y => - address_0_sqmuxa); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \address_RNIPPHB[5]\ : MX2C - port map(A => \addr_data_vector[5]\, B => - addr_data_vector_69, S => sel_data(1), Y => N_1326); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : XOR2 - port map(A => N_4_0, B => \addr_data_vector[5]\, Y => - N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[12]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f0(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - \update_r_RNIVJV4[0]\ : OR2B - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => un3_update_r); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XNOR2 - port map(A => N_19_0, B => \addr_data_vector[11]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[22]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f0(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[2]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - un1_address_m43 : NOR3C - port map(A => \addr_data_vector[25]\, B => N_42, C => - \addr_data_vector[26]\, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f0(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f0(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_64, Q => status_full_err(0)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : OR3B - port map(A => \addr_data_vector[9]\, B => - \addr_data_vector[10]\, C => N_16_0, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \state_RNIF9F11[2]\ : NOR2A - port map(A => \state[2]_net_1\, B => N_83_i, Y => N_84); - - un1_address_ADD_32x32_fast_I164_Y_0_0 : XNOR2 - port map(A => \addr_data_vector[6]\, B => address_0_sqmuxa, - Y => ADD_32x32_fast_I164_Y_0_0); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f0(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[5]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[15]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[13]\); - - un1_address_m20 : NOR2A - port map(A => \addr_data_vector[11]\, B => N_19_0, Y => - N_21_0); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \address_RNIJ894[17]\ : MX2C - port map(A => \addr_data_vector[17]\, B => - addr_data_vector_81, S => sel_data_1(1), Y => N_1310); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[19]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[25]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[23]\); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[7]\, C => - \addr_data_vector[8]\, Y => N_15_0_i_0); - - un1_address_m29 : AX1 - port map(A => N_27_0, B => \addr_data_vector[16]\, C => - \addr_data_vector[17]\, Y => N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \address_RNO_2[31]\ : NOR3B - port map(A => address_7_31_m6_e_3, B => address_7_31_m6_e_2, - C => \state_0[0]_net_1\, Y => \address_RNO_2_0[31]\); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[29]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[18]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f0(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f0(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address_RNIH894[16]\ : MX2C - port map(A => \addr_data_vector[16]\, B => - addr_data_vector_80, S => sel_data_1(1), Y => N_1309); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f0(0), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - \addr_data_vector[0]\); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - \state_RNIRJCD[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_85); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : NOR3B - port map(A => m40_m6_0_a2_7, B => \addr_data_vector[24]\, C - => N_13_0, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f0(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[4]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[28]\); - - un1_address_m1 : NOR3A - port map(A => \addr_data_vector[2]\, B => - \un1_state_12_2[4]\, C => \un1_state_12_3_0[4]\, Y => N_2); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3A - port map(A => N_85, B => \state[3]_net_1\, C => N_83_i, Y - => N_79); - - \address_RNO_1[31]\ : XNOR2 - port map(A => N_42, B => \addr_data_vector[31]\, Y => - \address_RNO_1_0[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I164_Y_0_0, B => N_5_0, Y => - \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f0(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f0(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[14]\); - - un1_address_m23_m7_i_a5_0 : OR2B - port map(A => N_5_0, B => address_0_sqmuxa, Y => m23_N_10); - - \state_RNO[1]\ : OA1B - port map(A => N_83_i, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => \state_RNO_0[1]_net_1\); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - un1_address_m40_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[13]\, B => - \addr_data_vector[23]\, C => m40_m6_0_a2_1, Y => - m40_m6_0_a2_4); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f0(14), S => - \state[0]_net_1\, Y => \address_7[14]\); - - un1_address_m23_m7_i_a5 : AO1D - port map(A => N_5_0, B => address_0_sqmuxa, C => - \addr_data_vector[6]\, Y => m23_m7_i_a5); - - \state_RNIA6SP8[3]\ : OR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[24]\); - - un1_address_m27 : XNOR2 - port map(A => N_27_0, B => \addr_data_vector[16]\, Y => - N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \address_RNO_0[31]\ : MX2C - port map(A => \addr_data_vector[31]\, B => addr_data_f0(31), - S => \state_0[0]_net_1\, Y => \address_RNO_0_0[31]\); - - un1_address_m60 : XOR2 - port map(A => N_42, B => \addr_data_vector[25]\, Y => - \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - un1_address_m30 : OR3B - port map(A => \addr_data_vector[16]\, B => - \addr_data_vector[17]\, C => N_27_0, Y => N_31_0); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[9]\, Y => - N_17_0_i_0); - - un1_address_m37_m6_0_a2_4_2 : NOR2B - port map(A => \addr_data_vector[17]\, B => - \addr_data_vector[18]\, Y => m37_m6_0_a2_4_2); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - un1_address_m23_m7_i : OR3C - port map(A => m23_N_10, B => m23_m7_i_5, C => m23_m7_i_a5, - Y => m23_m7_i); - - \state_RNI9QRU8[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3C - port map(A => N_79, B => N_78, C => \un1_state_12_2[4]\, Y - => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[8]\); - - un1_address_m40_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[9]\, B => - \addr_data_vector[10]\, Y => m40_m6_0_a2_2); - - \address_RNIHG94[23]\ : MX2C - port map(A => \addr_data_vector[23]\, B => - addr_data_vector_87, S => sel_data_1(1), Y => N_1302); - - un1_address_m50 : AX1C - port map(A => \addr_data_vector[3]\, B => N_2, C => - \addr_data_vector[4]\, Y => N_51_i_0); - - un1_address_m39 : AX1B - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, C => \addr_data_vector[2]\, Y => - N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : OR2A - port map(A => update_and_sel_7(0), B => update_and_sel_7(1), - Y => N_83_i); - - un1_address_m23_m7_i_2 : NOR2B - port map(A => \addr_data_vector[10]\, B => - \addr_data_vector[11]\, Y => m23_m7_i_2); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f0(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => status_full_ack(0), B => N_84, C => N_80, Y - => \state_ns[2]\); - - \address_RNIBG94[20]\ : MX2C - port map(A => \addr_data_vector[20]\, B => - addr_data_vector_84, S => sel_data_1(1), Y => N_1313); - - \address_RNI7894[11]\ : MX2C - port map(A => \addr_data_vector[11]\, B => - addr_data_vector_75, S => sel_data_1(1), Y => N_1318); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f0(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f0(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - un1_address_m40_m6_0_a2_3 : NOR2B - port map(A => \addr_data_vector[11]\, B => - \addr_data_vector[12]\, Y => m40_m6_0_a2_3); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1B - port map(A => m23_m7_i, B => m37_m6_0_a2_4_i, C => - \addr_data_vector[23]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa, C => - \addr_data_vector[6]\, Y => N_13_0); - - un1_address_m59 : AX1 - port map(A => N_13_0, B => m40_m6_0_a2_7, C => - \addr_data_vector[24]\, Y => \un1_address[24]\); - - \update_r[0]\ : DFN1P0 - port map(D => update_and_sel_7(0), CLK => HCLK_c, PRE => - HRESETn_c, Q => \update_r_i[0]\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - \state_RNIBABE[1]\ : NOR2A - port map(A => status_full_ack(0), B => N_85, Y => - \state_RNIBABE[1]_net_1\); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => m40_m6_0_a2_3, B => m40_m6_0_a2_2, C => - m40_m6_0_a2_4, Y => m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f0(17), S => - \state[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f0(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[7]\, B => - \addr_data_vector[8]\, C => N_13_0, Y => N_16_0); - - un1_address_m58 : AX1C - port map(A => \addr_data_vector[21]\, B => N_36_0, C => - \addr_data_vector[22]\, Y => \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - un1_address_m26 : OR3B - port map(A => \addr_data_vector[14]\, B => - \addr_data_vector[15]\, C => m23_m7_i, Y => N_27_0); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f0(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address_RNO_4[31]\ : NOR2B - port map(A => \addr_data_vector[28]\, B => - \addr_data_vector[29]\, Y => address_7_31_m6_e_2); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[3]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XOR2 - port map(A => N_46, B => \addr_data_vector[29]\, Y => - \un1_address[29]\); - - un1_address_m34 : XNOR2 - port map(A => N_34_0, B => \addr_data_vector[20]\, Y => - \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f0(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(0), B => N_85, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[3]_net_1\); - - un1_address_m23_m7_i_1 : NOR2B - port map(A => \addr_data_vector[8]\, B => - \addr_data_vector[9]\, Y => m23_m7_i_1); - - \address_RNIIVLA[0]\ : MX2C - port map(A => \addr_data_vector[0]\, B => - addr_data_vector_64, S => sel_data_0(1), Y => N_1279); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : AX1C - port map(A => \addr_data_vector[12]\, B => N_21_0, C => - \addr_data_vector[13]\, Y => N_55_0_i_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[7]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[5]_net_1\); - - un1_address_m3 : NOR3C - port map(A => \addr_data_vector[3]\, B => N_2, C => - \addr_data_vector[4]\, Y => N_4_0); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - \address_RNIDG94[21]\ : MX2C - port map(A => \addr_data_vector[21]\, B => - addr_data_vector_85, S => sel_data_1(1), Y => N_1314); - - un1_address_m25 : AX1 - port map(A => m23_m7_i, B => \addr_data_vector[14]\, C => - \addr_data_vector[15]\, Y => N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_1[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - \address_RNIFG94[22]\ : MX2C - port map(A => \addr_data_vector[22]\, B => - addr_data_vector_86, S => sel_data_1(1), Y => N_1315); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_7(1), CLK => HCLK_c, CLR => - HRESETn_c, Q => \update_r[1]_net_1\); - - un1_address_m40_m6_0_a2_7 : NOR2A - port map(A => m40_m6_0_a2_6, B => m37_m6_0_a2_4_i, Y => - m40_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - \address_RNINHHB[4]\ : MX2C - port map(A => \addr_data_vector[4]\, B => - addr_data_vector_68, S => sel_data(1), Y => N_1325); - - un1_address_m57 : XOR2 - port map(A => N_36_0, B => \addr_data_vector[21]\, Y => - \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - \address_RNING94[26]\ : MX2C - port map(A => \addr_data_vector[26]\, B => - addr_data_vector_90, S => sel_data_1(1), Y => N_1305); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f0(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : XOR2 - port map(A => N_2, B => \addr_data_vector[3]\, Y => - N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[9]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f0(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f0(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m23_m7_i_5 : NOR3C - port map(A => m23_m7_i_2, B => m23_m7_i_1, C => m23_m7_i_3, - Y => m23_m7_i_5); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - \address_RNIRG94[28]\ : MX2C - port map(A => \addr_data_vector[28]\, B => - addr_data_vector_92, S => sel_data_1(1), Y => N_1307); - - status_full_err_RNO : OR2 - port map(A => un1_state_5_i_0, B => N_84, Y => N_64); - - \state_0[0]\ : DFN1C0 - port map(D => \state_RNIBABE[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f0(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[11]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - \state_RNIU3MB[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => un3_update_r, Y => - address_0_sqmuxa_0); - - un1_address_m56 : XNOR2 - port map(A => N_31_0, B => \addr_data_vector[18]\, Y => - \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f0(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f0(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f0(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[21]\); - - un1_address_m23_m7_i_3 : NOR3C - port map(A => \addr_data_vector[7]\, B => - \addr_data_vector[13]\, C => \addr_data_vector[12]\, Y - => m23_m7_i_3); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - un1_address_m62 : XOR2 - port map(A => N_44, B => \addr_data_vector[27]\, Y => - \un1_address[27]\); - - \address_RNIB894[13]\ : MX2C - port map(A => \addr_data_vector[13]\, B => - addr_data_vector_77, S => sel_data_1(1), Y => N_1320); - - un1_address_m32 : AX1 - port map(A => N_31_0, B => \addr_data_vector[18]\, C => - \addr_data_vector[19]\, Y => \un1_address[19]\); - - un1_address_m12_e : OR2B - port map(A => N_4_0, B => \addr_data_vector[5]\, Y => N_5_0); - - \address_RNO_5[31]\ : NOR2B - port map(A => \addr_data_vector[26]\, B => - \addr_data_vector[27]\, Y => address_7_31_m6_e_1); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => \state_RNO_0[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[17]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : AX1C - port map(A => \addr_data_vector[29]\, B => N_46, C => - \addr_data_vector[30]\, Y => \un1_address[30]\); - - un1_address_m35 : NOR2A - port map(A => \addr_data_vector[20]\, B => N_34_0, Y => - N_36_0); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[7]\, Y => - N_1_i_0); - - \address_RNINFMA[2]\ : MX2C - port map(A => \addr_data_vector[2]\, B => - addr_data_vector_66, S => sel_data_1(1), Y => N_1323); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[27]\); - - \state_RNO[3]\ : NOR2B - port map(A => \state[4]_net_1\, B => N_83_i, Y => - \state_RNO_1[3]\); - - un1_address_m21 : XOR2 - port map(A => N_21_0, B => \addr_data_vector[12]\, Y => - N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - \address_RNIGO94[30]\ : MX2C - port map(A => \addr_data_vector[30]\, B => - addr_data_vector_94, S => sel_data_0(1), Y => N_1295); - - un1_address_m55 : XNOR2 - port map(A => m23_m7_i, B => \addr_data_vector[14]\, Y => - N_56_0_i_0); - - \address_RNO[31]\ : MX2C - port map(A => \address_RNO_0_0[31]\, B => - \address_RNO_1_0[31]\, S => \address_RNO_2_0[31]\, Y => - \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f0(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - \update_r_RNIVJV4_0[0]\ : OR2 - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => \un1_state_12_3_0[4]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : OR2 - port map(A => \state[2]_net_1\, B => N_80, Y => - un1_state_11); - - \address_RNIJG94[24]\ : MX2C - port map(A => \addr_data_vector[24]\, B => - addr_data_vector_88, S => sel_data_1(1), Y => N_1303); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f0(1), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - \addr_data_vector[1]\); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_11, Q => status_full(0)); - - un1_address_m63 : AX1C - port map(A => \addr_data_vector[27]\, B => N_44, C => - \addr_data_vector[28]\, Y => \un1_address[28]\); - - un1_address_m33 : OR3B - port map(A => \addr_data_vector[18]\, B => - \addr_data_vector[19]\, C => N_31_0, Y => N_34_0); - - \state_RNIA6SP8_0[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => state7, Y => N_80); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f0(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[8]_net_1\); - - \address_RNIL894[18]\ : MX2C - port map(A => \addr_data_vector[18]\, B => - addr_data_vector_82, S => sel_data_1(1), Y => N_1311); - - un1_address_m53 : AX1 - port map(A => N_16_0, B => \addr_data_vector[9]\, C => - \addr_data_vector[10]\, Y => N_54_0_i_0); - - un1_address_m40_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[7]\, B => - \addr_data_vector[8]\, Y => m40_m6_0_a2_1); - - \address_RNO_3[31]\ : NOR3C - port map(A => \addr_data_vector[25]\, B => - \addr_data_vector[30]\, C => address_7_31_m6_e_1, Y => - address_7_31_m6_e_3); - - un1_address_m37_m6_0_a2_4_4 : NOR3C - port map(A => \addr_data_vector[14]\, B => - \addr_data_vector[22]\, C => \addr_data_vector[21]\, Y - => m37_m6_0_a2_4_4); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[3]_net_1\, C - => \state[2]_net_1\, Y => N_78); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f0(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - un1_address_m37_m6_0_a2_4_5 : NOR3C - port map(A => \addr_data_vector[16]\, B => - \addr_data_vector[15]\, C => m37_m6_0_a2_4_2, Y => - m37_m6_0_a2_4_5); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_dma_send_16word is - - port( un7_dmain : out std_logic_vector(66 to 66); - data_address : in std_logic_vector(31 downto 0); - Store : out std_logic; - Fault : in std_logic; - un1_data_send_ok : out std_logic; - Request_0 : in std_logic; - N_1011 : out std_logic; - Lock_0 : in std_logic; - N_1013 : out std_logic; - N_957 : out std_logic; - N_956 : out std_logic; - N_955 : out std_logic; - N_954 : out std_logic; - N_953 : out std_logic; - N_952 : out std_logic; - N_951 : out std_logic; - N_964 : out std_logic; - N_963 : out std_logic; - N_962 : out std_logic; - N_961 : out std_logic; - N_960 : out std_logic; - time_select : in std_logic; - N_959 : out std_logic; - N_958 : out std_logic; - N_971 : out std_logic; - N_970 : out std_logic; - N_969 : out std_logic; - N_968 : out std_logic; - N_967 : out std_logic; - N_966 : out std_logic; - N_965 : out std_logic; - N_978 : out std_logic; - N_977 : out std_logic; - N_976 : out std_logic; - N_975 : out std_logic; - N_974 : out std_logic; - N_973 : out std_logic; - N_972 : out std_logic; - N_950 : out std_logic; - N_949 : out std_logic; - N_948 : out std_logic; - time_select_0 : in std_logic; - N_947 : out std_logic; - N_249 : out std_logic; - Grant : in std_logic; - Ready : in std_logic; - data_send : in std_logic; - OKAY : in std_logic; - N_200 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_dma_send_16word; - -architecture DEF_ARCH of lpp_dma_send_16word is - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[5]_net_1\, N_4, N_198_0, N_509, N_344, - N_154_0, N_241, N_235, N_242, N_202_0, m74_0, - \data_counter[30]_net_1\, \data_counter[29]_net_1\, - ADD_32x32_fast_I129_un1_Y_14, ADD_32x32_fast_I129_un1_Y_9, - ADD_32x32_fast_I129_un1_Y_8, ADD_32x32_fast_I129_un1_Y_13, - ADD_32x32_fast_I129_un1_Y_5, ADD_32x32_fast_I129_un1_Y_4, - ADD_32x32_fast_I129_un1_Y_11, \grant_counter[27]_net_1\, - \grant_counter[26]_net_1\, ADD_32x32_fast_I129_un1_Y_7, - \grant_counter[19]_net_1\, \grant_counter[18]_net_1\, - ADD_32x32_fast_I129_un1_Y_3, \grant_counter[15]_net_1\, - \grant_counter[14]_net_1\, ADD_32x32_fast_I129_un1_Y_1, - \grant_counter[28]_net_1\, \grant_counter[29]_net_1\, - \grant_counter[24]_net_1\, \grant_counter[25]_net_1\, - \grant_counter[22]_net_1\, \grant_counter[23]_net_1\, - \grant_counter[20]_net_1\, \grant_counter[21]_net_1\, - \grant_counter[16]_net_1\, \grant_counter[17]_net_1\, - m43_m6_0_a2_6, \grant_counter[13]_net_1\, - \grant_counter[12]_net_1\, m43_m6_0_a2_4, m43_m6_0_a2_5, - \grant_counter[9]_net_1\, \grant_counter[8]_net_1\, - m43_m6_0_a2_2, \grant_counter[7]_net_1\, - \grant_counter[6]_net_1\, \grant_counter[10]_net_1\, - \grant_counter[11]_net_1\, \data_counter_8_i_0[0]\, N_508, - N_338_1, N_337, \grant_counter_0_i_0[4]\, N_246, - un1_hresetn_inv_i_0, ADD_32x32_fast_I129_un1_Y_14_0, - ADD_32x32_fast_I129_un1_Y_9_0, - ADD_32x32_fast_I129_un1_Y_8_0, - ADD_32x32_fast_I129_un1_Y_13_0, - ADD_32x32_fast_I129_un1_Y_5_0, - ADD_32x32_fast_I129_un1_Y_4_0, - ADD_32x32_fast_I129_un1_Y_11_0, \data_counter[27]_net_1\, - \data_counter[26]_net_1\, ADD_32x32_fast_I129_un1_Y_7_0, - \data_counter[19]_net_1\, \data_counter[18]_net_1\, - ADD_32x32_fast_I129_un1_Y_3_0, \data_counter[15]_net_1\, - \data_counter[14]_net_1\, ADD_32x32_fast_I129_un1_Y_1_0, - \data_counter[28]_net_1\, \data_counter[24]_net_1\, - \data_counter[25]_net_1\, \data_counter[22]_net_1\, - \data_counter[23]_net_1\, \data_counter[20]_net_1\, - \data_counter[21]_net_1\, \data_counter[16]_net_1\, - \data_counter[17]_net_1\, m28_m6_5, \state[3]_net_1\, - m28_m6_4, m28_m6_1, m28_m6_0, m28_m6_2, - \data_counter[0]_net_1\, \state[0]_net_1\, - \data_counter[2]_net_1\, \data_counter[3]_net_1\, - \data_counter[13]_net_1\, \data_counter[1]_net_1\, - \grant_counter_0_0_0[0]\, \grant_counter[0]_net_1\, - un1_state_2_i_o2_0, \state[1]_net_1\, \state[2]_net_1\, - \state_ns_i_a2_i_0_0[0]\, un1_state_7_i_a4_0_1, N_518_1, - un1_state_5_i_o2_30, un1_state_5_i_o2_25, - un1_state_5_i_o2_24, un1_state_5_i_o2_29, - un1_state_5_i_o2_21, un1_state_5_i_o2_20, - un1_state_5_i_o2_27, un1_state_5_i_o2_13, - un1_state_5_i_o2_12, un1_state_5_i_o2_23, - un1_state_5_i_o2_5, un1_state_5_i_o2_4, - un1_state_5_i_o2_19, un1_state_5_i_o2_1, - un1_state_5_i_o2_0, un1_state_5_i_o2_17, - un1_state_5_i_o2_15, un1_state_5_i_o2_11, - un1_state_5_i_o2_9, un1_state_5_i_o2_7, - un1_state_5_i_o2_3, \data_counter[5]_net_1\, - \data_counter[4]_net_1\, \data_counter[10]_net_1\, - \data_counter[11]_net_1\, \data_counter[8]_net_1\, - \data_counter[9]_net_1\, \data_counter[6]_net_1\, - \data_counter[7]_net_1\, \data_counter[31]_net_1\, - \data_counter[12]_net_1\, \state_ns_i_a2_0_i_o2_29[3]\, - \state_ns_i_a2_0_i_o2_21[3]\, - \state_ns_i_a2_0_i_o2_20[3]\, - \state_ns_i_a2_0_i_o2_27[3]\, - \state_ns_i_a2_0_i_o2_22[3]\, - \state_ns_i_a2_0_i_o2_23[3]\, - \state_ns_i_a2_0_i_o2_25[3]\, \state_ns_i_a2_0_i_o2_5[3]\, - \state_ns_i_a2_0_i_o2_4[3]\, \state_ns_i_a2_0_i_o2_19[3]\, - \state_ns_i_a2_0_i_o2_24[3]\, \state_ns_i_a2_0_i_o2_3[3]\, - \state_ns_i_a2_0_i_o2_2[3]\, \state_ns_i_a2_0_i_o2_16[3]\, - \state_ns_i_a2_0_i_o2_15[3]\, - \state_ns_i_a2_0_i_o2_13[3]\, - \state_ns_i_a2_0_i_o2_11[3]\, \state_ns_i_a2_0_i_o2_9[3]\, - \state_ns_i_a2_0_i_o2_6[3]\, \state_ns_i_a2_0_i_o2_7[3]\, - \state_ns_i_a2_0_i_o2_1[3]\, \grant_counter[4]_net_1\, - \grant_counter[31]_net_1\, \grant_counter[2]_net_1\, - \grant_counter[3]_net_1\, \grant_counter[1]_net_1\, - \grant_counter[5]_net_1\, \grant_counter[30]_net_1\, - m27_m6_0_a2_4_5, m27_m6_0_a2_4_2, m27_m6_0_a2_4_4, - m27_m6_0_a2_4_3, N_75, N_72, I129_un1_Y, N623, - \grant_counter_RNO[0]_net_1\, N_89, N_19_0, N_346, N_243, - \state[4]_net_1\, N_194_i_0, N_522, Burst, N_526, N_339, - N_186, N_336, \un1_state_4_i_i[31]\, N_75_0, N_72_0, - m27_m6_0_a2_4, N_44, N_21_0, N623_0, N_28_0, N_19_0_0, - N_22_0, N_23_0, N_24_0, N_25_0, N_26_0, N_27_0, N_28_0_0, - \un1_hresetn_inv_2_i[26]\, \un1_hresetn_inv_2_i[15]\, - N_48, \un1_hresetn_inv_2_i[13]\, N_52, - \un1_hresetn_inv_2_i[11]\, N_56, \un1_hresetn_inv_2_i[9]\, - N_60, \un1_hresetn_inv_2_i[7]\, N_64, - \un1_hresetn_inv_2_i[5]\, N_68, \un1_hresetn_inv_2_i[3]\, - N_23_0_0, N_22_0_0, N_24_0_0, N_25_0_0, N_26_0_0, - N_27_0_0, N_45, N_46, N_48_0, N_50, N_52_0, N_54, N_56_0, - N_58, N_60_0, N_62, N_64_0, N_66, N_68_0, - \un1_state_4_i[17]\, \data_counter_8[7]\, - \data_counter_8[8]\, \data_counter_8[9]\, - \data_counter_8[10]\, \data_counter_8[11]\, - \data_counter_8[12]\, \data_counter_8[13]\, - \data_counter_8[14]\, \data_counter_8[15]\, - \data_counter_8[16]\, \data_counter_8[17]\, - \data_counter_8[18]\, \data_counter_8[19]\, - \data_counter_8[20]\, \data_counter_8[21]\, N_198, - \data_counter_8[22]\, \data_counter_8[23]\, - \data_counter_8[24]\, \data_counter_8[25]\, - \data_counter_8[26]\, N_13, N_15, N_17, N_19, N_21, N_23, - N_25, N_27, N_29, N_31, N_33, N_35, N_43, N_45_0, N_47, - N_49, N_51, N_53, N_55, \state[5]_net_1\, N_57, N_59, - N_61, N_63, N_65, N_67, N_69, N_71, N_73, N_75_1, N_77, - N_79, N_81, N_91, N_93, N_95, N_97, N_99, N_101, N_103, - N_105, N_107, N_109, N_111, N_113, N_115, N_117, N_119, - N_202, N_121, N_123, N_125, N_127, N_129, N_131, N_133, - N_135, N_137, N_139, N_141, N_143, \N_200\, \Address[0]\, - \Address[1]\, \Address[2]\, \Address[3]\, \Address[25]\, - \Address[26]\, \Address[27]\, \Address[28]\, - \Address[29]\, \Address[30]\, \Address[31]\, - \Address[18]\, \Address[19]\, \Address[20]\, - \Address[21]\, \Address[22]\, \Address[23]\, - \Address[24]\, \Address[11]\, \Address[12]\, - \Address[13]\, \Address[14]\, \Address[15]\, - \Address[16]\, \Address[17]\, \Address[4]\, \Address[5]\, - \Address[6]\, \Address[7]\, \Address[8]\, \Address[9]\, - \Address[10]\, Lock, Request, N_84, Request_5, N_32_0_i_0, - N_17_0, \grant_counter_RNO[2]_net_1\, N_513, N_146, N_516, - N_151, data_send_ok, data_send_ko, - \grant_counter_RNO[3]_net_1\, N_33_0_i_0, - \grant_counter_RNO[1]_net_1\, N_31_0_i_0, - \state_RNO_0[0]_net_1\, \state_RNO[0]_net_1\, - \state_RNO[3]_net_1\, N_154, N_192, \un1_state_4_i[28]\, - N_190, \un1_state_4_i[29]\, N_188, \un1_state_4_i[30]\, - N_156, N_348, \data_counter_8[31]\, \data_counter_8[30]\, - \un1_state_4_i[1]\, \data_counter_8[29]\, - \data_counter_8[28]\, N_70, \data_counter_8[27]\, - \data_counter_8[6]\, N_21_0_0, \data_counter_8[5]\, - N_20_0, \data_counter_8[4]\, N_510, N_18_0, N_16_0, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - N_200 <= \N_200\; - - un1_hresetn_inv_2_m66 : AX1E - port map(A => \grant_counter[25]_net_1\, B => N_64, C => - \grant_counter[26]_net_1\, Y => \un1_hresetn_inv_2_i[5]\); - - \state_RNIK8SG_1[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => OKAY, Y => N_249); - - \DMAIn.Address[7]\ : DFN1E1C0 - port map(D => N_27, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[7]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNO[0]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[0]_net_1\); - - un1_state_4_m28_m6_4 : NOR3C - port map(A => m28_m6_1, B => m28_m6_0, C => m28_m6_2, Y => - m28_m6_4); - - \data_counter_RNIMF78[4]\ : NOR3A - port map(A => un1_state_5_i_o2_3, B => - \data_counter[5]_net_1\, C => \data_counter[4]_net_1\, Y - => un1_state_5_i_o2_17); - - \data_counter_RNO[31]\ : XA1C - port map(A => \data_counter[31]_net_1\, B => N_75_0, C => - N_198, Y => \data_counter_8[31]\); - - un1_state_4_m51 : NOR2B - port map(A => N_50, B => \data_counter[18]_net_1\, Y => - N_52_0); - - \data_counter_RNO[2]\ : AOI1B - port map(A => \un1_state_4_i[29]\, B => N_344, C => N_509, - Y => N_190); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_3 : NOR2B - port map(A => \grant_counter[20]_net_1\, B => - \grant_counter[21]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_3); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y : NOR2B - port map(A => ADD_32x32_fast_I129_un1_Y_14, B => N623, Y - => I129_un1_Y); - - \data_counter_RNO[18]\ : XA1B - port map(A => \data_counter[18]_net_1\, B => N_50, C => - N_198_0, Y => \data_counter_8[18]\); - - un1_state_4_m17 : NOR3C - port map(A => \data_counter[1]_net_1\, B => N_16_0, C => - \data_counter[2]_net_1\, Y => N_18_0); - - \grant_counter_RNO[5]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[26]\, Y - => N_91); - - un1_state_4_m49 : NOR2B - port map(A => N_48_0, B => \data_counter[17]_net_1\, Y => - N_50); - - un1_state_4_m28_m6_2 : NOR2A - port map(A => \data_counter[0]_net_1\, B => - \state[0]_net_1\, Y => m28_m6_2); - - \DMAIn.Address_RNIJIRJ[25]\ : MX2 - port map(A => \Address[25]\, B => data_address(25), S => - time_select_0, Y => N_972); - - \DMAIn.Address_RNI54FJ[14]\ : MX2 - port map(A => \Address[14]\, B => data_address(14), S => - time_select, Y => N_961); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_5 : NOR2B - port map(A => \data_counter[24]_net_1\, B => - \data_counter[25]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_5_0); - - \grant_counter_RNO[26]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[5]\, Y => - N_133); - - \DMAIn.Address_RNO[20]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(20), Y - => N_59); - - \DMAIn.Address_RNIEF261[5]\ : MX2 - port map(A => \Address[5]\, B => data_address(5), S => - time_select, Y => N_952); - - \grant_counter[0]\ : DFN1 - port map(D => \grant_counter_RNO[0]_net_1\, CLK => HCLK_c, - Q => \grant_counter[0]_net_1\); - - \DMAIn.Address[6]\ : DFN1E1C0 - port map(D => N_25, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[6]\); - - \DMAIn.Address_RNI3IKI[13]\ : MX2 - port map(A => \Address[13]\, B => data_address(13), S => - time_select, Y => N_960); - - \DMAIn.Address_RNIL0M41[0]\ : MX2 - port map(A => \Address[0]\, B => data_address(0), S => - time_select_0, Y => N_947); - - un1_state_4_m53 : NOR2B - port map(A => N_52_0, B => \data_counter[19]_net_1\, Y => - N_54); - - \grant_counter[20]\ : DFN1 - port map(D => N_121, CLK => HCLK_c, Q => - \grant_counter[20]_net_1\); - - \DMAIn.Address_RNO[27]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(27), Y - => N_73); - - un1_state_4_m27_m6_0_a2_4_4 : NOR3C - port map(A => \data_counter[4]_net_1\, B => - \data_counter[12]_net_1\, C => \data_counter[11]_net_1\, - Y => m27_m6_0_a2_4_4); - - \data_counter_RNO[14]\ : NOR2 - port map(A => \un1_state_4_i[17]\, B => N_198_0, Y => - \data_counter_8[14]\); - - \data_counter_RNO[21]\ : XA1B - port map(A => \data_counter[21]_net_1\, B => N_56_0, C => - N_198, Y => \data_counter_8[21]\); - - \data_counter_RNIN6PF[31]\ : NOR2 - port map(A => \data_counter[31]_net_1\, B => - \data_counter[12]_net_1\, Y => un1_state_5_i_o2_0); - - \DMAIn.Address[2]\ : DFN1E1C0 - port map(D => N_17, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[2]\); - - \DMAIn.Address[28]\ : DFN1E1C0 - port map(D => N_75_1, CLK => HCLK_c, CLR => HRESETn_c, E - => N_154, Q => \Address[28]\); - - un1_state_4_m19 : NOR2B - port map(A => N_19_0_0, B => \data_counter[4]_net_1\, Y => - N_20_0); - - \grant_counter[26]\ : DFN1 - port map(D => N_133, CLK => HCLK_c, Q => - \grant_counter[26]_net_1\); - - \grant_counter[29]\ : DFN1 - port map(D => N_139, CLK => HCLK_c, Q => - \grant_counter[29]_net_1\); - - \grant_counter[1]\ : DFN1 - port map(D => \grant_counter_RNO[1]_net_1\, CLK => HCLK_c, - Q => \grant_counter[1]_net_1\); - - \data_counter[16]\ : DFN1C0 - port map(D => \data_counter_8[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[16]_net_1\); - - \data_counter[13]\ : DFN1C0 - port map(D => \data_counter_8[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[13]_net_1\); - - un1_state_4_m74 : OR2B - port map(A => m74_0, B => N_72_0, Y => N_75_0); - - un1_hresetn_inv_2_m21 : NOR2B - port map(A => N_21_0, B => \grant_counter[6]_net_1\, Y => - N_22_0); - - \state_0[5]\ : DFN1P0 - port map(D => N_4, CLK => HCLK_c, PRE => HRESETn_c, Q => - \state_0[5]_net_1\); - - \DMAIn.Address[29]\ : DFN1E1C0 - port map(D => N_77, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[29]\); - - \state_RNIV6P14[3]\ : OR2A - port map(A => N_526, B => N_242, Y => N_156); - - \grant_counter_RNO[3]\ : AO1 - port map(A => N_33_0_i_0, B => N_202, C => N_513, Y => - \grant_counter_RNO[3]_net_1\); - - \grant_counter_RNIP43F[6]\ : NOR2 - port map(A => \grant_counter[6]_net_1\, B => - \grant_counter[7]_net_1\, Y => - \state_ns_i_a2_0_i_o2_4[3]\); - - un1_hresetn_inv_2_m20 : NOR3C - port map(A => \grant_counter[4]_net_1\, B => N_19_0, C => - \grant_counter[5]_net_1\, Y => N_21_0); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_9 : NOR3C - port map(A => \data_counter[19]_net_1\, B => - \data_counter[18]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_3_0, Y => - ADD_32x32_fast_I129_un1_Y_9_0); - - \grant_counter_RNIC1Q[18]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_11[3]\, B => - \grant_counter[19]_net_1\, C => \grant_counter[18]_net_1\, - Y => \state_ns_i_a2_0_i_o2_21[3]\); - - \grant_counter_RNIBSC[10]\ : NOR2 - port map(A => \grant_counter[10]_net_1\, B => - \grant_counter[11]_net_1\, Y => - \state_ns_i_a2_0_i_o2_6[3]\); - - \grant_counter_RNO[16]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[15]\, Y - => N_113); - - un1_hresetn_inv_2_m23 : NOR2B - port map(A => N_23_0, B => \grant_counter[8]_net_1\, Y => - N_24_0); - - \data_counter[11]\ : DFN1C0 - port map(D => \data_counter_8[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[11]_net_1\); - - \data_counter_RNIMDJV[22]\ : NOR3A - port map(A => un1_state_5_i_o2_11, B => - \data_counter[23]_net_1\, C => \data_counter[22]_net_1\, - Y => un1_state_5_i_o2_21); - - \data_counter_RNI4TP71[4]\ : NOR3C - port map(A => un1_state_5_i_o2_1, B => un1_state_5_i_o2_0, - C => un1_state_5_i_o2_17, Y => un1_state_5_i_o2_24); - - \data_counter[8]\ : DFN1C0 - port map(D => \data_counter_8[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[8]_net_1\); - - \grant_counter_RNO[4]\ : XA1B - port map(A => \grant_counter[4]_net_1\, B => N_19_0, C => - \grant_counter_0_i_0[4]\, Y => N_89); - - \DMAIn.Address[1]\ : DFN1E1C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[1]\); - - \DMAIn.Address[13]\ : DFN1E1C0 - port map(D => N_45_0, CLK => HCLK_c, CLR => HRESETn_c, E - => N_154_0, Q => \Address[13]\); - - \state_RNIRGVK7[0]\ : OR2A - port map(A => N_348, B => N_235, Y => N_344); - - \state_RNI97HH[3]\ : MX2B - port map(A => \state[5]_net_1\, B => Fault, S => - \state[3]_net_1\, Y => N_242); - - \grant_counter_RNIH42F[3]\ : NOR2B - port map(A => \grant_counter[2]_net_1\, B => - \grant_counter[3]_net_1\, Y => - \state_ns_i_a2_0_i_o2_3[3]\); - - \DMAIn.Address[30]\ : DFN1E1C0 - port map(D => N_79, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[30]\); - - \DMAIn.Address_RNO[0]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(0), Y - => N_13); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[14]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_1, Y => - ADD_32x32_fast_I129_un1_Y_8); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_5 : NOR2B - port map(A => \grant_counter[24]_net_1\, B => - \grant_counter[25]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_5); - - un1_hresetn_inv_2_m26 : NOR2B - port map(A => N_26_0, B => \grant_counter[11]_net_1\, Y => - N_27_0); - - \DMAIn.Address_RNO[10]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(10), Y - => N_33); - - \DMAIn.Address_RNO[5]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(5), Y - => N_23); - - send_ok : DFN1E1C0 - port map(D => \state[0]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_146, Q => data_send_ok); - - \grant_counter_RNO[9]\ : XA1 - port map(A => \grant_counter[9]_net_1\, B => N_24_0, C => - N_202_0, Y => N_99); - - \data_counter_RNI5VQF[28]\ : NOR2 - port map(A => \data_counter[28]_net_1\, B => - \data_counter[29]_net_1\, Y => un1_state_5_i_o2_13); - - \DMAIn.Address[31]\ : DFN1E1C0 - port map(D => N_81, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[31]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_11 : NOR3C - port map(A => \grant_counter[27]_net_1\, B => - \grant_counter[26]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_7, Y => - ADD_32x32_fast_I129_un1_Y_11); - - \grant_counter_RNIC1GF[31]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_1[3]\, B => - \grant_counter[4]_net_1\, C => \grant_counter[31]_net_1\, - Y => \state_ns_i_a2_0_i_o2_16[3]\); - - \DMAIn.Address_RNIMP5I[11]\ : MX2 - port map(A => \Address[11]\, B => data_address(11), S => - time_select_0, Y => N_958); - - \grant_counter[25]\ : DFN1 - port map(D => N_131, CLK => HCLK_c, Q => - \grant_counter[25]_net_1\); - - \DMAIn.Address_RNO[17]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(17), Y - => N_53); - - un1_state_4_m18 : NOR2B - port map(A => N_18_0, B => \data_counter[3]_net_1\, Y => - N_19_0_0); - - un1_state_4_m55 : NOR2B - port map(A => N_54, B => \data_counter[20]_net_1\, Y => - N_56_0); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \data_counter[16]_net_1\, B => - \data_counter[17]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_1_0); - - un1_hresetn_inv_2_m71 : NOR3C - port map(A => \grant_counter[27]_net_1\, B => N_68, C => - \grant_counter[28]_net_1\, Y => N_72); - - \state[4]\ : DFN1C0 - port map(D => N_84, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[4]_net_1\); - - \grant_counter_RNO[6]\ : XA1 - port map(A => \grant_counter[6]_net_1\, B => N_21_0, C => - N_202_0, Y => N_93); - - \data_counter_RNO[22]\ : XA1B - port map(A => \data_counter[22]_net_1\, B => N_58, C => - N_198, Y => \data_counter_8[22]\); - - un1_hresetn_inv_2_m70 : AX1E - port map(A => \grant_counter[27]_net_1\, B => N_68, C => - \grant_counter[28]_net_1\, Y => \un1_hresetn_inv_2_i[3]\); - - \DMAIn.Address_RNO[28]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(28), Y - => N_75_1); - - \DMAIn.Address_RNI09N41[2]\ : MX2 - port map(A => \Address[2]\, B => data_address(2), S => - time_select_0, Y => N_949); - - \data_counter_RNITN34[6]\ : NOR2 - port map(A => \data_counter[6]_net_1\, B => - \data_counter[7]_net_1\, Y => un1_state_5_i_o2_3); - - \DMAIn.Address_RNIUHKI[12]\ : MX2 - port map(A => \Address[12]\, B => data_address(12), S => - time_select, Y => N_959); - - \data_counter_RNI1FQF[26]\ : NOR2 - port map(A => \data_counter[26]_net_1\, B => - \data_counter[27]_net_1\, Y => un1_state_5_i_o2_12); - - \grant_counter_RNO[20]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[11]\, Y => - N_121); - - un1_state_4_m21 : NOR2B - port map(A => N_21_0_0, B => \data_counter[6]_net_1\, Y => - N_22_0_0); - - \grant_counter_RNITK3F[8]\ : NOR2 - port map(A => \grant_counter[8]_net_1\, B => - \grant_counter[9]_net_1\, Y => - \state_ns_i_a2_0_i_o2_5[3]\); - - un1_hresetn_inv_2_m59 : NOR3C - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - \grant_counter[22]_net_1\, Y => N_60); - - \data_counter_RNIJJIB3[4]\ : NOR3B - port map(A => un1_state_5_i_o2_25, B => un1_state_5_i_o2_24, - C => OKAY, Y => un1_state_5_i_o2_30); - - \grant_counter_RNO[22]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[9]\, Y => - N_125); - - un1_state_4_m22 : NOR2B - port map(A => N_22_0_0, B => \data_counter[7]_net_1\, Y => - N_23_0_0); - - \state_RNI6D91[2]\ : OR2 - port map(A => \state[4]_net_1\, B => \state[2]_net_1\, Y - => N_518_1); - - \data_counter[3]\ : DFN1C0 - port map(D => N_192, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_counter[3]_net_1\); - - \DMAIn.Address_RNI9IRJ[23]\ : MX2 - port map(A => \Address[23]\, B => data_address(23), S => - time_select_0, Y => N_970); - - \state[5]\ : DFN1P0 - port map(D => N_4, CLK => HCLK_c, PRE => HRESETn_c, Q => - \state[5]_net_1\); - - \grant_counter_RNO[30]\ : XA1 - port map(A => \grant_counter[30]_net_1\, B => I129_un1_Y, C - => N_202, Y => N_141); - - \data_counter_RNO[8]\ : XA1B - port map(A => \data_counter[8]_net_1\, B => N_23_0_0, C => - N_198_0, Y => \data_counter_8[8]\); - - \data_counter[28]\ : DFN1C0 - port map(D => \data_counter_8[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[28]_net_1\); - - \state_RNI9EI2[0]\ : OR2 - port map(A => N_518_1, B => N_338_1, Y => N_516); - - \data_counter[10]\ : DFN1C0 - port map(D => \data_counter_8[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[10]_net_1\); - - \data_counter_RNO[13]\ : XA1C - port map(A => \data_counter[13]_net_1\, B => N_28_0, C => - N_198_0, Y => \data_counter_8[13]\); - - \data_counter[12]\ : DFN1C0 - port map(D => \data_counter_8[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[12]_net_1\); - - \data_counter[24]\ : DFN1C0 - port map(D => \data_counter_8[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[24]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \DMAIn.Address_RNO[26]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(26), Y - => N_71); - - un1_state_4_m23 : NOR2B - port map(A => N_23_0_0, B => \data_counter[8]_net_1\, Y => - N_24_0_0); - - un1_hresetn_inv_2_m47 : NOR3C - port map(A => \grant_counter[15]_net_1\, B => N_44, C => - \grant_counter[16]_net_1\, Y => N_48); - - \DMAIn.Address_RNO[23]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(23), Y - => N_65); - - \DMAIn.Address_RNIOUQJ[19]\ : MX2 - port map(A => \Address[19]\, B => data_address(19), S => - time_select_0, Y => N_966); - - \DMAIn.Address[12]\ : DFN1E1C0 - port map(D => N_43, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[12]\); - - \data_counter_RNIQ8473[22]\ : NOR3C - port map(A => un1_state_5_i_o2_21, B => un1_state_5_i_o2_20, - C => un1_state_5_i_o2_27, Y => un1_state_5_i_o2_29); - - \data_counter[27]\ : DFN1C0 - port map(D => \data_counter_8[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[27]_net_1\); - - \grant_counter_RNO[1]\ : AO1 - port map(A => N_31_0_i_0, B => N_202, C => N_513, Y => - \grant_counter_RNO[1]_net_1\); - - \DMAIn.Address[5]\ : DFN1E1C0 - port map(D => N_23, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_counter_RNO[10]\ : XA1B - port map(A => \data_counter[10]_net_1\, B => N_25_0_0, C - => N_198_0, Y => \data_counter_8[10]\); - - \data_counter_RNICTS71[2]\ : NOR3C - port map(A => un1_state_5_i_o2_13, B => un1_state_5_i_o2_12, - C => un1_state_5_i_o2_23, Y => un1_state_5_i_o2_27); - - \grant_counter_RNO[28]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[3]\, Y => - N_137); - - \grant_counter[17]\ : DFN1 - port map(D => N_115, CLK => HCLK_c, Q => - \grant_counter[17]_net_1\); - - \grant_counter_RNINSC[16]\ : NOR2 - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[17]_net_1\, Y => - \state_ns_i_a2_0_i_o2_9[3]\); - - \data_counter_RNO[27]\ : XA1B - port map(A => \data_counter[27]_net_1\, B => N_68_0, C => - N_198, Y => \data_counter_8[27]\); - - \grant_counter_RNO[24]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[7]\, Y => - N_129); - - \data_counter[1]\ : DFN1C0 - port map(D => N_188, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_counter[1]_net_1\); - - \grant_counter_RNO[10]\ : XA1 - port map(A => \grant_counter[10]_net_1\, B => N_25_0, C => - N_202_0, Y => N_101); - - \grant_counter[30]\ : DFN1 - port map(D => N_141, CLK => HCLK_c, Q => - \grant_counter[30]_net_1\); - - \grant_counter[9]\ : DFN1 - port map(D => N_99, CLK => HCLK_c, Q => - \grant_counter[9]_net_1\); - - \data_counter_RNO_1[0]\ : NOR3 - port map(A => N_235, B => \state[0]_net_1\, C => N_508, Y - => N_339); - - \data_counter_RNO[6]\ : XA1B - port map(A => \data_counter[6]_net_1\, B => N_21_0_0, C => - N_198, Y => \data_counter_8[6]\); - - \state_RNI1BT21[3]\ : OR2A - port map(A => N_348, B => \state[3]_net_1\, Y => N_509); - - \DMAIn.Address_RNO[30]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(30), Y - => N_79); - - \grant_counter_RNIFSC[12]\ : NOR2 - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[13]_net_1\, Y => - \state_ns_i_a2_0_i_o2_7[3]\); - - un1_state_4_m57 : NOR2B - port map(A => N_56_0, B => \data_counter[21]_net_1\, Y => - N_58); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_7 : NOR2B - port map(A => \grant_counter[28]_net_1\, B => - \grant_counter[29]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_7); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \grant_counter[22]_net_1\, B => - \grant_counter[23]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_4); - - \grant_counter_RNO[12]\ : XA1 - port map(A => \grant_counter[12]_net_1\, B => N_27_0, C => - N_202_0, Y => N_105); - - \DMAIn.Address_RNO[8]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(8), Y - => N_29); - - \DMAIn.Address[9]\ : DFN1E1C0 - port map(D => N_31, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[9]\); - - un1_state_4_m61 : NOR2B - port map(A => N_60_0, B => \data_counter[23]_net_1\, Y => - N_62); - - un1_state_4_m26 : OR2B - port map(A => N_26_0_0, B => \data_counter[11]_net_1\, Y - => N_27_0_0); - - \grant_counter[18]\ : DFN1 - port map(D => N_117, CLK => HCLK_c, Q => - \grant_counter[18]_net_1\); - - \data_counter_RNO[4]\ : XA1B - port map(A => \data_counter[4]_net_1\, B => N_19_0_0, C => - N_198, Y => \data_counter_8[4]\); - - \data_counter[29]\ : DFN1C0 - port map(D => \data_counter_8[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[29]_net_1\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[17]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_1); - - \DMAIn.Address_RNO[18]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(18), Y - => N_55); - - \DMAIn.Address[10]\ : DFN1E1C0 - port map(D => N_33, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[10]\); - - un1_state_4_m31 : AX1E - port map(A => \data_counter[1]_net_1\, B => N_16_0, C => - \data_counter[2]_net_1\, Y => \un1_state_4_i[29]\); - - \DMAIn.Address_RNO[29]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(29), Y - => N_77); - - \state_RNI1E9S2[3]\ : OAI1 - port map(A => N_246, B => un1_state_7_i_a4_0_1, C => N_516, - Y => N_146); - - un1_state_4_m32 : XNOR2 - port map(A => N_18_0, B => \data_counter[3]_net_1\, Y => - \un1_state_4_i[28]\); - - \DMAIn.Address_RNID6SJ[31]\ : MX2 - port map(A => \Address[31]\, B => data_address(31), S => - time_select_0, Y => N_978); - - \data_counter[2]\ : DFN1C0 - port map(D => N_190, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_counter[2]_net_1\); - - un1_hresetn_inv_2_m67 : NOR3C - port map(A => \grant_counter[25]_net_1\, B => N_64, C => - \grant_counter[26]_net_1\, Y => N_68); - - un1_hresetn_inv_2_m43_m6_0_a2_2 : NOR2B - port map(A => \grant_counter[10]_net_1\, B => - \grant_counter[11]_net_1\, Y => m43_m6_0_a2_2); - - \DMAIn.Address_RNI86SJ[30]\ : MX2 - port map(A => \Address[30]\, B => data_address(30), S => - time_select_0, Y => N_977); - - \DMAIn.Address[11]\ : DFN1E1C0 - port map(D => N_35, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[11]\); - - un1_hresetn_inv_2_m34 : AX1E - port map(A => \grant_counter[4]_net_1\, B => N_19_0, C => - \grant_counter[5]_net_1\, Y => \un1_hresetn_inv_2_i[26]\); - - \state_RNIR8B01[4]\ : OR2B - port map(A => \state[4]_net_1\, B => Grant, Y => \N_200\); - - \grant_counter[21]\ : DFN1 - port map(D => N_123, CLK => HCLK_c, Q => - \grant_counter[21]_net_1\); - - \DMAIn.Address_RNI6EA51[9]\ : MX2 - port map(A => \Address[9]\, B => data_address(9), S => - time_select, Y => N_956); - - \DMAIn.Address_RNI2JRJ[28]\ : MX2C - port map(A => \Address[28]\, B => data_address(28), S => - time_select_0, Y => N_975); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_7 : NOR2B - port map(A => \data_counter[28]_net_1\, B => - \data_counter[29]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_7_0); - - \grant_counter[22]\ : DFN1 - port map(D => N_125, CLK => HCLK_c, Q => - \grant_counter[22]_net_1\); - - \DMAIn.Address[14]\ : DFN1E1C0 - port map(D => N_47, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[14]\); - - \DMAIn.Burst_RNI9478\ : OR2A - port map(A => Burst, B => time_select, Y => un7_dmain(66)); - - un1_state_4_m63 : NOR2B - port map(A => N_62, B => \data_counter[24]_net_1\, Y => - N_64_0); - - un1_state_4_m44 : AX1E - port map(A => \data_counter[14]_net_1\, B => N623_0, C => - \data_counter[15]_net_1\, Y => N_45); - - \state_RNISRSN8[3]\ : OR2B - port map(A => N_509, B => N_344, Y => N_198); - - \DMAIn.Address_RNITB461[8]\ : MX2 - port map(A => \Address[8]\, B => data_address(8), S => - time_select, Y => N_955); - - \state_RNO_0[0]\ : NOR2A - port map(A => \state[0]_net_1\, B => Ready, Y => - \state_RNO_0[0]_net_1\); - - \grant_counter_RNO[18]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[13]\, Y - => N_117); - - \data_counter[0]\ : DFN1C0 - port map(D => N_186, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_counter[0]_net_1\); - - un1_hresetn_inv_2_m51 : NOR3C - port map(A => \grant_counter[17]_net_1\, B => N_48, C => - \grant_counter[18]_net_1\, Y => N_52); - - \grant_counter_RNO[27]\ : XA1 - port map(A => \grant_counter[27]_net_1\, B => N_68, C => - N_202, Y => N_135); - - \DMAIn.Address_RNO[16]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(16), Y - => N_51); - - \grant_counter_RNO[14]\ : XA1 - port map(A => \grant_counter[14]_net_1\, B => N623, C => - N_202_0, Y => N_109); - - un1_state_4_m59 : NOR2B - port map(A => N_58, B => \data_counter[22]_net_1\, Y => - N_60_0); - - \data_counter_RNI1O34[8]\ : NOR2 - port map(A => \data_counter[8]_net_1\, B => - \data_counter[9]_net_1\, Y => un1_state_5_i_o2_4); - - un1_hresetn_inv_2_m50 : AX1E - port map(A => \grant_counter[17]_net_1\, B => N_48, C => - \grant_counter[18]_net_1\, Y => \un1_hresetn_inv_2_i[13]\); - - \DMAIn.Address_RNO[13]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(13), Y - => N_45_0); - - un1_state_4_m25 : NOR2B - port map(A => N_25_0_0, B => \data_counter[10]_net_1\, Y - => N_26_0_0); - - \grant_counter_RNIU9Q[26]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_15[3]\, B => - \grant_counter[27]_net_1\, C => \grant_counter[26]_net_1\, - Y => \state_ns_i_a2_0_i_o2_23[3]\); - - \DMAIn.Address_RNIKHKI[10]\ : MX2 - port map(A => \Address[10]\, B => data_address(10), S => - time_select, Y => N_957); - - VCC_i : VCC - port map(Y => \VCC\); - - \state_RNIS4Q9[3]\ : OR3A - port map(A => Ready, B => \state[3]_net_1\, C => N_518_1, Y - => un1_state_7_i_a4_0_1); - - \DMAIn.Address_RNO[7]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(7), Y - => N_27); - - \data_counter_RNO_2[0]\ : NOR3B - port map(A => N_235, B => \state[3]_net_1\, C => - \un1_state_4_i_i[31]\, Y => N_336); - - \data_counter_RNO[16]\ : XA1B - port map(A => \data_counter[16]_net_1\, B => N_46, C => - N_198_0, Y => \data_counter_8[16]\); - - \data_counter_RNO[29]\ : XA1B - port map(A => \data_counter[29]_net_1\, B => N_72_0, C => - N_198, Y => \data_counter_8[29]\); - - un1_hresetn_inv_2_m16 : NOR3C - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => \grant_counter[1]_net_1\, Y => - N_17_0); - - \DMAIn.Address[8]\ : DFN1E1C0 - port map(D => N_29, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[8]\); - - \state_RNO[4]\ : AO1A - port map(A => Grant, B => \state[4]_net_1\, C => Request_5, - Y => N_84); - - \state_RNIK8SG_0[3]\ : OR2A - port map(A => \state[3]_net_1\, B => Fault, Y => N_522); - - un1_state_4_m27_m6_0_a2 : OR2B - port map(A => m27_m6_0_a2_4, B => N_19_0_0, Y => N_28_0); - - \grant_counter_RNIP4D[24]\ : NOR2 - port map(A => \grant_counter[24]_net_1\, B => - \grant_counter[25]_net_1\, Y => - \state_ns_i_a2_0_i_o2_13[3]\); - - \state_RNIAMD44[4]\ : NOR3A - port map(A => un1_hresetn_inv_i_0, B => N_246, C => - \state[4]_net_1\, Y => N_513); - - \DMAIn.Address_RNO[19]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(19), Y - => N_57); - - \DMAIn.Address[0]\ : DFN1E1C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[0]\); - - un1_hresetn_inv_2_m25 : NOR2B - port map(A => N_25_0, B => \grant_counter[10]_net_1\, Y => - N_26_0); - - un1_state_4_m27_m6_0_a2_4_5 : NOR3C - port map(A => \data_counter[6]_net_1\, B => - \data_counter[5]_net_1\, C => m27_m6_0_a2_4_2, Y => - m27_m6_0_a2_4_5); - - \state_RNO[2]\ : AO1C - port map(A => N_346, B => N_246, C => N_522, Y => N_151); - - \grant_counter_RNO[17]\ : XA1 - port map(A => \grant_counter[17]_net_1\, B => N_48, C => - N_202_0, Y => N_115); - - \grant_counter_RNIM2O7[30]\ : NOR2 - port map(A => \grant_counter[5]_net_1\, B => - \grant_counter[30]_net_1\, Y => - \state_ns_i_a2_0_i_o2_1[3]\); - - \state_RNIQIK31[4]\ : OR2A - port map(A => HRESETn_c, B => \N_200\, Y => N_202); - - un1_state_4_m71 : NOR2B - port map(A => N_70, B => \data_counter[28]_net_1\, Y => - N_72_0); - - \grant_counter[10]\ : DFN1 - port map(D => N_101, CLK => HCLK_c, Q => - \grant_counter[10]_net_1\); - - \data_counter_RNO[28]\ : XA1B - port map(A => \data_counter[28]_net_1\, B => N_70, C => - N_198, Y => \data_counter_8[28]\); - - \grant_counter[24]\ : DFN1 - port map(D => N_129, CLK => HCLK_c, Q => - \grant_counter[24]_net_1\); - - \data_counter_RNO[15]\ : NOR2 - port map(A => N_45, B => N_198_0, Y => \data_counter_8[15]\); - - \DMAIn.Lock_RNILJE7\ : MX2C - port map(A => Lock, B => Lock_0, S => time_select, Y => - N_1013); - - un1_state_4_m65 : NOR2B - port map(A => N_64_0, B => \data_counter[25]_net_1\, Y => - N_66); - - \DMAIn.Address_RNI4IRJ[22]\ : MX2 - port map(A => \Address[22]\, B => data_address(22), S => - time_select_0, Y => N_969); - - \grant_counter[16]\ : DFN1 - port map(D => N_113, CLK => HCLK_c, Q => - \grant_counter[16]_net_1\); - - \DMAIn.Address_RNION361[7]\ : MX2 - port map(A => \Address[7]\, B => data_address(7), S => - time_select, Y => N_954); - - \DMAIn.Address[15]\ : DFN1E1C0 - port map(D => N_49, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[15]\); - - un1_state_4_m20 : NOR2B - port map(A => N_20_0, B => \data_counter[5]_net_1\, Y => - N_21_0_0); - - \state_RNIAC4L7[3]\ : AO1D - port map(A => N_241, B => N_235, C => N_242, Y => N_154); - - \grant_counter[19]\ : DFN1 - port map(D => N_119, CLK => HCLK_c, Q => - \grant_counter[19]_net_1\); - - send_ok_RNIC0Q : NOR2 - port map(A => data_send_ok, B => data_send_ko, Y => - un1_data_send_ok); - - un1_hresetn_inv_2_m32 : AX1C - port map(A => \grant_counter[2]_net_1\, B => N_17_0, C => - \grant_counter[3]_net_1\, Y => N_33_0_i_0); - - un1_hresetn_inv_2_m27 : NOR2B - port map(A => N_27_0, B => \grant_counter[12]_net_1\, Y => - N_28_0_0); - - \data_counter[18]\ : DFN1C0 - port map(D => \data_counter_8[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[18]_net_1\); - - \DMAIn.Address_RNO[3]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(3), Y - => N_19); - - \data_counter_RNO[24]\ : XA1B - port map(A => \data_counter[24]_net_1\, B => N_62, C => - N_198, Y => \data_counter_8[24]\); - - \data_counter[14]\ : DFN1C0 - port map(D => \data_counter_8[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[14]_net_1\); - - \grant_counter_RNO[23]\ : XA1 - port map(A => \grant_counter[23]_net_1\, B => N_60, C => - N_202, Y => N_127); - - \DMAIn.Address_RNI5TN41[3]\ : MX2 - port map(A => \Address[3]\, B => data_address(3), S => - time_select_0, Y => N_950); - - un1_state_4_m28_m6_0 : NOR2B - port map(A => \data_counter[13]_net_1\, B => - \data_counter[1]_net_1\, Y => m28_m6_0); - - \state_RNIK8SG[3]\ : OR2B - port map(A => \state[3]_net_1\, B => Fault, Y => N_241); - - \DMAIn.Request_RNIJKMF\ : MX2 - port map(A => Request, B => Request_0, S => time_select, Y - => N_1011); - - \DMAIn.Address_RNO[21]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(21), Y - => N_61); - - \DMAIn.Address[23]\ : DFN1E1C0 - port map(D => N_65, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[23]\); - - \grant_counter[23]\ : DFN1 - port map(D => N_127, CLK => HCLK_c, Q => - \grant_counter[23]_net_1\); - - \data_counter[17]\ : DFN1C0 - port map(D => \data_counter_8[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[17]_net_1\); - - \state_RNIAC4L7_0[3]\ : AO1D - port map(A => N_241, B => N_235, C => N_242, Y => N_154_0); - - \state_RNI3191[1]\ : NOR2 - port map(A => \state[1]_net_1\, B => \state[2]_net_1\, Y - => un1_state_2_i_o2_0); - - \grant_counter_RNIH4D[20]\ : NOR2 - port map(A => \grant_counter[20]_net_1\, B => - \grant_counter[21]_net_1\, Y => - \state_ns_i_a2_0_i_o2_11[3]\); - - \DMAIn.Address_RNIQKM41[1]\ : MX2 - port map(A => \Address[1]\, B => data_address(1), S => - time_select_0, Y => N_948); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_14 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_9_0, B => - ADD_32x32_fast_I129_un1_Y_8_0, C => - ADD_32x32_fast_I129_un1_Y_13_0, Y => - ADD_32x32_fast_I129_un1_Y_14_0); - - \data_counter_RNIJN34[3]\ : NOR2B - port map(A => \data_counter[3]_net_1\, B => - \data_counter[0]_net_1\, Y => un1_state_5_i_o2_15); - - \data_counter[31]\ : DFN1C0 - port map(D => \data_counter_8[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[31]_net_1\); - - \data_counter_RNILUOF[20]\ : NOR2 - port map(A => \data_counter[20]_net_1\, B => - \data_counter[21]_net_1\, Y => un1_state_5_i_o2_9); - - un1_state_4_m29 : XNOR2 - port map(A => \data_counter[0]_net_1\, B => N_510, Y => - \un1_state_4_i_i[31]\); - - un1_hresetn_inv_2_m28 : NOR2B - port map(A => N_28_0_0, B => \grant_counter[13]_net_1\, Y - => N623); - - \data_counter_RNO_0[0]\ : AO1D - port map(A => N_508, B => N_338_1, C => N_337, Y => - \data_counter_8_i_0[0]\); - - \data_counter_RNIOTJV[18]\ : NOR3A - port map(A => un1_state_5_i_o2_9, B => - \data_counter[19]_net_1\, C => \data_counter[18]_net_1\, - Y => un1_state_5_i_o2_20); - - \grant_counter[31]\ : DFN1 - port map(D => N_143, CLK => HCLK_c, Q => - \grant_counter[31]_net_1\); - - \grant_counter[15]\ : DFN1 - port map(D => N_111, CLK => HCLK_c, Q => - \grant_counter[15]_net_1\); - - \DMAIn.Address_RNO[1]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(1), Y - => N_15); - - \grant_counter[6]\ : DFN1 - port map(D => N_93, CLK => HCLK_c, Q => - \grant_counter[6]_net_1\); - - \DMAIn.Address_RNO[22]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(22), Y - => N_63); - - \data_counter[19]\ : DFN1C0 - port map(D => \data_counter_8[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[19]_net_1\); - - \DMAIn.Address[16]\ : DFN1E1C0 - port map(D => N_51, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[16]\); - - \grant_counter_RNO_0[0]\ : XA1A - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => N_202_0, Y => - \grant_counter_0_0_0[0]\); - - \grant_counter[8]\ : DFN1 - port map(D => N_97, CLK => HCLK_c, Q => - \grant_counter[8]_net_1\); - - \data_counter_RNIN6PF[30]\ : NOR2 - port map(A => \data_counter[13]_net_1\, B => - \data_counter[30]_net_1\, Y => un1_state_5_i_o2_1); - - \state_RNI3191[0]\ : OR2 - port map(A => \state[3]_net_1\, B => \state[0]_net_1\, Y - => N_338_1); - - un1_state_4_m30 : XNOR2 - port map(A => N_16_0, B => \data_counter[1]_net_1\, Y => - \un1_state_4_i[30]\); - - \DMAIn.Address_RNO[24]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(24), Y - => N_67); - - \data_counter_RNO[3]\ : AOI1B - port map(A => \un1_state_4_i[28]\, B => N_344, C => N_509, - Y => N_192); - - un1_hresetn_inv_2_m43_m6_0_a2_5 : NOR3C - port map(A => \grant_counter[9]_net_1\, B => - \grant_counter[8]_net_1\, C => m43_m6_0_a2_2, Y => - m43_m6_0_a2_5); - - \DMAIn.Address_RNO[25]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(25), Y - => N_69); - - \data_counter_RNO[5]\ : XA1B - port map(A => \data_counter[5]_net_1\, B => N_20_0, C => - N_198, Y => \data_counter_8[5]\); - - \data_counter_RNITUPF[24]\ : NOR2 - port map(A => \data_counter[24]_net_1\, B => - \data_counter[25]_net_1\, Y => un1_state_5_i_o2_11); - - un1_state_4_m67 : NOR2B - port map(A => N_66, B => \data_counter[26]_net_1\, Y => - N_68_0); - - \grant_counter_RNO[13]\ : XA1 - port map(A => \grant_counter[13]_net_1\, B => N_28_0_0, C - => N_202_0, Y => N_107); - - \grant_counter_RNIDK1F[1]\ : NOR2B - port map(A => \grant_counter[0]_net_1\, B => - \grant_counter[1]_net_1\, Y => - \state_ns_i_a2_0_i_o2_2[3]\); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - \state_RNIJKJ6[1]\ : AO1A - port map(A => data_send, B => \state_0[5]_net_1\, C => - \state[1]_net_1\, Y => \state_ns_i_a2_i_0_0[0]\); - - \data_counter[7]\ : DFN1C0 - port map(D => \data_counter_8[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[7]_net_1\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_14 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_9, B => - ADD_32x32_fast_I129_un1_Y_8, C => - ADD_32x32_fast_I129_un1_Y_13, Y => - ADD_32x32_fast_I129_un1_Y_14); - - \grant_counter_RNO[21]\ : XA1 - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - N_202, Y => N_123); - - \data_counter[5]\ : DFN1C0 - port map(D => \data_counter_8[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[5]_net_1\); - - \DMAIn.Request\ : DFN1E1C0 - port map(D => Request_5, CLK => HCLK_c, CLR => HRESETn_c, E - => N_156, Q => Request); - - \DMAIn.Address_RNO[11]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(11), Y - => N_35); - - \grant_counter_RNO_0[4]\ : AO1C - port map(A => N_246, B => un1_hresetn_inv_i_0, C => N_202_0, - Y => \grant_counter_0_i_0[4]\); - - \DMAIn.Address_RNO[6]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(6), Y - => N_25); - - \DMAIn.Address[17]\ : DFN1E1C0 - port map(D => N_53, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[17]\); - - \data_counter_RNIVEQF[16]\ : NOR2 - port map(A => \data_counter[16]_net_1\, B => - \data_counter[17]_net_1\, Y => un1_state_5_i_o2_7); - - \grant_counter_RNO[31]\ : XA1 - port map(A => \grant_counter[31]_net_1\, B => N_75, C => - N_202, Y => N_143); - - \grant_counter_RNIGI0V[6]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_5[3]\, B => - \state_ns_i_a2_0_i_o2_4[3]\, C => - \state_ns_i_a2_0_i_o2_19[3]\, Y => - \state_ns_i_a2_0_i_o2_25[3]\); - - \state_RNIEK821[0]\ : NOR2 - port map(A => \state[0]_net_1\, B => N_243, Y => N_348); - - un1_state_4_m28_m6_5 : AOI1B - port map(A => \state[3]_net_1\, B => OKAY, C => m28_m6_4, Y - => m28_m6_5); - - \state_RNIF6GI1[0]\ : OR2A - port map(A => N_348, B => OKAY, Y => N_510); - - \DMAIn.Address[22]\ : DFN1E1C0 - port map(D => N_63, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[22]\); - - \data_counter_RNO[30]\ : NOR2 - port map(A => \un1_state_4_i[1]\, B => N_198, Y => - \data_counter_8[30]\); - - \data_counter[9]\ : DFN1C0 - port map(D => \data_counter_8[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[9]_net_1\); - - un1_state_4_m69 : NOR2B - port map(A => N_68_0, B => \data_counter[27]_net_1\, Y => - N_70); - - un1_hresetn_inv_2_m43_m6_0_a2_4 : NOR3C - port map(A => \grant_counter[7]_net_1\, B => - \grant_counter[6]_net_1\, C => \grant_counter[14]_net_1\, - Y => m43_m6_0_a2_4); - - un1_state_4_m27_m6_0_a2_4 : NOR3C - port map(A => m27_m6_0_a2_4_4, B => m27_m6_0_a2_4_3, C => - m27_m6_0_a2_4_5, Y => m27_m6_0_a2_4); - - \data_counter[30]\ : DFN1C0 - port map(D => \data_counter_8[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[30]_net_1\); - - un1_state_4_m28_m6_1 : NOR2B - port map(A => \data_counter[2]_net_1\, B => - \data_counter[3]_net_1\, Y => m28_m6_1); - - \data_counter_RNO[7]\ : XA1B - port map(A => \data_counter[7]_net_1\, B => N_22_0_0, C => - N_198_0, Y => \data_counter_8[7]\); - - \data_counter_RNO[11]\ : XA1B - port map(A => \data_counter[11]_net_1\, B => N_26_0_0, C - => N_198_0, Y => \data_counter_8[11]\); - - un1_hresetn_inv_2_m62 : AX1E - port map(A => \grant_counter[23]_net_1\, B => N_60, C => - \grant_counter[24]_net_1\, Y => \un1_hresetn_inv_2_i[7]\); - - \grant_counter_RNO[2]\ : AO1 - port map(A => N_32_0_i_0, B => N_202, C => N_513, Y => - \grant_counter_RNO[2]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_counter_RNO[23]\ : XA1B - port map(A => \data_counter[23]_net_1\, B => N_60_0, C => - N_198, Y => \data_counter_8[23]\); - - un1_hresetn_inv_2_m24 : NOR2B - port map(A => N_24_0, B => \grant_counter[9]_net_1\, Y => - N_25_0); - - \DMAIn.Address_RNO[12]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(12), Y - => N_43); - - un1_hresetn_inv_2_m55 : NOR3C - port map(A => \grant_counter[19]_net_1\, B => N_52, C => - \grant_counter[20]_net_1\, Y => N_56); - - \grant_counter_RNO[25]\ : XA1 - port map(A => \grant_counter[25]_net_1\, B => N_64, C => - N_202, Y => N_131); - - \DMAIn.Address_RNITIRJ[27]\ : MX2C - port map(A => \Address[27]\, B => data_address(27), S => - time_select_0, Y => N_974); - - \DMAIn.Address_RNO[14]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(14), Y - => N_47); - - \grant_counter_RNO[11]\ : XA1 - port map(A => \grant_counter[11]_net_1\, B => N_26_0, C => - N_202_0, Y => N_103); - - \grant_counter_RNI2E83[14]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_21[3]\, B => - \state_ns_i_a2_0_i_o2_20[3]\, C => - \state_ns_i_a2_0_i_o2_27[3]\, Y => - \state_ns_i_a2_0_i_o2_29[3]\); - - \DMAIn.Address[20]\ : DFN1E1C0 - port map(D => N_59, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[20]\); - - \DMAIn.Address_RNO[15]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(15), Y - => N_49); - - un1_state_4_m74_0 : NOR2B - port map(A => \data_counter[30]_net_1\, B => - \data_counter[29]_net_1\, Y => m74_0); - - \DMAIn.Address_RNIOIRJ[26]\ : MX2C - port map(A => \Address[26]\, B => data_address(26), S => - time_select_0, Y => N_973); - - \data_counter_RNO[20]\ : XA1B - port map(A => \data_counter[20]_net_1\, B => N_54, C => - N_198_0, Y => \data_counter_8[20]\); - - \state_RNI2R0V2[1]\ : AO1D - port map(A => N_346, B => N_246, C => - \state_ns_i_a2_i_0_0[0]\, Y => N_4); - - \DMAIn.Address_RNI7JRJ[29]\ : MX2 - port map(A => \Address[29]\, B => data_address(29), S => - time_select_0, Y => N_976); - - \DMAIn.Address[21]\ : DFN1E1C0 - port map(D => N_61, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[21]\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_13 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_5_0, B => - ADD_32x32_fast_I129_un1_Y_4_0, C => - ADD_32x32_fast_I129_un1_Y_11_0, Y => - ADD_32x32_fast_I129_un1_Y_13_0); - - \grant_counter[5]\ : DFN1 - port map(D => N_91, CLK => HCLK_c, Q => - \grant_counter[5]_net_1\); - - \DMAIn.Address_RNO[9]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(9), Y - => N_31); - - \DMAIn.Address[18]\ : DFN1E1C0 - port map(D => N_55, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[18]\); - - \data_counter[25]\ : DFN1C0 - port map(D => \data_counter_8[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[25]_net_1\); - - \grant_counter[4]\ : DFN1 - port map(D => N_89, CLK => HCLK_c, Q => - \grant_counter[4]_net_1\); - - \grant_counter[11]\ : DFN1 - port map(D => N_103, CLK => HCLK_c, Q => - \grant_counter[11]_net_1\); - - \DMAIn.Address[24]\ : DFN1E1C0 - port map(D => N_67, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[24]\); - - \grant_counter[12]\ : DFN1 - port map(D => N_105, CLK => HCLK_c, Q => - \grant_counter[12]_net_1\); - - \DMAIn.Burst_RNO\ : NOR3C - port map(A => N_522, B => Burst, C => N_526, Y => N_194_i_0); - - un1_hresetn_inv_2_m43_m6_0_a2 : NOR3C - port map(A => m43_m6_0_a2_6, B => m43_m6_0_a2_5, C => - N_21_0, Y => N_44); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_9 : NOR3C - port map(A => \grant_counter[19]_net_1\, B => - \grant_counter[18]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_3, Y => - ADD_32x32_fast_I129_un1_Y_9); - - \DMAIn.Address[19]\ : DFN1E1C0 - port map(D => N_57, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154_0, Q => \Address[19]\); - - \data_counter_RNO[1]\ : AOI1B - port map(A => \un1_state_4_i[30]\, B => N_344, C => N_509, - Y => N_188); - - \state_RNIMV7G3[3]\ : OR3B - port map(A => \state[3]_net_1\, B => Grant, C => N_246, Y - => N_526); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \data_counter[22]_net_1\, B => - \data_counter[23]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_4_0); - - \state_RNISRSN8_0[3]\ : OR2B - port map(A => N_509, B => N_344, Y => N_198_0); - - un1_hresetn_inv_2_m74 : NOR3C - port map(A => \grant_counter[29]_net_1\, B => - \grant_counter[30]_net_1\, C => N_72, Y => N_75); - - \grant_counter_RNI15D[28]\ : NOR2 - port map(A => \grant_counter[28]_net_1\, B => - \grant_counter[29]_net_1\, Y => - \state_ns_i_a2_0_i_o2_15[3]\); - - \data_counter[4]\ : DFN1C0 - port map(D => \data_counter_8[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[4]_net_1\); - - \DMAIn.Address_RNIVHRJ[21]\ : MX2 - port map(A => \Address[21]\, B => data_address(21), S => - time_select_0, Y => N_968); - - \grant_counter_RNO[15]\ : XA1 - port map(A => \grant_counter[15]_net_1\, B => N_44, C => - N_202_0, Y => N_111); - - un1_hresetn_inv_2_m43_m6_0_a2_6 : NOR3C - port map(A => \grant_counter[13]_net_1\, B => - \grant_counter[12]_net_1\, C => m43_m6_0_a2_4, Y => - m43_m6_0_a2_6); - - \grant_counter[7]\ : DFN1 - port map(D => N_95, CLK => HCLK_c, Q => - \grant_counter[7]_net_1\); - - \DMAIn.Address_RNO[31]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(31), Y - => N_81); - - \state[2]\ : DFN1C0 - port map(D => N_151, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[2]_net_1\); - - \data_counter_RNIE4HJ1[8]\ : NOR3C - port map(A => un1_state_5_i_o2_5, B => un1_state_5_i_o2_4, - C => un1_state_5_i_o2_19, Y => un1_state_5_i_o2_25); - - send_ko : DFN1E1C0 - port map(D => \state[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_146, Q => data_send_ko); - - \data_counter_RNO[12]\ : XA1C - port map(A => \data_counter[12]_net_1\, B => N_27_0_0, C - => N_198_0, Y => \data_counter_8[12]\); - - un1_state_4_ADD_32x32_fast_I190_Y_0 : AX1E - port map(A => N623_0, B => ADD_32x32_fast_I129_un1_Y_14_0, - C => \data_counter[30]_net_1\, Y => \un1_state_4_i[1]\); - - \DMAIn.Address_RNIMC0J[18]\ : MX2 - port map(A => \Address[18]\, B => data_address(18), S => - time_select_0, Y => N_965); - - un1_hresetn_inv_2_m31 : XOR2 - port map(A => N_17_0, B => \grant_counter[2]_net_1\, Y => - N_32_0_i_0); - - un1_state_4_m27_m6_0_a2_4_3 : NOR2B - port map(A => \data_counter[9]_net_1\, B => - \data_counter[10]_net_1\, Y => m27_m6_0_a2_4_3); - - \DMAIn.Store\ : DFN1E1C0 - port map(D => \state[5]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_156, Q => Store); - - \DMAIn.Address_RNI9R161[4]\ : MX2 - port map(A => \Address[4]\, B => data_address(4), S => - time_select, Y => N_951); - - un1_state_4_m27_m6_0_a2_4_2 : NOR2B - port map(A => \data_counter[7]_net_1\, B => - \data_counter[8]_net_1\, Y => m27_m6_0_a2_4_2); - - \grant_counter_RNO[29]\ : XA1 - port map(A => \grant_counter[29]_net_1\, B => N_72, C => - N_202, Y => N_139); - - \DMAIn.Address[3]\ : DFN1E1C0 - port map(D => N_19, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[3]\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_11 : NOR3C - port map(A => \data_counter[27]_net_1\, B => - \data_counter[26]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_7_0, Y => - ADD_32x32_fast_I129_un1_Y_11_0); - - \state[1]\ : DFN1C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - un1_hresetn_inv_2_m30 : AX1C - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => \grant_counter[1]_net_1\, Y => - N_31_0_i_0); - - \grant_counter_RNISQSF2[14]\ : OR3C - port map(A => \state_ns_i_a2_0_i_o2_25[3]\, B => - \state_ns_i_a2_0_i_o2_24[3]\, C => - \state_ns_i_a2_0_i_o2_29[3]\, Y => N_246); - - \DMAIn.Burst\ : DFN1P0 - port map(D => N_194_i_0, CLK => HCLK_c, PRE => HRESETn_c, Q - => Burst); - - un1_hresetn_inv_2_m18 : NOR3C - port map(A => \grant_counter[2]_net_1\, B => N_17_0, C => - \grant_counter[3]_net_1\, Y => N_19_0); - - un1_hresetn_inv_2_m58 : AX1E - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - \grant_counter[22]_net_1\, Y => \un1_hresetn_inv_2_i[9]\); - - \data_counter_RNO[9]\ : XA1B - port map(A => \data_counter[9]_net_1\, B => N_24_0_0, C => - N_198_0, Y => \data_counter_8[9]\); - - \DMAIn.Address_RNIK4FJ[17]\ : MX2 - port map(A => \Address[17]\, B => data_address(17), S => - time_select, Y => N_964); - - \data_counter_RNO[26]\ : XA1B - port map(A => \data_counter[26]_net_1\, B => N_66, C => - N_198, Y => \data_counter_8[26]\); - - un1_hresetn_inv_2_m22 : NOR2B - port map(A => N_22_0, B => \grant_counter[7]_net_1\, Y => - N_23_0); - - \state_RNO[3]\ : AO1C - port map(A => N_241, B => N_235, C => \N_200\, Y => - \state_RNO[3]_net_1\); - - \state_RNO[0]\ : AO1D - port map(A => N_241, B => N_235, C => - \state_RNO_0[0]_net_1\, Y => \state_RNO[0]_net_1\); - - \grant_counter[14]\ : DFN1 - port map(D => N_109, CLK => HCLK_c, Q => - \grant_counter[14]_net_1\); - - \grant_counter_RNICJK1[22]\ : NOR2B - port map(A => \state_ns_i_a2_0_i_o2_22[3]\, B => - \state_ns_i_a2_0_i_o2_23[3]\, Y => - \state_ns_i_a2_0_i_o2_27[3]\); - - \DMAIn.Address[4]\ : DFN1E1C0 - port map(D => N_21, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[4]\); - - \grant_counter[2]\ : DFN1 - port map(D => \grant_counter_RNO[2]_net_1\, CLK => HCLK_c, - Q => \grant_counter[2]_net_1\); - - \data_counter_RNIB4B41[0]\ : MX2A - port map(A => \state[5]_net_1\, B => - \data_counter[0]_net_1\, S => N_243, Y => N_508); - - \data_counter[26]\ : DFN1C0 - port map(D => \data_counter_8[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[26]_net_1\); - - \data_counter[23]\ : DFN1C0 - port map(D => \data_counter_8[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[23]_net_1\); - - \DMAIn.Address_RNIEIRJ[24]\ : MX2 - port map(A => \Address[24]\, B => data_address(24), S => - time_select_0, Y => N_971); - - \DMAIn.Address[25]\ : DFN1E1C0 - port map(D => N_69, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[25]\); - - un1_state_4_m45 : NOR3C - port map(A => \data_counter[14]_net_1\, B => N623_0, C => - \data_counter[15]_net_1\, Y => N_46); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \data_counter[15]_net_1\, B => - \data_counter[14]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_1_0, Y => - ADD_32x32_fast_I129_un1_Y_8_0); - - \grant_counter_RNO[19]\ : XA1 - port map(A => \grant_counter[19]_net_1\, B => N_52, C => - N_202, Y => N_119); - - \DMAIn.Address_RNO[2]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(2), Y - => N_17); - - \data_counter_RNO[17]\ : XA1B - port map(A => \data_counter[17]_net_1\, B => N_48_0, C => - N_198_0, Y => \data_counter_8[17]\); - - un1_state_4_m24 : NOR2B - port map(A => N_24_0_0, B => \data_counter[9]_net_1\, Y => - N_25_0_0); - - \data_counter_RNO[25]\ : XA1B - port map(A => \data_counter[25]_net_1\, B => N_64_0, C => - N_198, Y => \data_counter_8[25]\); - - \data_counter[21]\ : DFN1C0 - port map(D => \data_counter_8[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[21]_net_1\); - - \DMAIn.Address_RNO[4]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(4), Y - => N_21); - - \grant_counter_RNO[7]\ : XA1 - port map(A => \grant_counter[7]_net_1\, B => N_22_0, C => - N_202_0, Y => N_95); - - \data_counter_RNI6F78[2]\ : NOR3C - port map(A => \data_counter[2]_net_1\, B => - \data_counter[1]_net_1\, C => un1_state_5_i_o2_15, Y => - un1_state_5_i_o2_23); - - \DMAIn.Lock\ : DFN1E1C0 - port map(D => data_send, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[5]_net_1\, Q => Lock); - - \data_counter_RNO_3[0]\ : NOR2A - port map(A => \state[0]_net_1\, B => - \data_counter[0]_net_1\, Y => N_337); - - \state_RNIQIK31_0[4]\ : OR2A - port map(A => HRESETn_c, B => \N_200\, Y => N_202_0); - - \grant_counter[3]\ : DFN1 - port map(D => \grant_counter_RNO[3]_net_1\, CLK => HCLK_c, - Q => \grant_counter[3]_net_1\); - - \data_counter_RNIJUOF[10]\ : NOR2 - port map(A => \data_counter[10]_net_1\, B => - \data_counter[11]_net_1\, Y => un1_state_5_i_o2_5); - - \grant_counter[13]\ : DFN1 - port map(D => N_107, CLK => HCLK_c, Q => - \grant_counter[13]_net_1\); - - \grant_counter_RNIQOP[10]\ : NOR2B - port map(A => \state_ns_i_a2_0_i_o2_6[3]\, B => - \state_ns_i_a2_0_i_o2_7[3]\, Y => - \state_ns_i_a2_0_i_o2_19[3]\); - - \grant_counter[27]\ : DFN1 - port map(D => N_135, CLK => HCLK_c, Q => - \grant_counter[27]_net_1\); - - \state_RNI1FH3[5]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_send, Y => - Request_5); - - \DMAIn.Address_RNIF4FJ[16]\ : MX2 - port map(A => \Address[16]\, B => data_address(16), S => - time_select, Y => N_963); - - \DMAIn.Address_RNIA4FJ[15]\ : MX2 - port map(A => \Address[15]\, B => data_address(15), S => - time_select, Y => N_962); - - un1_state_4_m15 : AOI1B - port map(A => N_510, B => N_509, C => - \data_counter[0]_net_1\, Y => N_16_0); - - un1_hresetn_inv_2_m54 : AX1E - port map(A => \grant_counter[19]_net_1\, B => N_52, C => - \grant_counter[20]_net_1\, Y => \un1_hresetn_inv_2_i[11]\); - - \grant_counter_RNIAQJD1[31]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_3[3]\, B => - \state_ns_i_a2_0_i_o2_2[3]\, C => - \state_ns_i_a2_0_i_o2_16[3]\, Y => - \state_ns_i_a2_0_i_o2_24[3]\); - - \grant_counter[28]\ : DFN1 - port map(D => N_137, CLK => HCLK_c, Q => - \grant_counter[28]_net_1\); - - un1_state_4_ADD_32x32_fast_I174_Y_0 : XNOR2 - port map(A => N623_0, B => \data_counter[14]_net_1\, Y => - \un1_state_4_i[17]\); - - un1_hresetn_inv_2_m46 : AX1E - port map(A => \grant_counter[15]_net_1\, B => N_44, C => - \grant_counter[16]_net_1\, Y => \un1_hresetn_inv_2_i[15]\); - - \grant_counter_RNIE9Q[22]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_13[3]\, B => - \grant_counter[23]_net_1\, C => \grant_counter[22]_net_1\, - Y => \state_ns_i_a2_0_i_o2_22[3]\); - - \DMAIn.Address[26]\ : DFN1E1C0 - port map(D => N_71, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[26]\); - - \DMAIn.Address_RNIJ3361[6]\ : MX2 - port map(A => \Address[6]\, B => data_address(6), S => - time_select, Y => N_953); - - \data_counter_RNO[0]\ : NOR3 - port map(A => \data_counter_8_i_0[0]\, B => N_339, C => - N_336, Y => N_186); - - \state_RNIQ0SJ1[3]\ : NOR3B - port map(A => HRESETn_c, B => Grant, C => N_241, Y => - un1_hresetn_inv_i_0); - - \state_RNIJBG8[0]\ : OR2B - port map(A => \state[0]_net_1\, B => Ready, Y => N_346); - - \DMAIn.Address_RNIQHRJ[20]\ : MX2 - port map(A => \Address[20]\, B => data_address(20), S => - time_select_0, Y => N_967); - - \grant_counter_RNO[0]\ : AO1C - port map(A => N_246, B => un1_hresetn_inv_i_0, C => - \grant_counter_0_0_0[0]\, Y => - \grant_counter_RNO[0]_net_1\); - - \data_counter[6]\ : DFN1C0 - port map(D => \data_counter_8[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[6]_net_1\); - - \data_counter[15]\ : DFN1C0 - port map(D => \data_counter_8[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[15]_net_1\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_3 : NOR2B - port map(A => \data_counter[20]_net_1\, B => - \data_counter[21]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_3_0); - - un1_state_4_m47 : NOR2B - port map(A => N_46, B => \data_counter[16]_net_1\, Y => - N_48_0); - - \data_counter_RNIDSMI6[22]\ : OR2B - port map(A => un1_state_5_i_o2_30, B => un1_state_5_i_o2_29, - Y => N_235); - - un1_hresetn_inv_2_m63 : NOR3C - port map(A => \grant_counter[23]_net_1\, B => N_60, C => - \grant_counter[24]_net_1\, Y => N_64); - - \data_counter_RNO[19]\ : XA1B - port map(A => \data_counter[19]_net_1\, B => N_52_0, C => - N_198_0, Y => \data_counter_8[19]\); - - \grant_counter_RNO[8]\ : XA1 - port map(A => \grant_counter[8]_net_1\, B => N_23_0, C => - N_202_0, Y => N_97); - - \data_counter[20]\ : DFN1C0 - port map(D => \data_counter_8[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[20]_net_1\); - - un1_state_4_m28_m6 : NOR3B - port map(A => m28_m6_5, B => m27_m6_0_a2_4, C => N_243, Y - => N623_0); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_13 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_5, B => - ADD_32x32_fast_I129_un1_Y_4, C => - ADD_32x32_fast_I129_un1_Y_11, Y => - ADD_32x32_fast_I129_un1_Y_13); - - \data_counter[22]\ : DFN1C0 - port map(D => \data_counter_8[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_counter[22]_net_1\); - - \data_counter_RNIQDKV[15]\ : NOR3A - port map(A => un1_state_5_i_o2_7, B => - \data_counter[15]_net_1\, C => \data_counter[14]_net_1\, - Y => un1_state_5_i_o2_19); - - \state_RNIU9K11[4]\ : AO1C - port map(A => Grant, B => \state[4]_net_1\, C => - un1_state_2_i_o2_0, Y => N_243); - - \grant_counter_RNIAPP[14]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_9[3]\, B => - \grant_counter[15]_net_1\, C => \grant_counter[14]_net_1\, - Y => \state_ns_i_a2_0_i_o2_20[3]\); - - \DMAIn.Address[27]\ : DFN1E1C0 - port map(D => N_73, CLK => HCLK_c, CLR => HRESETn_c, E => - N_154, Q => \Address[27]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(1 to 1); - status_full : out std_logic_vector(1 to 1); - sel_data : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - update_and_sel_5 : in std_logic_vector(3 downto 2); - addr_data_f1 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(1 to 1); - addr_data_vector_94 : in std_logic; - addr_data_vector_91 : in std_logic; - addr_data_vector_89 : in std_logic; - addr_data_vector_87 : in std_logic; - addr_data_vector_86 : in std_logic; - addr_data_vector_85 : in std_logic; - addr_data_vector_84 : in std_logic; - addr_data_vector_83 : in std_logic; - addr_data_vector_67 : in std_logic; - addr_data_vector_66 : in std_logic; - addr_data_vector_65 : in std_logic; - addr_data_vector_64 : in std_logic; - addr_data_vector_75 : in std_logic; - addr_data_vector_73 : in std_logic; - addr_data_vector_81 : in std_logic; - addr_data_vector_79 : in std_logic; - addr_data_vector_77 : in std_logic; - addr_data_vector_24 : out std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_16 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_18 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_5 : out std_logic; - addr_data_vector_4 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_12 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_8 : out std_logic; - N_913 : out std_logic; - N_910 : out std_logic; - N_908 : out std_logic; - N_906 : out std_logic; - N_905 : out std_logic; - N_904 : out std_logic; - N_903 : out std_logic; - N_902 : out std_logic; - N_1300 : out std_logic; - N_1299 : out std_logic; - N_1298 : out std_logic; - N_1297 : out std_logic; - N_1294 : out std_logic; - N_1292 : out std_logic; - N_1286 : out std_logic; - N_1284 : out std_logic; - N_1282 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, m40_m6_0_a2_6, m40_m6_0_a2_1, - m40_m6_0_a2_0, m40_m6_0_a2_5, m40_m6_0_a2_3, - \addr_data_vector[41]\, \addr_data_vector[54]\, - \addr_data_vector[55]\, \addr_data_vector[43]\, - m20_m7_i_4, address_0_sqmuxa, m20_m7_i_3, m20_m7_i_0, - \addr_data_vector[42]\, m20_m7_i_1, - \addr_data_vector[40]\, \addr_data_vector[39]\, - m20_m3_e_0, \un1_state_12_3_0[4]\, \update_r_i[0]\, - \update_r[1]_net_1\, address_0_sqmuxa_0, \state[3]_net_1\, - un3_update_r, un1_state_5_i_0, \state[4]_net_1\, - \state_ns_i_0[3]\, N_131, address_7_31_m6_e_3, - \addr_data_vector[57]\, \addr_data_vector[62]\, - address_7_31_m6_e_1, address_7_31_m6_e_2, - \addr_data_vector[59]\, m36_m6_0_a2_4_6, - \addr_data_vector[51]\, m36_m6_0_a2_4_4, m36_m6_0_a2_4_5, - \addr_data_vector[47]\, m36_m6_0_a2_4_2, - \addr_data_vector[45]\, \addr_data_vector[53]\, - \addr_data_vector[52]\, \addr_data_vector[49]\, - \un1_address[6]\, \addr_data_vector[38]\, N_5_0, N_116, - N_129, \state[1]_net_1\, \state_ns[0]\, N_125, N_124, - \un1_state_12_2[4]\, N_110, \state[2]_net_1\, state7, - m36_m6_0_a2_4_i, \address_RNO_2[31]_net_1\, N_41, N_13_0, - m20_m3_e, N_69, m20_N_17_i_0, m20_m7_i_o5, - \address_7[31]\, \address_RNO_0[31]_net_1\, - \address_RNO_1[31]_net_1\, \addr_data_vector[63]\, N_37_0, - \addr_data_vector[44]\, N_2, \addr_data_vector[34]\, - N_15_0_i_0, N_16_0, N_17_0_i_0, N_18_0, N_20_0_i_0, - N_22_0_i_0, N_24_0, N_26_0_i_0, \addr_data_vector[46]\, - N_27_0, N_28_0_i_0, \addr_data_vector[48]\, N_30_0_i_0, - N_31_0, \un1_address[19]\, \addr_data_vector[50]\, N_34_0, - \un1_address[20]\, \un1_address[23]\, N_40_i_0, N_43, - \addr_data_vector[56]\, N_45, \addr_data_vector[58]\, - N_46, \addr_data_vector[60]\, N_50_i_0, - \addr_data_vector[35]\, N_51_i_0, \addr_data_vector[36]\, - N_52_i_0, \addr_data_vector[37]\, N_1_i_0, N_54_0_i_0, - N_55_0_i_0, \un1_address[18]\, \un1_address[21]\, - \un1_address[22]\, \un1_address[24]\, \un1_address[25]\, - \un1_address[26]\, \un1_address[27]\, \un1_address[28]\, - \un1_address[29]\, \addr_data_vector[61]\, - \un1_address[30]\, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[15]\, \address_7[16]\, - \address_7[17]\, \state[0]_net_1\, \address_7[18]\, - \address_7[19]\, \address_7[20]\, \address_7[21]\, - \address_7[22]\, \address_7[23]\, \address_7[24]\, - \address_7[25]\, \address_7[26]\, \address_7[27]\, - \address_7[28]\, \address_7[29]\, \address_7[30]\, - N_56_0_i_0, un1_state_9, \nb_send_5[0]\, \nb_send_5[1]\, - \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, N_127, N_113, \state_ns[2]\, - un1_state_11, \address_7[14]\, \addr_data_vector[32]\, - \addr_data_vector[33]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_24 <= \addr_data_vector[56]\; - addr_data_vector_31 <= \addr_data_vector[63]\; - addr_data_vector_16 <= \addr_data_vector[48]\; - addr_data_vector_14 <= \addr_data_vector[46]\; - addr_data_vector_18 <= \addr_data_vector[50]\; - addr_data_vector_26 <= \addr_data_vector[58]\; - addr_data_vector_29 <= \addr_data_vector[61]\; - addr_data_vector_28 <= \addr_data_vector[60]\; - addr_data_vector_5 <= \addr_data_vector[37]\; - addr_data_vector_4 <= \addr_data_vector[36]\; - addr_data_vector_6 <= \addr_data_vector[38]\; - addr_data_vector_12 <= \addr_data_vector[44]\; - addr_data_vector_10 <= \addr_data_vector[42]\; - addr_data_vector_7 <= \addr_data_vector[39]\; - addr_data_vector_8 <= \addr_data_vector[40]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[48]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[42]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[62]\); - - un1_address_m20_m7_i_0 : NOR2B - port map(A => \addr_data_vector[43]\, B => - \addr_data_vector[39]\, Y => m20_m7_i_0); - - un1_address_m45 : NOR2A - port map(A => \addr_data_vector[60]\, B => N_45, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f1(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : XNOR2 - port map(A => N_43, B => \addr_data_vector[58]\, Y => - \un1_address[26]\); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[58]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[52]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3B - port map(A => N_129, B => \state[2]_net_1\, C => - status_full_ack(1), Y => N_127); - - \state_RNI3CSP8[3]\ : OR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1C - port map(A => \addr_data_vector[36]\, B => N_69, C => - \addr_data_vector[37]\, Y => N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[44]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f1(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m36_m6_0_a2_4_4 : NOR3C - port map(A => \addr_data_vector[45]\, B => - \addr_data_vector[53]\, C => \addr_data_vector[52]\, Y - => m36_m6_0_a2_4_4); - - un1_address_m36_m6_0_a2_4 : OR2B - port map(A => m36_m6_0_a2_4_6, B => m36_m6_0_a2_4_5, Y => - m36_m6_0_a2_4_i); - - un1_address_m19 : AX1C - port map(A => \addr_data_vector[42]\, B => N_18_0, C => - \addr_data_vector[43]\, Y => N_20_0_i_0); - - \address_RNI68OA[9]\ : MX2C - port map(A => \addr_data_vector[41]\, B => - addr_data_vector_73, S => sel_data_0(1), Y => N_1292); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[54]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f1(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[34]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f1(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f1(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_110, Q => status_full_err(1)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f1(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[37]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[47]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[45]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[51]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[57]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[55]\); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[39]\, C => - \addr_data_vector[40]\, Y => N_15_0_i_0); - - un1_address_m29 : AX1C - port map(A => \addr_data_vector[48]\, B => N_27_0, C => - \addr_data_vector[49]\, Y => N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - un1_address_m36_m6_0_a2 : NOR3B - port map(A => \addr_data_vector[44]\, B => m20_N_17_i_0, C - => m36_m6_0_a2_4_i, Y => N_37_0); - - \address_RNO_2[31]\ : NOR3B - port map(A => address_7_31_m6_e_3, B => address_7_31_m6_e_2, - C => \state_0[0]_net_1\, Y => \address_RNO_2[31]_net_1\); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[61]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[50]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f1(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f1(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f1(0), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - \addr_data_vector[32]\); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m36_m6_0_a2_4_2 : NOR2B - port map(A => \addr_data_vector[48]\, B => - \addr_data_vector[49]\, Y => m36_m6_0_a2_4_2); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f1(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[36]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[60]\); - - un1_address_m1 : NOR3A - port map(A => \addr_data_vector[34]\, B => - \un1_state_12_2[4]\, C => \un1_state_12_3_0[4]\, Y => N_2); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - un1_address_m17 : NOR2A - port map(A => \addr_data_vector[41]\, B => N_16_0, Y => - N_18_0); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3B - port map(A => N_131, B => N_129, C => \state[3]_net_1\, Y - => N_125); - - \address_RNO_1[31]\ : AX1E - port map(A => \addr_data_vector[56]\, B => N_41, C => - \addr_data_vector[63]\, Y => \address_RNO_1[31]_net_1\); - - un1_address_m20_m7_i_4 : OA1A - port map(A => address_0_sqmuxa, B => \addr_data_vector[38]\, - C => m20_m7_i_3, Y => m20_m7_i_4); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR3 - port map(A => address_0_sqmuxa, B => \addr_data_vector[38]\, - C => N_5_0, Y => \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f1(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[7]_net_1\); - - un1_address_m40_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[40]\, B => - \addr_data_vector[39]\, C => m40_m6_0_a2_3, Y => - m40_m6_0_a2_5); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f1(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address_RNIFA45[30]\ : MX2C - port map(A => \addr_data_vector[62]\, B => - addr_data_vector_94, S => sel_data(1), Y => N_913); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[46]\); - - \state_RNO[1]\ : OA1C - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - \address_RNIJ245[25]\ : MX2C - port map(A => \addr_data_vector[57]\, B => - addr_data_vector_89, S => sel_data(1), Y => N_908); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f1(14), S => - \state[0]_net_1\, Y => \address_7[14]\); - - un1_address_m20_m3_e_0 : NOR2B - port map(A => \addr_data_vector[36]\, B => - \addr_data_vector[37]\, Y => m20_m3_e_0); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[56]\); - - un1_address_m27 : XOR2 - port map(A => N_27_0, B => \addr_data_vector[48]\, Y => - N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \address_RNO_0[31]\ : MX2C - port map(A => \addr_data_vector[63]\, B => addr_data_f1(31), - S => \state_0[0]_net_1\, Y => \address_RNO_0[31]_net_1\); - - \address_RNILQ35[19]\ : MX2C - port map(A => \addr_data_vector[51]\, B => - addr_data_vector_83, S => sel_data(1), Y => N_902); - - un1_address_m60 : AX1C - port map(A => \addr_data_vector[56]\, B => N_41, C => - \addr_data_vector[57]\, Y => \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - un1_address_m36_m6_0_a2_4_5 : NOR3C - port map(A => \addr_data_vector[47]\, B => - \addr_data_vector[46]\, C => m36_m6_0_a2_4_2, Y => - m36_m6_0_a2_4_5); - - un1_address_m30 : NOR3C - port map(A => \addr_data_vector[48]\, B => N_27_0, C => - \addr_data_vector[49]\, Y => N_31_0); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[41]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3C - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[40]\); - - un1_address_m50 : XOR2 - port map(A => N_69, B => \addr_data_vector[36]\, Y => - N_51_i_0); - - un1_address_m39 : AX1B - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, C => \addr_data_vector[34]\, Y => - N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : NOR2A - port map(A => update_and_sel_5(2), B => update_and_sel_5(3), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f1(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f1(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f1(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - un1_address_m40_m6_0_a2_3 : NOR2B - port map(A => \addr_data_vector[41]\, B => - \addr_data_vector[42]\, Y => m40_m6_0_a2_3); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1C - port map(A => \addr_data_vector[54]\, B => N_37_0, C => - \addr_data_vector[55]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa, C => - \addr_data_vector[38]\, Y => N_13_0); - - un1_address_m59 : XOR2 - port map(A => N_41, B => \addr_data_vector[56]\, Y => - \un1_address[24]\); - - \address_RNIB245[21]\ : MX2C - port map(A => \addr_data_vector[53]\, B => - addr_data_vector_85, S => sel_data(1), Y => N_904); - - \update_r[0]\ : DFN1P0 - port map(D => update_and_sel_5(2), CLK => HCLK_c, PRE => - HRESETn_c, Q => \update_r_i[0]\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => m40_m6_0_a2_1, B => m40_m6_0_a2_0, C => - m40_m6_0_a2_5, Y => m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f1(17), S => - \state[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f1(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[39]\, B => - \addr_data_vector[40]\, C => N_13_0, Y => N_16_0); - - un1_address_m58 : XOR2 - port map(A => N_37_0, B => \addr_data_vector[54]\, Y => - \un1_address[22]\); - - \state_RNI40SU8[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - un1_address_m26 : NOR3C - port map(A => \addr_data_vector[46]\, B => N_24_0, C => - \addr_data_vector[47]\, Y => N_27_0); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f1(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address_RNO_4[31]\ : NOR2B - port map(A => \addr_data_vector[60]\, B => - \addr_data_vector[61]\, Y => address_7_31_m6_e_2); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[35]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XOR2 - port map(A => N_46, B => \addr_data_vector[61]\, Y => - \un1_address[29]\); - - un1_address_m34 : XOR2 - port map(A => N_34_0, B => \addr_data_vector[52]\, Y => - \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f1(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \address_RNI9245[20]\ : MX2C - port map(A => \addr_data_vector[52]\, B => - addr_data_vector_84, S => sel_data(1), Y => N_903); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(1), B => N_131, Y => - \state_ns_i_0[3]\); - - \state_RNITJCD[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : AX1C - port map(A => \addr_data_vector[44]\, B => m20_N_17_i_0, C - => \addr_data_vector[45]\, Y => N_55_0_i_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[39]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - un1_address_m25 : AX1C - port map(A => \addr_data_vector[46]\, B => N_24_0, C => - \addr_data_vector[47]\, Y => N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[3]_net_1\); - - \address_RNIG894[15]\ : MX2C - port map(A => \addr_data_vector[47]\, B => - addr_data_vector_79, S => sel_data_0(1), Y => N_1284); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_5(3), CLK => HCLK_c, CLR => - HRESETn_c, Q => \update_r[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - \update_r_RNI1KV4_0[0]\ : OR2 - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => \un1_state_12_3_0[4]\); - - un1_address_m57 : AX1C - port map(A => \addr_data_vector[52]\, B => N_34_0, C => - \addr_data_vector[53]\, Y => \un1_address[21]\); - - un1_address_m20_m7_i_1 : NOR2B - port map(A => \addr_data_vector[40]\, B => - \addr_data_vector[41]\, Y => m20_m7_i_1); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - un1_address_m40_m6_0_a2 : NOR3A - port map(A => m40_m6_0_a2_6, B => m36_m6_0_a2_4_i, C => - N_13_0, Y => N_41); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f1(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : XOR2 - port map(A => N_2, B => \addr_data_vector[35]\, Y => - N_50_i_0); - - \address_RNIQNMA[3]\ : MX2C - port map(A => \addr_data_vector[35]\, B => - addr_data_vector_67, S => sel_data_0(1), Y => N_1300); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[41]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f1(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - \address_RNIKVLA[0]\ : MX2C - port map(A => \addr_data_vector[32]\, B => - addr_data_vector_64, S => sel_data_0(1), Y => N_1297); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNI8894[11]\ : MX2C - port map(A => \addr_data_vector[43]\, B => - addr_data_vector_75, S => sel_data_0(1), Y => N_1294); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f1(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[38]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - un1_address_m23 : NOR3C - port map(A => \addr_data_vector[44]\, B => m20_N_17_i_0, C - => \addr_data_vector[45]\, Y => N_24_0); - - status_full_err_RNO : AO1 - port map(A => \state[2]_net_1\, B => N_129, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f1(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address_RNIC894[13]\ : MX2C - port map(A => \addr_data_vector[45]\, B => - addr_data_vector_77, S => sel_data_0(1), Y => N_1282); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[43]\); - - un1_address_m20_m3_e : OR2B - port map(A => m20_m3_e_0, B => N_69, Y => m20_m3_e); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[63]\); - - un1_address_m36_m6_0_a2_4_6 : NOR3C - port map(A => \addr_data_vector[51]\, B => - \addr_data_vector[50]\, C => m36_m6_0_a2_4_4, Y => - m36_m6_0_a2_4_6); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : XOR2 - port map(A => N_31_0, B => \addr_data_vector[50]\, Y => - \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f1(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - un1_address_m44 : OR3B - port map(A => \addr_data_vector[58]\, B => - \addr_data_vector[59]\, C => N_43, Y => N_45); - - \address_RNIOFMA[2]\ : MX2C - port map(A => \addr_data_vector[34]\, B => - addr_data_vector_66, S => sel_data_0(1), Y => N_1299); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f1(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f1(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[53]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - un1_address_m62 : AX1 - port map(A => N_43, B => \addr_data_vector[58]\, C => - \addr_data_vector[59]\, Y => \un1_address[27]\); - - un1_address_m32 : AX1C - port map(A => \addr_data_vector[50]\, B => N_31_0, C => - \addr_data_vector[51]\, Y => \un1_address[19]\); - - un1_address_m12_e : OR3C - port map(A => \addr_data_vector[36]\, B => N_69, C => - \addr_data_vector[37]\, Y => N_5_0); - - \address_RNO_5[31]\ : NOR2B - port map(A => \addr_data_vector[58]\, B => - \addr_data_vector[59]\, Y => address_7_31_m6_e_1); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => HCLK_c, CLR => HRESETn_c, Q => - \state[1]_net_1\); - - \address_RNIF245[23]\ : MX2C - port map(A => \addr_data_vector[55]\, B => - addr_data_vector_87, S => sel_data(1), Y => N_906); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[49]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - \state_RNI40SU8_0[3]\ : OR2B - port map(A => address_0_sqmuxa_0, B => state7, Y => - address_0_sqmuxa); - - un1_address_m65 : AX1C - port map(A => \addr_data_vector[61]\, B => N_46, C => - \addr_data_vector[62]\, Y => \un1_address[30]\); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[39]\, Y => - N_1_i_0); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[59]\); - - \state_RNO[3]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : XOR2 - port map(A => m20_N_17_i_0, B => \addr_data_vector[44]\, Y - => N_22_0_i_0); - - un1_address_m20_m7_i_3 : NOR3C - port map(A => m20_m7_i_0, B => \addr_data_vector[42]\, C - => m20_m7_i_1, Y => m20_m7_i_3); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : XOR2 - port map(A => N_24_0, B => \addr_data_vector[46]\, Y => - N_56_0_i_0); - - \address_RNO[31]\ : MX2C - port map(A => \address_RNO_0[31]_net_1\, B => - \address_RNO_1[31]_net_1\, S => \address_RNO_2[31]_net_1\, - Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m20_m7_i_o5 : OR2A - port map(A => \addr_data_vector[38]\, B => address_0_sqmuxa, - Y => m20_m7_i_o5); - - un1_address_m10_e : NOR2B - port map(A => N_2, B => \addr_data_vector[35]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f1(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - \address_RNIK894[17]\ : MX2C - port map(A => \addr_data_vector[49]\, B => - addr_data_vector_81, S => sel_data_0(1), Y => N_1286); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \state_RNIEABE[1]\ : NOR2A - port map(A => status_full_ack(1), B => N_131, Y => N_118); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f1(1), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - \addr_data_vector[33]\); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_11, Q => status_full(1)); - - \update_r_RNI1KV4[0]\ : OR2B - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => un3_update_r); - - un1_address_m63 : XNOR2 - port map(A => N_45, B => \addr_data_vector[60]\, Y => - \un1_address[28]\); - - un1_address_m33 : NOR3C - port map(A => \addr_data_vector[50]\, B => N_31_0, C => - \addr_data_vector[51]\, Y => N_34_0); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNID245[22]\ : MX2C - port map(A => \addr_data_vector[54]\, B => - addr_data_vector_86, S => sel_data(1), Y => N_905); - - \address_RNIM7MA[1]\ : MX2C - port map(A => \addr_data_vector[33]\, B => - addr_data_vector_65, S => sel_data_0(1), Y => N_1298); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f1(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : XOR2 - port map(A => N_18_0, B => \addr_data_vector[42]\, Y => - N_54_0_i_0); - - un1_address_m40_m6_0_a2_0 : NOR2B - port map(A => \addr_data_vector[55]\, B => - \addr_data_vector[43]\, Y => m40_m6_0_a2_0); - - un1_address_m40_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[44]\, B => - \addr_data_vector[54]\, Y => m40_m6_0_a2_1); - - \address_RNO_3[31]\ : NOR3C - port map(A => \addr_data_vector[57]\, B => - \addr_data_vector[62]\, C => address_7_31_m6_e_1, Y => - address_7_31_m6_e_3); - - \state_RNI14MB[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => un3_update_r, Y => - address_0_sqmuxa_0); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[3]_net_1\, C - => \state[2]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f1(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un1_address_m20_m7_i : AOI1B - port map(A => m20_m7_i_o5, B => m20_m3_e, C => m20_m7_i_4, - Y => m20_N_17_i_0); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - un1_address_m42 : OR3C - port map(A => \addr_data_vector[56]\, B => N_41, C => - \addr_data_vector[57]\, Y => N_43); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - \address_RNIN245[27]\ : MX2C - port map(A => \addr_data_vector[59]\, B => - addr_data_vector_91, S => sel_data(1), Y => N_910); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_dma_send_1word is - - port( Lock : out std_logic; - Request : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - un1_time_send_ok : out std_logic; - time_select : in std_logic; - Store : in std_logic; - N_1012 : out std_logic; - Ready : in std_logic; - Fault : in std_logic; - time_send : in std_logic; - Grant : in std_logic - ); - -end lpp_dma_send_1word; - -architecture DEF_ARCH of lpp_dma_send_1word is - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un1_state_4_i_0, \state[1]_net_1\, \state[3]_net_1\, - \state_ns_i_a4_0[0]\, \state[0]_net_1\, \state[2]_net_1\, - un1_state_2, N_69, \state[4]_net_1\, N_66, N_58, N_60, - \state_ns[1]\, Request_4, N_61, Store_0, \state_ns[2]\, - \state_RNO[4]_net_1\, time_send_ok, time_send_ko, - \state_ns[3]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \state_RNI4AM7[1]\ : OR2 - port map(A => \state[1]_net_1\, B => \state[3]_net_1\, Y - => un1_state_4_i_0); - - \state[1]\ : DFN1C0 - port map(D => \state_ns[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - \state_RNIFCT8[4]\ : NOR2B - port map(A => time_send, B => \state[4]_net_1\, Y => - Request_4); - - GND_i_0 : GND - port map(Y => GND_0); - - \state_RNIAJH31[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => Grant, Y => N_66); - - \state_RNI6OUR[2]\ : NOR2A - port map(A => \state[2]_net_1\, B => N_61, Y => N_69); - - un1_state_2_0_o3 : NOR2A - port map(A => Fault, B => Ready, Y => N_61); - - \state[4]\ : DFN1P0 - port map(D => \state_RNO[4]_net_1\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \DMAIn.Request\ : DFN1E1C0 - port map(D => Request_4, CLK => HCLK_c, CLR => HRESETn_c, E - => un1_state_2, Q => Request); - - VCC_i : VCC - port map(Y => \VCC\); - - \state_RNO[4]\ : OA1C - port map(A => time_send, B => \state_ns_i_a4_0[0]\, C => - N_58, Y => \state_RNO[4]_net_1\); - - \state_RNIKGB32[4]\ : OR3 - port map(A => N_69, B => \state[4]_net_1\, C => N_66, Y => - un1_state_2); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - send_ok : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_58, Q => time_send_ok); - - \state_RNO[1]\ : NOR2A - port map(A => \state[2]_net_1\, B => Fault, Y => - \state_ns[3]\); - - GND_i : GND - port map(Y => \GND\); - - \DMAIn.Store_RNIVI9A\ : MX2 - port map(A => Store, B => Store_0, S => time_select, Y => - N_1012); - - \state_RNO_0[4]\ : OR2 - port map(A => \state[0]_net_1\, B => \state[2]_net_1\, Y - => \state_ns_i_a4_0[0]\); - - \DMAIn.Store\ : DFN1E1C0 - port map(D => \state[4]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_2, Q => Store_0); - - \DMAIn.Lock\ : DFN1E1C0 - port map(D => time_send, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[4]_net_1\, Q => Lock); - - \state_RNO[2]\ : AO1 - port map(A => \state[2]_net_1\, B => N_61, C => N_66, Y => - \state_ns[2]\); - - \state_ns_i_o3[0]\ : NOR2B - port map(A => Ready, B => Fault, Y => N_60); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO[3]\ : AO1A - port map(A => Grant, B => \state[3]_net_1\, C => Request_4, - Y => \state_ns[1]\); - - send_ko_RNI8BV9 : OR2 - port map(A => time_send_ok, B => time_send_ko, Y => - un1_time_send_ok); - - send_ko : DFN1E0C0 - port map(D => \state[0]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_58, Q => time_send_ko); - - \state[0]\ : DFN1C0 - port map(D => \state[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[0]_net_1\); - - \state_RNIA2L31[2]\ : AO1A - port map(A => N_60, B => \state[2]_net_1\, C => - un1_state_4_i_0, Y => N_58); - - \state[3]\ : DFN1C0 - port map(D => \state_ns[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(3 to 3); - status_full : out std_logic_vector(3 to 3); - sel_data : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - update_and_sel_1 : in std_logic_vector(7 downto 6); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(3 to 3); - addr_data_vector_61 : out std_logic; - addr_data_vector_60 : out std_logic; - addr_data_vector_27 : in std_logic; - addr_data_vector_25 : in std_logic; - addr_data_vector_24 : in std_logic; - addr_data_vector_22 : in std_logic; - addr_data_vector_20 : in std_logic; - addr_data_vector_0 : in std_logic; - addr_data_vector_6 : in std_logic; - addr_data_vector_4 : in std_logic; - addr_data_vector_3 : in std_logic; - addr_data_vector_2 : in std_logic; - addr_data_vector_1 : in std_logic; - addr_data_vector_14 : in std_logic; - addr_data_vector_12 : in std_logic; - addr_data_vector_10 : in std_logic; - addr_data_vector_8 : in std_logic; - addr_data_vector_63 : out std_logic; - addr_data_vector_90 : out std_logic; - addr_data_vector_87 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_62 : out std_logic; - addr_data_vector_69 : out std_logic; - addr_data_vector_73 : out std_logic; - addr_data_vector_71 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_83 : out std_logic; - addr_data_vector_75 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_81 : out std_logic; - N_914 : out std_logic; - N_912 : out std_logic; - N_911 : out std_logic; - N_909 : out std_logic; - N_907 : out std_logic; - N_1301 : out std_logic; - N_1293 : out std_logic; - N_1291 : out std_logic; - N_1290 : out std_logic; - N_1289 : out std_logic; - N_1288 : out std_logic; - N_1287 : out std_logic; - N_1285 : out std_logic; - N_1283 : out std_logic; - N_1281 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, \state_RNIKABE[1]_net_1\, N_38, - \nb_send[1]_net_1\, \nb_send[0]_net_1\, N_30, - \nb_send[3]_net_1\, \DWACT_FINC_E[0]\, N_7, - \nb_send[8]_net_1\, \DWACT_FINC_E[4]\, m40_m6_0_a2_7, - m40_m6_0_a2_2, m40_m6_0_a2_1, m40_m6_0_a2_6, - m40_m6_0_a2_4, \addr_data_vector[114]\, - \addr_data_vector[112]\, m24_m5_0_a2_5, - \addr_data_vector[106]\, m24_m5_0_a2_3, m24_m5_0_a2_4, - \addr_data_vector[103]\, \addr_data_vector[110]\, - m24_m5_0_a2_1, \addr_data_vector[108]\, - \addr_data_vector[104]\, \un1_state_12_3_0[4]\, - \update_r_i[0]\, \update_r[1]_net_1\, un1_state_5_i_0, - \state[4]_net_1\, \state[3]_net_1\, \state_ns_i_0[3]\, - N_131, \un1_state_12[4]\, \un1_state_12_2[4]\, - \un1_address[6]\, address_0_sqmuxa, - \addr_data_vector[102]\, N_5_0, \state_RNO[1]_net_1\, - N_129, \state[1]_net_1\, \state_ns[0]\, N_125, N_124, - N_110, \state[2]_net_1\, state7, un3_update_r, N_25_0_i_0, - N_13_0, N_15_0_i_0, N_16_0, N_17_0_i_0, - \addr_data_vector[105]\, N_19_0, N_20_0_i_0, - \addr_data_vector[107]\, N_22_0_i_0, N_23_0, N_26_0_i_0, - \addr_data_vector[111]\, N_28_0_i_0, N_29_0, N_30_0_i_0, - \addr_data_vector[113]\, N_32_0, N_33_0, - \addr_data_vector[115]\, N_35_0, \addr_data_vector[116]\, - N_36_0, N_37_0, \addr_data_vector[117]\, N_39, - \addr_data_vector[118]\, \addr_data_vector[119]\, - N_40_i_0, N_42, \addr_data_vector[120]\, N_44, - \addr_data_vector[122]\, N_46, \addr_data_vector[124]\, - N_47, \addr_data_vector[125]\, N_49_i_0, - \addr_data_vector[127]\, N_50_i_0, \addr_data_vector[98]\, - N_51_i_0, N_69, \addr_data_vector[100]\, N_52_i_0, - \addr_data_vector[101]\, N_1_i_0, N_54_0_i_0, N_55_0_i_0, - \addr_data_vector[109]\, N_57_0, N_58_0, N_59_0, N_60_0, - N_61_0, \addr_data_vector[121]\, N_62, N_63_0, - \addr_data_vector[123]\, N_64_0, N_65_0, N_66_0, - \addr_data_vector[126]\, \addr_data_vector[99]\, - \address_7[2]\, \address_7[3]\, \address_7[4]\, - \address_7[5]\, \address_7[6]\, \address_7[7]\, - \address_7[8]\, \address_7[9]\, \address_7[10]\, - \address_7[11]\, \address_7[12]\, \address_7[13]\, - \address_7[15]\, \address_7[16]\, \address_7[17]\, - \address_7[18]\, \address_7[19]\, \state[0]_net_1\, - \address_7[20]\, \address_7[21]\, \address_7[22]\, - \address_7[23]\, \address_7[24]\, \address_7[25]\, - \address_7[26]\, \address_7[27]\, \address_7[28]\, - \address_7[29]\, \address_7[30]\, \address_7[31]\, - N_56_0_i_0, un1_state_9, \nb_send_5[0]\, \nb_send_5[1]\, - I_5_19, \nb_send_5[2]\, I_9_19, \nb_send_5[3]\, I_13_19, - \nb_send_5[4]\, I_20_11, \nb_send_5[5]\, I_24_3, - \nb_send_5[6]\, I_31_4, \nb_send_5[7]\, I_38_3, - \nb_send_5[8]\, I_45_3, \nb_send_5[9]\, I_52_3, - \nb_send_5[10]\, I_56_3, N_127, \state_RNO_0[3]\, - \state_ns[2]\, un1_state_11, \address_7[14]\, - \nb_send[2]_net_1\, \nb_send[4]_net_1\, - \nb_send[5]_net_1\, \nb_send[6]_net_1\, - \nb_send[7]_net_1\, \nb_send[9]_net_1\, - \nb_send[10]_net_1\, N_4, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[3]\, N_12, N_17, N_22, \DWACT_FINC_E[1]\, - N_27, N_35, \DWACT_COMP0_E[1]\, \DWACT_COMP0_E[2]\, - \DWACT_COMP0_E[0]\, \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_1, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_63 <= \addr_data_vector[99]\; - addr_data_vector_90 <= \addr_data_vector[126]\; - addr_data_vector_87 <= \addr_data_vector[123]\; - addr_data_vector_85 <= \addr_data_vector[121]\; - addr_data_vector_62 <= \addr_data_vector[98]\; - addr_data_vector_69 <= \addr_data_vector[105]\; - addr_data_vector_73 <= \addr_data_vector[109]\; - addr_data_vector_71 <= \addr_data_vector[107]\; - addr_data_vector_77 <= \addr_data_vector[113]\; - addr_data_vector_79 <= \addr_data_vector[115]\; - addr_data_vector_82 <= \addr_data_vector[118]\; - addr_data_vector_83 <= \addr_data_vector[119]\; - addr_data_vector_75 <= \addr_data_vector[111]\; - addr_data_vector_80 <= \addr_data_vector[116]\; - addr_data_vector_81 <= \addr_data_vector[117]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[112]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[106]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNIKABE[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[126]\); - - un1_address_m45 : OR3B - port map(A => \addr_data_vector[123]\, B => - \addr_data_vector[124]\, C => N_44, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => N_62, B => addr_data_f3(26), S => - \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => I_52_3, B => nb_burst_available(9), C => N_31, - Y => N_36); - - un1_address_m61 : AX1 - port map(A => N_42, B => \addr_data_vector[121]\, C => - \addr_data_vector[122]\, Y => N_62); - - un1_address_m31 : OR3B - port map(A => \addr_data_vector[113]\, B => - \addr_data_vector[114]\, C => N_29_0, Y => N_32_0); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[122]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[116]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => I_20_11, B => nb_burst_available(4), C => - I_24_3, Y => \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3B - port map(A => N_129, B => \state[2]_net_1\, C => - status_full_ack(3), Y => N_127); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1C - port map(A => \addr_data_vector[100]\, B => N_69, C => - \addr_data_vector[101]\, Y => N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[108]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => I_52_3, B => nb_burst_available(9), C => N_29, - Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => N_65_0, B => addr_data_f3(29), S => - \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XOR2 - port map(A => N_19_0, B => \addr_data_vector[107]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[118]\); - - \address_RNO[23]\ : MX2 - port map(A => N_39, B => addr_data_f3(23), S => - \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[98]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => I_13_19); - - un1_address_m43 : OR3B - port map(A => \addr_data_vector[121]\, B => - \addr_data_vector[122]\, C => N_42, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => N_60_0, B => addr_data_f3(24), S => - \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f3(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_110, Q => status_full_err(3)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : NOR3C - port map(A => \addr_data_vector[105]\, B => N_16_0, C => - \addr_data_vector[106]\, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => I_5_19, B => state7, Y => \nb_send_5[1]\); - - \address_RNIA894[12]\ : MX2C - port map(A => addr_data_vector_8, B => - \addr_data_vector[108]\, S => sel_data_0(1), Y => N_1281); - - \address_RNI40OA[8]\ : MX2C - port map(A => addr_data_vector_4, B => - \addr_data_vector[104]\, S => sel_data_0(1), Y => N_1291); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => I_31_4); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f3(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[101]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => I_38_3, B => nb_burst_available(7), Y => - \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[111]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[109]\); - - \update_r_RNI5KV4[0]\ : OR2B - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => un3_update_r); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => I_52_3, B => state7, Y => \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[115]\); - - \address_RNII894[16]\ : MX2C - port map(A => addr_data_vector_12, B => - \addr_data_vector[112]\, S => sel_data_0(1), Y => N_1285); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[121]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address_RNIL245[26]\ : MX2C - port map(A => addr_data_vector_22, B => - \addr_data_vector[122]\, S => sel_data(1), Y => N_909); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[119]\); - - un1_address_m14 : AX1C - port map(A => \addr_data_vector[103]\, B => N_13_0, C => - \addr_data_vector[104]\, Y => N_15_0_i_0); - - un1_address_m29 : XNOR2 - port map(A => N_29_0, B => \addr_data_vector[113]\, Y => - N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => I_31_4, Y => - N_30_0); - - \address_RNIH245[24]\ : MX2C - port map(A => addr_data_vector_20, B => - \addr_data_vector[120]\, S => sel_data(1), Y => N_907); - - \state_RNIKABE[1]\ : NOR2A - port map(A => status_full_ack(3), B => N_131, Y => - \state_RNIKABE[1]_net_1\); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[125]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[114]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => I_31_4, B => state7, Y => \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => N_58_0, B => addr_data_f3(21), S => - \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f3(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f3(0), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - addr_data_vector_60); - - un1_address_m28 : OR3B - port map(A => \addr_data_vector[111]\, B => - \addr_data_vector[112]\, C => N_25_0_i_0, Y => N_29_0); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : OR3B - port map(A => m40_m6_0_a2_7, B => \addr_data_vector[120]\, - C => N_25_0_i_0, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => N_63_0, B => addr_data_f3(27), S => - \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[100]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[124]\); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \nb_send_RNO[2]\ : NOR2B - port map(A => I_9_19, B => state7, Y => \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3B - port map(A => N_131, B => N_129, C => \state[3]_net_1\, Y - => N_125); - - \address_RNI6894[10]\ : MX2C - port map(A => addr_data_vector_6, B => - \addr_data_vector[106]\, S => sel_data_0(1), Y => N_1293); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => I_9_19, B => nb_burst_available(2), Y => - \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => I_38_3, B => state7, Y => \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => I_24_3); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XNOR3 - port map(A => address_0_sqmuxa, B => - \addr_data_vector[102]\, C => N_5_0, Y => - \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => N_33_0, B => addr_data_f3(19), S => - \state[0]_net_1\, Y => \address_7[19]\); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f3(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[110]\); - - \state_RNO[1]\ : OA1C - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => \state_RNO[1]_net_1\); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[0]_net_1\); - - \state_RNILNSP8[3]\ : OR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => I_5_19, Y => - \ACT_LT4_E[2]\); - - un1_address_m40_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[111]\, B => - \addr_data_vector[119]\, C => \addr_data_vector[118]\, Y - => m40_m6_0_a2_4); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => I_13_19, Y => - \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f3(14), S => - \state[0]_net_1\, Y => \address_7[14]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => I_13_19, B => state7, Y => \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_1, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[120]\); - - un1_address_m27 : AX1 - port map(A => N_25_0_i_0, B => \addr_data_vector[111]\, C - => \addr_data_vector[112]\, Y => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[121]\, Y => - N_61_0); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XOR2 - port map(A => N_16_0, B => \addr_data_vector[105]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => I_45_3); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => I_45_3, B => state7, Y => \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => I_24_3, Y => - \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3C - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => I_52_3, B => nb_burst_available(9), Y => - \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[104]\); - - un1_address_m40_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[114]\, B => - \addr_data_vector[115]\, Y => m40_m6_0_a2_2); - - un1_address_m50 : XOR2 - port map(A => N_69, B => \addr_data_vector[100]\, Y => - N_51_i_0); - - un1_address_m39 : XOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[98]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => I_56_3, B => nb_burst_available(10), Y => - N_35_1); - - \state_ns_i_a2[1]\ : NOR2A - port map(A => update_and_sel_1(6), B => update_and_sel_1(7), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f3(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \update_r_RNIQBSU8[0]\ : NOR2 - port map(A => \un1_state_12_3_0[4]\, B => - \un1_state_12_2[4]\, Y => \un1_state_12[4]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => N_64_0, B => addr_data_f3(28), S => - \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f3(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => I_38_3, C => - N_30_0, Y => N_32); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => I_24_3, B => nb_burst_available(5), Y => - \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => I_31_4, B => nb_burst_available(6), Y => - \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1C - port map(A => \addr_data_vector[118]\, B => N_37_0, C => - \addr_data_vector[119]\, Y => N_39); - - un1_address_m12 : AO13 - port map(A => address_0_sqmuxa, B => - \addr_data_vector[102]\, C => N_5_0, Y => N_13_0); - - un1_address_m59 : AX1 - port map(A => N_25_0_i_0, B => m40_m6_0_a2_7, C => - \addr_data_vector[120]\, Y => N_60_0); - - \update_r[0]\ : DFN1P0 - port map(D => update_and_sel_1(6), CLK => HCLK_c, PRE => - HRESETn_c, Q => \update_r_i[0]\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => I_5_19); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[117]\, B => - \addr_data_vector[116]\, C => m40_m6_0_a2_4, Y => - m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f3(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f3(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : NOR3C - port map(A => \addr_data_vector[103]\, B => N_13_0, C => - \addr_data_vector[104]\, Y => N_16_0); - - un1_address_m58 : XOR2 - port map(A => N_37_0, B => \addr_data_vector[118]\, Y => - N_59_0); - - \address_RNIU7NA[5]\ : MX2C - port map(A => addr_data_vector_1, B => - \addr_data_vector[101]\, S => sel_data_0(1), Y => N_1288); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => I_56_3); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f3(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[99]\); - - \address_RNIR245[29]\ : MX2C - port map(A => addr_data_vector_25, B => - \addr_data_vector[125]\, S => sel_data(1), Y => N_912); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XNOR2 - port map(A => N_46, B => \addr_data_vector[125]\, Y => - N_65_0); - - un1_address_m34 : AX1 - port map(A => N_32_0, B => \addr_data_vector[115]\, C => - \addr_data_vector[116]\, Y => N_35_0); - - \address_RNO[30]\ : MX2 - port map(A => N_66_0, B => addr_data_f3(30), S => - \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(3), B => N_131, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[3]_net_1\); - - \state_RNIQBSU8_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => I_56_3, Y => - N_31); - - un1_address_m54 : XOR2 - port map(A => N_23_0, B => \addr_data_vector[109]\, Y => - N_55_0_i_0); - - un1_address_m22 : NOR3C - port map(A => \addr_data_vector[107]\, B => N_19_0, C => - \addr_data_vector[108]\, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[103]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => I_38_3); - - un1_address_m24_m5_0_a2_1 : NOR2B - port map(A => \addr_data_vector[104]\, B => - \addr_data_vector[105]\, Y => m24_m5_0_a2_1); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => I_24_3, B => state7, Y => \nb_send_5[5]\); - - un1_address_m25 : XNOR2 - port map(A => N_25_0_i_0, B => \addr_data_vector[111]\, Y - => N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_0[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_1(7), CLK => HCLK_c, CLR => - HRESETn_c, Q => \update_r[1]_net_1\); - - un1_address_m40_m6_0_a2_7 : NOR3C - port map(A => m40_m6_0_a2_2, B => m40_m6_0_a2_1, C => - m40_m6_0_a2_6, Y => m40_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => I_38_3, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => I_20_11, B => nb_burst_available(4), C => - nb_burst_available(5), Y => \ACT_LT2_E[2]\); - - un1_address_m57 : XNOR2 - port map(A => N_36_0, B => \addr_data_vector[117]\, Y => - N_58_0); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => I_45_3, B => nb_burst_available(8), C => N_28, - Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNI0GNA[6]\ : MX2C - port map(A => addr_data_vector_2, B => - \addr_data_vector[102]\, S => sel_data_0(1), Y => N_1289); - - \address_RNO[22]\ : MX2 - port map(A => N_59_0, B => addr_data_f3(22), S => - \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1C - port map(A => \addr_data_vector[98]\, B => - \un1_state_12[4]\, C => \addr_data_vector[99]\, Y => - N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[105]\); - - \address_RNO[18]\ : MX2 - port map(A => N_57_0, B => addr_data_f3(18), S => - \state_0[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f3(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[126]\, B => N_47, C => - \addr_data_vector[127]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[102]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => I_13_19, B => nb_burst_available(3), Y => - \ACT_LT4_E[8]\); - - \address_RNISVMA[4]\ : MX2C - port map(A => addr_data_vector_0, B => - \addr_data_vector[100]\, S => sel_data_0(1), Y => N_1301); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => I_56_3, B => nb_burst_available(10), Y => - \DWACT_BL_EQUAL_0_E[4]\); - - status_full_err_RNO : AO1 - port map(A => \state[2]_net_1\, B => N_129, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => \state_RNIKABE[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f3(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - \state_RNIQBSU8[3]\ : NOR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa); - - un1_address_m36 : NOR2A - port map(A => \addr_data_vector[117]\, B => N_36_0, Y => - N_37_0); - - \state_RNI1KCD[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - \address_RNIP245[28]\ : MX2C - port map(A => addr_data_vector_24, B => - \addr_data_vector[124]\, S => sel_data(1), Y => N_911); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => I_52_3); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[107]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[127]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => I_9_19, Y => - \ACT_LT4_E[4]\); - - un1_address_m56 : AX1 - port map(A => N_29_0, B => \addr_data_vector[113]\, C => - \addr_data_vector[114]\, Y => N_57_0); - - \address_RNIE894[14]\ : MX2C - port map(A => addr_data_vector_10, B => - \addr_data_vector[110]\, S => sel_data_0(1), Y => N_1283); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f3(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f3(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => N_61_0, B => addr_data_f3(25), S => - \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[117]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - un1_address_m62 : XNOR2 - port map(A => N_44, B => \addr_data_vector[123]\, Y => - N_63_0); - - un1_address_m32 : XNOR2 - port map(A => N_32_0, B => \addr_data_vector[115]\, Y => - N_33_0); - - un1_address_m12_e : OR3C - port map(A => \addr_data_vector[100]\, B => N_69, C => - \addr_data_vector[101]\, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => I_9_19); - - \state[1]\ : DFN1C0 - port map(D => \state_RNO[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - un1_address_m24_m5_0_a2 : OR3C - port map(A => m24_m5_0_a2_5, B => m24_m5_0_a2_4, C => - N_13_0, Y => N_25_0_i_0); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[113]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => I_5_19, Y => - \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[126]\, Y => - N_66_0); - - un1_address_m35 : OR3B - port map(A => \addr_data_vector[115]\, B => - \addr_data_vector[116]\, C => N_32_0, Y => N_36_0); - - un1_address_m52 : XOR2 - port map(A => N_13_0, B => \addr_data_vector[103]\, Y => - N_1_i_0); - - un1_address_m24_m5_0_a2_5 : NOR3C - port map(A => \addr_data_vector[107]\, B => - \addr_data_vector[106]\, C => m24_m5_0_a2_3, Y => - m24_m5_0_a2_5); - - \address_RNIM894[18]\ : MX2C - port map(A => addr_data_vector_14, B => - \addr_data_vector[114]\, S => sel_data_0(1), Y => N_1287); - - un1_address_m24_m5_0_a2_3 : NOR2B - port map(A => \addr_data_vector[108]\, B => - \addr_data_vector[109]\, Y => m24_m5_0_a2_3); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \addr_data_vector[123]\); - - \state_RNO[3]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_129, Y => - \state_RNO_0[3]\); - - un1_address_m21 : AX1C - port map(A => \addr_data_vector[107]\, B => N_19_0, C => - \addr_data_vector[108]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => I_20_11, B => state7, Y => \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => I_56_3, B => state7, Y => \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => I_45_3, B => nb_burst_available(8), Y => N_29); - - un1_address_m55 : AX1C - port map(A => \addr_data_vector[109]\, B => N_23_0, C => - \addr_data_vector[110]\, Y => N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f3(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \address_RNI2ONA[7]\ : MX2C - port map(A => addr_data_vector_3, B => - \addr_data_vector[103]\, S => sel_data_0(1), Y => N_1290); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : NOR3C - port map(A => \addr_data_vector[98]\, B => - \un1_state_12[4]\, C => \addr_data_vector[99]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => I_20_11, B => nb_burst_available(4), Y => - \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f3(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - \update_r_RNI5KV4_0[0]\ : OR2 - port map(A => \update_r_i[0]\, B => \update_r[1]_net_1\, Y - => \un1_state_12_3_0[4]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => I_45_3, B => nb_burst_available(8), Y => - \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address_RNIHA45[31]\ : MX2C - port map(A => addr_data_vector_27, B => - \addr_data_vector[127]\, S => sel_data(1), Y => N_914); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f3(1), CLK => HCLK_c, CLR => - HRESETn_c, E => \state[0]_net_1\, Q => - addr_data_vector_61); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_11, Q => status_full(3)); - - un1_address_m63 : AX1 - port map(A => N_44, B => \addr_data_vector[123]\, C => - \addr_data_vector[124]\, Y => N_64_0); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => N_35_0, B => addr_data_f3(20), S => - \state[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR2A - port map(A => \addr_data_vector[125]\, B => N_46, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : AX1C - port map(A => \addr_data_vector[105]\, B => N_16_0, C => - \addr_data_vector[106]\, Y => N_54_0_i_0); - - un1_address_m40_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[112]\, B => - \addr_data_vector[113]\, Y => m40_m6_0_a2_1); - - un1_address_m24_m5_0_a2_4 : NOR3C - port map(A => \addr_data_vector[103]\, B => - \addr_data_vector[110]\, C => m24_m5_0_a2_1, Y => - m24_m5_0_a2_4); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[3]_net_1\, C - => \state[2]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f3(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => I_20_11); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity DMA2AHB is - - port( hburst_c : out std_logic_vector(2 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - un7_dmain : in std_logic_vector(66 to 66); - hsize_c : out std_logic_vector(1 downto 0); - AHB_Master_In_c_5 : in std_logic; - AHB_Master_In_c_4 : in std_logic; - AHB_Master_In_c_0 : in std_logic; - AHB_Master_In_c_3 : in std_logic; - haddr_c : out std_logic_vector(31 downto 0); - hwrite_c : out std_logic; - Ready : out std_logic; - N_1012 : in std_logic; - Grant : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - OKAY : out std_logic; - Fault : out std_logic; - N_1011 : in std_logic; - N_1013 : in std_logic; - N_43 : out std_logic; - time_select_0 : in std_logic; - N_960 : in std_logic; - N_959 : in std_logic; - N_958 : in std_logic; - N_957 : in std_logic; - N_964 : in std_logic; - N_963 : in std_logic; - N_962 : in std_logic; - N_961 : in std_logic; - N_955 : in std_logic; - N_954 : in std_logic; - N_953 : in std_logic; - N_952 : in std_logic; - N_951 : in std_logic; - N_950 : in std_logic; - N_949 : in std_logic; - N_948 : in std_logic; - N_947 : in std_logic; - N_956 : in std_logic; - N_965 : in std_logic; - N_966 : in std_logic; - N_967 : in std_logic; - N_968 : in std_logic; - N_969 : in std_logic; - N_970 : in std_logic; - N_971 : in std_logic; - N_972 : in std_logic; - N_973 : in std_logic; - N_974 : in std_logic; - N_975 : in std_logic; - N_976 : in std_logic; - N_977 : in std_logic; - HRESETn_c : in std_logic; - N_978 : in std_logic; - HCLK_c : in std_logic - ); - -end DMA2AHB; - -architecture DEF_ARCH of DMA2AHB is - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \htrans_12_i_o2_2_5[0]\, \htrans_12_i_o2_2_2[0]\, - \htrans_12_i_o2_2_4[0]\, \htrans_12_i_o2_2_0[0]\, N_183, - N_556_i_0, N_58_0, \Address_0_i_1[29]\, N_181, - \un1_AddressSave_0_sqmuxa_1_i_i[29]\, \Address_0_i_1[28]\, - N_179, N_37, \Address_0_i_1[26]\, N_177, N_35, - \Address_0_i_1[25]\, N_175, N_33_0, \Address_0_i_1[24]\, - N_173, N_55_0, \Address_0_i_1[23]\, N_128, N_556_i, - N_56_0, \Address_0_i_1[27]\, N_30, - \un1_AddressSave_0_sqmuxa_1_i_i[32]\, \Address_0_i_1[31]\, - N_28, N_42, \Address_0_i_1[30]\, N_13_0, N_580, N_15_0, - N_18_0, N_22_0, N_26_0, N_29_0, N_32_0, \haddr_c[24]\, - N_36, \haddr_c[25]\, N_39, \haddr_c[26]\, N_41, - \haddr_c[22]\, \haddr_c[23]\, \haddr_c[27]\, - \haddr_c[28]\, \haddr_c[29]\, \haddr_c[30]\, N_566, - \AddressPhase\, \AddressPhase_0\, N_191, hsize_0_sqmuxa_0, - N_756, N_754_0, \ReDataPhase\, N_553, N_753_0, N_555, - N_557, \Address_0_i_0[31]\, \AddressSave[31]_net_1\, - \Address_0_i_0[30]\, \AddressSave[30]_net_1\, - \Address_0_i_0[29]\, \AddressSave[29]_net_1\, - \Address_0_i_0[28]\, \AddressSave[28]_net_1\, - \Address_0_i_0[27]\, \AddressSave[27]_net_1\, - \Address_0_i_0[26]\, \AddressSave[26]_net_1\, - \Address_0_i_0[25]\, \AddressSave[25]_net_1\, - \Address_0_i_0[24]\, \AddressSave[24]_net_1\, - \Address_0_i_0[23]\, \AddressSave[23]_net_1\, - \Address_0_i_1[22]\, \Address_0_i_0[22]\, - \AddressSave[22]_net_1\, \Address_0_i_1[21]\, - \Address_0_i_0[21]\, \AddressSave[21]_net_1\, - \Address_0_i_1[20]\, \Address_0_i_0[20]\, - \AddressSave[20]_net_1\, \Address_0_i_1[19]\, - \Address_0_i_0[19]\, \AddressSave[19]_net_1\, - \Address_0_i_1[18]\, \Address_0_i_0[18]\, - \AddressSave[18]_net_1\, \Address_0_i_1[9]\, - \Address_0_i_0[9]\, \AddressSave[9]_net_1\, - \Address_0_i_1[0]\, \Address_0_i_0[0]\, - \AddressSave[0]_net_1\, \Address_0_i_1[1]\, N_753, - \Address_0_i_0[1]\, \AddressSave[1]_net_1\, N_754, - \Address_0_i_1[2]\, \Address_0_i_0[2]\, - \AddressSave[2]_net_1\, \Address_0_i_1[3]\, - \Address_0_i_0[3]\, \AddressSave[3]_net_1\, - \Address_0_i_1[4]\, \Address_0_i_0[4]\, - \AddressSave[4]_net_1\, \Address_0_i_1[5]\, - \Address_0_i_0[5]\, \AddressSave[5]_net_1\, - \Address_0_i_1[6]\, \Address_0_i_0[6]\, - \AddressSave[6]_net_1\, \Address_0_i_1[7]\, - \Address_0_i_0[7]\, \AddressSave[7]_net_1\, - \Address_0_i_1[8]\, \Address_0_i_0[8]\, - \AddressSave[8]_net_1\, \Address_0_i_1[14]\, - \Address_0_i_0[14]\, \AddressSave[14]_net_1\, - \Address_0_i_1[15]\, \Address_0_i_0[15]\, - \AddressSave[15]_net_1\, \Address_0_i_1[16]\, - \Address_0_i_0[16]\, \AddressSave[16]_net_1\, - \Address_0_i_1[17]\, \Address_0_i_0[17]\, - \AddressSave[17]_net_1\, \Address_0_i_1[10]\, - \Address_0_i_0[10]\, \AddressSave[10]_net_1\, - \Address_0_i_1[11]\, \Address_0_i_0[11]\, - \AddressSave[11]_net_1\, \Address_0_i_1[12]\, - \Address_0_i_0[12]\, \AddressSave[12]_net_1\, - \Address_0_i_1[13]\, \Address_0_i_0[13]\, - \AddressSave[13]_net_1\, \hsize_1_i_0[0]\, - BoundaryPhase_2_i_1, N_686, N_684, \hsize_1_i_0[1]\, - \htrans_12_i_2[0]\, \htrans_12_i_0[0]\, N_678, N_675, - \hsize_1_i_a5_0[1]\, \hsize_c[1]\, un1_ahbin_3_0_0, N_561, - \hburst_11_i_a2_i_a5_1[1]\, \ReAddrPhase\, - \hburst_11_0_a2_i_2[0]\, \hburst_11_0_a2_i_0[0]\, N_643, - N_563, \SingleAcc\, N_559, \un1_dmain_20_i_0\, - ActivePhase_1_sqmuxa_i_a5_0, \DataPhase\, DataPhase_2_i_0, - N_576, Fault_0_a5_0, \Address_RNO[13]_net_1\, - \un1_AddressSave_0_sqmuxa_1_i_i[14]\, - \Address_RNO[12]_net_1\, - \un1_AddressSave_0_sqmuxa_1_i_i[13]\, - \Address_RNO[11]_net_1\, - \un1_AddressSave_0_sqmuxa_1_i_i[12]\, - \Address_RNO[10]_net_1\, - \un1_AddressSave_0_sqmuxa_1_i_i[11]\, N_171, - \un1_AddressSave_0_sqmuxa_1_i_i[23]\, N_169, - \un1_AddressSave_0_sqmuxa_1_i_i[22]\, N_167, - \un1_AddressSave_0_sqmuxa_1_i_i[21]\, N_165, - \un1_AddressSave_0_sqmuxa_1_i_i[20]\, N_163, - \un1_AddressSave_0_sqmuxa_1_i_i[19]\, N_161, - \un1_AddressSave_0_sqmuxa_1_i_i[18]\, N_159, - \un1_AddressSave_0_sqmuxa_1_i_i[17]\, N_157, - \un1_AddressSave_0_sqmuxa_1_i_i[16]\, N_155, - \un1_AddressSave_0_sqmuxa_1_i_i[15]\, N_153, - \un1_AddressSave_0_sqmuxa_1_i_i[9]\, N_151, N_569, N_126, - \un1_AddressSave_0_sqmuxa_1_i_i[8]\, N_124, - \un1_AddressSave_0_sqmuxa_1_i_i[7]\, N_122, - \un1_AddressSave_0_sqmuxa_1_i_i[6]\, N_120, - \un1_AddressSave_0_sqmuxa_1_i_i[5]\, N_118, - \un1_AddressSave_0_sqmuxa_1_i_i[4]\, N_116, - \un1_AddressSave_0_sqmuxa_1_i_i[3]\, N_114, N_112, N_26, - \un1_AddressSave_0_sqmuxa_1_i_i[10]\, N_137_i_0, - \htrans_RNO_1[0]\, N_676, N_20, hwrite_2_sqmuxa, N_560, - hwrite_2_sqmuxa_1, N_758, N_149, N_147_i_0, - \BoundaryPhase_RNO_1\, N_685, N_635, \IdlePhase\, N_829, - N_567, N_760, N_682, N_554, N_189, N_737, N_196, N_193, - N_614, N_738, N_139, N_680, N_679, un1_ahbin_3, N_568, - N_639, N_56_i_0, N_330, N_592, N_331, N_593, N_332, N_594, - N_333, N_595, N_334, N_586, N_335, N_587, N_336, N_588, - N_337, N_589, N_338, N_613, N_339, N_590, N_340, N_615, - N_341, N_616, N_342, N_617, N_343, N_618, N_344, N_596, - N_345, N_597, N_346, N_598, hsize_0_sqmuxa, N_347, N_599, - N_348, N_600, N_349, N_601, N_350, N_602, N_351, N_603, - N_352, N_604, N_353, N_605, N_354, N_606, N_355, N_607, - N_356, N_608, N_357, N_609, N_358, N_610, N_359, N_611, - N_360, N_612, N_361, N_591, \haddr_c[2]\, N_5_0, - \haddr_c[3]\, \haddr_c[4]\, N_3_0, N_7_0, \haddr_c[5]\, - \haddr_c[6]\, N_9_0, \haddr_c[7]\, \haddr_c[8]\, - \haddr_c[10]\, \haddr_c[14]\, \haddr_c[16]\, - \haddr_c[17]\, \haddr_c[18]\, \haddr_c[19]\, - \haddr_c[20]\, \haddr_c[21]\, \haddr_c[9]\, \haddr_c[11]\, - \haddr_c[12]\, \haddr_c[13]\, \haddr_c[15]\, N_213, N_215, - N_217, N_219, N_221, N_225, N_259, N_261, N_263, N_279, - N_281, N_283, N_285, N_287, N_289, N_291, N_293, N_295, - \AddressSave_RNO[2]_net_1\, \AddressSave_RNO[3]_net_1\, - N_512, N_514, N_516, N_518, N_520, N_522, N_524, N_526, - N_528, N_530, N_532, N_534, \haddr_c[31]\, \haddr_c[0]\, - \haddr_c[1]\, \EarlyPhase\, N_562, N_325, N_53, N_48, - \BoundaryPhase\, Retry, N_761, N_102, SingleAcc_2_sqmuxa, - N_104, N_322, N_326, N_329, N_22, N_100, N_558, - \ActivePhase\, \WriteAcc\, N_582, N_130, N_24, N_327, - N_108, N_320, N_106, N_321, \hsize_c[0]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - hsize_c(1) <= \hsize_c[1]\; - hsize_c(0) <= \hsize_c[0]\; - haddr_c(31) <= \haddr_c[31]\; - haddr_c(30) <= \haddr_c[30]\; - haddr_c(29) <= \haddr_c[29]\; - haddr_c(28) <= \haddr_c[28]\; - haddr_c(27) <= \haddr_c[27]\; - haddr_c(26) <= \haddr_c[26]\; - haddr_c(25) <= \haddr_c[25]\; - haddr_c(24) <= \haddr_c[24]\; - haddr_c(23) <= \haddr_c[23]\; - haddr_c(22) <= \haddr_c[22]\; - haddr_c(21) <= \haddr_c[21]\; - haddr_c(20) <= \haddr_c[20]\; - haddr_c(19) <= \haddr_c[19]\; - haddr_c(18) <= \haddr_c[18]\; - haddr_c(17) <= \haddr_c[17]\; - haddr_c(16) <= \haddr_c[16]\; - haddr_c(15) <= \haddr_c[15]\; - haddr_c(14) <= \haddr_c[14]\; - haddr_c(13) <= \haddr_c[13]\; - haddr_c(12) <= \haddr_c[12]\; - haddr_c(11) <= \haddr_c[11]\; - haddr_c(10) <= \haddr_c[10]\; - haddr_c(9) <= \haddr_c[9]\; - haddr_c(8) <= \haddr_c[8]\; - haddr_c(7) <= \haddr_c[7]\; - haddr_c(6) <= \haddr_c[6]\; - haddr_c(5) <= \haddr_c[5]\; - haddr_c(4) <= \haddr_c[4]\; - haddr_c(3) <= \haddr_c[3]\; - haddr_c(2) <= \haddr_c[2]\; - haddr_c(1) <= \haddr_c[1]\; - haddr_c(0) <= \haddr_c[0]\; - - \AHBOut.hwrite_RNO_0\ : OR2 - port map(A => \WriteAcc\, B => N_561, Y => N_680); - - \Address[16]\ : DFN1 - port map(D => N_159, CLK => HCLK_c, Q => \haddr_c[16]\); - - \Address[10]\ : DFN1 - port map(D => \Address_RNO[10]_net_1\, CLK => HCLK_c, Q => - \haddr_c[10]\); - - \Address_RNO_1[3]\ : OAI1 - port map(A => \AddressSave[3]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[3]\); - - \Address[30]\ : DFN1 - port map(D => N_28, CLK => HCLK_c, Q => \haddr_c[30]\); - - \AddressSave_RNO_0[30]\ : MX2 - port map(A => \AddressSave[30]_net_1\, B => N_612, S => - hsize_0_sqmuxa, Y => N_360); - - \AddressSave[8]\ : DFN1 - port map(D => N_283, CLK => HCLK_c, Q => - \AddressSave[8]_net_1\); - - \Address_RNO_1[0]\ : OAI1 - port map(A => \AddressSave[0]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[0]\); - - ReAddrPhase_RNIEV7K1 : NOR3B - port map(A => N_829, B => \hburst_11_i_a2_i_a5_1[1]\, C => - N_554, Y => N_682); - - \DMAOut.Fault_0_a5_0\ : NOR2A - port map(A => AHB_Master_In_c_4, B => AHB_Master_In_c_5, Y - => Fault_0_a5_0); - - \AHBOut.hsize_RNO[1]\ : OA1B - port map(A => N_569, B => \hsize_1_i_a5_0[1]\, C => - \hsize_1_i_0[1]\, Y => N_151); - - \Address_RNO[26]\ : OA1B - port map(A => N_556_i_0, B => N_37, C => - \Address_0_i_1[26]\, Y => N_179); - - \AddressSave_RNO_0[12]\ : MX2 - port map(A => \AddressSave[12]_net_1\, B => N_617, S => - hsize_0_sqmuxa_0, Y => N_342); - - \AddressSave_RNO_1[1]\ : MX2 - port map(A => N_948, B => \haddr_c[1]\, S => - \AddressPhase_0\, Y => N_593); - - un1_AddressSave_0_sqmuxa_1_m55 : AX1C - port map(A => \haddr_c[26]\, B => N_36, C => \haddr_c[27]\, - Y => N_56_0); - - EarlyPhase_RNIP1701 : NOR3B - port map(A => N_561, B => AHB_Master_In_c_3, C => N_1011, Y - => N_738); - - \Address_RNO[1]\ : OA1B - port map(A => \haddr_c[1]\, B => N_556_i, C => - \Address_0_i_1[1]\, Y => N_114); - - \AddressSave_RNO_0[10]\ : MX2 - port map(A => \AddressSave[10]_net_1\, B => N_615, S => - hsize_0_sqmuxa_0, Y => N_340); - - \AddressSave_RNO_0[27]\ : MX2 - port map(A => \AddressSave[27]_net_1\, B => N_609, S => - hsize_0_sqmuxa, Y => N_357); - - \AddressSave[15]\ : DFN1 - port map(D => N_287, CLK => HCLK_c, Q => - \AddressSave[15]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m50 : XOR2 - port map(A => N_13_0, B => \haddr_c[12]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[13]\); - - \Address[26]\ : DFN1 - port map(D => N_179, CLK => HCLK_c, Q => \haddr_c[26]\); - - \Address[20]\ : DFN1 - port map(D => N_167, CLK => HCLK_c, Q => \haddr_c[20]\); - - \AddressSave[12]\ : DFN1 - port map(D => N_285, CLK => HCLK_c, Q => - \AddressSave[12]_net_1\); - - \AddressSave_RNO_1[16]\ : MX2 - port map(A => N_963, B => \haddr_c[16]\, S => - \AddressPhase_0\, Y => N_598); - - \Address_RNO_1[8]\ : OAI1 - port map(A => \AddressSave[8]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[8]\); - - BoundaryPhase_RNO : NOR3C - port map(A => BoundaryPhase_2_i_1, B => - \BoundaryPhase_RNO_1\, C => N_685, Y => N_147_i_0); - - un1_AddressSave_0_sqmuxa_1_m31 : NOR3C - port map(A => \haddr_c[22]\, B => N_29_0, C => - \haddr_c[23]\, Y => N_32_0); - - IdlePhase_RNO : NOR2B - port map(A => N_326, B => HRESETn_c, Y => N_100); - - un1_AddressSave_0_sqmuxa_1_m47 : XNOR2 - port map(A => N_9_0, B => \haddr_c[9]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[10]\); - - \AHBOut.hsize[1]\ : DFN1 - port map(D => N_151, CLK => HCLK_c, Q => \hsize_c[1]\); - - ActivePhase_RNO_2 : OR2 - port map(A => \DataPhase\, B => \AddressPhase_0\, Y => - ActivePhase_1_sqmuxa_i_a5_0); - - \AHBOut.hburst_RNO_1[0]\ : AOI1B - port map(A => \SingleAcc\, B => N_559, C => - AHB_Master_In_c_0, Y => \hburst_11_0_a2_i_0[0]\); - - \Address_RNO_0[11]\ : AO1D - port map(A => N_958, B => N_753, C => \Address_0_i_0[11]\, - Y => \Address_0_i_1[11]\); - - \Address_RNO_0[8]\ : AO1D - port map(A => N_955, B => N_753, C => \Address_0_i_0[8]\, Y - => \Address_0_i_1[8]\); - - \Address_RNO_1[21]\ : OAI1 - port map(A => \AddressSave[21]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[21]\); - - \AHBOut.hwrite\ : DFN1E1 - port map(D => N_139, CLK => HCLK_c, E => N_130, Q => - hwrite_c); - - \Address[12]\ : DFN1 - port map(D => \Address_RNO[12]_net_1\, CLK => HCLK_c, Q => - \haddr_c[12]\); - - \AddressSave[23]\ : DFN1 - port map(D => N_526, CLK => HCLK_c, Q => - \AddressSave[23]_net_1\); - - \AddressSave_RNO_0[8]\ : MX2 - port map(A => \AddressSave[8]_net_1\, B => N_613, S => - hsize_0_sqmuxa_0, Y => N_338); - - \AddressSave_RNO_1[31]\ : MX2 - port map(A => N_978, B => \haddr_c[31]\, S => - \AddressPhase_0\, Y => N_591); - - \AddressSave_RNO[5]\ : NOR2B - port map(A => N_335, B => HRESETn_c, Y => N_281); - - \Address_RNO_1[11]\ : OAI1 - port map(A => \AddressSave[11]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[11]\); - - \AddressSave_RNO[18]\ : NOR2B - port map(A => N_348, B => HRESETn_c, Y => N_524); - - un1_AddressSave_0_sqmuxa_1_m41 : XOR2 - port map(A => N_41, B => \haddr_c[30]\, Y => N_42); - - \Address_RNO[29]\ : OA1B - port map(A => N_556_i_0, B => N_58_0, C => - \Address_0_i_1[29]\, Y => N_183); - - \AddressSave_RNO_1[28]\ : MX2A - port map(A => N_975, B => \haddr_c[28]\, S => - \AddressPhase\, Y => N_610); - - WriteAcc_RNO : NOR2B - port map(A => N_321, B => HRESETn_c, Y => N_106); - - \AddressSave_RNO[11]\ : NOR2B - port map(A => N_341, B => HRESETn_c, Y => N_518); - - SingleAcc_RNO : NOR2B - port map(A => N_322, B => HRESETn_c, Y => N_104); - - ReAddrPhase_RNO_1 : OA1B - port map(A => \AddressPhase\, B => \ReAddrPhase\, C => - AHB_Master_In_c_3, Y => N_53); - - \Address[22]\ : DFN1 - port map(D => N_171, CLK => HCLK_c, Q => \haddr_c[22]\); - - \Address_RNO[23]\ : OA1B - port map(A => N_556_i_0, B => N_55_0, C => - \Address_0_i_1[23]\, Y => N_173); - - \Address[2]\ : DFN1 - port map(D => N_116, CLK => HCLK_c, Q => \haddr_c[2]\); - - \Address_RNO_1[7]\ : OAI1 - port map(A => \AddressSave[7]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[7]\); - - \Address_RNO[24]\ : OA1B - port map(A => N_556_i_0, B => N_33_0, C => - \Address_0_i_1[24]\, Y => N_175); - - \Address_RNO[10]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[11]\, C => - \Address_0_i_1[10]\, Y => \Address_RNO[10]_net_1\); - - \AddressSave[20]\ : DFN1 - port map(D => N_225, CLK => HCLK_c, Q => - \AddressSave[20]_net_1\); - - \Address_RNO_1[30]\ : OAI1 - port map(A => \AddressSave[30]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[30]\); - - \AddressSave_RNO_1[3]\ : MX2 - port map(A => N_950, B => \haddr_c[3]\, S => - \AddressPhase_0\, Y => N_595); - - \AddressSave_RNO_1[19]\ : MX2 - port map(A => N_966, B => \haddr_c[19]\, S => - \AddressPhase_0\, Y => N_601); - - AddressPhase_RNI6S87 : OR2B - port map(A => \AddressPhase\, B => AHB_Master_In_c_3, Y => - N_566); - - ActivePhase_RNIS2FG1 : AO1 - port map(A => N_582, B => AHB_Master_In_c_3, C => N_563, Y - => N_130); - - EarlyPhase_RNO_1 : AO1C - port map(A => AHB_Master_In_c_0, B => N_568, C => - un1_ahbin_3_0_0, Y => un1_ahbin_3); - - \AddressSave_RNO_1[24]\ : MX2 - port map(A => N_971, B => \haddr_c[24]\, S => - \AddressPhase\, Y => N_606); - - \DMAOut.Ready_RNO\ : NOR3C - port map(A => HRESETn_c, B => AHB_Master_In_c_3, C => - \DataPhase\, Y => N_196); - - BoundaryPhase_RNO_2 : OR2A - port map(A => N_555, B => N_553, Y => N_685); - - \AddressSave_RNO[25]\ : NOR2B - port map(A => N_355, B => HRESETn_c, Y => N_530); - - \AddressSave_RNO_1[23]\ : MX2 - port map(A => N_970, B => \haddr_c[23]\, S => - \AddressPhase\, Y => N_605); - - \AHBOut.hbusreq_i_0_a2\ : NOR2A - port map(A => un7_dmain(66), B => N_1011, Y => N_761); - - \Address_RNO[9]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[10]\, C => - \Address_0_i_1[9]\, Y => N_26); - - \Address[5]\ : DFN1 - port map(D => N_122, CLK => HCLK_c, Q => \haddr_c[5]\); - - \AddressSave[30]\ : DFN1 - port map(D => N_532, CLK => HCLK_c, Q => - \AddressSave[30]_net_1\); - - \Address[15]\ : DFN1 - port map(D => N_157, CLK => HCLK_c, Q => \haddr_c[15]\); - - \AHBOut.hburst[2]\ : DFN1E1 - port map(D => N_682, CLK => HCLK_c, E => N_130, Q => - hburst_c(2)); - - \Address_RNO_0[9]\ : AO1D - port map(A => N_956, B => N_753_0, C => \Address_0_i_0[9]\, - Y => \Address_0_i_1[9]\); - - \Address[13]\ : DFN1 - port map(D => \Address_RNO[13]_net_1\, CLK => HCLK_c, Q => - \haddr_c[13]\); - - \AddressSave_RNO_1[15]\ : MX2 - port map(A => N_962, B => \haddr_c[15]\, S => - \AddressPhase_0\, Y => N_597); - - \AddressSave_RNO_1[11]\ : MX2 - port map(A => N_958, B => \haddr_c[11]\, S => - \AddressPhase\, Y => N_616); - - \AddressSave_RNO_0[18]\ : MX2 - port map(A => \AddressSave[18]_net_1\, B => N_600, S => - hsize_0_sqmuxa, Y => N_348); - - \AddressSave[6]\ : DFN1 - port map(D => N_215, CLK => HCLK_c, Q => - \AddressSave[6]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m24 : AX1C - port map(A => \haddr_c[18]\, B => N_22_0, C => - \haddr_c[19]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[20]\); - - \AHBOut.hsize_RNO_1[1]\ : OR2 - port map(A => \hsize_c[1]\, B => \AddressPhase_0\, Y => - \hsize_1_i_a5_0[1]\); - - \Address_RNO_1[4]\ : OAI1 - port map(A => \AddressSave[4]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[4]\); - - ReDataPhase_RNIORDS : OA1B - port map(A => N_555, B => \ReDataPhase\, C => N_553, Y => - N_556_i); - - \Address[19]\ : DFN1 - port map(D => N_165, CLK => HCLK_c, Q => \haddr_c[19]\); - - ActivePhase_RNII8GG : OR2A - port map(A => N_1011, B => \ActivePhase\, Y => N_554); - - BoundaryPhase_RNO_0 : NOR3C - port map(A => N_686, B => HRESETn_c, C => N_684, Y => - BoundaryPhase_2_i_1); - - \Address[25]\ : DFN1 - port map(D => N_177, CLK => HCLK_c, Q => \haddr_c[25]\); - - un1_AddressSave_0_sqmuxa_1_m12 : NOR3C - port map(A => \haddr_c[10]\, B => N_580, C => \haddr_c[11]\, - Y => N_13_0); - - \Address_RNO_0[27]\ : AO1A - port map(A => N_753_0, B => N_974, C => \Address_0_i_0[27]\, - Y => \Address_0_i_1[27]\); - - \AddressSave_RNO[7]\ : NOR2B - port map(A => N_337, B => HRESETn_c, Y => N_217); - - ActivePhase_RNIHBAN : OR2 - port map(A => N_554, B => N_553, Y => N_756); - - \Address[23]\ : DFN1 - port map(D => N_173, CLK => HCLK_c, Q => \haddr_c[23]\); - - \AddressSave_RNO_1[7]\ : MX2 - port map(A => N_954, B => \haddr_c[7]\, S => - \AddressPhase_0\, Y => N_589); - - \AHBOut.htrans[1]\ : DFN1E1 - port map(D => N_193, CLK => HCLK_c, E => N_189, Q => - htrans_c(1)); - - DataPhase_RNI0SGJ_0 : AO1C - port map(A => N_760, B => N_558, C => HRESETn_c, Y => N_563); - - AddressPhase_RNIDRDU1 : NOR3 - port map(A => N_563, B => N_614, C => N_738, Y => N_191); - - WriteAcc_RNO_0 : MX2 - port map(A => \WriteAcc\, B => N_1012, S => hwrite_2_sqmuxa, - Y => N_321); - - \AddressSave_RNO[29]\ : NOR2B - port map(A => N_359, B => HRESETn_c, Y => N_295); - - \AddressSave_RNO_0[14]\ : MX2 - port map(A => \AddressSave[14]_net_1\, B => N_596, S => - hsize_0_sqmuxa_0, Y => N_344); - - \Address[29]\ : DFN1 - port map(D => N_183, CLK => HCLK_c, Q => \haddr_c[29]\); - - \Address_RNIQTTQ[4]\ : NOR3C - port map(A => \haddr_c[4]\, B => \haddr_c[3]\, C => - \htrans_12_i_o2_2_0[0]\, Y => \htrans_12_i_o2_2_4[0]\); - - \Address[18]\ : DFN1 - port map(D => N_163, CLK => HCLK_c, Q => \haddr_c[18]\); - - \AddressSave_RNO[10]\ : NOR2B - port map(A => N_340, B => HRESETn_c, Y => N_516); - - \AddressSave[16]\ : DFN1 - port map(D => N_520, CLK => HCLK_c, Q => - \AddressSave[16]_net_1\); - - \AddressSave_RNO_1[26]\ : MX2A - port map(A => N_973, B => \haddr_c[26]\, S => - \AddressPhase\, Y => N_608); - - \AddressSave_RNO_0[13]\ : MX2 - port map(A => \AddressSave[13]_net_1\, B => N_618, S => - hsize_0_sqmuxa_0, Y => N_343); - - ActivePhase_RNO : NOR2B - port map(A => N_320, B => HRESETn_c, Y => N_108); - - \Address_RNO[21]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[22]\, C => - \Address_0_i_1[21]\, Y => N_169); - - \Address_RNO[16]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[17]\, C => - \Address_0_i_1[16]\, Y => N_159); - - SingleAcc_RNO_1 : NOR3C - port map(A => AHB_Master_In_c_0, B => N_561, C => - un7_dmain(66), Y => SingleAcc_2_sqmuxa); - - \Address_RNO_0[30]\ : AO1D - port map(A => N_977, B => N_753_0, C => \Address_0_i_0[30]\, - Y => \Address_0_i_1[30]\); - - \Address_RNO_0[24]\ : AO1D - port map(A => N_971, B => N_753_0, C => \Address_0_i_0[24]\, - Y => \Address_0_i_1[24]\); - - un1_AddressSave_0_sqmuxa_1_m2 : OR2A - port map(A => \haddr_c[2]\, B => N_566, Y => N_3_0); - - \Address_RNO_0[25]\ : AO1D - port map(A => N_972, B => N_753_0, C => \Address_0_i_0[25]\, - Y => \Address_0_i_1[25]\); - - \Address[0]\ : DFN1 - port map(D => N_112, CLK => HCLK_c, Q => \haddr_c[0]\); - - ReDataPhase_RNIHO18 : OR2A - port map(A => \ReDataPhase\, B => N_553, Y => N_754); - - \AddressSave_RNO[22]\ : NOR2B - port map(A => N_352, B => HRESETn_c, Y => N_291); - - DataPhase_RNIFGQC : NOR2A - port map(A => AHB_Master_In_c_5, B => N_760, Y => Retry); - - BoundaryPhase_RNO_1 : OR2 - port map(A => N_580, B => \BoundaryPhase\, Y => - \BoundaryPhase_RNO_1\); - - GND_i : GND - port map(Y => \GND\); - - \AddressSave_RNO_0[6]\ : MX2 - port map(A => \AddressSave[6]_net_1\, B => N_588, S => - hsize_0_sqmuxa_0, Y => N_336); - - \AHBOut.hsize_RNO_2[1]\ : OAI1 - port map(A => AHB_Master_In_c_3, B => \hsize_c[1]\, C => - HRESETn_c, Y => \hsize_1_i_0[1]\); - - \AHBOut.hburst_RNO_0[0]\ : NOR3B - port map(A => \hburst_11_0_a2_i_0[0]\, B => N_643, C => - N_563, Y => \hburst_11_0_a2_i_2[0]\); - - \AddressSave_RNO[16]\ : NOR2B - port map(A => N_346, B => HRESETn_c, Y => N_520); - - \Address_RNO[27]\ : OA1B - port map(A => N_556_i, B => N_56_0, C => - \Address_0_i_1[27]\, Y => N_128); - - \Address[4]\ : DFN1 - port map(D => N_120, CLK => HCLK_c, Q => \haddr_c[4]\); - - \Address[28]\ : DFN1 - port map(D => N_181, CLK => HCLK_c, Q => \haddr_c[28]\); - - \AHBOut.htrans_RNO_5[0]\ : OAI1 - port map(A => \ReAddrPhase\, B => N_1011, C => - \BoundaryPhase\, Y => N_675); - - \AddressSave_RNO[23]\ : NOR2B - port map(A => N_353, B => HRESETn_c, Y => N_526); - - un1_AddressSave_0_sqmuxa_1_m49 : AX1C - port map(A => \haddr_c[10]\, B => N_580, C => \haddr_c[11]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[12]\); - - un1_AddressSave_0_sqmuxa_1_m35 : NOR3C - port map(A => \haddr_c[24]\, B => N_32_0, C => - \haddr_c[25]\, Y => N_36); - - \Address_RNO_0[3]\ : AO1D - port map(A => N_950, B => N_753, C => \Address_0_i_0[3]\, Y - => \Address_0_i_1[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_AddressSave_0_sqmuxa_1_m52 : AX1C - port map(A => \haddr_c[14]\, B => N_15_0, C => - \haddr_c[15]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[16]\); - - EarlyPhase : DFN1 - port map(D => N_24, CLK => HCLK_c, Q => \EarlyPhase\); - - \Address_RNO_1[31]\ : OAI1 - port map(A => \AddressSave[31]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[31]\); - - \AddressSave_RNO[4]\ : NOR2B - port map(A => N_334, B => HRESETn_c, Y => N_512); - - un1_AddressSave_0_sqmuxa_1_m18 : XOR2 - port map(A => N_18_0, B => \haddr_c[16]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[17]\); - - \Address_RNO_0[4]\ : AO1D - port map(A => N_951, B => N_753, C => \Address_0_i_0[4]\, Y - => \Address_0_i_1[4]\); - - \Address_RNO_0[5]\ : AO1D - port map(A => N_952, B => N_753, C => \Address_0_i_0[5]\, Y - => \Address_0_i_1[5]\); - - \AHBOut.hsize[0]\ : DFN1 - port map(D => N_149, CLK => HCLK_c, Q => \hsize_c[0]\); - - \Address_RNO_0[17]\ : AO1D - port map(A => N_964, B => N_753, C => \Address_0_i_0[17]\, - Y => \Address_0_i_1[17]\); - - \AddressSave_RNO_1[2]\ : MX2 - port map(A => N_949, B => \haddr_c[2]\, S => - \AddressPhase_0\, Y => N_594); - - ReAddrPhase_RNO : NOR2B - port map(A => N_325, B => HRESETn_c, Y => N_102); - - \AddressSave_RNO_1[17]\ : MX2 - port map(A => N_964, B => \haddr_c[17]\, S => - \AddressPhase_0\, Y => N_599); - - \Address_RNO_1[27]\ : OAI1 - port map(A => \AddressSave[27]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[27]\); - - \AHBMaster.AHBOut.hwrite_8_iv_i_o5\ : OR2B - port map(A => AHB_Master_In_c_3, B => AHB_Master_In_c_0, Y - => N_553); - - un1_AddressSave_0_sqmuxa_1_m45 : AX1 - port map(A => N_5_0, B => \haddr_c[5]\, C => \haddr_c[6]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[7]\); - - \Address_RNI2UUQ[8]\ : NOR3C - port map(A => \haddr_c[8]\, B => \haddr_c[7]\, C => - \htrans_12_i_o2_2_2[0]\, Y => \htrans_12_i_o2_2_5[0]\); - - \Address_RNO[19]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[20]\, C => - \Address_0_i_1[19]\, Y => N_165); - - \AddressSave_RNO_0[16]\ : MX2 - port map(A => \AddressSave[16]_net_1\, B => N_598, S => - hsize_0_sqmuxa, Y => N_346); - - \Address_RNO_1[17]\ : OAI1 - port map(A => \AddressSave[17]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[17]\); - - \AHBOut.hburst[0]\ : DFN1E1 - port map(D => N_56_i_0, CLK => HCLK_c, E => N_130, Q => - hburst_c(0)); - - \AddressSave[9]\ : DFN1 - port map(D => N_514, CLK => HCLK_c, Q => - \AddressSave[9]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m40 : NOR3C - port map(A => \haddr_c[28]\, B => N_39, C => \haddr_c[29]\, - Y => N_41); - - IdlePhase_0_sqmuxa_0_o2 : OR2 - port map(A => AHB_Master_In_c_5, B => AHB_Master_In_c_4, Y - => N_558); - - \AddressSave_RNO_1[29]\ : MX2 - port map(A => N_976, B => \haddr_c[29]\, S => - \AddressPhase\, Y => N_611); - - \AddressSave_RNO[2]\ : NOR2B - port map(A => N_332, B => HRESETn_c, Y => - \AddressSave_RNO[2]_net_1\); - - \Address_RNO[13]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[14]\, C => - \Address_0_i_1[13]\, Y => \Address_RNO[13]_net_1\); - - \Address_RNO_0[14]\ : AO1D - port map(A => N_961, B => N_753, C => \Address_0_i_0[14]\, - Y => \Address_0_i_1[14]\); - - \Address[14]\ : DFN1 - port map(D => N_155, CLK => HCLK_c, Q => \haddr_c[14]\); - - \AddressSave[29]\ : DFN1 - port map(D => N_295, CLK => HCLK_c, Q => - \AddressSave[29]_net_1\); - - \Address_RNO_0[15]\ : AO1D - port map(A => N_962, B => N_753, C => \Address_0_i_0[15]\, - Y => \Address_0_i_1[15]\); - - \Address_RNO_1[24]\ : OAI1 - port map(A => \AddressSave[24]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[24]\); - - \AddressSave_RNO_0[1]\ : MX2 - port map(A => \AddressSave[1]_net_1\, B => N_593, S => - hsize_0_sqmuxa_0, Y => N_331); - - \IdlePhase_RNI03G71\ : OA1C - port map(A => N_761, B => N_559, C => \IdlePhase\, Y => - IdlePhase_RNI03G71); - - \Address_RNO_1[25]\ : OAI1 - port map(A => \AddressSave[25]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[25]\); - - \Address_RNO[14]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[15]\, C => - \Address_0_i_1[14]\, Y => N_155); - - \Address_RNO_1[14]\ : OAI1 - port map(A => \AddressSave[14]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[14]\); - - \Address_RNIV6FD[6]\ : NOR2B - port map(A => \haddr_c[5]\, B => \haddr_c[6]\, Y => - \htrans_12_i_o2_2_2[0]\); - - DataPhase_RNIGGQC : OR2B - port map(A => N_558, B => \DataPhase\, Y => N_737); - - \Address_RNO_1[15]\ : OAI1 - port map(A => \AddressSave[15]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[15]\); - - \AddressSave[11]\ : DFN1 - port map(D => N_518, CLK => HCLK_c, Q => - \AddressSave[11]_net_1\); - - \AddressSave_RNO_1[25]\ : MX2 - port map(A => N_972, B => \haddr_c[25]\, S => - \AddressPhase\, Y => N_607); - - \AddressSave_RNO_1[21]\ : MX2 - port map(A => N_968, B => \haddr_c[21]\, S => - \AddressPhase_0\, Y => N_603); - - \Address[24]\ : DFN1 - port map(D => N_175, CLK => HCLK_c, Q => \haddr_c[24]\); - - \Address_RNO_0[22]\ : AO1D - port map(A => N_969, B => N_753_0, C => \Address_0_i_0[22]\, - Y => \Address_0_i_1[22]\); - - \AddressSave[1]\ : DFN1 - port map(D => N_279, CLK => HCLK_c, Q => - \AddressSave[1]_net_1\); - - \AHBOut.hwrite_RNO\ : NOR3C - port map(A => N_193, B => N_680, C => N_679, Y => N_139); - - VCC_i : VCC - port map(Y => \VCC\); - - \Address_RNO_0[31]\ : AO1D - port map(A => N_978, B => N_753_0, C => \Address_0_i_0[31]\, - Y => \Address_0_i_1[31]\); - - \AddressSave[25]\ : DFN1 - port map(D => N_530, CLK => HCLK_c, Q => - \AddressSave[25]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m27 : AX1C - port map(A => \haddr_c[20]\, B => N_26_0, C => - \haddr_c[21]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[22]\); - - \AddressSave[22]\ : DFN1 - port map(D => N_291, CLK => HCLK_c, Q => - \AddressSave[22]_net_1\); - - \AddressSave_RNO_0[19]\ : MX2 - port map(A => \AddressSave[19]_net_1\, B => N_601, S => - hsize_0_sqmuxa, Y => N_349); - - ReDataPhase_RNIORDS_0 : OA1B - port map(A => N_555, B => \ReDataPhase\, C => N_553, Y => - N_556_i_0); - - \AddressSave_RNO_0[31]\ : MX2 - port map(A => \AddressSave[31]_net_1\, B => N_591, S => - hsize_0_sqmuxa, Y => N_361); - - \AddressSave_RNO[1]\ : NOR2B - port map(A => N_331, B => HRESETn_c, Y => N_279); - - \Address[8]\ : DFN1 - port map(D => N_153, CLK => HCLK_c, Q => \haddr_c[8]\); - - \Address_RNO_0[1]\ : AO1D - port map(A => N_948, B => N_753, C => \Address_0_i_0[1]\, Y - => \Address_0_i_1[1]\); - - un1_AddressSave_0_sqmuxa_1_m21 : NOR3C - port map(A => \haddr_c[16]\, B => N_18_0, C => - \haddr_c[17]\, Y => N_22_0); - - BoundaryPhase : DFN1 - port map(D => N_147_i_0, CLK => HCLK_c, Q => - \BoundaryPhase\); - - \AddressSave_RNO_0[7]\ : MX2 - port map(A => \AddressSave[7]_net_1\, B => N_589, S => - hsize_0_sqmuxa_0, Y => N_337); - - ReAddrPhase_RNO_2 : AO1A - port map(A => N_557, B => \ReAddrPhase\, C => Retry, Y => - N_48); - - EarlyPhase_RNILB3D : NOR2 - port map(A => N_559, B => \EarlyPhase\, Y => N_561); - - \AddressSave_RNO[24]\ : NOR2B - port map(A => N_354, B => HRESETn_c, Y => N_528); - - \AHBOut.htrans_RNO_0[0]\ : NOR3C - port map(A => \htrans_12_i_0[0]\, B => N_678, C => N_675, Y - => \htrans_12_i_2[0]\); - - \AddressSave_RNO_1[9]\ : MX2 - port map(A => N_956, B => \haddr_c[9]\, S => - \AddressPhase_0\, Y => N_590); - - \AHBOut.hburst_RNO_2[0]\ : OR2B - port map(A => un7_dmain(66), B => N_561, Y => N_643); - - \Address_RNO[6]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[7]\, C => - \Address_0_i_1[6]\, Y => N_124); - - IdlePhase : DFN1 - port map(D => N_100, CLK => HCLK_c, Q => \IdlePhase\); - - \AddressSave_RNO_0[15]\ : MX2 - port map(A => \AddressSave[15]_net_1\, B => N_597, S => - hsize_0_sqmuxa_0, Y => N_345); - - \AddressSave_RNO_0[11]\ : MX2 - port map(A => \AddressSave[11]_net_1\, B => N_616, S => - hsize_0_sqmuxa_0, Y => N_341); - - ReAddrPhase : DFN1 - port map(D => N_102, CLK => HCLK_c, Q => \ReAddrPhase\); - - \Address_RNO[28]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[29]\, C => - \Address_0_i_1[28]\, Y => N_181); - - \Address_RNO[11]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[12]\, C => - \Address_0_i_1[11]\, Y => \Address_RNO[11]_net_1\); - - \Address_RNO_0[12]\ : AO1D - port map(A => N_959, B => N_753, C => \Address_0_i_0[12]\, - Y => \Address_0_i_1[12]\); - - \AddressSave_RNO_1[5]\ : MX2 - port map(A => N_952, B => \haddr_c[5]\, S => - \AddressPhase_0\, Y => N_587); - - DataPhase_RNO_0 : OAI1 - port map(A => AHB_Master_In_c_3, B => N_576, C => HRESETn_c, - Y => DataPhase_2_i_0); - - \Address_RNO_1[22]\ : OAI1 - port map(A => \AddressSave[22]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[22]\); - - \Address_RNO[17]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[18]\, C => - \Address_0_i_1[17]\, Y => N_161); - - \AddressSave_RNO_0[0]\ : MX2 - port map(A => \AddressSave[0]_net_1\, B => N_592, S => - hsize_0_sqmuxa_0, Y => N_330); - - \AddressSave_RNO[31]\ : NOR2B - port map(A => N_361, B => HRESETn_c, Y => N_534); - - IdlePhase_RNI9HPU : NOR3 - port map(A => N_635, B => \IdlePhase\, C => N_1013, Y => - N_43); - - \Address_RNO[5]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[6]\, C => - \Address_0_i_1[5]\, Y => N_122); - - \AddressSave[17]\ : DFN1 - port map(D => N_522, CLK => HCLK_c, Q => - \AddressSave[17]_net_1\); - - \Address_RNO_1[12]\ : OAI1 - port map(A => \AddressSave[12]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[12]\); - - \AddressSave_RNO_1[27]\ : MX2A - port map(A => N_974, B => \haddr_c[27]\, S => - \AddressPhase\, Y => N_609); - - \AddressSave_RNO[15]\ : NOR2B - port map(A => N_345, B => HRESETn_c, Y => N_287); - - \AddressSave[4]\ : DFN1 - port map(D => N_512, CLK => HCLK_c, Q => - \AddressSave[4]_net_1\); - - \AddressSave[14]\ : DFN1 - port map(D => N_221, CLK => HCLK_c, Q => - \AddressSave[14]_net_1\); - - \Address_RNO[0]\ : OA1B - port map(A => \haddr_c[0]\, B => N_556_i, C => - \Address_0_i_1[0]\, Y => N_112); - - ActivePhase : DFN1 - port map(D => N_108, CLK => HCLK_c, Q => \ActivePhase\); - - ReAddrPhase_RNO_0 : MX2 - port map(A => \ReAddrPhase\, B => N_53, S => N_48, Y => - N_325); - - \AddressSave[7]\ : DFN1 - port map(D => N_217, CLK => HCLK_c, Q => - \AddressSave[7]_net_1\); - - DataPhase_RNI0SGJ : OR3B - port map(A => HRESETn_c, B => N_737, C => AHB_Master_In_c_3, - Y => N_189); - - \Address_RNO_0[2]\ : AO1D - port map(A => N_949, B => N_753, C => \Address_0_i_0[2]\, Y - => \Address_0_i_1[2]\); - - \AddressSave_RNO_0[22]\ : MX2 - port map(A => \AddressSave[22]_net_1\, B => N_604, S => - hsize_0_sqmuxa, Y => N_352); - - un1_AddressSave_0_sqmuxa_1_m14 : NOR3C - port map(A => \haddr_c[12]\, B => N_13_0, C => - \haddr_c[13]\, Y => N_15_0); - - \Address_RNO[3]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[4]\, C => - \Address_0_i_1[3]\, Y => N_118); - - \Address[3]\ : DFN1 - port map(D => N_118, CLK => HCLK_c, Q => \haddr_c[3]\); - - \AddressSave_RNO_1[6]\ : MX2 - port map(A => N_953, B => \haddr_c[6]\, S => - \AddressPhase_0\, Y => N_588); - - ActivePhase_RNO_1 : NOR3A - port map(A => un7_dmain(66), B => - ActivePhase_1_sqmuxa_i_a5_0, C => N_559, Y => N_639); - - un1_AddressSave_0_sqmuxa_1_m32 : XOR2 - port map(A => N_32_0, B => \haddr_c[24]\, Y => N_33_0); - - ReDataPhase_RNILM59 : OR2 - port map(A => \ReDataPhase\, B => \ReAddrPhase\, Y => N_559); - - \AddressSave_RNO_0[20]\ : MX2 - port map(A => \AddressSave[20]_net_1\, B => N_602, S => - hsize_0_sqmuxa, Y => N_350); - - \AddressSave_RNO[0]\ : NOR2B - port map(A => N_330, B => HRESETn_c, Y => N_213); - - \Address_RNO_1[2]\ : OAI1 - port map(A => \AddressSave[2]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[2]\); - - DataPhase_RNISED9 : OR2A - port map(A => \DataPhase\, B => AHB_Master_In_c_3, Y => - N_760); - - \Address_RNO[30]\ : OA1B - port map(A => N_556_i, B => N_42, C => \Address_0_i_1[30]\, - Y => N_28); - - \AddressSave[0]\ : DFN1 - port map(D => N_213, CLK => HCLK_c, Q => - \AddressSave[0]_net_1\); - - AddressPhase : DFN1 - port map(D => N_191, CLK => HCLK_c, Q => \AddressPhase\); - - BoundaryPhase_RNO_5 : MX2A - port map(A => \ReAddrPhase\, B => \ActivePhase\, S => - \AddressPhase\, Y => N_567); - - \AHBOut.htrans_RNO_6[0]\ : AOI1 - port map(A => N_1011, B => \AddressPhase\, C => - \ReAddrPhase\, Y => N_562); - - \AddressSave_RNO_0[5]\ : MX2 - port map(A => \AddressSave[5]_net_1\, B => N_587, S => - hsize_0_sqmuxa_0, Y => N_335); - - \AddressSave_RNO[3]\ : NOR2B - port map(A => N_333, B => HRESETn_c, Y => - \AddressSave_RNO[3]_net_1\); - - DataPhase_RNI1I7G : OR2B - port map(A => N_576, B => AHB_Master_In_c_3, Y => OKAY); - - ReAddrPhase_RNIMLKN : OR2A - port map(A => N_1011, B => \ReAddrPhase\, Y => - hwrite_2_sqmuxa_1); - - \AddressSave_RNO[19]\ : NOR2B - port map(A => N_349, B => HRESETn_c, Y => N_289); - - un1_AddressSave_0_sqmuxa_1_m42 : XNOR2 - port map(A => N_3_0, B => \haddr_c[3]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[4]\); - - \Address_RNO_0[6]\ : AO1D - port map(A => N_953, B => N_753, C => \Address_0_i_0[6]\, Y - => \Address_0_i_1[6]\); - - AddressPhase_RNIN7JU_0 : OR2B - port map(A => N_756, B => N_566, Y => hsize_0_sqmuxa); - - un1_AddressSave_0_sqmuxa_1_m6 : OR3B - port map(A => \haddr_c[5]\, B => \haddr_c[6]\, C => N_5_0, - Y => N_7_0); - - \AddressSave_RNO_0[17]\ : MX2 - port map(A => \AddressSave[17]_net_1\, B => N_599, S => - hsize_0_sqmuxa, Y => N_347); - - \Address[7]\ : DFN1 - port map(D => N_126, CLK => HCLK_c, Q => \haddr_c[7]\); - - un1_AddressSave_0_sqmuxa_1_m1 : XNOR2 - port map(A => N_566, B => \haddr_c[2]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[3]\); - - \Address_RNO_0[28]\ : AO1A - port map(A => N_753_0, B => N_975, C => \Address_0_i_0[28]\, - Y => \Address_0_i_1[28]\); - - AddressPhase_RNIORDS_0 : OR2A - port map(A => N_555, B => N_557, Y => N_753_0); - - \AddressSave_RNO[27]\ : NOR2B - port map(A => N_357, B => HRESETn_c, Y => N_261); - - \AddressSave_RNO[12]\ : NOR2B - port map(A => N_342, B => HRESETn_c, Y => N_285); - - \AddressSave[26]\ : DFN1 - port map(D => N_293, CLK => HCLK_c, Q => - \AddressSave[26]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m54 : AX1C - port map(A => \haddr_c[22]\, B => N_29_0, C => - \haddr_c[23]\, Y => N_55_0); - - un1_AddressSave_0_sqmuxa_1_m53 : XOR2 - port map(A => N_26_0, B => \haddr_c[20]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[21]\); - - AddressPhase_RNIORDS : OR2A - port map(A => N_555, B => N_557, Y => N_753); - - \DMAOut.Ready\ : DFN1 - port map(D => N_196, CLK => HCLK_c, Q => Ready); - - \AddressSave[18]\ : DFN1 - port map(D => N_524, CLK => HCLK_c, Q => - \AddressSave[18]_net_1\); - - \AddressSave_RNO[30]\ : NOR2B - port map(A => N_360, B => HRESETn_c, Y => N_532); - - \AddressSave_RNO[13]\ : NOR2B - port map(A => N_343, B => HRESETn_c, Y => N_219); - - un1_AddressSave_0_sqmuxa_1_m29 : XOR2 - port map(A => N_29_0, B => \haddr_c[22]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[23]\); - - un1_AddressSave_0_sqmuxa_1_m38 : NOR3C - port map(A => \haddr_c[26]\, B => N_36, C => \haddr_c[27]\, - Y => N_39); - - \AHBOut.hsize_RNO_0[1]\ : NOR2A - port map(A => AHB_Master_In_c_0, B => N_554, Y => N_569); - - \Address_RNO_0[26]\ : AO1A - port map(A => N_753_0, B => N_973, C => \Address_0_i_0[26]\, - Y => \Address_0_i_1[26]\); - - WriteAcc : DFN1 - port map(D => N_106, CLK => HCLK_c, Q => \WriteAcc\); - - \AHBOut.hsize_RNO_0[0]\ : NOR2B - port map(A => HRESETn_c, B => \hsize_c[0]\, Y => - \hsize_1_i_0[0]\); - - EarlyPhase_RNO_0 : MX2A - port map(A => AHB_Master_In_c_0, B => \EarlyPhase\, S => - un1_ahbin_3, Y => N_327); - - \AddressSave_RNO_0[3]\ : MX2 - port map(A => \AddressSave[3]_net_1\, B => N_595, S => - hsize_0_sqmuxa_0, Y => N_333); - - ActivePhase_RNI8O09 : OR2A - port map(A => \ActivePhase\, B => un7_dmain(66), Y => N_560); - - \Address_RNO_0[29]\ : AO1D - port map(A => N_976, B => N_753_0, C => \Address_0_i_0[29]\, - Y => \Address_0_i_1[29]\); - - un1_AddressSave_0_sqmuxa_1_m56 : XOR2 - port map(A => N_39, B => \haddr_c[28]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[29]\); - - un1_AddressSave_0_sqmuxa_1_m25 : NOR3C - port map(A => \haddr_c[18]\, B => N_22_0, C => - \haddr_c[19]\, Y => N_26_0); - - un1_AddressSave_0_sqmuxa_1_m48 : XNOR2 - port map(A => N_7_0, B => \haddr_c[7]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[8]\); - - un1_AddressSave_0_sqmuxa_1_m20 : AX1C - port map(A => \haddr_c[16]\, B => N_18_0, C => - \haddr_c[17]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[18]\); - - EarlyPhase_RNO_2 : OR2A - port map(A => \ActivePhase\, B => N_761, Y => N_568); - - \AHBOut.htrans_RNO_1[0]\ : OR3B - port map(A => \htrans_12_i_o2_2_4[0]\, B => - \htrans_12_i_o2_2_5[0]\, C => N_562, Y => - \htrans_RNO_1[0]\); - - \Address_RNO[22]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[23]\, C => - \Address_0_i_1[22]\, Y => N_171); - - \Address[9]\ : DFN1 - port map(D => N_26, CLK => HCLK_c, Q => \haddr_c[9]\); - - DataPhase_RNO : OA1C - port map(A => AHB_Master_In_c_3, B => \AddressPhase_0\, C - => DataPhase_2_i_0, Y => N_20); - - \Address_RNO[18]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[19]\, C => - \Address_0_i_1[18]\, Y => N_163); - - \Address_RNO_0[18]\ : AO1D - port map(A => N_965, B => N_753_0, C => \Address_0_i_0[18]\, - Y => \Address_0_i_1[18]\); - - \AddressSave_RNO_0[28]\ : MX2 - port map(A => \AddressSave[28]_net_1\, B => N_610, S => - hsize_0_sqmuxa, Y => N_358); - - GND_i_0 : GND - port map(Y => GND_0); - - \Address_RNO[7]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[8]\, C => - \Address_0_i_1[7]\, Y => N_126); - - \Address_RNO_1[28]\ : OAI1 - port map(A => \AddressSave[28]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[28]\); - - \Address_RNO_0[7]\ : AO1D - port map(A => N_954, B => N_753, C => \Address_0_i_0[7]\, Y - => \Address_0_i_1[7]\); - - SingleAcc : DFN1 - port map(D => N_104, CLK => HCLK_c, Q => \SingleAcc\); - - \AddressSave_RNO_0[4]\ : MX2 - port map(A => \AddressSave[4]_net_1\, B => N_586, S => - hsize_0_sqmuxa_0, Y => N_334); - - \Address_RNO_1[18]\ : OAI1 - port map(A => \AddressSave[18]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[18]\); - - \Address[6]\ : DFN1 - port map(D => N_124, CLK => HCLK_c, Q => \haddr_c[6]\); - - \AddressSave_RNO_1[30]\ : MX2 - port map(A => N_977, B => \haddr_c[30]\, S => - \AddressPhase\, Y => N_612); - - \AddressSave_RNO[9]\ : NOR2B - port map(A => N_339, B => HRESETn_c, Y => N_514); - - EarlyPhase_RNO_3 : AOI1B - port map(A => N_561, B => AHB_Master_In_c_0, C => - AHB_Master_In_c_3, Y => un1_ahbin_3_0_0); - - \Address_RNO_0[16]\ : AO1D - port map(A => N_963, B => N_753, C => \Address_0_i_0[16]\, - Y => \Address_0_i_1[16]\); - - \AddressSave_RNO_1[0]\ : MX2 - port map(A => N_947, B => \haddr_c[0]\, S => - \AddressPhase_0\, Y => N_592); - - \Address_RNO[8]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[9]\, C => - \Address_0_i_1[8]\, Y => N_153); - - \AddressSave_RNO_0[24]\ : MX2 - port map(A => \AddressSave[24]_net_1\, B => N_606, S => - hsize_0_sqmuxa, Y => N_354); - - \AddressSave[21]\ : DFN1 - port map(D => N_259, CLK => HCLK_c, Q => - \AddressSave[21]_net_1\); - - \Address_RNO_1[26]\ : OAI1 - port map(A => \AddressSave[26]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[26]\); - - \AddressSave_RNO_0[9]\ : MX2 - port map(A => \AddressSave[9]_net_1\, B => N_590, S => - hsize_0_sqmuxa_0, Y => N_339); - - un1_AddressSave_0_sqmuxa_1_m17 : NOR3C - port map(A => \haddr_c[14]\, B => N_15_0, C => - \haddr_c[15]\, Y => N_18_0); - - \AHBOut.htrans_RNO_2[0]\ : AO1D - port map(A => N_560, B => \EarlyPhase\, C => \ReAddrPhase\, - Y => N_676); - - \AddressSave_RNO_0[23]\ : MX2 - port map(A => \AddressSave[23]_net_1\, B => N_605, S => - hsize_0_sqmuxa, Y => N_353); - - SingleAcc_RNO_0 : MX2 - port map(A => \SingleAcc\, B => SingleAcc_2_sqmuxa, S => - hwrite_2_sqmuxa, Y => N_322); - - ReAddrPhase_RNI7EMV : NOR2 - port map(A => N_557, B => hwrite_2_sqmuxa_1, Y => Grant); - - \Address_RNO_1[16]\ : OAI1 - port map(A => \AddressSave[16]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[16]\); - - \Address_RNO_0[19]\ : AO1D - port map(A => N_966, B => N_753_0, C => \Address_0_i_0[19]\, - Y => \Address_0_i_1[19]\); - - \Address[11]\ : DFN1 - port map(D => \Address_RNO[11]_net_1\, CLK => HCLK_c, Q => - \haddr_c[11]\); - - \AddressSave[31]\ : DFN1 - port map(D => N_534, CLK => HCLK_c, Q => - \AddressSave[31]_net_1\); - - \Address[31]\ : DFN1 - port map(D => N_30, CLK => HCLK_c, Q => \haddr_c[31]\); - - \Address_RNO_1[29]\ : OAI1 - port map(A => \AddressSave[29]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[29]\); - - \AddressSave_RNO_0[2]\ : MX2 - port map(A => \AddressSave[2]_net_1\, B => N_594, S => - hsize_0_sqmuxa_0, Y => N_332); - - \AddressSave[13]\ : DFN1 - port map(D => N_219, CLK => HCLK_c, Q => - \AddressSave[13]_net_1\); - - AddressPhase_RNI73CK : NOR2 - port map(A => N_554, B => \AddressPhase\, Y => N_555); - - DataPhase_RNI1I7G_0 : OR2A - port map(A => Fault_0_a5_0, B => N_760, Y => Fault); - - \Address_RNO_1[19]\ : OAI1 - port map(A => \AddressSave[19]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[19]\); - - \AHBOut.hwrite_RNO_1\ : AO1B - port map(A => N_1012, B => N_560, C => N_561, Y => N_679); - - \Address_RNO[2]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[3]\, C => - \Address_0_i_1[2]\, Y => N_116); - - EarlyPhase_RNI6DT61 : OA1C - port map(A => N_561, B => N_1011, C => \un1_dmain_20_i_0\, - Y => N_193); - - \Address_RNO_1[5]\ : OAI1 - port map(A => \AddressSave[5]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[5]\); - - \Address_RNO[4]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[5]\, C => - \Address_0_i_1[4]\, Y => N_120); - - \AddressSave_RNO[14]\ : NOR2B - port map(A => N_344, B => HRESETn_c, Y => N_221); - - EarlyPhase_RNO : NOR2B - port map(A => N_327, B => HRESETn_c, Y => N_24); - - EarlyPhase_RNIHDVB : OR2 - port map(A => N_557, B => \EarlyPhase\, Y => N_758); - - \Address_RNO[25]\ : OA1B - port map(A => N_556_i_0, B => N_35, C => - \Address_0_i_1[25]\, Y => N_177); - - \Address[21]\ : DFN1 - port map(D => N_169, CLK => HCLK_c, Q => \haddr_c[21]\); - - \AddressSave_RNO[28]\ : NOR2B - port map(A => N_358, B => HRESETn_c, Y => N_263); - - \AddressSave_RNO_1[12]\ : MX2 - port map(A => N_959, B => \haddr_c[12]\, S => - \AddressPhase\, Y => N_617); - - \AddressSave_RNO_1[10]\ : MX2 - port map(A => N_957, B => \haddr_c[10]\, S => - \AddressPhase\, Y => N_615); - - ReDataPhase_RNO : NOR2B - port map(A => N_329, B => HRESETn_c, Y => N_22); - - \AHBOut.hsize_RNO[0]\ : NOR2A - port map(A => \hsize_1_i_0[0]\, B => hsize_0_sqmuxa_0, Y - => N_149); - - \AddressSave_RNO[21]\ : NOR2B - port map(A => N_351, B => HRESETn_c, Y => N_259); - - IdlePhase_RNO_0 : MX2B - port map(A => \IdlePhase\, B => N_760, S => N_189, Y => - N_326); - - un1_AddressSave_0_sqmuxa_1_m57 : AX1C - port map(A => \haddr_c[28]\, B => N_39, C => \haddr_c[29]\, - Y => N_58_0); - - \Address[17]\ : DFN1 - port map(D => N_161, CLK => HCLK_c, Q => \haddr_c[17]\); - - \AddressSave[10]\ : DFN1 - port map(D => N_516, CLK => HCLK_c, Q => - \AddressSave[10]_net_1\); - - \AddressSave_RNO_0[26]\ : MX2 - port map(A => \AddressSave[26]_net_1\, B => N_608, S => - hsize_0_sqmuxa, Y => N_356); - - \Address_RNO_1[1]\ : OAI1 - port map(A => \AddressSave[1]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[1]\); - - \Address_RNO_1[6]\ : OAI1 - port map(A => \AddressSave[6]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[6]\); - - un1_AddressSave_0_sqmuxa_1_m51 : AX1C - port map(A => \haddr_c[12]\, B => N_13_0, C => - \haddr_c[13]\, Y => \un1_AddressSave_0_sqmuxa_1_i_i[14]\); - - un1_AddressSave_0_sqmuxa_1_m34 : AX1C - port map(A => \haddr_c[24]\, B => N_32_0, C => - \haddr_c[25]\, Y => N_35); - - \Address_RNIV6FD[9]\ : NOR2B - port map(A => \haddr_c[9]\, B => \haddr_c[2]\, Y => - \htrans_12_i_o2_2_0[0]\); - - \Address[27]\ : DFN1 - port map(D => N_128, CLK => HCLK_c, Q => \haddr_c[27]\); - - \AddressSave[3]\ : DFN1 - port map(D => \AddressSave_RNO[3]_net_1\, CLK => HCLK_c, Q - => \AddressSave[3]_net_1\); - - DataPhase : DFN1 - port map(D => N_20, CLK => HCLK_c, Q => \DataPhase\); - - \AddressSave[2]\ : DFN1 - port map(D => \AddressSave_RNO[2]_net_1\, CLK => HCLK_c, Q - => \AddressSave[2]_net_1\); - - \AddressSave[27]\ : DFN1 - port map(D => N_261, CLK => HCLK_c, Q => - \AddressSave[27]_net_1\); - - AddressPhase_0 : DFN1 - port map(D => N_191, CLK => HCLK_c, Q => \AddressPhase_0\); - - \Address_RNO_0[20]\ : AO1D - port map(A => N_967, B => N_753_0, C => \Address_0_i_0[20]\, - Y => \Address_0_i_1[20]\); - - \AddressSave_RNO[8]\ : NOR2B - port map(A => N_338, B => HRESETn_c, Y => N_283); - - \AddressSave[5]\ : DFN1 - port map(D => N_281, CLK => HCLK_c, Q => - \AddressSave[5]_net_1\); - - \AddressSave[24]\ : DFN1 - port map(D => N_528, CLK => HCLK_c, Q => - \AddressSave[24]_net_1\); - - \AddressSave_RNO_1[8]\ : MX2 - port map(A => N_955, B => \haddr_c[8]\, S => \AddressPhase\, - Y => N_613); - - \Address_RNO[31]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[32]\, C => - \Address_0_i_1[31]\, Y => N_30); - - \AHBOut.htrans_RNO_4[0]\ : OR2A - port map(A => \ReAddrPhase\, B => \AddressPhase\, Y => - N_678); - - \AHBOut.htrans_RNO[0]\ : NOR3C - port map(A => \htrans_12_i_2[0]\, B => \htrans_RNO_1[0]\, C - => N_676, Y => N_137_i_0); - - un1_AddressSave_0_sqmuxa_1_m44 : XNOR2 - port map(A => N_5_0, B => \haddr_c[5]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[6]\); - - un1_AddressSave_0_sqmuxa_1_m43 : AX1 - port map(A => N_3_0, B => \haddr_c[3]\, C => \haddr_c[4]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[5]\); - - \Address_RNO[12]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[13]\, C => - \Address_0_i_1[12]\, Y => \Address_RNO[12]_net_1\); - - DataPhase_RNIGGQC_0 : NOR2A - port map(A => \DataPhase\, B => N_558, Y => N_576); - - un1_AddressSave_0_sqmuxa_1_m36 : XOR2 - port map(A => N_36, B => \haddr_c[26]\, Y => N_37); - - \Address_RNO_0[23]\ : AO1D - port map(A => N_970, B => N_753_0, C => \Address_0_i_0[23]\, - Y => \Address_0_i_1[23]\); - - un1_AddressSave_0_sqmuxa_1_m22 : XOR2 - port map(A => N_22_0, B => \haddr_c[18]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[19]\); - - \AddressSave_RNO[6]\ : NOR2B - port map(A => N_336, B => HRESETn_c, Y => N_215); - - \AddressSave_RNO_0[29]\ : MX2 - port map(A => \AddressSave[29]_net_1\, B => N_611, S => - hsize_0_sqmuxa, Y => N_359); - - \Address[1]\ : DFN1 - port map(D => N_114, CLK => HCLK_c, Q => \haddr_c[1]\); - - \AddressSave_RNO[20]\ : NOR2B - port map(A => N_350, B => HRESETn_c, Y => N_225); - - \AddressSave_RNO[17]\ : NOR2B - port map(A => N_347, B => HRESETn_c, Y => N_522); - - un1_AddressSave_0_sqmuxa_1_m46 : AX1 - port map(A => N_7_0, B => \haddr_c[7]\, C => \haddr_c[8]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[9]\); - - \AHBOut.hburst[1]\ : DFN1E1 - port map(D => N_682, CLK => HCLK_c, E => N_130, Q => - hburst_c(1)); - - ReDataPhase_RNIHO18_0 : OR2A - port map(A => \ReDataPhase\, B => N_553, Y => N_754_0); - - un1_dmain_20_i_0 : OR2A - port map(A => HRESETn_c, B => N_553, Y => - \un1_dmain_20_i_0\); - - un1_AddressSave_0_sqmuxa_1_m4 : OR3B - port map(A => \haddr_c[3]\, B => \haddr_c[4]\, C => N_3_0, - Y => N_5_0); - - ReAddrPhase_RNI25HF : NOR3A - port map(A => HRESETn_c, B => \ReAddrPhase\, C => - time_select_0, Y => \hburst_11_i_a2_i_a5_1[1]\); - - AddressPhase_RNIN7JU : OR2B - port map(A => N_756, B => N_566, Y => hsize_0_sqmuxa_0); - - BoundaryPhase_RNO_4 : OR3C - port map(A => N_829, B => N_567, C => N_1011, Y => N_684); - - \AddressSave_RNO_1[18]\ : MX2 - port map(A => N_965, B => \haddr_c[18]\, S => - \AddressPhase_0\, Y => N_600); - - \AddressSave_RNO_0[25]\ : MX2 - port map(A => \AddressSave[25]_net_1\, B => N_607, S => - hsize_0_sqmuxa, Y => N_355); - - AddressPhase_RNIKTLA : MX2C - port map(A => \AddressPhase\, B => AHB_Master_In_c_0, S => - AHB_Master_In_c_3, Y => N_614); - - \AddressSave_RNO_0[21]\ : MX2 - port map(A => \AddressSave[21]_net_1\, B => N_603, S => - hsize_0_sqmuxa, Y => N_351); - - \Address_RNO_0[10]\ : AO1D - port map(A => N_957, B => N_753, C => \Address_0_i_0[10]\, - Y => \Address_0_i_1[10]\); - - \Address_RNO[20]\ : OA1B - port map(A => N_556_i_0, B => - \un1_AddressSave_0_sqmuxa_1_i_i[21]\, C => - \Address_0_i_1[20]\, Y => N_167); - - ActivePhase_RNO_0 : AO1A - port map(A => N_639, B => \ActivePhase\, C => - hwrite_2_sqmuxa, Y => N_320); - - \AddressSave_RNO[26]\ : NOR2B - port map(A => N_356, B => HRESETn_c, Y => N_293); - - \Address_RNO_1[20]\ : OAI1 - port map(A => \AddressSave[20]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[20]\); - - \AHBOut.htrans_RNO_3[0]\ : NOR2A - port map(A => HRESETn_c, B => N_557, Y => - \htrans_12_i_0[0]\); - - \AddressSave[28]\ : DFN1 - port map(D => N_263, CLK => HCLK_c, Q => - \AddressSave[28]_net_1\); - - ReDataPhase_RNIHO18_1 : OR2 - port map(A => \ReDataPhase\, B => N_553, Y => N_557); - - \AddressSave_RNO_1[4]\ : MX2 - port map(A => N_951, B => \haddr_c[4]\, S => - \AddressPhase_0\, Y => N_586); - - EarlyPhase_RNIFRKC1 : NOR3A - port map(A => N_560, B => hwrite_2_sqmuxa_1, C => N_758, Y - => hwrite_2_sqmuxa); - - \Address_RNO_1[10]\ : OAI1 - port map(A => \AddressSave[10]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[10]\); - - \AddressSave_RNO_1[22]\ : MX2 - port map(A => N_969, B => \haddr_c[22]\, S => - \AddressPhase_0\, Y => N_604); - - \Address_RNI2O5T1[4]\ : NOR3B - port map(A => \htrans_12_i_o2_2_4[0]\, B => - \htrans_12_i_o2_2_5[0]\, C => N_566, Y => N_580); - - ReDataPhase : DFN1 - port map(D => N_22, CLK => HCLK_c, Q => \ReDataPhase\); - - \AHBOut.htrans[0]\ : DFN1E1 - port map(D => N_137_i_0, CLK => HCLK_c, E => N_189, Q => - htrans_c(0)); - - EarlyPhase_RNIQH6K : NOR2 - port map(A => un7_dmain(66), B => N_758, Y => N_829); - - BoundaryPhase_RNO_3 : OR3B - port map(A => \ReAddrPhase\, B => \AddressPhase\, C => - N_557, Y => N_686); - - un1_AddressSave_0_sqmuxa_1_m15 : XOR2 - port map(A => N_15_0, B => \haddr_c[14]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[15]\); - - ReDataPhase_RNO_0 : AO1 - port map(A => \ReDataPhase\, B => N_553, C => Retry, Y => - N_329); - - \AddressSave_RNO_1[20]\ : MX2 - port map(A => N_967, B => \haddr_c[20]\, S => - \AddressPhase_0\, Y => N_602); - - \AddressSave_RNO_1[14]\ : MX2 - port map(A => N_961, B => \haddr_c[14]\, S => - \AddressPhase_0\, Y => N_596); - - un1_AddressSave_0_sqmuxa_1_m8 : OR3B - port map(A => \haddr_c[7]\, B => \haddr_c[8]\, C => N_7_0, - Y => N_9_0); - - un1_AddressSave_0_sqmuxa_1_m28 : NOR3C - port map(A => \haddr_c[20]\, B => N_26_0, C => - \haddr_c[21]\, Y => N_29_0); - - \Address_RNO_0[13]\ : AO1D - port map(A => N_960, B => N_753, C => \Address_0_i_0[13]\, - Y => \Address_0_i_1[13]\); - - \Address_RNO[15]\ : OA1B - port map(A => N_556_i, B => - \un1_AddressSave_0_sqmuxa_1_i_i[16]\, C => - \Address_0_i_1[15]\, Y => N_157); - - ActivePhase_RNIB5HP : OR3B - port map(A => AHB_Master_In_c_0, B => N_561, C => N_560, Y - => N_582); - - un1_AddressSave_0_sqmuxa_1_m10 : XOR2 - port map(A => N_580, B => \haddr_c[10]\, Y => - \un1_AddressSave_0_sqmuxa_1_i_i[11]\); - - \AHBOut.hburst_RNO[0]\ : OA1A - port map(A => N_561, B => N_1011, C => - \hburst_11_0_a2_i_2[0]\, Y => N_56_i_0); - - \AddressSave_RNO_1[13]\ : MX2 - port map(A => N_960, B => \haddr_c[13]\, S => - \AddressPhase\, Y => N_618); - - \Address_RNO_1[23]\ : OAI1 - port map(A => \AddressSave[23]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[23]\); - - \Address_RNO_0[21]\ : AO1D - port map(A => N_968, B => N_753_0, C => \Address_0_i_0[21]\, - Y => \Address_0_i_1[21]\); - - \AddressSave[19]\ : DFN1 - port map(D => N_289, CLK => HCLK_c, Q => - \AddressSave[19]_net_1\); - - ReDataPhase_RNI5AUG : NOR2 - port map(A => N_1011, B => \ReDataPhase\, Y => N_635); - - \Address_RNO_1[13]\ : OAI1 - port map(A => \AddressSave[13]_net_1\, B => N_754, C => - HRESETn_c, Y => \Address_0_i_0[13]\); - - un1_AddressSave_0_sqmuxa_1_m59 : AX1C - port map(A => \haddr_c[30]\, B => N_41, C => \haddr_c[31]\, - Y => \un1_AddressSave_0_sqmuxa_1_i_i[32]\); - - \Address_RNO_1[9]\ : OAI1 - port map(A => \AddressSave[9]_net_1\, B => N_754_0, C => - HRESETn_c, Y => \Address_0_i_0[9]\); - - \Address_RNO_0[0]\ : AO1D - port map(A => N_947, B => N_753_0, C => \Address_0_i_0[0]\, - Y => \Address_0_i_1[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_dma is - - port( addr_data_f0 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - haddr_c : out std_logic_vector(31 downto 0); - AHB_Master_In_c_3 : in std_logic; - AHB_Master_In_c_0 : in std_logic; - AHB_Master_In_c_4 : in std_logic; - AHB_Master_In_c_5 : in std_logic; - hsize_c : out std_logic_vector(1 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0); - ready_i_0 : in std_logic_vector(3 downto 0); - data_ren : out std_logic_vector(3 downto 0); - time_ren : out std_logic_vector(3 downto 0); - time_ren_1z : out std_logic; - data_ren_1z : out std_logic; - N_43 : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - hwrite_c : out std_logic; - un20_time_write : out std_logic; - un13_time_write : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_waveform_dma; - -architecture DEF_ARCH of lpp_waveform_dma is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(2 to 2); - status_full : out std_logic_vector(2 to 2); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_3 : in std_logic_vector(5 downto 4) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(2 to 2) := (others => 'U'); - addr_data_vector_62 : out std_logic; - addr_data_vector_61 : out std_logic; - addr_data_vector_5 : in std_logic := 'U'; - addr_data_vector_4 : in std_logic := 'U'; - addr_data_vector_3 : in std_logic := 'U'; - addr_data_vector_0 : in std_logic := 'U'; - addr_data_vector_12 : in std_logic := 'U'; - addr_data_vector_11 : in std_logic := 'U'; - addr_data_vector_9 : in std_logic := 'U'; - addr_data_vector_7 : in std_logic := 'U'; - addr_data_vector_6 : in std_logic := 'U'; - addr_data_vector_26 : in std_logic := 'U'; - addr_data_vector_24 : in std_logic := 'U'; - addr_data_vector_22 : in std_logic := 'U'; - addr_data_vector_28 : in std_logic := 'U'; - addr_data_vector_66 : out std_logic; - addr_data_vector_65 : out std_logic; - addr_data_vector_91 : out std_logic; - addr_data_vector_89 : out std_logic; - addr_data_vector_87 : out std_logic; - addr_data_vector_63 : out std_logic; - addr_data_vector_72 : out std_logic; - addr_data_vector_74 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_78 : out std_logic; - addr_data_vector_81 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_84 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_83 : out std_logic; - N_1329 : out std_logic; - N_1328 : out std_logic; - N_1327 : out std_logic; - N_1324 : out std_logic; - N_1322 : out std_logic; - N_1321 : out std_logic; - N_1319 : out std_logic; - N_1317 : out std_logic; - N_1316 : out std_logic; - N_1308 : out std_logic; - N_1306 : out std_logic; - N_1304 : out std_logic; - N_1296 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(0 to 0); - status_full : out std_logic_vector(0 to 0); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_7 : in std_logic_vector(1 downto 0) := (others => 'U'); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(0 to 0) := (others => 'U'); - addr_data_vector_69 : in std_logic := 'U'; - addr_data_vector_68 : in std_logic := 'U'; - addr_data_vector_66 : in std_logic := 'U'; - addr_data_vector_77 : in std_logic := 'U'; - addr_data_vector_75 : in std_logic := 'U'; - addr_data_vector_86 : in std_logic := 'U'; - addr_data_vector_85 : in std_logic := 'U'; - addr_data_vector_84 : in std_logic := 'U'; - addr_data_vector_83 : in std_logic := 'U'; - addr_data_vector_82 : in std_logic := 'U'; - addr_data_vector_81 : in std_logic := 'U'; - addr_data_vector_80 : in std_logic := 'U'; - addr_data_vector_92 : in std_logic := 'U'; - addr_data_vector_90 : in std_logic := 'U'; - addr_data_vector_88 : in std_logic := 'U'; - addr_data_vector_87 : in std_logic := 'U'; - addr_data_vector_94 : in std_logic := 'U'; - addr_data_vector_65 : in std_logic := 'U'; - addr_data_vector_64 : in std_logic := 'U'; - addr_data_vector_3 : out std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_27 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_25 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_8 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_12 : out std_logic; - N_1326 : out std_logic; - N_1325 : out std_logic; - N_1323 : out std_logic; - N_1320 : out std_logic; - N_1318 : out std_logic; - N_1315 : out std_logic; - N_1314 : out std_logic; - N_1313 : out std_logic; - N_1312 : out std_logic; - N_1311 : out std_logic; - N_1310 : out std_logic; - N_1309 : out std_logic; - N_1307 : out std_logic; - N_1305 : out std_logic; - N_1303 : out std_logic; - N_1302 : out std_logic; - N_1295 : out std_logic; - N_1280 : out std_logic; - N_1279 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_dma_send_16word - port( un7_dmain : out std_logic_vector(66 to 66); - data_address : in std_logic_vector(31 downto 0) := (others => 'U'); - Store : out std_logic; - Fault : in std_logic := 'U'; - un1_data_send_ok : out std_logic; - Request_0 : in std_logic := 'U'; - N_1011 : out std_logic; - Lock_0 : in std_logic := 'U'; - N_1013 : out std_logic; - N_957 : out std_logic; - N_956 : out std_logic; - N_955 : out std_logic; - N_954 : out std_logic; - N_953 : out std_logic; - N_952 : out std_logic; - N_951 : out std_logic; - N_964 : out std_logic; - N_963 : out std_logic; - N_962 : out std_logic; - N_961 : out std_logic; - N_960 : out std_logic; - time_select : in std_logic := 'U'; - N_959 : out std_logic; - N_958 : out std_logic; - N_971 : out std_logic; - N_970 : out std_logic; - N_969 : out std_logic; - N_968 : out std_logic; - N_967 : out std_logic; - N_966 : out std_logic; - N_965 : out std_logic; - N_978 : out std_logic; - N_977 : out std_logic; - N_976 : out std_logic; - N_975 : out std_logic; - N_974 : out std_logic; - N_973 : out std_logic; - N_972 : out std_logic; - N_950 : out std_logic; - N_949 : out std_logic; - N_948 : out std_logic; - time_select_0 : in std_logic := 'U'; - N_947 : out std_logic; - N_249 : out std_logic; - Grant : in std_logic := 'U'; - Ready : in std_logic := 'U'; - data_send : in std_logic := 'U'; - OKAY : in std_logic := 'U'; - N_200 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(1 to 1); - status_full : out std_logic_vector(1 to 1); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_5 : in std_logic_vector(3 downto 2) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_vector_94 : in std_logic := 'U'; - addr_data_vector_91 : in std_logic := 'U'; - addr_data_vector_89 : in std_logic := 'U'; - addr_data_vector_87 : in std_logic := 'U'; - addr_data_vector_86 : in std_logic := 'U'; - addr_data_vector_85 : in std_logic := 'U'; - addr_data_vector_84 : in std_logic := 'U'; - addr_data_vector_83 : in std_logic := 'U'; - addr_data_vector_67 : in std_logic := 'U'; - addr_data_vector_66 : in std_logic := 'U'; - addr_data_vector_65 : in std_logic := 'U'; - addr_data_vector_64 : in std_logic := 'U'; - addr_data_vector_75 : in std_logic := 'U'; - addr_data_vector_73 : in std_logic := 'U'; - addr_data_vector_81 : in std_logic := 'U'; - addr_data_vector_79 : in std_logic := 'U'; - addr_data_vector_77 : in std_logic := 'U'; - addr_data_vector_24 : out std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_16 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_18 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_5 : out std_logic; - addr_data_vector_4 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_12 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_8 : out std_logic; - N_913 : out std_logic; - N_910 : out std_logic; - N_908 : out std_logic; - N_906 : out std_logic; - N_905 : out std_logic; - N_904 : out std_logic; - N_903 : out std_logic; - N_902 : out std_logic; - N_1300 : out std_logic; - N_1299 : out std_logic; - N_1298 : out std_logic; - N_1297 : out std_logic; - N_1294 : out std_logic; - N_1292 : out std_logic; - N_1286 : out std_logic; - N_1284 : out std_logic; - N_1282 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component lpp_dma_send_1word - port( Lock : out std_logic; - Request : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - un1_time_send_ok : out std_logic; - time_select : in std_logic := 'U'; - Store : in std_logic := 'U'; - N_1012 : out std_logic; - Ready : in std_logic := 'U'; - Fault : in std_logic := 'U'; - time_send : in std_logic := 'U'; - Grant : in std_logic := 'U' - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(3 to 3); - status_full : out std_logic_vector(3 to 3); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_1 : in std_logic_vector(7 downto 6) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(3 to 3) := (others => 'U'); - addr_data_vector_61 : out std_logic; - addr_data_vector_60 : out std_logic; - addr_data_vector_27 : in std_logic := 'U'; - addr_data_vector_25 : in std_logic := 'U'; - addr_data_vector_24 : in std_logic := 'U'; - addr_data_vector_22 : in std_logic := 'U'; - addr_data_vector_20 : in std_logic := 'U'; - addr_data_vector_0 : in std_logic := 'U'; - addr_data_vector_6 : in std_logic := 'U'; - addr_data_vector_4 : in std_logic := 'U'; - addr_data_vector_3 : in std_logic := 'U'; - addr_data_vector_2 : in std_logic := 'U'; - addr_data_vector_1 : in std_logic := 'U'; - addr_data_vector_14 : in std_logic := 'U'; - addr_data_vector_12 : in std_logic := 'U'; - addr_data_vector_10 : in std_logic := 'U'; - addr_data_vector_8 : in std_logic := 'U'; - addr_data_vector_63 : out std_logic; - addr_data_vector_90 : out std_logic; - addr_data_vector_87 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_62 : out std_logic; - addr_data_vector_69 : out std_logic; - addr_data_vector_73 : out std_logic; - addr_data_vector_71 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_83 : out std_logic; - addr_data_vector_75 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_81 : out std_logic; - N_914 : out std_logic; - N_912 : out std_logic; - N_911 : out std_logic; - N_909 : out std_logic; - N_907 : out std_logic; - N_1301 : out std_logic; - N_1293 : out std_logic; - N_1291 : out std_logic; - N_1290 : out std_logic; - N_1289 : out std_logic; - N_1288 : out std_logic; - N_1287 : out std_logic; - N_1285 : out std_logic; - N_1283 : out std_logic; - N_1281 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component DMA2AHB - port( hburst_c : out std_logic_vector(2 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - un7_dmain : in std_logic_vector(66 to 66) := (others => 'U'); - hsize_c : out std_logic_vector(1 downto 0); - AHB_Master_In_c_5 : in std_logic := 'U'; - AHB_Master_In_c_4 : in std_logic := 'U'; - AHB_Master_In_c_0 : in std_logic := 'U'; - AHB_Master_In_c_3 : in std_logic := 'U'; - haddr_c : out std_logic_vector(31 downto 0); - hwrite_c : out std_logic; - Ready : out std_logic; - N_1012 : in std_logic := 'U'; - Grant : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - OKAY : out std_logic; - Fault : out std_logic; - N_1011 : in std_logic := 'U'; - N_1013 : in std_logic := 'U'; - N_43 : out std_logic; - time_select_0 : in std_logic := 'U'; - N_960 : in std_logic := 'U'; - N_959 : in std_logic := 'U'; - N_958 : in std_logic := 'U'; - N_957 : in std_logic := 'U'; - N_964 : in std_logic := 'U'; - N_963 : in std_logic := 'U'; - N_962 : in std_logic := 'U'; - N_961 : in std_logic := 'U'; - N_955 : in std_logic := 'U'; - N_954 : in std_logic := 'U'; - N_953 : in std_logic := 'U'; - N_952 : in std_logic := 'U'; - N_951 : in std_logic := 'U'; - N_950 : in std_logic := 'U'; - N_949 : in std_logic := 'U'; - N_948 : in std_logic := 'U'; - N_947 : in std_logic := 'U'; - N_956 : in std_logic := 'U'; - N_965 : in std_logic := 'U'; - N_966 : in std_logic := 'U'; - N_967 : in std_logic := 'U'; - N_968 : in std_logic := 'U'; - N_969 : in std_logic := 'U'; - N_970 : in std_logic := 'U'; - N_971 : in std_logic := 'U'; - N_972 : in std_logic := 'U'; - N_973 : in std_logic := 'U'; - N_974 : in std_logic := 'U'; - N_975 : in std_logic := 'U'; - N_976 : in std_logic := 'U'; - N_977 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - N_978 : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal count_send_time_e18_0_0, \count_send_time[18]_net_1\, - N_1220, N_1099, \count_send_time_RNO[17]_net_1\, N_1091, - N_1096, N_1137, \count_send_time_RNO[28]_net_1\, N_1156, - \count_send_time[28]_net_1\, - \count_send_time_RNO[29]_net_1\, N_1160, - \count_send_time[29]_net_1\, count_send_time_e31, N_1191, - N_1193, N_1194, count_send_time_e30, N_1126, - count_send_time_e30_0_0, N_1128, N_1146, - \count_send_time[27]_net_1\, count_send_time_e30_0_a2_2_1, - count_send_time_e25, N_1178, N_1177, N_1180, - count_send_time_e24, N_1173, N_1172, N_1175, N_1161, - \count_send_time[31]_net_1\, \state[2]_net_1\, N_1162, - N_1145_0, \count_send_time[25]_net_1\, - count_send_time_e25_0_o3_N_7_i_0, - \count_send_time[23]_net_1\, N_1069, - count_send_time_e24_0_a2_1_0, - count_send_time_e24_0_a2_0_0, count_send_time_e23, N_1121, - N_1122, N_1123, count_send_time_e22, N_1117, N_1118, - N_1119, count_send_time_e21, N_1112, N_1113, N_1114, - count_send_time_e20, N_1107, N_1108, N_1109, - count_send_time_e19, N_1103, N_1102, N_1104, - count_send_time_e18, count_send_time_e30_0_a2_0_0, - \count_send_time[21]_net_1\, N_1066, - count_send_time_e22_0_a2_1_0, count_send_time_e22_0_a2_0, - N_1145, N_1063, \count_send_time[19]_net_1\, - count_send_time_e20_0_a2_1_0, count_send_time_e20_0_a2_0, - \count_send_time[17]_net_1\, N_1061, - count_send_time_e18_0_a2_0_0, N_1059, - \count_send_time[15]_net_1\, - count_send_time_e25_0_o3_m6_0_a2_7, N_1057, - \count_send_time[11]_net_1\, \count_send_time[12]_net_1\, - N_1159, \count_send_time[13]_net_1\, - \count_send_time[14]_net_1\, \count_send_time[16]_net_1\, - \count_send_time[20]_net_1\, \count_send_time[22]_net_1\, - \count_send_time_RNO[26]_net_1\, N_1163, - \count_send_time[26]_net_1\, - \count_send_time_RNO[27]_net_1\, N_1164, - \count_send_time[9]_net_1\, \count_send_time[10]_net_1\, - N_1225, N_1217, \count_send_time[0]_net_1\, - \count_send_time[1]_net_1\, \count_send_time[2]_net_1\, - N_1219, \count_send_time[3]_net_1\, - \count_send_time[4]_net_1\, N_1223, - \count_send_time[5]_net_1\, \count_send_time[6]_net_1\, - \count_send_time[7]_net_1\, \count_send_time[8]_net_1\, - \sel_data_0[0]_net_1\, N_1016_i_0, \state[7]_net_1\, - \sel_data_1[1]_net_1\, N_1015, \sel_data_0[1]_net_1\, - \state_0[2]_net_1\, \state_ns_i_a2_0[5]_net_1\, - \time_select_0\, time_fifo_ren_1, N_816, - time_fifo_ren_1_i, N_1049, N_1026, \state[4]_net_1\, - \state_ns_i_a2_0_1[5]\, N_1048, \state_ns_i_a2_0_0[5]\, - \count_send_time[24]_net_1\, \count_send_time[30]_net_1\, - N_1125, N_1075, count_send_time_e16_i_0, N_1077, - \state_ns_i_a2_0_a4_0_19_i[5]\, N_1050, - count_send_time_e25_0_o3_m6_0_a2_2, - count_send_time_e25_0_o3_m6_0_a2_1, - count_send_time_e25_0_o3_m6_0_a2_6, - count_send_time_e25_0_o3_m6_0_a2_4, - count_send_time_e14_i_0, - \count_send_time_RNO_1[14]_net_1\, state_tr2_i_0, - \send_16_3_time[0]_net_1\, - \state_ns_i_a2_0_a3_0[5]_net_1\, - \send_16_3_time_1_sqmuxa_i_o3_0\, - count_send_time_e12_0_a2_0_0, - count_send_time_e12_0_a2_1_0, count_send_time_e10_0_a2_0, - count_send_time_e10_0_a2_1_0, count_send_time_e8_0_a2_0, - count_send_time_e8_0_a2_1_0, count_send_time_e2_0_a2_1_0, - state_tr13_0_a2_15, state_tr13_0_a2_9_0, - state_tr13_0_a2_8, state_tr13_0_a2_12, state_tr13_0_a2_14, - state_tr13_0_a2_10, state_tr13_0_a2_9, state_tr13_0_a2_7, - state_tr13_0_a2_17_0, state_tr13_0_a2_17_1, - state_tr13_0_a2_6, state_tr13_0_a2_4, state_tr13_0_a2_2, - \state_ns_i_a2_0_a4_0_19_15[5]\, N_1047_25, - \state_ns_i_a2_0_a4_0_19_12[5]\, - \state_ns_i_a2_0_a4_0_19_11[5]\, N_1047_5, - \state_ns_i_a2_0_a4_0_25_4[5]\, - \state_ns_i_a2_0_a4_0_25_2[5]\, - \state_ns_i_a2_0_a4_0_25_1[5]\, - \state_ns_i_a2_0_a4_0_25_0[5]\, - count_send_time_e2_0_a2_0_0, un1_state_13_0_a4_0_0, - \state[1]_net_1\, \state[3]_net_1\, - \state_ns_i_a2_0_a4_0_19_9_0[5]\, - \count_send_time_RNO[14]_net_1\, - \count_send_time_RNO[15]_net_1\, N_1092, - \count_send_time_RNO[16]_net_1\, - \count_send_time_RNO[6]_net_1\, N_1253, N_1230, - \count_send_time_RNO[7]_net_1\, \state_ns[6]\, - count_send_time_e10, N_1270, N_1272, N_1273, - count_send_time_e9, N_1265, N_1267, N_1268, - count_send_time_e8, N_1260, N_1262, N_1263, - count_send_time_e3, N_1249, N_1247, N_1246, - count_send_time_e2, N_1244, N_1242, N_1241, - count_send_time_e1, N_1239, N_1237, N_1236, - count_send_time_e11, N_1167, N_1169, N_1170, - count_send_time_e13, N_1086, N_1085, N_1087, - count_send_time_e12, N_1081, N_1080, N_1082, - \state_RNO[6]_net_1\, N_1027, N_1036, N_812, - \state[0]_net_1\, N_1037, un5_time_write, - \sel_data[1]_net_1\, \un13_time_write\, \un20_time_write\, - un27_time_write, un7_time_write, \time_write\, - un15_time_write, un22_time_write, un29_time_write, - un2_status_full_ack, un7_status_full_ack, - un12_status_full_ack, un17_status_full_ack, \data_ren\, - N_200, N_249, \time_select\, \time_ren\, - \update_and_sel_1[6]\, \update[0]_net_1\, - \update_and_sel_1[7]\, \update[1]_net_1\, - \update_and_sel_3[4]\, \update_and_sel_3[5]\, - \update_and_sel_5[2]\, \update_and_sel_5[3]\, - \update_and_sel_7[0]\, \update_and_sel_7[1]\, - \data_address[0]\, N_1279, N_1297, \data_address[1]\, - N_1280, N_1298, \data_address[2]\, N_1323, N_1299, - \data_address[3]\, N_1324, N_1300, \data_address[4]\, - N_1325, N_1301, \data_address[5]\, N_1326, N_1288, - \data_address[6]\, N_1327, N_1289, \data_address[7]\, - N_1328, N_1290, \data_address[8]\, N_1329, N_1291, - \data_address[9]\, N_1316, N_1292, \data_address[10]\, - N_1317, N_1293, \data_address[11]\, N_1318, N_1294, - \data_address[12]\, N_1319, N_1281, \data_address[13]\, - N_1320, N_1282, \data_address[14]\, N_1321, N_1283, - \sel_data[0]_net_1\, \data_address[15]\, N_1322, N_1284, - \data_address[16]\, N_1309, N_1285, \data_address[17]\, - N_1310, N_1286, \data_address[18]\, N_1311, N_1287, - \data_address[19]\, N_1312, N_902, \data_address[20]\, - N_1313, N_903, \data_address[21]\, N_1314, N_904, - \data_address[22]\, N_1315, N_905, \data_address[23]\, - N_1302, N_906, \data_address[24]\, N_1303, N_907, - \data_address[25]\, N_1304, N_908, \data_address[26]\, - N_1305, N_909, \data_address[27]\, N_1306, N_910, - \data_address[28]\, N_1307, N_911, \data_address[29]\, - N_1308, N_912, \data_address[30]\, N_1295, N_913, - \data_address[31]\, N_1296, N_914, N_1024, - \time_already_send[3]\, \time_already_send[2]\, N_1025, - \time_already_send[1]\, \count_send_time_RNO_1[6]_net_1\, - count_send_time_e0, \count_send_time_RNO[4]_net_1\, - N_1227, \count_send_time_RNO[5]_net_1\, N_1228, - \state_RNO_1[0]\, un1_data_send_ok, N_815, N_1040, N_1014, - \state_RNO[7]_net_1\, \time_fifo_ren\, N_1030, - un1_state_12, \state[6]_net_1\, \time_already_send[0]\, - \state_RNO_2[3]\, N_1033, \state_RNO_0[4]_net_1\, N_1044, - \state_RNO[5]_net_1\, N_1042, un1_state_13, - un1_time_send_ok, \state[5]_net_1\, time_send_0_sqmuxa, - update_0_sqmuxa, \time_send\, \data_send\, - \send_16_3_time[2]_net_1\, \send_16_3_time[1]_net_1\, - \un7_dmain[66]\, Ready, N_1012, Grant, OKAY, Fault, - N_1011, N_1013, N_960, N_959, N_958, N_957, N_964, N_963, - N_962, N_961, N_955, N_954, N_953, N_952, N_951, N_950, - N_949, N_948, N_947, N_956, N_965, N_966, N_967, N_968, - N_969, N_970, N_971, N_972, N_973, N_974, N_975, N_976, - N_977, N_978, Lock, Request, Store, - \addr_data_vector[97]\, \addr_data_vector[96]\, - \addr_data_vector[63]\, \addr_data_vector[61]\, - \addr_data_vector[60]\, \addr_data_vector[58]\, - \addr_data_vector[56]\, \addr_data_vector[36]\, - \addr_data_vector[42]\, \addr_data_vector[40]\, - \addr_data_vector[39]\, \addr_data_vector[38]\, - \addr_data_vector[37]\, \addr_data_vector[50]\, - \addr_data_vector[48]\, \addr_data_vector[46]\, - \addr_data_vector[44]\, \addr_data_vector[99]\, - \addr_data_vector[126]\, \addr_data_vector[123]\, - \addr_data_vector[121]\, \addr_data_vector[98]\, - \addr_data_vector[105]\, \addr_data_vector[109]\, - \addr_data_vector[107]\, \addr_data_vector[113]\, - \addr_data_vector[115]\, \addr_data_vector[118]\, - \addr_data_vector[119]\, \addr_data_vector[111]\, - \addr_data_vector[116]\, \addr_data_vector[117]\, - \addr_data_vector[65]\, \addr_data_vector[64]\, - \addr_data_vector[8]\, \addr_data_vector[7]\, - \addr_data_vector[6]\, \addr_data_vector[3]\, - \addr_data_vector[15]\, \addr_data_vector[14]\, - \addr_data_vector[12]\, \addr_data_vector[10]\, - \addr_data_vector[9]\, \addr_data_vector[29]\, - \addr_data_vector[27]\, \addr_data_vector[25]\, - \addr_data_vector[31]\, \addr_data_vector[69]\, - \addr_data_vector[68]\, \addr_data_vector[94]\, - \addr_data_vector[92]\, \addr_data_vector[90]\, - \addr_data_vector[66]\, \addr_data_vector[75]\, - \addr_data_vector[77]\, \addr_data_vector[82]\, - \addr_data_vector[81]\, \addr_data_vector[84]\, - \addr_data_vector[83]\, \addr_data_vector[87]\, - \addr_data_vector[88]\, \addr_data_vector[80]\, - \addr_data_vector[85]\, \addr_data_vector[86]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\(DEF_ARCH); - for all : lpp_dma_send_16word - Use entity work.lpp_dma_send_16word(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\(DEF_ARCH); - for all : lpp_dma_send_1word - Use entity work.lpp_dma_send_1word(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\(DEF_ARCH); - for all : DMA2AHB - Use entity work.DMA2AHB(DEF_ARCH); -begin - - time_ren_1z <= \time_ren\; - data_ren_1z <= \data_ren\; - un20_time_write <= \un20_time_write\; - un13_time_write <= \un13_time_write\; - - \state[0]\ : DFN1C0 - port map(D => \state_RNO_1[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[0]_net_1\); - - \count_send_time_RNO_0[9]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[9]_net_1\, C => N_1225, Y => N_1265); - - \count_send_time_RNO_4[30]\ : OR3C - port map(A => N_1075, B => \count_send_time[30]_net_1\, C - => N_1091, Y => N_1125); - - \sel_data[0]\ : DFN1E1C0 - port map(D => N_1016_i_0, CLK => HCLK_c, CLR => HRESETn_c, - E => \state[7]_net_1\, Q => \sel_data[0]_net_1\); - - \gen_select_address.2.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(2) => status_full_err(2), status_full(2) - => status_full(2), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, sel_data_0(1) => - \sel_data_0[1]_net_1\, update_and_sel_3(5) => - \update_and_sel_3[5]\, update_and_sel_3(4) => - \update_and_sel_3[4]\, addr_data_f2(31) => - addr_data_f2(31), addr_data_f2(30) => addr_data_f2(30), - addr_data_f2(29) => addr_data_f2(29), addr_data_f2(28) - => addr_data_f2(28), addr_data_f2(27) => - addr_data_f2(27), addr_data_f2(26) => addr_data_f2(26), - addr_data_f2(25) => addr_data_f2(25), addr_data_f2(24) - => addr_data_f2(24), addr_data_f2(23) => - addr_data_f2(23), addr_data_f2(22) => addr_data_f2(22), - addr_data_f2(21) => addr_data_f2(21), addr_data_f2(20) - => addr_data_f2(20), addr_data_f2(19) => - addr_data_f2(19), addr_data_f2(18) => addr_data_f2(18), - addr_data_f2(17) => addr_data_f2(17), addr_data_f2(16) - => addr_data_f2(16), addr_data_f2(15) => - addr_data_f2(15), addr_data_f2(14) => addr_data_f2(14), - addr_data_f2(13) => addr_data_f2(13), addr_data_f2(12) - => addr_data_f2(12), addr_data_f2(11) => - addr_data_f2(11), addr_data_f2(10) => addr_data_f2(10), - addr_data_f2(9) => addr_data_f2(9), addr_data_f2(8) => - addr_data_f2(8), addr_data_f2(7) => addr_data_f2(7), - addr_data_f2(6) => addr_data_f2(6), addr_data_f2(5) => - addr_data_f2(5), addr_data_f2(4) => addr_data_f2(4), - addr_data_f2(3) => addr_data_f2(3), addr_data_f2(2) => - addr_data_f2(2), addr_data_f2(1) => addr_data_f2(1), - addr_data_f2(0) => addr_data_f2(0), status_full_ack(2) - => status_full_ack(2), addr_data_vector_62 => - \addr_data_vector[65]\, addr_data_vector_61 => - \addr_data_vector[64]\, addr_data_vector_5 => - \addr_data_vector[8]\, addr_data_vector_4 => - \addr_data_vector[7]\, addr_data_vector_3 => - \addr_data_vector[6]\, addr_data_vector_0 => - \addr_data_vector[3]\, addr_data_vector_12 => - \addr_data_vector[15]\, addr_data_vector_11 => - \addr_data_vector[14]\, addr_data_vector_9 => - \addr_data_vector[12]\, addr_data_vector_7 => - \addr_data_vector[10]\, addr_data_vector_6 => - \addr_data_vector[9]\, addr_data_vector_26 => - \addr_data_vector[29]\, addr_data_vector_24 => - \addr_data_vector[27]\, addr_data_vector_22 => - \addr_data_vector[25]\, addr_data_vector_28 => - \addr_data_vector[31]\, addr_data_vector_66 => - \addr_data_vector[69]\, addr_data_vector_65 => - \addr_data_vector[68]\, addr_data_vector_91 => - \addr_data_vector[94]\, addr_data_vector_89 => - \addr_data_vector[92]\, addr_data_vector_87 => - \addr_data_vector[90]\, addr_data_vector_63 => - \addr_data_vector[66]\, addr_data_vector_72 => - \addr_data_vector[75]\, addr_data_vector_74 => - \addr_data_vector[77]\, addr_data_vector_79 => - \addr_data_vector[82]\, addr_data_vector_78 => - \addr_data_vector[81]\, addr_data_vector_81 => - \addr_data_vector[84]\, addr_data_vector_80 => - \addr_data_vector[83]\, addr_data_vector_84 => - \addr_data_vector[87]\, addr_data_vector_85 => - \addr_data_vector[88]\, addr_data_vector_77 => - \addr_data_vector[80]\, addr_data_vector_82 => - \addr_data_vector[85]\, addr_data_vector_83 => - \addr_data_vector[86]\, N_1329 => N_1329, N_1328 => - N_1328, N_1327 => N_1327, N_1324 => N_1324, N_1322 => - N_1322, N_1321 => N_1321, N_1319 => N_1319, N_1317 => - N_1317, N_1316 => N_1316, N_1308 => N_1308, N_1306 => - N_1306, N_1304 => N_1304, N_1296 => N_1296, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \count_send_time_RNIRUBI[20]\ : NOR3C - port map(A => count_send_time_e25_0_o3_m6_0_a2_2, B => - count_send_time_e25_0_o3_m6_0_a2_1, C => - count_send_time_e25_0_o3_m6_0_a2_6, Y => - count_send_time_e25_0_o3_m6_0_a2_7); - - \count_send_time_RNO_0[16]\ : OAI1 - port map(A => N_1077, B => \count_send_time[16]_net_1\, C - => N_1091, Y => count_send_time_e16_i_0); - - \count_send_time_RNO_2[1]\ : OR2B - port map(A => \count_send_time[1]_net_1\, B => N_1220, Y - => N_1236); - - \count_send_time_RNO[4]\ : XA1A - port map(A => N_1227, B => \count_send_time[4]_net_1\, C - => N_1091, Y => \count_send_time_RNO[4]_net_1\); - - \count_send_time_RNINOP61[10]\ : OR3B - port map(A => \count_send_time[9]_net_1\, B => - \count_send_time[10]_net_1\, C => N_1225, Y => N_1159); - - \gen_select_address.0.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(0) => status_full_err(0), status_full(0) - => status_full(0), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, sel_data_0(1) => - \sel_data_0[1]_net_1\, update_and_sel_7(1) => - \update_and_sel_7[1]\, update_and_sel_7(0) => - \update_and_sel_7[0]\, addr_data_f0(31) => - addr_data_f0(31), addr_data_f0(30) => addr_data_f0(30), - addr_data_f0(29) => addr_data_f0(29), addr_data_f0(28) - => addr_data_f0(28), addr_data_f0(27) => - addr_data_f0(27), addr_data_f0(26) => addr_data_f0(26), - addr_data_f0(25) => addr_data_f0(25), addr_data_f0(24) - => addr_data_f0(24), addr_data_f0(23) => - addr_data_f0(23), addr_data_f0(22) => addr_data_f0(22), - addr_data_f0(21) => addr_data_f0(21), addr_data_f0(20) - => addr_data_f0(20), addr_data_f0(19) => - addr_data_f0(19), addr_data_f0(18) => addr_data_f0(18), - addr_data_f0(17) => addr_data_f0(17), addr_data_f0(16) - => addr_data_f0(16), addr_data_f0(15) => - addr_data_f0(15), addr_data_f0(14) => addr_data_f0(14), - addr_data_f0(13) => addr_data_f0(13), addr_data_f0(12) - => addr_data_f0(12), addr_data_f0(11) => - addr_data_f0(11), addr_data_f0(10) => addr_data_f0(10), - addr_data_f0(9) => addr_data_f0(9), addr_data_f0(8) => - addr_data_f0(8), addr_data_f0(7) => addr_data_f0(7), - addr_data_f0(6) => addr_data_f0(6), addr_data_f0(5) => - addr_data_f0(5), addr_data_f0(4) => addr_data_f0(4), - addr_data_f0(3) => addr_data_f0(3), addr_data_f0(2) => - addr_data_f0(2), addr_data_f0(1) => addr_data_f0(1), - addr_data_f0(0) => addr_data_f0(0), status_full_ack(0) - => status_full_ack(0), addr_data_vector_69 => - \addr_data_vector[69]\, addr_data_vector_68 => - \addr_data_vector[68]\, addr_data_vector_66 => - \addr_data_vector[66]\, addr_data_vector_77 => - \addr_data_vector[77]\, addr_data_vector_75 => - \addr_data_vector[75]\, addr_data_vector_86 => - \addr_data_vector[86]\, addr_data_vector_85 => - \addr_data_vector[85]\, addr_data_vector_84 => - \addr_data_vector[84]\, addr_data_vector_83 => - \addr_data_vector[83]\, addr_data_vector_82 => - \addr_data_vector[82]\, addr_data_vector_81 => - \addr_data_vector[81]\, addr_data_vector_80 => - \addr_data_vector[80]\, addr_data_vector_92 => - \addr_data_vector[92]\, addr_data_vector_90 => - \addr_data_vector[90]\, addr_data_vector_88 => - \addr_data_vector[88]\, addr_data_vector_87 => - \addr_data_vector[87]\, addr_data_vector_94 => - \addr_data_vector[94]\, addr_data_vector_65 => - \addr_data_vector[65]\, addr_data_vector_64 => - \addr_data_vector[64]\, addr_data_vector_3 => - \addr_data_vector[3]\, addr_data_vector_31 => - \addr_data_vector[31]\, addr_data_vector_14 => - \addr_data_vector[14]\, addr_data_vector_15 => - \addr_data_vector[15]\, addr_data_vector_27 => - \addr_data_vector[27]\, addr_data_vector_29 => - \addr_data_vector[29]\, addr_data_vector_25 => - \addr_data_vector[25]\, addr_data_vector_6 => - \addr_data_vector[6]\, addr_data_vector_8 => - \addr_data_vector[8]\, addr_data_vector_7 => - \addr_data_vector[7]\, addr_data_vector_10 => - \addr_data_vector[10]\, addr_data_vector_9 => - \addr_data_vector[9]\, addr_data_vector_12 => - \addr_data_vector[12]\, N_1326 => N_1326, N_1325 => - N_1325, N_1323 => N_1323, N_1320 => N_1320, N_1318 => - N_1318, N_1315 => N_1315, N_1314 => N_1314, N_1313 => - N_1313, N_1312 => N_1312, N_1311 => N_1311, N_1310 => - N_1310, N_1309 => N_1309, N_1307 => N_1307, N_1305 => - N_1305, N_1303 => N_1303, N_1302 => N_1302, N_1295 => - N_1295, N_1280 => N_1280, N_1279 => N_1279, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \count_send_time_RNIFF6R1[20]\ : OR3C - port map(A => N_1063, B => \count_send_time[19]_net_1\, C - => \count_send_time[20]_net_1\, Y => N_1066); - - \sel_data_0_RNI0MA8[0]\ : OR2B - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => un5_time_write); - - \count_send_time_RNO[26]\ : XA1A - port map(A => N_1163, B => \count_send_time[26]_net_1\, C - => N_1091, Y => \count_send_time_RNO[26]_net_1\); - - \count_send_time_RNINK24[24]\ : NOR2B - port map(A => \count_send_time[24]_net_1\, B => - \count_send_time[18]_net_1\, Y => - count_send_time_e25_0_o3_m6_0_a2_1); - - \sel_data_RNIM70E[0]\ : MX2C - port map(A => N_1308, B => N_912, S => \sel_data[0]_net_1\, - Y => \data_address[29]\); - - \all_time_write.0.time_already_send_RNI944DP[0]\ : MX2 - port map(A => N_1025, B => \time_already_send[0]\, S => - ready_i_0(0), Y => N_1026); - - \count_send_time[0]\ : DFN1 - port map(D => count_send_time_e0, CLK => HCLK_c, Q => - \count_send_time[0]_net_1\); - - \count_send_time_RNO_3[2]\ : OR3B - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => - \count_send_time[2]_net_1\, Y => - count_send_time_e2_0_a2_1_0); - - \count_send_time_RNO_0[10]\ : AO1C - port map(A => N_1225, B => \count_send_time[9]_net_1\, C - => count_send_time_e10_0_a2_0, Y => N_1270); - - \count_send_time_RNO[2]\ : OR3C - port map(A => N_1244, B => N_1242, C => N_1241, Y => - count_send_time_e2); - - time_fifo_ren_RNO : INV - port map(A => time_fifo_ren_1, Y => time_fifo_ren_1_i); - - lpp_dma_send_16word_1 : lpp_dma_send_16word - port map(un7_dmain(66) => \un7_dmain[66]\, data_address(31) - => \data_address[31]\, data_address(30) => - \data_address[30]\, data_address(29) => - \data_address[29]\, data_address(28) => - \data_address[28]\, data_address(27) => - \data_address[27]\, data_address(26) => - \data_address[26]\, data_address(25) => - \data_address[25]\, data_address(24) => - \data_address[24]\, data_address(23) => - \data_address[23]\, data_address(22) => - \data_address[22]\, data_address(21) => - \data_address[21]\, data_address(20) => - \data_address[20]\, data_address(19) => - \data_address[19]\, data_address(18) => - \data_address[18]\, data_address(17) => - \data_address[17]\, data_address(16) => - \data_address[16]\, data_address(15) => - \data_address[15]\, data_address(14) => - \data_address[14]\, data_address(13) => - \data_address[13]\, data_address(12) => - \data_address[12]\, data_address(11) => - \data_address[11]\, data_address(10) => - \data_address[10]\, data_address(9) => \data_address[9]\, - data_address(8) => \data_address[8]\, data_address(7) => - \data_address[7]\, data_address(6) => \data_address[6]\, - data_address(5) => \data_address[5]\, data_address(4) => - \data_address[4]\, data_address(3) => \data_address[3]\, - data_address(2) => \data_address[2]\, data_address(1) => - \data_address[1]\, data_address(0) => \data_address[0]\, - Store => Store, Fault => Fault, un1_data_send_ok => - un1_data_send_ok, Request_0 => Request, N_1011 => N_1011, - Lock_0 => Lock, N_1013 => N_1013, N_957 => N_957, N_956 - => N_956, N_955 => N_955, N_954 => N_954, N_953 => N_953, - N_952 => N_952, N_951 => N_951, N_964 => N_964, N_963 => - N_963, N_962 => N_962, N_961 => N_961, N_960 => N_960, - time_select => \time_select\, N_959 => N_959, N_958 => - N_958, N_971 => N_971, N_970 => N_970, N_969 => N_969, - N_968 => N_968, N_967 => N_967, N_966 => N_966, N_965 => - N_965, N_978 => N_978, N_977 => N_977, N_976 => N_976, - N_975 => N_975, N_974 => N_974, N_973 => N_973, N_972 => - N_972, N_950 => N_950, N_949 => N_949, N_948 => N_948, - time_select_0 => \time_select_0\, N_947 => N_947, N_249 - => N_249, Grant => Grant, Ready => Ready, data_send => - \data_send\, OKAY => OKAY, N_200 => N_200, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \count_send_time_RNO_1[6]\ : NOR3B - port map(A => N_1219, B => \count_send_time[5]_net_1\, C - => N_1145, Y => \count_send_time_RNO_1[6]_net_1\); - - \count_send_time_RNO_0[27]\ : OR2A - port map(A => N_1146, B => N_1145, Y => N_1164); - - \count_send_time_RNO_1[19]\ : OR2B - port map(A => \count_send_time[19]_net_1\, B => N_1220, Y - => N_1102); - - \count_send_time_RNIRQ3N1[17]\ : NOR3C - port map(A => N_1061, B => \count_send_time[17]_net_1\, C - => \count_send_time[18]_net_1\, Y => N_1063); - - \count_send_time[14]\ : DFN1 - port map(D => \count_send_time_RNO[14]_net_1\, CLK => - HCLK_c, Q => \count_send_time[14]_net_1\); - - \state[6]\ : DFN1C0 - port map(D => \state_RNO[6]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[6]_net_1\); - - \count_send_time_RNO_2[18]\ : NOR2B - port map(A => \count_send_time[18]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e18_0_a2_0_0); - - \count_send_time[21]\ : DFN1 - port map(D => count_send_time_e21, CLK => HCLK_c, Q => - \count_send_time[21]_net_1\); - - \count_send_time_RNO[14]\ : OA1C - port map(A => N_1059, B => N_1145_0, C => - count_send_time_e14_i_0, Y => - \count_send_time_RNO[14]_net_1\); - - \count_send_time[31]\ : DFN1 - port map(D => count_send_time_e31, CLK => HCLK_c, Q => - \count_send_time[31]_net_1\); - - \update_RNIPECD_0[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un20_time_write\, Y - => \update_and_sel_5[3]\); - - \sel_data_RNIP45D[0]\ : MX2C - port map(A => N_1321, B => N_1283, S => \sel_data[0]_net_1\, - Y => \data_address[14]\); - - \count_send_time_RNI8KVA[2]\ : OR3C - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => - \count_send_time[2]_net_1\, Y => N_1217); - - \count_send_time_RNO[22]\ : OR3C - port map(A => N_1117, B => N_1118, C => N_1119, Y => - count_send_time_e22); - - time_write_RNO : AO1D - port map(A => un1_state_13_0_a4_0_0, B => \state[7]_net_1\, - C => N_1033, Y => un1_state_13); - - \count_send_time[17]\ : DFN1 - port map(D => \count_send_time_RNO[17]_net_1\, CLK => - HCLK_c, Q => \count_send_time[17]_net_1\); - - \state_RNIKSS3_0[2]\ : OAI1 - port map(A => \state[2]_net_1\, B => \state[7]_net_1\, C - => HRESETn_c, Y => N_1220); - - \count_send_time_RNO_0[3]\ : OR3 - port map(A => N_1217, B => \count_send_time[3]_net_1\, C - => N_1145_0, Y => N_1249); - - \all_data_ren.2.data_time_ren_3[2]\ : OR2A - port map(A => \time_ren\, B => \un13_time_write\, Y => - time_ren(2)); - - \all_data_ren.1.data_data_ren_5[1]\ : OR2A - port map(A => \data_ren\, B => \un20_time_write\, Y => - data_ren(1)); - - \count_send_time_RNO_2[8]\ : OR3B - port map(A => N_1223, B => \count_send_time[7]_net_1\, C - => count_send_time_e8_0_a2_1_0, Y => N_1263); - - \count_send_time_RNIN9B7[4]\ : NOR2 - port map(A => \count_send_time[4]_net_1\, B => - \count_send_time[5]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_0[5]\); - - \update_RNIOECD_1[0]\ : OR2A - port map(A => \update[0]_net_1\, B => \un13_time_write\, Y - => \update_and_sel_3[4]\); - - \state_ns_i_a2_0_a3_0[5]\ : NAND2 - port map(A => N_1026, B => \state[4]_net_1\, Y => N_1049); - - \sel_data_0_RNIKH5P[0]\ : MX2C - port map(A => N_1324, B => N_1300, S => - \sel_data_0[0]_net_1\, Y => \data_address[3]\); - - \count_send_time_RNO[7]\ : XA1 - port map(A => N_1230, B => \count_send_time[7]_net_1\, C - => N_1091, Y => \count_send_time_RNO[7]_net_1\); - - \count_send_time_RNO_2[9]\ : OR3 - port map(A => N_1145_0, B => \count_send_time[9]_net_1\, C - => N_1225, Y => N_1268); - - \sel_data_0_RNIKIAC[0]\ : MX2C - port map(A => N_1319, B => N_1281, S => - \sel_data_0[0]_net_1\, Y => \data_address[12]\); - - \count_send_time[25]\ : DFN1 - port map(D => count_send_time_e25, CLK => HCLK_c, Q => - \count_send_time[25]_net_1\); - - \update_RNIPECD[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => un5_time_write, Y => - \update_and_sel_1[7]\); - - \count_send_time[5]\ : DFN1 - port map(D => \count_send_time_RNO[5]_net_1\, CLK => HCLK_c, - Q => \count_send_time[5]_net_1\); - - \update[1]\ : DFN1E0C0 - port map(D => \state[0]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_12, Q => \update[1]_net_1\); - - time_select : DFN1E1C0 - port map(D => time_fifo_ren_1, CLK => HCLK_c, CLR => - HRESETn_c, E => N_816, Q => \time_select\); - - \count_send_time_RNO_0[2]\ : OR2 - port map(A => count_send_time_e2_0_a2_1_0, B => N_1145_0, Y - => N_1244); - - \count_send_time_RNO[27]\ : XA1A - port map(A => N_1164, B => \count_send_time[27]_net_1\, C - => N_1091, Y => \count_send_time_RNO[27]_net_1\); - - \update_RNIOECD_0[0]\ : OR2A - port map(A => \update[0]_net_1\, B => \un20_time_write\, Y - => \update_and_sel_5[2]\); - - \state_RNIHU8A[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => un1_time_send_ok, Y - => N_1033); - - \sel_data_RNIU60E[0]\ : MX2C - port map(A => N_1302, B => N_906, S => \sel_data[0]_net_1\, - Y => \data_address[23]\); - - \count_send_time_RNO_1[10]\ : OR2B - port map(A => \count_send_time[10]_net_1\, B => N_1220, Y - => N_1272); - - \count_send_time_RNO[0]\ : MX2A - port map(A => N_1145, B => N_1220, S => - \count_send_time[0]_net_1\, Y => count_send_time_e0); - - \count_send_time_RNO[10]\ : OR3C - port map(A => N_1270, B => N_1272, C => N_1273, Y => - count_send_time_e10); - - \all_time_write.3.time_already_send[3]\ : DFN1E1C0 - port map(D => un7_time_write, CLK => HCLK_c, CLR => - HRESETn_c, E => un2_status_full_ack, Q => - \time_already_send[3]\); - - \sel_data_0[1]\ : DFN1E1C0 - port map(D => N_1015, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[7]_net_1\, Q => \sel_data_0[1]_net_1\); - - \count_send_time_RNO_4[12]\ : OR2 - port map(A => \count_send_time[12]_net_1\, B => N_1145_0, Y - => count_send_time_e12_0_a2_1_0); - - \count_send_time_RNI4A1J1[16]\ : NOR3C - port map(A => N_1059, B => \count_send_time[15]_net_1\, C - => \count_send_time[16]_net_1\, Y => N_1061); - - \state[4]\ : DFN1C0 - port map(D => \state_RNO_0[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \state[4]_net_1\); - - time_write : DFN1E0C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_13, Q => \time_write\); - - data_send_RNO : NOR3 - port map(A => \state[0]_net_1\, B => \state[1]_net_1\, C - => \state[7]_net_1\, Y => N_812); - - \sel_data_1[1]\ : DFN1E1C0 - port map(D => N_1015, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[7]_net_1\, Q => \sel_data_1[1]_net_1\); - - \sel_data_0_RNIBH4P[0]\ : MX2C - port map(A => N_1280, B => N_1298, S => - \sel_data_0[0]_net_1\, Y => \data_address[1]\); - - \count_send_time[28]\ : DFN1 - port map(D => \count_send_time_RNO[28]_net_1\, CLK => - HCLK_c, Q => \count_send_time[28]_net_1\); - - \update_RNIOECD[0]\ : OR2A - port map(A => \update[0]_net_1\, B => un5_time_write, Y => - \update_and_sel_1[6]\); - - \sel_data_RNIANVD[0]\ : MX2C - port map(A => N_1312, B => N_902, S => \sel_data[0]_net_1\, - Y => \data_address[19]\); - - \count_send_time_RNIGL6A[22]\ : NOR3C - port map(A => \count_send_time[22]_net_1\, B => - \count_send_time[21]_net_1\, C => - count_send_time_e25_0_o3_m6_0_a2_4, Y => - count_send_time_e25_0_o3_m6_0_a2_6); - - \count_send_time[8]\ : DFN1 - port map(D => count_send_time_e8, CLK => HCLK_c, Q => - \count_send_time[8]_net_1\); - - \sel_data_0_RNIO31Q[0]\ : MX2C - port map(A => N_1326, B => N_1288, S => - \sel_data_0[0]_net_1\, Y => \data_address[5]\); - - \count_send_time_RNO[13]\ : OR3C - port map(A => N_1086, B => N_1085, C => N_1087, Y => - count_send_time_e13); - - \state[7]\ : DFN1P0 - port map(D => \state_RNO[7]_net_1\, CLK => HCLK_c, PRE => - HRESETn_c, Q => \state[7]_net_1\); - - \count_send_time_RNIT09T[6]\ : NOR2A - port map(A => N_1223, B => N_1145, Y => N_1230); - - \count_send_time_RNO[3]\ : OR3C - port map(A => N_1249, B => N_1247, C => N_1246, Y => - count_send_time_e3); - - \count_send_time[10]\ : DFN1 - port map(D => count_send_time_e10, CLK => HCLK_c, Q => - \count_send_time[10]_net_1\); - - time_write_RNI6IL9_2 : NOR2A - port map(A => \time_write\, B => un27_time_write, Y => - un29_time_write); - - \count_send_time_RNO_2[30]\ : OR3B - port map(A => N_1146, B => \count_send_time[27]_net_1\, C - => count_send_time_e30_0_a2_2_1, Y => N_1128); - - \state[5]\ : DFN1C0 - port map(D => \state_RNO[5]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[5]_net_1\); - - data_send : DFN1E0C0 - port map(D => \state[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_812, Q => \data_send\); - - \count_send_time_RNI9946[30]\ : OR2A - port map(A => \count_send_time[30]_net_1\, B => N_1075, Y - => N_1161); - - \DMAWriteFSM_p.sel_data_3_i_a4[0]\ : OR2A - port map(A => ready_i_0(2), B => ready_i_0(1), Y => N_1037); - - \sel_data_0_RNIG15P[0]\ : MX2C - port map(A => N_1323, B => N_1299, S => - \sel_data_0[0]_net_1\, Y => \data_address[2]\); - - \update_RNIPECD_2[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => un27_time_write, Y - => \update_and_sel_7[1]\); - - \count_send_time_RNO_1[2]\ : OR2B - port map(A => count_send_time_e2_0_a2_0_0, B => - \state_0[2]_net_1\, Y => N_1242); - - \state_RNIMMJ[4]\ : NOR2 - port map(A => \state[6]_net_1\, B => \state[4]_net_1\, Y - => N_1030); - - GND_i : GND - port map(Y => \GND\); - - time_send_RNO : NOR2 - port map(A => N_1030, B => N_1026, Y => time_send_0_sqmuxa); - - \sel_data_0_RNI0MA8_1[0]\ : OR2A - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => \un13_time_write\); - - \count_send_time_RNO_3[24]\ : NOR2B - port map(A => \count_send_time[24]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e24_0_a2_0_0); - - \count_send_time_RNO_0[25]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[25]_net_1\, C => - count_send_time_e25_0_o3_N_7_i_0, Y => N_1178); - - \count_send_time_RNO_3[12]\ : NOR2B - port map(A => \count_send_time[12]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e12_0_a2_0_0); - - \count_send_time_RNIRPB7[6]\ : NOR2 - port map(A => \count_send_time[6]_net_1\, B => - \count_send_time[7]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_1[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \DMAWriteFSM_p.sel_data_3_i[0]\ : NOR3B - port map(A => N_1037, B => N_1027, C => ready_i_0(0), Y => - N_1016_i_0); - - \state_RNO_0[5]\ : OR2A - port map(A => \state[5]_net_1\, B => un1_time_send_ok, Y - => N_1042); - - \state_RNO_0[4]\ : OR2B - port map(A => \state[5]_net_1\, B => un1_time_send_ok, Y - => N_1044); - - \sel_data_RNITM0E[0]\ : MX2C - port map(A => N_1295, B => N_913, S => \sel_data[0]_net_1\, - Y => \data_address[30]\); - - \count_send_time_RNO_3[31]\ : OR3B - port map(A => N_1146, B => \count_send_time[27]_net_1\, C - => N_1161, Y => N_1162); - - \sel_data_RNII70E[0]\ : MX2C - port map(A => N_1307, B => N_911, S => \sel_data[0]_net_1\, - Y => \data_address[28]\); - - \count_send_time_RNO_1[25]\ : OR2B - port map(A => \count_send_time[25]_net_1\, B => N_1220, Y - => N_1177); - - \count_send_time_RNO_2[25]\ : OR3 - port map(A => N_1145_0, B => \count_send_time[25]_net_1\, C - => count_send_time_e25_0_o3_N_7_i_0, Y => N_1180); - - \count_send_time_RNINO24[24]\ : OR2 - port map(A => \count_send_time[24]_net_1\, B => - \count_send_time[25]_net_1\, Y => state_tr13_0_a2_17_1); - - \DMAWriteFSM_p.sel_data_3_i_o3[0]\ : OR2A - port map(A => ready_i_0(3), B => ready_i_0(1), Y => N_1027); - - \state_RNO_0[7]\ : OR3B - port map(A => \send_16_3_time_1_sqmuxa_i_o3_0\, B => - \state[7]_net_1\, C => N_1027, Y => N_1040); - - \count_send_time[7]\ : DFN1 - port map(D => \count_send_time_RNO[7]_net_1\, CLK => HCLK_c, - Q => \count_send_time[7]_net_1\); - - \count_send_time_RNO[25]\ : OR3C - port map(A => N_1178, B => N_1177, C => N_1180, Y => - count_send_time_e25); - - \count_send_time_RNO_1[9]\ : OR2B - port map(A => \count_send_time[9]_net_1\, B => N_1220, Y - => N_1267); - - \count_send_time_RNIVS36[16]\ : NOR3C - port map(A => \count_send_time[17]_net_1\, B => - \count_send_time[16]_net_1\, C => - \count_send_time[23]_net_1\, Y => - count_send_time_e25_0_o3_m6_0_a2_4); - - \count_send_time_RNO[31]\ : OR3C - port map(A => N_1191, B => N_1193, C => N_1194, Y => - count_send_time_e31); - - \state_ns_i_a2_0_RNO_2[5]\ : NOR2A - port map(A => \state[7]_net_1\, B => - \send_16_3_time[0]_net_1\, Y => - \state_ns_i_a2_0_a3_0[5]_net_1\); - - \count_send_time_RNIM7MP[6]\ : NOR3C - port map(A => N_1219, B => \count_send_time[5]_net_1\, C - => \count_send_time[6]_net_1\, Y => N_1223); - - \state_RNO[1]\ : NOR3C - port map(A => state_tr13_0_a2_14, B => N_1047_25, C => - state_tr13_0_a2_15, Y => \state_ns[6]\); - - \state_RNIKSS3[2]\ : OR3B - port map(A => \state[7]_net_1\, B => HRESETn_c, C => - \state[2]_net_1\, Y => N_1091); - - \count_send_time_RNO_3[22]\ : NOR2B - port map(A => \count_send_time[22]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e22_0_a2_0); - - \count_send_time_RNI6158[16]\ : OR3A - port map(A => \state_ns_i_a2_0_a4_0_19_9_0[5]\, B => - \count_send_time[17]_net_1\, C => - \count_send_time[16]_net_1\, Y => state_tr13_0_a2_9); - - \count_send_time_RNO_0[13]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[13]_net_1\, C => N_1057, Y => N_1086); - - time_write_RNI6IL9 : NOR2A - port map(A => \time_write\, B => un5_time_write, Y => - un7_time_write); - - \sel_data_0[0]\ : DFN1E1C0 - port map(D => N_1016_i_0, CLK => HCLK_c, CLR => HRESETn_c, - E => \state[7]_net_1\, Q => \sel_data_0[0]_net_1\); - - \count_send_time_RNO_0[14]\ : OAI1 - port map(A => \count_send_time_RNO_1[14]_net_1\, B => - \count_send_time[14]_net_1\, C => N_1091, Y => - count_send_time_e14_i_0); - - \sel_data_0_RNIGHOH_0[0]\ : OR2A - port map(A => \time_ren\, B => un5_time_write, Y => - time_ren(3)); - - \count_send_time_RNO[8]\ : OR3C - port map(A => N_1260, B => N_1262, C => N_1263, Y => - count_send_time_e8); - - \count_send_time[26]\ : DFN1 - port map(D => \count_send_time_RNO[26]_net_1\, CLK => - HCLK_c, Q => \count_send_time[26]_net_1\); - - \state_RNIQLS[5]\ : NOR3 - port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C - => \state[0]_net_1\, Y => N_816); - - \state_RNILNKV11[7]\ : AO1C - port map(A => N_1027, B => \send_16_3_time_1_sqmuxa_i_o3_0\, - C => \state[7]_net_1\, Y => N_1014); - - \count_send_time_RNIU2FB[29]\ : NOR3 - port map(A => \count_send_time[29]_net_1\, B => - \count_send_time[28]_net_1\, C => N_1047_5, Y => - state_tr13_0_a2_7); - - VCC_i : VCC - port map(Y => \VCC\); - - \count_send_time_RNI5L58[22]\ : NOR3A - port map(A => state_tr13_0_a2_6, B => - \count_send_time[22]_net_1\, C => - \count_send_time[21]_net_1\, Y => state_tr13_0_a2_10); - - \sel_data[1]\ : DFN1E1C0 - port map(D => N_1015, CLK => HCLK_c, CLR => HRESETn_c, E - => \state[7]_net_1\, Q => \sel_data[1]_net_1\); - - \count_send_time_RNIV9C7[8]\ : OR2 - port map(A => \count_send_time[9]_net_1\, B => - \count_send_time[8]_net_1\, Y => N_1047_5); - - \all_time_write.0.time_already_send[0]\ : DFN1E1C0 - port map(D => un29_time_write, CLK => HCLK_c, CLR => - HRESETn_c, E => un17_status_full_ack, Q => - \time_already_send[0]\); - - \sel_data_0_RNI4K2Q[0]\ : MX2C - port map(A => N_1329, B => N_1291, S => - \sel_data_0[0]_net_1\, Y => \data_address[8]\); - - \count_send_time_RNIKS24[30]\ : NOR2 - port map(A => \count_send_time[23]_net_1\, B => - \count_send_time[30]_net_1\, Y => state_tr13_0_a2_6); - - \count_send_time_RNI29SA1[12]\ : OR3B - port map(A => \count_send_time[11]_net_1\, B => - \count_send_time[12]_net_1\, C => N_1159, Y => N_1057); - - \sel_data_0_RNIIPAU1_0[0]\ : OR2A - port map(A => \data_ren\, B => un5_time_write, Y => - data_ren(3)); - - \count_send_time[29]\ : DFN1 - port map(D => \count_send_time_RNO[29]_net_1\, CLK => - HCLK_c, Q => \count_send_time[29]_net_1\); - - \send_16_3_time[1]\ : DFN1E0C0 - port map(D => \send_16_3_time[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => N_1014, Q => - \send_16_3_time[1]_net_1\); - - \sel_data_RNI670E[0]\ : MX2C - port map(A => N_1304, B => N_908, S => \sel_data[0]_net_1\, - Y => \data_address[25]\); - - \state_RNO[4]\ : AO1B - port map(A => \state[6]_net_1\, B => N_1026, C => N_1044, Y - => \state_RNO_0[4]_net_1\); - - \count_send_time_RNO[19]\ : OR3C - port map(A => N_1103, B => N_1102, C => N_1104, Y => - count_send_time_e19); - - send_16_3_time_1_sqmuxa_i_o3_0 : NOR2 - port map(A => ready_i_0(2), B => ready_i_0(0), Y => - \send_16_3_time_1_sqmuxa_i_o3_0\); - - \all_time_write.3.time_already_send_RNO[3]\ : OR2 - port map(A => status_full_ack(3), B => un7_time_write, Y - => un2_status_full_ack); - - \state_ns_i_a2_0_RNO_3[5]\ : OR3C - port map(A => \state_ns_i_a2_0_a4_0_19_12[5]\, B => - \state_ns_i_a2_0_a4_0_19_11[5]\, C => - \state_ns_i_a2_0_a4_0_19_15[5]\, Y => - \state_ns_i_a2_0_a4_0_19_i[5]\); - - \sel_data_RNIA70E[0]\ : MX2C - port map(A => N_1305, B => N_909, S => \sel_data[0]_net_1\, - Y => \data_address[26]\); - - \count_send_time_RNO_1[30]\ : AOI1B - port map(A => \count_send_time[30]_net_1\, B => N_1220, C - => N_1125, Y => count_send_time_e30_0_0); - - \count_send_time[13]\ : DFN1 - port map(D => count_send_time_e13, CLK => HCLK_c, Q => - \count_send_time[13]_net_1\); - - \count_send_time[12]\ : DFN1 - port map(D => count_send_time_e12, CLK => HCLK_c, Q => - \count_send_time[12]_net_1\); - - \sel_data_0_RNI0MA8_0[0]\ : OR2A - port map(A => \sel_data_0[0]_net_1\, B => - \sel_data[1]_net_1\, Y => \un20_time_write\); - - \DMAWriteFSM_p.sel_data_3_i[1]\ : NOR3 - port map(A => N_1036, B => ready_i_0(0), C => ready_i_0(1), - Y => N_1015); - - \count_send_time_RNO_0[12]\ : AO1C - port map(A => N_1159, B => \count_send_time[11]_net_1\, C - => count_send_time_e12_0_a2_0_0, Y => N_1081); - - \count_send_time_RNO[24]\ : OR3C - port map(A => N_1173, B => N_1172, C => N_1175, Y => - count_send_time_e24); - - \count_send_time_RNO_2[3]\ : OR2B - port map(A => \count_send_time[3]_net_1\, B => N_1220, Y - => N_1246); - - \sel_data_0_RNIGIAC[0]\ : MX2C - port map(A => N_1318, B => N_1294, S => - \sel_data_0[0]_net_1\, Y => \data_address[11]\); - - \count_send_time_RNI23LE[0]\ : NOR3B - port map(A => \count_send_time[1]_net_1\, B => - \state_ns_i_a2_0_a4_0_25_2[5]\, C => - \count_send_time[0]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_4[5]\); - - time_fifo_ren_RNIGRD9 : NOR2A - port map(A => \time_select\, B => \time_fifo_ren\, Y => - \time_ren\); - - \count_send_time_RNO_0[30]\ : AO1B - port map(A => \count_send_time[27]_net_1\, B => N_1146, C - => count_send_time_e30_0_a2_0_0, Y => N_1126); - - \count_send_time_RNO_1[13]\ : OR2B - port map(A => \count_send_time[13]_net_1\, B => N_1220, Y - => N_1085); - - \count_send_time_RNO_2[19]\ : OR3A - port map(A => N_1063, B => N_1145, C => - \count_send_time[19]_net_1\, Y => N_1104); - - \count_send_time_RNO_1[14]\ : NOR3A - port map(A => \count_send_time[13]_net_1\, B => N_1057, C - => N_1145, Y => \count_send_time_RNO_1[14]_net_1\); - - \count_send_time_RNO_0[6]\ : NOR2 - port map(A => \count_send_time[6]_net_1\, B => - \count_send_time_RNO_1[6]_net_1\, Y => N_1253); - - \count_send_time_RNO_0[11]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[11]_net_1\, C => N_1159, Y => N_1167); - - \count_send_time_RNO_4[8]\ : OR2 - port map(A => \count_send_time[8]_net_1\, B => N_1145_0, Y - => count_send_time_e8_0_a2_1_0); - - \all_time_write.2.time_already_send[2]\ : DFN1E1C0 - port map(D => un15_time_write, CLK => HCLK_c, CLR => - HRESETn_c, E => un7_status_full_ack, Q => - \time_already_send[2]\); - - \count_send_time[4]\ : DFN1 - port map(D => \count_send_time_RNO[4]_net_1\, CLK => HCLK_c, - Q => \count_send_time[4]_net_1\); - - \state_RNO[6]\ : OA1C - port map(A => \send_16_3_time_1_sqmuxa_i_o3_0\, B => N_1027, - C => state_tr2_i_0, Y => \state_RNO[6]_net_1\); - - \sel_data_0_RNISJ1Q[0]\ : MX2C - port map(A => N_1327, B => N_1289, S => - \sel_data_0[0]_net_1\, Y => \data_address[6]\); - - \state_RNIU5T[2]\ : OR2A - port map(A => N_1030, B => \state[2]_net_1\, Y => - time_fifo_ren_1); - - \count_send_time[3]\ : DFN1 - port map(D => count_send_time_e3, CLK => HCLK_c, Q => - \count_send_time[3]_net_1\); - - \count_send_time_RNIKK24_0[20]\ : NOR2 - port map(A => \count_send_time[19]_net_1\, B => - \count_send_time[20]_net_1\, Y => state_tr13_0_a2_4); - - \sel_data_0_RNIOIAC[0]\ : MX2C - port map(A => N_1320, B => N_1282, S => - \sel_data_0[0]_net_1\, Y => \data_address[13]\); - - \count_send_time_RNO_0[29]\ : NOR2A - port map(A => \count_send_time[28]_net_1\, B => N_1156, Y - => N_1160); - - \count_send_time_RNO[1]\ : OR3C - port map(A => N_1239, B => N_1237, C => N_1236, Y => - count_send_time_e1); - - \count_send_time_RNO_1[3]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[3]_net_1\, C => N_1217, Y => N_1247); - - \count_send_time_RNIJPA7[2]\ : NOR2A - port map(A => \count_send_time[3]_net_1\, B => - \count_send_time[2]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_2[5]\); - - \count_send_time_RNO_4[20]\ : OR2 - port map(A => \count_send_time[20]_net_1\, B => N_1145_0, Y - => count_send_time_e20_0_a2_1_0); - - \count_send_time_RNO[20]\ : OR3C - port map(A => N_1107, B => N_1108, C => N_1109, Y => - count_send_time_e20); - - \state_RNO[7]\ : AO1C - port map(A => un1_data_send_ok, B => \state[0]_net_1\, C - => N_1040, Y => \state_RNO[7]_net_1\); - - \count_send_time[2]\ : DFN1 - port map(D => count_send_time_e2, CLK => HCLK_c, Q => - \count_send_time[2]_net_1\); - - \sel_data_RNI955D[0]\ : MX2C - port map(A => N_1311, B => N_1287, S => \sel_data[0]_net_1\, - Y => \data_address[18]\); - - \sel_data_0_RNI0MA8_2[0]\ : OR2 - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => un27_time_write); - - \count_send_time_RNIKK24[20]\ : NOR2B - port map(A => \count_send_time[19]_net_1\, B => - \count_send_time[20]_net_1\, Y => - count_send_time_e25_0_o3_m6_0_a2_2); - - \state_RNI7PI3[2]\ : OR2B - port map(A => \state[2]_net_1\, B => HRESETn_c, Y => N_1145); - - \count_send_time_RNO_2[10]\ : OR3A - port map(A => \count_send_time[9]_net_1\, B => N_1225, C - => count_send_time_e10_0_a2_1_0, Y => N_1273); - - \count_send_time_RNO_0[26]\ : OR3A - port map(A => \count_send_time[25]_net_1\, B => - count_send_time_e25_0_o3_N_7_i_0, C => N_1145, Y => - N_1163); - - \count_send_time_RNO[18]\ : AO1C - port map(A => \count_send_time[18]_net_1\, B => N_1137, C - => count_send_time_e18_0_0, Y => count_send_time_e18); - - \state_RNO_0[1]\ : NOR3B - port map(A => \state_0[2]_net_1\, B => state_tr13_0_a2_10, - C => state_tr13_0_a2_9, Y => state_tr13_0_a2_14); - - \state_RNO_2[1]\ : NOR3A - port map(A => state_tr13_0_a2_7, B => state_tr13_0_a2_17_0, - C => state_tr13_0_a2_17_1, Y => state_tr13_0_a2_12); - - \count_send_time_RNI3V2D2[27]\ : OR3B - port map(A => N_1146, B => \count_send_time[27]_net_1\, C - => N_1145, Y => N_1156); - - \sel_data_0_RNI714P[0]\ : MX2C - port map(A => N_1279, B => N_1297, S => - \sel_data_0[0]_net_1\, Y => \data_address[0]\); - - \count_send_time_RNO[6]\ : NOR3A - port map(A => N_1091, B => N_1253, C => N_1230, Y => - \count_send_time_RNO[6]_net_1\); - - time_write_RNI6IL9_1 : NOR2A - port map(A => \time_write\, B => \un20_time_write\, Y => - un22_time_write); - - \gen_select_address.1.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(1) => status_full_err(1), status_full(1) - => status_full(1), sel_data(1) => \sel_data[1]_net_1\, - sel_data_0(1) => \sel_data_0[1]_net_1\, - update_and_sel_5(3) => \update_and_sel_5[3]\, - update_and_sel_5(2) => \update_and_sel_5[2]\, - addr_data_f1(31) => addr_data_f1(31), addr_data_f1(30) - => addr_data_f1(30), addr_data_f1(29) => - addr_data_f1(29), addr_data_f1(28) => addr_data_f1(28), - addr_data_f1(27) => addr_data_f1(27), addr_data_f1(26) - => addr_data_f1(26), addr_data_f1(25) => - addr_data_f1(25), addr_data_f1(24) => addr_data_f1(24), - addr_data_f1(23) => addr_data_f1(23), addr_data_f1(22) - => addr_data_f1(22), addr_data_f1(21) => - addr_data_f1(21), addr_data_f1(20) => addr_data_f1(20), - addr_data_f1(19) => addr_data_f1(19), addr_data_f1(18) - => addr_data_f1(18), addr_data_f1(17) => - addr_data_f1(17), addr_data_f1(16) => addr_data_f1(16), - addr_data_f1(15) => addr_data_f1(15), addr_data_f1(14) - => addr_data_f1(14), addr_data_f1(13) => - addr_data_f1(13), addr_data_f1(12) => addr_data_f1(12), - addr_data_f1(11) => addr_data_f1(11), addr_data_f1(10) - => addr_data_f1(10), addr_data_f1(9) => addr_data_f1(9), - addr_data_f1(8) => addr_data_f1(8), addr_data_f1(7) => - addr_data_f1(7), addr_data_f1(6) => addr_data_f1(6), - addr_data_f1(5) => addr_data_f1(5), addr_data_f1(4) => - addr_data_f1(4), addr_data_f1(3) => addr_data_f1(3), - addr_data_f1(2) => addr_data_f1(2), addr_data_f1(1) => - addr_data_f1(1), addr_data_f1(0) => addr_data_f1(0), - status_full_ack(1) => status_full_ack(1), - addr_data_vector_94 => \addr_data_vector[126]\, - addr_data_vector_91 => \addr_data_vector[123]\, - addr_data_vector_89 => \addr_data_vector[121]\, - addr_data_vector_87 => \addr_data_vector[119]\, - addr_data_vector_86 => \addr_data_vector[118]\, - addr_data_vector_85 => \addr_data_vector[117]\, - addr_data_vector_84 => \addr_data_vector[116]\, - addr_data_vector_83 => \addr_data_vector[115]\, - addr_data_vector_67 => \addr_data_vector[99]\, - addr_data_vector_66 => \addr_data_vector[98]\, - addr_data_vector_65 => \addr_data_vector[97]\, - addr_data_vector_64 => \addr_data_vector[96]\, - addr_data_vector_75 => \addr_data_vector[107]\, - addr_data_vector_73 => \addr_data_vector[105]\, - addr_data_vector_81 => \addr_data_vector[113]\, - addr_data_vector_79 => \addr_data_vector[111]\, - addr_data_vector_77 => \addr_data_vector[109]\, - addr_data_vector_24 => \addr_data_vector[56]\, - addr_data_vector_31 => \addr_data_vector[63]\, - addr_data_vector_16 => \addr_data_vector[48]\, - addr_data_vector_14 => \addr_data_vector[46]\, - addr_data_vector_18 => \addr_data_vector[50]\, - addr_data_vector_26 => \addr_data_vector[58]\, - addr_data_vector_29 => \addr_data_vector[61]\, - addr_data_vector_28 => \addr_data_vector[60]\, - addr_data_vector_5 => \addr_data_vector[37]\, - addr_data_vector_4 => \addr_data_vector[36]\, - addr_data_vector_6 => \addr_data_vector[38]\, - addr_data_vector_12 => \addr_data_vector[44]\, - addr_data_vector_10 => \addr_data_vector[42]\, - addr_data_vector_7 => \addr_data_vector[39]\, - addr_data_vector_8 => \addr_data_vector[40]\, N_913 => - N_913, N_910 => N_910, N_908 => N_908, N_906 => N_906, - N_905 => N_905, N_904 => N_904, N_903 => N_903, N_902 => - N_902, N_1300 => N_1300, N_1299 => N_1299, N_1298 => - N_1298, N_1297 => N_1297, N_1294 => N_1294, N_1292 => - N_1292, N_1286 => N_1286, N_1284 => N_1284, N_1282 => - N_1282, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c); - - \count_send_time[24]\ : DFN1 - port map(D => count_send_time_e24, CLK => HCLK_c, Q => - \count_send_time[24]_net_1\); - - \count_send_time_RNO_1[12]\ : OR2B - port map(A => \count_send_time[12]_net_1\, B => N_1220, Y - => N_1080); - - \update_RNO[0]\ : OA1 - port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C - => un1_time_send_ok, Y => update_0_sqmuxa); - - \count_send_time_RNO_0[20]\ : AO1B - port map(A => \count_send_time[19]_net_1\, B => N_1063, C - => count_send_time_e20_0_a2_0, Y => N_1107); - - \sel_data_0_RNICIAC[0]\ : MX2C - port map(A => N_1317, B => N_1293, S => - \sel_data_0[0]_net_1\, Y => \data_address[10]\); - - \count_send_time_RNI1RIK1[15]\ : NOR3B - port map(A => N_1059, B => \count_send_time[15]_net_1\, C - => N_1145, Y => N_1077); - - \count_send_time_RNO[23]\ : OR3C - port map(A => N_1121, B => N_1122, C => N_1123, Y => - count_send_time_e23); - - \sel_data_RNI155D[0]\ : MX2C - port map(A => N_1309, B => N_1285, S => \sel_data[0]_net_1\, - Y => \data_address[16]\); - - \count_send_time_RNO_1[11]\ : OR2B - port map(A => \count_send_time[11]_net_1\, B => N_1220, Y - => N_1169); - - \count_send_time_RNO[11]\ : OR3C - port map(A => N_1167, B => N_1169, C => N_1170, Y => - count_send_time_e11); - - \count_send_time[27]\ : DFN1 - port map(D => \count_send_time_RNO[27]_net_1\, CLK => - HCLK_c, Q => \count_send_time[27]_net_1\); - - \count_send_time_RNO_1[20]\ : OR2B - port map(A => \count_send_time[20]_net_1\, B => N_1220, Y - => N_1108); - - \count_send_time_RNO_4[2]\ : AOI1B - port map(A => \count_send_time[1]_net_1\, B => - \count_send_time[0]_net_1\, C => - \count_send_time[2]_net_1\, Y => - count_send_time_e2_0_a2_0_0); - - \count_send_time_RNO_2[20]\ : OR3B - port map(A => N_1063, B => \count_send_time[19]_net_1\, C - => count_send_time_e20_0_a2_1_0, Y => N_1109); - - \count_send_time_RNO_0[17]\ : OA1C - port map(A => N_1061, B => N_1145, C => - \count_send_time[17]_net_1\, Y => N_1096); - - time_select_RNII30M1 : OA1C - port map(A => N_200, B => N_249, C => \time_select\, Y => - \data_ren\); - - \sel_data_0_RNIIPAU1[0]\ : OR2A - port map(A => \data_ren\, B => un27_time_write, Y => - data_ren(0)); - - time_write_RNI6IL9_0 : NOR2A - port map(A => \time_write\, B => \un13_time_write\, Y => - un15_time_write); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_2[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - time_fifo_ren : DFN1E0P0 - port map(D => time_fifo_ren_1_i, CLK => HCLK_c, PRE => - HRESETn_c, E => \state[0]_net_1\, Q => \time_fifo_ren\); - - \count_send_time_RNIK6CT[0]\ : NOR3C - port map(A => \state_ns_i_a2_0_a4_0_25_1[5]\, B => - \state_ns_i_a2_0_a4_0_25_0[5]\, C => - \state_ns_i_a2_0_a4_0_25_4[5]\, Y => N_1047_25); - - time_write_RNO_0 : OR2 - port map(A => \state[1]_net_1\, B => \state[3]_net_1\, Y - => un1_state_13_0_a4_0_0); - - \count_send_time_RNO_1[1]\ : OR3B - port map(A => \count_send_time[1]_net_1\, B => - \state[2]_net_1\, C => \count_send_time[0]_net_1\, Y => - N_1237); - - time_select_0 : DFN1E1C0 - port map(D => time_fifo_ren_1, CLK => HCLK_c, CLR => - HRESETn_c, E => N_816, Q => \time_select_0\); - - \sel_data_RNI555D[0]\ : MX2C - port map(A => N_1310, B => N_1286, S => \sel_data[0]_net_1\, - Y => \data_address[17]\); - - \count_send_time_RNIJ9211[7]\ : OR3C - port map(A => N_1223, B => \count_send_time[7]_net_1\, C - => \count_send_time[8]_net_1\, Y => N_1225); - - \count_send_time_RNO_0[18]\ : AOI1B - port map(A => \count_send_time[18]_net_1\, B => N_1220, C - => N_1099, Y => count_send_time_e18_0_0); - - lpp_dma_send_1word_1 : lpp_dma_send_1word - port map(Lock => Lock, Request => Request, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, un1_time_send_ok => - un1_time_send_ok, time_select => \time_select\, Store => - Store, N_1012 => N_1012, Ready => Ready, Fault => Fault, - time_send => \time_send\, Grant => Grant); - - \all_time_write.0.time_already_send_RNO[0]\ : OR2 - port map(A => status_full_ack(0), B => un29_time_write, Y - => un17_status_full_ack); - - \count_send_time_RNIMBLO1[17]\ : NOR3B - port map(A => N_1061, B => \count_send_time[17]_net_1\, C - => N_1145, Y => N_1137); - - \count_send_time_RNO_2[31]\ : OR3 - port map(A => N_1161, B => \count_send_time[31]_net_1\, C - => N_1156, Y => N_1194); - - \count_send_time[11]\ : DFN1 - port map(D => count_send_time_e11, CLK => HCLK_c, Q => - \count_send_time[11]_net_1\); - - \sel_data_RNIQ60E[0]\ : MX2C - port map(A => N_1315, B => N_905, S => \sel_data[0]_net_1\, - Y => \data_address[22]\); - - \count_send_time[1]\ : DFN1 - port map(D => count_send_time_e1, CLK => HCLK_c, Q => - \count_send_time[1]_net_1\); - - \count_send_time[9]\ : DFN1 - port map(D => count_send_time_e9, CLK => HCLK_c, Q => - \count_send_time[9]_net_1\); - - \sel_data_0_RNI042Q[0]\ : MX2C - port map(A => N_1328, B => N_1290, S => - \sel_data_0[0]_net_1\, Y => \data_address[7]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \count_send_time_RNO_1[8]\ : OR2B - port map(A => \count_send_time[8]_net_1\, B => N_1220, Y - => N_1262); - - \sel_data_RNIE70E[0]\ : MX2C - port map(A => N_1306, B => N_910, S => \sel_data[0]_net_1\, - Y => \data_address[27]\); - - \sel_data_RNIM60E[0]\ : MX2C - port map(A => N_1314, B => N_904, S => \sel_data[0]_net_1\, - Y => \data_address[21]\); - - \count_send_time[20]\ : DFN1 - port map(D => count_send_time_e20, CLK => HCLK_c, Q => - \count_send_time[20]_net_1\); - - \state_ns_i_a2_0_RNO_5[5]\ : NOR2B - port map(A => state_tr13_0_a2_7, B => state_tr13_0_a2_8, Y - => \state_ns_i_a2_0_a4_0_19_12[5]\); - - \count_send_time[30]\ : DFN1 - port map(D => count_send_time_e30, CLK => HCLK_c, Q => - \count_send_time[30]_net_1\); - - \count_send_time[15]\ : DFN1 - port map(D => \count_send_time_RNO[15]_net_1\, CLK => - HCLK_c, Q => \count_send_time[15]_net_1\); - - \count_send_time_RNO[16]\ : OA1C - port map(A => N_1061, B => N_1145_0, C => - count_send_time_e16_i_0, Y => - \count_send_time_RNO[16]_net_1\); - - \DMAWriteFSM_p.sel_data_3_i_a4[1]\ : NOR2A - port map(A => ready_i_0(3), B => ready_i_0(2), Y => N_1036); - - \all_time_write.2.time_already_send_RNISCP08[2]\ : MX2 - port map(A => \time_already_send[3]\, B => - \time_already_send[2]\, S => ready_i_0(2), Y => N_1024); - - \state_RNO[5]\ : AO1C - port map(A => N_1026, B => \state[6]_net_1\, C => N_1042, Y - => \state_RNO[5]_net_1\); - - \count_send_time_RNITLAI[4]\ : NOR3B - port map(A => \count_send_time[3]_net_1\, B => - \count_send_time[4]_net_1\, C => N_1217, Y => N_1219); - - \count_send_time_RNI7558[13]\ : NOR3A - port map(A => state_tr13_0_a2_4, B => - \count_send_time[18]_net_1\, C => - \count_send_time[13]_net_1\, Y => state_tr13_0_a2_9_0); - - \count_send_time_RNO_1[18]\ : AO1B - port map(A => \count_send_time[17]_net_1\, B => N_1061, C - => count_send_time_e18_0_a2_0_0, Y => N_1099); - - \count_send_time_RNIHG24[14]\ : NOR2 - port map(A => \count_send_time[14]_net_1\, B => - \count_send_time[15]_net_1\, Y => - \state_ns_i_a2_0_a4_0_19_9_0[5]\); - - \sel_data_RNI1N0E[0]\ : MX2C - port map(A => N_1296, B => N_914, S => \sel_data[0]_net_1\, - Y => \data_address[31]\); - - \count_send_time[18]\ : DFN1 - port map(D => count_send_time_e18, CLK => HCLK_c, Q => - \count_send_time[18]_net_1\); - - \count_send_time_RNO_0[15]\ : OA1C - port map(A => N_1059, B => N_1145, C => - \count_send_time[15]_net_1\, Y => N_1092); - - \count_send_time_RNO[12]\ : OR3C - port map(A => N_1081, B => N_1080, C => N_1082, Y => - count_send_time_e12); - - \state[2]\ : DFN1C0 - port map(D => \state_ns_i_a2_0[5]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \state[2]_net_1\); - - \count_send_time_RNO_5[30]\ : OR3 - port map(A => N_1075, B => \count_send_time[30]_net_1\, C - => N_1145_0, Y => count_send_time_e30_0_a2_2_1); - - \send_16_3_time[0]\ : DFN1E0P0 - port map(D => \send_16_3_time[2]_net_1\, CLK => HCLK_c, PRE - => HRESETn_c, E => N_1014, Q => - \send_16_3_time[0]_net_1\); - - \count_send_time_RNO_3[8]\ : NOR2B - port map(A => \count_send_time[8]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e8_0_a2_0); - - \count_send_time_RNO_0[8]\ : AO1B - port map(A => \count_send_time[7]_net_1\, B => N_1223, C - => count_send_time_e8_0_a2_0, Y => N_1260); - - \count_send_time_RNO[29]\ : XA1 - port map(A => N_1160, B => \count_send_time[29]_net_1\, C - => N_1091, Y => \count_send_time_RNO[29]_net_1\); - - \count_send_time[6]\ : DFN1 - port map(D => \count_send_time_RNO[6]_net_1\, CLK => HCLK_c, - Q => \count_send_time[6]_net_1\); - - \send_16_3_time[2]\ : DFN1E0C0 - port map(D => \send_16_3_time[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => N_1014, Q => - \send_16_3_time[2]_net_1\); - - \state_0[2]\ : DFN1C0 - port map(D => \state_ns_i_a2_0[5]_net_1\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \state_0[2]_net_1\); - - \count_send_time_RNIQ858[31]\ : NOR3A - port map(A => state_tr13_0_a2_2, B => - \count_send_time[10]_net_1\, C => - \count_send_time[31]_net_1\, Y => state_tr13_0_a2_8); - - \count_send_time_RNI089V1[22]\ : OR3B - port map(A => \count_send_time[21]_net_1\, B => - \count_send_time[22]_net_1\, C => N_1066, Y => N_1069); - - \state[1]\ : DFN1C0 - port map(D => \state_ns[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - \count_send_time_RNO_4[10]\ : OR2 - port map(A => \count_send_time[10]_net_1\, B => N_1145_0, Y - => count_send_time_e10_0_a2_1_0); - - \count_send_time_RNIRO24[26]\ : OR2 - port map(A => \count_send_time[26]_net_1\, B => - \count_send_time[27]_net_1\, Y => state_tr13_0_a2_17_0); - - \count_send_time_RNO[17]\ : NOR3A - port map(A => N_1091, B => N_1096, C => N_1137, Y => - \count_send_time_RNO[17]_net_1\); - - time_send_RNO_0 : NOR2 - port map(A => \state[2]_net_1\, B => \state[0]_net_1\, Y - => N_815); - - \all_time_write.1.time_already_send_RNI7H7MG[1]\ : MX2 - port map(A => N_1024, B => \time_already_send[1]\, S => - ready_i_0(1), Y => N_1025); - - \sel_data_RNIT45D[0]\ : MX2C - port map(A => N_1322, B => N_1284, S => \sel_data[0]_net_1\, - Y => \data_address[15]\); - - \count_send_time_RNIEPE72[26]\ : NOR3B - port map(A => \count_send_time[25]_net_1\, B => - \count_send_time[26]_net_1\, C => - count_send_time_e25_0_o3_N_7_i_0, Y => N_1146); - - \state_ns_i_a2_0_RNO_1[5]\ : AOI1B - port map(A => \state_ns_i_a2_0_a4_0_19_i[5]\, B => - \state_0[2]_net_1\, C => N_1050, Y => - \state_ns_i_a2_0_0[5]\); - - \state_RNO_0[6]\ : OR2B - port map(A => \send_16_3_time[0]_net_1\, B => - \state[7]_net_1\, Y => state_tr2_i_0); - - \state_ns_i_a2_0[5]\ : NAND2 - port map(A => N_1049, B => \state_ns_i_a2_0_1[5]\, Y => - \state_ns_i_a2_0[5]_net_1\); - - \count_send_time_RNO_2[2]\ : OR2B - port map(A => \count_send_time[2]_net_1\, B => N_1220, Y - => N_1241); - - \count_send_time_RNO_4[24]\ : OR2 - port map(A => \count_send_time[24]_net_1\, B => N_1145_0, Y - => count_send_time_e24_0_a2_1_0); - - \all_time_write.1.time_already_send_RNO[1]\ : OR2 - port map(A => status_full_ack(1), B => un22_time_write, Y - => un12_status_full_ack); - - \state_RNO[3]\ : AO1A - port map(A => N_1026, B => \state[4]_net_1\, C => N_1033, Y - => \state_RNO_2[3]\); - - \state_RNO[0]\ : AO1 - port map(A => \state[0]_net_1\, B => un1_data_send_ok, C - => \state[1]_net_1\, Y => \state_RNO_1[0]\); - - \state_ns_i_a2_0_RNO[5]\ : AND2 - port map(A => N_1048, B => \state_ns_i_a2_0_0[5]\, Y => - \state_ns_i_a2_0_1[5]\); - - \sel_data_0_RNIKJ0Q[0]\ : MX2C - port map(A => N_1325, B => N_1301, S => - \sel_data_0[0]_net_1\, Y => \data_address[4]\); - - \count_send_time_RNO_2[13]\ : OR3 - port map(A => N_1145, B => \count_send_time[13]_net_1\, C - => N_1057, Y => N_1087); - - \state_RNO_1[1]\ : NOR3C - port map(A => state_tr13_0_a2_9_0, B => state_tr13_0_a2_8, - C => state_tr13_0_a2_12, Y => state_tr13_0_a2_15); - - \state_ns_i_a2_0_RNO_4[5]\ : OR2B - port map(A => \state[3]_net_1\, B => un1_time_send_ok, Y - => N_1050); - - \count_send_time_RNO_0[4]\ : OR3A - port map(A => \count_send_time[3]_net_1\, B => N_1217, C - => N_1145, Y => N_1227); - - \count_send_time_RNIL0C32[15]\ : OR3C - port map(A => N_1059, B => \count_send_time[15]_net_1\, C - => count_send_time_e25_0_o3_m6_0_a2_7, Y => - count_send_time_e25_0_o3_N_7_i_0); - - \sel_data_RNI270E[0]\ : MX2C - port map(A => N_1303, B => N_907, S => \sel_data[0]_net_1\, - Y => \data_address[24]\); - - \count_send_time_RNO_1[31]\ : OR2B - port map(A => \count_send_time[31]_net_1\, B => N_1220, Y - => N_1193); - - time_fifo_ren_RNIGHOH : OR2A - port map(A => \time_ren\, B => \un20_time_write\, Y => - time_ren(1)); - - \count_send_time_RNO_0[5]\ : OR2A - port map(A => N_1219, B => N_1145, Y => N_1228); - - \count_send_time_RNO_3[30]\ : NOR2B - port map(A => \count_send_time[30]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e30_0_a2_0_0); - - \count_send_time_RNO_0[23]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[23]_net_1\, C => N_1069, Y => N_1121); - - \count_send_time_RNO_0[24]\ : AO1C - port map(A => N_1069, B => \count_send_time[23]_net_1\, C - => count_send_time_e24_0_a2_0_0, Y => N_1173); - - time_send : DFN1E1C0 - port map(D => time_send_0_sqmuxa, CLK => HCLK_c, CLR => - HRESETn_c, E => N_815, Q => \time_send\); - - \count_send_time_RNO_0[31]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[31]_net_1\, C => N_1162, Y => N_1191); - - time_select_RNIIPAU1 : OR2A - port map(A => \data_ren\, B => \un13_time_write\, Y => - data_ren(2)); - - \count_send_time_RNO_3[10]\ : NOR2B - port map(A => \count_send_time[10]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e10_0_a2_0); - - \count_send_time_RNO_0[1]\ : OR3A - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => N_1145_0, Y => N_1239); - - \update[0]\ : DFN1E0C0 - port map(D => update_0_sqmuxa, CLK => HCLK_c, CLR => - HRESETn_c, E => un1_state_12, Q => \update[0]_net_1\); - - \count_send_time_RNO_1[23]\ : OR2B - port map(A => \count_send_time[23]_net_1\, B => N_1220, Y - => N_1122); - - \count_send_time_RNO[28]\ : XA1A - port map(A => N_1156, B => \count_send_time[28]_net_1\, C - => N_1091, Y => \count_send_time_RNO[28]_net_1\); - - \count_send_time_RNO_2[23]\ : OR3 - port map(A => N_1145_0, B => \count_send_time[23]_net_1\, C - => N_1069, Y => N_1123); - - \count_send_time_RNO_1[24]\ : OR2B - port map(A => \count_send_time[24]_net_1\, B => N_1220, Y - => N_1172); - - \count_send_time_RNIBG24[12]\ : NOR2 - port map(A => \count_send_time[11]_net_1\, B => - \count_send_time[12]_net_1\, Y => state_tr13_0_a2_2); - - \count_send_time_RNO_2[24]\ : OR3A - port map(A => \count_send_time[23]_net_1\, B => N_1069, C - => count_send_time_e24_0_a2_1_0, Y => N_1175); - - \count_send_time[23]\ : DFN1 - port map(D => count_send_time_e23, CLK => HCLK_c, Q => - \count_send_time[23]_net_1\); - - \count_send_time[22]\ : DFN1 - port map(D => count_send_time_e22, CLK => HCLK_c, Q => - \count_send_time[22]_net_1\); - - \state_ns_i_a2_0_RNO_6[5]\ : NOR3 - port map(A => state_tr13_0_a2_17_0, B => - state_tr13_0_a2_17_1, C => state_tr13_0_a2_9, Y => - \state_ns_i_a2_0_a4_0_19_11[5]\); - - \sel_data_RNII60E[0]\ : MX2C - port map(A => N_1313, B => N_903, S => \sel_data[0]_net_1\, - Y => \data_address[20]\); - - \update_RNIOECD_2[0]\ : OR2A - port map(A => \update[0]_net_1\, B => un27_time_write, Y - => \update_and_sel_7[0]\); - - \count_send_time_RNO_4[22]\ : OR2 - port map(A => \count_send_time[22]_net_1\, B => N_1145_0, Y - => count_send_time_e22_0_a2_1_0); - - \count_send_time[16]\ : DFN1 - port map(D => \count_send_time_RNO[16]_net_1\, CLK => - HCLK_c, Q => \count_send_time[16]_net_1\); - - \count_send_time_RNIHPUE1[14]\ : NOR3B - port map(A => \count_send_time[13]_net_1\, B => - \count_send_time[14]_net_1\, C => N_1057, Y => N_1059); - - \count_send_time_RNO[30]\ : OR3C - port map(A => N_1126, B => count_send_time_e30_0_0, C => - N_1128, Y => count_send_time_e30); - - \count_send_time_RNO[21]\ : OR3C - port map(A => N_1112, B => N_1113, C => N_1114, Y => - count_send_time_e21); - - \sel_data_0_RNIGHOH[0]\ : OR2A - port map(A => \time_ren\, B => un27_time_write, Y => - time_ren(0)); - - \count_send_time_RNO_2[12]\ : OR3A - port map(A => \count_send_time[11]_net_1\, B => N_1159, C - => count_send_time_e12_0_a2_1_0, Y => N_1082); - - \all_time_write.2.time_already_send_RNO[2]\ : OR2 - port map(A => status_full_ack(2), B => un15_time_write, Y - => un7_status_full_ack); - - \all_time_write.1.time_already_send[1]\ : DFN1E1C0 - port map(D => un22_time_write, CLK => HCLK_c, CLR => - HRESETn_c, E => un12_status_full_ack, Q => - \time_already_send[1]\); - - \gen_select_address.3.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(3) => status_full_err(3), status_full(3) - => status_full(3), sel_data(1) => \sel_data[1]_net_1\, - sel_data_0(1) => \sel_data_0[1]_net_1\, - update_and_sel_1(7) => \update_and_sel_1[7]\, - update_and_sel_1(6) => \update_and_sel_1[6]\, - addr_data_f3(31) => addr_data_f3(31), addr_data_f3(30) - => addr_data_f3(30), addr_data_f3(29) => - addr_data_f3(29), addr_data_f3(28) => addr_data_f3(28), - addr_data_f3(27) => addr_data_f3(27), addr_data_f3(26) - => addr_data_f3(26), addr_data_f3(25) => - addr_data_f3(25), addr_data_f3(24) => addr_data_f3(24), - addr_data_f3(23) => addr_data_f3(23), addr_data_f3(22) - => addr_data_f3(22), addr_data_f3(21) => - addr_data_f3(21), addr_data_f3(20) => addr_data_f3(20), - addr_data_f3(19) => addr_data_f3(19), addr_data_f3(18) - => addr_data_f3(18), addr_data_f3(17) => - addr_data_f3(17), addr_data_f3(16) => addr_data_f3(16), - addr_data_f3(15) => addr_data_f3(15), addr_data_f3(14) - => addr_data_f3(14), addr_data_f3(13) => - addr_data_f3(13), addr_data_f3(12) => addr_data_f3(12), - addr_data_f3(11) => addr_data_f3(11), addr_data_f3(10) - => addr_data_f3(10), addr_data_f3(9) => addr_data_f3(9), - addr_data_f3(8) => addr_data_f3(8), addr_data_f3(7) => - addr_data_f3(7), addr_data_f3(6) => addr_data_f3(6), - addr_data_f3(5) => addr_data_f3(5), addr_data_f3(4) => - addr_data_f3(4), addr_data_f3(3) => addr_data_f3(3), - addr_data_f3(2) => addr_data_f3(2), addr_data_f3(1) => - addr_data_f3(1), addr_data_f3(0) => addr_data_f3(0), - status_full_ack(3) => status_full_ack(3), - addr_data_vector_61 => \addr_data_vector[97]\, - addr_data_vector_60 => \addr_data_vector[96]\, - addr_data_vector_27 => \addr_data_vector[63]\, - addr_data_vector_25 => \addr_data_vector[61]\, - addr_data_vector_24 => \addr_data_vector[60]\, - addr_data_vector_22 => \addr_data_vector[58]\, - addr_data_vector_20 => \addr_data_vector[56]\, - addr_data_vector_0 => \addr_data_vector[36]\, - addr_data_vector_6 => \addr_data_vector[42]\, - addr_data_vector_4 => \addr_data_vector[40]\, - addr_data_vector_3 => \addr_data_vector[39]\, - addr_data_vector_2 => \addr_data_vector[38]\, - addr_data_vector_1 => \addr_data_vector[37]\, - addr_data_vector_14 => \addr_data_vector[50]\, - addr_data_vector_12 => \addr_data_vector[48]\, - addr_data_vector_10 => \addr_data_vector[46]\, - addr_data_vector_8 => \addr_data_vector[44]\, - addr_data_vector_63 => \addr_data_vector[99]\, - addr_data_vector_90 => \addr_data_vector[126]\, - addr_data_vector_87 => \addr_data_vector[123]\, - addr_data_vector_85 => \addr_data_vector[121]\, - addr_data_vector_62 => \addr_data_vector[98]\, - addr_data_vector_69 => \addr_data_vector[105]\, - addr_data_vector_73 => \addr_data_vector[109]\, - addr_data_vector_71 => \addr_data_vector[107]\, - addr_data_vector_77 => \addr_data_vector[113]\, - addr_data_vector_79 => \addr_data_vector[115]\, - addr_data_vector_82 => \addr_data_vector[118]\, - addr_data_vector_83 => \addr_data_vector[119]\, - addr_data_vector_75 => \addr_data_vector[111]\, - addr_data_vector_80 => \addr_data_vector[116]\, - addr_data_vector_81 => \addr_data_vector[117]\, N_914 => - N_914, N_912 => N_912, N_911 => N_911, N_909 => N_909, - N_907 => N_907, N_1301 => N_1301, N_1293 => N_1293, - N_1291 => N_1291, N_1290 => N_1290, N_1289 => N_1289, - N_1288 => N_1288, N_1287 => N_1287, N_1285 => N_1285, - N_1283 => N_1283, N_1281 => N_1281, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - \state_ns_i_a2_0_RNO_7[5]\ : NOR3C - port map(A => state_tr13_0_a2_10, B => state_tr13_0_a2_9_0, - C => N_1047_25, Y => \state_ns_i_a2_0_a4_0_19_15[5]\); - - \count_send_time_RNO_2[11]\ : OR3 - port map(A => N_1145_0, B => \count_send_time[11]_net_1\, C - => N_1159, Y => N_1170); - - \count_send_time_RNO[5]\ : XA1A - port map(A => N_1228, B => \count_send_time[5]_net_1\, C - => N_1091, Y => \count_send_time_RNO[5]_net_1\); - - \count_send_time[19]\ : DFN1 - port map(D => count_send_time_e19, CLK => HCLK_c, Q => - \count_send_time[19]_net_1\); - - \count_send_time_RNO_3[20]\ : NOR2B - port map(A => \count_send_time[20]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e20_0_a2_0); - - \sel_data_0_RNICI8P[0]\ : MX2C - port map(A => N_1316, B => N_1292, S => - \sel_data_0[0]_net_1\, Y => \data_address[9]\); - - \count_send_time_RNO_0[22]\ : AO1C - port map(A => N_1066, B => \count_send_time[21]_net_1\, C - => count_send_time_e22_0_a2_0, Y => N_1117); - - \count_send_time_RNO[15]\ : NOR3A - port map(A => N_1091, B => N_1092, C => N_1077, Y => - \count_send_time_RNO[15]_net_1\); - - \count_send_time_RNO_0[21]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[21]_net_1\, C => N_1066, Y => N_1112); - - \count_send_time_RNO_1[22]\ : OR2B - port map(A => \count_send_time[22]_net_1\, B => N_1220, Y - => N_1118); - - \update_RNIPECD_1[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un13_time_write\, Y - => \update_and_sel_3[5]\); - - \count_send_time_RNO_2[22]\ : OR3A - port map(A => \count_send_time[21]_net_1\, B => N_1066, C - => count_send_time_e22_0_a2_1_0, Y => N_1119); - - \state_0_RNIAU89[2]\ : OR2B - port map(A => \state_0[2]_net_1\, B => HRESETn_c, Y => - N_1145_0); - - \state_RNI8UM1[0]\ : AO1B - port map(A => \state[0]_net_1\, B => un1_data_send_ok, C - => N_1030, Y => un1_state_12); - - DMA2AHB_1 : DMA2AHB - port map(hburst_c(2) => hburst_c(2), hburst_c(1) => - hburst_c(1), hburst_c(0) => hburst_c(0), htrans_c(1) => - htrans_c(1), htrans_c(0) => htrans_c(0), un7_dmain(66) - => \un7_dmain[66]\, hsize_c(1) => hsize_c(1), hsize_c(0) - => hsize_c(0), AHB_Master_In_c_5 => AHB_Master_In_c_5, - AHB_Master_In_c_4 => AHB_Master_In_c_4, AHB_Master_In_c_0 - => AHB_Master_In_c_0, AHB_Master_In_c_3 => - AHB_Master_In_c_3, haddr_c(31) => haddr_c(31), - haddr_c(30) => haddr_c(30), haddr_c(29) => haddr_c(29), - haddr_c(28) => haddr_c(28), haddr_c(27) => haddr_c(27), - haddr_c(26) => haddr_c(26), haddr_c(25) => haddr_c(25), - haddr_c(24) => haddr_c(24), haddr_c(23) => haddr_c(23), - haddr_c(22) => haddr_c(22), haddr_c(21) => haddr_c(21), - haddr_c(20) => haddr_c(20), haddr_c(19) => haddr_c(19), - haddr_c(18) => haddr_c(18), haddr_c(17) => haddr_c(17), - haddr_c(16) => haddr_c(16), haddr_c(15) => haddr_c(15), - haddr_c(14) => haddr_c(14), haddr_c(13) => haddr_c(13), - haddr_c(12) => haddr_c(12), haddr_c(11) => haddr_c(11), - haddr_c(10) => haddr_c(10), haddr_c(9) => haddr_c(9), - haddr_c(8) => haddr_c(8), haddr_c(7) => haddr_c(7), - haddr_c(6) => haddr_c(6), haddr_c(5) => haddr_c(5), - haddr_c(4) => haddr_c(4), haddr_c(3) => haddr_c(3), - haddr_c(2) => haddr_c(2), haddr_c(1) => haddr_c(1), - haddr_c(0) => haddr_c(0), hwrite_c => hwrite_c, Ready => - Ready, N_1012 => N_1012, Grant => Grant, - IdlePhase_RNI03G71 => IdlePhase_RNI03G71, OKAY => OKAY, - Fault => Fault, N_1011 => N_1011, N_1013 => N_1013, N_43 - => N_43, time_select_0 => \time_select_0\, N_960 => - N_960, N_959 => N_959, N_958 => N_958, N_957 => N_957, - N_964 => N_964, N_963 => N_963, N_962 => N_962, N_961 => - N_961, N_955 => N_955, N_954 => N_954, N_953 => N_953, - N_952 => N_952, N_951 => N_951, N_950 => N_950, N_949 => - N_949, N_948 => N_948, N_947 => N_947, N_956 => N_956, - N_965 => N_965, N_966 => N_966, N_967 => N_967, N_968 => - N_968, N_969 => N_969, N_970 => N_970, N_971 => N_971, - N_972 => N_972, N_973 => N_973, N_974 => N_974, N_975 => - N_975, N_976 => N_976, N_977 => N_977, HRESETn_c => - HRESETn_c, N_978 => N_978, HCLK_c => HCLK_c); - - \count_send_time_RNO_1[21]\ : OR2B - port map(A => \count_send_time[21]_net_1\, B => N_1220, Y - => N_1113); - - \count_send_time_RNO_0[19]\ : OR3B - port map(A => \state[2]_net_1\, B => - \count_send_time[19]_net_1\, C => N_1063, Y => N_1103); - - \count_send_time_RNIVO24[29]\ : OR2B - port map(A => \count_send_time[29]_net_1\, B => - \count_send_time[28]_net_1\, Y => N_1075); - - \count_send_time_RNO_2[21]\ : OR3 - port map(A => N_1145, B => \count_send_time[21]_net_1\, C - => N_1066, Y => N_1114); - - \count_send_time_RNO[9]\ : OR3C - port map(A => N_1265, B => N_1267, C => N_1268, Y => - count_send_time_e9); - - \state_ns_i_a2_0_RNO_0[5]\ : AO1C - port map(A => N_1027, B => \send_16_3_time_1_sqmuxa_i_o3_0\, - C => \state_ns_i_a2_0_a3_0[5]_net_1\, Y => N_1048); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_arbiter is - - port( wdata : out std_logic_vector(31 downto 0); - data_wen : out std_logic_vector(3 downto 0); - valid_ack : out std_logic_vector(3 downto 0); - time_wen : out std_logic_vector(3 downto 0); - data_f3_out : in std_logic_vector(159 downto 64); - data_f2_out : in std_logic_vector(159 downto 64); - data_f1_out : in std_logic_vector(159 downto 64); - data_f0_out : in std_logic_vector(159 downto 64); - valid_out_i : in std_logic_vector(1 to 1); - ready_i_0 : in std_logic_vector(3 downto 0); - valid_out_3 : in std_logic; - valid_out_2 : in std_logic; - valid_out_0 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_waveform_fifo_arbiter; - -architecture DEF_ARCH of lpp_waveform_fifo_arbiter is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \data_valid_and_ready_3[0]_net_1\, - \data_valid_and_ready_2[0]_net_1\, - \data_valid_and_ready_1[0]_net_1\, - \data_valid_and_ready_0[0]_net_1\, - \data_valid_and_ready_3[2]_net_1\, - \data_valid_and_ready_2[2]_net_1\, - \data_valid_and_ready_1[2]_net_1\, - \data_valid_and_ready_0[2]_net_1\, N_863_2, - \state[4]_net_1\, \data_temp_5_i_a2_0_0[32]_net_1\, - N_1580_0, N_863_1, N_863_0, N_1580_3, - \data_valid_and_ready[1]_net_1\, N_1580_2, N_1580_1, - \state_0[4]\, N_860_i, N_860, \time_wen_3_i[0]\, - \time_wen_3[0]\, N_859_i, N_859, N_857_i, N_857, - state_0_sqmuxa_i_i, state_0_sqmuxa_i, - \data_temp_5_i_0[32]\, N_912_i, N_769, N_864, - \data_temp_5_i_0[33]\, N_770, N_867, - \data_temp_5_i_0[34]\, N_848, N_870, - \data_temp_5_i_0[35]\, N_849, N_873, - \data_temp_5_i_0[36]\, N_850, N_1650, - \data_temp_5_i_0[37]\, N_851, N_1653, - \data_temp_5_i_0[38]\, N_852, N_1656, - \data_temp_5_i_0[39]\, N_853, N_1659, - \data_temp_5_i_0[40]\, N_854, N_1662, - \data_temp_5_i_0[41]\, N_841, N_1665, - \data_temp_5_i_0[42]\, N_842, N_1668, - \data_temp_5_i_0[43]\, N_843, N_897, - \data_temp_5_i_0[92]\, N_794, N_900, - \data_temp_5_i_0[93]\, N_795, N_902, - \data_temp_5_i_0[124]\, N_1681, N_904, - \data_temp_5_i_0[125]\, N_1682, N_906, - \data_temp_5_i_0[91]\, N_793, N_908, - \data_temp_5_i_0[123]\, N_1680, N_910, - \time_wen_3_i_a2_0[3]_net_1\, - \data_valid_and_ready[3]_net_1\, \state_ns_i_i_a2_1[0]\, - \state[2]_net_1\, \state[1]_net_1\, \state[3]_net_1\, - N_239, N_898, N_237, N_1669, N_235, N_1666, N_233, N_1663, - N_231, N_1660, N_229, N_1657, N_227, N_1654, N_225, - N_1651, N_223, N_874, N_221, N_871, N_219, N_868, N_215, - N_865, N_251, N_913, N_249, N_247, N_914, N_245, N_915, - N_243, N_241, N_863, N_861, N_1306, \state[0]_net_1\, - N_917, N_858, \data_temp[64]_net_1\, N_1685, - \data_temp[65]_net_1\, N_1686, \data_temp[66]_net_1\, - N_1687, \data_temp[67]_net_1\, N_1688, - \data_temp[68]_net_1\, N_1689, \data_temp[69]_net_1\, - N_762, \data_temp[70]_net_1\, N_763, - \data_temp[71]_net_1\, N_764, \data_temp[72]_net_1\, - N_765, \data_temp[73]_net_1\, N_766, - \data_temp[74]_net_1\, N_767, \data_temp[75]_net_1\, - N_768, N_1731, N_1718, N_1693, N_1694, N_1730, N_1692, - \data_temp[123]_net_1\, \data_temp[125]_net_1\, - \data_temp[124]_net_1\, N_916, N_1580, N_1675, N_1676, - N_1677, N_1678, N_1679, N_1683, N_1684, N_1690, N_1691, - N_1695, N_1696, N_1697, N_1698, N_1699, N_1700, N_1701, - N_1702, N_1703, N_1704, N_1705, N_1706, N_1707, N_1708, - N_1709, N_1710, N_1711, N_1712, N_1713, N_1714, N_1715, - N_1716, N_1717, N_1719, N_1720, N_1721, N_1722, N_1723, - N_1724, N_1725, N_1726, N_1727, N_1728, N_1729, N_1732, - N_1733, N_1734, N_1735, N_1736, N_1737, N_1738, N_1739, - N_1740, N_729, N_730, N_731, N_732, N_733, N_734, N_735, - N_736, N_737, N_738, N_739, N_740, N_741, N_742, N_743, - N_744, N_745, N_746, N_747, N_748, N_749, N_750, N_751, - N_752, \data_valid_and_ready[2]_net_1\, N_753, N_754, - N_755, N_756, N_757, N_758, N_759, N_760, N_761, N_771, - N_772, N_773, N_774, N_775, N_776, N_777, N_778, N_779, - N_780, N_781, N_782, N_783, N_784, N_785, N_786, N_787, - N_788, N_789, N_790, N_791, N_792, N_796, N_797, N_798, - N_799, N_800, N_801, N_802, N_803, N_804, N_805, N_806, - N_807, N_808, N_809, N_810, N_811, N_812, N_813, N_814, - N_815, N_816, N_817, N_818, N_819, N_820, N_821, N_822, - N_823, N_824, N_825, N_826, N_827, N_828, N_829, N_830, - N_831, N_832, N_833, N_834, N_835, N_836, - \data_valid_and_ready[0]_net_1\, N_837, N_838, N_839, - N_840, N_844, N_845, N_846, N_847, \data_wen_3[0]\, - \time_en_temp[0]_net_1\, \data_wen_3[2]\, - \time_en_temp[2]_net_1\, \data_wen_3[3]\, - \time_en_temp[3]_net_1\, \data_selected[127]\, - \data_selected[159]\, N_696, \data_temp[127]_net_1\, - N_728, \data_temp_5[95]\, \data_temp_5[127]\, - \data_temp_5[14]\, \data_temp[46]_net_1\, - \data_temp_5[13]\, \data_temp[45]_net_1\, - \data_temp_5[12]\, \data_temp[44]_net_1\, - \data_temp_5[11]\, \data_temp[43]_net_1\, - \data_temp_5[10]\, \data_temp[42]_net_1\, - \data_temp_5[9]\, \data_temp[41]_net_1\, \data_temp_5[8]\, - \data_temp[40]_net_1\, \data_temp_5[7]\, - \data_temp[39]_net_1\, \data_temp_5[6]\, - \data_temp[38]_net_1\, \data_temp_5[5]\, - \data_temp[37]_net_1\, \data_temp_5[4]\, - \data_temp[36]_net_1\, \data_temp_5[3]\, - \data_temp[35]_net_1\, \data_temp_5[2]\, - \data_temp[34]_net_1\, \data_temp_5[1]\, - \data_temp[33]_net_1\, \data_temp_5[0]\, - \data_temp[32]_net_1\, \data_5[31]\, - \data_temp[31]_net_1\, \data_5[30]\, - \data_temp[30]_net_1\, \data_5[29]\, - \data_temp[29]_net_1\, \data_5[28]\, - \data_temp[28]_net_1\, \data_5[27]\, - \data_temp[27]_net_1\, \data_5[26]\, - \data_temp[26]_net_1\, \data_5[25]\, - \data_temp[25]_net_1\, \data_5[24]\, - \data_temp[24]_net_1\, \data_5[23]\, - \data_temp[23]_net_1\, \data_5[22]\, - \data_temp[22]_net_1\, \data_5[21]\, - \data_temp[21]_net_1\, \data_5[20]\, - \data_temp[20]_net_1\, \data_5[19]\, - \data_temp[19]_net_1\, \data_5[18]\, - \data_temp[18]_net_1\, \data_5[17]\, - \data_temp[17]_net_1\, \data_5[16]\, - \data_temp[16]_net_1\, \data_5[15]\, - \data_temp[15]_net_1\, \data_5[14]\, - \data_temp[14]_net_1\, \data_5[13]\, - \data_temp[13]_net_1\, \data_5[12]\, - \data_temp[12]_net_1\, \data_5[11]\, - \data_temp[11]_net_1\, \data_5[10]\, - \data_temp[10]_net_1\, \data_5[9]\, \data_temp[9]_net_1\, - \data_5[8]\, \data_temp[8]_net_1\, \data_5[7]\, - \data_temp[7]_net_1\, \data_5[6]\, \data_temp[6]_net_1\, - \data_selected[76]\, \data_selected[77]\, - \data_selected[78]\, \data_selected[79]\, - \data_selected[126]\, \data_selected[158]\, N_645, - \data_temp[76]_net_1\, N_646, \data_temp[77]_net_1\, - N_647, \data_temp[78]_net_1\, N_648, - \data_temp[79]_net_1\, N_695, \data_temp[126]_net_1\, - N_727, \data_temp_5[44]\, \data_temp_5[45]\, - \data_temp_5[46]\, \data_temp_5[47]\, \data_temp_5[94]\, - \data_temp_5[126]\, \data_temp_5[31]\, - \data_temp[63]_net_1\, \data_temp_5[30]\, - \data_temp[62]_net_1\, \data_temp_5[29]\, - \data_temp[61]_net_1\, \data_temp_5[28]\, - \data_temp[60]_net_1\, \data_temp_5[27]\, - \data_temp[59]_net_1\, \data_temp_5[26]\, - \data_temp[58]_net_1\, \data_temp_5[25]\, - \data_temp[57]_net_1\, \data_temp_5[24]\, - \data_temp[56]_net_1\, \data_temp_5[23]\, - \data_temp[55]_net_1\, \data_temp_5[22]\, - \data_temp[54]_net_1\, \data_temp_5[21]\, - \data_temp[53]_net_1\, \data_temp_5[20]\, - \data_temp[52]_net_1\, \data_temp_5[19]\, - \data_temp[51]_net_1\, \data_temp_5[18]\, - \data_temp[50]_net_1\, \data_temp_5[17]\, - \data_temp[49]_net_1\, \data_temp_5[16]\, - \data_temp[48]_net_1\, \data_temp_5[15]\, - \data_temp[47]_net_1\, N_928, N_929, \data_selected[80]\, - \data_selected[81]\, \data_selected[82]\, - \data_selected[83]\, \data_selected[84]\, - \data_selected[85]\, \data_selected[86]\, - \data_selected[87]\, \data_selected[88]\, - \data_selected[89]\, \data_selected[90]\, - \data_selected[91]\, \data_selected[92]\, - \data_selected[93]\, \data_selected[94]\, - \data_selected[95]\, \data_selected[112]\, - \data_selected[144]\, N_649, \data_temp[80]_net_1\, N_650, - \data_temp[81]_net_1\, N_651, \data_temp[82]_net_1\, - N_652, \data_temp[83]_net_1\, N_653, - \data_temp[84]_net_1\, N_654, \data_temp[85]_net_1\, - N_655, \data_temp[86]_net_1\, N_656, - \data_temp[87]_net_1\, N_657, \data_temp[88]_net_1\, - N_658, \data_temp[89]_net_1\, N_659, - \data_temp[90]_net_1\, N_660, \data_temp[91]_net_1\, - N_661, \data_temp[92]_net_1\, N_662, - \data_temp[93]_net_1\, N_663, \data_temp[94]_net_1\, - N_664, \data_temp[95]_net_1\, N_681, - \data_temp[112]_net_1\, N_713, \data_temp_5[48]\, - \data_temp_5[49]\, \data_temp_5[50]\, \data_temp_5[51]\, - \data_temp_5[52]\, \data_temp_5[53]\, \data_temp_5[54]\, - \data_temp_5[55]\, \data_temp_5[56]\, \data_temp_5[57]\, - \data_temp_5[58]\, \data_temp_5[59]\, \data_temp_5[60]\, - \data_temp_5[61]\, \data_temp_5[62]\, \data_temp_5[63]\, - \data_temp_5[80]\, \data_temp_5[112]\, \data_5[5]\, - \data_temp[5]_net_1\, \data_5[4]\, \data_temp[4]_net_1\, - \data_5[3]\, \data_temp[3]_net_1\, \data_5[2]\, - \data_temp[2]_net_1\, \data_5[1]\, \data_temp[1]_net_1\, - \data_5[0]\, \data_temp[0]_net_1\, \data_selected[108]\, - \data_selected[110]\, \data_selected[140]\, - \data_selected[142]\, N_677, \data_temp[108]_net_1\, - N_679, \data_temp[110]_net_1\, N_709, N_711, - \data_temp_5[76]\, \data_temp_5[78]\, \data_temp_5[108]\, - \data_temp_5[110]\, \data_selected[107]\, - \data_selected[111]\, \data_selected[139]\, - \data_selected[143]\, N_676, \data_temp[107]_net_1\, - N_680, \data_temp[111]_net_1\, N_708, N_712, - \data_temp_5[75]\, \data_temp_5[79]\, \data_temp_5[107]\, - \data_temp_5[111]\, \data_selected[106]\, - \data_selected[113]\, \data_selected[138]\, - \data_selected[145]\, N_675, \data_temp[106]_net_1\, - N_682, \data_temp[113]_net_1\, N_707, N_714, - \data_temp_5[74]\, \data_temp_5[81]\, \data_temp_5[106]\, - \data_temp_5[113]\, \data_selected[105]\, - \data_selected[114]\, \data_selected[137]\, - \data_selected[146]\, N_674, \data_temp[105]_net_1\, - N_683, \data_temp[114]_net_1\, N_706, N_715, - \data_temp_5[73]\, \data_temp_5[82]\, \data_temp_5[105]\, - \data_temp_5[114]\, \data_selected[104]\, - \data_selected[115]\, \data_selected[136]\, - \data_selected[147]\, N_673, \data_temp[104]_net_1\, - N_684, \data_temp[115]_net_1\, N_705, N_716, - \data_temp_5[72]\, \data_temp_5[83]\, \data_temp_5[104]\, - \data_temp_5[115]\, \data_selected[103]\, - \data_selected[116]\, \data_selected[135]\, - \data_selected[148]\, N_672, \data_temp[103]_net_1\, - N_685, \data_temp[116]_net_1\, N_704, N_717, - \data_temp_5[71]\, \data_temp_5[84]\, \data_temp_5[103]\, - \data_temp_5[116]\, \data_selected[102]\, - \data_selected[117]\, \data_selected[134]\, - \data_selected[149]\, N_671, \data_temp[102]_net_1\, - N_686, \data_temp[117]_net_1\, N_703, N_718, - \data_temp_5[70]\, \data_temp_5[85]\, \data_temp_5[102]\, - \data_temp_5[117]\, \data_selected[101]\, - \data_selected[118]\, \data_selected[133]\, - \data_selected[150]\, N_670, \data_temp[101]_net_1\, - N_687, \data_temp[118]_net_1\, N_702, N_719, - \data_temp_5[69]\, \data_temp_5[86]\, \data_temp_5[101]\, - \data_temp_5[118]\, \data_selected[100]\, - \data_selected[119]\, \data_selected[132]\, - \data_selected[151]\, N_669, \data_temp[100]_net_1\, - N_688, \data_temp[119]_net_1\, N_701, N_720, - \data_temp_5[68]\, \data_temp_5[87]\, \data_temp_5[100]\, - \data_temp_5[119]\, \data_selected[99]\, - \data_selected[120]\, \data_selected[131]\, - \data_selected[152]\, N_668, \data_temp[99]_net_1\, N_689, - \data_temp[120]_net_1\, N_700, N_721, \data_temp_5[67]\, - \data_temp_5[88]\, \data_temp_5[99]\, \data_temp_5[120]\, - \data_selected[98]\, \data_selected[121]\, - \data_selected[130]\, \data_selected[153]\, N_667, - \data_temp[98]_net_1\, N_690, \data_temp[121]_net_1\, - N_699, N_722, \data_temp_5[66]\, \data_temp_5[89]\, - \data_temp_5[98]\, \data_temp_5[121]\, - \data_selected[97]\, \data_selected[122]\, - \data_selected[129]\, \data_selected[154]\, N_666, - \data_temp[97]_net_1\, N_691, \data_temp[122]_net_1\, - N_698, N_723, \data_temp_5[65]\, \data_temp_5[90]\, - \data_temp_5[97]\, \data_temp_5[122]\, - \data_selected[96]\, \data_selected[109]\, - \data_selected[128]\, \data_selected[141]\, N_665, - \data_temp[96]_net_1\, N_678, \data_temp[109]_net_1\, - N_697, N_710, \data_temp_5[64]\, \data_temp_5[77]\, - \data_temp_5[96]\, \data_temp_5[109]\, \data_wen_3[1]\, - \time_en_temp[1]_net_1\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \data_temp_RNO_2[65]\ : MX2C - port map(A => data_f2_out(97), B => data_f3_out(97), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_734); - - \data_temp[124]\ : DFN1C0 - port map(D => N_245, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[124]_net_1\); - - \data_temp_RNO_4[42]\ : MX2 - port map(A => data_f2_out(74), B => data_f3_out(74), S => - \data_valid_and_ready[2]_net_1\, Y => N_767); - - \data_temp[99]\ : DFN1C0 - port map(D => \data_temp_5[99]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[99]_net_1\); - - \data_temp_RNO_1[76]\ : MX2C - port map(A => N_731, B => N_806, S => N_1580_2, Y => - \data_selected[108]\); - - \data_temp_RNO_0[42]\ : AO1D - port map(A => N_912_i, B => N_842, C => N_1668, Y => - \data_temp_5_i_0[42]\); - - \data[3]\ : DFN1C0 - port map(D => \data_5[3]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(3)); - - \data_temp_RNO_2[32]\ : MX2 - port map(A => data_f0_out(64), B => data_f1_out(64), S => - \data_valid_and_ready_0[0]_net_1\, Y => N_769); - - \data_temp_RNO_2[64]\ : MX2C - port map(A => data_f2_out(96), B => data_f3_out(96), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_747); - - \time_en_temp[1]\ : DFN1E0C0 - port map(D => N_917, CLK => HCLK_c, CLR => HRESETn_c, E => - state_0_sqmuxa_i, Q => \time_en_temp[1]_net_1\); - - \data_temp[127]\ : DFN1C0 - port map(D => \data_temp_5[127]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[127]_net_1\); - - \time_wen_RNO[1]\ : INV - port map(A => N_857, Y => N_857_i); - - \data_RNO[13]\ : NOR2A - port map(A => \data_temp[13]_net_1\, B => \state[4]_net_1\, - Y => \data_5[13]\); - - \state_RNIQTIC[2]\ : NOR2 - port map(A => \state[4]_net_1\, B => \state[2]_net_1\, Y - => N_928); - - \data_temp_RNO_1[86]\ : MX2C - port map(A => N_1725, B => N_802, S => N_1580_3, Y => - \data_selected[118]\); - - \data_temp_RNO_1[73]\ : MX2C - port map(A => N_1740, B => N_817, S => N_1580_2, Y => - \data_selected[105]\); - - \data_temp_RNO_0[103]\ : MX2C - port map(A => \data_temp[103]_net_1\, B => - \data_selected[135]\, S => \state[4]_net_1\, Y => N_704); - - \data_temp_RNO_1[101]\ : MX2C - port map(A => N_1712, B => N_789, S => N_1580_3, Y => - \data_selected[133]\); - - \data_temp_RNO_2[124]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1693, - Y => N_904); - - \data_temp_RNO_1[96]\ : MX2C - port map(A => N_1721, B => N_798, S => N_1580, Y => - \data_selected[128]\); - - \data_temp_RNO_1[83]\ : MX2C - port map(A => N_1736, B => N_799, S => N_1580_3, Y => - \data_selected[115]\); - - \data_temp[26]\ : DFN1C0 - port map(D => \data_temp_5[26]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[26]_net_1\); - - \data_RNO[17]\ : NOR2A - port map(A => \data_temp[17]_net_1\, B => \state[4]_net_1\, - Y => \data_5[17]\); - - \data_valid_ack[3]\ : DFN1E0C0 - port map(D => N_860_i, CLK => HCLK_c, CLR => HRESETn_c, E - => N_929, Q => valid_ack(3)); - - \data_temp_RNO_1[39]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_764, - Y => N_1660); - - \data_temp_RNO_1[93]\ : MX2 - port map(A => data_f0_out(125), B => data_f1_out(125), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_795); - - \data_temp[13]\ : DFN1C0 - port map(D => \data_temp_5[13]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[13]_net_1\); - - \data_temp[56]\ : DFN1C0 - port map(D => \data_temp_5[56]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[56]_net_1\); - - \data_temp_RNO_2[127]\ : MX2C - port map(A => data_f2_out(159), B => data_f3_out(159), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1696); - - \data_temp[125]\ : DFN1C0 - port map(D => N_247, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[125]_net_1\); - - \data_temp_RNO[65]\ : NOR2A - port map(A => N_863, B => N_666, Y => \data_temp_5[65]\); - - \data_temp_RNO[98]\ : NOR2A - port map(A => N_863, B => N_699, Y => \data_temp_5[98]\); - - \data_RNO[5]\ : NOR2A - port map(A => \data_temp[5]_net_1\, B => \state[4]_net_1\, - Y => \data_5[5]\); - - \data_temp_RNO_2[119]\ : MX2C - port map(A => data_f2_out(151), B => data_f3_out(151), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1702); - - \data_wen[3]\ : DFN1E0P0 - port map(D => \data_wen_3[3]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => data_wen(3)); - - \data_temp[70]\ : DFN1C0 - port map(D => \data_temp_5[70]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[70]_net_1\); - - \data_temp_RNO[39]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[39]\, C => - N_1660, Y => N_231); - - \data_temp_RNO[77]\ : NOR2A - port map(A => N_863, B => N_678, Y => \data_temp_5[77]\); - - \data[13]\ : DFN1C0 - port map(D => \data_5[13]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(13)); - - \data_temp_RNO_2[57]\ : MX2C - port map(A => data_f2_out(89), B => data_f3_out(89), S => - \data_valid_and_ready[2]_net_1\, Y => N_754); - - \data_temp[64]\ : DFN1C0 - port map(D => \data_temp_5[64]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[64]_net_1\); - - \data_temp_RNO[93]\ : NOR3B - port map(A => N_863_0, B => N_914, C => - \data_temp_5_i_0[93]\, Y => N_243); - - \state_RNO_0[4]\ : OR3 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, C - => \state[3]_net_1\, Y => \state_ns_i_i_a2_1[0]\); - - \data_temp_RNO_1[50]\ : MX2C - port map(A => N_761, B => N_836, S => N_1580_1, Y => - \data_selected[82]\); - - \data_temp[6]\ : DFN1C0 - port map(D => \data_temp_5[6]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[6]_net_1\); - - \data[31]\ : DFN1C0 - port map(D => \data_5[31]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(31)); - - \data_temp[112]\ : DFN1C0 - port map(D => \data_temp_5[112]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[112]_net_1\); - - \data_temp_RNO[112]\ : NOR2A - port map(A => N_863_1, B => N_713, Y => \data_temp_5[112]\); - - \data_temp[100]\ : DFN1C0 - port map(D => \data_temp_5[100]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[100]_net_1\); - - \data_temp_RNO_2[70]\ : MX2C - port map(A => data_f2_out(102), B => data_f3_out(102), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_739); - - \data_temp_RNO_3[56]\ : MX2C - port map(A => data_f0_out(88), B => data_f1_out(88), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_828); - - \data_temp_RNO_0[37]\ : AO1D - port map(A => N_912_i, B => N_851, C => N_1653, Y => - \data_temp_5_i_0[37]\); - - \data_temp_RNO[36]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[36]\, C => - N_1651, Y => N_225); - - \data_temp_RNO_0[59]\ : MX2C - port map(A => \data_temp[91]_net_1\, B => - \data_selected[91]\, S => \state[4]_net_1\, Y => N_660); - - \data_temp_RNO_0[51]\ : MX2C - port map(A => \data_temp[83]_net_1\, B => - \data_selected[83]\, S => \state[4]_net_1\, Y => N_652); - - \data_temp_RNO_3[66]\ : MX2C - port map(A => data_f0_out(98), B => data_f1_out(98), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_824); - - \data_temp_RNO_3[86]\ : MX2C - port map(A => data_f0_out(118), B => data_f1_out(118), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_802); - - \data_temp_RNO_3[49]\ : MX2C - port map(A => data_f0_out(81), B => data_f1_out(81), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_835); - - \data_temp_RNO_3[41]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[73]_net_1\, - Y => N_1665); - - \data_temp_RNO_2[40]\ : MX2 - port map(A => data_f0_out(72), B => data_f1_out(72), S => - \data_valid_and_ready[0]_net_1\, Y => N_854); - - \data_temp_RNO_0[116]\ : MX2C - port map(A => \data_temp[116]_net_1\, B => - \data_selected[148]\, S => \state[4]_net_1\, Y => N_717); - - \data_temp_RNO_1[35]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1688, - Y => N_874); - - \data_temp_RNO_3[53]\ : MX2C - port map(A => data_f0_out(85), B => data_f1_out(85), S => - \data_valid_and_ready[0]_net_1\, Y => N_839); - - \data_temp_RNO[49]\ : NOR2A - port map(A => N_863_1, B => N_650, Y => \data_temp_5[49]\); - - \data_temp_RNO_3[63]\ : MX2C - port map(A => data_f0_out(95), B => data_f1_out(95), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_821); - - \data_temp_RNO_3[83]\ : MX2C - port map(A => data_f0_out(115), B => data_f1_out(115), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_799); - - \data_temp_RNO_2[120]\ : MX2C - port map(A => data_f2_out(152), B => data_f3_out(152), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1703); - - \data_temp_RNO_1[52]\ : MX2C - port map(A => N_749, B => N_838, S => N_1580_1, Y => - \data_selected[84]\); - - \data_temp_RNO_1[34]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1687, - Y => N_871); - - \state[2]\ : DFN1C0 - port map(D => \state[3]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[2]_net_1\); - - \data_temp[36]\ : DFN1C0 - port map(D => N_225, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[36]_net_1\); - - un5_data_selected_i_i_a2 : OR2B - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_917); - - \data_wen_RNO[0]\ : OR2 - port map(A => \time_en_temp[0]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[0]\); - - \data_temp_RNO_2[72]\ : MX2C - port map(A => data_f2_out(104), B => data_f3_out(104), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1739); - - \data_temp_RNO_1[110]\ : MX2C - port map(A => N_1707, B => N_784, S => N_1580_2, Y => - \data_selected[142]\); - - \data_temp[82]\ : DFN1C0 - port map(D => \data_temp_5[82]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[82]_net_1\); - - \data_temp_RNO[46]\ : NOR2A - port map(A => N_863_0, B => N_647, Y => \data_temp_5[46]\); - - \data_temp[0]\ : DFN1C0 - port map(D => \data_temp_5[0]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[0]_net_1\); - - data_selected_sn_m2_0_o2_2 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_2); - - \data_temp_RNO_2[42]\ : MX2 - port map(A => data_f0_out(74), B => data_f1_out(74), S => - \data_valid_and_ready[0]_net_1\, Y => N_842); - - \data_temp_RNO_1[49]\ : MX2C - port map(A => N_760, B => N_835, S => N_1580_1, Y => - \data_selected[81]\); - - \data_temp_RNO_1[41]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_766, - Y => N_1666); - - \data_RNO[2]\ : NOR2A - port map(A => \data_temp[2]_net_1\, B => \state[4]_net_1\, - Y => \data_5[2]\); - - \data_temp_RNO_2[86]\ : MX2C - port map(A => data_f2_out(118), B => data_f3_out(118), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1725); - - \data_temp[10]\ : DFN1C0 - port map(D => \data_temp_5[10]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[10]_net_1\); - - \data_temp[111]\ : DFN1C0 - port map(D => \data_temp_5[111]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[111]_net_1\); - - \data_temp_RNO_3[36]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[68]_net_1\, - Y => N_1650); - - \data_temp_RNO_0[55]\ : MX2C - port map(A => \data_temp[87]_net_1\, B => - \data_selected[87]\, S => \state[4]_net_1\, Y => N_656); - - \time_wen[1]\ : DFN1E0P0 - port map(D => N_857_i, CLK => HCLK_c, PRE => HRESETn_c, E - => N_928, Q => time_wen(1)); - - \data_temp_RNO_1[127]\ : MX2C - port map(A => N_1696, B => N_1684, S => N_1580_1, Y => - \data_selected[159]\); - - \data_temp_RNO[10]\ : NOR2A - port map(A => \data_temp[42]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[10]\); - - \data_temp_RNO_3[45]\ : MX2C - port map(A => data_f0_out(77), B => data_f1_out(77), S => - \data_valid_and_ready[0]_net_1\, Y => N_845); - - \data_temp_RNO_3[108]\ : MX2C - port map(A => data_f0_out(140), B => data_f1_out(140), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_782); - - \data_temp[24]\ : DFN1C0 - port map(D => \data_temp_5[24]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[24]_net_1\); - - \data_temp_RNO_0[115]\ : MX2C - port map(A => \data_temp[115]_net_1\, B => - \data_selected[147]\, S => \state[4]_net_1\, Y => N_716); - - \data_temp_RNO_2[83]\ : MX2C - port map(A => data_f2_out(115), B => data_f3_out(115), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1736); - - \data_temp_RNO_0[54]\ : MX2C - port map(A => \data_temp[86]_net_1\, B => - \data_selected[86]\, S => \state[4]_net_1\, Y => N_655); - - \data_temp_RNO[4]\ : NOR2A - port map(A => \data_temp[36]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[4]\); - - \data_temp[119]\ : DFN1C0 - port map(D => \data_temp_5[119]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[119]_net_1\); - - \data_temp_RNO_3[33]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[65]_net_1\, - Y => N_867); - - \data_temp_RNO_2[66]\ : MX2C - port map(A => data_f2_out(98), B => data_f3_out(98), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_735); - - \data_temp[54]\ : DFN1C0 - port map(D => \data_temp_5[54]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[54]_net_1\); - - \data_temp_RNO_3[44]\ : MX2C - port map(A => data_f0_out(76), B => data_f1_out(76), S => - \data_valid_and_ready[0]_net_1\, Y => N_844); - - \data_temp_RNO[75]\ : NOR2A - port map(A => N_863_2, B => N_676, Y => \data_temp_5[75]\); - - \data_temp[81]\ : DFN1C0 - port map(D => \data_temp_5[81]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[81]_net_1\); - - \data_RNO[11]\ : NOR2A - port map(A => \data_temp[11]_net_1\, B => \state[4]_net_1\, - Y => \data_5[11]\); - - \data_temp_RNO_3[99]\ : MX2C - port map(A => data_f0_out(131), B => data_f1_out(131), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_787); - - \data_temp_RNO_3[91]\ : MX2 - port map(A => data_f2_out(123), B => data_f3_out(123), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1730); - - \data_temp_RNO[37]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[37]\, C => - N_1654, Y => N_227); - - \data_temp_RNO_2[63]\ : MX2C - port map(A => data_f2_out(95), B => data_f3_out(95), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_746); - - \data_RNO[12]\ : NOR2A - port map(A => \data_temp[12]_net_1\, B => \state[4]_net_1\, - Y => \data_5[12]\); - - \data_valid_ack_RNO[0]\ : INV - port map(A => \time_wen_3[0]\, Y => \time_wen_3_i[0]\); - - \data_temp_RNO_3[127]\ : MX2C - port map(A => data_f0_out(159), B => data_f1_out(159), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1684); - - \data_temp_RNO[2]\ : NOR2A - port map(A => \data_temp[34]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[2]\); - - \data_temp_RNO_1[68]\ : MX2C - port map(A => N_737, B => N_826, S => N_1580_3, Y => - \data_selected[100]\); - - \data_temp_RNO_0[120]\ : MX2C - port map(A => \data_temp[120]_net_1\, B => - \data_selected[152]\, S => \state[4]_net_1\, Y => N_721); - - \data_temp_RNO_1[45]\ : MX2C - port map(A => N_756, B => N_845, S => N_1580_1, Y => - \data_selected[77]\); - - \data_temp_RNO_0[98]\ : MX2C - port map(A => \data_temp[98]_net_1\, B => - \data_selected[130]\, S => \state[4]_net_1\, Y => N_699); - - \data_temp_RNO[91]\ : NOR3B - port map(A => N_863_0, B => N_913, C => - \data_temp_5_i_0[91]\, Y => N_249); - - \data_temp_RNO[115]\ : NOR2A - port map(A => N_863_2, B => N_716, Y => \data_temp_5[115]\); - - \data_temp[76]\ : DFN1C0 - port map(D => \data_temp_5[76]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[76]_net_1\); - - \data_temp_RNO_1[44]\ : MX2C - port map(A => N_755, B => N_844, S => N_1580_1, Y => - \data_selected[76]\); - - \data_RNO[28]\ : NOR2A - port map(A => \data_temp[28]_net_1\, B => \state[4]_net_1\, - Y => \data_5[28]\); - - \data_temp_RNO[68]\ : NOR2A - port map(A => N_863, B => N_669, Y => \data_temp_5[68]\); - - \data_temp_RNO_0[117]\ : MX2C - port map(A => \data_temp[117]_net_1\, B => - \data_selected[149]\, S => \state[4]_net_1\, Y => N_718); - - \data_temp_RNO[92]\ : NOR3B - port map(A => N_863_0, B => N_915, C => - \data_temp_5_i_0[92]\, Y => N_241); - - \time_en_temp_RNO[2]\ : OR2 - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - N_1580_0, Y => N_858); - - \data_temp_RNO_3[122]\ : MX2C - port map(A => data_f0_out(154), B => data_f1_out(154), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1679); - - \data_temp_RNO_2[50]\ : MX2C - port map(A => data_f2_out(82), B => data_f3_out(82), S => - \data_valid_and_ready[2]_net_1\, Y => N_761); - - \data_temp[88]\ : DFN1C0 - port map(D => \data_temp_5[88]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[88]_net_1\); - - \data[28]\ : DFN1C0 - port map(D => \data_5[28]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(28)); - - \data_temp_RNO[20]\ : NOR2A - port map(A => \data_temp[52]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[20]\); - - \data_temp_RNO[63]\ : NOR2A - port map(A => N_863_1, B => N_664, Y => \data_temp_5[63]\); - - \data_temp_RNO[47]\ : NOR2A - port map(A => N_863_0, B => N_648, Y => \data_temp_5[47]\); - - \data_temp_RNO[117]\ : NOR2A - port map(A => N_863_2, B => N_718, Y => \data_temp_5[117]\); - - \data_wen_RNO[1]\ : OR2 - port map(A => \time_en_temp[1]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[1]\); - - \data_temp[93]\ : DFN1C0 - port map(D => N_243, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[93]_net_1\); - - \data_temp[49]\ : DFN1C0 - port map(D => \data_temp_5[49]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[49]_net_1\); - - \data_temp_RNO_3[95]\ : MX2C - port map(A => data_f0_out(127), B => data_f1_out(127), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_797); - - \data_temp_RNO_2[109]\ : MX2C - port map(A => data_f2_out(141), B => data_f3_out(141), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1706); - - \data[5]\ : DFN1C0 - port map(D => \data_5[5]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(5)); - - \data_temp_RNO_4[41]\ : MX2 - port map(A => data_f2_out(73), B => data_f3_out(73), S => - \data_valid_and_ready[2]_net_1\, Y => N_766); - - \data_temp[34]\ : DFN1C0 - port map(D => N_221, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[34]_net_1\); - - \data[16]\ : DFN1C0 - port map(D => \data_5[16]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(16)); - - \data_temp_RNO_3[78]\ : MX2C - port map(A => data_f0_out(110), B => data_f1_out(110), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_808); - - \data_temp_RNO_0[49]\ : MX2C - port map(A => \data_temp[81]_net_1\, B => - \data_selected[81]\, S => \state[4]_net_1\, Y => N_650); - - \data_temp_RNO_0[41]\ : AO1D - port map(A => N_912_i, B => N_841, C => N_1665, Y => - \data_temp_5_i_0[41]\); - - \data_temp[62]\ : DFN1C0 - port map(D => \data_temp_5[62]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[62]_net_1\); - - \data_temp_RNO[94]\ : NOR2A - port map(A => N_863_1, B => N_695, Y => \data_temp_5[94]\); - - \data[7]\ : DFN1C0 - port map(D => \data_5[7]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(7)); - - \data_temp_RNO_3[114]\ : MX2C - port map(A => data_f0_out(146), B => data_f1_out(146), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_774); - - \data_temp_RNO_2[39]\ : MX2 - port map(A => data_f0_out(71), B => data_f1_out(71), S => - \data_valid_and_ready[0]_net_1\, Y => N_853); - - \data_temp_RNO[122]\ : NOR2A - port map(A => N_863, B => N_723, Y => \data_temp_5[122]\); - - \data_RNO[31]\ : NOR2A - port map(A => \data_temp[31]_net_1\, B => \state[4]_net_1\, - Y => \data_5[31]\); - - \data_temp_RNO_3[94]\ : MX2C - port map(A => data_f0_out(126), B => data_f1_out(126), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_796); - - \data_temp[87]\ : DFN1C0 - port map(D => \data_temp_5[87]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[87]_net_1\); - - \data_temp_RNO_3[126]\ : MX2C - port map(A => data_f0_out(158), B => data_f1_out(158), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1683); - - \data_temp_RNO_0[78]\ : MX2C - port map(A => \data_temp[110]_net_1\, B => - \data_selected[110]\, S => \state[4]_net_1\, Y => N_679); - - \data_temp_RNO_2[52]\ : MX2C - port map(A => data_f2_out(84), B => data_f3_out(84), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_749); - - \data_temp[108]\ : DFN1C0 - port map(D => \data_temp_5[108]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[108]_net_1\); - - \data_temp_RNO_1[112]\ : MX2C - port map(A => N_1709, B => N_772, S => N_1580_2, Y => - \data_selected[144]\); - - \data_temp_RNO_0[106]\ : MX2C - port map(A => \data_temp[106]_net_1\, B => - \data_selected[138]\, S => \state[4]_net_1\, Y => N_707); - - \data_temp_RNO[59]\ : NOR2A - port map(A => N_863_1, B => N_660, Y => \data_temp_5[59]\); - - \data_temp_RNO_0[32]\ : AO1D - port map(A => N_912_i, B => N_769, C => N_864, Y => - \data_temp_5_i_0[32]\); - - \data_temp[61]\ : DFN1C0 - port map(D => \data_temp_5[61]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[61]_net_1\); - - \data_temp_RNO_4[38]\ : MX2 - port map(A => data_f2_out(70), B => data_f3_out(70), S => - \data_valid_and_ready[2]_net_1\, Y => N_763); - - \data_temp[16]\ : DFN1C0 - port map(D => \data_temp_5[16]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[16]_net_1\); - - \data[21]\ : DFN1C0 - port map(D => \data_5[21]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(21)); - - \data_temp_RNO_1[36]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1689, - Y => N_1651); - - \data_temp_RNO[89]\ : NOR2A - port map(A => N_863, B => N_690, Y => \data_temp_5[89]\); - - \data_temp_RNO[35]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[35]\, C => - N_874, Y => N_223); - - \data_temp_RNO[102]\ : NOR2A - port map(A => N_863_2, B => N_703, Y => \data_temp_5[102]\); - - \data_temp_RNO_1[123]\ : MX2 - port map(A => data_f0_out(155), B => data_f1_out(155), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1680); - - \data_temp_RNO_3[110]\ : MX2C - port map(A => data_f0_out(142), B => data_f1_out(142), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_784); - - \data_temp_RNO_2[122]\ : MX2C - port map(A => data_f2_out(154), B => data_f3_out(154), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1691); - - \data_temp_RNO_0[45]\ : MX2C - port map(A => \data_temp[77]_net_1\, B => - \data_selected[77]\, S => \state[4]_net_1\, Y => N_646); - - \data_temp_RNO_2[125]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1694, - Y => N_906); - - \data[0]\ : DFN1C0 - port map(D => \data_5[0]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(0)); - - \data_temp_RNO[56]\ : NOR2A - port map(A => N_863_1, B => N_657, Y => \data_temp_5[56]\); - - \data_temp_RNO_2[35]\ : MX2 - port map(A => data_f0_out(67), B => data_f1_out(67), S => - \data_valid_and_ready[0]_net_1\, Y => N_849); - - \data_valid_ack[0]\ : DFN1E0C0 - port map(D => \time_wen_3_i[0]\, CLK => HCLK_c, CLR => - HRESETn_c, E => N_929, Q => valid_ack(0)); - - \data_temp_RNO_1[33]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1686, - Y => N_868); - - \data_temp_RNO[86]\ : NOR2A - port map(A => N_863, B => N_687, Y => \data_temp_5[86]\); - - \data_temp_RNO_1[119]\ : MX2C - port map(A => N_1702, B => N_1676, S => N_1580, Y => - \data_selected[151]\); - - \data_temp_RNO_1[100]\ : MX2C - port map(A => N_1711, B => N_788, S => N_1580, Y => - \data_selected[132]\); - - \data_temp_RNO_1[118]\ : MX2C - port map(A => N_1701, B => N_1675, S => N_1580_3, Y => - \data_selected[150]\); - - GND_i : GND - port map(Y => \GND\); - - \data_temp_RNO_0[44]\ : MX2C - port map(A => \data_temp[76]_net_1\, B => - \data_selected[76]\, S => \state[4]_net_1\, Y => N_645); - - \data_temp_RNO_2[34]\ : MX2 - port map(A => data_f0_out(66), B => data_f1_out(66), S => - \data_valid_and_ready[0]_net_1\, Y => N_848); - - \data_RNO[16]\ : NOR2A - port map(A => \data_temp[16]_net_1\, B => \state[4]_net_1\, - Y => \data_5[16]\); - - \data_temp[74]\ : DFN1C0 - port map(D => \data_temp_5[74]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[74]_net_1\); - - \data_temp[90]\ : DFN1C0 - port map(D => \data_temp_5[90]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[90]_net_1\); - - \data_temp[22]\ : DFN1C0 - port map(D => \data_temp_5[22]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[22]_net_1\); - - \time_wen_3_i_a2_0[3]\ : NOR2B - port map(A => \data_valid_and_ready[3]_net_1\, B => - \data_valid_and_ready_0[2]_net_1\, Y => - \time_wen_3_i_a2_0[3]_net_1\); - - \state_RNIUI96[4]\ : CLKINT - port map(A => \state_0[4]\, Y => \state[4]_net_1\); - - \data_temp_RNO_0[56]\ : MX2C - port map(A => \data_temp[88]_net_1\, B => - \data_selected[88]\, S => \state[4]_net_1\, Y => N_657); - - \data_temp_RNO_0[88]\ : MX2C - port map(A => \data_temp[120]_net_1\, B => - \data_selected[120]\, S => \state[4]_net_1\, Y => N_689); - - \data_temp_RNO[78]\ : NOR2A - port map(A => N_863_1, B => N_679, Y => \data_temp_5[78]\); - - \data_temp_RNO_1[67]\ : MX2C - port map(A => N_736, B => N_825, S => N_1580, Y => - \data_selected[99]\); - - \data_temp_RNO[45]\ : NOR2A - port map(A => N_863_0, B => N_646, Y => \data_temp_5[45]\); - - \data_temp_RNO_3[46]\ : MX2C - port map(A => data_f0_out(78), B => data_f1_out(78), S => - \data_valid_and_ready[0]_net_1\, Y => N_846); - - \data_temp_RNO_0[112]\ : MX2C - port map(A => \data_temp[112]_net_1\, B => - \data_selected[144]\, S => \state[4]_net_1\, Y => N_713); - - \data_temp[68]\ : DFN1C0 - port map(D => \data_temp_5[68]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[68]_net_1\); - - \time_en_temp[2]\ : DFN1E0C0 - port map(D => N_858, CLK => HCLK_c, CLR => HRESETn_c, E => - state_0_sqmuxa_i, Q => \time_en_temp[2]_net_1\); - - \data_temp_RNO_2[98]\ : MX2C - port map(A => data_f2_out(130), B => data_f3_out(130), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1723); - - \data_temp_RNO_0[105]\ : MX2C - port map(A => \data_temp[105]_net_1\, B => - \data_selected[137]\, S => \state[4]_net_1\, Y => N_706); - - \data_temp_RNIDNBC[124]\ : OR2 - port map(A => \state[4]_net_1\, B => \data_temp[124]_net_1\, - Y => N_915); - - \data_temp[52]\ : DFN1C0 - port map(D => \data_temp_5[52]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[52]_net_1\); - - \data_temp_RNO_0[97]\ : MX2C - port map(A => \data_temp[97]_net_1\, B => - \data_selected[129]\, S => \state[4]_net_1\, Y => N_698); - - \data_temp_RNO_0[119]\ : MX2C - port map(A => \data_temp[119]_net_1\, B => - \data_selected[151]\, S => \state[4]_net_1\, Y => N_720); - - \data[2]\ : DFN1C0 - port map(D => \data_5[2]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(2)); - - \data_temp_RNO[73]\ : NOR2A - port map(A => N_863_2, B => N_674, Y => \data_temp_5[73]\); - - \data_temp[85]\ : DFN1C0 - port map(D => \data_temp_5[85]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[85]_net_1\); - - \data_temp_5_i_a2_0_0[32]\ : NOR2A - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - \data_valid_and_ready[3]_net_1\, Y => - \data_temp_5_i_a2_0_0[32]_net_1\); - - \data_valid_and_ready_1[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready_1[2]_net_1\); - - \data_temp_RNO_0[53]\ : MX2C - port map(A => \data_temp[85]_net_1\, B => - \data_selected[85]\, S => \state[4]_net_1\, Y => N_654); - - \data_temp_RNO_3[43]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[75]_net_1\, - Y => N_897); - - \data[22]\ : DFN1C0 - port map(D => \data_5[22]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(22)); - - \data_temp_RNO_2[126]\ : MX2C - port map(A => data_f2_out(158), B => data_f3_out(158), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1695); - - \data_temp_RNO[61]\ : NOR2A - port map(A => N_863_1, B => N_662, Y => \data_temp_5[61]\); - - \data_temp_RNO_0[68]\ : MX2C - port map(A => \data_temp[100]_net_1\, B => - \data_selected[100]\, S => \state[4]_net_1\, Y => N_669); - - \data_temp[67]\ : DFN1C0 - port map(D => \data_temp_5[67]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[67]_net_1\); - - \data_temp[21]\ : DFN1C0 - port map(D => \data_temp_5[21]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[21]_net_1\); - - \data_wen[2]\ : DFN1E0P0 - port map(D => \data_wen_3[2]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => data_wen(2)); - - \data_temp[9]\ : DFN1C0 - port map(D => \data_temp_5[9]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[9]_net_1\); - - \data_temp_RNO[62]\ : NOR2A - port map(A => N_863_1, B => N_663, Y => \data_temp_5[62]\); - - \data_temp_RNO[125]\ : NOR3B - port map(A => N_863_0, B => N_914, C => - \data_temp_5_i_0[125]\, Y => N_247); - - \data_temp_RNO_1[59]\ : MX2C - port map(A => N_742, B => N_831, S => N_1580_2, Y => - \data_selected[91]\); - - \data_temp_RNO_1[51]\ : MX2C - port map(A => N_748, B => N_837, S => N_1580_1, Y => - \data_selected[83]\); - - \data_temp_RNO_1[46]\ : MX2C - port map(A => N_757, B => N_846, S => N_1580_1, Y => - \data_selected[78]\); - - \data_temp[51]\ : DFN1C0 - port map(D => \data_temp_5[51]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[51]_net_1\); - - data_selected_sn_m2_0_o2_3 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_3); - - \data_temp_RNO_2[79]\ : MX2C - port map(A => data_f2_out(111), B => data_f3_out(111), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1732); - - \data_temp_RNO_2[71]\ : MX2C - port map(A => data_f2_out(103), B => data_f3_out(103), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_740); - - \data_temp_RNO_3[77]\ : MX2C - port map(A => data_f0_out(109), B => data_f1_out(109), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_807); - - \data_temp[120]\ : DFN1C0 - port map(D => \data_temp_5[120]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[120]_net_1\); - - \state_RNIKK3V21_3[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \time_wen_3_i_a2_0[3]_net_1\, C => N_1580_0, Y => N_860); - - \data_temp[106]\ : DFN1C0 - port map(D => \data_temp_5[106]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[106]_net_1\); - - \time_wen[3]\ : DFN1E0P0 - port map(D => N_860, CLK => HCLK_c, PRE => HRESETn_c, E => - N_928, Q => time_wen(3)); - - \data_temp_RNO_2[49]\ : MX2C - port map(A => data_f2_out(81), B => data_f3_out(81), S => - \data_valid_and_ready[2]_net_1\, Y => N_760); - - \data_temp_RNO_2[41]\ : MX2 - port map(A => data_f0_out(73), B => data_f1_out(73), S => - \data_valid_and_ready[0]_net_1\, Y => N_841); - - \data_temp_RNO[127]\ : NOR2A - port map(A => N_863_0, B => N_728, Y => \data_temp_5[127]\); - - \data_temp_RNO_0[107]\ : MX2C - port map(A => \data_temp[107]_net_1\, B => - \data_selected[139]\, S => \state[4]_net_1\, Y => N_708); - - \data_temp_RNO_0[77]\ : MX2C - port map(A => \data_temp[109]_net_1\, B => - \data_selected[109]\, S => \state[4]_net_1\, Y => N_678); - - \data_temp_RNO_1[43]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_768, - Y => N_898); - - \data_temp_RNO[57]\ : NOR2A - port map(A => N_863_1, B => N_658, Y => \data_temp_5[57]\); - - \data_temp_RNO[64]\ : NOR2A - port map(A => N_863, B => N_665, Y => \data_temp_5[64]\); - - \data_temp[14]\ : DFN1C0 - port map(D => \data_temp_5[14]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[14]_net_1\); - - \data_temp_RNO[87]\ : NOR2A - port map(A => N_863, B => N_688, Y => \data_temp_5[87]\); - - \data_temp[114]\ : DFN1C0 - port map(D => \data_temp_5[114]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[114]_net_1\); - - \data_temp_RNO_0[124]\ : AO1D - port map(A => N_1681, B => N_912_i, C => N_904, Y => - \data_temp_5_i_0[124]\); - - \data_temp_RNO[110]\ : NOR2A - port map(A => N_863_1, B => N_711, Y => \data_temp_5[110]\); - - \data_temp_RNO_3[111]\ : MX2C - port map(A => data_f0_out(143), B => data_f1_out(143), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_771); - - \data_temp_RNO_0[121]\ : MX2C - port map(A => \data_temp[121]_net_1\, B => - \data_selected[153]\, S => \state[4]_net_1\, Y => N_722); - - \data_temp_RNO[105]\ : NOR2A - port map(A => N_863_2, B => N_706, Y => \data_temp_5[105]\); - - \data[29]\ : DFN1C0 - port map(D => \data_5[29]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(29)); - - \data_temp_RNO_1[78]\ : MX2C - port map(A => N_733, B => N_808, S => N_1580_2, Y => - \data_selected[110]\); - - \data_temp[32]\ : DFN1C0 - port map(D => N_215, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[32]_net_1\); - - \data_temp_RNO_0[118]\ : MX2C - port map(A => \data_temp[118]_net_1\, B => - \data_selected[150]\, S => \state[4]_net_1\, Y => N_719); - - \data_temp[28]\ : DFN1C0 - port map(D => \data_temp_5[28]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[28]_net_1\); - - \data_temp_RNO_3[96]\ : MX2C - port map(A => data_f0_out(128), B => data_f1_out(128), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_798); - - \data_temp[117]\ : DFN1C0 - port map(D => \data_temp_5[117]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[117]_net_1\); - - \data_RNO[19]\ : NOR2A - port map(A => \data_temp[19]_net_1\, B => \state[4]_net_1\, - Y => \data_5[19]\); - - \data_temp_RNO_4[37]\ : MX2 - port map(A => data_f2_out(69), B => data_f3_out(69), S => - \data_valid_and_ready[2]_net_1\, Y => N_762); - - data_selected_sn_m2_0_o2 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580); - - \data_temp[58]\ : DFN1C0 - port map(D => \data_temp_5[58]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[58]_net_1\); - - \data_temp_RNO_1[55]\ : MX2C - port map(A => N_752, B => N_827, S => N_1580_1, Y => - \data_selected[87]\); - - \data_temp_RNO_3[104]\ : MX2C - port map(A => data_f0_out(136), B => data_f1_out(136), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_778); - - \data_temp_RNO_1[88]\ : MX2C - port map(A => N_1727, B => N_804, S => N_1580, Y => - \data_selected[120]\); - - \data_temp_RNO[107]\ : NOR2A - port map(A => N_863_2, B => N_708, Y => \data_temp_5[107]\); - - \state_RNIKK3V21_1[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \data_temp_5_i_a2_0_0[32]_net_1\, C => N_1580_0, Y => - N_863_2); - - \data[25]\ : DFN1C0 - port map(D => \data_5[25]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(25)); - - \data_temp_RNO_3[93]\ : MX2 - port map(A => data_f2_out(125), B => data_f3_out(125), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1718); - - \data_temp_RNO_2[75]\ : MX2C - port map(A => data_f2_out(107), B => data_f3_out(107), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_730); - - \data_valid_and_ready_0[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready_0[2]_net_1\); - - \data_temp_RNO_1[115]\ : MX2C - port map(A => N_1698, B => N_775, S => N_1580_3, Y => - \data_selected[147]\); - - \data_temp[27]\ : DFN1C0 - port map(D => \data_temp_5[27]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[27]_net_1\); - - \data_temp_RNO_1[54]\ : MX2C - port map(A => N_751, B => N_840, S => N_1580_1, Y => - \data_selected[86]\); - - \data_temp_RNO[38]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[38]\, C => - N_1657, Y => N_229); - - \data_temp_RNO_2[45]\ : MX2C - port map(A => data_f2_out(77), B => data_f3_out(77), S => - \data_valid_and_ready[2]_net_1\, Y => N_756); - - \data_temp_RNO_1[98]\ : MX2C - port map(A => N_1723, B => N_786, S => N_1580, Y => - \data_selected[130]\); - - \data_temp[31]\ : DFN1C0 - port map(D => \data_temp_5[31]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[31]_net_1\); - - \data_temp_RNO_1[102]\ : MX2C - port map(A => N_1713, B => N_790, S => N_1580_3, Y => - \data_selected[134]\); - - \data_temp[3]\ : DFN1C0 - port map(D => \data_temp_5[3]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[3]_net_1\); - - \data_temp_RNO_2[74]\ : MX2C - port map(A => data_f2_out(106), B => data_f3_out(106), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_729); - - \data_temp[65]\ : DFN1C0 - port map(D => \data_temp_5[65]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[65]_net_1\); - - \data_temp[57]\ : DFN1C0 - port map(D => \data_temp_5[57]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[57]_net_1\); - - \state_RNIHQ76Q[4]\ : OR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => - \data_valid_and_ready_0[2]_net_1\, Y => N_859); - - \data_temp_RNO_3[115]\ : MX2C - port map(A => data_f0_out(147), B => data_f1_out(147), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_775); - - \state_RNO[3]\ : INV - port map(A => state_0_sqmuxa_i, Y => state_0_sqmuxa_i_i); - - \data_temp[7]\ : DFN1C0 - port map(D => \data_temp_5[7]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[7]_net_1\); - - \data_temp_RNO[33]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[33]\, C => - N_868, Y => N_219); - - \data_temp_RNO_2[44]\ : MX2C - port map(A => data_f2_out(76), B => data_f3_out(76), S => - \data_valid_and_ready[2]_net_1\, Y => N_755); - - \data_temp_RNO_2[118]\ : MX2C - port map(A => data_f2_out(150), B => data_f3_out(150), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1701); - - \data_temp_RNO_1[116]\ : MX2C - port map(A => N_1699, B => N_776, S => N_1580_3, Y => - \data_selected[148]\); - - \data_temp[96]\ : DFN1C0 - port map(D => \data_temp_5[96]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[96]_net_1\); - - \data_temp_RNO_0[87]\ : MX2C - port map(A => \data_temp[119]_net_1\, B => - \data_selected[119]\, S => \state[4]_net_1\, Y => N_688); - - \data_temp[115]\ : DFN1C0 - port map(D => \data_temp_5[115]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[115]_net_1\); - - \data_temp_RNO_3[100]\ : MX2C - port map(A => data_f0_out(132), B => data_f1_out(132), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_788); - - \data[14]\ : DFN1C0 - port map(D => \data_5[14]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(14)); - - \data_temp_RNO_2[97]\ : MX2C - port map(A => data_f2_out(129), B => data_f3_out(129), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1722); - - \data_temp_RNO_0[123]\ : AO1D - port map(A => N_1680, B => N_912_i, C => N_910, Y => - \data_temp_5_i_0[123]\); - - \data_temp_RNO[71]\ : NOR2A - port map(A => N_863_2, B => N_672, Y => \data_temp_5[71]\); - - \data_temp[43]\ : DFN1C0 - port map(D => N_239, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[43]_net_1\); - - \data_temp_RNO_0[46]\ : MX2C - port map(A => \data_temp[78]_net_1\, B => - \data_selected[78]\, S => \state[4]_net_1\, Y => N_647); - - \data_temp_RNO_1[60]\ : MX2C - port map(A => N_743, B => N_832, S => N_1580_2, Y => - \data_selected[92]\); - - \data_temp_RNO_1[121]\ : MX2C - port map(A => N_1690, B => N_1678, S => N_1580, Y => - \data_selected[153]\); - - \data_temp_RNO_2[36]\ : MX2 - port map(A => data_f0_out(68), B => data_f1_out(68), S => - \data_valid_and_ready[0]_net_1\, Y => N_850); - - \data_temp_RNO[72]\ : NOR2A - port map(A => N_863_2, B => N_673, Y => \data_temp_5[72]\); - - \data_temp_RNO[116]\ : NOR2A - port map(A => N_863_2, B => N_717, Y => \data_temp_5[116]\); - - \data_temp_RNO_0[90]\ : MX2C - port map(A => \data_temp[122]_net_1\, B => - \data_selected[122]\, S => \state[4]_net_1\, Y => N_691); - - \data_RNO[24]\ : NOR2A - port map(A => \data_temp[24]_net_1\, B => \state[4]_net_1\, - Y => \data_5[24]\); - - \data_temp_RNO_1[109]\ : MX2C - port map(A => N_1706, B => N_783, S => N_1580, Y => - \data_selected[141]\); - - \data_temp_RNO[90]\ : NOR2A - port map(A => N_863, B => N_691, Y => \data_temp_5[90]\); - - \data_temp_RNO[48]\ : NOR2A - port map(A => N_863_1, B => N_649, Y => \data_temp_5[48]\); - - \data_temp_RNO_1[108]\ : MX2C - port map(A => N_1705, B => N_782, S => N_1580_2, Y => - \data_selected[140]\); - - \data_temp[72]\ : DFN1C0 - port map(D => \data_temp_5[72]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[72]_net_1\); - - \data_temp_RNO_2[111]\ : MX2C - port map(A => data_f2_out(143), B => data_f3_out(143), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1708); - - \data_temp_RNO[5]\ : NOR2A - port map(A => \data_temp[37]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[5]\); - - \data_temp_RNO_4[43]\ : MX2 - port map(A => data_f2_out(75), B => data_f3_out(75), S => - \data_valid_and_ready[2]_net_1\, Y => N_768); - - \data_temp_RNO[55]\ : NOR2A - port map(A => N_863_1, B => N_656, Y => \data_temp_5[55]\); - - \data_temp_RNO_0[67]\ : MX2C - port map(A => \data_temp[99]_net_1\, B => - \data_selected[99]\, S => \state[4]_net_1\, Y => N_668); - - \data_temp_RNO_0[43]\ : AO1D - port map(A => N_912_i, B => N_843, C => N_897, Y => - \data_temp_5_i_0[43]\); - - \data_temp[38]\ : DFN1C0 - port map(D => N_229, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[38]_net_1\); - - \data_RNO[20]\ : NOR2A - port map(A => \data_temp[20]_net_1\, B => \state[4]_net_1\, - Y => \data_5[20]\); - - \data_temp_RNO[85]\ : NOR2A - port map(A => N_863_2, B => N_686, Y => \data_temp_5[85]\); - - \data_temp_RNO[7]\ : NOR2A - port map(A => \data_temp[39]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[7]\); - - \data_temp_RNO[43]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[43]\, C => - N_898, Y => N_239); - - \data_temp[103]\ : DFN1C0 - port map(D => \data_temp_5[103]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[103]_net_1\); - - \data[10]\ : DFN1C0 - port map(D => \data_5[10]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(10)); - - \data_temp_RNO_2[33]\ : MX2 - port map(A => data_f0_out(65), B => data_f1_out(65), S => - \data_valid_and_ready_0[0]_net_1\, Y => N_770); - - \data_temp_RNO_3[58]\ : MX2C - port map(A => data_f0_out(90), B => data_f1_out(90), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_830); - - \data_temp_RNO_3[68]\ : MX2C - port map(A => data_f0_out(100), B => data_f1_out(100), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_826); - - \data_temp_RNO_0[102]\ : MX2C - port map(A => \data_temp[102]_net_1\, B => - \data_selected[134]\, S => \state[4]_net_1\, Y => N_703); - - \state[4]\ : DFN1P0 - port map(D => N_861, CLK => HCLK_c, PRE => HRESETn_c, Q => - \state_0[4]\); - - \data_temp_RNO_3[88]\ : MX2C - port map(A => data_f0_out(120), B => data_f1_out(120), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_804); - - \data_temp_RNO[74]\ : NOR2A - port map(A => N_863_2, B => N_675, Y => \data_temp_5[74]\); - - \data_temp_RNO_2[59]\ : MX2C - port map(A => data_f2_out(91), B => data_f3_out(91), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_742); - - \data_temp_RNO_2[51]\ : MX2C - port map(A => data_f2_out(83), B => data_f3_out(83), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_748); - - \data_temp_RNO_0[109]\ : MX2C - port map(A => \data_temp[109]_net_1\, B => - \data_selected[141]\, S => \state[4]_net_1\, Y => N_710); - - \data_temp_RNO_3[113]\ : MX2C - port map(A => data_f0_out(145), B => data_f1_out(145), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_773); - - \data_temp_RNO_1[62]\ : MX2C - port map(A => N_745, B => N_820, S => N_1580_2, Y => - \data_selected[94]\); - - \data_temp_RNO_1[114]\ : MX2C - port map(A => N_1697, B => N_774, S => N_1580_3, Y => - \data_selected[146]\); - - \data_temp_RNO_0[92]\ : AO1D - port map(A => N_912_i, B => N_794, C => N_900, Y => - \data_temp_5_i_0[92]\); - - \data_valid_and_ready[3]\ : NOR2B - port map(A => valid_out_3, B => ready_i_0(3), Y => - \data_valid_and_ready[3]_net_1\); - - \data_temp[37]\ : DFN1C0 - port map(D => N_227, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[37]_net_1\); - - \data_temp[71]\ : DFN1C0 - port map(D => \data_temp_5[71]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[71]_net_1\); - - \data_temp_RNO_3[70]\ : MX2C - port map(A => data_f0_out(102), B => data_f1_out(102), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_814); - - \data_temp_RNO_0[39]\ : AO1D - port map(A => N_912_i, B => N_853, C => N_1659, Y => - \data_temp_5_i_0[39]\); - - \state_RNIR1JC[3]\ : NOR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => N_929); - - \data_temp[25]\ : DFN1C0 - port map(D => \data_temp_5[25]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[25]_net_1\); - - \data_temp_RNO[9]\ : NOR2A - port map(A => \data_temp[41]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[9]\); - - \data_RNO[25]\ : NOR2A - port map(A => \data_temp[25]_net_1\, B => \state[4]_net_1\, - Y => \data_5[25]\); - - \data_temp_RNO_0[70]\ : MX2C - port map(A => \data_temp[102]_net_1\, B => - \data_selected[102]\, S => \state[4]_net_1\, Y => N_671); - - \data_temp[55]\ : DFN1C0 - port map(D => \data_temp_5[55]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[55]_net_1\); - - \data_temp_RNO_1[77]\ : MX2C - port map(A => N_732, B => N_807, S => N_1580, Y => - \data_selected[109]\); - - \data_temp_RNO_2[88]\ : MX2C - port map(A => data_f2_out(120), B => data_f3_out(120), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1727); - - \data_temp_RNO_2[113]\ : MX2C - port map(A => data_f2_out(145), B => data_f3_out(145), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1710); - - \data_temp_RNO_3[38]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[70]_net_1\, - Y => N_1656); - - \data_temp[40]\ : DFN1C0 - port map(D => N_233, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[40]_net_1\); - - \data_temp_RNO[120]\ : NOR2A - port map(A => N_863, B => N_721, Y => \data_temp_5[120]\); - - \data_temp_RNO_1[87]\ : MX2C - port map(A => N_1726, B => N_803, S => N_1580_3, Y => - \data_selected[119]\); - - \data_temp[12]\ : DFN1C0 - port map(D => \data_temp_5[12]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[12]_net_1\); - - \data_temp_RNO_2[55]\ : MX2C - port map(A => data_f2_out(87), B => data_f3_out(87), S => - \data_valid_and_ready[2]_net_1\, Y => N_752); - - \data_temp_RNO_3[72]\ : MX2C - port map(A => data_f0_out(104), B => data_f1_out(104), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_816); - - \data_wen[1]\ : DFN1E0P0 - port map(D => \data_wen_3[1]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => data_wen(1)); - - \data_temp_RNO[19]\ : NOR2A - port map(A => \data_temp[51]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[19]\); - - \data_temp[94]\ : DFN1C0 - port map(D => \data_temp_5[94]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[94]_net_1\); - - \data_temp[78]\ : DFN1C0 - port map(D => \data_temp_5[78]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[78]_net_1\); - - \data_temp_RNO_2[68]\ : MX2C - port map(A => data_f2_out(100), B => data_f3_out(100), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_737); - - \data_temp_RNO_3[101]\ : MX2C - port map(A => data_f0_out(133), B => data_f1_out(133), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_789); - - \data_temp_RNO_2[54]\ : MX2C - port map(A => data_f2_out(86), B => data_f3_out(86), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_751); - - \data_temp_RNO_1[97]\ : MX2C - port map(A => N_1722, B => N_785, S => N_1580, Y => - \data_selected[129]\); - - \data_temp_RNO_0[72]\ : MX2C - port map(A => \data_temp[104]_net_1\, B => - \data_selected[104]\, S => \state[4]_net_1\, Y => N_673); - - \data_temp_RNO_0[35]\ : AO1D - port map(A => N_912_i, B => N_849, C => N_873, Y => - \data_temp_5_i_0[35]\); - - \data_RNO[7]\ : NOR2A - port map(A => \data_temp[7]_net_1\, B => \state[4]_net_1\, - Y => \data_5[7]\); - - \data_temp_RNO[31]\ : NOR2A - port map(A => \data_temp[63]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[31]\); - - \data_temp_RNO_0[108]\ : MX2C - port map(A => \data_temp[108]_net_1\, B => - \data_selected[140]\, S => \state[4]_net_1\, Y => N_709); - - \data[27]\ : DFN1C0 - port map(D => \data_5[27]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(27)); - - \data_temp_RNICJBC[123]\ : OR2 - port map(A => \state[4]_net_1\, B => \data_temp[123]_net_1\, - Y => N_913); - - \data_temp[5]\ : DFN1C0 - port map(D => \data_temp_5[5]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[5]_net_1\); - - \data_temp_RNO[32]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[32]\, C => - N_865, Y => N_215); - - \data_temp_RNO[16]\ : NOR2A - port map(A => \data_temp[48]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[16]\); - - \data_temp_RNO_0[34]\ : AO1D - port map(A => N_912_i, B => N_848, C => N_870, Y => - \data_temp_5_i_0[34]\); - - \data_temp_RNO[100]\ : NOR2A - port map(A => N_863, B => N_701, Y => \data_temp_5[100]\); - - \state[1]\ : DFN1C0 - port map(D => \state[2]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[1]_net_1\); - - \data_temp[102]\ : DFN1C0 - port map(D => \data_temp_5[102]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[102]_net_1\); - - \data_temp_RNO_1[56]\ : MX2C - port map(A => N_753, B => N_828, S => N_1580_1, Y => - \data_selected[88]\); - - \data_temp[77]\ : DFN1C0 - port map(D => \data_temp_5[77]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[77]_net_1\); - - \data_temp[11]\ : DFN1C0 - port map(D => \data_temp_5[11]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[11]_net_1\); - - \data_temp[89]\ : DFN1C0 - port map(D => \data_temp_5[89]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[89]_net_1\); - - \data_RNO[0]\ : NOR2A - port map(A => \data_temp[0]_net_1\, B => \state[4]_net_1\, - Y => \data_5[0]\); - - \data_temp_RNO_4[32]\ : MX2 - port map(A => data_f2_out(64), B => data_f3_out(64), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1685); - - \data_temp_RNO[118]\ : NOR2A - port map(A => N_863, B => N_719, Y => \data_temp_5[118]\); - - \data_temp_RNO_2[76]\ : MX2C - port map(A => data_f2_out(108), B => data_f3_out(108), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_731); - - \data_temp_RNO_0[80]\ : MX2C - port map(A => \data_temp[112]_net_1\, B => - \data_selected[112]\, S => \state[4]_net_1\, Y => N_681); - - \data_temp_RNO_1[105]\ : MX2C - port map(A => N_1716, B => N_779, S => N_1580_3, Y => - \data_selected[137]\); - - \data_temp[35]\ : DFN1C0 - port map(D => N_223, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[35]_net_1\); - - \data_temp_RNO_2[90]\ : MX2C - port map(A => data_f2_out(122), B => data_f3_out(122), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1729); - - \data_temp_RNO_2[114]\ : MX2C - port map(A => data_f2_out(146), B => data_f3_out(146), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1697); - - data_selected_sn_m2_0_o2_1 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_1); - - \data_temp_RNO_2[46]\ : MX2C - port map(A => data_f2_out(78), B => data_f3_out(78), S => - \data_valid_and_ready[2]_net_1\, Y => N_757); - - \data_valid_and_ready_2[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready_2[0]_net_1\); - - \data_temp_RNO_1[53]\ : MX2C - port map(A => N_750, B => N_839, S => N_1580_1, Y => - \data_selected[85]\); - - \data_temp_RNO[34]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[34]\, C => - N_871, Y => N_221); - - \data_temp_RNO[0]\ : NOR2A - port map(A => \data_temp[32]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[0]\); - - \data_temp_RNO[41]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[41]\, C => - N_1666, Y => N_235); - - \data_temp_RNO_3[105]\ : MX2C - port map(A => data_f0_out(137), B => data_f1_out(137), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_779); - - \data[8]\ : DFN1C0 - port map(D => \data_5[8]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(8)); - - \data_temp_RNO_2[73]\ : MX2C - port map(A => data_f2_out(105), B => data_f3_out(105), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1740); - - state_0_sqmuxa_i_0_o2_0_a2 : NOR2 - port map(A => \data_valid_and_ready[3]_net_1\, B => N_916, - Y => N_1306); - - \data_temp_RNO_2[108]\ : MX2C - port map(A => data_f2_out(140), B => data_f3_out(140), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1705); - - \data_temp_RNO[60]\ : NOR2A - port map(A => N_863_1, B => N_661, Y => \data_temp_5[60]\); - - \data_temp_RNO_1[106]\ : MX2C - port map(A => N_1717, B => N_780, S => N_1580_2, Y => - \data_selected[138]\); - - \data_temp_RNO[42]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[42]\, C => - N_1669, Y => N_237); - - \data_temp_RNO_2[43]\ : MX2 - port map(A => data_f0_out(75), B => data_f1_out(75), S => - \data_valid_and_ready[0]_net_1\, Y => N_843); - - \data_RNO[4]\ : NOR2A - port map(A => \data_temp[4]_net_1\, B => \state[4]_net_1\, - Y => \data_5[4]\); - - \data_temp_RNO_3[57]\ : MX2C - port map(A => data_f0_out(89), B => data_f1_out(89), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_829); - - \data_temp_RNO[126]\ : NOR2A - port map(A => N_863_1, B => N_727, Y => \data_temp_5[126]\); - - \data_temp_RNO_0[60]\ : MX2C - port map(A => \data_temp[92]_net_1\, B => - \data_selected[92]\, S => \state[4]_net_1\, Y => N_661); - - \data_temp_RNO_3[67]\ : MX2C - port map(A => data_f0_out(99), B => data_f1_out(99), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_825); - - \data_temp_RNO_2[117]\ : MX2C - port map(A => data_f2_out(149), B => data_f3_out(149), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1700); - - \data_temp_RNO_3[87]\ : MX2C - port map(A => data_f0_out(119), B => data_f1_out(119), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_803); - - \data_temp_RNO[58]\ : NOR2A - port map(A => N_863_1, B => N_659, Y => \data_temp_5[58]\); - - \data_temp[2]\ : DFN1C0 - port map(D => \data_temp_5[2]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[2]_net_1\); - - \data_temp_RNO[29]\ : NOR2A - port map(A => \data_temp[61]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[29]\); - - \data_temp[18]\ : DFN1C0 - port map(D => \data_temp_5[18]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[18]_net_1\); - - \data_temp_RNO_0[82]\ : MX2C - port map(A => \data_temp[114]_net_1\, B => - \data_selected[114]\, S => \state[4]_net_1\, Y => N_683); - - \data_temp_RNO[88]\ : NOR2A - port map(A => N_863, B => N_689, Y => \data_temp_5[88]\); - - \data_temp_RNO_2[92]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1731, - Y => N_900); - - \data_temp_RNO[8]\ : NOR2A - port map(A => \data_temp[40]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[8]\); - - \data_temp[101]\ : DFN1C0 - port map(D => \data_temp_5[101]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[101]_net_1\); - - \data_temp_RNO_2[101]\ : MX2C - port map(A => data_f2_out(133), B => data_f3_out(133), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1712); - - \data_temp_RNO[53]\ : NOR2A - port map(A => N_863_1, B => N_654, Y => \data_temp_5[53]\); - - \data_temp_RNO[44]\ : NOR2A - port map(A => N_863_0, B => N_645, Y => \data_temp_5[44]\); - - \data_temp_RNO[83]\ : NOR2A - port map(A => N_863_2, B => N_684, Y => \data_temp_5[83]\); - - \time_en_temp[0]\ : DFN1E0C0 - port map(D => \data_valid_and_ready[0]_net_1\, CLK => - HCLK_c, CLR => HRESETn_c, E => state_0_sqmuxa_i, Q => - \time_en_temp[0]_net_1\); - - \data_temp_RNO[26]\ : NOR2A - port map(A => \data_temp[58]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[26]\); - - \data_temp[126]\ : DFN1C0 - port map(D => \data_temp_5[126]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[126]_net_1\); - - \data_temp_RNO[106]\ : NOR2A - port map(A => N_863_2, B => N_707, Y => \data_temp_5[106]\); - - \data_temp[17]\ : DFN1C0 - port map(D => \data_temp_5[17]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[17]_net_1\); - - \data_temp[109]\ : DFN1C0 - port map(D => \data_temp_5[109]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[109]_net_1\); - - \data_temp_RNO_0[62]\ : MX2C - port map(A => \data_temp[94]_net_1\, B => - \data_selected[94]\, S => \state[4]_net_1\, Y => N_663); - - \data_RNO[23]\ : NOR2A - port map(A => \data_temp[23]_net_1\, B => \state[4]_net_1\, - Y => \data_5[23]\); - - \data[6]\ : DFN1C0 - port map(D => \data_5[6]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(6)); - - \data_temp_RNO[17]\ : NOR2A - port map(A => \data_temp[49]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[17]\); - - un23_data_selected_i_a2 : OR2A - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - N_1580_1, Y => N_916); - - \data_temp_RNO_2[87]\ : MX2C - port map(A => data_f2_out(119), B => data_f3_out(119), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1726); - - \data_temp_RNO[114]\ : NOR2A - port map(A => N_863_2, B => N_715, Y => \data_temp_5[114]\); - - \data_temp_RNO_3[103]\ : MX2C - port map(A => data_f0_out(135), B => data_f1_out(135), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_791); - - \data_temp_RNO_1[70]\ : MX2C - port map(A => N_739, B => N_814, S => N_1580_3, Y => - \data_selected[102]\); - - \data_temp[75]\ : DFN1C0 - port map(D => \data_temp_5[75]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[75]_net_1\); - - \data_temp_RNO_3[37]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[69]_net_1\, - Y => N_1653); - - \data_temp_RNO_1[38]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_763, - Y => N_1657); - - \data_temp_RNO_1[104]\ : MX2C - port map(A => N_1715, B => N_778, S => N_1580_3, Y => - \data_selected[136]\); - - \state_RNIKK3V21_0[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \data_temp_5_i_a2_0_0[32]_net_1\, C => N_1580_0, Y => - N_863_1); - - \data_temp[46]\ : DFN1C0 - port map(D => \data_temp_5[46]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[46]_net_1\); - - \data_temp_RNO[111]\ : NOR2A - port map(A => N_863_2, B => N_712, Y => \data_temp_5[111]\); - - \data_temp_RNO_2[110]\ : MX2C - port map(A => data_f2_out(142), B => data_f3_out(142), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1707); - - \data_temp[69]\ : DFN1C0 - port map(D => \data_temp_5[69]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[69]_net_1\); - - \data_temp_RNO_1[80]\ : MX2C - port map(A => N_1733, B => N_810, S => N_1580_2, Y => - \data_selected[112]\); - - \data_temp_RNO_2[67]\ : MX2C - port map(A => data_f2_out(99), B => data_f3_out(99), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_736); - - \data_RNO[27]\ : NOR2A - port map(A => \data_temp[27]_net_1\, B => \state[4]_net_1\, - Y => \data_5[27]\); - - \data_temp_RNO[6]\ : NOR2A - port map(A => \data_temp[38]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[6]\); - - \data_temp_RNO_0[126]\ : MX2C - port map(A => \data_temp[126]_net_1\, B => - \data_selected[158]\, S => \state[4]_net_1\, Y => N_727); - - \data_temp_RNO_1[90]\ : MX2C - port map(A => N_1729, B => N_792, S => N_1580, Y => - \data_selected[122]\); - - \data[23]\ : DFN1C0 - port map(D => \data_5[23]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(23)); - - \data_temp_RNO_2[103]\ : MX2C - port map(A => data_f2_out(135), B => data_f3_out(135), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1714); - - \state_RNIKK3V21[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \data_temp_5_i_a2_0_0[32]_net_1\, C => N_1580_0, Y => - N_863_0); - - \data_temp_RNO_1[72]\ : MX2C - port map(A => N_1739, B => N_816, S => N_1580_3, Y => - \data_selected[104]\); - - \data_temp_RNO_0[58]\ : MX2C - port map(A => \data_temp[90]_net_1\, B => - \data_selected[90]\, S => \state[4]_net_1\, Y => N_659); - - \data_temp_RNO_1[117]\ : MX2C - port map(A => N_1700, B => N_777, S => N_1580_3, Y => - \data_selected[149]\); - - \data_temp[4]\ : DFN1C0 - port map(D => \data_temp_5[4]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[4]_net_1\); - - \data_wen_RNO[2]\ : OR2 - port map(A => \time_en_temp[2]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[2]\); - - \data_temp_RNO_3[48]\ : MX2C - port map(A => data_f0_out(80), B => data_f1_out(80), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_834); - - \data_temp[92]\ : DFN1C0 - port map(D => N_241, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[92]_net_1\); - - \data_temp_RNO_2[56]\ : MX2C - port map(A => data_f2_out(88), B => data_f3_out(88), S => - \data_valid_and_ready[2]_net_1\, Y => N_753); - - \state_RNIKK3V21_2[4]\ : OR3B - port map(A => \state[4]_net_1\, B => - \data_temp_5_i_a2_0_0[32]_net_1\, C => N_1580_0, Y => - N_863); - - \data_temp_RNO[70]\ : NOR2A - port map(A => N_863_2, B => N_671, Y => \data_temp_5[70]\); - - \data_temp_RNO_1[82]\ : MX2C - port map(A => N_1735, B => N_812, S => N_1580_3, Y => - \data_selected[114]\); - - \data_RNO[18]\ : NOR2A - port map(A => \data_temp[18]_net_1\, B => \state[4]_net_1\, - Y => \data_5[18]\); - - \time_wen[0]\ : DFN1E0P0 - port map(D => \time_wen_3[0]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => time_wen(0)); - - \data_temp_RNO_1[120]\ : MX2C - port map(A => N_1703, B => N_1677, S => N_1580, Y => - \data_selected[152]\); - - \data_temp_RNO_0[36]\ : AO1D - port map(A => N_912_i, B => N_850, C => N_1650, Y => - \data_temp_5_i_0[36]\); - - \data_temp_RNO_2[53]\ : MX2C - port map(A => data_f2_out(85), B => data_f3_out(85), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_750); - - \data_temp_RNO_1[69]\ : MX2C - port map(A => N_738, B => N_813, S => N_1580_3, Y => - \data_selected[101]\); - - \data_temp_RNO_1[61]\ : MX2C - port map(A => N_744, B => N_833, S => N_1580_2, Y => - \data_selected[93]\); - - \state[0]\ : DFN1C0 - port map(D => \state[1]_net_1\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[0]_net_1\); - - \data_temp_RNO[27]\ : NOR2A - port map(A => \data_temp[59]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[27]\); - - \data_temp_RNO_1[92]\ : MX2 - port map(A => data_f0_out(124), B => data_f1_out(124), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_794); - - \data_temp_RNO_0[99]\ : MX2C - port map(A => \data_temp[99]_net_1\, B => - \data_selected[131]\, S => \state[4]_net_1\, Y => N_700); - - \data_temp_RNO_0[91]\ : AO1D - port map(A => N_912_i, B => N_793, C => N_908, Y => - \data_temp_5_i_0[91]\); - - \data_temp[15]\ : DFN1C0 - port map(D => \data_temp_5[15]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[15]_net_1\); - - \data_temp_RNO[119]\ : NOR2A - port map(A => N_863, B => N_720, Y => \data_temp_5[119]\); - - \data_RNO[1]\ : NOR2A - port map(A => \data_temp[1]_net_1\, B => \state[4]_net_1\, - Y => \data_5[1]\); - - \data_temp_RNO_3[117]\ : MX2C - port map(A => data_f0_out(149), B => data_f1_out(149), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_777); - - \data_temp_RNO_0[33]\ : AO1D - port map(A => N_912_i, B => N_770, C => N_867, Y => - \data_temp_5_i_0[33]\); - - \data_temp[91]\ : DFN1C0 - port map(D => N_249, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[91]_net_1\); - - \data_temp_RNO_0[125]\ : AO1D - port map(A => N_1682, B => N_912_i, C => N_906, Y => - \data_temp_5_i_0[125]\); - - \data_temp_RNO_0[110]\ : MX2C - port map(A => \data_temp[110]_net_1\, B => - \data_selected[142]\, S => \state[4]_net_1\, Y => N_711); - - \data_temp_RNO_1[48]\ : MX2C - port map(A => N_759, B => N_834, S => N_1580_1, Y => - \data_selected[80]\); - - \data_temp_RNO[15]\ : NOR2A - port map(A => \data_temp[47]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[15]\); - - \data[18]\ : DFN1C0 - port map(D => \data_5[18]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(18)); - - \data_temp[29]\ : DFN1C0 - port map(D => \data_temp_5[29]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[29]_net_1\); - - \data_temp_RNO_3[50]\ : MX2C - port map(A => data_f0_out(82), B => data_f1_out(82), S => - \data_valid_and_ready[0]_net_1\, Y => N_836); - - \data_temp[110]\ : DFN1C0 - port map(D => \data_temp_5[110]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[110]_net_1\); - - data_selected_sn_m2_0_o2_0 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_0); - - \data_temp_RNO[51]\ : NOR2A - port map(A => N_863_1, B => N_652, Y => \data_temp_5[51]\); - - \data_temp_RNO[113]\ : NOR2A - port map(A => N_863_2, B => N_714, Y => \data_temp_5[113]\); - - \data_temp_RNO_3[60]\ : MX2C - port map(A => data_f0_out(92), B => data_f1_out(92), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_832); - - \data_temp[123]\ : DFN1C0 - port map(D => N_251, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[123]_net_1\); - - \data_temp_RNO_3[80]\ : MX2C - port map(A => data_f0_out(112), B => data_f1_out(112), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_810); - - \data_temp_RNO_2[104]\ : MX2C - port map(A => data_f2_out(136), B => data_f3_out(136), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1715); - - \data_temp_RNO[81]\ : NOR2A - port map(A => N_863_2, B => N_682, Y => \data_temp_5[81]\); - - \data_temp_RNO[1]\ : NOR2A - port map(A => \data_temp[33]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[1]\); - - \data_temp[59]\ : DFN1C0 - port map(D => \data_temp_5[59]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[59]_net_1\); - - \data_temp_RNO[52]\ : NOR2A - port map(A => N_863_1, B => N_653, Y => \data_temp_5[52]\); - - \data_temp_RNO[82]\ : NOR2A - port map(A => N_863_2, B => N_683, Y => \data_temp_5[82]\); - - \data_temp_RNO[108]\ : NOR2A - port map(A => N_863_1, B => N_709, Y => \data_temp_5[108]\); - - \data_temp_RNO_3[112]\ : MX2C - port map(A => data_f0_out(144), B => data_f1_out(144), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_772); - - \data_temp_RNO_3[79]\ : MX2C - port map(A => data_f0_out(111), B => data_f1_out(111), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_809); - - \data_temp_RNO_3[71]\ : MX2C - port map(A => data_f0_out(103), B => data_f1_out(103), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_815); - - \data_temp[44]\ : DFN1C0 - port map(D => \data_temp_5[44]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[44]_net_1\); - - \data_temp_RNO_1[65]\ : MX2C - port map(A => N_734, B => N_823, S => N_1580, Y => - \data_selected[97]\); - - \data_temp_RNO_2[107]\ : MX2C - port map(A => data_f2_out(139), B => data_f3_out(139), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1704); - - \data_temp_RNO_3[98]\ : MX2C - port map(A => data_f0_out(130), B => data_f1_out(130), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_786); - - \data_temp_RNO_0[95]\ : MX2C - port map(A => \data_temp[127]_net_1\, B => - \data_selected[127]\, S => \state[4]_net_1\, Y => N_696); - - \data_temp_RNO_0[79]\ : MX2C - port map(A => \data_temp[111]_net_1\, B => - \data_selected[111]\, S => \state[4]_net_1\, Y => N_680); - - \data_temp_RNO_0[71]\ : MX2C - port map(A => \data_temp[103]_net_1\, B => - \data_selected[103]\, S => \state[4]_net_1\, Y => N_672); - - \data_valid_ack_RNO[3]\ : INV - port map(A => N_860, Y => N_860_i); - - \data_temp_RNO_3[52]\ : MX2C - port map(A => data_f0_out(84), B => data_f1_out(84), S => - \data_valid_and_ready[0]_net_1\, Y => N_838); - - \data_temp[98]\ : DFN1C0 - port map(D => \data_temp_5[98]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[98]_net_1\); - - \data_temp_RNO[54]\ : NOR2A - port map(A => N_863_1, B => N_655, Y => \data_temp_5[54]\); - - \data_valid_and_ready_1[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready_1[0]_net_1\); - - \data_temp_RNO_3[62]\ : MX2C - port map(A => data_f0_out(94), B => data_f1_out(94), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_820); - - \data_temp_RNO_1[37]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_762, - Y => N_1654); - - \data_temp_RNO_3[82]\ : MX2C - port map(A => data_f0_out(114), B => data_f1_out(114), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_812); - - \data_temp_RNO_1[64]\ : MX2C - port map(A => N_747, B => N_822, S => N_1580, Y => - \data_selected[96]\); - - \data_temp_RNO[84]\ : NOR2A - port map(A => N_863_2, B => N_685, Y => \data_temp_5[84]\); - - \data_temp_RNO_2[80]\ : MX2C - port map(A => data_f2_out(112), B => data_f3_out(112), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1733); - - \data_temp_RNO_0[94]\ : MX2C - port map(A => \data_temp[126]_net_1\, B => - \data_selected[126]\, S => \state[4]_net_1\, Y => N_695); - - \data_temp_RNO_0[127]\ : MX2C - port map(A => \data_temp[127]_net_1\, B => - \data_selected[159]\, S => \state[4]_net_1\, Y => N_728); - - \data_temp[83]\ : DFN1C0 - port map(D => \data_temp_5[83]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[83]_net_1\); - - \data_temp_RNO_3[116]\ : MX2C - port map(A => data_f0_out(148), B => data_f1_out(148), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_776); - - \data[4]\ : DFN1C0 - port map(D => \data_5[4]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(4)); - - \data[11]\ : DFN1C0 - port map(D => \data_5[11]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(11)); - - \data_temp_RNO[124]\ : NOR3B - port map(A => N_863_0, B => N_915, C => - \data_temp_5_i_0[124]\, Y => N_245); - - \data_valid_and_ready_3[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready_3[0]_net_1\); - - \data_RNO[21]\ : NOR2A - port map(A => \data_temp[21]_net_1\, B => \state[4]_net_1\, - Y => \data_5[21]\); - - \data_temp_RNO_4[39]\ : MX2 - port map(A => data_f2_out(71), B => data_f3_out(71), S => - \data_valid_and_ready[2]_net_1\, Y => N_764); - - \data_temp[97]\ : DFN1C0 - port map(D => \data_temp_5[97]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[97]_net_1\); - - \state_RNIKK3V21_4[4]\ : OR2A - port map(A => \state[4]_net_1\, B => N_1306, Y => - state_0_sqmuxa_i); - - \data_RNO[22]\ : NOR2A - port map(A => \data_temp[22]_net_1\, B => \state[4]_net_1\, - Y => \data_5[22]\); - - \data_temp_RNO_2[60]\ : MX2C - port map(A => data_f2_out(92), B => data_f3_out(92), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_743); - - \data_temp_RNO[30]\ : NOR2A - port map(A => \data_temp[62]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[30]\); - - \data_temp_RNO[25]\ : NOR2A - port map(A => \data_temp[57]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[25]\); - - \data_temp_RNO[121]\ : NOR2A - port map(A => N_863, B => N_722, Y => \data_temp_5[121]\); - - \time_en_temp[3]\ : DFN1E0C0 - port map(D => N_916, CLK => HCLK_c, CLR => HRESETn_c, E => - state_0_sqmuxa_i, Q => \time_en_temp[3]_net_1\); - - \data_temp_RNO_3[75]\ : MX2C - port map(A => data_f0_out(107), B => data_f1_out(107), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_819); - - \data_temp_RNO_3[124]\ : MX2 - port map(A => data_f2_out(156), B => data_f3_out(156), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1693); - - \data_temp_RNO_0[57]\ : MX2C - port map(A => \data_temp[89]_net_1\, B => - \data_selected[89]\, S => \state[4]_net_1\, Y => N_658); - - \data_temp[39]\ : DFN1C0 - port map(D => N_231, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[39]_net_1\); - - \data_temp_RNO_3[47]\ : MX2C - port map(A => data_f0_out(79), B => data_f1_out(79), S => - \data_valid_and_ready[0]_net_1\, Y => N_847); - - \data_temp_RNO_1[113]\ : MX2C - port map(A => N_1710, B => N_773, S => N_1580_2, Y => - \data_selected[145]\); - - \data_temp_RNO_2[82]\ : MX2C - port map(A => data_f2_out(114), B => data_f3_out(114), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1735); - - \data_temp_RNO_0[75]\ : MX2C - port map(A => \data_temp[107]_net_1\, B => - \data_selected[107]\, S => \state[4]_net_1\, Y => N_676); - - \data_temp_RNO_3[32]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[64]_net_1\, - Y => N_864); - - \data_temp_RNO_3[74]\ : MX2C - port map(A => data_f0_out(106), B => data_f1_out(106), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_818); - - \data_temp_RNO_2[100]\ : MX2C - port map(A => data_f2_out(132), B => data_f3_out(132), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1711); - - \data_temp_RNO_2[112]\ : MX2C - port map(A => data_f2_out(144), B => data_f3_out(144), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1709); - - \data_temp_RNO_0[48]\ : MX2C - port map(A => \data_temp[80]_net_1\, B => - \data_selected[80]\, S => \state[4]_net_1\, Y => N_649); - - \data_temp_RNO_2[115]\ : MX2C - port map(A => data_f2_out(147), B => data_f3_out(147), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1698); - - \data_temp_RNO[104]\ : NOR2A - port map(A => N_863_2, B => N_705, Y => \data_temp_5[104]\); - - \data_temp_RNO_2[38]\ : MX2 - port map(A => data_f0_out(70), B => data_f1_out(70), S => - \data_valid_and_ready[0]_net_1\, Y => N_852); - - \data_temp[122]\ : DFN1C0 - port map(D => \data_temp_5[122]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[122]_net_1\); - - \data_temp[8]\ : DFN1C0 - port map(D => \data_temp_5[8]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[8]_net_1\); - - \data[26]\ : DFN1C0 - port map(D => \data_5[26]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(26)); - - \data_temp_RNO_0[74]\ : MX2C - port map(A => \data_temp[106]_net_1\, B => - \data_selected[106]\, S => \state[4]_net_1\, Y => N_675); - - \data_temp_RNO_1[122]\ : MX2C - port map(A => N_1691, B => N_1679, S => N_1580, Y => - \data_selected[154]\); - - \data_temp_RNO_0[89]\ : MX2C - port map(A => \data_temp[121]_net_1\, B => - \data_selected[121]\, S => \state[4]_net_1\, Y => N_690); - - \data_temp_RNO_0[81]\ : MX2C - port map(A => \data_temp[113]_net_1\, B => - \data_selected[113]\, S => \state[4]_net_1\, Y => N_682); - - \data_temp_RNO[101]\ : NOR2A - port map(A => N_863, B => N_702, Y => \data_temp_5[101]\); - - \data_temp_RNO_2[99]\ : MX2C - port map(A => data_f2_out(131), B => data_f3_out(131), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1724); - - \data_temp_RNO_2[91]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1730, - Y => N_908); - - \data_temp_RNO_2[62]\ : MX2C - port map(A => data_f2_out(94), B => data_f3_out(94), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_745); - - \data_temp_RNO_3[119]\ : MX2C - port map(A => data_f0_out(151), B => data_f1_out(151), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1676); - - \data_temp_RNO[40]\ : NOR3A - port map(A => N_863_0, B => \data_temp_5_i_0[40]\, C => - N_1663, Y => N_233); - - \data_temp_RNO[99]\ : NOR2A - port map(A => N_863, B => N_700, Y => \data_temp_5[99]\); - - \data_temp_RNO_4[35]\ : MX2 - port map(A => data_f2_out(67), B => data_f3_out(67), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1688); - - \data[12]\ : DFN1C0 - port map(D => \data_5[12]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(12)); - - \data_temp_RNO_1[107]\ : MX2C - port map(A => N_1704, B => N_781, S => N_1580_2, Y => - \data_selected[139]\); - - \data_temp[104]\ : DFN1C0 - port map(D => \data_temp_5[104]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[104]_net_1\); - - \data_temp_RNO_3[120]\ : MX2C - port map(A => data_f0_out(152), B => data_f1_out(152), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1677); - - \data_temp_RNO_1[47]\ : MX2C - port map(A => N_758, B => N_847, S => N_1580_1, Y => - \data_selected[79]\); - - \data_temp_RNO_4[34]\ : MX2 - port map(A => data_f2_out(66), B => data_f3_out(66), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1687); - - \data_temp_RNO_0[69]\ : MX2C - port map(A => \data_temp[101]_net_1\, B => - \data_selected[101]\, S => \state[4]_net_1\, Y => N_670); - - \data_temp_RNO_0[61]\ : MX2C - port map(A => \data_temp[93]_net_1\, B => - \data_selected[93]\, S => \state[4]_net_1\, Y => N_662); - - \data_temp_RNO[96]\ : NOR2A - port map(A => N_863, B => N_697, Y => \data_temp_5[96]\); - - \data_temp[107]\ : DFN1C0 - port map(D => \data_temp_5[107]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[107]_net_1\); - - \data_temp[80]\ : DFN1C0 - port map(D => \data_temp_5[80]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[80]_net_1\); - - \data_temp_RNO_2[116]\ : MX2C - port map(A => data_f2_out(148), B => data_f3_out(148), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1699); - - \data_temp_RNO[18]\ : NOR2A - port map(A => \data_temp[50]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[18]\); - - \data_temp[95]\ : DFN1C0 - port map(D => \data_temp_5[95]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[95]_net_1\); - - \data_temp[63]\ : DFN1C0 - port map(D => \data_temp_5[63]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[63]_net_1\); - - \state_RNI8220I[4]\ : OR2B - port map(A => \state[4]_net_1\, B => N_1580_1, Y => N_912_i); - - \data_temp_RNO[123]\ : NOR3B - port map(A => N_863_0, B => N_913, C => - \data_temp_5_i_0[123]\, Y => N_251); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_temp_RNO_0[85]\ : MX2C - port map(A => \data_temp[117]_net_1\, B => - \data_selected[117]\, S => \state[4]_net_1\, Y => N_686); - - \data_temp[121]\ : DFN1C0 - port map(D => \data_temp_5[121]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[121]_net_1\); - - \data_temp[79]\ : DFN1C0 - port map(D => \data_temp_5[79]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[79]_net_1\); - - \data_temp_RNO_3[107]\ : MX2C - port map(A => data_f0_out(139), B => data_f1_out(139), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_781); - - \data[30]\ : DFN1C0 - port map(D => \data_5[30]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(30)); - - \data_temp_RNO_0[122]\ : MX2C - port map(A => \data_temp[122]_net_1\, B => - \data_selected[154]\, S => \state[4]_net_1\, Y => N_723); - - \data_temp_RNO_2[95]\ : MX2C - port map(A => data_f2_out(127), B => data_f3_out(127), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1720); - - \data_temp_RNO_0[100]\ : MX2C - port map(A => \data_temp[100]_net_1\, B => - \data_selected[132]\, S => \state[4]_net_1\, Y => N_701); - - \data_temp_RNO[13]\ : NOR2A - port map(A => \data_temp[45]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[13]\); - - \data_valid_and_ready[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready[0]_net_1\); - - \data_temp_RNO_3[97]\ : MX2C - port map(A => data_f0_out(129), B => data_f1_out(129), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_785); - - \data[19]\ : DFN1C0 - port map(D => \data_5[19]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(19)); - - \data_temp_RNO_0[84]\ : MX2C - port map(A => \data_temp[116]_net_1\, B => - \data_selected[116]\, S => \state[4]_net_1\, Y => N_685); - - \time_wen[2]\ : DFN1E0P0 - port map(D => N_859, CLK => HCLK_c, PRE => HRESETn_c, E => - N_928, Q => time_wen(2)); - - \data_temp[118]\ : DFN1C0 - port map(D => \data_temp_5[118]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[118]_net_1\); - - \data_temp_RNO[109]\ : NOR2A - port map(A => N_863, B => N_710, Y => \data_temp_5[109]\); - - \data_temp_RNO_2[94]\ : MX2C - port map(A => data_f2_out(126), B => data_f3_out(126), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1719); - - \data_temp_RNO_1[79]\ : MX2C - port map(A => N_1732, B => N_809, S => N_1580_2, Y => - \data_selected[111]\); - - \data_temp_RNO_1[71]\ : MX2C - port map(A => N_740, B => N_815, S => N_1580_3, Y => - \data_selected[103]\); - - \data_temp[105]\ : DFN1C0 - port map(D => \data_temp_5[105]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[105]_net_1\); - - \data_temp[42]\ : DFN1C0 - port map(D => N_237, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[42]_net_1\); - - \data_temp_RNO_0[65]\ : MX2C - port map(A => \data_temp[97]_net_1\, B => - \data_selected[97]\, S => \state[4]_net_1\, Y => N_666); - - \data_temp_RNO[103]\ : NOR2A - port map(A => N_863_2, B => N_704, Y => \data_temp_5[103]\); - - \data_temp_RNO_3[102]\ : MX2C - port map(A => data_f0_out(134), B => data_f1_out(134), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_790); - - \data_temp_RNO_0[114]\ : MX2C - port map(A => \data_temp[114]_net_1\, B => - \data_selected[146]\, S => \state[4]_net_1\, Y => N_715); - - \data[15]\ : DFN1C0 - port map(D => \data_5[15]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(15)); - - \data_temp_RNO_0[111]\ : MX2C - port map(A => \data_temp[111]_net_1\, B => - \data_selected[143]\, S => \state[4]_net_1\, Y => N_712); - - \data_RNO[26]\ : NOR2A - port map(A => \data_temp[26]_net_1\, B => \state[4]_net_1\, - Y => \data_5[26]\); - - \data_temp[1]\ : DFN1C0 - port map(D => \data_temp_5[1]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[1]_net_1\); - - \data_temp_RNO_1[66]\ : MX2C - port map(A => N_735, B => N_824, S => N_1580, Y => - \data_selected[98]\); - - \data_temp_RNO_1[89]\ : MX2C - port map(A => N_1728, B => N_805, S => N_1580, Y => - \data_selected[121]\); - - \data_temp_RNO_1[81]\ : MX2C - port map(A => N_1734, B => N_811, S => N_1580_2, Y => - \data_selected[113]\); - - \data_temp_RNO_0[64]\ : MX2C - port map(A => \data_temp[96]_net_1\, B => - \data_selected[96]\, S => \state[4]_net_1\, Y => N_665); - - \data_temp_RNO_0[96]\ : MX2C - port map(A => \data_temp[96]_net_1\, B => - \data_selected[128]\, S => \state[4]_net_1\, Y => N_697); - - \data_temp_RNO_1[58]\ : MX2C - port map(A => N_741, B => N_830, S => N_1580_2, Y => - \data_selected[90]\); - - \data_temp_RNO_1[99]\ : MX2C - port map(A => N_1724, B => N_787, S => N_1580, Y => - \data_selected[131]\); - - \data_temp_RNO_1[91]\ : MX2 - port map(A => data_f0_out(123), B => data_f1_out(123), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_793); - - \data_temp_RNO_1[63]\ : MX2C - port map(A => N_746, B => N_821, S => N_1580_2, Y => - \data_selected[95]\); - - \data_temp_RNO_3[106]\ : MX2C - port map(A => data_f0_out(138), B => data_f1_out(138), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_780); - - \data_temp_RNO[28]\ : NOR2A - port map(A => \data_temp[60]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[28]\); - - \data_temp_RNO_1[32]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1685, - Y => N_865); - - \data_temp[41]\ : DFN1C0 - port map(D => N_235, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[41]_net_1\); - - \data_temp_RNO_2[78]\ : MX2C - port map(A => data_f2_out(110), B => data_f3_out(110), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_733); - - \data_temp_RNO_0[93]\ : AO1D - port map(A => N_912_i, B => N_795, C => N_902, Y => - \data_temp_5_i_0[93]\); - - \data_temp_RNO_0[50]\ : MX2C - port map(A => \data_temp[82]_net_1\, B => - \data_selected[82]\, S => \state[4]_net_1\, Y => N_651); - - \data_temp_RNO[97]\ : NOR2A - port map(A => N_863, B => N_698, Y => \data_temp_5[97]\); - - \data_temp_RNO_0[47]\ : MX2C - port map(A => \data_temp[79]_net_1\, B => - \data_selected[79]\, S => \state[4]_net_1\, Y => N_648); - - \data_RNO[14]\ : NOR2A - port map(A => \data_temp[14]_net_1\, B => \state[4]_net_1\, - Y => \data_5[14]\); - - \data_temp_RNO_3[40]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[72]_net_1\, - Y => N_1662); - - \data_temp[23]\ : DFN1C0 - port map(D => \data_temp_5[23]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[23]_net_1\); - - \data_temp_RNO_3[121]\ : MX2C - port map(A => data_f0_out(153), B => data_f1_out(153), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1678); - - \data_temp_RNO_2[37]\ : MX2 - port map(A => data_f0_out(69), B => data_f1_out(69), S => - \data_valid_and_ready[0]_net_1\, Y => N_851); - - \data_temp[19]\ : DFN1C0 - port map(D => \data_temp_5[19]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[19]_net_1\); - - \data_temp_RNO_2[48]\ : MX2C - port map(A => data_f2_out(80), B => data_f3_out(80), S => - \data_valid_and_ready[2]_net_1\, Y => N_759); - - \data_temp_RNO_1[75]\ : MX2C - port map(A => N_730, B => N_819, S => N_1580_2, Y => - \data_selected[107]\); - - \data_valid_and_ready_0[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0(0), Y => - \data_valid_and_ready_0[0]_net_1\); - - \data_temp_RNO[23]\ : NOR2A - port map(A => \data_temp[55]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[23]\); - - \data_RNO[10]\ : NOR2A - port map(A => \data_temp[10]_net_1\, B => \state[4]_net_1\, - Y => \data_5[10]\); - - \data_temp[60]\ : DFN1C0 - port map(D => \data_temp_5[60]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[60]_net_1\); - - \data_temp[53]\ : DFN1C0 - port map(D => \data_temp_5[53]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[53]_net_1\); - - \data_valid_and_ready_3[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready_3[2]_net_1\); - - \data_temp_RNO_3[76]\ : MX2C - port map(A => data_f0_out(108), B => data_f1_out(108), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_806); - - \data_temp_RNO_1[74]\ : MX2C - port map(A => N_729, B => N_818, S => N_1580_2, Y => - \data_selected[106]\); - - \data_temp_RNO_1[85]\ : MX2C - port map(A => N_1738, B => N_801, S => N_1580_3, Y => - \data_selected[117]\); - - \data_wen_RNO[3]\ : OR2 - port map(A => \time_en_temp[3]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[3]\); - - \data_temp_RNO_1[103]\ : MX2C - port map(A => N_1714, B => N_791, S => N_1580_3, Y => - \data_selected[135]\); - - \data_RNO[8]\ : NOR2A - port map(A => \data_temp[8]_net_1\, B => \state[4]_net_1\, - Y => \data_5[8]\); - - \data_temp_RNO_0[113]\ : MX2C - port map(A => \data_temp[113]_net_1\, B => - \data_selected[145]\, S => \state[4]_net_1\, Y => N_714); - - \data_temp_RNO_0[76]\ : MX2C - port map(A => \data_temp[108]_net_1\, B => - \data_selected[108]\, S => \state[4]_net_1\, Y => N_677); - - \data_temp_RNO[69]\ : NOR2A - port map(A => N_863, B => N_670, Y => \data_temp_5[69]\); - - \data_temp_RNO_2[102]\ : MX2C - port map(A => data_f2_out(134), B => data_f3_out(134), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1713); - - \data_temp_RNO_0[52]\ : MX2C - port map(A => \data_temp[84]_net_1\, B => - \data_selected[84]\, S => \state[4]_net_1\, Y => N_653); - - \data_temp_RNO_1[125]\ : MX2 - port map(A => data_f0_out(157), B => data_f1_out(157), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1682); - - \data_RNO[9]\ : NOR2A - port map(A => \data_temp[9]_net_1\, B => \state[4]_net_1\, - Y => \data_5[9]\); - - \data_temp_RNO_2[105]\ : MX2C - port map(A => data_f2_out(137), B => data_f3_out(137), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1716); - - \data_temp_RNO_3[42]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[74]_net_1\, - Y => N_1668); - - \data_temp_RNO_1[111]\ : MX2C - port map(A => N_1708, B => N_771, S => N_1580_2, Y => - \data_selected[143]\); - - \data_valid_ack[1]\ : DFN1E0C0 - port map(D => N_857, CLK => HCLK_c, CLR => HRESETn_c, E => - N_929, Q => valid_ack(1)); - - \data_temp_RNO_3[73]\ : MX2C - port map(A => data_f0_out(105), B => data_f1_out(105), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_817); - - \data_temp_RNO_1[84]\ : MX2C - port map(A => N_1737, B => N_800, S => N_1580_3, Y => - \data_selected[116]\); - - \data_temp_RNO_1[95]\ : MX2C - port map(A => N_1720, B => N_797, S => N_1580_1, Y => - \data_selected[127]\); - - \data_temp_RNO_1[40]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_765, - Y => N_1663); - - \data_temp[48]\ : DFN1C0 - port map(D => \data_temp_5[48]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[48]_net_1\); - - \data_temp_RNO[50]\ : NOR2A - port map(A => N_863_1, B => N_651, Y => \data_temp_5[50]\); - - \data_temp[86]\ : DFN1C0 - port map(D => \data_temp_5[86]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[86]_net_1\); - - \state_RNI8220I_0[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_917, Y => N_857); - - \data_temp_RNO[3]\ : NOR2A - port map(A => \data_temp[35]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[3]\); - - \data_temp_RNO_3[59]\ : MX2C - port map(A => data_f0_out(91), B => data_f1_out(91), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_831); - - \data_temp_RNO_3[51]\ : MX2C - port map(A => data_f0_out(83), B => data_f1_out(83), S => - \data_valid_and_ready[0]_net_1\, Y => N_837); - - \data_temp_RNO[80]\ : NOR2A - port map(A => N_863_1, B => N_681, Y => \data_temp_5[80]\); - - \data_temp_RNO_3[125]\ : MX2 - port map(A => data_f2_out(157), B => data_f3_out(157), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1694); - - \data_temp_RNO_3[69]\ : MX2C - port map(A => data_f0_out(101), B => data_f1_out(101), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_813); - - \data_temp_RNO_3[61]\ : MX2C - port map(A => data_f0_out(93), B => data_f1_out(93), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_833); - - \data_temp_RNO_0[73]\ : MX2C - port map(A => \data_temp[105]_net_1\, B => - \data_selected[105]\, S => \state[4]_net_1\, Y => N_674); - - \data_RNO[15]\ : NOR2A - port map(A => \data_temp[15]_net_1\, B => \state[4]_net_1\, - Y => \data_5[15]\); - - \data_temp_RNO_3[89]\ : MX2C - port map(A => data_f0_out(121), B => data_f1_out(121), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_805); - - \data_temp_RNO_3[81]\ : MX2C - port map(A => data_f0_out(113), B => data_f1_out(113), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_811); - - \data_temp_RNO[66]\ : NOR2A - port map(A => N_863, B => N_667, Y => \data_temp_5[66]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_temp_RNO_3[109]\ : MX2C - port map(A => data_f0_out(141), B => data_f1_out(141), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_783); - - \data_temp[116]\ : DFN1C0 - port map(D => \data_temp_5[116]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[116]_net_1\); - - \data_temp_RNO_1[94]\ : MX2C - port map(A => N_1719, B => N_796, S => N_1580_1, Y => - \data_selected[126]\); - - \data_temp_RNO[11]\ : NOR2A - port map(A => \data_temp[43]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[11]\); - - \data_temp_RNO_1[126]\ : MX2C - port map(A => N_1695, B => N_1683, S => N_1580_1, Y => - \data_selected[158]\); - - \data_temp_RNO_4[36]\ : MX2 - port map(A => data_f2_out(68), B => data_f3_out(68), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1689); - - \data_RNO[29]\ : NOR2A - port map(A => \data_temp[29]_net_1\, B => \state[4]_net_1\, - Y => \data_5[29]\); - - \state[3]\ : DFN1C0 - port map(D => state_0_sqmuxa_i_i, CLK => HCLK_c, CLR => - HRESETn_c, Q => \state[3]_net_1\); - - \data_temp_RNO[12]\ : NOR2A - port map(A => \data_temp[44]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[12]\); - - \data_temp[47]\ : DFN1C0 - port map(D => \data_temp_5[47]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[47]_net_1\); - - \data_valid_ack_RNO[2]\ : INV - port map(A => N_859, Y => N_859_i); - - \data_RNO[30]\ : NOR2A - port map(A => \data_temp[30]_net_1\, B => \state[4]_net_1\, - Y => \data_5[30]\); - - \data_temp_RNO_4[33]\ : MX2 - port map(A => data_f2_out(65), B => data_f3_out(65), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1686); - - \data_temp_RNO_3[90]\ : MX2C - port map(A => data_f0_out(122), B => data_f1_out(122), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_792); - - \data_temp_RNO_1[42]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_767, - Y => N_1669); - - \data_temp_RNO_2[121]\ : MX2C - port map(A => data_f2_out(153), B => data_f3_out(153), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1690); - - \data_temp[33]\ : DFN1C0 - port map(D => N_219, CLK => HCLK_c, CLR => HRESETn_c, Q => - \data_temp[33]_net_1\); - - \data_temp[20]\ : DFN1C0 - port map(D => \data_temp_5[20]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[20]_net_1\); - - \data_temp_RNO_2[106]\ : MX2C - port map(A => data_f2_out(138), B => data_f3_out(138), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1717); - - \data_temp_RNIERBC[125]\ : OR2 - port map(A => \state[4]_net_1\, B => \data_temp[125]_net_1\, - Y => N_914); - - \data[24]\ : DFN1C0 - port map(D => \data_5[24]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(24)); - - \data_temp_RNO[95]\ : NOR2A - port map(A => N_863_0, B => N_696, Y => \data_temp_5[95]\); - - \data_temp_RNO[14]\ : NOR2A - port map(A => \data_temp[46]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[14]\); - - \data_temp_RNO_2[89]\ : MX2C - port map(A => data_f2_out(121), B => data_f3_out(121), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1728); - - \data_temp_RNO_2[81]\ : MX2C - port map(A => data_f2_out(113), B => data_f3_out(113), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1734); - - \data_temp_RNO_3[39]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[71]_net_1\, - Y => N_1659); - - \data_temp[50]\ : DFN1C0 - port map(D => \data_temp_5[50]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[50]_net_1\); - - \data_temp_RNO_3[55]\ : MX2C - port map(A => data_f0_out(87), B => data_f1_out(87), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_827); - - \data_temp_RNO_0[86]\ : MX2C - port map(A => \data_temp[118]_net_1\, B => - \data_selected[118]\, S => \state[4]_net_1\, Y => N_687); - - \data[1]\ : DFN1C0 - port map(D => \data_5[1]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(1)); - - \data_valid_and_ready_2[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready_2[2]_net_1\); - - \data_temp_RNO_3[65]\ : MX2C - port map(A => data_f0_out(97), B => data_f1_out(97), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_823); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_valid_and_ready[1]\ : NOR2 - port map(A => valid_out_i(1), B => ready_i_0(1), Y => - \data_valid_and_ready[1]_net_1\); - - \data_temp_RNO_3[85]\ : MX2C - port map(A => data_f0_out(117), B => data_f1_out(117), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_801); - - \state_RNO[4]\ : OA1B - port map(A => N_1306, B => \state[0]_net_1\, C => - \state_ns_i_i_a2_1[0]\, Y => N_861); - - \data_temp_RNO_2[96]\ : MX2C - port map(A => data_f2_out(128), B => data_f3_out(128), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1721); - - \data[9]\ : DFN1C0 - port map(D => \data_5[9]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(9)); - - \data_temp_RNO_3[123]\ : MX2 - port map(A => data_f2_out(155), B => data_f3_out(155), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1692); - - \data_valid_and_ready[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0(2), Y => - \data_valid_and_ready[2]_net_1\); - - \data_temp_RNO_3[54]\ : MX2C - port map(A => data_f0_out(86), B => data_f1_out(86), S => - \data_valid_and_ready[0]_net_1\, Y => N_840); - - \data_temp_RNO_1[124]\ : MX2 - port map(A => data_f0_out(156), B => data_f1_out(156), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1681); - - \data_temp_RNO_3[92]\ : MX2 - port map(A => data_f2_out(124), B => data_f3_out(124), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1731); - - \data_temp_RNO_3[64]\ : MX2C - port map(A => data_f0_out(96), B => data_f1_out(96), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_822); - - \data_temp_RNO_1[57]\ : MX2C - port map(A => N_754, B => N_829, S => N_1580_1, Y => - \data_selected[89]\); - - \data_temp_RNO_2[69]\ : MX2C - port map(A => data_f2_out(101), B => data_f3_out(101), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_738); - - \data_temp_RNO_2[61]\ : MX2C - port map(A => data_f2_out(93), B => data_f3_out(93), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_744); - - \data[17]\ : DFN1C0 - port map(D => \data_5[17]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(17)); - - \data_temp_RNO_3[84]\ : MX2C - port map(A => data_f0_out(116), B => data_f1_out(116), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_800); - - \data_temp_RNO_0[83]\ : MX2C - port map(A => \data_temp[115]_net_1\, B => - \data_selected[115]\, S => \state[4]_net_1\, Y => N_684); - - \data_temp_RNO_2[58]\ : MX2C - port map(A => data_f2_out(90), B => data_f3_out(90), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_741); - - \data[20]\ : DFN1C0 - port map(D => \data_5[20]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => wdata(20)); - - \data_temp_RNO_2[93]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_0, C => N_1718, - Y => N_902); - - \data_RNO[6]\ : NOR2A - port map(A => \data_temp[6]_net_1\, B => \state[4]_net_1\, - Y => \data_5[6]\); - - \data_RNO[3]\ : NOR2A - port map(A => \data_temp[3]_net_1\, B => \state[4]_net_1\, - Y => \data_5[3]\); - - \data_temp_RNO_2[77]\ : MX2C - port map(A => data_f2_out(109), B => data_f3_out(109), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_732); - - \data_temp_RNO_0[66]\ : MX2C - port map(A => \data_temp[98]_net_1\, B => - \data_selected[98]\, S => \state[4]_net_1\, Y => N_667); - - \data_temp_RNO[21]\ : NOR2A - port map(A => \data_temp[53]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[21]\); - - \data_wen[0]\ : DFN1E0P0 - port map(D => \data_wen_3[0]\, CLK => HCLK_c, PRE => - HRESETn_c, E => N_928, Q => data_wen(0)); - - \data_temp_RNO_0[104]\ : MX2C - port map(A => \data_temp[104]_net_1\, B => - \data_selected[136]\, S => \state[4]_net_1\, Y => N_705); - - \data_temp_RNO_4[40]\ : MX2 - port map(A => data_f2_out(72), B => data_f3_out(72), S => - \data_valid_and_ready[2]_net_1\, Y => N_765); - - \data_temp_RNO_2[47]\ : MX2C - port map(A => data_f2_out(79), B => data_f3_out(79), S => - \data_valid_and_ready[2]_net_1\, Y => N_758); - - \data_temp_RNO_0[101]\ : MX2C - port map(A => \data_temp[101]_net_1\, B => - \data_selected[133]\, S => \state[4]_net_1\, Y => N_702); - - \data_temp_RNO_0[40]\ : AO1D - port map(A => N_912_i, B => N_854, C => N_1662, Y => - \data_temp_5_i_0[40]\); - - \data_temp_RNO_0[38]\ : AO1D - port map(A => N_912_i, B => N_852, C => N_1656, Y => - \data_temp_5_i_0[38]\); - - \state_RNIIO749[4]\ : OR2A - port map(A => \state[4]_net_1\, B => - \data_valid_and_ready_0[0]_net_1\, Y => \time_wen_3[0]\); - - \data_temp_RNO[67]\ : NOR2A - port map(A => N_863, B => N_668, Y => \data_temp_5[67]\); - - \data_temp_RNO[22]\ : NOR2A - port map(A => \data_temp[54]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[22]\); - - \data_temp_RNO[79]\ : NOR2A - port map(A => N_863_2, B => N_680, Y => \data_temp_5[79]\); - - \data_temp[66]\ : DFN1C0 - port map(D => \data_temp_5[66]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[66]_net_1\); - - \data_temp_RNO_2[85]\ : MX2C - port map(A => data_f2_out(117), B => data_f3_out(117), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1738); - - \data_temp_RNO_2[123]\ : NOR3A - port map(A => \state[4]_net_1\, B => N_1580_1, C => N_1692, - Y => N_910); - - \data_temp_RNO_0[63]\ : MX2C - port map(A => \data_temp[95]_net_1\, B => - \data_selected[95]\, S => \state[4]_net_1\, Y => N_664); - - \data_temp_RNO_3[35]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[67]_net_1\, - Y => N_873); - - \data_temp[84]\ : DFN1C0 - port map(D => \data_temp_5[84]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[84]_net_1\); - - \data_temp[45]\ : DFN1C0 - port map(D => \data_temp_5[45]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[45]_net_1\); - - \data_valid_ack[2]\ : DFN1E0C0 - port map(D => N_859_i, CLK => HCLK_c, CLR => HRESETn_c, E - => N_929, Q => valid_ack(2)); - - \data_temp[73]\ : DFN1C0 - port map(D => \data_temp_5[73]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[73]_net_1\); - - \data_temp_RNO_3[118]\ : MX2C - port map(A => data_f0_out(150), B => data_f1_out(150), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1675); - - \data_temp_RNO_2[84]\ : MX2C - port map(A => data_f2_out(116), B => data_f3_out(116), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1737); - - \data_temp_RNO[76]\ : NOR2A - port map(A => N_863_1, B => N_677, Y => \data_temp_5[76]\); - - \data_temp_RNO_3[34]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[66]_net_1\, - Y => N_870); - - \data_temp[113]\ : DFN1C0 - port map(D => \data_temp_5[113]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[113]_net_1\); - - \data_temp_RNO[24]\ : NOR2A - port map(A => \data_temp[56]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[24]\); - - \data_temp[30]\ : DFN1C0 - port map(D => \data_temp_5[30]\, CLK => HCLK_c, CLR => - HRESETn_c, Q => \data_temp[30]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform is - - port( status_full_ack : in std_logic_vector(3 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hsize_c : out std_logic_vector(1 downto 0); - AHB_Master_In_c_5 : in std_logic; - AHB_Master_In_c_4 : in std_logic; - AHB_Master_In_c_0 : in std_logic; - AHB_Master_In_c_3 : in std_logic; - haddr_c : out std_logic_vector(31 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - status_full : out std_logic_vector(3 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - hwdata_c : out std_logic_vector(31 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - sample_f3_wdata : in std_logic_vector(95 downto 0); - sample_f2_wdata : in std_logic_vector(95 downto 0); - sample_f1_15 : in std_logic; - sample_f1_47 : in std_logic; - sample_f1_14 : in std_logic; - sample_f1_46 : in std_logic; - sample_f1_13 : in std_logic; - sample_f1_45 : in std_logic; - sample_f1_12 : in std_logic; - sample_f1_44 : in std_logic; - sample_f1_60 : in std_logic; - sample_f1_59 : in std_logic; - sample_f1_58 : in std_logic; - sample_f1_57 : in std_logic; - sample_f1_56 : in std_logic; - sample_f1_55 : in std_logic; - sample_f1_54 : in std_logic; - sample_f1_53 : in std_logic; - sample_f1_52 : in std_logic; - sample_f1_51 : in std_logic; - sample_f1_50 : in std_logic; - sample_f1_49 : in std_logic; - sample_f1_48 : in std_logic; - sample_f1_4 : in std_logic; - sample_f1_36 : in std_logic; - sample_f1_3 : in std_logic; - sample_f1_35 : in std_logic; - sample_f1_2 : in std_logic; - sample_f1_34 : in std_logic; - sample_f1_1 : in std_logic; - sample_f1_33 : in std_logic; - sample_f1_0 : in std_logic; - sample_f1_32 : in std_logic; - sample_f1_63 : in std_logic; - sample_f1_62 : in std_logic; - sample_f1_61 : in std_logic; - sample_f1_11 : in std_logic; - sample_f1_43 : in std_logic; - sample_f1_10 : in std_logic; - sample_f1_42 : in std_logic; - sample_f1_9 : in std_logic; - sample_f1_41 : in std_logic; - sample_f1_8 : in std_logic; - sample_f1_40 : in std_logic; - sample_f1_7 : in std_logic; - sample_f1_39 : in std_logic; - sample_f1_6 : in std_logic; - sample_f1_38 : in std_logic; - sample_f1_5 : in std_logic; - sample_f1_37 : in std_logic; - sample_f1_wdata_0 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_95 : in std_logic; - sample_f0_15 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_0 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_63 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_37 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_95 : in std_logic; - delta_f2_f1 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - nb_snapshot_param : in std_logic_vector(10 downto 0); - hwrite_c : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - N_43 : out std_logic; - lpp_waveform_GND : in std_logic; - lpp_waveform_VCC : in std_logic; - sample_f3_val : in std_logic; - enable_f3 : in std_logic; - burst_f2 : in std_logic; - enable_f2 : in std_logic; - sample_f1_val_0 : in std_logic; - burst_f1 : in std_logic; - enable_f1 : in std_logic; - data_shaping_R1_0 : in std_logic; - data_shaping_R1 : in std_logic; - burst_f0 : in std_logic; - data_shaping_R0_0 : in std_logic; - data_shaping_R0 : in std_logic; - enable_f0 : in std_logic; - coarse_time_0_c : in std_logic; - sample_f2_val : in std_logic; - sample_f0_val_0 : in std_logic; - HCLK_c : in std_logic; - HRESETn_c : in std_logic - ); - -end lpp_waveform; - -architecture DEF_ARCH of lpp_waveform is - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 - port( sample_f1_wdata_95 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - data_f1_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0) := (others => 'U'); - sample_f1_37 : in std_logic := 'U'; - sample_f1_5 : in std_logic := 'U'; - sample_f1_38 : in std_logic := 'U'; - sample_f1_6 : in std_logic := 'U'; - sample_f1_39 : in std_logic := 'U'; - sample_f1_7 : in std_logic := 'U'; - sample_f1_40 : in std_logic := 'U'; - sample_f1_8 : in std_logic := 'U'; - sample_f1_41 : in std_logic := 'U'; - sample_f1_9 : in std_logic := 'U'; - sample_f1_42 : in std_logic := 'U'; - sample_f1_10 : in std_logic := 'U'; - sample_f1_43 : in std_logic := 'U'; - sample_f1_11 : in std_logic := 'U'; - sample_f1_61 : in std_logic := 'U'; - sample_f1_62 : in std_logic := 'U'; - sample_f1_63 : in std_logic := 'U'; - sample_f1_32 : in std_logic := 'U'; - sample_f1_0 : in std_logic := 'U'; - sample_f1_33 : in std_logic := 'U'; - sample_f1_1 : in std_logic := 'U'; - sample_f1_34 : in std_logic := 'U'; - sample_f1_2 : in std_logic := 'U'; - sample_f1_35 : in std_logic := 'U'; - sample_f1_3 : in std_logic := 'U'; - sample_f1_36 : in std_logic := 'U'; - sample_f1_4 : in std_logic := 'U'; - sample_f1_48 : in std_logic := 'U'; - sample_f1_49 : in std_logic := 'U'; - sample_f1_50 : in std_logic := 'U'; - sample_f1_51 : in std_logic := 'U'; - sample_f1_52 : in std_logic := 'U'; - sample_f1_53 : in std_logic := 'U'; - sample_f1_54 : in std_logic := 'U'; - sample_f1_55 : in std_logic := 'U'; - sample_f1_56 : in std_logic := 'U'; - sample_f1_57 : in std_logic := 'U'; - sample_f1_58 : in std_logic := 'U'; - sample_f1_59 : in std_logic := 'U'; - sample_f1_60 : in std_logic := 'U'; - sample_f1_44 : in std_logic := 'U'; - sample_f1_12 : in std_logic := 'U'; - sample_f1_45 : in std_logic := 'U'; - sample_f1_13 : in std_logic := 'U'; - sample_f1_46 : in std_logic := 'U'; - sample_f1_14 : in std_logic := 'U'; - sample_f1_47 : in std_logic := 'U'; - sample_f1_15 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f1_out_valid : out std_logic; - N_4 : in std_logic := 'U'; - I_38_4 : in std_logic := 'U'; - I_24_4 : in std_logic := 'U'; - I_20_12 : in std_logic := 'U'; - I_13_20 : in std_logic := 'U'; - I_45_4 : in std_logic := 'U'; - I_9_20 : in std_logic := 'U'; - I_5_20 : in std_logic := 'U'; - I_52_4 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - I_56_4 : in std_logic := 'U'; - I_31_5 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U'; - start_snapshot_f1 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_controler - port( delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - start_snapshot_f2 : out std_logic; - start_snapshot_f1 : out std_logic; - start_snapshot_f0 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U'; - coarse_time_0_c : in std_logic := 'U' - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - port( status_new_err : out std_logic_vector(3 to 3); - valid_ack : in std_logic_vector(3 to 3) := (others => 'U'); - valid_out : out std_logic_vector(3 to 3); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f3_out_valid : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - port( status_new_err : out std_logic_vector(1 to 1); - valid_out_i : out std_logic_vector(1 to 1); - valid_ack : in std_logic_vector(1 to 1) := (others => 'U'); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f1_out_valid : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_waveform_burst - port( sample_f3_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - data_f3_out : out std_logic_vector(159 downto 64); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f3_out_valid : out std_logic; - enable_f3 : in std_logic := 'U'; - sample_f3_val : in std_logic := 'U' - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - port( status_new_err : out std_logic_vector(2 to 2); - valid_ack : in std_logic_vector(2 to 2) := (others => 'U'); - valid_out : out std_logic_vector(2 to 2); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f2_out_valid : in std_logic := 'U' - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - port( status_new_err : out std_logic_vector(0 to 0); - valid_ack : in std_logic_vector(0 to 0) := (others => 'U'); - valid_out : out std_logic_vector(0 to 0); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f0_out_valid : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo - port( data_wen : in std_logic_vector(3 downto 0) := (others => 'U'); - data_ren : in std_logic_vector(3 downto 0) := (others => 'U'); - ready_i_0 : out std_logic_vector(3 downto 0); - time_ren : in std_logic_vector(3 downto 0) := (others => 'U'); - time_wen : in std_logic_vector(3 downto 0) := (others => 'U'); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata_c : out std_logic_vector(31 downto 0); - time_ren_1z : in std_logic := 'U'; - data_ren_1z : in std_logic := 'U'; - un20_time_write : in std_logic := 'U'; - un13_time_write : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - lpp_waveform_fifo_VCC : in std_logic := 'U'; - lpp_waveform_fifo_GND : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_160_11 - port( sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - data_f0_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - sample_f0_37 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_0 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f0_out_valid : out std_logic; - enable_f0 : in std_logic := 'U'; - data_shaping_R0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - start_snapshot_f0 : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U' - ); - end component; - - component - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 - port( sample_f2_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - data_f2_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0) := (others => 'U'); - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_f2_out_valid : out std_logic; - I_13_20 : in std_logic := 'U'; - I_9_20 : in std_logic := 'U'; - I_5_20 : in std_logic := 'U'; - I_38_4 : in std_logic := 'U'; - I_31_5 : in std_logic := 'U'; - N_4 : in std_logic := 'U'; - I_45_4 : in std_logic := 'U'; - I_56_4 : in std_logic := 'U'; - I_52_4 : in std_logic := 'U'; - I_24_4 : in std_logic := 'U'; - I_20_12 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - start_snapshot_f2 : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U' - ); - end component; - - component lpp_waveform_dma - port( addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - haddr_c : out std_logic_vector(31 downto 0); - AHB_Master_In_c_3 : in std_logic := 'U'; - AHB_Master_In_c_0 : in std_logic := 'U'; - AHB_Master_In_c_4 : in std_logic := 'U'; - AHB_Master_In_c_5 : in std_logic := 'U'; - hsize_c : out std_logic_vector(1 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - ready_i_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - data_ren : out std_logic_vector(3 downto 0); - time_ren : out std_logic_vector(3 downto 0); - time_ren_1z : out std_logic; - data_ren_1z : out std_logic; - N_43 : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - hwrite_c : out std_logic; - un20_time_write : out std_logic; - un13_time_write : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_arbiter - port( wdata : out std_logic_vector(31 downto 0); - data_wen : out std_logic_vector(3 downto 0); - valid_ack : out std_logic_vector(3 downto 0); - time_wen : out std_logic_vector(3 downto 0); - data_f3_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f2_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f1_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f0_out : in std_logic_vector(159 downto 64) := (others => 'U'); - valid_out_i : in std_logic_vector(1 to 1) := (others => 'U'); - ready_i_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - valid_out_3 : in std_logic := 'U'; - valid_out_2 : in std_logic := 'U'; - valid_out_0 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - signal N_45, N_37, \DWACT_FINC_E[0]\, N_14, - \DWACT_FINC_E[4]\, N_4, \DWACT_FINC_E[6]\, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[5]\, I_56_4, N_11, - I_52_4, \DWACT_FINC_E[3]\, I_45_4, N_19, I_38_4, N_24, - I_31_5, N_29, \DWACT_FINC_E[1]\, I_24_4, N_34, I_20_12, - I_13_20, N_42, I_9_20, I_5_20, start_snapshot_f2, - start_snapshot_f1, start_snapshot_f0, \data_f0_out[64]\, - \data_f0_out[65]\, \data_f0_out[66]\, \data_f0_out[67]\, - \data_f0_out[68]\, \data_f0_out[69]\, \data_f0_out[70]\, - \data_f0_out[71]\, \data_f0_out[72]\, \data_f0_out[73]\, - \data_f0_out[74]\, \data_f0_out[75]\, \data_f0_out[76]\, - \data_f0_out[77]\, \data_f0_out[78]\, \data_f0_out[79]\, - \data_f0_out[80]\, \data_f0_out[81]\, \data_f0_out[82]\, - \data_f0_out[83]\, \data_f0_out[84]\, \data_f0_out[85]\, - \data_f0_out[86]\, \data_f0_out[87]\, \data_f0_out[88]\, - \data_f0_out[89]\, \data_f0_out[90]\, \data_f0_out[91]\, - \data_f0_out[92]\, \data_f0_out[93]\, \data_f0_out[94]\, - \data_f0_out[95]\, \data_f0_out[96]\, \data_f0_out[97]\, - \data_f0_out[98]\, \data_f0_out[99]\, \data_f0_out[100]\, - \data_f0_out[101]\, \data_f0_out[102]\, - \data_f0_out[103]\, \data_f0_out[104]\, - \data_f0_out[105]\, \data_f0_out[106]\, - \data_f0_out[107]\, \data_f0_out[108]\, - \data_f0_out[109]\, \data_f0_out[110]\, - \data_f0_out[111]\, \data_f0_out[112]\, - \data_f0_out[113]\, \data_f0_out[114]\, - \data_f0_out[115]\, \data_f0_out[116]\, - \data_f0_out[117]\, \data_f0_out[118]\, - \data_f0_out[119]\, \data_f0_out[120]\, - \data_f0_out[121]\, \data_f0_out[122]\, - \data_f0_out[123]\, \data_f0_out[124]\, - \data_f0_out[125]\, \data_f0_out[126]\, - \data_f0_out[127]\, \data_f0_out[128]\, - \data_f0_out[129]\, \data_f0_out[130]\, - \data_f0_out[131]\, \data_f0_out[132]\, - \data_f0_out[133]\, \data_f0_out[134]\, - \data_f0_out[135]\, \data_f0_out[136]\, - \data_f0_out[137]\, \data_f0_out[138]\, - \data_f0_out[139]\, \data_f0_out[140]\, - \data_f0_out[141]\, \data_f0_out[142]\, - \data_f0_out[143]\, \data_f0_out[144]\, - \data_f0_out[145]\, \data_f0_out[146]\, - \data_f0_out[147]\, \data_f0_out[148]\, - \data_f0_out[149]\, \data_f0_out[150]\, - \data_f0_out[151]\, \data_f0_out[152]\, - \data_f0_out[153]\, \data_f0_out[154]\, - \data_f0_out[155]\, \data_f0_out[156]\, - \data_f0_out[157]\, \data_f0_out[158]\, - \data_f0_out[159]\, data_f0_out_valid, \data_f1_out[64]\, - \data_f1_out[65]\, \data_f1_out[66]\, \data_f1_out[67]\, - \data_f1_out[68]\, \data_f1_out[69]\, \data_f1_out[70]\, - \data_f1_out[71]\, \data_f1_out[72]\, \data_f1_out[73]\, - \data_f1_out[74]\, \data_f1_out[75]\, \data_f1_out[76]\, - \data_f1_out[77]\, \data_f1_out[78]\, \data_f1_out[79]\, - \data_f1_out[80]\, \data_f1_out[81]\, \data_f1_out[82]\, - \data_f1_out[83]\, \data_f1_out[84]\, \data_f1_out[85]\, - \data_f1_out[86]\, \data_f1_out[87]\, \data_f1_out[88]\, - \data_f1_out[89]\, \data_f1_out[90]\, \data_f1_out[91]\, - \data_f1_out[92]\, \data_f1_out[93]\, \data_f1_out[94]\, - \data_f1_out[95]\, \data_f1_out[96]\, \data_f1_out[97]\, - \data_f1_out[98]\, \data_f1_out[99]\, \data_f1_out[100]\, - \data_f1_out[101]\, \data_f1_out[102]\, - \data_f1_out[103]\, \data_f1_out[104]\, - \data_f1_out[105]\, \data_f1_out[106]\, - \data_f1_out[107]\, \data_f1_out[108]\, - \data_f1_out[109]\, \data_f1_out[110]\, - \data_f1_out[111]\, \data_f1_out[112]\, - \data_f1_out[113]\, \data_f1_out[114]\, - \data_f1_out[115]\, \data_f1_out[116]\, - \data_f1_out[117]\, \data_f1_out[118]\, - \data_f1_out[119]\, \data_f1_out[120]\, - \data_f1_out[121]\, \data_f1_out[122]\, - \data_f1_out[123]\, \data_f1_out[124]\, - \data_f1_out[125]\, \data_f1_out[126]\, - \data_f1_out[127]\, \data_f1_out[128]\, - \data_f1_out[129]\, \data_f1_out[130]\, - \data_f1_out[131]\, \data_f1_out[132]\, - \data_f1_out[133]\, \data_f1_out[134]\, - \data_f1_out[135]\, \data_f1_out[136]\, - \data_f1_out[137]\, \data_f1_out[138]\, - \data_f1_out[139]\, \data_f1_out[140]\, - \data_f1_out[141]\, \data_f1_out[142]\, - \data_f1_out[143]\, \data_f1_out[144]\, - \data_f1_out[145]\, \data_f1_out[146]\, - \data_f1_out[147]\, \data_f1_out[148]\, - \data_f1_out[149]\, \data_f1_out[150]\, - \data_f1_out[151]\, \data_f1_out[152]\, - \data_f1_out[153]\, \data_f1_out[154]\, - \data_f1_out[155]\, \data_f1_out[156]\, - \data_f1_out[157]\, \data_f1_out[158]\, - \data_f1_out[159]\, data_f1_out_valid, \data_f2_out[64]\, - \data_f2_out[65]\, \data_f2_out[66]\, \data_f2_out[67]\, - \data_f2_out[68]\, \data_f2_out[69]\, \data_f2_out[70]\, - \data_f2_out[71]\, \data_f2_out[72]\, \data_f2_out[73]\, - \data_f2_out[74]\, \data_f2_out[75]\, \data_f2_out[76]\, - \data_f2_out[77]\, \data_f2_out[78]\, \data_f2_out[79]\, - \data_f2_out[80]\, \data_f2_out[81]\, \data_f2_out[82]\, - \data_f2_out[83]\, \data_f2_out[84]\, \data_f2_out[85]\, - \data_f2_out[86]\, \data_f2_out[87]\, \data_f2_out[88]\, - \data_f2_out[89]\, \data_f2_out[90]\, \data_f2_out[91]\, - \data_f2_out[92]\, \data_f2_out[93]\, \data_f2_out[94]\, - \data_f2_out[95]\, \data_f2_out[96]\, \data_f2_out[97]\, - \data_f2_out[98]\, \data_f2_out[99]\, \data_f2_out[100]\, - \data_f2_out[101]\, \data_f2_out[102]\, - \data_f2_out[103]\, \data_f2_out[104]\, - \data_f2_out[105]\, \data_f2_out[106]\, - \data_f2_out[107]\, \data_f2_out[108]\, - \data_f2_out[109]\, \data_f2_out[110]\, - \data_f2_out[111]\, \data_f2_out[112]\, - \data_f2_out[113]\, \data_f2_out[114]\, - \data_f2_out[115]\, \data_f2_out[116]\, - \data_f2_out[117]\, \data_f2_out[118]\, - \data_f2_out[119]\, \data_f2_out[120]\, - \data_f2_out[121]\, \data_f2_out[122]\, - \data_f2_out[123]\, \data_f2_out[124]\, - \data_f2_out[125]\, \data_f2_out[126]\, - \data_f2_out[127]\, \data_f2_out[128]\, - \data_f2_out[129]\, \data_f2_out[130]\, - \data_f2_out[131]\, \data_f2_out[132]\, - \data_f2_out[133]\, \data_f2_out[134]\, - \data_f2_out[135]\, \data_f2_out[136]\, - \data_f2_out[137]\, \data_f2_out[138]\, - \data_f2_out[139]\, \data_f2_out[140]\, - \data_f2_out[141]\, \data_f2_out[142]\, - \data_f2_out[143]\, \data_f2_out[144]\, - \data_f2_out[145]\, \data_f2_out[146]\, - \data_f2_out[147]\, \data_f2_out[148]\, - \data_f2_out[149]\, \data_f2_out[150]\, - \data_f2_out[151]\, \data_f2_out[152]\, - \data_f2_out[153]\, \data_f2_out[154]\, - \data_f2_out[155]\, \data_f2_out[156]\, - \data_f2_out[157]\, \data_f2_out[158]\, - \data_f2_out[159]\, data_f2_out_valid, \data_f3_out[64]\, - \data_f3_out[65]\, \data_f3_out[66]\, \data_f3_out[67]\, - \data_f3_out[68]\, \data_f3_out[69]\, \data_f3_out[70]\, - \data_f3_out[71]\, \data_f3_out[72]\, \data_f3_out[73]\, - \data_f3_out[74]\, \data_f3_out[75]\, \data_f3_out[76]\, - \data_f3_out[77]\, \data_f3_out[78]\, \data_f3_out[79]\, - \data_f3_out[80]\, \data_f3_out[81]\, \data_f3_out[82]\, - \data_f3_out[83]\, \data_f3_out[84]\, \data_f3_out[85]\, - \data_f3_out[86]\, \data_f3_out[87]\, \data_f3_out[88]\, - \data_f3_out[89]\, \data_f3_out[90]\, \data_f3_out[91]\, - \data_f3_out[92]\, \data_f3_out[93]\, \data_f3_out[94]\, - \data_f3_out[95]\, \data_f3_out[96]\, \data_f3_out[97]\, - \data_f3_out[98]\, \data_f3_out[99]\, \data_f3_out[100]\, - \data_f3_out[101]\, \data_f3_out[102]\, - \data_f3_out[103]\, \data_f3_out[104]\, - \data_f3_out[105]\, \data_f3_out[106]\, - \data_f3_out[107]\, \data_f3_out[108]\, - \data_f3_out[109]\, \data_f3_out[110]\, - \data_f3_out[111]\, \data_f3_out[112]\, - \data_f3_out[113]\, \data_f3_out[114]\, - \data_f3_out[115]\, \data_f3_out[116]\, - \data_f3_out[117]\, \data_f3_out[118]\, - \data_f3_out[119]\, \data_f3_out[120]\, - \data_f3_out[121]\, \data_f3_out[122]\, - \data_f3_out[123]\, \data_f3_out[124]\, - \data_f3_out[125]\, \data_f3_out[126]\, - \data_f3_out[127]\, \data_f3_out[128]\, - \data_f3_out[129]\, \data_f3_out[130]\, - \data_f3_out[131]\, \data_f3_out[132]\, - \data_f3_out[133]\, \data_f3_out[134]\, - \data_f3_out[135]\, \data_f3_out[136]\, - \data_f3_out[137]\, \data_f3_out[138]\, - \data_f3_out[139]\, \data_f3_out[140]\, - \data_f3_out[141]\, \data_f3_out[142]\, - \data_f3_out[143]\, \data_f3_out[144]\, - \data_f3_out[145]\, \data_f3_out[146]\, - \data_f3_out[147]\, \data_f3_out[148]\, - \data_f3_out[149]\, \data_f3_out[150]\, - \data_f3_out[151]\, \data_f3_out[152]\, - \data_f3_out[153]\, \data_f3_out[154]\, - \data_f3_out[155]\, \data_f3_out[156]\, - \data_f3_out[157]\, \data_f3_out[158]\, - \data_f3_out[159]\, data_f3_out_valid, \valid_ack[3]\, - \valid_out[3]\, \valid_ack[0]\, \valid_out[0]\, - \valid_out_i[1]\, \valid_ack[1]\, \valid_ack[2]\, - \valid_out[2]\, \wdata[0]\, \wdata[1]\, \wdata[2]\, - \wdata[3]\, \wdata[4]\, \wdata[5]\, \wdata[6]\, - \wdata[7]\, \wdata[8]\, \wdata[9]\, \wdata[10]\, - \wdata[11]\, \wdata[12]\, \wdata[13]\, \wdata[14]\, - \wdata[15]\, \wdata[16]\, \wdata[17]\, \wdata[18]\, - \wdata[19]\, \wdata[20]\, \wdata[21]\, \wdata[22]\, - \wdata[23]\, \wdata[24]\, \wdata[25]\, \wdata[26]\, - \wdata[27]\, \wdata[28]\, \wdata[29]\, \wdata[30]\, - \wdata[31]\, \data_wen[0]\, \data_wen[1]\, \data_wen[2]\, - \data_wen[3]\, \time_wen[0]\, \time_wen[1]\, - \time_wen[2]\, \time_wen[3]\, \ready_i_0[0]\, - \ready_i_0[1]\, \ready_i_0[2]\, \ready_i_0[3]\, - \data_ren[0]\, \data_ren[1]\, \data_ren[2]\, - \data_ren[3]\, \time_ren[0]\, \time_ren[1]\, - \time_ren[2]\, \time_ren[3]\, time_ren, data_ren, - un20_time_write, un13_time_write, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 - Use entity work. - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1(DEF_ARCH); - for all : lpp_waveform_snapshot_controler - Use entity work.lpp_waveform_snapshot_controler(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\(DEF_ARCH); - for all : lpp_waveform_burst - Use entity work.lpp_waveform_burst(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\(DEF_ARCH); - for all : lpp_waveform_fifo - Use entity work.lpp_waveform_fifo(DEF_ARCH); - for all : lpp_waveform_snapshot_160_11 - Use entity work.lpp_waveform_snapshot_160_11(DEF_ARCH); - for all : lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 - Use entity work. - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1(DEF_ARCH); - for all : lpp_waveform_dma - Use entity work.lpp_waveform_dma(DEF_ARCH); - for all : lpp_waveform_fifo_arbiter - Use entity work.lpp_waveform_fifo_arbiter(DEF_ARCH); -begin - - - un7_nb_snapshot_param_more_one_I_45 : XOR2 - port map(A => N_19, B => nb_snapshot_param(8), Y => I_45_4); - - un7_nb_snapshot_param_more_one_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => nb_snapshot_param(6), Y => N_24); - - un7_nb_snapshot_param_more_one_I_16 : AND3 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), C => nb_snapshot_param(2), Y => - \DWACT_FINC_E[0]\); - - lpp_waveform_snapshot_f1 : - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1 - port map(sample_f1_wdata_95 => sample_f1_wdata_95, - sample_f1_wdata_94 => sample_f1_wdata_94, - sample_f1_wdata_93 => sample_f1_wdata_93, - sample_f1_wdata_92 => sample_f1_wdata_92, - sample_f1_wdata_91 => sample_f1_wdata_91, - sample_f1_wdata_90 => sample_f1_wdata_90, - sample_f1_wdata_89 => sample_f1_wdata_89, - sample_f1_wdata_88 => sample_f1_wdata_88, - sample_f1_wdata_87 => sample_f1_wdata_87, - sample_f1_wdata_86 => sample_f1_wdata_86, - sample_f1_wdata_85 => sample_f1_wdata_85, - sample_f1_wdata_84 => sample_f1_wdata_84, - sample_f1_wdata_83 => sample_f1_wdata_83, - sample_f1_wdata_82 => sample_f1_wdata_82, - sample_f1_wdata_81 => sample_f1_wdata_81, - sample_f1_wdata_80 => sample_f1_wdata_80, - sample_f1_wdata_79 => sample_f1_wdata_79, - sample_f1_wdata_78 => sample_f1_wdata_78, - sample_f1_wdata_77 => sample_f1_wdata_77, - sample_f1_wdata_76 => sample_f1_wdata_76, - sample_f1_wdata_75 => sample_f1_wdata_75, - sample_f1_wdata_74 => sample_f1_wdata_74, - sample_f1_wdata_73 => sample_f1_wdata_73, - sample_f1_wdata_72 => sample_f1_wdata_72, - sample_f1_wdata_71 => sample_f1_wdata_71, - sample_f1_wdata_70 => sample_f1_wdata_70, - sample_f1_wdata_69 => sample_f1_wdata_69, - sample_f1_wdata_68 => sample_f1_wdata_68, - sample_f1_wdata_67 => sample_f1_wdata_67, - sample_f1_wdata_66 => sample_f1_wdata_66, - sample_f1_wdata_65 => sample_f1_wdata_65, - sample_f1_wdata_64 => sample_f1_wdata_64, - sample_f1_wdata_63 => sample_f1_wdata_63, - sample_f1_wdata_62 => sample_f1_wdata_62, - sample_f1_wdata_61 => sample_f1_wdata_61, - sample_f1_wdata_60 => sample_f1_wdata_60, - sample_f1_wdata_59 => sample_f1_wdata_59, - sample_f1_wdata_58 => sample_f1_wdata_58, - sample_f1_wdata_57 => sample_f1_wdata_57, - sample_f1_wdata_56 => sample_f1_wdata_56, - sample_f1_wdata_55 => sample_f1_wdata_55, - sample_f1_wdata_54 => sample_f1_wdata_54, - sample_f1_wdata_53 => sample_f1_wdata_53, - sample_f1_wdata_52 => sample_f1_wdata_52, - sample_f1_wdata_51 => sample_f1_wdata_51, - sample_f1_wdata_50 => sample_f1_wdata_50, - sample_f1_wdata_49 => sample_f1_wdata_49, - sample_f1_wdata_48 => sample_f1_wdata_48, - sample_f1_wdata_15 => sample_f1_wdata_15, - sample_f1_wdata_14 => sample_f1_wdata_14, - sample_f1_wdata_13 => sample_f1_wdata_13, - sample_f1_wdata_12 => sample_f1_wdata_12, - sample_f1_wdata_11 => sample_f1_wdata_11, - sample_f1_wdata_10 => sample_f1_wdata_10, - sample_f1_wdata_9 => sample_f1_wdata_9, sample_f1_wdata_8 - => sample_f1_wdata_8, sample_f1_wdata_7 => - sample_f1_wdata_7, sample_f1_wdata_6 => sample_f1_wdata_6, - sample_f1_wdata_5 => sample_f1_wdata_5, sample_f1_wdata_4 - => sample_f1_wdata_4, sample_f1_wdata_3 => - sample_f1_wdata_3, sample_f1_wdata_2 => sample_f1_wdata_2, - sample_f1_wdata_1 => sample_f1_wdata_1, sample_f1_wdata_0 - => sample_f1_wdata_0, data_f1_out(159) => - \data_f1_out[159]\, data_f1_out(158) => - \data_f1_out[158]\, data_f1_out(157) => - \data_f1_out[157]\, data_f1_out(156) => - \data_f1_out[156]\, data_f1_out(155) => - \data_f1_out[155]\, data_f1_out(154) => - \data_f1_out[154]\, data_f1_out(153) => - \data_f1_out[153]\, data_f1_out(152) => - \data_f1_out[152]\, data_f1_out(151) => - \data_f1_out[151]\, data_f1_out(150) => - \data_f1_out[150]\, data_f1_out(149) => - \data_f1_out[149]\, data_f1_out(148) => - \data_f1_out[148]\, data_f1_out(147) => - \data_f1_out[147]\, data_f1_out(146) => - \data_f1_out[146]\, data_f1_out(145) => - \data_f1_out[145]\, data_f1_out(144) => - \data_f1_out[144]\, data_f1_out(143) => - \data_f1_out[143]\, data_f1_out(142) => - \data_f1_out[142]\, data_f1_out(141) => - \data_f1_out[141]\, data_f1_out(140) => - \data_f1_out[140]\, data_f1_out(139) => - \data_f1_out[139]\, data_f1_out(138) => - \data_f1_out[138]\, data_f1_out(137) => - \data_f1_out[137]\, data_f1_out(136) => - \data_f1_out[136]\, data_f1_out(135) => - \data_f1_out[135]\, data_f1_out(134) => - \data_f1_out[134]\, data_f1_out(133) => - \data_f1_out[133]\, data_f1_out(132) => - \data_f1_out[132]\, data_f1_out(131) => - \data_f1_out[131]\, data_f1_out(130) => - \data_f1_out[130]\, data_f1_out(129) => - \data_f1_out[129]\, data_f1_out(128) => - \data_f1_out[128]\, data_f1_out(127) => - \data_f1_out[127]\, data_f1_out(126) => - \data_f1_out[126]\, data_f1_out(125) => - \data_f1_out[125]\, data_f1_out(124) => - \data_f1_out[124]\, data_f1_out(123) => - \data_f1_out[123]\, data_f1_out(122) => - \data_f1_out[122]\, data_f1_out(121) => - \data_f1_out[121]\, data_f1_out(120) => - \data_f1_out[120]\, data_f1_out(119) => - \data_f1_out[119]\, data_f1_out(118) => - \data_f1_out[118]\, data_f1_out(117) => - \data_f1_out[117]\, data_f1_out(116) => - \data_f1_out[116]\, data_f1_out(115) => - \data_f1_out[115]\, data_f1_out(114) => - \data_f1_out[114]\, data_f1_out(113) => - \data_f1_out[113]\, data_f1_out(112) => - \data_f1_out[112]\, data_f1_out(111) => - \data_f1_out[111]\, data_f1_out(110) => - \data_f1_out[110]\, data_f1_out(109) => - \data_f1_out[109]\, data_f1_out(108) => - \data_f1_out[108]\, data_f1_out(107) => - \data_f1_out[107]\, data_f1_out(106) => - \data_f1_out[106]\, data_f1_out(105) => - \data_f1_out[105]\, data_f1_out(104) => - \data_f1_out[104]\, data_f1_out(103) => - \data_f1_out[103]\, data_f1_out(102) => - \data_f1_out[102]\, data_f1_out(101) => - \data_f1_out[101]\, data_f1_out(100) => - \data_f1_out[100]\, data_f1_out(99) => \data_f1_out[99]\, - data_f1_out(98) => \data_f1_out[98]\, data_f1_out(97) => - \data_f1_out[97]\, data_f1_out(96) => \data_f1_out[96]\, - data_f1_out(95) => \data_f1_out[95]\, data_f1_out(94) => - \data_f1_out[94]\, data_f1_out(93) => \data_f1_out[93]\, - data_f1_out(92) => \data_f1_out[92]\, data_f1_out(91) => - \data_f1_out[91]\, data_f1_out(90) => \data_f1_out[90]\, - data_f1_out(89) => \data_f1_out[89]\, data_f1_out(88) => - \data_f1_out[88]\, data_f1_out(87) => \data_f1_out[87]\, - data_f1_out(86) => \data_f1_out[86]\, data_f1_out(85) => - \data_f1_out[85]\, data_f1_out(84) => \data_f1_out[84]\, - data_f1_out(83) => \data_f1_out[83]\, data_f1_out(82) => - \data_f1_out[82]\, data_f1_out(81) => \data_f1_out[81]\, - data_f1_out(80) => \data_f1_out[80]\, data_f1_out(79) => - \data_f1_out[79]\, data_f1_out(78) => \data_f1_out[78]\, - data_f1_out(77) => \data_f1_out[77]\, data_f1_out(76) => - \data_f1_out[76]\, data_f1_out(75) => \data_f1_out[75]\, - data_f1_out(74) => \data_f1_out[74]\, data_f1_out(73) => - \data_f1_out[73]\, data_f1_out(72) => \data_f1_out[72]\, - data_f1_out(71) => \data_f1_out[71]\, data_f1_out(70) => - \data_f1_out[70]\, data_f1_out(69) => \data_f1_out[69]\, - data_f1_out(68) => \data_f1_out[68]\, data_f1_out(67) => - \data_f1_out[67]\, data_f1_out(66) => \data_f1_out[66]\, - data_f1_out(65) => \data_f1_out[65]\, data_f1_out(64) => - \data_f1_out[64]\, nb_snapshot_param(0) => - nb_snapshot_param(0), sample_f1_37 => sample_f1_37, - sample_f1_5 => sample_f1_5, sample_f1_38 => sample_f1_38, - sample_f1_6 => sample_f1_6, sample_f1_39 => sample_f1_39, - sample_f1_7 => sample_f1_7, sample_f1_40 => sample_f1_40, - sample_f1_8 => sample_f1_8, sample_f1_41 => sample_f1_41, - sample_f1_9 => sample_f1_9, sample_f1_42 => sample_f1_42, - sample_f1_10 => sample_f1_10, sample_f1_43 => - sample_f1_43, sample_f1_11 => sample_f1_11, sample_f1_61 - => sample_f1_61, sample_f1_62 => sample_f1_62, - sample_f1_63 => sample_f1_63, sample_f1_32 => - sample_f1_32, sample_f1_0 => sample_f1_0, sample_f1_33 - => sample_f1_33, sample_f1_1 => sample_f1_1, - sample_f1_34 => sample_f1_34, sample_f1_2 => sample_f1_2, - sample_f1_35 => sample_f1_35, sample_f1_3 => sample_f1_3, - sample_f1_36 => sample_f1_36, sample_f1_4 => sample_f1_4, - sample_f1_48 => sample_f1_48, sample_f1_49 => - sample_f1_49, sample_f1_50 => sample_f1_50, sample_f1_51 - => sample_f1_51, sample_f1_52 => sample_f1_52, - sample_f1_53 => sample_f1_53, sample_f1_54 => - sample_f1_54, sample_f1_55 => sample_f1_55, sample_f1_56 - => sample_f1_56, sample_f1_57 => sample_f1_57, - sample_f1_58 => sample_f1_58, sample_f1_59 => - sample_f1_59, sample_f1_60 => sample_f1_60, sample_f1_44 - => sample_f1_44, sample_f1_12 => sample_f1_12, - sample_f1_45 => sample_f1_45, sample_f1_13 => - sample_f1_13, sample_f1_46 => sample_f1_46, sample_f1_14 - => sample_f1_14, sample_f1_47 => sample_f1_47, - sample_f1_15 => sample_f1_15, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, data_f1_out_valid => data_f1_out_valid, - N_4 => N_4, I_38_4 => I_38_4, I_24_4 => I_24_4, I_20_12 - => I_20_12, I_13_20 => I_13_20, I_45_4 => I_45_4, I_9_20 - => I_9_20, I_5_20 => I_5_20, I_52_4 => I_52_4, - data_shaping_R1 => data_shaping_R1, data_shaping_R1_0 => - data_shaping_R1_0, I_56_4 => I_56_4, I_31_5 => I_31_5, - enable_f1 => enable_f1, burst_f1 => burst_f1, - sample_f1_val_0 => sample_f1_val_0, start_snapshot_f1 => - start_snapshot_f1); - - lpp_waveform_snapshot_controler_1 : - lpp_waveform_snapshot_controler - port map(delta_f2_f0(9) => delta_f2_f0(9), delta_f2_f0(8) - => delta_f2_f0(8), delta_f2_f0(7) => delta_f2_f0(7), - delta_f2_f0(6) => delta_f2_f0(6), delta_f2_f0(5) => - delta_f2_f0(5), delta_f2_f0(4) => delta_f2_f0(4), - delta_f2_f0(3) => delta_f2_f0(3), delta_f2_f0(2) => - delta_f2_f0(2), delta_f2_f0(1) => delta_f2_f0(1), - delta_f2_f0(0) => delta_f2_f0(0), delta_snapshot(15) => - delta_snapshot(15), delta_snapshot(14) => - delta_snapshot(14), delta_snapshot(13) => - delta_snapshot(13), delta_snapshot(12) => - delta_snapshot(12), delta_snapshot(11) => - delta_snapshot(11), delta_snapshot(10) => - delta_snapshot(10), delta_snapshot(9) => - delta_snapshot(9), delta_snapshot(8) => delta_snapshot(8), - delta_snapshot(7) => delta_snapshot(7), delta_snapshot(6) - => delta_snapshot(6), delta_snapshot(5) => - delta_snapshot(5), delta_snapshot(4) => delta_snapshot(4), - delta_snapshot(3) => delta_snapshot(3), delta_snapshot(2) - => delta_snapshot(2), delta_snapshot(1) => - delta_snapshot(1), delta_snapshot(0) => delta_snapshot(0), - delta_f2_f1(9) => delta_f2_f1(9), delta_f2_f1(8) => - delta_f2_f1(8), delta_f2_f1(7) => delta_f2_f1(7), - delta_f2_f1(6) => delta_f2_f1(6), delta_f2_f1(5) => - delta_f2_f1(5), delta_f2_f1(4) => delta_f2_f1(4), - delta_f2_f1(3) => delta_f2_f1(3), delta_f2_f1(2) => - delta_f2_f1(2), delta_f2_f1(1) => delta_f2_f1(1), - delta_f2_f1(0) => delta_f2_f1(0), start_snapshot_f2 => - start_snapshot_f2, start_snapshot_f1 => start_snapshot_f1, - start_snapshot_f0 => start_snapshot_f0, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, sample_f0_val_0 => - sample_f0_val_0, sample_f2_val => sample_f2_val, - coarse_time_0_c => coarse_time_0_c); - - un7_nb_snapshot_param_more_one_I_20 : XOR2 - port map(A => N_37, B => nb_snapshot_param(4), Y => I_20_12); - - \all_input_valid.3.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - port map(status_new_err(3) => status_new_err(3), - valid_ack(3) => \valid_ack[3]\, valid_out(3) => - \valid_out[3]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - data_f3_out_valid => data_f3_out_valid); - - un7_nb_snapshot_param_more_one_I_52 : XOR2 - port map(A => N_14, B => nb_snapshot_param(9), Y => I_52_4); - - VCC_i : VCC - port map(Y => \VCC\); - - un7_nb_snapshot_param_more_one_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - un7_nb_snapshot_param_more_one_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => nb_snapshot_param(3), - C => nb_snapshot_param(4), Y => N_34); - - un7_nb_snapshot_param_more_one_I_56 : XOR2 - port map(A => N_11, B => nb_snapshot_param(10), Y => I_56_4); - - un7_nb_snapshot_param_more_one_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un7_nb_snapshot_param_more_one_I_19 : NOR2B - port map(A => nb_snapshot_param(3), B => \DWACT_FINC_E[0]\, - Y => N_37); - - un7_nb_snapshot_param_more_one_I_24 : XOR2 - port map(A => N_34, B => nb_snapshot_param(5), Y => I_24_4); - - un7_nb_snapshot_param_more_one_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_19); - - \all_input_valid.1.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - port map(status_new_err(1) => status_new_err(1), - valid_out_i(1) => \valid_out_i[1]\, valid_ack(1) => - \valid_ack[1]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - data_f1_out_valid => data_f1_out_valid); - - un7_nb_snapshot_param_more_one_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => nb_snapshot_param(8), - C => nb_snapshot_param(9), Y => N_11); - - un7_nb_snapshot_param_more_one_I_13 : XOR2 - port map(A => N_42, B => nb_snapshot_param(3), Y => I_13_20); - - un7_nb_snapshot_param_more_one_I_9 : XOR2 - port map(A => N_45, B => nb_snapshot_param(2), Y => I_9_20); - - un7_nb_snapshot_param_more_one_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => nb_snapshot_param(9), - C => nb_snapshot_param(10), Y => N_4); - - un7_nb_snapshot_param_more_one_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => nb_snapshot_param(5), Y => N_29); - - GND_i : GND - port map(Y => \GND\); - - un7_nb_snapshot_param_more_one_I_59 : AND3 - port map(A => nb_snapshot_param(6), B => - nb_snapshot_param(7), C => nb_snapshot_param(8), Y => - \DWACT_FINC_E[5]\); - - lpp_waveform_burst_f3 : lpp_waveform_burst - port map(sample_f3_wdata(95) => sample_f3_wdata(95), - sample_f3_wdata(94) => sample_f3_wdata(94), - sample_f3_wdata(93) => sample_f3_wdata(93), - sample_f3_wdata(92) => sample_f3_wdata(92), - sample_f3_wdata(91) => sample_f3_wdata(91), - sample_f3_wdata(90) => sample_f3_wdata(90), - sample_f3_wdata(89) => sample_f3_wdata(89), - sample_f3_wdata(88) => sample_f3_wdata(88), - sample_f3_wdata(87) => sample_f3_wdata(87), - sample_f3_wdata(86) => sample_f3_wdata(86), - sample_f3_wdata(85) => sample_f3_wdata(85), - sample_f3_wdata(84) => sample_f3_wdata(84), - sample_f3_wdata(83) => sample_f3_wdata(83), - sample_f3_wdata(82) => sample_f3_wdata(82), - sample_f3_wdata(81) => sample_f3_wdata(81), - sample_f3_wdata(80) => sample_f3_wdata(80), - sample_f3_wdata(79) => sample_f3_wdata(79), - sample_f3_wdata(78) => sample_f3_wdata(78), - sample_f3_wdata(77) => sample_f3_wdata(77), - sample_f3_wdata(76) => sample_f3_wdata(76), - sample_f3_wdata(75) => sample_f3_wdata(75), - sample_f3_wdata(74) => sample_f3_wdata(74), - sample_f3_wdata(73) => sample_f3_wdata(73), - sample_f3_wdata(72) => sample_f3_wdata(72), - sample_f3_wdata(71) => sample_f3_wdata(71), - sample_f3_wdata(70) => sample_f3_wdata(70), - sample_f3_wdata(69) => sample_f3_wdata(69), - sample_f3_wdata(68) => sample_f3_wdata(68), - sample_f3_wdata(67) => sample_f3_wdata(67), - sample_f3_wdata(66) => sample_f3_wdata(66), - sample_f3_wdata(65) => sample_f3_wdata(65), - sample_f3_wdata(64) => sample_f3_wdata(64), - sample_f3_wdata(63) => sample_f3_wdata(63), - sample_f3_wdata(62) => sample_f3_wdata(62), - sample_f3_wdata(61) => sample_f3_wdata(61), - sample_f3_wdata(60) => sample_f3_wdata(60), - sample_f3_wdata(59) => sample_f3_wdata(59), - sample_f3_wdata(58) => sample_f3_wdata(58), - sample_f3_wdata(57) => sample_f3_wdata(57), - sample_f3_wdata(56) => sample_f3_wdata(56), - sample_f3_wdata(55) => sample_f3_wdata(55), - sample_f3_wdata(54) => sample_f3_wdata(54), - sample_f3_wdata(53) => sample_f3_wdata(53), - sample_f3_wdata(52) => sample_f3_wdata(52), - sample_f3_wdata(51) => sample_f3_wdata(51), - sample_f3_wdata(50) => sample_f3_wdata(50), - sample_f3_wdata(49) => sample_f3_wdata(49), - sample_f3_wdata(48) => sample_f3_wdata(48), - sample_f3_wdata(47) => sample_f3_wdata(47), - sample_f3_wdata(46) => sample_f3_wdata(46), - sample_f3_wdata(45) => sample_f3_wdata(45), - sample_f3_wdata(44) => sample_f3_wdata(44), - sample_f3_wdata(43) => sample_f3_wdata(43), - sample_f3_wdata(42) => sample_f3_wdata(42), - sample_f3_wdata(41) => sample_f3_wdata(41), - sample_f3_wdata(40) => sample_f3_wdata(40), - sample_f3_wdata(39) => sample_f3_wdata(39), - sample_f3_wdata(38) => sample_f3_wdata(38), - sample_f3_wdata(37) => sample_f3_wdata(37), - sample_f3_wdata(36) => sample_f3_wdata(36), - sample_f3_wdata(35) => sample_f3_wdata(35), - sample_f3_wdata(34) => sample_f3_wdata(34), - sample_f3_wdata(33) => sample_f3_wdata(33), - sample_f3_wdata(32) => sample_f3_wdata(32), - sample_f3_wdata(31) => sample_f3_wdata(31), - sample_f3_wdata(30) => sample_f3_wdata(30), - sample_f3_wdata(29) => sample_f3_wdata(29), - sample_f3_wdata(28) => sample_f3_wdata(28), - sample_f3_wdata(27) => sample_f3_wdata(27), - sample_f3_wdata(26) => sample_f3_wdata(26), - sample_f3_wdata(25) => sample_f3_wdata(25), - sample_f3_wdata(24) => sample_f3_wdata(24), - sample_f3_wdata(23) => sample_f3_wdata(23), - sample_f3_wdata(22) => sample_f3_wdata(22), - sample_f3_wdata(21) => sample_f3_wdata(21), - sample_f3_wdata(20) => sample_f3_wdata(20), - sample_f3_wdata(19) => sample_f3_wdata(19), - sample_f3_wdata(18) => sample_f3_wdata(18), - sample_f3_wdata(17) => sample_f3_wdata(17), - sample_f3_wdata(16) => sample_f3_wdata(16), - sample_f3_wdata(15) => sample_f3_wdata(15), - sample_f3_wdata(14) => sample_f3_wdata(14), - sample_f3_wdata(13) => sample_f3_wdata(13), - sample_f3_wdata(12) => sample_f3_wdata(12), - sample_f3_wdata(11) => sample_f3_wdata(11), - sample_f3_wdata(10) => sample_f3_wdata(10), - sample_f3_wdata(9) => sample_f3_wdata(9), - sample_f3_wdata(8) => sample_f3_wdata(8), - sample_f3_wdata(7) => sample_f3_wdata(7), - sample_f3_wdata(6) => sample_f3_wdata(6), - sample_f3_wdata(5) => sample_f3_wdata(5), - sample_f3_wdata(4) => sample_f3_wdata(4), - sample_f3_wdata(3) => sample_f3_wdata(3), - sample_f3_wdata(2) => sample_f3_wdata(2), - sample_f3_wdata(1) => sample_f3_wdata(1), - sample_f3_wdata(0) => sample_f3_wdata(0), - data_f3_out(159) => \data_f3_out[159]\, data_f3_out(158) - => \data_f3_out[158]\, data_f3_out(157) => - \data_f3_out[157]\, data_f3_out(156) => - \data_f3_out[156]\, data_f3_out(155) => - \data_f3_out[155]\, data_f3_out(154) => - \data_f3_out[154]\, data_f3_out(153) => - \data_f3_out[153]\, data_f3_out(152) => - \data_f3_out[152]\, data_f3_out(151) => - \data_f3_out[151]\, data_f3_out(150) => - \data_f3_out[150]\, data_f3_out(149) => - \data_f3_out[149]\, data_f3_out(148) => - \data_f3_out[148]\, data_f3_out(147) => - \data_f3_out[147]\, data_f3_out(146) => - \data_f3_out[146]\, data_f3_out(145) => - \data_f3_out[145]\, data_f3_out(144) => - \data_f3_out[144]\, data_f3_out(143) => - \data_f3_out[143]\, data_f3_out(142) => - \data_f3_out[142]\, data_f3_out(141) => - \data_f3_out[141]\, data_f3_out(140) => - \data_f3_out[140]\, data_f3_out(139) => - \data_f3_out[139]\, data_f3_out(138) => - \data_f3_out[138]\, data_f3_out(137) => - \data_f3_out[137]\, data_f3_out(136) => - \data_f3_out[136]\, data_f3_out(135) => - \data_f3_out[135]\, data_f3_out(134) => - \data_f3_out[134]\, data_f3_out(133) => - \data_f3_out[133]\, data_f3_out(132) => - \data_f3_out[132]\, data_f3_out(131) => - \data_f3_out[131]\, data_f3_out(130) => - \data_f3_out[130]\, data_f3_out(129) => - \data_f3_out[129]\, data_f3_out(128) => - \data_f3_out[128]\, data_f3_out(127) => - \data_f3_out[127]\, data_f3_out(126) => - \data_f3_out[126]\, data_f3_out(125) => - \data_f3_out[125]\, data_f3_out(124) => - \data_f3_out[124]\, data_f3_out(123) => - \data_f3_out[123]\, data_f3_out(122) => - \data_f3_out[122]\, data_f3_out(121) => - \data_f3_out[121]\, data_f3_out(120) => - \data_f3_out[120]\, data_f3_out(119) => - \data_f3_out[119]\, data_f3_out(118) => - \data_f3_out[118]\, data_f3_out(117) => - \data_f3_out[117]\, data_f3_out(116) => - \data_f3_out[116]\, data_f3_out(115) => - \data_f3_out[115]\, data_f3_out(114) => - \data_f3_out[114]\, data_f3_out(113) => - \data_f3_out[113]\, data_f3_out(112) => - \data_f3_out[112]\, data_f3_out(111) => - \data_f3_out[111]\, data_f3_out(110) => - \data_f3_out[110]\, data_f3_out(109) => - \data_f3_out[109]\, data_f3_out(108) => - \data_f3_out[108]\, data_f3_out(107) => - \data_f3_out[107]\, data_f3_out(106) => - \data_f3_out[106]\, data_f3_out(105) => - \data_f3_out[105]\, data_f3_out(104) => - \data_f3_out[104]\, data_f3_out(103) => - \data_f3_out[103]\, data_f3_out(102) => - \data_f3_out[102]\, data_f3_out(101) => - \data_f3_out[101]\, data_f3_out(100) => - \data_f3_out[100]\, data_f3_out(99) => \data_f3_out[99]\, - data_f3_out(98) => \data_f3_out[98]\, data_f3_out(97) => - \data_f3_out[97]\, data_f3_out(96) => \data_f3_out[96]\, - data_f3_out(95) => \data_f3_out[95]\, data_f3_out(94) => - \data_f3_out[94]\, data_f3_out(93) => \data_f3_out[93]\, - data_f3_out(92) => \data_f3_out[92]\, data_f3_out(91) => - \data_f3_out[91]\, data_f3_out(90) => \data_f3_out[90]\, - data_f3_out(89) => \data_f3_out[89]\, data_f3_out(88) => - \data_f3_out[88]\, data_f3_out(87) => \data_f3_out[87]\, - data_f3_out(86) => \data_f3_out[86]\, data_f3_out(85) => - \data_f3_out[85]\, data_f3_out(84) => \data_f3_out[84]\, - data_f3_out(83) => \data_f3_out[83]\, data_f3_out(82) => - \data_f3_out[82]\, data_f3_out(81) => \data_f3_out[81]\, - data_f3_out(80) => \data_f3_out[80]\, data_f3_out(79) => - \data_f3_out[79]\, data_f3_out(78) => \data_f3_out[78]\, - data_f3_out(77) => \data_f3_out[77]\, data_f3_out(76) => - \data_f3_out[76]\, data_f3_out(75) => \data_f3_out[75]\, - data_f3_out(74) => \data_f3_out[74]\, data_f3_out(73) => - \data_f3_out[73]\, data_f3_out(72) => \data_f3_out[72]\, - data_f3_out(71) => \data_f3_out[71]\, data_f3_out(70) => - \data_f3_out[70]\, data_f3_out(69) => \data_f3_out[69]\, - data_f3_out(68) => \data_f3_out[68]\, data_f3_out(67) => - \data_f3_out[67]\, data_f3_out(66) => \data_f3_out[66]\, - data_f3_out(65) => \data_f3_out[65]\, data_f3_out(64) => - \data_f3_out[64]\, HRESETn_c => HRESETn_c, HCLK_c => - HCLK_c, data_f3_out_valid => data_f3_out_valid, enable_f3 - => enable_f3, sample_f3_val => sample_f3_val); - - \all_input_valid.2.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - port map(status_new_err(2) => status_new_err(2), - valid_ack(2) => \valid_ack[2]\, valid_out(2) => - \valid_out[2]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - data_f2_out_valid => data_f2_out_valid); - - un7_nb_snapshot_param_more_one_I_41 : AND2 - port map(A => nb_snapshot_param(6), B => - nb_snapshot_param(7), Y => \DWACT_FINC_E[3]\); - - un7_nb_snapshot_param_more_one_I_38 : XOR2 - port map(A => N_24, B => nb_snapshot_param(7), Y => I_38_4); - - \all_input_valid.0.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - port map(status_new_err(0) => status_new_err(0), - valid_ack(0) => \valid_ack[0]\, valid_out(0) => - \valid_out[0]\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - data_f0_out_valid => data_f0_out_valid); - - un7_nb_snapshot_param_more_one_I_27 : AND2 - port map(A => nb_snapshot_param(3), B => - nb_snapshot_param(4), Y => \DWACT_FINC_E[1]\); - - un7_nb_snapshot_param_more_one_I_34 : AND3 - port map(A => nb_snapshot_param(3), B => - nb_snapshot_param(4), C => nb_snapshot_param(5), Y => - \DWACT_FINC_E[2]\); - - un7_nb_snapshot_param_more_one_I_8 : NOR2B - port map(A => nb_snapshot_param(1), B => - nb_snapshot_param(0), Y => N_45); - - lpp_waveform_fifo_1 : lpp_waveform_fifo - port map(data_wen(3) => \data_wen[3]\, data_wen(2) => - \data_wen[2]\, data_wen(1) => \data_wen[1]\, data_wen(0) - => \data_wen[0]\, data_ren(3) => \data_ren[3]\, - data_ren(2) => \data_ren[2]\, data_ren(1) => - \data_ren[1]\, data_ren(0) => \data_ren[0]\, ready_i_0(3) - => \ready_i_0[3]\, ready_i_0(2) => \ready_i_0[2]\, - ready_i_0(1) => \ready_i_0[1]\, ready_i_0(0) => - \ready_i_0[0]\, time_ren(3) => \time_ren[3]\, time_ren(2) - => \time_ren[2]\, time_ren(1) => \time_ren[1]\, - time_ren(0) => \time_ren[0]\, time_wen(3) => - \time_wen[3]\, time_wen(2) => \time_wen[2]\, time_wen(1) - => \time_wen[1]\, time_wen(0) => \time_wen[0]\, - wdata(31) => \wdata[31]\, wdata(30) => \wdata[30]\, - wdata(29) => \wdata[29]\, wdata(28) => \wdata[28]\, - wdata(27) => \wdata[27]\, wdata(26) => \wdata[26]\, - wdata(25) => \wdata[25]\, wdata(24) => \wdata[24]\, - wdata(23) => \wdata[23]\, wdata(22) => \wdata[22]\, - wdata(21) => \wdata[21]\, wdata(20) => \wdata[20]\, - wdata(19) => \wdata[19]\, wdata(18) => \wdata[18]\, - wdata(17) => \wdata[17]\, wdata(16) => \wdata[16]\, - wdata(15) => \wdata[15]\, wdata(14) => \wdata[14]\, - wdata(13) => \wdata[13]\, wdata(12) => \wdata[12]\, - wdata(11) => \wdata[11]\, wdata(10) => \wdata[10]\, - wdata(9) => \wdata[9]\, wdata(8) => \wdata[8]\, wdata(7) - => \wdata[7]\, wdata(6) => \wdata[6]\, wdata(5) => - \wdata[5]\, wdata(4) => \wdata[4]\, wdata(3) => - \wdata[3]\, wdata(2) => \wdata[2]\, wdata(1) => - \wdata[1]\, wdata(0) => \wdata[0]\, hwdata_c(31) => - hwdata_c(31), hwdata_c(30) => hwdata_c(30), hwdata_c(29) - => hwdata_c(29), hwdata_c(28) => hwdata_c(28), - hwdata_c(27) => hwdata_c(27), hwdata_c(26) => - hwdata_c(26), hwdata_c(25) => hwdata_c(25), hwdata_c(24) - => hwdata_c(24), hwdata_c(23) => hwdata_c(23), - hwdata_c(22) => hwdata_c(22), hwdata_c(21) => - hwdata_c(21), hwdata_c(20) => hwdata_c(20), hwdata_c(19) - => hwdata_c(19), hwdata_c(18) => hwdata_c(18), - hwdata_c(17) => hwdata_c(17), hwdata_c(16) => - hwdata_c(16), hwdata_c(15) => hwdata_c(15), hwdata_c(14) - => hwdata_c(14), hwdata_c(13) => hwdata_c(13), - hwdata_c(12) => hwdata_c(12), hwdata_c(11) => - hwdata_c(11), hwdata_c(10) => hwdata_c(10), hwdata_c(9) - => hwdata_c(9), hwdata_c(8) => hwdata_c(8), hwdata_c(7) - => hwdata_c(7), hwdata_c(6) => hwdata_c(6), hwdata_c(5) - => hwdata_c(5), hwdata_c(4) => hwdata_c(4), hwdata_c(3) - => hwdata_c(3), hwdata_c(2) => hwdata_c(2), hwdata_c(1) - => hwdata_c(1), hwdata_c(0) => hwdata_c(0), time_ren_1z - => time_ren, data_ren_1z => data_ren, un20_time_write - => un20_time_write, un13_time_write => un13_time_write, - HRESETn_c => HRESETn_c, lpp_waveform_fifo_VCC => - lpp_waveform_VCC, lpp_waveform_fifo_GND => - lpp_waveform_GND, HCLK_c => HCLK_c); - - lpp_waveform_snapshot_f0 : lpp_waveform_snapshot_160_11 - port map(sample_f0_wdata_95 => sample_f0_wdata_95, - sample_f0_wdata_94 => sample_f0_wdata_94, - sample_f0_wdata_93 => sample_f0_wdata_93, - sample_f0_wdata_92 => sample_f0_wdata_92, - sample_f0_wdata_91 => sample_f0_wdata_91, - sample_f0_wdata_90 => sample_f0_wdata_90, - sample_f0_wdata_89 => sample_f0_wdata_89, - sample_f0_wdata_88 => sample_f0_wdata_88, - sample_f0_wdata_87 => sample_f0_wdata_87, - sample_f0_wdata_86 => sample_f0_wdata_86, - sample_f0_wdata_85 => sample_f0_wdata_85, - sample_f0_wdata_84 => sample_f0_wdata_84, - sample_f0_wdata_83 => sample_f0_wdata_83, - sample_f0_wdata_82 => sample_f0_wdata_82, - sample_f0_wdata_81 => sample_f0_wdata_81, - sample_f0_wdata_80 => sample_f0_wdata_80, - sample_f0_wdata_79 => sample_f0_wdata_79, - sample_f0_wdata_78 => sample_f0_wdata_78, - sample_f0_wdata_77 => sample_f0_wdata_77, - sample_f0_wdata_76 => sample_f0_wdata_76, - sample_f0_wdata_75 => sample_f0_wdata_75, - sample_f0_wdata_74 => sample_f0_wdata_74, - sample_f0_wdata_73 => sample_f0_wdata_73, - sample_f0_wdata_72 => sample_f0_wdata_72, - sample_f0_wdata_71 => sample_f0_wdata_71, - sample_f0_wdata_70 => sample_f0_wdata_70, - sample_f0_wdata_69 => sample_f0_wdata_69, - sample_f0_wdata_68 => sample_f0_wdata_68, - sample_f0_wdata_67 => sample_f0_wdata_67, - sample_f0_wdata_66 => sample_f0_wdata_66, - sample_f0_wdata_65 => sample_f0_wdata_65, - sample_f0_wdata_64 => sample_f0_wdata_64, - sample_f0_wdata_63 => sample_f0_wdata_63, - sample_f0_wdata_62 => sample_f0_wdata_62, - sample_f0_wdata_61 => sample_f0_wdata_61, - sample_f0_wdata_60 => sample_f0_wdata_60, - sample_f0_wdata_59 => sample_f0_wdata_59, - sample_f0_wdata_58 => sample_f0_wdata_58, - sample_f0_wdata_57 => sample_f0_wdata_57, - sample_f0_wdata_56 => sample_f0_wdata_56, - sample_f0_wdata_55 => sample_f0_wdata_55, - sample_f0_wdata_54 => sample_f0_wdata_54, - sample_f0_wdata_53 => sample_f0_wdata_53, - sample_f0_wdata_52 => sample_f0_wdata_52, - sample_f0_wdata_51 => sample_f0_wdata_51, - sample_f0_wdata_50 => sample_f0_wdata_50, - sample_f0_wdata_49 => sample_f0_wdata_49, - sample_f0_wdata_48 => sample_f0_wdata_48, - sample_f0_wdata_15 => sample_f0_wdata_15, - sample_f0_wdata_14 => sample_f0_wdata_14, - sample_f0_wdata_13 => sample_f0_wdata_13, - sample_f0_wdata_12 => sample_f0_wdata_12, - sample_f0_wdata_11 => sample_f0_wdata_11, - sample_f0_wdata_10 => sample_f0_wdata_10, - sample_f0_wdata_9 => sample_f0_wdata_9, sample_f0_wdata_8 - => sample_f0_wdata_8, sample_f0_wdata_7 => - sample_f0_wdata_7, sample_f0_wdata_6 => sample_f0_wdata_6, - sample_f0_wdata_5 => sample_f0_wdata_5, sample_f0_wdata_4 - => sample_f0_wdata_4, sample_f0_wdata_3 => - sample_f0_wdata_3, sample_f0_wdata_2 => sample_f0_wdata_2, - sample_f0_wdata_1 => sample_f0_wdata_1, sample_f0_wdata_0 - => sample_f0_wdata_0, data_f0_out(159) => - \data_f0_out[159]\, data_f0_out(158) => - \data_f0_out[158]\, data_f0_out(157) => - \data_f0_out[157]\, data_f0_out(156) => - \data_f0_out[156]\, data_f0_out(155) => - \data_f0_out[155]\, data_f0_out(154) => - \data_f0_out[154]\, data_f0_out(153) => - \data_f0_out[153]\, data_f0_out(152) => - \data_f0_out[152]\, data_f0_out(151) => - \data_f0_out[151]\, data_f0_out(150) => - \data_f0_out[150]\, data_f0_out(149) => - \data_f0_out[149]\, data_f0_out(148) => - \data_f0_out[148]\, data_f0_out(147) => - \data_f0_out[147]\, data_f0_out(146) => - \data_f0_out[146]\, data_f0_out(145) => - \data_f0_out[145]\, data_f0_out(144) => - \data_f0_out[144]\, data_f0_out(143) => - \data_f0_out[143]\, data_f0_out(142) => - \data_f0_out[142]\, data_f0_out(141) => - \data_f0_out[141]\, data_f0_out(140) => - \data_f0_out[140]\, data_f0_out(139) => - \data_f0_out[139]\, data_f0_out(138) => - \data_f0_out[138]\, data_f0_out(137) => - \data_f0_out[137]\, data_f0_out(136) => - \data_f0_out[136]\, data_f0_out(135) => - \data_f0_out[135]\, data_f0_out(134) => - \data_f0_out[134]\, data_f0_out(133) => - \data_f0_out[133]\, data_f0_out(132) => - \data_f0_out[132]\, data_f0_out(131) => - \data_f0_out[131]\, data_f0_out(130) => - \data_f0_out[130]\, data_f0_out(129) => - \data_f0_out[129]\, data_f0_out(128) => - \data_f0_out[128]\, data_f0_out(127) => - \data_f0_out[127]\, data_f0_out(126) => - \data_f0_out[126]\, data_f0_out(125) => - \data_f0_out[125]\, data_f0_out(124) => - \data_f0_out[124]\, data_f0_out(123) => - \data_f0_out[123]\, data_f0_out(122) => - \data_f0_out[122]\, data_f0_out(121) => - \data_f0_out[121]\, data_f0_out(120) => - \data_f0_out[120]\, data_f0_out(119) => - \data_f0_out[119]\, data_f0_out(118) => - \data_f0_out[118]\, data_f0_out(117) => - \data_f0_out[117]\, data_f0_out(116) => - \data_f0_out[116]\, data_f0_out(115) => - \data_f0_out[115]\, data_f0_out(114) => - \data_f0_out[114]\, data_f0_out(113) => - \data_f0_out[113]\, data_f0_out(112) => - \data_f0_out[112]\, data_f0_out(111) => - \data_f0_out[111]\, data_f0_out(110) => - \data_f0_out[110]\, data_f0_out(109) => - \data_f0_out[109]\, data_f0_out(108) => - \data_f0_out[108]\, data_f0_out(107) => - \data_f0_out[107]\, data_f0_out(106) => - \data_f0_out[106]\, data_f0_out(105) => - \data_f0_out[105]\, data_f0_out(104) => - \data_f0_out[104]\, data_f0_out(103) => - \data_f0_out[103]\, data_f0_out(102) => - \data_f0_out[102]\, data_f0_out(101) => - \data_f0_out[101]\, data_f0_out(100) => - \data_f0_out[100]\, data_f0_out(99) => \data_f0_out[99]\, - data_f0_out(98) => \data_f0_out[98]\, data_f0_out(97) => - \data_f0_out[97]\, data_f0_out(96) => \data_f0_out[96]\, - data_f0_out(95) => \data_f0_out[95]\, data_f0_out(94) => - \data_f0_out[94]\, data_f0_out(93) => \data_f0_out[93]\, - data_f0_out(92) => \data_f0_out[92]\, data_f0_out(91) => - \data_f0_out[91]\, data_f0_out(90) => \data_f0_out[90]\, - data_f0_out(89) => \data_f0_out[89]\, data_f0_out(88) => - \data_f0_out[88]\, data_f0_out(87) => \data_f0_out[87]\, - data_f0_out(86) => \data_f0_out[86]\, data_f0_out(85) => - \data_f0_out[85]\, data_f0_out(84) => \data_f0_out[84]\, - data_f0_out(83) => \data_f0_out[83]\, data_f0_out(82) => - \data_f0_out[82]\, data_f0_out(81) => \data_f0_out[81]\, - data_f0_out(80) => \data_f0_out[80]\, data_f0_out(79) => - \data_f0_out[79]\, data_f0_out(78) => \data_f0_out[78]\, - data_f0_out(77) => \data_f0_out[77]\, data_f0_out(76) => - \data_f0_out[76]\, data_f0_out(75) => \data_f0_out[75]\, - data_f0_out(74) => \data_f0_out[74]\, data_f0_out(73) => - \data_f0_out[73]\, data_f0_out(72) => \data_f0_out[72]\, - data_f0_out(71) => \data_f0_out[71]\, data_f0_out(70) => - \data_f0_out[70]\, data_f0_out(69) => \data_f0_out[69]\, - data_f0_out(68) => \data_f0_out[68]\, data_f0_out(67) => - \data_f0_out[67]\, data_f0_out(66) => \data_f0_out[66]\, - data_f0_out(65) => \data_f0_out[65]\, data_f0_out(64) => - \data_f0_out[64]\, nb_snapshot_param(10) => - nb_snapshot_param(10), nb_snapshot_param(9) => - nb_snapshot_param(9), nb_snapshot_param(8) => - nb_snapshot_param(8), nb_snapshot_param(7) => - nb_snapshot_param(7), nb_snapshot_param(6) => - nb_snapshot_param(6), nb_snapshot_param(5) => - nb_snapshot_param(5), nb_snapshot_param(4) => - nb_snapshot_param(4), nb_snapshot_param(3) => - nb_snapshot_param(3), nb_snapshot_param(2) => - nb_snapshot_param(2), nb_snapshot_param(1) => - nb_snapshot_param(1), nb_snapshot_param(0) => - nb_snapshot_param(0), sample_f0_37 => sample_f0_37, - sample_f0_5 => sample_f0_5, sample_f0_38 => sample_f0_38, - sample_f0_6 => sample_f0_6, sample_f0_39 => sample_f0_39, - sample_f0_7 => sample_f0_7, sample_f0_40 => sample_f0_40, - sample_f0_8 => sample_f0_8, sample_f0_41 => sample_f0_41, - sample_f0_9 => sample_f0_9, sample_f0_42 => sample_f0_42, - sample_f0_10 => sample_f0_10, sample_f0_43 => - sample_f0_43, sample_f0_11 => sample_f0_11, sample_f0_61 - => sample_f0_61, sample_f0_62 => sample_f0_62, - sample_f0_63 => sample_f0_63, sample_f0_32 => - sample_f0_32, sample_f0_0 => sample_f0_0, sample_f0_33 - => sample_f0_33, sample_f0_1 => sample_f0_1, - sample_f0_34 => sample_f0_34, sample_f0_2 => sample_f0_2, - sample_f0_35 => sample_f0_35, sample_f0_3 => sample_f0_3, - sample_f0_36 => sample_f0_36, sample_f0_4 => sample_f0_4, - sample_f0_48 => sample_f0_48, sample_f0_49 => - sample_f0_49, sample_f0_50 => sample_f0_50, sample_f0_51 - => sample_f0_51, sample_f0_52 => sample_f0_52, - sample_f0_53 => sample_f0_53, sample_f0_54 => - sample_f0_54, sample_f0_55 => sample_f0_55, sample_f0_56 - => sample_f0_56, sample_f0_57 => sample_f0_57, - sample_f0_58 => sample_f0_58, sample_f0_59 => - sample_f0_59, sample_f0_60 => sample_f0_60, sample_f0_44 - => sample_f0_44, sample_f0_12 => sample_f0_12, - sample_f0_45 => sample_f0_45, sample_f0_13 => - sample_f0_13, sample_f0_46 => sample_f0_46, sample_f0_14 - => sample_f0_14, sample_f0_47 => sample_f0_47, - sample_f0_15 => sample_f0_15, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, data_f0_out_valid => data_f0_out_valid, - enable_f0 => enable_f0, data_shaping_R0 => - data_shaping_R0, data_shaping_R0_0 => data_shaping_R0_0, - start_snapshot_f0 => start_snapshot_f0, sample_f0_val_0 - => sample_f0_val_0, burst_f0 => burst_f0); - - un7_nb_snapshot_param_more_one_I_31 : XOR2 - port map(A => N_29, B => nb_snapshot_param(6), Y => I_31_5); - - lpp_waveform_snapshot_f2 : - lpp_waveform_snapshot_160_12_lpp_waveform_snapshot_f1_1 - port map(sample_f2_wdata(95) => sample_f2_wdata(95), - sample_f2_wdata(94) => sample_f2_wdata(94), - sample_f2_wdata(93) => sample_f2_wdata(93), - sample_f2_wdata(92) => sample_f2_wdata(92), - sample_f2_wdata(91) => sample_f2_wdata(91), - sample_f2_wdata(90) => sample_f2_wdata(90), - sample_f2_wdata(89) => sample_f2_wdata(89), - sample_f2_wdata(88) => sample_f2_wdata(88), - sample_f2_wdata(87) => sample_f2_wdata(87), - sample_f2_wdata(86) => sample_f2_wdata(86), - sample_f2_wdata(85) => sample_f2_wdata(85), - sample_f2_wdata(84) => sample_f2_wdata(84), - sample_f2_wdata(83) => sample_f2_wdata(83), - sample_f2_wdata(82) => sample_f2_wdata(82), - sample_f2_wdata(81) => sample_f2_wdata(81), - sample_f2_wdata(80) => sample_f2_wdata(80), - sample_f2_wdata(79) => sample_f2_wdata(79), - sample_f2_wdata(78) => sample_f2_wdata(78), - sample_f2_wdata(77) => sample_f2_wdata(77), - sample_f2_wdata(76) => sample_f2_wdata(76), - sample_f2_wdata(75) => sample_f2_wdata(75), - sample_f2_wdata(74) => sample_f2_wdata(74), - sample_f2_wdata(73) => sample_f2_wdata(73), - sample_f2_wdata(72) => sample_f2_wdata(72), - sample_f2_wdata(71) => sample_f2_wdata(71), - sample_f2_wdata(70) => sample_f2_wdata(70), - sample_f2_wdata(69) => sample_f2_wdata(69), - sample_f2_wdata(68) => sample_f2_wdata(68), - sample_f2_wdata(67) => sample_f2_wdata(67), - sample_f2_wdata(66) => sample_f2_wdata(66), - sample_f2_wdata(65) => sample_f2_wdata(65), - sample_f2_wdata(64) => sample_f2_wdata(64), - sample_f2_wdata(63) => sample_f2_wdata(63), - sample_f2_wdata(62) => sample_f2_wdata(62), - sample_f2_wdata(61) => sample_f2_wdata(61), - sample_f2_wdata(60) => sample_f2_wdata(60), - sample_f2_wdata(59) => sample_f2_wdata(59), - sample_f2_wdata(58) => sample_f2_wdata(58), - sample_f2_wdata(57) => sample_f2_wdata(57), - sample_f2_wdata(56) => sample_f2_wdata(56), - sample_f2_wdata(55) => sample_f2_wdata(55), - sample_f2_wdata(54) => sample_f2_wdata(54), - sample_f2_wdata(53) => sample_f2_wdata(53), - sample_f2_wdata(52) => sample_f2_wdata(52), - sample_f2_wdata(51) => sample_f2_wdata(51), - sample_f2_wdata(50) => sample_f2_wdata(50), - sample_f2_wdata(49) => sample_f2_wdata(49), - sample_f2_wdata(48) => sample_f2_wdata(48), - sample_f2_wdata(47) => sample_f2_wdata(47), - sample_f2_wdata(46) => sample_f2_wdata(46), - sample_f2_wdata(45) => sample_f2_wdata(45), - sample_f2_wdata(44) => sample_f2_wdata(44), - sample_f2_wdata(43) => sample_f2_wdata(43), - sample_f2_wdata(42) => sample_f2_wdata(42), - sample_f2_wdata(41) => sample_f2_wdata(41), - sample_f2_wdata(40) => sample_f2_wdata(40), - sample_f2_wdata(39) => sample_f2_wdata(39), - sample_f2_wdata(38) => sample_f2_wdata(38), - sample_f2_wdata(37) => sample_f2_wdata(37), - sample_f2_wdata(36) => sample_f2_wdata(36), - sample_f2_wdata(35) => sample_f2_wdata(35), - sample_f2_wdata(34) => sample_f2_wdata(34), - sample_f2_wdata(33) => sample_f2_wdata(33), - sample_f2_wdata(32) => sample_f2_wdata(32), - sample_f2_wdata(31) => sample_f2_wdata(31), - sample_f2_wdata(30) => sample_f2_wdata(30), - sample_f2_wdata(29) => sample_f2_wdata(29), - sample_f2_wdata(28) => sample_f2_wdata(28), - sample_f2_wdata(27) => sample_f2_wdata(27), - sample_f2_wdata(26) => sample_f2_wdata(26), - sample_f2_wdata(25) => sample_f2_wdata(25), - sample_f2_wdata(24) => sample_f2_wdata(24), - sample_f2_wdata(23) => sample_f2_wdata(23), - sample_f2_wdata(22) => sample_f2_wdata(22), - sample_f2_wdata(21) => sample_f2_wdata(21), - sample_f2_wdata(20) => sample_f2_wdata(20), - sample_f2_wdata(19) => sample_f2_wdata(19), - sample_f2_wdata(18) => sample_f2_wdata(18), - sample_f2_wdata(17) => sample_f2_wdata(17), - sample_f2_wdata(16) => sample_f2_wdata(16), - sample_f2_wdata(15) => sample_f2_wdata(15), - sample_f2_wdata(14) => sample_f2_wdata(14), - sample_f2_wdata(13) => sample_f2_wdata(13), - sample_f2_wdata(12) => sample_f2_wdata(12), - sample_f2_wdata(11) => sample_f2_wdata(11), - sample_f2_wdata(10) => sample_f2_wdata(10), - sample_f2_wdata(9) => sample_f2_wdata(9), - sample_f2_wdata(8) => sample_f2_wdata(8), - sample_f2_wdata(7) => sample_f2_wdata(7), - sample_f2_wdata(6) => sample_f2_wdata(6), - sample_f2_wdata(5) => sample_f2_wdata(5), - sample_f2_wdata(4) => sample_f2_wdata(4), - sample_f2_wdata(3) => sample_f2_wdata(3), - sample_f2_wdata(2) => sample_f2_wdata(2), - sample_f2_wdata(1) => sample_f2_wdata(1), - sample_f2_wdata(0) => sample_f2_wdata(0), - data_f2_out(159) => \data_f2_out[159]\, data_f2_out(158) - => \data_f2_out[158]\, data_f2_out(157) => - \data_f2_out[157]\, data_f2_out(156) => - \data_f2_out[156]\, data_f2_out(155) => - \data_f2_out[155]\, data_f2_out(154) => - \data_f2_out[154]\, data_f2_out(153) => - \data_f2_out[153]\, data_f2_out(152) => - \data_f2_out[152]\, data_f2_out(151) => - \data_f2_out[151]\, data_f2_out(150) => - \data_f2_out[150]\, data_f2_out(149) => - \data_f2_out[149]\, data_f2_out(148) => - \data_f2_out[148]\, data_f2_out(147) => - \data_f2_out[147]\, data_f2_out(146) => - \data_f2_out[146]\, data_f2_out(145) => - \data_f2_out[145]\, data_f2_out(144) => - \data_f2_out[144]\, data_f2_out(143) => - \data_f2_out[143]\, data_f2_out(142) => - \data_f2_out[142]\, data_f2_out(141) => - \data_f2_out[141]\, data_f2_out(140) => - \data_f2_out[140]\, data_f2_out(139) => - \data_f2_out[139]\, data_f2_out(138) => - \data_f2_out[138]\, data_f2_out(137) => - \data_f2_out[137]\, data_f2_out(136) => - \data_f2_out[136]\, data_f2_out(135) => - \data_f2_out[135]\, data_f2_out(134) => - \data_f2_out[134]\, data_f2_out(133) => - \data_f2_out[133]\, data_f2_out(132) => - \data_f2_out[132]\, data_f2_out(131) => - \data_f2_out[131]\, data_f2_out(130) => - \data_f2_out[130]\, data_f2_out(129) => - \data_f2_out[129]\, data_f2_out(128) => - \data_f2_out[128]\, data_f2_out(127) => - \data_f2_out[127]\, data_f2_out(126) => - \data_f2_out[126]\, data_f2_out(125) => - \data_f2_out[125]\, data_f2_out(124) => - \data_f2_out[124]\, data_f2_out(123) => - \data_f2_out[123]\, data_f2_out(122) => - \data_f2_out[122]\, data_f2_out(121) => - \data_f2_out[121]\, data_f2_out(120) => - \data_f2_out[120]\, data_f2_out(119) => - \data_f2_out[119]\, data_f2_out(118) => - \data_f2_out[118]\, data_f2_out(117) => - \data_f2_out[117]\, data_f2_out(116) => - \data_f2_out[116]\, data_f2_out(115) => - \data_f2_out[115]\, data_f2_out(114) => - \data_f2_out[114]\, data_f2_out(113) => - \data_f2_out[113]\, data_f2_out(112) => - \data_f2_out[112]\, data_f2_out(111) => - \data_f2_out[111]\, data_f2_out(110) => - \data_f2_out[110]\, data_f2_out(109) => - \data_f2_out[109]\, data_f2_out(108) => - \data_f2_out[108]\, data_f2_out(107) => - \data_f2_out[107]\, data_f2_out(106) => - \data_f2_out[106]\, data_f2_out(105) => - \data_f2_out[105]\, data_f2_out(104) => - \data_f2_out[104]\, data_f2_out(103) => - \data_f2_out[103]\, data_f2_out(102) => - \data_f2_out[102]\, data_f2_out(101) => - \data_f2_out[101]\, data_f2_out(100) => - \data_f2_out[100]\, data_f2_out(99) => \data_f2_out[99]\, - data_f2_out(98) => \data_f2_out[98]\, data_f2_out(97) => - \data_f2_out[97]\, data_f2_out(96) => \data_f2_out[96]\, - data_f2_out(95) => \data_f2_out[95]\, data_f2_out(94) => - \data_f2_out[94]\, data_f2_out(93) => \data_f2_out[93]\, - data_f2_out(92) => \data_f2_out[92]\, data_f2_out(91) => - \data_f2_out[91]\, data_f2_out(90) => \data_f2_out[90]\, - data_f2_out(89) => \data_f2_out[89]\, data_f2_out(88) => - \data_f2_out[88]\, data_f2_out(87) => \data_f2_out[87]\, - data_f2_out(86) => \data_f2_out[86]\, data_f2_out(85) => - \data_f2_out[85]\, data_f2_out(84) => \data_f2_out[84]\, - data_f2_out(83) => \data_f2_out[83]\, data_f2_out(82) => - \data_f2_out[82]\, data_f2_out(81) => \data_f2_out[81]\, - data_f2_out(80) => \data_f2_out[80]\, data_f2_out(79) => - \data_f2_out[79]\, data_f2_out(78) => \data_f2_out[78]\, - data_f2_out(77) => \data_f2_out[77]\, data_f2_out(76) => - \data_f2_out[76]\, data_f2_out(75) => \data_f2_out[75]\, - data_f2_out(74) => \data_f2_out[74]\, data_f2_out(73) => - \data_f2_out[73]\, data_f2_out(72) => \data_f2_out[72]\, - data_f2_out(71) => \data_f2_out[71]\, data_f2_out(70) => - \data_f2_out[70]\, data_f2_out(69) => \data_f2_out[69]\, - data_f2_out(68) => \data_f2_out[68]\, data_f2_out(67) => - \data_f2_out[67]\, data_f2_out(66) => \data_f2_out[66]\, - data_f2_out(65) => \data_f2_out[65]\, data_f2_out(64) => - \data_f2_out[64]\, nb_snapshot_param(0) => - nb_snapshot_param(0), HRESETn_c => HRESETn_c, HCLK_c => - HCLK_c, data_f2_out_valid => data_f2_out_valid, I_13_20 - => I_13_20, I_9_20 => I_9_20, I_5_20 => I_5_20, I_38_4 - => I_38_4, I_31_5 => I_31_5, N_4 => N_4, I_45_4 => - I_45_4, I_56_4 => I_56_4, I_52_4 => I_52_4, I_24_4 => - I_24_4, I_20_12 => I_20_12, enable_f2 => enable_f2, - burst_f2 => burst_f2, start_snapshot_f2 => - start_snapshot_f2, sample_f2_val => sample_f2_val); - - un7_nb_snapshot_param_more_one_I_12 : AND3 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), C => nb_snapshot_param(2), Y => - N_42); - - un7_nb_snapshot_param_more_one_I_5 : XOR2 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), Y => I_5_20); - - un7_nb_snapshot_param_more_one_I_51 : NOR2B - port map(A => nb_snapshot_param(8), B => \DWACT_FINC_E[4]\, - Y => N_14); - - pp_waveform_dma_1 : lpp_waveform_dma - port map(addr_data_f0(31) => addr_data_f0(31), - addr_data_f0(30) => addr_data_f0(30), addr_data_f0(29) - => addr_data_f0(29), addr_data_f0(28) => - addr_data_f0(28), addr_data_f0(27) => addr_data_f0(27), - addr_data_f0(26) => addr_data_f0(26), addr_data_f0(25) - => addr_data_f0(25), addr_data_f0(24) => - addr_data_f0(24), addr_data_f0(23) => addr_data_f0(23), - addr_data_f0(22) => addr_data_f0(22), addr_data_f0(21) - => addr_data_f0(21), addr_data_f0(20) => - addr_data_f0(20), addr_data_f0(19) => addr_data_f0(19), - addr_data_f0(18) => addr_data_f0(18), addr_data_f0(17) - => addr_data_f0(17), addr_data_f0(16) => - addr_data_f0(16), addr_data_f0(15) => addr_data_f0(15), - addr_data_f0(14) => addr_data_f0(14), addr_data_f0(13) - => addr_data_f0(13), addr_data_f0(12) => - addr_data_f0(12), addr_data_f0(11) => addr_data_f0(11), - addr_data_f0(10) => addr_data_f0(10), addr_data_f0(9) => - addr_data_f0(9), addr_data_f0(8) => addr_data_f0(8), - addr_data_f0(7) => addr_data_f0(7), addr_data_f0(6) => - addr_data_f0(6), addr_data_f0(5) => addr_data_f0(5), - addr_data_f0(4) => addr_data_f0(4), addr_data_f0(3) => - addr_data_f0(3), addr_data_f0(2) => addr_data_f0(2), - addr_data_f0(1) => addr_data_f0(1), addr_data_f0(0) => - addr_data_f0(0), addr_data_f1(31) => addr_data_f1(31), - addr_data_f1(30) => addr_data_f1(30), addr_data_f1(29) - => addr_data_f1(29), addr_data_f1(28) => - addr_data_f1(28), addr_data_f1(27) => addr_data_f1(27), - addr_data_f1(26) => addr_data_f1(26), addr_data_f1(25) - => addr_data_f1(25), addr_data_f1(24) => - addr_data_f1(24), addr_data_f1(23) => addr_data_f1(23), - addr_data_f1(22) => addr_data_f1(22), addr_data_f1(21) - => addr_data_f1(21), addr_data_f1(20) => - addr_data_f1(20), addr_data_f1(19) => addr_data_f1(19), - addr_data_f1(18) => addr_data_f1(18), addr_data_f1(17) - => addr_data_f1(17), addr_data_f1(16) => - addr_data_f1(16), addr_data_f1(15) => addr_data_f1(15), - addr_data_f1(14) => addr_data_f1(14), addr_data_f1(13) - => addr_data_f1(13), addr_data_f1(12) => - addr_data_f1(12), addr_data_f1(11) => addr_data_f1(11), - addr_data_f1(10) => addr_data_f1(10), addr_data_f1(9) => - addr_data_f1(9), addr_data_f1(8) => addr_data_f1(8), - addr_data_f1(7) => addr_data_f1(7), addr_data_f1(6) => - addr_data_f1(6), addr_data_f1(5) => addr_data_f1(5), - addr_data_f1(4) => addr_data_f1(4), addr_data_f1(3) => - addr_data_f1(3), addr_data_f1(2) => addr_data_f1(2), - addr_data_f1(1) => addr_data_f1(1), addr_data_f1(0) => - addr_data_f1(0), addr_data_f2(31) => addr_data_f2(31), - addr_data_f2(30) => addr_data_f2(30), addr_data_f2(29) - => addr_data_f2(29), addr_data_f2(28) => - addr_data_f2(28), addr_data_f2(27) => addr_data_f2(27), - addr_data_f2(26) => addr_data_f2(26), addr_data_f2(25) - => addr_data_f2(25), addr_data_f2(24) => - addr_data_f2(24), addr_data_f2(23) => addr_data_f2(23), - addr_data_f2(22) => addr_data_f2(22), addr_data_f2(21) - => addr_data_f2(21), addr_data_f2(20) => - addr_data_f2(20), addr_data_f2(19) => addr_data_f2(19), - addr_data_f2(18) => addr_data_f2(18), addr_data_f2(17) - => addr_data_f2(17), addr_data_f2(16) => - addr_data_f2(16), addr_data_f2(15) => addr_data_f2(15), - addr_data_f2(14) => addr_data_f2(14), addr_data_f2(13) - => addr_data_f2(13), addr_data_f2(12) => - addr_data_f2(12), addr_data_f2(11) => addr_data_f2(11), - addr_data_f2(10) => addr_data_f2(10), addr_data_f2(9) => - addr_data_f2(9), addr_data_f2(8) => addr_data_f2(8), - addr_data_f2(7) => addr_data_f2(7), addr_data_f2(6) => - addr_data_f2(6), addr_data_f2(5) => addr_data_f2(5), - addr_data_f2(4) => addr_data_f2(4), addr_data_f2(3) => - addr_data_f2(3), addr_data_f2(2) => addr_data_f2(2), - addr_data_f2(1) => addr_data_f2(1), addr_data_f2(0) => - addr_data_f2(0), addr_data_f3(31) => addr_data_f3(31), - addr_data_f3(30) => addr_data_f3(30), addr_data_f3(29) - => addr_data_f3(29), addr_data_f3(28) => - addr_data_f3(28), addr_data_f3(27) => addr_data_f3(27), - addr_data_f3(26) => addr_data_f3(26), addr_data_f3(25) - => addr_data_f3(25), addr_data_f3(24) => - addr_data_f3(24), addr_data_f3(23) => addr_data_f3(23), - addr_data_f3(22) => addr_data_f3(22), addr_data_f3(21) - => addr_data_f3(21), addr_data_f3(20) => - addr_data_f3(20), addr_data_f3(19) => addr_data_f3(19), - addr_data_f3(18) => addr_data_f3(18), addr_data_f3(17) - => addr_data_f3(17), addr_data_f3(16) => - addr_data_f3(16), addr_data_f3(15) => addr_data_f3(15), - addr_data_f3(14) => addr_data_f3(14), addr_data_f3(13) - => addr_data_f3(13), addr_data_f3(12) => - addr_data_f3(12), addr_data_f3(11) => addr_data_f3(11), - addr_data_f3(10) => addr_data_f3(10), addr_data_f3(9) => - addr_data_f3(9), addr_data_f3(8) => addr_data_f3(8), - addr_data_f3(7) => addr_data_f3(7), addr_data_f3(6) => - addr_data_f3(6), addr_data_f3(5) => addr_data_f3(5), - addr_data_f3(4) => addr_data_f3(4), addr_data_f3(3) => - addr_data_f3(3), addr_data_f3(2) => addr_data_f3(2), - addr_data_f3(1) => addr_data_f3(1), addr_data_f3(0) => - addr_data_f3(0), status_full(3) => status_full(3), - status_full(2) => status_full(2), status_full(1) => - status_full(1), status_full(0) => status_full(0), - status_full_err(3) => status_full_err(3), - status_full_err(2) => status_full_err(2), - status_full_err(1) => status_full_err(1), - status_full_err(0) => status_full_err(0), - nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - haddr_c(31) => haddr_c(31), haddr_c(30) => haddr_c(30), - haddr_c(29) => haddr_c(29), haddr_c(28) => haddr_c(28), - haddr_c(27) => haddr_c(27), haddr_c(26) => haddr_c(26), - haddr_c(25) => haddr_c(25), haddr_c(24) => haddr_c(24), - haddr_c(23) => haddr_c(23), haddr_c(22) => haddr_c(22), - haddr_c(21) => haddr_c(21), haddr_c(20) => haddr_c(20), - haddr_c(19) => haddr_c(19), haddr_c(18) => haddr_c(18), - haddr_c(17) => haddr_c(17), haddr_c(16) => haddr_c(16), - haddr_c(15) => haddr_c(15), haddr_c(14) => haddr_c(14), - haddr_c(13) => haddr_c(13), haddr_c(12) => haddr_c(12), - haddr_c(11) => haddr_c(11), haddr_c(10) => haddr_c(10), - haddr_c(9) => haddr_c(9), haddr_c(8) => haddr_c(8), - haddr_c(7) => haddr_c(7), haddr_c(6) => haddr_c(6), - haddr_c(5) => haddr_c(5), haddr_c(4) => haddr_c(4), - haddr_c(3) => haddr_c(3), haddr_c(2) => haddr_c(2), - haddr_c(1) => haddr_c(1), haddr_c(0) => haddr_c(0), - AHB_Master_In_c_3 => AHB_Master_In_c_3, AHB_Master_In_c_0 - => AHB_Master_In_c_0, AHB_Master_In_c_4 => - AHB_Master_In_c_4, AHB_Master_In_c_5 => AHB_Master_In_c_5, - hsize_c(1) => hsize_c(1), hsize_c(0) => hsize_c(0), - htrans_c(1) => htrans_c(1), htrans_c(0) => htrans_c(0), - hburst_c(2) => hburst_c(2), hburst_c(1) => hburst_c(1), - hburst_c(0) => hburst_c(0), status_full_ack(3) => - status_full_ack(3), status_full_ack(2) => - status_full_ack(2), status_full_ack(1) => - status_full_ack(1), status_full_ack(0) => - status_full_ack(0), ready_i_0(3) => \ready_i_0[3]\, - ready_i_0(2) => \ready_i_0[2]\, ready_i_0(1) => - \ready_i_0[1]\, ready_i_0(0) => \ready_i_0[0]\, - data_ren(3) => \data_ren[3]\, data_ren(2) => - \data_ren[2]\, data_ren(1) => \data_ren[1]\, data_ren(0) - => \data_ren[0]\, time_ren(3) => \time_ren[3]\, - time_ren(2) => \time_ren[2]\, time_ren(1) => - \time_ren[1]\, time_ren(0) => \time_ren[0]\, time_ren_1z - => time_ren, data_ren_1z => data_ren, N_43 => N_43, - IdlePhase_RNI03G71 => IdlePhase_RNI03G71, hwrite_c => - hwrite_c, un20_time_write => un20_time_write, - un13_time_write => un13_time_write, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c); - - lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter - port map(wdata(31) => \wdata[31]\, wdata(30) => \wdata[30]\, - wdata(29) => \wdata[29]\, wdata(28) => \wdata[28]\, - wdata(27) => \wdata[27]\, wdata(26) => \wdata[26]\, - wdata(25) => \wdata[25]\, wdata(24) => \wdata[24]\, - wdata(23) => \wdata[23]\, wdata(22) => \wdata[22]\, - wdata(21) => \wdata[21]\, wdata(20) => \wdata[20]\, - wdata(19) => \wdata[19]\, wdata(18) => \wdata[18]\, - wdata(17) => \wdata[17]\, wdata(16) => \wdata[16]\, - wdata(15) => \wdata[15]\, wdata(14) => \wdata[14]\, - wdata(13) => \wdata[13]\, wdata(12) => \wdata[12]\, - wdata(11) => \wdata[11]\, wdata(10) => \wdata[10]\, - wdata(9) => \wdata[9]\, wdata(8) => \wdata[8]\, wdata(7) - => \wdata[7]\, wdata(6) => \wdata[6]\, wdata(5) => - \wdata[5]\, wdata(4) => \wdata[4]\, wdata(3) => - \wdata[3]\, wdata(2) => \wdata[2]\, wdata(1) => - \wdata[1]\, wdata(0) => \wdata[0]\, data_wen(3) => - \data_wen[3]\, data_wen(2) => \data_wen[2]\, data_wen(1) - => \data_wen[1]\, data_wen(0) => \data_wen[0]\, - valid_ack(3) => \valid_ack[3]\, valid_ack(2) => - \valid_ack[2]\, valid_ack(1) => \valid_ack[1]\, - valid_ack(0) => \valid_ack[0]\, time_wen(3) => - \time_wen[3]\, time_wen(2) => \time_wen[2]\, time_wen(1) - => \time_wen[1]\, time_wen(0) => \time_wen[0]\, - data_f3_out(159) => \data_f3_out[159]\, data_f3_out(158) - => \data_f3_out[158]\, data_f3_out(157) => - \data_f3_out[157]\, data_f3_out(156) => - \data_f3_out[156]\, data_f3_out(155) => - \data_f3_out[155]\, data_f3_out(154) => - \data_f3_out[154]\, data_f3_out(153) => - \data_f3_out[153]\, data_f3_out(152) => - \data_f3_out[152]\, data_f3_out(151) => - \data_f3_out[151]\, data_f3_out(150) => - \data_f3_out[150]\, data_f3_out(149) => - \data_f3_out[149]\, data_f3_out(148) => - \data_f3_out[148]\, data_f3_out(147) => - \data_f3_out[147]\, data_f3_out(146) => - \data_f3_out[146]\, data_f3_out(145) => - \data_f3_out[145]\, data_f3_out(144) => - \data_f3_out[144]\, data_f3_out(143) => - \data_f3_out[143]\, data_f3_out(142) => - \data_f3_out[142]\, data_f3_out(141) => - \data_f3_out[141]\, data_f3_out(140) => - \data_f3_out[140]\, data_f3_out(139) => - \data_f3_out[139]\, data_f3_out(138) => - \data_f3_out[138]\, data_f3_out(137) => - \data_f3_out[137]\, data_f3_out(136) => - \data_f3_out[136]\, data_f3_out(135) => - \data_f3_out[135]\, data_f3_out(134) => - \data_f3_out[134]\, data_f3_out(133) => - \data_f3_out[133]\, data_f3_out(132) => - \data_f3_out[132]\, data_f3_out(131) => - \data_f3_out[131]\, data_f3_out(130) => - \data_f3_out[130]\, data_f3_out(129) => - \data_f3_out[129]\, data_f3_out(128) => - \data_f3_out[128]\, data_f3_out(127) => - \data_f3_out[127]\, data_f3_out(126) => - \data_f3_out[126]\, data_f3_out(125) => - \data_f3_out[125]\, data_f3_out(124) => - \data_f3_out[124]\, data_f3_out(123) => - \data_f3_out[123]\, data_f3_out(122) => - \data_f3_out[122]\, data_f3_out(121) => - \data_f3_out[121]\, data_f3_out(120) => - \data_f3_out[120]\, data_f3_out(119) => - \data_f3_out[119]\, data_f3_out(118) => - \data_f3_out[118]\, data_f3_out(117) => - \data_f3_out[117]\, data_f3_out(116) => - \data_f3_out[116]\, data_f3_out(115) => - \data_f3_out[115]\, data_f3_out(114) => - \data_f3_out[114]\, data_f3_out(113) => - \data_f3_out[113]\, data_f3_out(112) => - \data_f3_out[112]\, data_f3_out(111) => - \data_f3_out[111]\, data_f3_out(110) => - \data_f3_out[110]\, data_f3_out(109) => - \data_f3_out[109]\, data_f3_out(108) => - \data_f3_out[108]\, data_f3_out(107) => - \data_f3_out[107]\, data_f3_out(106) => - \data_f3_out[106]\, data_f3_out(105) => - \data_f3_out[105]\, data_f3_out(104) => - \data_f3_out[104]\, data_f3_out(103) => - \data_f3_out[103]\, data_f3_out(102) => - \data_f3_out[102]\, data_f3_out(101) => - \data_f3_out[101]\, data_f3_out(100) => - \data_f3_out[100]\, data_f3_out(99) => \data_f3_out[99]\, - data_f3_out(98) => \data_f3_out[98]\, data_f3_out(97) => - \data_f3_out[97]\, data_f3_out(96) => \data_f3_out[96]\, - data_f3_out(95) => \data_f3_out[95]\, data_f3_out(94) => - \data_f3_out[94]\, data_f3_out(93) => \data_f3_out[93]\, - data_f3_out(92) => \data_f3_out[92]\, data_f3_out(91) => - \data_f3_out[91]\, data_f3_out(90) => \data_f3_out[90]\, - data_f3_out(89) => \data_f3_out[89]\, data_f3_out(88) => - \data_f3_out[88]\, data_f3_out(87) => \data_f3_out[87]\, - data_f3_out(86) => \data_f3_out[86]\, data_f3_out(85) => - \data_f3_out[85]\, data_f3_out(84) => \data_f3_out[84]\, - data_f3_out(83) => \data_f3_out[83]\, data_f3_out(82) => - \data_f3_out[82]\, data_f3_out(81) => \data_f3_out[81]\, - data_f3_out(80) => \data_f3_out[80]\, data_f3_out(79) => - \data_f3_out[79]\, data_f3_out(78) => \data_f3_out[78]\, - data_f3_out(77) => \data_f3_out[77]\, data_f3_out(76) => - \data_f3_out[76]\, data_f3_out(75) => \data_f3_out[75]\, - data_f3_out(74) => \data_f3_out[74]\, data_f3_out(73) => - \data_f3_out[73]\, data_f3_out(72) => \data_f3_out[72]\, - data_f3_out(71) => \data_f3_out[71]\, data_f3_out(70) => - \data_f3_out[70]\, data_f3_out(69) => \data_f3_out[69]\, - data_f3_out(68) => \data_f3_out[68]\, data_f3_out(67) => - \data_f3_out[67]\, data_f3_out(66) => \data_f3_out[66]\, - data_f3_out(65) => \data_f3_out[65]\, data_f3_out(64) => - \data_f3_out[64]\, data_f2_out(159) => \data_f2_out[159]\, - data_f2_out(158) => \data_f2_out[158]\, data_f2_out(157) - => \data_f2_out[157]\, data_f2_out(156) => - \data_f2_out[156]\, data_f2_out(155) => - \data_f2_out[155]\, data_f2_out(154) => - \data_f2_out[154]\, data_f2_out(153) => - \data_f2_out[153]\, data_f2_out(152) => - \data_f2_out[152]\, data_f2_out(151) => - \data_f2_out[151]\, data_f2_out(150) => - \data_f2_out[150]\, data_f2_out(149) => - \data_f2_out[149]\, data_f2_out(148) => - \data_f2_out[148]\, data_f2_out(147) => - \data_f2_out[147]\, data_f2_out(146) => - \data_f2_out[146]\, data_f2_out(145) => - \data_f2_out[145]\, data_f2_out(144) => - \data_f2_out[144]\, data_f2_out(143) => - \data_f2_out[143]\, data_f2_out(142) => - \data_f2_out[142]\, data_f2_out(141) => - \data_f2_out[141]\, data_f2_out(140) => - \data_f2_out[140]\, data_f2_out(139) => - \data_f2_out[139]\, data_f2_out(138) => - \data_f2_out[138]\, data_f2_out(137) => - \data_f2_out[137]\, data_f2_out(136) => - \data_f2_out[136]\, data_f2_out(135) => - \data_f2_out[135]\, data_f2_out(134) => - \data_f2_out[134]\, data_f2_out(133) => - \data_f2_out[133]\, data_f2_out(132) => - \data_f2_out[132]\, data_f2_out(131) => - \data_f2_out[131]\, data_f2_out(130) => - \data_f2_out[130]\, data_f2_out(129) => - \data_f2_out[129]\, data_f2_out(128) => - \data_f2_out[128]\, data_f2_out(127) => - \data_f2_out[127]\, data_f2_out(126) => - \data_f2_out[126]\, data_f2_out(125) => - \data_f2_out[125]\, data_f2_out(124) => - \data_f2_out[124]\, data_f2_out(123) => - \data_f2_out[123]\, data_f2_out(122) => - \data_f2_out[122]\, data_f2_out(121) => - \data_f2_out[121]\, data_f2_out(120) => - \data_f2_out[120]\, data_f2_out(119) => - \data_f2_out[119]\, data_f2_out(118) => - \data_f2_out[118]\, data_f2_out(117) => - \data_f2_out[117]\, data_f2_out(116) => - \data_f2_out[116]\, data_f2_out(115) => - \data_f2_out[115]\, data_f2_out(114) => - \data_f2_out[114]\, data_f2_out(113) => - \data_f2_out[113]\, data_f2_out(112) => - \data_f2_out[112]\, data_f2_out(111) => - \data_f2_out[111]\, data_f2_out(110) => - \data_f2_out[110]\, data_f2_out(109) => - \data_f2_out[109]\, data_f2_out(108) => - \data_f2_out[108]\, data_f2_out(107) => - \data_f2_out[107]\, data_f2_out(106) => - \data_f2_out[106]\, data_f2_out(105) => - \data_f2_out[105]\, data_f2_out(104) => - \data_f2_out[104]\, data_f2_out(103) => - \data_f2_out[103]\, data_f2_out(102) => - \data_f2_out[102]\, data_f2_out(101) => - \data_f2_out[101]\, data_f2_out(100) => - \data_f2_out[100]\, data_f2_out(99) => \data_f2_out[99]\, - data_f2_out(98) => \data_f2_out[98]\, data_f2_out(97) => - \data_f2_out[97]\, data_f2_out(96) => \data_f2_out[96]\, - data_f2_out(95) => \data_f2_out[95]\, data_f2_out(94) => - \data_f2_out[94]\, data_f2_out(93) => \data_f2_out[93]\, - data_f2_out(92) => \data_f2_out[92]\, data_f2_out(91) => - \data_f2_out[91]\, data_f2_out(90) => \data_f2_out[90]\, - data_f2_out(89) => \data_f2_out[89]\, data_f2_out(88) => - \data_f2_out[88]\, data_f2_out(87) => \data_f2_out[87]\, - data_f2_out(86) => \data_f2_out[86]\, data_f2_out(85) => - \data_f2_out[85]\, data_f2_out(84) => \data_f2_out[84]\, - data_f2_out(83) => \data_f2_out[83]\, data_f2_out(82) => - \data_f2_out[82]\, data_f2_out(81) => \data_f2_out[81]\, - data_f2_out(80) => \data_f2_out[80]\, data_f2_out(79) => - \data_f2_out[79]\, data_f2_out(78) => \data_f2_out[78]\, - data_f2_out(77) => \data_f2_out[77]\, data_f2_out(76) => - \data_f2_out[76]\, data_f2_out(75) => \data_f2_out[75]\, - data_f2_out(74) => \data_f2_out[74]\, data_f2_out(73) => - \data_f2_out[73]\, data_f2_out(72) => \data_f2_out[72]\, - data_f2_out(71) => \data_f2_out[71]\, data_f2_out(70) => - \data_f2_out[70]\, data_f2_out(69) => \data_f2_out[69]\, - data_f2_out(68) => \data_f2_out[68]\, data_f2_out(67) => - \data_f2_out[67]\, data_f2_out(66) => \data_f2_out[66]\, - data_f2_out(65) => \data_f2_out[65]\, data_f2_out(64) => - \data_f2_out[64]\, data_f1_out(159) => \data_f1_out[159]\, - data_f1_out(158) => \data_f1_out[158]\, data_f1_out(157) - => \data_f1_out[157]\, data_f1_out(156) => - \data_f1_out[156]\, data_f1_out(155) => - \data_f1_out[155]\, data_f1_out(154) => - \data_f1_out[154]\, data_f1_out(153) => - \data_f1_out[153]\, data_f1_out(152) => - \data_f1_out[152]\, data_f1_out(151) => - \data_f1_out[151]\, data_f1_out(150) => - \data_f1_out[150]\, data_f1_out(149) => - \data_f1_out[149]\, data_f1_out(148) => - \data_f1_out[148]\, data_f1_out(147) => - \data_f1_out[147]\, data_f1_out(146) => - \data_f1_out[146]\, data_f1_out(145) => - \data_f1_out[145]\, data_f1_out(144) => - \data_f1_out[144]\, data_f1_out(143) => - \data_f1_out[143]\, data_f1_out(142) => - \data_f1_out[142]\, data_f1_out(141) => - \data_f1_out[141]\, data_f1_out(140) => - \data_f1_out[140]\, data_f1_out(139) => - \data_f1_out[139]\, data_f1_out(138) => - \data_f1_out[138]\, data_f1_out(137) => - \data_f1_out[137]\, data_f1_out(136) => - \data_f1_out[136]\, data_f1_out(135) => - \data_f1_out[135]\, data_f1_out(134) => - \data_f1_out[134]\, data_f1_out(133) => - \data_f1_out[133]\, data_f1_out(132) => - \data_f1_out[132]\, data_f1_out(131) => - \data_f1_out[131]\, data_f1_out(130) => - \data_f1_out[130]\, data_f1_out(129) => - \data_f1_out[129]\, data_f1_out(128) => - \data_f1_out[128]\, data_f1_out(127) => - \data_f1_out[127]\, data_f1_out(126) => - \data_f1_out[126]\, data_f1_out(125) => - \data_f1_out[125]\, data_f1_out(124) => - \data_f1_out[124]\, data_f1_out(123) => - \data_f1_out[123]\, data_f1_out(122) => - \data_f1_out[122]\, data_f1_out(121) => - \data_f1_out[121]\, data_f1_out(120) => - \data_f1_out[120]\, data_f1_out(119) => - \data_f1_out[119]\, data_f1_out(118) => - \data_f1_out[118]\, data_f1_out(117) => - \data_f1_out[117]\, data_f1_out(116) => - \data_f1_out[116]\, data_f1_out(115) => - \data_f1_out[115]\, data_f1_out(114) => - \data_f1_out[114]\, data_f1_out(113) => - \data_f1_out[113]\, data_f1_out(112) => - \data_f1_out[112]\, data_f1_out(111) => - \data_f1_out[111]\, data_f1_out(110) => - \data_f1_out[110]\, data_f1_out(109) => - \data_f1_out[109]\, data_f1_out(108) => - \data_f1_out[108]\, data_f1_out(107) => - \data_f1_out[107]\, data_f1_out(106) => - \data_f1_out[106]\, data_f1_out(105) => - \data_f1_out[105]\, data_f1_out(104) => - \data_f1_out[104]\, data_f1_out(103) => - \data_f1_out[103]\, data_f1_out(102) => - \data_f1_out[102]\, data_f1_out(101) => - \data_f1_out[101]\, data_f1_out(100) => - \data_f1_out[100]\, data_f1_out(99) => \data_f1_out[99]\, - data_f1_out(98) => \data_f1_out[98]\, data_f1_out(97) => - \data_f1_out[97]\, data_f1_out(96) => \data_f1_out[96]\, - data_f1_out(95) => \data_f1_out[95]\, data_f1_out(94) => - \data_f1_out[94]\, data_f1_out(93) => \data_f1_out[93]\, - data_f1_out(92) => \data_f1_out[92]\, data_f1_out(91) => - \data_f1_out[91]\, data_f1_out(90) => \data_f1_out[90]\, - data_f1_out(89) => \data_f1_out[89]\, data_f1_out(88) => - \data_f1_out[88]\, data_f1_out(87) => \data_f1_out[87]\, - data_f1_out(86) => \data_f1_out[86]\, data_f1_out(85) => - \data_f1_out[85]\, data_f1_out(84) => \data_f1_out[84]\, - data_f1_out(83) => \data_f1_out[83]\, data_f1_out(82) => - \data_f1_out[82]\, data_f1_out(81) => \data_f1_out[81]\, - data_f1_out(80) => \data_f1_out[80]\, data_f1_out(79) => - \data_f1_out[79]\, data_f1_out(78) => \data_f1_out[78]\, - data_f1_out(77) => \data_f1_out[77]\, data_f1_out(76) => - \data_f1_out[76]\, data_f1_out(75) => \data_f1_out[75]\, - data_f1_out(74) => \data_f1_out[74]\, data_f1_out(73) => - \data_f1_out[73]\, data_f1_out(72) => \data_f1_out[72]\, - data_f1_out(71) => \data_f1_out[71]\, data_f1_out(70) => - \data_f1_out[70]\, data_f1_out(69) => \data_f1_out[69]\, - data_f1_out(68) => \data_f1_out[68]\, data_f1_out(67) => - \data_f1_out[67]\, data_f1_out(66) => \data_f1_out[66]\, - data_f1_out(65) => \data_f1_out[65]\, data_f1_out(64) => - \data_f1_out[64]\, data_f0_out(159) => \data_f0_out[159]\, - data_f0_out(158) => \data_f0_out[158]\, data_f0_out(157) - => \data_f0_out[157]\, data_f0_out(156) => - \data_f0_out[156]\, data_f0_out(155) => - \data_f0_out[155]\, data_f0_out(154) => - \data_f0_out[154]\, data_f0_out(153) => - \data_f0_out[153]\, data_f0_out(152) => - \data_f0_out[152]\, data_f0_out(151) => - \data_f0_out[151]\, data_f0_out(150) => - \data_f0_out[150]\, data_f0_out(149) => - \data_f0_out[149]\, data_f0_out(148) => - \data_f0_out[148]\, data_f0_out(147) => - \data_f0_out[147]\, data_f0_out(146) => - \data_f0_out[146]\, data_f0_out(145) => - \data_f0_out[145]\, data_f0_out(144) => - \data_f0_out[144]\, data_f0_out(143) => - \data_f0_out[143]\, data_f0_out(142) => - \data_f0_out[142]\, data_f0_out(141) => - \data_f0_out[141]\, data_f0_out(140) => - \data_f0_out[140]\, data_f0_out(139) => - \data_f0_out[139]\, data_f0_out(138) => - \data_f0_out[138]\, data_f0_out(137) => - \data_f0_out[137]\, data_f0_out(136) => - \data_f0_out[136]\, data_f0_out(135) => - \data_f0_out[135]\, data_f0_out(134) => - \data_f0_out[134]\, data_f0_out(133) => - \data_f0_out[133]\, data_f0_out(132) => - \data_f0_out[132]\, data_f0_out(131) => - \data_f0_out[131]\, data_f0_out(130) => - \data_f0_out[130]\, data_f0_out(129) => - \data_f0_out[129]\, data_f0_out(128) => - \data_f0_out[128]\, data_f0_out(127) => - \data_f0_out[127]\, data_f0_out(126) => - \data_f0_out[126]\, data_f0_out(125) => - \data_f0_out[125]\, data_f0_out(124) => - \data_f0_out[124]\, data_f0_out(123) => - \data_f0_out[123]\, data_f0_out(122) => - \data_f0_out[122]\, data_f0_out(121) => - \data_f0_out[121]\, data_f0_out(120) => - \data_f0_out[120]\, data_f0_out(119) => - \data_f0_out[119]\, data_f0_out(118) => - \data_f0_out[118]\, data_f0_out(117) => - \data_f0_out[117]\, data_f0_out(116) => - \data_f0_out[116]\, data_f0_out(115) => - \data_f0_out[115]\, data_f0_out(114) => - \data_f0_out[114]\, data_f0_out(113) => - \data_f0_out[113]\, data_f0_out(112) => - \data_f0_out[112]\, data_f0_out(111) => - \data_f0_out[111]\, data_f0_out(110) => - \data_f0_out[110]\, data_f0_out(109) => - \data_f0_out[109]\, data_f0_out(108) => - \data_f0_out[108]\, data_f0_out(107) => - \data_f0_out[107]\, data_f0_out(106) => - \data_f0_out[106]\, data_f0_out(105) => - \data_f0_out[105]\, data_f0_out(104) => - \data_f0_out[104]\, data_f0_out(103) => - \data_f0_out[103]\, data_f0_out(102) => - \data_f0_out[102]\, data_f0_out(101) => - \data_f0_out[101]\, data_f0_out(100) => - \data_f0_out[100]\, data_f0_out(99) => \data_f0_out[99]\, - data_f0_out(98) => \data_f0_out[98]\, data_f0_out(97) => - \data_f0_out[97]\, data_f0_out(96) => \data_f0_out[96]\, - data_f0_out(95) => \data_f0_out[95]\, data_f0_out(94) => - \data_f0_out[94]\, data_f0_out(93) => \data_f0_out[93]\, - data_f0_out(92) => \data_f0_out[92]\, data_f0_out(91) => - \data_f0_out[91]\, data_f0_out(90) => \data_f0_out[90]\, - data_f0_out(89) => \data_f0_out[89]\, data_f0_out(88) => - \data_f0_out[88]\, data_f0_out(87) => \data_f0_out[87]\, - data_f0_out(86) => \data_f0_out[86]\, data_f0_out(85) => - \data_f0_out[85]\, data_f0_out(84) => \data_f0_out[84]\, - data_f0_out(83) => \data_f0_out[83]\, data_f0_out(82) => - \data_f0_out[82]\, data_f0_out(81) => \data_f0_out[81]\, - data_f0_out(80) => \data_f0_out[80]\, data_f0_out(79) => - \data_f0_out[79]\, data_f0_out(78) => \data_f0_out[78]\, - data_f0_out(77) => \data_f0_out[77]\, data_f0_out(76) => - \data_f0_out[76]\, data_f0_out(75) => \data_f0_out[75]\, - data_f0_out(74) => \data_f0_out[74]\, data_f0_out(73) => - \data_f0_out[73]\, data_f0_out(72) => \data_f0_out[72]\, - data_f0_out(71) => \data_f0_out[71]\, data_f0_out(70) => - \data_f0_out[70]\, data_f0_out(69) => \data_f0_out[69]\, - data_f0_out(68) => \data_f0_out[68]\, data_f0_out(67) => - \data_f0_out[67]\, data_f0_out(66) => \data_f0_out[66]\, - data_f0_out(65) => \data_f0_out[65]\, data_f0_out(64) => - \data_f0_out[64]\, valid_out_i(1) => \valid_out_i[1]\, - ready_i_0(3) => \ready_i_0[3]\, ready_i_0(2) => - \ready_i_0[2]\, ready_i_0(1) => \ready_i_0[1]\, - ready_i_0(0) => \ready_i_0[0]\, valid_out_3 => - \valid_out[3]\, valid_out_2 => \valid_out[2]\, - valid_out_0 => \valid_out[0]\, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_8_16_4 is - - port( sample_f0_0 : out std_logic; - sample_f0_1 : out std_logic; - sample_f0_2 : out std_logic; - sample_f0_3 : out std_logic; - sample_f0_4 : out std_logic; - sample_f0_5 : out std_logic; - sample_f0_6 : out std_logic; - sample_f0_7 : out std_logic; - sample_f0_8 : out std_logic; - sample_f0_9 : out std_logic; - sample_f0_10 : out std_logic; - sample_f0_11 : out std_logic; - sample_f0_12 : out std_logic; - sample_f0_13 : out std_logic; - sample_f0_14 : out std_logic; - sample_f0_15 : out std_logic; - sample_f0_32 : out std_logic; - sample_f0_33 : out std_logic; - sample_f0_34 : out std_logic; - sample_f0_35 : out std_logic; - sample_f0_36 : out std_logic; - sample_f0_37 : out std_logic; - sample_f0_38 : out std_logic; - sample_f0_39 : out std_logic; - sample_f0_40 : out std_logic; - sample_f0_41 : out std_logic; - sample_f0_42 : out std_logic; - sample_f0_43 : out std_logic; - sample_f0_44 : out std_logic; - sample_f0_45 : out std_logic; - sample_f0_46 : out std_logic; - sample_f0_47 : out std_logic; - sample_f0_48 : out std_logic; - sample_f0_49 : out std_logic; - sample_f0_50 : out std_logic; - sample_f0_51 : out std_logic; - sample_f0_52 : out std_logic; - sample_f0_53 : out std_logic; - sample_f0_54 : out std_logic; - sample_f0_55 : out std_logic; - sample_f0_56 : out std_logic; - sample_f0_57 : out std_logic; - sample_f0_58 : out std_logic; - sample_f0_59 : out std_logic; - sample_f0_60 : out std_logic; - sample_f0_61 : out std_logic; - sample_f0_62 : out std_logic; - sample_f0_63 : out std_logic; - sample_data_shaping_out_0 : in std_logic; - sample_data_shaping_out_1 : in std_logic; - sample_data_shaping_out_2 : in std_logic; - sample_data_shaping_out_3 : in std_logic; - sample_data_shaping_out_4 : in std_logic; - sample_data_shaping_out_5 : in std_logic; - sample_data_shaping_out_6 : in std_logic; - sample_data_shaping_out_7 : in std_logic; - sample_data_shaping_out_8 : in std_logic; - sample_data_shaping_out_9 : in std_logic; - sample_data_shaping_out_10 : in std_logic; - sample_data_shaping_out_11 : in std_logic; - sample_data_shaping_out_12 : in std_logic; - sample_data_shaping_out_13 : in std_logic; - sample_data_shaping_out_14 : in std_logic; - sample_data_shaping_out_15 : in std_logic; - sample_data_shaping_out_18 : in std_logic; - sample_data_shaping_out_19 : in std_logic; - sample_data_shaping_out_20 : in std_logic; - sample_data_shaping_out_21 : in std_logic; - sample_data_shaping_out_22 : in std_logic; - sample_data_shaping_out_23 : in std_logic; - sample_data_shaping_out_24 : in std_logic; - sample_data_shaping_out_25 : in std_logic; - sample_data_shaping_out_26 : in std_logic; - sample_data_shaping_out_27 : in std_logic; - sample_data_shaping_out_28 : in std_logic; - sample_data_shaping_out_29 : in std_logic; - sample_data_shaping_out_30 : in std_logic; - sample_data_shaping_out_31 : in std_logic; - sample_data_shaping_out_32 : in std_logic; - sample_data_shaping_out_33 : in std_logic; - sample_data_shaping_out_36 : in std_logic; - sample_data_shaping_out_37 : in std_logic; - sample_data_shaping_out_38 : in std_logic; - sample_data_shaping_out_39 : in std_logic; - sample_data_shaping_out_40 : in std_logic; - sample_data_shaping_out_41 : in std_logic; - sample_data_shaping_out_42 : in std_logic; - sample_data_shaping_out_43 : in std_logic; - sample_data_shaping_out_44 : in std_logic; - sample_data_shaping_out_45 : in std_logic; - sample_data_shaping_out_46 : in std_logic; - sample_data_shaping_out_47 : in std_logic; - sample_data_shaping_out_48 : in std_logic; - sample_data_shaping_out_49 : in std_logic; - sample_data_shaping_out_50 : in std_logic; - sample_data_shaping_out_51 : in std_logic; - sample_data_shaping_out_54 : in std_logic; - sample_data_shaping_out_55 : in std_logic; - sample_data_shaping_out_56 : in std_logic; - sample_data_shaping_out_57 : in std_logic; - sample_data_shaping_out_58 : in std_logic; - sample_data_shaping_out_59 : in std_logic; - sample_data_shaping_out_60 : in std_logic; - sample_data_shaping_out_61 : in std_logic; - sample_data_shaping_out_62 : in std_logic; - sample_data_shaping_out_63 : in std_logic; - sample_data_shaping_out_64 : in std_logic; - sample_data_shaping_out_65 : in std_logic; - sample_data_shaping_out_66 : in std_logic; - sample_data_shaping_out_67 : in std_logic; - sample_data_shaping_out_68 : in std_logic; - sample_data_shaping_out_69 : in std_logic; - sample_data_shaping_out_90 : in std_logic; - sample_data_shaping_out_91 : in std_logic; - sample_data_shaping_out_92 : in std_logic; - sample_data_shaping_out_93 : in std_logic; - sample_data_shaping_out_94 : in std_logic; - sample_data_shaping_out_95 : in std_logic; - sample_data_shaping_out_96 : in std_logic; - sample_data_shaping_out_97 : in std_logic; - sample_data_shaping_out_98 : in std_logic; - sample_data_shaping_out_99 : in std_logic; - sample_data_shaping_out_100 : in std_logic; - sample_data_shaping_out_101 : in std_logic; - sample_data_shaping_out_102 : in std_logic; - sample_data_shaping_out_103 : in std_logic; - sample_data_shaping_out_104 : in std_logic; - sample_data_shaping_out_105 : in std_logic; - sample_data_shaping_out_108 : in std_logic; - sample_data_shaping_out_109 : in std_logic; - sample_data_shaping_out_110 : in std_logic; - sample_data_shaping_out_111 : in std_logic; - sample_data_shaping_out_112 : in std_logic; - sample_data_shaping_out_113 : in std_logic; - sample_data_shaping_out_114 : in std_logic; - sample_data_shaping_out_115 : in std_logic; - sample_data_shaping_out_116 : in std_logic; - sample_data_shaping_out_117 : in std_logic; - sample_data_shaping_out_118 : in std_logic; - sample_data_shaping_out_119 : in std_logic; - sample_data_shaping_out_120 : in std_logic; - sample_data_shaping_out_121 : in std_logic; - sample_data_shaping_out_122 : in std_logic; - sample_data_shaping_out_123 : in std_logic; - sample_data_shaping_out_126 : in std_logic; - sample_data_shaping_out_127 : in std_logic; - sample_data_shaping_out_128 : in std_logic; - sample_data_shaping_out_129 : in std_logic; - sample_data_shaping_out_130 : in std_logic; - sample_data_shaping_out_131 : in std_logic; - sample_data_shaping_out_132 : in std_logic; - sample_data_shaping_out_133 : in std_logic; - sample_data_shaping_out_134 : in std_logic; - sample_data_shaping_out_135 : in std_logic; - sample_data_shaping_out_136 : in std_logic; - sample_data_shaping_out_137 : in std_logic; - sample_data_shaping_out_138 : in std_logic; - sample_data_shaping_out_139 : in std_logic; - sample_data_shaping_out_140 : in std_logic; - sample_data_shaping_out_141 : in std_logic; - sample_f0_wdata_95 : out std_logic; - sample_f0_wdata_94 : out std_logic; - sample_f0_wdata_93 : out std_logic; - sample_f0_wdata_92 : out std_logic; - sample_f0_wdata_91 : out std_logic; - sample_f0_wdata_90 : out std_logic; - sample_f0_wdata_89 : out std_logic; - sample_f0_wdata_88 : out std_logic; - sample_f0_wdata_87 : out std_logic; - sample_f0_wdata_86 : out std_logic; - sample_f0_wdata_85 : out std_logic; - sample_f0_wdata_84 : out std_logic; - sample_f0_wdata_83 : out std_logic; - sample_f0_wdata_82 : out std_logic; - sample_f0_wdata_81 : out std_logic; - sample_f0_wdata_80 : out std_logic; - sample_f0_wdata_79 : out std_logic; - sample_f0_wdata_78 : out std_logic; - sample_f0_wdata_77 : out std_logic; - sample_f0_wdata_76 : out std_logic; - sample_f0_wdata_75 : out std_logic; - sample_f0_wdata_74 : out std_logic; - sample_f0_wdata_73 : out std_logic; - sample_f0_wdata_72 : out std_logic; - sample_f0_wdata_71 : out std_logic; - sample_f0_wdata_70 : out std_logic; - sample_f0_wdata_69 : out std_logic; - sample_f0_wdata_68 : out std_logic; - sample_f0_wdata_67 : out std_logic; - sample_f0_wdata_66 : out std_logic; - sample_f0_wdata_65 : out std_logic; - sample_f0_wdata_64 : out std_logic; - sample_f0_wdata_63 : out std_logic; - sample_f0_wdata_62 : out std_logic; - sample_f0_wdata_61 : out std_logic; - sample_f0_wdata_60 : out std_logic; - sample_f0_wdata_59 : out std_logic; - sample_f0_wdata_58 : out std_logic; - sample_f0_wdata_57 : out std_logic; - sample_f0_wdata_56 : out std_logic; - sample_f0_wdata_55 : out std_logic; - sample_f0_wdata_54 : out std_logic; - sample_f0_wdata_53 : out std_logic; - sample_f0_wdata_52 : out std_logic; - sample_f0_wdata_51 : out std_logic; - sample_f0_wdata_50 : out std_logic; - sample_f0_wdata_49 : out std_logic; - sample_f0_wdata_48 : out std_logic; - sample_f0_wdata_15 : out std_logic; - sample_f0_wdata_14 : out std_logic; - sample_f0_wdata_13 : out std_logic; - sample_f0_wdata_12 : out std_logic; - sample_f0_wdata_11 : out std_logic; - sample_f0_wdata_10 : out std_logic; - sample_f0_wdata_9 : out std_logic; - sample_f0_wdata_8 : out std_logic; - sample_f0_wdata_7 : out std_logic; - sample_f0_wdata_6 : out std_logic; - sample_f0_wdata_5 : out std_logic; - sample_f0_wdata_4 : out std_logic; - sample_f0_wdata_3 : out std_logic; - sample_f0_wdata_2 : out std_logic; - sample_f0_wdata_1 : out std_logic; - sample_f0_wdata_0 : out std_logic; - sample_data_shaping_out_val : in std_logic; - sample_f0_val : out std_logic; - sample_data_shaping_out_val_0 : in std_logic; - sample_f0_val_0 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_f0_val_1 : out std_logic - ); - -end Downsampling_8_16_4; - -architecture DEF_ARCH of Downsampling_8_16_4 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - signal sample_out_val_19, sample_out_0_sqmuxa_3, - un14_sample_in_val_0, sample_out_0_sqmuxa_2, - sample_out_0_sqmuxa_1, sample_out_0_sqmuxa_0, - un14_sample_in_val_23, un14_sample_in_val_22, - un14_sample_in_val_24, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un14_sample_in_val_15, - un14_sample_in_val_14, un14_sample_in_val_20, - un14_sample_in_val_9, un14_sample_in_val_8, - un14_sample_in_val_19, un14_sample_in_val_5, - un14_sample_in_val_4, un14_sample_in_val_17, - un14_sample_in_val_13, \counter[24]_net_1\, - un14_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un14_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un14_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un14_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un14_sample_in_val, - sample_out_0_sqmuxa, \counter_4[2]\, I_9, \counter_4[3]\, - I_13, \counter_4[4]\, I_20, \counter_4[5]\, I_24, - \counter_4[6]\, I_31_0, \counter_4[7]\, I_38, - \counter_4[8]\, I_45, \counter_4[9]\, I_52, - \counter_4[10]\, I_56, \counter_4[11]\, I_66, - \counter_4[12]\, I_73, \counter_4[13]\, I_77, - \counter_4[14]\, I_84, \counter_4[15]\, I_91, - \counter_4[16]\, I_98, \counter_4[17]\, I_105, - \counter_4[18]\, I_115, \counter_4[19]\, I_122, - \counter_4[20]\, I_129, \counter_4[21]\, I_136, - \counter_4[22]\, I_143, \counter_4[23]\, I_156, - \counter_4[24]\, I_166, \counter_4[25]\, I_173, - \counter_4[26]\, I_186, \counter_4[27]\, I_196, I_4, I_5, - N_4, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[19]_net_1\); - - \sample_out[125]\ : DFN1E1 - port map(D => sample_data_shaping_out_139, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_2); - - \sample_out[102]\ : DFN1E1 - port map(D => sample_data_shaping_out_114, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_54); - - \sample_out[122]\ : DFN1E1 - port map(D => sample_data_shaping_out_136, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_5); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_data_shaping_out_24, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_73); - - \sample_out[101]\ : DFN1E1 - port map(D => sample_data_shaping_out_113, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_53); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_data_shaping_out_22, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_75); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_data_shaping_out_13, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_82); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_data_shaping_out_1, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_94); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_data_shaping_out_21, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_76); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_data_shaping_out_67, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_13); - - \sample_out[121]\ : DFN1E1 - port map(D => sample_data_shaping_out_135, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_6); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_data_shaping_out_42, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_57); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_data_shaping_out_105, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_47); - - \counter_RNO[11]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_66, Y => - \counter_4[11]\); - - \counter_RNIHDLE1[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa_1); - - \sample_out[104]\ : DFN1E1 - port map(D => sample_data_shaping_out_116, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_56); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_data_shaping_out_38, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_61); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4); - - \sample_out[124]\ : DFN1E1 - port map(D => sample_data_shaping_out_138, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_3); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \counter_RNI0L371[10]\ : OR3C - port map(A => un14_sample_in_val_23, B => - un14_sample_in_val_22, C => un14_sample_in_val_24, Y => - un14_sample_in_val_0); - - \sample_out[97]\ : DFN1E1 - port map(D => sample_data_shaping_out_109, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_49); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186); - - \sample_out[108]\ : DFN1E1 - port map(D => sample_data_shaping_out_120, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_60); - - \counter_RNO[15]\ : NOR2B - port map(A => un14_sample_in_val, B => I_91, Y => - \counter_4[15]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_data_shaping_out_57, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_3); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_data_shaping_out_62, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_8); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_data_shaping_out_0, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_95); - - \counter_RNO[7]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_38, Y => - \counter_4[7]\); - - \counter[6]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_data_shaping_out_91, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_33); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_data_shaping_out_96, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_38); - - \counter[3]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73); - - \counter_RNO[8]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_45, Y => - \counter_4[8]\); - - \counter_RNO[13]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_77, Y => - \counter_4[13]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52); - - \counter_RNIKF54[20]\ : NOR3A - port map(A => un14_sample_in_val_3, B => - \counter[23]_net_1\, C => \counter[20]_net_1\, Y => - un14_sample_in_val_15); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_data_shaping_out_12, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_83); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_data_shaping_out_10, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_85); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_data_shaping_out_49, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_50); - - \counter_RNO[12]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_73, Y => - \counter_4[12]\); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_data_shaping_out_37, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_62); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_data_shaping_out_43, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_56); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[17]_net_1\); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_data_shaping_out_5, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_90); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_data_shaping_out_51, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_48); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \counter_RNILSE[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un14_sample_in_val_1); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - \sample_out[115]\ : DFN1E1 - port map(D => sample_data_shaping_out_129, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_data_shaping_out_23, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_74); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_data_shaping_out_28, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_69); - - \counter_RNIB507[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un14_sample_in_val_13); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_data_shaping_out_2, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_93); - - \sample_out[98]\ : DFN1E1 - port map(D => sample_data_shaping_out_110, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_50); - - \sample_out[112]\ : DFN1E1 - port map(D => sample_data_shaping_out_126, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_15); - - \counter_RNIHDLE1_1[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa_0); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[27]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[27]_net_1\); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_data_shaping_out_104, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_46); - - \sample_out[111]\ : DFN1E1 - port map(D => sample_data_shaping_out_123, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_63); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166); - - \counter_RNO[17]\ : NOR2B - port map(A => un14_sample_in_val, B => I_105, Y => - \counter_4[17]\); - - \counter_RNII3CB1[10]\ : NOR2A - port map(A => sample_data_shaping_out_val_0, B => - un14_sample_in_val_0, Y => sample_out_val_19); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[23]_net_1\); - - \counter_RNIGCTE[12]\ : NOR3C - port map(A => un14_sample_in_val_9, B => - un14_sample_in_val_8, C => un14_sample_in_val_19, Y => - un14_sample_in_val_23); - - \counter_RNI8DT[27]\ : NOR3A - port map(A => un14_sample_in_val_1, B => - \counter[11]_net_1\, C => \counter[27]_net_1\, Y => - un14_sample_in_val_14); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_data_shaping_out_61, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_7); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \sample_out[114]\ : DFN1E1 - port map(D => sample_data_shaping_out_128, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196); - - \counter_RNIHDLE1_0[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa_2); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_data_shaping_out_36, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_63); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122); - - \sample_out[118]\ : DFN1E1 - port map(D => sample_data_shaping_out_132, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_9); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_data_shaping_out_63, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_9); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_data_shaping_out_32, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_65); - - \counter_RNO[14]\ : NOR2B - port map(A => un14_sample_in_val, B => I_84, Y => - \counter_4[14]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_data_shaping_out_95, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_37); - - \counter_RNI51T[12]\ : NOR3A - port map(A => un14_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un14_sample_in_val_19); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_data_shaping_out_val, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => un14_sample_in_val, B => I_186, Y => - \counter_4[26]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_data_shaping_out_4, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_91); - - \counter_RNO[5]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_24, Y => - \counter_4[5]\); - - \sample_out[103]\ : DFN1E1 - port map(D => sample_data_shaping_out_115, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_55); - - \sample_out[100]\ : DFN1E1 - port map(D => sample_data_shaping_out_112, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_52); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[25]_net_1\); - - \sample_out[123]\ : DFN1E1 - port map(D => sample_data_shaping_out_137, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_4); - - \sample_out[120]\ : DFN1E1 - port map(D => sample_data_shaping_out_134, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_7); - - \counter_RNI0RM3[10]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un14_sample_in_val_4); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_19, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f0_val); - - \counter_RNO[3]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_13, Y => - \counter_4[3]\); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_data_shaping_out_97, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_39); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_data_shaping_out_54, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_0); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_data_shaping_out_103, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_45); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_data_shaping_out_11, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_84); - - \sample_out[99]\ : DFN1E1 - port map(D => sample_data_shaping_out_111, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_51); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_data_shaping_out_18, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_79); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[5]_net_1\); - - \counter_RNIAGNA[24]\ : NOR3A - port map(A => un14_sample_in_val_13, B => - \counter[1]_net_1\, C => \counter[24]_net_1\, Y => - un14_sample_in_val_20); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_data_shaping_out_48, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_51); - - \counter_RNIP507[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un14_sample_in_val_9); - - \counter_RNIJKE[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un14_sample_in_val_5); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNINB64[22]\ : NOR3A - port map(A => un14_sample_in_val_7, B => - \counter[22]_net_1\, C => \counter[19]_net_1\, Y => - un14_sample_in_val_17); - - \counter_RNO[10]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_56, Y => - \counter_4[10]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9); - - \counter_RNO[21]\ : NOR2B - port map(A => un14_sample_in_val, B => I_136, Y => - \counter_4[21]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_data_shaping_out_27, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_70); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => un14_sample_in_val, B => I_173, Y => - \counter_4[25]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_0); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98); - - \counter_RNIHDLE1_3[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_data_shaping_out_29, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_68); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNO[6]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_31_0, Y => - \counter_4[6]\); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - \counter_RNI6DQF[20]\ : NOR3C - port map(A => un14_sample_in_val_15, B => - un14_sample_in_val_14, C => un14_sample_in_val_20, Y => - un14_sample_in_val_24); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_data_shaping_out_64, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_10); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[26]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66); - - \counter_RNO[23]\ : NOR2B - port map(A => un14_sample_in_val, B => I_156, Y => - \counter_4[23]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_data_shaping_out_60, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_6); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_data_shaping_out_47, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_52); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_data_shaping_out_55, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_1); - - sample_out_val_0 : DFN1C0 - port map(D => sample_out_val_19, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f0_val_0); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_data_shaping_out_102, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_44); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_data_shaping_out_98, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_40); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_data_shaping_out_100, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_42); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91); - - \counter_RNO[22]\ : NOR2B - port map(A => un14_sample_in_val, B => I_143, Y => - \counter_4[22]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_data_shaping_out_33, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_64); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_data_shaping_out_40, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_59); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_data_shaping_out_94, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_36); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_data_shaping_out_69, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_15); - - \counter_RNI5JN3[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un14_sample_in_val_3); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_data_shaping_out_15, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_80); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[113]\ : DFN1E1 - port map(D => sample_data_shaping_out_127, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_14); - - \sample_out[110]\ : DFN1E1 - port map(D => sample_data_shaping_out_122, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_62); - - \counter_RNO[4]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_20, Y => - \counter_4[4]\); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \sample_out[106]\ : DFN1E1 - port map(D => sample_data_shaping_out_118, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_58); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_data_shaping_out_19, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_78); - - \sample_out[107]\ : DFN1E1 - port map(D => sample_data_shaping_out_119, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_59); - - \counter_RNO[18]\ : NOR2B - port map(A => un14_sample_in_val, B => I_115, Y => - \counter_4[18]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[126]\ : DFN1E1 - port map(D => sample_data_shaping_out_140, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_1); - - \sample_out[127]\ : DFN1E1 - port map(D => sample_data_shaping_out_141, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_0); - - \counter_RNIKKE[21]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un14_sample_in_val_11); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_data_shaping_out_59, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_5); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_data_shaping_out_30, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_67); - - \counter_RNO[27]\ : NOR2B - port map(A => un14_sample_in_val, B => I_196, Y => - \counter_4[27]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_data_shaping_out_65, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_11); - - \sample_out[109]\ : DFN1E1 - port map(D => sample_data_shaping_out_121, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_61); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_data_shaping_out_26, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_71); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_data_shaping_out_46, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_53); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_data_shaping_out_44, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_55); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_data_shaping_out_93, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_35); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_data_shaping_out_99, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_41); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => un14_sample_in_val, B => I_166, Y => - \counter_4[24]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_data_shaping_out_6, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_89); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_data_shaping_out_68, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_14); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_data_shaping_out_66, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_12); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_data_shaping_out_39, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_60); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_data_shaping_out_101, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_43); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - \sample_out[96]\ : DFN1E1 - port map(D => sample_data_shaping_out_108, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_48); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - \counter_RNII507[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un14_sample_in_val_8); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNI1FN3[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un14_sample_in_val_7); - - sample_out_val_1 : DFN1C0 - port map(D => sample_out_val_19, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f0_val_1); - - \counter_RNO[20]\ : NOR2B - port map(A => un14_sample_in_val, B => I_129, Y => - \counter_4[20]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_data_shaping_out_41, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_58); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_data_shaping_out_25, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_72); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_data_shaping_out_58, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_4); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_data_shaping_out_31, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_66); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_data_shaping_out_56, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_2); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_data_shaping_out_20, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_77); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_data_shaping_out_9, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_wdata_86); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_data_shaping_out_7, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_88); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_data_shaping_out_14, CLK => HCLK_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_81); - - \counter_RNIHDLE1_2[10]\ : NOR3B - port map(A => sample_data_shaping_out_val_0, B => HRESETn_c, - C => un14_sample_in_val_0, Y => sample_out_0_sqmuxa_3); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_data_shaping_out_92, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_34); - - \counter_RNO[2]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_9, Y => - \counter_4[2]\); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[9]_net_1\); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_data_shaping_out_90, CLK => HCLK_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_32); - - \counter_RNO[19]\ : NOR2B - port map(A => un14_sample_in_val, B => I_122, Y => - \counter_4[19]\); - - \counter_RNIARB8[10]\ : NOR3C - port map(A => un14_sample_in_val_5, B => - un14_sample_in_val_4, C => un14_sample_in_val_17, Y => - un14_sample_in_val_22); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : NOR2B - port map(A => un14_sample_in_val_0, B => I_52, Y => - \counter_4[9]\); - - \counter_RNI0L371_0[10]\ : OR3C - port map(A => un14_sample_in_val_23, B => - un14_sample_in_val_22, C => un14_sample_in_val_24, Y => - un14_sample_in_val); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val, Q => - \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143); - - \sample_out[116]\ : DFN1E1 - port map(D => sample_data_shaping_out_130, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_11); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_data_shaping_out_val_0, Q => - \counter[18]_net_1\); - - \sample_out[117]\ : DFN1E1 - port map(D => sample_data_shaping_out_131, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_10); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_data_shaping_out_8, CLK => HCLK_c, E - => sample_out_0_sqmuxa, Q => sample_f0_wdata_87); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_data_shaping_out_45, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_54); - - \counter_RNO[16]\ : NOR2B - port map(A => un14_sample_in_val, B => I_98, Y => - \counter_4[16]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_data_shaping_out_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_data_shaping_out_50, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_49); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_data_shaping_out_3, CLK => HCLK_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_92); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - \sample_out[105]\ : DFN1E1 - port map(D => sample_data_shaping_out_117, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_57); - - \sample_out[119]\ : DFN1E1 - port map(D => sample_data_shaping_out_133, CLK => HCLK_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_8_16_6 is - - port( sample_f0_0 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_15 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_37 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_63 : in std_logic; - sample_f1_0 : out std_logic; - sample_f1_1 : out std_logic; - sample_f1_2 : out std_logic; - sample_f1_3 : out std_logic; - sample_f1_4 : out std_logic; - sample_f1_5 : out std_logic; - sample_f1_6 : out std_logic; - sample_f1_7 : out std_logic; - sample_f1_8 : out std_logic; - sample_f1_9 : out std_logic; - sample_f1_10 : out std_logic; - sample_f1_11 : out std_logic; - sample_f1_12 : out std_logic; - sample_f1_13 : out std_logic; - sample_f1_14 : out std_logic; - sample_f1_15 : out std_logic; - sample_f1_32 : out std_logic; - sample_f1_33 : out std_logic; - sample_f1_34 : out std_logic; - sample_f1_35 : out std_logic; - sample_f1_36 : out std_logic; - sample_f1_37 : out std_logic; - sample_f1_38 : out std_logic; - sample_f1_39 : out std_logic; - sample_f1_40 : out std_logic; - sample_f1_41 : out std_logic; - sample_f1_42 : out std_logic; - sample_f1_43 : out std_logic; - sample_f1_44 : out std_logic; - sample_f1_45 : out std_logic; - sample_f1_46 : out std_logic; - sample_f1_47 : out std_logic; - sample_f1_48 : out std_logic; - sample_f1_49 : out std_logic; - sample_f1_50 : out std_logic; - sample_f1_51 : out std_logic; - sample_f1_52 : out std_logic; - sample_f1_53 : out std_logic; - sample_f1_54 : out std_logic; - sample_f1_55 : out std_logic; - sample_f1_56 : out std_logic; - sample_f1_57 : out std_logic; - sample_f1_58 : out std_logic; - sample_f1_59 : out std_logic; - sample_f1_60 : out std_logic; - sample_f1_61 : out std_logic; - sample_f1_62 : out std_logic; - sample_f1_63 : out std_logic; - sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f1_wdata_95 : out std_logic; - sample_f1_wdata_94 : out std_logic; - sample_f1_wdata_93 : out std_logic; - sample_f1_wdata_92 : out std_logic; - sample_f1_wdata_91 : out std_logic; - sample_f1_wdata_90 : out std_logic; - sample_f1_wdata_89 : out std_logic; - sample_f1_wdata_88 : out std_logic; - sample_f1_wdata_87 : out std_logic; - sample_f1_wdata_86 : out std_logic; - sample_f1_wdata_85 : out std_logic; - sample_f1_wdata_84 : out std_logic; - sample_f1_wdata_83 : out std_logic; - sample_f1_wdata_82 : out std_logic; - sample_f1_wdata_81 : out std_logic; - sample_f1_wdata_80 : out std_logic; - sample_f1_wdata_79 : out std_logic; - sample_f1_wdata_78 : out std_logic; - sample_f1_wdata_77 : out std_logic; - sample_f1_wdata_76 : out std_logic; - sample_f1_wdata_75 : out std_logic; - sample_f1_wdata_74 : out std_logic; - sample_f1_wdata_73 : out std_logic; - sample_f1_wdata_72 : out std_logic; - sample_f1_wdata_71 : out std_logic; - sample_f1_wdata_70 : out std_logic; - sample_f1_wdata_69 : out std_logic; - sample_f1_wdata_68 : out std_logic; - sample_f1_wdata_67 : out std_logic; - sample_f1_wdata_66 : out std_logic; - sample_f1_wdata_65 : out std_logic; - sample_f1_wdata_64 : out std_logic; - sample_f1_wdata_63 : out std_logic; - sample_f1_wdata_62 : out std_logic; - sample_f1_wdata_61 : out std_logic; - sample_f1_wdata_60 : out std_logic; - sample_f1_wdata_59 : out std_logic; - sample_f1_wdata_58 : out std_logic; - sample_f1_wdata_57 : out std_logic; - sample_f1_wdata_56 : out std_logic; - sample_f1_wdata_55 : out std_logic; - sample_f1_wdata_54 : out std_logic; - sample_f1_wdata_53 : out std_logic; - sample_f1_wdata_52 : out std_logic; - sample_f1_wdata_51 : out std_logic; - sample_f1_wdata_50 : out std_logic; - sample_f1_wdata_49 : out std_logic; - sample_f1_wdata_48 : out std_logic; - sample_f1_wdata_15 : out std_logic; - sample_f1_wdata_14 : out std_logic; - sample_f1_wdata_13 : out std_logic; - sample_f1_wdata_12 : out std_logic; - sample_f1_wdata_11 : out std_logic; - sample_f1_wdata_10 : out std_logic; - sample_f1_wdata_9 : out std_logic; - sample_f1_wdata_8 : out std_logic; - sample_f1_wdata_7 : out std_logic; - sample_f1_wdata_6 : out std_logic; - sample_f1_wdata_5 : out std_logic; - sample_f1_wdata_4 : out std_logic; - sample_f1_wdata_3 : out std_logic; - sample_f1_wdata_2 : out std_logic; - sample_f1_wdata_1 : out std_logic; - sample_f1_wdata_0 : out std_logic; - sample_f0_val_1 : in std_logic; - sample_f1_val : out std_logic; - sample_f0_val_0 : in std_logic; - sample_out_0_sqmuxa_1 : out std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - sample_f1_val_0 : out std_logic - ); - -end Downsampling_8_16_6; - -architecture DEF_ARCH of Downsampling_8_16_6 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal sample_out_val_14, sample_out_0_sqmuxa_3, - un10_sample_in_val_24, un10_sample_in_val_25, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1_net_1, - sample_out_0_sqmuxa_1_0, sample_out_0_sqmuxa_0, - un10_sample_in_val_24_0, un10_sample_in_val_15, - un10_sample_in_val_14, un10_sample_in_val_20, - un10_sample_in_val_25_0, un10_sample_in_val_17, - un10_sample_in_val_16, un10_sample_in_val_23, N_137, - \counter[1]_net_1\, \counter[0]_net_1\, N_129, - \counter[3]_net_1\, \DWACT_FDEC_E[0]\, N_106, - \counter[8]_net_1\, \DWACT_FDEC_E[4]\, N_91, - \DWACT_FDEC_E[7]\, \DWACT_FDEC_E[6]\, - un10_sample_in_val_9, un10_sample_in_val_8, - un10_sample_in_val_19, un10_sample_in_val_13, - \counter[24]_net_1\, un10_sample_in_val_11, - \counter[15]_net_1\, \counter[12]_net_1\, - un10_sample_in_val_7, \counter[22]_net_1\, - \counter[19]_net_1\, un10_sample_in_val_5, - \counter[10]_net_1\, \counter[7]_net_1\, - un10_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un10_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, \counter_4[1]\, I_5_0, - \counter_4[3]\, I_13_0, \counter_4[4]\, I_20_0, - \counter_4[5]\, I_24_0, \counter_4[6]\, I_31_1, - \counter_4[7]\, I_38_0, \counter_4[8]\, I_45_0, - \counter_4[9]\, I_52_0, \counter_4[10]\, I_56_0, - \counter_4[11]\, I_66_0, \counter_4[12]\, I_73_0, - \counter_4[13]\, I_77_0, \counter_4[14]\, I_84_0, - \counter_4[15]\, I_91_0, \counter_4[16]\, I_98_0, - \counter_4[17]\, I_105_0, \counter_4[18]\, I_115_0, - \counter_4[19]\, I_122_0, \counter_4[20]\, I_129_0, - \counter_4[21]\, I_136_0, \counter_4[22]\, I_143_0, - \counter_4[23]\, I_156_0, \counter_4[24]\, I_166_0, - \counter_4[25]\, I_173_0, \counter_4[26]\, I_186_0, - \counter_4[27]\, I_196_0, sample_out_0_sqmuxa, I_4_0, - I_9_0, N_4, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - sample_out_0_sqmuxa_1 <= sample_out_0_sqmuxa_1_net_1; - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[19]_net_1\); - - \sample_out[125]\ : DFN1E1 - port map(D => sample_f0_wdata_2, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_2); - - \sample_out[102]\ : DFN1E1 - port map(D => sample_f0_54, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_54); - - \sample_out[122]\ : DFN1E1 - port map(D => sample_f0_wdata_5, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_5); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f0_wdata_73, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_73); - - \sample_out[101]\ : DFN1E1 - port map(D => sample_f0_53, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_53); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f0_wdata_75, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_75); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f0_wdata_82, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_82); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f0_wdata_94, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_94); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f0_wdata_76, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_76); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f0_13, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_13); - - \sample_out[121]\ : DFN1E1 - port map(D => sample_f0_wdata_6, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_6); - - \counter_RNIA89N_0[10]\ : NOR3C - port map(A => un10_sample_in_val_17, B => - un10_sample_in_val_16, C => un10_sample_in_val_23, Y => - un10_sample_in_val_25_0); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f0_wdata_57, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_57); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f0_47, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_47); - - \counter_RNO[11]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_66_0, Y => - \counter_4[11]\); - - \sample_out[104]\ : DFN1E1 - port map(D => sample_f0_56, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_56); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f0_wdata_61, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_61); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_0); - - \sample_out[124]\ : DFN1E1 - port map(D => sample_f0_wdata_3, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_3); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \sample_out[97]\ : DFN1E1 - port map(D => sample_f0_49, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_49); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_0); - - \sample_out[108]\ : DFN1E1 - port map(D => sample_f0_60, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_60); - - \counter_RNO[15]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_91_0, Y => \counter_4[15]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f0_3, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_3); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f0_8, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_8); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f0_wdata_95, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_95); - - \counter_RNO[7]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_38_0, Y => \counter_4[7]\); - - \counter[6]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_0); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f0_33, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_33); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f0_38, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_38); - - \counter[3]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_0, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val_1, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_0); - - \counter_RNO[8]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_45_0, Y => \counter_4[8]\); - - \counter_RNO[13]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_77_0, Y => - \counter_4[13]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_0); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f0_wdata_83, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_83); - - \counter_RNINF54[10]\ : NOR3A - port map(A => un10_sample_in_val_5, B => - \counter[10]_net_1\, C => \counter[7]_net_1\, Y => - un10_sample_in_val_16); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f0_wdata_85, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_85); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f0_wdata_50, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_50); - - \counter_RNO[12]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_73_0, Y => - \counter_4[12]\); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f0_wdata_62, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_62); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f0_wdata_56, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_56); - - \counter_RNO[1]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_5_0, Y => \counter_4[1]\); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[17]_net_1\); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter_RNIRB64[22]\ : NOR3A - port map(A => un10_sample_in_val_7, B => - \counter[22]_net_1\, C => \counter[19]_net_1\, Y => - un10_sample_in_val_17); - - \counter[4]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_0); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f0_wdata_90, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_90); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f0_wdata_48, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_48); - - \counter_RNI91T[12]\ : NOR3A - port map(A => un10_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un10_sample_in_val_19); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - \sample_out[115]\ : DFN1E1 - port map(D => sample_f0_wdata_12, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f0_wdata_74, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_74); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f0_wdata_69, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_69); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f0_wdata_93, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_93); - - \sample_out[98]\ : DFN1E1 - port map(D => sample_f0_50, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_50); - - \sample_out[112]\ : DFN1E1 - port map(D => sample_f0_wdata_15, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_15); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[27]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[27]_net_1\); - - \counter_RNIIDQF[20]\ : NOR3C - port map(A => un10_sample_in_val_15, B => - un10_sample_in_val_14, C => un10_sample_in_val_20, Y => - un10_sample_in_val_24); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f0_46, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_46); - - \sample_out[111]\ : DFN1E1 - port map(D => sample_f0_63, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_63); - - \counter_RNIMKE[21]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un10_sample_in_val_11); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_0); - - \counter_RNO[17]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_105_0, Y => \counter_4[17]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f0_7, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_7); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \sample_out[114]\ : DFN1E1 - port map(D => sample_f0_wdata_13, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_0); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f0_wdata_63, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_63); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_0); - - \counter_RNILKE[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un10_sample_in_val_5); - - \sample_out[118]\ : DFN1E1 - port map(D => sample_f0_wdata_9, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_9); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f0_9, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_9); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f0_wdata_65, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_65); - - \counter_RNO[14]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_84_0, Y => - \counter_4[14]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f0_37, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_37); - - \counter[1]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_186_0, Y => \counter_4[26]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f0_wdata_91, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_91); - - \counter_RNO[5]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_24_0, Y => \counter_4[5]\); - - \sample_out[103]\ : DFN1E1 - port map(D => sample_f0_55, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_55); - - \sample_out[100]\ : DFN1E1 - port map(D => sample_f0_52, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_52); - - \counter_RNI7KBF1_0[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa_2); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[25]_net_1\); - - \sample_out[123]\ : DFN1E1 - port map(D => sample_f0_wdata_4, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_4); - - \sample_out[120]\ : DFN1E1 - port map(D => sample_f0_wdata_7, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_7); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_14, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f1_val); - - \counter_RNO[3]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_13_0, Y => \counter_4[3]\); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f0_39, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_39); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_0); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_0); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f0_0, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_0); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_0); - - \counter_RNID507[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un10_sample_in_val_13); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f0_45, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_45); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f0_wdata_84, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_84); - - \sample_out[99]\ : DFN1E1 - port map(D => sample_f0_51, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_51); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f0_wdata_79, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_79); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f0_wdata_51, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_51); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_56_0, Y => - \counter_4[10]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_0); - - \counter_RNO[21]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_136_0, Y => \counter_4[21]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_0); - - \counter_RNIK507[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un10_sample_in_val_8); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f0_wdata_70, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_70); - - \counter_RNI7KBF1_3[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_0); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_173_0, Y => \counter_4[25]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_1); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_0); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f0_wdata_68, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_68); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNO[6]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_31_1, Y => \counter_4[6]\); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_0); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f0_10, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_10); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[26]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_0); - - \counter_RNO[23]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_156_0, Y => \counter_4[23]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f0_6, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_6); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f0_wdata_52, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_52); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f0_1, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_1); - - sample_out_val_0 : DFN1C0 - port map(D => sample_out_val_14, CLK => HCLK_c, CLR => - HRESETn_c, Q => sample_f1_val_0); - - \counter_RNI3FN3[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un10_sample_in_val_7); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_0); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_0); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f0_44, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_44); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_0); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f0_40, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_40); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f0_42, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_42); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_0); - - \counter_RNO[22]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_143_0, Y => \counter_4[22]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f0_wdata_64, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_64); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f0_wdata_59, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_59); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out_0_sqmuxa_1\ : NOR2B - port map(A => sample_f0_val_0, B => HRESETn_c, Y => - sample_out_0_sqmuxa_1_net_1); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f0_36, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_36); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f0_15, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_15); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f0_wdata_80, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_80); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_0); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[113]\ : DFN1E1 - port map(D => sample_f0_wdata_14, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_14); - - \sample_out[110]\ : DFN1E1 - port map(D => sample_f0_62, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_62); - - \counter_RNO[4]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_20_0, Y => \counter_4[4]\); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \counter_RNI7KBF1_1[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa_0); - - \counter_RNINSE[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un10_sample_in_val_1); - - \sample_out[106]\ : DFN1E1 - port map(D => sample_f0_58, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_58); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_0); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f0_wdata_78, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_78); - - \sample_out[107]\ : DFN1E1 - port map(D => sample_f0_59, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_59); - - \counter_RNO[18]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_115_0, Y => \counter_4[18]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[126]\ : DFN1E1 - port map(D => sample_f0_wdata_1, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_1); - - \sample_out[127]\ : DFN1E1 - port map(D => sample_f0_wdata_0, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_0); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f0_5, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_5); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f0_wdata_67, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_67); - - \counter_RNO[27]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_196_0, Y => \counter_4[27]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f0_11, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_11); - - \counter_RNI7KBF1_2[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa_3); - - \sample_out[109]\ : DFN1E1 - port map(D => sample_f0_61, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_61); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f0_wdata_71, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_71); - - \counter_RNIOF54[20]\ : NOR3A - port map(A => un10_sample_in_val_3, B => - \counter[23]_net_1\, C => \counter[20]_net_1\, Y => - un10_sample_in_val_15); - - \counter_RNIOCTE[12]\ : NOR3C - port map(A => un10_sample_in_val_9, B => - un10_sample_in_val_8, C => un10_sample_in_val_19, Y => - un10_sample_in_val_23); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f0_wdata_53, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_53); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f0_wdata_55, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_55); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f0_35, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_35); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f0_41, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_41); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_166_0, Y => \counter_4[24]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_0); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f0_wdata_89, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_89); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f0_14, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_14); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f0_12, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_12); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \counter_RNI7JN3[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un10_sample_in_val_3); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f0_wdata_60, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_60); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f0_43, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_43); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - \sample_out[96]\ : DFN1E1 - port map(D => sample_f0_48, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_48); - - \counter_RNICDT[27]\ : NOR3A - port map(A => un10_sample_in_val_1, B => - \counter[11]_net_1\, C => \counter[27]_net_1\, Y => - un10_sample_in_val_14); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - \counter_RNI8A2C1[10]\ : NOR3C - port map(A => un10_sample_in_val_24_0, B => - un10_sample_in_val_25_0, C => sample_f0_val_0, Y => - sample_out_val_14); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_129_0, Y => \counter_4[20]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f0_wdata_58, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_58); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f0_wdata_72, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_72); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f0_4, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_4); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f0_wdata_66, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_66); - - \counter_RNIEGNA[24]\ : NOR3A - port map(A => un10_sample_in_val_13, B => - \counter[1]_net_1\, C => \counter[24]_net_1\, Y => - un10_sample_in_val_20); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f0_2, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_2); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f0_wdata_77, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_77); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f0_wdata_86, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_wdata_86); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f0_wdata_88, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_88); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f0_wdata_81, CLK => HCLK_c, E => - sample_out_0_sqmuxa_1_0, Q => sample_f1_wdata_81); - - \counter_RNI7KBF1[10]\ : NOR3C - port map(A => un10_sample_in_val_24, B => - un10_sample_in_val_25, C => sample_out_0_sqmuxa_1_net_1, - Y => sample_out_0_sqmuxa_1_0); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f0_34, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_34); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[9]_net_1\); - - \counter_RNIA89N[10]\ : NOR3C - port map(A => un10_sample_in_val_17, B => - un10_sample_in_val_16, C => un10_sample_in_val_23, Y => - un10_sample_in_val_25); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f0_32, CLK => HCLK_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_32); - - \counter_RNO[19]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_122_0, Y => \counter_4[19]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : AOI1B - port map(A => un10_sample_in_val_25_0, B => - un10_sample_in_val_24_0, C => I_52_0, Y => \counter_4[9]\); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_1, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_0); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_0); - - \counter_RNIR507[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un10_sample_in_val_9); - - \sample_out[116]\ : DFN1E1 - port map(D => sample_f0_wdata_11, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_11); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => HCLK_c, CLR => - HRESETn_c, E => sample_f0_val_0, Q => \counter[18]_net_1\); - - \sample_out[117]\ : DFN1E1 - port map(D => sample_f0_wdata_10, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_10); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \counter_RNIIDQF_0[20]\ : NOR3C - port map(A => un10_sample_in_val_15, B => - un10_sample_in_val_14, C => un10_sample_in_val_20, Y => - un10_sample_in_val_24_0); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f0_wdata_87, CLK => HCLK_c, E => - sample_out_0_sqmuxa, Q => sample_f1_wdata_87); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f0_wdata_54, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_54); - - \counter_RNO[16]\ : AOI1B - port map(A => un10_sample_in_val_25, B => - un10_sample_in_val_24, C => I_98_0, Y => \counter_4[16]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_0, CLK => HCLK_c, CLR => HRESETn_c, E => - sample_f0_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f0_wdata_49, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_49); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f0_wdata_92, CLK => HCLK_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_92); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - \sample_out[105]\ : DFN1E1 - port map(D => sample_f0_57, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_57); - - \sample_out[119]\ : DFN1E1 - port map(D => sample_f0_wdata_8, CLK => HCLK_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity SYNC_FF_1 is - - port( cnv_run_c : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - cnv_run_sync : out std_logic - ); - -end SYNC_FF_1; - -architecture DEF_ARCH of SYNC_FF_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \A_temp[1]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sync_loop.0.A_temp[0]\ : DFN1C0 - port map(D => \A_temp[1]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => cnv_run_sync); - - GND_i_0 : GND - port map(Y => GND_0); - - \sync_loop.1.A_temp[1]\ : DFN1C0 - port map(D => cnv_run_c, CLK => HCLK_c, CLR => HRESETn_c, Q - => \A_temp[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity SYNC_FF is - - port( cnv_c : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic; - cnv_sync : out std_logic; - cnv_sync_i : out std_logic - ); - -end SYNC_FF; - -architecture DEF_ARCH of SYNC_FF is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \cnv_sync\, \A_temp[1]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - cnv_sync <= \cnv_sync\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sync_loop.0.A_temp[0]\ : DFN1C0 - port map(D => \A_temp[1]\, CLK => HCLK_c, CLR => HRESETn_c, - Q => \cnv_sync\); - - GND_i_0 : GND - port map(Y => GND_0); - - \sync_loop.1.A_temp[1]\ : DFN1C0 - port map(D => cnv_c, CLK => HCLK_c, CLR => HRESETn_c, Q => - \A_temp[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sync_loop.0.A_temp_RNIEBA5[0]\ : INV - port map(A => \cnv_sync\, Y => cnv_sync_i); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity AD7688_drvr is - - port( sample_7 : out std_logic_vector(15 downto 0); - sample_0 : out std_logic_vector(15 downto 0); - sample_1 : out std_logic_vector(15 downto 0); - sample_2 : out std_logic_vector(15 downto 0); - sample_3 : out std_logic_vector(15 downto 0); - sample_4 : out std_logic_vector(15 downto 0); - sample_5 : out std_logic_vector(15 downto 0); - sdo_c : in std_logic_vector(7 downto 0); - sample_6 : out std_logic_vector(15 downto 0); - cnv_rstn_c : in std_logic; - cnv_clk_c : in std_logic; - cnv_c : out std_logic; - sample_val : out std_logic; - sck_c : out std_logic; - cnv_run_c : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end AD7688_drvr; - -architecture DEF_ARCH of AD7688_drvr is - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component SYNC_FF_1 - port( cnv_run_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - cnv_run_sync : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component SYNC_FF - port( cnv_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - cnv_sync : out std_logic; - cnv_sync_i : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \sample_bit_counter_4[0]_net_1\, - sample_bit_counter_n0, N_6, - \sample_bit_counter_3[0]_net_1\, - \sample_bit_counter_2[0]_net_1\, - \sample_bit_counter_1[0]_net_1\, - \sample_bit_counter_0[0]_net_1\, sample_0_0_sqmuxa, - \sample_bit_counter_RNIVMI9[5]_net_1\, - \sample_bit_counter_i[0]\, sample_bit_counterlde_i_a3_0_1, - \sample_bit_counter[3]_net_1\, - \sample_bit_counter[2]_net_1\, - \sample_bit_counter[4]_net_1\, un3_cnv_runlto8_0, - \cnv_cycle_counter[8]_net_1\, - \cnv_cycle_counter[7]_net_1\, un3_cnv_runlto5_0, - \cnv_cycle_counter[4]_net_1\, - \cnv_cycle_counter[5]_net_1\, un2_cnv_runlto8_2, - \cnv_cycle_counter[2]_net_1\, - \cnv_cycle_counter[3]_net_1\, un2_cnv_runlto8_1, - \cnv_cycle_counter[6]_net_1\, un2_cnv_runlto8_0, N_30, - N_38, N_36, N_17, N_22, N_15, N_21, N_13, N_20, N_11, - un3_cnv_runlt6, cnv_cycle_counter_c2, un3_cnv_run, - un2_cnv_run, cnv_cycle_counter_n8, cnv_cycle_counter_33_0, - cnv_s_0_sqmuxa, cnv_cycle_counter_n7, - cnv_cycle_counter_c6, cnv_cycle_counter_n6, - cnv_cycle_counter_c5, cnv_cycle_counter_n5, - cnv_cycle_counter_c4, cnv_cycle_counter_n4, - cnv_cycle_counter_n4_tz_i, cnv_cycle_counter_n3, - cnv_cycle_counter_n3_tz_i, cnv_cycle_counter_n2, - cnv_cycle_counter_n2_tz_i, \cnv_cycle_counter[0]_net_1\, - \cnv_cycle_counter[1]_net_1\, N_23, - \sample_bit_counter[1]_net_1\, N_19, cnv_done_i, - cnv_run_sync, \sample_bit_counter[5]_net_1\, - \sample_bit_counter_RNI0D96[5]_net_1\, - cnv_cycle_counter_n1, cnv_cycle_counter_n0, \cnv_s_RNO\, - cnv_done_1, cnv_sync_r_i_0, cnv_sync, cnv_sync_i, - \sample_bit_counter[0]_net_1\, \shift_reg_6[0]_net_1\, - \shift_reg_6[1]_net_1\, \shift_reg_6[2]_net_1\, - \shift_reg_6[3]_net_1\, \shift_reg_6[4]_net_1\, - \shift_reg_6[5]_net_1\, \shift_reg_6[6]_net_1\, - \shift_reg_6[7]_net_1\, \shift_reg_6[8]_net_1\, - \shift_reg_6[9]_net_1\, \shift_reg_6[10]_net_1\, - \shift_reg_6[11]_net_1\, \shift_reg_6[12]_net_1\, - \shift_reg_6[13]_net_1\, \shift_reg_6[14]_net_1\, - \shift_reg_5[0]_net_1\, \shift_reg_5[1]_net_1\, - \shift_reg_5[2]_net_1\, \shift_reg_5[3]_net_1\, - \shift_reg_5[4]_net_1\, \shift_reg_5[5]_net_1\, - \shift_reg_5[6]_net_1\, \shift_reg_5[7]_net_1\, - \shift_reg_5[8]_net_1\, \shift_reg_5[9]_net_1\, - \shift_reg_5[10]_net_1\, \shift_reg_5[11]_net_1\, - \shift_reg_5[12]_net_1\, \shift_reg_5[13]_net_1\, - \shift_reg_5[14]_net_1\, \shift_reg_4[0]_net_1\, - \shift_reg_4[1]_net_1\, \shift_reg_4[2]_net_1\, - \shift_reg_4[3]_net_1\, \shift_reg_4[4]_net_1\, - \shift_reg_4[5]_net_1\, \shift_reg_4[6]_net_1\, - \shift_reg_4[7]_net_1\, \shift_reg_4[8]_net_1\, - \shift_reg_4[9]_net_1\, \shift_reg_4[10]_net_1\, - \shift_reg_4[11]_net_1\, \shift_reg_4[12]_net_1\, - \shift_reg_4[13]_net_1\, \shift_reg_4[14]_net_1\, - \shift_reg_3[0]_net_1\, \shift_reg_3[1]_net_1\, - \shift_reg_3[2]_net_1\, \shift_reg_3[3]_net_1\, - \shift_reg_3[4]_net_1\, \shift_reg_3[5]_net_1\, - \shift_reg_3[6]_net_1\, \shift_reg_3[7]_net_1\, - \shift_reg_3[8]_net_1\, \shift_reg_3[9]_net_1\, - \shift_reg_3[10]_net_1\, \shift_reg_3[11]_net_1\, - \shift_reg_3[12]_net_1\, \shift_reg_3[13]_net_1\, - \shift_reg_3[14]_net_1\, \shift_reg_2[0]_net_1\, - \shift_reg_2[1]_net_1\, \shift_reg_2[2]_net_1\, - \shift_reg_2[3]_net_1\, \shift_reg_2[4]_net_1\, - \shift_reg_2[5]_net_1\, \shift_reg_2[6]_net_1\, - \shift_reg_2[7]_net_1\, \shift_reg_2[8]_net_1\, - \shift_reg_2[9]_net_1\, \shift_reg_2[10]_net_1\, - \shift_reg_2[11]_net_1\, \shift_reg_2[12]_net_1\, - \shift_reg_2[13]_net_1\, \shift_reg_2[14]_net_1\, - \shift_reg_1[0]_net_1\, \shift_reg_1[1]_net_1\, - \shift_reg_1[2]_net_1\, \shift_reg_1[3]_net_1\, - \shift_reg_1[4]_net_1\, \shift_reg_1[5]_net_1\, - \shift_reg_1[6]_net_1\, \shift_reg_1[7]_net_1\, - \shift_reg_1[8]_net_1\, \shift_reg_1[9]_net_1\, - \shift_reg_1[10]_net_1\, \shift_reg_1[11]_net_1\, - \shift_reg_1[12]_net_1\, \shift_reg_1[13]_net_1\, - \shift_reg_1[14]_net_1\, \shift_reg_0[0]_net_1\, - \shift_reg_0[1]_net_1\, \shift_reg_0[2]_net_1\, - \shift_reg_0[3]_net_1\, \shift_reg_0[4]_net_1\, - \shift_reg_0[5]_net_1\, \shift_reg_0[6]_net_1\, - \shift_reg_0[7]_net_1\, \shift_reg_0[8]_net_1\, - \shift_reg_0[9]_net_1\, \shift_reg_0[10]_net_1\, - \shift_reg_0[11]_net_1\, \shift_reg_0[12]_net_1\, - \shift_reg_0[13]_net_1\, \shift_reg_0[14]_net_1\, - \shift_reg_7[0]_net_1\, \shift_reg_7[1]_net_1\, - \shift_reg_7[2]_net_1\, \shift_reg_7[3]_net_1\, - \shift_reg_7[4]_net_1\, \shift_reg_7[5]_net_1\, - \shift_reg_7[6]_net_1\, \shift_reg_7[7]_net_1\, - \shift_reg_7[8]_net_1\, \shift_reg_7[9]_net_1\, - \shift_reg_7[10]_net_1\, \shift_reg_7[11]_net_1\, - \shift_reg_7[12]_net_1\, \shift_reg_7[13]_net_1\, - \shift_reg_7[14]_net_1\, \cnv_c\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : SYNC_FF_1 - Use entity work.SYNC_FF_1(DEF_ARCH); - for all : SYNC_FF - Use entity work.SYNC_FF(DEF_ARCH); -begin - - cnv_c <= \cnv_c\; - - \sample_bit_counter[2]\ : DFN1E0C0 - port map(D => N_13, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[2]_net_1\); - - \shift_reg_0[1]\ : DFN1E1C0 - port map(D => \shift_reg_0[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[1]_net_1\); - - \cnv_cycle_counter_RNO_0[2]\ : AX1E - port map(A => \cnv_cycle_counter[0]_net_1\, B => - \cnv_cycle_counter[1]_net_1\, C => - \cnv_cycle_counter[2]_net_1\, Y => - cnv_cycle_counter_n2_tz_i); - - \shift_reg_7[14]\ : DFN1E1C0 - port map(D => \shift_reg_7[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[14]_net_1\); - - \sample_6[13]\ : DFN1E1 - port map(D => \shift_reg_6[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(13)); - - \sample_7[11]\ : DFN1E1 - port map(D => \shift_reg_7[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(11)); - - \sample_0[3]\ : DFN1E1 - port map(D => \shift_reg_0[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(3)); - - \shift_reg_6[12]\ : DFN1E1C0 - port map(D => \shift_reg_6[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[12]_net_1\); - - \sample_1[0]\ : DFN1E1 - port map(D => sdo_c(1), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(0)); - - \sample_0[12]\ : DFN1E1 - port map(D => \shift_reg_0[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(12)); - - \shift_reg_6[9]\ : DFN1E1C0 - port map(D => \shift_reg_6[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[9]_net_1\); - - \shift_reg_2[0]\ : DFN1E1C0 - port map(D => sdo_c(2), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[0]_net_1\); - - \shift_reg_5[11]\ : DFN1E1C0 - port map(D => \shift_reg_5[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_5[11]_net_1\); - - cnv_s : DFN1C0 - port map(D => \cnv_s_RNO\, CLK => cnv_clk_c, CLR => - cnv_rstn_c, Q => \cnv_c\); - - \sample_6[11]\ : DFN1E1 - port map(D => \shift_reg_6[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(11)); - - \sample_3[9]\ : DFN1E1 - port map(D => \shift_reg_3[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(9)); - - \shift_reg_0[10]\ : DFN1E1C0 - port map(D => \shift_reg_0[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[10]_net_1\); - - \shift_reg_7[6]\ : DFN1E1C0 - port map(D => \shift_reg_7[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[6]_net_1\); - - \shift_reg_7[2]\ : DFN1E1C0 - port map(D => \shift_reg_7[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[2]_net_1\); - - \sample_2[6]\ : DFN1E1 - port map(D => \shift_reg_2[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(6)); - - \cnv_cycle_counter[4]\ : DFN1C0 - port map(D => cnv_cycle_counter_n4, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[4]_net_1\); - - \cnv_cycle_counter_RNO[2]\ : NOR2 - port map(A => cnv_s_0_sqmuxa, B => - cnv_cycle_counter_n2_tz_i, Y => cnv_cycle_counter_n2); - - \sample_6[2]\ : DFN1E1 - port map(D => \shift_reg_6[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(2)); - - \sample_7[5]\ : DFN1E1 - port map(D => \shift_reg_7[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(5)); - - \shift_reg_5[6]\ : DFN1E1C0 - port map(D => \shift_reg_5[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[6]_net_1\); - - \shift_reg_0[14]\ : DFN1E1C0 - port map(D => \shift_reg_0[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[14]_net_1\); - - \shift_reg_1[7]\ : DFN1E1C0 - port map(D => \shift_reg_1[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[7]_net_1\); - - \sample_0[15]\ : DFN1E1 - port map(D => \shift_reg_0[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(15)); - - \sample_2[4]\ : DFN1E1 - port map(D => \shift_reg_2[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(4)); - - \sample_bit_counter_RNO[3]\ : XA1B - port map(A => N_21, B => \sample_bit_counter[3]_net_1\, C - => N_36, Y => N_15); - - \sample_1[6]\ : DFN1E1 - port map(D => \shift_reg_1[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(6)); - - \cnv_cycle_counter_RNO[8]\ : XA1C - port map(A => \cnv_cycle_counter[8]_net_1\, B => - cnv_cycle_counter_33_0, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n8); - - \sample_2[14]\ : DFN1E1 - port map(D => \shift_reg_2[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(14)); - - \sample_5[10]\ : DFN1E1 - port map(D => \shift_reg_5[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(10)); - - \sample_2[0]\ : DFN1E1 - port map(D => sdo_c(2), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(0)); - - \sample_5[1]\ : DFN1E1 - port map(D => \shift_reg_5[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(1)); - - \shift_reg_4[13]\ : DFN1E1C0 - port map(D => \shift_reg_4[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[13]_net_1\); - - \cnv_cycle_counter_RNO[1]\ : XA1B - port map(A => \cnv_cycle_counter[1]_net_1\, B => - \cnv_cycle_counter[0]_net_1\, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n1); - - \shift_reg_7[5]\ : DFN1E1C0 - port map(D => \shift_reg_7[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[5]_net_1\); - - \sample_0[7]\ : DFN1E1 - port map(D => \shift_reg_0[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(7)); - - \sample_0[13]\ : DFN1E1 - port map(D => \shift_reg_0[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(13)); - - \shift_reg_1[10]\ : DFN1E1C0 - port map(D => \shift_reg_1[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_1[10]_net_1\); - - \sample_6[3]\ : DFN1E1 - port map(D => \shift_reg_6[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(3)); - - \shift_reg_1[5]\ : DFN1E1C0 - port map(D => \shift_reg_1[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[5]_net_1\); - - \shift_reg_5[1]\ : DFN1E1C0 - port map(D => \shift_reg_5[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[1]_net_1\); - - \shift_reg_1[14]\ : DFN1E1C0 - port map(D => \shift_reg_1[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[14]_net_1\); - - cnv_done_RNO : OR2 - port map(A => cnv_sync_r_i_0, B => cnv_sync, Y => - cnv_done_1); - - \shift_reg_6[2]\ : DFN1E1C0 - port map(D => \shift_reg_6[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[2]_net_1\); - - \shift_reg_3[5]\ : DFN1E1C0 - port map(D => \shift_reg_3[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[5]_net_1\); - - cnv_done_RNI4H78 : AOI1B - port map(A => \sample_bit_counter_0[0]_net_1\, B => - cnv_done_i, C => cnv_run_sync, Y => sample_bit_counter_n0); - - \sample_7[6]\ : DFN1E1 - port map(D => \shift_reg_7[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(6)); - - \sample_7[10]\ : DFN1E1 - port map(D => \shift_reg_7[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(10)); - - \sample_6[6]\ : DFN1E1 - port map(D => \shift_reg_6[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(6)); - - \sample_0[11]\ : DFN1E1 - port map(D => \shift_reg_0[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(11)); - - \shift_reg_0[0]\ : DFN1E1C0 - port map(D => sdo_c(0), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[0]_net_1\); - - \sample_0[0]\ : DFN1E1 - port map(D => sdo_c(0), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(0)); - - \sample_5[4]\ : DFN1E1 - port map(D => \shift_reg_5[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(4)); - - \sample_7[9]\ : DFN1E1 - port map(D => \shift_reg_7[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(9)); - - \sample_4[9]\ : DFN1E1 - port map(D => \shift_reg_4[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(9)); - - \cnv_cycle_counter[6]\ : DFN1C0 - port map(D => cnv_cycle_counter_n6, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[6]_net_1\); - - \shift_reg_2[12]\ : DFN1E1C0 - port map(D => \shift_reg_2[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[12]_net_1\); - - \sample_bit_counter_1[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_1[0]_net_1\); - - \sample_5[9]\ : DFN1E1 - port map(D => \shift_reg_5[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(9)); - - \shift_reg_7[0]\ : DFN1E1C0 - port map(D => sdo_c(7), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[0]_net_1\); - - SYNC_FF_run : SYNC_FF_1 - port map(cnv_run_c => cnv_run_c, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, cnv_run_sync => cnv_run_sync); - - \shift_reg_1[1]\ : DFN1E1C0 - port map(D => \shift_reg_1[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[1]_net_1\); - - \shift_reg_3[9]\ : DFN1E1C0 - port map(D => \shift_reg_3[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_3[9]_net_1\); - - \sample_5[7]\ : DFN1E1 - port map(D => \shift_reg_5[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(7)); - - \sample_bit_counter[5]\ : DFN1E0C0 - port map(D => N_19, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[5]_net_1\); - - \sample_6[10]\ : DFN1E1 - port map(D => \shift_reg_6[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(10)); - - \sample_3[12]\ : DFN1E1 - port map(D => \shift_reg_3[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(12)); - - \shift_reg_3[6]\ : DFN1E1C0 - port map(D => \shift_reg_3[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[6]_net_1\); - - \sample_5[0]\ : DFN1E1 - port map(D => sdo_c(5), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(0)); - - \sample_4[7]\ : DFN1E1 - port map(D => \shift_reg_4[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(7)); - - \shift_reg_0[5]\ : DFN1E1C0 - port map(D => \shift_reg_0[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[5]_net_1\); - - \sample_bit_counter[4]\ : DFN1E0C0 - port map(D => N_17, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[4]_net_1\); - - \sample_4[12]\ : DFN1E1 - port map(D => \shift_reg_4[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(12)); - - \sample_2[7]\ : DFN1E1 - port map(D => \shift_reg_2[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(7)); - - \shift_reg_7[8]\ : DFN1E1C0 - port map(D => \shift_reg_7[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[8]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \sample_bit_counter_RNID104[3]\ : NOR2B - port map(A => \sample_bit_counter[3]_net_1\, B => N_21, Y - => N_22); - - \shift_reg_0[3]\ : DFN1E1C0 - port map(D => \shift_reg_0[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[3]_net_1\); - - \sample_bit_counter_RNILHR2[2]\ : NOR2B - port map(A => \sample_bit_counter[2]_net_1\, B => N_20, Y - => N_21); - - \sample_bit_counter_RNIOIIL[5]\ : AO1A - port map(A => N_36, B => \sample_bit_counter[5]_net_1\, C - => N_30, Y => N_6); - - \shift_reg_6[11]\ : DFN1E1C0 - port map(D => \shift_reg_6[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[11]_net_1\); - - \sample_3[15]\ : DFN1E1 - port map(D => \shift_reg_3[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(15)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \shift_reg_3[8]\ : DFN1E1C0 - port map(D => \shift_reg_3[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[8]_net_1\); - - \shift_reg_4[10]\ : DFN1E1C0 - port map(D => \shift_reg_4[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[10]_net_1\); - - \sample_4[15]\ : DFN1E1 - port map(D => \shift_reg_4[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(15)); - - \shift_reg_5[13]\ : DFN1E1C0 - port map(D => \shift_reg_5[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_5[13]_net_1\); - - \shift_reg_3[7]\ : DFN1E1C0 - port map(D => \shift_reg_3[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[7]_net_1\); - - \sample_0[2]\ : DFN1E1 - port map(D => \shift_reg_0[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(2)); - - \cnv_cycle_counter_RNITOET[2]\ : OR2B - port map(A => un2_cnv_run, B => cnv_run_c, Y => - cnv_s_0_sqmuxa); - - \shift_reg_4[14]\ : DFN1E1C0 - port map(D => \shift_reg_4[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[14]_net_1\); - - \sample_bit_counter_RNI8FD3[2]\ : NOR3 - port map(A => \sample_bit_counter[3]_net_1\, B => - \sample_bit_counter[2]_net_1\, C => - \sample_bit_counter[4]_net_1\, Y => - sample_bit_counterlde_i_a3_0_1); - - \sample_0[5]\ : DFN1E1 - port map(D => \shift_reg_0[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(5)); - - \sample_3[13]\ : DFN1E1 - port map(D => \shift_reg_3[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(13)); - - \sample_bit_counter_RNIVMI9_0[5]\ : CLKINT - port map(A => \sample_bit_counter_RNIVMI9[5]_net_1\, Y => - sample_0_0_sqmuxa); - - \sample_2[5]\ : DFN1E1 - port map(D => \shift_reg_2[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(5)); - - \shift_reg_2[5]\ : DFN1E1C0 - port map(D => \shift_reg_2[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[5]_net_1\); - - \sample_4[13]\ : DFN1E1 - port map(D => \shift_reg_4[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(13)); - - \sample_3[1]\ : DFN1E1 - port map(D => \shift_reg_3[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(1)); - - \sample_0[1]\ : DFN1E1 - port map(D => \shift_reg_0[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(1)); - - \sample_0[10]\ : DFN1E1 - port map(D => \shift_reg_0[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(10)); - - \shift_reg_0[2]\ : DFN1E1C0 - port map(D => \shift_reg_0[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[2]_net_1\); - - \sample_2[12]\ : DFN1E1 - port map(D => \shift_reg_2[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(12)); - - \sample_6[0]\ : DFN1E1 - port map(D => sdo_c(6), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(0)); - - \shift_reg_3[12]\ : DFN1E1C0 - port map(D => \shift_reg_3[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[12]_net_1\); - - \sample_val\ : DFN1C0 - port map(D => \sample_bit_counter_RNI0D96[5]_net_1\, CLK - => HCLK_c, CLR => HRESETn_c, Q => sample_val); - - \cnv_cycle_counter_RNO[3]\ : NOR2 - port map(A => cnv_s_0_sqmuxa, B => - cnv_cycle_counter_n3_tz_i, Y => cnv_cycle_counter_n3); - - \sample_3[11]\ : DFN1E1 - port map(D => \shift_reg_3[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(11)); - - \sample_0[9]\ : DFN1E1 - port map(D => \shift_reg_0[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(9)); - - \shift_reg_5[8]\ : DFN1E1C0 - port map(D => \shift_reg_5[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[8]_net_1\); - - \sample_bit_counter_RNO[4]\ : XA1B - port map(A => N_22, B => \sample_bit_counter[4]_net_1\, C - => N_36, Y => N_17); - - \cnv_cycle_counter[3]\ : DFN1C0 - port map(D => cnv_cycle_counter_n3, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[3]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_4[11]\ : DFN1E1 - port map(D => \shift_reg_4[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(11)); - - \shift_reg_7[12]\ : DFN1E1C0 - port map(D => \shift_reg_7[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[12]_net_1\); - - \sample_6[7]\ : DFN1E1 - port map(D => \shift_reg_6[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(7)); - - \sample_2[9]\ : DFN1E1 - port map(D => \shift_reg_2[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(9)); - - \cnv_cycle_counter_RNO_0[8]\ : OR2B - port map(A => cnv_cycle_counter_c6, B => - \cnv_cycle_counter[7]_net_1\, Y => cnv_cycle_counter_33_0); - - \shift_reg_6[1]\ : DFN1E1C0 - port map(D => \shift_reg_6[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[1]_net_1\); - - \shift_reg_7[7]\ : DFN1E1C0 - port map(D => \shift_reg_7[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[7]_net_1\); - - \sample_2[15]\ : DFN1E1 - port map(D => \shift_reg_2[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(15)); - - \sample_bit_counter_0[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_0[0]_net_1\); - - \shift_reg_6[3]\ : DFN1E1C0 - port map(D => \shift_reg_6[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[3]_net_1\); - - \sample_6[4]\ : DFN1E1 - port map(D => \shift_reg_6[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(4)); - - \sample_4[3]\ : DFN1E1 - port map(D => \shift_reg_4[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(3)); - - \sample_1[9]\ : DFN1E1 - port map(D => \shift_reg_1[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(9)); - - \cnv_cycle_counter_RNO_0[4]\ : AX1E - port map(A => \cnv_cycle_counter[3]_net_1\, B => - cnv_cycle_counter_c2, C => \cnv_cycle_counter[4]_net_1\, - Y => cnv_cycle_counter_n4_tz_i); - - \shift_reg_5[5]\ : DFN1E1C0 - port map(D => \shift_reg_5[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[5]_net_1\); - - \cnv_cycle_counter[7]\ : DFN1C0 - port map(D => cnv_cycle_counter_n7, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[7]_net_1\); - - \sample_1[14]\ : DFN1E1 - port map(D => \shift_reg_1[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(14)); - - \shift_reg_2[11]\ : DFN1E1C0 - port map(D => \shift_reg_2[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[11]_net_1\); - - \shift_reg_7[3]\ : DFN1E1C0 - port map(D => \shift_reg_7[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[3]_net_1\); - - \shift_reg_5[10]\ : DFN1E1C0 - port map(D => \shift_reg_5[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_5[10]_net_1\); - - \shift_reg_3[4]\ : DFN1E1C0 - port map(D => \shift_reg_3[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[4]_net_1\); - - \sample_2[13]\ : DFN1E1 - port map(D => \shift_reg_2[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(13)); - - \sample_bit_counter_RNI0D96[5]\ : NOR2 - port map(A => \sample_bit_counter[5]_net_1\, B => N_23, Y - => \sample_bit_counter_RNI0D96[5]_net_1\); - - \sample_3[0]\ : DFN1E1 - port map(D => sdo_c(3), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(0)); - - \shift_reg_0[12]\ : DFN1E1C0 - port map(D => \shift_reg_0[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[12]_net_1\); - - \sample_4[2]\ : DFN1E1 - port map(D => \shift_reg_4[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(2)); - - \sample_bit_counter[1]\ : DFN1E0C0 - port map(D => N_11, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[1]_net_1\); - - \shift_reg_5[14]\ : DFN1E1C0 - port map(D => \shift_reg_5[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[14]_net_1\); - - \sample_7[0]\ : DFN1E1 - port map(D => sdo_c(7), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(0)); - - \sample_bit_counter_RNI28PC[2]\ : NOR3B - port map(A => sample_bit_counterlde_i_a3_0_1, B => N_38, C - => N_36, Y => N_30); - - \sample_2[3]\ : DFN1E1 - port map(D => \shift_reg_2[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(3)); - - \sample_3[7]\ : DFN1E1 - port map(D => \shift_reg_3[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(7)); - - \sample_7[1]\ : DFN1E1 - port map(D => \shift_reg_7[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(1)); - - \sample_2[11]\ : DFN1E1 - port map(D => \shift_reg_2[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(11)); - - cnv_sync_r : DFN1P0 - port map(D => cnv_sync_i, CLK => HCLK_c, PRE => HRESETn_c, - Q => cnv_sync_r_i_0); - - \cnv_cycle_counter_RNI6D3R[6]\ : NOR2A - port map(A => \cnv_cycle_counter[6]_net_1\, B => - cnv_cycle_counter_c5, Y => cnv_cycle_counter_c6); - - \shift_reg_1[9]\ : DFN1E1C0 - port map(D => \shift_reg_1[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[9]_net_1\); - - \shift_reg_6[13]\ : DFN1E1C0 - port map(D => \shift_reg_6[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[13]_net_1\); - - \sample_6[1]\ : DFN1E1 - port map(D => \shift_reg_6[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(1)); - - \shift_reg_0[8]\ : DFN1E1C0 - port map(D => \shift_reg_0[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[8]_net_1\); - - \sample_3[10]\ : DFN1E1 - port map(D => \shift_reg_3[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(10)); - - \shift_reg_4[0]\ : DFN1E1C0 - port map(D => sdo_c(4), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[0]_net_1\); - - SYNC_FF_cnv : SYNC_FF - port map(cnv_c => \cnv_c\, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c, cnv_sync => cnv_sync, cnv_sync_i => - cnv_sync_i); - - \shift_reg_2[2]\ : DFN1E1C0 - port map(D => \shift_reg_2[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[2]_net_1\); - - \sample_bit_counter_RNIU5N1_0[1]\ : NOR2 - port map(A => \sample_bit_counter[1]_net_1\, B => - \sample_bit_counter_0[0]_net_1\, Y => N_38); - - \shift_reg_1[3]\ : DFN1E1C0 - port map(D => \shift_reg_1[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[3]_net_1\); - - \shift_reg_1[12]\ : DFN1E1C0 - port map(D => \shift_reg_1[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[12]_net_1\); - - \sample_7[2]\ : DFN1E1 - port map(D => \shift_reg_7[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(2)); - - \sample_4[10]\ : DFN1E1 - port map(D => \shift_reg_4[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(10)); - - \sample_bit_counter_RNIU5N1[1]\ : NOR2B - port map(A => \sample_bit_counter[1]_net_1\, B => - \sample_bit_counter_0[0]_net_1\, Y => N_20); - - \sample_3[8]\ : DFN1E1 - port map(D => \shift_reg_3[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(8)); - - \shift_reg_3[3]\ : DFN1E1C0 - port map(D => \shift_reg_3[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[3]_net_1\); - - \shift_reg_1[8]\ : DFN1E1C0 - port map(D => \shift_reg_1[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[8]_net_1\); - - \sample_bit_counter_3[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_3[0]_net_1\); - - \cnv_cycle_counter[8]\ : DFN1C0 - port map(D => cnv_cycle_counter_n8, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[8]_net_1\); - - \sample_bit_counter[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter[0]_net_1\); - - \sample_1[1]\ : DFN1E1 - port map(D => \shift_reg_1[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(1)); - - \shift_reg_4[1]\ : DFN1E1C0 - port map(D => \shift_reg_4[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[1]_net_1\); - - \cnv_cycle_counter_RNO[0]\ : NOR2 - port map(A => \cnv_cycle_counter[0]_net_1\, B => - cnv_s_0_sqmuxa, Y => cnv_cycle_counter_n0); - - \sample_5[14]\ : DFN1E1 - port map(D => \shift_reg_5[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(14)); - - \cnv_cycle_counter_RNIQQN7[8]\ : NOR2B - port map(A => \cnv_cycle_counter[8]_net_1\, B => - \cnv_cycle_counter[4]_net_1\, Y => un2_cnv_runlto8_0); - - \shift_reg_3[1]\ : DFN1E1C0 - port map(D => \shift_reg_3[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[1]_net_1\); - - \shift_reg_2[8]\ : DFN1E1C0 - port map(D => \shift_reg_2[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[8]_net_1\); - - \sample_2[8]\ : DFN1E1 - port map(D => \shift_reg_2[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(8)); - - \shift_reg_3[11]\ : DFN1E1C0 - port map(D => \shift_reg_3[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[11]_net_1\); - - \shift_reg_0[4]\ : DFN1E1C0 - port map(D => \shift_reg_0[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[4]_net_1\); - - \sample_4[5]\ : DFN1E1 - port map(D => \shift_reg_4[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(5)); - - \sample_0[4]\ : DFN1E1 - port map(D => \shift_reg_0[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(4)); - - \shift_reg_7[11]\ : DFN1E1C0 - port map(D => \shift_reg_7[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[11]_net_1\); - - \shift_reg_3[0]\ : DFN1E1C0 - port map(D => sdo_c(3), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[0]_net_1\); - - \sample_3[4]\ : DFN1E1 - port map(D => \shift_reg_3[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(4)); - - \sample_5[5]\ : DFN1E1 - port map(D => \shift_reg_5[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(5)); - - \shift_reg_1[0]\ : DFN1E1C0 - port map(D => sdo_c(1), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_1[0]_net_1\); - - \shift_reg_4[9]\ : DFN1E1C0 - port map(D => \shift_reg_4[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[9]_net_1\); - - \shift_reg_1[6]\ : DFN1E1C0 - port map(D => \shift_reg_1[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[6]_net_1\); - - \sample_4[1]\ : DFN1E1 - port map(D => \shift_reg_4[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(1)); - - \shift_reg_2[9]\ : DFN1E1C0 - port map(D => \shift_reg_2[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[9]_net_1\); - - cnv_done_RNISIK7 : OR2B - port map(A => cnv_run_sync, B => cnv_done_i, Y => N_36); - - \shift_reg_4[2]\ : DFN1E1C0 - port map(D => \shift_reg_4[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[2]_net_1\); - - \sample_7[8]\ : DFN1E1 - port map(D => \shift_reg_7[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(8)); - - \sample_7[14]\ : DFN1E1 - port map(D => \shift_reg_7[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(14)); - - \sample_2[10]\ : DFN1E1 - port map(D => \shift_reg_2[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(10)); - - \shift_reg_6[10]\ : DFN1E1C0 - port map(D => \shift_reg_6[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[10]_net_1\); - - \shift_reg_3[2]\ : DFN1E1C0 - port map(D => \shift_reg_3[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[2]_net_1\); - - \shift_reg_4[12]\ : DFN1E1C0 - port map(D => \shift_reg_4[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[12]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \shift_reg_7[4]\ : DFN1E1C0 - port map(D => \shift_reg_7[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[4]_net_1\); - - \shift_reg_2[13]\ : DFN1E1C0 - port map(D => \shift_reg_2[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[13]_net_1\); - - \sample_6[5]\ : DFN1E1 - port map(D => \shift_reg_6[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(5)); - - \shift_reg_6[14]\ : DFN1E1C0 - port map(D => \shift_reg_6[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[14]_net_1\); - - \cnv_cycle_counter_RNO[6]\ : XA1C - port map(A => \cnv_cycle_counter[6]_net_1\, B => - cnv_cycle_counter_c5, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n6); - - \sample_bit_counter_2[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_2[0]_net_1\); - - \sample_5[2]\ : DFN1E1 - port map(D => \shift_reg_5[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(2)); - - \sample_5[8]\ : DFN1E1 - port map(D => \shift_reg_5[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(8)); - - \sample_1[12]\ : DFN1E1 - port map(D => \shift_reg_1[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(12)); - - \shift_reg_2[6]\ : DFN1E1C0 - port map(D => \shift_reg_2[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[6]_net_1\); - - \shift_reg_0[11]\ : DFN1E1C0 - port map(D => \shift_reg_0[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[11]_net_1\); - - \sample_6[14]\ : DFN1E1 - port map(D => \shift_reg_6[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(14)); - - cnv_s_RNO_0 : OA1C - port map(A => \cnv_cycle_counter[6]_net_1\, B => - un3_cnv_runlt6, C => un3_cnv_runlto8_0, Y => un3_cnv_run); - - \shift_reg_4[8]\ : DFN1E1C0 - port map(D => \shift_reg_4[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[8]_net_1\); - - cnv_s_RNO_1 : AOI1 - port map(A => cnv_cycle_counter_c2, B => - \cnv_cycle_counter[3]_net_1\, C => un3_cnv_runlto5_0, Y - => un3_cnv_runlt6); - - \cnv_cycle_counter[2]\ : DFN1C0 - port map(D => cnv_cycle_counter_n2, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[2]_net_1\); - - \sample_7[7]\ : DFN1E1 - port map(D => \shift_reg_7[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(7)); - - \sample_3[5]\ : DFN1E1 - port map(D => \shift_reg_3[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(5)); - - \shift_reg_7[1]\ : DFN1E1C0 - port map(D => \shift_reg_7[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[1]_net_1\); - - \sample_7[3]\ : DFN1E1 - port map(D => \shift_reg_7[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(3)); - - \sample_3[6]\ : DFN1E1 - port map(D => \shift_reg_3[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(6)); - - \cnv_cycle_counter_RNO[5]\ : XA1B - port map(A => \cnv_cycle_counter[5]_net_1\, B => - cnv_cycle_counter_c4, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n5); - - \shift_reg_5[9]\ : DFN1E1C0 - port map(D => \shift_reg_5[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[9]_net_1\); - - \shift_reg_4[6]\ : DFN1E1C0 - port map(D => \shift_reg_4[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[6]_net_1\); - - \shift_reg_1[4]\ : DFN1E1C0 - port map(D => \shift_reg_1[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[4]_net_1\); - - \cnv_cycle_counter_RNIPQN7[5]\ : NOR2B - port map(A => \cnv_cycle_counter[5]_net_1\, B => - \cnv_cycle_counter[6]_net_1\, Y => un2_cnv_runlto8_1); - - \shift_reg_4[5]\ : DFN1E1C0 - port map(D => \shift_reg_4[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[5]_net_1\); - - \sample_2[1]\ : DFN1E1 - port map(D => \shift_reg_2[0]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(1)); - - \sample_1[15]\ : DFN1E1 - port map(D => \shift_reg_1[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(15)); - - sck : DFN1P0 - port map(D => \sample_bit_counter_i[0]\, CLK => HCLK_c, PRE - => HRESETn_c, Q => sck_c); - - \shift_reg_6[8]\ : DFN1E1C0 - port map(D => \shift_reg_6[7]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[8]_net_1\); - - \shift_reg_5[4]\ : DFN1E1C0 - port map(D => \shift_reg_5[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[4]_net_1\); - - \cnv_cycle_counter_RNO[4]\ : NOR2 - port map(A => cnv_s_0_sqmuxa, B => - cnv_cycle_counter_n4_tz_i, Y => cnv_cycle_counter_n4); - - \sample_bit_counter_RNO[2]\ : XA1B - port map(A => N_20, B => \sample_bit_counter[2]_net_1\, C - => N_36, Y => N_13); - - \sample_5[6]\ : DFN1E1 - port map(D => \shift_reg_5[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(6)); - - \sample_bit_counter_4[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => HCLK_c, CLR => - HRESETn_c, E => N_6, Q => \sample_bit_counter_4[0]_net_1\); - - \shift_reg_0[6]\ : DFN1E1C0 - port map(D => \shift_reg_0[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[6]_net_1\); - - \sample_1[3]\ : DFN1E1 - port map(D => \shift_reg_1[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(3)); - - \cnv_cycle_counter_RNIONJB[1]\ : NOR3C - port map(A => \cnv_cycle_counter[0]_net_1\, B => - \cnv_cycle_counter[1]_net_1\, C => - \cnv_cycle_counter[2]_net_1\, Y => cnv_cycle_counter_c2); - - \shift_reg_5[3]\ : DFN1E1C0 - port map(D => \shift_reg_5[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[3]_net_1\); - - \sample_3[2]\ : DFN1E1 - port map(D => \shift_reg_3[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(2)); - - \sample_5[3]\ : DFN1E1 - port map(D => \shift_reg_5[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(3)); - - \shift_reg_1[11]\ : DFN1E1C0 - port map(D => \shift_reg_1[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[11]_net_1\); - - \sample_bit_counter_RNO[5]\ : NOR2 - port map(A => N_36, B => N_23, Y => N_19); - - \cnv_cycle_counter[5]\ : DFN1C0 - port map(D => cnv_cycle_counter_n5, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[5]_net_1\); - - \sample_1[7]\ : DFN1E1 - port map(D => \shift_reg_1[6]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(7)); - - \sample_1[13]\ : DFN1E1 - port map(D => \shift_reg_1[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(13)); - - sck_RNO : INV - port map(A => \sample_bit_counter_0[0]_net_1\, Y => - \sample_bit_counter_i[0]\); - - \shift_reg_5[2]\ : DFN1E1C0 - port map(D => \shift_reg_5[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[2]_net_1\); - - \sample_bit_counter_RNO[1]\ : NOR3 - port map(A => N_38, B => N_36, C => N_20, Y => N_11); - - \sample_6[8]\ : DFN1E1 - port map(D => \shift_reg_6[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(8)); - - \sample_1[2]\ : DFN1E1 - port map(D => \shift_reg_1[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(2)); - - \sample_bit_counter_RNI6L45[4]\ : OR2B - port map(A => \sample_bit_counter[4]_net_1\, B => N_22, Y - => N_23); - - \cnv_cycle_counter_RNIKD3R[2]\ : OR3C - port map(A => un2_cnv_runlto8_1, B => un2_cnv_runlto8_0, C - => un2_cnv_runlto8_2, Y => un2_cnv_run); - - \sample_0[8]\ : DFN1E1 - port map(D => \shift_reg_0[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(8)); - - \sample_0[14]\ : DFN1E1 - port map(D => \shift_reg_0[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(14)); - - \sample_5[12]\ : DFN1E1 - port map(D => \shift_reg_5[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(12)); - - \shift_reg_0[9]\ : DFN1E1C0 - port map(D => \shift_reg_0[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[9]_net_1\); - - \sample_bit_counter_RNIVMI9[5]\ : NOR2B - port map(A => \sample_bit_counter_RNI0D96[5]_net_1\, B => - HRESETn_c, Y => \sample_bit_counter_RNIVMI9[5]_net_1\); - - \sample_1[11]\ : DFN1E1 - port map(D => \shift_reg_1[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(11)); - - \shift_reg_5[7]\ : DFN1E1C0 - port map(D => \shift_reg_5[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_5[7]_net_1\); - - \sample_0[6]\ : DFN1E1 - port map(D => \shift_reg_0[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_0(6)); - - \shift_reg_2[10]\ : DFN1E1C0 - port map(D => \shift_reg_2[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[10]_net_1\); - - \shift_reg_5[12]\ : DFN1E1C0 - port map(D => \shift_reg_5[11]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_5[12]_net_1\); - - \shift_reg_3[13]\ : DFN1E1C0 - port map(D => \shift_reg_3[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[13]_net_1\); - - cnv_done : DFN1P0 - port map(D => cnv_done_1, CLK => HCLK_c, PRE => HRESETn_c, - Q => cnv_done_i); - - \shift_reg_2[1]\ : DFN1E1C0 - port map(D => \shift_reg_2[0]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[1]_net_1\); - - \sample_7[4]\ : DFN1E1 - port map(D => \shift_reg_7[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(4)); - - \sample_4[6]\ : DFN1E1 - port map(D => \shift_reg_4[5]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(6)); - - \shift_reg_1[2]\ : DFN1E1C0 - port map(D => \shift_reg_1[1]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[2]_net_1\); - - cnv_s_RNO_3 : OR2 - port map(A => \cnv_cycle_counter[4]_net_1\, B => - \cnv_cycle_counter[5]_net_1\, Y => un3_cnv_runlto5_0); - - \shift_reg_7[13]\ : DFN1E1C0 - port map(D => \shift_reg_7[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[13]_net_1\); - - \shift_reg_2[14]\ : DFN1E1C0 - port map(D => \shift_reg_2[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_2[14]_net_1\); - - \cnv_cycle_counter_RNIDIBJ[4]\ : NOR3C - port map(A => \cnv_cycle_counter[3]_net_1\, B => - cnv_cycle_counter_c2, C => \cnv_cycle_counter[4]_net_1\, - Y => cnv_cycle_counter_c4); - - \shift_reg_6[5]\ : DFN1E1C0 - port map(D => \shift_reg_6[4]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[5]_net_1\); - - \sample_4[8]\ : DFN1E1 - port map(D => \shift_reg_4[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(8)); - - \sample_5[15]\ : DFN1E1 - port map(D => \shift_reg_5[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(15)); - - \shift_reg_2[3]\ : DFN1E1C0 - port map(D => \shift_reg_2[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[3]_net_1\); - - cnv_s_RNO : OA1A - port map(A => un2_cnv_run, B => un3_cnv_run, C => cnv_run_c, - Y => \cnv_s_RNO\); - - \shift_reg_6[0]\ : DFN1E1C0 - port map(D => sdo_c(6), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[0]_net_1\); - - \cnv_cycle_counter[0]\ : DFN1C0 - port map(D => cnv_cycle_counter_n0, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[0]_net_1\); - - \shift_reg_2[7]\ : DFN1E1C0 - port map(D => \shift_reg_2[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[7]_net_1\); - - \shift_reg_6[4]\ : DFN1E1C0 - port map(D => \shift_reg_6[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_4[0]_net_1\, Q - => \shift_reg_6[4]_net_1\); - - \shift_reg_2[4]\ : DFN1E1C0 - port map(D => \shift_reg_2[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_2[4]_net_1\); - - \sample_6[9]\ : DFN1E1 - port map(D => \shift_reg_6[8]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(9)); - - \shift_reg_4[4]\ : DFN1E1C0 - port map(D => \shift_reg_4[3]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[4]_net_1\); - - \sample_7[12]\ : DFN1E1 - port map(D => \shift_reg_7[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(12)); - - \cnv_cycle_counter_RNIPF7N[5]\ : OR2B - port map(A => cnv_cycle_counter_c4, B => - \cnv_cycle_counter[5]_net_1\, Y => cnv_cycle_counter_c5); - - \shift_reg_4[3]\ : DFN1E1C0 - port map(D => \shift_reg_4[2]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[3]_net_1\); - - \shift_reg_4[11]\ : DFN1E1C0 - port map(D => \shift_reg_4[10]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[11]_net_1\); - - \sample_bit_counter[3]\ : DFN1E0C0 - port map(D => N_15, CLK => HCLK_c, CLR => HRESETn_c, E => - N_6, Q => \sample_bit_counter[3]_net_1\); - - \cnv_cycle_counter_RNI1OJB[2]\ : OA1 - port map(A => \cnv_cycle_counter[2]_net_1\, B => - \cnv_cycle_counter[3]_net_1\, C => - \cnv_cycle_counter[7]_net_1\, Y => un2_cnv_runlto8_2); - - \sample_5[13]\ : DFN1E1 - port map(D => \shift_reg_5[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(13)); - - \shift_reg_0[7]\ : DFN1E1C0 - port map(D => \shift_reg_0[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[7]_net_1\); - - cnv_s_RNO_2 : OR2 - port map(A => \cnv_cycle_counter[8]_net_1\, B => - \cnv_cycle_counter[7]_net_1\, Y => un3_cnv_runlto8_0); - - \shift_reg_0[13]\ : DFN1E1C0 - port map(D => \shift_reg_0[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_0[0]_net_1\, Q - => \shift_reg_0[13]_net_1\); - - \sample_2[2]\ : DFN1E1 - port map(D => \shift_reg_2[1]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_2(2)); - - \sample_1[8]\ : DFN1E1 - port map(D => \shift_reg_1[7]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(8)); - - \sample_1[5]\ : DFN1E1 - port map(D => \shift_reg_1[4]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(5)); - - \sample_6[12]\ : DFN1E1 - port map(D => \shift_reg_6[11]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(12)); - - \cnv_cycle_counter_RNO[7]\ : XA1B - port map(A => \cnv_cycle_counter[7]_net_1\, B => - cnv_cycle_counter_c6, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n7); - - \sample_7[15]\ : DFN1E1 - port map(D => \shift_reg_7[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(15)); - - \sample_4[0]\ : DFN1E1 - port map(D => sdo_c(4), CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(0)); - - \shift_reg_5[0]\ : DFN1E1C0 - port map(D => sdo_c(5), CLK => HCLK_c, CLR => HRESETn_c, E - => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[0]_net_1\); - - \sample_3[3]\ : DFN1E1 - port map(D => \shift_reg_3[2]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(3)); - - \sample_5[11]\ : DFN1E1 - port map(D => \shift_reg_5[10]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_5(11)); - - \shift_reg_4[7]\ : DFN1E1C0 - port map(D => \shift_reg_4[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_3[0]_net_1\, Q - => \shift_reg_4[7]_net_1\); - - \shift_reg_6[6]\ : DFN1E1C0 - port map(D => \shift_reg_6[5]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[6]_net_1\); - - \sample_4[4]\ : DFN1E1 - port map(D => \shift_reg_4[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(4)); - - \sample_6[15]\ : DFN1E1 - port map(D => \shift_reg_6[14]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_6(15)); - - \shift_reg_3[10]\ : DFN1E1C0 - port map(D => \shift_reg_3[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[10]_net_1\); - - \sample_1[10]\ : DFN1E1 - port map(D => \shift_reg_1[9]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(10)); - - \sample_3[14]\ : DFN1E1 - port map(D => \shift_reg_3[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_3(14)); - - \sample_7[13]\ : DFN1E1 - port map(D => \shift_reg_7[12]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_7(13)); - - \shift_reg_7[9]\ : DFN1E1C0 - port map(D => \shift_reg_7[8]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[9]_net_1\); - - \sample_1[4]\ : DFN1E1 - port map(D => \shift_reg_1[3]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_1(4)); - - \cnv_cycle_counter_RNO_0[3]\ : XNOR2 - port map(A => cnv_cycle_counter_c2, B => - \cnv_cycle_counter[3]_net_1\, Y => - cnv_cycle_counter_n3_tz_i); - - \cnv_cycle_counter[1]\ : DFN1C0 - port map(D => cnv_cycle_counter_n1, CLK => cnv_clk_c, CLR - => cnv_rstn_c, Q => \cnv_cycle_counter[1]_net_1\); - - \shift_reg_7[10]\ : DFN1E1C0 - port map(D => \shift_reg_7[9]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[10]_net_1\); - - \sample_4[14]\ : DFN1E1 - port map(D => \shift_reg_4[13]_net_1\, CLK => HCLK_c, E => - sample_0_0_sqmuxa, Q => sample_4(14)); - - \shift_reg_6[7]\ : DFN1E1C0 - port map(D => \shift_reg_6[6]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[7]_net_1\); - - \shift_reg_3[14]\ : DFN1E1C0 - port map(D => \shift_reg_3[13]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_2[0]_net_1\, Q - => \shift_reg_3[14]_net_1\); - - \shift_reg_1[13]\ : DFN1E1C0 - port map(D => \shift_reg_1[12]_net_1\, CLK => HCLK_c, CLR - => HRESETn_c, E => \sample_bit_counter_1[0]_net_1\, Q - => \shift_reg_1[13]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_lfr_wf_picker_ip is - - port( nb_snapshot_param : in std_logic_vector(10 downto 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - hwdata_c : out std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - haddr_c : out std_logic_vector(31 downto 0); - AHB_Master_In_c_3 : in std_logic; - AHB_Master_In_c_0 : in std_logic; - AHB_Master_In_c_4 : in std_logic; - AHB_Master_In_c_5 : in std_logic; - hsize_c : out std_logic_vector(1 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0); - sdo_c : in std_logic_vector(7 downto 0); - coarse_time_0_c : in std_logic; - enable_f0 : in std_logic; - data_shaping_R0 : in std_logic; - data_shaping_R0_0 : in std_logic; - burst_f0 : in std_logic; - data_shaping_R1 : in std_logic; - data_shaping_R1_0 : in std_logic; - enable_f1 : in std_logic; - burst_f1 : in std_logic; - enable_f2 : in std_logic; - burst_f2 : in std_logic; - enable_f3 : in std_logic; - N_43 : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - hwrite_c : out std_logic; - lpp_top_lfr_wf_picker_ip_GND : in std_logic; - lpp_top_lfr_wf_picker_ip_VCC : in std_logic; - cnv_run_c : in std_logic; - sck_c : out std_logic; - cnv_c : out std_logic; - cnv_clk_c : in std_logic; - cnv_rstn_c : in std_logic; - data_shaping_SP0 : in std_logic; - data_shaping_SP1 : in std_logic; - HRESETn_c : in std_logic; - HCLK_c : in std_logic - ); - -end lpp_top_lfr_wf_picker_ip; - -architecture DEF_ARCH of lpp_top_lfr_wf_picker_ip is - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2 - port( sample_filter_v2_out_0 : out std_logic; - sample_filter_v2_out_1 : out std_logic; - sample_filter_v2_out_2 : out std_logic; - sample_filter_v2_out_3 : out std_logic; - sample_filter_v2_out_4 : out std_logic; - sample_filter_v2_out_5 : out std_logic; - sample_filter_v2_out_6 : out std_logic; - sample_filter_v2_out_7 : out std_logic; - sample_filter_v2_out_8 : out std_logic; - sample_filter_v2_out_9 : out std_logic; - sample_filter_v2_out_10 : out std_logic; - sample_filter_v2_out_11 : out std_logic; - sample_filter_v2_out_12 : out std_logic; - sample_filter_v2_out_13 : out std_logic; - sample_filter_v2_out_14 : out std_logic; - sample_filter_v2_out_15 : out std_logic; - sample_filter_v2_out_18 : out std_logic; - sample_filter_v2_out_19 : out std_logic; - sample_filter_v2_out_20 : out std_logic; - sample_filter_v2_out_21 : out std_logic; - sample_filter_v2_out_22 : out std_logic; - sample_filter_v2_out_23 : out std_logic; - sample_filter_v2_out_24 : out std_logic; - sample_filter_v2_out_25 : out std_logic; - sample_filter_v2_out_26 : out std_logic; - sample_filter_v2_out_27 : out std_logic; - sample_filter_v2_out_28 : out std_logic; - sample_filter_v2_out_29 : out std_logic; - sample_filter_v2_out_30 : out std_logic; - sample_filter_v2_out_31 : out std_logic; - sample_filter_v2_out_32 : out std_logic; - sample_filter_v2_out_33 : out std_logic; - sample_filter_v2_out_36 : out std_logic; - sample_filter_v2_out_37 : out std_logic; - sample_filter_v2_out_38 : out std_logic; - sample_filter_v2_out_39 : out std_logic; - sample_filter_v2_out_40 : out std_logic; - sample_filter_v2_out_41 : out std_logic; - sample_filter_v2_out_42 : out std_logic; - sample_filter_v2_out_43 : out std_logic; - sample_filter_v2_out_44 : out std_logic; - sample_filter_v2_out_45 : out std_logic; - sample_filter_v2_out_46 : out std_logic; - sample_filter_v2_out_47 : out std_logic; - sample_filter_v2_out_48 : out std_logic; - sample_filter_v2_out_49 : out std_logic; - sample_filter_v2_out_50 : out std_logic; - sample_filter_v2_out_51 : out std_logic; - sample_filter_v2_out_54 : out std_logic; - sample_filter_v2_out_55 : out std_logic; - sample_filter_v2_out_56 : out std_logic; - sample_filter_v2_out_57 : out std_logic; - sample_filter_v2_out_58 : out std_logic; - sample_filter_v2_out_59 : out std_logic; - sample_filter_v2_out_60 : out std_logic; - sample_filter_v2_out_61 : out std_logic; - sample_filter_v2_out_62 : out std_logic; - sample_filter_v2_out_63 : out std_logic; - sample_filter_v2_out_64 : out std_logic; - sample_filter_v2_out_65 : out std_logic; - sample_filter_v2_out_66 : out std_logic; - sample_filter_v2_out_67 : out std_logic; - sample_filter_v2_out_68 : out std_logic; - sample_filter_v2_out_69 : out std_logic; - sample_filter_v2_out_90 : out std_logic; - sample_filter_v2_out_91 : out std_logic; - sample_filter_v2_out_92 : out std_logic; - sample_filter_v2_out_93 : out std_logic; - sample_filter_v2_out_94 : out std_logic; - sample_filter_v2_out_95 : out std_logic; - sample_filter_v2_out_96 : out std_logic; - sample_filter_v2_out_97 : out std_logic; - sample_filter_v2_out_98 : out std_logic; - sample_filter_v2_out_99 : out std_logic; - sample_filter_v2_out_100 : out std_logic; - sample_filter_v2_out_101 : out std_logic; - sample_filter_v2_out_102 : out std_logic; - sample_filter_v2_out_103 : out std_logic; - sample_filter_v2_out_104 : out std_logic; - sample_filter_v2_out_105 : out std_logic; - sample_filter_v2_out_108 : out std_logic; - sample_filter_v2_out_126 : out std_logic; - sample_filter_v2_out_109 : out std_logic; - sample_filter_v2_out_127 : out std_logic; - sample_filter_v2_out_110 : out std_logic; - sample_filter_v2_out_128 : out std_logic; - sample_filter_v2_out_111 : out std_logic; - sample_filter_v2_out_129 : out std_logic; - sample_filter_v2_out_112 : out std_logic; - sample_filter_v2_out_130 : out std_logic; - sample_filter_v2_out_113 : out std_logic; - sample_filter_v2_out_131 : out std_logic; - sample_filter_v2_out_114 : out std_logic; - sample_filter_v2_out_132 : out std_logic; - sample_filter_v2_out_115 : out std_logic; - sample_filter_v2_out_133 : out std_logic; - sample_filter_v2_out_116 : out std_logic; - sample_filter_v2_out_134 : out std_logic; - sample_filter_v2_out_117 : out std_logic; - sample_filter_v2_out_135 : out std_logic; - sample_filter_v2_out_118 : out std_logic; - sample_filter_v2_out_136 : out std_logic; - sample_filter_v2_out_119 : out std_logic; - sample_filter_v2_out_137 : out std_logic; - sample_filter_v2_out_120 : out std_logic; - sample_filter_v2_out_138 : out std_logic; - sample_filter_v2_out_121 : out std_logic; - sample_filter_v2_out_139 : out std_logic; - sample_filter_v2_out_122 : out std_logic; - sample_filter_v2_out_140 : out std_logic; - sample_filter_v2_out_123 : out std_logic; - sample_filter_v2_out_141 : out std_logic; - sample_6 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_5 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_2 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_1 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_3 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_4 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_7 : in std_logic_vector(15 downto 0) := (others => 'U'); - IIR_CEL_CTRLR_v2_VCC : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_GND : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_filter_v2_out_val : out std_logic; - sample_val_delay : in std_logic := 'U' - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component Downsampling_6_16_256 - port( sample_f1 : in std_logic_vector(111 downto 80) := (others => 'U'); - sample_f1_wdata_95 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - sample_f3_wdata : out std_logic_vector(95 downto 0); - sample_f1_val : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f3_val : out std_logic; - HRESETn_c : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component Downsampling_6_16_96 - port( sample_f0 : in std_logic_vector(111 downto 80) := (others => 'U'); - sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f2_wdata : out std_logic_vector(95 downto 0); - sample_f0_val : in std_logic := 'U'; - sample_f0_val_1 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f2_val : out std_logic; - sample_f0_val_0 : in std_logic := 'U'; - sample_out_0_sqmuxa_1 : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform - port( status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - hburst_c : out std_logic_vector(2 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hsize_c : out std_logic_vector(1 downto 0); - AHB_Master_In_c_5 : in std_logic := 'U'; - AHB_Master_In_c_4 : in std_logic := 'U'; - AHB_Master_In_c_0 : in std_logic := 'U'; - AHB_Master_In_c_3 : in std_logic := 'U'; - haddr_c : out std_logic_vector(31 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(3 downto 0); - status_full : out std_logic_vector(3 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata_c : out std_logic_vector(31 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - sample_f3_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - sample_f2_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - sample_f1_15 : in std_logic := 'U'; - sample_f1_47 : in std_logic := 'U'; - sample_f1_14 : in std_logic := 'U'; - sample_f1_46 : in std_logic := 'U'; - sample_f1_13 : in std_logic := 'U'; - sample_f1_45 : in std_logic := 'U'; - sample_f1_12 : in std_logic := 'U'; - sample_f1_44 : in std_logic := 'U'; - sample_f1_60 : in std_logic := 'U'; - sample_f1_59 : in std_logic := 'U'; - sample_f1_58 : in std_logic := 'U'; - sample_f1_57 : in std_logic := 'U'; - sample_f1_56 : in std_logic := 'U'; - sample_f1_55 : in std_logic := 'U'; - sample_f1_54 : in std_logic := 'U'; - sample_f1_53 : in std_logic := 'U'; - sample_f1_52 : in std_logic := 'U'; - sample_f1_51 : in std_logic := 'U'; - sample_f1_50 : in std_logic := 'U'; - sample_f1_49 : in std_logic := 'U'; - sample_f1_48 : in std_logic := 'U'; - sample_f1_4 : in std_logic := 'U'; - sample_f1_36 : in std_logic := 'U'; - sample_f1_3 : in std_logic := 'U'; - sample_f1_35 : in std_logic := 'U'; - sample_f1_2 : in std_logic := 'U'; - sample_f1_34 : in std_logic := 'U'; - sample_f1_1 : in std_logic := 'U'; - sample_f1_33 : in std_logic := 'U'; - sample_f1_0 : in std_logic := 'U'; - sample_f1_32 : in std_logic := 'U'; - sample_f1_63 : in std_logic := 'U'; - sample_f1_62 : in std_logic := 'U'; - sample_f1_61 : in std_logic := 'U'; - sample_f1_11 : in std_logic := 'U'; - sample_f1_43 : in std_logic := 'U'; - sample_f1_10 : in std_logic := 'U'; - sample_f1_42 : in std_logic := 'U'; - sample_f1_9 : in std_logic := 'U'; - sample_f1_41 : in std_logic := 'U'; - sample_f1_8 : in std_logic := 'U'; - sample_f1_40 : in std_logic := 'U'; - sample_f1_7 : in std_logic := 'U'; - sample_f1_39 : in std_logic := 'U'; - sample_f1_6 : in std_logic := 'U'; - sample_f1_38 : in std_logic := 'U'; - sample_f1_5 : in std_logic := 'U'; - sample_f1_37 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_95 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_0 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_37 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_95 : in std_logic := 'U'; - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - hwrite_c : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - N_43 : out std_logic; - lpp_waveform_GND : in std_logic := 'U'; - lpp_waveform_VCC : in std_logic := 'U'; - sample_f3_val : in std_logic := 'U'; - enable_f3 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - data_shaping_R0 : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - coarse_time_0_c : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U' - ); - end component; - - component Downsampling_8_16_4 - port( sample_f0_0 : out std_logic; - sample_f0_1 : out std_logic; - sample_f0_2 : out std_logic; - sample_f0_3 : out std_logic; - sample_f0_4 : out std_logic; - sample_f0_5 : out std_logic; - sample_f0_6 : out std_logic; - sample_f0_7 : out std_logic; - sample_f0_8 : out std_logic; - sample_f0_9 : out std_logic; - sample_f0_10 : out std_logic; - sample_f0_11 : out std_logic; - sample_f0_12 : out std_logic; - sample_f0_13 : out std_logic; - sample_f0_14 : out std_logic; - sample_f0_15 : out std_logic; - sample_f0_32 : out std_logic; - sample_f0_33 : out std_logic; - sample_f0_34 : out std_logic; - sample_f0_35 : out std_logic; - sample_f0_36 : out std_logic; - sample_f0_37 : out std_logic; - sample_f0_38 : out std_logic; - sample_f0_39 : out std_logic; - sample_f0_40 : out std_logic; - sample_f0_41 : out std_logic; - sample_f0_42 : out std_logic; - sample_f0_43 : out std_logic; - sample_f0_44 : out std_logic; - sample_f0_45 : out std_logic; - sample_f0_46 : out std_logic; - sample_f0_47 : out std_logic; - sample_f0_48 : out std_logic; - sample_f0_49 : out std_logic; - sample_f0_50 : out std_logic; - sample_f0_51 : out std_logic; - sample_f0_52 : out std_logic; - sample_f0_53 : out std_logic; - sample_f0_54 : out std_logic; - sample_f0_55 : out std_logic; - sample_f0_56 : out std_logic; - sample_f0_57 : out std_logic; - sample_f0_58 : out std_logic; - sample_f0_59 : out std_logic; - sample_f0_60 : out std_logic; - sample_f0_61 : out std_logic; - sample_f0_62 : out std_logic; - sample_f0_63 : out std_logic; - sample_data_shaping_out_0 : in std_logic := 'U'; - sample_data_shaping_out_1 : in std_logic := 'U'; - sample_data_shaping_out_2 : in std_logic := 'U'; - sample_data_shaping_out_3 : in std_logic := 'U'; - sample_data_shaping_out_4 : in std_logic := 'U'; - sample_data_shaping_out_5 : in std_logic := 'U'; - sample_data_shaping_out_6 : in std_logic := 'U'; - sample_data_shaping_out_7 : in std_logic := 'U'; - sample_data_shaping_out_8 : in std_logic := 'U'; - sample_data_shaping_out_9 : in std_logic := 'U'; - sample_data_shaping_out_10 : in std_logic := 'U'; - sample_data_shaping_out_11 : in std_logic := 'U'; - sample_data_shaping_out_12 : in std_logic := 'U'; - sample_data_shaping_out_13 : in std_logic := 'U'; - sample_data_shaping_out_14 : in std_logic := 'U'; - sample_data_shaping_out_15 : in std_logic := 'U'; - sample_data_shaping_out_18 : in std_logic := 'U'; - sample_data_shaping_out_19 : in std_logic := 'U'; - sample_data_shaping_out_20 : in std_logic := 'U'; - sample_data_shaping_out_21 : in std_logic := 'U'; - sample_data_shaping_out_22 : in std_logic := 'U'; - sample_data_shaping_out_23 : in std_logic := 'U'; - sample_data_shaping_out_24 : in std_logic := 'U'; - sample_data_shaping_out_25 : in std_logic := 'U'; - sample_data_shaping_out_26 : in std_logic := 'U'; - sample_data_shaping_out_27 : in std_logic := 'U'; - sample_data_shaping_out_28 : in std_logic := 'U'; - sample_data_shaping_out_29 : in std_logic := 'U'; - sample_data_shaping_out_30 : in std_logic := 'U'; - sample_data_shaping_out_31 : in std_logic := 'U'; - sample_data_shaping_out_32 : in std_logic := 'U'; - sample_data_shaping_out_33 : in std_logic := 'U'; - sample_data_shaping_out_36 : in std_logic := 'U'; - sample_data_shaping_out_37 : in std_logic := 'U'; - sample_data_shaping_out_38 : in std_logic := 'U'; - sample_data_shaping_out_39 : in std_logic := 'U'; - sample_data_shaping_out_40 : in std_logic := 'U'; - sample_data_shaping_out_41 : in std_logic := 'U'; - sample_data_shaping_out_42 : in std_logic := 'U'; - sample_data_shaping_out_43 : in std_logic := 'U'; - sample_data_shaping_out_44 : in std_logic := 'U'; - sample_data_shaping_out_45 : in std_logic := 'U'; - sample_data_shaping_out_46 : in std_logic := 'U'; - sample_data_shaping_out_47 : in std_logic := 'U'; - sample_data_shaping_out_48 : in std_logic := 'U'; - sample_data_shaping_out_49 : in std_logic := 'U'; - sample_data_shaping_out_50 : in std_logic := 'U'; - sample_data_shaping_out_51 : in std_logic := 'U'; - sample_data_shaping_out_54 : in std_logic := 'U'; - sample_data_shaping_out_55 : in std_logic := 'U'; - sample_data_shaping_out_56 : in std_logic := 'U'; - sample_data_shaping_out_57 : in std_logic := 'U'; - sample_data_shaping_out_58 : in std_logic := 'U'; - sample_data_shaping_out_59 : in std_logic := 'U'; - sample_data_shaping_out_60 : in std_logic := 'U'; - sample_data_shaping_out_61 : in std_logic := 'U'; - sample_data_shaping_out_62 : in std_logic := 'U'; - sample_data_shaping_out_63 : in std_logic := 'U'; - sample_data_shaping_out_64 : in std_logic := 'U'; - sample_data_shaping_out_65 : in std_logic := 'U'; - sample_data_shaping_out_66 : in std_logic := 'U'; - sample_data_shaping_out_67 : in std_logic := 'U'; - sample_data_shaping_out_68 : in std_logic := 'U'; - sample_data_shaping_out_69 : in std_logic := 'U'; - sample_data_shaping_out_90 : in std_logic := 'U'; - sample_data_shaping_out_91 : in std_logic := 'U'; - sample_data_shaping_out_92 : in std_logic := 'U'; - sample_data_shaping_out_93 : in std_logic := 'U'; - sample_data_shaping_out_94 : in std_logic := 'U'; - sample_data_shaping_out_95 : in std_logic := 'U'; - sample_data_shaping_out_96 : in std_logic := 'U'; - sample_data_shaping_out_97 : in std_logic := 'U'; - sample_data_shaping_out_98 : in std_logic := 'U'; - sample_data_shaping_out_99 : in std_logic := 'U'; - sample_data_shaping_out_100 : in std_logic := 'U'; - sample_data_shaping_out_101 : in std_logic := 'U'; - sample_data_shaping_out_102 : in std_logic := 'U'; - sample_data_shaping_out_103 : in std_logic := 'U'; - sample_data_shaping_out_104 : in std_logic := 'U'; - sample_data_shaping_out_105 : in std_logic := 'U'; - sample_data_shaping_out_108 : in std_logic := 'U'; - sample_data_shaping_out_109 : in std_logic := 'U'; - sample_data_shaping_out_110 : in std_logic := 'U'; - sample_data_shaping_out_111 : in std_logic := 'U'; - sample_data_shaping_out_112 : in std_logic := 'U'; - sample_data_shaping_out_113 : in std_logic := 'U'; - sample_data_shaping_out_114 : in std_logic := 'U'; - sample_data_shaping_out_115 : in std_logic := 'U'; - sample_data_shaping_out_116 : in std_logic := 'U'; - sample_data_shaping_out_117 : in std_logic := 'U'; - sample_data_shaping_out_118 : in std_logic := 'U'; - sample_data_shaping_out_119 : in std_logic := 'U'; - sample_data_shaping_out_120 : in std_logic := 'U'; - sample_data_shaping_out_121 : in std_logic := 'U'; - sample_data_shaping_out_122 : in std_logic := 'U'; - sample_data_shaping_out_123 : in std_logic := 'U'; - sample_data_shaping_out_126 : in std_logic := 'U'; - sample_data_shaping_out_127 : in std_logic := 'U'; - sample_data_shaping_out_128 : in std_logic := 'U'; - sample_data_shaping_out_129 : in std_logic := 'U'; - sample_data_shaping_out_130 : in std_logic := 'U'; - sample_data_shaping_out_131 : in std_logic := 'U'; - sample_data_shaping_out_132 : in std_logic := 'U'; - sample_data_shaping_out_133 : in std_logic := 'U'; - sample_data_shaping_out_134 : in std_logic := 'U'; - sample_data_shaping_out_135 : in std_logic := 'U'; - sample_data_shaping_out_136 : in std_logic := 'U'; - sample_data_shaping_out_137 : in std_logic := 'U'; - sample_data_shaping_out_138 : in std_logic := 'U'; - sample_data_shaping_out_139 : in std_logic := 'U'; - sample_data_shaping_out_140 : in std_logic := 'U'; - sample_data_shaping_out_141 : in std_logic := 'U'; - sample_f0_wdata_95 : out std_logic; - sample_f0_wdata_94 : out std_logic; - sample_f0_wdata_93 : out std_logic; - sample_f0_wdata_92 : out std_logic; - sample_f0_wdata_91 : out std_logic; - sample_f0_wdata_90 : out std_logic; - sample_f0_wdata_89 : out std_logic; - sample_f0_wdata_88 : out std_logic; - sample_f0_wdata_87 : out std_logic; - sample_f0_wdata_86 : out std_logic; - sample_f0_wdata_85 : out std_logic; - sample_f0_wdata_84 : out std_logic; - sample_f0_wdata_83 : out std_logic; - sample_f0_wdata_82 : out std_logic; - sample_f0_wdata_81 : out std_logic; - sample_f0_wdata_80 : out std_logic; - sample_f0_wdata_79 : out std_logic; - sample_f0_wdata_78 : out std_logic; - sample_f0_wdata_77 : out std_logic; - sample_f0_wdata_76 : out std_logic; - sample_f0_wdata_75 : out std_logic; - sample_f0_wdata_74 : out std_logic; - sample_f0_wdata_73 : out std_logic; - sample_f0_wdata_72 : out std_logic; - sample_f0_wdata_71 : out std_logic; - sample_f0_wdata_70 : out std_logic; - sample_f0_wdata_69 : out std_logic; - sample_f0_wdata_68 : out std_logic; - sample_f0_wdata_67 : out std_logic; - sample_f0_wdata_66 : out std_logic; - sample_f0_wdata_65 : out std_logic; - sample_f0_wdata_64 : out std_logic; - sample_f0_wdata_63 : out std_logic; - sample_f0_wdata_62 : out std_logic; - sample_f0_wdata_61 : out std_logic; - sample_f0_wdata_60 : out std_logic; - sample_f0_wdata_59 : out std_logic; - sample_f0_wdata_58 : out std_logic; - sample_f0_wdata_57 : out std_logic; - sample_f0_wdata_56 : out std_logic; - sample_f0_wdata_55 : out std_logic; - sample_f0_wdata_54 : out std_logic; - sample_f0_wdata_53 : out std_logic; - sample_f0_wdata_52 : out std_logic; - sample_f0_wdata_51 : out std_logic; - sample_f0_wdata_50 : out std_logic; - sample_f0_wdata_49 : out std_logic; - sample_f0_wdata_48 : out std_logic; - sample_f0_wdata_15 : out std_logic; - sample_f0_wdata_14 : out std_logic; - sample_f0_wdata_13 : out std_logic; - sample_f0_wdata_12 : out std_logic; - sample_f0_wdata_11 : out std_logic; - sample_f0_wdata_10 : out std_logic; - sample_f0_wdata_9 : out std_logic; - sample_f0_wdata_8 : out std_logic; - sample_f0_wdata_7 : out std_logic; - sample_f0_wdata_6 : out std_logic; - sample_f0_wdata_5 : out std_logic; - sample_f0_wdata_4 : out std_logic; - sample_f0_wdata_3 : out std_logic; - sample_f0_wdata_2 : out std_logic; - sample_f0_wdata_1 : out std_logic; - sample_f0_wdata_0 : out std_logic; - sample_data_shaping_out_val : in std_logic := 'U'; - sample_f0_val : out std_logic; - sample_data_shaping_out_val_0 : in std_logic := 'U'; - sample_f0_val_0 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f0_val_1 : out std_logic - ); - end component; - - component Downsampling_8_16_6 - port( sample_f0_0 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_37 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f1_0 : out std_logic; - sample_f1_1 : out std_logic; - sample_f1_2 : out std_logic; - sample_f1_3 : out std_logic; - sample_f1_4 : out std_logic; - sample_f1_5 : out std_logic; - sample_f1_6 : out std_logic; - sample_f1_7 : out std_logic; - sample_f1_8 : out std_logic; - sample_f1_9 : out std_logic; - sample_f1_10 : out std_logic; - sample_f1_11 : out std_logic; - sample_f1_12 : out std_logic; - sample_f1_13 : out std_logic; - sample_f1_14 : out std_logic; - sample_f1_15 : out std_logic; - sample_f1_32 : out std_logic; - sample_f1_33 : out std_logic; - sample_f1_34 : out std_logic; - sample_f1_35 : out std_logic; - sample_f1_36 : out std_logic; - sample_f1_37 : out std_logic; - sample_f1_38 : out std_logic; - sample_f1_39 : out std_logic; - sample_f1_40 : out std_logic; - sample_f1_41 : out std_logic; - sample_f1_42 : out std_logic; - sample_f1_43 : out std_logic; - sample_f1_44 : out std_logic; - sample_f1_45 : out std_logic; - sample_f1_46 : out std_logic; - sample_f1_47 : out std_logic; - sample_f1_48 : out std_logic; - sample_f1_49 : out std_logic; - sample_f1_50 : out std_logic; - sample_f1_51 : out std_logic; - sample_f1_52 : out std_logic; - sample_f1_53 : out std_logic; - sample_f1_54 : out std_logic; - sample_f1_55 : out std_logic; - sample_f1_56 : out std_logic; - sample_f1_57 : out std_logic; - sample_f1_58 : out std_logic; - sample_f1_59 : out std_logic; - sample_f1_60 : out std_logic; - sample_f1_61 : out std_logic; - sample_f1_62 : out std_logic; - sample_f1_63 : out std_logic; - sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f1_wdata_95 : out std_logic; - sample_f1_wdata_94 : out std_logic; - sample_f1_wdata_93 : out std_logic; - sample_f1_wdata_92 : out std_logic; - sample_f1_wdata_91 : out std_logic; - sample_f1_wdata_90 : out std_logic; - sample_f1_wdata_89 : out std_logic; - sample_f1_wdata_88 : out std_logic; - sample_f1_wdata_87 : out std_logic; - sample_f1_wdata_86 : out std_logic; - sample_f1_wdata_85 : out std_logic; - sample_f1_wdata_84 : out std_logic; - sample_f1_wdata_83 : out std_logic; - sample_f1_wdata_82 : out std_logic; - sample_f1_wdata_81 : out std_logic; - sample_f1_wdata_80 : out std_logic; - sample_f1_wdata_79 : out std_logic; - sample_f1_wdata_78 : out std_logic; - sample_f1_wdata_77 : out std_logic; - sample_f1_wdata_76 : out std_logic; - sample_f1_wdata_75 : out std_logic; - sample_f1_wdata_74 : out std_logic; - sample_f1_wdata_73 : out std_logic; - sample_f1_wdata_72 : out std_logic; - sample_f1_wdata_71 : out std_logic; - sample_f1_wdata_70 : out std_logic; - sample_f1_wdata_69 : out std_logic; - sample_f1_wdata_68 : out std_logic; - sample_f1_wdata_67 : out std_logic; - sample_f1_wdata_66 : out std_logic; - sample_f1_wdata_65 : out std_logic; - sample_f1_wdata_64 : out std_logic; - sample_f1_wdata_63 : out std_logic; - sample_f1_wdata_62 : out std_logic; - sample_f1_wdata_61 : out std_logic; - sample_f1_wdata_60 : out std_logic; - sample_f1_wdata_59 : out std_logic; - sample_f1_wdata_58 : out std_logic; - sample_f1_wdata_57 : out std_logic; - sample_f1_wdata_56 : out std_logic; - sample_f1_wdata_55 : out std_logic; - sample_f1_wdata_54 : out std_logic; - sample_f1_wdata_53 : out std_logic; - sample_f1_wdata_52 : out std_logic; - sample_f1_wdata_51 : out std_logic; - sample_f1_wdata_50 : out std_logic; - sample_f1_wdata_49 : out std_logic; - sample_f1_wdata_48 : out std_logic; - sample_f1_wdata_15 : out std_logic; - sample_f1_wdata_14 : out std_logic; - sample_f1_wdata_13 : out std_logic; - sample_f1_wdata_12 : out std_logic; - sample_f1_wdata_11 : out std_logic; - sample_f1_wdata_10 : out std_logic; - sample_f1_wdata_9 : out std_logic; - sample_f1_wdata_8 : out std_logic; - sample_f1_wdata_7 : out std_logic; - sample_f1_wdata_6 : out std_logic; - sample_f1_wdata_5 : out std_logic; - sample_f1_wdata_4 : out std_logic; - sample_f1_wdata_3 : out std_logic; - sample_f1_wdata_2 : out std_logic; - sample_f1_wdata_1 : out std_logic; - sample_f1_wdata_0 : out std_logic; - sample_f0_val_1 : in std_logic := 'U'; - sample_f1_val : out std_logic; - sample_f0_val_0 : in std_logic := 'U'; - sample_out_0_sqmuxa_1 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - sample_f1_val_0 : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AD7688_drvr - port( sample_7 : out std_logic_vector(15 downto 0); - sample_0 : out std_logic_vector(15 downto 0); - sample_1 : out std_logic_vector(15 downto 0); - sample_2 : out std_logic_vector(15 downto 0); - sample_3 : out std_logic_vector(15 downto 0); - sample_4 : out std_logic_vector(15 downto 0); - sample_5 : out std_logic_vector(15 downto 0); - sdo_c : in std_logic_vector(7 downto 0) := (others => 'U'); - sample_6 : out std_logic_vector(15 downto 0); - cnv_rstn_c : in std_logic := 'U'; - cnv_clk_c : in std_logic := 'U'; - cnv_c : out std_logic; - sample_val : out std_logic; - sck_c : out std_logic; - cnv_run_c : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \sample_data_shaping_out_val_0\, - sample_filter_v2_out_val, \sample_val_delay\, - sample_val_delay_0, SUB_16x16_medium_area_I57_Y_2, N244, - N229, SUB_16x16_medium_area_I57_Y_1, N254, N212, - SUB_16x16_medium_area_I57_Y_0, N206, - \sample_filter_v2_out[111]\, \sample_filter_v2_out[93]\, - SUB_16x16_medium_area_I57_Y_2_0, N244_0, N229_0, - SUB_16x16_medium_area_I57_Y_1_0, N212_0, N254_0, - SUB_16x16_medium_area_I57_Y_0_0, N206_0, - \sample_filter_v2_out[129]\, - SUB_16x16_medium_area_I57_un1_Y_0, N245, - SUB_16x16_medium_area_I57_un1_Y_0_0, N245_0, - SUB_16x16_medium_area_I56_Y_1, N274, N220, - SUB_16x16_medium_area_I56_Y_0, N190, - \sample_filter_v2_out[119]\, \sample_filter_v2_out[101]\, - SUB_16x16_medium_area_I56_Y_1_0, N274_0, N220_0, - SUB_16x16_medium_area_I56_Y_0_0, N190_0, - \sample_filter_v2_out[137]\, - SUB_16x16_medium_area_I56_un1_Y_0, N275, - SUB_16x16_medium_area_I49_Y_0, N198, - \sample_filter_v2_out[115]\, \sample_filter_v2_out[97]\, - SUB_16x16_medium_area_I49_Y_0_0, N198_0, - \sample_filter_v2_out[133]\, - SUB_16x16_medium_area_I53_Y_0, N182, - \sample_filter_v2_out[123]\, \sample_filter_v2_out[105]\, - SUB_16x16_medium_area_I53_Y_0_0, N182_0, - \sample_filter_v2_out[141]\, - SUB_16x16_medium_area_I53_un1_Y_0, N225, N264, N216, N240, - N268, I53_un1_Y, N225_0, N183, N181, N278, N264_0, N216_0, - N240_0, N268_0, I56_un1_Y, N275_0, N278_0, - \sample_data_shaping_f2_f1_s[15]\, - \sample_filter_v2_out[110]\, \sample_filter_v2_out[92]\, - \sample_data_shaping_f1_f0_s[15]\, - \sample_filter_v2_out[128]\, N181_0, N194, - \sample_filter_v2_out[118]\, \sample_filter_v2_out[136]\, - \sample_filter_v2_out[116]\, \sample_filter_v2_out[134]\, - N202, \sample_filter_v2_out[114]\, - \sample_filter_v2_out[132]\, \sample_filter_v2_out[112]\, - \sample_filter_v2_out[130]\, N205, - \sample_filter_v2_out[131]\, \sample_filter_v2_out[113]\, - N255, N201, N197, N265, N195, N258, N260, N270, N282_i, - N284_i, N286_i, \sample_data_shaping_f1_f0_s[7]\, - \sample_data_shaping_f1_f0_s[9]\, - \sample_data_shaping_f1_f0_s[10]\, - \sample_data_shaping_f1_f0_s[11]\, - \sample_data_shaping_f1_f0_s[12]\, - \sample_data_shaping_f1_f0_s[13]\, - \sample_data_shaping_f1_f0_s_i[14]\, N186, - \sample_filter_v2_out[122]\, \sample_filter_v2_out[140]\, - \sample_filter_v2_out[120]\, \sample_filter_v2_out[138]\, - N191, N189, \sample_filter_v2_out[121]\, - \sample_filter_v2_out[139]\, N187, N185, I85_un1_Y, - I90_un1_Y, SUB_16x16_medium_area_I91_un1_Y, - \sample_data_shaping_f1_f0_s[3]\, - \sample_data_shaping_f1_f0_s[4]\, - \sample_data_shaping_f1_f0_s[5]\, - \sample_data_shaping_f1_f0_s[6]\, N194_0, - \sample_filter_v2_out[100]\, \sample_filter_v2_out[98]\, - N202_0, \sample_filter_v2_out[96]\, - \sample_filter_v2_out[94]\, N207, N205_0, - \sample_filter_v2_out[95]\, N255_0, N203, N201_0, N199, - N197_0, \sample_filter_v2_out[99]\, - \sample_filter_v2_out[117]\, N265_0, N195_0, N193, - I64_un1_Y, I71_un1_Y, I78_un1_Y, I86_un1_Y, - SUB_16x16_medium_area_I87_un1_Y, I88_un1_Y, - SUB_16x16_medium_area_I89_un1_Y, - \sample_data_shaping_f2_f1_s[7]\, - \sample_data_shaping_f2_f1_s[8]\, - \sample_data_shaping_f2_f1_s[9]\, - \sample_data_shaping_f2_f1_s[10]\, - \sample_data_shaping_f2_f1_s[11]\, - \sample_data_shaping_f2_f1_s[12]\, - \sample_data_shaping_f2_f1_s[13]\, - \sample_data_shaping_f2_f1_s[14]\, N186_0, - \sample_filter_v2_out[104]\, \sample_filter_v2_out[102]\, - N189_0, \sample_filter_v2_out[103]\, N187_0, N280, N290_i, - SUB_16x16_medium_area_I91_un1_Y_0, - \sample_data_shaping_f2_f1_s[3]\, - \sample_data_shaping_f2_f1_s[4]\, - \sample_data_shaping_f2_f1_s[5]\, - \sample_data_shaping_f2_f1_s[6]\, - \sample_data_shaping_out_377[92]\, - \sample_data_shaping_out_353[93]\, - \sample_data_shaping_out_329[94]\, - \sample_data_shaping_out_305[95]\, - \sample_data_shaping_out_281[96]\, - \sample_data_shaping_out_257[97]\, - \sample_data_shaping_out_233[98]\, - \sample_data_shaping_out_209[99]\, - \sample_data_shaping_out_185[100]\, - \sample_data_shaping_out_161[101]\, - \sample_data_shaping_out_137[102]\, - \sample_data_shaping_out_113[103]\, - \sample_data_shaping_out_89[104]\, - \sample_data_shaping_out_373[110]\, - \sample_data_shaping_out_349[111]\, - \sample_data_shaping_out_325[112]\, - \sample_data_shaping_out_301[113]\, - \sample_data_shaping_out_277[114]\, - \sample_data_shaping_out_253[115]\, - \sample_data_shaping_out_229[116]\, - \sample_data_shaping_out_181[118]\, - \sample_data_shaping_out_157[119]\, - \sample_data_shaping_out_133[120]\, - \sample_data_shaping_out_109[121]\, - \sample_data_shaping_out_85[122]\, - \sample_filter_v2_out[143]\, \sample_filter_v2_out[125]\, - \sample_filter_v2_out[107]\, - \sample_data_shaping_out_17[107]\, - \sample_data_shaping_out_13[125]\, - \sample_data_shaping_out_37[124]\, - \sample_filter_v2_out[124]\, - \sample_data_shaping_f1_f0_s[1]\, - \sample_data_shaping_out_61[123]\, - \sample_data_shaping_f1_f0_s[2]\, - \sample_data_shaping_out_205[117]\, - \sample_data_shaping_f1_f0_s[8]\, - \sample_data_shaping_out_41[106]\, - \sample_filter_v2_out[106]\, - \sample_data_shaping_f2_f1_s[1]\, - \sample_data_shaping_out_65[105]\, - \sample_data_shaping_f2_f1_s[2]\, N294_i, I92_un1_Y, - \sample_filter_v2_out[142]\, \sample_filter_v2_out[135]\, - N288_i, sample_val, \sample_data_shaping_out_val\, - \sample_data_shaping_out[20]\, \sample_filter_v2_out[20]\, - \sample_data_shaping_out[21]\, \sample_filter_v2_out[21]\, - \sample_data_shaping_out[22]\, \sample_filter_v2_out[22]\, - \sample_data_shaping_out[23]\, \sample_filter_v2_out[23]\, - \sample_data_shaping_out[24]\, \sample_filter_v2_out[24]\, - \sample_data_shaping_out[25]\, \sample_filter_v2_out[25]\, - \sample_data_shaping_out[26]\, \sample_filter_v2_out[26]\, - \sample_data_shaping_out[27]\, \sample_filter_v2_out[27]\, - \sample_data_shaping_out[28]\, \sample_filter_v2_out[28]\, - \sample_data_shaping_out[29]\, \sample_filter_v2_out[29]\, - \sample_data_shaping_out[30]\, \sample_filter_v2_out[30]\, - \sample_data_shaping_out[31]\, \sample_filter_v2_out[31]\, - \sample_data_shaping_out[32]\, \sample_filter_v2_out[32]\, - \sample_data_shaping_out[33]\, \sample_filter_v2_out[33]\, - \sample_data_shaping_out[34]\, \sample_filter_v2_out[34]\, - \sample_data_shaping_out[35]\, \sample_filter_v2_out[35]\, - \sample_data_shaping_out[38]\, \sample_filter_v2_out[38]\, - \sample_data_shaping_out[39]\, \sample_filter_v2_out[39]\, - \sample_data_shaping_out[40]\, \sample_filter_v2_out[40]\, - \sample_data_shaping_out[41]\, \sample_filter_v2_out[41]\, - \sample_data_shaping_out[42]\, \sample_filter_v2_out[42]\, - \sample_data_shaping_out[43]\, \sample_filter_v2_out[43]\, - \sample_data_shaping_out[44]\, \sample_filter_v2_out[44]\, - \sample_data_shaping_out[45]\, \sample_filter_v2_out[45]\, - \sample_data_shaping_out[46]\, \sample_filter_v2_out[46]\, - \sample_data_shaping_out[47]\, \sample_filter_v2_out[47]\, - \sample_data_shaping_out[48]\, \sample_filter_v2_out[48]\, - \sample_data_shaping_out[49]\, \sample_filter_v2_out[49]\, - \sample_data_shaping_out[50]\, \sample_filter_v2_out[50]\, - \sample_data_shaping_out[51]\, \sample_filter_v2_out[51]\, - \sample_data_shaping_out[52]\, \sample_filter_v2_out[52]\, - \sample_data_shaping_out[53]\, \sample_filter_v2_out[53]\, - \sample_data_shaping_out[56]\, \sample_filter_v2_out[56]\, - \sample_data_shaping_out[57]\, \sample_filter_v2_out[57]\, - \sample_data_shaping_out[58]\, \sample_filter_v2_out[58]\, - \sample_data_shaping_out[59]\, \sample_filter_v2_out[59]\, - \sample_data_shaping_out[60]\, \sample_filter_v2_out[60]\, - \sample_data_shaping_out[61]\, \sample_filter_v2_out[61]\, - \sample_data_shaping_out[62]\, \sample_filter_v2_out[62]\, - \sample_data_shaping_out[63]\, \sample_filter_v2_out[63]\, - \sample_data_shaping_out[64]\, \sample_filter_v2_out[64]\, - \sample_data_shaping_out[65]\, \sample_filter_v2_out[65]\, - \sample_data_shaping_out[66]\, \sample_filter_v2_out[66]\, - \sample_data_shaping_out[67]\, \sample_filter_v2_out[67]\, - \sample_data_shaping_out[68]\, \sample_filter_v2_out[68]\, - \sample_data_shaping_out[69]\, \sample_filter_v2_out[69]\, - \sample_data_shaping_out[70]\, \sample_filter_v2_out[70]\, - \sample_data_shaping_out[71]\, \sample_filter_v2_out[71]\, - \sample_data_shaping_out[128]\, - \sample_data_shaping_out[129]\, - \sample_data_shaping_out[130]\, - \sample_data_shaping_out[131]\, - \sample_data_shaping_out[132]\, - \sample_data_shaping_out[133]\, - \sample_data_shaping_out[134]\, - \sample_data_shaping_out[135]\, - \sample_data_shaping_out[136]\, - \sample_data_shaping_out[137]\, - \sample_data_shaping_out[138]\, - \sample_data_shaping_out[139]\, - \sample_data_shaping_out[140]\, - \sample_data_shaping_out[141]\, - \sample_data_shaping_out[142]\, - \sample_data_shaping_out[143]\, - \sample_data_shaping_out[2]\, \sample_filter_v2_out[2]\, - \sample_data_shaping_out[3]\, \sample_filter_v2_out[3]\, - \sample_data_shaping_out[4]\, \sample_filter_v2_out[4]\, - \sample_data_shaping_out[5]\, \sample_filter_v2_out[5]\, - \sample_data_shaping_out[6]\, \sample_filter_v2_out[6]\, - \sample_data_shaping_out[7]\, \sample_filter_v2_out[7]\, - \sample_data_shaping_out[8]\, \sample_filter_v2_out[8]\, - \sample_data_shaping_out[9]\, \sample_filter_v2_out[9]\, - \sample_data_shaping_out[10]\, \sample_filter_v2_out[10]\, - \sample_data_shaping_out[11]\, \sample_filter_v2_out[11]\, - \sample_data_shaping_out[12]\, \sample_filter_v2_out[12]\, - \sample_data_shaping_out[13]\, \sample_filter_v2_out[13]\, - \sample_data_shaping_out[14]\, \sample_filter_v2_out[14]\, - \sample_data_shaping_out[15]\, \sample_filter_v2_out[15]\, - \sample_data_shaping_out[16]\, \sample_filter_v2_out[16]\, - \sample_data_shaping_out[17]\, \sample_filter_v2_out[17]\, - \sample_data_shaping_out[92]\, - \sample_data_shaping_out[93]\, - \sample_data_shaping_out[94]\, - \sample_data_shaping_out[95]\, - \sample_data_shaping_out[96]\, - \sample_data_shaping_out[97]\, - \sample_data_shaping_out[98]\, - \sample_data_shaping_out[99]\, - \sample_data_shaping_out[100]\, - \sample_data_shaping_out[101]\, - \sample_data_shaping_out[102]\, - \sample_data_shaping_out[103]\, - \sample_data_shaping_out[104]\, - \sample_data_shaping_out[105]\, - \sample_data_shaping_out[106]\, - \sample_data_shaping_out[107]\, - \sample_data_shaping_out[110]\, - \sample_data_shaping_out[111]\, - \sample_data_shaping_out[112]\, - \sample_data_shaping_out[113]\, - \sample_data_shaping_out[114]\, - \sample_data_shaping_out[115]\, - \sample_data_shaping_out[116]\, - \sample_data_shaping_out[117]\, - \sample_data_shaping_out[118]\, - \sample_data_shaping_out[119]\, - \sample_data_shaping_out[120]\, - \sample_data_shaping_out[121]\, - \sample_data_shaping_out[122]\, - \sample_data_shaping_out[123]\, - \sample_data_shaping_out[124]\, - \sample_data_shaping_out[125]\, \sample_7[0]\, - \sample_7[1]\, \sample_7[2]\, \sample_7[3]\, - \sample_7[4]\, \sample_7[5]\, \sample_7[6]\, - \sample_7[7]\, \sample_7[8]\, \sample_7[9]\, - \sample_7[10]\, \sample_7[11]\, \sample_7[12]\, - \sample_7[13]\, \sample_7[14]\, \sample_7[15]\, - \sample_0[0]\, \sample_0[1]\, \sample_0[2]\, - \sample_0[3]\, \sample_0[4]\, \sample_0[5]\, - \sample_0[6]\, \sample_0[7]\, \sample_0[8]\, - \sample_0[9]\, \sample_0[10]\, \sample_0[11]\, - \sample_0[12]\, \sample_0[13]\, \sample_0[14]\, - \sample_0[15]\, \sample_1[0]\, \sample_1[1]\, - \sample_1[2]\, \sample_1[3]\, \sample_1[4]\, - \sample_1[5]\, \sample_1[6]\, \sample_1[7]\, - \sample_1[8]\, \sample_1[9]\, \sample_1[10]\, - \sample_1[11]\, \sample_1[12]\, \sample_1[13]\, - \sample_1[14]\, \sample_1[15]\, \sample_2[0]\, - \sample_2[1]\, \sample_2[2]\, \sample_2[3]\, - \sample_2[4]\, \sample_2[5]\, \sample_2[6]\, - \sample_2[7]\, \sample_2[8]\, \sample_2[9]\, - \sample_2[10]\, \sample_2[11]\, \sample_2[12]\, - \sample_2[13]\, \sample_2[14]\, \sample_2[15]\, - \sample_3[0]\, \sample_3[1]\, \sample_3[2]\, - \sample_3[3]\, \sample_3[4]\, \sample_3[5]\, - \sample_3[6]\, \sample_3[7]\, \sample_3[8]\, - \sample_3[9]\, \sample_3[10]\, \sample_3[11]\, - \sample_3[12]\, \sample_3[13]\, \sample_3[14]\, - \sample_3[15]\, \sample_4[0]\, \sample_4[1]\, - \sample_4[2]\, \sample_4[3]\, \sample_4[4]\, - \sample_4[5]\, \sample_4[6]\, \sample_4[7]\, - \sample_4[8]\, \sample_4[9]\, \sample_4[10]\, - \sample_4[11]\, \sample_4[12]\, \sample_4[13]\, - \sample_4[14]\, \sample_4[15]\, \sample_5[0]\, - \sample_5[1]\, \sample_5[2]\, \sample_5[3]\, - \sample_5[4]\, \sample_5[5]\, \sample_5[6]\, - \sample_5[7]\, \sample_5[8]\, \sample_5[9]\, - \sample_5[10]\, \sample_5[11]\, \sample_5[12]\, - \sample_5[13]\, \sample_5[14]\, \sample_5[15]\, - \sample_6[0]\, \sample_6[1]\, \sample_6[2]\, - \sample_6[3]\, \sample_6[4]\, \sample_6[5]\, - \sample_6[6]\, \sample_6[7]\, \sample_6[8]\, - \sample_6[9]\, \sample_6[10]\, \sample_6[11]\, - \sample_6[12]\, \sample_6[13]\, \sample_6[14]\, - \sample_6[15]\, \sample_f0[48]\, \sample_f0[49]\, - \sample_f0[50]\, \sample_f0[51]\, \sample_f0[52]\, - \sample_f0[53]\, \sample_f0[54]\, \sample_f0[55]\, - \sample_f0[56]\, \sample_f0[57]\, \sample_f0[58]\, - \sample_f0[59]\, \sample_f0[60]\, \sample_f0[61]\, - \sample_f0[62]\, \sample_f0[63]\, \sample_f0[80]\, - \sample_f0[81]\, \sample_f0[82]\, \sample_f0[83]\, - \sample_f0[84]\, \sample_f0[85]\, \sample_f0[86]\, - \sample_f0[87]\, \sample_f0[88]\, \sample_f0[89]\, - \sample_f0[90]\, \sample_f0[91]\, \sample_f0[92]\, - \sample_f0[93]\, \sample_f0[94]\, \sample_f0[95]\, - \sample_f0[96]\, \sample_f0[97]\, \sample_f0[98]\, - \sample_f0[99]\, \sample_f0[100]\, \sample_f0[101]\, - \sample_f0[102]\, \sample_f0[103]\, \sample_f0[104]\, - \sample_f0[105]\, \sample_f0[106]\, \sample_f0[107]\, - \sample_f0[108]\, \sample_f0[109]\, \sample_f0[110]\, - \sample_f0[111]\, \sample_f0_wdata[95]\, - \sample_f0_wdata[94]\, \sample_f0_wdata[93]\, - \sample_f0_wdata[92]\, \sample_f0_wdata[91]\, - \sample_f0_wdata[90]\, \sample_f0_wdata[89]\, - \sample_f0_wdata[88]\, \sample_f0_wdata[87]\, - \sample_f0_wdata[86]\, \sample_f0_wdata[85]\, - \sample_f0_wdata[84]\, \sample_f0_wdata[83]\, - \sample_f0_wdata[82]\, \sample_f0_wdata[81]\, - \sample_f0_wdata[80]\, \sample_f0_wdata[79]\, - \sample_f0_wdata[78]\, \sample_f0_wdata[77]\, - \sample_f0_wdata[76]\, \sample_f0_wdata[75]\, - \sample_f0_wdata[74]\, \sample_f0_wdata[73]\, - \sample_f0_wdata[72]\, \sample_f0_wdata[71]\, - \sample_f0_wdata[70]\, \sample_f0_wdata[69]\, - \sample_f0_wdata[68]\, \sample_f0_wdata[67]\, - \sample_f0_wdata[66]\, \sample_f0_wdata[65]\, - \sample_f0_wdata[64]\, \sample_f0_wdata[63]\, - \sample_f0_wdata[62]\, \sample_f0_wdata[61]\, - \sample_f0_wdata[60]\, \sample_f0_wdata[59]\, - \sample_f0_wdata[58]\, \sample_f0_wdata[57]\, - \sample_f0_wdata[56]\, \sample_f0_wdata[55]\, - \sample_f0_wdata[54]\, \sample_f0_wdata[53]\, - \sample_f0_wdata[52]\, \sample_f0_wdata[51]\, - \sample_f0_wdata[50]\, \sample_f0_wdata[49]\, - \sample_f0_wdata[48]\, \sample_f0_wdata[15]\, - \sample_f0_wdata[14]\, \sample_f0_wdata[13]\, - \sample_f0_wdata[12]\, \sample_f0_wdata[11]\, - \sample_f0_wdata[10]\, \sample_f0_wdata[9]\, - \sample_f0_wdata[8]\, \sample_f0_wdata[7]\, - \sample_f0_wdata[6]\, \sample_f0_wdata[5]\, - \sample_f0_wdata[4]\, \sample_f0_wdata[3]\, - \sample_f0_wdata[2]\, \sample_f0_wdata[1]\, - \sample_f0_wdata[0]\, sample_f0_val, sample_f0_val_0, - sample_f0_val_1, \sample_f1[48]\, \sample_f1[49]\, - \sample_f1[50]\, \sample_f1[51]\, \sample_f1[52]\, - \sample_f1[53]\, \sample_f1[54]\, \sample_f1[55]\, - \sample_f1[56]\, \sample_f1[57]\, \sample_f1[58]\, - \sample_f1[59]\, \sample_f1[60]\, \sample_f1[61]\, - \sample_f1[62]\, \sample_f1[63]\, \sample_f1[80]\, - \sample_f1[81]\, \sample_f1[82]\, \sample_f1[83]\, - \sample_f1[84]\, \sample_f1[85]\, \sample_f1[86]\, - \sample_f1[87]\, \sample_f1[88]\, \sample_f1[89]\, - \sample_f1[90]\, \sample_f1[91]\, \sample_f1[92]\, - \sample_f1[93]\, \sample_f1[94]\, \sample_f1[95]\, - \sample_f1[96]\, \sample_f1[97]\, \sample_f1[98]\, - \sample_f1[99]\, \sample_f1[100]\, \sample_f1[101]\, - \sample_f1[102]\, \sample_f1[103]\, \sample_f1[104]\, - \sample_f1[105]\, \sample_f1[106]\, \sample_f1[107]\, - \sample_f1[108]\, \sample_f1[109]\, \sample_f1[110]\, - \sample_f1[111]\, \sample_f1_wdata[95]\, - \sample_f1_wdata[94]\, \sample_f1_wdata[93]\, - \sample_f1_wdata[92]\, \sample_f1_wdata[91]\, - \sample_f1_wdata[90]\, \sample_f1_wdata[89]\, - \sample_f1_wdata[88]\, \sample_f1_wdata[87]\, - \sample_f1_wdata[86]\, \sample_f1_wdata[85]\, - \sample_f1_wdata[84]\, \sample_f1_wdata[83]\, - \sample_f1_wdata[82]\, \sample_f1_wdata[81]\, - \sample_f1_wdata[80]\, \sample_f1_wdata[79]\, - \sample_f1_wdata[78]\, \sample_f1_wdata[77]\, - \sample_f1_wdata[76]\, \sample_f1_wdata[75]\, - \sample_f1_wdata[74]\, \sample_f1_wdata[73]\, - \sample_f1_wdata[72]\, \sample_f1_wdata[71]\, - \sample_f1_wdata[70]\, \sample_f1_wdata[69]\, - \sample_f1_wdata[68]\, \sample_f1_wdata[67]\, - \sample_f1_wdata[66]\, \sample_f1_wdata[65]\, - \sample_f1_wdata[64]\, \sample_f1_wdata[63]\, - \sample_f1_wdata[62]\, \sample_f1_wdata[61]\, - \sample_f1_wdata[60]\, \sample_f1_wdata[59]\, - \sample_f1_wdata[58]\, \sample_f1_wdata[57]\, - \sample_f1_wdata[56]\, \sample_f1_wdata[55]\, - \sample_f1_wdata[54]\, \sample_f1_wdata[53]\, - \sample_f1_wdata[52]\, \sample_f1_wdata[51]\, - \sample_f1_wdata[50]\, \sample_f1_wdata[49]\, - \sample_f1_wdata[48]\, \sample_f1_wdata[15]\, - \sample_f1_wdata[14]\, \sample_f1_wdata[13]\, - \sample_f1_wdata[12]\, \sample_f1_wdata[11]\, - \sample_f1_wdata[10]\, \sample_f1_wdata[9]\, - \sample_f1_wdata[8]\, \sample_f1_wdata[7]\, - \sample_f1_wdata[6]\, \sample_f1_wdata[5]\, - \sample_f1_wdata[4]\, \sample_f1_wdata[3]\, - \sample_f1_wdata[2]\, \sample_f1_wdata[1]\, - \sample_f1_wdata[0]\, sample_f1_val, - sample_out_0_sqmuxa_1, sample_f1_val_0, - \sample_f2_wdata[0]\, \sample_f2_wdata[1]\, - \sample_f2_wdata[2]\, \sample_f2_wdata[3]\, - \sample_f2_wdata[4]\, \sample_f2_wdata[5]\, - \sample_f2_wdata[6]\, \sample_f2_wdata[7]\, - \sample_f2_wdata[8]\, \sample_f2_wdata[9]\, - \sample_f2_wdata[10]\, \sample_f2_wdata[11]\, - \sample_f2_wdata[12]\, \sample_f2_wdata[13]\, - \sample_f2_wdata[14]\, \sample_f2_wdata[15]\, - \sample_f2_wdata[16]\, \sample_f2_wdata[17]\, - \sample_f2_wdata[18]\, \sample_f2_wdata[19]\, - \sample_f2_wdata[20]\, \sample_f2_wdata[21]\, - \sample_f2_wdata[22]\, \sample_f2_wdata[23]\, - \sample_f2_wdata[24]\, \sample_f2_wdata[25]\, - \sample_f2_wdata[26]\, \sample_f2_wdata[27]\, - \sample_f2_wdata[28]\, \sample_f2_wdata[29]\, - \sample_f2_wdata[30]\, \sample_f2_wdata[31]\, - \sample_f2_wdata[32]\, \sample_f2_wdata[33]\, - \sample_f2_wdata[34]\, \sample_f2_wdata[35]\, - \sample_f2_wdata[36]\, \sample_f2_wdata[37]\, - \sample_f2_wdata[38]\, \sample_f2_wdata[39]\, - \sample_f2_wdata[40]\, \sample_f2_wdata[41]\, - \sample_f2_wdata[42]\, \sample_f2_wdata[43]\, - \sample_f2_wdata[44]\, \sample_f2_wdata[45]\, - \sample_f2_wdata[46]\, \sample_f2_wdata[47]\, - \sample_f2_wdata[48]\, \sample_f2_wdata[49]\, - \sample_f2_wdata[50]\, \sample_f2_wdata[51]\, - \sample_f2_wdata[52]\, \sample_f2_wdata[53]\, - \sample_f2_wdata[54]\, \sample_f2_wdata[55]\, - \sample_f2_wdata[56]\, \sample_f2_wdata[57]\, - \sample_f2_wdata[58]\, \sample_f2_wdata[59]\, - \sample_f2_wdata[60]\, \sample_f2_wdata[61]\, - \sample_f2_wdata[62]\, \sample_f2_wdata[63]\, - \sample_f2_wdata[64]\, \sample_f2_wdata[65]\, - \sample_f2_wdata[66]\, \sample_f2_wdata[67]\, - \sample_f2_wdata[68]\, \sample_f2_wdata[69]\, - \sample_f2_wdata[70]\, \sample_f2_wdata[71]\, - \sample_f2_wdata[72]\, \sample_f2_wdata[73]\, - \sample_f2_wdata[74]\, \sample_f2_wdata[75]\, - \sample_f2_wdata[76]\, \sample_f2_wdata[77]\, - \sample_f2_wdata[78]\, \sample_f2_wdata[79]\, - \sample_f2_wdata[80]\, \sample_f2_wdata[81]\, - \sample_f2_wdata[82]\, \sample_f2_wdata[83]\, - \sample_f2_wdata[84]\, \sample_f2_wdata[85]\, - \sample_f2_wdata[86]\, \sample_f2_wdata[87]\, - \sample_f2_wdata[88]\, \sample_f2_wdata[89]\, - \sample_f2_wdata[90]\, \sample_f2_wdata[91]\, - \sample_f2_wdata[92]\, \sample_f2_wdata[93]\, - \sample_f2_wdata[94]\, \sample_f2_wdata[95]\, - sample_f2_val, \sample_f3_wdata[0]\, \sample_f3_wdata[1]\, - \sample_f3_wdata[2]\, \sample_f3_wdata[3]\, - \sample_f3_wdata[4]\, \sample_f3_wdata[5]\, - \sample_f3_wdata[6]\, \sample_f3_wdata[7]\, - \sample_f3_wdata[8]\, \sample_f3_wdata[9]\, - \sample_f3_wdata[10]\, \sample_f3_wdata[11]\, - \sample_f3_wdata[12]\, \sample_f3_wdata[13]\, - \sample_f3_wdata[14]\, \sample_f3_wdata[15]\, - \sample_f3_wdata[16]\, \sample_f3_wdata[17]\, - \sample_f3_wdata[18]\, \sample_f3_wdata[19]\, - \sample_f3_wdata[20]\, \sample_f3_wdata[21]\, - \sample_f3_wdata[22]\, \sample_f3_wdata[23]\, - \sample_f3_wdata[24]\, \sample_f3_wdata[25]\, - \sample_f3_wdata[26]\, \sample_f3_wdata[27]\, - \sample_f3_wdata[28]\, \sample_f3_wdata[29]\, - \sample_f3_wdata[30]\, \sample_f3_wdata[31]\, - \sample_f3_wdata[32]\, \sample_f3_wdata[33]\, - \sample_f3_wdata[34]\, \sample_f3_wdata[35]\, - \sample_f3_wdata[36]\, \sample_f3_wdata[37]\, - \sample_f3_wdata[38]\, \sample_f3_wdata[39]\, - \sample_f3_wdata[40]\, \sample_f3_wdata[41]\, - \sample_f3_wdata[42]\, \sample_f3_wdata[43]\, - \sample_f3_wdata[44]\, \sample_f3_wdata[45]\, - \sample_f3_wdata[46]\, \sample_f3_wdata[47]\, - \sample_f3_wdata[48]\, \sample_f3_wdata[49]\, - \sample_f3_wdata[50]\, \sample_f3_wdata[51]\, - \sample_f3_wdata[52]\, \sample_f3_wdata[53]\, - \sample_f3_wdata[54]\, \sample_f3_wdata[55]\, - \sample_f3_wdata[56]\, \sample_f3_wdata[57]\, - \sample_f3_wdata[58]\, \sample_f3_wdata[59]\, - \sample_f3_wdata[60]\, \sample_f3_wdata[61]\, - \sample_f3_wdata[62]\, \sample_f3_wdata[63]\, - \sample_f3_wdata[64]\, \sample_f3_wdata[65]\, - \sample_f3_wdata[66]\, \sample_f3_wdata[67]\, - \sample_f3_wdata[68]\, \sample_f3_wdata[69]\, - \sample_f3_wdata[70]\, \sample_f3_wdata[71]\, - \sample_f3_wdata[72]\, \sample_f3_wdata[73]\, - \sample_f3_wdata[74]\, \sample_f3_wdata[75]\, - \sample_f3_wdata[76]\, \sample_f3_wdata[77]\, - \sample_f3_wdata[78]\, \sample_f3_wdata[79]\, - \sample_f3_wdata[80]\, \sample_f3_wdata[81]\, - \sample_f3_wdata[82]\, \sample_f3_wdata[83]\, - \sample_f3_wdata[84]\, \sample_f3_wdata[85]\, - \sample_f3_wdata[86]\, \sample_f3_wdata[87]\, - \sample_f3_wdata[88]\, \sample_f3_wdata[89]\, - \sample_f3_wdata[90]\, \sample_f3_wdata[91]\, - \sample_f3_wdata[92]\, \sample_f3_wdata[93]\, - \sample_f3_wdata[94]\, \sample_f3_wdata[95]\, - sample_f3_val, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : IIR_CEL_CTRLR_v2 - Use entity work.IIR_CEL_CTRLR_v2(DEF_ARCH); - for all : Downsampling_6_16_256 - Use entity work.Downsampling_6_16_256(DEF_ARCH); - for all : Downsampling_6_16_96 - Use entity work.Downsampling_6_16_96(DEF_ARCH); - for all : lpp_waveform - Use entity work.lpp_waveform(DEF_ARCH); - for all : Downsampling_8_16_4 - Use entity work.Downsampling_8_16_4(DEF_ARCH); - for all : Downsampling_8_16_6 - Use entity work.Downsampling_8_16_6(DEF_ARCH); - for all : AD7688_drvr - Use entity work.AD7688_drvr(DEF_ARCH); -begin - - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I91_un1_Y : - XA1A - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, C => N278_0, Y => - SUB_16x16_medium_area_I91_un1_Y_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I27_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[96]\, B => - \sample_filter_v2_out[114]\, Y => N202_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[29]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[29]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[29]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[97]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_257[97]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[97]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out_RNO[120]\ : - MX2 - port map(A => \sample_filter_v2_out[120]\, B => - \sample_data_shaping_f1_f0_s[5]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_133[120]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[138]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[138]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[138]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I86_Y : - AO18 - port map(A => N260, B => \sample_filter_v2_out[130]\, C => - \sample_filter_v2_out[112]\, Y => N282_i); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[117]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_205[117]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[117]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[23]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[23]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[23]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out_RNO[103]\ : - MX2 - port map(A => \sample_filter_v2_out[103]\, B => - \sample_data_shaping_f2_f1_s[4]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_113[103]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I106_Y_0 : - AX1D - port map(A => I71_un1_Y, B => N254, C => N205_0, Y => - \sample_data_shaping_f2_f1_s[13]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I100_Y_0 : - XOR2 - port map(A => N268_0, B => N193, Y => - \sample_data_shaping_f2_f1_s[7]\); - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - port map(sample_filter_v2_out_0 => - \sample_filter_v2_out[2]\, sample_filter_v2_out_1 => - \sample_filter_v2_out[3]\, sample_filter_v2_out_2 => - \sample_filter_v2_out[4]\, sample_filter_v2_out_3 => - \sample_filter_v2_out[5]\, sample_filter_v2_out_4 => - \sample_filter_v2_out[6]\, sample_filter_v2_out_5 => - \sample_filter_v2_out[7]\, sample_filter_v2_out_6 => - \sample_filter_v2_out[8]\, sample_filter_v2_out_7 => - \sample_filter_v2_out[9]\, sample_filter_v2_out_8 => - \sample_filter_v2_out[10]\, sample_filter_v2_out_9 => - \sample_filter_v2_out[11]\, sample_filter_v2_out_10 => - \sample_filter_v2_out[12]\, sample_filter_v2_out_11 => - \sample_filter_v2_out[13]\, sample_filter_v2_out_12 => - \sample_filter_v2_out[14]\, sample_filter_v2_out_13 => - \sample_filter_v2_out[15]\, sample_filter_v2_out_14 => - \sample_filter_v2_out[16]\, sample_filter_v2_out_15 => - \sample_filter_v2_out[17]\, sample_filter_v2_out_18 => - \sample_filter_v2_out[20]\, sample_filter_v2_out_19 => - \sample_filter_v2_out[21]\, sample_filter_v2_out_20 => - \sample_filter_v2_out[22]\, sample_filter_v2_out_21 => - \sample_filter_v2_out[23]\, sample_filter_v2_out_22 => - \sample_filter_v2_out[24]\, sample_filter_v2_out_23 => - \sample_filter_v2_out[25]\, sample_filter_v2_out_24 => - \sample_filter_v2_out[26]\, sample_filter_v2_out_25 => - \sample_filter_v2_out[27]\, sample_filter_v2_out_26 => - \sample_filter_v2_out[28]\, sample_filter_v2_out_27 => - \sample_filter_v2_out[29]\, sample_filter_v2_out_28 => - \sample_filter_v2_out[30]\, sample_filter_v2_out_29 => - \sample_filter_v2_out[31]\, sample_filter_v2_out_30 => - \sample_filter_v2_out[32]\, sample_filter_v2_out_31 => - \sample_filter_v2_out[33]\, sample_filter_v2_out_32 => - \sample_filter_v2_out[34]\, sample_filter_v2_out_33 => - \sample_filter_v2_out[35]\, sample_filter_v2_out_36 => - \sample_filter_v2_out[38]\, sample_filter_v2_out_37 => - \sample_filter_v2_out[39]\, sample_filter_v2_out_38 => - \sample_filter_v2_out[40]\, sample_filter_v2_out_39 => - \sample_filter_v2_out[41]\, sample_filter_v2_out_40 => - \sample_filter_v2_out[42]\, sample_filter_v2_out_41 => - \sample_filter_v2_out[43]\, sample_filter_v2_out_42 => - \sample_filter_v2_out[44]\, sample_filter_v2_out_43 => - \sample_filter_v2_out[45]\, sample_filter_v2_out_44 => - \sample_filter_v2_out[46]\, sample_filter_v2_out_45 => - \sample_filter_v2_out[47]\, sample_filter_v2_out_46 => - \sample_filter_v2_out[48]\, sample_filter_v2_out_47 => - \sample_filter_v2_out[49]\, sample_filter_v2_out_48 => - \sample_filter_v2_out[50]\, sample_filter_v2_out_49 => - \sample_filter_v2_out[51]\, sample_filter_v2_out_50 => - \sample_filter_v2_out[52]\, sample_filter_v2_out_51 => - \sample_filter_v2_out[53]\, sample_filter_v2_out_54 => - \sample_filter_v2_out[56]\, sample_filter_v2_out_55 => - \sample_filter_v2_out[57]\, sample_filter_v2_out_56 => - \sample_filter_v2_out[58]\, sample_filter_v2_out_57 => - \sample_filter_v2_out[59]\, sample_filter_v2_out_58 => - \sample_filter_v2_out[60]\, sample_filter_v2_out_59 => - \sample_filter_v2_out[61]\, sample_filter_v2_out_60 => - \sample_filter_v2_out[62]\, sample_filter_v2_out_61 => - \sample_filter_v2_out[63]\, sample_filter_v2_out_62 => - \sample_filter_v2_out[64]\, sample_filter_v2_out_63 => - \sample_filter_v2_out[65]\, sample_filter_v2_out_64 => - \sample_filter_v2_out[66]\, sample_filter_v2_out_65 => - \sample_filter_v2_out[67]\, sample_filter_v2_out_66 => - \sample_filter_v2_out[68]\, sample_filter_v2_out_67 => - \sample_filter_v2_out[69]\, sample_filter_v2_out_68 => - \sample_filter_v2_out[70]\, sample_filter_v2_out_69 => - \sample_filter_v2_out[71]\, sample_filter_v2_out_90 => - \sample_filter_v2_out[92]\, sample_filter_v2_out_91 => - \sample_filter_v2_out[93]\, sample_filter_v2_out_92 => - \sample_filter_v2_out[94]\, sample_filter_v2_out_93 => - \sample_filter_v2_out[95]\, sample_filter_v2_out_94 => - \sample_filter_v2_out[96]\, sample_filter_v2_out_95 => - \sample_filter_v2_out[97]\, sample_filter_v2_out_96 => - \sample_filter_v2_out[98]\, sample_filter_v2_out_97 => - \sample_filter_v2_out[99]\, sample_filter_v2_out_98 => - \sample_filter_v2_out[100]\, sample_filter_v2_out_99 => - \sample_filter_v2_out[101]\, sample_filter_v2_out_100 => - \sample_filter_v2_out[102]\, sample_filter_v2_out_101 => - \sample_filter_v2_out[103]\, sample_filter_v2_out_102 => - \sample_filter_v2_out[104]\, sample_filter_v2_out_103 => - \sample_filter_v2_out[105]\, sample_filter_v2_out_104 => - \sample_filter_v2_out[106]\, sample_filter_v2_out_105 => - \sample_filter_v2_out[107]\, sample_filter_v2_out_108 => - \sample_filter_v2_out[110]\, sample_filter_v2_out_126 => - \sample_filter_v2_out[128]\, sample_filter_v2_out_109 => - \sample_filter_v2_out[111]\, sample_filter_v2_out_127 => - \sample_filter_v2_out[129]\, sample_filter_v2_out_110 => - \sample_filter_v2_out[112]\, sample_filter_v2_out_128 => - \sample_filter_v2_out[130]\, sample_filter_v2_out_111 => - \sample_filter_v2_out[113]\, sample_filter_v2_out_129 => - \sample_filter_v2_out[131]\, sample_filter_v2_out_112 => - \sample_filter_v2_out[114]\, sample_filter_v2_out_130 => - \sample_filter_v2_out[132]\, sample_filter_v2_out_113 => - \sample_filter_v2_out[115]\, sample_filter_v2_out_131 => - \sample_filter_v2_out[133]\, sample_filter_v2_out_114 => - \sample_filter_v2_out[116]\, sample_filter_v2_out_132 => - \sample_filter_v2_out[134]\, sample_filter_v2_out_115 => - \sample_filter_v2_out[117]\, sample_filter_v2_out_133 => - \sample_filter_v2_out[135]\, sample_filter_v2_out_116 => - \sample_filter_v2_out[118]\, sample_filter_v2_out_134 => - \sample_filter_v2_out[136]\, sample_filter_v2_out_117 => - \sample_filter_v2_out[119]\, sample_filter_v2_out_135 => - \sample_filter_v2_out[137]\, sample_filter_v2_out_118 => - \sample_filter_v2_out[120]\, sample_filter_v2_out_136 => - \sample_filter_v2_out[138]\, sample_filter_v2_out_119 => - \sample_filter_v2_out[121]\, sample_filter_v2_out_137 => - \sample_filter_v2_out[139]\, sample_filter_v2_out_120 => - \sample_filter_v2_out[122]\, sample_filter_v2_out_138 => - \sample_filter_v2_out[140]\, sample_filter_v2_out_121 => - \sample_filter_v2_out[123]\, sample_filter_v2_out_139 => - \sample_filter_v2_out[141]\, sample_filter_v2_out_122 => - \sample_filter_v2_out[124]\, sample_filter_v2_out_140 => - \sample_filter_v2_out[142]\, sample_filter_v2_out_123 => - \sample_filter_v2_out[125]\, sample_filter_v2_out_141 => - \sample_filter_v2_out[143]\, sample_6(15) => - \sample_6[15]\, sample_6(14) => \sample_6[14]\, - sample_6(13) => \sample_6[13]\, sample_6(12) => - \sample_6[12]\, sample_6(11) => \sample_6[11]\, - sample_6(10) => \sample_6[10]\, sample_6(9) => - \sample_6[9]\, sample_6(8) => \sample_6[8]\, sample_6(7) - => \sample_6[7]\, sample_6(6) => \sample_6[6]\, - sample_6(5) => \sample_6[5]\, sample_6(4) => - \sample_6[4]\, sample_6(3) => \sample_6[3]\, sample_6(2) - => \sample_6[2]\, sample_6(1) => \sample_6[1]\, - sample_6(0) => \sample_6[0]\, sample_5(15) => - \sample_5[15]\, sample_5(14) => \sample_5[14]\, - sample_5(13) => \sample_5[13]\, sample_5(12) => - \sample_5[12]\, sample_5(11) => \sample_5[11]\, - sample_5(10) => \sample_5[10]\, sample_5(9) => - \sample_5[9]\, sample_5(8) => \sample_5[8]\, sample_5(7) - => \sample_5[7]\, sample_5(6) => \sample_5[6]\, - sample_5(5) => \sample_5[5]\, sample_5(4) => - \sample_5[4]\, sample_5(3) => \sample_5[3]\, sample_5(2) - => \sample_5[2]\, sample_5(1) => \sample_5[1]\, - sample_5(0) => \sample_5[0]\, sample_2(15) => - \sample_2[15]\, sample_2(14) => \sample_2[14]\, - sample_2(13) => \sample_2[13]\, sample_2(12) => - \sample_2[12]\, sample_2(11) => \sample_2[11]\, - sample_2(10) => \sample_2[10]\, sample_2(9) => - \sample_2[9]\, sample_2(8) => \sample_2[8]\, sample_2(7) - => \sample_2[7]\, sample_2(6) => \sample_2[6]\, - sample_2(5) => \sample_2[5]\, sample_2(4) => - \sample_2[4]\, sample_2(3) => \sample_2[3]\, sample_2(2) - => \sample_2[2]\, sample_2(1) => \sample_2[1]\, - sample_2(0) => \sample_2[0]\, sample_0(15) => - \sample_0[15]\, sample_0(14) => \sample_0[14]\, - sample_0(13) => \sample_0[13]\, sample_0(12) => - \sample_0[12]\, sample_0(11) => \sample_0[11]\, - sample_0(10) => \sample_0[10]\, sample_0(9) => - \sample_0[9]\, sample_0(8) => \sample_0[8]\, sample_0(7) - => \sample_0[7]\, sample_0(6) => \sample_0[6]\, - sample_0(5) => \sample_0[5]\, sample_0(4) => - \sample_0[4]\, sample_0(3) => \sample_0[3]\, sample_0(2) - => \sample_0[2]\, sample_0(1) => \sample_0[1]\, - sample_0(0) => \sample_0[0]\, sample_1(15) => - \sample_1[15]\, sample_1(14) => \sample_1[14]\, - sample_1(13) => \sample_1[13]\, sample_1(12) => - \sample_1[12]\, sample_1(11) => \sample_1[11]\, - sample_1(10) => \sample_1[10]\, sample_1(9) => - \sample_1[9]\, sample_1(8) => \sample_1[8]\, sample_1(7) - => \sample_1[7]\, sample_1(6) => \sample_1[6]\, - sample_1(5) => \sample_1[5]\, sample_1(4) => - \sample_1[4]\, sample_1(3) => \sample_1[3]\, sample_1(2) - => \sample_1[2]\, sample_1(1) => \sample_1[1]\, - sample_1(0) => \sample_1[0]\, sample_3(15) => - \sample_3[15]\, sample_3(14) => \sample_3[14]\, - sample_3(13) => \sample_3[13]\, sample_3(12) => - \sample_3[12]\, sample_3(11) => \sample_3[11]\, - sample_3(10) => \sample_3[10]\, sample_3(9) => - \sample_3[9]\, sample_3(8) => \sample_3[8]\, sample_3(7) - => \sample_3[7]\, sample_3(6) => \sample_3[6]\, - sample_3(5) => \sample_3[5]\, sample_3(4) => - \sample_3[4]\, sample_3(3) => \sample_3[3]\, sample_3(2) - => \sample_3[2]\, sample_3(1) => \sample_3[1]\, - sample_3(0) => \sample_3[0]\, sample_4(15) => - \sample_4[15]\, sample_4(14) => \sample_4[14]\, - sample_4(13) => \sample_4[13]\, sample_4(12) => - \sample_4[12]\, sample_4(11) => \sample_4[11]\, - sample_4(10) => \sample_4[10]\, sample_4(9) => - \sample_4[9]\, sample_4(8) => \sample_4[8]\, sample_4(7) - => \sample_4[7]\, sample_4(6) => \sample_4[6]\, - sample_4(5) => \sample_4[5]\, sample_4(4) => - \sample_4[4]\, sample_4(3) => \sample_4[3]\, sample_4(2) - => \sample_4[2]\, sample_4(1) => \sample_4[1]\, - sample_4(0) => \sample_4[0]\, sample_7(15) => - \sample_7[15]\, sample_7(14) => \sample_7[14]\, - sample_7(13) => \sample_7[13]\, sample_7(12) => - \sample_7[12]\, sample_7(11) => \sample_7[11]\, - sample_7(10) => \sample_7[10]\, sample_7(9) => - \sample_7[9]\, sample_7(8) => \sample_7[8]\, sample_7(7) - => \sample_7[7]\, sample_7(6) => \sample_7[6]\, - sample_7(5) => \sample_7[5]\, sample_7(4) => - \sample_7[4]\, sample_7(3) => \sample_7[3]\, sample_7(2) - => \sample_7[2]\, sample_7(1) => \sample_7[1]\, - sample_7(0) => \sample_7[0]\, IIR_CEL_CTRLR_v2_VCC => - lpp_top_lfr_wf_picker_ip_VCC, IIR_CEL_CTRLR_v2_GND => - lpp_top_lfr_wf_picker_ip_GND, HRESETn_c => HRESETn_c, - HCLK_c => HCLK_c, sample_filter_v2_out_val => - sample_filter_v2_out_val, sample_val_delay => - \sample_val_delay\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I101_Y_0 : - XNOR2 - port map(A => N288_i, B => N195, Y => - \sample_data_shaping_f1_f0_s[8]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[103]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_113[103]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[103]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I22_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[137]\, B => - \sample_filter_v2_out[119]\, Y => N191); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[135]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[135]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[135]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I98_Y_0 : - AX1D - port map(A => I85_un1_Y, B => N274_0, C => N189, Y => - \sample_data_shaping_f1_f0_s[5]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I24_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[135]\, B => - \sample_filter_v2_out[117]\, Y => N195); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[28]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[28]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[28]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out_RNO[110]\ : - MX2 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_data_shaping_f1_f0_s[15]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_373[110]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I108_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_filter_v2_out[128]\, C => N240, Y => - \sample_data_shaping_f1_f0_s[15]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I78_Y : - AO1 - port map(A => N268, B => N265, C => N264, Y => N270); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I71_Y : - AO1C - port map(A => N255, B => N258, C => N254_0, Y => N260); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I49_Y_0 : - AO18 - port map(A => N198_0, B => \sample_filter_v2_out[133]\, C - => \sample_filter_v2_out[115]\, Y => - SUB_16x16_medium_area_I49_Y_0_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I17_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[124]\, B => - \sample_filter_v2_out[106]\, Y => N181_0); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[30]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[30]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[30]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I33_Y : - XAI1A - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[129]\, C => N205, Y => N212_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I17_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[124]\, B => - \sample_filter_v2_out[142]\, Y => N182_0); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I104_Y_0 : - XOR2 - port map(A => N258, B => N201, Y => - \sample_data_shaping_f1_f0_s[11]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[119]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_157[119]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[119]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I49_Y_0 : - AO18 - port map(A => N198, B => \sample_filter_v2_out[115]\, C => - \sample_filter_v2_out[97]\, Y => - SUB_16x16_medium_area_I49_Y_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out_RNO[101]\ : - MX2 - port map(A => \sample_filter_v2_out[101]\, B => - \sample_data_shaping_f2_f1_s[6]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_161[101]\); - - sample_val_delay_RNI8T43 : CLKINT - port map(A => sample_val_delay_0, Y => \sample_val_delay\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I29_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[94]\, B => - \sample_filter_v2_out[112]\, Y => N206); - - \SampleLoop_data_shaping.14.sample_data_shaping_out_RNO[93]\ : - MX2 - port map(A => \sample_filter_v2_out[93]\, B => - \sample_data_shaping_f2_f1_s[14]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_353[93]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[47]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[47]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[47]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[120]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_133[120]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[120]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[13]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[13]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[13]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[32]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[32]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[32]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I21_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[102]\, B => - \sample_filter_v2_out[120]\, Y => N190); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[15]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[15]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[15]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out_RNO[95]\ : - MX2 - port map(A => \sample_filter_v2_out[95]\, B => - \sample_data_shaping_f2_f1_s[12]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_305[95]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[113]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_301[113]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[113]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y_1 : - AOI1B - port map(A => N274_0, B => N220_0, C => - SUB_16x16_medium_area_I56_Y_0_0, Y => - SUB_16x16_medium_area_I56_Y_1_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I20_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[121]\, B => - \sample_filter_v2_out[103]\, Y => N187_0); - - \SampleLoop_data_shaping.2.sample_data_shaping_out_RNO[123]\ : - MX2 - port map(A => \sample_filter_v2_out[123]\, B => - \sample_data_shaping_f1_f0_s[2]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_61[123]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[67]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[67]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[67]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I87_un1_Y : - OA1A - port map(A => I64_un1_Y, B => N244, C => N201_0, Y => - SUB_16x16_medium_area_I87_un1_Y); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I71_un1_Y : - OA1A - port map(A => I64_un1_Y, B => N244, C => N255_0, Y => - I71_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I37_Y : - NOR2B - port map(A => N199, B => N197_0, Y => N216_0); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[104]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_89[104]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[104]\); - - sample_val_delay : DFN1C0 - port map(D => sample_val, CLK => HCLK_c, CLR => HRESETn_c, - Q => sample_val_delay_0); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[35]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[35]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[35]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I48_Y : - NOR2B - port map(A => N255_0, B => N212, Y => N229); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_un1_Y_0 : - NOR2B - port map(A => N229, B => N245, Y => - SUB_16x16_medium_area_I57_un1_Y_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[129]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[129]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[129]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I94_Y_0 : - XOR2 - port map(A => N225_0, B => N181, Y => - \sample_data_shaping_f1_f0_s[1]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[107]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_17[107]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[107]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I28_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[95]\, Y => N203); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I107_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[129]\, C => N282_i, Y => - \sample_data_shaping_f1_f0_s_i[14]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I19_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[140]\, B => - \sample_filter_v2_out[122]\, Y => N185); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[137]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[137]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[137]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[11]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[11]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[11]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[46]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[46]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[46]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[110]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_373[110]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[110]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[61]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[61]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[61]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I102_Y_0 : - XOR2 - port map(A => N270, B => N197, Y => - \sample_data_shaping_f1_f0_s[9]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[68]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[68]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[68]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I42_Y : - AO13 - port map(A => N186_0, B => \sample_filter_v2_out[103]\, C - => \sample_filter_v2_out[121]\, Y => N274); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[57]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[57]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[57]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I107_Y_0 : - AX1D - port map(A => I86_un1_Y, B => N206, C => N207, Y => - \sample_data_shaping_f2_f1_s[14]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_un1_Y_0 : - XA1A - port map(A => \sample_filter_v2_out[105]\, B => - \sample_filter_v2_out[123]\, C => N225, Y => - SUB_16x16_medium_area_I53_un1_Y_0); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[49]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[49]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[49]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out_RNO[104]\ : - MX2 - port map(A => \sample_filter_v2_out[104]\, B => - \sample_data_shaping_f2_f1_s[3]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_89[104]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[17]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[17]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[17]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I92_Y : - AO18 - port map(A => N225, B => \sample_filter_v2_out[124]\, C => - \sample_filter_v2_out[106]\, Y => N294_i); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I105_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[131]\, C => N284_i, Y => - \sample_data_shaping_f1_f0_s[12]\); - - \SampleLoop_data_shaping.9.sample_data_shaping_out_RNO[116]\ : - MX2 - port map(A => \sample_filter_v2_out[116]\, B => - \sample_data_shaping_f1_f0_s[9]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_229[116]\); - - Downsampling_f3 : Downsampling_6_16_256 - port map(sample_f1(111) => \sample_f1[111]\, sample_f1(110) - => \sample_f1[110]\, sample_f1(109) => \sample_f1[109]\, - sample_f1(108) => \sample_f1[108]\, sample_f1(107) => - \sample_f1[107]\, sample_f1(106) => \sample_f1[106]\, - sample_f1(105) => \sample_f1[105]\, sample_f1(104) => - \sample_f1[104]\, sample_f1(103) => \sample_f1[103]\, - sample_f1(102) => \sample_f1[102]\, sample_f1(101) => - \sample_f1[101]\, sample_f1(100) => \sample_f1[100]\, - sample_f1(99) => \sample_f1[99]\, sample_f1(98) => - \sample_f1[98]\, sample_f1(97) => \sample_f1[97]\, - sample_f1(96) => \sample_f1[96]\, sample_f1(95) => - \sample_f1[95]\, sample_f1(94) => \sample_f1[94]\, - sample_f1(93) => \sample_f1[93]\, sample_f1(92) => - \sample_f1[92]\, sample_f1(91) => \sample_f1[91]\, - sample_f1(90) => \sample_f1[90]\, sample_f1(89) => - \sample_f1[89]\, sample_f1(88) => \sample_f1[88]\, - sample_f1(87) => \sample_f1[87]\, sample_f1(86) => - \sample_f1[86]\, sample_f1(85) => \sample_f1[85]\, - sample_f1(84) => \sample_f1[84]\, sample_f1(83) => - \sample_f1[83]\, sample_f1(82) => \sample_f1[82]\, - sample_f1(81) => \sample_f1[81]\, sample_f1(80) => - \sample_f1[80]\, sample_f1_wdata_95 => - \sample_f1_wdata[95]\, sample_f1_wdata_94 => - \sample_f1_wdata[94]\, sample_f1_wdata_93 => - \sample_f1_wdata[93]\, sample_f1_wdata_92 => - \sample_f1_wdata[92]\, sample_f1_wdata_91 => - \sample_f1_wdata[91]\, sample_f1_wdata_90 => - \sample_f1_wdata[90]\, sample_f1_wdata_89 => - \sample_f1_wdata[89]\, sample_f1_wdata_88 => - \sample_f1_wdata[88]\, sample_f1_wdata_87 => - \sample_f1_wdata[87]\, sample_f1_wdata_86 => - \sample_f1_wdata[86]\, sample_f1_wdata_85 => - \sample_f1_wdata[85]\, sample_f1_wdata_84 => - \sample_f1_wdata[84]\, sample_f1_wdata_83 => - \sample_f1_wdata[83]\, sample_f1_wdata_82 => - \sample_f1_wdata[82]\, sample_f1_wdata_81 => - \sample_f1_wdata[81]\, sample_f1_wdata_80 => - \sample_f1_wdata[80]\, sample_f1_wdata_79 => - \sample_f1_wdata[79]\, sample_f1_wdata_78 => - \sample_f1_wdata[78]\, sample_f1_wdata_77 => - \sample_f1_wdata[77]\, sample_f1_wdata_76 => - \sample_f1_wdata[76]\, sample_f1_wdata_75 => - \sample_f1_wdata[75]\, sample_f1_wdata_74 => - \sample_f1_wdata[74]\, sample_f1_wdata_73 => - \sample_f1_wdata[73]\, sample_f1_wdata_72 => - \sample_f1_wdata[72]\, sample_f1_wdata_71 => - \sample_f1_wdata[71]\, sample_f1_wdata_70 => - \sample_f1_wdata[70]\, sample_f1_wdata_69 => - \sample_f1_wdata[69]\, sample_f1_wdata_68 => - \sample_f1_wdata[68]\, sample_f1_wdata_67 => - \sample_f1_wdata[67]\, sample_f1_wdata_66 => - \sample_f1_wdata[66]\, sample_f1_wdata_65 => - \sample_f1_wdata[65]\, sample_f1_wdata_64 => - \sample_f1_wdata[64]\, sample_f1_wdata_63 => - \sample_f1_wdata[63]\, sample_f1_wdata_62 => - \sample_f1_wdata[62]\, sample_f1_wdata_61 => - \sample_f1_wdata[61]\, sample_f1_wdata_60 => - \sample_f1_wdata[60]\, sample_f1_wdata_59 => - \sample_f1_wdata[59]\, sample_f1_wdata_58 => - \sample_f1_wdata[58]\, sample_f1_wdata_57 => - \sample_f1_wdata[57]\, sample_f1_wdata_56 => - \sample_f1_wdata[56]\, sample_f1_wdata_55 => - \sample_f1_wdata[55]\, sample_f1_wdata_54 => - \sample_f1_wdata[54]\, sample_f1_wdata_53 => - \sample_f1_wdata[53]\, sample_f1_wdata_52 => - \sample_f1_wdata[52]\, sample_f1_wdata_51 => - \sample_f1_wdata[51]\, sample_f1_wdata_50 => - \sample_f1_wdata[50]\, sample_f1_wdata_49 => - \sample_f1_wdata[49]\, sample_f1_wdata_48 => - \sample_f1_wdata[48]\, sample_f1_wdata_15 => - \sample_f1_wdata[15]\, sample_f1_wdata_14 => - \sample_f1_wdata[14]\, sample_f1_wdata_13 => - \sample_f1_wdata[13]\, sample_f1_wdata_12 => - \sample_f1_wdata[12]\, sample_f1_wdata_11 => - \sample_f1_wdata[11]\, sample_f1_wdata_10 => - \sample_f1_wdata[10]\, sample_f1_wdata_9 => - \sample_f1_wdata[9]\, sample_f1_wdata_8 => - \sample_f1_wdata[8]\, sample_f1_wdata_7 => - \sample_f1_wdata[7]\, sample_f1_wdata_6 => - \sample_f1_wdata[6]\, sample_f1_wdata_5 => - \sample_f1_wdata[5]\, sample_f1_wdata_4 => - \sample_f1_wdata[4]\, sample_f1_wdata_3 => - \sample_f1_wdata[3]\, sample_f1_wdata_2 => - \sample_f1_wdata[2]\, sample_f1_wdata_1 => - \sample_f1_wdata[1]\, sample_f1_wdata_0 => - \sample_f1_wdata[0]\, sample_f3_wdata(95) => - \sample_f3_wdata[95]\, sample_f3_wdata(94) => - \sample_f3_wdata[94]\, sample_f3_wdata(93) => - \sample_f3_wdata[93]\, sample_f3_wdata(92) => - \sample_f3_wdata[92]\, sample_f3_wdata(91) => - \sample_f3_wdata[91]\, sample_f3_wdata(90) => - \sample_f3_wdata[90]\, sample_f3_wdata(89) => - \sample_f3_wdata[89]\, sample_f3_wdata(88) => - \sample_f3_wdata[88]\, sample_f3_wdata(87) => - \sample_f3_wdata[87]\, sample_f3_wdata(86) => - \sample_f3_wdata[86]\, sample_f3_wdata(85) => - \sample_f3_wdata[85]\, sample_f3_wdata(84) => - \sample_f3_wdata[84]\, sample_f3_wdata(83) => - \sample_f3_wdata[83]\, sample_f3_wdata(82) => - \sample_f3_wdata[82]\, sample_f3_wdata(81) => - \sample_f3_wdata[81]\, sample_f3_wdata(80) => - \sample_f3_wdata[80]\, sample_f3_wdata(79) => - \sample_f3_wdata[79]\, sample_f3_wdata(78) => - \sample_f3_wdata[78]\, sample_f3_wdata(77) => - \sample_f3_wdata[77]\, sample_f3_wdata(76) => - \sample_f3_wdata[76]\, sample_f3_wdata(75) => - \sample_f3_wdata[75]\, sample_f3_wdata(74) => - \sample_f3_wdata[74]\, sample_f3_wdata(73) => - \sample_f3_wdata[73]\, sample_f3_wdata(72) => - \sample_f3_wdata[72]\, sample_f3_wdata(71) => - \sample_f3_wdata[71]\, sample_f3_wdata(70) => - \sample_f3_wdata[70]\, sample_f3_wdata(69) => - \sample_f3_wdata[69]\, sample_f3_wdata(68) => - \sample_f3_wdata[68]\, sample_f3_wdata(67) => - \sample_f3_wdata[67]\, sample_f3_wdata(66) => - \sample_f3_wdata[66]\, sample_f3_wdata(65) => - \sample_f3_wdata[65]\, sample_f3_wdata(64) => - \sample_f3_wdata[64]\, sample_f3_wdata(63) => - \sample_f3_wdata[63]\, sample_f3_wdata(62) => - \sample_f3_wdata[62]\, sample_f3_wdata(61) => - \sample_f3_wdata[61]\, sample_f3_wdata(60) => - \sample_f3_wdata[60]\, sample_f3_wdata(59) => - \sample_f3_wdata[59]\, sample_f3_wdata(58) => - \sample_f3_wdata[58]\, sample_f3_wdata(57) => - \sample_f3_wdata[57]\, sample_f3_wdata(56) => - \sample_f3_wdata[56]\, sample_f3_wdata(55) => - \sample_f3_wdata[55]\, sample_f3_wdata(54) => - \sample_f3_wdata[54]\, sample_f3_wdata(53) => - \sample_f3_wdata[53]\, sample_f3_wdata(52) => - \sample_f3_wdata[52]\, sample_f3_wdata(51) => - \sample_f3_wdata[51]\, sample_f3_wdata(50) => - \sample_f3_wdata[50]\, sample_f3_wdata(49) => - \sample_f3_wdata[49]\, sample_f3_wdata(48) => - \sample_f3_wdata[48]\, sample_f3_wdata(47) => - \sample_f3_wdata[47]\, sample_f3_wdata(46) => - \sample_f3_wdata[46]\, sample_f3_wdata(45) => - \sample_f3_wdata[45]\, sample_f3_wdata(44) => - \sample_f3_wdata[44]\, sample_f3_wdata(43) => - \sample_f3_wdata[43]\, sample_f3_wdata(42) => - \sample_f3_wdata[42]\, sample_f3_wdata(41) => - \sample_f3_wdata[41]\, sample_f3_wdata(40) => - \sample_f3_wdata[40]\, sample_f3_wdata(39) => - \sample_f3_wdata[39]\, sample_f3_wdata(38) => - \sample_f3_wdata[38]\, sample_f3_wdata(37) => - \sample_f3_wdata[37]\, sample_f3_wdata(36) => - \sample_f3_wdata[36]\, sample_f3_wdata(35) => - \sample_f3_wdata[35]\, sample_f3_wdata(34) => - \sample_f3_wdata[34]\, sample_f3_wdata(33) => - \sample_f3_wdata[33]\, sample_f3_wdata(32) => - \sample_f3_wdata[32]\, sample_f3_wdata(31) => - \sample_f3_wdata[31]\, sample_f3_wdata(30) => - \sample_f3_wdata[30]\, sample_f3_wdata(29) => - \sample_f3_wdata[29]\, sample_f3_wdata(28) => - \sample_f3_wdata[28]\, sample_f3_wdata(27) => - \sample_f3_wdata[27]\, sample_f3_wdata(26) => - \sample_f3_wdata[26]\, sample_f3_wdata(25) => - \sample_f3_wdata[25]\, sample_f3_wdata(24) => - \sample_f3_wdata[24]\, sample_f3_wdata(23) => - \sample_f3_wdata[23]\, sample_f3_wdata(22) => - \sample_f3_wdata[22]\, sample_f3_wdata(21) => - \sample_f3_wdata[21]\, sample_f3_wdata(20) => - \sample_f3_wdata[20]\, sample_f3_wdata(19) => - \sample_f3_wdata[19]\, sample_f3_wdata(18) => - \sample_f3_wdata[18]\, sample_f3_wdata(17) => - \sample_f3_wdata[17]\, sample_f3_wdata(16) => - \sample_f3_wdata[16]\, sample_f3_wdata(15) => - \sample_f3_wdata[15]\, sample_f3_wdata(14) => - \sample_f3_wdata[14]\, sample_f3_wdata(13) => - \sample_f3_wdata[13]\, sample_f3_wdata(12) => - \sample_f3_wdata[12]\, sample_f3_wdata(11) => - \sample_f3_wdata[11]\, sample_f3_wdata(10) => - \sample_f3_wdata[10]\, sample_f3_wdata(9) => - \sample_f3_wdata[9]\, sample_f3_wdata(8) => - \sample_f3_wdata[8]\, sample_f3_wdata(7) => - \sample_f3_wdata[7]\, sample_f3_wdata(6) => - \sample_f3_wdata[6]\, sample_f3_wdata(5) => - \sample_f3_wdata[5]\, sample_f3_wdata(4) => - \sample_f3_wdata[4]\, sample_f3_wdata(3) => - \sample_f3_wdata[3]\, sample_f3_wdata(2) => - \sample_f3_wdata[2]\, sample_f3_wdata(1) => - \sample_f3_wdata[1]\, sample_f3_wdata(0) => - \sample_f3_wdata[0]\, sample_f1_val => sample_f1_val, - HCLK_c => HCLK_c, sample_f3_val => sample_f3_val, - HRESETn_c => HRESETn_c, sample_f1_val_0 => - sample_f1_val_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I34_Y : - AO18 - port map(A => N202, B => \sample_filter_v2_out[131]\, C => - \sample_filter_v2_out[113]\, Y => N254_0); - - \SampleLoop_data_shaping.10.sample_data_shaping_out_RNO[115]\ : - MX2 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_data_shaping_f1_f0_s[10]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_253[115]\); - - GND_i : GND - port map(Y => \GND\); - - Downsampling_f2 : Downsampling_6_16_96 - port map(sample_f0(111) => \sample_f0[111]\, sample_f0(110) - => \sample_f0[110]\, sample_f0(109) => \sample_f0[109]\, - sample_f0(108) => \sample_f0[108]\, sample_f0(107) => - \sample_f0[107]\, sample_f0(106) => \sample_f0[106]\, - sample_f0(105) => \sample_f0[105]\, sample_f0(104) => - \sample_f0[104]\, sample_f0(103) => \sample_f0[103]\, - sample_f0(102) => \sample_f0[102]\, sample_f0(101) => - \sample_f0[101]\, sample_f0(100) => \sample_f0[100]\, - sample_f0(99) => \sample_f0[99]\, sample_f0(98) => - \sample_f0[98]\, sample_f0(97) => \sample_f0[97]\, - sample_f0(96) => \sample_f0[96]\, sample_f0(95) => - \sample_f0[95]\, sample_f0(94) => \sample_f0[94]\, - sample_f0(93) => \sample_f0[93]\, sample_f0(92) => - \sample_f0[92]\, sample_f0(91) => \sample_f0[91]\, - sample_f0(90) => \sample_f0[90]\, sample_f0(89) => - \sample_f0[89]\, sample_f0(88) => \sample_f0[88]\, - sample_f0(87) => \sample_f0[87]\, sample_f0(86) => - \sample_f0[86]\, sample_f0(85) => \sample_f0[85]\, - sample_f0(84) => \sample_f0[84]\, sample_f0(83) => - \sample_f0[83]\, sample_f0(82) => \sample_f0[82]\, - sample_f0(81) => \sample_f0[81]\, sample_f0(80) => - \sample_f0[80]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_f2_wdata(95) => - \sample_f2_wdata[95]\, sample_f2_wdata(94) => - \sample_f2_wdata[94]\, sample_f2_wdata(93) => - \sample_f2_wdata[93]\, sample_f2_wdata(92) => - \sample_f2_wdata[92]\, sample_f2_wdata(91) => - \sample_f2_wdata[91]\, sample_f2_wdata(90) => - \sample_f2_wdata[90]\, sample_f2_wdata(89) => - \sample_f2_wdata[89]\, sample_f2_wdata(88) => - \sample_f2_wdata[88]\, sample_f2_wdata(87) => - \sample_f2_wdata[87]\, sample_f2_wdata(86) => - \sample_f2_wdata[86]\, sample_f2_wdata(85) => - \sample_f2_wdata[85]\, sample_f2_wdata(84) => - \sample_f2_wdata[84]\, sample_f2_wdata(83) => - \sample_f2_wdata[83]\, sample_f2_wdata(82) => - \sample_f2_wdata[82]\, sample_f2_wdata(81) => - \sample_f2_wdata[81]\, sample_f2_wdata(80) => - \sample_f2_wdata[80]\, sample_f2_wdata(79) => - \sample_f2_wdata[79]\, sample_f2_wdata(78) => - \sample_f2_wdata[78]\, sample_f2_wdata(77) => - \sample_f2_wdata[77]\, sample_f2_wdata(76) => - \sample_f2_wdata[76]\, sample_f2_wdata(75) => - \sample_f2_wdata[75]\, sample_f2_wdata(74) => - \sample_f2_wdata[74]\, sample_f2_wdata(73) => - \sample_f2_wdata[73]\, sample_f2_wdata(72) => - \sample_f2_wdata[72]\, sample_f2_wdata(71) => - \sample_f2_wdata[71]\, sample_f2_wdata(70) => - \sample_f2_wdata[70]\, sample_f2_wdata(69) => - \sample_f2_wdata[69]\, sample_f2_wdata(68) => - \sample_f2_wdata[68]\, sample_f2_wdata(67) => - \sample_f2_wdata[67]\, sample_f2_wdata(66) => - \sample_f2_wdata[66]\, sample_f2_wdata(65) => - \sample_f2_wdata[65]\, sample_f2_wdata(64) => - \sample_f2_wdata[64]\, sample_f2_wdata(63) => - \sample_f2_wdata[63]\, sample_f2_wdata(62) => - \sample_f2_wdata[62]\, sample_f2_wdata(61) => - \sample_f2_wdata[61]\, sample_f2_wdata(60) => - \sample_f2_wdata[60]\, sample_f2_wdata(59) => - \sample_f2_wdata[59]\, sample_f2_wdata(58) => - \sample_f2_wdata[58]\, sample_f2_wdata(57) => - \sample_f2_wdata[57]\, sample_f2_wdata(56) => - \sample_f2_wdata[56]\, sample_f2_wdata(55) => - \sample_f2_wdata[55]\, sample_f2_wdata(54) => - \sample_f2_wdata[54]\, sample_f2_wdata(53) => - \sample_f2_wdata[53]\, sample_f2_wdata(52) => - \sample_f2_wdata[52]\, sample_f2_wdata(51) => - \sample_f2_wdata[51]\, sample_f2_wdata(50) => - \sample_f2_wdata[50]\, sample_f2_wdata(49) => - \sample_f2_wdata[49]\, sample_f2_wdata(48) => - \sample_f2_wdata[48]\, sample_f2_wdata(47) => - \sample_f2_wdata[47]\, sample_f2_wdata(46) => - \sample_f2_wdata[46]\, sample_f2_wdata(45) => - \sample_f2_wdata[45]\, sample_f2_wdata(44) => - \sample_f2_wdata[44]\, sample_f2_wdata(43) => - \sample_f2_wdata[43]\, sample_f2_wdata(42) => - \sample_f2_wdata[42]\, sample_f2_wdata(41) => - \sample_f2_wdata[41]\, sample_f2_wdata(40) => - \sample_f2_wdata[40]\, sample_f2_wdata(39) => - \sample_f2_wdata[39]\, sample_f2_wdata(38) => - \sample_f2_wdata[38]\, sample_f2_wdata(37) => - \sample_f2_wdata[37]\, sample_f2_wdata(36) => - \sample_f2_wdata[36]\, sample_f2_wdata(35) => - \sample_f2_wdata[35]\, sample_f2_wdata(34) => - \sample_f2_wdata[34]\, sample_f2_wdata(33) => - \sample_f2_wdata[33]\, sample_f2_wdata(32) => - \sample_f2_wdata[32]\, sample_f2_wdata(31) => - \sample_f2_wdata[31]\, sample_f2_wdata(30) => - \sample_f2_wdata[30]\, sample_f2_wdata(29) => - \sample_f2_wdata[29]\, sample_f2_wdata(28) => - \sample_f2_wdata[28]\, sample_f2_wdata(27) => - \sample_f2_wdata[27]\, sample_f2_wdata(26) => - \sample_f2_wdata[26]\, sample_f2_wdata(25) => - \sample_f2_wdata[25]\, sample_f2_wdata(24) => - \sample_f2_wdata[24]\, sample_f2_wdata(23) => - \sample_f2_wdata[23]\, sample_f2_wdata(22) => - \sample_f2_wdata[22]\, sample_f2_wdata(21) => - \sample_f2_wdata[21]\, sample_f2_wdata(20) => - \sample_f2_wdata[20]\, sample_f2_wdata(19) => - \sample_f2_wdata[19]\, sample_f2_wdata(18) => - \sample_f2_wdata[18]\, sample_f2_wdata(17) => - \sample_f2_wdata[17]\, sample_f2_wdata(16) => - \sample_f2_wdata[16]\, sample_f2_wdata(15) => - \sample_f2_wdata[15]\, sample_f2_wdata(14) => - \sample_f2_wdata[14]\, sample_f2_wdata(13) => - \sample_f2_wdata[13]\, sample_f2_wdata(12) => - \sample_f2_wdata[12]\, sample_f2_wdata(11) => - \sample_f2_wdata[11]\, sample_f2_wdata(10) => - \sample_f2_wdata[10]\, sample_f2_wdata(9) => - \sample_f2_wdata[9]\, sample_f2_wdata(8) => - \sample_f2_wdata[8]\, sample_f2_wdata(7) => - \sample_f2_wdata[7]\, sample_f2_wdata(6) => - \sample_f2_wdata[6]\, sample_f2_wdata(5) => - \sample_f2_wdata[5]\, sample_f2_wdata(4) => - \sample_f2_wdata[4]\, sample_f2_wdata(3) => - \sample_f2_wdata[3]\, sample_f2_wdata(2) => - \sample_f2_wdata[2]\, sample_f2_wdata(1) => - \sample_f2_wdata[1]\, sample_f2_wdata(0) => - \sample_f2_wdata[0]\, sample_f0_val => sample_f0_val, - sample_f0_val_1 => sample_f0_val_1, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, sample_f2_val => - sample_f2_val, sample_f0_val_0 => sample_f0_val_0, - sample_out_0_sqmuxa_1 => sample_out_0_sqmuxa_1); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I38_Y : - AO13 - port map(A => N194_0, B => \sample_filter_v2_out[99]\, C - => \sample_filter_v2_out[117]\, Y => N264_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I95_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[105]\, B => - \sample_filter_v2_out[123]\, C => N294_i, Y => - \sample_data_shaping_f2_f1_s[2]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[33]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[33]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[33]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_Y : - OR2B - port map(A => SUB_16x16_medium_area_I53_Y_0_0, B => - I53_un1_Y, Y => N278); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y : - AO1B - port map(A => SUB_16x16_medium_area_I56_un1_Y_0, B => N278, - C => SUB_16x16_medium_area_I56_Y_1_0, Y => N268); - - \SampleLoop_data_shaping.14.sample_data_shaping_out_RNO[111]\ : - MX2B - port map(A => \sample_filter_v2_out[111]\, B => - \sample_data_shaping_f1_f0_s_i[14]\, S => - data_shaping_SP0, Y => \sample_data_shaping_out_349[111]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I89_Y : - AO18 - port map(A => N268, B => \sample_filter_v2_out[136]\, C => - \sample_filter_v2_out[118]\, Y => N288_i); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[122]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_85[122]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[122]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[20]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[20]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[20]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_Y : - AO1B - port map(A => SUB_16x16_medium_area_I53_un1_Y_0, B => - N181_0, C => SUB_16x16_medium_area_I53_Y_0, Y => N278_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I87_Y : - AO18 - port map(A => N258, B => \sample_filter_v2_out[132]\, C => - \sample_filter_v2_out[114]\, Y => N284_i); - - \SampleLoop_data_shaping.11.sample_data_shaping_out_RNO[96]\ : - MX2 - port map(A => \sample_filter_v2_out[96]\, B => - \sample_data_shaping_f2_f1_s[11]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_281[96]\); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[3]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[3]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[3]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_un1_Y_0 : - NOR2B - port map(A => N229_0, B => N245_0, Y => - SUB_16x16_medium_area_I57_un1_Y_0_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I43_Y : - NOR2B - port map(A => N187, B => N185, Y => N275); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[58]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[58]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[58]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I46_Y : - OR2A - port map(A => \sample_filter_v2_out[143]\, B => - \sample_filter_v2_out[125]\, Y => N225_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[26]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[26]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[26]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[56]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[56]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[56]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I102_Y_0 : - AX1D - port map(A => I78_un1_Y, B => N264_0, C => N197_0, Y => - \sample_data_shaping_f2_f1_s[9]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I21_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[138]\, B => - \sample_filter_v2_out[120]\, Y => N189); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[143]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[143]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[143]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I26_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[97]\, Y => N199); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I88_un1_Y : - OA1 - port map(A => I78_un1_Y, B => N264_0, C => N197_0, Y => - I88_un1_Y); - - \SampleLoop_data_shaping.0.sample_data_shaping_out_RNO[107]\ : - AX1C - port map(A => \sample_filter_v2_out[125]\, B => - data_shaping_SP1, C => \sample_filter_v2_out[107]\, Y => - \sample_data_shaping_out_17[107]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I85_Y : - AO1 - port map(A => N278_0, B => N275_0, C => N274, Y => N280); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[27]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[27]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[27]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I85_un1_Y : - NOR2B - port map(A => N278, B => N275, Y => I85_un1_Y); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[136]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[136]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[136]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I39_Y : - XA1A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N195, Y => N265); - - lpp_waveform_1 : lpp_waveform - port map(status_full_ack(3) => status_full_ack(3), - status_full_ack(2) => status_full_ack(2), - status_full_ack(1) => status_full_ack(1), - status_full_ack(0) => status_full_ack(0), hburst_c(2) => - hburst_c(2), hburst_c(1) => hburst_c(1), hburst_c(0) => - hburst_c(0), htrans_c(1) => htrans_c(1), htrans_c(0) => - htrans_c(0), hsize_c(1) => hsize_c(1), hsize_c(0) => - hsize_c(0), AHB_Master_In_c_5 => AHB_Master_In_c_5, - AHB_Master_In_c_4 => AHB_Master_In_c_4, AHB_Master_In_c_0 - => AHB_Master_In_c_0, AHB_Master_In_c_3 => - AHB_Master_In_c_3, haddr_c(31) => haddr_c(31), - haddr_c(30) => haddr_c(30), haddr_c(29) => haddr_c(29), - haddr_c(28) => haddr_c(28), haddr_c(27) => haddr_c(27), - haddr_c(26) => haddr_c(26), haddr_c(25) => haddr_c(25), - haddr_c(24) => haddr_c(24), haddr_c(23) => haddr_c(23), - haddr_c(22) => haddr_c(22), haddr_c(21) => haddr_c(21), - haddr_c(20) => haddr_c(20), haddr_c(19) => haddr_c(19), - haddr_c(18) => haddr_c(18), haddr_c(17) => haddr_c(17), - haddr_c(16) => haddr_c(16), haddr_c(15) => haddr_c(15), - haddr_c(14) => haddr_c(14), haddr_c(13) => haddr_c(13), - haddr_c(12) => haddr_c(12), haddr_c(11) => haddr_c(11), - haddr_c(10) => haddr_c(10), haddr_c(9) => haddr_c(9), - haddr_c(8) => haddr_c(8), haddr_c(7) => haddr_c(7), - haddr_c(6) => haddr_c(6), haddr_c(5) => haddr_c(5), - haddr_c(4) => haddr_c(4), haddr_c(3) => haddr_c(3), - haddr_c(2) => haddr_c(2), haddr_c(1) => haddr_c(1), - haddr_c(0) => haddr_c(0), nb_burst_available(10) => - nb_burst_available(10), nb_burst_available(9) => - nb_burst_available(9), nb_burst_available(8) => - nb_burst_available(8), nb_burst_available(7) => - nb_burst_available(7), nb_burst_available(6) => - nb_burst_available(6), nb_burst_available(5) => - nb_burst_available(5), nb_burst_available(4) => - nb_burst_available(4), nb_burst_available(3) => - nb_burst_available(3), nb_burst_available(2) => - nb_burst_available(2), nb_burst_available(1) => - nb_burst_available(1), nb_burst_available(0) => - nb_burst_available(0), status_full_err(3) => - status_full_err(3), status_full_err(2) => - status_full_err(2), status_full_err(1) => - status_full_err(1), status_full_err(0) => - status_full_err(0), status_full(3) => status_full(3), - status_full(2) => status_full(2), status_full(1) => - status_full(1), status_full(0) => status_full(0), - addr_data_f3(31) => addr_data_f3(31), addr_data_f3(30) - => addr_data_f3(30), addr_data_f3(29) => - addr_data_f3(29), addr_data_f3(28) => addr_data_f3(28), - addr_data_f3(27) => addr_data_f3(27), addr_data_f3(26) - => addr_data_f3(26), addr_data_f3(25) => - addr_data_f3(25), addr_data_f3(24) => addr_data_f3(24), - addr_data_f3(23) => addr_data_f3(23), addr_data_f3(22) - => addr_data_f3(22), addr_data_f3(21) => - addr_data_f3(21), addr_data_f3(20) => addr_data_f3(20), - addr_data_f3(19) => addr_data_f3(19), addr_data_f3(18) - => addr_data_f3(18), addr_data_f3(17) => - addr_data_f3(17), addr_data_f3(16) => addr_data_f3(16), - addr_data_f3(15) => addr_data_f3(15), addr_data_f3(14) - => addr_data_f3(14), addr_data_f3(13) => - addr_data_f3(13), addr_data_f3(12) => addr_data_f3(12), - addr_data_f3(11) => addr_data_f3(11), addr_data_f3(10) - => addr_data_f3(10), addr_data_f3(9) => addr_data_f3(9), - addr_data_f3(8) => addr_data_f3(8), addr_data_f3(7) => - addr_data_f3(7), addr_data_f3(6) => addr_data_f3(6), - addr_data_f3(5) => addr_data_f3(5), addr_data_f3(4) => - addr_data_f3(4), addr_data_f3(3) => addr_data_f3(3), - addr_data_f3(2) => addr_data_f3(2), addr_data_f3(1) => - addr_data_f3(1), addr_data_f3(0) => addr_data_f3(0), - addr_data_f2(31) => addr_data_f2(31), addr_data_f2(30) - => addr_data_f2(30), addr_data_f2(29) => - addr_data_f2(29), addr_data_f2(28) => addr_data_f2(28), - addr_data_f2(27) => addr_data_f2(27), addr_data_f2(26) - => addr_data_f2(26), addr_data_f2(25) => - addr_data_f2(25), addr_data_f2(24) => addr_data_f2(24), - addr_data_f2(23) => addr_data_f2(23), addr_data_f2(22) - => addr_data_f2(22), addr_data_f2(21) => - addr_data_f2(21), addr_data_f2(20) => addr_data_f2(20), - addr_data_f2(19) => addr_data_f2(19), addr_data_f2(18) - => addr_data_f2(18), addr_data_f2(17) => - addr_data_f2(17), addr_data_f2(16) => addr_data_f2(16), - addr_data_f2(15) => addr_data_f2(15), addr_data_f2(14) - => addr_data_f2(14), addr_data_f2(13) => - addr_data_f2(13), addr_data_f2(12) => addr_data_f2(12), - addr_data_f2(11) => addr_data_f2(11), addr_data_f2(10) - => addr_data_f2(10), addr_data_f2(9) => addr_data_f2(9), - addr_data_f2(8) => addr_data_f2(8), addr_data_f2(7) => - addr_data_f2(7), addr_data_f2(6) => addr_data_f2(6), - addr_data_f2(5) => addr_data_f2(5), addr_data_f2(4) => - addr_data_f2(4), addr_data_f2(3) => addr_data_f2(3), - addr_data_f2(2) => addr_data_f2(2), addr_data_f2(1) => - addr_data_f2(1), addr_data_f2(0) => addr_data_f2(0), - addr_data_f1(31) => addr_data_f1(31), addr_data_f1(30) - => addr_data_f1(30), addr_data_f1(29) => - addr_data_f1(29), addr_data_f1(28) => addr_data_f1(28), - addr_data_f1(27) => addr_data_f1(27), addr_data_f1(26) - => addr_data_f1(26), addr_data_f1(25) => - addr_data_f1(25), addr_data_f1(24) => addr_data_f1(24), - addr_data_f1(23) => addr_data_f1(23), addr_data_f1(22) - => addr_data_f1(22), addr_data_f1(21) => - addr_data_f1(21), addr_data_f1(20) => addr_data_f1(20), - addr_data_f1(19) => addr_data_f1(19), addr_data_f1(18) - => addr_data_f1(18), addr_data_f1(17) => - addr_data_f1(17), addr_data_f1(16) => addr_data_f1(16), - addr_data_f1(15) => addr_data_f1(15), addr_data_f1(14) - => addr_data_f1(14), addr_data_f1(13) => - addr_data_f1(13), addr_data_f1(12) => addr_data_f1(12), - addr_data_f1(11) => addr_data_f1(11), addr_data_f1(10) - => addr_data_f1(10), addr_data_f1(9) => addr_data_f1(9), - addr_data_f1(8) => addr_data_f1(8), addr_data_f1(7) => - addr_data_f1(7), addr_data_f1(6) => addr_data_f1(6), - addr_data_f1(5) => addr_data_f1(5), addr_data_f1(4) => - addr_data_f1(4), addr_data_f1(3) => addr_data_f1(3), - addr_data_f1(2) => addr_data_f1(2), addr_data_f1(1) => - addr_data_f1(1), addr_data_f1(0) => addr_data_f1(0), - addr_data_f0(31) => addr_data_f0(31), addr_data_f0(30) - => addr_data_f0(30), addr_data_f0(29) => - addr_data_f0(29), addr_data_f0(28) => addr_data_f0(28), - addr_data_f0(27) => addr_data_f0(27), addr_data_f0(26) - => addr_data_f0(26), addr_data_f0(25) => - addr_data_f0(25), addr_data_f0(24) => addr_data_f0(24), - addr_data_f0(23) => addr_data_f0(23), addr_data_f0(22) - => addr_data_f0(22), addr_data_f0(21) => - addr_data_f0(21), addr_data_f0(20) => addr_data_f0(20), - addr_data_f0(19) => addr_data_f0(19), addr_data_f0(18) - => addr_data_f0(18), addr_data_f0(17) => - addr_data_f0(17), addr_data_f0(16) => addr_data_f0(16), - addr_data_f0(15) => addr_data_f0(15), addr_data_f0(14) - => addr_data_f0(14), addr_data_f0(13) => - addr_data_f0(13), addr_data_f0(12) => addr_data_f0(12), - addr_data_f0(11) => addr_data_f0(11), addr_data_f0(10) - => addr_data_f0(10), addr_data_f0(9) => addr_data_f0(9), - addr_data_f0(8) => addr_data_f0(8), addr_data_f0(7) => - addr_data_f0(7), addr_data_f0(6) => addr_data_f0(6), - addr_data_f0(5) => addr_data_f0(5), addr_data_f0(4) => - addr_data_f0(4), addr_data_f0(3) => addr_data_f0(3), - addr_data_f0(2) => addr_data_f0(2), addr_data_f0(1) => - addr_data_f0(1), addr_data_f0(0) => addr_data_f0(0), - hwdata_c(31) => hwdata_c(31), hwdata_c(30) => - hwdata_c(30), hwdata_c(29) => hwdata_c(29), hwdata_c(28) - => hwdata_c(28), hwdata_c(27) => hwdata_c(27), - hwdata_c(26) => hwdata_c(26), hwdata_c(25) => - hwdata_c(25), hwdata_c(24) => hwdata_c(24), hwdata_c(23) - => hwdata_c(23), hwdata_c(22) => hwdata_c(22), - hwdata_c(21) => hwdata_c(21), hwdata_c(20) => - hwdata_c(20), hwdata_c(19) => hwdata_c(19), hwdata_c(18) - => hwdata_c(18), hwdata_c(17) => hwdata_c(17), - hwdata_c(16) => hwdata_c(16), hwdata_c(15) => - hwdata_c(15), hwdata_c(14) => hwdata_c(14), hwdata_c(13) - => hwdata_c(13), hwdata_c(12) => hwdata_c(12), - hwdata_c(11) => hwdata_c(11), hwdata_c(10) => - hwdata_c(10), hwdata_c(9) => hwdata_c(9), hwdata_c(8) => - hwdata_c(8), hwdata_c(7) => hwdata_c(7), hwdata_c(6) => - hwdata_c(6), hwdata_c(5) => hwdata_c(5), hwdata_c(4) => - hwdata_c(4), hwdata_c(3) => hwdata_c(3), hwdata_c(2) => - hwdata_c(2), hwdata_c(1) => hwdata_c(1), hwdata_c(0) => - hwdata_c(0), status_new_err(3) => status_new_err(3), - status_new_err(2) => status_new_err(2), status_new_err(1) - => status_new_err(1), status_new_err(0) => - status_new_err(0), sample_f3_wdata(95) => - \sample_f3_wdata[95]\, sample_f3_wdata(94) => - \sample_f3_wdata[94]\, sample_f3_wdata(93) => - \sample_f3_wdata[93]\, sample_f3_wdata(92) => - \sample_f3_wdata[92]\, sample_f3_wdata(91) => - \sample_f3_wdata[91]\, sample_f3_wdata(90) => - \sample_f3_wdata[90]\, sample_f3_wdata(89) => - \sample_f3_wdata[89]\, sample_f3_wdata(88) => - \sample_f3_wdata[88]\, sample_f3_wdata(87) => - \sample_f3_wdata[87]\, sample_f3_wdata(86) => - \sample_f3_wdata[86]\, sample_f3_wdata(85) => - \sample_f3_wdata[85]\, sample_f3_wdata(84) => - \sample_f3_wdata[84]\, sample_f3_wdata(83) => - \sample_f3_wdata[83]\, sample_f3_wdata(82) => - \sample_f3_wdata[82]\, sample_f3_wdata(81) => - \sample_f3_wdata[81]\, sample_f3_wdata(80) => - \sample_f3_wdata[80]\, sample_f3_wdata(79) => - \sample_f3_wdata[79]\, sample_f3_wdata(78) => - \sample_f3_wdata[78]\, sample_f3_wdata(77) => - \sample_f3_wdata[77]\, sample_f3_wdata(76) => - \sample_f3_wdata[76]\, sample_f3_wdata(75) => - \sample_f3_wdata[75]\, sample_f3_wdata(74) => - \sample_f3_wdata[74]\, sample_f3_wdata(73) => - \sample_f3_wdata[73]\, sample_f3_wdata(72) => - \sample_f3_wdata[72]\, sample_f3_wdata(71) => - \sample_f3_wdata[71]\, sample_f3_wdata(70) => - \sample_f3_wdata[70]\, sample_f3_wdata(69) => - \sample_f3_wdata[69]\, sample_f3_wdata(68) => - \sample_f3_wdata[68]\, sample_f3_wdata(67) => - \sample_f3_wdata[67]\, sample_f3_wdata(66) => - \sample_f3_wdata[66]\, sample_f3_wdata(65) => - \sample_f3_wdata[65]\, sample_f3_wdata(64) => - \sample_f3_wdata[64]\, sample_f3_wdata(63) => - \sample_f3_wdata[63]\, sample_f3_wdata(62) => - \sample_f3_wdata[62]\, sample_f3_wdata(61) => - \sample_f3_wdata[61]\, sample_f3_wdata(60) => - \sample_f3_wdata[60]\, sample_f3_wdata(59) => - \sample_f3_wdata[59]\, sample_f3_wdata(58) => - \sample_f3_wdata[58]\, sample_f3_wdata(57) => - \sample_f3_wdata[57]\, sample_f3_wdata(56) => - \sample_f3_wdata[56]\, sample_f3_wdata(55) => - \sample_f3_wdata[55]\, sample_f3_wdata(54) => - \sample_f3_wdata[54]\, sample_f3_wdata(53) => - \sample_f3_wdata[53]\, sample_f3_wdata(52) => - \sample_f3_wdata[52]\, sample_f3_wdata(51) => - \sample_f3_wdata[51]\, sample_f3_wdata(50) => - \sample_f3_wdata[50]\, sample_f3_wdata(49) => - \sample_f3_wdata[49]\, sample_f3_wdata(48) => - \sample_f3_wdata[48]\, sample_f3_wdata(47) => - \sample_f3_wdata[47]\, sample_f3_wdata(46) => - \sample_f3_wdata[46]\, sample_f3_wdata(45) => - \sample_f3_wdata[45]\, sample_f3_wdata(44) => - \sample_f3_wdata[44]\, sample_f3_wdata(43) => - \sample_f3_wdata[43]\, sample_f3_wdata(42) => - \sample_f3_wdata[42]\, sample_f3_wdata(41) => - \sample_f3_wdata[41]\, sample_f3_wdata(40) => - \sample_f3_wdata[40]\, sample_f3_wdata(39) => - \sample_f3_wdata[39]\, sample_f3_wdata(38) => - \sample_f3_wdata[38]\, sample_f3_wdata(37) => - \sample_f3_wdata[37]\, sample_f3_wdata(36) => - \sample_f3_wdata[36]\, sample_f3_wdata(35) => - \sample_f3_wdata[35]\, sample_f3_wdata(34) => - \sample_f3_wdata[34]\, sample_f3_wdata(33) => - \sample_f3_wdata[33]\, sample_f3_wdata(32) => - \sample_f3_wdata[32]\, sample_f3_wdata(31) => - \sample_f3_wdata[31]\, sample_f3_wdata(30) => - \sample_f3_wdata[30]\, sample_f3_wdata(29) => - \sample_f3_wdata[29]\, sample_f3_wdata(28) => - \sample_f3_wdata[28]\, sample_f3_wdata(27) => - \sample_f3_wdata[27]\, sample_f3_wdata(26) => - \sample_f3_wdata[26]\, sample_f3_wdata(25) => - \sample_f3_wdata[25]\, sample_f3_wdata(24) => - \sample_f3_wdata[24]\, sample_f3_wdata(23) => - \sample_f3_wdata[23]\, sample_f3_wdata(22) => - \sample_f3_wdata[22]\, sample_f3_wdata(21) => - \sample_f3_wdata[21]\, sample_f3_wdata(20) => - \sample_f3_wdata[20]\, sample_f3_wdata(19) => - \sample_f3_wdata[19]\, sample_f3_wdata(18) => - \sample_f3_wdata[18]\, sample_f3_wdata(17) => - \sample_f3_wdata[17]\, sample_f3_wdata(16) => - \sample_f3_wdata[16]\, sample_f3_wdata(15) => - \sample_f3_wdata[15]\, sample_f3_wdata(14) => - \sample_f3_wdata[14]\, sample_f3_wdata(13) => - \sample_f3_wdata[13]\, sample_f3_wdata(12) => - \sample_f3_wdata[12]\, sample_f3_wdata(11) => - \sample_f3_wdata[11]\, sample_f3_wdata(10) => - \sample_f3_wdata[10]\, sample_f3_wdata(9) => - \sample_f3_wdata[9]\, sample_f3_wdata(8) => - \sample_f3_wdata[8]\, sample_f3_wdata(7) => - \sample_f3_wdata[7]\, sample_f3_wdata(6) => - \sample_f3_wdata[6]\, sample_f3_wdata(5) => - \sample_f3_wdata[5]\, sample_f3_wdata(4) => - \sample_f3_wdata[4]\, sample_f3_wdata(3) => - \sample_f3_wdata[3]\, sample_f3_wdata(2) => - \sample_f3_wdata[2]\, sample_f3_wdata(1) => - \sample_f3_wdata[1]\, sample_f3_wdata(0) => - \sample_f3_wdata[0]\, sample_f2_wdata(95) => - \sample_f2_wdata[95]\, sample_f2_wdata(94) => - \sample_f2_wdata[94]\, sample_f2_wdata(93) => - \sample_f2_wdata[93]\, sample_f2_wdata(92) => - \sample_f2_wdata[92]\, sample_f2_wdata(91) => - \sample_f2_wdata[91]\, sample_f2_wdata(90) => - \sample_f2_wdata[90]\, sample_f2_wdata(89) => - \sample_f2_wdata[89]\, sample_f2_wdata(88) => - \sample_f2_wdata[88]\, sample_f2_wdata(87) => - \sample_f2_wdata[87]\, sample_f2_wdata(86) => - \sample_f2_wdata[86]\, sample_f2_wdata(85) => - \sample_f2_wdata[85]\, sample_f2_wdata(84) => - \sample_f2_wdata[84]\, sample_f2_wdata(83) => - \sample_f2_wdata[83]\, sample_f2_wdata(82) => - \sample_f2_wdata[82]\, sample_f2_wdata(81) => - \sample_f2_wdata[81]\, sample_f2_wdata(80) => - \sample_f2_wdata[80]\, sample_f2_wdata(79) => - \sample_f2_wdata[79]\, sample_f2_wdata(78) => - \sample_f2_wdata[78]\, sample_f2_wdata(77) => - \sample_f2_wdata[77]\, sample_f2_wdata(76) => - \sample_f2_wdata[76]\, sample_f2_wdata(75) => - \sample_f2_wdata[75]\, sample_f2_wdata(74) => - \sample_f2_wdata[74]\, sample_f2_wdata(73) => - \sample_f2_wdata[73]\, sample_f2_wdata(72) => - \sample_f2_wdata[72]\, sample_f2_wdata(71) => - \sample_f2_wdata[71]\, sample_f2_wdata(70) => - \sample_f2_wdata[70]\, sample_f2_wdata(69) => - \sample_f2_wdata[69]\, sample_f2_wdata(68) => - \sample_f2_wdata[68]\, sample_f2_wdata(67) => - \sample_f2_wdata[67]\, sample_f2_wdata(66) => - \sample_f2_wdata[66]\, sample_f2_wdata(65) => - \sample_f2_wdata[65]\, sample_f2_wdata(64) => - \sample_f2_wdata[64]\, sample_f2_wdata(63) => - \sample_f2_wdata[63]\, sample_f2_wdata(62) => - \sample_f2_wdata[62]\, sample_f2_wdata(61) => - \sample_f2_wdata[61]\, sample_f2_wdata(60) => - \sample_f2_wdata[60]\, sample_f2_wdata(59) => - \sample_f2_wdata[59]\, sample_f2_wdata(58) => - \sample_f2_wdata[58]\, sample_f2_wdata(57) => - \sample_f2_wdata[57]\, sample_f2_wdata(56) => - \sample_f2_wdata[56]\, sample_f2_wdata(55) => - \sample_f2_wdata[55]\, sample_f2_wdata(54) => - \sample_f2_wdata[54]\, sample_f2_wdata(53) => - \sample_f2_wdata[53]\, sample_f2_wdata(52) => - \sample_f2_wdata[52]\, sample_f2_wdata(51) => - \sample_f2_wdata[51]\, sample_f2_wdata(50) => - \sample_f2_wdata[50]\, sample_f2_wdata(49) => - \sample_f2_wdata[49]\, sample_f2_wdata(48) => - \sample_f2_wdata[48]\, sample_f2_wdata(47) => - \sample_f2_wdata[47]\, sample_f2_wdata(46) => - \sample_f2_wdata[46]\, sample_f2_wdata(45) => - \sample_f2_wdata[45]\, sample_f2_wdata(44) => - \sample_f2_wdata[44]\, sample_f2_wdata(43) => - \sample_f2_wdata[43]\, sample_f2_wdata(42) => - \sample_f2_wdata[42]\, sample_f2_wdata(41) => - \sample_f2_wdata[41]\, sample_f2_wdata(40) => - \sample_f2_wdata[40]\, sample_f2_wdata(39) => - \sample_f2_wdata[39]\, sample_f2_wdata(38) => - \sample_f2_wdata[38]\, sample_f2_wdata(37) => - \sample_f2_wdata[37]\, sample_f2_wdata(36) => - \sample_f2_wdata[36]\, sample_f2_wdata(35) => - \sample_f2_wdata[35]\, sample_f2_wdata(34) => - \sample_f2_wdata[34]\, sample_f2_wdata(33) => - \sample_f2_wdata[33]\, sample_f2_wdata(32) => - \sample_f2_wdata[32]\, sample_f2_wdata(31) => - \sample_f2_wdata[31]\, sample_f2_wdata(30) => - \sample_f2_wdata[30]\, sample_f2_wdata(29) => - \sample_f2_wdata[29]\, sample_f2_wdata(28) => - \sample_f2_wdata[28]\, sample_f2_wdata(27) => - \sample_f2_wdata[27]\, sample_f2_wdata(26) => - \sample_f2_wdata[26]\, sample_f2_wdata(25) => - \sample_f2_wdata[25]\, sample_f2_wdata(24) => - \sample_f2_wdata[24]\, sample_f2_wdata(23) => - \sample_f2_wdata[23]\, sample_f2_wdata(22) => - \sample_f2_wdata[22]\, sample_f2_wdata(21) => - \sample_f2_wdata[21]\, sample_f2_wdata(20) => - \sample_f2_wdata[20]\, sample_f2_wdata(19) => - \sample_f2_wdata[19]\, sample_f2_wdata(18) => - \sample_f2_wdata[18]\, sample_f2_wdata(17) => - \sample_f2_wdata[17]\, sample_f2_wdata(16) => - \sample_f2_wdata[16]\, sample_f2_wdata(15) => - \sample_f2_wdata[15]\, sample_f2_wdata(14) => - \sample_f2_wdata[14]\, sample_f2_wdata(13) => - \sample_f2_wdata[13]\, sample_f2_wdata(12) => - \sample_f2_wdata[12]\, sample_f2_wdata(11) => - \sample_f2_wdata[11]\, sample_f2_wdata(10) => - \sample_f2_wdata[10]\, sample_f2_wdata(9) => - \sample_f2_wdata[9]\, sample_f2_wdata(8) => - \sample_f2_wdata[8]\, sample_f2_wdata(7) => - \sample_f2_wdata[7]\, sample_f2_wdata(6) => - \sample_f2_wdata[6]\, sample_f2_wdata(5) => - \sample_f2_wdata[5]\, sample_f2_wdata(4) => - \sample_f2_wdata[4]\, sample_f2_wdata(3) => - \sample_f2_wdata[3]\, sample_f2_wdata(2) => - \sample_f2_wdata[2]\, sample_f2_wdata(1) => - \sample_f2_wdata[1]\, sample_f2_wdata(0) => - \sample_f2_wdata[0]\, sample_f1_15 => \sample_f1[63]\, - sample_f1_47 => \sample_f1[95]\, sample_f1_14 => - \sample_f1[62]\, sample_f1_46 => \sample_f1[94]\, - sample_f1_13 => \sample_f1[61]\, sample_f1_45 => - \sample_f1[93]\, sample_f1_12 => \sample_f1[60]\, - sample_f1_44 => \sample_f1[92]\, sample_f1_60 => - \sample_f1[108]\, sample_f1_59 => \sample_f1[107]\, - sample_f1_58 => \sample_f1[106]\, sample_f1_57 => - \sample_f1[105]\, sample_f1_56 => \sample_f1[104]\, - sample_f1_55 => \sample_f1[103]\, sample_f1_54 => - \sample_f1[102]\, sample_f1_53 => \sample_f1[101]\, - sample_f1_52 => \sample_f1[100]\, sample_f1_51 => - \sample_f1[99]\, sample_f1_50 => \sample_f1[98]\, - sample_f1_49 => \sample_f1[97]\, sample_f1_48 => - \sample_f1[96]\, sample_f1_4 => \sample_f1[52]\, - sample_f1_36 => \sample_f1[84]\, sample_f1_3 => - \sample_f1[51]\, sample_f1_35 => \sample_f1[83]\, - sample_f1_2 => \sample_f1[50]\, sample_f1_34 => - \sample_f1[82]\, sample_f1_1 => \sample_f1[49]\, - sample_f1_33 => \sample_f1[81]\, sample_f1_0 => - \sample_f1[48]\, sample_f1_32 => \sample_f1[80]\, - sample_f1_63 => \sample_f1[111]\, sample_f1_62 => - \sample_f1[110]\, sample_f1_61 => \sample_f1[109]\, - sample_f1_11 => \sample_f1[59]\, sample_f1_43 => - \sample_f1[91]\, sample_f1_10 => \sample_f1[58]\, - sample_f1_42 => \sample_f1[90]\, sample_f1_9 => - \sample_f1[57]\, sample_f1_41 => \sample_f1[89]\, - sample_f1_8 => \sample_f1[56]\, sample_f1_40 => - \sample_f1[88]\, sample_f1_7 => \sample_f1[55]\, - sample_f1_39 => \sample_f1[87]\, sample_f1_6 => - \sample_f1[54]\, sample_f1_38 => \sample_f1[86]\, - sample_f1_5 => \sample_f1[53]\, sample_f1_37 => - \sample_f1[85]\, sample_f1_wdata_0 => - \sample_f1_wdata[0]\, sample_f1_wdata_1 => - \sample_f1_wdata[1]\, sample_f1_wdata_2 => - \sample_f1_wdata[2]\, sample_f1_wdata_3 => - \sample_f1_wdata[3]\, sample_f1_wdata_4 => - \sample_f1_wdata[4]\, sample_f1_wdata_5 => - \sample_f1_wdata[5]\, sample_f1_wdata_6 => - \sample_f1_wdata[6]\, sample_f1_wdata_7 => - \sample_f1_wdata[7]\, sample_f1_wdata_8 => - \sample_f1_wdata[8]\, sample_f1_wdata_9 => - \sample_f1_wdata[9]\, sample_f1_wdata_10 => - \sample_f1_wdata[10]\, sample_f1_wdata_11 => - \sample_f1_wdata[11]\, sample_f1_wdata_12 => - \sample_f1_wdata[12]\, sample_f1_wdata_13 => - \sample_f1_wdata[13]\, sample_f1_wdata_14 => - \sample_f1_wdata[14]\, sample_f1_wdata_15 => - \sample_f1_wdata[15]\, sample_f1_wdata_48 => - \sample_f1_wdata[48]\, sample_f1_wdata_49 => - \sample_f1_wdata[49]\, sample_f1_wdata_50 => - \sample_f1_wdata[50]\, sample_f1_wdata_51 => - \sample_f1_wdata[51]\, sample_f1_wdata_52 => - \sample_f1_wdata[52]\, sample_f1_wdata_53 => - \sample_f1_wdata[53]\, sample_f1_wdata_54 => - \sample_f1_wdata[54]\, sample_f1_wdata_55 => - \sample_f1_wdata[55]\, sample_f1_wdata_56 => - \sample_f1_wdata[56]\, sample_f1_wdata_57 => - \sample_f1_wdata[57]\, sample_f1_wdata_58 => - \sample_f1_wdata[58]\, sample_f1_wdata_59 => - \sample_f1_wdata[59]\, sample_f1_wdata_60 => - \sample_f1_wdata[60]\, sample_f1_wdata_61 => - \sample_f1_wdata[61]\, sample_f1_wdata_62 => - \sample_f1_wdata[62]\, sample_f1_wdata_63 => - \sample_f1_wdata[63]\, sample_f1_wdata_64 => - \sample_f1_wdata[64]\, sample_f1_wdata_65 => - \sample_f1_wdata[65]\, sample_f1_wdata_66 => - \sample_f1_wdata[66]\, sample_f1_wdata_67 => - \sample_f1_wdata[67]\, sample_f1_wdata_68 => - \sample_f1_wdata[68]\, sample_f1_wdata_69 => - \sample_f1_wdata[69]\, sample_f1_wdata_70 => - \sample_f1_wdata[70]\, sample_f1_wdata_71 => - \sample_f1_wdata[71]\, sample_f1_wdata_72 => - \sample_f1_wdata[72]\, sample_f1_wdata_73 => - \sample_f1_wdata[73]\, sample_f1_wdata_74 => - \sample_f1_wdata[74]\, sample_f1_wdata_75 => - \sample_f1_wdata[75]\, sample_f1_wdata_76 => - \sample_f1_wdata[76]\, sample_f1_wdata_77 => - \sample_f1_wdata[77]\, sample_f1_wdata_78 => - \sample_f1_wdata[78]\, sample_f1_wdata_79 => - \sample_f1_wdata[79]\, sample_f1_wdata_80 => - \sample_f1_wdata[80]\, sample_f1_wdata_81 => - \sample_f1_wdata[81]\, sample_f1_wdata_82 => - \sample_f1_wdata[82]\, sample_f1_wdata_83 => - \sample_f1_wdata[83]\, sample_f1_wdata_84 => - \sample_f1_wdata[84]\, sample_f1_wdata_85 => - \sample_f1_wdata[85]\, sample_f1_wdata_86 => - \sample_f1_wdata[86]\, sample_f1_wdata_87 => - \sample_f1_wdata[87]\, sample_f1_wdata_88 => - \sample_f1_wdata[88]\, sample_f1_wdata_89 => - \sample_f1_wdata[89]\, sample_f1_wdata_90 => - \sample_f1_wdata[90]\, sample_f1_wdata_91 => - \sample_f1_wdata[91]\, sample_f1_wdata_92 => - \sample_f1_wdata[92]\, sample_f1_wdata_93 => - \sample_f1_wdata[93]\, sample_f1_wdata_94 => - \sample_f1_wdata[94]\, sample_f1_wdata_95 => - \sample_f1_wdata[95]\, sample_f0_15 => \sample_f0[63]\, - sample_f0_47 => \sample_f0[95]\, sample_f0_14 => - \sample_f0[62]\, sample_f0_46 => \sample_f0[94]\, - sample_f0_13 => \sample_f0[61]\, sample_f0_45 => - \sample_f0[93]\, sample_f0_12 => \sample_f0[60]\, - sample_f0_44 => \sample_f0[92]\, sample_f0_60 => - \sample_f0[108]\, sample_f0_59 => \sample_f0[107]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_57 => - \sample_f0[105]\, sample_f0_56 => \sample_f0[104]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_54 => - \sample_f0[102]\, sample_f0_53 => \sample_f0[101]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_51 => - \sample_f0[99]\, sample_f0_50 => \sample_f0[98]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_48 => - \sample_f0[96]\, sample_f0_4 => \sample_f0[52]\, - sample_f0_36 => \sample_f0[84]\, sample_f0_3 => - \sample_f0[51]\, sample_f0_35 => \sample_f0[83]\, - sample_f0_2 => \sample_f0[50]\, sample_f0_34 => - \sample_f0[82]\, sample_f0_1 => \sample_f0[49]\, - sample_f0_33 => \sample_f0[81]\, sample_f0_0 => - \sample_f0[48]\, sample_f0_32 => \sample_f0[80]\, - sample_f0_63 => \sample_f0[111]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_61 => \sample_f0[109]\, - sample_f0_11 => \sample_f0[59]\, sample_f0_43 => - \sample_f0[91]\, sample_f0_10 => \sample_f0[58]\, - sample_f0_42 => \sample_f0[90]\, sample_f0_9 => - \sample_f0[57]\, sample_f0_41 => \sample_f0[89]\, - sample_f0_8 => \sample_f0[56]\, sample_f0_40 => - \sample_f0[88]\, sample_f0_7 => \sample_f0[55]\, - sample_f0_39 => \sample_f0[87]\, sample_f0_6 => - \sample_f0[54]\, sample_f0_38 => \sample_f0[86]\, - sample_f0_5 => \sample_f0[53]\, sample_f0_37 => - \sample_f0[85]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, delta_f2_f1(9) => delta_f2_f1(9), - delta_f2_f1(8) => delta_f2_f1(8), delta_f2_f1(7) => - delta_f2_f1(7), delta_f2_f1(6) => delta_f2_f1(6), - delta_f2_f1(5) => delta_f2_f1(5), delta_f2_f1(4) => - delta_f2_f1(4), delta_f2_f1(3) => delta_f2_f1(3), - delta_f2_f1(2) => delta_f2_f1(2), delta_f2_f1(1) => - delta_f2_f1(1), delta_f2_f1(0) => delta_f2_f1(0), - delta_snapshot(15) => delta_snapshot(15), - delta_snapshot(14) => delta_snapshot(14), - delta_snapshot(13) => delta_snapshot(13), - delta_snapshot(12) => delta_snapshot(12), - delta_snapshot(11) => delta_snapshot(11), - delta_snapshot(10) => delta_snapshot(10), - delta_snapshot(9) => delta_snapshot(9), delta_snapshot(8) - => delta_snapshot(8), delta_snapshot(7) => - delta_snapshot(7), delta_snapshot(6) => delta_snapshot(6), - delta_snapshot(5) => delta_snapshot(5), delta_snapshot(4) - => delta_snapshot(4), delta_snapshot(3) => - delta_snapshot(3), delta_snapshot(2) => delta_snapshot(2), - delta_snapshot(1) => delta_snapshot(1), delta_snapshot(0) - => delta_snapshot(0), delta_f2_f0(9) => delta_f2_f0(9), - delta_f2_f0(8) => delta_f2_f0(8), delta_f2_f0(7) => - delta_f2_f0(7), delta_f2_f0(6) => delta_f2_f0(6), - delta_f2_f0(5) => delta_f2_f0(5), delta_f2_f0(4) => - delta_f2_f0(4), delta_f2_f0(3) => delta_f2_f0(3), - delta_f2_f0(2) => delta_f2_f0(2), delta_f2_f0(1) => - delta_f2_f0(1), delta_f2_f0(0) => delta_f2_f0(0), - nb_snapshot_param(10) => nb_snapshot_param(10), - nb_snapshot_param(9) => nb_snapshot_param(9), - nb_snapshot_param(8) => nb_snapshot_param(8), - nb_snapshot_param(7) => nb_snapshot_param(7), - nb_snapshot_param(6) => nb_snapshot_param(6), - nb_snapshot_param(5) => nb_snapshot_param(5), - nb_snapshot_param(4) => nb_snapshot_param(4), - nb_snapshot_param(3) => nb_snapshot_param(3), - nb_snapshot_param(2) => nb_snapshot_param(2), - nb_snapshot_param(1) => nb_snapshot_param(1), - nb_snapshot_param(0) => nb_snapshot_param(0), hwrite_c - => hwrite_c, IdlePhase_RNI03G71 => IdlePhase_RNI03G71, - N_43 => N_43, lpp_waveform_GND => - lpp_top_lfr_wf_picker_ip_GND, lpp_waveform_VCC => - lpp_top_lfr_wf_picker_ip_VCC, sample_f3_val => - sample_f3_val, enable_f3 => enable_f3, burst_f2 => - burst_f2, enable_f2 => enable_f2, sample_f1_val_0 => - sample_f1_val_0, burst_f1 => burst_f1, enable_f1 => - enable_f1, data_shaping_R1_0 => data_shaping_R1_0, - data_shaping_R1 => data_shaping_R1, burst_f0 => burst_f0, - data_shaping_R0_0 => data_shaping_R0_0, data_shaping_R0 - => data_shaping_R0, enable_f0 => enable_f0, - coarse_time_0_c => coarse_time_0_c, sample_f2_val => - sample_f2_val, sample_f0_val_0 => sample_f0_val_0, HCLK_c - => HCLK_c, HRESETn_c => HRESETn_c); - - Downsampling_f0 : Downsampling_8_16_4 - port map(sample_f0_0 => \sample_f0[48]\, sample_f0_1 => - \sample_f0[49]\, sample_f0_2 => \sample_f0[50]\, - sample_f0_3 => \sample_f0[51]\, sample_f0_4 => - \sample_f0[52]\, sample_f0_5 => \sample_f0[53]\, - sample_f0_6 => \sample_f0[54]\, sample_f0_7 => - \sample_f0[55]\, sample_f0_8 => \sample_f0[56]\, - sample_f0_9 => \sample_f0[57]\, sample_f0_10 => - \sample_f0[58]\, sample_f0_11 => \sample_f0[59]\, - sample_f0_12 => \sample_f0[60]\, sample_f0_13 => - \sample_f0[61]\, sample_f0_14 => \sample_f0[62]\, - sample_f0_15 => \sample_f0[63]\, sample_f0_32 => - \sample_f0[80]\, sample_f0_33 => \sample_f0[81]\, - sample_f0_34 => \sample_f0[82]\, sample_f0_35 => - \sample_f0[83]\, sample_f0_36 => \sample_f0[84]\, - sample_f0_37 => \sample_f0[85]\, sample_f0_38 => - \sample_f0[86]\, sample_f0_39 => \sample_f0[87]\, - sample_f0_40 => \sample_f0[88]\, sample_f0_41 => - \sample_f0[89]\, sample_f0_42 => \sample_f0[90]\, - sample_f0_43 => \sample_f0[91]\, sample_f0_44 => - \sample_f0[92]\, sample_f0_45 => \sample_f0[93]\, - sample_f0_46 => \sample_f0[94]\, sample_f0_47 => - \sample_f0[95]\, sample_f0_48 => \sample_f0[96]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_50 => - \sample_f0[98]\, sample_f0_51 => \sample_f0[99]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_53 => - \sample_f0[101]\, sample_f0_54 => \sample_f0[102]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_56 => - \sample_f0[104]\, sample_f0_57 => \sample_f0[105]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_59 => - \sample_f0[107]\, sample_f0_60 => \sample_f0[108]\, - sample_f0_61 => \sample_f0[109]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_63 => \sample_f0[111]\, - sample_data_shaping_out_0 => \sample_data_shaping_out[2]\, - sample_data_shaping_out_1 => \sample_data_shaping_out[3]\, - sample_data_shaping_out_2 => \sample_data_shaping_out[4]\, - sample_data_shaping_out_3 => \sample_data_shaping_out[5]\, - sample_data_shaping_out_4 => \sample_data_shaping_out[6]\, - sample_data_shaping_out_5 => \sample_data_shaping_out[7]\, - sample_data_shaping_out_6 => \sample_data_shaping_out[8]\, - sample_data_shaping_out_7 => \sample_data_shaping_out[9]\, - sample_data_shaping_out_8 => - \sample_data_shaping_out[10]\, sample_data_shaping_out_9 - => \sample_data_shaping_out[11]\, - sample_data_shaping_out_10 => - \sample_data_shaping_out[12]\, sample_data_shaping_out_11 - => \sample_data_shaping_out[13]\, - sample_data_shaping_out_12 => - \sample_data_shaping_out[14]\, sample_data_shaping_out_13 - => \sample_data_shaping_out[15]\, - sample_data_shaping_out_14 => - \sample_data_shaping_out[16]\, sample_data_shaping_out_15 - => \sample_data_shaping_out[17]\, - sample_data_shaping_out_18 => - \sample_data_shaping_out[20]\, sample_data_shaping_out_19 - => \sample_data_shaping_out[21]\, - sample_data_shaping_out_20 => - \sample_data_shaping_out[22]\, sample_data_shaping_out_21 - => \sample_data_shaping_out[23]\, - sample_data_shaping_out_22 => - \sample_data_shaping_out[24]\, sample_data_shaping_out_23 - => \sample_data_shaping_out[25]\, - sample_data_shaping_out_24 => - \sample_data_shaping_out[26]\, sample_data_shaping_out_25 - => \sample_data_shaping_out[27]\, - sample_data_shaping_out_26 => - \sample_data_shaping_out[28]\, sample_data_shaping_out_27 - => \sample_data_shaping_out[29]\, - sample_data_shaping_out_28 => - \sample_data_shaping_out[30]\, sample_data_shaping_out_29 - => \sample_data_shaping_out[31]\, - sample_data_shaping_out_30 => - \sample_data_shaping_out[32]\, sample_data_shaping_out_31 - => \sample_data_shaping_out[33]\, - sample_data_shaping_out_32 => - \sample_data_shaping_out[34]\, sample_data_shaping_out_33 - => \sample_data_shaping_out[35]\, - sample_data_shaping_out_36 => - \sample_data_shaping_out[38]\, sample_data_shaping_out_37 - => \sample_data_shaping_out[39]\, - sample_data_shaping_out_38 => - \sample_data_shaping_out[40]\, sample_data_shaping_out_39 - => \sample_data_shaping_out[41]\, - sample_data_shaping_out_40 => - \sample_data_shaping_out[42]\, sample_data_shaping_out_41 - => \sample_data_shaping_out[43]\, - sample_data_shaping_out_42 => - \sample_data_shaping_out[44]\, sample_data_shaping_out_43 - => \sample_data_shaping_out[45]\, - sample_data_shaping_out_44 => - \sample_data_shaping_out[46]\, sample_data_shaping_out_45 - => \sample_data_shaping_out[47]\, - sample_data_shaping_out_46 => - \sample_data_shaping_out[48]\, sample_data_shaping_out_47 - => \sample_data_shaping_out[49]\, - sample_data_shaping_out_48 => - \sample_data_shaping_out[50]\, sample_data_shaping_out_49 - => \sample_data_shaping_out[51]\, - sample_data_shaping_out_50 => - \sample_data_shaping_out[52]\, sample_data_shaping_out_51 - => \sample_data_shaping_out[53]\, - sample_data_shaping_out_54 => - \sample_data_shaping_out[56]\, sample_data_shaping_out_55 - => \sample_data_shaping_out[57]\, - sample_data_shaping_out_56 => - \sample_data_shaping_out[58]\, sample_data_shaping_out_57 - => \sample_data_shaping_out[59]\, - sample_data_shaping_out_58 => - \sample_data_shaping_out[60]\, sample_data_shaping_out_59 - => \sample_data_shaping_out[61]\, - sample_data_shaping_out_60 => - \sample_data_shaping_out[62]\, sample_data_shaping_out_61 - => \sample_data_shaping_out[63]\, - sample_data_shaping_out_62 => - \sample_data_shaping_out[64]\, sample_data_shaping_out_63 - => \sample_data_shaping_out[65]\, - sample_data_shaping_out_64 => - \sample_data_shaping_out[66]\, sample_data_shaping_out_65 - => \sample_data_shaping_out[67]\, - sample_data_shaping_out_66 => - \sample_data_shaping_out[68]\, sample_data_shaping_out_67 - => \sample_data_shaping_out[69]\, - sample_data_shaping_out_68 => - \sample_data_shaping_out[70]\, sample_data_shaping_out_69 - => \sample_data_shaping_out[71]\, - sample_data_shaping_out_90 => - \sample_data_shaping_out[92]\, sample_data_shaping_out_91 - => \sample_data_shaping_out[93]\, - sample_data_shaping_out_92 => - \sample_data_shaping_out[94]\, sample_data_shaping_out_93 - => \sample_data_shaping_out[95]\, - sample_data_shaping_out_94 => - \sample_data_shaping_out[96]\, sample_data_shaping_out_95 - => \sample_data_shaping_out[97]\, - sample_data_shaping_out_96 => - \sample_data_shaping_out[98]\, sample_data_shaping_out_97 - => \sample_data_shaping_out[99]\, - sample_data_shaping_out_98 => - \sample_data_shaping_out[100]\, - sample_data_shaping_out_99 => - \sample_data_shaping_out[101]\, - sample_data_shaping_out_100 => - \sample_data_shaping_out[102]\, - sample_data_shaping_out_101 => - \sample_data_shaping_out[103]\, - sample_data_shaping_out_102 => - \sample_data_shaping_out[104]\, - sample_data_shaping_out_103 => - \sample_data_shaping_out[105]\, - sample_data_shaping_out_104 => - \sample_data_shaping_out[106]\, - sample_data_shaping_out_105 => - \sample_data_shaping_out[107]\, - sample_data_shaping_out_108 => - \sample_data_shaping_out[110]\, - sample_data_shaping_out_109 => - \sample_data_shaping_out[111]\, - sample_data_shaping_out_110 => - \sample_data_shaping_out[112]\, - sample_data_shaping_out_111 => - \sample_data_shaping_out[113]\, - sample_data_shaping_out_112 => - \sample_data_shaping_out[114]\, - sample_data_shaping_out_113 => - \sample_data_shaping_out[115]\, - sample_data_shaping_out_114 => - \sample_data_shaping_out[116]\, - sample_data_shaping_out_115 => - \sample_data_shaping_out[117]\, - sample_data_shaping_out_116 => - \sample_data_shaping_out[118]\, - sample_data_shaping_out_117 => - \sample_data_shaping_out[119]\, - sample_data_shaping_out_118 => - \sample_data_shaping_out[120]\, - sample_data_shaping_out_119 => - \sample_data_shaping_out[121]\, - sample_data_shaping_out_120 => - \sample_data_shaping_out[122]\, - sample_data_shaping_out_121 => - \sample_data_shaping_out[123]\, - sample_data_shaping_out_122 => - \sample_data_shaping_out[124]\, - sample_data_shaping_out_123 => - \sample_data_shaping_out[125]\, - sample_data_shaping_out_126 => - \sample_data_shaping_out[128]\, - sample_data_shaping_out_127 => - \sample_data_shaping_out[129]\, - sample_data_shaping_out_128 => - \sample_data_shaping_out[130]\, - sample_data_shaping_out_129 => - \sample_data_shaping_out[131]\, - sample_data_shaping_out_130 => - \sample_data_shaping_out[132]\, - sample_data_shaping_out_131 => - \sample_data_shaping_out[133]\, - sample_data_shaping_out_132 => - \sample_data_shaping_out[134]\, - sample_data_shaping_out_133 => - \sample_data_shaping_out[135]\, - sample_data_shaping_out_134 => - \sample_data_shaping_out[136]\, - sample_data_shaping_out_135 => - \sample_data_shaping_out[137]\, - sample_data_shaping_out_136 => - \sample_data_shaping_out[138]\, - sample_data_shaping_out_137 => - \sample_data_shaping_out[139]\, - sample_data_shaping_out_138 => - \sample_data_shaping_out[140]\, - sample_data_shaping_out_139 => - \sample_data_shaping_out[141]\, - sample_data_shaping_out_140 => - \sample_data_shaping_out[142]\, - sample_data_shaping_out_141 => - \sample_data_shaping_out[143]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_data_shaping_out_val => - \sample_data_shaping_out_val\, sample_f0_val => - sample_f0_val, sample_data_shaping_out_val_0 => - \sample_data_shaping_out_val_0\, sample_f0_val_0 => - sample_f0_val_0, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, - sample_f0_val_1 => sample_f0_val_1); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[51]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[51]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[51]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[141]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[141]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[141]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I95_Y_0 : - AX1D - port map(A => I92_un1_Y, B => N182_0, C => N183, Y => - \sample_data_shaping_f1_f0_s[2]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I37_Y : - XA1A - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[133]\, C => N197, Y => N216); - - \SampleLoop_data_shaping.1.sample_data_shaping_out_RNO[106]\ : - MX2 - port map(A => \sample_filter_v2_out[106]\, B => - \sample_data_shaping_f2_f1_s[1]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_41[106]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I49_Y : - AO1B - port map(A => N264_0, B => N216_0, C => - SUB_16x16_medium_area_I49_Y_0, Y => N244); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_0 : - AO18 - port map(A => N206_0, B => \sample_filter_v2_out[129]\, C - => \sample_filter_v2_out[111]\, Y => - SUB_16x16_medium_area_I57_Y_0_0); - - sample_data_shaping_out_val : DFN1C0 - port map(D => sample_filter_v2_out_val, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out_val\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out_RNO[125]\ : - AX1C - port map(A => \sample_filter_v2_out[143]\, B => - data_shaping_SP0, C => \sample_filter_v2_out[125]\, Y => - \sample_data_shaping_out_13[125]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I103_Y_0 : - AX1D - port map(A => I88_un1_Y, B => N198, C => N199, Y => - \sample_data_shaping_f2_f1_s[10]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I23_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, Y => N194); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[106]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_41[106]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[106]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[118]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_181[118]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[118]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I99_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[101]\, B => - \sample_filter_v2_out[119]\, C => N290_i, Y => - \sample_data_shaping_f2_f1_s[6]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[102]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_137[102]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[102]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I90_un1_Y : - OA1 - port map(A => I85_un1_Y, B => N274_0, C => N189, Y => - I90_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I46_Y : - OR2A - port map(A => \sample_filter_v2_out[125]\, B => - \sample_filter_v2_out[107]\, Y => N225); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[4]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[4]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[4]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[125]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_13[125]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[125]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I99_Y_0 : - AX1D - port map(A => I90_un1_Y, B => N190_0, C => N191, Y => - \sample_data_shaping_f1_f0_s[6]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I29_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[130]\, B => - \sample_filter_v2_out[112]\, Y => N205); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[6]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[6]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[6]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[69]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[69]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[69]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[25]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[25]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[25]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[121]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_109[121]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[121]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I90_Y : - AO18 - port map(A => N280, B => \sample_filter_v2_out[120]\, C => - \sample_filter_v2_out[102]\, Y => N290_i); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[94]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_329[94]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[94]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_1 : - OA1 - port map(A => N212_0, B => N254_0, C => - SUB_16x16_medium_area_I57_Y_0_0, Y => - SUB_16x16_medium_area_I57_Y_1_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I39_Y : - NOR2B - port map(A => N195_0, B => N193, Y => N265_0); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[53]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[53]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[53]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_0 : - AO18 - port map(A => N206, B => \sample_filter_v2_out[111]\, C => - \sample_filter_v2_out[93]\, Y => - SUB_16x16_medium_area_I57_Y_0); - - \SampleLoop_data_shaping.1.sample_data_shaping_out_RNO[124]\ : - MX2 - port map(A => \sample_filter_v2_out[124]\, B => - \sample_data_shaping_f1_f0_s[1]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_37[124]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I108_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_filter_v2_out[92]\, C => N240_0, Y => - \sample_data_shaping_f2_f1_s[15]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I94_Y_0 : - XOR2 - port map(A => N225, B => N181_0, Y => - \sample_data_shaping_f2_f1_s[1]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I29_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[112]\, B => - \sample_filter_v2_out[130]\, Y => N206_0); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[99]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_209[99]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[99]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I88_Y : - AO18 - port map(A => N270, B => \sample_filter_v2_out[134]\, C => - \sample_filter_v2_out[116]\, Y => N286_i); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[116]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_229[116]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[116]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I50_Y : - NOR2B - port map(A => N265, B => N216, Y => N245_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I24_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[117]\, B => - \sample_filter_v2_out[99]\, Y => N195_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I18_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[141]\, B => - \sample_filter_v2_out[123]\, Y => N183); - - \SampleLoop_data_shaping.6.sample_data_shaping_out_RNO[119]\ : - MX2 - port map(A => \sample_filter_v2_out[119]\, B => - \sample_data_shaping_f1_f0_s[6]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_157[119]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[139]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[139]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[139]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[70]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[70]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[70]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I27_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[114]\, B => - \sample_filter_v2_out[96]\, Y => N201_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[8]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[8]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[8]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[112]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_325[112]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[112]\); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[98]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_233[98]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[98]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[128]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[128]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[128]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y_0 : - AO18 - port map(A => N190, B => \sample_filter_v2_out[119]\, C => - \sample_filter_v2_out[101]\, Y => - SUB_16x16_medium_area_I56_Y_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[134]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[134]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[134]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I25_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[116]\, B => - \sample_filter_v2_out[98]\, Y => N197_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I29_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[112]\, B => - \sample_filter_v2_out[94]\, Y => N205_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I64_Y : - AO1 - port map(A => N268, B => N245_0, C => N244_0, Y => N258); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y : - AO1B - port map(A => SUB_16x16_medium_area_I57_un1_Y_0_0, B => - N268, C => SUB_16x16_medium_area_I57_Y_2_0, Y => N240); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[59]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[59]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[59]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I34_Y : - AO13 - port map(A => N202_0, B => \sample_filter_v2_out[95]\, C - => \sample_filter_v2_out[113]\, Y => N254); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[10]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[10]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[10]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I96_Y_0 : - XOR2 - port map(A => N278, B => N185, Y => - \sample_data_shaping_f1_f0_s[3]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I21_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[120]\, B => - \sample_filter_v2_out[138]\, Y => N190_0); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[40]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[40]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[40]\); - - Downsampling_f1 : Downsampling_8_16_6 - port map(sample_f0_0 => \sample_f0[48]\, sample_f0_1 => - \sample_f0[49]\, sample_f0_2 => \sample_f0[50]\, - sample_f0_3 => \sample_f0[51]\, sample_f0_4 => - \sample_f0[52]\, sample_f0_5 => \sample_f0[53]\, - sample_f0_6 => \sample_f0[54]\, sample_f0_7 => - \sample_f0[55]\, sample_f0_8 => \sample_f0[56]\, - sample_f0_9 => \sample_f0[57]\, sample_f0_10 => - \sample_f0[58]\, sample_f0_11 => \sample_f0[59]\, - sample_f0_12 => \sample_f0[60]\, sample_f0_13 => - \sample_f0[61]\, sample_f0_14 => \sample_f0[62]\, - sample_f0_15 => \sample_f0[63]\, sample_f0_32 => - \sample_f0[80]\, sample_f0_33 => \sample_f0[81]\, - sample_f0_34 => \sample_f0[82]\, sample_f0_35 => - \sample_f0[83]\, sample_f0_36 => \sample_f0[84]\, - sample_f0_37 => \sample_f0[85]\, sample_f0_38 => - \sample_f0[86]\, sample_f0_39 => \sample_f0[87]\, - sample_f0_40 => \sample_f0[88]\, sample_f0_41 => - \sample_f0[89]\, sample_f0_42 => \sample_f0[90]\, - sample_f0_43 => \sample_f0[91]\, sample_f0_44 => - \sample_f0[92]\, sample_f0_45 => \sample_f0[93]\, - sample_f0_46 => \sample_f0[94]\, sample_f0_47 => - \sample_f0[95]\, sample_f0_48 => \sample_f0[96]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_50 => - \sample_f0[98]\, sample_f0_51 => \sample_f0[99]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_53 => - \sample_f0[101]\, sample_f0_54 => \sample_f0[102]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_56 => - \sample_f0[104]\, sample_f0_57 => \sample_f0[105]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_59 => - \sample_f0[107]\, sample_f0_60 => \sample_f0[108]\, - sample_f0_61 => \sample_f0[109]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_63 => \sample_f0[111]\, - sample_f1_0 => \sample_f1[48]\, sample_f1_1 => - \sample_f1[49]\, sample_f1_2 => \sample_f1[50]\, - sample_f1_3 => \sample_f1[51]\, sample_f1_4 => - \sample_f1[52]\, sample_f1_5 => \sample_f1[53]\, - sample_f1_6 => \sample_f1[54]\, sample_f1_7 => - \sample_f1[55]\, sample_f1_8 => \sample_f1[56]\, - sample_f1_9 => \sample_f1[57]\, sample_f1_10 => - \sample_f1[58]\, sample_f1_11 => \sample_f1[59]\, - sample_f1_12 => \sample_f1[60]\, sample_f1_13 => - \sample_f1[61]\, sample_f1_14 => \sample_f1[62]\, - sample_f1_15 => \sample_f1[63]\, sample_f1_32 => - \sample_f1[80]\, sample_f1_33 => \sample_f1[81]\, - sample_f1_34 => \sample_f1[82]\, sample_f1_35 => - \sample_f1[83]\, sample_f1_36 => \sample_f1[84]\, - sample_f1_37 => \sample_f1[85]\, sample_f1_38 => - \sample_f1[86]\, sample_f1_39 => \sample_f1[87]\, - sample_f1_40 => \sample_f1[88]\, sample_f1_41 => - \sample_f1[89]\, sample_f1_42 => \sample_f1[90]\, - sample_f1_43 => \sample_f1[91]\, sample_f1_44 => - \sample_f1[92]\, sample_f1_45 => \sample_f1[93]\, - sample_f1_46 => \sample_f1[94]\, sample_f1_47 => - \sample_f1[95]\, sample_f1_48 => \sample_f1[96]\, - sample_f1_49 => \sample_f1[97]\, sample_f1_50 => - \sample_f1[98]\, sample_f1_51 => \sample_f1[99]\, - sample_f1_52 => \sample_f1[100]\, sample_f1_53 => - \sample_f1[101]\, sample_f1_54 => \sample_f1[102]\, - sample_f1_55 => \sample_f1[103]\, sample_f1_56 => - \sample_f1[104]\, sample_f1_57 => \sample_f1[105]\, - sample_f1_58 => \sample_f1[106]\, sample_f1_59 => - \sample_f1[107]\, sample_f1_60 => \sample_f1[108]\, - sample_f1_61 => \sample_f1[109]\, sample_f1_62 => - \sample_f1[110]\, sample_f1_63 => \sample_f1[111]\, - sample_f0_wdata_95 => \sample_f0_wdata[95]\, - sample_f0_wdata_94 => \sample_f0_wdata[94]\, - sample_f0_wdata_93 => \sample_f0_wdata[93]\, - sample_f0_wdata_92 => \sample_f0_wdata[92]\, - sample_f0_wdata_91 => \sample_f0_wdata[91]\, - sample_f0_wdata_90 => \sample_f0_wdata[90]\, - sample_f0_wdata_89 => \sample_f0_wdata[89]\, - sample_f0_wdata_88 => \sample_f0_wdata[88]\, - sample_f0_wdata_87 => \sample_f0_wdata[87]\, - sample_f0_wdata_86 => \sample_f0_wdata[86]\, - sample_f0_wdata_85 => \sample_f0_wdata[85]\, - sample_f0_wdata_84 => \sample_f0_wdata[84]\, - sample_f0_wdata_83 => \sample_f0_wdata[83]\, - sample_f0_wdata_82 => \sample_f0_wdata[82]\, - sample_f0_wdata_81 => \sample_f0_wdata[81]\, - sample_f0_wdata_80 => \sample_f0_wdata[80]\, - sample_f0_wdata_79 => \sample_f0_wdata[79]\, - sample_f0_wdata_78 => \sample_f0_wdata[78]\, - sample_f0_wdata_77 => \sample_f0_wdata[77]\, - sample_f0_wdata_76 => \sample_f0_wdata[76]\, - sample_f0_wdata_75 => \sample_f0_wdata[75]\, - sample_f0_wdata_74 => \sample_f0_wdata[74]\, - sample_f0_wdata_73 => \sample_f0_wdata[73]\, - sample_f0_wdata_72 => \sample_f0_wdata[72]\, - sample_f0_wdata_71 => \sample_f0_wdata[71]\, - sample_f0_wdata_70 => \sample_f0_wdata[70]\, - sample_f0_wdata_69 => \sample_f0_wdata[69]\, - sample_f0_wdata_68 => \sample_f0_wdata[68]\, - sample_f0_wdata_67 => \sample_f0_wdata[67]\, - sample_f0_wdata_66 => \sample_f0_wdata[66]\, - sample_f0_wdata_65 => \sample_f0_wdata[65]\, - sample_f0_wdata_64 => \sample_f0_wdata[64]\, - sample_f0_wdata_63 => \sample_f0_wdata[63]\, - sample_f0_wdata_62 => \sample_f0_wdata[62]\, - sample_f0_wdata_61 => \sample_f0_wdata[61]\, - sample_f0_wdata_60 => \sample_f0_wdata[60]\, - sample_f0_wdata_59 => \sample_f0_wdata[59]\, - sample_f0_wdata_58 => \sample_f0_wdata[58]\, - sample_f0_wdata_57 => \sample_f0_wdata[57]\, - sample_f0_wdata_56 => \sample_f0_wdata[56]\, - sample_f0_wdata_55 => \sample_f0_wdata[55]\, - sample_f0_wdata_54 => \sample_f0_wdata[54]\, - sample_f0_wdata_53 => \sample_f0_wdata[53]\, - sample_f0_wdata_52 => \sample_f0_wdata[52]\, - sample_f0_wdata_51 => \sample_f0_wdata[51]\, - sample_f0_wdata_50 => \sample_f0_wdata[50]\, - sample_f0_wdata_49 => \sample_f0_wdata[49]\, - sample_f0_wdata_48 => \sample_f0_wdata[48]\, - sample_f0_wdata_15 => \sample_f0_wdata[15]\, - sample_f0_wdata_14 => \sample_f0_wdata[14]\, - sample_f0_wdata_13 => \sample_f0_wdata[13]\, - sample_f0_wdata_12 => \sample_f0_wdata[12]\, - sample_f0_wdata_11 => \sample_f0_wdata[11]\, - sample_f0_wdata_10 => \sample_f0_wdata[10]\, - sample_f0_wdata_9 => \sample_f0_wdata[9]\, - sample_f0_wdata_8 => \sample_f0_wdata[8]\, - sample_f0_wdata_7 => \sample_f0_wdata[7]\, - sample_f0_wdata_6 => \sample_f0_wdata[6]\, - sample_f0_wdata_5 => \sample_f0_wdata[5]\, - sample_f0_wdata_4 => \sample_f0_wdata[4]\, - sample_f0_wdata_3 => \sample_f0_wdata[3]\, - sample_f0_wdata_2 => \sample_f0_wdata[2]\, - sample_f0_wdata_1 => \sample_f0_wdata[1]\, - sample_f0_wdata_0 => \sample_f0_wdata[0]\, - sample_f1_wdata_95 => \sample_f1_wdata[95]\, - sample_f1_wdata_94 => \sample_f1_wdata[94]\, - sample_f1_wdata_93 => \sample_f1_wdata[93]\, - sample_f1_wdata_92 => \sample_f1_wdata[92]\, - sample_f1_wdata_91 => \sample_f1_wdata[91]\, - sample_f1_wdata_90 => \sample_f1_wdata[90]\, - sample_f1_wdata_89 => \sample_f1_wdata[89]\, - sample_f1_wdata_88 => \sample_f1_wdata[88]\, - sample_f1_wdata_87 => \sample_f1_wdata[87]\, - sample_f1_wdata_86 => \sample_f1_wdata[86]\, - sample_f1_wdata_85 => \sample_f1_wdata[85]\, - sample_f1_wdata_84 => \sample_f1_wdata[84]\, - sample_f1_wdata_83 => \sample_f1_wdata[83]\, - sample_f1_wdata_82 => \sample_f1_wdata[82]\, - sample_f1_wdata_81 => \sample_f1_wdata[81]\, - sample_f1_wdata_80 => \sample_f1_wdata[80]\, - sample_f1_wdata_79 => \sample_f1_wdata[79]\, - sample_f1_wdata_78 => \sample_f1_wdata[78]\, - sample_f1_wdata_77 => \sample_f1_wdata[77]\, - sample_f1_wdata_76 => \sample_f1_wdata[76]\, - sample_f1_wdata_75 => \sample_f1_wdata[75]\, - sample_f1_wdata_74 => \sample_f1_wdata[74]\, - sample_f1_wdata_73 => \sample_f1_wdata[73]\, - sample_f1_wdata_72 => \sample_f1_wdata[72]\, - sample_f1_wdata_71 => \sample_f1_wdata[71]\, - sample_f1_wdata_70 => \sample_f1_wdata[70]\, - sample_f1_wdata_69 => \sample_f1_wdata[69]\, - sample_f1_wdata_68 => \sample_f1_wdata[68]\, - sample_f1_wdata_67 => \sample_f1_wdata[67]\, - sample_f1_wdata_66 => \sample_f1_wdata[66]\, - sample_f1_wdata_65 => \sample_f1_wdata[65]\, - sample_f1_wdata_64 => \sample_f1_wdata[64]\, - sample_f1_wdata_63 => \sample_f1_wdata[63]\, - sample_f1_wdata_62 => \sample_f1_wdata[62]\, - sample_f1_wdata_61 => \sample_f1_wdata[61]\, - sample_f1_wdata_60 => \sample_f1_wdata[60]\, - sample_f1_wdata_59 => \sample_f1_wdata[59]\, - sample_f1_wdata_58 => \sample_f1_wdata[58]\, - sample_f1_wdata_57 => \sample_f1_wdata[57]\, - sample_f1_wdata_56 => \sample_f1_wdata[56]\, - sample_f1_wdata_55 => \sample_f1_wdata[55]\, - sample_f1_wdata_54 => \sample_f1_wdata[54]\, - sample_f1_wdata_53 => \sample_f1_wdata[53]\, - sample_f1_wdata_52 => \sample_f1_wdata[52]\, - sample_f1_wdata_51 => \sample_f1_wdata[51]\, - sample_f1_wdata_50 => \sample_f1_wdata[50]\, - sample_f1_wdata_49 => \sample_f1_wdata[49]\, - sample_f1_wdata_48 => \sample_f1_wdata[48]\, - sample_f1_wdata_15 => \sample_f1_wdata[15]\, - sample_f1_wdata_14 => \sample_f1_wdata[14]\, - sample_f1_wdata_13 => \sample_f1_wdata[13]\, - sample_f1_wdata_12 => \sample_f1_wdata[12]\, - sample_f1_wdata_11 => \sample_f1_wdata[11]\, - sample_f1_wdata_10 => \sample_f1_wdata[10]\, - sample_f1_wdata_9 => \sample_f1_wdata[9]\, - sample_f1_wdata_8 => \sample_f1_wdata[8]\, - sample_f1_wdata_7 => \sample_f1_wdata[7]\, - sample_f1_wdata_6 => \sample_f1_wdata[6]\, - sample_f1_wdata_5 => \sample_f1_wdata[5]\, - sample_f1_wdata_4 => \sample_f1_wdata[4]\, - sample_f1_wdata_3 => \sample_f1_wdata[3]\, - sample_f1_wdata_2 => \sample_f1_wdata[2]\, - sample_f1_wdata_1 => \sample_f1_wdata[1]\, - sample_f1_wdata_0 => \sample_f1_wdata[0]\, - sample_f0_val_1 => sample_f0_val_1, sample_f1_val => - sample_f1_val, sample_f0_val_0 => sample_f0_val_0, - sample_out_0_sqmuxa_1 => sample_out_0_sqmuxa_1, HRESETn_c - => HRESETn_c, HCLK_c => HCLK_c, sample_f1_val_0 => - sample_f1_val_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out_RNO[100]\ : - MX2 - port map(A => \sample_filter_v2_out[100]\, B => - \sample_data_shaping_f2_f1_s[7]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_185[100]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I49_Y : - AO1B - port map(A => N264, B => N216, C => - SUB_16x16_medium_area_I49_Y_0_0, Y => N244_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I23_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[100]\, Y => N193); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I41_Y : - XA1A - port map(A => \sample_filter_v2_out[101]\, B => - \sample_filter_v2_out[119]\, C => N189_0, Y => N220); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y : - AO1B - port map(A => SUB_16x16_medium_area_I57_un1_Y_0, B => - N268_0, C => SUB_16x16_medium_area_I57_Y_2, Y => N240_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I17_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[142]\, B => - \sample_filter_v2_out[124]\, Y => N181); - - \SampleLoop_data_shaping.9.sample_data_shaping_out_RNO[98]\ : - MX2 - port map(A => \sample_filter_v2_out[98]\, B => - \sample_data_shaping_f2_f1_s[9]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_233[98]\); - - sample_data_shaping_out_val_0 : DFN1C0 - port map(D => sample_filter_v2_out_val, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out_val_0\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I38_Y : - AO13 - port map(A => N194, B => \sample_filter_v2_out[117]\, C => - \sample_filter_v2_out[135]\, Y => N264); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[41]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[41]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[41]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[140]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[140]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[140]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out_RNO[105]\ : - MX2 - port map(A => \sample_filter_v2_out[105]\, B => - \sample_data_shaping_f2_f1_s[2]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_65[105]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_1 : - AOI1B - port map(A => N254, B => N212, C => - SUB_16x16_medium_area_I57_Y_0, Y => - SUB_16x16_medium_area_I57_Y_1); - - \SampleLoop_data_shaping.5.sample_data_shaping_out_RNO[102]\ : - MX2 - port map(A => \sample_filter_v2_out[102]\, B => - \sample_data_shaping_f2_f1_s[5]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_137[102]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_2 : - AOI1B - port map(A => N244_0, B => N229_0, C => - SUB_16x16_medium_area_I57_Y_1_0, Y => - SUB_16x16_medium_area_I57_Y_2_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[39]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[39]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[39]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[130]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[130]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[130]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I97_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I91_un1_Y_0, B => - N186_0, C => N187_0, Y => - \sample_data_shaping_f2_f1_s[4]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I21_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[120]\, B => - \sample_filter_v2_out[102]\, Y => N189_0); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[63]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[63]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[63]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[101]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_161[101]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[101]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I106_Y_0 : - XOR2 - port map(A => N260, B => N205, Y => - \sample_data_shaping_f1_f0_s[13]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[45]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[45]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[45]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[123]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_61[123]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[123]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[24]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[24]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[24]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out_RNO[122]\ : - MX2 - port map(A => \sample_filter_v2_out[122]\, B => - \sample_data_shaping_f1_f0_s[3]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_85[122]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[115]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_253[115]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[115]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[43]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[43]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[43]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I78_un1_Y : - NOR2B - port map(A => N268_0, B => N265_0, Y => I78_un1_Y); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[60]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[60]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[60]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I42_Y : - AO13 - port map(A => N186, B => \sample_filter_v2_out[121]\, C => - \sample_filter_v2_out[139]\, Y => N274_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[64]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[64]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[64]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[133]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[133]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[133]\); - - GND_i_0 : GND - port map(Y => GND_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_2 : - AOI1B - port map(A => N244, B => N229, C => - SUB_16x16_medium_area_I57_Y_1, Y => - SUB_16x16_medium_area_I57_Y_2); - - \SampleLoop_data_shaping.4.sample_data_shaping_out_RNO[121]\ : - MX2 - port map(A => \sample_filter_v2_out[121]\, B => - \sample_data_shaping_f1_f0_s[4]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_109[121]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[142]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[142]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[142]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I96_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, C => N278_0, Y => - \sample_data_shaping_f2_f1_s[3]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_un1_Y : - OR3C - port map(A => N225_0, B => N183, C => N181, Y => I53_un1_Y); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[14]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[14]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[14]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out_RNO[99]\ : - MX2 - port map(A => \sample_filter_v2_out[99]\, B => - \sample_data_shaping_f2_f1_s[8]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_209[99]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I101_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I89_un1_Y, B => N194_0, - C => N195_0, Y => \sample_data_shaping_f2_f1_s[8]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out_RNO[118]\ : - MX2 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_data_shaping_f1_f0_s[7]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_181[118]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I103_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[133]\, C => N286_i, Y => - \sample_data_shaping_f1_f0_s[10]\); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[93]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_353[93]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[93]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I92_un1_Y : - NOR2B - port map(A => N225_0, B => N181, Y => I92_un1_Y); - - \SampleLoop_data_shaping.8.sample_data_shaping_out_RNO[117]\ : - MX2 - port map(A => \sample_filter_v2_out[117]\, B => - \sample_data_shaping_f1_f0_s[8]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_205[117]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out_RNO[112]\ : - MX2 - port map(A => \sample_filter_v2_out[112]\, B => - \sample_data_shaping_f1_f0_s[13]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_325[112]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_Y_0 : - AO18 - port map(A => N182, B => \sample_filter_v2_out[123]\, C => - \sample_filter_v2_out[105]\, Y => - SUB_16x16_medium_area_I53_Y_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[114]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_277[114]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[114]\); - - DIGITAL_acquisition : AD7688_drvr - port map(sample_7(15) => \sample_7[15]\, sample_7(14) => - \sample_7[14]\, sample_7(13) => \sample_7[13]\, - sample_7(12) => \sample_7[12]\, sample_7(11) => - \sample_7[11]\, sample_7(10) => \sample_7[10]\, - sample_7(9) => \sample_7[9]\, sample_7(8) => - \sample_7[8]\, sample_7(7) => \sample_7[7]\, sample_7(6) - => \sample_7[6]\, sample_7(5) => \sample_7[5]\, - sample_7(4) => \sample_7[4]\, sample_7(3) => - \sample_7[3]\, sample_7(2) => \sample_7[2]\, sample_7(1) - => \sample_7[1]\, sample_7(0) => \sample_7[0]\, - sample_0(15) => \sample_0[15]\, sample_0(14) => - \sample_0[14]\, sample_0(13) => \sample_0[13]\, - sample_0(12) => \sample_0[12]\, sample_0(11) => - \sample_0[11]\, sample_0(10) => \sample_0[10]\, - sample_0(9) => \sample_0[9]\, sample_0(8) => - \sample_0[8]\, sample_0(7) => \sample_0[7]\, sample_0(6) - => \sample_0[6]\, sample_0(5) => \sample_0[5]\, - sample_0(4) => \sample_0[4]\, sample_0(3) => - \sample_0[3]\, sample_0(2) => \sample_0[2]\, sample_0(1) - => \sample_0[1]\, sample_0(0) => \sample_0[0]\, - sample_1(15) => \sample_1[15]\, sample_1(14) => - \sample_1[14]\, sample_1(13) => \sample_1[13]\, - sample_1(12) => \sample_1[12]\, sample_1(11) => - \sample_1[11]\, sample_1(10) => \sample_1[10]\, - sample_1(9) => \sample_1[9]\, sample_1(8) => - \sample_1[8]\, sample_1(7) => \sample_1[7]\, sample_1(6) - => \sample_1[6]\, sample_1(5) => \sample_1[5]\, - sample_1(4) => \sample_1[4]\, sample_1(3) => - \sample_1[3]\, sample_1(2) => \sample_1[2]\, sample_1(1) - => \sample_1[1]\, sample_1(0) => \sample_1[0]\, - sample_2(15) => \sample_2[15]\, sample_2(14) => - \sample_2[14]\, sample_2(13) => \sample_2[13]\, - sample_2(12) => \sample_2[12]\, sample_2(11) => - \sample_2[11]\, sample_2(10) => \sample_2[10]\, - sample_2(9) => \sample_2[9]\, sample_2(8) => - \sample_2[8]\, sample_2(7) => \sample_2[7]\, sample_2(6) - => \sample_2[6]\, sample_2(5) => \sample_2[5]\, - sample_2(4) => \sample_2[4]\, sample_2(3) => - \sample_2[3]\, sample_2(2) => \sample_2[2]\, sample_2(1) - => \sample_2[1]\, sample_2(0) => \sample_2[0]\, - sample_3(15) => \sample_3[15]\, sample_3(14) => - \sample_3[14]\, sample_3(13) => \sample_3[13]\, - sample_3(12) => \sample_3[12]\, sample_3(11) => - \sample_3[11]\, sample_3(10) => \sample_3[10]\, - sample_3(9) => \sample_3[9]\, sample_3(8) => - \sample_3[8]\, sample_3(7) => \sample_3[7]\, sample_3(6) - => \sample_3[6]\, sample_3(5) => \sample_3[5]\, - sample_3(4) => \sample_3[4]\, sample_3(3) => - \sample_3[3]\, sample_3(2) => \sample_3[2]\, sample_3(1) - => \sample_3[1]\, sample_3(0) => \sample_3[0]\, - sample_4(15) => \sample_4[15]\, sample_4(14) => - \sample_4[14]\, sample_4(13) => \sample_4[13]\, - sample_4(12) => \sample_4[12]\, sample_4(11) => - \sample_4[11]\, sample_4(10) => \sample_4[10]\, - sample_4(9) => \sample_4[9]\, sample_4(8) => - \sample_4[8]\, sample_4(7) => \sample_4[7]\, sample_4(6) - => \sample_4[6]\, sample_4(5) => \sample_4[5]\, - sample_4(4) => \sample_4[4]\, sample_4(3) => - \sample_4[3]\, sample_4(2) => \sample_4[2]\, sample_4(1) - => \sample_4[1]\, sample_4(0) => \sample_4[0]\, - sample_5(15) => \sample_5[15]\, sample_5(14) => - \sample_5[14]\, sample_5(13) => \sample_5[13]\, - sample_5(12) => \sample_5[12]\, sample_5(11) => - \sample_5[11]\, sample_5(10) => \sample_5[10]\, - sample_5(9) => \sample_5[9]\, sample_5(8) => - \sample_5[8]\, sample_5(7) => \sample_5[7]\, sample_5(6) - => \sample_5[6]\, sample_5(5) => \sample_5[5]\, - sample_5(4) => \sample_5[4]\, sample_5(3) => - \sample_5[3]\, sample_5(2) => \sample_5[2]\, sample_5(1) - => \sample_5[1]\, sample_5(0) => \sample_5[0]\, sdo_c(7) - => sdo_c(7), sdo_c(6) => sdo_c(6), sdo_c(5) => sdo_c(5), - sdo_c(4) => sdo_c(4), sdo_c(3) => sdo_c(3), sdo_c(2) => - sdo_c(2), sdo_c(1) => sdo_c(1), sdo_c(0) => sdo_c(0), - sample_6(15) => \sample_6[15]\, sample_6(14) => - \sample_6[14]\, sample_6(13) => \sample_6[13]\, - sample_6(12) => \sample_6[12]\, sample_6(11) => - \sample_6[11]\, sample_6(10) => \sample_6[10]\, - sample_6(9) => \sample_6[9]\, sample_6(8) => - \sample_6[8]\, sample_6(7) => \sample_6[7]\, sample_6(6) - => \sample_6[6]\, sample_6(5) => \sample_6[5]\, - sample_6(4) => \sample_6[4]\, sample_6(3) => - \sample_6[3]\, sample_6(2) => \sample_6[2]\, sample_6(1) - => \sample_6[1]\, sample_6(0) => \sample_6[0]\, - cnv_rstn_c => cnv_rstn_c, cnv_clk_c => cnv_clk_c, cnv_c - => cnv_c, sample_val => sample_val, sck_c => sck_c, - cnv_run_c => cnv_run_c, HRESETn_c => HRESETn_c, HCLK_c - => HCLK_c); - - \SampleLoop_data_shaping.10.sample_data_shaping_out_RNO[97]\ : - MX2 - port map(A => \sample_filter_v2_out[97]\, B => - \sample_data_shaping_f2_f1_s[10]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_257[97]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[96]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_281[96]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[96]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I20_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[139]\, B => - \sample_filter_v2_out[121]\, Y => N187); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I19_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[122]\, B => - \sample_filter_v2_out[140]\, Y => N186); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[62]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[62]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[62]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I43_Y : - XA1A - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, C => N187_0, Y => N275_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I48_Y : - NOR2 - port map(A => N255, B => N212_0, Y => N229_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I35_Y : - XAI1A - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[131]\, C => N201, Y => N255); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I41_Y : - NOR2B - port map(A => N191, B => N189, Y => N220_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[42]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[42]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[42]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[71]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[71]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[71]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I27_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[132]\, B => - \sample_filter_v2_out[114]\, Y => N201); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I17_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[106]\, B => - \sample_filter_v2_out[124]\, Y => N182); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[52]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[52]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[52]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I30_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[93]\, Y => N207); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[34]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[34]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[34]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_un1_Y : - OR3C - port map(A => N275_0, B => N220, C => N278_0, Y => - I56_un1_Y); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I64_un1_Y : - OR2B - port map(A => N268_0, B => N245, Y => I64_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I25_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[98]\, B => - \sample_filter_v2_out[116]\, Y => N198); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I25_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[116]\, B => - \sample_filter_v2_out[134]\, Y => N198_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I27_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[114]\, B => - \sample_filter_v2_out[132]\, Y => N202); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[111]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_349[111]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[111]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[9]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[9]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[9]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I105_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I87_un1_Y, B => N202_0, - C => N203, Y => \sample_data_shaping_f2_f1_s[12]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[7]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[7]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[7]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[48]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[48]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[48]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[132]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[132]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[132]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[31]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[31]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[31]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[16]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[16]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[16]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I33_Y : - NOR2B - port map(A => N207, B => N205_0, Y => N212); - - \SampleLoop_data_shaping.11.sample_data_shaping_out_RNO[114]\ : - MX2 - port map(A => \sample_filter_v2_out[114]\, B => - \sample_data_shaping_f1_f0_s[11]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_277[114]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I86_un1_Y : - OA1 - port map(A => I71_un1_Y, B => N254, C => N205_0, Y => - I86_un1_Y); - - \SampleLoop_data_shaping.12.sample_data_shaping_out_RNO[113]\ : - MX2 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_data_shaping_f1_f0_s[12]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_301[113]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[50]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[50]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[50]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out_RNO[94]\ : - MX2 - port map(A => \sample_filter_v2_out[94]\, B => - \sample_data_shaping_f2_f1_s[13]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_329[94]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[2]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[2]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[2]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[66]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[66]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[66]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[124]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_37[124]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[124]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I19_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, Y => N186_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I25_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[134]\, B => - \sample_filter_v2_out[116]\, Y => N197); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y : - OR2B - port map(A => SUB_16x16_medium_area_I56_Y_1, B => I56_un1_Y, - Y => N268_0); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[5]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[5]\, CLK => HCLK_c, CLR - => HRESETn_c, Q => \sample_data_shaping_out[5]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[105]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_65[105]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[105]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I104_Y_0 : - AX1A - port map(A => N244, B => I64_un1_Y, C => N201_0, Y => - \sample_data_shaping_f2_f1_s[11]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[92]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_377[92]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[92]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I89_un1_Y : - NOR2B - port map(A => N268_0, B => N193, Y => - SUB_16x16_medium_area_I89_un1_Y); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[44]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[44]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[44]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y_0 : - AO18 - port map(A => N190_0, B => \sample_filter_v2_out[137]\, C - => \sample_filter_v2_out[119]\, Y => - SUB_16x16_medium_area_I56_Y_0_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[21]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[21]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[21]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I35_Y : - NOR2B - port map(A => N203, B => N201_0, Y => N255_0); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[38]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[38]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[38]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y_1 : - AOI1B - port map(A => N274, B => N220, C => - SUB_16x16_medium_area_I56_Y_0, Y => - SUB_16x16_medium_area_I56_Y_1); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I50_Y : - NOR2B - port map(A => N265_0, B => N216_0, Y => N245); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_un1_Y_0 : - NOR2B - port map(A => N220_0, B => N275, Y => - SUB_16x16_medium_area_I56_un1_Y_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[100]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_185[100]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[100]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I98_Y_0 : - XOR2 - port map(A => N280, B => N189_0, Y => - \sample_data_shaping_f2_f1_s[5]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[95]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_305[95]\, CLK => - HCLK_c, CLR => HRESETn_c, Q => - \sample_data_shaping_out[95]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[65]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[65]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[65]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out_RNO[92]\ : - MX2 - port map(A => \sample_filter_v2_out[92]\, B => - \sample_data_shaping_f2_f1_s[15]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_377[92]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[131]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[131]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[131]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[22]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[22]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[22]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I91_un1_Y : - NOR2B - port map(A => N278, B => N185, Y => - SUB_16x16_medium_area_I91_un1_Y); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_Y_0 : - AO18 - port map(A => N182_0, B => \sample_filter_v2_out[141]\, C - => \sample_filter_v2_out[123]\, Y => - SUB_16x16_medium_area_I53_Y_0_0); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[12]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[12]\, CLK => HCLK_c, - CLR => HRESETn_c, Q => \sample_data_shaping_out[12]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I23_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, Y => N194_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I97_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I91_un1_Y, B => N186, C - => N187, Y => \sample_data_shaping_f1_f0_s[4]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I100_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N268, Y => - \sample_data_shaping_f1_f0_s[7]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_lfr_wf_picker is - - port( cnv_run : in std_logic; - cnv : out std_logic; - sck : out std_logic; - sdo : in std_logic_vector(7 downto 0); - cnv_clk : in std_logic; - cnv_rstn : in std_logic; - HCLK : in std_logic; - HRESETn : in std_logic; - apbi : in std_logic_vector(121 downto 0); - apbo : out std_logic_vector(131 downto 0); - AHB_Master_In : in std_logic_vector(90 downto 0); - AHB_Master_Out : out std_logic_vector(370 downto 0); - coarse_time_0 : in std_logic; - data_shaping_BW : out std_logic - ); - -end lpp_top_lfr_wf_picker; - -architecture DEF_ARCH of lpp_top_lfr_wf_picker is - - component OUTBUF - port( D : in std_logic := 'U'; - PAD : out std_logic - ); - end component; - - component INBUF - port( PAD : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component lpp_top_apbreg - port( status_full_ack : out std_logic_vector(3 downto 0); - prdata_c : out std_logic_vector(31 downto 0); - pirq_c : out std_logic_vector(15 to 15); - addr_data_f2 : out std_logic_vector(31 downto 0); - status_new_err_3 : in std_logic := 'U'; - status_new_err_0_2 : in std_logic := 'U'; - status_new_err_0_0 : in std_logic := 'U'; - status_new_err_0_1 : in std_logic := 'U'; - status_full_err_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - status_full : in std_logic_vector(3 downto 0) := (others => 'U'); - addr_data_f3 : out std_logic_vector(31 downto 0); - nb_burst_available : out std_logic_vector(10 downto 0); - addr_data_f1 : out std_logic_vector(31 downto 0); - delta_f2_f1 : out std_logic_vector(9 downto 0); - addr_data_f0 : out std_logic_vector(31 downto 0); - delta_f2_f0 : out std_logic_vector(9 downto 0); - delta_snapshot : out std_logic_vector(15 downto 0); - nb_snapshot_param : out std_logic_vector(10 downto 0); - apbi_c_81 : in std_logic := 'U'; - apbi_c_80 : in std_logic := 'U'; - apbi_c_79 : in std_logic := 'U'; - apbi_c_78 : in std_logic := 'U'; - apbi_c_77 : in std_logic := 'U'; - apbi_c_76 : in std_logic := 'U'; - apbi_c_75 : in std_logic := 'U'; - apbi_c_74 : in std_logic := 'U'; - apbi_c_73 : in std_logic := 'U'; - apbi_c_72 : in std_logic := 'U'; - apbi_c_71 : in std_logic := 'U'; - apbi_c_70 : in std_logic := 'U'; - apbi_c_69 : in std_logic := 'U'; - apbi_c_68 : in std_logic := 'U'; - apbi_c_67 : in std_logic := 'U'; - apbi_c_66 : in std_logic := 'U'; - apbi_c_65 : in std_logic := 'U'; - apbi_c_64 : in std_logic := 'U'; - apbi_c_63 : in std_logic := 'U'; - apbi_c_62 : in std_logic := 'U'; - apbi_c_61 : in std_logic := 'U'; - apbi_c_60 : in std_logic := 'U'; - apbi_c_59 : in std_logic := 'U'; - apbi_c_58 : in std_logic := 'U'; - apbi_c_57 : in std_logic := 'U'; - apbi_c_56 : in std_logic := 'U'; - apbi_c_55 : in std_logic := 'U'; - apbi_c_24 : in std_logic := 'U'; - apbi_c_23 : in std_logic := 'U'; - apbi_c_0 : in std_logic := 'U'; - apbi_c_50 : in std_logic := 'U'; - apbi_c_51 : in std_logic := 'U'; - apbi_c_52 : in std_logic := 'U'; - apbi_c_16 : in std_logic := 'U'; - apbi_c_49 : in std_logic := 'U'; - apbi_c_22 : in std_logic := 'U'; - apbi_c_20 : in std_logic := 'U'; - apbi_c_19 : in std_logic := 'U'; - apbi_c_21 : in std_logic := 'U'; - apbi_c_54 : in std_logic := 'U'; - apbi_c_53 : in std_logic := 'U'; - data_shaping_R0 : out std_logic; - data_shaping_R1 : out std_logic; - enable_f0 : out std_logic; - data_shaping_BW_c : out std_logic; - burst_f2 : out std_logic; - burst_f1 : out std_logic; - burst_f0 : out std_logic; - enable_f3 : out std_logic; - enable_f2 : out std_logic; - data_shaping_SP1 : out std_logic; - enable_f1 : out std_logic; - data_shaping_SP0 : out std_logic; - data_shaping_R1_0 : out std_logic; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U'; - data_shaping_R0_0 : out std_logic - ); - end component; - - component lpp_top_lfr_wf_picker_ip - port( nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - status_new_err : out std_logic_vector(3 downto 0); - hwdata_c : out std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - haddr_c : out std_logic_vector(31 downto 0); - AHB_Master_In_c_3 : in std_logic := 'U'; - AHB_Master_In_c_0 : in std_logic := 'U'; - AHB_Master_In_c_4 : in std_logic := 'U'; - AHB_Master_In_c_5 : in std_logic := 'U'; - hsize_c : out std_logic_vector(1 downto 0); - htrans_c : out std_logic_vector(1 downto 0); - hburst_c : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - sdo_c : in std_logic_vector(7 downto 0) := (others => 'U'); - coarse_time_0_c : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - data_shaping_R0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - enable_f3 : in std_logic := 'U'; - N_43 : out std_logic; - IdlePhase_RNI03G71 : out std_logic; - hwrite_c : out std_logic; - lpp_top_lfr_wf_picker_ip_GND : in std_logic := 'U'; - lpp_top_lfr_wf_picker_ip_VCC : in std_logic := 'U'; - cnv_run_c : in std_logic := 'U'; - sck_c : out std_logic; - cnv_c : out std_logic; - cnv_clk_c : in std_logic := 'U'; - cnv_rstn_c : in std_logic := 'U'; - data_shaping_SP0 : in std_logic := 'U'; - data_shaping_SP1 : in std_logic := 'U'; - HRESETn_c : in std_logic := 'U'; - HCLK_c : in std_logic := 'U' - ); - end component; - - component CLKBUF - port( PAD : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \status_full[0]\, \status_full[1]\, \status_full[2]\, - \status_full[3]\, \status_full_ack[0]\, - \status_full_ack[1]\, \status_full_ack[2]\, - \status_full_ack[3]\, \status_full_err[0]\, - \status_full_err[1]\, \status_full_err[2]\, - \status_full_err[3]\, \status_new_err[0]\, - \status_new_err[1]\, \status_new_err[2]\, - \status_new_err[3]\, data_shaping_SP0, data_shaping_SP1, - data_shaping_R0, data_shaping_R1, \delta_snapshot[0]\, - \delta_snapshot[1]\, \delta_snapshot[2]\, - \delta_snapshot[3]\, \delta_snapshot[4]\, - \delta_snapshot[5]\, \delta_snapshot[6]\, - \delta_snapshot[7]\, \delta_snapshot[8]\, - \delta_snapshot[9]\, \delta_snapshot[10]\, - \delta_snapshot[11]\, \delta_snapshot[12]\, - \delta_snapshot[13]\, \delta_snapshot[14]\, - \delta_snapshot[15]\, \delta_f2_f1[0]\, \delta_f2_f1[1]\, - \delta_f2_f1[2]\, \delta_f2_f1[3]\, \delta_f2_f1[4]\, - \delta_f2_f1[5]\, \delta_f2_f1[6]\, \delta_f2_f1[7]\, - \delta_f2_f1[8]\, \delta_f2_f1[9]\, \delta_f2_f0[0]\, - \delta_f2_f0[1]\, \delta_f2_f0[2]\, \delta_f2_f0[3]\, - \delta_f2_f0[4]\, \delta_f2_f0[5]\, \delta_f2_f0[6]\, - \delta_f2_f0[7]\, \delta_f2_f0[8]\, \delta_f2_f0[9]\, - \nb_burst_available[0]\, \nb_burst_available[1]\, - \nb_burst_available[2]\, \nb_burst_available[3]\, - \nb_burst_available[4]\, \nb_burst_available[5]\, - \nb_burst_available[6]\, \nb_burst_available[7]\, - \nb_burst_available[8]\, \nb_burst_available[9]\, - \nb_burst_available[10]\, \nb_snapshot_param[0]\, - \nb_snapshot_param[1]\, \nb_snapshot_param[2]\, - \nb_snapshot_param[3]\, \nb_snapshot_param[4]\, - \nb_snapshot_param[5]\, \nb_snapshot_param[6]\, - \nb_snapshot_param[7]\, \nb_snapshot_param[8]\, - \nb_snapshot_param[9]\, \nb_snapshot_param[10]\, - enable_f0, enable_f1, enable_f2, enable_f3, burst_f0, - burst_f1, burst_f2, \addr_data_f0[0]\, \addr_data_f0[1]\, - \addr_data_f0[2]\, \addr_data_f0[3]\, \addr_data_f0[4]\, - \addr_data_f0[5]\, \addr_data_f0[6]\, \addr_data_f0[7]\, - \addr_data_f0[8]\, \addr_data_f0[9]\, \addr_data_f0[10]\, - \addr_data_f0[11]\, \addr_data_f0[12]\, - \addr_data_f0[13]\, \addr_data_f0[14]\, - \addr_data_f0[15]\, \addr_data_f0[16]\, - \addr_data_f0[17]\, \addr_data_f0[18]\, - \addr_data_f0[19]\, \addr_data_f0[20]\, - \addr_data_f0[21]\, \addr_data_f0[22]\, - \addr_data_f0[23]\, \addr_data_f0[24]\, - \addr_data_f0[25]\, \addr_data_f0[26]\, - \addr_data_f0[27]\, \addr_data_f0[28]\, - \addr_data_f0[29]\, \addr_data_f0[30]\, - \addr_data_f0[31]\, \addr_data_f1[0]\, \addr_data_f1[1]\, - \addr_data_f1[2]\, \addr_data_f1[3]\, \addr_data_f1[4]\, - \addr_data_f1[5]\, \addr_data_f1[6]\, \addr_data_f1[7]\, - \addr_data_f1[8]\, \addr_data_f1[9]\, \addr_data_f1[10]\, - \addr_data_f1[11]\, \addr_data_f1[12]\, - \addr_data_f1[13]\, \addr_data_f1[14]\, - \addr_data_f1[15]\, \addr_data_f1[16]\, - \addr_data_f1[17]\, \addr_data_f1[18]\, - \addr_data_f1[19]\, \addr_data_f1[20]\, - \addr_data_f1[21]\, \addr_data_f1[22]\, - \addr_data_f1[23]\, \addr_data_f1[24]\, - \addr_data_f1[25]\, \addr_data_f1[26]\, - \addr_data_f1[27]\, \addr_data_f1[28]\, - \addr_data_f1[29]\, \addr_data_f1[30]\, - \addr_data_f1[31]\, \addr_data_f2[0]\, \addr_data_f2[1]\, - \addr_data_f2[2]\, \addr_data_f2[3]\, \addr_data_f2[4]\, - \addr_data_f2[5]\, \addr_data_f2[6]\, \addr_data_f2[7]\, - \addr_data_f2[8]\, \addr_data_f2[9]\, \addr_data_f2[10]\, - \addr_data_f2[11]\, \addr_data_f2[12]\, - \addr_data_f2[13]\, \addr_data_f2[14]\, - \addr_data_f2[15]\, \addr_data_f2[16]\, - \addr_data_f2[17]\, \addr_data_f2[18]\, - \addr_data_f2[19]\, \addr_data_f2[20]\, - \addr_data_f2[21]\, \addr_data_f2[22]\, - \addr_data_f2[23]\, \addr_data_f2[24]\, - \addr_data_f2[25]\, \addr_data_f2[26]\, - \addr_data_f2[27]\, \addr_data_f2[28]\, - \addr_data_f2[29]\, \addr_data_f2[30]\, - \addr_data_f2[31]\, \addr_data_f3[0]\, \addr_data_f3[1]\, - \addr_data_f3[2]\, \addr_data_f3[3]\, \addr_data_f3[4]\, - \addr_data_f3[5]\, \addr_data_f3[6]\, \addr_data_f3[7]\, - \addr_data_f3[8]\, \addr_data_f3[9]\, \addr_data_f3[10]\, - \addr_data_f3[11]\, \addr_data_f3[12]\, - \addr_data_f3[13]\, \addr_data_f3[14]\, - \addr_data_f3[15]\, \addr_data_f3[16]\, - \addr_data_f3[17]\, \addr_data_f3[18]\, - \addr_data_f3[19]\, \addr_data_f3[20]\, - \addr_data_f3[21]\, \addr_data_f3[22]\, - \addr_data_f3[23]\, \addr_data_f3[24]\, - \addr_data_f3[25]\, \addr_data_f3[26]\, - \addr_data_f3[27]\, \addr_data_f3[28]\, - \addr_data_f3[29]\, \addr_data_f3[30]\, - \addr_data_f3[31]\, IdlePhase_RNI03G71, - \lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.N_43\, - cnv_run_c, cnv_c, sck_c, \sdo_c[0]\, \sdo_c[1]\, - \sdo_c[2]\, \sdo_c[3]\, \sdo_c[4]\, \sdo_c[5]\, - \sdo_c[6]\, \sdo_c[7]\, cnv_clk_c, cnv_rstn_c, HCLK_c, - HRESETn_c, \apbi_c[0]\, \apbi_c[16]\, \apbi_c[19]\, - \apbi_c[20]\, \apbi_c[21]\, \apbi_c[22]\, \apbi_c[23]\, - \apbi_c[24]\, \apbi_c[49]\, \apbi_c[50]\, \apbi_c[51]\, - \apbi_c[52]\, \apbi_c[53]\, \apbi_c[54]\, \apbi_c[55]\, - \apbi_c[56]\, \apbi_c[57]\, \apbi_c[58]\, \apbi_c[59]\, - \apbi_c[60]\, \apbi_c[61]\, \apbi_c[62]\, \apbi_c[63]\, - \apbi_c[64]\, \apbi_c[65]\, \apbi_c[66]\, \apbi_c[67]\, - \apbi_c[68]\, \apbi_c[69]\, \apbi_c[70]\, \apbi_c[71]\, - \apbi_c[72]\, \apbi_c[73]\, \apbi_c[74]\, \apbi_c[75]\, - \apbi_c[76]\, \apbi_c[77]\, \apbi_c[78]\, \apbi_c[79]\, - \apbi_c[80]\, \apbi_c[81]\, \apbo.prdata_c[0]\, - \apbo.prdata_c[1]\, \apbo.prdata_c[2]\, - \apbo.prdata_c[3]\, \apbo.prdata_c[4]\, - \apbo.prdata_c[5]\, \apbo.prdata_c[6]\, - \apbo.prdata_c[7]\, \apbo.prdata_c[8]\, - \apbo.prdata_c[9]\, \apbo.prdata_c[10]\, - \apbo.prdata_c[11]\, \apbo.prdata_c[12]\, - \apbo.prdata_c[13]\, \apbo.prdata_c[14]\, - \apbo.prdata_c[15]\, \apbo.prdata_c[16]\, - \apbo.prdata_c[17]\, \apbo.prdata_c[18]\, - \apbo.prdata_c[19]\, \apbo.prdata_c[20]\, - \apbo.prdata_c[21]\, \apbo.prdata_c[22]\, - \apbo.prdata_c[23]\, \apbo.prdata_c[24]\, - \apbo.prdata_c[25]\, \apbo.prdata_c[26]\, - \apbo.prdata_c[27]\, \apbo.prdata_c[28]\, - \apbo.prdata_c[29]\, \apbo.prdata_c[30]\, - \apbo.prdata_c[31]\, \apbo.pirq_c[15]\, - \AHB_Master_In_c[13]\, \AHB_Master_In_c[16]\, - \AHB_Master_In_c[17]\, \AHB_Master_In_c[18]\, - \AHB_Master_Out.htrans_c[0]\, - \AHB_Master_Out.htrans_c[1]\, \AHB_Master_Out.haddr_c[0]\, - \AHB_Master_Out.haddr_c[1]\, \AHB_Master_Out.haddr_c[2]\, - \AHB_Master_Out.haddr_c[3]\, \AHB_Master_Out.haddr_c[4]\, - \AHB_Master_Out.haddr_c[5]\, \AHB_Master_Out.haddr_c[6]\, - \AHB_Master_Out.haddr_c[7]\, \AHB_Master_Out.haddr_c[8]\, - \AHB_Master_Out.haddr_c[9]\, \AHB_Master_Out.haddr_c[10]\, - \AHB_Master_Out.haddr_c[11]\, - \AHB_Master_Out.haddr_c[12]\, - \AHB_Master_Out.haddr_c[13]\, - \AHB_Master_Out.haddr_c[14]\, - \AHB_Master_Out.haddr_c[15]\, - \AHB_Master_Out.haddr_c[16]\, - \AHB_Master_Out.haddr_c[17]\, - \AHB_Master_Out.haddr_c[18]\, - \AHB_Master_Out.haddr_c[19]\, - \AHB_Master_Out.haddr_c[20]\, - \AHB_Master_Out.haddr_c[21]\, - \AHB_Master_Out.haddr_c[22]\, - \AHB_Master_Out.haddr_c[23]\, - \AHB_Master_Out.haddr_c[24]\, - \AHB_Master_Out.haddr_c[25]\, - \AHB_Master_Out.haddr_c[26]\, - \AHB_Master_Out.haddr_c[27]\, - \AHB_Master_Out.haddr_c[28]\, - \AHB_Master_Out.haddr_c[29]\, - \AHB_Master_Out.haddr_c[30]\, - \AHB_Master_Out.haddr_c[31]\, \AHB_Master_Out.hwrite_c\, - \AHB_Master_Out.hsize_c[0]\, \AHB_Master_Out.hsize_c[1]\, - \AHB_Master_Out.hburst_c[0]\, - \AHB_Master_Out.hburst_c[1]\, - \AHB_Master_Out.hburst_c[2]\, - \AHB_Master_Out.hwdata_c[0]\, - \AHB_Master_Out.hwdata_c[1]\, - \AHB_Master_Out.hwdata_c[2]\, - \AHB_Master_Out.hwdata_c[3]\, - \AHB_Master_Out.hwdata_c[4]\, - \AHB_Master_Out.hwdata_c[5]\, - \AHB_Master_Out.hwdata_c[6]\, - \AHB_Master_Out.hwdata_c[7]\, - \AHB_Master_Out.hwdata_c[8]\, - \AHB_Master_Out.hwdata_c[9]\, - \AHB_Master_Out.hwdata_c[10]\, - \AHB_Master_Out.hwdata_c[11]\, - \AHB_Master_Out.hwdata_c[12]\, - \AHB_Master_Out.hwdata_c[13]\, - \AHB_Master_Out.hwdata_c[14]\, - \AHB_Master_Out.hwdata_c[15]\, - \AHB_Master_Out.hwdata_c[16]\, - \AHB_Master_Out.hwdata_c[17]\, - \AHB_Master_Out.hwdata_c[18]\, - \AHB_Master_Out.hwdata_c[19]\, - \AHB_Master_Out.hwdata_c[20]\, - \AHB_Master_Out.hwdata_c[21]\, - \AHB_Master_Out.hwdata_c[22]\, - \AHB_Master_Out.hwdata_c[23]\, - \AHB_Master_Out.hwdata_c[24]\, - \AHB_Master_Out.hwdata_c[25]\, - \AHB_Master_Out.hwdata_c[26]\, - \AHB_Master_Out.hwdata_c[27]\, - \AHB_Master_Out.hwdata_c[28]\, - \AHB_Master_Out.hwdata_c[29]\, - \AHB_Master_Out.hwdata_c[30]\, - \AHB_Master_Out.hwdata_c[31]\, \VCC\, \GND\, - coarse_time_0_c, data_shaping_BW_c, data_shaping_R1_0, - data_shaping_R0_0, GND_0, VCC_0 : std_logic; - - for all : lpp_top_apbreg - Use entity work.lpp_top_apbreg(DEF_ARCH); - for all : lpp_top_lfr_wf_picker_ip - Use entity work.lpp_top_lfr_wf_picker_ip(DEF_ARCH); -begin - - - \apbo_pad[90]\ : OUTBUF - port map(D => \GND\, PAD => apbo(90)); - - \apbi_pad[78]\ : INBUF - port map(PAD => apbi(78), Y => \apbi_c[78]\); - - \apbo_pad[113]\ : OUTBUF - port map(D => \GND\, PAD => apbo(113)); - - \AHB_Master_Out_pad[189]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(189)); - - \AHB_Master_Out_pad[170]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(170)); - - \apbo_pad[106]\ : OUTBUF - port map(D => \GND\, PAD => apbo(106)); - - \apbi_pad[23]\ : INBUF - port map(PAD => apbi(23), Y => \apbi_c[23]\); - - \apbo_pad[18]\ : OUTBUF - port map(D => \apbo.prdata_c[18]\, PAD => apbo(18)); - - \AHB_Master_Out_pad[15]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[11]\, PAD => - AHB_Master_Out(15)); - - \AHB_Master_Out_pad[6]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[2]\, PAD => - AHB_Master_Out(6)); - - \AHB_Master_Out_pad[4]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[0]\, PAD => - AHB_Master_Out(4)); - - \AHB_Master_Out_pad[40]\ : OUTBUF - port map(D => \AHB_Master_Out.hburst_c[0]\, PAD => - AHB_Master_Out(40)); - - \AHB_Master_Out_pad[176]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(176)); - - \AHB_Master_Out_pad[132]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(132)); - - \AHB_Master_Out_pad[51]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[4]\, PAD => - AHB_Master_Out(51)); - - \apbo_pad[102]\ : OUTBUF - port map(D => \GND\, PAD => apbo(102)); - - \AHB_Master_Out_pad[257]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(257)); - - \apbo_pad[124]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(124)); - - \AHB_Master_Out_pad[318]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(318)); - - \apbo_pad[91]\ : OUTBUF - port map(D => \GND\, PAD => apbo(91)); - - \AHB_Master_Out_pad[328]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(328)); - - \AHB_Master_In_pad[17]\ : INBUF - port map(PAD => AHB_Master_In(17), Y => - \AHB_Master_In_c[17]\); - - \apbo_pad[95]\ : OUTBUF - port map(D => \GND\, PAD => apbo(95)); - - \AHB_Master_Out_pad[348]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(348)); - - \AHB_Master_Out_pad[259]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(259)); - - \AHB_Master_Out_pad[332]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(332)); - - \AHB_Master_Out_pad[12]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[8]\, PAD => - AHB_Master_Out(12)); - - \AHB_Master_Out_pad[1]\ : OUTBUF - port map(D => - \lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.N_43\, - PAD => AHB_Master_Out(1)); - - \sdo_pad[4]\ : INBUF - port map(PAD => sdo(4), Y => \sdo_c[4]\); - - \AHB_Master_Out_pad[46]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(46)); - - \apbo_pad[48]\ : OUTBUF - port map(D => \GND\, PAD => apbo(48)); - - \AHB_Master_Out_pad[214]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(214)); - - \apbo_pad[6]\ : OUTBUF - port map(D => \apbo.prdata_c[6]\, PAD => apbo(6)); - - \AHB_Master_Out_pad[224]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(224)); - - \AHB_Master_Out_pad[244]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(244)); - - \AHB_Master_Out_pad[150]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(150)); - - \AHB_Master_Out_pad[368]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(368)); - - \AHB_Master_Out_pad[339]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(339)); - - \AHB_Master_Out_pad[297]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(297)); - - \AHB_Master_Out_pad[201]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(201)); - - \AHB_Master_Out_pad[47]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[0]\, PAD => - AHB_Master_Out(47)); - - \AHB_Master_Out_pad[307]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(307)); - - \AHB_Master_Out_pad[213]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(213)); - - \apbo_pad[57]\ : OUTBUF - port map(D => \GND\, PAD => apbo(57)); - - \AHB_Master_Out_pad[223]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(223)); - - \AHB_Master_Out_pad[156]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(156)); - - \AHB_Master_Out_pad[111]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(111)); - - \apbi_pad[76]\ : INBUF - port map(PAD => apbi(76), Y => \apbi_c[76]\); - - \AHB_Master_Out_pad[243]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(243)); - - \AHB_Master_Out_pad[121]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(121)); - - \apbo_pad[89]\ : OUTBUF - port map(D => \GND\, PAD => apbo(89)); - - \AHB_Master_Out_pad[299]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(299)); - - \AHB_Master_Out_pad[141]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(141)); - - \AHB_Master_Out_pad[49]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[2]\, PAD => - AHB_Master_Out(49)); - - \AHB_Master_Out_pad[182]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(182)); - - \apbo_pad[16]\ : OUTBUF - port map(D => \apbo.prdata_c[16]\, PAD => apbo(16)); - - \AHB_Master_Out_pad[264]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(264)); - - \AHB_Master_Out_pad[301]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(301)); - - \apbo_pad[53]\ : OUTBUF - port map(D => \GND\, PAD => apbo(53)); - - \AHB_Master_Out_pad[190]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(190)); - - \AHB_Master_Out_pad[232]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(232)); - - \AHB_Master_In_pad[16]\ : INBUF - port map(PAD => AHB_Master_In(16), Y => - \AHB_Master_In_c[16]\); - - \AHB_Master_Out_pad[263]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(263)); - - \AHB_Master_Out_pad[25]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[21]\, PAD => - AHB_Master_Out(25)); - - \AHB_Master_Out_pad[161]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(161)); - - \AHB_Master_Out_pad[196]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(196)); - - \AHB_Master_Out_pad[134]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(134)); - - \AHB_Master_Out_pad[0]\ : OUTBUF - port map(D => IdlePhase_RNI03G71, PAD => AHB_Master_Out(0)); - - \AHB_Master_In_pad[13]\ : INBUF - port map(PAD => AHB_Master_In(13), Y => - \AHB_Master_In_c[13]\); - - sck_pad : OUTBUF - port map(D => sck_c, PAD => sck); - - \apbi_pad[68]\ : INBUF - port map(PAD => apbi(68), Y => \apbi_c[68]\); - - \AHB_Master_Out_pad[200]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(200)); - - \AHB_Master_Out_pad[61]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[14]\, PAD => - AHB_Master_Out(61)); - - \AHB_Master_Out_pad[105]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(105)); - - \AHB_Master_Out_pad[117]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(117)); - - \AHB_Master_Out_pad[127]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(127)); - - \AHB_Master_Out_pad[147]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(147)); - - \apbo_pad[46]\ : OUTBUF - port map(D => \GND\, PAD => apbo(46)); - - \AHB_Master_Out_pad[335]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(335)); - - \apbi_pad[74]\ : INBUF - port map(PAD => apbi(74), Y => \apbi_c[74]\); - - \AHB_Master_Out_pad[22]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[18]\, PAD => - AHB_Master_Out(22)); - - \apbo_pad[131]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(131)); - - \apbo_pad[7]\ : OUTBUF - port map(D => \apbo.prdata_c[7]\, PAD => apbo(7)); - - \AHB_Master_Out_pad[206]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(206)); - - coarse_time_0_pad : INBUF - port map(PAD => coarse_time_0, Y => coarse_time_0_c); - - \apbo_pad[127]\ : OUTBUF - port map(D => \GND\, PAD => apbo(127)); - - \apbo_pad[14]\ : OUTBUF - port map(D => \apbo.prdata_c[14]\, PAD => apbo(14)); - - \AHB_Master_Out_pad[108]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(108)); - - \apbo_pad[119]\ : OUTBUF - port map(D => \GND\, PAD => apbo(119)); - - \AHB_Master_Out_pad[167]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(167)); - - \AHB_Master_Out_pad[14]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[10]\, PAD => - AHB_Master_Out(14)); - - \AHB_Master_Out_pad[31]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[27]\, PAD => - AHB_Master_Out(31)); - - \AHB_Master_Out_pad[282]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(282)); - - \AHB_Master_Out_pad[184]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(184)); - - \AHB_Master_Out_pad[133]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(133)); - - \apbo_pad[98]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(98)); - - \AHB_Master_Out_pad[303]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(303)); - - \apbo_pad[44]\ : OUTBUF - port map(D => \GND\, PAD => apbo(44)); - - \apbi_pad[66]\ : INBUF - port map(PAD => apbi(66), Y => \apbi_c[66]\); - - \AHB_Master_Out_pad[274]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(274)); - - \apbo_pad[79]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(79)); - - \AHB_Master_Out_pad[211]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(211)); - - \apbo_pad[32]\ : OUTBUF - port map(D => \GND\, PAD => apbo(32)); - - \AHB_Master_Out_pad[317]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(317)); - - \AHB_Master_Out_pad[221]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(221)); - - \AHB_Master_Out_pad[327]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(327)); - - \AHB_Master_Out_pad[241]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(241)); - - \apbi_pad[52]\ : INBUF - port map(PAD => apbi(52), Y => \apbi_c[52]\); - - \AHB_Master_Out_pad[347]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(347)); - - \apbo_pad[22]\ : OUTBUF - port map(D => \apbo.prdata_c[22]\, PAD => apbo(22)); - - \AHB_Master_Out_pad[7]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[3]\, PAD => - AHB_Master_Out(7)); - - \AHB_Master_Out_pad[336]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(336)); - - \AHB_Master_Out_pad[273]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(273)); - - \apbo_pad[116]\ : OUTBUF - port map(D => \GND\, PAD => apbo(116)); - - \AHB_Master_Out_pad[171]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(171)); - - \apbo_pad[108]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(108)); - - \sdo_pad[1]\ : INBUF - port map(PAD => sdo(1), Y => \sdo_c[1]\); - - \AHB_Master_Out_pad[98]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(98)); - - \AHB_Master_Out_pad[13]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[9]\, PAD => - AHB_Master_Out(13)); - - \AHB_Master_Out_pad[358]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(358)); - - \AHB_Master_Out_pad[311]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(311)); - - \apbo_pad[30]\ : OUTBUF - port map(D => \apbo.prdata_c[30]\, PAD => apbo(30)); - - \AHB_Master_Out_pad[321]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(321)); - - \AHB_Master_Out_pad[208]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(208)); - - \apbo_pad[62]\ : OUTBUF - port map(D => \GND\, PAD => apbo(62)); - - \apbo_pad[112]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(112)); - - \AHB_Master_Out_pad[341]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(341)); - - \apbi_pad[50]\ : INBUF - port map(PAD => apbi(50), Y => \apbi_c[50]\); - - \apbo_pad[20]\ : OUTBUF - port map(D => \apbo.prdata_c[20]\, PAD => apbo(20)); - - \AHB_Master_Out_pad[261]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(261)); - - \AHB_Master_Out_pad[367]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(367)); - - \AHB_Master_Out_pad[90]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(90)); - - \AHB_Master_Out_pad[183]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(183)); - - \AHB_Master_Out_pad[109]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(109)); - - GND_i : GND - port map(Y => \GND\); - - \AHB_Master_Out_pad[45]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(45)); - - \AHB_Master_Out_pad[254]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(254)); - - \AHB_Master_Out_pad[210]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(210)); - - \AHB_Master_Out_pad[220]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(220)); - - \AHB_Master_Out_pad[115]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(115)); - - \apbo_pad[60]\ : OUTBUF - port map(D => \GND\, PAD => apbo(60)); - - \apbi_pad[77]\ : INBUF - port map(PAD => apbi(77), Y => \apbi_c[77]\); - - \apbi_pad[64]\ : INBUF - port map(PAD => apbi(64), Y => \apbi_c[64]\); - - \AHB_Master_Out_pad[240]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(240)); - - \AHB_Master_Out_pad[125]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(125)); - - \apbo_pad[96]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(96)); - - \AHB_Master_Out_pad[145]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(145)); - - \apbo_pad[31]\ : OUTBUF - port map(D => \apbo.prdata_c[31]\, PAD => apbo(31)); - - \AHB_Master_Out_pad[361]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(361)); - - \AHB_Master_Out_pad[334]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(334)); - - \AHB_Master_Out_pad[24]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[20]\, PAD => - AHB_Master_Out(24)); - - \AHB_Master_In_pad[18]\ : INBUF - port map(PAD => AHB_Master_In(18), Y => - \AHB_Master_In_c[18]\); - - \apbo_pad[35]\ : OUTBUF - port map(D => \GND\, PAD => apbo(35)); - - \apbi_pad[51]\ : INBUF - port map(PAD => apbi(51), Y => \apbi_c[51]\); - - \AHB_Master_Out_pad[253]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(253)); - - \AHB_Master_Out_pad[177]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(177)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \apbo_pad[21]\ : OUTBUF - port map(D => \apbo.prdata_c[21]\, PAD => apbo(21)); - - \apbi_pad[55]\ : INBUF - port map(PAD => apbi(55), Y => \apbi_c[55]\); - - \AHB_Master_Out_pad[151]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(151)); - - \apbo_pad[25]\ : OUTBUF - port map(D => \apbo.prdata_c[25]\, PAD => apbo(25)); - - \apbo_pad[17]\ : OUTBUF - port map(D => \apbo.prdata_c[17]\, PAD => apbo(17)); - - \apbo_pad[120]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(120)); - - \AHB_Master_Out_pad[300]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(300)); - - data_shaping_BW_pad : OUTBUF - port map(D => data_shaping_BW_c, PAD => data_shaping_BW); - - \apbi_pad[73]\ : INBUF - port map(PAD => apbi(73), Y => \apbi_c[73]\); - - \AHB_Master_Out_pad[96]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(96)); - - \AHB_Master_Out_pad[216]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(216)); - - \apbo_pad[4]\ : OUTBUF - port map(D => \apbo.prdata_c[4]\, PAD => apbo(4)); - - \AHB_Master_Out_pad[226]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(226)); - - \AHB_Master_Out_pad[42]\ : OUTBUF - port map(D => \AHB_Master_Out.hburst_c[2]\, PAD => - AHB_Master_Out(42)); - - \AHB_Master_Out_pad[246]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(246)); - - \AHB_Master_Out_pad[260]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(260)); - - \AHB_Master_Out_pad[118]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(118)); - - \apbo_pad[61]\ : OUTBUF - port map(D => \GND\, PAD => apbo(61)); - - \AHB_Master_Out_pad[294]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(294)); - - \AHB_Master_Out_pad[165]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(165)); - - \AHB_Master_Out_pad[128]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(128)); - - \apbo_pad[65]\ : OUTBUF - port map(D => \GND\, PAD => apbo(65)); - - \AHB_Master_Out_pad[148]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(148)); - - \apbo_pad[13]\ : OUTBUF - port map(D => \apbo.prdata_c[13]\, PAD => apbo(13)); - - \AHB_Master_Out_pad[97]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(97)); - - \apbi_pad[80]\ : INBUF - port map(PAD => apbi(80), Y => \apbi_c[80]\); - - \AHB_Master_Out_pad[235]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(235)); - - \apbo_pad[101]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(101)); - - \AHB_Master_Out_pad[293]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(293)); - - \AHB_Master_Out_pad[191]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(191)); - - \AHB_Master_Out_pad[99]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(99)); - - \apbo_pad[59]\ : OUTBUF - port map(D => \GND\, PAD => apbo(59)); - - \apbo_pad[47]\ : OUTBUF - port map(D => \apbo.pirq_c[15]\, PAD => apbo(47)); - - \AHB_Master_Out_pad[266]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(266)); - - \AHB_Master_Out_pad[23]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[19]\, PAD => - AHB_Master_Out(23)); - - \apbo_pad[94]\ : OUTBUF - port map(D => \GND\, PAD => apbo(94)); - - \apbo_pad[105]\ : OUTBUF - port map(D => \GND\, PAD => apbo(105)); - - \AHB_Master_Out_pad[157]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(157)); - - \AHB_Master_Out_pad[313]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(313)); - - \AHB_Master_Out_pad[168]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(168)); - - \AHB_Master_Out_pad[323]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(323)); - - \AHB_Master_Out_pad[102]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(102)); - - \AHB_Master_Out_pad[343]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(343)); - - \apbo_pad[5]\ : OUTBUF - port map(D => \apbo.prdata_c[5]\, PAD => apbo(5)); - - \apbi_pad[81]\ : INBUF - port map(PAD => apbi(81), Y => \apbi_c[81]\); - - \apbo_pad[43]\ : OUTBUF - port map(D => \GND\, PAD => apbo(43)); - - lpp_top_apbreg_1 : lpp_top_apbreg - port map(status_full_ack(3) => \status_full_ack[3]\, - status_full_ack(2) => \status_full_ack[2]\, - status_full_ack(1) => \status_full_ack[1]\, - status_full_ack(0) => \status_full_ack[0]\, prdata_c(31) - => \apbo.prdata_c[31]\, prdata_c(30) => - \apbo.prdata_c[30]\, prdata_c(29) => \apbo.prdata_c[29]\, - prdata_c(28) => \apbo.prdata_c[28]\, prdata_c(27) => - \apbo.prdata_c[27]\, prdata_c(26) => \apbo.prdata_c[26]\, - prdata_c(25) => \apbo.prdata_c[25]\, prdata_c(24) => - \apbo.prdata_c[24]\, prdata_c(23) => \apbo.prdata_c[23]\, - prdata_c(22) => \apbo.prdata_c[22]\, prdata_c(21) => - \apbo.prdata_c[21]\, prdata_c(20) => \apbo.prdata_c[20]\, - prdata_c(19) => \apbo.prdata_c[19]\, prdata_c(18) => - \apbo.prdata_c[18]\, prdata_c(17) => \apbo.prdata_c[17]\, - prdata_c(16) => \apbo.prdata_c[16]\, prdata_c(15) => - \apbo.prdata_c[15]\, prdata_c(14) => \apbo.prdata_c[14]\, - prdata_c(13) => \apbo.prdata_c[13]\, prdata_c(12) => - \apbo.prdata_c[12]\, prdata_c(11) => \apbo.prdata_c[11]\, - prdata_c(10) => \apbo.prdata_c[10]\, prdata_c(9) => - \apbo.prdata_c[9]\, prdata_c(8) => \apbo.prdata_c[8]\, - prdata_c(7) => \apbo.prdata_c[7]\, prdata_c(6) => - \apbo.prdata_c[6]\, prdata_c(5) => \apbo.prdata_c[5]\, - prdata_c(4) => \apbo.prdata_c[4]\, prdata_c(3) => - \apbo.prdata_c[3]\, prdata_c(2) => \apbo.prdata_c[2]\, - prdata_c(1) => \apbo.prdata_c[1]\, prdata_c(0) => - \apbo.prdata_c[0]\, pirq_c(15) => \apbo.pirq_c[15]\, - addr_data_f2(31) => \addr_data_f2[31]\, addr_data_f2(30) - => \addr_data_f2[30]\, addr_data_f2(29) => - \addr_data_f2[29]\, addr_data_f2(28) => - \addr_data_f2[28]\, addr_data_f2(27) => - \addr_data_f2[27]\, addr_data_f2(26) => - \addr_data_f2[26]\, addr_data_f2(25) => - \addr_data_f2[25]\, addr_data_f2(24) => - \addr_data_f2[24]\, addr_data_f2(23) => - \addr_data_f2[23]\, addr_data_f2(22) => - \addr_data_f2[22]\, addr_data_f2(21) => - \addr_data_f2[21]\, addr_data_f2(20) => - \addr_data_f2[20]\, addr_data_f2(19) => - \addr_data_f2[19]\, addr_data_f2(18) => - \addr_data_f2[18]\, addr_data_f2(17) => - \addr_data_f2[17]\, addr_data_f2(16) => - \addr_data_f2[16]\, addr_data_f2(15) => - \addr_data_f2[15]\, addr_data_f2(14) => - \addr_data_f2[14]\, addr_data_f2(13) => - \addr_data_f2[13]\, addr_data_f2(12) => - \addr_data_f2[12]\, addr_data_f2(11) => - \addr_data_f2[11]\, addr_data_f2(10) => - \addr_data_f2[10]\, addr_data_f2(9) => \addr_data_f2[9]\, - addr_data_f2(8) => \addr_data_f2[8]\, addr_data_f2(7) => - \addr_data_f2[7]\, addr_data_f2(6) => \addr_data_f2[6]\, - addr_data_f2(5) => \addr_data_f2[5]\, addr_data_f2(4) => - \addr_data_f2[4]\, addr_data_f2(3) => \addr_data_f2[3]\, - addr_data_f2(2) => \addr_data_f2[2]\, addr_data_f2(1) => - \addr_data_f2[1]\, addr_data_f2(0) => \addr_data_f2[0]\, - status_new_err_3 => \status_new_err[3]\, - status_new_err_0_2 => \status_new_err[2]\, - status_new_err_0_0 => \status_new_err[0]\, - status_new_err_0_1 => \status_new_err[1]\, - status_full_err_0(3) => \status_full_err[3]\, - status_full_err_0(2) => \status_full_err[2]\, - status_full_err_0(1) => \status_full_err[1]\, - status_full_err_0(0) => \status_full_err[0]\, - status_full(3) => \status_full[3]\, status_full(2) => - \status_full[2]\, status_full(1) => \status_full[1]\, - status_full(0) => \status_full[0]\, addr_data_f3(31) => - \addr_data_f3[31]\, addr_data_f3(30) => - \addr_data_f3[30]\, addr_data_f3(29) => - \addr_data_f3[29]\, addr_data_f3(28) => - \addr_data_f3[28]\, addr_data_f3(27) => - \addr_data_f3[27]\, addr_data_f3(26) => - \addr_data_f3[26]\, addr_data_f3(25) => - \addr_data_f3[25]\, addr_data_f3(24) => - \addr_data_f3[24]\, addr_data_f3(23) => - \addr_data_f3[23]\, addr_data_f3(22) => - \addr_data_f3[22]\, addr_data_f3(21) => - \addr_data_f3[21]\, addr_data_f3(20) => - \addr_data_f3[20]\, addr_data_f3(19) => - \addr_data_f3[19]\, addr_data_f3(18) => - \addr_data_f3[18]\, addr_data_f3(17) => - \addr_data_f3[17]\, addr_data_f3(16) => - \addr_data_f3[16]\, addr_data_f3(15) => - \addr_data_f3[15]\, addr_data_f3(14) => - \addr_data_f3[14]\, addr_data_f3(13) => - \addr_data_f3[13]\, addr_data_f3(12) => - \addr_data_f3[12]\, addr_data_f3(11) => - \addr_data_f3[11]\, addr_data_f3(10) => - \addr_data_f3[10]\, addr_data_f3(9) => \addr_data_f3[9]\, - addr_data_f3(8) => \addr_data_f3[8]\, addr_data_f3(7) => - \addr_data_f3[7]\, addr_data_f3(6) => \addr_data_f3[6]\, - addr_data_f3(5) => \addr_data_f3[5]\, addr_data_f3(4) => - \addr_data_f3[4]\, addr_data_f3(3) => \addr_data_f3[3]\, - addr_data_f3(2) => \addr_data_f3[2]\, addr_data_f3(1) => - \addr_data_f3[1]\, addr_data_f3(0) => \addr_data_f3[0]\, - nb_burst_available(10) => \nb_burst_available[10]\, - nb_burst_available(9) => \nb_burst_available[9]\, - nb_burst_available(8) => \nb_burst_available[8]\, - nb_burst_available(7) => \nb_burst_available[7]\, - nb_burst_available(6) => \nb_burst_available[6]\, - nb_burst_available(5) => \nb_burst_available[5]\, - nb_burst_available(4) => \nb_burst_available[4]\, - nb_burst_available(3) => \nb_burst_available[3]\, - nb_burst_available(2) => \nb_burst_available[2]\, - nb_burst_available(1) => \nb_burst_available[1]\, - nb_burst_available(0) => \nb_burst_available[0]\, - addr_data_f1(31) => \addr_data_f1[31]\, addr_data_f1(30) - => \addr_data_f1[30]\, addr_data_f1(29) => - \addr_data_f1[29]\, addr_data_f1(28) => - \addr_data_f1[28]\, addr_data_f1(27) => - \addr_data_f1[27]\, addr_data_f1(26) => - \addr_data_f1[26]\, addr_data_f1(25) => - \addr_data_f1[25]\, addr_data_f1(24) => - \addr_data_f1[24]\, addr_data_f1(23) => - \addr_data_f1[23]\, addr_data_f1(22) => - \addr_data_f1[22]\, addr_data_f1(21) => - \addr_data_f1[21]\, addr_data_f1(20) => - \addr_data_f1[20]\, addr_data_f1(19) => - \addr_data_f1[19]\, addr_data_f1(18) => - \addr_data_f1[18]\, addr_data_f1(17) => - \addr_data_f1[17]\, addr_data_f1(16) => - \addr_data_f1[16]\, addr_data_f1(15) => - \addr_data_f1[15]\, addr_data_f1(14) => - \addr_data_f1[14]\, addr_data_f1(13) => - \addr_data_f1[13]\, addr_data_f1(12) => - \addr_data_f1[12]\, addr_data_f1(11) => - \addr_data_f1[11]\, addr_data_f1(10) => - \addr_data_f1[10]\, addr_data_f1(9) => \addr_data_f1[9]\, - addr_data_f1(8) => \addr_data_f1[8]\, addr_data_f1(7) => - \addr_data_f1[7]\, addr_data_f1(6) => \addr_data_f1[6]\, - addr_data_f1(5) => \addr_data_f1[5]\, addr_data_f1(4) => - \addr_data_f1[4]\, addr_data_f1(3) => \addr_data_f1[3]\, - addr_data_f1(2) => \addr_data_f1[2]\, addr_data_f1(1) => - \addr_data_f1[1]\, addr_data_f1(0) => \addr_data_f1[0]\, - delta_f2_f1(9) => \delta_f2_f1[9]\, delta_f2_f1(8) => - \delta_f2_f1[8]\, delta_f2_f1(7) => \delta_f2_f1[7]\, - delta_f2_f1(6) => \delta_f2_f1[6]\, delta_f2_f1(5) => - \delta_f2_f1[5]\, delta_f2_f1(4) => \delta_f2_f1[4]\, - delta_f2_f1(3) => \delta_f2_f1[3]\, delta_f2_f1(2) => - \delta_f2_f1[2]\, delta_f2_f1(1) => \delta_f2_f1[1]\, - delta_f2_f1(0) => \delta_f2_f1[0]\, addr_data_f0(31) => - \addr_data_f0[31]\, addr_data_f0(30) => - \addr_data_f0[30]\, addr_data_f0(29) => - \addr_data_f0[29]\, addr_data_f0(28) => - \addr_data_f0[28]\, addr_data_f0(27) => - \addr_data_f0[27]\, addr_data_f0(26) => - \addr_data_f0[26]\, addr_data_f0(25) => - \addr_data_f0[25]\, addr_data_f0(24) => - \addr_data_f0[24]\, addr_data_f0(23) => - \addr_data_f0[23]\, addr_data_f0(22) => - \addr_data_f0[22]\, addr_data_f0(21) => - \addr_data_f0[21]\, addr_data_f0(20) => - \addr_data_f0[20]\, addr_data_f0(19) => - \addr_data_f0[19]\, addr_data_f0(18) => - \addr_data_f0[18]\, addr_data_f0(17) => - \addr_data_f0[17]\, addr_data_f0(16) => - \addr_data_f0[16]\, addr_data_f0(15) => - \addr_data_f0[15]\, addr_data_f0(14) => - \addr_data_f0[14]\, addr_data_f0(13) => - \addr_data_f0[13]\, addr_data_f0(12) => - \addr_data_f0[12]\, addr_data_f0(11) => - \addr_data_f0[11]\, addr_data_f0(10) => - \addr_data_f0[10]\, addr_data_f0(9) => \addr_data_f0[9]\, - addr_data_f0(8) => \addr_data_f0[8]\, addr_data_f0(7) => - \addr_data_f0[7]\, addr_data_f0(6) => \addr_data_f0[6]\, - addr_data_f0(5) => \addr_data_f0[5]\, addr_data_f0(4) => - \addr_data_f0[4]\, addr_data_f0(3) => \addr_data_f0[3]\, - addr_data_f0(2) => \addr_data_f0[2]\, addr_data_f0(1) => - \addr_data_f0[1]\, addr_data_f0(0) => \addr_data_f0[0]\, - delta_f2_f0(9) => \delta_f2_f0[9]\, delta_f2_f0(8) => - \delta_f2_f0[8]\, delta_f2_f0(7) => \delta_f2_f0[7]\, - delta_f2_f0(6) => \delta_f2_f0[6]\, delta_f2_f0(5) => - \delta_f2_f0[5]\, delta_f2_f0(4) => \delta_f2_f0[4]\, - delta_f2_f0(3) => \delta_f2_f0[3]\, delta_f2_f0(2) => - \delta_f2_f0[2]\, delta_f2_f0(1) => \delta_f2_f0[1]\, - delta_f2_f0(0) => \delta_f2_f0[0]\, delta_snapshot(15) - => \delta_snapshot[15]\, delta_snapshot(14) => - \delta_snapshot[14]\, delta_snapshot(13) => - \delta_snapshot[13]\, delta_snapshot(12) => - \delta_snapshot[12]\, delta_snapshot(11) => - \delta_snapshot[11]\, delta_snapshot(10) => - \delta_snapshot[10]\, delta_snapshot(9) => - \delta_snapshot[9]\, delta_snapshot(8) => - \delta_snapshot[8]\, delta_snapshot(7) => - \delta_snapshot[7]\, delta_snapshot(6) => - \delta_snapshot[6]\, delta_snapshot(5) => - \delta_snapshot[5]\, delta_snapshot(4) => - \delta_snapshot[4]\, delta_snapshot(3) => - \delta_snapshot[3]\, delta_snapshot(2) => - \delta_snapshot[2]\, delta_snapshot(1) => - \delta_snapshot[1]\, delta_snapshot(0) => - \delta_snapshot[0]\, nb_snapshot_param(10) => - \nb_snapshot_param[10]\, nb_snapshot_param(9) => - \nb_snapshot_param[9]\, nb_snapshot_param(8) => - \nb_snapshot_param[8]\, nb_snapshot_param(7) => - \nb_snapshot_param[7]\, nb_snapshot_param(6) => - \nb_snapshot_param[6]\, nb_snapshot_param(5) => - \nb_snapshot_param[5]\, nb_snapshot_param(4) => - \nb_snapshot_param[4]\, nb_snapshot_param(3) => - \nb_snapshot_param[3]\, nb_snapshot_param(2) => - \nb_snapshot_param[2]\, nb_snapshot_param(1) => - \nb_snapshot_param[1]\, nb_snapshot_param(0) => - \nb_snapshot_param[0]\, apbi_c_81 => \apbi_c[81]\, - apbi_c_80 => \apbi_c[80]\, apbi_c_79 => \apbi_c[79]\, - apbi_c_78 => \apbi_c[78]\, apbi_c_77 => \apbi_c[77]\, - apbi_c_76 => \apbi_c[76]\, apbi_c_75 => \apbi_c[75]\, - apbi_c_74 => \apbi_c[74]\, apbi_c_73 => \apbi_c[73]\, - apbi_c_72 => \apbi_c[72]\, apbi_c_71 => \apbi_c[71]\, - apbi_c_70 => \apbi_c[70]\, apbi_c_69 => \apbi_c[69]\, - apbi_c_68 => \apbi_c[68]\, apbi_c_67 => \apbi_c[67]\, - apbi_c_66 => \apbi_c[66]\, apbi_c_65 => \apbi_c[65]\, - apbi_c_64 => \apbi_c[64]\, apbi_c_63 => \apbi_c[63]\, - apbi_c_62 => \apbi_c[62]\, apbi_c_61 => \apbi_c[61]\, - apbi_c_60 => \apbi_c[60]\, apbi_c_59 => \apbi_c[59]\, - apbi_c_58 => \apbi_c[58]\, apbi_c_57 => \apbi_c[57]\, - apbi_c_56 => \apbi_c[56]\, apbi_c_55 => \apbi_c[55]\, - apbi_c_24 => \apbi_c[24]\, apbi_c_23 => \apbi_c[23]\, - apbi_c_0 => \apbi_c[0]\, apbi_c_50 => \apbi_c[50]\, - apbi_c_51 => \apbi_c[51]\, apbi_c_52 => \apbi_c[52]\, - apbi_c_16 => \apbi_c[16]\, apbi_c_49 => \apbi_c[49]\, - apbi_c_22 => \apbi_c[22]\, apbi_c_20 => \apbi_c[20]\, - apbi_c_19 => \apbi_c[19]\, apbi_c_21 => \apbi_c[21]\, - apbi_c_54 => \apbi_c[54]\, apbi_c_53 => \apbi_c[53]\, - data_shaping_R0 => data_shaping_R0, data_shaping_R1 => - data_shaping_R1, enable_f0 => enable_f0, - data_shaping_BW_c => data_shaping_BW_c, burst_f2 => - burst_f2, burst_f1 => burst_f1, burst_f0 => burst_f0, - enable_f3 => enable_f3, enable_f2 => enable_f2, - data_shaping_SP1 => data_shaping_SP1, enable_f1 => - enable_f1, data_shaping_SP0 => data_shaping_SP0, - data_shaping_R1_0 => data_shaping_R1_0, HRESETn_c => - HRESETn_c, HCLK_c => HCLK_c, data_shaping_R0_0 => - data_shaping_R0_0); - - \AHB_Master_Out_pad[78]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[31]\, PAD => - AHB_Master_Out(78)); - - \AHB_Master_Out_pad[271]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(271)); - - cnv_pad : OUTBUF - port map(D => cnv_c, PAD => cnv); - - \AHB_Master_Out_pad[302]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(302)); - - \AHB_Master_Out_pad[88]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(88)); - - \AHB_Master_Out_pad[363]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(363)); - - \AHB_Master_Out_pad[218]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(218)); - - \AHB_Master_Out_pad[197]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(197)); - - \apbo_pad[104]\ : OUTBUF - port map(D => \GND\, PAD => apbo(104)); - - \AHB_Master_Out_pad[70]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[23]\, PAD => - AHB_Master_Out(70)); - - \AHB_Master_Out_pad[228]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(228)); - - \AHB_Master_Out_pad[248]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(248)); - - \AHB_Master_Out_pad[285]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(285)); - - \sdo_pad[3]\ : INBUF - port map(PAD => sdo(3), Y => \sdo_c[3]\); - - \AHB_Master_Out_pad[80]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(80)); - - \AHB_Master_Out_pad[309]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(309)); - - VCC_i : VCC - port map(Y => \VCC\); - - \apbo_pad[82]\ : OUTBUF - port map(D => \GND\, PAD => apbo(82)); - - \apbi_pad[67]\ : INBUF - port map(PAD => apbi(67), Y => \apbi_c[67]\); - - \AHB_Master_Out_pad[119]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(119)); - - \apbo_pad[0]\ : OUTBUF - port map(D => \apbo.prdata_c[0]\, PAD => apbo(0)); - - \AHB_Master_Out_pad[129]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(129)); - - \AHB_Master_Out_pad[149]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(149)); - - \AHB_Master_Out_pad[58]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[11]\, PAD => - AHB_Master_Out(58)); - - \AHB_Master_Out_pad[270]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(270)); - - \AHB_Master_Out_pad[268]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(268)); - - \AHB_Master_Out_pad[251]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(251)); - - \AHB_Master_Out_pad[237]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(237)); - - \AHB_Master_Out_pad[175]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(175)); - - \AHB_Master_Out_pad[11]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[7]\, PAD => - AHB_Master_Out(11)); - - \apbi_pad[63]\ : INBUF - port map(PAD => apbi(63), Y => \apbi_c[63]\); - - \AHB_Master_Out_pad[76]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[29]\, PAD => - AHB_Master_Out(76)); - - \AHB_Master_Out_pad[357]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(357)); - - \apbo_pad[80]\ : OUTBUF - port map(D => \GND\, PAD => apbo(80)); - - \AHB_Master_Out_pad[44]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(44)); - - \AHB_Master_Out_pad[310]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(310)); - - \AHB_Master_Out_pad[86]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(86)); - - \AHB_Master_Out_pad[50]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[3]\, PAD => - AHB_Master_Out(50)); - - \AHB_Master_Out_pad[320]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(320)); - - \AHB_Master_Out_pad[239]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(239)); - - \AHB_Master_Out_pad[202]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(202)); - - \sdo_pad[5]\ : INBUF - port map(PAD => sdo(5), Y => \sdo_c[5]\); - - lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip - port map(nb_snapshot_param(10) => \nb_snapshot_param[10]\, - nb_snapshot_param(9) => \nb_snapshot_param[9]\, - nb_snapshot_param(8) => \nb_snapshot_param[8]\, - nb_snapshot_param(7) => \nb_snapshot_param[7]\, - nb_snapshot_param(6) => \nb_snapshot_param[6]\, - nb_snapshot_param(5) => \nb_snapshot_param[5]\, - nb_snapshot_param(4) => \nb_snapshot_param[4]\, - nb_snapshot_param(3) => \nb_snapshot_param[3]\, - nb_snapshot_param(2) => \nb_snapshot_param[2]\, - nb_snapshot_param(1) => \nb_snapshot_param[1]\, - nb_snapshot_param(0) => \nb_snapshot_param[0]\, - delta_f2_f0(9) => \delta_f2_f0[9]\, delta_f2_f0(8) => - \delta_f2_f0[8]\, delta_f2_f0(7) => \delta_f2_f0[7]\, - delta_f2_f0(6) => \delta_f2_f0[6]\, delta_f2_f0(5) => - \delta_f2_f0[5]\, delta_f2_f0(4) => \delta_f2_f0[4]\, - delta_f2_f0(3) => \delta_f2_f0[3]\, delta_f2_f0(2) => - \delta_f2_f0[2]\, delta_f2_f0(1) => \delta_f2_f0[1]\, - delta_f2_f0(0) => \delta_f2_f0[0]\, delta_snapshot(15) - => \delta_snapshot[15]\, delta_snapshot(14) => - \delta_snapshot[14]\, delta_snapshot(13) => - \delta_snapshot[13]\, delta_snapshot(12) => - \delta_snapshot[12]\, delta_snapshot(11) => - \delta_snapshot[11]\, delta_snapshot(10) => - \delta_snapshot[10]\, delta_snapshot(9) => - \delta_snapshot[9]\, delta_snapshot(8) => - \delta_snapshot[8]\, delta_snapshot(7) => - \delta_snapshot[7]\, delta_snapshot(6) => - \delta_snapshot[6]\, delta_snapshot(5) => - \delta_snapshot[5]\, delta_snapshot(4) => - \delta_snapshot[4]\, delta_snapshot(3) => - \delta_snapshot[3]\, delta_snapshot(2) => - \delta_snapshot[2]\, delta_snapshot(1) => - \delta_snapshot[1]\, delta_snapshot(0) => - \delta_snapshot[0]\, delta_f2_f1(9) => \delta_f2_f1[9]\, - delta_f2_f1(8) => \delta_f2_f1[8]\, delta_f2_f1(7) => - \delta_f2_f1[7]\, delta_f2_f1(6) => \delta_f2_f1[6]\, - delta_f2_f1(5) => \delta_f2_f1[5]\, delta_f2_f1(4) => - \delta_f2_f1[4]\, delta_f2_f1(3) => \delta_f2_f1[3]\, - delta_f2_f1(2) => \delta_f2_f1[2]\, delta_f2_f1(1) => - \delta_f2_f1[1]\, delta_f2_f1(0) => \delta_f2_f1[0]\, - status_new_err(3) => \status_new_err[3]\, - status_new_err(2) => \status_new_err[2]\, - status_new_err(1) => \status_new_err[1]\, - status_new_err(0) => \status_new_err[0]\, hwdata_c(31) - => \AHB_Master_Out.hwdata_c[31]\, hwdata_c(30) => - \AHB_Master_Out.hwdata_c[30]\, hwdata_c(29) => - \AHB_Master_Out.hwdata_c[29]\, hwdata_c(28) => - \AHB_Master_Out.hwdata_c[28]\, hwdata_c(27) => - \AHB_Master_Out.hwdata_c[27]\, hwdata_c(26) => - \AHB_Master_Out.hwdata_c[26]\, hwdata_c(25) => - \AHB_Master_Out.hwdata_c[25]\, hwdata_c(24) => - \AHB_Master_Out.hwdata_c[24]\, hwdata_c(23) => - \AHB_Master_Out.hwdata_c[23]\, hwdata_c(22) => - \AHB_Master_Out.hwdata_c[22]\, hwdata_c(21) => - \AHB_Master_Out.hwdata_c[21]\, hwdata_c(20) => - \AHB_Master_Out.hwdata_c[20]\, hwdata_c(19) => - \AHB_Master_Out.hwdata_c[19]\, hwdata_c(18) => - \AHB_Master_Out.hwdata_c[18]\, hwdata_c(17) => - \AHB_Master_Out.hwdata_c[17]\, hwdata_c(16) => - \AHB_Master_Out.hwdata_c[16]\, hwdata_c(15) => - \AHB_Master_Out.hwdata_c[15]\, hwdata_c(14) => - \AHB_Master_Out.hwdata_c[14]\, hwdata_c(13) => - \AHB_Master_Out.hwdata_c[13]\, hwdata_c(12) => - \AHB_Master_Out.hwdata_c[12]\, hwdata_c(11) => - \AHB_Master_Out.hwdata_c[11]\, hwdata_c(10) => - \AHB_Master_Out.hwdata_c[10]\, hwdata_c(9) => - \AHB_Master_Out.hwdata_c[9]\, hwdata_c(8) => - \AHB_Master_Out.hwdata_c[8]\, hwdata_c(7) => - \AHB_Master_Out.hwdata_c[7]\, hwdata_c(6) => - \AHB_Master_Out.hwdata_c[6]\, hwdata_c(5) => - \AHB_Master_Out.hwdata_c[5]\, hwdata_c(4) => - \AHB_Master_Out.hwdata_c[4]\, hwdata_c(3) => - \AHB_Master_Out.hwdata_c[3]\, hwdata_c(2) => - \AHB_Master_Out.hwdata_c[2]\, hwdata_c(1) => - \AHB_Master_Out.hwdata_c[1]\, hwdata_c(0) => - \AHB_Master_Out.hwdata_c[0]\, addr_data_f0(31) => - \addr_data_f0[31]\, addr_data_f0(30) => - \addr_data_f0[30]\, addr_data_f0(29) => - \addr_data_f0[29]\, addr_data_f0(28) => - \addr_data_f0[28]\, addr_data_f0(27) => - \addr_data_f0[27]\, addr_data_f0(26) => - \addr_data_f0[26]\, addr_data_f0(25) => - \addr_data_f0[25]\, addr_data_f0(24) => - \addr_data_f0[24]\, addr_data_f0(23) => - \addr_data_f0[23]\, addr_data_f0(22) => - \addr_data_f0[22]\, addr_data_f0(21) => - \addr_data_f0[21]\, addr_data_f0(20) => - \addr_data_f0[20]\, addr_data_f0(19) => - \addr_data_f0[19]\, addr_data_f0(18) => - \addr_data_f0[18]\, addr_data_f0(17) => - \addr_data_f0[17]\, addr_data_f0(16) => - \addr_data_f0[16]\, addr_data_f0(15) => - \addr_data_f0[15]\, addr_data_f0(14) => - \addr_data_f0[14]\, addr_data_f0(13) => - \addr_data_f0[13]\, addr_data_f0(12) => - \addr_data_f0[12]\, addr_data_f0(11) => - \addr_data_f0[11]\, addr_data_f0(10) => - \addr_data_f0[10]\, addr_data_f0(9) => \addr_data_f0[9]\, - addr_data_f0(8) => \addr_data_f0[8]\, addr_data_f0(7) => - \addr_data_f0[7]\, addr_data_f0(6) => \addr_data_f0[6]\, - addr_data_f0(5) => \addr_data_f0[5]\, addr_data_f0(4) => - \addr_data_f0[4]\, addr_data_f0(3) => \addr_data_f0[3]\, - addr_data_f0(2) => \addr_data_f0[2]\, addr_data_f0(1) => - \addr_data_f0[1]\, addr_data_f0(0) => \addr_data_f0[0]\, - addr_data_f1(31) => \addr_data_f1[31]\, addr_data_f1(30) - => \addr_data_f1[30]\, addr_data_f1(29) => - \addr_data_f1[29]\, addr_data_f1(28) => - \addr_data_f1[28]\, addr_data_f1(27) => - \addr_data_f1[27]\, addr_data_f1(26) => - \addr_data_f1[26]\, addr_data_f1(25) => - \addr_data_f1[25]\, addr_data_f1(24) => - \addr_data_f1[24]\, addr_data_f1(23) => - \addr_data_f1[23]\, addr_data_f1(22) => - \addr_data_f1[22]\, addr_data_f1(21) => - \addr_data_f1[21]\, addr_data_f1(20) => - \addr_data_f1[20]\, addr_data_f1(19) => - \addr_data_f1[19]\, addr_data_f1(18) => - \addr_data_f1[18]\, addr_data_f1(17) => - \addr_data_f1[17]\, addr_data_f1(16) => - \addr_data_f1[16]\, addr_data_f1(15) => - \addr_data_f1[15]\, addr_data_f1(14) => - \addr_data_f1[14]\, addr_data_f1(13) => - \addr_data_f1[13]\, addr_data_f1(12) => - \addr_data_f1[12]\, addr_data_f1(11) => - \addr_data_f1[11]\, addr_data_f1(10) => - \addr_data_f1[10]\, addr_data_f1(9) => \addr_data_f1[9]\, - addr_data_f1(8) => \addr_data_f1[8]\, addr_data_f1(7) => - \addr_data_f1[7]\, addr_data_f1(6) => \addr_data_f1[6]\, - addr_data_f1(5) => \addr_data_f1[5]\, addr_data_f1(4) => - \addr_data_f1[4]\, addr_data_f1(3) => \addr_data_f1[3]\, - addr_data_f1(2) => \addr_data_f1[2]\, addr_data_f1(1) => - \addr_data_f1[1]\, addr_data_f1(0) => \addr_data_f1[0]\, - addr_data_f2(31) => \addr_data_f2[31]\, addr_data_f2(30) - => \addr_data_f2[30]\, addr_data_f2(29) => - \addr_data_f2[29]\, addr_data_f2(28) => - \addr_data_f2[28]\, addr_data_f2(27) => - \addr_data_f2[27]\, addr_data_f2(26) => - \addr_data_f2[26]\, addr_data_f2(25) => - \addr_data_f2[25]\, addr_data_f2(24) => - \addr_data_f2[24]\, addr_data_f2(23) => - \addr_data_f2[23]\, addr_data_f2(22) => - \addr_data_f2[22]\, addr_data_f2(21) => - \addr_data_f2[21]\, addr_data_f2(20) => - \addr_data_f2[20]\, addr_data_f2(19) => - \addr_data_f2[19]\, addr_data_f2(18) => - \addr_data_f2[18]\, addr_data_f2(17) => - \addr_data_f2[17]\, addr_data_f2(16) => - \addr_data_f2[16]\, addr_data_f2(15) => - \addr_data_f2[15]\, addr_data_f2(14) => - \addr_data_f2[14]\, addr_data_f2(13) => - \addr_data_f2[13]\, addr_data_f2(12) => - \addr_data_f2[12]\, addr_data_f2(11) => - \addr_data_f2[11]\, addr_data_f2(10) => - \addr_data_f2[10]\, addr_data_f2(9) => \addr_data_f2[9]\, - addr_data_f2(8) => \addr_data_f2[8]\, addr_data_f2(7) => - \addr_data_f2[7]\, addr_data_f2(6) => \addr_data_f2[6]\, - addr_data_f2(5) => \addr_data_f2[5]\, addr_data_f2(4) => - \addr_data_f2[4]\, addr_data_f2(3) => \addr_data_f2[3]\, - addr_data_f2(2) => \addr_data_f2[2]\, addr_data_f2(1) => - \addr_data_f2[1]\, addr_data_f2(0) => \addr_data_f2[0]\, - addr_data_f3(31) => \addr_data_f3[31]\, addr_data_f3(30) - => \addr_data_f3[30]\, addr_data_f3(29) => - \addr_data_f3[29]\, addr_data_f3(28) => - \addr_data_f3[28]\, addr_data_f3(27) => - \addr_data_f3[27]\, addr_data_f3(26) => - \addr_data_f3[26]\, addr_data_f3(25) => - \addr_data_f3[25]\, addr_data_f3(24) => - \addr_data_f3[24]\, addr_data_f3(23) => - \addr_data_f3[23]\, addr_data_f3(22) => - \addr_data_f3[22]\, addr_data_f3(21) => - \addr_data_f3[21]\, addr_data_f3(20) => - \addr_data_f3[20]\, addr_data_f3(19) => - \addr_data_f3[19]\, addr_data_f3(18) => - \addr_data_f3[18]\, addr_data_f3(17) => - \addr_data_f3[17]\, addr_data_f3(16) => - \addr_data_f3[16]\, addr_data_f3(15) => - \addr_data_f3[15]\, addr_data_f3(14) => - \addr_data_f3[14]\, addr_data_f3(13) => - \addr_data_f3[13]\, addr_data_f3(12) => - \addr_data_f3[12]\, addr_data_f3(11) => - \addr_data_f3[11]\, addr_data_f3(10) => - \addr_data_f3[10]\, addr_data_f3(9) => \addr_data_f3[9]\, - addr_data_f3(8) => \addr_data_f3[8]\, addr_data_f3(7) => - \addr_data_f3[7]\, addr_data_f3(6) => \addr_data_f3[6]\, - addr_data_f3(5) => \addr_data_f3[5]\, addr_data_f3(4) => - \addr_data_f3[4]\, addr_data_f3(3) => \addr_data_f3[3]\, - addr_data_f3(2) => \addr_data_f3[2]\, addr_data_f3(1) => - \addr_data_f3[1]\, addr_data_f3(0) => \addr_data_f3[0]\, - status_full(3) => \status_full[3]\, status_full(2) => - \status_full[2]\, status_full(1) => \status_full[1]\, - status_full(0) => \status_full[0]\, status_full_err(3) - => \status_full_err[3]\, status_full_err(2) => - \status_full_err[2]\, status_full_err(1) => - \status_full_err[1]\, status_full_err(0) => - \status_full_err[0]\, nb_burst_available(10) => - \nb_burst_available[10]\, nb_burst_available(9) => - \nb_burst_available[9]\, nb_burst_available(8) => - \nb_burst_available[8]\, nb_burst_available(7) => - \nb_burst_available[7]\, nb_burst_available(6) => - \nb_burst_available[6]\, nb_burst_available(5) => - \nb_burst_available[5]\, nb_burst_available(4) => - \nb_burst_available[4]\, nb_burst_available(3) => - \nb_burst_available[3]\, nb_burst_available(2) => - \nb_burst_available[2]\, nb_burst_available(1) => - \nb_burst_available[1]\, nb_burst_available(0) => - \nb_burst_available[0]\, haddr_c(31) => - \AHB_Master_Out.haddr_c[31]\, haddr_c(30) => - \AHB_Master_Out.haddr_c[30]\, haddr_c(29) => - \AHB_Master_Out.haddr_c[29]\, haddr_c(28) => - \AHB_Master_Out.haddr_c[28]\, haddr_c(27) => - \AHB_Master_Out.haddr_c[27]\, haddr_c(26) => - \AHB_Master_Out.haddr_c[26]\, haddr_c(25) => - \AHB_Master_Out.haddr_c[25]\, haddr_c(24) => - \AHB_Master_Out.haddr_c[24]\, haddr_c(23) => - \AHB_Master_Out.haddr_c[23]\, haddr_c(22) => - \AHB_Master_Out.haddr_c[22]\, haddr_c(21) => - \AHB_Master_Out.haddr_c[21]\, haddr_c(20) => - \AHB_Master_Out.haddr_c[20]\, haddr_c(19) => - \AHB_Master_Out.haddr_c[19]\, haddr_c(18) => - \AHB_Master_Out.haddr_c[18]\, haddr_c(17) => - \AHB_Master_Out.haddr_c[17]\, haddr_c(16) => - \AHB_Master_Out.haddr_c[16]\, haddr_c(15) => - \AHB_Master_Out.haddr_c[15]\, haddr_c(14) => - \AHB_Master_Out.haddr_c[14]\, haddr_c(13) => - \AHB_Master_Out.haddr_c[13]\, haddr_c(12) => - \AHB_Master_Out.haddr_c[12]\, haddr_c(11) => - \AHB_Master_Out.haddr_c[11]\, haddr_c(10) => - \AHB_Master_Out.haddr_c[10]\, haddr_c(9) => - \AHB_Master_Out.haddr_c[9]\, haddr_c(8) => - \AHB_Master_Out.haddr_c[8]\, haddr_c(7) => - \AHB_Master_Out.haddr_c[7]\, haddr_c(6) => - \AHB_Master_Out.haddr_c[6]\, haddr_c(5) => - \AHB_Master_Out.haddr_c[5]\, haddr_c(4) => - \AHB_Master_Out.haddr_c[4]\, haddr_c(3) => - \AHB_Master_Out.haddr_c[3]\, haddr_c(2) => - \AHB_Master_Out.haddr_c[2]\, haddr_c(1) => - \AHB_Master_Out.haddr_c[1]\, haddr_c(0) => - \AHB_Master_Out.haddr_c[0]\, AHB_Master_In_c_3 => - \AHB_Master_In_c[16]\, AHB_Master_In_c_0 => - \AHB_Master_In_c[13]\, AHB_Master_In_c_4 => - \AHB_Master_In_c[17]\, AHB_Master_In_c_5 => - \AHB_Master_In_c[18]\, hsize_c(1) => - \AHB_Master_Out.hsize_c[1]\, hsize_c(0) => - \AHB_Master_Out.hsize_c[0]\, htrans_c(1) => - \AHB_Master_Out.htrans_c[1]\, htrans_c(0) => - \AHB_Master_Out.htrans_c[0]\, hburst_c(2) => - \AHB_Master_Out.hburst_c[2]\, hburst_c(1) => - \AHB_Master_Out.hburst_c[1]\, hburst_c(0) => - \AHB_Master_Out.hburst_c[0]\, status_full_ack(3) => - \status_full_ack[3]\, status_full_ack(2) => - \status_full_ack[2]\, status_full_ack(1) => - \status_full_ack[1]\, status_full_ack(0) => - \status_full_ack[0]\, sdo_c(7) => \sdo_c[7]\, sdo_c(6) - => \sdo_c[6]\, sdo_c(5) => \sdo_c[5]\, sdo_c(4) => - \sdo_c[4]\, sdo_c(3) => \sdo_c[3]\, sdo_c(2) => - \sdo_c[2]\, sdo_c(1) => \sdo_c[1]\, sdo_c(0) => - \sdo_c[0]\, coarse_time_0_c => coarse_time_0_c, enable_f0 - => enable_f0, data_shaping_R0 => data_shaping_R0, - data_shaping_R0_0 => data_shaping_R0_0, burst_f0 => - burst_f0, data_shaping_R1 => data_shaping_R1, - data_shaping_R1_0 => data_shaping_R1_0, enable_f1 => - enable_f1, burst_f1 => burst_f1, enable_f2 => enable_f2, - burst_f2 => burst_f2, enable_f3 => enable_f3, N_43 => - \lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.N_43\, - IdlePhase_RNI03G71 => IdlePhase_RNI03G71, hwrite_c => - \AHB_Master_Out.hwrite_c\, lpp_top_lfr_wf_picker_ip_GND - => \GND\, lpp_top_lfr_wf_picker_ip_VCC => \VCC\, - cnv_run_c => cnv_run_c, sck_c => sck_c, cnv_c => cnv_c, - cnv_clk_c => cnv_clk_c, cnv_rstn_c => cnv_rstn_c, - data_shaping_SP0 => data_shaping_SP0, data_shaping_SP1 - => data_shaping_SP1, HRESETn_c => HRESETn_c, HCLK_c => - HCLK_c); - - \apbo_pad[38]\ : OUTBUF - port map(D => \GND\, PAD => apbo(38)); - - \AHB_Master_Out_pad[340]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(340)); - - \AHB_Master_Out_pad[169]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(169)); - - \apbi_pad[58]\ : INBUF - port map(PAD => apbi(58), Y => \apbi_c[58]\); - - \AHB_Master_Out_pad[77]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[30]\, PAD => - AHB_Master_Out(77)); - - \apbo_pad[28]\ : OUTBUF - port map(D => \apbo.prdata_c[28]\, PAD => apbo(28)); - - \AHB_Master_Out_pad[104]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(104)); - - \AHB_Master_Out_pad[351]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(351)); - - \AHB_Master_Out_pad[276]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(276)); - - \apbo_pad[118]\ : OUTBUF - port map(D => \GND\, PAD => apbo(118)); - - \AHB_Master_Out_pad[87]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(87)); - - \AHB_Master_Out_pad[79]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(79)); - - \AHB_Master_Out_pad[178]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(178)); - - \AHB_Master_Out_pad[130]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(130)); - - \apbo_pad[81]\ : OUTBUF - port map(D => \GND\, PAD => apbo(81)); - - \AHB_Master_Out_pad[291]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(291)); - - \apbo_pad[85]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(85)); - - \apbo_pad[97]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(97)); - - \apbo_pad[68]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(68)); - - \AHB_Master_Out_pad[89]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(89)); - - \AHB_Master_Out_pad[360]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(360)); - - \AHB_Master_Out_pad[305]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(305)); - - \AHB_Master_Out_pad[136]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(136)); - - \AHB_Master_Out_pad[56]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[9]\, PAD => - AHB_Master_Out(56)); - - \apbo_pad[130]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(130)); - - \AHB_Master_Out_pad[250]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(250)); - - \apbo_pad[1]\ : OUTBUF - port map(D => \apbo.prdata_c[1]\, PAD => apbo(1)); - - \AHB_Master_Out_pad[155]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(155)); - - \apbo_pad[8]\ : OUTBUF - port map(D => \apbo.prdata_c[8]\, PAD => apbo(8)); - - \AHB_Master_Out_pad[112]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(112)); - - \AHB_Master_Out_pad[43]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(43)); - - \AHB_Master_Out_pad[122]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(122)); - - \apbo_pad[93]\ : OUTBUF - port map(D => \GND\, PAD => apbo(93)); - - \AHB_Master_Out_pad[57]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[10]\, PAD => - AHB_Master_Out(57)); - - \AHB_Master_Out_pad[287]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(287)); - - \AHB_Master_Out_pad[142]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(142)); - - \apbo_pad[123]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(123)); - - \AHB_Master_Out_pad[59]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[12]\, PAD => - AHB_Master_Out(59)); - - \AHB_Master_Out_pad[289]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(289)); - - \AHB_Master_Out_pad[256]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(256)); - - \AHB_Master_Out_pad[95]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(95)); - - \AHB_Master_Out_pad[312]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(312)); - - \apbo_pad[107]\ : OUTBUF - port map(D => \GND\, PAD => apbo(107)); - - \AHB_Master_Out_pad[322]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(322)); - - \AHB_Master_Out_pad[158]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(158)); - - \AHB_Master_Out_pad[342]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(342)); - - \AHB_Master_Out_pad[290]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(290)); - - \AHB_Master_Out_pad[103]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(103)); - - \apbo_pad[36]\ : OUTBUF - port map(D => \GND\, PAD => apbo(36)); - - \apbi_pad[16]\ : INBUF - port map(PAD => apbi(16), Y => \apbi_c[16]\); - - \AHB_Master_Out_pad[68]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[21]\, PAD => - AHB_Master_Out(68)); - - \AHB_Master_Out_pad[195]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(195)); - - \AHB_Master_Out_pad[21]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[17]\, PAD => - AHB_Master_Out(21)); - - \apbi_pad[56]\ : INBUF - port map(PAD => apbi(56), Y => \apbi_c[56]\); - - \AHB_Master_Out_pad[162]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(162)); - - \apbo_pad[72]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(72)); - - \apbo_pad[26]\ : OUTBUF - port map(D => \apbo.prdata_c[26]\, PAD => apbo(26)); - - \apbi_pad[79]\ : INBUF - port map(PAD => apbi(79), Y => \apbi_c[79]\); - - \AHB_Master_Out_pad[180]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(180)); - - \AHB_Master_Out_pad[278]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(278)); - - \AHB_Master_Out_pad[319]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(319)); - - \AHB_Master_Out_pad[329]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(329)); - - \apbo_pad[111]\ : OUTBUF - port map(D => \GND\, PAD => apbo(111)); - - \AHB_Master_Out_pad[60]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[13]\, PAD => - AHB_Master_Out(60)); - - \AHB_Master_Out_pad[349]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(349)); - - \AHB_Master_Out_pad[186]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(186)); - - \apbo_pad[19]\ : OUTBUF - port map(D => \apbo.prdata_c[19]\, PAD => apbo(19)); - - \AHB_Master_Out_pad[92]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(92)); - - \AHB_Master_Out_pad[296]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(296)); - - \apbo_pad[66]\ : OUTBUF - port map(D => \GND\, PAD => apbo(66)); - - \AHB_Master_Out_pad[362]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(362)); - - \AHB_Master_Out_pad[353]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(353)); - - \AHB_Master_Out_pad[306]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(306)); - - \AHB_Master_Out_pad[179]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(179)); - - \apbo_pad[70]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(70)); - - \apbi_pad[22]\ : INBUF - port map(PAD => apbi(22), Y => \apbi_c[22]\); - - \AHB_Master_Out_pad[198]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(198)); - - \apbo_pad[115]\ : OUTBUF - port map(D => \GND\, PAD => apbo(115)); - - \AHB_Master_Out_pad[38]\ : OUTBUF - port map(D => \AHB_Master_Out.hsize_c[1]\, PAD => - AHB_Master_Out(38)); - - \AHB_Master_Out_pad[369]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(369)); - - \AHB_Master_Out_pad[212]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(212)); - - \AHB_Master_Out_pad[222]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(222)); - - \AHB_Master_Out_pad[66]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[19]\, PAD => - AHB_Master_Out(66)); - - \AHB_Master_Out_pad[242]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(242)); - - \apbi_pad[20]\ : INBUF - port map(PAD => apbi(20), Y => \apbi_c[20]\); - - \AHB_Master_Out_pad[370]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(370)); - - \apbo_pad[34]\ : OUTBUF - port map(D => \GND\, PAD => apbo(34)); - - \AHB_Master_Out_pad[114]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(114)); - - \apbo_pad[49]\ : OUTBUF - port map(D => \GND\, PAD => apbo(49)); - - \AHB_Master_Out_pad[124]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(124)); - - \apbo_pad[71]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(71)); - - \apbi_pad[54]\ : INBUF - port map(PAD => apbi(54), Y => \apbi_c[54]\); - - \AHB_Master_Out_pad[30]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[26]\, PAD => - AHB_Master_Out(30)); - - \AHB_Master_Out_pad[258]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(258)); - - \AHB_Master_Out_pad[144]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(144)); - - \apbo_pad[75]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(75)); - - \apbo_pad[24]\ : OUTBUF - port map(D => \apbo.prdata_c[24]\, PAD => apbo(24)); - - \AHB_Master_Out_pad[67]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[20]\, PAD => - AHB_Master_Out(67)); - - \apbo_pad[114]\ : OUTBUF - port map(D => \GND\, PAD => apbo(114)); - - \AHB_Master_Out_pad[304]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(304)); - - \apbo_pad[3]\ : OUTBUF - port map(D => \apbo.prdata_c[3]\, PAD => apbo(3)); - - \AHB_Master_Out_pad[315]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(315)); - - \AHB_Master_Out_pad[159]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(159)); - - \AHB_Master_Out_pad[69]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[22]\, PAD => - AHB_Master_Out(69)); - - \AHB_Master_Out_pad[325]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(325)); - - \AHB_Master_Out_pad[262]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(262)); - - \apbo_pad[64]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(64)); - - \AHB_Master_Out_pad[345]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(345)); - - \apbi_pad[21]\ : INBUF - port map(PAD => apbi(21), Y => \apbi_c[21]\); - - \apbo_pad[88]\ : OUTBUF - port map(D => \GND\, PAD => apbo(88)); - - \AHB_Master_Out_pad[164]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(164)); - - \apbo_pad[2]\ : OUTBUF - port map(D => \apbo.prdata_c[2]\, PAD => apbo(2)); - - \AHB_Master_Out_pad[36]\ : OUTBUF - port map(D => \AHB_Master_Out.hwrite_c\, PAD => - AHB_Master_Out(36)); - - \AHB_Master_Out_pad[338]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(338)); - - \AHB_Master_Out_pad[298]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(298)); - - \AHB_Master_Out_pad[75]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[28]\, PAD => - AHB_Master_Out(75)); - - \AHB_Master_Out_pad[172]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(172)); - - \AHB_Master_Out_pad[350]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(350)); - - \apbo_pad[100]\ : OUTBUF - port map(D => \GND\, PAD => apbo(100)); - - \AHB_Master_Out_pad[85]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(85)); - - \AHB_Master_Out_pad[205]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(205)); - - \sdo_pad[7]\ : INBUF - port map(PAD => sdo(7), Y => \sdo_c[7]\); - - \apbo_pad[52]\ : OUTBUF - port map(D => \GND\, PAD => apbo(52)); - - \AHB_Master_Out_pad[37]\ : OUTBUF - port map(D => \AHB_Master_Out.hsize_c[0]\, PAD => - AHB_Master_Out(37)); - - \AHB_Master_Out_pad[365]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(365)); - - \AHB_Master_Out_pad[199]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(199)); - - \apbi_pad[69]\ : INBUF - port map(PAD => apbi(69), Y => \apbi_c[69]\); - - \AHB_Master_Out_pad[113]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(113)); - - \AHB_Master_Out_pad[234]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(234)); - - \AHB_Master_Out_pad[123]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(123)); - - \apbo_pad[129]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(129)); - - \AHB_Master_Out_pad[39]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(39)); - - \AHB_Master_Out_pad[143]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(143)); - - HRESETn_pad : CLKBUF - port map(PAD => HRESETn, Y => HRESETn_c); - - \AHB_Master_Out_pad[94]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(94)); - - \AHB_Master_Out_pad[72]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[25]\, PAD => - AHB_Master_Out(72)); - - \AHB_Master_Out_pad[41]\ : OUTBUF - port map(D => \AHB_Master_Out.hburst_c[1]\, PAD => - AHB_Master_Out(41)); - - \apbo_pad[50]\ : OUTBUF - port map(D => \GND\, PAD => apbo(50)); - - \AHB_Master_Out_pad[233]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(233)); - - \AHB_Master_Out_pad[131]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(131)); - - \AHB_Master_Out_pad[8]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[4]\, PAD => - AHB_Master_Out(8)); - - \AHB_Master_Out_pad[82]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(82)); - - \AHB_Master_Out_pad[55]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[8]\, PAD => - AHB_Master_Out(55)); - - \AHB_Master_Out_pad[316]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(316)); - - \AHB_Master_Out_pad[326]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(326)); - - \AHB_Master_Out_pad[163]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(163)); - - \AHB_Master_Out_pad[152]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(152)); - - \AHB_Master_Out_pad[346]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(346)); - - GND_i_0 : GND - port map(Y => GND_0); - - \apbo_pad[86]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(86)); - - \sdo_pad[0]\ : INBUF - port map(PAD => sdo(0), Y => \sdo_c[0]\); - - \apbo_pad[51]\ : OUTBUF - port map(D => \GND\, PAD => apbo(51)); - - \apbo_pad[37]\ : OUTBUF - port map(D => \GND\, PAD => apbo(37)); - - \apbo_pad[55]\ : OUTBUF - port map(D => \GND\, PAD => apbo(55)); - - \apbi_pad[57]\ : INBUF - port map(PAD => apbi(57), Y => \apbi_c[57]\); - - \apbo_pad[27]\ : OUTBUF - port map(D => \apbo.prdata_c[27]\, PAD => apbo(27)); - - \AHB_Master_Out_pad[52]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[5]\, PAD => - AHB_Master_Out(52)); - - \AHB_Master_Out_pad[352]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(352)); - - \apbo_pad[99]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(99)); - - \apbo_pad[126]\ : OUTBUF - port map(D => \GND\, PAD => apbo(126)); - - \AHB_Master_Out_pad[272]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(272)); - - \AHB_Master_Out_pad[93]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(93)); - - \AHB_Master_Out_pad[366]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(366)); - - \AHB_Master_Out_pad[284]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(284)); - - \apbo_pad[117]\ : OUTBUF - port map(D => \GND\, PAD => apbo(117)); - - \AHB_Master_Out_pad[137]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(137)); - - \apbo_pad[33]\ : OUTBUF - port map(D => \GND\, PAD => apbo(33)); - - \AHB_Master_Out_pad[192]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(192)); - - \AHB_Master_Out_pad[174]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(174)); - - \apbo_pad[122]\ : OUTBUF - port map(D => \GND\, PAD => apbo(122)); - - \apbo_pad[67]\ : OUTBUF - port map(D => \GND\, PAD => apbo(67)); - - \apbi_pad[53]\ : INBUF - port map(PAD => apbi(53), Y => \apbi_c[53]\); - - \apbo_pad[23]\ : OUTBUF - port map(D => \apbo.prdata_c[23]\, PAD => apbo(23)); - - \AHB_Master_Out_pad[359]\ : OUTBUF - port map(D => \VCC\, PAD => AHB_Master_Out(359)); - - \AHB_Master_Out_pad[314]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(314)); - - \AHB_Master_Out_pad[324]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(324)); - - \AHB_Master_Out_pad[283]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(283)); - - \AHB_Master_Out_pad[207]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(207)); - - \apbo_pad[78]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(78)); - - \AHB_Master_Out_pad[344]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(344)); - - \AHB_Master_Out_pad[181]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(181)); - - \AHB_Master_Out_pad[209]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(209)); - - \apbo_pad[63]\ : OUTBUF - port map(D => \GND\, PAD => apbo(63)); - - \apbo_pad[84]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(84)); - - \AHB_Master_Out_pad[364]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(364)); - - \AHB_Master_Out_pad[252]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(252)); - - \AHB_Master_Out_pad[100]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(100)); - - \AHB_Master_Out_pad[215]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(215)); - - \AHB_Master_Out_pad[225]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(225)); - - \AHB_Master_Out_pad[65]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[18]\, PAD => - AHB_Master_Out(65)); - - \AHB_Master_Out_pad[245]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(245)); - - \apbi_pad[0]\ : INBUF - port map(PAD => apbi(0), Y => \apbi_c[0]\); - - \AHB_Master_Out_pad[154]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(154)); - - \AHB_Master_Out_pad[74]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[27]\, PAD => - AHB_Master_Out(74)); - - \AHB_Master_Out_pad[106]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(106)); - - \AHB_Master_Out_pad[187]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(187)); - - \AHB_Master_Out_pad[84]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(84)); - - \AHB_Master_Out_pad[173]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(173)); - - \AHB_Master_Out_pad[18]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[14]\, PAD => - AHB_Master_Out(18)); - - \AHB_Master_Out_pad[231]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(231)); - - \AHB_Master_Out_pad[337]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(337)); - - \AHB_Master_Out_pad[355]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(355)); - - \AHB_Master_Out_pad[292]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(292)); - - \AHB_Master_Out_pad[265]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(265)); - - \AHB_Master_Out_pad[62]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[15]\, PAD => - AHB_Master_Out(62)); - - \apbo_pad[76]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(76)); - - \AHB_Master_Out_pad[10]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[6]\, PAD => - AHB_Master_Out(10)); - - \AHB_Master_Out_pad[9]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[5]\, PAD => - AHB_Master_Out(9)); - - \AHB_Master_Out_pad[194]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(194)); - - \AHB_Master_Out_pad[35]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[31]\, PAD => - AHB_Master_Out(35)); - - \AHB_Master_Out_pad[331]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(331)); - - \apbi_pad[72]\ : INBUF - port map(PAD => apbi(72), Y => \apbi_c[72]\); - - cnv_rstn_pad : INBUF - port map(PAD => cnv_rstn, Y => cnv_rstn_c); - - \AHB_Master_Out_pad[54]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[7]\, PAD => - AHB_Master_Out(54)); - - \apbo_pad[103]\ : OUTBUF - port map(D => \GND\, PAD => apbo(103)); - - \AHB_Master_Out_pad[73]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[26]\, PAD => - AHB_Master_Out(73)); - - \apbo_pad[9]\ : OUTBUF - port map(D => \apbo.prdata_c[9]\, PAD => apbo(9)); - - \apbo_pad[12]\ : OUTBUF - port map(D => \apbo.prdata_c[12]\, PAD => apbo(12)); - - \apbo_pad[110]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(110)); - - \AHB_Master_Out_pad[153]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(153)); - - \AHB_Master_Out_pad[83]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(83)); - - \AHB_Master_Out_pad[5]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[1]\, PAD => - AHB_Master_Out(5)); - - \AHB_Master_Out_pad[230]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(230)); - - \apbo_pad[58]\ : OUTBUF - port map(D => \GND\, PAD => apbo(58)); - - \apbi_pad[70]\ : INBUF - port map(PAD => apbi(70), Y => \apbi_c[70]\); - - \AHB_Master_Out_pad[16]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[12]\, PAD => - AHB_Master_Out(16)); - - \AHB_Master_Out_pad[135]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(135)); - - \AHB_Master_Out_pad[32]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[28]\, PAD => - AHB_Master_Out(32)); - - \AHB_Master_Out_pad[281]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(281)); - - \apbo_pad[10]\ : OUTBUF - port map(D => \apbo.prdata_c[10]\, PAD => apbo(10)); - - \AHB_Master_Out_pad[217]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(217)); - - \AHB_Master_Out_pad[227]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(227)); - - \AHB_Master_Out_pad[17]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[13]\, PAD => - AHB_Master_Out(17)); - - \AHB_Master_Out_pad[247]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(247)); - - \apbo_pad[87]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(87)); - - \apbo_pad[74]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(74)); - - \AHB_Master_Out_pad[236]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(236)); - - \AHB_Master_Out_pad[356]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(356)); - - \AHB_Master_Out_pad[219]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(219)); - - \apbo_pad[42]\ : OUTBUF - port map(D => \GND\, PAD => apbo(42)); - - \AHB_Master_Out_pad[229]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(229)); - - \AHB_Master_Out_pad[19]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[15]\, PAD => - AHB_Master_Out(19)); - - \apbi_pad[71]\ : INBUF - port map(PAD => apbi(71), Y => \apbi_c[71]\); - - \AHB_Master_Out_pad[53]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[6]\, PAD => - AHB_Master_Out(53)); - - \AHB_Master_Out_pad[249]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(249)); - - \AHB_Master_Out_pad[193]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(193)); - - \AHB_Master_Out_pad[138]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(138)); - - \apbi_pad[75]\ : INBUF - port map(PAD => apbi(75), Y => \apbi_c[75]\); - - \AHB_Master_Out_pad[28]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[24]\, PAD => - AHB_Master_Out(28)); - - \AHB_Master_Out_pad[91]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(91)); - - \apbo_pad[83]\ : OUTBUF - port map(D => \GND\, PAD => apbo(83)); - - \sdo_pad[6]\ : INBUF - port map(PAD => sdo(6), Y => \sdo_c[6]\); - - \apbo_pad[11]\ : OUTBUF - port map(D => \apbo.prdata_c[11]\, PAD => apbo(11)); - - \AHB_Master_Out_pad[110]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(110)); - - \apbo_pad[15]\ : OUTBUF - port map(D => \apbo.prdata_c[15]\, PAD => apbo(15)); - - \apbi_pad[24]\ : INBUF - port map(PAD => apbi(24), Y => \apbi_c[24]\); - - \AHB_Master_Out_pad[267]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(267)); - - \AHB_Master_Out_pad[120]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(120)); - - \AHB_Master_Out_pad[140]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(140)); - - \apbo_pad[40]\ : OUTBUF - port map(D => \GND\, PAD => apbo(40)); - - \AHB_Master_Out_pad[20]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[16]\, PAD => - AHB_Master_Out(20)); - - \AHB_Master_Out_pad[275]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(275)); - - \AHB_Master_Out_pad[116]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(116)); - - cnv_run_pad : INBUF - port map(PAD => cnv_run, Y => cnv_run_c); - - \AHB_Master_Out_pad[280]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(280)); - - \AHB_Master_Out_pad[269]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(269)); - - \AHB_Master_Out_pad[126]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(126)); - - \AHB_Master_Out_pad[185]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(185)); - - \AHB_Master_Out_pad[146]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(146)); - - \apbo_pad[128]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(128)); - - \AHB_Master_Out_pad[333]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(333)); - - \apbo_pad[56]\ : OUTBUF - port map(D => \GND\, PAD => apbo(56)); - - \apbi_pad[49]\ : INBUF - port map(PAD => apbi(49), Y => \apbi_c[49]\); - - \AHB_Master_Out_pad[64]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[17]\, PAD => - AHB_Master_Out(64)); - - \AHB_Master_Out_pad[354]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(354)); - - \AHB_Master_Out_pad[308]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(308)); - - cnv_clk_pad : INBUF - port map(PAD => cnv_clk, Y => cnv_clk_c); - - \AHB_Master_Out_pad[160]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(160)); - - \apbo_pad[41]\ : OUTBUF - port map(D => \GND\, PAD => apbo(41)); - - \apbo_pad[39]\ : OUTBUF - port map(D => \GND\, PAD => apbo(39)); - - \apbi_pad[19]\ : INBUF - port map(PAD => apbi(19), Y => \apbi_c[19]\); - - \AHB_Master_Out_pad[2]\ : OUTBUF - port map(D => \AHB_Master_Out.htrans_c[0]\, PAD => - AHB_Master_Out(2)); - - \apbo_pad[45]\ : OUTBUF - port map(D => \GND\, PAD => apbo(45)); - - \apbi_pad[62]\ : INBUF - port map(PAD => apbi(62), Y => \apbi_c[62]\); - - \AHB_Master_Out_pad[286]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(286)); - - \apbi_pad[59]\ : INBUF - port map(PAD => apbi(59), Y => \apbi_c[59]\); - - \AHB_Master_Out_pad[26]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[22]\, PAD => - AHB_Master_Out(26)); - - \apbo_pad[29]\ : OUTBUF - port map(D => \apbo.prdata_c[29]\, PAD => apbo(29)); - - \AHB_Master_Out_pad[166]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(166)); - - \AHB_Master_Out_pad[188]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(188)); - - \AHB_Master_Out_pad[238]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(238)); - - HCLK_pad : CLKBUF - port map(PAD => HCLK, Y => HCLK_c); - - \AHB_Master_Out_pad[204]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(204)); - - \AHB_Master_Out_pad[3]\ : OUTBUF - port map(D => \AHB_Master_Out.htrans_c[1]\, PAD => - AHB_Master_Out(3)); - - \AHB_Master_Out_pad[27]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[23]\, PAD => - AHB_Master_Out(27)); - - \AHB_Master_Out_pad[255]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(255)); - - \apbo_pad[69]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(69)); - - \apbi_pad[60]\ : INBUF - port map(PAD => apbi(60), Y => \apbi_c[60]\); - - \sdo_pad[2]\ : INBUF - port map(PAD => sdo(2), Y => \sdo_c[2]\); - - \AHB_Master_Out_pad[34]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[30]\, PAD => - AHB_Master_Out(34)); - - \AHB_Master_Out_pad[203]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(203)); - - \AHB_Master_Out_pad[139]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(139)); - - \AHB_Master_Out_pad[29]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[25]\, PAD => - AHB_Master_Out(29)); - - \AHB_Master_Out_pad[101]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(101)); - - \AHB_Master_Out_pad[63]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[16]\, PAD => - AHB_Master_Out(63)); - - \apbo_pad[109]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(109)); - - \apbo_pad[54]\ : OUTBUF - port map(D => \GND\, PAD => apbo(54)); - - \apbo_pad[77]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(77)); - - \apbi_pad[61]\ : INBUF - port map(PAD => apbi(61), Y => \apbi_c[61]\); - - \AHB_Master_Out_pad[330]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(330)); - - \apbo_pad[121]\ : OUTBUF - port map(D => \GND\, PAD => apbo(121)); - - \apbi_pad[65]\ : INBUF - port map(PAD => apbi(65), Y => \apbi_c[65]\); - - \AHB_Master_Out_pad[295]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(295)); - - \apbo_pad[92]\ : OUTBUF - port map(D => \GND\, PAD => apbo(92)); - - \AHB_Master_Out_pad[277]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(277)); - - \AHB_Master_Out_pad[71]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[24]\, PAD => - AHB_Master_Out(71)); - - \apbo_pad[73]\ : OUTBUF - port map(D => \VCC\, PAD => apbo(73)); - - \AHB_Master_Out_pad[81]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(81)); - - \AHB_Master_Out_pad[279]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(279)); - - \apbo_pad[125]\ : OUTBUF - port map(D => \GND\, PAD => apbo(125)); - - \AHB_Master_Out_pad[288]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(288)); - - \AHB_Master_Out_pad[107]\ : OUTBUF - port map(D => \GND\, PAD => AHB_Master_Out(107)); - - \AHB_Master_Out_pad[48]\ : OUTBUF - port map(D => \AHB_Master_Out.hwdata_c[1]\, PAD => - AHB_Master_Out(48)); - - \AHB_Master_Out_pad[33]\ : OUTBUF - port map(D => \AHB_Master_Out.haddr_c[29]\, PAD => - AHB_Master_Out(33)); - - -end DEF_ARCH; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp.vhd +++ /dev/null @@ -1,739 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2010, Aeroflex Gaisler AB - all rights reserved. --- --- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN --- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED --- IN ADVANCE IN WRITING. ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE GRLIB.DMA2AHB_Package.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; ---USE gaisler.pci.ALL; -USE gaisler.net.ALL; -USE gaisler.jtag.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; ---USE esa.pcicomp.ALL; -USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_bootloader_pkg.ALL; -use lpp.lpp_lfr_time_management.all; -- PLE -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - resetn : IN STD_ULOGIC; - clk : IN STD_ULOGIC; - pllref : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - dsutx : OUT STD_ULOGIC; -- DSU tx data - dsurx : IN STD_ULOGIC; -- DSU rx data - dsuen : IN STD_ULOGIC; - dsubre : IN STD_ULOGIC; - dsuact : OUT STD_ULOGIC; - txd1 : OUT STD_ULOGIC; -- UART1 tx data - rxd1 : IN STD_ULOGIC; -- UART1 rx data - txd2 : OUT STD_ULOGIC; -- UART2 tx data - rxd2 : IN STD_ULOGIC; -- UART2 rx data - ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - oen : OUT STD_ULOGIC; - writen : OUT STD_ULOGIC; - read : OUT STD_ULOGIC; - iosn : OUT STD_ULOGIC; - romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - emddis : OUT STD_LOGIC; - epwrdwn : OUT STD_ULOGIC; - ereset : OUT STD_ULOGIC; - esleep : OUT STD_ULOGIC; - epause : OUT STD_ULOGIC; - - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC; - pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - spw_clk : IN STD_ULOGIC; - spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - ramclk : OUT STD_LOGIC; - - nBWa : OUT STD_LOGIC; - nBWb : OUT STD_LOGIC; - nBWc : OUT STD_LOGIC; - nBWd : OUT STD_LOGIC; - nBWE : OUT STD_LOGIC; - nADSC : OUT STD_LOGIC; - nADSP : OUT STD_LOGIC; - nADV : OUT STD_LOGIC; - nGW : OUT STD_LOGIC; - nCE1 : OUT STD_LOGIC; - CE2 : OUT STD_LOGIC; - nCE3 : OUT STD_LOGIC; - nOE : OUT STD_LOGIC; - MODE : OUT STD_LOGIC; - SSRAM_CLK : OUT STD_LOGIC; - ZZ : OUT STD_LOGIC; - - tck, tms, tdi : IN STD_ULOGIC; - tdo : OUT STD_ULOGIC; - - -- waveform picker------ - clk49_152MHz : in std_ulogic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic - - - ); -END; - -ARCHITECTURE rtl OF leon3mp IS - - CONSTANT blength : INTEGER := 12; - - CONSTANT maxahbmsp : INTEGER := NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI); - CONSTANT maxahbm : INTEGER := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp + 2; -- +LPP_DMA - - - - SIGNAL vcc, gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdi : sdctrl_in_type; - SIGNAL sdo : sdram_out_type; - SIGNAL sdo2, sdo3 : sdctrl_out_type; - - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - - SIGNAL clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; - SIGNAL u1i, u2i, dui : uart_in_type; - SIGNAL u1o, u2o, duo : uart_out_type; - - SIGNAL irqi : irq_in_vector(0 TO NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO NCPU-1); - - SIGNAL dbgi : l3_debug_in_vector(0 TO NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO NCPU-1); - - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - - -- SIGNAL pcii : pci_in_type; --- SIGNAL pcio : pci_out_type; - - SIGNAL ethi, ethi1, ethi2 : eth_in_type; - SIGNAL etho, etho1, etho2 : eth_out_type; - - SIGNAL gpti : gptimer_in_type; - - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - - - SIGNAL lclk, pci_lclk : STD_ULOGIC := '0'; - SIGNAL pci_arb_req_n, pci_arb_gnt_n : STD_LOGIC_VECTOR(0 TO 3); - - SIGNAL spwi : grspw_in_type_vector(0 TO 2); - SIGNAL spwo : grspw_out_type_vector(0 TO 2); - SIGNAL spw_rx_clk : STD_ULOGIC; - - ATTRIBUTE sync_set_reset : STRING; - ATTRIBUTE sync_set_reset OF rstn : SIGNAL IS "true"; - - CONSTANT BOARD_FREQ : INTEGER := 40000; -- Board frequency in KHz - CONSTANT CPU_FREQ : INTEGER := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; - CONSTANT IOAEN : INTEGER := CFG_SDCTRL; - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - - CONSTANT sysfreq : INTEGER := (CFG_CLKMUL/CFG_CLKDIV)*40000; - - ----------------------------------------------------------------------------- - - SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fifo_empty : STD_LOGIC; - SIGNAL fifo_ren : STD_LOGIC; - SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL dma_empty : STD_LOGIC; - SIGNAL dma_ren : STD_LOGIC; - SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL header_val : STD_LOGIC; - SIGNAL header_ack : STD_LOGIC; - - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - - CONSTANT boardfreq : INTEGER := 50000; - - signal coarse_time : std_logic_vector(31 downto 0); - signal fine_time : std_logic_vector(31 downto 0); - -BEGIN - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); - gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; - cgi.pllrst <= rstraw; - - pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref); - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x); - - PROCESS(lclk2x) - BEGIN - IF lclk2x'EVENT AND lclk2x = '1' THEN - lclk <= NOT lclk; - END IF; - END PROCESS; - - pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk, lclk, clkm, OPEN, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; - - rst0 : rstgen -- reset generator - PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw); - ----------------------------------------------------------------------- ---- AHB CONTROLLER -------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- LEON3 processor and DSU ----------------------------------------- ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : odpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsuen_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsuen, dsui.enable); - dsubre_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsubre, dsui.break); - dsuact_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsuact, dsuo.active); - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart -- Debug UART - GENERIC MAP (hindex => NCPU, pindex => 7, paddr => 7) - PORT MAP (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsurx, dui.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsutx, duo.txd); - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(7) <= apb_none; END GENERATE; - - ahbjtaggen0 : IF CFG_AHB_JTAG = 1 GENERATE - ahbjtag0 : ahbjtag GENERIC MAP(tech => fabtech, hindex => NCPU+CFG_AHB_UART) - PORT MAP(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), - OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, gnd(0)); - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers ---------------------------------------------- ----------------------------------------------------------------------- --- LEON2 memory controller - sr1 : mctrl - GENERIC MAP ( - hindex => 0, - pindex => 0, - romaddr => 16#000#, - rommask => 16#E00#, - ioaddr => 16#200#, - iomask => 16#E00#, - ramaddr => 16#400#, - rammask => 16#C00#, - paddr => 0, - pmask => 16#fff#, - wprot => 0, - invclk => 0, - fast => 0, - romasel => 28, - sdrasel => 29, - srbanks => 4, - ram8 => 0, - ram16 => 0, - sden => 0, - sepbus => 0, - sdbits => 32, - sdlsb => 2, -- set to 12 for the GE-HPE board - oepol => 0, - syncrst => 0, - pageburst => 0, - scantest => 0, - mobile => 0 - ) - PORT MAP ( - rst => rstn, - clk => clkm, - memi => memi, - memo => memo, - ahbsi => ahbsi, - ahbso => ahbso(0), - apbi => apbi, - apbo => apbo(0), - wpo => wpo, - sdo => sdo - ); - - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads - addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0)); - rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0)); - roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0)); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (oen, memo.oen); - rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn); - roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0)); - wri_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (writen, memo.writen); - read_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (read, memo.read); - iosn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (iosn, memo.iosn); - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP (data(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - END GENERATE; - - SSRAM_0 : ssram_plugin - GENERIC MAP (tech => padtech) - PORT MAP (lclk2x, memo, SSRAM_CLK, - nBWa, nBWb, nBWc, nBWd, nBWE, nADSC, nADSP, nADV, nGW, nCE1, CE2, nCE3, nOE, MODE, ZZ); - - - ----------------------------------------------------------------------- ---- APB Bridge and various periherals ------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), u1i, u1o); - u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - - ua2 : IF CFG_UART2_ENABLE /= 0 GENERATE - uart2 : apbuart -- UART 2 - GENERIC MAP (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(9), u2i, u2o); - u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd; - END GENERATE; - noua1 : IF CFG_UART2_ENABLE = 0 GENERATE apbo(9) <= apb_none; END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, OPEN); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - gpio0 : IF CFG_GRGPIO_ENABLE /= 0 GENERATE -- GR GPIO unit - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, - nbits => CFG_GRGPIO_WIDTH) - PORT MAP(rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : FOR i IN 0 TO CFG_GRGPIO_WIDTH-1 GENERATE - pio_pad : iopad GENERIC MAP (tech => padtech) - PORT MAP (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - END GENERATE; - END GENERATE; - ------------------------------------------------------------------------ ---- PCI ------------------------------------------------------------ ------------------------------------------------------------------------ - - --pp : IF CFG_PCI /= 0 GENERATE - - -- pci_gr0 : IF CFG_PCI = 1 GENERATE -- simple target-only - -- pci0 : pci_target GENERIC MAP (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- device_id => CFG_PCIDID, vendor_id => CFG_PCIVID) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG)); - -- END GENERATE; - - -- pci_mtf0 : IF CFG_PCI = 2 GENERATE -- master/target with fifo - -- pci0 : pci_mtf GENERIC MAP (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - -- hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, - -- ioaddr => 16#400#, nsync => 2, hostrst => 1) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4), - -- ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - -- END GENERATE; - - -- pci_mtf1 : IF CFG_PCI = 3 GENERATE -- master/target with fifo and DMA - -- dma : pcidma GENERIC MAP (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1, - -- dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - -- slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, - -- nsync => 2, hostrst => 1) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1), - -- apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - -- END GENERATE; - - -- pci_trc0 : IF CFG_PCITBUFEN /= 0 GENERATE -- PCI trace buffer - -- pt0 : pcitrace GENERIC MAP (depth => (6 + log2(CFG_PCITBUF/256)), - -- memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#) - -- PORT MAP (rstn, clkm, pciclk, pcii, apbi, apbo(8)); - -- END GENERATE; - - -- pcia0 : IF CFG_PCI_ARB = 1 GENERATE -- PCI arbiter - -- pciarb0 : pciarb GENERIC MAP (pindex => 10, paddr => 10, - -- apb_en => CFG_PCI_ARBAPB) - -- PORT MAP (clk => pciclk, rst_n => pcii.rst, - -- req_n => pci_arb_req_n, frame_n => pcii.frame, - -- gnt_n => pci_arb_gnt_n, pclk => clkm, - -- prst_n => rstn, apbi => apbi, apbo => apbo(10) - -- ); - -- pgnt_pad : outpadv GENERIC MAP (tech => padtech, width => 4) - -- PORT MAP (pci_arb_gnt, pci_arb_gnt_n); - -- preq_pad : inpadv GENERIC MAP (tech => padtech, width => 4) - -- PORT MAP (pci_arb_req, pci_arb_req_n); - -- END GENERATE; - - -- pcipads0 : pcipads GENERIC MAP (padtech => padtech) -- PCI pads - -- PORT MAP (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - -- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, - -- pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio); - - --END GENERATE; - --- nop1 : IF CFG_PCI <= 1 GENERATE apbo(4) <= apb_none; END GENERATE; --- nop2 : IF CFG_PCI <= 2 GENERATE apbo(5) <= apb_none; END GENERATE; - nop3 : IF CFG_PCI <= 1 GENERATE ahbso(4) <= ahbs_none; END GENERATE; - notrc : IF CFG_PCITBUFEN = 0 GENERATE apbo(8) <= apb_none; END GENERATE; - noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE; - pci_rst <= '0'; - pci_lock <= '0'; - pci_ad <= (OTHERS => '0'); - pci_cbe <= (OTHERS => '0'); - pci_frame <= '0'; - pci_irdy <= '0'; - pci_trdy <= '0'; - pci_devsel <= '0'; - pci_stop <= '0'; - pci_perr <= '0'; - pci_par <= '0'; - pci_req <= '0'; - pci_serr <= '0'; - pci_arb_gnt <= (OTHERS => '0'); - - --- ahbso(6) <= ahbs_none; - ------------------------------------------------------------------------ ---- AHB RAM ---------------------------------------------------------- ------------------------------------------------------------------------ - - ocram : IF CFG_AHBRAMEN = 1 GENERATE - ahbram0 : ahbram GENERIC MAP (hindex => 7, haddr => CFG_AHBRADDR, - tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) - PORT MAP (rstn, clkm, ahbsi, ahbso(7)); - END GENERATE; - nram : IF CFG_AHBRAMEN = 0 GENERATE ahbso(7) <= ahbs_none; END GENERATE; - ------------------------------------------------------------------------ ---- SPACEWIRE ------------------------------------------------------- ------------------------------------------------------------------------ - --This template does NOT currently support grspw2 so only use grspw1 - spw : IF CFG_SPW_EN > 0 GENERATE - spw_rx_clk <= '0'; - spw_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (spw_clk, spw_lclk); - swloop : FOR i IN 0 TO CFG_SPW_NUM-1 GENERATE - sw0 : grspwm GENERIC MAP(tech => memtech, netlist => CFG_SPW_NETLIST, - hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i, - sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1, - fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO, - rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW) - PORT MAP(resetn, clkm, spw_rx_clk, spw_rx_clk, spw_lclk, spw_lclk, - ahbmi, ahbmo(maxahbmsp+i), - apbi, apbo(12+i), spwi(i), spwo(i)); - spwi(i).tickin <= '0'; spwi(i).rmapen <= '1'; - spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8); - spw_rxd_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxd(i), spw_rxdn(i), spwi(i).d(0)); - spw_rxs_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxs(i), spw_rxsn(i), spwi(i).s(0)); - spw_txd_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0)); - spw_txs_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0)); - END GENERATE; - END GENERATE; - no_spw: IF CFG_SPW_EN = 0 GENERATE - spw_txd <= (OTHERS => '0'); - spw_txdn <= (OTHERS => '0'); - spw_txs <= (OTHERS => '0'); - spw_txsn <= (OTHERS => '0'); - END GENERATE no_spw; - - - -------------------------------------------------------------------------------- --- BOOT MEMORY AND REGISTER -------------------------------------------------------------------------------- - - lpp_bootloader_1 : lpp_bootloader - GENERIC MAP ( - pindex => 13, - paddr => 13, - pmask => 16#fff#, - - hindex => 6, - haddr => 16#900#, - hmask => 16#F00#) - PORT MAP ( - HCLK => clkm, - HRESETn => resetn, - apbi => apbi, - apbo => apbo(13), - ahbsi => ahbsi, - ahbso => ahbso(6)); - - -------------------------------------------------------------------------------- --- AHB DMA -------------------------------------------------------------------------------- - - --lpp_dma_1 : lpp_dma - -- GENERIC MAP ( - -- tech => fabtech, - -- hindex => 2, - -- pindex => 14, - -- paddr => 14, - -- pmask => 16#fff#, - -- pirq => 0) - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- apbi => apbi, - -- apbo => apbo(14), - -- AHB_Master_In => ahbmi, - -- AHB_Master_Out => ahbmo(2), - -- fifo_data => fifo_data, --dma_data, - -- fifo_empty => fifo_empty, --dma_empty, - -- fifo_ren => fifo_ren, --dma_ren, - -- header => header, - -- header_val => header_val, - -- header_ack => header_ack); - - --fifo_test_dma_1 : fifo_test_dma - -- GENERIC MAP ( - -- tech => fabtech, - -- pindex => 15, - -- paddr => 15, - -- pmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- apbi => apbi, - -- apbo => apbo(15), - -- fifo_data => fifo_data, - -- fifo_empty => fifo_empty, - -- fifo_ren => fifo_ren, - -- header => header, - -- header_val => header_val, - -- header_ack => header_ack); - --------------------------- --- APB_LFR_TIME_MANAGEMENT --------------------------- - lfrtimemanagement_0 : apb_lfr_time_management - generic map( - pindex => 15, - paddr => 15, - pmask => 16#fff#, - masterclk => 25000000, - timeclk => 49152000, - finetimeclk => 65536, - pirq => 12) -- the IP uses 2 consecutive IRQ lines - port map( - clkm, - clk49_152MHz, - rstn, - '0', - apbi, - apbo(15), - coarse_time, - fine_time); - ------------------- --- WAVEFORM PICKER ------------------- - waveform_picker0 : lpp_top_lfr_wf_picker - GENERIC MAP( - hindex => 3, - pindex => 14, - paddr => 14, - pmask => 16#fff#, - pirq => 15, - tech => CFG_FABTECH, - nb_burst_available_size => 11, -- size of the register holding the nb of burst - nb_snapshot_param_size => 11, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 10, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 10 -- nb f0 ticks before starting the f1 snapshot - ) - PORT MAP( - -- ADS7886 - cnv_run => '1', -- stop the sampling request - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(14), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(3), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => Bias_Fails - ); - ------------------------------------------------------------------------ ---- Boot message ---------------------------------------------------- ------------------------------------------------------------------------ - --- pragma translate_off - x : report_version - GENERIC MAP ( - msg1 => "LEON3 MP Demonstration design", - msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION MOD 1000)/100) - & "." & tost(LIBVHDL_VERSION MOD 100) & ", build " & tost(LIBVHDL_BUILD), - msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech), - mdel => 1 - ); --- pragma translate_on -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp_post.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp_post.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp_post.vhd +++ /dev/null @@ -1,758 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2010, Aeroflex Gaisler AB - all rights reserved. --- --- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN --- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED --- IN ADVANCE IN WRITING. ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE GRLIB.DMA2AHB_Package.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; ---USE gaisler.pci.ALL; -USE gaisler.net.ALL; -USE gaisler.jtag.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; ---USE esa.pcicomp.ALL; -USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_bootloader_pkg.ALL; -use lpp.lpp_lfr_time_management.all; -- PLE -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_memory.ALL; ---USE lpp.lpp_top_lfr_pkg.ALL; - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - resetn : IN STD_ULOGIC; - clk : IN STD_ULOGIC; - pllref : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - dsutx : OUT STD_ULOGIC; -- DSU tx data - dsurx : IN STD_ULOGIC; -- DSU rx data - dsuen : IN STD_ULOGIC; - dsubre : IN STD_ULOGIC; - dsuact : OUT STD_ULOGIC; - txd1 : OUT STD_ULOGIC; -- UART1 tx data - rxd1 : IN STD_ULOGIC; -- UART1 rx data - txd2 : OUT STD_ULOGIC; -- UART2 tx data - rxd2 : IN STD_ULOGIC; -- UART2 rx data - ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - oen : OUT STD_ULOGIC; - writen : OUT STD_ULOGIC; - read : OUT STD_ULOGIC; - iosn : OUT STD_ULOGIC; - romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - emddis : OUT STD_LOGIC; - epwrdwn : OUT STD_ULOGIC; - ereset : OUT STD_ULOGIC; - esleep : OUT STD_ULOGIC; - epause : OUT STD_ULOGIC; - - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC; - pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - spw_clk : IN STD_ULOGIC; - spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - ramclk : OUT STD_LOGIC; - - nBWa : OUT STD_LOGIC; - nBWb : OUT STD_LOGIC; - nBWc : OUT STD_LOGIC; - nBWd : OUT STD_LOGIC; - nBWE : OUT STD_LOGIC; - nADSC : OUT STD_LOGIC; - nADSP : OUT STD_LOGIC; - nADV : OUT STD_LOGIC; - nGW : OUT STD_LOGIC; - nCE1 : OUT STD_LOGIC; - CE2 : OUT STD_LOGIC; - nCE3 : OUT STD_LOGIC; - nOE : OUT STD_LOGIC; - MODE : OUT STD_LOGIC; - SSRAM_CLK : OUT STD_LOGIC; - ZZ : OUT STD_LOGIC; - - tck, tms, tdi : IN STD_ULOGIC; - tdo : OUT STD_ULOGIC; - - -- waveform picker------ - clk49_152MHz : in std_ulogic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic - - - ); -END; - -ARCHITECTURE rtl OF leon3mp IS - - CONSTANT blength : INTEGER := 12; - - CONSTANT maxahbmsp : INTEGER := NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI); - CONSTANT maxahbm : INTEGER := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp + 2; -- +LPP_DMA - - - - SIGNAL vcc, gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdi : sdctrl_in_type; - SIGNAL sdo : sdram_out_type; - SIGNAL sdo2, sdo3 : sdctrl_out_type; - - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - - SIGNAL clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; - SIGNAL u1i, u2i, dui : uart_in_type; - SIGNAL u1o, u2o, duo : uart_out_type; - - SIGNAL irqi : irq_in_vector(0 TO NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO NCPU-1); - - SIGNAL dbgi : l3_debug_in_vector(0 TO NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO NCPU-1); - - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - - -- SIGNAL pcii : pci_in_type; --- SIGNAL pcio : pci_out_type; - - SIGNAL ethi, ethi1, ethi2 : eth_in_type; - SIGNAL etho, etho1, etho2 : eth_out_type; - - SIGNAL gpti : gptimer_in_type; - - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - - - SIGNAL lclk, pci_lclk : STD_ULOGIC := '0'; - SIGNAL pci_arb_req_n, pci_arb_gnt_n : STD_LOGIC_VECTOR(0 TO 3); - - SIGNAL spwi : grspw_in_type_vector(0 TO 2); - SIGNAL spwo : grspw_out_type_vector(0 TO 2); - SIGNAL spw_rx_clk : STD_ULOGIC; - - ATTRIBUTE sync_set_reset : STRING; - ATTRIBUTE sync_set_reset OF rstn : SIGNAL IS "true"; - - CONSTANT BOARD_FREQ : INTEGER := 40000; -- Board frequency in KHz - CONSTANT CPU_FREQ : INTEGER := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; - CONSTANT IOAEN : INTEGER := CFG_SDCTRL; - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - - CONSTANT sysfreq : INTEGER := (CFG_CLKMUL/CFG_CLKDIV)*40000; - - ----------------------------------------------------------------------------- - - SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fifo_empty : STD_LOGIC; - SIGNAL fifo_ren : STD_LOGIC; - SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL dma_empty : STD_LOGIC; - SIGNAL dma_ren : STD_LOGIC; - SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL header_val : STD_LOGIC; - SIGNAL header_ack : STD_LOGIC; - - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - - CONSTANT boardfreq : INTEGER := 50000; - - signal coarse_time : std_logic_vector(31 downto 0); - signal fine_time : std_logic_vector(31 downto 0); - - COMPONENT lpp_top_lfr_wf_picker - PORT ( - cnv_run : in std_logic; - cnv : out std_logic; - sck : out std_logic; - sdo : in std_logic_vector(7 downto 0); - cnv_clk : in std_logic; - cnv_rstn : in std_logic; - HCLK : in std_logic; - HRESETn : in std_logic; - apbi : in std_logic_vector(121 downto 0); - apbo : out std_logic_vector(131 downto 0); - AHB_Master_In : in std_logic_vector(90 downto 0); - AHB_Master_Out : out std_logic_vector(370 downto 0); - coarse_time_0 : in std_logic; - data_shaping_BW : out std_logic); - END COMPONENT; - -BEGIN - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); - gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; - cgi.pllrst <= rstraw; - - pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref); - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x); - - PROCESS(lclk2x) - BEGIN - IF lclk2x'EVENT AND lclk2x = '1' THEN - lclk <= NOT lclk; - END IF; - END PROCESS; - - pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk, lclk, clkm, OPEN, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; - - rst0 : rstgen -- reset generator - PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw); - ----------------------------------------------------------------------- ---- AHB CONTROLLER -------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- LEON3 processor and DSU ----------------------------------------- ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : odpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsuen_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsuen, dsui.enable); - dsubre_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsubre, dsui.break); - dsuact_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsuact, dsuo.active); - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart -- Debug UART - GENERIC MAP (hindex => NCPU, pindex => 7, paddr => 7) - PORT MAP (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (dsurx, dui.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (dsutx, duo.txd); - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(7) <= apb_none; END GENERATE; - - ahbjtaggen0 : IF CFG_AHB_JTAG = 1 GENERATE - ahbjtag0 : ahbjtag GENERIC MAP(tech => fabtech, hindex => NCPU+CFG_AHB_UART) - PORT MAP(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), - OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, OPEN, gnd(0)); - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers ---------------------------------------------- ----------------------------------------------------------------------- --- LEON2 memory controller - sr1 : mctrl - GENERIC MAP ( - hindex => 0, - pindex => 0, - romaddr => 16#000#, - rommask => 16#E00#, - ioaddr => 16#200#, - iomask => 16#E00#, - ramaddr => 16#400#, - rammask => 16#C00#, - paddr => 0, - pmask => 16#fff#, - wprot => 0, - invclk => 0, - fast => 0, - romasel => 28, - sdrasel => 29, - srbanks => 4, - ram8 => 0, - ram16 => 0, - sden => 0, - sepbus => 0, - sdbits => 32, - sdlsb => 2, -- set to 12 for the GE-HPE board - oepol => 0, - syncrst => 0, - pageburst => 0, - scantest => 0, - mobile => 0 - ) - PORT MAP ( - rst => rstn, - clk => clkm, - memi => memi, - memo => memo, - ahbsi => ahbsi, - ahbso => ahbso(0), - apbi => apbi, - apbo => apbo(0), - wpo => wpo, - sdo => sdo - ); - - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads - addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0)); - rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0)); - roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0)); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (oen, memo.oen); - rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn); - roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0)); - wri_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (writen, memo.writen); - read_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (read, memo.read); - iosn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (iosn, memo.iosn); - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP (data(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - END GENERATE; - - SSRAM_0 : ssram_plugin - GENERIC MAP (tech => padtech) - PORT MAP (lclk2x, memo, SSRAM_CLK, - nBWa, nBWb, nBWc, nBWd, nBWE, nADSC, nADSP, nADV, nGW, nCE1, CE2, nCE3, nOE, MODE, ZZ); - - - ----------------------------------------------------------------------- ---- APB Bridge and various periherals ------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), u1i, u1o); - u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - - ua2 : IF CFG_UART2_ENABLE /= 0 GENERATE - uart2 : apbuart -- UART 2 - GENERIC MAP (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(9), u2i, u2o); - u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd; - END GENERATE; - noua1 : IF CFG_UART2_ENABLE = 0 GENERATE apbo(9) <= apb_none; END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, OPEN); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - gpio0 : IF CFG_GRGPIO_ENABLE /= 0 GENERATE -- GR GPIO unit - grgpio0 : grgpio - GENERIC MAP(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, - nbits => CFG_GRGPIO_WIDTH) - PORT MAP(rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : FOR i IN 0 TO CFG_GRGPIO_WIDTH-1 GENERATE - pio_pad : iopad GENERIC MAP (tech => padtech) - PORT MAP (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - END GENERATE; - END GENERATE; - ------------------------------------------------------------------------ ---- PCI ------------------------------------------------------------ ------------------------------------------------------------------------ - - --pp : IF CFG_PCI /= 0 GENERATE - - -- pci_gr0 : IF CFG_PCI = 1 GENERATE -- simple target-only - -- pci0 : pci_target GENERIC MAP (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- device_id => CFG_PCIDID, vendor_id => CFG_PCIVID) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG)); - -- END GENERATE; - - -- pci_mtf0 : IF CFG_PCI = 2 GENERATE -- master/target with fifo - -- pci0 : pci_mtf GENERIC MAP (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - -- hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, - -- ioaddr => 16#400#, nsync => 2, hostrst => 1) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4), - -- ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - -- END GENERATE; - - -- pci_mtf1 : IF CFG_PCI = 3 GENERATE -- master/target with fifo and DMA - -- dma : pcidma GENERIC MAP (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1, - -- dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - -- fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, - -- slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, - -- nsync => 2, hostrst => 1) - -- PORT MAP (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1), - -- apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); - -- END GENERATE; - - -- pci_trc0 : IF CFG_PCITBUFEN /= 0 GENERATE -- PCI trace buffer - -- pt0 : pcitrace GENERIC MAP (depth => (6 + log2(CFG_PCITBUF/256)), - -- memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#) - -- PORT MAP (rstn, clkm, pciclk, pcii, apbi, apbo(8)); - -- END GENERATE; - - -- pcia0 : IF CFG_PCI_ARB = 1 GENERATE -- PCI arbiter - -- pciarb0 : pciarb GENERIC MAP (pindex => 10, paddr => 10, - -- apb_en => CFG_PCI_ARBAPB) - -- PORT MAP (clk => pciclk, rst_n => pcii.rst, - -- req_n => pci_arb_req_n, frame_n => pcii.frame, - -- gnt_n => pci_arb_gnt_n, pclk => clkm, - -- prst_n => rstn, apbi => apbi, apbo => apbo(10) - -- ); - -- pgnt_pad : outpadv GENERIC MAP (tech => padtech, width => 4) - -- PORT MAP (pci_arb_gnt, pci_arb_gnt_n); - -- preq_pad : inpadv GENERIC MAP (tech => padtech, width => 4) - -- PORT MAP (pci_arb_req, pci_arb_req_n); - -- END GENERATE; - - -- pcipads0 : pcipads GENERIC MAP (padtech => padtech) -- PCI pads - -- PORT MAP (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - -- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, - -- pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio); - - --END GENERATE; - --- nop1 : IF CFG_PCI <= 1 GENERATE apbo(4) <= apb_none; END GENERATE; --- nop2 : IF CFG_PCI <= 2 GENERATE apbo(5) <= apb_none; END GENERATE; - nop3 : IF CFG_PCI <= 1 GENERATE ahbso(4) <= ahbs_none; END GENERATE; - notrc : IF CFG_PCITBUFEN = 0 GENERATE apbo(8) <= apb_none; END GENERATE; - noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE; - pci_rst <= '0'; - pci_lock <= '0'; - pci_ad <= (OTHERS => '0'); - pci_cbe <= (OTHERS => '0'); - pci_frame <= '0'; - pci_irdy <= '0'; - pci_trdy <= '0'; - pci_devsel <= '0'; - pci_stop <= '0'; - pci_perr <= '0'; - pci_par <= '0'; - pci_req <= '0'; - pci_serr <= '0'; - pci_arb_gnt <= (OTHERS => '0'); - - --- ahbso(6) <= ahbs_none; - ------------------------------------------------------------------------ ---- AHB RAM ---------------------------------------------------------- ------------------------------------------------------------------------ - - ocram : IF CFG_AHBRAMEN = 1 GENERATE - ahbram0 : ahbram GENERIC MAP (hindex => 7, haddr => CFG_AHBRADDR, - tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) - PORT MAP (rstn, clkm, ahbsi, ahbso(7)); - END GENERATE; - nram : IF CFG_AHBRAMEN = 0 GENERATE ahbso(7) <= ahbs_none; END GENERATE; - ------------------------------------------------------------------------ ---- SPACEWIRE ------------------------------------------------------- ------------------------------------------------------------------------ - --This template does NOT currently support grspw2 so only use grspw1 - spw : IF CFG_SPW_EN > 0 GENERATE - spw_rx_clk <= '0'; - spw_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (spw_clk, spw_lclk); - swloop : FOR i IN 0 TO CFG_SPW_NUM-1 GENERATE - sw0 : grspwm GENERIC MAP(tech => memtech, netlist => CFG_SPW_NETLIST, - hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i, - sysfreq => sysfreq, nsync => 1, rmap => 0, ports => 1, dmachan => 1, - fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO, - rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW) - PORT MAP(resetn, clkm, spw_rx_clk, spw_rx_clk, spw_lclk, spw_lclk, - ahbmi, ahbmo(maxahbmsp+i), - apbi, apbo(12+i), spwi(i), spwo(i)); - spwi(i).tickin <= '0'; spwi(i).rmapen <= '1'; - spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8); - spw_rxd_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxd(i), spw_rxdn(i), spwi(i).d(0)); - spw_rxs_pad : inpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_rxs(i), spw_rxsn(i), spwi(i).s(0)); - spw_txd_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0)); - spw_txs_pad : outpad_ds GENERIC MAP (padtech, lvds, x25v) - PORT MAP (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0)); - END GENERATE; - END GENERATE; - no_spw: IF CFG_SPW_EN = 0 GENERATE - spw_txd <= (OTHERS => '0'); - spw_txdn <= (OTHERS => '0'); - spw_txs <= (OTHERS => '0'); - spw_txsn <= (OTHERS => '0'); - END GENERATE no_spw; - - - -------------------------------------------------------------------------------- --- BOOT MEMORY AND REGISTER -------------------------------------------------------------------------------- - - lpp_bootloader_1 : lpp_bootloader - GENERIC MAP ( - pindex => 13, - paddr => 13, - pmask => 16#fff#, - - hindex => 6, - haddr => 16#900#, - hmask => 16#F00#) - PORT MAP ( - HCLK => clkm, - HRESETn => resetn, - apbi => apbi, - apbo => apbo(13), - ahbsi => ahbsi, - ahbso => ahbso(6)); - - -------------------------------------------------------------------------------- --- AHB DMA -------------------------------------------------------------------------------- - - --lpp_dma_1 : lpp_dma - -- GENERIC MAP ( - -- tech => fabtech, - -- hindex => 2, - -- pindex => 14, - -- paddr => 14, - -- pmask => 16#fff#, - -- pirq => 0) - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- apbi => apbi, - -- apbo => apbo(14), - -- AHB_Master_In => ahbmi, - -- AHB_Master_Out => ahbmo(2), - -- fifo_data => fifo_data, --dma_data, - -- fifo_empty => fifo_empty, --dma_empty, - -- fifo_ren => fifo_ren, --dma_ren, - -- header => header, - -- header_val => header_val, - -- header_ack => header_ack); - - --fifo_test_dma_1 : fifo_test_dma - -- GENERIC MAP ( - -- tech => fabtech, - -- pindex => 15, - -- paddr => 15, - -- pmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clkm, - -- HRESETn => resetn, - -- apbi => apbi, - -- apbo => apbo(15), - -- fifo_data => fifo_data, - -- fifo_empty => fifo_empty, - -- fifo_ren => fifo_ren, - -- header => header, - -- header_val => header_val, - -- header_ack => header_ack); - --------------------------- --- APB_LFR_TIME_MANAGEMENT --------------------------- - lfrtimemanagement_0 : apb_lfr_time_management - generic map( - pindex => 15, - paddr => 15, - pmask => 16#fff#, - masterclk => 25000000, - otherclk => 49152000, - finetimeclk => 65536, - pirq => 12) -- the IP uses 2 consecutive IRQ lines - port map( - clkm, - clk49_152MHz, - rstn, - '0', - apbi, - apbo(15), - coarse_time, - fine_time); - ------------------- --- WAVEFORM PICKER ------------------- --- waveform_picker0 : lpp_top_lfr_wf_picker --- GENERIC MAP( --- hindex => 3, --- pindex => 14, --- paddr => 14, --- pmask => 16#fff#, --- pirq => 15, - -- tech => CFG_FABTECH, --- nb_burst_available_size => 11, -- size of the register holding the nb of burst --- nb_snapshot_param_size => 11, -- size of the register holding the snapshots size --- delta_snapshot_size => 16, -- snapshots period --- delta_f2_f0_size => 10, -- initialize the counter when the f2 snapshot starts --- delta_f2_f1_size => 10 -- nb f0 ticks before starting the f1 snapshot --- ) - waveform_picker0 : lpp_top_lfr_wf_picker - PORT MAP( - -- ADS7886 - cnv_run => '1', -- stop the sampling request - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(14), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(3), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => Bias_Fails - ); - ------------------------------------------------------------------------ ---- Boot message ---------------------------------------------------- ------------------------------------------------------------------------ - --- pragma translate_off - x : report_version - GENERIC MAP ( - msg1 => "LEON3 MP Demonstration design", - msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION MOD 1000)/100) - & "." & tost(LIBVHDL_VERSION MOD 100) & ", build " & tost(LIBVHDL_BUILD), - msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech), - mdel => 1 - ); --- pragma translate_on -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp_wfp_post.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp_wfp_post.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/leon3mp_wfp_post.vhd +++ /dev/null @@ -1,192155 +0,0 @@ --- Version: 9.1 SP5 9.1.5.1 - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity gptimer is - - port( scaler_4 : out std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_0 : in std_logic; - pwdata_1_2 : in std_logic; - paddr : in std_logic_vector(6 downto 2); - value_6 : out std_logic; - value_0 : out std_logic; - paddr_2 : in std_logic_vector(2 to 2); - pirq : out std_logic_vector(9 downto 8); - readdata_9_5 : out std_logic; - readdata_9_0 : out std_logic; - readdata_9_27 : out std_logic; - readdata_9_4 : out std_logic; - paddr_1 : in std_logic_vector(2 to 2); - reload_RNIRDRG : out std_logic_vector(1 to 1); - value_RNIBAHH : out std_logic_vector(1 to 1); - reload_RNI6SNI : out std_logic_vector(1 to 1); - scaler_i_m : out std_logic_vector(1 to 1); - reload_m_0_2 : out std_logic; - reload_m_0_3 : out std_logic; - reload_m_0_0 : out std_logic; - scaler_m_5 : out std_logic; - scaler_m_7 : out std_logic; - scaler_m_6 : out std_logic; - scaler_m_0 : out std_logic; - pwdata_0_d0 : in std_logic; - pwdata_14 : in std_logic; - pwdata_25 : in std_logic; - pwdata_12 : in std_logic; - pwdata_24 : in std_logic; - pwdata_23 : in std_logic; - pwdata_22 : in std_logic; - pwdata_21 : in std_logic; - pwdata_20 : in std_logic; - pwdata_19 : in std_logic; - pwdata_18 : in std_logic; - pwdata_17 : in std_logic; - pwdata_16 : in std_logic; - pwdata_15 : in std_logic; - pwdata_13 : in std_logic; - pwdata_11 : in std_logic; - pwdata_10 : in std_logic; - reload_28 : out std_logic; - reload_12 : out std_logic; - reload_11 : out std_logic; - reload_10 : out std_logic; - reload_8 : out std_logic; - reload_7 : out std_logic; - reload_6 : out std_logic; - reload_5 : out std_logic; - reload_0_7 : out std_logic; - reload_0_6 : out std_logic; - reload_0_4 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 0); - prdata_17 : out std_logic; - prdata_0 : out std_logic; - prdata_2 : out std_logic; - prdata_4 : out std_logic; - prdata_16 : out std_logic; - prdata_3 : out std_logic; - prdata_5 : out std_logic; - prdata_11 : out std_logic; - prdata_15 : out std_logic; - prdata_9 : out std_logic; - readdata_9_i_m : out std_logic_vector(1 to 1); - readdata_1_iv_0_0 : out std_logic; - readdata_1_iv_0_2 : out std_logic; - readdata_1_iv_0_11 : out std_logic; - readdata_1_iv_0_13 : out std_logic; - readdata_1_iv_0_9 : out std_logic; - readdata_iv_3 : out std_logic_vector(3 downto 2); - reload_m_20 : out std_logic; - reload_m_5 : out std_logic; - reload_m_9 : out std_logic; - reload_m_21 : out std_logic; - reload_m_0_d0 : out std_logic; - reload_m_27 : out std_logic; - reload_m_4 : out std_logic; - value_m_1 : out std_logic; - value_m_9 : out std_logic; - value_m_5 : out std_logic; - value_m_23 : out std_logic; - value_m_17 : out std_logic; - value_m_11 : out std_logic; - value_m_3 : out std_logic; - value_m_20 : out std_logic; - value_m_6 : out std_logic; - value_m_4 : out std_logic; - value_m_7 : out std_logic; - value_m_0 : out std_logic; - value_m_24 : out std_logic; - value_m_22 : out std_logic; - value_m_18 : out std_logic; - value_m_8 : out std_logic; - value_m_16 : out std_logic; - paddr_0 : in std_logic_vector(3 downto 2); - N_228 : out std_logic; - readdata51_1 : out std_logic; - N_6455 : in std_logic; - chain_m : out std_logic; - rdata60_1 : out std_logic; - rdata60_4 : in std_logic; - enable_m : out std_logic; - rdata59_4 : in std_logic; - N_217 : out std_logic; - N_229 : out std_logic; - N_215 : out std_logic; - rdata61_2 : in std_logic; - readdata55_3 : out std_logic; - N_218 : out std_logic; - N_216 : out std_logic; - N_214 : out std_logic; - irqpen_m : out std_logic; - N_219 : out std_logic; - N_236 : out std_logic; - N_220 : out std_logic; - rstn : in std_logic; - restart_RNIIKBB : out std_logic; - N_240 : out std_logic; - readdata55 : out std_logic; - dishlt : out std_logic; - penable : in std_logic; - pwrite : in std_logic; - N_773 : in std_logic; - N_769 : in std_logic; - readdata57 : out std_logic; - un1_apbi_0 : out std_logic; - N_78 : in std_logic; - un1_apbi_7_3 : in std_logic; - un1_apbi_2 : out std_logic; - readdata56 : out std_logic; - N_232_0 : in std_logic; - N_240_0 : out std_logic; - readdata_1_sqmuxa_1_0 : out std_logic; - N_232 : in std_logic; - value_0_sqmuxa_0 : out std_logic; - N_6455_0 : in std_logic; - lclk_c : in std_logic - ); - -end gptimer; - -architecture DEF_ARCH of gptimer is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \tsel_0[0]\, \tsel_RNIG6TH[0]\, reload_1_sqmuxa_0, - readdata30, un1_apbi, value_2_sqmuxa_0, irq_0_sqmuxa, - load, value_1_sqmuxa_0, value_2_sqmuxa_0_0, - irq_0_sqmuxa_0, load_0, value_1_sqmuxa_0_0, - reload_1_sqmuxa_0_0, \readdata_1_sqmuxa_1\, readdata51, - \value_0_sqmuxa_0\, value_1_sn_N_9_i_0, restart, un19_res, - value_1_sn_N_9_i_0_0, restart_0, N_157, - \value_RNI534J[1]\, \value_RNI3R3J[0]\, N_149, - \value_RNI9J4J[3]\, \DWACT_FDEC_E[0]\, N_126, - \value_RNIJR5J[8]\, \DWACT_FDEC_E[4]\, N_111, - \DWACT_FDEC_E[7]\, \DWACT_FDEC_E[6]\, N_30, \scaler[1]\, - \scaler[0]\, N_22, \scaler[3]\, \DWACT_FDEC_E_0[0]\, - \value[20]\, \reload[4]\, \reload[27]\, - readdata_1_sqmuxa_1_0_net_1, irqpen_0_sqmuxa_0, irqen, - \tsel[1]\, irqpen_0_sqmuxa_1, un4_i, irqen_0, - \reload_m[2]\, \readdata_iv_0[2]\, \readdata_iv_2[2]\, - \value[2]\, \scaler_m[2]\, \readdata_2_sqmuxa\, - \readdata_9[2]\, \reload_m[3]\, \readdata_iv_0[3]\, - \readdata_iv_2[3]\, \value[3]\, \scaler_m[3]\, - \readdata_9[3]\, \readdata_1_iv_0[31]\, \N_240_0\, N_239, - \reload_m[31]\, \readdata_1_iv_0[14]\, N_222, - \reload_m[14]\, \readdata_1_iv_0[16]\, \reload[16]\, - \readdata_9[16]\, N_230, \reload_m[22]\, N_234, - \reload_m[26]\, \readdata_1_iv_0[19]\, N_227, - \reload_m[19]\, N_232_1, \reload_m[24]\, N_223, - \reload_m[15]\, N_221, \reload_m[13]\, - \readdata_9_i_m_0[1]\, un1_apbi_0_0, \readdata_9[1]\, - value_1_sqmuxa, \reload_m[23]\, \readdata_9[23]\, - \value_m[23]\, \reload_m[29]\, \readdata_9[29]\, - \value_m[29]\, \reload_m[25]\, \readdata_9[25]\, - \value_m[25]\, \value[19]\, \reload_m[17]\, - \readdata_9[17]\, \value_m[17]\, \reload_m[30]\, - \readdata_9[30]\, \value_m[30]\, \reload_m[18]\, - \readdata_9[18]\, \value_m[18]\, \value[16]\, - reload_1_sqmuxa, load_RNO, load_1_sqmuxa, \value[14]\, - irqpen_0_sqmuxa_1_0, un34_i, value_2_sqmuxa, - value_2_sqmuxa_1, \value[31]\, \un1_apbi_0\, N_620, - load_1_sqmuxa_1, N_631, dishlt_1_sqmuxa, N_553, - \reload[0]\, N_554, \reload[1]\, N_555, \reload[2]\, - N_556, \reload[3]\, N_557, N_558, N_559, N_560, N_561, - N_562, \reload[9]\, N_563, N_564, N_565, N_566, - \reload[13]\, N_568, \reload[15]\, N_569, N_570, - \reload[17]\, reload_1_sqmuxa_1, N_572, \reload[19]\, - N_574, \reload[21]\, N_575, \reload[22]\, N_576, - \reload[23]\, N_577, \reload[24]\, N_578, \reload[25]\, - N_579, \reload[26]\, N_580, N_581, N_582, \reload[29]\, - N_583, \reload[30]\, N_623, \reload_0[0]\, - reload_1_sqmuxa_2, N_624, \reload_0[1]\, N_625, - \reload_0[2]\, N_626, \reload_0[3]\, N_627, N_628, - \reload_0[5]\, N_629, N_630, N_208, \un1_timer0[8]\, - \reload_1[0]\, \readdata56\, N_201, N_209, \readdata55\, - \value[1]\, N_324, I_44, N_325, I_5_6, N_326, I_9_6, - \scaler_1[0]\, scaler_0_sqmuxa, \scaler_1[1]\, - \scaler_1[2]\, N_343, I_5_5, \reload_1[1]\, N_344, I_9_5, - \reload_1[2]\, \value_1[1]\, \value_1[2]\, N_431, I_143_1, - \value_1[22]\, N_198, \scaler_RNO[0]\, \scaler_RNO[1]\, - \scaler_RNO[2]\, \un1_timer0[20]\, \reload_0[12]\, N_224, - \un1_timer0[24]\, \reload_0[16]\, N_226, \un1_timer0[26]\, - \reload[18]\, \un1_timer0[30]\, \reload_0[22]\, - \un1_timer0[34]\, \reload_0[26]\, \un1_timer0[36]\, - \reload_0[28]\, N_238, \un1_timer0[38]\, \reload_0[30]\, - \value[12]\, \value[18]\, \reload_0[18]\, \value[22]\, - \value[26]\, \value[28]\, \value[30]\, N_342, N_345, - I_13_9, \reload_1[3]\, \value_1[0]\, \value_1[3]\, N_409, - N_411, N_412, \value_1_0[0]\, \value_1_0[2]\, - \value_1_0[3]\, \N_240\, N_212, \un1_timer0[12]\, - \reload_1[4]\, \un1_timer0[19]\, \reload_0[11]\, N_225, - \un1_timer0[25]\, \reload_0[17]\, \un1_timer0[27]\, - \reload_0[19]\, N_233, \un1_timer0[33]\, \reload_0[25]\, - N_237, \un1_timer0[37]\, \reload_0[29]\, N_204, - \value[4]\, value_0_sqmuxa, irqpen, \value[11]\, - \value[17]\, \value[25]\, \value[29]\, N_346, I_20_5, - N_368, I_186_1, \value_1[4]\, \value_1[26]\, N_413, - \reload_0[4]\, N_435, \value_1_0[4]\, \value_1_0[26]\, - irqpen_0, N_347, I_24_6, \reload_1[5]\, N_349, I_38_2, - \reload_1[7]\, N_351, I_52_2, \reload_0[9]\, N_355, - I_77_1, \reload_0[13]\, N_366, I_166_1, \reload_0[24]\, - N_367, I_173_1, \value_1[5]\, \value_1[7]\, \value_1[9]\, - \value_1[13]\, \value_1[24]\, \value_1[25]\, N_414, - \reload[5]\, N_416, \reload[7]\, N_418, N_422, - \value_1_0[5]\, \value_1_0[7]\, \value_1_0[9]\, - \value_1_0[13]\, \un1_timer0[14]\, \reload_1[6]\, - \un1_timer0[16]\, \reload_0[8]\, \scaler[6]\, \value[8]\, - N_330, I_31_5, \reload_0[6]\, \scaler_1[6]\, N_348, - I_31_4, N_353, I_66_2, \value_1[6]\, \value_1[11]\, N_415, - \reload[6]\, N_420, \reload[11]\, N_433, N_434, - \value_1_0[6]\, \value_1_0[11]\, \value_1_0[24]\, - \value_1_0[25]\, \scaler_RNO[6]\, N_350, I_45_2, N_352, - I_56_2, \reload_0[10]\, N_354, I_73_1, value_1_sn_N_9_i, - N_358, I_98_1, N_359, I_105_1, N_360, I_115_1, N_361, - I_122_1, N_363, I_136_1, \reload_0[21]\, N_365, I_156_1, - \reload_0[23]\, N_369, I_196_1, \reload_0[27]\, N_370, - I_203_1, N_372, I_217, \value_1[8]\, \value_1[10]\, - \value_1[12]\, \value_1[16]\, \value_1[17]\, - \value_1[18]\, \value_1[19]\, \value_1[21]\, - \value_1[23]\, \value_1[27]\, \value_1[28]\, - \value_1[30]\, N_417, \reload[8]\, N_419, \reload[10]\, - N_421, \reload[12]\, value_1_sn_N_9_i_1, N_423, I_84_1, - \reload[14]\, N_425, N_426, N_427, N_428, N_430, N_432, - N_436, N_437, \reload[28]\, N_439, \value_1_0[8]\, - \value_1_0[10]\, \value_1_0[12]\, value_1_sqmuxa_1, - \value_1[14]\, \value_1_0[16]\, \value_1_0[17]\, - \value_1_0[18]\, \value_1_0[19]\, \value_1_0[21]\, - \value_1_0[23]\, \value_1_0[27]\, \value_1_0[28]\, - \value_1_0[30]\, \un1_timer0[18]\, \value[10]\, N_364, - N_371, I_210_1, \value_1_0[22]\, N_424, I_91_1, N_438, - \value_1[15]\, \value_1[29]\, \readdata57\, - \un1_timer0[5]\, \un1_timer0[32]\, \value[24]\, irqpen_1, - irqpen_4, irqpen_1_0, load_1_sqmuxa_0, irqpen_4_0, - \un1_timer0[15]\, \un1_timer0[23]\, \reload_0[15]\, - \un1_timer0[29]\, N_235, \un1_timer0[35]\, \scaler[7]\, - \value[7]\, \value[15]\, \value[21]\, \value[27]\, N_328, - I_20_6, \scaler_1[4]\, irqpen_RNO, irqpen_RNO_0, - \scaler_RNO[4]\, N_327, I_13_10, N_329, I_24_7, N_331, - I_38_3, \reload_0[7]\, \scaler_1[3]\, \scaler_1[5]\, - \scaler_1[7]\, \scaler_RNO[3]\, \scaler_RNO[5]\, - \scaler_RNO[7]\, \un1_timer0[17]\, \un1_timer0[21]\, - \value[9]\, \value[13]\, dishlt_RNO, irqen_RNO, - \reload_RNO[16]\, \reload_RNO[17]\, \reload_RNO[19]\, - \reload_RNO[21]\, \reload_RNO[22]\, \reload_RNO[23]\, - \reload_RNO[24]\, \reload_RNO[25]\, \reload_RNO[26]\, - \reload_RNO[27]\, \reload_RNO[28]\, \reload_RNO[29]\, - \reload_RNO[30]\, \tsel_RNO[1]\, \reload_RNO[0]\, - \reload_RNO[1]\, \reload_RNO[2]\, \reload_RNO[3]\, - \reload_RNO[4]\, \reload_RNO[5]\, \reload_RNO[6]\, - \reload_RNO[7]\, \reload_RNO[8]\, \reload_RNO[9]\, - \reload_RNO[10]\, \reload_RNO[11]\, \reload_RNO[12]\, - \reload_RNO[13]\, \reload_RNO[15]\, \reload_RNO_0[0]\, - \reload_RNO_0[1]\, \reload_RNO_0[2]\, \reload_RNO_0[3]\, - \reload_RNO_0[4]\, \reload_RNO_0[5]\, \reload_RNO_0[6]\, - \reload_RNO_0[7]\, N_231, \un1_timer0[31]\, \value[23]\, - \un1_timer0[6]\, \un1_timer0[22]\, \reload_0[14]\, N_203, - N_211, \un1_timer0[9]\, \value_RNI7B4J[2]\, - \un1_timer0[10]\, \un1_timer0[11]\, \value_RNIBR4J[4]\, - \value_RNID35J[5]\, \value[5]\, \un1_timer0[13]\, - \value_RNIFB5J[6]\, \value_RNIHJ5J[7]\, - \value_RNIL36J[9]\, \value_RNI73QI[10]\, - \value_RNI93QI[11]\, \value_RNIB3QI[12]\, - \value_RNID3QI[13]\, \value_RNIF3QI[14]\, - \value_RNIH3QI[15]\, \value_RNIJ3QI[16]\, - \value_RNIVLUG[17]\, \tsel[0]\, \value_RNI3MUG[19]\, - \value_RNIPTUG[21]\, \value_RNIRTUG[22]\, - \value_RNITTUG[23]\, \value_RNIVTUG[24]\, - \value_RNI1UUG[25]\, \value_RNI3UUG[26]\, - \value_RNI5UUG[27]\, \value_RNI7UUG[28]\, - \value_RNI9UUG[29]\, \value_RNIT5VG[30]\, N_200, enable, - enable_0, chain, \scaler[2]\, tsel_1_sqmuxa, - \un1_timer0[7]\, N_205, enable_RNO, N_544, chain_0, - \scaler[5]\, N_213, enable_1_sqmuxa, load_RNIC53BJ, - enable_1, N_202, N_210, \rdata60_1\, \un1_apbi_2\, - \readdata51_1\, \readdata55_3\, \value_RNI1MUG[18]\, - \reload_RNO[14]\, N_567, \reload_RNO[18]\, N_571, - \value_1_0[29]\, \value_1_0[14]\, N_356, irq_2, N_543, - enable_1_0, enable_1_sqmuxa_0, N_617, N_619, irq_RNO, - chain_RNO, irqen_RNO_0, enable_RNO_0, I_224, - \value_RNIV5VG[31]\, \reload_RNO[31]\, N_584, restart_RNO, - N_618, \un1_timer0[39]\, \reload[31]\, \reload_0[31]\, - load_RNO_0, \value_1[31]\, N_440, \value_1_0[31]\, N_373, - \value_RNINTUG[20]\, \un1_timer0[28]\, \reload_RNO[20]\, - N_573, \value_1_0[15]\, N_357, \value_1[20]\, N_429, - I_129_1, \reload[20]\, \value_1_0[20]\, N_362, - \reload_0[20]\, \value_1_0[1]\, N_410, \dishlt\, - \value[0]\, \value[6]\, \DWACT_FDEC_E[3]\, - \DWACT_FDEC_E[2]\, N_9, \scaler[4]\, N_14, - \DWACT_FDEC_E[1]\, N_19, N_27, N_4, \DWACT_FDEC_E[24]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[27]\, - \DWACT_FDEC_E[26]\, N_9_0, N_14_0, \DWACT_FDEC_E[25]\, - N_19_0, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, N_24, - \DWACT_FDEC_E[15]\, \DWACT_FDEC_E[17]\, - \DWACT_FDEC_E[22]\, N_31, \DWACT_FDEC_E[21]\, - \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, \DWACT_FDEC_E[20]\, - N_40, \DWACT_FDEC_E[13]\, \DWACT_FDEC_E[19]\, N_45, - \DWACT_FDEC_E[18]\, N_52, \DWACT_FDEC_E[33]\, - \DWACT_FDEC_E[34]\, \DWACT_FDEC_E_0[2]\, - \DWACT_FDEC_E[5]\, N_61, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_66, N_71, \DWACT_FDEC_E[14]\, N_76, - N_81, \DWACT_FDEC_E[10]\, N_88, \DWACT_FDEC_E[11]\, N_93, - N_98, N_103, \DWACT_FDEC_E[8]\, N_108, N_116, N_123, - \DWACT_FDEC_E_0[3]\, N_131, N_136, N_141, - \DWACT_FDEC_E_0[1]\, N_146, N_154, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - scaler_4 <= \scaler[4]\; - value_6 <= \value[6]\; - value_0 <= \value[0]\; - reload_28 <= \reload[28]\; - reload_12 <= \reload[12]\; - reload_11 <= \reload[11]\; - reload_10 <= \reload[10]\; - reload_8 <= \reload[8]\; - reload_7 <= \reload[7]\; - reload_6 <= \reload[6]\; - reload_5 <= \reload[5]\; - reload_0_7 <= \reload_0[7]\; - reload_0_6 <= \reload_0[6]\; - reload_0_4 <= \reload_0[4]\; - readdata51_1 <= \readdata51_1\; - rdata60_1 <= \rdata60_1\; - readdata55_3 <= \readdata55_3\; - N_240 <= \N_240\; - readdata55 <= \readdata55\; - dishlt <= \dishlt\; - readdata57 <= \readdata57\; - un1_apbi_0 <= \un1_apbi_0\; - un1_apbi_2 <= \un1_apbi_2\; - readdata56 <= \readdata56\; - N_240_0 <= \N_240_0\; - readdata_1_sqmuxa_1_0 <= readdata_1_sqmuxa_1_0_net_1; - value_0_sqmuxa_0 <= \value_0_sqmuxa_0\; - - \r.timers_1.value_RNI3MUG[19]\ : MX2 - port map(A => \value[19]\, B => \un1_timer0[27]\, S => - \tsel[0]\, Y => \value_RNI3MUG[19]\); - - un12_res_I_108 : OR3 - port map(A => \value_RNIH3QI[15]\, B => \value_RNIJ3QI[16]\, - C => \value_RNIVLUG[17]\, Y => \DWACT_FDEC_E[12]\); - - \r.timers_2.value_RNO[5]\ : MX2A - port map(A => N_414, B => pwdata_0(5), S => - value_1_sqmuxa_0_0, Y => \value_1_0[5]\); - - un12_res_I_52 : XNOR2 - port map(A => N_126, B => \value_RNIL36J[9]\, Y => I_52_2); - - \r.timers_1.restart_RNIC90KI\ : AO1 - port map(A => restart_0, B => un19_res, C => load, Y => - value_1_sn_N_9_i); - - un12_res_I_224 : XNOR2 - port map(A => N_4, B => \value_RNIV5VG[31]\, Y => I_224); - - \r.timers_2.reload[13]\ : DFN1 - port map(D => \reload_RNO[13]\, CLK => lclk_c, Q => - \reload[13]\); - - \r.timers_1.reload[8]\ : DFN1E1 - port map(D => pwdata_0(8), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[8]\); - - \r.scaler_RNO[1]\ : OR2B - port map(A => rstn, B => \scaler_1[1]\, Y => - \scaler_RNO[1]\); - - \comb.readdata57\ : OR2 - port map(A => rdata60_4, B => paddr(6), Y => \readdata57\); - - \r.timers_2.reload[9]\ : DFN1 - port map(D => \reload_RNO[9]\, CLK => lclk_c, Q => - \reload[9]\); - - \r.timers_1.irqen\ : DFN1 - port map(D => irqen_RNO, CLK => lclk_c, Q => irqen_0); - - \r.scaler[2]\ : DFN1 - port map(D => \scaler_RNO[2]\, CLK => lclk_c, Q => - \scaler[2]\); - - \r.timers_2.reload_RNO[27]\ : NOR2B - port map(A => rstn, B => N_580, Y => \reload_RNO[27]\); - - \r.timers_2.load_RNO\ : AO1B - port map(A => load_1_sqmuxa_0, B => pwdata_0(2), C => rstn, - Y => load_RNO_0); - - \r.timers_2.restart\ : DFN1 - port map(D => restart_RNO, CLK => lclk_c, Q => restart); - - \r.timers_2.value[16]\ : DFN1E0 - port map(D => \value_1_0[16]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[16]\); - - \r.timers_1.value_RNIV2CL[23]\ : OR2B - port map(A => \N_240\, B => N_231, Y => \readdata_9[23]\); - - \r.timers_1.value_RNI1UUG[25]\ : MX2 - port map(A => \value[25]\, B => \un1_timer0[33]\, S => - \tsel[0]\, Y => \value_RNI1UUG[25]\); - - \r.dishlt_RNO_0\ : MX2 - port map(A => \dishlt\, B => pwdata_0(9), S => - dishlt_1_sqmuxa, Y => N_631); - - \r.timers_2.reload[6]\ : DFN1 - port map(D => \reload_RNO[6]\, CLK => lclk_c, Q => - \reload[6]\); - - \r.timers_1.value_RNO_0[19]\ : MX2C - port map(A => I_122_1, B => \reload_0[19]\, S => - value_1_sn_N_9_i, Y => N_361); - - un12_res_I_77 : XNOR2 - port map(A => N_108, B => \value_RNID3QI[13]\, Y => I_77_1); - - \r.timers_2.irqen\ : DFN1 - port map(D => irqen_RNO_0, CLK => lclk_c, Q => irqen); - - un12_res_I_31 : XNOR2 - port map(A => N_141, B => \value_RNIFB5J[6]\, Y => I_31_4); - - \r.timers_2.value[4]\ : DFN1E0 - port map(D => \value_1_0[4]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[4]\); - - \r.timers_1.value_RNO_0[6]\ : MX2C - port map(A => I_31_4, B => \reload_1[6]\, S => - value_1_sn_N_9_i_0_0, Y => N_348); - - \r.timers_1.value_RNO[3]\ : MX2A - port map(A => N_345, B => pwdata_0(3), S => - value_1_sqmuxa_0, Y => \value_1[3]\); - - \r.timers_1.value_RNIH3QI[15]\ : MX2 - port map(A => \value[15]\, B => \un1_timer0[23]\, S => - \tsel_0[0]\, Y => \value_RNIH3QI[15]\); - - \r.tsel_RNO[1]\ : NOR2B - port map(A => rstn, B => \tsel_0[0]\, Y => \tsel_RNO[1]\); - - \r.timers_1.enable_RNO\ : NOR2B - port map(A => rstn, B => N_544, Y => enable_RNO); - - \r.timers_1.value_RNIAQJC[26]\ : MX2 - port map(A => \un1_timer0[34]\, B => \reload_0[26]\, S => - paddr_1(2), Y => N_234); - - \r.scaler_RNO[4]\ : OR2B - port map(A => rstn, B => \scaler_1[4]\, Y => - \scaler_RNO[4]\); - - \r.timers_2.reload_RNILNBI[29]\ : OR2A - port map(A => \reload[29]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[29]\); - - \r.timers_2.value_RNO_0[29]\ : MX2C - port map(A => I_210_1, B => \reload[29]\, S => - value_1_sn_N_9_i_1, Y => N_438); - - un12_res_I_91 : XNOR2 - port map(A => N_98, B => \value_RNIH3QI[15]\, Y => I_91_1); - - \r.reload[1]\ : DFN1 - port map(D => \reload_RNO_0[1]\, CLK => lclk_c, Q => - \reload_0[1]\); - - un6_scaler_I_13 : XNOR2 - port map(A => N_27, B => \scaler[3]\, Y => I_13_10); - - un12_res_I_80 : OR2 - port map(A => \value_RNIB3QI[12]\, B => \value_RNID3QI[13]\, - Y => \DWACT_FDEC_E[8]\); - - un12_res_I_13 : XNOR2 - port map(A => N_154, B => \value_RNI9J4J[3]\, Y => I_13_9); - - \r.timers_1.value_RNO_0[23]\ : MX2C - port map(A => I_156_1, B => \reload_0[23]\, S => - value_1_sn_N_9_i, Y => N_365); - - \r.timers_2.value_RNIS2KN1[14]\ : AO1C - port map(A => \value_0_sqmuxa_0\, B => \value[14]\, C => - \readdata_1_iv_0[14]\, Y => prdata_0); - - \r.timers_2.value_RNIBAHH[1]\ : OR2 - port map(A => \value_0_sqmuxa_0\, B => \value[1]\, Y => - value_RNIBAHH(1)); - - \r.timers_1.value_RNI2FCL[17]\ : OR2B - port map(A => \N_240\, B => N_225, Y => \readdata_9[17]\); - - \comb.1.un1_apbi_2\ : OR2B - port map(A => paddr(3), B => paddr(2), Y => \un1_apbi_2\); - - un12_res_I_8 : OR2 - port map(A => \value_RNI534J[1]\, B => \value_RNI3R3J[0]\, - Y => N_157); - - un12_res_I_19 : OR2 - port map(A => \value_RNI9J4J[3]\, B => \DWACT_FDEC_E[0]\, Y - => N_149); - - \r.timers_1.reload[22]\ : DFN1E1 - port map(D => pwdata_16, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[22]\); - - \r.timers_2.value_RNI6O211[3]\ : OA1A - port map(A => \value[3]\, B => \value_0_sqmuxa_0\, C => - \scaler_m[3]\, Y => \readdata_iv_2[3]\); - - \r.reload_RNO[1]\ : OR2A - port map(A => rstn, B => N_624, Y => \reload_RNO_0[1]\); - - \r.timers_1.reload_RNIN27C[0]\ : MX2 - port map(A => \un1_timer0[8]\, B => \reload_1[0]\, S => - paddr_0(2), Y => N_208); - - \r.timers_1.value_RNO_0[1]\ : MX2C - port map(A => I_5_5, B => \reload_1[1]\, S => - value_1_sn_N_9_i_0_0, Y => N_343); - - \r.timers_2.value_RNO_0[11]\ : MX2C - port map(A => I_66_2, B => \reload[11]\, S => - value_1_sn_N_9_i_0, Y => N_420); - - \r.timers_2.value_RNI9HCH[29]\ : OR2A - port map(A => \value[29]\, B => value_0_sqmuxa, Y => - \value_m[29]\); - - \r.timers_1.value_RNI6JCL[27]\ : OR2B - port map(A => \N_240\, B => N_235, Y => readdata_9_27); - - \r.scaler[0]\ : DFN1 - port map(D => \scaler_RNO[0]\, CLK => lclk_c, Q => - \scaler[0]\); - - \r.timers_1.reload_RNIP9761[22]\ : AOI1B - port map(A => \N_240_0\, B => N_230, C => \reload_m[22]\, Y - => readdata_1_iv_0_9); - - \r.timers_2.value_RNITCCH[10]\ : OR2A - port map(A => \value[10]\, B => value_0_sqmuxa, Y => - value_m_6); - - \r.timers_1.reload[10]\ : DFN1E1 - port map(D => pwdata_0(10), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[10]\); - - \r.scaler[6]\ : DFN1 - port map(D => \scaler_RNO[6]\, CLK => lclk_c, Q => - \scaler[6]\); - - \r.timers_2.reload_RNO_0[12]\ : MX2 - port map(A => \reload[12]\, B => pwdata_0(12), S => - reload_1_sqmuxa_0_0, Y => N_565); - - un12_res_I_105 : XNOR2 - port map(A => N_88, B => \value_RNIVLUG[17]\, Y => I_105_1); - - \r.timers_1.load_RNO\ : NOR3A - port map(A => pwdata_0(2), B => load_1_sqmuxa, C => - un1_apbi, Y => load_RNO); - - \r.timers_1.reload[5]\ : DFN1E1 - port map(D => pwdata_0(5), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[5]\); - - un12_res_I_122 : XNOR2 - port map(A => N_76, B => \value_RNI3MUG[19]\, Y => I_122_1); - - \r.timers_2.reload_RNIGMN71[16]\ : OA1A - port map(A => \reload[16]\, B => - readdata_1_sqmuxa_1_0_net_1, C => \readdata_9[16]\, Y => - \readdata_1_iv_0[16]\); - - \r.timers_2.value_RNI8HCH[28]\ : OR2A - port map(A => \value[28]\, B => \value_0_sqmuxa_0\, Y => - value_m_24); - - \r.timers_2.value[22]\ : DFN1E0 - port map(D => \value_1[22]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[22]\); - - \r.timers_1.load_RNIN4901\ : MX2C - port map(A => N_202, B => N_210, S => \N_240\, Y => - \readdata_9[2]\); - - \r.timers_1.value_RNI5MJC[16]\ : MX2 - port map(A => \un1_timer0[24]\, B => \reload_0[16]\, S => - paddr_0(2), Y => N_224); - - \r.timers_1.value_RNIVP761[24]\ : AOI1B - port map(A => \N_240_0\, B => N_232_1, C => \reload_m[24]\, - Y => readdata_1_iv_0_11); - - \r.timers_1.value[28]\ : DFN1E0 - port map(D => \value_1[28]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[36]\); - - \r.timers_2.reload[10]\ : DFN1 - port map(D => \reload_RNO[10]\, CLK => lclk_c, Q => - \reload[10]\); - - \r.timers_2.value_RNI5HCH[25]\ : OR2A - port map(A => \value[25]\, B => value_0_sqmuxa, Y => - \value_m[25]\); - - \r.timers_2.value[11]\ : DFN1E0 - port map(D => \value_1_0[11]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[11]\); - - \r.timers_2.reload_RNIH7BI[25]\ : OR2A - port map(A => \reload[25]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[25]\); - - \r.timers_2.chain\ : DFN1 - port map(D => chain_RNO, CLK => lclk_c, Q => chain_0); - - \r.timers_1.value[4]\ : DFN1E0 - port map(D => \value_1[4]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[12]\); - - \r.timers_1.reload[13]\ : DFN1E1 - port map(D => pwdata_0(13), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[13]\); - - \r.timers_2.value_RNO[15]\ : MX2A - port map(A => N_424, B => pwdata_0(15), S => - value_1_sqmuxa_1, Y => \value_1[15]\); - - un12_res_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \value_RNIVTUG[24]\, Y => \DWACT_FDEC_E[19]\); - - \r.timers_2.value_RNO_0[0]\ : MX2B - port map(A => \value_RNI3R3J[0]\, B => \reload[0]\, S => - value_1_sn_N_9_i_0, Y => N_409); - - \r.timers_1.value_RNIOD761[13]\ : AOI1B - port map(A => \N_240_0\, B => N_221, C => \reload_m[13]\, Y - => readdata_1_iv_0_0); - - \r.timers_1.reload_RNIVR451[0]\ : MX2C - port map(A => N_200, B => N_208, S => \N_240\, Y => - readdata_9_0); - - \r.reload[2]\ : DFN1 - port map(D => \reload_RNO_0[2]\, CLK => lclk_c, Q => - \reload_0[2]\); - - un12_res_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[1]\, - C => \value_RNID35J[5]\, Y => N_141); - - \r.timers_1.value_RNO[17]\ : MX2A - port map(A => N_359, B => pwdata_11, S => value_1_sqmuxa, Y - => \value_1[17]\); - - un6_scaler_I_9 : XNOR2 - port map(A => N_30, B => \scaler[2]\, Y => I_9_6); - - \r.timers_1.value_RNO_0[24]\ : MX2C - port map(A => I_166_1, B => \reload_0[24]\, S => - value_1_sn_N_9_i_0_0, Y => N_366); - - un12_res_I_27 : OR2 - port map(A => \value_RNI9J4J[3]\, B => \value_RNIBR4J[4]\, - Y => \DWACT_FDEC_E_0[1]\); - - \r.timers_1.value_RNO[14]\ : MX2A - port map(A => N_356, B => pwdata_0(14), S => value_1_sqmuxa, - Y => \value_1_0[14]\); - - \r.reload_RNO_0[0]\ : MX2 - port map(A => \reload_0[0]\, B => pwdata_0(0), S => - reload_1_sqmuxa_2, Y => N_623); - - \r.timers_1.value_RNO_0[28]\ : MX2C - port map(A => I_203_1, B => \reload_0[28]\, S => - value_1_sn_N_9_i, Y => N_370); - - \r.timers_1.value[12]\ : DFN1E0 - port map(D => \value_1[12]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[20]\); - - \r.timers_2.value_RNO_0[17]\ : MX2C - port map(A => I_105_1, B => \reload[17]\, S => - value_1_sn_N_9_i_1, Y => N_426); - - un12_res_I_59 : OR3 - port map(A => \value_RNIFB5J[6]\, B => \value_RNIHJ5J[7]\, - C => \value_RNIJR5J[8]\, Y => \DWACT_FDEC_E[5]\); - - un12_res_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_98); - - \r.timers_1.irq_RNIAUTI\ : OA1A - port map(A => chain_0, B => \un1_timer0[6]\, C => enable_0, - Y => un34_i); - - un12_res_I_66 : XNOR2 - port map(A => N_116, B => \value_RNI93QI[11]\, Y => I_66_2); - - un12_res_I_213 : OR3 - port map(A => \value_RNI5UUG[27]\, B => \value_RNI7UUG[28]\, - C => \value_RNI9UUG[29]\, Y => \DWACT_FDEC_E[26]\); - - \r.timers_1.value_RNIHHNII[31]\ : NOR2A - port map(A => I_224, B => \value_RNIV5VG[31]\, Y => - un19_res); - - \v.timers_2.reload_1_sqmuxa_0\ : NOR2 - port map(A => \readdata_1_sqmuxa_1\, B => un1_apbi, Y => - reload_1_sqmuxa_0_0); - - \r.timers_1.value_RNO[0]\ : MX2A - port map(A => N_342, B => pwdata_0(0), S => - value_1_sqmuxa_0, Y => \value_1[0]\); - - un12_res_I_176 : OR2 - port map(A => \value_RNIVTUG[24]\, B => \value_RNI1UUG[25]\, - Y => \DWACT_FDEC_E[20]\); - - \r.timers_2.reload[12]\ : DFN1 - port map(D => \reload_RNO[12]\, CLK => lclk_c, Q => - \reload[12]\); - - \r.timers_1.reload[9]\ : DFN1E1 - port map(D => pwdata_0(9), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[9]\); - - un12_res_I_9 : XNOR2 - port map(A => N_157, B => \value_RNI7B4J[2]\, Y => I_9_5); - - \r.timers_2.value_RNO[4]\ : MX2A - port map(A => N_413, B => pwdata_0(4), S => - value_1_sqmuxa_0_0, Y => \value_1_0[4]\); - - \r.timers_2.value[31]\ : DFN1E0 - port map(D => \value_1[31]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[31]\); - - \r.timers_1.reload_RNI2AJC[22]\ : MX2 - port map(A => \un1_timer0[30]\, B => \reload_0[22]\, S => - paddr_1(2), Y => N_230); - - \r.timers_2.reload_RNO_0[10]\ : MX2 - port map(A => \reload[10]\, B => pwdata_0(10), S => - reload_1_sqmuxa_0_0, Y => N_563); - - \r.timers_1.value_RNO[27]\ : MX2A - port map(A => N_369, B => pwdata_21, S => value_1_sqmuxa, Y - => \value_1[27]\); - - \r.timers_1.reload[6]\ : DFN1E1 - port map(D => pwdata_0_d0, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[6]\); - - \r.timers_2.reload_RNO_0[13]\ : MX2 - port map(A => \reload[13]\, B => pwdata_0(13), S => - reload_1_sqmuxa_0_0, Y => N_566); - - \r.timers_1.value_RNO[24]\ : MX2A - port map(A => N_366, B => pwdata_18, S => value_1_sqmuxa_0, - Y => \value_1[24]\); - - \r.timers_2.reload[7]\ : DFN1 - port map(D => \reload_RNO[7]\, CLK => lclk_c, Q => - \reload[7]\); - - \r.scaler_RNO_1[2]\ : MX2 - port map(A => I_9_6, B => \reload_0[2]\, S => I_44, Y => - N_326); - - \r.timers_2.value_RNIJ34P1[16]\ : AO1C - port map(A => \value_0_sqmuxa_0\, B => \value[16]\, C => - \readdata_1_iv_0[16]\, Y => prdata_2); - - \r.timers_1.value[8]\ : DFN1E0 - port map(D => \value_1[8]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[16]\); - - \r.timers_2.value_RNO_0[6]\ : MX2C - port map(A => I_31_4, B => \reload[6]\, S => - value_1_sn_N_9_i_0, Y => N_415); - - \r.timers_1.value_RNI9J4J[3]\ : MX2 - port map(A => \value[3]\, B => \un1_timer0[11]\, S => - \tsel_0[0]\, Y => \value_RNI9J4J[3]\); - - \comb.1.readdata_9_sn_m1\ : OR2A - port map(A => readdata30, B => paddr(2), Y => N_198); - - \r.scaler_RNO[0]\ : OR2B - port map(A => rstn, B => \scaler_1[0]\, Y => - \scaler_RNO[0]\); - - \r.timers_1.reload_RNI4R7C[6]\ : MX2 - port map(A => \un1_timer0[14]\, B => \reload_1[6]\, S => - paddr_1(2), Y => N_214); - - \r.timers_1.enable_RNO_2\ : NOR2 - port map(A => load_1_sqmuxa_1, B => load_RNIC53BJ, Y => - enable_1_sqmuxa); - - \r.timers_2.value_RNIEMHH[4]\ : OR2A - port map(A => \value[4]\, B => value_0_sqmuxa, Y => - value_m_0); - - \r.timers_1.value_RNO[30]\ : MX2A - port map(A => N_372, B => pwdata_24, S => value_1_sqmuxa, Y - => \value_1[30]\); - - \r.timers_2.value_RNO_0[4]\ : MX2C - port map(A => I_20_5, B => \reload_0[4]\, S => - value_1_sn_N_9_i_0, Y => N_413); - - \r.timers_1.reload[25]\ : DFN1E1 - port map(D => pwdata_19, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[25]\); - - \r.timers_2.reload_RNO[22]\ : NOR2B - port map(A => rstn, B => N_575, Y => \reload_RNO[22]\); - - \r.timers_1.irqen_RNO_0\ : MX2 - port map(A => irqen_0, B => pwdata_0(3), S => - load_1_sqmuxa_1, Y => N_620); - - \r.timers_1.irqen_RNO\ : NOR2B - port map(A => rstn, B => N_620, Y => irqen_RNO); - - un12_res_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_31); - - \r.scaler_RNO_1[3]\ : MX2 - port map(A => I_13_10, B => \reload_0[3]\, S => I_44, Y => - N_327); - - \r.timers_2.value_RNO[20]\ : MX2A - port map(A => N_429, B => pwdata_14, S => value_1_sqmuxa_1, - Y => \value_1[20]\); - - \r.timers_1.restart_RNISC09\ : NOR2A - port map(A => restart_0, B => N_198, Y => N_201); - - \r.timers_1.irqen_RNI6SEC\ : NOR2A - port map(A => irqen_0, B => N_198, Y => N_203); - - \r.timers_2.load_RNIMIAC1\ : OA1A - port map(A => load_0, B => \readdata_2_sqmuxa\, C => - \readdata_9[2]\, Y => \readdata_iv_0[2]\); - - \r.dishlt_RNO_1\ : NOR2 - port map(A => un1_apbi, B => \readdata57\, Y => - dishlt_1_sqmuxa); - - \r.timers_1.value_RNIVTUG[24]\ : MX2 - port map(A => \value[24]\, B => \un1_timer0[32]\, S => - \tsel[0]\, Y => \value_RNIVTUG[24]\); - - \r.timers_1.value[9]\ : DFN1E0 - port map(D => \value_1[9]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[17]\); - - \r.timers_2.value_RNIFB3P1[31]\ : AO1C - port map(A => \value_0_sqmuxa_0\, B => \value[31]\, C => - \readdata_1_iv_0[31]\, Y => prdata_17); - - \r.timers_2.value[29]\ : DFN1E0 - port map(D => \value_1[29]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[29]\); - - \r.timers_1.value_RNI3UUG[26]\ : MX2 - port map(A => \value[26]\, B => \un1_timer0[34]\, S => - \tsel[0]\, Y => \value_RNI3UUG[26]\); - - \r.timers_2.value_RNO_0[5]\ : MX2C - port map(A => I_24_6, B => \reload[5]\, S => - value_1_sn_N_9_i_0, Y => N_414); - - \r.timers_1.reload_RNI26JC[30]\ : MX2 - port map(A => \un1_timer0[38]\, B => \reload_0[30]\, S => - paddr_1(2), Y => N_238); - - \r.timers_1.value_RNO[31]\ : MX2A - port map(A => N_373, B => pwdata_25, S => value_1_sqmuxa, Y - => \value_1_0[31]\); - - \r.timers_1.value_RNICUJC[27]\ : MX2 - port map(A => \un1_timer0[35]\, B => \reload_0[27]\, S => - paddr_1(2), Y => N_235); - - \r.timers_1.load_RNI0B3K3_0\ : NOR3 - port map(A => irq_0_sqmuxa, B => load, C => - value_1_sqmuxa_0, Y => value_2_sqmuxa_0); - - un12_res_I_220 : OR2 - port map(A => \DWACT_FDEC_E[26]\, B => \value_RNIT5VG[30]\, - Y => \DWACT_FDEC_E[27]\); - - \r.timers_1.value_RNO_0[26]\ : MX2C - port map(A => I_186_1, B => \reload_0[26]\, S => - value_1_sn_N_9_i_0_0, Y => N_368); - - \r.timers_2.reload_RNO_0[28]\ : MX2 - port map(A => \reload[28]\, B => pwdata_22, S => - reload_1_sqmuxa_1, Y => N_581); - - \r.scaler_RNO_0[3]\ : MX2C - port map(A => pwdata_0(3), B => N_327, S => scaler_0_sqmuxa, - Y => \scaler_1[3]\); - - \r.timers_1.reload_RNII7ND[5]\ : MX2 - port map(A => \un1_timer0[13]\, B => \reload_1[5]\, S => - paddr(2), Y => N_213); - - un12_res_I_132 : OR3 - port map(A => \value_RNI1MUG[18]\, B => \value_RNI3MUG[19]\, - C => \value_RNINTUG[20]\, Y => \DWACT_FDEC_E[15]\); - - \r.timers_2.value_RNO[21]\ : MX2A - port map(A => N_430, B => pwdata_15, S => value_1_sqmuxa_1, - Y => \value_1_0[21]\); - - un12_res_I_41 : OR2 - port map(A => \value_RNIFB5J[6]\, B => \value_RNIHJ5J[7]\, - Y => \DWACT_FDEC_E_0[3]\); - - \r.timers_1.irqpen_RNO_1\ : AO1 - port map(A => irqpen_0_sqmuxa_1, B => irq_2, C => irqpen_0, - Y => irqpen_4); - - \r.timers_2.value_RNIOB4P1[17]\ : OR3C - port map(A => \reload_m[17]\, B => \readdata_9[17]\, C => - \value_m[17]\, Y => prdata_3); - - \r.timers_1.reload[17]\ : DFN1E1 - port map(D => pwdata_11, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[17]\); - - \r.reload_RNO_0[3]\ : MX2 - port map(A => \reload_0[3]\, B => pwdata_0(3), S => - reload_1_sqmuxa_2, Y => N_626); - - un12_res_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \r.timers_2.reload_RNO[31]\ : NOR2B - port map(A => rstn, B => N_584, Y => \reload_RNO[31]\); - - \r.timers_2.value[20]\ : DFN1E0 - port map(D => \value_1[20]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[20]\); - - \r.timers_2.value[15]\ : DFN1E0 - port map(D => \value_1[15]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[15]\); - - \r.timers_1.value_RNI534J[1]\ : MX2 - port map(A => \value[1]\, B => \un1_timer0[9]\, S => - \tsel_0[0]\, Y => \value_RNI534J[1]\); - - un12_res_I_38 : XNOR2 - port map(A => N_136, B => \value_RNIHJ5J[7]\, Y => I_38_2); - - un12_res_I_203 : XNOR2 - port map(A => N_19_0, B => \value_RNI7UUG[28]\, Y => - I_203_1); - - \r.timers_2.value_RNO[26]\ : MX2A - port map(A => N_435, B => pwdata_20, S => - value_1_sqmuxa_0_0, Y => \value_1_0[26]\); - - \r.timers_2.reload[23]\ : DFN1 - port map(D => \reload_RNO[23]\, CLK => lclk_c, Q => - \reload[23]\); - - \r.timers_1.value[19]\ : DFN1E0 - port map(D => \value_1[19]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[27]\); - - \r.scaler_RNO_1[0]\ : MX2A - port map(A => \scaler[0]\, B => \reload_0[0]\, S => I_44, Y - => N_324); - - \r.timers_1.irqpen_RNO_2\ : NOR3C - port map(A => un4_i, B => irqen_0, C => \tsel_0[0]\, Y => - irqpen_0_sqmuxa_1); - - un12_res_I_98 : XNOR2 - port map(A => N_93, B => \value_RNIJ3QI[16]\, Y => I_98_1); - - un12_res_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \value_RNIJR5J[8]\, C - => \value_RNIL36J[9]\, Y => N_123); - - \comb.un1_apbi_0\ : OR2B - port map(A => pwrite, B => penable, Y => \un1_apbi_0\); - - un6_scaler_I_37 : OR3 - port map(A => \DWACT_FDEC_E_0[0]\, B => \DWACT_FDEC_E[2]\, - C => \scaler[6]\, Y => N_9); - - \r.timers_2.reload_RNO_0[19]\ : MX2 - port map(A => \reload[19]\, B => pwdata_13, S => - reload_1_sqmuxa_1, Y => N_572); - - \r.timers_1.value_RNI7B4J[2]\ : MX2 - port map(A => \value[2]\, B => \un1_timer0[10]\, S => - \tsel_0[0]\, Y => \value_RNI7B4J[2]\); - - un12_res_I_129 : XNOR2 - port map(A => N_71, B => \value_RNINTUG[20]\, Y => I_129_1); - - \r.timers_1.chain_RNIQO9C\ : NOR2A - port map(A => chain, B => N_198, Y => N_205); - - \r.timers_1.value_RNO[9]\ : MX2A - port map(A => N_351, B => pwdata_0(9), S => - value_1_sqmuxa_0, Y => \value_1[9]\); - - \r.timers_1.reload_RNIKQ2E[31]\ : MX2 - port map(A => \un1_timer0[39]\, B => \reload_0[31]\, S => - paddr(2), Y => N_239); - - un12_res_I_84 : XNOR2 - port map(A => N_103, B => \value_RNIF3QI[14]\, Y => I_84_1); - - \r.timers_1.value_RNO_0[13]\ : MX2C - port map(A => I_77_1, B => \reload_0[13]\, S => - value_1_sn_N_9_i_0_0, Y => N_355); - - \r.timers_1.irqpen_RNO_0\ : AO1B - port map(A => load_1_sqmuxa_1, B => pwdata_0(4), C => - irqpen_4, Y => irqpen_1); - - \r.scaler_RNO_0[0]\ : MX2C - port map(A => pwdata_0(0), B => N_324, S => scaler_0_sqmuxa, - Y => \scaler_1[0]\); - - \r.timers_2.value_RNO_0[30]\ : MX2C - port map(A => I_217, B => \reload[30]\, S => - value_1_sn_N_9_i_1, Y => N_439); - - \r.timers_2.value_RNI4DCH[17]\ : OR2A - port map(A => \value[17]\, B => value_0_sqmuxa, Y => - \value_m[17]\); - - \r.timers_2.reload_RNO[2]\ : OR2A - port map(A => rstn, B => N_555, Y => \reload_RNO[2]\); - - \r.timers_1.value[10]\ : DFN1E0 - port map(D => \value_1[10]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[18]\); - - \r.timers_2.value_RNO[7]\ : MX2A - port map(A => N_416, B => pwdata_0(7), S => - value_1_sqmuxa_0_0, Y => \value_1_0[7]\); - - \r.timers_2.value_RNO_0[23]\ : MX2C - port map(A => I_156_1, B => \reload[23]\, S => - value_1_sn_N_9_i_1, Y => N_432); - - \v.scaler_0_sqmuxa\ : OR2A - port map(A => un1_apbi_7_3, B => un1_apbi, Y => - scaler_0_sqmuxa); - - \r.timers_2.value[14]\ : DFN1E0 - port map(D => \value_1[14]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[14]\); - - \r.timers_2.reload_RNO_0[0]\ : MX2 - port map(A => \reload[0]\, B => pwdata_0(0), S => - reload_1_sqmuxa_0_0, Y => N_553); - - \r.timers_2.value_RNO[17]\ : MX2A - port map(A => N_426, B => pwdata_11, S => value_1_sqmuxa_1, - Y => \value_1_0[17]\); - - un12_res_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \r.timers_2.value_RNO[14]\ : MX2A - port map(A => N_423, B => pwdata_0(14), S => - value_1_sqmuxa_1, Y => \value_1[14]\); - - \r.timers_2.reload_RNIKNBI[19]\ : OR2A - port map(A => \reload[19]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[19]\); - - \r.tick_RNIGFUB\ : AO1D - port map(A => \un1_timer0[7]\, B => \tsel[0]\, C => - \tsel[1]\, Y => tsel_1_sqmuxa); - - \r.timers_2.value_RNIJAIH[9]\ : OR2A - port map(A => \value[9]\, B => value_0_sqmuxa, Y => - value_m_5); - - \r.timers_1.value_RNO[12]\ : MX2A - port map(A => N_354, B => pwdata_0(12), S => value_1_sqmuxa, - Y => \value_1[12]\); - - \readdata_1_sqmuxa_1_0\ : OR2A - port map(A => readdata51, B => N_6455_0, Y => - readdata_1_sqmuxa_1_0_net_1); - - \r.reload_RNI98OI[4]\ : OR2A - port map(A => \reload[4]\, B => \readdata56\, Y => - reload_m_4); - - \r.timers_1.load_RNIHKP9\ : NOR2A - port map(A => load, B => N_198, Y => N_202); - - GND_i : GND - port map(Y => \GND\); - - \r.timers_1.value_RNIBR4J[4]\ : MX2 - port map(A => \value[4]\, B => \un1_timer0[12]\, S => - \tsel_0[0]\, Y => \value_RNIBR4J[4]\); - - \r.reload_RNO[7]\ : OR2A - port map(A => rstn, B => N_630, Y => \reload_RNO_0[7]\); - - \r.timers_1.value_RNO[2]\ : MX2A - port map(A => N_344, B => pwdata_0(2), S => - value_1_sqmuxa_0, Y => \value_1[2]\); - - \r.timers_2.value_RNI5DCH[18]\ : OR2A - port map(A => \value[18]\, B => \value_0_sqmuxa_0\, Y => - \value_m[18]\); - - un12_res_I_20 : XNOR2 - port map(A => N_149, B => \value_RNIBR4J[4]\, Y => I_20_5); - - un12_res_I_216 : OR3 - port map(A => \DWACT_FDEC_E[24]\, B => \DWACT_FDEC_E[23]\, - C => \DWACT_FDEC_E[26]\, Y => N_9_0); - - \r.timers_2.enable_RNO_1\ : MX2 - port map(A => restart, B => pwdata_0(0), S => - load_1_sqmuxa_0, Y => enable_1_0); - - \r.timers_1.value[27]\ : DFN1E0 - port map(D => \value_1[27]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[35]\); - - \r.timers_1.restart_RNIM16U1\ : OR3C - port map(A => \readdata_9[1]\, B => \readdata_9_i_m_0[1]\, - C => \readdata57\, Y => readdata_9_i_m(1)); - - \r.timers_2.value_RNI4G211[2]\ : OA1A - port map(A => \value[2]\, B => \value_0_sqmuxa_0\, C => - \scaler_m[2]\, Y => \readdata_iv_2[2]\); - - \r.timers_1.reload[7]\ : DFN1E1 - port map(D => pwdata_0(7), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[7]\); - - \r.timers_2.value[9]\ : DFN1E0 - port map(D => \value_1_0[9]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[9]\); - - \r.timers_1.value_RNO[18]\ : MX2A - port map(A => N_360, B => pwdata_12, S => value_1_sqmuxa, Y - => \value_1[18]\); - - \r.reload[3]\ : DFN1 - port map(D => \reload_RNO_0[3]\, CLK => lclk_c, Q => - \reload_0[3]\); - - \r.timers_1.value_RNO[7]\ : MX2A - port map(A => N_349, B => pwdata_0(7), S => - value_1_sqmuxa_0, Y => \value_1[7]\); - - \r.timers_1.value_RNO_0[7]\ : MX2C - port map(A => I_38_2, B => \reload_1[7]\, S => - value_1_sn_N_9_i_0_0, Y => N_349); - - \r.timers_1.reload[20]\ : DFN1E1 - port map(D => pwdata_14, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[20]\); - - \r.timers_1.reload_RNIVE7C[3]\ : MX2 - port map(A => \un1_timer0[11]\, B => \reload_1[3]\, S => - paddr_2(2), Y => N_211); - - \v.timers_2.value_1_sqmuxa_0\ : NOR2 - port map(A => \value_0_sqmuxa_0\, B => un1_apbi, Y => - value_1_sqmuxa_0_0); - - \r.timers_1.value_RNO[22]\ : MX2A - port map(A => N_364, B => pwdata_16, S => value_1_sqmuxa, Y - => \value_1_0[22]\); - - \r.timers_2.reload_RNO[23]\ : NOR2B - port map(A => rstn, B => N_576, Y => \reload_RNO[23]\); - - un6_scaler_I_31 : XNOR2 - port map(A => N_14, B => \scaler[6]\, Y => I_31_5); - - un12_res_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \value_RNI1MUG[18]\, Y => N_76); - - \r.timers_2.restart_RNIIKBB\ : OR2 - port map(A => \readdata_2_sqmuxa\, B => restart, Y => - restart_RNIIKBB); - - \r.timers_2.value_RNO_0[9]\ : MX2C - port map(A => I_52_2, B => \reload[9]\, S => - value_1_sn_N_9_i_0, Y => N_418); - - \r.timers_2.enable\ : DFN1 - port map(D => enable_RNO_0, CLK => lclk_c, Q => enable_0); - - \r.timers_1.irqpen_RNIMRIG\ : NOR2A - port map(A => irqpen_0, B => N_198, Y => N_204); - - \r.scaler[7]\ : DFN1 - port map(D => \scaler_RNO[7]\, CLK => lclk_c, Q => - \scaler[7]\); - - \r.timers_2.reload_RNIERAI[22]\ : OR2A - port map(A => \reload[22]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => \reload_m[22]\); - - \v.timers_2.reload_1_sqmuxa\ : NOR2 - port map(A => \readdata_1_sqmuxa_1\, B => un1_apbi, Y => - reload_1_sqmuxa_1); - - \r.timers_1.value_RNI2BCL[25]\ : OR2B - port map(A => \N_240\, B => N_233, Y => \readdata_9[25]\); - - \r.scaler_RNO_0[7]\ : MX2C - port map(A => pwdata_0(7), B => N_331, S => scaler_0_sqmuxa, - Y => \scaler_1[7]\); - - un12_res_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \r.timers_2.reload_RNO_0[16]\ : MX2 - port map(A => \reload[16]\, B => pwdata_10, S => - reload_1_sqmuxa_0_0, Y => N_569); - - \r.timers_2.reload[20]\ : DFN1 - port map(D => \reload_RNO[20]\, CLK => lclk_c, Q => - \reload[20]\); - - \r.timers_2.enable_RNO_0\ : MX2 - port map(A => enable_1_0, B => enable_0, S => - enable_1_sqmuxa_0, Y => N_543); - - \r.timers_2.reload_RNO[11]\ : OR2A - port map(A => rstn, B => N_564, Y => \reload_RNO[11]\); - - \r.timers_2.reload_RNO_0[4]\ : MX2 - port map(A => \reload_0[4]\, B => pwdata_0(4), S => - reload_1_sqmuxa_0_0, Y => N_557); - - \r.timers_2.reload[31]\ : DFN1 - port map(D => \reload_RNO[31]\, CLK => lclk_c, Q => - \reload[31]\); - - \r.scaler_RNIMPGF[0]\ : OR2B - port map(A => \scaler[0]\, B => \readdata55\, Y => - scaler_m_0); - - \r.timers_2.value_RNI2DCH[15]\ : OR2A - port map(A => \value[15]\, B => value_0_sqmuxa, Y => - value_m_11); - - \r.timers_1.value_RNO_0[14]\ : MX2C - port map(A => I_84_1, B => \reload_0[14]\, S => - value_1_sn_N_9_i, Y => N_356); - - \r.timers_1.value_RNO[28]\ : MX2A - port map(A => N_370, B => pwdata_22, S => value_1_sqmuxa, Y - => \value_1[28]\); - - un12_res_I_34 : OR3 - port map(A => \value_RNI9J4J[3]\, B => \value_RNIBR4J[4]\, - C => \value_RNID35J[5]\, Y => \DWACT_FDEC_E_0[2]\); - - \r.timers_1.value_RNO_0[18]\ : MX2C - port map(A => I_115_1, B => \reload[18]\, S => - value_1_sn_N_9_i, Y => N_360); - - \r.timers_1.reload[23]\ : DFN1E1 - port map(D => pwdata_17, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[23]\); - - \r.timers_1.reload_RNIG3J51[4]\ : MX2C - port map(A => N_204, B => N_212, S => \N_240\, Y => - readdata_9_4); - - un6_scaler_I_12 : OR3 - port map(A => \scaler[0]\, B => \scaler[1]\, C => - \scaler[2]\, Y => N_27); - - \r.timers_2.value_RNO_0[19]\ : MX2C - port map(A => I_122_1, B => \reload[19]\, S => - value_1_sn_N_9_i_1, Y => N_428); - - \r.timers_2.value[13]\ : DFN1E0 - port map(D => \value_1_0[13]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[13]\); - - \r.timers_1.value_RNIPTUG[21]\ : MX2 - port map(A => \value[21]\, B => \un1_timer0[29]\, S => - \tsel[0]\, Y => \value_RNIPTUG[21]\); - - \r.timers_1.value_RNIFB5J[6]\ : MX2 - port map(A => \value[6]\, B => \un1_timer0[14]\, S => - \tsel_0[0]\, Y => \value_RNIFB5J[6]\); - - un12_res_I_173 : XNOR2 - port map(A => N_40, B => \value_RNI1UUG[25]\, Y => I_173_1); - - \r.timers_1.value[0]\ : DFN1E0 - port map(D => \value_1[0]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[8]\); - - \r.timers_2.reload_RNO[20]\ : NOR2B - port map(A => rstn, B => N_573, Y => \reload_RNO[20]\); - - un12_res_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \r.timers_2.value_RNO_0[24]\ : MX2C - port map(A => I_166_1, B => \reload[24]\, S => - value_1_sn_N_9_i_0, Y => N_433); - - un6_scaler_I_16 : OR3 - port map(A => \scaler[0]\, B => \scaler[1]\, C => - \scaler[2]\, Y => \DWACT_FDEC_E_0[0]\); - - \v.timers_1.reload_1_sqmuxa_0\ : NOR3A - port map(A => readdata30, B => N_6455_0, C => un1_apbi, Y - => reload_1_sqmuxa_0); - - \r.timers_2.value_RNO_0[28]\ : MX2C - port map(A => I_203_1, B => \reload[28]\, S => - value_1_sn_N_9_i_1, Y => N_437); - - \r.scaler_RNO_1[1]\ : MX2 - port map(A => I_5_6, B => \reload_0[1]\, S => I_44, Y => - N_325); - - \r.timers_2.value_RNO[30]\ : MX2A - port map(A => N_439, B => pwdata_24, S => value_1_sqmuxa_1, - Y => \value_1_0[30]\); - - \r.timers_2.value_RNO[8]\ : MX2A - port map(A => N_417, B => pwdata_0(8), S => - value_1_sqmuxa_0_0, Y => \value_1_0[8]\); - - \comb.2.readdata51_1\ : OR2A - port map(A => paddr(5), B => paddr(6), Y => \readdata51_1\); - - \r.timers_1.value_RNID35J[5]\ : MX2 - port map(A => \value[5]\, B => \un1_timer0[13]\, S => - \tsel_0[0]\, Y => \value_RNID35J[5]\); - - \r.timers_1.value_RNI3EJC[14]\ : MX2 - port map(A => \un1_timer0[22]\, B => \reload_0[14]\, S => - paddr_2(2), Y => N_222); - - \r.timers_2.reload_RNO_0[27]\ : MX2 - port map(A => \reload[27]\, B => pwdata_21, S => - reload_1_sqmuxa_1, Y => N_580); - - \r.timers_2.value_RNI0DCH[13]\ : OR2A - port map(A => \value[13]\, B => value_0_sqmuxa, Y => - value_m_9); - - un12_res_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \value_RNIPTUG[21]\, - Y => \DWACT_FDEC_E[16]\); - - \r.timers_2.reload_RNO_0[9]\ : MX2 - port map(A => \reload[9]\, B => pwdata_0(9), S => - reload_1_sqmuxa_0_0, Y => N_562); - - \r.timers_1.value[5]\ : DFN1E0 - port map(D => \value_1[5]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[13]\); - - \r.timers_2.reload[22]\ : DFN1 - port map(D => \reload_RNO[22]\, CLK => lclk_c, Q => - \reload[22]\); - - \r.timers_2.reload_RNO_0[1]\ : MX2 - port map(A => \reload[1]\, B => pwdata_0(1), S => - reload_1_sqmuxa_0_0, Y => N_554); - - \r.timers_2.reload_RNO_0[21]\ : MX2 - port map(A => \reload[21]\, B => pwdata_15, S => - reload_1_sqmuxa_1, Y => N_574); - - \r.timers_2.reload_RNO[16]\ : NOR2B - port map(A => rstn, B => N_569, Y => \reload_RNO[16]\); - - \r.timers_2.value_RNO[31]\ : MX2A - port map(A => N_440, B => pwdata_25, S => value_1_sqmuxa_1, - Y => \value_1[31]\); - - un6_scaler_I_23 : OR3 - port map(A => \DWACT_FDEC_E_0[0]\, B => \scaler[3]\, C => - \scaler[4]\, Y => N_19); - - \r.timers_2.value[26]\ : DFN1E0 - port map(D => \value_1_0[26]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[26]\); - - un12_res_I_199 : OR2 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - Y => \DWACT_FDEC_E[24]\); - - \r.timers_1.value_RNI6IJC[24]\ : MX2 - port map(A => \un1_timer0[32]\, B => \reload_0[24]\, S => - paddr_1(2), Y => N_232_1); - - un12_res_I_206 : OR2 - port map(A => \value_RNI5UUG[27]\, B => \value_RNI7UUG[28]\, - Y => \DWACT_FDEC_E[25]\); - - \r.timers_1.chain\ : DFN1E1 - port map(D => pwdata_0(5), CLK => lclk_c, E => - load_1_sqmuxa_1, Q => chain); - - \r.timers_2.reload_RNO[5]\ : OR2A - port map(A => rstn, B => N_558, Y => \reload_RNO[5]\); - - \r.timers_2.chain_RNO\ : NOR2B - port map(A => rstn, B => N_619, Y => chain_RNO); - - \v.timers_1.value_1_sqmuxa_0\ : NOR3A - port map(A => readdata30, B => N_232_0, C => un1_apbi, Y - => value_1_sqmuxa_0); - - \r.timers_2.value_RNO[23]\ : MX2A - port map(A => N_432, B => pwdata_17, S => value_1_sqmuxa_1, - Y => \value_1_0[23]\); - - \r.timers_1.value_RNO[19]\ : MX2A - port map(A => N_361, B => pwdata_13, S => value_1_sqmuxa, Y - => \value_1[19]\); - - \r.timers_2.value_RNO_0[31]\ : MX2C - port map(A => I_224, B => \reload[31]\, S => - value_1_sn_N_9_i_1, Y => N_440); - - \r.timers_2.value_RNI0HCH[20]\ : OR2A - port map(A => \value[20]\, B => \value_0_sqmuxa_0\, Y => - value_m_16); - - \r.timers_1.reload_RNICRMD[2]\ : MX2 - port map(A => \un1_timer0[10]\, B => \reload_1[2]\, S => - paddr(2), Y => N_210); - - un6_scaler_I_44 : NOR3 - port map(A => \DWACT_FDEC_E[3]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E_0[0]\, Y => I_44); - - \r.timers_1.value_RNO_0[2]\ : MX2C - port map(A => I_9_5, B => \reload_1[2]\, S => - value_1_sn_N_9_i_0_0, Y => N_344); - - \r.timers_2.reload_RNO[28]\ : NOR2B - port map(A => rstn, B => N_581, Y => \reload_RNO[28]\); - - \r.timers_2.value[5]\ : DFN1E0 - port map(D => \value_1_0[5]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[5]\); - - un12_res_I_69 : OR3 - port map(A => \value_RNIL36J[9]\, B => \value_RNI73QI[10]\, - C => \value_RNI93QI[11]\, Y => \DWACT_FDEC_E[7]\); - - un12_res_I_186 : XNOR2 - port map(A => N_31, B => \value_RNI3UUG[26]\, Y => I_186_1); - - \r.scaler_RNO[5]\ : OR2B - port map(A => rstn, B => \scaler_1[5]\, Y => - \scaler_RNO[5]\); - - \r.timers_2.irqpen_RNIM1UI\ : OR2A - port map(A => irqpen, B => \readdata_2_sqmuxa\, Y => - irqpen_m); - - \r.timers_1.irqpen\ : DFN1 - port map(D => irqpen_RNO_0, CLK => lclk_c, Q => irqpen_0); - - \r.timers_2.value_RNO[9]\ : MX2A - port map(A => N_418, B => pwdata_0(9), S => - value_1_sqmuxa_0_0, Y => \value_1_0[9]\); - - \r.reload_RNI84OI[3]\ : OR2A - port map(A => \reload_0[3]\, B => \readdata56\, Y => - reload_m_0_3); - - \r.timers_1.value_RNO_0[16]\ : MX2C - port map(A => I_98_1, B => \reload_0[16]\, S => - value_1_sn_N_9_i, Y => N_358); - - \r.timers_1.value_RNIB3QI[12]\ : MX2 - port map(A => \value[12]\, B => \un1_timer0[20]\, S => - \tsel_0[0]\, Y => \value_RNIB3QI[12]\); - - \r.timers_1.irq\ : DFN1 - port map(D => load_RNIC53BJ, CLK => lclk_c, Q => - \un1_timer0[6]\); - - \comb.un1_apbi_0_0\ : NOR2 - port map(A => N_78, B => \un1_apbi_0\, Y => un1_apbi_0_0); - - \r.timers_1.value[16]\ : DFN1E0 - port map(D => \value_1[16]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[24]\); - - \r.timers_1.restart_RNI0PFV\ : MX2C - port map(A => N_201, B => N_209, S => \N_240\, Y => - \readdata_9[1]\); - - un12_res_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E_0[3]\, Y => \DWACT_FDEC_E[4]\); - - un12_res_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_45); - - \r.timers_2.reload_RNO[29]\ : NOR2B - port map(A => rstn, B => N_582, Y => \reload_RNO[29]\); - - \r.timers_1.value_RNO_0[25]\ : MX2C - port map(A => I_173_1, B => \reload_0[25]\, S => - value_1_sn_N_9_i_0_0, Y => N_367); - - \r.timers_2.value_RNO_0[26]\ : MX2C - port map(A => I_186_1, B => \reload[26]\, S => - value_1_sn_N_9_i_0, Y => N_435); - - \r.timers_2.value_RNO[12]\ : MX2A - port map(A => N_421, B => pwdata_0(12), S => - value_1_sqmuxa_1, Y => \value_1_0[12]\); - - \r.scaler_RNIO1HF[2]\ : OR2B - port map(A => \scaler[2]\, B => \readdata55\, Y => - \scaler_m[2]\); - - \r.reload_RNI6SNI[1]\ : OR2 - port map(A => \reload_0[1]\, B => \readdata56\, Y => - reload_RNI6SNI(1)); - - \r.timers_1.value_RNI7UUG[28]\ : MX2 - port map(A => \value[28]\, B => \un1_timer0[36]\, S => - \tsel[0]\, Y => \value_RNI7UUG[28]\); - - \r.timers_2.reload[14]\ : DFN1 - port map(D => \reload_RNO[14]\, CLK => lclk_c, Q => - \reload[14]\); - - \r.timers_1.value_RNO[29]\ : MX2A - port map(A => N_371, B => pwdata_23, S => value_1_sqmuxa, Y - => \value_1_0[29]\); - - \r.timers_1.reload[18]\ : DFN1E1 - port map(D => pwdata_12, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload[18]\); - - \r.timers_1.irqpen_RNO\ : NOR2A - port map(A => rstn, B => irqpen_1, Y => irqpen_RNO_0); - - \r.scaler_RNO_1[4]\ : MX2 - port map(A => I_20_6, B => \reload[4]\, S => I_44, Y => - N_328); - - \r.timers_1.value[22]\ : DFN1E0 - port map(D => \value_1_0[22]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[30]\); - - \r.timers_1.reload[31]\ : DFN1E1 - port map(D => pwdata_25, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[31]\); - - \r.reload_RNO[2]\ : OR2A - port map(A => rstn, B => N_625, Y => \reload_RNO_0[2]\); - - \r.timers_2.restart_RNO\ : NOR2B - port map(A => rstn, B => N_618, Y => restart_RNO); - - \r.timers_2.reload_RNO_0[6]\ : MX2 - port map(A => \reload[6]\, B => pwdata_0(6), S => - reload_1_sqmuxa_0_0, Y => N_559); - - \r.timers_2.reload[11]\ : DFN1 - port map(D => \reload_RNO[11]\, CLK => lclk_c, Q => - \reload[11]\); - - \r.timers_2.value_RNO[18]\ : MX2A - port map(A => N_427, B => pwdata_12, S => value_1_sqmuxa_1, - Y => \value_1_0[18]\); - - \r.timers_1.reload[27]\ : DFN1E1 - port map(D => pwdata_21, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[27]\); - - un12_res_I_209 : OR3 - port map(A => \DWACT_FDEC_E[24]\, B => \DWACT_FDEC_E[23]\, - C => \DWACT_FDEC_E[25]\, Y => N_14_0); - - \r.timers_2.reload_RNIFVAI[23]\ : OR2A - port map(A => \reload[23]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[23]\); - - \r.timers_1.reload[19]\ : DFN1E1 - port map(D => pwdata_13, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[19]\); - - \r.timers_2.reload[1]\ : DFN1 - port map(D => \reload_RNO[1]\, CLK => lclk_c, Q => - \reload[1]\); - - \r.timers_2.value_RNISJ4P1[18]\ : OR3C - port map(A => \reload_m[18]\, B => \readdata_9[18]\, C => - \value_m[18]\, Y => prdata_4); - - \r.timers_2.value[21]\ : DFN1E0 - port map(D => \value_1_0[21]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[21]\); - - \r.reload[5]\ : DFN1 - port map(D => \reload_RNO_0[5]\, CLK => lclk_c, Q => - \reload_0[5]\); - - \r.timers_2.value[3]\ : DFN1E0 - port map(D => \value_1_0[3]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[3]\); - - \r.scaler_RNO_0[1]\ : MX2C - port map(A => pwdata_0(1), B => N_325, S => scaler_0_sqmuxa, - Y => \scaler_1[1]\); - - \r.timers_2.reload[4]\ : DFN1 - port map(D => \reload_RNO[4]\, CLK => lclk_c, Q => - \reload_0[4]\); - - \r.tsel_RNIG6TH[0]\ : XA1A - port map(A => \tsel[0]\, B => tsel_1_sqmuxa, C => rstn, Y - => \tsel_RNIG6TH[0]\); - - \r.reload_RNO[4]\ : OR2A - port map(A => rstn, B => N_627, Y => \reload_RNO_0[4]\); - - \r.tsel_RNI3KAN[0]\ : NOR2B - port map(A => \tsel[0]\, B => un4_i, Y => irq_0_sqmuxa); - - \r.timers_1.value_RNIVLUG[17]\ : MX2 - port map(A => \value[17]\, B => \un1_timer0[25]\, S => - \tsel[0]\, Y => \value_RNIVLUG[17]\); - - \r.timers_2.reload_RNO[15]\ : OR2A - port map(A => rstn, B => N_568, Y => \reload_RNO[15]\); - - \r.timers_1.reload[16]\ : DFN1E1 - port map(D => pwdata_10, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[16]\); - - un12_res_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_71); - - \r.timers_2.reload_RNO[4]\ : OR2A - port map(A => rstn, B => N_557, Y => \reload_RNO[4]\); - - \r.tsel_RNIHTGN[1]\ : OR2B - port map(A => \tsel[1]\, B => un34_i, Y => irq_0_sqmuxa_0); - - \r.timers_1.reload_RNI6V7C[7]\ : MX2 - port map(A => \un1_timer0[15]\, B => \reload_1[7]\, S => - paddr_1(2), Y => N_215); - - \r.reload_RNO_0[5]\ : MX2 - port map(A => \reload_0[5]\, B => pwdata_0(5), S => - reload_1_sqmuxa_2, Y => N_628); - - \r.timers_1.value_RNO_0[22]\ : MX2C - port map(A => I_143_1, B => \reload_0[22]\, S => - value_1_sn_N_9_i, Y => N_364); - - \r.timers_1.value_RNITTUG[23]\ : MX2 - port map(A => \value[23]\, B => \un1_timer0[31]\, S => - \tsel[0]\, Y => \value_RNITTUG[23]\); - - \r.timers_2.value[18]\ : DFN1E0 - port map(D => \value_1_0[18]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[18]\); - - un12_res_I_159 : OR3 - port map(A => \value_RNIPTUG[21]\, B => \value_RNIRTUG[22]\, - C => \value_RNITTUG[23]\, Y => \DWACT_FDEC_E[17]\); - - \r.timers_2.irqpen_RNO\ : NOR2A - port map(A => rstn, B => irqpen_1_0, Y => irqpen_RNO); - - \r.timers_1.value_RNINTUG[20]\ : MX2 - port map(A => \value[20]\, B => \un1_timer0[28]\, S => - \tsel[0]\, Y => \value_RNINTUG[20]\); - - \r.timers_2.load\ : DFN1 - port map(D => load_RNO_0, CLK => lclk_c, Q => load_0); - - \r.timers_1.value_RNO_0[20]\ : MX2C - port map(A => I_129_1, B => \reload_0[20]\, S => - value_1_sn_N_9_i, Y => N_362); - - \r.timers_1.chain_RNI6LP21\ : MX2C - port map(A => N_205, B => N_213, S => \N_240\, Y => - readdata_9_5); - - \r.timers_1.value[11]\ : DFN1E0 - port map(D => \value_1[11]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[19]\); - - un6_scaler_I_24 : XNOR2 - port map(A => N_19, B => \scaler[5]\, Y => I_24_7); - - un12_res_I_24 : XNOR2 - port map(A => N_146, B => \value_RNID35J[5]\, Y => I_24_6); - - \r.timers_2.reload_RNIDNAI[21]\ : OR2A - port map(A => \reload[21]\, B => \readdata_1_sqmuxa_1\, Y - => reload_m_21); - - \r.timers_1.value_RNI1AJC[13]\ : MX2 - port map(A => \un1_timer0[21]\, B => \reload_0[13]\, S => - paddr_2(2), Y => N_221); - - \r.timers_2.value_RNO_0[3]\ : MX2C - port map(A => I_13_9, B => \reload[3]\, S => - value_1_sn_N_9_i_0, Y => N_412); - - \r.timers_2.value_RNI2HCH[22]\ : OR2A - port map(A => \value[22]\, B => \value_0_sqmuxa_0\, Y => - value_m_18); - - \r.timers_2.value_RNO[25]\ : MX2A - port map(A => N_434, B => pwdata_19, S => - value_1_sqmuxa_0_0, Y => \value_1_0[25]\); - - un12_res_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \value_RNIL36J[9]\, C - => \value_RNI73QI[10]\, Y => N_116); - - \r.timers_1.value[3]\ : DFN1E0 - port map(D => \value_1[3]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[11]\); - - un12_res_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \value_RNIPTUG[21]\, - C => \value_RNIRTUG[22]\, Y => \DWACT_FDEC_E[33]\); - - \r.timers_2.value_RNIH2IH[7]\ : OR2A - port map(A => \value[7]\, B => value_0_sqmuxa, Y => - value_m_3); - - \r.timers_2.load_RNIP9AN3\ : NOR3A - port map(A => irq_0_sqmuxa_0, B => load_0, C => - value_1_sqmuxa_0_0, Y => value_2_sqmuxa); - - un12_res_I_51 : OR2 - port map(A => \value_RNIJR5J[8]\, B => \DWACT_FDEC_E[4]\, Y - => N_126); - - \r.timers_1.value_RNI4IJC[15]\ : MX2 - port map(A => \un1_timer0[23]\, B => \reload_0[15]\, S => - paddr_1(2), Y => N_223); - - \r.reload_RNO[3]\ : OR2A - port map(A => rstn, B => N_626, Y => \reload_RNO_0[3]\); - - \v.timers_2.value_1_sqmuxa\ : NOR2 - port map(A => value_0_sqmuxa, B => un1_apbi, Y => - value_1_sqmuxa_1); - - un12_res_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E_0[3]\, Y => N_131); - - un12_res_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \value_RNIB3QI[12]\, Y => N_108); - - \r.timers_2.reload_RNO_0[25]\ : MX2 - port map(A => \reload[25]\, B => pwdata_19, S => - reload_1_sqmuxa_1, Y => N_578); - - \r.timers_2.reload[15]\ : DFN1 - port map(D => \reload_RNO[15]\, CLK => lclk_c, Q => - \reload[15]\); - - \r.timers_2.reload_RNO[14]\ : OR2A - port map(A => rstn, B => N_567, Y => \reload_RNO[14]\); - - \r.timers_2.reload_RNO[1]\ : OR2A - port map(A => rstn, B => N_554, Y => \reload_RNO[1]\); - - \r.timers_2.reload[17]\ : DFN1 - port map(D => \reload_RNO[17]\, CLK => lclk_c, Q => - \reload[17]\); - - \r.timers_2.value_RNIHJ3P1[23]\ : OR3C - port map(A => \reload_m[23]\, B => \readdata_9[23]\, C => - \value_m[23]\, Y => prdata_9); - - \r.timers_1.value_RNI8MJC[25]\ : MX2 - port map(A => \un1_timer0[33]\, B => \reload_0[25]\, S => - paddr_1(2), Y => N_233); - - \r.timers_1.value[29]\ : DFN1E0 - port map(D => \value_1_0[29]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[37]\); - - \r.timers_2.irqpen\ : DFN1 - port map(D => irqpen_RNO, CLK => lclk_c, Q => irqpen); - - un12_res_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_40); - - \r.timers_2.value_RNIFBLN1[19]\ : AO1C - port map(A => \value_0_sqmuxa_0\, B => \value[19]\, C => - \readdata_1_iv_0[19]\, Y => prdata_5); - - \comb.1.readdata_9_sn_m3_0\ : NOR2A - port map(A => readdata30, B => paddr_0(3), Y => \N_240_0\); - - \comb.1.readdata_9_i_m_0[1]\ : AOI1 - port map(A => readdata51, B => \un1_apbi_2\, C => - un1_apbi_7_3, Y => \readdata_9_i_m_0[1]\); - - \r.timers_2.value_RNO[19]\ : MX2A - port map(A => N_428, B => pwdata_13, S => value_1_sqmuxa_1, - Y => \value_1_0[19]\); - - \r.reload_RNO[6]\ : OR2A - port map(A => rstn, B => N_629, Y => \reload_RNO_0[6]\); - - \r.reload_RNO[0]\ : OR2A - port map(A => rstn, B => N_623, Y => \reload_RNO_0[0]\); - - \r.timers_1.value_RNIRTUG[22]\ : MX2 - port map(A => \value[22]\, B => \un1_timer0[30]\, S => - \tsel[0]\, Y => \value_RNIRTUG[22]\); - - \r.timers_1.value_RNIF3QI[14]\ : MX2 - port map(A => \value[14]\, B => \un1_timer0[22]\, S => - \tsel_0[0]\, Y => \value_RNIF3QI[14]\); - - \r.timers_1.enable\ : DFN1 - port map(D => enable_RNO, CLK => lclk_c, Q => enable); - - \r.timers_1.value_RNO_0[5]\ : MX2C - port map(A => I_24_6, B => \reload_1[5]\, S => - value_1_sn_N_9_i_0_0, Y => N_347); - - \r.timers_1.reload[11]\ : DFN1E1 - port map(D => pwdata_0(11), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[11]\); - - un12_res_I_125 : OR2 - port map(A => \value_RNI1MUG[18]\, B => \value_RNI3MUG[19]\, - Y => \DWACT_FDEC_E[14]\); - - \r.timers_1.value_RNITT761[15]\ : AOI1B - port map(A => \N_240_0\, B => N_223, C => \reload_m[15]\, Y - => readdata_1_iv_0_2); - - \r.timers_2.value[0]\ : DFN1E0 - port map(D => \value_1_0[0]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[0]\); - - \r.timers_2.value_RNO_0[13]\ : MX2C - port map(A => I_77_1, B => \reload[13]\, S => - value_1_sn_N_9_i_0, Y => N_422); - - un6_scaler_I_20 : XNOR2 - port map(A => N_22, B => \scaler[4]\, Y => I_20_6); - - \r.timers_1.value[20]\ : DFN1E0 - port map(D => \value_1_0[20]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[28]\); - - \r.scaler_RNO_0[5]\ : MX2C - port map(A => pwdata_0(5), B => N_329, S => scaler_0_sqmuxa, - Y => \scaler_1[5]\); - - \r.timers_1.restart\ : DFN1E1 - port map(D => pwdata_1_0, CLK => lclk_c, E => - load_1_sqmuxa_1, Q => restart_0); - - \r.timers_1.irq_RNIBSFB\ : NOR2B - port map(A => \un1_timer0[6]\, B => irqen_0, Y => pirq(8)); - - \r.scaler_RNIRDHF[5]\ : OR2B - port map(A => \scaler[5]\, B => \readdata55\, Y => - scaler_m_5); - - \r.timers_1.value_RNIRL761[14]\ : AOI1B - port map(A => \N_240_0\, B => N_222, C => \reload_m[14]\, Y - => \readdata_1_iv_0[14]\); - - \r.scaler_RNO_1[6]\ : MX2 - port map(A => I_31_5, B => \reload_0[6]\, S => I_44, Y => - N_330); - - \r.timers_1.value_RNO_0[0]\ : MX2B - port map(A => \value_RNI3R3J[0]\, B => \reload_1[0]\, S => - value_1_sn_N_9_i_0_0, Y => N_342); - - \r.timers_1.reload_RNISQBL[30]\ : OR2B - port map(A => \N_240\, B => N_238, Y => \readdata_9[30]\); - - \r.timers_2.value[25]\ : DFN1E0 - port map(D => \value_1_0[25]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[25]\); - - \comb.readdata56\ : OR2A - port map(A => rdata59_4, B => paddr(6), Y => \readdata56\); - - \r.timers_2.irqen_RNO_0\ : MX2 - port map(A => irqen, B => pwdata_1_2, S => load_1_sqmuxa_0, - Y => N_617); - - \r.timers_1.reload[1]\ : DFN1E1 - port map(D => pwdata_1_0, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_1[1]\); - - \r.timers_2.load_RNIP9AN3_0\ : NOR3A - port map(A => irq_0_sqmuxa_0, B => load_0, C => - value_1_sqmuxa_0_0, Y => value_2_sqmuxa_0_0); - - \r.timers_1.reload[14]\ : DFN1E1 - port map(D => pwdata_0(14), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[14]\); - - \r.timers_2.reload[18]\ : DFN1 - port map(D => \reload_RNO[18]\, CLK => lclk_c, Q => - \reload_0[18]\); - - \r.timers_1.reload[4]\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[4]\); - - \r.reload_RNI70OI[2]\ : OR2A - port map(A => \reload_0[2]\, B => \readdata56\, Y => - reload_m_0_2); - - \r.timers_1.value_RNIL36J[9]\ : MX2 - port map(A => \value[9]\, B => \un1_timer0[17]\, S => - \tsel_0[0]\, Y => \value_RNIL36J[9]\); - - \r.timers_2.reload_RNO_0[31]\ : MX2 - port map(A => \reload[31]\, B => pwdata_25, S => - reload_1_sqmuxa_1, Y => N_584); - - \r.timers_1.value_RNO_0[30]\ : MX2C - port map(A => I_217, B => \reload_0[30]\, S => - value_1_sn_N_9_i, Y => N_372); - - \r.tsel[0]\ : DFN1 - port map(D => \tsel_RNIG6TH[0]\, CLK => lclk_c, Q => - \tsel[0]\); - - \r.timers_2.reload_RNO[17]\ : NOR2B - port map(A => rstn, B => N_570, Y => \reload_RNO[17]\); - - \r.timers_1.value[2]\ : DFN1E0 - port map(D => \value_1[2]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[10]\); - - \r.timers_2.irqen_RNO\ : OR2A - port map(A => rstn, B => N_617, Y => irqen_RNO_0); - - \r.timers_2.reload[16]\ : DFN1 - port map(D => \reload_RNO[16]\, CLK => lclk_c, Q => - \reload[16]\); - - \r.timers_2.reload_RNO_0[18]\ : MX2 - port map(A => \reload_0[18]\, B => pwdata_12, S => - reload_1_sqmuxa_1, Y => N_571); - - \r.timers_1.value[15]\ : DFN1E0 - port map(D => \value_1_0[15]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[23]\); - - \r.timers_2.irq_RNIF1IB\ : OR2B - port map(A => \un1_timer0[5]\, B => irqen, Y => pirq(9)); - - \r.timers_1.irqen_RNIVVE11\ : MX2C - port map(A => N_203, B => N_211, S => \N_240\, Y => - \readdata_9[3]\); - - \r.timers_2.reload_RNO_0[24]\ : MX2 - port map(A => \reload[24]\, B => pwdata_18, S => - reload_1_sqmuxa_1, Y => N_577); - - \r.reload_RNIACOI[5]\ : OR2A - port map(A => \reload_0[5]\, B => \readdata56\, Y => - reload_m_5); - - \r.timers_1.value_RNO_0[4]\ : MX2C - port map(A => I_20_5, B => \reload_1[4]\, S => - value_1_sn_N_9_i_0_0, Y => N_346); - - \r.timers_2.enable_RNIEAGI\ : OR2A - port map(A => enable_0, B => \readdata_2_sqmuxa\, Y => - enable_m); - - un12_res_I_5 : XNOR2 - port map(A => \value_RNI3R3J[0]\, B => \value_RNI534J[1]\, - Y => I_5_5); - - \r.timers_2.value[24]\ : DFN1E0 - port map(D => \value_1_0[24]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[24]\); - - \r.timers_2.enable_RNO_2\ : OA1C - port map(A => \tsel[1]\, B => irqpen_0_sqmuxa_1_0, C => - load_1_sqmuxa_0, Y => enable_1_sqmuxa_0); - - \r.timers_1.value_RNO_0[15]\ : MX2C - port map(A => I_91_1, B => \reload_0[15]\, S => - value_1_sn_N_9_i, Y => N_357); - - \r.timers_1.value_RNO_0[21]\ : MX2C - port map(A => I_136_1, B => \reload_0[21]\, S => - value_1_sn_N_9_i, Y => N_363); - - un12_res_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_103); - - un12_res_I_166 : XNOR2 - port map(A => N_45, B => \value_RNIVTUG[24]\, Y => I_166_1); - - \r.timers_1.value_RNIVACL[16]\ : OR2B - port map(A => \N_240\, B => N_224, Y => \readdata_9[16]\); - - \r.timers_2.value_RNO_0[25]\ : MX2C - port map(A => I_173_1, B => \reload[25]\, S => - value_1_sn_N_9_i_0, Y => N_434); - - \r.timers_2.value_RNO_0[14]\ : MX2C - port map(A => I_84_1, B => \reload[14]\, S => - value_1_sn_N_9_i_1, Y => N_423); - - \r.timers_2.reload_RNIDJAI[30]\ : OR2A - port map(A => \reload[30]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => \reload_m[30]\); - - \r.timers_2.value_RNO_0[18]\ : MX2C - port map(A => I_115_1, B => \reload_0[18]\, S => - value_1_sn_N_9_i_1, Y => N_427); - - \r.timers_1.value[30]\ : DFN1E0 - port map(D => \value_1[30]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[38]\); - - \r.timers_1.value_RNIHJ5J[7]\ : MX2 - port map(A => \value[7]\, B => \un1_timer0[15]\, S => - \tsel_0[0]\, Y => \value_RNIHJ5J[7]\); - - \r.timers_2.value_RNO[3]\ : MX2A - port map(A => N_412, B => pwdata_0(3), S => - value_1_sqmuxa_0_0, Y => \value_1_0[3]\); - - \r.timers_2.reload[24]\ : DFN1 - port map(D => \reload_RNO[24]\, CLK => lclk_c, Q => - \reload[24]\); - - \r.timers_1.reload[28]\ : DFN1E1 - port map(D => pwdata_22, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[28]\); - - \r.scaler_RNO_1[7]\ : MX2 - port map(A => I_38_3, B => \reload_0[7]\, S => I_44, Y => - N_331); - - \r.timers_2.restart_RNI607KI_0\ : AO1 - port map(A => restart, B => un19_res, C => load_0, Y => - value_1_sn_N_9_i_0); - - \r.timers_2.value_RNO[1]\ : MX2A - port map(A => N_410, B => pwdata_1_0, S => value_1_sqmuxa_1, - Y => \value_1_0[1]\); - - \r.timers_1.load_RNI0B3K3\ : NOR3 - port map(A => irq_0_sqmuxa, B => load, C => - value_1_sqmuxa_0, Y => value_2_sqmuxa_1); - - un12_res_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_111); - - \r.timers_1.value_RNI93QI[11]\ : MX2 - port map(A => \value[11]\, B => \un1_timer0[19]\, S => - \tsel_0[0]\, Y => \value_RNI93QI[11]\); - - \r.timers_2.value_RNIVCCH[12]\ : OR2A - port map(A => \value[12]\, B => \value_0_sqmuxa_0\, Y => - value_m_8); - - \r.timers_1.value[14]\ : DFN1E0 - port map(D => \value_1_0[14]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[22]\); - - \r.reload_RNO_0[4]\ : MX2 - port map(A => \reload[4]\, B => pwdata_0(4), S => - reload_1_sqmuxa_2, Y => N_627); - - un6_scaler_I_19 : OR2 - port map(A => \scaler[3]\, B => \DWACT_FDEC_E_0[0]\, Y => - N_22); - - \r.timers_2.load_RNIMG8U2\ : NOR3C - port map(A => \reload_m[2]\, B => \readdata_iv_0[2]\, C => - \readdata_iv_2[2]\, Y => readdata_iv_3(2)); - - \r.timers_2.value_RNO[27]\ : MX2A - port map(A => N_436, B => pwdata_21, S => value_1_sqmuxa_1, - Y => \value_1_0[27]\); - - \r.timers_2.reload[21]\ : DFN1 - port map(D => \reload_RNO[21]\, CLK => lclk_c, Q => - \reload[21]\); - - \r.timers_2.value_RNO[24]\ : MX2A - port map(A => N_433, B => pwdata_18, S => - value_1_sqmuxa_0_0, Y => \value_1_0[24]\); - - \r.timers_2.value[17]\ : DFN1E0 - port map(D => \value_1_0[17]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[17]\); - - \r.scaler[1]\ : DFN1 - port map(D => \scaler_RNO[1]\, CLK => lclk_c, Q => - \scaler[1]\); - - un12_res_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_66); - - \r.timers_1.reload[29]\ : DFN1E1 - port map(D => pwdata_23, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[29]\); - - \r.timers_2.value_RNI7HCH[27]\ : OR2A - port map(A => \value[27]\, B => value_0_sqmuxa, Y => - value_m_23); - - \r.timers_1.value_RNO_0[12]\ : MX2C - port map(A => I_73_1, B => \reload_0[12]\, S => - value_1_sn_N_9_i, Y => N_354); - - \r.timers_1.value_RNIT5VG[30]\ : MX2 - port map(A => \value[30]\, B => \un1_timer0[38]\, S => - \tsel[0]\, Y => \value_RNIT5VG[30]\); - - un12_res_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_24); - - \r.timers_1.chain_RNITONI\ : OA1A - port map(A => chain, B => \un1_timer0[5]\, C => enable, Y - => un4_i); - - \r.timers_2.value_RNI6HCH[26]\ : OR2A - port map(A => \value[26]\, B => \value_0_sqmuxa_0\, Y => - value_m_22); - - \r.timers_2.value[23]\ : DFN1E0 - port map(D => \value_1_0[23]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[23]\); - - \r.timers_1.value_RNO_0[10]\ : MX2C - port map(A => I_56_2, B => \reload_0[10]\, S => - value_1_sn_N_9_i_0_0, Y => N_352); - - \r.timers_1.value_RNO_0[27]\ : MX2C - port map(A => I_196_1, B => \reload_0[27]\, S => - value_1_sn_N_9_i, Y => N_369); - - \r.timers_1.value_RNIC2KC[19]\ : MX2 - port map(A => \un1_timer0[27]\, B => \reload_0[19]\, S => - paddr_1(2), Y => N_227); - - un12_res_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \r.timers_1.value_RNI5A861[26]\ : AOI1B - port map(A => \N_240_0\, B => N_234, C => \reload_m[26]\, Y - => readdata_1_iv_0_13); - - \r.timers_2.enable_RNO\ : OR2A - port map(A => rstn, B => N_543, Y => enable_RNO_0); - - \r.timers_1.reload[26]\ : DFN1E1 - port map(D => pwdata_20, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[26]\); - - \r.timers_2.value_RNO_0[22]\ : MX2C - port map(A => I_143_1, B => \reload[22]\, S => - value_1_sn_N_9_i_0, Y => N_431); - - \r.timers_2.reload[0]\ : DFN1 - port map(D => \reload_RNO[0]\, CLK => lclk_c, Q => - \reload[0]\); - - un6_scaler_I_5 : XNOR2 - port map(A => \scaler[0]\, B => \scaler[1]\, Y => I_5_6); - - un12_res_I_223 : OR3 - port map(A => \DWACT_FDEC_E[24]\, B => \DWACT_FDEC_E[23]\, - C => \DWACT_FDEC_E[27]\, Y => N_4); - - un12_res_I_143 : XNOR2 - port map(A => N_61, B => \value_RNIRTUG[22]\, Y => I_143_1); - - \r.timers_2.value_RNO_0[20]\ : MX2C - port map(A => I_129_1, B => \reload[20]\, S => - value_1_sn_N_9_i_1, Y => N_429); - - \r.reload_RNO[5]\ : OR2A - port map(A => rstn, B => N_628, Y => \reload_RNO_0[5]\); - - \r.timers_1.reload_RNIQTIC[10]\ : MX2 - port map(A => \un1_timer0[18]\, B => \reload_0[10]\, S => - paddr_1(2), Y => N_218); - - \r.timers_2.reload_RNO[7]\ : OR2A - port map(A => rstn, B => N_560, Y => \reload_RNO[7]\); - - un12_res_I_210 : XNOR2 - port map(A => N_14_0, B => \value_RNI9UUG[29]\, Y => - I_210_1); - - \r.timers_1.value[26]\ : DFN1E0 - port map(D => \value_1[26]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[34]\); - - \r.timers_1.value_RNO[10]\ : MX2A - port map(A => N_352, B => pwdata_0(10), S => - value_1_sqmuxa_0, Y => \value_1[10]\); - - \r.timers_2.value_RNO_0[16]\ : MX2C - port map(A => I_98_1, B => \reload[16]\, S => - value_1_sn_N_9_i_1, Y => N_425); - - \r.timers_1.value_RNO[5]\ : MX2A - port map(A => N_347, B => pwdata_0(5), S => - value_1_sqmuxa_0, Y => \value_1[5]\); - - \r.timers_2.reload[19]\ : DFN1 - port map(D => \reload_RNO[19]\, CLK => lclk_c, Q => - \reload[19]\); - - \r.timers_1.value[13]\ : DFN1E0 - port map(D => \value_1[13]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[21]\); - - un6_scaler_I_8 : OR2 - port map(A => \scaler[1]\, B => \scaler[0]\, Y => N_30); - - \v.reload_1_sqmuxa\ : NOR2 - port map(A => un1_apbi, B => \readdata56\, Y => - reload_1_sqmuxa_2); - - \r.tsel[1]\ : DFN1 - port map(D => \tsel_RNO[1]\, CLK => lclk_c, Q => \tsel[1]\); - - \r.timers_1.value_RNO_0[31]\ : MX2C - port map(A => I_224, B => \reload_0[31]\, S => - value_1_sn_N_9_i, Y => N_373); - - \r.timers_1.value_RNO[11]\ : MX2A - port map(A => N_353, B => pwdata_0(11), S => - value_1_sqmuxa_0, Y => \value_1[11]\); - - \r.timers_2.reload_RNIENAI[31]\ : OR2A - port map(A => \reload[31]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[31]\); - - \r.timers_2.value_RNO_0[2]\ : MX2C - port map(A => I_9_5, B => \reload[2]\, S => - value_1_sn_N_9_i_0, Y => N_411); - - \r.timers_1.value_RNO_0[9]\ : MX2C - port map(A => I_52_2, B => \reload_0[9]\, S => - value_1_sn_N_9_i_0_0, Y => N_351); - - \r.timers_1.value[6]\ : DFN1E0 - port map(D => \value_1[6]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[14]\); - - \r.timers_2.reload_RNO_0[22]\ : MX2 - port map(A => \reload[22]\, B => pwdata_16, S => - reload_1_sqmuxa_1, Y => N_575); - - \r.timers_1.value_RNO[20]\ : MX2A - port map(A => N_362, B => pwdata_14, S => value_1_sqmuxa, Y - => \value_1_0[20]\); - - \r.timers_1.value_RNIV5VG[31]\ : MX2 - port map(A => \value[31]\, B => \un1_timer0[39]\, S => - \tsel[0]\, Y => \value_RNIV5VG[31]\); - - \v.timers_1.load_1_sqmuxa\ : OR2A - port map(A => readdata30, B => \rdata60_1\, Y => - load_1_sqmuxa); - - \r.timers_2.reload[25]\ : DFN1 - port map(D => \reload_RNO[25]\, CLK => lclk_c, Q => - \reload[25]\); - - un12_res_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_81); - - \r.timers_2.value_RNO_0[1]\ : MX2C - port map(A => I_5_5, B => \reload[1]\, S => - value_1_sn_N_9_i_1, Y => N_410); - - \r.timers_2.value[1]\ : DFN1E0 - port map(D => \value_1_0[1]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[1]\); - - \r.timers_2.reload[27]\ : DFN1 - port map(D => \reload_RNO[27]\, CLK => lclk_c, Q => - \reload[27]\); - - \r.timers_1.reload_RNIBMM71[31]\ : AOI1B - port map(A => \N_240_0\, B => N_239, C => \reload_m[31]\, Y - => \readdata_1_iv_0[31]\); - - \r.timers_2.reload_RNO[3]\ : OR2A - port map(A => rstn, B => N_556, Y => \reload_RNO[3]\); - - \r.timers_1.value_RNO[16]\ : MX2A - port map(A => N_358, B => pwdata_10, S => value_1_sqmuxa, Y - => \value_1[16]\); - - \r.timers_1.reload_RNIANMD[1]\ : MX2 - port map(A => \un1_timer0[9]\, B => \reload_1[1]\, S => - paddr(2), Y => N_209); - - \comb.readdata55_3\ : OR2 - port map(A => rdata61_2, B => N_232_0, Y => \readdata55_3\); - - \r.scaler_RNO[7]\ : OR2B - port map(A => rstn, B => \scaler_1[7]\, Y => - \scaler_RNO[7]\); - - \r.timers_2.reload_RNO_0[17]\ : MX2 - port map(A => \reload[17]\, B => pwdata_11, S => - reload_1_sqmuxa_1, Y => N_570); - - \r.timers_2.reload_RNO_0[3]\ : MX2 - port map(A => \reload[3]\, B => pwdata_0(3), S => - reload_1_sqmuxa_0_0, Y => N_556); - - \r.timers_2.restart_RNI607KI\ : AO1 - port map(A => restart, B => un19_res, C => load_0, Y => - value_1_sn_N_9_i_1); - - \r.timers_1.value[1]\ : DFN1E0 - port map(D => \value_1[1]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[9]\); - - \r.timers_1.value_RNO[21]\ : MX2A - port map(A => N_363, B => pwdata_15, S => value_1_sqmuxa, Y - => \value_1[21]\); - - \r.scaler_RNO[2]\ : OR2B - port map(A => rstn, B => \scaler_1[2]\, Y => - \scaler_RNO[2]\); - - \r.timers_2.reload_RNO[12]\ : OR2A - port map(A => rstn, B => N_565, Y => \reload_RNO[12]\); - - \r.timers_2.irq_RNO\ : NOR3B - port map(A => \tsel[1]\, B => rstn, C => - irqpen_0_sqmuxa_1_0, Y => irq_RNO); - - un12_res_I_73 : XNOR2 - port map(A => N_111, B => \value_RNIB3QI[12]\, Y => I_73_1); - - \r.timers_2.reload_RNO_0[11]\ : MX2 - port map(A => \reload[11]\, B => pwdata_0(11), S => - reload_1_sqmuxa_0_0, Y => N_564); - - \r.timers_1.reload[21]\ : DFN1E1 - port map(D => pwdata_15, CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[21]\); - - \r.timers_2.reload_RNIJJBI[18]\ : OR2A - port map(A => \reload_0[18]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => \reload_m[18]\); - - \r.timers_2.value_RNIC33P1[30]\ : OR3C - port map(A => \reload_m[30]\, B => \readdata_9[30]\, C => - \value_m[30]\, Y => prdata_16); - - \r.timers_1.value_RNI5UUG[27]\ : MX2 - port map(A => \value[27]\, B => \un1_timer0[35]\, S => - \tsel[0]\, Y => \value_RNI5UUG[27]\); - - \r.timers_2.chain_RNO_0\ : MX2 - port map(A => chain_0, B => pwdata_0(5), S => - load_1_sqmuxa_0, Y => N_619); - - \r.timers_2.value_RNO[0]\ : MX2A - port map(A => N_409, B => pwdata_0(0), S => - value_1_sqmuxa_0_0, Y => \value_1_0[0]\); - - \r.scaler_RNO_0[2]\ : MX2C - port map(A => pwdata_0(2), B => N_326, S => scaler_0_sqmuxa, - Y => \scaler_1[2]\); - - un12_res_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_52); - - \r.scaler[4]\ : DFN1 - port map(D => \scaler_RNO[4]\, CLK => lclk_c, Q => - \scaler[4]\); - - \r.tick\ : DFN1 - port map(D => I_44, CLK => lclk_c, Q => \un1_timer0[7]\); - - \r.timers_1.value_RNO[26]\ : MX2A - port map(A => N_368, B => pwdata_20, S => value_1_sqmuxa_0, - Y => \value_1[26]\); - - \r.timers_1.value[21]\ : DFN1E0 - port map(D => \value_1[21]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[29]\); - - \r.timers_2.reload_RNI3ERG[9]\ : OR2A - port map(A => \reload[9]\, B => \readdata_1_sqmuxa_1\, Y - => reload_m_9); - - un12_res_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \r.reload_RNO_0[6]\ : MX2 - port map(A => \reload_0[6]\, B => pwdata_0(6), S => - reload_1_sqmuxa_2, Y => N_629); - - \r.timers_2.reload_RNIIFBI[17]\ : OR2A - port map(A => \reload[17]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[17]\); - - \r.reload_RNO_0[2]\ : MX2 - port map(A => \reload_0[2]\, B => pwdata_0(2), S => - reload_1_sqmuxa_2, Y => N_625); - - \r.timers_2.reload_RNIRDRG[1]\ : OR2 - port map(A => readdata_1_sqmuxa_1_0_net_1, B => \reload[1]\, - Y => reload_RNIRDRG(1)); - - \r.timers_2.irqpen_RNO_1\ : AO1D - port map(A => irqpen_0_sqmuxa_0, B => irqpen_0_sqmuxa_1_0, - C => irqpen, Y => irqpen_4_0); - - \r.timers_1.value_RNI5EJC[23]\ : MX2 - port map(A => \un1_timer0[31]\, B => \reload_0[23]\, S => - paddr_2(2), Y => N_231); - - \r.timers_2.reload_RNO[21]\ : NOR2B - port map(A => rstn, B => N_574, Y => \reload_RNO[21]\); - - \r.timers_2.load_RNIS3O6J\ : OR3B - port map(A => un34_i, B => un19_res, C => load_0, Y => - irqpen_0_sqmuxa_1_0); - - \r.timers_1.reload[24]\ : DFN1E1 - port map(D => pwdata_18, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[24]\); - - \r.timers_1.load_RNI9HOJI\ : NOR2A - port map(A => un19_res, B => load, Y => irq_2); - - \r.timers_1.reload_RNIB78C[9]\ : MX2 - port map(A => \un1_timer0[17]\, B => \reload_0[9]\, S => - paddr_2(2), Y => N_217); - - \r.timers_2.value[12]\ : DFN1E0 - port map(D => \value_1_0[12]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[12]\); - - \r.timers_2.reload[28]\ : DFN1 - port map(D => \reload_RNO[28]\, CLK => lclk_c, Q => - \reload[28]\); - - \r.timers_2.value[6]\ : DFN1E0 - port map(D => \value_1_0[6]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[6]\); - - \r.timers_2.reload_RNIQDRG[0]\ : OR2A - port map(A => \reload[0]\, B => readdata_1_sqmuxa_1_0_net_1, - Y => reload_m_0_0); - - \r.timers_1.value_RNI8QJC[17]\ : MX2 - port map(A => \un1_timer0[25]\, B => \reload_0[17]\, S => - paddr_1(2), Y => N_225); - - \r.timers_2.value_RNO[22]\ : MX2A - port map(A => N_431, B => pwdata_16, S => - value_1_sqmuxa_0_0, Y => \value_1[22]\); - - \r.timers_2.value[2]\ : DFN1E0 - port map(D => \value_1_0[2]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[2]\); - - un12_res_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \r.timers_2.reload_RNO_0[20]\ : MX2 - port map(A => \reload[20]\, B => pwdata_14, S => - reload_1_sqmuxa_1, Y => N_573); - - \r.timers_2.reload_RNO_0[23]\ : MX2 - port map(A => \reload[23]\, B => pwdata_17, S => - reload_1_sqmuxa_1, Y => N_576); - - \r.timers_2.reload_RNO[30]\ : NOR2B - port map(A => rstn, B => N_583, Y => \reload_RNO[30]\); - - \r.timers_2.irqpen_RNO_2\ : OR2B - port map(A => irqen, B => \tsel[1]\, Y => irqpen_0_sqmuxa_0); - - \r.timers_2.reload[2]\ : DFN1 - port map(D => \reload_RNO[2]\, CLK => lclk_c, Q => - \reload[2]\); - - \r.timers_1.reload[0]\ : DFN1E1 - port map(D => pwdata_0(0), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_1[0]\); - - \r.timers_1.value_RNO_0[11]\ : MX2C - port map(A => I_66_2, B => \reload_0[11]\, S => - value_1_sn_N_9_i_0_0, Y => N_353); - - \r.timers_2.value[28]\ : DFN1E0 - port map(D => \value_1_0[28]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[28]\); - - \r.timers_1.value_RNIT5JC[12]\ : MX2 - port map(A => \un1_timer0[20]\, B => \reload_0[12]\, S => - paddr_0(2), Y => N_220); - - \r.timers_2.reload_RNIG3BI[24]\ : OR2A - port map(A => \reload[24]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[24]\); - - \r.timers_2.reload[26]\ : DFN1 - port map(D => \reload_RNO[26]\, CLK => lclk_c, Q => - \reload[26]\); - - \r.timers_2.irqen_RNI8S323\ : NOR3C - port map(A => \reload_m[3]\, B => \readdata_iv_0[3]\, C => - \readdata_iv_2[3]\, Y => readdata_iv_3(3)); - - \r.timers_1.restart_RNIC90KI_0\ : AO1 - port map(A => restart_0, B => un19_res, C => load, Y => - value_1_sn_N_9_i_0_0); - - \r.timers_2.value_RNI1HCH[21]\ : OR2A - port map(A => \value[21]\, B => value_0_sqmuxa, Y => - value_m_17); - - \r.timers_1.reload_RNIS1JC[11]\ : MX2 - port map(A => \un1_timer0[19]\, B => \reload_0[11]\, S => - paddr_1(2), Y => N_219); - - \comb.un1_apbi\ : OR3C - port map(A => N_769, B => N_773, C => un1_apbi_0_0, Y => - un1_apbi); - - \r.timers_2.value_RNO[28]\ : MX2A - port map(A => N_437, B => pwdata_22, S => value_1_sqmuxa_1, - Y => \value_1_0[28]\); - - \r.timers_2.value_RNO_0[21]\ : MX2C - port map(A => I_136_1, B => \reload[21]\, S => - value_1_sn_N_9_i_1, Y => N_430); - - \r.timers_1.value_RNO_0[3]\ : MX2C - port map(A => I_13_9, B => \reload_1[3]\, S => - value_1_sn_N_9_i_0_0, Y => N_345); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.timers_2.irqpen_RNO_0\ : AO1B - port map(A => load_1_sqmuxa_0, B => pwdata_0(4), C => - irqpen_4_0, Y => irqpen_1_0); - - \r.timers_1.value_RNIAUJC[18]\ : MX2 - port map(A => \un1_timer0[26]\, B => \reload[18]\, S => - paddr_1(2), Y => N_226); - - \r.scaler_RNO_1[5]\ : MX2 - port map(A => I_24_7, B => \reload_0[5]\, S => I_44, Y => - N_329); - - un12_res_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_88); - - \r.timers_2.value_RNI4HCH[24]\ : OR2A - port map(A => \value[24]\, B => value_0_sqmuxa, Y => - value_m_20); - - \r.timers_2.reload_RNO[6]\ : OR2A - port map(A => rstn, B => N_559, Y => \reload_RNO[6]\); - - \r.timers_1.value[7]\ : DFN1E0 - port map(D => \value_1[7]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[15]\); - - \r.timers_1.value_RNO[1]\ : MX2A - port map(A => N_343, B => pwdata_0(1), S => - value_1_sqmuxa_0, Y => \value_1[1]\); - - un12_res_I_217 : XNOR2 - port map(A => N_9_0, B => \value_RNIT5VG[30]\, Y => I_217); - - \r.timers_2.reload_RNO[26]\ : NOR2B - port map(A => rstn, B => N_579, Y => \reload_RNO[26]\); - - \r.timers_1.value_RNO[6]\ : MX2A - port map(A => N_348, B => pwdata_0(6), S => - value_1_sqmuxa_0, Y => \value_1[6]\); - - \r.dishlt_RNO\ : NOR2B - port map(A => rstn, B => N_631, Y => dishlt_RNO); - - \r.timers_2.value_RNO[10]\ : MX2A - port map(A => N_419, B => pwdata_0(10), S => - value_1_sqmuxa_0_0, Y => \value_1_0[10]\); - - un12_res_I_16 : OR3 - port map(A => \value_RNI3R3J[0]\, B => \value_RNI534J[1]\, - C => \value_RNI7B4J[2]\, Y => \DWACT_FDEC_E[0]\); - - \v.timers_2.value_0_sqmuxa\ : OR2A - port map(A => readdata51, B => N_232, Y => value_0_sqmuxa); - - \r.timers_2.reload_RNO_0[5]\ : MX2 - port map(A => \reload[5]\, B => pwdata_0(5), S => - reload_1_sqmuxa_0_0, Y => N_558); - - un6_scaler_I_41 : OR2 - port map(A => \scaler[6]\, B => \scaler[7]\, Y => - \DWACT_FDEC_E[3]\); - - \r.timers_2.reload_RNITDRG[3]\ : OR2A - port map(A => \reload[3]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[3]\); - - \r.timers_2.value_RNO[6]\ : MX2A - port map(A => N_415, B => pwdata_0(6), S => - value_1_sqmuxa_0_0, Y => \value_1_0[6]\); - - \r.timers_1.value[18]\ : DFN1E0 - port map(D => \value_1[18]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[26]\); - - \r.timers_1.enable_RNIE45G\ : NOR2A - port map(A => enable, B => N_198, Y => N_200); - - \r.timers_1.value_RNI1MUG[18]\ : MX2 - port map(A => \value[18]\, B => \un1_timer0[26]\, S => - \tsel[0]\, Y => \value_RNI1MUG[18]\); - - \r.timers_2.reload_RNO[9]\ : OR2A - port map(A => rstn, B => N_562, Y => \reload_RNO[9]\); - - \r.reload[7]\ : DFN1 - port map(D => \reload_RNO_0[7]\, CLK => lclk_c, Q => - \reload_0[7]\); - - \v.timers_2.value_0_sqmuxa_0\ : OR2A - port map(A => readdata51, B => N_232, Y => - \value_0_sqmuxa_0\); - - un12_res_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \value_RNI9J4J[3]\, C - => \value_RNIBR4J[4]\, Y => N_146); - - \r.timers_1.value[31]\ : DFN1E0 - port map(D => \value_1_0[31]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[39]\); - - \r.timers_2.reload_RNICJAI[20]\ : OR2A - port map(A => \reload[20]\, B => \readdata_1_sqmuxa_1\, Y - => reload_m_20); - - \r.timers_2.reload[3]\ : DFN1 - port map(D => \reload_RNO[3]\, CLK => lclk_c, Q => - \reload[3]\); - - \comb.readdata55\ : NOR2 - port map(A => \readdata55_3\, B => paddr(6), Y => - \readdata55\); - - \r.timers_2.value_RNO[11]\ : MX2A - port map(A => N_420, B => pwdata_0(11), S => - value_1_sqmuxa_0_0, Y => \value_1_0[11]\); - - \r.scaler_RNISHHF[6]\ : OR2B - port map(A => \scaler[6]\, B => \readdata55\, Y => - scaler_m_6); - - un12_res_I_136 : XNOR2 - port map(A => N_66, B => \value_RNIPTUG[21]\, Y => I_136_1); - - \r.timers_2.reload_RNIF3BI[14]\ : OR2A - port map(A => \reload[14]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[14]\); - - \r.timers_1.value_RNIG6KC[29]\ : MX2 - port map(A => \un1_timer0[37]\, B => \reload_0[29]\, S => - paddr_1(2), Y => N_237); - - \r.timers_2.reload_RNISDRG[2]\ : OR2A - port map(A => \reload[2]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[2]\); - - readdata_1_sqmuxa_1 : OR2A - port map(A => readdata51, B => N_6455, Y => - \readdata_1_sqmuxa_1\); - - \r.timers_1.value_RNO_0[17]\ : MX2C - port map(A => I_105_1, B => \reload_0[17]\, S => - value_1_sn_N_9_i, Y => N_359); - - readdata_2_sqmuxa : OR2A - port map(A => readdata51, B => \rdata60_1\, Y => - \readdata_2_sqmuxa\); - - un6_scaler_I_27 : OR2 - port map(A => \scaler[3]\, B => \scaler[4]\, Y => - \DWACT_FDEC_E[1]\); - - \r.timers_2.value_RNI845P1[29]\ : OR3C - port map(A => \reload_m[29]\, B => \readdata_9[29]\, C => - \value_m[29]\, Y => prdata_15); - - \r.timers_1.value_RNO_0[29]\ : MX2C - port map(A => I_210_1, B => \reload_0[29]\, S => - value_1_sn_N_9_i, Y => N_371); - - \r.scaler[3]\ : DFN1 - port map(D => \scaler_RNO[3]\, CLK => lclk_c, Q => - \scaler[3]\); - - \r.timers_2.value_RNO_0[8]\ : MX2C - port map(A => I_45_2, B => \reload[8]\, S => - value_1_sn_N_9_i_0, Y => N_417); - - \r.timers_2.reload_RNO[13]\ : OR2A - port map(A => rstn, B => N_566, Y => \reload_RNO[13]\); - - un12_res_I_196 : XNOR2 - port map(A => N_24, B => \value_RNI5UUG[27]\, Y => I_196_1); - - un12_res_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_61); - - \r.timers_1.value_RNI9U861[19]\ : AOI1B - port map(A => \N_240_0\, B => N_227, C => \reload_m[19]\, Y - => \readdata_1_iv_0[19]\); - - \r.timers_1.value_RNI73QI[10]\ : MX2 - port map(A => \value[10]\, B => \un1_timer0[18]\, S => - \tsel_0[0]\, Y => \value_RNI73QI[10]\); - - \r.timers_1.reload_RNI06JC[21]\ : MX2 - port map(A => \un1_timer0[29]\, B => \reload_0[21]\, S => - paddr_1(2), Y => N_229); - - \r.timers_2.value_RNO[16]\ : MX2A - port map(A => N_425, B => pwdata_10, S => value_1_sqmuxa_1, - Y => \value_1_0[16]\); - - \r.timers_2.value_RNO_0[27]\ : MX2C - port map(A => I_196_1, B => \reload[27]\, S => - value_1_sn_N_9_i_1, Y => N_436); - - \comb.1.readdata_9_sn_m3\ : NOR2A - port map(A => readdata30, B => paddr(3), Y => \N_240\); - - \r.timers_2.reload_RNO_0[7]\ : MX2 - port map(A => \reload[7]\, B => pwdata_0(7), S => - reload_1_sqmuxa_0_0, Y => N_560); - - \v.timers_1.load_1_sqmuxa_1\ : NOR2 - port map(A => load_1_sqmuxa, B => un1_apbi, Y => - load_1_sqmuxa_1); - - un12_res_I_202 : OR3 - port map(A => \DWACT_FDEC_E[24]\, B => \DWACT_FDEC_E[23]\, - C => \value_RNI5UUG[27]\, Y => N_19_0); - - \r.timers_1.reload[12]\ : DFN1E1 - port map(D => pwdata_0(12), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[12]\); - - \r.timers_2.reload_RNO_0[29]\ : MX2 - port map(A => \reload[29]\, B => pwdata_23, S => - reload_1_sqmuxa_1, Y => N_582); - - \r.timers_1.value[25]\ : DFN1E0 - port map(D => \value_1[25]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[33]\); - - \r.timers_2.value[19]\ : DFN1E0 - port map(D => \value_1_0[19]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[19]\); - - un6_scaler_I_34 : OR3 - port map(A => \scaler[3]\, B => \scaler[4]\, C => - \scaler[5]\, Y => \DWACT_FDEC_E[2]\); - - \r.timers_1.enable_RNO_1\ : MX2 - port map(A => restart_0, B => pwdata_0(0), S => - load_1_sqmuxa_1, Y => enable_1); - - un12_res_I_101 : OR2 - port map(A => \value_RNIH3QI[15]\, B => \value_RNIJ3QI[16]\, - Y => \DWACT_FDEC_E[11]\); - - \r.timers_2.reload_RNO[8]\ : OR2A - port map(A => rstn, B => N_561, Y => \reload_RNO[8]\); - - \r.timers_2.irq\ : DFN1 - port map(D => irq_RNO, CLK => lclk_c, Q => \un1_timer0[5]\); - - \r.timers_1.value_RNO[13]\ : MX2A - port map(A => N_355, B => pwdata_0(13), S => - value_1_sqmuxa_0, Y => \value_1[13]\); - - \r.timers_1.reload_RNI838C[8]\ : MX2 - port map(A => \un1_timer0[16]\, B => \reload_0[8]\, S => - paddr_1(2), Y => N_216); - - \r.timers_2.reload_RNO_0[15]\ : MX2 - port map(A => \reload[15]\, B => pwdata_0(15), S => - reload_1_sqmuxa_0_0, Y => N_568); - - \r.timers_2.reload_RNO[10]\ : OR2A - port map(A => rstn, B => N_563, Y => \reload_RNO[10]\); - - \r.scaler[5]\ : DFN1 - port map(D => \scaler_RNO[5]\, CLK => lclk_c, Q => - \scaler[5]\); - - \r.timers_2.value_RNO_0[15]\ : MX2C - port map(A => I_91_1, B => \reload[15]\, S => - value_1_sn_N_9_i_1, Y => N_424); - - \r.timers_2.value_RNIFQHH[5]\ : OR2A - port map(A => \value[5]\, B => value_0_sqmuxa, Y => - value_m_1); - - \r.timers_2.value_RNO[29]\ : MX2A - port map(A => N_438, B => pwdata_23, S => value_1_sqmuxa_1, - Y => \value_1[29]\); - - \r.scaler_RNITLHF[7]\ : OR2B - port map(A => \scaler[7]\, B => \readdata55\, Y => - scaler_m_7); - - \r.timers_2.value[7]\ : DFN1E0 - port map(D => \value_1_0[7]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[7]\); - - un12_res_I_56 : XNOR2 - port map(A => N_123, B => \value_RNI73QI[10]\, Y => I_56_2); - - \r.timers_2.value[10]\ : DFN1E0 - port map(D => \value_1_0[10]\, CLK => lclk_c, E => - value_2_sqmuxa_0_0, Q => \value[10]\); - - \r.timers_1.value_RNO[4]\ : MX2A - port map(A => N_346, B => pwdata_0(4), S => - value_1_sqmuxa_0, Y => \value_1[4]\); - - \r.timers_1.value_RNI3R3J[0]\ : MX2 - port map(A => \value[0]\, B => \un1_timer0[8]\, S => - \tsel_0[0]\, Y => \value_RNI3R3J[0]\); - - \r.reload_RNI5ONI[0]\ : OR2A - port map(A => \reload_0[0]\, B => \readdata56\, Y => - reload_m_0_d0); - - \r.timers_2.reload[8]\ : DFN1 - port map(D => \reload_RNO[8]\, CLK => lclk_c, Q => - \reload[8]\); - - \r.timers_1.value_RNI9UUG[29]\ : MX2 - port map(A => \value[29]\, B => \un1_timer0[37]\, S => - \tsel[0]\, Y => \value_RNI9UUG[29]\); - - \r.timers_1.value_RNO[23]\ : MX2A - port map(A => N_365, B => pwdata_17, S => value_1_sqmuxa, Y - => \value_1[23]\); - - \r.timers_2.reload_RNO[25]\ : NOR2B - port map(A => rstn, B => N_578, Y => \reload_RNO[25]\); - - un12_res_I_189 : OR3 - port map(A => \value_RNIVTUG[24]\, B => \value_RNI1UUG[25]\, - C => \value_RNI3UUG[26]\, Y => \DWACT_FDEC_E[22]\); - - \r.timers_2.reload[29]\ : DFN1 - port map(D => \reload_RNO[29]\, CLK => lclk_c, Q => - \reload[29]\); - - \r.timers_1.enable_RNO_0\ : MX2 - port map(A => enable_1, B => enable, S => enable_1_sqmuxa, - Y => N_544); - - \r.timers_2.reload_RNIEVAI[13]\ : OR2A - port map(A => \reload[13]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[13]\); - - un12_res_I_87 : OR3 - port map(A => \value_RNIB3QI[12]\, B => \value_RNID3QI[13]\, - C => \value_RNIF3QI[14]\, Y => \DWACT_FDEC_E[9]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.timers_1.value[24]\ : DFN1E0 - port map(D => \value_1[24]\, CLK => lclk_c, E => - value_2_sqmuxa_1, Q => \un1_timer0[32]\); - - \r.timers_1.reload[2]\ : DFN1E1 - port map(D => pwdata_0(2), CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[2]\); - - \comb.2.readdata51\ : NOR2 - port map(A => \readdata51_1\, B => paddr(4), Y => - readdata51); - - \r.timers_1.value_RNID3QI[13]\ : MX2 - port map(A => \value[13]\, B => \un1_timer0[21]\, S => - \tsel_0[0]\, Y => \value_RNID3QI[13]\); - - \r.timers_1.reload_RNI0J7C[4]\ : MX2 - port map(A => \un1_timer0[12]\, B => \reload_1[4]\, S => - paddr_1(2), Y => N_212); - - \r.timers_2.value_RNII6IH[8]\ : OR2A - port map(A => \value[8]\, B => value_0_sqmuxa, Y => - value_m_4); - - \r.timers_2.chain_RNIQIHE\ : OR2A - port map(A => chain_0, B => \readdata_2_sqmuxa\, Y => - chain_m); - - \r.timers_1.value_RNIJR5J[8]\ : MX2 - port map(A => \value[8]\, B => \un1_timer0[16]\, S => - \tsel_0[0]\, Y => \value_RNIJR5J[8]\); - - \r.reload[6]\ : DFN1 - port map(D => \reload_RNO_0[6]\, CLK => lclk_c, Q => - \reload_0[6]\); - - \r.timers_1.load_RNIC53BJ\ : NOR2B - port map(A => irq_0_sqmuxa, B => irq_2, Y => load_RNIC53BJ); - - \r.timers_2.reload_RNIJFBI[27]\ : OR2A - port map(A => \reload[27]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => reload_m_27); - - \r.timers_1.value_RNIE2KC[28]\ : MX2 - port map(A => \un1_timer0[36]\, B => \reload_0[28]\, S => - paddr_1(2), Y => N_236); - - \r.timers_2.reload_RNO_0[8]\ : MX2 - port map(A => \reload[8]\, B => pwdata_0(8), S => - reload_1_sqmuxa_0_0, Y => N_561); - - un12_res_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \v.timers_1.value_1_sqmuxa\ : NOR3A - port map(A => readdata30, B => N_232_0, C => un1_apbi, Y - => value_1_sqmuxa); - - un6_scaler_I_30 : OR3 - port map(A => \DWACT_FDEC_E_0[0]\, B => \DWACT_FDEC_E[1]\, - C => \scaler[5]\, Y => N_14); - - \r.timers_2.reload_RNO[18]\ : NOR2B - port map(A => rstn, B => N_571, Y => \reload_RNO[18]\); - - \r.timers_1.load\ : DFN1 - port map(D => load_RNO, CLK => lclk_c, Q => load); - - \r.timers_1.value_RNI4JCL[18]\ : OR2B - port map(A => \N_240\, B => N_226, Y => \readdata_9[18]\); - - \r.timers_2.value_RNO_0[12]\ : MX2C - port map(A => I_73_1, B => \reload[12]\, S => - value_1_sn_N_9_i_1, Y => N_421); - - \r.timers_2.reload_RNO_0[26]\ : MX2 - port map(A => \reload[26]\, B => pwdata_20, S => - reload_1_sqmuxa_1, Y => N_579); - - \r.scaler_RNIP5HF[3]\ : OR2B - port map(A => \scaler[3]\, B => \readdata55\, Y => - \scaler_m[3]\); - - \r.timers_2.value_RNI3HCH[23]\ : OR2A - port map(A => \value[23]\, B => value_0_sqmuxa, Y => - \value_m[23]\); - - \r.timers_2.value[8]\ : DFN1E0 - port map(D => \value_1_0[8]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[8]\); - - \r.timers_2.value[30]\ : DFN1E0 - port map(D => \value_1_0[30]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[30]\); - - \r.timers_2.value_RNO_0[10]\ : MX2C - port map(A => I_56_2, B => \reload[10]\, S => - value_1_sn_N_9_i_0, Y => N_419); - - un12_res_I_12 : OR3 - port map(A => \value_RNI3R3J[0]\, B => \value_RNI534J[1]\, - C => \value_RNI7B4J[2]\, Y => N_154); - - \r.reload[0]\ : DFN1 - port map(D => \reload_RNO_0[0]\, CLK => lclk_c, Q => - \reload_0[0]\); - - \comb.1.readdata26\ : OR2A - port map(A => paddr(3), B => paddr(2), Y => \rdata60_1\); - - \r.reload_RNO_0[1]\ : MX2 - port map(A => \reload_0[1]\, B => pwdata_0(1), S => - reload_1_sqmuxa_2, Y => N_624); - - un12_res_I_156 : XNOR2 - port map(A => N_52, B => \value_RNITTUG[23]\, Y => I_156_1); - - \r.reload_RNO_0[7]\ : MX2 - port map(A => \reload_0[7]\, B => pwdata_0(7), S => - reload_1_sqmuxa_2, Y => N_630); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.timers_2.value_RNI3LCH[30]\ : OR2A - port map(A => \value[30]\, B => \value_0_sqmuxa_0\, Y => - \value_m[30]\); - - \r.timers_2.reload_RNO[19]\ : NOR2B - port map(A => rstn, B => N_572, Y => \reload_RNO[19]\); - - \r.timers_2.reload_RNIG7BI[15]\ : OR2A - port map(A => \reload[15]\, B => \readdata_1_sqmuxa_1\, Y - => \reload_m[15]\); - - \comb.1.readdata30\ : NOR3A - port map(A => paddr(4), B => paddr(6), C => paddr(5), Y => - readdata30); - - \r.timers_1.reload[3]\ : DFN1E1 - port map(D => pwdata_1_2, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_1[3]\); - - \r.scaler_RNO_0[6]\ : MX2C - port map(A => pwdata_0(6), B => N_330, S => scaler_0_sqmuxa, - Y => \scaler_1[6]\); - - \r.scaler_RNO[3]\ : OR2B - port map(A => rstn, B => \scaler_1[3]\, Y => - \scaler_RNO[3]\); - - \r.timers_2.value_RNIUCCH[11]\ : OR2A - port map(A => \value[11]\, B => value_0_sqmuxa, Y => - value_m_7); - - \r.timers_2.reload_RNO[24]\ : NOR2B - port map(A => rstn, B => N_577, Y => \reload_RNO[24]\); - - \v.timers_2.load_1_sqmuxa\ : NOR2 - port map(A => \readdata_2_sqmuxa\, B => un1_apbi, Y => - load_1_sqmuxa_0); - - \r.timers_1.value_RNO[8]\ : MX2A - port map(A => N_350, B => pwdata_0(8), S => - value_1_sqmuxa_0, Y => \value_1[8]\); - - \r.timers_2.value_RNIO34P1[25]\ : OR3C - port map(A => \reload_m[25]\, B => \readdata_9[25]\, C => - \value_m[25]\, Y => prdata_11); - - un12_res_I_45 : XNOR2 - port map(A => N_131, B => \value_RNIJR5J[8]\, Y => I_45_2); - - \r.timers_2.reload_RNIIBBI[26]\ : OR2A - port map(A => \reload[26]\, B => - readdata_1_sqmuxa_1_0_net_1, Y => \reload_m[26]\); - - \r.timers_1.value_RNIARCL[29]\ : OR2B - port map(A => \N_240\, B => N_237, Y => \readdata_9[29]\); - - \r.timers_2.reload_RNO_0[14]\ : MX2 - port map(A => \reload[14]\, B => pwdata_0(14), S => - reload_1_sqmuxa_1, Y => N_567); - - \r.scaler_RNO[6]\ : OR2B - port map(A => rstn, B => \scaler_1[6]\, Y => - \scaler_RNO[6]\); - - \r.timers_2.value[27]\ : DFN1E0 - port map(D => \value_1_0[27]\, CLK => lclk_c, E => - value_2_sqmuxa, Q => \value[27]\); - - \r.timers_1.reload_RNIEI2E[20]\ : MX2 - port map(A => \un1_timer0[28]\, B => \reload_0[20]\, S => - paddr(2), Y => N_228); - - \r.timers_2.reload[5]\ : DFN1 - port map(D => \reload_RNO[5]\, CLK => lclk_c, Q => - \reload[5]\); - - \r.timers_2.value_RNO[2]\ : MX2A - port map(A => N_411, B => pwdata_0(2), S => - value_1_sqmuxa_0_0, Y => \value_1_0[2]\); - - un12_res_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \r.timers_1.value_RNO_0[8]\ : MX2C - port map(A => I_45_2, B => \reload_0[8]\, S => - value_1_sn_N_9_i_0_0, Y => N_350); - - \r.reload[4]\ : DFN1 - port map(D => \reload_RNO_0[4]\, CLK => lclk_c, Q => - \reload[4]\); - - \r.timers_1.value[23]\ : DFN1E0 - port map(D => \value_1[23]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[31]\); - - \r.timers_1.reload[15]\ : DFN1E1 - port map(D => pwdata_0(15), CLK => lclk_c, E => - reload_1_sqmuxa_0, Q => \reload_0[15]\); - - \r.tsel_0_0[0]\ : DFN1 - port map(D => \tsel_RNIG6TH[0]\, CLK => lclk_c, Q => - \tsel_0[0]\); - - \r.timers_1.reload[30]\ : DFN1E1 - port map(D => pwdata_24, CLK => lclk_c, E => - reload_1_sqmuxa, Q => \reload_0[30]\); - - \r.timers_2.restart_RNO_0\ : MX2 - port map(A => restart, B => pwdata_1_0, S => - load_1_sqmuxa_0, Y => N_618); - - \r.timers_2.reload_RNO[0]\ : OR2A - port map(A => rstn, B => N_553, Y => \reload_RNO[0]\); - - \r.timers_1.value_RNO[15]\ : MX2A - port map(A => N_357, B => pwdata_0(15), S => value_1_sqmuxa, - Y => \value_1_0[15]\); - - \v.timers_1.reload_1_sqmuxa\ : NOR3A - port map(A => readdata30, B => N_6455_0, C => un1_apbi, Y - => reload_1_sqmuxa); - - \r.timers_1.value_RNIJ3QI[16]\ : MX2 - port map(A => \value[16]\, B => \un1_timer0[24]\, S => - \tsel_0[0]\, Y => \value_RNIJ3QI[16]\); - - un12_res_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E_0[2]\, - C => \value_RNIFB5J[6]\, Y => N_136); - - \r.scaler_RNO_0[4]\ : MX2C - port map(A => pwdata_0(4), B => N_328, S => scaler_0_sqmuxa, - Y => \scaler_1[4]\); - - \r.timers_2.value_RNO_0[7]\ : MX2C - port map(A => I_38_2, B => \reload[7]\, S => - value_1_sn_N_9_i_0, Y => N_416); - - un6_scaler_I_38 : XNOR2 - port map(A => N_9, B => \scaler[7]\, Y => I_38_3); - - \r.timers_2.reload_RNO_0[30]\ : MX2 - port map(A => \reload[30]\, B => pwdata_24, S => - reload_1_sqmuxa_1, Y => N_583); - - \r.dishlt\ : DFN1 - port map(D => dishlt_RNO, CLK => lclk_c, Q => \dishlt\); - - un12_res_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \value_RNIH3QI[15]\, Y => N_93); - - \r.timers_2.reload[30]\ : DFN1 - port map(D => \reload_RNO[30]\, CLK => lclk_c, Q => - \reload[30]\); - - \r.timers_2.irqen_RNI5M5G1\ : OA1A - port map(A => irqen, B => \readdata_2_sqmuxa\, C => - \readdata_9[3]\, Y => \readdata_iv_0[3]\); - - un12_res_I_149 : OR3 - port map(A => \value_RNI3R3J[0]\, B => \value_RNI534J[1]\, - C => \value_RNI7B4J[2]\, Y => \DWACT_FDEC_E[34]\); - - un12_res_I_115 : XNOR2 - port map(A => N_81, B => \value_RNI1MUG[18]\, Y => I_115_1); - - \r.timers_1.value[17]\ : DFN1E0 - port map(D => \value_1[17]\, CLK => lclk_c, E => - value_2_sqmuxa_0, Q => \un1_timer0[25]\); - - \r.scaler_RNINTGF[1]\ : OR2A - port map(A => \readdata55\, B => \scaler[1]\, Y => - scaler_i_m(1)); - - \r.timers_2.value_RNO[13]\ : MX2A - port map(A => N_422, B => pwdata_0(13), S => - value_1_sqmuxa_0_0, Y => \value_1_0[13]\); - - \r.timers_2.reload_RNO_0[2]\ : MX2 - port map(A => \reload[2]\, B => pwdata_0(2), S => - reload_1_sqmuxa_0_0, Y => N_555); - - \r.timers_1.value_RNO[25]\ : MX2A - port map(A => N_367, B => pwdata_19, S => value_1_sqmuxa_0, - Y => \value_1[25]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ssram_plugin is - - port( state_RNIFS55 : out std_logic_vector(4 to 4); - ramsn_c : in std_logic_vector(0 to 0); - rwen_c : in std_logic_vector(3 downto 0); - address_c : in std_logic_vector(27 downto 20); - address : in std_logic_vector(31 downto 28); - state_i : out std_logic_vector(3 to 3); - ssram_plugin_GND : in std_logic; - clk_c : in std_logic; - writen_c : in std_logic; - nBWE_c : out std_logic; - nBWd_c : out std_logic; - nBWc_c : out std_logic; - nBWb_c : out std_logic; - nBWa_c : out std_logic; - nCE1_c : out std_logic; - nCE3_c : out std_logic; - CE2_c : out std_logic - ); - -end ssram_plugin; - -architecture DEF_ARCH of ssram_plugin is - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1P1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state[3]_net_1\, nCE1int_2, \nCE3int_0\, \CE2int_0\, - \state_ns[1]\, \state[2]_net_1\, \state[1]_net_1\, - \state[4]_net_1\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - nBWbint : OR2 - port map(A => rwen_c(2), B => ramsn_c(0), Y => nBWb_c); - - \state_RNIE94H[3]\ : NOR3B - port map(A => \state[3]_net_1\, B => address(30), C => - address(28), Y => nCE1int_2); - - nCE3int_0 : OR2 - port map(A => address_c(20), B => address_c(21), Y => - \nCE3int_0\); - - \state[1]\ : DFN1C1 - port map(D => \state[2]_net_1\, CLK => clk_c, CLR => - ramsn_c(0), Q => \state[1]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \state[4]\ : DFN1P1 - port map(D => ssram_plugin_GND, CLK => clk_c, PRE => - ramsn_c(0), Q => \state[4]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \state_RNINMLV[3]\ : OR3A - port map(A => nCE1int_2, B => address(31), C => address(29), - Y => nCE1_c); - - nCE3int : OR3 - port map(A => address_c(23), B => address_c(22), C => - \nCE3int_0\, Y => nCE3_c); - - nBWdint : OR2 - port map(A => rwen_c(0), B => ramsn_c(0), Y => nBWd_c); - - CE2int : NOR3 - port map(A => address_c(27), B => address_c(26), C => - \CE2int_0\, Y => CE2_c); - - \state[2]\ : DFN1C1 - port map(D => \state[3]_net_1\, CLK => clk_c, CLR => - ramsn_c(0), Q => \state[2]_net_1\); - - nBWaint : OR2 - port map(A => rwen_c(3), B => ramsn_c(0), Y => nBWa_c); - - CE2int_0 : OR2 - port map(A => address_c(24), B => address_c(25), Y => - \CE2int_0\); - - \state_RNIFS55[4]\ : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => state_RNIFS55(4)); - - GND_i : GND - port map(Y => \GND\); - - nBWEint : OR2 - port map(A => writen_c, B => ramsn_c(0), Y => nBWE_c); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO[3]\ : NOR3 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, C - => \state[3]_net_1\, Y => \state_ns[1]\); - - nBWcint : OR2 - port map(A => rwen_c(1), B => ramsn_c(0), Y => nBWc_c); - - \state_RNI7SI2[3]\ : INV - port map(A => \state[3]_net_1\, Y => state_i(3)); - - \state[3]\ : DFN1C1 - port map(D => \state_ns[1]\, CLK => clk_c, CLR => - ramsn_c(0), Q => \state[3]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_work_leon3mp_wfp_rtl_1 is - - port( clk : in std_logic; - address : in std_logic_vector(9 downto 0); - datain : in std_logic_vector(31 downto 0); - dataout : out std_logic_vector(31 downto 0); - enable : in std_logic; - write : in std_logic - ); - -end proasic3_syncram_work_leon3mp_wfp_rtl_1; - -architecture DEF_ARCH of proasic3_syncram_work_leon3mp_wfp_rtl_1 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ1_1 is - - port( dstate_RNI1G47MJ : in std_logic_vector(1 to 1); - dataout_0 : out std_logic_vector(31 downto 28); - dataout : out std_logic_vector(27 downto 0); - xaddress_RNIJI2O22 : in std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : in std_logic_vector(1 to 1); - xaddress_RNIK99NK1 : in std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : in std_logic_vector(0 to 0); - xaddress_RNILK99L1 : in std_logic_vector(1 to 1); - xaddress_RNILHOK61 : in std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : in std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : in std_logic_vector(1 to 1); - dstate_RNIFS6E51 : in std_logic_vector(1 to 1); - dstate_RNIFPT581 : in std_logic_vector(1 to 1); - dstate_RNIC3QA81 : in std_logic_vector(1 to 1); - faddr_RNI7MK691 : in std_logic_vector(6 to 6); - xaddress_RNID252J1 : in std_logic_vector(10 to 10); - faddr_RNIB0UOO : in std_logic_vector(2 to 2); - faddr_RNIEHR0O : in std_logic_vector(1 to 1); - faddr_RNI7879K : in std_logic_vector(0 to 0); - xaddress_RNITFTTE : in std_logic_vector(3 to 3); - xaddress_RNIFP43F : in std_logic_vector(2 to 2); - syncramZ1_1_VCC : in std_logic; - read_RNIEEGDD1 : in std_logic; - read_RNI75LJ31 : in std_logic; - read_RNIC9O9B1 : in std_logic; - read_RNIC70OF1 : in std_logic; - read_RNICKHE91 : in std_logic; - read_RNISLPNU : in std_logic; - read_RNIQMJI41 : in std_logic; - read_RNICAQK41 : in std_logic; - read_RNIQH64D1 : in std_logic; - read_RNIL633F1 : in std_logic; - read_RNIMJHQT : in std_logic; - read_RNIEKS231 : in std_logic; - read_RNI7G7G41 : in std_logic; - read_RNI76N8R : in std_logic; - read_RNIAQJ831 : in std_logic; - read_RNI8DFM31 : in std_logic; - read_RNIQPCQ11 : in std_logic; - read_RNIFPFT31 : in std_logic; - read_RNIQFOD21 : in std_logic; - read_RNIRO4K31 : in std_logic; - read_RNI0IQ7R : in std_logic; - N_26 : in std_logic; - N_24 : in std_logic; - N_10 : in std_logic; - lclk_c : in std_logic - ); - -end syncramZ1_1; - -architecture DEF_ARCH of syncramZ1_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_1 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(9 downto 0) := (others => 'U'); - datain : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout : out std_logic_vector(31 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_1 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_1(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_1 - port map(clk => lclk_c, address(9) => faddr_RNI7MK691(6), - address(8) => xaddress_RNID252J1(10), address(7) => N_26, - address(6) => N_24, address(5) => faddr_RNIB0UOO(2), - address(4) => faddr_RNIEHR0O(1), address(3) => - faddr_RNI7879K(0), address(2) => N_10, address(1) => - xaddress_RNITFTTE(3), address(0) => xaddress_RNIFP43F(2), - datain(31) => xaddress_RNIJI2O22(1), datain(30) => - xaddress_RNIP2BVK1(1), datain(29) => - xaddress_RNIK99NK1(1), datain(28) => - xaddress_RNI1I3MQ1(0), datain(27) => - xaddress_RNILK99L1(1), datain(26) => - xaddress_RNILHOK61(1), datain(25) => - xaddress_RNIEHIUT1(1), datain(24) => - xaddress_RNI1Q9ST1(1), datain(23) => read_RNIEEGDD1, - datain(22) => read_RNI75LJ31, datain(21) => - read_RNIC9O9B1, datain(20) => read_RNIC70OF1, datain(19) - => read_RNICKHE91, datain(18) => read_RNISLPNU, - datain(17) => read_RNIQMJI41, datain(16) => - read_RNICAQK41, datain(15) => read_RNIQH64D1, datain(14) - => read_RNIL633F1, datain(13) => read_RNIMJHQT, - datain(12) => read_RNIEKS231, datain(11) => - read_RNI7G7G41, datain(10) => read_RNI76N8R, datain(9) - => read_RNIAQJ831, datain(8) => read_RNI8DFM31, - datain(7) => read_RNIQPCQ11, datain(6) => - dstate_RNIFS6E51(1), datain(5) => read_RNIFPFT31, - datain(4) => read_RNIQFOD21, datain(3) => read_RNIRO4K31, - datain(2) => read_RNI0IQ7R, datain(1) => - dstate_RNIFPT581(1), datain(0) => dstate_RNIC3QA81(1), - dataout(31) => dataout_0(31), dataout(30) => - dataout_0(30), dataout(29) => dataout_0(29), dataout(28) - => dataout_0(28), dataout(27) => dataout(27), - dataout(26) => dataout(26), dataout(25) => dataout(25), - dataout(24) => dataout(24), dataout(23) => dataout(23), - dataout(22) => dataout(22), dataout(21) => dataout(21), - dataout(20) => dataout(20), dataout(19) => dataout(19), - dataout(18) => dataout(18), dataout(17) => dataout(17), - dataout(16) => dataout(16), dataout(15) => dataout(15), - dataout(14) => dataout(14), dataout(13) => dataout(13), - dataout(12) => dataout(12), dataout(11) => dataout(11), - dataout(10) => dataout(10), dataout(9) => dataout(9), - dataout(8) => dataout(8), dataout(7) => dataout(7), - dataout(6) => dataout(6), dataout(5) => dataout(5), - dataout(4) => dataout(4), dataout(3) => dataout(3), - dataout(2) => dataout(2), dataout(1) => dataout(1), - dataout(0) => dataout(0), enable => syncramZ1_1_VCC, - write => dstate_RNI1G47MJ(1)); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_work_leon3mp_wfp_rtl_2 is - - port( clk : in std_logic; - address : in std_logic_vector(6 downto 0); - datain : in std_logic_vector(35 downto 0); - dataout : out std_logic_vector(35 downto 0); - enable : in std_logic; - write : in std_logic - ); - -end proasic3_syncram_work_leon3mp_wfp_rtl_2; - -architecture DEF_ARCH of proasic3_syncram_work_leon3mp_wfp_rtl_2 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ2_1 is - - port( dataout : out std_logic_vector(35 downto 28); - dataout_0 : out std_logic_vector(27 downto 0); - ctx : in std_logic_vector(7 downto 0); - vdtdatain_0_1_5 : in std_logic; - xaddress_RNI9MB27S2 : in std_logic_vector(23 to 23); - xaddress_RNIC5A27S2 : in std_logic_vector(21 to 21); - xaddress_RNI1D927S2 : in std_logic_vector(20 to 20); - xaddress_RNI0GI17S2 : in std_logic_vector(17 to 17); - xaddress_RNIID927S2 : in std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : in std_logic_vector(15 to 15); - xaddress_RNIN7J17S2 : in std_logic_vector(14 to 14); - xaddress_RNICFI17S2 : in std_logic_vector(13 to 13); - xaddress_RNITMH17S2 : in std_logic_vector(12 to 12); - dstate_i_RNI29QQ7J3 : in std_logic_vector(8 to 8); - dstate_i_0_RNIH0PPES : in std_logic_vector(8 to 8); - dstate_i_0_RNIL7FGFS : in std_logic_vector(8 to 8); - faddr_RNI7MK691 : in std_logic_vector(6 to 6); - xaddress_RNID252J1 : in std_logic_vector(10 to 10); - faddr_RNIB0UOO : in std_logic_vector(2 to 2); - faddr_RNIEHR0O : in std_logic_vector(1 to 1); - faddr_RNI7879K : in std_logic_vector(0 to 0); - newtag_1_0 : in std_logic_vector(27 downto 24); - dci_m_3 : in std_logic; - dci_m_2 : in std_logic; - dci_m_1 : in std_logic; - dci_m_0 : in std_logic; - dci_m_6 : in std_logic; - maddress : in std_logic_vector(28 to 28); - addr : in std_logic_vector(30 to 30); - un1_p0_2_0 : in std_logic_vector(498 to 498); - edata2_iv_i_0 : in std_logic_vector(31 to 31); - flush_RNIGBB873 : in std_logic; - syncramZ2_1_VCC : in std_logic; - flush_0_1_RNIPTA27S2 : in std_logic; - flush_0_1_RNIOMB27S2 : in std_logic; - flush_0_1_RNIBUA27S2 : in std_logic; - N_3239_i_0 : in std_logic; - N_16_i_0 : in std_logic; - flush_RNIGUM2OH3 : in std_logic; - flush_RNIJEN4SI3 : in std_logic; - N_12_i_0 : in std_logic; - N_26 : in std_logic; - N_24 : in std_logic; - lclk_c : in std_logic; - N_269 : in std_logic; - N_270 : in std_logic; - N_3846 : in std_logic; - N_144 : in std_logic; - N_329 : in std_logic; - N_267 : in std_logic; - N_330 : in std_logic; - N_3254_0 : in std_logic - ); - -end syncramZ2_1; - -architecture DEF_ARCH of syncramZ2_1 is - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_2 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(6 downto 0) := (others => 'U'); - datain : in std_logic_vector(35 downto 0) := (others => 'U'); - dataout : out std_logic_vector(35 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - signal \vdtdatain_0_1_1[27]\, \vdtdatain_0_1_0[26]\, - \vdtdatain_0_1_0[24]\, \vdtdatain_0_1[24]\, - \vdtdatain_0_1[26]\, \vdtdatain_0_1[27]\, - \vdtdatain_0_1[20]\, \vdtdatain_0_1[21]\, - \vdtdatain_0_1[22]\, \vdtdatain_0_1[23]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_2 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_2(DEF_ARCH); -begin - - - \proa3.x0_RNO_8\ : OA1C - port map(A => edata2_iv_i_0(31), B => N_3254_0, C => - un1_p0_2_0(498), Y => \vdtdatain_0_1_1[27]\); - - \proa3.x0_RNO_5\ : OR3C - port map(A => N_270, B => N_269, C => \vdtdatain_0_1_1[27]\, - Y => \vdtdatain_0_1[27]\); - - \proa3.x0_RNO_4\ : OR3B - port map(A => dci_m_6, B => \vdtdatain_0_1_0[26]\, C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[26]\); - - \proa3.x0_RNO_2\ : OA1B - port map(A => dci_m_3, B => newtag_1_0(27), C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[23]\); - - \proa3.x0_RNO\ : OA1B - port map(A => dci_m_0, B => newtag_1_0(24), C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[20]\); - - \proa3.x0_RNO_1\ : OA1B - port map(A => dci_m_2, B => newtag_1_0(26), C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[22]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO_7\ : AOI1B - port map(A => addr(30), B => N_330, C => N_267, Y => - \vdtdatain_0_1_0[26]\); - - \proa3.x0_RNO_3\ : OR3B - port map(A => N_3846, B => \vdtdatain_0_1_0[24]\, C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[24]\); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \proa3.x0_RNO_6\ : AOI1B - port map(A => maddress(28), B => N_329, C => N_144, Y => - \vdtdatain_0_1_0[24]\); - - \proa3.x0_RNO_0\ : OA1B - port map(A => dci_m_1, B => newtag_1_0(25), C => - un1_p0_2_0(498), Y => \vdtdatain_0_1[21]\); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_2 - port map(clk => lclk_c, address(6) => faddr_RNI7MK691(6), - address(5) => xaddress_RNID252J1(10), address(4) => N_26, - address(3) => N_24, address(2) => faddr_RNIB0UOO(2), - address(1) => faddr_RNIEHR0O(1), address(0) => - faddr_RNI7879K(0), datain(35) => ctx(7), datain(34) => - ctx(6), datain(33) => ctx(5), datain(32) => ctx(4), - datain(31) => ctx(3), datain(30) => ctx(2), datain(29) - => ctx(1), datain(28) => ctx(0), datain(27) => - \vdtdatain_0_1[27]\, datain(26) => \vdtdatain_0_1[26]\, - datain(25) => vdtdatain_0_1_5, datain(24) => - \vdtdatain_0_1[24]\, datain(23) => \vdtdatain_0_1[23]\, - datain(22) => \vdtdatain_0_1[22]\, datain(21) => - \vdtdatain_0_1[21]\, datain(20) => \vdtdatain_0_1[20]\, - datain(19) => xaddress_RNI9MB27S2(23), datain(18) => - flush_0_1_RNIPTA27S2, datain(17) => - xaddress_RNIC5A27S2(21), datain(16) => - xaddress_RNI1D927S2(20), datain(15) => - flush_0_1_RNIOMB27S2, datain(14) => flush_0_1_RNIBUA27S2, - datain(13) => xaddress_RNI0GI17S2(17), datain(12) => - xaddress_RNIID927S2(16), datain(11) => - xaddress_RNI2MB27S2(15), datain(10) => - xaddress_RNIN7J17S2(14), datain(9) => - xaddress_RNICFI17S2(13), datain(8) => - xaddress_RNITMH17S2(12), datain(7) => N_3239_i_0, - datain(6) => dstate_i_RNI29QQ7J3(8), datain(5) => - N_16_i_0, datain(4) => flush_RNIGUM2OH3, datain(3) => - dstate_i_0_RNIH0PPES(8), datain(2) => flush_RNIJEN4SI3, - datain(1) => N_12_i_0, datain(0) => - dstate_i_0_RNIL7FGFS(8), dataout(35) => dataout(35), - dataout(34) => dataout(34), dataout(33) => dataout(33), - dataout(32) => dataout(32), dataout(31) => dataout(31), - dataout(30) => dataout(30), dataout(29) => dataout(29), - dataout(28) => dataout(28), dataout(27) => dataout_0(27), - dataout(26) => dataout_0(26), dataout(25) => - dataout_0(25), dataout(24) => dataout_0(24), dataout(23) - => dataout_0(23), dataout(22) => dataout_0(22), - dataout(21) => dataout_0(21), dataout(20) => - dataout_0(20), dataout(19) => dataout_0(19), dataout(18) - => dataout_0(18), dataout(17) => dataout_0(17), - dataout(16) => dataout_0(16), dataout(15) => - dataout_0(15), dataout(14) => dataout_0(14), dataout(13) - => dataout_0(13), dataout(12) => dataout_0(12), - dataout(11) => dataout_0(11), dataout(10) => - dataout_0(10), dataout(9) => dataout_0(9), dataout(8) => - dataout_0(8), dataout(7) => dataout_0(7), dataout(6) => - dataout_0(6), dataout(5) => dataout_0(5), dataout(4) => - dataout_0(4), dataout(3) => dataout_0(3), dataout(2) => - dataout_0(2), dataout(1) => dataout_0(1), dataout(0) => - dataout_0(0), enable => syncramZ2_1_VCC, write => - flush_RNIGBB873); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ1 is - - port( istate_RNIJCMP6 : in std_logic_vector(0 to 0); - dataout_2 : out std_logic_vector(31 downto 28); - dataout_1 : out std_logic_vector(27 downto 0); - istate_RNIENB3M : in std_logic_vector(0 to 0); - istate_RNIS4VK8 : in std_logic_vector(0 to 0); - istate_RNIRASC8 : in std_logic_vector(0 to 0); - istate_RNIJSOBE : in std_logic_vector(0 to 0); - istate_RNIR2JU8 : in std_logic_vector(0 to 0); - istate_RNIOJJE1 : in std_logic_vector(0 to 0); - istate_RNIAP6PI : in std_logic_vector(0 to 0); - istate_RNIH0NBI : in std_logic_vector(0 to 0); - istate_RNI5V68H : in std_logic_vector(0 to 0); - istate_RNIM2DE7 : in std_logic_vector(0 to 0); - istate_RNIAJH4F : in std_logic_vector(0 to 0); - istate_RNIVTQIJ : in std_logic_vector(0 to 0); - istate_RNI2MM6D : in std_logic_vector(0 to 0); - istate_RNI8BL1A : in std_logic_vector(0 to 0); - istate_RNILTAC8 : in std_logic_vector(0 to 0); - istate_RNIK9NF8 : in std_logic_vector(0 to 0); - istate_RNIA8N5H : in std_logic_vector(0 to 0); - istate_RNIOVC5J : in std_logic_vector(0 to 0); - istate_RNI6PSS1 : in std_logic_vector(0 to 0); - istate_RNIN6957 : in std_logic_vector(0 to 0); - istate_RNIKJBN8 : in std_logic_vector(0 to 0); - istate_RNI6LOO6 : in std_logic_vector(0 to 0); - istate_RNIGUTA8 : in std_logic_vector(0 to 0); - istate_RNIMRTH8 : in std_logic_vector(0 to 0); - istate_RNIV33V9 : in std_logic_vector(0 to 0); - istate_RNI7BUID : in std_logic_vector(0 to 0); - istate_RNIEC82C : in std_logic_vector(0 to 0); - istate_RNIG7IIA : in std_logic_vector(0 to 0); - istate_RNI57KLB : in std_logic_vector(0 to 0); - istate_RNI6HPAI : in std_logic_vector(0 to 0); - istate_RNIPSU8G : in std_logic_vector(0 to 0); - istate_RNIUCOFG : in std_logic_vector(0 to 0); - faddr_RNIDN2CUE : in std_logic_vector(6 to 6); - faddr_RNI7UFASD : in std_logic_vector(5 to 5); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4); - faddr_RNIUT72LB : in std_logic_vector(3 to 3); - faddr_RNISJSHQA : in std_logic_vector(2 to 2); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0); - vaddress_RNIJG6QR7 : in std_logic_vector(4 to 4); - vaddress_RNIFCB8U6 : in std_logic_vector(3 to 3); - vaddress_RNI8EVQ36 : in std_logic_vector(2 to 2); - syncramZ1_VCC : in std_logic; - lclk_c : in std_logic - ); - -end syncramZ1; - -architecture DEF_ARCH of syncramZ1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_1 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(9 downto 0) := (others => 'U'); - datain : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout : out std_logic_vector(31 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_1 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_1(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_1 - port map(clk => lclk_c, address(9) => faddr_RNIDN2CUE(6), - address(8) => faddr_RNI7UFASD(5), address(7) => - faddr_RNI0FOJNE(4), address(6) => faddr_RNIUT72LB(3), - address(5) => faddr_RNISJSHQA(2), address(4) => - faddr_RNIKVTLT9(1), address(3) => faddr_RNI7H6KT8(0), - address(2) => vaddress_RNIJG6QR7(4), address(1) => - vaddress_RNIFCB8U6(3), address(0) => - vaddress_RNI8EVQ36(2), datain(31) => istate_RNIENB3M(0), - datain(30) => istate_RNIS4VK8(0), datain(29) => - istate_RNIRASC8(0), datain(28) => istate_RNIJSOBE(0), - datain(27) => istate_RNIR2JU8(0), datain(26) => - istate_RNIOJJE1(0), datain(25) => istate_RNIAP6PI(0), - datain(24) => istate_RNIH0NBI(0), datain(23) => - istate_RNI5V68H(0), datain(22) => istate_RNIM2DE7(0), - datain(21) => istate_RNIAJH4F(0), datain(20) => - istate_RNIVTQIJ(0), datain(19) => istate_RNI2MM6D(0), - datain(18) => istate_RNI8BL1A(0), datain(17) => - istate_RNILTAC8(0), datain(16) => istate_RNIK9NF8(0), - datain(15) => istate_RNIA8N5H(0), datain(14) => - istate_RNIOVC5J(0), datain(13) => istate_RNI6PSS1(0), - datain(12) => istate_RNIN6957(0), datain(11) => - istate_RNIKJBN8(0), datain(10) => istate_RNI6LOO6(0), - datain(9) => istate_RNIGUTA8(0), datain(8) => - istate_RNIMRTH8(0), datain(7) => istate_RNIV33V9(0), - datain(6) => istate_RNI7BUID(0), datain(5) => - istate_RNIEC82C(0), datain(4) => istate_RNIG7IIA(0), - datain(3) => istate_RNI57KLB(0), datain(2) => - istate_RNI6HPAI(0), datain(1) => istate_RNIPSU8G(0), - datain(0) => istate_RNIUCOFG(0), dataout(31) => - dataout_2(31), dataout(30) => dataout_2(30), dataout(29) - => dataout_2(29), dataout(28) => dataout_2(28), - dataout(27) => dataout_1(27), dataout(26) => - dataout_1(26), dataout(25) => dataout_1(25), dataout(24) - => dataout_1(24), dataout(23) => dataout_1(23), - dataout(22) => dataout_1(22), dataout(21) => - dataout_1(21), dataout(20) => dataout_1(20), dataout(19) - => dataout_1(19), dataout(18) => dataout_1(18), - dataout(17) => dataout_1(17), dataout(16) => - dataout_1(16), dataout(15) => dataout_1(15), dataout(14) - => dataout_1(14), dataout(13) => dataout_1(13), - dataout(12) => dataout_1(12), dataout(11) => - dataout_1(11), dataout(10) => dataout_1(10), dataout(9) - => dataout_1(9), dataout(8) => dataout_1(8), dataout(7) - => dataout_1(7), dataout(6) => dataout_1(6), dataout(5) - => dataout_1(5), dataout(4) => dataout_1(4), dataout(3) - => dataout_1(3), dataout(2) => dataout_1(2), dataout(1) - => dataout_1(1), dataout(0) => dataout_1(0), enable => - syncramZ1_VCC, write => istate_RNIJCMP6(0)); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ2 is - - port( dataout_0 : out std_logic_vector(35 downto 32); - dataout_1 : out std_logic_vector(31 downto 28); - dataout_2 : out std_logic_vector(27 downto 0); - ctx : in std_logic_vector(7 downto 0); - vaddress_RNI0OAKMI : in std_logic_vector(23 to 23); - vaddress_RNIUNAKMI : in std_logic_vector(22 to 22); - vaddress_RNISNAKMI : in std_logic_vector(21 to 21); - vaddress_RNIQNAKMI : in std_logic_vector(20 to 20); - vaddress_RNI6GAKMI : in std_logic_vector(19 to 19); - vaddress_RNI4GAKMI : in std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : in std_logic_vector(17 to 17); - vaddress_RNI0GAKMI : in std_logic_vector(16 to 16); - vaddress_RNIUFAKMI : in std_logic_vector(15 to 15); - vaddress_RNISFAKMI : in std_logic_vector(14 to 14); - vaddress_RNIQFAKMI : in std_logic_vector(13 to 13); - vaddress_RNIOFAKMI : in std_logic_vector(12 to 12); - un1_p0_2_i_4 : in std_logic; - un1_p0_2_i_0 : in std_logic; - faddr_RNIDN2CUE : in std_logic_vector(6 to 6); - faddr_RNI7UFASD : in std_logic_vector(5 to 5); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4); - faddr_RNIUT72LB : in std_logic_vector(3 to 3); - faddr_RNISJSHQA : in std_logic_vector(2 to 2); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0); - un1_p0_2_0 : in std_logic_vector(148 to 148); - vitdatain_0_1_0 : in std_logic_vector(22 to 22); - flush2_RNI5I3N7 : in std_logic; - syncramZ2_VCC : in std_logic; - flush2_0_0_RNI7G6O2 : in std_logic; - flush2_RNIFMGM2 : in std_logic; - flush2_0_0_RNI146O2 : in std_logic; - flush2_0_0_RNIVV5O2 : in std_logic; - flush2_0_0_RNITR5O2 : in std_logic; - flush2_0_0_RNIPJ5O2 : in std_logic; - lclk_c : in std_logic; - N_984 : in std_logic; - N_987 : in std_logic; - flush2 : in std_logic; - N_986 : in std_logic; - N_985 : in std_logic; - un1_ici : in std_logic; - N_982 : in std_logic; - N_983 : in std_logic; - N_981 : in std_logic; - N_980 : in std_logic - ); - -end syncramZ2; - -architecture DEF_ARCH of syncramZ2 is - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_2 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(6 downto 0) := (others => 'U'); - datain : in std_logic_vector(35 downto 0) := (others => 'U'); - dataout : out std_logic_vector(35 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - signal \vitdatain_0_1[20]\, \vitdatain_0_1[21]\, - \vitdatain_0_1[23]\, \vitdatain_0_1[22]\, - \vitdatain_0_1[25]\, \vitdatain_0_1[26]\, - \vitdatain_0_1[27]\, \vitdatain_0_1[24]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_2 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_2(DEF_ARCH); -begin - - - \proa3.x0_RNO_5\ : AO1A - port map(A => un1_ici, B => N_986, C => flush2, Y => - \vitdatain_0_1[26]\); - - \proa3.x0_RNO_4\ : AO1A - port map(A => un1_ici, B => N_985, C => un1_p0_2_0(148), Y - => \vitdatain_0_1[25]\); - - \proa3.x0_RNO_2\ : NOR2 - port map(A => N_983, B => vitdatain_0_1_0(22), Y => - \vitdatain_0_1[23]\); - - \proa3.x0_RNO\ : NOR2 - port map(A => N_980, B => vitdatain_0_1_0(22), Y => - \vitdatain_0_1[20]\); - - \proa3.x0_RNO_1\ : NOR2 - port map(A => N_982, B => vitdatain_0_1_0(22), Y => - \vitdatain_0_1[22]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO_3\ : AO1A - port map(A => un1_ici, B => N_984, C => flush2, Y => - \vitdatain_0_1[24]\); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \proa3.x0_RNO_6\ : AO1A - port map(A => un1_ici, B => N_987, C => flush2, Y => - \vitdatain_0_1[27]\); - - \proa3.x0_RNO_0\ : NOR2 - port map(A => N_981, B => vitdatain_0_1_0(22), Y => - \vitdatain_0_1[21]\); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_2 - port map(clk => lclk_c, address(6) => faddr_RNIDN2CUE(6), - address(5) => faddr_RNI7UFASD(5), address(4) => - faddr_RNI0FOJNE(4), address(3) => faddr_RNIUT72LB(3), - address(2) => faddr_RNISJSHQA(2), address(1) => - faddr_RNIKVTLT9(1), address(0) => faddr_RNI7H6KT8(0), - datain(35) => ctx(7), datain(34) => ctx(6), datain(33) - => ctx(5), datain(32) => ctx(4), datain(31) => ctx(3), - datain(30) => ctx(2), datain(29) => ctx(1), datain(28) - => ctx(0), datain(27) => \vitdatain_0_1[27]\, datain(26) - => \vitdatain_0_1[26]\, datain(25) => - \vitdatain_0_1[25]\, datain(24) => \vitdatain_0_1[24]\, - datain(23) => \vitdatain_0_1[23]\, datain(22) => - \vitdatain_0_1[22]\, datain(21) => \vitdatain_0_1[21]\, - datain(20) => \vitdatain_0_1[20]\, datain(19) => - vaddress_RNI0OAKMI(23), datain(18) => - vaddress_RNIUNAKMI(22), datain(17) => - vaddress_RNISNAKMI(21), datain(16) => - vaddress_RNIQNAKMI(20), datain(15) => - vaddress_RNI6GAKMI(19), datain(14) => - vaddress_RNI4GAKMI(18), datain(13) => - vaddress_RNI2GAKMI(17), datain(12) => - vaddress_RNI0GAKMI(16), datain(11) => - vaddress_RNIUFAKMI(15), datain(10) => - vaddress_RNISFAKMI(14), datain(9) => - vaddress_RNIQFAKMI(13), datain(8) => - vaddress_RNIOFAKMI(12), datain(7) => flush2_0_0_RNI7G6O2, - datain(6) => flush2_RNIFMGM2, datain(5) => un1_p0_2_i_4, - datain(4) => flush2_0_0_RNI146O2, datain(3) => - flush2_0_0_RNIVV5O2, datain(2) => flush2_0_0_RNITR5O2, - datain(1) => un1_p0_2_i_0, datain(0) => - flush2_0_0_RNIPJ5O2, dataout(35) => dataout_0(35), - dataout(34) => dataout_0(34), dataout(33) => - dataout_0(33), dataout(32) => dataout_0(32), dataout(31) - => dataout_1(31), dataout(30) => dataout_1(30), - dataout(29) => dataout_1(29), dataout(28) => - dataout_1(28), dataout(27) => dataout_2(27), dataout(26) - => dataout_2(26), dataout(25) => dataout_2(25), - dataout(24) => dataout_2(24), dataout(23) => - dataout_2(23), dataout(22) => dataout_2(22), dataout(21) - => dataout_2(21), dataout(20) => dataout_2(20), - dataout(19) => dataout_2(19), dataout(18) => - dataout_2(18), dataout(17) => dataout_2(17), dataout(16) - => dataout_2(16), dataout(15) => dataout_2(15), - dataout(14) => dataout_2(14), dataout(13) => - dataout_2(13), dataout(12) => dataout_2(12), dataout(11) - => dataout_2(11), dataout(10) => dataout_2(10), - dataout(9) => dataout_2(9), dataout(8) => dataout_2(8), - dataout(7) => dataout_2(7), dataout(6) => dataout_2(6), - dataout(5) => dataout_2(5), dataout(4) => dataout_2(4), - dataout(3) => dataout_2(3), dataout(2) => dataout_2(2), - dataout(1) => dataout_2(1), dataout(0) => dataout_2(0), - enable => syncramZ2_VCC, write => flush2_RNI5I3N7); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity cachemem is - - port( xaddress_RNIFP43F : in std_logic_vector(2 to 2); - xaddress_RNITFTTE : in std_logic_vector(3 to 3); - dstate_RNIC3QA81 : in std_logic_vector(1 to 1); - dstate_RNIFPT581 : in std_logic_vector(1 to 1); - dstate_RNIFS6E51 : in std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : in std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : in std_logic_vector(1 to 1); - xaddress_RNILHOK61 : in std_logic_vector(1 to 1); - xaddress_RNILK99L1 : in std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : in std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : in std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : in std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : in std_logic_vector(1 to 1); - dstate_RNI1G47MJ : in std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 to 31); - addr : in std_logic_vector(30 to 30); - maddress : in std_logic_vector(28 to 28); - newtag_1_0 : in std_logic_vector(27 downto 24); - faddr_RNI7879K : in std_logic_vector(0 to 0); - faddr_RNIEHR0O : in std_logic_vector(1 to 1); - faddr_RNIB0UOO : in std_logic_vector(2 to 2); - xaddress_RNID252J1 : in std_logic_vector(10 to 10); - faddr_RNI7MK691 : in std_logic_vector(6 to 6); - dstate_i_0_RNIL7FGFS : in std_logic_vector(8 to 8); - dstate_i_0_RNIH0PPES : in std_logic_vector(8 to 8); - dstate_i_RNI29QQ7J3 : in std_logic_vector(8 to 8); - xaddress_RNITMH17S2 : in std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : in std_logic_vector(13 to 13); - xaddress_RNIN7J17S2 : in std_logic_vector(14 to 14); - xaddress_RNI2MB27S2 : in std_logic_vector(15 to 15); - xaddress_RNIID927S2 : in std_logic_vector(16 to 16); - xaddress_RNI0GI17S2 : in std_logic_vector(17 to 17); - xaddress_RNI1D927S2 : in std_logic_vector(20 to 20); - xaddress_RNIC5A27S2 : in std_logic_vector(21 to 21); - xaddress_RNI9MB27S2 : in std_logic_vector(23 to 23); - dataout : out std_logic_vector(35 downto 0); - vaddress_RNI8EVQ36 : in std_logic_vector(2 to 2); - vaddress_RNIFCB8U6 : in std_logic_vector(3 to 3); - vaddress_RNIJG6QR7 : in std_logic_vector(4 to 4); - istate_RNIUCOFG : in std_logic_vector(0 to 0); - istate_RNIPSU8G : in std_logic_vector(0 to 0); - istate_RNI6HPAI : in std_logic_vector(0 to 0); - istate_RNI57KLB : in std_logic_vector(0 to 0); - istate_RNIG7IIA : in std_logic_vector(0 to 0); - istate_RNIEC82C : in std_logic_vector(0 to 0); - istate_RNI7BUID : in std_logic_vector(0 to 0); - istate_RNIV33V9 : in std_logic_vector(0 to 0); - istate_RNIMRTH8 : in std_logic_vector(0 to 0); - istate_RNIGUTA8 : in std_logic_vector(0 to 0); - istate_RNI6LOO6 : in std_logic_vector(0 to 0); - istate_RNIKJBN8 : in std_logic_vector(0 to 0); - istate_RNIN6957 : in std_logic_vector(0 to 0); - istate_RNI6PSS1 : in std_logic_vector(0 to 0); - istate_RNIOVC5J : in std_logic_vector(0 to 0); - istate_RNIA8N5H : in std_logic_vector(0 to 0); - istate_RNIK9NF8 : in std_logic_vector(0 to 0); - istate_RNILTAC8 : in std_logic_vector(0 to 0); - istate_RNI8BL1A : in std_logic_vector(0 to 0); - istate_RNI2MM6D : in std_logic_vector(0 to 0); - istate_RNIVTQIJ : in std_logic_vector(0 to 0); - istate_RNIAJH4F : in std_logic_vector(0 to 0); - istate_RNIM2DE7 : in std_logic_vector(0 to 0); - istate_RNI5V68H : in std_logic_vector(0 to 0); - istate_RNIH0NBI : in std_logic_vector(0 to 0); - istate_RNIAP6PI : in std_logic_vector(0 to 0); - istate_RNIOJJE1 : in std_logic_vector(0 to 0); - istate_RNIR2JU8 : in std_logic_vector(0 to 0); - istate_RNIJSOBE : in std_logic_vector(0 to 0); - istate_RNIRASC8 : in std_logic_vector(0 to 0); - istate_RNIS4VK8 : in std_logic_vector(0 to 0); - istate_RNIENB3M : in std_logic_vector(0 to 0); - istate_RNIJCMP6 : in std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1); - faddr_RNISJSHQA : in std_logic_vector(2 to 2); - faddr_RNIUT72LB : in std_logic_vector(3 to 3); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4); - faddr_RNI7UFASD : in std_logic_vector(5 to 5); - faddr_RNIDN2CUE : in std_logic_vector(6 to 6); - un1_p0_2_i_0 : in std_logic; - un1_p0_2_i_4 : in std_logic; - vaddress_RNIOFAKMI : in std_logic_vector(12 to 12); - vaddress_RNIQFAKMI : in std_logic_vector(13 to 13); - vaddress_RNISFAKMI : in std_logic_vector(14 to 14); - vaddress_RNIUFAKMI : in std_logic_vector(15 to 15); - vaddress_RNI0GAKMI : in std_logic_vector(16 to 16); - vaddress_RNI2GAKMI : in std_logic_vector(17 to 17); - vaddress_RNI4GAKMI : in std_logic_vector(18 to 18); - vaddress_RNI6GAKMI : in std_logic_vector(19 to 19); - vaddress_RNIQNAKMI : in std_logic_vector(20 to 20); - vaddress_RNISNAKMI : in std_logic_vector(21 to 21); - vaddress_RNIUNAKMI : in std_logic_vector(22 to 22); - vaddress_RNI0OAKMI : in std_logic_vector(23 to 23); - ctx : in std_logic_vector(7 downto 0); - dataout_2 : out std_logic_vector(31 downto 0); - dataout_1 : out std_logic_vector(31 downto 0); - dataout_0 : out std_logic_vector(35 downto 0); - vitdatain_0_1_0 : out std_logic_vector(22 to 22); - un1_p0_2_0_0 : in std_logic; - un1_p0_2_0_350 : in std_logic; - dci_m_6 : in std_logic; - dci_m_0 : in std_logic; - dci_m_1 : in std_logic; - dci_m_2 : in std_logic; - dci_m_3 : in std_logic; - dci_m_5 : in std_logic; - N_10 : in std_logic; - read_RNI0IQ7R : in std_logic; - read_RNIRO4K31 : in std_logic; - read_RNIQFOD21 : in std_logic; - read_RNIFPFT31 : in std_logic; - read_RNIQPCQ11 : in std_logic; - read_RNI8DFM31 : in std_logic; - read_RNIAQJ831 : in std_logic; - read_RNI76N8R : in std_logic; - read_RNI7G7G41 : in std_logic; - read_RNIEKS231 : in std_logic; - read_RNIMJHQT : in std_logic; - read_RNIL633F1 : in std_logic; - read_RNIQH64D1 : in std_logic; - read_RNICAQK41 : in std_logic; - read_RNIQMJI41 : in std_logic; - read_RNISLPNU : in std_logic; - read_RNICKHE91 : in std_logic; - read_RNIC70OF1 : in std_logic; - read_RNIC9O9B1 : in std_logic; - read_RNI75LJ31 : in std_logic; - read_RNIEEGDD1 : in std_logic; - N_3254_0 : in std_logic; - N_330 : in std_logic; - N_267 : in std_logic; - N_329 : in std_logic; - N_144 : in std_logic; - N_3846 : in std_logic; - N_270 : in std_logic; - N_269 : in std_logic; - N_24 : in std_logic; - N_26 : in std_logic; - N_12_i_0 : in std_logic; - flush_RNIJEN4SI3 : in std_logic; - flush_RNIGUM2OH3 : in std_logic; - N_16_i_0 : in std_logic; - N_3239_i_0 : in std_logic; - flush_0_1_RNIBUA27S2 : in std_logic; - flush_0_1_RNIOMB27S2 : in std_logic; - flush_0_1_RNIPTA27S2 : in std_logic; - flush_RNIGBB873 : in std_logic; - N_980 : in std_logic; - N_981 : in std_logic; - N_983 : in std_logic; - N_982 : in std_logic; - N_985 : in std_logic; - N_986 : in std_logic; - flush2 : in std_logic; - N_987 : in std_logic; - N_984 : in std_logic; - lclk_c : in std_logic; - flush2_0_0_RNIPJ5O2 : in std_logic; - flush2_0_0_RNITR5O2 : in std_logic; - flush2_0_0_RNIVV5O2 : in std_logic; - flush2_0_0_RNI146O2 : in std_logic; - flush2_RNIFMGM2 : in std_logic; - flush2_0_0_RNI7G6O2 : in std_logic; - cachemem_VCC : in std_logic; - flush2_RNI5I3N7 : in std_logic; - un1_ici : in std_logic; - N_258 : in std_logic; - N_259 : in std_logic - ); - -end cachemem; - -architecture DEF_ARCH of cachemem is - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ1_1 - port( dstate_RNI1G47MJ : in std_logic_vector(1 to 1) := (others => 'U'); - dataout_0 : out std_logic_vector(31 downto 28); - dataout : out std_logic_vector(27 downto 0); - xaddress_RNIJI2O22 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIP2BVK1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIK99NK1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNI1I3MQ1 : in std_logic_vector(0 to 0) := (others => 'U'); - xaddress_RNILK99L1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNILHOK61 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIEHIUT1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNI1Q9ST1 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIFS6E51 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIFPT581 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIC3QA81 : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7MK691 : in std_logic_vector(6 to 6) := (others => 'U'); - xaddress_RNID252J1 : in std_logic_vector(10 to 10) := (others => 'U'); - faddr_RNIB0UOO : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIEHR0O : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7879K : in std_logic_vector(0 to 0) := (others => 'U'); - xaddress_RNITFTTE : in std_logic_vector(3 to 3) := (others => 'U'); - xaddress_RNIFP43F : in std_logic_vector(2 to 2) := (others => 'U'); - syncramZ1_1_VCC : in std_logic := 'U'; - read_RNIEEGDD1 : in std_logic := 'U'; - read_RNI75LJ31 : in std_logic := 'U'; - read_RNIC9O9B1 : in std_logic := 'U'; - read_RNIC70OF1 : in std_logic := 'U'; - read_RNICKHE91 : in std_logic := 'U'; - read_RNISLPNU : in std_logic := 'U'; - read_RNIQMJI41 : in std_logic := 'U'; - read_RNICAQK41 : in std_logic := 'U'; - read_RNIQH64D1 : in std_logic := 'U'; - read_RNIL633F1 : in std_logic := 'U'; - read_RNIMJHQT : in std_logic := 'U'; - read_RNIEKS231 : in std_logic := 'U'; - read_RNI7G7G41 : in std_logic := 'U'; - read_RNI76N8R : in std_logic := 'U'; - read_RNIAQJ831 : in std_logic := 'U'; - read_RNI8DFM31 : in std_logic := 'U'; - read_RNIQPCQ11 : in std_logic := 'U'; - read_RNIFPFT31 : in std_logic := 'U'; - read_RNIQFOD21 : in std_logic := 'U'; - read_RNIRO4K31 : in std_logic := 'U'; - read_RNI0IQ7R : in std_logic := 'U'; - N_26 : in std_logic := 'U'; - N_24 : in std_logic := 'U'; - N_10 : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component syncramZ2_1 - port( dataout : out std_logic_vector(35 downto 28); - dataout_0 : out std_logic_vector(27 downto 0); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - vdtdatain_0_1_5 : in std_logic := 'U'; - xaddress_RNI9MB27S2 : in std_logic_vector(23 to 23) := (others => 'U'); - xaddress_RNIC5A27S2 : in std_logic_vector(21 to 21) := (others => 'U'); - xaddress_RNI1D927S2 : in std_logic_vector(20 to 20) := (others => 'U'); - xaddress_RNI0GI17S2 : in std_logic_vector(17 to 17) := (others => 'U'); - xaddress_RNIID927S2 : in std_logic_vector(16 to 16) := (others => 'U'); - xaddress_RNI2MB27S2 : in std_logic_vector(15 to 15) := (others => 'U'); - xaddress_RNIN7J17S2 : in std_logic_vector(14 to 14) := (others => 'U'); - xaddress_RNICFI17S2 : in std_logic_vector(13 to 13) := (others => 'U'); - xaddress_RNITMH17S2 : in std_logic_vector(12 to 12) := (others => 'U'); - dstate_i_RNI29QQ7J3 : in std_logic_vector(8 to 8) := (others => 'U'); - dstate_i_0_RNIH0PPES : in std_logic_vector(8 to 8) := (others => 'U'); - dstate_i_0_RNIL7FGFS : in std_logic_vector(8 to 8) := (others => 'U'); - faddr_RNI7MK691 : in std_logic_vector(6 to 6) := (others => 'U'); - xaddress_RNID252J1 : in std_logic_vector(10 to 10) := (others => 'U'); - faddr_RNIB0UOO : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIEHR0O : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7879K : in std_logic_vector(0 to 0) := (others => 'U'); - newtag_1_0 : in std_logic_vector(27 downto 24) := (others => 'U'); - dci_m_3 : in std_logic := 'U'; - dci_m_2 : in std_logic := 'U'; - dci_m_1 : in std_logic := 'U'; - dci_m_0 : in std_logic := 'U'; - dci_m_6 : in std_logic := 'U'; - maddress : in std_logic_vector(28 to 28) := (others => 'U'); - addr : in std_logic_vector(30 to 30) := (others => 'U'); - un1_p0_2_0 : in std_logic_vector(498 to 498) := (others => 'U'); - edata2_iv_i_0 : in std_logic_vector(31 to 31) := (others => 'U'); - flush_RNIGBB873 : in std_logic := 'U'; - syncramZ2_1_VCC : in std_logic := 'U'; - flush_0_1_RNIPTA27S2 : in std_logic := 'U'; - flush_0_1_RNIOMB27S2 : in std_logic := 'U'; - flush_0_1_RNIBUA27S2 : in std_logic := 'U'; - N_3239_i_0 : in std_logic := 'U'; - N_16_i_0 : in std_logic := 'U'; - flush_RNIGUM2OH3 : in std_logic := 'U'; - flush_RNIJEN4SI3 : in std_logic := 'U'; - N_12_i_0 : in std_logic := 'U'; - N_26 : in std_logic := 'U'; - N_24 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_269 : in std_logic := 'U'; - N_270 : in std_logic := 'U'; - N_3846 : in std_logic := 'U'; - N_144 : in std_logic := 'U'; - N_329 : in std_logic := 'U'; - N_267 : in std_logic := 'U'; - N_330 : in std_logic := 'U'; - N_3254_0 : in std_logic := 'U' - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ1 - port( istate_RNIJCMP6 : in std_logic_vector(0 to 0) := (others => 'U'); - dataout_2 : out std_logic_vector(31 downto 28); - dataout_1 : out std_logic_vector(27 downto 0); - istate_RNIENB3M : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIS4VK8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIRASC8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIJSOBE : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIR2JU8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIOJJE1 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIAP6PI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIH0NBI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI5V68H : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIM2DE7 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIAJH4F : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIVTQIJ : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI2MM6D : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI8BL1A : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNILTAC8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIK9NF8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIA8N5H : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIOVC5J : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6PSS1 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIN6957 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIKJBN8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6LOO6 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIGUTA8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIMRTH8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIV33V9 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI7BUID : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIEC82C : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIG7IIA : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI57KLB : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6HPAI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIPSU8G : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIUCOFG : in std_logic_vector(0 to 0) := (others => 'U'); - faddr_RNIDN2CUE : in std_logic_vector(6 to 6) := (others => 'U'); - faddr_RNI7UFASD : in std_logic_vector(5 to 5) := (others => 'U'); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4) := (others => 'U'); - faddr_RNIUT72LB : in std_logic_vector(3 to 3) := (others => 'U'); - faddr_RNISJSHQA : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0) := (others => 'U'); - vaddress_RNIJG6QR7 : in std_logic_vector(4 to 4) := (others => 'U'); - vaddress_RNIFCB8U6 : in std_logic_vector(3 to 3) := (others => 'U'); - vaddress_RNI8EVQ36 : in std_logic_vector(2 to 2) := (others => 'U'); - syncramZ1_VCC : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component syncramZ2 - port( dataout_0 : out std_logic_vector(35 downto 32); - dataout_1 : out std_logic_vector(31 downto 28); - dataout_2 : out std_logic_vector(27 downto 0); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - vaddress_RNI0OAKMI : in std_logic_vector(23 to 23) := (others => 'U'); - vaddress_RNIUNAKMI : in std_logic_vector(22 to 22) := (others => 'U'); - vaddress_RNISNAKMI : in std_logic_vector(21 to 21) := (others => 'U'); - vaddress_RNIQNAKMI : in std_logic_vector(20 to 20) := (others => 'U'); - vaddress_RNI6GAKMI : in std_logic_vector(19 to 19) := (others => 'U'); - vaddress_RNI4GAKMI : in std_logic_vector(18 to 18) := (others => 'U'); - vaddress_RNI2GAKMI : in std_logic_vector(17 to 17) := (others => 'U'); - vaddress_RNI0GAKMI : in std_logic_vector(16 to 16) := (others => 'U'); - vaddress_RNIUFAKMI : in std_logic_vector(15 to 15) := (others => 'U'); - vaddress_RNISFAKMI : in std_logic_vector(14 to 14) := (others => 'U'); - vaddress_RNIQFAKMI : in std_logic_vector(13 to 13) := (others => 'U'); - vaddress_RNIOFAKMI : in std_logic_vector(12 to 12) := (others => 'U'); - un1_p0_2_i_4 : in std_logic := 'U'; - un1_p0_2_i_0 : in std_logic := 'U'; - faddr_RNIDN2CUE : in std_logic_vector(6 to 6) := (others => 'U'); - faddr_RNI7UFASD : in std_logic_vector(5 to 5) := (others => 'U'); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4) := (others => 'U'); - faddr_RNIUT72LB : in std_logic_vector(3 to 3) := (others => 'U'); - faddr_RNISJSHQA : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0) := (others => 'U'); - un1_p0_2_0 : in std_logic_vector(148 to 148) := (others => 'U'); - vitdatain_0_1_0 : in std_logic_vector(22 to 22) := (others => 'U'); - flush2_RNI5I3N7 : in std_logic := 'U'; - syncramZ2_VCC : in std_logic := 'U'; - flush2_0_0_RNI7G6O2 : in std_logic := 'U'; - flush2_RNIFMGM2 : in std_logic := 'U'; - flush2_0_0_RNI146O2 : in std_logic := 'U'; - flush2_0_0_RNIVV5O2 : in std_logic := 'U'; - flush2_0_0_RNITR5O2 : in std_logic := 'U'; - flush2_0_0_RNIPJ5O2 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_984 : in std_logic := 'U'; - N_987 : in std_logic := 'U'; - flush2 : in std_logic := 'U'; - N_986 : in std_logic := 'U'; - N_985 : in std_logic := 'U'; - un1_ici : in std_logic := 'U'; - N_982 : in std_logic := 'U'; - N_983 : in std_logic := 'U'; - N_981 : in std_logic := 'U'; - N_980 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \vdtdatain_0_1[25]\, \vdtdatain_0_1_0[25]\, - \vdtdatain_0_1_1[25]\, \vitdatain_0_1_0[22]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : syncramZ1_1 - Use entity work.syncramZ1_1(DEF_ARCH); - for all : syncramZ2_1 - Use entity work.syncramZ2_1(DEF_ARCH); - for all : syncramZ1 - Use entity work.syncramZ1(DEF_ARCH); - for all : syncramZ2 - Use entity work.syncramZ2(DEF_ARCH); -begin - - vitdatain_0_1_0(22) <= \vitdatain_0_1_0[22]\; - - \itinsel.vdtdatain_0_1[25]\ : NAND2 - port map(A => \vdtdatain_0_1_0[25]\, B => - \vdtdatain_0_1_1[25]\, Y => \vdtdatain_0_1[25]\); - - \itinsel.vitdatain_0_1_0[20]\ : OR2 - port map(A => un1_p0_2_0_0, B => un1_ici, Y => - \vitdatain_0_1_0[22]\); - - \itinsel.vdtdatain_0_1_RNO[25]\ : AND2 - port map(A => N_259, B => N_258, Y => \vdtdatain_0_1_0[25]\); - - \dme.dd0.0.ddata0\ : syncramZ1_1 - port map(dstate_RNI1G47MJ(1) => dstate_RNI1G47MJ(1), - dataout_0(31) => dataout_0(31), dataout_0(30) => - dataout_0(30), dataout_0(29) => dataout_0(29), - dataout_0(28) => dataout_0(28), dataout(27) => - dataout(27), dataout(26) => dataout(26), dataout(25) => - dataout(25), dataout(24) => dataout(24), dataout(23) => - dataout(23), dataout(22) => dataout(22), dataout(21) => - dataout(21), dataout(20) => dataout(20), dataout(19) => - dataout(19), dataout(18) => dataout(18), dataout(17) => - dataout(17), dataout(16) => dataout(16), dataout(15) => - dataout(15), dataout(14) => dataout(14), dataout(13) => - dataout(13), dataout(12) => dataout(12), dataout(11) => - dataout(11), dataout(10) => dataout(10), dataout(9) => - dataout(9), dataout(8) => dataout(8), dataout(7) => - dataout(7), dataout(6) => dataout(6), dataout(5) => - dataout(5), dataout(4) => dataout(4), dataout(3) => - dataout(3), dataout(2) => dataout(2), dataout(1) => - dataout(1), dataout(0) => dataout(0), - xaddress_RNIJI2O22(1) => xaddress_RNIJI2O22(1), - xaddress_RNIP2BVK1(1) => xaddress_RNIP2BVK1(1), - xaddress_RNIK99NK1(1) => xaddress_RNIK99NK1(1), - xaddress_RNI1I3MQ1(0) => xaddress_RNI1I3MQ1(0), - xaddress_RNILK99L1(1) => xaddress_RNILK99L1(1), - xaddress_RNILHOK61(1) => xaddress_RNILHOK61(1), - xaddress_RNIEHIUT1(1) => xaddress_RNIEHIUT1(1), - xaddress_RNI1Q9ST1(1) => xaddress_RNI1Q9ST1(1), - dstate_RNIFS6E51(1) => dstate_RNIFS6E51(1), - dstate_RNIFPT581(1) => dstate_RNIFPT581(1), - dstate_RNIC3QA81(1) => dstate_RNIC3QA81(1), - faddr_RNI7MK691(6) => faddr_RNI7MK691(6), - xaddress_RNID252J1(10) => xaddress_RNID252J1(10), - faddr_RNIB0UOO(2) => faddr_RNIB0UOO(2), faddr_RNIEHR0O(1) - => faddr_RNIEHR0O(1), faddr_RNI7879K(0) => - faddr_RNI7879K(0), xaddress_RNITFTTE(3) => - xaddress_RNITFTTE(3), xaddress_RNIFP43F(2) => - xaddress_RNIFP43F(2), syncramZ1_1_VCC => cachemem_VCC, - read_RNIEEGDD1 => read_RNIEEGDD1, read_RNI75LJ31 => - read_RNI75LJ31, read_RNIC9O9B1 => read_RNIC9O9B1, - read_RNIC70OF1 => read_RNIC70OF1, read_RNICKHE91 => - read_RNICKHE91, read_RNISLPNU => read_RNISLPNU, - read_RNIQMJI41 => read_RNIQMJI41, read_RNICAQK41 => - read_RNICAQK41, read_RNIQH64D1 => read_RNIQH64D1, - read_RNIL633F1 => read_RNIL633F1, read_RNIMJHQT => - read_RNIMJHQT, read_RNIEKS231 => read_RNIEKS231, - read_RNI7G7G41 => read_RNI7G7G41, read_RNI76N8R => - read_RNI76N8R, read_RNIAQJ831 => read_RNIAQJ831, - read_RNI8DFM31 => read_RNI8DFM31, read_RNIQPCQ11 => - read_RNIQPCQ11, read_RNIFPFT31 => read_RNIFPFT31, - read_RNIQFOD21 => read_RNIQFOD21, read_RNIRO4K31 => - read_RNIRO4K31, read_RNI0IQ7R => read_RNI0IQ7R, N_26 => - N_26, N_24 => N_24, N_10 => N_10, lclk_c => lclk_c); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \dme.dtags0.dt0.0.dtags0\ : syncramZ2_1 - port map(dataout(35) => dataout(35), dataout(34) => - dataout(34), dataout(33) => dataout(33), dataout(32) => - dataout(32), dataout(31) => dataout(31), dataout(30) => - dataout(30), dataout(29) => dataout(29), dataout(28) => - dataout(28), dataout_0(27) => dataout_0(27), - dataout_0(26) => dataout_0(26), dataout_0(25) => - dataout_0(25), dataout_0(24) => dataout_0(24), - dataout_0(23) => dataout_0(23), dataout_0(22) => - dataout_0(22), dataout_0(21) => dataout_0(21), - dataout_0(20) => dataout_0(20), dataout_0(19) => - dataout_0(19), dataout_0(18) => dataout_0(18), - dataout_0(17) => dataout_0(17), dataout_0(16) => - dataout_0(16), dataout_0(15) => dataout_0(15), - dataout_0(14) => dataout_0(14), dataout_0(13) => - dataout_0(13), dataout_0(12) => dataout_0(12), - dataout_0(11) => dataout_0(11), dataout_0(10) => - dataout_0(10), dataout_0(9) => dataout_0(9), dataout_0(8) - => dataout_0(8), dataout_0(7) => dataout_0(7), - dataout_0(6) => dataout_0(6), dataout_0(5) => - dataout_0(5), dataout_0(4) => dataout_0(4), dataout_0(3) - => dataout_0(3), dataout_0(2) => dataout_0(2), - dataout_0(1) => dataout_0(1), dataout_0(0) => - dataout_0(0), ctx(7) => ctx(7), ctx(6) => ctx(6), ctx(5) - => ctx(5), ctx(4) => ctx(4), ctx(3) => ctx(3), ctx(2) - => ctx(2), ctx(1) => ctx(1), ctx(0) => ctx(0), - vdtdatain_0_1_5 => \vdtdatain_0_1[25]\, - xaddress_RNI9MB27S2(23) => xaddress_RNI9MB27S2(23), - xaddress_RNIC5A27S2(21) => xaddress_RNIC5A27S2(21), - xaddress_RNI1D927S2(20) => xaddress_RNI1D927S2(20), - xaddress_RNI0GI17S2(17) => xaddress_RNI0GI17S2(17), - xaddress_RNIID927S2(16) => xaddress_RNIID927S2(16), - xaddress_RNI2MB27S2(15) => xaddress_RNI2MB27S2(15), - xaddress_RNIN7J17S2(14) => xaddress_RNIN7J17S2(14), - xaddress_RNICFI17S2(13) => xaddress_RNICFI17S2(13), - xaddress_RNITMH17S2(12) => xaddress_RNITMH17S2(12), - dstate_i_RNI29QQ7J3(8) => dstate_i_RNI29QQ7J3(8), - dstate_i_0_RNIH0PPES(8) => dstate_i_0_RNIH0PPES(8), - dstate_i_0_RNIL7FGFS(8) => dstate_i_0_RNIL7FGFS(8), - faddr_RNI7MK691(6) => faddr_RNI7MK691(6), - xaddress_RNID252J1(10) => xaddress_RNID252J1(10), - faddr_RNIB0UOO(2) => faddr_RNIB0UOO(2), faddr_RNIEHR0O(1) - => faddr_RNIEHR0O(1), faddr_RNI7879K(0) => - faddr_RNI7879K(0), newtag_1_0(27) => newtag_1_0(27), - newtag_1_0(26) => newtag_1_0(26), newtag_1_0(25) => - newtag_1_0(25), newtag_1_0(24) => newtag_1_0(24), dci_m_3 - => dci_m_3, dci_m_2 => dci_m_2, dci_m_1 => dci_m_1, - dci_m_0 => dci_m_0, dci_m_6 => dci_m_6, maddress(28) => - maddress(28), addr(30) => addr(30), un1_p0_2_0(498) => - un1_p0_2_0_350, edata2_iv_i_0(31) => edata2_iv_i_0(31), - flush_RNIGBB873 => flush_RNIGBB873, syncramZ2_1_VCC => - cachemem_VCC, flush_0_1_RNIPTA27S2 => - flush_0_1_RNIPTA27S2, flush_0_1_RNIOMB27S2 => - flush_0_1_RNIOMB27S2, flush_0_1_RNIBUA27S2 => - flush_0_1_RNIBUA27S2, N_3239_i_0 => N_3239_i_0, N_16_i_0 - => N_16_i_0, flush_RNIGUM2OH3 => flush_RNIGUM2OH3, - flush_RNIJEN4SI3 => flush_RNIJEN4SI3, N_12_i_0 => - N_12_i_0, N_26 => N_26, N_24 => N_24, lclk_c => lclk_c, - N_269 => N_269, N_270 => N_270, N_3846 => N_3846, N_144 - => N_144, N_329 => N_329, N_267 => N_267, N_330 => N_330, - N_3254_0 => N_3254_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \itinsel.vdtdatain_0_1_RNO_0[25]\ : NOR2A - port map(A => dci_m_5, B => un1_p0_2_0_350, Y => - \vdtdatain_0_1_1[25]\); - - \ime.im0.0.idata0\ : syncramZ1 - port map(istate_RNIJCMP6(0) => istate_RNIJCMP6(0), - dataout_2(31) => dataout_2(31), dataout_2(30) => - dataout_2(30), dataout_2(29) => dataout_2(29), - dataout_2(28) => dataout_2(28), dataout_1(27) => - dataout_1(27), dataout_1(26) => dataout_1(26), - dataout_1(25) => dataout_1(25), dataout_1(24) => - dataout_1(24), dataout_1(23) => dataout_1(23), - dataout_1(22) => dataout_1(22), dataout_1(21) => - dataout_1(21), dataout_1(20) => dataout_1(20), - dataout_1(19) => dataout_1(19), dataout_1(18) => - dataout_1(18), dataout_1(17) => dataout_1(17), - dataout_1(16) => dataout_1(16), dataout_1(15) => - dataout_1(15), dataout_1(14) => dataout_1(14), - dataout_1(13) => dataout_1(13), dataout_1(12) => - dataout_1(12), dataout_1(11) => dataout_1(11), - dataout_1(10) => dataout_1(10), dataout_1(9) => - dataout_1(9), dataout_1(8) => dataout_1(8), dataout_1(7) - => dataout_1(7), dataout_1(6) => dataout_1(6), - dataout_1(5) => dataout_1(5), dataout_1(4) => - dataout_1(4), dataout_1(3) => dataout_1(3), dataout_1(2) - => dataout_1(2), dataout_1(1) => dataout_1(1), - dataout_1(0) => dataout_1(0), istate_RNIENB3M(0) => - istate_RNIENB3M(0), istate_RNIS4VK8(0) => - istate_RNIS4VK8(0), istate_RNIRASC8(0) => - istate_RNIRASC8(0), istate_RNIJSOBE(0) => - istate_RNIJSOBE(0), istate_RNIR2JU8(0) => - istate_RNIR2JU8(0), istate_RNIOJJE1(0) => - istate_RNIOJJE1(0), istate_RNIAP6PI(0) => - istate_RNIAP6PI(0), istate_RNIH0NBI(0) => - istate_RNIH0NBI(0), istate_RNI5V68H(0) => - istate_RNI5V68H(0), istate_RNIM2DE7(0) => - istate_RNIM2DE7(0), istate_RNIAJH4F(0) => - istate_RNIAJH4F(0), istate_RNIVTQIJ(0) => - istate_RNIVTQIJ(0), istate_RNI2MM6D(0) => - istate_RNI2MM6D(0), istate_RNI8BL1A(0) => - istate_RNI8BL1A(0), istate_RNILTAC8(0) => - istate_RNILTAC8(0), istate_RNIK9NF8(0) => - istate_RNIK9NF8(0), istate_RNIA8N5H(0) => - istate_RNIA8N5H(0), istate_RNIOVC5J(0) => - istate_RNIOVC5J(0), istate_RNI6PSS1(0) => - istate_RNI6PSS1(0), istate_RNIN6957(0) => - istate_RNIN6957(0), istate_RNIKJBN8(0) => - istate_RNIKJBN8(0), istate_RNI6LOO6(0) => - istate_RNI6LOO6(0), istate_RNIGUTA8(0) => - istate_RNIGUTA8(0), istate_RNIMRTH8(0) => - istate_RNIMRTH8(0), istate_RNIV33V9(0) => - istate_RNIV33V9(0), istate_RNI7BUID(0) => - istate_RNI7BUID(0), istate_RNIEC82C(0) => - istate_RNIEC82C(0), istate_RNIG7IIA(0) => - istate_RNIG7IIA(0), istate_RNI57KLB(0) => - istate_RNI57KLB(0), istate_RNI6HPAI(0) => - istate_RNI6HPAI(0), istate_RNIPSU8G(0) => - istate_RNIPSU8G(0), istate_RNIUCOFG(0) => - istate_RNIUCOFG(0), faddr_RNIDN2CUE(6) => - faddr_RNIDN2CUE(6), faddr_RNI7UFASD(5) => - faddr_RNI7UFASD(5), faddr_RNI0FOJNE(4) => - faddr_RNI0FOJNE(4), faddr_RNIUT72LB(3) => - faddr_RNIUT72LB(3), faddr_RNISJSHQA(2) => - faddr_RNISJSHQA(2), faddr_RNIKVTLT9(1) => - faddr_RNIKVTLT9(1), faddr_RNI7H6KT8(0) => - faddr_RNI7H6KT8(0), vaddress_RNIJG6QR7(4) => - vaddress_RNIJG6QR7(4), vaddress_RNIFCB8U6(3) => - vaddress_RNIFCB8U6(3), vaddress_RNI8EVQ36(2) => - vaddress_RNI8EVQ36(2), syncramZ1_VCC => cachemem_VCC, - lclk_c => lclk_c); - - \ime.im0.0.itags0\ : syncramZ2 - port map(dataout_0(35) => dataout_0(35), dataout_0(34) => - dataout_0(34), dataout_0(33) => dataout_0(33), - dataout_0(32) => dataout_0(32), dataout_1(31) => - dataout_1(31), dataout_1(30) => dataout_1(30), - dataout_1(29) => dataout_1(29), dataout_1(28) => - dataout_1(28), dataout_2(27) => dataout_2(27), - dataout_2(26) => dataout_2(26), dataout_2(25) => - dataout_2(25), dataout_2(24) => dataout_2(24), - dataout_2(23) => dataout_2(23), dataout_2(22) => - dataout_2(22), dataout_2(21) => dataout_2(21), - dataout_2(20) => dataout_2(20), dataout_2(19) => - dataout_2(19), dataout_2(18) => dataout_2(18), - dataout_2(17) => dataout_2(17), dataout_2(16) => - dataout_2(16), dataout_2(15) => dataout_2(15), - dataout_2(14) => dataout_2(14), dataout_2(13) => - dataout_2(13), dataout_2(12) => dataout_2(12), - dataout_2(11) => dataout_2(11), dataout_2(10) => - dataout_2(10), dataout_2(9) => dataout_2(9), dataout_2(8) - => dataout_2(8), dataout_2(7) => dataout_2(7), - dataout_2(6) => dataout_2(6), dataout_2(5) => - dataout_2(5), dataout_2(4) => dataout_2(4), dataout_2(3) - => dataout_2(3), dataout_2(2) => dataout_2(2), - dataout_2(1) => dataout_2(1), dataout_2(0) => - dataout_2(0), ctx(7) => ctx(7), ctx(6) => ctx(6), ctx(5) - => ctx(5), ctx(4) => ctx(4), ctx(3) => ctx(3), ctx(2) - => ctx(2), ctx(1) => ctx(1), ctx(0) => ctx(0), - vaddress_RNI0OAKMI(23) => vaddress_RNI0OAKMI(23), - vaddress_RNIUNAKMI(22) => vaddress_RNIUNAKMI(22), - vaddress_RNISNAKMI(21) => vaddress_RNISNAKMI(21), - vaddress_RNIQNAKMI(20) => vaddress_RNIQNAKMI(20), - vaddress_RNI6GAKMI(19) => vaddress_RNI6GAKMI(19), - vaddress_RNI4GAKMI(18) => vaddress_RNI4GAKMI(18), - vaddress_RNI2GAKMI(17) => vaddress_RNI2GAKMI(17), - vaddress_RNI0GAKMI(16) => vaddress_RNI0GAKMI(16), - vaddress_RNIUFAKMI(15) => vaddress_RNIUFAKMI(15), - vaddress_RNISFAKMI(14) => vaddress_RNISFAKMI(14), - vaddress_RNIQFAKMI(13) => vaddress_RNIQFAKMI(13), - vaddress_RNIOFAKMI(12) => vaddress_RNIOFAKMI(12), - un1_p0_2_i_4 => un1_p0_2_i_4, un1_p0_2_i_0 => - un1_p0_2_i_0, faddr_RNIDN2CUE(6) => faddr_RNIDN2CUE(6), - faddr_RNI7UFASD(5) => faddr_RNI7UFASD(5), - faddr_RNI0FOJNE(4) => faddr_RNI0FOJNE(4), - faddr_RNIUT72LB(3) => faddr_RNIUT72LB(3), - faddr_RNISJSHQA(2) => faddr_RNISJSHQA(2), - faddr_RNIKVTLT9(1) => faddr_RNIKVTLT9(1), - faddr_RNI7H6KT8(0) => faddr_RNI7H6KT8(0), un1_p0_2_0(148) - => un1_p0_2_0_0, vitdatain_0_1_0(22) => - \vitdatain_0_1_0[22]\, flush2_RNI5I3N7 => flush2_RNI5I3N7, - syncramZ2_VCC => cachemem_VCC, flush2_0_0_RNI7G6O2 => - flush2_0_0_RNI7G6O2, flush2_RNIFMGM2 => flush2_RNIFMGM2, - flush2_0_0_RNI146O2 => flush2_0_0_RNI146O2, - flush2_0_0_RNIVV5O2 => flush2_0_0_RNIVV5O2, - flush2_0_0_RNITR5O2 => flush2_0_0_RNITR5O2, - flush2_0_0_RNIPJ5O2 => flush2_0_0_RNIPJ5O2, lclk_c => - lclk_c, N_984 => N_984, N_987 => N_987, flush2 => flush2, - N_986 => N_986, N_985 => N_985, un1_ici => un1_ici, N_982 - => N_982, N_983 => N_983, N_981 => N_981, N_980 => N_980); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity iu3 is - - port( asi_0 : out std_logic_vector(4 downto 0); - wdata : out std_logic_vector(31 downto 0); - size_0_1 : out std_logic; - size_1_0 : out std_logic; - rdatav_0_1_1_iv_7 : in std_logic_vector(6 to 6); - rdatav_0_1_0_iv_7 : in std_logic_vector(2 to 2); - rdatav_0_1_0_iv_0_2 : in std_logic_vector(10 to 10); - rdatav_0_1_0_iv_5_4 : in std_logic; - rdatav_0_1_0_iv_5_1 : in std_logic; - rdatav_0_1_0_iv_5_0 : in std_logic; - rdatav_0_1_0_iv_5_6 : in std_logic; - waddr : out std_logic_vector(7 downto 0); - rfa2 : out std_logic_vector(7 downto 0); - raddr2 : out std_logic_vector(7 downto 0); - rfa1 : out std_logic_vector(7 downto 0); - raddr1 : out std_logic_vector(7 downto 0); - data_0_2_13 : in std_logic; - data_0_2_14 : in std_logic; - data_0_2_17 : in std_logic; - data_0_2_16 : in std_logic; - data_0_2_8 : in std_logic; - data_0_2_24 : in std_logic; - data_0_2_31 : in std_logic; - data_0_2_30 : in std_logic; - data_0_2_29 : in std_logic; - data_0_2_28 : in std_logic; - data_0_2_27 : in std_logic; - data_0_2_26 : in std_logic; - data_0_2_25 : in std_logic; - data_0_2_21 : in std_logic; - data_0_2_4 : in std_logic; - data_0_2_0 : in std_logic; - edata2_iv_i_0 : out std_logic_vector(31 downto 24); - rpc_6 : out std_logic; - rpc_8 : out std_logic; - rpc_5 : out std_logic; - rpc_7 : out std_logic; - rpc_2 : out std_logic; - rpc_0 : out std_logic; - rpc_1 : out std_logic; - rpc_3 : out std_logic; - irl_0 : in std_logic_vector(3 downto 0); - irl : out std_logic_vector(3 downto 0); - data2 : in std_logic_vector(31 downto 0); - mcdo_m_0_27 : in std_logic; - mcdo_m_0_29 : in std_logic; - mcdo_m_0_4 : in std_logic; - mcdo_m_0_20 : in std_logic; - mcdo_m_0_17 : in std_logic; - mcdo_m_0_0 : in std_logic; - mcdo_m_0_16 : in std_logic; - mcdo_m_0_7 : in std_logic; - mcdo_m_0_22 : in std_logic; - mcdo_m_0_21 : in std_logic; - rdatav_0_1_0_iv_4_20 : in std_logic; - rdatav_0_1_0_iv_4_22 : in std_logic; - rdatav_0_1_0_iv_4_0 : in std_logic; - rdatav_0_1_0_iv_4_14 : in std_logic; - maddress : out std_logic_vector(31 downto 0); - data1 : in std_logic_vector(31 downto 0); - un1_p0_6_0 : out std_logic; - edata2_0_iv : out std_logic_vector(23 downto 0); - fpc : out std_logic_vector(31 downto 2); - data_0_0_15 : in std_logic; - data_0_0_20 : in std_logic; - data_0_0_11 : in std_logic; - data_0_0_6 : in std_logic; - data_0_0_23 : in std_logic; - data_0_0_19 : in std_logic; - data_0_0_17 : in std_logic; - data_0_0_16 : in std_logic; - data_0_0_14 : in std_logic; - data_0_0_13 : in std_logic; - data_0_0_12 : in std_logic; - data_0_0_10 : in std_logic; - data_0_0_9 : in std_logic; - data_0_0_7 : in std_logic; - data_0_0_5 : in std_logic; - data_0_0_3 : in std_logic; - data_0_0_2 : in std_logic; - data_0_0_1 : in std_logic; - data_0_0_0 : in std_logic; - data_0_0_4 : in std_logic; - data_0_0_26 : in std_logic; - data_0_0_8 : in std_logic; - data_0_0_28 : in std_logic; - data_0_0_27 : in std_logic; - data_0_0_30 : in std_logic; - data_0_0_25 : in std_logic; - data_0_0_24 : in std_logic; - data_0_0_21 : in std_logic; - eaddress_4 : out std_logic; - eaddress_2 : out std_logic; - eaddress_12 : out std_logic; - eaddress_24 : out std_logic; - eaddress_5 : out std_logic; - eaddress_11 : out std_logic; - eaddress_30 : out std_logic; - eaddress_6 : out std_logic; - eaddress_3 : out std_logic; - eaddress_27 : out std_logic; - eaddress_31 : out std_logic; - eaddress_15 : out std_logic; - eaddress_17 : out std_logic; - eaddress_20 : out std_logic; - eaddress_18 : out std_logic; - eaddress_26 : out std_logic; - eaddress_14 : out std_logic; - eaddress_21 : out std_logic; - eaddress_25 : out std_logic; - eaddress_29 : out std_logic; - eaddress_19 : out std_logic; - eaddress_23 : out std_logic; - eaddress_22 : out std_logic; - eaddress_9 : out std_logic; - eaddress_10 : out std_logic; - eaddress_7 : out std_logic; - eaddress_8 : out std_logic; - data_0_22 : in std_logic; - data_0_20 : in std_logic; - data_0_18 : in std_logic; - data_0_15 : in std_logic; - data_0_11 : in std_logic; - data_0_7 : in std_logic; - data_0_12 : in std_logic; - data_0_31 : in std_logic; - data_0_29 : in std_logic; - dco_i_2 : in std_logic_vector(132 to 132); - maddress_0_2 : out std_logic; - maddress_0_0 : out std_logic; - msu : out std_logic; - error_i_2 : out std_logic; - read_1 : out std_logic; - write_0 : out std_logic; - mexc_2 : in std_logic; - enaddr : out std_logic; - eenaddr : out std_logic; - N_26 : out std_logic; - lock : out std_logic; - N_28 : out std_logic; - su_0 : out std_logic; - rfe2 : out std_logic; - ren2 : out std_logic; - mexc : in std_logic; - N_3305_0 : in std_logic; - intack_2 : out std_logic; - wren : out std_logic; - rfe1 : out std_logic; - ren1 : out std_logic; - werr_2 : in std_logic; - rstate_1188n : in std_logic; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : in std_logic; - ldlock_3_0 : out std_logic; - rst_RNIINI1H : in std_logic; - rbranch : out std_logic; - r_N_6 : out std_logic; - un1_addout_12 : out std_logic; - flush_i_0 : out std_logic; - N_3389_i_0 : in std_logic; - N_3227_i_0 : in std_logic; - N_3387_i_0 : in std_logic; - nullify : out std_logic; - ldlock_2 : out std_logic; - fbranch : out std_logic; - d_m5_0_a3_2 : out std_logic; - hold_pc_7 : out std_logic; - nullify2_0_sqmuxa : out std_logic; - me_nullify2_1_2 : out std_logic; - un9_icc_check_bp : out std_logic; - inull : out std_logic; - de_hold_pc_1 : out std_logic; - rst : in std_logic; - un17_casaen_0_0 : out std_logic; - xc_exception_1_0 : out std_logic; - mds : in std_logic; - ra_bpmiss_1_0 : out std_logic; - read_0 : out std_logic; - holdn : in std_logic; - lclk_c : in std_logic - ); - -end iu3; - -architecture DEF_ARCH of iu3 is - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO16 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI4 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_p0_6_0[51]\, \inst_0_0_0_RNI7TVIO2[12]\, - \un1_p0_6_0[60]\, \inst_0_0_0_RNIQ98I03[21]\, \eres2[1]\, - \eres2[3]\, read, wy_0, wy, \npc_0[0]\, \npc_1[0]\, - \npc_1[1]\, \npc_1_0[1]\, \npc_0[1]\, \rsel2_1[0]\, - N_3944, \rsel2_0[0]\, \aluop_0[0]\, \aluop[0]\, - \aluop_2[1]\, \aluop[1]\, \aluop_1[1]\, \aluop_0[1]\, - \aluop_0[2]\, \aluop[2]\, \rsel1_0[2]\, rs1, ldbp2_2, - ldbp2, ldbp2_1, ldbp2_0, invop2_1, N_6680, invop2_0, - mulstep_0, mulstep, ld_0, ld, ldbp1_4, ldbp, ldbp1_3, - ldbp1_2, ldbp1_1, ldbp1_0, y08_0, wy_1, d27_0, d28_0_0, - wy_1_0, wy_2, y14_0, shleft_1, N_208, shleft_0, - edata_3_sqmuxa_0, un1_logicout21, un17_casaen_0, - ex_bpmiss_1_0, ex_bpmiss_1_0_1, ex_bpmiss_1_0_2, - ra_bpmiss_1_1, branch, jump_0, jump_1_sqmuxa_1_i_0, - jump_0_sqmuxa_1_i_0, annul, de_hold_pc_1_0, - un2_rstn_5_0_i, un18_hold_pc, un2_rstn_3_0, - un12_de_hold_pc, un2_rstn_4_0_0, un2_rstn_4_0, - un2_rstn_5_2, un2_rstn_5_0, \un2_rstn_5_0_0\, - mexc_1_sqmuxa_1_0, un14_casaen_s0_0_1, d26, - un17_casaen_0_2, \rstate_0[0]\, N_6322s, s_3_sqmuxa_0, - \rstate_d[2]\, xc_wreg9, rstate_6314_d_0, \rstate[1]\, - N_481_0, y_1_sqmuxa_1, y_1_sqmuxa_0, d25_0, d26_0, - un14_casaen_s1_0_1, d31_0, \rsel2[2]\, \rsel2[1]\, - aluresult_7_sqmuxa_0_0, aluresult_7_sqmuxa_0, - logicout21_1, ld_0_0, mexc_1_sqmuxa_0, - aluresult_10_sqmuxa_0, miscout69, logicout20, - aluresult_9_sqmuxa_1, aluresult_12_sqmuxa_0_0, - aluresult_12_sqmuxa_0, aluresult_12_sqmuxa_4, - aluresult_12_sqmuxa_5, aluresult_1_sqmuxa_0, jmpl, - aluresult_1_sqmuxa_0_0, \ex_shcnt_1[0]\, ex_sari_1_1_0_0, - sari, ex_sari_1, aluresult_2_sqmuxa_0, jmpl_0, - miscout_11_sqmuxa, aluresult_0_sqmuxa_0, aluresult12, - aluresult_3_sqmuxa_0, \alusel[1]\, \alusel[0]\, d14_0, - \rsel1[0]\, \rsel1[1]\, bpdata6_0_0, bpdata6_8, bpdata6_7, - bpdata6_9, d13_0, N_484, un14_casaen_s1_0_0, N_494, - un14_casaen_s0_0_0, d11_0, d11_0_a5_0, N_227_0, N_226, - N_203, N_204, un1_aop2_1_sqmuxa_0, N_457, N_456, N_458, - N_484_0, call_hold5_0, \inst_0[31]\, \inst_0[30]\, casa, - N_3355_1, un17_casaen_0_1, \ex_shcnt_1_i_0[1]\, - \shcnt[1]\, N_3305, \ex_shcnt_1_i_0[2]\, \shcnt[2]\, - N_3306, \ex_shcnt_1_i_0[3]\, \shcnt[3]\, N_3307, - \ex_shcnt_1_i_0[4]\, \shcnt[4]\, N_3308, bpmiss_1_i_0_0, - \ra_bpmiss_1_0\, N_6763_i_0, N_6922_i_0, wy_RNILF1N3, - N_6866_i_0, N_6697_i_0_0, N_451, \aop2_i_o2_2[0]\, N_452, - wy_1_0_0, d29_0_0, \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_TMP[0]\, \ncwp[1]\, - \DWACT_ADD_CI_0_g_array_1_0[0]\, - \DWACT_ADD_CI_0_TMP_0[0]\, \cwp[1]\, - \DWACT_ADD_CI_0_g_array_1_1[0]\, - \DWACT_ADD_CI_0_TMP_1[0]\, - \DWACT_ADD_CI_0_g_array_1_2[0]\, - \DWACT_ADD_CI_0_TMP_2[0]\, N_147, \fe_pc[3]\, \fe_pc[2]\, - N_139, \fe_pc[5]\, \DWACT_FINC_E[0]\, N_116, \fe_pc[10]\, - \DWACT_FINC_E[4]\, N_101, \DWACT_FINC_E[7]\, - \DWACT_FINC_E[6]\, \un6_ex_add_res_s2_1[26]\, - \data_0[25]\, \un1_iu0_6[25]\, \un6_ex_add_res_s2[26]\, - N776, \un6_ex_add_res_s0[26]\, N776_0, N814, I249_un1_Y_i, - N668, \dco_m_0[125]\, rdata_5_sqmuxa, I157_un1_Y_i, - N561_i, N568, \un6_ex_add_res_s0[31]\, N766, - \un6_ex_add_res_s2_1[31]\, \un6_ex_add_res_s2[31]\, - N766_0, \data_0[30]\, \un1_iu0_6[30]\, N495, N_50, N485_i, - \op2[29]\, \un1_iu0_6[29]\, N482, \un1_iu0_6[28]\, - \data_0[28]\, \data_0_1_2[17]\, \rdata_5_m_9[8]\, - \rdata_13_m_9[8]\, \un6_ex_add_res_s2_1[30]\, - \data_0_0[29]\, N485_i_0, N484, N479, \un1_iu0_6[27]\, - \data_0[27]\, N488, rd_0_i_0, \rd[0]\, \rd_0[0]\, N527, - N434, N437, \annul_current_3_sqmuxa_1\, un5_exbpmiss_i_0, - call_hold7_i, \un6_ex_add_res_s2[25]\, N778, - \un6_ex_add_res_s2_1[25]\, \un6_ex_add_res_s0[25]\, - N778_0, \dco_m_0[127]\, \tmp_m[22]\, \tmp[22]\, - \un6_ex_add_res_m_1[9]\, \un6_ex_add_res_s2_1[27]\, - \data_0[26]\, \un1_iu0_6[26]\, N476, \op2[26]\, N_74_i, - N782, N_15_i, N506, N467, N464, I33_un1_Y, \data_0[24]\, - \un1_iu0_6[24]\, N470, \op2[24]\, N566_i, I103_un1_Y_i, - N500, N506_0, N_74, N493, N497, N495_0, N811, - I248_un1_Y_i, N666, N473, \op2[25]\, - \un6_ex_add_res_s0[28]\, N772, \un6_ex_add_res_s2_1[28]\, - \un6_ex_add_res_s2[28]\, N772_0, I33_un1_Y_0, N484_0, - N488_0, \op2[30]\, \un6_ex_add_res_s2[15]\, N799, - \un6_ex_add_res_s2_1[15]\, \data_0[14]\, \un1_iu0_6[14]\, - I244_un1_Y, N658, \un6_ex_add_res_s0[22]\, N784, - \un6_ex_add_res_s2_1[22]\, \un6_ex_add_res_s2[22]\, - N784_0, \data_0[21]\, \un1_iu0_6[21]\, - \un6_ex_add_res_s0[9]\, N817, \un6_ex_add_res_s2_1[9]\, - \un6_ex_add_res_s2[9]\, N817_0, \data_0[8]\, - \un1_iu0_6[8]\, N418, N_62, N418_0, - ADD_33x33_fast_I250_Y_0_a3_0, \un6_ex_add_res_s2_1[11]\, - \data_0[10]\, \un1_iu0_6[10]\, N524, I65_un1_Y, N439, - N436, N440, \un6_ex_add_res_s0[24]\, N780, - \un6_ex_add_res_s2_1[24]\, \un6_ex_add_res_s2[24]\, - N780_0, \data_0[23]\, \un1_iu0_6[23]\, N413, \data_0[5]\, - \un1_iu0_6[5]\, I231_un1_Y_i, N645, N660, N413_0, - \dco_m_i[117]\, N_3455, miscout140, miscout140_1, - \un6_ex_add_res_s2[30]\, N768, \un6_ex_add_res_s2[27]\, - N774, \un6_ex_add_res_s2[11]\, N811_0, N_74_1, N464_0, - N467_0, \un6_ex_add_res_s0[30]\, N768_0, - \un6_ex_add_res_s0[27]\, N774_0, \un6_ex_add_res_s0[11]\, - \shiftin_17_m[15]\, \shiftin_17[15]\, \tmp_m[29]\, - \tmp[29]\, \shiftin_17_m[7]\, \shiftin_17[7]\, - \bpdata_m_2[0]\, aluresult_4_sqmuxa, \bpdata[0]\, - \bpdata_m_1[3]\, N_3957_1, \bpdata[3]\, \bpdata_m[19]\, - aluresult_6_sqmuxa, \bpdata[19]\, \tba_m[7]\, \tba[7]\, - \tmp_m[19]\, \tmp[19]\, \tmp_m[23]\, \tmp[23]\, N501, - N525, N437_0, N_72, N463, N817_i, N418_1, - ADD_33x33_fast_I250_Y_0_a3, N506_1, N466, N416, - \un1_iu0_6[6]\, \data_0[6]\, I248_un1_Y, N666_0, N541, - CO0, \cwp[0]\, \rstate_RNIRDFU5[1]\, rdata199, - \me_size_1[0]\, \me_size_1[1]\, \tmp_m[4]\, \tmp[4]\, - \ex_op1_i_m[26]\, \bpdata_i_m[2]\, N_3687, \bpdata[2]\, - \shiftin_17_m[21]\, \shiftin_17[21]\, \tmp_m[16]\, - \tmp[16]\, N505, \op2[13]\, \un1_iu0_6[13]\, \op2[14]\, - \op2[22]\, \un1_iu0_6[22]\, \op2[23]\, N527_0, N434_0, - I105_un1_Y, N502, I165_un1_Y, N569, N576, N503, N493_0, - \dco_m_i[108]\, rdata_2_sqmuxa, \data_0_m_i[4]\, - \data_0[4]\, \dco_m_0_i[120]\, \aluresult_m_i[29]\, - \aluresult[29]\, N401, \data_0[1]\, \un1_iu0_6[1]\, - N644_i, N578, I175_un1_Y, N416_0, I163_un1_Y, N567, N574, - N541_0, \op2[12]\, \un1_iu0_6[12]\, I45_un1_Y, \pc_m[8]\, - \wovf_exc_0_sqmuxa_1\, un7_op, \wovf_exc_0_sqmuxa\, - \wovf_exc_1_sqmuxa\, trap, un1_annul, trap_0, icc_check5, - N_145, ticc_exception_1, un6_xc_exception, - \xc_exception_1_0\, \tmp_m[25]\, \tmp[25]\, \tmp_m[8]\, - \tmp[8]\, N428, \inst_0_1[25]\, \dpc[25]\, N377, - \inst_0[6]\, \dpc[8]\, N376_i, N586_i, I160_un1_Y_i, N526, - \tmp_m[15]\, \tmp[15]\, N_6619, \tmp[14]\, \tmp_m[5]\, - \tmp[5]\, \tmp_m[28]\, \tmp[28]\, \tmp_m[10]\, \tmp[10]\, - \tmp_m[12]\, \tmp[12]\, \tmp_m[17]\, \tmp[17]\, - \un2_rstn_5\, \tmp_m[31]\, \tmp[31]\, \tmp_m[13]\, - \tmp[13]\, \tmp_m[20]\, \tmp[20]\, N_39, \tmp[6]\, - \tmp_m[30]\, \tmp[30]\, \tmp_m[26]\, \tmp[26]\, N_6620, - \tmp[11]\, \tmp_m[27]\, \tmp[27]\, N492, N374, - ADD_30x30_fast_I40_Y_0_a3, N424, \dpc[24]\, - \inst_0_0_0_RNI9O79[21]\, N431, \inst_0_1[26]\, \dpc[26]\, - N456, \tmp[2]\, \dpc[2]\, \inst_0_RNI0FUM[0]\, un8_op, - un25_op, \tmp_m[21]\, \tmp[21]\, \tmp_m[3]\, \tmp[3]\, - \un6_fe_npc_m[1]\, I_5, \op1_RNI3RNF[26]\, - \un17_casaen_0_0\, \op1[26]\, \tmp_m[2]\, \op1_i_m[17]\, - \op1[17]\, \bpdata_i_m[17]\, edata_2_sqmuxa, \bpdata[17]\, - \tmp_m[7]\, \tmp[7]\, N_142, wy_1_0_a3_1_0, N373, - \dpc[7]\, \inst_0[5]\, I74_un1_Y_i, N491, N776_1, - I265_un1_Y_i, ADD_33x33_fast_I265_Y_1, I265_un1_Y_i_0, - ADD_33x33_fast_I265_Y_1_0, \un6_ex_add_res_s1_i[26]\, - ADD_33x33_fast_I316_Y_0_0, I260_un1_Y_i, - ADD_33x33_fast_I260_Y_3, I260_un1_Y_i_0, - ADD_33x33_fast_I260_Y_3_0, I263_un1_Y, - ADD_33x33_fast_I263_Y_1, I229_un1_Y, - ADD_33x33_fast_I268_Y_0, ADD_33x33_fast_I260_un1_Y_0, - I269_un1_Y_i, ADD_33x33_fast_I269_Y_0, - aluresult_11_sqmuxa_5_0, \un6_ex_add_res_s1[10]\, - ADD_33x33_fast_I300_Y_0_0, \data_0_1[16]\, - \data_0_1_1_iv_1[16]\, \data_0_1[31]\, - \data_0_1_1_iv_1[31]\, N593, ADD_33x33_fast_I130_Y_0, - enaddr_1_sqmuxa_1, enaddr_1_sqmuxa_1_1, N712_i, - ADD_30x30_fast_I280_Y_0_0, I265_un1_Y_i_1, - ADD_33x33_fast_I265_Y_1_1, ADD_33x33_fast_I265_un1_Y_0, - \edata2_0_iv_0[2]\, N698, ADD_30x30_fast_I287_Y_0_0, N710, - ADD_30x30_fast_I281_Y_0_0, N718_i, - ADD_30x30_fast_I277_Y_0_0, N726_i, - ADD_30x30_fast_I274_Y_0_0, N501_0, - ADD_30x30_fast_I262_Y_0_0, \un6_ex_add_res_s1_i[30]\, - N768_1, ADD_33x33_fast_I320_Y_0_0, \d_1[29]\, - \d_1_iv_4[29]\, \data_0_1[19]\, \data_0_1_1_iv_1[19]\, - \un6_ex_add_res_s1[9]\, ADD_33x33_fast_I299_Y_0_0, - \un6_ex_add_res_s1_i[24]\, N780_1, - ADD_33x33_fast_I314_Y_0_0, I267_un1_Y, - ADD_33x33_fast_I267_Y_0, I267_un1_Y_0, - ADD_33x33_fast_I267_Y_0_0, N_57_i, - ADD_33x33_fast_I206_Y_0_a3_1_0, I263_un1_Y_0, - ADD_33x33_fast_I263_Y_1_0, I261_un1_Y, - ADD_33x33_fast_I261_Y_2, I264_un1_Y, - ADD_33x33_fast_I264_un1_Y_0, ADD_33x33_fast_I264_Y_1, - I261_un1_Y_0, ADD_33x33_fast_I261_Y_2_0, I261_un1_Y_1, - ADD_33x33_fast_I261_Y_2_1, I269_un1_Y, - ADD_33x33_fast_I269_Y_0_0, I264_un1_Y_0, - ADD_33x33_fast_I264_un1_Y_0_0, ADD_33x33_fast_I264_Y_1_0, - I267_un1_Y_1, ADD_33x33_fast_I267_Y_0_1, N706, - ADD_30x30_fast_I283_Y_0_0, N614, - ADD_30x30_fast_I265_Y_0_0, N556_i, - ADD_30x30_fast_I264_Y_0_0, N358, - ADD_30x30_fast_I261_Y_0_0, N729, - ADD_30x30_fast_I273_Y_0_0, N732_i, - ADD_30x30_fast_I272_Y_0_0, N558, - ADD_30x30_fast_I263_Y_0_0, N700, - ADD_30x30_fast_I286_Y_0_0, un1_icc_check5, - un1_icc_check5_2, ldchkra, ldchkra_0, N612, - ADD_30x30_fast_I266_Y_0_0, N_6528, SUM1_0_0, N694, - ADD_30x30_fast_I289_Y_0_0, N696, - ADD_30x30_fast_I288_Y_0_0, N702_i, - ADD_30x30_fast_I285_Y_0_0, N704, - ADD_30x30_fast_I284_Y_0_0, N714, - ADD_30x30_fast_I279_Y_0_0, N716, - ADD_30x30_fast_I278_Y_0_0, N723, - ADD_30x30_fast_I275_Y_0_0, N735, - ADD_30x30_fast_I271_Y_0_0, N738, - ADD_30x30_fast_I270_Y_0_0, N741, - ADD_30x30_fast_I269_Y_0_0, N608_i, - ADD_30x30_fast_I268_Y_0_0, I242_un1_Y, - ADD_30x30_fast_I242_un1_Y_0, \pc_1[3]\, \pc_1_iv_2[3]\, - \xc_trap_address_m[2]\, \xc_trap_address_m_0[2]\, - \xc_trap_address_m[3]\, \xc_trap_address_m_0[3]\, - \npc_iv_1[8]\, N398, alucin, bpdata6_1, bpdata6_0, wreg, - annul_0, \inst[19]\, \edata2_iv_0[26]\, et_RNI1BRF2, - \cwp_0[1]\, N431_0, N428_0, un1_icc_check5_1, imm9, - \edata2_0_iv_0[17]\, N651, N635, \un1_iu0_6[9]\, \op2[9]\, - N651_0, N635_0, N653, N637, G_6_1, G_6_0, - annul_current_2_sqmuxa_1, annul_1, - ADD_33x33_fast_I264_Y_0, N627, N643, \ex_op1_i_m[2]\, - \op1_i_m[2]\, \op2[8]\, ADD_33x33_fast_I263_Y_0, - ADD_30x30_fast_I242_Y_0, \aluresult_1_iv_8[6]\, - \aluresult_1_iv_7[6]\, \aluresult_1_iv_6[6]\, - \bpdata_m[6]\, ldlock2_1, ldlock2_0, wreg_0, ld_1, - \aluresult_1_iv_5[8]\, \aluresult_1_iv_3[8]\, \tt_m[4]\, - \aluresult_1_iv_1[8]\, \aluresult_1_iv_5[24]\, - \aluresult_1_iv_3[24]\, \aluresult_1_iv_1[24]\, - \tba_m[12]\, \aluresult_1_iv_8[20]\, - \aluresult_1_iv_7[20]\, \aluresult_1_iv_6[20]\, - \logicout_m_0[20]\, \aluresult_1_iv_8[14]\, - \aluresult_1_iv_7[14]\, \aluresult_1_iv_6[14]\, - \logicout_m_0[14]\, \aluresult_1_iv_5[19]\, - \aluresult_1_iv_4[19]\, \aluresult_1_iv_3[19]\, - \aluresult_1_iv_2[19]\, \data_0_1_0_iv_0[8]\, - \data_0_m_i[8]\, \data_0_1_1[16]\, \data_0_1_1_iv_0[31]\, - \data_0_1_1_iv_0[16]\, \data_0_1_1_iv_0[19]\, - rdata_2_sqmuxa_1, rdata_2_sqmuxa_0, \me_laddr_2[1]\, - \me_laddr_2[0]\, rdata_1_sqmuxa_1, rdata_1_sqmuxa_0, - enaddr_1_sqmuxa_1_0, \cnt[1]\, \op1_m_i[29]\, - \d_1_iv_3[29]\, \data_0_1_0_iv_0[13]\, \data_0_m[13]\, - \data_0_1_0_iv_0[15]\, \data_0_m[15]\, - \data_0_1_1_iv_2[5]\, \data_0_1_1_iv_1[5]\, - \data_0_1_1_iv_0[5]\, \dco_m_i[125]\, - \data_0_1_1_iv_0[4]\, \pc_1_iv_1[3]\, \pc_1_iv_1[4]\, - \pc_4_m[4]\, \xc_trap_address_m[4]\, - \un6_ex_add_res_m_1[5]\, \pc_1_iv_1[7]\, \pc_1_iv_0[7]\, - \pc_4[7]\, \xc_trap_address_m[7]\, \pc_1_iv_1[10]\, - \pc_1_iv_0[10]\, \pc_4[10]\, \xc_trap_address_m[10]\, - \pc_1_iv_2[5]\, \un6_ex_add_res_m_1[6]\, \pc_1_iv_0[5]\, - \pc_4[5]\, \xc_trap_address_m[5]\, \pc_1_iv_1[8]\, - \eaddress[8]\, \pc_1_iv_0[8]\, \pc_4[8]\, - \xc_trap_address_m[8]\, \pc_1_iv_2[2]\, - \un6_ex_add_res_m[3]\, \pc_1_iv_0[2]\, \pc_4_m[2]\, - \pc_1_iv_1[9]\, \pc_1_iv_0[9]\, \xc_trap_address_m[9]\, - \pc_4_m[9]\, \pc_4_m[3]\, \un6_ex_add_res_m_1[4]\, - \pc_1_iv_1[22]\, \pc_1_iv_0[22]\, \pc_4[22]\, - \xc_trap_address_m[22]\, \pc_1_iv_1[24]\, \pc_4_m[24]\, - \xc_trap_address_m[24]\, \un6_ex_add_res_m_1[25]\, - \pc_1_iv_1[23]\, \pc_1_iv_0[23]\, \pc_4[23]\, - \xc_trap_address_m[23]\, \pc_1_iv_1[19]\, \pc_1_iv_0[19]\, - \pc_4[19]\, \xc_trap_address_m[19]\, \pc_1_iv_1[16]\, - \eaddress[16]\, \pc_1_iv_0[16]\, \pc_4[16]\, - \xc_trap_address_m[16]\, \pc_1_iv_1[29]\, \pc_1_iv_0[29]\, - \pc_4[29]\, \xc_trap_address_m[29]\, \pc_1_iv_1[25]\, - \pc_1_iv_0[25]\, \pc_4[25]\, \xc_trap_address_m[25]\, - \pc_1_iv_1[28]\, \eaddress[28]\, \pc_1_iv_0[28]\, - \pc_4[28]\, \xc_trap_address_m[28]\, \pc_1_iv_1[21]\, - \pc_1_iv_0[21]\, \pc_4[21]\, \xc_trap_address_m[21]\, - m7_1, m7_0, \pc_4[14]\, \xc_trap_address_m[14]\, - \pc_1_iv_2[27]\, \un6_ex_add_res_m_1[28]\, - \pc_1_iv_0[27]\, \pc_4[27]\, \xc_trap_address_m[27]\, - m14_2, N_9, m14_0, N_31, \pc_4[11]\, - \xc_trap_address_m[11]\, \pc_1_iv_1[26]\, \pc_1_iv_0[26]\, - \pc_4[26]\, \xc_trap_address_m[26]\, \pc_1_iv_1[30]\, - \pc_4_m[30]\, \xc_trap_address_m[30]\, - \un6_ex_add_res_m_1[31]\, \pc_1_iv_1[18]\, - \pc_1_iv_0[18]\, \pc_4[18]\, \xc_trap_address_m[18]\, - \pc_1_iv_2[12]\, \un6_ex_add_res_m_1[13]\, - \pc_1_iv_0[12]\, \pc_4[12]\, \xc_trap_address_m[12]\, - \pc_1_iv_1[13]\, \eaddress[13]\, \pc_1_iv_0[13]\, - \pc_4[13]\, \xc_trap_address_m[13]\, \pc_1_iv_1[20]\, - annul_RNI5L7FE1, \pc_1_iv_0[20]\, \pc_4[20]\, - \xc_trap_address_m[20]\, \pc_1_iv_1[17]\, \pc_1_iv_0[17]\, - \pc_4[17]\, \xc_trap_address_m[17]\, \pc_1_iv_1[15]\, - \pc_1_iv_0[15]\, \pc_4[15]\, \xc_trap_address_m[15]\, - \pc_1_iv_1[31]\, \pc_1_iv_0[31]\, \de_hold_pc_1\, - \pc_4[31]\, \xc_trap_address_m[31]\, m21_2, - ldbp2_2_RNIFB78T1, m21_0, \pc_4[6]\, - \xc_trap_address_m[6]\, cnt_3_sqmuxa_0, ldlock, - hold_pc_2_sqmuxa, cnt_2_sqmuxa_0, hold_pc_0_sqmuxa_1, - pv_3, un6_rabpmiss_2, N_4240, pv_2, N_4241_i_0, pv_0, - N_4242, un23_exbpmiss_i_0, un9_rabpmiss, - un1_annul_next_1_sqmuxa_3_3, annul_next_1_sqmuxa_1_6, - un1_annul_next_1_sqmuxa_3_2, un1_annul_next_1_sqmuxa_3_0, - un25_exbpmiss, annul_next_2_sqmuxa_1_8, un13_exbpmiss_0, - annul_next_2_sqmuxa_1_6, annul_next_2_sqmuxa_1_5, - annul_next_2_sqmuxa_1_3, annul_next_2_sqmuxa_1_2, N_108, - un19_inst, annul_next_2_sqmuxa_1_0, \data_0_1_0_iv_0[9]\, - \data_0_m[9]\, \data_0_1_0_iv_0[14]\, \data_0_m[14]\, - \data_0_1_0_iv_0[11]\, \data_0_m[11]\, - \data_0_1_0_iv_0[12]\, \data_0_m[12]\, branch_0, - un6_rabpmiss_0, pv, \inst[29]\, \dco_m_i[109]\, - \data_0_1_1_iv_1[7]\, \dco_m_i[111]\, \data_0_m_i[7]\, - \dco_m_i[127]\, \data_0_1_1_iv_2[0]\, - \data_0_1_1_iv_0[0]\, \dco_m_i[120]\, \dco_m_i[112]\, - \data_0_m_i[0]\, \data_0_1_1_iv_2[1]\, - \data_0_1_1_iv_0[1]\, \dco_m_i[121]\, \dco_m_i[113]\, - \dco_m_i[105]\, \data_0_1_1_iv_1[2]\, rdata_0_sqmuxa, - \data_0_1_1_iv_0[2]\, \data_0[2]\, \dco_m_i[106]\, - \data_0_1_1_iv_2[3]\, \data_0_1_1_iv_0[3]\, - \dco_m_i[123]\, \dco_m_i[115]\, \data_0[3]\, - \dco_m_i[107]\, \data_0_1_1_iv_2[4]\, \dco_m_i[124]\, - \dco_m_i[116]\, \data_0_1_1_iv_1[6]\, \dco_m_i[110]\, - \data_0_m_i[6]\, \dco_m_i[126]\, \data_0_1_0_iv_1[8]\, - \rdata_13_m[8]\, \rdata_17_m[8]\, \data_0_1_0_iv_1[10]\, - \data_0_1_0_iv_0[10]\, \data_0_m_i[10]\, annul_2, - \data_0_0[31]\, \dco_m_1[127]\, \data_0[16]\, - \dco_m_0[112]\, \data_0_1_1_iv_1[17]\, \dco_m_0[113]\, - \data_0_m[17]\, \data_0[19]\, \dco_m_0[115]\, cin_iv_i_2, - alucin_RNO_2, N_350, cin_iv_i_0, \inst[30]\, \inst[31]\, - bp_1_0, not_valid, \data_0_1_1_iv_1[24]\, - \data_0_m_i[24]\, \dco_m_1_i[120]\, cin_iv_i_a5_0, - \inst[22]\, ctrl_annul_i_0_a2_0, inhibit_current, - annul_current_0, annul_current_4, \icc_12_iv_0[1]\, - \icc_7_m_2[1]\, \icc_7[1]\, \icc_2_m[1]\, pv_12_i_a6_0_2, - pv_12_i_a6_0_1, \cnt_0[1]\, annul_next_1_sqmuxa_1_4, - hold_pc_1_sqmuxa, annul_next_1_sqmuxa_1_1, - annul_next_1_sqmuxa_1_0, annul_next_1_sqmuxa_1_2, - \inst_0[28]\, \inst_0[29]\, \inst_0[25]\, \inst_0[27]\, - \inull\, \inst_0[26]\, me_nullify2_1_0, \d_iv_2[31]\, - \d_iv_1[31]\, \result_m_0[31]\, \cpi_m_0[383]\, - \result_m_0_0[31]\, \d_1_iv_3[31]\, \d_1_iv_1[31]\, - \d_1_iv_0[31]\, \rfo_m_i[63]\, \cpi_m_i[383]\, - \result[31]\, \imm_m_i[31]\, \icc_8_m_1[1]\, \inst[24]\, - un3_notag, \icc_7_m_0[1]\, \icc_8_m_5[1]\, - \rdata_9_m_0[8]\, me_signed_1, \d_1_iv_3[16]\, - \d_1_iv_1[16]\, \d_1_iv_0[16]\, \rfo_m_i[48]\, - \cpi_m_i[368]\, \result[16]\, \imm_m_i[16]\, \d_iv_2[16]\, - \d_iv_0[16]\, \result_m_0[16]\, \rfo_m[16]\, - \un1_p0_6[368]\, \result_m_0_0[16]\, \d_1_iv_3[28]\, - \d_1_iv_1[28]\, \d_1_iv_0[28]\, \rfo_m_i[60]\, - \cpi_m_i[380]\, \result[28]\, \imm_m_i[28]\, \d_iv_3[28]\, - \rfo_m[28]\, \d_iv_1[28]\, \op1_m_0[28]\, - \result_m_0[28]\, \cpi_m_0[380]\, \result_m_0_0[28]\, - \d_1_iv_3[15]\, \d_1_iv_1[15]\, \d_1_iv_0[15]\, - \rfo_m_i[47]\, \cpi_m_i[367]\, \result[15]\, - \imm_m_i[15]\, \d_iv_2[15]\, \d_iv_0[15]\, - \result_m_0[15]\, \rfo_m[15]\, \un1_p0_6[367]\, - \result_m_0_0[15]\, enaddr_2_sqmuxa_3, N_3749_3, - enaddr_2_sqmuxa_0, enaddr_2_sqmuxa_1, N_3749_2, N_3356_3, - \cnt[0]\, \aluresult_1_iv_8[31]\, \shiftin_17[32]\, - \aluresult_1_iv_7[31]\, \logicout[31]\, - \aluresult_1_iv_6[31]\, \bpdata_m_2[7]\, - \aluresult_1_iv_3[31]\, \aluresult_1_iv_4[31]\, - \aluop_RNIK0RF4[1]\, \aluresult_1_iv_0[31]\, - \bpdata_m_0[15]\, \tba[19]\, \aluresult_1_iv_1[31]\, - \pc[31]\, \aluresult_6[31]\, \y[31]\, \ex_op2_m[31]\, - \d_1_iv_4[23]\, \rfo_m_i[55]\, \d_1_iv_2[23]\, - \op1_m_i[23]\, \result_m_i[23]\, \imm_m_i[23]\, - \d_1_iv_1[23]\, \result_m_i_0[23]\, \cpi_m_i[375]\, - \d_iv_2[23]\, \d_iv_0[23]\, \result_m_0[23]\, \rfo_m[23]\, - \un1_p0_6[375]\, \result_m_0_0[23]\, \d_1_iv_3[8]\, - \d_1_iv_1[8]\, \d_1_iv_0[8]\, \rfo_m_i[40]\, - \cpi_m_i[360]\, \imm_m_i[8]\, \result_m_i[8]\, - \d_iv_2[8]\, \d_iv_0[8]\, \result_m_0[8]\, \rfo_m[8]\, - \un1_p0_6[360]\, \result_m_0_0[8]\, \dpc[30]\, - \inst_0_1[30]\, \d_1_iv_3[27]\, \d_1_iv_1[27]\, - \d_1_iv_0[27]\, \rfo_m_i[59]\, \cpi_m_i[379]\, - \result[27]\, \imm_m_i[27]\, \d_iv_2[27]\, \d_iv_0[27]\, - \result_m_0[27]\, \rfo_m[27]\, \un1_p0_6[379]\, - \result_m_0_0[27]\, \d_1_iv_3[24]\, \d_1_iv_1[24]\, - \d_1_iv_0[24]\, \rfo_m_i[56]\, \result_m_i[24]\, - \cpi_m_i[376]\, \result[24]\, \imm_m_i[24]\, \d_iv_3[24]\, - \rfo_m[24]\, \d_iv_1[24]\, \op1_m_0[24]\, - \result_m_0[24]\, \cpi_m_0[376]\, \result_m_0_0[24]\, - \d_1_iv_3[30]\, \d_1_iv_1[30]\, \d_1_iv_0[30]\, - \rfo_m_i[62]\, \cpi_m_i[382]\, \result[30]\, - \imm_m_i[30]\, \d_iv_2[30]\, \d_iv_0[30]\, - \result_m_0[30]\, \rfo_m[30]\, \un1_p0_6[382]\, - \result_m_0_0[30]\, \aluresult_1_iv_7[16]\, - \aluresult_1_iv_5[16]\, \logicout_m_0[16]\, - \shiftin_17_m[17]\, \aluresult_1_iv_3[16]\, - \aluresult_1_iv_2[16]\, \bpdata_m_1[0]\, \bpdata[16]\, - \tba_m[4]\, \ex_op2_m[16]\, aluresult_8_sqmuxa_i, - \aluresult_1_iv_1[16]\, \y[16]\, \cpi_m[161]\, - \d_1_iv_3[12]\, \d_1_iv_2[12]\, \result_m_i[12]\, - \imm_m_i[12]\, \d_1_iv_1[12]\, \result_m_i_0[12]\, - \cpi_m_i[364]\, \d_iv_2[12]\, \d_iv_0[12]\, - \result_m_0[12]\, \rfo_m[12]\, \un1_p0_6[364]\, - \result_m_0_0[12]\, \d_1_iv_1[29]\, \d_1_iv_0[29]\, - \rfo_m_i[61]\, \cpi_m_i[381]\, \result[29]\, - \imm_m_i[29]\, \d_iv_3[29]\, \rfo_m[29]\, \d_iv_1[29]\, - \op1_m_0[29]\, \result_m_0[29]\, \cpi_m_0[381]\, - \result_m_0_0[29]\, \d_iv_2[20]\, \d_iv_0[20]\, - \result_m_0[20]\, \rfo_m[20]\, \un1_p0_6[372]\, - \result_m_0_0[20]\, \d_1_iv_3[20]\, \d_1_iv_2[20]\, - \result_m_i[20]\, \imm_m_i[20]\, \d_1_iv_1[20]\, - \cpi_m_i[372]\, \aluresult_1_iv_9[28]\, - \shiftin_17_m[29]\, \aluresult_1_iv_7[28]\, - \shiftin_17_m_0[28]\, \logicout[28]\, - \aluresult_1_iv_6[28]\, \bpdata_m_2[4]\, - \aluresult_1_iv_3[28]\, \aluresult_1_iv_4[28]\, - \aluop_RNI2TEB4[1]\, \aluresult_1_iv_0[28]\, - \aluop_RNIPR2R4[2]\, \tba[16]\, \aluresult_1_iv_1[28]\, - \cpi_m[173]\, \y[28]\, \ex_op2_m[28]\, - ADD_30x30_fast_I233_Y_0_0, \dpc[29]\, - \inst_0_RNI8AJ4[27]\, N436_0, ldlock_2_0, - de_fins_hold_1_2, N_3832, un5_ldlock, \d_1_iv_3[7]\, - \d_1_iv_1[7]\, \d_1_iv_0[7]\, \rfo_m_i[39]\, - \cpi_m_i[359]\, \result[7]\, \imm_m_i[7]\, \d_iv_2[7]\, - \d_iv_0[7]\, \result_m_0[7]\, \rfo_m[7]\, \un1_p0_6[359]\, - \result_m_0_0[7]\, un1_addout_12_0, un12_ex_add_res, - \d_1_iv_3[26]\, \d_1_iv_1[26]\, \d_1_iv_0[26]\, - \rfo_m_i[58]\, \cpi_m_i[378]\, \imm_m_i[26]\, - \result_m_i[26]\, \d_iv_2[26]\, \d_iv_0[26]\, - \result_m_0[26]\, \rfo_m[26]\, \un1_p0_6[378]\, - \result_m_0_0[26]\, \d_1_iv_3[25]\, \d_1_iv_1[25]\, - \d_1_iv_0[25]\, \rfo_m_i[57]\, \cpi_m_i[377]\, - \result[25]\, \imm_m_i[25]\, \d_iv_2[25]\, \d_iv_0[25]\, - \result_m_0[25]\, \rfo_m[25]\, \un1_p0_6[377]\, - \result_m_0_0[25]\, \osel_i_a3_0[0]\, un1_rs1, N_3948, - rfe_2, rfe_0, wreg_1, ldcheck2, imm, - ADD_30x30_fast_I276_Y_0_0, \dpc[18]\, \inst_0[16]\, - \d_1_iv_3[11]\, \d_1_iv_1[11]\, \d_1_iv_0[11]\, - \rfo_m_i[43]\, \cpi_m_i[363]\, \result[11]\, - \imm_m_i[11]\, \d_iv_2[11]\, \d_iv_0[11]\, - \result_m_0[11]\, \rfo_m[11]\, \un1_p0_6[363]\, - \result_m_0_0[11]\, \aluresult_1_iv_7[15]\, - \shiftin_17[16]\, \aluresult_1_iv_6[15]\, \logicout[15]\, - \aluresult_1_iv_5[15]\, \aluresult_1_iv_2[15]\, - \tba_m[3]\, \aluresult_1_iv_4[15]\, \bpdata_m[15]\, - \cpi_m[160]\, \y_m_1[15]\, \aluresult_1_iv_0[15]\, - \un1_iu0_5[81]\, \d_1_iv_3[22]\, \d_1_iv_1[22]\, - \d_1_iv_0[22]\, \rfo_m_i[54]\, \cpi_m_i[374]\, - \result[22]\, \imm_m_i[22]\, \d_iv_2[22]\, \d_iv_0[22]\, - \result_m_0[22]\, \rfo_m[22]\, \un1_p0_6[374]\, - \result_m_0_0[22]\, \d_1_iv_4[21]\, \op1[21]\, - \d_1_iv_3[21]\, \d_1_iv_1[21]\, \d_1_iv_0[21]\, - \rfo_m_i[53]\, \cpi_m_i[373]\, \result[21]\, - \imm_m_i[21]\, \d_iv_3[21]\, \rfo_m[21]\, \d_iv_1[21]\, - \op1_m_0[21]\, \result_m_0[21]\, \cpi_m_0[373]\, - \result_m_0_0[21]\, tt_2_sqmuxa_1_0, un1_trap_1_sqmuxa, - annul_3, \d_1_iv_3[14]\, \d_1_iv_1[14]\, \d_1_iv_0[14]\, - \rfo_m_i[46]\, \cpi_m_i[366]\, \result[14]\, - \imm_m_i[14]\, \d_iv_2[14]\, \d_iv_0[14]\, - \result_m_0[14]\, \rfo_m[14]\, \un1_p0_6[366]\, - \result_m_0_0[14]\, \aluresult_1_iv_9[23]\, - \shiftin_17[23]\, \aluresult_1_iv_8[23]\, - \aluresult_1_iv_6[23]\, \aluop_RNII15D6[0]\, - \shiftin_17_m[24]\, \aluresult_1_iv_4[23]\, - \aluresult_1_iv_3[23]\, \bpdata_m_1[7]\, \tba[11]\, - \aluresult_1_iv_2[23]\, \bpdata[23]\, - \aluresult_1_iv_1[23]\, \aluresult_1_iv_0[23]\, - \icc_m[3]\, \y[23]\, \cpi_m[168]\, \un1_iu0_5[89]\, - \d_1_iv_3[19]\, \d_1_iv_1[19]\, \d_1_iv_0[19]\, - \rfo_m_i[51]\, \cpi_m_i[371]\, \result[19]\, - \imm_m_i[19]\, \d_iv_2[19]\, \d_iv_0[19]\, - \result_m_0[19]\, \rfo_m[19]\, \un1_p0_6[371]\, - \result_m_0_0[19]\, \aluresult_1_iv_9[8]\, - \shiftin_17_m[9]\, \aluresult_1_iv_7[8]\, - \shiftin_17_m_0[8]\, \aluresult_1_iv_4[8]\, - \logicout_m_0[8]\, \pil_m[0]\, \aluresult_1_iv_0[8]\, - \bpdata_m[8]\, \y[8]\, \cpi_m[153]\, \un1_iu0_5[74]\, - \d_1_iv_3[17]\, \d_1_iv_1[17]\, \d_1_iv_0[17]\, - \rfo_m_i[49]\, d27, \cpi_m_i[369]\, \result[17]\, - \imm_m_i[17]\, \d_iv_2[17]\, \d_iv_0[17]\, - \result_m_0[17]\, \rfo_m[17]\, \un1_p0_6[369]\, - \result_m_0_0[17]\, \d_iv_2[18]\, \d_iv_0[18]\, - \result_m_0[18]\, \rfo_m[18]\, \un1_p0_6[370]\, d14, - \result_m_0_0[18]\, \d_1_iv_3[18]\, \d_1_iv_1[18]\, - \d_1_iv_0[18]\, \rfo_m_i[50]\, \cpi_m_i[370]\, - \result[18]\, d31, \imm_m_i[18]\, \dpc[31]\, - \inst_0_1[31]\, \d_1_iv_4[4]\, \op1[4]\, \d_1_iv_3[4]\, - \d_1_iv_2[4]\, \result_m_i[4]\, \imm_m_i[4]\, - \d_1_iv_1[4]\, \cpi_m_i[356]\, \d_iv_3[4]\, \rfo_m[4]\, - \d_iv_1[4]\, \op1_m_0[4]\, \result_m_0[4]\, - \cpi_m_0[356]\, \result_m_0_0[4]\, \d_1_iv_4[13]\, - \op1[13]\, \d_1_iv_3[13]\, \d_1_iv_2[13]\, \cpi_m_i[365]\, - \result_m_i[13]\, \d_1_iv_0[13]\, \result[13]\, - \imm_m_i[13]\, \d_iv_2[13]\, \d_iv_0[13]\, - \result_m_0[13]\, \rfo_m[13]\, \un1_p0_6[365]\, - \result_m_0_0[13]\, \aluresult_0_iv_9[27]\, - \shiftin_17[27]\, \aluresult_0_iv_8[27]\, - \aluresult_0_iv_6[27]\, \logicout_m_0[27]\, - \shiftin_17_m[28]\, \aluop_RNIEPDN4[2]\, - \aluresult_0_iv_2[27]\, \aluresult_0_iv_5[27]\, - \tba_m[15]\, \aluop_RNI5N3F4[1]\, \bpdata_m_2[3]\, - \ex_op2_m[27]\, \aluresult_0_iv_1[27]\, \pc[27]\, - \y_m_1[27]\, \aluresult_1_iv_8[24]\, - \aluresult_1_iv_6[24]\, \shiftin_17_m[25]\, N_198, - \aluresult_1_iv_4[24]\, \bpdata[8]\, aluresult_5_sqmuxa, - \aluresult_1_iv_2[24]\, \aluresult_1_iv_0[24]\, - \aluop_RNIN0RF4[1]\, \cpi_m[169]\, \y[24]\, - \ex_op2_m[24]\, \aluresult_1_iv_8[30]\, \shiftin_17[31]\, - \aluresult_1_iv_7[30]\, \aluresult_1_iv_5[30]\, - \aluresult_1_iv_4[30]\, \logicout_m_0[30]\, - \aluresult_1_iv_1[30]\, \tba_m[18]\, \bpdata_m_2[6]\, - \aluop_RNIC8EB4[1]\, \aluresult_1_iv_0[30]\, - \aluop_RNI143R4[2]\, \cpi_m[175]\, \y[30]\, - \ex_op2_m[30]\, \dpc[22]\, \inst_0[20]\, \dpc[14]\, - \aluresult_1_iv_7[12]\, \shiftin_17[13]\, - \aluresult_1_iv_6[12]\, \aluresult_1_iv_4[12]\, - \aluresult_1_iv_3[12]\, \logicout_m_0[12]\, N_3974, - \bpdata[12]\, \aluresult_1_iv_1[12]\, - \aluresult_1_iv_0[12]\, \tba_m[0]\, \y[12]\, \cpi_m[157]\, - \un1_iu0_5[78]\, \dpc[28]\, \inst_0_1[28]\, \d_iv_2[10]\, - \d_iv_0[10]\, \result_m_0[10]\, \rfo_m[10]\, - \un1_p0_6[362]\, \result_m_0_0[10]\, \d_1_iv_4[10]\, - \rfo_m_i[42]\, \d_1_iv_2[10]\, \op1_m_i[10]\, - \result_m_i[10]\, \imm_m_i[10]\, \d_1_iv_1[10]\, - \cpi_m_i[362]\, \aluresult_1_iv_8[29]\, - \aluresult_1_iv_6[29]\, \logicout_m_0[29]\, - \shiftin_17_m[30]\, \bpdata_m_2[5]\, - \aluresult_1_iv_3[29]\, \aluresult_1_iv_4[29]\, - \bpdata[13]\, \aluresult_1_iv_2[29]\, \tba[17]\, - \aluresult_1_iv_1[29]\, \bpdata[29]\, - \aluresult_1_iv_0[29]\, \cpi_m[174]\, \y[29]\, - \ex_op2_m[29]\, \d_1_iv_4[9]\, \rfo_m_i[41]\, - \d_1_iv_2[9]\, \op1_m_i[9]\, \result_m_i[9]\, - \imm_m_i[9]\, \d_1_iv_1[9]\, \result_m_i_0[9]\, - \cpi_m_i[361]\, \d_iv_2[9]\, \d_iv_1[9]\, \d_iv_0[9]\, - \cpi_m_0[361]\, \result_m_0[9]\, \dpc[17]\, \inst_0[15]\, - \aluresult_1_iv_4[20]\, \aluresult_1_iv_3[20]\, - \bpdata_m_1[4]\, \icc_m[0]\, \aluresult_1_iv_0[20]\, - \tba_m[8]\, \cpi_m[165]\, \y_m_1[20]\, \bpdata_m[20]\, - \un1_iu0_5[86]\, \dpc[27]\, \inst_0_1[27]\, - ADD_30x30_fast_I234_Y_1, N518, N511, - ADD_30x30_fast_I234_Y_0, N455, N452, N451, - ADD_30x30_fast_I232_Y_2, I86_un1_Y, - ADD_30x30_fast_I232_Y_0, I140_un1_Y_i, - ADD_30x30_fast_I30_un1_Y, \dpc[10]\, \inst_0[8]\, - ADD_30x30_fast_I282_Y_0_0, un6_annul_4, un3_irl, - un6_annul_2, annul_RNIPFOQ, irqen, irqen2, un6_annul_1, - et, pv_1, wreg_1_6, un1_de_ren1_4_i_0, wreg_1_4, - un1_de_ren1_5_i_0, wreg_1_2, wreg_1_1, \rd_RNIQP6H1[7]\, - \rd[3]\, \inst_0_RNI3RUM[3]\, wreg_1_0, \rd[1]\, - \inst_0_RNI1JUM[1]\, un1_de_ren1_2_0_i_0, wreg_2, - \dpc[16]\, \inst_0[14]\, \d_1_iv_3[6]\, \d_1_iv_1[6]\, - \d_1_iv_0[6]\, \rfo_m_i[38]\, \cpi_m_i[358]\, \result[6]\, - \imm_m_i[6]\, \d_iv_2[6]\, \d_iv_0[6]\, \result_m_0[6]\, - \rfo_m[6]\, \un1_p0_6[358]\, \result_m_0_0[6]\, irqen_1, - trap27, trap63, \aluresult_1_iv_8[7]\, \shiftin_17[8]\, - \aluresult_1_iv_7[7]\, \bpdata[7]\, N_3957, - \aluresult_1_iv_6[7]\, \aluresult_1_iv_4[7]\, - \aluresult_1_iv_3[7]\, \logicout_m_0[7]\, - \aluresult_1_iv_2[7]\, esu, aluresult_11_sqmuxa, - \aluresult_1_iv_1[7]\, \y[7]\, \cpi_m[152]\, - \un1_iu0_5[73]\, \aluresult_1_iv_0[7]\, \wim_m[7]\, - \aluresult_1_iv_9[26]\, \shiftin_17_m[27]\, - \aluresult_1_iv_7[26]\, \shiftin_17_m_0[26]\, - \aluresult_1_iv_5[26]\, \aluresult_1_iv_4[26]\, - \logicout_m_0[26]\, \aluresult_1_iv_3[26]\, - \bpdata_m_2[2]\, \bpdata[10]\, \aluresult_1_iv_2[26]\, - \tba[14]\, \aluresult_1_iv_1[26]\, \bpdata[26]\, - \aluresult_1_iv_0[26]\, \pc[26]\, \aluresult_4[1]\, - \un1_iu0_5[92]\, \y_m_1[26]\, ADD_30x30_fast_I235_Y_2, - N588, N573, ADD_30x30_fast_I235_Y_1, N520, N513, - ADD_30x30_fast_I235_Y_0, I36_un1_Y_i, I92_un1_Y, N433, - \aluresult_1_iv_9[25]\, \shiftin_17_m[26]\, - \aluresult_1_iv_7[25]\, \shiftin_17_m_0[25]\, - \aluresult_1_iv_5[25]\, \aluresult_1_iv_4[25]\, - \logicout_m_0[25]\, \aluresult_1_iv_3[25]\, - \bpdata_m_2[1]\, \aluresult_1_iv_2[25]\, \bpdata_m_0[9]\, - \tba[13]\, \aluresult_1_iv_1[25]\, \y_m_1[25]\, - \ex_op2_m[25]\, \aluop_RNIQ4RF4[1]\, \pc[25]\, - \d_1_iv_3[3]\, \d_1_iv_1[3]\, \d_1_iv_0[3]\, - \rfo_m_i[35]\, \result_m_i[3]\, \cpi_m_i[355]\, - \result[3]\, \imm_m_i[3]\, \d_iv_2[3]\, \d_iv_0[3]\, - \result_m_0[3]\, \rfo_m[3]\, \un1_p0_6[355]\, - \result_m_0_0[3]\, ADD_30x30_fast_I238_Y_0, N519, - \d_1_iv_3[5]\, \d_1_iv_1[5]\, \d_1_iv_0[5]\, - \rfo_m_i[37]\, \cpi_m_i[357]\, \result[5]\, \imm_m_i[5]\, - \d_iv_0_2[5]\, \d_iv_0_0[5]\, N_406, - \rsel1_0_RNITC8M2[2]\, \un1_p0_6[357]\, N_403, \dpc[20]\, - \inst_0[18]\, \aluresult_1_iv_8[11]\, \shiftin_17[12]\, - \aluresult_1_iv_7[11]\, \logicout[11]\, - \aluresult_1_iv_6[11]\, \aluresult_1_iv_3[11]\, - \aluresult_1_iv_4[11]\, \bpdata[11]\, - \aluresult_1_iv_2[11]\, \cpi_m[156]\, \y_m_1[11]\, - \tt_m[7]\, \pil[3]\, \aluresult_1_iv_0[11]\, - \un1_iu0_5[77]\, ADD_30x30_fast_I236_Y_1, N590, N575, - ADD_30x30_fast_I236_Y_0, N522, N515, N514, \dpc[19]\, - \inst_0[17]\, \dpc[21]\, \inst_0[19]\, wreg_5, wreg_3, - \rd_RNI2Q6H1[7]\, un1_de_ren1_1_4_i_0, wreg_0_0, - un1_de_ren1_1_3_i_0, wreg_1_7, un1_de_ren1_1_1_i_0, - un1_de_ren1_1_2_i_0, \rd_1[0]\, wreg_4, un1_de_ren1_NE_5, - un1_de_ren1_4_i, un1_de_ren1_NE_3, un1_de_ren1_5_i, - un1_de_ren1_NE_1, un1_de_ren1_NE_0, \rd_RNIMP6H1[7]\, - \rd[2]\, \inst_0_RNI2NUM[2]\, un1_de_ren1_3_i, \rd_2[0]\, - un1_de_ren1_1_i, \aluresult_1_iv_8[22]\, - \aluresult_1_iv_7[22]\, \logicout[22]\, - \aluresult_1_iv_6[22]\, \aluresult_1_iv_4[22]\, - \aluresult_1_iv_3[22]\, \bpdata_m_1[6]\, \tba[10]\, - \aluresult_1_iv_2[22]\, \bpdata[22]\, - \aluresult_1_iv_1[22]\, \aluresult_1_iv_0[22]\, - \icc_m[2]\, \y[22]\, \cpi_m[167]\, \un1_iu0_5[88]\, - \aluresult_1_iv_8[21]\, \shiftin_17[22]\, - \aluresult_1_iv_7[21]\, \aluresult_1_iv_5[21]\, - \bpdata_m_1[5]\, \logicout_m_0[21]\, - \aluresult_1_iv_2[21]\, \tba_m[9]\, - \aluresult_1_iv_3[21]\, \cpi_m[166]\, \y_m_1[21]\, - \bpdata_m[21]\, \ex_op2_m[21]\, \icc_m[1]\, - ADD_30x30_fast_I239_Y_1, I154_un1_Y, I204_un1_Y, - \dpc[23]\, \dpc[15]\, \inst_0[13]\, \dpc[13]\, - \inst_0[11]\, \aluresult_1_iv_3[14]\, \tba_m[2]\, - \aluresult_1_iv_5[14]\, \bpdata[14]\, - \aluresult_1_iv_1[14]\, \aluresult_1_iv_2[14]\, - \y_m_1[14]\, \cpi_m[159]\, \aluresult_1_iv_0[14]\, - \ex_op2_m[14]\, dwt, aluresult_9_sqmuxa, - \aluresult_1_iv_7[19]\, \shiftin_17[20]\, - \aluresult_1_iv_6[19]\, \logicout[19]\, \ex_op2_m[19]\, - \aluresult_1_iv_1[19]\, \pc[19]\, \y_m_1[19]\, - \aluresult_1_iv_8[17]\, \shiftin_17_m[18]\, - \aluresult_1_iv_6[17]\, \shiftin_17_m_0[17]\, - \aluresult_1_iv_4[17]\, \bpdata_m_1[1]\, - \logicout_m_0[17]\, \aluresult_1_iv_1[17]\, - \aluresult_1_iv_0[17]\, \aluresult_1_iv_3[17]\, - \tba_m[5]\, \y[17]\, \cpi_m[162]\, \un1_iu0_5[83]\, - ADD_30x30_fast_I267_Y_0_0, \dpc[9]\, \inst_0[7]\, - \aluresult_1_iv_7[18]\, \shiftin_17[19]\, - \aluresult_1_iv_6[18]\, \logicout[18]\, - \aluresult_1_iv_5[18]\, \bpdata_m_1[2]\, - \aluresult_1_iv_4[18]\, \aluresult_1_iv_1[18]\, - \aluresult_1_iv_0[18]\, \aluresult_1_iv_3[18]\, - \bpdata[18]\, \tba_m[6]\, \y_m_1[18]\, \cpi_m[163]\, - \un1_iu0_5[84]\, \dpc[12]\, \inst_0[10]\, - \aluresult_1_iv_7[4]\, \shiftin_17[5]\, - \aluresult_1_iv_6[4]\, \bpdata[4]\, \aluresult_1_iv_5[4]\, - \logicout[4]\, \aluresult_1_iv_4[4]\, - \aluresult_1_iv_3[4]\, \aluresult_1_iv_0[4]\, - \ex_op2_m[4]\, \aluresult_1_iv_2[4]\, \pc[4]\, \y_m_1[4]\, - \wim[4]\, aluresult_13_sqmuxa, - ADD_30x30_fast_I235_un1_Y_0, N589, \dpc[11]\, \inst_0[9]\, - ADD_30x30_fast_I236_un1_Y_0, N591, \aluresult_1_iv_7[13]\, - \shiftin_17[14]\, \aluresult_1_iv_6[13]\, \logicout[13]\, - \aluresult_1_iv_5[13]\, \aluresult_1_iv_2[13]\, - \tba_m[1]\, \aluresult_1_iv_4[13]\, \ex_op2_m[13]\, - \aluresult_1_iv_1[13]\, \y[13]\, \cpi_m[158]\, - \d_1_iv_3[2]\, \d_1_iv_1[2]\, \d_1_iv_0[2]\, - \rfo_m_i[34]\, \cpi_m_i[354]\, \result[2]\, \imm_m_i[2]\, - \d_iv_2[2]\, \d_iv_0[2]\, \result_m_0[2]\, \rfo_m[2]\, - \un1_p0_6[354]\, \result_m_0_0[2]\, - ADD_33x33_fast_I322_Y_0_0, \op2[31]\, \un1_iu0_6[31]\, - \aluresult_1_iv_8[10]\, \shiftin_17[11]\, - \aluresult_1_iv_7[10]\, \logicout[10]\, - \aluresult_1_iv_6[10]\, \aluresult_1_iv_3[10]\, - \aluresult_1_iv_4[10]\, \aluresult_1_iv_2[10]\, - \cpi_m[155]\, \y_m_1[10]\, \tt_m[6]\, \pil[2]\, - \aluresult_1_iv_0[10]\, \un1_iu0_5[76]\, - \aluresult_1_iv_8[9]\, \aluresult_1_iv_6[9]\, - \logicout_m_0[9]\, \shiftin_17_m[10]\, - \aluresult_1_iv_4[9]\, \aluresult_1_iv_5[9]\, \tt_m[5]\, - \aluresult_1_iv_1[9]\, \pil_m[1]\, \aluresult_1_iv_0[9]\, - \bpdata_m[9]\, \pc[9]\, \y_m_1[9]\, \un1_iu0_5[75]\, - \dpc[6]\, \inst_0_RNI4VUM[4]\, ADD_33x33_fast_I259_Y_3, - I155_un1_Y, ADD_33x33_fast_I259_Y_1, I211_un1_Y, - I33_un1_Y_1, N487, I95_un1_Y, ADD_33x33_fast_I259_Y_3_0, - I155_un1_Y_0, ADD_33x33_fast_I259_Y_1_0, I211_un1_Y_0, - N487_0, I95_un1_Y_0, ADD_33x33_fast_I319_Y_0_0, \op2[28]\, - \aluresult_1_iv_5[6]\, \logicout_m_0[6]\, - \aluresult_1_iv_1[6]\, ps_m_0, \aluresult_1_iv_4[6]\, - \aluresult_1_iv_2[6]\, \pc[6]\, \y_m_1[6]\, - \un1_iu0_5[72]\, \aluresult_1_iv_0[6]\, \wim_m[6]\, - iflush_1_0, \inst_0[24]\, \inst[21]\, trap_0_sqmuxa_1_1_i, - ADD_33x33_fast_I259_Y_3_1, N625, N640, - ADD_33x33_fast_I259_Y_2, I95_un1_Y_1, - ADD_33x33_fast_I259_Y_0, I155_un1_Y_1, \d_1_iv_4[1]\, - \op1[1]\, \d_1_iv_3[1]\, \d_1_iv_1[1]\, \d_1_iv_0[1]\, - \rfo_m_i[33]\, \result_m_i[1]\, \cpi_m_i[353]\, - \result[1]\, \imm_m_i[1]\, \d_iv_2[1]\, \d_iv_0[1]\, - \result_m_0[1]\, \rfo_m[1]\, \un1_p0_6[353]\, - \result_m_0_0[1]\, \aluresult_1_iv_7[3]\, - \shiftin_17_m_0[3]\, \aluresult_1_iv_6[3]\, - \aluresult_1_iv_5[3]\, \shiftin_17_m[4]\, \bpdata_m[3]\, - \aluresult_1_iv_4[3]\, \aluresult_1_iv_3[3]\, - \logicout_m_0[3]\, \cpi_m[148]\, \y_m_1[3]\, - \aluresult_1_iv_1[3]\, \un1_iu0_5[69]\, - \aluresult_1_iv_0[3]\, \wim_m[3]\, \d_iv_2[0]\, - \d_iv_0[0]\, \result_m_0[0]\, \rfo_m[0]\, \un1_p0_6[352]\, - \result_m_0_0[0]\, \d_1_iv_4[0]\, \rfo_m_i[32]\, - \d_1_iv_2[0]\, \op1_m_i[0]\, \result_m_i[0]\, - \imm_m_i[0]\, \d_1_iv_1[0]\, \cpi_m_i[352]\, - \aluresult_1_iv_9[5]\, \shiftin_17_m[6]\, - \aluresult_1_iv_7[5]\, \shiftin_17_m_0[5]\, \bpdata[5]\, - \aluresult_1_iv_6[5]\, \aluresult_1_iv_4[5]\, - \aluresult_1_iv_3[5]\, \logicout_m_0[5]\, - \aluresult_1_iv_2[5]\, et_0, \aluresult_1_iv_1[5]\, - \pc[5]\, \y_m_1[5]\, \un1_iu0_5[71]\, - \aluresult_1_iv_0[5]\, \wim_m[5]\, - ADD_33x33_fast_I262_Y_0_0, N_52, N478, - ADD_33x33_fast_I39_Y_0_a3, ADD_33x33_fast_I262_Y_0_0_0, - N502_0, N_50_0, N498_i, N551, N587, N543, \dpc[4]\, - \dpc[5]\, me_nullify2_1_2_1, un5_trap, trap_0_sqmuxa_7, - me_nullify2_1_2_0, nullify_0_sqmuxa_0, - ADD_33x33_fast_I262_Y_0_0_1, N502_1, N_50_1, N498, - \aluresult_2_iv_7[2]\, \shiftin_17[3]\, - aluresult_1_sqmuxa, \aluresult_2_iv_6[2]\, - \aluresult_2_iv_5[2]\, \aluresult_2_iv_3[2]\, - \aluresult_2_iv_2[2]\, \logicout_m_0[2]\, \cpi_m[147]\, - \y_m_1[2]\, \cwp_m[2]\, \ex_op2_m[2]\, \wim_m[2]\, - ADD_30x30_fast_I244_un1_Y_0, ADD_33x33_fast_I262_Y_0_a3_0, - N503_0, ADD_33x33_fast_I321_Y_0_0, \tt_0[1]\, \tt_0[2]\, - N_4036, ADD_33x33_fast_I318_Y_0_0, \op2[27]\, I227_un1_Y, - N640_0, N656, N641, N640_1, - ADD_33x33_fast_I262_Y_0_a3_0_0, N503_1, - ADD_30x30_fast_I132_Y_0, N370, ADD_33x33_fast_I303_Y_0_0, - ADD_33x33_fast_I311_Y_0_0, \op2[20]\, \un1_iu0_6[20]\, - N_454, \inst_RNIJ02L[19]\, \aop2_i_o2_0[0]\, N_219, - \tt_9_0_a3_0_1[5]\, ticc, trap_1, \tt_4[3]\, trap_4_1_0, - N656_0, N641_0, N648, N633, N648_0, N633_0, - ADD_33x33_fast_I263_Y_0_0, N574_0, N567_0, N566, N642, - N627_0, ADD_33x33_fast_I260_Y_2, N568_0, N561, - ADD_33x33_fast_I260_Y_1, ADD_33x33_fast_I260_Y_0, - ADD_33x33_fast_I97_un1_Y, N481, \aluresult_2_iv_7[1]\, - \shiftin_17[2]\, \shiftin_17_m_0[1]\, - \aluresult_2_iv_6[1]\, \eaddress[1]\, - \aluresult_2_iv_5[1]\, \logicout_m_0[1]\, - \aluresult_2_iv_3[1]\, \bpdata_m[1]\, \cwp_m[1]\, - \aluresult_2_iv_0[1]\, \aluresult_2_iv_1[1]\, \y[1]\, - \wim_m[1]\, \ex_op2_m[1]\, ADD_33x33_fast_I260_Y_3_1, - N642_0, N627_1, ADD_33x33_fast_I260_Y_2_0, I97_un1_Y, - ADD_33x33_fast_I260_Y_0_0, N481_0, \aluresult_2_iv_7[0]\, - \shiftin_17[0]\, \aluresult_2_iv_6[0]\, \logicout_m_0[0]\, - \aluresult_2_iv_4[0]\, \bpdata_m[0]\, - \aluresult_2_iv_1[0]\, \cwp_m[0]\, \aluresult_2_iv_2[0]\, - \aluresult_2_iv_0[0]\, \op2_RNI59C6[0]\, - aluresult_7_sqmuxa, \y_m_0[0]\, \wim[0]\, - \un6_ex_add_res_m[1]\, tba_610_e_5, tba_610_e_3, - tba_610_e_2, annul_1_0, \inst_1[19]\, y15, \inst_0[22]\, - \inst[23]\, \inst[20]\, \inst_0[21]\, I157_un1_Y_i_0, - ADD_33x33_fast_I260_Y_1_0, I213_un1_Y_i, - ADD_33x33_fast_I260_Y_0_1, N481_1, - ADD_33x33_fast_I317_Y_0_0, ldbp2_0_a5_0, N629, N644, - ADD_33x33_fast_I261_Y_1, I99_un1_Y, I159_un1_Y, N496, - I159_un1_Y_0, ADD_33x33_fast_I261_Y_0, I215_un1_Y, N497_0, - N496_0, ADD_33x33_fast_I263_Y_1_1, I163_un1_Y_i, - I219_un1_Y_i, N566_0, I159_un1_Y_1, - ADD_33x33_fast_I261_Y_0_0, I215_un1_Y_0, N500_0, N496_1, - ADD_33x33_fast_I312_Y_0_0, \op2[21]\, icc_0_sqmuxa_1_29, - icc_0_sqmuxa_1_18, icc_0_sqmuxa_1_17, icc_0_sqmuxa_1_26, - icc_0_sqmuxa_1_28, icc_0_sqmuxa_1_14, icc_0_sqmuxa_1_13, - icc_0_sqmuxa_1_24, icc_0_sqmuxa_1_27, icc_0_sqmuxa_1_10, - icc_0_sqmuxa_1_9, icc_0_sqmuxa_1_22, icc_0_sqmuxa_1_8, - icc_0_sqmuxa_1_7, icc_0_sqmuxa_1_19, icc_0_sqmuxa_1_16, - \logicout[21]\, icc_0_sqmuxa_1_0, icc_0_sqmuxa_1_12, - \logicout[30]\, icc_0_sqmuxa_1_5, \logicout[16]\, - icc_0_sqmuxa_1_3, \logicout[12]\, icc_0_sqmuxa_1_2, - \logicout[6]\, \logicout[5]\, \logicout[23]\, - \logicout[1]\, \logicout[20]\, \logicout[0]\, - \logicout[2]\, \logicout[3]\, \logicout[29]\, - \logicout[26]\, \logicout[27]\, \logicout[25]\, - \logicout[17]\, \logicout[14]\, \logicout[9]\, - \logicout[7]\, \logicout[8]\, ADD_33x33_fast_I310_Y_0_0, - \op2[19]\, \op1_RNID1VH[19]\, ADD_33x33_fast_I308_Y_0_0, - \op2[17]\, \un1_iu0_6[17]\, I165_un1_Y_0, I221_un1_Y, - N568_1, ADD_33x33_fast_I264_Y_1_1, N650, N635_1, - \tt_3[3]\, \tt_1[3]\, cp_disabled_4, fp_disabled_4, - \dpc[3]\, N650_0, ADD_33x33_fast_I264_Y_0_0, N576_0, - N569_0, N652, N637_0, ADD_33x33_fast_I265_Y_0, N578_0, - N571, N570, N652_0, ADD_33x33_fast_I265_Y_0_0, N578_1, - N571_0, N570_0, I167_un1_Y_i, I223_un1_Y_i, N570_1, - \edata2_0_iv_0[0]\, \op1[0]\, \ex_op1_i_m[0]\, - \edata2_0_iv_0[7]\, \op1[7]\, \ex_op1_i_m[7]\, - \edata2_0_iv_0[5]\, \op1[5]\, \ex_op1_i_m[5]\, - \edata2_0_iv_0[3]\, \op1[3]\, \ex_op1_i_m[3]\, - \edata2_0_iv_0[4]\, \un1_iu0_6[4]\, \op1_i_m[4]\, - ADD_33x33_fast_I261_un1_Y_0, N629_0, un1_rs1_2, un1_rs1_0, - un1_rs1_1, ADD_33x33_fast_I268_Y_0_0, N658_0, N643_0, - ADD_33x33_fast_I268_Y_0_1, N658_1, N643_1, - ADD_33x33_fast_I261_un1_Y_0_0, N629_1, N645_0, - de_inull_0_2004_0, rett_1, de_inull_0_a3_1_0, jmpl_1, - ADD_33x33_fast_I269_Y_0_1, N660_0, N645_1, branch_1_m7_3, - branch_1_m7_1, N660_1, N644_0, ADD_33x33_fast_I271_Y_0, - N664, N649, ADD_33x33_fast_I271_Y_0_0, I235_un1_Y_i, - I179_un1_Y, N582, SUM2_0_0, \cwp[2]\, tt_9_0_1862_0, - N_16684_tz_tz, trap_4_1, ADD_33x33_fast_I271_Y_0_1, - N664_0, N649_0, ADD_33x33_fast_I268_un1_Y_0, N674, N642_1, - ADD_33x33_fast_I273_Y_0, ADD_33x33_fast_I273_un1_Y_0, - N653_0, N652_1, ADD_33x33_fast_I273_Y_0_0, - ADD_33x33_fast_I273_un1_Y_0_0, d_m5_0_a3_0, \y_iv_2[31]\, - \y_m[31]\, \y_m_0[31]\, \y_iv_0[31]\, ex_ymsb_1_m, - ADD_33x33_fast_I265_un1_Y_0_0, N653_1, - ADD_33x33_fast_I265_un1_Y_0_1, N637_1, - ADD_33x33_fast_I273_Y_0_1, ADD_33x33_fast_I273_un1_Y_0_1, - un9_rabpmiss_1, un9_rabpmiss_0, \y_iv_1[22]\, \y_0[22]\, - \y_m[22]\, \y_iv_0[22]\, \y_m[23]\, \y_iv_2[21]\, - \y_m[21]\, \y_m_0[21]\, \y_iv_0[21]\, \y[21]\, - \y_m_0[22]\, \y_iv_1[23]\, \y_0[23]\, \y_m_0[23]\, - \y_iv_0[23]\, \y_m[24]\, \y_iv_1[20]\, \y[20]\, \y_m[20]\, - \y_iv_0[20]\, \y_0[20]\, \y_m_2[21]\, \y_iv_0_1[1]\, - \y_0[1]\, N_378, \y_iv_0_0[1]\, N_381, \y_iv_0_o5_1[0]\, - \y[0]\, N_465, \y_iv_0_o5_0[0]\, \y_0[0]\, N_468, - trap_0_sqmuxa_7_1, trap_2, werr_1, - ADD_33x33_fast_I268_un1_Y_0_0, N659, \y_iv_2[3]\, - \y_m[4]\, \y_m_0[3]\, \y_iv_1[3]\, \y[3]\, \y_m[3]\, - \y_iv_1[2]\, \y[2]\, \y_m[2]\, \y_iv_0[2]\, \y_0[2]\, - \y_m_2[3]\, \y_iv_2[4]\, \y_m_0[4]\, \y_m_2[4]\, - \y_iv_0[4]\, \y[4]\, \y_m[5]\, \tt_9_0_a3_0[5]\, - \y_iv_0_1[14]\, \y[14]\, N_387, \y_iv_0_0[14]\, \y_0[14]\, - N_389, \y_iv_0_2[29]\, N_419, N_416, \y_iv_0_1[29]\, - \y_0[29]\, N_417, \y_iv_1[11]\, \y[11]\, \y_m[11]\, - \y_iv_0[11]\, \y_0[11]\, \y_m[12]\, \y_iv_2[5]\, \y_m[6]\, - \y_m_0[5]\, \y_iv_1[5]\, \y[5]\, \y_m_2[5]\, \y_iv_2[9]\, - \y_m[10]\, \y_m_0[9]\, \y_iv_1[9]\, \y[9]\, \y_m[9]\, - \y_iv_1[10]\, \y[10]\, \y_m_0[10]\, \y_iv_0[10]\, - \y_0[10]\, \y_m_0[11]\, \y_iv_1[19]\, \y[19]\, \y_m[19]\, - \y_iv_0[19]\, \y_0[19]\, \y_m_0[20]\, \y_iv_0_2[18]\, - N_397, N_394, \y_iv_0_1[18]\, \y[18]\, N_395, - \y_iv_0_1[27]\, \y[27]\, N_422, \y_iv_0_0[27]\, \y_0[27]\, - N_424, \y_iv_2[26]\, \y_m[27]\, \y_m_0[26]\, \y_iv_1[26]\, - wy_RNIMKUI, \y[26]\, \y_m[26]\, \y_iv_1[12]\, \y_0[12]\, - \y_m_0[12]\, \y_iv_0[12]\, \y_m[13]\, \y_iv_2[28]\, - \y_m[29]\, \y_m_0[28]\, \y_iv_1[28]\, \y_0[28]\, - \y_m[28]\, \y_iv_2[17]\, \y_m[18]\, \y_m_0[17]\, - \y_iv_1[17]\, \y_0[17]\, \y_m[17]\, \y_iv_2[15]\, - \y_m[15]\, \y_m_0[15]\, \y_iv_0[15]\, \y[15]\, \y_m[16]\, - \y_iv_1[8]\, \y_0[8]\, \y_m[8]\, \y_iv_0[8]\, y08, - \y_m_2[9]\, \y_iv_1[13]\, \y_0[13]\, \y_m_0[13]\, - \y_iv_0[13]\, \y_m[14]\, \y_iv_1[16]\, \y_0[16]\, - \y_m_0[16]\, \y_iv_0[16]\, \y_m_1[17]\, \y_iv_1[6]\, - \y[6]\, \y_m_0[6]\, \y_iv_0[6]\, \y_0[6]\, \y_m[7]\, - \y_iv_2[7]\, \y_m_0[8]\, \y_m_0[7]\, \y_iv_1[7]\, - \y_0[7]\, \y_m_1[7]\, \y_iv_2[25]\, \y_m_2[26]\, - \y_m_0[25]\, \y_iv_1[25]\, \y[25]\, \y_m[25]\, - \y_iv_2[30]\, \y_m_1[31]\, \y_m_0[30]\, \y_iv_1[30]\, - \y_0[30]\, \y_m[30]\, ADD_33x33_fast_I268_un1_Y_0_1, - N593_0, N601, ADD_33x33_fast_I271_un1_Y_0, N665, N614_0, - ADD_33x33_fast_I269_un1_Y_0, N595, N603_i, - un23_exbpmiss_0, wreg_1_6_0, wreg_1_0_0, un2_rs1_2_0_i_0, - wreg_1_3, wreg_1_5, un2_rs1_2_7_i_0, un2_rs1_2_5_i_0, - wreg_1_2_0, \un3_de_ren1[94]\, \rd_0[3]\, un2_rs1_2_6_i_0, - \un3_de_ren1[92]\, \rd_0[1]\, un2_rs1_2_2_i_0, - \un3_de_ren1[95]\, \rd[4]\, N552, N669, N552_0, N669_0, - illegal_inst_7_iv_7, N_603, illegal_inst_7_iv_8_tz, - illegal_inst_7_iv_5, illegal_inst_7_iv_6_0, \cpi_m[121]\, - illegal_inst_7_iv_3, \inst_RNI3RNK9[19]\, - illegal_inst_7_iv_6_tz, illegal_inst_7_iv_2_0_a5_1_0, - N_474, illegal_inst_7_iv_0, N_444, illegal_inst_7_iv_1, - illegal_inst_4_m_0, illegal_inst33, - cp_disabled_3_sqmuxa_2, illegal_inst_1_sqmuxa_i_2, N_434, - \cpi_m_i[133]\, wreg_2_5, un2_rs1_1_7_i_0, - un2_rs1_1_5_i_0, wreg_2_2, wreg_2_4, \rs1_iv_i_0[0]\, - wreg_2_0, wreg_2_3, un2_rs1_1_6_i_0, un2_rs1_1_2_i_0, - \rd_0[4]\, un2_rs1_NE_5, un2_rs1_0_i, un2_rs1_6_i, - un2_rs1_NE_2, un2_rs1_NE_4, un2_rs1_5_i, un2_rs1_4_i, - un2_rs1_NE_1, \un3_de_ren1[93]\, un2_rs1_3_i, - \un3_de_ren1[98]\, \rd[7]\, un2_rs1_1_i, N659_0, N552_1, - N611, \edata2_0_iv_0[8]\, \op1[8]\, \ex_op1_i_m[8]\, - \edata2_0_iv_0[9]\, \op1[9]\, \ex_op1_i_m[9]\, - \edata2_0_iv_0[10]\, \op1_i_m[10]\, \edata2_0_iv_1[15]\, - \ex_op1_i_m[15]\, \op1_i_m[15]\, \bpdata_i_m_2[7]\, - \y_iv_0_2[24]\, N_374, N_371, \y_iv_0_1[24]\, \y_0[24]\, - N_372, \edata2_0_iv_1[21]\, \edata2_0_iv_0[21]\, - \bpdata[21]\, \op1_i_m[21]\, \edata2_0_iv_0[19]\, - \op1_i_m[19]\, \edata2_0_iv_0[16]\, \op1_i_m[16]\, - \edata2_0_iv_0[18]\, \op1_i_m[18]\, \edata2_0_iv_0[22]\, - \op1_i_m[22]\, \edata2_0_iv_1[23]\, \bpdata_i_m[23]\, - \op1_i_m[23]\, \ex_op1_i_m[23]\, \edata2_0_iv_1[20]\, - \edata2_0_iv_0[20]\, \bpdata[20]\, \op1_i_m[20]\, - \edata2_0_iv_0[11]\, \op1[11]\, \ex_op1_i_m[11]\, - \edata2_0_iv_1[13]\, \ex_op1_i_m[13]\, \op1_i_m[13]\, - \bpdata_i_m[13]\, \edata2_0_iv_0[12]\, \op1[12]\, - \ex_op1_i_m[12]\, \edata2_0_iv_1[14]\, \bpdata_i_m[14]\, - \edata2_0_iv_0[14]\, \op1_i_m[14]\, \edata2_iv_2[27]\, - edata_1_sqmuxa, \bpdata_i_m_2[3]\, \edata2_iv_1[27]\, - \ex_op1_i_m[27]\, \op1_RNI4VNF[27]\, \bpdata_i_m[27]\, - \edata2_iv_1[29]\, \ex_op1_i_m[29]\, \op1_RNI67OF[29]\, - \bpdata_i_m[29]\, \edata2_iv_2[25]\, \bpdata[9]\, - \bpdata_i_m_2[1]\, \edata2_iv_1[25]\, \bpdata[25]\, - \edata2_iv_0[25]\, \op1_RNI2NNF[25]\, \edata2_iv_2[24]\, - \aluop_RNI6QSC4[2]\, \bpdata_i_m_2[0]\, \edata2_iv_1[24]\, - \ex_op1_i_m[24]\, \op1_RNI1JNF[24]\, \bpdata_i_m[24]\, - \edata2_iv_2[30]\, \bpdata_i_m_0[14]\, \bpdata_i_m_2[6]\, - \edata2_iv_1[30]\, \bpdata[30]\, \edata2_iv_0[30]\, - \op1_RNIU2NF[30]\, \edata2_iv_2[28]\, \bpdata_i_m_2[4]\, - \edata2_iv_0[28]\, \op1[28]\, \ex_op1_i_m[28]\, - \edata2_iv_2[26]\, \bpdata_i_m_2[2]\, \edata2_iv_1[31]\, - un4_icc_m, \op1_i_m[31]\, \bpdata_i_m[31]\, rs1_2, - \rs1[4]\, \alusel_i_0_2[0]\, \alusel_i_0_1[0]\, N_351, - N_352, N_602, \alusel_i_0_1[1]\, N_341, \alusel_i_0_0[1]\, - N_212, \alusel_i_0_a5_0_0[1]\, N_339, - ADD_33x33_fast_I293_Y_0_0, \op2[2]\, \un1_iu0_6[2]\, - illegal_inst_7_iv_2_0_a5_0_1, \inst_2[19]\, - illegal_inst35_4, illegal_inst_7_iv_2_0_a5_0_0, N_487, - \inst_1[24]\, ADD_33x33_fast_I121_Y_0, \data_0[17]\, N445, - ADD_33x33_fast_I129_Y_0, N433_0, - ADD_33x33_fast_I121_Y_0_0, N445_0, \icc_1_iv_0[1]\, - icc_2_sqmuxa, \result_0[21]\, \icc_m_0[1]\, - \icc_1_iv_0[0]\, \result[20]\, \icc_m_0[0]\, - \icc_1_iv_0[3]\, \result[23]\, \icc_m_0[3]\, - \icc_1_iv_0[2]\, \result_0[22]\, \icc_m_0[2]\, - ADD_33x33_fast_I145_Y_0, \op2[5]\, N409, - ADD_33x33_fast_I145_Y_0_0, N409_0, - ADD_33x33_fast_I137_Y_0, N421, \data_0[9]\, N_271, N_209, - ADD_33x33_fast_I129_Y_0_0, N433_1, \data_0[13]\, - ADD_33x33_fast_I121_Y_0_1, N445_1, - ADD_33x33_fast_I137_Y_0_0, N421_0, - ADD_33x33_fast_I145_Y_0_1, N409_1, - ADD_33x33_fast_I137_Y_0_1, N421_1, un1_ld_1_sqmuxa_1_0, - un3_op2, write_reg_4_sqmuxa, ADD_33x33_fast_I113_Y_0, - N457, ADD_33x33_fast_I113_Y_0_0, N457_0, - ticc_exception_0_a3_1, un1_inst, un1_icc_check5_1_0, - icc_check9, \alusel_i_0_o5_0[1]\, \alusel_i_0_a2_1_0[1]\, - N_476, \tt_9_i_a4_0[2]\, wunf, wovf, bp, wim_1_sqmuxa_1, - wim_1_sqmuxa_0, un1_illegal_inst33_2, - un1_illegal_inst33_0, privileged_inst_0_sqmuxa, N_202, - illegal_inst37_4, illegal_inst38, G_9_0, N_6337, - ADD_33x33_fast_I130_Y_0_0, \op2[10]\, N431_1, - ADD_33x33_fast_I138_Y_0, N419, \inst_1[20]\, \inst_1[22]\, - \inst_0[23]\, ADD_33x33_fast_I138_Y_0_0, N419_0, - ADD_33x33_fast_I122_Y_0, N443, icc_check6_0, un7_op_3, - un1_icc_check5_0, icc_check10, - ADD_33x33_fast_I206_Y_0_o3_1_0, N397, \npc_cnst_m_0[0]\, - pv_4, pv_5, \npc_cnst_m_0[1]\, - ADD_33x33_fast_I206_Y_0_o3_1_0_0, \op2[1]\, N397_0, - ADD_33x33_fast_I206_Y_0_o3_1_0_1, N397_1, write_reg7_0, - N_89, N_122_1, inst_0, ADD_33x33_fast_I146_Y_0, N404, - N407, ADD_33x33_fast_I130_Y_0_1, N431_2, aluop_2_1_0_2, - aluadd_16_sqmuxa_0_a5_1, N_205, N_359, aluop_2_1_0_1, - N_360, \cnt_RNILD6A1[0]\, N_345, aluop_0_1_0_2, - aluop_0_1_0_a5_3_0, N_363, aluop_0_1_0_1, N_365, - \inst_RNILL631[19]\, N_362, de_inst_0_sqmuxa_0, un19_rd_1, - N_17, N_122_2, N_79, dwt_1_sqmuxa_3, dwt_1_sqmuxa_2, - \inst[27]\, \inst[26]\, \inst_1[29]\, \inst[25]\, - \inst[28]\, icc_2_sqmuxa_2, icc_2_sqmuxa_1, wicc, - \logicout_5_0_i_a5_0_0[24]\, illegal_inst34_3, - illegal_inst34_1, illegal_inst34_0, inst_5, inst_11_1, - inst_9_3, inst_22, inst_32_1, inst_32_0, inst_21, - ADD_33x33_fast_I206_Y_0_a3_1_0_0, N398_0, - aluresult_13_sqmuxa_3_0, aluresult_13_sqmuxa_1, - aluresult_13_sqmuxa_0_0, aluresult_13_sqmuxa_3, - \inst_1[21]\, \inst_0_m_0[26]\, un14_op_1, un14_op_2, - aluop_1_1_0_2, aluop_1_1_0_a5_0_0, aluop_1_1_0_0, N_262, - aluop_1_1_0_a5_0, N_344, invop2_0_1_i_0, N_58, - fp_disabled_4_0_1_1, cp_disabled_10_sqmuxa_1, N_260, - cp_disabled_5_sqmuxa, cp_disabled_4_0_1_1, - cp_disabled_11_sqmuxa, cp_disabled_4_0_1_0, - cp_disabled_2_sqmuxa_0, N_216, cp_disabled_8_sqmuxa_1, - bpdata6_2, rd_7_i_0, rd_4_i_0, rd_3_i_0, bpdata6_4, - \rd[5]\, \rd_0[5]\, rd_6_i_0, \rd_1[1]\, rd_2_i_0, - rstate_4_2, y6, y10, rstate_4_1, error_1_sqmuxa, - trap_1_sqmuxa_1, \cnt_1[1]\, \cnt_0[0]\, rstate_7_0, - ex_bpmiss_1_0_a5_0_0, N_261, ex_bpmiss_1_0_0, - ex_bpmiss_1_0_a5_0, N_328, N_427, cwp_2_sqmuxa_4, - cwp_2_sqmuxa_1, cwp_2_sqmuxa_2, icc_0_sqmuxa_1, - illegal_inst_7_iv_2_0_a5_5_0, et_1, \inst_2[21]\, - aluresult_11_sqmuxa_0, aluresult_11_sqmuxa_6, \inst[13]\, - \inst_1[25]\, \inst_2[20]\, N_201, bicc_hold_3, - bicc_hold_1, N_3736_2, rstate_9_0, un1_trap_0_sqmuxa_1_0, - trap55_i, \maddress[0]\, trap_0_sqmuxa_3, - \un6_ex_add_res_s0_0_0[1]\, \data_0[0]\, wicc_1_0_tz_0, - wicc_1_0_a3_1_1_0, N_152, wicc_1_0_a3_0, - cp_disabled_3_sqmuxa_2_0, un1_aop2_1_sqmuxa_0_a2_0_0, - ldcheck1_2, ldcheck1_5_i_a6_2_2, N_3737_1, N_3736, - ldcheck1_1, ldcheck1_5_i_a6_0_0, ldcheck1_0, - ADD_30x30_fast_I100_Y_0, N418_2, aluop_2_1_0_a2_1, - aluop_2_1_0_a2_0, \inst_1[23]\, illegal_inst_1_sqmuxa_i_0, - N_433, alusel24_2, \cpi_m_1[133]\, y_0_sqmuxa_3, - y_0_sqmuxa_1, \inst_0_0[24]\, de_fins_hold_1_1, bp_0, - \size_1[1]\, ex_sari_1_1_0, ADD_30x30_fast_I116_Y_0, N394, - ex_bpmiss_1_0_2_tz_0, ex_bpmiss_1_0_a5_2_1_0, N_248, - ex_bpmiss_1_0_a5_4_1, wy_1_0_a3_0_7_2, N_3525_3, - wy_1_0_a3_0_7_1, icc_check_bp_1, tmp, aluop_0_1_0_a5_0, - N_225, \inst_1[26]\, \inst_1[27]\, ex_bpmiss_1_0_a5_1_1, - N_482, illegal_inst12_0, N_492, \cnt_2[1]\, - ldcheck2_2_sqmuxa_1_1, \inst_0_0[22]\, ldchkex_0, - \size_0[0]\, N_3758, miscout_11_sqmuxa_0, y_0_sqmuxa_2, - jump_1_sqmuxa_1_1, un1_trap_0_sqmuxa_0, trap_0_sqmuxa_2, - trap_0_sqmuxa_1, d29_0, illegal_inst35_4_0, \cnt_1[0]\, - icc_check_3_0_a3_1, \inst_0_0[23]\, un54_casaen, - \alusel_i_0_a5_0_0[0]\, N_3518_1, aluresult_8_sqmuxa_1, - inst_11_0, jump_0_sqmuxa_1_2, jump_0_sqmuxa_1_0, N_3749_1, - ADD_30x30_fast_I109_Y_0, N404_0, un3_op_2, un3_op_1, - aluresult_11_sqmuxa_4, inst_22_0, inst_21_1, - trap_0_sqmuxa_3_1, \inst_3[19]\, trap_0_sqmuxa_3_2, - ADD_30x30_fast_I117_Y_0, N392, trap54_1517_0, - \inst_3[20]\, ldcheck1_5_i_a6_1_1, un11_op, fins_0_a3_0, - SIGNED_2_1, ex_bpmiss_1_0_1630_tz_0, \inst_2[25]\, - ex_bpmiss_1_0_a5_3_0, ADD_30x30_fast_I125_Y_0, N380, - ldcheck1_5_i_a6_2_1, y6_0_0, read_1_sqmuxa_0, - y_0_sqmuxa_1_1, y11_0, un4_op_0, intack_1, \tt[6]\, - \tt[7]\, intack_0, \tt[4]\, \tt[5]\, aluop_2_1_0_a5_1_0, - icc_check8_1, N_3515_1, un1_icc_2_sqmuxa_1, icc_check7_2, - \icc[1]\, \icc[3]\, aluop_0_1_0_a5_1_0_0, - write_3_0_a3_0_2_0, force_a2_1, force_a2_0, - trap_0_sqmuxa_2_1, trap_0_sqmuxa_2_0, \inst_2[23]\, - trap27_0, trap_0_sqmuxa_1_0, nalign, inst_4_2, - \inst_2[22]\, inst_4_1, y10_3_0, inst_3_2_1, inst_3_2_0, - tt_2, \tt_0[4]\, \tt_0[5]\, tt_1, \tt[2]\, \tt[3]\, tt_0, - \tt[0]\, \tt[1]\, un29_casaen_5, \inst[8]\, un29_casaen_3, - \inst[5]\, un29_casaen_4, un29_casaen_1, \inst[11]\, - \inst[10]\, \inst[7]\, \inst[9]\, \inst[6]\, \inst[12]\, - wy_1_0_1, un5_irl_1, un5_irl_0, rett_1_0, rett, rett_0, - rett_0_0, rett_2, rett_3, \npc_iv_2[8]\, - \un6_fe_npc_m[6]\, \npc_iv_0[8]\, \npc_iv_2[10]\, - \un6_fe_npc_m[8]\, \npc_iv_1[10]\, \eaddress[10]\, - \pc_m[10]\, \npc_iv_0[10]\, \npc_iv_2[7]\, - \un6_fe_npc_m[5]\, \npc_iv_1[7]\, \eaddress[7]\, - \pc_m[7]\, \npc_iv_0[7]\, \npc_iv_2[9]\, - \un6_fe_npc_m[7]\, \npc_iv_1[9]\, \eaddress[9]\, - \pc_m[9]\, \npc_iv_0[9]\, \tmp_m[9]\, \npc_iv_2[4]\, - \un6_fe_npc_m[2]\, \npc_iv_1[4]\, \npc_iv_0[4]\, - \npc_iv_3[2]\, \npc_iv_1[2]\, \fpc[2]\, \npc_iv_2[3]\, - \npc_iv_1[3]\, \fpc[3]\, \npc_iv_0[3]\, \npc_iv_2[5]\, - I_13, \npc_iv_1[5]\, \npc_iv_0[5]\, - illegal_inst_7_iv_2_0_a5_4_2, N_472, N_229, N_523, N528, - I52_un1_Y, N409_2, I108_un1_Y, N529, N407_0, N410, N537, - N478_0, N544, I68_un1_Y, N385, I124_un1_Y, N545, N486, - N552_2, N497_1, N494, I243_un1_Y, N605, I212_un1_Y, - I232_un1_Y, N567_1, N583, I190_un1_Y, I210_un1_Y, - I244_un1_Y_0, N607, N_41, N_39_0, N454, - ADD_30x30_fast_I233_Y_0_a3_0, trap_0_sqmuxa_2_2, - trap_0_sqmuxa_1_2_i, \y_0[4]\, \pc_1[9]\, \y_1[20]\, - \logicout_m[20]\, N_351_1, \y_1[30]\, \y_0[25]\, - \y_1[23]\, \y_RNO_2[23]\, \aluop_RNIESJP4[2]\, N_259, - N_515, cwp_2_sqmuxa_i, tba_1_sqmuxa_3, \y_1[2]\, - \logicout_m[2]\, \bpdata_i_m[12]\, \y_1[7]\, \y_1[6]\, - \logicout_m[6]\, wim_1_sqmuxa, y_0_sqmuxa_1_2, - xc_wreg_0_sqmuxa, cwp_1_sqmuxa, \bpdata_i_m[26]\, - \bpdata_i_m_1[4]\, \bpdata_i_m[15]\, \bpdata_i_m[28]\, - \pc_1[2]\, \un6_fe_npc_m[0]\, N_241, illegal_inst_7_i_0, - \bpdata_i_m_1[7]\, \y_1[16]\, \logicout_m[16]\, - \ex_op1_i_m[22]\, \bpdata_i_m_1[6]\, N_22, N_6618, - \bpdata_i_m_2[5]\, \ex_op1_i_m[17]\, \bpdata_i_m_1[1]\, - \pc_1[31]\, \un6_fe_npc_m[29]\, \y_1[13]\, - \logicout_m[13]\, \pc_1[15]\, \un6_fe_npc_m[13]\, - \pc_1[17]\, \un6_fe_npc_m[15]\, \pc_1[20]\, - \un6_fe_npc_m[18]\, \pc_1[13]\, \un6_fe_npc_m[11]\, - \pc_1[12]\, I_56, \pc_1[18]\, \tmp_m[18]\, - \un6_fe_npc_m[16]\, \bpdata_i_m[10]\, y6_0, \y_0[3]\, - \y_1[8]\, \logicout_m[8]\, \y_0[15]\, \y_1[17]\, - \y_0[21]\, \y_1[22]\, \logicout_m[22]\, \y_0[31]\, - \y_1[28]\, \y_1[12]\, \logicout_m[12]\, \y_0[26]\, - \y_1[0]\, N_463, \pc_1[30]\, \un6_fe_npc_m[28]\, N_481, - \pc_1[26]\, \un6_fe_npc_m[24]\, N_15, \pc_1[27]\, I_173, - \y_1[27]\, N_420, \y_1[1]\, N_377, \y_1[24]\, N_230, - N_473_i, N_256_i_0, N_6696, N_519, N_232, N_172, N_410, - N_409, N_411, N_163, N_399, N_398, N_400, N_158, N_391, - N_390, N_392, N_6686, N_368, N_367, N_369, N_470, N_207, - N_469, y_1_sqmuxa, inst_14, N_3738, un1_ldcheck1_1, - un1_illegal_inst34, \bpdata_i_m[3]\, \icc_1[2]\, - icc_1_sqmuxa, \icc[2]\, N_127, N_126, N_128, - un1_de_ren1_NE_i_0, \rd[6]\, \un3_de_ren1[105]\, - \tmp[18]\, N403, ADD_30x30_fast_I216_Y_0_a3, - un2_rs1_NE_i_0, \inst[18]\, \inst[14]\, \inst[17]\, - N_8_0_i_0, N_29, N536, N481_2, annul_RNIVCQHS1, - \pc_1[21]\, \un6_fe_npc_m[19]\, \pc_1[28]\, - \un6_fe_npc_m[26]\, trap_1_sqmuxa, trap_0_sqmuxa_4, y11, - \maddress[2]\, result_1, dwt_1_sqmuxa, N_3721, ldcheck1, - \inst_0_RNIMRAH[23]\, rfe_1, rfe_1_1, rfe_1_2, bp_1, - ctrl_annul_i, \pc_1[8]\, \y_0[18]\, \y_1[19]\, - \logicout_m[19]\, inst_1, iflush_1, ticc_exception, - branch_1, ra_bpmiss_1, rd_0_sqmuxa, N_67, un52_casaen, - un19_rd, \rd_3[0]\, \inst_RNIHVSN2[24]\, wreg_1_8, - \rd_0[6]\, wreg_2_1, ldcheck2_2_sqmuxa_1_i, N_3834_2, - un4_op3, de_inst_0_sqmuxa_i_0, N_6697_i_0, - illegal_inst37_2, SIGNED_2, N_3742_i, un17_casaen, - tt_2_sqmuxa_1, un6_annul, icc_0_sqmuxa_1_i, werr_RNO, - irqen_0, trap_2_0, un1_trap_0_sqmuxa_5, icc_check8, - icc_check7_i, un13_op3, un8_op3, un12_op3, - un1_ld_1_sqmuxa_1, write_reg_2_sqmuxa, - annul_next_2_sqmuxa_1, un2_exbpmiss, - un1_annul_next_1_sqmuxa_3, N_149, ra_bpannul_1, - \un1_p0_6[0]\, N_117, N_96, N_150, annul_current, pv_6, - pv_4_0, pv_RNO_6, N_4239, \inst_2[29]\, un2_exbpmiss_0, - \icc_1[3]\, \icc_0[3]\, \icc_1[0]\, \icc[0]\, - icc_0_sqmuxa, cnt_2_sqmuxa, annul_4, cnt_3_sqmuxa, N465, - N462, hold_pc_2_m, I239_un1_Y, N581, N597, \tmp[9]\, N610, - \pc_1[25]\, \un6_fe_npc_m[23]\, I202_un1_Y_i, I238_un1_Y, - N579, N595_0, cp_disabled_6_sqmuxa, cp_disabled_1_sqmuxa, - trap_4, N_4033_i, N_211, ex_bpmiss_1, N_6695_i, - \icc_0[2]\, branch_1_sqmuxa_i, \y_1[10]\, - \logicout_m[10]\, \y_0[9]\, \d_1[0]\, \aluresult_m_i[0]\, - N802, N584, N522_0, N519_0, N585, N443_0, N440_0, N592, - I67_un1_Y, N436_1, I129_un1_Y, N600, N538, N535, N601_0, - N608, N546, N543_0, I272_un1_Y, N667, N616, N790, - I237_un1_Y, N802_0, I51_un1_Y, N460, I113_un1_Y, N585_0, - N519_1, N592_0, N530, N419_1, N416_1, N535_0, - I264_un1_Y_1, N651_1, N811_1, N782_0, N674_0, - I272_un1_Y_0, N667_0, N616_0, N790_0, I237_un1_Y_0, - N802_1, N676, N585_1, N443_1, N440_1, N519_2, N593_1, - N527_1, N600_0, N538_0, N535_1, N608_0, N546_0, N543_1, - N609, N407_1, N404_1, I272_un1_Y_i, N667_1, N616_1, - N790_1, I237_un1_Y_1, N650_1, N657, N672, N_57, N398_1, - N401_0, I234_un1_Y, N571_1, I194_un1_Y, I240_un1_Y, N599, - I206_un1_Y, N582_0, I214_un1_Y, rdata_3_sqmuxa, - rdata_3_sqmuxa_2, un1_de_ren1_1_5_i_0, - un1_de_ren1_1_6_i_0, rfe, un1_de_ren1_2, \pc_1[5]\, - \aluresult[5]\, \un6_ex_add_res_m[6]\, \y_0[5]\, - \d_i[19]\, \op1_m_0[19]\, \aluresult_m_0[19]\, \d[4]\, - \aluresult[4]\, \d[3]\, \op1_m_0[3]\, \aluresult_m_0[3]\, - \aluresult[20]\, \shiftin_17_m_0[20]\, - \un6_ex_add_res_m[21]\, \d_i[27]\, \op1_m_0[27]\, - \aluresult_m_0[27]\, \d_i[22]\, \op1_m_0[22]\, - \aluresult_m_0[22]\, \d_i[21]\, \aluresult[21]\, - \d_i[17]\, \op1_m_0[17]\, \aluresult_m_0[17]\, \d_i[7]\, - \op1_m_0[7]\, \aluresult_m_0[7]\, \shiftin_17_m_0[29]\, - \un6_ex_add_res_m[30]\, \aluresult[24]\, - \shiftin_17_m_0[24]\, \un6_ex_add_res_m[25]\, - \aluresult[25]\, \un6_ex_add_res_m[26]\, \d_i[26]\, - \op1_m_0[26]\, \aluresult_m_0[26]\, \d_i[25]\, - \op1_m_0[25]\, \aluresult_m_0[25]\, \d_i[24]\, \d_i[23]\, - \op1_m_0[23]\, \aluresult_m_0[23]\, \aluresult[0]\, - \shiftin_17_m[1]\, \d_i[30]\, \op1_m_0[30]\, - \aluresult_m_0[30]\, \d_i[16]\, \op1_m_0[16]\, - \aluresult_m_0[16]\, \d_i[6]\, \op1_m_0[6]\, - \aluresult_m_0[6]\, \d_i[29]\, \d_i[28]\, \aluresult[28]\, - \d[2]\, \op1_m_0[2]\, \aluresult_m_0[2]\, \bpdata_i_m[9]\, - \bpdata_i_m_0[13]\, \ex_op1_i_m[18]\, \bpdata_i_m_1[2]\, - \ex_op1_i_m[16]\, \bpdata_i_m_1[0]\, \bpdata_i_m[8]\, - \aluresult[17]\, \un6_ex_add_res_m[18]\, - \shiftin_17_m_0[21]\, \un6_ex_add_res_m[22]\, - \aluresult[7]\, \shiftin_17_m_0[7]\, ldbp2_0_RNIKEHUF, - \d[1]\, \op1_m_0[1]\, \aluresult_m_0[1]\, - un1_illegal_inst33, \aluresult[31]\, \shiftin_17_m_0[31]\, - \un6_ex_add_res_m[32]\, \bpdata_i_m[11]\, \d_i[8]\, - \op1_m_0[8]\, \aluresult_m_0[8]\, \d_i[9]\, \op1_m_0[9]\, - \aluresult_m_0[9]\, \d_i[15]\, \op1_m_0[15]\, - \aluresult_m_0[15]\, \aluresult[27]\, \d_i[14]\, - \op1_m_0[14]\, \aluresult_m_0[14]\, \ex_op1_i_m[19]\, - \bpdata_i_m_1[3]\, \aluresult[10]\, \shiftin_17_m_0[10]\, - \un6_ex_add_res_m[11]\, \aluresult[11]\, - \shiftin_17_m_0[11]\, \un6_ex_add_res_m[12]\, - \aluresult[18]\, \shiftin_17_m_0[18]\, - \un6_ex_add_res_m[19]\, \aluresult[12]\, - \shiftin_17_m_0[12]\, \un6_ex_add_res_m[13]\, - \aluresult[3]\, ldbp2_2_RNI7G0C6, \aluresult[8]\, - \pc_1[10]\, intack, \aluresult[14]\, \shiftin_17_m_0[14]\, - \un6_ex_add_res_m[15]\, \pc_1[29]\, \un6_fe_npc_m[27]\, - \pc_1[16]\, \un6_fe_npc_m[14]\, \aluresult[23]\, - \un6_ex_add_res_m[24]\, \d_i[12]\, \op1_m_0[12]\, - \aluresult_m_0[12]\, \d_i[11]\, \op1_m_0[11]\, - \aluresult_m_0[11]\, \d_i[13]\, \op1_m_0[13]\, - \aluresult_m_0[13]\, \aluresult[6]\, \shiftin_17_m_0[6]\, - ldbp2_2_RNI5355F, \aluresult[26]\, \un6_ex_add_res_m[27]\, - \y_1[11]\, \logicout_m[11]\, \aluresult[22]\, - \shiftin_17_m_0[22]\, \un6_ex_add_res_m[23]\, \d[0]\, - \op1_m_0[0]\, \aluresult_m_0[0]\, un1_aop2_1_sqmuxa, - \aluresult[19]\, \shiftin_17_m_0[19]\, - \un6_ex_add_res_m[20]\, tt_i, N_3749, N_3748, - \aluresult[15]\, \shiftin_17_m_0[15]\, - \un6_ex_add_res_m[16]\, \pc_1[19]\, \un6_fe_npc_m[17]\, - \pc_1[23]\, \un6_fe_npc_m[21]\, \un6_ex_add_res_m[29]\, - aluresult_10_sqmuxa, aluresult_12_sqmuxa, \y_1[29]\, - \d_i_0[5]\, N_407, N_408, \y_1[14]\, N_385, N_6684_i_0, - N_348, N_236, N_346, N_3840, N_500, N_6829, - \un1_iu0_6[3]\, N_6838, N_6841, N_6853, \un1_iu0_5[96]\, - N_6856, \un1_iu0_5[91]\, N_6862, N_6865, \un1_iu0_6[0]\, - N_6868, N_6871, \un1_iu0_6[7]\, N_6874, \un1_iu0_5[94]\, - N_6877, N_6883, \un1_iu0_6[15]\, N_6886, \un1_iu0_6[16]\, - \un1_iu0_5[82]\, N_6889, \op2_RNI1LHG[1]\, N_6895, - \un1_iu0_6[18]\, N_6898, \un1_iu0_5[79]\, N_6901, - \un1_iu0_5[80]\, N_6904_i, \un1_iu0_5[87]\, N_6907, - \un1_iu0_5[68]\, N_6910, \un1_iu0_6[11]\, N_6913, - \un1_iu0_5[85]\, N_6916, \un1_iu0_5[97]\, N_6919, N_174, - N_413, N_412, N_414, N_153, N_383, N_382, N_384, N_220, - \ex_op1_i_m[1]\, \op1_i_m[1]\, \bpdata_i_m[1]\, - \bpdata_i_m[5]\, \ex_op1_i_m[6]\, \op1_i_m[6]\, - \bpdata_i_m[6]\, \bpdata_i_m[7]\, ps_1, s_m, ps_m, - \result_m[6]\, \bpdata_i_m[0]\, rdata200, rdata_4_sqmuxa, - N_6529, ANC1, CO1_0, \un6_ex_add_res_s1_i[27]\, - \un6_ex_add_res_s1_i[19]\, \op2[18]\, - \un6_ex_add_res_s1_i[17]\, \op2[16]\, N794_i, - \un6_ex_add_res_s1_i[13]\, N430, - ADD_33x33_fast_I246_Y_0_a3_0, \un6_ex_add_res_s1_i[11]\, - \un6_ex_add_res_s1[8]\, \op2[7]\, N672_0, \d_1[31]\, - \op1_m_i[31]\, \aluresult_m_i[31]\, \d_1[30]\, - \op1_m_i[30]\, \aluresult_m_i[30]\, \d_1[28]\, - \op1_m_i[28]\, \aluresult_m_i[28]\, \d_1[27]\, - \op1_m_i[27]\, \aluresult_m_i[27]\, \d_1[26]\, - \op1_m_i[26]\, \aluresult_m_i[26]\, \d_1[25]\, - \op1_m_i[25]\, \aluresult_m_i[25]\, \d_1[24]\, - \op1_m_i[24]\, \aluresult_m_i[24]\, \d_1[23]\, \d_1[22]\, - \op1_m_i[22]\, \aluresult_m_i[22]\, \d_1[21]\, \d_1[20]\, - \op1_m_i[20]\, \aluresult_m_i[20]\, \d_1[19]\, - \op1_m_i[19]\, \aluresult_m_i[19]\, \d_1[18]\, - \op1_m_i[18]\, \aluresult_m_i[18]\, \d_1[17]\, - \op1_m_i[17]\, \aluresult_m_i[17]\, \d_1[16]\, - \op1_m_i[16]\, \aluresult_m_i[16]\, \d_1[15]\, - \op1_m_i[15]\, \aluresult_m_i[15]\, \d_1[14]\, - \op1_m_i[14]\, \aluresult_m_i[14]\, \d_1[13]\, - \aluresult[13]\, \d_1[12]\, \op1_m_i[12]\, - \aluresult_m_i[12]\, \d_1[11]\, \op1_m_i[11]\, - \aluresult_m_i[11]\, \d_1[10]\, \d_1[9]\, \aluresult[9]\, - \d_1[8]\, \op1_m_i[8]\, \aluresult_m_i[8]\, \d_1[7]\, - \op1_m_i[7]\, \aluresult_m_i[7]\, \d_1[6]\, \op1_m_i[6]\, - \aluresult_m_i[6]\, \d_1[5]\, \op1_m_i[5]\, - \aluresult_m_i[5]\, \d_1[4]\, \d_1[3]\, \op1_m_i[3]\, - \aluresult_m_i[3]\, \d_1[2]\, \op1_m_i[2]\, - \aluresult_m_i[2]\, \d_1[1]\, \aluresult_m_i[1]\, - \data_0_1[26]\, \dco_m_1[122]\, \data_0_m[26]\, - \data_0_1_4[18]\, \data_0_1[25]\, \dco_m_1[121]\, - \data_0_m[25]\, \data_0_1[17]\, \data_0_1[12]\, - \dco_m_0[108]\, \data_0_1_4[9]\, \data_0_1[10]\, - \dco_m_0_i[106]\, \data_0_1_1[12]\, \data_0_1[8]\, - \dco_m_0_i[104]\, \data_0_1[6]\, \dco_m_i[118]\, - \dco_m_i[102]\, \data_0_1[4]\, N_3456, \data_0_1[3]\, - \data_0_1[2]\, \dco_m_i[114]\, \dco_m_i[98]\, - \data_0_1[1]\, \data_0_1[0]\, \data_0_1[21]\, - \dco_m_0[117]\, \data_0_m[21]\, \un6_ex_add_res_s1_i[3]\, - \shiftin_17_m_0[13]\, \un6_ex_add_res_m[14]\, - \aluresult[1]\, \data_0_1[7]\, \dco_m_i[119]\, - \dco_m_i[103]\, \d_i[10]\, \op1_m_0[10]\, - \aluresult_m_0[10]\, \data_0_1[11]\, \dco_m_0[107]\, - N_6844, N_57_i_0, N401_1, N609_0, N543_2, N608_1, - I145_un1_Y, N584_0, N522_1, \un6_ex_add_res_s1_i[18]\, - I239_un1_Y_0, \un6_ex_add_res_s1_i[23]\, N657_0, N641_1, - N657_1, N672_1, \data_0_1[5]\, N661, N676_0, N_6640_i, - \un6_ex_add_res_s1_i[28]\, I263_un1_Y_i, N_6892, - \un1_iu0_5[93]\, N808, N649_1, N633_1, N808_0, I259_un1_Y, - N796, N808_1, \un6_ex_add_res_s1_i[15]\, N799_0, N799_1, - \un6_ex_add_res_s1[32]\, I259_un1_Y_0, N625_0, N796_0, - I259_un1_Y_1, N625_1, N796_1, \un6_ex_add_res_s1_i[22]\, - I269_un1_Y_0, N661_0, N676_1, s_2_sqmuxa, logicout22_1, - \aluresult[2]\, \shiftin_17_m_0[2]\, jmpl_RNIR18H6, N_334, - N_3838_i_0, \data_0_1[18]\, \dco_m_0[114]\, - \data_0_m[18]\, \aluresult[16]\, \shiftin_17_m_0[16]\, - \un6_ex_add_res_m[17]\, \aluresult[30]\, - \shiftin_17_m_0[30]\, \un6_ex_add_res_m[31]\, s_1_iv, - ps_i_m, s_i_m, \result_i_m[7]\, \icc_8_1[1]\, \icc_2[1]\, - N_6859, \data_0_1[22]\, \dco_m_0[118]\, \data_0_m[22]\, - \data_0_1[24]\, \un6_ex_add_res_s1_i[21]\, N786_i, N_6835, - \un6_ex_add_res_s1[4]\, \op2[3]\, \data_0_1[23]\, - \dco_m_0[119]\, \data_0_m[23]\, \un6_ex_add_res_s1[7]\, - \op2[6]\, N782_1, N674_1, N514_0, N511_0, \data_0_1[20]\, - \dco_m_0[116]\, \data_0_m[20]\, N_6847, \d_i[20]\, - \op1_m_0[20]\, \aluresult_m_0[20]\, \data_0_1[28]\, - \dco_m_1[124]\, \data_0_m[28]\, rdata_6_sqmuxa, - \data_0_1[29]\, \dco_m_1[125]\, \data_0_m[29]\, - \data_0_1[30]\, \dco_m_1[126]\, \data_0_m[30]\, N_6850, - \un1_iu0_5[95]\, bpdata6, N_3946, N_3950, N_3946_1, d11, - \icc_8[1]\, \size[1]\, N_3755, jump_0_sqmuxa, - read_1_sqmuxa_i, un3_op_i, \size[0]\, N_3757, I271_un1_Y, - N665_0, N614_1, I271_un1_Y_i, I271_un1_Y_i_0, N665_1, - N614_2, \un6_ex_add_res_s1_i[20]\, - \un6_ex_add_res_s1_i[12]\, \op2[11]\, N609_1, N407_2, - N404_2, enaddr_2_sqmuxa, iflush_4, - \un6_ex_add_res_s1_i[6]\, \pc_1[7]\, - \un6_ex_add_res_s1_i[25]\, N778_1, \tmp[24]\, \pc_1[24]\, - \tmp_m[24]\, \un6_fe_npc_m[22]\, \icc_8_m_i[1]\, - \icc_1[1]\, \icc_0[1]\, \d_i[31]\, \op1_m_0[31]\, - \aluresult_m_0[31]\, \data_0_1[15]\, \dco_m_0[111]\, - \data_0_1[14]\, \dco_m_0[110]\, N592_1, N530_0, - \pc_1[22]\, \un6_fe_npc_m[20]\, \un6_ex_add_res_s1_i[16]\, - \op2[15]\, N814_0, I249_un1_Y, N668_0, - \un6_ex_add_res_s1_i[1]\, \op2[0]\, - \un6_ex_add_res_s1[14]\, \d_i[18]\, \op1_m_0[18]\, - \aluresult_m_0[18]\, N_4042, privileged_inst_5, N_4039, - \tt_0[3]\, \tt_9_1[0]\, \tt_1[2]\, N_4043_i, \tt_1[1]\, - N_16735_tz, \bpdata_i_m_1[5]\, \data_0_1[27]\, - \dco_m_1[123]\, \data_0_m[27]\, \data_0_1[13]\, - \dco_m_0[109]\, \rdata_9_m[8]\, N_51_i, N_51_i_0, - \un6_ex_add_res_s1_i[5]\, \op2[4]\, N678_i, - \un6_ex_add_res_s1[29]\, N_51_i_1, \shiftin_17_m_0[4]\, - \un6_ex_add_res_m[5]\, \pc_1[4]\, I260_un1_Y, - \data_0_1[9]\, \dco_m_0[105]\, \un6_ex_add_res_s1_i[31]\, - \shiftin_17_m_0[9]\, \un6_ex_add_res_m[10]\, N600_1, - N538_1, \un6_ex_add_res_s1_i[2]\, N_448, \un1_iu0_5[90]\, - \logicout_5_0_i_0[24]\, N_447, N_6880_i, N_6832, - \un1_iu0_5[70]\, inst_3_2, \me_nullify2_1_2\, - nullify_1_sqmuxa, wy_1_0_a3_0_4, illegal_inst12, - illegal_inst12_tz_tz, \inst_RNI884O1[22]\, inst_2_0, - \tt_RNO_0[0]\, annul_1tt_N_7, annul_5, branch_RNIA8KSK, - branch_RNIMJA92, N437_1, N440_2, rstate_8_0, d28_0, - un5_op3, logicout19_0, wy_1_0_a3_1, aluresult_2_sqmuxa, - mcasa, d25, N_478, cwp_1_sqmuxa_0, N_3739, N_6681_1, - write, write_3_tz, N_263, ex_bpmiss_1_0_1630_0, N_475, - ex_bpmiss_1_0_a5_6_0, wicc_1, wicc_1_0_a3_0_0, N_143, - \un1_addout_12\, annul_RNIVI35T, \fbranch\, annul_1tt_N_5, - CO1_0_tz, \logicout_5_0_i_0_tz[24]\, un1_illegal_inst11_0, - un1_illegal_inst11_2_0_a5_0, illegal_inst11_0_a5_0, - nobp_RNO_0, N_16827_tz, N_85, inull_RNIFV6VG2_0, - ld_1_sqmuxa, \inst_0_RNIPQUJ[21]\, wy_1_1, N_97, N_3718, - annul_RNIETIP, jmpl_2, \icc_0[0]\, inst_0_2, un1_addout, - \eaddress[31]\, de_inull, nobp_1, un1_reg, N_6322, N_6323, - \rstate_ns[1]\, N_6323s, N_4600, \inst_0[0]\, N_4601, - \inst_0[1]\, N_4602, \inst_0[2]\, N_4603, \inst_0[3]\, - N_4604, \inst_0[4]\, N_4605, N_4607, N_4609, N_4610, - N_4611, N_4612, N_4613, N_4614, N_4615, N_4616, N_4617, - N_4618, N_4619, N_4620, N_4621, N_4623, N_4625, N_4626, - N_4627, N_4628, N_4629, N_4630, N_4631, N361, N362, N364, - N365, N367, N371, N383, N386, N434_1, N498_0, N473_0, - N379, N_44, I170_un1_Y, N596, N604, I184_un1_Y, - ADD_30x30_fast_I218_un1_Y, N443_2, N542, N487_1, N484_1, - N483, I130_un1_Y, N495_1, N550, N476_0, N480, N527_2, - I176_un1_Y, N397_2, N398_2, N400, N422, N419_2, N388, - N391, N467_1, N416_2, N412, N415, N421_2, N425, N427, - N459, N460_0, N463_0, N464_1, I118_un1_Y_i, N538_2, - N479_0, N539, N546_1, N488_1, N547, I134_un1_Y, N499, - N496_2, N554, N555, N523, N530_1, N531, I172_un1_Y, N598, - N606, N471, N472, I110_un1_Y, N475, I114_un1_Y, N534, - \inst_1[31]\, \inst_1[30]\, wreg_6, \rd_1[3]\, N_3764, - \y_2[0]\, \result[0]\, N_4064, \eaddress[21]\, I_20, - N_4049, I_122, N_3768, \y_1[4]\, \result[4]\, N_3769, - \y_1[5]\, \result_0[5]\, \y_2[5]\, \y_2[4]\, \pc_4[3]\, - N_3886, \fe_pc[9]\, \pc_0[9]\, N_4046, N_4052, \fpc[9]\, - \pc_4[9]\, I_38, \inst_0_RNO[31]\, N_3784, \y_2[20]\, y14, - N_3897, \fe_pc[20]\, \pc[20]\, \xc_trap_address[20]\, - \fpc[20]\, \tba[8]\, \aluop_RNIGM3N1[2]\, N_3794, - \y_2[30]\, \result_0[30]\, N_3907, \fe_pc[30]\, \pc[30]\, - N_3789, \y_1[25]\, \result_0[25]\, \y_2[25]\, N_3787, - \y_2[23]\, N_3889, \fe_pc[12]\, \pc[12]\, \bpdata[31]\, - \un3_de_ren1[103]\, \DWACT_ADD_CI_0_partial_sum[0]\, - \un3_de_ren1[104]\, I_13_1, I_14_0, \rd_1[5]\, \rd_2[5]\, - \rd_0[7]\, \rd_1[7]\, \rd_2[7]\, \rd_0[2]\, - \de_raddr1_2[5]\, I_13_2, un26_rs1opt, \de_raddr1_2[6]\, - I_14_1, \de_raddr1_1[5]\, I_13_3, \un3_de_ren1[96]\, - rs1mod, \de_raddr1_1[6]\, I_14_2, \un3_de_ren1[97]\, - error_RNO, error, \rd_1[4]\, \rd_1[6]\, \icc_2[2]\, - N_6357, \de_raddr1_2[4]\, - \DWACT_ADD_CI_0_partial_sum_0[0]\, \de_raddr1_1[4]\, - \DWACT_ADD_CI_0_partial_sum_1[0]\, rett_i, su, s, ps, - \asi[0]\, \inst_1[5]\, \y_1[3]\, \y_2[2]\, \y_2[10]\, - N_3766, \result_0[2]\, N_3771, \y_2[7]\, \result_0[7]\, - N_3770, \y_2[6]\, \result_0[6]\, N_3724, N_3722, N_3723, - \ncwp_3[1]\, N_3726, \wim_1[2]\, \wim_1[6]\, \ncwp_3[2]\, - N_3727, N_3725, \cwp_0[0]\, N_3871, \result_0[1]\, - \cwp_1[1]\, \wim[2]\, \bpdata[15]\, N_3879, \pc[2]\, - \bpdata[28]\, \inst_0_RNIFKEG[25]\, N_4182, - \inst_0_RNO[30]\, illegal_inst35, bp_1_1, wicc_1_0, - wicc_0, un1_ldcheck1, \inst_0_0[21]\, icc_check9_2, - call_hold5, N_33, \DWACT_ADD_CI_0_partial_sum_2[0]\, - un3_reg, N_35, I_13_0, N_37, I_14, nerror_1, - \inst_0_RNO[28]\, \un3_de_ren1[128]\, \un3_de_ren1[129]\, - \un3_de_ren1[130]\, \un3_de_ren1[131]\, - \un3_de_ren1[132]\, \un3_de_ren1[133]\, - \un3_de_ren1[135]\, \un3_de_ren1[136]\, - \un3_de_ren1[137]\, \un3_de_ren1[138]\, - \un3_de_ren1[139]\, \un3_de_ren1[141]\, - \un3_de_ren1[142]\, \un3_de_ren1[143]\, - \un3_de_ren1[144]\, \inst_0[12]\, \un3_de_ren1[145]\, - \un3_de_ren1[146]\, \un3_de_ren1[147]\, - \un3_de_ren1[148]\, \un3_de_ren1[149]\, - \un3_de_ren1[119]\, \un3_de_ren1[120]\, - \un3_de_ren1[121]\, \un3_de_ren1[123]\, - \un3_de_ren1[125]\, \un3_de_ren1[127]\, \cnt_2[0]\, - \rd_2[1]\, \inst_0_RNO[26]\, \inst_0_RNO[27]\, N_4045, - ldbp2_1_RNIL7Q55, \pc_4[2]\, \inst_0_RNO[29]\, - \inst_0_RNO[0]\, \inst_0_RNO[1]\, \inst_0_RNO[2]\, - \inst_0_RNO[3]\, \inst_0_RNO[4]\, \inst_0_RNO[5]\, - \inst_0_RNO[7]\, \inst_0_RNO[9]\, \inst_0_RNO[10]\, - \inst_0_RNO[11]\, \inst_0_RNO[13]\, \inst_0_RNO[14]\, - \inst_0_RNO[15]\, \inst_0_RNO[16]\, \inst_0_RNO[17]\, - \inst_0_RNO[18]\, \inst_0_RNO[19]\, \inst_0_RNO[20]\, - \inst_0_RNO[23]\, \inst_0_RNO[25]\, N_3339, N_375, - \inst_2[27]\, \inst_1[28]\, N_3340, branch_3, branch_7, - N_3341, \inst_2[26]\, N_3343, branch_4, branch_8, - branch_2, branch_6, N_3883, \fe_pc[6]\, \pc_0[6]\, - \xc_trap_address[6]\, N_3885, \fpc[8]\, \fe_pc[8]\, - \pc[8]\, N_3780, \y_2[16]\, \result_0[16]\, \op1[22]\, - \bpdata[6]\, N_3703_i, \pc_RNI8CM4[6]\, \fpc[6]\, N_3908, - \fe_pc[31]\, \pc_0[31]\, \xc_trap_address[31]\, \fpc[31]\, - N_3903, \fe_pc[26]\, \pc_0[26]\, \bpdata[24]\, - \xc_vectt_1[2]\, \bpdata[1]\, N_3894, \fe_pc[17]\, - \pc[17]\, N_4061, \eaddress[18]\, I_98, - \xc_trap_address[17]\, \fpc[17]\, \tba[5]\, N_3898, - \fpc[21]\, \fe_pc[21]\, \pc[21]\, \xc_trap_address[13]\, - \tba[1]\, N_3895, \fpc[18]\, \fe_pc[18]\, \pc[18]\, - \xc_trap_address[12]\, \fpc[12]\, \tba[0]\, N_3906, - \fe_pc[29]\, \pc[29]\, N_3890, \fpc[13]\, N_4074, I_210, - N_4051, I_31, N_4053, I_45, N_3777, \y_2[13]\, - \result_0[13]\, \fe_pc[13]\, \pc[13]\, N_4058, - \eaddress[15]\, I_77, N_4060, \eaddress[17]\, I_91, - N_4056, N_4063, \eaddress[20]\, I_66, I_115, N_4055, - xc_exception_1, \xc_trap_address[18]\, - \xc_trap_address[8]\, \xc_trap_address[15]\, \y_1[9]\, - \y_1[18]\, \y_1[26]\, N_4069, \fpc[26]\, \eaddress[26]\, - I_166, bpmiss_1_i_0, rett_1_1, N_3767, \y_2[3]\, - \result_0[3]\, mulstep_1, N_3772, \y_2[8]\, \result[8]\, - N_3775, \y_2[11]\, \result_0[11]\, N_3779, \y_1[15]\, - \result_0[15]\, \y_2[15]\, N_3781, \y_2[17]\, - \result_0[17]\, wy_3, \y_1[21]\, \y_2[21]\, N_3786, - \y_2[22]\, ex_ymsb_1, \y_1[31]\, \y_2[31]\, N_3776, - \y_2[12]\, \result[12]\, N_3792, \y_2[28]\, - \result_0[28]\, N_3790, \y_2[26]\, \result[26]\, - \result_0[24]\, \y_2[24]\, \y_2[1]\, \result_0[14]\, - \result_0[18]\, \y_2[18]\, \result_0[27]\, \y_2[27]\, - N_483, N_3880, N_3888, \tba[6]\, N_4073, \fpc[30]\, - \pc_4[30]\, I_203, \xc_trap_address[30]\, \fe_pc[11]\, - \pc[11]\, \xc_vectt_1[4]\, \xc_trap_address[11]\, N_3892, - \fpc[15]\, \fe_pc[15]\, \pc[15]\, \tba[3]\, \pc[3]\, - N_3882, \fpc[5]\, \pc_0[5]\, \xc_trap_address[21]\, - \tba[9]\, I_52, N_4054, N_3904, \fe_pc[27]\, \pc_0[27]\, - N_4070, \fpc[27]\, \eaddress[27]\, jump, - \xc_trap_address[27]\, \tba[15]\, \xc_trap_address[26]\, - \tba[18]\, rstate_6314_d, N_6763_i, \pc_RNO[2]\, - \pc_RNO[3]\, \pc_RNO[5]\, \pc_RNO[6]\, \pc_RNO[8]\, - \pc_RNO[9]\, \pc_RNO[10]\, \fpc[10]\, \pc_RNO[11]\, - \fpc[11]\, \pc_RNO[12]\, \pc_RNO[13]\, \pc_RNO[15]\, - \pc_RNO[17]\, \pc_RNO[18]\, \pc_RNO[20]\, \pc_RNO[21]\, - \pc_RNO[26]\, \pc_RNO[27]\, \pc_RNO[29]\, \fpc[29]\, - \pc_RNO[30]\, N_6922_i, inst_5_1, \pc_RNO[14]\, - \xc_trap_address[14]\, \fpc[14]\, \tba[2]\, \fe_pc[14]\, - \pc[14]\, N_3891, I_73, N_4057, \eaddress[14]\, - I62_un1_Y_i, I137_un1_Y_i, I221_un1_Y_0, I183_un1_Y_i, - N468, N_14, N_59, N_11, \pc_RNO[28]\, - \xc_trap_address[28]\, \fpc[28]\, I_186, N_4071, - \fe_pc[28]\, \pc[28]\, N_3905, inst, N_318, N_170, werr, - werr_0, wicc_2, \icco[2]\, N_4187, N_4177, wicc_3, - \icc_16[2]\, \un9_icc_check_bp\, nobp, N_4021, - \un3_de_ren1[122]\, un1_wcwp, \y_2[19]\, N_3783, - \result_0[19]\, \inst_RNIVASI1[30]\, \asi[3]\, - \inst_1[8]\, \asi[1]\, \inst_1[6]\, \un3_de_ren1[126]\, - \ncwp[0]\, \ncwp[2]\, \cwp_0[2]\, N_3344, N_3342, N_3361, - \inst_2[24]\, un10_op, wreg_1_9, wreg_7, N_6350, - xc_wreg_1, N_4624, \rsel1_RNO_0[0]\, \rd_1[2]\, - annul_RNILQG71, ld_2, write_reg_0_sqmuxa_1, - \inst_0_RNO[24]\, \osel[0]\, ldcheck2_0_sqmuxa_1, - ldcheck2_0_sqmuxa, ldcheck1_1_sqmuxa_1, N_518, - \inst_2[31]\, \inst_2[30]\, trap2, trap_0_sqmuxa, - \maddress_0[3]\, \maddress[4]\, trap_0_sqmuxa_6, - tt_0_sqmuxa, tt_1_sqmuxa_1, \tt2[5]\, N_4209, N_4210_i_0, - \tt_1[5]\, \nullify2_0_sqmuxa\, \tt2[3]\, N_4201_i_0, - N_4207, \tt_2[3]\, un6_op, N_6825_i, \inst_0_RNO[22]\, - N_4622, un3_op, rett_1_2, jmpl_3, wreg_1_10, wreg_1_11, - write_reg, un1_ld_1_sqmuxa, annul_next_14, un1_exbpmiss, - wicc_1_1, annul_1_1, \un3_de_ren1[118]\, \pc_RNO[7]\, - I_24, N_4050, hold_pc_0_sqmuxa, \ldlock_3_0\, \ldlock_2\, - ctrl_pv, N_3014, \icc_16[0]\, \icc_3_i_0[0]\, aluadd, - \icc_16[1]\, N_4175, N_4176, N_4185, N_4180, N_4186, - N_4181, \icco[0]\, \icco[1]\, wicc_1_2, icc_0_sqmuxa_0, - pil_0_sqmuxa, \icc_2[0]\, \icc_3[1]\, \icc_2[3]\, - \cnt_RNO[1]\, N_3899, \fe_pc[22]\, \pc[22]\, I_129, - N_4065, \fpc[22]\, \eaddress[22]\, \pc_RNO[22]\, N_3034, - \hold_pc_7\, annul_2_0, N_3033_1_i, \inst_0_RNO[8]\, - N_4608, \xc_trap_address[9]\, \xc_vectt_1[5]\, - \pc_RNO[25]\, \xc_trap_address[25]\, \fpc[25]\, - \fe_pc[25]\, \pc_0[25]\, N_3902, I_156, \inst_0_RNO[6]\, - N_4606, \un3_de_ren1[124]\, \un3_de_ren1[134]\, N_4068, - \eaddress[25]\, N594, I168_un1_Y_i, trap_3, un2_irl, - \rd_3[1]\, \rd_2[2]\, \inst_RNIJ0JA[25]\, \inst_2[28]\, - branch_4_i, branch_8_i, branch_7_i, branch_3_i, - branch_6_i, branch_2_i, N_3348, N_3351, N_3349, N_3350, - N_3346, N_3347, I_9, \pc_4[4]\, N_4047, N_3774, - \result[10]\, \y_2[9]\, et_2_sqmuxa, et_0_sqmuxa, y6_2, - et_1_0, N_3029, et_m, \imm[0]\, intack_3, \inst_3[31]\, - \inst_3[30]\, N_3473, \data_0_2[12]\, \rdata_5[8]\, ld_3, - \maddress_0[1]\, \imm[1]\, \op1[2]\, \imm[2]\, \imm[3]\, - \un1_p0_6[356]\, \imm[4]\, \result_0[4]\, \imm[5]\, - \op1[6]\, \imm[6]\, \imm[7]\, \imm[8]\, \result_0[8]\, - \maddress[9]\, \un1_p0_6[361]\, \imm[9]\, \result[9]\, - \op1[10]\, \imm[10]\, \result_0[10]\, \imm[11]\, - \imm[12]\, \result_0[12]\, \imm[13]\, un14_casaen_s0, - \op1[14]\, \imm[14]\, \op1[15]\, \imm[15]\, \op1[16]\, - \imm[16]\, un14_casaen_s1, \imm[17]\, \op1[18]\, - \imm[18]\, \op1[19]\, \imm[19]\, \op1[20]\, \imm[20]\, - \result_0[20]\, \un1_p0_6[373]\, \imm[21]\, \rsel2[0]\, - \imm[22]\, \op1[23]\, \imm[23]\, \result_0[23]\, - \op1[24]\, \un1_p0_6[376]\, \imm[24]\, \op1[25]\, - \imm[25]\, \imm[26]\, \result_0[26]\, \op1[27]\, - \imm[27]\, \un1_p0_6[380]\, \imm[28]\, \op1[29]\, - \un1_p0_6[381]\, \imm[29]\, \op1[30]\, \imm[30]\, - \op1[31]\, \un1_p0_6[383]\, \imm[31]\, N_4943, N_5246, - mexc_0, N410_0, N536_0, N563, N473_1, N476_1, N516, - N513_0, N512, N579_0, N517, N586, N524_0, N521, N520_0, - N594_0, N532, N529_0, N528_0, N595_1, N533, N602, N540, - N537_0, N603, N571_2, N587_0, I183_un1_Y, N488_2, N415_0, - N478_1, N479_1, N442, N422_0, N439_0, \data_0_2[20]\, - N461, N425_0, N530_2, N577, N448, N449, N454_0, N455_0, - \data_0_0[18]\, I111_un1_Y_i, N464_2, N575_0, N582_1, - N583_0, N446, N424_0, N412_0, N598_0, N599_0, N606_0, - N544_0, ADD_33x33_fast_I246_Y_0_a3, N427_0, N430_0, - N403_0, N406, N451_0, N400_0, N406_0, N410_1, N504, N469, - N528_1, N544_1, N548, N500_1, N497_2, N509, N516_0, - N513_1, N512_0, N594_1, N532_0, N529_1, N595_2, N533_0, - N602_0, N403_1, N415_1, N479_2, N482_0, N537_1, N446_0, - N461_0, N425_1, N458, N514_1, N577_0, N666_1, N413_1, - N451_1, N452_0, N448_0, N574_1, N508, N575_1, N520_1, - N517_0, N583_1, N590_0, N591_0, N598_1, N599_1, N664_1, - N606_1, N607_0, I203_un1_Y, I243_un1_Y_0, N472_0, - I81_un1_Y, N412_1, N540_0, N541_1, N567_2, N536_1, N427_1, - N546_2, N442_0, N_30, N400_1, N410_2, N528_2, N430_1, - N544_2, N406_1, N549, N586_0, N521_0, N524_1, N520_2, - N587_1, N525_0, N594_2, N532_1, N529_2, N533_1, N602_1, - N540_1, N537_2, N536_2, N610_0, N548_0, N545_0, - I151_un1_Y, I205_un1_Y, I245_un1_Y, N415_2, N442_1, - N436_2, N437_2, N425_2, I121_un1_Y, N_53_i, I113_un1_Y_i, - N569_1, N577_1, I197_un1_Y, I204_un1_Y_0, N448_1, N449_0, - N454_1, N455_1, N516_1, N517_1, N452_1, N582_2, N583_2, - N591_1, N599_2, N606_2, N598_2, I203_un1_Y_0, - I243_un1_Y_1, N446_1, N424_1, N412_2, N590_1, - ADD_33x33_fast_I246_Y_0_a3_1, ADD_33x33_fast_I274_Y_0_a3, - N403_2, N507, N_6527, N_4204, \tt_0[0]\, \tt2[0]\, - N_4200_i_0, \laddr[1]\, \size_2[0]\, \size_2[1]\, - \logicout_3[3]\, \logicout_4[3]\, N_3319, N_3562, N_3530, - N_3626, N_3881, \fpc[4]\, \fe_pc[4]\, \pc_0[4]\, - \eaddress[6]\, \xc_trap_address[4]\, \xc_vectt_1[0]\, - \logicout_3[5]\, \logicout_3[6]\, \logicout_4[6]\, N_3324, - N_3532, N_3533, N_3565, N_3629, \wim[5]\, N_4048, - \eaddress[5]\, \eaddress[3]\, \logicout_3[9]\, - \logicout_4[9]\, N_3220, \pc_2[9]\, N_3250, \pc_3[9]\, - \xc_result[9]\, N_3400, N_3536, N_3568, N_3632, N_3773, - \result_0[9]\, \pc_0[20]\, \maddress[19]\, \aop1[2]\, - \aop1[3]\, \aop1[19]\, \eres2[4]\, \eres2[19]\, sari_0, - \maddress[7]\, \maddress[17]\, \maddress[21]\, - \maddress[22]\, \maddress[27]\, \aop1[0]\, \aop1[1]\, - \aop1[5]\, \aop1[6]\, \aop1[7]\, \aop1[15]\, \aop1[16]\, - \aop1[17]\, \aop1[18]\, \aop1[20]\, \aop1[21]\, - \aop1[22]\, \aop1[25]\, \aop1[26]\, N_227, \aop1[27]\, - \aop1[28]\, \aop1[29]\, \aop1[30]\, \eres2[22]\, - \eres2[27]\, \logicout_3[30]\, \logicout_4[30]\, N_3225, - \pc_0[14]\, \pc_1[14]\, N_3255, \pc_2[14]\, - \xc_result[14]\, N_3405, N_3556, N_3557, N_3589, N_3653, - \pc_0[29]\, \eaddress[29]\, \shiftin_17[30]\, - \shiftin_17[29]\, N_4277, \logicout_3[25]\, - \logicout_4[25]\, \logicout_4[26]\, N_3552, N_3553, - N_3584, N_3585, \logicout_3[26]\, N_3648, N_3649, - \pc[24]\, \shiftin_17[25]\, \shiftin_17[24]\, \tba[12]\, - \shiftin_17[26]\, \maddress[25]\, \maddress[26]\, - \aop1[24]\, \eres2[25]\, \eres2[26]\, \shiftin_8[41]\, - \shiftin_5[57]\, \shiftin_5[41]\, \logicout_3[22]\, - \logicout_4[22]\, N_3235, \pc_0[24]\, N_3265, \pc_2[24]\, - \pc_3[24]\, \xc_result[24]\, N_3415, N_3549, N_3581, - N_3645, N_3901, \fe_pc[24]\, N_4269_i, \maddress[23]\, - \maddress[24]\, \aop1[23]\, \eres2[23]\, \eres2[24]\, - \shiftin_5[53]\, \data_0_0[22]\, \logicout_3[0]\, - \logicout_4[0]\, N_3527, N_3559, N_3623, \eaddress[0]\, - \shiftin_17[1]\, aluresult_3_sqmuxa, \cwp_1[0]\, - \shiftin_14[2]\, \shiftin_14[0]\, \shiftin_11[4]\, - \shiftin_11[0]\, \shiftin_8[8]\, \shiftin_8[0]\, - \shiftin_5[16]\, \shiftin_5[0]\, N_3872, \maddress[28]\, - \maddress[30]\, N_4220, wcwp, N_4229, \cwp_1[2]\, - \cwp_1_0[2]\, N_6358, \rd_2[4]\, \rd_2[6]\, - \logicout_3[8]\, \logicout_4[8]\, N_3535, N_3567, N_3631, - et_0_sqmuxa_i, su2, N_4255, N_3221, \pc[10]\, \pc_0[10]\, - N_3251, \pc_2[10]\, \pc_3[10]\, \xc_result[10]\, N_3401, - d13, \maddress[16]\, un14_casaen_s0_0, \maddress[6]\, - \rsel1[2]\, \logicout_3[7]\, \logicout_4[7]\, N_3534, - N_3566, N_3630, \logicout_3[28]\, \logicout_4[28]\, - N_3555, N_3587, N_3651, \maddress[29]\, un14_casaen_s1_0, - \logicout_3[17]\, \logicout_4[17]\, N_3544, N_3576, - N_3640, \wim_1[1]\, \wim_1[5]\, \wim_1[3]\, \wim_1[7]\, - \wim_1[0]\, \wim_1[4]\, N_3870, \cwp_1_0[0]\, \wim[1]\, - \wim[3]\, \wim[6]\, \wim[7]\, \shiftin_17[18]\, - \shiftin_17[17]\, N_4278, \eres2[30]\, \eres2[31]\, - edata_3_sqmuxa, \ex_shcnt_1_i[2]\, N_3218, \pc[7]\, - \pc_0[7]\, N_3248, \pc_2[7]\, \pc_3[7]\, \xc_result[7]\, - N_3398, \eres2[8]\, \eres2[9]\, N_4257, \eres2[15]\, - \eres2[16]\, N_3213, \pc_0[2]\, \pc_2[2]\, N_3243, - \pc_3[2]\, \xc_result[2]\, N_3393, N_4263, \pc_0[17]\, - \eres2[17]\, \eres2[18]\, \pc_0[21]\, \eres2[7]\, - \eres2[0]\, \eres2[5]\, N_3884, \fpc[7]\, \fe_pc[7]\, - N_4276_i, \eres2[13]\, \eres2[14]\, \eres2[29]\, N_3223, - \pc_0[12]\, \pc_2[12]\, N_3253, \pc_3[12]\, - \xc_result[12]\, N_3403, \eres2[28]\, \pc[16]\, - \eres2[6]\, \eres2[11]\, \eres2[12]\, \eres2[21]\, - \data_0_2[7]\, \shiftin_17[6]\, \shiftin_17[9]\, N_6632, - \logicout_3[15]\, \logicout_4[15]\, N_3542, N_3574, - N_3638, \shiftin_11[6]\, \shiftin_11[2]\, \shiftin_8[10]\, - \shiftin_8[2]\, \shiftin_11[10]\, \shiftin_8[18]\, - \shiftin_5[18]\, \shiftin_5[2]\, jmpl_4, N_4254, N_6576, - \shiftin_8[15]\, \shiftin_5[31]\, \shiftin_5[15]\, N_6630, - \un6_ex_add_res_s2[13]\, \un6_ex_add_res_s0[13]\, N_6563, - \un6_ex_add_res_s2[17]\, \un6_ex_add_res_s0[17]\, N_6638, - \un6_ex_add_res_s2[19]\, \un6_ex_add_res_s0[19]\, N_6554, - \un6_ex_add_res_s2[8]\, \un6_ex_add_res_s0[8]\, N_4266, - N_3233, \pc_0[22]\, \pc_2[22]\, N_3263, \pc_3[22]\, - \xc_result[22]\, N_3413, N_4253, \ex_shcnt_1_i[3]\, - N_6658, \shiftin_14[3]\, \shiftin_14[1]\, \shiftin_14[5]\, - \shiftin_17[4]\, \shiftin_14[6]\, \shiftin_14[4]\, - \shiftin_14[7]\, \shiftin_14[8]\, \shiftin_14[9]\, - \shiftin_14[10]\, \shiftin_14[11]\, \shiftin_17[10]\, - \shiftin_14[12]\, \shiftin_14[13]\, \shiftin_14[14]\, - \shiftin_14[15]\, \shiftin_14[16]\, \shiftin_14[17]\, - \shiftin_14[18]\, \shiftin_14[19]\, \shiftin_14[20]\, - \ex_shcnt_1_i[1]\, \shiftin_14[21]\, \shiftin_14[22]\, - \shiftin_14[23]\, \shiftin_14[24]\, \shiftin_14[25]\, - \shiftin_14[26]\, \shiftin_14[27]\, \shiftin_14[28]\, - \shiftin_14[29]\, \shiftin_17[28]\, \shiftin_14[30]\, - \shiftin_14[31]\, \shiftin_14[32]\, \shiftin_11[5]\, - \shiftin_11[1]\, \shiftin_11[7]\, \shiftin_11[3]\, - \shiftin_11[9]\, \shiftin_11[11]\, \shiftin_11[12]\, - \shiftin_11[8]\, \shiftin_11[13]\, \shiftin_11[14]\, - \shiftin_11[15]\, \shiftin_11[16]\, \shiftin_11[17]\, - \shiftin_11[18]\, \shiftin_11[19]\, \shiftin_11[20]\, - \shiftin_11[21]\, \shiftin_11[22]\, \shiftin_11[23]\, - \shiftin_11[24]\, \shiftin_11[25]\, \shiftin_11[26]\, - \shiftin_11[27]\, \shiftin_11[28]\, \shiftin_11[29]\, - \shiftin_11[30]\, \shiftin_11[31]\, \shiftin_11[32]\, - \shiftin_11[33]\, \shiftin_11[34]\, \shiftin_8[9]\, - \shiftin_8[1]\, \shiftin_8[11]\, \shiftin_8[3]\, - \shiftin_8[7]\, \shiftin_8[17]\, \shiftin_8[19]\, - \shiftin_8[23]\, \shiftin_8[25]\, \shiftin_8[27]\, - \shiftin_8[31]\, \shiftin_8[33]\, \shiftin_5[19]\, - \shiftin_5[3]\, \shiftin_5[35]\, \shiftin_8[26]\, - \shiftin_8[35]\, \shiftin_5[17]\, shleft_0_RNIU2BG, - \shiftin_5[23]\, shleft_0_RNIBRBG, \shiftin_5[33]\, - \shiftin_5[39]\, s_RNO, mexc_RNO, \pc_4[24]\, - privileged_inst_1_sqmuxa, un1_privileged_inst_1_sqmuxa, - su_1, \maddress[8]\, \shiftin_14[34]\, \shiftin_11[38]\, - \shiftin_8[38]\, \shiftin_5[54]\, \shiftin_5[38]\, - \xc_trap_address[29]\, \shiftin_5[51]\, \shiftin_8[14]\, - \shiftin_8[6]\, \shiftin_5[22]\, \shiftin_5[6]\, - \shiftin_8[22]\, N_3217, \pc_1[6]\, N_3247, \pc_2[6]\, - \xc_result[6]\, N_3397, N_3219, \pc_0[8]\, \pc_2[8]\, - \xc_result[8]\, N_3249, N_3399, \aop1[8]\, - \shiftin_5[26]\, shleft_0_RNIJ8HP, N_3226, \pc_0[15]\, - \pc_2[15]\, N_3256, \pc_3[15]\, \xc_result[15]\, N_3406, - \maddress[15]\, \aop1[14]\, \logicout_3[16]\, - \logicout_4[16]\, N_3543, \aluop_1[2]\, N_3575, N_3639, - \xc_trap_address[16]\, \tba[4]\, \shiftin_5[47]\, N_4264, - \shiftin_14[33]\, \shiftin_11[37]\, \shiftin_8[45]\, - \shiftin_8[37]\, \shiftin_5[61]\, \shiftin_5[45]\, N_3268, - \pc_2[27]\, \bpdata[27]\, \aop1[10]\, \aop1[11]\, N_3242, - \pc_2[31]\, N_3272, \pc_3[31]\, \xc_result[31]\, N_3422, - \shiftin_8[46]\, \shiftin_5[62]\, \shiftin_5[46]\, - \maddress[14]\, \aop1[12]\, \aop1[13]\, N_3234, \pc[23]\, - \pc_0[23]\, N_3237, \pc_2[26]\, N_3264, \pc_2[23]\, - \pc_3[23]\, N_3267, \pc_3[26]\, \xc_result[23]\, - \xc_result[26]\, N_3414, s_3_sqmuxa, N_3417, - \shiftin_8[12]\, \shiftin_8[4]\, \shiftin_8[13]\, - \shiftin_8[5]\, \shiftin_8[16]\, \shiftin_8[20]\, - \shiftin_8[21]\, \shiftin_8[28]\, \shiftin_8[29]\, - \shiftin_8[30]\, \shiftin_8[34]\, \shiftin_8[36]\, - \shiftin_8[42]\, \shiftin_11[36]\, \shiftin_8[44]\, - \shiftin_5[20]\, shleft_1_RNI5FBG, \shiftin_5[21]\, - shleft_1_RNI9JBG, \shiftin_5[28]\, shleft_1_RNINGHP, - \shiftin_5[34]\, \shiftin_5[36]\, \shiftin_5[37]\, - \shiftin_5[42]\, \shiftin_5[44]\, \shiftin_5[50]\, - \ex_shcnt_1_i[4]\, \shiftin_5[52]\, \shiftin_5[58]\, - \shiftin_5[60]\, ex_sari_1_1, \shiftin_8[24]\, - \shiftin_8[40]\, \shiftin_8[32]\, \shiftin_5[24]\, - shleft_1_RNIDVBG, \shiftin_5[32]\, \shiftin_5[40]\, - \shiftin_5[30]\, \shiftin_5[49]\, \shiftin_5[56]\, shleft, - \pc_0[18]\, \logicout_3[1]\, \logicout_4[1]\, N_3528, - N_3560, N_3624, \aluop_1[0]\, aluresult_0_sqmuxa, N_3224, - \pc_0[13]\, \pc_2[13]\, N_3254, \pc_3[13]\, - \xc_result[13]\, N_3404, \rstate[0]\, N_4260, N_3228, - \pc_2[17]\, N_3258, \pc_3[17]\, \xc_result[17]\, \npc[0]\, - N_3408, N_3230, \pc_0[19]\, N_3260, \pc_2[19]\, - \pc_3[19]\, \xc_result[19]\, N_3410, N_3232, \pc_2[21]\, - N_3262, \pc_3[21]\, \xc_result[21]\, N_3412, N_3785, - \eaddress[12]\, N_3554, N_3586, \logicout_3[27]\, N_4259, - N_3240, \pc_2[29]\, N_3270, \pc_3[29]\, \xc_result[29]\, - N_3420, N_3900, \fe_pc[23]\, \pc_0[3]\, \logicout_3[18]\, - \logicout_4[18]\, N_3545, N_3577, N_3641, N_3215, - \pc_2[4]\, N_3245, \pc_3[4]\, \xc_result[4]\, N_3395, - edata_0_sqmuxa, \pil[0]\, \eaddress[23]\, I_84, - \logicout_3[13]\, \logicout_4[13]\, N_3540, N_3572, - N_3636, I_196, N_4072, N_3893, \fpc[16]\, \fe_pc[16]\, - \pc_0[16]\, N_4066, \fpc[23]\, \logicout_3[14]\, - \logicout_4[14]\, N_3541, N_3573, N_3637, - \logicout_3[21]\, \logicout_4[21]\, N_3548, N_3580, - N_3644, \maddress[11]\, \maddress[12]\, N_4059, - \maddress[13]\, \xc_trap_address[7]\, - \xc_trap_address[10]\, \result_0[0]\, \maddress[1]\, - \logicout_3[2]\, \logicout_4[2]\, N_3529, N_3561, N_3625, - \asi[2]\, \inst_1[7]\, \asi[4]\, \inst_1[9]\, - \logicout_3[31]\, \logicout_4[31]\, N_3558, N_3590, - \aluop_3[1]\, lock_0, annul_all, \logicout_3[11]\, - \logicout_4[11]\, N_3538, N_3570, N_3634, - \logicout_3[19]\, \logicout_4[19]\, N_3546, N_3578, - N_3642, ymsb, N_3795, \result_0[31]\, N_3654, \y_2[14]\, - \maddress[5]\, \result_0[29]\, \y_2[29]\, N_167, - N_266_i_i_0, N_268_i_i_0, N_269_i_i_0, N_270_i_i_0, N_284, - N_285, N_286, N_287, N_288, N_289, N_290, N_291, N_292, - N_293, N_294, N_295, N_296, N_297, N_298, N_299, N_300, - N_301, N_302, N_303, N_304, N_305, N_306, N_307, N_308, - N_309, N_310, N_311, N_312, N_313, N_314, N_315, - xc_vectt14, \eaddress[19]\, lock_1, \xc_vectt_1[3]\, - \eaddress[30]\, N_3322, \xc_vectt_1[6]\, N_3887, N_3227, - \pc_2[16]\, N_3257, \pc_3[16]\, \npc[1]\, \xc_result[16]\, - N_3407, I_105, N_3214, \pc_2[3]\, N_3244, \pc_3[3]\, - \xc_result[3]\, N_3394, N_3896, \fe_pc[19]\, N_3246, - \pc_2[5]\, \eaddress[11]\, \xc_trap_address[23]\, N_3321, - N_3323, I_136, N_4062, \fpc[19]\, \xc_trap_address[19]\, - \logicout_3[12]\, \logicout_4[12]\, N_3239, \pc_0[28]\, - \pc_2[28]\, N_3269, \pc_3[28]\, \xc_result[28]\, N_3419, - N_3539, N_3571, N_3635, N_3236, \pc_2[25]\, N_3266, - \pc_3[25]\, \xc_result[25]\, N_3416, N_6699, N_6747, - \tt_RNO[0]\, \irl[0]\, \pc_RNO[4]\, \pc_RNO[16]\, - \pc_RNO[19]\, \pc_RNO[23]\, N_6866_i, - \un6_ex_add_res_s0_1[17]\, \un6_ex_add_res_s0_1[13]\, - ld_4, N_4268_i, N460_1, \un6_ex_add_res_s0[3]\, - \un6_ex_add_res_s2_1[3]\, \un6_ex_add_res_s2[3]\, N_6642, - \cwp_2[1]\, \un6_ex_add_res_s2_1[8]\, \shiftin_5[55]\, - \shiftin_8[39]\, \aop1[9]\, \maddress[10]\, N_6555, - \eres2[10]\, N575_2, N579_1, N_3402, \xc_result[11]\, - \pc_0[11]\, N_3222, N_3252, \pc_1[11]\, \pc_2[11]\, - N_4258, \data_0_2[11]\, N603_0, N_3633, \logicout_4[10]\, - \shiftin_5_i[14]\, \shiftin_5[13]\, \shiftin_5[29]\, - N_3569, N_3537, \logicout_3[10]\, N427_2, - \un6_ex_add_res_s2_1[16]\, \data_0_2[15]\, N_4262, N_53, - N449_1, N521_1, I183_un1_Y_i_0, N586_1, N579_2, - \un6_ex_add_res_s0[18]\, I239_un1_Y_1, - \un6_ex_add_res_s2_1[18]\, \un6_ex_add_res_s2[18]\, - I239_un1_Y_i, \shiftin_5[48]\, N_6637, N668_1, - I249_un1_Y_0, \un6_ex_add_res_s0[23]\, - \un6_ex_add_res_s2_1[23]\, N_71, N_30_0, - \un6_ex_add_res_s2[23]\, \shiftin_11[35]\, - \shiftin_5[59]\, \shiftin_5[43]\, \shiftin_8[43]\, - \shiftin_5[27]\, N_6570, N_6569, \shiftin_5_i[11]\, - N656_1, N_4252, I245_un1_Y_0, N610_1, I205_un1_Y_0, - N545_1, N549_0, I197_un1_Y_i, I189_un1_Y_i, - \shiftin_5[25]\, \shiftin_5_i[9]\, N_4272, N563_0, N473_2, - N472_1, N472_2, N_3650, \logicout_4[27]\, N_4274, N_3418, - \xc_result[27]\, \pc_3[27]\, N_3238, N_6574, N_4275, - N475_0, N482_1, N485, \un6_ex_add_res_s0[15]\, N_6634, - I173_un1_Y_i, \un6_ex_add_res_s0[32]\, - \un6_ex_add_res_s2_1[32]\, \un6_ex_add_res_s2[32]\, - N_6659, N559, N_6568, \laddr[0]\, \eres2[2]\, \cwp_2[2]\, - N_4261, N_267_i_i_0, N_4265, \pc_0[30]\, N451_2, ps_RNO, - N_4993, \un6_ex_add_res_s0[4]\, \un6_ex_add_res_s2_1[4]\, - \un6_ex_add_res_s2[4]\, \un6_ex_add_res_s2_1[20]\, N_6643, - I247_un1_Y, \eaddress[2]\, \cwp_1_1[0]\, N_4227, N_4218, - N_4273, N476_2, N475_1, N463_1, N466_0, N505_0, - I103_un1_Y, N504_0, N513_2, N509_0, N512_1, N508_0, - N470_0, N469_0, N_4271, invop2, N505_1, N504_1, N470_1, - N469_1, N467_2, N466_1, \un6_ex_add_res_s0[10]\, - \un6_ex_add_res_s2_1[10]\, ADD_33x33_fast_I274_Y_0_a3_0, - \un6_ex_add_res_s2[10]\, N_6629, \un6_ex_add_res_s0[21]\, - \un6_ex_add_res_s2_1[21]\, \un6_ex_add_res_s2[21]\, N786, - N_3628, \logicout_4[5]\, N_6567, N_3564, N455_2, N454_2, - N545_2, N611_0, N610_2, N549_1, \un6_ex_add_res_s0[7]\, - \un6_ex_add_res_s2_1[7]\, N_15_0, \un6_ex_add_res_s2[7]\, - N_4270, N_6646, N463_2, N508_1, N461_1, N458_0, N460_2, - N_71_1, N514_2, N_4267, ldbp2_3, N_3643, \logicout_4[20]\, - \eres2[20]\, \maddress[20]\, N_3579, N_3547, - \logicout_3[20]\, N_3411, \xc_result[20]\, \pc_2[20]\, - N_3231, N_3261, \pc_3[20]\, ldbp1, \rdata_13[8]\, N_3480, - N_3652, \logicout_4[29]\, N_3588, \logicout_3[29]\, - N478_2, \rd_2[3]\, N_6352, \cwp_1_0[1]\, N_4228, N_4219, - \rd_3[2]\, N_3421, \xc_result[30]\, \pc_2[30]\, N_3241, - N_3271, \pc_3[30]\, mexc_1_sqmuxa, SIGNED, SIGNED_0, - \tt2[1]\, N_4205, \tt2[2]\, N_4206, \tt_2[2]\, \tt_2[1]\, - I107_un1_Y_i, N_6654, \un6_ex_add_res_s2[20]\, - \un6_ex_add_res_s0[20]\, N_6631, \un6_ex_add_res_s2[12]\, - \un6_ex_add_res_s0[12]\, \un6_ex_add_res_s2_1[12]\, - N607_1, N_3304, \shcnt[0]\, ADD_33x33_fast_I206_Y_0_a3, - N591_2, N525_1, N590_2, I171_un1_Y_i, N548_1, N400_2, - rett_1_3, N_4, N_6645, \un6_ex_add_res_s2[6]\, - \un6_ex_add_res_s0[6]\, N_6571, \eaddress[24]\, - \pc_RNO[24]\, \fpc[24]\, I_143, N_4067, - \xc_trap_address[24]\, wcwp_0, N_4178, N_4183, N_4188, - \icco[3]\, \maddress[31]\, \aop1_1_i[31]\, \aop1[31]\, - \un1_p0_6[349]\, trap_5, I181_un1_Y_i, - \xc_trap_address[22]\, N_6635, \un6_ex_add_res_s2[16]\, - \un6_ex_add_res_s0[16]\, N_6657, \maddress[18]\, - \un6_ex_add_res_s0[14]\, \un6_ex_add_res_s2[14]\, N_3409, - \xc_result[18]\, \pc_2[18]\, N_3229, N_3259, \pc_3[18]\, - N_6633, \tt_RNO[1]\, \xc_vectt_1[1]\, \irl[1]\, - \xc_trap_address[5]\, N_3320, \pc_3[8]\, \tt_1[0]\, - \tt_2[5]\, \tt2[4]\, N_6625, \un6_ex_add_res_s2[29]\, - \un6_ex_add_res_s0[29]\, \un6_ex_add_res_s2_1[29]\, - \un6_ex_add_res_s0[5]\, \un6_ex_add_res_s2_1[5]\, - \un6_ex_add_res_s2[5]\, ADD_33x33_fast_I206_Y_0_a3_0, - \eaddress[4]\, N_6644, N424_2, \pil[1]\, N_6577, N_4256, - ADD_33x33_fast_I244_un1_Y, \un6_ex_add_res_s0[2]\, - \un6_ex_add_res_s2_1[2]\, \un6_ex_add_res_s2[2]\, N_3646, - \logicout_4[23]\, N_3627, \logicout_4[4]\, N_3396, - \xc_result[5]\, \pc_3[5]\, N_3216, N_246, N_6641, N_3582, - N_3550, \logicout_3[23]\, et_2, N_3563, N_3531, - \logicout_3[4]\, \rfe2\, \rfe1\, \eenaddr\, \rbranch\, - mexc_1, \tt_3[5]\, \su_0\, ld_5, \inst_3[25]\, - \inst_3[26]\, \inst_3[27]\, \inst_3[28]\, \inst_3[29]\, - \tt_2[0]\, \tt_3[1]\, \tt_3[2]\, \tt_5[3]\, \cwp_2[0]\, - \cwp_3[1]\, \cwp_3[2]\, \inst_1[14]\, \inst_1[17]\, - \inst_1[18]\, \wdata[0]\, \wdata[1]\, \wdata[2]\, - \wdata[3]\, \wdata[4]\, \wdata[5]\, \wdata[6]\, - \wdata[7]\, \wdata[8]\, \wdata[9]\, \wdata[10]\, - \wdata[11]\, \wdata[12]\, \wdata[13]\, \wdata[14]\, - \wdata[15]\, \wdata[16]\, \wdata[17]\, \wdata[18]\, - \wdata[19]\, \wdata[20]\, \wdata[21]\, \wdata[22]\, - \wdata[23]\, \wdata[24]\, \wdata[25]\, \wdata[26]\, - \wdata[27]\, \wdata[28]\, \wdata[29]\, \wdata[30]\, - \wdata[31]\, \irl[2]\, \irl[3]\, \size_1[0]\, \size_0[1]\, - \maddress[3]\, \rfa2[0]\, \rfa2[1]\, \rfa2[2]\, \rfa2[3]\, - \rfa2[4]\, \rfa2[5]\, \rfa2[6]\, \rfa2[7]\, \raddr2[7]\, - \rfa1[0]\, \rfa1[1]\, \rfa1[2]\, \rfa1[3]\, \rfa1[4]\, - \rfa1[5]\, \rfa1[6]\, \rfa1[7]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \DWACT_ADD_CI_0_g_array_1_3[0]\, - \DWACT_ADD_CI_0_pog_array_0[0]\, - \DWACT_ADD_CI_0_g_array_0_1[0]\, - \DWACT_ADD_CI_0_partial_sum[2]\, - \DWACT_ADD_CI_0_partial_sum[1]\, N_4_0, - \DWACT_FINC_E[24]\, \DWACT_FINC_E[23]\, - \DWACT_FINC_E[25]\, N_9_0, \DWACT_FINC_E[29]\, - \DWACT_FINC_E[30]\, N_14_0, \DWACT_FINC_E[15]\, - \DWACT_FINC_E[17]\, \DWACT_FINC_E[22]\, N_21, - \DWACT_FINC_E[21]\, \DWACT_FINC_E[9]\, \DWACT_FINC_E[12]\, - \DWACT_FINC_E[20]\, N_30_1, \DWACT_FINC_E[13]\, - \DWACT_FINC_E[19]\, N_35_0, \DWACT_FINC_E[18]\, N_42, - \DWACT_FINC_E[33]\, \DWACT_FINC_E[34]\, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[5]\, N_51, \DWACT_FINC_E[28]\, - \DWACT_FINC_E[16]\, N_56, N_61, \DWACT_FINC_E[14]\, N_66, - N_71_0, \DWACT_FINC_E[10]\, N_78, \DWACT_FINC_E[11]\, - N_83, N_88, N_93, \DWACT_FINC_E[8]\, N_98, N_106, N_113, - \DWACT_FINC_E[3]\, N_121, N_126_0, N_131, - \DWACT_FINC_E[1]\, N_136, N_144, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - wdata(31) <= \wdata[31]\; - wdata(30) <= \wdata[30]\; - wdata(29) <= \wdata[29]\; - wdata(28) <= \wdata[28]\; - wdata(27) <= \wdata[27]\; - wdata(26) <= \wdata[26]\; - wdata(25) <= \wdata[25]\; - wdata(24) <= \wdata[24]\; - wdata(23) <= \wdata[23]\; - wdata(22) <= \wdata[22]\; - wdata(21) <= \wdata[21]\; - wdata(20) <= \wdata[20]\; - wdata(19) <= \wdata[19]\; - wdata(18) <= \wdata[18]\; - wdata(17) <= \wdata[17]\; - wdata(16) <= \wdata[16]\; - wdata(15) <= \wdata[15]\; - wdata(14) <= \wdata[14]\; - wdata(13) <= \wdata[13]\; - wdata(12) <= \wdata[12]\; - wdata(11) <= \wdata[11]\; - wdata(10) <= \wdata[10]\; - wdata(9) <= \wdata[9]\; - wdata(8) <= \wdata[8]\; - wdata(7) <= \wdata[7]\; - wdata(6) <= \wdata[6]\; - wdata(5) <= \wdata[5]\; - wdata(4) <= \wdata[4]\; - wdata(3) <= \wdata[3]\; - wdata(2) <= \wdata[2]\; - wdata(1) <= \wdata[1]\; - wdata(0) <= \wdata[0]\; - size_0_1 <= \size_0[1]\; - size_1_0 <= \size_1[0]\; - rfa2(7) <= \rfa2[7]\; - rfa2(6) <= \rfa2[6]\; - rfa2(5) <= \rfa2[5]\; - rfa2(4) <= \rfa2[4]\; - rfa2(3) <= \rfa2[3]\; - rfa2(2) <= \rfa2[2]\; - rfa2(1) <= \rfa2[1]\; - rfa2(0) <= \rfa2[0]\; - raddr2(7) <= \raddr2[7]\; - rfa1(7) <= \rfa1[7]\; - rfa1(6) <= \rfa1[6]\; - rfa1(5) <= \rfa1[5]\; - rfa1(4) <= \rfa1[4]\; - rfa1(3) <= \rfa1[3]\; - rfa1(2) <= \rfa1[2]\; - rfa1(1) <= \rfa1[1]\; - rfa1(0) <= \rfa1[0]\; - irl(3) <= \irl[3]\; - irl(2) <= \irl[2]\; - irl(1) <= \irl[1]\; - irl(0) <= \irl[0]\; - maddress(31) <= \maddress[31]\; - maddress(30) <= \maddress[30]\; - maddress(29) <= \maddress[29]\; - maddress(28) <= \maddress[28]\; - maddress(27) <= \maddress[27]\; - maddress(26) <= \maddress[26]\; - maddress(25) <= \maddress[25]\; - maddress(24) <= \maddress[24]\; - maddress(23) <= \maddress[23]\; - maddress(22) <= \maddress[22]\; - maddress(21) <= \maddress[21]\; - maddress(20) <= \maddress[20]\; - maddress(19) <= \maddress[19]\; - maddress(18) <= \maddress[18]\; - maddress(17) <= \maddress[17]\; - maddress(16) <= \maddress[16]\; - maddress(15) <= \maddress[15]\; - maddress(14) <= \maddress[14]\; - maddress(13) <= \maddress[13]\; - maddress(12) <= \maddress[12]\; - maddress(11) <= \maddress[11]\; - maddress(10) <= \maddress[10]\; - maddress(9) <= \maddress[9]\; - maddress(8) <= \maddress[8]\; - maddress(7) <= \maddress[7]\; - maddress(6) <= \maddress[6]\; - maddress(5) <= \maddress[5]\; - maddress(4) <= \maddress[4]\; - maddress(3) <= \maddress[3]\; - maddress(2) <= \maddress[2]\; - maddress(1) <= \maddress[1]\; - maddress(0) <= \maddress[0]\; - un1_p0_6_0 <= \un1_p0_6[0]\; - fpc(31) <= \fpc[31]\; - fpc(30) <= \fpc[30]\; - fpc(29) <= \fpc[29]\; - fpc(28) <= \fpc[28]\; - fpc(27) <= \fpc[27]\; - fpc(26) <= \fpc[26]\; - fpc(25) <= \fpc[25]\; - fpc(24) <= \fpc[24]\; - fpc(23) <= \fpc[23]\; - fpc(22) <= \fpc[22]\; - fpc(21) <= \fpc[21]\; - fpc(20) <= \fpc[20]\; - fpc(19) <= \fpc[19]\; - fpc(18) <= \fpc[18]\; - fpc(17) <= \fpc[17]\; - fpc(16) <= \fpc[16]\; - fpc(15) <= \fpc[15]\; - fpc(14) <= \fpc[14]\; - fpc(13) <= \fpc[13]\; - fpc(12) <= \fpc[12]\; - fpc(11) <= \fpc[11]\; - fpc(10) <= \fpc[10]\; - fpc(9) <= \fpc[9]\; - fpc(8) <= \fpc[8]\; - fpc(7) <= \fpc[7]\; - fpc(6) <= \fpc[6]\; - fpc(5) <= \fpc[5]\; - fpc(4) <= \fpc[4]\; - fpc(3) <= \fpc[3]\; - fpc(2) <= \fpc[2]\; - eaddress_4 <= \eaddress[4]\; - eaddress_2 <= \eaddress[2]\; - eaddress_12 <= \eaddress[12]\; - eaddress_24 <= \eaddress[24]\; - eaddress_5 <= \eaddress[5]\; - eaddress_11 <= \eaddress[11]\; - eaddress_30 <= \eaddress[30]\; - eaddress_6 <= \eaddress[6]\; - eaddress_3 <= \eaddress[3]\; - eaddress_27 <= \eaddress[27]\; - eaddress_31 <= \eaddress[31]\; - eaddress_15 <= \eaddress[15]\; - eaddress_17 <= \eaddress[17]\; - eaddress_20 <= \eaddress[20]\; - eaddress_18 <= \eaddress[18]\; - eaddress_26 <= \eaddress[26]\; - eaddress_14 <= \eaddress[14]\; - eaddress_21 <= \eaddress[21]\; - eaddress_25 <= \eaddress[25]\; - eaddress_29 <= \eaddress[29]\; - eaddress_19 <= \eaddress[19]\; - eaddress_23 <= \eaddress[23]\; - eaddress_22 <= \eaddress[22]\; - eaddress_9 <= \eaddress[9]\; - eaddress_10 <= \eaddress[10]\; - eaddress_7 <= \eaddress[7]\; - eaddress_8 <= \eaddress[8]\; - maddress_0_2 <= \maddress_0[3]\; - maddress_0_0 <= \maddress_0[1]\; - eenaddr <= \eenaddr\; - su_0 <= \su_0\; - rfe2 <= \rfe2\; - rfe1 <= \rfe1\; - ldlock_3_0 <= \ldlock_3_0\; - rbranch <= \rbranch\; - un1_addout_12 <= \un1_addout_12\; - ldlock_2 <= \ldlock_2\; - fbranch <= \fbranch\; - hold_pc_7 <= \hold_pc_7\; - nullify2_0_sqmuxa <= \nullify2_0_sqmuxa\; - me_nullify2_1_2 <= \me_nullify2_1_2\; - un9_icc_check_bp <= \un9_icc_check_bp\; - inull <= \inull\; - de_hold_pc_1 <= \de_hold_pc_1\; - un17_casaen_0_0 <= \un17_casaen_0_0\; - xc_exception_1_0 <= \xc_exception_1_0\; - ra_bpmiss_1_0 <= \ra_bpmiss_1_0\; - - \r.e.ctrl.inst[7]\ : DFN1E0 - port map(D => \inst[7]\, CLK => lclk_c, E => holdn, Q => - \inst_1[7]\); - - \r.a.rsel1_0_RNIH7LJ2[2]\ : OR2B - port map(A => data1(27), B => d11_0, Y => \rfo_m[27]\); - - \r.w.s.tba_RNIF5JUN[2]\ : AND2 - port map(A => \aluresult_1_iv_6[14]\, B => - \logicout_m_0[14]\, Y => \aluresult_1_iv_7[14]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I56_Y_i : AO1C - port map(A => \un1_iu0_6[18]\, B => \data_0_0[18]\, C => - N455_0, Y => N_30_0); - - \r.e.op2_RNO_6[10]\ : OR3B - port map(A => d29_0_0, B => \imm[10]\, C => \rsel2_1[0]\, Y - => \imm_m_i[10]\); - - \r.e.ctrl.pc_RNIH8UN2[28]\ : NOR2A - port map(A => \cpi_m[173]\, B => \aluresult_6[31]\, Y => - \aluresult_1_iv_1[28]\); - - \r.e.ctrl.pc[16]\ : DFN1E0 - port map(D => \pc_0[16]\, CLK => lclk_c, E => holdn, Q => - \pc[16]\); - - \r.x.ctrl.pc_RNI9GI61[17]\ : MX2C - port map(A => \un1_p0_6[369]\, B => \pc_2[17]\, S => - s_3_sqmuxa, Y => N_3408); - - \r.m.result_RNIOA753[18]\ : NOR3C - port map(A => \d_iv_0[18]\, B => \result_m_0[18]\, C => - \rfo_m[18]\, Y => \d_iv_2[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I299_Y_0_1 : XOR2 - port map(A => \data_0[8]\, B => \un1_iu0_6[8]\, Y => - \un6_ex_add_res_s2_1[9]\); - - \r.e.op2[21]\ : DFN1E0 - port map(D => N_305, CLK => lclk_c, E => holdn, Q => - \op2[21]\); - - \r.e.ldbp2_RNIQMSNU2\ : OR2A - port map(A => \eaddress[19]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[20]\); - - \r.a.ctrl.inst_RNI013H1[20]\ : OR3A - port map(A => aluop_0_1_0_a5_0, B => N_201, C => inst_9_3, - Y => N_362); - - un6_fe_npc_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_121); - - \r.e.ctrl.rd_RNI3QO53[1]\ : NOR3C - port map(A => un2_rs1_1_7_i_0, B => un2_rs1_1_5_i_0, C => - wreg_2_2, Y => wreg_2_5); - - \r.w.result_RNIMJD4[24]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[24]\, - Y => \result_m_0[24]\); - - \r.e.alucin_RNO_1\ : XAI1 - port map(A => N_220, B => \inst_2[21]\, C => cin_iv_i_a5_0, - Y => N_348); - - \r.x.data_0_RNO_3[8]\ : OR2A - port map(A => data_0_0_24, B => rdata_5_sqmuxa, Y => - \dco_m_0_i[120]\); - - \r.e.op2_RNO[13]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[13]\, Y => N_297); - - \comb.branch_address.tmp_ADD_30x30_fast_I21_G0N\ : NOR2B - port map(A => \un1_p0_6_0[60]\, B => \dpc[23]\, Y => N421_2); - - \r.e.aluop_0_RNIR9EM3[0]\ : MX2C - port map(A => N_3562, B => N_3626, S => \aluop_0[0]\, Y => - \logicout[3]\); - - \r.e.op2_RNO_6[28]\ : OR2B - port map(A => data2(28), B => d25, Y => \rfo_m_i[60]\); - - \r.d.inull_RNIIH9QT\ : OR2 - port map(A => de_hold_pc_1_0, B => holdn, Y => N_6763_i_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I130_Y\ : OR2 - port map(A => N491, B => I130_un1_Y, Y => N550); - - \r.d.pc_RNO[18]\ : MX2 - port map(A => \fpc[18]\, B => \dpc[18]\, S => N_6763_i_0, Y - => \pc_RNO[18]\); - - \r.m.result_RNO[12]\ : MX2 - port map(A => \aluresult[12]\, B => \op1[12]\, S => - un17_casaen_0_2, Y => \eres2[12]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I310_Y_0 : AX1C - port map(A => I271_un1_Y_i, B => ADD_33x33_fast_I271_Y_0_0, - C => ADD_33x33_fast_I310_Y_0_0, Y => - \un6_ex_add_res_s1_i[20]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I273_Y_0 : AO1 - port map(A => ADD_33x33_fast_I273_un1_Y_0_0, B => N653, C - => N652_0, Y => ADD_33x33_fast_I273_Y_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I44_Y : NOR2A - port map(A => N473_1, B => N470_1, Y => N503_0); - - \r.m.y_RNO_2[15]\ : OR2B - port map(A => wy_RNIMKUI, B => \y_2[15]\, Y => \y_m_0[15]\); - - \r.a.rsel1_RNI62UN02[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[3]\, Y - => \aluresult_m_0[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I81_Y : AO13 - port map(A => N412_0, B => \un1_iu0_6[6]\, C => \data_0[6]\, - Y => N540); - - \r.e.shcnt_RNIT5TM5[3]\ : MX2 - port map(A => \shiftin_8[29]\, B => \shiftin_8[21]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[21]\); - - \r.a.ctrl.inst_RNIMS131[31]\ : OR3A - port map(A => N_6681_1, B => \inst[30]\, C => \inst[31]\, Y - => cp_disabled_1_sqmuxa); - - \r.a.bp_RNO\ : NOR2 - port map(A => bp_1_0, B => ctrl_annul_i, Y => bp_1); - - \r.e.op2_RNICBH32[23]\ : AOI1B - port map(A => \un1_iu0_5[89]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[23]\); - - \r.e.jmpl_RNIN50TT\ : OR2B - port map(A => \shiftin_17[26]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[26]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I146_Y_0 : NOR2B - port map(A => N404, B => N407, Y => ADD_33x33_fast_I146_Y_0); - - \r.e.op2_RNO_5[16]\ : AOI1B - port map(A => \result[16]\, B => d31_0, C => \imm_m_i[16]\, - Y => \d_1_iv_0[16]\); - - un6_fe_npc_I_189 : AND3 - port map(A => \fe_pc[26]\, B => \fe_pc[27]\, C => - \fe_pc[28]\, Y => \DWACT_FINC_E[22]\); - - \r.a.imm[1]\ : DFN1E0 - port map(D => \un3_de_ren1[119]\, CLK => lclk_c, E => holdn, - Q => \imm[1]\); - - \r.e.shcnt_RNI98SF5[3]\ : MX2 - port map(A => \shiftin_8[25]\, B => \shiftin_8[17]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[17]\); - - \r.e.op1_RNIGF98B6[22]\ : NOR3C - port map(A => \op1_m_0[22]\, B => \d_iv_2[22]\, C => - \aluresult_m_0[22]\, Y => \d_i[22]\); - - \r.m.y_RNO_4[23]\ : OR2B - port map(A => \y[24]\, B => mulstep_0, Y => \y_m[24]\); - - \r.w.result_RNIQM3C[2]\ : AOI1B - port map(A => \result[2]\, B => d31, C => \imm_m_i[2]\, Y - => \d_1_iv_0[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I6_P0N : OR2A - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, Y => N413_0); - - \r.m.y_RNIGQT25[0]\ : OR3C - port map(A => \y_iv_0_o5_1[0]\, B => \y_iv_0_o5_0[0]\, C - => N_463, Y => \y_1[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I269_un1_Y : OR3C - port map(A => N645, B => N661, C => N676_0, Y => - I269_un1_Y_i); - - \r.e.shcnt_RNIKHVJE[2]\ : MX2 - port map(A => \shiftin_11[35]\, B => \shiftin_11[31]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[31]\); - - \r.e.jmpl_RNISQNAQ\ : OR2B - port map(A => \shiftin_17[18]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[18]\); - - \r.a.ctrl.inst_RNI7C0E[31]\ : OR2B - port map(A => \inst[31]\, B => \inst[30]\, Y => N_212); - - \r.e.invop2_0\ : DFN1E0 - port map(D => N_6680, CLK => lclk_c, E => holdn, Q => - invop2_0); - - \r.e.aluop_0_RNIJ59C6[0]\ : OR2B - port map(A => \logicout[16]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[16]\); - - \r.e.ctrl.pc_RNITIEE6[4]\ : NOR3C - port map(A => \aluresult_1_iv_0[4]\, B => \ex_op2_m[4]\, C - => \aluresult_1_iv_2[4]\, Y => \aluresult_1_iv_3[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I245_un1_Y : NOR2B - port map(A => N676_0, B => N661, Y => I245_un1_Y_0); - - \r.m.ctrl.trap_RNI92KDJ\ : OR3C - port map(A => trap_2_0, B => un1_trap_0_sqmuxa_5, C => - un6_annul_4, Y => un6_annul); - - \r.a.ctrl.pc[28]\ : DFN1E0 - port map(D => \dpc[28]\, CLK => lclk_c, E => holdn, Q => - \pc[28]\); - - \r.w.s.tt_RNIEJP81[4]\ : OR2B - port map(A => \tt[4]\, B => aluresult_12_sqmuxa, Y => - \tt_m[4]\); - - \r.e.ctrl.pc_RNIICUN2[29]\ : NOR2A - port map(A => \cpi_m[174]\, B => \aluresult_6[31]\, Y => - \aluresult_1_iv_1[29]\); - - \r.e.op2_RNO_6[9]\ : OR3B - port map(A => d29_0_0, B => \imm[9]\, C => \rsel2_1[0]\, Y - => \imm_m_i[9]\); - - \r.e.aluop_1_RNI6H393[1]\ : MX2C - port map(A => \logicout_4[19]\, B => N_6913, S => N_6866_i, - Y => N_3642); - - \r.f.pc_RNO_1[10]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[10]\, C => - \xc_trap_address_m[10]\, Y => \pc_1_iv_0[10]\); - - un6_fe_npc_I_149 : AND3 - port map(A => \fe_pc[2]\, B => \fe_pc[3]\, C => \fe_pc[4]\, - Y => \DWACT_FINC_E[34]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I219_un1_Y : OAI1 - port map(A => I179_un1_Y, B => N582, C => N633_1, Y => - I219_un1_Y_i); - - \r.d.inst_0_RNO_0[7]\ : MX2 - port map(A => data_0_0_7, B => \inst_0[7]\, S => - mexc_1_sqmuxa_1_0, Y => N_4607); - - \comb.branch_address.tmp_ADD_30x30_fast_I264_Y_0\ : XNOR2 - port map(A => N556_i, B => ADD_30x30_fast_I264_Y_0_0, Y => - \tmp[6]\); - - \r.m.result_RNIEJD4[26]\ : OR2B - port map(A => d13_0, B => \maddress[26]\, Y => - \result_m_0[26]\); - - \r.e.ctrl.inst_RNIROQF[25]\ : AO1B - port map(A => \inst_1[26]\, B => \inst_2[25]\, C => - \icc_0[2]\, Y => N_248); - - \r.f.pc_RNO_1[8]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[8]\, C => - \xc_trap_address_m[8]\, Y => \pc_1_iv_0[8]\); - - \r.a.ctrl.inst_RNIU43A1[23]\ : OR3A - port map(A => inst_22_0, B => N_271, C => N_241, Y => - inst_22); - - \r.f.pc_RNO_3[28]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[28]\, C => - \xc_trap_address_m[28]\, Y => \pc_1_iv_0[28]\); - - \r.m.result_RNIKO4D3[17]\ : NOR3C - port map(A => \d_iv_0[17]\, B => \result_m_0[17]\, C => - \rfo_m[17]\, Y => \d_iv_2[17]\); - - \r.e.shleft_0_RNI5BBG\ : OR2A - port map(A => \un1_iu0_6[3]\, B => shleft_0, Y => - \shiftin_5[3]\); - - \r.e.op2_RNI1PHG[2]\ : MX2 - port map(A => \op2[2]\, B => N_3306, S => ldbp2_0, Y => - \un1_iu0_5[68]\); - - \r.x.ctrl.trap\ : DFN1E0 - port map(D => trap2, CLK => lclk_c, E => holdn, Q => trap_5); - - \r.m.ctrl.pc[26]\ : DFN1E0 - port map(D => \pc[26]\, CLK => lclk_c, E => holdn, Q => - \pc_3[26]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I148_Y : NOR2B - port map(A => N549_1, B => N545_2, Y => N611_0); - - \r.w.s.dwt_RNI3GVA\ : OR2A - port map(A => werr, B => dwt, Y => werr_1); - - \r.d.inst_0_RNO_0[10]\ : MX2 - port map(A => data_0_0_10, B => \inst_0[10]\, S => - mexc_1_sqmuxa_1_0, Y => N_4610); - - \r.w.s.y[31]\ : DFN1E0 - port map(D => N_3795, CLK => lclk_c, E => N_6922_i, Q => - \y_2[31]\); - - un2_rstn_5 : NOR2 - port map(A => un2_rstn_5_2, B => \un2_rstn_5_0_0\, Y => - \un2_rstn_5\); - - \r.e.ctrl.wicc_RNIOBKQ6G\ : MX2 - port map(A => N_4186, B => N_4176, S => wicc_2, Y => - \icco[1]\); - - \r.a.ctrl.rett_RNO\ : NOR2A - port map(A => N_152, B => N_150, Y => rett_1_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I47_Y_0_a3 : AND2 - port map(A => N463, B => N467_0, Y => N_72); - - un6_ex_add_res_d0_ADD_33x33_fast_I197_Y : OR2A - port map(A => I197_un1_Y_i, B => N600, Y => N666); - - un6_ex_add_res_d1_ADD_33x33_fast_I37_Y : MAJ3 - port map(A => \op2[28]\, B => \un1_iu0_6[28]\, C => N478, Y - => N496); - - un6_ex_add_res_d2_ADD_33x33_fast_I246_Y_0_a3 : NOR2B - port map(A => N808, B => N431_2, Y => - ADD_33x33_fast_I246_Y_0_a3_1); - - \r.m.result_0_RNI05AB4[3]\ : AOI1 - port map(A => un1_trap_0_sqmuxa_0, B => trap_0_sqmuxa, C - => trap63, Y => trap_0_sqmuxa_6); - - un6_ex_add_res_d2_ADD_33x33_fast_I264_un1_Y_0 : AND2 - port map(A => N651, B => N635, Y => - ADD_33x33_fast_I264_un1_Y_0_0); - - \r.w.s.tba_RNI64CA1[5]\ : OR2B - port map(A => \tba[5]\, B => aluresult_12_sqmuxa, Y => - \tba_m[5]\); - - \r.x.data_0_RNO_0[1]\ : NOR3C - port map(A => \data_0_1_1_iv_0[1]\, B => \dco_m_i[121]\, C - => \dco_m_i[113]\, Y => \data_0_1_1_iv_2[1]\); - - \r.e.ctrl.rd_RNINR0HO[6]\ : NOR2 - port map(A => wreg_1, B => wreg_1_8, Y => N_3948); - - \r.w.s.tt[4]\ : DFN1E0 - port map(D => \xc_vectt_1[4]\, CLK => lclk_c, E => N_6747, - Q => \tt[4]\); - - \r.e.op2_RNI5OOH1[24]\ : OR2B - port map(A => \un1_iu0_5[90]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[24]\); - - un6_fe_npc_I_209 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[25]\, Y => N_4_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I171_Y : AOI1 - port map(A => N582, B => N575_1, C => N574_1, Y => N640); - - \r.a.ctrl.inst_RNIFG1L[22]\ : NOR2B - port map(A => \inst[22]\, B => aluop_2_1_0_a2_0, Y => - aluop_2_1_0_a2_1); - - \comb.op_mux.d_1_iv[29]\ : NAND2 - port map(A => \aluresult_m_i[29]\, B => \d_1_iv_4[29]\, Y - => \d_1[29]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I259_un1_Y : OR3C - port map(A => N641_1, B => N625_1, C => N796_1, Y => - I259_un1_Y_1); - - \r.e.invop2_1_RNI3LVB11\ : MX2C - port map(A => \un6_ex_add_res_s2[15]\, B => - \un6_ex_add_res_s0[15]\, S => invop2_1, Y => N_6634); - - \r.a.ctrl.wreg_RNO_1\ : NOR3 - port map(A => un19_rd, B => un1_ld_1_sqmuxa_1_0, C => - write_reg_2_sqmuxa, Y => un1_ld_1_sqmuxa_1); - - \r.w.s.tba_RNIBM524[17]\ : AOI1B - port map(A => \tba[17]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[29]\, Y => \aluresult_1_iv_3[29]\); - - \r.x.ctrl.inst_RNI7O0H2[30]\ : OR2A - port map(A => rst, B => s_2_sqmuxa, Y => et_2_sqmuxa); - - \r.a.ctrl.inst_RNIFVJ8L[23]\ : OA1 - port map(A => N_603, B => illegal_inst_7_iv_8_tz, C => - illegal_inst_7_iv_5, Y => illegal_inst_7_iv_7); - - un6_fe_npc_I_114 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[12]\, Y => N_71_0); - - \r.a.ctrl.rd_RNI1CCC2[5]\ : XNOR2 - port map(A => \un3_de_ren1[104]\, B => \rd_1[5]\, Y => - un1_de_ren1_5_i); - - \r.d.inst_0_RNO[13]\ : NOR2B - port map(A => rst, B => N_4613, Y => \inst_0_RNO[13]\); - - \r.e.op1_RNIE6VM1[11]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[11]\, Y => - \ex_op1_i_m[11]\); - - \r.x.data_0_RNO_3[15]\ : NOR2A - port map(A => \data_0_2[15]\, B => ld_3, Y => - \data_0_m[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I93_Y : AO13 - port map(A => alucin, B => \un1_iu0_6[0]\, C => \data_0[0]\, - Y => N552); - - un6_ex_add_res_d0_ADD_33x33_fast_I6_G0N : NOR3A - port map(A => \op1[5]\, B => ldbp1_3, C => \data_0[5]\, Y - => N412_0); - - \r.e.ctrl.pc_RNI75K11[12]\ : OR2B - port map(A => \pc_2[12]\, B => jmpl_4, Y => \cpi_m[157]\); - - \r.m.dci.lock_RNO_0\ : OR3 - port map(A => N_3749_2, B => N_3749_1, C => N_3749_3, Y => - N_3749); - - \r.d.inst_0_RNO[9]\ : NOR2B - port map(A => rst, B => N_4609, Y => \inst_0_RNO[9]\); - - \r.f.branch_RNIRIA332\ : MX2C - port map(A => rst_RNIINI1H, B => annul_RNIVI35T, S => - branch_RNIA8KSK, Y => \rbranch\); - - un6_ex_add_res_d2_ADD_33x33_fast_I272_Y : OR3B - port map(A => I272_un1_Y_i, B => I237_un1_Y_1, C => N650_1, - Y => N790_1); - - \r.f.pc_RNO_6[28]\ : MX2 - port map(A => \fpc[28]\, B => \eaddress[28]\, S => jump, Y - => N_4071); - - \r.a.rfa2_RNI099O2[5]\ : MX2 - port map(A => \un3_de_ren1[104]\, B => \rfa2[5]\, S => - holdn, Y => raddr2(5)); - - \r.m.y_RNO_4[12]\ : OR2B - port map(A => \y[13]\, B => mulstep_1, Y => \y_m[13]\); - - \r.m.y_RNO_0[8]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[8]\, C => \y_m[8]\, Y - => \y_iv_1[8]\); - - \r.e.op1_RNI2DUH[14]\ : MX2 - port map(A => \op1[14]\, B => \data_0[14]\, S => ldbp1_1, Y - => \un1_iu0_6[14]\); - - \r.d.annul_RNIV849\ : NOR3A - port map(A => un19_inst, B => annul_1, C => call_hold5_0, Y - => branch_1_sqmuxa_i); - - \r.a.ctrl.inst_RNIFG1L[24]\ : OR2A - port map(A => \inst_1[24]\, B => N_202, Y => N_259); - - \comb.branch_address.tmp_ADD_30x30_fast_I0_S_0\ : XOR2 - port map(A => \dpc[2]\, B => \inst_0_RNI0FUM[0]\, Y => - \tmp[2]\); - - un2_rstn_5_0_0_RNI5QOIQ4 : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[8]\, C => - \tmp_m[8]\, Y => \npc_iv_0[8]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I160_un1_Y\ : OR2B - port map(A => N534, B => N527_2, Y => I160_un1_Y_i); - - \r.w.s.pil_RNIJHGH8[0]\ : NOR3C - port map(A => \pil_m[0]\, B => \aluresult_1_iv_0[8]\, C => - \bpdata_m[8]\, Y => \aluresult_1_iv_4[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I79_Y_0 : AO1 - port map(A => N419_1, B => N415_1, C => N418_1, Y => N538_1); - - \r.x.ctrl.wy_RNILI9I\ : OR2 - port map(A => wy_2, B => annul_1_0, Y => y_1_sqmuxa_0); - - \r.d.inst_0_0_0[12]\ : DFN1 - port map(D => \inst_0_0_0_RNI7TVIO2[12]\, CLK => lclk_c, Q - => \un1_p0_6_0[51]\); - - \r.d.pc_RNO[24]\ : MX2 - port map(A => \fpc[24]\, B => \dpc[24]\, S => N_6763_i, Y - => \pc_RNO[24]\); - - \r.a.ctrl.pc_RNIP8M0C[8]\ : MX2 - port map(A => \pc[8]\, B => N_3885, S => ex_bpmiss_1_0, Y - => \fe_pc[8]\); - - \r.e.ldbp2_1_RNIMHAS57\ : OR2B - port map(A => \aluresult_1_iv_9[26]\, B => - \un6_ex_add_res_m[27]\, Y => \aluresult[26]\); - - \r.m.ctrl.inst_RNI211E[22]\ : OR2B - port map(A => \inst_2[22]\, B => \inst_0[24]\, Y => - inst_3_2_1); - - \r.m.y_RNINHBPL[17]\ : NOR3C - port map(A => \aluresult_1_iv_4[17]\, B => \bpdata_m_1[1]\, - C => \logicout_m_0[17]\, Y => \aluresult_1_iv_6[17]\); - - \r.e.aluop_RNIDBCS3[0]\ : MX2C - port map(A => N_3560, B => N_3624, S => \aluop_1[0]\, Y => - \logicout[1]\); - - \r.m.result_RNIVVO1[15]\ : OR2B - port map(A => d13, B => \maddress[15]\, Y => - \result_m_0[15]\); - - \r.w.s.ps\ : DFN1 - port map(D => ps_RNO, CLK => lclk_c, Q => ps); - - \r.x.ctrl.pc_RNIEIA71[28]\ : MX2C - port map(A => \un1_p0_6[380]\, B => \pc_0[28]\, S => - s_3_sqmuxa, Y => N_3419); - - \r.f.pc_RNO_3[14]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[14]\, C => - \xc_trap_address_m[14]\, Y => m7_0); - - \r.e.ctrl.rd_RNI6PSA2[0]\ : XA1A - port map(A => \rd[0]\, B => \rs1_iv_i_0[0]\, C => wreg_2_0, - Y => wreg_2_4); - - \r.a.rsel1_RNIKDB0O2[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[9]\, Y => - \aluresult_m_0[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I218_un1_Y\ : NOR2B - port map(A => N612, B => N597, Y => - ADD_30x30_fast_I218_un1_Y); - - \r.x.ctrl.tt_RNO[4]\ : MX2B - port map(A => \tt_2[3]\, B => un6_annul, S => tt_1_sqmuxa_1, - Y => \tt2[4]\); - - \r.m.y_RNO_0[24]\ : NOR3C - port map(A => N_374, B => N_371, C => \y_iv_0_1[24]\, Y => - \y_iv_0_2[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I1_G0N : NOR3A - port map(A => \op1[0]\, B => ldbp1_0, C => \data_0[0]\, Y - => N397); - - \r.e.ctrl.inst_RNIN01L[20]\ : NOR3B - port map(A => \inst_1[20]\, B => \inst_1[22]\, C => - \inst_0[23]\, Y => aluresult_12_sqmuxa_0); - - \r.e.op2_RNO_3[27]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[27]\, Y => - \aluresult_m_i[27]\); - - \r.e.shleft_1_RNIJEFP1\ : MX2A - port map(A => \shiftin_5[28]\, B => shleft_1_RNINGHP, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[12]\); - - \r.f.pc_RNI3AI9ME[11]\ : AO1A - port map(A => rst, B => \fpc[11]\, C => N_15, Y => N_26); - - \r.a.ctrl.inst_RNI013H1[21]\ : OR3A - port map(A => inst_5_1, B => N_201, C => inst_9_3, Y => - N_360); - - \r.m.y_RNO_0[2]\ : AOI1B - port map(A => wy_1_0, B => \y[2]\, C => \y_m[2]\, Y => - \y_iv_1[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I21_P0N : OR2 - port map(A => \un1_iu0_6[20]\, B => \op2[20]\, Y => N458); - - un6_ex_add_res_d1_ADD_33x33_fast_I180_Y : NOR2A - port map(A => N583_1, B => N591_0, Y => N649_1); - - \r.m.icc_RNI96A3[0]\ : XNOR2 - port map(A => \inst_0[28]\, B => \icc_0[0]\, Y => - branch_6_i); - - \r.e.aluop_RNIJ10O6[0]\ : MX2C - port map(A => N_3571, B => N_3635, S => \aluop_1[0]\, Y => - \logicout[12]\); - - \r.e.aluop_0_RNIJR2T2[1]\ : MX2C - port map(A => \logicout_4[18]\, B => N_6895, S => - N_6866_i_0, Y => N_3641); - - \comb.branch_address.tmp_ADD_30x30_fast_I280_Y_0_0\ : XOR2 - port map(A => \dpc[22]\, B => \inst_0[20]\, Y => - ADD_30x30_fast_I280_Y_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I74_Y\ : NAND2 - port map(A => I74_un1_Y_i, B => N376_i, Y => N491); - - \comb.branch_address.tmp_ADD_30x30_fast_I15_P0N\ : OR2 - port map(A => \inst_0[15]\, B => \dpc[17]\, Y => N404_0); - - \r.e.ctrl.inst_RNI31DJ[26]\ : OR3C - port map(A => N_229, B => \inst_1[26]\, C => N_523, Y => - ex_bpmiss_1_0_a5_4_1); - - \r.d.pc_RNO[11]\ : MX2 - port map(A => \fpc[11]\, B => \dpc[11]\, S => N_6763_i_0, Y - => \pc_RNO[11]\); - - \r.e.op1_RNIBA0C6[15]\ : OR3 - port map(A => \ex_op1_i_m[15]\, B => \op1_i_m[15]\, C => - \bpdata_i_m_2[7]\, Y => \edata2_0_iv_1[15]\); - - \r.a.ctrl.pc[6]\ : DFN1E0 - port map(D => \dpc[6]\, CLK => lclk_c, E => holdn, Q => - \pc_0[6]\); - - \r.m.result_RNI53K83[20]\ : NOR3C - port map(A => \d_iv_0[20]\, B => \result_m_0[20]\, C => - \rfo_m[20]\, Y => \d_iv_2[20]\); - - \r.d.inst_0_RNO_0[19]\ : MX2 - port map(A => data_0_0_19, B => \inst_0[19]\, S => - inull_RNIFV6VG2_0, Y => N_4619); - - un6_ex_add_res_d0_ADD_33x33_fast_I29_P0N : OR3A - port map(A => \data_0[28]\, B => \op1[28]\, C => ldbp1_3, Y - => N482_1); - - \r.e.ldbp2_0_RNIBFPFQ4\ : OR2A - port map(A => \eaddress[29]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[30]\); - - \r.e.jmpl_RNIDN24Q\ : OR2B - port map(A => \shiftin_17[17]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[17]\); - - \r.m.ctrl.pc_RNI62IF[27]\ : MX2 - port map(A => \pc_2[27]\, B => \pc_0[27]\, S => \npc_1[1]\, - Y => N_3268); - - \r.x.ctrl.rd[6]\ : DFN1E0 - port map(D => \rd_1[6]\, CLK => lclk_c, E => holdn, Q => - \rd_2[6]\); - - \r.x.ctrl.pc[8]\ : DFN1E0 - port map(D => \pc_3[8]\, CLK => lclk_c, E => holdn, Q => - \pc_0[8]\); - - \r.m.ctrl.pc[9]\ : DFN1E0 - port map(D => \pc[9]\, CLK => lclk_c, E => holdn, Q => - \pc_3[9]\); - - \r.e.ctrl.pc[15]\ : DFN1E0 - port map(D => \pc[15]\, CLK => lclk_c, E => holdn, Q => - \pc_2[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I160_Y : NOR3A - port map(A => N571_0, B => N497_2, C => N501, Y => N629); - - \r.a.ctrl.inst_RNIFK1L[21]\ : NOR2A - port map(A => \inst_2[21]\, B => N_472, Y => inst_5_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I165_Y\ : NOR2A - port map(A => N531, B => N539, Y => N591); - - \r.d.inst_0_RNO[22]\ : NOR2B - port map(A => rst, B => N_4622, Y => \inst_0_RNO[22]\); - - \r.x.result_RNITEIU5[0]\ : OR2B - port map(A => \bpdata[0]\, B => N_3957, Y => \bpdata_m[0]\); - - \r.a.rsel1_RNI1RFA_2[0]\ : NOR2A - port map(A => N_494, B => un17_casaen_0, Y => - un14_casaen_s0_0_0); - - wovf_exc_0_sqmuxa_RNO : MX2C - port map(A => N_3724, B => N_3727, S => \cwp_0[0]\, Y => - un25_op); - - \r.d.inst_0_RNIDGAF[20]\ : AOI1B - port map(A => ticc_exception_1, B => N_145, C => icc_check9, - Y => un1_icc_check5_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I309_Y_0 : XNOR3 - port map(A => \un1_iu0_6[18]\, B => \op2[18]\, C => N790_0, - Y => \un6_ex_add_res_s1_i[19]\); - - \r.w.s.y_RNO[22]\ : MX2 - port map(A => \y_2[22]\, B => \result_0[22]\, S => N_481_0, - Y => N_3786); - - un6_ex_add_res_d1_ADD_33x33_fast_I4_G0N : NOR2B - port map(A => \un1_iu0_6[3]\, B => \op2[3]\, Y => N406_0); - - \r.w.s.tba[17]\ : DFN1E1 - port map(D => \result_0[29]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[17]\); - - \r.e.op2[6]\ : DFN1E0 - port map(D => N_290, CLK => lclk_c, E => holdn, Q => - \op2[6]\); - - \r.m.icc_RNO_15[2]\ : NOR3A - port map(A => icc_0_sqmuxa_1_2, B => \logicout[6]\, C => - \logicout[5]\, Y => icc_0_sqmuxa_1_17); - - \r.d.inst_0_RNI0FUM[0]\ : NOR2B - port map(A => \inst_0[0]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI0FUM[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_Y_0 : AO1 - port map(A => N576_0, B => N569_0, C => N568_0, Y => - ADD_33x33_fast_I264_Y_0_0); - - \r.f.pc_RNIM5HB4[20]\ : MX2 - port map(A => \dpc[20]\, B => \fpc[20]\, S => - \ra_bpmiss_1_0\, Y => N_3897); - - un6_ex_add_res_d2_ADD_33x33_fast_I130_Y : NOR2A - port map(A => N527_1, B => ADD_33x33_fast_I130_Y_0_1, Y => - N593_1); - - \r.f.pc_RNO_1[29]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[29]\, C => - \pc_1_iv_0[29]\, Y => \pc_1_iv_1[29]\); - - \r.x.result_RNI1RIU5[1]\ : OR2B - port map(A => \bpdata[1]\, B => N_3957, Y => \bpdata_m[1]\); - - \r.f.pc_RNO[24]\ : OR3C - port map(A => \tmp_m[24]\, B => \pc_1_iv_1[24]\, C => - \un6_fe_npc_m[22]\, Y => \pc_1[24]\); - - \r.e.op1_RNIBP2B2[10]\ : AO1A - port map(A => \un1_iu0_6[10]\, B => edata_3_sqmuxa_0, C => - \op1_i_m[10]\, Y => \edata2_0_iv_0[10]\); - - \r.d.inst_0_RNI2423[13]\ : OR2B - port map(A => \inst_0[31]\, B => \inst_0[13]\, Y => N_126); - - un6_ex_add_res_d2_ADD_33x33_fast_I113_un1_Y : OR3B - port map(A => N458_0, B => N461_1, C => N514_2, Y => - I113_un1_Y_i); - - \r.e.shleft_0_RNIL7CQ1\ : MX2C - port map(A => \shiftin_5[19]\, B => \shiftin_5[3]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[3]\); - - \r.x.data_0_RNO_1[6]\ : NOR3C - port map(A => \dco_m_i[110]\, B => \data_0_m_i[6]\, C => - \dco_m_i[126]\, Y => \data_0_1_1_iv_1[6]\); - - \r.x.ctrl.tt_RNI9PVQ[2]\ : MX2 - port map(A => \result_0[2]\, B => \tt[2]\, S => tt_i, Y => - N_3321); - - \r.f.pc_RNO_1[16]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[16]\, C => - \pc_1_iv_0[16]\, Y => \pc_1_iv_1[16]\); - - \r.x.data_0_RNO_0[24]\ : NOR3B - port map(A => \data_0_m_i[24]\, B => \dco_m_1_i[120]\, C - => \rdata_5_m_9[8]\, Y => \data_0_1_1_iv_1[24]\); - - \r.w.s.ps_RNIJK089\ : NOR3C - port map(A => \aluresult_1_iv_1[6]\, B => ps_m_0, C => - \aluresult_1_iv_4[6]\, Y => \aluresult_1_iv_5[6]\); - - \r.m.y_RNO_2[20]\ : OR2A - port map(A => \logicout[20]\, B => y14, Y => - \logicout_m[20]\); - - \r.f.pc_RNO_6[13]\ : MX2 - port map(A => \fpc[13]\, B => \eaddress[13]\, S => jump_0, - Y => N_4056); - - \r.m.result_RNO[15]\ : MX2 - port map(A => \aluresult[15]\, B => \op1[15]\, S => - un17_casaen_0_1, Y => \eres2[15]\); - - \r.m.irqen2_RNISH4E3\ : NOR3B - port map(A => un3_irl, B => un6_annul_2, C => annul_RNIPFOQ, - Y => un6_annul_4); - - \r.e.op2_RNO_7[18]\ : OR3C - port map(A => d28_0, B => \rsel2_1[0]\, C => - \un1_p0_6[370]\, Y => \cpi_m_i[370]\); - - \r.m.y_RNO[26]\ : AO1C - port map(A => y14_0, B => \logicout[26]\, C => \y_iv_2[26]\, - Y => \y_0[26]\); - - \r.x.data_0_RNO[30]\ : OR3 - port map(A => \dco_m_1[126]\, B => \data_0_m[30]\, C => - \data_0_1_4[18]\, Y => \data_0_1[30]\); - - \r.m.icc_RNILOP8[1]\ : NOR2B - port map(A => \icc[1]\, B => \inst_0[24]\, Y => - trap_0_sqmuxa_2_1); - - \comb.lock_gen.ldchkra_RNITJNF\ : AND2 - port map(A => ldchkra, B => ldlock2_0, Y => ldlock2_1); - - \r.m.y_RNIT52T5[12]\ : NOR3C - port map(A => \aluresult_1_iv_1[12]\, B => - \aluresult_1_iv_0[12]\, C => \tba_m[0]\, Y => - \aluresult_1_iv_3[12]\); - - \r.f.pc_RNO_1[5]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[5]\, C => - \xc_trap_address_m[5]\, Y => \pc_1_iv_0[5]\); - - \r.x.result_RNINC6E[15]\ : MX2 - port map(A => \result_0[15]\, B => \data_0_2[15]\, S => - ld_4, Y => \un1_p0_6[367]\); - - \r.x.data_0_RNO_0[23]\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_14, B => mcdo_m_0_21, C => - rdata_6_sqmuxa, Y => \dco_m_0[119]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I205_Y : AO1 - port map(A => N611_0, B => N552_0, C => N610_2, Y => N676_1); - - \r.m.dci.lock_RNI09G7\ : NOR2A - port map(A => lock_0, B => annul_5, Y => lock); - - \r.e.jmpl_RNID6FUG1\ : AOI1B - port map(A => \shiftin_17[19]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[18]\, Y => \aluresult_1_iv_7[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I111_Y : AO1 - port map(A => N512_1, B => N509_0, C => N508_0, Y => N574_0); - - \r.d.pc_RNO[26]\ : MX2 - port map(A => \fpc[26]\, B => \dpc[26]\, S => N_6763_i, Y - => \pc_RNO[26]\); - - \r.x.data_0_RNO_0[18]\ : AOI1B - port map(A => rdatav_0_1_0_iv_5_0, B => mcdo_m_0_16, C => - rdata_6_sqmuxa, Y => \dco_m_0[114]\); - - \r.e.op2_RNO_2[31]\ : NOR3C - port map(A => \d_1_iv_1[31]\, B => \d_1_iv_0[31]\, C => - \rfo_m_i[63]\, Y => \d_1_iv_3[31]\); - - \comb.un6_xc_exception_RNI1M3D\ : NAND2 - port map(A => un6_xc_exception, B => - \xc_trap_address_m_0[2]\, Y => \xc_trap_address_m[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I322_Y_0 : AX1E - port map(A => I259_un1_Y_0, B => ADD_33x33_fast_I259_Y_3_0, - C => \un6_ex_add_res_s2_1[32]\, Y => - \un6_ex_add_res_s2[32]\); - - \r.m.y_RNI5QAV2[28]\ : AOI1B - port map(A => \y[28]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[28]\, Y => \aluresult_1_iv_0[28]\); - - \r.w.result_RNI6MDI[14]\ : AOI1B - port map(A => \un1_p0_6[366]\, B => d14_0, C => - \result_m_0_0[14]\, Y => \d_iv_0[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I106_Y\ : AO1 - port map(A => N471, B => N468, C => N467_1, Y => N526); - - \r.e.ctrl.pc_RNINMOI4[19]\ : NOR3C - port map(A => \ex_op2_m[19]\, B => aluresult_8_sqmuxa_i, C - => \aluresult_1_iv_1[19]\, Y => \aluresult_1_iv_2[19]\); - - \r.d.pc_RNO[20]\ : MX2 - port map(A => \fpc[20]\, B => \dpc[20]\, S => N_6763_i_0, Y - => \pc_RNO[20]\); - - \r.e.shleft_RNIPG831\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[2]\, S => shleft, - Y => \shiftin_5[33]\); - - \r.f.pc[13]\ : DFN1E0 - port map(D => \pc_1[13]\, CLK => lclk_c, E => holdn, Q => - \fpc[13]\); - - \r.a.imm[20]\ : DFN1E0 - port map(D => \un3_de_ren1[138]\, CLK => lclk_c, E => holdn, - Q => \imm[20]\); - - \r.w.s.y_RNO[30]\ : MX2 - port map(A => \y_2[30]\, B => \result_0[30]\, S => N_481_0, - Y => N_3794); - - \comb.v.x.data_0_1_1_iv_RNO[19]\ : OR2 - port map(A => \data_0_1_1[16]\, B => \data_0_1_1_iv_0[19]\, - Y => \data_0_1_1_iv_1[19]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I7_G0N\ : NOR2B - port map(A => \inst_0[7]\, B => \dpc[9]\, Y => N379); - - \r.e.shleft_0_RNI455I1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[30]\, S => - shleft_0, Y => \shiftin_5[61]\); - - \r.e.ctrl.inst[6]\ : DFN1E0 - port map(D => \inst[6]\, CLK => lclk_c, E => holdn, Q => - \inst_1[6]\); - - \r.a.imm_RNO[23]\ : MX2 - port map(A => \inst_0[13]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[141]\); - - \r.d.cwp[0]\ : DFN1E0 - port map(D => \cwp_1_1[0]\, CLK => lclk_c, E => holdn, Q - => \cwp_0[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I19_G0N : NOR2B - port map(A => \un1_iu0_6[18]\, B => \op2[18]\, Y => N451_1); - - \r.x.data_0[27]\ : DFN1E0 - port map(D => \data_0_1[27]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[27]\); - - \r.f.pc_RNO_1[30]\ : NOR3C - port map(A => \pc_4_m[30]\, B => \xc_trap_address_m[30]\, C - => \un6_ex_add_res_m_1[31]\, Y => \pc_1_iv_1[30]\); - - \r.m.y_RNO_4[24]\ : OR3A - port map(A => \y_2[24]\, B => wy_3, C => wy_1_0_1, Y => - N_372); - - \r.e.invop2_RNIOFG59\ : MX2 - port map(A => \un6_ex_add_res_s2[7]\, B => - \un6_ex_add_res_s0[7]\, S => invop2, Y => N_6646); - - un6_ex_add_res_d0_ADD_33x33_fast_I267_Y : NAND2 - port map(A => I267_un1_Y_0, B => ADD_33x33_fast_I267_Y_0_0, - Y => N780); - - \r.d.inst_0[27]\ : DFN1 - port map(D => \inst_0_RNO[27]\, CLK => lclk_c, Q => - \inst_0[27]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I106_Y : NOR2A - port map(A => N503_0, B => N_15_0, Y => N569_0); - - \r.a.ctrl.inst[24]\ : DFN1E0 - port map(D => \inst_0_0[24]\, CLK => lclk_c, E => holdn, Q - => \inst_1[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I182_Y : NOR2B - port map(A => N593, B => N585, Y => N651_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I54_Y : OA1A - port map(A => \data_0_2[20]\, B => \un1_iu0_6[20]\, C => - N455_0, Y => N513_0); - - \r.e.ctrl.annul_RNIDR5HD1\ : OR2A - port map(A => un12_de_hold_pc, B => \de_hold_pc_1\, Y => - un2_rstn_5_2); - - \r.x.result_RNIJ22O3[16]\ : MX2 - port map(A => \un1_iu0_6[16]\, B => \un1_p0_6[368]\, S => - bpdata6_0_0, Y => \bpdata[16]\); - - \r.e.aluop_RNIUDI14[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[3]\, Y => - \bpdata_i_m_2[3]\); - - \r.x.y[11]\ : DFN1E0 - port map(D => \y_0[11]\, CLK => lclk_c, E => holdn, Q => - \y_2[11]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I111_un1_Y : OR3C - port map(A => N461, B => N464_2, C => N512, Y => - I111_un1_Y_i); - - \r.m.ctrl.pc[25]\ : DFN1E0 - port map(D => \pc[25]\, CLK => lclk_c, E => holdn, Q => - \pc_3[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0\ : OR3C - port map(A => N_41, B => ADD_30x30_fast_I233_Y_0_0, C => - N_39_0, Y => N696); - - \r.m.ctrl.inst[22]\ : DFN1E0 - port map(D => \inst_1[22]\, CLK => lclk_c, E => holdn, Q - => \inst_2[22]\); - - \r.e.shcnt_RNIFVKOC[2]\ : MX2C - port map(A => \shiftin_11[23]\, B => \shiftin_11[19]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[19]\); - - \r.e.aluop_RNIOBIJ1[2]\ : XA1 - port map(A => \un1_iu0_5[97]\, B => \aluop_1[2]\, C => - \un1_iu0_6[31]\, Y => N_3558); - - \comb.branch_address.tmp_ADD_30x30_fast_I218_Y\ : NOR2 - port map(A => N596, B => ADD_30x30_fast_I218_un1_Y, Y => - N726_i); - - \r.x.rstate_RNIK4IR1[0]\ : MX2C - port map(A => N_3394, B => \xc_result[3]\, S => \rstate[0]\, - Y => \wdata[3]\); - - \r.e.op1_RNIR6CR1[23]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[23]\, Y => - \ex_op1_i_m[23]\); - - \r.f.pc_RNO_5[29]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[29]\, Y => \xc_trap_address_m[29]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I188_Y : NOR2 - port map(A => N599_0, B => N591_2, Y => N657_1); - - \r.x.ctrl.pc_RNIQRH61[12]\ : MX2C - port map(A => \un1_p0_6[364]\, B => \pc_0[12]\, S => - s_3_sqmuxa_0, Y => N_3403); - - \comb.branch_address.tmp_ADD_30x30_fast_I103_Y\ : NOR2B - port map(A => N468, B => N464_1, Y => N523); - - \r.f.pc_RNO_7[24]\ : MX2 - port map(A => \fpc[24]\, B => \tba[12]\, S => rstate_6314_d, - Y => \xc_trap_address[24]\); - - \r.f.pc_RNO_3[21]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[21]\, C => - \xc_trap_address_m[21]\, Y => \pc_1_iv_0[21]\); - - \r.e.alucin_RNO_0\ : NOR3C - port map(A => alucin_RNO_2, B => N_350, C => cin_iv_i_0, Y - => cin_iv_i_2); - - \r.x.data_0_RNO_1[2]\ : OA1A - port map(A => data_0_0_26, B => rdata_0_sqmuxa, C => - \data_0_1_1_iv_0[2]\, Y => \data_0_1_1_iv_1[2]\); - - \r.e.op2_RNO_7[25]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[377]\, - Y => \cpi_m_i[377]\); - - \r.x.result[0]\ : DFN1E0 - port map(D => \maddress[0]\, CLK => lclk_c, E => holdn, Q - => \result[0]\); - - \r.x.dci.size_RNIFJHJI[1]\ : NOR2B - port map(A => ld_3, B => \me_size_1[1]\, Y => - rdata_6_sqmuxa); - - \r.x.result_RNIRKP65[0]\ : OR2B - port map(A => \bpdata[0]\, B => N_3957_1, Y => - \bpdata_m_1[0]\); - - \r.e.op2_RNIVFMB1_0[22]\ : OR2 - port map(A => \un1_iu0_6[22]\, B => \un1_iu0_5[88]\, Y => - \logicout_3[22]\); - - \r.m.result_RNICFD4[17]\ : OR2B - port map(A => d13_0, B => \maddress[17]\, Y => - \result_m_0[17]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I279_Y_0\ : XOR2 - port map(A => N714, B => ADD_30x30_fast_I279_Y_0_0, Y => - \tmp[21]\); - - \r.x.result_RNIHN5B[4]\ : OR2B - port map(A => \un1_p0_6[356]\, B => d14, Y => - \cpi_m_0[356]\); - - \r.w.s.icc_RNO_1[1]\ : OR2B - port map(A => icc_0_sqmuxa, B => \icc_3[1]\, Y => - \icc_m_0[1]\); - - \r.e.ctrl.rd_RNISJ8T9[4]\ : NOR3C - port map(A => un1_de_ren1_4_i_0, B => wreg_1_4, C => - un1_de_ren1_5_i_0, Y => wreg_1_6); - - \r.w.s.y[22]\ : DFN1E0 - port map(D => N_3786, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[22]\); - - \comb.v.x.data_0_1_1_iv[16]\ : OR2 - port map(A => \data_0_1_2[17]\, B => \data_0_1_1_iv_1[16]\, - Y => \data_0_1[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I168_Y : NOR2B - port map(A => N579_0, B => N571_2, Y => N637_1); - - \r.x.ctrl.inst_RNI0MFG[24]\ : OR2A - port map(A => \inst_2[24]\, B => \rstate_d[2]\, Y => - tba_1_sqmuxa_3); - - \r.e.op2_RNI7C9P[1]\ : OR2A - port map(A => \op2_RNI1LHG[1]\, B => \un1_iu0_6[1]\, Y => - \logicout_4[1]\); - - \r.e.aluop_RNIKJC91[2]\ : XA1 - port map(A => \un1_iu0_5[86]\, B => \aluop_1[2]\, C => - \un1_iu0_6[20]\, Y => N_3547); - - \r.d.pv_RNI36O874\ : OR3C - port map(A => un2_exbpmiss, B => - un1_annul_next_1_sqmuxa_3_3, C => annul_next_2_sqmuxa_1_8, - Y => un1_annul_next_1_sqmuxa_3); - - wovf_exc_0_sqmuxa_RNO_3 : MX2 - port map(A => \wim_1[3]\, B => \wim_1[7]\, S => \ncwp_3[2]\, - Y => N_3723); - - un6_ex_add_res_d1_ADD_33x33_fast_I239_un1_Y : NOR2B - port map(A => N668, B => N653, Y => I239_un1_Y_0); - - \r.e.op2_RNIM3HN1[13]\ : OR2B - port map(A => \un1_iu0_5[79]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[13]\); - - \r.e.ldbp2_1_RNI7QDSS2\ : OR2A - port map(A => \eaddress[18]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[19]\); - - \r.e.op1_RNINQ8G[12]\ : OR2B - port map(A => \op1[12]\, B => un14_casaen_s1_0, Y => - \op1_m_0[12]\); - - \r.m.result[28]\ : DFN1E0 - port map(D => \eres2[28]\, CLK => lclk_c, E => holdn, Q => - \maddress[28]\); - - \comb.cwp_ctrl.ncwp_3_I_14\ : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[2]\, B => - \DWACT_ADD_CI_0_g_array_1_3[0]\, Y => \ncwp_3[2]\); - - \r.e.shcnt_RNIL4ER8[2]\ : MX2C - port map(A => \shiftin_11[4]\, B => \shiftin_11[0]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[0]\); - - \r.e.op2_RNO_1[17]\ : OR2B - port map(A => \op1[17]\, B => un14_casaen_s1, Y => - \op1_m_i[17]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I71_Y_0 : AO1 - port map(A => N431_0, B => N427_0, C => N430_0, Y => N530_2); - - \r.w.s.icc_RNO_0[0]\ : AOI1B - port map(A => icc_2_sqmuxa, B => \result[20]\, C => - \icc_m_0[0]\, Y => \icc_1_iv_0[0]\); - - \r.e.shcnt_RNO[1]\ : XOR2 - port map(A => \d_1[1]\, B => N_208, Y => N_267_i_i_0); - - un9_ra_I_14 : XOR2 - port map(A => \cwp_0[2]\, B => - \DWACT_ADD_CI_0_g_array_1_2[0]\, Y => I_14_2); - - \r.x.data_0[1]\ : DFN1E0 - port map(D => \data_0_1[1]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[1]\); - - \r.d.inst_0_RNO_0[31]\ : MX2 - port map(A => data_0_2_31, B => \inst_0[31]\, S => - inull_RNIFV6VG2_0, Y => N_4631); - - un6_ex_add_res_d2_ADD_33x33_fast_I24_G0N : NOR2B - port map(A => \un1_iu0_6[23]\, B => \data_0[23]\, Y => - N466_0); - - \r.x.result_RNIQMED[14]\ : MX2 - port map(A => \result_0[14]\, B => \data_0[14]\, S => ld_0, - Y => \un1_p0_6[366]\); - - \r.w.s.y_RNO[29]\ : NOR3 - port map(A => N_413, B => N_412, C => N_414, Y => N_174); - - \r.a.ctrl.inst[27]\ : DFN1E0 - port map(D => \inst_0[27]\, CLK => lclk_c, E => holdn, Q - => \inst_2[27]\); - - \r.f.branch\ : DFN1E0 - port map(D => \rbranch\, CLK => lclk_c, E => holdn, Q => - \fbranch\); - - \r.x.mexc_RNIQ5MM\ : NOR2 - port map(A => mexc_0, B => tt_i, Y => xc_vectt14); - - \comb.branch_address.tmp_ADD_30x30_fast_I161_Y\ : NOR3C - port map(A => N476_0, B => N480, C => N527_2, Y => N587); - - \comb.branch_address.tmp_ADD_30x30_fast_I117_Y\ : OR2B - port map(A => ADD_30x30_fast_I117_Y_0, B => N478_0, Y => - N537); - - un6_ex_add_res_d1_ADD_33x33_fast_I293_Y_0 : XNOR2 - port map(A => ADD_33x33_fast_I293_Y_0_0, B => N616_0, Y => - \un6_ex_add_res_s1_i[3]\); - - \r.e.aluop_2_RNI84413[1]\ : MX2C - port map(A => N_3548, B => \logicout_3[21]\, S => - \aluop_2[1]\, Y => N_3580); - - \r.e.op1_RNIGBO8[6]\ : MX2 - port map(A => \op1[6]\, B => \data_0[6]\, S => ldbp1_1, Y - => \un1_iu0_6[6]\); - - \r.x.rstate_0_RNIOG082[0]\ : MX2C - port map(A => N_3397, B => \xc_result[6]\, S => - \rstate_0[0]\, Y => \wdata[6]\); - - \r.d.annul_RNICD012\ : AOI1 - port map(A => bicc_hold_3, B => N_3718, C => annul_RNIETIP, - Y => \ldlock_3_0\); - - \r.e.op2_RNO_6[7]\ : OR2B - port map(A => data2(7), B => d25_0, Y => \rfo_m_i[39]\); - - \r.e.op2_RNIH5402[8]\ : AOI1B - port map(A => \un1_iu0_5[74]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[8]\); - - \r.a.ctrl.inst_RNIFG1L[23]\ : OR2A - port map(A => \inst_1[23]\, B => inst_9_3, Y => N_515); - - \r.m.y_RNITHO71[25]\ : OR2B - port map(A => \y_2[25]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[25]\); - - \r.f.pc_RNO_6[21]\ : MX2 - port map(A => \fpc[21]\, B => \eaddress[21]\, S => jump_0, - Y => N_4064); - - \r.w.s.y_RNO_0[29]\ : NOR2A - port map(A => N_481, B => \result_0[29]\, Y => N_413); - - \r.e.op1_RNIP29G[14]\ : OR2B - port map(A => \op1[14]\, B => un14_casaen_s1_0, Y => - \op1_m_0[14]\); - - un2_rstn_5_RNI87L95 : NAND2 - port map(A => \tmp[6]\, B => \un2_rstn_5\, Y => N_39); - - \r.e.shcnt_RNO[0]\ : XOR2 - port map(A => \d_1[0]\, B => N_208, Y => N_266_i_i_0); - - \r.x.result_RNI08LA[8]\ : MX2 - port map(A => \result[8]\, B => \data_0[8]\, S => ld_0, Y - => \un1_p0_6[360]\); - - \r.w.s.tba_RNII1TPG[10]\ : NOR3C - port map(A => \aluresult_1_iv_4[22]\, B => - \aluresult_1_iv_3[22]\, C => \bpdata_m_1[6]\, Y => - \aluresult_1_iv_6[22]\); - - \r.m.ctrl.pc[30]\ : DFN1E0 - port map(D => \pc_0[30]\, CLK => lclk_c, E => holdn, Q => - \pc_3[30]\); - - \r.e.shcnt_RNI5072V[1]\ : MX2 - port map(A => \shiftin_14[33]\, B => \shiftin_14[31]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[31]\); - - \r.x.data_0_RNO_2[17]\ : NOR2A - port map(A => \data_0[17]\, B => ld_0_0, Y => - \data_0_m[17]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I54_Y\ : MAJ3 - port map(A => \dpc[18]\, B => \inst_0[16]\, C => N403, Y - => N471); - - un6_ex_add_res_d1_ADD_33x33_fast_I73_Y : MAJ3 - port map(A => \op2[10]\, B => \un1_iu0_6[10]\, C => N424_2, - Y => N532_0); - - \r.a.rsel1_RNIPFH[2]\ : NOR2A - port map(A => N_484, B => \rsel1[2]\, Y => d13); - - un6_fe_npc_I_12 : AND3 - port map(A => \fe_pc[2]\, B => \fe_pc[3]\, C => \fe_pc[4]\, - Y => N_144); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_Y_0 : AOI1 - port map(A => N578_0, B => N571, C => N570, Y => - ADD_33x33_fast_I265_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I249_un1_Y : NOR2B - port map(A => N669, B => N552, Y => I249_un1_Y_0); - - \r.e.op1_RNI9LUH[16]\ : MX2 - port map(A => \op1[16]\, B => \data_0[16]\, S => ldbp1_4, Y - => \un1_iu0_6[16]\); - - \r.x.data_0_RNO_1[27]\ : NOR2A - port map(A => \data_0[27]\, B => ld_3, Y => \data_0_m[27]\); - - \r.m.y_RNO[9]\ : AO1C - port map(A => y14_0, B => \logicout[9]\, C => \y_iv_2[9]\, - Y => \y_0[9]\); - - \r.a.ctrl.inst_RNI293H1[24]\ : OR3A - port map(A => N_472, B => N_212, C => N_259, Y => - cp_disabled_5_sqmuxa); - - \r.a.rsel1_RNIQQVRB5[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[19]\, Y - => \aluresult_m_0[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I68_Y : AND2 - port map(A => N434_0, B => N437_0, Y => N527_0); - - \r.a.ctrl.inst_RNI5H3O1[23]\ : OR3 - port map(A => N_202, B => illegal_inst37_4, C => N_201, Y - => N_346); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_a3_1_0 : NOR2B - port map(A => alucin, B => N398_0, Y => - ADD_33x33_fast_I206_Y_0_a3_1_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I322_Y_0 : AX1C - port map(A => I259_un1_Y_1, B => ADD_33x33_fast_I259_Y_3, C - => \un6_ex_add_res_s2_1[32]\, Y => - \un6_ex_add_res_s0[32]\); - - \r.w.result_RNICD4P3[1]\ : NOR3C - port map(A => \d_1_iv_1[1]\, B => \d_1_iv_0[1]\, C => - \rfo_m_i[33]\, Y => \d_1_iv_3[1]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I243_un1_Y\ : NOR3C - port map(A => N605, B => N589, C => N501_0, Y => I243_un1_Y); - - \r.a.rfa1_RNIS1041[7]\ : MX2 - port map(A => \un3_de_ren1[98]\, B => \rfa1[7]\, S => holdn, - Y => raddr1(7)); - - un6_ex_add_res_d0_ADD_33x33_fast_I237_un1_Y : NOR2B - port map(A => N666, B => N651_0, Y => I237_un1_Y); - - \r.m.y_RNO_3[9]\ : AOI1B - port map(A => wy_1_0, B => \y[9]\, C => \y_m[9]\, Y => - \y_iv_1[9]\); - - \r.m.result_RNI522A3[0]\ : NOR3C - port map(A => \d_iv_0[0]\, B => \result_m_0[0]\, C => - \rfo_m[0]\, Y => \d_iv_2[0]\); - - \r.e.ctrl.pc_RNIE3E92[19]\ : AOI1B - port map(A => \pc[19]\, B => jmpl_0, C => \y_m_1[19]\, Y - => \aluresult_1_iv_1[19]\); - - \r.w.s.wim[4]\ : DFN1E0 - port map(D => \wim_1[4]\, CLK => lclk_c, E => holdn, Q => - \wim[4]\); - - un2_rstn_5_RNI9UJNL9 : OR2B - port map(A => m21_2, B => N_6618, Y => N_22); - - \r.e.op2_RNO_2[26]\ : NOR3C - port map(A => \d_1_iv_1[26]\, B => \d_1_iv_0[26]\, C => - \rfo_m_i[58]\, Y => \d_1_iv_3[26]\); - - \r.a.ctrl.inst_RNI6L3O1[22]\ : NOR3B - port map(A => illegal_inst_1_sqmuxa_i_0, B => N_433, C => - N_201, Y => illegal_inst_1_sqmuxa_i_2); - - \r.x.nerror_RNO\ : NOR2B - port map(A => rst, B => error, Y => nerror_1); - - \r.e.ldbp2\ : DFN1E0 - port map(D => ldbp2, CLK => lclk_c, E => holdn, Q => - ldbp2_3); - - un6_ex_add_res_d2_ADD_33x33_fast_I116_Y : NOR2A - port map(A => N513_2, B => N517_1, Y => N579_1); - - \r.m.ctrl.inst[31]\ : DFN1E0 - port map(D => \inst_2[31]\, CLK => lclk_c, E => holdn, Q - => \inst_1[31]\); - - \r.m.werr_RNIA2H4\ : OR2 - port map(A => werr_0, B => werr_2, Y => werr); - - \r.f.pc_RNO_5[16]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[16]\, Y => \xc_trap_address_m[16]\); - - \r.e.alusel_RNIRC5C_1[0]\ : NOR3A - port map(A => \alusel[1]\, B => \alusel[0]\, C => jmpl, Y - => aluresult_3_sqmuxa_0); - - \r.e.ldbp1_1\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_1); - - \r.e.jmpl_RNO\ : NOR2A - port map(A => jmpl_2, B => trap_1, Y => N_4); - - \r.m.werr\ : DFN1 - port map(D => werr_RNO, CLK => lclk_c, Q => werr_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_un1_Y_0 : NOR2B - port map(A => N629_0, B => N645, Y => - ADD_33x33_fast_I261_un1_Y_0); - - \r.d.pc_RNIMTGB4[13]\ : MX2 - port map(A => \dpc[13]\, B => \fpc[13]\, S => ra_bpmiss_1, - Y => N_3890); - - \r.x.data_0_RNO_3[4]\ : OR2B - port map(A => N_3455, B => data_0_0_20, Y => \dco_m_i[116]\); - - \r.f.pc_RNO_3[12]\ : NAND2 - port map(A => \tmp[12]\, B => un2_rstn_5_0, Y => - \tmp_m[12]\); - - \r.e.op1[18]\ : DFN1E0 - port map(D => \aop1[18]\, CLK => lclk_c, E => holdn, Q => - \op1[18]\); - - \r.a.imm_RNICUT01[4]\ : NOR3C - port map(A => \result_m_i[4]\, B => \imm_m_i[4]\, C => - \d_1_iv_1[4]\, Y => \d_1_iv_2[4]\); - - \r.d.inull\ : DFN1E0 - port map(D => de_inull, CLK => lclk_c, E => holdn, Q => - \inull\); - - \r.m.result_RNI3D5D3[27]\ : NOR3C - port map(A => \d_iv_0[27]\, B => \result_m_0[27]\, C => - \rfo_m[27]\, Y => \d_iv_2[27]\); - - \r.e.op2_RNIU6OP[31]\ : MX2 - port map(A => \op2[31]\, B => N_4278, S => ldbp2_1, Y => - \un1_iu0_5[97]\); - - \r.e.shcnt_RNI56DTT[1]\ : MX2C - port map(A => \shiftin_14[30]\, B => \shiftin_14[28]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[28]\); - - \r.e.aluop_RNI5N3F4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[27]\, Y => - \aluop_RNI5N3F4[1]\); - - GND_i : GND - port map(Y => \GND\); - - wovf_exc_0_sqmuxa_RNO_2 : MX2 - port map(A => \wim_1[1]\, B => \wim_1[5]\, S => \ncwp_3[2]\, - Y => N_3722); - - \r.d.annul_RNILQG71\ : AO1 - port map(A => ldcheck2_0_sqmuxa_1, B => ldcheck2_0_sqmuxa, - C => annul_1, Y => annul_RNILQG71); - - \comb.branch_address.tmp_ADD_30x30_fast_I271_Y_0_0\ : XOR2 - port map(A => \dpc[13]\, B => \inst_0[11]\, Y => - ADD_30x30_fast_I271_Y_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I19_P0N : AO1A - port map(A => ldbp1_3, B => \op1[18]\, C => \data_0_0[18]\, - Y => N452_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_Y : NAND2 - port map(A => I261_un1_Y, B => ADD_33x33_fast_I261_Y_2, Y - => N768_0); - - \r.e.op1_RNIPACR1[15]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[15]\, Y => - \ex_op1_i_m[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I313_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[23]\, B => N782_1, Y => - \un6_ex_add_res_s0[23]\); - - \r.x.ctrl.annul_RNI7RVD3\ : OR2 - port map(A => y6_2, B => annul_1_0, Y => et_0_sqmuxa_i); - - \comb.cwp_ctrl.un7_op_0_a3\ : NAND2 - port map(A => N_142, B => wy_1_0_a3_1_0, Y => un7_op); - - \r.x.result_RNI5L6E[29]\ : MX2 - port map(A => \result_0[29]\, B => \data_0_0[29]\, S => - ld_4, Y => \un1_p0_6[381]\); - - \r.x.npc_RNIUABL[0]\ : MX2C - port map(A => N_3241, B => N_3271, S => \npc[0]\, Y => - \xc_result[30]\); - - \r.d.inst_0_RNO_0[24]\ : MX2 - port map(A => data_0_2_24, B => \inst_0_0[24]\, S => - inull_RNIFV6VG2_0, Y => N_4624); - - \comb.op_mux.d_1_iv_RNO_3[29]\ : OA1A - port map(A => \maddress[29]\, B => d27_0, C => - \cpi_m_i[381]\, Y => \d_1_iv_1[29]\); - - \r.a.rsel1_RNI4RCNJ5[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[20]\, Y => - \aluresult_m_0[20]\); - - \r.a.imm[0]\ : DFN1E0 - port map(D => \un3_de_ren1[118]\, CLK => lclk_c, E => holdn, - Q => \imm[0]\); - - \r.e.shleft_1_RNIHHIM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[27]\, S => - shleft_1, Y => \shiftin_5[58]\); - - \r.a.ctrl.inst_RNIERBU3[20]\ : NOR3C - port map(A => N_365, B => \inst_RNILL631[19]\, C => N_362, - Y => aluop_0_1_0_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I199_Y : OAI1 - port map(A => N603_i, B => N610_0, C => N602_1, Y => N668_0); - - \r.e.op2_RNO_6[17]\ : OR2B - port map(A => data2(17), B => d25, Y => \rfo_m_i[49]\); - - \r.e.ctrl.inst_RNIPS1E[26]\ : NOR2B - port map(A => \inst_1[26]\, B => \inst_1[27]\, Y => - ex_bpmiss_1_0_a5_0_0); - - \r.d.inst_0_0_0_RNIQKFJ[21]\ : NOR3A - port map(A => not_valid, B => \un1_p0_6_0[60]\, C => - annul_1, Y => bicc_hold_1); - - \r.d.annul_RNIIHK0F_0\ : AO1 - port map(A => branch_0, B => bpmiss_1_i_0_0, C => - un2_rstn_5_0_i, Y => un2_rstn_4_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I11_G0N\ : NOR2B - port map(A => \inst_0[11]\, B => \dpc[13]\, Y => N391); - - \r.a.rfa2[5]\ : DFN1E0 - port map(D => \un3_de_ren1[104]\, CLK => lclk_c, E => holdn, - Q => \rfa2[5]\); - - \r.e.aluop_1_RNI20193[1]\ : MX2C - port map(A => \logicout_4[14]\, B => N_6901, S => N_6866_i, - Y => N_3637); - - un6_fe_npc_I_97 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \fe_pc[17]\, Y => N_83); - - \r.f.pc_RNO_2[19]\ : OR2B - port map(A => I_105, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[17]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I239_un1_Y : OR2B - port map(A => N668_0, B => N653_1, Y => I239_un1_Y_i); - - \r.a.ctrl.wreg_RNO_5\ : NOR3 - port map(A => N_89, B => \inst_0_0[22]\, C => un1_inst, Y - => write_reg_4_sqmuxa); - - \r.e.shleft_0_RNITKLK1\ : MX2C - port map(A => \shiftin_5[18]\, B => \shiftin_5[2]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[2]\); - - \r.d.annul_RNIU4C2O1\ : OA1A - port map(A => annul_next_1_sqmuxa_1_6, B => ldlock, C => - un1_annul_next_1_sqmuxa_3_2, Y => - un1_annul_next_1_sqmuxa_3_3); - - \r.a.ctrl.inst_RNILL631[19]\ : OR2 - port map(A => aluop_1_1_0_a5_0, B => N_472, Y => - \inst_RNILL631[19]\); - - \r.f.pc[8]\ : DFN1E0 - port map(D => \pc_1[8]\, CLK => lclk_c, E => holdn, Q => - \fpc[8]\); - - \r.d.pv_RNO_4\ : OR3 - port map(A => ex_bpmiss_1_0, B => annul_2, C => - \de_hold_pc_1\, Y => N_4242); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_Y_1 : AOI1B - port map(A => N498, B => N495_0, C => - ADD_33x33_fast_I260_Y_0_1, Y => ADD_33x33_fast_I260_Y_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I313_Y_0 : XNOR3 - port map(A => \un1_iu0_6[22]\, B => \op2[22]\, C => N782_0, - Y => \un6_ex_add_res_s1_i[23]\); - - \r.a.rsel2_0_RNI7V53_2[0]\ : NOR2A - port map(A => d26_0, B => \rsel2_0[0]\, Y => d25); - - \r.a.rsel1_RNIPFH[0]\ : NOR3B - port map(A => \rsel1[0]\, B => \rsel1[1]\, C => \rsel1[2]\, - Y => d14); - - un6_fe_npc_I_80 : AND2 - port map(A => \fe_pc[14]\, B => \fe_pc[15]\, Y => - \DWACT_FINC_E[8]\); - - \r.f.pc_RNO_0[2]\ : NOR3C - port map(A => \un6_ex_add_res_m[3]\, B => \pc_1_iv_0[2]\, C - => \tmp_m[2]\, Y => \pc_1_iv_2[2]\); - - \r.a.ctrl.rd_RNO[5]\ : NOR2A - port map(A => I_13_0, B => un3_reg, Y => N_35); - - \r.m.y_RNIM65F7[25]\ : NOR3C - port map(A => \y_m_1[25]\, B => \ex_op2_m[25]\, C => - \aluop_RNIQ4RF4[1]\, Y => \aluresult_1_iv_2[25]\); - - \r.m.y_RNO_0[25]\ : NOR3C - port map(A => \y_m_2[26]\, B => \y_m_0[25]\, C => - \y_iv_1[25]\, Y => \y_iv_2[25]\); - - \r.e.ctrl.rett\ : DFN1E0 - port map(D => rett_1, CLK => lclk_c, E => holdn, Q => - rett_3); - - \r.d.inst_0_RNIRAPD[23]\ : AO1C - port map(A => tmp, B => icc_check_3_0_a3_1, C => N_3721, Y - => N_3718); - - \r.x.ctrl.tt[0]\ : DFN1E0 - port map(D => \tt2[0]\, CLK => lclk_c, E => holdn, Q => - \tt[0]\); - - \r.x.data_0_RNI796I1[7]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[7]\, Y => - \ex_op1_i_m[7]\); - - \r.a.ctrl.pc_RNI0GE2C[23]\ : MX2 - port map(A => \pc_3[23]\, B => N_3900, S => ex_bpmiss_1, Y - => \fe_pc[23]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I60_Y : NOR2B - port map(A => N449, B => N446, Y => N519_0); - - \r.x.result[11]\ : DFN1E0 - port map(D => \maddress[11]\, CLK => lclk_c, E => holdn, Q - => \result_0[11]\); - - \r.e.op1[27]\ : DFN1E0 - port map(D => \aop1[27]\, CLK => lclk_c, E => holdn, Q => - \op1[27]\); - - \r.a.ctrl.pc_RNI1GE2C[31]\ : MX2 - port map(A => \pc_0[31]\, B => N_3908, S => ex_bpmiss_1_0, - Y => \fe_pc[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I23_G0N : OA1 - port map(A => \op1[22]\, B => ldbp1_3, C => \data_0_0[22]\, - Y => N463_1); - - \r.e.op1_RNIK8N34[0]\ : NOR3C - port map(A => \rfo_m_i[32]\, B => \d_1_iv_2[0]\, C => - \op1_m_i[0]\, Y => \d_1_iv_4[0]\); - - \r.w.s.y_RNO[9]\ : MX2 - port map(A => \y_2[9]\, B => \result_0[9]\, S => N_481, Y - => N_3773); - - \r.e.ctrl.rd_RNID7P71[6]\ : XNOR2 - port map(A => \rd_0[6]\, B => \un3_de_ren1[97]\, Y => - un2_rs1_1_6_i_0); - - \r.w.s.y[6]\ : DFN1E0 - port map(D => N_3770, CLK => lclk_c, E => N_6922_i, Q => - \y[6]\); - - \r.x.result_RNI47MJ3[29]\ : MX2C - port map(A => \un1_iu0_6[29]\, B => \un1_p0_6[381]\, S => - bpdata6_0_0, Y => \bpdata[29]\); - - \r.e.op2_RNO_0[20]\ : OR3C - port map(A => \op1_m_i[20]\, B => \d_1_iv_3[20]\, C => - \aluresult_m_i[20]\, Y => \d_1[20]\); - - \r.a.rsel2_0[0]\ : DFN1E0 - port map(D => N_3944, CLK => lclk_c, E => holdn, Q => - \rsel2_0[0]\); - - \r.e.aluop_1_RNIHDBS1[1]\ : MX2C - port map(A => N_3530, B => \logicout_3[3]\, S => - \aluop_1[1]\, Y => N_3562); - - \r.x.data_0[22]\ : DFN1E0 - port map(D => \data_0_1[22]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_0[22]\); - - \r.e.aluop_0_RNIFL2Q5[0]\ : MX2C - port map(A => N_3574, B => N_3638, S => \aluop_0[0]\, Y => - \logicout[15]\); - - \r.e.op2_RNI40IN1[29]\ : OR2B - port map(A => \un1_iu0_5[95]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[29]\); - - \r.x.result_RNIKCOE[31]\ : OR2B - port map(A => \un1_p0_6[383]\, B => d14, Y => - \cpi_m_0[383]\); - - \r.a.ctrl.inst[25]\ : DFN1E0 - port map(D => \inst_0[25]\, CLK => lclk_c, E => holdn, Q - => \inst_1[25]\); - - \r.e.op2_RNI0OG11_0[20]\ : OR2 - port map(A => \un1_iu0_6[20]\, B => \un1_iu0_5[86]\, Y => - \logicout_3[20]\); - - \r.e.op1_RNIUI9G[28]\ : OR2B - port map(A => \op1[28]\, B => un14_casaen_s1_0, Y => - \op1_m_0[28]\); - - \r.a.ctrl.inst_RNI3HLO[27]\ : MX2C - port map(A => branch_2, B => branch_6, S => \inst_2[27]\, Y - => N_3342); - - \comb.branch_address.tmp_ADD_30x30_fast_I37_Y\ : OA1A - port map(A => \inst_0_1[26]\, B => \dpc[26]\, C => N434_1, - Y => N454); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_Y_1\ : AOI1B - port map(A => N520, B => N513, C => ADD_30x30_fast_I235_Y_0, - Y => ADD_30x30_fast_I235_Y_1); - - \r.m.y_RNO_3[13]\ : OR3A - port map(A => \y_2[13]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[13]\); - - \r.e.op2_RNINUNP[11]\ : MX2 - port map(A => \op2[11]\, B => N_4258, S => ldbp2_1, Y => - \un1_iu0_5[77]\); - - \r.e.op2_RNO_8[24]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[376]\, - Y => \cpi_m_i[376]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I103_un1_Y : OR3C - port map(A => N473_1, B => N476_1, C => N504_1, Y => - I103_un1_Y_i); - - \r.e.jmpl_RNIDN24Q_0\ : OR2B - port map(A => \shiftin_17[17]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[17]\); - - \r.e.jmpl_RNIMI00K1\ : NOR3C - port map(A => \aluresult_1_iv_6[23]\, B => - \aluop_RNII15D6[0]\, C => \shiftin_17_m[24]\, Y => - \aluresult_1_iv_8[23]\); - - \r.e.aluop[2]\ : DFN1E0 - port map(D => \aluop[2]\, CLK => lclk_c, E => holdn, Q => - \aluop_1[2]\); - - un9_ra_I_13 : XOR2 - port map(A => \cwp[1]\, B => \DWACT_ADD_CI_0_TMP_2[0]\, Y - => I_13_3); - - \r.d.pc[10]\ : DFN1 - port map(D => \pc_RNO[10]\, CLK => lclk_c, Q => \dpc[10]\); - - \r.e.aluop_RNIFR794[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[28]\, Y => - \bpdata_i_m[28]\); - - \r.a.imm_RNO[11]\ : MX2 - port map(A => \inst_0_RNI1JUM[1]\, B => \inst_0[11]\, S => - call_hold5_0, Y => \un3_de_ren1[129]\); - - \r.e.op2_RNO[30]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[30]\, Y => N_314); - - \r.e.op2_RNI2NOP[17]\ : MX2 - port map(A => \op2[17]\, B => N_4264, S => ldbp2_1, Y => - \un1_iu0_5[83]\); - - \r.e.op1_RNI6C23A6[23]\ : NOR3C - port map(A => \op1_m_0[23]\, B => \d_iv_2[23]\, C => - \aluresult_m_0[23]\, Y => \d_i[23]\); - - \r.w.result_RNI50P1[11]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[11]\, Y - => \result_m_0_0[11]\); - - \r.e.ctrl.trap\ : DFN1E0 - port map(D => trap_3, CLK => lclk_c, E => holdn, Q => - trap_0); - - \r.d.cnt_RNI666I[1]\ : AO1D - port map(A => ldcheck1_1_sqmuxa_1, B => un54_casaen, C => - call_hold7_i, Y => ldcheck2_0_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I79_Y\ : OA1 - port map(A => \dpc[5]\, B => \inst_0_RNI3RUM[3]\, C => N371, - Y => N496_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I183_un1_Y : NOR2B - port map(A => N594_0, B => N587_0, Y => I183_un1_Y); - - \r.x.npc_RNIE6KU[0]\ : MX2C - port map(A => N_3215, B => N_3245, S => \npc[0]\, Y => - \xc_result[4]\); - - \r.f.pc[17]\ : DFN1E0 - port map(D => \pc_1[17]\, CLK => lclk_c, E => holdn, Q => - \fpc[17]\); - - \r.a.ctrl.inst_RNI7NUN[31]\ : OA1A - port map(A => \inst[30]\, B => N_219, C => \inst[31]\, Y - => \aop2_i_o2_0[0]\); - - \r.f.pc[31]\ : DFN1E0 - port map(D => \pc_1[31]\, CLK => lclk_c, E => holdn, Q => - \fpc[31]\); - - \r.e.aluop_RNI4J3F4[1]\ : NAND2 - port map(A => aluresult_6_sqmuxa, B => \bpdata[19]\, Y => - \bpdata_m[19]\); - - \r.e.invop2_RNIB98T6\ : MX2C - port map(A => \un6_ex_add_res_s2[6]\, B => - \un6_ex_add_res_s0[6]\, S => invop2, Y => N_6645); - - un6_ex_add_res_d2_ADD_33x33_fast_I197_Y : OR2A - port map(A => I197_un1_Y, B => N600_0, Y => N666_0); - - \r.f.pc_RNO_0[31]\ : NAND2 - port map(A => \tmp[31]\, B => \un2_rstn_5\, Y => - \tmp_m[31]\); - - \r.f.pc_RNO_7[22]\ : MX2 - port map(A => \fpc[22]\, B => \tba[10]\, S => rstate_6314_d, - Y => \xc_trap_address[22]\); - - \r.e.ldbp2_RNIT8TAA2\ : OR2B - port map(A => \aluresult_1_iv_9[5]\, B => - \un6_ex_add_res_m[6]\, Y => \aluresult[5]\); - - \r.m.ctrl.inst_RNIO92L[19]\ : NOR3A - port map(A => \inst_2[22]\, B => \inst_3[19]\, C => - \inst_0[24]\, Y => inst_4_2); - - \r.a.ctrl.rd_RNI6FAVB[6]\ : XA1A - port map(A => \rd[6]\, B => \un3_de_ren1[105]\, C => - un1_de_ren1_NE_5, Y => un1_de_ren1_NE_i_0); - - \r.e.aluop_RNIDO0N[2]\ : XA1 - port map(A => \un1_iu0_5[70]\, B => \aluop_1[2]\, C => - \un1_iu0_6[4]\, Y => N_3531); - - \r.e.op1_RNI1JNF[24]\ : OR2A - port map(A => un17_casaen_0_2, B => \op1[24]\, Y => - \op1_RNI1JNF[24]\); - - \r.a.ctrl.inst_RNIMC2S[19]\ : AXO5 - port map(A => N_232, B => \inst_2[19]\, C => \inst_2[20]\, - Y => N_262); - - \r.e.alusel_RNO[0]\ : NOR3C - port map(A => N_500, B => \alusel_i_0_o5_0[1]\, C => - \alusel_i_0_2[0]\, Y => N_3838_i_0); - - \r.d.pc_RNI2CCA4[8]\ : MX2 - port map(A => \dpc[8]\, B => \fpc[8]\, S => \ra_bpmiss_1_0\, - Y => N_3885); - - \r.w.s.tba_RNINQF44[14]\ : AOI1B - port map(A => \tba[14]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[26]\, Y => \aluresult_1_iv_3[26]\); - - \r.e.shleft_RNIOULD2\ : MX2B - port map(A => \shiftin_5[46]\, B => \shiftin_5[30]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[30]\); - - \r.w.result[21]\ : DFN1E0 - port map(D => \wdata[21]\, CLK => lclk_c, E => holdn, Q => - \result[21]\); - - \r.e.invop2_0_RNIA1FAP1\ : MX2C - port map(A => \un6_ex_add_res_s2[19]\, B => - \un6_ex_add_res_s0[19]\, S => invop2_0, Y => N_6638); - - \r.m.ctrl.pc_RNIV9HF[24]\ : MX2 - port map(A => \pc_2[24]\, B => \pc_3[24]\, S => \npc_0[1]\, - Y => N_3265); - - \r.e.op2_RNO_8[18]\ : OR3B - port map(A => d29_0, B => \imm[18]\, C => \rsel2_1[0]\, Y - => \imm_m_i[18]\); - - \r.x.result_RNI79BV5[3]\ : OR2B - port map(A => \bpdata[3]\, B => N_3957, Y => \bpdata_m[3]\); - - \r.e.aluop_0_RNI34A66[0]\ : OR2B - port map(A => \logicout[26]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[26]\); - - \r.f.pc_RNO_7[14]\ : MX2 - port map(A => \fpc[14]\, B => \tba[2]\, S => rstate_6314_d, - Y => \xc_trap_address[14]\); - - \r.e.jmpl_RNI66TM71\ : AOI1B - port map(A => \shiftin_17[2]\, B => aluresult_1_sqmuxa, C - => \shiftin_17_m_0[1]\, Y => \aluresult_2_iv_7[1]\); - - \r.a.imm[22]\ : DFN1E0 - port map(D => \inst_0[12]\, CLK => lclk_c, E => holdn, Q - => \imm[22]\); - - \r.a.rsel1_0_RNIVK8M2[2]\ : OR2B - port map(A => data1(7), B => d11_0, Y => \rfo_m[7]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I311_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[21]\, B => N786, Y => - \un6_ex_add_res_s2[21]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I82_Y : NOR2B - port map(A => N416_1, B => N413_1, Y => N541_1); - - \r.e.ldbp2_RNIB8SLL4\ : MX2 - port map(A => \un6_ex_add_res_s1[29]\, B => N_6625, S => - ldbp2_3, Y => \eaddress[28]\); - - \r.e.op2_RNO_6[20]\ : OR3B - port map(A => d29_0, B => \imm[20]\, C => \rsel2_1[0]\, Y - => \imm_m_i[20]\); - - \r.e.aluop_1_RNI0PFT2[1]\ : MX2C - port map(A => \logicout_4[23]\, B => N_6880_i, S => - N_6866_i, Y => N_3646); - - \r.a.ctrl.pc_RNIJVD2C[11]\ : MX2 - port map(A => \pc[11]\, B => N_3888, S => ex_bpmiss_1, Y - => \fe_pc[11]\); - - \r.e.shcnt_RNIAR1C[4]\ : MX2C - port map(A => \shcnt[4]\, B => N_3308, S => ldbp2_3, Y => - \ex_shcnt_1_i[4]\); - - \r.e.op2_RNI6ROP[18]\ : MX2 - port map(A => \op2[18]\, B => N_4265, S => ldbp2_2, Y => - \un1_iu0_5[84]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I42_Y : NAND2 - port map(A => N473, B => N476, Y => N501); - - \r.x.data_0_RNO_0[22]\ : AOI1B - port map(A => rdatav_0_1_0_iv_5_4, B => mcdo_m_0_20, C => - rdata_6_sqmuxa, Y => \dco_m_0[118]\); - - \r.m.y_RNO_4[25]\ : OR3A - port map(A => \y_1[25]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[25]\); - - \r.a.rsel1_RNIJAKCP1[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[0]\, Y => - \aluresult_m_0[0]\); - - \r.f.pc_RNIF2C62[7]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[7]\, Y => \xc_trap_address_m[7]\); - - \r.a.ctrl.pc_RNIB0F2C[19]\ : MX2 - port map(A => \pc_3[19]\, B => N_3896, S => ex_bpmiss_1, Y - => \fe_pc[19]\); - - \r.a.ctrl.inst_RNIDG1E_0[21]\ : OR2B - port map(A => \inst_2[21]\, B => \inst_2[19]\, Y => N_241); - - \r.f.pc_RNIEJ56[3]\ : NOR2A - port map(A => \fpc[3]\, B => rstate_6314_d_0, Y => - \xc_trap_address_m_0[3]\); - - \r.e.op1_RNI5S1CE2[5]\ : NOR3C - port map(A => N_407, B => \d_iv_0_2[5]\, C => N_408, Y => - \d_i_0[5]\); - - \r.e.op2_RNO_3[19]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[19]\, Y => - \aluresult_m_i[19]\); - - \r.d.pv_RNI0OB48\ : OR3A - port map(A => un23_exbpmiss_0, B => un52_casaen, C => - ra_bpannul_1, Y => un23_exbpmiss_i_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I308_Y_0_0 : XOR2 - port map(A => \op2[17]\, B => \un1_iu0_6[17]\, Y => - ADD_33x33_fast_I308_Y_0_0); - - \r.e.shleft_RNIEH9D2\ : MX2B - port map(A => \shiftin_5[39]\, B => \shiftin_5[23]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I80_Y\ : AO13 - port map(A => \inst_0_RNI3RUM[3]\, B => \dpc[5]\, C => N364, - Y => N497_1); - - \r.e.op1_RNI7O0M7[0]\ : OR2B - port map(A => \edata2_0_iv_0[0]\, B => \bpdata_i_m[0]\, Y - => edata2_0_iv(0)); - - \r.a.ctrl.pc_RNIVFE2C[15]\ : MX2 - port map(A => \pc[15]\, B => N_3892, S => ex_bpmiss_1, Y - => \fe_pc[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I147_Y : AO1 - port map(A => N548_1, B => N545_1, C => N544_0, Y => N610_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I305_Y_0_1 : XOR2 - port map(A => \data_0[14]\, B => \un1_iu0_6[14]\, Y => - \un6_ex_add_res_s2_1[15]\); - - \r.m.ctrl.ld\ : DFN1E0 - port map(D => ld_5, CLK => lclk_c, E => holdn, Q => ld); - - \r.d.inst_0[26]\ : DFN1 - port map(D => \inst_0_RNO[26]\, CLK => lclk_c, Q => - \inst_0[26]\); - - \r.x.result_RNIT3AB3[6]\ : MX2 - port map(A => \un1_iu0_6[6]\, B => \un1_p0_6[358]\, S => - bpdata6_0_0, Y => \bpdata[6]\); - - \r.d.cnt_RNI703B[1]\ : OR3A - port map(A => ldcheck2_2_sqmuxa_1_1, B => N_89, C => - call_hold7_i, Y => ldcheck2_2_sqmuxa_1_i); - - \r.x.npc_0[1]\ : DFN1E0 - port map(D => \npc_1_0[1]\, CLK => lclk_c, E => holdn, Q - => \npc_0[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I113_Y_0 : MIN3 - port map(A => \data_0[21]\, B => \un1_iu0_6[21]\, C => - N457_0, Y => ADD_33x33_fast_I113_Y_0_0); - - \r.x.ctrl.wreg_RNIHAGI1\ : MX2C - port map(A => N_6350, B => wreg, S => xc_wreg_0_sqmuxa, Y - => xc_wreg_1); - - \r.a.ctrl.inst_RNI0Q593[20]\ : OA1A - port map(A => illegal_inst38, B => N_212, C => - cp_disabled_11_sqmuxa, Y => cp_disabled_4_0_1_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I73_Y : AO13 - port map(A => N424_0, B => \un1_iu0_6[10]\, C => - \data_0[10]\, Y => N532); - - un6_ex_add_res_d0_ADD_33x33_fast_I144_Y : OR2B - port map(A => N545_1, B => N541_0, Y => N607_1); - - \r.m.y_RNIOTN71[20]\ : OR2B - port map(A => \y_0[20]\, B => aluresult_10_sqmuxa_0, Y => - \y_m_1[20]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I262_Y_0_0 : NOR3A - port map(A => N_52, B => N478, C => - ADD_33x33_fast_I39_Y_0_a3, Y => ADD_33x33_fast_I262_Y_0_0); - - \r.e.op2_RNO_0[6]\ : OR3C - port map(A => \op1_m_i[6]\, B => \d_1_iv_3[6]\, C => - \aluresult_m_i[6]\, Y => \d_1[6]\); - - \r.e.op2_RNI2EQ2JA[0]\ : AOI1B - port map(A => \icc_7_m_2[1]\, B => \icc_7[1]\, C => - \icc_2_m[1]\, Y => \icc_12_iv_0[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I25_G0N : NOR2B - port map(A => \un1_iu0_6[24]\, B => \op2[24]\, Y => N469); - - un6_ex_add_res_d1_ADD_33x33_fast_I196_Y : NOR2A - port map(A => N607_0, B => N599_1, Y => N665); - - \r.e.invop2_RNIAAN583\ : MX2C - port map(A => \un6_ex_add_res_s2[31]\, B => - \un6_ex_add_res_s0[31]\, S => invop2, Y => N_6577); - - \r.d.pc_RNIQTGB4[15]\ : MX2 - port map(A => \dpc[15]\, B => \fpc[15]\, S => ra_bpmiss_1, - Y => N_3892); - - \r.a.ctrl.inst_RNIC8Q8[28]\ : XOR2 - port map(A => \inst_1[28]\, B => \icc_0[0]\, Y => branch_6); - - un6_ex_add_res_d0_ADD_33x33_fast_I62_Y : NOR2B - port map(A => N446, B => N443_0, Y => N521); - - \r.a.rsel1_RNI0N5AB3[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[12]\, Y => - \aluresult_m_0[12]\); - - \r.x.data_0_RNO_0[11]\ : NOR2B - port map(A => N_3473, B => data_0_0_11, Y => \dco_m_0[107]\); - - \r.x.ctrl.pc_RNIJ2IF[17]\ : MX2 - port map(A => \pc_2[17]\, B => \pc_0[17]\, S => \npc_1[1]\, - Y => N_3228); - - \r.e.shcnt_RNINQM94[3]\ : MX2 - port map(A => \shiftin_8[17]\, B => \shiftin_8[9]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I286_Y_0_0\ : XOR2 - port map(A => \dpc[28]\, B => \inst_0_1[28]\, Y => - ADD_30x30_fast_I286_Y_0_0); - - \r.f.pc_RNO_2[23]\ : OR2B - port map(A => I_136, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[21]\); - - \r.e.op2_RNIUSAP_0[7]\ : OR2 - port map(A => \un1_iu0_6[7]\, B => \un1_iu0_5[73]\, Y => - \logicout_3[7]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I269_Y_0\ : XOR2 - port map(A => N741, B => ADD_30x30_fast_I269_Y_0_0, Y => - \tmp[11]\); - - \r.e.op2_RNO_6[30]\ : OR2B - port map(A => data2(30), B => d25, Y => \rfo_m_i[62]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I14_G0N\ : NOR2B - port map(A => \inst_0[14]\, B => \dpc[16]\, Y => N400); - - \r.a.jmpl_RNO\ : NOR2 - port map(A => un7_op_3, B => N_150, Y => jmpl_3); - - \r.e.et\ : DFN1E0 - port map(D => et_1, CLK => lclk_c, E => holdn, Q => et_0); - - \r.w.result_RNIMFD4[17]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[17]\, - Y => \result_m_0_0[17]\); - - \r.e.op2_RNO_0[14]\ : OR3C - port map(A => \op1_m_i[14]\, B => \d_1_iv_3[14]\, C => - \aluresult_m_i[14]\, Y => \d_1[14]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I174_Y : NOR2B - port map(A => N585, B => N577, Y => N643_1); - - \r.w.s.et_RNIVNF2\ : OR2B - port map(A => \rstate_0[0]\, B => et, Y => N_6337); - - \r.m.y_RNO_0[31]\ : NOR3C - port map(A => \y_m[31]\, B => \y_m_0[31]\, C => - \y_iv_0[31]\, Y => \y_iv_2[31]\); - - \r.a.ctrl.rd_RNIMP6H1[7]\ : XOR2 - port map(A => \rd[7]\, B => un1_reg, Y => \rd_RNIMP6H1[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I248_un1_Y : OR2B - port map(A => N667, B => N616, Y => I248_un1_Y_i); - - \r.m.result_RNIT3P1[20]\ : OR2B - port map(A => d13, B => \maddress[20]\, Y => - \result_m_0[20]\); - - \r.x.data_0_RNICF9E[16]\ : XOR2 - port map(A => \data_0[16]\, B => invop2_0, Y => N_4263); - - \r.w.s.tt[2]\ : DFN1E0 - port map(D => \xc_vectt_1[2]\, CLK => lclk_c, E => N_6747, - Q => \irl[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I134_Y\ : OR2 - port map(A => N495_1, B => I134_un1_Y, Y => N554); - - un6_ex_add_res_d2_ADD_33x33_fast_I100_Y : NOR3C - port map(A => N473_2, B => N476_2, C => N497, Y => N563_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I268_Y_0_0\ : XOR2 - port map(A => \dpc[10]\, B => \inst_0[8]\, Y => - ADD_30x30_fast_I268_Y_0_0); - - \r.a.ctrl.inst_RNIH5562[21]\ : AOI1 - port map(A => un1_illegal_inst11_2_0_a5_0, B => - illegal_inst11_0_a5_0, C => N_216, Y => - un1_illegal_inst11_0); - - \r.a.ctrl.inst_RNIA01E[22]\ : OR2A - port map(A => \inst[22]\, B => \inst_1[24]\, Y => N_232); - - \r.x.ctrl.inst_RNIP51E[24]\ : NOR2B - port map(A => \inst_2[24]\, B => \inst[23]\, Y => y6_0); - - \r.m.y_RNIA0LA2[8]\ : AOI1B - port map(A => \y[8]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[153]\, Y => \aluresult_1_iv_1[8]\); - - \r.d.pv_RNO_1\ : OA1A - port map(A => un6_rabpmiss_2, B => \de_hold_pc_1\, C => - N_4240, Y => pv_3); - - \r.x.result_RNIDQD25[6]\ : NOR2 - port map(A => \bpdata[6]\, B => N_3703_i, Y => - \bpdata_i_m_1[6]\); - - \r.d.pc_RNI04CA4[7]\ : MX2 - port map(A => \dpc[7]\, B => \fpc[7]\, S => ra_bpmiss_1, Y - => N_3884); - - \r.e.op2_RNO_3[16]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[16]\, Y => - \aluresult_m_i[16]\); - - \r.e.aluop_0_RNIPL6R[2]\ : XA1 - port map(A => \un1_iu0_5[73]\, B => \aluop_0[2]\, C => - \un1_iu0_6[7]\, Y => N_3534); - - \r.a.ctrl.pc[16]\ : DFN1E0 - port map(D => \dpc[16]\, CLK => lclk_c, E => holdn, Q => - \pc_0[16]\); - - \r.m.icc_RNIJ2R41[1]\ : OR3B - port map(A => trap_0_sqmuxa_2_0, B => trap_0_sqmuxa_2_1, C - => trap_0_sqmuxa_2_2, Y => trap_0_sqmuxa_2); - - \r.e.ctrl.pc[12]\ : DFN1E0 - port map(D => \pc[12]\, CLK => lclk_c, E => holdn, Q => - \pc_2[12]\); - - \r.d.cwp_RNISTPR[1]\ : MX2 - port map(A => \cwp[1]\, B => \ncwp_3[1]\, S => un8_op, Y - => \ncwp[1]\); - - \r.a.rsel2[0]\ : DFN1E0 - port map(D => N_3944, CLK => lclk_c, E => holdn, Q => - \rsel2[0]\); - - \r.m.y_RNIO6C97[24]\ : NOR2B - port map(A => \aluresult_1_iv_0[24]\, B => - \aluop_RNIN0RF4[1]\, Y => \aluresult_1_iv_2[24]\); - - \r.x.npc_RNIERDL[0]\ : MX2C - port map(A => N_3236, B => N_3266, S => \npc[0]\, Y => - \xc_result[25]\); - - \r.m.result[0]\ : DFN1E0 - port map(D => \eres2[0]\, CLK => lclk_c, E => holdn, Q => - \maddress[0]\); - - \r.e.op2_RNI40NB1[15]\ : OR2A - port map(A => \un1_iu0_5[81]\, B => \un1_iu0_6[15]\, Y => - \logicout_4[15]\); - - \r.e.jmpl_RNIDNUP91\ : AOI1B - port map(A => \shiftin_17[8]\, B => aluresult_1_sqmuxa_0, C - => \aluresult_1_iv_7[7]\, Y => \aluresult_1_iv_8[7]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I71_Y_0 : AO1 - port map(A => N431_1, B => N427_1, C => N430, Y => N530); - - un23_ra_I_15 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP_1[0]\, B => \cwp[1]\, Y - => \DWACT_ADD_CI_0_g_array_1_1[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I168_un1_Y\ : OR3C - port map(A => N476_0, B => N480, C => N542, Y => - I168_un1_Y_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I274_Y_0_a3 : NOR2B - port map(A => N796_1, B => N443_0, Y => - ADD_33x33_fast_I274_Y_0_a3_0); - - \r.x.result_RNIBED25[5]\ : NOR2 - port map(A => \bpdata[5]\, B => N_3703_i, Y => - \bpdata_i_m_1[5]\); - - \r.a.ctrl.inst_RNIIK1S[13]\ : OA1B - port map(A => \inst[13]\, B => \inst_1[25]\, C => N_212, Y - => illegal_inst_4_m_0); - - \r.d.cnt_RNIFET3[0]\ : OR2A - port map(A => \cnt_2[0]\, B => \cnt_0[1]\, Y => un52_casaen); - - \r.w.s.tba_RNIN17A1[15]\ : OR2B - port map(A => \tba[15]\, B => aluresult_12_sqmuxa, Y => - \tba_m[15]\); - - \r.e.ctrl.inst_RNIOS1E[24]\ : NOR2A - port map(A => \inst[24]\, B => \inst[19]\, Y => - \icc_7_m_0[1]\); - - \r.w.s.y_RNO_0[24]\ : NOR2A - port map(A => N_481, B => \result_0[24]\, Y => N_368); - - \r.w.s.tba[16]\ : DFN1E1 - port map(D => \result_0[28]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[16]\); - - \r.e.ctrl.inst[29]\ : DFN1E0 - port map(D => \inst[29]\, CLK => lclk_c, E => holdn, Q => - \inst_2[29]\); - - \r.a.ctrl.pc_RNIGGL0C[5]\ : MX2 - port map(A => \pc_0[5]\, B => N_3882, S => ex_bpmiss_1, Y - => \fe_pc[5]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I108_Y\ : OR3C - port map(A => I52_un1_Y, B => N409_2, C => I108_un1_Y, Y - => N528); - - un6_ex_add_res_d1_ADD_33x33_fast_I23_P0N : OR2 - port map(A => \op2[22]\, B => \un1_iu0_6[22]\, Y => N464_0); - - \r.e.op1_RNISA9G[26]\ : OR2B - port map(A => \op1[26]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[26]\); - - \r.e.jmpl_RNICCUBQ1\ : NOR3C - port map(A => \aluresult_1_iv_6[29]\, B => - \logicout_m_0[29]\, C => \shiftin_17_m[30]\, Y => - \aluresult_1_iv_8[29]\); - - \r.m.ctrl.pc[3]\ : DFN1E0 - port map(D => \pc_0[3]\, CLK => lclk_c, E => holdn, Q => - \pc_3[3]\); - - \r.w.s.tba_RNI14CA1[0]\ : OR2B - port map(A => \tba[0]\, B => aluresult_12_sqmuxa, Y => - \tba_m[0]\); - - \r.e.op1_RNO[23]\ : MX2C - port map(A => \d_i[23]\, B => \d_i[24]\, S => N_227, Y => - \aop1[23]\); - - \r.d.inst_0_RNI3AJ4[23]\ : OR3A - port map(A => \inst_0_0[23]\, B => \inst_0[20]\, C => - \inst_0[30]\, Y => N_3738); - - un6_ex_add_res_d2_ADD_33x33_fast_I298_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[7]\, B => \data_0_2[7]\, Y => - \un6_ex_add_res_s2_1[8]\); - - \r.w.s.tba_RNIDE5KG[11]\ : NOR3C - port map(A => \aluresult_1_iv_4[23]\, B => - \aluresult_1_iv_3[23]\, C => \bpdata_m_1[7]\, Y => - \aluresult_1_iv_6[23]\); - - \r.x.data_0_RNO_2[8]\ : AND2 - port map(A => \dco_m_0_i[120]\, B => \data_0_m_i[8]\, Y => - \data_0_1_0_iv_0[8]\); - - \r.m.result_RNO[5]\ : MX2 - port map(A => \aluresult[5]\, B => \op1[5]\, S => - un17_casaen_0_2, Y => \eres2[5]\); - - \r.e.aluop_RNIH8S04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[7]\, Y => - \bpdata_i_m_2[7]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I19_G0N\ : NOR2B - port map(A => \inst_0[19]\, B => \dpc[21]\, Y => N415); - - \comb.branch_address.tmp_ADD_30x30_fast_I122_Y\ : AO1 - port map(A => N487_1, B => N484_1, C => N483, Y => N542); - - un6_ex_add_res_d1_ADD_33x33_fast_I1_G0N : NOR2B - port map(A => \un1_iu0_6[0]\, B => \op2[0]\, Y => N397_0); - - \r.e.aluop_0_RNIQ8ID1[2]\ : XA1 - port map(A => \un1_iu0_5[88]\, B => \aluop_0[2]\, C => - \un1_iu0_6[22]\, Y => N_3549); - - \r.x.result_RNI3TAN3[27]\ : MX2C - port map(A => \un1_iu0_6[27]\, B => \un1_p0_6[379]\, S => - bpdata6, Y => \bpdata[27]\); - - \r.e.jmpl_RNIJRHU44\ : OR3C - port map(A => \aluresult_1_iv_7[16]\, B => - \shiftin_17_m_0[16]\, C => \un6_ex_add_res_m[17]\, Y => - \aluresult[16]\); - - \r.m.y_RNO[20]\ : OR3C - port map(A => \y_iv_1[20]\, B => \y_iv_0[20]\, C => - \logicout_m[20]\, Y => \y_1[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I59_Y\ : OA1 - port map(A => \dpc[16]\, B => \inst_0[14]\, C => N398_2, Y - => N476_0); - - \r.d.inst_0_RNIAAJ4[29]\ : MX2C - port map(A => \inst_0_0[21]\, B => \inst_0[29]\, S => - \inst_0[30]\, Y => \inst_0_1[31]\); - - \r.e.jmpl_RNIH6LEL1\ : NOR3C - port map(A => \aluresult_1_iv_6[24]\, B => - \aluresult_1_iv_5[24]\, C => \shiftin_17_m[25]\, Y => - \aluresult_1_iv_8[24]\); - - un37_ra_I_13 : XOR2 - port map(A => \cwp[1]\, B => \DWACT_ADD_CI_0_TMP_0[0]\, Y - => I_13_1); - - \r.e.ldbp2_2_RNI57ED02\ : OR2B - port map(A => \aluresult_1_iv_7[3]\, B => ldbp2_2_RNI7G0C6, - Y => \aluresult[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I129_un1_Y : NOR3C - port map(A => N434, B => N437, C => N530_2, Y => I129_un1_Y); - - \r.x.ctrl.pc_RNID3431[4]\ : MX2C - port map(A => \un1_p0_6[356]\, B => \pc_2[4]\, S => - s_3_sqmuxa, Y => N_3395); - - \r.m.y_RNO_3[14]\ : OR3A - port map(A => \y_2[14]\, B => wy_3, C => wy_1_0_1, Y => - N_387); - - \r.a.imm_RNI1645[0]\ : OR3B - port map(A => d29_0_0, B => \imm[0]\, C => \rsel2_0[0]\, Y - => \imm_m_i[0]\); - - \r.e.shcnt_RNIEJ7HD[2]\ : MX2C - port map(A => \shiftin_11[27]\, B => \shiftin_11[23]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[23]\); - - \r.a.ctrl.inst_RNIS0331[30]\ : AO1A - port map(A => N_209, B => N_472, C => \inst[30]\, Y => - N_451); - - \r.e.ctrl.rd_RNIRMGKE[0]\ : AOI1B - port map(A => wreg_1_6_0, B => wreg_1_5, C => wreg_2_1, Y - => rfe_1_1); - - \r.e.ctrl.rd_RNIHC1L[2]\ : XNOR2 - port map(A => \rd_1[2]\, B => \un3_de_ren1[93]\, Y => - un2_rs1_1_2_i_0); - - \r.e.aluop_0_RNIVQ1T2[1]\ : MX2C - port map(A => \logicout_4[16]\, B => N_6886, S => - N_6866_i_0, Y => N_3639); - - \r.d.pc_RNO[23]\ : MX2 - port map(A => \fpc[23]\, B => \dpc[23]\, S => N_6763_i, Y - => \pc_RNO[23]\); - - \r.w.s.icc_RNO_0[3]\ : AOI1B - port map(A => icc_2_sqmuxa, B => \result[23]\, C => - \icc_m_0[3]\, Y => \icc_1_iv_0[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I271_un1_Y : OR2B - port map(A => ADD_33x33_fast_I271_un1_Y_0, B => N649_1, Y - => I271_un1_Y_i); - - un2_rstn_5_0_0_RNITV7K4 : NAND2 - port map(A => \tmp[5]\, B => un2_rstn_5_0, Y => \tmp_m[5]\); - - \r.d.inst_0_RNIM3TA[29]\ : OR2B - port map(A => I_14_2, B => N_3525_3, Y => \de_raddr1_1[6]\); - - \r.m.ctrl.wy_RNI8E1D\ : NOR2A - port map(A => wy_1, B => wy_3, Y => y08); - - \r.d.inst_0_RNO[29]\ : NOR2B - port map(A => rst, B => N_4629, Y => \inst_0_RNO[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I116_Y\ : AO1B - port map(A => N481_2, B => N478_0, C => - ADD_30x30_fast_I116_Y_0, Y => N536); - - \r.e.op2_RNIR6OP[13]\ : MX2 - port map(A => \op2[13]\, B => N_4260, S => ldbp2_1, Y => - \un1_iu0_5[79]\); - - \r.e.ldbp2_RNIS1OF04\ : OR2A - port map(A => \eaddress[24]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[25]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I10_G0N : NOR2B - port map(A => \un1_iu0_6[9]\, B => \op2[9]\, Y => N424_2); - - \r.e.op2_RNO_7[23]\ : NOR2B - port map(A => \result_m_i_0[23]\, B => \cpi_m_i[375]\, Y - => \d_1_iv_1[23]\); - - \r.e.shleft_1_RNI5THM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[13]\, S => - shleft_1, Y => \shiftin_5[44]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I247_Y : OR2 - port map(A => N664, B => I247_un1_Y, Y => N808); - - \r.e.op1_RNI8TPD1[9]\ : NOR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[9]\, Y => - \ex_op1_i_m[9]\); - - \r.m.result_RNIFFJ83[15]\ : NOR3C - port map(A => \d_iv_0[15]\, B => \result_m_0[15]\, C => - \rfo_m[15]\, Y => \d_iv_2[15]\); - - \r.m.y_RNO_0[10]\ : AOI1B - port map(A => wy_1_0, B => \y[10]\, C => \y_m_0[10]\, Y => - \y_iv_1[10]\); - - \r.x.ctrl.rd_RNI5SGO[1]\ : AO1A - port map(A => N_6352, B => \rd_1[1]\, C => \rstate[0]\, Y - => waddr(1)); - - \r.e.op2_RNIP7HN1[14]\ : OR2B - port map(A => \un1_iu0_5[80]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[14]\); - - wovf_exc_0_sqmuxa_RNO_1 : MX2C - port map(A => N_3725, B => N_3726, S => \ncwp_3[1]\, Y => - N_3727); - - \r.e.aluop_0_RNIIRTVP[0]\ : AOI1B - port map(A => \logicout[28]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[28]\, Y => \aluresult_1_iv_7[28]\); - - \r.a.ctrl.pc_RNI5OE2C[17]\ : MX2 - port map(A => \pc[17]\, B => N_3894, S => ex_bpmiss_1_0, Y - => \fe_pc[17]\); - - \r.w.result[18]\ : DFN1E0 - port map(D => \wdata[18]\, CLK => lclk_c, E => holdn, Q => - \result[18]\); - - \r.e.shcnt_RNIFFO7E[2]\ : MX2C - port map(A => \shiftin_11[32]\, B => \shiftin_11[28]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[28]\); - - \r.e.op1_RNIOU8G[13]\ : OR2B - port map(A => \op1[13]\, B => un14_casaen_s1_0, Y => - \op1_m_0[13]\); - - \r.e.shleft_1_RNIQNBN2\ : MX2B - port map(A => \shiftin_5[36]\, B => \shiftin_5[20]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[20]\); - - \r.m.ctrl.pc[22]\ : DFN1E0 - port map(D => \pc_2[22]\, CLK => lclk_c, E => holdn, Q => - \pc_3[22]\); - - \r.e.ctrl.inst[21]\ : DFN1E0 - port map(D => \inst_2[21]\, CLK => lclk_c, E => holdn, Q - => \inst_1[21]\); - - \r.d.pv_RNO_0\ : NOR3C - port map(A => N_4241_i_0, B => pv_0, C => N_4242, Y => pv_2); - - \r.e.ctrl.inst_RNI2P1S[22]\ : NOR3A - port map(A => aluresult_12_sqmuxa_4, B => \inst_1[22]\, C - => \inst_0[23]\, Y => un1_icc_2_sqmuxa_1); - - \r.e.op1_RNIFU3U1[4]\ : OA1A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[4]\, C => - \op1_i_m[4]\, Y => \edata2_0_iv_0[4]\); - - \r.e.ldbp2_1_RNICD8GS2\ : MX2C - port map(A => \un6_ex_add_res_s1_i[19]\, B => N_6638, S => - ldbp2_1, Y => \eaddress[18]\); - - \r.m.ctrl.tt[1]\ : DFN1E0 - port map(D => \tt_3[1]\, CLK => lclk_c, E => holdn, Q => - \tt_2[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I157_un1_Y : NAND2 - port map(A => N561_i, B => N568, Y => I157_un1_Y_i); - - \r.m.y[31]\ : DFN1E0 - port map(D => \y_0[31]\, CLK => lclk_c, E => holdn, Q => - \y[31]\); - - \r.x.npc_RNI65VI[0]\ : MX2C - port map(A => N_3216, B => N_3246, S => \npc[0]\, Y => - \xc_result[5]\); - - \r.e.aluop_RNIN0RF4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[24]\, Y => - \aluop_RNIN0RF4[1]\); - - \r.w.result[10]\ : DFN1E0 - port map(D => \wdata[10]\, CLK => lclk_c, E => holdn, Q => - \result_0[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I195_Y : AO1A - port map(A => N599_1, B => N606_1, C => N598_1, Y => N664_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I319_Y_0_0 : XOR2 - port map(A => \op2[28]\, B => \un1_iu0_6[28]\, Y => - ADD_33x33_fast_I319_Y_0_0); - - \r.e.jmpl_RNI5K9661\ : AOI1B - port map(A => \shiftin_17[5]\, B => aluresult_1_sqmuxa_0, C - => \aluresult_1_iv_6[4]\, Y => \aluresult_1_iv_7[4]\); - - \r.e.op2_RNO_3[7]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[7]\, Y - => \aluresult_m_i[7]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_10\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I107_un1_Y : OR2B - port map(A => N508_1, B => N505_1, Y => I107_un1_Y_i); - - \r.e.op2_RNO_1[31]\ : OR2B - port map(A => \op1[31]\, B => un14_casaen_s1, Y => - \op1_m_i[31]\); - - \r.e.jmpl_RNIN2MUS_0\ : OR2B - port map(A => \shiftin_17[24]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[24]\); - - \r.d.inst_0_RNIOSIB[21]\ : OR3B - port map(A => un4_op3, B => un54_casaen, C => call_hold7_i, - Y => hold_pc_0_sqmuxa_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I109_Y\ : NOR3C - port map(A => N407_0, B => N410, C => - ADD_30x30_fast_I109_Y_0, Y => N529); - - un6_fe_npc_I_69 : AND3 - port map(A => \fe_pc[11]\, B => \fe_pc[12]\, C => - \fe_pc[13]\, Y => \DWACT_FINC_E[7]\); - - \r.x.ctrl.pc_RNI4AGF[10]\ : MX2 - port map(A => \pc[10]\, B => \pc_0[10]\, S => \npc_0[1]\, Y - => N_3221); - - \r.e.op2_RNO_7[10]\ : OA1A - port map(A => \maddress[10]\, B => d27, C => \cpi_m_i[362]\, - Y => \d_1_iv_1[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I301_Y_0 : XNOR3 - port map(A => \un1_iu0_6[10]\, B => \op2[10]\, C => N811_1, - Y => \un6_ex_add_res_s1_i[11]\); - - \r.x.result_RNIGR0QJ[2]\ : AOI1B - port map(A => \bpdata[2]\, B => N_3957, C => - \aluresult_2_iv_5[2]\, Y => \aluresult_2_iv_6[2]\); - - \r.m.y_RNO_1[22]\ : AOI1B - port map(A => \y[22]\, B => y08_0, C => \y_m[23]\, Y => - \y_iv_0[22]\); - - \r.m.ctrl.pc[16]\ : DFN1E0 - port map(D => \pc[16]\, CLK => lclk_c, E => holdn, Q => - \pc_3[16]\); - - \r.d.inst_0_0_0_RNI7IM7[21]\ : OR2A - port map(A => \un1_p0_6_0[60]\, B => \inst_0_0[22]\, Y => - un4_op_0); - - \r.d.annul_RNIN67I\ : NOR3C - port map(A => un19_inst, B => annul_next_1_sqmuxa_1_4, C - => hold_pc_1_sqmuxa, Y => annul_next_1_sqmuxa_1_6); - - \comb.branch_address.tmp_ADD_30x30_fast_I127_Y\ : OR2B - port map(A => N492, B => N488_1, Y => N547); - - \r.a.rfe1_RNI917BR\ : MX2 - port map(A => rfe_1, B => \rfe1\, S => holdn, Y => ren1); - - \r.x.data_0_RNO_0[25]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_25, Y => - \dco_m_1[121]\); - - \r.e.aluop_RNIVELC2[1]\ : OR2A - port map(A => N_3703_i, B => edata_2_sqmuxa, Y => N_3687); - - un6_ex_add_res_d2_ADD_33x33_fast_I197_un1_Y : OR3C - port map(A => N535_1, B => ADD_33x33_fast_I138_Y_0_0, C => - N608_0, Y => I197_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I305_Y_0 : XNOR3 - port map(A => \un1_iu0_6[14]\, B => \op2[14]\, C => N799_0, - Y => \un6_ex_add_res_s1_i[15]\); - - \r.d.inst_0_RNIF88C[21]\ : OR3C - port map(A => un8_op3, B => N_89, C => un12_op3, Y => - un13_op3); - - \r.x.data_0_RNI3FS8[2]\ : XOR2 - port map(A => \data_0[2]\, B => invop2_0, Y => N_3306); - - \r.w.s.y_RNO_0[27]\ : NOR2A - port map(A => N_481, B => \result_0[27]\, Y => N_410); - - \r.m.casa_RNI8BU9_0\ : NOR2A - port map(A => casa, B => N_3355_1, Y => un17_casaen_0); - - \r.e.op1_RNI0JNF[14]\ : NOR2A - port map(A => un17_casaen_0_2, B => \op1[14]\, Y => - \op1_i_m[14]\); - - \r.m.y_RNO[25]\ : AO1C - port map(A => y14_0, B => \logicout[25]\, C => \y_iv_2[25]\, - Y => \y_0[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I43_Y : MAJ3 - port map(A => \data_0[25]\, B => \un1_iu0_6[25]\, C => - N469_0, Y => N502_1); - - \r.f.pc_RNO_0[29]\ : NAND2 - port map(A => \tmp[29]\, B => un2_rstn_5_0, Y => - \tmp_m[29]\); - - \r.x.result[22]\ : DFN1E0 - port map(D => \maddress[22]\, CLK => lclk_c, E => holdn, Q - => \result_0[22]\); - - \r.e.op2_RNO_2[7]\ : NOR3C - port map(A => \d_1_iv_1[7]\, B => \d_1_iv_0[7]\, C => - \rfo_m_i[39]\, Y => \d_1_iv_3[7]\); - - \r.e.op1_RNID1VH[19]\ : MX2 - port map(A => \op1[19]\, B => \data_0[19]\, S => ldbp1_2, Y - => \op1_RNID1VH[19]\); - - \r.e.aluop_RNI2JHJ1[2]\ : XA1 - port map(A => \un1_iu0_5[76]\, B => \aluop_1[2]\, C => - \un1_iu0_6[10]\, Y => N_3537); - - \r.d.inull_RNIPRHA_0\ : NOR3B - port map(A => un19_inst, B => annul_next_2_sqmuxa_1_0, C - => call_hold5_0, Y => annul_next_2_sqmuxa_1_2); - - un6_fe_npc_I_104 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \DWACT_FINC_E[11]\, Y => N_78); - - \r.m.dci.write_RNO_1\ : NOR2A - port map(A => \inst_1[21]\, B => \inst_1[22]\, Y => - write_3_0_a3_0_2_0); - - \r.w.s.tt_RNIF7EJ3[1]\ : AOI1B - port map(A => aluresult_12_sqmuxa_0_0, B => \irl[1]\, C => - \aluresult_1_iv_2[5]\, Y => \aluresult_1_iv_4[5]\); - - \r.a.ctrl.inst_RNIB8549[30]\ : NOR3C - port map(A => N_451, B => \aop2_i_o2_2[0]\, C => N_452, Y - => N_6697_i_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I28_P0N : OR3A - port map(A => \data_0[27]\, B => \op1[27]\, C => ldbp1_0, Y - => N479_1); - - \r.e.op2_RNO_5[28]\ : AOI1B - port map(A => \result[28]\, B => d31_0, C => \imm_m_i[28]\, - Y => \d_1_iv_0[28]\); - - \r.e.op2_RNIBDIG[7]\ : MX2 - port map(A => \op2[7]\, B => N_4254, S => ldbp2_0, Y => - \un1_iu0_5[73]\); - - \r.a.ctrl.cnt_RNI7NUN[0]\ : OR2A - port map(A => N_219, B => N_212, Y => N_456); - - \r.a.ctrl.wreg_RNIGHAIA\ : AOI1 - port map(A => wreg_6, B => un2_rs1_NE_i_0, C => rs1, Y => - rfe_1_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I239_un1_Y\ : NOR3C - port map(A => N581, B => N597, C => N612, Y => I239_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I165_un1_Y : NOR2 - port map(A => N569, B => N576, Y => I165_un1_Y); - - \r.e.op2_RNO_0[11]\ : OR3C - port map(A => \op1_m_i[11]\, B => \d_1_iv_3[11]\, C => - \aluresult_m_i[11]\, Y => \d_1[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I4_G0N\ : NOR2B - port map(A => \inst_0_RNI4VUM[4]\, B => \dpc[6]\, Y => N370); - - \r.e.ctrl.rd_RNI5CCC2[5]\ : XNOR2 - port map(A => \un3_de_ren1[104]\, B => \rd[5]\, Y => - un1_de_ren1_5_i_0); - - \r.m.wcwp_RNO\ : NOR2 - port map(A => annul, B => un3_op_i, Y => wcwp_0); - - \r.a.ctrl.inst_RNII02L_0[24]\ : OR2 - port map(A => \inst_1[24]\, B => N_207, Y => N_433); - - \r.f.pc_RNO_7[12]\ : MX2 - port map(A => \fpc[12]\, B => \tba[0]\, S => - rstate_6314_d_0, Y => \xc_trap_address[12]\); - - \r.e.op1[10]\ : DFN1E0 - port map(D => \aop1[10]\, CLK => lclk_c, E => holdn, Q => - \op1[10]\); - - \r.m.y_RNO_4[13]\ : OR2B - port map(A => \y_0[14]\, B => mulstep_0, Y => \y_m[14]\); - - \r.e.aluop_RNIMPHR1[1]\ : OR2 - port map(A => aluresult_5_sqmuxa, B => aluresult_4_sqmuxa, - Y => N_3957_1); - - un6_fe_npc_I_66 : XOR2 - port map(A => N_106, B => \fe_pc[13]\, Y => I_66); - - \r.e.ldbp2_RNIV9NBU2\ : MX2C - port map(A => \un6_ex_add_res_s1_i[20]\, B => N_6654, S => - ldbp2_3, Y => \eaddress[19]\); - - \r.d.inst_0_RNI0QP8[29]\ : OR2B - port map(A => I_13_3, B => N_3525_3, Y => \de_raddr1_1[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I128_Y : NOR2A - port map(A => N529_2, B => N525_0, Y => N591_1); - - \r.e.shleft_1_RNIDVBG\ : NOR2A - port map(A => \un1_iu0_6[8]\, B => shleft_1, Y => - shleft_1_RNIDVBG); - - \r.d.inst_0_RNIQE58[27]\ : MX2C - port map(A => branch_2_i, B => branch_6_i, S => - \inst_0[27]\, Y => N_3349); - - \r.d.pc_RNI46HB4[27]\ : MX2 - port map(A => \dpc[27]\, B => \fpc[27]\, S => ra_bpmiss_1, - Y => N_3904); - - \r.e.shleft_RNIEIRJ\ : OR2A - port map(A => \un1_iu0_6[24]\, B => shleft, Y => - \shiftin_5[24]\); - - \r.d.inst_0_RNIDEJ4[29]\ : NOR2B - port map(A => \inst_0[29]\, B => N_85, Y => N_79); - - \r.a.rsel1_RNIHM4G85[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[18]\, Y => - \aluresult_m_0[18]\); - - \r.f.pc_RNIO5OJ62[9]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[9]\, C => - \pc_m[9]\, Y => \npc_iv_1[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I154_un1_Y\ : NOR3C - port map(A => N462, B => N_14, C => N528, Y => I154_un1_Y); - - \r.e.aluop_0_RNIG5791[1]\ : XOR3 - port map(A => \un1_iu0_6[28]\, B => \aluop_0[1]\, C => - \un1_iu0_5[94]\, Y => N_6874); - - \r.e.shleft_RNIEQEC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[12]\, S => - shleft, Y => \shiftin_5[43]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I272_Y_0_0\ : XOR2 - port map(A => \dpc[14]\, B => \un1_p0_6_0[51]\, Y => - ADD_30x30_fast_I272_Y_0_0); - - un6_fe_npc_I_83 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[8]\, Y => N_93); - - \r.d.inull_RNO_3\ : NOR2A - port map(A => jmpl, B => annul, Y => jmpl_1); - - un6_fe_npc_I_195 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[23]\, Y => N_14_0); - - \r.m.werr_RNO\ : NOR3B - port map(A => rst, B => trap_0_sqmuxa_7, C => werr_1, Y => - werr_RNO); - - \r.e.aluop_0_RNI5D6R[1]\ : MX2C - port map(A => \logicout_4[9]\, B => N_6841, S => N_6866_i_0, - Y => N_3632); - - \r.d.pc_RNI86HB4[29]\ : MX2 - port map(A => \dpc[29]\, B => \fpc[29]\, S => ra_bpmiss_1, - Y => N_3906); - - \comb.branch_address.tmp_ADD_30x30_fast_I232_un1_Y\ : OR3C - port map(A => N567_1, B => N583, C => N729, Y => I232_un1_Y); - - \r.x.ctrl.pc[9]\ : DFN1E0 - port map(D => \pc_3[9]\, CLK => lclk_c, E => holdn, Q => - \pc_2[9]\); - - \r.w.s.y[5]\ : DFN1E0 - port map(D => N_3769, CLK => lclk_c, E => N_6922_i, Q => - \y[5]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I28_G0N : NOR2A - port map(A => \un1_iu0_6[27]\, B => \data_0[27]\, Y => - N478_1); - - \r.m.icc_RNITN961[1]\ : OR2A - port map(A => \icc[1]\, B => aluresult_11_sqmuxa, Y => - \icc_m[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I63_Y_0_a3 : NOR3C - port map(A => \op2[14]\, B => \un1_iu0_6[14]\, C => N443, Y - => N_53); - - un6_ex_add_res_d0_ADD_33x33_fast_I22_G0N : NOR3A - port map(A => \op1[21]\, B => ldbp1_2, C => \data_0[21]\, Y - => N460_1); - - \r.x.result_RNIVKAN3[18]\ : MX2 - port map(A => \un1_iu0_6[18]\, B => \un1_p0_6[370]\, S => - bpdata6, Y => \bpdata[18]\); - - \r.x.ctrl.pc[17]\ : DFN1E0 - port map(D => \pc_3[17]\, CLK => lclk_c, E => holdn, Q => - \pc_2[17]\); - - \r.w.result[16]\ : DFN1E0 - port map(D => \wdata[16]\, CLK => lclk_c, E => holdn, Q => - \result[16]\); - - \r.a.ctrl.pc[15]\ : DFN1E0 - port map(D => \dpc[15]\, CLK => lclk_c, E => holdn, Q => - \pc[15]\); - - \r.w.result_RNIO7QL[25]\ : AOI1B - port map(A => \un1_p0_6[377]\, B => d14_0, C => - \result_m_0_0[25]\, Y => \d_iv_0[25]\); - - \r.f.pc_RNO_3[17]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[17]\, C => - \xc_trap_address_m[17]\, Y => \pc_1_iv_0[17]\); - - \r.a.ctrl.inst_RNIJ02S[21]\ : OR3A - port map(A => N_256_i_0, B => \inst_2[20]\, C => - \inst_2[21]\, Y => illegal_inst11_0_a5_0); - - \r.e.op2_RNO_4[12]\ : NOR3C - port map(A => \result_m_i[12]\, B => \imm_m_i[12]\, C => - \d_1_iv_1[12]\, Y => \d_1_iv_2[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I87_Y\ : NOR3A - port map(A => N452, B => N440_2, C => N443_2, Y => N507); - - \r.w.s.y_RNO[17]\ : MX2 - port map(A => \y_2[17]\, B => \result_0[17]\, S => N_481_0, - Y => N_3781); - - \r.e.op1_RNIC8HP7[13]\ : OR3 - port map(A => \ex_op1_i_m[13]\, B => \op1_i_m[13]\, C => - \bpdata_i_m[13]\, Y => \edata2_0_iv_1[13]\); - - \r.d.pc[9]\ : DFN1 - port map(D => \pc_RNO[9]\, CLK => lclk_c, Q => \dpc[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I112_Y : NOR3C - port map(A => N461, B => N464_2, C => N513_0, Y => N575_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I155_un1_Y : OR3B - port map(A => N493_0, B => N566_0, C => N497_2, Y => - I155_un1_Y_1); - - \r.w.s.tba_RNI94CA1[8]\ : OR2B - port map(A => \tba[8]\, B => aluresult_12_sqmuxa_0_0, Y => - \tba_m[8]\); - - \r.d.inst_0_RNIMO2O8[23]\ : OR2B - port map(A => un2_rs1_NE_i_0, B => ldcheck1, Y => - un1_ldcheck1); - - \r.w.s.tt_RNIIBEJ3[2]\ : AOI1B - port map(A => aluresult_12_sqmuxa_0_0, B => \irl[2]\, C => - \aluresult_1_iv_2[6]\, Y => \aluresult_1_iv_4[6]\); - - \r.m.icc_RNO_17[2]\ : NOR2A - port map(A => \logicout[23]\, B => \logicout[31]\, Y => - icc_0_sqmuxa_1_16); - - \r.e.aluop_0_RNILHN3[1]\ : OR2A - port map(A => \aluop_0[2]\, B => \aluop_0[1]\, Y => - N_6866_i_0); - - \r.e.ldbp2_RNI1LI304\ : MX2C - port map(A => \un6_ex_add_res_s1_i[25]\, B => N_6571, S => - ldbp2_3, Y => \eaddress[24]\); - - \r.e.ctrl.pc_RNI6PFM7[9]\ : NOR3C - port map(A => \tt_m[5]\, B => \aluresult_1_iv_1[9]\, C => - \bpdata_m_2[1]\, Y => \aluresult_1_iv_5[9]\); - - \r.e.aluop_RNI5O511[2]\ : XA1 - port map(A => \un1_iu0_5[69]\, B => \aluop_1[2]\, C => - \un1_iu0_6[3]\, Y => N_3530); - - \r.a.ctrl.inst_RNIMGCC[28]\ : AX1A - port map(A => \icc_0[2]\, B => N_211, C => \inst_1[28]\, Y - => branch_3); - - \r.x.result_RNII6E25[7]\ : NOR2 - port map(A => \bpdata[7]\, B => N_3703_i, Y => - \bpdata_i_m_1[7]\); - - \r.e.aluop_0_RNIOO306[0]\ : MX2C - port map(A => N_3575, B => N_3639, S => \aluop_0[0]\, Y => - \logicout[16]\); - - \r.x.result_RNIO9S65[7]\ : OR2B - port map(A => \bpdata[7]\, B => N_3957_1, Y => - \bpdata_m_1[7]\); - - \r.w.result_RNI60P1[12]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[12]\, - Y => \result_m_0_0[12]\); - - \r.e.jmpl_RNICH3L22\ : OR3C - port map(A => \aluresult_2_iv_7[2]\, B => - \shiftin_17_m_0[2]\, C => jmpl_RNIR18H6, Y => - \aluresult[2]\); - - \r.a.rsel1_0_RNI73LJ2[2]\ : OR2B - port map(A => data1(10), B => d11, Y => \rfo_m[10]\); - - \r.a.ctrl.rd[2]\ : DFN1E0 - port map(D => \rd_2[2]\, CLK => lclk_c, E => holdn, Q => - \rd[2]\); - - \r.a.ctrl.inst[10]\ : DFN1E0 - port map(D => \inst_0[10]\, CLK => lclk_c, E => holdn, Q - => \inst[10]\); - - \r.m.y_RNO_1[10]\ : AOI1B - port map(A => \y_0[10]\, B => y08_0, C => \y_m_0[11]\, Y - => \y_iv_0[10]\); - - \r.e.jmpl_RNICI5ES1\ : AOI1B - port map(A => \shiftin_17[32]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[31]\, Y => \aluresult_1_iv_8[31]\); - - \r.x.data_0_RNIDVN8[3]\ : MX2 - port map(A => \op1[3]\, B => \data_0[3]\, S => ldbp1_4, Y - => \un1_iu0_6[3]\); - - un6_fe_npc_I_165 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[18]\, Y => N_35_0); - - \r.x.data_0_RNO_2[24]\ : AO1B - port map(A => rdatav_0_1_0_iv_5_6, B => mcdo_m_0_22, C => - rdata_6_sqmuxa, Y => \dco_m_1_i[120]\); - - \r.e.aluop_0_RNIR3AK2[1]\ : MX2C - port map(A => \logicout_4[28]\, B => N_6874, S => - N_6866_i_0, Y => N_3651); - - \r.e.op2_RNO_3[25]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[25]\, Y => - \aluresult_m_i[25]\); - - \r.x.data_0_RNO_0[14]\ : NOR2B - port map(A => N_3473, B => data_0_2_14, Y => \dco_m_0[110]\); - - \r.a.rsel1_RNI1RFA_0[0]\ : NOR2B - port map(A => un17_casaen_0, B => N_494, Y => - un14_casaen_s1_0); - - \r.a.ctrl.inst_RNIFO1E[23]\ : NOR2B - port map(A => \inst_1[23]\, B => \inst_2[19]\, Y => - inst_32_0); - - \r.e.op2_RNIH11O85[0]\ : OR3C - port map(A => \op2_RNI1LHG[1]\, B => \op2_RNI59C6[0]\, C - => \icc_8_1[1]\, Y => \icc_8[1]\); - - \r.x.result[14]\ : DFN1E0 - port map(D => \maddress[14]\, CLK => lclk_c, E => holdn, Q - => \result_0[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I180_Y\ : AO1A - port map(A => N547, B => N554, C => N546_1, Y => N606); - - \r.x.data_0_RNO[10]\ : OR3B - port map(A => \data_0_1_0_iv_1[10]\, B => \dco_m_0_i[106]\, - C => \data_0_1_1[12]\, Y => \data_0_1[10]\); - - \r.e.op1[29]\ : DFN1E0 - port map(D => \aop1[29]\, CLK => lclk_c, E => holdn, Q => - \op1[29]\); - - \r.a.rsel2_RNI9LB_3[1]\ : NOR2 - port map(A => \rsel2[2]\, B => \rsel2[1]\, Y => d26_0); - - \r.a.rsel1_0_RNIE7LJ2[2]\ : OR2B - port map(A => data1(24), B => d11_0, Y => \rfo_m[24]\); - - \r.a.et\ : DFN1E0 - port map(D => et_2, CLK => lclk_c, E => holdn, Q => et_1); - - \r.e.ctrl.tt_RNO_1[2]\ : OR3 - port map(A => ticc, B => wunf, C => wovf, Y => - \tt_9_i_a4_0[2]\); - - \r.d.inst_0_RNO[5]\ : NOR2B - port map(A => rst, B => N_4605, Y => \inst_0_RNO[5]\); - - \r.d.cnt[0]\ : DFN1E1 - port map(D => cnt_2_sqmuxa, CLK => lclk_c, E => N_6825_i, Q - => \cnt_2[0]\); - - \comb.ld_align.rdata199_RNI46JTI_0\ : NOR2A - port map(A => rdata_2_sqmuxa_0, B => rdata199, Y => - rdata_2_sqmuxa_1); - - \r.m.ctrl.inst_RNIDP678[30]\ : OR2 - port map(A => \inst_RNIVASI1[30]\, B => trap_1_sqmuxa, Y - => un1_trap_1_sqmuxa); - - \r.d.inst_0_RNIKC392[4]\ : NOR2B - port map(A => I_13_1, B => un1_reg, Y => \un3_de_ren1[104]\); - - \r.x.data_0_RNO_0[13]\ : NOR2B - port map(A => N_3473, B => data_0_2_13, Y => \dco_m_0[109]\); - - \r.e.op2_RNI1PJF75_0[31]\ : AO16 - port map(A => \un1_iu0_6[31]\, B => \un1_iu0_5[97]\, C => - \eaddress[31]\, Y => \icc_2[1]\); - - \r.f.pc_RNO[21]\ : OR3C - port map(A => \tmp_m[21]\, B => \pc_1_iv_1[21]\, C => - \un6_fe_npc_m[19]\, Y => \pc_1[21]\); - - \r.a.ctrl.inst_RNI013H1_0[21]\ : OR3 - port map(A => inst_9_3, B => N_241, C => N_204, Y => N_359); - - \r.e.op1_RNIC3O8[4]\ : MX2 - port map(A => \op1[4]\, B => \data_0[4]\, S => ldbp1_1, Y - => \un1_iu0_6[4]\); - - \r.a.bp_RNIKBBRB\ : NOR2B - port map(A => ra_bpmiss_1, B => ex_bpmiss_1, Y => - bpmiss_1_i_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I24_P0N : OR3A - port map(A => \data_0[23]\, B => \op1[23]\, C => ldbp1, Y - => N467_2); - - \r.e.aluop_0[1]\ : DFN1E0 - port map(D => \aluop[1]\, CLK => lclk_c, E => holdn, Q => - \aluop_0[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I246_Y_0_a3 : NOR2B - port map(A => N808_0, B => N431_1, Y => - ADD_33x33_fast_I246_Y_0_a3_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I189_un1_Y : OR2B - port map(A => N600, B => N593, Y => I189_un1_Y_i); - - \r.m.result_RNIOIRC3[8]\ : NOR3C - port map(A => \d_iv_0[8]\, B => \result_m_0[8]\, C => - \rfo_m[8]\, Y => \d_iv_2[8]\); - - \r.d.pc_RNO[19]\ : MX2 - port map(A => \fpc[19]\, B => \dpc[19]\, S => N_6763_i, Y - => \pc_RNO[19]\); - - \r.w.s.icc_RNO[3]\ : AO1B - port map(A => icc_1_sqmuxa, B => \icc_0[3]\, C => - \icc_1_iv_0[3]\, Y => \icc_1[3]\); - - \r.e.op2_RNO_1[24]\ : OR2B - port map(A => \op1[24]\, B => un14_casaen_s1, Y => - \op1_m_i[24]\); - - \r.x.result[6]\ : DFN1E0 - port map(D => \maddress[6]\, CLK => lclk_c, E => holdn, Q - => \result_0[6]\); - - \r.w.s.wim_RNI75RD2[1]\ : OR2B - port map(A => \wim[1]\, B => aluresult_13_sqmuxa, Y => - \wim_m[1]\); - - \r.a.ctrl.inst_RNI7K0E[21]\ : OR2 - port map(A => \inst[22]\, B => \inst_2[21]\, Y => N_492); - - \r.e.op2_RNI33A92[15]\ : AOI1B - port map(A => \un1_iu0_5[81]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[15]\); - - \r.e.shcnt_RNIGTEB5[3]\ : MX2 - port map(A => \shiftin_8[18]\, B => \shiftin_8[10]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I96_Y : NOR3B - port map(A => N485, B => N488_2, C => N497_0, Y => N559); - - \r.m.y_RNO_2[18]\ : OR2B - port map(A => \y_1[18]\, B => y08, Y => N_394); - - \r.e.op2_RNO_0[27]\ : OR3C - port map(A => \op1_m_i[27]\, B => \d_1_iv_3[27]\, C => - \aluresult_m_i[27]\, Y => \d_1[27]\); - - \r.x.ctrl.pc_RNIB2HF[13]\ : MX2 - port map(A => \pc_0[13]\, B => \pc_2[13]\, S => \npc_1[1]\, - Y => N_3224); - - \r.e.op1_RNIVANF[22]\ : NOR2A - port map(A => \un17_casaen_0_0\, B => \op1[22]\, Y => - \op1_i_m[22]\); - - \r.e.aluop_0_RNIP8ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[22]\, B => \aluop_0[1]\, C => - \un1_iu0_5[88]\, Y => N_6862); - - \r.a.ctrl.inst_RNIFK1L[20]\ : NOR2B - port map(A => \inst_2[20]\, B => N_225, Y => - aluop_0_1_0_a5_0); - - \r.x.data_0[7]\ : DFN1E0 - port map(D => \data_0_1[7]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0_2[7]\); - - \r.w.s.wim_RNIB4JO5[0]\ : NOR2A - port map(A => \aluresult_2_iv_0[0]\, B => \aluresult_4[1]\, - Y => \aluresult_2_iv_2[0]\); - - \r.a.imm[27]\ : DFN1E0 - port map(D => \un3_de_ren1[145]\, CLK => lclk_c, E => holdn, - Q => \imm[27]\); - - \r.e.ctrl.pc_RNIMR011[2]\ : OR2B - port map(A => \pc_2[2]\, B => jmpl_4, Y => \cpi_m[147]\); - - \r.m.y_RNO_3[22]\ : OR3A - port map(A => \y_2[22]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[22]\); - - \r.e.aluop_RNIK26I6[0]\ : MX2C - port map(A => N_3586, B => N_3650, S => \aluop_1[0]\, Y => - \logicout[27]\); - - \r.f.pc_RNO_1[23]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[23]\, C => - \pc_1_iv_0[23]\, Y => \pc_1_iv_1[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I125_Y_0\ : OA1 - port map(A => \dpc[8]\, B => \inst_0[6]\, C => N380, Y => - ADD_30x30_fast_I125_Y_0); - - \r.d.inst_0[8]\ : DFN1 - port map(D => \inst_0_RNO[8]\, CLK => lclk_c, Q => - \inst_0[8]\); - - \r.x.mexc_RNIGSPT\ : OR2 - port map(A => mexc_0, B => N_3322, Y => \xc_vectt_1[3]\); - - \r.a.ctrl.rd_RNIRU2V[0]\ : XNOR2 - port map(A => \rs1_iv_i_0[0]\, B => \rd_2[0]\, Y => - un2_rs1_0_i); - - \r.x.ctrl.pc_RNI04I61[14]\ : MX2C - port map(A => \un1_p0_6[366]\, B => \pc_0[14]\, S => - s_3_sqmuxa_0, Y => N_3405); - - \r.w.s.tba[6]\ : DFN1E1 - port map(D => \result_0[18]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[6]\); - - \r.e.op1_RNI6CMO6[20]\ : AO1A - port map(A => \un1_iu0_6[20]\, B => edata_3_sqmuxa_0, C => - \edata2_0_iv_0[20]\, Y => \edata2_0_iv_1[20]\); - - \r.e.jmpl_RNIUM1833\ : OR3C - port map(A => \aluresult_1_iv_8[10]\, B => - \shiftin_17_m_0[10]\, C => \un6_ex_add_res_m[11]\, Y => - \aluresult[10]\); - - un6_fe_npc_I_51 : NOR2B - port map(A => \fe_pc[10]\, B => \DWACT_FINC_E[4]\, Y => - N_116); - - \r.m.ctrl.pc[15]\ : DFN1E0 - port map(D => \pc_2[15]\, CLK => lclk_c, E => holdn, Q => - \pc_3[15]\); - - \r.e.op2_RNO[8]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[8]\, Y => N_292); - - un6_ex_add_res_d2_ADD_33x33_fast_I179_Y : AO1 - port map(A => N590_1, B => N583_2, C => N582_2, Y => N648_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_o3_1_0 : AO18 - port map(A => N397, B => \data_0[1]\, C => \un1_iu0_6[1]\, - Y => ADD_33x33_fast_I206_Y_0_o3_1_0); - - \r.a.ctrl.pc_RNIJOL0C[6]\ : MX2 - port map(A => \pc_0[6]\, B => N_3883, S => ex_bpmiss_1_0, Y - => \fe_pc[6]\); - - \r.e.alusel_RNO_0[0]\ : OA1A - port map(A => N_226, B => N_204, C => \alusel_i_0_1[0]\, Y - => \alusel_i_0_2[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I110_un1_Y\ : NOR2B - port map(A => N475, B => N472, Y => I110_un1_Y); - - \comb.v.x.data_0_1_1_iv_2[19]\ : OR2 - port map(A => \rdata_5_m_9[8]\, B => \rdata_13_m_9[8]\, Y - => \data_0_1_2[17]\); - - \r.e.aluop_RNI4VJD4[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[24]\, Y => - \bpdata_i_m[24]\); - - \r.e.jmpl_RNI221OS\ : OR2B - port map(A => \shiftin_17[25]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[25]\); - - \r.d.inst_0_RNO_0[30]\ : MX2 - port map(A => data_0_2_30, B => \inst_0[30]\, S => - inull_RNIFV6VG2_0, Y => N_4630); - - \r.e.op1_RNI5HUH[15]\ : MX2 - port map(A => \op1[15]\, B => \data_0_2[15]\, S => ldbp1_2, - Y => \un1_iu0_6[15]\); - - \r.f.pc_RNO_7[27]\ : MX2 - port map(A => \fpc[27]\, B => \tba[15]\, S => - rstate_6314_d_0, Y => \xc_trap_address[27]\); - - un6_fe_npc_I_27 : AND2 - port map(A => \fe_pc[5]\, B => \fe_pc[6]\, Y => - \DWACT_FINC_E[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I17_G0N : NOR3A - port map(A => \op1[16]\, B => ldbp1_4, C => \data_0[16]\, Y - => N445_0); - - \r.e.shcnt_RNITNFBC[2]\ : MX2C - port map(A => \shiftin_11[22]\, B => \shiftin_11[18]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[18]\); - - \r.w.s.tba[3]\ : DFN1E1 - port map(D => \result_0[15]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[3]\); - - \r.x.rstate_0_RNI40DE1[0]\ : OA1A - port map(A => rstate_1188n, B => holdn, C => N_6322, Y => - N_6322s); - - \r.e.op2_RNO_4[28]\ : OA1A - port map(A => \maddress[28]\, B => d27_0, C => - \cpi_m_i[380]\, Y => \d_1_iv_1[28]\); - - \r.e.ctrl.pc[14]\ : DFN1E0 - port map(D => \pc[14]\, CLK => lclk_c, E => holdn, Q => - \pc_1[14]\); - - \r.a.ctrl.pc_RNIUBE2C[30]\ : MX2 - port map(A => \pc[30]\, B => N_3907, S => ex_bpmiss_1_0, Y - => \fe_pc[30]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I271_un1_Y : OR3C - port map(A => N649, B => N665_1, C => N614_2, Y => - I271_un1_Y_i_0); - - \r.e.ctrl.tt_RNO[1]\ : OA1B - port map(A => N_16735_tz, B => N_4033_i, C => \tt_0[1]\, Y - => \tt_1[1]\); - - \r.m.icc_RNI68I3[0]\ : OR2 - port map(A => \icc_0[2]\, B => \icc_0[0]\, Y => N_375); - - \r.e.shleft_RNI7ERJ\ : NOR2A - port map(A => \un1_iu0_6[14]\, B => shleft, Y => - \shiftin_5_i[14]\); - - \r.d.pv_RNO_8\ : OR3B - port map(A => annul_2, B => \de_hold_pc_1\, C => - \inst_2[29]\, Y => N_4239); - - \r.x.ctrl.wicc\ : DFN1E0 - port map(D => wicc_1_2, CLK => lclk_c, E => holdn, Q => - wicc); - - \r.d.cnt_RNIIB6B[1]\ : NOR2A - port map(A => un5_op3, B => \cnt_0[1]\, Y => - ldcheck1_1_sqmuxa_1); - - \r.a.rsel1_RNIEQG766[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[23]\, Y - => \aluresult_m_0[23]\); - - \r.e.op2_RNO_9[9]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[361]\, Y => \cpi_m_i[361]\); - - \r.x.ctrl.tt[2]\ : DFN1E0 - port map(D => \tt2[2]\, CLK => lclk_c, E => holdn, Q => - \tt[2]\); - - \r.e.op1_RNIK04F[2]\ : OR2B - port map(A => \op1[2]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[2]\); - - \r.e.cwp_RNIFT8H3[2]\ : NOR3C - port map(A => \cpi_m[147]\, B => \y_m_1[2]\, C => - \cwp_m[2]\, Y => \aluresult_2_iv_3[2]\); - - \r.e.op1_RNIN2TR3[4]\ : NOR3C - port map(A => \rfo_m[4]\, B => \d_iv_1[4]\, C => - \op1_m_0[4]\, Y => \d_iv_3[4]\); - - \r.e.op2_RNIIGNB1[26]\ : OR2A - port map(A => \un1_iu0_5[92]\, B => \un1_iu0_6[26]\, Y => - \logicout_4[26]\); - - \r.x.y[4]\ : DFN1E0 - port map(D => \y[4]\, CLK => lclk_c, E => holdn, Q => - \y_1[4]\); - - \r.x.data_0_RNIIVG8[20]\ : XOR2 - port map(A => \data_0_2[20]\, B => invop2, Y => N_4267); - - \r.e.op2_RNO_6[27]\ : OR2B - port map(A => data2(27), B => d25, Y => \rfo_m_i[59]\); - - \r.d.pc_RNO[2]\ : MX2 - port map(A => \fpc[2]\, B => \dpc[2]\, S => N_6763_i_0, Y - => \pc_RNO[2]\); - - \r.e.invop2_1_RNI67J0N2\ : MX2C - port map(A => \un6_ex_add_res_s2[28]\, B => - \un6_ex_add_res_s0[28]\, S => invop2_1, Y => N_6574); - - \r.e.aluop_RNIBO773[1]\ : MX2C - port map(A => N_3546, B => \logicout_3[19]\, S => - \aluop_3[1]\, Y => N_3578); - - \r.d.inst_0_RNI9446[21]\ : NOR3C - port map(A => \inst_0[19]\, B => \inst_0_0[21]\, C => - icc_check9_2, Y => inst_0_2); - - \r.e.aluop_RNI575F1[2]\ : XA1 - port map(A => \un1_iu0_5[77]\, B => \aluop_1[2]\, C => - \un1_iu0_6[11]\, Y => N_3538); - - \r.a.ctrl.inst_RNI6G0E[22]\ : OR2B - port map(A => \inst[22]\, B => \inst_2[20]\, Y => N_271); - - \comb.branch_address.tmp_ADD_30x30_fast_I287_Y_0_0\ : XOR2 - port map(A => \dpc[29]\, B => \inst_0_RNI8AJ4[27]\, Y => - ADD_30x30_fast_I287_Y_0_0); - - \r.x.y[1]\ : DFN1E0 - port map(D => \y[1]\, CLK => lclk_c, E => holdn, Q => - \y_2[1]\); - - un6_fe_npc_I_76 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \fe_pc[14]\, Y => N_98); - - un6_ex_add_res_d0_ADD_33x33_fast_I314_Y_0 : XNOR2 - port map(A => N780, B => \un6_ex_add_res_s2_1[24]\, Y => - \un6_ex_add_res_s0[24]\); - - \r.e.aluop_2_RNI05613[1]\ : MX2C - port map(A => N_3543, B => \logicout_3[16]\, S => - \aluop_2[1]\, Y => N_3575); - - \r.x.data_0_RNO_1[10]\ : AO1B - port map(A => rdatav_0_1_0_iv_0_2(10), B => N_3305_0, C => - N_3473, Y => \dco_m_0_i[106]\); - - \r.x.ctrl.wy_RNILF1N3_1\ : NOR2 - port map(A => y_1_sqmuxa_1, B => y_1_sqmuxa_0, Y => N_481_0); - - \r.m.y_RNO_4[14]\ : OR2B - port map(A => \y[15]\, B => mulstep_1, Y => N_389); - - \r.f.pc_RNO_5[23]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[23]\, Y => \xc_trap_address_m[23]\); - - un6_fe_npc_I_192 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[22]\, Y => \DWACT_FINC_E[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I151_Y : AO1 - port map(A => N552_0, B => N549_1, C => N548, Y => N614_0); - - \dci.enaddr_1_sqmuxa_1_RNI3PQ961\ : MX2C - port map(A => enaddr_1_sqmuxa_1, B => \inst_1[21]\, S => - enaddr_2_sqmuxa, Y => \eenaddr\); - - \r.e.jmpl_RNIJIRLN2\ : OR3C - port map(A => \aluresult_1_iv_8[9]\, B => - \shiftin_17_m_0[9]\, C => \un6_ex_add_res_m[10]\, Y => - \aluresult[9]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I158_Y : NOR3A - port map(A => N495, B => N_50, C => N569, Y => N627_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I6_P0N\ : OR2 - port map(A => \inst_0[6]\, B => \dpc[8]\, Y => N377); - - \r.x.result[20]\ : DFN1E0 - port map(D => \maddress[20]\, CLK => lclk_c, E => holdn, Q - => \result[20]\); - - \r.f.pc_RNO_3[24]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[24]\, Y => - \pc_4_m[24]\); - - \r.m.y_RNO_3[15]\ : AOI1B - port map(A => \y[15]\, B => y08_0, C => \y_m[16]\, Y => - \y_iv_0[15]\); - - \r.a.ctrl.pc_RNIF4F2C[28]\ : MX2 - port map(A => \pc[28]\, B => N_3905, S => ex_bpmiss_1, Y - => \fe_pc[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I131_Y : AO1 - port map(A => N532_0, B => N529_1, C => N528_1, Y => N594_1); - - \r.m.ctrl.annul\ : DFN1E0 - port map(D => annul_1_1, CLK => lclk_c, E => holdn, Q => - annul_5); - - un6_ex_add_res_d1_ADD_33x33_fast_I138_Y : NOR3C - port map(A => N419_1, B => N416_1, C => N535_0, Y => N601); - - \r.x.result[19]\ : DFN1E0 - port map(D => \maddress[19]\, CLK => lclk_c, E => holdn, Q - => \result_0[19]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I147_Y : AOI1 - port map(A => N548_0, B => N545_0, C => N544_2, Y => N610_0); - - \r.f.pc_RNO_2[30]\ : OR2B - port map(A => I_203, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[28]\); - - \r.e.aluop_0_RNIK8ROQ[0]\ : NOR3C - port map(A => \aluresult_1_iv_5[26]\, B => - \aluresult_1_iv_4[26]\, C => \logicout_m_0[26]\, Y => - \aluresult_1_iv_7[26]\); - - \r.e.op2_RNO_1[15]\ : OR2B - port map(A => \op1[15]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[15]\); - - \r.e.jmpl_RNI60MO28\ : OR3C - port map(A => \aluresult_1_iv_8[31]\, B => - \shiftin_17_m_0[31]\, C => \un6_ex_add_res_m[32]\, Y => - \aluresult[31]\); - - \r.x.ctrl.inst_RNIVU2L[25]\ : NOR3 - port map(A => \inst[26]\, B => \inst[25]\, C => - \inst_1[29]\, Y => y_0_sqmuxa_2); - - un9_ra_I_9 : XOR2 - port map(A => \cwp_0[0]\, B => \inst_0[29]\, Y => - \DWACT_ADD_CI_0_partial_sum_1[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I271_un1_Y : OR3C - port map(A => N649_0, B => N665_0, C => N614_1, Y => - I271_un1_Y); - - \r.x.data_0[31]\ : DFN1E0 - port map(D => \data_0_1[31]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0_0[31]\); - - \r.e.aluop_2_RNIJBDM1[1]\ : MX2C - port map(A => N_3534, B => \logicout_3[7]\, S => - \aluop_2[1]\, Y => N_3566); - - \r.x.mexc_RNIAGPT\ : NOR2 - port map(A => mexc_0, B => N_3319, Y => \xc_vectt_1[0]\); - - \r.a.cwp[2]\ : DFN1E0 - port map(D => \cwp_0[2]\, CLK => lclk_c, E => holdn, Q => - \cwp_3[2]\); - - \r.x.data_0[17]\ : DFN1E0 - port map(D => \data_0_1[17]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[17]\); - - \r.m.ctrl.trap_RNIPFG4B\ : NOR2A - port map(A => un1_trap_1_sqmuxa, B => annul_3, Y => - tt_2_sqmuxa_1_0); - - \r.e.ctrl.trap_RNO_0\ : NOR3A - port map(A => trap_4_1_0, B => trap_4_1, C => N_4033_i, Y - => trap_4); - - un6_ex_add_res_d2_ADD_33x33_fast_I18_P0N : AO1A - port map(A => ldbp1_1, B => \op1[17]\, C => \data_0[17]\, Y - => N449_0); - - \r.e.shleft_1_RNI55IP\ : OR2A - port map(A => \un1_iu0_6[26]\, B => shleft_1, Y => - \shiftin_5[26]\); - - un6_fe_npc_I_136 : XOR2 - port map(A => N_56, B => \fe_pc[23]\, Y => I_136); - - \r.f.pc_RNO_4[18]\ : MX2 - port map(A => I_98, B => N_4061, S => bpmiss_1_i_0_0, Y => - \pc_4[18]\); - - \r.f.pc_RNIEG981[4]\ : MX2B - port map(A => \fpc[4]\, B => \xc_vectt_1[0]\, S => - rstate_6314_d, Y => \xc_trap_address[4]\); - - \r.e.op2_RNIMCB71[28]\ : OR2A - port map(A => \un1_iu0_5[94]\, B => \un1_iu0_6[28]\, Y => - \logicout_4[28]\); - - \r.e.jmpl_RNITT19R\ : OR2B - port map(A => \shiftin_17[20]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[20]\); - - \r.a.ctrl.wicc_RNO_4\ : AOI1 - port map(A => \un1_p0_6_0[60]\, B => un7_op_3, C => un3_op2, - Y => wicc_1_0_a3_0); - - \r.d.pc[26]\ : DFN1 - port map(D => \pc_RNO[26]\, CLK => lclk_c, Q => \dpc[26]\); - - \r.x.data_0_RNO[21]\ : OR3 - port map(A => \dco_m_0[117]\, B => \data_0_m[21]\, C => - \data_0_1_4[18]\, Y => \data_0_1[21]\); - - \r.e.jmpl_RNIRFSGR\ : NAND2 - port map(A => aluresult_1_sqmuxa_0, B => \shiftin_17[21]\, - Y => \shiftin_17_m[21]\); - - \r.e.mulstep_RNI8VGC_1\ : NOR2B - port map(A => mulstep, B => wy_0, Y => mulstep_0); - - \r.d.inst_0_RNIAM6B2[4]\ : NOR2B - port map(A => I_14_0, B => un1_reg, Y => \un3_de_ren1[105]\); - - \r.a.ctrl.annul_RNI7R7R8\ : OR3A - port map(A => ra_bpannul_1, B => annul_2, C => - \un1_p0_6[0]\, Y => N_149); - - \r.e.op2_RNO_0[30]\ : OR3C - port map(A => \op1_m_i[30]\, B => \d_1_iv_3[30]\, C => - \aluresult_m_i[30]\, Y => \d_1[30]\); - - \r.a.rfe2\ : DFN1E0 - port map(D => rfe, CLK => lclk_c, E => holdn, Q => \rfe2\); - - \r.m.ctrl.pc[24]\ : DFN1E0 - port map(D => \pc[24]\, CLK => lclk_c, E => holdn, Q => - \pc_2[24]\); - - un6_fe_npc_I_162 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - Y => \DWACT_FINC_E[18]\); - - \r.d.cnt_RNIRCME[0]\ : NOR2A - port map(A => un10_op, B => call_hold7_i, Y => rs1mod); - - \r.m.result_RNIRVO1[11]\ : OR2B - port map(A => d13, B => \maddress[11]\, Y => - \result_m_0[11]\); - - \r.m.icc_RNO_6[2]\ : NOR3C - port map(A => icc_0_sqmuxa_1_10, B => icc_0_sqmuxa_1_9, C - => icc_0_sqmuxa_1_22, Y => icc_0_sqmuxa_1_27); - - \r.e.shleft_0_RNISKHP\ : OR2A - port map(A => \un1_iu0_6[22]\, B => shleft_0, Y => - \shiftin_5[22]\); - - \r.e.op2_RNO_5[14]\ : AOI1B - port map(A => \result[14]\, B => d31_0, C => \imm_m_i[14]\, - Y => \d_1_iv_0[14]\); - - \r.e.aluop_RNIGM3N1[2]\ : OR2 - port map(A => edata_2_sqmuxa, B => edata_1_sqmuxa, Y => - \aluop_RNIGM3N1[2]\); - - \r.e.jmpl_RNII70061\ : NOR2B - port map(A => \aluresult_1_iv_5[3]\, B => \shiftin_17_m[4]\, - Y => \aluresult_1_iv_6[3]\); - - \r.e.ctrl.inst_RNI2H1S[30]\ : NOR2A - port map(A => un3_notag, B => N_3749_2, Y => un3_op_2); - - \r.e.ctrl.pc[13]\ : DFN1E0 - port map(D => \pc[13]\, CLK => lclk_c, E => holdn, Q => - \pc_2[13]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I313_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[22]\, B => \data_0_0[22]\, Y => - \un6_ex_add_res_s2_1[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I14_G0N : AND2 - port map(A => \op2[13]\, B => \un1_iu0_6[13]\, Y => N436); - - \r.x.ctrl.wy_RNI4SI14_0\ : OR2 - port map(A => wy_RNILF1N3, B => holdn, Y => N_6922_i_0); - - \r.x.ctrl.pc_RNIVT971[23]\ : MX2C - port map(A => \un1_p0_6[375]\, B => \pc[23]\, S => - s_3_sqmuxa, Y => N_3414); - - \r.a.ctrl.cnt_RNI6P4J3[0]\ : NOR3C - port map(A => N_457, B => N_456, C => N_458, Y => - un1_aop2_1_sqmuxa); - - un6_ex_add_res_d0_ADD_33x33_fast_I307_Y_0 : AX1D - port map(A => N442, B => ADD_33x33_fast_I274_Y_0_a3_0, C - => \un6_ex_add_res_s0_1[17]\, Y => - \un6_ex_add_res_s0[17]\); - - \r.f.pc_RNO_6[24]\ : MX2 - port map(A => I_143, B => N_4067, S => bpmiss_1_i_0, Y => - \pc_4[24]\); - - \r.a.ctrl.pc_RNID8L0C[4]\ : MX2 - port map(A => \pc_0[4]\, B => N_3881, S => ex_bpmiss_1, Y - => \fe_pc[4]\); - - \r.x.dci.size_RNIUK8C9[1]\ : MX2 - port map(A => \size_0[1]\, B => \size_2[1]\, S => - dco_i_2(132), Y => \me_size_1[1]\); - - \r.w.s.y_RNI5H6G1[0]\ : AOI1B - port map(A => wy_1_0, B => \y[0]\, C => N_465, Y => - \y_iv_0_o5_1[0]\); - - \r.m.ctrl.inst_RNI5S3O1[20]\ : AOI1 - port map(A => inst_4_2, B => inst_4_1, C => inst, Y => - trap55_i); - - \r.e.ctrl.pc_RNI6VEPF[9]\ : NOR2B - port map(A => \aluresult_1_iv_4[9]\, B => - \aluresult_1_iv_5[9]\, Y => \aluresult_1_iv_6[9]\); - - \r.e.op1[11]\ : DFN1E0 - port map(D => \aop1[11]\, CLK => lclk_c, E => holdn, Q => - \op1[11]\); - - \comb.v.x.data_0_1_1_iv_RNO_0[16]\ : AO1A - port map(A => ld_0_0, B => \data_0[16]\, C => - \dco_m_0[112]\, Y => \data_0_1_1_iv_0[16]\); - - \r.d.inst_0_RNI513S[17]\ : MX2C - port map(A => \de_raddr1_2[4]\, B => \de_raddr1_1[4]\, S - => rs1mod, Y => \un3_de_ren1[95]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I18_G0N : OA1 - port map(A => \op1[17]\, B => ldbp1_1, C => \data_0[17]\, Y - => N448_1); - - \r.e.op2_RNO_8[10]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[362]\, Y => \cpi_m_i[362]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I12_G0N : OAI1 - port map(A => \op1[11]\, B => ldbp1, C => \data_0_2[11]\, Y - => N430_1); - - \r.e.ldbp2_RNI7TP6N1\ : OR2A - port map(A => \eaddress[15]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[16]\); - - \r.e.op2_RNO_1[21]\ : AOI1B - port map(A => \op1[21]\, B => un14_casaen_s1_0_1, C => - \d_1_iv_3[21]\, Y => \d_1_iv_4[21]\); - - \r.m.ctrl.pc_RNI2PL9[20]\ : MX2 - port map(A => \pc_3[20]\, B => \pc[20]\, S => \npc[1]\, Y - => N_3261); - - \r.e.aluop_0_RNIID791[2]\ : XA1 - port map(A => \un1_iu0_5[95]\, B => \aluop_0[2]\, C => - \un1_iu0_6[29]\, Y => N_3556); - - \r.d.inull_RNIE9S2\ : NOR2 - port map(A => \inull\, B => annul_1, Y => - annul_next_2_sqmuxa_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_Y : NAND2 - port map(A => I265_un1_Y_i, B => ADD_33x33_fast_I265_Y_1, Y - => N776_1); - - \r.e.ctrl.tt_RNO_2[0]\ : AO1A - port map(A => wunf, B => ticc, C => wovf, Y => - N_16684_tz_tz); - - un6_fe_npc_I_98 : XOR2 - port map(A => N_83, B => \fe_pc[18]\, Y => I_98); - - un6_ex_add_res_d1_ADD_33x33_fast_I55_Y_0_o3 : AO1 - port map(A => N455_2, B => N451_1, C => N454_2, Y => N514_1); - - \r.d.pc[7]\ : DFN1 - port map(D => \pc_RNO[7]\, CLK => lclk_c, Q => \dpc[7]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I145_un1_Y : NOR2B - port map(A => N546_2, B => N543_2, Y => I145_un1_Y); - - \r.m.icc_RNIL8JA[3]\ : NOR3B - port map(A => \icc[1]\, B => \icc[3]\, C => \inst_1[27]\, Y - => ex_bpmiss_1_0_a5_2_1_0); - - \r.e.jmpl\ : DFN1E0 - port map(D => N_4, CLK => lclk_c, E => holdn, Q => jmpl); - - \r.d.inst_0_RNO_0[0]\ : MX2 - port map(A => data_0_2_0, B => \inst_0[0]\, S => - mexc_1_sqmuxa_1_0, Y => N_4600); - - un6_ex_add_res_d1_ADD_33x33_fast_I146_Y : NOR2B - port map(A => ADD_33x33_fast_I146_Y_0, B => N543_2, Y => - N609_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I15_P0N : OR3A - port map(A => \data_0[14]\, B => \op1[14]\, C => ldbp1_0, Y - => N440_0); - - \r.d.annul_RNIMNQL44\ : OR2B - port map(A => I_24, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[5]\); - - \r.a.imm[16]\ : DFN1E0 - port map(D => \un3_de_ren1[134]\, CLK => lclk_c, E => holdn, - Q => \imm[16]\); - - \r.e.shleft_0_RNIB1IM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[23]\, S => - shleft_0, Y => \shiftin_5[54]\); - - \r.d.pc[2]\ : DFN1 - port map(D => \pc_RNO[2]\, CLK => lclk_c, Q => \dpc[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I215_un1_Y : OAI1 - port map(A => I175_un1_Y, B => N578, C => N629_0, Y => - I215_un1_Y); - - \r.e.aluop_2_RNIG4513[1]\ : MX2C - port map(A => N_3541, B => \logicout_3[14]\, S => - \aluop_2[1]\, Y => N_3573); - - \r.m.icc_RNO_20[2]\ : NOR2 - port map(A => \logicout[9]\, B => \logicout[10]\, Y => - icc_0_sqmuxa_1_3); - - \r.w.result_RNI8TA4[1]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[1]\, Y - => \result_m_0_0[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I89_Y : AO13 - port map(A => \un1_iu0_6[2]\, B => \data_0[2]\, C => N400_1, - Y => N548_0); - - \r.e.op1_RNIRTKP72[4]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[4]\, C - => \d_1_iv_4[4]\, Y => \d_1[4]\); - - \r.e.aluop_RNI2ECS1[1]\ : MX2C - port map(A => N_3532, B => \logicout_3[5]\, S => - \aluop_3[1]\, Y => N_3564); - - \r.m.y_RNO_3[5]\ : AOI1B - port map(A => wy_1_0, B => \y[5]\, C => \y_m_2[5]\, Y => - \y_iv_1[5]\); - - \r.m.ctrl.inst_RNI8FKRJ[30]\ : NOR2 - port map(A => un5_trap, B => un6_annul, Y => - \nullify2_0_sqmuxa\); - - \r.m.ctrl.pc_RNI8MF8[5]\ : MX2 - port map(A => \pc_2[5]\, B => \pc_0[5]\, S => \npc[1]\, Y - => N_3246); - - \r.e.ctrl.pc[6]\ : DFN1E0 - port map(D => \pc_0[6]\, CLK => lclk_c, E => holdn, Q => - \pc[6]\); - - \r.d.inst_0_RNI2KBFU8[29]\ : OR2B - port map(A => pv_4_0, B => annul_next_14, Y => annul_4); - - \r.m.ctrl.rd_RNIDCCC2[5]\ : XNOR2 - port map(A => \un3_de_ren1[104]\, B => \rd_2[5]\, Y => - un1_de_ren1_1_5_i_0); - - \r.m.y_RNI84K91[2]\ : OR2B - port map(A => \y_0[2]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[2]\); - - \r.d.pc_RNIUDHB4[31]\ : MX2 - port map(A => \dpc[31]\, B => \fpc[31]\, S => - \ra_bpmiss_1_0\, Y => N_3908); - - un6_fe_npc_I_94 : AND2 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, Y - => \DWACT_FINC_E[10]\); - - \comb.fpstdata.edata2_0_iv_RNO[2]\ : OR2A - port map(A => N_3687, B => \bpdata[2]\, Y => - \bpdata_i_m[2]\); - - \r.w.s.y_RNO[16]\ : MX2 - port map(A => \y_2[16]\, B => \result_0[16]\, S => N_481_0, - Y => N_3780); - - \r.e.op2_RNIVQ992[22]\ : AOI1B - port map(A => \un1_iu0_5[88]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I176_Y : NOR3C - port map(A => N521_1, B => N525, C => N579_2, Y => N645_1); - - \r.e.op2[24]\ : DFN1E0 - port map(D => N_308, CLK => lclk_c, E => holdn, Q => - \op2[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I166_Y : NOR2B - port map(A => N577, B => N569_0, Y => N635_0); - - \r.f.pc_RNO_4[28]\ : MX2 - port map(A => I_186, B => N_4071, S => bpmiss_1_i_0, Y => - \pc_4[28]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I98_Y\ : AO1 - port map(A => N463_0, B => N460_0, C => N459, Y => N518); - - \r.e.op2[8]\ : DFN1E0 - port map(D => N_292, CLK => lclk_c, E => holdn, Q => - \op2[8]\); - - \r.x.data_0_RNO_1[1]\ : OA1A - port map(A => \data_0[1]\, B => ld_0_0, C => \dco_m_i[105]\, - Y => \data_0_1_1_iv_0[1]\); - - \r.m.result_RNIUQB33[0]\ : AO1A - port map(A => trap55_i, B => \maddress[0]\, C => - trap_0_sqmuxa_3, Y => un1_trap_0_sqmuxa_1_0); - - \r.a.rsel1_0_RNIB3LJ2[2]\ : OR2B - port map(A => data1(14), B => d11, Y => \rfo_m[14]\); - - \r.a.rsel2_0_RNIFA4D[0]\ : NOR2B - port map(A => un17_casaen_0_2, B => d26, Y => - un14_casaen_s1); - - \r.a.rsel1_RNI1RFA[0]\ : NOR2B - port map(A => un17_casaen_0, B => N_494, Y => - un14_casaen_s1_0_0); - - \r.w.s.wim[2]\ : DFN1E0 - port map(D => \wim_1[2]\, CLK => lclk_c, E => holdn, Q => - \wim[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I275_Y_0\ : XOR2 - port map(A => N723, B => ADD_30x30_fast_I275_Y_0_0, Y => - \tmp[17]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I308_Y_0 : AX1E - port map(A => I239_un1_Y_i, B => ADD_33x33_fast_I273_Y_0_1, - C => \un6_ex_add_res_s2_1[18]\, Y => - \un6_ex_add_res_s2[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I85_Y : MAJ3 - port map(A => \data_0[4]\, B => \un1_iu0_6[4]\, C => N406_1, - Y => N544_2); - - \r.m.y[6]\ : DFN1E0 - port map(D => \y_1[6]\, CLK => lclk_c, E => holdn, Q => - \y_0[6]\); - - \r.m.icc_RNO_19[2]\ : NOR2 - port map(A => \logicout[2]\, B => \logicout[3]\, Y => - icc_0_sqmuxa_1_12); - - \r.e.jmpl_RNIUUEBP\ : NAND2 - port map(A => aluresult_1_sqmuxa_0, B => \shiftin_17[15]\, - Y => \shiftin_17_m[15]\); - - \r.x.rstate_RNIHR5I2[0]\ : MX2C - port map(A => N_3404, B => \xc_result[13]\, S => - \rstate[0]\, Y => \wdata[13]\); - - \r.e.op2_RNO_2[18]\ : NOR3C - port map(A => \d_1_iv_1[18]\, B => \d_1_iv_0[18]\, C => - \rfo_m_i[50]\, Y => \d_1_iv_3[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I46_Y\ : MAJ3 - port map(A => \dpc[22]\, B => \inst_0[20]\, C => N415, Y - => N463_0); - - \r.f.pc_RNO_1[19]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[19]\, C => - \pc_1_iv_0[19]\, Y => \pc_1_iv_1[19]\); - - \r.w.s.tba_RNI83558[12]\ : AND2 - port map(A => \bpdata_m_2[0]\, B => \aluresult_1_iv_3[24]\, - Y => \aluresult_1_iv_5[24]\); - - \r.a.rsel1_RNIKEBD73[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[11]\, Y => - \aluresult_m_0[11]\); - - \r.a.ctrl.inst_RNIU03A1[31]\ : OR3A - port map(A => \inst[31]\, B => N_207, C => N_260, Y => - N_470); - - \r.a.ctrl.inst_RNI5I693[20]\ : OA1A - port map(A => aluadd_16_sqmuxa_0_a5_1, B => N_205, C => - N_359, Y => aluop_2_1_0_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I307_Y_0 : XOR3 - port map(A => \un1_iu0_6[16]\, B => \op2[16]\, C => N794_i, - Y => \un6_ex_add_res_s1_i[17]\); - - \r.m.ctrl.pc[23]\ : DFN1E0 - port map(D => \pc_0[23]\, CLK => lclk_c, E => holdn, Q => - \pc_2[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I118_Y\ : OR2A - port map(A => I118_un1_Y_i, B => N479_0, Y => N538_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I14_P0N : OA1C - port map(A => \op1[13]\, B => ldbp1_1, C => \data_0[13]\, Y - => N437_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I76_Y : OA1 - port map(A => \op2[8]\, B => \un1_iu0_6[8]\, C => N425_1, Y - => N535_0); - - \r.x.data_0_RNO_5[6]\ : OR2A - port map(A => data_0_0_30, B => rdata_0_sqmuxa, Y => - \dco_m_i[126]\); - - \r.w.s.wim_RNID5RD2[7]\ : OR2B - port map(A => \wim[7]\, B => aluresult_13_sqmuxa, Y => - \wim_m[7]\); - - \r.f.pc_RNI46M784[9]\ : MX2 - port map(A => I_38, B => N_4052, S => bpmiss_1_i_0_0, Y => - \pc_4[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I8_G0N : NOR3A - port map(A => \op1[7]\, B => ldbp1_2, C => \data_0_2[7]\, Y - => N418_0); - - \r.d.cnt_RNIFET3_1[0]\ : NOR2 - port map(A => \cnt_0[1]\, B => \cnt_2[0]\, Y => un54_casaen); - - \r.x.data_0_RNIAJ33[0]\ : XOR2 - port map(A => \data_0[0]\, B => invop2, Y => N_3304); - - \r.a.ctrl.inst_RNI9U6G3[20]\ : AOI1B - port map(A => aluop_1_1_0_a5_0_0, B => N_209, C => N_345, Y - => aluop_1_1_0_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I126_Y\ : AO1 - port map(A => N491, B => N488_1, C => N487_1, Y => N546_1); - - \r.f.pc_RNIC2JOI4[8]\ : NOR2B - port map(A => \un6_fe_npc_m[6]\, B => - \xc_trap_address_m[8]\, Y => \npc_iv_2[8]\); - - \r.e.op2_RNO_6[15]\ : OR2B - port map(A => data2(15), B => d25_0, Y => \rfo_m_i[47]\); - - \r.e.aluop_0_RNIB4D85[0]\ : MX2C - port map(A => N_3589, B => N_3653, S => \aluop_0[0]\, Y => - \logicout[30]\); - - \r.e.op2_RNIM7MB1[12]\ : OR2A - port map(A => \un1_iu0_5[78]\, B => \un1_iu0_6[12]\, Y => - \logicout_4[12]\); - - \r.m.result_RNIEFD4[19]\ : OR2B - port map(A => d13_0, B => \maddress[19]\, Y => - \result_m_0[19]\); - - \r.e.op2[5]\ : DFN1E0 - port map(D => N_289, CLK => lclk_c, E => holdn, Q => - \op2[5]\); - - \r.m.casa_RNIB08P582\ : OR2B - port map(A => \un17_casaen_0_0\, B => un1_addout, Y => - un17_casaen); - - \r.e.ctrl.inst[23]\ : DFN1E0 - port map(D => \inst_1[23]\, CLK => lclk_c, E => holdn, Q - => \inst_0[23]\); - - \r.e.op2_RNO_2[6]\ : NOR3C - port map(A => \d_1_iv_1[6]\, B => \d_1_iv_0[6]\, C => - \rfo_m_i[38]\, Y => \d_1_iv_3[6]\); - - \r.e.op1_RNO[2]\ : MX2 - port map(A => \d[2]\, B => \d[3]\, S => N_227_0, Y => - \aop1[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I281_Y_0\ : XOR2 - port map(A => N710, B => ADD_30x30_fast_I281_Y_0_0, Y => - \tmp[23]\); - - \r.m.y_RNO_4[4]\ : OR2B - port map(A => \y_2[5]\, B => mulstep_0, Y => \y_m[5]\); - - \r.a.rsel1_RNIJC5DK3[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[13]\, Y => - \aluresult_m_0[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I81_Y : OR2 - port map(A => N415_1, B => I81_un1_Y, Y => N540_0); - - \r.x.ctrl.rd[5]\ : DFN1E0 - port map(D => \rd_2[5]\, CLK => lclk_c, E => holdn, Q => - \rd_0[5]\); - - \r.e.shcnt_RNIGI26F[2]\ : MX2 - port map(A => \shiftin_11[36]\, B => \shiftin_11[32]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[32]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I143_Y : AO1 - port map(A => N544_0, B => N541_0, C => N540, Y => N606_0); - - \r.d.pc[19]\ : DFN1 - port map(D => \pc_RNO[19]\, CLK => lclk_c, Q => \dpc[19]\); - - \r.f.pc_RNO_2[13]\ : OR2B - port map(A => I_66, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[11]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I271_un1_Y_0 : NOR2B - port map(A => N665, B => N614_0, Y => - ADD_33x33_fast_I271_un1_Y_0); - - \r.e.aluop_0_RNIL8ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[13]\, B => \aluop_0[1]\, C => - \un1_iu0_5[79]\, Y => N_6898); - - un6_ex_add_res_d0_ADD_33x33_fast_I199_Y : AO1 - port map(A => N610_1, B => N603, C => N602, Y => N668_1); - - \r.e.op1_RNIK2CR1[13]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[13]\, Y => - \ex_op1_i_m[13]\); - - \r.a.ctrl.inst_RNIE8Q8[28]\ : XOR2 - port map(A => \inst_1[28]\, B => \icc_0[2]\, Y => branch_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I123_Y\ : OR2B - port map(A => N488_1, B => N484_1, Y => N543); - - \r.m.result[20]\ : DFN1E0 - port map(D => \eres2[20]\, CLK => lclk_c, E => holdn, Q => - \maddress[20]\); - - \r.e.op1_RNIU4UH[12]\ : MX2 - port map(A => \op1[12]\, B => \data_0_2[12]\, S => ldbp1_1, - Y => \un1_iu0_6[12]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I41_Y : MAJ3 - port map(A => \op2[26]\, B => \un1_iu0_6[26]\, C => N472_0, - Y => N500_1); - - \r.w.s.y[11]\ : DFN1E0 - port map(D => N_3775, CLK => lclk_c, E => N_6922_i_0, Q => - \y[11]\); - - \r.d.inst_0_RNO_0[9]\ : MX2 - port map(A => data_0_0_9, B => \inst_0[9]\, S => - mexc_1_sqmuxa_1_0, Y => N_4609); - - \r.e.op1_RNI0FNF[23]\ : NOR2A - port map(A => un17_casaen_0, B => \op1[23]\, Y => - \op1_i_m[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I17_G0N\ : OR2B - port map(A => \inst_0[17]\, B => \dpc[19]\, Y => N409_2); - - \r.e.op2_RNO_7[17]\ : OR3C - port map(A => d28_0, B => \rsel2_1[0]\, C => - \un1_p0_6[369]\, Y => \cpi_m_i[369]\); - - \r.e.op1_RNI4MBT4[16]\ : AO1A - port map(A => \bpdata[16]\, B => edata_2_sqmuxa, C => - \op1_i_m[16]\, Y => \edata2_0_iv_0[16]\); - - \r.d.cwp_RNO_0[1]\ : MX2 - port map(A => \ncwp[1]\, B => N_4219, S => un1_wcwp, Y => - N_4228); - - \r.e.invop2_0_RNI5B8AV2\ : MX2C - port map(A => \un6_ex_add_res_s2[30]\, B => - \un6_ex_add_res_s0[30]\, S => invop2_0, Y => N_6576); - - \r.e.ctrl.pc[11]\ : DFN1E0 - port map(D => \pc[11]\, CLK => lclk_c, E => holdn, Q => - \pc_2[11]\); - - \r.a.ctrl.pv_RNO\ : NOR2A - port map(A => pv, B => annul_current, Y => ctrl_pv); - - \r.d.annul_RNI8949\ : OR3 - port map(A => tmp, B => annul_1, C => call_hold5_0, Y => - icc_check_bp_1); - - \r.a.ctrl.inst[29]\ : DFN1E0 - port map(D => \inst_0[29]\, CLK => lclk_c, E => holdn, Q - => \inst[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I26_P0N\ : OR2 - port map(A => \inst_0_1[28]\, B => \dpc[28]\, Y => N437_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I58_Y : OR2B - port map(A => N452_1, B => N449_0, Y => N517_1); - - \r.e.ldbp2_2_RNIT8T365\ : MX2 - port map(A => \un6_ex_add_res_s1[32]\, B => N_6659, S => - ldbp2_2, Y => \eaddress[31]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I173_Y : AO1 - port map(A => N584, B => N577, C => N576_0, Y => N642); - - \r.e.ldbp2_1_RNIL7Q55\ : MX2C - port map(A => \un6_ex_add_res_s1_i[3]\, B => N_6642, S => - ldbp2_1, Y => ldbp2_1_RNIL7Q55); - - un6_ex_add_res_d1_ADD_33x33_fast_I312_Y_0_0 : XOR2 - port map(A => \op2[21]\, B => \un1_iu0_6[21]\, Y => - ADD_33x33_fast_I312_Y_0_0); - - \r.x.ctrl.pc_RNI1QN9[28]\ : MX2 - port map(A => \pc_0[28]\, B => \pc_2[28]\, S => \npc[1]\, Y - => N_3239); - - un6_ex_add_res_d2_ADD_33x33_fast_I205_un1_Y : OR2A - port map(A => N552_1, B => N611, Y => I205_un1_Y); - - \r.f.pc_RNO[9]\ : OR3C - port map(A => \tmp_m[9]\, B => \pc_1_iv_1[9]\, C => - \un6_fe_npc_m[7]\, Y => \pc_1[9]\); - - \r.e.shleft_RNIP6FC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[24]\, S => - shleft, Y => \shiftin_5[55]\); - - \r.a.ctrl.inst_RNIDG1E_1[21]\ : OR2 - port map(A => \inst_2[21]\, B => \inst_2[19]\, Y => N_225); - - un6_ex_add_res_d2_ADD_33x33_fast_I87_Y_0 : AO1 - port map(A => N407_1, B => N403_2, C => N406_1, Y => N546_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I245_Y : OR2 - port map(A => N660_1, B => I245_un1_Y, Y => N802_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I27_P0N : OR3A - port map(A => \data_0[26]\, B => \op1[26]\, C => ldbp1_3, Y - => N476_1); - - \r.m.result_RNIS9JM[9]\ : AOI1B - port map(A => d13_0, B => \maddress[9]\, C => \d_iv_0[9]\, - Y => \d_iv_1[9]\); - - \r.w.s.dwt_RNO_3\ : NOR3B - port map(A => \inst_1[29]\, B => \inst[25]\, C => - \inst[28]\, Y => dwt_1_sqmuxa_2); - - \r.w.s.wim_RNIEF4N2[4]\ : MX2 - port map(A => \wim[4]\, B => \result[4]\, S => wim_1_sqmuxa, - Y => \wim_1[4]\); - - \r.a.ctrl.inst_RNICP4O1[23]\ : OR3B - port map(A => illegal_inst37_4, B => aluop_2_1_0_a2_0, C - => N_472, Y => illegal_inst_7_iv_2_0_a5_4_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I10_P0N : OR3A - port map(A => \data_0[9]\, B => \op1[9]\, C => ldbp1, Y => - N425_0); - - \r.w.s.y[14]\ : DFN1E0 - port map(D => N_153, CLK => lclk_c, E => holdn, Q => - \y[14]\); - - \r.e.ctrl.inst[31]\ : DFN1E0 - port map(D => \inst[31]\, CLK => lclk_c, E => holdn, Q => - \inst_2[31]\); - - \r.a.rsel1_0_RNIQ08M2[2]\ : OR2B - port map(A => data1(2), B => d11_0, Y => \rfo_m[2]\); - - \r.e.op1_RNIE0J494[16]\ : NOR3C - port map(A => \op1_m_0[16]\, B => \d_iv_2[16]\, C => - \aluresult_m_0[16]\, Y => \d_i[16]\); - - \r.e.op1_RNI3S43N6[24]\ : AOI1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[24]\, C - => \d_iv_3[24]\, Y => \d_i[24]\); - - \r.m.ctrl.rd_RNI4MFE2[6]\ : XNOR2 - port map(A => \un3_de_ren1[105]\, B => \rd_1[6]\, Y => - un1_de_ren1_1_6_i_0); - - \r.a.ctrl.inst_RNIKHI77[20]\ : OR3C - port map(A => aluop_1_1_0_0, B => N_346, C => aluop_1_1_0_2, - Y => \aluop[1]\); - - \r.m.irqen_RNO\ : OR3C - port map(A => trap_2_0, B => un1_trap_0_sqmuxa_5, C => - irqen_1, Y => irqen_0); - - \r.w.result_RNIFPB4[8]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[8]\, Y - => \result_m_0_0[8]\); - - \r.e.op2_RNO[7]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[7]\, Y => N_291); - - \r.e.aluop_0_RNIVOID1[2]\ : XA1 - port map(A => \un1_iu0_5[81]\, B => \aluop_0[2]\, C => - \un1_iu0_6[15]\, Y => N_3542); - - \r.e.shleft_0_RNIBK9C2\ : MX2B - port map(A => \shiftin_5[31]\, B => \shiftin_5[15]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[15]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I119_Y\ : OR2B - port map(A => N484_1, B => N480, Y => N539); - - un6_ex_add_res_d0_ADD_33x33_fast_I61_Y : AO13 - port map(A => N442, B => \un1_iu0_6[16]\, C => \data_0[16]\, - Y => N520_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I13_G0N : NOR2B - port map(A => \un1_iu0_6[12]\, B => \op2[12]\, Y => N433_0); - - \r.x.dci.SIGNED\ : DFN1E0 - port map(D => SIGNED, CLK => lclk_c, E => holdn, Q => - SIGNED_0); - - \r.m.dci.size_RNO_0[0]\ : OR2 - port map(A => N_3356_3, B => N_3758, Y => \size_0[0]\); - - \r.a.su_RNIPLKAI\ : OR2A - port map(A => un1_privileged_inst_1_sqmuxa, B => su_1, Y - => privileged_inst_5); - - \r.d.inst_0_RNIQQ3D[25]\ : OA1C - port map(A => \inst_0[30]\, B => rd_0_sqmuxa, C => - \inst_0[25]\, Y => N_3361); - - \r.d.inst_0_RNIB1HFI[13]\ : NOR3B - port map(A => rfe_0, B => wreg_1, C => un1_rs1, Y => rfe_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_Y\ : AO1B - port map(A => ADD_30x30_fast_I235_un1_Y_0, B => N738, C => - ADD_30x30_fast_I235_Y_2, Y => N700); - - un6_ex_add_res_d0_ADD_33x33_fast_I115_Y : AO1 - port map(A => N516, B => N513_0, C => N512, Y => N578); - - \r.e.op2_RNO_5[11]\ : AOI1B - port map(A => \result[11]\, B => d31_0, C => \imm_m_i[11]\, - Y => \d_1_iv_0[11]\); - - \r.e.jmpl_RNIQBA4F1\ : AOI1B - port map(A => \shiftin_17[13]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[12]\, Y => \aluresult_1_iv_7[12]\); - - \r.x.data_0_RNO_0[12]\ : NOR2B - port map(A => N_3473, B => data_0_12, Y => \dco_m_0[108]\); - - \r.x.ctrl.wy_RNIMKUI_0\ : NOR3 - port map(A => wy_1, B => wy_2, C => wy_0, Y => wy_1_0); - - \r.f.pc_RNO_7[17]\ : MX2 - port map(A => \fpc[17]\, B => \tba[5]\, S => - rstate_6314_d_0, Y => \xc_trap_address[17]\); - - \r.f.pc_RNO_0[18]\ : OR3A - port map(A => \tmp[18]\, B => un2_rstn_5_2, C => - \un2_rstn_5_0_0\, Y => \tmp_m[18]\); - - \r.a.ctrl.rd_RNIOC217[0]\ : NOR2B - port map(A => un2_rs1_NE_5, B => un2_rs1_NE_4, Y => - un2_rs1_NE_i_0); - - \r.a.ctrl.pc[9]\ : DFN1E0 - port map(D => \dpc[9]\, CLK => lclk_c, E => holdn, Q => - \pc_0[9]\); - - \r.x.ctrl.pc_RNIGOI61[27]\ : MX2C - port map(A => \un1_p0_6[379]\, B => \pc_3[27]\, S => - s_3_sqmuxa, Y => N_3418); - - \r.e.op2[23]\ : DFN1E0 - port map(D => N_307, CLK => lclk_c, E => holdn, Q => - \op2[23]\); - - \r.e.op1_RNI9RN8[2]\ : MX2 - port map(A => \op1[2]\, B => \data_0[2]\, S => ldbp1_2, Y - => \un1_iu0_6[2]\); - - \r.e.op1_RNIB9KOA[9]\ : NOR3 - port map(A => \bpdata_i_m_2[1]\, B => \edata2_0_iv_0[9]\, C - => \bpdata_i_m[9]\, Y => edata2_0_iv(9)); - - \r.e.ctrl.wicc\ : DFN1E0 - port map(D => wicc_1_0, CLK => lclk_c, E => holdn, Q => - wicc_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I145_Y : OR2 - port map(A => ADD_33x33_fast_I145_Y_0, B => I145_un1_Y, Y - => N608_1); - - \r.e.op1_RNO[7]\ : MX2C - port map(A => \d_i[7]\, B => \d_i[8]\, S => N_227_0, Y => - \aop1[7]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I294_Y_0 : XOR3 - port map(A => \un1_iu0_6[3]\, B => \op2[3]\, C => N614_0, Y - => \un6_ex_add_res_s1[4]\); - - \r.d.inst_0_RNI8446[19]\ : NOR3C - port map(A => \inst_0[19]\, B => \inst_0_0[22]\, C => - N_3515_1, Y => icc_check8_1); - - \r.e.aluop[1]\ : DFN1E0 - port map(D => \aluop[1]\, CLK => lclk_c, E => holdn, Q => - \aluop_3[1]\); - - \r.x.y[23]\ : DFN1E0 - port map(D => \y[23]\, CLK => lclk_c, E => holdn, Q => - \y_2[23]\); - - \r.e.jmpl_RNI3A18F1\ : AOI1B - port map(A => \shiftin_17[12]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[11]\, Y => \aluresult_1_iv_8[11]\); - - \r.x.ctrl.inst_RNI2TRS1[22]\ : NOR3B - port map(A => tba_610_e_3, B => tba_610_e_2, C => annul_1_0, - Y => tba_610_e_5); - - \r.e.ctrl.tt_RNO_1[0]\ : NOR2A - port map(A => N_16684_tz_tz, B => trap_4_1, Y => - tt_9_0_1862_0); - - \r.w.result[15]\ : DFN1E0 - port map(D => \wdata[15]\, CLK => lclk_c, E => holdn, Q => - \result[15]\); - - \r.e.ctrl.annul_RNIDKHT5\ : NOR3B - port map(A => rst, B => \hold_pc_7\, C => jump_0, Y => - branch_1_m7_1); - - \r.a.imm_RNO[5]\ : NOR2B - port map(A => \inst_0[5]\, B => call_hold5, Y => - \un3_de_ren1[123]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I3_P0N : OR3A - port map(A => \data_0[2]\, B => \op1[2]\, C => ldbp1_2, Y - => N404_2); - - \r.e.aluop_RNI143R4[2]\ : OR2A - port map(A => aluresult_5_sqmuxa, B => \bpdata[14]\, Y => - \aluop_RNI143R4[2]\); - - \r.d.inst_0_RNI5DOH[17]\ : MX2 - port map(A => \inst_0[17]\, B => \inst_0[28]\, S => rs1mod, - Y => \un3_de_ren1[94]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I97_un1_Y : OR3B - port map(A => N482_1, B => N485, C => N498_i, Y => - ADD_33x33_fast_I97_un1_Y); - - \r.e.aluop_RNI7NNF[1]\ : OR2B - port map(A => \aluop_1[2]\, B => \aluop_3[1]\, Y => - miscout140_1); - - \r.e.op1_RNIQ1BT4[22]\ : AO1A - port map(A => \bpdata[22]\, B => edata_2_sqmuxa, C => - \op1_i_m[22]\, Y => \edata2_0_iv_0[22]\); - - \r.e.shleft_0_RNI5DIP\ : OR2A - port map(A => \op1_RNID1VH[19]\, B => shleft_0, Y => - \shiftin_5[19]\); - - \r.m.result_RNINV3I[0]\ : OA1A - port map(A => \maddress[0]\, B => d27, C => \cpi_m_i[352]\, - Y => \d_1_iv_1[0]\); - - \r.e.shcnt_RNIV330Q[1]\ : MX2C - port map(A => \shiftin_14[21]\, B => \shiftin_14[19]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[19]\); - - \r.e.op2_RNIE8NB1_0[25]\ : OR2 - port map(A => \un1_iu0_6[25]\, B => \un1_iu0_5[91]\, Y => - \logicout_3[25]\); - - \r.a.ctrl.inst_RNIB41E[23]\ : OR2B - port map(A => \inst_1[24]\, B => \inst_1[23]\, Y => N_216); - - \r.a.ctrl.inst[21]\ : DFN1E0 - port map(D => \inst_0_0[21]\, CLK => lclk_c, E => holdn, Q - => \inst_2[21]\); - - \r.x.ctrl.inst[30]\ : DFN1E0 - port map(D => \inst_1[30]\, CLK => lclk_c, E => holdn, Q - => \inst_3[30]\); - - \r.e.shleft_0_RNIPL9A3\ : MX2 - port map(A => \shiftin_5[54]\, B => \shiftin_5[38]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[38]\); - - \r.e.aluop_0_RNI91JD1[2]\ : XA1 - port map(A => \un1_iu0_5[91]\, B => \aluop_0[2]\, C => - \un1_iu0_6[25]\, Y => N_3552); - - \r.f.pc_RNO_3[22]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[22]\, C => - \xc_trap_address_m[22]\, Y => \pc_1_iv_0[22]\); - - \r.e.shleft_1_RNIPBVI2\ : MX2B - port map(A => \shiftin_5[37]\, B => \shiftin_5[21]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[21]\); - - \r.d.inst_0_RNI3RUM[3]\ : NOR2B - port map(A => \inst_0[3]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI3RUM[3]\); - - \r.x.data_0[12]\ : DFN1E0 - port map(D => \data_0_1[12]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_2[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I3_G0N\ : OR2B - port map(A => \inst_0_RNI3RUM[3]\, B => \dpc[5]\, Y => N367); - - \r.w.result_RNIMOV6[4]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => - \result_0[4]\, Y => \result_m_0[4]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I175_Y : AOI1 - port map(A => N586_1, B => N579_2, C => N578_1, Y => N644); - - un6_ex_add_res_d2_ADD_33x33_fast_I311_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[20]\, B => \data_0_2[20]\, Y => - \un6_ex_add_res_s2_1[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I84_Y : OA1A - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N410_0, - Y => N543_0); - - \r.m.result_RNO[18]\ : MX2 - port map(A => \aluresult[18]\, B => \op1[18]\, S => - un17_casaen_0_2, Y => \eres2[18]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I113_un1_Y : NOR3C - port map(A => N458, B => N461_0, C => N514_1, Y => - I113_un1_Y); - - \comb.v.f.pc_1_iv_RNO_0[3]\ : AND2 - port map(A => \tmp_m[3]\, B => \pc_1_iv_1[3]\, Y => - \pc_1_iv_2[3]\); - - \r.x.result_RNIAELJ3[30]\ : MX2C - port map(A => \un1_iu0_6[30]\, B => \un1_p0_6[382]\, S => - bpdata6, Y => \bpdata[30]\); - - \r.f.pc_RNIMGQQE3[5]\ : AOI1B - port map(A => I_13, B => un2_rstn_4_0_0, C => - \xc_trap_address_m[5]\, Y => \npc_iv_2[5]\); - - \r.e.aluop_1_RNIL7KO1[1]\ : OR2B - port map(A => aluresult_9_sqmuxa, B => aluresult_8_sqmuxa_i, - Y => \aluresult_4[1]\); - - \r.x.y[20]\ : DFN1E0 - port map(D => \y_0[20]\, CLK => lclk_c, E => holdn, Q => - \y_2[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I63_Y_0_a3 : OR3C - port map(A => \data_0[14]\, B => \un1_iu0_6[14]\, C => - N443_1, Y => N_53_i); - - \r.m.ctrl.pc[21]\ : DFN1E0 - port map(D => \pc_0[21]\, CLK => lclk_c, E => holdn, Q => - \pc_3[21]\); - - \r.m.result[6]\ : DFN1E0 - port map(D => \eres2[6]\, CLK => lclk_c, E => holdn, Q => - \maddress[6]\); - - \r.a.bp\ : DFN1E0 - port map(D => bp_1, CLK => lclk_c, E => holdn, Q => bp); - - \r.x.data_0_RNO_0[9]\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_0, B => mcdo_m_0_7, C => - N_3473, Y => \dco_m_0[105]\); - - \r.e.op2_RNO[4]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[4]\, Y => N_288); - - un6_ex_add_res_d0_ADD_33x33_fast_I49_Y : AO13 - port map(A => N460_1, B => \un1_iu0_6[22]\, C => - \data_0_0[22]\, Y => N508_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I38_Y\ : AO13 - port map(A => N427, B => \dpc[26]\, C => \inst_0_1[26]\, Y - => N455); - - \r.m.result[15]\ : DFN1E0 - port map(D => \eres2[15]\, CLK => lclk_c, E => holdn, Q => - \maddress[15]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I134_un1_Y\ : NOR2B - port map(A => N499, B => N496_2, Y => I134_un1_Y); - - \r.e.op2_RNIE8NB1[25]\ : OR2A - port map(A => \un1_iu0_5[91]\, B => \un1_iu0_6[25]\, Y => - \logicout_4[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I62_Y\ : OR2A - port map(A => I62_un1_Y_i, B => N394, Y => N479_0); - - \r.m.y_RNO[12]\ : OR3C - port map(A => \y_iv_1[12]\, B => \y_iv_0[12]\, C => - \logicout_m[12]\, Y => \y_1[12]\); - - \r.a.imm_RNO[4]\ : NOR2B - port map(A => \inst_0_RNI4VUM[4]\, B => call_hold5, Y => - \un3_de_ren1[122]\); - - \r.f.pc_RNO_6[15]\ : MX2 - port map(A => \fpc[15]\, B => \eaddress[15]\, S => jump_0, - Y => N_4058); - - \r.f.pc_RNIE0J51[10]\ : MX2 - port map(A => \fpc[10]\, B => \xc_vectt_1[6]\, S => - rstate_6314_d, Y => \xc_trap_address[10]\); - - \r.a.ctrl.rd_RNIND3G3[4]\ : NOR3C - port map(A => un2_rs1_5_i, B => un2_rs1_4_i, C => - un2_rs1_NE_1, Y => un2_rs1_NE_4); - - \r.a.ctrl.pc_RNIGRD2C[10]\ : MX2 - port map(A => \pc_3[10]\, B => N_3887, S => ex_bpmiss_1, Y - => \fe_pc[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I65_un1_Y : AND2 - port map(A => N436, B => N440, Y => I65_un1_Y); - - \r.e.op1[3]\ : DFN1E0 - port map(D => \aop1[3]\, CLK => lclk_c, E => holdn, Q => - \op1[3]\); - - \r.e.op2_RNIS7MB1_0[21]\ : NOR2 - port map(A => \un1_iu0_6[21]\, B => \un1_iu0_5[87]\, Y => - \logicout_4[21]\); - - \r.a.ctrl.pc[12]\ : DFN1E0 - port map(D => \dpc[12]\, CLK => lclk_c, E => holdn, Q => - \pc[12]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I12_P0N : OR3A - port map(A => \data_0_2[11]\, B => \op1[11]\, C => ldbp1, Y - => N431_0); - - \r.m.ctrl.inst_RNI1T0E[23]\ : OR2B - port map(A => \inst_2[23]\, B => \inst_2[22]\, Y => - trap_0_sqmuxa_1_1_i); - - \r.e.ctrl.rd[0]\ : DFN1E0 - port map(D => \rd_2[0]\, CLK => lclk_c, E => holdn, Q => - \rd[0]\); - - \r.x.data_0_RNO_3[7]\ : OR2B - port map(A => rdata_2_sqmuxa, B => data_0_0_15, Y => - \dco_m_i[111]\); - - \r.d.inst_0_RNIV2072[4]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum[0]\, B => un1_reg, - Y => \un3_de_ren1[103]\); - - \r.e.op2_RNO_3[23]\ : NOR3C - port map(A => \result_m_i[23]\, B => \imm_m_i[23]\, C => - \d_1_iv_1[23]\, Y => \d_1_iv_2[23]\); - - \r.e.ctrl.rd_RNIF29A2[4]\ : XNOR2 - port map(A => \un3_de_ren1[103]\, B => \rd_0[4]\, Y => - un1_de_ren1_4_i_0); - - \r.e.shcnt_RNIHNTNM[1]\ : MX2C - port map(A => \shiftin_14[13]\, B => \shiftin_14[11]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[11]\); - - \r.e.ctrl.trap_RNIIHVT1\ : OR2A - port map(A => jump_0_sqmuxa_1_2, B => jump_0_sqmuxa, Y => - jump_0_sqmuxa_1_i_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I1_P0N : OR3A - port map(A => \data_0[0]\, B => \op1[0]\, C => ldbp1_0, Y - => N398); - - \r.f.pc_RNO_6[22]\ : MX2 - port map(A => \fpc[22]\, B => \eaddress[22]\, S => jump, Y - => N_4065); - - \r.e.shcnt_RNIBFEG[4]\ : MX2C - port map(A => \shcnt[4]\, B => N_3308, S => ldbp2_0, Y => - \ex_shcnt_1_i_0[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I45_Y : AO18 - port map(A => N466_1, B => \un1_iu0_6[24]\, C => - \data_0[24]\, Y => N504_1); - - \r.x.data_0_RNI4JS8[3]\ : XOR2 - port map(A => \data_0[3]\, B => invop2_0, Y => N_3307); - - \r.m.y_RNO_4[15]\ : OR2B - port map(A => \y[16]\, B => mulstep_0, Y => \y_m[16]\); - - \r.m.y_RNO_2[17]\ : OR2B - port map(A => \y[17]\, B => y08, Y => \y_m_0[17]\); - - \r.f.pc_RNO_5[19]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[19]\, Y => \xc_trap_address_m[19]\); - - \r.a.ctrl.rd_RNIH0CV[4]\ : XNOR2 - port map(A => \rd_1[4]\, B => \un3_de_ren1[95]\, Y => - un2_rs1_4_i); - - \r.f.pc_RNO_4[21]\ : MX2 - port map(A => I_122, B => N_4064, S => bpmiss_1_i_0_0, Y - => \pc_4[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I130_Y_0 : AND2 - port map(A => N431_0, B => N428_0, Y => - ADD_33x33_fast_I130_Y_0); - - \r.m.icc_RNO_1[2]\ : MX2C - port map(A => \logicout[22]\, B => \icc_16[2]\, S => - un3_op_i, Y => N_4177); - - \r.e.aluop_RNI7GQF4[1]\ : OR2B - port map(A => \bpdata[20]\, B => aluresult_6_sqmuxa, Y => - \bpdata_m[20]\); - - \r.a.ctrl.inst_RNIODC7I[31]\ : AO1C - port map(A => N_212, B => un1_illegal_inst33, C => - privileged_inst_1_sqmuxa, Y => - un1_privileged_inst_1_sqmuxa); - - \r.e.op2_RNO_5[20]\ : OR2B - port map(A => \result_0[20]\, B => d31, Y => - \result_m_i[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I191_Y : AO1 - port map(A => N602, B => N595_1, C => N594_0, Y => N660); - - \r.m.y_RNO_4[30]\ : OR3A - port map(A => \y_2[30]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[30]\); - - \r.x.result[18]\ : DFN1E0 - port map(D => \maddress[18]\, CLK => lclk_c, E => holdn, Q - => \result_0[18]\); - - \r.w.s.wim[3]\ : DFN1E0 - port map(D => \wim_1[3]\, CLK => lclk_c, E => holdn, Q => - \wim[3]\); - - \r.m.y_RNIBINI4[16]\ : NOR3C - port map(A => \ex_op2_m[16]\, B => aluresult_8_sqmuxa_i, C - => \aluresult_1_iv_1[16]\, Y => \aluresult_1_iv_2[16]\); - - \r.e.aluop_RNI6F7OM[0]\ : AOI1B - port map(A => \logicout[19]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_5[19]\, Y => \aluresult_1_iv_6[19]\); - - \r.d.inst_0_RNIPQUJ[21]\ : AO1 - port map(A => wy_1_0_a3_1_0, B => N_142, C => inst_0_2, Y - => \inst_0_RNIPQUJ[21]\); - - \r.x.result[8]\ : DFN1E0 - port map(D => \maddress[8]\, CLK => lclk_c, E => holdn, Q - => \result[8]\); - - \r.x.npc_0_RNIS6KU[0]\ : MX2C - port map(A => N_3219, B => N_3249, S => \npc_0[0]\, Y => - \xc_result[8]\); - - \r.a.imm[13]\ : DFN1E0 - port map(D => \un3_de_ren1[131]\, CLK => lclk_c, E => holdn, - Q => \imm[13]\); - - \r.m.result_RNO[11]\ : MX2 - port map(A => \aluresult[11]\, B => \op1[11]\, S => - un17_casaen_0_2, Y => \eres2[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I242_un1_Y\ : NAND2 - port map(A => N558, B => ADD_30x30_fast_I242_un1_Y_0, Y => - I242_un1_Y); - - \r.w.s.ps_RNO_0\ : MX2 - port map(A => ps_1, B => ps, S => holdn, Y => N_4993); - - un6_ex_add_res_d1_ADD_33x33_fast_I261_Y_2 : OA1A - port map(A => N629, B => N644, C => ADD_33x33_fast_I261_Y_1, - Y => ADD_33x33_fast_I261_Y_2_0); - - \r.e.op1_RNI9PUH[17]\ : MX2 - port map(A => \op1[17]\, B => \data_0[17]\, S => ldbp1_2, Y - => \un1_iu0_6[17]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I197_Y : AO1 - port map(A => N608_1, B => N601, C => N600_1, Y => N666_1); - - \r.e.ctrl.inst_RNIQSQF[25]\ : NOR3B - port map(A => \inst_2[25]\, B => \inst_1[27]\, C => - \icc_0[0]\, Y => ex_bpmiss_1_0_a5_6_0); - - \r.a.ctrl.ld\ : DFN1E0 - port map(D => ld_2, CLK => lclk_c, E => holdn, Q => ld_1); - - \r.w.s.tba[7]\ : DFN1E1 - port map(D => \result_0[19]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[7]\); - - \r.a.ctrl.inst_RNI293H1[22]\ : OR3B - port map(A => N_472, B => N_6681_1, C => N_212, Y => - cp_disabled_8_sqmuxa_1); - - \r.d.inst_0_RNIF423_0[29]\ : NOR2B - port map(A => \inst_0[28]\, B => \inst_0[29]\, Y => - annul_next_1_sqmuxa_1_2); - - \r.x.data_0_RNO_1[29]\ : NOR2A - port map(A => \data_0_0[29]\, B => ld_3, Y => - \data_0_m[29]\); - - \r.x.icc_RNI9SID[0]\ : MX2 - port map(A => \icc[0]\, B => \icc_2[0]\, S => wicc, Y => - N_4180); - - \r.m.y_RNO_0[28]\ : NOR3C - port map(A => \y_m[29]\, B => \y_m_0[28]\, C => - \y_iv_1[28]\, Y => \y_iv_2[28]\); - - \r.a.imm[30]\ : DFN1E0 - port map(D => \un3_de_ren1[148]\, CLK => lclk_c, E => holdn, - Q => \imm[30]\); - - \r.w.s.y_RNO_2[18]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[18]\, Y - => N_392); - - \r.f.pc_RNO[16]\ : OR3C - port map(A => \tmp_m[16]\, B => \pc_1_iv_1[16]\, C => - \un6_fe_npc_m[14]\, Y => \pc_1[16]\); - - \r.e.op2_RNO_4[31]\ : OA1A - port map(A => \maddress[31]\, B => d27_0, C => - \cpi_m_i[383]\, Y => \d_1_iv_1[31]\); - - \r.a.ctrl.rd_RNIQGFK1[2]\ : XA1A - port map(A => \rd[2]\, B => \inst_0_RNI2NUM[2]\, C => - un1_de_ren1_3_i, Y => un1_de_ren1_NE_1); - - \r.e.op1_RNI09UH[13]\ : MX2 - port map(A => \op1[13]\, B => \data_0[13]\, S => ldbp1_1, Y - => \un1_iu0_6[13]\); - - \r.x.ctrl.rd_RNIC2NU[5]\ : MX2 - port map(A => \cwp_0[1]\, B => \rd_0[5]\, S => N_6357, Y - => waddr(5)); - - \comb.branch_address.tmp_ADD_30x30_fast_I232_Y_2\ : NOR3C - port map(A => I86_un1_Y, B => ADD_30x30_fast_I232_Y_0, C - => I140_un1_Y_i, Y => ADD_30x30_fast_I232_Y_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I292_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[1]\, B => \data_0[1]\, Y => - \un6_ex_add_res_s2_1[2]\); - - \r.e.aluop_1_RNIAG093[1]\ : MX2C - port map(A => \logicout_4[31]\, B => N_6916, S => N_6866_i, - Y => N_3654); - - \r.x.ctrl.inst_RNI893A1[21]\ : NOR3B - port map(A => y6_0, B => y10_3_0, C => y11_0, Y => y11); - - \r.m.y_RNI5B6P6[20]\ : NOR3C - port map(A => \cpi_m[165]\, B => \y_m_1[20]\, C => - \bpdata_m[20]\, Y => \aluresult_1_iv_3[20]\); - - \r.e.ldbp2_2_RNIAMVOE\ : MX2C - port map(A => \un6_ex_add_res_s1[7]\, B => N_6646, S => - ldbp2_2, Y => \eaddress[6]\); - - \r.x.ctrl.pc_RNIUT971[15]\ : MX2C - port map(A => \un1_p0_6[367]\, B => \pc_0[15]\, S => - s_3_sqmuxa_0, Y => N_3406); - - \r.x.data_0_RNI97T8[8]\ : XOR2 - port map(A => \data_0[8]\, B => invop2_0, Y => N_4255); - - \r.m.y_RNINF7P6[23]\ : AOI1B - port map(A => \bpdata[23]\, B => aluresult_6_sqmuxa, C => - \aluresult_1_iv_1[23]\, Y => \aluresult_1_iv_3[23]\); - - \r.a.ctrl.inst_RNIDS0S[22]\ : NOR3 - port map(A => \inst_2[20]\, B => \inst[22]\, C => N_201, Y - => cp_disabled_10_sqmuxa_1); - - \r.m.casa_RNIKPD91_0\ : NOR2 - port map(A => un1_logicout21, B => un17_casaen_0, Y => - edata_3_sqmuxa_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I76_Y : NOR2B - port map(A => N425_0, B => N422_0, Y => N535); - - \r.x.ctrl.pc[27]\ : DFN1E0 - port map(D => \pc_2[27]\, CLK => lclk_c, E => holdn, Q => - \pc_3[27]\); - - \r.e.aluop_0_RNI59JD1[1]\ : XOR3 - port map(A => \un1_iu0_6[17]\, B => \aluop_0[1]\, C => - \un1_iu0_5[83]\, Y => N_6877); - - \r.d.pc_RNIGTGB4[10]\ : MX2 - port map(A => \dpc[10]\, B => \fpc[10]\, S => ra_bpmiss_1, - Y => N_3887); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.m.y_RNO[7]\ : AO1C - port map(A => y14_0, B => \logicout[7]\, C => \y_iv_2[7]\, - Y => \y_1[7]\); - - \r.e.op2_RNO_2[24]\ : NOR3C - port map(A => \d_1_iv_1[24]\, B => \d_1_iv_0[24]\, C => - \rfo_m_i[56]\, Y => \d_1_iv_3[24]\); - - \r.m.y_RNO[2]\ : OR3C - port map(A => \y_iv_1[2]\, B => \y_iv_0[2]\, C => - \logicout_m[2]\, Y => \y_1[2]\); - - \r.e.ctrl.pc_RNIRR011[7]\ : OR2B - port map(A => \pc_0[7]\, B => jmpl_4, Y => \cpi_m[152]\); - - \r.a.imm_RNO[31]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[149]\); - - \r.a.et_RNO\ : OR2A - port map(A => su2, B => et_1_0, Y => et_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I278_Y_0\ : XOR2 - port map(A => N716, B => ADD_30x30_fast_I278_Y_0_0, Y => - \tmp[20]\); - - \r.x.icc[2]\ : DFN1E0 - port map(D => \icc_0[2]\, CLK => lclk_c, E => holdn, Q => - \icc_2[2]\); - - \r.x.data_0_RNO[12]\ : OR3 - port map(A => \dco_m_0[108]\, B => \data_0_1_0_iv_0[12]\, C - => \data_0_1_4[9]\, Y => \data_0_1[12]\); - - \r.f.pc_RNI29U6A[3]\ : MX2B - port map(A => \fpc[3]\, B => \eaddress[3]\, S => jump_0, Y - => N_4046); - - \r.x.result_RNI990C3[2]\ : MX2 - port map(A => \un1_iu0_6[2]\, B => \un1_p0_6[354]\, S => - bpdata6_0_0, Y => \bpdata[2]\); - - \r.e.aluop_RNIUIL06[0]\ : MX2C - port map(A => N_3588, B => N_3652, S => \aluop_1[0]\, Y => - \logicout[29]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I90_Y : OA1A - port map(A => \data_0[1]\, B => \un1_iu0_6[1]\, C => N404_2, - Y => N549_0); - - \r.e.op1_RNIHP3M7[6]\ : OR3C - port map(A => \ex_op1_i_m[6]\, B => \op1_i_m[6]\, C => - \bpdata_i_m[6]\, Y => edata2_0_iv(6)); - - \r.m.result_RNIEVPK[4]\ : OA1A - port map(A => \maddress[4]\, B => d27, C => \cpi_m_i[356]\, - Y => \d_1_iv_1[4]\); - - \r.a.imm_RNO[29]\ : MX2 - port map(A => \inst_0[19]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[147]\); - - \r.m.ctrl.wy_RNI3TDC\ : NOR2A - port map(A => wy_1, B => wy_0, Y => y08_0); - - \r.a.ctrl.inst[30]\ : DFN1E0 - port map(D => \inst_0[30]\, CLK => lclk_c, E => holdn, Q - => \inst[30]\); - - \r.w.s.y[0]\ : DFN1E0 - port map(D => N_3764, CLK => lclk_c, E => N_6922_i_0, Q => - \y[0]\); - - \r.m.ctrl.pc[12]\ : DFN1E0 - port map(D => \pc_2[12]\, CLK => lclk_c, E => holdn, Q => - \pc_3[12]\); - - \r.e.ctrl.rd_RNI0KI31[5]\ : XNOR2 - port map(A => \rd[5]\, B => \un3_de_ren1[96]\, Y => - un2_rs1_1_5_i_0); - - \r.e.op2_RNI88NB1[16]\ : OR2A - port map(A => \un1_iu0_5[82]\, B => \un1_iu0_6[16]\, Y => - \logicout_4[16]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I298_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[8]\, B => N672, Y => - \un6_ex_add_res_s2[8]\); - - \comb.lock_gen.un1_icc_check5\ : NAND2 - port map(A => icc_check5, B => un1_icc_check5_2, Y => - un1_icc_check5); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_Y_3 : NOR3C - port map(A => I157_un1_Y_i_0, B => - ADD_33x33_fast_I260_Y_1_0, C => I213_un1_Y_i, Y => - ADD_33x33_fast_I260_Y_3_0); - - \r.e.ctrl.pc[27]\ : DFN1E0 - port map(D => \pc_0[27]\, CLK => lclk_c, E => holdn, Q => - \pc[27]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I39_Y_0_o3 : AOI1 - port map(A => N479_1, B => N475_0, C => N478_1, Y => N498_i); - - \r.w.result_RNI77PF[18]\ : AOI1B - port map(A => \un1_p0_6[370]\, B => d14, C => - \result_m_0_0[18]\, Y => \d_iv_0[18]\); - - \r.m.ctrl.trap_RNIJ6H22\ : NOR2A - port map(A => trap_0_sqmuxa_7, B => trap_2, Y => trap_2_0); - - \r.x.ctrl.wy_RNILF1N3\ : OR2B - port map(A => rstate_9_0, B => y_1_sqmuxa, Y => wy_RNILF1N3); - - \r.e.ctrl.rd[5]\ : DFN1E0 - port map(D => \rd_1[5]\, CLK => lclk_c, E => holdn, Q => - \rd[5]\); - - \r.x.icc_RNIFSID[3]\ : MX2C - port map(A => \icc_0[3]\, B => \icc_2[3]\, S => wicc, Y => - N_4183); - - un6_ex_add_res_d2_ADD_33x33_fast_I78_Y : OA1 - port map(A => \data_0[8]\, B => \un1_iu0_6[8]\, C => N419_0, - Y => N537_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I295_Y_0 : XOR3 - port map(A => \un1_iu0_6[4]\, B => \op2[4]\, C => N678_i, Y - => \un6_ex_add_res_s1_i[5]\); - - \r.m.y_RNO_1[23]\ : AOI1B - port map(A => \y[23]\, B => y08_0, C => \y_m[24]\, Y => - \y_iv_0[23]\); - - \r.d.cwp[2]\ : DFN1E0 - port map(D => \cwp_1[2]\, CLK => lclk_c, E => holdn, Q => - \cwp_0[2]\); - - \r.a.ctrl.pc_RNI6OE2C[25]\ : MX2 - port map(A => \pc_0[25]\, B => N_3902, S => ex_bpmiss_1, Y - => \fe_pc[25]\); - - \r.e.op2_RNIS7MB1[21]\ : NOR2A - port map(A => \un1_iu0_5[87]\, B => \un1_iu0_6[21]\, Y => - \logicout_3[21]\); - - \r.w.s.dwt\ : DFN1E0 - port map(D => N_170, CLK => lclk_c, E => holdn, Q => dwt); - - \comb.branch_address.tmp_ADD_30x30_fast_I274_Y_0_0\ : XOR2 - port map(A => \dpc[16]\, B => \inst_0[14]\, Y => - ADD_30x30_fast_I274_Y_0_0); - - \r.x.data_0_RNO_0[15]\ : NOR2B - port map(A => N_3473, B => data_0_0_15, Y => \dco_m_0[111]\); - - \r.d.inst_0_RNO[7]\ : NOR2B - port map(A => rst, B => N_4607, Y => \inst_0_RNO[7]\); - - \r.x.dci.size_RNISC8C9[0]\ : MX2C - port map(A => \size_1[0]\, B => \size_2[0]\, S => - dco_i_2(132), Y => \me_size_1[0]\); - - \r.e.op2_RNO_4[7]\ : OA1A - port map(A => \maddress[7]\, B => d27_0, C => - \cpi_m_i[359]\, Y => \d_1_iv_1[7]\); - - \r.e.ldbp2_RNIDJSF18\ : OR3C - port map(A => \aluresult_1_iv_8[30]\, B => - \shiftin_17_m_0[30]\, C => \un6_ex_add_res_m[31]\, Y => - \aluresult[30]\); - - \r.x.data_0_RNO_0[26]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_26, Y => - \dco_m_1[122]\); - - \r.e.shleft_RNIVDEF\ : NOR2A - port map(A => \un1_iu0_6[11]\, B => shleft, Y => - \shiftin_5_i[11]\); - - \r.e.ldbp2_RNIPVFHB5\ : OR3C - port map(A => \aluresult_1_iv_7[19]\, B => - \shiftin_17_m_0[19]\, C => \un6_ex_add_res_m[20]\, Y => - \aluresult[19]\); - - \r.a.ctrl.wreg_RNO_4\ : AOI1 - port map(A => write_reg7_0, B => un3_op, C => un1_inst, Y - => write_reg_2_sqmuxa); - - \r.x.result_RNI978B3[1]\ : MX2 - port map(A => \un1_iu0_6[1]\, B => \un1_p0_6[353]\, S => - bpdata6, Y => \bpdata[1]\); - - \r.d.inst_0_RNO[11]\ : NOR2B - port map(A => rst, B => N_4611, Y => \inst_0_RNO[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I52_un1_Y\ : OR3C - port map(A => \dpc[18]\, B => \inst_0[16]\, C => N410, Y - => I52_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I120_Y : NOR2B - port map(A => N521_1, B => N517_0, Y => N583_1); - - \r.x.result_RNIRN9B3[5]\ : MX2 - port map(A => \un1_iu0_6[5]\, B => \un1_p0_6[357]\, S => - bpdata6_0_0, Y => \bpdata[5]\); - - \r.m.result_RNI3R5A3[6]\ : NOR3C - port map(A => \d_iv_0[6]\, B => \result_m_0[6]\, C => - \rfo_m[6]\, Y => \d_iv_2[6]\); - - \r.d.inst_0[21]\ : DFN1 - port map(D => \inst_0_0_0_RNIQ98I03[21]\, CLK => lclk_c, Q - => \inst_0_0[21]\); - - \r.e.op2_RNIKONB1[27]\ : OR2A - port map(A => \un1_iu0_5[93]\, B => \un1_iu0_6[27]\, Y => - \logicout_4[27]\); - - \r.d.pc_RNO[28]\ : MX2 - port map(A => \fpc[28]\, B => \dpc[28]\, S => N_6763_i, Y - => \pc_RNO[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I108_Y : NOR2B - port map(A => N509, B => N505, Y => N571_0); - - \r.e.shcnt_RNI2HUGE[2]\ : MX2C - port map(A => \shiftin_11[33]\, B => \shiftin_11[29]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[29]\); - - \r.w.s.y_RNO[0]\ : MX2 - port map(A => \y_2[0]\, B => \result[0]\, S => N_481_0, Y - => N_3764); - - \r.x.result_RNIS4OE[28]\ : OR2B - port map(A => \un1_p0_6[380]\, B => d14, Y => - \cpi_m_0[380]\); - - \r.w.result[0]\ : DFN1E0 - port map(D => \wdata[0]\, CLK => lclk_c, E => holdn, Q => - \result_0[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I265_Y_0\ : XOR2 - port map(A => N614, B => ADD_30x30_fast_I265_Y_0_0, Y => - \tmp[7]\); - - \r.m.ctrl.trap_RNI2I4IU\ : OR2B - port map(A => tt_2_sqmuxa_1_0, B => un6_annul, Y => - tt_2_sqmuxa_1); - - \r.e.aluop_0_RNI81JD1[1]\ : XOR3 - port map(A => \un1_iu0_6[25]\, B => \aluop_0[1]\, C => - \un1_iu0_5[91]\, Y => N_6856); - - \r.a.ctrl.inst_RNIKK131[20]\ : NOR2 - port map(A => N_216, B => N_204, Y => N_6696); - - un6_ex_add_res_d2_ADD_33x33_fast_I17_P0N : AO1A - port map(A => ldbp1_4, B => \op1[16]\, C => \data_0[16]\, Y - => N446_1); - - \r.d.pc[22]\ : DFN1 - port map(D => \pc_RNO[22]\, CLK => lclk_c, Q => \dpc[22]\); - - \r.d.inst_0_RNO_0[1]\ : MX2 - port map(A => data_0_0_1, B => \inst_0[1]\, S => - mexc_1_sqmuxa_1_0, Y => N_4601); - - \r.m.result_RNI5PB4[8]\ : OR2B - port map(A => d13, B => \maddress[8]\, Y => \result_m_0[8]\); - - \r.e.op2_RNO_1[13]\ : AOI1B - port map(A => \op1[13]\, B => un14_casaen_s1_0_1, C => - \d_1_iv_3[13]\, Y => \d_1_iv_4[13]\); - - \r.d.inst_0_RNI7QTD1[4]\ : OR2 - port map(A => \inst_0_RNI4VUM[4]\, B => \inst_0_RNI3RUM[3]\, - Y => un1_reg); - - \r.m.y_RNO_4[28]\ : OR3A - port map(A => \y_2[28]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[28]\); - - \r.a.rsel1_0_RNIS88M2[2]\ : OR2B - port map(A => data1(4), B => d11_0, Y => \rfo_m[4]\); - - \r.a.imm_RNO[13]\ : MX2 - port map(A => \inst_0_RNI3RUM[3]\, B => \un1_p0_6_0[51]\, S - => call_hold5_0, Y => \un3_de_ren1[131]\); - - \r.e.op1_RNII04F[0]\ : OR2B - port map(A => \op1[0]\, B => un14_casaen_s1, Y => - \op1_m_i[0]\); - - \r.a.imm[18]\ : DFN1E0 - port map(D => \un3_de_ren1[136]\, CLK => lclk_c, E => holdn, - Q => \imm[18]\); - - \r.e.op2_RNIPS4F[4]\ : OR2A - port map(A => \un1_iu0_5[70]\, B => \un1_iu0_6[4]\, Y => - \logicout_4[4]\); - - \r.d.pc[31]\ : DFN1E0 - port map(D => \fpc[31]\, CLK => lclk_c, E => N_6763_i, Q - => \dpc[31]\); - - \r.a.ctrl.wicc_RNO_1\ : AO1 - port map(A => wicc_1_0_a3_1_1_0, B => N_152, C => - wicc_1_0_a3_0, Y => wicc_1_0_tz_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I22_G0N\ : NOR2B - port map(A => \dpc[24]\, B => \inst_0_0_0_RNI9O79[21]\, Y - => N424); - - \r.m.result_RNIAM2A3[1]\ : NOR3C - port map(A => \d_iv_0[1]\, B => \result_m_0[1]\, C => - \rfo_m[1]\, Y => \d_iv_2[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I180_Y : NOR2B - port map(A => N591_1, B => N583_2, Y => N649); - - un6_ex_add_res_d2_ADD_33x33_fast_I27_G0N : NOR2B - port map(A => \un1_iu0_6[26]\, B => \data_0[26]\, Y => - N475_1); - - \r.e.op1_RNI43OF[18]\ : NOR2A - port map(A => un17_casaen_0_1, B => \op1[18]\, Y => - \op1_i_m[18]\); - - \r.e.shcnt_RNIAIVC8[2]\ : MX2C - port map(A => \shiftin_11[5]\, B => \shiftin_11[1]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[1]\); - - \r.e.op2_RNO_5[5]\ : AOI1B - port map(A => \result[5]\, B => d31, C => \imm_m_i[5]\, Y - => \d_1_iv_0[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I307_Y_0 : AX1B - port map(A => N442_1, B => ADD_33x33_fast_I274_Y_0_a3, C - => \un6_ex_add_res_s0_1[17]\, Y => - \un6_ex_add_res_s2[17]\); - - \r.x.mexc_1_sqmuxa_0\ : NOR2A - port map(A => holdn, B => dco_i_2(132), Y => - mexc_1_sqmuxa_0); - - \r.e.sari_RNO\ : NOR3A - port map(A => aluadd_16_sqmuxa_0_a5_1, B => N_205, C => - \d_i[31]\, Y => sari_0); - - \r.e.jmpl_RNIINJV66\ : OR3C - port map(A => \aluresult_1_iv_8[22]\, B => - \shiftin_17_m_0[22]\, C => \un6_ex_add_res_m[23]\, Y => - \aluresult[22]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I118_un1_Y\ : OR2B - port map(A => N483, B => N480, Y => I118_un1_Y_i); - - \r.d.inst_0_RNO_0[6]\ : MX2 - port map(A => data_0_0_6, B => \inst_0[6]\, S => - inull_RNIFV6VG2_0, Y => N_4606); - - \r.a.ctrl.pc_RNIA0L0C[3]\ : MX2 - port map(A => \pc[3]\, B => N_3880, S => ex_bpmiss_1, Y => - \fe_pc[3]\); - - un6_fe_npc_I_173 : XOR2 - port map(A => N_30_1, B => \fe_pc[27]\, Y => I_173); - - \r.m.y_RNO_2[22]\ : OR2A - port map(A => \logicout[22]\, B => y14, Y => - \logicout_m[22]\); - - \r.m.dci.asi_RNO_0[0]\ : MX2 - port map(A => s, B => ps, S => rett_i, Y => su); - - un6_ex_add_res_d2_ADD_33x33_fast_I160_Y : NOR2B - port map(A => N571, B => N563_0, Y => N629_1); - - \r.m.result_RNI9JD4[21]\ : OR2B - port map(A => d13_0, B => \maddress[21]\, Y => - \result_m_0_0[21]\); - - \r.a.rsel1_RNI7R5338[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[31]\, Y => - \aluresult_m_0[31]\); - - un6_fe_npc_I_128 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[14]\, Y => N_61); - - \r.f.pc_RNIIODR76[11]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[11]\, C => - \xc_trap_address_m[11]\, Y => m14_0); - - \r.a.imm_RNO[28]\ : MX2 - port map(A => \inst_0[18]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[146]\); - - \r.m.result_RNI9MI7[1]\ : OR2 - port map(A => \maddress[1]\, B => \maddress[0]\, Y => - result_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I184_Y\ : OR2 - port map(A => N552_2, B => I184_un1_Y, Y => N612); - - \r.e.ctrl.inst_RNIS08H[21]\ : OR2 - port map(A => \inst_1[21]\, B => force_a2_0, Y => - force_a2_1); - - \r.x.ctrl.pc_RNIR1N9[25]\ : MX2 - port map(A => \pc_2[25]\, B => \pc[25]\, S => \npc[1]\, Y - => N_3236); - - \r.a.ctrl.inst_RNIEK1E[22]\ : NOR2B - port map(A => \inst[22]\, B => \inst_2[19]\, Y => N_256_i_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I5_G0N : NOR3A - port map(A => \op1[4]\, B => ldbp1, C => \data_0[4]\, Y => - N409_0); - - \r.e.op2_RNIIONB1[18]\ : OR2A - port map(A => \un1_iu0_5[84]\, B => \un1_iu0_6[18]\, Y => - \logicout_4[18]\); - - \r.f.pc_RNIB83E01[10]\ : MX2 - port map(A => \fpc[10]\, B => \eaddress[10]\, S => jump_0, - Y => N_4053); - - un6_ex_add_res_d2_ADD_33x33_fast_I4_P0N : AO1A - port map(A => ldbp1_4, B => \op1[3]\, C => \data_0[3]\, Y - => N407_1); - - \r.e.shleft_1_RNID40G3\ : MX2 - port map(A => \shiftin_5[50]\, B => \shiftin_5[34]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[34]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I306_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[16]\, B => N796_0, Y => - \un6_ex_add_res_s2[16]\); - - \r.e.shcnt_RNIUNLOQ[1]\ : MX2C - port map(A => \shiftin_14[23]\, B => \shiftin_14[21]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[21]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I232_Y\ : OR3C - port map(A => ADD_30x30_fast_I232_Y_2, B => I190_un1_Y, C - => I232_un1_Y, Y => N694); - - \r.a.ctrl.wy_RNO\ : OA1B - port map(A => wy_1_0_a3_0_4, B => wy_1_0_a3_1, C => N_143, - Y => wy_1_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I121_Y_0 : MAJ3 - port map(A => \data_0[17]\, B => \un1_iu0_6[17]\, C => N445, - Y => ADD_33x33_fast_I121_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I301_Y_0 : XNOR2 - port map(A => N811, B => \un6_ex_add_res_s2_1[11]\, Y => - \un6_ex_add_res_s0[11]\); - - \r.e.op2_RNO_4[20]\ : NOR3C - port map(A => \result_m_i[20]\, B => \imm_m_i[20]\, C => - \d_1_iv_1[20]\, Y => \d_1_iv_2[20]\); - - \r.f.pc_RNO_0[23]\ : NAND2 - port map(A => \tmp[23]\, B => un2_rstn_5_0, Y => - \tmp_m[23]\); - - \r.e.aluop_0_RNI0544G1[0]\ : NOR3C - port map(A => \aluresult_1_iv_5[16]\, B => - \logicout_m_0[16]\, C => \shiftin_17_m[17]\, Y => - \aluresult_1_iv_7[16]\); - - \r.e.op2_RNO_4[6]\ : OA1A - port map(A => \maddress[6]\, B => d27, C => \cpi_m_i[358]\, - Y => \d_1_iv_1[6]\); - - \r.e.shcnt_RNIQG5R3[3]\ : MX2 - port map(A => \shiftin_8[8]\, B => \shiftin_8[0]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[0]\); - - \r.x.result_RNIEGQL8[0]\ : MX2C - port map(A => \result[0]\, B => N_6527, S => cwp_1_sqmuxa_0, - Y => N_3870); - - \r.e.op2_RNO_8[17]\ : OR3B - port map(A => d29_0, B => \imm[17]\, C => \rsel2_1[0]\, Y - => \imm_m_i[17]\); - - \r.f.pc[20]\ : DFN1E0 - port map(D => \pc_1[20]\, CLK => lclk_c, E => holdn, Q => - \fpc[20]\); - - \r.e.op2[17]\ : DFN1E0 - port map(D => N_301, CLK => lclk_c, E => holdn, Q => - \op2[17]\); - - \r.d.inst_0_RNO[14]\ : NOR2B - port map(A => rst, B => N_4614, Y => \inst_0_RNO[14]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I2_P0N : OR2 - port map(A => \un1_iu0_6[1]\, B => \op2[1]\, Y => N401_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I137_Y : AO1 - port map(A => N538, B => N535, C => ADD_33x33_fast_I137_Y_0, - Y => N600); - - \r.m.y[5]\ : DFN1E0 - port map(D => \y_0[5]\, CLK => lclk_c, E => holdn, Q => - \y_2[5]\); - - \r.m.dci.asi[0]\ : DFN1E0 - port map(D => \asi[0]\, CLK => lclk_c, E => holdn, Q => - asi_0(0)); - - \r.e.shleft_RNIQ7CF1\ : MX2A - port map(A => \shiftin_5[27]\, B => \shiftin_5_i[11]\, S - => \ex_shcnt_1_i[4]\, Y => \shiftin_8[11]\); - - \r.e.shcnt_RNITO1A4[3]\ : MX2 - port map(A => \shiftin_8[12]\, B => \shiftin_8[4]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[4]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I280_Y_0\ : XNOR2 - port map(A => N712_i, B => ADD_30x30_fast_I280_Y_0_0, Y => - \tmp[22]\); - - \comb.v.x.data_0_1_1_iv_RNO[16]\ : OR2 - port map(A => \data_0_1_1[16]\, B => \data_0_1_1_iv_0[16]\, - Y => \data_0_1_1_iv_1[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I122_Y : NOR3C - port map(A => N443_0, B => N440_0, C => N519_0, Y => N585); - - \r.e.op1_RNIE81M7[1]\ : OR3C - port map(A => \ex_op1_i_m[1]\, B => \op1_i_m[1]\, C => - \bpdata_i_m[1]\, Y => edata2_0_iv(1)); - - \r.x.data_0_RNO[23]\ : OR3 - port map(A => \dco_m_0[119]\, B => \data_0_m[23]\, C => - \data_0_1_4[18]\, Y => \data_0_1[23]\); - - \r.m.result_0_RNIENIJ1[3]\ : OAI1 - port map(A => \maddress_0[3]\, B => \maddress[4]\, C => - trap27, Y => trap_0_sqmuxa); - - \r.e.ldbp2_RNI1UFSV7\ : NOR3 - port map(A => \eaddress[28]\, B => un1_addout_12_0, C => - \eaddress[16]\, Y => \un1_addout_12\); - - \r.e.jmpl_RNI31UJV_0\ : OR2B - port map(A => \shiftin_17[30]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[30]\); - - \r.x.ctrl.inst[24]\ : DFN1E0 - port map(D => \inst_0[24]\, CLK => lclk_c, E => holdn, Q - => \inst_2[24]\); - - \r.e.aluop_2_RNIJ26R2[1]\ : MX2C - port map(A => N_3552, B => \logicout_3[25]\, S => - \aluop_2[1]\, Y => N_3584); - - un6_fe_npc_I_31 : XOR2 - port map(A => N_131, B => \fe_pc[8]\, Y => I_31); - - \r.x.ctrl.wy_RNIRE1D\ : OR2A - port map(A => wy_2, B => wy_1, Y => wy_1_0_0); - - \r.d.inull_RNICHGG\ : AO1 - port map(A => \inull\, B => hold_pc_0_sqmuxa, C => - hold_pc_2_m, Y => N_3034); - - \r.w.s.pil_RNIF8C79[2]\ : AOI1B - port map(A => \bpdata[10]\, B => N_3974, C => - \aluresult_1_iv_2[10]\, Y => \aluresult_1_iv_4[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I128_Y : OR2B - port map(A => N529_0, B => N525_1, Y => N591_2); - - \r.e.aluop_0_RNIK9N4D[0]\ : NOR2B - port map(A => \aluresult_1_iv_5[6]\, B => \logicout_m_0[6]\, - Y => \aluresult_1_iv_6[6]\); - - \r.m.dci.lock_RNO_1\ : OR3A - port map(A => \inst[19]\, B => \inst[24]\, C => N_3749_3, Y - => N_3748); - - \r.e.op2_RNIVFMB1[22]\ : OR2A - port map(A => \un1_iu0_5[88]\, B => \un1_iu0_6[22]\, Y => - \logicout_4[22]\); - - \r.e.op1_RNICRPRB[10]\ : NOR3 - port map(A => \bpdata_i_m_2[2]\, B => \edata2_0_iv_0[10]\, - C => \bpdata_i_m[10]\, Y => edata2_0_iv(10)); - - un6_ex_add_res_d1_ADD_33x33_fast_I261_un1_Y : OR3C - port map(A => N645_1, B => N629, C => N802_0, Y => - I261_un1_Y_0); - - \r.m.ctrl.rd_RNIEFCA7[4]\ : NOR3C - port map(A => wreg_3, B => \rd_RNI2Q6H1[7]\, C => - un1_de_ren1_1_4_i_0, Y => wreg_5); - - \r.e.shleft_RNIIM661\ : MX2A - port map(A => \shiftin_5[25]\, B => \shiftin_5_i[9]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[9]\); - - \r.e.shcnt_RNIQN6B7[3]\ : MX2 - port map(A => \shiftin_8[41]\, B => \shiftin_8[33]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[33]\); - - \r.m.result_RNO[0]\ : MX2 - port map(A => \aluresult[0]\, B => \op1[0]\, S => - un17_casaen_0_2, Y => \eres2[0]\); - - \r.f.pc_RNO_6[30]\ : MX2 - port map(A => I_203, B => N_4073, S => bpmiss_1_i_0, Y => - \pc_4[30]\); - - \r.e.shleft_0\ : DFN1E0 - port map(D => N_208, CLK => lclk_c, E => holdn, Q => - shleft_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I11_P0N : OR3A - port map(A => \data_0[10]\, B => \op1[10]\, C => ldbp1_2, Y - => N428_0); - - \r.x.laddr_RNI21NB9[0]\ : MX2 - port map(A => \maddress[0]\, B => \laddr[0]\, S => - dco_i_2(132), Y => \me_laddr_2[0]\); - - \r.a.ctrl.ld_RNO\ : MX2C - port map(A => \inst_0_0[21]\, B => write_reg_0_sqmuxa_1, S - => ld_1_sqmuxa, Y => ld_2); - - \r.e.op1_RNI596JF[26]\ : NOR3C - port map(A => \edata2_iv_0[26]\, B => \bpdata_i_m[26]\, C - => \edata2_iv_2[26]\, Y => edata2_iv_i_0(26)); - - \r.m.wcwp\ : DFN1E0 - port map(D => wcwp_0, CLK => lclk_c, E => holdn, Q => wcwp); - - \r.a.imm_RNO[25]\ : MX2 - port map(A => \inst_0[15]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[143]\); - - \r.e.aluop_RNICSR04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[6]\, Y => - \bpdata_i_m_2[6]\); - - \r.x.dci.SIGNED_RNIIUIRU9\ : OR3 - port map(A => \rdata_13_m[8]\, B => \rdata_17_m[8]\, C => - \data_0_1_1[12]\, Y => \data_0_1_4[9]\); - - \r.e.op1_RNIJKHP7[14]\ : OR2 - port map(A => \bpdata_i_m[14]\, B => \edata2_0_iv_0[14]\, Y - => \edata2_0_iv_1[14]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_Y_2 : NOR3C - port map(A => I159_un1_Y_1, B => ADD_33x33_fast_I261_Y_0_0, - C => I215_un1_Y_0, Y => ADD_33x33_fast_I261_Y_2_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I157_un1_Y : OR3B - port map(A => N495_0, B => N568_1, C => N_50_1, Y => - I157_un1_Y_i_0); - - \r.x.rstate_RNO[1]\ : OA1A - port map(A => rstate_1188n, B => holdn, C => N_6323, Y => - N_6323s); - - \r.e.aluop_RNIGM3N1[1]\ : NOR2 - port map(A => edata_1_sqmuxa, B => edata_0_sqmuxa, Y => - N_3703_i); - - \r.m.y_RNO_2[11]\ : OR2A - port map(A => \logicout[11]\, B => y14, Y => - \logicout_m[11]\); - - \r.f.pc_RNO[18]\ : OR3C - port map(A => \tmp_m[18]\, B => \pc_1_iv_1[18]\, C => - \un6_fe_npc_m[16]\, Y => \pc_1[18]\); - - \r.e.op2_RNO_2[21]\ : NOR3C - port map(A => \d_1_iv_1[21]\, B => \d_1_iv_0[21]\, C => - \rfo_m_i[53]\, Y => \d_1_iv_3[21]\); - - \r.e.op1_RNI7HFC[3]\ : OR2B - port map(A => \op1[3]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I46_Y : NOR2B - port map(A => N470_0, B => N467, Y => N505_0); - - \r.e.ctrl.wicc_RNO\ : NOR3B - port map(A => ra_bpannul_1, B => wicc_0, C => \un1_p0_6[0]\, - Y => wicc_1_0); - - \r.e.ctrl.inst_RNI5I3O1[22]\ : OR2B - port map(A => un3_op_2, B => un3_op_1, Y => un3_op_i); - - \r.m.ctrl.rd_RNIFP2A1[1]\ : XA1A - port map(A => \un3_de_ren1[92]\, B => \rd_0[1]\, C => - un2_rs1_2_2_i_0, Y => wreg_1_2_0); - - \r.f.pc_RNO_4[31]\ : MX2 - port map(A => I_210, B => N_4074, S => bpmiss_1_i_0_0, Y - => \pc_4[31]\); - - \r.e.op1_RNIFKSFN7[29]\ : AOI1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[29]\, C - => \d_iv_3[29]\, Y => \d_i[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I2_G0N : NOR2B - port map(A => \un1_iu0_6[1]\, B => \op2[1]\, Y => N400_0); - - \r.w.s.wim_RNIB5RD2[5]\ : OR2B - port map(A => \wim[5]\, B => aluresult_13_sqmuxa, Y => - \wim_m[5]\); - - \r.m.result_RNI6CJN[28]\ : NOR3C - port map(A => \result_m_0[28]\, B => \cpi_m_0[380]\, C => - \result_m_0_0[28]\, Y => \d_iv_1[28]\); - - \r.e.op2_RNO_6[13]\ : AOI1B - port map(A => \result[13]\, B => d31, C => \imm_m_i[13]\, Y - => \d_1_iv_0[13]\); - - \r.x.ctrl.inst[27]\ : DFN1E0 - port map(D => \inst_3[27]\, CLK => lclk_c, E => holdn, Q - => \inst[27]\); - - \r.a.rsel2_0_RNI58AN3[0]\ : AOI1B - port map(A => data2(4), B => d25_0, C => \d_1_iv_2[4]\, Y - => \d_1_iv_3[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I25_P0N : AO1A - port map(A => ldbp1_4, B => \op1[24]\, C => \data_0[24]\, Y - => N470_0); - - \r.e.aluop_RNIVGC66[0]\ : MX2C - port map(A => N_3570, B => N_3634, S => \aluop_1[0]\, Y => - \logicout[11]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I259_Y_1 : NOR3C - port map(A => I33_un1_Y_1, B => N487, C => I95_un1_Y, Y => - ADD_33x33_fast_I259_Y_1); - - \r.a.ctrl.pc[26]\ : DFN1E0 - port map(D => \dpc[26]\, CLK => lclk_c, E => holdn, Q => - \pc_0[26]\); - - \r.m.y_RNO_3[23]\ : OR3A - port map(A => \y_2[23]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[23]\); - - \r.m.y_RNI96NI4[15]\ : NOR3C - port map(A => \cpi_m[160]\, B => \y_m_1[15]\, C => - \aluresult_1_iv_0[15]\, Y => \aluresult_1_iv_2[15]\); - - \r.d.pc_RNO[21]\ : MX2 - port map(A => \fpc[21]\, B => \dpc[21]\, S => N_6763_i_0, Y - => \pc_RNO[21]\); - - \r.e.op2_RNO_5[8]\ : NOR2B - port map(A => \imm_m_i[8]\, B => \result_m_i[8]\, Y => - \d_1_iv_0[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I54_Y : NOR2B - port map(A => N458, B => N455_2, Y => N513_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I239_un1_Y : NOR2B - port map(A => N668_1, B => N653_0, Y => I239_un1_Y_1); - - \r.e.aluop_RNI7UIK4[0]\ : OR2B - port map(A => \logicout[2]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[2]\); - - \r.e.jmpl_RNI85S3N\ : OR2B - port map(A => \shiftin_17[10]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[10]\); - - \r.a.rsel1_0[2]\ : DFN1E0 - port map(D => rs1, CLK => lclk_c, E => holdn, Q => - \rsel1_0[2]\); - - \r.e.aluop_RNI9EAU2[1]\ : MX2C - port map(A => N_3538, B => \logicout_3[11]\, S => - \aluop_3[1]\, Y => N_3570); - - \r.x.mexc_1_sqmuxa\ : NOR2A - port map(A => holdn, B => dco_i_2(132), Y => mexc_1_sqmuxa); - - \r.e.aluop_RNIAUMP8[2]\ : AOI1 - port map(A => edata_1_sqmuxa, B => \bpdata[12]\, C => - \bpdata_i_m_2[4]\, Y => \edata2_iv_2[28]\); - - \r.e.aluop_0_RNIBR1T2[1]\ : MX2C - port map(A => \logicout_4[25]\, B => N_6856, S => - N_6866_i_0, Y => N_3648); - - \r.e.op1_RNO[14]\ : MX2C - port map(A => \d_i[14]\, B => \d_i[15]\, S => N_227, Y => - \aop1[14]\); - - \r.a.imm[2]\ : DFN1E0 - port map(D => \un3_de_ren1[120]\, CLK => lclk_c, E => holdn, - Q => \imm[2]\); - - \r.m.dci.asi[2]\ : DFN1E0 - port map(D => \asi[2]\, CLK => lclk_c, E => holdn, Q => - asi_0(2)); - - \r.e.ctrl.inst_RNIJ41E[24]\ : OR2B - port map(A => \inst_0[23]\, B => \inst[24]\, Y => N_3749_2); - - \r.x.result_RNIQPKJ3[11]\ : MX2C - port map(A => \un1_iu0_6[11]\, B => \un1_p0_6[363]\, S => - bpdata6, Y => \bpdata[11]\); - - \r.f.pc_RNIT1222[8]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[8]\, Y => \xc_trap_address_m[8]\); - - \r.x.rstate_RNIOP1U[1]\ : OR2A - port map(A => rst, B => xc_exception_1, Y => \un1_p0_6[0]\); - - \r.e.op2_RNISM992[12]\ : AOI1B - port map(A => \un1_iu0_5[78]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[12]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I250_Y_0_a3 : NOR2B - port map(A => N672_0, B => N419_1, Y => - ADD_33x33_fast_I250_Y_0_a3); - - \r.a.ctrl.pc[14]\ : DFN1E0 - port map(D => \dpc[14]\, CLK => lclk_c, E => holdn, Q => - \pc[14]\); - - wovf_exc_0_sqmuxa_1 : NOR2 - port map(A => un7_op, B => \wovf_exc_0_sqmuxa\, Y => - \wovf_exc_0_sqmuxa_1\); - - \r.m.y_RNO_2[8]\ : OR2A - port map(A => \logicout[8]\, B => y14, Y => \logicout_m[8]\); - - \r.e.ctrl.cnt_RNIBT47[0]\ : OR2A - port map(A => \cnt[1]\, B => \cnt[0]\, Y => N_3355_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I31_G0N : OR2B - port map(A => \un1_iu0_6[30]\, B => \data_0[30]\, Y => - N487_0); - - \r.x.icc[1]\ : DFN1E0 - port map(D => \icc[1]\, CLK => lclk_c, E => holdn, Q => - \icc_3[1]\); - - \r.w.result[14]\ : DFN1E0 - port map(D => \wdata[14]\, CLK => lclk_c, E => holdn, Q => - \result[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I16_P0N\ : OR2 - port map(A => \inst_0[16]\, B => \dpc[18]\, Y => N407_0); - - \r.f.pc_RNI5DT811[2]\ : MX2A - port map(A => \fe_pc[2]\, B => N_4045, S => bpmiss_1_i_0_0, - Y => \pc_4[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I70_Y : OA1 - port map(A => \op2[12]\, B => \un1_iu0_6[12]\, C => N431_1, - Y => N529_1); - - \r.m.y_RNO_1[24]\ : OR2B - port map(A => \y_2[25]\, B => mulstep_1, Y => N_374); - - \r.m.dci.size_RNO_1[0]\ : OA1A - port map(A => \inst[19]\, B => \inst_1[21]\, C => - \inst[24]\, Y => N_3757); - - \r.e.jmpl_RNITN6O_1\ : NOR3 - port map(A => jmpl, B => aluresult_1_sqmuxa_0_0, C => - \ex_shcnt_1[0]\, Y => aluresult_1_sqmuxa); - - \r.m.result[26]\ : DFN1E0 - port map(D => \eres2[26]\, CLK => lclk_c, E => holdn, Q => - \maddress[26]\); - - un6_fe_npc_I_24 : XOR2 - port map(A => N_136, B => \fe_pc[7]\, Y => I_24); - - un2_rstn_5_RNIROLH1 : NAND2 - port map(A => \tmp[3]\, B => \un2_rstn_5\, Y => \tmp_m[3]\); - - \r.m.ctrl.trap_RNI90MMC\ : OR2B - port map(A => me_nullify2_1_2_1, B => nullify_1_sqmuxa, Y - => \me_nullify2_1_2\); - - \r.e.ctrl.inst_RNI2H1S[24]\ : NOR2A - port map(A => N_3749_2, B => N_3356_3, Y => - enaddr_2_sqmuxa_1); - - \r.e.jmpl_RNISAER71\ : AOI1B - port map(A => \shiftin_17[3]\, B => aluresult_1_sqmuxa, C - => \aluresult_2_iv_6[2]\, Y => \aluresult_2_iv_7[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I282_Y_0\ : AX1D - port map(A => I239_un1_Y, B => ADD_30x30_fast_I239_Y_1, C - => ADD_30x30_fast_I282_Y_0_0, Y => \tmp[24]\); - - \r.m.result[12]\ : DFN1E0 - port map(D => \eres2[12]\, CLK => lclk_c, E => holdn, Q => - \maddress[12]\); - - \r.e.op2_RNO_0[25]\ : OR3C - port map(A => \op1_m_i[25]\, B => \d_1_iv_3[25]\, C => - \aluresult_m_i[25]\, Y => \d_1[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I195_Y : AO1 - port map(A => N606_2, B => N599_2, C => N598_2, Y => N664); - - \r.w.s.y_RNO_2[29]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[29]\, Y - => N_414); - - \r.e.aluop_RNI77PI2[1]\ : MX2C - port map(A => N_3547, B => \logicout_3[20]\, S => - \aluop_3[1]\, Y => N_3579); - - \r.a.ctrl.inst_RNI628V1[19]\ : OA1 - port map(A => N_262, B => aluop_1_1_0_a5_0, C => N_344, Y - => aluop_1_1_0_0); - - \r.e.op1_RNIST53T1[0]\ : OR3C - port map(A => \op1_m_0[0]\, B => \d_iv_2[0]\, C => - \aluresult_m_0[0]\, Y => \d[0]\); - - \r.m.icc_RNO_10[2]\ : NOR3A - port map(A => icc_0_sqmuxa_1_16, B => \logicout[22]\, C => - \logicout[21]\, Y => icc_0_sqmuxa_1_24); - - \r.e.ctrl.pc[10]\ : DFN1E0 - port map(D => \pc_3[10]\, CLK => lclk_c, E => holdn, Q => - \pc_0[10]\); - - \r.m.ctrl.inst_RNITC0E[20]\ : NOR2A - port map(A => \inst_3[20]\, B => \inst[21]\, Y => inst_4_1); - - \r.d.annul_RNIFM901\ : AOI1 - port map(A => hold_pc_2_sqmuxa, B => hold_pc_0_sqmuxa_1, C - => annul_1, Y => annul_2_0); - - \r.m.y[9]\ : DFN1E0 - port map(D => \y_0[9]\, CLK => lclk_c, E => holdn, Q => - \y_1[9]\); - - \r.w.result[17]\ : DFN1E0 - port map(D => \wdata[17]\, CLK => lclk_c, E => holdn, Q => - \result[17]\); - - \r.a.rsel2_0_RNI7V53_0[0]\ : OR2A - port map(A => d28_0_0, B => \rsel2_0[0]\, Y => d27); - - \r.e.shcnt_RNIKJ4TL[1]\ : MX2C - port map(A => \shiftin_14[10]\, B => \shiftin_14[8]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[8]\); - - \r.a.ctrl.inst_RNIKJV9I1[13]\ : NOR2B - port map(A => illegal_inst_7_iv_7, B => - illegal_inst_7_iv_6_0, Y => illegal_inst_7_i_0); - - \r.e.jmpl_RNIRSOT\ : OR2A - port map(A => miscout_11_sqmuxa, B => jmpl, Y => jmpl_4); - - \r.e.op2_RNO_3[14]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[14]\, Y => - \aluresult_m_i[14]\); - - \r.d.inst_0[15]\ : DFN1 - port map(D => \inst_0_RNO[15]\, CLK => lclk_c, Q => - \inst_0[15]\); - - \r.d.inst_0_RNI0423[20]\ : NOR2 - port map(A => \inst_0[20]\, B => \inst_0_0[22]\, Y => - fins_0_a3_0); - - \r.x.data_0_RNO_1[7]\ : NOR3C - port map(A => \dco_m_i[111]\, B => \data_0_m_i[7]\, C => - \dco_m_i[127]\, Y => \data_0_1_1_iv_1[7]\); - - \r.w.s.icc_RNO[0]\ : AO1B - port map(A => icc_1_sqmuxa, B => \icc[0]\, C => - \icc_1_iv_0[0]\, Y => \icc_1[0]\); - - \r.m.ctrl.inst_RNIHFAI01[30]\ : NOR2 - port map(A => \me_nullify2_1_2\, B => \nullify2_0_sqmuxa\, - Y => me_nullify2_1_0); - - \r.a.ctrl.rd_RNIAI7Q[1]\ : XNOR2 - port map(A => \inst_0_RNI1JUM[1]\, B => \rd_2[1]\, Y => - un1_de_ren1_1_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I267_Y_0 : NOR2A - port map(A => I227_un1_Y, B => N640_0, Y => - ADD_33x33_fast_I267_Y_0_0); - - \r.e.op2_RNO_2[10]\ : OR2B - port map(A => data2(10), B => d25_0, Y => \rfo_m_i[42]\); - - \r.e.ctrl.inst_RNIHI8M1[20]\ : NOR3B - port map(A => aluresult_13_sqmuxa_1, B => - aluresult_13_sqmuxa_0_0, C => aluresult_9_sqmuxa_1, Y => - aluresult_13_sqmuxa_3_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I285_Y_0_0\ : XOR2 - port map(A => \dpc[27]\, B => \inst_0_1[27]\, Y => - ADD_30x30_fast_I285_Y_0_0); - - \r.d.inst_0_0_0_RNI7IM7_0[21]\ : NOR2B - port map(A => \inst_0_0[22]\, B => \un1_p0_6_0[60]\, Y => - ldcheck1_5_i_a6_2_1); - - \r.a.rsel1_0_RNIJ7LJ2[2]\ : OR2B - port map(A => data1(29), B => d11, Y => \rfo_m[29]\); - - \r.a.ctrl.wy_RNO_3\ : NOR2 - port map(A => N_3525_3, B => N_122_1, Y => wy_1_0_a3_0_7_2); - - \comb.dcache_gen.un1_r.e.ctrl.trap\ : NOR2 - port map(A => un1_annul, B => trap_0, Y => trap); - - un6_ex_add_res_d1_ADD_33x33_fast_I26_G0N : NOR2B - port map(A => \un1_iu0_6[25]\, B => \op2[25]\, Y => N472_0); - - \r.m.ctrl.pc_RNIS6AE[4]\ : MX2 - port map(A => \pc_3[4]\, B => \pc_0[4]\, S => \npc_1[1]\, Y - => N_3245); - - \r.a.rfe1\ : DFN1E0 - port map(D => rfe_1, CLK => lclk_c, E => holdn, Q => \rfe1\); - - \r.w.s.wim_RNIJSJV2[4]\ : AOI1B - port map(A => \wim[4]\, B => aluresult_13_sqmuxa, C => - aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[4]\); - - \r.e.shleft_RNIL6FC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[15]\, S => - shleft, Y => \shiftin_5[46]\); - - \r.d.inst_0_RNO_0[22]\ : MX2 - port map(A => data_0_22, B => \inst_0_0[22]\, S => - inull_RNIFV6VG2_0, Y => N_4622); - - un6_ex_add_res_d2_ADD_33x33_fast_I270_Y_0_a3_1 : NOR2B - port map(A => N455_1, B => N452_1, Y => N_71_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I116_Y : NOR2B - port map(A => N517, B => N513_0, Y => N579_0); - - \r.a.rsel1_0_RNIA3LJ2[2]\ : OR2B - port map(A => data1(13), B => d11, Y => \rfo_m[13]\); - - \r.a.ctrl.inst[23]\ : DFN1E0 - port map(D => \inst_0_0[23]\, CLK => lclk_c, E => holdn, Q - => \inst_1[23]\); - - \r.f.pc_RNO_2[25]\ : OR2B - port map(A => I_156, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[23]\); - - \r.a.ctrl.inst_RNI7C0E_1[31]\ : OR2A - port map(A => \inst[30]\, B => \inst[31]\, Y => N_344); - - \r.e.jmpl_RNIVRLVA3\ : OR3C - port map(A => \aluresult_1_iv_7[12]\, B => - \shiftin_17_m_0[12]\, C => \un6_ex_add_res_m[13]\, Y => - \aluresult[12]\); - - \comb.v.x.data_0_1_1_iv_RNO[31]\ : OR2 - port map(A => \data_0_1_1[16]\, B => \data_0_1_1_iv_0[31]\, - Y => \data_0_1_1_iv_1[31]\); - - \r.f.pc_RNIOH32M1[4]\ : OA1A - port map(A => \fpc[4]\, B => rst, C => - \un6_ex_add_res_m_1[5]\, Y => \npc_iv_1[4]\); - - \r.e.op2_RNO[26]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[26]\, Y => N_310); - - \r.e.op1_RNIMP3B2[14]\ : AO1A - port map(A => \un1_iu0_6[14]\, B => edata_3_sqmuxa_0, C => - \op1_i_m[14]\, Y => \edata2_0_iv_0[14]\); - - \r.m.result_RNIABJN[21]\ : NOR3C - port map(A => \result_m_0[21]\, B => \cpi_m_0[373]\, C => - \result_m_0_0[21]\, Y => \d_iv_1[21]\); - - \r.m.icc_RNO_24[2]\ : NOR3A - port map(A => icc_0_sqmuxa_1_5, B => \logicout[16]\, C => - \logicout[15]\, Y => icc_0_sqmuxa_1_19); - - \comb.op_mux.d_1_iv_RNO_2[29]\ : NOR3C - port map(A => \d_1_iv_1[29]\, B => \d_1_iv_0[29]\, C => - \rfo_m_i[61]\, Y => \d_1_iv_3[29]\); - - \r.x.data_0_RNO_4[4]\ : NAND2 - port map(A => data_0_12, B => rdata_2_sqmuxa, Y => - \dco_m_i[108]\); - - \r.x.data_0[30]\ : DFN1E0 - port map(D => \data_0_1[30]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[30]\); - - \r.f.pc_RNO_3[27]\ : NAND2 - port map(A => \tmp[27]\, B => \un2_rstn_5\, Y => - \tmp_m[27]\); - - \r.a.rsel2_RNI9LB_1[1]\ : NOR2A - port map(A => \rsel2[2]\, B => \rsel2[1]\, Y => d29_0_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_Y_1 : AOI1B - port map(A => N652_0, B => N637, C => - ADD_33x33_fast_I265_Y_0_0, Y => ADD_33x33_fast_I265_Y_1); - - \r.e.shcnt_RNI8D0R7[3]\ : MX2 - port map(A => \shiftin_8[44]\, B => \shiftin_8[36]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[36]\); - - \r.a.rsel1_RNIDCJV22[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[2]\, Y => - \aluresult_m_0[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I183_un1_Y\ : OR2B - port map(A => N558, B => N551, Y => I183_un1_Y_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I306_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[16]\, B => N796_1, Y => - \un6_ex_add_res_s0[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I179_Y : AO1 - port map(A => N590_2, B => N583_0, C => N582_1, Y => N648); - - \r.m.result_0_RNI5ER8[1]\ : OR2A - port map(A => \maddress_0[1]\, B => d27, Y => - \result_m_i[1]\); - - \r.d.inst_0_RNO[3]\ : NOR2B - port map(A => rst, B => N_4603, Y => \inst_0_RNO[3]\); - - \r.x.laddr_RNI66ENI[0]\ : OR2A - port map(A => \me_laddr_2[0]\, B => \me_laddr_2[1]\, Y => - rdata_1_sqmuxa_0); - - un54_ra_I_15 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => \ncwp[1]\, Y - => \DWACT_ADD_CI_0_g_array_1[0]\); - - \r.x.result[26]\ : DFN1E0 - port map(D => \maddress[26]\, CLK => lclk_c, E => holdn, Q - => \result[26]\); - - \r.e.op2_RNO_6[25]\ : OR2B - port map(A => data2(25), B => d25, Y => \rfo_m_i[57]\); - - \r.a.ctrl.pc[13]\ : DFN1E0 - port map(D => \dpc[13]\, CLK => lclk_c, E => holdn, Q => - \pc[13]\); - - \r.x.ctrl.inst_RNIE0331[20]\ : NOR3B - port map(A => y6_0, B => y10_3_0, C => \inst[20]\, Y => y10); - - \r.w.s.y_RNO[11]\ : MX2 - port map(A => \y_2[11]\, B => \result_0[11]\, S => N_481_0, - Y => N_3775); - - \r.a.ctrl.wreg_RNO_7\ : OR2B - port map(A => \inst_0[19]\, B => N_145, Y => un3_op); - - \r.x.ctrl.annul_RNI0THC\ : NOR2 - port map(A => annul_0, B => \rstate_d[2]\, Y => rstate_8_0); - - \r.m.result[8]\ : DFN1E0 - port map(D => \eres2[8]\, CLK => lclk_c, E => holdn, Q => - \maddress[8]\); - - \r.e.op2_RNO_1[7]\ : OR2B - port map(A => \op1[7]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[7]\); - - \r.f.pc_RNI9IB62[5]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[5]\, Y => \xc_trap_address_m[5]\); - - \r.e.aluop_RNIFC5U6[0]\ : OR2B - port map(A => \logicout[21]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[21]\); - - \r.f.pc_RNO_7[31]\ : MX2 - port map(A => \fpc[31]\, B => \tba[19]\, S => - rstate_6314_d_0, Y => \xc_trap_address[31]\); - - \r.e.op2_RNO_7[8]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[360]\, Y => \cpi_m_i[360]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I20_P0N : AO1A - port map(A => ldbp1_1, B => \op1[19]\, C => \data_0[19]\, Y - => N455_1); - - \r.w.s.y[21]\ : DFN1E0 - port map(D => N_3785, CLK => lclk_c, E => N_6922_i_0, Q => - \y_2[21]\); - - \r.f.pc_RNI4MT6S[9]\ : MX2 - port map(A => \fpc[9]\, B => \eaddress[9]\, S => jump_0, Y - => N_4052); - - un6_fe_npc_I_41 : AND2 - port map(A => \fe_pc[8]\, B => \fe_pc[9]\, Y => - \DWACT_FINC_E[3]\); - - \r.x.dci.SIGNED_RNIETQQB1\ : NOR2B - port map(A => me_signed_1, B => data_0_0_15, Y => - \rdata_13[8]\); - - \r.e.jmpl_RNIKTFSN\ : OR2B - port map(A => \shiftin_17[12]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I268_Y_0\ : XNOR2 - port map(A => N608_i, B => ADD_30x30_fast_I268_Y_0_0, Y => - \tmp[10]\); - - \r.m.ctrl.pc[20]\ : DFN1E0 - port map(D => \pc_0[20]\, CLK => lclk_c, E => holdn, Q => - \pc_3[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I170_Y\ : OR2 - port map(A => N536, B => I170_un1_Y, Y => N596); - - \r.d.pc_RNO[12]\ : MX2 - port map(A => \fpc[12]\, B => \dpc[12]\, S => N_6763_i_0, Y - => \pc_RNO[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I28_P0N\ : NOR2 - port map(A => \inst_0_1[30]\, B => \dpc[30]\, Y => N443_2); - - \r.m.y[23]\ : DFN1E0 - port map(D => \y_1[23]\, CLK => lclk_c, E => holdn, Q => - \y[23]\); - - \r.m.ctrl.pc[14]\ : DFN1E0 - port map(D => \pc_1[14]\, CLK => lclk_c, E => holdn, Q => - \pc_2[14]\); - - \r.e.op1_RNI3P2M7[4]\ : AO1C - port map(A => \bpdata[4]\, B => N_3687, C => - \edata2_0_iv_0[4]\, Y => edata2_0_iv(4)); - - \r.m.y[0]\ : DFN1E0 - port map(D => \y_1[0]\, CLK => lclk_c, E => holdn, Q => - \y_0[0]\); - - \r.e.op2_RNO_7[26]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[378]\, - Y => \cpi_m_i[378]\); - - \r.e.ctrl.annul_RNIAMD1G\ : OR3C - port map(A => jump_0, B => ex_bpmiss_1_0, C => - \ra_bpmiss_1_0\, Y => un12_de_hold_pc); - - \r.a.ctrl.inst_RNIFG1L[25]\ : NOR3B - port map(A => \inst_1[25]\, B => \inst_2[20]\, C => - \inst_1[24]\, Y => \cpi_m_1[133]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I29_G0N : NOR2A - port map(A => \un1_iu0_6[28]\, B => \data_0[28]\, Y => N481); - - \r.x.ctrl.rd[2]\ : DFN1E0 - port map(D => \rd_0[2]\, CLK => lclk_c, E => holdn, Q => - \rd_3[2]\); - - \r.w.s.y_RNO[8]\ : MX2 - port map(A => \y_2[8]\, B => \result[8]\, S => N_481_0, Y - => N_3772); - - un9_ra_I_1 : AND2 - port map(A => \cwp_0[0]\, B => \inst_0[29]\, Y => - \DWACT_ADD_CI_0_TMP_2[0]\); - - \r.e.ldbp2_2_RNI5355F\ : OR2 - port map(A => aluresult_0_sqmuxa, B => \eaddress[6]\, Y => - ldbp2_2_RNI5355F); - - \r.x.laddr[0]\ : DFN1E0 - port map(D => \maddress[0]\, CLK => lclk_c, E => holdn, Q - => \laddr[0]\); - - \r.d.pc_RNI0UGB4[18]\ : MX2 - port map(A => \dpc[18]\, B => \fpc[18]\, S => - \ra_bpmiss_1_0\, Y => N_3895); - - \r.e.aluop_0_RNI91C3J[0]\ : AND2 - port map(A => \aluresult_1_iv_6[6]\, B => \bpdata_m[6]\, Y - => \aluresult_1_iv_7[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I265_un1_Y_0 : NOR2B - port map(A => N637_1, B => N653_0, Y => - ADD_33x33_fast_I265_un1_Y_0_1); - - \r.m.y_RNIONRFG[20]\ : NOR3C - port map(A => \aluresult_1_iv_4[20]\, B => - \aluresult_1_iv_3[20]\, C => \bpdata_m_1[4]\, Y => - \aluresult_1_iv_6[20]\); - - \r.e.ctrl.pv\ : DFN1E0 - port map(D => pv_4, CLK => lclk_c, E => holdn, Q => pv_5); - - \r.w.s.y[24]\ : DFN1E0 - port map(D => N_6686, CLK => lclk_c, E => holdn, Q => - \y_0[24]\); - - \r.a.ctrl.inst_RNIS96K2[21]\ : OA1A - port map(A => inst_11_1, B => inst_9_3, C => inst_22, Y => - illegal_inst34_1); - - \r.f.pc_RNO_6[27]\ : MX2 - port map(A => \fpc[27]\, B => \eaddress[27]\, S => jump, Y - => N_4070); - - \r.a.rsel2_0_RNIMTBM2[0]\ : OR2B - port map(A => data2(1), B => d25_0, Y => \rfo_m_i[33]\); - - \r.e.aluop_0_RNICHJD1[1]\ : XOR3 - port map(A => \un1_iu0_6[18]\, B => \aluop_0[1]\, C => - \un1_iu0_5[84]\, Y => N_6895); - - \r.e.ldbp2_2_RNI35VBO\ : OR2A - port map(A => \eaddress[9]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[10]\); - - \r.x.result_RNI2GAB3[7]\ : MX2 - port map(A => \un1_iu0_6[7]\, B => \un1_p0_6[359]\, S => - bpdata6_0_0, Y => \bpdata[7]\); - - \r.a.ctrl.rd_RNIAC1L[1]\ : XNOR2 - port map(A => \rd_2[1]\, B => \un3_de_ren1[92]\, Y => - un2_rs1_1_i); - - \r.m.y[20]\ : DFN1E0 - port map(D => \y_1[20]\, CLK => lclk_c, E => holdn, Q => - \y_0[20]\); - - \r.e.shcnt_RNIFEVV3[3]\ : MX2 - port map(A => \shiftin_8[11]\, B => \shiftin_8[3]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[3]\); - - \r.e.aluop_0[0]\ : DFN1E0 - port map(D => \aluop[0]\, CLK => lclk_c, E => holdn, Q => - \aluop_0[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I305_Y_0 : XOR2 - port map(A => N799, B => \un6_ex_add_res_s2_1[15]\, Y => - \un6_ex_add_res_s2[15]\); - - \r.m.y_RNO_0[27]\ : AOI1B - port map(A => wy_1_0, B => \y[27]\, C => N_422, Y => - \y_iv_0_1[27]\); - - \r.e.alucin_RNO_5\ : MX2C - port map(A => \icc_0[0]\, B => \icco[0]\, S => wicc_2, Y - => N_220); - - un6_ex_add_res_d1_ADD_33x33_fast_I268_un1_Y_0 : NOR3C - port map(A => N593_0, B => N601, C => N643_0, Y => - ADD_33x33_fast_I268_un1_Y_0_1); - - \r.m.y_RNO_1[1]\ : AOI1B - port map(A => \y[1]\, B => y08_0, C => N_381, Y => - \y_iv_0_0[1]\); - - \r.e.op1_RNITACR1[24]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[24]\, Y => - \ex_op1_i_m[24]\); - - \r.x.ctrl.inst[25]\ : DFN1E0 - port map(D => \inst_3[25]\, CLK => lclk_c, E => holdn, Q - => \inst[25]\); - - \r.e.op2_RNO_5[27]\ : AOI1B - port map(A => \result[27]\, B => d31_0, C => \imm_m_i[27]\, - Y => \d_1_iv_0[27]\); - - \r.e.ctrl.pv_RNIKLVC\ : NOR2 - port map(A => pv_5, B => pv_1, Y => \npc_cnst_m_0[1]\); - - \r.x.ctrl.pc_RNIJJ431[6]\ : MX2C - port map(A => \un1_p0_6[358]\, B => \pc_1[6]\, S => - s_3_sqmuxa_0, Y => N_3397); - - \r.w.result_RNIA4P1[23]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[23]\, - Y => \result_m_0_0[23]\); - - \r.e.ldbp2_0_RNIKEHUF\ : OR2 - port map(A => aluresult_0_sqmuxa_0, B => \eaddress[7]\, Y - => ldbp2_0_RNIKEHUF); - - \r.a.ctrl.rd_RNIEQ7Q[3]\ : XNOR2 - port map(A => \inst_0_RNI3RUM[3]\, B => \rd_1[3]\, Y => - un1_de_ren1_3_i); - - aluresult_11_sqmuxa_5_RNO : OR2A - port map(A => \inst[19]\, B => aluresult_9_sqmuxa_1, Y => - aluresult_11_sqmuxa_5_0); - - \r.x.ctrl.inst_RNIFU0L[23]\ : NOR3B - port map(A => \inst_0[21]\, B => \inst[23]\, C => - \inst[20]\, Y => cwp_2_sqmuxa_2); - - \r.x.data_0_RNI96HK[31]\ : NOR2A - port map(A => \data_0_0[31]\, B => ex_sari_1_1_0, Y => - ex_sari_1); - - \r.f.pc_RNO_7[20]\ : MX2 - port map(A => \fpc[20]\, B => \tba[8]\, S => - rstate_6314_d_0, Y => \xc_trap_address[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I19_P0N\ : OR2 - port map(A => \inst_0[19]\, B => \dpc[21]\, Y => N416_2); - - \r.x.ctrl.pc[18]\ : DFN1E0 - port map(D => \pc_3[18]\, CLK => lclk_c, E => holdn, Q => - \pc_2[18]\); - - \r.e.shleft_1\ : DFN1E0 - port map(D => N_208, CLK => lclk_c, E => holdn, Q => - shleft_1); - - \r.e.ctrl.rd[6]\ : DFN1E0 - port map(D => \rd[6]\, CLK => lclk_c, E => holdn, Q => - \rd_0[6]\); - - \r.m.dci.lock_RNO\ : AOI1 - port map(A => N_3749, B => N_3748, C => N_3356_3, Y => - lock_1); - - \r.m.ctrl.trap_RNICM9T2\ : OR2A - port map(A => trap_2_0, B => annul_RNIPFOQ, Y => annul_3); - - \r.f.pc_RNO_0[8]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[8]\, C => - \pc_1_iv_0[8]\, Y => \pc_1_iv_1[8]\); - - \r.x.result_RNISNKA[6]\ : MX2 - port map(A => \result_0[6]\, B => \data_0[6]\, S => ld_0, Y - => \un1_p0_6[358]\); - - \r.w.s.tt_RNIHVP81[7]\ : OR2B - port map(A => \tt[7]\, B => aluresult_12_sqmuxa, Y => - \tt_m[7]\); - - \r.e.op1_RNI15UH[21]\ : MX2 - port map(A => \op1[21]\, B => \data_0[21]\, S => ldbp1_2, Y - => \un1_iu0_6[21]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_3\ : AND2A - port map(A => irl_0(1), B => \pil[1]\, Y => \ACT_LT4_E[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I121_un1_Y : OA1A - port map(A => N_53_i, B => N442_1, C => N519_2, Y => - I121_un1_Y); - - \r.a.rsel1_0_RNIF3LJ2[2]\ : OR2B - port map(A => data1(18), B => d11, Y => \rfo_m[18]\); - - \r.x.laddr_RNIH68NE1[0]\ : OR3A - port map(A => rdata_3_sqmuxa_2, B => \me_laddr_2[1]\, C => - \me_laddr_2[0]\, Y => rdata_0_sqmuxa); - - \r.d.inst_0_RNO_0[14]\ : MX2 - port map(A => data_0_0_14, B => \inst_0[14]\, S => - mexc_1_sqmuxa_1_0, Y => N_4614); - - \r.f.pc_RNO_3[16]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[16]\, C => - \xc_trap_address_m[16]\, Y => \pc_1_iv_0[16]\); - - \r.e.op2_RNO_5[6]\ : AOI1B - port map(A => \result[6]\, B => d31, C => \imm_m_i[6]\, Y - => \d_1_iv_0[6]\); - - \r.a.ctrl.pc[25]\ : DFN1E0 - port map(D => \dpc[25]\, CLK => lclk_c, E => holdn, Q => - \pc_0[25]\); - - \r.w.s.wim[0]\ : DFN1E0 - port map(D => \wim_1[0]\, CLK => lclk_c, E => holdn, Q => - \wim[0]\); - - \r.e.aluop_RNIE2SO4[2]\ : OR2B - port map(A => edata_1_sqmuxa, B => \bpdata[14]\, Y => - \bpdata_i_m_0[14]\); - - \r.m.result_RNIAMTD3[30]\ : NOR3C - port map(A => \d_iv_0[30]\, B => \result_m_0[30]\, C => - \rfo_m[30]\, Y => \d_iv_2[30]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I77_Y : MAJ3 - port map(A => \op2[8]\, B => \un1_iu0_6[8]\, C => N418_1, Y - => N536_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I116_Y_0\ : MIN3 - port map(A => \dpc[15]\, B => \inst_0[13]\, C => N394, Y - => ADD_30x30_fast_I116_Y_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I34_Y : NOR2A - port map(A => N488, B => N485_i_0, Y => N493); - - \r.e.op2_RNO_3[9]\ : NOR3C - port map(A => \result_m_i[9]\, B => \imm_m_i[9]\, C => - \d_1_iv_1[9]\, Y => \d_1_iv_2[9]\); - - \r.a.ctrl.inst_RNI9T3V1[31]\ : OR2A - port map(A => illegal_inst12, B => N_201, Y => N_345); - - \r.x.y[3]\ : DFN1E0 - port map(D => \y_1[3]\, CLK => lclk_c, E => holdn, Q => - \y_2[3]\); - - \r.e.op2_RNO_8[22]\ : OR3B - port map(A => d29_0, B => \imm[22]\, C => \rsel2[0]\, Y => - \imm_m_i[22]\); - - \r.e.ldbp2_RNITF9UK\ : OA1A - port map(A => \eaddress[1]\, B => aluresult_0_sqmuxa_0, C - => \aluresult_2_iv_5[1]\, Y => \aluresult_2_iv_6[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I69_Y : AO18 - port map(A => \un1_iu0_6[12]\, B => N430_1, C => - \data_0_2[12]\, Y => N528_2); - - \r.m.ctrl.trap_RNIBN4L1\ : OA1C - port map(A => nullify_0_sqmuxa_0, B => un5_trap, C => - annul_RNIPFOQ, Y => me_nullify2_1_2_0); - - \r.m.ctrl.rett\ : DFN1E0 - port map(D => rett_1_3, CLK => lclk_c, E => holdn, Q => - rett); - - \r.e.aluop_RNI27PHA8[0]\ : MX2A - port map(A => \logicout[23]\, B => \aluresult[31]\, S => - un3_op_i, Y => N_4178); - - un6_ex_add_res_d2_ADD_33x33_fast_I22_P0N : AO1A - port map(A => ldbp1_4, B => \op1[21]\, C => \data_0[21]\, Y - => N461_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I249_Y : OR2A - port map(A => I249_un1_Y_i, B => N668, Y => N814); - - \r.m.y_RNO_3[24]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[24]\, C => N_372, Y => - \y_iv_0_1[24]\); - - \r.e.aluop_RNIKVO31[2]\ : NOR3 - port map(A => logicout22_1, B => \aluop_1[2]\, C => - aluresult_9_sqmuxa_1, Y => aluresult_5_sqmuxa); - - \r.m.y_RNO_2[19]\ : OR2A - port map(A => \logicout[19]\, B => y14, Y => - \logicout_m[19]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I210_un1_Y\ : OAI1 - port map(A => I176_un1_Y, B => N542, C => N587, Y => - I210_un1_Y); - - \r.e.aluop_0_RNIM51E[2]\ : OR2 - port map(A => \aluop_0[2]\, B => aluresult_9_sqmuxa_1, Y - => aluresult_7_sqmuxa_0); - - \r.e.shleft\ : DFN1E0 - port map(D => N_208, CLK => lclk_c, E => holdn, Q => shleft); - - \r.d.inst_0_RNIN0IBM[13]\ : AO1B - port map(A => un1_de_ren1_NE_i_0, B => ldcheck2, C => - un1_ldcheck1, Y => un1_ldcheck1_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_un1_Y : OR2B - port map(A => ADD_33x33_fast_I261_un1_Y_0_0, B => N802_1, Y - => I261_un1_Y_1); - - \r.e.op1_RNI1RCR1[19]\ : NOR2A - port map(A => edata_3_sqmuxa_0, B => \op1_RNID1VH[19]\, Y - => \ex_op1_i_m[19]\); - - \r.m.dci.write\ : DFN1E0 - port map(D => write, CLK => lclk_c, E => holdn, Q => - write_0); - - \r.m.ctrl.pc[13]\ : DFN1E0 - port map(D => \pc_2[13]\, CLK => lclk_c, E => holdn, Q => - \pc_3[13]\); - - \r.e.shleft_RNI5ARJ\ : OR2A - port map(A => \un1_iu0_6[13]\, B => shleft, Y => - \shiftin_5[13]\); - - \r.a.ctrl.wy_RNO_2\ : NOR3 - port map(A => N_122_2, B => \inst_0[25]\, C => N_89, Y => - wy_1_0_a3_0_7_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I312_Y_0 : AX1C - port map(A => I269_un1_Y_0, B => ADD_33x33_fast_I269_Y_0_1, - C => ADD_33x33_fast_I312_Y_0_0, Y => - \un6_ex_add_res_s1_i[22]\); - - \r.f.pc_RNI8CM4[6]\ : NOR2A - port map(A => \fpc[6]\, B => rst, Y => \pc_RNI8CM4[6]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I143_Y : AO1 - port map(A => N544_2, B => N541, C => N540_1, Y => N606_2); - - \r.e.op1_RNIF0O9F[29]\ : NOR3B - port map(A => \bpdata_i_m_0[13]\, B => \edata2_iv_1[29]\, C - => \bpdata_i_m_2[5]\, Y => edata2_iv_i_0(29)); - - \r.e.cwp_RNIHTJ61[2]\ : OR2A - port map(A => \cwp_2[2]\, B => aluresult_11_sqmuxa, Y => - \cwp_m[2]\); - - \r.m.icc_RNO_9[2]\ : NOR2 - port map(A => \logicout[4]\, B => \logicout[0]\, Y => - icc_0_sqmuxa_1_13); - - un6_ex_add_res_d2_ADD_33x33_fast_I310_Y_0 : AX1E - port map(A => I271_un1_Y_i_0, B => ADD_33x33_fast_I271_Y_0, - C => \un6_ex_add_res_s2_1[20]\, Y => - \un6_ex_add_res_s2[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I302_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[12]\, B => N808, Y => - \un6_ex_add_res_s2[12]\); - - \r.e.op1_RNI2B0N1[29]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[29]\, Y => - \ex_op1_i_m[29]\); - - \r.d.pv_RNO_5\ : OR3B - port map(A => pv, B => N_4239, C => ex_bpmiss_1_0, Y => - N_4240); - - \r.a.ctrl.pv_RNI6GFJ\ : OA1C - port map(A => pv_4, B => pv_5, C => pv_1, Y => - \npc_cnst_m_0[0]\); - - \r.m.y_RNI8BD92[16]\ : AOI1B - port map(A => \y[16]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[161]\, Y => \aluresult_1_iv_1[16]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I65_Y : MIN3 - port map(A => \data_0[14]\, B => \un1_iu0_6[14]\, C => - N436_2, Y => N524_1); - - \r.m.y_RNO_1[31]\ : OR3A - port map(A => \y_1[31]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[31]\); - - \r.e.jmpl_RNIATCQK2\ : NOR3C - port map(A => \shiftin_17_m[26]\, B => - \aluresult_1_iv_7[25]\, C => \shiftin_17_m_0[25]\, Y => - \aluresult_1_iv_9[25]\); - - \r.e.op2_RNO_3[11]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[11]\, Y - => \aluresult_m_i[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I135_Y\ : NOR3C - port map(A => N362, B => N365, C => N496_2, Y => N555); - - \r.e.aluop_RNII95R8[2]\ : OA1C - port map(A => edata_1_sqmuxa, B => \bpdata[10]\, C => - \bpdata_i_m_2[2]\, Y => \edata2_iv_2[26]\); - - \r.w.s.y_RNO[5]\ : MX2 - port map(A => \y_1[5]\, B => \result_0[5]\, S => N_481_0, Y - => N_3769); - - \r.w.result_RNIOFD4[19]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[19]\, - Y => \result_m_0_0[19]\); - - \r.m.ctrl.inst[30]\ : DFN1E0 - port map(D => \inst_2[30]\, CLK => lclk_c, E => holdn, Q - => \inst_1[30]\); - - \r.m.y[13]\ : DFN1E0 - port map(D => \y_1[13]\, CLK => lclk_c, E => holdn, Q => - \y[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I314_Y_0 : XNOR2 - port map(A => N780_1, B => ADD_33x33_fast_I314_Y_0_0, Y => - \un6_ex_add_res_s1_i[24]\); - - \r.f.pc_RNIA9TC9[2]\ : MX2 - port map(A => \fpc[2]\, B => ldbp2_1_RNIL7Q55, S => jump_0, - Y => N_4045); - - \comb.branch_address.tmp_ADD_30x30_fast_I137_un1_Y\ : OR3C - port map(A => N362, B => N365, C => N358, Y => I137_un1_Y_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I147_Y : AO1 - port map(A => N548, B => N545_2, C => N544_1, Y => N610_2); - - \r.a.ctrl.pc[11]\ : DFN1E0 - port map(D => \dpc[11]\, CLK => lclk_c, E => holdn, Q => - \pc[11]\); - - \r.w.result_RNI062L[19]\ : AOI1B - port map(A => \un1_p0_6[371]\, B => d14_0, C => - \result_m_0_0[19]\, Y => \d_iv_0[19]\); - - \r.m.y_RNIRDO71[14]\ : OR2B - port map(A => \y_0[14]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[14]\); - - \r.a.rsel2_0_RNIV6QD[0]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[356]\, Y => \cpi_m_i[356]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I173_Y : OR3C - port map(A => I113_un1_Y_i, B => ADD_33x33_fast_I113_Y_0_0, - C => I173_un1_Y_i, Y => N642_1); - - \r.d.pc_RNIQ5HB4[22]\ : MX2 - port map(A => \dpc[22]\, B => \fpc[22]\, S => ra_bpmiss_1, - Y => N_3899); - - un6_ex_add_res_d0_ADD_33x33_fast_I171_Y : OR2A - port map(A => I171_un1_Y_i, B => N574, Y => N640_0); - - \r.w.s.dwt_RNO\ : NOR2A - port map(A => rst, B => N_318, Y => N_170); - - \r.e.op2_RNO[16]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0, S => - \d_1[16]\, Y => N_300); - - \r.a.ctrl.inst_RNIJ42L_0[19]\ : NOR2 - port map(A => \inst_2[19]\, B => N_202, Y => N_226); - - \r.e.ldbp1_2\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_2); - - \r.a.imm_RNO[1]\ : NOR2B - port map(A => \inst_0_RNI1JUM[1]\, B => call_hold5, Y => - \un3_de_ren1[119]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I139_Y : AOI1 - port map(A => N540_1, B => N537_2, C => N536_2, Y => N602_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_o3_1_0 : MIN3 - port map(A => \op2[1]\, B => \un1_iu0_6[1]\, C => N397_0, Y - => ADD_33x33_fast_I206_Y_0_o3_1_0_0); - - \r.m.y_RNO_4[27]\ : OR2B - port map(A => \y[28]\, B => mulstep_1, Y => N_424); - - un6_ex_add_res_d0_ADD_33x33_fast_I294_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[4]\, B => N614_1, Y => - \un6_ex_add_res_s0[4]\); - - \r.e.ctrl.pc_RNIJ4A7J[27]\ : NOR3C - port map(A => \aluop_RNIEPDN4[2]\, B => - \aluresult_0_iv_2[27]\, C => \aluresult_0_iv_5[27]\, Y - => \aluresult_0_iv_6[27]\); - - \r.d.inst_0_0_0_RNIL4JE03[21]\ : MX2 - port map(A => data_0_2_21, B => \un1_p0_6_0[60]\, S => - inull_RNIFV6VG2_0, Y => N_4621); - - \r.a.rfa1_RNID98B1[4]\ : MX2 - port map(A => \un3_de_ren1[95]\, B => \rfa1[4]\, S => holdn, - Y => raddr1(4)); - - \r.x.ctrl.tt_RNI32K6[0]\ : NOR2B - port map(A => \tt[0]\, B => \tt[1]\, Y => tt_0); - - \r.e.ctrl.tt[0]\ : DFN1E0 - port map(D => \tt_1[0]\, CLK => lclk_c, E => holdn, Q => - \tt_2[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I268_un1_Y_0 : NOR2B - port map(A => N659, B => N643_1, Y => - ADD_33x33_fast_I268_un1_Y_0_0); - - \r.f.pc_RNO_1[13]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[13]\, C => - \pc_1_iv_0[13]\, Y => \pc_1_iv_1[13]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_un1_Y : OR2B - port map(A => ADD_33x33_fast_I261_un1_Y_0, B => N802, Y => - I261_un1_Y); - - \r.x.data_0_RNO[7]\ : OR3C - port map(A => \dco_m_i[119]\, B => \data_0_1_1_iv_1[7]\, C - => \dco_m_i[103]\, Y => \data_0_1[7]\); - - \r.m.y[10]\ : DFN1E0 - port map(D => \y_1[10]\, CLK => lclk_c, E => holdn, Q => - \y_0[10]\); - - \r.d.inull_RNIOT29\ : NOR3C - port map(A => annul_next_1_sqmuxa_1_1, B => - annul_next_1_sqmuxa_1_0, C => annul_next_1_sqmuxa_1_2, Y - => annul_next_1_sqmuxa_1_4); - - \r.e.shleft_RNIA62L1\ : MX2A - port map(A => \shiftin_5[30]\, B => \shiftin_5_i[14]\, S - => \ex_shcnt_1_i[4]\, Y => \shiftin_8[14]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I70_Y : NOR2B - port map(A => N434, B => N431_0, Y => N529_0); - - \r.m.ctrl.pc_RNIN6AE[2]\ : MX2 - port map(A => \pc_3[2]\, B => \pc[2]\, S => \npc_0[1]\, Y - => N_3243); - - \r.x.result_RNIE4OE[21]\ : OR2B - port map(A => \un1_p0_6[373]\, B => d14, Y => - \cpi_m_0[373]\); - - \r.f.pc[23]\ : DFN1E0 - port map(D => \pc_1[23]\, CLK => lclk_c, E => holdn, Q => - \fpc[23]\); - - \r.x.result_RNILIDE5[12]\ : NOR2B - port map(A => \bpdata[12]\, B => \aluop_RNIGM3N1[2]\, Y => - \bpdata_i_m[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I70_Y\ : MAJ3 - port map(A => \dpc[10]\, B => \inst_0[8]\, C => N379, Y => - N487_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I200_Y : NOR2A - port map(A => N611_0, B => N603_0, Y => N669_0); - - \r.e.aluop_0_RNIRSOT[2]\ : NOR2 - port map(A => aluresult_7_sqmuxa_0, B => logicout21_1, Y - => aluresult_7_sqmuxa); - - \r.d.annul_RNIVCQHS1\ : NOR2 - port map(A => un2_rstn_4_0, B => un2_rstn_5_2, Y => - annul_RNIVCQHS1); - - \r.x.result_RNIJTR65[6]\ : OR2B - port map(A => \bpdata[6]\, B => N_3957_1, Y => - \bpdata_m_1[6]\); - - \r.e.aluop_RNI83T5C[2]\ : OA1A - port map(A => aluresult_5_sqmuxa, B => \bpdata[13]\, C => - \aluresult_1_iv_2[29]\, Y => \aluresult_1_iv_4[29]\); - - \r.a.ctrl.inst_RNIB41E_0[23]\ : NOR2A - port map(A => \inst_1[24]\, B => \inst_1[23]\, Y => - aluop_2_1_0_a2_0); - - \r.x.ctrl.wicc_RNISFUM2_0\ : NOR2B - port map(A => icc_2_sqmuxa_2, B => cwp_1_sqmuxa, Y => - icc_2_sqmuxa); - - \r.x.ctrl.tt_RNO_0[5]\ : OR2B - port map(A => tt_0_sqmuxa, B => \tt_1[5]\, Y => N_4209); - - \comb.branch_address.tmp_ADD_30x30_fast_I12_G0N\ : NOR2B - port map(A => \inst_0[12]\, B => \dpc[14]\, Y => N394); - - \r.a.ctrl.inst_RNIICJA[28]\ : XNOR2 - port map(A => \inst_1[28]\, B => N_211, Y => branch_4); - - \r.x.result_RNI5M1O3[20]\ : MX2 - port map(A => \un1_iu0_6[20]\, B => \un1_p0_6[372]\, S => - bpdata6, Y => \bpdata[20]\); - - \r.m.ctrl.pc_RNIC9N9[16]\ : MX2 - port map(A => \pc_3[16]\, B => \pc_0[16]\, S => \npc[1]\, Y - => N_3257); - - \r.e.op2_RNO[27]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[27]\, Y => N_311); - - \r.d.annul_RNIRK1K4\ : NOR3A - port map(A => un6_rabpmiss_0, B => annul_1, C => - \ra_bpmiss_1_0\, Y => un6_rabpmiss_2); - - \r.w.s.wim_RNILSJV2[6]\ : NOR2B - port map(A => aluresult_8_sqmuxa_i, B => \wim_m[6]\, Y => - \aluresult_1_iv_0[6]\); - - \r.e.jmpl_RNI1EKJ51\ : AOI1B - port map(A => \shiftin_17[0]\, B => aluresult_2_sqmuxa_0, C - => \aluresult_2_iv_6[0]\, Y => \aluresult_2_iv_7[0]\); - - \r.m.ctrl.pc_RNIS1HF[13]\ : MX2 - port map(A => \pc_3[13]\, B => \pc[13]\, S => \npc_1[1]\, Y - => N_3254); - - \r.e.shleft_1_RNIQCHP\ : OR2A - port map(A => \un1_iu0_6[20]\, B => shleft_1, Y => - \shiftin_5[20]\); - - \r.w.s.y[2]\ : DFN1E0 - port map(D => N_3766, CLK => lclk_c, E => N_6922_i, Q => - \y[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.e.shleft_1_RNI5GVF3\ : MX2 - port map(A => \shiftin_5[52]\, B => \shiftin_5[36]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[36]\); - - \r.e.ctrl.inst_RNIJ0JA[25]\ : MX2 - port map(A => \icc[3]\, B => \icc[1]\, S => \inst_2[25]\, Y - => \inst_RNIJ0JA[25]\); - - \r.m.y_RNO_3[18]\ : AOI1B - port map(A => wy_1_0, B => \y[18]\, C => N_395, Y => - \y_iv_0_1[18]\); - - \r.m.dci.write_RNO_0\ : AXO5 - port map(A => write_3_0_a3_0_2_0, B => \cnt[0]\, C => - \cnt[1]\, Y => write_3_tz); - - \r.e.op2_RNO_7[15]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[367]\, Y => \cpi_m_i[367]\); - - \r.a.rsel1_0_RNI93LJ2[2]\ : OR2B - port map(A => data1(12), B => d11, Y => \rfo_m[12]\); - - \r.f.pc_RNO_7[26]\ : MX2 - port map(A => \fpc[26]\, B => \tba[14]\, S => rstate_6314_d, - Y => \xc_trap_address[26]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I144_Y : NOR2B - port map(A => N545_2, B => N541_1, Y => N607_0); - - \r.x.ctrl.tt_RNO_0[3]\ : OA1C - port map(A => iflush_4, B => trap_0_sqmuxa_2, C => - un1_trap_0_sqmuxa_5, Y => N_4201_i_0); - - \r.a.rfa2[3]\ : DFN1E0 - port map(D => \inst_0_RNI3RUM[3]\, CLK => lclk_c, E => - holdn, Q => \rfa2[3]\); - - \r.e.ldbp2_0_RNIM5MI31\ : MX2C - port map(A => \un6_ex_add_res_s1_i[13]\, B => N_6632, S => - ldbp2_0, Y => \eaddress[12]\); - - \r.e.jmpl_RNI30TCJ5\ : OR3C - port map(A => \aluresult_1_iv_8[20]\, B => - \shiftin_17_m_0[20]\, C => \un6_ex_add_res_m[21]\, Y => - \aluresult[20]\); - - \r.x.ctrl.rd_RNINVH6[6]\ : XNOR2 - port map(A => \rd_2[6]\, B => \rd_0[6]\, Y => rd_6_i_0); - - \r.e.op2_RNO_0[12]\ : OR3C - port map(A => \op1_m_i[12]\, B => \d_1_iv_3[12]\, C => - \aluresult_m_i[12]\, Y => \d_1[12]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I314_Y_0 : XOR2 - port map(A => N780_0, B => \un6_ex_add_res_s2_1[24]\, Y => - \un6_ex_add_res_s2[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I21_P0N\ : OR2 - port map(A => \un1_p0_6_0[60]\, B => \dpc[23]\, Y => N422); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_Y_1 : AO1 - port map(A => N650_0, B => N635_0, C => - ADD_33x33_fast_I264_Y_0_0, Y => ADD_33x33_fast_I264_Y_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I34_Y : NOR2A - port map(A => N488_0, B => N485_i, Y => N493_0); - - \r.w.s.ps_RNIHGNV8\ : NOR3 - port map(A => ps_i_m, B => s_i_m, C => \result_i_m[7]\, Y - => s_1_iv); - - \comb.ld_align.rdata199_RNINGRP32\ : NOR3B - port map(A => ld_0_0, B => \rdata_9_m_0[8]\, C => - rdata_1_sqmuxa_1, Y => \rdata_9_m[8]\); - - \r.e.op2[19]\ : DFN1E0 - port map(D => N_303, CLK => lclk_c, E => holdn, Q => - \op2[19]\); - - \r.m.ctrl.rd_RNILISE3[0]\ : NOR3C - port map(A => wreg_0_0, B => un1_de_ren1_1_3_i_0, C => - wreg_1_7, Y => wreg_3); - - \r.x.npc_0[0]\ : DFN1E0 - port map(D => \npc_1[0]\, CLK => lclk_c, E => holdn, Q => - \npc_0[0]\); - - \r.a.ctrl.inst_RNICO0S[31]\ : AO1C - port map(A => \inst[30]\, B => N_58, C => \inst[31]\, Y => - invop2_0_1_i_0); - - \r.m.ctrl.ld_RNI4LM47\ : OA1C - port map(A => N_227_0, B => \y_1[0]\, C => ldbp2_0_a5_0, Y - => ldbp2); - - \r.m.y_RNIF4K91[9]\ : OR2B - port map(A => \y_1[9]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[9]\); - - \r.e.ctrl.tt_RNO_0[5]\ : OR3A - port map(A => \tt_9_0_a3_0_1[5]\, B => fp_disabled_4, C => - N_4033_i, Y => N_4043_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I174_Y : NOR2B - port map(A => N585_0, B => N577_0, Y => N643_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I40_Y_i_o3 : OR2B - port map(A => N479_1, B => N476_1, Y => N_50_0); - - \r.m.y_RNO_1[25]\ : OR2B - port map(A => \y_1[26]\, B => mulstep_0, Y => \y_m_2[26]\); - - \r.e.op2_RNI0OG11[20]\ : OR2A - port map(A => \un1_iu0_5[86]\, B => \un1_iu0_6[20]\, Y => - \logicout_4[20]\); - - \r.m.result[31]\ : DFN1E0 - port map(D => \eres2[31]\, CLK => lclk_c, E => holdn, Q => - \maddress[31]\); - - \r.a.ctrl.inst_RNID81L[20]\ : OR2 - port map(A => \inst_2[20]\, B => N_216, Y => N_434); - - \comb.branch_address.tmp_ADD_30x30_fast_I286_Y_0\ : XOR2 - port map(A => N700, B => ADD_30x30_fast_I286_Y_0_0, Y => - \tmp[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I107_Y : OR2A - port map(A => I107_un1_Y_i, B => N504_1, Y => N570_1); - - \r.e.ctrl.pc[8]\ : DFN1E0 - port map(D => \pc[8]\, CLK => lclk_c, E => holdn, Q => - \pc_2[8]\); - - \r.e.op2_RNO_4[27]\ : OA1A - port map(A => \maddress[27]\, B => d27_0, C => - \cpi_m_i[379]\, Y => \d_1_iv_1[27]\); - - \r.e.op1[1]\ : DFN1E0 - port map(D => \aop1[1]\, CLK => lclk_c, E => holdn, Q => - \op1[1]\); - - \r.d.pc_RNO[17]\ : MX2 - port map(A => \fpc[17]\, B => \dpc[17]\, S => N_6763_i_0, Y - => \pc_RNO[17]\); - - \r.e.op1_RNI456I1[6]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[6]\, Y => - \ex_op1_i_m[6]\); - - \r.m.result_RNIBND4[30]\ : OR2B - port map(A => d13_0, B => \maddress[30]\, Y => - \result_m_0[30]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I137_Y : AO1B - port map(A => N538_0, B => N535_1, C => - ADD_33x33_fast_I137_Y_0_1, Y => N600_0); - - un23_ra_I_14 : XOR2 - port map(A => \cwp_0[2]\, B => - \DWACT_ADD_CI_0_g_array_1_1[0]\, Y => I_14_1); - - \r.e.op1_RNIOQ8G[22]\ : OR2B - port map(A => \op1[22]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[22]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I104_Y : NOR3C - port map(A => N473_1, B => N476_1, C => N505_1, Y => N567); - - \r.e.op2[9]\ : DFN1E0 - port map(D => N_293, CLK => lclk_c, E => holdn, Q => - \op2[9]\); - - \r.a.imm[24]\ : DFN1E0 - port map(D => \un3_de_ren1[142]\, CLK => lclk_c, E => holdn, - Q => \imm[24]\); - - \r.m.ctrl.pc[11]\ : DFN1E0 - port map(D => \pc_2[11]\, CLK => lclk_c, E => holdn, Q => - \pc_1[11]\); - - \r.f.pc_RNI17ATA5[10]\ : NOR2B - port map(A => \un6_fe_npc_m[8]\, B => - \xc_trap_address_m[10]\, Y => \npc_iv_2[10]\); - - \r.m.icc[0]\ : DFN1E0 - port map(D => \icco[0]\, CLK => lclk_c, E => holdn, Q => - \icc_0[0]\); - - \r.e.ctrl.inst_RNI312S[22]\ : NOR3A - port map(A => \inst[19]\, B => \inst_1[22]\, C => - aluresult_11_sqmuxa_4, Y => un3_op_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I302_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[12]\, B => N808_1, Y => - \un6_ex_add_res_s0[12]\); - - \r.a.rsel1[2]\ : DFN1E0 - port map(D => rs1, CLK => lclk_c, E => holdn, Q => - \rsel1[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I40_Y_i_o3 : OAI1 - port map(A => \data_0[27]\, B => \un1_iu0_6[27]\, C => - N476_2, Y => N_50_1); - - \r.e.op1_RNIH494A7[26]\ : NOR3C - port map(A => \op1_m_0[26]\, B => \d_iv_2[26]\, C => - \aluresult_m_0[26]\, Y => \d_i[26]\); - - \comb.cwp_ctrl.ncwp_3_I_15\ : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0[0]\, B => - \cwp_0[0]\, C => \DWACT_ADD_CI_0_g_array_0_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_3[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I131_Y\ : NOR2B - port map(A => N496_2, B => N492, Y => N551); - - \r.x.npc_0_RNIADT61[0]\ : MX2C - port map(A => N_3226, B => N_3256, S => \npc_0[0]\, Y => - \xc_result[15]\); - - \r.e.op1_RNIJO8M02[1]\ : OR3C - port map(A => \op1_m_0[1]\, B => \d_iv_2[1]\, C => - \aluresult_m_0[1]\, Y => \d[1]\); - - \r.e.aluop_0_RNI4LVG[2]\ : XA1 - port map(A => \op2_RNI59C6[0]\, B => \aluop_0[2]\, C => - \un1_iu0_6[0]\, Y => N_3527); - - \r.m.y_RNO_2[16]\ : OR2A - port map(A => \logicout[16]\, B => y14, Y => - \logicout_m[16]\); - - \r.f.pc_RNO_4[14]\ : MX2 - port map(A => I_73, B => N_4057, S => bpmiss_1_i_0, Y => - \pc_4[14]\); - - \r.d.cnt_RNI338J[0]\ : OR3A - port map(A => un13_op3, B => call_hold7_i, C => un52_casaen, - Y => hold_pc_2_sqmuxa); - - \r.x.result_RNIL3RV[0]\ : NOR2B - port map(A => \un1_p0_6[352]\, B => N_6357, Y => \wdata[0]\); - - \r.x.ctrl.inst_RNIF32S[19]\ : NOR3B - port map(A => \inst[20]\, B => wim_1_sqmuxa_0, C => - \inst_1[19]\, Y => wim_1_sqmuxa_1); - - \r.e.ldbp2_RNI6L12M4\ : OR2A - port map(A => \eaddress[28]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[29]\); - - \r.d.inst_0_RNI5C23[31]\ : OR2B - port map(A => \inst_0[31]\, B => \inst_0[30]\, Y => - call_hold7_i); - - \r.w.s.y_RNO_2[24]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[24]\, Y - => N_369); - - \r.m.icc_RNIA6A3[1]\ : XNOR2 - port map(A => \inst_0[28]\, B => \icc[1]\, Y => branch_8_i); - - \r.a.ctrl.inst[5]\ : DFN1E0 - port map(D => \inst_0[5]\, CLK => lclk_c, E => holdn, Q => - \inst[5]\); - - \r.d.annul_RNI8MUI42\ : OR3A - port map(A => \tmp[9]\, B => un2_rstn_5_2, C => - \un2_rstn_5_0_0\, Y => \tmp_m[9]\); - - \r.x.result_RNIFL0C3[3]\ : MX2 - port map(A => \un1_iu0_6[3]\, B => \un1_p0_6[355]\, S => - bpdata6, Y => \bpdata[3]\); - - \r.e.op2_RNO_7[7]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[359]\, Y => \cpi_m_i[359]\); - - \r.d.inst_0_RNO[10]\ : NOR2B - port map(A => rst, B => N_4610, Y => \inst_0_RNO[10]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I181_un1_Y : OR2B - port map(A => N592_1, B => N585_1, Y => I181_un1_Y_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I33_un1_Y : OR3B - port map(A => \un1_iu0_6[29]\, B => N488_2, C => - \data_0_0[29]\, Y => I33_un1_Y_1); - - \r.e.invop2_RNI18F2G2\ : MX2C - port map(A => \un6_ex_add_res_s2[26]\, B => - \un6_ex_add_res_s0[26]\, S => invop2, Y => N_6657); - - \r.d.inst_0_RNIAO79[23]\ : NOR3 - port map(A => \inst_0[30]\, B => \inst_0_0[23]\, C => - \un1_p0_6_0[60]\, Y => ldcheck1_5_i_a6_1_1); - - \comb.un6_xc_exception_RNI2Q3D\ : NAND2 - port map(A => un6_xc_exception, B => - \xc_trap_address_m_0[3]\, Y => \xc_trap_address_m[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I19_G0N : OA1 - port map(A => \op1[18]\, B => ldbp1_3, C => \data_0_0[18]\, - Y => N451_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I15_G0N : NOR3A - port map(A => \op1[14]\, B => ldbp1_0, C => \data_0[14]\, Y - => N439_0); - - \r.x.result_RNIHHR65[5]\ : OR2B - port map(A => \bpdata[5]\, B => N_3957_1, Y => - \bpdata_m_1[5]\); - - \r.m.result_RNIJ85P[4]\ : NOR3C - port map(A => \result_m_0[4]\, B => \cpi_m_0[356]\, C => - \result_m_0_0[4]\, Y => \d_iv_1[4]\); - - \r.e.shcnt_RNI7AMS6[3]\ : MX2 - port map(A => \shiftin_8[36]\, B => \shiftin_8[28]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[28]\); - - \r.a.rfa1[6]\ : DFN1E0 - port map(D => \un3_de_ren1[97]\, CLK => lclk_c, E => holdn, - Q => \rfa1[6]\); - - \r.d.inst_0_RNIANSA[17]\ : OR2B - port map(A => I_14_1, B => un26_rs1opt, Y => - \de_raddr1_2[6]\); - - \r.e.op1[6]\ : DFN1E0 - port map(D => \aop1[6]\, CLK => lclk_c, E => holdn, Q => - \op1[6]\); - - \r.a.ctrl.inst_RNIGS1E[19]\ : NOR2A - port map(A => \inst_1[24]\, B => \inst_2[19]\, Y => - illegal_inst37_2); - - \r.m.y_RNI08OJF[16]\ : NOR3C - port map(A => \aluresult_1_iv_3[16]\, B => - \aluresult_1_iv_2[16]\, C => \bpdata_m_1[0]\, Y => - \aluresult_1_iv_5[16]\); - - \r.m.y_RNO_0[12]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[12]\, C => \y_m_0[12]\, - Y => \y_iv_1[12]\); - - \r.e.op2_RNO_8[5]\ : OR3B - port map(A => d29_0_0, B => \imm[5]\, C => \rsel2_0[0]\, Y - => \imm_m_i[5]\); - - \r.e.aluop_1_RNIQVV83[1]\ : MX2C - port map(A => \logicout_4[21]\, B => N_6904_i, S => - N_6866_i, Y => N_3644); - - \r.x.data_0_RNIHJ9E[27]\ : XOR2 - port map(A => \data_0[27]\, B => invop2_1, Y => N_4274); - - \r.x.data_0_RNIFF9E[19]\ : XOR2 - port map(A => \data_0[19]\, B => invop2_0, Y => N_4266); - - \r.x.rstate_RNI5S7L[1]\ : OR2 - port map(A => annul_1_0, B => \rstate_d[2]\, Y => - rstate_7_0); - - \r.e.ctrl.rd_RNI85J65[1]\ : NOR3C - port map(A => wreg_1_2, B => wreg_1_1, C => - \rd_RNIQP6H1[7]\, Y => wreg_1_4); - - \r.m.ctrl.tt[3]\ : DFN1E0 - port map(D => \tt_5[3]\, CLK => lclk_c, E => holdn, Q => - \tt_2[3]\); - - \r.e.op1[25]\ : DFN1E0 - port map(D => \aop1[25]\, CLK => lclk_c, E => holdn, Q => - \op1[25]\); - - \r.w.s.tba_RNIKCQJF[3]\ : NOR3C - port map(A => \aluresult_1_iv_2[15]\, B => \tba_m[3]\, C - => \aluresult_1_iv_4[15]\, Y => \aluresult_1_iv_5[15]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I295_Y_0 : AX1D - port map(A => N406_1, B => ADD_33x33_fast_I206_Y_0_a3_0, C - => \un6_ex_add_res_s2_1[5]\, Y => \un6_ex_add_res_s2[5]\); - - \r.e.op1_RNIU6NF[21]\ : NOR2A - port map(A => un17_casaen_0, B => \op1[21]\, Y => - \op1_i_m[21]\); - - \r.m.y_RNO_0[21]\ : NOR3C - port map(A => \y_m[21]\, B => \y_m_0[21]\, C => - \y_iv_0[21]\, Y => \y_iv_2[21]\); - - \r.w.s.ps_RNIF5EF2\ : NOR2 - port map(A => s_2_sqmuxa, B => ps, Y => ps_i_m); - - \r.x.result_RNIRS6E[31]\ : MX2 - port map(A => \result_0[31]\, B => \data_0_0[31]\, S => - ld_4, Y => \un1_p0_6[383]\); - - \r.e.aluop_RNIGHSC4[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[26]\, Y => - \bpdata_i_m[26]\); - - \r.d.inst_0_RNIA7PNP9[29]\ : OA1C - port map(A => ldlock, B => annul_4, C => holdn, Y => - N_6825_i); - - \r.x.data_0_RNIBJ9E[22]\ : XNOR2 - port map(A => \data_0_0[22]\, B => invop2_0, Y => N_4269_i); - - \r.e.aluop_0_RNIUE2QL[0]\ : AOI1B - port map(A => \logicout[15]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_5[15]\, Y => \aluresult_1_iv_6[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I156_Y : NOR3A - port map(A => N493_0, B => N497_2, C => N567_2, Y => N625); - - \un1_r.w.s.cwp_1_SUM0_0\ : XNOR2 - port map(A => \rstate_RNIRDFU5[1]\, B => \cwp[0]\, Y => - N_6527); - - \r.f.pc_RNO_1[25]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[25]\, C => - \pc_1_iv_0[25]\, Y => \pc_1_iv_1[25]\); - - \r.a.ctrl.inst_RNI2H3H1[23]\ : NOR2 - port map(A => illegal_inst12_0, B => illegal_inst12_tz_tz, - Y => illegal_inst12); - - \r.w.s.cwp[2]\ : DFN1E0 - port map(D => \cwp_1_0[2]\, CLK => lclk_c, E => holdn, Q - => \cwp[2]\); - - \r.d.inst_0_RNI1HLVD2[21]\ : OR2A - port map(A => N_145, B => N_143, Y => N_150); - - \r.e.ldbp2_2_RNI64M357\ : AO1C - port map(A => aluresult_0_sqmuxa_0, B => \eaddress[27]\, C - => \aluresult_0_iv_9[27]\, Y => \aluresult[27]\); - - \r.d.pc_RNO[30]\ : MX2 - port map(A => \fpc[30]\, B => \dpc[30]\, S => N_6763_i, Y - => \pc_RNO[30]\); - - \r.a.imm_RNO[6]\ : NOR2B - port map(A => \inst_0[6]\, B => call_hold5, Y => - \un3_de_ren1[124]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I136_Y : OR2B - port map(A => N537_1, B => N533_0, Y => N599_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I242_Y\ : OR2B - port map(A => ADD_30x30_fast_I242_Y_0, B => I210_un1_Y, Y - => N714); - - \r.d.inull_RNIVKU2\ : NOR2 - port map(A => \inull\, B => \inst_0[26]\, Y => - annul_next_1_sqmuxa_1_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I266_Y_0_0\ : XOR2 - port map(A => \dpc[8]\, B => \inst_0[6]\, Y => - ADD_30x30_fast_I266_Y_0_0); - - \r.m.y_RNO_3[4]\ : AOI1B - port map(A => \y[4]\, B => y08_0, C => \y_m[5]\, Y => - \y_iv_0[4]\); - - \r.e.op2_RNIQCAP[5]\ : OR2A - port map(A => \un1_iu0_5[71]\, B => \un1_iu0_6[5]\, Y => - \logicout_4[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I48_Y_i : NOR2B - port map(A => N467, B => N464, Y => N_15_i); - - \comb.branch_address.tmp_ADD_30x30_fast_I283_Y_0_0\ : XOR2 - port map(A => \dpc[25]\, B => \inst_0_1[25]\, Y => - ADD_30x30_fast_I283_Y_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I77_Y : AO13 - port map(A => N418_0, B => \un1_iu0_6[8]\, C => \data_0[8]\, - Y => N536_0); - - \r.w.s.s_RNO\ : OR2A - port map(A => rst, B => N_4943, Y => s_RNO); - - \r.a.ctrl.inst_RNIQO231[23]\ : OR2A - port map(A => inst_21_1, B => N_225, Y => inst_21); - - \r.e.op1_RNO[11]\ : MX2C - port map(A => \d_i[11]\, B => \d_i[12]\, S => N_227, Y => - \aop1[11]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I312_Y_0_1 : XOR2 - port map(A => \data_0[21]\, B => \un1_iu0_6[21]\, Y => - \un6_ex_add_res_s2_1[22]\); - - \r.x.ctrl.rd_RNI4SGO[0]\ : OA1B - port map(A => N_6352, B => \rd_0[0]\, C => \rstate[0]\, Y - => waddr(0)); - - \r.f.pc_RNO_5[13]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[13]\, Y => \xc_trap_address_m[13]\); - - \r.e.op2_RNO[17]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[17]\, Y => N_301); - - \r.e.op1_RNIOM8G[31]\ : OR2B - port map(A => \op1[31]\, B => un14_casaen_s1_0, Y => - \op1_m_0[31]\); - - \r.x.data_0[26]\ : DFN1E0 - port map(D => \data_0_1[26]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[26]\); - - \r.f.pc_RNO_4[24]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[24]\, Y => \xc_trap_address_m[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I50_Y\ : AO13 - port map(A => \inst_0[18]\, B => \dpc[20]\, C => N409_2, Y - => N467_1); - - \r.f.pc_RNO_0[5]\ : NOR3C - port map(A => \un6_ex_add_res_m_1[6]\, B => \pc_1_iv_0[5]\, - C => \tmp_m[5]\, Y => \pc_1_iv_2[5]\); - - un6_fe_npc_I_196 : XOR2 - port map(A => N_14_0, B => \fe_pc[29]\, Y => I_196); - - \r.f.pc_RNO_0[9]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[9]\, C => - \pc_1_iv_0[9]\, Y => \pc_1_iv_1[9]\); - - \r.a.ctrl.rett\ : DFN1E0 - port map(D => rett_1_2, CLK => lclk_c, E => holdn, Q => - rett_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I13_P0N : OR3A - port map(A => \data_0_2[12]\, B => \op1[12]\, C => ldbp1_0, - Y => N434); - - un6_ex_add_res_d2_ADD_33x33_fast_I21_P0N : AO1A - port map(A => ldbp1, B => \op1[20]\, C => \data_0_2[20]\, Y - => N458_0); - - \r.x.result_RNI1VVN5[7]\ : OR2A - port map(A => N_3687, B => \bpdata[7]\, Y => - \bpdata_i_m[7]\); - - \comb.lock_gen.un1_icc_check5_RNO_0\ : OA1A - port map(A => icc_check6_0, B => un7_op_3, C => - un1_icc_check5_0, Y => un1_icc_check5_1); - - \r.e.op2_RNO_0[23]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[23]\, C - => \d_1_iv_4[23]\, Y => \d_1[23]\); - - \r.w.s.y_RNO_2[27]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[27]\, Y - => N_411); - - \r.e.op1_RNO[31]\ : MX2C - port map(A => \d_i[31]\, B => \aop1_1_i[31]\, S => N_227, Y - => \aop1[31]\); - - \r.e.ctrl.inst_RNI1L1S[20]\ : NOR3A - port map(A => \inst_1[20]\, B => \inst_0[23]\, C => - aluresult_13_sqmuxa_3, Y => aluresult_13_sqmuxa_1); - - \r.d.inst_0_RNI4023[20]\ : OR2B - port map(A => \inst_0[20]\, B => \inst_0[19]\, Y => N_67); - - \r.x.rstate_RNI7VQQ1[0]\ : MX2C - port map(A => N_3396, B => \xc_result[5]\, S => \rstate[0]\, - Y => \wdata[5]\); - - \r.w.result[6]\ : DFN1E0 - port map(D => \wdata[6]\, CLK => lclk_c, E => holdn, Q => - \result[6]\); - - \r.w.s.wim[1]\ : DFN1E0 - port map(D => \wim_1[1]\, CLK => lclk_c, E => holdn, Q => - \wim[1]\); - - \r.x.data_0[3]\ : DFN1E0 - port map(D => \data_0_1[3]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I273_Y_0\ : XOR2 - port map(A => N729, B => ADD_30x30_fast_I273_Y_0_0, Y => - \tmp[15]\); - - \r.x.npc_RNIU4VI[0]\ : MX2C - port map(A => N_3214, B => N_3244, S => \npc[0]\, Y => - \xc_result[3]\); - - \r.d.inst_0_RNI4423[24]\ : NOR2B - port map(A => \inst_0_0[24]\, B => \inst_0_0[22]\, Y => - N_3736_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I322_Y_0_0 : XOR2 - port map(A => \op2[31]\, B => \un1_iu0_6[31]\, Y => - ADD_33x33_fast_I322_Y_0_0); - - \r.e.shleft_RNIHEFF\ : OR2A - port map(A => \un1_iu0_6[28]\, B => shleft, Y => - \shiftin_5[28]\); - - \r.x.rstate_0[0]\ : DFN1 - port map(D => N_6322s, CLK => lclk_c, Q => \rstate_0[0]\); - - \r.m.ctrl.inst[24]\ : DFN1E0 - port map(D => \inst[24]\, CLK => lclk_c, E => holdn, Q => - \inst_0[24]\); - - \r.f.pc_RNO_5[25]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[25]\, Y => \xc_trap_address_m[25]\); - - \r.e.aluop_RNIB3P34[1]\ : OR2B - port map(A => \bpdata[2]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[2]\); - - \comb.cwp_ctrl.ncwp_3_I_11\ : XNOR2 - port map(A => \inst_0[19]\, B => \cwp_0[2]\, Y => - \DWACT_ADD_CI_0_partial_sum[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I6_G0N : NOR2B - port map(A => \un1_iu0_6[5]\, B => \op2[5]\, Y => N412_1); - - \r.f.pc[9]\ : DFN1E0 - port map(D => \pc_1[9]\, CLK => lclk_c, E => holdn, Q => - \fpc[9]\); - - \r.e.aluop_RNIR7511[2]\ : XA1 - port map(A => \op2_RNI1LHG[1]\, B => \aluop_1[2]\, C => - \un1_iu0_6[1]\, Y => N_3528); - - \r.e.ldbp2_0_RNIHIRU31\ : OR2A - port map(A => \eaddress[12]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[13]\); - - \r.a.ctrl.rd[4]\ : DFN1E0 - port map(D => N_33, CLK => lclk_c, E => holdn, Q => - \rd_1[4]\); - - \r.a.rsel1[0]\ : DFN1E0 - port map(D => \osel[0]\, CLK => lclk_c, E => holdn, Q => - \rsel1[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I172_Y : NOR2B - port map(A => N583_2, B => N575_2, Y => N641); - - \r.d.inst_0_RNILEV6[19]\ : NOR3B - port map(A => \inst_0[19]\, B => un11_op, C => - \inst_0_0[22]\, Y => un14_op_1); - - \r.e.aluop_RNIKVVH6[0]\ : MX2 - port map(A => N_3580, B => N_3644, S => \aluop_1[0]\, Y => - \logicout[21]\); - - un6_fe_npc_I_166 : XOR2 - port map(A => N_35_0, B => \fe_pc[26]\, Y => I_166); - - un6_ex_add_res_d1_ADD_33x33_fast_I199_Y : AO1A - port map(A => N603_0, B => N610_2, C => N602_0, Y => N668); - - \r.e.aluop_2_RNI9AV11[1]\ : MX2C - port map(A => N_3527, B => \logicout_3[0]\, S => - \aluop_2[1]\, Y => N_3559); - - \r.w.s.y_RNO_0[18]\ : NOR2A - port map(A => N_481, B => \result_0[18]\, Y => N_391); - - \r.e.aluop_1_RNIUUU83[1]\ : MX2C - port map(A => \logicout_4[10]\, B => N_6844, S => N_6866_i, - Y => N_3633); - - \r.w.s.y[17]\ : DFN1E0 - port map(D => N_3781, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[17]\); - - un2_rstn_5_RNIL50VA : NAND2 - port map(A => \tmp[11]\, B => \un2_rstn_5\, Y => N_6620); - - \r.m.ctrl.inst_RNI4D1E_0[19]\ : NOR2B - port map(A => \inst_3[20]\, B => \inst_3[19]\, Y => - iflush_1); - - \r.e.op2_RNO_2[17]\ : NOR3C - port map(A => \d_1_iv_1[17]\, B => \d_1_iv_0[17]\, C => - \rfo_m_i[49]\, Y => \d_1_iv_3[17]\); - - \r.e.jmpl_RNIS1V9M\ : OR2B - port map(A => \shiftin_17[9]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[9]\); - - \r.m.y_RNO_4[21]\ : OR2B - port map(A => \y[22]\, B => mulstep_0, Y => \y_m_0[22]\); - - \r.x.result_RNI606K6[5]\ : OA1C - port map(A => \result_0[5]\, B => cwp_1_sqmuxa_0, C => et_m, - Y => N_3029); - - \comb.branch_address.tmp_ADD_30x30_fast_I176_un1_Y\ : NOR2A - port map(A => N550, B => N543, Y => I176_un1_Y); - - \r.e.su_RNI28U5D\ : NOR3C - port map(A => \aluresult_1_iv_4[7]\, B => - \aluresult_1_iv_3[7]\, C => \logicout_m_0[7]\, Y => - \aluresult_1_iv_6[7]\); - - \r.f.pc_RNIIOQV1[11]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[11]\, Y => \xc_trap_address_m[11]\); - - \r.e.aluop_1_RNIN0ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[21]\, B => \aluop_1[1]\, C => - \un1_iu0_5[87]\, Y => N_6904_i); - - \r.m.y_RNO_3[25]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y[25]\, C => \y_m[25]\, Y - => \y_iv_1[25]\); - - \r.e.jmpl_RNI4HD5L\ : OR2B - port map(A => \shiftin_17[4]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[4]\); - - \comb.ld_align.rdata199_RNI46JTI\ : OR2 - port map(A => rdata_1_sqmuxa_0, B => rdata199, Y => - rdata_1_sqmuxa_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I61_Y\ : OA1 - port map(A => \dpc[14]\, B => \inst_0[12]\, C => N398_2, Y - => N478_0); - - \r.d.inst_0_RNI9AJ4[28]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[28]\, S => - \inst_0[30]\, Y => \inst_0_1[30]\); - - \r.e.op1_RNO[18]\ : MX2C - port map(A => \d_i[18]\, B => \d_i[19]\, S => N_227_0, Y - => \aop1[18]\); - - \r.x.rstate_RNIC27D2[0]\ : MX2C - port map(A => N_3420, B => \xc_result[29]\, S => - \rstate[0]\, Y => \wdata[29]\); - - \r.e.shleft_0_RNIV7VF3\ : MX2 - port map(A => \shiftin_5[51]\, B => \shiftin_5[35]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[35]\); - - \r.e.aluop_RNIPG1E1[1]\ : MX2C - port map(A => N_3531, B => \logicout_3[4]\, S => - \aluop_3[1]\, Y => N_3563); - - \r.a.rsel1_RNI5LB_0[0]\ : NOR2A - port map(A => \rsel1[1]\, B => \rsel1[0]\, Y => N_484); - - un6_ex_add_res_d2_ADD_33x33_fast_I145_Y : AO1B - port map(A => N546_0, B => N543_1, C => - ADD_33x33_fast_I145_Y_0_1, Y => N608_0); - - \r.e.aluop_0_RNI68HG3[0]\ : MX2C - port map(A => N_3565, B => N_3629, S => \aluop_0[0]\, Y => - \logicout[6]\); - - \r.a.ctrl.pc_RNII8F2C[29]\ : MX2 - port map(A => \pc[29]\, B => N_3906, S => ex_bpmiss_1_0, Y - => \fe_pc[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I260_Y_2 : NOR3C - port map(A => I97_un1_Y, B => ADD_33x33_fast_I260_Y_0_0, C - => I157_un1_Y_i, Y => ADD_33x33_fast_I260_Y_2_0); - - \r.e.aluop_0_RNIH37O1[1]\ : MX2C - port map(A => \logicout_4[3]\, B => N_6829, S => N_6866_i_0, - Y => N_3626); - - \r.e.aluop_0_RNIEMIQG[0]\ : NOR2B - port map(A => \bpdata_m[3]\, B => \aluresult_1_iv_4[3]\, Y - => \aluresult_1_iv_5[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I45_Y\ : NOR2B - port map(A => N422, B => N419_2, Y => N462); - - \r.a.ctrl.pc_RNIQ7E2C[21]\ : MX2 - port map(A => \pc[21]\, B => N_3898, S => ex_bpmiss_1_0, Y - => \fe_pc[21]\); - - \r.d.pc[20]\ : DFN1 - port map(D => \pc_RNO[20]\, CLK => lclk_c, Q => \dpc[20]\); - - \r.e.op2_RNIUAOP[14]\ : MX2 - port map(A => \op2[14]\, B => N_4261, S => ldbp2_2, Y => - \un1_iu0_5[80]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I77_Y\ : OA1 - port map(A => \dpc[7]\, B => \inst_0[5]\, C => N371, Y => - N494); - - \r.e.ldbp2_RNI3BS185\ : OR2A - port map(A => \eaddress[30]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[31]\); - - \r.m.y_RNO_1[12]\ : AOI1B - port map(A => \y[12]\, B => y08_0, C => \y_m[13]\, Y => - \y_iv_0[12]\); - - \r.m.ctrl.inst[27]\ : DFN1E0 - port map(D => \inst_1[27]\, CLK => lclk_c, E => holdn, Q - => \inst_3[27]\); - - \r.e.cwp_RNIFULQD[2]\ : NOR3C - port map(A => \aluresult_2_iv_3[2]\, B => - \aluresult_2_iv_2[2]\, C => \logicout_m_0[2]\, Y => - \aluresult_2_iv_5[2]\); - - \r.e.ldbp2_2\ : DFN1E0 - port map(D => ldbp2, CLK => lclk_c, E => holdn, Q => - ldbp2_2); - - \r.e.op2_RNO_6[23]\ : OR3B - port map(A => d29_0, B => \imm[23]\, C => \rsel2[0]\, Y => - \imm_m_i[23]\); - - \r.m.ctrl.wicc_RNILN9L\ : MX2C - port map(A => N_4180, B => \icc_0[0]\, S => wicc_3, Y => - N_4185); - - \r.f.pc[27]\ : DFN1E0 - port map(D => \pc_1[27]\, CLK => lclk_c, E => holdn, Q => - \fpc[27]\); - - \r.e.invop2_0_RNILIU7M\ : MX2C - port map(A => \un6_ex_add_res_s2[13]\, B => - \un6_ex_add_res_s0[13]\, S => invop2_0, Y => N_6632); - - un6_ex_add_res_d2_ADD_33x33_fast_I321_Y_0_1 : XOR2 - port map(A => \data_0[30]\, B => \un1_iu0_6[30]\, Y => - \un6_ex_add_res_s2_1[31]\); - - un6_fe_npc_I_143 : XOR2 - port map(A => N_51, B => \fe_pc[24]\, Y => I_143); - - \r.m.y_RNI1EMI4[13]\ : NOR3C - port map(A => \ex_op2_m[13]\, B => aluresult_8_sqmuxa_i, C - => \aluresult_1_iv_1[13]\, Y => \aluresult_1_iv_2[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I66_Y : AND2 - port map(A => N437_0, B => N440, Y => N525); - - \r.m.y_RNO_2[23]\ : OR2 - port map(A => y14, B => \logicout[23]\, Y => \y_RNO_2[23]\); - - \r.d.inst_0_RNO[28]\ : NOR2B - port map(A => rst, B => N_4628, Y => \inst_0_RNO[28]\); - - \r.x.y[28]\ : DFN1E0 - port map(D => \y[28]\, CLK => lclk_c, E => holdn, Q => - \y_2[28]\); - - \r.m.result[27]\ : DFN1E0 - port map(D => \eres2[27]\, CLK => lclk_c, E => holdn, Q => - \maddress[27]\); - - \r.x.data_0_RNO_0[27]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_27, Y => - \dco_m_1[123]\); - - \r.x.laddr_RNIF5HB51_0[1]\ : NOR3C - port map(A => \me_laddr_2[1]\, B => rdata200, C => ld_0_0, - Y => rdata_4_sqmuxa); - - \r.e.ctrl.tt[3]\ : DFN1E0 - port map(D => \tt_0[3]\, CLK => lclk_c, E => holdn, Q => - \tt_5[3]\); - - \r.x.data_0_RNO_2[10]\ : OA1A - port map(A => data_0_0_26, B => rdata_5_sqmuxa, C => - \data_0_m_i[10]\, Y => \data_0_1_0_iv_0[10]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I175_Y : AO1 - port map(A => N586_0, B => N579_1, C => N578_0, Y => N644_0); - - \r.e.op1[30]\ : DFN1E0 - port map(D => \aop1[30]\, CLK => lclk_c, E => holdn, Q => - \op1[30]\); - - \r.w.s.ps_RNI76J61\ : OR2A - port map(A => ps, B => aluresult_11_sqmuxa, Y => ps_m_0); - - \r.e.ldbp2_1_RNI1B7RI2\ : AO1C - port map(A => aluresult_0_sqmuxa_0, B => \eaddress[8]\, C - => \aluresult_1_iv_9[8]\, Y => \aluresult[8]\); - - \r.a.ctrl.wicc_RNO\ : OA1B - port map(A => wicc_1_0_a3_0_0, B => wicc_1_0_tz_0, C => - N_143, Y => wicc_1); - - \r.x.ctrl.inst_RNISL1E[22]\ : NOR2B - port map(A => \inst_0[22]\, B => \inst_1[19]\, Y => y10_3_0); - - \r.w.s.tba_RNIA4CA1[9]\ : OR2B - port map(A => \tba[9]\, B => aluresult_12_sqmuxa, Y => - \tba_m[9]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I33_un1_Y : NAND2 - port map(A => N484_0, B => N488_0, Y => I33_un1_Y_0); - - \r.x.y[31]\ : DFN1E0 - port map(D => \y[31]\, CLK => lclk_c, E => holdn, Q => - \y_1[31]\); - - \r.m.y_RNO_2[30]\ : OR2B - port map(A => \y[30]\, B => y08, Y => \y_m_0[30]\); - - \r.x.result_RNISIVN5[6]\ : OR2A - port map(A => N_3687, B => \bpdata[6]\, Y => - \bpdata_i_m[6]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I266_Y_0_o3 : OR2A - port map(A => N_74_i, B => N506, Y => N778); - - \r.x.data_0_RNO_1[20]\ : NOR2A - port map(A => \data_0_2[20]\, B => ld_3, Y => - \data_0_m[20]\); - - \r.a.ctrl.wy_RNO_0\ : NOR3B - port map(A => wy_1_0_a3_0_7_1, B => wy_1_0_a3_0_7_2, C => - un7_op_3, Y => wy_1_0_a3_0_4); - - \r.a.ctrl.inst_RNIDG1E[21]\ : XNOR2 - port map(A => \inst_2[19]\, B => \inst_2[21]\, Y => N_209); - - \r.f.pc_RNO_0[14]\ : OR2B - port map(A => I_73, B => annul_RNIVCQHS1, Y => N_29); - - \r.m.result_RNI20P1[18]\ : OR2B - port map(A => d13, B => \maddress[18]\, Y => - \result_m_0[18]\); - - \r.e.ctrl.pc_RNIBCTN2[31]\ : AOI1 - port map(A => \pc[31]\, B => jmpl_0, C => \aluresult_6[31]\, - Y => \aluresult_1_iv_1[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I135_Y : AO1 - port map(A => N536_1, B => N533_0, C => N532_0, Y => N598_1); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.a.bp_RNIKBBRB_0\ : NOR2B - port map(A => \ra_bpmiss_1_0\, B => ex_bpmiss_1_0, Y => - bpmiss_1_i_0_0); - - \r.f.pc_RNO_7[16]\ : MX2 - port map(A => \fpc[16]\, B => \tba[4]\, S => rstate_6314_d, - Y => \xc_trap_address[16]\); - - \r.e.ctrl.inst[20]\ : DFN1E0 - port map(D => \inst_2[20]\, CLK => lclk_c, E => holdn, Q - => \inst_1[20]\); - - \r.e.op1[14]\ : DFN1E0 - port map(D => \aop1[14]\, CLK => lclk_c, E => holdn, Q => - \op1[14]\); - - \r.a.ctrl.cnt_RNILD6A1[0]\ : OR3 - port map(A => aluop_2_1_0_a5_1_0, B => N_519, C => N_232, Y - => \cnt_RNILD6A1[0]\); - - \r.m.result_RNIT6SC3[9]\ : AOI1B - port map(A => data1(9), B => d11_0, C => \d_iv_1[9]\, Y => - \d_iv_2[9]\); - - \r.m.result_RNO[31]\ : MX2 - port map(A => \aluresult[31]\, B => \op1[31]\, S => - un17_casaen_0_1, Y => \eres2[31]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I197_un1_Y : OR2B - port map(A => N608, B => N601_0, Y => I197_un1_Y_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I53_Y : MAJ3 - port map(A => \data_0_2[20]\, B => \un1_iu0_6[20]\, C => - N454_1, Y => N512_1); - - \r.e.op2_RNI4GMB1_0[31]\ : OR2 - port map(A => \un1_iu0_6[31]\, B => \un1_iu0_5[97]\, Y => - \logicout_3[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I130_Y_0 : OAI1 - port map(A => \data_0[10]\, B => \un1_iu0_6[10]\, C => - N431_2, Y => ADD_33x33_fast_I130_Y_0_1); - - \r.e.ldbp2_1\ : DFN1E0 - port map(D => ldbp2, CLK => lclk_c, E => holdn, Q => - ldbp2_1); - - \r.e.ctrl.cnt_RNI6U9K1[0]\ : NOR3C - port map(A => N_3749_3, B => enaddr_2_sqmuxa_0, C => - enaddr_2_sqmuxa_1, Y => enaddr_2_sqmuxa_3); - - \r.a.imm[7]\ : DFN1E0 - port map(D => \un3_de_ren1[125]\, CLK => lclk_c, E => holdn, - Q => \imm[7]\); - - \r.a.ctrl.inst_RNICT362[31]\ : OR2B - port map(A => N_473_i, B => N_344, Y => N_230); - - \r.w.s.tba_RNI24CA1[1]\ : OR2B - port map(A => \tba[1]\, B => aluresult_12_sqmuxa, Y => - \tba_m[1]\); - - \r.e.op1_RNIQ2CR1[31]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[31]\, Y => - un4_icc_m); - - \r.e.aluop_RNICHD84[0]\ : MX2C - port map(A => N_3561, B => N_3625, S => \aluop_1[0]\, Y => - \logicout[2]\); - - \r.e.aluop_2_RNIVH5R2[1]\ : MX2C - port map(A => N_3542, B => \logicout_3[15]\, S => - \aluop_2[1]\, Y => N_3574); - - \r.d.pc[18]\ : DFN1 - port map(D => \pc_RNO[18]\, CLK => lclk_c, Q => \dpc[18]\); - - \r.e.alusel_RNO_0[1]\ : OR2 - port map(A => N_341, B => \alusel_i_0_0[1]\, Y => - \alusel_i_0_1[1]\); - - \r.e.op2_RNO_1[22]\ : OR2B - port map(A => \op1[22]\, B => un14_casaen_s1, Y => - \op1_m_i[22]\); - - \r.e.op1_RNI90CQB[12]\ : NOR3 - port map(A => \edata2_0_iv_0[12]\, B => \bpdata_i_m[12]\, C - => \bpdata_i_m_2[4]\, Y => edata2_0_iv(12)); - - un6_ex_add_res_d0_ADD_33x33_fast_I20_G0N : NOR3A - port map(A => \op1[19]\, B => ldbp1_0, C => \data_0[19]\, Y - => N454_0); - - \r.e.op1_RNI7RKB97[27]\ : NOR3C - port map(A => \op1_m_0[27]\, B => \d_iv_2[27]\, C => - \aluresult_m_0[27]\, Y => \d_i[27]\); - - \r.a.ctrl.pc_RNIC0F2C[27]\ : MX2 - port map(A => \pc_0[27]\, B => N_3904, S => ex_bpmiss_1, Y - => \fe_pc[27]\); - - \r.d.inst_0_RNO[0]\ : NOR2B - port map(A => rst, B => N_4600, Y => \inst_0_RNO[0]\); - - un6_fe_npc_I_203 : XOR2 - port map(A => N_9_0, B => \fe_pc[30]\, Y => I_203); - - \r.w.s.y_RNO[15]\ : MX2 - port map(A => \y_1[15]\, B => \result_0[15]\, S => N_481_0, - Y => N_3779); - - un6_ex_add_res_d1_ADD_33x33_fast_I192_Y : NOR2 - port map(A => N603_0, B => N595_2, Y => N661_0); - - \r.m.y_RNO_4[18]\ : OR3A - port map(A => \y_2[18]\, B => wy_3, C => wy_1_0_1, Y => - N_395); - - un6_fe_npc_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \fe_pc[7]\, Y => N_131); - - un6_ex_add_res_d1_ADD_33x33_fast_I267_un1_Y : OR3C - port map(A => N641_0, B => N657_0, C => N672_0, Y => - I267_un1_Y); - - \r.w.s.y_RNO[18]\ : NOR3 - port map(A => N_391, B => N_390, C => N_392, Y => N_158); - - \r.a.rsel2_0_RNIOKHE[0]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[355]\, Y => \cpi_m_i[355]\); - - \r.x.icc_RNIBSID[1]\ : MX2C - port map(A => \icc_0[1]\, B => \icc_3[1]\, S => wicc, Y => - N_4181); - - \r.m.y_RNIF26I3[11]\ : NOR3C - port map(A => \cpi_m[156]\, B => \y_m_1[11]\, C => - \tt_m[7]\, Y => \aluresult_1_iv_3[11]\); - - \r.f.pc_RNO_4[12]\ : MX2 - port map(A => I_56, B => N_4055, S => bpmiss_1_i_0_0, Y => - \pc_4[12]\); - - \r.e.op1_RNISAE6F[24]\ : NOR2B - port map(A => \edata2_iv_2[24]\, B => \edata2_iv_1[24]\, Y - => edata2_iv_i_0(24)); - - un6_ex_add_res_d0_ADD_33x33_fast_I113_Y_0 : AO18 - port map(A => N457, B => \data_0[21]\, C => \un1_iu0_6[21]\, - Y => ADD_33x33_fast_I113_Y_0); - - \r.d.inst_0_RNI2423[23]\ : NOR2B - port map(A => \inst_0_0[23]\, B => \inst_0_0[21]\, Y => - N_3834_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I17_G0N : NOR2B - port map(A => \un1_iu0_6[16]\, B => \op2[16]\, Y => N445_1); - - \r.x.data_0_RNO_0[4]\ : NOR3C - port map(A => \data_0_1_1_iv_0[4]\, B => \dco_m_i[124]\, C - => \dco_m_i[116]\, Y => \data_0_1_1_iv_2[4]\); - - \r.e.aluop_RNIFOHL[1]\ : NOR3B - port map(A => logicout19_0, B => \aluop_3[1]\, C => - un17_casaen_0, Y => edata_0_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_Y_2\ : AOI1B - port map(A => N588, B => N573, C => ADD_30x30_fast_I235_Y_1, - Y => ADD_30x30_fast_I235_Y_2); - - aluresult_11_sqmuxa_5_RNIQJG41_1 : OR2B - port map(A => aluresult_11_sqmuxa_0, B => - aluresult_12_sqmuxa_5, Y => aluresult_11_sqmuxa); - - un6_ex_add_res_d2_ADD_33x33_fast_I159_un1_Y : OR2B - port map(A => N570, B => N563_0, Y => I159_un1_Y_1); - - \r.w.s.tt_RNIGRP81[6]\ : OR2B - port map(A => \tt[6]\, B => aluresult_12_sqmuxa, Y => - \tt_m[6]\); - - aluresult_11_sqmuxa_5_RNI3B9M1 : OR2B - port map(A => aluresult_11_sqmuxa, B => - aluresult_8_sqmuxa_i, Y => \aluresult_6[31]\); - - \r.e.shcnt_RNIBDLBM[1]\ : MX2C - port map(A => \shiftin_14[12]\, B => \shiftin_14[10]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[10]\); - - \r.e.op2_RNO_8[15]\ : OR3B - port map(A => d29_0_0, B => \imm[15]\, C => \rsel2_1[0]\, Y - => \imm_m_i[15]\); - - \r.e.aluop_0_RNI155R[1]\ : XOR3 - port map(A => \un1_iu0_6[1]\, B => \aluop_0[1]\, C => - \op2_RNI1LHG[1]\, Y => N_6889); - - \r.d.inst_0_RNIL0GL[23]\ : OR2B - port map(A => icc_check8, B => icc_check7_i, Y => imm9); - - \r.m.casa_RNI99E608\ : OR2A - port map(A => \un17_casaen_0_0\, B => \un1_addout_12\, Y - => r_N_6); - - \r.e.ldbp2_2_RNI7V5E57\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[27]\, Y - => \aluresult_m_0[27]\); - - \comb.v.x.data_0_1_1_iv_RNO_1[31]\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_22, B => mcdo_m_0_29, C => - rdata_6_sqmuxa, Y => \dco_m_1[127]\); - - \r.m.casa\ : DFN1E0 - port map(D => mcasa, CLK => lclk_c, E => holdn, Q => casa); - - \r.m.dci.SIGNED_RNO_1\ : XOR2 - port map(A => \inst_1[20]\, B => \inst[19]\, Y => N_3742_i); - - \r.e.shcnt_RNITOC27[3]\ : MX2 - port map(A => \shiftin_8[34]\, B => \shiftin_8[26]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[26]\); - - \r.a.ctrl.pc[22]\ : DFN1E0 - port map(D => \dpc[22]\, CLK => lclk_c, E => holdn, Q => - \pc[22]\); - - \r.m.icc_RNO_14[2]\ : NOR3A - port map(A => icc_0_sqmuxa_1_3, B => \logicout[12]\, C => - \logicout[11]\, Y => icc_0_sqmuxa_1_18); - - \r.e.ctrl.inst_RNIHQGF1[26]\ : AO1D - port map(A => ex_bpmiss_1_0_1630_tz_0, B => - ex_bpmiss_1_0_a5_6_0, C => \inst_1[26]\, Y => - ex_bpmiss_1_0_1630_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I268_Y_0 : AO1 - port map(A => N658_1, B => N643_1, C => N642, Y => - ADD_33x33_fast_I268_Y_0_1); - - \r.x.ctrl.inst_RNI2JBD2[19]\ : NOR3C - port map(A => y_0_sqmuxa_1_2, B => wim_1_sqmuxa_1, C => - xc_wreg_0_sqmuxa, Y => wim_1_sqmuxa); - - \r.d.inst_0_RNIHM3M4[13]\ : OR2 - port map(A => un1_rs1, B => imm, Y => N_3946_1); - - \r.m.y_RNO_0[29]\ : NOR3C - port map(A => N_419, B => N_416, C => \y_iv_0_1[29]\, Y => - \y_iv_0_2[29]\); - - \r.a.ctrl.inst_RNICC1E_1[19]\ : OR2 - port map(A => \inst_2[20]\, B => \inst_2[19]\, Y => N_207); - - \r.w.s.tba_RNIEN558[13]\ : NOR2B - port map(A => \aluresult_1_iv_3[25]\, B => \bpdata_m_2[1]\, - Y => \aluresult_1_iv_5[25]\); - - \comb.misc_op.un1_r.x.ctrl.rd_0_0\ : XNOR2 - port map(A => \rd[0]\, B => \rd_0[0]\, Y => rd_0_i_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I162_Y\ : AO1 - port map(A => N536, B => N529, C => N528, Y => N588); - - \r.x.rstate_RNO_0[1]\ : MX2 - port map(A => \rstate_ns[1]\, B => \rstate[1]\, S => holdn, - Y => N_6323); - - \r.e.bp\ : DFN1E0 - port map(D => bp_1_1, CLK => lclk_c, E => holdn, Q => bp_0); - - \r.d.pv_RNI565951\ : OR3A - port map(A => un2_exbpmiss_0, B => ex_bpmiss_1_0, C => - \de_hold_pc_1\, Y => un2_exbpmiss); - - \r.f.pc_RNO_2[15]\ : OR2B - port map(A => I_77, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[13]\); - - \r.d.inst_0_RNIVIU9[27]\ : MX2C - port map(A => branch_4_i, B => branch_8_i, S => - \inst_0[27]\, Y => N_3350); - - \r.e.shcnt_RNIJN0OF[2]\ : MX2A - port map(A => \shiftin_11[37]\, B => \shiftin_11[33]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[33]\); - - \r.m.dci.enaddr\ : DFN1E0 - port map(D => \eenaddr\, CLK => lclk_c, E => holdn, Q => - enaddr); - - \r.e.jmpl_RNI0468A2\ : NOR3C - port map(A => \shiftin_17_m[18]\, B => - \aluresult_1_iv_6[17]\, C => \shiftin_17_m_0[17]\, Y => - \aluresult_1_iv_8[17]\); - - \r.w.result_RNIOB5J[11]\ : AOI1B - port map(A => \un1_p0_6[363]\, B => d14_0, C => - \result_m_0_0[11]\, Y => \d_iv_0[11]\); - - \r.x.result[25]\ : DFN1E0 - port map(D => \maddress[25]\, CLK => lclk_c, E => holdn, Q - => \result_0[25]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I129_Y_0 : MAJ3 - port map(A => \op2[13]\, B => \un1_iu0_6[13]\, C => N433_0, - Y => ADD_33x33_fast_I129_Y_0); - - \r.w.s.y_RNO[27]\ : NOR3 - port map(A => N_410, B => N_409, C => N_411, Y => N_172); - - \r.e.aluop_RNIAJG84[0]\ : MX2C - port map(A => N_3564, B => N_3628, S => \aluop_1[0]\, Y => - \logicout[5]\); - - \r.d.inst_0_0_0[21]\ : DFN1 - port map(D => \inst_0_0_0_RNIQ98I03[21]\, CLK => lclk_c, Q - => \un1_p0_6_0[60]\); - - \r.w.s.tba[0]\ : DFN1E1 - port map(D => \result[12]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[0]\); - - \r.e.aluop_0_RNI6ALC[2]\ : XA1 - port map(A => \un1_iu0_5[75]\, B => \aluop_0[2]\, C => - \un1_iu0_6[9]\, Y => N_3536); - - un6_ex_add_res_d1_ADD_33x33_fast_I244_Y : OR2 - port map(A => N658_0, B => ADD_33x33_fast_I244_un1_Y, Y => - N799_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I181_Y : AOI1 - port map(A => N592_0, B => N585_0, C => N584_0, Y => N650); - - \r.e.aluop_0_RNI1LMS3[0]\ : OR2B - port map(A => \logicout[6]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[6]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I188_Y : NOR2 - port map(A => N599_1, B => N591_0, Y => N657_0); - - \r.x.npc_1[1]\ : DFN1E0 - port map(D => \npc_1_0[1]\, CLK => lclk_c, E => holdn, Q - => \npc_1[1]\); - - \r.x.y[0]\ : DFN1E0 - port map(D => \y_0[0]\, CLK => lclk_c, E => holdn, Q => - \y_2[0]\); - - \r.e.aluop_RNIVC7U6[0]\ : OR2B - port map(A => \logicout[14]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[14]\); - - \r.e.aluop_0_RNIEAJ5[1]\ : NOR3A - port map(A => \aluop_0[2]\, B => \aluop_0[0]\, C => - \aluop_0[1]\, Y => aluresult_8_sqmuxa_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I234_Y\ : OR3C - port map(A => I194_un1_Y, B => ADD_30x30_fast_I234_Y_1, C - => I234_un1_Y, Y => N698); - - \r.x.mexc_RNO_0\ : MX2 - port map(A => mexc, B => mexc_0, S => mexc_1_sqmuxa_0, Y - => N_5246); - - \r.e.aluop_RNI1UH11[2]\ : NOR3 - port map(A => logicout22_1, B => \aluop_1[2]\, C => - un17_casaen_0, Y => edata_1_sqmuxa); - - \r.a.ctrl.pc[10]\ : DFN1E0 - port map(D => \dpc[10]\, CLK => lclk_c, E => holdn, Q => - \pc_3[10]\); - - \r.w.s.wim_RNIA74N2[2]\ : MX2 - port map(A => \wim[2]\, B => \result_0[2]\, S => - wim_1_sqmuxa, Y => \wim_1[2]\); - - \r.a.ctrl.inst_RNI8LEQ[27]\ : MX2C - port map(A => branch_4, B => branch_8, S => \inst_2[27]\, Y - => N_3343); - - \r.f.pc_RNIQF6641[11]\ : MX2B - port map(A => \fpc[11]\, B => \eaddress[11]\, S => jump, Y - => N_4054); - - un6_ex_add_res_d1_ADD_33x33_fast_I168_Y : NOR2B - port map(A => N579_2, B => N571_0, Y => N637); - - \r.x.result_RNI1PAN3[26]\ : MX2C - port map(A => \un1_iu0_6[26]\, B => \un1_p0_6[378]\, S => - bpdata6_0_0, Y => \bpdata[26]\); - - \r.f.pc_RNO_4[22]\ : MX2 - port map(A => I_129, B => N_4065, S => bpmiss_1_i_0, Y => - \pc_4[22]\); - - \r.w.s.pil_RNI8MFA1[1]\ : OR2A - port map(A => \pil[1]\, B => aluresult_11_sqmuxa, Y => - \pil_m[1]\); - - \r.e.invop2_1_RNIJC7882\ : MX2C - port map(A => \un6_ex_add_res_s2[24]\, B => - \un6_ex_add_res_s0[24]\, S => invop2_1, Y => N_6570); - - \r.m.y_RNO_3[17]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[17]\, C => \y_m[17]\, Y - => \y_iv_1[17]\); - - \r.e.op1[13]\ : DFN1E0 - port map(D => \aop1[13]\, CLK => lclk_c, E => holdn, Q => - \op1[13]\); - - \r.e.aluop_RNIPVQC6[0]\ : OR2B - port map(A => \logicout[29]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[29]\); - - \r.m.result_RNI0V3G3[2]\ : NOR3C - port map(A => \d_iv_0[2]\, B => \result_m_0[2]\, C => - \rfo_m[2]\, Y => \d_iv_2[2]\); - - \r.e.aluop_RNI6SJJ1[2]\ : XA1 - port map(A => \un1_iu0_5[85]\, B => \aluop_1[2]\, C => - \op1_RNID1VH[19]\, Y => N_3546); - - \r.e.shleft_RNI559D2\ : MX2B - port map(A => \shiftin_5[33]\, B => \shiftin_5[17]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[17]\); - - \r.e.op1[26]\ : DFN1E0 - port map(D => \aop1[26]\, CLK => lclk_c, E => holdn, Q => - \op1[26]\); - - \r.e.shleft_RNIS6QU1\ : MX2B - port map(A => \shiftin_5[40]\, B => \shiftin_5[24]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[24]\); - - \r.e.op1_RNO[6]\ : MX2C - port map(A => \d_i[6]\, B => \d_i[7]\, S => N_227_0, Y => - \aop1[6]\); - - \r.a.rsel1_RNIJI3A76[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[22]\, Y - => \aluresult_m_0[22]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I243_Y\ : OR3 - port map(A => I243_un1_Y, B => N588, C => I212_un1_Y, Y => - N716); - - \r.x.ctrl.pc_RNICKI61[18]\ : MX2C - port map(A => \un1_p0_6[370]\, B => \pc_2[18]\, S => - s_3_sqmuxa, Y => N_3409); - - \r.m.icc_RNO_18[2]\ : NOR3A - port map(A => \alusel[1]\, B => \alusel[0]\, C => N_198, Y - => icc_0_sqmuxa_1_0); - - \r.e.shcnt_RNIQAF6S[1]\ : MX2C - port map(A => \shiftin_14[26]\, B => \shiftin_14[24]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[24]\); - - \r.e.aluop_1_RNIL56R[1]\ : XOR3 - port map(A => \un1_iu0_6[5]\, B => \aluop_1[1]\, C => - \un1_iu0_5[71]\, Y => N_6835); - - \r.x.ctrl.pc_RNICBI21[30]\ : MX2C - port map(A => \un1_p0_6[382]\, B => \pc_2[30]\, S => N_6352, - Y => N_3421); - - \r.m.ctrl.inst[25]\ : DFN1E0 - port map(D => \inst_2[25]\, CLK => lclk_c, E => holdn, Q - => \inst_3[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I214_un1_Y\ : NOR2B - port map(A => N606, B => N591, Y => I214_un1_Y); - - \r.x.result[1]\ : DFN1E0 - port map(D => \maddress[1]\, CLK => lclk_c, E => holdn, Q - => \result_0[1]\); - - \r.x.ctrl.pc[28]\ : DFN1E0 - port map(D => \pc_3[28]\, CLK => lclk_c, E => holdn, Q => - \pc_0[28]\); - - \r.a.ctrl.inst_RNIBOET5[20]\ : NOR3C - port map(A => illegal_inst34_1, B => illegal_inst34_0, C - => inst_5, Y => illegal_inst34_3); - - \r.e.op2_RNO_3[26]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[26]\, Y => - \aluresult_m_i[26]\); - - \r.f.pc[12]\ : DFN1E0 - port map(D => \pc_1[12]\, CLK => lclk_c, E => holdn, Q => - \fpc[12]\); - - \r.d.pc_RNO[29]\ : MX2 - port map(A => \fpc[29]\, B => \dpc[29]\, S => N_6763_i, Y - => \pc_RNO[29]\); - - \r.e.aluop_1_RNIRGC31[1]\ : XOR3 - port map(A => \un1_iu0_6[20]\, B => \aluop_1[1]\, C => - \un1_iu0_5[86]\, Y => N_6847); - - un6_ex_add_res_d0_ADD_33x33_fast_I305_Y_0 : XNOR3 - port map(A => \data_0[14]\, B => \un1_iu0_6[14]\, C => - N799_1, Y => \un6_ex_add_res_s0[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I318_Y_0 : XNOR2 - port map(A => N772, B => \un6_ex_add_res_s2_1[28]\, Y => - \un6_ex_add_res_s0[28]\); - - \r.e.shleft_1_RNIJ56I1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[29]\, S => - shleft_1, Y => \shiftin_5[60]\); - - \r.w.s.tba_RNI8JFP5[6]\ : AOI1B - port map(A => \bpdata[18]\, B => aluresult_6_sqmuxa, C => - \tba_m[6]\, Y => \aluresult_1_iv_3[18]\); - - \r.f.pc[7]\ : DFN1E0 - port map(D => \pc_1[7]\, CLK => lclk_c, E => holdn, Q => - \fpc[7]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I250_Y_0_o3 : OR2 - port map(A => N418, B => N_62, Y => N817_0); - - \r.e.op2_RNISHAE1[1]\ : OR2B - port map(A => \op2_RNI1LHG[1]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[1]\); - - \r.a.ctrl.inst_RNI7C0E_0[31]\ : OR2A - port map(A => \inst[31]\, B => \inst[30]\, Y => N_201); - - \r.f.pc[2]\ : DFN1E0 - port map(D => \pc_1[2]\, CLK => lclk_c, E => holdn, Q => - \fpc[2]\); - - \r.e.op2_RNIENLB1[10]\ : OR2A - port map(A => \un1_iu0_5[76]\, B => \un1_iu0_6[10]\, Y => - \logicout_4[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I15_P0N : OR2 - port map(A => \un1_iu0_6[14]\, B => \op2[14]\, Y => N440); - - \r.x.y[29]\ : DFN1E0 - port map(D => \y[29]\, CLK => lclk_c, E => holdn, Q => - \y_2[29]\); - - \r.a.imm[11]\ : DFN1E0 - port map(D => \un3_de_ren1[129]\, CLK => lclk_c, E => holdn, - Q => \imm[11]\); - - \r.d.pv_RNI4IIHE\ : NOR3C - port map(A => un5_exbpmiss_i_0, B => - annul_next_2_sqmuxa_1_3, C => un9_rabpmiss, Y => - annul_next_2_sqmuxa_1_5); - - \comb.branch_address.tmp_ADD_30x30_fast_I11_P0N\ : OR2 - port map(A => \inst_0[11]\, B => \dpc[13]\, Y => N392); - - \r.e.op2_RNO_7[13]\ : OR3B - port map(A => d29_0_0, B => \imm[13]\, C => \rsel2_1[0]\, Y - => \imm_m_i[13]\); - - \r.e.shleft_1_RNI6D5I1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[14]\, S => - shleft_1, Y => \shiftin_5[45]\); - - \r.e.shleft_0_RNI64JB3\ : MX2 - port map(A => \shiftin_5[53]\, B => \shiftin_5[37]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[37]\); - - \r.m.y_RNO_4[29]\ : OR3A - port map(A => \y_2[29]\, B => wy_3, C => wy_1_0_1, Y => - N_417); - - \r.m.result_RNO[24]\ : MX2 - port map(A => \aluresult[24]\, B => \op1[24]\, S => - un17_casaen_0_1, Y => \eres2[24]\); - - \r.e.ctrl.pc[28]\ : DFN1E0 - port map(D => \pc[28]\, CLK => lclk_c, E => holdn, Q => - \pc_2[28]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I145_Y\ : NOR2B - port map(A => N519, B => N511, Y => N571_1); - - \r.m.y_RNO_2[24]\ : OR2B - port map(A => \y[24]\, B => y08, Y => N_371); - - \r.e.op2_RNO_5[12]\ : OR2B - port map(A => \result_0[12]\, B => d31, Y => - \result_m_i[12]\); - - \r.e.op1[5]\ : DFN1E0 - port map(D => \aop1[5]\, CLK => lclk_c, E => holdn, Q => - \op1[5]\); - - \r.w.s.tba_RNI6U424[19]\ : AOI1B - port map(A => \tba[19]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[31]\, Y => \aluresult_1_iv_3[31]\); - - \r.m.ctrl.ld_RNIF9L9\ : OR2A - port map(A => ld, B => d27, Y => ldbp2_0_a5_0); - - \r.e.op2_RNIRJ971_0[30]\ : OR2 - port map(A => \un1_iu0_6[30]\, B => \un1_iu0_5[96]\, Y => - \logicout_3[30]\); - - \r.e.ctrl.inst_RNI8T131[23]\ : NOR2A - port map(A => aluresult_11_sqmuxa_6, B => \inst_0[23]\, Y - => aluresult_11_sqmuxa_0); - - \r.e.ctrl.pc_RNI89K11[13]\ : OR2B - port map(A => \pc_2[13]\, B => jmpl_4, Y => \cpi_m[158]\); - - \r.f.pc_RNIO9TUV1[8]\ : AND2 - port map(A => \un6_ex_add_res_m_1[9]\, B => \pc_m[8]\, Y - => \npc_iv_1[8]\); - - \r.e.ldbp2_1_RNI90VAH\ : MX2 - port map(A => \un6_ex_add_res_s1[9]\, B => N_6555, S => - ldbp2_1, Y => \eaddress[8]\); - - \r.d.cwp_RNO[1]\ : MX2 - port map(A => N_4228, B => \cwp_1[1]\, S => N_6358, Y => - \cwp_1_0[1]\); - - \r.e.op1_RNI67OF[29]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[29]\, Y => - \op1_RNI67OF[29]\); - - \r.e.shleft_RNIHURJ\ : OR2A - port map(A => \un1_iu0_6[18]\, B => shleft, Y => - \shiftin_5[18]\); - - \r.e.op2_RNO_4[18]\ : OA1A - port map(A => \maddress[18]\, B => d27, C => \cpi_m_i[370]\, - Y => \d_1_iv_1[18]\); - - un37_ra_I_15 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP_0[0]\, B => \cwp[1]\, Y - => \DWACT_ADD_CI_0_g_array_1_0[0]\); - - \r.d.inst_0_RNO_0[2]\ : MX2 - port map(A => data_0_0_2, B => \inst_0[2]\, S => - mexc_1_sqmuxa_1_0, Y => N_4602); - - \r.m.dci.SIGNED_RNO\ : NOR3B - port map(A => SIGNED_2_1, B => N_3742_i, C => N_3356_3, Y - => SIGNED_2); - - \r.a.rsel2_0_RNIPEPD[0]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[353]\, Y => \cpi_m_i[353]\); - - \r.a.ctrl.inst_RNIG9IL7[21]\ : NOR3B - port map(A => inst_14, B => illegal_inst34_3, C => N_212, Y - => N_474); - - un6_ex_add_res_d2_ADD_33x33_fast_I107_Y : AO1 - port map(A => N508_0, B => N505_0, C => N504_0, Y => N570); - - \r.m.result_RNO[19]\ : MX2 - port map(A => \aluresult[19]\, B => \op1[19]\, S => - un17_casaen_0_1, Y => \eres2[19]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I289_Y_0_0\ : XOR2 - port map(A => \dpc[31]\, B => \inst_0_1[31]\, Y => - ADD_30x30_fast_I289_Y_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I190_un1_Y\ : OR2A - port map(A => N567_1, B => N582_0, Y => I190_un1_Y); - - \r.x.ctrl.pc_RNI0U971[31]\ : MX2C - port map(A => \un1_p0_6[383]\, B => \pc_2[31]\, S => - s_3_sqmuxa_0, Y => N_3422); - - \comb.op_mux.d_1_iv_RNO_1[29]\ : OR2B - port map(A => \op1[29]\, B => un14_casaen_s1, Y => - \op1_m_i[29]\); - - \r.e.mulstep_RNI8VGC_0\ : OR2A - port map(A => wy_0, B => mulstep, Y => y14_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I190_Y : NOR2B - port map(A => N601_0, B => N593, Y => N659); - - \r.e.op1_RNINM8G[21]\ : OR2B - port map(A => \op1[21]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[21]\); - - \r.m.y_RNIBO006[14]\ : NOR2B - port map(A => \aluresult_1_iv_1[14]\, B => - \aluresult_1_iv_2[14]\, Y => \aluresult_1_iv_3[14]\); - - \r.e.aluop_RNI9A7HM[0]\ : AOI1B - port map(A => \logicout[13]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_5[13]\, Y => \aluresult_1_iv_6[13]\); - - \r.f.pc_RNID32PM6[3]\ : OR3C - port map(A => \npc_iv_1[3]\, B => \npc_iv_0[3]\, C => - \npc_iv_2[3]\, Y => rpc_1); - - \r.e.op2_RNO[1]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[1]\, Y => N_285); - - \r.e.aluop_0_RNIRSOT_0[2]\ : NOR2 - port map(A => aluresult_7_sqmuxa_0, B => logicout21_1, Y - => aluresult_7_sqmuxa_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_Y : NAND2 - port map(A => I261_un1_Y_1, B => ADD_33x33_fast_I261_Y_2_1, - Y => N768); - - \r.e.aluop_0_RNI36M72[0]\ : MX2C - port map(A => N_3559, B => N_3623, S => \aluop_0[0]\, Y => - \logicout[0]\); - - \r.e.ctrl.pc_RNI3E8CA[19]\ : AND2 - port map(A => \aluresult_1_iv_3[19]\, B => - \aluresult_1_iv_2[19]\, Y => \aluresult_1_iv_4[19]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I301_Y_0_1 : XOR2 - port map(A => \data_0[10]\, B => \un1_iu0_6[10]\, Y => - \un6_ex_add_res_s2_1[11]\); - - \r.e.cwp_RNI0C0D9[0]\ : NOR3C - port map(A => \aluresult_2_iv_1[0]\, B => \cwp_m[0]\, C => - \aluresult_2_iv_2[0]\, Y => \aluresult_2_iv_4[0]\); - - \r.e.ctrl.inst_RNIB1LO[25]\ : AO1D - port map(A => \inst_1[27]\, B => \inst_2[25]\, C => - ex_bpmiss_1_0_a5_3_0, Y => ex_bpmiss_1_0_1630_tz_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I319_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[28]\, B => \data_0[28]\, Y => - \un6_ex_add_res_s2_1[29]\); - - \r.e.op2_RNO_1[19]\ : OR2B - port map(A => \op1[19]\, B => un14_casaen_s1, Y => - \op1_m_i[19]\); - - \r.d.inst_0_RNIRO4K1[13]\ : MX2C - port map(A => \inst_0[13]\, B => ldcheck2_2_sqmuxa_1_i, S - => annul_RNILQG71, Y => ldcheck2); - - \r.w.s.tba[4]\ : DFN1E1 - port map(D => \result_0[16]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[4]\); - - \r.m.ctrl.pc[10]\ : DFN1E0 - port map(D => \pc_0[10]\, CLK => lclk_c, E => holdn, Q => - \pc_2[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I263_Y_0\ : XOR2 - port map(A => N558, B => ADD_30x30_fast_I263_Y_0_0, Y => - \tmp[5]\); - - \r.a.ctrl.rd_RNIEPQG9[4]\ : NOR3C - port map(A => un1_de_ren1_4_i, B => un1_de_ren1_NE_3, C => - un1_de_ren1_5_i, Y => un1_de_ren1_NE_5); - - \r.m.y_RNO_0[26]\ : NOR3C - port map(A => \y_m[27]\, B => \y_m_0[26]\, C => - \y_iv_1[26]\, Y => \y_iv_2[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I73_Y : AO13 - port map(A => \un1_iu0_6[10]\, B => \data_0[10]\, C => - N424_1, Y => N532_1); - - \r.e.aluop_RNIG3IJ1[2]\ : XAI1A - port map(A => \un1_iu0_5[87]\, B => \aluop_1[2]\, C => - \un1_iu0_6[21]\, Y => N_3548); - - un6_ex_add_res_d1_ADD_33x33_fast_I84_Y : NOR2B - port map(A => N413_1, B => N410_1, Y => N543_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I26_P0N : OR2 - port map(A => \un1_iu0_6[25]\, B => \op2[25]\, Y => N473); - - un6_ex_add_res_d1_ADD_33x33_fast_I260_Y_3 : AOI1B - port map(A => N642_0, B => N627_1, C => - ADD_33x33_fast_I260_Y_2_0, Y => ADD_33x33_fast_I260_Y_3_1); - - \r.e.shcnt_RNIHOGO9[2]\ : MX2C - port map(A => \shiftin_11[13]\, B => \shiftin_11[9]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[9]\); - - \r.e.op1_RNIKT53I2[6]\ : NOR3C - port map(A => \op1_m_0[6]\, B => \d_iv_2[6]\, C => - \aluresult_m_0[6]\, Y => \d_i[6]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I267_Y_0_0\ : XOR2 - port map(A => \dpc[9]\, B => \inst_0[7]\, Y => - ADD_30x30_fast_I267_Y_0_0); - - \r.f.pc_RNO_0[12]\ : NOR3C - port map(A => \un6_ex_add_res_m_1[13]\, B => - \pc_1_iv_0[12]\, C => \tmp_m[12]\, Y => \pc_1_iv_2[12]\); - - \r.a.ctrl.cnt_RNI0BU9[0]\ : OA1C - port map(A => \cnt_2[1]\, B => casa, C => \cnt_1[0]\, Y => - \alusel_i_0_a2_1_0[1]\); - - \r.e.ctrl.inst_RNIFSP8[25]\ : OR2A - port map(A => \icc_0[2]\, B => \inst_2[25]\, Y => N_229); - - \r.a.rsel2_0_RNIKHIQ02[0]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[3]\, Y - => \aluresult_m_i[3]\); - - \r.e.shleft_1_RNI38921\ : MX2 - port map(A => \un1_iu0_6[31]\, B => \un1_iu0_6[0]\, S => - shleft_1, Y => \shiftin_5[31]\); - - \r.e.shcnt_RNI8DOVD[2]\ : MX2C - port map(A => \shiftin_11[31]\, B => \shiftin_11[27]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[27]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I44_Y : AND2 - port map(A => N470, B => N473, Y => N503); - - \r.e.op1[31]\ : DFN1E0 - port map(D => \aop1[31]\, CLK => lclk_c, E => holdn, Q => - \op1[31]\); - - \r.x.data_0[29]\ : DFN1E0 - port map(D => \data_0_1[29]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0_0[29]\); - - \r.m.ctrl.inst_RNIG51L[24]\ : NOR2 - port map(A => \inst_0[24]\, B => trap_0_sqmuxa_3_2, Y => - inst); - - \r.x.data_0_RNO[20]\ : OR3 - port map(A => \dco_m_0[116]\, B => \data_0_m[20]\, C => - \data_0_1_4[18]\, Y => \data_0_1[20]\); - - \r.f.pc_RNO_5[31]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[31]\, Y => \xc_trap_address_m[31]\); - - \r.a.rsel1_RNIPFH_0[0]\ : NOR3A - port map(A => \rsel1[0]\, B => \rsel1[2]\, C => \rsel1[1]\, - Y => N_494); - - un6_ex_add_res_d0_ADD_33x33_fast_I250_Y_0_o3 : OR2 - port map(A => N418_0, B => ADD_33x33_fast_I250_Y_0_a3_0, Y - => N817); - - \r.e.op2_RNIMVGN1[30]\ : OR2B - port map(A => \un1_iu0_5[96]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[30]\); - - \r.d.inst_0_RNO_0[26]\ : MX2 - port map(A => data_0_2_26, B => \inst_0[26]\, S => - inull_RNIFV6VG2_0, Y => N_4626); - - un6_ex_add_res_d2_ADD_33x33_fast_I10_G0N : OAI1 - port map(A => \op1[9]\, B => ldbp1, C => \data_0[9]\, Y => - N424_1); - - \r.w.s.tba[10]\ : DFN1E1 - port map(D => \result_0[22]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[10]\); - - \r.w.s.s_RNIAI3V3\ : AOI1 - port map(A => rstate_8_0, B => et_0_sqmuxa_i, C => s, Y => - s_i_m); - - \r.e.op2_RNO_4[9]\ : OR2B - port map(A => \op1[9]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[9]\); - - \r.e.op2_RNO_7[30]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[382]\, - Y => \cpi_m_i[382]\); - - \r.a.imm_RNO[24]\ : MX2 - port map(A => \inst_0[14]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[142]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I106_Y : OR2B - port map(A => N_74_1, B => N503, Y => N569); - - \r.w.s.et_RNIVNF2_0\ : NOR2A - port map(A => \rstate_0[0]\, B => et, Y => error_1_sqmuxa); - - \r.a.rsel2_0_RNIN1CM2[0]\ : OR2B - port map(A => data2(2), B => d25_0, Y => \rfo_m_i[34]\); - - \r.a.ctrl.inst_RNIEP7S[27]\ : MX2C - port map(A => branch_3, B => branch_7, S => \inst_2[27]\, Y - => N_3340); - - \r.f.pc_RNO[8]\ : OR3C - port map(A => \tmp_m[8]\, B => \pc_1_iv_1[8]\, C => - \un6_fe_npc_m[6]\, Y => \pc_1[8]\); - - \r.e.aluop_RNI44R04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[4]\, Y => - \bpdata_i_m_2[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I310_Y_0 : AX1C - port map(A => I271_un1_Y, B => ADD_33x33_fast_I271_Y_0_1, C - => \un6_ex_add_res_s2_1[20]\, Y => - \un6_ex_add_res_s0[20]\); - - \r.e.ctrl.pc[9]\ : DFN1E0 - port map(D => \pc_0[9]\, CLK => lclk_c, E => holdn, Q => - \pc[9]\); - - \r.e.op1_RNIMM3RB[16]\ : NOR3 - port map(A => \edata2_0_iv_0[16]\, B => \ex_op1_i_m[16]\, C - => \bpdata_i_m_1[0]\, Y => edata2_0_iv(16)); - - \r.x.data_0_RNO_3[1]\ : OR2B - port map(A => N_3455, B => data_0_2_17, Y => \dco_m_i[113]\); - - \r.x.y[6]\ : DFN1E0 - port map(D => \y_0[6]\, CLK => lclk_c, E => holdn, Q => - \y_2[6]\); - - \r.e.op1_RNI3E3U1[0]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[0]\, C => - \ex_op1_i_m[0]\, Y => \edata2_0_iv_0[0]\); - - \r.x.nerror\ : DFN1E0 - port map(D => nerror_1, CLK => lclk_c, E => holdn, Q => - error_i_2); - - \r.e.op2_RNO_8[6]\ : OR3B - port map(A => d29_0_0, B => \imm[6]\, C => \rsel2_0[0]\, Y - => \imm_m_i[6]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I268_un1_Y_0 : OR2 - port map(A => N659_0, B => N643, Y => - ADD_33x33_fast_I268_un1_Y_0); - - \r.e.op2_RNIHS9P[3]\ : OR2A - port map(A => \un1_iu0_5[69]\, B => \un1_iu0_6[3]\, Y => - \logicout_4[3]\); - - \r.e.aluop_1_RNICGR61_0[1]\ : NOR3B - port map(A => miscout69, B => logicout20, C => - aluresult_9_sqmuxa_1, Y => aluresult_10_sqmuxa); - - \r.e.shcnt_RNIK99MI[1]\ : MX2C - port map(A => \shiftin_14[3]\, B => \shiftin_14[1]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[1]\); - - \r.e.op2_RNO_1[16]\ : OR2B - port map(A => \op1[16]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[16]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I10_P0N : OR2 - port map(A => \un1_iu0_6[9]\, B => \op2[9]\, Y => N425_1); - - \r.m.result[18]\ : DFN1E0 - port map(D => \eres2[18]\, CLK => lclk_c, E => holdn, Q => - \maddress[18]\); - - \r.e.op1_RNI69UH[31]\ : MX2 - port map(A => \op1[31]\, B => \data_0_0[31]\, S => ldbp1_3, - Y => \un1_iu0_6[31]\); - - \r.x.ctrl.inst[29]\ : DFN1E0 - port map(D => \inst_3[29]\, CLK => lclk_c, E => holdn, Q - => \inst_1[29]\); - - \r.x.npc_0_RNI9NE41[0]\ : MX2C - port map(A => N_3217, B => N_3247, S => \npc_0[0]\, Y => - \xc_result[6]\); - - \r.f.pc_RNISTGB4[16]\ : MX2 - port map(A => \dpc[16]\, B => \fpc[16]\, S => ra_bpmiss_1, - Y => N_3893); - - un6_ex_add_res_d0_ADD_33x33_fast_I296_Y_0 : XNOR3 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N676_0, - Y => \un6_ex_add_res_s0[6]\); - - \r.x.data_0_RNO_4[3]\ : OR2B - port map(A => rdata_2_sqmuxa, B => data_0_0_11, Y => - \dco_m_i[107]\); - - \r.e.op2_RNO_5[25]\ : AOI1B - port map(A => \result[25]\, B => d31_0, C => \imm_m_i[25]\, - Y => \d_1_iv_0[25]\); - - \r.e.aluop_RNI9KQF4[1]\ : OR2B - port map(A => \bpdata[21]\, B => aluresult_6_sqmuxa, Y => - \bpdata_m[21]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I141_Y\ : NOR2B - port map(A => N515, B => N507, Y => N567_1); - - \r.x.ctrl.pc_RNI22A71[24]\ : MX2C - port map(A => \un1_p0_6[376]\, B => \pc_0[24]\, S => - s_3_sqmuxa_0, Y => N_3415); - - \r.a.ctrl.rd_RNIB29A2[4]\ : XNOR2 - port map(A => \un3_de_ren1[103]\, B => \rd_1[4]\, Y => - un1_de_ren1_4_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I25_G0N : NOR2B - port map(A => \un1_iu0_6[24]\, B => \data_0[24]\, Y => - N469_0); - - \r.m.result_RNICJD4[24]\ : OR2B - port map(A => d13_0, B => \maddress[24]\, Y => - \result_m_0_0[24]\); - - \r.x.y[24]\ : DFN1E0 - port map(D => \y[24]\, CLK => lclk_c, E => holdn, Q => - \y_2[24]\); - - \r.d.pc[6]\ : DFN1 - port map(D => \pc_RNO[6]\, CLK => lclk_c, Q => \dpc[6]\); - - \r.m.y_RNO_3[1]\ : OR3A - port map(A => \y_2[1]\, B => wy_3, C => wy_1_0_1, Y => - N_378); - - \r.e.ctrl.cnt[0]\ : DFN1E0 - port map(D => \cnt_1[0]\, CLK => lclk_c, E => holdn, Q => - \cnt[0]\); - - \r.e.aluop_1_RNIARCM1[1]\ : MX2C - port map(A => N_3533, B => \logicout_3[6]\, S => - \aluop_1[1]\, Y => N_3565); - - \r.a.ctrl.pc_RNITBE2C[22]\ : MX2 - port map(A => \pc[22]\, B => N_3899, S => ex_bpmiss_1, Y - => \fe_pc[22]\); - - \r.e.ldbp2_0\ : DFN1E0 - port map(D => ldbp2, CLK => lclk_c, E => holdn, Q => - ldbp2_0); - - \r.d.pc_RNISDHB4[30]\ : MX2 - port map(A => \dpc[30]\, B => \fpc[30]\, S => - \ra_bpmiss_1_0\, Y => N_3907); - - \r.x.npc_0_RNIMQ1A1[1]\ : MX2 - port map(A => \npc_0[1]\, B => \npc_cnst_m_0[1]\, S => - s_3_sqmuxa_0, Y => \npc_1_0[1]\); - - \r.f.pc_RNO_3[20]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[20]\, C => - \xc_trap_address_m[20]\, Y => \pc_1_iv_0[20]\); - - \r.e.op2_RNO_6[8]\ : OR2B - port map(A => data2(8), B => d25_0, Y => \rfo_m_i[40]\); - - \r.w.s.tba[15]\ : DFN1E1 - port map(D => \result_0[27]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I40_Y_i_o3 : OAI1 - port map(A => \op2[26]\, B => \un1_iu0_6[26]\, C => N479_2, - Y => N_50); - - \r.w.result[8]\ : DFN1E0 - port map(D => \wdata[8]\, CLK => lclk_c, E => holdn, Q => - \result_0[8]\); - - \r.e.op1_RNIK64RB[21]\ : NOR2 - port map(A => \edata2_0_iv_1[21]\, B => \bpdata_i_m_1[5]\, - Y => edata2_0_iv(21)); - - \r.a.rsel1_0_RNID3LJ2[2]\ : OR2B - port map(A => data1(16), B => d11, Y => \rfo_m[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I216_Y_0_a3\ : NOR2B - port map(A => N723, B => N404_0, Y => - ADD_30x30_fast_I216_Y_0_a3); - - \r.x.y[26]\ : DFN1E0 - port map(D => \y_1[26]\, CLK => lclk_c, E => holdn, Q => - \y_2[26]\); - - \r.m.y_RNO_4[26]\ : OR3A - port map(A => \y_2[26]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[26]\); - - \r.a.rsel1_0_RNIUG8M2[2]\ : OR2B - port map(A => data1(6), B => d11, Y => \rfo_m[6]\); - - \r.w.result_RNIPOV6[4]\ : OR2B - port map(A => \result_0[4]\, B => d31, Y => \result_m_i[4]\); - - \r.e.ldbp2_RNIC795BE\ : NOR3C - port map(A => N_9, B => m14_0, C => N_31, Y => m14_2); - - \r.e.op1_RNI416I1[5]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[5]\, Y => - \ex_op1_i_m[5]\); - - \r.x.npc_0_RNI1TR61[0]\ : MX2C - port map(A => N_3233, B => N_3263, S => \npc_0[0]\, Y => - \xc_result[22]\); - - \r.e.op2_RNIRJ971[30]\ : OR2A - port map(A => \un1_iu0_5[96]\, B => \un1_iu0_6[30]\, Y => - \logicout_4[30]\); - - \r.e.op1_RNO[26]\ : MX2C - port map(A => \d_i[26]\, B => \d_i[27]\, S => N_227, Y => - \aop1[26]\); - - \r.e.aluop_RNI1VJD4[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[31]\, Y => - \bpdata_i_m[31]\); - - \r.d.inst_0_RNI1JUM[1]\ : NOR2B - port map(A => \inst_0[1]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI1JUM[1]\); - - \r.a.ctrl.inst_RNIS96K2[22]\ : OA1B - port map(A => N_202, B => illegal_inst37_4, C => - illegal_inst38, Y => un1_illegal_inst33_0); - - \r.m.ctrl.trap_RNIMI3D31\ : OR3C - port map(A => trap_2_0, B => un1_trap_0_sqmuxa_5, C => - un6_annul, Y => trap2); - - \r.m.ctrl.pc_RNIU1HF[23]\ : MX2 - port map(A => \pc_2[23]\, B => \pc_3[23]\, S => \npc_1[1]\, - Y => N_3264); - - \r.m.ctrl.pc_RNIV6AE[6]\ : MX2 - port map(A => \pc_2[6]\, B => \pc_0[6]\, S => \npc_0[1]\, Y - => N_3247); - - \r.f.pc_RNIMEJIR1[4]\ : MX2 - port map(A => I_9, B => N_4047, S => bpmiss_1_i_0, Y => - \pc_4[4]\); - - \r.x.result_RNIPV335[2]\ : NOR2 - port map(A => \bpdata[2]\, B => N_3703_i, Y => - \bpdata_i_m_1[2]\); - - un6_fe_npc_I_206 : AND2 - port map(A => \fe_pc[29]\, B => \fe_pc[30]\, Y => - \DWACT_FINC_E[25]\); - - \r.m.dci.SIGNED\ : DFN1E0 - port map(D => SIGNED_2, CLK => lclk_c, E => holdn, Q => - SIGNED); - - un6_ex_add_res_d0_ADD_33x33_fast_I89_Y : AO13 - port map(A => N400_2, B => \un1_iu0_6[2]\, C => \data_0[2]\, - Y => N548_1); - - \r.d.inst_0_RNO[23]\ : NOR2B - port map(A => rst, B => N_4623, Y => \inst_0_RNO[23]\); - - \r.e.op2_RNO_6[19]\ : OR2B - port map(A => data2(19), B => d25, Y => \rfo_m_i[51]\); - - \r.x.ctrl.inst[21]\ : DFN1E0 - port map(D => \inst[21]\, CLK => lclk_c, E => holdn, Q => - \inst_0[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I103_Y : NOR2A - port map(A => I103_un1_Y_i, B => N500, Y => N566_i); - - \r.x.ctrl.ld\ : DFN1E0 - port map(D => ld, CLK => lclk_c, E => holdn, Q => ld_4); - - un6_ex_add_res_d1_ADD_33x33_fast_I99_un1_Y : OR2A - port map(A => N500_1, B => N497_2, Y => I99_un1_Y); - - \r.x.dci.SIGNED_RNIQD0LV4\ : AO1A - port map(A => rdata_0_sqmuxa, B => \rdata_5[8]\, C => - \rdata_9_m[8]\, Y => \data_0_1_1[12]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I143_Y : AO1 - port map(A => N544_1, B => N541_1, C => N540_0, Y => N606_1); - - \r.a.ctrl.inst_RNINQ7L2[5]\ : AO1B - port map(A => un29_casaen_5, B => un29_casaen_4, C => - illegal_inst35, Y => privileged_inst_0_sqmuxa); - - \r.e.aluop_1_RNI47603[1]\ : MX2C - port map(A => \logicout_4[11]\, B => N_6910, S => N_6866_i, - Y => N_3634); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_un1_Y : NAND2 - port map(A => N799, B => ADD_33x33_fast_I260_un1_Y_0, Y => - I260_un1_Y_i_0); - - \r.a.rsel1_RNI4V53[0]\ : NOR3B - port map(A => \rsel1[0]\, B => \rsel1[1]\, C => - \rsel1_0[2]\, Y => d14_0); - - \r.w.s.y_RNO[26]\ : MX2 - port map(A => \y_2[26]\, B => \result[26]\, S => N_481, Y - => N_3790); - - \r.d.cnt_RNIATF3[1]\ : NOR2B - port map(A => \cnt_0[1]\, B => \inst_0[30]\, Y => N_3737_1); - - \comb.v.x.data_0_1_1_iv_RNO_1[16]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_2_16, Y => - \dco_m_0[112]\); - - un6_fe_npc_I_210 : XOR2 - port map(A => N_4_0, B => \fe_pc[31]\, Y => I_210); - - un6_ex_add_res_d0_ADD_33x33_fast_I24_G0N : OR2A - port map(A => \un1_iu0_6[23]\, B => \data_0[23]\, Y => - N466_1); - - \r.d.pc_RNIITGB4[11]\ : MX2 - port map(A => \dpc[11]\, B => \fpc[11]\, S => ra_bpmiss_1, - Y => N_3888); - - un6_ex_add_res_d2_ADD_33x33_fast_I250_Y_0_a3 : NOR2B - port map(A => N672, B => N419_0, Y => N_62); - - un6_ex_add_res_d1_ADD_33x33_fast_I12_P0N : OR2 - port map(A => \un1_iu0_6[11]\, B => \op2[11]\, Y => N431_1); - - \r.d.inst_0_RNI3DOH[16]\ : MX2 - port map(A => \inst_0[16]\, B => \inst_0[27]\, S => rs1mod, - Y => \un3_de_ren1[93]\); - - \r.a.ctrl.pc_RNI9SE2C[26]\ : MX2 - port map(A => \pc_0[26]\, B => N_3903, S => ex_bpmiss_1_0, - Y => \fe_pc[26]\); - - \r.x.rstate_RNICOF62[0]\ : MX2C - port map(A => N_3395, B => \xc_result[4]\, S => \rstate[0]\, - Y => \wdata[4]\); - - \r.m.y_RNO_3[11]\ : OR3A - port map(A => \y_2[11]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[11]\); - - \r.x.data_0_RNO[29]\ : OR3 - port map(A => \dco_m_1[125]\, B => \data_0_m[29]\, C => - \data_0_1_4[18]\, Y => \data_0_1[29]\); - - \r.e.op1_RNI3VNF[17]\ : NOR2A - port map(A => \un17_casaen_0_0\, B => \op1[17]\, Y => - \op1_i_m[17]\); - - \r.w.s.y_RNO[4]\ : MX2 - port map(A => \y_1[4]\, B => \result[4]\, S => N_481_0, Y - => N_3768); - - \r.f.pc_RNO_6[20]\ : MX2 - port map(A => \fpc[20]\, B => \eaddress[20]\, S => jump_0, - Y => N_4063); - - \r.a.et_RNILF8A\ : NOR2A - port map(A => et_1, B => \inst_2[21]\, Y => - illegal_inst_7_iv_2_0_a5_5_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I23_P0N : AO1A - port map(A => ldbp1_3, B => \op1[22]\, C => \data_0_0[22]\, - Y => N464); - - un6_ex_add_res_d0_ADD_33x33_fast_I85_Y : AO13 - port map(A => N406, B => \un1_iu0_6[4]\, C => \data_0[4]\, - Y => N544_0); - - \r.e.op1_RNO[9]\ : MX2C - port map(A => \d_i[9]\, B => \d_i[10]\, S => N_227, Y => - \aop1[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I7_G0N : NOR3A - port map(A => \op1[6]\, B => ldbp1_0, C => \data_0[6]\, Y - => N415_0); - - \r.e.alucin\ : DFN1E0 - port map(D => N_6684_i_0, CLK => lclk_c, E => holdn, Q => - alucin); - - un6_ex_add_res_d1_ADD_33x33_fast_I173_Y : AO1B - port map(A => N584_0, B => N577_0, C => N576, Y => N642_0); - - \r.a.ctrl.pc[24]\ : DFN1E0 - port map(D => \dpc[24]\, CLK => lclk_c, E => holdn, Q => - \pc_3[24]\); - - \r.x.y[22]\ : DFN1E0 - port map(D => \y[22]\, CLK => lclk_c, E => holdn, Q => - \y_2[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I205_Y : OR2B - port map(A => N610_0, B => I205_un1_Y, Y => N676); - - \r.w.s.icc_RNO[1]\ : AO1B - port map(A => icc_1_sqmuxa, B => \icc_0[1]\, C => - \icc_1_iv_0[1]\, Y => \icc_1[1]\); - - \r.d.inst_0_RNIVB391[25]\ : MX2C - port map(A => N_3348, B => N_3351, S => \inst_0[25]\, Y => - branch_1); - - \r.f.pc_RNO[13]\ : OR3C - port map(A => \tmp_m[13]\, B => \pc_1_iv_1[13]\, C => - \un6_fe_npc_m[11]\, Y => \pc_1[13]\); - - \r.e.shcnt_RNI6SQUK[1]\ : MX2C - port map(A => \shiftin_14[9]\, B => \shiftin_14[7]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[7]\); - - \r.e.op1_RNIU2NF[30]\ : OR2A - port map(A => un17_casaen_0, B => \op1[30]\, Y => - \op1_RNIU2NF[30]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I95_Y\ : NOR2B - port map(A => N460_0, B => N456, Y => N515); - - \r.e.cwp[2]\ : DFN1E0 - port map(D => \cwp_3[2]\, CLK => lclk_c, E => holdn, Q => - \cwp_2[2]\); - - \r.m.ctrl.rd_RNIMI7Q[1]\ : XNOR2 - port map(A => \inst_0_RNI1JUM[1]\, B => \rd_0[1]\, Y => - un1_de_ren1_1_1_i_0); - - \r.a.rsel1_RNI5LB[0]\ : OR2 - port map(A => \rsel1[0]\, B => \rsel1[1]\, Y => d11_0_a5_0); - - \r.e.op2_RNIVEOP[15]\ : MX2 - port map(A => \op2[15]\, B => N_4262, S => ldbp2_1, Y => - \un1_iu0_5[81]\); - - \r.e.aluop_RNIB31O6[0]\ : MX2C - port map(A => N_3590, B => N_3654, S => \aluop_1[0]\, Y => - \logicout[31]\); - - \r.e.aluop_0_RNIUOID1[1]\ : XOR3 - port map(A => \un1_iu0_6[15]\, B => \aluop_0[1]\, C => - \un1_iu0_5[81]\, Y => N_6883); - - \r.f.pc_RNIU2F8F[5]\ : MX2 - port map(A => \fpc[5]\, B => \eaddress[5]\, S => jump, Y - => N_4048); - - \r.e.aluop_RNI0IA98[2]\ : OA1C - port map(A => edata_1_sqmuxa, B => \bpdata[9]\, C => - \bpdata_i_m_2[1]\, Y => \edata2_iv_2[25]\); - - \r.e.ldbp2_RNIHA2632\ : OR3C - port map(A => \aluresult_1_iv_7[4]\, B => - \shiftin_17_m_0[4]\, C => \un6_ex_add_res_m[5]\, Y => - \aluresult[4]\); - - \r.d.cwp_RNO_0[0]\ : MX2 - port map(A => \ncwp[0]\, B => N_4218, S => un1_wcwp, Y => - N_4227); - - \r.e.invop2_0_RNI74UFN2\ : MX2C - port map(A => \un6_ex_add_res_s2[27]\, B => - \un6_ex_add_res_s0[27]\, S => invop2_0, Y => N_6658); - - \r.f.pc_RNO_0[25]\ : NAND2 - port map(A => \tmp[25]\, B => un2_rstn_5_0, Y => - \tmp_m[25]\); - - \r.a.ctrl.inst_RNI9S0E[23]\ : OR2 - port map(A => \inst_1[23]\, B => \inst[22]\, Y => N_202); - - \comb.branch_address.tmp_ADD_30x30_fast_I48_Y_0_o3\ : AO1 - port map(A => N416_2, B => N412, C => N415, Y => N465); - - \r.e.jmpl_RNITN6O_2\ : NOR3 - port map(A => jmpl, B => aluresult_1_sqmuxa_0_0, C => - \ex_shcnt_1[0]\, Y => aluresult_1_sqmuxa_0); - - \r.a.ctrl.pc[4]\ : DFN1E0 - port map(D => \dpc[4]\, CLK => lclk_c, E => holdn, Q => - \pc_0[4]\); - - \r.f.pc_RNIMOOJK1[3]\ : OA1C - port map(A => \fpc[3]\, B => rst, C => - \un6_ex_add_res_m_1[4]\, Y => \npc_iv_1[3]\); - - \r.a.ctrl.pc_RNIP7E2C[13]\ : MX2 - port map(A => \pc[13]\, B => N_3890, S => ex_bpmiss_1, Y - => \fe_pc[13]\); - - \r.e.op1_RNIO2CR1[22]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[22]\, Y => - \ex_op1_i_m[22]\); - - un37_ra_I_1 : AND2 - port map(A => \cwp_0[0]\, B => \inst_0_RNI4VUM[4]\, Y => - \DWACT_ADD_CI_0_TMP_0[0]\); - - \r.e.op2_RNO_6[16]\ : OR2B - port map(A => data2(16), B => d25, Y => \rfo_m_i[48]\); - - \r.e.aluop_0_RNI63A66[0]\ : OR2B - port map(A => \logicout[17]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[17]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I105_Y : OR2 - port map(A => I105_un1_Y, B => N502, Y => N568); - - \r.e.shcnt_RNITM6M[1]\ : MX2C - port map(A => \shcnt[1]\, B => N_3305, S => ldbp2_0, Y => - \ex_shcnt_1_i_0[1]\); - - \r.e.op2_RNO_6[5]\ : OR2B - port map(A => data2(5), B => d25_0, Y => \rfo_m_i[37]\); - - \r.w.s.y[9]\ : DFN1E0 - port map(D => N_3773, CLK => lclk_c, E => N_6922_i, Q => - \y[9]\); - - \r.e.op2_RNI8ROP[27]\ : MX2 - port map(A => \op2[27]\, B => N_4274, S => ldbp2_2, Y => - \un1_iu0_5[93]\); - - \r.e.invop2_0_RNI9V5MH\ : MX2C - port map(A => \un6_ex_add_res_s2[11]\, B => - \un6_ex_add_res_s0[11]\, S => invop2_0, Y => N_6630); - - \r.w.s.wim_RNIKR4N2[7]\ : MX2 - port map(A => \wim[7]\, B => \result_0[7]\, S => - wim_1_sqmuxa, Y => \wim_1[7]\); - - \r.f.pc_RNO[10]\ : OR3C - port map(A => \tmp_m[10]\, B => \pc_1_iv_1[10]\, C => - \un6_fe_npc_m[8]\, Y => \pc_1[10]\); - - \r.m.y_RNO_4[17]\ : OR3A - port map(A => \y_2[17]\, B => wy_3, C => wy_1_0_0, Y => - \y_m[17]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I139_Y : AO1 - port map(A => N540, B => N537_0, C => N536_0, Y => N602); - - \comb.branch_address.tmp_ADD_30x30_fast_I234_Y_1\ : AOI1B - port map(A => N518, B => N511, C => ADD_30x30_fast_I234_Y_0, - Y => ADD_30x30_fast_I234_Y_1); - - wovf_exc_0_sqmuxa_RNO_0 : MX2C - port map(A => N_3722, B => N_3723, S => \ncwp_3[1]\, Y => - N_3724); - - \r.e.su_RNIR2OL5\ : OA1A - port map(A => esu, B => aluresult_11_sqmuxa, C => - \aluresult_1_iv_1[7]\, Y => \aluresult_1_iv_3[7]\); - - \r.a.imm_RNO[19]\ : MX2 - port map(A => \inst_0[9]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[137]\); - - \r.e.ctrl.inst[26]\ : DFN1E0 - port map(D => \inst_2[26]\, CLK => lclk_c, E => holdn, Q - => \inst_1[26]\); - - \r.x.ctrl.tt_RNID10R[4]\ : MX2C - port map(A => \result[4]\, B => \tt_0[4]\, S => tt_i, Y => - N_3323); - - \r.x.ctrl.rd[7]\ : DFN1E0 - port map(D => \rd_0[7]\, CLK => lclk_c, E => holdn, Q => - \rd_2[7]\); - - \r.m.y_RNO[18]\ : AO1C - port map(A => y14_0, B => \logicout[18]\, C => - \y_iv_0_2[18]\, Y => \y_0[18]\); - - \r.e.shcnt_RNI178JO[1]\ : MX2C - port map(A => \shiftin_14[17]\, B => \shiftin_14[15]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[15]\); - - \r.x.result_RNIOO5H2[7]\ : NOR2 - port map(A => cwp_1_sqmuxa_0, B => \result_0[7]\, Y => - \result_i_m[7]\); - - \r.e.op1_RNO[10]\ : MX2C - port map(A => \d_i[10]\, B => \d_i[11]\, S => N_227, Y => - \aop1[10]\); - - \r.e.invop2_RNIDSAME2\ : MX2C - port map(A => \un6_ex_add_res_s2[25]\, B => - \un6_ex_add_res_s0[25]\, S => invop2, Y => N_6571); - - un6_ex_add_res_d2_ADD_33x33_fast_I203_un1_Y : NOR3C - port map(A => N541, B => N545_0, C => N614_2, Y => - I203_un1_Y_0); - - \r.x.annul_all_RNILS0QF\ : MX2 - port map(A => ps_1, B => s_1_iv, S => su2, Y => \su_0\); - - \r.e.op2_RNI4JOP[25]\ : MX2 - port map(A => \op2[25]\, B => N_4272, S => ldbp2_2, Y => - \un1_iu0_5[91]\); - - \r.e.op1_RNO[4]\ : MX2B - port map(A => \d[4]\, B => \d_i_0[5]\, S => N_227, Y => - N_167); - - un6_ex_add_res_d2_ADD_33x33_fast_I272_un1_Y : OR3C - port map(A => N667_1, B => N616_1, C => N651, Y => - I272_un1_Y_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I245_Y : OR2 - port map(A => N660, B => I245_un1_Y_0, Y => N802); - - \r.e.aluop_2_RNI6K413[1]\ : MX2C - port map(A => N_3540, B => \logicout_3[13]\, S => - \aluop_2[1]\, Y => N_3572); - - \r.e.shleft_1_RNIILIM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \op1_RNID1VH[19]\, S - => shleft_1, Y => \shiftin_5[50]\); - - \r.e.op1_RNITUPM7[3]\ : OR2B - port map(A => \edata2_0_iv_0[3]\, B => \bpdata_i_m[3]\, Y - => edata2_0_iv(3)); - - \r.m.y[28]\ : DFN1E0 - port map(D => \y_1[28]\, CLK => lclk_c, E => holdn, Q => - \y[28]\); - - \r.m.result_RNIKDAI[29]\ : NOR3C - port map(A => \result_m_0[29]\, B => \cpi_m_0[381]\, C => - \result_m_0_0[29]\, Y => \d_iv_1[29]\); - - \r.e.invop2\ : DFN1E0 - port map(D => N_6680, CLK => lclk_c, E => holdn, Q => - invop2); - - \r.m.y_RNISHO71[15]\ : OR2B - port map(A => \y[15]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I60_Y : NOR2B - port map(A => N449_1, B => N446_0, Y => N519_1); - - \r.e.op2_RNO_5[7]\ : AOI1B - port map(A => \result[7]\, B => d31_0, C => \imm_m_i[7]\, Y - => \d_1_iv_0[7]\); - - \r.e.op1_RNIBE3RB[20]\ : NOR2 - port map(A => \edata2_0_iv_1[20]\, B => \bpdata_i_m_1[4]\, - Y => edata2_0_iv(20)); - - \r.x.ctrl.pc_RNIH1M9[11]\ : MX2 - port map(A => \pc_0[11]\, B => \pc_2[11]\, S => \npc[1]\, Y - => N_3222); - - \r.x.data_0_RNO_3[0]\ : OR2B - port map(A => N_3455, B => data_0_2_16, Y => \dco_m_i[112]\); - - \r.w.s.y[27]\ : DFN1E0 - port map(D => N_172, CLK => lclk_c, E => holdn, Q => - \y[27]\); - - \r.e.aluop_0_RNI5B2T2[1]\ : MX2C - port map(A => \logicout_4[17]\, B => N_6877, S => - N_6866_i_0, Y => N_3640); - - \r.x.result_RNIVB435[3]\ : NOR2 - port map(A => \bpdata[3]\, B => N_3703_i, Y => - \bpdata_i_m_1[3]\); - - \r.x.ctrl.inst_RNITM3O1[30]\ : NOR2B - port map(A => y15, B => y6, Y => cwp_1_sqmuxa); - - \r.e.ctrl.pc_RNISR011[8]\ : OR2B - port map(A => \pc_2[8]\, B => jmpl_4, Y => \cpi_m[153]\); - - \r.d.inst_0_RNO[6]\ : NOR2B - port map(A => rst, B => N_4606, Y => \inst_0_RNO[6]\); - - \r.x.result_RNI0NED[17]\ : MX2 - port map(A => \result_0[17]\, B => \data_0[17]\, S => ld_0, - Y => \un1_p0_6[369]\); - - \r.w.result_RNIBTIF[9]\ : NOR2B - port map(A => \cpi_m_0[361]\, B => \result_m_0[9]\, Y => - \d_iv_0[9]\); - - \r.a.rsel1_0_RNIC7LJ2[2]\ : OR2B - port map(A => data1(22), B => d11_0, Y => \rfo_m[22]\); - - \r.f.pc_RNO_3[26]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[26]\, C => - \xc_trap_address_m[26]\, Y => \pc_1_iv_0[26]\); - - \r.e.aluop_RNIQ4RF4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[25]\, Y => - \aluop_RNIQ4RF4[1]\); - - \r.d.inst_0_RNI2423_0[23]\ : NOR2 - port map(A => \inst_0_0[23]\, B => \inst_0_0[21]\, Y => - N_3518_1); - - \r.e.op2_RNO_3[5]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[5]\, Y - => \aluresult_m_i[5]\); - - \r.e.aluop_0_RNI9NOH[1]\ : OR2A - port map(A => aluresult_8_sqmuxa_1, B => - aluresult_9_sqmuxa_1, Y => aluresult_8_sqmuxa_i); - - \r.x.data_0_RNO_3[2]\ : OA1A - port map(A => \data_0[2]\, B => ld_0_0, C => \dco_m_i[106]\, - Y => \data_0_1_1_iv_0[2]\); - - \r.e.shleft_RNIKOJ03\ : MX2 - port map(A => \shiftin_5[59]\, B => \shiftin_5[43]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[43]\); - - \r.f.pc_RNO_4[17]\ : MX2 - port map(A => I_91, B => N_4060, S => bpmiss_1_i_0_0, Y => - \pc_4[17]\); - - \r.e.aluop_RNITMRR[1]\ : OR2B - port map(A => \un1_iu0_5[90]\, B => \aluop_3[1]\, Y => - N_246); - - \r.e.op1_RNO[30]\ : MX2C - port map(A => \d_i[30]\, B => \d_i[31]\, S => N_227, Y => - \aop1[30]\); - - \r.a.ctrl.pc[23]\ : DFN1E0 - port map(D => \dpc[23]\, CLK => lclk_c, E => holdn, Q => - \pc_3[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I95_un1_Y : OR2B - port map(A => N496, B => N493_0, Y => I95_un1_Y_1); - - \r.m.y_RNO_0[13]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[13]\, C => \y_m_0[13]\, - Y => \y_iv_1[13]\); - - \r.e.shleft_0_RNIBRBG\ : NOR2A - port map(A => \un1_iu0_6[7]\, B => shleft_0, Y => - shleft_0_RNIBRBG); - - \r.e.op2_RNO_4[25]\ : OA1A - port map(A => \maddress[25]\, B => d27_0, C => - \cpi_m_i[377]\, Y => \d_1_iv_1[25]\); - - \r.a.rsel2_RNICN4B[0]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[352]\, - Y => \cpi_m_i[352]\); - - \r.m.y_RNO_2[25]\ : OR2B - port map(A => \y_2[25]\, B => y08, Y => \y_m_0[25]\); - - \r.e.ctrl.inst[30]\ : DFN1E0 - port map(D => \inst[30]\, CLK => lclk_c, E => holdn, Q => - \inst_2[30]\); - - \r.d.inst_0_RNI6846[21]\ : NOR2A - port map(A => N_142, B => \inst_0_0[21]\, Y => N_145); - - \r.a.rfa1[5]\ : DFN1E0 - port map(D => \un3_de_ren1[96]\, CLK => lclk_c, E => holdn, - Q => \rfa1[5]\); - - \r.x.data_0[2]\ : DFN1E0 - port map(D => \data_0_1[2]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[2]\); - - \r.e.aluop_RNIFV0I6[0]\ : MX2C - port map(A => N_3572, B => N_3636, S => \aluop_1[0]\, Y => - \logicout[13]\); - - \r.x.ctrl.pc_RNISP971[22]\ : MX2C - port map(A => \un1_p0_6[374]\, B => \pc_0[22]\, S => - s_3_sqmuxa_0, Y => N_3413); - - \r.e.op2_RNI6NOP[26]\ : MX2 - port map(A => \op2[26]\, B => N_4273, S => ldbp2_2, Y => - \un1_iu0_5[92]\); - - \r.f.pc_RNO[15]\ : OR3C - port map(A => \tmp_m[15]\, B => \pc_1_iv_1[15]\, C => - \un6_fe_npc_m[13]\, Y => \pc_1[15]\); - - \r.e.op1_RNI3IC972[2]\ : OR3C - port map(A => \op1_m_i[2]\, B => \d_1_iv_3[2]\, C => - \aluresult_m_i[2]\, Y => \d_1[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I239_Y_1\ : OR3 - port map(A => I154_un1_Y, B => N520, C => I204_un1_Y, Y => - ADD_30x30_fast_I239_Y_1); - - \r.a.ctrl.inst[9]\ : DFN1E0 - port map(D => \inst_0[9]\, CLK => lclk_c, E => holdn, Q => - \inst[9]\); - - \r.w.s.wim_RNIP2QK5[2]\ : NOR3B - port map(A => \ex_op2_m[2]\, B => \wim_m[2]\, C => - \aluresult_4[1]\, Y => \aluresult_2_iv_2[2]\); - - \r.f.pc_RNO[31]\ : OR3C - port map(A => \tmp_m[31]\, B => \pc_1_iv_1[31]\, C => - \un6_fe_npc_m[29]\, Y => \pc_1[31]\); - - \r.x.data_0_RNO[6]\ : OR3C - port map(A => \dco_m_i[118]\, B => \data_0_1_1_iv_1[6]\, C - => \dco_m_i[102]\, Y => \data_0_1[6]\); - - \r.e.op2_RNIR2OP[21]\ : MX2A - port map(A => \op2[21]\, B => N_4268_i, S => ldbp2_1, Y => - \un1_iu0_5[87]\); - - \r.m.ctrl.cnt[1]\ : DFN1E0 - port map(D => \cnt[1]\, CLK => lclk_c, E => holdn, Q => - \cnt_1[1]\); - - \comb.v.x.data_0_1_1_iv_RNO_0[19]\ : AO1A - port map(A => ld_0_0, B => \data_0[19]\, C => - \dco_m_0[115]\, Y => \data_0_1_1_iv_0[19]\); - - \r.e.op1[22]\ : DFN1E0 - port map(D => \aop1[22]\, CLK => lclk_c, E => holdn, Q => - \op1[22]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I87_Y_0 : AO1 - port map(A => N407_2, B => N403_0, C => N406, Y => N546); - - un6_ex_add_res_d0_ADD_33x33_fast_I163_un1_Y : NAND2 - port map(A => N567, B => N574, Y => I163_un1_Y); - - \r.a.ctrl.inst_RNI5H3O1_0[19]\ : NOR3A - port map(A => N_226, B => N_203, C => N_204, Y => N_227_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I306_Y_0 : XNOR3 - port map(A => \un1_iu0_6[15]\, B => \op2[15]\, C => N796, Y - => \un6_ex_add_res_s1_i[16]\); - - \r.x.dci.size[0]\ : DFN1E0 - port map(D => \size_1[0]\, CLK => lclk_c, E => holdn, Q => - \size_2[0]\); - - \r.e.shcnt_RNO[2]\ : XOR2 - port map(A => \d_1[2]\, B => N_208, Y => N_268_i_i_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I319_Y_0 : AX1E - port map(A => N_51_i_1, B => ADD_33x33_fast_I262_Y_0_0, C - => ADD_33x33_fast_I319_Y_0_0, Y => - \un6_ex_add_res_s1[29]\); - - \r.e.op2_RNIRFMB1[13]\ : OR2A - port map(A => \un1_iu0_5[79]\, B => \un1_iu0_6[13]\, Y => - \logicout_4[13]\); - - \r.m.ctrl.inst_RNI2Q1S[22]\ : NOR2 - port map(A => inst_3_2_1, B => inst_3_2_0, Y => inst_3_2); - - \r.e.shleft_0_RNIGNBD1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[4]\, S => - shleft_0, Y => \shiftin_5[35]\); - - \r.e.aluop_1_RNIH0ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[12]\, B => \aluop_1[1]\, C => - \un1_iu0_5[78]\, Y => N_6919); - - \r.m.icc_RNO_8[2]\ : NOR2 - port map(A => \logicout[1]\, B => \logicout[20]\, Y => - icc_0_sqmuxa_1_14); - - \r.e.op2_RNO_2[22]\ : NOR3C - port map(A => \d_1_iv_1[22]\, B => \d_1_iv_0[22]\, C => - \rfo_m_i[54]\, Y => \d_1_iv_3[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I273_un1_Y_0 : NOR2B - port map(A => N552_0, B => N669_0, Y => - ADD_33x33_fast_I273_un1_Y_0_0); - - \r.e.op2_RNO_3[8]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[8]\, Y - => \aluresult_m_i[8]\); - - \r.m.irqen2_RNIF63C\ : NOR3C - port map(A => irqen, B => irqen2, C => un6_annul_1, Y => - un6_annul_2); - - \r.e.aluop_2[1]\ : DFN1E0 - port map(D => \aluop[1]\, CLK => lclk_c, E => holdn, Q => - \aluop_2[1]\); - - \r.m.y_RNO[13]\ : OR3C - port map(A => \y_iv_1[13]\, B => \y_iv_0[13]\, C => - \logicout_m[13]\, Y => \y_1[13]\); - - \r.e.ldbp2_RNIJDFUV3\ : OR3C - port map(A => \aluresult_1_iv_7[15]\, B => - \shiftin_17_m_0[15]\, C => \un6_ex_add_res_m[16]\, Y => - \aluresult[15]\); - - \r.w.s.icc[3]\ : DFN1E0 - port map(D => \icc_1[3]\, CLK => lclk_c, E => holdn, Q => - \icc_0[3]\); - - \r.m.result[1]\ : DFN1E0 - port map(D => \eres2[1]\, CLK => lclk_c, E => holdn, Q => - \maddress[1]\); - - \r.d.inst_0_0_0_RNI35KP[21]\ : NOR3B - port map(A => bicc_hold_1, B => N_3736_2, C => un1_inst, Y - => bicc_hold_3); - - \comb.branch_address.tmp_ADD_30x30_fast_I185_Y\ : AO1 - port map(A => N555, B => N358, C => N554, Y => N614); - - \comb.irq_trap.un5_irl_1\ : NOR2B - port map(A => irl_0(2), B => irl_0(3), Y => un5_irl_1); - - \r.f.pc_RNO_6[26]\ : MX2 - port map(A => \fpc[26]\, B => \eaddress[26]\, S => jump_0, - Y => N_4069); - - \r.e.op2_RNIQ2VD4[6]\ : AOI1B - port map(A => \un1_iu0_5[72]\, B => aluresult_7_sqmuxa_0_0, - C => \aluresult_1_iv_0[6]\, Y => \aluresult_1_iv_1[6]\); - - \r.a.imm_RNO[18]\ : MX2 - port map(A => \inst_0[8]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[136]\); - - \r.e.shleft_0_RNIL1PK3\ : MX2 - port map(A => \shiftin_5[61]\, B => \shiftin_5[45]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[45]\); - - \r.a.ctrl.inst[18]\ : DFN1E0 - port map(D => \inst_0[18]\, CLK => lclk_c, E => holdn, Q - => \inst_1[18]\); - - \r.e.ldbp1_4\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_4); - - \r.w.result[11]\ : DFN1E0 - port map(D => \wdata[11]\, CLK => lclk_c, E => holdn, Q => - \result[11]\); - - \r.e.op1_RNIV3P873[10]\ : NOR3C - port map(A => \op1_m_0[10]\, B => \d_iv_2[10]\, C => - \aluresult_m_0[10]\, Y => \d_i[10]\); - - \r.e.op1_RNIQ94M7[7]\ : OR2B - port map(A => \edata2_0_iv_0[7]\, B => \bpdata_i_m[7]\, Y - => edata2_0_iv(7)); - - \r.m.y_RNO[17]\ : AO1C - port map(A => y14_0, B => \logicout[17]\, C => \y_iv_2[17]\, - Y => \y_1[17]\); - - \r.f.pc_RNO_3[19]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[19]\, C => - \xc_trap_address_m[19]\, Y => \pc_1_iv_0[19]\); - - \r.e.shcnt_RNIQQVS4[3]\ : MX2 - port map(A => \shiftin_8[19]\, B => \shiftin_8[11]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[11]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I98_Y : NOR2A - port map(A => N495, B => N_50, Y => N561_i); - - \r.a.ctrl.inst[20]\ : DFN1E0 - port map(D => \inst_0[20]\, CLK => lclk_c, E => holdn, Q - => \inst_2[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I23_G0N : NOR3A - port map(A => \op1[22]\, B => ldbp1_4, C => \data_0_0[22]\, - Y => N463_2); - - \r.e.ldbp2_RNIFKJUB1\ : MX2 - port map(A => \un6_ex_add_res_s1[14]\, B => N_6633, S => - ldbp2_3, Y => \eaddress[13]\); - - \r.e.op1_RNO[27]\ : MX2C - port map(A => \d_i[27]\, B => \d_i[28]\, S => N_227, Y => - \aop1[27]\); - - \r.e.bp_RNI77CD_0\ : NOR3A - port map(A => bp_0, B => annul, C => \inst_2[28]\, Y => - N_475); - - \r.x.laddr_RNIH68NE1_0[0]\ : NOR3C - port map(A => \me_laddr_2[1]\, B => \me_laddr_2[0]\, C => - rdata_3_sqmuxa_2, Y => rdata_3_sqmuxa); - - \r.m.result_RNO[16]\ : MX2 - port map(A => \aluresult[16]\, B => \op1[16]\, S => - un17_casaen_0_1, Y => \eres2[16]\); - - \r.e.ctrl.pc[7]\ : DFN1E0 - port map(D => \pc_3[7]\, CLK => lclk_c, E => holdn, Q => - \pc_0[7]\); - - \r.x.result_RNITK6E[25]\ : MX2 - port map(A => \result_0[25]\, B => \data_0[25]\, S => ld_4, - Y => \un1_p0_6[377]\); - - \r.e.op2_RNO_4[8]\ : OA1A - port map(A => \maddress[8]\, B => d27_0, C => - \cpi_m_i[360]\, Y => \d_1_iv_1[8]\); - - \r.x.rstate_RNIJEP02[0]\ : MX2C - port map(A => N_3409, B => \xc_result[18]\, S => - \rstate[0]\, Y => \wdata[18]\); - - \r.w.s.y_RNO_1[14]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y[14]\, Y => N_382); - - \r.a.ctrl.inst_RNICC1E[19]\ : OR2B - port map(A => \inst_2[20]\, B => \inst_2[19]\, Y => N_487); - - un6_ex_add_res_d1_ADD_33x33_fast_I172_Y : NOR2B - port map(A => N583_1, B => N575_1, Y => N641_0); - - \r.e.op1_RNIF1UB[4]\ : OR2A - port map(A => un17_casaen_0, B => \op1[4]\, Y => - \op1_i_m[4]\); - - \r.a.ctrl.inst_RNIE1HC6[5]\ : NOR3B - port map(A => un1_illegal_inst33_0, B => - privileged_inst_0_sqmuxa, C => illegal_inst33, Y => - un1_illegal_inst33_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I316_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[25]\, B => \op2[25]\, Y => - ADD_33x33_fast_I316_Y_0_0); - - \r.d.inst_0_RNINSV2[31]\ : NOR2A - port map(A => \inst_0[31]\, B => annul_1, Y => ldcheck1_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I120_Y : NOR2 - port map(A => N521_0, B => N517_1, Y => N583_2); - - \r.w.s.y_RNO[7]\ : MX2 - port map(A => \y_2[7]\, B => \result_0[7]\, S => N_481_0, Y - => N_3771); - - \r.f.pc_RNO_4[27]\ : MX2 - port map(A => I_173, B => N_4070, S => bpmiss_1_i_0, Y => - \pc_4[27]\); - - \r.e.op2_RNO[5]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[5]\, Y => N_289); - - \r.e.aluop_RNIOVP04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[1]\, Y => - \bpdata_i_m_2[1]\); - - \r.d.inst_0_RNI12TD1[0]\ : NOR2 - port map(A => \inst_0_RNI0FUM[0]\, B => \inst_0_RNI1JUM[1]\, - Y => un1_rs1_0); - - \r.a.rsel1_0_RNI83LJ2[2]\ : OR2B - port map(A => data1(11), B => d11, Y => \rfo_m[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I35_Y\ : NOR2B - port map(A => N437_1, B => N434_1, Y => N452); - - \r.m.ctrl.rd_RNIVH85C[5]\ : OR3C - port map(A => un1_de_ren1_1_5_i_0, B => wreg_5, C => - un1_de_ren1_1_6_i_0, Y => wreg_1); - - \r.e.ctrl.rd_RNI1KQS1[3]\ : XA1A - port map(A => \un3_de_ren1[94]\, B => \rd[3]\, C => - un2_rs1_1_6_i_0, Y => wreg_2_3); - - \r.m.y[18]\ : DFN1E0 - port map(D => \y_0[18]\, CLK => lclk_c, E => holdn, Q => - \y_1[18]\); - - \r.e.shcnt_RNIO57AL[1]\ : MX2C - port map(A => \shiftin_14[8]\, B => \shiftin_14[6]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[6]\); - - \r.e.op2_RNO_7[24]\ : OR2A - port map(A => \maddress[24]\, B => d27, Y => - \result_m_i[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I151_Y : AO1 - port map(A => N552, B => N549_0, C => N548_1, Y => N614_1); - - \r.f.pc_RNO_0[30]\ : NAND2 - port map(A => \tmp[30]\, B => \un2_rstn_5\, Y => - \tmp_m[30]\); - - \r.e.ctrl.rd_RNIUA09B1[6]\ : NOR3A - port map(A => rfe_2, B => wreg_1_8, C => un1_de_ren1_2, Y - => rfe); - - \comb.branch_address.tmp_ADD_30x30_fast_I163_Y\ : NOR2A - port map(A => N529, B => N537, Y => N589); - - \r.e.ctrl.inst_RNILDSK2[26]\ : AO1 - port map(A => ex_bpmiss_1_0_a5_0, B => N_328, C => N_427, Y - => ex_bpmiss_1_0_0); - - \r.x.npc_RNIUS311[0]\ : MX2C - port map(A => N_3228, B => N_3258, S => \npc[0]\, Y => - \xc_result[17]\); - - \r.e.ctrl.pc_RNIAHK11[15]\ : OR2B - port map(A => \pc_2[15]\, B => jmpl_4, Y => \cpi_m[160]\); - - \r.a.ctrl.inst_RNIVB1K1[30]\ : AO1A - port map(A => N_219, B => \inst[30]\, C => N_478, Y => - N_236); - - un6_ex_add_res_d0_ADD_33x33_fast_I131_Y : AO1 - port map(A => N532, B => N529_0, C => N528_0, Y => N594_0); - - \comb.cwp_ctrl.ncwp_3_I_5\ : NOR2A - port map(A => \cwp[1]\, B => \inst_0[19]\, Y => - \DWACT_ADD_CI_0_g_array_0_1[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I62_Y : NOR2B - port map(A => N446_0, B => N443, Y => N521_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I303_Y_0_1 : XNOR2 - port map(A => \un1_iu0_6[12]\, B => \data_0_2[12]\, Y => - \un6_ex_add_res_s0_1[13]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0_a3_0_0\ : - NOR2A - port map(A => N437_1, B => N440_2, Y => - ADD_30x30_fast_I233_Y_0_a3_0); - - \r.e.ctrl.pc[4]\ : DFN1E0 - port map(D => \pc_0[4]\, CLK => lclk_c, E => holdn, Q => - \pc[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I165_un1_Y : AO1B - port map(A => ADD_33x33_fast_I113_Y_0_0, B => I113_un1_Y_i, - C => N569_1, Y => I165_un1_Y_0); - - \r.e.aluop_RNI5NNF[1]\ : OR2B - port map(A => \aluop_3[1]\, B => \aluop_1[0]\, Y => - logicout22_1); - - \r.m.icc_RNIVN961[3]\ : OR2A - port map(A => \icc[3]\, B => aluresult_11_sqmuxa, Y => - \icc_m[3]\); - - \r.a.imm_RNO[15]\ : MX2 - port map(A => \inst_0[5]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[133]\); - - \r.x.ctrl.pc_RNIP3531[8]\ : MX2C - port map(A => \un1_p0_6[360]\, B => \pc_0[8]\, S => - s_3_sqmuxa_0, Y => N_3399); - - \r.e.shleft_1_RNIKBV81\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[6]\, S => - shleft_1, Y => \shiftin_5[37]\); - - \r.w.result_RNIIJQL[30]\ : AOI1B - port map(A => \un1_p0_6[382]\, B => d14_0, C => - \result_m_0_0[30]\, Y => \d_iv_0[30]\); - - \r.m.result[23]\ : DFN1E0 - port map(D => \eres2[23]\, CLK => lclk_c, E => holdn, Q => - \maddress[23]\); - - \r.m.ctrl.pc_RNIC1N9[25]\ : MX2 - port map(A => \pc_3[25]\, B => \pc_0[25]\, S => \npc[1]\, Y - => N_3266); - - \r.m.y_RNIVPO71[27]\ : OR2B - port map(A => \y_0[27]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[27]\); - - \r.m.ctrl.pc_RNI4PL9[30]\ : MX2 - port map(A => \pc_3[30]\, B => \pc[30]\, S => \npc[1]\, Y - => N_3271); - - un6_ex_add_res_d1_ADD_33x33_fast_I137_Y : AO1B - port map(A => N538_1, B => N535_0, C => - ADD_33x33_fast_I137_Y_0_0, Y => N600_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I132_Y_0\ : MAJ3 - port map(A => \dpc[7]\, B => \inst_0[5]\, C => N370, Y => - ADD_30x30_fast_I132_Y_0); - - \r.m.result_0_RNI7MR8[3]\ : OR2A - port map(A => \maddress_0[3]\, B => d27, Y => - \result_m_i[3]\); - - \r.e.shcnt_RNI7P6DK[1]\ : MX2C - port map(A => \shiftin_14[6]\, B => \shiftin_14[4]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[4]\); - - \r.e.aluop_0_RNI6HIK5[0]\ : OR2B - port map(A => \logicout[30]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I187_Y : AO1A - port map(A => N591_2, B => N598_0, C => N590_2, Y => N656_1); - - \r.e.ldbp2_0_RNIG2K3Q4\ : MX2C - port map(A => \un6_ex_add_res_s1_i[30]\, B => N_6576, S => - ldbp2_0, Y => \eaddress[29]\); - - \r.d.inst_0_0_0_RNI2OAFO2[12]\ : MX2 - port map(A => data_0_0_12, B => \un1_p0_6_0[51]\, S => - mexc_1_sqmuxa_1_0, Y => N_4612); - - \r.x.data_0_RNIIJ9E[28]\ : XOR2 - port map(A => \data_0[28]\, B => invop2_1, Y => N_4275); - - \r.x.ctrl.annul_RNI2ROB_0\ : OR2 - port map(A => annul_0, B => \un1_p0_6[349]\, Y => xc_wreg9); - - \r.m.result_RNIK2TD3[25]\ : NOR3C - port map(A => \d_iv_0[25]\, B => \result_m_0[25]\, C => - \rfo_m[25]\, Y => \d_iv_2[25]\); - - \r.a.rfa2[7]\ : DFN1 - port map(D => \raddr2[7]\, CLK => lclk_c, Q => \rfa2[7]\); - - \r.f.pc_RNO[26]\ : OR3C - port map(A => \tmp_m[26]\, B => \pc_1_iv_1[26]\, C => - \un6_fe_npc_m[24]\, Y => \pc_1[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I14_G0N : OA1 - port map(A => \op1[13]\, B => ldbp1_1, C => \data_0[13]\, Y - => N436_2); - - \r.d.inst_0_RNO_0[23]\ : MX2 - port map(A => data_0_0_23, B => \inst_0_0[23]\, S => - inull_RNIFV6VG2_0, Y => N_4623); - - un6_ex_add_res_d0_ADD_33x33_fast_I184_Y : NOR2B - port map(A => N595_1, B => N587_0, Y => N653_0); - - \r.e.aluop_0_RNI3LVG[1]\ : XOR3 - port map(A => \un1_iu0_6[0]\, B => \aluop_0[1]\, C => - \op2_RNI59C6[0]\, Y => N_6865); - - \r.a.ctrl.pc[21]\ : DFN1E0 - port map(D => \dpc[21]\, CLK => lclk_c, E => holdn, Q => - \pc[21]\); - - \r.m.y_RNO_3[19]\ : OR3A - port map(A => \y_2[19]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[19]\); - - \r.d.inull_RNII4QJ1\ : MX2C - port map(A => annul_2_0, B => N_3034, S => N_3033_1_i, Y - => \hold_pc_7\); - - \r.e.jmpl_RNICLDQ81\ : AND2 - port map(A => \shiftin_17_m[7]\, B => \aluresult_1_iv_7[6]\, - Y => \aluresult_1_iv_8[6]\); - - \r.d.inst_0_RNO_0[25]\ : MX2 - port map(A => data_0_2_25, B => \inst_0[25]\, S => - inull_RNIFV6VG2_0, Y => N_4625); - - un6_ex_add_res_d2_ADD_33x33_fast_I174_Y : OR2B - port map(A => N585_1, B => N577_1, Y => N643); - - \r.m.ctrl.cnt_RNIEEAK6[0]\ : OA1B - port map(A => trap_0_sqmuxa_4, B => un1_trap_0_sqmuxa_1_0, - C => trap_1_sqmuxa_1, Y => trap_1_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I284_Y_0\ : XNOR2 - port map(A => N704, B => ADD_30x30_fast_I284_Y_0_0, Y => - \tmp[26]\); - - \r.d.pc[29]\ : DFN1 - port map(D => \pc_RNO[29]\, CLK => lclk_c, Q => \dpc[29]\); - - \r.d.inst_0_RNI66J4[23]\ : OR3A - port map(A => \inst_0_0[24]\, B => \inst_0_0[22]\, C => - \inst_0_0[23]\, Y => un3_op2); - - \r.e.shleft_0_RNIL3CQ1\ : MX2A - port map(A => \shiftin_5[23]\, B => shleft_0_RNIBRBG, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[7]\); - - \r.a.rsel2_0_RNIFA4D_2[0]\ : NOR2A - port map(A => d26, B => un17_casaen_0_2, Y => - un14_casaen_s0_0_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I244_Y\ : NOR3 - port map(A => I244_un1_Y_0, B => N590, C => I214_un1_Y, Y - => N718_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I41_Y : MAJ3 - port map(A => \data_0[26]\, B => \un1_iu0_6[26]\, C => - N472_1, Y => N500_0); - - \r.w.s.tba_RNIVT0JF[1]\ : NOR3C - port map(A => \aluresult_1_iv_2[13]\, B => \tba_m[1]\, C - => \aluresult_1_iv_4[13]\, Y => \aluresult_1_iv_5[13]\); - - \r.e.ldbp2_RNIDO5E7\ : MX2C - port map(A => \un6_ex_add_res_s1_i[5]\, B => N_6644, S => - ldbp2_3, Y => \eaddress[4]\); - - \r.e.alusel_RNO_1[1]\ : NOR2A - port map(A => \inst[22]\, B => N_602, Y => N_341); - - \r.m.y_RNO_1[13]\ : AOI1B - port map(A => \y[13]\, B => y08, C => \y_m[14]\, Y => - \y_iv_0[13]\); - - \r.e.aluop_2_RNIUCAS1[1]\ : MX2C - port map(A => N_3528, B => \logicout_3[1]\, S => - \aluop_2[1]\, Y => N_3560); - - \comb.branch_address.tmp_ADD_30x30_fast_I9_P0N\ : OR2 - port map(A => \inst_0[9]\, B => \dpc[11]\, Y => N386); - - \r.f.pc_RNO[4]\ : OR3C - port map(A => \tmp_m[4]\, B => \pc_1_iv_1[4]\, C => - \un6_fe_npc_m[2]\, Y => \pc_1[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I164_Y : NOR2B - port map(A => N575_0, B => N567, Y => N633); - - \r.x.ctrl.pc_RNINMF8[5]\ : MX2 - port map(A => \pc_3[5]\, B => \pc[5]\, S => \npc[1]\, Y => - N_3216); - - \r.e.shcnt_RNIKVP67[3]\ : MX2 - port map(A => \shiftin_8[43]\, B => \shiftin_8[35]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[35]\); - - \r.a.ctrl.inst_RNIFO1E_0[23]\ : NOR2A - port map(A => \inst_1[23]\, B => \inst_2[19]\, Y => - inst_11_0); - - un6_fe_npc_I_139 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \fe_pc[23]\, Y => - \DWACT_FINC_E[16]\); - - \r.f.pc_RNI5Q6S64[7]\ : NOR2B - port map(A => \un6_fe_npc_m[5]\, B => - \xc_trap_address_m[7]\, Y => \npc_iv_2[7]\); - - \r.w.s.wim[6]\ : DFN1E0 - port map(D => \wim_1[6]\, CLK => lclk_c, E => holdn, Q => - \wim[6]\); - - \r.x.data_0_RNO_0[17]\ : OR3 - port map(A => \dco_m_0[113]\, B => \data_0_m[17]\, C => - \data_0_1_1[16]\, Y => \data_0_1_1_iv_1[17]\); - - \r.e.op1_RNIL04F[3]\ : OR2B - port map(A => \op1[3]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[3]\); - - \r.m.icc_RNISEJF3[1]\ : NOR3C - port map(A => \ex_op2_m[21]\, B => aluresult_8_sqmuxa_i, C - => \icc_m[1]\, Y => \aluresult_1_iv_2[21]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I155_un1_Y : OR3C - port map(A => N493, B => N497, C => N566, Y => I155_un1_Y_0); - - \r.m.y_RNI4JC92[23]\ : AOI1B - port map(A => \y[23]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[168]\, Y => \aluresult_1_iv_1[23]\); - - \r.m.y[29]\ : DFN1E0 - port map(D => \y_1[29]\, CLK => lclk_c, E => holdn, Q => - \y[29]\); - - \r.e.op2_RNO_2[15]\ : NOR3C - port map(A => \d_1_iv_1[15]\, B => \d_1_iv_0[15]\, C => - \rfo_m_i[47]\, Y => \d_1_iv_3[15]\); - - un6_fe_npc_I_91 : XOR2 - port map(A => N_88, B => \fe_pc[17]\, Y => I_91); - - \r.m.result_RNI3HB4[6]\ : OR2B - port map(A => d13, B => \maddress[6]\, Y => \result_m_0[6]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I181_Y\ : NOR2A - port map(A => N555, B => N547, Y => N607); - - \r.x.data_0[16]\ : DFN1E0 - port map(D => \data_0_1[16]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[16]\); - - \r.x.ctrl.trap_RNI5VL8\ : NOR2 - port map(A => mexc_0, B => trap_5, Y => \un1_p0_6[349]\); - - \r.m.y_RNO_1[28]\ : OR2B - port map(A => \y[29]\, B => mulstep_1, Y => \y_m[29]\); - - \r.e.ctrl.rd_RNIQP6H1[7]\ : XOR2 - port map(A => \rd_1[7]\, B => un1_reg, Y => - \rd_RNIQP6H1[7]\); - - \r.e.ldbp2_1_RNIHE5NT4\ : OR2B - port map(A => \aluresult_1_iv_8[17]\, B => - \un6_ex_add_res_m[18]\, Y => \aluresult[17]\); - - \r.e.aluop_RNIHA56M[0]\ : AOI1B - port map(A => \logicout[18]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_5[18]\, Y => \aluresult_1_iv_6[18]\); - - \r.f.pc_RNO_7[29]\ : MX2 - port map(A => \fpc[29]\, B => \tba[17]\, S => rstate_6314_d, - Y => \xc_trap_address[29]\); - - \r.f.pc[14]\ : DFN1E0 - port map(D => N_8_0_i_0, CLK => lclk_c, E => holdn, Q => - \fpc[14]\); - - \r.a.imm_RNO[20]\ : MX2 - port map(A => \inst_0[10]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[138]\); - - \r.e.op2_RNO_8[8]\ : OR3B - port map(A => d29_0_0, B => \imm[8]\, C => \rsel2_0[0]\, Y - => \imm_m_i[8]\); - - \r.x.result[3]\ : DFN1E0 - port map(D => \maddress[3]\, CLK => lclk_c, E => holdn, Q - => \result_0[3]\); - - \r.d.annul_RNIEC3SK5\ : OR2B - port map(A => I_52, B => annul_RNIVCQHS1, Y => N_31); - - \r.x.rstate_RNIMCA72[0]\ : MX2C - port map(A => N_3407, B => \xc_result[16]\, S => - \rstate[0]\, Y => \wdata[16]\); - - \r.x.rstate[1]\ : DFN1 - port map(D => N_6323s, CLK => lclk_c, Q => \rstate[1]\); - - \r.a.rsel2_RNO_0[1]\ : NOR2A - port map(A => wreg_1, B => wreg_1_8, Y => N_3950); - - \r.e.ctrl.rd_RNIO9OBC[6]\ : XA1A - port map(A => \rd_0[6]\, B => \un3_de_ren1[105]\, C => - wreg_1_6, Y => wreg_1_8); - - \r.a.ticc_RNO_0\ : NOR3A - port map(A => ticc_exception_1, B => annul_1, C => un1_inst, - Y => ticc_exception_0_a3_1); - - \r.x.ctrl.rd[4]\ : DFN1E0 - port map(D => \rd[4]\, CLK => lclk_c, E => holdn, Q => - \rd_2[4]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I86_un1_Y\ : OR3A - port map(A => N451, B => N440_2, C => N443_2, Y => - I86_un1_Y); - - un6_ex_add_res_d0_ADD_33x33_fast_I309_Y_0 : XNOR3 - port map(A => \data_0_0[18]\, B => \un1_iu0_6[18]\, C => - N790, Y => \un6_ex_add_res_s0[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I87_Y_0 : AO1 - port map(A => N407, B => N403_1, C => N406_0, Y => N546_2); - - \r.x.ctrl.rd_RNI6SGO[2]\ : NOR2B - port map(A => \rd_3[2]\, B => N_6357, Y => waddr(2)); - - un6_ex_add_res_d2_ADD_33x33_fast_I137_Y_0 : MIN3 - port map(A => \data_0[9]\, B => \un1_iu0_6[9]\, C => N421_1, - Y => ADD_33x33_fast_I137_Y_0_1); - - \comb.irq_trap.un5_irl_0\ : NOR2B - port map(A => irl_0(0), B => irl_0(1), Y => un5_irl_0); - - \r.e.shcnt_RNI5AQVR[1]\ : MX2C - port map(A => \shiftin_14[27]\, B => \shiftin_14[25]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[25]\); - - \r.a.ctrl.inst_RNISS231[30]\ : NOR3B - port map(A => \inst_1[24]\, B => N_205, C => \inst[30]\, Y - => N_478); - - \r.x.rstate_0_RNIHG622[0]\ : MX2C - port map(A => N_3399, B => \xc_result[8]\, S => - \rstate_0[0]\, Y => \wdata[8]\); - - \r.f.pc_RNO_0[17]\ : NAND2 - port map(A => \tmp[17]\, B => \un2_rstn_5\, Y => - \tmp_m[17]\); - - \r.w.s.y_RNO[6]\ : MX2 - port map(A => \y_2[6]\, B => \result_0[6]\, S => N_481_0, Y - => N_3770); - - \r.w.result_RNIOI3C[1]\ : AOI1B - port map(A => \result[1]\, B => d31, C => \imm_m_i[1]\, Y - => \d_1_iv_0[1]\); - - \r.m.result_RNIFPR73[14]\ : NOR3C - port map(A => \d_iv_0[14]\, B => \result_m_0[14]\, C => - \rfo_m[14]\, Y => \d_iv_2[14]\); - - \r.m.y_RNO_4[11]\ : OR2B - port map(A => \y[12]\, B => mulstep_1, Y => \y_m[12]\); - - \r.m.y_RNO_2[9]\ : OR2B - port map(A => \y_1[9]\, B => y08, Y => \y_m_0[9]\); - - \r.x.data_0_RNO_4[6]\ : OR2A - port map(A => \data_0[6]\, B => ld_0_0, Y => - \data_0_m_i[6]\); - - \r.d.pc[5]\ : DFN1 - port map(D => \pc_RNO[5]\, CLK => lclk_c, Q => \dpc[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I111_Y : AO1 - port map(A => N512_0, B => N509, C => N508, Y => N574_1); - - \r.m.y_RNO_0[14]\ : AOI1B - port map(A => wy_1_0, B => \y[14]\, C => N_387, Y => - \y_iv_0_1[14]\); - - \r.e.op1_RNIKJO8[8]\ : MX2 - port map(A => \op1[8]\, B => \data_0[8]\, S => ldbp1_1, Y - => \un1_iu0_6[8]\); - - \r.e.shleft_0_RNIQCT43\ : MX2 - port map(A => \shiftin_5[47]\, B => \shiftin_5[31]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[31]\); - - \r.x.result[27]\ : DFN1E0 - port map(D => \maddress[27]\, CLK => lclk_c, E => holdn, Q - => \result_0[27]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I140_Y : NOR2B - port map(A => N541_0, B => N537_0, Y => N603); - - \comb.branch_address.tmp_ADD_30x30_fast_I100_Y\ : AO1B - port map(A => N465, B => N462, C => ADD_30x30_fast_I100_Y_0, - Y => N520); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_Y_0 : AOI1 - port map(A => N500_0, B => N497, C => N496_1, Y => - ADD_33x33_fast_I261_Y_0_0); - - \r.x.result_RNI4NED[19]\ : MX2 - port map(A => \result_0[19]\, B => \data_0[19]\, S => ld_0, - Y => \un1_p0_6[371]\); - - \r.d.pc[14]\ : DFN1 - port map(D => \pc_RNO[14]\, CLK => lclk_c, Q => \dpc[14]\); - - \r.m.ctrl.rd_RNICD3O[7]\ : XNOR2 - port map(A => \rd_0[7]\, B => \un3_de_ren1[98]\, Y => - un2_rs1_2_7_i_0); - - \r.e.op1_RNO_0[31]\ : XNOR2 - port map(A => \icco[3]\, B => \icco[1]\, Y => - \aop1_1_i[31]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I223_un1_Y : OR2B - port map(A => N652_1, B => N637_1, Y => I223_un1_Y_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I138_Y_0 : OA1 - port map(A => \data_0[6]\, B => \un1_iu0_6[6]\, C => N419_0, - Y => ADD_33x33_fast_I138_Y_0_0); - - \r.f.pc[11]\ : DFN1E0 - port map(D => N_15, CLK => lclk_c, E => holdn, Q => - \fpc[11]\); - - \r.e.aluop_2_RNIK5713[1]\ : MX2C - port map(A => N_3545, B => \logicout_3[18]\, S => - \aluop_2[1]\, Y => N_3577); - - \r.f.pc_RNI1T85[10]\ : OR2A - port map(A => \fpc[10]\, B => rst, Y => \pc_m[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I265_Y_1 : NOR3B - port map(A => I167_un1_Y_i, B => I223_un1_Y_i, C => N570_1, - Y => ADD_33x33_fast_I265_Y_1_1); - - \r.w.s.y_RNO[14]\ : NOR3 - port map(A => N_383, B => N_382, C => N_384, Y => N_153); - - \r.e.op2_RNO_4[10]\ : OR2B - port map(A => \op1[10]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[10]\); - - \r.x.ctrl.tt_RNO[5]\ : MX2B - port map(A => un1_trap_0_sqmuxa_5, B => N_4209, S => - N_4210_i_0, Y => \tt2[5]\); - - \r.e.jmpl_RNI221OS_0\ : OR2B - port map(A => \shiftin_17[25]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[25]\); - - \r.x.data_0_RNI7RS8[5]\ : XOR2 - port map(A => \data_0[5]\, B => invop2_1, Y => N_4252); - - \r.d.inst_0_RNIU3LJ[26]\ : MX2C - port map(A => N_3349, B => N_3350, S => \inst_0[26]\, Y => - N_3351); - - \r.m.ctrl.pc_RNIPPGF[12]\ : MX2 - port map(A => \pc_3[12]\, B => \pc[12]\, S => \npc_0[1]\, Y - => N_3253); - - \r.m.y_RNO_3[30]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[30]\, C => \y_m[30]\, Y - => \y_iv_1[30]\); - - \r.a.rfa1_RNI5OLJ1[6]\ : MX2 - port map(A => \un3_de_ren1[97]\, B => \rfa1[6]\, S => holdn, - Y => raddr1(6)); - - \r.a.ctrl.inst_RNI3D3H1[21]\ : OR3 - port map(A => N_201, B => alusel24_2, C => N_205, Y => - N_458); - - \r.e.aluop_0_RNIOL6R[1]\ : XOR3 - port map(A => \un1_iu0_6[7]\, B => \aluop_0[1]\, C => - \un1_iu0_5[73]\, Y => N_6871); - - \r.m.y_RNO_1[5]\ : OR2B - port map(A => \y_0[6]\, B => mulstep_1, Y => \y_m[6]\); - - \r.e.op2_RNO_5[23]\ : OR2B - port map(A => \result_0[23]\, B => d31, Y => - \result_m_i[23]\); - - \r.e.op2_RNO_7[21]\ : OR3B - port map(A => d29_0, B => \imm[21]\, C => \rsel2[0]\, Y => - \imm_m_i[21]\); - - \r.d.pv\ : DFN1E0 - port map(D => pv_6, CLK => lclk_c, E => holdn, Q => pv); - - \r.m.y_RNO[3]\ : AO1C - port map(A => y14_0, B => \logicout[3]\, C => \y_iv_2[3]\, - Y => \y_0[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I322_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[31]\, B => \data_0_0[31]\, Y => - \un6_ex_add_res_s2_1[32]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I320_Y_0 : XNOR2 - port map(A => N768_1, B => ADD_33x33_fast_I320_Y_0_0, Y => - \un6_ex_add_res_s1_i[30]\); - - \r.m.nalign\ : DFN1E0 - port map(D => un12_ex_add_res, CLK => lclk_c, E => holdn, Q - => nalign); - - \r.m.ctrl.pc_RNI8IIF[19]\ : MX2 - port map(A => \pc_2[19]\, B => \pc_3[19]\, S => \npc_1[1]\, - Y => N_3260); - - \comb.branch_address.tmp_ADD_30x30_fast_I78_Y\ : AO13 - port map(A => \inst_0_RNI4VUM[4]\, B => \dpc[6]\, C => N367, - Y => N495_1); - - \r.e.shcnt_RNI7PA7A[2]\ : MX2C - port map(A => \shiftin_11[10]\, B => \shiftin_11[6]\, S => - \ex_shcnt_1_i[2]\, Y => \shiftin_14[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I167_un1_Y : OR2B - port map(A => N578, B => N571_2, Y => I167_un1_Y_i); - - \r.x.data_0_RNO[0]\ : AO1B - port map(A => N_3456, B => data_0_0_0, C => - \data_0_1_1_iv_2[0]\, Y => \data_0_1[0]\); - - \r.m.ctrl.tt[0]\ : DFN1E0 - port map(D => \tt_2[0]\, CLK => lclk_c, E => holdn, Q => - \tt_0[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I267_Y : NAND2 - port map(A => I267_un1_Y_1, B => ADD_33x33_fast_I267_Y_0_1, - Y => N780_0); - - \r.m.y[19]\ : DFN1E0 - port map(D => \y_1[19]\, CLK => lclk_c, E => holdn, Q => - \y_0[19]\); - - \r.e.shcnt_RNISCPM3[3]\ : MX2 - port map(A => \shiftin_8[9]\, B => \shiftin_8[1]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[1]\); - - \r.e.cwp[0]\ : DFN1E0 - port map(D => \cwp_2[0]\, CLK => lclk_c, E => holdn, Q => - \cwp_1[0]\); - - \r.m.ctrl.rd[1]\ : DFN1E0 - port map(D => \rd[1]\, CLK => lclk_c, E => holdn, Q => - \rd_0[1]\); - - \r.e.op1_RNI1NNF[15]\ : NOR2A - port map(A => un17_casaen_0_2, B => \op1[15]\, Y => - \op1_i_m[15]\); - - \r.e.op2_RNO_8[31]\ : OR3B - port map(A => d29_0, B => \imm[31]\, C => \rsel2[0]\, Y => - \imm_m_i[31]\); - - \r.w.s.y_RNO[10]\ : MX2 - port map(A => \y_2[10]\, B => \result[10]\, S => N_481, Y - => N_3774); - - \r.w.s.y[4]\ : DFN1E0 - port map(D => N_3768, CLK => lclk_c, E => N_6922_i, Q => - \y_2[4]\); - - \r.f.pc_RNO_1[15]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[15]\, C => - \pc_1_iv_0[15]\, Y => \pc_1_iv_1[15]\); - - \r.x.result[12]\ : DFN1E0 - port map(D => \maddress[12]\, CLK => lclk_c, E => holdn, Q - => \result[12]\); - - \r.m.dci.SIGNED_RNO_0\ : NOR3A - port map(A => \inst_1[22]\, B => \inst[24]\, C => - \inst_1[21]\, Y => SIGNED_2_1); - - \r.x.data_0[23]\ : DFN1E0 - port map(D => \data_0_1[23]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[23]\); - - \r.x.data_0_RNO[22]\ : OR3 - port map(A => \dco_m_0[118]\, B => \data_0_m[22]\, C => - \data_0_1_4[18]\, Y => \data_0_1[22]\); - - \r.x.ctrl.inst_RNI2JBD2[30]\ : OR3C - port map(A => y11, B => y15, C => xc_wreg_0_sqmuxa, Y => - s_2_sqmuxa); - - \r.a.su\ : DFN1E0 - port map(D => \su_0\, CLK => lclk_c, E => holdn, Q => su_1); - - \r.e.op2_RNIIGNB1_0[26]\ : OR2 - port map(A => \un1_iu0_6[26]\, B => \un1_iu0_5[92]\, Y => - \logicout_3[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I13_G0N : OAI1 - port map(A => \op1[12]\, B => ldbp1_1, C => \data_0_2[12]\, - Y => N433_1); - - \r.e.op2_RNO_3[12]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[12]\, Y - => \aluresult_m_i[12]\); - - \r.m.y_RNO_3[16]\ : OR3A - port map(A => \y_2[16]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[16]\); - - \r.e.op1_RNI8HFC[4]\ : OR2B - port map(A => \op1[4]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[4]\); - - \r.d.pv_RNICUFKC\ : OR2B - port map(A => un25_exbpmiss, B => un9_rabpmiss, Y => - inhibit_current); - - \r.x.ctrl.inst[23]\ : DFN1E0 - port map(D => \inst_2[23]\, CLK => lclk_c, E => holdn, Q - => \inst[23]\); - - \r.e.jmpl_RNI4I9RO1\ : NOR3C - port map(A => \aluresult_0_iv_6[27]\, B => - \logicout_m_0[27]\, C => \shiftin_17_m[28]\, Y => - \aluresult_0_iv_8[27]\); - - \r.d.pc_RNO[6]\ : MX2 - port map(A => \fpc[6]\, B => \dpc[6]\, S => N_6763_i_0, Y - => \pc_RNO[6]\); - - \r.x.ctrl.inst_RNIJD0E[21]\ : OR2 - port map(A => \inst_0[21]\, B => \inst[20]\, Y => y11_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I42_Y\ : MAJ3 - port map(A => \dpc[24]\, B => \inst_0_0_0_RNI9O79[21]\, C - => N421_2, Y => N459); - - \r.f.pc[16]\ : DFN1E0 - port map(D => \pc_1[16]\, CLK => lclk_c, E => holdn, Q => - \fpc[16]\); - - \r.e.op2_RNO_3[30]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[30]\, Y => - \aluresult_m_i[30]\); - - \r.m.icc_RNO_21[2]\ : NOR2 - port map(A => \logicout[7]\, B => \logicout[8]\, Y => - icc_0_sqmuxa_1_2); - - \r.m.y_RNIB4K91[5]\ : OR2B - port map(A => \y_2[5]\, B => aluresult_10_sqmuxa_0, Y => - \y_m_1[5]\); - - \r.m.y[24]\ : DFN1E0 - port map(D => \y_1[24]\, CLK => lclk_c, E => holdn, Q => - \y[24]\); - - \r.e.op2_RNIVFHN1[25]\ : OR2B - port map(A => \un1_iu0_5[91]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[25]\); - - \r.e.jmpl_RNILTD2M_0\ : OR2B - port map(A => \shiftin_17[6]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[6]\); - - \r.a.rsel1_RNIKM1954[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[16]\, Y - => \aluresult_m_0[16]\); - - \r.f.pc_RNO_6[18]\ : MX2 - port map(A => \fpc[18]\, B => \eaddress[18]\, S => jump_0, - Y => N_4061); - - \r.e.jmpl_RNIHBBLM\ : OR2B - port map(A => \shiftin_17[8]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[8]\); - - \r.x.data_0[9]\ : DFN1E0 - port map(D => \data_0_1[9]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[9]\); - - \r.m.ctrl.rd_RNIE9FK1[1]\ : NOR2B - port map(A => un1_de_ren1_1_1_i_0, B => un1_de_ren1_1_2_i_0, - Y => wreg_1_7); - - \r.f.pc_RNO[17]\ : OR3C - port map(A => \tmp_m[17]\, B => \pc_1_iv_1[17]\, C => - \un6_fe_npc_m[15]\, Y => \pc_1[17]\); - - \r.w.s.icc_RNO_1[2]\ : OR2B - port map(A => icc_0_sqmuxa, B => \icc_2[2]\, Y => - \icc_m_0[2]\); - - \r.d.inull_RNIOQ1F\ : AO1A - port map(A => N_85, B => \inull\, C => hold_pc_2_m, Y => - N_3014); - - un6_ex_add_res_d2_ADD_33x33_fast_I206_Y_0_o3_1 : OR2B - port map(A => ADD_33x33_fast_I206_Y_0_o3_1_0_1, B => N_57, - Y => N616_1); - - \r.w.result_RNIDHB4[6]\ : OR3C - port map(A => N_484_0, B => \rsel1[2]\, C => \result[6]\, Y - => \result_m_0_0[6]\); - - \r.e.ldbp2_RNIJJR273\ : OR3C - port map(A => \aluresult_1_iv_8[11]\, B => - \shiftin_17_m_0[11]\, C => \un6_ex_add_res_m[12]\, Y => - \aluresult[11]\); - - \r.e.jmpl_RNIBKNAF1\ : AOI1B - port map(A => \shiftin_17[14]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[13]\, Y => \aluresult_1_iv_7[13]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I58_Y : OA1A - port map(A => \data_0_0[18]\, B => \un1_iu0_6[18]\, C => - N449, Y => N517); - - \r.x.rstate_RNIOP1U_0[1]\ : OR2A - port map(A => rst, B => \xc_exception_1_0\, Y => - un2_rstn_5_0_i); - - \r.e.ctrl.trap_RNO_1\ : NOR3 - port map(A => trap_1, B => ticc, C => \tt_4[3]\, Y => - trap_4_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I264_Y_1 : AO1D - port map(A => N650, B => N635_1, C => - ADD_33x33_fast_I264_Y_0, Y => ADD_33x33_fast_I264_Y_1_1); - - \r.x.laddr[1]\ : DFN1E0 - port map(D => \maddress[1]\, CLK => lclk_c, E => holdn, Q - => \laddr[1]\); - - \r.w.result_RNI7O5J[23]\ : AOI1B - port map(A => \un1_p0_6[375]\, B => d14_0, C => - \result_m_0_0[23]\, Y => \d_iv_0[23]\); - - \r.m.y_RNO[8]\ : OR3C - port map(A => \y_iv_1[8]\, B => \y_iv_0[8]\, C => - \logicout_m[8]\, Y => \y_1[8]\); - - \r.m.y[26]\ : DFN1E0 - port map(D => \y_0[26]\, CLK => lclk_c, E => holdn, Q => - \y_1[26]\); - - \r.f.pc_RNO[28]\ : OR3C - port map(A => \tmp_m[28]\, B => \pc_1_iv_1[28]\, C => - \un6_fe_npc_m[26]\, Y => \pc_1[28]\); - - \r.x.rstate_0_RNI0CHE2[0]\ : MX2C - port map(A => N_3401, B => \xc_result[10]\, S => - \rstate_0[0]\, Y => \wdata[10]\); - - \r.m.y[4]\ : DFN1E0 - port map(D => \y_0[4]\, CLK => lclk_c, E => holdn, Q => - \y[4]\); - - \r.m.ctrl.trap_RNIMABN\ : NOR3A - port map(A => pv_1, B => trap_2, C => werr_1, Y => - trap_0_sqmuxa_7_1); - - un6_fe_npc_I_59 : AND3 - port map(A => \fe_pc[8]\, B => \fe_pc[9]\, C => \fe_pc[10]\, - Y => \DWACT_FINC_E[5]\); - - un54_ra_I_14 : XOR2 - port map(A => \ncwp[2]\, B => \DWACT_ADD_CI_0_g_array_1[0]\, - Y => I_14); - - \r.e.ldbp2_1_RNIEL6QV1\ : NAND2 - port map(A => \eaddress[8]\, B => un2_rstn_3_0, Y => - \un6_ex_add_res_m_1[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I4_G0N : OA1 - port map(A => \op1[3]\, B => ldbp1_4, C => \data_0[3]\, Y - => N406_1); - - \r.x.ctrl.pc_RNIVHN9[27]\ : MX2 - port map(A => \pc_3[27]\, B => \pc[27]\, S => \npc[1]\, Y - => N_3238); - - un6_ex_add_res_d2_ADD_33x33_fast_I132_Y : OR2B - port map(A => N533_1, B => N529_2, Y => N595); - - \r.a.ctrl.inst_RNI1D4C3[21]\ : NOR3 - port map(A => invop2_0_1_i_0, B => N_334, C => N_236, Y => - N_6680); - - \r.m.ctrl.pc[4]\ : DFN1E0 - port map(D => \pc[4]\, CLK => lclk_c, E => holdn, Q => - \pc_3[4]\); - - \r.m.y_RNO_3[28]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[28]\, C => \y_m[28]\, Y - => \y_iv_1[28]\); - - \r.m.result_RNO[22]\ : MX2 - port map(A => \aluresult[22]\, B => \op1[22]\, S => - un17_casaen_0_1, Y => \eres2[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I270_Y_0_o3 : AO1B - port map(A => N_71_1, B => N790_1, C => N514_2, Y => N786); - - \r.m.y_RNO_1[14]\ : AOI1B - port map(A => \y_0[14]\, B => y08_0, C => N_389, Y => - \y_iv_0_0[14]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I45_un1_Y : AND2 - port map(A => N466, B => N470, Y => I45_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I243_Y : OR2 - port map(A => N656_0, B => I243_un1_Y_0, Y => N796); - - \r.e.shleft_RNIEMRJ\ : OR2A - port map(A => \un1_iu0_6[16]\, B => shleft, Y => - \shiftin_5[16]\); - - \r.e.ldbp2_RNI3M6LS1\ : OR2B - port map(A => \aluresult_2_iv_7[1]\, B => - \aluresult_2_iv_6[1]\, Y => \aluresult[1]\); - - \r.e.op2_RNIQFHN1[16]\ : OR2B - port map(A => \un1_iu0_5[82]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I175_un1_Y : NOR2B - port map(A => N586, B => N579_0, Y => I175_un1_Y); - - \r.x.data_0_RNI8F9E[12]\ : XOR2 - port map(A => \data_0_2[12]\, B => invop2_0, Y => N_4259); - - \r.d.annul_RNIP2H4\ : NOR2 - port map(A => annul_1, B => call_hold5, Y => - hold_pc_1_sqmuxa); - - \r.a.rsel2_0_RNIVADN[0]\ : NOR2B - port map(A => \result_m_i[3]\, B => \cpi_m_i[355]\, Y => - \d_1_iv_1[3]\); - - \r.e.op1_RNIQ69G[15]\ : OR2B - port map(A => \op1[15]\, B => un14_casaen_s1_0, Y => - \op1_m_0[15]\); - - \r.e.op1_RNI2RNF[16]\ : NOR2A - port map(A => un17_casaen_0_1, B => \op1[16]\, Y => - \op1_i_m[16]\); - - \r.d.inull_RNI7S342\ : NOR2A - port map(A => annul_next_2_sqmuxa_1_2, B => N_108, Y => - annul_next_2_sqmuxa_1_3); - - \r.e.op1_RNIPA4U1[7]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[7]\, C => - \ex_op1_i_m[7]\, Y => \edata2_0_iv_0[7]\); - - \r.m.ctrl.pc_RNIL9GF[10]\ : MX2 - port map(A => \pc_2[10]\, B => \pc_3[10]\, S => \npc_0[1]\, - Y => N_3251); - - \r.m.ctrl.inst[29]\ : DFN1E0 - port map(D => \inst_2[29]\, CLK => lclk_c, E => holdn, Q - => \inst_3[29]\); - - \r.e.op1_RNIBHFC[7]\ : OR2B - port map(A => \op1[7]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[7]\); - - \r.w.result[29]\ : DFN1E0 - port map(D => \wdata[29]\, CLK => lclk_c, E => holdn, Q => - \result[29]\); - - \r.x.data_0_RNO_0[6]\ : AO1B - port map(A => rdatav_0_1_0_iv_5_4, B => mcdo_m_0_20, C => - N_3455, Y => \dco_m_i[118]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I2_G0N : NOR3A - port map(A => \op1[1]\, B => ldbp1, C => \data_0[1]\, Y => - N400_2); - - \r.m.y_RNO_3[7]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[7]\, C => \y_m_1[7]\, Y - => \y_iv_1[7]\); - - \r.e.shcnt_RNI2B1C[0]\ : MX2C - port map(A => \shcnt[0]\, B => N_3304, S => ldbp2_3, Y => - \ex_shcnt_1[0]\); - - \r.e.ctrl.pc[19]\ : DFN1E0 - port map(D => \pc_3[19]\, CLK => lclk_c, E => holdn, Q => - \pc[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I29_P0N : OR2 - port map(A => \un1_iu0_6[28]\, B => \op2[28]\, Y => N482_0); - - \r.e.op1_RNIJB1JB[11]\ : NOR3 - port map(A => \edata2_0_iv_0[11]\, B => \bpdata_i_m[11]\, C - => \bpdata_i_m_2[3]\, Y => edata2_0_iv(11)); - - \r.m.y_RNIV8FM7[8]\ : AND2 - port map(A => \bpdata_m_2[0]\, B => \aluresult_1_iv_3[8]\, - Y => \aluresult_1_iv_5[8]\); - - \r.m.y_RNIID7CA[17]\ : NOR3C - port map(A => \aluresult_1_iv_1[17]\, B => - \aluresult_1_iv_0[17]\, C => \aluresult_1_iv_3[17]\, Y - => \aluresult_1_iv_4[17]\); - - un6_fe_npc_I_56 : XOR2 - port map(A => N_113, B => \fe_pc[12]\, Y => I_56); - - \r.a.rsel2_RNI9LB_0[1]\ : NOR2A - port map(A => \rsel2[1]\, B => \rsel2[2]\, Y => d28_0); - - \r.e.op2[15]\ : DFN1E0 - port map(D => N_299, CLK => lclk_c, E => holdn, Q => - \op2[15]\); - - \r.x.ctrl.pc_RNIPIIF[29]\ : MX2 - port map(A => \pc_2[29]\, B => \pc_0[29]\, S => \npc_1[1]\, - Y => N_3240); - - \comb.branch_address.tmp_ADD_30x30_fast_I217_Y\ : AO1 - port map(A => N610, B => N595_0, C => N594, Y => N723); - - \r.a.rsel2_1[0]\ : DFN1E0 - port map(D => N_3944, CLK => lclk_c, E => holdn, Q => - \rsel2_1[0]\); - - \r.m.y[22]\ : DFN1E0 - port map(D => \y_1[22]\, CLK => lclk_c, E => holdn, Q => - \y[22]\); - - \r.e.aluop_0_RNID9JD1[2]\ : XA1 - port map(A => \un1_iu0_5[92]\, B => \aluop_0[2]\, C => - \un1_iu0_6[26]\, Y => N_3553); - - \r.m.result_RNO[9]\ : MX2 - port map(A => \aluresult[9]\, B => \op1[9]\, S => - un17_casaen_0_1, Y => \eres2[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I204_un1_Y : NOR2B - port map(A => N616_1, B => N609, Y => I204_un1_Y_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I3_G0N : NOR2B - port map(A => \un1_iu0_6[2]\, B => \op2[2]\, Y => N403_1); - - \r.m.y_RNI0BC92[12]\ : AOI1B - port map(A => \y[12]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[157]\, Y => \aluresult_1_iv_1[12]\); - - \r.m.result[29]\ : DFN1E0 - port map(D => \eres2[29]\, CLK => lclk_c, E => holdn, Q => - \maddress[29]\); - - \r.w.s.tba_RNI1E424[12]\ : AND2 - port map(A => \aluresult_1_iv_1[24]\, B => \tba_m[12]\, Y - => \aluresult_1_iv_3[24]\); - - \r.e.shcnt_RNIKP4RT[1]\ : MX2B - port map(A => \shiftin_14[31]\, B => \shiftin_14[29]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[29]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I294_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[4]\, B => N614_2, Y => - \un6_ex_add_res_s2[4]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I5_P0N : OR2 - port map(A => \un1_iu0_6[4]\, B => \op2[4]\, Y => N410_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I16_G0N : NOR3A - port map(A => \op1[15]\, B => ldbp1_3, C => \data_0_2[15]\, - Y => N442); - - \r.a.rfa2[1]\ : DFN1E0 - port map(D => \inst_0_RNI1JUM[1]\, CLK => lclk_c, E => - holdn, Q => \rfa2[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I135_Y : AO1 - port map(A => N536_2, B => N533_1, C => N532_1, Y => N598_2); - - \r.a.ctrl.pc[31]\ : DFN1E0 - port map(D => \dpc[31]\, CLK => lclk_c, E => holdn, Q => - \pc_0[31]\); - - \r.x.result_RNIJK6E[20]\ : MX2 - port map(A => \result[20]\, B => \data_0_2[20]\, S => ld_4, - Y => \un1_p0_6[372]\); - - \r.e.aluop_RNIRJNA4[2]\ : OR2B - port map(A => \bpdata[9]\, B => aluresult_5_sqmuxa, Y => - \bpdata_m_0[9]\); - - \r.d.inst_0_RNI7DOH[29]\ : MX2C - port map(A => \inst_0[18]\, B => \inst_0[29]\, S => rs1mod, - Y => \rs1[4]\); - - \r.e.shleft_0_RNI15IP\ : OR2A - port map(A => \un1_iu0_6[17]\, B => shleft_0, Y => - \shiftin_5[17]\); - - \r.e.op2_RNO[3]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[3]\, Y => N_287); - - \r.e.ldbp2_RNIOFQ534\ : MX2C - port map(A => \un6_ex_add_res_s1_i[26]\, B => N_6657, S => - ldbp2_3, Y => \eaddress[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I182_Y_0_o3\ : AOI1 - port map(A => N610, B => N380, C => N379, Y => N608_i); - - \r.e.op1_RNILI8G[10]\ : OR2B - port map(A => \op1[10]\, B => un14_casaen_s1_0, Y => - \op1_m_0[10]\); - - \r.a.bp_RNO_0\ : OR2A - port map(A => not_valid, B => \un9_icc_check_bp\, Y => - bp_1_0); - - \r.d.cwp_RNO_1[2]\ : MX2 - port map(A => \cwp_0[2]\, B => \maddress[2]\, S => wcwp, Y - => N_4220); - - \r.m.y[14]\ : DFN1E0 - port map(D => \y_1[14]\, CLK => lclk_c, E => holdn, Q => - \y_0[14]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I269_Y_0 : AOI1B - port map(A => N660_0, B => N645_1, C => N644, Y => - ADD_33x33_fast_I269_Y_0_1); - - \r.e.op2_RNO_0[26]\ : OR3C - port map(A => \op1_m_i[26]\, B => \d_1_iv_3[26]\, C => - \aluresult_m_i[26]\, Y => \d_1[26]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I63_Y\ : OA1 - port map(A => \dpc[14]\, B => \inst_0[12]\, C => N392, Y - => N480); - - \r.m.ctrl.inst[21]\ : DFN1E0 - port map(D => \inst_1[21]\, CLK => lclk_c, E => holdn, Q - => \inst[21]\); - - \r.e.op2_RNI3OHN1[27]\ : OR2B - port map(A => \un1_iu0_5[93]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I265_Y_0_0\ : XOR2 - port map(A => \dpc[7]\, B => \inst_0[5]\, Y => - ADD_30x30_fast_I265_Y_0_0); - - \r.e.ctrl.pc_RNI1T8Q2[26]\ : AOI1 - port map(A => \pc[26]\, B => jmpl_0, C => \aluresult_4[1]\, - Y => \aluresult_1_iv_1[26]\); - - \r.a.imm_RNO[0]\ : NOR2B - port map(A => \inst_0_RNI0FUM[0]\, B => call_hold5, Y => - \un3_de_ren1[118]\); - - \r.w.s.icc_RNO[2]\ : AO1B - port map(A => icc_1_sqmuxa, B => \icc[2]\, C => - \icc_1_iv_0[2]\, Y => \icc_1[2]\); - - \r.a.imm[5]\ : DFN1E0 - port map(D => \un3_de_ren1[123]\, CLK => lclk_c, E => holdn, - Q => \imm[5]\); - - \r.w.result_RNIQJD4[28]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[28]\, - Y => \result_m_0[28]\); - - \r.m.y_RNO_4[19]\ : OR2B - port map(A => \y_0[20]\, B => mulstep_1, Y => \y_m_0[20]\); - - \r.e.op2_RNO_4[23]\ : OR2B - port map(A => \op1[23]\, B => un14_casaen_s1, Y => - \op1_m_i[23]\); - - \r.d.inst_0_RNI4VUM[4]\ : NOR2B - port map(A => \inst_0[4]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI4VUM[4]\); - - \r.m.y[16]\ : DFN1E0 - port map(D => \y_1[16]\, CLK => lclk_c, E => holdn, Q => - \y[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I58_Y\ : MAJ3 - port map(A => \dpc[16]\, B => \inst_0[14]\, C => N397_2, Y - => N475); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y_2 : AOI1B - port map(A => N568_0, B => N561, C => - ADD_33x33_fast_I260_Y_1, Y => ADD_33x33_fast_I260_Y_2); - - \r.f.pc_RNO_7[19]\ : MX2 - port map(A => \fpc[19]\, B => \tba[7]\, S => rstate_6314_d, - Y => \xc_trap_address[19]\); - - \r.a.ctrl.inst_RNIG5R8[7]\ : NOR2 - port map(A => \inst[7]\, B => \inst[9]\, Y => un29_casaen_3); - - \r.x.rstate_RNIRDFU5[1]\ : AOI1 - port map(A => rstate_4_2, B => rstate_6314_d_0, C => - et_RNI1BRF2, Y => \rstate_RNIRDFU5[1]\); - - \r.a.rsel1_RNIUKSMO6[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[25]\, Y - => \aluresult_m_0[25]\); - - \r.e.op2_RNI5SHN1[28]\ : OR2B - port map(A => \un1_iu0_5[94]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[28]\); - - \r.e.aluop_0_RNINA1T2[1]\ : MX2C - port map(A => \logicout_4[15]\, B => N_6883, S => - N_6866_i_0, Y => N_3638); - - \r.f.pc_RNI6QK32[10]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[10]\, Y => \xc_trap_address_m[10]\); - - \r.x.result_RNI52D25[4]\ : NOR2 - port map(A => \bpdata[4]\, B => N_3703_i, Y => - \bpdata_i_m_1[4]\); - - \r.x.ctrl.wicc_RNIVOQU_0\ : NOR2A - port map(A => icc_0_sqmuxa_1, B => \rstate_d[2]\, Y => - icc_0_sqmuxa); - - \r.x.ctrl.tt_RNO_0[2]\ : MX2C - port map(A => irl_0(2), B => \tt_2[2]\, S => tt_0_sqmuxa, Y - => N_4206); - - \r.m.ctrl.pc[29]\ : DFN1E0 - port map(D => \pc_0[29]\, CLK => lclk_c, E => holdn, Q => - \pc_3[29]\); - - \r.a.ctrl.inst_RNI9T2M3[25]\ : MX2C - port map(A => N_3341, B => N_3344, S => \inst_1[25]\, Y => - branch); - - \r.x.ctrl.inst_RNI2JBD2_0[30]\ : OR2B - port map(A => xc_wreg_0_sqmuxa, B => cwp_1_sqmuxa, Y => - cwp_1_sqmuxa_0); - - \r.e.jmpl_RNITN6O\ : NOR3A - port map(A => \ex_shcnt_1[0]\, B => jmpl, C => - aluresult_1_sqmuxa_0_0, Y => aluresult_2_sqmuxa); - - \r.x.result_RNITK5F5[15]\ : NOR2A - port map(A => \aluop_RNIGM3N1[2]\, B => \bpdata[15]\, Y => - \bpdata_i_m[15]\); - - \r.e.op1_RNO[15]\ : MX2C - port map(A => \d_i[15]\, B => \d_i[16]\, S => N_227_0, Y - => \aop1[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I159_un1_Y : OR2B - port map(A => N570_1, B => N563, Y => I159_un1_Y_0); - - \comb.irq_trap.op_gt.un2_irl_0_I_9\ : OR2A - port map(A => \pil[3]\, B => irl_0(3), Y => \ACT_LT4_E[8]\); - - \r.e.aluop_RNI50KR2[1]\ : MX2C - port map(A => N_3550, B => \logicout_3[23]\, S => - \aluop_3[1]\, Y => N_3582); - - \r.d.inst_0_RNO[16]\ : NOR2B - port map(A => rst, B => N_4616, Y => \inst_0_RNO[16]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I189_Y : AO1 - port map(A => N600_0, B => N593_1, C => N592_1, Y => N658); - - \r.m.ctrl.rett_RNITNQB\ : OR2 - port map(A => rett, B => rett_0, Y => rett_1_0); - - \r.e.op2_RNO_5[30]\ : AOI1B - port map(A => \result[30]\, B => d31_0, C => \imm_m_i[30]\, - Y => \d_1_iv_0[30]\); - - \r.d.annul_RNI0LULC\ : OR2 - port map(A => annul_1, B => inhibit_current, Y => - ctrl_annul_i_0_a2_0); - - \r.e.aluop_0_RNIDA0T2[1]\ : MX2C - port map(A => \logicout_4[22]\, B => N_6862, S => - N_6866_i_0, Y => N_3645); - - \comb.branch_address.tmp_ADD_30x30_fast_I281_Y_0_0\ : XOR2 - port map(A => \dpc[23]\, B => \un1_p0_6_0[60]\, Y => - ADD_30x30_fast_I281_Y_0_0); - - \r.f.pc_RNO_5[15]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[15]\, Y => \xc_trap_address_m[15]\); - - \r.x.ctrl.tt_RNO_0[0]\ : NOR2B - port map(A => tt_2_sqmuxa_1, B => trap_0_sqmuxa_7, Y => - N_4200_i_0); - - \r.m.y_RNO_2[3]\ : OR2B - port map(A => \y_1[3]\, B => y08, Y => \y_m_0[3]\); - - \r.a.nobp_RNIP6STQ\ : AO1A - port map(A => \ldlock_3_0\, B => \un9_icc_check_bp\, C => - \ldlock_2\, Y => ldlock); - - \r.e.op1[0]\ : DFN1E0 - port map(D => \aop1[0]\, CLK => lclk_c, E => holdn, Q => - \op1[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I211_un1_Y : OR2B - port map(A => N640_1, B => N625_0, Y => I211_un1_Y_0); - - \comb.op_mux.d_1_iv_RNO_4[29]\ : AOI1B - port map(A => \result[29]\, B => d31_0, C => \imm_m_i[29]\, - Y => \d_1_iv_0[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I242_Y_0\ : AND2 - port map(A => I242_un1_Y, B => N586_i, Y => - ADD_30x30_fast_I242_Y_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I221_Y\ : OR3 - port map(A => I176_un1_Y, B => N542, C => I221_un1_Y_0, Y - => N735); - - \r.e.jmpl_RNI772QP1\ : AOI1B - port map(A => \shiftin_17[31]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[30]\, Y => \aluresult_1_iv_8[30]\); - - \r.m.dci.asi[4]\ : DFN1E0 - port map(D => \asi[4]\, CLK => lclk_c, E => holdn, Q => - asi_0(4)); - - \r.w.s.y_RNO[21]\ : MX2 - port map(A => \y_1[21]\, B => \result_0[21]\, S => N_481, Y - => N_3785); - - \r.e.shcnt_RNIE5275[3]\ : MX2 - port map(A => \shiftin_8[20]\, B => \shiftin_8[12]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[12]\); - - \r.a.ctrl.inst[26]\ : DFN1E0 - port map(D => \inst_0[26]\, CLK => lclk_c, E => holdn, Q - => \inst_2[26]\); - - \r.e.ctrl.inst_RNI2P2L[14]\ : OR3B - port map(A => \inst[18]\, B => \inst[14]\, C => \inst[17]\, - Y => miscout69); - - \r.e.aluop_RNI6QSC4[2]\ : OR2A - port map(A => edata_1_sqmuxa, B => \bpdata[8]\, Y => - \aluop_RNI6QSC4[2]\); - - \r.m.y_RNO_1[4]\ : OR3A - port map(A => \y_1[4]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[4]\); - - \r.e.ctrl.inst_RNIFC0E_0[30]\ : NOR2A - port map(A => \inst_2[31]\, B => \inst_2[30]\, Y => - un3_notag); - - \comb.branch_address.tmp_ADD_30x30_fast_I168_Y\ : OR2A - port map(A => I168_un1_Y_i, B => N534, Y => N594); - - \un1_r.w.s.cwp_1_CO1_0_tz\ : AO1A - port map(A => \rstate_RNIRDFU5[1]\, B => \cwp[0]\, C => - \cwp_0[1]\, Y => CO1_0_tz); - - \r.d.pc_RNO[22]\ : MX2 - port map(A => \fpc[22]\, B => \dpc[22]\, S => N_6763_i, Y - => \pc_RNO[22]\); - - \r.x.data_0_RNO_0[29]\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_20, B => mcdo_m_0_27, C => - rdata_6_sqmuxa, Y => \dco_m_1[125]\); - - \r.e.op1_RNIMOCQB[13]\ : NOR2 - port map(A => \edata2_0_iv_1[13]\, B => \bpdata_i_m_2[5]\, - Y => edata2_0_iv(13)); - - \r.d.inst_0_RNIR8HPD2[31]\ : OR2 - port map(A => un1_inst, B => ctrl_annul_i, Y => N_143); - - \r.e.op2_RNINE992[10]\ : AOI1B - port map(A => \un1_iu0_5[76]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[10]\); - - \r.e.op2_RNO_6[26]\ : OR2B - port map(A => data2(26), B => d25, Y => \rfo_m_i[58]\); - - \r.d.inst_0_RNI42J4_0[21]\ : OR2A - port map(A => \inst_0_0[21]\, B => N_67, Y => un8_op3); - - \r.m.y_RNO_2[1]\ : OR2A - port map(A => \logicout[1]\, B => y14, Y => N_377); - - \r.m.result_0[3]\ : DFN1E0 - port map(D => \eres2[3]\, CLK => lclk_c, E => holdn, Q => - \maddress_0[3]\); - - \r.e.op2_RNI0OMB1[14]\ : OR2A - port map(A => \un1_iu0_5[80]\, B => \un1_iu0_6[14]\, Y => - \logicout_4[14]\); - - \comb.misc_op.un1_r.x.ctrl.rd_0_0_RNIQ42F\ : AND2 - port map(A => rd_0_i_0, B => bpdata6_0, Y => bpdata6_1); - - \r.m.y[12]\ : DFN1E0 - port map(D => \y_1[12]\, CLK => lclk_c, E => holdn, Q => - \y[12]\); - - \r.e.ctrl.inst[18]\ : DFN1E0 - port map(D => \inst_1[18]\, CLK => lclk_c, E => holdn, Q - => \inst[18]\); - - \r.e.aluop_1_RNIC4591[1]\ : XOR3 - port map(A => \un1_iu0_6[11]\, B => \aluop_1[1]\, C => - \un1_iu0_5[77]\, Y => N_6910); - - \r.a.rsel2_0_RNI1Q8FP1[0]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[0]\, Y - => \aluresult_m_i[0]\); - - \r.e.jmpl_RNI9VDQM2\ : AOI1B - port map(A => \shiftin_17[27]\, B => aluresult_2_sqmuxa_0, - C => \aluresult_0_iv_8[27]\, Y => \aluresult_0_iv_9[27]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I269_Y_0 : AOI1 - port map(A => N660_1, B => N645_0, C => N644_0, Y => - ADD_33x33_fast_I269_Y_0_0); - - \r.e.su_RNISBJ4J\ : AOI1B - port map(A => \bpdata[7]\, B => N_3957, C => - \aluresult_1_iv_6[7]\, Y => \aluresult_1_iv_7[7]\); - - \r.a.imm[6]\ : DFN1E0 - port map(D => \un3_de_ren1[124]\, CLK => lclk_c, E => holdn, - Q => \imm[6]\); - - \r.x.data_0_RNIFF9E[18]\ : XOR2 - port map(A => \data_0_0[18]\, B => invop2_1, Y => N_4265); - - \r.m.y_RNO_5[31]\ : MX2 - port map(A => ymsb, B => \data_0[0]\, S => ldbp2_1, Y => - ex_ymsb_1); - - \r.d.inst_0_RNIBIL7[23]\ : OR2 - port map(A => un3_op2, B => call_hold5_0, Y => N_128); - - \comb.fpstdata.edata2_0_iv_RNO_0[2]\ : AND2 - port map(A => \ex_op1_i_m[2]\, B => \op1_i_m[2]\, Y => - \edata2_0_iv_0[2]\); - - \r.a.ctrl.cnt[1]\ : DFN1E0 - port map(D => \cnt_0[1]\, CLK => lclk_c, E => holdn, Q => - \cnt_2[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I302_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[11]\, B => \data_0_2[11]\, Y => - \un6_ex_add_res_s2_1[12]\); - - \r.e.ctrl.annul_RNI5L7FE1\ : NOR3 - port map(A => un2_rstn_5_0_i, B => un12_de_hold_pc, C => - \de_hold_pc_1\, Y => annul_RNI5L7FE1); - - \r.e.aluop_1_RNIATP71[1]\ : XNOR3 - port map(A => \un1_iu0_6[23]\, B => \aluop_1[1]\, C => - \un1_iu0_5[89]\, Y => N_6880_i); - - \r.m.y_RNO_0[15]\ : NOR3C - port map(A => \y_m[15]\, B => \y_m_0[15]\, C => - \y_iv_0[15]\, Y => \y_iv_2[15]\); - - \r.e.jmpl_RNIG24IP\ : OR2B - port map(A => \shiftin_17[16]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[16]\); - - \r.x.ctrl.tt_RNI7LVQ[1]\ : MX2 - port map(A => \result_0[1]\, B => \tt[1]\, S => tt_i, Y => - N_3320); - - \r.e.op2_RNI5VOP[19]\ : MX2 - port map(A => \op2[19]\, B => N_4266, S => ldbp2_0, Y => - \un1_iu0_5[85]\); - - \r.e.aluop_RNI8KJJ1[2]\ : XA1 - port map(A => \un1_iu0_5[93]\, B => \aluop_1[2]\, C => - \un1_iu0_6[27]\, Y => N_3554); - - \r.x.result[10]\ : DFN1E0 - port map(D => \maddress[10]\, CLK => lclk_c, E => holdn, Q - => \result[10]\); - - \r.x.intack_RNO_1\ : NOR2A - port map(A => \tt[4]\, B => \tt[5]\, Y => intack_0); - - \r.m.y_RNI2BC92[22]\ : AOI1B - port map(A => \y[22]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[167]\, Y => \aluresult_1_iv_1[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I103_Y : OR2 - port map(A => N500_0, B => I103_un1_Y, Y => N566); - - \r.x.ctrl.pc[6]\ : DFN1E0 - port map(D => \pc_2[6]\, CLK => lclk_c, E => holdn, Q => - \pc_1[6]\); - - \r.x.ctrl.inst_RNIH32S[22]\ : NOR3B - port map(A => \inst_1[19]\, B => y15, C => \inst_0[22]\, Y - => tba_610_e_3); - - \r.m.ctrl.rd_RNIPC1L[2]\ : XNOR2 - port map(A => \rd_0[2]\, B => \un3_de_ren1[93]\, Y => - un2_rs1_2_2_i_0); - - \r.e.shleft_RNI49931\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[8]\, S => shleft, - Y => \shiftin_5[39]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_a3_1_0 : AND2 - port map(A => N398, B => alucin, Y => - ADD_33x33_fast_I206_Y_0_a3_1_0); - - \r.x.rstate[0]\ : DFN1 - port map(D => N_6322s, CLK => lclk_c, Q => \rstate[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I211_un1_Y : OR2B - port map(A => N640_0, B => N625_1, Y => I211_un1_Y); - - \r.x.y[5]\ : DFN1E0 - port map(D => \y_2[5]\, CLK => lclk_c, E => holdn, Q => - \y_1[5]\); - - \r.d.pv_RNIEN8IS\ : NOR3C - port map(A => un1_annul_next_1_sqmuxa_3_0, B => - un23_exbpmiss_i_0, C => un9_rabpmiss, Y => - un1_annul_next_1_sqmuxa_3_2); - - un6_fe_npc_I_121 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \fe_pc[20]\, Y => N_66); - - \r.e.op2[27]\ : DFN1E0 - port map(D => N_311, CLK => lclk_c, E => holdn, Q => - \op2[27]\); - - \r.a.rsel1_0_RNIOO7M2[2]\ : OR2B - port map(A => data1(0), B => d11, Y => \rfo_m[0]\); - - \r.e.op2_RNI6BA92[17]\ : AOI1B - port map(A => \un1_iu0_5[83]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[17]\); - - \comb.cwp_ctrl.ncwp_3_I_10\ : XNOR2 - port map(A => \inst_0[19]\, B => \cwp[1]\, Y => - \DWACT_ADD_CI_0_partial_sum[1]\); - - \r.w.s.tba[12]\ : DFN1E1 - port map(D => \result_0[24]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[12]\); - - \r.x.mexc_RNICKPT\ : OR2A - port map(A => N_3320, B => mexc_0, Y => \xc_vectt_1[1]\); - - \r.m.result_RNO[25]\ : MX2 - port map(A => \aluresult[25]\, B => \op1[25]\, S => - un17_casaen_0_1, Y => \eres2[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I76_Y : OA1 - port map(A => \data_0[8]\, B => \un1_iu0_6[8]\, C => N425_2, - Y => N535_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I107_Y : AO1 - port map(A => N508, B => N505, C => N504, Y => N570_0); - - \r.m.ctrl.inst_RNIHADL4[21]\ : OR3C - port map(A => iflush_1_0, B => iflush_1, C => iflush_4, Y - => flush_i_0); - - \r.f.branch_RNI6I584\ : NOR2 - port map(A => \fbranch\, B => jump_0, Y => d_m5_0_a3_0); - - \r.x.data_0[19]\ : DFN1E0 - port map(D => \data_0_1[19]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[19]\); - - \r.x.ctrl.pc_RNIHPL9[20]\ : MX2 - port map(A => \pc_2[20]\, B => \pc_0[20]\, S => \npc[1]\, Y - => N_3231); - - \r.e.op1_RNO[12]\ : MX2C - port map(A => \d_i[12]\, B => \d_i[13]\, S => N_227, Y => - \aop1[12]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I243_Y : AO1 - port map(A => N672_1, B => N657_1, C => N656_1, Y => N796_1); - - \r.m.result[3]\ : DFN1E0 - port map(D => \eres2[3]\, CLK => lclk_c, E => holdn, Q => - \maddress[3]\); - - \r.e.cwp_RNIF0258[1]\ : NOR3C - port map(A => \cwp_m[1]\, B => \aluresult_2_iv_0[1]\, C => - \aluresult_2_iv_1[1]\, Y => \aluresult_2_iv_3[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I263_Y_1 : AOI1B - port map(A => N648, B => N633, C => ADD_33x33_fast_I263_Y_0, - Y => ADD_33x33_fast_I263_Y_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I187_Y : AO1 - port map(A => N598_2, B => N591_1, C => N590_1, Y => N656); - - \r.m.ctrl.rd_RNIHKQS1[3]\ : XA1A - port map(A => \un3_de_ren1[94]\, B => \rd_0[3]\, C => - un2_rs1_2_6_i_0, Y => wreg_1_3); - - \r.e.ctrl.cnt_RNILO7A_1[0]\ : NOR3 - port map(A => \cnt[0]\, B => \cnt[1]\, C => annul, Y => - read_1_sqmuxa_0); - - \r.m.y_RNIO1O71[11]\ : OR2B - port map(A => \y_0[11]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[11]\); - - \r.m.result_RNO[17]\ : MX2 - port map(A => \aluresult[17]\, B => \op1[17]\, S => - un17_casaen_0_2, Y => \eres2[17]\); - - \r.a.ctrl.inst_RNIIUL69[13]\ : OR3B - port map(A => \inst[13]\, B => un1_illegal_inst34, C => - N_212, Y => \cpi_m[121]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I6_G0N : OAI1 - port map(A => \op1[5]\, B => ldbp1_3, C => \data_0[5]\, Y - => N412_2); - - \r.x.result_RNIMMED[12]\ : MX2 - port map(A => \result[12]\, B => \data_0_2[12]\, S => ld_0, - Y => \un1_p0_6[364]\); - - \r.d.inst_0_0_0_RNI7TVIO2[12]\ : NOR2B - port map(A => rst, B => N_4612, Y => - \inst_0_0_0_RNI7TVIO2[12]\); - - \r.m.ctrl.pc[7]\ : DFN1E0 - port map(D => \pc_0[7]\, CLK => lclk_c, E => holdn, Q => - \pc_2[7]\); - - \r.w.s.y_RNO[13]\ : MX2 - port map(A => \y_2[13]\, B => \result_0[13]\, S => N_481_0, - Y => N_3777); - - \r.d.pc_RNO[9]\ : MX2 - port map(A => \fpc[9]\, B => \dpc[9]\, S => N_6763_i_0, Y - => \pc_RNO[9]\); - - \r.m.y_RNO_1[27]\ : AOI1B - port map(A => \y_0[27]\, B => y08_0, C => N_424, Y => - \y_iv_0_0[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I169_Y\ : NOR3B - port map(A => N476_0, B => N480, C => N543, Y => N595_0); - - \r.x.data_0[0]\ : DFN1E0 - port map(D => \data_0_1[0]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[0]\); - - \r.m.y_RNI2JC92[13]\ : AOI1B - port map(A => \y[13]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[158]\, Y => \aluresult_1_iv_1[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I15_G0N : NOR2B - port map(A => \op2[14]\, B => \un1_iu0_6[14]\, Y => N439); - - \r.e.aluop_RNIILSC4[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[27]\, Y => - \bpdata_i_m[27]\); - - \r.e.op2_RNIDPC6[4]\ : MX2 - port map(A => \op2[4]\, B => N_3308, S => ldbp2_3, Y => - \un1_iu0_5[70]\); - - \r.a.ctrl.pc[20]\ : DFN1E0 - port map(D => \dpc[20]\, CLK => lclk_c, E => holdn, Q => - \pc[20]\); - - \r.m.dci.asi_RNO[2]\ : NOR2B - port map(A => \inst_0[23]\, B => \inst_1[7]\, Y => \asi[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I311_Y_0 : XOR2 - port map(A => ADD_33x33_fast_I311_Y_0_0, B => N786_i, Y => - \un6_ex_add_res_s1_i[21]\); - - \r.m.ctrl.pc_RNIGPN9[18]\ : MX2 - port map(A => \pc_3[18]\, B => \pc[18]\, S => \npc[1]\, Y - => N_3259); - - \r.e.ctrl.pc_RNINR011[3]\ : OR2B - port map(A => \pc_0[3]\, B => jmpl_4, Y => \cpi_m[148]\); - - \r.a.ctrl.wy\ : DFN1E0 - port map(D => wy_1_1, CLK => lclk_c, E => holdn, Q => wy); - - \r.x.rstate_0_RNIVGIE2[0]\ : MX2C - port map(A => N_3422, B => \xc_result[31]\, S => - \rstate_0[0]\, Y => \wdata[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I315_Y_0 : XNOR3 - port map(A => \un1_iu0_6[24]\, B => \op2[24]\, C => N778_1, - Y => \un6_ex_add_res_s1_i[25]\); - - \r.x.rstate_RNIK02D2[0]\ : MX2C - port map(A => N_3412, B => \xc_result[21]\, S => - \rstate[0]\, Y => \wdata[21]\); - - \r.w.s.pil_RNI59PJ3[3]\ : OA1A - port map(A => \pil[3]\, B => aluresult_11_sqmuxa, C => - \aluresult_1_iv_0[11]\, Y => \aluresult_1_iv_2[11]\); - - \r.d.pc[17]\ : DFN1 - port map(D => \pc_RNO[17]\, CLK => lclk_c, Q => \dpc[17]\); - - \r.a.rsel1_0_RNIG7LJ2[2]\ : OR2B - port map(A => data1(26), B => d11_0, Y => \rfo_m[26]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I277_Y_0\ : XNOR2 - port map(A => N718_i, B => ADD_30x30_fast_I277_Y_0_0, Y => - \tmp[19]\); - - \r.e.aluop_0[2]\ : DFN1E0 - port map(D => \aluop[2]\, CLK => lclk_c, E => holdn, Q => - \aluop_0[2]\); - - \r.e.ctrl.wy_0\ : DFN1E0 - port map(D => wy, CLK => lclk_c, E => holdn, Q => wy_0); - - \r.d.inst_0_RNI3846[21]\ : OR2B - port map(A => un14_op_2, B => icc_check9_2, Y => icc_check9); - - \r.d.annul_RNIMSEMD2\ : OR2 - port map(A => ctrl_annul_i_0_a2_0, B => annul_current, Y - => ctrl_annul_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I68_Y : OA1B - port map(A => \data_0_2[12]\, B => \un1_iu0_6[12]\, C => - N437_2, Y => N527_1); - - \r.m.y_RNO_4[16]\ : OR2B - port map(A => \y[17]\, B => mulstep_0, Y => \y_m_1[17]\); - - \r.e.op2_RNO_2[13]\ : AOI1B - port map(A => data2(13), B => d25_0, C => \d_1_iv_2[13]\, Y - => \d_1_iv_3[13]\); - - \r.e.op2_RNI7C9P_0[1]\ : OR2 - port map(A => \un1_iu0_6[1]\, B => \op2_RNI1LHG[1]\, Y => - \logicout_3[1]\); - - \r.d.inst_0_RNIJCK6[27]\ : AX1C - port map(A => N_375, B => \inst_0[27]\, C => \inst_0[28]\, - Y => N_3346); - - \comb.ld_align.rdata199_RNI4ADG12\ : AO1C - port map(A => rdata_1_sqmuxa_1, B => ld_3, C => - rdata_5_sqmuxa, Y => N_3455); - - \r.x.y[13]\ : DFN1E0 - port map(D => \y[13]\, CLK => lclk_c, E => holdn, Q => - \y_2[13]\); - - \r.a.ctrl.rd_RNISJI31[5]\ : XNOR2 - port map(A => \rd_1[5]\, B => \un3_de_ren1[96]\, Y => - un2_rs1_5_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I104_Y : OR2A - port map(A => N505, B => N501, Y => N567_2); - - \r.m.y_RNO_3[3]\ : AOI1B - port map(A => wy_1_0, B => \y[3]\, C => \y_m[3]\, Y => - \y_iv_1[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I236_Y\ : AOI1 - port map(A => ADD_30x30_fast_I236_un1_Y_0, B => N741, C => - ADD_30x30_fast_I236_Y_1, Y => N702_i); - - \r.x.result_RNIB5R65[4]\ : OR2B - port map(A => \bpdata[4]\, B => N_3957_1, Y => - \bpdata_m_1[4]\); - - \r.e.aluop_RNIK0RF4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[31]\, Y => - \aluop_RNIK0RF4[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I11_G0N : NOR3A - port map(A => \op1[10]\, B => ldbp1_2, C => \data_0[10]\, Y - => N427_0); - - \r.e.op2_RNO_9[23]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[375]\, - Y => \cpi_m_i[375]\); - - \r.e.aluop_0_RNIN8IG3[0]\ : MX2C - port map(A => N_3566, B => N_3630, S => \aluop_0[0]\, Y => - \logicout[7]\); - - \r.e.ctrl.ld\ : DFN1E0 - port map(D => ld_1, CLK => lclk_c, E => holdn, Q => ld_5); - - \r.e.ctrl.inst_RNIFC0E[30]\ : OR2B - port map(A => \inst_2[31]\, B => \inst_2[30]\, Y => - N_3356_3); - - \r.x.y[25]\ : DFN1E0 - port map(D => \y_2[25]\, CLK => lclk_c, E => holdn, Q => - \y_1[25]\); - - \r.m.y_RNO[14]\ : OR3C - port map(A => \y_iv_0_1[14]\, B => \y_iv_0_0[14]\, C => - N_385, Y => \y_1[14]\); - - \r.e.aluop_0_RNI39JG3[0]\ : MX2C - port map(A => N_3567, B => N_3631, S => \aluop_0[0]\, Y => - \logicout[8]\); - - \r.e.shleft_0_RNISUAG\ : OR2A - port map(A => \un1_iu0_6[0]\, B => shleft_0, Y => - \shiftin_5[0]\); - - \r.e.op2_RNO_7[19]\ : OR3C - port map(A => d28_0, B => \rsel2_1[0]\, C => - \un1_p0_6[371]\, Y => \cpi_m_i[371]\); - - \r.x.data_0[4]\ : DFN1E0 - port map(D => \data_0_1[4]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[4]\); - - \r.x.ctrl.inst_RNIHVSN2[24]\ : NOR3A - port map(A => tba_610_e_5, B => tba_1_sqmuxa_3, C => holdn, - Y => \inst_RNIHVSN2[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I249_Y : OR2 - port map(A => N668_1, B => I249_un1_Y_0, Y => N814_0); - - \r.e.shcnt_RNIGAVV3[3]\ : MX2 - port map(A => \shiftin_8[13]\, B => \shiftin_8[5]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[5]\); - - \r.e.op2_RNIHS9P_0[3]\ : OR2 - port map(A => \un1_iu0_6[3]\, B => \un1_iu0_5[69]\, Y => - \logicout_3[3]\); - - \r.e.ctrl.pc_RNI60LA2[6]\ : AOI1B - port map(A => \pc[6]\, B => jmpl_0, C => \y_m_1[6]\, Y => - \aluresult_1_iv_2[6]\); - - \r.x.y[10]\ : DFN1E0 - port map(D => \y_0[10]\, CLK => lclk_c, E => holdn, Q => - \y_2[10]\); - - \r.a.rsel2[2]\ : DFN1E0 - port map(D => N_3946_1, CLK => lclk_c, E => holdn, Q => - \rsel2[2]\); - - wovf_exc_0_sqmuxa_RNO_5 : MX2 - port map(A => \wim_1[2]\, B => \wim_1[6]\, S => \ncwp_3[2]\, - Y => N_3726); - - \r.a.ctrl.inst_RNIU43A1_0[21]\ : OR2A - port map(A => inst_5_1, B => N_515, Y => inst_5); - - \r.x.ctrl.pc[16]\ : DFN1E0 - port map(D => \pc_3[16]\, CLK => lclk_c, E => holdn, Q => - \pc_2[16]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I166_Y : OR2A - port map(A => N577_0, B => N569, Y => N635_1); - - \r.f.pc_RNO[5]\ : AO1B - port map(A => I_13, B => un2_rstn_4_0_0, C => - \pc_1_iv_2[5]\, Y => \pc_1[5]\); - - \r.e.ldbp2_2_RNI620KL1\ : OR2A - port map(A => \eaddress[14]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[15]\); - - \r.e.ctrl.pc_RNIC0LA2[9]\ : AOI1B - port map(A => \pc[9]\, B => jmpl_0, C => \y_m_1[9]\, Y => - \aluresult_1_iv_1[9]\); - - \r.x.npc_0_RNI3DR61[0]\ : MX2C - port map(A => N_3242, B => N_3272, S => \npc_0[0]\, Y => - \xc_result[31]\); - - \r.m.ctrl.rd[0]\ : DFN1E0 - port map(D => \rd[0]\, CLK => lclk_c, E => holdn, Q => - \rd_1[0]\); - - \r.e.op2_RNO_2[5]\ : NOR3C - port map(A => \d_1_iv_1[5]\, B => \d_1_iv_0[5]\, C => - \rfo_m_i[37]\, Y => \d_1_iv_3[5]\); - - \r.e.aluop_2_RNIDI6R2[1]\ : MX2C - port map(A => N_3544, B => \logicout_3[17]\, S => - \aluop_2[1]\, Y => N_3576); - - un6_ex_add_res_d1_ADD_33x33_fast_I13_P0N : OR2 - port map(A => \op2[12]\, B => \un1_iu0_6[12]\, Y => N434_0); - - \r.e.ctrl.inst_RNIHS0E[24]\ : NOR2A - port map(A => \inst[24]\, B => \inst_1[21]\, Y => - aluresult_12_sqmuxa_4); - - \r.w.s.tba_RNI074BK[16]\ : NOR3C - port map(A => \bpdata_m_2[4]\, B => \aluresult_1_iv_3[28]\, - C => \aluresult_1_iv_4[28]\, Y => \aluresult_1_iv_6[28]\); - - \r.x.data_0_RNO_3[10]\ : OR2A - port map(A => \data_0[10]\, B => ld_0_0, Y => - \data_0_m_i[10]\); - - \r.f.pc_RNI7BEN55[9]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[9]\, Y => - \pc_4_m[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I248_Y : OR2A - port map(A => I248_un1_Y_i, B => N666, Y => N811); - - \r.e.ldbp2_RNICGKQM1\ : MX2C - port map(A => \un6_ex_add_res_s1_i[16]\, B => N_6635, S => - ldbp2_3, Y => \eaddress[15]\); - - \r.x.result_RNI8MTN5[1]\ : OR2A - port map(A => N_3687, B => \bpdata[1]\, Y => - \bpdata_i_m[1]\); - - \r.x.data_0_RNIMVG8[24]\ : XOR2 - port map(A => \data_0[24]\, B => invop2, Y => N_4271); - - \r.m.y_RNO_1[15]\ : OR3A - port map(A => \y_1[15]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[15]\); - - \r.e.op2_RNIUSAP[7]\ : OR2A - port map(A => \un1_iu0_5[73]\, B => \un1_iu0_6[7]\, Y => - \logicout_4[7]\); - - \r.e.op2_RNO_8[28]\ : OR3B - port map(A => d29_0, B => \imm[28]\, C => \rsel2[0]\, Y => - \imm_m_i[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I297_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[7]\, B => N674_1, Y => - \un6_ex_add_res_s0[7]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I5_G0N\ : AND2 - port map(A => \dpc[7]\, B => \inst_0[5]\, Y => N373); - - \r.m.ctrl.tt[5]\ : DFN1E0 - port map(D => \tt_3[5]\, CLK => lclk_c, E => holdn, Q => - \tt_1[5]\); - - \r.e.shcnt_RNIR4JM7[3]\ : MX2C - port map(A => \shiftin_8[45]\, B => \shiftin_8[37]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[37]\); - - \r.e.op2[30]\ : DFN1E0 - port map(D => N_314, CLK => lclk_c, E => holdn, Q => - \op2[30]\); - - \r.e.op1_RNIVENF[13]\ : NOR2A - port map(A => \un17_casaen_0_0\, B => \op1[13]\, Y => - \op1_i_m[13]\); - - \r.e.alusel_RNIJDA9[0]\ : OR2A - port map(A => \alusel[0]\, B => \alusel[1]\, Y => - aluresult_1_sqmuxa_0_0); - - \r.e.op1_RNIFNIO58[30]\ : NOR3C - port map(A => \op1_m_0[30]\, B => \d_iv_2[30]\, C => - \aluresult_m_0[30]\, Y => \d_i[30]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I289_Y_0\ : XNOR2 - port map(A => N694, B => ADD_30x30_fast_I289_Y_0_0, Y => - \tmp[31]\); - - \r.w.s.et_RNI1BRF2\ : OR2B - port map(A => cwp_2_sqmuxa_i, B => N_6337, Y => et_RNI1BRF2); - - \r.e.op2_RNO_3[24]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[24]\, Y => - \aluresult_m_i[24]\); - - \r.x.result_RNIHLBB[3]\ : MX2 - port map(A => \result_0[3]\, B => \data_0[3]\, S => ld_4, Y - => \un1_p0_6[355]\); - - \r.a.ctrl.inst_RNISAEP[10]\ : NOR3A - port map(A => un29_casaen_1, B => \inst[11]\, C => - \inst[10]\, Y => un29_casaen_4); - - \r.m.ctrl.pv\ : DFN1E0 - port map(D => pv_5, CLK => lclk_c, E => holdn, Q => pv_1); - - \r.e.op2_RNO_4[17]\ : OA1A - port map(A => \maddress[17]\, B => d27, C => \cpi_m_i[369]\, - Y => \d_1_iv_1[17]\); - - \r.a.rsel1_0_RNI4V53_0[2]\ : NOR2 - port map(A => d11_0_a5_0, B => \rsel1_0[2]\, Y => d11_0); - - \r.x.rstate_RNI1BC12[0]\ : MX2C - port map(A => N_3411, B => \xc_result[20]\, S => - \rstate[0]\, Y => \wdata[20]\); - - \r.e.ldbp2_2_RNI2UDR53\ : MX2C - port map(A => \un6_ex_add_res_s1_i[21]\, B => N_6567, S => - ldbp2_2, Y => \eaddress[20]\); - - \r.a.ctrl.pv\ : DFN1E0 - port map(D => ctrl_pv, CLK => lclk_c, E => holdn, Q => pv_4); - - \comb.branch_address.tmp_ADD_30x30_fast_I110_Y\ : OR2 - port map(A => N471, B => I110_un1_Y, Y => N530_1); - - \r.x.mexc_RNII0QT\ : NOR2 - port map(A => mexc_0, B => N_3323, Y => \xc_vectt_1[4]\); - - \r.e.op2[16]\ : DFN1E0 - port map(D => N_300, CLK => lclk_c, E => holdn, Q => - \op2[16]\); - - \r.e.aluop_RNIMFFR5[0]\ : OR2B - port map(A => \logicout[20]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[20]\); - - un2_rstn_5_0_0_RNIQT8C2 : NAND2 - port map(A => \tmp[4]\, B => un2_rstn_5_0, Y => \tmp_m[4]\); - - \r.e.shleft_0_RNITSHP\ : OR2A - port map(A => \un1_iu0_6[15]\, B => shleft_0, Y => - \shiftin_5[15]\); - - \r.m.result[10]\ : DFN1E0 - port map(D => \eres2[10]\, CLK => lclk_c, E => holdn, Q => - \maddress[10]\); - - \r.m.icc_RNI88I3_0[3]\ : NOR2 - port map(A => \icc[3]\, B => \icc[1]\, Y => N_523); - - \r.e.op2_RNO_7[16]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[368]\, Y => \cpi_m_i[368]\); - - \r.w.result_RNIJJD4[21]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[21]\, - Y => \result_m_0[21]\); - - \r.e.ctrl.tt_RNO_0[2]\ : NOR2 - port map(A => \tt_9_i_a4_0[2]\, B => trap_4_1, Y => N_4039); - - \r.e.ctrl.rd[7]\ : DFN1E0 - port map(D => \rd[7]\, CLK => lclk_c, E => holdn, Q => - \rd_1[7]\); - - \r.e.shcnt_RNIUQP9D[2]\ : MX2C - port map(A => \shiftin_11[26]\, B => \shiftin_11[22]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[22]\); - - \r.f.pc_RNO_2[28]\ : OR2B - port map(A => I_186, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I293_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[2]\, B => \data_0[2]\, Y => - \un6_ex_add_res_s2_1[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I183_Y : OR2 - port map(A => N586, B => I183_un1_Y, Y => N652_1); - - \r.e.mulstep_RNI8VGC_2\ : NOR2B - port map(A => mulstep, B => wy_0, Y => mulstep_1); - - \r.e.ctrl.inst_RNIN8Q71[26]\ : AOI1B - port map(A => N_229, B => N_211, C => ex_bpmiss_1_0_a5_1_1, - Y => N_427); - - \r.d.pc_RNO[27]\ : MX2 - port map(A => \fpc[27]\, B => \dpc[27]\, S => N_6763_i, Y - => \pc_RNO[27]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I6_P0N : OR2 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, Y => N413); - - \r.a.ctrl.cnt_RNI515E[0]\ : OR3A - port map(A => \cnt_2[1]\, B => \cnt_1[0]\, C => - \inst_2[20]\, Y => aluop_2_1_0_a5_1_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I114_Y : NOR2A - port map(A => N511_0, B => N_30_0, Y => N577); - - \r.x.laddr_RNI4ADG12[1]\ : OR2 - port map(A => rdata_4_sqmuxa, B => rdata_2_sqmuxa, Y => - N_3480); - - \r.x.result_RNI905F5[10]\ : NOR2A - port map(A => \aluop_RNIGM3N1[2]\, B => \bpdata[10]\, Y => - \bpdata_i_m[10]\); - - \r.w.s.pil_RNILSV29[3]\ : OA1A - port map(A => N_3974, B => \bpdata[11]\, C => - \aluresult_1_iv_2[11]\, Y => \aluresult_1_iv_4[11]\); - - \r.m.nalign_RNI0UR41\ : NOR3 - port map(A => trap_0_sqmuxa_1_1_i, B => trap_0_sqmuxa_1_0, - C => trap_0_sqmuxa_1_2_i, Y => trap_0_sqmuxa_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_un1_Y : OAI1 - port map(A => I249_un1_Y, B => N668_0, C => - ADD_33x33_fast_I265_un1_Y_0_0, Y => I265_un1_Y_i_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I61_Y : MAJ3 - port map(A => \op2[16]\, B => \un1_iu0_6[16]\, C => N442_0, - Y => N520_1); - - \r.m.irqen_RNO_0\ : NOR3A - port map(A => trap27, B => trap63, C => annul_RNIPFOQ, Y - => irqen_1); - - \r.f.pc_RNIVNV31[6]\ : MX2 - port map(A => \fpc[6]\, B => \xc_vectt_1[2]\, S => - rstate_6314_d_0, Y => \xc_trap_address[6]\); - - \r.e.alusel_RNO_2[0]\ : OR2B - port map(A => N_351_1, B => N_203, Y => N_351); - - \r.m.y_RNIAJD92[17]\ : AOI1B - port map(A => \y[17]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[162]\, Y => \aluresult_1_iv_1[17]\); - - \r.m.ctrl.wreg\ : DFN1E0 - port map(D => wreg_1_9, CLK => lclk_c, E => holdn, Q => - wreg_4); - - \r.e.ctrl.inst_RNIGF49A5[24]\ : OR3B - port map(A => \icc_8_m_1[1]\, B => \icc_8[1]\, C => - \icc_8_m_5[1]\, Y => \icc_8_m_i[1]\); - - \r.x.ctrl.pc_RNI67AE[2]\ : MX2 - port map(A => \pc_0[2]\, B => \pc_2[2]\, S => \npc_0[1]\, Y - => N_3213); - - \r.e.et_RNI9QNL5\ : OA1A - port map(A => et_0, B => aluresult_11_sqmuxa, C => - \aluresult_1_iv_1[5]\, Y => \aluresult_1_iv_3[5]\); - - \r.x.data_0_RNO[5]\ : AO1B - port map(A => N_3456, B => N_3389_i_0, C => - \data_0_1_1_iv_2[5]\, Y => \data_0_1[5]\); - - \r.e.su\ : DFN1E0 - port map(D => su_1, CLK => lclk_c, E => holdn, Q => esu); - - \r.e.shcnt_RNISL246[3]\ : MX2 - port map(A => \shiftin_8[26]\, B => \shiftin_8[18]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[18]\); - - \r.d.inst_0_RNIKG46[29]\ : NOR2A - port map(A => N_85, B => N_3525_3, Y => un3_reg); - - \r.a.ctrl.wreg_RNO_8\ : OR3B - port map(A => \inst_0[20]\, B => N_142, C => - \un1_p0_6_0[60]\, Y => inst_0); - - \r.e.shcnt_RNI0NSS4[3]\ : MX2 - port map(A => \shiftin_8[15]\, B => \shiftin_8[7]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_o3_1 : OR2B - port map(A => ADD_33x33_fast_I206_Y_0_o3_1_0, B => N_57_i, - Y => N616); - - \r.w.s.y[13]\ : DFN1E0 - port map(D => N_3777, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[13]\); - - \r.m.result[21]\ : DFN1E0 - port map(D => \eres2[21]\, CLK => lclk_c, E => holdn, Q => - \maddress[21]\); - - \r.m.dci.asi_RNO_1[0]\ : NOR2A - port map(A => rett_0, B => annul_0, Y => rett_i); - - \r.e.op1_RNI221HH7[28]\ : AOI1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[28]\, C - => \d_iv_3[28]\, Y => \d_i[28]\); - - \r.e.ldbp2_2_RNI2O2TD4\ : MX2C - port map(A => \un6_ex_add_res_s1_i[28]\, B => N_6574, S => - ldbp2_2, Y => \eaddress[27]\); - - \r.m.y_RNO_3[27]\ : OR3A - port map(A => \y_2[27]\, B => wy_3, C => wy_1_0_1, Y => - N_422); - - \r.e.shleft_RNI7BQR2\ : MX2 - port map(A => \shiftin_5[55]\, B => \shiftin_5[39]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[39]\); - - \r.m.result_RNO[10]\ : MX2 - port map(A => \aluresult[10]\, B => \op1[10]\, S => - un17_casaen_0, Y => \eres2[10]\); - - \r.e.ldbp2_0_RNI874SQ1\ : MX2C - port map(A => \un6_ex_add_res_s1_i[17]\, B => N_6563, S => - ldbp2_0, Y => \eaddress[16]\); - - \r.a.rfa2[4]\ : DFN1E0 - port map(D => \un3_de_ren1[103]\, CLK => lclk_c, E => holdn, - Q => \rfa2[4]\); - - \r.e.ctrl.pc_RNIDTK11[18]\ : OR2B - port map(A => \pc_0[18]\, B => jmpl_4, Y => \cpi_m[163]\); - - \r.x.data_0_RNO_0[2]\ : AO1B - port map(A => rdatav_0_1_0_iv_5_0, B => mcdo_m_0_16, C => - N_3455, Y => \dco_m_i[114]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I7_P0N : OR2 - port map(A => \un1_iu0_6[6]\, B => \op2[6]\, Y => N416_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I231_un1_Y : NAND2 - port map(A => N645, B => N660, Y => I231_un1_Y_i); - - \r.e.jmpl_RNID42AH1\ : AND2 - port map(A => \shiftin_17_m[15]\, B => - \aluresult_1_iv_7[14]\, Y => \aluresult_1_iv_8[14]\); - - \r.x.rstate_RNIEO45[1]\ : OR2A - port map(A => \rstate[1]\, B => \rstate_0[0]\, Y => - rstate_6314_d_0); - - \r.m.y_RNIUT7CA[18]\ : NOR3C - port map(A => \aluresult_1_iv_1[18]\, B => - \aluresult_1_iv_0[18]\, C => \aluresult_1_iv_3[18]\, Y - => \aluresult_1_iv_4[18]\); - - \r.a.ctrl.rett_RNIS5SE\ : NOR3A - port map(A => rett_2, B => trap_1, C => annul_2, Y => - rett_1); - - \r.a.jmpl\ : DFN1E0 - port map(D => jmpl_3, CLK => lclk_c, E => holdn, Q => - jmpl_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I3_P0N : OR2 - port map(A => \un1_iu0_6[2]\, B => \op2[2]\, Y => N404); - - \r.e.ctrl.tt_RNO[5]\ : AOI1 - port map(A => N_4043_i, B => N_4042, C => annul_2, Y => - \tt_2[5]\); - - \r.a.ctrl.inst_RNID8Q8[28]\ : XOR2 - port map(A => \inst_1[28]\, B => \icc[1]\, Y => branch_8); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_Y : NAND2 - port map(A => I265_un1_Y_i_0, B => - ADD_33x33_fast_I265_Y_1_0, Y => N776); - - \r.e.jmpl_RNI2UJLU_0\ : OR2B - port map(A => \shiftin_17[28]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[28]\); - - \r.e.op2_RNO_2[30]\ : NOR3C - port map(A => \d_1_iv_1[30]\, B => \d_1_iv_0[30]\, C => - \rfo_m_i[62]\, Y => \d_1_iv_3[30]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_4\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \r.e.aluop_RNIE7BBM[0]\ : AND2 - port map(A => \aluresult_1_iv_6[20]\, B => - \logicout_m_0[20]\, Y => \aluresult_1_iv_7[20]\); - - \r.a.imm_RNO[9]\ : NOR2B - port map(A => \inst_0[9]\, B => call_hold5, Y => - \un3_de_ren1[127]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I30_un1_Y\ : OR3B - port map(A => \dpc[29]\, B => \inst_0_RNI8AJ4[27]\, C => - N443_2, Y => ADD_30x30_fast_I30_un1_Y); - - \r.x.y[7]\ : DFN1E0 - port map(D => \y[7]\, CLK => lclk_c, E => holdn, Q => - \y_2[7]\); - - \r.x.npc_RNIAS011[0]\ : MX2C - port map(A => N_3232, B => N_3262, S => \npc[0]\, Y => - \xc_result[21]\); - - \r.e.ldbp2_RNIIDDTL1\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[4]\, Y => - \un6_ex_add_res_m_1[5]\); - - \r.w.s.tba_RNI34CA1[2]\ : OR2B - port map(A => \tba[2]\, B => aluresult_12_sqmuxa, Y => - \tba_m[2]\); - - \r.f.pc_RNO_3[13]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[13]\, C => - \xc_trap_address_m[13]\, Y => \pc_1_iv_0[13]\); - - \r.x.data_0_RNO_4[1]\ : AO1B - port map(A => rdatav_0_1_0_iv_4_0, B => mcdo_m_0_7, C => - rdata_2_sqmuxa, Y => \dco_m_i[105]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I227_un1_Y : OR2B - port map(A => N656_1, B => N641_1, Y => I227_un1_Y); - - \r.e.op2_RNO_0[18]\ : OR3C - port map(A => \op1_m_i[18]\, B => \d_1_iv_3[18]\, C => - \aluresult_m_i[18]\, Y => \d_1[18]\); - - \r.x.data_0_RNO_2[0]\ : AO1 - port map(A => rdatav_0_1_0_iv_5_6, B => mcdo_m_0_22, C => - rdata_0_sqmuxa, Y => \dco_m_i[120]\); - - \r.m.y_RNO_4[9]\ : OR3A - port map(A => \y_2[9]\, B => wy_3, C => wy_1_0_1, Y => - \y_m[9]\); - - \r.e.jmpl_RNIGBJ9J1\ : AOI1B - port map(A => \shiftin_17[23]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[22]\, Y => \aluresult_1_iv_8[22]\); - - \r.a.rsel2_0_RNIMCHE[0]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[354]\, Y => \cpi_m_i[354]\); - - \r.e.aluop_0_RNIT26O1[1]\ : MX2C - port map(A => \logicout_4[1]\, B => N_6889, S => N_6866_i_0, - Y => N_3624); - - \comb.branch_address.tmp_ADD_30x30_fast_I263_Y_0_0\ : XOR2 - port map(A => \dpc[5]\, B => \inst_0_RNI3RUM[3]\, Y => - ADD_30x30_fast_I263_Y_0_0); - - \r.e.op1_RNIIUBR1[12]\ : NOR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[12]\, Y => - \ex_op1_i_m[12]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I321_Y_0 : XOR2 - port map(A => N766_0, B => \un6_ex_add_res_s2_1[31]\, Y => - \un6_ex_add_res_s2[31]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I18_G0N\ : NOR2B - port map(A => \inst_0[18]\, B => \dpc[20]\, Y => N412); - - \r.x.result_RNIQGAN3[17]\ : MX2 - port map(A => \un1_iu0_6[17]\, B => \un1_p0_6[369]\, S => - bpdata6, Y => \bpdata[17]\); - - \r.x.ctrl.rett\ : DFN1E0 - port map(D => rett_1_1, CLK => lclk_c, E => holdn, Q => - rett_0); - - \r.f.pc_RNIQUO11[11]\ : MX2 - port map(A => \fpc[11]\, B => xc_vectt14, S => - rstate_6314_d, Y => \xc_trap_address[11]\); - - \r.d.inst_0_RNO[4]\ : NOR2B - port map(A => rst, B => N_4604, Y => \inst_0_RNO[4]\); - - \r.x.ctrl.wy_RNIGJP13\ : AO1A - port map(A => y_0_sqmuxa_1, B => y_0_sqmuxa_3, C => wy_2, Y - => y_1_sqmuxa); - - un6_fe_npc_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - \r.x.result_RNINK6E[22]\ : MX2 - port map(A => \result_0[22]\, B => \data_0_0[22]\, S => - ld_4, Y => \un1_p0_6[374]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I50_Y : NOR2B - port map(A => N464, B => N461_1, Y => N509_0); - - \r.d.cwp[1]\ : DFN1E0 - port map(D => \cwp_1_0[1]\, CLK => lclk_c, E => holdn, Q - => \cwp[1]\); - - \r.a.et_RNIGQT5A\ : NOR3C - port map(A => illegal_inst_7_iv_0, B => N_444, C => - illegal_inst_7_iv_1, Y => illegal_inst_7_iv_3); - - un6_ex_add_res_d1_ADD_33x33_fast_I56_Y_i : OR2B - port map(A => N455_2, B => N452_0, Y => N_30); - - \r.e.op1_RNI4VNF[27]\ : OR2A - port map(A => un17_casaen_0, B => \op1[27]\, Y => - \op1_RNI4VNF[27]\); - - \r.a.ctrl.inst_RNITH523[22]\ : OA1A - port map(A => cp_disabled_10_sqmuxa_1, B => N_260, C => - cp_disabled_5_sqmuxa, Y => fp_disabled_4_0_1_1); - - \r.w.result_RNIG4P1[29]\ : OR3C - port map(A => N_484_0, B => \rsel1[2]\, C => \result[29]\, - Y => \result_m_0[29]\); - - \comb.lock_gen.ldchkra\ : OR2A - port map(A => ldchkra_0, B => call_hold7_i, Y => ldchkra); - - \r.m.y_RNO_1[21]\ : OR3A - port map(A => \y_1[21]\, B => wy_3, C => wy_1_0_0, Y => - \y_m[21]\); - - \r.x.data_0_RNO[1]\ : AO1B - port map(A => N_3456, B => N_3227_i_0, C => - \data_0_1_1_iv_2[1]\, Y => \data_0_1[1]\); - - \r.e.op2_RNO_1[14]\ : OR2B - port map(A => \op1[14]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[14]\); - - \r.d.inst_0_0_0_RNIAG79[21]\ : NOR3A - port map(A => \un1_p0_6_0[60]\, B => \inst_0[19]\, C => - \inst_0[20]\, Y => wy_1_0_a3_1_0); - - \r.a.ctrl.inst_RNIK15D2[30]\ : OA1A - port map(A => aluop_0_1_0_a5_3_0, B => N_205, C => N_363, Y - => aluop_0_1_0_2); - - \r.w.s.tba[8]\ : DFN1E1 - port map(D => \result[20]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[8]\); - - \r.w.result_RNISDSI[2]\ : AOI1B - port map(A => \un1_p0_6[354]\, B => d14, C => - \result_m_0_0[2]\, Y => \d_iv_0[2]\); - - \r.e.aluop_1[1]\ : DFN1E0 - port map(D => \aluop[1]\, CLK => lclk_c, E => holdn, Q => - \aluop_1[1]\); - - \r.a.bp_RNIQD984\ : OR2B - port map(A => ra_bpmiss_1_1, B => branch, Y => - \ra_bpmiss_1_0\); - - \r.a.ctrl.rd_RNITO2A1[2]\ : XA1A - port map(A => \un3_de_ren1[93]\, B => \rd[2]\, C => - un2_rs1_3_i, Y => un2_rs1_NE_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I278_Y_0_0\ : XOR2 - port map(A => \dpc[20]\, B => \inst_0[18]\, Y => - ADD_30x30_fast_I278_Y_0_0); - - \r.x.result_RNIF7GQ[6]\ : NOR2B - port map(A => \result_0[6]\, B => xc_vectt14, Y => - \xc_vectt_1[6]\); - - \r.e.op2_RNI1PJF75[31]\ : AO18 - port map(A => \un1_iu0_6[31]\, B => \eaddress[31]\, C => - \un1_iu0_5[97]\, Y => \icc_3_i_0[0]\); - - \r.e.op1_RNICHFC[8]\ : OR2B - port map(A => \op1[8]\, B => un14_casaen_s1_0, Y => - \op1_m_0[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I105_Y : AO1 - port map(A => N506, B => N503_1, C => N502_1, Y => N568_1); - - \r.w.result[1]\ : DFN1E0 - port map(D => \wdata[1]\, CLK => lclk_c, E => holdn, Q => - \result[1]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I237_Y_0_a3\ : AO1D - port map(A => ADD_30x30_fast_I239_Y_1, B => I239_un1_Y, C - => N_11, Y => N_59); - - \r.e.invop2_1_RNIBPPN3\ : MX2 - port map(A => \un6_ex_add_res_s2[4]\, B => - \un6_ex_add_res_s0[4]\, S => invop2_1, Y => N_6643); - - \r.a.ctrl.cnt_RNI041R1[0]\ : OA1A - port map(A => \alusel_i_0_a2_1_0[1]\, B => N_212, C => - N_476, Y => \alusel_i_0_o5_0[1]\); - - \r.f.pc_RNO[7]\ : OR3C - port map(A => \tmp_m[7]\, B => \pc_1_iv_1[7]\, C => - \un6_fe_npc_m[5]\, Y => \pc_1[7]\); - - \r.a.ctrl.inst_RNIE15O1[19]\ : AO1D - port map(A => \inst_2[19]\, B => illegal_inst35_4, C => - illegal_inst_7_iv_2_0_a5_0_0, Y => - illegal_inst_7_iv_2_0_a5_0_1); - - \r.x.ctrl.pc[15]\ : DFN1E0 - port map(D => \pc_3[15]\, CLK => lclk_c, E => holdn, Q => - \pc_0[15]\); - - \r.m.ctrl.rd_RNIN29A2[4]\ : XNOR2 - port map(A => \un3_de_ren1[103]\, B => \rd[4]\, Y => - un1_de_ren1_1_4_i_0); - - un6_fe_npc_I_90 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[9]\, Y => N_88); - - \r.a.ctrl.inst_RNIEC1L_0[23]\ : OR2 - port map(A => \inst_1[23]\, B => alusel24_2, Y => - illegal_inst12_0); - - \r.m.y_RNIULO71[26]\ : OR2B - port map(A => \y_1[26]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[26]\); - - un6_fe_npc_I_77 : XOR2 - port map(A => N_98, B => \fe_pc[15]\, Y => I_77); - - \r.x.result_RNINA2U4[9]\ : NOR2A - port map(A => \aluop_RNIGM3N1[2]\, B => \bpdata[9]\, Y => - \bpdata_i_m[9]\); - - \r.a.rsel2_0_RNIFA4D_0[0]\ : NOR2B - port map(A => un17_casaen_0_2, B => d26, Y => - un14_casaen_s1_0_1); - - \r.d.inst_0_RNI1DOH[15]\ : MX2 - port map(A => \inst_0[15]\, B => \inst_0[26]\, S => rs1mod, - Y => \un3_de_ren1[92]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I259_Y_3 : NOR3C - port map(A => I155_un1_Y_0, B => ADD_33x33_fast_I259_Y_1_0, - C => I211_un1_Y_0, Y => ADD_33x33_fast_I259_Y_3_0); - - \r.m.ctrl.inst[23]\ : DFN1E0 - port map(D => \inst_0[23]\, CLK => lclk_c, E => holdn, Q - => \inst_2[23]\); - - \r.e.op2_RNO_3[21]\ : OA1A - port map(A => \maddress[21]\, B => d27_0, C => - \cpi_m_i[373]\, Y => \d_1_iv_1[21]\); - - \r.a.ctrl.pc[30]\ : DFN1E0 - port map(D => \dpc[30]\, CLK => lclk_c, E => holdn, Q => - \pc[30]\); - - \r.e.op2_RNIMVGN1[21]\ : OR2A - port map(A => aluresult_7_sqmuxa, B => \un1_iu0_5[87]\, Y - => \ex_op2_m[21]\); - - \r.m.icc_RNO_11[2]\ : NOR2 - port map(A => \logicout[28]\, B => \logicout[29]\, Y => - icc_0_sqmuxa_1_10); - - \comb.branch_address.tmp_ADD_30x30_fast_I68_un1_Y\ : NOR3C - port map(A => \dpc[10]\, B => \inst_0[8]\, C => N386, Y => - I68_un1_Y); - - un6_ex_add_res_d2_ADD_33x33_fast_I229_un1_Y : NOR2A - port map(A => N658, B => N643, Y => I229_un1_Y); - - \r.m.y_RNO_1[6]\ : AOI1B - port map(A => \y_0[6]\, B => y08, C => \y_m[7]\, Y => - \y_iv_0[6]\); - - \r.f.pc_RNITQQB85[11]\ : MX2 - port map(A => I_52, B => N_4054, S => bpmiss_1_i_0, Y => - \pc_4[11]\); - - \comb.cwp_ctrl.ncwp_3_I_13\ : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[1]\, B => - \cwp_0[0]\, Y => \ncwp_3[1]\); - - \r.f.pc_RNITOA81[9]\ : MX2 - port map(A => \fpc[9]\, B => \xc_vectt_1[5]\, S => - rstate_6314_d, Y => \xc_trap_address[9]\); - - \r.x.result_RNI7Q1O3[21]\ : MX2 - port map(A => \un1_iu0_6[21]\, B => \un1_p0_6[373]\, S => - bpdata6, Y => \bpdata[21]\); - - \r.m.ctrl.inst_RNI211E_0[22]\ : NOR2 - port map(A => \inst_0[24]\, B => \inst_2[22]\, Y => - inst_2_0); - - \r.m.y_RNIT0QJF[18]\ : NOR2B - port map(A => \bpdata_m_1[2]\, B => \aluresult_1_iv_4[18]\, - Y => \aluresult_1_iv_5[18]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I308_Y_0 : AX1B - port map(A => I239_un1_Y_0, B => ADD_33x33_fast_I273_Y_0_0, - C => ADD_33x33_fast_I308_Y_0_0, Y => - \un6_ex_add_res_s1_i[18]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I139_Y : AO1 - port map(A => N540_0, B => N537_1, C => N536_1, Y => N602_0); - - \r.m.y_RNO_2[7]\ : OR2B - port map(A => \y[7]\, B => y08, Y => \y_m_0[7]\); - - \r.f.pc_RNO_8[30]\ : MX2 - port map(A => \fpc[30]\, B => \eaddress[30]\, S => jump_0, - Y => N_4073); - - \r.d.inull_RNO_2\ : NOR2A - port map(A => jmpl_2, B => trap_1, Y => de_inull_0_a3_1_0); - - \r.e.op2_RNIAK9P_0[2]\ : OR2 - port map(A => \un1_iu0_6[2]\, B => \un1_iu0_5[68]\, Y => - \logicout_3[2]\); - - \r.a.ctrl.inst_RNIJ42L[21]\ : NOR3A - port map(A => \inst_2[21]\, B => \inst_2[19]\, C => - \inst_1[24]\, Y => un1_aop2_1_sqmuxa_0_a2_0_0); - - \r.m.y_RNI04GU[0]\ : AOI1B - port map(A => \y_0[0]\, B => y08_0, C => N_468, Y => - \y_iv_0_o5_0[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I282_Y_0_0\ : XOR2 - port map(A => \dpc[24]\, B => \inst_0_0_0_RNI9O79[21]\, Y - => ADD_30x30_fast_I282_Y_0_0); - - un6_fe_npc_I_125 : AND2 - port map(A => \fe_pc[20]\, B => \fe_pc[21]\, Y => - \DWACT_FINC_E[14]\); - - \r.e.jmpl_RNIRSOT_0\ : OR2A - port map(A => miscout_11_sqmuxa, B => jmpl, Y => jmpl_0); - - \comb.op_mux.d_1_iv_RNO_0[29]\ : AND2 - port map(A => \op1_m_i[29]\, B => \d_1_iv_3[29]\, Y => - \d_1_iv_4[29]\); - - \r.a.ctrl.pc_RNI8SE2C[18]\ : MX2 - port map(A => \pc[18]\, B => N_3895, S => ex_bpmiss_1_0, Y - => \fe_pc[18]\); - - \r.e.op1_RNISTJ352[3]\ : OR3C - port map(A => \op1_m_i[3]\, B => \d_1_iv_3[3]\, C => - \aluresult_m_i[3]\, Y => \d_1[3]\); - - \r.d.inst_0_RNI4023_1[20]\ : NOR2A - port map(A => \inst_0[20]\, B => \inst_0[19]\, Y => - ticc_exception_1); - - \r.e.op1_RNIULHR3[24]\ : NOR3C - port map(A => \rfo_m[24]\, B => \d_iv_1[24]\, C => - \op1_m_0[24]\, Y => \d_iv_3[24]\); - - \r.f.pc_RNO_4[20]\ : MX2 - port map(A => I_115, B => N_4063, S => bpmiss_1_i_0_0, Y - => \pc_4[20]\); - - \r.a.ctrl.inst_RNI5C0E[21]\ : NOR2B - port map(A => \inst_2[21]\, B => \inst_2[20]\, Y => N_58); - - un6_ex_add_res_d0_ADD_33x33_fast_I4_G0N : NOR3A - port map(A => \op1[3]\, B => ldbp1_4, C => \data_0[3]\, Y - => N406); - - \un1_r.w.s.cwp_1_ANB0\ : NOR2A - port map(A => \cwp[0]\, B => \rstate_RNIRDFU5[1]\, Y => CO0); - - un6_ex_add_res_d1_ADD_33x33_fast_I121_Y : AO1B - port map(A => N522_1, B => N519_1, C => - ADD_33x33_fast_I121_Y_0_1, Y => N584_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I128_Y : OR2B - port map(A => N529_1, B => N525, Y => N591_0); - - \r.e.ctrl.pc_RNI99K11[23]\ : OR2B - port map(A => \pc_0[23]\, B => jmpl_4, Y => \cpi_m[168]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I317_Y_0 : XNOR2 - port map(A => N774_0, B => \un6_ex_add_res_s2_1[27]\, Y => - \un6_ex_add_res_s0[27]\); - - \r.e.op1_RNIQ29G[24]\ : OR2B - port map(A => \op1[24]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[24]\); - - \comb.lock_gen.un1_icc_check5_RNO_1\ : NOR2B - port map(A => N_3518_1, B => N_3736_2, Y => icc_check6_0); - - \r.e.op1_RNIU3N9F[28]\ : NOR3C - port map(A => \edata2_iv_0[28]\, B => \bpdata_i_m[28]\, C - => \edata2_iv_2[28]\, Y => edata2_iv_i_0(28)); - - \r.m.y_RNO_2[28]\ : OR2B - port map(A => \y[28]\, B => y08, Y => \y_m_0[28]\); - - \r.a.rfa2_RNILU3T1[7]\ : MX2A - port map(A => un1_reg, B => \rfa2[7]\, S => holdn, Y => - \raddr2[7]\); - - un6_fe_npc_I_172 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[19]\, Y => N_30_1); - - \r.f.pc_RNIKTGB4[12]\ : MX2 - port map(A => \dpc[12]\, B => \fpc[12]\, S => - \ra_bpmiss_1_0\, Y => N_3889); - - \r.e.shleft_1_RNILRBD1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[5]\, S => - shleft_1, Y => \shiftin_5[36]\); - - \r.a.imm_RNO[2]\ : NOR2B - port map(A => \inst_0_RNI2NUM[2]\, B => call_hold5, Y => - \un3_de_ren1[120]\); - - un2_rstn_5_RNI97F2T5 : NOR3C - port map(A => ldbp2_2_RNIFB78T1, B => m21_0, C => N_39, Y - => m21_2); - - \r.e.shcnt_RNI378QA[2]\ : MX2C - port map(A => \shiftin_11[14]\, B => \shiftin_11[10]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[10]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I26_G0N : NOR2B - port map(A => \un1_iu0_6[25]\, B => \data_0[25]\, Y => - N472_1); - - \r.m.dci.size[0]\ : DFN1E0 - port map(D => \size[0]\, CLK => lclk_c, E => holdn, Q => - \size_1[0]\); - - \r.f.pc_RNO_7[23]\ : MX2 - port map(A => \fpc[23]\, B => \tba[11]\, S => rstate_6314_d, - Y => \xc_trap_address[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I117_Y_0\ : OA1 - port map(A => \dpc[12]\, B => \inst_0[10]\, C => N392, Y - => ADD_30x30_fast_I117_Y_0); - - \r.f.pc_RNO_2[21]\ : OR2B - port map(A => I_122, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[19]\); - - \r.f.pc_RNIB8UPIA[7]\ : OR3C - port map(A => \npc_iv_1[7]\, B => \npc_iv_0[7]\, C => - \npc_iv_2[7]\, Y => rpc_5); - - \r.x.mexc_RNIK4QT\ : NOR2 - port map(A => mexc_0, B => N_3324, Y => \xc_vectt_1[5]\); - - \r.f.pc_RNO_3[29]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[29]\, C => - \xc_trap_address_m[29]\, Y => \pc_1_iv_0[29]\); - - \r.e.ctrl.tt_RNO_3[5]\ : NOR2A - port map(A => cp_disabled_4, B => trap_1, Y => - \tt_9_0_a3_0[5]\); - - \r.x.ctrl.pc_RNISB531[9]\ : MX2C - port map(A => \un1_p0_6[361]\, B => \pc_2[9]\, S => - s_3_sqmuxa_0, Y => N_3400); - - \r.m.result_RNIKL0O3[2]\ : NOR3C - port map(A => \d_1_iv_1[2]\, B => \d_1_iv_0[2]\, C => - \rfo_m_i[34]\, Y => \d_1_iv_3[2]\); - - \r.e.invop2_1_RNIGRG83\ : MX2C - port map(A => \un6_ex_add_res_s2[3]\, B => - \un6_ex_add_res_s0[3]\, S => invop2_1, Y => N_6642); - - \r.a.rfa2[0]\ : DFN1E0 - port map(D => \inst_0_RNI0FUM[0]\, CLK => lclk_c, E => - holdn, Q => \rfa2[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I69_Y\ : NOR2B - port map(A => N386, B => N383, Y => N486); - - \r.e.op1_RNIU5NPR2[9]\ : NOR3C - port map(A => \op1_m_0[9]\, B => \d_iv_2[9]\, C => - \aluresult_m_0[9]\, Y => \d_i[9]\); - - \r.d.inst_0_RNI703B[23]\ : AOI1B - port map(A => ldcheck1_5_i_a6_0_0, B => N_3737_1, C => - ldcheck1_0, Y => ldcheck1_1); - - \r.a.ctrl.rd_RNIAP4D1[7]\ : XA1A - port map(A => \un3_de_ren1[98]\, B => \rd[7]\, C => - un2_rs1_1_i, Y => un2_rs1_NE_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I248_Y : OR2 - port map(A => I248_un1_Y, B => N666_0, Y => N811_0); - - \r.x.dci.SIGNED_RNIG9LI9C\ : OR3 - port map(A => \rdata_5_m_9[8]\, B => \rdata_13_m_9[8]\, C - => \data_0_1_1[16]\, Y => \data_0_1_4[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I267_Y_0\ : XOR2 - port map(A => ADD_30x30_fast_I267_Y_0_0, B => N610, Y => - \tmp[9]\); - - \r.a.ctrl.inst[12]\ : DFN1E0 - port map(D => \inst_0[12]\, CLK => lclk_c, E => holdn, Q - => \inst[12]\); - - \r.e.op1_RNO[1]\ : MX2 - port map(A => \d[1]\, B => \d[2]\, S => N_227_0, Y => - \aop1[1]\); - - \r.x.rstate_0_RNI75KE2[0]\ : MX2C - port map(A => N_3415, B => \xc_result[24]\, S => - \rstate_0[0]\, Y => \wdata[24]\); - - \r.m.ctrl.inst_RNIB3AB3[30]\ : NOR2 - port map(A => annul_3, B => trap63, Y => iflush_4); - - \r.a.nobp_RNIM7G012\ : AO1C - port map(A => inhibit_current, B => ldlock, C => - annul_current_0, Y => annul_current); - - \r.e.op1[28]\ : DFN1E0 - port map(D => \aop1[28]\, CLK => lclk_c, E => holdn, Q => - \op1[28]\); - - \r.x.data_0_RNO_1[18]\ : NOR2A - port map(A => \data_0_0[18]\, B => ld_3, Y => - \data_0_m[18]\); - - \r.d.inst_0[18]\ : DFN1 - port map(D => \inst_0_RNO[18]\, CLK => lclk_c, Q => - \inst_0[18]\); - - \r.e.shcnt_RNIS2JO4[3]\ : MX2 - port map(A => \shiftin_8[21]\, B => \shiftin_8[13]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[13]\); - - un6_fe_npc_I_13 : XOR2 - port map(A => N_144, B => \fe_pc[5]\, Y => I_13); - - \r.f.pc_RNO_4[16]\ : MX2 - port map(A => I_84, B => N_4059, S => bpmiss_1_i_0, Y => - \pc_4[16]\); - - \r.e.shleft_0_RNIGDIM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[26]\, S => - shleft_0, Y => \shiftin_5[57]\); - - \r.e.shleft_0_RNI8NBG\ : OR2A - port map(A => \un1_iu0_6[6]\, B => shleft_0, Y => - \shiftin_5[6]\); - - \r.e.op2[29]\ : DFN1E0 - port map(D => N_313, CLK => lclk_c, E => holdn, Q => - \op2[29]\); - - \r.x.ctrl.wicc_RNIVOQU\ : NOR2A - port map(A => icc_2_sqmuxa_1, B => \rstate_d[2]\, Y => - icc_2_sqmuxa_2); - - \r.w.result_RNINJD4[25]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[25]\, - Y => \result_m_0_0[25]\); - - \r.e.op2[31]\ : DFN1E0 - port map(D => N_315, CLK => lclk_c, E => holdn, Q => - \op2[31]\); - - \r.e.ctrl.rd_RNIU7L61[0]\ : XA1C - port map(A => \rd[0]\, B => \inst_0_RNI0FUM[0]\, C => - wreg_2, Y => wreg_1_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_un1_Y : AND2 - port map(A => N811, B => ADD_33x33_fast_I264_un1_Y_0, Y => - I264_un1_Y); - - \r.m.y_RNO_0[30]\ : NOR3C - port map(A => \y_m_1[31]\, B => \y_m_0[30]\, C => - \y_iv_1[30]\, Y => \y_iv_2[30]\); - - \r.e.op2_RNO_8[19]\ : OR3B - port map(A => d29_0, B => \imm[19]\, C => \rsel2_1[0]\, Y - => \imm_m_i[19]\); - - \r.e.ctrl.rd_RNIG2T02[3]\ : XA1A - port map(A => \rd[3]\, B => \inst_0_RNI3RUM[3]\, C => - wreg_1_0, Y => wreg_1_2); - - \r.e.op2_RNO_6[14]\ : OR2B - port map(A => data2(14), B => d25_0, Y => \rfo_m_i[46]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I318_Y_0 : XOR2 - port map(A => N772_0, B => \un6_ex_add_res_s2_1[28]\, Y => - \un6_ex_add_res_s2[28]\); - - \r.e.shcnt_RNI0HEE4[3]\ : MX2 - port map(A => \shiftin_8[10]\, B => \shiftin_8[2]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0_a3\ : OR3C - port map(A => N454, B => ADD_30x30_fast_I233_Y_0_a3_0, C - => N704, Y => N_39_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I74_Y : OA1 - port map(A => \op2[10]\, B => \un1_iu0_6[10]\, C => N425_1, - Y => N533_0); - - \r.e.op2_RNO[24]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[24]\, Y => N_308); - - \r.d.inst_0[0]\ : DFN1 - port map(D => \inst_0_RNO[0]\, CLK => lclk_c, Q => - \inst_0[0]\); - - \r.e.op1[7]\ : DFN1E0 - port map(D => \aop1[7]\, CLK => lclk_c, E => holdn, Q => - \op1[7]\); - - \r.x.ctrl.inst_RNI893A1[19]\ : NOR3C - port map(A => y6_0, B => y6_0_0, C => wim_1_sqmuxa_0, Y => - y6); - - \r.f.pc_RNO_6[29]\ : MX2 - port map(A => \fpc[29]\, B => \eaddress[29]\, S => jump, Y - => N_4072); - - un6_ex_add_res_d1_ADD_33x33_fast_I262_Y_0_a3_0 : OR2A - port map(A => N502, B => N_50, Y => N_52); - - \r.m.dci.lock\ : DFN1E0 - port map(D => lock_1, CLK => lclk_c, E => holdn, Q => - lock_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I317_Y_0 : AX1B - port map(A => I264_un1_Y_1, B => ADD_33x33_fast_I264_Y_1_1, - C => ADD_33x33_fast_I317_Y_0_0, Y => - \un6_ex_add_res_s1_i[27]\); - - \r.x.result_RNIPTB25[1]\ : NOR2 - port map(A => \bpdata[1]\, B => N_3703_i, Y => - \bpdata_i_m_1[1]\); - - \r.x.rstate_RNI31F9_0[1]\ : OR2 - port map(A => \rstate[1]\, B => \rstate[0]\, Y => - \rstate_d[2]\); - - \r.e.shleft_0_RNID9IM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[16]\, S => - shleft_0, Y => \shiftin_5[47]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I57_Y : MIN3 - port map(A => \data_0_0[18]\, B => \un1_iu0_6[18]\, C => - N448_1, Y => N516_1); - - \r.x.rstate_RNITMC12[0]\ : MX2C - port map(A => N_3402, B => \xc_result[11]\, S => - \rstate[0]\, Y => \wdata[11]\); - - \r.f.pc_RNI969ADB[8]\ : OR3C - port map(A => \npc_iv_1[8]\, B => \npc_iv_0[8]\, C => - \npc_iv_2[8]\, Y => rpc_6); - - \r.d.inst_0_RNI1423[21]\ : OR2 - port map(A => \inst_0_0[22]\, B => \inst_0_0[21]\, Y => - N_122_1); - - \r.a.rfa1_RNIO0FF1[5]\ : MX2 - port map(A => \un3_de_ren1[96]\, B => \rfa1[5]\, S => holdn, - Y => raddr1(5)); - - \r.e.aluop_0_RNIRK0Q5[0]\ : MX2C - port map(A => N_3581, B => N_3645, S => \aluop_0[0]\, Y => - \logicout[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I132_Y : OR2B - port map(A => N533_0, B => N529_1, Y => N595_2); - - \r.e.jmpl_RNIEH6CF1\ : AOI1B - port map(A => \shiftin_17[16]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[15]\, Y => \aluresult_1_iv_7[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I204_Y : AO1 - port map(A => N616_0, B => N609_0, C => N608_1, Y => N674_0); - - \r.w.result_RNIKGV6[2]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[2]\, - Y => \result_m_0_0[2]\); - - \r.w.s.y_RNO[25]\ : MX2 - port map(A => \y_1[25]\, B => \result_0[25]\, S => N_481_0, - Y => N_3789); - - \r.e.jmpl_RNIRC5C_0\ : OR2 - port map(A => jmpl, B => aluresult12, Y => - aluresult_0_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I155_Y\ : NOR3C - port map(A => N462, B => N_14, C => N529, Y => N581); - - \r.x.data_0_RNO_0[5]\ : AND2 - port map(A => \dco_m_i[117]\, B => \data_0_1_1_iv_1[5]\, Y - => \data_0_1_1_iv_2[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I8_G0N : NOR2B - port map(A => \un1_iu0_6[7]\, B => \op2[7]\, Y => N418_1); - - \r.w.result_RNIQ52L[17]\ : AOI1B - port map(A => \un1_p0_6[369]\, B => d14_0, C => - \result_m_0_0[17]\, Y => \d_iv_0[17]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I28_P0N : OR2 - port map(A => \un1_iu0_6[27]\, B => \op2[27]\, Y => N479_2); - - \r.d.inst_0_RNIAJPI3[3]\ : NOR2B - port map(A => un1_rs1_2, B => un1_rs1_1, Y => un1_rs1); - - \r.m.ctrl.inst_RNI4D1E[19]\ : OR2 - port map(A => \inst_3[19]\, B => \inst_3[20]\, Y => - trap54_1517_0); - - \r.w.s.y_RNO[28]\ : MX2 - port map(A => \y_2[28]\, B => \result_0[28]\, S => N_481, Y - => N_3792); - - \r.d.pc_RNI06HB4[25]\ : MX2 - port map(A => \dpc[25]\, B => \fpc[25]\, S => ra_bpmiss_1, - Y => N_3902); - - \r.x.data_0_RNO_0[0]\ : NOR3C - port map(A => \data_0_1_1_iv_0[0]\, B => \dco_m_i[120]\, C - => \dco_m_i[112]\, Y => \data_0_1_1_iv_2[0]\); - - \r.e.ldbp2_2_RNIBLQ7L1\ : MX2C - port map(A => \un6_ex_add_res_s1_i[15]\, B => N_6634, S => - ldbp2_2, Y => \eaddress[14]\); - - \r.d.cnt[1]\ : DFN1 - port map(D => \cnt_RNO[1]\, CLK => lclk_c, Q => \cnt_0[1]\); - - \r.x.result_RNILNKU5[6]\ : OR2B - port map(A => \bpdata[6]\, B => N_3957, Y => \bpdata_m[6]\); - - \r.e.op1_RNI9OMO6[21]\ : AO1A - port map(A => \un1_iu0_6[21]\, B => edata_3_sqmuxa_0, C => - \edata2_0_iv_0[21]\, Y => \edata2_0_iv_1[21]\); - - \r.e.invop2_1_RNI58E2J1\ : MX2C - port map(A => \un6_ex_add_res_s2[18]\, B => - \un6_ex_add_res_s0[18]\, S => invop2_1, Y => N_6637); - - \r.e.op2_RNIM7MB1_0[12]\ : OR2 - port map(A => \un1_iu0_6[12]\, B => \un1_iu0_5[78]\, Y => - \logicout_3[12]\); - - \r.a.ctrl.wreg_RNO\ : NOR2 - port map(A => write_reg, B => ctrl_annul_i, Y => wreg_1_11); - - \r.e.aluop_1_RNI0DNN[1]\ : AXOI4 - port map(A => \aluop_0[2]\, B => \un1_iu0_5[90]\, C => - \aluop_1[1]\, Y => \logicout_5_0_i_0_tz[24]\); - - \r.m.y_RNO_3[21]\ : AOI1B - port map(A => \y[21]\, B => y08_0, C => \y_m_0[22]\, Y => - \y_iv_0[21]\); - - \r.e.op2_RNO_1[11]\ : OR2B - port map(A => \op1[11]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[11]\); - - \r.a.imm_RNO[14]\ : MX2 - port map(A => \inst_0_RNI4VUM[4]\, B => \un1_p0_6_0[51]\, S - => call_hold5_0, Y => \un3_de_ren1[132]\); - - \r.e.op1_RNO[19]\ : MX2C - port map(A => \d_i[19]\, B => \d_i[20]\, S => N_227_0, Y - => \aop1[19]\); - - \r.x.result_RNIDC6E[10]\ : MX2 - port map(A => \result[10]\, B => \data_0[10]\, S => ld_4, Y - => \un1_p0_6[362]\); - - \r.x.data_0_RNO_2[5]\ : AND2 - port map(A => \data_0_1_1_iv_0[5]\, B => \dco_m_i[125]\, Y - => \data_0_1_1_iv_1[5]\); - - \r.f.pc_RNO_0[10]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[10]\, C => - \pc_1_iv_0[10]\, Y => \pc_1_iv_1[10]\); - - \r.e.invop2_1\ : DFN1E0 - port map(D => N_6680, CLK => lclk_c, E => holdn, Q => - invop2_1); - - un6_fe_npc_I_72 : NOR2B - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y - => N_101); - - un6_ex_add_res_d1_ADD_33x33_fast_I268_Y_0 : AOI1 - port map(A => N658_0, B => N643_0, C => N642_0, Y => - ADD_33x33_fast_I268_Y_0_0); - - \r.e.et_RNIT1STD\ : NOR3C - port map(A => \aluresult_1_iv_4[5]\, B => - \aluresult_1_iv_3[5]\, C => \logicout_m_0[5]\, Y => - \aluresult_1_iv_6[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I93_Y : MAJ3 - port map(A => \data_0[0]\, B => \un1_iu0_6[0]\, C => alucin, - Y => N552_1); - - \r.w.s.y_RNO_0[1]\ : NOR2A - port map(A => N_481, B => \result_0[1]\, Y => N_399); - - \r.e.shcnt_RNI0710C[2]\ : MX2C - port map(A => \shiftin_11[19]\, B => \shiftin_11[15]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[15]\); - - \r.e.ctrl.inst_RNIJ3DK[26]\ : NOR2A - port map(A => N_482, B => \inst_1[26]\, Y => - ex_bpmiss_1_0_a5_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I171_Y\ : NOR2 - port map(A => N545, B => N537, Y => N597); - - un6_ex_add_res_d1_ADD_33x33_fast_I89_Y : MAJ3 - port map(A => \op2[2]\, B => \un1_iu0_6[2]\, C => N400_0, Y - => N548); - - aluresult_11_sqmuxa_5_RNIQJG41_0 : NOR3C - port map(A => aluresult_12_sqmuxa_0, B => - aluresult_12_sqmuxa_4, C => aluresult_12_sqmuxa_5, Y => - aluresult_12_sqmuxa_0_0); - - \r.e.shcnt_RNIID7HC[2]\ : MX2C - port map(A => \shiftin_11[25]\, B => \shiftin_11[21]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[21]\); - - \r.x.rstate_0_RNIVO082[0]\ : MX2C - port map(A => N_3398, B => \xc_result[7]\, S => - \rstate_0[0]\, Y => \wdata[7]\); - - \r.a.rsel1_RNI4HMVS1[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[1]\, Y => - \aluresult_m_0[1]\); - - \r.x.ctrl.wreg_RNI1S09\ : NOR2A - port map(A => wreg, B => annul_0, Y => bpdata6_0); - - \r.w.result[23]\ : DFN1E0 - port map(D => \wdata[23]\, CLK => lclk_c, E => holdn, Q => - \result_0[23]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I245_un1_Y : NOR3A - port map(A => N676, B => N595, C => N603_i, Y => I245_un1_Y); - - \r.e.op2_RNO_8[16]\ : OR3B - port map(A => d29_0, B => \imm[16]\, C => \rsel2_1[0]\, Y - => \imm_m_i[16]\); - - \r.a.ctrl.pc[19]\ : DFN1E0 - port map(D => \dpc[19]\, CLK => lclk_c, E => holdn, Q => - \pc_3[19]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I294_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[3]\, B => \data_0[3]\, Y => - \un6_ex_add_res_s2_1[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I103_un1_Y : NOR3C - port map(A => N473_2, B => N476_2, C => N504_0, Y => - I103_un1_Y); - - \r.e.shcnt_RNIV9OHL[1]\ : MX2C - port map(A => \shiftin_14[11]\, B => \shiftin_14[9]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[9]\); - - \r.f.pc_RNO_4[26]\ : MX2 - port map(A => I_166, B => N_4069, S => bpmiss_1_i_0, Y => - \pc_4[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I1_P0N : AO1A - port map(A => ldbp1_0, B => \op1[0]\, C => \data_0[0]\, Y - => N398_1); - - un2_rstn_5_0_0_RNIN7DHU5 : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[10]\, C => - \tmp_m[10]\, Y => \npc_iv_0[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I49_Y : MAJ3 - port map(A => \op2[22]\, B => \un1_iu0_6[22]\, C => N460, Y - => N508); - - \r.f.pc_RNIJNFPJ[7]\ : MX2B - port map(A => \fpc[7]\, B => \eaddress[7]\, S => jump, Y - => N_4050); - - un6_ex_add_res_d1_ADD_33x33_fast_I28_G0N : NOR2B - port map(A => \un1_iu0_6[27]\, B => \op2[27]\, Y => N478); - - \r.w.s.tba_RNIGB5BK[17]\ : NOR3C - port map(A => \bpdata_m_2[5]\, B => \aluresult_1_iv_3[29]\, - C => \aluresult_1_iv_4[29]\, Y => \aluresult_1_iv_6[29]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I70_Y : OA1 - port map(A => \data_0_2[12]\, B => \un1_iu0_6[12]\, C => - N431_2, Y => N529_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I22_G0N : NOR2B - port map(A => \un1_iu0_6[21]\, B => \op2[21]\, Y => N460); - - \r.f.pc_RNIHAASL9[6]\ : OR2 - port map(A => \pc_RNI8CM4[6]\, B => N_22, Y => N_28); - - \r.f.pc_RNO_1[28]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[28]\, C => - \pc_1_iv_0[28]\, Y => \pc_1_iv_1[28]\); - - \r.d.inst_0[25]\ : DFN1 - port map(D => \inst_0_RNO[25]\, CLK => lclk_c, Q => - \inst_0[25]\); - - un6_fe_npc_I_8 : NOR2B - port map(A => \fe_pc[3]\, B => \fe_pc[2]\, Y => N_147); - - \r.w.s.dwt_RNO_1\ : NOR3B - port map(A => dwt_1_sqmuxa_3, B => xc_wreg_0_sqmuxa, C => - y_0_sqmuxa_1, Y => dwt_1_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I93_Y : MAJ3 - port map(A => \op2[0]\, B => \un1_iu0_6[0]\, C => alucin, Y - => N552_0); - - \r.w.result_RNIOJD4[26]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => - \result_0[26]\, Y => \result_m_0_0[26]\); - - \r.m.dci.size_RNO[0]\ : NOR3 - port map(A => \size_0[0]\, B => N_3757, C => N_3755, Y => - \size[0]\); - - \r.x.npc_0_RNIDNE41[0]\ : MX2C - port map(A => N_3218, B => N_3248, S => \npc_0[0]\, Y => - \xc_result[7]\); - - \r.e.ctrl.pc_RNI85K11[22]\ : OR2B - port map(A => \pc_2[22]\, B => jmpl_4, Y => \cpi_m[167]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I119_Y : OAI1 - port map(A => N517_1, B => N520_2, C => N516_1, Y => N582_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I85_Y : MAJ3 - port map(A => \op2[4]\, B => \un1_iu0_6[4]\, C => N406_0, Y - => N544_1); - - \r.a.imm[4]\ : DFN1E0 - port map(D => \un3_de_ren1[122]\, CLK => lclk_c, E => holdn, - Q => \imm[4]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I27_G0N : NOR2A - port map(A => \un1_iu0_6[26]\, B => \data_0[26]\, Y => - N475_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I264_Y_1 : NOR3B - port map(A => I165_un1_Y_0, B => I221_un1_Y, C => N568_1, Y - => ADD_33x33_fast_I264_Y_1_0); - - \r.m.y_RNIVTO71[18]\ : OR2B - port map(A => \y_1[18]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[18]\); - - un6_fe_npc_I_118 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[13]\); - - \r.a.rfa1_RNI69T01[1]\ : MX2 - port map(A => \un3_de_ren1[92]\, B => \rfa1[1]\, S => holdn, - Y => raddr1(1)); - - \r.a.imm[19]\ : DFN1E0 - port map(D => \un3_de_ren1[137]\, CLK => lclk_c, E => holdn, - Q => \imm[19]\); - - un6_fe_npc_I_122 : XOR2 - port map(A => N_66, B => \fe_pc[21]\, Y => I_122); - - \r.e.aluop_RNIEE547[0]\ : OR2B - port map(A => \logicout[12]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[12]\); - - \r.a.ctrl.rd_RNI2B5Q4[0]\ : NOR3C - port map(A => un1_de_ren1_NE_1, B => un1_de_ren1_NE_0, C - => \rd_RNIMP6H1[7]\, Y => un1_de_ren1_NE_3); - - \r.x.y[2]\ : DFN1E0 - port map(D => \y_0[2]\, CLK => lclk_c, E => holdn, Q => - \y_2[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I45_Y : OR2 - port map(A => N469, B => I45_un1_Y, Y => N504); - - \r.e.op2[12]\ : DFN1E0 - port map(D => N_296, CLK => lclk_c, E => holdn, Q => - \op2[12]\); - - \r.e.ctrl.inst[9]\ : DFN1E0 - port map(D => \inst[9]\, CLK => lclk_c, E => holdn, Q => - \inst_1[9]\); - - \r.m.y_RNO_1[29]\ : OR2B - port map(A => \y[30]\, B => mulstep_1, Y => N_419); - - \r.m.ctrl.annul_RNI69JJ\ : OR3A - port map(A => xc_wreg9, B => annul_5, C => \rstate[1]\, Y - => annul_1tt_N_7); - - \r.a.rsel1_0_RNIPS7M2[2]\ : OR2B - port map(A => data1(1), B => d11, Y => \rfo_m[1]\); - - \r.x.result_RNI4VED[26]\ : MX2 - port map(A => \result[26]\, B => \data_0[26]\, S => ld_0, Y - => \un1_p0_6[378]\); - - \r.e.aluop_0_RNIKHN3[0]\ : NOR2 - port map(A => \aluop_0[2]\, B => \aluop_0[0]\, Y => - logicout19_0); - - \r.a.ctrl.inst_RNIJ02S_1[21]\ : OR2A - port map(A => N_207, B => N_492, Y => - un1_illegal_inst11_2_0_a5_0); - - \r.a.ctrl.inst_RNIIK1S[30]\ : OR3B - port map(A => \inst_1[24]\, B => N_202, C => \inst[30]\, Y - => N_454); - - un6_ex_add_res_d0_ADD_33x33_fast_I69_Y : AO13 - port map(A => N430_0, B => \un1_iu0_6[12]\, C => - \data_0_2[12]\, Y => N528_0); - - \r.e.ctrl.tt_RNO_0[0]\ : OR2B - port map(A => tt_9_0_1862_0, B => illegal_inst_7_i_0, Y => - \tt_RNO_0[0]\); - - \r.m.icc_RNIJ2RD1[3]\ : AOI1B - port map(A => ex_bpmiss_1_0_a5_2_1_0, B => N_248, C => - ex_bpmiss_1_0_a5_4_1, Y => ex_bpmiss_1_0_2_tz_0); - - \r.x.data_0[13]\ : DFN1E0 - port map(D => \data_0_1[13]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[13]\); - - \r.x.ctrl.pc_RNIK7AE[9]\ : MX2 - port map(A => \pc_2[9]\, B => \pc[9]\, S => \npc_0[1]\, Y - => N_3220); - - \r.e.op1_RNIRH0G6[29]\ : NOR3C - port map(A => \ex_op1_i_m[29]\, B => \op1_RNI67OF[29]\, C - => \bpdata_i_m[29]\, Y => \edata2_iv_1[29]\); - - \r.a.ctrl.inst_RNIEC1L[23]\ : OR2A - port map(A => \inst_1[23]\, B => N_203, Y => N_260); - - \r.x.npc[1]\ : DFN1E0 - port map(D => \npc_1_0[1]\, CLK => lclk_c, E => holdn, Q - => \npc[1]\); - - \r.m.ctrl.pc_RNI57AE[9]\ : MX2 - port map(A => \pc_3[9]\, B => \pc_0[9]\, S => \npc_0[1]\, Y - => N_3250); - - \r.e.op2_RNO_1[28]\ : OR2B - port map(A => \op1[28]\, B => un14_casaen_s1, Y => - \op1_m_i[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_a3_1 : NAND2 - port map(A => N401, B => ADD_33x33_fast_I206_Y_0_a3_1_0, Y - => N_57_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I43_Y : AO13 - port map(A => N469_1, B => \un1_iu0_6[25]\, C => - \data_0[25]\, Y => N502_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I26_G0N\ : NOR2B - port map(A => \inst_0_1[28]\, B => \dpc[28]\, Y => N436_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I3_G0N : OA1 - port map(A => \op1[2]\, B => ldbp1_2, C => \data_0[2]\, Y - => N403_2); - - \r.m.ctrl.inst_RNI0P0E[20]\ : OR2A - port map(A => \inst_0[24]\, B => \inst_3[20]\, Y => - trap_0_sqmuxa_1_2_i); - - \r.e.jmpl_RNILGINV3\ : OR3C - port map(A => \aluresult_1_iv_8[14]\, B => - \shiftin_17_m_0[14]\, C => \un6_ex_add_res_m[15]\, Y => - \aluresult[14]\); - - \r.f.pc[6]\ : DFN1E0 - port map(D => N_22, CLK => lclk_c, E => holdn, Q => - \fpc[6]\); - - \r.x.result_RNI5SAB3[8]\ : MX2 - port map(A => \un1_iu0_6[8]\, B => \un1_p0_6[360]\, S => - bpdata6_0_0, Y => \bpdata[8]\); - - un2_rstn_5_RNIV6DND4 : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[7]\, C => - \tmp_m[7]\, Y => \npc_iv_0[7]\); - - \r.e.op2_RNINKB71[29]\ : OR2A - port map(A => \un1_iu0_5[95]\, B => \un1_iu0_6[29]\, Y => - \logicout_4[29]\); - - \comb.op_mux.d_1_iv_RNO_6[29]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[381]\, - Y => \cpi_m_i[381]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I67_un1_Y : NOR3B - port map(A => \un1_iu0_6[12]\, B => N437, C => - \data_0_2[12]\, Y => I67_un1_Y); - - \r.x.data_0_RNO_1[3]\ : OA1A - port map(A => \data_0[3]\, B => ld_0_0, C => \dco_m_i[107]\, - Y => \data_0_1_1_iv_0[3]\); - - \r.x.data_0_RNO_1[0]\ : AOI1B - port map(A => rdata_2_sqmuxa, B => data_0_0_8, C => - \data_0_m_i[0]\, Y => \data_0_1_1_iv_0[0]\); - - \r.d.inst_0[12]\ : DFN1 - port map(D => \inst_0_0_0_RNI7TVIO2[12]\, CLK => lclk_c, Q - => \inst_0[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I232_Y_0\ : AOI1B - port map(A => \inst_0_1[30]\, B => \dpc[30]\, C => - ADD_30x30_fast_I30_un1_Y, Y => ADD_30x30_fast_I232_Y_0); - - \r.e.op2_RNIENLB1_0[10]\ : OR2 - port map(A => \un1_iu0_6[10]\, B => \un1_iu0_5[76]\, Y => - \logicout_3[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I24_P0N : OR2 - port map(A => \un1_iu0_6[23]\, B => \op2[23]\, Y => N467_0); - - \r.x.ctrl.rd_RNIFVH6[2]\ : XNOR2 - port map(A => \rd_3[2]\, B => \rd_1[2]\, Y => rd_2_i_0); - - \r.a.rfa2_RNIB7461[2]\ : MX2 - port map(A => \inst_0_RNI2NUM[2]\, B => \rfa2[2]\, S => - holdn, Y => raddr2(2)); - - \r.x.ctrl.pc_RNIVPN9[18]\ : MX2 - port map(A => \pc_2[18]\, B => \pc_0[18]\, S => \npc[1]\, Y - => N_3229); - - un6_ex_add_res_d1_ADD_33x33_fast_I237_un1_Y : NOR2B - port map(A => N666_1, B => N651_1, Y => I237_un1_Y_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I314_Y_0_1 : XOR2 - port map(A => \data_0[23]\, B => \un1_iu0_6[23]\, Y => - \un6_ex_add_res_s2_1[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I65_Y : AO13 - port map(A => N436_1, B => \un1_iu0_6[14]\, C => - \data_0[14]\, Y => N524_0); - - \r.w.s.wim_RNIISJV2[3]\ : NOR2B - port map(A => aluresult_8_sqmuxa_i, B => \wim_m[3]\, Y => - \aluresult_1_iv_0[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_un1_Y : NAND2 - port map(A => N814, B => ADD_33x33_fast_I265_un1_Y_0, Y => - I265_un1_Y_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I7_G0N : NOR2B - port map(A => \un1_iu0_6[6]\, B => \op2[6]\, Y => N415_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_un1_Y_0\ : NOR2B - port map(A => N589, B => N573, Y => - ADD_30x30_fast_I235_un1_Y_0); - - \r.x.y_RNI0QAM[0]\ : OR3A - port map(A => \y_2[0]\, B => wy_3, C => wy_1_0_1, Y => - N_465); - - \r.x.rstate_RNIORDC2[0]\ : MX2C - port map(A => N_3408, B => \xc_result[17]\, S => - \rstate[0]\, Y => \wdata[17]\); - - \r.m.y[25]\ : DFN1E0 - port map(D => \y_0[25]\, CLK => lclk_c, E => holdn, Q => - \y_2[25]\); - - \r.e.shleft_0_RNI5LHM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[20]\, S => - shleft_0, Y => \shiftin_5[51]\); - - \r.e.jmpl_RNI2ODQV\ : OR2B - port map(A => \shiftin_17[31]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[31]\); - - \r.f.pc_RNO_5[28]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[28]\, Y => \xc_trap_address_m[28]\); - - \r.e.jmpl_RNIRFSGR_0\ : OR2B - port map(A => \shiftin_17[21]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[21]\); - - \rp.error_RNO\ : OA1 - port map(A => error, B => error_1_sqmuxa, C => rst, Y => - error_RNO); - - \r.w.s.tba_RNI3K758[18]\ : NOR3C - port map(A => \aluresult_1_iv_1[30]\, B => \tba_m[18]\, C - => \bpdata_m_2[6]\, Y => \aluresult_1_iv_5[30]\); - - \r.f.pc_RNIDF56[2]\ : NOR2A - port map(A => \fpc[2]\, B => rstate_6314_d_0, Y => - \xc_trap_address_m_0[2]\); - - \r.e.alusel_RNIRC5C[0]\ : OR3B - port map(A => \alusel[0]\, B => \alusel[1]\, C => jmpl, Y - => aluresult_9_sqmuxa_1); - - \r.d.pv_RNI83B6\ : NOR2B - port map(A => pv, B => annul_2, Y => un2_exbpmiss_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0_a3_1\ : AO1C - port map(A => N433, B => I36_un1_Y_i, C => - ADD_30x30_fast_I233_Y_0_a3_0, Y => N_41); - - \r.e.shleft_1_RNIQDPK3\ : MX2 - port map(A => \shiftin_5[58]\, B => \shiftin_5[42]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[42]\); - - \r.m.y[30]\ : DFN1E0 - port map(D => \y_1[30]\, CLK => lclk_c, E => holdn, Q => - \y[30]\); - - \r.e.op2_RNO[14]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[14]\, Y => N_298); - - un6_ex_add_res_d1_ADD_33x33_fast_I122_Y_0 : OA1 - port map(A => \op2[14]\, B => \un1_iu0_6[14]\, C => N443, Y - => ADD_33x33_fast_I122_Y_0); - - \r.x.data_0_RNO_0[3]\ : NOR3C - port map(A => \data_0_1_1_iv_0[3]\, B => \dco_m_i[123]\, C - => \dco_m_i[115]\, Y => \data_0_1_1_iv_2[3]\); - - \r.e.aluop_0_RNI21JD1[1]\ : XOR3 - port map(A => \un1_iu0_6[16]\, B => \aluop_0[1]\, C => - \un1_iu0_5[82]\, Y => N_6886); - - un6_ex_add_res_d2_ADD_33x33_fast_I21_G0N : OA1 - port map(A => \op1[20]\, B => ldbp1_4, C => \data_0_2[20]\, - Y => N457_0); - - \r.m.result_RNO[13]\ : MX2 - port map(A => \aluresult[13]\, B => \op1[13]\, S => - un17_casaen_0_2, Y => \eres2[13]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I267_un1_Y : OR3C - port map(A => N641, B => N657, C => N672, Y => I267_un1_Y_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_o3 : AOI1 - port map(A => N614_0, B => N407, C => N406_0, Y => N678_i); - - \r.m.ctrl.trap_RNIF2S741\ : NOR2A - port map(A => trap2, B => annul_RNIPFOQ, Y => un1_annul); - - \r.e.aluop_0_RNIH5791[2]\ : XA1 - port map(A => \un1_iu0_5[94]\, B => \aluop_0[2]\, C => - \un1_iu0_6[28]\, Y => N_3555); - - \r.a.ctrl.inst_RNIF2TK1[26]\ : MX2C - port map(A => N_3339, B => N_3340, S => \inst_2[26]\, Y => - N_3341); - - \r.e.op2_RNO_6[11]\ : OR2B - port map(A => data2(11), B => d25_0, Y => \rfo_m_i[43]\); - - \r.d.annul_RNIVCQHS1_0\ : NOR2 - port map(A => un2_rstn_4_0, B => un2_rstn_5_2, Y => - un2_rstn_4_0_0); - - \r.m.ctrl.pc[19]\ : DFN1E0 - port map(D => \pc[19]\, CLK => lclk_c, E => holdn, Q => - \pc_2[19]\); - - \r.e.jmpl_RNI85S3N_0\ : OR2B - port map(A => \shiftin_17[10]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I264_un1_Y : NOR3B - port map(A => N651_1, B => N811_1, C => N635_1, Y => - I264_un1_Y_1); - - \r.e.op2_RNIPS4F_0[4]\ : OR2 - port map(A => \un1_iu0_6[4]\, B => \un1_iu0_5[70]\, Y => - \logicout_3[4]\); - - \r.e.op1_RNINI8G[30]\ : OR2B - port map(A => \op1[30]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[30]\); - - \r.w.result_RNIB8P1[31]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[31]\, Y - => \result_m_0[31]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I269_Y_0_0\ : XOR2 - port map(A => \dpc[11]\, B => \inst_0[9]\, Y => - ADD_30x30_fast_I269_Y_0_0); - - \r.e.ctrl.inst_RNIIULP85[22]\ : AO1B - port map(A => un1_icc_2_sqmuxa_1, B => un3_notag, C => - \icc_2[1]\, Y => \icc_2_m[1]\); - - \r.m.result[16]\ : DFN1E0 - port map(D => \eres2[16]\, CLK => lclk_c, E => holdn, Q => - \maddress[16]\); - - \r.e.op1_RNIK24U1[5]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[5]\, C => - \ex_op1_i_m[5]\, Y => \edata2_0_iv_0[5]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I16_P0N : OR3A - port map(A => \data_0_2[15]\, B => \op1[15]\, C => ldbp1_3, - Y => N443_0); - - \r.x.dci.SIGNED_RNI32NV72\ : NOR2B - port map(A => \rdata_13[8]\, B => rdata_2_sqmuxa, Y => - \rdata_13_m[8]\); - - \r.d.inst_0_RNO_0[16]\ : MX2 - port map(A => data_0_0_16, B => \inst_0[16]\, S => - mexc_1_sqmuxa_1_0, Y => N_4616); - - un6_ex_add_res_d0_ADD_33x33_fast_I4_P0N : OR3A - port map(A => \data_0[3]\, B => \op1[3]\, C => ldbp1_4, Y - => N407_2); - - \r.f.pc_RNO_0[16]\ : NAND2 - port map(A => \tmp[16]\, B => un2_rstn_5_0, Y => - \tmp_m[16]\); - - \r.m.result_RNI9T3I3[7]\ : NOR3C - port map(A => \d_iv_0[7]\, B => \result_m_0[7]\, C => - \rfo_m[7]\, Y => \d_iv_2[7]\); - - \r.e.invop2_1_RNIUM5NA\ : MX2 - port map(A => \un6_ex_add_res_s2[9]\, B => - \un6_ex_add_res_s0[9]\, S => invop2_1, Y => N_6555); - - \r.m.result_RNO[6]\ : MX2 - port map(A => \aluresult[6]\, B => \op1[6]\, S => - un17_casaen_0_2, Y => \eres2[6]\); - - \r.x.data_0_RNO_2[9]\ : NOR2A - port map(A => \data_0[9]\, B => ld_3, Y => \data_0_m[9]\); - - \r.f.pc_RNO_4[30]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[30]\, Y => \xc_trap_address_m[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I130_Y : AND2 - port map(A => N527, B => ADD_33x33_fast_I130_Y_0, Y => N593); - - \r.m.result_RNIVU7B3[16]\ : NOR3C - port map(A => \d_iv_0[16]\, B => \result_m_0[16]\, C => - \rfo_m[16]\, Y => \d_iv_2[16]\); - - \r.e.op1_RNI064B2[25]\ : OA1A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[25]\, C => - \op1_RNI2NNF[25]\, Y => \edata2_iv_0[25]\); - - \r.e.invop2_1_RNIHGG322\ : MX2C - port map(A => \un6_ex_add_res_s2[22]\, B => - \un6_ex_add_res_s0[22]\, S => invop2_1, Y => N_6568); - - un6_fe_npc_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \fe_pc[11]\, C => - \fe_pc[12]\, Y => N_106); - - un54_ra_I_1 : AND2 - port map(A => \ncwp[0]\, B => N_79, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - \r.m.dci.read\ : DFN1E0 - port map(D => read, CLK => lclk_c, E => holdn, Q => read_1); - - \r.d.pc_RNISJBA4[5]\ : MX2 - port map(A => \dpc[5]\, B => \fpc[5]\, S => ra_bpmiss_1, Y - => N_3882); - - \r.x.dci.SIGNED_RNII78BD3\ : NOR2B - port map(A => \rdata_13[8]\, B => N_3480, Y => - \rdata_13_m_9[8]\); - - \r.a.ctrl.inst_RNIJG131[20]\ : NOR3A - port map(A => \inst_2[20]\, B => N_201, C => inst_9_3, Y - => aluop_1_1_0_a5_0_0); - - \r.e.op2_RNINKB71_0[29]\ : OR2 - port map(A => \un1_iu0_6[29]\, B => \un1_iu0_5[95]\, Y => - \logicout_3[29]\); - - \r.m.y_RNI3J9F[1]\ : OR2B - port map(A => \y[1]\, B => mulstep_1, Y => N_468); - - \r.e.ctrl.wicc_RNI2M0DB8\ : MX2 - port map(A => N_4188, B => N_4178, S => wicc_2, Y => - \icco[3]\); - - \r.e.ctrl.pc_RNI5TJ11[10]\ : OR2B - port map(A => \pc_0[10]\, B => jmpl_4, Y => \cpi_m[155]\); - - \r.w.s.tba_RNID84T9[15]\ : NOR3C - port map(A => \tba_m[15]\, B => \aluop_RNI5N3F4[1]\, C => - \bpdata_m_2[3]\, Y => \aluresult_0_iv_5[27]\); - - \r.f.pc_RNI58041[8]\ : MX2 - port map(A => \fpc[8]\, B => \xc_vectt_1[4]\, S => - rstate_6314_d_0, Y => \xc_trap_address[8]\); - - \r.e.op2_RNO_2[9]\ : OR2B - port map(A => data2(9), B => d25_0, Y => \rfo_m_i[41]\); - - \r.m.ctrl.trap_RNI1LRM8\ : OR2B - port map(A => trap_1_sqmuxa, B => trap_2_0, Y => - nullify_1_sqmuxa); - - \r.d.pc[28]\ : DFN1 - port map(D => \pc_RNO[28]\, CLK => lclk_c, Q => \dpc[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I198_Y : NOR3C - port map(A => N535_1, B => ADD_33x33_fast_I138_Y_0_0, C => - N609, Y => N667_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I25_P0N : NOR3A - port map(A => \data_0[24]\, B => \op1[24]\, C => ldbp1_4, Y - => N470_1); - - \r.e.op2_RNO[0]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[0]\, Y => N_284); - - \r.e.op1_RNIG93B2[12]\ : AO1A - port map(A => \op1[12]\, B => \un17_casaen_0_0\, C => - \ex_op1_i_m[12]\, Y => \edata2_0_iv_0[12]\); - - \r.x.result[31]\ : DFN1E0 - port map(D => \maddress[31]\, CLK => lclk_c, E => holdn, Q - => \result_0[31]\); - - \r.a.rsel2_0_RNI7V53_1[0]\ : NOR2B - port map(A => \rsel2_0[0]\, B => d26_0, Y => d26); - - \comb.misc_op.miscout140\ : OR2 - port map(A => miscout140_1, B => \aluop_0[0]\, Y => - miscout140); - - \r.d.inst_0_RNO_0[4]\ : MX2 - port map(A => data_0_2_4, B => \inst_0[4]\, S => - mexc_1_sqmuxa_1_0, Y => N_4604); - - \r.e.op1_RNI0JCR1[26]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[26]\, Y => - \ex_op1_i_m[26]\); - - un6_fe_npc_I_199 : AND2 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - Y => \DWACT_FINC_E[24]\); - - \r.f.pc_RNO_7[13]\ : MX2 - port map(A => \fpc[13]\, B => \tba[1]\, S => - rstate_6314_d_0, Y => \xc_trap_address[13]\); - - \r.d.pv_RNO_3\ : NOR2B - port map(A => un23_exbpmiss_i_0, B => un9_rabpmiss, Y => - pv_0); - - \r.x.result_RNIPK6E[23]\ : MX2 - port map(A => \result[23]\, B => \data_0[23]\, S => ld_4, Y - => \un1_p0_6[375]\); - - \r.w.s.y_RNO[3]\ : MX2 - port map(A => \y_2[3]\, B => \result_0[3]\, S => N_481_0, Y - => N_3767); - - \r.d.pc[11]\ : DFN1 - port map(D => \pc_RNO[11]\, CLK => lclk_c, Q => \dpc[11]\); - - \r.d.pc_RNO[3]\ : MX2 - port map(A => \fpc[3]\, B => \dpc[3]\, S => N_6763_i_0, Y - => \pc_RNO[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I310_Y_0_1 : XOR2 - port map(A => \op1_RNID1VH[19]\, B => \data_0[19]\, Y => - \un6_ex_add_res_s2_1[20]\); - - \r.m.result_RNI5PR73[12]\ : NOR3C - port map(A => \d_iv_0[12]\, B => \result_m_0[12]\, C => - \rfo_m[12]\, Y => \d_iv_2[12]\); - - \r.a.ctrl.inst_RNIQG231[24]\ : OR3 - port map(A => N_241, B => \inst_1[24]\, C => N_212, Y => - N_469); - - \r.x.ctrl.inst_RNI023H1[22]\ : NOR3C - port map(A => y15, B => cwp_2_sqmuxa_1, C => cwp_2_sqmuxa_2, - Y => cwp_2_sqmuxa_4); - - \r.m.y_RNO[22]\ : OR3C - port map(A => \y_iv_1[22]\, B => \y_iv_0[22]\, C => - \logicout_m[22]\, Y => \y_1[22]\); - - \r.e.shcnt_RNI9K75G[2]\ : MX2 - port map(A => \shiftin_11[38]\, B => \shiftin_11[34]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[34]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I77_Y : MAJ3 - port map(A => \data_0[8]\, B => \un1_iu0_6[8]\, C => N418, - Y => N536_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I30_P0N : OR2A - port map(A => \data_0_0[29]\, B => \un1_iu0_6[29]\, Y => - N485); - - \r.w.s.wim[5]\ : DFN1E0 - port map(D => \wim_1[5]\, CLK => lclk_c, E => holdn, Q => - \wim[5]\); - - \r.x.ctrl.pc[26]\ : DFN1E0 - port map(D => \pc_3[26]\, CLK => lclk_c, E => holdn, Q => - \pc_2[26]\); - - \r.x.ctrl.wicc_RNISFUM2\ : OA1 - port map(A => icc_0_sqmuxa_0, B => rstate_7_0, C => rst, Y - => icc_1_sqmuxa); - - \r.e.aluop_0_RNIILNS3[0]\ : OR2B - port map(A => \logicout[7]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[7]\); - - \r.w.result_RNILND4[30]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[30]\, - Y => \result_m_0_0[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I74_Y : NOR2B - port map(A => N428_0, B => N425_0, Y => N533); - - \r.e.op2_RNO_8[20]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[372]\, - Y => \cpi_m_i[372]\); - - \r.e.ldbp2_1_RNIKNA7L3\ : MX2C - port map(A => \un6_ex_add_res_s1_i[24]\, B => N_6570, S => - ldbp2_1, Y => \eaddress[23]\); - - \r.e.ctrl.pc[31]\ : DFN1E0 - port map(D => \pc_0[31]\, CLK => lclk_c, E => holdn, Q => - \pc[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I116_Y : NOR2B - port map(A => N517_0, B => N513_1, Y => N579_2); - - \r.m.y_RNI94K91[3]\ : OR2B - port map(A => \y_1[3]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[3]\); - - \r.m.y_RNI02P71[19]\ : OR2B - port map(A => \y_0[19]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[19]\); - - \r.a.imm_RNO[8]\ : NOR2B - port map(A => \inst_0[8]\, B => call_hold5, Y => - \un3_de_ren1[126]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I137_Y_0 : AO13 - port map(A => N421, B => \un1_iu0_6[9]\, C => \data_0[9]\, - Y => ADD_33x33_fast_I137_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I189_Y : OR2A - port map(A => I189_un1_Y_i, B => N592, Y => N658_1); - - \r.w.s.tba_RNI84CA1[7]\ : NAND2 - port map(A => aluresult_12_sqmuxa_0_0, B => \tba[7]\, Y => - \tba_m[7]\); - - \r.m.ctrl.ld_RNIHU879_0\ : OR2 - port map(A => ld, B => dco_i_2(132), Y => ld_0_0); - - \r.e.aluop_RNI1UQR4[2]\ : OR2B - port map(A => \bpdata[15]\, B => aluresult_5_sqmuxa, Y => - \bpdata_m_0[15]\); - - \r.e.aluop_0_RNIRDEVH[0]\ : NOR3C - port map(A => \logicout_m_0[0]\, B => \aluresult_2_iv_4[0]\, - C => \bpdata_m[0]\, Y => \aluresult_2_iv_6[0]\); - - \r.x.result[16]\ : DFN1E0 - port map(D => \maddress[16]\, CLK => lclk_c, E => holdn, Q - => \result_0[16]\); - - \r.w.s.ps_RNO\ : OR2A - port map(A => rst, B => N_4993, Y => ps_RNO); - - \r.m.y[15]\ : DFN1E0 - port map(D => \y_0[15]\, CLK => lclk_c, E => holdn, Q => - \y[15]\); - - \r.e.op2_RNIHMUD4[3]\ : AOI1B - port map(A => \un1_iu0_5[69]\, B => aluresult_7_sqmuxa_0_0, - C => \aluresult_1_iv_0[3]\, Y => \aluresult_1_iv_1[3]\); - - \r.d.inull_RNO_0\ : AO1D - port map(A => rett_1, B => de_inull_0_a3_1_0, C => jmpl_1, - Y => de_inull_0_2004_0); - - \r.d.inst_0_RNID24008[29]\ : MX2C - port map(A => un1_annul_next_1_sqmuxa_3, B => \inst_0[29]\, - S => annul_next_2_sqmuxa_1, Y => annul_next_14); - - un6_fe_npc_I_169 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \fe_pc[26]\, Y => \DWACT_FINC_E[19]\); - - \r.m.y_RNO_1[26]\ : OR2B - port map(A => \y_0[27]\, B => mulstep_0, Y => \y_m[27]\); - - \r.e.ctrl.pc[26]\ : DFN1E0 - port map(D => \pc_0[26]\, CLK => lclk_c, E => holdn, Q => - \pc[26]\); - - \r.e.op2_RNO_5[18]\ : AOI1B - port map(A => \result[18]\, B => d31, C => \imm_m_i[18]\, Y - => \d_1_iv_0[18]\); - - \r.d.pc_RNIS5HB4[23]\ : MX2 - port map(A => \dpc[23]\, B => \fpc[23]\, S => ra_bpmiss_1, - Y => N_3900); - - un6_fe_npc_I_155 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[33]\, Y => N_42); - - \r.e.shcnt_RNI98VRI[1]\ : MX2C - port map(A => \shiftin_14[2]\, B => \shiftin_14[0]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[0]\); - - \r.a.ctrl.pc_RNISBE2C[14]\ : MX2 - port map(A => \pc[14]\, B => N_3891, S => ex_bpmiss_1, Y - => \fe_pc[14]\); - - \r.a.ctrl.inst_RNI7K0E_0[21]\ : NOR2B - port map(A => \inst_2[21]\, B => \inst[22]\, Y => - illegal_inst35_4_0); - - \r.x.ctrl.inst_RNILL0E[21]\ : NOR2 - port map(A => \inst_0[22]\, B => \inst_0[21]\, Y => - wim_1_sqmuxa_0); - - \r.e.ctrl.pc_RNIA8TN2[30]\ : NOR2A - port map(A => \cpi_m[175]\, B => \aluresult_6[31]\, Y => - \aluresult_1_iv_1[30]\); - - \r.f.pc_RNO_1[21]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[21]\, C => - \pc_1_iv_0[21]\, Y => \pc_1_iv_1[21]\); - - \r.a.bp_RNIFI8U\ : OR3C - port map(A => \inst[29]\, B => bp, C => un8_op, Y => - un5_ldlock); - - \r.m.y_RNO_3[29]\ : AOI1B - port map(A => wy_1_0, B => \y_0[29]\, C => N_417, Y => - \y_iv_0_1[29]\); - - \r.e.aluop_2_RNIPRDM1[1]\ : MX2C - port map(A => N_3535, B => \logicout_3[8]\, S => - \aluop_2[1]\, Y => N_3567); - - \comb.branch_address.tmp_ADD_30x30_fast_I132_Y\ : AO1 - port map(A => N497_1, B => N494, C => - ADD_30x30_fast_I132_Y_0, Y => N552_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I103_Y : AO1A - port map(A => N501, B => N504, C => N500_1, Y => N566_0); - - un2_rstn_5_RNISAMP : NAND2 - port map(A => \tmp[2]\, B => \un2_rstn_5\, Y => \tmp_m[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I220_Y_0_o3\ : AOI1 - port map(A => N735, B => N392, C => N391, Y => N732_i); - - \r.w.s.tba[14]\ : DFN1E1 - port map(D => \result[26]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[14]\); - - \r.f.pc_RNO_6[14]\ : MX2 - port map(A => \fpc[14]\, B => \eaddress[14]\, S => jump, Y - => N_4057); - - \r.e.shcnt_RNID7Q6E[2]\ : MX2C - port map(A => \shiftin_11[30]\, B => \shiftin_11[26]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[26]\); - - \r.a.imm[15]\ : DFN1E0 - port map(D => \un3_de_ren1[133]\, CLK => lclk_c, E => holdn, - Q => \imm[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I298_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[8]\, B => N672_1, Y => - \un6_ex_add_res_s0[8]\); - - \r.a.ctrl.inst_RNI9S0E[21]\ : OR2B - port map(A => \inst_1[24]\, B => \inst_2[21]\, Y => N_203); - - \r.x.npc_RNIQQBL[0]\ : MX2C - port map(A => N_3222, B => N_3252, S => \npc[0]\, Y => - \xc_result[11]\); - - \r.e.alucin_RNO_6\ : NOR2A - port map(A => \inst[22]\, B => \inst[30]\, Y => - cin_iv_i_a5_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I179_un1_Y : NOR2B - port map(A => N590_0, B => N583_1, Y => I179_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I267_Y_0 : AOI1B - port map(A => N656_0, B => N641_0, C => N640, Y => - ADD_33x33_fast_I267_Y_0); - - \r.m.result_RNO[7]\ : MX2 - port map(A => \aluresult[7]\, B => \op1[7]\, S => - un17_casaen_0_2, Y => \eres2[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I155_un1_Y : AO1C - port map(A => N500, B => I103_un1_Y_i, C => N559, Y => - I155_un1_Y); - - \r.m.ctrl.pc_RNI4QHF[26]\ : MX2 - port map(A => \pc_3[26]\, B => \pc_0[26]\, S => \npc_1[1]\, - Y => N_3267); - - \r.e.aluop_RNIIRTL9[1]\ : OA1A - port map(A => N_3974, B => \bpdata[12]\, C => - \bpdata_m_2[4]\, Y => \aluresult_1_iv_4[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I82_Y\ : MAJ3 - port map(A => \dpc[4]\, B => \inst_0_RNI2NUM[2]\, C => N361, - Y => N499); - - \r.w.s.tba_RNIF87ON[9]\ : NOR3C - port map(A => \aluresult_1_iv_5[21]\, B => \bpdata_m_1[5]\, - C => \logicout_m_0[21]\, Y => \aluresult_1_iv_7[21]\); - - \r.f.pc_RNIRJ9HO4[10]\ : MX2 - port map(A => I_45, B => N_4053, S => bpmiss_1_i_0_0, Y => - \pc_4[10]\); - - \r.w.s.tba[9]\ : DFN1E1 - port map(D => \result_0[21]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[9]\); - - \r.e.shcnt_RNISH246[3]\ : MX2 - port map(A => \shiftin_8[28]\, B => \shiftin_8[20]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[20]\); - - \r.x.data_0[21]\ : DFN1E0 - port map(D => \data_0_1[21]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[21]\); - - \r.m.result[24]\ : DFN1E0 - port map(D => \eres2[24]\, CLK => lclk_c, E => holdn, Q => - \maddress[24]\); - - \r.e.shleft_1_RNIPS4L\ : OR2A - port map(A => \un1_iu0_6[30]\, B => shleft_1, Y => - \shiftin_5[30]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I238_Y\ : OR3C - port map(A => I202_un1_Y_i, B => ADD_30x30_fast_I238_Y_0, C - => I238_un1_Y, Y => N706); - - \r.e.ctrl.annul\ : DFN1E0 - port map(D => N_149, CLK => lclk_c, E => holdn, Q => annul); - - \r.e.aluop_RNI7L034[1]\ : NAND2 - port map(A => aluresult_4_sqmuxa, B => \bpdata[0]\, Y => - \bpdata_m_2[0]\); - - \r.d.inst_0_RNO[24]\ : NOR2B - port map(A => rst, B => N_4624, Y => \inst_0_RNO[24]\); - - \r.m.ctrl.wicc_RNO\ : NOR2A - port map(A => wicc_2, B => \un1_p0_6[0]\, Y => wicc_1_1); - - un2_rstn_5_0_0 : NOR2 - port map(A => un2_rstn_5_2, B => \un2_rstn_5_0_0\, Y => - un2_rstn_5_0); - - \r.e.op2_RNO_5[26]\ : NOR2B - port map(A => \imm_m_i[26]\, B => \result_m_i[26]\, Y => - \d_1_iv_0[26]\); - - \rp.error\ : DFN1 - port map(D => error_RNO, CLK => lclk_c, Q => error); - - \r.d.inst_0_RNI4TR42[3]\ : NOR2A - port map(A => un1_rs1_0, B => \inst_0_RNI3RUM[3]\, Y => - un1_rs1_2); - - \r.x.ctrl.rd_RNI7SGO[3]\ : NOR2B - port map(A => \rd_2[3]\, B => N_6357, Y => waddr(3)); - - \r.w.s.y[23]\ : DFN1E0 - port map(D => N_3787, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[23]\); - - \r.f.pc_RNO_2[18]\ : OR2B - port map(A => I_98, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[16]\); - - \r.x.result_RNI7KU63[9]\ : MX2 - port map(A => \un1_iu0_6[9]\, B => \un1_p0_6[361]\, S => - bpdata6_0_0, Y => \bpdata[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I191_Y : AO1D - port map(A => N602_1, B => N595, C => N594_2, Y => N660_1); - - \r.e.aluop_RNI0RJD4[1]\ : NOR2A - port map(A => edata_2_sqmuxa, B => \bpdata[23]\, Y => - \bpdata_i_m[23]\); - - \r.d.inst_0_RNI8AJ4[27]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[27]\, S => - \inst_0[30]\, Y => \inst_0_RNI8AJ4[27]\); - - \r.e.op2_RNO_1[30]\ : OR2B - port map(A => \op1[30]\, B => un14_casaen_s1, Y => - \op1_m_i[30]\); - - \r.x.ctrl.tt_RNO_1[0]\ : MX2C - port map(A => \tt_0[0]\, B => irl_0(0), S => tt_1_sqmuxa_1, - Y => N_4204); - - \r.f.pc_RNO_7[30]\ : MX2 - port map(A => \fpc[30]\, B => \tba[18]\, S => - rstate_6314_d_0, Y => \xc_trap_address[30]\); - - \r.x.laddr_RNIFVAM63[0]\ : OR3 - port map(A => rdata_3_sqmuxa, B => rdata_4_sqmuxa, C => - rdata_6_sqmuxa, Y => N_3456); - - \r.x.result_RNIPKPCK[2]\ : MX2C - port map(A => \result_0[2]\, B => N_6529, S => - cwp_1_sqmuxa_0, Y => N_3872); - - \r.e.ctrl.inst[8]\ : DFN1E0 - port map(D => \inst[8]\, CLK => lclk_c, E => holdn, Q => - \inst_1[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I17_G0N : OA1 - port map(A => \op1[16]\, B => ldbp1_4, C => \data_0[16]\, Y - => N445); - - \r.e.op1_RNIFN41T1[1]\ : MX2 - port map(A => \aluresult[1]\, B => \op1[1]\, S => - un17_casaen_0, Y => \eres2[1]\); - - \r.e.shcnt[2]\ : DFN1E0 - port map(D => N_268_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[2]\); - - \r.e.op1_RNICTUH[18]\ : MX2 - port map(A => \op1[18]\, B => \data_0_0[18]\, S => ldbp1_3, - Y => \un1_iu0_6[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I238_un1_Y\ : OR3C - port map(A => N579, B => N595_0, C => N610, Y => I238_un1_Y); - - \r.x.ctrl.pc[12]\ : DFN1E0 - port map(D => \pc_3[12]\, CLK => lclk_c, E => holdn, Q => - \pc_0[12]\); - - \r.f.pc[22]\ : DFN1E0 - port map(D => \pc_1[22]\, CLK => lclk_c, E => holdn, Q => - \fpc[22]\); - - \r.w.result_RNIP407[7]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[7]\, - Y => \result_m_0_0[7]\); - - \r.e.op2_RNIHB971[11]\ : OR2A - port map(A => \un1_iu0_5[77]\, B => \un1_iu0_6[11]\, Y => - \logicout_4[11]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I20_P0N : OR3A - port map(A => \data_0[19]\, B => \op1[19]\, C => ldbp1_0, Y - => N455_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I113_Y : AO1B - port map(A => N514_0, B => N511_0, C => - ADD_33x33_fast_I113_Y_0, Y => N576_0); - - \r.a.ctrl.inst_RNIU43A1[22]\ : NOR3 - port map(A => N_472, B => \inst[22]\, C => N_260, Y => - illegal_inst38); - - \r.x.result[4]\ : DFN1E0 - port map(D => \maddress[4]\, CLK => lclk_c, E => holdn, Q - => \result[4]\); - - \r.m.y_RNO_2[27]\ : OR2A - port map(A => \logicout[27]\, B => y14, Y => N_420); - - \comb.branch_address.tmp_ADD_30x30_fast_I114_Y\ : OR2 - port map(A => N475, B => I114_un1_Y, Y => N534); - - \r.x.data_0_RNO_0[20]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_20, Y => - \dco_m_0[116]\); - - \r.m.y_RNO_4[7]\ : OR3A - port map(A => \y_2[7]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_1[7]\); - - \r.x.ctrl.tt_RNO_0[1]\ : MX2C - port map(A => irl_0(1), B => \tt_2[1]\, S => tt_0_sqmuxa, Y - => N_4205); - - \r.f.pc_RNO_5[21]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[21]\, Y => \xc_trap_address_m[21]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I317_Y_0 : XOR2 - port map(A => N774, B => \un6_ex_add_res_s2_1[27]\, Y => - \un6_ex_add_res_s2[27]\); - - \r.x.data_0_RNO_1[11]\ : AO1A - port map(A => rdata_5_sqmuxa, B => data_0_0_27, C => - \data_0_m[11]\, Y => \data_0_1_0_iv_0[11]\); - - \r.e.ctrl.pc[3]\ : DFN1E0 - port map(D => \pc[3]\, CLK => lclk_c, E => holdn, Q => - \pc_0[3]\); - - \r.e.ymsb\ : DFN1E0 - port map(D => \d[0]\, CLK => lclk_c, E => holdn, Q => ymsb); - - \comb.branch_address.tmp_ADD_30x30_fast_I137_Y\ : OR2A - port map(A => I137_un1_Y_i, B => N499, Y => N558); - - un6_ex_add_res_d0_ADD_33x33_fast_I53_Y : AO13 - port map(A => N454_0, B => \un1_iu0_6[20]\, C => - \data_0_2[20]\, Y => N512); - - annul_current_3_sqmuxa_1 : OR2A - port map(A => un5_exbpmiss_i_0, B => call_hold7_i, Y => - \annul_current_3_sqmuxa_1\); - - \r.m.result_RNI18P1[31]\ : OR2B - port map(A => d13, B => \maddress[31]\, Y => - \result_m_0_0[31]\); - - \r.e.ctrl.pc_RNICJD92[27]\ : AOI1B - port map(A => \pc[27]\, B => jmpl_0, C => \y_m_1[27]\, Y - => \aluresult_0_iv_1[27]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I311_Y_0_0 : XOR2 - port map(A => \op2[20]\, B => \un1_iu0_6[20]\, Y => - ADD_33x33_fast_I311_Y_0_0); - - \r.e.op2[1]\ : DFN1E0 - port map(D => N_285, CLK => lclk_c, E => holdn, Q => - \op2[1]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_11\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => un2_irl); - - \r.e.aluadd_RNIMCA2F5\ : MX2C - port map(A => \logicout[20]\, B => \icc_16[0]\, S => - un3_op_i, Y => N_4175); - - \r.e.op2_RNO_0[10]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[10]\, C - => \d_1_iv_4[10]\, Y => \d_1[10]\); - - \r.x.ctrl.inst[20]\ : DFN1E0 - port map(D => \inst_3[20]\, CLK => lclk_c, E => holdn, Q - => \inst[20]\); - - \r.w.s.pil[3]\ : DFN1E0 - port map(D => \result_0[11]\, CLK => lclk_c, E => N_6699, Q - => \pil[3]\); - - \r.f.pc_RNIHO981[5]\ : MX2B - port map(A => \fpc[5]\, B => \xc_vectt_1[1]\, S => - rstate_6314_d, Y => \xc_trap_address[5]\); - - \r.e.op1[20]\ : DFN1E0 - port map(D => \aop1[20]\, CLK => lclk_c, E => holdn, Q => - \op1[20]\); - - \r.e.invop2_0_RNISJIJ\ : XNOR3 - port map(A => invop2_0, B => \un6_ex_add_res_s0_0_0[1]\, C - => \un1_iu0_6[0]\, Y => N_6640_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I266_Y_0_o3 : AO1 - port map(A => N_74_1, B => N782_0, C => N506_1, Y => N778_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I316_Y_0 : XOR2 - port map(A => N776, B => \un6_ex_add_res_s2_1[26]\, Y => - \un6_ex_add_res_s2[26]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I205_Y : OR2 - port map(A => N610_1, B => I205_un1_Y_0, Y => N676_0); - - \r.w.s.pil_RNI06V28[1]\ : NOR3C - port map(A => \pil_m[1]\, B => \aluresult_1_iv_0[9]\, C => - \bpdata_m[9]\, Y => \aluresult_1_iv_4[9]\); - - \r.x.dci.SIGNED_RNII2M614\ : AOI1B - port map(A => rdata_5_sqmuxa, B => rdata_0_sqmuxa, C => - \rdata_5[8]\, Y => \rdata_5_m_9[8]\); - - \r.x.data_0_RNIDN9E[31]\ : XOR2 - port map(A => \data_0_0[31]\, B => invop2_0, Y => N_4278); - - \r.e.aluop_RNI2SUL9[1]\ : OA1A - port map(A => N_3974, B => \bpdata[14]\, C => - \bpdata_m_2[6]\, Y => \aluresult_1_iv_5[14]\); - - \r.e.shcnt_RNIQ376K[1]\ : MX2C - port map(A => \shiftin_14[7]\, B => \shiftin_14[5]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[5]\); - - \r.m.y_RNIG37P6[22]\ : AOI1B - port map(A => \bpdata[22]\, B => aluresult_6_sqmuxa, C => - \aluresult_1_iv_1[22]\, Y => \aluresult_1_iv_3[22]\); - - \r.f.pc_RNO[23]\ : OR3C - port map(A => \tmp_m[23]\, B => \pc_1_iv_1[23]\, C => - \un6_fe_npc_m[21]\, Y => \pc_1[23]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I311_Y_0 : AX1B - port map(A => N514_0, B => N_71, C => - \un6_ex_add_res_s2_1[21]\, Y => \un6_ex_add_res_s0[21]\); - - \r.a.rfa1_RNI9DT01[2]\ : MX2 - port map(A => \un3_de_ren1[93]\, B => \rfa1[2]\, S => holdn, - Y => raddr1(2)); - - un6_ex_add_res_d2_ADD_33x33_fast_I7_P0N : OR2 - port map(A => \un1_iu0_6[6]\, B => \data_0[6]\, Y => N416); - - \r.e.op2_RNIDHIG[8]\ : MX2 - port map(A => \op2[8]\, B => N_4255, S => ldbp2_0, Y => - \un1_iu0_5[74]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I23_P0N\ : OR2 - port map(A => \inst_0_1[25]\, B => \dpc[25]\, Y => N428); - - \r.e.op2_RNIVIOP[16]\ : MX2 - port map(A => \op2[16]\, B => N_4263, S => ldbp2_0, Y => - \un1_iu0_5[82]\); - - \r.w.result[3]\ : DFN1E0 - port map(D => \wdata[3]\, CLK => lclk_c, E => holdn, Q => - \result[3]\); - - \r.e.ctrl.tt_RNO_1[1]\ : OR2 - port map(A => \tt_0[2]\, B => N_4036, Y => \tt_0[1]\); - - \r.a.ctrl.inst_RNIDG9A[29]\ : NOR2B - port map(A => \inst[29]\, B => pv, Y => un9_rabpmiss_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I212_un1_Y\ : NOR2B - port map(A => N604, B => N589, Y => I212_un1_Y); - - \r.d.pc_RNIURBA4[6]\ : MX2 - port map(A => \dpc[6]\, B => \fpc[6]\, S => \ra_bpmiss_1_0\, - Y => N_3883); - - un6_fe_npc_I_20 : XOR2 - port map(A => N_139, B => \fe_pc[6]\, Y => I_20); - - un6_ex_add_res_d2_ADD_33x33_fast_I206_Y_0_a3_1 : OR3C - port map(A => N398_1, B => alucin, C => N401_0, Y => N_57); - - \r.e.op1_RNISE9G[17]\ : OR2B - port map(A => \op1[17]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[17]\); - - \r.w.s.wim_RNIGJ4N2[5]\ : MX2 - port map(A => \wim[5]\, B => \result_0[5]\, S => - wim_1_sqmuxa, Y => \wim_1[5]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_5\ : OR2A - port map(A => irl_0(2), B => \pil[2]\, Y => \ACT_LT4_E[4]\); - - \r.x.ctrl.tt_RNO[3]\ : MX2C - port map(A => N_4201_i_0, B => N_4207, S => N_4210_i_0, Y - => \tt2[3]\); - - \r.e.shcnt_RNIN594N[1]\ : MX2C - port map(A => \shiftin_14[14]\, B => \shiftin_14[12]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[12]\); - - \r.e.ctrl.inst[28]\ : DFN1E0 - port map(D => \inst_1[28]\, CLK => lclk_c, E => holdn, Q - => \inst_2[28]\); - - un6_fe_npc_I_185 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[21]\, Y => N_21); - - un6_ex_add_res_d2_ADD_33x33_fast_I243_Y : OR2 - port map(A => N656, B => I243_un1_Y_1, Y => N796_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I183_Y : AO1 - port map(A => N594_2, B => N587_1, C => N586_0, Y => N652); - - un6_ex_add_res_d1_ADD_33x33_fast_I115_Y : AO1 - port map(A => N516_0, B => N513_1, C => N512_0, Y => N578_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I181_Y : AO1 - port map(A => N592, B => N585, C => N584, Y => N650_0); - - \r.w.result_RNIPJD4[27]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[27]\, - Y => \result_m_0_0[27]\); - - \r.a.rfa2_RNINMCQ2[6]\ : MX2 - port map(A => \un3_de_ren1[105]\, B => \rfa2[6]\, S => - holdn, Y => raddr2(6)); - - \r.e.op2_RNIQKAP_0[6]\ : OR2 - port map(A => \un1_iu0_6[6]\, B => \un1_iu0_5[72]\, Y => - \logicout_3[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_un1_Y : OR3C - port map(A => N643_1, B => N627_0, C => N799_1, Y => - I260_un1_Y_i); - - \r.w.s.tba_RNI2U888[14]\ : NOR2B - port map(A => \aluresult_1_iv_3[26]\, B => \bpdata_m_2[2]\, - Y => \aluresult_1_iv_5[26]\); - - \r.f.pc_RNO[20]\ : OR3C - port map(A => \tmp_m[20]\, B => \pc_1_iv_1[20]\, C => - \un6_fe_npc_m[18]\, Y => \pc_1[20]\); - - \r.e.ctrl.rd_RNI4D3O[7]\ : XNOR2 - port map(A => \rd_1[7]\, B => \un3_de_ren1[98]\, Y => - un2_rs1_1_7_i_0); - - \r.e.shcnt_RNI8H0R7[3]\ : MX2 - port map(A => \shiftin_8[42]\, B => \shiftin_8[34]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[34]\); - - \r.e.shcnt_RNI376H5[3]\ : MX2 - port map(A => \shiftin_8[30]\, B => \shiftin_8[22]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[22]\); - - \comb.op_mux.d_1_iv_RNO_5[29]\ : OR2B - port map(A => data2(29), B => d25, Y => \rfo_m_i[61]\); - - \r.a.ctrl.pc[2]\ : DFN1E0 - port map(D => \dpc[2]\, CLK => lclk_c, E => holdn, Q => - \pc[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I22_P0N : OR3A - port map(A => \data_0[21]\, B => \op1[21]\, C => ldbp1_2, Y - => N461); - - \r.e.aluop_1_RNIRGID1[1]\ : XOR3 - port map(A => \un1_iu0_6[14]\, B => \aluop_1[1]\, C => - \un1_iu0_5[80]\, Y => N_6901); - - \r.e.shcnt_RNIKLLCA[2]\ : MX2C - port map(A => \shiftin_11[12]\, B => \shiftin_11[8]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[8]\); - - \r.e.op2_RNO_7[22]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[374]\, - Y => \cpi_m_i[374]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I248_un1_Y : NOR2B - port map(A => N667_1, B => N616_1, Y => I248_un1_Y); - - \r.a.ctrl.wicc_RNO_2\ : NOR2B - port map(A => \inst_0_0[22]\, B => un7_op_3, Y => N_97); - - \r.x.result_RNIV0Q65[1]\ : OR2B - port map(A => \bpdata[1]\, B => N_3957_1, Y => - \bpdata_m_1[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I267_Y_0 : AOI1 - port map(A => N656, B => N641, C => N640_1, Y => - ADD_33x33_fast_I267_Y_0_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I187_Y : AO1A - port map(A => N591_0, B => N598_1, C => N590_0, Y => N656_0); - - \r.x.result_RNIIFJA[1]\ : MX2 - port map(A => \result_0[1]\, B => \data_0[1]\, S => ld_0, Y - => \un1_p0_6[353]\); - - \r.x.ctrl.pc[25]\ : DFN1E0 - port map(D => \pc_3[25]\, CLK => lclk_c, E => holdn, Q => - \pc_2[25]\); - - \r.a.imm_RNO[10]\ : MX2 - port map(A => \inst_0_RNI0FUM[0]\, B => \inst_0[10]\, S => - call_hold5_0, Y => \un3_de_ren1[128]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I44_Y : NOR2B - port map(A => N473_2, B => N470_0, Y => N503_1); - - \r.e.op2_RNO_3[6]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[6]\, Y - => \aluresult_m_i[6]\); - - \r.e.op2_RNO[21]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[21]\, Y => N_305); - - un6_ex_add_res_d0_ADD_33x33_fast_I127_Y : AO1 - port map(A => N528_0, B => N525_1, C => N524_0, Y => N590_2); - - \r.e.ctrl.pc_RNIADK11[24]\ : OR2B - port map(A => \pc[24]\, B => jmpl_0, Y => \cpi_m[169]\); - - \r.d.inst_0_RNI1GIQ[24]\ : AOI1B - port map(A => ldcheck1_5_i_a6_2_2, B => N_3737_1, C => - N_3736, Y => ldcheck1_2); - - \r.d.inst_0[7]\ : DFN1 - port map(D => \inst_0_RNO[7]\, CLK => lclk_c, Q => - \inst_0[7]\); - - \r.x.ctrl.tt_RNIB2K6[4]\ : NOR2B - port map(A => \tt_0[4]\, B => \tt_0[5]\, Y => tt_2); - - \r.m.y_RNO[6]\ : OR3C - port map(A => \y_iv_1[6]\, B => \y_iv_0[6]\, C => - \logicout_m[6]\, Y => \y_1[6]\); - - \r.e.shcnt_RNI4KQGC[2]\ : MX2C - port map(A => \shiftin_11[24]\, B => \shiftin_11[20]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[20]\); - - \r.e.aluop_RNI36373[1]\ : MX2C - port map(A => N_3537, B => \logicout_3[10]\, S => - \aluop_3[1]\, Y => N_3569); - - un6_ex_add_res_d0_ADD_33x33_fast_I269_Y_0 : AND2 - port map(A => I231_un1_Y_i, B => N644_i, Y => - ADD_33x33_fast_I269_Y_0); - - \r.x.data_0_RNIGJ9E[26]\ : XOR2 - port map(A => \data_0[26]\, B => invop2_1, Y => N_4273); - - \comb.branch_address.tmp_ADD_30x30_fast_I7_P0N\ : OR2 - port map(A => \inst_0[7]\, B => \dpc[9]\, Y => N380); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_Y_0 : OA1C - port map(A => N500, B => N497_0, C => N496_0, Y => - ADD_33x33_fast_I261_Y_0); - - \r.m.y_RNO_3[26]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y[26]\, C => \y_m[26]\, Y - => \y_iv_1[26]\); - - \r.e.op1_RNIDN5RB[23]\ : NOR2 - port map(A => \edata2_0_iv_1[23]\, B => \bpdata_i_m_1[7]\, - Y => edata2_0_iv(23)); - - \r.a.imm_RNO[26]\ : MX2 - port map(A => \inst_0[16]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[144]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I124_Y : NOR2B - port map(A => N525_1, B => N521, Y => N587_0); - - \r.e.op2_RNO_4[15]\ : OA1A - port map(A => \maddress[15]\, B => d27_0, C => - \cpi_m_i[367]\, Y => \d_1_iv_1[15]\); - - \r.x.result_RNITDG25[9]\ : OR2B - port map(A => \bpdata[9]\, B => N_3974, Y => \bpdata_m[9]\); - - \r.e.shleft_1_RNINGHP\ : NOR2A - port map(A => \un1_iu0_6[12]\, B => shleft_1, Y => - shleft_1_RNINGHP); - - \r.e.op2_RNO_5[9]\ : OR2B - port map(A => \result[9]\, B => d31, Y => \result_m_i[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I236_Y_0\ : AO1 - port map(A => N522, B => N515, C => N514, Y => - ADD_30x30_fast_I236_Y_0); - - \r.a.ctrl.inst_RNI8O0E[20]\ : NOR2 - port map(A => \inst_2[20]\, B => \inst_1[24]\, Y => - inst_32_1); - - un6_fe_npc_I_152 : AND3 - port map(A => \DWACT_FINC_E[34]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I27_P0N : OR2 - port map(A => \un1_iu0_6[26]\, B => \op2[26]\, Y => N476); - - \r.m.y_RNO_0[18]\ : NOR3C - port map(A => N_397, B => N_394, C => \y_iv_0_1[18]\, Y => - \y_iv_0_2[18]\); - - \r.d.inst_0[2]\ : DFN1 - port map(D => \inst_0_RNO[2]\, CLK => lclk_c, Q => - \inst_0[2]\); - - \r.e.aluop_0_RNI8N4Q5[0]\ : MX2C - port map(A => N_3585, B => N_3649, S => \aluop_0[0]\, Y => - \logicout[26]\); - - \r.e.shleft_RNI35931\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[7]\, S => shleft, - Y => \shiftin_5[38]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I15_P0N : AO1A - port map(A => ldbp1_1, B => \op1[14]\, C => \data_0[14]\, Y - => N440_1); - - \r.x.rstate_RNO_1[1]\ : OR2A - port map(A => rstate_6314_d_0, B => error_1_sqmuxa, Y => - \rstate_ns[1]\); - - \r.w.s.s_RNI8MPP\ : OR2B - port map(A => s_3_sqmuxa_0, B => s, Y => s_m); - - \r.e.ctrl.pc[25]\ : DFN1E0 - port map(D => \pc_0[25]\, CLK => lclk_c, E => holdn, Q => - \pc[25]\); - - \r.e.op2_RNI4THG[3]\ : MX2 - port map(A => \op2[3]\, B => N_3307, S => ldbp2_1, Y => - \un1_iu0_5[69]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I30_G0N : NOR2B - port map(A => \un1_iu0_6[29]\, B => \op2[29]\, Y => N484_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I263_Y_1 : NOR3B - port map(A => I163_un1_Y_i, B => I219_un1_Y_i, C => N566_0, - Y => ADD_33x33_fast_I263_Y_1_1); - - \r.e.op1_RNIC8KS4[17]\ : OR2 - port map(A => \bpdata_i_m[17]\, B => \op1_i_m[17]\, Y => - \edata2_0_iv_0[17]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I247_un1_Y : NOR2B - port map(A => N665_1, B => N614_2, Y => I247_un1_Y); - - \r.x.mexc_RNO\ : NOR2B - port map(A => rst, B => N_5246, Y => mexc_RNO); - - \r.m.y_RNI16HP2[24]\ : AOI1B - port map(A => \y[24]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[24]\, Y => \aluresult_1_iv_0[24]\); - - \r.e.op1_RNI6NN8[1]\ : MX2 - port map(A => \op1[1]\, B => \data_0[1]\, S => ldbp1_1, Y - => \un1_iu0_6[1]\); - - \r.d.inst_0[19]\ : DFN1 - port map(D => \inst_0_RNO[19]\, CLK => lclk_c, Q => - \inst_0[19]\); - - \r.e.op1_RNO[5]\ : MX2C - port map(A => \d_i_0[5]\, B => \d_i[6]\, S => N_227_0, Y - => \aop1[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I244_un1_Y : NOR3C - port map(A => N593_0, B => N601, C => N674_0, Y => - ADD_33x33_fast_I244_un1_Y); - - \r.e.shcnt_RNIBUE9R[1]\ : MX2C - port map(A => \shiftin_14[24]\, B => \shiftin_14[22]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[22]\); - - \r.x.mexc_RNIEOPT\ : NOR2A - port map(A => N_3321, B => mexc_0, Y => \xc_vectt_1[2]\); - - \r.a.ctrl.inst_RNI914O1[25]\ : OR3A - port map(A => \cpi_m_1[133]\, B => N_212, C => N_205, Y => - \cpi_m_i[133]\); - - \r.x.data_0_RNO_0[30]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_30, Y => - \dco_m_1[126]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I196_Y : NOR3C - port map(A => N541, B => N545_0, C => N599_2, Y => N665_1); - - \r.x.data_0[28]\ : DFN1E0 - port map(D => \data_0_1[28]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[28]\); - - \comb.lock_gen.ldchkra_RNIR29CO\ : AO1B - port map(A => ldlock2_1, B => un1_ldcheck1_1, C => - ldlock_2_0, Y => \ldlock_2\); - - un6_ex_add_res_d1_ADD_33x33_fast_I8_P0N : OR2 - port map(A => \un1_iu0_6[7]\, B => \op2[7]\, Y => N419_1); - - \r.f.pc_RNO[25]\ : OR3C - port map(A => \tmp_m[25]\, B => \pc_1_iv_1[25]\, C => - \un6_fe_npc_m[23]\, Y => \pc_1[25]\); - - \r.a.imm[26]\ : DFN1E0 - port map(D => \un3_de_ren1[144]\, CLK => lclk_c, E => holdn, - Q => \imm[26]\); - - \r.w.s.y[3]\ : DFN1E0 - port map(D => N_3767, CLK => lclk_c, E => N_6922_i, Q => - \y[3]\); - - \r.e.op2_RNO_0[24]\ : OR3C - port map(A => \op1_m_i[24]\, B => \d_1_iv_3[24]\, C => - \aluresult_m_i[24]\, Y => \d_1[24]\); - - \r.w.s.tba_RNIQD7A1[18]\ : OR2B - port map(A => \tba[18]\, B => aluresult_12_sqmuxa, Y => - \tba_m[18]\); - - \r.f.pc_RNIN8A81[7]\ : MX2 - port map(A => \fpc[7]\, B => \xc_vectt_1[3]\, S => - rstate_6314_d, Y => \xc_trap_address[7]\); - - \r.w.result[30]\ : DFN1E0 - port map(D => \wdata[30]\, CLK => lclk_c, E => holdn, Q => - \result[30]\); - - \r.x.data_0_RNIJN43[9]\ : XOR2 - port map(A => \data_0[9]\, B => invop2, Y => N_4256); - - \r.m.casa_RNIKPD91\ : NOR2 - port map(A => un1_logicout21, B => un17_casaen_0, Y => - edata_3_sqmuxa); - - \r.e.ctrl.wicc_RNIDRHTF5\ : MX2C - port map(A => N_4185, B => N_4175, S => wicc_2, Y => - \icco[0]\); - - \r.m.ctrl.inst_RNIUG0E[20]\ : OR2A - port map(A => \inst_3[20]\, B => \inst_2[22]\, Y => - trap_0_sqmuxa_3_2); - - \r.e.aluop_0_RNIHLB5Q[0]\ : NOR3C - port map(A => \aluresult_1_iv_5[25]\, B => - \aluresult_1_iv_4[25]\, C => \logicout_m_0[25]\, Y => - \aluresult_1_iv_7[25]\); - - \dci.enaddr_1_sqmuxa_1_RNO\ : NOR2A - port map(A => enaddr_1_sqmuxa_1_0, B => \cnt[1]\, Y => - enaddr_1_sqmuxa_1_1); - - \r.x.npc_0_RNI7LHG1[0]\ : MX2 - port map(A => \npc_0[0]\, B => \npc_cnst_m_0[0]\, S => - s_3_sqmuxa_0, Y => \npc_1[0]\); - - \r.w.result_RNILFD4[16]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[16]\, - Y => \result_m_0_0[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I2_P0N\ : OR2 - port map(A => \inst_0_RNI2NUM[2]\, B => \dpc[4]\, Y => N365); - - un6_ex_add_res_d1_ADD_33x33_fast_I203_un1_Y : NOR2B - port map(A => N614_0, B => N607_0, Y => I203_un1_Y); - - \r.e.invop2_RNINRBQE\ : MX2 - port map(A => \un6_ex_add_res_s2[10]\, B => - \un6_ex_add_res_s0[10]\, S => invop2, Y => N_6629); - - \r.e.ctrl.wy\ : DFN1E0 - port map(D => wy, CLK => lclk_c, E => holdn, Q => wy_3); - - un6_ex_add_res_d1_ADD_33x33_fast_I184_Y : NOR3B - port map(A => N521_1, B => N525, C => N595_2, Y => N653); - - \r.f.pc[5]\ : DFN1E0 - port map(D => \pc_1[5]\, CLK => lclk_c, E => holdn, Q => - \fpc[5]\); - - \r.d.pv_RNITOEF91\ : NOR2A - port map(A => annul_next_2_sqmuxa_1_5, B => ldlock, Y => - annul_next_2_sqmuxa_1_6); - - un6_ex_add_res_d1_ADD_33x33_fast_I6_P0N : OR2 - port map(A => \un1_iu0_6[5]\, B => \op2[5]\, Y => N413_1); - - \r.e.op2_RNO_4[26]\ : OA1A - port map(A => \maddress[26]\, B => d27_0, C => - \cpi_m_i[378]\, Y => \d_1_iv_1[26]\); - - \r.e.ctrl.rd[4]\ : DFN1E0 - port map(D => \rd_1[4]\, CLK => lclk_c, E => holdn, Q => - \rd_0[4]\); - - \r.e.aluop_RNIC8EB4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[30]\, Y => - \aluop_RNIC8EB4[1]\); - - un2_rstn_5_0_0_RNI05FAD3 : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[5]\, C => - \tmp_m[5]\, Y => \npc_iv_0[5]\); - - \r.x.y[27]\ : DFN1E0 - port map(D => \y_0[27]\, CLK => lclk_c, E => holdn, Q => - \y_2[27]\); - - \r.x.result[23]\ : DFN1E0 - port map(D => \maddress[23]\, CLK => lclk_c, E => holdn, Q - => \result[23]\); - - \r.d.inst_0_RNI5C23_3[31]\ : OR2 - port map(A => \inst_0[31]\, B => \inst_0[30]\, Y => - call_hold5_0); - - \r.e.shcnt_RNO[3]\ : XOR2 - port map(A => \d_1[3]\, B => N_208, Y => N_269_i_i_0); - - \r.e.op2_RNO_9[8]\ : OR2B - port map(A => \result_0[8]\, B => d31, Y => \result_m_i[8]\); - - \r.m.y_RNIC4K91[6]\ : OR2B - port map(A => \y_0[6]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[6]\); - - \r.d.pv_RNO_6\ : MX2 - port map(A => un4_op3, B => un13_op3, S => \cnt_2[0]\, Y - => pv_RNO_6); - - \r.x.result_RNIPC6E[16]\ : MX2 - port map(A => \result_0[16]\, B => \data_0[16]\, S => ld_4, - Y => \un1_p0_6[368]\); - - \r.e.op2_RNO_0[8]\ : OR3C - port map(A => \op1_m_i[8]\, B => \d_1_iv_3[8]\, C => - \aluresult_m_i[8]\, Y => \d_1[8]\); - - \r.d.inst_0[30]\ : DFN1 - port map(D => \inst_0_RNO[30]\, CLK => lclk_c, Q => - \inst_0[30]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I164_Y : NOR2A - port map(A => N575_1, B => N567_2, Y => N633_1); - - \r.a.nobp_RNO_0\ : OR2A - port map(A => N_16827_tz, B => ctrl_annul_i, Y => - nobp_RNO_0); - - \r.e.op2_RNO[28]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[28]\, Y => N_312); - - un6_ex_add_res_d2_ADD_33x33_fast_I104_Y : NOR3C - port map(A => N473_2, B => N476_2, C => N505_0, Y => N567_0); - - \r.f.pc_RNI8P4IL3[8]\ : MX2 - port map(A => I_31, B => N_4051, S => bpmiss_1_i_0_0, Y => - \pc_4[8]\); - - \r.w.s.wim_RNIIN4N2[6]\ : MX2 - port map(A => \wim[6]\, B => \result_0[6]\, S => - wim_1_sqmuxa, Y => \wim_1[6]\); - - \r.m.result_RNIQVO1[10]\ : OR2B - port map(A => d13, B => \maddress[10]\, Y => - \result_m_0[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I284_Y_0_0\ : XOR2 - port map(A => \dpc[26]\, B => \inst_0_1[26]\, Y => - ADD_30x30_fast_I284_Y_0_0); - - \r.d.pc_RNIO5HB4[21]\ : MX2 - port map(A => \dpc[21]\, B => \fpc[21]\, S => - \ra_bpmiss_1_0\, Y => N_3898); - - \r.f.pc_RNIBOM4[9]\ : OR2A - port map(A => \fpc[9]\, B => rst, Y => \pc_m[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I309_Y_0 : XOR3 - port map(A => \data_0_0[18]\, B => \un1_iu0_6[18]\, C => - N790_1, Y => \un6_ex_add_res_s2[19]\); - - \r.a.ctrl.cnt_RNI0BU9_0[0]\ : NOR3B - port map(A => \cnt_2[1]\, B => casa, C => \cnt_1[0]\, Y => - N_219); - - \r.m.ctrl.wy\ : DFN1E0 - port map(D => wy_3, CLK => lclk_c, E => holdn, Q => wy_1); - - \r.m.y_RNO_2[5]\ : OR2B - port map(A => \y_2[5]\, B => y08, Y => \y_m_0[5]\); - - \r.d.inst_0_RNO_0[13]\ : MX2 - port map(A => data_0_0_13, B => \inst_0[13]\, S => - mexc_1_sqmuxa_1_0, Y => N_4613); - - \r.x.ctrl.pc_RNIID971[11]\ : MX2C - port map(A => \un1_p0_6[363]\, B => \pc_0[11]\, S => - s_3_sqmuxa, Y => N_3402); - - \r.e.ctrl.inst_RNI0L256[21]\ : OA1B - port map(A => N_3356_3, B => force_a2_1, C => - ldbp2_1_RNIL7Q55, Y => \eaddress[2]\); - - \r.w.s.y_RNO_1[1]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y_0[1]\, Y => N_398); - - \comb.v.x.data_0_1_1_iv_RNO_1[19]\ : AOI1B - port map(A => rdatav_0_1_0_iv_5_1, B => mcdo_m_0_17, C => - rdata_6_sqmuxa, Y => \dco_m_0[115]\); - - \r.e.aluop_0_RNIKBTV81[0]\ : NOR3C - port map(A => \aluresult_1_iv_6[9]\, B => \logicout_m_0[9]\, - C => \shiftin_17_m[10]\, Y => \aluresult_1_iv_8[9]\); - - \r.w.s.y[18]\ : DFN1E0 - port map(D => N_158, CLK => lclk_c, E => holdn, Q => - \y[18]\); - - \r.m.ctrl.pc[6]\ : DFN1E0 - port map(D => \pc[6]\, CLK => lclk_c, E => holdn, Q => - \pc_2[6]\); - - \r.d.inst_0_RNO_0[15]\ : MX2 - port map(A => data_0_15, B => \inst_0[15]\, S => - mexc_1_sqmuxa_1_0, Y => N_4615); - - \r.f.pc_RNO_6[12]\ : MX2 - port map(A => \fpc[12]\, B => \eaddress[12]\, S => jump, Y - => N_4055); - - \r.e.et_RNIGDGSJ\ : AOI1B - port map(A => \bpdata[5]\, B => N_3957, C => - \aluresult_1_iv_6[5]\, Y => \aluresult_1_iv_7[5]\); - - \r.d.inst_0_RNIF423[29]\ : OR2 - port map(A => \inst_0[29]\, B => \inst_0[28]\, Y => - N_3525_3); - - \r.w.s.tt[0]\ : DFN1 - port map(D => \tt_RNO[0]\, CLK => lclk_c, Q => \irl[0]\); - - \r.a.ctrl.pc_RNIM0M0C[7]\ : MX2 - port map(A => \pc_3[7]\, B => N_3884, S => ex_bpmiss_1, Y - => \fe_pc[7]\); - - \r.w.s.tt_RNO[0]\ : MX2A - port map(A => \xc_vectt_1[0]\, B => \irl[0]\, S => N_6747, - Y => \tt_RNO[0]\); - - \r.a.ctrl.wicc_RNO_0\ : NOR3A - port map(A => \inst_0_0[23]\, B => \inst_0_0[24]\, C => - N_97, Y => wicc_1_0_a3_0_0); - - \r.a.ctrl.inst_RNID81L[23]\ : NOR3B - port map(A => \inst_2[20]\, B => \inst_1[23]\, C => - \inst_1[24]\, Y => inst_21_1); - - \r.e.jmpl_RNIIF42P1\ : OR2B - port map(A => \aluresult_2_iv_7[0]\, B => \shiftin_17_m[1]\, - Y => \aluresult[0]\); - - \r.a.ctrl.inst_RNICC292[30]\ : NOR3C - port map(A => N_454, B => \inst_RNIJ02L[19]\, C => - \aop2_i_o2_0[0]\, Y => \aop2_i_o2_2[0]\); - - \r.e.op2_RNIR1VL1[9]\ : AOI1B - port map(A => \un1_iu0_5[75]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[9]\); - - \r.e.op2_RNO_6[24]\ : OR2B - port map(A => data2(24), B => d25, Y => \rfo_m_i[56]\); - - \r.x.y[18]\ : DFN1E0 - port map(D => \y_1[18]\, CLK => lclk_c, E => holdn, Q => - \y_2[18]\); - - \r.e.ctrl.pc_RNIETK11[28]\ : OR2B - port map(A => \pc_2[28]\, B => jmpl_4, Y => \cpi_m[173]\); - - \r.m.y_RNO[19]\ : OR3C - port map(A => \y_iv_1[19]\, B => \y_iv_0[19]\, C => - \logicout_m[19]\, Y => \y_1[19]\); - - \r.a.ctrl.pc_RNI3KE2C[24]\ : MX2 - port map(A => \pc_3[24]\, B => N_3901, S => ex_bpmiss_1, Y - => \fe_pc[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I285_Y_0\ : XNOR2 - port map(A => N702_i, B => ADD_30x30_fast_I285_Y_0_0, Y => - \tmp[27]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I303_Y_0 : AX1 - port map(A => ADD_33x33_fast_I246_Y_0_a3_1, B => N430_1, C - => \un6_ex_add_res_s0_1[13]\, Y => - \un6_ex_add_res_s2[13]\); - - \r.e.ctrl.rd_RNIU8FK1[1]\ : XA1A - port map(A => \rd[1]\, B => \inst_0_RNI1JUM[1]\, C => - un1_de_ren1_2_0_i_0, Y => wreg_1_1); - - \r.a.rsel1_0_RNIE3LJ2[2]\ : OR2B - port map(A => data1(17), B => d11_0, Y => \rfo_m[17]\); - - \r.e.shcnt_RNI970Q5[3]\ : MX2 - port map(A => \shiftin_8[27]\, B => \shiftin_8[19]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[19]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I316_Y_0 : XNOR2 - port map(A => N776_0, B => \un6_ex_add_res_s2_1[26]\, Y => - \un6_ex_add_res_s0[26]\); - - \r.x.ctrl.wy_RNILF1N3_0\ : NOR2 - port map(A => y_1_sqmuxa_1, B => y_1_sqmuxa_0, Y => N_481); - - \r.e.op2_RNIS6VD4[7]\ : AOI1B - port map(A => \un1_iu0_5[73]\, B => aluresult_7_sqmuxa_0_0, - C => \aluresult_1_iv_0[7]\, Y => \aluresult_1_iv_1[7]\); - - \r.e.aluop_0_RNIRHPC4[0]\ : NOR3 - port map(A => \logicout_5_0_i_0[24]\, B => N_448, C => - N_447, Y => N_198); - - \r.a.imm_RNI2645[1]\ : OR3B - port map(A => d29_0_0, B => \imm[1]\, C => \rsel2_0[0]\, Y - => \imm_m_i[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I31_P0N : OR2A - port map(A => \data_0[30]\, B => \un1_iu0_6[30]\, Y => - N488_2); - - \r.w.s.tba_RNIKL6A1[12]\ : OR2B - port map(A => \tba[12]\, B => aluresult_12_sqmuxa_0_0, Y - => \tba_m[12]\); - - \r.x.ctrl.inst_RNI0TN43[27]\ : OR3A - port map(A => y_0_sqmuxa_3, B => y_0_sqmuxa_1, C => - \rstate_d[2]\, Y => y_1_sqmuxa_1); - - \r.d.cnt_RNI9TF3[0]\ : OR2B - port map(A => \cnt_2[0]\, B => \inst_0[30]\, Y => N_3739); - - un6_ex_add_res_d2_ADD_33x33_fast_I151_un1_Y : NOR2B - port map(A => N552_1, B => N549, Y => I151_un1_Y); - - aluresult_11_sqmuxa_5_RNIQJG41 : NOR3C - port map(A => aluresult_12_sqmuxa_0, B => - aluresult_12_sqmuxa_4, C => aluresult_12_sqmuxa_5, Y => - aluresult_12_sqmuxa); - - un6_fe_npc_I_182 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[30]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I10_P0N : AO1A - port map(A => ldbp1, B => \op1[9]\, C => \data_0[9]\, Y => - N425_2); - - \r.d.inst_0[13]\ : DFN1 - port map(D => \inst_0_RNO[13]\, CLK => lclk_c, Q => - \inst_0[13]\); - - \r.e.op2[0]\ : DFN1E0 - port map(D => N_284, CLK => lclk_c, E => holdn, Q => - \op2[0]\); - - \r.f.branch_RNIJ4KLC\ : NOR3B - port map(A => d_m5_0_a3_0, B => ex_bpmiss_1_0, C => - \xc_exception_1_0\, Y => d_m5_0_a3_2); - - \r.e.ldbp2_2_RNITAJ763\ : OR2A - port map(A => \eaddress[20]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[21]\); - - \r.e.op2_RNO_2[19]\ : NOR3C - port map(A => \d_1_iv_1[19]\, B => \d_1_iv_0[19]\, C => - \rfo_m_i[51]\, Y => \d_1_iv_3[19]\); - - \r.e.op2_RNO[11]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[11]\, Y => N_295); - - \r.m.y_RNO_2[21]\ : OR2B - port map(A => wy_RNIMKUI, B => \y_2[21]\, Y => \y_m_0[21]\); - - \r.e.cwp_RNIFTJ61[0]\ : OR2A - port map(A => \cwp_1[0]\, B => aluresult_11_sqmuxa, Y => - \cwp_m[0]\); - - \r.x.ctrl.pc_RNINIIF[19]\ : MX2 - port map(A => \pc_0[19]\, B => \pc[19]\, S => \npc_1[1]\, Y - => N_3230); - - \r.d.cwp_RNO_1[0]\ : MX2 - port map(A => \cwp_0[0]\, B => \maddress[0]\, S => wcwp, Y - => N_4218); - - \r.a.rsel2_0_RNILPBM2[0]\ : OR2B - port map(A => data2(0), B => d25, Y => \rfo_m_i[32]\); - - \r.e.op1_RNIFQ3U1[3]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[3]\, C => - \ex_op1_i_m[3]\, Y => \edata2_0_iv_0[3]\); - - \r.e.ldbp2_2_RNIV858N3\ : MX2C - port map(A => \un6_ex_add_res_s1_i[23]\, B => N_6569, S => - ldbp2_2, Y => \eaddress[22]\); - - \r.m.y_RNO_1[18]\ : OR2B - port map(A => \y_0[19]\, B => mulstep_1, Y => N_397); - - un6_ex_add_res_d0_ADD_33x33_fast_I38_Y : OR2B - port map(A => N482_1, B => N479_1, Y => N497_0); - - \r.x.result[7]\ : DFN1E0 - port map(D => \maddress[7]\, CLK => lclk_c, E => holdn, Q - => \result_0[7]\); - - \r.x.ctrl.pc_RNIG7AE[7]\ : MX2 - port map(A => \pc[7]\, B => \pc_0[7]\, S => \npc_0[1]\, Y - => N_3218); - - \r.e.ctrl.inst_RNIB1LO[27]\ : AO1B - port map(A => \inst_1[27]\, B => \icc_0[0]\, C => N_6695_i, - Y => N_328); - - \r.e.shcnt_RNIAUGF6[3]\ : MX2 - port map(A => \shiftin_8[37]\, B => \shiftin_8[29]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[29]\); - - \r.e.ctrl.cnt_RNILO7A_0[0]\ : NOR3A - port map(A => \cnt[0]\, B => \cnt[1]\, C => annul, Y => - enaddr_2_sqmuxa_0); - - \r.e.op2_RNO_2[28]\ : NOR3C - port map(A => \d_1_iv_1[28]\, B => \d_1_iv_0[28]\, C => - \rfo_m_i[60]\, Y => \d_1_iv_3[28]\); - - \r.d.inst_0[14]\ : DFN1 - port map(D => \inst_0_RNO[14]\, CLK => lclk_c, Q => - \inst_0[14]\); - - \r.a.imm[10]\ : DFN1E0 - port map(D => \un3_de_ren1[128]\, CLK => lclk_c, E => holdn, - Q => \imm[10]\); - - \r.a.bp_RNIHG6I\ : NOR3A - port map(A => bp, B => annul_2, C => not_valid, Y => - ra_bpmiss_1_1); - - \r.e.op2_RNIJQNP[10]\ : MX2 - port map(A => \op2[10]\, B => N_4257, S => ldbp2_0, Y => - \un1_iu0_5[76]\); - - un6_fe_npc_I_142 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[16]\, Y => N_51); - - \r.a.ctrl.inst_RNII02L[24]\ : OR2A - port map(A => N_487, B => \inst_1[24]\, Y => - illegal_inst_7_iv_2_0_a5_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I91_Y\ : NOR2B - port map(A => N456, B => N452, Y => N511); - - un6_ex_add_res_d1_ADD_33x33_fast_I314_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[23]\, B => \op2[23]\, Y => - ADD_33x33_fast_I314_Y_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I100_Y : NOR3B - port map(A => N473_1, B => N476_1, C => N497_0, Y => N563); - - \r.x.data_0_RNO_1[14]\ : AO1A - port map(A => rdata_5_sqmuxa, B => data_0_0_30, C => - \data_0_m[14]\, Y => \data_0_1_0_iv_0[14]\); - - \r.m.result_RNIBJD4[23]\ : OR2B - port map(A => d13_0, B => \maddress[23]\, Y => - \result_m_0[23]\); - - \r.e.shleft_1_RNI6PHM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[21]\, S => - shleft_1, Y => \shiftin_5[52]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I261_Y_2 : NOR3C - port map(A => I159_un1_Y_0, B => ADD_33x33_fast_I261_Y_0, C - => I215_un1_Y, Y => ADD_33x33_fast_I261_Y_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I271_Y_0 : AOI1 - port map(A => N664, B => N649, C => N648_0, Y => - ADD_33x33_fast_I271_Y_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I22_P0N\ : OR2 - port map(A => \inst_0_0_0_RNI9O79[21]\, B => \dpc[24]\, Y - => N425); - - \r.e.shcnt_RNI8LCF4[3]\ : MX2 - port map(A => \shiftin_8[16]\, B => \shiftin_8[8]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I315_Y_0 : XOR2 - port map(A => N778, B => \un6_ex_add_res_s2_1[25]\, Y => - \un6_ex_add_res_s2[25]\); - - \r.d.cnt_RNO[1]\ : MX2B - port map(A => \cnt_0[1]\, B => cnt_3_sqmuxa, S => N_6825_i, - Y => \cnt_RNO[1]\); - - \r.x.data_0_RNO_2[1]\ : OR2A - port map(A => data_0_0_25, B => rdata_0_sqmuxa, Y => - \dco_m_i[121]\); - - \r.m.result_RNO[30]\ : MX2 - port map(A => \aluresult[30]\, B => \op1[30]\, S => - un17_casaen_0_1, Y => \eres2[30]\); - - \r.d.inst_0_RNI5C23_2[31]\ : OR2 - port map(A => \inst_0[31]\, B => \inst_0[30]\, Y => - call_hold5); - - \r.e.aluop_0_RNII3966[0]\ : OR2B - port map(A => \logicout[25]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[25]\); - - \r.e.aluop_0_RNIBM4Q5[0]\ : MX2C - port map(A => N_3576, B => N_3640, S => \aluop_0[0]\, Y => - \logicout[17]\); - - \r.x.data_0_RNO_1[13]\ : OR2 - port map(A => \dco_m_0[125]\, B => \data_0_m[13]\, Y => - \data_0_1_0_iv_0[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I248_Y : AO1 - port map(A => N667_0, B => N616_0, C => N666_1, Y => N811_1); - - \r.e.op1_RNIMOKS4[19]\ : AO1A - port map(A => \bpdata[19]\, B => edata_2_sqmuxa, C => - \op1_i_m[19]\, Y => \edata2_0_iv_0[19]\); - - \r.d.pc_RNIU5HB4[24]\ : MX2 - port map(A => \dpc[24]\, B => \fpc[24]\, S => ra_bpmiss_1, - Y => N_3901); - - \r.e.invop2_RNICR63K\ : MX2C - port map(A => \un6_ex_add_res_s2[12]\, B => - \un6_ex_add_res_s0[12]\, S => invop2, Y => N_6631); - - \r.m.result_RNO[28]\ : MX2 - port map(A => \aluresult[28]\, B => \op1[28]\, S => - un17_casaen_0_2, Y => \eres2[28]\); - - \r.x.rstate_RNI4GF12[0]\ : MX2C - port map(A => N_3416, B => \xc_result[25]\, S => - \rstate[0]\, Y => \wdata[25]\); - - \r.e.op1[21]\ : DFN1E0 - port map(D => \aop1[21]\, CLK => lclk_c, E => holdn, Q => - \op1[21]\); - - \r.f.branch_RNIA8KSK\ : NOR3C - port map(A => branch_RNIMJA92, B => branch_1_m7_3, C => - \ra_bpmiss_1_0\, Y => branch_RNIA8KSK); - - \r.e.op1[17]\ : DFN1E0 - port map(D => \aop1[17]\, CLK => lclk_c, E => holdn, Q => - \op1[17]\); - - \r.e.aluop_0_RNIL56R[2]\ : XA1 - port map(A => \un1_iu0_5[71]\, B => \aluop_0[2]\, C => - \un1_iu0_6[5]\, Y => N_3532); - - \r.f.pc_RNO_0[28]\ : NAND2 - port map(A => \tmp[28]\, B => un2_rstn_5_0, Y => - \tmp_m[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I182_Y : NOR2B - port map(A => N593_1, B => N585_1, Y => N651); - - \r.e.op2_RNO_1[20]\ : OR2B - port map(A => \op1[20]\, B => un14_casaen_s1, Y => - \op1_m_i[20]\); - - \r.a.ctrl.pc[3]\ : DFN1E0 - port map(D => \dpc[3]\, CLK => lclk_c, E => holdn, Q => - \pc[3]\); - - \r.f.pc_RNI8ILOU1[2]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[2]\, Y => - \pc_4_m[2]\); - - \r.e.op2_RNO_0[21]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[21]\, C - => \d_1_iv_4[21]\, Y => \d_1[21]\); - - \r.a.nobp\ : DFN1E0 - port map(D => nobp_1, CLK => lclk_c, E => holdn, Q => nobp); - - \r.e.shleft_RNIBIEC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[10]\, S => - shleft, Y => \shiftin_5[41]\); - - \r.e.op2_RNO_2[16]\ : NOR3C - port map(A => \d_1_iv_1[16]\, B => \d_1_iv_0[16]\, C => - \rfo_m_i[48]\, Y => \d_1_iv_3[16]\); - - \r.x.ctrl.pc[14]\ : DFN1E0 - port map(D => \pc_2[14]\, CLK => lclk_c, E => holdn, Q => - \pc_0[14]\); - - \r.x.ctrl.pc_RNIE7AE[6]\ : MX2 - port map(A => \pc_1[6]\, B => \pc[6]\, S => \npc_0[1]\, Y - => N_3217); - - \r.e.ctrl.inst_RNIQT1J7_0[26]\ : NOR2 - port map(A => ex_bpmiss_1_0_1, B => ex_bpmiss_1_0_2, Y => - ex_bpmiss_1); - - \r.x.npc_0_RNIJTT61[0]\ : MX2C - port map(A => N_3237, B => N_3267, S => \npc_0[0]\, Y => - \xc_result[26]\); - - \r.x.result[5]\ : DFN1E0 - port map(D => \maddress[5]\, CLK => lclk_c, E => holdn, Q - => \result_0[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I12_P0N : AO1A - port map(A => ldbp1, B => \op1[11]\, C => \data_0_2[11]\, Y - => N431_2); - - \r.e.ldbp2_RNITPCCO6\ : OR2B - port map(A => \aluresult_1_iv_9[25]\, B => - \un6_ex_add_res_m[26]\, Y => \aluresult[25]\); - - \r.e.aluop_RNI2QON[1]\ : NOR3B - port map(A => logicout19_0, B => \aluop_3[1]\, C => - aluresult_9_sqmuxa_1, Y => aluresult_4_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I9_G0N : NOR2B - port map(A => \un1_iu0_6[8]\, B => \op2[8]\, Y => N421_0); - - \r.a.rsel1_RNI1RFA_1[0]\ : NOR2A - port map(A => N_494, B => un17_casaen_0, Y => - un14_casaen_s0_0); - - \r.e.op1_RNICTUH[27]\ : MX2 - port map(A => \op1[27]\, B => \data_0[27]\, S => ldbp1_1, Y - => \un1_iu0_6[27]\); - - \comb.fpstdata.edata2_0_iv_RNO_2[2]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[2]\, Y => - \op1_i_m[2]\); - - \r.e.op2_RNO_9[26]\ : OR2B - port map(A => \result_0[26]\, B => d31, Y => - \result_m_i[26]\); - - \r.e.op2_RNO[18]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[18]\, Y => N_302); - - \r.e.op2_RNINDD6[9]\ : MX2 - port map(A => \op2[9]\, B => N_4256, S => ldbp2_3, Y => - \un1_iu0_5[75]\); - - \r.e.ctrl.pc_RNI7TJ11[30]\ : OR2B - port map(A => \pc_0[30]\, B => jmpl_4, Y => \cpi_m[175]\); - - \r.a.ctrl.pc[8]\ : DFN1E0 - port map(D => \dpc[8]\, CLK => lclk_c, E => holdn, Q => - \pc[8]\); - - \r.e.jmpl_RNI2VIHF1\ : AOI1B - port map(A => \shiftin_17[11]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[10]\, Y => \aluresult_1_iv_8[10]\); - - \r.e.aluop_0_RNI3K8O1[1]\ : MX2C - port map(A => \logicout_4[6]\, B => N_6838, S => N_6866_i_0, - Y => N_3629); - - \comb.branch_address.tmp_ADD_30x30_fast_I108_un1_Y\ : OR3C - port map(A => N407_0, B => N410, C => N473_0, Y => - I108_un1_Y); - - \r.f.pc_RNO_3[23]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[23]\, C => - \xc_trap_address_m[23]\, Y => \pc_1_iv_0[23]\); - - \r.f.pc_RNO_2[24]\ : OR2B - port map(A => I_143, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[22]\); - - \r.e.op2_RNO_8[27]\ : OR3B - port map(A => d29_0, B => \imm[27]\, C => \rsel2[0]\, Y => - \imm_m_i[27]\); - - \r.d.inst_0_0_0_RNIQ98I03[21]\ : NOR2B - port map(A => rst, B => N_4621, Y => - \inst_0_0_0_RNIQ98I03[21]\); - - \r.x.data_0_RNO_1[30]\ : NOR2A - port map(A => \data_0[30]\, B => ld_3, Y => \data_0_m[30]\); - - \r.a.ctrl.inst_RNI5H3O1_1[19]\ : NOR3 - port map(A => N_203, B => N_204, C => N_205, Y => N_208); - - un6_ex_add_res_d2_ADD_33x33_fast_I26_P0N : AO1A - port map(A => ldbp1_3, B => \op1[25]\, C => \data_0[25]\, Y - => N473_2); - - \r.e.aluop_RNI5NNF_0[1]\ : OR2A - port map(A => \aluop_1[0]\, B => \aluop_3[1]\, Y => - logicout21_1); - - \r.x.result_RNI4ATN5[0]\ : OR2A - port map(A => N_3687, B => \bpdata[0]\, Y => - \bpdata_i_m[0]\); - - \r.e.ctrl.cnt_RNILO7A[0]\ : OR3A - port map(A => \cnt[0]\, B => \cnt[1]\, C => annul, Y => - force_a2_0); - - \r.x.data_0_RNIJFO8[7]\ : MX2 - port map(A => \op1[7]\, B => \data_0_2[7]\, S => ldbp1_2, Y - => \un1_iu0_6[7]\); - - \r.a.ctrl.pc_RNIN3E2C[20]\ : MX2 - port map(A => \pc[20]\, B => N_3897, S => ex_bpmiss_1_0, Y - => \fe_pc[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I1_P0N\ : OR2 - port map(A => \inst_0_RNI1JUM[1]\, B => \dpc[3]\, Y => N362); - - \r.m.casa_RNI8BU9_2\ : NOR2A - port map(A => casa, B => N_3355_1, Y => un17_casaen_0_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I236_Y_1\ : AO1 - port map(A => N590, B => N575, C => ADD_30x30_fast_I236_Y_0, - Y => ADD_30x30_fast_I236_Y_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I263_Y_0 : AND2 - port map(A => I163_un1_Y, B => N566_i, Y => - ADD_33x33_fast_I263_Y_0); - - \r.x.npc_0_RNILNE41[0]\ : MX2C - port map(A => N_3220, B => N_3250, S => \npc_0[0]\, Y => - \xc_result[9]\); - - \r.w.result_RNI70P1[13]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[13]\, Y - => \result_m_0_0[13]\); - - \r.m.icc_RNO_4[2]\ : OR3C - port map(A => icc_0_sqmuxa_1_28, B => icc_0_sqmuxa_1_27, C - => icc_0_sqmuxa_1_29, Y => icc_0_sqmuxa_1_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I312_Y_0 : XOR2 - port map(A => N784_0, B => \un6_ex_add_res_s2_1[22]\, Y => - \un6_ex_add_res_s2[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I16_G0N : NOR2B - port map(A => \un1_iu0_6[15]\, B => \op2[15]\, Y => N442_0); - - \r.x.rstate_0_RNISNTD2[0]\ : MX2C - port map(A => N_3417, B => \xc_result[26]\, S => - \rstate_0[0]\, Y => \wdata[26]\); - - \r.m.y_RNO[11]\ : OR3C - port map(A => \y_iv_1[11]\, B => \y_iv_0[11]\, C => - \logicout_m[11]\, Y => \y_1[11]\); - - \r.m.ctrl.rd_RNIEK714[0]\ : NOR3C - port map(A => wreg_1_0_0, B => un2_rs1_2_0_i_0, C => - wreg_1_3, Y => wreg_1_6_0); - - \r.e.ldbp2_RNI8UML75\ : MX2C - port map(A => \un6_ex_add_res_s1_i[31]\, B => N_6577, S => - ldbp2_3, Y => \eaddress[30]\); - - \r.e.ctrl.pc[30]\ : DFN1E0 - port map(D => \pc[30]\, CLK => lclk_c, E => holdn, Q => - \pc_0[30]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I9_G0N\ : NOR2B - port map(A => \inst_0[9]\, B => \dpc[11]\, Y => N385); - - \r.x.data_0_RNO_2[6]\ : AO1B - port map(A => rdatav_0_1_1_iv_7(6), B => mcdo_m_0_4, C => - N_3456, Y => \dco_m_i[102]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I170_un1_Y\ : NOR2A - port map(A => N544, B => N537, Y => I170_un1_Y); - - \r.m.result[17]\ : DFN1E0 - port map(D => \eres2[17]\, CLK => lclk_c, E => holdn, Q => - \maddress[17]\); - - \r.d.inst_0_RNI4023_0[20]\ : OR2 - port map(A => \inst_0[20]\, B => \inst_0[19]\, Y => - un7_op_3); - - un6_ex_add_res_d2_ADD_33x33_fast_I148_Y : OR2B - port map(A => N549, B => N545_0, Y => N611); - - un6_ex_add_res_d0_ADD_33x33_fast_I9_P0N : OR3A - port map(A => \data_0[8]\, B => \op1[8]\, C => ldbp1_0, Y - => N422_0); - - \r.x.rstate_RNIKDGG[1]\ : NOR2 - port map(A => \rstate[1]\, B => xc_wreg9, Y => N_6352); - - \r.e.ctrl.inst_RNIB4OA3[26]\ : AOI1B - port map(A => ex_bpmiss_1_0_2_tz_0, B => - ex_bpmiss_1_0_1630_0, C => N_475, Y => ex_bpmiss_1_0_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I58_Y : NOR2B - port map(A => N452_0, B => N449_1, Y => N517_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I5_G0N : NOR2B - port map(A => \un1_iu0_6[4]\, B => \op2[4]\, Y => N409); - - \r.x.result_RNID4AN3[14]\ : MX2C - port map(A => \un1_iu0_6[14]\, B => \un1_p0_6[366]\, S => - bpdata6_0_0, Y => \bpdata[14]\); - - \r.x.data_0_RNO_4[8]\ : OR2A - port map(A => \data_0[8]\, B => ld_0_0, Y => - \data_0_m_i[8]\); - - \r.f.pc_RNI7DJ3E1[3]\ : MX2 - port map(A => I_5, B => N_4046, S => bpmiss_1_i_0_0, Y => - \pc_4[3]\); - - \r.f.pc[15]\ : DFN1E0 - port map(D => \pc_1[15]\, CLK => lclk_c, E => holdn, Q => - \fpc[15]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I55_Y_0_o3 : AOI1 - port map(A => N455_1, B => N451_2, C => N454_1, Y => N514_2); - - \r.w.result[22]\ : DFN1E0 - port map(D => \wdata[22]\, CLK => lclk_c, E => holdn, Q => - \result[22]\); - - \r.e.shleft_1_RNIGT5I1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[18]\, S => - shleft_1, Y => \shiftin_5[49]\); - - \r.f.pc_RNO[12]\ : AO1B - port map(A => I_56, B => un2_rstn_4_0_0, C => - \pc_1_iv_2[12]\, Y => \pc_1[12]\); - - \r.e.ctrl.inst_RNIVD3H1[24]\ : NOR3B - port map(A => un3_notag, B => \icc_7_m_0[1]\, C => - \icc_8_m_5[1]\, Y => \icc_7_m_2[1]\); - - \r.m.result[4]\ : DFN1E0 - port map(D => \eres2[4]\, CLK => lclk_c, E => holdn, Q => - \maddress[4]\); - - \r.a.ctrl.inst_RNIL82S[21]\ : OR2B - port map(A => illegal_inst37_2, B => N_58, Y => - illegal_inst37_4); - - \r.e.shcnt_RNIGVRBP[1]\ : MX2C - port map(A => \shiftin_14[19]\, B => \shiftin_14[17]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[17]\); - - \r.w.s.y_RNO[24]\ : NOR3 - port map(A => N_368, B => N_367, C => N_369, Y => N_6686); - - \r.a.imm_RNI5645[4]\ : OR3B - port map(A => d29_0_0, B => \imm[4]\, C => \rsel2_0[0]\, Y - => \imm_m_i[4]\); - - \r.x.dci.SIGNED_RNILER6N2\ : NOR3C - port map(A => me_signed_1, B => data_0_7, C => - rdata_3_sqmuxa, Y => \rdata_17_m[8]\); - - \r.x.data_0_RNO_4[5]\ : AO1 - port map(A => rdatav_0_1_0_iv_4_20, B => mcdo_m_0_27, C => - rdata_0_sqmuxa, Y => \dco_m_i[125]\); - - \r.m.result_RNO[21]\ : MX2 - port map(A => \aluresult[21]\, B => \op1[21]\, S => - un17_casaen_0_2, Y => \eres2[21]\); - - \r.a.ctrl.wreg_RNO_2\ : NOR2 - port map(A => ld_1_sqmuxa, B => un19_rd, Y => - un1_ld_1_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I247_Y : AO1 - port map(A => N665, B => N614_0, C => N664_1, Y => N808_0); - - \r.e.op1_RNI9HFC[5]\ : OR2B - port map(A => \op1[5]\, B => un14_casaen_s1_0, Y => N_407); - - \r.w.s.tba_RNIGOB0H[2]\ : NOR3C - port map(A => \aluresult_1_iv_3[14]\, B => \tba_m[2]\, C - => \aluresult_1_iv_5[14]\, Y => \aluresult_1_iv_6[14]\); - - \r.e.op2_RNIR6OP[22]\ : MX2B - port map(A => \op2[22]\, B => N_4269_i, S => ldbp2_0, Y => - \un1_iu0_5[88]\); - - \r.m.y_RNO_4[2]\ : OR2B - port map(A => \y_1[3]\, B => mulstep_0, Y => \y_m_2[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I86_Y : NOR2B - port map(A => N410_2, B => N407_1, Y => N545_0); - - \r.x.intack_RNI3VGC\ : OR2A - port map(A => intack_3, B => holdn, Y => intack_2); - - \r.e.shleft_0_RNI3TH32\ : MX2A - port map(A => \shiftin_5[26]\, B => shleft_0_RNIJ8HP, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[10]\); - - \r.e.aluop_1_RNIM9842[1]\ : MX2C - port map(A => \logicout_4[5]\, B => N_6835, S => N_6866_i, - Y => N_3628); - - \r.f.pc_RNIOTGB4[14]\ : MX2 - port map(A => \dpc[14]\, B => \fpc[14]\, S => ra_bpmiss_1, - Y => N_3891); - - \r.e.op2_RNO_6[21]\ : OR3C - port map(A => d28_0, B => \rsel2_1[0]\, C => - \un1_p0_6[373]\, Y => \cpi_m_i[373]\); - - \r.e.jmpl_RNINUSPJ1\ : AOI1B - port map(A => \shiftin_17[22]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_7[21]\, Y => \aluresult_1_iv_8[21]\); - - \r.e.ctrl.tt_RNO_0[3]\ : NOR3A - port map(A => \tt_1[3]\, B => cp_disabled_4, C => - fp_disabled_4, Y => \tt_3[3]\); - - \r.d.inst_0_RNIUB0N1[23]\ : NOR3C - port map(A => \inst_0_RNIMRAH[23]\, B => ldcheck1_1, C => - ldcheck1_2, Y => ldcheck1); - - \r.d.inst_0_RNIKMSG[20]\ : OAI1 - port map(A => wy_1_0_a3_1_0, B => N_152, C => N_142, Y => - un6_op); - - \r.x.data_0[24]\ : DFN1E0 - port map(D => \data_0_1[24]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[24]\); - - \r.a.imm[23]\ : DFN1E0 - port map(D => \un3_de_ren1[141]\, CLK => lclk_c, E => holdn, - Q => \imm[23]\); - - \r.x.result_RNI90AN3[13]\ : MX2C - port map(A => \un1_iu0_6[13]\, B => \un1_p0_6[365]\, S => - bpdata6, Y => \bpdata[13]\); - - \r.x.npc_RNIQBFL[0]\ : MX2C - port map(A => N_3239, B => N_3269, S => \npc[0]\, Y => - \xc_result[28]\); - - \r.m.ctrl.rd_RNIL7P71[6]\ : XNOR2 - port map(A => \rd_1[6]\, B => \un3_de_ren1[97]\, Y => - un2_rs1_2_6_i_0); - - \r.e.op1_RNIBUD2V5[21]\ : AOI1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[21]\, C - => \d_iv_3[21]\, Y => \d_i[21]\); - - \r.e.aluop_0_RNI7D7RA[0]\ : NOR2B - port map(A => \aluresult_1_iv_3[3]\, B => \logicout_m_0[3]\, - Y => \aluresult_1_iv_4[3]\); - - \r.e.aluop_2_RNIO5713[1]\ : MX2C - port map(A => N_3554, B => \logicout_3[27]\, S => - \aluop_2[1]\, Y => N_3586); - - \r.f.pc_RNO_6[23]\ : MX2 - port map(A => \fpc[23]\, B => \eaddress[23]\, S => jump, Y - => N_4066); - - \r.e.shcnt_RNIUM6M[1]\ : MX2C - port map(A => \shcnt[1]\, B => N_3305, S => ldbp2_1, Y => - \ex_shcnt_1_i[1]\); - - \r.a.rfe2_RNIVNBMB1\ : MX2 - port map(A => rfe, B => \rfe2\, S => holdn, Y => ren2); - - \r.a.nobp_RNIIMIG\ : OR3A - port map(A => un19_inst, B => icc_check_bp_1, C => nobp, Y - => \un9_icc_check_bp\); - - \r.e.op2_RNI9S3F_0[0]\ : OR2 - port map(A => \un1_iu0_6[0]\, B => \op2_RNI59C6[0]\, Y => - \logicout_3[0]\); - - \r.d.inst_0_RNI8K79[24]\ : NOR3B - port map(A => \inst_0[20]\, B => \inst_0_0[24]\, C => - \un1_p0_6_0[60]\, Y => icc_check7_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I136_Y\ : AOI1 - port map(A => N501_0, B => N498_0, C => N497_1, Y => N556_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I95_un1_Y : OR2B - port map(A => N496_1, B => N493, Y => I95_un1_Y_0); - - \r.x.y[19]\ : DFN1E0 - port map(D => \y_0[19]\, CLK => lclk_c, E => holdn, Q => - \y_2[19]\); - - \r.x.ctrl.pc[13]\ : DFN1E0 - port map(D => \pc_3[13]\, CLK => lclk_c, E => holdn, Q => - \pc_0[13]\); - - \r.w.s.tt[6]\ : DFN1E0 - port map(D => \xc_vectt_1[6]\, CLK => lclk_c, E => N_6747, - Q => \tt[6]\); - - \r.e.shcnt_RNIBF6RA[2]\ : MX2C - port map(A => \shiftin_11[16]\, B => \shiftin_11[12]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[12]\); - - \r.x.ctrl.tt[4]\ : DFN1E0 - port map(D => \tt2[4]\, CLK => lclk_c, E => holdn, Q => - \tt_0[4]\); - - \r.e.shleft_0_RNIAJFJ3\ : MX2 - port map(A => \shiftin_5[62]\, B => \shiftin_5[46]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[46]\); - - \r.e.op2_RNO_7[14]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[366]\, Y => \cpi_m_i[366]\); - - \r.e.op1_RNIM6IR3[28]\ : NOR3C - port map(A => \rfo_m[28]\, B => \d_iv_1[28]\, C => - \op1_m_0[28]\, Y => \d_iv_3[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I203_Y : OR2 - port map(A => N606_1, B => I203_un1_Y, Y => N672_0); - - un6_fe_npc_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \fe_pc[5]\, C => - \fe_pc[6]\, Y => N_136); - - \r.x.ctrl.pc_RNICAHF[14]\ : MX2 - port map(A => \pc_0[14]\, B => \pc_1[14]\, S => \npc_0[1]\, - Y => N_3225); - - \r.x.result_RNIPMDE5[13]\ : NOR2B - port map(A => \bpdata[13]\, B => \aluop_RNIGM3N1[2]\, Y => - \bpdata_i_m[13]\); - - \r.w.s.y_RNO[20]\ : MX2 - port map(A => \y_2[20]\, B => \result[20]\, S => N_481_0, Y - => N_3784); - - \r.e.jmpl_RNI3K1NL_0\ : OR2B - port map(A => \shiftin_17[7]\, B => aluresult_2_sqmuxa_0, Y - => \shiftin_17_m_0[7]\); - - un6_fe_npc_I_108 : AND3 - port map(A => \fe_pc[17]\, B => \fe_pc[18]\, C => - \fe_pc[19]\, Y => \DWACT_FINC_E[12]\); - - \r.m.icc_RNO_23[2]\ : NOR2 - port map(A => \logicout[17]\, B => \logicout[18]\, Y => - icc_0_sqmuxa_1_7); - - \r.e.op1_RNIHEJA12[1]\ : OR2B - port map(A => \d_1_iv_4[1]\, B => \aluresult_m_i[1]\, Y => - \d_1[1]\); - - \r.e.aluop_RNIKJIJ1[2]\ : XA1 - port map(A => \un1_iu0_5[80]\, B => \aluop_1[2]\, C => - \un1_iu0_6[14]\, Y => N_3541); - - \comb.branch_address.tmp_ADD_30x30_fast_I75_Y\ : AND2 - port map(A => N374, B => N377, Y => N492); - - \r.e.op1_RNIQ8NO6[31]\ : NOR3C - port map(A => un4_icc_m, B => \op1_i_m[31]\, C => - \bpdata_i_m[31]\, Y => \edata2_iv_1[31]\); - - \r.d.inst_0_RNI7S13[17]\ : OR2 - port map(A => \inst_0[18]\, B => \inst_0[17]\, Y => - un26_rs1opt); - - \r.x.ctrl.ld_0_RNISHEJ\ : NOR3C - port map(A => N_3355_1, B => rd_7_i_0, C => ld_0, Y => - bpdata6_8); - - \r.d.inst_0_RNO[20]\ : NOR2B - port map(A => rst, B => N_4620, Y => \inst_0_RNO[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I129_Y : AO1B - port map(A => N530_0, B => N527_1, C => - ADD_33x33_fast_I129_Y_0_0, Y => N592_1); - - \r.e.alusel[1]\ : DFN1E0 - port map(D => N_3840, CLK => lclk_c, E => holdn, Q => - \alusel[1]\); - - \r.e.aluop_1_RNIA1393[1]\ : MX2C - port map(A => \logicout_4[27]\, B => N_6892, S => N_6866_i, - Y => N_3650); - - \r.d.pv_RNO_9\ : NOR2A - port map(A => \inst_0[30]\, B => annul_1, Y => - pv_12_i_a6_0_1); - - \r.m.y_RNO_0[1]\ : AOI1B - port map(A => wy_1_0, B => \y_0[1]\, C => N_378, Y => - \y_iv_0_1[1]\); - - \r.e.aluop_RNIA3IJ1[2]\ : XA1 - port map(A => \un1_iu0_5[78]\, B => \aluop_1[2]\, C => - \un1_iu0_6[12]\, Y => N_3539); - - \r.f.pc_RNIOTOUQ2[6]\ : MX2 - port map(A => I_20, B => N_4049, S => bpmiss_1_i_0_0, Y => - \pc_4[6]\); - - \comb.irq_trap.un3_irl\ : AO1 - port map(A => un5_irl_1, B => un5_irl_0, C => un2_irl, Y - => un3_irl); - - un6_fe_npc_I_87 : AND3 - port map(A => \fe_pc[14]\, B => \fe_pc[15]\, C => - \fe_pc[16]\, Y => \DWACT_FINC_E[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I124_Y\ : OR3 - port map(A => I68_un1_Y, B => N385, C => I124_un1_Y, Y => - N544); - - \r.x.data_0_RNO_5[4]\ : OR2A - port map(A => \data_0[4]\, B => ld_0_0, Y => - \data_0_m_i[4]\); - - \r.e.ctrl.pc_RNI9DK11[14]\ : OR2B - port map(A => \pc_1[14]\, B => jmpl_4, Y => \cpi_m[159]\); - - \r.m.y_RNIS9Q5C[30]\ : NOR3C - port map(A => \aluop_RNIC8EB4[1]\, B => - \aluresult_1_iv_0[30]\, C => \aluop_RNI143R4[2]\, Y => - \aluresult_1_iv_4[30]\); - - \comb.fpstdata.edata2_0_iv_RNO_1[2]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[2]\, Y => - \ex_op1_i_m[2]\); - - \r.f.pc_RNO[27]\ : AO1B - port map(A => I_173, B => un2_rstn_4_0_0, C => - \pc_1_iv_2[27]\, Y => \pc_1[27]\); - - \r.e.aluop_1_RNIID791[1]\ : XOR3 - port map(A => \un1_iu0_6[29]\, B => \aluop_1[1]\, C => - \un1_iu0_5[95]\, Y => N_6850); - - \r.x.ctrl.wy_RNIMKUI\ : NOR3 - port map(A => wy_1, B => wy_2, C => wy_0, Y => wy_RNIMKUI); - - \r.e.op1_RNIQG5I1[1]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[1]\, Y => - \ex_op1_i_m[1]\); - - \r.e.op1_RNIJS6S62[2]\ : OR3C - port map(A => \op1_m_0[2]\, B => \d_iv_2[2]\, C => - \aluresult_m_0[2]\, Y => \d[2]\); - - \r.d.inst_0_RNO[17]\ : NOR2B - port map(A => rst, B => N_4617, Y => \inst_0_RNO[17]\); - - \r.e.op2_RNIQKAP[6]\ : OR2A - port map(A => \un1_iu0_5[72]\, B => \un1_iu0_6[6]\, Y => - \logicout_4[6]\); - - wovf_exc_1_sqmuxa : NOR2A - port map(A => un7_op, B => \wovf_exc_0_sqmuxa\, Y => - \wovf_exc_1_sqmuxa\); - - \r.e.op2_RNO_6[31]\ : OR2B - port map(A => data2(31), B => d25, Y => \rfo_m_i[63]\); - - \r.d.pv_RNI83B6_0\ : NOR2 - port map(A => pv, B => annul_2, Y => un23_exbpmiss_0); - - \r.x.data_0_RNO_2[3]\ : OR2A - port map(A => data_0_0_27, B => rdata_0_sqmuxa, Y => - \dco_m_i[123]\); - - \r.x.data_0_RNI8F9E[11]\ : XOR2 - port map(A => \data_0_2[11]\, B => invop2_1, Y => N_4258); - - \r.e.aluop_RNIFFBU6[0]\ : OR2B - port map(A => \logicout[27]\, B => aluresult_3_sqmuxa, Y - => \logicout_m_0[27]\); - - \r.e.jmpl_RNI3K1NL\ : NAND2 - port map(A => aluresult_1_sqmuxa_0, B => \shiftin_17[7]\, Y - => \shiftin_17_m[7]\); - - \r.m.ctrl.inst_RNIM8PR2[21]\ : OA1 - port map(A => \inst_RNI884O1[22]\, B => inst_1, C => - result_1, Y => trap_0_sqmuxa_4); - - \r.f.pc_RNO_3[31]\ : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[31]\, C => - \xc_trap_address_m[31]\, Y => \pc_1_iv_0[31]\); - - \r.a.ctrl.inst_RNIRS231[23]\ : NOR2 - port map(A => N_515, B => N_487, Y => illegal_inst33); - - \r.x.ctrl.inst[26]\ : DFN1E0 - port map(D => \inst_3[26]\, CLK => lclk_c, E => holdn, Q - => \inst[26]\); - - \r.m.result_RNIFJD4[27]\ : OR2B - port map(A => d13_0, B => \maddress[27]\, Y => - \result_m_0[27]\); - - \r.e.op2_RNO_0[17]\ : OR3C - port map(A => \op1_m_i[17]\, B => \d_1_iv_3[17]\, C => - \aluresult_m_i[17]\, Y => \d_1[17]\); - - \r.d.inst_0_RNO_0[8]\ : MX2 - port map(A => data_0_2_8, B => \inst_0[8]\, S => - inull_RNIFV6VG2_0, Y => N_4608); - - \r.d.pc[3]\ : DFN1 - port map(D => \pc_RNO[3]\, CLK => lclk_c, Q => \dpc[3]\); - - \r.e.op2_RNO_5[10]\ : OR2B - port map(A => \result_0[10]\, B => d31, Y => - \result_m_i[10]\); - - \r.e.ldbp1_0\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_0); - - \r.a.cwp[0]\ : DFN1E0 - port map(D => \cwp_0[0]\, CLK => lclk_c, E => holdn, Q => - \cwp_2[0]\); - - \r.x.ctrl.rd_RNICV3D[5]\ : XA1A - port map(A => \rd[5]\, B => \rd_0[5]\, C => rd_6_i_0, Y => - bpdata6_4); - - \r.a.ctrl.inst_RNINU2KD[21]\ : OR3C - port map(A => inst_14, B => illegal_inst34_3, C => - un1_illegal_inst33_2, Y => un1_illegal_inst33); - - \comb.branch_address.tmp_ADD_30x30_fast_I13_P0N\ : OR2 - port map(A => \inst_0[13]\, B => \dpc[15]\, Y => N398_2); - - \r.x.npc_RNIQABL[0]\ : MX2C - port map(A => N_3231, B => N_3261, S => \npc[0]\, Y => - \xc_result[20]\); - - \r.e.ctrl.inst_RNIJ8JA[27]\ : AOI1 - port map(A => \inst_1[27]\, B => \icc_0[0]\, C => - \icc_0[2]\, Y => ex_bpmiss_1_0_a5_3_0); - - \r.x.ctrl.wy\ : DFN1E0 - port map(D => wy_1, CLK => lclk_c, E => holdn, Q => wy_2); - - \r.x.ctrl.inst_RNISL1E_0[22]\ : NOR2A - port map(A => \inst_0[22]\, B => \inst_1[19]\, Y => - cwp_2_sqmuxa_1); - - \r.x.result[15]\ : DFN1E0 - port map(D => \maddress[15]\, CLK => lclk_c, E => holdn, Q - => \result_0[15]\); - - \r.x.result_RNIH22O3[23]\ : MX2 - port map(A => \un1_iu0_6[23]\, B => \un1_p0_6[375]\, S => - bpdata6, Y => \bpdata[23]\); - - \r.e.jmpl_RNI31UJV\ : OR2B - port map(A => \shiftin_17[30]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[30]\); - - \r.a.ctrl.inst_RNI3RNK9[19]\ : OR2 - port map(A => illegal_inst_7_iv_2_0_a5_0_1, B => N_603, Y - => \inst_RNI3RNK9[19]\); - - \r.e.mulstep\ : DFN1E0 - port map(D => N_227, CLK => lclk_c, E => holdn, Q => - mulstep); - - \r.w.s.tt[1]\ : DFN1 - port map(D => \tt_RNO[1]\, CLK => lclk_c, Q => \irl[1]\); - - \r.e.op1_RNO[24]\ : MX2C - port map(A => \d_i[24]\, B => \d_i[25]\, S => N_227, Y => - \aop1[24]\); - - \r.d.inst_0_RNO[15]\ : NOR2B - port map(A => rst, B => N_4615, Y => \inst_0_RNO[15]\); - - \r.a.ctrl.inst_RNILPIS7[23]\ : OR2B - port map(A => \inst_1[23]\, B => N_474, Y => N_603); - - \comb.branch_address.tmp_ADD_30x30_fast_I270_Y_0_0\ : XOR2 - port map(A => \dpc[12]\, B => \inst_0[10]\, Y => - ADD_30x30_fast_I270_Y_0_0); - - \r.e.op2_RNO_8[7]\ : OR3B - port map(A => d29_0_0, B => \imm[7]\, C => \rsel2_0[0]\, Y - => \imm_m_i[7]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I261_un1_Y_0 : NOR2B - port map(A => N629_1, B => N645_0, Y => - ADD_33x33_fast_I261_un1_Y_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I312_Y_0 : XNOR2 - port map(A => N784, B => \un6_ex_add_res_s2_1[22]\, Y => - \un6_ex_add_res_s0[22]\); - - \r.x.ctrl.tt_RNO[1]\ : OR2B - port map(A => N_4210_i_0, B => N_4205, Y => \tt2[1]\); - - \r.e.aluop_RNIOJAJ2[1]\ : OR2 - port map(A => aluresult_6_sqmuxa, B => N_3957_1, Y => - N_3957); - - \r.m.y_RNO_2[29]\ : OR2B - port map(A => \y[29]\, B => y08, Y => N_416); - - \comb.branch_address.tmp_ADD_30x30_fast_I288_Y_0\ : XOR2 - port map(A => N696, B => ADD_30x30_fast_I288_Y_0_0, Y => - \tmp[30]\); - - \r.w.s.tba[5]\ : DFN1E1 - port map(D => \result_0[17]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[5]\); - - \r.e.op1_RNIB8EM42[3]\ : OR3C - port map(A => \op1_m_0[3]\, B => \d_iv_2[3]\, C => - \aluresult_m_0[3]\, Y => \d[3]\); - - \r.a.ctrl.pc_RNISGM0C[9]\ : MX2 - port map(A => \pc_0[9]\, B => N_3886, S => ex_bpmiss_1_0, Y - => \fe_pc[9]\); - - \r.e.ctrl.inst_RNI792S[24]\ : NOR3C - port map(A => \inst[19]\, B => \inst[24]\, C => un3_notag, - Y => \icc_8_m_1[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I3_G0N : NOR3A - port map(A => \op1[2]\, B => ldbp1_2, C => \data_0[2]\, Y - => N403_0); - - \r.e.shcnt_RNIUQ6M[2]\ : MX2C - port map(A => \shcnt[2]\, B => N_3306, S => ldbp2_0, Y => - \ex_shcnt_1_i_0[2]\); - - \r.a.rsel1_RNI5L1QF2[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[7]\, Y - => \aluresult_m_0[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I119_Y : AO1 - port map(A => N520_0, B => N517, C => N516, Y => N582_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I171_Y : AO1 - port map(A => N582_2, B => N575_2, C => N574_0, Y => N640_1); - - \r.e.shcnt_RNIQDP4T[1]\ : MX2C - port map(A => \shiftin_14[28]\, B => \shiftin_14[26]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[26]\); - - \r.e.jmpl_RNIH1GEJ\ : OR2B - port map(A => \shiftin_17[1]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[1]\); - - \r.f.pc[18]\ : DFN1E0 - port map(D => \pc_1[18]\, CLK => lclk_c, E => holdn, Q => - \fpc[18]\); - - \r.e.aluop_RNIR2AF5[0]\ : MX2C - port map(A => N_3579, B => N_3643, S => \aluop_1[0]\, Y => - \logicout[20]\); - - \r.f.pc[24]\ : DFN1E0 - port map(D => \pc_1[24]\, CLK => lclk_c, E => holdn, Q => - \fpc[24]\); - - \r.f.pc_RNI9GM4[7]\ : OR2A - port map(A => \fpc[7]\, B => rst, Y => \pc_m[7]\); - - \r.f.pc_RNI4Q2IL[8]\ : MX2 - port map(A => \fpc[8]\, B => \eaddress[8]\, S => jump_0, Y - => N_4051); - - \r.m.y_RNO_0[17]\ : NOR3C - port map(A => \y_m[18]\, B => \y_m_0[17]\, C => - \y_iv_1[17]\, Y => \y_iv_2[17]\); - - \r.f.pc_RNO_0[21]\ : NAND2 - port map(A => \tmp[21]\, B => \un2_rstn_5\, Y => - \tmp_m[21]\); - - \comb.lock_gen.un1_icc_check5_RNIRTRJ\ : AO1 - port map(A => un1_icc_check5_1_0, B => un1_icc_check5, C - => un1_inst, Y => ldcheck2_0_sqmuxa_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I219_Y\ : AO1 - port map(A => N614, B => N599, C => N598, Y => N729); - - \comb.branch_address.tmp_ADD_30x30_fast_I114_un1_Y\ : NOR2B - port map(A => N479_0, B => N476_0, Y => I114_un1_Y); - - \r.e.aluop_RNI2QON_0[1]\ : NOR3A - port map(A => logicout19_0, B => \aluop_3[1]\, C => - aluresult_9_sqmuxa_1, Y => aluresult_6_sqmuxa); - - \r.a.imm[28]\ : DFN1E0 - port map(D => \un3_de_ren1[146]\, CLK => lclk_c, E => holdn, - Q => \imm[28]\); - - \r.f.pc_RNI00F6B2[5]\ : MX2 - port map(A => I_13, B => N_4048, S => bpmiss_1_i_0, Y => - \pc_4[5]\); - - \r.e.ctrl.inst_RNIQT1J7[26]\ : NOR2 - port map(A => ex_bpmiss_1_0_1, B => ex_bpmiss_1_0_2, Y => - ex_bpmiss_1_0); - - \r.e.ctrl.pc_RNIDOTN2[24]\ : NOR2A - port map(A => \cpi_m[169]\, B => \aluresult_6[31]\, Y => - \aluresult_1_iv_1[24]\); - - \r.e.aluop_RNI357O6[0]\ : MX2C - port map(A => N_3578, B => N_3642, S => \aluop_1[0]\, Y => - \logicout[19]\); - - un37_ra_I_14 : XOR2 - port map(A => \cwp_0[2]\, B => - \DWACT_ADD_CI_0_g_array_1_0[0]\, Y => I_14_0); - - \r.a.wovf\ : DFN1E0 - port map(D => \wovf_exc_0_sqmuxa_1\, CLK => lclk_c, E => - holdn, Q => wovf); - - \r.d.inst_0_RNO[31]\ : NOR2B - port map(A => rst, B => N_4631, Y => \inst_0_RNO[31]\); - - \r.d.pc_RNO[8]\ : MX2 - port map(A => \fpc[8]\, B => \dpc[8]\, S => N_6763_i_0, Y - => \pc_RNO[8]\); - - \r.d.inst_0_RNIFA35[28]\ : XOR2 - port map(A => \inst_0[28]\, B => N_211, Y => branch_4_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I127_Y : OAI1 - port map(A => N525_0, B => N528_2, C => N524_1, Y => N590_1); - - \r.e.op2_RNO_3[18]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[18]\, Y => - \aluresult_m_i[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I147_Y\ : NOR3C - port map(A => N462, B => N_14, C => N513, Y => N573); - - \r.e.shcnt_RNINTG101[1]\ : MX2 - port map(A => \shiftin_14[34]\, B => \shiftin_14[32]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[32]\); - - \r.f.pc[30]\ : DFN1E0 - port map(D => \pc_1[30]\, CLK => lclk_c, E => holdn, Q => - \fpc[30]\); - - \r.e.jmpl_RNITT2412\ : NOR3C - port map(A => \shiftin_17_m[9]\, B => \aluresult_1_iv_7[8]\, - C => \shiftin_17_m_0[8]\, Y => \aluresult_1_iv_9[8]\); - - \r.e.alusel_RNO_4[1]\ : NOR2 - port map(A => N_259, B => N_201, Y => N_339); - - \r.x.ctrl.tt_RNI5HVQ[0]\ : MX2 - port map(A => \result[0]\, B => \tt[0]\, S => tt_i, Y => - N_3319); - - \r.d.inst_0[5]\ : DFN1 - port map(D => \inst_0_RNO[5]\, CLK => lclk_c, Q => - \inst_0[5]\); - - \r.e.op2_RNO_4[13]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[365]\, Y => \cpi_m_i[365]\); - - \r.x.intack\ : DFN1E0 - port map(D => intack, CLK => lclk_c, E => holdn, Q => - intack_3); - - \comb.irq_trap.op_gt.un2_irl_0_I_1\ : NOR2A - port map(A => irl_0(0), B => \pil[0]\, Y => \ACT_LT4_E[0]\); - - \r.x.ctrl.pc[11]\ : DFN1E0 - port map(D => \pc_1[11]\, CLK => lclk_c, E => holdn, Q => - \pc_0[11]\); - - \r.e.aluop_RNIFN473[1]\ : MX2C - port map(A => N_3558, B => \logicout_3[31]\, S => - \aluop_3[1]\, Y => N_3590); - - \r.d.inst_0_RNO[1]\ : NOR2B - port map(A => rst, B => N_4601, Y => \inst_0_RNO[1]\); - - \r.x.ctrl.pc[22]\ : DFN1E0 - port map(D => \pc_3[22]\, CLK => lclk_c, E => holdn, Q => - \pc_0[22]\); - - \r.e.aluop_0_RNI5ALC[1]\ : XOR3 - port map(A => \un1_iu0_6[9]\, B => \aluop_0[1]\, C => - \un1_iu0_5[75]\, Y => N_6841); - - \r.e.op1_RNICDID[28]\ : MX2 - port map(A => \op1[28]\, B => \data_0[28]\, S => ldbp1, Y - => \un1_iu0_6[28]\); - - \r.x.y[14]\ : DFN1E0 - port map(D => \y_0[14]\, CLK => lclk_c, E => holdn, Q => - \y_2[14]\); - - \r.d.pc[24]\ : DFN1 - port map(D => \pc_RNO[24]\, CLK => lclk_c, Q => \dpc[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I64_Y_0\ : AO1 - port map(A => N392, B => N388, C => N391, Y => N481_2); - - \r.e.ctrl.pc[17]\ : DFN1E0 - port map(D => \pc[17]\, CLK => lclk_c, E => holdn, Q => - \pc_0[17]\); - - \r.e.ldbp2_0_RNIKIIIS\ : OR2A - port map(A => \eaddress[10]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[11]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I38_Y : AND2 - port map(A => N479, B => N482, Y => N497); - - \r.e.op2_RNIARVJ[24]\ : MX2 - port map(A => \op2[24]\, B => N_4271, S => ldbp2_2, Y => - \un1_iu0_5[90]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I300_Y_0 : XOR2 - port map(A => N814, B => ADD_33x33_fast_I300_Y_0_0, Y => - \un6_ex_add_res_s1[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I273_un1_Y_0 : NOR2B - port map(A => N552, B => N669, Y => - ADD_33x33_fast_I273_un1_Y_0); - - \r.e.op2_RNO[6]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[6]\, Y => N_290); - - \r.a.imm[12]\ : DFN1E0 - port map(D => \un3_de_ren1[130]\, CLK => lclk_c, E => holdn, - Q => \imm[12]\); - - \r.m.y_RNIP1O71[21]\ : OR2B - port map(A => \y[21]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[21]\); - - \r.f.pc_RNO_3[15]\ : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[15]\, C => - \xc_trap_address_m[15]\, Y => \pc_1_iv_0[15]\); - - \r.d.inst_0[1]\ : DFN1 - port map(D => \inst_0_RNO[1]\, CLK => lclk_c, Q => - \inst_0[1]\); - - \r.x.npc_0_RNI5TS61[0]\ : MX2C - port map(A => N_3225, B => N_3255, S => \npc_0[0]\, Y => - \xc_result[14]\); - - \r.f.pc_RNO_4[19]\ : MX2 - port map(A => I_105, B => N_4062, S => bpmiss_1_i_0, Y => - \pc_4[19]\); - - \r.f.pc[21]\ : DFN1E0 - port map(D => \pc_1[21]\, CLK => lclk_c, E => holdn, Q => - \fpc[21]\); - - \r.a.ctrl.wreg_RNO_0\ : MX2A - port map(A => un1_ld_1_sqmuxa_1, B => \inst_0_0[21]\, S => - un1_ld_1_sqmuxa, Y => write_reg); - - un6_ex_add_res_d0_ADD_33x33_fast_I46_Y : NOR2A - port map(A => N467_2, B => N470_1, Y => N505_1); - - \r.m.result_RNIVI8B3[23]\ : NOR3C - port map(A => \d_iv_0[23]\, B => \result_m_0[23]\, C => - \rfo_m[23]\, Y => \d_iv_2[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I11_G0N : NOR2B - port map(A => \un1_iu0_6[10]\, B => \op2[10]\, Y => N427_1); - - \r.x.y[16]\ : DFN1E0 - port map(D => \y[16]\, CLK => lclk_c, E => holdn, Q => - \y_2[16]\); - - \r.e.shcnt_RNI04UKN[1]\ : MX2C - port map(A => \shiftin_14[15]\, B => \shiftin_14[13]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[13]\); - - \r.e.ctrl.pc[22]\ : DFN1E0 - port map(D => \pc[22]\, CLK => lclk_c, E => holdn, Q => - \pc_2[22]\); - - \r.e.ctrl.rd_RNIA7GD7[0]\ : OR3C - port map(A => wreg_2_4, B => wreg_2_3, C => wreg_2_5, Y => - wreg_2_1); - - \r.e.alusel_RNO_4[0]\ : NOR2A - port map(A => \inst[31]\, B => \cnt_2[1]\, Y => - \alusel_i_0_a5_0_0[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I233_Y_0_0\ : MIN3 - port map(A => \dpc[29]\, B => \inst_0_RNI8AJ4[27]\, C => - N436_0, Y => ADD_30x30_fast_I233_Y_0_0); - - \r.m.ctrl.inst[20]\ : DFN1E0 - port map(D => \inst_1[20]\, CLK => lclk_c, E => holdn, Q - => \inst_3[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I244_Y : OR2 - port map(A => I244_un1_Y, B => N658, Y => N799); - - \r.e.shcnt_RNI69NRU[1]\ : MX2B - port map(A => \shiftin_14[32]\, B => \shiftin_14[30]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[30]\); - - \r.m.ctrl.inst_RNI2Q1S[21]\ : NOR3A - port map(A => \inst_0[24]\, B => \inst[21]\, C => - trap_0_sqmuxa_1_1_i, Y => iflush_1_0); - - \r.f.pc_RNO[19]\ : OR3C - port map(A => \tmp_m[19]\, B => \pc_1_iv_1[19]\, C => - \un6_fe_npc_m[17]\, Y => \pc_1[19]\); - - \r.w.result_RNI74P1[20]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[20]\, - Y => \result_m_0_0[20]\); - - \r.e.op2_RNO_7[11]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[363]\, Y => \cpi_m_i[363]\); - - \r.e.op1_RNIR69G[25]\ : OR2B - port map(A => \op1[25]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[25]\); - - \r.a.ctrl.inst[28]\ : DFN1E0 - port map(D => \inst_0[28]\, CLK => lclk_c, E => holdn, Q - => \inst_1[28]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I261_Y_0_0\ : XOR2 - port map(A => \dpc[3]\, B => \inst_0_RNI1JUM[1]\, Y => - ADD_30x30_fast_I261_Y_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I5_P0N : AO1A - port map(A => ldbp1_1, B => \op1[4]\, C => \data_0[4]\, Y - => N410_2); - - \r.e.shcnt_RNI1V6M[3]\ : MX2C - port map(A => \shcnt[3]\, B => N_3307, S => ldbp2_1, Y => - \ex_shcnt_1_i[3]\); - - \r.d.inull_RNIP82GO\ : AOI1 - port map(A => N_3014, B => G_6_1, C => un1_exbpmiss, Y => - annul_current_4); - - \r.f.pc_RNO_2[22]\ : OR2B - port map(A => I_129, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I192_Y : NOR2B - port map(A => N603, B => N595_1, Y => N661); - - \r.x.result_RNIG7JA[0]\ : MX2 - port map(A => \result[0]\, B => \data_0[0]\, S => ld_0, Y - => \un1_p0_6[352]\); - - \r.m.y_RNO_2[10]\ : OR2A - port map(A => \logicout[10]\, B => y14, Y => - \logicout_m[10]\); - - \r.e.op2_RNO_4[30]\ : OA1A - port map(A => \maddress[30]\, B => d27_0, C => - \cpi_m_i[382]\, Y => \d_1_iv_1[30]\); - - \r.e.op2_RNIHB971_0[11]\ : OR2 - port map(A => \un1_iu0_6[11]\, B => \un1_iu0_5[77]\, Y => - \logicout_3[11]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I55_Y\ : NOR2B - port map(A => N407_0, B => N404_0, Y => N472); - - \r.e.alusel_RNIJTTQ[0]\ : OR2 - port map(A => miscout_11_sqmuxa_0, B => logicout22_1, Y => - miscout_11_sqmuxa); - - \r.w.s.ps_RNIC1HI2\ : AO1B - port map(A => rstate_8_0, B => pil_0_sqmuxa, C => ps, Y => - ps_m); - - \r.a.ctrl.wreg_RNILGCE\ : OA1A - port map(A => ldchkra_0, B => call_hold7_i, C => wreg_0, Y - => wreg_6); - - \r.x.npc_0_RNI7DS61[0]\ : MX2C - port map(A => N_3234, B => N_3264, S => \npc_0[0]\, Y => - \xc_result[23]\); - - \r.d.inst_0_RNI7AJ4[26]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[26]\, S => - \inst_0[30]\, Y => \inst_0_1[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I198_Y : NOR2B - port map(A => N609_1, B => N601_0, Y => N667); - - \r.w.s.wim_RNI6V3N2[0]\ : MX2 - port map(A => \wim[0]\, B => \result[0]\, S => wim_1_sqmuxa, - Y => \wim_1[0]\); - - \r.e.op2_RNO_1[5]\ : OR2B - port map(A => \op1[5]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[5]\); - - \r.m.y_RNO_3[8]\ : OR3A - port map(A => \y_2[8]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[8]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I205_un1_Y : NOR3C - port map(A => N545_1, B => N549_0, C => N552, Y => - I205_un1_Y_0); - - \r.m.ctrl.inst_RNIVC0E_0[30]\ : OR2A - port map(A => \inst_1[31]\, B => \inst_1[30]\, Y => trap63); - - \comb.branch_address.tmp_ADD_30x30_fast_I23_G0N\ : NOR2B - port map(A => \inst_0_1[25]\, B => \dpc[25]\, Y => N427); - - un6_ex_add_res_d1_ADD_33x33_fast_I51_un1_Y : NOR3C - port map(A => \op2[20]\, B => \un1_iu0_6[20]\, C => N461_0, - Y => I51_un1_Y); - - un6_ex_add_res_d0_ADD_33x33_fast_I203_Y : AO1A - port map(A => N607_1, B => N614_1, C => N606_0, Y => N672_1); - - \r.m.icc_RNO_5[2]\ : NOR3C - port map(A => icc_0_sqmuxa_1_14, B => icc_0_sqmuxa_1_13, C - => icc_0_sqmuxa_1_24, Y => icc_0_sqmuxa_1_28); - - \r.e.op1_RNI7DUH[23]\ : MX2 - port map(A => \op1[23]\, B => \data_0[23]\, S => ldbp1_4, Y - => \un1_iu0_6[23]\); - - \r.e.aluop_RNI7NNF_0[1]\ : OR2A - port map(A => \aluop_1[2]\, B => \aluop_3[1]\, Y => - N_6866_i); - - \r.d.inst_0_RNI2NUM[2]\ : NOR2B - port map(A => \inst_0[2]\, B => de_inst_0_sqmuxa_i_0, Y => - \inst_0_RNI2NUM[2]\); - - \r.a.ctrl.inst_RNISK2A1[21]\ : OR2A - port map(A => un1_aop2_1_sqmuxa_0_a2_0_0, B => N_204, Y => - N_457); - - \r.w.s.dwt_RNO_2\ : NOR3A - port map(A => dwt_1_sqmuxa_2, B => \inst[27]\, C => - \inst[26]\, Y => dwt_1_sqmuxa_3); - - \r.e.aluop_RNIVLQ53[0]\ : MX2C - port map(A => N_3563, B => N_3627, S => \aluop_1[0]\, Y => - \logicout[4]\); - - \r.e.aluop_0_RNI8330N[0]\ : AOI1B - port map(A => \logicout[22]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[22]\, Y => \aluresult_1_iv_7[22]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I244_Y : AO1 - port map(A => N674_1, B => N659, C => N658_1, Y => N799_1); - - \r.m.icc_RNISN961[0]\ : OR2A - port map(A => \icc_0[0]\, B => aluresult_11_sqmuxa, Y => - \icc_m[0]\); - - \r.a.ctrl.inst_RNI5KB1T[13]\ : NOR3C - port map(A => \cpi_m[121]\, B => illegal_inst_7_iv_3, C => - \inst_RNI3RNK9[19]\, Y => illegal_inst_7_iv_6_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I146_Y : NOR3C - port map(A => N407_1, B => N404_1, C => N543_1, Y => N609); - - \r.w.result_RNIUN5J[20]\ : AOI1B - port map(A => \un1_p0_6[372]\, B => d14_0, C => - \result_m_0_0[20]\, Y => \d_iv_0[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I109_Y_0\ : OA1 - port map(A => \dpc[16]\, B => \inst_0[14]\, C => N404_0, Y - => ADD_30x30_fast_I109_Y_0); - - \r.m.y[8]\ : DFN1E0 - port map(D => \y_1[8]\, CLK => lclk_c, E => holdn, Q => - \y[8]\); - - \r.x.y[12]\ : DFN1E0 - port map(D => \y[12]\, CLK => lclk_c, E => holdn, Q => - \y_2[12]\); - - \r.x.data_0[6]\ : DFN1E0 - port map(D => \data_0_1[6]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[6]\); - - \r.x.data_0[20]\ : DFN1E0 - port map(D => \data_0_1[20]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_2[20]\); - - \r.m.result[7]\ : DFN1E0 - port map(D => \eres2[7]\, CLK => lclk_c, E => holdn, Q => - \maddress[7]\); - - \r.f.pc_RNO_6[17]\ : MX2 - port map(A => \fpc[17]\, B => \eaddress[17]\, S => jump_0, - Y => N_4060); - - \r.x.data_0_RNO_1[12]\ : AO1A - port map(A => rdata_5_sqmuxa, B => data_0_0_28, C => - \data_0_m[12]\, Y => \data_0_1_0_iv_0[12]\); - - \r.w.result_RNI0MDI[12]\ : AOI1B - port map(A => \un1_p0_6[364]\, B => d14_0, C => - \result_m_0_0[12]\, Y => \d_iv_0[12]\); - - \r.m.ctrl.pc[27]\ : DFN1E0 - port map(D => \pc[27]\, CLK => lclk_c, E => holdn, Q => - \pc_2[27]\); - - \r.f.pc[26]\ : DFN1E0 - port map(D => \pc_1[26]\, CLK => lclk_c, E => holdn, Q => - \fpc[26]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I29_G0N : NOR2B - port map(A => \un1_iu0_6[28]\, B => \op2[28]\, Y => N481_0); - - \r.w.s.pil[2]\ : DFN1E0 - port map(D => \result[10]\, CLK => lclk_c, E => N_6699, Q - => \pil[2]\); - - \r.m.y[27]\ : DFN1E0 - port map(D => \y_1[27]\, CLK => lclk_c, E => holdn, Q => - \y_0[27]\); - - \r.e.aluop_RNIO1I14[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[2]\, Y => - \bpdata_i_m_2[2]\); - - \r.a.rsel1_0_RNIDBLJ2[2]\ : OR2B - port map(A => data1(30), B => d11, Y => \rfo_m[30]\); - - un6_fe_npc_I_176 : AND2 - port map(A => \fe_pc[26]\, B => \fe_pc[27]\, Y => - \DWACT_FINC_E[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I111_Y : OR2A - port map(A => I111_un1_Y_i, B => N508_1, Y => N574); - - \r.f.pc_RNO_4[29]\ : MX2 - port map(A => I_196, B => N_4072, S => bpmiss_1_i_0, Y => - \pc_4[29]\); - - \r.m.y_RNO_2[26]\ : OR2B - port map(A => \y_1[26]\, B => y08, Y => \y_m_0[26]\); - - \r.f.pc_RNIIKIGQ3[6]\ : AOI1B - port map(A => \de_hold_pc_1\, B => \pc_4[6]\, C => - \xc_trap_address_m[6]\, Y => m21_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I176_Y : NOR2B - port map(A => N587_1, B => N579_1, Y => N645_0); - - \r.x.npc_0_RNITSR61[0]\ : MX2C - port map(A => N_3223, B => N_3253, S => \npc_0[0]\, Y => - \xc_result[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I184_un1_Y\ : NOR3C - port map(A => N494, B => N498_0, C => N501_0, Y => - I184_un1_Y); - - \r.e.shleft_0_RNIJ8HP\ : NOR2A - port map(A => \un1_iu0_6[10]\, B => shleft_0, Y => - shleft_0_RNIJ8HP); - - \r.m.y_RNO_1[17]\ : OR2B - port map(A => \y_1[18]\, B => mulstep_0, Y => \y_m[18]\); - - \r.d.cwp_RNIID231[2]\ : MX2 - port map(A => \cwp_0[2]\, B => \ncwp_3[2]\, S => un8_op, Y - => \ncwp[2]\); - - \r.m.ctrl.trap_RNIU6LS1\ : OR3A - port map(A => trap_0_sqmuxa_7_1, B => annul_RNIPFOQ, C => - holdn, Y => trap_0_sqmuxa_7); - - \r.e.alusel_RNIE66B[0]\ : OR3C - port map(A => \alusel[0]\, B => \alusel[1]\, C => - \aluop_0[2]\, Y => miscout_11_sqmuxa_0); - - \r.a.rsel1_RNO_0[0]\ : NOR3C - port map(A => wreg_1_5, B => wreg_1_6_0, C => wreg_2_1, Y - => \rsel1_RNO_0[0]\); - - \r.m.y_RNI84VAC[31]\ : NOR3C - port map(A => \aluop_RNIK0RF4[1]\, B => - \aluresult_1_iv_0[31]\, C => \bpdata_m_0[15]\, Y => - \aluresult_1_iv_4[31]\); - - \r.e.aluop_RNI2TDE7[1]\ : OA1A - port map(A => aluresult_6_sqmuxa, B => \bpdata[26]\, C => - \aluresult_1_iv_0[26]\, Y => \aluresult_1_iv_2[26]\); - - \r.e.op2_RNO_1[8]\ : OR2B - port map(A => \op1[8]\, B => un14_casaen_s1, Y => - \op1_m_i[8]\); - - un6_fe_npc_I_19 : NOR2B - port map(A => \fe_pc[5]\, B => \DWACT_FINC_E[0]\, Y => - N_139); - - \r.f.pc_RNO_1[18]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[18]\, C => - \pc_1_iv_0[18]\, Y => \pc_1_iv_1[18]\); - - \r.e.op1_RNITI9G[18]\ : OR2B - port map(A => \op1[18]\, B => un14_casaen_s1_0, Y => - \op1_m_0[18]\); - - \r.x.data_0_RNO_0[10]\ : NOR3A - port map(A => \data_0_1_0_iv_0[10]\, B => \rdata_13_m[8]\, - C => \rdata_17_m[8]\, Y => \data_0_1_0_iv_1[10]\); - - un6_fe_npc_I_202 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \fe_pc[29]\, Y => N_9_0); - - \r.f.pc_RNO_1[24]\ : NOR3C - port map(A => \pc_4_m[24]\, B => \xc_trap_address_m[24]\, C - => \un6_ex_add_res_m_1[25]\, Y => \pc_1_iv_1[24]\); - - \r.a.ctrl.pc[29]\ : DFN1E0 - port map(D => \dpc[29]\, CLK => lclk_c, E => holdn, Q => - \pc[29]\); - - \r.e.op2_RNO[20]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[20]\, Y => N_304); - - \r.x.npc_RNICC9R[0]\ : MX2C - port map(A => N_3238, B => N_3268, S => \npc[0]\, Y => - \xc_result[27]\); - - \r.e.shcnt_RNIVETT4[3]\ : MX2 - port map(A => \shiftin_8[24]\, B => \shiftin_8[16]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[16]\); - - \r.e.op2[18]\ : DFN1E0 - port map(D => N_302, CLK => lclk_c, E => holdn, Q => - \op2[18]\); - - \r.e.ldbp2_0_RNI3K98R1\ : OR2A - port map(A => \eaddress[16]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[17]\); - - \r.e.op1_RNI5K76B3[11]\ : NOR3C - port map(A => \op1_m_0[11]\, B => \d_iv_2[11]\, C => - \aluresult_m_0[11]\, Y => \d_i[11]\); - - \r.e.op2_RNO_3[22]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[22]\, Y => - \aluresult_m_i[22]\); - - \r.e.op2_RNI15BP[8]\ : OR2A - port map(A => \un1_iu0_5[74]\, B => \un1_iu0_6[8]\, Y => - \logicout_4[8]\); - - \r.e.op1_RNIALUH[25]\ : MX2 - port map(A => \op1[25]\, B => \data_0[25]\, S => ldbp1_3, Y - => \un1_iu0_6[25]\); - - \r.m.y_RNO[16]\ : OR3C - port map(A => \y_iv_1[16]\, B => \y_iv_0[16]\, C => - \logicout_m[16]\, Y => \y_1[16]\); - - \r.e.jmpl_RNISQNAQ_0\ : OR2B - port map(A => \shiftin_17[18]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[18]\); - - \r.a.rsel1_RNIVHHI33[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[10]\, Y => - \aluresult_m_0[10]\); - - \r.m.y_RNO_2[2]\ : OR2A - port map(A => \logicout[2]\, B => y14, Y => \logicout_m[2]\); - - \r.x.data_0_RNO[17]\ : OR3 - port map(A => \rdata_5_m_9[8]\, B => \rdata_13_m_9[8]\, C - => \data_0_1_1_iv_1[17]\, Y => \data_0_1[17]\); - - \r.d.inst_0_RNI5C23_1[31]\ : OR2A - port map(A => \inst_0[31]\, B => \inst_0[30]\, Y => - un1_inst); - - un6_ex_add_res_d0_ADD_33x33_fast_I123_Y : AO1 - port map(A => N524_0, B => N521, C => N520_0, Y => N586); - - \r.a.ctrl.wy_RNO_1\ : NOR2A - port map(A => wy_1_0_a3_1_0, B => un3_op2, Y => wy_1_0_a3_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I38_Y : OR2B - port map(A => N482_0, B => N479_2, Y => N497_2); - - \r.x.ctrl.tt_RNIF50R[5]\ : MX2C - port map(A => \result_0[5]\, B => \tt_0[5]\, S => tt_i, Y - => N_3324); - - \r.a.ctrl.inst_RNIN8T1C[22]\ : AO1B - port map(A => illegal_inst_7_iv_6_tz, B => - illegal_inst_7_iv_2_0_a5_1_0, C => N_474, Y => - illegal_inst_7_iv_5); - - \r.f.pc_RNO_7[25]\ : MX2 - port map(A => \fpc[25]\, B => \tba[13]\, S => rstate_6314_d, - Y => \xc_trap_address[25]\); - - \r.e.jmpl_RNI9N7SH1\ : AND2 - port map(A => \shiftin_17_m[21]\, B => - \aluresult_1_iv_7[20]\, Y => \aluresult_1_iv_8[20]\); - - \r.m.y_RNO_1[2]\ : AOI1B - port map(A => \y_0[2]\, B => y08_0, C => \y_m_2[3]\, Y => - \y_iv_0[2]\); - - \comb.ld_align.rdata199_RNIL4S4S\ : NOR2B - port map(A => rdata_2_sqmuxa_1, B => ld_0_0, Y => - rdata_2_sqmuxa); - - \r.f.pc_RNI2M3CJ3[2]\ : NOR3C - port map(A => \pc_4_m[2]\, B => \tmp_m[2]\, C => - \npc_iv_1[2]\, Y => \npc_iv_3[2]\); - - \r.e.ldbp2_RNI4B3TI6\ : OR3C - port map(A => \aluresult_1_iv_8[24]\, B => - \shiftin_17_m_0[24]\, C => \un6_ex_add_res_m[25]\, Y => - \aluresult[24]\); - - \r.m.result[5]\ : DFN1E0 - port map(D => \eres2[5]\, CLK => lclk_c, E => holdn, Q => - \maddress[5]\); - - \r.m.dci.size_RNO_2[0]\ : NOR2B - port map(A => \inst_1[22]\, B => \inst[19]\, Y => N_3758); - - \r.e.ctrl.pc_RNIBLK11[16]\ : OR2B - port map(A => \pc[16]\, B => jmpl_0, Y => \cpi_m[161]\); - - \r.w.s.y[30]\ : DFN1E0 - port map(D => N_3794, CLK => lclk_c, E => N_6922_i, Q => - \y_0[30]\); - - \r.m.ctrl.pc_RNIEMF8[8]\ : MX2 - port map(A => \pc_3[8]\, B => \pc[8]\, S => \npc[1]\, Y => - N_3249); - - \r.m.ctrl.inst_RNIVK0E[23]\ : NOR2A - port map(A => \inst_3[20]\, B => \inst_2[23]\, Y => - trap_0_sqmuxa_2_0); - - \r.d.inst_0_RNO_0[28]\ : MX2 - port map(A => data_0_2_28, B => \inst_0[28]\, S => - inull_RNIFV6VG2_0, Y => N_4628); - - un6_ex_add_res_d1_ADD_33x33_fast_I293_Y_0_0 : XOR2 - port map(A => \op2[2]\, B => \un1_iu0_6[2]\, Y => - ADD_33x33_fast_I293_Y_0_0); - - \r.x.ctrl.tt[5]\ : DFN1E0 - port map(D => \tt2[5]\, CLK => lclk_c, E => holdn, Q => - \tt_0[5]\); - - \r.a.ctrl.wreg_RNO_6\ : OA1 - port map(A => N_89, B => N_122_1, C => inst_0, Y => - write_reg7_0); - - \r.d.annul_RNIETIP\ : NOR3B - port map(A => un19_inst, B => not_valid, C => - icc_check_bp_1, Y => annul_RNIETIP); - - \r.x.data_0_RNO_2[4]\ : OR2A - port map(A => data_0_0_28, B => rdata_0_sqmuxa, Y => - \dco_m_i[124]\); - - \r.w.s.y_RNO[23]\ : MX2 - port map(A => \y_2[23]\, B => \result[23]\, S => N_481_0, Y - => N_3787); - - \r.f.pc_RNO_5[30]\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[30]\, Y => - \un6_ex_add_res_m_1[31]\); - - \r.x.ctrl.inst_RNIF32S_0[19]\ : NOR3A - port map(A => wim_1_sqmuxa_0, B => \inst[20]\, C => - \inst_1[19]\, Y => y_0_sqmuxa_1_1); - - \r.x.ctrl.rd_RNISU3D[1]\ : XA1A - port map(A => \rd[1]\, B => \rd_1[1]\, C => rd_2_i_0, Y => - bpdata6_2); - - \r.a.rsel2[1]\ : DFN1E0 - port map(D => N_3946, CLK => lclk_c, E => holdn, Q => - \rsel2[1]\); - - un6_fe_npc_I_16 : AND3 - port map(A => \fe_pc[2]\, B => \fe_pc[3]\, C => \fe_pc[4]\, - Y => \DWACT_FINC_E[0]\); - - \r.x.ctrl.pc_RNI9IGF[21]\ : MX2 - port map(A => \pc_2[21]\, B => \pc_0[21]\, S => \npc_1[1]\, - Y => N_3232); - - \r.e.jmpl_RNIH1GEJ_0\ : OR2B - port map(A => \shiftin_17[1]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[1]\); - - \r.m.ctrl.rd[4]\ : DFN1E0 - port map(D => \rd_0[4]\, CLK => lclk_c, E => holdn, Q => - \rd[4]\); - - \r.e.op1[19]\ : DFN1E0 - port map(D => \aop1[19]\, CLK => lclk_c, E => holdn, Q => - \op1[19]\); - - \r.e.invop2_RNI4EL7S2\ : MX2 - port map(A => \un6_ex_add_res_s2[29]\, B => - \un6_ex_add_res_s0[29]\, S => invop2, Y => N_6625); - - \r.a.ctrl.inst_RNIU43A1[21]\ : OR3A - port map(A => \inst_2[21]\, B => N_207, C => N_515, Y => - inst_14); - - \r.m.ctrl.pc_RNIRPGF[22]\ : MX2 - port map(A => \pc_3[22]\, B => \pc[22]\, S => \npc_0[1]\, Y - => N_3263); - - \r.e.op2_RNIVMIF[20]\ : MX2 - port map(A => \op2[20]\, B => N_4267, S => ldbp2_3, Y => - \un1_iu0_5[86]\); - - \r.e.ctrl.inst_RNI963Q7[29]\ : OR2A - port map(A => \inst_2[29]\, B => ex_bpmiss_1, Y => - ra_bpannul_1); - - \r.e.jmpl_RNI4HD5L_0\ : OR2B - port map(A => \shiftin_17[4]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[4]\); - - \r.x.result[2]\ : DFN1E0 - port map(D => \maddress[2]\, CLK => lclk_c, E => holdn, Q - => \result_0[2]\); - - un54_ra_I_13 : XOR2 - port map(A => \ncwp[1]\, B => \DWACT_ADD_CI_0_TMP[0]\, Y - => I_13_0); - - \r.w.s.y[28]\ : DFN1E0 - port map(D => N_3792, CLK => lclk_c, E => N_6922_i, Q => - \y_0[28]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I172_un1_Y\ : NOR2A - port map(A => N546_1, B => N539, Y => I172_un1_Y); - - \r.e.op1_RNIUM9G[19]\ : OR2B - port map(A => \op1[19]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[19]\); - - \r.a.rfa2_RNI7N361[0]\ : MX2 - port map(A => \inst_0_RNI0FUM[0]\, B => \rfa2[0]\, S => - holdn, Y => raddr2(0)); - - un6_ex_add_res_d1_ADD_33x33_fast_I114_Y : NOR3B - port map(A => N458, B => N461_0, C => N_30, Y => N577_0); - - \r.e.op2_RNO_8[14]\ : OR3B - port map(A => d29_0_0, B => \imm[14]\, C => \rsel2_1[0]\, Y - => \imm_m_i[14]\); - - \r.x.data_0[11]\ : DFN1E0 - port map(D => \data_0_1[11]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_2[11]\); - - \r.f.pc_RNO_5[24]\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[24]\, Y => - \un6_ex_add_res_m_1[25]\); - - \r.d.inull_RNIH24EP\ : NOR2A - port map(A => annul_current_4, B => \un1_p0_6[0]\, Y => - annul_current_0); - - un54_ra_I_9 : XOR2 - port map(A => \ncwp[0]\, B => N_79, Y => - \DWACT_ADD_CI_0_partial_sum_2[0]\); - - \r.e.shleft_0_RNIL4LK1\ : MX2C - port map(A => \shiftin_5[16]\, B => \shiftin_5[0]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I240_Y\ : OR3C - port map(A => I206_un1_Y, B => N582_0, C => I240_un1_Y, Y - => N710); - - \r.e.shcnt_RNIJATPO[1]\ : MX2C - port map(A => \shiftin_14[18]\, B => \shiftin_14[16]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[16]\); - - \r.e.shcnt_RNI8RII6[3]\ : MX2 - port map(A => \shiftin_8[35]\, B => \shiftin_8[27]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[27]\); - - \r.m.y[17]\ : DFN1E0 - port map(D => \y_1[17]\, CLK => lclk_c, E => holdn, Q => - \y[17]\); - - \r.e.op2_RNO_1[27]\ : OR2B - port map(A => \op1[27]\, B => un14_casaen_s1, Y => - \op1_m_i[27]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I215_un1_Y : OR2B - port map(A => N644_0, B => N629_1, Y => I215_un1_Y_0); - - \r.e.ldbp2_RNI7DGUV\ : MX2 - port map(A => \un6_ex_add_res_s1_i[12]\, B => N_6631, S => - ldbp2_3, Y => \eaddress[11]\); - - \r.x.result_RNILHB25[0]\ : NOR2 - port map(A => \bpdata[0]\, B => N_3703_i, Y => - \bpdata_i_m_1[0]\); - - \r.e.op1_RNIIGKS4[18]\ : AO1A - port map(A => \bpdata[18]\, B => edata_2_sqmuxa, C => - \op1_i_m[18]\, Y => \edata2_0_iv_0[18]\); - - \r.a.ctrl.inst_RNICC1E_0[19]\ : OR2A - port map(A => \inst_2[20]\, B => \inst_2[19]\, Y => N_472); - - un6_ex_add_res_d1_ADD_33x33_fast_I260_Y_0 : MIN3 - port map(A => \op2[29]\, B => \un1_iu0_6[29]\, C => N481_0, - Y => ADD_33x33_fast_I260_Y_0_0); - - \r.d.inst_0_RNI66J4_1[23]\ : NOR3A - port map(A => \inst_0_0[23]\, B => \inst_0_0[24]\, C => - \inst_0_0[22]\, Y => un19_inst); - - un23_ra_I_1 : AND2 - port map(A => \cwp_0[0]\, B => \inst_0[18]\, Y => - \DWACT_ADD_CI_0_TMP_1[0]\); - - \r.m.y_RNO_0[11]\ : AOI1B - port map(A => wy_1_0, B => \y[11]\, C => \y_m[11]\, Y => - \y_iv_1[11]\); - - \r.e.op2_RNIAK9P[2]\ : OR2A - port map(A => \un1_iu0_5[68]\, B => \un1_iu0_6[2]\, Y => - \logicout_4[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I320_Y_0_1 : XOR2 - port map(A => \data_0_0[29]\, B => \un1_iu0_6[29]\, Y => - \un6_ex_add_res_s2_1[30]\); - - \r.e.aluop_2_RNIRI6R2[1]\ : MX2C - port map(A => N_3553, B => \logicout_3[26]\, S => - \aluop_2[1]\, Y => N_3585); - - un6_ex_add_res_d0_ADD_33x33_fast_I5_P0N : OR3A - port map(A => \data_0[4]\, B => \op1[4]\, C => ldbp1_0, Y - => N410_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I25_G0N : NOR2A - port map(A => \un1_iu0_6[24]\, B => \data_0[24]\, Y => - N469_1); - - \r.x.result_RNIUVKA[7]\ : MX2 - port map(A => \result_0[7]\, B => \data_0_2[7]\, S => ld_0, - Y => \un1_p0_6[359]\); - - \r.x.ctrl.rd_RNIA2NU[4]\ : MX2 - port map(A => \cwp[0]\, B => \rd_2[4]\, S => N_6357, Y => - waddr(4)); - - un6_ex_add_res_d1_ADD_33x33_fast_I322_Y_0 : AX1E - port map(A => I259_un1_Y, B => ADD_33x33_fast_I259_Y_3_1, C - => ADD_33x33_fast_I322_Y_0_0, Y => - \un6_ex_add_res_s1[32]\); - - \r.x.data_0_RNIBJ9E[21]\ : XNOR2 - port map(A => \data_0[21]\, B => invop2_1, Y => N_4268_i); - - \r.f.pc_RNO_0[19]\ : NAND2 - port map(A => \tmp[19]\, B => un2_rstn_5_0, Y => - \tmp_m[19]\); - - \r.e.op2[25]\ : DFN1E0 - port map(D => N_309, CLK => lclk_c, E => holdn, Q => - \op2[25]\); - - \r.a.ctrl.pc_RNIM3E2C[12]\ : MX2 - port map(A => \pc[12]\, B => N_3889, S => ex_bpmiss_1_0, Y - => \fe_pc[12]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I320_Y_0 : XOR2 - port map(A => N768, B => \un6_ex_add_res_s2_1[30]\, Y => - \un6_ex_add_res_s2[30]\); - - \r.a.ctrl.pc[5]\ : DFN1E0 - port map(D => \dpc[5]\, CLK => lclk_c, E => holdn, Q => - \pc_0[5]\); - - \r.w.s.icc_RNO_0[1]\ : AOI1B - port map(A => icc_2_sqmuxa, B => \result_0[21]\, C => - \icc_m_0[1]\, Y => \icc_1_iv_0[1]\); - - \r.e.op1_RNIALL2O3[13]\ : NOR3C - port map(A => \op1_m_0[13]\, B => \d_iv_2[13]\, C => - \aluresult_m_0[13]\, Y => \d_i[13]\); - - \r.e.op2_RNI4GMB1[31]\ : OR2A - port map(A => \un1_iu0_5[97]\, B => \un1_iu0_6[31]\, Y => - \logicout_4[31]\); - - \r.x.data_0_RNO_1[5]\ : NAND2 - port map(A => data_0_0_21, B => N_3455, Y => \dco_m_i[117]\); - - \r.e.op1_RNIMAEPF5[19]\ : NOR3C - port map(A => \op1_m_0[19]\, B => \d_iv_2[19]\, C => - \aluresult_m_0[19]\, Y => \d_i[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I183_Y : OR2A - port map(A => I183_un1_Y_i_0, B => N586_1, Y => N652_0); - - \r.a.rfa2_RNIDF461[3]\ : MX2 - port map(A => \inst_0_RNI3RUM[3]\, B => \rfa2[3]\, S => - holdn, Y => raddr2(3)); - - \un1_r.w.s.cwp_1_SUM2_0\ : AX1E - port map(A => ANC1, B => CO1_0, C => SUM2_0_0, Y => N_6529); - - \r.x.ctrl.inst_RNIQD1E[19]\ : NOR2A - port map(A => \inst_1[19]\, B => \inst[20]\, Y => y6_0_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I299_Y_0 : XNOR2 - port map(A => N817_i, B => ADD_33x33_fast_I299_Y_0_0, Y => - \un6_ex_add_res_s1[9]\); - - \r.e.op2_RNIIONB1_0[18]\ : OR2 - port map(A => \un1_iu0_6[18]\, B => \un1_iu0_5[84]\, Y => - \logicout_3[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I81_Y\ : OA1 - port map(A => \dpc[5]\, B => \inst_0_RNI3RUM[3]\, C => N365, - Y => N498_0); - - \r.a.rsel1_0_RNII7LJ2[2]\ : OR2B - port map(A => data1(28), B => d11_0, Y => \rfo_m[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I145_Y_0 : MAJ3 - port map(A => \op2[5]\, B => \un1_iu0_6[5]\, C => N409, Y - => ADD_33x33_fast_I145_Y_0); - - \r.e.ldbp2_2_RNIOL2G65\ : OR2A - port map(A => \eaddress[31]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[32]\); - - \r.m.y_RNO[5]\ : AO1C - port map(A => y14_0, B => \logicout[5]\, C => \y_iv_2[5]\, - Y => \y_0[5]\); - - \r.e.jmpl_RNIUUEBP_0\ : OR2B - port map(A => \shiftin_17[15]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[15]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I130_un1_Y\ : NOR2B - port map(A => N495_1, B => N492, Y => I130_un1_Y); - - \r.x.data_0_RNO_1[28]\ : NOR2A - port map(A => \data_0[28]\, B => ld_3, Y => \data_0_m[28]\); - - \r.e.op2_RNO_2[20]\ : AOI1B - port map(A => data2(20), B => d25_0, C => \d_1_iv_2[20]\, Y - => \d_1_iv_3[20]\); - - \r.a.imm[3]\ : DFN1E0 - port map(D => \un3_de_ren1[121]\, CLK => lclk_c, E => holdn, - Q => \imm[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I43_Y\ : NOR2B - port map(A => N425, B => N422, Y => N460_0); - - \r.x.ctrl.inst_RNIHVSN2[30]\ : OR2 - port map(A => cwp_1_sqmuxa_0, B => holdn, Y => N_6699); - - \r.d.cwp_RNO_0[2]\ : MX2 - port map(A => \ncwp[2]\, B => N_4220, S => un1_wcwp, Y => - N_4229); - - un6_ex_add_res_d1_ADD_33x33_fast_I183_un1_Y : OR3C - port map(A => N521_1, B => N525, C => N594_1, Y => - I183_un1_Y_i_0); - - \r.e.ctrl.inst_RNIVC1S[20]\ : NOR2 - port map(A => aluresult_13_sqmuxa_3, B => - aluresult_11_sqmuxa_4, Y => aluresult_11_sqmuxa_6); - - un6_ex_add_res_d2_ADD_33x33_fast_I269_Y : NAND2 - port map(A => I269_un1_Y, B => ADD_33x33_fast_I269_Y_0_0, Y - => N784_0); - - \r.m.ctrl.pc_RNI4MF8[3]\ : MX2 - port map(A => \pc_3[3]\, B => \pc[3]\, S => \npc[1]\, Y => - N_3244); - - \r.f.branch_RNIMJA92\ : XOR2 - port map(A => branch_0, B => \fbranch\, Y => - branch_RNIMJA92); - - \r.e.op1_RNIFHQEF[27]\ : NOR2B - port map(A => \edata2_iv_2[27]\, B => \edata2_iv_1[27]\, Y - => edata2_iv_i_0(27)); - - \r.e.aluop_RNI2TEB4[1]\ : OR2A - port map(A => aluresult_6_sqmuxa, B => \bpdata[28]\, Y => - \aluop_RNI2TEB4[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I206_Y_0_a3 : NOR2B - port map(A => N614_1, B => N407_2, Y => - ADD_33x33_fast_I206_Y_0_a3); - - \r.e.shleft_1_RNI5FBG\ : NOR2A - port map(A => \un1_iu0_6[4]\, B => shleft_1, Y => - shleft_1_RNI5FBG); - - \r.e.op1_RNIMM8G[11]\ : OR2B - port map(A => \op1[11]\, B => un14_casaen_s1_0, Y => - \op1_m_0[11]\); - - \r.e.aluop_RNIMPHR1[2]\ : OR2 - port map(A => aluresult_6_sqmuxa, B => aluresult_5_sqmuxa, - Y => N_3974); - - \r.m.y_RNO[1]\ : OR3C - port map(A => \y_iv_0_1[1]\, B => \y_iv_0_0[1]\, C => N_377, - Y => \y_1[1]\); - - \r.d.inst_0_RNI2SEN2[13]\ : NOR2A - port map(A => ldcheck2, B => imm, Y => rfe_0); - - \r.a.ctrl.inst_RNISU854[20]\ : AOI1B - port map(A => illegal_inst_1_sqmuxa_i_2, B => N_434, C => - \cpi_m_i[133]\, Y => illegal_inst_7_iv_0); - - \r.e.ldbp2_RNIC2ODE2\ : OR2A - port map(A => annul_RNI5L7FE1, B => \eaddress[11]\, Y => - N_9); - - \r.x.data_0_RNO[14]\ : OR3 - port map(A => \dco_m_0[110]\, B => \data_0_1_0_iv_0[14]\, C - => \data_0_1_4[9]\, Y => \data_0_1[14]\); - - \r.e.op2_RNO_1[12]\ : OR2B - port map(A => \op1[12]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[12]\); - - \r.e.aluop_0_RNIULOS3[0]\ : OR2B - port map(A => \logicout[8]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[8]\); - - \r.w.s.y_RNO[2]\ : MX2 - port map(A => \y_2[2]\, B => \result_0[2]\, S => N_481_0, Y - => N_3766); - - \r.e.op1_RNO[3]\ : MX2 - port map(A => \d[3]\, B => \d[4]\, S => N_227_0, Y => - \aop1[3]\); - - \r.d.inst_0_RNI62J4[21]\ : OR3C - port map(A => \inst_0[19]\, B => \inst_0_0[21]\, C => - \inst_0_0[22]\, Y => un12_op3); - - \r.e.op2_RNIF4U51_0[23]\ : NOR2 - port map(A => \un1_iu0_6[23]\, B => \un1_iu0_5[89]\, Y => - \logicout_3[23]\); - - \r.e.op2_RNO[10]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[10]\, Y => N_294); - - un6_ex_add_res_d0_ADD_33x33_fast_I63_Y_0 : AO1 - port map(A => N443_0, B => N439_0, C => N442, Y => N522_0); - - \r.d.inst_0_RNI42J4[21]\ : OR2A - port map(A => N_67, B => \inst_0_0[21]\, Y => un4_op3); - - un6_ex_add_res_d2_ADD_33x33_fast_I30_G0N : NOR2B - port map(A => \data_0_0[29]\, B => \un1_iu0_6[29]\, Y => - N484); - - \r.e.op1[8]\ : DFN1E0 - port map(D => \aop1[8]\, CLK => lclk_c, E => holdn, Q => - \op1[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I121_Y_0 : MIN3 - port map(A => \op2[17]\, B => \un1_iu0_6[17]\, C => N445_1, - Y => ADD_33x33_fast_I121_Y_0_1); - - \r.x.data_0_RNO_1[15]\ : OR2 - port map(A => \dco_m_0[127]\, B => \data_0_m[15]\, Y => - \data_0_1_0_iv_0[15]\); - - \r.e.op1_RNI2TNO6[24]\ : NOR3C - port map(A => \ex_op1_i_m[24]\, B => \op1_RNI1JNF[24]\, C - => \bpdata_i_m[24]\, Y => \edata2_iv_1[24]\); - - \r.w.result_RNIO6PF[13]\ : AOI1B - port map(A => \un1_p0_6[365]\, B => d14, C => - \result_m_0_0[13]\, Y => \d_iv_0[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I189_Y : AO1 - port map(A => N600_1, B => N593_0, C => N592_0, Y => N658_0); - - \r.x.data_0_RNO[18]\ : OR3 - port map(A => \dco_m_0[114]\, B => \data_0_m[18]\, C => - \data_0_1_4[18]\, Y => \data_0_1[18]\); - - \r.d.inst_0_RNIFK901[17]\ : MX2C - port map(A => \de_raddr1_2[5]\, B => \de_raddr1_1[5]\, S - => rs1mod, Y => \un3_de_ren1[96]\); - - \r.m.result_RNO[8]\ : MX2 - port map(A => \aluresult[8]\, B => \op1[8]\, S => - un17_casaen_0_1, Y => \eres2[8]\); - - \r.d.inst_0[10]\ : DFN1 - port map(D => \inst_0_RNO[10]\, CLK => lclk_c, Q => - \inst_0[10]\); - - \comb.lock_gen.icc_check5_0_a3\ : NAND2 - port map(A => N_145, B => ticc_exception_1, Y => icc_check5); - - un6_ex_add_res_d0_ADD_33x33_fast_I23_P0N : OR3A - port map(A => \data_0_0[22]\, B => \op1[22]\, C => ldbp1_4, - Y => N464_2); - - \r.m.icc_RNO_7[2]\ : NOR3C - port map(A => icc_0_sqmuxa_1_18, B => icc_0_sqmuxa_1_17, C - => icc_0_sqmuxa_1_26, Y => icc_0_sqmuxa_1_29); - - \r.e.shleft_RNIFMRJ\ : OR2A - port map(A => \un1_iu0_6[25]\, B => shleft, Y => - \shiftin_5[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I92_un1_Y\ : OAI1 - port map(A => N427, B => ADD_30x30_fast_I40_Y_0_a3, C => - N454, Y => I92_un1_Y); - - \r.a.nobp_RNO_1\ : AO1C - port map(A => \inst_0[31]\, B => un19_inst, C => N_85, Y - => N_16827_tz); - - un6_ex_add_res_d1_ADD_33x33_fast_I261_Y : NAND2 - port map(A => I261_un1_Y_0, B => ADD_33x33_fast_I261_Y_2_0, - Y => N768_1); - - \r.x.result_RNIRV6B[9]\ : OR2B - port map(A => \un1_p0_6[361]\, B => d14, Y => - \cpi_m_0[361]\); - - \r.e.aluop_0_RNIBL5R[1]\ : XOR3 - port map(A => \un1_iu0_6[3]\, B => \aluop_0[1]\, C => - \un1_iu0_5[69]\, Y => N_6829); - - \r.a.rsel1_0_RNIB7LJ2[2]\ : OR2B - port map(A => data1(21), B => d11_0, Y => \rfo_m[21]\); - - \r.a.ctrl.wicc\ : DFN1E0 - port map(D => wicc_1, CLK => lclk_c, E => holdn, Q => - wicc_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_un1_Y_0 : NOR2B - port map(A => N637_0, B => N653_1, Y => - ADD_33x33_fast_I265_un1_Y_0_0); - - \r.m.y_RNICRD92[18]\ : NOR2B - port map(A => \y_m_1[18]\, B => \cpi_m[163]\, Y => - \aluresult_1_iv_1[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I263_un1_Y : NOR3C - port map(A => N649, B => N633_0, C => N808, Y => - I263_un1_Y_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I159_un1_Y : OR3A - port map(A => N570_0, B => N497_2, C => N501, Y => - I159_un1_Y); - - \r.f.pc_RNO_5[18]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[18]\, Y => \xc_trap_address_m[18]\); - - \r.a.rfa1_RNINNUA1[0]\ : MX2 - port map(A => \rs1_iv_i_0[0]\, B => \rfa1[0]\, S => holdn, - Y => raddr1(0)); - - \r.x.ctrl.pc_RNIBIGF[31]\ : MX2 - port map(A => \pc_2[31]\, B => \pc[31]\, S => \npc_1[1]\, Y - => N_3242); - - \r.e.aluop_RNIUF511[2]\ : XA1 - port map(A => \un1_iu0_5[68]\, B => \aluop_1[2]\, C => - \un1_iu0_6[2]\, Y => N_3529); - - \r.a.ctrl.rd_RNIGC1L[3]\ : XNOR2 - port map(A => \rd_1[3]\, B => \un3_de_ren1[94]\, Y => - un2_rs1_3_i); - - \r.m.y_RNO_1[30]\ : OR2B - port map(A => \y[31]\, B => mulstep_0, Y => \y_m_1[31]\); - - \r.e.op1_RNIR8E64[4]\ : AOI1B - port map(A => \op1[4]\, B => un14_casaen_s1_0_1, C => - \d_1_iv_3[4]\, Y => \d_1_iv_4[4]\); - - \r.d.pc_RNIUTGB4[17]\ : MX2 - port map(A => \dpc[17]\, B => \fpc[17]\, S => - \ra_bpmiss_1_0\, Y => N_3894); - - un6_ex_add_res_d2_ADD_33x33_fast_I5_G0N : OA1 - port map(A => \op1[4]\, B => ldbp1_1, C => \data_0[4]\, Y - => N409_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I315_Y_0 : XNOR2 - port map(A => N778_0, B => \un6_ex_add_res_s2_1[25]\, Y => - \un6_ex_add_res_s0[25]\); - - \r.x.result_RNII62O3[31]\ : MX2C - port map(A => \un1_iu0_6[31]\, B => \un1_p0_6[383]\, S => - bpdata6_0_0, Y => \bpdata[31]\); - - \r.f.pc_RNI04KTU4[9]\ : NOR2B - port map(A => \un6_fe_npc_m[7]\, B => - \xc_trap_address_m[9]\, Y => \npc_iv_2[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I299_Y_0 : XOR2 - port map(A => N817_0, B => \un6_ex_add_res_s2_1[9]\, Y => - \un6_ex_add_res_s2[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I200_Y : NOR3C - port map(A => N545_1, B => N549_0, C => N603, Y => N669); - - \r.x.result_RNI3L6E[28]\ : MX2 - port map(A => \result_0[28]\, B => \data_0[28]\, S => ld_4, - Y => \un1_p0_6[380]\); - - \r.x.ctrl.pc[24]\ : DFN1E0 - port map(D => \pc_2[24]\, CLK => lclk_c, E => holdn, Q => - \pc_0[24]\); - - \r.e.op1_RNO[13]\ : MX2C - port map(A => \d_i[13]\, B => \d_i[14]\, S => N_227, Y => - \aop1[13]\); - - \r.x.laddr_RNIF5HB51[1]\ : OR3B - port map(A => rdata200, B => ld_0_0, C => \me_laddr_2[1]\, - Y => rdata_5_sqmuxa); - - un6_ex_add_res_d2_ADD_33x33_fast_I317_Y_0_1 : XOR2 - port map(A => \data_0[26]\, B => \un1_iu0_6[26]\, Y => - \un6_ex_add_res_s2_1[27]\); - - \r.e.shleft_RNI9KCC2\ : MX2B - port map(A => \shiftin_5[43]\, B => \shiftin_5[27]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[27]\); - - \r.x.rstate_RNI64FC2[0]\ : MX2C - port map(A => N_3410, B => \xc_result[19]\, S => - \rstate[0]\, Y => \wdata[19]\); - - \r.d.pc_RNO[4]\ : MX2 - port map(A => \fpc[4]\, B => \dpc[4]\, S => N_6763_i, Y => - \pc_RNO[4]\); - - \r.x.npc_RNIAT411[0]\ : MX2C - port map(A => N_3240, B => N_3270, S => \npc[0]\, Y => - \xc_result[29]\); - - \r.e.op1_RNI9HUH[24]\ : MX2 - port map(A => \op1[24]\, B => \data_0[24]\, S => ldbp1_4, Y - => \un1_iu0_6[24]\); - - \r.e.ctrl.tt_RNO_0[1]\ : OA1B - port map(A => ticc, B => wunf, C => wovf, Y => N_16735_tz); - - \r.e.op2_RNI9S3F[0]\ : OR2A - port map(A => \op2_RNI59C6[0]\, B => \un1_iu0_6[0]\, Y => - \logicout_4[0]\); - - \r.e.op2_RNO_0[31]\ : OR3C - port map(A => \op1_m_i[31]\, B => \d_1_iv_3[31]\, C => - \aluresult_m_i[31]\, Y => \d_1[31]\); - - \r.x.data_0_RNO[3]\ : AO1B - port map(A => N_3456, B => N_3387_i_0, C => - \data_0_1_1_iv_2[3]\, Y => \data_0_1[3]\); - - \r.e.op2_RNIF4U51[23]\ : NOR2A - port map(A => \un1_iu0_5[89]\, B => \un1_iu0_6[23]\, Y => - \logicout_4[23]\); - - \r.e.ctrl.pc_RNIF1L11[29]\ : OR2B - port map(A => \pc_0[29]\, B => jmpl_0, Y => \cpi_m[174]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I39_Y_0_a3 : NOR3C - port map(A => \op2[26]\, B => \un1_iu0_6[26]\, C => N479_2, - Y => ADD_33x33_fast_I39_Y_0_a3); - - un6_ex_add_res_d0_ADD_33x33_fast_I265_Y : NAND2 - port map(A => I265_un1_Y_i_1, B => - ADD_33x33_fast_I265_Y_1_1, Y => N776_0); - - un6_fe_npc_I_5 : XOR2 - port map(A => \fe_pc[2]\, B => \fe_pc[3]\, Y => I_5); - - un6_ex_add_res_d0_ADD_33x33_fast_I145_Y_0 : AO13 - port map(A => N409_0, B => \un1_iu0_6[5]\, C => \data_0[5]\, - Y => ADD_33x33_fast_I145_Y_0_0); - - \r.e.ldbp2_RNIEEFAF1\ : OR2 - port map(A => un12_ex_add_res, B => \eaddress[13]\, Y => - un1_addout_12_0); - - \r.e.invop2_RNIR5ON11\ : MX2C - port map(A => \un6_ex_add_res_s2[16]\, B => - \un6_ex_add_res_s0[16]\, S => invop2, Y => N_6635); - - un6_ex_add_res_d0_ADD_33x33_fast_I262_Y_0_a3 : OAI1 - port map(A => N506_0, B => N_74, C => - ADD_33x33_fast_I262_Y_0_a3_0, Y => N_51_i_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I112_Y : NOR2B - port map(A => N513_2, B => N509_0, Y => N575_2); - - \r.e.ctrl.pc[2]\ : DFN1E0 - port map(D => \pc[2]\, CLK => lclk_c, E => holdn, Q => - \pc_2[2]\); - - \r.e.ctrl.pc[24]\ : DFN1E0 - port map(D => \pc_3[24]\, CLK => lclk_c, E => holdn, Q => - \pc[24]\); - - \r.a.ctrl.rd_RNI97P71[6]\ : XNOR2 - port map(A => \rd[6]\, B => \un3_de_ren1[97]\, Y => - un2_rs1_6_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I321_Y_0_0 : XOR2 - port map(A => \op2[30]\, B => \un1_iu0_6[30]\, Y => - ADD_33x33_fast_I321_Y_0_0); - - \r.m.ctrl.annul_RNIPFOQ\ : AO1B - port map(A => annul_1tt_N_7, B => annul_1tt_N_5, C => rst, - Y => annul_RNIPFOQ); - - \r.e.op2_RNO_5[17]\ : AOI1B - port map(A => \result[17]\, B => d31_0, C => \imm_m_i[17]\, - Y => \d_1_iv_0[17]\); - - \r.e.jmpl_RNIR18H6\ : OR2 - port map(A => aluresult_0_sqmuxa, B => \eaddress[2]\, Y => - jmpl_RNIR18H6); - - \r.e.aluop_1_RNIKB2T2[1]\ : MX2C - port map(A => \logicout_4[26]\, B => N_6859, S => - N_6866_i_0, Y => N_3649); - - \r.m.result_0_RNIQ9USD[3]\ : AO1D - port map(A => trap_1_sqmuxa, B => trap_0_sqmuxa_6, C => - annul_3, Y => un1_trap_0_sqmuxa_5); - - \r.w.s.icc_RNO_0[2]\ : AOI1B - port map(A => icc_2_sqmuxa, B => \result_0[22]\, C => - \icc_m_0[2]\, Y => \icc_1_iv_0[2]\); - - \r.x.dci.size_RNIQ1HOI[0]\ : NOR2 - port map(A => \me_size_1[1]\, B => \me_size_1[0]\, Y => - rdata200); - - \r.x.dci.size[1]\ : DFN1E0 - port map(D => \size_0[1]\, CLK => lclk_c, E => holdn, Q => - \size_2[1]\); - - \r.m.y_RNO_1[11]\ : AOI1B - port map(A => \y_0[11]\, B => y08_0, C => \y_m[12]\, Y => - \y_iv_0[11]\); - - \r.e.op2_RNII0OB1_0[19]\ : OR2 - port map(A => \op1_RNID1VH[19]\, B => \un1_iu0_5[85]\, Y - => \logicout_3[19]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I292_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[2]\, B => N552, Y => - \un6_ex_add_res_s0[2]\); - - \r.e.op2_RNO_8[11]\ : OR3B - port map(A => d29_0_0, B => \imm[11]\, C => \rsel2_1[0]\, Y - => \imm_m_i[11]\); - - \r.f.pc_RNO_2[14]\ : NAND2 - port map(A => \tmp[14]\, B => un2_rstn_5_0, Y => N_6619); - - \r.e.op1_RNO[21]\ : MX2C - port map(A => \d_i[21]\, B => \d_i[22]\, S => N_227_0, Y - => \aop1[21]\); - - \r.x.data_0[18]\ : DFN1E0 - port map(D => \data_0_1[18]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_0[18]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I138_Y_0 : OA1A - port map(A => \data_0[6]\, B => \un1_iu0_6[6]\, C => N419, - Y => ADD_33x33_fast_I138_Y_0); - - \r.w.s.icc_RNO_1[0]\ : OR2B - port map(A => icc_0_sqmuxa, B => \icc_2[0]\, Y => - \icc_m_0[0]\); - - \r.e.cwp[1]\ : DFN1E0 - port map(D => \cwp_3[1]\, CLK => lclk_c, E => holdn, Q => - \cwp_2[1]\); - - \r.e.aluop_0_RNIHK9O1[1]\ : MX2C - port map(A => \logicout_4[8]\, B => N_6868, S => N_6866_i_0, - Y => N_3631); - - \r.d.inst_0_RNO_0[5]\ : MX2 - port map(A => data_0_0_5, B => \inst_0[5]\, S => - mexc_1_sqmuxa_1_0, Y => N_4605); - - \r.d.inst_0_RNIBO79[24]\ : MX2C - port map(A => \un1_p0_6_0[60]\, B => \inst_0_0[24]\, S => - \inst_0[30]\, Y => \inst_0_1[26]\); - - \r.f.pc_RNO_1[22]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[22]\, C => - \pc_1_iv_0[22]\, Y => \pc_1_iv_1[22]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I276_Y_0_0\ : XOR2 - port map(A => \dpc[18]\, B => \inst_0[16]\, Y => - ADD_30x30_fast_I276_Y_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I7_G0N : OA1 - port map(A => \op1[6]\, B => ldbp1_1, C => \data_0[6]\, Y - => N415_2); - - \r.e.shcnt_RNIV5R9D[2]\ : MX2C - port map(A => \shiftin_11[29]\, B => \shiftin_11[25]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[25]\); - - \r.e.shcnt_RNIP4QF5[3]\ : MX2 - port map(A => \shiftin_8[23]\, B => \shiftin_8[15]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[15]\); - - \r.d.pc[27]\ : DFN1 - port map(D => \pc_RNO[27]\, CLK => lclk_c, Q => \dpc[27]\); - - \r.x.ctrl.rd_RNIGU7Q[3]\ : NOR3C - port map(A => rd_4_i_0, B => rd_3_i_0, C => bpdata6_4, Y - => bpdata6_7); - - \r.e.ldbp2_1_RNIB95RE4\ : MX2C - port map(A => \un6_ex_add_res_s1_i[27]\, B => N_6658, S => - ldbp2_1, Y => \eaddress[26]\); - - \r.d.inst_0_RNIF6J4[25]\ : NOR2 - port map(A => \inst_0[25]\, B => N_122_2, Y => tmp); - - \r.x.result_RNIL62O3[24]\ : MX2C - port map(A => \un1_iu0_6[24]\, B => \un1_p0_6[376]\, S => - bpdata6_0_0, Y => \bpdata[24]\); - - \r.e.ctrl.inst[22]\ : DFN1E0 - port map(D => \inst[22]\, CLK => lclk_c, E => holdn, Q => - \inst_1[22]\); - - \r.w.s.tba_RNIUK1K4[11]\ : AOI1B - port map(A => \tba[11]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_2[23]\, Y => \aluresult_1_iv_4[23]\); - - \r.a.ctrl.inst_RNIFRN9A[20]\ : OR3B - port map(A => aluop_2_1_0_1, B => aluop_2_1_0_2, C => N_230, - Y => \aluop[2]\); - - \r.w.s.y[15]\ : DFN1E0 - port map(D => N_3779, CLK => lclk_c, E => N_6922_i_0, Q => - \y_2[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I182_Y : NOR2B - port map(A => N593_0, B => N585_0, Y => N651_1); - - \r.e.ctrl.pc_RNI6TJ11[20]\ : OR2B - port map(A => \pc_0[20]\, B => jmpl_0, Y => \cpi_m[165]\); - - \r.a.ctrl.pc_RNI65FI82[2]\ : OR2A - port map(A => un2_rstn_4_0_0, B => \fe_pc[2]\, Y => - \un6_fe_npc_m[0]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I1_G0N\ : NOR2B - port map(A => \inst_0_RNI1JUM[1]\, B => \dpc[3]\, Y => N361); - - \r.a.imm[17]\ : DFN1E0 - port map(D => \un3_de_ren1[135]\, CLK => lclk_c, E => holdn, - Q => \imm[17]\); - - \r.x.result_RNINBRV[1]\ : NOR2B - port map(A => \un1_p0_6[353]\, B => N_6357, Y => \wdata[1]\); - - \r.d.inst_0_RNI6AJ4[25]\ : MX2 - port map(A => \inst_0_0[21]\, B => \inst_0[25]\, S => - \inst_0[30]\, Y => \inst_0_1[27]\); - - \r.w.s.dwt_RNO_0\ : MX2C - port map(A => dwt, B => \result_0[14]\, S => dwt_1_sqmuxa, - Y => N_318); - - \r.m.casa_RNI8BU9\ : NOR2A - port map(A => casa, B => N_3355_1, Y => \un17_casaen_0_0\); - - \r.d.inst_0_RNO_0[27]\ : MX2 - port map(A => data_0_2_27, B => \inst_0[27]\, S => - inull_RNIFV6VG2_0, Y => N_4627); - - \r.e.op2_RNO_6[12]\ : OR3B - port map(A => d29_0_0, B => \imm[12]\, C => \rsel2_1[0]\, Y - => \imm_m_i[12]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I115_Y : AO1A - port map(A => N516_1, B => N513_2, C => N512_1, Y => N578_0); - - \r.x.result_RNIJ5SBB[1]\ : MX2C - port map(A => \result_0[1]\, B => N_6528, S => - cwp_1_sqmuxa_0, Y => N_3871); - - \r.f.pc_RNIAIBJB2[3]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[3]\, Y => - \pc_4_m[3]\); - - \r.x.rstate_RNIDJJ62[0]\ : MX2C - port map(A => N_3418, B => \xc_result[27]\, S => - \rstate[0]\, Y => \wdata[27]\); - - \r.e.aluop_RNIQDMD8[2]\ : NOR2A - port map(A => \aluop_RNI6QSC4[2]\, B => \bpdata_i_m_2[0]\, - Y => \edata2_iv_2[24]\); - - \r.x.data_0[5]\ : DFN1E0 - port map(D => \data_0_1[5]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[5]\); - - \r.x.ctrl.pc[23]\ : DFN1E0 - port map(D => \pc_2[23]\, CLK => lclk_c, E => holdn, Q => - \pc[23]\); - - \r.e.op1_RNI0HHD[30]\ : MX2 - port map(A => \op1[30]\, B => \data_0[30]\, S => ldbp1, Y - => \un1_iu0_6[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I8_P0N : OR3A - port map(A => \data_0_2[7]\, B => \op1[7]\, C => ldbp1_2, Y - => N419); - - \r.f.pc_RNO_7[15]\ : MX2 - port map(A => \fpc[15]\, B => \tba[3]\, S => - rstate_6314_d_0, Y => \xc_trap_address[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I303_Y_0 : AX1D - port map(A => N430_0, B => ADD_33x33_fast_I246_Y_0_a3, C - => \un6_ex_add_res_s0_1[13]\, Y => - \un6_ex_add_res_s0[13]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I234_Y_0\ : AOI1 - port map(A => N455, B => N452, C => N451, Y => - ADD_30x30_fast_I234_Y_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I29_P0N : OR2 - port map(A => \un1_iu0_6[28]\, B => \data_0[28]\, Y => N482); - - \r.e.shcnt_RNI490TB[2]\ : MX2C - port map(A => \shiftin_11[21]\, B => \shiftin_11[17]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[17]\); - - \r.e.op2_RNIKONB1_0[27]\ : OR2 - port map(A => \un1_iu0_6[27]\, B => \un1_iu0_5[93]\, Y => - \logicout_3[27]\); - - \r.e.ctrl.tt[2]\ : DFN1E0 - port map(D => \tt_1[2]\, CLK => lclk_c, E => holdn, Q => - \tt_3[2]\); - - \r.e.shcnt_RNI36MUA[2]\ : MX2C - port map(A => \shiftin_11[17]\, B => \shiftin_11[13]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[13]\); - - \r.a.imm_RNO[30]\ : MX2 - port map(A => \inst_0[20]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[148]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I317_Y_0_0 : XOR2 - port map(A => \op2[26]\, B => \un1_iu0_6[26]\, Y => - ADD_33x33_fast_I317_Y_0_0); - - \r.e.ctrl.wreg_RNO\ : NOR3B - port map(A => ra_bpannul_1, B => wreg_0, C => \un1_p0_6[0]\, - Y => wreg_1_10); - - \r.m.icc_RNO_13[2]\ : NOR3B - port map(A => icc_0_sqmuxa_1_0, B => icc_0_sqmuxa_1_12, C - => \logicout[30]\, Y => icc_0_sqmuxa_1_22); - - \r.e.ctrl.inst_RNIKC1E_0[20]\ : OR2 - port map(A => \inst_1[20]\, B => \inst[19]\, Y => N_3749_1); - - \r.x.ctrl.pc_RNI29R31[2]\ : MX2C - port map(A => \un1_p0_6[354]\, B => \pc_0[2]\, S => - s_3_sqmuxa_0, Y => N_3393); - - un6_ex_add_res_d0_ADD_33x33_fast_I195_Y : AO1A - port map(A => N599_0, B => N606_0, C => N598_0, Y => N664_0); - - \r.x.ctrl.ld_0_RNIH0TN2\ : NOR3C - port map(A => bpdata6_8, B => bpdata6_7, C => bpdata6_9, Y - => bpdata6_0_0); - - \r.d.inull_RNIFV6VG2\ : OA1B - port map(A => holdn, B => de_hold_pc_1_0, C => mds, Y => - mexc_1_sqmuxa_1_0); - - \r.e.op1_RNI6C9M3[29]\ : NOR3C - port map(A => \rfo_m[29]\, B => \d_iv_1[29]\, C => - \op1_m_0[29]\, Y => \d_iv_3[29]\); - - \r.a.ctrl.ld_RNI99DC\ : AND2 - port map(A => wreg_0, B => ld_1, Y => ldlock2_0); - - \r.f.pc_RNI3830J[6]\ : MX2B - port map(A => \fpc[6]\, B => \eaddress[6]\, S => jump, Y - => N_4049); - - \r.a.ctrl.inst_RNIBO0L[31]\ : NOR3A - port map(A => \inst[22]\, B => \inst[30]\, C => \inst[31]\, - Y => cp_disabled_2_sqmuxa_0); - - \r.a.ctrl.inst_RNI5H3O1_0[23]\ : OR3 - port map(A => N_202, B => illegal_inst37_4, C => N_212, Y - => cp_disabled_6_sqmuxa); - - \r.e.op1_RNI11UH[20]\ : MX2 - port map(A => \op1[20]\, B => \data_0_2[20]\, S => ldbp1_4, - Y => \un1_iu0_6[20]\); - - \r.e.op2_RNO_5[24]\ : AOI1B - port map(A => \result[24]\, B => d31_0, C => \imm_m_i[24]\, - Y => \d_1_iv_0[24]\); - - \r.e.op2[2]\ : DFN1E0 - port map(D => N_286, CLK => lclk_c, E => holdn, Q => - \op2[2]\); - - \r.e.ctrl.pc[23]\ : DFN1E0 - port map(D => \pc_3[23]\, CLK => lclk_c, E => holdn, Q => - \pc_0[23]\); - - \r.m.result[13]\ : DFN1E0 - port map(D => \eres2[13]\, CLK => lclk_c, E => holdn, Q => - \maddress[13]\); - - \r.w.s.pil_RNI05PJ3[2]\ : OA1A - port map(A => \pil[2]\, B => aluresult_11_sqmuxa, C => - \aluresult_1_iv_0[10]\, Y => \aluresult_1_iv_2[10]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I90_Y : NOR2B - port map(A => N404_1, B => N401_0, Y => N549); - - \r.f.pc_RNO_5[22]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[22]\, Y => \xc_trap_address_m[22]\); - - \r.f.pc[19]\ : DFN1E0 - port map(D => \pc_1[19]\, CLK => lclk_c, E => holdn, Q => - \fpc[19]\); - - \r.x.ctrl.pc[10]\ : DFN1E0 - port map(D => \pc_2[10]\, CLK => lclk_c, E => holdn, Q => - \pc[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I20_P0N\ : OR2 - port map(A => \inst_0[20]\, B => \dpc[22]\, Y => N419_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I262_Y_0_0\ : XOR2 - port map(A => \dpc[4]\, B => \inst_0_RNI2NUM[2]\, Y => - ADD_30x30_fast_I262_Y_0_0); - - \r.x.data_0_RNI7VS8[6]\ : XOR2 - port map(A => \data_0[6]\, B => invop2_0, Y => N_4253); - - \r.a.wunf\ : DFN1E0 - port map(D => \wovf_exc_1_sqmuxa\, CLK => lclk_c, E => - holdn, Q => wunf); - - un6_ex_add_res_d1_ADD_33x33_fast_I303_Y_0 : AX1B - port map(A => N430, B => ADD_33x33_fast_I246_Y_0_a3_0, C - => ADD_33x33_fast_I303_Y_0_0, Y => - \un6_ex_add_res_s1_i[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I140_Y : OR2B - port map(A => N541_1, B => N537_1, Y => N603_0); - - \r.x.ctrl.rd_RNI5G6A1[1]\ : NOR3B - port map(A => bpdata6_2, B => bpdata6_1, C => N_3356_3, Y - => bpdata6_9); - - \r.m.ctrl.inst[19]\ : DFN1E0 - port map(D => \inst[19]\, CLK => lclk_c, E => holdn, Q => - \inst_3[19]\); - - \r.e.jmpl_RNILTD2M\ : OR2B - port map(A => \shiftin_17[6]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[6]\); - - \r.e.op1_RNO[28]\ : MX2C - port map(A => \d_i[28]\, B => \d_i[29]\, S => N_227, Y => - \aop1[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I82_Y : AND2 - port map(A => N413, B => N416, Y => N541); - - \r.x.laddr_RNI45NB9[1]\ : MX2 - port map(A => \maddress[1]\, B => \laddr[1]\, S => - dco_i_2(132), Y => \me_laddr_2[1]\); - - \r.m.icc[3]\ : DFN1E0 - port map(D => \icco[3]\, CLK => lclk_c, E => holdn, Q => - \icc[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I274_Y_0_a3 : NOR2B - port map(A => N796_0, B => N443_1, Y => - ADD_33x33_fast_I274_Y_0_a3); - - \r.m.y_RNO_0[19]\ : AOI1B - port map(A => wy_1_0, B => \y[19]\, C => \y_m[19]\, Y => - \y_iv_1[19]\); - - \r.e.ldbp2_2_RNI3L9F582\ : OR3B - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_24, B => - \un1_addout_12\, C => \eaddress[31]\, Y => un1_addout); - - \r.w.s.tba_RNI74CA1[6]\ : OR2B - port map(A => \tba[6]\, B => aluresult_12_sqmuxa, Y => - \tba_m[6]\); - - \r.w.result_RNIL8V6[0]\ : OR2B - port map(A => \result_0[0]\, B => d31, Y => \result_m_i[0]\); - - \r.e.aluop_2_RNIDPAI2[1]\ : MX2C - port map(A => N_3557, B => \logicout_3[30]\, S => - \aluop_2[1]\, Y => N_3589); - - un6_ex_add_res_d2_ADD_33x33_fast_I300_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[9]\, B => \data_0[9]\, Y => - \un6_ex_add_res_s2_1[10]\); - - \r.e.alusel_RNO_3[0]\ : OR3A - port map(A => \alusel_i_0_a5_0_0[0]\, B => N_487, C => - N_492, Y => N_352); - - \r.m.y_RNI9N6P6[21]\ : NOR3C - port map(A => \cpi_m[166]\, B => \y_m_1[21]\, C => - \bpdata_m[21]\, Y => \aluresult_1_iv_3[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I266_Y_0_a3 : NOR2A - port map(A => N782_1, B => N_15_0, Y => N_74); - - \r.m.ctrl.inst[26]\ : DFN1E0 - port map(D => \inst_1[26]\, CLK => lclk_c, E => holdn, Q - => \inst_3[26]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I184_Y : NOR2A - port map(A => N587_1, B => N595, Y => N653_1); - - \r.x.ctrl.inst[19]\ : DFN1E0 - port map(D => \inst_3[19]\, CLK => lclk_c, E => holdn, Q - => \inst_1[19]\); - - \r.m.y_RNO_0[3]\ : NOR3C - port map(A => \y_m[4]\, B => \y_m_0[3]\, C => \y_iv_1[3]\, - Y => \y_iv_2[3]\); - - \r.e.op1_RNIHHAT4[20]\ : AO1A - port map(A => \bpdata[20]\, B => edata_2_sqmuxa, C => - \op1_i_m[20]\, Y => \edata2_0_iv_0[20]\); - - \r.e.shcnt_RNIBG9HR[1]\ : MX2C - port map(A => \shiftin_14[25]\, B => \shiftin_14[23]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[23]\); - - \r.e.ctrl.pc_RNI61K11[11]\ : OR2B - port map(A => \pc_2[11]\, B => jmpl_4, Y => \cpi_m[156]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_2\ : OR2A - port map(A => irl_0(1), B => \pil[1]\, Y => \ACT_LT4_E[1]\); - - \r.m.result_RNIBVU53[10]\ : NOR3C - port map(A => \d_iv_0[10]\, B => \result_m_0[10]\, C => - \rfo_m[10]\, Y => \d_iv_2[10]\); - - \r.e.aluop_0_RNILC591[1]\ : XOR3 - port map(A => \un1_iu0_6[30]\, B => \aluop_0[1]\, C => - \un1_iu0_5[96]\, Y => N_6853); - - \comb.un6_xc_exception_RNIIV70L2\ : AOI1B - port map(A => I_5, B => un2_rstn_4_0_0, C => - \xc_trap_address_m[3]\, Y => \npc_iv_2[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I90_Y : NOR2B - port map(A => N404, B => N401_1, Y => N549_1); - - \r.e.ctrl.inst_RNII01E[24]\ : OR2B - port map(A => \inst_1[22]\, B => \inst[24]\, Y => - aluresult_13_sqmuxa_3); - - \r.d.annul_RNIBH7NS4\ : OR2B - port map(A => I_38, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[7]\); - - \r.m.ctrl.rd[7]\ : DFN1E0 - port map(D => \rd_1[7]\, CLK => lclk_c, E => holdn, Q => - \rd_0[7]\); - - \r.a.rsel2_0_RNIUSKM[0]\ : NOR2B - port map(A => \result_m_i[1]\, B => \cpi_m_i[353]\, Y => - \d_1_iv_1[1]\); - - un2_rstn_5_RNI5B15D2 : NOR2B - port map(A => \tmp_m[3]\, B => \pc_4_m[3]\, Y => - \npc_iv_0[3]\); - - \r.m.y_RNO_0[7]\ : NOR3C - port map(A => \y_m_0[8]\, B => \y_m_0[7]\, C => \y_iv_1[7]\, - Y => \y_iv_2[7]\); - - \r.f.pc_RNO_2[27]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[27]\, C => - \xc_trap_address_m[27]\, Y => \pc_1_iv_0[27]\); - - \r.d.inst_0_RNIV323[21]\ : NOR2B - port map(A => \inst_0_0[21]\, B => \inst_0[20]\, Y => - un14_op_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I164_Y : NOR2B - port map(A => N575_2, B => N567_0, Y => N633_0); - - \r.e.op1_RNIV6NF[31]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[31]\, Y => - \op1_i_m[31]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_8\ : NOR2A - port map(A => \pil[2]\, B => irl_0(2), Y => \ACT_LT4_E[7]\); - - \r.e.shcnt_RNI8LT6T[1]\ : MX2C - port map(A => \shiftin_14[29]\, B => \shiftin_14[27]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[27]\); - - \r.x.ctrl.ld_0\ : DFN1E0 - port map(D => ld, CLK => lclk_c, E => holdn, Q => ld_0); - - \r.m.y_RNO_0[20]\ : AOI1B - port map(A => wy_1_0, B => \y[20]\, C => \y_m[20]\, Y => - \y_iv_1[20]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I310_Y_0_0 : XOR2 - port map(A => \op2[19]\, B => \op1_RNID1VH[19]\, Y => - ADD_33x33_fast_I310_Y_0_0); - - \r.e.shcnt_RNI0V6M[3]\ : MX2C - port map(A => \shcnt[3]\, B => N_3307, S => ldbp2_0, Y => - \ex_shcnt_1_i_0[3]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I13_G0N\ : NOR2B - port map(A => \inst_0[13]\, B => \dpc[15]\, Y => N397_2); - - \r.a.ctrl.inst_RNID81L[22]\ : NOR2B - port map(A => \inst[22]\, B => alusel24_2, Y => - illegal_inst_1_sqmuxa_i_0); - - \r.m.nalign_RNIV7Q8\ : OR2A - port map(A => nalign, B => \inst[21]\, Y => - trap_0_sqmuxa_1_0); - - \r.m.result_RNO[2]\ : MX2 - port map(A => \aluresult[2]\, B => \op1[2]\, S => - un17_casaen_0, Y => \eres2[2]\); - - \r.w.s.y_RNO_2[1]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[1]\, Y => - N_400); - - \r.f.pc_RNO_1[31]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[31]\, C => - \pc_1_iv_0[31]\, Y => \pc_1_iv_1[31]\); - - \r.e.shleft_RNI3RMD2\ : MX2B - port map(A => \shiftin_5[45]\, B => \shiftin_5[29]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[29]\); - - \r.e.op1_RNI0NCR1[18]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[18]\, Y => - \ex_op1_i_m[18]\); - - \r.e.ldbp2_RNIVPRB3\ : OR2 - port map(A => \eaddress[1]\, B => \eaddress[0]\, Y => - un12_ex_add_res); - - \r.e.aluop_0_RNIMC591[2]\ : XA1 - port map(A => \un1_iu0_5[96]\, B => \aluop_0[2]\, C => - \un1_iu0_6[30]\, Y => N_3557); - - \r.a.ctrl.inst_RNIK42S[21]\ : NOR3A - port map(A => inst_11_0, B => \inst_2[20]\, C => - \inst_2[21]\, Y => inst_11_1); - - \r.a.rsel2_RNI9LB_2[1]\ : NOR2A - port map(A => \rsel2[2]\, B => \rsel2[1]\, Y => d29_0); - - \r.e.op2_RNO_8[25]\ : OR3B - port map(A => d29_0, B => \imm[25]\, C => \rsel2[0]\, Y => - \imm_m_i[25]\); - - \r.d.mexc\ : DFN1E0 - port map(D => mexc_2, CLK => lclk_c, E => inull_RNIFV6VG2_0, - Q => mexc_1); - - \r.e.sari\ : DFN1E0 - port map(D => sari_0, CLK => lclk_c, E => holdn, Q => sari); - - \r.w.result_RNIASGG[10]\ : AOI1B - port map(A => \un1_p0_6[362]\, B => d14, C => - \result_m_0_0[10]\, Y => \d_iv_0[10]\); - - \r.d.inst_0_RNO[30]\ : NOR2B - port map(A => rst, B => N_4630, Y => \inst_0_RNO[30]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I173_un1_Y : OAI1 - port map(A => I121_un1_Y, B => ADD_33x33_fast_I121_Y_0, C - => N577_1, Y => I173_un1_Y_i); - - \r.e.aluop_RNIUSCV5G[0]\ : MX2B - port map(A => \logicout[21]\, B => \icc_16[1]\, S => - un3_op_i, Y => N_4176); - - un6_ex_add_res_d0_ADD_33x33_fast_I247_Y : AO1 - port map(A => N665_0, B => N614_1, C => N664_0, Y => N808_1); - - \r.e.op2_RNO_3[10]\ : NOR3C - port map(A => \result_m_i[10]\, B => \imm_m_i[10]\, C => - \d_1_iv_1[10]\, Y => \d_1_iv_2[10]\); - - \r.a.rsel2_0_RNIO5CM2[0]\ : OR2B - port map(A => data2(3), B => d25_0, Y => \rfo_m_i[35]\); - - \r.a.ctrl.pc_RNI2KE2C[16]\ : MX2 - port map(A => \pc_0[16]\, B => N_3893, S => ex_bpmiss_1, Y - => \fe_pc[16]\); - - \r.e.aluop_RNIJ0UN6[0]\ : MX2C - port map(A => N_3569, B => N_3633, S => \aluop_1[0]\, Y => - \logicout[10]\); - - \r.e.bp_RNIE5V7\ : OA1B - port map(A => bp, B => bp_0, C => annul_1, Y => - de_fins_hold_1_1); - - \r.m.ctrl.trap_RNIALRKM1\ : OR2B - port map(A => tt_1_sqmuxa_1, B => un6_annul, Y => - N_4210_i_0); - - \r.e.op2[10]\ : DFN1E0 - port map(D => N_294, CLK => lclk_c, E => holdn, Q => - \op2[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I18_P0N : OR3A - port map(A => \data_0[17]\, B => \op1[17]\, C => ldbp1_0, Y - => N449); - - \r.w.result_RNISQ3C[3]\ : AOI1B - port map(A => \result[3]\, B => d31, C => \imm_m_i[3]\, Y - => \d_1_iv_0[3]\); - - \r.d.pc[13]\ : DFN1 - port map(D => \pc_RNO[13]\, CLK => lclk_c, Q => \dpc[13]\); - - \r.e.op2[26]\ : DFN1E0 - port map(D => N_310, CLK => lclk_c, E => holdn, Q => - \op2[26]\); - - \r.e.shcnt_RNIUQ6M_0[2]\ : MX2C - port map(A => \shcnt[2]\, B => N_3306, S => ldbp2_0, Y => - \ex_shcnt_1_i[2]\); - - \r.e.op2_RNIPUUD4[5]\ : AOI1B - port map(A => \un1_iu0_5[71]\, B => aluresult_7_sqmuxa_0_0, - C => \aluresult_1_iv_0[5]\, Y => \aluresult_1_iv_1[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I250_Y_0_o3 : NOR2 - port map(A => N418_1, B => ADD_33x33_fast_I250_Y_0_a3, Y - => N817_i); - - \r.e.aluop_RNI7R22F[1]\ : NOR2B - port map(A => \edata2_iv_2[25]\, B => \edata2_iv_1[25]\, Y - => edata2_iv_i_0(25)); - - \r.e.ctrl.tt_RNO_2[1]\ : NOR2B - port map(A => trap_4_1, B => privileged_inst_5, Y => N_4036); - - \r.x.result_RNI2NED[18]\ : MX2 - port map(A => \result_0[18]\, B => \data_0_0[18]\, S => - ld_0, Y => \un1_p0_6[370]\); - - \r.e.jmpl_RNI8D3FJ7\ : OR3C - port map(A => \aluresult_1_iv_8[29]\, B => - \shiftin_17_m_0[29]\, C => \un6_ex_add_res_m[30]\, Y => - \aluresult[29]\); - - \r.e.invop2_RNI7J1L4\ : MX2C - port map(A => \un6_ex_add_res_s2[5]\, B => - \un6_ex_add_res_s0[5]\, S => invop2, Y => N_6644); - - \r.w.s.tt_RNILFEJ3[3]\ : AOI1B - port map(A => aluresult_12_sqmuxa_0_0, B => \irl[3]\, C => - \aluresult_1_iv_2[7]\, Y => \aluresult_1_iv_4[7]\); - - \r.m.icc_RNO_3[2]\ : MX2C - port map(A => un1_addout, B => icc_0_sqmuxa_1_i, S => - aluresult12, Y => \icc_16[2]\); - - \r.e.shcnt_RNI2NUM6[3]\ : MX2 - port map(A => \shiftin_8[39]\, B => \shiftin_8[31]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I66_Y : OR2A - port map(A => N440_1, B => N437_2, Y => N525_0); - - \r.a.ctrl.inst_RNIGVLQB[31]\ : OR2 - port map(A => fp_disabled_4, B => cp_disabled_4, Y => - trap_4_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I301_Y_0 : XOR2 - port map(A => N811_0, B => \un6_ex_add_res_s2_1[11]\, Y => - \un6_ex_add_res_s2[11]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I95_un1_Y : OR3C - port map(A => N485, B => N488_2, C => N496_0, Y => - I95_un1_Y); - - \r.x.result[17]\ : DFN1E0 - port map(D => \maddress[17]\, CLK => lclk_c, E => holdn, Q - => \result_0[17]\); - - \r.d.inull_RNI35OFT_0\ : NOR2 - port map(A => un2_rstn_5_0_i, B => un18_hold_pc, Y => - de_hold_pc_1_0); - - \r.a.rsel1_RNIMB2204[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[14]\, Y => - \aluresult_m_0[14]\); - - \r.a.ctrl.inst_RNIE41S[30]\ : NOR3 - port map(A => N_203, B => \inst[30]\, C => \inst_2[20]\, Y - => aluop_0_1_0_a5_3_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I16_P0N : OR2 - port map(A => \un1_iu0_6[15]\, B => \op2[15]\, Y => N443); - - \r.x.ctrl.pc[21]\ : DFN1E0 - port map(D => \pc_3[21]\, CLK => lclk_c, E => holdn, Q => - \pc_2[21]\); - - \r.m.result[2]\ : DFN1E0 - port map(D => \eres2[2]\, CLK => lclk_c, E => holdn, Q => - \maddress[2]\); - - \r.e.op1_RNI5HFC[1]\ : OR2B - port map(A => \op1[1]\, B => un14_casaen_s1_0, Y => - \op1_m_0[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I20_G0N : NOR2B - port map(A => \op1_RNID1VH[19]\, B => \op2[19]\, Y => - N454_2); - - \r.e.shcnt_RNIPR6OB[2]\ : MX2C - port map(A => \shiftin_11[20]\, B => \shiftin_11[16]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[16]\); - - \r.e.op1_RNIOC5I1[0]\ : OR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[0]\, Y => - \ex_op1_i_m[0]\); - - \r.a.ctrl.inst_RNIT2954[13]\ : AOI1B - port map(A => illegal_inst_4_m_0, B => illegal_inst33, C - => cp_disabled_3_sqmuxa_2, Y => illegal_inst_7_iv_1); - - \r.a.ctrl.annul\ : DFN1E0 - port map(D => ctrl_annul_i, CLK => lclk_c, E => holdn, Q - => annul_2); - - \r.x.result_RNI3OJJ5[15]\ : OR2B - port map(A => \bpdata[15]\, B => N_3974, Y => - \bpdata_m[15]\); - - un6_fe_npc_I_84 : XOR2 - port map(A => N_93, B => \fe_pc[16]\, Y => I_84); - - un6_ex_add_res_d2_ADD_33x33_fast_I263_Y_0 : AO1 - port map(A => N574_0, B => N567_0, C => N566, Y => - ADD_33x33_fast_I263_Y_0_0); - - \r.w.s.et_RNI1DI8\ : NOR2B - port map(A => et, B => pv_1, Y => un6_annul_1); - - \r.e.aluop_RNI5JL9F[1]\ : NOR2B - port map(A => \edata2_iv_2[30]\, B => \edata2_iv_1[30]\, Y - => edata2_iv_i_0(30)); - - \r.e.op1_RNITECR1[16]\ : NOR2A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[16]\, Y => - \ex_op1_i_m[16]\); - - \r.x.result_RNIAGOA5[11]\ : NOR2B - port map(A => \bpdata[11]\, B => \aluop_RNIGM3N1[2]\, Y => - \bpdata_i_m[11]\); - - \r.e.op1_RNIG7O8[5]\ : MX2 - port map(A => \op1[5]\, B => \data_0[5]\, S => ldbp1_3, Y - => \un1_iu0_6[5]\); - - \r.x.data_0_RNO[15]\ : OR3 - port map(A => \dco_m_0[111]\, B => \data_0_1_0_iv_0[15]\, C - => \data_0_1_4[9]\, Y => \data_0_1[15]\); - - \r.x.data_0_RNI83T8[7]\ : XOR2 - port map(A => \data_0_2[7]\, B => invop2_0, Y => N_4254); - - un6_ex_add_res_d0_ADD_33x33_fast_I9_G0N : NOR3A - port map(A => \op1[8]\, B => ldbp1_0, C => \data_0[8]\, Y - => N421); - - un6_ex_add_res_d0_ADD_33x33_fast_I172_Y : NOR2B - port map(A => N583_0, B => N575_0, Y => N641_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I41_Y_i\ : OAI1 - port map(A => \dpc[25]\, B => \inst_0_1[25]\, C => N425, Y - => N_11); - - un6_ex_add_res_d0_ADD_33x33_fast_I18_G0N : NOR3A - port map(A => \op1[17]\, B => ldbp1_0, C => \data_0[17]\, Y - => N448); - - un6_ex_add_res_d0_ADD_33x33_fast_I180_Y : NOR2A - port map(A => N583_0, B => N591_2, Y => N649_0); - - \r.e.op1_RNIRGNO6[23]\ : OR3 - port map(A => \bpdata_i_m[23]\, B => \op1_i_m[23]\, C => - \ex_op1_i_m[23]\, Y => \edata2_0_iv_1[23]\); - - \r.a.ctrl.rd_RNII0FK1[0]\ : XA1A - port map(A => \rd_2[0]\, B => \inst_0_RNI0FUM[0]\, C => - un1_de_ren1_1_i, Y => un1_de_ren1_NE_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I12_G0N : NOR3A - port map(A => \op1[11]\, B => ldbp1, C => \data_0_2[11]\, Y - => N430_0); - - \r.a.ctrl.rett_RNIUMQB\ : OR2 - port map(A => rett_2, B => rett_3, Y => rett_0_0); - - \r.a.ctrl.trap\ : DFN1E0 - port map(D => mexc_1, CLK => lclk_c, E => holdn, Q => - trap_1); - - \r.m.dci.asi[3]\ : DFN1E0 - port map(D => \asi[3]\, CLK => lclk_c, E => holdn, Q => - asi_0(3)); - - \r.m.ctrl.pc_RNI42IF[17]\ : MX2 - port map(A => \pc_3[17]\, B => \pc[17]\, S => \npc_1[1]\, Y - => N_3258); - - \r.e.ctrl.pc[21]\ : DFN1E0 - port map(D => \pc[21]\, CLK => lclk_c, E => holdn, Q => - \pc_0[21]\); - - \r.e.alusel_RNIRC5C_0[0]\ : NOR3A - port map(A => \alusel[1]\, B => \alusel[0]\, C => jmpl, Y - => aluresult_3_sqmuxa); - - \r.e.alusel_RNIJDA9_0[0]\ : OR2 - port map(A => \alusel[1]\, B => \alusel[0]\, Y => - aluresult12); - - \r.m.icc_RNI88I3[3]\ : XNOR2 - port map(A => \icc[1]\, B => \icc[3]\, Y => N_211); - - \r.e.aluop_0_RNIS2ML[1]\ : AO1 - port map(A => \un1_iu0_6[24]\, B => \aluop_0[0]\, C => - \aluop_0[1]\, Y => \logicout_5_0_i_a5_0_0[24]\); - - \r.m.result_RNI3TGL[2]\ : OA1A - port map(A => \maddress[2]\, B => d27, C => \cpi_m_i[354]\, - Y => \d_1_iv_1[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I171_un1_Y : OR2B - port map(A => N582_1, B => N575_0, Y => I171_un1_Y_i); - - \r.a.ctrl.trap_RNI2LGGI\ : NOR2A - port map(A => privileged_inst_5, B => trap_1, Y => - \tt_9_1[0]\); - - \r.a.ctrl.ld_RNO_0\ : OR2A - port map(A => un54_casaen, B => call_hold7_i, Y => - write_reg_0_sqmuxa_1); - - \r.e.aluop_RNIO3ML1[0]\ : XA1B - port map(A => N_246, B => \aluop_1[0]\, C => - \un1_iu0_6[24]\, Y => N_447); - - \r.x.result_RNI03MJ3[28]\ : MX2C - port map(A => \un1_iu0_6[28]\, B => \un1_p0_6[380]\, S => - bpdata6, Y => \bpdata[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I160_Y : NOR2B - port map(A => N571_2, B => N563, Y => N629_0); - - \r.a.ctrl.inst_RNIDG9A_0[29]\ : NOR2A - port map(A => pv, B => \inst[29]\, Y => un6_rabpmiss_0); - - \r.m.y_RNO_4[20]\ : OR2B - port map(A => \y[21]\, B => mulstep_0, Y => \y_m_2[21]\); - - \r.m.y_RNO_1[3]\ : OR2B - port map(A => \y[4]\, B => mulstep_1, Y => \y_m[4]\); - - \r.d.annul_RNIFVDAE2\ : OR2A - port map(A => un8_op, B => ctrl_annul_i, Y => un1_wcwp); - - \comb.branch_address.tmp_ADD_30x30_fast_I271_Y_0\ : XOR2 - port map(A => N735, B => ADD_30x30_fast_I271_Y_0_0, Y => - \tmp[13]\); - - \r.e.op1_RNICPUH[26]\ : MX2 - port map(A => \op1[26]\, B => \data_0[26]\, S => ldbp1_3, Y - => \un1_iu0_6[26]\); - - \r.d.inst_0_RNI66J4_2[23]\ : AOI1B - port map(A => \inst_0_0[23]\, B => \inst_0_0[22]\, C => - \inst_0_0[24]\, Y => ldcheck1_5_i_a6_0_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I243_un1_Y : NOR2B - port map(A => N672, B => N657, Y => I243_un1_Y_1); - - \r.d.inst_0_0_0_RNI9O79[21]\ : MX2 - port map(A => \un1_p0_6_0[60]\, B => \inst_0_0[22]\, S => - \inst_0[30]\, Y => \inst_0_0_0_RNI9O79[21]\); - - \r.d.cwp_RNO_1[1]\ : MX2 - port map(A => \cwp[1]\, B => \maddress[1]\, S => wcwp, Y - => N_4219); - - \comb.branch_address.tmp_ADD_30x30_fast_I236_un1_Y_0\ : NOR2B - port map(A => N591, B => N575, Y => - ADD_30x30_fast_I236_un1_Y_0); - - \r.a.bp_RNIQD984_0\ : OR2B - port map(A => ra_bpmiss_1_1, B => branch, Y => ra_bpmiss_1); - - \r.w.s.tba_RNI9E524[16]\ : AOI1B - port map(A => \tba[16]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[28]\, Y => \aluresult_1_iv_3[28]\); - - \r.m.y_RNO_1[19]\ : AOI1B - port map(A => \y_0[19]\, B => y08_0, C => \y_m_0[20]\, Y - => \y_iv_0[19]\); - - \r.d.cnt_RNISDD3[1]\ : NOR2A - port map(A => \cnt_0[1]\, B => annul_1, Y => ldchkex_0); - - wovf_exc_0_sqmuxa : NAND2 - port map(A => un8_op, B => un25_op, Y => - \wovf_exc_0_sqmuxa\); - - un6_ex_add_res_d1_ADD_33x33_fast_I299_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[8]\, B => \op2[8]\, Y => - ADD_33x33_fast_I299_Y_0_0); - - \r.e.ldbp2_1_RNIMTP2J2\ : MX2C - port map(A => \un6_ex_add_res_s1_i[18]\, B => N_6637, S => - ldbp2_1, Y => \eaddress[17]\); - - \r.d.pc_RNI4KCA4[9]\ : MX2 - port map(A => \dpc[9]\, B => \fpc[9]\, S => \ra_bpmiss_1_0\, - Y => N_3886); - - \r.m.y_RNO[10]\ : OR3C - port map(A => \y_iv_1[10]\, B => \y_iv_0[10]\, C => - \logicout_m[10]\, Y => \y_1[10]\); - - \r.d.pc[15]\ : DFN1 - port map(D => \pc_RNO[15]\, CLK => lclk_c, Q => \dpc[15]\); - - un6_fe_npc_I_156 : XOR2 - port map(A => N_42, B => \fe_pc[25]\, Y => I_156); - - \r.d.pc[30]\ : DFN1 - port map(D => \pc_RNO[30]\, CLK => lclk_c, Q => \dpc[30]\); - - \r.x.data_0_RNO_2[11]\ : NOR2A - port map(A => \data_0_2[11]\, B => ld_3, Y => - \data_0_m[11]\); - - \r.m.result_0_RNI4MR8[3]\ : OR2B - port map(A => d13_0, B => \maddress_0[3]\, Y => - \result_m_0[3]\); - - \r.e.op2_RNO_5[21]\ : OR2B - port map(A => data2(21), B => d25, Y => \rfo_m_i[53]\); - - \r.m.y_RNO_0[16]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y_0[16]\, C => \y_m_0[16]\, - Y => \y_iv_1[16]\); - - \r.f.pc_RNO_2[12]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[12]\, C => - \xc_trap_address_m[12]\, Y => \pc_1_iv_0[12]\); - - \r.e.shcnt_RNI5I91O[1]\ : MX2C - port map(A => \shiftin_14[16]\, B => \shiftin_14[14]\, S - => \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[14]\); - - \r.d.inull_RNI35OFT\ : NOR2 - port map(A => un2_rstn_5_0_i, B => un18_hold_pc, Y => - \de_hold_pc_1\); - - un2_rstn_5_RNI1D94ME : OR2B - port map(A => m14_2, B => N_6620, Y => N_15); - - \r.x.data_0[14]\ : DFN1E0 - port map(D => \data_0_1[14]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[14]\); - - \r.w.result[4]\ : DFN1E0 - port map(D => \wdata[4]\, CLK => lclk_c, E => holdn, Q => - \result_0[4]\); - - \r.e.op2_RNO_4[24]\ : NOR2B - port map(A => \result_m_i[24]\, B => \cpi_m_i[376]\, Y => - \d_1_iv_1[24]\); - - \r.e.op2_RNO[25]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[25]\, Y => N_309); - - \r.e.ldbp2_2_RNIHO2FK1\ : NOR2A - port map(A => annul_RNI5L7FE1, B => \eaddress[3]\, Y => - \un6_ex_add_res_m_1[4]\); - - \r.m.ctrl.pc_RNI17AE[7]\ : MX2 - port map(A => \pc_2[7]\, B => \pc_3[7]\, S => \npc_0[1]\, Y - => N_3248); - - \r.x.data_0_RNO_1[21]\ : NOR2A - port map(A => \data_0[21]\, B => ld_3, Y => \data_0_m[21]\); - - \r.e.aluop_RNIF68AC[2]\ : AOI1B - port map(A => \bpdata[10]\, B => aluresult_5_sqmuxa, C => - \aluresult_1_iv_2[26]\, Y => \aluresult_1_iv_4[26]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I295_Y_0 : AX1B - port map(A => N406, B => ADD_33x33_fast_I206_Y_0_a3, C => - \un6_ex_add_res_s2_1[5]\, Y => \un6_ex_add_res_s0[5]\); - - \r.w.s.tba_RNI3M424[13]\ : AOI1B - port map(A => \tba[13]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_1[25]\, Y => \aluresult_1_iv_3[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I283_Y_0\ : XOR2 - port map(A => N706, B => ADD_30x30_fast_I283_Y_0_0, Y => - \tmp[25]\); - - \r.x.result_RNI5FI75[3]\ : NAND2 - port map(A => N_3957_1, B => \bpdata[3]\, Y => - \bpdata_m_1[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_Y_0 : MIN3 - port map(A => \data_0_0[29]\, B => \un1_iu0_6[29]\, C => - N481_1, Y => ADD_33x33_fast_I260_Y_0_1); - - \r.e.op2_RNO_0[15]\ : OR3C - port map(A => \op1_m_i[15]\, B => \d_1_iv_3[15]\, C => - \aluresult_m_i[15]\, Y => \d_1[15]\); - - \r.d.inst_0[4]\ : DFN1 - port map(D => \inst_0_RNO[4]\, CLK => lclk_c, Q => - \inst_0[4]\); - - \r.x.ctrl.annul\ : DFN1E0 - port map(D => annul_RNIPFOQ, CLK => lclk_c, E => holdn, Q - => annul_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I204_un1_Y\ : NOR2B - port map(A => N596, B => N581, Y => I204_un1_Y); - - \r.x.icc[3]\ : DFN1E0 - port map(D => \icc[3]\, CLK => lclk_c, E => holdn, Q => - \icc_2[3]\); - - \r.e.aluop_RNIJ6473[1]\ : MX2C - port map(A => N_3539, B => \logicout_3[12]\, S => - \aluop_3[1]\, Y => N_3571); - - un6_ex_add_res_d0_ADD_33x33_fast_I14_P0N : OR3A - port map(A => \data_0[13]\, B => \op1[13]\, C => ldbp1_0, Y - => N437); - - un6_ex_add_res_d0_ADD_33x33_fast_I129_Y : OR3 - port map(A => I67_un1_Y, B => N436_1, C => I129_un1_Y, Y - => N592); - - \r.x.result_RNINK5H2[6]\ : OR2A - port map(A => \result_0[6]\, B => cwp_1_sqmuxa_0, Y => - \result_m[6]\); - - \r.m.y_RNIB3QA7[29]\ : OA1A - port map(A => aluresult_6_sqmuxa, B => \bpdata[29]\, C => - \aluresult_1_iv_0[29]\, Y => \aluresult_1_iv_2[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I274_Y_0_o3 : AOI1 - port map(A => N796, B => N443, C => N442_0, Y => N794_i); - - \r.x.ctrl.pc_RNIEIHF[15]\ : MX2 - port map(A => \pc_0[15]\, B => \pc_2[15]\, S => \npc_0[1]\, - Y => N_3226); - - \r.d.cnt_RNO_1[1]\ : OR3 - port map(A => ldlock, B => annul_1, C => hold_pc_2_sqmuxa, - Y => cnt_3_sqmuxa_0); - - \r.a.rfa1[7]\ : DFN1E0 - port map(D => \un3_de_ren1[98]\, CLK => lclk_c, E => holdn, - Q => \rfa1[7]\); - - \r.x.data_0_RNO_3[5]\ : OA1A - port map(A => \data_0[5]\, B => ld_0_0, C => \dco_m_i[109]\, - Y => \data_0_1_1_iv_0[5]\); - - \r.e.ldbp2_0_RNIP5D6S\ : MX2C - port map(A => \un6_ex_add_res_s1_i[11]\, B => N_6630, S => - ldbp2_0, Y => \eaddress[10]\); - - \r.d.annul_RNIP2H4_0\ : NOR2 - port map(A => annul_1, B => N_85, Y => hold_pc_0_sqmuxa); - - \r.a.ctrl.inst_RNIIG1S[31]\ : NOR3A - port map(A => N_216, B => \inst[30]\, C => \inst[31]\, Y - => cp_disabled_3_sqmuxa_2_0); - - \r.x.result_RNIPS6E[30]\ : MX2 - port map(A => \result_0[30]\, B => \data_0[30]\, S => ld_4, - Y => \un1_p0_6[382]\); - - \r.e.ctrl.rd[3]\ : DFN1E0 - port map(D => \rd_1[3]\, CLK => lclk_c, E => holdn, Q => - \rd[3]\); - - \r.e.aluop_RNIVGDQB[1]\ : NOR2 - port map(A => \edata2_0_iv_1[14]\, B => \bpdata_i_m_2[6]\, - Y => edata2_0_iv(14)); - - \r.a.ctrl.pc[17]\ : DFN1E0 - port map(D => \dpc[17]\, CLK => lclk_c, E => holdn, Q => - \pc[17]\); - - \r.w.s.wim_RNIC5RD2[6]\ : OR2B - port map(A => \wim[6]\, B => aluresult_13_sqmuxa, Y => - \wim_m[6]\); - - \r.m.y[7]\ : DFN1E0 - port map(D => \y_1[7]\, CLK => lclk_c, E => holdn, Q => - \y[7]\); - - \r.m.dci.asi[1]\ : DFN1E0 - port map(D => \asi[1]\, CLK => lclk_c, E => holdn, Q => - asi_0(1)); - - \r.e.aluop_RNISTEO2[1]\ : MX2C - port map(A => N_3556, B => \logicout_3[29]\, S => - \aluop_3[1]\, Y => N_3588); - - \r.x.rstate_RNI5S7L_1[1]\ : NOR2 - port map(A => annul_1_0, B => \rstate_d[2]\, Y => - rstate_9_0); - - \r.a.ctrl.inst_RNIP42A1[21]\ : OR3 - port map(A => N_201, B => N_216, C => N_492, Y => N_365); - - \r.x.npc_RNIMBFL[0]\ : MX2C - port map(A => N_3229, B => N_3259, S => \npc[0]\, Y => - \xc_result[18]\); - - \r.m.result_RNILLE71[2]\ : OA1B - port map(A => \maddress[2]\, B => result_1, C => - trap_0_sqmuxa_3_1, Y => trap_0_sqmuxa_3); - - un6_ex_add_res_d1_ADD_33x33_fast_I316_Y_0 : XNOR2 - port map(A => N776_1, B => ADD_33x33_fast_I316_Y_0_0, Y => - \un6_ex_add_res_s1_i[26]\); - - \r.x.npc[0]\ : DFN1E0 - port map(D => \npc_1[0]\, CLK => lclk_c, E => holdn, Q => - \npc[0]\); - - \r.m.y[3]\ : DFN1E0 - port map(D => \y_0[3]\, CLK => lclk_c, E => holdn, Q => - \y_1[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I8_G0N : OA1 - port map(A => \op1[7]\, B => ldbp1_2, C => \data_0_2[7]\, Y - => N418); - - \r.e.op1_RNO[0]\ : MX2 - port map(A => \d[0]\, B => \d[1]\, S => N_227_0, Y => - \aop1[0]\); - - \r.e.ctrl.pc_RNIO2OI4[27]\ : NOR3C - port map(A => \ex_op2_m[27]\, B => aluresult_8_sqmuxa_i, C - => \aluresult_0_iv_1[27]\, Y => \aluresult_0_iv_2[27]\); - - \r.m.y_RNO[28]\ : AO1C - port map(A => y14_0, B => \logicout[28]\, C => \y_iv_2[28]\, - Y => \y_1[28]\); - - \r.e.shleft_RNIA99D2\ : MX2B - port map(A => \shiftin_5[38]\, B => \shiftin_5[22]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[22]\); - - \r.x.data_0_RNIDF9E[17]\ : XOR2 - port map(A => \data_0[17]\, B => invop2_0, Y => N_4264); - - un6_ex_add_res_d0_ADD_33x33_fast_I7_P0N : OR2A - port map(A => \data_0[6]\, B => \un1_iu0_6[6]\, Y => N416_0); - - \comb.v.x.data_0_1_1_iv[19]\ : OR2 - port map(A => \data_0_1_2[17]\, B => \data_0_1_1_iv_1[19]\, - Y => \data_0_1[19]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I68_Y : AND2 - port map(A => N434, B => N437, Y => N527); - - \r.e.ctrl.annul_RNIMA264\ : AOI1 - port map(A => jump_1_sqmuxa_1_i_0, B => jump_0_sqmuxa_1_i_0, - C => annul, Y => jump_0); - - \r.w.result_RNIVCHF[5]\ : AOI1B - port map(A => \un1_p0_6[357]\, B => d14, C => N_403, Y => - \d_iv_0_0[5]\); - - \r.d.inst_0_RNI4023_2[20]\ : NOR2A - port map(A => \inst_0[19]\, B => \inst_0[20]\, Y => N_152); - - \r.d.inst_0_RNO[2]\ : NOR2B - port map(A => rst, B => N_4602, Y => \inst_0_RNO[2]\); - - \r.x.y[30]\ : DFN1E0 - port map(D => \y[30]\, CLK => lclk_c, E => holdn, Q => - \y_2[30]\); - - \r.a.rsel2_RNO[1]\ : NOR3 - port map(A => N_3950, B => N_3946_1, C => un1_de_ren1_2, Y - => N_3946); - - \r.m.y_RNO[15]\ : AO1C - port map(A => y14_0, B => \logicout[15]\, C => \y_iv_2[15]\, - Y => \y_0[15]\); - - \r.e.shleft_0_RNI0KCN2\ : MX2B - port map(A => \shiftin_5[35]\, B => \shiftin_5[19]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[19]\); - - \r.e.ldbp2_RNIA1PAC1\ : OR2A - port map(A => \eaddress[13]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I124_un1_Y\ : OA1 - port map(A => N379, B => N_44, C => N486, Y => I124_un1_Y); - - \r.e.op2_RNO_2[27]\ : NOR3C - port map(A => \d_1_iv_1[27]\, B => \d_1_iv_0[27]\, C => - \rfo_m_i[59]\, Y => \d_1_iv_3[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I67_Y\ : OA1 - port map(A => \dpc[12]\, B => \inst_0[10]\, C => N386, Y - => N484_1); - - \r.w.result[19]\ : DFN1E0 - port map(D => \wdata[19]\, CLK => lclk_c, E => holdn, Q => - \result[19]\); - - \r.e.op1_RNIB33185[0]\ : NOR3 - port map(A => \un1_iu0_6[1]\, B => \un1_iu0_6[0]\, C => - \icc_2[1]\, Y => \icc_8_1[1]\); - - \r.d.annul_RNIVI35T\ : XNOR2 - port map(A => ldlock, B => branch_0, Y => annul_RNIVI35T); - - \comb.branch_address.tmp_ADD_30x30_fast_I93_Y\ : NOR2A - port map(A => N454, B => N_11, Y => N513); - - \r.m.result_RNIUC5D3[26]\ : NOR3C - port map(A => \d_iv_0[26]\, B => \result_m_0[26]\, C => - \rfo_m[26]\, Y => \d_iv_2[26]\); - - \r.e.aluop_1_RNICGR61_1[1]\ : NOR3B - port map(A => miscout69, B => logicout20, C => - aluresult_9_sqmuxa_1, Y => aluresult_10_sqmuxa_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_a3_1 : OR2B - port map(A => ADD_33x33_fast_I206_Y_0_a3_1_0_0, B => N401_1, - Y => N_57_i_0); - - \r.x.ctrl.tt_RNIL6SJ[0]\ : OR3C - port map(A => tt_1, B => tt_0, C => tt_2, Y => tt_i); - - \r.m.icc_RNIUN961[2]\ : OR2A - port map(A => \icc_0[2]\, B => aluresult_11_sqmuxa, Y => - \icc_m[2]\); - - \r.f.pc_RNO_0[24]\ : OR3A - port map(A => \tmp[24]\, B => un2_rstn_5_2, C => - \un2_rstn_5_0_0\, Y => \tmp_m[24]\); - - \r.w.result_RNIVPSI[3]\ : AOI1B - port map(A => \un1_p0_6[355]\, B => d14, C => - \result_m_0_0[3]\, Y => \d_iv_0[3]\); - - \r.m.ctrl.rd_RNIDE501[0]\ : XA1A - port map(A => \rd_1[0]\, B => \inst_0_RNI0FUM[0]\, C => - wreg_4, Y => wreg_0_0); - - \r.d.inst_0[17]\ : DFN1 - port map(D => \inst_0_RNO[17]\, CLK => lclk_c, Q => - \inst_0[17]\); - - \r.m.y_RNILEVOG[11]\ : NOR3C - port map(A => \bpdata_m_2[3]\, B => \aluresult_1_iv_3[11]\, - C => \aluresult_1_iv_4[11]\, Y => \aluresult_1_iv_6[11]\); - - \r.a.ctrl.inst_RNIPC231[19]\ : OR3 - port map(A => \inst_1[24]\, B => \inst_2[19]\, C => N_204, - Y => N_476); - - \r.m.y_RNIA4K91[4]\ : OR2B - port map(A => \y[4]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[4]\); - - \r.a.su_RNID9KK42\ : OR2B - port map(A => privileged_inst_5, B => illegal_inst_7_i_0, Y - => N_4033_i); - - \r.x.ctrl.pc_RNIDKI61[26]\ : MX2C - port map(A => \un1_p0_6[378]\, B => \pc_2[26]\, S => - s_3_sqmuxa, Y => N_3417); - - \r.e.ldbp2_1_RNI6MA7F4\ : OR2A - port map(A => \eaddress[26]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[27]\); - - \comb.v.f.pc_1_iv_RNO_1[3]\ : NOR3B - port map(A => \pc_4_m[3]\, B => \xc_trap_address_m[3]\, C - => \un6_ex_add_res_m_1[4]\, Y => \pc_1_iv_1[3]\); - - \r.e.aluop_0_RNIB57K2[0]\ : OR2A - port map(A => \logicout[0]\, B => y14, Y => N_463); - - \r.e.op2_RNO[22]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[22]\, Y => N_306); - - \r.x.result_RNIUPEGK[2]\ : NOR2A - port map(A => rst, B => N_3872, Y => \cwp_1_0[2]\); - - \r.w.s.y_RNO_1[29]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y_0[29]\, Y => N_412); - - \r.e.shleft_1_RNIJ9G13\ : MX2 - port map(A => \shiftin_5[49]\, B => \shiftin_5[33]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[33]\); - - \r.x.data_0_RNO[4]\ : AO1B - port map(A => N_3456, B => data_0_0_4, C => - \data_0_1_1_iv_2[4]\, Y => \data_0_1[4]\); - - \r.e.jmpl_RNIDV0T56\ : OR2B - port map(A => \aluresult_1_iv_9[23]\, B => - \un6_ex_add_res_m[24]\, Y => \aluresult[23]\); - - \r.e.ldbp2_1_RNIHAVEJ2\ : OR2A - port map(A => \eaddress[17]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[18]\); - - \r.m.result_RNI2DB4[5]\ : OR2B - port map(A => d13, B => \maddress[5]\, Y => N_406); - - \r.e.jmpl_RNISR9OQ\ : OR2B - port map(A => \shiftin_17[19]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[19]\); - - \r.x.y[21]\ : DFN1E0 - port map(D => \y[21]\, CLK => lclk_c, E => holdn, Q => - \y_1[21]\); - - \r.m.result[19]\ : DFN1E0 - port map(D => \eres2[19]\, CLK => lclk_c, E => holdn, Q => - \maddress[19]\); - - \r.e.op1_RNI8D6I1[8]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[8]\, Y => - \ex_op1_i_m[8]\); - - \r.w.s.tt[5]\ : DFN1E0 - port map(D => \xc_vectt_1[5]\, CLK => lclk_c, E => N_6747, - Q => \tt[5]\); - - \r.e.op2[7]\ : DFN1E0 - port map(D => N_291, CLK => lclk_c, E => holdn, Q => - \op2[7]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I264_un1_Y : NAND2 - port map(A => N811_0, B => ADD_33x33_fast_I264_un1_Y_0_0, Y - => I264_un1_Y_0); - - \r.x.data_0_RNILVG8[23]\ : XOR2 - port map(A => \data_0[23]\, B => invop2, Y => N_4270); - - \r.x.ctrl.pc[7]\ : DFN1E0 - port map(D => \pc_2[7]\, CLK => lclk_c, E => holdn, Q => - \pc[7]\); - - \r.m.y_RNI4RC92[14]\ : NOR2B - port map(A => \y_m_1[14]\, B => \cpi_m[159]\, Y => - \aluresult_1_iv_2[14]\); - - \r.m.result_RNIV9753[13]\ : NOR3C - port map(A => \d_iv_0[13]\, B => \result_m_0[13]\, C => - \rfo_m[13]\, Y => \d_iv_2[13]\); - - \r.e.ctrl.inst_RNIQTV42[22]\ : OR3B - port map(A => aluresult_11_sqmuxa_6, B => jump_1_sqmuxa_1_1, - C => jump_0_sqmuxa, Y => jump_1_sqmuxa_1_i_0); - - un6_fe_npc_I_186 : XOR2 - port map(A => N_21, B => \fe_pc[28]\, Y => I_186); - - un6_ex_add_res_d2_ADD_33x33_fast_I158_Y : NOR3B - port map(A => N495_0, B => N569_1, C => N_50_1, Y => N627); - - \r.x.result_RNIV2I75[2]\ : OR2B - port map(A => \bpdata[2]\, B => N_3957_1, Y => - \bpdata_m_1[2]\); - - \r.e.ldbp2_RNIBAJGP1\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[5]\, Y => - \un6_ex_add_res_m_1[6]\); - - \r.m.result_RNITOA4[0]\ : OR2B - port map(A => d13, B => \maddress[0]\, Y => \result_m_0[0]\); - - \r.e.aluop_RNI8OH84[0]\ : OR2B - port map(A => \logicout[1]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[1]\); - - \r.e.aluop_1_RNIV8ID1[1]\ : XOR3 - port map(A => \un1_iu0_6[31]\, B => \aluop_1[1]\, C => - \un1_iu0_5[97]\, Y => N_6916); - - \r.x.data_0_RNO_3[3]\ : AO1B - port map(A => rdatav_0_1_0_iv_5_1, B => mcdo_m_0_17, C => - N_3455, Y => \dco_m_i[115]\); - - \r.x.npc_0_RNIPME41[0]\ : MX2C - port map(A => N_3213, B => N_3243, S => \npc_0[0]\, Y => - \xc_result[2]\); - - \r.f.pc_RNIII9LP1[5]\ : OA1A - port map(A => \fpc[5]\, B => rst, C => - \un6_ex_add_res_m_1[6]\, Y => \npc_iv_1[5]\); - - \r.a.ctrl.inst_RNIA01E_0[22]\ : OR2 - port map(A => \inst_1[24]\, B => \inst[22]\, Y => inst_9_3); - - \r.m.y_RNO[23]\ : OR3C - port map(A => \y_iv_1[23]\, B => \y_iv_0[23]\, C => - \y_RNO_2[23]\, Y => \y_1[23]\); - - \r.f.pc_RNO_4[13]\ : MX2 - port map(A => I_66, B => N_4056, S => bpmiss_1_i_0_0, Y => - \pc_4[13]\); - - \r.x.result[9]\ : DFN1E0 - port map(D => \maddress[9]\, CLK => lclk_c, E => holdn, Q - => \result_0[9]\); - - \r.m.icc_RNO[2]\ : MX2C - port map(A => N_4187, B => N_4177, S => wicc_2, Y => - \icco[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I183_Y\ : OR2A - port map(A => I183_un1_Y_i, B => N550, Y => N610); - - un6_ex_add_res_d0_ADD_33x33_fast_I263_un1_Y : OR3C - port map(A => N649_0, B => N633, C => N808_1, Y => - I263_un1_Y); - - \r.e.ldbp2_RNI85BQ7\ : OR2A - port map(A => \eaddress[4]\, B => aluresult_0_sqmuxa, Y => - \un6_ex_add_res_m[5]\); - - \r.m.irqen2\ : DFN1E0 - port map(D => irqen, CLK => lclk_c, E => holdn, Q => irqen2); - - un2_rstn_5_0_0_RNIPEBG8 : NAND2 - port map(A => \tmp[10]\, B => un2_rstn_5_0, Y => - \tmp_m[10]\); - - \r.m.y_RNO_1[16]\ : AOI1B - port map(A => \y[16]\, B => y08, C => \y_m_1[17]\, Y => - \y_iv_0[16]\); - - \r.a.ctrl.inst_RNIKU8G3[22]\ : AOI1B - port map(A => \inst[22]\, B => N_263, C => - illegal_inst_7_iv_2_0_a5_4_2, Y => illegal_inst_7_iv_6_tz); - - \comb.branch_address.tmp_ADD_30x30_fast_I277_Y_0_0\ : XOR2 - port map(A => \dpc[19]\, B => \inst_0[17]\, Y => - ADD_30x30_fast_I277_Y_0_0); - - \r.e.op2_RNII0OB1[19]\ : OR2A - port map(A => \un1_iu0_5[85]\, B => \op1_RNID1VH[19]\, Y - => \logicout_4[19]\); - - \r.a.imm_RNO[16]\ : MX2 - port map(A => \inst_0[6]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[134]\); - - \r.m.ctrl.pc[17]\ : DFN1E0 - port map(D => \pc_0[17]\, CLK => lclk_c, E => holdn, Q => - \pc_3[17]\); - - \r.e.shcnt_RNIIJ6E6[3]\ : MX2 - port map(A => \shiftin_8[38]\, B => \shiftin_8[30]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[30]\); - - \r.m.y_RNO[27]\ : OR3C - port map(A => \y_iv_0_1[27]\, B => \y_iv_0_0[27]\, C => - N_420, Y => \y_1[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I140_un1_Y\ : OR2B - port map(A => N514, B => N507, Y => I140_un1_Y_i); - - un6_fe_npc_I_146 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \fe_pc[23]\, C => - \fe_pc[24]\, Y => \DWACT_FINC_E[33]\); - - \r.x.npc_RNI4S8R[0]\ : MX2C - port map(A => N_3227, B => N_3257, S => \npc[0]\, Y => - \xc_result[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I222_Y\ : AO1 - port map(A => N605, B => N501_0, C => N604, Y => N738); - - un6_ex_add_res_d0_ADD_33x33_fast_I2_P0N : OR2A - port map(A => \data_0[1]\, B => \un1_iu0_6[1]\, Y => N401); - - \r.a.ctrl.wicc_RNO_3\ : NOR3A - port map(A => \inst_0_0[24]\, B => \inst_0_0[22]\, C => - \un1_p0_6_0[60]\, Y => wicc_1_0_a3_1_1_0); - - \r.e.op1_RNIPU8G[23]\ : OR2B - port map(A => \op1[23]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[23]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I272_Y : OR3A - port map(A => N650, B => I272_un1_Y_0, C => I237_un1_Y_0, Y - => N790_0); - - \r.x.data_0_RNO_1[9]\ : AO1A - port map(A => rdata_5_sqmuxa, B => data_0_0_25, C => - \data_0_m[9]\, Y => \data_0_1_0_iv_0[9]\); - - \r.e.shleft_1_RNIEL5I1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[25]\, S => - shleft_1, Y => \shiftin_5[56]\); - - \r.e.aluop_2_RNI4TAS1[1]\ : MX2C - port map(A => N_3529, B => \logicout_3[2]\, S => - \aluop_2[1]\, Y => N_3561); - - \r.e.op2_RNO[15]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[15]\, Y => N_299); - - \r.d.inst_0_RNO[19]\ : NOR2B - port map(A => rst, B => N_4619, Y => \inst_0_RNO[19]\); - - \r.x.rstate_0_RNI4HKE2[0]\ : MX2C - port map(A => N_3406, B => \xc_result[15]\, S => - \rstate_0[0]\, Y => \wdata[15]\); - - \r.m.icc[1]\ : DFN1E0 - port map(D => \icco[1]\, CLK => lclk_c, E => holdn, Q => - \icc[1]\); - - \r.x.result[21]\ : DFN1E0 - port map(D => \maddress[21]\, CLK => lclk_c, E => holdn, Q - => \result_0[21]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I123_Y : OAI1 - port map(A => N521_0, B => N524_1, C => N520_2, Y => N586_0); - - \r.e.op2_RNO_2[14]\ : NOR3C - port map(A => \d_1_iv_1[14]\, B => \d_1_iv_0[14]\, C => - \rfo_m_i[46]\, Y => \d_1_iv_3[14]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I121_Y : AO1 - port map(A => N522_0, B => N519_0, C => - ADD_33x33_fast_I121_Y_0_0, Y => N584); - - \comb.branch_address.tmp_ADD_30x30_fast_I111_Y\ : NOR2B - port map(A => N476_0, B => N472, Y => N531); - - \r.x.rstate_RNIPCH12[0]\ : MX2C - port map(A => N_3419, B => \xc_result[28]\, S => - \rstate[0]\, Y => \wdata[28]\); - - \r.e.op2_RNO_4[21]\ : AOI1B - port map(A => \result[21]\, B => d31_0, C => \imm_m_i[21]\, - Y => \d_1_iv_0[21]\); - - \r.f.pc_RNI7BPRFE[9]\ : OR3C - port map(A => \npc_iv_1[9]\, B => \npc_iv_0[9]\, C => - \npc_iv_2[9]\, Y => rpc_7); - - \r.m.y_RNI80LA2[7]\ : AOI1B - port map(A => \y[7]\, B => aluresult_10_sqmuxa_0, C => - \cpi_m[152]\, Y => \aluresult_1_iv_2[7]\); - - \r.e.op2_RNO_9[24]\ : OR3B - port map(A => d29_0, B => \imm[24]\, C => \rsel2[0]\, Y => - \imm_m_i[24]\); - - \r.x.y[15]\ : DFN1E0 - port map(D => \y[15]\, CLK => lclk_c, E => holdn, Q => - \y_1[15]\); - - \r.e.op2[11]\ : DFN1E0 - port map(D => N_295, CLK => lclk_c, E => holdn, Q => - \op2[11]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I235_un1_Y : OR2B - port map(A => N664_1, B => N649_1, Y => I235_un1_Y_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I49_Y : MAJ3 - port map(A => \data_0_0[22]\, B => \un1_iu0_6[22]\, C => - N460_2, Y => N508_0); - - \r.w.s.y_RNO_2[14]\ : NOR3 - port map(A => N_481, B => wy_RNILF1N3, C => \y_2[14]\, Y - => N_384); - - \r.e.ldbp2_RNI6LB1B\ : MX2C - port map(A => \un6_ex_add_res_s1_i[6]\, B => N_6645, S => - ldbp2_3, Y => \eaddress[5]\); - - \r.x.rstate_RNIR4LS1[0]\ : MX2C - port map(A => N_3421, B => \xc_result[30]\, S => - \rstate[0]\, Y => \wdata[30]\); - - \r.e.op1_RNI6HFC[2]\ : OR2B - port map(A => \op1[2]\, B => un14_casaen_s1_0, Y => - \op1_m_0[2]\); - - \r.e.op2_RNIQCAP_0[5]\ : OR2 - port map(A => \un1_iu0_6[5]\, B => \un1_iu0_5[71]\, Y => - \logicout_3[5]\); - - \r.e.aluop_0_RNI13R31[1]\ : MX2C - port map(A => \logicout_4[0]\, B => N_6865, S => N_6866_i_0, - Y => N_3623); - - \comb.v.f.pc_1_iv_RNO[3]\ : NAND2 - port map(A => un2_rstn_4_0_0, B => I_5, Y => - \un6_fe_npc_m[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I127_Y : AO1 - port map(A => N528_1, B => N525, C => N524, Y => N590_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I53_Y : MAJ3 - port map(A => \op2[20]\, B => \un1_iu0_6[20]\, C => N454_2, - Y => N512_0); - - \r.m.icc_RNO_16[2]\ : NOR3C - port map(A => icc_0_sqmuxa_1_8, B => icc_0_sqmuxa_1_7, C - => icc_0_sqmuxa_1_19, Y => icc_0_sqmuxa_1_26); - - \r.f.pc_RNO_1[27]\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[27]\, Y => - \un6_ex_add_res_m_1[28]\); - - \r.a.cwp[1]\ : DFN1E0 - port map(D => \cwp[1]\, CLK => lclk_c, E => holdn, Q => - \cwp_3[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I269_un1_Y_0 : NOR3A - port map(A => N645_0, B => N595, C => N603_i, Y => - ADD_33x33_fast_I269_un1_Y_0); - - \r.e.aluop_RNI79OO6[1]\ : AOI1B - port map(A => edata_2_sqmuxa, B => \bpdata[25]\, C => - \edata2_iv_0[25]\, Y => \edata2_iv_1[25]\); - - \r.d.pc_RNIO3BA4[3]\ : MX2 - port map(A => \dpc[3]\, B => \fpc[3]\, S => ra_bpmiss_1, Y - => N_3880); - - \r.a.rsel2_0_RNII0B2T1[0]\ : OR2B - port map(A => un14_casaen_s0_0_1, B => \aluresult[1]\, Y - => \aluresult_m_i[1]\); - - \r.a.ctrl.rd[3]\ : DFN1E0 - port map(D => N_17, CLK => lclk_c, E => holdn, Q => - \rd_1[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I113_Y : NOR3 - port map(A => I51_un1_Y, B => N460, C => I113_un1_Y, Y => - N576); - - un6_ex_add_res_d1_ADD_33x33_fast_I298_Y_0 : XOR3 - port map(A => \un1_iu0_6[7]\, B => \op2[7]\, C => N672_0, Y - => \un6_ex_add_res_s1[8]\); - - \r.x.ctrl.pc[2]\ : DFN1E0 - port map(D => \pc_3[2]\, CLK => lclk_c, E => holdn, Q => - \pc_0[2]\); - - \r.e.invop2_RNI1CH9Q1\ : MX2C - port map(A => \un6_ex_add_res_s2[20]\, B => - \un6_ex_add_res_s0[20]\, S => invop2, Y => N_6654); - - \r.d.cnt_RNITPRI[1]\ : OR3C - port map(A => N_142, B => wy_1_0_a3_1_0, C => - de_inst_0_sqmuxa_0, Y => de_inst_0_sqmuxa_i_0); - - \r.m.y_RNO_4[31]\ : OR2B - port map(A => mulstep_1, B => ex_ymsb_1, Y => ex_ymsb_1_m); - - \r.x.y[8]\ : DFN1E0 - port map(D => \y[8]\, CLK => lclk_c, E => holdn, Q => - \y_2[8]\); - - \r.e.op1_RNI49UH[22]\ : MX2 - port map(A => \op1[22]\, B => \data_0_0[22]\, S => ldbp1_3, - Y => \un1_iu0_6[22]\); - - \r.e.shcnt_RNINC346[3]\ : MX2 - port map(A => \shiftin_8[33]\, B => \shiftin_8[25]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I237_un1_Y : OR2B - port map(A => N666_0, B => N651, Y => I237_un1_Y_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I319_Y_0 : AX1C - port map(A => N_51_i_0, B => ADD_33x33_fast_I262_Y_0_0_0, C - => \un6_ex_add_res_s2_1[29]\, Y => - \un6_ex_add_res_s0[29]\); - - \r.d.pc_RNO[5]\ : MX2 - port map(A => \fpc[5]\, B => \dpc[5]\, S => N_6763_i_0, Y - => \pc_RNO[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I9_G0N : OA1 - port map(A => \op1[8]\, B => ldbp1_1, C => \data_0[8]\, Y - => N421_1); - - \r.e.op1_RNIDHFC[9]\ : OR2B - port map(A => \op1[9]\, B => un14_casaen_s1_0, Y => - \op1_m_0[9]\); - - \r.a.ctrl.inst_RNIO55K2[31]\ : OA1A - port map(A => cp_disabled_2_sqmuxa_0, B => N_216, C => - cp_disabled_8_sqmuxa_1, Y => cp_disabled_4_0_1_0); - - \r.e.shleft_0_RNI17BG\ : OR2A - port map(A => \un1_iu0_6[2]\, B => shleft_0, Y => - \shiftin_5[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I45_Y : MAJ3 - port map(A => \data_0[24]\, B => \un1_iu0_6[24]\, C => - N466_0, Y => N504_0); - - \r.d.inst_0_RNICEJ4[28]\ : OR2A - port map(A => N_85, B => \inst_0[28]\, Y => N_17); - - \r.f.pc_RNO_4[23]\ : MX2 - port map(A => I_136, B => N_4066, S => bpmiss_1_i_0, Y => - \pc_4[23]\); - - \r.e.aluop_2_RNI3BEI2[1]\ : MX2C - port map(A => N_3555, B => \logicout_3[28]\, S => - \aluop_2[1]\, Y => N_3587); - - \comb.branch_address.tmp_ADD_30x30_fast_I94_Y\ : AO1 - port map(A => N459, B => N456, C => N455, Y => N514); - - \r.d.inst_0_RNIE0IP1[25]\ : OR2 - port map(A => \inst_0_RNIFKEG[25]\, B => branch_1, Y => - N_108); - - \r.e.op1_RNIRA9G[16]\ : OR2B - port map(A => \op1[16]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[16]\); - - \r.a.rsel1_0_RNITC8M2[2]\ : OR3 - port map(A => d11_0_a5_0, B => \rsel1_0[2]\, C => data1(5), - Y => \rsel1_0_RNITC8M2[2]\); - - \r.x.ctrl.pc_RNIHMA71[29]\ : MX2C - port map(A => \un1_p0_6[381]\, B => \pc_2[29]\, S => - s_3_sqmuxa, Y => N_3420); - - \r.x.data_0_RNO_1[4]\ : AND2 - port map(A => \dco_m_i[108]\, B => \data_0_m_i[4]\, Y => - \data_0_1_1_iv_0[4]\); - - \r.a.imm[21]\ : DFN1E0 - port map(D => \un3_de_ren1[139]\, CLK => lclk_c, E => holdn, - Q => \imm[21]\); - - \r.e.op2[3]\ : DFN1E0 - port map(D => N_287, CLK => lclk_c, E => holdn, Q => - \op2[3]\); - - \r.w.s.wim_RNIMSJV2[7]\ : NOR2B - port map(A => aluresult_8_sqmuxa_i, B => \wim_m[7]\, Y => - \aluresult_1_iv_0[7]\); - - \r.e.aluop_2_RNILH4R2[1]\ : MX2C - port map(A => N_3549, B => \logicout_3[22]\, S => - \aluop_2[1]\, Y => N_3581); - - \r.d.inst_0_RNIQCIO[31]\ : OR2A - port map(A => imm9, B => un1_inst, Y => N_127); - - \comb.branch_address.tmp_ADD_30x30_fast_I160_Y\ : NOR2A - port map(A => I160_un1_Y_i, B => N526, Y => N586_i); - - \r.e.shcnt_RNIAARK6[3]\ : MX2A - port map(A => \shiftin_8[40]\, B => \shiftin_8[32]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[32]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I74_un1_Y\ : NAND2 - port map(A => N373, B => N377, Y => I74_un1_Y_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I151_Y : OR2 - port map(A => N548_0, B => I151_un1_Y, Y => N614_2); - - \r.a.ctrl.rd[7]\ : DFN1E0 - port map(D => un3_reg, CLK => lclk_c, E => holdn, Q => - \rd[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I320_Y_0 : XNOR2 - port map(A => N768_0, B => \un6_ex_add_res_s2_1[30]\, Y => - \un6_ex_add_res_s0[30]\); - - \r.m.ctrl.ld_RNIHU879\ : OR2 - port map(A => ld, B => dco_i_2(132), Y => ld_3); - - \r.e.jmpl_RNITR4DO\ : OR2B - port map(A => \shiftin_17[13]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[13]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I6_G0N\ : OR2B - port map(A => \inst_0[6]\, B => \dpc[8]\, Y => N376_i); - - \r.e.ctrl.pc_RNI71K11[21]\ : OR2B - port map(A => \pc_0[21]\, B => jmpl_0, Y => \cpi_m[166]\); - - \r.a.rsel1_0_RNIA7LJ2[2]\ : OR2B - port map(A => data1(20), B => d11, Y => \rfo_m[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I131_Y : AO1B - port map(A => N532_1, B => N529_2, C => N528_2, Y => N594_2); - - \comb.branch_address.tmp_ADD_30x30_fast_I242_un1_Y_0\ : NOR3B - port map(A => N551, B => N587, C => N543, Y => - ADD_30x30_fast_I242_un1_Y_0); - - \r.x.data_0[10]\ : DFN1E0 - port map(D => \data_0_1[10]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0[10]\); - - \un1_r.w.s.cwp_1_SUM2_0_0\ : XOR2 - port map(A => \cwp[2]\, B => et_RNI1BRF2, Y => SUM2_0_0); - - \r.x.ctrl.inst_RNITM3O1[19]\ : OR2B - port map(A => y_0_sqmuxa_1_1, B => y_0_sqmuxa_1_2, Y => - y_0_sqmuxa_1); - - \r.e.jmpl_RNITN6O_0\ : NOR3A - port map(A => \ex_shcnt_1[0]\, B => jmpl, C => - aluresult_1_sqmuxa_0_0, Y => aluresult_2_sqmuxa_0); - - \r.a.ctrl.inst_RNIM82S[21]\ : OA1C - port map(A => \inst_2[21]\, B => \inst_2[19]\, C => N_518, - Y => N_334); - - \r.x.ctrl.inst_RNI50723[30]\ : OA1 - port map(A => y6, B => y11, C => y15, Y => y6_2); - - \r.m.result_RNO[29]\ : MX2 - port map(A => \aluresult[29]\, B => \op1[29]\, S => - un17_casaen_0_2, Y => \eres2[29]\); - - \r.e.op1[24]\ : DFN1E0 - port map(D => \aop1[24]\, CLK => lclk_c, E => holdn, Q => - \op1[24]\); - - \r.a.ctrl.inst_RNIBO0L[22]\ : NOR2 - port map(A => \inst[22]\, B => N_201, Y => N_351_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I137_Y_0 : MIN3 - port map(A => \op2[9]\, B => \un1_iu0_6[9]\, C => N421_0, Y - => ADD_33x33_fast_I137_Y_0_0); - - \r.d.pv_RNIH9E08\ : OR2A - port map(A => un2_exbpmiss_0, B => ra_bpannul_1, Y => - un25_exbpmiss); - - \r.e.op2_RNO[12]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[12]\, Y => N_296); - - \r.d.inst_0_RNI7EVG1[30]\ : AOI1B - port map(A => de_fins_hold_1_2, B => N_3832, C => - un5_ldlock, Y => ldlock_2_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I119_Y : AO1 - port map(A => N520_1, B => N517_0, C => N516_0, Y => N582); - - \r.e.shcnt_RNIHQ03B[2]\ : MX2C - port map(A => \shiftin_11[15]\, B => \shiftin_11[11]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[11]\); - - \r.d.annul_RNI0N4LO3\ : OR2B - port map(A => I_20, B => annul_RNIVCQHS1, Y => N_6618); - - un6_ex_add_res_d2_ADD_33x33_fast_I203_Y : OR2 - port map(A => N606_2, B => I203_un1_Y_0, Y => N672); - - \r.f.pc_RNO_3[25]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[25]\, C => - \xc_trap_address_m[25]\, Y => \pc_1_iv_0[25]\); - - \r.e.aluop_RNII15D6[0]\ : OR2A - port map(A => aluresult_3_sqmuxa, B => \logicout[23]\, Y - => \aluop_RNII15D6[0]\); - - \comb.un6_xc_exception_RNI9HMBS5\ : OR3C - port map(A => \xc_trap_address_m[2]\, B => - \un6_fe_npc_m[0]\, C => \npc_iv_3[2]\, Y => rpc_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I52_Y : OA1A - port map(A => \data_0_2[20]\, B => \un1_iu0_6[20]\, C => - N461, Y => N511_0); - - \r.f.pc_RNO_5[27]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[27]\, Y => \xc_trap_address_m[27]\); - - \r.w.result[7]\ : DFN1E0 - port map(D => \wdata[7]\, CLK => lclk_c, E => holdn, Q => - \result[7]\); - - \r.m.y_RNO_1[8]\ : AOI1B - port map(A => \y[8]\, B => y08, C => \y_m_2[9]\, Y => - \y_iv_0[8]\); - - \r.d.cnt_RNO_0[1]\ : OR2 - port map(A => cnt_3_sqmuxa_0, B => annul_4, Y => - cnt_3_sqmuxa); - - \r.x.data_0_RNO_2[14]\ : NOR2A - port map(A => \data_0[14]\, B => ld_3, Y => \data_0_m[14]\); - - \r.d.annul\ : DFN1E0 - port map(D => annul_4, CLK => lclk_c, E => holdn, Q => - annul_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_un1_Y_0 : NOR2A - port map(A => N627, B => N643, Y => - ADD_33x33_fast_I260_un1_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I196_Y : NOR2 - port map(A => N607_1, B => N599_0, Y => N665_0); - - \r.d.inull_RNIIH9QT_0\ : OR2 - port map(A => \de_hold_pc_1\, B => holdn, Y => N_6763_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I259_Y_1 : NOR3C - port map(A => I33_un1_Y, B => N487_0, C => I95_un1_Y_0, Y - => ADD_33x33_fast_I259_Y_1_0); - - \r.d.pc_RNIMRAA4[2]\ : MX2 - port map(A => \dpc[2]\, B => \fpc[2]\, S => \ra_bpmiss_1_0\, - Y => N_3879); - - \r.x.data_0_RNO[2]\ : OR3C - port map(A => \dco_m_i[114]\, B => \data_0_1_1_iv_1[2]\, C - => \dco_m_i[98]\, Y => \data_0_1[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I149_Y\ : NOR2B - port map(A => N523, B => N515, Y => N575); - - \r.e.op2_RNO_0[22]\ : OR3C - port map(A => \op1_m_i[22]\, B => \d_1_iv_3[22]\, C => - \aluresult_m_i[22]\, Y => \d_1[22]\); - - \r.a.ctrl.inst_RNIJ02L[19]\ : OR2A - port map(A => \inst_2[19]\, B => N_518, Y => - \inst_RNIJ02L[19]\); - - \r.m.dci.asi_RNO[4]\ : NOR2B - port map(A => \inst_0[23]\, B => \inst_1[9]\, Y => \asi[4]\); - - \r.d.pc_RNO[15]\ : MX2 - port map(A => \fpc[15]\, B => \dpc[15]\, S => N_6763_i_0, Y - => \pc_RNO[15]\); - - \r.x.data_0_RNO_1[24]\ : OR2A - port map(A => \data_0[24]\, B => ld_3, Y => - \data_0_m_i[24]\); - - \r.e.shleft_1_RNI9JBG\ : NOR2A - port map(A => \un1_iu0_6[5]\, B => shleft_1, Y => - shleft_1_RNI9JBG); - - \comb.branch_address.tmp_ADD_30x30_fast_I72_Y_0_a3\ : NOR3C - port map(A => \dpc[8]\, B => \inst_0[6]\, C => N380, Y => - N_44); - - \r.a.ctrl.inst[14]\ : DFN1E0 - port map(D => \inst_0[14]\, CLK => lclk_c, E => holdn, Q - => \inst_1[14]\); - - \r.e.jmpl_RNI4QHFF2\ : OR3C - port map(A => \aluresult_1_iv_8[7]\, B => - \shiftin_17_m_0[7]\, C => ldbp2_0_RNIKEHUF, Y => - \aluresult[7]\); - - \r.a.wovf_RNIO7N5\ : OR2 - port map(A => wunf, B => wovf, Y => \tt_4[3]\); - - \r.e.op2[22]\ : DFN1E0 - port map(D => N_306, CLK => lclk_c, E => holdn, Q => - \op2[22]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I24_G0N : NOR2B - port map(A => \op2[23]\, B => \un1_iu0_6[23]\, Y => N466); - - \r.x.data_0_RNO_2[13]\ : NOR2A - port map(A => data_0_29, B => rdata_5_sqmuxa, Y => - \dco_m_0[125]\); - - \r.e.shleft_1_RNIABBQ1\ : MX2A - port map(A => \shiftin_5[20]\, B => shleft_1_RNI5FBG, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[4]\); - - \r.x.ctrl.rett_RNO\ : NOR2A - port map(A => rett, B => annul_5, Y => rett_1_1); - - \r.e.ldbp2_2_RNICBJHB3\ : OR2A - port map(A => \eaddress[21]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[22]\); - - \r.e.ldbp2_2_RNI7G0C6\ : OR2 - port map(A => aluresult_0_sqmuxa, B => \eaddress[3]\, Y => - ldbp2_2_RNI7G0C6); - - \r.x.data_0_RNO_1[23]\ : NOR2A - port map(A => \data_0[23]\, B => ld_0_0, Y => - \data_0_m[23]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I57_Y : AO13 - port map(A => N448, B => \un1_iu0_6[18]\, C => - \data_0_0[18]\, Y => N516); - - un6_fe_npc_I_111 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I271_Y_0 : AOI1 - port map(A => N664_0, B => N649_0, C => N648, Y => - ADD_33x33_fast_I271_Y_0_1); - - \r.e.ctrl.inst_RNIV42L[22]\ : NOR3C - port map(A => \inst_1[22]\, B => \inst_0[23]\, C => - \inst[19]\, Y => jump_1_sqmuxa_1_1); - - \r.a.ctrl.inst_RNI4P3H1[24]\ : MX2 - port map(A => illegal_inst35_4, B => \inst_1[24]\, S => - N_207, Y => N_263); - - \r.a.ctrl.inst_RNIB8549_0[30]\ : NOR3C - port map(A => N_451, B => \aop2_i_o2_2[0]\, C => N_452, Y - => N_6697_i_0_0); - - \r.e.op2_RNO_1[25]\ : OR2B - port map(A => \op1[25]\, B => un14_casaen_s1, Y => - \op1_m_i[25]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I261_Y_0\ : XOR2 - port map(A => N358, B => ADD_30x30_fast_I261_Y_0_0, Y => - \tmp[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I297_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[6]\, B => \data_0[6]\, Y => - \un6_ex_add_res_s2_1[7]\); - - \r.a.ctrl.inst[22]\ : DFN1E0 - port map(D => \inst_0_0[22]\, CLK => lclk_c, E => holdn, Q - => \inst[22]\); - - \r.x.rstate_0_RNID9182[0]\ : MX2C - port map(A => N_3400, B => \xc_result[9]\, S => - \rstate_0[0]\, Y => \wdata[9]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I263_Y : NAND2 - port map(A => I263_un1_Y, B => ADD_33x33_fast_I263_Y_1, Y - => N772); - - \r.x.rstate_0_RNIN5N82[0]\ : MX2C - port map(A => N_3393, B => \xc_result[2]\, S => - \rstate_0[0]\, Y => \wdata[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I145_Y : AO1 - port map(A => N546, B => N543_0, C => - ADD_33x33_fast_I145_Y_0_0, Y => N608); - - \r.w.s.y[25]\ : DFN1E0 - port map(D => N_3789, CLK => lclk_c, E => N_6922_i, Q => - \y[25]\); - - \r.x.data_0_RNO_2[7]\ : OR2B - port map(A => N_3456, B => data_0_7, Y => \dco_m_i[103]\); - - \r.f.pc_RNO_6[25]\ : MX2 - port map(A => \fpc[25]\, B => \eaddress[25]\, S => jump, Y - => N_4068); - - \r.e.ctrl.inst_RNILO0L[20]\ : OR2B - port map(A => \inst_1[20]\, B => N_3749_3, Y => N_3755); - - \r.m.result_0_RNIUK0I3[3]\ : NOR3C - port map(A => \d_iv_0[3]\, B => \result_m_0[3]\, C => - \rfo_m[3]\, Y => \d_iv_2[3]\); - - \r.e.op2_RNO_4[19]\ : OA1A - port map(A => \maddress[19]\, B => d27_0, C => - \cpi_m_i[371]\, Y => \d_1_iv_1[19]\); - - \r.e.shleft_0_RNIVOHP\ : OR2A - port map(A => \un1_iu0_6[23]\, B => shleft_0, Y => - \shiftin_5[23]\); - - \r.m.result_RNIUO4D3[19]\ : NOR3C - port map(A => \d_iv_0[19]\, B => \result_m_0[19]\, C => - \rfo_m[19]\, Y => \d_iv_2[19]\); - - \r.e.jmpl_RNIHHBJU\ : OR2B - port map(A => \shiftin_17[29]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[29]\); - - \r.e.invop2_0_RNIJ6B541\ : MX2C - port map(A => \un6_ex_add_res_s2[17]\, B => - \un6_ex_add_res_s0[17]\, S => invop2_0, Y => N_6563); - - \r.m.dci.size_RNO[1]\ : AO1C - port map(A => \inst[19]\, B => N_3755, C => \size_1[1]\, Y - => \size[1]\); - - \r.w.result[5]\ : DFN1E0 - port map(D => \wdata[5]\, CLK => lclk_c, E => holdn, Q => - \result[5]\); - - \r.e.op2_RNO_0[5]\ : OR3C - port map(A => \op1_m_i[5]\, B => \d_1_iv_3[5]\, C => - \aluresult_m_i[5]\, Y => \d_1[5]\); - - \r.e.ctrl.pc[18]\ : DFN1E0 - port map(D => \pc[18]\, CLK => lclk_c, E => holdn, Q => - \pc_0[18]\); - - \r.d.inst_0_RNIRPAV1[29]\ : NOR3A - port map(A => \rs1[4]\, B => \un3_de_ren1[92]\, C => - \rs1_iv_i_0[0]\, Y => rs1_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I17_P0N : OR3A - port map(A => \data_0[16]\, B => \op1[16]\, C => ldbp1_4, Y - => N446); - - \r.f.pc_RNO_0[22]\ : NAND2 - port map(A => \tmp[22]\, B => un2_rstn_5_0, Y => - \tmp_m[22]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I270_Y_0\ : XOR2 - port map(A => N738, B => ADD_30x30_fast_I270_Y_0_0, Y => - \tmp[12]\); - - \r.m.ctrl.rd_RNIM0A51[4]\ : XA1A - port map(A => \un3_de_ren1[95]\, B => \rd[4]\, C => wreg_4, - Y => wreg_1_0_0); - - \r.e.op2_RNO_8[23]\ : OR2A - port map(A => \maddress[23]\, B => d27, Y => - \result_m_i_0[23]\); - - \r.e.op1_RNO[20]\ : MX2C - port map(A => \d_i[20]\, B => \d_i[21]\, S => N_227_0, Y - => \aop1[20]\); - - \r.a.ctrl.inst[17]\ : DFN1E0 - port map(D => \inst_0[17]\, CLK => lclk_c, E => holdn, Q - => \inst_1[17]\); - - \r.e.op1_RNIC1UB[1]\ : OR2A - port map(A => un17_casaen_0_2, B => \op1[1]\, Y => - \op1_i_m[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I175_Y : NOR2 - port map(A => N578, B => I175_un1_Y, Y => N644_i); - - \r.f.pc_RNO_0[13]\ : NAND2 - port map(A => \tmp[13]\, B => \un2_rstn_5\, Y => - \tmp_m[13]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I2_G0N\ : OR2B - port map(A => \inst_0_RNI2NUM[2]\, B => \dpc[4]\, Y => N364); - - un6_ex_add_res_d2_ADD_33x33_fast_I54_Y : NOR2B - port map(A => N458_0, B => N455_1, Y => N513_2); - - \r.x.data_0_RNI3BS8[1]\ : XOR2 - port map(A => \data_0[1]\, B => invop2_1, Y => N_3305); - - \r.e.op2_RNO_3[17]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[17]\, Y => - \aluresult_m_i[17]\); - - \r.e.op2_RNO_2[11]\ : NOR3C - port map(A => \d_1_iv_1[11]\, B => \d_1_iv_0[11]\, C => - \rfo_m_i[43]\, Y => \d_1_iv_3[11]\); - - \r.a.rsel1_0_RNIF7LJ2[2]\ : OR2B - port map(A => data1(25), B => d11_0, Y => \rfo_m[25]\); - - \r.e.aluop_RNI30QD1[2]\ : XAI1 - port map(A => \un1_iu0_5[89]\, B => \aluop_1[2]\, C => - \un1_iu0_6[23]\, Y => N_3550); - - \r.d.pc[21]\ : DFN1 - port map(D => \pc_RNO[21]\, CLK => lclk_c, Q => \dpc[21]\); - - \r.x.result_RNIU4OE[29]\ : OR2B - port map(A => \un1_p0_6[381]\, B => d14, Y => - \cpi_m_0[381]\); - - \r.e.op2_RNO_6[22]\ : OR2B - port map(A => data2(22), B => d25, Y => \rfo_m_i[54]\); - - \r.w.s.wim_RNI3N5S3[1]\ : NOR2B - port map(A => \wim_m[1]\, B => \ex_op2_m[1]\, Y => - \aluresult_2_iv_0[1]\); - - \r.e.ctrl.inst_RNIM53A1[21]\ : NOR3A - port map(A => jump_0_sqmuxa_1_0, B => N_3749_1, C => - N_3749_2, Y => jump_0_sqmuxa_1_2); - - \r.a.ctrl.wicc_RNI0ERB\ : OR2 - port map(A => wicc_2, B => wicc_0, Y => not_valid); - - \r.e.shleft_0_RNI8THM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[22]\, S => - shleft_0, Y => \shiftin_5[53]\); - - \r.a.rsel1_RNIEECQ18[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[30]\, Y - => \aluresult_m_0[30]\); - - \r.x.ctrl.pc_RNITVH61[13]\ : MX2C - port map(A => \un1_p0_6[365]\, B => \pc_0[13]\, S => - s_3_sqmuxa, Y => N_3404); - - \r.a.ctrl.inst_RNIF8Q8[28]\ : XOR2 - port map(A => \inst_1[28]\, B => \icc[3]\, Y => branch_7); - - \r.e.op1_RNIK3C4[9]\ : MX2 - port map(A => \op1[9]\, B => \data_0[9]\, S => ldbp1, Y => - \un1_iu0_6[9]\); - - \r.d.pv_RNIJARPF\ : NOR2B - port map(A => un5_exbpmiss_i_0, B => un25_exbpmiss, Y => - un1_annul_next_1_sqmuxa_3_0); - - \r.d.inst_0_RNIKI1A[20]\ : OR3 - port map(A => N_67, B => un52_casaen, C => N_122_1, Y => - rd_0_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I112_Y : NOR2B - port map(A => N513_1, B => N509, Y => N575_1); - - \r.e.ctrl.pc_RNIESTN2[25]\ : AOI1 - port map(A => \pc[25]\, B => jmpl_0, C => \aluresult_6[31]\, - Y => \aluresult_1_iv_1[25]\); - - \r.a.rsel2_0_RNIFA4D_1[0]\ : NOR2A - port map(A => d26, B => un17_casaen_0_2, Y => - un14_casaen_s0); - - \r.d.pc[4]\ : DFN1 - port map(D => \pc_RNO[4]\, CLK => lclk_c, Q => \dpc[4]\); - - \r.e.op2_RNIO2OP[12]\ : MX2 - port map(A => \op2[12]\, B => N_4259, S => ldbp2_1, Y => - \un1_iu0_5[78]\); - - \r.a.imm_RNO[27]\ : MX2 - port map(A => \inst_0[17]\, B => \inst_0[12]\, S => - call_hold5, Y => \un3_de_ren1[145]\); - - \r.m.ctrl.cnt[0]\ : DFN1E0 - port map(D => \cnt[0]\, CLK => lclk_c, E => holdn, Q => - \cnt_0[0]\); - - \r.a.rsel1[1]\ : DFN1E0 - port map(D => N_4021, CLK => lclk_c, E => holdn, Q => - \rsel1[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I266_Y_0_a3_1 : AND2 - port map(A => N464_0, B => N467_0, Y => N_74_1); - - \r.m.result_RNI0TAI[31]\ : NOR3C - port map(A => \result_m_0[31]\, B => \cpi_m_0[383]\, C => - \result_m_0_0[31]\, Y => \d_iv_1[31]\); - - \r.a.rfa2[6]\ : DFN1E0 - port map(D => \un3_de_ren1[105]\, CLK => lclk_c, E => holdn, - Q => \rfa2[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I304_Y_0 : XNOR3 - port map(A => \data_0[13]\, B => \un1_iu0_6[13]\, C => N802, - Y => \un6_ex_add_res_s0[14]\); - - \r.x.data_0[25]\ : DFN1E0 - port map(D => \data_0_1[25]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[25]\); - - \r.e.op1_RNIMB1O6[27]\ : NOR3C - port map(A => \ex_op1_i_m[27]\, B => \op1_RNI4VNF[27]\, C - => \bpdata_i_m[27]\, Y => \edata2_iv_1[27]\); - - \r.e.op1[23]\ : DFN1E0 - port map(D => \aop1[23]\, CLK => lclk_c, E => holdn, Q => - \op1[23]\); - - \r.w.s.tba_RNI54CA1[4]\ : OR2B - port map(A => \tba[4]\, B => aluresult_12_sqmuxa, Y => - \tba_m[4]\); - - \r.e.jmpl_RNIUQG9G2\ : AOI1B - port map(A => \shiftin_17[23]\, B => aluresult_2_sqmuxa_0, - C => \aluresult_1_iv_8[23]\, Y => \aluresult_1_iv_9[23]\); - - \r.e.op1_RNIVU4RB[22]\ : NOR3 - port map(A => \edata2_0_iv_0[22]\, B => \ex_op1_i_m[22]\, C - => \bpdata_i_m_1[6]\, Y => edata2_0_iv(22)); - - \r.m.icc_RNI87QF4[0]\ : NOR3C - port map(A => \icc_m[0]\, B => \aluresult_1_iv_0[20]\, C - => \tba_m[8]\, Y => \aluresult_1_iv_4[20]\); - - \r.e.shleft_RNI4PSU\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[9]\, S => shleft, - Y => \shiftin_5[40]\); - - \r.d.inst_0_RNI66J4_0[23]\ : NOR3C - port map(A => \inst_0_0[23]\, B => \inst_0_0[24]\, C => - \inst_0_0[22]\, Y => N_142); - - \r.x.ctrl.pc[20]\ : DFN1E0 - port map(D => \pc_3[20]\, CLK => lclk_c, E => holdn, Q => - \pc_2[20]\); - - \r.d.inst_0_RNIA869[19]\ : OR2B - port map(A => icc_check8_1, B => N_3518_1, Y => icc_check8); - - \r.e.op1_RNIEHID[29]\ : MX2 - port map(A => \op1[29]\, B => \data_0_0[29]\, S => ldbp1, Y - => \un1_iu0_6[29]\); - - \r.e.ctrl.rd_RNI1FQ3S[6]\ : OR2 - port map(A => un1_rs1, B => N_3948, Y => \osel_i_a3_0[0]\); - - \r.e.op2_RNISLAE1[2]\ : OR2B - port map(A => \un1_iu0_5[68]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I33_un1_Y : NAND2 - port map(A => N484, B => N488, Y => I33_un1_Y); - - un6_ex_add_res_d0_ADD_33x33_fast_I269_Y : NAND2 - port map(A => I269_un1_Y_i, B => ADD_33x33_fast_I269_Y_0, Y - => N784); - - \r.x.ctrl.pc[31]\ : DFN1E0 - port map(D => \pc_3[31]\, CLK => lclk_c, E => holdn, Q => - \pc_2[31]\); - - \r.e.op2_RNO_4[16]\ : OA1A - port map(A => \maddress[16]\, B => d27_0, C => - \cpi_m_i[368]\, Y => \d_1_iv_1[16]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I34_Y\ : MAJ3 - port map(A => \dpc[28]\, B => \inst_0_1[28]\, C => N433, Y - => N451); - - \r.x.ctrl.rd_RNIBSGO[7]\ : NOR2B - port map(A => \rd_2[7]\, B => N_6357, Y => waddr(7)); - - \r.m.result_RNIUVO1[14]\ : OR2B - port map(A => d13, B => \maddress[14]\, Y => - \result_m_0[14]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I156_Y : NOR3C - port map(A => N493, B => N497, C => N567_0, Y => N625_0); - - \r.e.ldbp2_1_RNIQS1LJ1\ : OR2B - port map(A => annul_RNI5L7FE1, B => ldbp2_1_RNIL7Q55, Y => - \un6_ex_add_res_m[3]\); - - \r.m.y_RNI6APD2[0]\ : AOI1B - port map(A => \op2_RNI59C6[0]\, B => aluresult_7_sqmuxa, C - => \y_m_0[0]\, Y => \aluresult_2_iv_1[0]\); - - \r.e.ctrl.tt[5]\ : DFN1E0 - port map(D => \tt_2[5]\, CLK => lclk_c, E => holdn, Q => - \tt_3[5]\); - - \r.d.pc_RNO[7]\ : MX2 - port map(A => \fpc[7]\, B => \dpc[7]\, S => N_6763_i, Y => - \pc_RNO[7]\); - - \r.e.shleft_RNIPEFC1\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[17]\, S => - shleft, Y => \shiftin_5[48]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I136_Y : NOR2B - port map(A => N537_2, B => N533_1, Y => N599_2); - - \r.x.data_0_RNO_4[7]\ : OR2A - port map(A => \data_0_2[7]\, B => ld_3, Y => - \data_0_m_i[7]\); - - \r.x.ctrl.rd_RNIJVH6[4]\ : XNOR2 - port map(A => \rd_2[4]\, B => \rd_0[4]\, Y => rd_4_i_0); - - \r.e.ctrl.wreg\ : DFN1E0 - port map(D => wreg_1_10, CLK => lclk_c, E => holdn, Q => - wreg_7); - - \r.a.rsel2_0_RNIRR7232[0]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[2]\, Y => - \aluresult_m_i[2]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I81_un1_Y : NOR2B - port map(A => N416_1, B => N412_1, Y => I81_un1_Y); - - \r.e.jmpl_RNIEF4GN\ : OR2B - port map(A => \shiftin_17[11]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[11]\); - - \r.a.ctrl.cnt_RNIUBDQ4[0]\ : NOR3C - port map(A => N_360, B => \cnt_RNILD6A1[0]\, C => N_345, Y - => aluop_2_1_0_1); - - \r.e.ctrl.rd[2]\ : DFN1E0 - port map(D => \rd[2]\, CLK => lclk_c, E => holdn, Q => - \rd_1[2]\); - - \r.e.bp_RNO\ : NOR2B - port map(A => bp, B => \ra_bpmiss_1_0\, Y => bp_1_1); - - \r.a.rsel1_0_RNI4V53[2]\ : NOR2A - port map(A => N_484, B => \rsel1_0[2]\, Y => d13_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I60_Y : NOR2B - port map(A => N449_0, B => N446_1, Y => N519_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I316_Y_0_1 : XOR2 - port map(A => \data_0[25]\, B => \un1_iu0_6[25]\, Y => - \un6_ex_add_res_s2_1[26]\); - - \r.m.ctrl.pc[28]\ : DFN1E0 - port map(D => \pc_2[28]\, CLK => lclk_c, E => holdn, Q => - \pc_3[28]\); - - \r.e.ctrl.pc[20]\ : DFN1E0 - port map(D => \pc[20]\, CLK => lclk_c, E => holdn, Q => - \pc_0[20]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I244_un1_Y : NOR2 - port map(A => N674, B => N659_0, Y => I244_un1_Y); - - \r.e.jmpl_RNI5D4VT\ : OR2B - port map(A => \shiftin_17[27]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[27]\); - - \r.e.aluop_RNI402I6[0]\ : MX2C - port map(A => N_3573, B => N_3637, S => \aluop_1[0]\, Y => - \logicout[14]\); - - \r.d.inst_0_RNO[26]\ : NOR2B - port map(A => rst, B => N_4626, Y => \inst_0_RNO[26]\); - - \r.a.ctrl.wreg_RNI9KRTQ\ : NOR3C - port map(A => rfe_1_1, B => ldcheck1, C => rfe_1_2, Y => - rfe_1); - - \r.e.shleft_RNIS2381\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[28]\, S => - shleft, Y => \shiftin_5[59]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I28_P0N : OR2 - port map(A => \un1_iu0_6[27]\, B => \data_0[27]\, Y => N479); - - un6_ex_add_res_d0_ADD_33x33_fast_I268_Y : AO1 - port map(A => ADD_33x33_fast_I268_un1_Y_0_0, B => N674_1, C - => ADD_33x33_fast_I268_Y_0_1, Y => N782_1); - - \r.a.ctrl.inst_RNI9O0E[30]\ : OR2 - port map(A => \inst[30]\, B => \inst_1[24]\, Y => N_518); - - \r.d.pc_RNI66HB4[28]\ : MX2 - port map(A => \dpc[28]\, B => \fpc[28]\, S => ra_bpmiss_1, - Y => N_3905); - - \r.e.aluop_0_RNIST6R[2]\ : XA1 - port map(A => \un1_iu0_5[74]\, B => \aluop_0[2]\, C => - \un1_iu0_6[8]\, Y => N_3535); - - \r.d.inst_0[16]\ : DFN1 - port map(D => \inst_0_RNO[16]\, CLK => lclk_c, Q => - \inst_0[16]\); - - \comb.cwp_ctrl.ncwp_3_I_7\ : XNOR2 - port map(A => \inst_0[19]\, B => \cwp[1]\, Y => - \DWACT_ADD_CI_0_pog_array_0[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I122_Y : NOR3C - port map(A => N443_1, B => N440_1, C => N519_2, Y => N585_1); - - \r.f.pc_RNO_6[16]\ : MX2 - port map(A => \fpc[16]\, B => \eaddress[16]\, S => jump, Y - => N_4059); - - un6_ex_add_res_d2_ADD_33x33_fast_I318_Y_0_1 : XOR2 - port map(A => \data_0[27]\, B => \un1_iu0_6[27]\, Y => - \un6_ex_add_res_s2_1[28]\); - - \r.w.result[28]\ : DFN1E0 - port map(D => \wdata[28]\, CLK => lclk_c, E => holdn, Q => - \result[28]\); - - \r.m.y_RNO_3[10]\ : OR3A - port map(A => \y_2[10]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[10]\); - - \r.m.result_RNIREJ83[11]\ : NOR3C - port map(A => \d_iv_0[11]\, B => \result_m_0[11]\, C => - \rfo_m[11]\, Y => \d_iv_2[11]\); - - \r.a.rfa1_RNICHT01[3]\ : MX2 - port map(A => \un3_de_ren1[94]\, B => \rfa1[3]\, S => holdn, - Y => raddr1(3)); - - un6_ex_add_res_d2_ADD_33x33_fast_I295_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[4]\, B => \data_0[4]\, Y => - \un6_ex_add_res_s2_1[5]\); - - \r.e.shleft_1_RNI2UPK3\ : MX2 - port map(A => \shiftin_5[60]\, B => \shiftin_5[44]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[44]\); - - \r.x.laddr_RNI66ENI_0[0]\ : NOR2A - port map(A => \me_laddr_2[1]\, B => \me_laddr_2[0]\, Y => - rdata_2_sqmuxa_0); - - \r.m.result_RNIAJD4[22]\ : OR2B - port map(A => d13_0, B => \maddress[22]\, Y => - \result_m_0[22]\); - - \r.e.aluop_RNI4A334[1]\ : OR2B - port map(A => \bpdata[7]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[7]\); - - \r.a.et_RNINOBR1\ : OR3C - port map(A => N_256_i_0, B => illegal_inst_7_iv_2_0_a5_5_0, - C => N_6696, Y => N_444); - - un6_ex_add_res_d2_ADD_33x33_fast_I114_Y : NOR3C - port map(A => N458_0, B => N461_1, C => N_71_1, Y => N577_1); - - \r.w.s.y_RNO_1[24]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y_0[24]\, Y => N_367); - - \r.f.pc_RNO_2[17]\ : OR2B - port map(A => I_91, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[15]\); - - \un1_r.w.s.cwp_1_ANC1\ : OR3B - port map(A => \cwp[0]\, B => \cwp_0[1]\, C => - \rstate_RNIRDFU5[1]\, Y => ANC1); - - \r.x.data_0_RNO[9]\ : OR3 - port map(A => \dco_m_0[105]\, B => \data_0_1_0_iv_0[9]\, C - => \data_0_1_4[9]\, Y => \data_0_1[9]\); - - \r.w.s.icc[0]\ : DFN1E0 - port map(D => \icc_1[0]\, CLK => lclk_c, E => holdn, Q => - \icc[0]\); - - \r.m.ctrl.tt[2]\ : DFN1E0 - port map(D => \tt_3[2]\, CLK => lclk_c, E => holdn, Q => - \tt_2[2]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I264_Y_0_0\ : XOR2 - port map(A => \dpc[6]\, B => \inst_0_RNI4VUM[4]\, Y => - ADD_30x30_fast_I264_Y_0_0); - - \r.f.pc_RNO_1[14]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[14]\, C => m7_0, - Y => m7_1); - - \r.w.result[20]\ : DFN1E0 - port map(D => \wdata[20]\, CLK => lclk_c, E => holdn, Q => - \result_0[20]\); - - \r.e.op1_RNI2H3V15[17]\ : NOR3C - port map(A => \op1_m_0[17]\, B => \d_iv_2[17]\, C => - \aluresult_m_0[17]\, Y => \d_i[17]\); - - \r.w.result_RNIC0P1[18]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[18]\, Y - => \result_m_0_0[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I272_Y_0\ : XNOR2 - port map(A => N732_i, B => ADD_30x30_fast_I272_Y_0_0, Y => - \tmp[14]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I223_Y\ : AO1 - port map(A => N607, B => N358, C => N606, Y => N741); - - \r.m.ctrl.inst_RNI6E2S[19]\ : OR3A - port map(A => \inst_3[19]\, B => \inst_0[24]\, C => - trap_0_sqmuxa_3_2, Y => trap_0_sqmuxa_3_1); - - \r.e.jmpl_RNI2UJLU\ : OR2B - port map(A => \shiftin_17[28]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[28]\); - - \r.m.ctrl.ld_RNICKJJ\ : AO1 - port map(A => ld, B => d13_0, C => N_219, Y => ldbp); - - \r.d.inst_0_RNI62J4_0[23]\ : NOR3B - port map(A => \inst_0_0[23]\, B => \inst_0[20]\, C => - \inst_0[19]\, Y => icc_check_3_0_a3_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I23_G0N : AND2 - port map(A => \op2[22]\, B => \un1_iu0_6[22]\, Y => N463); - - \r.w.s.y[19]\ : DFN1E0 - port map(D => N_3783, CLK => lclk_c, E => N_6922_i_0, Q => - \y[19]\); - - \r.m.result[11]\ : DFN1E0 - port map(D => \eres2[11]\, CLK => lclk_c, E => holdn, Q => - \maddress[11]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I297_Y_0 : XOR3 - port map(A => \un1_iu0_6[6]\, B => \op2[6]\, C => N674_0, Y - => \un6_ex_add_res_s1[7]\); - - \r.w.s.tba[2]\ : DFN1E1 - port map(D => \result_0[14]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[2]\); - - \r.e.op2_RNO_7[28]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[380]\, - Y => \cpi_m_i[380]\); - - \r.m.ctrl.pc_RNI21M9[11]\ : MX2 - port map(A => \pc_1[11]\, B => \pc[11]\, S => \npc[1]\, Y - => N_3252); - - \r.m.ctrl.rd[3]\ : DFN1E0 - port map(D => \rd[3]\, CLK => lclk_c, E => holdn, Q => - \rd_0[3]\); - - \r.e.op2_RNO_0[13]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[13]\, C - => \d_1_iv_4[13]\, Y => \d_1[13]\); - - \r.e.op1_RNIT2NF[20]\ : NOR2A - port map(A => un17_casaen_0_2, B => \op1[20]\, Y => - \op1_i_m[20]\); - - \r.e.op2_RNO_5[15]\ : AOI1B - port map(A => \result[15]\, B => d31_0, C => \imm_m_i[15]\, - Y => \d_1_iv_0[15]\); - - \r.e.aluop_RNI99SC4[1]\ : NOR2A - port map(A => edata_2_sqmuxa, B => \bpdata[17]\, Y => - \bpdata_i_m[17]\); - - \r.e.alucin_RNI0313\ : XOR2 - port map(A => alucin, B => \data_0[0]\, Y => - \un6_ex_add_res_s0_0_0[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I81_Y : AO13 - port map(A => \un1_iu0_6[6]\, B => \data_0[6]\, C => N412_2, - Y => N540_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I28_G0N : NOR2B - port map(A => \un1_iu0_6[27]\, B => \data_0[27]\, Y => - N478_2); - - \comb.lock_gen.un1_icc_check5_RNO\ : NOR2A - port map(A => un1_icc_check5_1, B => imm9, Y => - un1_icc_check5_2); - - un6_ex_add_res_d2_ADD_33x33_fast_I22_G0N : OA1 - port map(A => \op1[21]\, B => ldbp1_4, C => \data_0[21]\, Y - => N460_2); - - \r.m.result_RNI64P1[29]\ : OR2B - port map(A => d13, B => \maddress[29]\, Y => - \result_m_0_0[29]\); - - \r.e.alusel_RNO_1[0]\ : NOR3C - port map(A => N_351, B => N_352, C => N_602, Y => - \alusel_i_0_1[0]\); - - \r.w.s.et_RNI4T46\ : NOR2B - port map(A => N_6337, B => rst, Y => G_9_0); - - \r.e.invop2_1_RNIDR3T73\ : MX2 - port map(A => \un6_ex_add_res_s2[32]\, B => - \un6_ex_add_res_s0[32]\, S => invop2_1, Y => N_6659); - - \r.m.dci.write_RNO\ : NOR3 - port map(A => N_3356_3, B => annul, C => write_3_tz, Y => - write); - - \r.x.ctrl.pc_RNIPL971[21]\ : MX2C - port map(A => \un1_p0_6[373]\, B => \pc_2[21]\, S => - s_3_sqmuxa, Y => N_3412); - - \r.e.aluop_RNIOSDKR[0]\ : AOI1B - port map(A => \logicout[31]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[31]\, Y => \aluresult_1_iv_7[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I105_un1_Y : NOR2B - port map(A => N506_1, B => N503, Y => I105_un1_Y); - - \r.e.op1_RNO[8]\ : MX2C - port map(A => \d_i[8]\, B => \d_i[9]\, S => N_227, Y => - \aop1[8]\); - - \r.x.ctrl.pc_RNI12A71[16]\ : MX2C - port map(A => \un1_p0_6[368]\, B => \pc_2[16]\, S => - s_3_sqmuxa, Y => N_3407); - - \r.e.alusel_RNO_3[1]\ : NOR3 - port map(A => N_487, B => N_492, C => \cnt_2[1]\, Y => - \alusel_i_0_a5_0_0[1]\); - - \r.e.op2_RNO_0[9]\ : AO1B - port map(A => un14_casaen_s0_0_1, B => \aluresult[9]\, C - => \d_1_iv_4[9]\, Y => \d_1[9]\); - - \r.a.ctrl.inst_RNI5H3O1[19]\ : NOR3A - port map(A => N_226, B => N_203, C => N_204, Y => N_227); - - \r.f.pc_RNI77A6U1[7]\ : OA1A - port map(A => annul_RNI5L7FE1, B => \eaddress[7]\, C => - \pc_m[7]\, Y => \npc_iv_1[7]\); - - \r.m.y_RNI62BTG[10]\ : NOR3C - port map(A => \bpdata_m_2[2]\, B => \aluresult_1_iv_3[10]\, - C => \aluresult_1_iv_4[10]\, Y => \aluresult_1_iv_6[10]\); - - \r.m.ctrl.rd[5]\ : DFN1E0 - port map(D => \rd[5]\, CLK => lclk_c, E => holdn, Q => - \rd_2[5]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I125_Y\ : OR2B - port map(A => ADD_30x30_fast_I125_Y_0, B => N486, Y => N545); - - \r.a.rsel1_0_RNIR48M2[2]\ : OR2B - port map(A => data1(3), B => d11_0, Y => \rfo_m[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I292_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[2]\, B => N552_1, Y => - \un6_ex_add_res_s2[2]\); - - \r.w.result_RNIGTB4[9]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[9]\, Y - => \result_m_0[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I172_Y\ : OR2 - port map(A => N538_2, B => I172_un1_Y, Y => N598); - - \r.e.aluop_0_RNIN7K85[0]\ : MX2C - port map(A => N_3587, B => N_3651, S => \aluop_0[0]\, Y => - \logicout[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I273_un1_Y_0 : NOR3A - port map(A => N552_1, B => N603_i, C => N611, Y => - ADD_33x33_fast_I273_un1_Y_0_1); - - \r.x.y[9]\ : DFN1E0 - port map(D => \y_1[9]\, CLK => lclk_c, E => holdn, Q => - \y_2[9]\); - - \r.a.ctrl.rd[5]\ : DFN1E0 - port map(D => N_35, CLK => lclk_c, E => holdn, Q => - \rd_1[5]\); - - \r.m.ctrl.rd_RNIOM7Q[2]\ : XNOR2 - port map(A => \inst_0_RNI2NUM[2]\, B => \rd_0[2]\, Y => - un1_de_ren1_1_2_i_0); - - \r.a.ctrl.pc_RNI7OK0C[2]\ : MX2 - port map(A => \pc[2]\, B => N_3879, S => ex_bpmiss_1_0, Y - => \fe_pc[2]\); - - \r.m.ctrl.inst_RNIVK0E[21]\ : OR2 - port map(A => \inst_2[22]\, B => \inst[21]\, Y => - trap_0_sqmuxa_2_2); - - \r.f.pc_RNILIC62[9]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[9]\, Y => \xc_trap_address_m[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I25_G0N\ : NOR2B - port map(A => \inst_0_1[27]\, B => \dpc[27]\, Y => N433); - - \r.x.data_0_RNICF9E[15]\ : XOR2 - port map(A => \data_0_2[15]\, B => invop2_1, Y => N_4262); - - \r.m.y_RNO_0[9]\ : NOR3C - port map(A => \y_m[10]\, B => \y_m_0[9]\, C => \y_iv_1[9]\, - Y => \y_iv_2[9]\); - - \r.e.aluop_0_RNIGGO4K[0]\ : NOR3C - port map(A => \aluresult_1_iv_5[8]\, B => - \aluresult_1_iv_4[8]\, C => \logicout_m_0[8]\, Y => - \aluresult_1_iv_7[8]\); - - \r.x.mexc\ : DFN1 - port map(D => mexc_RNO, CLK => lclk_c, Q => mexc_0); - - \r.d.inst_0_RNIB423[26]\ : OR2 - port map(A => \inst_0[27]\, B => \inst_0[26]\, Y => N_122_2); - - \r.w.result_RNIGGFF[0]\ : AOI1B - port map(A => \un1_p0_6[352]\, B => d14, C => - \result_m_0_0[0]\, Y => \d_iv_0[0]\); - - \r.m.result[9]\ : DFN1E0 - port map(D => \eres2[9]\, CLK => lclk_c, E => holdn, Q => - \maddress[9]\); - - \r.e.jmpl_RNIN2MUS\ : OR2B - port map(A => \shiftin_17[24]\, B => aluresult_1_sqmuxa, Y - => \shiftin_17_m[24]\); - - \r.d.inst_0[28]\ : DFN1 - port map(D => \inst_0_RNO[28]\, CLK => lclk_c, Q => - \inst_0[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I129_Y_0 : AO18 - port map(A => \un1_iu0_6[13]\, B => N433_1, C => - \data_0[13]\, Y => ADD_33x33_fast_I129_Y_0_0); - - un2_rstn_5_RNIUJPE8 : NAND2 - port map(A => \tmp[7]\, B => \un2_rstn_5\, Y => \tmp_m[7]\); - - \r.e.shleft_RNI2OCF1\ : MX2C - port map(A => \shiftin_5[29]\, B => \shiftin_5[13]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[13]\); - - \r.m.ctrl.annul_RNO\ : OR2 - port map(A => annul, B => \un1_p0_6[0]\, Y => annul_1_1); - - \r.e.aluop_RNIKFE1O[0]\ : AOI1B - port map(A => \logicout[10]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[10]\, Y => \aluresult_1_iv_7[10]\); - - \r.x.ctrl.pc[4]\ : DFN1E0 - port map(D => \pc_3[4]\, CLK => lclk_c, E => holdn, Q => - \pc_2[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I24_P0N : AO1A - port map(A => ldbp1, B => \op1[23]\, C => \data_0[23]\, Y - => N467); - - \r.e.invop2_RNI9V6D1\ : MX2C - port map(A => \un6_ex_add_res_s2[2]\, B => - \un6_ex_add_res_s0[2]\, S => invop2, Y => N_6641); - - \r.d.inst_0_RNI73A31[13]\ : OR3C - port map(A => N_127, B => N_126, C => N_128, Y => imm); - - \r.x.laddr_RNIUO2VN1[1]\ : OR2 - port map(A => rdata_6_sqmuxa, B => rdata_4_sqmuxa, Y => - N_3473); - - \r.x.ctrl.pc_RNI5HR31[3]\ : MX2C - port map(A => \un1_p0_6[355]\, B => \pc_2[3]\, S => - s_3_sqmuxa, Y => N_3394); - - un6_ex_add_res_d2_ADD_33x33_fast_I2_P0N : AO1A - port map(A => ldbp1_0, B => \op1[1]\, C => \data_0[1]\, Y - => N401_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I55_Y_0_o3 : AO1 - port map(A => N455_0, B => N451_0, C => N454_0, Y => N514_0); - - \r.w.result[26]\ : DFN1E0 - port map(D => \wdata[26]\, CLK => lclk_c, E => holdn, Q => - \result_0[26]\); - - \r.e.shleft_0_RNIATHM1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[31]\, S => - shleft_0, Y => \shiftin_5[62]\); - - \r.a.rsel1_RNIK8V804[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[15]\, Y => - \aluresult_m_0[15]\); - - \r.e.aluop_0_RNIH2S72[0]\ : NOR3A - port map(A => aluresult_13_sqmuxa_3_0, B => miscout140_1, C - => \aluop_0[0]\, Y => aluresult_13_sqmuxa); - - \r.x.data_0_RNI1P5I1[3]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[3]\, Y => - \ex_op1_i_m[3]\); - - \r.m.result_RNO[4]\ : MX2 - port map(A => \aluresult[4]\, B => \op1[4]\, S => - \un17_casaen_0_0\, Y => \eres2[4]\); - - \r.w.result_RNILKV6[3]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[3]\, - Y => \result_m_0_0[3]\); - - \r.w.s.y_RNO_1[27]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y[27]\, Y => N_409); - - \r.e.op2_RNI0OMB1_0[14]\ : OR2 - port map(A => \un1_iu0_6[14]\, B => \un1_iu0_5[80]\, Y => - \logicout_3[14]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I62_Y : OR2B - port map(A => N446_1, B => N443_1, Y => N521_0); - - \r.w.result_RNI4C5J[15]\ : AOI1B - port map(A => \un1_p0_6[367]\, B => d14_0, C => - \result_m_0_0[15]\, Y => \d_iv_0[15]\); - - \r.w.s.wim[7]\ : DFN1E0 - port map(D => \wim_1[7]\, CLK => lclk_c, E => holdn, Q => - \wim[7]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I246_Y_0_a3 : NOR2B - port map(A => N808_1, B => N431_0, Y => - ADD_33x33_fast_I246_Y_0_a3); - - un23_ra_I_13 : XOR2 - port map(A => \cwp[1]\, B => \DWACT_ADD_CI_0_TMP_1[0]\, Y - => I_13_2); - - \r.w.s.pil[1]\ : DFN1E0 - port map(D => \result_0[9]\, CLK => lclk_c, E => N_6699, Q - => \pil[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_un1_Y_0 : AND2 - port map(A => N653, B => N637, Y => - ADD_33x33_fast_I265_un1_Y_0); - - \r.m.y_RNI52BV2[29]\ : AOI1B - port map(A => \y[29]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[29]\, Y => \aluresult_1_iv_0[29]\); - - \r.e.op2_RNO_7[12]\ : NOR2B - port map(A => \result_m_i_0[12]\, B => \cpi_m_i[364]\, Y - => \d_1_iv_1[12]\); - - \r.e.op2_RNO[29]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[29]\, Y => N_313); - - \r.f.pc[3]\ : DFN1E0 - port map(D => \pc_1[3]\, CLK => lclk_c, E => holdn, Q => - \fpc[3]\); - - \r.e.aluop_0_RNINF093[1]\ : MX2C - port map(A => \logicout_4[13]\, B => N_6898, S => N_6866_i, - Y => N_3636); - - \r.a.ctrl.rd_RNO[2]\ : OR2A - port map(A => N_85, B => \inst_0[27]\, Y => \rd_2[2]\); - - \r.m.casa_RNI8BU9_1\ : NOR2A - port map(A => casa, B => N_3355_1, Y => un17_casaen_0_2); - - un6_ex_add_res_d0_ADD_33x33_fast_I273_Y_0 : AO1 - port map(A => ADD_33x33_fast_I273_un1_Y_0, B => N653_0, C - => N652_1, Y => ADD_33x33_fast_I273_Y_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I19_P0N : OR2 - port map(A => \un1_iu0_6[18]\, B => \op2[18]\, Y => N452_0); - - \r.x.ctrl.wy_RNI4SI14\ : OR2 - port map(A => wy_RNILF1N3, B => holdn, Y => N_6922_i); - - \r.a.imm_RNO[7]\ : NOR2B - port map(A => \inst_0[7]\, B => call_hold5, Y => - \un3_de_ren1[125]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y : NAND2 - port map(A => I260_un1_Y_i, B => ADD_33x33_fast_I260_Y_3, Y - => N766); - - un6_ex_add_res_d2_ADD_33x33_fast_I74_Y : OA1 - port map(A => \data_0[10]\, B => \un1_iu0_6[10]\, C => - N425_2, Y => N533_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I108_Y : NOR2B - port map(A => N509_0, B => N505_0, Y => N571); - - \r.x.result_RNIRK6E[24]\ : MX2 - port map(A => \result_0[24]\, B => \data_0[24]\, S => ld_4, - Y => \un1_p0_6[376]\); - - \r.d.inst_0_RNI3KR23[16]\ : NOR3A - port map(A => rs1_2, B => \un3_de_ren1[94]\, C => - \un3_de_ren1[93]\, Y => rs1); - - \comb.branch_address.tmp_ADD_30x30_fast_I99_Y\ : NOR2B - port map(A => N464_1, B => N460_0, Y => N519); - - \r.e.shcnt_RNI06RGQ[1]\ : MX2C - port map(A => \shiftin_14[22]\, B => \shiftin_14[20]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[20]\); - - \r.m.ctrl.trap_RNI1J7731\ : OR2B - port map(A => tt_0_sqmuxa, B => trap_0_sqmuxa_7, Y => - tt_1_sqmuxa_1); - - \r.e.shcnt_RNIFVRIB[2]\ : MX2C - port map(A => \shiftin_11[18]\, B => \shiftin_11[14]\, S - => \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[14]\); - - \r.d.annul_RNIF0HMG4\ : OR2B - port map(A => I_31, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[6]\); - - \r.f.pc_RNIF1DAA7[9]\ : NOR2B - port map(A => \tmp_m[9]\, B => \pc_4_m[9]\, Y => - \npc_iv_0[9]\); - - \r.e.op2_RNI8NVJ[23]\ : MX2 - port map(A => \op2[23]\, B => N_4270, S => ldbp2_2, Y => - \un1_iu0_5[89]\); - - \r.d.inst_0_RNO[8]\ : NOR2B - port map(A => rst, B => N_4608, Y => \inst_0_RNO[8]\); - - \r.x.result[24]\ : DFN1E0 - port map(D => \maddress[24]\, CLK => lclk_c, E => holdn, Q - => \result_0[24]\); - - \r.m.ctrl.rd_RNI7V2V[0]\ : XNOR2 - port map(A => \rs1_iv_i_0[0]\, B => \rd_1[0]\, Y => - un2_rs1_2_0_i_0); - - \r.e.shcnt_RNIOVDVE[2]\ : MX2C - port map(A => \shiftin_11[34]\, B => \shiftin_11[30]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[30]\); - - \r.e.op2_RNIBHPA_0[9]\ : OR2 - port map(A => \un1_iu0_6[9]\, B => \un1_iu0_5[75]\, Y => - \logicout_3[9]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I296_Y_0 : XOR3 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N676, - Y => \un6_ex_add_res_s2[6]\); - - \r.d.pc_RNO[14]\ : MX2 - port map(A => \fpc[14]\, B => \dpc[14]\, S => N_6763_i, Y - => \pc_RNO[14]\); - - \r.d.pv_RNI0R6T91\ : AO1D - port map(A => un6_rabpmiss_2, B => un13_exbpmiss_0, C => - \de_hold_pc_1\, Y => annul_next_2_sqmuxa_1_8); - - un6_ex_add_res_d2_ADD_33x33_fast_I297_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[7]\, B => N674, Y => - \un6_ex_add_res_s2[7]\); - - \r.x.ctrl.pc_RNIFOI61[19]\ : MX2C - port map(A => \un1_p0_6[371]\, B => \pc_0[19]\, S => - s_3_sqmuxa, Y => N_3410); - - \r.e.op1_RNI0NCR1[27]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[27]\, Y => - \ex_op1_i_m[27]\); - - \r.e.ctrl.trap_RNISBSJ\ : OR2A - port map(A => un3_notag, B => trap_0, Y => jump_0_sqmuxa); - - un6_fe_npc_I_52 : XOR2 - port map(A => N_116, B => \fe_pc[11]\, Y => I_52); - - \r.m.y[21]\ : DFN1E0 - port map(D => \y_0[21]\, CLK => lclk_c, E => holdn, Q => - \y[21]\); - - \r.m.result_RNO[26]\ : MX2 - port map(A => \aluresult[26]\, B => \op1[26]\, S => - un17_casaen_0_1, Y => \eres2[26]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I56_Y_0\ : AO1 - port map(A => N404_0, B => N400, C => N403, Y => N473_0); - - \r.x.annul_all_RNIPVOS\ : AO1D - port map(A => rett_1_0, B => rett_0_0, C => annul_all, Y - => su2); - - \r.d.inst_0_RNO_0[20]\ : MX2 - port map(A => data_0_20, B => \inst_0[20]\, S => - inull_RNIFV6VG2_0, Y => N_4620); - - \r.d.inst_0_RNI62J4[23]\ : OR3A - port map(A => \inst_0[19]\, B => \inst_0_0[23]\, C => - \inst_0[20]\, Y => N_3721); - - un6_ex_add_res_d1_ADD_33x33_fast_I270_Y_0_o3 : OA1C - port map(A => N790_0, B => N_30, C => N514_1, Y => N786_i); - - \r.e.op1_RNIMI8G[20]\ : OR2B - port map(A => \op1[20]\, B => un14_casaen_s1_0, Y => - \op1_m_0[20]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I299_Y_0 : XNOR2 - port map(A => N817, B => \un6_ex_add_res_s2_1[9]\, Y => - \un6_ex_add_res_s0[9]\); - - \r.e.jmpl_RNI3D91I1\ : AOI1B - port map(A => \shiftin_17[20]\, B => aluresult_1_sqmuxa_0, - C => \aluresult_1_iv_6[19]\, Y => \aluresult_1_iv_7[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I271_Y_0 : NOR3A - port map(A => I235_un1_Y_i, B => I179_un1_Y, C => N582, Y - => ADD_33x33_fast_I271_Y_0_0); - - \r.e.shleft_RNID1MH2\ : MX2B - port map(A => \shiftin_5[34]\, B => \shiftin_5[18]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[18]\); - - \r.d.inst_0[31]\ : DFN1 - port map(D => \inst_0_RNO[31]\, CLK => lclk_c, Q => - \inst_0[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I1_G0N : OA1 - port map(A => \op1[0]\, B => ldbp1_0, C => \data_0[0]\, Y - => N397_1); - - \r.d.inst_0_RNO_0[3]\ : MX2 - port map(A => data_0_0_3, B => \inst_0[3]\, S => - mexc_1_sqmuxa_1_0, Y => N_4603); - - \r.d.annul_RNIRK1K4_0\ : OR2A - port map(A => un9_rabpmiss_1, B => \ra_bpmiss_1_0\, Y => - un9_rabpmiss); - - \r.e.op1[2]\ : DFN1E0 - port map(D => \aop1[2]\, CLK => lclk_c, E => holdn, Q => - \op1[2]\); - - \r.m.y_RNIOJEJ3[8]\ : AND2 - port map(A => \tt_m[4]\, B => \aluresult_1_iv_1[8]\, Y => - \aluresult_1_iv_3[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I269_un1_Y : OR3C - port map(A => N645_1, B => N661_0, C => N676_1, Y => - I269_un1_Y_0); - - \r.e.op1_RNIVG9GN5[20]\ : NOR3C - port map(A => \op1_m_0[20]\, B => \d_iv_2[20]\, C => - \aluresult_m_0[20]\, Y => \d_i[20]\); - - \r.e.ldbp2_RNI12HDB\ : OR2A - port map(A => \eaddress[5]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[6]\); - - \r.w.s.pil_RNI7MFA1[0]\ : OR2A - port map(A => \pil[0]\, B => aluresult_11_sqmuxa, Y => - \pil_m[0]\); - - \r.m.ctrl.pc[8]\ : DFN1E0 - port map(D => \pc_2[8]\, CLK => lclk_c, E => holdn, Q => - \pc_3[8]\); - - \r.e.invop2_0_RNID83K9\ : MX2 - port map(A => \un6_ex_add_res_s2[8]\, B => - \un6_ex_add_res_s0[8]\, S => invop2_0, Y => N_6554); - - \r.m.ctrl.inst_RNIVC0E[30]\ : OR2B - port map(A => \inst_1[31]\, B => \inst_1[30]\, Y => - un5_trap); - - un6_ex_add_res_d2_ADD_33x33_fast_I79_Y_0 : AO1 - port map(A => N419_0, B => N415_2, C => N418, Y => N538_0); - - \r.f.pc_RNO_5[14]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[14]\, Y => \xc_trap_address_m[14]\); - - \r.x.data_0_RNO_2[12]\ : NOR2A - port map(A => \data_0_2[12]\, B => ld_0_0, Y => - \data_0_m[12]\); - - \r.m.ctrl.rd_RNI3RO53[1]\ : NOR3C - port map(A => un2_rs1_2_7_i_0, B => un2_rs1_2_5_i_0, C => - wreg_1_2_0, Y => wreg_1_5); - - \r.m.dci.size[1]\ : DFN1E0 - port map(D => \size[1]\, CLK => lclk_c, E => holdn, Q => - \size_0[1]\); - - \r.w.s.y_RNO[12]\ : MX2 - port map(A => \y_2[12]\, B => \result[12]\, S => N_481_0, Y - => N_3776); - - un23_ra_I_9 : XOR2 - port map(A => \cwp_0[0]\, B => \inst_0[18]\, Y => - \DWACT_ADD_CI_0_partial_sum_0[0]\); - - \r.e.aluop_0_RNI67I22[0]\ : OR2B - port map(A => \logicout[9]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[9]\); - - \r.a.ctrl.inst_RNIK42S[22]\ : NOR2A - port map(A => N_271, B => N_256_i_0, Y => - illegal_inst12_tz_tz); - - \r.x.result_RNIOMED[13]\ : MX2 - port map(A => \result_0[13]\, B => \data_0[13]\, S => ld_0, - Y => \un1_p0_6[365]\); - - \r.e.op1_RNIRE4U1[8]\ : AO1A - port map(A => \op1[8]\, B => \un17_casaen_0_0\, C => - \ex_op1_i_m[8]\, Y => \edata2_0_iv_0[8]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I4_P0N\ : OR2 - port map(A => \inst_0_RNI4VUM[4]\, B => \dpc[6]\, Y => N371); - - \r.e.aluop_1_RNIMO642[1]\ : MX2C - port map(A => \logicout_4[2]\, B => N_6907, S => N_6866_i, - Y => N_3625); - - \r.x.data_0_RNO_1[22]\ : NOR2A - port map(A => \data_0_0[22]\, B => ld_3, Y => - \data_0_m[22]\); - - \r.f.pc_RNO[22]\ : OR3C - port map(A => \tmp_m[22]\, B => \pc_1_iv_1[22]\, C => - \un6_fe_npc_m[20]\, Y => \pc_1[22]\); - - \r.e.shleft_RNI1RFM2\ : MX2B - port map(A => \shiftin_5[44]\, B => \shiftin_5[28]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[28]\); - - \r.e.jmpl_RNIUPCSQ5\ : OR3C - port map(A => \aluresult_1_iv_8[21]\, B => - \shiftin_17_m_0[21]\, C => \un6_ex_add_res_m[22]\, Y => - \aluresult[21]\); - - \r.e.sari_RNIC80T\ : MX2 - port map(A => sari, B => ex_sari_1, S => ldbp1_0, Y => - ex_sari_1_1_0_0); - - \r.e.jmpl_RNIGRVKM2\ : NOR3C - port map(A => \shiftin_17_m[27]\, B => - \aluresult_1_iv_7[26]\, C => \shiftin_17_m_0[26]\, Y => - \aluresult_1_iv_9[26]\); - - un6_fe_npc_I_115 : XOR2 - port map(A => N_71_0, B => \fe_pc[20]\, Y => I_115); - - un6_ex_add_res_d2_ADD_33x33_fast_I190_Y : OR3C - port map(A => N535_1, B => ADD_33x33_fast_I138_Y_0_0, C => - N593_1, Y => N659_0); - - \r.w.s.y[10]\ : DFN1E0 - port map(D => N_3774, CLK => lclk_c, E => N_6922_i_0, Q => - \y[10]\); - - \r.e.ldbp1\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1); - - \r.x.ctrl.rd_RNIE2NU[6]\ : MX2 - port map(A => \cwp[2]\, B => \rd_2[6]\, S => N_6357, Y => - waddr(6)); - - \r.x.data_0_RNIIJ9E[29]\ : XNOR2 - port map(A => \data_0_0[29]\, B => invop2_0, Y => N_4276_i); - - \r.f.pc_RNO[14]\ : OR3C - port map(A => N_29, B => m7_1, C => N_6619, Y => N_8_0_i_0); - - \r.e.op1_RNIKPAT4[21]\ : AO1A - port map(A => \bpdata[21]\, B => edata_2_sqmuxa, C => - \op1_i_m[21]\, Y => \edata2_0_iv_0[21]\); - - \r.e.op1_RNIAHFC[6]\ : OR2B - port map(A => \op1[6]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[6]\); - - \r.e.shcnt_RNID03J9[2]\ : MX2C - port map(A => \shiftin_11[7]\, B => \shiftin_11[3]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[3]\); - - \r.e.op2_RNI59C6[0]\ : MX2 - port map(A => \op2[0]\, B => N_3304, S => ldbp2_3, Y => - \op2_RNI59C6[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I41_Y : AO13 - port map(A => N472_2, B => \un1_iu0_6[26]\, C => - \data_0[26]\, Y => N500); - - \r.a.ctrl.rd_RNIRVMDC[6]\ : NOR2B - port map(A => wreg_6, B => un1_de_ren1_NE_i_0, Y => - un1_de_ren1_2); - - \r.a.ctrl.inst_RNI23QQ3[22]\ : OAI1 - port map(A => N_483, B => N_6696, C => \inst[22]\, Y => - N_500); - - \r.w.s.y_RNO_1[18]\ : NOR2A - port map(A => wy_RNILF1N3, B => \y[18]\, Y => N_390); - - \r.f.pc_RNI429LB[4]\ : MX2 - port map(A => \fpc[4]\, B => \eaddress[4]\, S => jump, Y - => N_4047); - - \r.d.inst_0_RNI3IRK91[13]\ : OA1B - port map(A => un1_de_ren1_2, B => \osel_i_a3_0[0]\, C => - imm, Y => N_3944); - - \r.e.jmpl_RNI8ML1S\ : OR2B - port map(A => \shiftin_17[22]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[22]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I86_Y : NOR2B - port map(A => N410_0, B => N407_2, Y => N545_1); - - \r.f.pc_RNO_2[31]\ : OR2B - port map(A => I_210, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[29]\); - - \r.e.op2_RNI88NB1_0[16]\ : OR2 - port map(A => \un1_iu0_6[16]\, B => \un1_iu0_5[82]\, Y => - \logicout_3[16]\); - - \r.d.inst_0_RNIKD1B[31]\ : NOR3C - port map(A => \inst_0[31]\, B => \inst_0_0[24]\, C => - de_fins_hold_1_1, Y => de_fins_hold_1_2); - - \r.a.ctrl.inst_RNI5H3O1[22]\ : OR3A - port map(A => aluop_2_1_0_a2_1, B => N_225, C => N_204, Y - => N_473_i); - - \r.e.shleft_0_RNIU2BG\ : NOR2A - port map(A => \un1_iu0_6[1]\, B => shleft_0, Y => - shleft_0_RNIU2BG); - - \r.e.ldbp2_2_RNILAU51\ : MX2C - port map(A => \un6_ex_add_res_s1_i[1]\, B => N_6640_i, S - => ldbp2_2, Y => \eaddress[0]\); - - \r.e.cwp_RNIGTJ61[1]\ : OR2A - port map(A => \cwp_2[1]\, B => aluresult_11_sqmuxa, Y => - \cwp_m[1]\); - - \r.d.inull_RNIPRHA\ : NOR3C - port map(A => un19_inst, B => \inull\, C => - hold_pc_1_sqmuxa, Y => hold_pc_2_m); - - \comb.branch_address.tmp_ADD_30x30_fast_I157_Y\ : NOR2B - port map(A => N531, B => N523, Y => N583); - - \r.e.shcnt_RNIV2HIP[1]\ : MX2C - port map(A => \shiftin_14[20]\, B => \shiftin_14[18]\, S - => \ex_shcnt_1_i[1]\, Y => \shiftin_17[18]\); - - \r.e.ldbp2_2_RNIC3RV5\ : MX2C - port map(A => \un6_ex_add_res_s1[4]\, B => N_6643, S => - ldbp2_2, Y => \eaddress[3]\); - - \r.e.mulstep_RNI8VGC\ : OR2A - port map(A => wy_0, B => mulstep, Y => y14); - - \r.d.inst_0[22]\ : DFN1 - port map(D => \inst_0_RNO[22]\, CLK => lclk_c, Q => - \inst_0_0[22]\); - - \r.e.op1_RNIS2NF[10]\ : NOR2A - port map(A => un17_casaen_0, B => \op1[10]\, Y => - \op1_i_m[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I259_un1_Y : OR3C - port map(A => N641_0, B => N625, C => N796, Y => I259_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I260_un1_Y : OR3C - port map(A => N643_0, B => N627_1, C => N799_0, Y => - I260_un1_Y); - - \r.d.pc_RNO[16]\ : MX2 - port map(A => \fpc[16]\, B => \dpc[16]\, S => N_6763_i, Y - => \pc_RNO[16]\); - - \r.e.ctrl.pc_RNI40LA2[5]\ : AOI1B - port map(A => \pc[5]\, B => jmpl_0, C => \y_m_1[5]\, Y => - \aluresult_1_iv_2[5]\); - - \comb.v.x.data_0_1_1_iv[31]\ : OR2 - port map(A => \data_0_1_2[17]\, B => \data_0_1_1_iv_1[31]\, - Y => \data_0_1[31]\); - - \r.x.ctrl.annul_RNIK8PV\ : OR2A - port map(A => s_3_sqmuxa, B => holdn, Y => N_6747); - - \r.e.ldbp2_2_RNI8OPVN\ : MX2 - port map(A => \un6_ex_add_res_s1[10]\, B => N_6629, S => - ldbp2_2, Y => \eaddress[9]\); - - \r.f.pc_RNO_2[20]\ : OR2B - port map(A => I_115, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[18]\); - - \r.e.op2_RNI15BP_0[8]\ : OR2 - port map(A => \un1_iu0_6[8]\, B => \un1_iu0_5[74]\, Y => - \logicout_3[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I268_Y : OR2 - port map(A => I229_un1_Y, B => ADD_33x33_fast_I268_Y_0, Y - => N782); - - \r.e.op1[15]\ : DFN1E0 - port map(D => \aop1[15]\, CLK => lclk_c, E => holdn, Q => - \op1[15]\); - - \r.w.s.wim_RNI85RD2[2]\ : OR2B - port map(A => \wim[2]\, B => aluresult_13_sqmuxa, Y => - \wim_m[2]\); - - \r.d.pc_RNO[10]\ : MX2 - port map(A => \fpc[10]\, B => \dpc[10]\, S => N_6763_i_0, Y - => \pc_RNO[10]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I26_G0N : NOR2A - port map(A => \un1_iu0_6[25]\, B => \data_0[25]\, Y => - N472_2); - - \r.e.aluop_RNIS3JJ1[2]\ : XA1 - port map(A => \un1_iu0_5[82]\, B => \aluop_1[2]\, C => - \un1_iu0_6[16]\, Y => N_3543); - - \r.a.ctrl.inst_RNITAMH[5]\ : NOR3B - port map(A => \inst[8]\, B => un29_casaen_3, C => \inst[5]\, - Y => un29_casaen_5); - - \r.f.pc_RNIPJB2P2[4]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[4]\, Y => - \pc_4_m[4]\); - - \r.d.inst_0_RNO_0[29]\ : MX2 - port map(A => data_0_2_29, B => \inst_0[29]\, S => - inull_RNIFV6VG2_0, Y => N_4629); - - \r.e.op2[4]\ : DFN1E0 - port map(D => N_288, CLK => lclk_c, E => holdn, Q => - \op2[4]\); - - \r.a.imm[8]\ : DFN1E0 - port map(D => \un3_de_ren1[126]\, CLK => lclk_c, E => holdn, - Q => \imm[8]\); - - \r.e.jmpl_RNIL4D8K\ : OR2B - port map(A => \shiftin_17[2]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I267_un1_Y : OR3C - port map(A => N641_1, B => N657_1, C => N672_1, Y => - I267_un1_Y_0); - - \r.f.pc_RNO_1[12]\ : OR2B - port map(A => annul_RNI5L7FE1, B => \eaddress[12]\, Y => - \un6_ex_add_res_m_1[13]\); - - \r.f.pc_RNI88JQL8[5]\ : OR3C - port map(A => \npc_iv_1[5]\, B => \npc_iv_0[5]\, C => - \npc_iv_2[5]\, Y => rpc_3); - - \r.f.pc_RNO[30]\ : OR3C - port map(A => \tmp_m[30]\, B => \pc_1_iv_1[30]\, C => - \un6_fe_npc_m[28]\, Y => \pc_1[30]\); - - \r.e.shcnt_RNI380K7[3]\ : MX2 - port map(A => \shiftin_8[46]\, B => \shiftin_8[38]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[38]\); - - \r.x.data_0_RNO_0[7]\ : AO1B - port map(A => rdatav_0_1_0_iv_4_14, B => mcdo_m_0_21, C => - N_3455, Y => \dco_m_i[119]\); - - \r.e.aluop_RNIAURO4[2]\ : OR2B - port map(A => edata_1_sqmuxa, B => \bpdata[13]\, Y => - \bpdata_i_m_0[13]\); - - \r.e.ctrl.inst_RNIKC1E[20]\ : OR2B - port map(A => \inst_1[20]\, B => \inst[19]\, Y => - ex_sari_1_1_0); - - \r.x.ctrl.inst[28]\ : DFN1E0 - port map(D => \inst_3[28]\, CLK => lclk_c, E => holdn, Q - => \inst[28]\); - - \r.w.s.tt_RNIFNP81[5]\ : OR2B - port map(A => \tt[5]\, B => aluresult_12_sqmuxa, Y => - \tt_m[5]\); - - \r.m.y[11]\ : DFN1E0 - port map(D => \y_1[11]\, CLK => lclk_c, E => holdn, Q => - \y_0[11]\); - - \r.e.invop2_RNIUBQUU1\ : MX2C - port map(A => \un6_ex_add_res_s2[21]\, B => - \un6_ex_add_res_s0[21]\, S => invop2, Y => N_6567); - - \r.e.ctrl.rd_RNIGM7Q[2]\ : XNOR2 - port map(A => \inst_0_RNI2NUM[2]\, B => \rd_1[2]\, Y => - un1_de_ren1_2_0_i_0); - - \r.e.aluop_RNIPS566[0]\ : MX2C - port map(A => N_3577, B => N_3641, S => \aluop_1[0]\, Y => - \logicout[18]\); - - \r.d.inst_0_RNIHDQK[17]\ : MX2C - port map(A => un26_rs1opt, B => N_3525_3, S => rs1mod, Y - => \un3_de_ren1[98]\); - - \r.m.y_RNO_2[12]\ : OR2A - port map(A => \logicout[12]\, B => y14, Y => - \logicout_m[12]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I27_P0N\ : NOR2 - port map(A => \inst_0_RNI8AJ4[27]\, B => \dpc[29]\, Y => - N440_2); - - \r.e.op2_RNO[19]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[19]\, Y => N_303); - - \r.e.op2_RNI93PP[29]\ : MX2B - port map(A => \op2[29]\, B => N_4276_i, S => ldbp2_0, Y => - \un1_iu0_5[95]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I259_Y_2 : NOR3C - port map(A => I95_un1_Y_1, B => ADD_33x33_fast_I259_Y_0, C - => I155_un1_Y_1, Y => ADD_33x33_fast_I259_Y_2); - - \r.f.pc_RNINH122[6]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[6]\, Y => \xc_trap_address_m[6]\); - - \r.x.result[29]\ : DFN1E0 - port map(D => \maddress[29]\, CLK => lclk_c, E => holdn, Q - => \result_0[29]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I30_P0N : NOR2 - port map(A => \op2[29]\, B => \un1_iu0_6[29]\, Y => N485_i); - - \r.w.result_RNI2PHF[6]\ : AOI1B - port map(A => \un1_p0_6[358]\, B => d14, C => - \result_m_0_0[6]\, Y => \d_iv_0[6]\); - - \r.m.dci.asi_RNO[1]\ : OR2A - port map(A => \inst_0[23]\, B => \inst_1[6]\, Y => \asi[1]\); - - \r.m.result_RNIGJD4[28]\ : OR2B - port map(A => d13_0, B => \maddress[28]\, Y => - \result_m_0_0[28]\); - - \r.a.ctrl.inst_RNIGH462[31]\ : OR3C - port map(A => N_259, B => cp_disabled_3_sqmuxa_2_0, C => - N_515, Y => cp_disabled_3_sqmuxa_2); - - \r.w.s.tba_RNIF0QP4[10]\ : AOI1B - port map(A => \tba[10]\, B => aluresult_12_sqmuxa_0_0, C - => \aluresult_1_iv_2[22]\, Y => \aluresult_1_iv_4[22]\); - - \r.x.ctrl.pc_RNIJPL9[30]\ : MX2 - port map(A => \pc_2[30]\, B => \pc_0[30]\, S => \npc[1]\, Y - => N_3241); - - un6_ex_add_res_d0_ADD_33x33_fast_I48_Y_i : OR2B - port map(A => N467_2, B => N464_2, Y => N_15_0); - - \r.m.y_RNO_4[10]\ : OR2B - port map(A => \y_0[11]\, B => mulstep_1, Y => \y_m_0[11]\); - - \r.a.ctrl.inst_RNIJ25Q1[26]\ : MX2C - port map(A => N_3342, B => N_3343, S => \inst_2[26]\, Y => - N_3344); - - \r.w.s.y[16]\ : DFN1E0 - port map(D => N_3780, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[16]\); - - \r.w.result[13]\ : DFN1E0 - port map(D => \wdata[13]\, CLK => lclk_c, E => holdn, Q => - \result[13]\); - - \r.m.y_RNO[24]\ : AO1C - port map(A => y14_0, B => N_198, C => \y_iv_0_2[24]\, Y => - \y_1[24]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I245_Y : AO1 - port map(A => N676_1, B => N661_0, C => N660_0, Y => N802_0); - - \r.w.result[2]\ : DFN1E0 - port map(D => \wdata[2]\, CLK => lclk_c, E => holdn, Q => - \result[2]\); - - \r.m.y_RNO_2[4]\ : OR2B - port map(A => wy_RNIMKUI, B => \y_2[4]\, Y => \y_m_2[4]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I97_un1_Y : OAI1 - port map(A => N478, B => ADD_33x33_fast_I39_Y_0_a3, C => - N495, Y => I97_un1_Y); - - \r.e.op1_RNI98FC72[4]\ : AO1B - port map(A => un14_casaen_s0_0_0, B => \aluresult[4]\, C - => \d_iv_3[4]\, Y => \d[4]\); - - \r.a.imm[9]\ : DFN1E0 - port map(D => \un3_de_ren1[127]\, CLK => lclk_c, E => holdn, - Q => \imm[9]\); - - \r.a.ctrl.cnt_RNI6P4J3_0[0]\ : NOR3C - port map(A => N_457, B => N_456, C => N_458, Y => - un1_aop2_1_sqmuxa_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I84_Y\ : MAJ3 - port map(A => \dpc[3]\, B => \inst_0_RNI1JUM[1]\, C => N358, - Y => N501_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I39_Y\ : AND2 - port map(A => N428, B => N431, Y => N456); - - wovf_exc_0_sqmuxa_RNO_4 : MX2 - port map(A => \wim_1[0]\, B => \wim_1[4]\, S => \ncwp_3[2]\, - Y => N_3725); - - \r.e.ctrl.inst[14]\ : DFN1E0 - port map(D => \inst_1[14]\, CLK => lclk_c, E => holdn, Q - => \inst[14]\); - - \r.m.dci.asi_RNO[3]\ : OR2A - port map(A => \inst_0[23]\, B => \inst_1[8]\, Y => \asi[3]\); - - \r.e.op2_RNO_1[23]\ : NOR3C - port map(A => \rfo_m_i[55]\, B => \d_1_iv_2[23]\, C => - \op1_m_i[23]\, Y => \d_1_iv_4[23]\); - - \r.e.ctrl.tt_RNO[0]\ : AOI1 - port map(A => \tt_9_1[0]\, B => \tt_RNO_0[0]\, C => annul_2, - Y => \tt_1[0]\); - - \r.w.s.y_RNO[19]\ : MX2 - port map(A => \y_2[19]\, B => \result_0[19]\, S => N_481, Y - => N_3783); - - \r.e.cwp_RNIOJ6CI[1]\ : NOR3C - port map(A => \logicout_m_0[1]\, B => \aluresult_2_iv_3[1]\, - C => \bpdata_m[1]\, Y => \aluresult_2_iv_5[1]\); - - \r.e.aluop_0_RNIKD6R[1]\ : XOR3 - port map(A => \un1_iu0_6[6]\, B => \aluop_0[1]\, C => - \un1_iu0_5[72]\, Y => N_6838); - - \r.e.aluop_RNIAGR04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[5]\, Y => - \bpdata_i_m_2[5]\); - - \r.x.ctrl.pc_RNIAQGF[22]\ : MX2 - port map(A => \pc_0[22]\, B => \pc_2[22]\, S => \npc_0[1]\, - Y => N_3233); - - \r.d.pv_RNI7DFS7\ : OR2A - port map(A => un5_exbpmiss_i_0, B => un1_inst, Y => - annul_current_2_sqmuxa_1); - - \r.x.data_0_RNO_5[5]\ : OR2B - port map(A => rdata_2_sqmuxa, B => data_0_2_13, Y => - \dco_m_i[109]\); - - \r.a.rsel1_RNO[0]\ : OR2A - port map(A => rfe_1_2, B => \rsel1_RNO_0[0]\, Y => - \osel[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I63_Y_0 : OR2 - port map(A => N_53, B => N442_0, Y => N522_1); - - \r.m.y_RNITF5NM[12]\ : NOR3C - port map(A => \aluresult_1_iv_4[12]\, B => - \aluresult_1_iv_3[12]\, C => \logicout_m_0[12]\, Y => - \aluresult_1_iv_6[12]\); - - \r.a.rsel1_0_RNIU65A3[2]\ : NOR3C - port map(A => \d_iv_0_0[5]\, B => N_406, C => - \rsel1_0_RNITC8M2[2]\, Y => \d_iv_0_2[5]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I276_Y_0\ : AX1D - port map(A => N403, B => ADD_30x30_fast_I216_Y_0_a3, C => - ADD_30x30_fast_I276_Y_0_0, Y => \tmp[18]\); - - \r.x.dci.SIGNED_RNIEJUC9\ : MX2 - port map(A => SIGNED, B => SIGNED_0, S => dco_i_2(132), Y - => me_signed_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I320_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[29]\, B => \op2[29]\, Y => - ADD_33x33_fast_I320_Y_0_0); - - \r.e.aluop_1_RNIGPA03[1]\ : MX2C - port map(A => \logicout_4[29]\, B => N_6850, S => N_6866_i, - Y => N_3652); - - \r.f.pc_RNIVNTQA2[10]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[10]\, C => - \pc_m[10]\, Y => \npc_iv_1[10]\); - - \r.d.inst_0_RNIKDP8[17]\ : OR2B - port map(A => I_13_2, B => un26_rs1opt, Y => - \de_raddr1_2[5]\); - - \r.x.rstate_0_RNIGE601[0]\ : MX2 - port map(A => s_3_sqmuxa_0, B => \rstate_0[0]\, S => holdn, - Y => N_6322); - - \r.x.ctrl.tt_RNO[2]\ : MX2C - port map(A => tt_2_sqmuxa_1, B => N_4206, S => N_4210_i_0, - Y => \tt2[2]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I146_Y : NOR3C - port map(A => N407_2, B => N404_2, C => N543_0, Y => N609_1); - - \r.e.sari_RNIBKJO\ : MX2 - port map(A => sari, B => ex_sari_1, S => ldbp1, Y => - ex_sari_1_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I269_un1_Y : OR2B - port map(A => ADD_33x33_fast_I269_un1_Y_0, B => N676, Y => - I269_un1_Y); - - \r.x.result_RNIQFKA[5]\ : MX2 - port map(A => \result_0[5]\, B => \data_0[5]\, S => ld_0, Y - => \un1_p0_6[357]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I39_Y_0_o3 : MAJ3 - port map(A => N475_1, B => \data_0[27]\, C => - \un1_iu0_6[27]\, Y => N498); - - un6_ex_add_res_d1_ADD_33x33_fast_I69_Y : MAJ3 - port map(A => \op2[12]\, B => \un1_iu0_6[12]\, C => N430, Y - => N528_1); - - \r.e.aluop_0_RNILD6R[2]\ : XA1 - port map(A => \un1_iu0_5[72]\, B => \aluop_0[2]\, C => - \un1_iu0_6[6]\, Y => N_3533); - - \comb.irq_trap.op_gt.un2_irl_0_I_6\ : NOR2A - port map(A => irl_0(3), B => \pil[3]\, Y => \ACT_LT4_E[5]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I262_Y_0\ : XOR2 - port map(A => N501_0, B => ADD_30x30_fast_I262_Y_0_0, Y => - \tmp[4]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I130_Y : NOR2B - port map(A => ADD_33x33_fast_I130_Y_0_0, B => N527_0, Y => - N593_0); - - \r.x.rstate_RNIJKCQ_0[1]\ : OR2A - port map(A => rstate_6314_d_0, B => s_3_sqmuxa_0, Y => - xc_exception_1); - - \r.f.pc_RNO_0[27]\ : NOR3C - port map(A => \un6_ex_add_res_m_1[28]\, B => - \pc_1_iv_0[27]\, C => \tmp_m[27]\, Y => \pc_1_iv_2[27]\); - - \r.e.op1_RNI6A2VM2[8]\ : NOR3C - port map(A => \op1_m_0[8]\, B => \d_iv_2[8]\, C => - \aluresult_m_0[8]\, Y => \d_i[8]\); - - \r.d.inst_0_RNI5NNB[27]\ : MX2C - port map(A => branch_3_i, B => branch_7_i, S => - \inst_0[27]\, Y => N_3347); - - \comb.branch_address.tmp_ADD_30x30_fast_I194_un1_Y\ : AO1C - port map(A => N526, B => I160_un1_Y_i, C => N571_1, Y => - I194_un1_Y); - - \r.w.result_RNIR3RK[7]\ : AOI1B - port map(A => \un1_p0_6[359]\, B => d14_0, C => - \result_m_0_0[7]\, Y => \d_iv_0[7]\); - - \r.x.result_RNIE4MO5[3]\ : OR2A - port map(A => N_3687, B => \bpdata[3]\, Y => - \bpdata_i_m[3]\); - - \r.e.op2_RNIP3HN1[31]\ : OR2B - port map(A => \un1_iu0_5[97]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[31]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I204_Y : NOR2 - port map(A => N608_0, B => I204_un1_Y_0, Y => N674); - - \r.m.result_RNICOV6[4]\ : OR2B - port map(A => d13_0, B => \maddress[4]\, Y => - \result_m_0_0[4]\); - - \r.e.op2_RNI8M541[4]\ : OR2B - port map(A => \un1_iu0_5[70]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[4]\); - - \dci.enaddr_1_sqmuxa_1\ : NAND2 - port map(A => trap, B => enaddr_1_sqmuxa_1_1, Y => - enaddr_1_sqmuxa_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I262_Y_0_a3 : AO1C - port map(A => N506, B => N_74_i, C => - ADD_33x33_fast_I262_Y_0_a3_0_0, Y => N_51_i); - - \r.a.ctrl.inst_RNI3RVN5[30]\ : OR3B - port map(A => illegal_inst37_2, B => \y_1[0]\, C => - \inst[30]\, Y => N_452); - - \r.x.ctrl.rd[3]\ : DFN1E0 - port map(D => \rd_0[3]\, CLK => lclk_c, E => holdn, Q => - \rd_2[3]\); - - \r.e.alusel_RNI71FHG[0]\ : AOI1B - port map(A => aluresult_3_sqmuxa_0, B => N_198, C => - \aluresult_1_iv_4[24]\, Y => \aluresult_1_iv_6[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I176_Y : NOR2B - port map(A => N587_0, B => N579_0, Y => N645); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_un1_Y_0 : AND2 - port map(A => N651_0, B => N635_0, Y => - ADD_33x33_fast_I264_un1_Y_0); - - \r.e.op2_RNO_2[25]\ : NOR3C - port map(A => \d_1_iv_1[25]\, B => \d_1_iv_0[25]\, C => - \rfo_m_i[57]\, Y => \d_1_iv_3[25]\); - - \r.e.ctrl.inst[17]\ : DFN1E0 - port map(D => \inst_1[17]\, CLK => lclk_c, E => holdn, Q - => \inst[17]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I31_G0N : OR2A - port map(A => \un1_iu0_6[30]\, B => \data_0[30]\, Y => N487); - - \r.a.rsel1_RNII9L1U4[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[17]\, Y - => \aluresult_m_0[17]\); - - \r.a.ctrl.inst_RNI72LH8[21]\ : OR3B - port map(A => inst_14, B => illegal_inst34_3, C => - illegal_inst35, Y => un1_illegal_inst34); - - \r.a.rsel1_RNI7HGCE2[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[6]\, Y => - \aluresult_m_0[6]\); - - \r.e.op2_RNIBHPA[9]\ : OR2A - port map(A => \un1_iu0_5[75]\, B => \un1_iu0_6[9]\, Y => - \logicout_4[9]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I65_Y : OR2 - port map(A => I65_un1_Y, B => N439, Y => N524); - - \r.e.op1_RNI5AO62[28]\ : OA1A - port map(A => \un17_casaen_0_0\, B => \op1[28]\, C => - \ex_op1_i_m[28]\, Y => \edata2_iv_0[28]\); - - \r.d.cnt_RNIDLUQ[0]\ : AO1 - port map(A => un54_casaen, B => \inst_0_RNIPQUJ[21]\, C => - call_hold7_i, Y => ld_1_sqmuxa); - - \r.a.ctrl.inst_RNIIC131[20]\ : NOR3A - port map(A => \inst_2[20]\, B => N_203, C => N_201, Y => - aluadd_16_sqmuxa_0_a5_1); - - \r.x.ctrl.inst_RNICAF93[20]\ : OA1 - port map(A => y6, B => y10, C => rstate_4_1, Y => - rstate_4_2); - - \r.x.result_RNI6VED[27]\ : MX2 - port map(A => \result_0[27]\, B => \data_0[27]\, S => ld_0, - Y => \un1_p0_6[379]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I206_un1_Y\ : OR2B - port map(A => N598, B => N583, Y => I206_un1_Y); - - \r.m.y_RNI0JS5C[28]\ : NOR3C - port map(A => \aluop_RNI2TEB4[1]\, B => - \aluresult_1_iv_0[28]\, C => \aluop_RNIPR2R4[2]\, Y => - \aluresult_1_iv_4[28]\); - - \r.a.imm[14]\ : DFN1E0 - port map(D => \un3_de_ren1[132]\, CLK => lclk_c, E => holdn, - Q => \imm[14]\); - - \r.d.annul_RNITDPJ03\ : OR2B - port map(A => I_9, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[2]\); - - \r.m.ctrl.rd_RNI2Q6H1[7]\ : XOR2 - port map(A => \rd_0[7]\, B => un1_reg, Y => - \rd_RNI2Q6H1[7]\); - - \r.e.ctrl.tt_RNO_1[3]\ : NOR3A - port map(A => ticc, B => annul_2, C => \tt_4[3]\, Y => - \tt_1[3]\); - - \r.w.result_RNIJSFF[1]\ : AOI1B - port map(A => \un1_p0_6[353]\, B => d14, C => - \result_m_0_0[1]\, Y => \d_iv_0[1]\); - - \r.f.pc_RNO_2[26]\ : OR2B - port map(A => I_166, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[24]\); - - \r.e.ldbp2_RNIB0VAD7\ : OR2B - port map(A => \aluresult_1_iv_9[28]\, B => - \un6_ex_add_res_m[29]\, Y => \aluresult[28]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I259_un1_Y : OR3C - port map(A => N641, B => N625_0, C => N796_0, Y => - I259_un1_Y_0); - - \r.x.ctrl.pc[5]\ : DFN1E0 - port map(D => \pc_2[5]\, CLK => lclk_c, E => holdn, Q => - \pc_3[5]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I204_Y : AO1 - port map(A => N616, B => N609_1, C => N608, Y => N674_1); - - \r.x.data_0_RNO_2[15]\ : NOR2A - port map(A => data_0_31, B => rdata_5_sqmuxa, Y => - \dco_m_0[127]\); - - \r.a.rsel1_0_RNIC3LJ2[2]\ : OR2B - port map(A => data1(15), B => d11, Y => \rfo_m[15]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I275_Y_0_0\ : XOR2 - port map(A => \dpc[17]\, B => \inst_0[15]\, Y => - ADD_30x30_fast_I275_Y_0_0); - - \r.e.shcnt[0]\ : DFN1E0 - port map(D => N_266_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[0]\); - - \r.e.alucin_RNO_3\ : OR3 - port map(A => \inst_2[21]\, B => \inst[30]\, C => inst_9_3, - Y => N_350); - - \r.x.result_RNIO7KA[4]\ : MX2 - port map(A => \result[4]\, B => \data_0[4]\, S => ld_0, Y - => \un1_p0_6[356]\); - - \r.w.s.tba[11]\ : DFN1E1 - port map(D => \result[23]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[11]\); - - \r.w.result_RNIIRPL[16]\ : AOI1B - port map(A => \un1_p0_6[368]\, B => d14_0, C => - \result_m_0_0[16]\, Y => \d_iv_0[16]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I106_Y : NOR3C - port map(A => N464, B => N467, C => N503_1, Y => N569_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I272_un1_Y : NOR3C - port map(A => N667_0, B => N616_0, C => N651_1, Y => - I272_un1_Y_0); - - \r.f.pc_RNO[2]\ : OR2B - port map(A => \pc_1_iv_2[2]\, B => \un6_fe_npc_m[0]\, Y => - \pc_1[2]\); - - \r.e.op1_RNO[25]\ : MX2C - port map(A => \d_i[25]\, B => \d_i[26]\, S => N_227_0, Y - => \aop1[25]\); - - \r.e.ldbp1_3\ : DFN1E0 - port map(D => ldbp, CLK => lclk_c, E => holdn, Q => ldbp1_3); - - \r.e.aluop_RNIFCHBN[0]\ : AOI1B - port map(A => \logicout[11]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_6[11]\, Y => \aluresult_1_iv_7[11]\); - - un2_rstn_5_0_0_RNIQRRG7 : NAND2 - port map(A => \tmp[8]\, B => un2_rstn_5_0, Y => \tmp_m[8]\); - - \r.e.aluop_RNINKV06[0]\ : MX2C - port map(A => N_3582, B => N_3646, S => \aluop_1[0]\, Y => - \logicout[23]\); - - \r.m.ctrl.inst_RNI5A2S[21]\ : NOR3B - port map(A => \inst[21]\, B => iflush_1, C => \inst_0[24]\, - Y => inst_1); - - \r.x.data_0_RNO_1[25]\ : NOR2A - port map(A => \data_0[25]\, B => ld_0_0, Y => - \data_0_m[25]\); - - \r.f.pc[25]\ : DFN1E0 - port map(D => \pc_1[25]\, CLK => lclk_c, E => holdn, Q => - \fpc[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I27_P0N : AO1A - port map(A => ldbp1_3, B => \op1[26]\, C => \data_0[26]\, Y - => N476_2); - - \r.x.ctrl.pc[30]\ : DFN1E0 - port map(D => \pc_3[30]\, CLK => lclk_c, E => holdn, Q => - \pc_2[30]\); - - \r.e.aluop_RNIKJP04[1]\ : NOR2A - port map(A => edata_0_sqmuxa, B => \bpdata[0]\, Y => - \bpdata_i_m_2[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I130_Y_0 : OA1 - port map(A => \op2[10]\, B => \un1_iu0_6[10]\, C => N431_1, - Y => ADD_33x33_fast_I130_Y_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I164_Y\ : AO1 - port map(A => N538_2, B => N531, C => N530_1, Y => N590); - - annul_current_3_sqmuxa_1_RNIVK738 : AND2 - port map(A => G_6_0, B => \annul_current_3_sqmuxa_1\, Y => - G_6_1); - - \r.f.pc_RNO[29]\ : OR3C - port map(A => \tmp_m[29]\, B => \pc_1_iv_1[29]\, C => - \un6_fe_npc_m[27]\, Y => \pc_1[29]\); - - \r.a.ctrl.rd[1]\ : DFN1E0 - port map(D => \rd_3[1]\, CLK => lclk_c, E => holdn, Q => - \rd_2[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I293_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[3]\, B => N616, Y => - \un6_ex_add_res_s0[3]\); - - \r.e.aluop_1_RNIK9TF1[1]\ : MX2C - port map(A => \logicout_4[4]\, B => N_6832, S => N_6866_i, - Y => N_3627); - - \r.d.inull_RNO_1\ : OR3A - port map(A => N_96, B => \inst_0[20]\, C => N_150, Y => - N_117); - - \r.x.ctrl.pc_RNIHQHF[16]\ : MX2 - port map(A => \pc_2[16]\, B => \pc[16]\, S => \npc_1[1]\, Y - => N_3227); - - un6_ex_add_res_d0_ADD_33x33_fast_I132_Y : NOR2B - port map(A => N533, B => N529_0, Y => N595_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I19_G0N : NOR3A - port map(A => \op1[18]\, B => ldbp1_3, C => \data_0_0[18]\, - Y => N451_0); - - \r.e.aluop_0_RNI1NHB1[2]\ : XA1C - port map(A => \aluop_0[2]\, B => \un1_iu0_5[90]\, C => - \logicout_5_0_i_a5_0_0[24]\, Y => N_448); - - \r.a.ctrl.cnt[0]\ : DFN1E0 - port map(D => \cnt_2[0]\, CLK => lclk_c, E => holdn, Q => - \cnt_1[0]\); - - \r.w.s.tba_RNI44CA1[3]\ : OR2B - port map(A => \tba[3]\, B => aluresult_12_sqmuxa, Y => - \tba_m[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I158_Y : NOR2B - port map(A => N569_0, B => N561, Y => N627_0); - - \r.m.icc_RNIB6A3[2]\ : XNOR2 - port map(A => \inst_0[28]\, B => \icc_0[2]\, Y => - branch_2_i); - - \r.e.op1_RNIDQEP68[31]\ : NOR3C - port map(A => \op1_m_0[31]\, B => \d_iv_2[31]\, C => - \aluresult_m_0[31]\, Y => \d_i[31]\); - - \r.x.ctrl.tt_RNIBTVQ[3]\ : MX2 - port map(A => \result_0[3]\, B => \tt[3]\, S => tt_i, Y => - N_3322); - - \r.x.result_RNI2PAN3[19]\ : MX2 - port map(A => \op1_RNID1VH[19]\, B => \un1_p0_6[371]\, S - => bpdata6, Y => \bpdata[19]\); - - \r.e.op2_RNO_8[12]\ : OR2A - port map(A => \maddress[12]\, B => d27, Y => - \result_m_i_0[12]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I138_Y : NOR2B - port map(A => ADD_33x33_fast_I138_Y_0, B => N535, Y => - N601_0); - - \r.f.pc_RNO_5[12]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[12]\, Y => \xc_trap_address_m[12]\); - - \r.a.rsel1_0_RNI4V53_1[2]\ : NOR2 - port map(A => d11_0_a5_0, B => \rsel1_0[2]\, Y => d11); - - un6_ex_add_res_d2_ADD_33x33_fast_I8_P0N : AO1A - port map(A => ldbp1_2, B => \op1[7]\, C => \data_0_2[7]\, Y - => N419_0); - - \r.w.s.y_RNO[31]\ : MX2 - port map(A => \y_1[31]\, B => \result_0[31]\, S => N_481, Y - => N_3795); - - \r.e.aluop_1_RNIKL0H[1]\ : XOR3 - port map(A => \un1_iu0_6[4]\, B => \aluop_1[1]\, C => - \un1_iu0_5[70]\, Y => N_6832); - - \r.m.icc_RNIJ0N92[1]\ : NOR2A - port map(A => trap_0_sqmuxa_2, B => trap_0_sqmuxa_1, Y => - un1_trap_0_sqmuxa_0); - - \comb.op_mux.d_1_iv_RNO_7[29]\ : OR3B - port map(A => d29_0, B => \imm[29]\, C => \rsel2[0]\, Y => - \imm_m_i[29]\); - - \r.d.inull_RNO\ : OAI1 - port map(A => N_149, B => de_inull_0_2004_0, C => N_117, Y - => de_inull); - - un6_ex_add_res_d1_ADD_33x33_fast_I123_Y : AO1 - port map(A => N524, B => N521_1, C => N520_1, Y => N586_1); - - \r.x.result_RNILB9B3[4]\ : MX2 - port map(A => \un1_iu0_6[4]\, B => \un1_p0_6[356]\, S => - bpdata6_0_0, Y => \bpdata[4]\); - - \r.e.shcnt_RNI39LF9[2]\ : MX2C - port map(A => \shiftin_11[8]\, B => \shiftin_11[4]\, S => - \ex_shcnt_1_i[2]\, Y => \shiftin_14[4]\); - - \r.e.op2_RNO_5[13]\ : OR2A - port map(A => \maddress[13]\, B => d27, Y => - \result_m_i[13]\); - - \r.d.inst_0_RNO_0[18]\ : MX2 - port map(A => data_0_18, B => \inst_0[18]\, S => - mexc_1_sqmuxa_1_0, Y => N_4618); - - \r.d.cnt_RNIFET3_0[0]\ : NOR2A - port map(A => \cnt_0[1]\, B => \cnt_2[0]\, Y => un11_op); - - \r.a.ctrl.rd[6]\ : DFN1E0 - port map(D => N_37, CLK => lclk_c, E => holdn, Q => \rd[6]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I291_Y_0 : XNOR3 - port map(A => alucin, B => \op2[0]\, C => \un1_iu0_6[0]\, Y - => \un6_ex_add_res_s1_i[1]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I21_G0N : NOR3A - port map(A => \op1[20]\, B => ldbp1_4, C => \data_0_2[20]\, - Y => N457); - - \r.e.op2_RNO_7[9]\ : NOR2B - port map(A => \result_m_i_0[9]\, B => \cpi_m_i[361]\, Y => - \d_1_iv_1[9]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I318_Y_0 : AX1C - port map(A => I263_un1_Y_i, B => ADD_33x33_fast_I263_Y_1_1, - C => ADD_33x33_fast_I318_Y_0_0, Y => - \un6_ex_add_res_s1_i[28]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I47_Y_0_o3 : AO1B - port map(A => N467_2, B => N463_2, C => N466_1, Y => N506_0); - - \r.x.intack_RNO\ : NOR3C - port map(A => intack_1, B => intack_0, C => \rstate_0[0]\, - Y => intack); - - \r.x.data_0_RNIFJ9E[25]\ : XOR2 - port map(A => \data_0[25]\, B => invop2_1, Y => N_4272); - - \r.w.result_RNIJ07I[8]\ : AOI1B - port map(A => \un1_p0_6[360]\, B => d14_0, C => - \result_m_0_0[8]\, Y => \d_iv_0[8]\); - - \r.w.s.wim_RNIMSUV3[0]\ : AOI1B - port map(A => \wim[0]\, B => aluresult_13_sqmuxa, C => - \un6_ex_add_res_m[1]\, Y => \aluresult_2_iv_0[0]\); - - \r.w.result_RNI80P1[14]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[14]\, Y - => \result_m_0_0[14]\); - - \r.x.ctrl.pc[3]\ : DFN1E0 - port map(D => \pc_3[3]\, CLK => lclk_c, E => holdn, Q => - \pc_2[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I249_un1_Y : OR2B - port map(A => N669_0, B => N552_0, Y => I249_un1_Y_i); - - \r.e.op1_RNI2NNF[25]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[25]\, Y => - \op1_RNI2NNF[25]\); - - \r.x.result_RNI5R7B3[0]\ : MX2 - port map(A => \un1_iu0_6[0]\, B => \un1_p0_6[352]\, S => - bpdata6_0_0, Y => \bpdata[0]\); - - \r.m.ctrl.pc_RNI0IHF[15]\ : MX2 - port map(A => \pc_3[15]\, B => \pc[15]\, S => \npc_1[1]\, Y - => N_3256); - - \r.w.s.wim_RNIKSJV2[5]\ : NOR2B - port map(A => aluresult_8_sqmuxa_i, B => \wim_m[5]\, Y => - \aluresult_1_iv_0[5]\); - - \r.m.result_RNIMBJN[24]\ : NOR3C - port map(A => \result_m_0[24]\, B => \cpi_m_0[376]\, C => - \result_m_0_0[24]\, Y => \d_iv_1[24]\); - - \r.a.rsel1_0_RNIE8063[2]\ : AOI1B - port map(A => data1(31), B => d11_0, C => \d_iv_1[31]\, Y - => \d_iv_2[31]\); - - \r.x.result_RNIOAHFB[1]\ : NOR2A - port map(A => rst, B => N_3871, Y => \cwp_1[1]\); - - \r.a.rfa2[2]\ : DFN1E0 - port map(D => \inst_0_RNI2NUM[2]\, CLK => lclk_c, E => - holdn, Q => \rfa2[2]\); - - \comb.irq_trap.op_gt.un2_irl_0_I_7\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \r.e.aluop_1_RNIDPJD1[1]\ : XOR3 - port map(A => \op1_RNID1VH[19]\, B => \aluop_1[1]\, C => - \un1_iu0_5[85]\, Y => N_6913); - - \comb.branch_address.tmp_ADD_30x30_fast_I8_P0N\ : OR2 - port map(A => \inst_0[8]\, B => \dpc[10]\, Y => N383); - - \r.d.inst_0_RNIFKEG[25]\ : NOR2A - port map(A => not_valid, B => tmp, Y => - \inst_0_RNIFKEG[25]\); - - \r.m.y_RNO_0[4]\ : NOR3C - port map(A => \y_m_0[4]\, B => \y_m_2[4]\, C => \y_iv_0[4]\, - Y => \y_iv_2[4]\); - - \r.d.inst_0_RNIBGM6[29]\ : OR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_1[0]\, B => - N_3525_3, Y => \de_raddr1_1[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I47_Y_0_o3 : AO1 - port map(A => N467, B => N463_1, C => N466_0, Y => N506); - - \r.w.s.tt[3]\ : DFN1E0 - port map(D => \xc_vectt_1[3]\, CLK => lclk_c, E => N_6747, - Q => \irl[3]\); - - \r.d.pv_RNI2QQLO3\ : NOR3C - port map(A => un2_exbpmiss, B => annul_next_2_sqmuxa_1_6, C - => annul_next_2_sqmuxa_1_8, Y => annul_next_2_sqmuxa_1); - - \r.a.ctrl.inst_RNIJO1S[31]\ : OR2 - port map(A => \inst[31]\, B => N_259, Y => N_363); - - un6_ex_add_res_d0_ADD_33x33_fast_I259_Y_3 : NOR3C - port map(A => I155_un1_Y, B => ADD_33x33_fast_I259_Y_1, C - => I211_un1_Y, Y => ADD_33x33_fast_I259_Y_3); - - \r.e.op1_RNO[22]\ : MX2C - port map(A => \d_i[22]\, B => \d_i[23]\, S => N_227_0, Y - => \aop1[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I16_G0N : OA1 - port map(A => \op1[15]\, B => ldbp1_3, C => \data_0_2[15]\, - Y => N442_1); - - \r.m.ctrl.inst_RNI8BQV3[30]\ : OA1 - port map(A => un5_trap, B => trap_0_sqmuxa_7, C => - me_nullify2_1_2_0, Y => me_nullify2_1_2_1); - - \r.w.s.y_RNO_0[14]\ : NOR2A - port map(A => N_481, B => \result_0[14]\, Y => N_383); - - \comb.branch_address.tmp_ADD_30x30_fast_I71_Y\ : NOR2B - port map(A => N383, B => N380, Y => N488_1); - - \r.a.rsel2_0_RNI7V53_3[0]\ : NOR2A - port map(A => d26_0, B => \rsel2_0[0]\, Y => d25_0); - - \r.a.ctrl.cnt_RNI995L[0]\ : OR2 - port map(A => aluop_0_1_0_a5_1_0_0, B => N_519, Y => - aluop_1_1_0_a5_0); - - \r.w.s.cwp[0]\ : DFN1E0 - port map(D => \cwp_1_0[0]\, CLK => lclk_c, E => holdn, Q - => \cwp[0]\); - - \r.e.aluop_1_RNICGR61[1]\ : OR3A - port map(A => logicout20, B => aluresult_9_sqmuxa_1, C => - miscout69, Y => aluresult_9_sqmuxa); - - \comb.branch_address.tmp_ADD_30x30_fast_I15_G0N\ : NOR2B - port map(A => \inst_0[15]\, B => \dpc[17]\, Y => N403); - - \r.x.ctrl.rd_RNIPVH6[7]\ : XNOR2 - port map(A => \rd_2[7]\, B => \rd_1[7]\, Y => rd_7_i_0); - - \r.x.ctrl.tt[1]\ : DFN1E0 - port map(D => \tt2[1]\, CLK => lclk_c, E => holdn, Q => - \tt[1]\); - - un6_fe_npc_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \fe_pc[10]\, C => - \fe_pc[11]\, Y => N_113); - - \r.e.shleft_RNI44CC2\ : MX2B - port map(A => \shiftin_5[41]\, B => \shiftin_5[25]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[25]\); - - \r.e.ldbp2_RNIJSVH34\ : OR2A - port map(A => \eaddress[25]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[26]\); - - \r.a.ctrl.inst[8]\ : DFN1E0 - port map(D => \inst_0[8]\, CLK => lclk_c, E => holdn, Q => - \inst[8]\); - - \r.w.result[31]\ : DFN1E0 - port map(D => \wdata[31]\, CLK => lclk_c, E => holdn, Q => - \result[31]\); - - \r.e.op2_RNIAVOP[28]\ : MX2 - port map(A => \op2[28]\, B => N_4275, S => ldbp2_2, Y => - \un1_iu0_5[94]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I129_Y : AO1 - port map(A => N530, B => N527_0, C => - ADD_33x33_fast_I129_Y_0, Y => N592_0); - - \r.x.ctrl.inst_RNILD0E[30]\ : NOR2A - port map(A => \inst_3[31]\, B => \inst_3[30]\, Y => y15); - - \r.a.ctrl.inst[6]\ : DFN1E0 - port map(D => \inst_0[6]\, CLK => lclk_c, E => holdn, Q => - \inst[6]\); - - \r.x.result_RNIDU1O3[15]\ : MX2 - port map(A => \un1_iu0_6[15]\, B => \un1_p0_6[367]\, S => - bpdata6_0_0, Y => \bpdata[15]\); - - \r.w.result[25]\ : DFN1E0 - port map(D => \wdata[25]\, CLK => lclk_c, E => holdn, Q => - \result[25]\); - - \r.m.ctrl.inst_RNIVASI1[30]\ : NOR2A - port map(A => trap_0_sqmuxa_1, B => trap63, Y => - \inst_RNIVASI1[30]\); - - \r.e.aluop_0_RNI5BT8N2[0]\ : NOR3C - port map(A => \shiftin_17_m[29]\, B => - \aluresult_1_iv_7[28]\, C => \shiftin_17_m_0[28]\, Y => - \aluresult_1_iv_9[28]\); - - \r.x.rstate_0_RNI17SD2[0]\ : MX2C - port map(A => N_3405, B => \xc_result[14]\, S => - \rstate_0[0]\, Y => \wdata[14]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I206_Y_0_o3_1_0 : MIN3 - port map(A => \data_0[1]\, B => \un1_iu0_6[1]\, C => N397_1, - Y => ADD_33x33_fast_I206_Y_0_o3_1_0_1); - - \comb.branch_address.tmp_ADD_30x30_fast_I237_Y_0_o3\ : OR3A - port map(A => N_59, B => N427, C => - ADD_30x30_fast_I40_Y_0_a3, Y => N704); - - \r.e.invop2_1_RNI7H6D92\ : MX2C - port map(A => \un6_ex_add_res_s2[23]\, B => - \un6_ex_add_res_s0[23]\, S => invop2_1, Y => N_6569); - - \r.m.ctrl.inst_RNI0P0E[23]\ : OR2B - port map(A => \inst_2[23]\, B => \inst[21]\, Y => - inst_3_2_0); - - \r.f.pc_RNIAKM4[8]\ : OR2A - port map(A => \fpc[8]\, B => rst, Y => \pc_m[8]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I262_Y_0_a3 : OR3B - port map(A => N503, B => N778_1, C => N_50, Y => N_51_i_1); - - \r.m.casa_RNO\ : NOR3 - port map(A => N_3356_3, B => annul, C => N_3749_2, Y => - mcasa); - - \r.m.y_RNO[31]\ : AO1C - port map(A => y14_0, B => \logicout[31]\, C => \y_iv_2[31]\, - Y => \y_0[31]\); - - \r.e.ldbp2_1_RNI26N5J2\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[8]\, Y => - \aluresult_m_0[8]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I221_un1_Y\ : NOR3B - port map(A => N551, B => N558, C => N543, Y => I221_un1_Y_0); - - \r.d.pv_RNI21DP7\ : OR3A - port map(A => pv, B => ex_bpmiss_1, C => annul_2, Y => - un5_exbpmiss_i_0); - - \r.d.inst_0_RNIOKIB[25]\ : AOI1 - port map(A => un14_op_1, B => un14_op_2, C => \inst_0[25]\, - Y => \inst_0_m_0[26]\); - - \r.x.ctrl.pc_RNIMH971[20]\ : MX2C - port map(A => \un1_p0_6[372]\, B => \pc_2[20]\, S => - s_3_sqmuxa, Y => N_3411); - - \r.f.pc[28]\ : DFN1E0 - port map(D => \pc_1[28]\, CLK => lclk_c, E => holdn, Q => - \fpc[28]\); - - un6_fe_npc_I_101 : AND2 - port map(A => \fe_pc[17]\, B => \fe_pc[18]\, Y => - \DWACT_FINC_E[11]\); - - \r.m.result[14]\ : DFN1E0 - port map(D => \eres2[14]\, CLK => lclk_c, E => holdn, Q => - \maddress[14]\); - - \r.m.y_RNO_4[8]\ : OR2B - port map(A => \y_1[9]\, B => mulstep_0, Y => \y_m_2[9]\); - - \r.e.shleft_1_RNIANU81\ : MX2 - port map(A => ex_sari_1_1, B => \un1_iu0_6[1]\, S => - shleft_1, Y => \shiftin_5[32]\); - - \r.e.aluop_1_RNI5D5R[1]\ : XOR3 - port map(A => \un1_iu0_6[2]\, B => \aluop_1[1]\, C => - \un1_iu0_5[68]\, Y => N_6907); - - \r.e.op1_RNI57OF[19]\ : NOR2A - port map(A => un17_casaen_0, B => \op1[19]\, Y => - \op1_i_m[19]\); - - \r.a.ctrl.pc[18]\ : DFN1E0 - port map(D => \dpc[18]\, CLK => lclk_c, E => holdn, Q => - \pc[18]\); - - \r.m.result[25]\ : DFN1E0 - port map(D => \eres2[25]\, CLK => lclk_c, E => holdn, Q => - \maddress[25]\); - - \r.e.op1[16]\ : DFN1E0 - port map(D => \aop1[16]\, CLK => lclk_c, E => holdn, Q => - \op1[16]\); - - \r.w.s.y[29]\ : DFN1E0 - port map(D => N_174, CLK => lclk_c, E => holdn, Q => - \y_0[29]\); - - \r.m.ctrl.inst_RNI673A1[23]\ : NOR3 - port map(A => trap_0_sqmuxa_2_2, B => trap27_0, C => - trap_0_sqmuxa_1_2_i, Y => trap27); - - \r.e.shleft_RNIJIFF\ : OR2A - port map(A => \un1_iu0_6[29]\, B => shleft, Y => - \shiftin_5[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I173_Y\ : NOR2 - port map(A => N547, B => N539, Y => N599); - - \r.x.data_0_RNO_5[7]\ : AO1 - port map(A => rdatav_0_1_0_iv_4_22, B => mcdo_m_0_29, C => - rdata_0_sqmuxa, Y => \dco_m_i[127]\); - - \r.x.data_0_RNO[26]\ : OR3 - port map(A => \dco_m_1[122]\, B => \data_0_m[26]\, C => - \data_0_1_4[18]\, Y => \data_0_1[26]\); - - \r.e.jmpl_RNINRDUK\ : OR2B - port map(A => \shiftin_17[5]\, B => aluresult_2_sqmuxa_0, Y - => \shiftin_17_m_0[5]\); - - \r.e.ctrl.pc_RNI20LA2[4]\ : AOI1B - port map(A => \pc[4]\, B => jmpl_0, C => \y_m_1[4]\, Y => - \aluresult_1_iv_2[4]\); - - \r.a.ctrl.pc[27]\ : DFN1E0 - port map(D => \dpc[27]\, CLK => lclk_c, E => holdn, Q => - \pc_0[27]\); - - \r.m.irqen\ : DFN1E0 - port map(D => irqen_0, CLK => lclk_c, E => holdn, Q => - irqen); - - \r.e.op2_RNO_7[20]\ : OA1A - port map(A => \maddress[20]\, B => d27_0, C => - \cpi_m_i[372]\, Y => \d_1_iv_1[20]\); - - \r.m.ctrl.inst_RNI884O1[22]\ : OA1B - port map(A => inst_2_0, B => inst_3_2, C => trap54_1517_0, - Y => \inst_RNI884O1[22]\); - - \r.m.y[2]\ : DFN1E0 - port map(D => \y_1[2]\, CLK => lclk_c, E => holdn, Q => - \y_0[2]\); - - \r.e.ldbp2_RNI2QLA01\ : OR2 - port map(A => aluresult_0_sqmuxa, B => \eaddress[11]\, Y - => \un6_ex_add_res_m[12]\); - - \r.e.aluop_RNISBUL9[1]\ : OA1A - port map(A => N_3974, B => \bpdata[13]\, C => - \bpdata_m_2[5]\, Y => \aluresult_1_iv_4[13]\); - - \r.x.npc_0_RNI9TS61[0]\ : MX2C - port map(A => N_3235, B => N_3265, S => \npc_0[0]\, Y => - \xc_result[24]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I98_Y : NOR3B - port map(A => N482_1, B => N485, C => N_50_0, Y => N561); - - \r.d.inst_0[29]\ : DFN1 - port map(D => \inst_0_RNO[29]\, CLK => lclk_c, Q => - \inst_0[29]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I234_un1_Y\ : OR3C - port map(A => N571_1, B => N587, C => N735, Y => I234_un1_Y); - - un2_rstn_5_0_0_RNIJHKER2 : NOR2B - port map(A => \tmp_m[4]\, B => \pc_4_m[4]\, Y => - \npc_iv_0[4]\); - - \un1_r.w.s.cwp_1_SUM1_0\ : XOR2 - port map(A => CO0, B => SUM1_0_0, Y => N_6528); - - \r.f.pc_RNO_1[20]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[20]\, C => - \pc_1_iv_0[20]\, Y => \pc_1_iv_1[20]\); - - \r.e.op1_RNIRSTH[10]\ : MX2 - port map(A => \op1[10]\, B => \data_0[10]\, S => ldbp1_2, Y - => \un1_iu0_6[10]\); - - \r.x.data_0_RNIE343[4]\ : XOR2 - port map(A => \data_0[4]\, B => invop2, Y => N_3308); - - un6_ex_add_res_d1_ADD_33x33_fast_I300_Y_0_0 : XOR2 - port map(A => \un1_iu0_6[9]\, B => \op2[9]\, Y => - ADD_33x33_fast_I300_Y_0_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I240_un1_Y\ : OR3C - port map(A => N583, B => N599, C => N614, Y => I240_un1_Y); - - \r.x.result_RNIOA2O3[25]\ : MX2C - port map(A => \un1_iu0_6[25]\, B => \un1_p0_6[377]\, S => - bpdata6_0_0, Y => \bpdata[25]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I213_un1_Y : OR2B - port map(A => N642_1, B => N627, Y => I213_un1_Y_i); - - \comb.branch_address.tmp_ADD_30x30_fast_I49_Y_i\ : OA1 - port map(A => \dpc[20]\, B => \inst_0[18]\, C => N416_2, Y - => N_14); - - \comb.branch_address.tmp_ADD_30x30_fast_I20_G0N\ : NOR2B - port map(A => \inst_0[20]\, B => \dpc[22]\, Y => N418_2); - - \r.e.op2_RNO_8[30]\ : OR3B - port map(A => d29_0, B => \imm[30]\, C => \rsel2[0]\, Y => - \imm_m_i[30]\); - - \r.x.y[17]\ : DFN1E0 - port map(D => \y[17]\, CLK => lclk_c, E => holdn, Q => - \y_2[17]\); - - \r.e.op2_RNO_0[7]\ : OR3C - port map(A => \op1_m_i[7]\, B => \d_1_iv_3[7]\, C => - \aluresult_m_i[7]\, Y => \d_1[7]\); - - \r.e.ctrl.tt_RNO_2[5]\ : NOR3A - port map(A => ticc, B => trap_1, C => \tt_4[3]\, Y => - \tt_9_0_a3_0_1[5]\); - - \r.d.inst_0_RNI5423[23]\ : OR2B - port map(A => \inst_0_0[24]\, B => \inst_0_0[23]\, Y => - N_89); - - un6_ex_add_res_d1_ADD_33x33_fast_I43_Y : MAJ3 - port map(A => \op2[25]\, B => \un1_iu0_6[25]\, C => N469, Y - => N502); - - un6_fe_npc_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \fe_pc[8]\, Y => N_126_0); - - \r.e.ctrl.inst_RNIDC0E[20]\ : OR2 - port map(A => \inst_1[21]\, B => \inst_1[20]\, Y => - aluresult_11_sqmuxa_4); - - \r.w.s.tba_RNIIC7GK[19]\ : NOR3C - port map(A => \bpdata_m_2[7]\, B => \aluresult_1_iv_3[31]\, - C => \aluresult_1_iv_4[31]\, Y => \aluresult_1_iv_6[31]\); - - \r.x.result[28]\ : DFN1E0 - port map(D => \maddress[28]\, CLK => lclk_c, E => holdn, Q - => \result_0[28]\); - - \r.a.rsel2_0_RNI7V53[0]\ : OR2A - port map(A => d28_0_0, B => \rsel2_0[0]\, Y => d27_0); - - \r.e.alusel_RNO[1]\ : NOR3B - port map(A => N_500, B => \alusel_i_0_o5_0[1]\, C => - \alusel_i_0_1[1]\, Y => N_3840); - - un6_ex_add_res_d1_ADD_33x33_fast_I321_Y_0 : AX1C - port map(A => I260_un1_Y, B => ADD_33x33_fast_I260_Y_3_1, C - => ADD_33x33_fast_I321_Y_0_0, Y => - \un6_ex_add_res_s1_i[31]\); - - \r.x.data_0_RNIAF9E[13]\ : XOR2 - port map(A => \data_0[13]\, B => invop2_1, Y => N_4260); - - \r.m.y_RNO_4[1]\ : OR2B - port map(A => \y_0[2]\, B => mulstep_1, Y => N_381); - - \comb.branch_address.tmp_ADD_30x30_fast_I5_P0N\ : OR2 - port map(A => \inst_0[5]\, B => \dpc[7]\, Y => N374); - - \r.x.npc_0_RNI3DS61[0]\ : MX2C - port map(A => N_3224, B => N_3254, S => \npc_0[0]\, Y => - \xc_result[13]\); - - \r.w.s.et_RNIGF034\ : AOI1B - port map(A => et_0_sqmuxa, B => rstate_6314_d, C => et, Y - => et_m); - - \r.e.op1_RNIP3LOJ2[7]\ : NOR3C - port map(A => \op1_m_0[7]\, B => \d_iv_2[7]\, C => - \aluresult_m_0[7]\, Y => \d_i[7]\); - - \r.e.alucin_RNO_4\ : OA1 - port map(A => N_203, B => \inst[30]\, C => \inst[31]\, Y - => cin_iv_i_0); - - \r.m.y_RNO_2[31]\ : OR2B - port map(A => wy_RNIMKUI, B => \y_2[31]\, Y => \y_m_0[31]\); - - \r.a.ctrl.inst_RNIV03A1[21]\ : OR3 - port map(A => N_201, B => N_216, C => N_225, Y => N_602); - - \r.w.s.cwp[1]\ : DFN1E0 - port map(D => \cwp_1[1]\, CLK => lclk_c, E => holdn, Q => - \cwp_0[1]\); - - \r.x.rstate_0_RNI2HJE2[0]\ : MX2C - port map(A => N_3414, B => \xc_result[23]\, S => - \rstate_0[0]\, Y => \wdata[23]\); - - \r.x.ctrl.wicc_RNISNBL\ : NOR3B - port map(A => rst, B => wicc, C => annul_1_0, Y => - icc_0_sqmuxa_1); - - \r.e.op2_RNO_3[28]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[28]\, Y => - \aluresult_m_i[28]\); - - \r.m.result_RNI00P1[16]\ : OR2B - port map(A => d13, B => \maddress[16]\, Y => - \result_m_0[16]\); - - \r.e.bp_RNI77CD\ : NOR3B - port map(A => bp_0, B => \inst_2[28]\, C => annul, Y => - N_482); - - un6_ex_add_res_d1_ADD_33x33_fast_I122_Y : NOR2B - port map(A => ADD_33x33_fast_I122_Y_0, B => N519_1, Y => - N585_0); - - \r.m.y_RNIJ59V2[31]\ : AOI1B - port map(A => \y[31]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[31]\, Y => \aluresult_1_iv_0[31]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I156_Y\ : AOI1 - port map(A => N530_1, B => N523, C => N522, Y => N582_0); - - \r.x.rstate_0_RNI1B24[0]\ : OR2A - port map(A => rst, B => \rstate_0[0]\, Y => N_6358); - - un6_ex_add_res_d1_ADD_33x33_fast_I31_P0N : OR2 - port map(A => \un1_iu0_6[30]\, B => \op2[30]\, Y => N488_0); - - \r.e.aluop_0_RNI5I6K2[1]\ : MX2C - port map(A => \logicout_4[30]\, B => N_6853, S => - N_6866_i_0, Y => N_3653); - - \comb.lock_gen.un1_icc_check5_RNO_3\ : OR3B - port map(A => N_3515_1, B => N_3834_2, C => \inst_0_0[22]\, - Y => icc_check10); - - \r.e.op1_RNI6KL5C5[18]\ : NOR3C - port map(A => \op1_m_0[18]\, B => \d_iv_2[18]\, C => - \aluresult_m_0[18]\, Y => \d_i[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I249_un1_Y : NOR3A - port map(A => N552_1, B => N603_i, C => N611, Y => - I249_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I296_Y_0 : XNOR3 - port map(A => \un1_iu0_6[5]\, B => \op2[5]\, C => N676_1, Y - => \un6_ex_add_res_s1_i[6]\); - - \r.e.op2_RNO_3[15]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[15]\, Y => - \aluresult_m_i[15]\); - - \r.e.ctrl.rd_RNI7QPB1[4]\ : XA1C - port map(A => \un3_de_ren1[95]\, B => \rd_0[4]\, C => - wreg_2, Y => wreg_2_0); - - \r.x.data_0_RNO_1[17]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_2_17, Y => - \dco_m_0[113]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I206_Y_0_a3 : NOR2B - port map(A => N614_2, B => N407_1, Y => - ADD_33x33_fast_I206_Y_0_a3_0); - - \r.a.ctrl.rd_RNO[1]\ : OR2A - port map(A => N_85, B => \inst_0[26]\, Y => \rd_3[1]\); - - \r.d.pc[8]\ : DFN1 - port map(D => \pc_RNO[8]\, CLK => lclk_c, Q => \dpc[8]\); - - \r.e.op1_RNIVM9G[29]\ : OR2B - port map(A => \op1[29]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[29]\); - - \r.e.ldbp2_2_RNIQLAKN3\ : OR2A - port map(A => \eaddress[22]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[23]\); - - \r.e.aluop_RNIEPDN4[2]\ : OR2A - port map(A => aluresult_5_sqmuxa, B => \bpdata[11]\, Y => - \aluop_RNIEPDN4[2]\); - - \r.f.pc_RNO_5[20]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[20]\, Y => \xc_trap_address_m[20]\); - - \r.a.rsel1_0_RNID7LJ2[2]\ : OR2B - port map(A => data1(23), B => d11_0, Y => \rfo_m[23]\); - - \r.m.ctrl.annul_RNIE1G3\ : OR2A - port map(A => \rstate_0[0]\, B => annul_5, Y => - annul_1tt_N_5); - - \r.x.data_0_RNO[27]\ : OR3 - port map(A => \dco_m_1[123]\, B => \data_0_m[27]\, C => - \data_0_1_4[18]\, Y => \data_0_1[27]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I288_Y_0_0\ : XOR2 - port map(A => \dpc[30]\, B => \inst_0_1[30]\, Y => - ADD_30x30_fast_I288_Y_0_0); - - \r.a.rsel1_RNIU3DLA2[0]\ : OR2B - port map(A => un14_casaen_s0_0, B => \aluresult[5]\, Y => - N_408); - - \r.a.ctrl.inst[7]\ : DFN1E0 - port map(D => \inst_0[7]\, CLK => lclk_c, E => holdn, Q => - \inst[7]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I266_Y_0\ : XOR2 - port map(A => N612, B => ADD_30x30_fast_I266_Y_0_0, Y => - \tmp[8]\); - - \r.f.pc_RNO_3[18]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[18]\, C => - \xc_trap_address_m[18]\, Y => \pc_1_iv_0[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I153_Y\ : NOR2B - port map(A => N527_2, B => N519, Y => N579); - - \r.x.ctrl.wicc_RNISNBL_0\ : NOR3A - port map(A => rst, B => wicc, C => annul_1_0, Y => - icc_2_sqmuxa_1); - - \r.e.aluop_0_RNINM3Q5[0]\ : MX2C - port map(A => N_3584, B => N_3648, S => \aluop_0[0]\, Y => - \logicout[25]\); - - \r.m.icc_RNO_0[2]\ : MX2C - port map(A => N_4182, B => \icc_0[2]\, S => wicc_3, Y => - N_4187); - - \r.e.ctrl.rd_RNIVO2A1[1]\ : XA1A - port map(A => \un3_de_ren1[92]\, B => \rd[1]\, C => - un2_rs1_1_2_i_0, Y => wreg_2_2); - - \r.m.ctrl.pc[18]\ : DFN1E0 - port map(D => \pc_0[18]\, CLK => lclk_c, E => holdn, Q => - \pc_3[18]\); - - \r.x.ctrl.pc_RNIF9971[10]\ : MX2C - port map(A => \un1_p0_6[362]\, B => \pc[10]\, S => - s_3_sqmuxa_0, Y => N_3401); - - \r.e.ctrl.tt_RNO[2]\ : NOR3 - port map(A => N_4039, B => \tt_0[2]\, C => N_4033_i, Y => - \tt_1[2]\); - - \r.e.ctrl.annul_RNI5L7FE1_0\ : NOR3 - port map(A => un2_rstn_5_0_i, B => un12_de_hold_pc, C => - de_hold_pc_1_0, Y => un2_rstn_3_0); - - \r.m.result_RNI52TD3[22]\ : NOR3C - port map(A => \d_iv_0[22]\, B => \result_m_0[22]\, C => - \rfo_m[22]\, Y => \d_iv_2[22]\); - - \r.w.s.icc_RNO_1[3]\ : OR2B - port map(A => icc_0_sqmuxa, B => \icc_2[3]\, Y => - \icc_m_0[3]\); - - \r.m.result_RNO[27]\ : MX2 - port map(A => \aluresult[27]\, B => \op1[27]\, S => - un17_casaen_0_1, Y => \eres2[27]\); - - \r.a.ctrl.inst_RNI6C0E[21]\ : OR2B - port map(A => \inst[30]\, B => \inst_2[21]\, Y => N_519); - - un6_ex_add_res_d1_ADD_33x33_fast_I1_P0N : OR2 - port map(A => \un1_iu0_6[0]\, B => \op2[0]\, Y => N398_0); - - \r.d.annul_RNI35C5\ : NOR2 - port map(A => annul_1, B => un54_casaen, Y => ldchkra_0); - - \r.d.inst_0_RNIBO9C[23]\ : OR3B - port map(A => \inst_0_0[22]\, B => icc_check7_2, C => - \inst_0_0[23]\, Y => icc_check7_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I265_Y_1 : AOI1B - port map(A => N652, B => N637_0, C => - ADD_33x33_fast_I265_Y_0, Y => ADD_33x33_fast_I265_Y_1_0); - - \r.w.s.tba_RNIFA6JB[9]\ : NOR3C - port map(A => \aluresult_1_iv_2[21]\, B => \tba_m[9]\, C - => \aluresult_1_iv_3[21]\, Y => \aluresult_1_iv_5[21]\); - - \r.w.result_RNI3I2L[27]\ : AOI1B - port map(A => \un1_p0_6[379]\, B => d14_0, C => - \result_m_0_0[27]\, Y => \d_iv_0[27]\); - - \r.d.inull_RNIFV6VG2_0\ : OA1B - port map(A => holdn, B => \de_hold_pc_1\, C => mds, Y => - inull_RNIFV6VG2_0); - - \r.d.inst_0_RNI5C23_0[31]\ : OR2A - port map(A => \inst_0[30]\, B => \inst_0[31]\, Y => N_85); - - \comb.branch_address.tmp_ADD_30x30_fast_I51_Y\ : OA1 - port map(A => \dpc[20]\, B => \inst_0[18]\, C => N410, Y - => N468); - - \r.x.ctrl.annul_RNI2ROB\ : OR2A - port map(A => \un1_p0_6[349]\, B => annul_0, Y => annul_1_0); - - \r.a.ctrl.cnt_RNI3T47[0]\ : OR2A - port map(A => \cnt_1[0]\, B => \cnt_2[1]\, Y => - aluop_0_1_0_a5_1_0_0); - - \r.a.ctrl.inst_RNIH95V1[20]\ : AOI1B - port map(A => inst_32_1, B => inst_32_0, C => inst_21, Y - => illegal_inst34_0); - - \r.e.op2_RNIRI992[11]\ : AOI1B - port map(A => \un1_iu0_5[77]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[11]\); - - \r.x.ctrl.pc_RNIMR431[7]\ : MX2C - port map(A => \un1_p0_6[359]\, B => \pc[7]\, S => - s_3_sqmuxa_0, Y => N_3398); - - \r.w.result_RNI7PA4[0]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[0]\, Y - => \result_m_0_0[0]\); - - \un1_r.w.s.cwp_1_SUM1_0_0\ : XOR2 - port map(A => et_RNI1BRF2, B => \cwp_0[1]\, Y => SUM1_0_0); - - \r.d.inst_0[23]\ : DFN1 - port map(D => \inst_0_RNO[23]\, CLK => lclk_c, Q => - \inst_0_0[23]\); - - \r.e.shcnt_RNILEIO4[3]\ : MX2 - port map(A => \shiftin_8[22]\, B => \shiftin_8[14]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[14]\); - - \r.e.ldbp2_2_RNIFB78T1\ : OR2A - port map(A => annul_RNI5L7FE1, B => \eaddress[6]\, Y => - ldbp2_2_RNIFB78T1); - - \r.d.inst_0_RNI4EL7[30]\ : AO1 - port map(A => fins_0_a3_0, B => N_3834_2, C => \inst_0[30]\, - Y => N_3832); - - un6_ex_add_res_d2_ADD_33x33_fast_I263_Y : OR2 - port map(A => I263_un1_Y_0, B => ADD_33x33_fast_I263_Y_1_0, - Y => N772_0); - - \r.a.ticc\ : DFN1E0 - port map(D => ticc_exception, CLK => lclk_c, E => holdn, Q - => ticc); - - \r.a.rsel2_RNI9LB[1]\ : NOR2A - port map(A => \rsel2[1]\, B => \rsel2[2]\, Y => d28_0_0); - - \r.m.ctrl.cnt_RNIQA5L[0]\ : OR3 - port map(A => \cnt_1[1]\, B => \cnt_0[0]\, C => un5_trap, Y - => trap_1_sqmuxa_1); - - \r.e.op2_RNO_7[31]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[383]\, - Y => \cpi_m_i[383]\); - - \r.e.ctrl.rd[1]\ : DFN1E0 - port map(D => \rd_2[1]\, CLK => lclk_c, E => holdn, Q => - \rd[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I124_Y : NOR2 - port map(A => N525_0, B => N521_0, Y => N587_1); - - \r.m.ctrl.rd[6]\ : DFN1E0 - port map(D => \rd_0[6]\, CLK => lclk_c, E => holdn, Q => - \rd_1[6]\); - - \r.e.op2_RNO_5[22]\ : AOI1B - port map(A => \result[22]\, B => d31_0, C => \imm_m_i[22]\, - Y => \d_1_iv_0[22]\); - - \r.e.aluop_0_RNIMMJ24[0]\ : OR2B - port map(A => \logicout[3]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[3]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I307_Y_0_1 : XNOR2 - port map(A => \un1_iu0_6[16]\, B => \data_0[16]\, Y => - \un6_ex_add_res_s0_1[17]\); - - \r.m.ctrl.pc_RNISHGF[31]\ : MX2 - port map(A => \pc_3[31]\, B => \pc_0[31]\, S => \npc_1[1]\, - Y => N_3272); - - \r.e.ctrl.inst_RNILG1E[21]\ : NOR2 - port map(A => \inst[19]\, B => \inst_1[21]\, Y => - aluresult_13_sqmuxa_0_0); - - \r.w.s.dwt_RNI7TJM3\ : NOR2B - port map(A => \aluresult_1_iv_0[14]\, B => \ex_op2_m[14]\, - Y => \aluresult_1_iv_1[14]\); - - \r.e.shcnt_RNIOC3GA[2]\ : MX2C - port map(A => \shiftin_11[11]\, B => \shiftin_11[7]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[7]\); - - \r.f.pc_RNO_1[17]\ : AOI1B - port map(A => annul_RNI5L7FE1, B => \eaddress[17]\, C => - \pc_1_iv_0[17]\, Y => \pc_1_iv_1[17]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I250_Y_0_a3 : NOR2B - port map(A => N672_1, B => N419, Y => - ADD_33x33_fast_I250_Y_0_a3_0); - - \r.e.shleft_0_RNIANBQ1\ : MX2A - port map(A => \shiftin_5[17]\, B => shleft_0_RNIU2BG, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I140_Y : OR2B - port map(A => N541, B => N537_2, Y => N603_i); - - un6_ex_add_res_d0_ADD_33x33_fast_I266_Y_0_o3 : OR2 - port map(A => N506_0, B => N_74, Y => N778_0); - - \r.w.s.tba[19]\ : DFN1E1 - port map(D => \result_0[31]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[19]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I17_P0N\ : OR2 - port map(A => \inst_0[17]\, B => \dpc[19]\, Y => N410); - - \r.f.pc_RNO_1[9]\ : NOR2B - port map(A => \xc_trap_address_m[9]\, B => \pc_4_m[9]\, Y - => \pc_1_iv_0[9]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I100_Y_0\ : MIN3 - port map(A => \dpc[23]\, B => \un1_p0_6_0[60]\, C => N418_2, - Y => ADD_30x30_fast_I100_Y_0); - - \r.e.ldbp2_RNIIHL2K3\ : OR3C - port map(A => \aluresult_1_iv_7[13]\, B => - \shiftin_17_m_0[13]\, C => \un6_ex_add_res_m[14]\, Y => - \aluresult[13]\); - - \r.e.aluop_RNIPR2R4[2]\ : OR2A - port map(A => aluresult_5_sqmuxa, B => \bpdata[12]\, Y => - \aluop_RNIPR2R4[2]\); - - \r.d.inst_0[24]\ : DFN1 - port map(D => \inst_0_RNO[24]\, CLK => lclk_c, Q => - \inst_0_0[24]\); - - \r.e.op1_RNISUNP1[9]\ : AO1A - port map(A => \op1[9]\, B => \un17_casaen_0_0\, C => - \ex_op1_i_m[9]\, Y => \edata2_0_iv_0[9]\); - - \r.d.inull_RNIBBMHS\ : NOR2A - port map(A => \hold_pc_7\, B => ldlock, Y => un18_hold_pc); - - \r.m.icc_RNO_22[2]\ : NOR2 - port map(A => \logicout[19]\, B => \logicout[25]\, Y => - icc_0_sqmuxa_1_8); - - \r.e.op1_RNIL20JT1[0]\ : OR2B - port map(A => \d_1_iv_4[0]\, B => \aluresult_m_i[0]\, Y => - \d_1[0]\); - - \r.d.cwp_RNO[2]\ : MX2 - port map(A => N_4229, B => \cwp_1_0[2]\, S => N_6358, Y => - \cwp_1[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I71_Y_0 : AO1B - port map(A => N431_2, B => N427_2, C => N430_1, Y => N530_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I11_G0N : OA1 - port map(A => \op1[10]\, B => ldbp1_2, C => \data_0[10]\, Y - => N427_2); - - \r.a.rsel2_RNI7V53_0[1]\ : NOR3B - port map(A => \rsel2[2]\, B => \rsel2[1]\, C => - \rsel2_0[0]\, Y => d31_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I0_CO1\ : NOR2B - port map(A => \inst_0_RNI0FUM[0]\, B => \dpc[2]\, Y => N358); - - \r.f.pc_RNO_1[26]\ : AOI1B - port map(A => un2_rstn_3_0, B => \eaddress[26]\, C => - \pc_1_iv_0[26]\, Y => \pc_1_iv_1[26]\); - - \r.d.pc_RNO[13]\ : MX2 - port map(A => \fpc[13]\, B => \dpc[13]\, S => N_6763_i_0, Y - => \pc_RNO[13]\); - - \r.d.inst_0_RNIJVPR[14]\ : MX2B - port map(A => \inst_0[14]\, B => \inst_0_m_0[26]\, S => - rs1mod, Y => \rs1_iv_i_0[0]\); - - \r.d.inst_0_RNO_0[17]\ : MX2 - port map(A => data_0_0_17, B => \inst_0[17]\, S => - mexc_1_sqmuxa_1_0, Y => N_4617); - - \r.m.y_RNO_0[22]\ : AOI1B - port map(A => wy_1_0, B => \y_0[22]\, C => \y_m[22]\, Y => - \y_iv_1[22]\); - - \r.e.shleft_1_RNIS94T2\ : MX2C - port map(A => \shiftin_5[56]\, B => \shiftin_5[40]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[40]\); - - \r.e.op2_RNI3B4V1[20]\ : AOI1B - port map(A => \un1_iu0_5[86]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[20]\); - - \r.e.op2_RNIBGNB1[17]\ : OR2A - port map(A => \un1_iu0_5[83]\, B => \un1_iu0_6[17]\, Y => - \logicout_4[17]\); - - \r.x.data_0[15]\ : DFN1E0 - port map(D => \data_0_1[15]\, CLK => lclk_c, E => - mexc_1_sqmuxa_0, Q => \data_0_2[15]\); - - \r.e.shcnt_RNIFN69J[1]\ : MX2C - port map(A => \shiftin_14[5]\, B => \shiftin_14[3]\, S => - \ex_shcnt_1_i_0[1]\, Y => \shiftin_17[3]\); - - \r.d.inst_0_RNI6MTD1[4]\ : NOR2 - port map(A => \inst_0_RNI2NUM[2]\, B => \inst_0_RNI4VUM[4]\, - Y => un1_rs1_1); - - \r.w.s.pil[0]\ : DFN1E0 - port map(D => \result[8]\, CLK => lclk_c, E => N_6699, Q - => \pil[0]\); - - \r.w.result_RNIKJD4[22]\ : OR3C - port map(A => N_484_0, B => \rsel1_0[2]\, C => \result[22]\, - Y => \result_m_0_0[22]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I61_Y : MIN3 - port map(A => \data_0[16]\, B => \un1_iu0_6[16]\, C => - N442_1, Y => N520_2); - - \r.d.inst_0_RNINSV2_0[31]\ : NOR2 - port map(A => \inst_0[31]\, B => annul_1, Y => N_3033_1_i); - - \r.d.inst_0_RNIA423[25]\ : NOR2 - port map(A => \inst_0[25]\, B => \inst_0[27]\, Y => - annul_next_1_sqmuxa_1_1); - - \r.a.imm_RNO[21]\ : MX2 - port map(A => \inst_0[11]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[139]\); - - \r.x.result_RNIFC6E[11]\ : MX2 - port map(A => \result_0[11]\, B => \data_0_2[11]\, S => - ld_4, Y => \un1_p0_6[363]\); - - \r.x.result[13]\ : DFN1E0 - port map(D => \maddress[13]\, CLK => lclk_c, E => holdn, Q - => \result_0[13]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I18_P0N : OR2 - port map(A => \un1_iu0_6[17]\, B => \op2[17]\, Y => N449_1); - - \r.m.ctrl.trap\ : DFN1E0 - port map(D => trap_0, CLK => lclk_c, E => holdn, Q => - trap_2); - - \r.e.shcnt[3]\ : DFN1E0 - port map(D => N_269_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[3]\); - - \r.x.ctrl.annul_RNI5S7L\ : NOR2 - port map(A => \rstate_d[2]\, B => xc_wreg9, Y => s_3_sqmuxa); - - un6_ex_add_res_d1_ADD_33x33_fast_I263_un1_Y : OR3C - port map(A => N649_1, B => N633_1, C => N808_0, Y => - I263_un1_Y_i); - - \r.e.op2_RNO_6[6]\ : OR2B - port map(A => data2(6), B => d25_0, Y => \rfo_m_i[38]\); - - \r.w.s.y[20]\ : DFN1E0 - port map(D => N_3784, CLK => lclk_c, E => N_6922_i_0, Q => - \y[20]\); - - \r.a.nobp_RNO\ : OAI1 - port map(A => N_150, B => \inst_0[19]\, C => nobp_RNO_0, Y - => nobp_1); - - \r.x.ctrl.annul_RNI5S7L_0\ : NOR2 - port map(A => \rstate_d[2]\, B => xc_wreg9, Y => - s_3_sqmuxa_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I36_Y : NOR2A - port map(A => N482, B => N485_i_0, Y => N495_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I4_P0N : OR2 - port map(A => \un1_iu0_6[3]\, B => \op2[3]\, Y => N407); - - \comb.branch_address.tmp_ADD_30x30_fast_I235_Y_0\ : NOR3B - port map(A => I36_un1_Y_i, B => I92_un1_Y, C => N433, Y => - ADD_30x30_fast_I235_Y_0); - - \r.m.y_RNO_4[5]\ : OR3A - port map(A => \y_1[5]\, B => wy_3, C => wy_1_0_1, Y => - \y_m_2[5]\); - - \r.e.op1_RNIPD7JF[31]\ : NOR3B - port map(A => \aluop_RNIESJP4[2]\, B => \edata2_iv_1[31]\, - C => \bpdata_i_m_2[7]\, Y => edata2_iv_i_0(31)); - - \comb.branch_address.tmp_ADD_30x30_fast_I273_Y_0_0\ : XOR2 - port map(A => \dpc[15]\, B => \inst_0[13]\, Y => - ADD_30x30_fast_I273_Y_0_0); - - \r.f.pc_RNO_6[31]\ : MX2 - port map(A => \fpc[31]\, B => \eaddress[31]\, S => jump_0, - Y => N_4074); - - \r.f.pc_RNO_1[2]\ : NOR2B - port map(A => \xc_trap_address_m[2]\, B => \pc_4_m[2]\, Y - => \pc_1_iv_0[2]\); - - \r.e.shcnt_RNIOC6GJ[1]\ : MX2C - port map(A => \shiftin_14[4]\, B => \shiftin_14[2]\, S => - \ex_shcnt_1_i[1]\, Y => \shiftin_17[2]\); - - \r.e.ldbp2_2_RNIGN3I1\ : OR2A - port map(A => \eaddress[0]\, B => aluresult_0_sqmuxa_0, Y - => \un6_ex_add_res_m[1]\); - - \r.e.jmpl_RNIRC5C\ : OR2 - port map(A => jmpl, B => aluresult12, Y => - aluresult_0_sqmuxa_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I287_Y_0\ : XOR2 - port map(A => N698, B => ADD_30x30_fast_I287_Y_0_0, Y => - \tmp[29]\); - - \r.e.op2_RNO_1[18]\ : OR2B - port map(A => \op1[18]\, B => un14_casaen_s1, Y => - \op1_m_i[18]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I261_Y_1 : NOR3B - port map(A => I99_un1_Y, B => I159_un1_Y, C => N496, Y => - ADD_33x33_fast_I261_Y_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I302_Y_0 : XNOR3 - port map(A => \un1_iu0_6[11]\, B => \op2[11]\, C => N808_0, - Y => \un6_ex_add_res_s1_i[12]\); - - \r.d.annul_RNI6C772\ : MX2 - port map(A => hold_pc_0_sqmuxa, B => N_108, S => - branch_1_sqmuxa_i, Y => branch_0); - - \r.x.rstate_RNI5S7L_0[1]\ : NOR2 - port map(A => \rstate_d[2]\, B => annul_1_0, Y => - xc_wreg_0_sqmuxa); - - \r.e.op2[28]\ : DFN1E0 - port map(D => N_312, CLK => lclk_c, E => holdn, Q => - \op2[28]\); - - \r.x.data_0_RNICN9E[30]\ : XOR2 - port map(A => \data_0[30]\, B => invop2_0, Y => N_4277); - - un6_ex_add_res_d2_ADD_33x33_fast_I300_Y_0 : AX1D - port map(A => I249_un1_Y, B => N668_0, C => - \un6_ex_add_res_s2_1[10]\, Y => \un6_ex_add_res_s2[10]\); - - \r.e.ctrl.pc[5]\ : DFN1E0 - port map(D => \pc_0[5]\, CLK => lclk_c, E => holdn, Q => - \pc[5]\); - - \r.e.aluop_RNIJV794[1]\ : OR2B - port map(A => edata_2_sqmuxa, B => \bpdata[29]\, Y => - \bpdata_i_m[29]\); - - \r.e.aluop_1_RNID9JD1[1]\ : XOR3 - port map(A => \un1_iu0_6[26]\, B => \aluop_1[1]\, C => - \un1_iu0_5[92]\, Y => N_6859); - - \r.m.ctrl.inst_RNI7P1E[23]\ : OR2B - port map(A => \inst_2[23]\, B => \inst_3[19]\, Y => - trap27_0); - - \r.e.jmpl_RNICFD1K\ : OR2B - port map(A => \shiftin_17[3]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[3]\); - - \r.f.pc_RNO_7[28]\ : MX2 - port map(A => \fpc[28]\, B => \tba[16]\, S => rstate_6314_d, - Y => \xc_trap_address[28]\); - - \r.e.alucin_RNO_2\ : OR2A - port map(A => N_207, B => N_518, Y => alucin_RNO_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I18_G0N : NOR2B - port map(A => \un1_iu0_6[17]\, B => \op2[17]\, Y => N448_0); - - \r.e.aluop_RNIB1134[1]\ : OR2B - port map(A => \bpdata[1]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[1]\); - - \comb.v.x.data_0_1_1_iv_RNO_0[31]\ : AO1A - port map(A => ld_0_0, B => \data_0_0[31]\, C => - \dco_m_1[127]\, Y => \data_0_1_1_iv_0[31]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I12_G0N : NOR2B - port map(A => \un1_iu0_6[11]\, B => \op2[11]\, Y => N430); - - \r.f.pc_RNO_5[26]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[26]\, Y => \xc_trap_address_m[26]\); - - \r.x.data_0_RNO[24]\ : OR3A - port map(A => \data_0_1_1_iv_1[24]\, B => \rdata_13_m_9[8]\, - C => \data_0_1_1[16]\, Y => \data_0_1[24]\); - - \r.a.rfa1[1]\ : DFN1E0 - port map(D => \un3_de_ren1[92]\, CLK => lclk_c, E => holdn, - Q => \rfa1[1]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I304_Y_0 : XOR3 - port map(A => \un1_iu0_6[13]\, B => \op2[13]\, C => N802_0, - Y => \un6_ex_add_res_s1[14]\); - - \r.x.ctrl.pc[19]\ : DFN1E0 - port map(D => \pc_2[19]\, CLK => lclk_c, E => holdn, Q => - \pc_0[19]\); - - \r.e.ctrl.annul_RNIMA264_0\ : AOI1 - port map(A => jump_1_sqmuxa_1_i_0, B => jump_0_sqmuxa_1_i_0, - C => annul, Y => jump); - - \r.a.ctrl.inst[19]\ : DFN1E0 - port map(D => \inst_0[19]\, CLK => lclk_c, E => holdn, Q - => \inst_2[19]\); - - \r.f.pc_RNO_4[15]\ : MX2 - port map(A => I_77, B => N_4058, S => bpmiss_1_i_0_0, Y => - \pc_4[15]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I78_Y : OA1 - port map(A => \op2[8]\, B => \un1_iu0_6[8]\, C => N419_1, Y - => N537_1); - - \r.m.result_RNO[14]\ : MX2 - port map(A => \aluresult[14]\, B => \op1[14]\, S => - un17_casaen_0_2, Y => \eres2[14]\); - - \r.m.ctrl.rett_RNO\ : NOR2A - port map(A => rett_3, B => annul, Y => rett_1_3); - - un6_ex_add_res_d0_ADD_33x33_fast_I120_Y : NOR2B - port map(A => N521, B => N517, Y => N583_0); - - \r.x.npc_RNI6T411[0]\ : MX2C - port map(A => N_3230, B => N_3260, S => \npc[0]\, Y => - \xc_result[19]\); - - \r.e.shleft_RNID1G13\ : MX2 - port map(A => \shiftin_5[48]\, B => \shiftin_5[32]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[32]\); - - \r.e.shleft_0_RNIFRBQ1\ : MX2C - port map(A => \shiftin_5[22]\, B => \shiftin_5[6]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[6]\); - - \r.e.op2_RNO_2[23]\ : OR2B - port map(A => data2(23), B => d25, Y => \rfo_m_i[55]\); - - \r.x.data_0_RNO[28]\ : OR3 - port map(A => \dco_m_1[124]\, B => \data_0_m[28]\, C => - \data_0_1_4[18]\, Y => \data_0_1[28]\); - - \r.x.ctrl.tt_RNO_1[3]\ : MX2C - port map(A => irl_0(3), B => \tt_2[3]\, S => tt_0_sqmuxa, Y - => N_4207); - - \r.w.s.et_RNIM09S\ : NOR3A - port map(A => y15, B => error_1_sqmuxa, C => annul_1_0, Y - => rstate_4_1); - - \comb.ld_align.rdata199\ : OR2A - port map(A => \me_size_1[0]\, B => \me_size_1[1]\, Y => - rdata199); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y_3 : AOI1B - port map(A => N642, B => N627_0, C => - ADD_33x33_fast_I260_Y_2, Y => ADD_33x33_fast_I260_Y_3); - - un6_ex_add_res_d0_ADD_33x33_fast_I135_Y : AO1 - port map(A => N536_0, B => N533, C => N532, Y => N598_0); - - \r.m.y_RNO_4[22]\ : OR2B - port map(A => \y[23]\, B => mulstep_0, Y => \y_m[23]\); - - \r.e.op1_RNIU77Q34[14]\ : NOR3C - port map(A => \op1_m_0[14]\, B => \d_iv_2[14]\, C => - \aluresult_m_0[14]\, Y => \d_i[14]\); - - \r.x.ctrl.inst_RNI05531[27]\ : NOR3A - port map(A => y_0_sqmuxa_2, B => \inst[28]\, C => - \inst[27]\, Y => y_0_sqmuxa_3); - - \r.a.ctrl.rd_RNO[4]\ : NOR2A - port map(A => \DWACT_ADD_CI_0_partial_sum_2[0]\, B => - un3_reg, Y => N_33); - - \r.a.ctrl.wreg_RNO_3\ : AO1A - port map(A => call_hold5_0, B => un3_op2, C => - write_reg_4_sqmuxa, Y => un1_ld_1_sqmuxa_1_0); - - \r.e.aluop_RNIESJP4[2]\ : OR2A - port map(A => edata_1_sqmuxa, B => \bpdata[15]\, Y => - \aluop_RNIESJP4[2]\); - - \r.a.ctrl.inst_RNI9G0L[20]\ : OR2 - port map(A => \inst_2[20]\, B => N_201, Y => N_204); - - \r.m.ctrl.inst[28]\ : DFN1E0 - port map(D => \inst_2[28]\, CLK => lclk_c, E => holdn, Q - => \inst_3[28]\); - - \r.e.op1_RNITE9G[27]\ : OR2B - port map(A => \op1[27]\, B => un14_casaen_s1_0_0, Y => - \op1_m_0[27]\); - - \r.e.op1[9]\ : DFN1E0 - port map(D => \aop1[9]\, CLK => lclk_c, E => holdn, Q => - \op1[9]\); - - \r.a.rfa1[3]\ : DFN1E0 - port map(D => \un3_de_ren1[94]\, CLK => lclk_c, E => holdn, - Q => \rfa1[3]\); - - \r.w.s.y[26]\ : DFN1E0 - port map(D => N_3790, CLK => lclk_c, E => N_6922_i, Q => - \y[26]\); - - \r.d.cnt_RNO_0[0]\ : OR3 - port map(A => ldlock, B => annul_1, C => hold_pc_0_sqmuxa_1, - Y => cnt_2_sqmuxa_0); - - \r.x.data_0_RNO[8]\ : OR3B - port map(A => \data_0_1_0_iv_1[8]\, B => \dco_m_0_i[104]\, - C => \data_0_1_1[12]\, Y => \data_0_1[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I266_Y_0_a3 : NAND2 - port map(A => N782, B => N_15_i, Y => N_74_i); - - \r.x.dci.SIGNED_RNI2CVK71\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_14, B => mcdo_m_0_21, C => - me_signed_1, Y => \rdata_9_m_0[8]\); - - un6_fe_npc_I_179 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[20]\, Y => \DWACT_FINC_E[21]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I82_Y : AND2 - port map(A => N413_0, B => N416_0, Y => N541_0); - - \r.d.inst_0[11]\ : DFN1 - port map(D => \inst_0_RNO[11]\, CLK => lclk_c, Q => - \inst_0[11]\); - - \r.e.jmpl_RNIN50TT_0\ : OR2B - port map(A => \shiftin_17[26]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[26]\); - - \r.d.pc[16]\ : DFN1 - port map(D => \pc_RNO[16]\, CLK => lclk_c, Q => \dpc[16]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I14_P0N : OR2 - port map(A => \un1_iu0_6[13]\, B => \op2[13]\, Y => N437_0); - - \r.e.aluadd\ : DFN1E0 - port map(D => un1_aop2_1_sqmuxa, CLK => lclk_c, E => holdn, - Q => aluadd); - - \r.e.shleft_0_RNI6FFJ3\ : MX2 - port map(A => \shiftin_5[57]\, B => \shiftin_5[41]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[41]\); - - \r.e.ctrl.inst_RNISSQF[25]\ : XAI1 - port map(A => \inst_2[25]\, B => \inst_1[27]\, C => - \icc_0[2]\, Y => N_6695_i); - - \r.d.inst_0[3]\ : DFN1 - port map(D => \inst_0_RNO[3]\, CLK => lclk_c, Q => - \inst_0[3]\); - - \r.x.ctrl.wy_RNIRE1D_0\ : OR2A - port map(A => wy_2, B => wy_1, Y => wy_1_0_1); - - \r.a.ctrl.inst[11]\ : DFN1E0 - port map(D => \inst_0[11]\, CLK => lclk_c, E => holdn, Q - => \inst[11]\); - - \r.x.data_0_RNO_4[2]\ : AO1B - port map(A => rdatav_0_1_0_iv_0_2(10), B => N_3305_0, C => - rdata_2_sqmuxa, Y => \dco_m_i[106]\); - - \r.m.result_RNO[20]\ : MX2 - port map(A => \aluresult[20]\, B => \op1[20]\, S => - un17_casaen_0, Y => \eres2[20]\); - - \r.a.rfa2_RNIAR5M2[4]\ : MX2 - port map(A => \un3_de_ren1[103]\, B => \rfa2[4]\, S => - holdn, Y => raddr2(4)); - - \r.m.ctrl.trap_RNI3CIA11\ : NOR2B - port map(A => un1_trap_0_sqmuxa_5, B => un6_annul, Y => - tt_0_sqmuxa); - - \r.e.op1_RNITUR144[15]\ : NOR3C - port map(A => \op1_m_0[15]\, B => \d_iv_2[15]\, C => - \aluresult_m_0[15]\, Y => \d_i[15]\); - - \r.f.pc_RNIUONPJ1[2]\ : OA1A - port map(A => \fpc[2]\, B => rst, C => - \un6_ex_add_res_m[3]\, Y => \npc_iv_1[2]\); - - \r.e.op2_RNIA5IG[5]\ : MX2 - port map(A => \op2[5]\, B => N_4252, S => ldbp2_2, Y => - \un1_iu0_5[71]\); - - \r.e.op2_RNO_4[5]\ : OA1A - port map(A => \maddress[5]\, B => d27, C => \cpi_m_i[357]\, - Y => \d_1_iv_1[5]\); - - \r.x.data_0_RNO_0[8]\ : NOR3A - port map(A => \data_0_1_0_iv_0[8]\, B => \rdata_13_m[8]\, C - => \rdata_17_m[8]\, Y => \data_0_1_0_iv_1[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I304_Y_0 : XOR3 - port map(A => \data_0[13]\, B => \un1_iu0_6[13]\, C => - N802_1, Y => \un6_ex_add_res_s2[14]\); - - \r.w.result_RNICDB4[5]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[5]\, Y - => N_403); - - \r.e.op2[14]\ : DFN1E0 - port map(D => N_298, CLK => lclk_c, E => holdn, Q => - \op2[14]\); - - \r.e.ctrl.cnt_RNI458O[0]\ : NOR2A - port map(A => read_1_sqmuxa_0, B => N_3356_3, Y => - read_1_sqmuxa_i); - - \r.x.ctrl.rd[0]\ : DFN1E0 - port map(D => \rd_1[0]\, CLK => lclk_c, E => holdn, Q => - \rd_0[0]\); - - \r.d.inst_0_RNO_0[11]\ : MX2 - port map(A => data_0_11, B => \inst_0[11]\, S => - mexc_1_sqmuxa_1_0, Y => N_4611); - - \r.m.ctrl.trap_RNIJQBC\ : NOR2B - port map(A => trap_2, B => pv_1, Y => nullify_0_sqmuxa_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y_0 : AO18 - port map(A => N481, B => \data_0_0[29]\, C => - \un1_iu0_6[29]\, Y => ADD_33x33_fast_I260_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I108_Y : NOR3C - port map(A => N461, B => N464_2, C => N505_1, Y => N571_2); - - \r.a.rsel1_RNI5LB_1[0]\ : NOR2A - port map(A => \rsel1[1]\, B => \rsel1[0]\, Y => N_484_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I262_Y_0_0 : OA1C - port map(A => N502_1, B => N_50_1, C => N498, Y => - ADD_33x33_fast_I262_Y_0_0_1); - - \r.m.y_RNO_0[6]\ : AOI1B - port map(A => wy_RNIMKUI, B => \y[6]\, C => \y_m_0[6]\, Y - => \y_iv_1[6]\); - - \r.f.pc_RNO_4[25]\ : MX2 - port map(A => I_156, B => N_4068, S => bpmiss_1_i_0, Y => - \pc_4[25]\); - - \r.e.op2_RNO_4[22]\ : OA1A - port map(A => \maddress[22]\, B => d27_0, C => - \cpi_m_i[374]\, Y => \d_1_iv_1[22]\); - - \r.e.op1_RNIBDM62[11]\ : AO1A - port map(A => \op1[11]\, B => \un17_casaen_0_0\, C => - \ex_op1_i_m[11]\, Y => \edata2_0_iv_0[11]\); - - \r.a.ctrl.inst_RNIU43A1[19]\ : NOR2 - port map(A => illegal_inst35_4, B => N_207, Y => - illegal_inst35); - - un6_ex_add_res_d2_ADD_33x33_fast_I273_Y_0 : AOI1 - port map(A => ADD_33x33_fast_I273_un1_Y_0_1, B => N653_1, C - => N652, Y => ADD_33x33_fast_I273_Y_0_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I36_Y : OA1 - port map(A => \op2[29]\, B => \un1_iu0_6[29]\, C => N482_0, - Y => N495); - - \r.w.result[9]\ : DFN1E0 - port map(D => \wdata[9]\, CLK => lclk_c, E => holdn, Q => - \result[9]\); - - un6_fe_npc_I_105 : XOR2 - port map(A => N_78, B => \fe_pc[19]\, Y => I_105); - - \r.m.icc_RNIB3R93[3]\ : NOR2B - port map(A => \aluresult_1_iv_0[23]\, B => \icc_m[3]\, Y - => \aluresult_1_iv_2[23]\); - - \r.f.pc_RNO_5[17]\ : OR3C - port map(A => \xc_exception_1_0\, B => rst, C => - \xc_trap_address[17]\, Y => \xc_trap_address_m[17]\); - - \r.e.aluop_1_RNIEVV83[1]\ : MX2C - port map(A => \logicout_4[12]\, B => N_6919, S => N_6866_i, - Y => N_3635); - - un6_ex_add_res_d2_ADD_33x33_fast_I221_un1_Y : OR2B - port map(A => N650_1, B => N635, Y => I221_un1_Y); - - un6_ex_add_res_d1_ADD_33x33_fast_I318_Y_0_0 : XOR2 - port map(A => \op2[27]\, B => \un1_iu0_6[27]\, Y => - ADD_33x33_fast_I318_Y_0_0); - - \r.w.result_RNIJBTP3[3]\ : NOR3C - port map(A => \d_1_iv_1[3]\, B => \d_1_iv_0[3]\, C => - \rfo_m_i[35]\, Y => \d_1_iv_3[3]\); - - \r.a.ctrl.inst_RNIQ2954[31]\ : AO1D - port map(A => un1_illegal_inst11_0, B => illegal_inst12, C - => N_201, Y => privileged_inst_1_sqmuxa); - - \r.w.s.y[8]\ : DFN1E0 - port map(D => N_3772, CLK => lclk_c, E => N_6922_i, Q => - \y_0[8]\); - - \r.m.y_RNIHQSPB[25]\ : NOR2B - port map(A => \aluresult_1_iv_2[25]\, B => \bpdata_m_0[9]\, - Y => \aluresult_1_iv_4[25]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I260_Y_1 : NOR2B - port map(A => ADD_33x33_fast_I260_Y_0, B => - ADD_33x33_fast_I97_un1_Y, Y => ADD_33x33_fast_I260_Y_1); - - \r.e.alusel_RNO_2[1]\ : AO1A - port map(A => N_212, B => \alusel_i_0_a5_0_0[1]\, C => - N_339, Y => \alusel_i_0_0[1]\); - - \r.a.ctrl.inst_RNIEQKH8[30]\ : OR3B - port map(A => aluop_0_1_0_1, B => aluop_0_1_0_2, C => N_230, - Y => \aluop[0]\); - - \dci.enaddr_1_sqmuxa_1_RNO_0\ : NOR2 - port map(A => annul, B => N_3356_3, Y => - enaddr_1_sqmuxa_1_0); - - \r.w.result[24]\ : DFN1E0 - port map(D => \wdata[24]\, CLK => lclk_c, E => holdn, Q => - \result[24]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I315_Y_0_1 : XOR2 - port map(A => \data_0[24]\, B => \un1_iu0_6[24]\, Y => - \un6_ex_add_res_s2_1[25]\); - - \r.e.ldbp2_1_RNIF4GJL3\ : OR2A - port map(A => \eaddress[23]\, B => aluresult_0_sqmuxa, Y - => \un6_ex_add_res_m[24]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I66_Y\ : MAJ3 - port map(A => \dpc[12]\, B => \inst_0[10]\, C => N385, Y - => N483); - - \r.x.data_0_RNO_2[2]\ : AO1B - port map(A => rdatav_0_1_0_iv_7(2), B => mcdo_m_0_0, C => - N_3456, Y => \dco_m_i[98]\); - - \r.e.op2_RNO_6[18]\ : OR2B - port map(A => data2(18), B => d25, Y => \rfo_m_i[50]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I259_Y_0 : AOI1B - port map(A => \un1_iu0_6[30]\, B => \op2[30]\, C => - I33_un1_Y_0, Y => ADD_33x33_fast_I259_Y_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I10_G0N : NOR3A - port map(A => \op1[9]\, B => ldbp1, C => \data_0[9]\, Y => - N424_0); - - \r.w.s.wim_RNICB4N2[3]\ : MX2 - port map(A => \wim[3]\, B => \result_0[3]\, S => - wim_1_sqmuxa, Y => \wim_1[3]\); - - \r.m.result[22]\ : DFN1E0 - port map(D => \eres2[22]\, CLK => lclk_c, E => holdn, Q => - \maddress[22]\); - - \r.x.result_RNI2GLA[9]\ : MX2 - port map(A => \result_0[9]\, B => \data_0[9]\, S => ld_0, Y - => \un1_p0_6[361]\); - - \r.w.s.tt_RNO[1]\ : MX2A - port map(A => \xc_vectt_1[1]\, B => \irl[1]\, S => N_6747, - Y => \tt_RNO[1]\); - - \r.d.inst_0_RNI2423[24]\ : NOR2A - port map(A => \inst_0_0[24]\, B => \inst_0[20]\, Y => - N_3515_1); - - \r.m.ctrl.wicc_RNION9L\ : MX2A - port map(A => N_4181, B => \icc[1]\, S => wicc_3, Y => - N_4186); - - \r.e.op1_RNIVD884[1]\ : AOI1B - port map(A => \op1[1]\, B => un14_casaen_s1_0_1, C => - \d_1_iv_3[1]\, Y => \d_1_iv_4[1]\); - - \r.e.invop2_RNIK8QGR\ : MX2 - port map(A => \un6_ex_add_res_s2[14]\, B => - \un6_ex_add_res_s0[14]\, S => invop2, Y => N_6633); - - \r.f.pc_RNO_6[19]\ : MX2 - port map(A => \fpc[19]\, B => \eaddress[19]\, S => jump, Y - => N_4062); - - \r.x.result_RNIJLFP8[0]\ : NOR2A - port map(A => rst, B => N_3870, Y => \cwp_1_0[0]\); - - \r.w.result[27]\ : DFN1E0 - port map(D => \wdata[27]\, CLK => lclk_c, E => holdn, Q => - \result[27]\); - - \r.x.data_0_RNO[11]\ : OR3 - port map(A => \dco_m_0[107]\, B => \data_0_1_0_iv_0[11]\, C - => \data_0_1_4[9]\, Y => \data_0_1[11]\); - - \r.w.result_RNI90P1[15]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result[15]\, Y - => \result_m_0_0[15]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I3_P0N : AO1A - port map(A => ldbp1_2, B => \op1[2]\, C => \data_0[2]\, Y - => N404_1); - - \r.m.y_RNO_1[20]\ : AOI1B - port map(A => \y_0[20]\, B => y08_0, C => \y_m_2[21]\, Y - => \y_iv_0[20]\); - - \r.e.op2_RNO_8[26]\ : OR3B - port map(A => d29_0, B => \imm[26]\, C => \rsel2[0]\, Y => - \imm_m_i[26]\); - - \r.a.imm[31]\ : DFN1E0 - port map(D => \un3_de_ren1[149]\, CLK => lclk_c, E => holdn, - Q => \imm[31]\); - - \r.x.dci.size_RNIB0QVR[0]\ : NOR3B - port map(A => \me_size_1[0]\, B => ld_3, C => - \me_size_1[1]\, Y => rdata_3_sqmuxa_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I268_Y : AO1B - port map(A => ADD_33x33_fast_I268_un1_Y_0_1, B => N674_0, C - => ADD_33x33_fast_I268_Y_0_0, Y => N782_0); - - \r.e.aluop_0_RNI2NHB1[0]\ : NOR3C - port map(A => \aluop_0[0]\, B => \un1_iu0_6[24]\, C => - \logicout_5_0_i_0_tz[24]\, Y => \logicout_5_0_i_0[24]\); - - \r.e.op1[12]\ : DFN1E0 - port map(D => \aop1[12]\, CLK => lclk_c, E => holdn, Q => - \op1[12]\); - - \r.m.y_RNIFT8V2[30]\ : AOI1B - port map(A => \y[30]\, B => aluresult_10_sqmuxa_0, C => - \ex_op2_m[30]\, Y => \aluresult_1_iv_0[30]\); - - \r.e.shleft_1_RNI5D9G1\ : MX2A - port map(A => \shiftin_5[24]\, B => shleft_1_RNIDVBG, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[8]\); - - \r.m.icc_RNIC6A3[3]\ : XNOR2 - port map(A => \inst_0[28]\, B => \icc[3]\, Y => branch_7_i); - - \r.d.inst_0_RNIES9C[23]\ : OR2B - port map(A => ldcheck1_5_i_a6_1_1, B => N_3736_2, Y => - N_3736); - - un6_ex_add_res_d2_ADD_33x33_fast_I29_G0N : NOR2B - port map(A => \un1_iu0_6[28]\, B => \data_0[28]\, Y => - N481_1); - - \r.e.op1_RNI2PCQB[17]\ : NOR3 - port map(A => \edata2_0_iv_0[17]\, B => \ex_op1_i_m[17]\, C - => \bpdata_i_m_1[1]\, Y => edata2_0_iv(17)); - - \r.d.inst_0_RNIAK79[24]\ : OR3B - port map(A => \inst_0_0[24]\, B => \un1_p0_6_0[60]\, C => - \inst_0_0[22]\, Y => un5_op3); - - un6_ex_add_res_d0_ADD_33x33_fast_I262_Y_0_0 : OA1A - port map(A => N502_0, B => N_50_0, C => N498_i, Y => - ADD_33x33_fast_I262_Y_0_0_0); - - \r.e.aluop_RNIVT234[1]\ : OR2B - port map(A => \bpdata[6]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[6]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I303_Y_0_0 : XOR2 - port map(A => \op2[12]\, B => \un1_iu0_6[12]\, Y => - ADD_33x33_fast_I303_Y_0_0); - - \r.m.result_RNISVO1[12]\ : OR2B - port map(A => d13, B => \maddress[12]\, Y => - \result_m_0[12]\); - - \r.e.ctrl.trap_RNO\ : MX2A - port map(A => trap_4, B => trap_1, S => annul_2, Y => - trap_3); - - \r.e.ctrl.inst_RNI1FB51[25]\ : MX2 - port map(A => N_475, B => N_482, S => \inst_RNIJ0JA[25]\, Y - => N_261); - - \r.m.y_RNO_2[13]\ : OR2A - port map(A => \logicout[13]\, B => y14, Y => - \logicout_m[13]\); - - \r.e.aluop_RNI6KJJ1[2]\ : XA1 - port map(A => \un1_iu0_5[84]\, B => \aluop_1[2]\, C => - \un1_iu0_6[18]\, Y => N_3545); - - \r.e.op1_RNO[29]\ : MX2C - port map(A => \d_i[29]\, B => \d_i[30]\, S => N_227, Y => - \aop1[29]\); - - \r.e.ctrl.inst_RNI04ER[26]\ : NOR3B - port map(A => \inst_1[26]\, B => N_482, C => \inst_1[27]\, - Y => ex_bpmiss_1_0_a5_1_1); - - \r.e.op1_RNIB75RB[18]\ : NOR3 - port map(A => \edata2_0_iv_0[18]\, B => \ex_op1_i_m[18]\, C - => \bpdata_i_m_1[2]\, Y => edata2_0_iv(18)); - - \r.x.ctrl.tt_RNO[0]\ : MX2C - port map(A => N_4200_i_0, B => N_4204, S => N_4210_i_0, Y - => \tt2[0]\); - - \r.x.ctrl.inst_RNIFU0L_0[23]\ : NOR3B - port map(A => \inst[23]\, B => \inst[20]\, C => - \inst_0[21]\, Y => tba_610_e_2); - - \r.w.result[12]\ : DFN1E0 - port map(D => \wdata[12]\, CLK => lclk_c, E => holdn, Q => - \result_0[12]\); - - \r.e.op2_RNIRFMB1_0[13]\ : OR2 - port map(A => \un1_iu0_6[13]\, B => \un1_iu0_5[79]\, Y => - \logicout_3[13]\); - - \r.x.result_RNIFDBB[2]\ : MX2 - port map(A => \result_0[2]\, B => \data_0[2]\, S => ld_4, Y - => \un1_p0_6[354]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I178_Y\ : AO1A - port map(A => N545, B => N552_2, C => N544, Y => N604); - - \r.m.y_RNIHMJO6[3]\ : NOR3C - port map(A => \cpi_m[148]\, B => \y_m_1[3]\, C => - \aluresult_1_iv_1[3]\, Y => \aluresult_1_iv_3[3]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I206_Y_0_o3_1 : OR2B - port map(A => ADD_33x33_fast_I206_Y_0_o3_1_0_0, B => - N_57_i_0, Y => N616_0); - - \r.f.pc_RNO_2[16]\ : OR2B - port map(A => I_84, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[14]\); - - \r.e.op1_RNIC9HR3[21]\ : NOR3C - port map(A => \rfo_m[21]\, B => \d_iv_1[21]\, C => - \op1_m_0[21]\, Y => \d_iv_3[21]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I262_Y_0_a3_0_0 : NOR2A - port map(A => N503_1, B => N_50_1, Y => - ADD_33x33_fast_I262_Y_0_a3_0_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I272_un1_Y : NOR3C - port map(A => N667, B => N616, C => N651_0, Y => I272_un1_Y); - - \r.x.ctrl.pc_RNI56A71[25]\ : MX2C - port map(A => \un1_p0_6[377]\, B => \pc_2[25]\, S => - s_3_sqmuxa, Y => N_3416); - - \r.e.ctrl.tt_RNO[3]\ : NOR3C - port map(A => \tt_9_1[0]\, B => \tt_3[3]\, C => - illegal_inst_7_i_0, Y => \tt_0[3]\); - - \r.d.annul_RNIIHK0F\ : OR3B - port map(A => bpmiss_1_i_0_0, B => branch_0, C => - un2_rstn_5_0_i, Y => \un2_rstn_5_0_0\); - - \r.a.imm_RNO[12]\ : MX2 - port map(A => \inst_0_RNI2NUM[2]\, B => \un1_p0_6_0[51]\, S - => call_hold5_0, Y => \un3_de_ren1[130]\); - - \r.e.shcnt_RNIFCE9D[2]\ : MX2C - port map(A => \shiftin_11[28]\, B => \shiftin_11[24]\, S - => \ex_shcnt_1_i[2]\, Y => \shiftin_14[24]\); - - \r.a.imm_RNI4645[3]\ : OR3B - port map(A => d29_0_0, B => \imm[3]\, C => \rsel2_0[0]\, Y - => \imm_m_i[3]\); - - \r.w.s.wim_RNI95RD2[3]\ : OR2B - port map(A => \wim[3]\, B => aluresult_13_sqmuxa, Y => - \wim_m[3]\); - - \r.d.pv_RNI2POTF\ : OR2B - port map(A => un23_exbpmiss_i_0, B => un5_exbpmiss_i_0, Y - => un1_exbpmiss); - - \r.w.s.tt[7]\ : DFN1E0 - port map(D => xc_vectt14, CLK => lclk_c, E => N_6747, Q => - \tt[7]\); - - \r.e.shleft_RNIHURJ_0\ : OR2A - port map(A => \un1_iu0_6[27]\, B => shleft, Y => - \shiftin_5[27]\); - - \r.e.op2_RNO_0[19]\ : OR3C - port map(A => \op1_m_i[19]\, B => \d_1_iv_3[19]\, C => - \aluresult_m_i[19]\, Y => \d_1[19]\); - - \r.a.rfa1[0]\ : DFN1E0 - port map(D => \rs1_iv_i_0[0]\, CLK => lclk_c, E => holdn, Q - => \rfa1[0]\); - - \r.x.rstate_RNI5S7L[0]\ : NOR2 - port map(A => \rstate[0]\, B => N_6352, Y => N_6357); - - \r.m.icc_RNITIJF3[2]\ : NOR2B - port map(A => \aluresult_1_iv_0[22]\, B => \icc_m[2]\, Y - => \aluresult_1_iv_2[22]\); - - \r.a.ctrl.inst_RNI3T3A1[22]\ : OA1C - port map(A => N_203, B => N_472, C => N_256_i_0, Y => - illegal_inst_7_iv_8_tz); - - un6_ex_add_res_d2_ADD_33x33_fast_I188_Y : NOR2B - port map(A => N599_2, B => N591_1, Y => N657); - - \r.e.op2_RNO_4[14]\ : OA1A - port map(A => \maddress[14]\, B => d27_0, C => - \cpi_m_i[366]\, Y => \d_1_iv_1[14]\); - - \r.f.pc_RNO_8[24]\ : MX2 - port map(A => \fpc[24]\, B => \eaddress[24]\, S => jump, Y - => N_4067); - - \r.f.pc_RNO_7[21]\ : MX2 - port map(A => \fpc[21]\, B => \tba[9]\, S => - rstate_6314_d_0, Y => \xc_trap_address[21]\); - - \r.m.y_RNO_0[5]\ : NOR3C - port map(A => \y_m[6]\, B => \y_m_0[5]\, C => \y_iv_1[5]\, - Y => \y_iv_2[5]\); - - \r.f.pc_RNIERSAK7[4]\ : OR3C - port map(A => \npc_iv_1[4]\, B => \npc_iv_0[4]\, C => - \npc_iv_2[4]\, Y => rpc_2); - - \r.e.jmpl_RNIUMD1Q1\ : NOR2B - port map(A => \shiftin_17_m_0[3]\, B => - \aluresult_1_iv_6[3]\, Y => \aluresult_1_iv_7[3]\); - - \r.f.pc_RNO_0[7]\ : OA1A - port map(A => un2_rstn_3_0, B => \eaddress[7]\, C => - \pc_1_iv_0[7]\, Y => \pc_1_iv_1[7]\); - - \r.m.ctrl.pc[2]\ : DFN1E0 - port map(D => \pc_2[2]\, CLK => lclk_c, E => holdn, Q => - \pc_3[2]\); - - \r.e.aluadd_RNIMNSQ75\ : XA1B - port map(A => \icc_3_i_0[0]\, B => aluadd, C => aluresult12, - Y => \icc_16[0]\); - - \r.m.y_RNO[4]\ : AO1C - port map(A => y14_0, B => \logicout[4]\, C => \y_iv_2[4]\, - Y => \y_0[4]\); - - \r.x.result[30]\ : DFN1E0 - port map(D => \maddress[30]\, CLK => lclk_c, E => holdn, Q - => \result_0[30]\); - - \r.w.s.y_RNO[1]\ : NOR3 - port map(A => N_399, B => N_398, C => N_400, Y => N_163); - - \r.e.op2[13]\ : DFN1E0 - port map(D => N_297, CLK => lclk_c, E => holdn, Q => - \op2[13]\); - - \r.e.ctrl.inst_RNIFK0E[21]\ : OR2B - port map(A => \inst_1[22]\, B => \inst_1[21]\, Y => - N_3749_3); - - un6_ex_add_res_d2_ADD_33x33_fast_I168_Y : NOR2B - port map(A => N579_1, B => N571, Y => N637_0); - - \r.x.rstate_0_RNIPSIE2[0]\ : MX2C - port map(A => N_3413, B => \xc_result[22]\, S => - \rstate_0[0]\, Y => \wdata[22]\); - - \r.f.pc_RNO_0[15]\ : NAND2 - port map(A => \tmp[15]\, B => un2_rstn_5_0, Y => - \tmp_m[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I26_P0N : OR3A - port map(A => \data_0[25]\, B => \op1[25]\, C => ldbp1_3, Y - => N473_1); - - \r.e.op1_RNIMV5RB[19]\ : NOR3 - port map(A => \edata2_0_iv_0[19]\, B => \ex_op1_i_m[19]\, C - => \bpdata_i_m_1[3]\, Y => edata2_0_iv(19)); - - \r.d.annul_RNIRCLP85\ : OR2B - port map(A => I_45, B => un2_rstn_4_0_0, Y => - \un6_fe_npc_m[8]\); - - \r.e.shcnt_RNO[4]\ : XOR2 - port map(A => \d_1[4]\, B => N_208, Y => N_270_i_i_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I30_P0N : NOR2 - port map(A => \un1_iu0_6[29]\, B => \data_0_0[29]\, Y => - N485_i_0); - - \r.m.result_RNIDJD4[25]\ : OR2B - port map(A => d13_0, B => \maddress[25]\, Y => - \result_m_0[25]\); - - \r.e.op2_RNO[2]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[2]\, Y => N_286); - - un6_fe_npc_I_129 : XOR2 - port map(A => N_61, B => \fe_pc[22]\, Y => I_129); - - \r.x.data_0_RNO_1[8]\ : OR2B - port map(A => N_3473, B => data_0_0_8, Y => - \dco_m_0_i[104]\); - - \r.x.ctrl.inst_RNIEJ1S[24]\ : NOR2B - port map(A => y15, B => y6_0, Y => y_0_sqmuxa_1_2); - - \r.e.op2_RNO_7[27]\ : OR3C - port map(A => d28_0, B => \rsel2[0]\, C => \un1_p0_6[379]\, - Y => \cpi_m_i[379]\); - - \r.x.ctrl.tt[3]\ : DFN1E0 - port map(D => \tt2[3]\, CLK => lclk_c, E => holdn, Q => - \tt[3]\); - - \r.x.rstate_RNIJKCQ[1]\ : OR2A - port map(A => rstate_6314_d_0, B => s_3_sqmuxa_0, Y => - \xc_exception_1_0\); - - \r.x.data_0_RNO_0[28]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_28, Y => - \dco_m_1[124]\); - - \r.e.ctrl.inst_RNIO41L[21]\ : OR3 - port map(A => \inst_1[22]\, B => \inst_0[23]\, C => - \inst_1[21]\, Y => \icc_8_m_5[1]\); - - \r.d.inst_0_RNIV66G[25]\ : OR2B - port map(A => N_3361, B => N_85, Y => \rd_3[0]\); - - \r.m.su\ : DFN1E0 - port map(D => esu, CLK => lclk_c, E => holdn, Q => msu); - - \r.a.rsel1_0_RNIG3LJ2[2]\ : OR2B - port map(A => data1(19), B => d11_0, Y => \rfo_m[19]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I267_Y : NAND2 - port map(A => I267_un1_Y, B => ADD_33x33_fast_I267_Y_0, Y - => N780_1); - - \r.d.inst_0_RNIP2VJ[31]\ : NOR2 - port map(A => un1_inst, B => un6_op, Y => un8_op); - - \comb.branch_address.tmp_ADD_30x30_fast_I40_Y_0_a3\ : AND2 - port map(A => N424, B => N428, Y => - ADD_30x30_fast_I40_Y_0_a3); - - \comb.branch_address.tmp_ADD_30x30_fast_I10_G0N\ : NOR2B - port map(A => \inst_0[10]\, B => \dpc[12]\, Y => N388); - - \r.m.y_RNICM5I3[10]\ : NOR3C - port map(A => \cpi_m[155]\, B => \y_m_1[10]\, C => - \tt_m[6]\, Y => \aluresult_1_iv_3[10]\); - - \r.e.op2_RNO_7[6]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[358]\, Y => \cpi_m_i[358]\); - - \r.d.inst_0_RNI419C[28]\ : OR3 - port map(A => N_17, B => N_122_2, C => N_79, Y => un19_rd_1); - - \r.a.rsel2_RNI7V53[1]\ : NOR3B - port map(A => \rsel2[2]\, B => \rsel2[1]\, C => - \rsel2_0[0]\, Y => d31); - - \r.e.ldbp2_RNIAFT52\ : MX2C - port map(A => \un6_ex_add_res_s1_i[2]\, B => N_6641, S => - ldbp2_3, Y => \eaddress[1]\); - - \r.e.aluop_0_RNIBQCM1[0]\ : MX2C - port map(A => N_3568, B => N_3632, S => \aluop_0[0]\, Y => - \logicout[9]\); - - \r.x.data_0_RNO_3[6]\ : OR2B - port map(A => rdata_2_sqmuxa, B => data_0_2_14, Y => - \dco_m_i[110]\); - - \r.x.data_0_RNO_3[13]\ : NOR2A - port map(A => \data_0[13]\, B => ld_3, Y => \data_0_m[13]\); - - \r.m.result_RNITVO1[13]\ : OR2B - port map(A => d13, B => \maddress[13]\, Y => - \result_m_0[13]\); - - \r.d.inst_0_RNI9MOA[24]\ : NOR3A - port map(A => ldcheck1_5_i_a6_2_1, B => \inst_0[20]\, C => - \inst_0_0[24]\, Y => ldcheck1_5_i_a6_2_2); - - un6_ex_add_res_d1_ADD_33x33_fast_I264_Y_0 : OR2 - port map(A => I165_un1_Y, B => N568, Y => - ADD_33x33_fast_I264_Y_0); - - \r.e.shcnt[4]\ : DFN1E0 - port map(D => N_270_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[4]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I238_Y_0\ : AOI1 - port map(A => N526, B => N519, C => N518, Y => - ADD_30x30_fast_I238_Y_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I191_Y : AO1A - port map(A => N595_2, B => N602_0, C => N594_1, Y => N660_0); - - \r.e.alucin_RNO\ : NOR3B - port map(A => cin_iv_i_2, B => N_348, C => N_236, Y => - N_6684_i_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I198_Y : NOR2B - port map(A => N609_0, B => N601, Y => N667_0); - - \r.e.op1_RNI070N1[28]\ : OR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[28]\, Y => - \ex_op1_i_m[28]\); - - \r.a.ctrl.inst_RNIOVAT5[31]\ : OR3C - port map(A => cp_disabled_6_sqmuxa, B => - cp_disabled_1_sqmuxa, C => fp_disabled_4_0_1_1, Y => - fp_disabled_4); - - \r.m.y[1]\ : DFN1E0 - port map(D => \y_1[1]\, CLK => lclk_c, E => holdn, Q => - \y[1]\); - - \r.f.pc[29]\ : DFN1E0 - port map(D => \pc_1[29]\, CLK => lclk_c, E => holdn, Q => - \fpc[29]\); - - \r.e.ctrl.wreg_RNIIPDC\ : AO1C - port map(A => call_hold7_i, B => ldchkex_0, C => wreg_7, Y - => wreg_2); - - \r.x.ctrl.pc_RNID2HF[23]\ : MX2 - port map(A => \pc[23]\, B => \pc_0[23]\, S => \npc_1[1]\, Y - => N_3234); - - \r.d.pv_RNI21DP7_0\ : NOR3 - port map(A => ex_bpmiss_1_0, B => annul_2, C => pv, Y => - un13_exbpmiss_0); - - \r.e.op1_RNI4JN8[0]\ : MX2 - port map(A => \op1[0]\, B => \data_0[0]\, S => ldbp1_1, Y - => \un1_iu0_6[0]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I243_un1_Y : NOR2B - port map(A => N672_0, B => N657_0, Y => I243_un1_Y_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I179_Y\ : NOR3B - port map(A => N494, B => N498_0, C => N545, Y => N605); - - un6_ex_add_res_d0_ADD_33x33_fast_I121_Y_0 : AO13 - port map(A => N445_0, B => \un1_iu0_6[17]\, C => - \data_0[17]\, Y => ADD_33x33_fast_I121_Y_0_0); - - \r.e.op2_RNO_2[12]\ : AOI1B - port map(A => data2(12), B => d25_0, C => \d_1_iv_2[12]\, Y - => \d_1_iv_3[12]\); - - \r.e.op2_RNIR2OP[30]\ : MX2 - port map(A => \op2[30]\, B => N_4277, S => ldbp2_0, Y => - \un1_iu0_5[96]\); - - \r.e.ctrl.annul_RNIQ60BE\ : NOR3B - port map(A => ex_bpmiss_1_0, B => branch_1_m7_1, C => - \xc_exception_1_0\, Y => branch_1_m7_3); - - un6_ex_add_res_d0_ADD_33x33_fast_I78_Y : NOR2B - port map(A => N422_0, B => N419, Y => N537_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I36_un1_Y\ : OR3B - port map(A => \dpc[26]\, B => N434_1, C => \inst_0_1[26]\, - Y => I36_un1_Y_i); - - un6_ex_add_res_d1_ADD_33x33_fast_I47_Y_0_o3 : OR2 - port map(A => N466, B => N_72, Y => N506_1); - - \r.e.op2_RNO_0[16]\ : OR3C - port map(A => \op1_m_i[16]\, B => \d_1_iv_3[16]\, C => - \aluresult_m_i[16]\, Y => \d_1[16]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I272_Y : OR3 - port map(A => N650_0, B => I272_un1_Y, C => I237_un1_Y, Y - => N790); - - \r.a.ctrl.rd_RNI1VUG3[0]\ : NOR3C - port map(A => un2_rs1_0_i, B => un2_rs1_6_i, C => - un2_rs1_NE_2, Y => un2_rs1_NE_5); - - \r.d.annul_RNI17OB\ : NOR2A - port map(A => un9_rabpmiss_0, B => annul_1, Y => - un9_rabpmiss_1); - - \r.x.result_RNIP91O3[10]\ : MX2 - port map(A => \un1_iu0_6[10]\, B => \un1_p0_6[362]\, S => - bpdata6, Y => \bpdata[10]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I50_Y : OA1 - port map(A => \op2[22]\, B => \un1_iu0_6[22]\, C => N461_0, - Y => N509); - - \r.x.ctrl.annul_RNIVHS32\ : OR2 - port map(A => cwp_1_sqmuxa, B => annul_1_0, Y => - pil_0_sqmuxa); - - \r.f.pc_RNO_7[18]\ : MX2 - port map(A => \fpc[18]\, B => \tba[6]\, S => - rstate_6314_d_0, Y => \xc_trap_address[18]\); - - \r.m.ctrl.rd_RNIQQ7Q[3]\ : XNOR2 - port map(A => \inst_0_RNI3RUM[3]\, B => \rd_0[3]\, Y => - un1_de_ren1_1_3_i_0); - - \r.d.inst_0_RNIV3M6[17]\ : OR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_0[0]\, B => - un26_rs1opt, Y => \de_raddr1_2[4]\); - - \r.e.shcnt_RNIA7HM5[3]\ : MX2 - port map(A => \shiftin_8[32]\, B => \shiftin_8[24]\, S => - \ex_shcnt_1_i[3]\, Y => \shiftin_11[24]\); - - \r.d.cnt_RNO[0]\ : NOR2 - port map(A => cnt_2_sqmuxa_0, B => annul_4, Y => - cnt_2_sqmuxa); - - \r.x.result_RNILK6E[21]\ : MX2 - port map(A => \result_0[21]\, B => \data_0[21]\, S => ld_4, - Y => \un1_p0_6[373]\); - - \r.e.ldbp2_2_RNIHUD5B3\ : MX2C - port map(A => \un6_ex_add_res_s1_i[22]\, B => N_6568, S => - ldbp2_2, Y => \eaddress[21]\); - - \r.a.ctrl.inst_RNIIO1S[21]\ : OR2A - port map(A => illegal_inst35_4_0, B => N_216, Y => - illegal_inst35_4); - - \r.w.result_RNIF7QL[22]\ : AOI1B - port map(A => \un1_p0_6[374]\, B => d14_0, C => - \result_m_0_0[22]\, Y => \d_iv_0[22]\); - - \r.d.pv_RNO\ : NOR3C - port map(A => pv_4_0, B => pv_2, C => pv_3, Y => pv_6); - - \r.e.shleft_1_RNIFL5S2\ : MX2B - port map(A => \shiftin_5[42]\, B => \shiftin_5[26]\, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[26]\); - - \r.e.op2_RNO_3[13]\ : NOR3C - port map(A => \cpi_m_i[365]\, B => \result_m_i[13]\, C => - \d_1_iv_0[13]\, Y => \d_1_iv_2[13]\); - - \r.x.result_RNIRLS65[8]\ : OR2B - port map(A => \bpdata[8]\, B => N_3974, Y => \bpdata_m[8]\); - - \r.e.jmpl_RNI6M02E2\ : OR3C - port map(A => \aluresult_1_iv_8[6]\, B => - \shiftin_17_m_0[6]\, C => ldbp2_2_RNI5355F, Y => - \aluresult[6]\); - - \r.f.pc_RNIN6L9KD[10]\ : OR3C - port map(A => \npc_iv_1[10]\, B => \npc_iv_0[10]\, C => - \npc_iv_2[10]\, Y => rpc_8); - - \r.w.s.tba[1]\ : DFN1E1 - port map(D => \result_0[13]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[1]\); - - \r.x.data_0_RNO_1[26]\ : NOR2A - port map(A => \data_0[26]\, B => ld_3, Y => \data_0_m[26]\); - - \r.x.ctrl.wicc_RNO\ : NOR2A - port map(A => wicc_3, B => \un1_p0_6[0]\, Y => wicc_1_2); - - \r.e.aluop_1_RNI9GHD1[1]\ : XOR3 - port map(A => \un1_iu0_6[10]\, B => \aluop_1[1]\, C => - \un1_iu0_5[76]\, Y => N_6844); - - \comb.fpstdata.edata2_0_iv[2]\ : NAND2 - port map(A => \bpdata_i_m[2]\, B => \edata2_0_iv_0[2]\, Y - => edata2_0_iv(2)); - - \r.x.result_RNIHLBB9[5]\ : AO1C - port map(A => N_3029, B => G_9_0, C => et_2_sqmuxa, Y => - et_1_0); - - \r.x.data_0_RNO[25]\ : OR3 - port map(A => \dco_m_1[121]\, B => \data_0_m[25]\, C => - \data_0_1_4[18]\, Y => \data_0_1[25]\); - - \r.e.shleft_1_RNIEJBQ1\ : MX2A - port map(A => \shiftin_5[21]\, B => shleft_1_RNI9JBG, S => - \ex_shcnt_1_i_0[4]\, Y => \shiftin_8[5]\); - - \r.e.aluop_RNIHFP34[1]\ : OR2B - port map(A => \bpdata[3]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[3]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I319_Y_0 : AX1E - port map(A => N_51_i, B => ADD_33x33_fast_I262_Y_0_0_1, C - => \un6_ex_add_res_s2_1[29]\, Y => - \un6_ex_add_res_s2[29]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I181_Y : OR3A - port map(A => I181_un1_Y_i, B => I121_un1_Y, C => - ADD_33x33_fast_I121_Y_0, Y => N650_1); - - \r.x.npc_0_RNILSQ61[0]\ : MX2C - port map(A => N_3221, B => N_3251, S => \npc_0[0]\, Y => - \xc_result[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I62_un1_Y\ : OAI1 - port map(A => \dpc[14]\, B => \inst_0[12]\, C => N391, Y - => I62_un1_Y_i); - - \r.m.icc_RNO_25[2]\ : NOR2 - port map(A => \logicout[13]\, B => \logicout[14]\, Y => - icc_0_sqmuxa_1_5); - - \r.w.s.tba_RNICNFP5[7]\ : AND2 - port map(A => \tba_m[7]\, B => \bpdata_m[19]\, Y => - \aluresult_1_iv_3[19]\); - - \un1_r.w.s.cwp_1_CO1_0\ : OR2B - port map(A => et_RNI1BRF2, B => CO1_0_tz, Y => CO1_0); - - \r.m.dci.size_RNO_0[1]\ : NOR3A - port map(A => ex_sari_1_1_0, B => \inst[24]\, C => N_3356_3, - Y => \size_1[1]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I244_un1_Y\ : NOR2B - port map(A => ADD_30x30_fast_I244_un1_Y_0, B => N607, Y => - I244_un1_Y_0); - - \r.d.inst_0_RNI4423_0[24]\ : NOR2A - port map(A => \inst_0_0[22]\, B => \inst_0_0[24]\, Y => - icc_check9_2); - - \r.a.ctrl.inst_RNI9S0E_0[21]\ : OR2A - port map(A => \inst_1[24]\, B => \inst_2[21]\, Y => - alusel24_2); - - \r.f.pc_RNO_3[30]\ : OR2B - port map(A => \de_hold_pc_1\, B => \pc_4[30]\, Y => - \pc_4_m[30]\); - - \r.m.y_RNO_3[20]\ : OR3A - port map(A => \y_2[20]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[20]\); - - \r.x.result_RNITQDE5[14]\ : NOR2B - port map(A => \bpdata[14]\, B => \aluop_RNIGM3N1[2]\, Y => - \bpdata_i_m[14]\); - - \r.e.aluop_RNIP5PM8[2]\ : AOI1 - port map(A => edata_1_sqmuxa, B => \bpdata[11]\, C => - \bpdata_i_m_2[3]\, Y => \edata2_iv_2[27]\); - - \r.m.ctrl.rd[2]\ : DFN1E0 - port map(D => \rd_1[2]\, CLK => lclk_c, E => holdn, Q => - \rd_0[2]\); - - \r.e.op2_RNO[9]\ : MX2C - port map(A => un1_aop2_1_sqmuxa_0, B => N_6697_i_0_0, S => - \d_1[9]\, Y => N_293); - - un6_ex_add_res_d0_ADD_33x33_fast_I37_Y : AO13 - port map(A => N478_1, B => \un1_iu0_6[28]\, C => - \data_0[28]\, Y => N496_0); - - \r.e.op2_RNIBGNB1_0[17]\ : OR2 - port map(A => \un1_iu0_6[17]\, B => \un1_iu0_5[83]\, Y => - \logicout_3[17]\); - - \r.e.op1_RNIE93M7[5]\ : OR2B - port map(A => \edata2_0_iv_0[5]\, B => \bpdata_i_m[5]\, Y - => edata2_0_iv(5)); - - \r.e.ldbp2_0_RNIP1CIF\ : MX2C - port map(A => \un6_ex_add_res_s1[8]\, B => N_6554, S => - ldbp2_0, Y => \eaddress[7]\); - - \r.e.jmpl_RNIGRK585\ : OR3C - port map(A => \aluresult_1_iv_7[18]\, B => - \shiftin_17_m_0[18]\, C => \un6_ex_add_res_m[19]\, Y => - \aluresult[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I279_Y_0_0\ : XOR2 - port map(A => \dpc[21]\, B => \inst_0[19]\, Y => - ADD_30x30_fast_I279_Y_0_0); - - \r.a.rsel1_0_RNI0P8M2[2]\ : OR2B - port map(A => data1(8), B => d11, Y => \rfo_m[8]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I145_Y_0 : MIN3 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N409_1, - Y => ADD_33x33_fast_I145_Y_0_1); - - \r.x.ctrl.pc_RNII7AE[8]\ : MX2 - port map(A => \pc_0[8]\, B => \pc_2[8]\, S => \npc_0[1]\, Y - => N_3219); - - \r.w.s.ps_RNIBCGT5\ : OR3C - port map(A => s_m, B => ps_m, C => \result_m[6]\, Y => ps_1); - - \r.d.inst_0_RNIR7G41[17]\ : MX2C - port map(A => \de_raddr1_2[6]\, B => \de_raddr1_1[6]\, S - => rs1mod, Y => \un3_de_ren1[97]\); - - \r.m.y_RNO_3[2]\ : OR3A - port map(A => \y_2[2]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[2]\); - - \r.a.rfa1[2]\ : DFN1E0 - port map(D => \un3_de_ren1[93]\, CLK => lclk_c, E => holdn, - Q => \rfa1[2]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I306_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[15]\, B => \data_0_2[15]\, Y => - \un6_ex_add_res_s2_1[16]\); - - \r.x.ctrl.pc_RNIB7AE[4]\ : MX2 - port map(A => \pc_2[4]\, B => \pc[4]\, S => \npc_1[1]\, Y - => N_3215); - - \r.d.pc[23]\ : DFN1 - port map(D => \pc_RNO[23]\, CLK => lclk_c, Q => \dpc[23]\); - - \r.x.ctrl.rd[1]\ : DFN1E0 - port map(D => \rd_0[1]\, CLK => lclk_c, E => holdn, Q => - \rd_1[1]\); - - \r.m.y_RNO_1[7]\ : OR2B - port map(A => \y[8]\, B => mulstep_0, Y => \y_m_0[8]\); - - \r.e.shcnt_RNINCAA9[2]\ : MX2C - port map(A => \shiftin_11[6]\, B => \shiftin_11[2]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[2]\); - - \r.a.rsel1_RNINCQ667[0]\ : OR2B - port map(A => un14_casaen_s0_0_0, B => \aluresult[26]\, Y - => \aluresult_m_0[26]\); - - \r.e.ctrl.cnt[1]\ : DFN1E0 - port map(D => \cnt_2[1]\, CLK => lclk_c, E => holdn, Q => - \cnt[1]\); - - \r.e.shcnt_RNI50TV8[2]\ : MX2C - port map(A => \shiftin_11[9]\, B => \shiftin_11[5]\, S => - \ex_shcnt_1_i_0[2]\, Y => \shiftin_14[5]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I308_Y_0_1 : XOR2 - port map(A => \un1_iu0_6[17]\, B => \data_0[17]\, Y => - \un6_ex_add_res_s2_1[18]\); - - \r.w.s.s_RNO_0\ : MX2 - port map(A => s_1_iv, B => s, S => holdn, Y => N_4943); - - \r.e.aluop_2_RNIDKAP[1]\ : MX2C - port map(A => N_3536, B => \logicout_3[9]\, S => - \aluop_2[1]\, Y => N_3568); - - \r.e.op1_RNO[16]\ : MX2C - port map(A => \d_i[16]\, B => \d_i[17]\, S => N_227_0, Y - => \aop1[16]\); - - \r.d.cwp_RNI1M5O[0]\ : MX2B - port map(A => \cwp_0[0]\, B => \cwp_0[0]\, S => un8_op, Y - => \ncwp[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I313_Y_0 : AX1D - port map(A => I229_un1_Y, B => ADD_33x33_fast_I268_Y_0, C - => \un6_ex_add_res_s2_1[23]\, Y => - \un6_ex_add_res_s2[23]\); - - \r.x.dci.SIGNED_RNIIMS3D1\ : AOI1B - port map(A => rdatav_0_1_0_iv_4_22, B => mcdo_m_0_29, C => - me_signed_1, Y => \rdata_5[8]\); - - \r.x.ctrl.tt_RNI72K6[2]\ : NOR2B - port map(A => \tt[2]\, B => \tt[3]\, Y => tt_1); - - \r.e.op1_RNITICR1[17]\ : NOR2A - port map(A => edata_3_sqmuxa, B => \un1_iu0_6[17]\, Y => - \ex_op1_i_m[17]\); - - \r.e.jmpl_RNIS1V9M_0\ : OR2B - port map(A => \shiftin_17[9]\, B => aluresult_2_sqmuxa_0, Y - => \shiftin_17_m_0[9]\); - - aluresult_11_sqmuxa_5 : NOR2 - port map(A => miscout140, B => aluresult_11_sqmuxa_5_0, Y - => aluresult_12_sqmuxa_5); - - \r.x.result_RNIQ6VN5[5]\ : OR2A - port map(A => N_3687, B => \bpdata[5]\, Y => - \bpdata_i_m[5]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I25_P0N : OR2 - port map(A => \op2[24]\, B => \un1_iu0_6[24]\, Y => N470); - - \r.e.op2_RNO_8[9]\ : OR2A - port map(A => \maddress[9]\, B => d27, Y => - \result_m_i_0[9]\); - - \r.e.op1_RNISAA2F3[12]\ : NOR3C - port map(A => \op1_m_0[12]\, B => \d_iv_2[12]\, C => - \aluresult_m_0[12]\, Y => \d_i[12]\); - - \comb.v.f.pc_1_iv[3]\ : NAND2 - port map(A => \un6_fe_npc_m[1]\, B => \pc_1_iv_2[3]\, Y => - \pc_1[3]\); - - \r.e.op1_RNI4LC1B[8]\ : NOR3 - port map(A => \bpdata_i_m_2[0]\, B => \edata2_0_iv_0[8]\, C - => \bpdata_i_m[8]\, Y => edata2_0_iv(8)); - - \r.e.op2_RNI0SHN1[19]\ : OR2B - port map(A => \un1_iu0_5[85]\, B => aluresult_7_sqmuxa, Y - => \ex_op2_m[19]\); - - \r.d.cnt_RNITFU4[1]\ : NOR3B - port map(A => \inst_0_0[22]\, B => \cnt_0[1]\, C => annul_1, - Y => ldcheck2_2_sqmuxa_1_1); - - \r.m.y_RNO_4[6]\ : OR2B - port map(A => \y[7]\, B => mulstep_0, Y => \y_m[7]\); - - \r.e.aluop_RNITH234[1]\ : OR2B - port map(A => \bpdata[5]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[5]\); - - \r.x.ctrl.rd_RNIHVH6[3]\ : XNOR2 - port map(A => \rd_2[3]\, B => \rd[3]\, Y => rd_3_i_0); - - \r.m.y_RNO_2[14]\ : OR2A - port map(A => \logicout[14]\, B => y14, Y => N_385); - - \r.f.pc_RNO_0[20]\ : NAND2 - port map(A => \tmp[20]\, B => \un2_rstn_5\, Y => - \tmp_m[20]\); - - \r.e.op2_RNO_4[11]\ : OA1A - port map(A => \maddress[11]\, B => d27_0, C => - \cpi_m_i[363]\, Y => \d_1_iv_1[11]\); - - \r.a.imm_RNO[17]\ : MX2 - port map(A => \inst_0[7]\, B => \un1_p0_6_0[51]\, S => - call_hold5_0, Y => \un3_de_ren1[135]\); - - \r.x.ctrl.inst[22]\ : DFN1E0 - port map(D => \inst_2[22]\, CLK => lclk_c, E => holdn, Q - => \inst_0[22]\); - - \r.e.aluop_RNIN5234[1]\ : OR2B - port map(A => \bpdata[4]\, B => aluresult_4_sqmuxa, Y => - \bpdata_m_2[4]\); - - \r.x.ctrl.wreg_RNI0N1T1\ : NOR2 - port map(A => xc_wreg_1, B => holdn, Y => wren); - - \r.w.s.dwt_RNIEL2V1\ : OA1A - port map(A => dwt, B => aluresult_9_sqmuxa, C => - aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[14]\); - - \r.m.y_RNI5FKVP[30]\ : NOR3C - port map(A => \aluresult_1_iv_5[30]\, B => - \aluresult_1_iv_4[30]\, C => \logicout_m_0[30]\, Y => - \aluresult_1_iv_7[30]\); - - \r.e.op2_RNO_3[20]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[20]\, Y => - \aluresult_m_i[20]\); - - \r.m.dci.read_0\ : DFN1E0 - port map(D => read, CLK => lclk_c, E => holdn, Q => read_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I17_P0N : OR2 - port map(A => \un1_iu0_6[16]\, B => \op2[16]\, Y => N446_0); - - \r.m.result[30]\ : DFN1E0 - port map(D => \eres2[30]\, CLK => lclk_c, E => holdn, Q => - \maddress[30]\); - - \r.a.imm_RNO[3]\ : NOR2B - port map(A => \inst_0_RNI3RUM[3]\, B => call_hold5, Y => - \un3_de_ren1[121]\); - - \r.e.shcnt[1]\ : DFN1E0 - port map(D => N_267_i_i_0, CLK => lclk_c, E => holdn, Q => - \shcnt[1]\); - - \r.e.op2[20]\ : DFN1E0 - port map(D => N_304, CLK => lclk_c, E => holdn, Q => - \op2[20]\); - - \r.x.result_RNI5S9N3[12]\ : MX2C - port map(A => \un1_iu0_6[12]\, B => \un1_p0_6[364]\, S => - bpdata6, Y => \bpdata[12]\); - - \r.e.op1_RNI4HFC[0]\ : OR2B - port map(A => \op1[0]\, B => un14_casaen_s1_0, Y => - \op1_m_0[0]\); - - \r.f.pc_RNO_0[4]\ : NOR3C - port map(A => \pc_4_m[4]\, B => \xc_trap_address_m[4]\, C - => \un6_ex_add_res_m_1[5]\, Y => \pc_1_iv_1[4]\); - - \r.e.ctrl.inst[24]\ : DFN1E0 - port map(D => \inst_1[24]\, CLK => lclk_c, E => holdn, Q - => \inst[24]\); - - \r.x.ctrl.pc_RNIEAHF[24]\ : MX2 - port map(A => \pc_0[24]\, B => \pc[24]\, S => \npc_0[1]\, Y - => N_3235); - - \r.d.inull_RNILH7FU\ : OA1C - port map(A => \inull\, B => \de_hold_pc_1\, C => - \un1_p0_6[0]\, Y => pv_4_0); - - \r.x.ctrl.wreg\ : DFN1E0 - port map(D => wreg_4, CLK => lclk_c, E => holdn, Q => wreg); - - \r.x.ctrl.ld_0_RNIH0TN2_0\ : NOR3C - port map(A => bpdata6_8, B => bpdata6_7, C => bpdata6_9, Y - => bpdata6); - - \r.d.inst_0_RNI38FS[28]\ : NOR2 - port map(A => un19_rd_1, B => \rd_3[0]\, Y => un19_rd); - - \r.m.y_RNO_4[3]\ : OR3A - port map(A => \y_2[3]\, B => wy_0, C => wy_1_0_0, Y => - \y_m[3]\); - - \r.e.aluop_RNIFOHL_0[1]\ : NOR3A - port map(A => logicout19_0, B => \aluop_3[1]\, C => - un17_casaen_0, Y => edata_2_sqmuxa); - - \r.x.result_RNICU1O3[22]\ : MX2 - port map(A => \un1_iu0_6[22]\, B => \un1_p0_6[374]\, S => - bpdata6, Y => \bpdata[22]\); - - \r.d.inst_0_RNO[18]\ : NOR2B - port map(A => rst, B => N_4618, Y => \inst_0_RNO[18]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I293_Y_0 : XOR2 - port map(A => \un6_ex_add_res_s2_1[3]\, B => N616_1, Y => - \un6_ex_add_res_s2[3]\); - - \r.x.icc[0]\ : DFN1E0 - port map(D => \icc_0[0]\, CLK => lclk_c, E => holdn, Q => - \icc_2[0]\); - - \r.d.inst_0[6]\ : DFN1 - port map(D => \inst_0_RNO[6]\, CLK => lclk_c, Q => - \inst_0[6]\); - - un6_fe_npc_I_9 : XOR2 - port map(A => N_147, B => \fe_pc[4]\, Y => I_9); - - \r.m.y_RNO_1[9]\ : OR2B - port map(A => \y_0[10]\, B => mulstep_1, Y => \y_m[10]\); - - \r.m.ctrl.wreg_RNO\ : NOR2A - port map(A => wreg_7, B => \un1_p0_6[0]\, Y => wreg_1_9); - - \r.a.imm[29]\ : DFN1E0 - port map(D => \un3_de_ren1[147]\, CLK => lclk_c, E => holdn, - Q => \imm[29]\); - - \r.x.ctrl.wicc_RNIIE1U1\ : NOR2 - port map(A => cwp_1_sqmuxa, B => wicc, Y => icc_0_sqmuxa_0); - - \comb.branch_address.tmp_ADD_30x30_fast_I25_P0N\ : OR2 - port map(A => \inst_0_1[27]\, B => \dpc[27]\, Y => N434_1); - - \r.e.op2_RNIAFA92[18]\ : AOI1B - port map(A => \un1_iu0_5[84]\, B => aluresult_7_sqmuxa_0_0, - C => aluresult_8_sqmuxa_i, Y => \aluresult_1_iv_0[18]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I274_Y_0\ : XNOR2 - port map(A => N726_i, B => ADD_30x30_fast_I274_Y_0_0, Y => - \tmp[16]\); - - \r.w.s.et_RNI8EAN\ : NOR2A - port map(A => et, B => N_6357, Y => N_6350); - - \r.w.s.tt_RNIEOR7H[0]\ : AOI1B - port map(A => \bpdata[4]\, B => N_3957, C => - \aluresult_1_iv_5[4]\, Y => \aluresult_1_iv_6[4]\); - - \r.a.rfa2_RNI9V361[1]\ : MX2 - port map(A => \inst_0_RNI1JUM[1]\, B => \rfa2[1]\, S => - holdn, Y => raddr2(1)); - - \r.m.icc[2]\ : DFN1E0 - port map(D => \icco[2]\, CLK => lclk_c, E => holdn, Q => - \icc_0[2]\); - - \r.f.pc[4]\ : DFN1E0 - port map(D => \pc_1[4]\, CLK => lclk_c, E => holdn, Q => - \fpc[4]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I268_Y_0 : AO1D - port map(A => ADD_33x33_fast_I268_un1_Y_0, B => N674, C => - N642_1, Y => ADD_33x33_fast_I268_Y_0); - - \r.x.annul_all\ : DFN1E0 - port map(D => \un1_p0_6[0]\, CLK => lclk_c, E => holdn, Q - => annul_all); - - \r.w.s.y[12]\ : DFN1E0 - port map(D => N_3776, CLK => lclk_c, E => N_6922_i_0, Q => - \y_0[12]\); - - \r.e.op1_RNIJ8CP02[3]\ : MX2 - port map(A => \aluresult[3]\, B => \op1[3]\, S => - \un17_casaen_0_0\, Y => \eres2[3]\); - - \r.a.ticc_RNO\ : NOR3C - port map(A => N_145, B => ticc_exception_0_a3_1, C => - branch_1, Y => ticc_exception); - - \r.a.ctrl.trap_RNIFQU8\ : OR2 - port map(A => trap_1, B => annul_2, Y => \tt_0[2]\); - - \r.m.y_RNO[29]\ : AO1C - port map(A => y14_0, B => \logicout[29]\, C => - \y_iv_0_2[29]\, Y => \y_1[29]\); - - \r.d.pc[25]\ : DFN1 - port map(D => \pc_RNO[25]\, CLK => lclk_c, Q => \dpc[25]\); - - \r.w.s.y[7]\ : DFN1E0 - port map(D => N_3771, CLK => lclk_c, E => N_6922_i, Q => - \y_0[7]\); - - \r.e.aluop_1_RNI20LK2[1]\ : MX2C - port map(A => \logicout_4[20]\, B => N_6847, S => N_6866_i, - Y => N_3643); - - un6_ex_add_res_d1_ADD_33x33_fast_I265_Y_0 : AOI1 - port map(A => N578_1, B => N571_0, C => N570_0, Y => - ADD_33x33_fast_I265_Y_0_0); - - \r.e.op2_RNI40NB1_0[15]\ : OR2 - port map(A => \un1_iu0_6[15]\, B => \un1_iu0_5[81]\, Y => - \logicout_3[15]\); - - \r.d.inst_0_RNIMRAH[23]\ : AO1 - port map(A => N_3739, B => N_3738, C => un5_op3, Y => - \inst_0_RNIMRAH[23]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I265_un1_Y : OR2B - port map(A => ADD_33x33_fast_I265_un1_Y_0_1, B => N814_0, Y - => I265_un1_Y_i_1); - - \r.x.rstate_RNI31F9[1]\ : OR2A - port map(A => \rstate[1]\, B => \rstate[0]\, Y => - rstate_6314_d); - - \r.d.pc_RNIQBBA4[4]\ : MX2 - port map(A => \dpc[4]\, B => \fpc[4]\, S => ra_bpmiss_1, Y - => N_3881); - - un6_ex_add_res_d1_ADD_33x33_fast_I259_Y_3 : OA1A - port map(A => N625, B => N640, C => ADD_33x33_fast_I259_Y_2, - Y => ADD_33x33_fast_I259_Y_3_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I264_Y : NAND2 - port map(A => I264_un1_Y_0, B => ADD_33x33_fast_I264_Y_1_0, - Y => N774); - - un6_ex_add_res_d1_ADD_33x33_fast_I57_Y : MAJ3 - port map(A => \op2[18]\, B => \un1_iu0_6[18]\, C => N448_0, - Y => N516_0); - - \r.e.shleft_RNI29S82\ : MX2B - port map(A => \shiftin_5[32]\, B => \shiftin_5[16]\, S => - \ex_shcnt_1_i[4]\, Y => \shiftin_8[16]\); - - \r.e.op2_RNO_3[31]\ : OR2B - port map(A => un14_casaen_s0, B => \aluresult[31]\, Y => - \aluresult_m_i[31]\); - - \comb.op_mux.d_1_iv_RNO[29]\ : NAND2 - port map(A => \aluresult[29]\, B => un14_casaen_s0_0_1, Y - => \aluresult_m_i[29]\); - - \r.m.ctrl.pc_RNIQHGF[21]\ : MX2 - port map(A => \pc_3[21]\, B => \pc[21]\, S => \npc_1[1]\, Y - => N_3262); - - \comb.branch_address.tmp_ADD_30x30_fast_I102_Y\ : AO1 - port map(A => N467_1, B => N464_1, C => N463_0, Y => N522); - - \r.e.ctrl.pc_RNICPK11[17]\ : OR2B - port map(A => \pc_0[17]\, B => jmpl_0, Y => \cpi_m[162]\); - - \r.a.ctrl.inst_RNIPCKH[27]\ : AX1E - port map(A => N_375, B => \inst_2[27]\, C => \inst_1[28]\, - Y => N_3339); - - \r.m.dci.asi_RNO[0]\ : MX2 - port map(A => su, B => \inst_1[5]\, S => \inst_0[23]\, Y - => \asi[0]\); - - \r.m.result_RNIF407[7]\ : OR2B - port map(A => d13_0, B => \maddress[7]\, Y => - \result_m_0[7]\); - - \r.x.result_RNIK4OE[24]\ : OR2B - port map(A => \un1_p0_6[376]\, B => d14, Y => - \cpi_m_0[376]\); - - \r.e.ctrl.inst[27]\ : DFN1E0 - port map(D => \inst_2[27]\, CLK => lclk_c, E => holdn, Q - => \inst_1[27]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I79_Y_0 : AO1 - port map(A => N419, B => N415_0, C => N418_0, Y => N538); - - \r.e.aluop_RNI50MK4[0]\ : OR2B - port map(A => \logicout[5]\, B => aluresult_3_sqmuxa_0, Y - => \logicout_m_0[5]\); - - \r.m.y_RNINTN71[10]\ : OR2B - port map(A => \y_0[10]\, B => aluresult_10_sqmuxa, Y => - \y_m_1[10]\); - - \r.a.ctrl.pc[7]\ : DFN1E0 - port map(D => \dpc[7]\, CLK => lclk_c, E => holdn, Q => - \pc_3[7]\); - - \r.a.ctrl.inst_RNIB41E_1[23]\ : NOR2A - port map(A => \inst_1[23]\, B => \inst_1[24]\, Y => - inst_22_0); - - \r.w.s.tba[18]\ : DFN1E1 - port map(D => \result_0[30]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[18]\); - - \r.m.result_RNO[23]\ : MX2 - port map(A => \aluresult[23]\, B => \op1[23]\, S => - un17_casaen_0_1, Y => \eres2[23]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I244_un1_Y_0\ : NOR2B - port map(A => N591, B => N358, Y => - ADD_30x30_fast_I244_un1_Y_0); - - \r.w.s.tt_RNI1P79B[0]\ : AOI1B - port map(A => \logicout[4]\, B => aluresult_3_sqmuxa_0, C - => \aluresult_1_iv_4[4]\, Y => \aluresult_1_iv_5[4]\); - - \r.a.ctrl.inst_RNIJ02S_0[21]\ : OR2 - port map(A => N_271, B => N_209, Y => - illegal_inst_7_iv_2_0_a5_1_0); - - \r.a.ctrl.rd[0]\ : DFN1E0 - port map(D => \rd_3[0]\, CLK => lclk_c, E => holdn, Q => - \rd_2[0]\); - - \r.m.ctrl.pc_RNIT9HF[14]\ : MX2 - port map(A => \pc_2[14]\, B => \pc[14]\, S => \npc_0[1]\, Y - => N_3255); - - \r.e.aluop_RNIBKTF6[1]\ : AOI1B - port map(A => edata_2_sqmuxa, B => \bpdata[30]\, C => - \edata2_iv_0[30]\, Y => \edata2_iv_1[30]\); - - \r.a.ctrl.cnt_RNIA2OG2[1]\ : AOI1 - port map(A => N_470, B => N_469, C => \cnt_2[1]\, Y => - N_483); - - un6_fe_npc_I_38 : XOR2 - port map(A => N_126_0, B => \fe_pc[9]\, Y => I_38); - - \r.w.s.y[1]\ : DFN1E0 - port map(D => N_163, CLK => lclk_c, E => holdn, Q => - \y_0[1]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I16_P0N : AO1A - port map(A => ldbp1_2, B => \op1[15]\, C => \data_0_2[15]\, - Y => N443_1); - - \r.w.result_RNI0I2L[26]\ : AOI1B - port map(A => \un1_p0_6[378]\, B => d14_0, C => - \result_m_0_0[26]\, Y => \d_iv_0[26]\); - - \r.d.pv_RNO_2\ : OR3B - port map(A => pv_RNO_6, B => pv_12_i_a6_0_2, C => ldlock, Y - => N_4241_i_0); - - \r.e.op2_RNO_2[8]\ : NOR3C - port map(A => \d_1_iv_1[8]\, B => \d_1_iv_0[8]\, C => - \rfo_m_i[40]\, Y => \d_1_iv_3[8]\); - - un6_fe_npc_I_135 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[15]\, Y => N_56); - - \r.e.aluop_1_RNIFAJ5[1]\ : NOR3B - port map(A => \aluop_0[2]\, B => \aluop_0[0]\, C => - \aluop_1[1]\, Y => logicout20); - - \r.e.op2_RNIMCB71_0[28]\ : OR2 - port map(A => \un1_iu0_6[28]\, B => \un1_iu0_5[94]\, Y => - \logicout_3[28]\); - - \r.e.op1_RNI3E4B2[26]\ : AND2 - port map(A => \ex_op1_i_m[26]\, B => \op1_RNI3RNF[26]\, Y - => \edata2_iv_0[26]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I14_G0N : NOR3A - port map(A => \op1[13]\, B => ldbp1_0, C => \data_0[13]\, Y - => N436_1); - - un6_ex_add_res_d1_ADD_33x33_fast_I292_Y_0 : XNOR3 - port map(A => \un1_iu0_6[1]\, B => \op2[1]\, C => N552_0, Y - => \un6_ex_add_res_s1_i[2]\); - - \r.x.data_0_RNI6F9E[10]\ : XOR2 - port map(A => \data_0[10]\, B => invop2_0, Y => N_4257); - - un6_ex_add_res_d0_ADD_33x33_fast_I105_Y : AO1 - port map(A => N506_0, B => N503_0, C => N502_0, Y => N568_0); - - \r.x.ctrl.inst[31]\ : DFN1E0 - port map(D => \inst_1[31]\, CLK => lclk_c, E => holdn, Q - => \inst_3[31]\); - - \r.e.ctrl.inst[19]\ : DFN1E0 - port map(D => \inst_2[19]\, CLK => lclk_c, E => holdn, Q - => \inst[19]\); - - \r.m.ctrl.pc[5]\ : DFN1E0 - port map(D => \pc[5]\, CLK => lclk_c, E => holdn, Q => - \pc_2[5]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I264_Y : OR2 - port map(A => I264_un1_Y, B => ADD_33x33_fast_I264_Y_1, Y - => N774_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I262_Y_0_a3_0_0 : NOR2A - port map(A => N503_0, B => N_50_0, Y => - ADD_33x33_fast_I262_Y_0_a3_0); - - \r.e.op1_RNIIDM62[30]\ : OA1A - port map(A => edata_3_sqmuxa_0, B => \un1_iu0_6[30]\, C => - \op1_RNIU2NF[30]\, Y => \edata2_iv_0[30]\); - - \r.e.aluop_0_RNIRT6R[1]\ : XOR3 - port map(A => \un1_iu0_6[8]\, B => \aluop_0[1]\, C => - \un1_iu0_5[74]\, Y => N_6868); - - \comb.branch_address.tmp_ADD_30x30_fast_I24_P0N\ : OR2A - port map(A => \inst_0_1[26]\, B => \dpc[26]\, Y => N431); - - un6_ex_add_res_d2_ADD_33x33_fast_I166_Y : NOR2B - port map(A => N577_1, B => N569_1, Y => N635); - - \r.m.y_RNI64K91[0]\ : OR2B - port map(A => \y_0[0]\, B => aluresult_10_sqmuxa, Y => - \y_m_0[0]\); - - \r.a.ctrl.wreg\ : DFN1E0 - port map(D => wreg_1_11, CLK => lclk_c, E => holdn, Q => - wreg_0); - - \r.e.ctrl.inst[5]\ : DFN1E0 - port map(D => \inst[5]\, CLK => lclk_c, E => holdn, Q => - \inst_1[5]\); - - \r.m.icc_RNO_12[2]\ : NOR2 - port map(A => \logicout[26]\, B => \logicout[27]\, Y => - icc_0_sqmuxa_1_9); - - un6_fe_npc_I_34 : AND3 - port map(A => \fe_pc[5]\, B => \fe_pc[6]\, C => \fe_pc[7]\, - Y => \DWACT_FINC_E[2]\); - - \r.d.pc[12]\ : DFN1 - port map(D => \pc_RNO[12]\, CLK => lclk_c, Q => \dpc[12]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I156_Y : NOR2B - port map(A => N567, B => N559, Y => N625_1); - - \r.f.pc_RNO_1[7]\ : AOI1B - port map(A => de_hold_pc_1_0, B => \pc_4[7]\, C => - \xc_trap_address_m[7]\, Y => \pc_1_iv_0[7]\); - - \r.d.inst_0_RNO[27]\ : NOR2B - port map(A => rst, B => N_4627, Y => \inst_0_RNO[27]\); - - \r.a.ctrl.rd_RNO[6]\ : NOR2A - port map(A => I_14, B => un3_reg, Y => N_37); - - un6_ex_add_res_d1_ADD_33x33_fast_I20_P0N : OR2 - port map(A => \op1_RNID1VH[19]\, B => \op2[19]\, Y => - N455_2); - - \r.m.y_RNO_3[12]\ : OR3A - port map(A => \y_2[12]\, B => wy_3, C => wy_1_0_1, Y => - \y_m_0[12]\); - - \r.e.op1_RNIH1UB[6]\ : OR2A - port map(A => un17_casaen_0_1, B => \op1[6]\, Y => - \op1_i_m[6]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I136_Y : OR2B - port map(A => N537_0, B => N533, Y => N599_0); - - un6_ex_add_res_d2_ADD_33x33_fast_I84_Y : OA1 - port map(A => \data_0[5]\, B => \un1_iu0_6[5]\, C => N410_2, - Y => N543_1); - - \r.e.ctrl.tt[1]\ : DFN1E0 - port map(D => \tt_1[1]\, CLK => lclk_c, E => holdn, Q => - \tt_3[1]\); - - \r.m.y_RNO_3[6]\ : OR3A - port map(A => \y_2[6]\, B => wy_0, C => wy_1_0_0, Y => - \y_m_0[6]\); - - \r.e.ctrl.tt_RNO_1[5]\ : OR2B - port map(A => \tt_9_0_a3_0[5]\, B => privileged_inst_5, Y - => N_4042); - - \r.d.pc_RNO[25]\ : MX2 - port map(A => \fpc[25]\, B => \dpc[25]\, S => N_6763_i, Y - => \pc_RNO[25]\); - - \r.e.op2_RNO_1[9]\ : NOR3C - port map(A => \rfo_m_i[41]\, B => \d_1_iv_2[9]\, C => - \op1_m_i[9]\, Y => \d_1_iv_4[9]\); - - \r.m.ctrl.pc_RNIIPN9[28]\ : MX2 - port map(A => \pc_3[28]\, B => \pc[28]\, S => \npc[1]\, Y - => N_3269); - - \r.d.cwp_RNO[0]\ : MX2 - port map(A => N_4227, B => \cwp_1_0[0]\, S => N_6358, Y => - \cwp_1_1[0]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I308_Y_0 : AX1B - port map(A => I239_un1_Y_1, B => ADD_33x33_fast_I273_Y_0, C - => \un6_ex_add_res_s2_1[18]\, Y => - \un6_ex_add_res_s0[18]\); - - \r.e.op2_RNIA9IG[6]\ : MX2 - port map(A => \op2[6]\, B => N_4253, S => ldbp2_1, Y => - \un1_iu0_5[72]\); - - \r.a.ctrl.inst[13]\ : DFN1E0 - port map(D => \inst_0[13]\, CLK => lclk_c, E => holdn, Q - => \inst[13]\); - - \r.e.ctrl.inst_RNIFP984[26]\ : AO1 - port map(A => ex_bpmiss_1_0_a5_0_0, B => N_261, C => - ex_bpmiss_1_0_0, Y => ex_bpmiss_1_0_1); - - \r.w.s.icc[1]\ : DFN1E0 - port map(D => \icc_1[1]\, CLK => lclk_c, E => holdn, Q => - \icc_0[1]\); - - \r.d.annul_RNIR3UT7\ : NOR2A - port map(A => annul_current_2_sqmuxa_1, B => annul_1, Y => - G_6_0); - - \comb.ld_align.rdata199_RNICVM0R4\ : OR2 - port map(A => \rdata_17_m[8]\, B => \rdata_9_m[8]\, Y => - \data_0_1_1[16]\); - - un6_fe_npc_I_45 : XOR2 - port map(A => N_121, B => \fe_pc[10]\, Y => I_45); - - \r.d.inst_0[20]\ : DFN1 - port map(D => \inst_0_RNO[20]\, CLK => lclk_c, Q => - \inst_0[20]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I202_un1_Y\ : OR2B - port map(A => N594, B => N579, Y => I202_un1_Y_i); - - \comb.branch_address.tmp_ADD_30x30_fast_I107_Y\ : NOR2B - port map(A => N472, B => N468, Y => N527_2); - - un9_ra_I_15 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP_2[0]\, B => \cwp[1]\, Y - => \DWACT_ADD_CI_0_g_array_1_2[0]\); - - \r.d.inst_0[9]\ : DFN1 - port map(D => \inst_0_RNO[9]\, CLK => lclk_c, Q => - \inst_0[9]\); - - \r.x.data_0[8]\ : DFN1E0 - port map(D => \data_0_1[8]\, CLK => lclk_c, E => - mexc_1_sqmuxa, Q => \data_0[8]\); - - \r.f.pc_RNO_0[26]\ : NAND2 - port map(A => \tmp[26]\, B => \un2_rstn_5\, Y => - \tmp_m[26]\); - - \r.e.op2_RNO[23]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[23]\, Y => N_307); - - \r.m.result_RNIUSA4[1]\ : OR2B - port map(A => d13, B => \maddress[1]\, Y => \result_m_0[1]\); - - \r.m.ctrl.rd_RNI8KI31[5]\ : XNOR2 - port map(A => \rd_2[5]\, B => \un3_de_ren1[96]\, Y => - un2_rs1_2_5_i_0); - - \r.e.ctrl.inst_RNIJP861[21]\ : AO1B - port map(A => read_1_sqmuxa_i, B => \inst_1[22]\, C => - \inst_1[21]\, Y => read); - - \r.w.s.s\ : DFN1 - port map(D => s_RNO, CLK => lclk_c, Q => s); - - \r.w.s.tba_RNI2FFP5[5]\ : AOI1B - port map(A => \bpdata[17]\, B => aluresult_6_sqmuxa, C => - \tba_m[5]\, Y => \aluresult_1_iv_3[17]\); - - \r.x.result_RNILIE25[8]\ : NOR2A - port map(A => \aluop_RNIGM3N1[2]\, B => \bpdata[8]\, Y => - \bpdata_i_m[8]\); - - \r.w.s.tba_RNIQ07Q5[4]\ : AOI1B - port map(A => \bpdata[16]\, B => aluresult_6_sqmuxa, C => - \tba_m[4]\, Y => \aluresult_1_iv_3[16]\); - - \r.e.op1_RNI3RNF[26]\ : OR2A - port map(A => \un17_casaen_0_0\, B => \op1[26]\, Y => - \op1_RNI3RNF[26]\); - - \r.a.ctrl.inst_RNIPUDB[12]\ : NOR2A - port map(A => \inst[6]\, B => \inst[12]\, Y => - un29_casaen_1); - - \r.x.result_RNI8TQJF[3]\ : AND2 - port map(A => \aluresult_1_iv_4[19]\, B => \bpdata_m_1[3]\, - Y => \aluresult_1_iv_5[19]\); - - \r.w.s.tt_RNI7M7N7[0]\ : AOI1B - port map(A => aluresult_12_sqmuxa_0_0, B => \irl[0]\, C => - \aluresult_1_iv_3[4]\, Y => \aluresult_1_iv_4[4]\); - - \r.a.ctrl.inst_RNIR82H1[20]\ : OR3B - port map(A => N_351_1, B => \inst_2[20]\, C => N_260, Y => - cp_disabled_11_sqmuxa); - - \r.m.y_RNISB823[1]\ : AOI1 - port map(A => \y[1]\, B => aluresult_10_sqmuxa_0, C => - \aluresult_4[1]\, Y => \aluresult_2_iv_1[1]\); - - \comb.lock_gen.un1_icc_check5_RNO_2\ : NOR2B - port map(A => icc_check10, B => icc_check9, Y => - un1_icc_check5_0); - - \r.w.s.et\ : DFN1E0 - port map(D => et_1_0, CLK => lclk_c, E => holdn, Q => et); - - \r.e.op2_RNO_1[10]\ : NOR3C - port map(A => \rfo_m_i[42]\, B => \d_1_iv_2[10]\, C => - \op1_m_i[10]\, Y => \d_1_iv_4[10]\); - - \r.e.op2_RNO_7[5]\ : OR3C - port map(A => d28_0_0, B => \rsel2_0[0]\, C => - \un1_p0_6[357]\, Y => \cpi_m_i[357]\); - - \r.e.aluop_1_RNIFHJD1[1]\ : XOR3 - port map(A => \un1_iu0_6[27]\, B => \aluop_1[1]\, C => - \un1_iu0_5[93]\, Y => N_6892); - - \r.e.shcnt_RNI8TD86[3]\ : MX2 - port map(A => \shiftin_8[31]\, B => \shiftin_8[23]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[23]\); - - \r.x.ctrl.pc_RNIJQHF[26]\ : MX2 - port map(A => \pc_2[26]\, B => \pc[26]\, S => \npc_1[1]\, Y - => N_3237); - - \r.e.jmpl_RNI2AGPO\ : OR2B - port map(A => \shiftin_17[14]\, B => aluresult_2_sqmuxa, Y - => \shiftin_17_m_0[14]\); - - \r.d.inst_0_RNO[25]\ : NOR2B - port map(A => rst, B => N_4625, Y => \inst_0_RNO[25]\); - - \r.d.pc_RNI2UGB4[19]\ : MX2 - port map(A => \dpc[19]\, B => \fpc[19]\, S => ra_bpmiss_1, - Y => N_3896); - - \r.f.pc_RNO_2[29]\ : OR2B - port map(A => I_196, B => annul_RNIVCQHS1, Y => - \un6_fe_npc_m[27]\); - - \r.a.ctrl.inst_RNIJ42L[19]\ : OR2A - port map(A => \inst_2[19]\, B => N_202, Y => N_205); - - \r.e.alusel[0]\ : DFN1E0 - port map(D => N_3838_i_0, CLK => lclk_c, E => holdn, Q => - \alusel[0]\); - - \r.m.y_RNIV9AV2[26]\ : AOI1B - port map(A => \un1_iu0_5[92]\, B => aluresult_7_sqmuxa_0_0, - C => \y_m_1[26]\, Y => \aluresult_1_iv_0[26]\); - - \r.x.ctrl.pc_RNIGB431[5]\ : MX2C - port map(A => \un1_p0_6[357]\, B => \pc_3[5]\, S => - s_3_sqmuxa, Y => N_3396); - - \r.e.op1_RNO[17]\ : MX2C - port map(A => \d_i[17]\, B => \d_i[18]\, S => N_227_0, Y - => \aop1[17]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I260_Y : NAND2 - port map(A => I260_un1_Y_i_0, B => - ADD_33x33_fast_I260_Y_3_0, Y => N766_0); - - \r.e.op1_RNI8V5RB[15]\ : NOR2 - port map(A => \edata2_0_iv_1[15]\, B => \bpdata_i_m[15]\, Y - => edata2_0_iv(15)); - - \r.e.aluop_RNICEFV[1]\ : NOR2B - port map(A => miscout140_1, B => logicout21_1, Y => - un1_logicout21); - - \r.e.shcnt_RNIP0L54[3]\ : MX2 - port map(A => \shiftin_8[14]\, B => \shiftin_8[6]\, S => - \ex_shcnt_1_i_0[3]\, Y => \shiftin_11[6]\); - - \r.m.icc_RNIJES6[2]\ : AX1 - port map(A => \icc_0[2]\, B => N_211, C => \inst_0[28]\, Y - => branch_3_i); - - \r.f.pc[10]\ : DFN1E0 - port map(D => \pc_1[10]\, CLK => lclk_c, E => holdn, Q => - \fpc[10]\); - - \r.w.result_RNI40P1[10]\ : OR3C - port map(A => N_484, B => \rsel1[2]\, C => \result_0[10]\, - Y => \result_m_0_0[10]\); - - \comb.branch_address.tmp_ADD_30x30_fast_I47_Y\ : NOR2B - port map(A => N419_2, B => N416_2, Y => N464_1); - - \r.m.y_RNO[30]\ : AO1C - port map(A => y14_0, B => \logicout[30]\, C => \y_iv_2[30]\, - Y => \y_1[30]\); - - \r.e.shleft_RNIP496\ : NOR2A - port map(A => \un1_iu0_6[9]\, B => shleft, Y => - \shiftin_5_i[9]\); - - \r.m.ctrl.pc[31]\ : DFN1E0 - port map(D => \pc[31]\, CLK => lclk_c, E => holdn, Q => - \pc_3[31]\); - - \r.e.op2_RNO_1[26]\ : OR2B - port map(A => \op1[26]\, B => un14_casaen_s1, Y => - \op1_m_i[26]\); - - \r.x.ctrl.pc_RNIJMF8[3]\ : MX2 - port map(A => \pc_2[3]\, B => \pc_0[3]\, S => \npc[1]\, Y - => N_3214); - - \r.m.casa_RNISFIB692\ : OR2B - port map(A => me_nullify2_1_0, B => un17_casaen, Y => - nullify); - - \r.f.pc_RNIUDRO73[7]\ : MX2 - port map(A => I_24, B => N_4050, S => bpmiss_1_i_0, Y => - \pc_4[7]\); - - \r.a.imm_RNIDE7U[0]\ : NOR3C - port map(A => \result_m_i[0]\, B => \imm_m_i[0]\, C => - \d_1_iv_1[0]\, Y => \d_1_iv_2[0]\); - - \r.e.aluop_RNIFBIJ1[2]\ : XA1 - port map(A => \un1_iu0_5[79]\, B => \aluop_1[2]\, C => - \un1_iu0_6[13]\, Y => N_3540); - - un37_ra_I_9 : XOR2 - port map(A => \cwp_0[0]\, B => \inst_0_RNI4VUM[4]\, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \r.m.y_RNO[21]\ : AO1C - port map(A => y14_0, B => \logicout[21]\, C => \y_iv_2[21]\, - Y => \y_0[21]\); - - \r.d.inst_0_RNIAO79_0[23]\ : MX2 - port map(A => \un1_p0_6_0[60]\, B => \inst_0_0[23]\, S => - \inst_0[30]\, Y => \inst_0_1[25]\); - - \r.e.shleft_1_RNIQGHP\ : OR2A - port map(A => \un1_iu0_6[21]\, B => shleft_1, Y => - \shiftin_5[21]\); - - \r.e.jmpl_RNIS6CTU1\ : NOR3C - port map(A => \shiftin_17_m[6]\, B => \aluresult_1_iv_7[5]\, - C => \shiftin_17_m_0[5]\, Y => \aluresult_1_iv_9[5]\); - - \r.e.aluop_0_RNIUIRJ2[0]\ : OR2B - port map(A => \logicout[0]\, B => aluresult_3_sqmuxa, Y => - \logicout_m_0[0]\); - - un6_ex_add_res_d2_ADD_33x33_fast_I31_P0N : OR2 - port map(A => \un1_iu0_6[30]\, B => \data_0[30]\, Y => N488); - - \r.x.rstate_RNIASEN3[1]\ : AO1A - port map(A => annul_1_0, B => y6_2, C => \rstate_d[2]\, Y - => et_0_sqmuxa); - - \r.a.rsel1_RNO[1]\ : NOR2A - port map(A => rfe_1_2, B => rfe_1_1, Y => N_4021); - - \r.a.ctrl.inst_RNIFG1L_0[22]\ : NOR2 - port map(A => \inst[22]\, B => N_216, Y => N_6681_1); - - \r.e.shleft_0_RNIHJBD1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[3]\, S => - shleft_0, Y => \shiftin_5[34]\); - - \r.d.inst_0_RNIT5TJ[26]\ : MX2C - port map(A => N_3346, B => N_3347, S => \inst_0[26]\, Y => - N_3348); - - \r.x.ctrl.pc[29]\ : DFN1E0 - port map(D => \pc_3[29]\, CLK => lclk_c, E => holdn, Q => - \pc_2[29]\); - - \r.e.op2_RNO_9[12]\ : OR3C - port map(A => d28_0_0, B => \rsel2_1[0]\, C => - \un1_p0_6[364]\, Y => \cpi_m_i[364]\); - - \r.e.op2_RNO_1[6]\ : OR2B - port map(A => \op1[6]\, B => un14_casaen_s1_0_1, Y => - \op1_m_i[6]\); - - \r.e.jmpl_RNIHHBJU_0\ : OR2B - port map(A => \shiftin_17[29]\, B => aluresult_2_sqmuxa_0, - Y => \shiftin_17_m_0[29]\); - - un6_fe_npc_I_159 : AND3 - port map(A => \fe_pc[23]\, B => \fe_pc[24]\, C => - \fe_pc[25]\, Y => \DWACT_FINC_E[17]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I22_P0N : OR2 - port map(A => \un1_iu0_6[21]\, B => \op2[21]\, Y => N461_0); - - \r.e.ctrl.inst_RNIFK0E_0[21]\ : NOR2A - port map(A => \inst_1[22]\, B => \inst_1[21]\, Y => - jump_0_sqmuxa_1_0); - - \r.d.cnt_RNID315[1]\ : NOR3B - port map(A => \inst_0[30]\, B => \inst_0[31]\, C => - \cnt_0[1]\, Y => de_inst_0_sqmuxa_0); - - un6_ex_add_res_d0_ADD_33x33_fast_I321_Y_0 : XNOR2 - port map(A => N766, B => \un6_ex_add_res_s2_1[31]\, Y => - \un6_ex_add_res_s0[31]\); - - \r.a.rfa1[4]\ : DFN1E0 - port map(D => \un3_de_ren1[95]\, CLK => lclk_c, E => holdn, - Q => \rfa1[4]\); - - \r.a.ctrl.inst_RNIOVAT5[20]\ : OR2B - port map(A => cp_disabled_4_0_1_1, B => cp_disabled_4_0_1_0, - Y => cp_disabled_4); - - \r.m.y_RNO_2[6]\ : OR2A - port map(A => \logicout[6]\, B => y14, Y => \logicout_m[6]\); - - \r.f.pc_RNI26HB4[26]\ : MX2 - port map(A => \dpc[26]\, B => \fpc[26]\, S => - \ra_bpmiss_1_0\, Y => N_3903); - - \r.m.y_RNO_3[31]\ : AOI1B - port map(A => \y[31]\, B => y08_0, C => ex_ymsb_1_m, Y => - \y_iv_0[31]\); - - \r.e.op2_RNO[31]\ : MX2C - port map(A => un1_aop2_1_sqmuxa, B => N_6697_i_0, S => - \d_1[31]\, Y => N_315); - - un6_ex_add_res_d2_ADD_33x33_fast_I2_G0N : OAI1 - port map(A => \op1[1]\, B => ldbp1_0, C => \data_0[1]\, Y - => N400_1); - - \r.f.pc_RNI3O4Q23[4]\ : NOR2B - port map(A => \un6_fe_npc_m[2]\, B => - \xc_trap_address_m[4]\, Y => \npc_iv_2[4]\); - - \r.e.op2_RNIH11O85_0[0]\ : OR3A - port map(A => \icc_8_1[1]\, B => \op2_RNI1LHG[1]\, C => - \op2_RNI59C6[0]\, Y => \icc_7[1]\); - - \r.a.imm[25]\ : DFN1E0 - port map(D => \un3_de_ren1[143]\, CLK => lclk_c, E => holdn, - Q => \imm[25]\); - - un6_fe_npc_I_73 : XOR2 - port map(A => N_101, B => \fe_pc[14]\, Y => I_73); - - \r.f.pc_RNI6AB62[4]\ : OR3C - port map(A => xc_exception_1, B => rst, C => - \xc_trap_address[4]\, Y => \xc_trap_address_m[4]\); - - \r.e.op2_RNO_5[31]\ : AOI1B - port map(A => \result[31]\, B => d31_0, C => \imm_m_i[31]\, - Y => \d_1_iv_0[31]\); - - \r.x.ctrl.inst_RNI2JBD2[24]\ : OR3A - port map(A => cwp_2_sqmuxa_4, B => annul_1_0, C => - tba_1_sqmuxa_3, Y => cwp_2_sqmuxa_i); - - \r.e.ctrl.pc[29]\ : DFN1E0 - port map(D => \pc[29]\, CLK => lclk_c, E => holdn, Q => - \pc_0[29]\); - - \r.d.inull_RNO_4\ : OR2A - port map(A => jmpl_2, B => annul_2, Y => N_96); - - un6_ex_add_res_d1_ADD_33x33_fast_I86_Y : NOR2B - port map(A => N410_1, B => N407, Y => N545_2); - - \r.e.op1_RNIQCHD[11]\ : MX2 - port map(A => \op1[11]\, B => \data_0_2[11]\, S => ldbp1, Y - => \un1_iu0_6[11]\); - - \r.x.data_0_RNO_0[21]\ : NOR2B - port map(A => rdata_6_sqmuxa, B => data_0_0_21, Y => - \dco_m_0[117]\); - - \r.x.intack_RNO_0\ : NOR2 - port map(A => \tt[6]\, B => \tt[7]\, Y => intack_1); - - \r.m.ctrl.wicc_RNIUN9L\ : MX2A - port map(A => N_4183, B => \icc[3]\, S => wicc_3, Y => - N_4188); - - \r.e.aluop_RNIQUNP8[2]\ : NOR2A - port map(A => \bpdata_i_m_0[14]\, B => \bpdata_i_m_2[6]\, Y - => \edata2_iv_2[30]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I270_Y_0_a3 : NOR2A - port map(A => N790, B => N_30_0, Y => N_71); - - \r.e.op2_RNO_0[28]\ : OR3C - port map(A => \op1_m_i[28]\, B => \d_1_iv_3[28]\, C => - \aluresult_m_i[28]\, Y => \d_1[28]\); - - un6_ex_add_res_d1_ADD_33x33_fast_I163_un1_Y : OR2A - port map(A => N574_1, B => N567_2, Y => I163_un1_Y_i); - - \r.m.result_0[1]\ : DFN1E0 - port map(D => \eres2[1]\, CLK => lclk_c, E => holdn, Q => - \maddress_0[1]\); - - \r.e.alusel_RNI5B9LTF[0]\ : AO1 - port map(A => \icc_12_iv_0[1]\, B => \icc_8_m_i[1]\, C => - aluresult12, Y => \icc_16[1]\); - - \r.m.icc_RNO_2[2]\ : MX2 - port map(A => \icc[2]\, B => \icc_2[2]\, S => wicc, Y => - N_4182); - - \comb.branch_address.tmp_ADD_30x30_fast_I241_Y_0_o3\ : AOI1 - port map(A => N_14, B => N716, C => N465, Y => N712_i); - - un6_ex_add_res_d2_ADD_33x33_fast_I263_Y_1 : AO1 - port map(A => N648_0, B => N633_0, C => - ADD_33x33_fast_I263_Y_0_0, Y => ADD_33x33_fast_I263_Y_1_0); - - un6_ex_add_res_d1_ADD_33x33_fast_I46_Y : AND2 - port map(A => N467_0, B => N470, Y => N505); - - \r.m.y_RNO_0[23]\ : AOI1B - port map(A => wy_1_0, B => \y_0[23]\, C => \y_m_0[23]\, Y - => \y_iv_1[23]\); - - \r.e.op1_RNIDU2LS6[25]\ : NOR3C - port map(A => \op1_m_0[25]\, B => \d_iv_2[25]\, C => - \aluresult_m_0[25]\, Y => \d_i[25]\); - - \r.d.cnt_RNIM0KB[0]\ : AXOI4 - port map(A => un4_op_0, B => \cnt_2[0]\, C => \cnt_0[1]\, Y - => un10_op); - - \r.x.data_0_RNIBF9E[14]\ : XOR2 - port map(A => \data_0[14]\, B => invop2_1, Y => N_4261); - - \r.d.pv_RNO_7\ : NOR3B - port map(A => \inst_0[31]\, B => pv_12_i_a6_0_1, C => - \cnt_0[1]\, Y => pv_12_i_a6_0_2); - - \r.m.ctrl.pc_RNIAIIF[29]\ : MX2 - port map(A => \pc_3[29]\, B => \pc[29]\, S => \npc_1[1]\, Y - => N_3270); - - \r.e.op2_RNI1LHG[1]\ : MX2 - port map(A => \op2[1]\, B => N_3305, S => ldbp2_1, Y => - \op2_RNI1LHG[1]\); - - \r.a.ctrl.inst[31]\ : DFN1E0 - port map(D => \inst_0[31]\, CLK => lclk_c, E => holdn, Q - => \inst[31]\); - - \r.m.ctrl.wicc\ : DFN1E0 - port map(D => wicc_1_1, CLK => lclk_c, E => holdn, Q => - wicc_3); - - \r.e.ctrl.trap_RNI202261\ : NOR3A - port map(A => enaddr_2_sqmuxa_3, B => un1_annul, C => - trap_0, Y => enaddr_2_sqmuxa); - - \r.e.aluop_RNIH2GOB[2]\ : AOI1B - port map(A => \bpdata[8]\, B => aluresult_5_sqmuxa, C => - \aluresult_1_iv_2[24]\, Y => \aluresult_1_iv_4[24]\); - - \r.x.data_0_RNO_4[0]\ : OR2A - port map(A => \data_0[0]\, B => ld_0_0, Y => - \data_0_m_i[0]\); - - \r.e.ctrl.inst[25]\ : DFN1E0 - port map(D => \inst_1[25]\, CLK => lclk_c, E => holdn, Q - => \inst_2[25]\); - - \r.e.aluop_0_RNIB49O1[1]\ : MX2C - port map(A => \logicout_4[7]\, B => N_6871, S => N_6866_i_0, - Y => N_3630); - - un6_ex_add_res_d2_ADD_33x33_fast_I37_Y : MAJ3 - port map(A => \data_0[28]\, B => \un1_iu0_6[28]\, C => - N478_2, Y => N496_1); - - un6_ex_add_res_d2_ADD_33x33_fast_I20_G0N : OA1 - port map(A => \op1[19]\, B => ldbp1_1, C => \data_0[19]\, Y - => N454_1); - - un6_ex_add_res_d0_ADD_33x33_fast_I300_Y_0 : XNOR2 - port map(A => \un6_ex_add_res_s2_1[10]\, B => N814_0, Y => - \un6_ex_add_res_s0[10]\); - - \r.x.ctrl.pc_RNI8QGF[12]\ : MX2 - port map(A => \pc_0[12]\, B => \pc_2[12]\, S => \npc_0[1]\, - Y => N_3223); - - \r.e.op1[4]\ : DFN1E0 - port map(D => N_167, CLK => lclk_c, E => holdn, Q => - \op1[4]\); - - \r.e.op2_RNO_5[19]\ : AOI1B - port map(A => \result[19]\, B => d31_0, C => \imm_m_i[19]\, - Y => \d_1_iv_0[19]\); - - \r.x.data_0_RNO[13]\ : OR3 - port map(A => \dco_m_0[109]\, B => \data_0_1_0_iv_0[13]\, C - => \data_0_1_4[9]\, Y => \data_0_1[13]\); - - \r.e.aluop[0]\ : DFN1E0 - port map(D => \aluop[0]\, CLK => lclk_c, E => holdn, Q => - \aluop_1[0]\); - - \r.w.s.tba[13]\ : DFN1E1 - port map(D => \result_0[25]\, CLK => lclk_c, E => - \inst_RNIHVSN2[24]\, Q => \tba[13]\); - - \r.w.s.icc[2]\ : DFN1E0 - port map(D => \icc_1[2]\, CLK => lclk_c, E => holdn, Q => - \icc[2]\); - - \r.m.result_RNIAGV6[2]\ : OR2B - port map(A => d13_0, B => \maddress[2]\, Y => - \result_m_0[2]\); - - \r.e.shleft_1_RNIV05I1\ : MX2 - port map(A => ex_sari_1_1_0_0, B => \un1_iu0_6[11]\, S => - shleft_1, Y => \shiftin_5[42]\); - - \r.e.aluop_RNI72NM9[1]\ : NOR2B - port map(A => \bpdata_m[15]\, B => \bpdata_m_2[7]\, Y => - \aluresult_1_iv_4[15]\); - - un6_fe_npc_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \r.w.s.wim_RNI834N2[1]\ : MX2 - port map(A => \wim[1]\, B => \result_0[1]\, S => - wim_1_sqmuxa, Y => \wim_1[1]\); - - \r.a.imm_RNI3645[2]\ : OR3B - port map(A => d29_0_0, B => \imm[2]\, C => \rsel2_0[0]\, Y - => \imm_m_i[2]\); - - un6_fe_npc_I_132 : AND3 - port map(A => \fe_pc[20]\, B => \fe_pc[21]\, C => - \fe_pc[22]\, Y => \DWACT_FINC_E[15]\); - - un6_ex_add_res_d0_ADD_33x33_fast_I66_Y : NOR2B - port map(A => N440_0, B => N437, Y => N525_1); - - \r.e.aluop_0_RNI69JD1[2]\ : XA1 - port map(A => \un1_iu0_5[83]\, B => \aluop_0[2]\, C => - \un1_iu0_6[17]\, Y => N_3544); - - \comb.un6_xc_exception\ : AND2 - port map(A => \xc_exception_1_0\, B => rst, Y => - un6_xc_exception); - - \r.x.rstate_0_RNIJUQD2[0]\ : MX2C - port map(A => N_3403, B => \xc_result[12]\, S => - \rstate_0[0]\, Y => \wdata[12]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu_dcache is - - port( data_1_19 : out std_logic; - data_1_18 : out std_logic; - data_1_17 : out std_logic; - data_1_16 : out std_logic; - data_1_15 : out std_logic; - data_1_14 : out std_logic; - data_1_13 : out std_logic; - data_1_12 : out std_logic; - data_1_9 : out std_logic; - data_1_8 : out std_logic; - data_1_5 : out std_logic; - data_1_4 : out std_logic; - data_1_3 : out std_logic; - data_1_2 : out std_logic; - data_1_1 : out std_logic; - data_1_0 : out std_logic; - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - size_1 : out std_logic_vector(1 downto 0); - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - dci_m_94 : out std_logic; - dci_m_93 : out std_logic; - dci_m_91 : out std_logic; - dci_m_90 : out std_logic; - dci_m_89 : out std_logic; - dci_m_88 : out std_logic; - faddr_RNI7879K : out std_logic_vector(0 to 0); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 downto 24); - ctx : out std_logic_vector(7 downto 0); - hrdata_0_d0 : in std_logic; - hrdata_24 : in std_logic; - hrdata_26 : in std_logic; - hrdata_25 : in std_logic; - hrdata_23 : in std_logic; - hrdata_1 : in std_logic; - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - size_0_0 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_0 : in std_logic; - dco_i_2 : out std_logic_vector(132 to 132); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - newtag_1_0_9 : out std_logic; - newtag_1_0_8 : out std_logic; - newtag_1_0_7 : out std_logic; - newtag_1_0_6 : out std_logic; - edata2_0_iv : in std_logic_vector(23 downto 0); - asi_0_0 : out std_logic; - dataout_1 : in std_logic_vector(11 downto 10); - size_1_d0 : in std_logic; - bo_d : in std_logic_vector(2 to 2); - rdatav_0_1_1_iv_7 : out std_logic_vector(6 to 6); - rdatav_0_1_0_iv_0_2_0 : out std_logic; - rdatav_0_1_0_iv_7_2 : out std_logic; - un1_m0_2_0 : in std_logic_vector(35 to 35); - ics : out std_logic_vector(1 downto 0); - maddress_0_2 : in std_logic; - maddress_0_0 : in std_logic; - asi : in std_logic_vector(4 downto 0); - data : out std_logic_vector(31 downto 0); - LVL_RNIT69H911 : in std_logic_vector(0 to 0); - data_1_3_i_a3_6_2 : in std_logic; - data_1_3_i_a3_6_4 : in std_logic; - data_1_3_i_a3_6_0 : in std_logic; - data_1_3_i_a3_6_1 : in std_logic; - data_RNIKU1T4 : in std_logic_vector(16 to 16); - un1_m0_2_73 : in std_logic; - un1_m0_2_2 : in std_logic; - un1_m0_2_4 : in std_logic; - un1_m0_2_10 : in std_logic; - un1_m0_2_9 : in std_logic; - un1_m0_2_40 : in std_logic; - un1_m0_2_5 : in std_logic; - un1_m0_2_1 : in std_logic; - un1_m0_2_7 : in std_logic; - un1_m0_2_68 : in std_logic; - un1_m0_2_38 : in std_logic; - un1_m0_2_42 : in std_logic; - un1_m0_2_59 : in std_logic; - un1_m0_2_58 : in std_logic; - un1_m0_2_67 : in std_logic; - un1_m0_2_43 : in std_logic; - un1_m0_2_65 : in std_logic; - un1_m0_2_77 : out std_logic; - un1_m0_2_34 : in std_logic; - un1_m0_2_78 : out std_logic; - un1_m0_2_75 : out std_logic; - un1_m0_2_6 : in std_logic; - un1_m0_2_29 : in std_logic; - un1_m0_2_19 : in std_logic; - un1_m0_2_23 : in std_logic; - un1_m0_2_60 : in std_logic; - un1_m0_2_79 : out std_logic; - un1_m0_2_80 : out std_logic; - un1_m0_2_81 : out std_logic; - un1_m0_2_84 : out std_logic; - un1_m0_2_83 : out std_logic; - un1_m0_2_86 : out std_logic; - un1_m0_2_76 : out std_logic; - un1_m0_2_15 : in std_logic; - un1_m0_2_11 : in std_logic; - un1_m0_2_18 : in std_logic; - un1_m0_2_85 : out std_logic; - un1_m0_2_54 : in std_logic; - un1_m0_2_71 : in std_logic; - un1_m0_2_55 : in std_logic; - un1_m0_2_70 : in std_logic; - un1_m0_2_61 : in std_logic; - un1_m0_2_69 : in std_logic; - un1_m0_2_37 : in std_logic; - un1_m0_2_66 : in std_logic; - un1_m0_2_56 : in std_logic; - un1_m0_2_64 : in std_logic; - un1_m0_2_62 : in std_logic; - un1_m0_2_57 : in std_logic; - un1_m0_2_41 : in std_logic; - un1_m0_2_94 : in std_logic; - un1_m0_2_91 : in std_logic; - un1_m0_2_106 : in std_logic; - un1_m0_2_96 : in std_logic; - un1_m0_2_92 : in std_logic; - un1_m0_2_95 : in std_logic; - un1_m0_2_97 : in std_logic; - un1_m0_2_93 : in std_logic; - un1_m0_2_98 : in std_logic; - un1_m0_2_33 : in std_logic; - un1_m0_2_72 : in std_logic; - un1_m0_2_39 : in std_logic; - un1_m0_2_63 : in std_logic; - un1_m0_2_44 : in std_logic; - un1_m0_2_35 : in std_logic; - un1_m0_2_36 : in std_logic; - un1_m0_2_0_d0 : in std_logic; - un1_m0_2_3 : in std_logic; - un1_m0_2_12 : in std_logic; - un1_m0_2_82 : out std_logic; - un1_m0_2_8 : in std_logic; - un1_m0_2_31 : in std_logic; - un1_m0_2_108 : in std_logic; - eaddress_7 : in std_logic; - eaddress_3 : in std_logic; - eaddress_0 : in std_logic; - eaddress_8 : in std_logic; - eaddress_1 : in std_logic; - eaddress_4 : in std_logic; - eaddress_12 : in std_logic; - eaddress_16 : in std_logic; - eaddress_24 : in std_logic; - eaddress_2 : in std_logic; - eaddress_20 : in std_logic; - eaddress_5 : in std_logic; - eaddress_15 : in std_logic; - eaddress_27 : in std_logic; - eaddress_17 : in std_logic; - eaddress_9 : in std_logic; - eaddress_19 : in std_logic; - eaddress_23 : in std_logic; - eaddress_25 : in std_logic; - eaddress_10 : in std_logic; - eaddress_6 : in std_logic; - eaddress_18 : in std_logic; - eaddress_28 : in std_logic; - eaddress_13 : in std_logic; - eaddress_21 : in std_logic; - eaddress_22 : in std_logic; - eaddress_29 : in std_logic; - rdatav_0_1_0_iv_5_18 : out std_logic; - rdatav_0_1_0_iv_5_14 : out std_logic; - rdatav_0_1_0_iv_5_15 : out std_logic; - rdatav_0_1_0_iv_5_20 : out std_logic; - rdatav_0_1_0_iv_4_23 : out std_logic; - rdatav_0_1_0_iv_4_9 : out std_logic; - rdatav_0_1_0_iv_4_29 : out std_logic; - rdatav_0_1_0_iv_4_31 : out std_logic; - mcdo_m_0_8 : out std_logic; - mcdo_m_0_5 : out std_logic; - mcdo_m_0_18 : out std_logic; - mcdo_m_0_21 : out std_logic; - mcdo_m_0_22 : out std_logic; - mcdo_m_0_17 : out std_logic; - mcdo_m_0_1 : out std_logic; - mcdo_m_0_28 : out std_logic; - mcdo_m_0_23 : out std_logic; - mcdo_m_0_30 : out std_logic; - data_0_23 : out std_logic; - data_0_22 : out std_logic; - data_0_19 : out std_logic; - data_0_18 : out std_logic; - data_0_7 : out std_logic; - data_0_15 : out std_logic; - data_0_12 : out std_logic; - data_0_0 : out std_logic; - data_0_26 : out std_logic; - data_0_4 : out std_logic; - data_0_21 : out std_logic; - data_0_11 : out std_logic; - data_0_8 : out std_logic; - data_0_28 : out std_logic; - data_0_17 : out std_logic; - data_0_16 : out std_logic; - data_0_25 : out std_logic; - data_0_14 : out std_logic; - data_0_20 : out std_logic; - data_0_27 : out std_logic; - data_0_30 : out std_logic; - data_0_13 : out std_logic; - data_0_29 : out std_logic; - data_0_24 : out std_logic; - data_0_31 : out std_logic; - dataout : in std_logic_vector(35 downto 0); - ctxp_13 : out std_logic; - ctxp_16 : out std_logic; - ctxp_7 : out std_logic; - ctxp_10 : out std_logic; - ctxp_3 : out std_logic; - ctxp_8 : out std_logic; - ctxp_19 : out std_logic; - ctxp_17 : out std_logic; - ctxp_15 : out std_logic; - ctxp_14 : out std_logic; - ctxp_20 : out std_logic; - ctxp_18 : out std_logic; - ctxp_6 : out std_logic; - ctxp_21 : out std_logic; - ctxp_11 : out std_logic; - ctxp_4 : out std_logic; - ctxp_25 : out std_logic; - ctxp_0 : out std_logic; - ctxp_22 : out std_logic; - ctxp_23 : out std_logic; - ctxp_24 : out std_logic; - ctxp_5 : out std_logic; - ctxp_12 : out std_logic; - ctxp_9 : out std_logic; - ctxp_1 : out std_logic; - ctxp_2 : out std_logic; - diagdata_6 : in std_logic; - diagdata_7 : in std_logic; - diagdata_1 : in std_logic; - diagdata_3 : in std_logic; - diagdata_5 : in std_logic; - diagdata_29 : in std_logic; - diagdata_22 : in std_logic; - diagdata_27 : in std_logic; - diagdata_20 : in std_logic; - diagdata_8 : in std_logic; - diagdata_25 : in std_logic; - diagdata_18 : in std_logic; - diagdata_31 : in std_logic; - diagdata_17 : in std_logic; - diagdata_24 : in std_logic; - diagdata_23 : in std_logic; - diagdata_21 : in std_logic; - diagdata_16 : in std_logic; - diagdata_12 : in std_logic; - diagdata_9 : in std_logic; - diagdata_26 : in std_logic; - diagdata_0 : in std_logic; - diagdata_19 : in std_logic; - diagdata_14 : in std_logic; - diagdata_15 : in std_logic; - diagdata_2 : in std_logic; - diagdata_13 : in std_logic; - diagdata_30 : in std_logic; - diagdata_4 : in std_logic; - diagdata_28 : in std_logic; - address : out std_logic_vector(31 downto 0); - addr_30 : out std_logic; - addr_11 : out std_logic; - addr_6 : out std_logic; - addr_4 : out std_logic; - addr_7 : out std_logic; - addr_5 : out std_logic; - addr_3 : out std_logic; - addr_8 : out std_logic; - addr_10 : out std_logic; - addr_9 : out std_logic; - addr_2 : out std_logic; - dataout_0 : in std_logic_vector(31 downto 0); - maddress : in std_logic_vector(31 downto 0); - un1_p0_2_0 : out std_logic_vector(498 to 498); - ctx_0 : out std_logic_vector(7 downto 0); - size_1z : out std_logic; - enable : out std_logic; - N_10 : out std_logic; - write : in std_logic; - eenaddr : in std_logic; - msu : in std_logic; - su : out std_logic; - read_3 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - N_415 : in std_logic; - N_351 : in std_logic; - flush_RNIGBB873 : out std_logic; - N_192 : in std_logic; - N_190_0 : in std_logic; - diagrdy : in std_logic; - burst_0 : out std_logic; - N_264_0 : in std_logic; - N_425 : out std_logic; - trans_op_0 : out std_logic; - flush_op_i_0 : out std_logic; - trans_op : out std_logic; - un2_m_tlb_type : in std_logic; - tlbdis : out std_logic; - read_2 : out std_logic; - grant : in std_logic; - N_317_0 : in std_logic; - N_2886 : in std_logic; - N_2887 : in std_logic; - N_270 : out std_logic; - N_269 : out std_logic; - N_267 : out std_logic; - N_353 : in std_logic; - N_259 : out std_logic; - N_258 : out std_logic; - N_236_0 : in std_logic; - N_417 : in std_logic; - N_144 : out std_logic; - N_3846 : out std_logic; - e : out std_logic; - N_421_0 : in std_logic; - N_3305 : out std_logic; - nf : out std_logic; - N_262_0 : in std_logic; - un54_fault_pro_m : in std_logic; - M_m : in std_logic; - r_N_6 : in std_logic; - vaddr_1_sqmuxa_0_a2_2 : out std_logic; - fault_pro : in std_logic; - stpend_RNI6P41NG3 : out std_logic; - read_1 : in std_logic; - read_RNIQH64D1 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIRO4K31 : out std_logic; - N_3389_i_0 : out std_logic; - read_RNI0IQ7R : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNICKHE91 : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - un59_nbo : in std_logic; - lock_m : out std_logic; - N_2699_i_0 : in std_logic; - mexc_1 : out std_logic; - N_3239_i_0 : out std_logic; - N_2701 : in std_logic; - N_2703_i_0 : in std_logic; - N_2714 : in std_logic; - N_3227_i_0 : out std_logic; - N_3387_i_0 : out std_logic; - N_26 : out std_logic; - read_RNIEKS231 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIC9O9B1 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNICAQK41 : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIEEGDD1 : out std_logic; - N_12_i_0 : out std_logic; - N_16_i_0 : out std_logic; - N_696 : in std_logic; - N_695 : in std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - N_2702_i_0 : in std_logic; - N_2717 : in std_logic; - N_2720 : in std_logic; - N_694 : in std_logic; - N_2711_i_0 : in std_logic; - fsread_i_0 : out std_logic; - N_24 : out std_logic; - N_329 : out std_logic; - N_330 : out std_logic; - N_78_0 : in std_logic; - ba : in std_logic; - hcache : in std_logic; - cache : out std_logic; - cdwrite_0_sqmuxa_i_0_0 : in std_logic; - lock_0 : out std_logic; - un17_casaen_0_0 : in std_logic; - mexc : in std_logic; - me_nullify2_1_2 : in std_logic; - nullify2_0_sqmuxa : in std_logic; - flush : in std_logic; - hold_0 : in std_logic; - fault_pro67 : in std_logic; - req : out std_logic; - intack : in std_logic; - N_523 : out std_logic; - fault_pri : in std_logic; - iflush_1_0_a2_0 : out std_logic; - N_419 : in std_logic; - N_2709_i_0 : in std_logic; - nullify : in std_logic; - flush_i_0 : in std_logic; - N_293 : in std_logic; - read_0 : in std_logic; - rst : in std_logic; - burst : out std_logic; - accexc_6 : in std_logic; - un1_addout_12 : in std_logic; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : out std_logic; - G_80_0 : in std_logic; - lock : in std_logic; - ready : in std_logic; - mmudci_trans_op_1_sqmuxa_1 : out std_logic; - hold : out std_logic; - enaddr : in std_logic; - N_425_0 : out std_logic; - N_121 : out std_logic; - N_3254_0 : out std_logic; - e_0 : out std_logic; - lclk_c : in std_logic - ); - -end mmu_dcache; - -architecture DEF_ARCH of mmu_dcache is - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \ctx_RNIB8BR[0]\, \ctx_0_0_RNIQIPQ[1]\, - \ctx_RNIFGBR[2]\, \ctx_RNIAM7T[3]\, \ctx_0_0_RNI7TTO[4]\, - \ctx_0_0_RNI91UO[5]\, \ctx_RNIN0CR[6]\, - \ctx_0_0_RNID9UO[7]\, N_2710_i, e_0_sqmuxa_RNIQKNL, - \dstate_2[7]\, \dstate_nss[1]\, \dstate_1[7]\, - \dstate_0[7]\, \dstate_0[2]\, \dstate_nss[6]\, - paddress_1_sqmuxa_0, N_487, N_506, addr_1_sqmuxa_0, - dwrite_1_sqmuxa, rdatasel_1_sqmuxa_1_0, N_3253_i, N_526, - mexc_0_sqmuxa_0_0, data2_0_sqmuxa_1, holdn_2_sqmuxa, - mexc_0_sqmuxa_0, addr_1_sqmuxa_2_0, un18_m_en, - \dstate_i_0[8]\, N_328, addr_2_sqmuxa_0, un47_m_en, - N_3331, data1_0_sqmuxa_0, stpend_0_sqmuxa, - \dstate_RNI5GFM4[5]\, rdatav_0_6_sqmuxa_0, - rdatav_0_6_sqmuxa_3, N_2165_0, burst_0_sqmuxa, - rdatav_012_0, nomds, \dstate_i[8]\, \dstate_i_2[8]\, - \dstate_nss_i_0[0]\, \dstate_i_1[8]\, - tdiagwrite_1_0_0_o2_1, N_3749, N_3748, N_484_0, - un1_m_en_2, un1_m_en_1, \e_0\, req_0_sqmuxa_1_0, N_566, - dstate_14, N_3331_0, N_485, N_486_0, vaddr_1_sqmuxa_0, - vaddr_1_sqmuxa_0_0, ctxp_1_sqmuxa_0_0, e_0_sqmuxa_2, - ctxp_1_sqmuxa_0, N_3344_i_0_0, N_3321, edata_0_sqmuxa_i_0, - edata_0_sqmuxa_1, N_3443_i, \dstate[1]\, N_20, \faddr[1]\, - \faddr[0]\, N_12, \faddr[3]\, \DWACT_FINC_E[0]\, N_500_i, - N_499, un6_validrawv, N_3041_11, N_3514, N_139_i_i, - un1_dci_2_i, un1_dci_5_i, un1_dci_13_i, N_559, N_3747, - N_502, N_501, \dcs[0]\, addr_1_sqmuxa_1, addr_0_sqmuxa_2, - N_3715, N_514, \dcramo_m_i[255]\, N_2088, \edata_m_i[31]\, - ddatainv_0_6_sqmuxa, \edata[31]\, \dcramo_m_0[252]\, - \ico_m[162]\, \ctxp_m[2]\, \dcramo_m_0[228]\, - \ico_m[138]\, N_3723, \dcramo_m_0[254]\, \ico_m[164]\, - N_264, \dcramo_m_i[242]\, \xaddress_RNI1CIE2_0[0]\, - \edata_m_i[18]\, \edata[18]\, \dcramo_m_i[251]\, - \edata_m_i[27]\, \edata[27]\, burst_2_sqmuxa_m3_e, - burst_2_sqmuxa_m3_e_RNO, burst_16_m, burst_16_m_0, - \dstate_RNO_8[4]\, dstate_ns_0_2065_0, - twrite_14_iv_0_a2_a0, un1_addout_13_i, - twrite_14_iv_0_a2_a0_4, burst_2_sqmuxa_m8_0_a4_0, - burst_2_sqmuxa_m8_0_a4_0_2, N_1_28_i, - twrite_14_iv_0_o2_a0_4, N_3654, - \vmaskraw_1_i_o2_i_a2_0_0[1]\, N_3661, - \vmaskraw_1_i_o2_i_a3_0_a2_0_0[3]\, \addr_1[10]\, - \addr_1_1_iv_0_3[10]\, e_0_sqmuxa, e_0_sqmuxa_0, - ctxp_1_sqmuxa, mmctrl1wr, \addr[3]\, \addr[8]\, - \ddatainv_0_1_0_iv_0[18]\, \ddatainv_0_1_0_iv_0[27]\, - \ddatainv_0_1_0_iv_0[31]\, un1_dci_NE_3, un1_dci_NE_1, - \rdatav_0_1_0_iv_7[4]\, \rdatav_0_1_0_iv_6[4]\, - \rdatav_0_1_0_iv_5[4]\, \rdatav_0_1_0_iv_4[4]\, - \ctx_m[4]\, \rdatav_0_1_0_iv_3[30]\, - \rdatav_0_1_1_iv_5[28]\, N_421, \addr[2]\, - \addr_1_1_iv_0_2[10]\, \addr_1_1_iv_0_1[10]\, - twrite_14_iv_0_o2_a0_3, twrite_14_iv_0_a2_a0_3, - \addr_1_1_iv_0_1[31]\, N_3652, \addr_1_1_iv_0_0[31]\, - burst_1_sqmuxa_1, burst_1_sqmuxa_0, data2_1_sqmuxa, - N_3151, N_3499, N_16887_tz_tz, burst_2_sqmuxa_m8_0_a4_0_1, - \addr_1_1_iv_0_2[29]\, \addr_1_1_iv_0_1[29]\, N_261, - \addr_1_1_iv_0_0[29]\, \addr_1_1_iv_0_2[31]\, - \dstate_ns_i_a4_i_9[0]\, N_611, \dstate_ns_i_a4_i_8[0]\, - \dstate_ns_i_a4_i_6[0]\, N_3680_i, N_3679, - \dstate_ns_i_a4_i_4[0]\, N_3683_i, N_3815, N_3682, - \dstate_ns_i_a4_i_2[0]\, \dcs_RNIBN6EB[0]\, - \dstate_ns_i_a4_i_0[0]\, N_3685, N_3677, - \dstate_ns_i_a4_i_a2_7_0[0]\, N_519, holdn_0_0, - stpend_1_0, holdn_1_5, \dstate_ns_i_a4_i_a2_0[0]\, N_507, - N_3745, req_1_2, req_0_sqmuxa_3_1, N_547, req_1_1, - N_2471_i, burst_1_m8_i_0, burst_0_sqmuxa_5, holdn_0_5, - holdn_0_3, holdn_1_sqmuxa_3, holdn_1_sqmuxa, holdn_0_1, - N_3750, dstate_0_sqmuxa, dstate_tr22_2, N_3545, N_3089_7, - dstate_tr22_1, \dstate_RNO_5[1]\, N_3086_i, - dstate_tr22_15_N_10_i, \dstate_ns_0_3[4]\, - dstate_tr16_13_0_0_a2_0_5, \dstate_ns_0_2[4]\, - \dstate_RNO_6[4]\, \dstate_ns_0_0[4]\, dstate_ns_0_2064_1, - N_3511, N_3181, burst_1_m8_i_a5_0, burst_2_sqmuxa_m8_0_0, - burst_1_iv_2, holdn_1, holdn_3_sqmuxa_0_0_2, N_3611, - holdn_0, N_3604, flush_0_0, I_31_1, flush_0_sqmuxa_0, - dstate_tr16_10_0_i_2, dstate_tr16_10_0_i_0, N_395, - N_581_i, burst_1_m8_i_o5_0, req_2_sqmuxa_1_0, - \addr_1_1_iv_2[26]\, \dci_m[34]\, \addr_1_1_iv_0[26]\, - \addr_m[26]\, \paddress[26]\, \mmudco_m[28]\, - \addr_1_1_iv_2[30]\, \dci_m[38]\, \addr_1_1_iv_0[30]\, - \addr_m[30]\, \paddress_m[30]\, \addr_1_1_iv_2[25]\, - \dci_m[33]\, \addr_1_1_iv_0[25]\, \addr_m[25]\, - \paddress[25]\, \mmudco_m[27]\, \addr_1_1_iv_0_2[28]\, - N_3888, \addr_1_1_iv_0_0[28]\, N_214, N_3839, N_213, - \addr_1_1_iv_0_2[27]\, N_250, \addr_1_1_iv_0_0[27]\, - N_253, N_249, N_546, N_262, N_544, N_3716, - \addr_1_1_iv_0_2[24]\, N_3634, \addr_1_1_iv_0_0[24]\, - N_3739, N_545, N_3740, holdns_iv_0_1, N_3615, - holdns_iv_0_0, holdns_iv_0_a2_2_3, - \dstate_i_RNIF4S5B92[8]\, N_3614, \addr_1_1_iv_2[15]\, - \dci_m[23]\, \addr_1_1_iv_0[15]\, \addr_m[15]\, N_673, - \mmudco_m[17]\, \addr_1_1_iv_0_2[12]\, N_277, - \addr_1_1_iv_0_0[12]\, N_280, N_676, N_278, - faddr_1_sqmuxa_0, \un1_p0_2_0[498]\, holdn_3_sqmuxa_0_0_0, - e_0_0_RNI8APPC92, N_510, \addr_1_1_iv_2[16]\, \dci_m[24]\, - \addr_1_1_iv_0[16]\, \addr_m[16]\, \paddress_m[16]\, - \addr_1_1_iv_0_2[14]\, N_3636, \addr_1_1_iv_0_0[14]\, - N_3728, N_554, N_3729, \addr_1_1_iv_0_2[17]\, N_3640, - \addr_1_1_iv_0_0[17]\, N_3721, N_553, N_3722, - \addr_1_1_iv_0_2[13]\, N_272, \addr_1_1_iv_0_0[13]\, - N_275, N_677, N_273, ready_0_sqmuxa_0_2, - ready_0_sqmuxa_0_a2_1_0, N_3697, ready_0_sqmuxa_0_0, - N_511, ready_0_sqmuxa_0_a2_1, N_572, cctrlwr13, - mmudci_diag_op_1_0_a2_0, N_3790, - dstate_tr22_15_m8_i_a5_0_0, N_3586, N_595, - \mmudco_m_0[102]\, \mmudco_m_0[106]\, \mmudco_m_0[101]\, - \addr_1_1_iv_0_a3_2_0[29]\, \addr_1_1_iv_0_a3_2_0[27]\, - \addr_1_1_iv_0_a3_1_0[28]\, \dstate_ns_0_0_1[1]\, - \dstate_ns_0_0_a2_0[1]\, N_3781, \dstate_ns_0_0_0[1]\, - N_585, N_3707, N_3505_i, dstate_tr16_13_0_0_a2_0_3, - dstate_tr16_13_0_0_a2_0_1, N_114_i_i_0, - dstate_tr16_13_0_0_a2_0_0, \mmudco_m_0[91]\, - \addr_1_1_iv_0_a3_2_0[12]\, dstate_tr22_15_a2_2_m8_i_0_0, - dstate_tr22_15_a2_2_m8_i_0_tz, N_3576, N_3583, - burst_1_sqmuxa_3, data2_0_sqmuxa, burst_0_sqmuxa_3, - holdns_iv_0_a2_1_0, e_RNIKN3D, N_489, N_481, - holdns_iv_0_a2_2_1, holdn_3_sqmuxa_0_0_a2_2_0, N_590, - \dstate_ns_0_0_o2_0[1]\, N_3746, ready_RNO_7, - mexc_1_m_0_1, N_176, N_175, N_174, \dstate_ns_0_6[3]\, - \dstate_ns_0_7_i[3]\, \dstate_ns_0_1[3]\, - \dstate_RNO_4[5]\, \dstate_ns_0_5[3]\, N_3028, - \dstate_ns_0_2_0[3]\, \dstate_ns_0_3[3]\, N_2996_8, - \dstate_ns_0_4_tz[3]\, N_29, N_3180_i, N_3035, - dstate_tr22_15_a2_2_m8_i_a5_1_1, - dstate_tr22_15_a2_2_m8_i_a5_1_0, dstate_tr22_15_a2_14_1_0, - N_459, \addr_1_1_iv_0_2[19]\, N_221, - \addr_1_1_iv_0_0[19]\, N_224, N_3837, N_3890, - \addr_1_1_iv_0_2[21]\, N_3638, \addr_1_1_iv_0_0[21]\, - N_3718, N_3717, \addr_1_1_iv_0_2[20]\, N_3860, - \addr_1_1_iv_0_0[20]\, N_3863, N_3859, N_3862, - \addr_1_1_iv_0_2[22]\, N_3871, \addr_1_1_iv_0_0[22]\, - N_185, N_3870, N_3873, \addr_1_1_iv_0_2[18]\, N_187, - \addr_1_1_iv_0_0[18]\, N_190, N_3841, N_189, - \addr_1_1_iv_0_2[23]\, N_216, \addr_1_1_iv_0_0[23]\, - N_3889, N_3838, N_218, \req_0_sqmuxa[0]\, - mexc_1_m_0_2000_0, mexc_1_m_0_2000_tz_1, - mexc_1_m_0_a2_1_0, mexc_0_sqmuxa_1, cctrlwr11_0, - vaddr_1_sqmuxa_0_a2_a0_0, dstate_tr22_15_a2_1_1_0, - \ics_0_i_0[1]\, un19_eholdn_3, - \mmudci_fsread_1_sqmuxa_0_a2_0\, un30_m_en, N_527, N_3758, - N_3778, \dcs_0_i_0_a2_0[1]\, dfrz, \ics_0_i_0[0]\, - \N_523\, burst_1_iv_2_1, un116_m_en_m, burst_19_m, - dstate_tr16_13_0_0_a2_0, holdn_0_sqmuxa_1_m8_0_a2_5, - holdn_0_sqmuxa_1_m8_0_a2_3, holdn_0_sqmuxa_1_m8_0_a2_1, - cctrlwr19_2_0_a2_1_1, dcs_1_i_s_0_o2_0_RNIMMIH9, - holdn_0_sqmuxa_1_m8_0_a2_0, N_576, \ics_0_i_a4_1_0[1]\, - ifrz, burst_3_m_3, burst_3_m_1, burst_0_sqmuxa_2, - burst_2_sqmuxa_2, dstate_tr22_15_0_a2_1, - dstate_tr22_15_0_a2_0, N_666, dstate_tr20_2, - dstate_tr20_0, dstate_tr22_15_a2_3_1_0, d_m6_i_a3_1, - holdn_RNO_20, cctrlwr19_1_0, un1_eholdn_2, \un1_dci_5[0]\, - N_16886_tz_tz, flush_0_sqmuxa_0_o3_i_o2_5, - flush_0_sqmuxa_0_o3_i_o2_0, flush_0_sqmuxa_0_o3_i_o2_4, - flush_0_sqmuxa_0_o3_i_o2_2, cctrlwr, \dstate_ns_0_0_0[8]\, - \dstate_ns_0_0_a2_0_3[8]\, N_135, lock_1_iv_0_a2_1_0, - \addr_1_1_iv_2[1]\, \addr_1_1_iv_0[1]\, \addr_m[1]\, - \mmudco_m[3]\, \paddress[1]\, \mmudco_m[77]\, - \addr_1_0_iv_0_3[2]\, \addr_1_0_iv_0_1[2]\, N_315, N_314, - N_316, N_317, N_318, \addr_1_1_iv_0_2[3]\, - \addr_1_1_iv_0_0[3]\, N_295, N_293_0, - \dstate_RNIP22L4[7]\, N_675, N_294, \addr_1_1_iv_0_2[5]\, - \addr_1_1_iv_0_0[5]\, N_290, N_288, - \addr_1_1_iv_0_a3_0_0[5]\, N_289, \addr_1_1_iv_0_2[4]\, - \addr_1_1_iv_0_0[4]\, \addr_m[4]\, \mmudco_m[6]\, N_678, - \mmudco_m[80]\, \addr_1_1_iv_1[0]\, dstate_19, - \addr_1_1_iv_0[0]\, \paddress[0]\, \mmudco_m[76]\, - \addr_1_1_iv_0_2[6]\, \paddress[6]\, N_3792, N_3731, - \addr_1_1_iv_0_1[6]\, N_3733, N_3628, N_3732, - \addr_1_1_iv_0_3[7]\, N_3735, N_3734, - \addr_1_1_iv_0_1[7]\, \addr_1_1_iv_0_0[7]\, N_3737, - twrite_14_iv_0_o2_0_0, twrite_14_iv_0_o2_a1_3, - twrite_11_m, \addr_1_1_iv_2[9]\, \mmudco_m[11]\, - \addr_1_1_iv_0[9]\, \dci_m[17]\, \paddress[9]\, - \mmudco_m[85]\, \addr_1_1_iv_2[8]\, \mmudco_m[10]\, - \addr_1_1_iv_0[8]\, \dci_m[16]\, \paddress[8]\, - \mmudco_m[84]\, \addr_1_1_iv_0_1[11]\, - \addr_1_1_iv_0_0[11]\, \addr_1_1_iv_0_a3_0[11]\, N_284, - N_3726, N_3641, N_3642, \paddress[10]\, N_3725, - vaddr_1_sqmuxa_0_a2_5, vaddr_1_sqmuxa_0_a2_3, - dcs_1_i_s_0_o2_0_RNIAN3E3, vaddr_1_sqmuxa_0_a2_1, - stpend_RNI07PA2, vaddr_1_sqmuxa_0_a2_0, - twrite_14_iv_0_o2_a0_1, setrepl_0_sqmuxa_1_m_i_5_4, - twrite_14_iv_0_o2_a1_0, un1_dci_12_0, - twrite_14_iv_0_a2_a0_1, flush_i, mexc_0_sqmuxa, - twrite_14_iv_0_o2_a1_2, twrite_14_iv_0_o2_a1_1, - twrite_14_iv_0_a2_a1_2, twrite_14_iv_0_a2_a1_0, - \dstate_ns_i_a4_i_a2_3_2[0]\, - \dstate_ns_i_a4_i_a2_3_0[0]\, N_3788, - \dstate_ns_i_a4_i_a2_16_0[0]\, N_496, - \vaddr_1_sqmuxa_0_a2_4_m1_e_24\, - vaddr_1_sqmuxa_0_a2_4_m1_e_21, - vaddr_1_sqmuxa_0_a2_4_m1_e_20, - vaddr_1_sqmuxa_0_a2_4_m1_e_22, - vaddr_1_sqmuxa_0_a2_4_m1_e_19, - vaddr_1_sqmuxa_0_a2_4_m1_e_13, - vaddr_1_sqmuxa_0_a2_4_m1_e_12, - vaddr_1_sqmuxa_0_a2_4_m1_e_11, - vaddr_1_sqmuxa_0_a2_4_m1_e_16, - vaddr_1_sqmuxa_0_a2_4_m1_e_10, - vaddr_1_sqmuxa_0_a2_4_m1_e_9, - vaddr_1_sqmuxa_0_a2_4_m1_e_3, - vaddr_1_sqmuxa_0_a2_4_m1_e_5, - vaddr_1_sqmuxa_0_a2_4_m1_e_2, lock_1_iv_0_a2_0, \req\, - \dstate_ns_i_a4_i_o2_11_2[0]\, - \dstate_ns_i_a4_i_o2_11_0[0]\, N_72_i, ready_0, - \dstate[5]\, stpend, \paddress[11]\, \paddress[5]\, - \addr[5]\, burst_19_m_0, \dstate_ns_i_a4_i_a2_6_0[0]\, - N_522, \rdatav_0_1_1_iv_i_a2_6[3]\, - \rdatav_0_1_1_iv_i_a2_5[3]\, \rdatav_0_1_1_iv_i_a2_2[3]\, - \rdatav_0_1_1_iv_i_a2_1[3]\, \rdatav_0_1_1_iv_i_a2_4[3]\, - \ctx_0[3]\, miscdata_2_sqmuxa, \rdatav_0_1_6[3]\, - \dcs[1]\, rdatav_0_0_sqmuxa, N_3399, N_3400, N_3403, - N_3401, dstate_19_4, addr_3_sqmuxa, dstate_19_3, - dstate_19_1, \dstate[0]\, \dstate[3]\, - \rdatav_0_1_0_iv_3[13]\, \dcramo_m_0[237]\, - \rdatav_0_1_0_iv_2[13]\, \mmudco_m[56]\, - \rdatav_0_1_0_iv_0[13]\, \ctxp_m[11]\, \data2_m[13]\, - \rdatav_0_1_1_iv_3[11]\, \rdatav_0_1_1_iv_2[11]\, - \ico_m_0[145]\, \rdatav_0_1_1_iv_1[11]\, - rdatav_0_1_sqmuxa, \data2_m[11]\, rdatav_0_2_sqmuxa, - \dstate_ns_i_a4_i_o2_9_2[0]\, - \dstate_ns_i_a4_i_o2_9_0[0]\, N_3811, - \dstate_ns_i_a4_i_a2_15_0[0]\, \ctxp_m[0]\, - \rdatav_0_1_0_iv_4[2]\, \rdatav_0_1_0_iv_6[2]\, - \dcramo_m_0[226]\, \ctx_0[2]\, \rdatav_0_1_0_iv_3[2]\, - \rdatav_0_1_0_iv_1[2]\, \rdatav_0_1_0_iv_2[2]\, - \mmudco_m[38]\, \dcramo_m[410]\, \data2_m[2]\, - \dcramo_m[98]\, mexc_1_m_0_a2_3_0, mexc_0, - mexc_1_m_0_a2_4_0, N_84, \rdatav_0_1_0_iv_i_a4_6[1]\, - nf_m, \rdatav_0_1_0_iv_i_a4_4[1]\, \dcramo_m_0[225]\, - N_3232, \rdatav_0_1_0_iv_i_a4_1[1]\, - \rdatav_0_1_0_iv_i_a4_3[1]\, miscdata_3_sqmuxa, N_3231, - rdatasel_3_sqmuxa, \rdatav_0_1_0_iv_i_a4_0[1]\, N_89, - N_3233, \rdatav_0_1_0_iv_0_5[15]\, \dcramo_m_0[239]\, - \rdatav_0_1_0_iv_0_4[15]\, tlbdis_m, - \rdatav_0_1_0_iv_0_2[15]\, \ctxp_m[13]\, - \rdatav_0_1_0_iv_0_0[15]\, N_205, \mmudco_m[58]\, - \data2[15]\, N_204, \rdatav_0_1_0_iv_5[14]\, - \dcramo_m_0[238]\, \rdatav_0_1_0_iv_4[14]\, - \rdatav_0_1_0_iv_3[14]\, \mmudco_m[57]\, - \rdatav_0_1_0_iv_1[14]\, miscdata_0_sqmuxa, flush_m, - \rdatav_0_1_0_iv_0[14]\, \data2[14]\, \dcramo_m[110]\, - \ctxp_m[17]\, \rdatav_0_1_0_iv_2[19]\, - \rdatav_0_1_0_iv_4[19]\, \dcramo_m_0[243]\, - \mmudco_m[62]\, \rdatav_0_1_0_iv_0[19]\, \data2[19]\, - \dcramo_m[115]\, \rdatav_0_1_1_iv_0_6[7]\, N_3312, - \rdatav_0_1_1_iv_0_5[7]\, \rdatav_0_1_1_iv_0_4[7]\, - \rdatav_0_1_1_iv_0_2[7]\, \mmudco_m[41]\, - \rdatav_0_1_1_iv_0_0[7]\, N_3302, N_3311, N_3314, - \dcramo_m[415]\, \rdatav_0_1_0_iv_7[0]\, - \rdatav_0_1_0_iv_6[0]\, e_m, \rdatav_0_1_0_iv_4[0]\, - \dcramo_m_0[224]\, \rdatav_0_1_0_iv_2[0]\, - \rdatav_0_1_0_iv_1[0]\, \ctx_m[0]\, \ics_m[0]\, - \dcramo_m[408]\, \data2_m[0]\, \dcramo_m[96]\, - \rdatav_0_1_0_iv_3[26]\, \dcramo_m_0[250]\, - \rdatav_0_1_0_iv_2[26]\, \rdatav_0_1_0_iv_1[26]\, - \dcramo_m[122]\, \data2_m[26]\, \mmudco_m[69]\, - \ctxp_m[7]\, \rdatav_0_1_0_iv_1[9]\, - \rdatav_0_1_0_iv_3[9]\, \dcramo_m_0[233]\, - \rdatav_0_1_0_iv_0[9]\, \data2_m[9]\, \dcramo_m_0[105]\, - \rdatav_0_1_0_iv_0_3[12]\, N_160, - \rdatav_0_1_0_iv_0_2[12]\, \mmudco_m[55]\, - \rdatav_0_1_0_iv_0_0[12]\, \ctxp_m[10]\, \data2_m[12]\, - N_159, \rdatav_0_1_0_iv_0_1[10]\, N_3306, N_3304, N_167, - \rdatav_0_1_1_iv_5[16]\, \dcramo_m_0[240]\, - \rdatav_0_1_1_iv_4[16]\, \rdatav_0_1_1_iv_2[16]\, - \mmudco_m[59]\, \ctxp_m[14]\, \rdatav_0_1_1_iv_0[16]\, - burst_m, \data2_m[16]\, \dcramo_m[112]\, - \rdatav_0_1_1_iv_5[21]\, \dcramo_m_0[245]\, - \rdatav_0_1_1_iv_4[21]\, \rdatav_0_1_1_iv_2[21]\, - \rdatav_0_1_1_iv_1[21]\, \ctxp_m[19]\, miscdata_4_sqmuxa, - \dcramo_m[117]\, \data2_m[21]\, \ctxp_m[21]\, - \rdatav_0_1_0_iv_1[23]\, \rdatav_0_1_0_iv_3[23]\, - \dcramo_m_0[247]\, \dcramo_m[119]\, \data2_m[23]\, - \mmudco_m[66]\, \ctxp_m[4]\, \rdatav_0_1_1_iv_4[6]\, - \rdatav_0_1_1_iv_6[6]\, \ico_m[140]\, - \rdatav_0_1_1_iv_1[6]\, \mmudco_m[42]\, - \rdatav_0_1_1_iv_3[6]\, \ctx_m[6]\, \dcramo_m[414]\, - \data2_m[6]\, \dcramo_m[102]\, \dcramo_m[100]\, - \rdatav_0_1_0_iv_1[4]\, \rdatav_0_1_0_iv_3[4]\, ifrz_m, - \dcramo_m[412]\, \data2_m[4]\, \rdatav_0_1_0_iv_5[24]\, - \ctxp_m[22]\, \rdatav_0_1_0_iv_2[24]\, - \rdatav_0_1_0_iv_4[24]\, \dcramo_m_0[248]\, - \mmudco_m[67]\, \rdatav_0_1_0_iv_0[24]\, \data2_m[24]\, - \dcramo_m[120]\, \rdatav_0_1_0_iv_4[30]\, \ctxp_m[28]\, - \rdatav_0_1_0_iv_1[30]\, \rdatav_0_1_0_iv_0[30]\, - \data2_m[30]\, \rdatav_0_1_1_iv_5[17]\, \dcramo_m_0[241]\, - \rdatav_0_1_1_iv_4[17]\, \mmudco_m[60]\, - \rdatav_0_1_1_iv_2[17]\, \ctxp_m[15]\, - \rdatav_0_1_1_iv_0[17]\, \dcramo_m[113]\, \data2[17]\, - \rdatav_0_1_0_iv_4[31]\, \ctxp_m[29]\, - \rdatav_0_1_0_iv_1[31]\, \rdatav_0_1_0_iv_3[31]\, - \dstate[2]\, \dcramo_m_0[255]\, \dcramo_m[127]\, - \data2_m[31]\, \mmudco_m[74]\, - \rdatav_0_1_1_iv_i_a2_6[5]\, \rdatav_0_1_1_iv_i_a2_4[5]\, - \rdatav_0_1_1_iv_i_a2_3[5]\, N_3395, \ctx_0[5]\, N_3392, - N_3329, \rdatav_0_1_1_iv_i_a2_1[5]\, - \rdatav_0_1_1_iv_i_a2_0[5]\, N_3396, - \rdatav_0_1_1_iv_4[28]\, \mmudco_m[71]\, - \rdatav_0_1_1_iv_2[28]\, \ctxp_m[26]\, - \rdatav_0_1_1_iv_1[28]\, \data2_m[28]\, - twrite_14_iv_0_o4_0_o2_0, \dstate[4]\, N_58, \ctxp_m[16]\, - \rdatav_0_1_0_iv_2[18]\, \rdatav_0_1_0_iv_4[18]\, - \dcramo_m_0[242]\, \mmudco_m[61]\, - \rdatav_0_1_0_iv_0[18]\, \data2_m[18]\, \dcramo_m[114]\, - \rdatav_0_1_0_iv_3[25]\, \dcramo_m_0[249]\, - \rdatav_0_1_0_iv_2[25]\, \rdatav_0_1_0_iv_1[25]\, - \dcramo_m[121]\, \data2_m[25]\, \mmudco_m[68]\, - \rdatav_0_1_0_iv_3[8]\, \dcramo_m_0[232]\, - \rdatav_0_1_0_iv_2[8]\, \rdatav_0_1_0_iv_0[8]\, - \mmudco_m[44]\, \ctxp_m[6]\, \data2[8]\, - \rdatav_0_1_0_iv_4[20]\, \ctxp_m[18]\, - \rdatav_0_1_0_iv_1[20]\, \rdatav_0_1_0_iv_3[20]\, - \dcramo_m_0[244]\, \dcramo_m[116]\, \data2_m[20]\, - \mmudco_m[63]\, \rdatav_0_1_0_iv_3[27]\, - \dcramo_m_0[251]\, \rdatav_0_1_0_iv_2[27]\, - \mmudco_m[70]\, \rdatav_0_1_0_iv_0[27]\, \ctxp_m[25]\, - \data2_m[27]\, \ctxp_m[20]\, \rdatav_0_1_0_iv_2[22]\, - \rdatav_0_1_0_iv_4[22]\, \dcramo_m_0[246]\, - \mmudco_m[65]\, \rdatav_0_1_0_iv_0[22]\, \data2[22]\, - \dcramo_m[118]\, \dstate_ns_0_0_a2_0_1[8]\, - un121_m_en_i_s_0, hit, lock_m_0, \lock_0\, - \rdatav_0_1_0_iv_4[29]\, \ctxp_m[27]\, - \rdatav_0_1_0_iv_1[29]\, \rdatav_0_1_0_iv_3[29]\, - \dcramo_m_0[253]\, \dcramo_m[125]\, \data2_m[29]\, - \mmudco_m[72]\, setrepl_0_sqmuxa_1_m_i_5_2, - setrepl_0_sqmuxa_1_m_i_5_1, setrepl_0_sqmuxa_1_m_i_5_0, - un10_m_en, N_495, ready_0_sqmuxa_0_a2_0_a2_0, - cache_1_0_0_0, cache_1_0_a3_0_0, dstate_15_1, N_508, - cctrlwr19_2_0_2072_0, N_3779, N_494, dcs_1_i_s_0_0, N_512, - dstate_25_0_a2_0, \miscdata_4_sqmuxa_0_a2_1\, - \miscdata_4_sqmuxa_0_a2_0\, - \miscdata_2_sqmuxa_0_a4_0_a2_0_a3_0\, N_3569_2, - cache_1_0_a2_0_0, \vmask_0_5_1_0[4]\, - \vmask_0_5_1_a4_0_0[4]\, rdatav_0_6_sqmuxa_3_2, - rdatav_0_6_sqmuxa_3_0, rdatav_0_6_sqmuxa_3_1, N_206_1, - N_2042, \vmask_0_5_1_0[2]\, \vmask_0_5_1_a2_2_0[2]\, - \rdatav_0_1_0_iv_i_a2_2_0[1]\, \ctx_0[1]\, - \dstate_ns_0_7_tz_0[3]\, dstate_tr8_4_9_0_a2_0_a2_0_a2_0, - wbinit, hit_1_iv_0_a2_0_3, hit_1_iv_0_a2_0_2, un1_dci_NE, - hit_1_iv_0_a2_0_0, cctrlwr19_2_0_a2_1_1_0, - mexc_1_m_0_a2_0, mexc_1_m_0_a2_0_1, mexc_1_m_0_a2_5_0, - cctrlwr12, tdiagwrite_1_0_0_o2_1_0, N_132, - dstate_tr8_2_8_0_a2_1_a2_0, dstate_tr8_1_8_0_a2_0, N_505, - cctrlwr19_2_0_o2_0_0, N_223, N_3091_3, - cctrlwr19_2_0_o2_7_0, N_3798, dstate_tr8_5_9_0_a2_0_a2_0, - \rdatasel_1_i_a5_1[7]\, un1_dci_NE_17, un1_dci_NE_9, - un1_dci_NE_8, un1_dci_NE_15, un1_dci_NE_16, un1_dci_NE_5, - un1_dci_NE_4, un1_dci_NE_13, un1_dci_NE_0, un1_dci_NE_11, - un1_dci_16_i, un1_dci_11_i, un1_dci_NE_7, un1_dci_15_i, - un1_dci_14_i, un1_dci_9_i, N_149_i_i, un1_dci_18_i, - un1_dci_10_i, un1_dci_7_i, un1_dci_1_i, cctrlwr13_0_a2_0, - \faddr[6]\, ctx_NE_5, ctx_4_i, ctx_2_i, ctx_NE_3, - ctx_NE_4, N_103_i_i, N_102_i_i, ctx_NE_1, \ctx_0[6]\, - ctx_7_i, ctx_0_i, twrite_11_m_0_a2_0_2, - twrite_11_m_0_a2_0_1, N_3845, twrite_11_m_0_a2_0_0, - cache_0, mexc_1_m_0_a2_0_2_0, mmudci_read_1_1_0_a2_0_0, - mmudci_read_1_1_0_a2_0, read, dlock, \valid_0[4]\, - \valid_0[2]\, \vmask_0_1_2_o3_0_a2_0[3]\, \valid_0[3]\, - ctx_1_sqmuxa_0_a2_0, \addr[9]\, - \rdatasel_1_i_a3_2_0[7]_net_1\, \ctx\, \asi_0[1]\, - \asi_0[2]\, \asi_0[3]\, \ddatainv_0_1_1_iv_0[15]\, - \edata[15]\, \size_RNIBHS22[0]\, \dcramo_m[239]\, - \ddatainv_0_1_1_iv_0[7]\, \edata[7]\, ddatainv_0_3_sqmuxa, - \dcramo_m[231]\, dstate_17_2, \dstate_RNIET0O2[5]\, - dstate_17_1, \dstate[6]\, \ddatainv_0_1_1_iv_0[3]\, - \edata[3]\, \dcramo_m[227]\, \ddatainv_0_1_1_iv_1[0]\, - \edata[0]\, \mcdo_m[0]\, \ddatainv_0_1_1_iv_1[1]\, - \edata[1]\, \mcdo_m[1]\, \ddatainv_0_1_1_iv_0[2]\, - \edata[2]\, \dcramo_m[226]\, \ddatainv_0_1_1_iv_0[4]\, - \xaddress_RNIQDEG2_0[0]\, \edata_m[4]\, - \ddatainv_0_1_1_iv_0[8]\, \dstate_RNII450C[1]\, - \dcramo_m[232]\, \ddatainv_0_1_1_iv_0[9]\, \edata[9]\, - \dcramo_m[233]\, \ddatainv_0_1_1_iv_0[10]\, \edata[10]\, - \dcramo_m[234]\, \ddatainv_0_1_1_iv_0[11]\, \edata[11]\, - \dcramo_m[235]\, \ddatainv_0_1_1_iv_0[13]\, \edata[13]\, - \dcramo_m[237]\, \ddatainv_0_1_1_iv_0[14]\, \edata[14]\, - \dcramo_m[238]\, \ddatainv_0_1_0_iv_1[19]\, - ddatainv_0_1_sqmuxa, ddatainv_0_4_sqmuxa, - \ddatainv_0_1_0_iv_0[19]\, \edata[19]\, \dcramo_m_i[243]\, - \newtag_1_0[19]\, \N_3254_0\, N_3875, \vmask_0_1_i_1[7]\, - N_3248, N_3282, \address_i_0[7]\, N_195, N_3291, - \ddatainv_0_1_1_iv_0[12]\, \edata[12]\, \dcramo_m[236]\, - \ddatainv_0_1_1_iv_0[5]\, \edata_m[5]\, - \ddatainv_0_1_0_iv_1[21]\, \edata[5]\, - \ddatainv_0_1_0_iv_0[21]\, \edata_m_i[21]\, un19_m_en_m_2, - N_533, \N_121\, un19_m_en_m_1, N_3595, \vmask_0_1_2_0[4]\, - \vmask_0_1_2_a4_0_0[4]\, N_128_1, dwrite_1_iv_1, - un157_m_en_m, dwrite_1_iv_0, N_55, - \ddatainv_0_1_1_iv_1[6]\, \edata[6]\, \mcdo_m[6]\, - \ddatainv_0_1_0_iv_1[16]\, \ddatainv_0_1_0_iv_0[16]\, - \edata[16]\, \dcramo_m_i[240]\, \ddatainv_0_1_0_iv_1[17]\, - \ddatainv_0_1_0_iv_0[17]\, \edata[17]\, \dcramo_m_i[241]\, - \ddatainv_0_1_0_iv_1[18]\, \ddatainv_0_1_0_iv_1[20]\, - \edata[4]\, \ddatainv_0_1_0_iv_0[20]\, \edata_m_i[20]\, - \ddatainv_0_1_0_iv_1[22]\, \ddatainv_0_1_0_iv_0[22]\, - \edata[22]\, \dcramo_m_i[246]\, \ddatainv_0_1_0_iv_1[23]\, - \ddatainv_0_1_0_iv_0[23]\, \edata[23]\, \dcramo_m_i[247]\, - \ddatainv_0_1_0_iv_1[24]\, ddatainv_0_0_sqmuxa, - \edata_m_0_i[8]\, \ddatainv_0_1_0_iv_0[24]\, \edata[24]\, - \dcramo_m_i[248]\, \ddatainv_0_1_0_iv_2[25]\, \N_425_0\, - \ddatainv_0_1_0_iv_0[25]\, \edata[25]\, \dcramo_m_i[249]\, - \ddatainv_0_1_0_iv_1[26]\, \edata_m_0_i[10]\, - \ddatainv_0_1_0_iv_0[26]\, \edata[26]\, \dcramo_m_i[250]\, - \ddatainv_0_1_0_iv_1[27]\, \edata_m_4_i[3]\, - \ddatainv_0_1_0_iv_1[28]\, \edata_m_4_i[4]\, - \ddatainv_0_1_0_iv_0[28]\, \edata_m_i[28]\, - \ddatainv_0_1_0_iv_1[29]\, \edata_m_0_i[13]\, - \ddatainv_0_1_0_iv_0[29]\, \edata[29]\, \dcramo_m_i[253]\, - \ddatainv_0_1_0_iv_1[30]\, \edata_m_4_i[6]\, - \ddatainv_0_1_0_iv_0[30]\, \edata[30]\, \dcramo_m_i[254]\, - \ddatainv_0_1_0_iv_1[31]\, \edata_m_0_i[15]\, - \newtag_1_0[18]\, N_3850, \newtag_1_0[22]\, N_3864, - \newtag_1_0[23]\, \addr[23]\, N_3878, \addr[24]\, \N_330\, - N_3892, \addr[25]\, N_236, \addr[26]\, N_245, N_3895, - \address_i_1[6]\, N_3289, N_3290, \address_i_0[8]\, - N_3295, un1_dci_12, \dstate_ns_0_8_tz[3]\, N_2994_6, - \dstate_ns_0_2_0_tz[3]\, N_2994_8, N_3002_9, N_2995_8, - un30_m_en_0, rdatasel_4_sqmuxa, \mcdo_m_0[13]\, N_2047, - flush2, \mcdo_m_0[30]\, \dstate_RNI5ED76[1]\, N_3556, - N_162, N_3298, N_3297, N_3288, N_3287, un19_eholdn, - addr_0_sqmuxa, N_27, N_3203, N_3204, addr_1_sqmuxa_2, - \addr_1[12]\, \addr_1[13]\, \addr_1[29]\, \addr_1[27]\, - \addr_1[23]\, \addr_1[28]\, \addr_1[18]\, \addr_1[22]\, - \addr_1[20]\, N_3675, N_302, N_301, N_303, N_257, N_255, - \dci_m[87]\, N_242, N_240, \dci_m[88]\, N_239, N_237, - \dci_m[86]\, N_3894, N_232, \dci_m[93]\, N_3893, N_229, - \dci_m[89]\, \N_329\, N_156, N_155, N_157, N_3849, N_3848, - \dci_m[85]\, N_148, N_146, \dci_m[84]\, addr_0_sqmuxa_1, - N_3755, N_102, \addr_1[7]\, N_2164, cache_RNO_0, N_3674, - N_2481, N_51, N_672, N_3664, \addr_1[17]\, \addr_1[21]\, - \addr_1[14]\, \addr_1[24]\, N_3197, N_111, N_32, N_19, - N_3360, N_3362, N_3363, \data2[3]\, N_130, N_91, N_131, - N_126, \vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\, N_110, - \mcdo_m_i[31]\, \mcdo_m_i[30]\, \mcdo_m_i[29]\, - \mcdo_m_i[28]\, \mcdo_m_i[27]\, \mcdo_m_i[26]\, - \edata_m_4_i[1]\, \edata_m_0_i[9]\, \mcdo_m_i[24]\, - \mcdo_m_i[23]\, \mcdo_m_i[22]\, \mcdo_m_i[20]\, - \mcdo_m_i[18]\, \mcdo_m_i[17]\, \mcdo_m_i[16]\, - \edata_m[6]\, \dcramo_m[230]\, N_3770, N_3765, N_490, - \addr_1[31]\, vaddr_1_sqmuxa, - \mmudci_trans_op_1_sqmuxa_1\, N_227, N_2938_2, N_3605, - un157_m_en, holdn_10, N_3613, flush_1_i_0, - dwrite_4_sqmuxa, holdn_RNO_0, holdn_0_sqmuxa_1, N_305, - N_304, N_306, N_349, \vmask_0_5[4]\, req_2_sqmuxa, req16, - N_60, N_580, \dstate_i_2_RNITVLGB92[8]\, N_3607, N_561, - N_3610, N_608, N_492, edata_0_sqmuxa_i, N_665, N_563, - N_3710, N_3676, N_3818, N_688, N_3814, N_562, N_467, - \mcdo_m_i[21]\, \addr_1[6]\, N_3627, ctx_1_sqmuxa, - \addr[10]\, \mcdo_m[5]\, \edata_m_0[5]\, \mcdo_m[12]\, - \edata_m_1[4]\, \mcdo_m_0[27]\, N_3294, N_3293, - \mcdo_m_0[20]\, \mcdo_m_0[14]\, \mcdo_m_0[25]\, - \mcdo_m_0[16]\, \mcdo_m_0[17]\, \mcdo_m_0[28]\, - \mcdo_m_0[8]\, \dcramo_m_0[235]\, \mcdo_m_0[11]\, - \mcdo_m_0[21]\, \mcdo_m_0[4]\, N_3069_i, N_551, N_3404, - N_3340, \ico_m[135]\, \mcdo_m_0[1]\, N_179, N_178, - \addr_1[25]\, \mcdo_m_0[26]\, \addr_1[30]\, \addr_1[26]\, - \addr_1[16]\, N_587, N_3775, N_556, \addr_1[0]\, - \mmudco_m[2]\, \dci_m[8]\, N_90, N_3279, N_3278, - \addr_1[15]\, N_3494, \addr_1[4]\, N_3320, \addr_1[5]\, - \addr_1[11]\, N_282, N_285, \addr_1[19]\, N_158, - ready_0_sqmuxa, ready_RNO_0, \vmask_0_5[2]\, N_3657, - N_3655, N_345, \valid_0[0]\, un17_m_en, N_3653, N_568, - N_3564_i, N_3546, N_3700, N_3699, \size_0[1]\, \size[0]\, - \addr[1]\, ready_0_sqmuxa_0, N_3660, N_21, N_3364, N_3365, - N_3366, \data2[5]\, N_3421, N_679, N_143, N_25, \ics[0]\, - \mcdo_m_i[19]\, \mcdo_m[14]\, \edata_m_1[6]\, - \mcdo_m[13]\, \edata_m_1[5]\, \mcdo_m[11]\, - \edata_m_1[3]\, \mcdo_m[10]\, \edata_m_1[2]\, \mcdo_m[9]\, - \edata_m_1[1]\, \mcdo_m[8]\, \edata_m_1[0]\, \mcdo_m[4]\, - \edata_m_0[4]\, \mcdo_m[2]\, \edata_m_0[2]\, \edata_m[1]\, - \dcramo_m[225]\, \edata_m[0]\, \dcramo_m[224]\, N_202, - N_3259, N_3313, N_3397, N_3341, rdatasel_0_sqmuxa_1, - hit_1_iv_0_a2_0, lock_2_sqmuxa, N_86, N_3554, lock_1, - N_3553, N_3555, N_56, \addr_1[8]\, \mcdo_m[3]\, - \edata_m_0[3]\, \addr_1[9]\, flush_1_sqmuxa, - un1_eholdn_2_9, \valid_0_1[7]\, N_3285, N_3283, N_3286, - N_3286_1, twrite_14, \dstate_RNIR2CO3[4]\, N_3752, N_3760, - N_3698, N_503, \xaddress_1[2]\, N_652_i, N_115, - \addr_1[3]\, \addr_1[2]\, \addr_1[1]\, \mcdo_m[7]\, - \edata_m_0[7]\, \mcdo_m[15]\, \edata_m_1[7]\, N_557, - flush_RNICQGM51, N_3322, flush_RNITKH06, - dstate_tr22_15_a2_2_m1_e, e_0_0_RNIIAUC4Q1, burst_1_N_9, - burst_1_N_7, burst_1_N_12, burst_RNO_3, burst_RNO, - vaddr_1_sqmuxa_0_a2_4_m7_i_a4, dstate_tr22_15_a2_1, - N_3787, holdn_RNO_4, dstate_tr22_15_a2_2_m8_i_a5_0_0, - dstate_tr22_15_a2_4_1, dstate_tr22_15_a2_9_0, - \ddatainv_0_1_3_0[0]\, N_3763, N_3782, - \ddatainv_0_1_0_0[24]\, \addr[0]\, N_3764, N_3785, - \dstate_ns_0_0_a2_0_1[2]\, N_549, N_574, N_3153, - hit_RNO_2, N_575, N_3569, N_3835, \xaddress_RNIQDEG2[0]\, - holdn_RNO_3, dstate_tr22_15_a2_15_0, - \vaddr_1_sqmuxa_0_a2_2\, \stpend_RNI6P41NG3\, - \valid_0_1_1_0[5]\, \valid_0_1_1_a4_1_0[5]\, N_188, - \valid_0_1_1_0[1]\, \valid_0_1_1_a4_1_0[1]\, N_16828_tz, - \dstate_RNO_1[6]\, \dstate_ns_0_0_a2_0[2]\, N_95, N_96, - N_136, \valid_0_1[5]\, N_88, \dstate_i_RNII68N892_0[8]\, - \valid_0_1[1]\, cache_1, N_3836, \edata[20]\, \edata[28]\, - dstate_25, N_2675, N_2684, N_3668, \dstate_nss[8]\, - N_2664, N_2667, \ctx_0[4]\, N_2668, N_2669, N_2670, - \ctx_0[7]\, \data2[24]\, \mcdo_m_0[24]\, \data2[28]\, - \ctxp[26]\, \valid_0[1]\, \data2[4]\, \data2[6]\, - \ctx[6]\, N_3338, N_2126, \data1_1[28]\, \data2_1[28]\, - N_2105, \data2[7]\, N_2108, \data2[10]\, N_2110, - \data2[12]\, \data1_1[7]\, \data1_1[10]\, \data1_1[11]\, - N_2109, \data1_1[12]\, \data2_1[10]\, \data2_1[12]\, - N_2111, \data2[13]\, N_2116, \data2[18]\, N_2118, - \data2[20]\, \data1_1[13]\, \data1_1[18]\, \data1_1[20]\, - \data2_1[13]\, \data2_1[18]\, \data2_1[20]\, N_2120, - \data1_1[22]\, \data2_1[22]\, N_2099, \data2[1]\, N_2112, - N_2121, \data2[23]\, \data1_1[1]\, \data1_1[14]\, - \data1_1[23]\, \data2_1[1]\, \data2_1[14]\, \data2_1[23]\, - N_2122, \data1_1[19]\, N_2117, \data1_1[24]\, - \data2_1[24]\, N_2115, N_2123, \data2[25]\, \data1_1[17]\, - req_0_sqmuxa_1, \data1_1[25]\, \data2_1[17]\, - \data2_1[25]\, N_2124, \data2[26]\, \data1_1[26]\, - \data2_1[26]\, N_2098, \data2[0]\, N_2125, \data2[27]\, - \data1_1[0]\, \data1_1[27]\, \data2_1[0]\, \data2_1[27]\, - N_2113, N_2127, \data2[29]\, \data1_1[15]\, \data1_1[29]\, - \ctxp[27]\, \mcdo_m_0[29]\, \data2_1[15]\, \data2_1[29]\, - N_2128, \data2[30]\, \data1_1[30]\, \data2_1[30]\, N_2129, - \data2[31]\, \data1_1[31]\, \data2_1[31]\, N_184, - twrite_14_iv_0_a2_a0_RNIGON1LK, N_2102, \data1_1[4]\, N_8, - N_3260, N_3270, N_2100, \data2[2]\, N_2104, \data1_1[2]\, - \data1_1[6]\, \data2_1[6]\, N_3347, N_3348, N_2114, - \data2[16]\, \data1_1[16]\, \data2_1[16]\, N_727, N_3598, - N_3599, N_3805, N_3600, N_3757, N_552, N_3796, - \paddress[7]\, \addr[7]\, N_486, \hold\, \paddress[24]\, - \paddress[29]\, \addr[29]\, \paddress[21]\, \addr[21]\, - \paddress[17]\, \addr[17]\, \paddress[14]\, \addr[14]\, - N_564, \data[28]\, \vaddr[28]\, \data[12]\, \vaddr[12]\, - \vaddr[18]\, \vaddr[20]\, \vaddr[22]\, \vaddr[23]\, - \vaddr[13]\, \vaddr[24]\, \vaddr[17]\, \vaddr[25]\, - \vaddr[26]\, \vaddr[27]\, \data[15]\, \vaddr[15]\, - \vaddr[29]\, \vaddr[1]\, \vaddr[16]\, \data[30]\, - \vaddr[30]\, \vaddr[11]\, \vaddr[14]\, \vaddr[31]\, - \vaddr[19]\, \vaddr[8]\, \vaddr[9]\, \un1_m0_2[86]\, - \vaddr[10]\, \un1_m0_2[83]\, \vaddr[7]\, \vaddr[6]\, - \vaddr[5]\, \vaddr[4]\, N_674, \paddress[27]\, \addr[27]\, - \paddress[12]\, \addr[12]\, \paddress[13]\, \addr[13]\, - N_710, \addr[6]\, N_712, N_718, \e\, \ctxp[28]\, N_3319, - un1_taddr_1_sqmuxa, \faddr[5]\, N_2233, \taddr_7[6]\, - taddr_2_sqmuxa, N_3344_i_0, \un1_m0_2[80]\, N_2232, - \taddr_7[5]\, lrr_1_sqmuxa, read_RNO, nf_RNO, \ctx_0[0]\, - N_3780, \addr[28]\, \addr[18]\, \addr[20]\, N_3842, - \addr[22]\, N_3840, \addr[16]\, \addr[15]\, addr_2_sqmuxa, - \addr[31]\, addr_1_sqmuxa, \un1_m0_2[81]\, - \valid_0_RNI7F6M2[0]\, \dstate_i_RNID1NU1[8]\, N_3833, - \paddress[23]\, \paddress[28]\, \paddress[22]\, - \paddress[18]\, \paddress[20]\, N_484, N_3246, N_3665_1, - N_582, N_2663, \vaddr[0]\, N_3799, N_537, \paddress[31]\, - mmctrl1wr_RNO, \vaddr[3]\, flush_0, pso_RNO, N_2674, pso, - tlbdis_RNO, N_2673, N_716, \un1_m0_2[85]\, - \dstate_nss[5]\, \dstate_ns[5]\, trans_op_RNO_1, - flush_op_RNO, N_3672, \trans_op\, \flush_op_i_0\, - flush_op, N_2715_i, \taddr_7[11]\, \faddr_1_i[6]\, - \faddr_1[5]\, I_24_1, \faddr_1[4]\, I_20_1, \faddr_1[3]\, - I_13_5, \faddr_1[2]\, I_9_1, \faddr_1[1]\, I_5_1, - \faddr_1[0]\, N_2238, \addr[11]\, faddr_2_sqmuxa, - dstate_5_sqmuxa, stpend_RNO, \data2_1[4]\, req_RNO, - N_3588, N_3572, N_3671, \dstate_nss[2]\, N_3810, N_3709, - N_3743, N_3742, \vaddr[21]\, \data2_1[21]\, \data1_1[21]\, - N_2119, \data2[21]\, \edata[21]\, N_2666, N_2665, - \vaddr[2]\, \un1_m0_2[82]\, \burst\, N_419_0, - \un1_m0_2[78]\, \un1_m0_2[77]\, ddatainv_0_2_sqmuxa, - \faddr[4]\, \N_425\, N_2629, N_2676, \dstate_nss[3]\, - \dstate_nss[4]\, ilramen_1_sqmuxa, \dstate_nss[7]\, \nf\, - \burst_0\, rdatav_012, rdatav_0_6_sqmuxa, - rdatasel_1_sqmuxa_1, \ctx[2]\, \data2[11]\, \dstate[7]\, - N_3377, N_3380, \valid_0_1[0]\, \valid_0_1[3]\, N_3339, - \ctx[3]\, N_2107, \data2[9]\, \data1_1[9]\, \data2_1[7]\, - \data2_1[9]\, \data2_1[11]\, \data2_1[19]\, - \paddress_0[25]\, \paddress[30]\, \paddress_0[30]\, - \paddress_0[26]\, valid_0_2_sqmuxa, N_2362, - \vmask_0_6[2]\, N_2366, \vmask_0_6[6]\, N_2381, N_2385, - \valid_0_1[2]\, \valid_0_1[6]\, \data2_1[2]\, N_3244_i_0, - N_3808, N_3800, paddress_1_sqmuxa, \paddress[16]\, - \paddress_0[16]\, N_3662, N_534, N_3793, N_3621, N_3623, - N_3625, N_3626, \addr[4]\, N_3766, N_3768, \dcs_RNO[0]\, - N_671, N_591, \paddress[15]\, \paddress[4]\, N_709, N_713, - N_715, N_719, \un1_m0_2[76]\, \paddress_0[0]\, N_7, - N_2016, N_2017, \vmask_0_5[7]\, N_3315, N_2230, N_2229, - mexc_1_sqmuxa, burst_RNO_0, \ctx[0]\, \ics[1]\, - \addr[19]\, \un1_m0_2[87]\, N_296, N_298, N_348, - \vmask_0_5[6]\, \paddress[19]\, \cache\, \tlbdis\, - \ctx[7]\, N_3754, N_182, N_2013, N_2014, N_2012, N_9, - hit_1, data1_0_sqmuxa, \paddress_0[8]\, \un1_m0_2[84]\, - su_0, \paddress_0[9]\, N_509, \vmask_0_4[6]\, N_2026, - \valid_0[6]\, \valid_0_1[4]\, N_2364, N_44_i_0, - \vmask_0_4[7]\, N_2027, \valid_0[7]\, \valid_0[5]\, - \taddr_7[7]\, \faddr[2]\, N_2234, burst_1_sqmuxa, - nomds_RNO, N_2596, nomds_1, N_670, N_3791, \paddress[2]\, - N_323, size, \un1_m0_2[79]\, \paddress_0[1]\, - \paddress[3]\, N_654, N_653, \mcdo_m_0[31]\, \ctxp[29]\, - N_3261, \read_2\, \trans_op_0\, \ctx[5]\, \asi_0[0]\, - \size_1[0]\, \size_1[1]\, \ctxp[0]\, \ctxp[1]\, \ctxp[2]\, - \ctxp[3]\, \ctxp[4]\, \ctxp[5]\, \ctxp[6]\, \ctxp[7]\, - \ctxp[8]\, \ctxp[9]\, \ctxp[10]\, \ctxp[11]\, \ctxp[12]\, - \ctxp[13]\, \ctxp[14]\, \ctxp[15]\, \ctxp[16]\, - \ctxp[17]\, \ctxp[18]\, \ctxp[19]\, \ctxp[20]\, - \ctxp[21]\, \ctxp[22]\, \ctxp[23]\, \ctxp[24]\, - \ctxp[25]\, \addr[30]\, \address[0]\, \address[1]\, - \address[2]\, \address[3]\, \address[4]\, \address[5]\, - \address[6]\, \address[7]\, \address[8]\, \address[9]\, - \address[10]\, \address[11]\, \address[12]\, - \address[13]\, \address[14]\, \address[15]\, - \address[16]\, \address[17]\, \address[18]\, - \address[19]\, \address[20]\, \address[21]\, - \address[22]\, \address[23]\, \address[24]\, - \address[25]\, \address[26]\, \address[27]\, - \address[28]\, \address[29]\, \address[30]\, - \address[31]\, N_4, \DWACT_FINC_E[1]\, N_9_0, N_17, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - size_1(1) <= \size_1[1]\; - size_1(0) <= \size_1[0]\; - ctx(7) <= \ctx[7]\; - ctx(6) <= \ctx[6]\; - ctx(5) <= \ctx[5]\; - ctx(3) <= \ctx[3]\; - ctx(2) <= \ctx[2]\; - ctx(0) <= \ctx[0]\; - asi_0_0 <= \asi_0[0]\; - ics(1) <= \ics[1]\; - ics(0) <= \ics[0]\; - data(30) <= \data[30]\; - data(28) <= \data[28]\; - data(15) <= \data[15]\; - data(12) <= \data[12]\; - un1_m0_2_77 <= \un1_m0_2[78]\; - un1_m0_2_78 <= \un1_m0_2[79]\; - un1_m0_2_75 <= \un1_m0_2[76]\; - un1_m0_2_79 <= \un1_m0_2[80]\; - un1_m0_2_80 <= \un1_m0_2[81]\; - un1_m0_2_81 <= \un1_m0_2[82]\; - un1_m0_2_84 <= \un1_m0_2[85]\; - un1_m0_2_83 <= \un1_m0_2[84]\; - un1_m0_2_86 <= \un1_m0_2[87]\; - un1_m0_2_76 <= \un1_m0_2[77]\; - un1_m0_2_85 <= \un1_m0_2[86]\; - un1_m0_2_82 <= \un1_m0_2[83]\; - rdatav_0_1_0_iv_5_20 <= \rdatav_0_1_0_iv_5[24]\; - rdatav_0_1_0_iv_4_29 <= \rdatav_0_1_0_iv_4[29]\; - rdatav_0_1_0_iv_4_31 <= \rdatav_0_1_0_iv_4[31]\; - mcdo_m_0_28 <= \mcdo_m_0[29]\; - mcdo_m_0_23 <= \mcdo_m_0[24]\; - mcdo_m_0_30 <= \mcdo_m_0[31]\; - ctxp_13 <= \ctxp[13]\; - ctxp_16 <= \ctxp[16]\; - ctxp_7 <= \ctxp[7]\; - ctxp_10 <= \ctxp[10]\; - ctxp_3 <= \ctxp[3]\; - ctxp_8 <= \ctxp[8]\; - ctxp_19 <= \ctxp[19]\; - ctxp_17 <= \ctxp[17]\; - ctxp_15 <= \ctxp[15]\; - ctxp_14 <= \ctxp[14]\; - ctxp_20 <= \ctxp[20]\; - ctxp_18 <= \ctxp[18]\; - ctxp_6 <= \ctxp[6]\; - ctxp_21 <= \ctxp[21]\; - ctxp_11 <= \ctxp[11]\; - ctxp_4 <= \ctxp[4]\; - ctxp_25 <= \ctxp[25]\; - ctxp_0 <= \ctxp[0]\; - ctxp_22 <= \ctxp[22]\; - ctxp_23 <= \ctxp[23]\; - ctxp_24 <= \ctxp[24]\; - ctxp_5 <= \ctxp[5]\; - ctxp_12 <= \ctxp[12]\; - ctxp_9 <= \ctxp[9]\; - ctxp_1 <= \ctxp[1]\; - ctxp_2 <= \ctxp[2]\; - address(31) <= \address[31]\; - address(30) <= \address[30]\; - address(29) <= \address[29]\; - address(28) <= \address[28]\; - address(27) <= \address[27]\; - address(26) <= \address[26]\; - address(25) <= \address[25]\; - address(24) <= \address[24]\; - address(23) <= \address[23]\; - address(22) <= \address[22]\; - address(21) <= \address[21]\; - address(20) <= \address[20]\; - address(19) <= \address[19]\; - address(18) <= \address[18]\; - address(17) <= \address[17]\; - address(16) <= \address[16]\; - address(15) <= \address[15]\; - address(14) <= \address[14]\; - address(13) <= \address[13]\; - address(12) <= \address[12]\; - address(11) <= \address[11]\; - address(10) <= \address[10]\; - address(9) <= \address[9]\; - address(8) <= \address[8]\; - address(7) <= \address[7]\; - address(6) <= \address[6]\; - address(5) <= \address[5]\; - address(4) <= \address[4]\; - address(3) <= \address[3]\; - address(2) <= \address[2]\; - address(1) <= \address[1]\; - address(0) <= \address[0]\; - addr_30 <= \addr[30]\; - addr_11 <= \addr[11]\; - addr_6 <= \addr[6]\; - addr_4 <= \addr[4]\; - addr_7 <= \addr[7]\; - addr_5 <= \addr[5]\; - addr_3 <= \addr[3]\; - addr_8 <= \addr[8]\; - addr_10 <= \addr[10]\; - addr_9 <= \addr[9]\; - addr_2 <= \addr[2]\; - un1_p0_2_0(498) <= \un1_p0_2_0[498]\; - ctx_0(7) <= \ctx_0[7]\; - ctx_0(6) <= \ctx_0[6]\; - ctx_0(5) <= \ctx_0[5]\; - ctx_0(4) <= \ctx_0[4]\; - ctx_0(3) <= \ctx_0[3]\; - ctx_0(2) <= \ctx_0[2]\; - ctx_0(1) <= \ctx_0[1]\; - ctx_0(0) <= \ctx_0[0]\; - size_1z <= size; - burst_0 <= \burst_0\; - N_425 <= \N_425\; - trans_op_0 <= \trans_op_0\; - flush_op_i_0 <= \flush_op_i_0\; - trans_op <= \trans_op\; - tlbdis <= \tlbdis\; - read_2 <= \read_2\; - e <= \e\; - nf <= \nf\; - vaddr_1_sqmuxa_0_a2_2 <= \vaddr_1_sqmuxa_0_a2_2\; - stpend_RNI6P41NG3 <= \stpend_RNI6P41NG3\; - N_329 <= \N_329\; - N_330 <= \N_330\; - cache <= \cache\; - lock_0 <= \lock_0\; - req <= \req\; - N_523 <= \N_523\; - burst <= \burst\; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 <= - \vaddr_1_sqmuxa_0_a2_4_m1_e_24\; - mmudci_trans_op_1_sqmuxa_1 <= \mmudci_trans_op_1_sqmuxa_1\; - hold <= \hold\; - N_425_0 <= \N_425_0\; - N_121 <= \N_121\; - N_3254_0 <= \N_3254_0\; - e_0 <= \e_0\; - - \r.wb.addr_RNO_3[2]\ : OR2B - port map(A => un1_m0_2_3, B => addr_1_sqmuxa, Y => N_314); - - \r.cctrl.burst_RNO\ : NOR2B - port map(A => rst, B => N_2629, Y => burst_RNO_0); - - \r.wb.data1_RNO[22]\ : MX2A - port map(A => N_2120, B => maddress(22), S => - req_0_sqmuxa_1_0, Y => \data1_1[22]\); - - \r.holdn_RNI8AEJ\ : NOR3B - port map(A => enaddr, B => \hold\, C => \dstate_i_0[8]\, Y - => N_486_0); - - mexc_1_sqmuxa_0_o2 : OR2 - port map(A => un1_m0_2_0_d0, B => un1_m0_2_34, Y => N_506); - - \r.mmctrl1.ctx_0_0_RNI5V101[1]\ : NOR3C - port map(A => N_103_i_i, B => N_102_i_i, C => ctx_NE_1, Y - => ctx_NE_4); - - \v.mmctrl1.e_0_sqmuxa_RNILF2I\ : MX2 - port map(A => \e\, B => maddress(0), S => e_0_sqmuxa, Y => - N_2676); - - \r.mmctrl1.ctxp_RNIRQ1UD[18]\ : NOR3C - port map(A => \ctxp_m[18]\, B => \rdatav_0_1_0_iv_1[20]\, C - => \rdatav_0_1_0_iv_3[20]\, Y => \rdatav_0_1_0_iv_4[20]\); - - \r.wb.addr[23]\ : DFN1 - port map(D => \addr_1[23]\, CLK => lclk_c, Q => - \address[23]\); - - \r.flush_0_1_RNI4FE0MI\ : NOR3C - port map(A => flush_1_i_0, B => faddr_1_sqmuxa_0, C => rst, - Y => faddr_2_sqmuxa); - - \r.holdn_RNIPU251\ : OR2B - port map(A => maddress(3), B => N_534, Y => N_3808); - - \r.cctrl.dcs_RNO_0[0]\ : MX2C - port map(A => maddress(2), B => \dcs[0]\, S => \N_523\, Y - => N_671); - - \r.vaddr[2]\ : DFN1E1 - port map(D => maddress(2), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[2]\); - - \r.dstate_RNI1JGE7_2[2]\ : AOI1B - port map(A => diagdata_8, B => \dstate[2]\, C => - \dcramo_m_0[232]\, Y => \rdatav_0_1_0_iv_3[8]\); - - \r.holdn_RNIQ28U_0\ : OR3 - port map(A => N_3763, B => maddress(0), C => maddress(1), Y - => N_3621); - - \r.dstate_i_2_RNISK8N1_25[8]\ : OR2B - port map(A => dataout_0(18), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[118]\); - - \r.xaddress[28]\ : DFN1E1 - port map(D => maddress(28), CLK => lclk_c, E => N_486, Q - => \addr[28]\); - - \r.wb.addr[13]\ : DFN1 - port map(D => \addr_1[13]\, CLK => lclk_c, Q => - \address[13]\); - - \r.flush2_RNIP0PM5\ : OA1A - port map(A => un6_validrawv, B => un10_m_en, C => N_499, Y - => setrepl_0_sqmuxa_1_m_i_5_1); - - \r.wb.addr_RNO_1[24]\ : OR2B - port map(A => maddress(24), B => addr_2_sqmuxa_0, Y => - N_3634); - - \r.dstate_RNIV347A[1]\ : NOR2B - port map(A => \edata[0]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[0]\); - - \r.wb.data2_RNIIVB46[15]\ : NOR3C - port map(A => \rdatav_0_1_0_iv_0_0[15]\, B => N_205, C => - \mmudco_m[58]\, Y => \rdatav_0_1_0_iv_0_2[15]\); - - \r.wb.data1_RNO_2[5]\ : NOR3A - port map(A => edata2_0_iv(5), B => req_0_sqmuxa_1_0, C => - N_3331_0, Y => N_3366); - - \r.wb.addr_RNO_4[27]\ : OR2B - port map(A => \address[27]\, B => N_514, Y => N_253); - - \r.wb.addr_RNO_2[25]\ : OR2B - port map(A => maddress(25), B => addr_2_sqmuxa, Y => - \dci_m[33]\); - - \r.mmctrl1.ctxp[5]\ : DFN1E1 - port map(D => maddress(7), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[5]\); - - \r.wb.addr_RNO[11]\ : OR3C - port map(A => N_282, B => \addr_1_1_iv_0_1[11]\, C => N_285, - Y => \addr_1[11]\); - - \r.wb.addr_RNO_6[12]\ : OR2B - port map(A => N_2886, B => addr_1_sqmuxa, Y => N_278); - - \r.wb.addr_RNO_0[2]\ : NOR3C - port map(A => \addr_1_0_iv_0_1[2]\, B => N_315, C => N_314, - Y => \addr_1_0_iv_0_3[2]\); - - \r.dstate_0_RNI0ASD21[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_0_5[15]\, B => - \rdatav_0_1_0_iv_0_4[15]\, C => N_202, Y => data_0_15); - - \r.wb.data2_RNO[16]\ : MX2 - port map(A => edata2_0_iv(16), B => hrdata_0_16, S => - \dstate_1[7]\, Y => \data2_1[16]\); - - \r.holdn_RNO_23\ : NOR2B - port map(A => e_RNIKN3D, B => N_489, Y => - holdns_iv_0_a2_1_0); - - \r.dstate_RNIHILB6_12[7]\ : OR2B - port map(A => dataout(0), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[224]\); - - \r.dstate_RNI123K[0]\ : NOR3 - port map(A => \dstate[1]\, B => \dstate[0]\, C => - \dstate[3]\, Y => dstate_19_1); - - \r.wb.addr_RNO_5[19]\ : OR2B - port map(A => N_415, B => addr_1_sqmuxa, Y => N_3890); - - \r.cctrlwr\ : DFN1 - port map(D => N_2715_i, CLK => lclk_c, Q => cctrlwr); - - \r.wb.data2[3]\ : DFN1E1 - port map(D => N_3347, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[3]\); - - \r.size_RNIQO6E_0[1]\ : NOR3A - port map(A => N_3749, B => \size_0[1]\, C => \addr[1]\, Y - => N_3805); - - \r.dstate_i_RNI3KIBI6[8]\ : OAI1 - port map(A => N_188, B => \dstate_i[8]\, C => N_182, Y => - N_88); - - \r.stpend_RNIO6COHV3\ : NOR2B - port map(A => dstate_tr22_15_a2_1_1_0, B => fault_pri, Y - => vaddr_1_sqmuxa_0_a2_a0_0); - - \r.dstate_RNIHILB6_13[7]\ : OR2B - port map(A => dataout(9), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[233]\); - - \r.dstate_0_RNIIC256_5[7]\ : OR2B - port map(A => dataout(1), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[225]\); - - \r.dstate_0_RNI8VO931[7]\ : AO1B - port map(A => \dstate_0[7]\, B => hrdata_0_0, C => - \rdatav_0_1_0_iv_7[0]\, Y => data_0_0); - - \dctrl.0.genmux.un6_validrawv_6\ : MX2C - port map(A => N_7, B => N_2016, S => maddress(3), Y => - N_2017); - - \r.dstate_RNIS3GB3[6]\ : OR2A - port map(A => \dstate[6]\, B => N_580, Y => N_3750); - - \un1_v.holdn_3_sqmuxa_0_0_a2_4\ : OR2A - port map(A => N_489, B => asi(3), Y => N_3743); - - \r.vaddr_RNIBQHC[31]\ : MX2 - port map(A => maddress(31), B => \vaddr[31]\, S => - \dstate_i_2[8]\, Y => data(31)); - - \dctrl.un1_eholdn_2_1_0_a2_0\ : NOR2 - port map(A => N_3799, B => N_2938_2, Y => N_227); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_12\ : NOR3A - port map(A => eaddress_9, B => eaddress_17, C => - eaddress_27, Y => vaddr_1_sqmuxa_0_a2_4_m1_e_12); - - \r.asi[3]\ : DFN1E1 - port map(D => asi(3), CLK => lclk_c, E => N_486_0, Q => - \asi_0[3]\); - - N_3253_i_0_a2 : NOR2 - port map(A => N_533, B => N_505, Y => N_3253_i); - - \dctrl.twrite_14_iv_0_o2_a0_RNO\ : AND2 - port map(A => twrite_14_iv_0_o2_a0_3, B => un1_addout_12, Y - => twrite_14_iv_0_o2_a0_4); - - \r.dstate_RNO_12[4]\ : OR2A - port map(A => \req\, B => N_16887_tz_tz, Y => - dstate_tr16_13_0_0_a2_0); - - \r.dstate[4]\ : DFN1 - port map(D => \dstate_nss[4]\, CLK => lclk_c, Q => - \dstate[4]\); - - \dctrl.0.un1_dci_0_0_0_x2\ : XNOR2 - port map(A => maddress(12), B => dataout_0(8), Y => - N_139_i_i); - - \r.wb.addr_RNO_5[6]\ : OR2B - port map(A => \un1_m0_2[82]\, B => addr_1_sqmuxa_2, Y => - N_3628); - - \r.dstate_2_RNIAQ3G8[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_27, Y => - \mcdo_m_0[27]\); - - \r.xaddress_RNO[4]\ : MX2 - port map(A => \addr[4]\, B => maddress(4), S => N_486_0, Y - => N_715); - - \r.vaddr_RNIIJ9G[3]\ : MX2 - port map(A => maddress_0_2, B => \vaddr[3]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[79]\); - - \dctrl.twrite_14_iv_0_o2_a0_RNO_0\ : NOR3A - port map(A => twrite_14_iv_0_o2_a0_1, B => me_nullify2_1_2, - C => nullify2_0_sqmuxa, Y => twrite_14_iv_0_o2_a0_3); - - \r.holdn_RNI1TJA\ : OR2 - port map(A => maddress(2), B => N_3443_i, Y => N_3754); - - \r.vaddr[25]\ : DFN1E1 - port map(D => maddress(25), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[25]\); - - \r.read_RNIQH64D1\ : OR3 - port map(A => \mcdo_m[15]\, B => \edata_m_1[7]\, C => - \ddatainv_0_1_1_iv_0[15]\, Y => read_RNIQH64D1); - - \r.wb.data2_RNIIOUT5[21]\ : NOR3B - port map(A => \dcramo_m[117]\, B => \data2_m[21]\, C => - \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_1[21]\); - - \r.mmctrl1.ctxp[19]\ : DFN1E1 - port map(D => maddress(21), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[19]\); - - \r.dstate_RNIN17FC[1]\ : MX2 - port map(A => maddress(11), B => edata2_0_iv(11), S => - edata_0_sqmuxa_i, Y => \edata[11]\); - - \r.dstate_RNI86ELB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[3]\, Y => \ddatainv_0_1_0_iv_1[19]\); - - \r.read_RNIEG3AM\ : OR2B - port map(A => \N_425_0\, B => hrdata_26, Y => - \mcdo_m_i[31]\); - - \r.flush_RNIJCBP1\ : NOR2B - port map(A => tdiagwrite_1_0_0_o2_1_0, B => N_3253_i, Y => - tdiagwrite_1_0_0_o2_1); - - \r.dstate_0_RNI1JGE7_7[2]\ : AOI1B - port map(A => diagdata_14, B => \dstate_0[2]\, C => - \dcramo_m_0[238]\, Y => \rdatav_0_1_0_iv_5[14]\); - - \r.mmctrl1.e_0_0_RNIPO5UKG3\ : NOR2B - port map(A => un1_m0_2_108, B => \e_0\, Y => N_3787); - - \r.dstate_RNIHILB6_8[7]\ : OR2B - port map(A => dataout(16), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[240]\); - - \r.dstate_i_1[8]\ : DFN1 - port map(D => \dstate_nss_i_0[0]\, CLK => lclk_c, Q => - \dstate_i_1[8]\); - - \dctrl.iflush_1_0_a2_0_0\ : OA1B - port map(A => cctrlwr13, B => cctrlwr11_0, C => read_0, Y - => iflush_1_0_a2_0); - - \r.nomds_RNIGK9H\ : NOR2 - port map(A => nomds, B => un17_m_en, Y => un1_dci_12_0); - - \r.mmctrl1.pso_RNI3H092\ : OR3B - port map(A => N_3259, B => N_3320, C => maddress(8), Y => - N_3302); - - \r.dstate_i_2_RNISK8N1_10[8]\ : OR2B - port map(A => dataout_0(12), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[112]\); - - \r.dstate_i_2_RNIPA514[8]\ : AOI1 - port map(A => un1_m0_2_63, B => miscdata_4_sqmuxa, C => - miscdata_0_sqmuxa, Y => \rdatav_0_1_1_iv_2[21]\); - - \r.size[0]\ : DFN1E1 - port map(D => size_0_0, CLK => lclk_c, E => N_486_0, Q => - \size[0]\); - - \r.mmctrl1.e_RNIVDG11\ : NOR3B - port map(A => asi(4), B => e_RNIKN3D, C => N_505, Y => - dstate_tr8_4_9_0_a2_0_a2_0_a2_0); - - \r.xaddress_RNIQDEG2[0]\ : OR2B - port map(A => \ddatainv_0_1_0_0[24]\, B => N_575, Y => - \xaddress_RNIQDEG2[0]\); - - \r.xaddress_RNIA46U81[11]\ : MX2A - port map(A => N_2238, B => eaddress_9, S => taddr_2_sqmuxa, - Y => \taddr_7[11]\); - - \r.valid_0_RNI7F6M2[0]\ : AO1C - port map(A => N_679, B => N_3421, C => N_345, Y => - \valid_0_RNI7F6M2[0]\); - - \r.xaddress_RNIS0S1I[8]\ : OR2 - port map(A => N_3289, B => N_3290, Y => \address_i_1[6]\); - - \r.dstate_RNICFIMC[1]\ : MX2 - port map(A => maddress(17), B => edata2_0_iv(17), S => - edata_0_sqmuxa_i, Y => \edata[17]\); - - \r.xaddress_RNI74LI2[4]\ : NOR3 - port map(A => N_3657, B => \vmask_0_5_1_0[2]\, C => N_3655, - Y => \vmask_0_5[2]\); - - \r.xaddress_RNIJH2O2[0]\ : NOR2B - port map(A => dataout(15), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[239]\); - - \r.dstate_i_2_RNITQRS1_1[8]\ : NOR2B - port map(A => \miscdata_2_sqmuxa_0_a4_0_a2_0_a3_0\, B => - N_3320, Y => miscdata_2_sqmuxa); - - mexc_0_sqmuxa_i_o2 : OR2A - port map(A => un1_m0_2_34, B => un1_m0_2_0_d0, Y => N_580); - - \r.flush_RNI7M41E91\ : AO1C - port map(A => twrite_14_iv_0_a2_a0_RNIGON1LK, B => - \dstate_RNIR2CO3[4]\, C => N_349, Y => N_3835); - - \r.mmctrl1.ctxp_RNI1J38A[13]\ : NOR3C - port map(A => tlbdis_m, B => \rdatav_0_1_0_iv_0_2[15]\, C - => \ctxp_m[13]\, Y => \rdatav_0_1_0_iv_0_4[15]\); - - \r.dstate_i_RNISEF4J92[8]\ : AO1D - port map(A => cctrlwr19_1_0, B => un1_dci_12, C => - \dstate_i[8]\, Y => burst_0_sqmuxa_3); - - \r.wb.addr_RNO[2]\ : AO1B - port map(A => maddress(2), B => N_2164, C => - \addr_1_0_iv_0_3[2]\, Y => \addr_1[2]\); - - \r.vaddr[24]\ : DFN1E1 - port map(D => maddress(24), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[24]\); - - \r.dstate_0_RNI6TSB21[2]\ : OR3C - port map(A => \rdatav_0_1_1_iv_5[21]\, B => - \rdatav_0_1_1_iv_4[21]\, C => \mcdo_m_0[21]\, Y => - data_0_21); - - \r.hit_RNO_2\ : NOR2B - port map(A => hit_1_iv_0_a2_0, B => N_84, Y => hit_RNO_2); - - \r.wb.data2_RNI24132[30]\ : AOI1B - port map(A => dataout_0(26), B => rdatasel_1_sqmuxa_1_0, C - => \data2_m[30]\, Y => \rdatav_0_1_0_iv_0[30]\); - - \r.paddress[6]\ : DFN1E1 - port map(D => un1_m0_2_7, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[6]\); - - \r.mmctrl1.ctxp_RNI3QJ12[27]\ : OR2B - port map(A => \ctxp[27]\, B => N_3344_i_0_0, Y => - \ctxp_m[27]\); - - \r.dstate_i_2_RNIAD9N[8]\ : NOR2B - port map(A => N_507, B => N_3745, Y => - \dstate_ns_i_a4_i_a2_0[0]\); - - \r.dstate_i_2_RNI76B62[8]\ : OR2 - port map(A => \dstate_i_2[8]\, B => N_485, Y => - addr_3_sqmuxa); - - \r.ready_RNO_3\ : MX2C - port map(A => N_512, B => asi(3), S => N_519, Y => - N_16828_tz); - - \r.wb.data2[14]\ : DFN1E1 - port map(D => \data2_1[14]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[14]\); - - \r.cctrl.dcs_RNIB9M04[0]\ : AOI1B - port map(A => \dcs[0]\, B => rdatav_0_0_sqmuxa, C => - \mmudco_m[38]\, Y => \rdatav_0_1_0_iv_2[2]\); - - \r.burst_RNO_0\ : AO1C - port map(A => \burst\, B => burst_0_sqmuxa_5, C => rst, Y - => burst_1_m8_i_0); - - \r.dstate_i_RNICU82792[8]\ : NOR2A - port map(A => read_1, B => \N_121\, Y => N_3781); - - \r.wb.data2_RNO[9]\ : MX2 - port map(A => edata2_0_iv(9), B => hrdata_0_9, S => - \dstate[7]\, Y => \data2_1[9]\); - - \r.flush_RNIKBAG1\ : AO1 - port map(A => read_1, B => N_132, C => mexc_1_m_0_a2_0_2_0, - Y => mexc_1_m_0_a2_0_1); - - \r.faddr_RNO[5]\ : NOR3C - port map(A => rst, B => flush_0, C => I_24_1, Y => - \faddr_1[5]\); - - \dctrl.0.un1_dci_9_0\ : XNOR2 - port map(A => dataout_0(17), B => maddress(21), Y => - un1_dci_9_i); - - \r.read_RNILAFM8\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_16, Y => - \mcdo_m_i[16]\); - - \r.asi_RNIF2TA[2]\ : NOR2B - port map(A => \asi_0[2]\, B => \asi_0[3]\, Y => un1_m_en_1); - - \r.mmctrl1.ctx_0_0[7]\ : DFN1 - port map(D => \ctx_0_0_RNID9UO[7]\, CLK => lclk_c, Q => - \ctx_0[7]\); - - \r.dstate_RNIPE6G5[1]\ : AO1 - port map(A => \edata[2]\, B => ddatainv_0_3_sqmuxa, C => - \dcramo_m[226]\, Y => \ddatainv_0_1_1_iv_0[2]\); - - \r.wb.addr_RNO_4[23]\ : MX2 - port map(A => \paddress[23]\, B => \addr[23]\, S => N_484_0, - Y => N_3838); - - \r.dstate_RNO_15[4]\ : OR2 - port map(A => N_3499, B => N_16887_tz_tz, Y => - dstate_ns_0_2065_0); - - \r.wb.addr[21]\ : DFN1 - port map(D => \addr_1[21]\, CLK => lclk_c, Q => - \address[21]\); - - \r.mmctrl1.ctxp_RNIRD91A[26]\ : NOR3C - port map(A => \mmudco_m[71]\, B => \rdatav_0_1_1_iv_2[28]\, - C => \ctxp_m[26]\, Y => \rdatav_0_1_1_iv_4[28]\); - - \r.mmctrl1.ctxp_RNIDPN0C[19]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_2[21]\, B => - \rdatav_0_1_1_iv_1[21]\, C => \ctxp_m[19]\, Y => - \rdatav_0_1_1_iv_4[21]\); - - \r.dstate_i_0_RNIQR7N[8]\ : NOR3B - port map(A => dstate_tr20_0, B => hold_0, C => - \dstate_i_0[8]\, Y => dstate_tr20_2); - - \r.vaddr[5]\ : DFN1E1 - port map(D => maddress(5), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[5]\); - - \r.mmctrl1.ctxp_RNIK8BOF[20]\ : NOR3C - port map(A => \ctxp_m[20]\, B => \rdatav_0_1_0_iv_2[22]\, C - => \rdatav_0_1_0_iv_4[22]\, Y => rdatav_0_1_0_iv_5_18); - - \r.flush_RNI2I582\ : OR2 - port map(A => flush_0, B => mexc, Y => flush_i); - - \r.vaddr_RNI66HC[30]\ : MX2 - port map(A => maddress(30), B => \vaddr[30]\, S => - \dstate_i_1[8]\, Y => \data[30]\); - - \r.paddress[17]\ : DFN1E1 - port map(D => un1_m0_2_18, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[17]\); - - \r.dstate_RNO[0]\ : AOI1B - port map(A => \dstate_ns_0_0_0[8]\, B => N_3556, C => rst, - Y => \dstate_nss[8]\); - - \r.dstate_RNIIRS9_0[2]\ : NOR2A - port map(A => \dstate[2]\, B => diagrdy, Y => - ilramen_1_sqmuxa); - - \r.cctrl.dcs_RNI14TA2[0]\ : NOR2B - port map(A => \dcs[0]\, B => N_495, Y => - setrepl_0_sqmuxa_1_m_i_5_0); - - \r.xaddress[13]\ : DFN1E1 - port map(D => maddress(13), CLK => lclk_c, E => N_486, Q - => \addr[13]\); - - \r.wb.addr[29]\ : DFN1 - port map(D => \addr_1[29]\, CLK => lclk_c, Q => - \address[29]\); - - \r.wb.addr[11]\ : DFN1 - port map(D => \addr_1[11]\, CLK => lclk_c, Q => - \address[11]\); - - \r.dstate_RNIG74RG[1]\ : AO1 - port map(A => \dstate_RNII450C[1]\, B => \size_RNIBHS22[0]\, - C => \dcramo_m[232]\, Y => \ddatainv_0_1_1_iv_0[8]\); - - \dctrl.vmaskraw_1_i_o2_i_o2[1]\ : OR2A - port map(A => N_3747, B => \addr[2]\, Y => N_559); - - \r.mmctrl1.e_0_0_RNI8APPC92\ : NOR3 - port map(A => \dstate_i_2_RNITVLGB92[8]\, B => N_3778, C - => holdn_3_sqmuxa_0_0_a2_2_0, Y => e_0_0_RNI8APPC92); - - \r.flush_RNI8M718\ : NOR3B - port map(A => \mmudco_m[57]\, B => \rdatav_0_1_0_iv_1[14]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_3[14]\); - - \r.wb.data2_RNI9BB72[1]\ : NOR2B - port map(A => N_89, B => N_3233, Y => - \rdatav_0_1_0_iv_i_a4_0[1]\); - - \r.wb.addr[19]\ : DFN1 - port map(D => \addr_1[19]\, CLK => lclk_c, Q => - \address[19]\); - - \r.dstate_RNO_8[5]\ : OR3A - port map(A => \dstate[4]\, B => wbinit, C => N_506, Y => - N_3180_i); - - \r.mmctrl1.ctxp_RNIBIFRD[29]\ : NOR3C - port map(A => \ctxp_m[29]\, B => \rdatav_0_1_0_iv_1[31]\, C - => \rdatav_0_1_0_iv_3[31]\, Y => \rdatav_0_1_0_iv_4[31]\); - - \r.vaddr[11]\ : DFN1E1 - port map(D => maddress(11), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[11]\); - - \r.dstate_i_2_RNISK8N1_9[8]\ : OR2B - port map(A => dataout_0(14), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[114]\); - - \r.wb.data1[28]\ : DFN1E0 - port map(D => \data1_1[28]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_16); - - \r.dstate_RNIGLO42[7]\ : NOR2A - port map(A => \dstate[7]\, B => N_510, Y => N_84); - - \dctrl.0.un1_dci_5_0\ : XNOR2 - port map(A => maddress(17), B => dataout_0(13), Y => - un1_dci_5_i); - - \r.wb.data2_RNI5S032[19]\ : AOI1B - port map(A => \data2[19]\, B => rdatav_012_0, C => - \dcramo_m[115]\, Y => \rdatav_0_1_0_iv_0[19]\); - - \r.cctrlwr_RNO\ : NOR2A - port map(A => N_227, B => N_3790, Y => N_2715_i); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_0[10]\ : NOR3C - port map(A => N_3726, B => N_3641, C => N_3642, Y => - \addr_1_1_iv_0_2[10]\); - - \r.wb.addr_RNO_4[25]\ : OR2B - port map(A => \address[25]\, B => N_514, Y => \addr_m[25]\); - - \r.dstate_i_2_RNISK8N1_21[8]\ : OR2B - port map(A => dataout_0(25), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[125]\); - - \r.cctrl.ics_RNO_1[1]\ : NOR3B - port map(A => \ics_0_i_a4_1_0[1]\, B => \N_523\, C => - intack, Y => N_3204); - - \un1_r.faddr_I_16\ : AND3 - port map(A => \faddr[0]\, B => \faddr[1]\, C => \faddr[2]\, - Y => \DWACT_FINC_E[0]\); - - \r.mmctrl1.ctxp_RNII5F32[2]\ : NAND2 - port map(A => N_3344_i_0_0, B => \ctxp[2]\, Y => - \ctxp_m[2]\); - - \r.holdn_RNIFRAS\ : OR3A - port map(A => size_0_0, B => N_3757, C => maddress_0_0, Y - => N_3600); - - \r.valid_0_RNIQ2NB[2]\ : NOR2B - port map(A => \valid_0[2]\, B => hit, Y => - \vmask_0_5_1_a2_2_0[2]\); - - \r.xaddress_RNI4PC9O[1]\ : AOI1B - port map(A => \edata[12]\, B => ddatainv_0_4_sqmuxa, C => - \edata_m_4_i[4]\, Y => \ddatainv_0_1_0_iv_1[28]\); - - \r.wb.addr_RNO_2[6]\ : OR2B - port map(A => maddress(6), B => N_2164, Y => N_3627); - - \r.vaddr_RNI12EE[7]\ : MX2 - port map(A => maddress(7), B => \vaddr[7]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[83]\); - - \r.dstate_2_RNI4UR08[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_8, Y => - \mcdo_m_0[8]\); - - \r.burst_RNO_2\ : NOR3 - port map(A => burst_0_sqmuxa_5, B => burst_1_m8_i_a5_0, C - => burst_1_N_7, Y => burst_1_N_9); - - \r.wb.addr_RNO_5[26]\ : MX2 - port map(A => \paddress_0[26]\, B => \addr[26]\, S => N_484, - Y => \paddress[26]\); - - \r.dstate_i_2_RNIN4022[8]\ : OR2B - port map(A => un1_m0_2_37, B => miscdata_3_sqmuxa, Y => - \mmudco_m[38]\); - - \r.dstate_i_2[8]\ : DFN1 - port map(D => \dstate_nss_i_0[0]\, CLK => lclk_c, Q => - \dstate_i_2[8]\); - - \r.wb.addr_RNO[22]\ : AO1B - port map(A => un1_m0_2_97, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[22]\, Y => \addr_1[22]\); - - \r.vaddr_RNICQHC[17]\ : MX2 - port map(A => maddress(17), B => \vaddr[17]\, S => - \dstate_i_1[8]\, Y => data(17)); - - \r.mmctrl1.tlbdis_RNIJT322\ : OR2B - port map(A => \tlbdis\, B => miscdata_0_sqmuxa, Y => - tlbdis_m); - - \r.xaddress_RNIQF6M2_3[0]\ : OR2B - port map(A => dataout(24), B => N_2088, Y => - \dcramo_m_i[248]\); - - \r.dstate_RNIVFCD[0]\ : NOR2 - port map(A => \dstate[1]\, B => \dstate[0]\, Y => holdn_0_0); - - \r.xaddress_RNIQDEG2_0[0]\ : OR2B - port map(A => \ddatainv_0_1_3_0[0]\, B => N_575, Y => - \xaddress_RNIQDEG2_0[0]\); - - \r.wb.addr_RNO[16]\ : AO1B - port map(A => un1_m0_2_91, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_2[16]\, Y => \addr_1[16]\); - - \r.faddr_RNO[1]\ : NOR3C - port map(A => rst, B => flush_0, C => I_5_1, Y => - \faddr_1[1]\); - - \r.wb.data1_RNO[30]\ : MX2A - port map(A => N_2128, B => maddress(30), S => - req_0_sqmuxa_1, Y => \data1_1[30]\); - - \r.mmctrl1.tlbdis_RNO\ : NOR2B - port map(A => rst, B => N_2673, Y => tlbdis_RNO); - - \r.wb.size_RNO[0]\ : MX2 - port map(A => size_0_0, B => \size[0]\, S => \dstate_i[8]\, - Y => N_653); - - \r.mmctrl1.ctx[7]\ : DFN1 - port map(D => \ctx_0_0_RNID9UO[7]\, CLK => lclk_c, Q => - \ctx[7]\); - - \r.mmctrl1.ctxp[3]\ : DFN1E1 - port map(D => maddress(5), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[3]\); - - \r.holdn_RNIABJM\ : OR3C - port map(A => maddress_0_0, B => N_3748, C => size_0_0, Y - => N_3700); - - mmudci_trans_op_1_sqmuxa_1_0_o2 : NOR2 - port map(A => N_3791, B => N_492, Y => N_503); - - \r.vaddr_RNI26HC[12]\ : MX2 - port map(A => maddress(12), B => \vaddr[12]\, S => - \dstate_i_1[8]\, Y => \data[12]\); - - \r.dstate_RNIS3JC[2]\ : NOR2B - port map(A => dataout_1(11), B => \dstate[2]\, Y => - \ico_m_0[145]\); - - \r.dstate_i_2_RNI9SET1[8]\ : OR3B - port map(A => maddress_0_2, B => maddress(2), C => - rdatasel_0_sqmuxa_1, Y => rdatav_0_2_sqmuxa); - - \dctrl.0.un1_dci_11_0\ : XNOR2 - port map(A => dataout_0(19), B => maddress(23), Y => - un1_dci_11_i); - - \r.wb.addr_RNO[25]\ : AO1B - port map(A => \mmudco_m_0[101]\, B => N_2714, C => - \addr_1_1_iv_2[25]\, Y => \addr_1[25]\); - - \r.dstate_RNI6BSIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[6]\, Y => \ddatainv_0_1_0_iv_1[22]\); - - \r.dstate_2_RNISVQTU[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_7[4]\, B => - \rdatav_0_1_0_iv_6[4]\, C => \mcdo_m_0[4]\, Y => data_0_4); - - \r.xaddress_RNIV1DSTI[23]\ : AOI1B - port map(A => \addr[23]\, B => \N_330\, C => N_3878, Y => - \newtag_1_0[23]\); - - \r.wb.data2_RNO[12]\ : MX2 - port map(A => edata2_0_iv(12), B => hrdata_0_12, S => - \dstate_0[7]\, Y => \data2_1[12]\); - - \r.nomds_RNISER4B92\ : OR2A - port map(A => N_509, B => un1_dci_12, Y => N_511); - - \r.paddress[3]\ : DFN1E1 - port map(D => un1_m0_2_4, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[3]\); - - \r.mmctrl1.ctx_0_0_RNIETOV1[4]\ : OR2B - port map(A => \ctx_0[4]\, B => miscdata_2_sqmuxa, Y => - \ctx_m[4]\); - - \dctrl.0.un1_dci_3_0_0_x2\ : XNOR2 - port map(A => dataout_0(11), B => maddress(15), Y => - N_149_i_i); - - \r.dstate_i_2_RNISK8N1_6[8]\ : OR2B - port map(A => dataout_0(21), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[121]\); - - \r.read_RNIL633F1\ : OR3 - port map(A => \mcdo_m[14]\, B => \edata_m_1[6]\, C => - \ddatainv_0_1_1_iv_0[14]\, Y => read_RNIL633F1); - - \r.paddress[30]\ : DFN1E1 - port map(D => un1_m0_2_31, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress_0[30]\); - - \r.nomds_RNIJ0HM01\ : NOR2A - port map(A => twrite_14_iv_0_o2_a1_2, B => me_nullify2_1_2, - Y => twrite_14_iv_0_o2_a1_3); - - \r.size[1]\ : DFN1E1 - port map(D => size_1_d0, CLK => lclk_c, E => N_486_0, Q => - \size_0[1]\); - - \r.holdn_RNO_19\ : NOR2A - port map(A => N_3604, B => \dstate_0[2]\, Y => holdn_0); - - \dctrl.0.un1_dci_NE_13\ : NOR3C - port map(A => un1_dci_16_i, B => un1_dci_11_i, C => - un1_dci_NE_7, Y => un1_dci_NE_13); - - \r.dstate_i_2_RNIKF842[8]\ : OR2B - port map(A => un1_m0_2_55, B => miscdata_4_sqmuxa, Y => - \mmudco_m[56]\); - - \r.wb.data1_RNO_0[2]\ : MX2B - port map(A => edata2_0_iv(2), B => \data2[2]\, S => N_3331, - Y => N_2100); - - \r.xaddress_RNIQ3QK4[2]\ : MX2C - port map(A => maddress(2), B => \addr[2]\, S => - un1_taddr_1_sqmuxa, Y => N_2229); - - \r.wb.addr_RNO_1[4]\ : AOI1B - port map(A => \dstate_RNIP22L4[7]\, B => N_678, C => - \mmudco_m[80]\, Y => \addr_1_1_iv_0_0[4]\); - - \r.dstate_0_RNISS4BF[2]\ : NOR3C - port map(A => \ctxp_m[22]\, B => \rdatav_0_1_0_iv_2[24]\, C - => \rdatav_0_1_0_iv_4[24]\, Y => \rdatav_0_1_0_iv_5[24]\); - - \r.xaddress_RNIUGTB[3]\ : NOR3A - port map(A => flush_0_sqmuxa_0_o3_i_o2_0, B => \addr[3]\, C - => read_0, Y => flush_0_sqmuxa_0_o3_i_o2_5); - - \r.flush\ : DFN1 - port map(D => N_2710_i, CLK => lclk_c, Q => flush_0); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_2\ : NOR3A - port map(A => eaddress_0, B => eaddress_3, C => eaddress_7, - Y => vaddr_1_sqmuxa_0_a2_4_m1_e_2); - - \r.wb.addr_RNO_3[24]\ : OR2B - port map(A => \address[24]\, B => N_514, Y => N_3739); - - \r.mmctrl1.ctx[4]\ : DFN1 - port map(D => \ctx_0_0_RNI7TTO[4]\, CLK => lclk_c, Q => - ctx(4)); - - \r.dstate_RNIFF53J[4]\ : NOR3C - port map(A => N_3682, B => \dstate_ns_i_a4_i_2[0]\, C => - \dcs_RNIBN6EB[0]\, Y => \dstate_ns_i_a4_i_4[0]\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNI9ON72\ : OR2A - port map(A => N_495, B => N_502, Y => N_527); - - \dctrl.twrite_14_iv_0_a2_a0_RNIGON1LK\ : AO1B - port map(A => N_3322, B => N_3246, C => - \dstate_i_RNII68N892_0[8]\, Y => - twrite_14_iv_0_a2_a0_RNIGON1LK); - - \r.wb.data1_RNO_0[19]\ : MX2C - port map(A => edata2_0_iv(19), B => \data2[19]\, S => - N_3331, Y => N_2117); - - \r.faddr_RNIBVMU01[5]\ : AO1D - port map(A => eaddress_8, B => N_195, C => N_3295, Y => - \address_i_0[8]\); - - \r.dstate_RNI7GDD[5]\ : NOR2 - port map(A => \dstate[5]\, B => \dstate[4]\, Y => - edata_0_sqmuxa_1); - - \r.wb.addr[26]\ : DFN1 - port map(D => \addr_1[26]\, CLK => lclk_c, Q => - \address[26]\); - - \r.paddress[0]\ : DFN1E1 - port map(D => un1_m0_2_1, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress_0[0]\); - - \r.dstate_i_2_RNISK8N1_27[8]\ : OR2B - port map(A => dataout_0(4), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[100]\); - - \r.wb.data1[16]\ : DFN1E0 - port map(D => \data1_1[16]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_4); - - \r.mmctrl1.nf\ : DFN1 - port map(D => nf_RNO, CLK => lclk_c, Q => \nf\); - - \r.dstate_i_2_RNIF2GP[8]\ : NOR2A - port map(A => lock, B => N_526, Y => dstate_tr22_15_a2_9_0); - - \r.dstate_RNIHTD53[3]\ : NOR3A - port map(A => \dstate_RNIET0O2[5]\, B => \dstate[3]\, C => - \dstate[2]\, Y => dstate_17_2); - - \r.dstate_RNI3I7EH[7]\ : MX2C - port map(A => N_3339, B => hrdata_0_3, S => \dstate[7]\, Y - => N_3340); - - \r.dstate_0_RNI16DP2[2]\ : NOR3B - port map(A => dstate_19_1, B => data2_1_sqmuxa, C => - \dstate_0[2]\, Y => dstate_19_3); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_1[10]\ : AOI1B - port map(A => \paddress[10]\, B => N_3792, C => N_3725, Y - => \addr_1_1_iv_0_1[10]\); - - \r.wb.addr[16]\ : DFN1 - port map(D => \addr_1[16]\, CLK => lclk_c, Q => - \address[16]\); - - \r.dstate_i_RNIKIKVI92[8]\ : AOI1B - port map(A => un19_m_en_m_2, B => un19_m_en_m_1, C => - un157_m_en_m, Y => dwrite_1_iv_1); - - \r.cctrl.burst_RNI4ATO7\ : NOR3B - port map(A => \rdatav_0_1_1_iv_0[16]\, B => burst_m, C => - \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_2[16]\); - - \r.xaddress_RNICFI17S2[13]\ : OR3C - port map(A => N_3849, B => N_3848, C => \dci_m[85]\, Y => - xaddress_RNICFI17S2(13)); - - \r.wb.data1_RNO_0[25]\ : MX2C - port map(A => edata2_iv_i_0(25), B => \data2[25]\, S => - N_3331_0, Y => N_2123); - - \r.paddress[5]\ : DFN1E1 - port map(D => un1_m0_2_6, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[5]\); - - \r.mmctrl1.ctxp[9]\ : DFN1E1 - port map(D => maddress(11), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[9]\); - - \r.trans_op_RNO\ : NOR3A - port map(A => rst, B => un2_m_tlb_type, C => \trans_op\, Y - => trans_op_RNO_1); - - \r.dstate_i_2_RNIOV842[8]\ : OR2B - port map(A => un1_m0_2_59, B => miscdata_4_sqmuxa, Y => - \mmudco_m[60]\); - - \r.dstate_i_2_RNI447L1[8]\ : NOR2 - port map(A => maddress(10), B => rdatasel_4_sqmuxa, Y => - N_3320); - - \r.wb.data1_RNO[20]\ : MX2A - port map(A => N_2118, B => maddress(20), S => - req_0_sqmuxa_1_0, Y => \data1_1[20]\); - - \r.dstate_i_2_RNISK8N1_7[8]\ : OR2B - port map(A => dataout_0(17), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[117]\); - - \r.wb.data2_RNI7FOB[31]\ : OR2B - port map(A => \data2[31]\, B => rdatav_012, Y => - \data2_m[31]\); - - \r.flush_0_1_RNIO3F3O61\ : OA1A - port map(A => \un1_p0_2_0[498]\, B => N_3248, C => N_3282, - Y => \vmask_0_1_i_1[7]\); - - \r.dstate_i_RNICGCDG92[8]\ : OR2A - port map(A => edata2_0_iv(7), B => - \dstate_i_RNII68N892_0[8]\, Y => N_3279); - - \r.xaddress_RNIRDIV8[8]\ : NOR3B - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - \addr[8]\, Y => N_3290); - - \r.xaddress_RNIK99NK1[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[29]\, B => - \mcdo_m_i[29]\, C => \ddatainv_0_1_0_iv_1[29]\, Y => - xaddress_RNIK99NK1(1)); - - \r.wb.data1[30]\ : DFN1E0 - port map(D => \data1_1[30]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_18); - - \r.mmctrl1.ctx_0_0_RNINUPHF[5]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_i_a2_4[5]\, B => - \rdatav_0_1_1_iv_i_a2_3[5]\, C => N_3395, Y => - \rdatav_0_1_1_iv_i_a2_6[5]\); - - \r.holdn_RNO_27\ : NOR2A - port map(A => holdn_0_sqmuxa_1_m8_0_a2_0, B => N_576, Y => - holdn_0_sqmuxa_1_m8_0_a2_1); - - \r.dstate_i_2_RNIA2SML3[8]\ : OR2A - port map(A => vaddr_1_sqmuxa_0_0, B => - \mmudci_trans_op_1_sqmuxa_1\, Y => vaddr_1_sqmuxa_0); - - \r.wb.addr_RNO_5[20]\ : OR2B - port map(A => N_417, B => addr_1_sqmuxa_0, Y => N_3862); - - \r.dstate_1_RNIP4DE1[7]\ : OR2B - port map(A => \dstate_1[7]\, B => hrdata_0_13, Y => - \mcdo_m_0[13]\); - - \r.dstate_RNI9MVN21[2]\ : OR3C - port map(A => \rdatav_0_1_1_iv_i_a2_6[5]\, B => N_3397, C - => N_3341, Y => N_3389_i_0); - - \r.dstate_i_2_RNIHH1P1[8]\ : NOR2A - port map(A => N_3320, B => maddress(9), Y => N_3321); - - \r.read_RNISF83A\ : NOR2B - port map(A => \N_425\, B => hrdata_0_7, Y => \mcdo_m[7]\); - - \r.mmctrl1.e_RNIVSEJ1\ : NOR3B - port map(A => N_3755, B => e_RNIKN3D, C => N_590, Y => - N_2994_8); - - \r.mmctrl1.ctx_RNIB8BR[0]\ : NOR2B - port map(A => rst, B => N_2663, Y => \ctx_RNIB8BR[0]\); - - \r.wb.lock\ : DFN1E0 - port map(D => lock_1, CLK => lclk_c, E => lock_2_sqmuxa, Q - => \lock_0\); - - \r.holdn_RNI1OS81\ : NOR2 - port map(A => maddress(4), B => N_3808, Y => N_3655); - - \r.read_RNIC9O9B1\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[21]\, B => - \mcdo_m_i[21]\, C => \ddatainv_0_1_0_iv_1[21]\, Y => - read_RNIC9O9B1); - - \r.dstate_RNI1G47MJ[1]\ : OR3C - port map(A => dwrite_1_iv_0, B => dwrite_4_sqmuxa, C => - dwrite_1_iv_1, Y => dstate_RNI1G47MJ(1)); - - \r.dstate_i_2_RNINR842[8]\ : OR2B - port map(A => un1_m0_2_58, B => miscdata_4_sqmuxa, Y => - \mmudco_m[59]\); - - \r.cctrl.burst\ : DFN1 - port map(D => burst_RNO_0, CLK => lclk_c, Q => \burst_0\); - - \r.mmctrl1.ctxp_RNI7PLC21[1]\ : OR3C - port map(A => \rdatav_0_1_1_iv_i_a2_6[3]\, B => N_3404, C - => N_3340, Y => N_3387_i_0); - - \r.dstate_0_RNIJAURF92[7]\ : AOI1B - port map(A => \dstate_ns_0_0_a2_0[1]\, B => N_3781, C => - \dstate_ns_0_0_0[1]\, Y => \dstate_ns_0_0_1[1]\); - - \dctrl.0.un1_dci_13_0\ : XNOR2 - port map(A => maddress(25), B => dataout_0(21), Y => - un1_dci_13_i); - - \r.flush_op_RNO\ : NOR3A - port map(A => rst, B => un2_m_tlb_type, C => \flush_op_i_0\, - Y => flush_op_RNO); - - \r.wb.addr_RNO_5[22]\ : OR2B - port map(A => un1_m0_2_23, B => addr_1_sqmuxa_0, Y => - N_3873); - - \dctrl.rdatav_0_1_0_iv[24]\ : NAND2 - port map(A => \mcdo_m_0[24]\, B => \rdatav_0_1_0_iv_5[24]\, - Y => data_0_24); - - \dctrl.mexc_1_m_0_a2_0_2_0\ : OR2 - port map(A => N_519, B => N_3091_3, Y => - mexc_1_m_0_a2_0_2_0); - - \r.wb.addr_RNO_0[4]\ : NOR3C - port map(A => \addr_1_1_iv_0_0[4]\, B => \addr_m[4]\, C => - \mmudco_m[6]\, Y => \addr_1_1_iv_0_2[4]\); - - \r.read_RNIOV4L7\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_22, Y => - \mcdo_m_i[22]\); - - \r.dstate_tr22_15_a2_15_0\ : OR2 - port map(A => asi(3), B => N_505, Y => - dstate_tr22_15_a2_15_0); - - \r.dstate_RNO_1[3]\ : NOR2B - port map(A => un1_m0_2_0_d0, B => \dstate[3]\, Y => N_3672); - - \r.wb.data2_RNI37OB[13]\ : OR2B - port map(A => \data2[13]\, B => rdatav_012_0, Y => - \data2_m[13]\); - - \r.mmctrl1.ctxp_RNIVLJ12[16]\ : OR2B - port map(A => \ctxp[16]\, B => N_3344_i_0, Y => - \ctxp_m[16]\); - - \r.mmctrl1.ctxp_RNIATS86[10]\ : NOR3C - port map(A => \mmudco_m[55]\, B => - \rdatav_0_1_0_iv_0_0[12]\, C => \ctxp_m[10]\, Y => - \rdatav_0_1_0_iv_0_2[12]\); - - \r.flush_0_1_RNIHVA8LK\ : NOR3B - port map(A => N_3322, B => \un1_p0_2_0[498]\, C => N_3248, - Y => N_184); - - \r.wb.addr_RNO[21]\ : AO1B - port map(A => un1_m0_2_96, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[21]\, Y => \addr_1[21]\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNIMS3C2\ : OR2A - port map(A => read_1, B => N_527, Y => N_608); - - \r.read_RNIQFOD21\ : OR3 - port map(A => \mcdo_m[4]\, B => \edata_m_0[4]\, C => - \ddatainv_0_1_1_iv_0[4]\, Y => read_RNIQFOD21); - - \r.dstate_RNIJ9IBG[1]\ : AOI1B - port map(A => dataout(20), B => \xaddress_RNI1CIE2_0[0]\, C - => \edata_m_i[20]\, Y => \ddatainv_0_1_0_iv_0[20]\); - - \r.mmctrl1.tlbdis_RNO_0\ : MX2 - port map(A => \tlbdis\, B => maddress(15), S => e_0_sqmuxa, - Y => N_2673); - - \r.mmctrl1.ctxp_RNI2MJ12[19]\ : OR2B - port map(A => \ctxp[19]\, B => N_3344_i_0, Y => - \ctxp_m[19]\); - - \r.wb.data2_RNIQBA74[20]\ : NOR3C - port map(A => \dcramo_m[116]\, B => \data2_m[20]\, C => - \mmudco_m[63]\, Y => \rdatav_0_1_0_iv_1[20]\); - - \r.dstate_RNI1HM61[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_0_26, Y => - \mcdo_m_0[26]\); - - \dctrl.twrite_14_iv_0_a2_a0_RNIGF1B4U2\ : AO1C - port map(A => N_3248, B => N_3322, C => N_2381, Y => N_296); - - \r.holdn_RNO_21\ : NOR3A - port map(A => holdn_0_sqmuxa_1_m8_0_a2_1, B => - cctrlwr19_2_0_a2_1_1, C => dcs_1_i_s_0_o2_0_RNIMMIH9, Y - => holdn_0_sqmuxa_1_m8_0_a2_3); - - \r.wb.data2_RNIOLJ16[22]\ : NOR3B - port map(A => \mmudco_m[65]\, B => \rdatav_0_1_0_iv_0[22]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_2[22]\); - - \un1_v.cctrlwr11_0\ : AO1C - port map(A => asi(0), B => N_3779, C => cctrlwr12, Y => - cctrlwr11_0); - - \r.paddress[8]\ : DFN1E1 - port map(D => un1_m0_2_9, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress_0[8]\); - - \r.paddress[27]\ : DFN1E1 - port map(D => N_293, CLK => lclk_c, E => paddress_1_sqmuxa, - Q => \paddress[27]\); - - \r.faddr_RNIB0UOO[2]\ : MX2 - port map(A => \taddr_7[7]\, B => \faddr[2]\, S => flush_0, - Y => faddr_RNIB0UOO(2)); - - \r.dstate_RNI9QJBG[1]\ : AOI1B - port map(A => \edata[22]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[246]\, Y => \ddatainv_0_1_0_iv_0[22]\); - - \r.xaddress[23]\ : DFN1E1 - port map(D => maddress(23), CLK => lclk_c, E => N_486, Q - => \addr[23]\); - - \r.mmctrl1.pso_RNO_0\ : MX2 - port map(A => pso, B => maddress(7), S => e_0_sqmuxa, Y => - N_2674); - - \r.wb.data2_RNI4S032[18]\ : NOR2B - port map(A => \data2_m[18]\, B => \dcramo_m[114]\, Y => - \rdatav_0_1_0_iv_0[18]\); - - \r.wb.data2[12]\ : DFN1E1 - port map(D => \data2_1[12]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[12]\); - - \r.wb.addr_RNO_5[3]\ : OR2B - port map(A => \un1_m0_2[79]\, B => addr_1_sqmuxa_2, Y => - N_294); - - \r.valid_0_RNO[4]\ : OA1B - port map(A => hit_1_iv_0_a2_0_0, B => twrite_14, C => - N_2364, Y => \valid_0_1[4]\); - - \r.size_RNI8H2U[1]\ : AO1B - port map(A => size_1_d0, B => N_3748, C => N_3766, Y => - ddatainv_0_6_sqmuxa); - - \r.dstate_RNIFHVNC[1]\ : MX2 - port map(A => maddress(10), B => edata2_0_iv(10), S => - edata_0_sqmuxa_i_0, Y => \edata[10]\); - - \r.dstate_i_0_RNI4GFP2[8]\ : AO1B - port map(A => N_3421, B => N_679, C => \vmask_0_5_1_0[4]\, - Y => \vmask_0_5[4]\); - - \r.read_RNIS71C7\ : NOR2B - port map(A => \N_425_0\, B => hrdata_0_12, Y => - \mcdo_m[12]\); - - \r.ready_RNO_0\ : OR2B - port map(A => \dstate_i_RNIF4S5B92[8]\, B => N_16828_tz, Y - => ready_RNO_0); - - \r.mmctrl1.ctxp[29]\ : DFN1E1 - port map(D => maddress(31), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[29]\); - - \r.dstate_RNO[6]\ : AOI1B - port map(A => N_3671, B => \dstate_RNO_1[6]\, C => rst, Y - => \dstate_nss[2]\); - - \r.dstate_i_0_RNITRO4892[8]\ : OR3A - port map(A => dstate_tr20_2, B => N_551, C => N_581_i, Y - => N_3069_i); - - \r.wb.size[0]\ : DFN1E0 - port map(D => N_653, CLK => lclk_c, E => - \dstate_RNI5GFM4[5]\, Q => \size_1[0]\); - - \r.wb.data2[29]\ : DFN1E1 - port map(D => \data2_1[29]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[29]\); - - \r.dstate_i_2_RNIAME21[8]\ : OR3A - port map(A => read_0, B => N_490, C => N_3758, Y => N_3685); - - \r.mmctrl1.ctx_0_0_RNIATOV1[0]\ : OR2B - port map(A => \ctx_0[0]\, B => miscdata_2_sqmuxa, Y => - \ctx_m[0]\); - - \r.dstate_RNISB0BG[1]\ : MX2 - port map(A => maddress(27), B => edata2_iv_i_0(27), S => - edata_0_sqmuxa_i, Y => \edata[27]\); - - \r.mmctrl1.ctxp[7]\ : DFN1E1 - port map(D => maddress(9), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[7]\); - - \r.holdn_RNO_3\ : OA1B - port map(A => un1_dci_12, B => d_m6_i_a3_1, C => - \dstate_i_0[8]\, Y => holdn_RNO_3); - - \r.dstate_RNIVP6I3_0[6]\ : NOR2B - port map(A => N_506, B => N_487, Y => N_3775); - - \r.dstate_i_RNIAGA5V92[8]\ : AO1C - port map(A => \N_121\, B => mexc_1_m_0_2000_0, C => - mexc_1_m_0_1, Y => mexc_1); - - \r.wb.data1[21]\ : DFN1E0 - port map(D => \data1_1[21]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_9); - - \r.holdn_RNO_9\ : AOI1B - port map(A => holdn_3_sqmuxa_0_0_2, B => N_3611, C => - holdn_0, Y => holdn_1); - - \r.mmctrl1.e_RNIL9MBLG3\ : NOR3B - port map(A => un1_m0_2_108, B => \e\, C => lock, Y => N_564); - - \dctrl.v.dstate34_i_o2_0\ : OR2B - port map(A => hold_0, B => eenaddr, Y => N_563); - - \r.xaddress_RNIEOTFII[25]\ : AO1 - port map(A => \addr[25]\, B => \N_330\, C => N_236, Y => - newtag_1_0_7); - - \r.mmctrl1.ctxp_RNID1T86[11]\ : NOR3C - port map(A => \mmudco_m[56]\, B => \rdatav_0_1_0_iv_0[13]\, - C => \ctxp_m[11]\, Y => \rdatav_0_1_0_iv_2[13]\); - - \r.dstate_i_1_RNI0LGRA92[8]\ : OR3C - port map(A => N_111, B => N_32, C => \N_3254_0\, Y => - N_3197); - - \r.paddress[1]\ : DFN1E1 - port map(D => un1_m0_2_2, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress_0[1]\); - - \r.mmctrl1.e_0_0_RNIJB6I3\ : NOR2B - port map(A => dstate_tr22_15_a2_2_m8_i_a5_1_0, B => N_3576, - Y => dstate_tr22_15_a2_2_m8_i_a5_1_1); - - \r.dstate_2_RNIH205M[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[27]\, B => - \rdatav_0_1_0_iv_2[27]\, C => \mcdo_m_0[27]\, Y => - data_0_27); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_0\ : OA1 - port map(A => N_512, B => N_519, C => asi(3), Y => - dcs_1_i_s_0_0); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0_RNIV8VH1[3]\ : AOI1B - port map(A => N_3661, B => N_3660, C => N_679, Y => - N_44_i_0); - - \r.wb.addr_RNO_3[19]\ : OR2B - port map(A => \address[19]\, B => N_514, Y => N_224); - - \r.dstate_i_RNINFEAO92[8]\ : NOR2A - port map(A => edata2_iv_i_0(26), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_90); - - \r.dstate_2_RNIOMNPG[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_23, Y => - mcdo_m_0_22); - - \r.vaddr_RNIBR8G[1]\ : MX2 - port map(A => maddress_0_0, B => \vaddr[1]\, S => - \dstate_i_1[8]\, Y => \un1_m0_2[77]\); - - \r.dstate_i_RNI7IS4E92[8]\ : MX2C - port map(A => N_547, B => N_487, S => \dstate_i[8]\, Y => - N_556); - - \r.wb.addr_RNO_6[26]\ : OR2B - port map(A => N_192, B => addr_1_sqmuxa, Y => - \mmudco_m[28]\); - - \r.flush_RNI7MOL2\ : NOR2 - port map(A => N_3595, B => flush_i, Y => un19_m_en_m_1); - - \un1_r.faddr_I_12\ : AND3 - port map(A => \faddr[0]\, B => \faddr[1]\, C => \faddr[2]\, - Y => N_17); - - \r.dstate_RNIGIR6[4]\ : OR2 - port map(A => \dstate_2[7]\, B => \dstate[4]\, Y => N_3833); - - \r.wb.data1_RNO_0[18]\ : MX2C - port map(A => edata2_0_iv(18), B => \data2[18]\, S => - N_3331_0, Y => N_2116); - - \r.wb.data2_RNO[30]\ : MX2 - port map(A => edata2_iv_i_0(30), B => hrdata_25, S => - \dstate_1[7]\, Y => \data2_1[30]\); - - \r.holdn_RNO_4\ : NOR3A - port map(A => holdn_0_sqmuxa_1_m8_0_a2_5, B => un1_dci_12, - C => accexc_6, Y => holdn_RNO_4); - - \r.dstate_i_RNIKVKHK92[8]\ : OR2A - port map(A => edata2_0_iv(17), B => \N_3254_0\, Y => - \dci_m[89]\); - - \r.wb.data1_RNO[28]\ : MX2A - port map(A => N_2126, B => maddress(28), S => - req_0_sqmuxa_1_0, Y => \data1_1[28]\); - - \r.wb.addr_RNO_5[21]\ : MX2 - port map(A => \paddress[21]\, B => \addr[21]\, S => N_484_0, - Y => N_552); - - \r.wb.size_RNI1RLD[0]\ : OR2B - port map(A => \size_1[1]\, B => \size_1[0]\, Y => size); - - \r.req_RNI9CCP1\ : OR2A - port map(A => ready, B => \req\, Y => N_72_i); - - \r.cctrl.dcs_RNO_1[1]\ : NOR3C - port map(A => \N_523\, B => \dcs[0]\, C => - \dcs_0_i_0_a2_0[1]\, Y => N_3664); - - \r.dstate_RNIFS6E51[1]\ : OR3 - port map(A => \edata_m[6]\, B => \dcramo_m[230]\, C => - \ddatainv_0_1_1_iv_1[6]\, Y => dstate_RNIFS6E51(1)); - - \r.wbinit_RNI2J1A3\ : OR2A - port map(A => wbinit, B => N_506, Y => dwrite_1_sqmuxa); - - \r.stpend_RNI07PA2\ : OR3B - port map(A => lock, B => N_485, C => read_1, Y => - stpend_RNI07PA2); - - \dctrl.mmudci_read_1_1_0_a2_0_0_0\ : NOR2A - port map(A => read_0, B => lock, Y => - mmudci_read_1_1_0_a2_0_0); - - \r.wb.addr_RNO_5[8]\ : OR2B - port map(A => \un1_m0_2[84]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[84]\); - - \r.wb.data1_RNO[6]\ : MX2A - port map(A => N_2104, B => maddress(6), S => req_0_sqmuxa_1, - Y => \data1_1[6]\); - - \r.mmctrl1.ctxp_RNIGTE32[0]\ : OR2B - port map(A => \ctxp[0]\, B => N_3344_i_0_0, Y => - \ctxp_m[0]\); - - \r.dstate_ns_0_0_a2_2[5]\ : NOR3A - port map(A => asi(4), B => asi(0), C => N_490, Y => N_3791); - - \r.dstate_i_2_RNI9SET1_0[8]\ : OR3A - port map(A => maddress_0_2, B => maddress(2), C => - rdatasel_0_sqmuxa_1, Y => rdatav_0_1_sqmuxa); - - \r.stpend_RNISIQ5F1\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_3, B => me_nullify2_1_2, - C => nullify2_0_sqmuxa, Y => vaddr_1_sqmuxa_0_a2_5); - - \r.dstate_i_2_RNI3RM12[8]\ : OR2B - port map(A => un1_m0_2_73, B => miscdata_4_sqmuxa, Y => - \mmudco_m[74]\); - - mmudci_fsread_1_sqmuxa_0_a2_0 : OR2A - port map(A => read_0, B => un30_m_en, Y => - \mmudci_fsread_1_sqmuxa_0_a2_0\); - - \r.dstate_i_RNII68N892_0[8]\ : OR2A - port map(A => tdiagwrite_1_0_0_o2_1, B => \N_121\, Y => - \dstate_i_RNII68N892_0[8]\); - - \r.dstate_i_2_RNISK8N1_28[8]\ : OR2B - port map(A => dataout_0(1), B => rdatasel_1_sqmuxa_1_0, Y - => N_3232); - - \r.dstate_tr16_10_0_i_o2_0_i\ : OR2B - port map(A => N_3586, B => N_595, Y => N_395); - - \r.dstate_i_0_RNIQA6JH92[8]\ : AO1C - port map(A => N_328, B => lock, C => req_2_sqmuxa_1_0, Y - => burst_2_sqmuxa_m8_0_0); - - \dctrl.twrite_14_iv_0_a2_a0_RNO_1\ : NOR3A - port map(A => tdiagwrite_1_0_0_o2_1, B => - vaddr_1_sqmuxa_0_a2_0, C => flush_i, Y => - twrite_14_iv_0_a2_a0_1); - - \r.mmctrl1.ctxp_RNIA69ED[28]\ : NOR3C - port map(A => \ctxp_m[28]\, B => \rdatav_0_1_0_iv_1[30]\, C - => \rdatav_0_1_0_iv_3[30]\, Y => \rdatav_0_1_0_iv_4[30]\); - - \r.flush_0_1_RNI6GU5992\ : OR2B - port map(A => maddress(12), B => \N_329\, Y => N_148); - - \r.flush2_RNIRVRLG\ : NOR3B - port map(A => setrepl_0_sqmuxa_1_m_i_5_2, B => - setrepl_0_sqmuxa_1_m_i_5_1, C => un1_eholdn_2, Y => - setrepl_0_sqmuxa_1_m_i_5_4); - - \r.dstate_RNI0P3L7_2[2]\ : AOI1B - port map(A => diagdata_20, B => \dstate[2]\, C => - \dcramo_m_0[244]\, Y => \rdatav_0_1_0_iv_3[20]\); - - \r.xaddress_RNO[6]\ : MX2 - port map(A => \addr[6]\, B => maddress(6), S => N_486_0, Y - => N_710); - - \r.dstate_RNIVRDN8[1]\ : MX2B - port map(A => maddress_0_2, B => edata2_0_iv(3), S => - edata_0_sqmuxa_i, Y => \edata[3]\); - - \r.cctrl.dcs_RNIELEH[1]\ : NOR2A - port map(A => \cache\, B => bo_d(2), Y => - twrite_11_m_0_a2_0_2); - - \r.cctrl.ics_RNIP4MU1[0]\ : OR2B - port map(A => \ics[0]\, B => rdatav_0_0_sqmuxa, Y => - \ics_m[0]\); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0_RNIV8VH1_0[3]\ : AO1 - port map(A => N_3661, B => N_3660, C => N_679, Y => N_348); - - \r.wb.data2_RNI67OB[16]\ : OR2B - port map(A => \data2[16]\, B => rdatav_012, Y => - \data2_m[16]\); - - \r.wb.data1_RNO[1]\ : MX2A - port map(A => N_2099, B => maddress_0_0, S => - req_0_sqmuxa_1_0, Y => \data1_1[1]\); - - \r.holdn_RNO_7\ : NOR2B - port map(A => N_3615, B => holdns_iv_0_0, Y => - holdns_iv_0_1); - - \r.wb.addr_RNO_0[18]\ : NOR3C - port map(A => N_187, B => \addr_1_1_iv_0_0[18]\, C => N_190, - Y => \addr_1_1_iv_0_2[18]\); - - \v.mmctrl1.ctxp_1_sqmuxa\ : AND2 - port map(A => e_0_sqmuxa_2, B => ctxp_1_sqmuxa_0, Y => - ctxp_1_sqmuxa); - - \r.nomds_RNIO3D071\ : MX2B - port map(A => enaddr, B => N_563, S => N_522, Y => N_162); - - \r.vaddr[23]\ : DFN1E1 - port map(D => maddress(23), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[23]\); - - \r.dstate_i_0_RNILKM24[8]\ : NOR3C - port map(A => \dstate_ns_i_a4_i_0[0]\, B => N_3685, C => - N_3677, Y => \dstate_ns_i_a4_i_2[0]\); - - \r.wb.data2_RNI60132[27]\ : AOI1B - port map(A => dataout_0(23), B => rdatasel_1_sqmuxa_1_0, C - => \data2_m[27]\, Y => \rdatav_0_1_0_iv_0[27]\); - - \r.wb.addr_RNO_5[0]\ : OR2B - port map(A => \un1_m0_2[76]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[76]\); - - \r.xaddress[17]\ : DFN1E1 - port map(D => maddress(17), CLK => lclk_c, E => N_486, Q - => \addr[17]\); - - \r.holdn_RNO_10\ : OR3 - port map(A => dcs_1_i_s_0_o2_0_RNIMMIH9, B => N_576, C => - holdn_RNO_20, Y => d_m6_i_a3_1); - - \r.vaddr_RNII2IC[28]\ : MX2 - port map(A => maddress(28), B => \vaddr[28]\, S => - \dstate_i_1[8]\, Y => \data[28]\); - - \r.dstate_RNIJA4E[6]\ : NOR2A - port map(A => \dstate_i_0[8]\, B => \dstate[6]\, Y => - dstate_17_1); - - \r.wb.addr_RNO_4[14]\ : MX2 - port map(A => \paddress[14]\, B => \addr[14]\, S => N_484_0, - Y => N_554); - - \r.holdn_RNILLEQ\ : NOR2A - port map(A => maddress(0), B => N_3763, Y => N_3785); - - \r.dstate_i[8]\ : DFN1 - port map(D => \dstate_nss_i_0[0]\, CLK => lclk_c, Q => - \dstate_i[8]\); - - \r.cctrl.ics[1]\ : DFN1 - port map(D => N_27, CLK => lclk_c, Q => \ics[1]\); - - \dctrl.0.un1_dci_16_0\ : XNOR2 - port map(A => dataout_0(24), B => maddress(28), Y => - un1_dci_16_i); - - \r.mmctrl1.ctxp_RNI4QJ12[28]\ : OR2B - port map(A => \ctxp[28]\, B => N_3344_i_0_0, Y => - \ctxp_m[28]\); - - \r.cctrl.dcs_RNI58EH[0]\ : NOR2A - port map(A => \dcs[0]\, B => N_496, Y => - \dstate_ns_i_a4_i_a2_16_0[0]\); - - \r.read_RNIQK3U8\ : NOR2B - port map(A => \N_425\, B => hrdata_0_11, Y => \mcdo_m[11]\); - - \r.dstate_i_RNINPT0O92[8]\ : OR2A - port map(A => edata2_iv_i_0(30), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_94); - - \dctrl.v.burst_16_m_RNO\ : NOR2 - port map(A => N_421, B => \addr[2]\, Y => burst_16_m_0); - - \r.wb.data1[3]\ : DFN1E0 - port map(D => N_19, CLK => lclk_c, E => data1_0_sqmuxa, Q - => data(3)); - - \r.hit_RNO\ : AO1 - port map(A => hit_1_iv_0_a2_0_3, B => N_495, C => hit_RNO_2, - Y => hit_1); - - \r.dstate_RNIB977A[1]\ : NOR2B - port map(A => \edata[5]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[5]\); - - \r.flush_0_1_RNI7KU5992\ : OR2B - port map(A => maddress(20), B => \N_329\, Y => N_157); - - \r.xaddress_RNIJH2O2_0[0]\ : NOR2B - port map(A => dataout(14), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[238]\); - - \r.wb.data1_RNO_1[5]\ : NOR2A - port map(A => req_0_sqmuxa_1, B => maddress(5), Y => N_3365); - - \r.wb.addr_RNO[26]\ : AO1B - port map(A => \mmudco_m_0[102]\, B => N_2701, C => - \addr_1_1_iv_2[26]\, Y => \addr_1[26]\); - - \r.wb.data2_RNIOV3M3[3]\ : NOR3C - port map(A => N_3400, B => N_3403, C => N_3401, Y => - \rdatav_0_1_1_iv_i_a2_1[3]\); - - \r.wb.addr_RNO_6[20]\ : MX2 - port map(A => \paddress[20]\, B => \addr[20]\, S => N_484, - Y => N_3842); - - \r.dstate_RNO[5]\ : AOI1B - port map(A => \dstate_ns_0_6[3]\, B => \dstate_ns_0_5[3]\, - C => rst, Y => \dstate_nss[3]\); - - \r.ready_RNIL4492\ : OR2B - port map(A => N_566, B => N_508, Y => burst_0_sqmuxa); - - \dctrl.0.un1_dci_14_0\ : XNOR2 - port map(A => dataout_0(22), B => maddress(26), Y => - un1_dci_14_i); - - \r.wb.addr_RNO_5[18]\ : OR2B - port map(A => un1_m0_2_19, B => addr_1_sqmuxa_0, Y => N_189); - - \r.dstate_i_2_RNI3KVJ1[8]\ : NOR3 - port map(A => N_223, B => N_3091_3, C => N_526, Y => - rdatasel_3_sqmuxa); - - \r.wb.data2_RNO[10]\ : MX2 - port map(A => edata2_0_iv(10), B => hrdata_0_10, S => - \dstate_0[7]\, Y => \data2_1[10]\); - - \r.ready_RNO_7\ : NOR2B - port map(A => asi(1), B => N_608, Y => ready_RNO_7); - - \r.dstate_i_2_RNISK8N1_15[8]\ : OR2B - port map(A => dataout_0(6), B => rdatasel_1_sqmuxa_1, Y => - \dcramo_m[102]\); - - \r.xaddress_RNID252J1[10]\ : NOR3 - port map(A => N_3298, B => N_3297, C => \address_i_0[8]\, Y - => xaddress_RNID252J1(10)); - - \r.wb.addr_RNO_1[14]\ : OR2B - port map(A => maddress(14), B => addr_2_sqmuxa_0, Y => - N_3636); - - \r.dstate_RNII450C[1]\ : MX2 - port map(A => maddress(8), B => edata2_0_iv(8), S => - edata_0_sqmuxa_i, Y => \dstate_RNII450C[1]\); - - \r.dstate_0_RNI1JGE7_6[2]\ : AOI1B - port map(A => diagdata_17, B => \dstate_0[2]\, C => - \dcramo_m_0[241]\, Y => \rdatav_0_1_1_iv_5[17]\); - - \r.wb.addr_RNO_6[22]\ : MX2 - port map(A => \paddress[22]\, B => \addr[22]\, S => N_484_0, - Y => N_3840); - - \r.dstate_RNIBGU46[2]\ : NOR2B - port map(A => dataout(5), B => rdatav_0_6_sqmuxa_3, Y => - N_3338); - - \r.wb.data2[13]\ : DFN1E1 - port map(D => \data2_1[13]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[13]\); - - \r.wb.addr[5]\ : DFN1 - port map(D => \addr_1[5]\, CLK => lclk_c, Q => \address[5]\); - - \r.dstate_RNO_2[6]\ : AOI1B - port map(A => \dstate_ns_0_0_o2_0[1]\, B => N_3746, C => - \e_0\, Y => \dstate_ns_0_0_a2_0[2]\); - - \r.flush_op_RNI1CME892\ : OA1C - port map(A => cctrlwr13, B => N_3790, C => flush_op, Y => - \flush_op_i_0\); - - \r.cctrl.ics_RNO_3[1]\ : NOR2B - port map(A => ifrz, B => \ics[0]\, Y => \ics_0_i_a4_1_0[1]\); - - \r.holdn_RNI9UQO3\ : AO1B - port map(A => dstate_17_2, B => dstate_17_1, C => \hold\, Y - => N_3665_1); - - \r.dstate_i_2_RNIA9PN1[8]\ : NOR2 - port map(A => maddress(3), B => rdatasel_0_sqmuxa_1, Y => - rdatav_0_0_sqmuxa); - - \r.wb.addr_RNO[20]\ : AO1B - port map(A => un1_m0_2_95, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[20]\, Y => \addr_1[20]\); - - \r.dstate_tr22_15_a2_14_1_0\ : NOR2 - port map(A => asi(0), B => asi(1), Y => - dstate_tr22_15_a2_14_1_0); - - \dctrl.0.un1_dci_NE_9\ : XA1A - port map(A => maddress(16), B => dataout_0(12), C => - un1_dci_9_i, Y => un1_dci_NE_9); - - \r.wb.addr_RNO_0[0]\ : AOI1B - port map(A => \address[0]\, B => dstate_19, C => - \addr_1_1_iv_0[0]\, Y => \addr_1_1_iv_1[0]\); - - \r.wb.addr[0]\ : DFN1 - port map(D => \addr_1[0]\, CLK => lclk_c, Q => \address[0]\); - - \r.read_RNIDG9BF\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_21, Y => - \mcdo_m_i[21]\); - - \r.holdn_RNO_12\ : OR3B - port map(A => N_60, B => \dstate[4]\, C => N_580, Y => - holdn_1_sqmuxa); - - \r.wb.data1_RNO[31]\ : MX2A - port map(A => N_2129, B => maddress(31), S => - req_0_sqmuxa_1, Y => \data1_1[31]\); - - \r.vaddr[17]\ : DFN1E1 - port map(D => maddress(17), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[17]\); - - \dctrl.v.wb.addr_1_1_iv_0[10]\ : NAND2 - port map(A => N_3723, B => \addr_1_1_iv_0_3[10]\, Y => - \addr_1[10]\); - - \dctrl.0.un1_dci_5_0_RNID777\ : AND2 - port map(A => un1_dci_5_i, B => N_139_i_i, Y => - un1_dci_NE_3); - - \dctrl.v.burst_16_m_RNILVFJ6\ : NOR3C - port map(A => burst_16_m, B => un116_m_en_m, C => - burst_19_m, Y => burst_1_iv_2_1); - - \r.wb.addr_RNO_0[17]\ : NOR3C - port map(A => N_3640, B => \addr_1_1_iv_0_0[17]\, C => - N_3721, Y => \addr_1_1_iv_0_2[17]\); - - \r.mmctrl1.ctx_0_0[2]\ : DFN1 - port map(D => \ctx_RNIFGBR[2]\, CLK => lclk_c, Q => - \ctx_0[2]\); - - \r.dstate_RNIHILB6_0[7]\ : OR2B - port map(A => dataout_0(31), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[255]\); - - \dctrl.0.un1_dci_15_0\ : XNOR2 - port map(A => dataout_0(23), B => maddress(27), Y => - un1_dci_15_i); - - \r.flush_op\ : DFN1 - port map(D => flush_op_RNO, CLK => lclk_c, Q => flush_op); - - \r.xaddress_RNIQF6M2_1[0]\ : OR2B - port map(A => dataout(26), B => N_2088, Y => - \dcramo_m_i[250]\); - - \r.flush2_RNIHI3F73\ : OR2A - port map(A => hit_1_iv_0_a2_0_0, B => twrite_14, Y => N_182); - - \r.dstate_RNO_1[4]\ : OR3B - port map(A => un1_m0_2_108, B => dstate_tr16_10_0_i_2, C - => lock, Y => N_3494); - - \r.valid_0_RNO_0[7]\ : OR2 - port map(A => N_3286_1, B => N_3246, Y => N_3285); - - \r.xaddress_RNO_0[2]\ : MX2B - port map(A => N_670, B => \addr[2]\, S => \dstate_i[8]\, Y - => N_652_i); - - \r.dstate_i_RNICP4M4[8]\ : MX2 - port map(A => \vmask_0_4[6]\, B => N_2026, S => - \dstate_i[8]\, Y => \vmask_0_5[6]\); - - \r.cache_RNO_4\ : MX2C - port map(A => cache_1_0_0_0, B => un47_m_en, S => N_3836, Y - => cache_1); - - \r.read_RNI5R3ND\ : NOR2B - port map(A => \N_425_0\, B => hrdata_1, Y => \mcdo_m[6]\); - - \dctrl.twrite_14_iv_0_a2_a0_RNIQKKTDU2\ : AO1C - port map(A => N_3248, B => N_3322, C => N_2385, Y => N_298); - - \r.wb.addr_RNO[14]\ : AO1B - port map(A => N_695, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_0_2[14]\, Y => \addr_1[14]\); - - \r.vaddr_RNI36EE[8]\ : MX2 - port map(A => maddress(8), B => \vaddr[8]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[84]\); - - \v.burst_2_sqmuxa_m8_0_a4_0\ : AND2 - port map(A => burst_2_sqmuxa_m3_e, B => - burst_2_sqmuxa_m8_0_a4_0_2, Y => burst_2_sqmuxa_m8_0_a4_0); - - \r.wb.addr_RNO_2[14]\ : AOI1B - port map(A => N_2165_0, B => N_554, C => N_3729, Y => - \addr_1_1_iv_0_0[14]\); - - \r.size_RNI7099[0]\ : OR3B - port map(A => \size_0[1]\, B => \size[0]\, C => read, Y => - N_3747); - - \r.holdn_RNID0UG\ : OR2A - port map(A => N_3748, B => size_1_d0, Y => N_3757); - - \r.dstate_RNI7IF44[4]\ : OR2A - port map(A => burst_19_m_0, B => holdn_2_sqmuxa, Y => - burst_19_m); - - \r.wb.data1_RNO[24]\ : MX2A - port map(A => N_2122, B => maddress(24), S => - req_0_sqmuxa_1_0, Y => \data1_1[24]\); - - \r.wb.addr_RNO_0[24]\ : NOR3C - port map(A => N_3634, B => \addr_1_1_iv_0_0[24]\, C => - N_3739, Y => \addr_1_1_iv_0_2[24]\); - - \r.dstate_RNII69VC[1]\ : AO1 - port map(A => dataout(4), B => \xaddress_RNIQDEG2_0[0]\, C - => \edata_m[4]\, Y => \ddatainv_0_1_1_iv_0[4]\); - - \rdatasel_1_i_a5_0_0_a2_1[7]\ : NOR2 - port map(A => N_505, B => N_459, Y => N_206_1); - - \r.xaddress_RNIQ0B62[3]\ : NOR2 - port map(A => dataout_0(6), B => N_3244_i_0, Y => - \vmask_0_4[6]\); - - \r.stpend_RNIUDDF6_0\ : NOR2B - port map(A => stpend_0_sqmuxa, B => \dstate_RNI5GFM4[5]\, Y - => data1_0_sqmuxa); - - \dctrl.0.un1_dci_2_0_RNISLRJ2\ : OR2B - port map(A => un1_dci_NE_17, B => un1_dci_NE_16, Y => - un1_dci_NE); - - \v.burst_2_sqmuxa_m3_e\ : NAND2 - port map(A => burst_2_sqmuxa_m3_e_RNO, B => G_80_0, Y => - burst_2_sqmuxa_m3_e); - - \r.xaddress_RNIUVU9992[14]\ : OR2B - port map(A => \addr[14]\, B => \N_330\, Y => N_237); - - \r.xaddress[14]\ : DFN1E1 - port map(D => maddress(14), CLK => lclk_c, E => N_486, Q - => \addr[14]\); - - \r.wb.data2_RNI1S032[15]\ : AOI1B - port map(A => \data2[15]\, B => rdatav_012_0, C => N_204, Y - => \rdatav_0_1_0_iv_0_0[15]\); - - \r.dstate_i_2_RNII5MM2[8]\ : OR2B - port map(A => dstate_tr22_15_a2_9_0, B => N_395, Y => - N_3576); - - \r.wb.data1_RNO_0[27]\ : MX2C - port map(A => edata2_iv_i_0(27), B => \data2[27]\, S => - N_3331, Y => N_2125); - - \r.wb.data1_RNO_0[11]\ : MX2C - port map(A => edata2_0_iv(11), B => \data2[11]\, S => - N_3331, Y => N_2109); - - \r.wb.data2_RNIV05V5[7]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_0_0[7]\, B => N_3302, C => - N_3311, Y => \rdatav_0_1_1_iv_0_2[7]\); - - \r.nomds_RNIA0RVJ\ : NOR3B - port map(A => setrepl_0_sqmuxa_1_m_i_5_4, B => - twrite_14_iv_0_o2_a1_1, C => mexc, Y => - twrite_14_iv_0_o2_a1_2); - - \r.wb.addr_RNO_5[17]\ : OR2B - port map(A => un1_m0_2_18, B => addr_1_sqmuxa_0, Y => - N_3722); - - \r.dstate_RNI5ED76_0[1]\ : OR3B - port map(A => data2_0_sqmuxa_1, B => holdn_2_sqmuxa, C => - mexc_0_sqmuxa_0, Y => mexc_0_sqmuxa_0_0); - - \r.vaddr_RNICMHC[25]\ : MX2 - port map(A => maddress(25), B => \vaddr[25]\, S => - \dstate_i_1[8]\, Y => data(25)); - - \r.vaddr[7]\ : DFN1E1 - port map(D => maddress(7), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[7]\); - - \r.dstate_RNI5UPJ2[5]\ : AND2 - port map(A => data2_1_sqmuxa, B => N_3151, Y => - burst_1_sqmuxa_0); - - \r.wb.addr_RNO_1[26]\ : NOR3C - port map(A => \dci_m[34]\, B => \addr_1_1_iv_0[26]\, C => - \addr_m[26]\, Y => \addr_1_1_iv_2[26]\); - - \r.holdn_RNO_25\ : OR3B - port map(A => N_510, B => \dstate_2[7]\, C => N_3588, Y => - N_3614); - - \r.dstate_i_2_RNISK8N1[8]\ : OR2B - port map(A => dataout(34), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[414]\); - - \r.xaddress_RNO[11]\ : MX2 - port map(A => \addr[11]\, B => maddress(11), S => N_486_0, - Y => N_713); - - \r.wb.data1[27]\ : DFN1E0 - port map(D => \data1_1[27]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_15); - - \r.mmctrl1wr_RNIBK68\ : AND2 - port map(A => \addr[8]\, B => mmctrl1wr, Y => - ctxp_1_sqmuxa_0); - - \r.dstate_RNO_1[5]\ : NOR3C - port map(A => N_3028, B => \dstate_ns_0_2_0[3]\, C => - \dstate_ns_0_3[3]\, Y => \dstate_ns_0_5[3]\); - - \r.dstate_i_RNIKNRVF91[8]\ : OR2B - port map(A => N_3835, B => \dstate_i_RNID1NU1[8]\, Y => - N_304); - - \r.dstate_RNIPCRK8[1]\ : MX2B - port map(A => maddress(5), B => edata2_0_iv(5), S => - edata_0_sqmuxa_i_0, Y => \edata[5]\); - - \r.dstate_i_2_RNI1EFJ1[8]\ : OA1C - port map(A => N_206_1, B => N_526, C => rdatav_012_0, Y => - rdatav_0_6_sqmuxa_3_1); - - \r.wb.data2_RNIRB4M3[6]\ : NOR3C - port map(A => \dcramo_m[414]\, B => \data2_m[6]\, C => - \dcramo_m[102]\, Y => \rdatav_0_1_1_iv_1[6]\); - - \r.dstate_2_RNILP1MF[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_1, Y => - \mcdo_m_0[1]\); - - \r.size_RNIDM4B2[0]\ : OR2 - port map(A => data2_0_sqmuxa_1, B => N_421, Y => - un116_m_en_m); - - \r.mmctrl1.ctxp_RNIOTF32[8]\ : OR2B - port map(A => \ctxp[8]\, B => N_3344_i_0, Y => N_167); - - \r.flush_0_1_RNIOMB27S2\ : AO1B - port map(A => maddress(19), B => \N_329\, C => - \newtag_1_0[19]\, Y => flush_0_1_RNIOMB27S2); - - \r.dstate_i_2_RNI3KVJ1_0[8]\ : OR2A - port map(A => N_227, B => N_526, Y => rdatasel_0_sqmuxa_1); - - \un1_r.dstate_25_0_o2_0\ : OR2A - port map(A => asi(2), B => asi(0), Y => N_512); - - \r.xaddress_RNIPQFG1[0]\ : AO1C - port map(A => maddress(1), B => N_3785, C => N_3623, Y => - ddatainv_0_1_sqmuxa); - - \r.read_RNIFPFT31\ : OR3 - port map(A => \mcdo_m[5]\, B => \edata_m_0[5]\, C => - \ddatainv_0_1_1_iv_0[5]\, Y => read_RNIFPFT31); - - \dctrl.vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\ : AO1B - port map(A => N_3654, B => N_3653, C => N_679, Y => - \vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\); - - \r.wb.data1_RNO_0[12]\ : MX2C - port map(A => edata2_0_iv(12), B => \data2[12]\, S => - N_3331_0, Y => N_2110); - - \r.cctrl.ics_RNO[1]\ : NOR3 - port map(A => N_3203, B => N_3204, C => \ics_0_i_0[1]\, Y - => N_27); - - \r.xaddress_RNILHOK61[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[26]\, B => - \mcdo_m_i[26]\, C => \ddatainv_0_1_0_iv_1[26]\, Y => - xaddress_RNILHOK61(1)); - - \r.wb.data1_RNO[21]\ : MX2A - port map(A => N_2119, B => maddress(21), S => - req_0_sqmuxa_1, Y => \data1_1[21]\); - - \r.wb.data2_RNO[18]\ : MX2 - port map(A => edata2_0_iv(18), B => hrdata_0_18, S => - \dstate_0[7]\, Y => \data2_1[18]\); - - \dctrl.v.cctrlwr4_0_a2_0_0_a2_0\ : OR2A - port map(A => asi(0), B => N_519, Y => N_3798); - - \r.flush_RNIRA645\ : NOR3B - port map(A => tdiagwrite_1_0_0_o2_1, B => - twrite_14_iv_0_a2_a1_0, C => flush_i, Y => - twrite_14_iv_0_a2_a1_2); - - \r.xaddress_RNI24RK4[6]\ : MX2C - port map(A => maddress(6), B => \addr[6]\, S => - un1_taddr_1_sqmuxa, Y => N_2233); - - \r.xaddress_RNI1Q9ST1[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[24]\, B => - \mcdo_m_i[24]\, C => \ddatainv_0_1_0_iv_1[24]\, Y => - xaddress_RNI1Q9ST1(1)); - - \r.hit_RNO_1\ : NOR2A - port map(A => hit_1_iv_0_a2_0_2, B => un1_dci_NE, Y => - hit_1_iv_0_a2_0_3); - - \r.xaddress_RNITFTTE[3]\ : MX2C - port map(A => N_2230, B => eaddress_1, S => taddr_2_sqmuxa, - Y => xaddress_RNITFTTE(3)); - - \r.mmctrl1.ctx_0_0_RNIVLMQ5[3]\ : AOI1 - port map(A => \ctx_0[3]\, B => miscdata_2_sqmuxa, C => - \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_i_a2_4[3]\); - - \r.dstate_2_RNIE3VV21[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_i_a4_6[1]\, B => - \ico_m[135]\, C => \mcdo_m_0[1]\, Y => N_3227_i_0); - - \r.dstate_RNI5ED76[1]\ : OR3B - port map(A => data2_0_sqmuxa_1, B => holdn_2_sqmuxa, C => - mexc_0_sqmuxa_0, Y => \dstate_RNI5ED76[1]\); - - \r.xaddress_RNIB6DSTI[19]\ : OA1A - port map(A => edata2_0_iv(19), B => \N_3254_0\, C => N_3875, - Y => \newtag_1_0[19]\); - - \r.xaddress_RNI10232[3]\ : AOI1B - port map(A => N_3808, B => N_3800, C => N_679, Y => - N_3244_i_0); - - \r.wb.data2[15]\ : DFN1E1 - port map(D => \data2_1[15]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[15]\); - - \un1_v.cctrlwr19_2_0_o2_1\ : OR3B - port map(A => asi(2), B => asi(3), C => asi(4), Y => N_533); - - \r.size_RNIQO6E[1]\ : NOR3B - port map(A => N_3749, B => \addr[1]\, C => \size_0[1]\, Y - => N_3768); - - \r.wb.addr_RNO_3[4]\ : OR2B - port map(A => un1_m0_2_5, B => addr_1_sqmuxa, Y => - \mmudco_m[6]\); - - \r.dstate_ns_0_2065_tz_tz\ : NOR2B - port map(A => N_3569_2, B => N_666, Y => N_16887_tz_tz); - - \r.dstate_i_RNIDOO0HI[8]\ : OA1A - port map(A => maddress(22), B => \N_523\, C => - flush_1_sqmuxa, Y => flush_1_i_0); - - \r.mmctrl1.e_RNI1TEJ1\ : NOR3B - port map(A => N_3755, B => e_RNIKN3D, C => - dstate_tr8_2_8_0_a2_1_a2_0, Y => N_2996_8); - - \r.wb.addr_RNO_0[13]\ : NOR3C - port map(A => N_272, B => \addr_1_1_iv_0_0[13]\, C => N_275, - Y => \addr_1_1_iv_0_2[13]\); - - \r.wb.addr_RNO_7[2]\ : OR2A - port map(A => ready, B => size, Y => N_323); - - \r.dstate_RNIV0IM2_0[5]\ : NOR2A - port map(A => N_566, B => dstate_14, Y => req_0_sqmuxa_1); - - \r.dstate_0_RNI1JGE7_0[2]\ : AOI1B - port map(A => diagdata_9, B => \dstate_0[2]\, C => - \dcramo_m_0[233]\, Y => \rdatav_0_1_0_iv_3[9]\); - - \r.xaddress_RNIISBI1[0]\ : OR2B - port map(A => N_3598, B => N_727, Y => ddatainv_0_3_sqmuxa); - - \r.xaddress[27]\ : DFN1E1 - port map(D => maddress(27), CLK => lclk_c, E => N_486, Q - => \addr[27]\); - - \r.wb.data1_RNO_0[30]\ : MX2C - port map(A => edata2_iv_i_0(30), B => \data2[30]\, S => - N_3331, Y => N_2128); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0_RNIO98L1[3]\ : NOR2 - port map(A => dataout_0(7), B => N_44_i_0, Y => - \vmask_0_4[7]\); - - \dctrl.v.cctrlwr12_0_a2\ : OR3A - port map(A => asi(4), B => N_3595, C => N_2938_2, Y => - cctrlwr12); - - \r.nomds_RNIC4SS692\ : OR2A - port map(A => un1_dci_12_0, B => nullify, Y => un1_dci_12); - - \v.mmctrl1.ctxp_1_sqmuxa_0_0\ : AND2 - port map(A => e_0_sqmuxa_2, B => ctxp_1_sqmuxa_0, Y => - ctxp_1_sqmuxa_0_0); - - \r.mmctrl1.e_0_0_RNI3LED1\ : NOR2A - port map(A => N_3755, B => dstate_tr8_5_9_0_a2_0_a2_0, Y - => N_3002_9); - - \r.dstate_RNIVP6I3[6]\ : OR2A - port map(A => N_487, B => N_580, Y => mexc_0_sqmuxa_1); - - \r.dstate_i_2_RNISK8N1_24[8]\ : OR2B - port map(A => dataout_0(16), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[116]\); - - \r.dstate_i_2_RNISK8N1_11[8]\ : OR2B - port map(A => dataout_0(15), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[115]\); - - \r.dstate_RNILC7J1[3]\ : OR2A - port map(A => \dstate[3]\, B => un1_m0_2_0_d0, Y => - dstate_0_sqmuxa); - - \r.dstate_RNI26UQ[1]\ : OR3B - port map(A => edata_0_sqmuxa_1, B => N_3443_i, C => - \dstate[1]\, Y => edata_0_sqmuxa_i_0); - - \r.dlock\ : DFN1E1 - port map(D => lock, CLK => lclk_c, E => N_486_0, Q => dlock); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNI75A73\ : NOR3B - port map(A => N_481, B => asi(3), C => N_608, Y => N_3610); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_20\ : NOR3B - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_11, B => - vaddr_1_sqmuxa_0_a2_4_m1_e_16, C => eaddress_28, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_20); - - \r.mmctrl1.e\ : DFN1 - port map(D => e_0_sqmuxa_RNIQKNL, CLK => lclk_c, Q => \e\); - - \r.dstate_RNII7B5A[1]\ : NOR2B - port map(A => \edata[5]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[5]\); - - \r.wb.data2[7]\ : DFN1E1 - port map(D => \data2_1[7]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[7]\); - - \r.asi_RNIQTPH[2]\ : OR3B - port map(A => \asi_0[3]\, B => \dcs[1]\, C => \asi_0[2]\, Y - => N_3845); - - \r.mmctrl1.ctx_0_0_RNILD4N[1]\ : MX2 - port map(A => \ctx_0[1]\, B => maddress_0_0, S => - ctx_1_sqmuxa, Y => N_2664); - - \r.dstate_i_RNI6E3LA92[8]\ : OR3C - port map(A => \vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\, B => - N_110, C => \N_3254_0\, Y => N_130); - - \r.dstate_i_2_RNI1HQB[8]\ : NOR2 - port map(A => read_1, B => \dstate_i_2[8]\, Y => N_3745); - - \r.wb.read_RNO\ : MX2 - port map(A => read_1, B => read, S => \dstate_i[8]\, Y => - N_419_0); - - \r.wb.addr[8]\ : DFN1 - port map(D => \addr_1[8]\, CLK => lclk_c, Q => \address[8]\); - - \r.wb.addr[2]\ : DFN1 - port map(D => \addr_1[2]\, CLK => lclk_c, Q => \address[2]\); - - \r.dstate_RNO_7[1]\ : OR3 - port map(A => dstate_tr22_15_a2_1, B => - dstate_tr22_15_m8_i_a5_0_0, C => N_3787, Y => - dstate_tr22_15_N_10_i); - - \dctrl.hit_1_i_a2_0_a2_0\ : NOR2A - port map(A => asi(4), B => N_512, Y => N_3780); - - \r.dstate_RNI35VL5[4]\ : OR2B - port map(A => data2_0_sqmuxa_1, B => holdn_2_sqmuxa, Y => - holdn_1_5); - - \r.xaddress_RNIV7L4O[1]\ : AOI1B - port map(A => \edata[11]\, B => ddatainv_0_4_sqmuxa, C => - \edata_m_4_i[3]\, Y => \ddatainv_0_1_0_iv_1[27]\); - - \r.wb.addr_RNO_0[15]\ : OA1 - port map(A => \data[15]\, B => N_2709_i_0, C => - addr_1_sqmuxa_2_0, Y => \mmudco_m_0[91]\); - - \r.read_RNI7G7G41\ : OR3 - port map(A => \mcdo_m[11]\, B => \edata_m_1[3]\, C => - \ddatainv_0_1_1_iv_0[11]\, Y => read_RNI7G7G41); - - \r.dstate_i_RNI0GBDG92[8]\ : OR2A - port map(A => edata2_0_iv(5), B => \N_3254_0\, Y => N_131); - - \r.burst_RNO_5\ : OA1C - port map(A => un1_m0_2_108, B => lock, C => - burst_1_m8_i_o5_0, Y => burst_1_N_7); - - \r.dstate_RNIR2CO3[4]\ : OR2A - port map(A => twrite_14_iv_0_o4_0_o2_0, B => N_580, Y => - \dstate_RNIR2CO3[4]\); - - \r.wb.addr[28]\ : DFN1 - port map(D => \addr_1[28]\, CLK => lclk_c, Q => - \address[28]\); - - \r.wb.addr_RNO_5[13]\ : OR2B - port map(A => N_2887, B => addr_1_sqmuxa, Y => N_273); - - \r.mmctrl1.e_RNI92T4J\ : OR3C - port map(A => N_495, B => \dstate_ns_i_a4_i_a2_3_2[0]\, C - => N_3814, Y => N_3680_i); - - \r.mmctrl1.ctx_RNIAM7T[3]\ : NOR2B - port map(A => rst, B => N_2666, Y => \ctx_RNIAM7T[3]\); - - \r.dstate_0_RNI2DT77_4[2]\ : AND2 - port map(A => \ico_m[162]\, B => \dcramo_m_0[252]\, Y => - \rdatav_0_1_1_iv_5[28]\); - - \r.vaddr[8]\ : DFN1E1 - port map(D => maddress(8), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[8]\); - - \r.dstate_RNO_7[4]\ : OA1A - port map(A => dstate_ns_0_2064_1, B => N_3511, C => N_3181, - Y => \dstate_ns_0_0[4]\); - - \dctrl.0.un1_dci_10_0\ : XNOR2 - port map(A => dataout_0(18), B => maddress(22), Y => - un1_dci_10_i); - - \r.wb.data2_RNO[26]\ : MX2 - port map(A => edata2_iv_i_0(26), B => hrdata_0_26, S => - \dstate_1[7]\, Y => \data2_1[26]\); - - \r.wb.data1[31]\ : DFN1E0 - port map(D => \data1_1[31]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_19); - - \r.dstate_i_0_RNID0P84_1[8]\ : NOR3 - port map(A => un18_m_en, B => \dstate_i_0[8]\, C => N_328, - Y => addr_1_sqmuxa_2_0); - - \r.wb.addr_RNO_1[20]\ : OR2B - port map(A => maddress(20), B => addr_2_sqmuxa_0, Y => - N_3860); - - \r.wb.addr[18]\ : DFN1 - port map(D => \addr_1[18]\, CLK => lclk_c, Q => - \address[18]\); - - \r.wb.data2_RNIQ74M3[5]\ : AOI1B - port map(A => dataout_0(5), B => rdatasel_1_sqmuxa_1_0, C - => \rdatav_0_1_1_iv_i_a2_0[5]\, Y => - \rdatav_0_1_1_iv_i_a2_1[5]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m7_i_a4\ : AO1C - port map(A => eaddress_29, B => - \vaddr_1_sqmuxa_0_a2_4_m1_e_24\, C => un17_casaen_0_0, Y - => vaddr_1_sqmuxa_0_a2_4_m7_i_a4); - - \r.wb.data2_RNIABOB[27]\ : OR2B - port map(A => \data2[27]\, B => rdatav_012_0, Y => - \data2_m[27]\); - - \r.wb.addr_RNO[1]\ : AO1B - port map(A => maddress_0_0, B => N_2164, C => - \addr_1_1_iv_2[1]\, Y => \addr_1[1]\); - - \r.dstate_i_0_RNI15JQ8[8]\ : NOR3 - port map(A => un47_m_en, B => vaddr_1_sqmuxa_0_a2_0, C => - un1_eholdn_2, Y => vaddr_1_sqmuxa_0_a2_1); - - \dctrl.un17_m_en\ : OR2B - port map(A => hold_0, B => enaddr, Y => un17_m_en); - - \r.stpend_RNIB3GJE\ : NOR3C - port map(A => dcs_1_i_s_0_o2_0_RNIAN3E3, B => - vaddr_1_sqmuxa_0_a2_1, C => stpend_RNI07PA2, Y => - vaddr_1_sqmuxa_0_a2_3); - - \r.dstate_tr16_10_0_i_o2_0_i_a2\ : AO1A - port map(A => N_3572, B => N_590, C => asi(3), Y => N_3586); - - \r.mmctrl1.ctx_0_0_RNIQBN6[1]\ : NOR2A - port map(A => \ctx_0[1]\, B => maddress(8), Y => - \rdatav_0_1_0_iv_i_a2_2_0[1]\); - - \r.dstate_RNIL46AH[1]\ : AO1 - port map(A => \edata[11]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[235]\, Y => \ddatainv_0_1_1_iv_0[11]\); - - \r.wb.data2_RNIVR032[13]\ : AOI1B - port map(A => dataout_0(9), B => rdatasel_1_sqmuxa_1_0, C - => \data2_m[13]\, Y => \rdatav_0_1_0_iv_0[13]\); - - \r.xaddress_RNISVU9992[12]\ : OR2B - port map(A => \addr[12]\, B => \N_330\, Y => N_146); - - \r.xaddress_RNI9MB27S2[23]\ : AO1B - port map(A => maddress(23), B => \N_329\, C => - \newtag_1_0[23]\, Y => xaddress_RNI9MB27S2(23)); - - \r.wb.data2_RNO[31]\ : MX2 - port map(A => edata2_iv_i_0(31), B => hrdata_26, S => - \dstate_1[7]\, Y => \data2_1[31]\); - - \r.wb.addr_RNO_1[22]\ : OR2B - port map(A => maddress(22), B => addr_2_sqmuxa_0, Y => - N_3871); - - \r.wb.data1_RNO_0[24]\ : MX2C - port map(A => edata2_iv_i_0(24), B => \data2[24]\, S => - N_3331_0, Y => N_2122); - - \r.dstate_RNIHILB6_5[7]\ : OR2B - port map(A => dataout(19), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[243]\); - - GND_i : GND - port map(Y => \GND\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNIAN3E3\ : OR2A - port map(A => read_1, B => N_102, Y => - dcs_1_i_s_0_o2_0_RNIAN3E3); - - \r.wb.addr_RNO_5[15]\ : MX2 - port map(A => \paddress[15]\, B => \addr[15]\, S => N_484, - Y => N_673); - - \r.mmctrl1.ctxp[18]\ : DFN1E1 - port map(D => maddress(20), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[18]\); - - \r.mmctrl1.ctxp_RNIMKK2V[5]\ : OR3C - port map(A => \rdatav_0_1_1_iv_0_6[7]\, B => - \rdatav_0_1_1_iv_0_5[7]\, C => N_3313, Y => data_0_7); - - \r.cache_RNO_6\ : AO1D - port map(A => \dstate[4]\, B => cache_1_0_a3_0_0, C => - un1_m0_2_33, Y => cache_1_0_0_0); - - \dctrl.v.cctrlwr4_0_a2_1_o2\ : OR3A - port map(A => asi(2), B => asi(4), C => N_490, Y => N_551); - - \r.xaddress[7]\ : DFN1 - port map(D => N_712, CLK => lclk_c, Q => \addr[7]\); - - \r.vaddr_RNIJ5DE[0]\ : MX2 - port map(A => maddress(0), B => \vaddr[0]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[76]\); - - \r.dstate_RNIUEDLD[1]\ : NAND2 - port map(A => ddatainv_0_6_sqmuxa, B => \edata[18]\, Y => - \edata_m_i[18]\); - - \r.dstate_RNIHILB6_6[7]\ : OR2B - port map(A => dataout(18), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[242]\); - - \r.dstate_i_2_RNISK8N1_17[8]\ : OR2B - port map(A => dataout_0(2), B => rdatasel_1_sqmuxa_1, Y => - \dcramo_m[98]\); - - \r.asi[0]\ : DFN1E1 - port map(D => asi(0), CLK => lclk_c, E => N_486_0, Q => - \asi_0[0]\); - - \r.wb.addr[7]\ : DFN1 - port map(D => \addr_1[7]\, CLK => lclk_c, Q => \address[7]\); - - \v.burst_2_sqmuxa_m8_0_a4_0_RNO_0\ : NOR3B - port map(A => fault_pri, B => fault_pro67, C => N_328, Y - => burst_2_sqmuxa_m8_0_a4_0_1); - - \r.mmctrl1.ctxp[6]\ : DFN1E1 - port map(D => maddress(8), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[6]\); - - \r.dstate_i_RNIGJ620T2[8]\ : MX2B - port map(A => edata2_0_iv(4), B => \vmask_0_1_2_a4_0_0[4]\, - S => \N_3254_0\, Y => \vmask_0_1_2_0[4]\); - - \r.mmctrl1.ctx_0_0_RNI91UO[5]\ : NOR2B - port map(A => rst, B => N_2668, Y => \ctx_0_0_RNI91UO[5]\); - - \r.dstate_2_RNI2QG1A[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_4, Y => - \mcdo_m_0[4]\); - - \r.wb.data2[24]\ : DFN1E1 - port map(D => \data2_1[24]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[24]\); - - \r.wb.data1_RNO[16]\ : MX2A - port map(A => N_2114, B => maddress(16), S => - req_0_sqmuxa_1, Y => \data1_1[16]\); - - \r.dstate_i_RNIF4S5B92[8]\ : NOR2 - port map(A => \dstate_i[8]\, B => N_511, Y => - \dstate_i_RNIF4S5B92[8]\); - - \r.paddress[31]\ : DFN1E1 - port map(D => N_317_0, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[31]\); - - \r.wb.addr_RNO_4[1]\ : MX2 - port map(A => \paddress_0[1]\, B => \addr[1]\, S => N_484, - Y => \paddress[1]\); - - \r.dstate_i_2_RNISK8N1_22[8]\ : OR2B - port map(A => dataout_0(20), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[120]\); - - \r.wb.addr[4]\ : DFN1 - port map(D => \addr_1[4]\, CLK => lclk_c, Q => \address[4]\); - - \r.valid_0[2]\ : DFN1E0 - port map(D => \valid_0_1[2]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[2]\); - - \r.xaddress_RNIPQFG1_0[1]\ : OR2B - port map(A => N_3626, B => N_3625, Y => ddatainv_0_2_sqmuxa); - - \r.xaddress_RNIJH2O2_3[0]\ : NOR2B - port map(A => dataout(11), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[235]\); - - \r.xaddress[24]\ : DFN1E1 - port map(D => maddress(24), CLK => lclk_c, E => N_486, Q - => \addr[24]\); - - \r.valid_0[0]\ : DFN1E0 - port map(D => \valid_0_1[0]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[0]\); - - \un1_v.cctrlwr19_2_0_a2_5\ : OR3 - port map(A => asi(4), B => asi(2), C => N_490, Y => N_3765); - - \r.read_RNIA18D\ : OR2 - port map(A => read, B => N_135, Y => N_143); - - \r.dstate_RNI0P3L7_1[2]\ : AOI1B - port map(A => diagdata_22, B => \dstate[2]\, C => - \dcramo_m_0[246]\, Y => \rdatav_0_1_0_iv_4[22]\); - - \r.req_RNO_4\ : OA1A - port map(A => read_1, B => N_102, C => un47_m_en, Y => - \req_0_sqmuxa[0]\); - - \r.flush_0_1_RNICPBQ3D2\ : NOR3C - port map(A => N_3279, B => N_3278, C => \vmask_0_1_i_1[7]\, - Y => N_3239_i_0); - - \r.dstate_i_RNI1O26O92[8]\ : NOR2A - port map(A => edata2_iv_i_0(27), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_91); - - \r.dstate_RNIEOAIH[1]\ : AO1 - port map(A => \edata[15]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[239]\, Y => \ddatainv_0_1_1_iv_0[15]\); - - \r.cache_RNO\ : OR3 - port map(A => N_3674, B => N_3675, C => N_2481, Y => - cache_RNO_0); - - \r.xaddress_RNO[8]\ : MX2 - port map(A => \addr[8]\, B => maddress(8), S => N_486_0, Y - => N_716); - - \r.wb.data2_RNO[14]\ : MX2 - port map(A => edata2_0_iv(14), B => hrdata_0_14, S => - \dstate_1[7]\, Y => \data2_1[14]\); - - \r.wb.data2_RNI46J7[7]\ : OR2B - port map(A => \data2[7]\, B => rdatav_012, Y => N_3314); - - \r.vaddr_RNIVTDE[6]\ : MX2 - port map(A => maddress(6), B => \vaddr[6]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[82]\); - - \r.dstate_RNO[4]\ : AOI1B - port map(A => \dstate_ns_0_3[4]\, B => N_3494, C => rst, Y - => \dstate_nss[4]\); - - \r.wb.data1[7]\ : DFN1E0 - port map(D => \data1_1[7]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(7)); - - \r.nomds_RNIMCHA\ : OR2 - port map(A => \hold\, B => nomds, Y => N_522); - - \r.mmctrl1.e_RNIUU9O\ : OR2A - port map(A => \e\, B => N_526, Y => N_3499); - - \r.mmctrl1.e_RNIN8042\ : AO1B - port map(A => ctx_NE_5, B => ctx_NE_4, C => \e\, Y => N_495); - - \r.dstate_RNICUS5G[1]\ : MX2 - port map(A => maddress(28), B => edata2_iv_i_0(28), S => - edata_0_sqmuxa_i_0, Y => \edata[28]\); - - \r.dstate_i_2_RNIOU7E[8]\ : OR2 - port map(A => asi(2), B => \dstate_i_2[8]\, Y => N_3758); - - \r.xaddress_RNI0L8AO[1]\ : AOI1B - port map(A => \edata[7]\, B => ddatainv_0_0_sqmuxa, C => - \edata_m_0_i[15]\, Y => \ddatainv_0_1_0_iv_1[31]\); - - \r.wb.addr_RNO_2[24]\ : AOI1B - port map(A => N_2165_0, B => N_545, C => N_3740, Y => - \addr_1_1_iv_0_0[24]\); - - \r.wb.data1_RNO_0[26]\ : MX2C - port map(A => edata2_iv_i_0(26), B => \data2[26]\, S => - N_3331, Y => N_2124); - - \r.stpend_RNITKI6C\ : OR2 - port map(A => un1_eholdn_2, B => \un1_dci_5[0]\, Y => - cctrlwr19_1_0); - - \r.cctrl.dcs_RNI25QM7[0]\ : NOR2B - port map(A => \rdatav_0_1_0_iv_1[2]\, B => - \rdatav_0_1_0_iv_2[2]\, Y => \rdatav_0_1_0_iv_3[2]\); - - \r.wb.data1_RNO_2[3]\ : NOR3A - port map(A => edata2_0_iv(3), B => req_0_sqmuxa_1_0, C => - N_3331_0, Y => N_3363); - - \r.wb.addr_RNO_1[21]\ : OR2B - port map(A => maddress(21), B => addr_2_sqmuxa_0, Y => - N_3638); - - \r.cctrl.ics_RNIJFPM9[1]\ : NOR3C - port map(A => N_3232, B => \rdatav_0_1_0_iv_i_a4_1[1]\, C - => \rdatav_0_1_0_iv_i_a4_3[1]\, Y => - \rdatav_0_1_0_iv_i_a4_4[1]\); - - \r.wb.addr_RNO_5[9]\ : OR2B - port map(A => \un1_m0_2[85]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[85]\); - - \r.mmctrl1.e_RNIEMFKMG3\ : AO1B - port map(A => asi(3), B => N_3780, C => N_3810, Y => N_688); - - \r.dstate_RNI5GFM4[5]\ : MX2A - port map(A => N_566, B => N_3331, S => dstate_14, Y => - \dstate_RNI5GFM4[5]\); - - \r.cctrl.dcs_RNO[1]\ : NOR3A - port map(A => rst, B => N_672, C => N_3664, Y => N_51); - - \r.wb.data2[10]\ : DFN1E1 - port map(D => \data2_1[10]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[10]\); - - \r.dstate_RNIMHOIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[0]\, Y => \ddatainv_0_1_0_iv_1[16]\); - - \r.dstate_i_2_RNIU4F1Q92[8]\ : NOR3A - port map(A => setrepl_0_sqmuxa_1_m_i_5_4, B => mexc, C => - N_3790, Y => N_55); - - \r.dstate_RNIT0SK8[1]\ : MX2B - port map(A => maddress(6), B => edata2_0_iv(6), S => - edata_0_sqmuxa_i_0, Y => \edata[6]\); - - \r.wb.addr_RNO_3[26]\ : AOI1B - port map(A => \paddress[26]\, B => N_2165_0, C => - \mmudco_m[28]\, Y => \addr_1_1_iv_0[26]\); - - \dctrl.v.wb.addr_1_1_iv_0_RNO[10]\ : AND2 - port map(A => \addr_1_1_iv_0_2[10]\, B => - \addr_1_1_iv_0_1[10]\, Y => \addr_1_1_iv_0_3[10]\); - - \r.xaddress_RNIVN7I[0]\ : OR3C - port map(A => N_3764, B => \addr[0]\, C => \addr[1]\, Y => - N_727); - - \r.mmctrl1.ctxp_RNIPLJ12[10]\ : OR2B - port map(A => \ctxp[10]\, B => N_3344_i_0, Y => - \ctxp_m[10]\); - - \r.dstate_i_RNIR6KHK92[8]\ : OR2A - port map(A => edata2_0_iv(12), B => \N_3254_0\, Y => - \dci_m[84]\); - - \r.dstate_0_RNIIC256_10[7]\ : NAND2 - port map(A => rdatav_0_6_sqmuxa_0, B => dataout(4), Y => - \dcramo_m_0[228]\); - - \r.mmctrl1wr_RNO\ : NOR2 - port map(A => un19_eholdn, B => N_3790, Y => mmctrl1wr_RNO); - - \r.mmctrl1.ctxp[11]\ : DFN1E1 - port map(D => maddress(13), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[11]\); - - \r.dstate_RNO_17[4]\ : OR2A - port map(A => ready, B => \req\, Y => N_16886_tz_tz); - - \dctrl.twrite_14_iv_0_o2_a0\ : NAND2 - port map(A => un1_addout_13_i, B => twrite_14_iv_0_o2_a0_4, - Y => N_1_28_i); - - \r.wb.data2_RNO[11]\ : MX2 - port map(A => edata2_0_iv(11), B => hrdata_0_11, S => - \dstate[7]\, Y => \data2_1[11]\); - - \r.read_RNIDMGV6\ : NOR2B - port map(A => \N_425\, B => hrdata_0_10, Y => \mcdo_m[10]\); - - \r.faddr[2]\ : DFN1E0 - port map(D => \faddr_1[2]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[2]\); - - \r.xaddress_RNIJH2O2_6[0]\ : NOR2B - port map(A => dataout(8), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[232]\); - - \r.flush_0_1_RNI30N4992\ : NOR3B - port map(A => \dstate_i_RNII68N892_0[8]\, B => N_3833, C - => \un1_p0_2_0[498]\, Y => \N_330\); - - \r.flush_0_1_RNIBKU5992\ : NOR2B - port map(A => maddress(24), B => \N_329\, Y => N_3892); - - \r.faddr[0]\ : DFN1E0 - port map(D => \faddr_1[0]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[0]\); - - \r.xaddress[12]\ : DFN1E1 - port map(D => maddress(12), CLK => lclk_c, E => N_486_0, Q - => \addr[12]\); - - \r.wb.addr_RNO_3[9]\ : OR2B - port map(A => maddress(9), B => addr_2_sqmuxa, Y => - \dci_m[17]\); - - \r.wb.addr_RNO_3[18]\ : OR2B - port map(A => \address[18]\, B => N_514, Y => N_190); - - \r.wb.addr_RNO[24]\ : AO1B - port map(A => N_696, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_0_2[24]\, Y => \addr_1[24]\); - - \r.ready_RNO_6\ : OR3 - port map(A => \dstate_i_2_RNITVLGB92[8]\, B => N_3778, C - => asi(2), Y => N_3697); - - \r.xaddress_RNI44V9992[27]\ : NOR2B - port map(A => \addr[27]\, B => \N_330\, Y => N_3895); - - \r.flush_0_1_RNISQE2E91\ : OA1B - port map(A => twrite_14_iv_0_a2_a0_RNIGON1LK, B => - \dstate_RNIR2CO3[4]\, C => N_184, Y => N_91); - - \r.dstate_0_RNIMIEID[2]\ : NOR3C - port map(A => \ctxp_m[7]\, B => \rdatav_0_1_0_iv_1[9]\, C - => \rdatav_0_1_0_iv_3[9]\, Y => rdatav_0_1_0_iv_4_9); - - \r.dstate_i_0[8]\ : DFN1 - port map(D => \dstate_nss_i_0[0]\, CLK => lclk_c, Q => - \dstate_i_0[8]\); - - \r.dstate_2_RNIGGD211[7]\ : OR2B - port map(A => \rdatav_0_1_0_iv_4[20]\, B => \mcdo_m_0[20]\, - Y => data_0_20); - - \r.xaddress_RNIVVU9992[15]\ : OR2B - port map(A => \addr[15]\, B => \N_330\, Y => N_255); - - \r.vaddr[9]\ : DFN1E1 - port map(D => maddress(9), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[9]\); - - \r.dstate_tr22_15_a2_2_m1_e\ : OR3B - port map(A => fault_pri, B => fault_pro, C => accexc_6, Y - => dstate_tr22_15_a2_2_m1_e); - - \r.dstate_0_RNIKBNPH[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_0_2, Y => - mcdo_m_0_1); - - \r.wb.data1_RNO_0[1]\ : MX2B - port map(A => edata2_0_iv(1), B => \data2[1]\, S => - N_3331_0, Y => N_2099); - - \r.wb.addr_RNO_4[2]\ : OR3B - port map(A => \dstate[7]\, B => N_115, C => burst_0_sqmuxa, - Y => N_316); - - \r.holdn_RNO_5\ : NOR3C - port map(A => holdn_1_sqmuxa, B => holdn_0_1, C => N_3750, - Y => holdn_0_3); - - \r.dstate_i_RNI8TBIK92[8]\ : OR2A - port map(A => edata2_0_iv(16), B => - \dstate_i_RNII68N892_0[8]\, Y => \dci_m[88]\); - - \r.dstate_RNIFMKG5_0[7]\ : NOR2A - port map(A => \dstate_RNIP22L4[7]\, B => N_484_0, Y => - N_3792); - - \rdatasel_1_i_a3_2_0[7]\ : OR2 - port map(A => asi(0), B => asi(4), Y => - \rdatasel_1_i_a3_2_0[7]_net_1\); - - \r.xaddress_RNIAOA4[5]\ : NOR3A - port map(A => flush_0_sqmuxa_0_o3_i_o2_2, B => \addr[5]\, C - => \addr[7]\, Y => flush_0_sqmuxa_0_o3_i_o2_4); - - \r.wb.addr_RNO_2[4]\ : OR2B - port map(A => \address[4]\, B => dstate_19, Y => - \addr_m[4]\); - - \r.holdn_RNO_2\ : AO1B - port map(A => holdns_iv_0_1, B => N_3613, C => holdn_1, Y - => holdn_10); - - \r.dstate_RNIHILB6_2[7]\ : OR2B - port map(A => dataout(22), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[246]\); - - \r.cctrl.dcs_RNIKN0L[0]\ : NOR3B - port map(A => \dcs[0]\, B => read_0, C => lock, Y => - \dstate_ns_i_a4_i_a2_3_0[0]\); - - \r.wb.lock_RNO_4\ : OR3A - port map(A => lock_1_iv_0_a2_1_0, B => N_3331_0, C => - nullify, Y => N_3555); - - \r.dstate_RNIAQNB0A2[7]\ : NOR2A - port map(A => twrite_11_m, B => N_55, Y => N_3246); - - \r.dstate_RNI05S4E[1]\ : OR2B - port map(A => \edata[15]\, B => ddatainv_0_4_sqmuxa, Y => - \edata_m_0_i[15]\); - - \dctrl.un1_eholdn_2_i_i_o2\ : OR2A - port map(A => N_509, B => N_503, Y => un1_eholdn_2); - - \r.vaddr[31]\ : DFN1E1 - port map(D => maddress(31), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[31]\); - - \r.vaddr[12]\ : DFN1E1 - port map(D => maddress(12), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[12]\); - - \r.mmctrl1.ctx_0_0_RNI4S8L[5]\ : MX2 - port map(A => \ctx_0[5]\, B => maddress(5), S => - ctx_1_sqmuxa, Y => N_2668); - - \r.nomds_RNICGJOB\ : AO1 - port map(A => \dstate_ns_i_a4_i_o2_9_2[0]\, B => - mexc_0_sqmuxa_1, C => \dstate_ns_i_a4_i_a2_6_0[0]\, Y => - N_3683_i); - - \r.wb.data2_RNO[22]\ : MX2 - port map(A => edata2_0_iv(22), B => hrdata_0_22, S => - \dstate_0[7]\, Y => \data2_1[22]\); - - \r.paddress[12]\ : DFN1E1 - port map(D => N_2886, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[12]\); - - \r.wb.data1[26]\ : DFN1E0 - port map(D => \data1_1[26]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_14); - - \r.dstate_i_0_RNINTFVC[8]\ : NOR3B - port map(A => burst_3_m_1, B => burst_0_sqmuxa_2, C => - burst_2_sqmuxa_2, Y => burst_3_m_3); - - \r.mmctrl1.ctx[0]\ : DFN1 - port map(D => \ctx_RNIB8BR[0]\, CLK => lclk_c, Q => - \ctx[0]\); - - \r.wb.data2_RNIT9I7[0]\ : OR2B - port map(A => \data2[0]\, B => rdatav_012, Y => - \data2_m[0]\); - - \r.wb.addr_RNO_5[29]\ : MX2 - port map(A => \paddress[29]\, B => \addr[29]\, S => N_484_0, - Y => N_546); - - \r.mmctrl1.e_0_0_RNIMJIR\ : AO1B - port map(A => un1_m_en_2, B => un1_m_en_1, C => \e_0\, Y - => N_484_0); - - \r.dstate_RNIQDJBR[1]\ : AO1 - port map(A => \edata[0]\, B => \size_RNIBHS22[0]\, C => - \mcdo_m[0]\, Y => \ddatainv_0_1_1_iv_1[0]\); - - \r.wb.addr[24]\ : DFN1 - port map(D => \addr_1[24]\, CLK => lclk_c, Q => - \address[24]\); - - \un1_v.cctrlwr19_2_0_a2_4\ : AO1D - port map(A => flush, B => asi(1), C => N_533, Y => N_3770); - - \r.mmctrl1.ctx_0_0_RNIBTOV1[1]\ : OR3B - port map(A => \rdatav_0_1_0_iv_i_a2_2_0[1]\, B => - un30_m_en_0, C => rdatasel_4_sqmuxa, Y => N_3233); - - \r.dstate_RNIFT77A[1]\ : NOR2B - port map(A => \edata[6]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[6]\); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_2[10]\ : OR2B - port map(A => un1_m0_2_11, B => addr_1_sqmuxa_0, Y => - N_3726); - - \r.mmctrl1.ctx_0_0_RNI1MMQ5[5]\ : AOI1 - port map(A => \ctx_0[5]\, B => miscdata_2_sqmuxa, C => - \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_i_a2_4[5]\); - - \r.valid_0_RNO_0[5]\ : AO1 - port map(A => \valid_0_1_1_a4_1_0[5]\, B => - \vmaskraw_1_i_o2_i_a2_0_RNIBEQD1[1]\, C => N_188, Y => - \valid_0_1_1_0[5]\); - - \r.read_RNI2LUJG\ : NOR2B - port map(A => \N_425\, B => hrdata_0_0, Y => \mcdo_m[0]\); - - \r.wb.data2_RNO[3]\ : MX2A - port map(A => edata2_0_iv(3), B => hrdata_0_3, S => - \dstate_1[7]\, Y => N_3347); - - \r.wb.data2_RNI6FOB[30]\ : OR2B - port map(A => \data2[30]\, B => rdatav_012_0, Y => - \data2_m[30]\); - - \r.valid_0_RNIUBMT1[7]\ : AOI1 - port map(A => hit, B => \valid_0[7]\, C => N_44_i_0, Y => - N_2027); - - \r.holdn_RNIRBQ6\ : OR2A - port map(A => \hold\, B => write, Y => N_3443_i); - - \r.wb.addr[14]\ : DFN1 - port map(D => \addr_1[14]\, CLK => lclk_c, Q => - \address[14]\); - - \dctrl.twrite_14_iv_0_o2_a0_RNO_1\ : NOR3B - port map(A => setrepl_0_sqmuxa_1_m_i_5_4, B => - twrite_14_iv_0_o2_a1_0, C => mexc, Y => - twrite_14_iv_0_o2_a0_1); - - \r.dstate_i_2_RNISK8N1_18[8]\ : OR2B - port map(A => dataout_0(0), B => rdatasel_1_sqmuxa_1, Y => - \dcramo_m[96]\); - - \r.wb.addr_RNO_3[30]\ : AOI1B - port map(A => un1_m0_2_31, B => addr_1_sqmuxa_0, C => - \paddress_m[30]\, Y => \addr_1_1_iv_0[30]\); - - \r.flush_0_1\ : DFN1 - port map(D => N_2710_i, CLK => lclk_c, Q => - \un1_p0_2_0[498]\); - - \r.dstate_RNIHILB6_9[7]\ : OR2B - port map(A => dataout(15), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[239]\); - - \r.wb.lock_RNI3VPBB\ : OR2A - port map(A => lock_m_0, B => un59_nbo, Y => lock_m); - - \r.wb.data1_RNO[7]\ : MX2A - port map(A => N_2105, B => maddress(7), S => - req_0_sqmuxa_1_0, Y => \data1_1[7]\); - - \r.read_RNID1UNB\ : NOR2B - port map(A => \N_425\, B => hrdata_0_3, Y => \mcdo_m[3]\); - - \r.wb.data2_RNI27OB[12]\ : OR2B - port map(A => \data2[12]\, B => rdatav_012, Y => - \data2_m[12]\); - - \r.read_RNI3V8BG\ : NOR2B - port map(A => \N_425\, B => hrdata_0_1, Y => \mcdo_m[1]\); - - \r.dstate_i_0_RNI48F4E92[8]\ : NOR3 - port map(A => burst_2_sqmuxa_2, B => read_0, C => - un1_dci_12, Y => req_2_sqmuxa_1_0); - - \r.cctrl.dcs_RNIJNS78H3[0]\ : OR3C - port map(A => N_3818, B => \dstate_ns_i_a4_i_a2_0[0]\, C - => N_688, Y => N_3676); - - \r.cctrl.burst_RNIGLUQ1\ : OR2B - port map(A => \burst_0\, B => rdatav_0_0_sqmuxa, Y => - burst_m); - - \r.xaddress_RNIJH2O2_9[0]\ : NOR2B - port map(A => dataout(0), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[224]\); - - \r.wb.addr_RNO_3[17]\ : OR2B - port map(A => \address[17]\, B => N_514, Y => N_3721); - - \r.dstate_i_RNI7TT2I92[8]\ : NOR3 - port map(A => N_3775, B => N_3745, C => N_556, Y => N_587); - - \r.wb.data1_RNO[12]\ : MX2A - port map(A => N_2110, B => maddress(12), S => - req_0_sqmuxa_1_0, Y => \data1_1[12]\); - - \r.wb.addr_RNO_3[20]\ : OR2B - port map(A => \address[20]\, B => N_514, Y => N_3863); - - \r.dstate_RNIK0O51[1]\ : MX2B - port map(A => maddress(2), B => edata2_0_iv(2), S => - edata_0_sqmuxa_i, Y => \edata[2]\); - - \un1_v.cctrlwr19_2_0_o2_3\ : OR2 - port map(A => flush, B => N_551, Y => N_561); - - \r.mmctrl1.ctx_0_0_RNI7TTO[4]\ : NOR2B - port map(A => rst, B => N_2667, Y => \ctx_0_0_RNI7TTO[4]\); - - \r.xaddress_RNIUJQK4[4]\ : MX2 - port map(A => maddress(4), B => \addr[4]\, S => - un1_taddr_1_sqmuxa, Y => N_3261); - - \r.mmctrl1.e_RNIMP673\ : OR2A - port map(A => N_485, B => un47_m_en, Y => N_328); - - \r.cache_RNIRE2K\ : NOR3C - port map(A => hcache, B => ba, C => cache_0, Y => - twrite_11_m_0_a2_0_0); - - \r.dstate_RNIF6E91[2]\ : OR2B - port map(A => diagdata_1, B => \dstate[2]\, Y => - \ico_m[135]\); - - \r.cctrl.dfrz\ : DFN1E0 - port map(D => maddress(5), CLK => lclk_c, E => \N_523\, Q - => dfrz); - - \r.stpend_RNIJPSU1\ : AO1C - port map(A => \req\, B => ready, C => stpend, Y => N_485); - - \r.xaddress[10]\ : DFN1 - port map(D => N_718, CLK => lclk_c, Q => \addr[10]\); - - \r.wb.addr[30]\ : DFN1 - port map(D => \addr_1[30]\, CLK => lclk_c, Q => - \address[30]\); - - \r.dstate_RNO_2[5]\ : OR3A - port map(A => \req\, B => \dstate_ns_0_8_tz[3]\, C => - N_3514, Y => \dstate_ns_0_7_i[3]\); - - \r.xaddress_RNIQF6M2_11[0]\ : NAND2 - port map(A => \xaddress_RNI1CIE2_0[0]\, B => dataout(18), Y - => \dcramo_m_i[242]\); - - \r.wb.data2[9]\ : DFN1E1 - port map(D => \data2_1[9]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[9]\); - - \r.mmctrl1.ctxp_RNIMLF32[6]\ : OR2B - port map(A => \ctxp[6]\, B => N_3344_i_0, Y => \ctxp_m[6]\); - - \r.wb.addr_RNO_4[24]\ : MX2 - port map(A => \paddress[24]\, B => \addr[24]\, S => N_484_0, - Y => N_545); - - \r.wb.addr_RNO_3[22]\ : OR2B - port map(A => \address[22]\, B => N_514, Y => N_185); - - \r.dstate_RNIKFV3H[1]\ : OR2B - port map(A => \edata[28]\, B => ddatainv_0_6_sqmuxa, Y => - \edata_m_i[28]\); - - \r.dstate_RNIGVSIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[7]\, Y => \ddatainv_0_1_0_iv_1[23]\); - - \r.size_RNI2C3G[0]\ : NOR3A - port map(A => N_3749, B => \size_0[1]\, C => \size[0]\, Y - => N_3764); - - \r.dstate_0_RNIQF2BJ[2]\ : AOI1B - port map(A => diagdata_0, B => \dstate_0[2]\, C => - \rdatav_0_1_0_iv_6[0]\, Y => \rdatav_0_1_0_iv_7[0]\); - - \r.wb.addr_RNO_0[30]\ : OA1 - port map(A => \data[30]\, B => LVL_RNIT69H911(0), C => - addr_1_sqmuxa_2_0, Y => \mmudco_m_0[106]\); - - \r.cctrl.dcs_RNIJJUSO[0]\ : AO1B - port map(A => \dstate_ns_i_a4_i_a2_16_0[0]\, B => N_3815, C - => N_3709, Y => N_467); - - \r.wb.data1_RNO[25]\ : MX2A - port map(A => N_2123, B => maddress(25), S => - req_0_sqmuxa_1, Y => \data1_1[25]\); - - \r.flush_0_1_RNIIH0S4\ : NOR2A - port map(A => flush_i_0, B => \un1_p0_2_0[498]\, Y => - faddr_1_sqmuxa_0); - - \r.dstate_2_RNIP66J9[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_18, Y => - mcdo_m_0_17); - - \r.dstate_1_RNIER442[7]\ : NOR2A - port map(A => \dstate_1[7]\, B => N_585, Y => N_3811); - - \r.dstate_0_RNIRJ8TD[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_23, Y => - \mcdo_m_0[28]\); - - \r.cache_RNO_9\ : NOR2B - port map(A => \dstate[6]\, B => cache_0, Y => - cache_1_0_a3_0_0); - - \r.xaddress[6]\ : DFN1 - port map(D => N_710, CLK => lclk_c, Q => \addr[6]\); - - \r.wb.data2[22]\ : DFN1E1 - port map(D => \data2_1[22]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[22]\); - - \r.wb.data2_RNI17OB[11]\ : OR2B - port map(A => \data2[11]\, B => rdatav_012, Y => - \data2_m[11]\); - - \r.mmctrl1.ctx_0_0_RNI6JTGB[4]\ : AND2 - port map(A => \rdatav_0_1_0_iv_4[4]\, B => \ctx_m[4]\, Y - => \rdatav_0_1_0_iv_5[4]\); - - \r.holdn_RNO_18\ : OR3A - port map(A => N_492, B => \e_0\, C => - \dstate_i_2_RNITVLGB92[8]\, Y => N_3611); - - \r.flush2_RNIPC79F\ : AO1A - port map(A => un6_validrawv, B => N_499, C => N_562, Y => - N_3814); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_19\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_10, B => - eaddress_18, C => eaddress_6, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_19); - - \r.xaddress_RNO_3[2]\ : OR2B - port map(A => \hold\, B => enaddr, Y => N_591); - - \r.xaddress_RNIVDCSTI[18]\ : OA1A - port map(A => edata2_0_iv(18), B => \N_3254_0\, C => N_3850, - Y => \newtag_1_0[18]\); - - \r.mmctrl1.ctxp_RNI3LB66[24]\ : AOI1B - port map(A => \ctxp[24]\, B => N_3344_i_0_0, C => - \rdatav_0_1_0_iv_1[26]\, Y => \rdatav_0_1_0_iv_2[26]\); - - \un1_r.faddr_I_5\ : XOR2 - port map(A => \faddr[0]\, B => \faddr[1]\, Y => I_5_1); - - \r.dstate_tr13_11_11\ : OR2 - port map(A => N_3514, B => ready, Y => N_3041_11); - - \v.burst_2_sqmuxa_m3_e_RNO\ : OR2 - port map(A => M_m, B => un54_fault_pro_m, Y => - burst_2_sqmuxa_m3_e_RNO); - - \un1_v.ready_0_sqmuxa_0_a2_4\ : OR3B - port map(A => asi(4), B => asi(3), C => asi(0), Y => N_3778); - - \r.cache_RNO_1\ : NOR3 - port map(A => N_3788, B => cache_1_0_a2_0_0, C => N_502, Y - => N_3675); - - \r.wb.data1[19]\ : DFN1E0 - port map(D => \data1_1[19]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_0_19); - - \r.dstate_i_RNI6DCIK92[8]\ : OR2A - port map(A => edata2_0_iv(21), B => \N_3254_0\, Y => - \dci_m[93]\); - - \r.dstate_i_0_RNI1GDM[8]\ : MX2 - port map(A => dataout_0(2), B => \vmask_0_5_1_a2_2_0[2]\, S - => \dstate_i_0[8]\, Y => \vmask_0_5_1_0[2]\); - - \r.dstate_RNO_11[4]\ : XNOR2 - port map(A => asi(3), B => asi(0), Y => N_114_i_i_0); - - \r.flush_0_1_RNI8KU5992\ : OR2B - port map(A => maddress(21), B => \N_329\, Y => N_3894); - - \dctrl.v.holdns_iv_0_o2\ : OR2B - port map(A => asi(4), B => N_512, Y => N_489); - - \r.wb.data1_RNO_0[8]\ : MX2 - port map(A => edata2_0_iv(8), B => \data2[8]\, S => N_3331, - Y => N_3260); - - \r.valid_0_RNO_1[7]\ : OR3B - port map(A => hit_1_iv_0_a2_0_0, B => dataout_0(7), C => - twrite_14, Y => N_3283); - - \r.stpend_RNO_0\ : OA1 - port map(A => un47_m_en, B => req16, C => req_2_sqmuxa_1_0, - Y => dstate_5_sqmuxa); - - \un1_r.faddr_I_9\ : XOR2 - port map(A => N_20, B => \faddr[2]\, Y => I_9_1); - - \r.wb.data2_RNI07OB[10]\ : OR2B - port map(A => \data2[10]\, B => rdatav_012, Y => N_3304); - - \r.wb.addr_RNO_5[7]\ : OR2B - port map(A => \address[7]\, B => dstate_19, Y => N_3737); - - \r.wb.addr_RNO[31]\ : AO1B - port map(A => un1_m0_2_106, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_0_2[31]\, Y => \addr_1[31]\); - - \r.xaddress_RNITVU9992[13]\ : OR2B - port map(A => \addr[13]\, B => \N_330\, Y => N_3848); - - \r.paddress[14]\ : DFN1E1 - port map(D => un1_m0_2_15, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[14]\); - - \r.nomds_RNO_0\ : MX2 - port map(A => nomds_1, B => nomds, S => N_3153, Y => N_2596); - - \r.mmctrl1.ctxp[14]\ : DFN1E1 - port map(D => maddress(16), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[14]\); - - \dctrl.mmudci_diag_op_1_0_a2_0\ : NOR2B - port map(A => asi(2), B => un19_eholdn_3, Y => - mmudci_diag_op_1_0_a2_0); - - \r.vaddr[10]\ : DFN1E1 - port map(D => maddress(10), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[10]\); - - \r.mmctrl1.ctxp[28]\ : DFN1E1 - port map(D => maddress(30), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[28]\); - - \r.dstate_RNO_3[5]\ : NOR3C - port map(A => N_3180_i, B => data2_1_sqmuxa, C => N_3035, Y - => \dstate_ns_0_1[3]\); - - \r.vaddr_RNIK6IC[29]\ : MX2 - port map(A => maddress(29), B => \vaddr[29]\, S => - \dstate_i_1[8]\, Y => data(29)); - - \r.wb.data2_RNO[5]\ : MX2A - port map(A => edata2_0_iv(5), B => hrdata_0_d0, S => - \dstate_1[7]\, Y => N_3348); - - \r.wb.data2_RNI3BOB[20]\ : OR2B - port map(A => \data2[20]\, B => rdatav_012, Y => - \data2_m[20]\); - - \dctrl.0.un1_dci_7_0\ : XNOR2 - port map(A => dataout_0(15), B => maddress(19), Y => - un1_dci_7_i); - - \r.wb.addr_RNO_3[31]\ : AOI1B - port map(A => N_2165_0, B => N_544, C => N_3716, Y => - \addr_1_1_iv_0_0[31]\); - - \r.flush_0_1_RNIPTA27S2\ : AO1B - port map(A => maddress(22), B => \N_329\, C => - \newtag_1_0[22]\, Y => flush_0_1_RNIPTA27S2); - - \r.wb.addr_RNO[19]\ : AO1B - port map(A => un1_m0_2_94, B => addr_1_sqmuxa_2, C => - \addr_1_1_iv_0_2[19]\, Y => \addr_1[19]\); - - \r.dstate_RNIUR652[5]\ : OR2B - port map(A => \dstate[5]\, B => N_566, Y => - data2_0_sqmuxa_1); - - \r.xaddress[22]\ : DFN1E1 - port map(D => maddress(22), CLK => lclk_c, E => N_486, Q - => \addr[22]\); - - \r.faddr[6]\ : DFN1E0 - port map(D => \faddr_1_i[6]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[6]\); - - \r.wb.data2_RNIVHI7[2]\ : OR2B - port map(A => \data2[2]\, B => rdatav_012, Y => - \data2_m[2]\); - - \r.dstate_i_RNI7SGE8[8]\ : NOR2A - port map(A => \dstate_RNIR2CO3[4]\, B => \vmask_0_5[6]\, Y - => \vmask_0_6[6]\); - - \r.dstate_2_RNIAQTV6[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_22, Y => - mcdo_m_0_21); - - \r.wb.data2[18]\ : DFN1E1 - port map(D => \data2_1[18]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[18]\); - - \r.dstate_RNO_0[3]\ : AO1A - port map(A => N_3790, B => cctrlwr13, C => N_3672, Y => - \dstate_ns[5]\); - - \r.wb.addr_RNO_3[13]\ : OR2B - port map(A => \address[13]\, B => N_514, Y => N_275); - - \r.wb.addr_RNO_3[21]\ : OR2B - port map(A => \address[21]\, B => N_514, Y => N_3718); - - \r.dstate_RNIOGKSE[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_0_21, Y => - \mcdo_m_0[21]\); - - \r.wb.addr_RNO_4[16]\ : OR2B - port map(A => \paddress[16]\, B => \dstate_RNIP22L4[7]\, Y - => \paddress_m[16]\); - - \r.vaddr[3]\ : DFN1E1 - port map(D => maddress(3), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[3]\); - - \un1_v.cctrlwr19_2_0_o2\ : OR2B - port map(A => asi(2), B => N_537, Y => N_481); - - \r.req_RNO_1\ : OR3B - port map(A => req_2_sqmuxa_1_0, B => req16, C => un47_m_en, - Y => req_2_sqmuxa); - - \r.asi[4]\ : DFN1E1 - port map(D => asi(4), CLK => lclk_c, E => N_486_0, Q => - \ctx\); - - \r.dstate_0_RNIIC256_8[7]\ : NAND2 - port map(A => rdatav_0_6_sqmuxa_0, B => dataout_0(30), Y - => \dcramo_m_0[254]\); - - \r.flush_0_1_RNIOHD0NI\ : AOI1B - port map(A => faddr_1_sqmuxa_0, B => flush_1_i_0, C => - flush_0_0, Y => N_2710_i); - - \r.dstate_2_RNIU38NG[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_15, Y => N_202); - - \v.wb.addr_1_sqmuxa_1_0_i2_0_a2\ : NOR2A - port map(A => \dstate_0[7]\, B => burst_0_sqmuxa, Y => - addr_1_sqmuxa_1); - - \r.xaddress_RNIIEFGO[7]\ : MX2C - port map(A => N_2234, B => eaddress_5, S => taddr_2_sqmuxa, - Y => \taddr_7[7]\); - - \r.wb.data2_RNIBBOB[28]\ : OR2B - port map(A => \data2[28]\, B => rdatav_012_0, Y => - \data2_m[28]\); - - \r.ready_RNO\ : OR3C - port map(A => ready_RNO_0, B => ready_0_sqmuxa_0_0, C => - ready_0_sqmuxa_0_2, Y => ready_0_sqmuxa); - - \r.wb.data1_RNO_0[7]\ : MX2B - port map(A => edata2_0_iv(7), B => \data2[7]\, S => - N_3331_0, Y => N_2105); - - \r.wb.addr_RNO_2[9]\ : AOI1B - port map(A => \paddress[9]\, B => \dstate_RNIP22L4[7]\, C - => \mmudco_m[85]\, Y => \addr_1_1_iv_0[9]\); - - \r.mmctrl1.ctxp_RNIK377L[4]\ : NOR3C - port map(A => \ctxp_m[4]\, B => \rdatav_0_1_1_iv_4[6]\, C - => \rdatav_0_1_1_iv_6[6]\, Y => rdatav_0_1_1_iv_7(6)); - - \r.burst_RNO_4\ : AO1D - port map(A => burst_2_sqmuxa_m8_0_0, B => - burst_2_sqmuxa_m8_0_a4_0, C => burst_1_iv_2, Y => - burst_1_m8_i_a5_0); - - \r.holdn_RNINK401\ : OR3B - port map(A => maddress_0_2, B => N_568, C => N_3443_i, Y - => N_3660); - - \r.dstate_tr22_15_a2_11\ : NOR2 - port map(A => N_581_i, B => N_507, Y => N_3583); - - \r.wb.addr_RNO_0[31]\ : AND2 - port map(A => N_3715, B => \addr_1_1_iv_0_1[31]\, Y => - \addr_1_1_iv_0_2[31]\); - - \r.read_RNICKHE91\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[19]\, B => - \mcdo_m_i[19]\, C => \ddatainv_0_1_0_iv_1[19]\, Y => - read_RNICKHE91); - - \r.dstate_RNIACT4D[1]\ : OR2B - port map(A => \edata[9]\, B => ddatainv_0_4_sqmuxa, Y => - \edata_m_0_i[9]\); - - \r.mmctrl1.ctx_0_0_RNIE2JM9[2]\ : AOI1B - port map(A => \ctx_0[2]\, B => miscdata_2_sqmuxa, C => - \rdatav_0_1_0_iv_3[2]\, Y => \rdatav_0_1_0_iv_4[2]\); - - \r.holdn_RNIHCLM\ : OR2 - port map(A => size_0_0, B => N_3757, Y => N_3763); - - \r.cache_RNO_8\ : OR2A - port map(A => N_512, B => N_3788, Y => dstate_25_0_a2_0); - - \r.paddress[22]\ : DFN1E1 - port map(D => un1_m0_2_23, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[22]\); - - \r.wb.addr_RNO_3[15]\ : AOI1B - port map(A => N_2165_0, B => N_673, C => \mmudco_m[17]\, Y - => \addr_1_1_iv_0[15]\); - - \r.cache\ : DFN1 - port map(D => cache_RNO_0, CLK => lclk_c, Q => cache_0); - - \r.paddress[13]\ : DFN1E1 - port map(D => N_2887, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[13]\); - - \r.xaddress[3]\ : DFN1 - port map(D => N_719, CLK => lclk_c, Q => \addr[3]\); - - \r.wb.data2_RNI10132[22]\ : AOI1B - port map(A => \data2[22]\, B => rdatav_012_0, C => - \dcramo_m[118]\, Y => \rdatav_0_1_0_iv_0[22]\); - - \r.wb.addr_RNO_1[16]\ : OR2B - port map(A => maddress(16), B => addr_2_sqmuxa_0, Y => - \dci_m[24]\); - - \r.ready_RNI3M8L2\ : NOR3B - port map(A => \dstate_ns_i_a4_i_o2_11_0[0]\, B => N_72_i, C - => N_496, Y => \dstate_ns_i_a4_i_o2_11_2[0]\); - - \r.dstate_RNO_2[4]\ : NOR3B - port map(A => N_3505_i, B => dstate_tr16_13_0_0_a2_0_3, C - => nullify, Y => dstate_tr16_13_0_0_a2_0_5); - - \r.xaddress_RNIT3V9992[20]\ : OR2B - port map(A => \addr[20]\, B => \N_330\, Y => N_155); - - \r.mexc_RNICCRR3\ : OR2B - port map(A => mexc_1_m_0_a2_3_0, B => mexc_0_sqmuxa_1, Y - => N_175); - - \r.valid_0_RNO_0[1]\ : AO1 - port map(A => \valid_0_1_1_a4_1_0[1]\, B => N_32, C => - N_188, Y => \valid_0_1_1_0[1]\); - - \r.size_RNI29NJ[0]\ : NOR2 - port map(A => N_421, B => un1_m0_2_3, Y => burst_19_m_0); - - \r.wb.addr_RNO_6[29]\ : OR2B - port map(A => N_353, B => addr_1_sqmuxa_0, Y => N_262); - - \r.dstate_tr0_32_0_0_a2_1_2_i\ : OR2B - port map(A => asi(3), B => asi(2), Y => N_459); - - \r.dstate_i_1_RNI30EM[8]\ : MX2C - port map(A => dataout_0(1), B => N_95, S => \dstate_i_1[8]\, - Y => N_111); - - \r.wb.data2_RNI6BOB[23]\ : OR2B - port map(A => \data2[23]\, B => rdatav_012_0, Y => - \data2_m[23]\); - - \r.wb.data1_RNO_0[13]\ : MX2C - port map(A => edata2_0_iv(13), B => \data2[13]\, S => - N_3331_0, Y => N_2111); - - \r.dstate_0[7]\ : DFN1 - port map(D => \dstate_nss[1]\, CLK => lclk_c, Q => - \dstate_0[7]\); - - \r.wb.data1[0]\ : DFN1E0 - port map(D => \data1_1[0]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data(0)); - - \r.wb.data2_RNI32J7[6]\ : OR2B - port map(A => \data2[6]\, B => rdatav_012_0, Y => - \data2_m[6]\); - - \r.vaddr_RNI1EHC[10]\ : MX2 - port map(A => maddress(10), B => \vaddr[10]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[86]\); - - \r.read_RNILU2J8\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_17, Y => - \mcdo_m_i[17]\); - - \r.mmctrl1.e_RNIIRI11\ : AO1B - port map(A => un1_m_en_2, B => un1_m_en_1, C => \e\, Y => - N_484); - - \r.flush2_RNO\ : OR2A - port map(A => rst, B => \un1_p0_2_0[498]\, Y => - lrr_1_sqmuxa); - - \r.xaddress_RNIEHIUT1[1]\ : OR3C - port map(A => \edata_m_4_i[1]\, B => \edata_m_0_i[9]\, C - => \ddatainv_0_1_0_iv_2[25]\, Y => xaddress_RNIEHIUT1(1)); - - \r.mmctrl1.ctxp[21]\ : DFN1E1 - port map(D => maddress(23), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[21]\); - - \r.xaddress[0]\ : DFN1E1 - port map(D => maddress(0), CLK => lclk_c, E => N_486_0, Q - => \addr[0]\); - - \r.wb.data2[6]\ : DFN1E1 - port map(D => \data2_1[6]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[6]\); - - \r.mmctrl1.ctxp_RNIL00LF[1]\ : AOI1B - port map(A => \ctxp[1]\, B => N_3344_i_0_0, C => - \rdatav_0_1_1_iv_i_a2_5[3]\, Y => - \rdatav_0_1_1_iv_i_a2_6[3]\); - - \r.dstate_i_2_RNI0RM12[8]\ : OR2B - port map(A => un1_m0_2_70, B => miscdata_4_sqmuxa, Y => - \mmudco_m[71]\); - - \r.xaddress_RNI20V9992[18]\ : OR2B - port map(A => \addr[18]\, B => \N_330\, Y => N_3850); - - \r.wb.addr_RNO_5[5]\ : OR2B - port map(A => \un1_m0_2[81]\, B => addr_1_sqmuxa_2, Y => - N_289); - - \r.xaddress_RNI9SHE[10]\ : NOR3A - port map(A => ctx_1_sqmuxa_0_a2_0, B => \addr[8]\, C => - \addr[10]\, Y => ctx_1_sqmuxa); - - \r.dstate_RNI15BH[7]\ : NOR2B - port map(A => \dstate[7]\, B => N_508, Y => mexc_1_sqmuxa); - - \r.xaddress[20]\ : DFN1E1 - port map(D => maddress(20), CLK => lclk_c, E => N_486, Q - => \addr[20]\); - - \r.wb.data1_RNO[2]\ : MX2A - port map(A => N_2100, B => maddress(2), S => req_0_sqmuxa_1, - Y => \data1_1[2]\); - - \r.mmctrl1.ctxp_RNIBAR3A[15]\ : NOR3C - port map(A => \mmudco_m[60]\, B => \rdatav_0_1_1_iv_2[17]\, - C => \ctxp_m[15]\, Y => \rdatav_0_1_1_iv_4[17]\); - - \r.wb.addr_RNO_2[16]\ : AOI1B - port map(A => data_RNIKU1T4(16), B => addr_1_sqmuxa_0, C - => \paddress_m[16]\, Y => \addr_1_1_iv_0[16]\); - - \r.wb.addr_RNO_0[26]\ : AOI1B - port map(A => data_1_3_i_a3_6_1, B => LVL_RNIT69H911(0), C - => addr_1_sqmuxa_2_0, Y => \mmudco_m_0[102]\); - - \r.dstate_0_RNIOEF6V[7]\ : OR3C - port map(A => \rdatav_0_1_1_iv_5[28]\, B => - \rdatav_0_1_1_iv_4[28]\, C => \mcdo_m_0[28]\, Y => - data_0_28); - - \r.mmctrl1.ctxp_RNIP9TQF[16]\ : NOR3C - port map(A => \ctxp_m[16]\, B => \rdatav_0_1_0_iv_2[18]\, C - => \rdatav_0_1_0_iv_4[18]\, Y => rdatav_0_1_0_iv_5_14); - - \r.dstate_1_RNI7S4O73[7]\ : NOR3C - port map(A => \dstate_ns_i_a4_i_6[0]\, B => N_3680_i, C => - N_3679, Y => \dstate_ns_i_a4_i_8[0]\); - - \r.xaddress[5]\ : DFN1E1 - port map(D => maddress(5), CLK => lclk_c, E => N_486, Q => - \addr[5]\); - - \dctrl.0.un1_dci_NE_7\ : XA1A - port map(A => maddress(29), B => dataout_0(25), C => - un1_dci_18_i, Y => un1_dci_NE_7); - - \r.read_RNIMGBL1\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_26, Y => - \mcdo_m_i[26]\); - - \r.mmctrl1.ctxp[13]\ : DFN1E1 - port map(D => maddress(15), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[13]\); - - \r.hit\ : DFN1E1 - port map(D => hit_1, CLK => lclk_c, E => N_9, Q => hit); - - \r.wb.data2[23]\ : DFN1E1 - port map(D => \data2_1[23]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[23]\); - - \r.dstate_i_2_RNISK8N1_14[8]\ : OR2B - port map(A => dataout_0(7), B => rdatasel_1_sqmuxa_1, Y => - N_3311); - - \dctrl.mexc_1_m_0_a2_5_0\ : OR2 - port map(A => N_3798, B => N_3091_3, Y => mexc_1_m_0_a2_5_0); - - \r.dstate_i_0_RNIRI691[8]\ : OA1A - port map(A => \dstate_ns_i_a4_i_a2_7_0[0]\, B => N_519, C - => holdn_0_0, Y => \dstate_ns_i_a4_i_0[0]\); - - \r.dlock_RNIKFGT\ : MX2B - port map(A => mmudci_read_1_1_0_a2_0_0, B => - mmudci_read_1_1_0_a2_0, S => N_3443_i, Y => read_3); - - \r.xaddress_RNI388I[3]\ : OR2B - port map(A => \addr[3]\, B => N_3793, Y => N_3800); - - \r.mmctrl1.nf_RNIA3F0I\ : NOR3C - port map(A => nf_m, B => \rdatav_0_1_0_iv_i_a4_4[1]\, C => - \dcramo_m_0[225]\, Y => \rdatav_0_1_0_iv_i_a4_6[1]\); - - \r.dstate_RNIRVS21[2]\ : OR3C - port map(A => \dstate[2]\, B => dataout_1(10), C => - cdwrite_0_sqmuxa_i_0_0, Y => N_3306); - - \r.dstate_i_2_RNIQ7942[8]\ : OR2B - port map(A => un1_m0_2_61, B => miscdata_4_sqmuxa, Y => - \mmudco_m[62]\); - - \r.dstate_tr16_1_4_0_a2_0_a2_0_a2_0_a2\ : OR2A - port map(A => asi(2), B => asi(3), Y => N_3091_3); - - \dctrl.0.un1_dci_2_0_RNIGHMF1\ : NOR3C - port map(A => un1_dci_NE_9, B => un1_dci_NE_8, C => - un1_dci_NE_15, Y => un1_dci_NE_17); - - \r.mmctrl1.ctx_RNIIUJ8[0]\ : XNOR2 - port map(A => dataout(28), B => \ctx[0]\, Y => ctx_0_i); - - \r.vaddr_RNIMMV7[2]\ : MX2 - port map(A => maddress(2), B => \vaddr[2]\, S => - \dstate_i[8]\, Y => \un1_m0_2[78]\); - - \r.wb.addr_RNO[8]\ : AO1B - port map(A => \address[8]\, B => N_514, C => - \addr_1_1_iv_2[8]\, Y => \addr_1[8]\); - - \r.read_RNIRO4K31\ : OR3 - port map(A => \mcdo_m[3]\, B => \edata_m_0[3]\, C => - \ddatainv_0_1_1_iv_0[3]\, Y => read_RNIRO4K31); - - \r.flush_RNIVHBN\ : NOR2A - port map(A => N_132, B => read_0, Y => - tdiagwrite_1_0_0_o2_1_0); - - \r.dstate_RNIT1JBG[1]\ : AOI1B - port map(A => dataout(21), B => \xaddress_RNI1CIE2_0[0]\, C - => \edata_m_i[21]\, Y => \ddatainv_0_1_0_iv_0[21]\); - - \r.dstate_0_RNIEKF0B[2]\ : OR3C - port map(A => dstate_19_4, B => dstate_19_3, C => - addr_0_sqmuxa, Y => dstate_19); - - \r.nomds_RNI4C96_0\ : NOR2A - port map(A => nomds, B => \dstate_i[8]\, Y => rdatav_012_0); - - \r.dstate_RNIHILB6_10[7]\ : OR2B - port map(A => dataout(14), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[238]\); - - \dctrl.0.un1_dci_NE_4\ : XA1A - port map(A => maddress(18), B => dataout_0(14), C => - un1_dci_7_i, Y => un1_dci_NE_4); - - \r.wb.addr_RNO_4[12]\ : OR2B - port map(A => \address[12]\, B => N_514, Y => N_280); - - \r.wb.data2_RNO[8]\ : MX2 - port map(A => edata2_0_iv(8), B => hrdata_0_8, S => - \dstate_1[7]\, Y => N_3270); - - \r.wb.data2_RNO[20]\ : MX2 - port map(A => edata2_0_iv(20), B => N_262_0, S => - \dstate_0[7]\, Y => \data2_1[20]\); - - \r.dstate_i_0_RNID0P84_0[8]\ : NOR3 - port map(A => un18_m_en, B => \dstate_i_0[8]\, C => N_328, - Y => addr_1_sqmuxa_2); - - \r.read_RNIR05CJ\ : NOR2B - port map(A => \N_425\, B => hrdata_0_14, Y => \mcdo_m[14]\); - - \r.dstate_RNIVP6I3_1[6]\ : NOR2A - port map(A => N_487, B => N_506, Y => paddress_1_sqmuxa_0); - - \r.dstate_0_RNI2DT77_1[2]\ : AOI1B - port map(A => diagdata_2, B => \dstate_0[2]\, C => - \dcramo_m_0[226]\, Y => \rdatav_0_1_0_iv_6[2]\); - - \r.wb.data2_RNO[15]\ : MX2 - port map(A => edata2_0_iv(15), B => hrdata_0_15, S => - \dstate_1[7]\, Y => \data2_1[15]\); - - \r.flush_RNIJEN4SI3\ : OAI1 - port map(A => N_349, B => \vmask_0_5[2]\, C => N_296, Y => - flush_RNIJEN4SI3); - - \r.dstate_RNO_7[5]\ : OAI1 - port map(A => N_2996_8, B => \dstate_ns_0_4_tz[3]\, C => - N_29, Y => \dstate_ns_0_3[3]\); - - \r.dstate_i_RNIF52EG92[8]\ : OR2 - port map(A => edata2_0_iv(3), B => - \dstate_i_RNII68N892_0[8]\, Y => N_306); - - \r.dstate_0[2]\ : DFN1 - port map(D => \dstate_nss[6]\, CLK => lclk_c, Q => - \dstate_0[2]\); - - \r.wb.data1[5]\ : DFN1E0 - port map(D => N_21, CLK => lclk_c, E => data1_0_sqmuxa, Q - => data(5)); - - \r.wb.data2_RNI50KU3[1]\ : AOI1B - port map(A => dataout(29), B => rdatasel_3_sqmuxa, C => - \rdatav_0_1_0_iv_i_a4_0[1]\, Y => - \rdatav_0_1_0_iv_i_a4_1[1]\); - - \r.wb.addr_RNO_3[1]\ : OR2B - port map(A => un1_m0_2_2, B => addr_1_sqmuxa, Y => - \mmudco_m[3]\); - - \r.paddress[24]\ : DFN1E1 - port map(D => N_421_0, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[24]\); - - \r.holdn_RNO_24\ : NOR3C - port map(A => N_481, B => holdns_iv_0_a2_2_1, C => N_485, Y - => holdns_iv_0_a2_2_3); - - \r.dstate_RNIOVBIG[1]\ : AO1 - port map(A => \edata[9]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[233]\, Y => \ddatainv_0_1_1_iv_0[9]\); - - \r.dstate_i_2_RNITQRS1_2[8]\ : NOR2B - port map(A => maddress(8), B => N_3321, Y => N_3344_i_0); - - \r.read_RNIQPCQ11\ : OR3 - port map(A => \mcdo_m[7]\, B => \edata_m_0[7]\, C => - \ddatainv_0_1_1_iv_0[7]\, Y => read_RNIQPCQ11); - - \r.trans_op_RNIFVCECQ1\ : NOR2 - port map(A => \trans_op_0\, B => - \mmudci_trans_op_1_sqmuxa_1\, Y => \trans_op\); - - \r.dstate_2_RNIE2QM6[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_12, Y => N_158); - - \r.flush_0_1_RNIBOU5992\ : OR2B - port map(A => maddress(31), B => \N_329\, Y => N_270); - - \r.dstate_RNIJP5O3[3]\ : AO1A - port map(A => \dstate[3]\, B => N_3752, C => un1_m0_2_0_d0, - Y => N_3760); - - \r.dstate_0_RNIIC256_0[7]\ : OR2B - port map(A => dataout(27), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[251]\); - - \r.cctrl.dcs_RNIRJ3SG[0]\ : OR3B - port map(A => N_3710, B => \dstate_ns_i_a4_i_o2_11_2[0]\, C - => N_562, Y => N_3818); - - \r.xaddress[8]\ : DFN1 - port map(D => N_716, CLK => lclk_c, Q => \addr[8]\); - - \r.dstate_RNICU24E[1]\ : OR2B - port map(A => \edata[13]\, B => ddatainv_0_4_sqmuxa, Y => - \edata_m_0_i[13]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_24\ : NOR3C - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_21, B => - vaddr_1_sqmuxa_0_a2_4_m1_e_20, C => - vaddr_1_sqmuxa_0_a2_4_m1_e_22, Y => - \vaddr_1_sqmuxa_0_a2_4_m1_e_24\); - - \r.vaddr[18]\ : DFN1E1 - port map(D => maddress(18), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[18]\); - - \r.wb.addr_RNO[30]\ : AO1B - port map(A => \mmudco_m_0[106]\, B => N_2703_i_0, C => - \addr_1_1_iv_2[30]\, Y => \addr_1[30]\); - - \r.dstate_0_RNI1JGE7_4[2]\ : AOI1B - port map(A => diagdata_12, B => \dstate_0[2]\, C => N_160, - Y => \rdatav_0_1_0_iv_0_3[12]\); - - \r.dlock_RNIF7I8\ : OR2A - port map(A => read, B => dlock, Y => mmudci_read_1_1_0_a2_0); - - \r.wb.addr_RNO_1[1]\ : AOI1B - port map(A => \paddress[1]\, B => N_2165_0, C => - \mmudco_m[77]\, Y => \addr_1_1_iv_0[1]\); - - \r.dstate_RNO_0[6]\ : OR2B - port map(A => un1_m0_2_0_d0, B => \dstate[6]\, Y => N_3671); - - \r.wb.addr_RNO_1[12]\ : NOR3C - port map(A => N_277, B => \addr_1_1_iv_0_0[12]\, C => N_280, - Y => \addr_1_1_iv_0_2[12]\); - - \r.mmctrl1.ctx_0_0_RNIA366[4]\ : XNOR2 - port map(A => dataout(32), B => \ctx_0[4]\, Y => ctx_4_i); - - \r.faddr_RNI4DPMS[4]\ : AO1D - port map(A => eaddress_7, B => N_195, C => N_3291, Y => - \address_i_0[7]\); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_5[10]\ : OR2B - port map(A => \addr[10]\, B => N_3796, Y => N_3725); - - \r.dstate_RNIDOQK8[1]\ : MX2B - port map(A => maddress(4), B => edata2_0_iv(4), S => - edata_0_sqmuxa_i_0, Y => \edata[4]\); - - \r.dstate_i_RNIVTDIK92[8]\ : OR2A - port map(A => edata2_0_iv(23), B => \N_3254_0\, Y => N_3878); - - \r.mmctrl1.pso_RNO\ : NOR2B - port map(A => rst, B => N_2674, Y => pso_RNO); - - \r.wb.data1_RNO[27]\ : MX2A - port map(A => N_2125, B => maddress(27), S => - req_0_sqmuxa_1, Y => \data1_1[27]\); - - \r.dstate_RNO_10[4]\ : NOR2A - port map(A => dstate_tr16_13_0_0_a2_0_0, B => read_0, Y => - dstate_tr16_13_0_0_a2_0_1); - - \r.xaddress_RNI0G5H[0]\ : NOR2A - port map(A => N_3764, B => \addr[0]\, Y => N_3782); - - \r.dstate_RNO_8[1]\ : OR2A - port map(A => dstate_tr22_15_a2_9_0, B => N_3569_2, Y => - N_3569); - - \r.wb.data1_RNO[10]\ : MX2A - port map(A => N_2108, B => maddress(10), S => - req_0_sqmuxa_1_0, Y => \data1_1[10]\); - - \r.wb.data2_RNI2UI7[5]\ : OR2B - port map(A => \data2[5]\, B => rdatav_012, Y => N_3396); - - \r.paddress[2]\ : DFN1E1 - port map(D => un1_m0_2_3, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[2]\); - - \r.dstate_i_2_RNIP3942[8]\ : OR2B - port map(A => un1_m0_2_60, B => miscdata_4_sqmuxa, Y => - \mmudco_m[61]\); - - \r.xaddress_RNI64V9992[29]\ : OR2B - port map(A => \addr[29]\, B => \N_330\, Y => N_258); - - \r.wb.data2[11]\ : DFN1E1 - port map(D => \data2_1[11]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[11]\); - - \r.wb.addr[27]\ : DFN1 - port map(D => \addr_1[27]\, CLK => lclk_c, Q => - \address[27]\); - - \r.dstate_i_RNI0P84892[8]\ : OR2A - port map(A => N_3781, B => un10_m_en, Y => N_3668); - - \r.dstate_RNIUQT5G[1]\ : MX2 - port map(A => maddress(29), B => edata2_iv_i_0(29), S => - edata_0_sqmuxa_i, Y => \edata[29]\); - - \r.xaddress[1]\ : DFN1 - port map(D => N_709, CLK => lclk_c, Q => \addr[1]\); - - \r.valid_0_RNO[6]\ : OA1B - port map(A => hit_1_iv_0_a2_0_0, B => twrite_14, C => - N_2366, Y => \valid_0_1[6]\); - - \r.faddr_RNI7MK691[6]\ : MX2A - port map(A => \taddr_7[11]\, B => \faddr[6]\, S => flush_0, - Y => faddr_RNI7MK691(6)); - - \r.vaddr[16]\ : DFN1E1 - port map(D => maddress(16), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[16]\); - - \r.wb.addr[17]\ : DFN1 - port map(D => \addr_1[17]\, CLK => lclk_c, Q => - \address[17]\); - - \r.dstate_i_2_RNISK8N1_19[8]\ : OR2B - port map(A => dataout(35), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m_0[105]\); - - \r.ready_RNO_5\ : OA1 - port map(A => N_572, B => ready_RNO_7, C => N_481, Y => - ready_0_sqmuxa_0_a2_1_0); - - \r.dstate_i_2_RNISK8N1_12[8]\ : OR2B - port map(A => dataout_0(11), B => rdatasel_1_sqmuxa_1, Y - => N_204); - - \r.wb.addr_RNO_2[1]\ : OR2B - port map(A => \address[1]\, B => dstate_19, Y => - \addr_m[1]\); - - \r.mexc_RNIDIK9\ : NOR2B - port map(A => mexc_0, B => rdatav_012_0, Y => - mexc_1_m_0_a2_3_0); - - \rdatasel_1_i_a3_2[7]\ : NOR3A - port map(A => asi(1), B => asi(3), C => - \rdatasel_1_i_a3_2_0[7]_net_1\, Y => N_2047); - - \r.wb.addr_RNO_0[20]\ : NOR3C - port map(A => N_3860, B => \addr_1_1_iv_0_0[20]\, C => - N_3863, Y => \addr_1_1_iv_0_2[20]\); - - \r.vaddr[19]\ : DFN1E1 - port map(D => maddress(19), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[19]\); - - \r.req_RNI4F042\ : OR2 - port map(A => \req\, B => N_510, Y => N_585); - - \r.read_RNIHTEII\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_24, Y => - \mcdo_m_i[24]\); - - \r.dstate_RNIJ4ON8[6]\ : AOI1B - port map(A => mexc_1_m_0_2000_tz_1, B => mexc_1_m_0_a2_1_0, - C => mexc_0_sqmuxa_1, Y => mexc_1_m_0_2000_0); - - \r.dstate_i_RNI4EBC7[8]\ : OR2B - port map(A => \vmask_0_5[7]\, B => \dstate_RNIR2CO3[4]\, Y - => N_3286_1); - - \r.xaddress_RNI1D927S2[20]\ : OR3C - port map(A => N_156, B => N_155, C => N_157, Y => - xaddress_RNI1D927S2(20)); - - \r.read_RNI75LJ31\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[22]\, B => - \mcdo_m_i[22]\, C => \ddatainv_0_1_0_iv_1[22]\, Y => - read_RNI75LJ31); - - \dctrl.0.genmux.un6_validrawv_3\ : MX2C - port map(A => N_2012, B => N_2013, S => maddress(3), Y => - N_2014); - - \r.wb.lock_RNO_6\ : NOR2B - port map(A => hold_0, B => lock, Y => lock_1_iv_0_a2_1_0); - - \r.wb.data2_RNI4BOB[21]\ : OR2B - port map(A => \data2[21]\, B => rdatav_012, Y => - \data2_m[21]\); - - \r.wb.addr_RNO_4[11]\ : MX2 - port map(A => \paddress[11]\, B => \addr[11]\, S => N_484_0, - Y => \addr_1_1_iv_0_a3_0[11]\); - - \r.mmctrl1.ctx_RNI63MN[0]\ : MX2 - port map(A => \ctx[0]\, B => maddress(0), S => ctx_1_sqmuxa, - Y => N_2663); - - \dctrl.rdatav_0_1_0_iv_i_a2_2_0[1]\ : NOR2A - port map(A => maddress(9), B => maddress(10), Y => - un30_m_en_0); - - \r.xaddress_RNIQF6M2_2[0]\ : OR2B - port map(A => dataout(25), B => N_2088, Y => - \dcramo_m_i[249]\); - - \r.valid_0[3]\ : DFN1E0 - port map(D => \valid_0_1[3]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[3]\); - - \r.dstate_0_RNIO8S3OI[7]\ : AOI1B - port map(A => \dstate_ns_0_0_1[1]\, B => N_3668, C => rst, - Y => \dstate_nss[1]\); - - \r.wb.addr_RNO_2[12]\ : OR2B - port map(A => maddress(12), B => addr_2_sqmuxa, Y => N_277); - - \r.wb.addr_RNO_1[5]\ : AOI1B - port map(A => \addr_1_1_iv_0_a3_0_0[5]\, B => - \dstate_RNIP22L4[7]\, C => N_289, Y => - \addr_1_1_iv_0_0[5]\); - - \r.paddress[23]\ : DFN1E1 - port map(D => N_236_0, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[23]\); - - \dctrl.0.un1_dci_18_0\ : XNOR2 - port map(A => dataout_0(26), B => maddress(30), Y => - un1_dci_18_i); - - \r.xaddress_RNI6JA5A[1]\ : OR2B - port map(A => \edata[4]\, B => ddatainv_0_0_sqmuxa, Y => - \edata_m_4_i[4]\); - - \r.wb.data2[25]\ : DFN1E1 - port map(D => \data2_1[25]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[25]\); - - \r.wb.addr_RNO_0[22]\ : NOR3C - port map(A => N_3871, B => \addr_1_1_iv_0_0[22]\, C => - N_185, Y => \addr_1_1_iv_0_2[22]\); - - \r.mmctrl1.ctx_RNINUJ8[5]\ : XNOR2 - port map(A => dataout(33), B => \ctx[5]\, Y => N_103_i_i); - - \r.holdn_RNO_13\ : NOR3C - port map(A => rst, B => holdn_0_0, C => dstate_0_sqmuxa, Y - => holdn_0_1); - - \r.xaddress_RNIEV5QJ[0]\ : AOI1B - port map(A => dataout_0(28), B => N_2088, C => - \edata_m_i[28]\, Y => \ddatainv_0_1_0_iv_0[28]\); - - \r.mmctrl1.ctx_0_0_RNI34KT[4]\ : NOR3C - port map(A => ctx_4_i, B => ctx_2_i, C => ctx_NE_3, Y => - ctx_NE_5); - - \r.wb.data2_RNIPV0SB[7]\ : NOR3B - port map(A => \rdatav_0_1_1_iv_0_2[7]\, B => \mmudco_m[41]\, - C => \rdatav_0_1_6[3]\, Y => \rdatav_0_1_1_iv_0_4[7]\); - - \r.mmctrl1.ctx_0_0_RNIP1QE[1]\ : XA1A - port map(A => \ctx_0[1]\, B => dataout(29), C => ctx_0_i, Y - => ctx_NE_1); - - \r.dstate_i_2_RNITQRS1_0[8]\ : NOR2 - port map(A => rdatasel_4_sqmuxa, B => un30_m_en, Y => - miscdata_3_sqmuxa); - - \r.faddr_RNIHMO9[5]\ : NOR2A - port map(A => \un1_p0_2_0[498]\, B => \faddr[5]\, Y => - N_3295); - - \r.cctrl.ics_RNIQ4MU1[1]\ : OR2B - port map(A => \ics[1]\, B => rdatav_0_0_sqmuxa, Y => N_3231); - - \un1_r.faddr_I_24\ : XOR2 - port map(A => N_9_0, B => \faddr[5]\, Y => I_24_1); - - \r.wb.data2_RNO[28]\ : MX2 - port map(A => edata2_iv_i_0(28), B => hrdata_23, S => - \dstate_0[7]\, Y => \data2_1[28]\); - - \r.mmctrl1.ctxp[24]\ : DFN1E1 - port map(D => maddress(26), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[24]\); - - \r.dstate_RNIK6UF4[0]\ : OA1C - port map(A => N_582, B => N_3665_1, C => \dstate[0]\, Y => - un1_taddr_1_sqmuxa); - - \r.dstate_i_RNIO3TO792[8]\ : NOR3 - port map(A => N_533, B => \N_121\, C => read_0, Y => - un19_m_en_m_2); - - \r.dstate_0_RNIJM7GP[2]\ : OR3C - port map(A => \rdatav_0_1_1_iv_5[17]\, B => - \rdatav_0_1_1_iv_4[17]\, C => \mcdo_m_0[17]\, Y => - data_0_17); - - N_3503_i_i : OR2B - port map(A => asi(1), B => asi(0), Y => N_3595); - - \r.faddr_RNIEHR0O[1]\ : MX2 - port map(A => \taddr_7[6]\, B => \faddr[1]\, S => - \un1_p0_2_0[498]\, Y => faddr_RNIEHR0O(1)); - - \r.wb.addr_RNO_1[11]\ : AOI1B - port map(A => un1_m0_2_12, B => addr_1_sqmuxa_0, C => - \addr_1_1_iv_0_0[11]\, Y => \addr_1_1_iv_0_1[11]\); - - \r.stpend_RNIPT84NG3\ : OA1A - port map(A => un1_m0_2_108, B => lock, C => N_485, Y => - req16); - - \r.dstate_RNIIRS9[2]\ : OR2B - port map(A => diagrdy, B => \dstate[2]\, Y => N_135); - - \dctrl.mexc_1_m_0_a2_1_0\ : AO1C - port map(A => size_0_0, B => size_1_d0, C => N_3253_i, Y - => mexc_1_m_0_a2_1_0); - - \r.valid_0_RNO_1[1]\ : OR2B - port map(A => \dstate_i_1[8]\, B => N_95, Y => - \valid_0_1_1_a4_1_0[1]\); - - \r.xaddress_RNISBQK4[3]\ : MX2C - port map(A => maddress(3), B => \addr[3]\, S => - un1_taddr_1_sqmuxa, Y => N_2230); - - \r.wb.addr_RNO_1[29]\ : AND2 - port map(A => N_264, B => \addr_1_1_iv_0_1[29]\, Y => - \addr_1_1_iv_0_2[29]\); - - \r.read_RNIEKS231\ : OR3 - port map(A => \mcdo_m[12]\, B => \edata_m_1[4]\, C => - \ddatainv_0_1_1_iv_0[12]\, Y => read_RNIEKS231); - - \r.wb.addr_RNO_6[15]\ : OR2B - port map(A => N_351, B => addr_1_sqmuxa, Y => - \mmudco_m[17]\); - - \dctrl.0.genmux.un6_validrawv_7\ : MX2 - port map(A => N_2014, B => N_2017, S => maddress(2), Y => - un6_validrawv); - - \r.wb.data2_RNI9RN44[29]\ : NOR3C - port map(A => \dcramo_m[125]\, B => \data2_m[29]\, C => - \mmudco_m[72]\, Y => \rdatav_0_1_0_iv_1[29]\); - - \r.wb.addr_RNO[29]\ : AO1B - port map(A => \addr_1_1_iv_0_a3_2_0[29]\, B => N_2720, C - => \addr_1_1_iv_0_2[29]\, Y => \addr_1[29]\); - - \r.dstate_RNI86TMJ[1]\ : AOI1B - port map(A => \edata[24]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[248]\, Y => \ddatainv_0_1_0_iv_0[24]\); - - \r.cctrl.dcs_RNI4NCI3[0]\ : OR3A - port map(A => \dstate[4]\, B => \dcs[0]\, C => N_580, Y => - N_3710); - - \r.wb.data1_RNO_0[9]\ : MX2C - port map(A => edata2_0_iv(9), B => \data2[9]\, S => N_3331, - Y => N_2107); - - \r.mmctrl1.ctxp_RNI5QJ12[29]\ : OR2B - port map(A => \ctxp[29]\, B => N_3344_i_0, Y => - \ctxp_m[29]\); - - \r.flush2_RNID91C\ : NOR2 - port map(A => \un1_p0_2_0[498]\, B => flush2, Y => - hit_1_iv_0_a2_0_0); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_3[10]\ : OR2B - port map(A => \un1_m0_2[86]\, B => addr_1_sqmuxa_2, Y => - N_3641); - - \v.burst_2_sqmuxa_m8_0_a4_0_RNO\ : NOR2A - port map(A => burst_2_sqmuxa_m8_0_a4_0_1, B => accexc_6, Y - => burst_2_sqmuxa_m8_0_a4_0_2); - - \r.xaddress_RNIC5A27S2[21]\ : OR3C - port map(A => N_3894, B => N_232, C => \dci_m[93]\, Y => - xaddress_RNIC5A27S2(21)); - - \r.dstate_RNIM2RIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[4]\, Y => \ddatainv_0_1_0_iv_1[20]\); - - \r.wb.data1_RNO_0[10]\ : MX2C - port map(A => edata2_0_iv(10), B => \data2[10]\, S => - N_3331_0, Y => N_2108); - - \r.valid_0_RNO[0]\ : AO1B - port map(A => dataout_0(0), B => N_88, C => N_3377, Y => - \valid_0_1[0]\); - - \r.dstate_0_RNI37JF4[7]\ : AOI1B - port map(A => burst_0_sqmuxa, B => \dstate_0[7]\, C => - addr_3_sqmuxa, Y => dstate_19_4); - - \un1_v.cctrlwr19_2_0_o2_0\ : OR2A - port map(A => cctrlwr19_2_0_o2_0_0, B => N_227, Y => N_494); - - \r.dstate_RNIDJ8UEJ[4]\ : AO1A - port map(A => N_3248, B => mexc, C => \dstate_RNIR2CO3[4]\, - Y => N_3315); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_21\ : NOR3B - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_13, B => - vaddr_1_sqmuxa_0_a2_4_m1_e_12, C => eaddress_13, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_21); - - \r.wb.data2_RNI1QI7[4]\ : OR2B - port map(A => \data2[4]\, B => rdatav_012_0, Y => - \data2_m[4]\); - - \r.dstate_RNIEARL2[2]\ : NOR2A - port map(A => N_2042, B => \dstate[2]\, Y => - rdatav_0_6_sqmuxa_3_0); - - \r.wb.addr_RNO_0[8]\ : NOR3C - port map(A => \mmudco_m[10]\, B => \addr_1_1_iv_0[8]\, C - => \dci_m[16]\, Y => \addr_1_1_iv_2[8]\); - - \r.read_RNIG3IS2\ : OR3B - port map(A => N_143, B => N_84, C => N_522, Y => N_178); - - \r.wb.data1_RNO[18]\ : MX2A - port map(A => N_2116, B => maddress(18), S => - req_0_sqmuxa_1_0, Y => \data1_1[18]\); - - \r.flush_0_1_RNIAOU5992\ : OR2B - port map(A => maddress(30), B => \N_329\, Y => N_267); - - \r.mmctrl1.ctxp_RNINPF32[7]\ : OR2B - port map(A => \ctxp[7]\, B => N_3344_i_0, Y => \ctxp_m[7]\); - - \r.mmctrl1.ctxp_RNIORPUB[14]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_2[16]\, B => \mmudco_m[59]\, - C => \ctxp_m[14]\, Y => \rdatav_0_1_1_iv_4[16]\); - - \r.dstate_RNO_3[6]\ : NOR3B - port map(A => N_481, B => N_549, C => N_495, Y => - \dstate_ns_0_0_a2_0_1[2]\); - - \r.wb.data2_RNI23SU1[9]\ : NOR2B - port map(A => \data2_m[9]\, B => \dcramo_m_0[105]\, Y => - \rdatav_0_1_0_iv_0[9]\); - - \r.wb.data2[8]\ : DFN1E1 - port map(D => N_3270, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[8]\); - - \r.wb.data1_RNO[0]\ : MX2A - port map(A => N_2098, B => maddress(0), S => req_0_sqmuxa_1, - Y => \data1_1[0]\); - - \r.dstate_RNI1JGE7_3[2]\ : AOI1B - port map(A => dataout(7), B => rdatav_0_6_sqmuxa_0, C => - N_3312, Y => \rdatav_0_1_1_iv_0_6[7]\); - - \r.wb.data1_RNO_0[4]\ : MX2B - port map(A => edata2_0_iv(4), B => \data2[4]\, S => N_3331, - Y => N_2102); - - \r.dstate_0_RNI2DT77_5[2]\ : AND2 - port map(A => \ico_m[164]\, B => \dcramo_m_0[254]\, Y => - \rdatav_0_1_0_iv_3[30]\); - - \r.wb.data2_RNI0MI7[3]\ : OR2B - port map(A => \data2[3]\, B => rdatav_012, Y => N_3403); - - \dctrl.hit_1_i_a2_0_a2\ : OR2A - port map(A => N_3780, B => N_490, Y => un10_m_en); - - \r.wb.data2_RNIJ45I3[10]\ : NOR3C - port map(A => N_3306, B => N_3304, C => N_167, Y => - \rdatav_0_1_0_iv_0_1[10]\); - - \r.stpend_RNIPTTO1\ : OR2B - port map(A => ready, B => stpend, Y => stpend_0_sqmuxa); - - \r.dstate_i_RNIASSRO92[8]\ : MX2A - port map(A => edata2_0_iv(6), B => \vmask_0_6[6]\, S => - \dstate_i_RNII68N892_0[8]\, Y => N_2385); - - \r.wb.size[1]\ : DFN1E0 - port map(D => N_654, CLK => lclk_c, E => - \dstate_RNI5GFM4[5]\, Q => \size_1[1]\); - - \r.wb.addr_RNO_2[11]\ : OR2B - port map(A => \address[11]\, B => N_514, Y => N_285); - - \r.dstate_0_RNIIC256_2[7]\ : OR2B - port map(A => dataout(24), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[248]\); - - \r.wb.addr_RNO_0[21]\ : NOR3C - port map(A => N_3638, B => \addr_1_1_iv_0_0[21]\, C => - N_3718, Y => \addr_1_1_iv_0_2[21]\); - - \r.flush_0_1_RNI30N4992_0\ : NOR3A - port map(A => \dstate_i_RNII68N892_0[8]\, B => - \un1_p0_2_0[498]\, C => N_3833, Y => \N_329\); - - \dctrl.un1_r.cctrl.dcs_1_i_a2_0_0_a2\ : OR2 - port map(A => asi(0), B => N_519, Y => N_223); - - \r.wb.addr_RNO_5[28]\ : MX2 - port map(A => \paddress[28]\, B => \addr[28]\, S => N_484_0, - Y => N_3839); - - \r.size_RNI1K5H[0]\ : OR2B - port map(A => \size[0]\, B => N_3805, Y => N_3599); - - \r.dstate_RNO_3[0]\ : NOR2B - port map(A => hit, B => \dstate[4]\, Y => - \dstate_ns_0_0_a2_0_1[8]\); - - \r.wb.data2_RNO[2]\ : MX2A - port map(A => edata2_0_iv(2), B => hrdata_0_2, S => - \dstate[7]\, Y => \data2_1[2]\); - - \r.dstate_RNI7LSK8[1]\ : MX2B - port map(A => maddress(7), B => edata2_0_iv(7), S => - edata_0_sqmuxa_i, Y => \edata[7]\); - - \r.dstate_0_RNIPG8A6[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_0_10, Y => N_3305); - - \r.wb.data2_RNIOL4H9[4]\ : NOR3C - port map(A => \dcramo_m[100]\, B => \rdatav_0_1_0_iv_1[4]\, - C => \rdatav_0_1_0_iv_3[4]\, Y => \rdatav_0_1_0_iv_4[4]\); - - \r.wb.addr_RNO_4[9]\ : MX2 - port map(A => \paddress_0[9]\, B => \addr[9]\, S => N_484, - Y => \paddress[9]\); - - \r.dstate_RNI0P3L7_0[2]\ : AOI1B - port map(A => diagdata_18, B => \dstate[2]\, C => - \dcramo_m_0[242]\, Y => \rdatav_0_1_0_iv_4[18]\); - - \dctrl.0.un1_dci_5_0_RNIKH8G\ : NOR3C - port map(A => un1_dci_15_i, B => un1_dci_14_i, C => - un1_dci_NE_3, Y => un1_dci_NE_11); - - \r.wb.addr_RNO_2[5]\ : OR2B - port map(A => \address[5]\, B => dstate_19, Y => N_290); - - \r.xaddress_RNI2052[4]\ : NOR2 - port map(A => \addr[4]\, B => \addr[2]\, Y => - flush_0_sqmuxa_0_o3_i_o2_2); - - \r.size_RNIFQT5[0]\ : OR2B - port map(A => \size_0[1]\, B => \size[0]\, Y => N_421); - - \un1_v.holdn_3_sqmuxa_0_0_a2_3\ : OR2B - port map(A => asi(1), B => N_481, Y => N_3742); - - \r.wb.addr_RNO_2[26]\ : OR2B - port map(A => maddress(26), B => addr_2_sqmuxa, Y => - \dci_m[34]\); - - \r.dstate_RNO_9[5]\ : OR3A - port map(A => N_2996_8, B => N_3511, C => ready, Y => - N_3035); - - \r.flush_RNINJ2O3\ : NOR3C - port map(A => mexc_1_m_0_a2_0, B => mexc_1_m_0_a2_0_1, C - => mexc_1_m_0_a2_5_0, Y => mexc_1_m_0_2000_tz_1); - - \r.ready_RNIQ1GU1\ : OR2A - port map(A => N_72_i, B => ready_0, Y => N_566); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNI6AN51\ : OR3C - port map(A => N_481, B => N_549, C => N_502, Y => N_3746); - - \r.xaddress_RNO[2]\ : OR3B - port map(A => N_652_i, B => N_3698, C => N_84, Y => - \xaddress_1[2]\); - - \r.wb.data1[14]\ : DFN1E0 - port map(D => \data1_1[14]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_2); - - \dctrl.v.burst_16_m\ : NAND2 - port map(A => addr_1_sqmuxa_1, B => burst_16_m_0, Y => - burst_16_m); - - \r.dstate_RNI3HNSH[7]\ : MX2C - port map(A => N_3338, B => hrdata_0_d0, S => \dstate[7]\, Y - => N_3341); - - \r.dstate_i_2_RNILJ842[8]\ : OR2B - port map(A => un1_m0_2_56, B => miscdata_4_sqmuxa, Y => - \mmudco_m[57]\); - - \r.dstate_RNI0Q09A[1]\ : NOR2B - port map(A => \edata[1]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[1]\); - - \r.asi_RNIKJBG[1]\ : NOR3A - port map(A => \ctx\, B => \asi_0[1]\, C => \asi_0[0]\, Y - => un1_m_en_2); - - \r.wb.addr_RNO_1[8]\ : OR2B - port map(A => un1_m0_2_9, B => addr_1_sqmuxa, Y => - \mmudco_m[10]\); - - \r.wb.addr[20]\ : DFN1 - port map(D => \addr_1[20]\, CLK => lclk_c, Q => - \address[20]\); - - \r.dstate_0_RNIPI7EK[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_0_3[12]\, B => - \rdatav_0_1_0_iv_0_2[12]\, C => N_158, Y => data_0_12); - - \dctrl.vmaskraw_1_i_o2_i_o2_0[1]\ : AO1D - port map(A => read_1, B => N_507, C => maddress(2), Y => - N_568); - - \r.dstate_i_2_RNITQRS1_4[8]\ : NOR2A - port map(A => N_3321, B => maddress(8), Y => - miscdata_0_sqmuxa); - - N_68_i_i_o2 : OR2B - port map(A => asi(2), B => asi(1), Y => N_590); - - \r.dstate_RNI26UQ_0[1]\ : OR3B - port map(A => edata_0_sqmuxa_1, B => N_3443_i, C => - \dstate[1]\, Y => edata_0_sqmuxa_i); - - \r.dstate_2_RNISOJVV[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[25]\, B => - \rdatav_0_1_0_iv_2[25]\, C => \mcdo_m_0[25]\, Y => - data_0_25); - - \r.nomds_RNIRCHA\ : OR2A - port map(A => hold_0, B => nomds, Y => N_496); - - \r.wb.addr[10]\ : DFN1 - port map(D => \addr_1[10]\, CLK => lclk_c, Q => - \address[10]\); - - \r.dstate_tr0_32_0_0_a3_0_o2\ : OR2A - port map(A => asi(4), B => asi(1), Y => N_519); - - \r.nomds_RNIS8RHB\ : OR3B - port map(A => mexc_0_sqmuxa_1, B => - \dstate_ns_i_a4_i_o2_9_2[0]\, C => N_496, Y => N_3709); - - \r.mmctrl1.ctx[6]\ : DFN1 - port map(D => \ctx_RNIN0CR[6]\, CLK => lclk_c, Q => - \ctx[6]\); - - \r.dstate_RNI7O47A[1]\ : NOR2B - port map(A => \edata[1]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[1]\); - - \r.wb.addr_RNO[6]\ : OR3C - port map(A => \addr_1_1_iv_0_2[6]\, B => - \addr_1_1_iv_0_1[6]\, C => N_3627, Y => \addr_1[6]\); - - \r.xaddress_RNIMRB5A[1]\ : OR2B - port map(A => \edata[6]\, B => ddatainv_0_0_sqmuxa, Y => - \edata_m_4_i[6]\); - - \r.wb.data2_RNIUIRU1[5]\ : AOI1B - port map(A => dataout(33), B => rdatasel_3_sqmuxa, C => - N_3396, Y => \rdatav_0_1_1_iv_i_a2_0[5]\); - - \r.xaddress_RNI5SAJ[4]\ : NOR2 - port map(A => \addr[4]\, B => N_3800, Y => N_3657); - - \r.mmctrl1.ctxp[23]\ : DFN1E1 - port map(D => maddress(25), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[23]\); - - \r.wb.data2_RNILKUT5[17]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_0[17]\, B => - rdatav_0_2_sqmuxa, C => \dcramo_m[113]\, Y => - \rdatav_0_1_1_iv_2[17]\); - - \r.dstate_RNO_0[1]\ : AOI1B - port map(A => N_3545, B => N_3089_7, C => dstate_tr22_1, Y - => dstate_tr22_2); - - \r.xaddress_RNITMH17S2[12]\ : OR3C - port map(A => N_148, B => N_146, C => \dci_m[84]\, Y => - xaddress_RNITMH17S2(12)); - - \r.dstate_RNIC3BVC[1]\ : AO1 - port map(A => \edata[7]\, B => ddatainv_0_3_sqmuxa, C => - \dcramo_m[231]\, Y => \ddatainv_0_1_1_iv_0[7]\); - - \r.wb.data2_RNO[17]\ : MX2 - port map(A => edata2_0_iv(17), B => hrdata_0_17, S => - \dstate_1[7]\, Y => \data2_1[17]\); - - \r.mmctrl1.ctx_RNIKUJ8[2]\ : XNOR2 - port map(A => dataout(30), B => \ctx[2]\, Y => ctx_2_i); - - \r.faddr[1]\ : DFN1E0 - port map(D => \faddr_1[1]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[1]\); - - \r.faddr_RNIP7K31[6]\ : OA1 - port map(A => I_31_1, B => flush_0_sqmuxa_0, C => rst, Y - => flush_0_0); - - \r.dstate_RNO_3[4]\ : NOR3C - port map(A => \dstate_RNO_6[4]\, B => \dstate_ns_0_0[4]\, C - => \dstate_RNO_8[4]\, Y => \dstate_ns_0_2[4]\); - - \r.valid_0[4]\ : DFN1E0 - port map(D => \valid_0_1[4]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[4]\); - - \r.mmctrl1.ctxp_RNISLJ12[13]\ : OR2B - port map(A => \ctxp[13]\, B => N_3344_i_0, Y => - \ctxp_m[13]\); - - \r.dstate_2_RNI75818[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_16, Y => - \mcdo_m_0[16]\); - - \r.wb.data2_RNI8BOB[25]\ : OR2B - port map(A => \data2[25]\, B => rdatav_012, Y => - \data2_m[25]\); - - \r.valid_0_RNIT2NB[5]\ : NOR2B - port map(A => \valid_0[5]\, B => hit, Y => N_96); - - \r.xaddress_RNIGOTFII[26]\ : AO1 - port map(A => \addr[26]\, B => \N_330\, C => N_245, Y => - newtag_1_0_8); - - \r.wb.addr_RNO_5[27]\ : OR2B - port map(A => \dstate_RNIP22L4[7]\, B => N_674, Y => N_249); - - \r.wb.addr[22]\ : DFN1 - port map(D => \addr_1[22]\, CLK => lclk_c, Q => - \address[22]\); - - \r.flush_RNI1J929\ : NOR3A - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - maddress(8), Y => N_3289); - - \r.dstate_RNI59OG3[4]\ : OR2B - port map(A => \dstate[4]\, B => dwrite_1_sqmuxa, Y => - data2_0_sqmuxa); - - \r.wb.data2[20]\ : DFN1E1 - port map(D => \data2_1[20]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[20]\); - - \r.mmctrl1.ctxp_RNIKDF32[4]\ : OR2B - port map(A => \ctxp[4]\, B => N_3344_i_0_0, Y => - \ctxp_m[4]\); - - \r.faddr_RNO[3]\ : NOR3C - port map(A => rst, B => flush_0, C => I_13_5, Y => - \faddr_1[3]\); - - \r.dstate_tr8_9_10_i_o2_i_a2_i_o2\ : OR2A - port map(A => N_549, B => N_537, Y => N_666); - - \r.dstate_RNO_4[1]\ : OAI1 - port map(A => N_3787, B => dstate_tr22_15_a2_4_1, C => - e_0_0_RNIIAUC4Q1, Y => N_3546); - - \r.mmctrl1.e_RNI30A81\ : OR2B - port map(A => \e\, B => un10_m_en, Y => un47_m_en); - - \r.wb.data2_RNO[24]\ : MX2 - port map(A => edata2_iv_i_0(24), B => hrdata_0_24, S => - \dstate_1[7]\, Y => \data2_1[24]\); - - \r.wb.data2[17]\ : DFN1E1 - port map(D => \data2_1[17]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[17]\); - - \r.wb.addr[12]\ : DFN1 - port map(D => \addr_1[12]\, CLK => lclk_c, Q => - \address[12]\); - - \r.read_RNI8HVEI\ : NOR2B - port map(A => \N_425\, B => hrdata_0_2, Y => \mcdo_m[2]\); - - \dctrl.rdatav_0_1_0_iv[31]\ : NAND2 - port map(A => \mcdo_m_0[31]\, B => \rdatav_0_1_0_iv_4[31]\, - Y => data_0_31); - - \dctrl.0.un1_dci_NE_8\ : XA1A - port map(A => maddress(31), B => dataout_0(27), C => - N_149_i_i, Y => un1_dci_NE_8); - - \r.wb.addr_RNO_0[14]\ : NOR3C - port map(A => N_3636, B => \addr_1_1_iv_0_0[14]\, C => - N_3728, Y => \addr_1_1_iv_0_2[14]\); - - \r.flush_RNICQGM51\ : NOR3A - port map(A => twrite_14_iv_0_a2_a1_2, B => me_nullify2_1_2, - C => nullify2_0_sqmuxa, Y => flush_RNICQGM51); - - \r.dstate_RNIGI4QJ[1]\ : AOI1B - port map(A => \edata[30]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[254]\, Y => \ddatainv_0_1_0_iv_0[30]\); - - \r.read_RNI0IQ7R\ : OR3 - port map(A => \mcdo_m[2]\, B => \edata_m_0[2]\, C => - \ddatainv_0_1_1_iv_0[2]\, Y => read_RNI0IQ7R); - - \r.xaddress_RNI00V9992[16]\ : OR2B - port map(A => \addr[16]\, B => \N_330\, Y => N_240); - - \r.cctrl.ifrz_RNITGHR1\ : OR2B - port map(A => ifrz, B => rdatav_0_0_sqmuxa, Y => ifrz_m); - - \r.dstate_0_RNI1JGE7[2]\ : AOI1B - port map(A => diagdata_19, B => \dstate_0[2]\, C => - \dcramo_m_0[243]\, Y => \rdatav_0_1_0_iv_4[19]\); - - \r.wb.data1_RNO[23]\ : MX2A - port map(A => N_2121, B => maddress(23), S => - req_0_sqmuxa_1_0, Y => \data1_1[23]\); - - \r.wb.data2_RNI30132[24]\ : NOR2B - port map(A => \data2_m[24]\, B => \dcramo_m[120]\, Y => - \rdatav_0_1_0_iv_0[24]\); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0_RNO[3]\ : AND2 - port map(A => N_3443_i, B => \addr[3]\, Y => - \vmaskraw_1_i_o2_i_a3_0_a2_0_0[3]\); - - \r.xaddress_RNI1I3MQ1[0]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[28]\, B => - \mcdo_m_i[28]\, C => \ddatainv_0_1_0_iv_1[28]\, Y => - xaddress_RNI1I3MQ1(0)); - - \r.wb.addr_RNO_4[6]\ : OR2B - port map(A => \address[6]\, B => dstate_19, Y => N_3733); - - \r.dstate_i_1_RNISU8B9S1[8]\ : NOR3C - port map(A => N_126, B => N_91, C => N_3197, Y => N_12_i_0); - - \r.vaddr[15]\ : DFN1E1 - port map(D => maddress(15), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[15]\); - - \r.mmctrl1.ctxp[8]\ : DFN1E1 - port map(D => maddress(10), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[8]\); - - \r.wb.addr_RNO_6[6]\ : OR2B - port map(A => un1_m0_2_7, B => addr_1_sqmuxa, Y => N_3732); - - \r.cctrl.burst_RNO_0\ : MX2 - port map(A => maddress(16), B => \burst_0\, S => \N_523\, Y - => N_2629); - - \r.wb.addr_RNO_3[7]\ : AOI1B - port map(A => un1_m0_2_8, B => addr_1_sqmuxa_0, C => - \addr_1_1_iv_0_0[7]\, Y => \addr_1_1_iv_0_1[7]\); - - \r.wb.addr_RNO_2[20]\ : NOR2B - port map(A => N_3859, B => N_3862, Y => - \addr_1_1_iv_0_0[20]\); - - \r.read_RNIEEGDD1\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[23]\, B => - \mcdo_m_i[23]\, C => \ddatainv_0_1_0_iv_1[23]\, Y => - read_RNIEEGDD1); - - \r.wb.data1_RNO[3]\ : NOR3 - port map(A => N_3360, B => N_3362, C => N_3363, Y => N_19); - - \r.dstate_0_RNIG0R21[2]\ : NAND2 - port map(A => \dstate_0[2]\, B => diagdata_30, Y => - \ico_m[164]\); - - \r.xaddress_RNIL5KB1[0]\ : AOI1 - port map(A => \addr[0]\, B => N_3764, C => N_3785, Y => - \ddatainv_0_1_0_0[24]\); - - \r.xaddress_RNIJH2O2_10[0]\ : NOR2B - port map(A => dataout(7), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[231]\); - - \r.xaddress_RNICOTFII[24]\ : AO1 - port map(A => \addr[24]\, B => \N_330\, C => N_3892, Y => - newtag_1_0_6); - - \r.xaddress_RNI0SQK4[5]\ : MX2 - port map(A => maddress(5), B => \addr[5]\, S => - un1_taddr_1_sqmuxa, Y => N_2232); - - \r.su_RNI2PIF\ : MX2 - port map(A => msu, B => su_0, S => N_3443_i, Y => su); - - \r.faddr_RNIQHE8[3]\ : NOR2A - port map(A => flush_0, B => \faddr[3]\, Y => N_3287); - - \r.cctrl.ifrz_RNIMLHT3\ : AOI1B - port map(A => un1_m0_2_39, B => miscdata_3_sqmuxa, C => - ifrz_m, Y => \rdatav_0_1_0_iv_3[4]\); - - \r.burst_RNO_3\ : NOR2A - port map(A => N_485, B => N_507, Y => burst_RNO_3); - - \r.wb.addr_RNO_3[6]\ : OR2B - port map(A => \addr[6]\, B => N_3796, Y => N_3731); - - \r.dstate_RNO_3[1]\ : NOR3C - port map(A => \dstate_RNO_5[1]\, B => N_3086_i, C => - dstate_tr22_15_N_10_i, Y => dstate_tr22_1); - - \r.wb.data1_RNO[14]\ : MX2A - port map(A => N_2112, B => maddress(14), S => - req_0_sqmuxa_1_0, Y => \data1_1[14]\); - - \r.read_RNIJH5A\ : NOR2A - port map(A => N_3443_i, B => read, Y => N_3749); - - \r.dstate_RNIEMHMC[1]\ : MX2 - port map(A => maddress(12), B => edata2_0_iv(12), S => - edata_0_sqmuxa_i_0, Y => \edata[12]\); - - \un1_r.faddr_I_30\ : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \faddr[5]\, Y => N_4); - - \r.wb.data2_RNO[21]\ : MX2 - port map(A => edata2_0_iv(21), B => hrdata_0_21, S => - \dstate_2[7]\, Y => \data2_1[21]\); - - \r.mmctrl1.ctxp_RNIEHGVD[5]\ : AOI1B - port map(A => \ctxp[5]\, B => N_3344_i_0_0, C => - \rdatav_0_1_1_iv_0_4[7]\, Y => \rdatav_0_1_1_iv_0_5[7]\); - - \r.dstate_RNO_5[4]\ : NOR3B - port map(A => dstate_tr16_13_0_0_a2_0_1, B => N_114_i_i_0, - C => lock, Y => dstate_tr16_13_0_0_a2_0_3); - - \dctrl.twrite_14_iv_0_o2_a0_RNIVBERA3\ : OR2B - port map(A => twrite_14, B => \dstate_RNIR2CO3[4]\, Y => - N_188); - - \r.paddress[19]\ : DFN1E1 - port map(D => N_415, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[19]\); - - \r.wb.addr_RNO_2[22]\ : NOR2B - port map(A => N_3870, B => N_3873, Y => - \addr_1_1_iv_0_0[22]\); - - \r.holdn_RNO_26\ : AOI1 - port map(A => \dstate_0[7]\, B => N_510, C => \dstate_0[2]\, - Y => holdn_3_sqmuxa_0_0_0); - - \r.wb.addr_RNO_5[14]\ : OR2B - port map(A => un1_m0_2_15, B => addr_1_sqmuxa_0, Y => - N_3729); - - \r.vaddr[21]\ : DFN1E1 - port map(D => maddress(21), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[21]\); - - miscdata_4_sqmuxa_0_a2_0 : NOR2A - port map(A => maddress(10), B => maddress(9), Y => - \miscdata_4_sqmuxa_0_a2_0\); - - \r.wb.addr_RNO_2[8]\ : AOI1B - port map(A => \paddress[8]\, B => \dstate_RNIP22L4[7]\, C - => \mmudco_m[84]\, Y => \addr_1_1_iv_0[8]\); - - miscdata_2_sqmuxa_0_a4_0_a2_0_a3_0 : NOR2A - port map(A => maddress(9), B => maddress(8), Y => - \miscdata_2_sqmuxa_0_a4_0_a2_0_a3_0\); - - \r.wb.data2[0]\ : DFN1E1 - port map(D => \data2_1[0]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[0]\); - - \r.wbinit_RNIA7FN3_0\ : NOR2A - port map(A => N_487, B => dwrite_1_sqmuxa, Y => - addr_1_sqmuxa_0); - - \r.dstate_i_2_RNITQRS1[8]\ : NOR2A - port map(A => \miscdata_4_sqmuxa_0_a2_1\, B => - rdatasel_4_sqmuxa, Y => miscdata_4_sqmuxa); - - \r.wb.data2_RNIUR032[12]\ : NOR2B - port map(A => \data2_m[12]\, B => N_159, Y => - \rdatav_0_1_0_iv_0_0[12]\); - - \r.wb.addr_RNO_3[0]\ : AOI1B - port map(A => \paddress[0]\, B => \dstate_RNIP22L4[7]\, C - => \mmudco_m[76]\, Y => \addr_1_1_iv_0[0]\); - - \r.hit_RNIG1QI\ : NOR2A - port map(A => N_58, B => N_421, Y => un157_m_en); - - \r.xaddress_RNIJH2O2_5[0]\ : NOR2B - port map(A => dataout(9), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[233]\); - - \r.wb.addr_RNO_4[26]\ : OR2B - port map(A => \address[26]\, B => N_514, Y => \addr_m[26]\); - - \r.vaddr[14]\ : DFN1E1 - port map(D => maddress(14), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[14]\); - - \r.vaddr_RNIRLDE[4]\ : MX2 - port map(A => maddress(4), B => \vaddr[4]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[80]\); - - \r.xaddress_RNIU5E9O[1]\ : AOI1B - port map(A => \edata[5]\, B => ddatainv_0_0_sqmuxa, C => - \edata_m_0_i[13]\, Y => \ddatainv_0_1_0_iv_1[29]\); - - \r.holdn_RNO_17\ : NOR3B - port map(A => N_3604, B => holdn_3_sqmuxa_0_0_0, C => - e_0_0_RNI8APPC92, Y => holdn_3_sqmuxa_0_0_2); - - \r.dstate_RNI3CDFG[1]\ : MX2 - port map(A => maddress(31), B => edata2_iv_i_0(31), S => - edata_0_sqmuxa_i, Y => \edata[31]\); - - \r.wb.addr_RNO_3[29]\ : OR2B - port map(A => maddress(29), B => addr_2_sqmuxa, Y => N_261); - - \r.read_RNIR1CL\ : NOR2 - port map(A => N_3749, B => N_3748, Y => \N_425\); - - \dctrl.v.wb.addr_1_1_iv_0_a3_3[29]\ : NAND2 - port map(A => N_514, B => \address[29]\, Y => N_264); - - \r.dstate_RNIDDSEO[1]\ : AO1 - port map(A => \edata[6]\, B => \size_RNIBHS22[0]\, C => - \mcdo_m[6]\, Y => \ddatainv_0_1_1_iv_1[6]\); - - \dctrl.0.un1_dci_NE_0\ : XA1A - port map(A => maddress(24), B => dataout_0(20), C => - un1_dci_1_i, Y => un1_dci_NE_0); - - \r.wb.data2[30]\ : DFN1E1 - port map(D => \data2_1[30]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[30]\); - - \r.dstate_RNIP22L4[7]\ : AO1C - port map(A => burst_0_sqmuxa, B => \dstate[7]\, C => - data2_0_sqmuxa_1, Y => \dstate_RNIP22L4[7]\); - - \r.wb.data1_RNO_0[29]\ : MX2C - port map(A => edata2_iv_i_0(29), B => \data2[29]\, S => - N_3331, Y => N_2127); - - \r.req\ : DFN1 - port map(D => req_RNO, CLK => lclk_c, Q => \req\); - - \r.dstate_RNIGLBNC[1]\ : MX2 - port map(A => maddress(15), B => edata2_0_iv(15), S => - edata_0_sqmuxa_i_0, Y => \edata[15]\); - - \r.mmctrl1.e_0_0_RNI16GR\ : OA1A - port map(A => dstate_tr22_15_a2_14_1_0, B => N_459, C => - \e_0\, Y => dstate_tr22_15_a2_2_m8_i_a5_1_0); - - \r.icenable\ : DFN1 - port map(D => ilramen_1_sqmuxa, CLK => lclk_c, Q => enable); - - \r.holdn_RNO\ : OR3C - port map(A => holdn_0_sqmuxa_1, B => holdn_0_5, C => - holdn_10, Y => holdn_RNO_0); - - \r.mmctrl1.ctxp[17]\ : DFN1E1 - port map(D => maddress(19), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[17]\); - - \r.wb.addr_RNO_5[4]\ : OR2B - port map(A => \un1_m0_2[80]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[80]\); - - \r.dstate_RNO_1[1]\ : OR3A - port map(A => N_3546, B => N_72_i, C => read_0, Y => - N_3564_i); - - \r.wb.data1_RNO[11]\ : MX2A - port map(A => N_2109, B => maddress(11), S => - req_0_sqmuxa_1_0, Y => \data1_1[11]\); - - \r.wb.addr_RNO_5[23]\ : OR2B - port map(A => N_236_0, B => addr_1_sqmuxa_0, Y => N_218); - - \r.mmctrl1.ctx_RNILUJ8[3]\ : XNOR2 - port map(A => dataout(31), B => \ctx[3]\, Y => N_102_i_i); - - \r.mmctrl1.e_RNIJ62V\ : NOR2B - port map(A => \e\, B => N_3755, Y => N_3505_i); - - \r.wb.addr_RNO_6[28]\ : OR2B - port map(A => un1_m0_2_29, B => addr_1_sqmuxa_0, Y => N_213); - - \dctrl.0.un1_dci_NE_5\ : XA1A - port map(A => maddress(20), B => dataout_0(16), C => - un1_dci_10_i, Y => un1_dci_NE_5); - - \r.wb.data2_RNICBOB[29]\ : OR2B - port map(A => \data2[29]\, B => rdatav_012_0, Y => - \data2_m[29]\); - - \r.size_RNIPK6E[0]\ : OR3C - port map(A => \size[0]\, B => N_3749, C => \addr[1]\, Y => - N_3699); - - \r.dstate_RNIKSAI892[2]\ : OA1A - port map(A => N_3069_i, B => ilramen_1_sqmuxa, C => rst, Y - => \dstate_nss[6]\); - - \r.dstate_i_0_RNIV2M5JU1[8]\ : NOR3C - port map(A => N_3676, B => \dstate_ns_i_a4_i_9[0]\, C => - rst, Y => \dstate_nss_i_0[0]\); - - \r.dstate_0_RNIIC256_7[7]\ : OR2B - port map(A => dataout(2), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[226]\); - - \r.wb.addr_RNO_5[30]\ : OR2B - port map(A => \paddress[30]\, B => \dstate_RNIP22L4[7]\, Y - => \paddress_m[30]\); - - \r.dstate_0_RNI8J7VE[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[13]\, B => - \rdatav_0_1_0_iv_2[13]\, C => \mcdo_m_0[13]\, Y => - data_0_13); - - \r.holdn_RNO_11\ : NOR3C - port map(A => N_485, B => holdn_0_sqmuxa_1_m8_0_a2_3, C => - fault_pri, Y => holdn_0_sqmuxa_1_m8_0_a2_5); - - \r.read\ : DFN1 - port map(D => read_RNO, CLK => lclk_c, Q => read); - - \r.asi[2]\ : DFN1E1 - port map(D => asi(2), CLK => lclk_c, E => N_486_0, Q => - \asi_0[2]\); - - \r.valid_0_RNO_1[5]\ : OR2B - port map(A => \dstate_i_1[8]\, B => N_96, Y => - \valid_0_1_1_a4_1_0[5]\); - - \r.nomds_RNIPG271\ : NOR2A - port map(A => twrite_14_iv_0_o2_a1_0, B => un17_casaen_0_0, - Y => twrite_14_iv_0_o2_a1_1); - - \r.mmctrl1.e_RNIUU9O_0\ : OR2 - port map(A => \e\, B => N_526, Y => N_2994_6); - - \r.dstate_RNI7GJK9[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_0_7, Y => N_3313); - - \r.dstate_RNO_0[4]\ : AOI1B - port map(A => dstate_tr16_13_0_0_a2_0_5, B => un1_m0_2_108, - C => \dstate_ns_0_2[4]\, Y => \dstate_ns_0_3[4]\); - - \r.mmctrl1.ctxp_RNITPJ12[21]\ : OR2B - port map(A => \ctxp[21]\, B => N_3344_i_0, Y => - \ctxp_m[21]\); - - \r.dstate_RNIDR7M2[1]\ : NOR2B - port map(A => \edata[2]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[2]\); - - \r.stpend_RNI897S692\ : OR3A - port map(A => stpend, B => read_1, C => N_581_i, Y => - N_3514); - - \r.mmctrl1.ctx_0_0_RNI4VGHD[3]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_i_a2_2[3]\, B => - \rdatav_0_1_1_iv_i_a2_1[3]\, C => - \rdatav_0_1_1_iv_i_a2_4[3]\, Y => - \rdatav_0_1_1_iv_i_a2_5[3]\); - - \r.dstate_i_0_RNID0P84[8]\ : OR3A - port map(A => un18_m_en, B => \dstate_i_0[8]\, C => N_328, - Y => addr_0_sqmuxa_1); - - \r.dstate_RNIEVI95[2]\ : AOI1B - port map(A => \ico_m_0[145]\, B => cdwrite_0_sqmuxa_i_0_0, - C => \rdatav_0_1_1_iv_1[11]\, Y => - \rdatav_0_1_1_iv_2[11]\); - - \r.wb.addr_RNO_5[25]\ : MX2 - port map(A => \paddress_0[25]\, B => \addr[25]\, S => N_484, - Y => \paddress[25]\); - - \r.read_RNIMJHQT\ : OR3 - port map(A => \mcdo_m[13]\, B => \edata_m_1[5]\, C => - \ddatainv_0_1_1_iv_0[13]\, Y => read_RNIMJHQT); - - \r.wb.addr_RNO_2[21]\ : AOI1B - port map(A => N_419, B => addr_1_sqmuxa_0, C => N_3717, Y - => \addr_1_1_iv_0_0[21]\); - - \r.xaddress_RNIRHEVJ[5]\ : MX2 - port map(A => N_2232, B => eaddress_3, S => taddr_2_sqmuxa, - Y => \taddr_7[5]\); - - \r.wb.lock_RNI35I6\ : NOR2B - port map(A => \lock_0\, B => bo_d(2), Y => lock_m_0); - - \r.dstate_RNI67JMC[1]\ : MX2 - port map(A => maddress(14), B => edata2_0_iv(14), S => - edata_0_sqmuxa_i_0, Y => \edata[14]\); - - \un1_r.faddr_I_27\ : AND2 - port map(A => \faddr[3]\, B => \faddr[4]\, Y => - \DWACT_FINC_E[1]\); - - \r.mmctrl1.ctxp_RNIQLJ12[11]\ : OR2B - port map(A => \ctxp[11]\, B => N_3344_i_0_0, Y => - \ctxp_m[11]\); - - \r.dstate_RNII2LPC[5]\ : NOR2A - port map(A => data2_0_sqmuxa_1, B => N_562, Y => N_3815); - - \dctrl.0.un1_dci_NE_16\ : NOR3C - port map(A => un1_dci_NE_5, B => un1_dci_NE_4, C => - un1_dci_NE_13, Y => un1_dci_NE_16); - - \r.faddr[5]\ : DFN1E0 - port map(D => \faddr_1[5]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[5]\); - - \r.cctrl.dcs_RNIITHQ2A2[0]\ : OR3A - port map(A => N_467, B => N_576, C => N_581_i, Y => N_611); - - \r.wb.data1[12]\ : DFN1E0 - port map(D => \data1_1[12]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_0); - - \r.read_RNI0NEDD\ : OR2B - port map(A => \N_425\, B => N_264_0, Y => \mcdo_m_i[19]\); - - \r.dstate[0]\ : DFN1 - port map(D => \dstate_nss[8]\, CLK => lclk_c, Q => - \dstate[0]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_10\ : NOR2A - port map(A => eaddress_5, B => eaddress_20, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_10); - - \r.wb.data1[29]\ : DFN1E0 - port map(D => \data1_1[29]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_17); - - \r.wb.addr_RNO[9]\ : AO1B - port map(A => \address[9]\, B => N_514, C => - \addr_1_1_iv_2[9]\, Y => \addr_1[9]\); - - \r.stpend_RNIUDDF6\ : NOR2B - port map(A => stpend_0_sqmuxa, B => \dstate_RNI5GFM4[5]\, Y - => data1_0_sqmuxa_0); - - \r.xaddress_RNI0GI17S2[17]\ : OR3C - port map(A => N_3893, B => N_229, C => \dci_m[89]\, Y => - xaddress_RNI0GI17S2(17)); - - \r.read_RNO\ : NOR2B - port map(A => rst, B => N_2684, Y => read_RNO); - - \dctrl.un11_eholdn_2_0_a2_0_a4_0_a2\ : OR2 - port map(A => asi(3), B => asi(2), Y => N_2938_2); - - \r.dstate_RNO_2[0]\ : NOR3B - port map(A => \dstate_ns_0_0_a2_0_1[8]\, B => - un121_m_en_i_s_0, C => un1_m0_2_0_d0, Y => - \dstate_ns_0_0_a2_0_3[8]\); - - \r.dstate_i_2_RNISK8N1_4[8]\ : OR2B - port map(A => dataout(28), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[408]\); - - \r.dstate_i_2_RNIDLM8792[8]\ : OR2A - port map(A => N_3745, B => un1_dci_12, Y => N_3790); - - \r.paddress[4]\ : DFN1E1 - port map(D => un1_m0_2_5, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[4]\); - - \r.dstate_i_RNINU2473[8]\ : NOR2A - port map(A => \dstate_i[8]\, B => twrite_14, Y => - valid_0_2_sqmuxa); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e\ : NOR2A - port map(A => \vaddr_1_sqmuxa_0_a2_4_m1_e_24\, B => - eaddress_29, Y => un1_addout_13_i); - - \r.mmctrl1.ctx_RNIEH4T5[6]\ : NOR2A - port map(A => \ctx_m[6]\, B => \rdatav_0_1_6[3]\, Y => - \rdatav_0_1_1_iv_3[6]\); - - \r.cctrl.ifrz\ : DFN1E0 - port map(D => maddress(4), CLK => lclk_c, E => \N_523\, Q - => ifrz); - - \r.wb.addr_RNO_4[20]\ : OR2B - port map(A => N_3842, B => \dstate_RNIP22L4[7]\, Y => - N_3859); - - \r.dstate_2_RNI7PRT7[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_17, Y => - \mcdo_m_0[17]\); - - \r.xaddress[11]\ : DFN1 - port map(D => N_713, CLK => lclk_c, Q => \addr[11]\); - - \r.read_RNID0E6C\ : NOR2B - port map(A => \N_425_0\, B => hrdata_0_d0, Y => \mcdo_m[5]\); - - \r.vaddr_RNIEQHC[26]\ : MX2 - port map(A => maddress(26), B => \vaddr[26]\, S => - \dstate_i_1[8]\, Y => data(26)); - - \r.wb.addr_RNO_6[27]\ : MX2 - port map(A => \paddress[27]\, B => \addr[27]\, S => N_484_0, - Y => N_674); - - \r.dstate_RNO_8[4]\ : OR2 - port map(A => N_3041_11, B => dstate_ns_0_2065_0, Y => - \dstate_RNO_8[4]\); - - \r.wb.data1_RNO[29]\ : MX2A - port map(A => N_2127, B => maddress(29), S => - req_0_sqmuxa_1, Y => \data1_1[29]\); - - \r.dstate_RNIR0ANC[1]\ : MX2 - port map(A => maddress(21), B => edata2_0_iv(21), S => - edata_0_sqmuxa_i, Y => \edata[21]\); - - \r.dstate_i_2_RNISK8N1_3[8]\ : OR2B - port map(A => dataout(30), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[410]\); - - \r.dstate_RNIVHK83[1]\ : NOR2B - port map(A => \edata[2]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[2]\); - - \r.mmctrl1.ctxp_RNI1QJ12[25]\ : OR2B - port map(A => \ctxp[25]\, B => N_3344_i_0_0, Y => - \ctxp_m[25]\); - - \dctrl.rdatav_0_1_0_iv[29]\ : NAND2 - port map(A => \mcdo_m_0[29]\, B => \rdatav_0_1_0_iv_4[29]\, - Y => data_0_29); - - \r.xaddress_RNIFP43F[2]\ : MX2C - port map(A => N_2229, B => eaddress_0, S => taddr_2_sqmuxa, - Y => xaddress_RNIFP43F(2)); - - \r.flush_RNIMPMV8\ : NOR3A - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - maddress(10), Y => N_3297); - - \r.xaddress_RNI7O47A[1]\ : OR2B - port map(A => \edata[1]\, B => ddatainv_0_0_sqmuxa, Y => - \edata_m_4_i[1]\); - - \r.wb.addr_RNO_4[22]\ : OR2B - port map(A => N_3840, B => \dstate_RNIP22L4[7]\, Y => - N_3870); - - \r.valid_0_RNO_0[3]\ : OR2A - port map(A => \dstate_i_RNID1NU1[8]\, B => N_188, Y => - N_3380); - - \r.holdn_RNO_0\ : MX2C - port map(A => holdn_RNO_3, B => fault_pro, S => holdn_RNO_4, - Y => holdn_0_sqmuxa_1); - - \dctrl.0.un1_dci_2_0_RNII1KT\ : NOR3C - port map(A => un1_dci_NE_1, B => un1_dci_NE_0, C => - un1_dci_NE_11, Y => un1_dci_NE_15); - - \r.wb.size_RNO[1]\ : MX2 - port map(A => size_1_d0, B => \size_0[1]\, S => - \dstate_i[8]\, Y => N_654); - - \r.wb.data2[28]\ : DFN1E1 - port map(D => \data2_1[28]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[28]\); - - \dctrl.0.genmux.un6_validrawv_5\ : MX2 - port map(A => dataout_0(3), B => dataout_0(7), S => - maddress(4), Y => N_2016); - - \r.xaddress_RNI1CIE2[0]\ : OR2B - port map(A => \ddatainv_0_1_0_0[24]\, B => N_574, Y => - N_2088); - - \r.wb.addr_RNO_1[0]\ : OR2B - port map(A => un1_m0_2_1, B => addr_1_sqmuxa, Y => - \mmudco_m[2]\); - - \r.vaddr_RNI7MHC[21]\ : MX2 - port map(A => maddress(21), B => \vaddr[21]\, S => - \dstate_i_2[8]\, Y => data(21)); - - \r.dstate_0_RNI0KIER[2]\ : OR3C - port map(A => \rdatav_0_1_1_iv_5[16]\, B => - \rdatav_0_1_1_iv_4[16]\, C => \mcdo_m_0[16]\, Y => - data_0_16); - - \un1_r.faddr_I_31\ : XOR2 - port map(A => N_4, B => \faddr[6]\, Y => I_31_1); - - \r.wb.data2_RNI6BAS3[4]\ : NOR3C - port map(A => \dcramo_m[412]\, B => \data2_m[4]\, C => - rdatav_0_2_sqmuxa, Y => \rdatav_0_1_0_iv_1[4]\); - - \r.valid_0[1]\ : DFN1E0 - port map(D => \valid_0_1[1]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[1]\); - - \r.wb.addr_RNO_5[31]\ : OR2B - port map(A => N_317_0, B => addr_1_sqmuxa, Y => N_3716); - - \r.size_RNIRG4D[1]\ : OR2B - port map(A => \size_0[1]\, B => N_3749, Y => N_3766); - - \r.flush_RNI13HE4\ : OR2A - port map(A => taddr_2_sqmuxa, B => flush_0, Y => N_195); - - \r.dstate_i_RNI9P0G[8]\ : MX2C - port map(A => dataout_0(5), B => N_96, S => \dstate_i[8]\, - Y => N_110); - - \r.wb.data1[1]\ : DFN1E0 - port map(D => \data1_1[1]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data(1)); - - \r.dstate_i_RNI29QQ7J3[8]\ : OAI1 - port map(A => N_349, B => \vmask_0_5[6]\, C => N_298, Y => - dstate_i_RNI29QQ7J3(8)); - - \r.dstate_RNO_14[4]\ : OR2B - port map(A => un1_m0_2_0_d0, B => \dstate[4]\, Y => N_3181); - - \r.dstate_i_RNI85G9RS2[8]\ : AO1B - port map(A => \vmask_0_5[7]\, B => N_3315, C => - \dstate_i_RNII68N892_0[8]\, Y => N_3278); - - \r.wbinit\ : DFN1E1 - port map(D => N_485, CLK => lclk_c, E => - \mmudci_trans_op_1_sqmuxa_1\, Q => wbinit); - - \r.wb.addr_RNO_0[7]\ : NOR3C - port map(A => N_3735, B => N_3734, C => - \addr_1_1_iv_0_1[7]\, Y => \addr_1_1_iv_0_3[7]\); - - \r.dstate_0_RNI2DT77_2[2]\ : AOI1B - port map(A => diagdata_13, B => \dstate_0[2]\, C => - \dcramo_m_0[237]\, Y => \rdatav_0_1_0_iv_3[13]\); - - \r.wb.data1_RNO_0[28]\ : MX2C - port map(A => edata2_iv_i_0(28), B => \data2[28]\, S => - N_3331_0, Y => N_2126); - - \r.wb.addr_RNO_4[7]\ : AOI1B - port map(A => \un1_m0_2[83]\, B => addr_1_sqmuxa_2_0, C => - N_3737, Y => \addr_1_1_iv_0_0[7]\); - - \r.valid_0[6]\ : DFN1E0 - port map(D => \valid_0_1[6]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[6]\); - - \r.cctrl.dcs_RNO_2[1]\ : NOR2A - port map(A => dfrz, B => intack, Y => \dcs_0_i_0_a2_0[1]\); - - \r.xaddress_RNIC9N39[10]\ : NOR3B - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - \addr[10]\, Y => N_3298); - - \r.wb.data1_RNO_0[0]\ : MX2B - port map(A => edata2_0_iv(0), B => \data2[0]\, S => N_3331, - Y => N_2098); - - \r.read_RNIOVA59\ : OR2B - port map(A => \N_425\, B => hrdata_0_27, Y => - \mcdo_m_i[27]\); - - \r.wb.data2_RNO[13]\ : MX2 - port map(A => edata2_0_iv(13), B => hrdata_0_13, S => - \dstate_0[7]\, Y => \data2_1[13]\); - - \r.paddress[29]\ : DFN1E1 - port map(D => N_353, CLK => lclk_c, E => paddress_1_sqmuxa, - Q => \paddress[29]\); - - \r.wb.addr[25]\ : DFN1 - port map(D => \addr_1[25]\, CLK => lclk_c, Q => - \address[25]\); - - \un1_r.faddr_I_23\ : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \faddr[3]\, C => - \faddr[4]\, Y => N_9_0); - - \r.wb.addr_RNO[18]\ : AO1B - port map(A => un1_m0_2_93, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[18]\, Y => \addr_1[18]\); - - \r.dstate_i_RNI8VKHK92[8]\ : OR2A - port map(A => edata2_0_iv(13), B => \N_3254_0\, Y => - \dci_m[85]\); - - \r.mmctrl1.ctxp_RNISPJ12[20]\ : OR2B - port map(A => \ctxp[20]\, B => N_3344_i_0, Y => - \ctxp_m[20]\); - - \r.mmctrl1.ctxp[2]\ : DFN1E1 - port map(D => maddress(4), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[2]\); - - \r.dstate_i_RNIPU8DG92[8]\ : OR2 - port map(A => edata2_0_iv(0), B => - \dstate_i_RNII68N892_0[8]\, Y => N_303); - - \r.dstate_i_2_RNI41OO[8]\ : NOR3A - port map(A => enaddr, B => \dstate_i_2[8]\, C => N_496, Y - => N_3755); - - \r.mmctrl1.e_RNIG9094\ : OA1B - port map(A => N_666, B => N_2994_6, C => - \dstate_ns_0_7_tz_0[3]\, Y => \dstate_ns_0_8_tz[3]\); - - \r.dstate_RNO_9[4]\ : NOR2 - port map(A => read_0, B => N_3499, Y => - dstate_tr16_10_0_i_0); - - \r.wb.addr[15]\ : DFN1 - port map(D => \addr_1[15]\, CLK => lclk_c, Q => - \address[15]\); - - \r.req_RNO\ : AOI1B - port map(A => req_1_2, B => req_2_sqmuxa, C => rst, Y => - req_RNO); - - \r.flush_RNISQ07LK\ : OR3A - port map(A => N_3322, B => N_3248, C => flush_0, Y => N_349); - - \r.dstate_RNIMTANC[1]\ : MX2 - port map(A => maddress(18), B => edata2_0_iv(18), S => - edata_0_sqmuxa_i_0, Y => \edata[18]\); - - \r.cctrl.dcs_RNI2RG54[0]\ : OA1A - port map(A => un6_validrawv, B => size_1_d0, C => - setrepl_0_sqmuxa_1_m_i_5_0, Y => - setrepl_0_sqmuxa_1_m_i_5_2); - - \r.wb.addr_RNO_3[3]\ : OR2B - port map(A => un1_m0_2_4, B => addr_1_sqmuxa, Y => N_293_0); - - \r.wb.addr_RNO_1[30]\ : NOR3C - port map(A => \dci_m[38]\, B => \addr_1_1_iv_0[30]\, C => - \addr_m[30]\, Y => \addr_1_1_iv_2[30]\); - - \r.holdn_RNI8G6B\ : NOR2 - port map(A => read_1, B => N_3443_i, Y => N_3748); - - \r.vaddr[30]\ : DFN1E1 - port map(D => maddress(30), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[30]\); - - \r.faddr_RNI7879K[0]\ : MX2 - port map(A => \taddr_7[5]\, B => \faddr[0]\, S => - \un1_p0_2_0[498]\, Y => faddr_RNI7879K(0)); - - \r.dstate_RNIBGU46_0[2]\ : NOR2B - port map(A => dataout(3), B => rdatav_0_6_sqmuxa_3, Y => - N_3339); - - \r.dstate_i_2_RNISK8N1_8[8]\ : OR2B - port map(A => dataout_0(13), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[113]\); - - \r.wb.addr_RNO_2[2]\ : AO1C - port map(A => \address[2]\, B => N_323, C => dstate_19, Y - => N_315); - - \r.mmctrl1.ctx_0_0[1]\ : DFN1 - port map(D => \ctx_0_0_RNIQIPQ[1]\, CLK => lclk_c, Q => - \ctx_0[1]\); - - \r.dstate_RNIO9NNA[1]\ : NOR2B - port map(A => \edata[4]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[4]\); - - \r.dstate_ns_0_0_o2_0[1]\ : NOR2B - port map(A => N_3569_2, B => N_3586, Y => - \dstate_ns_0_0_o2_0[1]\); - - \r.xaddress_RNIJH2O2_11[0]\ : NOR2B - port map(A => dataout(3), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[227]\); - - \r.wb.addr_RNO_2[3]\ : OR2B - port map(A => \address[3]\, B => dstate_19, Y => N_295); - - \r.wb.data2_RNISU546[19]\ : NOR3B - port map(A => \mmudco_m[62]\, B => \rdatav_0_1_0_iv_0[19]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_2[19]\); - - \r.dstate_1_RNI223L7[7]\ : NOR3B - port map(A => \dstate_ns_i_a4_i_o2_9_0[0]\, B => - data2_0_sqmuxa_1, C => N_3811, Y => - \dstate_ns_i_a4_i_o2_9_2[0]\); - - \r.dstate_i_RNII68N892[8]\ : OR2A - port map(A => tdiagwrite_1_0_0_o2_1, B => \N_121\, Y => - \N_3254_0\); - - \r.xaddress_RNIID927S2[16]\ : OR3C - port map(A => N_242, B => N_240, C => \dci_m[88]\, Y => - xaddress_RNIID927S2(16)); - - \r.mmctrl1.ctxp_RNIOOCKD[2]\ : AND2 - port map(A => \ctxp_m[2]\, B => \rdatav_0_1_0_iv_5[4]\, Y - => \rdatav_0_1_0_iv_6[4]\); - - \r.cctrl.dcs[0]\ : DFN1 - port map(D => \dcs_RNO[0]\, CLK => lclk_c, Q => \dcs[0]\); - - \r.wb.addr_RNO_4[21]\ : OR2B - port map(A => \dstate_RNIP22L4[7]\, B => N_552, Y => N_3717); - - \r.wb.data1_RNO_0[15]\ : MX2C - port map(A => edata2_0_iv(15), B => \data2[15]\, S => - N_3331, Y => N_2113); - - \r.cctrl.dcs_RNIBN6EB[0]\ : AO1 - port map(A => \dstate_ns_i_a4_i_o2_9_2[0]\, B => - mexc_0_sqmuxa_1, C => \dcs[0]\, Y => \dcs_RNIBN6EB[0]\); - - \r.read_RNIFPGIE\ : OR2B - port map(A => \N_425_0\, B => hrdata_23, Y => - \mcdo_m_i[28]\); - - \r.dstate_RNO_6[5]\ : OR3A - port map(A => \dstate_ns_0_2_0_tz[3]\, B => N_3511, C => - ready, Y => \dstate_ns_0_2_0[3]\); - - \r.dstate_RNI4UNNA[1]\ : NOR2B - port map(A => \edata[5]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[5]\); - - \r.stpend_RNIGCK85\ : NOR2B - port map(A => N_485, B => N_102, Y => burst_0_sqmuxa_2); - - \r.xaddress_RNIQF6M2_10[0]\ : OR2B - port map(A => dataout(16), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[240]\); - - \r.wb.data2[16]\ : DFN1E1 - port map(D => \data2_1[16]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[16]\); - - \r.ready\ : DFN1E1 - port map(D => ready_0_sqmuxa_0, CLK => lclk_c, E => - ready_0_sqmuxa, Q => ready_0); - - \r.mmctrl1.e_RNIC0632\ : OR2B - port map(A => \e\, B => miscdata_0_sqmuxa, Y => e_m); - - \r.holdn_RNO_29\ : NOR2 - port map(A => \dstate_i_0[8]\, B => lock, Y => - holdn_0_sqmuxa_1_m8_0_a2_0); - - \r.flush_0_1_RNI7GU5992\ : OR2B - port map(A => maddress(13), B => \N_329\, Y => N_3849); - - \r.dstate_RNIN7LKB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[1]\, Y => \ddatainv_0_1_0_iv_1[17]\); - - \r.dstate_RNIMK5S4[7]\ : AO1A - port map(A => burst_0_sqmuxa, B => \dstate[7]\, C => - ready_0_sqmuxa_0, Y => N_572); - - \r.xaddress_RNI5PMB[4]\ : MX2 - port map(A => maddress(4), B => \addr[4]\, S => N_3443_i, Y - => N_679); - - \r.wb.data2_RNI9BOB[26]\ : OR2B - port map(A => \data2[26]\, B => rdatav_012, Y => - \data2_m[26]\); - - \r.wb.addr_RNO_4[19]\ : MX2 - port map(A => \paddress[19]\, B => \addr[19]\, S => N_484, - Y => N_3837); - - \un1_v.cctrlwr19_2_0_a2_0\ : NOR3C - port map(A => N_561, B => read_0, C => cctrlwr13, Y => - N_3607); - - \r.flush_RNILUNG\ : NOR3A - port map(A => size_1_d0, B => size_0_0, C => flush_0, Y => - N_132); - - \r.stpend_RNIRDAC2\ : NOR2 - port map(A => ready_0_sqmuxa_0_a2_0_a2_0, B => N_72_i, Y - => ready_0_sqmuxa_0); - - \r.dstate_RNIHILB6_7[7]\ : OR2B - port map(A => dataout(17), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[241]\); - - \v.burst_2_sqmuxa_m8_0_a4_0_RNIQKINJ92\ : OR3 - port map(A => burst_2_sqmuxa_m8_0_a4_0, B => - burst_2_sqmuxa_m8_0_0, C => N_485, Y => burst_1_sqmuxa); - - \dctrl.v.burst_16_m_RNIO1SFQ92\ : AO1C - port map(A => un1_dci_12, B => burst_3_m_3, C => - burst_1_iv_2_1, Y => burst_1_iv_2); - - \r.dstate_RNI1JGE7[2]\ : AOI1B - port map(A => diagdata_29, B => \dstate[2]\, C => - \dcramo_m_0[253]\, Y => \rdatav_0_1_0_iv_3[29]\); - - \r.dstate_2_RNIPUOKL[7]\ : OR2B - port map(A => \rdatav_0_1_0_iv_4[30]\, B => \mcdo_m_0[30]\, - Y => data_0_30); - - \r.dstate_0_RNI5PIRE[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[26]\, B => - \rdatav_0_1_0_iv_2[26]\, C => \mcdo_m_0[26]\, Y => - data_0_26); - - \r.xaddress_RNI10V9992[17]\ : OR2B - port map(A => \addr[17]\, B => \N_330\, Y => N_229); - - \r.wb.addr_RNO_3[8]\ : OR2B - port map(A => maddress(8), B => addr_2_sqmuxa, Y => - \dci_m[16]\); - - \r.hit_RNO_3\ : NOR3B - port map(A => hit_1_iv_0_a2_0_0, B => un10_m_en, C => - \dstate_i_0[8]\, Y => hit_1_iv_0_a2_0_2); - - \r.dstate_i_RNINECF892[8]\ : OR3 - port map(A => un19_eholdn, B => - \mmudci_fsread_1_sqmuxa_0_a2_0\, C => \N_121\, Y => - fsread_i_0); - - \r.cache_RNO_7\ : NOR2A - port map(A => N_102, B => \dstate_i_2[8]\, Y => N_3836); - - \r.dstate_i_RNIGAV0O92[8]\ : OR2A - port map(A => edata2_iv_i_0(28), B => \N_3254_0\, Y => - N_144); - - \r.wb.addr_RNO_1[28]\ : NOR3C - port map(A => N_3888, B => \addr_1_1_iv_0_0[28]\, C => - N_214, Y => \addr_1_1_iv_0_2[28]\); - - \r.wb.addr_RNO_0[9]\ : NOR3C - port map(A => \mmudco_m[11]\, B => \addr_1_1_iv_0[9]\, C - => \dci_m[17]\, Y => \addr_1_1_iv_2[9]\); - - \r.mmctrl1.nf_RNO\ : NOR2B - port map(A => rst, B => N_2675, Y => nf_RNO); - - \r.dstate_0_RNIIC256_6[7]\ : OR2B - port map(A => dataout(8), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[232]\); - - \r.wb.addr_RNO_5[1]\ : OR2B - port map(A => \un1_m0_2[77]\, B => addr_1_sqmuxa_2, Y => - \mmudco_m[77]\); - - \r.vaddr_RNI6AHC[22]\ : MX2 - port map(A => maddress(22), B => \vaddr[22]\, S => - \dstate_i_1[8]\, Y => data(22)); - - \r.paddress[18]\ : DFN1E1 - port map(D => un1_m0_2_19, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[18]\); - - \r.mmctrl1.ctx_RNISO622[6]\ : OR2B - port map(A => \ctx[6]\, B => miscdata_2_sqmuxa, Y => - \ctx_m[6]\); - - \r.dstate_RNIF6E91_0[2]\ : OR2B - port map(A => diagdata_5, B => \dstate[2]\, Y => N_3397); - - \r.xaddress_RNIP2BVK1[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[30]\, B => - \mcdo_m_i[30]\, C => \ddatainv_0_1_0_iv_1[30]\, Y => - xaddress_RNIP2BVK1(1)); - - \r.xaddress_RNIQF6M2[0]\ : OR2B - port map(A => dataout_0(30), B => N_2088, Y => - \dcramo_m_i[254]\); - - \r.wb.data2_RNI1VRU1[8]\ : AOI1B - port map(A => \data2[8]\, B => rdatav_012_0, C => - \dcramo_m_0[105]\, Y => \rdatav_0_1_0_iv_0[8]\); - - \r.read_RNI8DFM31\ : OR3 - port map(A => \mcdo_m[8]\, B => \edata_m_1[0]\, C => - \ddatainv_0_1_1_iv_0[8]\, Y => read_RNI8DFM31); - - \r.dstate_RNIVK67A[1]\ : NOR2B - port map(A => \edata[4]\, B => ddatainv_0_3_sqmuxa, Y => - \edata_m[4]\); - - \r.dstate_0_RNI7FKF5[7]\ : AOI1B - port map(A => \dstate_0[7]\, B => N_585, C => N_3707, Y => - \dstate_ns_0_0_0[1]\); - - \r.faddr_RNIRHE8[4]\ : NOR2A - port map(A => flush_0, B => \faddr[4]\, Y => N_3291); - - \r.wb.data1[13]\ : DFN1E0 - port map(D => \data1_1[13]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_1); - - \r.dstate_RNIF6E91_2[2]\ : OR2B - port map(A => diagdata_6, B => \dstate[2]\, Y => - \ico_m[140]\); - - \r.dstate_i_2_RNIRQM12[8]\ : OR2B - port map(A => un1_m0_2_65, B => miscdata_4_sqmuxa, Y => - \mmudco_m[66]\); - - \r.dstate_i_0_RNI3GDM[8]\ : MX2C - port map(A => dataout_0(4), B => \vmask_0_5_1_a4_0_0[4]\, S - => \dstate_i_0[8]\, Y => \vmask_0_5_1_0[4]\); - - \r.mexc\ : DFN1E1 - port map(D => mexc, CLK => lclk_c, E => mexc_0_sqmuxa, Q - => mexc_0); - - \r.xaddress_RNIUC9VJ[0]\ : AND2 - port map(A => \edata_m_i[27]\, B => \dcramo_m_i[251]\, Y - => \ddatainv_0_1_0_iv_0[27]\); - - \r.dstate_i_2_RNIPLVA892[8]\ : OR2B - port map(A => dstate_tr22_15_a2_3_1_0, B => N_3583, Y => - dstate_tr22_15_a2_4_1); - - \r.wb.addr_RNO_6[25]\ : OR2B - port map(A => N_190_0, B => addr_1_sqmuxa, Y => - \mmudco_m[27]\); - - \r.wb.addr_RNO_1[19]\ : OR2B - port map(A => maddress(19), B => addr_2_sqmuxa, Y => N_221); - - \r.dstate_RNO_11[5]\ : OR2 - port map(A => N_2995_8, B => N_2994_8, Y => - \dstate_ns_0_4_tz[3]\); - - \r.dstate_RNIETKM8[1]\ : MX2B - port map(A => maddress_0_0, B => edata2_0_iv(1), S => - edata_0_sqmuxa_i_0, Y => \edata[1]\); - - \r.mmctrl1.ctxp_RNI0MJ12[17]\ : OR2B - port map(A => \ctxp[17]\, B => N_3344_i_0, Y => - \ctxp_m[17]\); - - \r.stpend_RNIFU09L92\ : NOR3C - port map(A => vaddr_1_sqmuxa_0_a2_4_m7_i_a4, B => - vaddr_1_sqmuxa_0_a2_5, C => r_N_6, Y => - \vaddr_1_sqmuxa_0_a2_2\); - - \r.dstate_i_0_RNIE3RBE91_0[8]\ : OR3B - port map(A => N_3835, B => dataout_0(0), C => - \dstate_i_0[8]\, Y => N_302); - - \r.dstate_0_RNI2DT77_0[2]\ : AOI1B - port map(A => diagdata_24, B => \dstate_0[2]\, C => - \dcramo_m_0[248]\, Y => \rdatav_0_1_0_iv_4[24]\); - - \r.xaddress_RNI0D8CG[4]\ : MX2 - port map(A => N_3261, B => eaddress_2, S => taddr_2_sqmuxa, - Y => N_10); - - \r.read_RNITTMR8\ : OR2B - port map(A => \N_425_0\, B => hrdata_25, Y => - \mcdo_m_i[30]\); - - \r.dstate_RNIK6EKA[3]\ : OR3C - port map(A => N_3750, B => N_3760, C => holdn_2_sqmuxa, Y - => N_562); - - \r.dstate_i_0_RNIRJRKFJ[8]\ : NOR2B - port map(A => N_128_1, B => N_3248, Y => - \vmask_0_1_2_a4_0_0[4]\); - - \dctrl.v.wb.addr_1_1_iv_0_RNO_4[10]\ : OR2B - port map(A => maddress(10), B => addr_2_sqmuxa_0, Y => - N_3642); - - \r.ready_RNIR2KA\ : OR2 - port map(A => stpend, B => ready_0, Y => N_508); - - \r.dstate_RNI0S6QJ[1]\ : AOI1B - port map(A => \edata[29]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[253]\, Y => \ddatainv_0_1_0_iv_0[29]\); - - \r.valid_0_RNO[5]\ : AO1B - port map(A => dataout_0(5), B => N_88, C => - \valid_0_1_1_0[5]\, Y => \valid_0_1[5]\); - - \r.paddress[9]\ : DFN1E1 - port map(D => un1_m0_2_10, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress_0[9]\); - - \r.mmctrl1.ctx_0_0_RNI849L[7]\ : MX2 - port map(A => \ctx_0[7]\, B => maddress(7), S => - ctx_1_sqmuxa, Y => N_2670); - - \r.dstate_tr8_9_10_i_o2_i_a2_i_o2_0\ : OR2B - port map(A => asi(4), B => asi(0), Y => N_537); - - \r.hit_RNICORB1\ : OA1A - port map(A => N_3845, B => hit, C => twrite_11_m_0_a2_0_0, - Y => twrite_11_m_0_a2_0_1); - - \r.burst\ : DFN1 - port map(D => burst_RNO, CLK => lclk_c, Q => \burst\); - - \r.mmctrl1.ctxp[10]\ : DFN1E1 - port map(D => maddress(12), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[10]\); - - \r.size_RNIBHS22[0]\ : OR3B - port map(A => N_3700, B => N_3699, C => ddatainv_0_6_sqmuxa, - Y => \size_RNIBHS22[0]\); - - \dctrl.vmaskraw_1_i_o2_i_a3_0_a2_0[3]\ : NAND2 - port map(A => N_559, B => - \vmaskraw_1_i_o2_i_a3_0_a2_0_0[3]\, Y => N_3661); - - \v.mmctrl1.e_0_sqmuxa\ : AND2 - port map(A => e_0_sqmuxa_2, B => e_0_sqmuxa_0, Y => - e_0_sqmuxa); - - \r.wb.addr_RNO_1[31]\ : AND2 - port map(A => N_3652, B => \addr_1_1_iv_0_0[31]\, Y => - \addr_1_1_iv_0_1[31]\); - - \r.dstate_RNI4TIJ[4]\ : NOR2B - port map(A => \dstate[4]\, B => N_58, Y => - twrite_14_iv_0_o4_0_o2_0); - - \r.xaddress_RNIQF6M2_8[0]\ : OR2B - port map(A => dataout(19), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[243]\); - - \r.valid_0[7]\ : DFN1E0 - port map(D => \valid_0_1[7]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[7]\); - - \r.nomds_RNIH54T\ : NOR2B - port map(A => un1_dci_12_0, B => N_3745, Y => - twrite_14_iv_0_o2_a1_0); - - \r.dstate_RNI0GC5A[1]\ : NOR2B - port map(A => \edata[7]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[7]\); - - \r.wb.addr_RNO_1[7]\ : OR2B - port map(A => \addr[7]\, B => N_3796, Y => N_3735); - - \r.nomds_RNIRCHA_0\ : OR2A - port map(A => nomds, B => hold_0, Y => N_3588); - - \r.wb.lock_RNO_3\ : OR3B - port map(A => lock, B => N_566, C => dstate_14, Y => N_3554); - - \r.xaddress[21]\ : DFN1E1 - port map(D => maddress(21), CLK => lclk_c, E => N_486, Q - => \addr[21]\); - - \r.wb.addr_RNO_2[7]\ : OR2B - port map(A => \paddress[7]\, B => N_3792, Y => N_3734); - - \r.vaddr_RNIAMHC[16]\ : MX2 - port map(A => maddress(16), B => \vaddr[16]\, S => - \dstate_i_1[8]\, Y => data(16)); - - \r.mmctrl1.ctxp[27]\ : DFN1E1 - port map(D => maddress(29), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[27]\); - - \r.dstate_RNIV0IM2[5]\ : NOR2A - port map(A => N_566, B => dstate_14, Y => req_0_sqmuxa_1_0); - - \r.wb.data2[2]\ : DFN1E1 - port map(D => \data2_1[2]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[2]\); - - \r.holdn_RNO_15\ : OR3B - port map(A => N_485, B => holdns_iv_0_a2_1_0, C => - \dstate_i_2_RNITVLGB92[8]\, Y => N_3615); - - \r.dstate_RNID7OK8[1]\ : MX2B - port map(A => maddress(0), B => edata2_0_iv(0), S => - edata_0_sqmuxa_i, Y => \edata[0]\); - - \r.mmctrl1.ctx_RNIABMN[2]\ : MX2 - port map(A => \ctx[2]\, B => maddress(2), S => ctx_1_sqmuxa, - Y => N_2665); - - \r.xaddress_RNIU3V9992[21]\ : OR2B - port map(A => \addr[21]\, B => \N_330\, Y => N_232); - - miscdata_4_sqmuxa_0_a2_1 : NOR2A - port map(A => \miscdata_4_sqmuxa_0_a2_0\, B => maddress(8), - Y => \miscdata_4_sqmuxa_0_a2_1\); - - \dctrl.v.cctrlwr13_0_a2\ : NOR2 - port map(A => cctrlwr13_0_a2_0, B => N_223, Y => cctrlwr13); - - \r.dstate_0_RNI0DV1J[2]\ : NOR3C - port map(A => \ctxp_m[0]\, B => \rdatav_0_1_0_iv_4[2]\, C - => \rdatav_0_1_0_iv_6[2]\, Y => rdatav_0_1_0_iv_7_2); - - \r.dstate_RNIQHHHH[1]\ : AO1 - port map(A => \edata[13]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[237]\, Y => \ddatainv_0_1_1_iv_0[13]\); - - \r.wb.addr_RNO_2[19]\ : AOI1B - port map(A => N_3837, B => N_2165_0, C => N_3890, Y => - \addr_1_1_iv_0_0[19]\); - - \r.wb.addr_RNO_0[29]\ : AOI1B - port map(A => data_1_3_i_a3_6_4, B => LVL_RNIT69H911(0), C - => addr_1_sqmuxa_2_0, Y => \addr_1_1_iv_0_a3_2_0[29]\); - - \r.xaddress[16]\ : DFN1E1 - port map(D => maddress(16), CLK => lclk_c, E => N_486, Q - => \addr[16]\); - - \r.wb.data2_RNIPOUT5[28]\ : AOI1B - port map(A => dataout_0(24), B => rdatasel_1_sqmuxa_1_0, C - => \rdatav_0_1_1_iv_1[28]\, Y => \rdatav_0_1_1_iv_2[28]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_22\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_19, B => - eaddress_22, C => eaddress_21, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_22); - - \r.wb.data1_RNO_1[3]\ : NOR2A - port map(A => req_0_sqmuxa_1, B => maddress_0_2, Y => - N_3362); - - \r.wb.data2_RNO[25]\ : MX2 - port map(A => edata2_iv_i_0(25), B => N_78_0, S => - \dstate_1[7]\, Y => \data2_1[25]\); - - \r.wb.addr_RNO_3[14]\ : OR2B - port map(A => \address[14]\, B => N_514, Y => N_3728); - - \r.mmctrl1.e_RNI9F783_0\ : NOR2A - port map(A => un47_m_en, B => N_3331, Y => addr_2_sqmuxa); - - \r.dstate_RNIF6E91_1[2]\ : OR2B - port map(A => diagdata_3, B => \dstate[2]\, Y => N_3404); - - \r.wb.addr_RNO_1[27]\ : NOR3C - port map(A => N_250, B => \addr_1_1_iv_0_0[27]\, C => N_253, - Y => \addr_1_1_iv_0_2[27]\); - - \r.size_RNI58Q41[1]\ : OA1B - port map(A => N_3757, B => maddress_0_0, C => N_3805, Y => - N_575); - - \r.dstate_RNIM2E08[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_0_9, Y => mcdo_m_0_8); - - \r.xaddress_RNIVN7I_0[0]\ : OR3B - port map(A => N_3764, B => \addr[0]\, C => \addr[1]\, Y => - N_3623); - - \r.dstate_RNIHILB6_1[7]\ : OR2B - port map(A => dataout(26), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[250]\); - - \r.dstate_RNIFMKG5[7]\ : NOR2B - port map(A => \dstate_RNIP22L4[7]\, B => N_484_0, Y => - N_3796); - - \r.wb.data2[21]\ : DFN1E1 - port map(D => \data2_1[21]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[21]\); - - \r.wb.addr_RNO[7]\ : AO1B - port map(A => maddress(7), B => N_2164, C => - \addr_1_1_iv_0_3[7]\, Y => \addr_1[7]\); - - \r.dstate_i_RNI0F9DG92[8]\ : OR2A - port map(A => edata2_0_iv(1), B => \N_3254_0\, Y => N_126); - - \r.cctrl.ics_RNIEBF34[0]\ : AOI1B - port map(A => un1_m0_2_35, B => miscdata_3_sqmuxa, C => - \ics_m[0]\, Y => \rdatav_0_1_0_iv_2[0]\); - - \r.wb.data2_RNIG3792[17]\ : AOI1B - port map(A => \data2[17]\, B => rdatav_012_0, C => - rdatav_0_1_sqmuxa, Y => \rdatav_0_1_1_iv_0[17]\); - - \r.dstate_RNIH89NC[1]\ : MX2 - port map(A => maddress(20), B => edata2_0_iv(20), S => - edata_0_sqmuxa_i_0, Y => \edata[20]\); - - \r.wb.data2_RNO[19]\ : MX2 - port map(A => edata2_0_iv(19), B => N_264_0, S => - \dstate[7]\, Y => \data2_1[19]\); - - \r.wb.addr[3]\ : DFN1 - port map(D => \addr_1[3]\, CLK => lclk_c, Q => \address[3]\); - - \r.dstate_i_2_RNIA2SML3_0[8]\ : OR2A - port map(A => vaddr_1_sqmuxa_0_0, B => - \mmudci_trans_op_1_sqmuxa_1\, Y => vaddr_1_sqmuxa); - - \r.xaddress_RNO[7]\ : MX2 - port map(A => \addr[7]\, B => maddress(7), S => N_486_0, Y - => N_712); - - \r.wbinit_RNIMANB3\ : OA1A - port map(A => \dstate_ns_i_a4_i_a2_15_0[0]\, B => - un1_m0_2_0_d0, C => dstate_0_sqmuxa, Y => - \dstate_ns_i_a4_i_o2_9_0[0]\); - - \r.dstate_RNI33OR2[1]\ : OR3B - port map(A => N_58, B => \dstate[1]\, C => flush_i, Y => - dwrite_4_sqmuxa); - - \r.vaddr[27]\ : DFN1E1 - port map(D => maddress(27), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[27]\); - - \r.wb.data1_RNO_0[21]\ : MX2C - port map(A => edata2_0_iv(21), B => \data2[21]\, S => - N_3331, Y => N_2119); - - \r.vaddr[13]\ : DFN1E1 - port map(D => maddress(13), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[13]\); - - \r.dstate_RNIAQNB0A2_0[7]\ : NOR2A - port map(A => twrite_11_m, B => N_55, Y => dwrite_1_iv_0); - - \r.dstate_i_2_RNIGB1N1[8]\ : OR3A - port map(A => N_665, B => N_3758, C => asi(3), Y => N_3677); - - \r.nomds_RNI4C96\ : NOR2A - port map(A => nomds, B => \dstate_i[8]\, Y => rdatav_012); - - \r.dstate_i_RNIQ5EIK92[8]\ : OR2A - port map(A => edata2_0_iv(15), B => - \dstate_i_RNII68N892_0[8]\, Y => \dci_m[87]\); - - \r.dstate[3]\ : DFN1 - port map(D => \dstate_nss[5]\, CLK => lclk_c, Q => - \dstate[3]\); - - \r.read_RNI9KP09\ : OR3C - port map(A => N_179, B => N_178, C => mexc_0_sqmuxa_1, Y - => dco_i_2(132)); - - \r.mmctrl1.e_RNIAF78I\ : NOR3C - port map(A => e_m, B => \rdatav_0_1_0_iv_4[0]\, C => - \dcramo_m_0[224]\, Y => \rdatav_0_1_0_iv_6[0]\); - - \r.wb.addr_RNO_6[30]\ : MX2 - port map(A => \paddress_0[30]\, B => \addr[30]\, S => N_484, - Y => \paddress[30]\); - - \r.dstate_RNIUR652_0[5]\ : OR2A - port map(A => \dstate[5]\, B => N_566, Y => data2_1_sqmuxa); - - \r.mmctrl1.ctxp_RNI6LB66[25]\ : NOR3C - port map(A => \mmudco_m[70]\, B => \rdatav_0_1_0_iv_0[27]\, - C => \ctxp_m[25]\, Y => \rdatav_0_1_0_iv_2[27]\); - - \r.dstate_RNO_10[1]\ : NOR2A - port map(A => dstate_tr22_15_0_a2_0, B => N_666, Y => - dstate_tr22_15_0_a2_1); - - \r.dstate_i_2_RNIV16D1[8]\ : NOR2 - port map(A => N_666, B => N_526, Y => - dstate_tr22_15_a2_3_1_0); - - \r.dstate_i_2_RNI3KVJ1_3[8]\ : NOR2A - port map(A => N_3253_i, B => N_526, Y => - rdatasel_1_sqmuxa_1); - - \r.wb.read\ : DFN1E0 - port map(D => N_419_0, CLK => lclk_c, E => - \dstate_RNI5GFM4[5]\, Q => \read_2\); - - \r.read_RNIQMJI41\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[17]\, B => - \mcdo_m_i[17]\, C => \ddatainv_0_1_0_iv_1[17]\, Y => - read_RNIQMJI41); - - \dctrl.un1_eholdn_2_i_i_o2_0\ : NOR2 - port map(A => cctrlwr13, B => N_494, Y => N_509); - - \r.ready_RNO_4\ : OR3A - port map(A => N_527, B => N_3758, C => N_3778, Y => - ready_0_sqmuxa_0_a2_1); - - \r.flush_RNIGBB873\ : OR2 - port map(A => flush_0, B => twrite_14, Y => flush_RNIGBB873); - - \r.wb.data2_RNIQQ546[18]\ : NOR3B - port map(A => \mmudco_m[61]\, B => \rdatav_0_1_0_iv_0[18]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_2[18]\); - - \r.mmctrl1.pso_RNIJ3VF\ : MX2 - port map(A => pso, B => \ctx[7]\, S => maddress(9), Y => - N_3259); - - \r.dstate_i_RNIRRRPEJ[8]\ : OR3A - port map(A => mexc, B => N_3248, C => \vmask_0_5[7]\, Y => - N_3282); - - \dctrl.un1_eholdn_2_1_0_a2_1_0_o2_i_a2\ : OR2 - port map(A => asi(4), B => N_505, Y => N_3799); - - \dctrl.0.genmux.un6_validrawv_1\ : MX2 - port map(A => dataout_0(0), B => dataout_0(4), S => - maddress(4), Y => N_2012); - - \r.wb.data1_RNO[15]\ : MX2A - port map(A => N_2113, B => maddress(15), S => - req_0_sqmuxa_1, Y => \data1_1[15]\); - - \r.wb.data1[15]\ : DFN1E0 - port map(D => \data1_1[15]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_3); - - \r.xaddress_RNO_2[2]\ : MX2C - port map(A => maddress(2), B => \addr[2]\, S => N_591, Y - => N_670); - - \r.flush_0_1_RNIDKU5992\ : NOR2B - port map(A => maddress(26), B => \N_329\, Y => N_245); - - \r.mmctrl1.ctxp_RNI1MJ12[18]\ : OR2B - port map(A => \ctxp[18]\, B => N_3344_i_0, Y => - \ctxp_m[18]\); - - \r.dstate_RNO_5[5]\ : OR2B - port map(A => N_3002_9, B => N_29, Y => N_3028); - - \r.stpend_RNO\ : OA1 - port map(A => dstate_5_sqmuxa, B => stpend_1_0, C => rst, Y - => stpend_RNO); - - \r.xaddress_RNIS6BN1[3]\ : AO1C - port map(A => \addr[3]\, B => N_3793, C => N_3662, Y => - N_3421); - - \r.wb.data1_RNO_0[22]\ : MX2C - port map(A => edata2_0_iv(22), B => \data2[22]\, S => - N_3331_0, Y => N_2120); - - \r.wb.data1[2]\ : DFN1E0 - port map(D => \data1_1[2]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(2)); - - \r.flush_RNI13HE4_0\ : NOR2 - port map(A => flush_0, B => taddr_2_sqmuxa, Y => N_3319); - - \r.faddr[3]\ : DFN1E0 - port map(D => \faddr_1[3]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[3]\); - - \r.dstate_i_2_RNISK8N1_26[8]\ : OR2B - port map(A => dataout_0(10), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[110]\); - - \r.dstate_RNO_2[1]\ : OAI1 - port map(A => dstate_tr22_15_a2_4_1, B => un1_m0_2_108, C - => e_0_0_RNIIAUC4Q1, Y => N_3545); - - \r.paddress[10]\ : DFN1E1 - port map(D => un1_m0_2_11, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[10]\); - - \r.mmctrl1.e_RNI0TEJ1\ : NOR3B - port map(A => N_3755, B => e_RNIKN3D, C => - dstate_tr8_1_8_0_a2_0, Y => N_2995_8); - - \dctrl.twrite_14_iv_0_a2_a0_RNO\ : AND2 - port map(A => twrite_14_iv_0_a2_a0_3, B => un1_addout_12, Y - => twrite_14_iv_0_a2_a0_4); - - \v.wb.addr_0_sqmuxa_2_RNI7GIK2\ : AND2 - port map(A => burst_1_sqmuxa_0, B => addr_0_sqmuxa_2, Y => - burst_1_sqmuxa_1); - - \r.wb.data2_RNIT3M64[28]\ : NOR3C - port map(A => rdatav_0_1_sqmuxa, B => \data2_m[28]\, C => - rdatav_0_2_sqmuxa, Y => \rdatav_0_1_1_iv_1[28]\); - - \r.cctrl.ics_RNO_0[1]\ : NOR2A - port map(A => \N_523\, B => \ics[1]\, Y => N_3203); - - \r.xaddress_RNI30V9992[19]\ : OR2B - port map(A => \addr[19]\, B => \N_330\, Y => N_3875); - - \r.dstate_0_RNI7RSMI[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_0_14, Y => - \mcdo_m_0[14]\); - - \r.xaddress_RNO_1[2]\ : OR3 - port map(A => N_503, B => N_507, C => - \dstate_i_2_RNITVLGB92[8]\, Y => N_3698); - - \r.mmctrl1.ctxp_RNID8SKD[27]\ : NOR3C - port map(A => \ctxp_m[27]\, B => \rdatav_0_1_0_iv_1[29]\, C - => \rdatav_0_1_0_iv_3[29]\, Y => \rdatav_0_1_0_iv_4[29]\); - - \r.dstate_RNO_11[1]\ : AO1 - port map(A => N_3586, B => N_595, C => N_526, Y => - dstate_tr22_15_m8_i_a5_0_0); - - \r.dstate_i_RNIVPST692[8]\ : OR2 - port map(A => \dstate_i[8]\, B => un1_dci_12, Y => \N_121\); - - \r.wb.data2_RNIV27LB[6]\ : NOR3C - port map(A => \rdatav_0_1_1_iv_1[6]\, B => \mmudco_m[42]\, - C => \rdatav_0_1_1_iv_3[6]\, Y => \rdatav_0_1_1_iv_4[6]\); - - \r.nomds_RNIBK9H\ : OR2 - port map(A => enaddr, B => N_522, Y => - \dstate_ns_i_a4_i_a2_6_0[0]\); - - \r.cache_RNO_5\ : OAI1 - port map(A => N_527, B => dstate_25_0_a2_0, C => N_587, Y - => dstate_25); - - \dctrl.vmaskraw_1_i_o2_i_a2_0_RNIBEQD1_0[1]\ : AO1 - port map(A => N_3654, B => N_3653, C => N_679, Y => N_32); - - \r.vaddr_RNI9UHC[14]\ : MX2 - port map(A => maddress(14), B => \vaddr[14]\, S => - \dstate_i_2[8]\, Y => data(14)); - - \r.cctrl.ics_RNO[0]\ : OA1C - port map(A => \N_523\, B => \ics[0]\, C => \ics_0_i_0[0]\, - Y => N_25); - - \r.dstate_RNI5V1O[5]\ : NOR2 - port map(A => mexc_1_sqmuxa, B => \dstate[5]\, Y => - dstate_14); - - \r.dstate_RNIPGERL[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_26, Y => - \mcdo_m_0[31]\); - - \r.dstate_i_0_RNIDBOO[8]\ : NOR3 - port map(A => N_496, B => asi(2), C => \dstate_i_0[8]\, Y - => \rdatasel_1_i_a5_1[7]\); - - \r.dstate_RNI7PANC[1]\ : MX2 - port map(A => maddress(22), B => edata2_0_iv(22), S => - edata_0_sqmuxa_i_0, Y => \edata[22]\); - - \r.valid_0_RNO_0[2]\ : MX2C - port map(A => dataout_0(2), B => \vmask_0_6[2]\, S => - twrite_14, Y => N_2362); - - \r.flush_RNIFDO51\ : OR2A - port map(A => N_136, B => N_533, Y => mexc_1_m_0_a2_0); - - \r.dstate_i_2_RNISK8N1_23[8]\ : OR2B - port map(A => dataout_0(19), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[119]\); - - \r.dstate_RNIPPBLD[1]\ : OR2B - port map(A => \edata[20]\, B => ddatainv_0_6_sqmuxa, Y => - \edata_m_i[20]\); - - \r.dstate_RNIJ4L3K[1]\ : AOI1B - port map(A => \edata[26]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[250]\, Y => \ddatainv_0_1_0_iv_0[26]\); - - \r.dstate_0_RNIT7AKF[2]\ : NOR3C - port map(A => \ctxp_m[17]\, B => \rdatav_0_1_0_iv_2[19]\, C - => \rdatav_0_1_0_iv_4[19]\, Y => rdatav_0_1_0_iv_5_15); - - \r.xaddress_RNIJH2O2_7[0]\ : NOR2B - port map(A => dataout(6), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[230]\); - - \r.vaddr_RNITPDE[5]\ : MX2 - port map(A => maddress(5), B => \vaddr[5]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[81]\); - - \r.holdn_RNII9911\ : AO1C - port map(A => N_507, B => N_3748, C => N_3754, Y => N_534); - - \r.wb.data2[31]\ : DFN1E1 - port map(D => \data2_1[31]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[31]\); - - \r.dstate_RNIBTFDH[1]\ : NAND2 - port map(A => ddatainv_0_6_sqmuxa, B => \edata[31]\, Y => - \edata_m_i[31]\); - - \r.valid_0_RNO_0[0]\ : OR2A - port map(A => \valid_0_RNI7F6M2[0]\, B => N_188, Y => - N_3377); - - \r.paddress[28]\ : DFN1E1 - port map(D => un1_m0_2_29, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[28]\); - - \dctrl.0.un1_dci_2_0\ : XNOR2 - port map(A => maddress(14), B => dataout_0(10), Y => - un1_dci_2_i); - - \r.xaddress_RNI2MB27S2[15]\ : OR3C - port map(A => N_257, B => N_255, C => \dci_m[87]\, Y => - xaddress_RNI2MB27S2(15)); - - \r.wb.data2_RNI87OB[18]\ : OR2B - port map(A => \data2[18]\, B => rdatav_012, Y => - \data2_m[18]\); - - \r.wb.addr_RNO[5]\ : AO1B - port map(A => maddress(5), B => N_2164, C => - \addr_1_1_iv_0_2[5]\, Y => \addr_1[5]\); - - \r.dstate_2_RNICFS88[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_0_11, Y => - \mcdo_m_0[11]\); - - \dctrl.v.cctrlwr13_0_a2_0\ : OR2A - port map(A => asi(3), B => asi(2), Y => cctrlwr13_0_a2_0); - - \un1_r.faddr_I_20\ : XOR2 - port map(A => N_12, B => \faddr[4]\, Y => I_20_1); - - \r.mmctrl1.ctx_0_0_RNIQIPQ[1]\ : NOR2B - port map(A => rst, B => N_2664, Y => \ctx_0_0_RNIQIPQ[1]\); - - \r.dstate_i_RNI2PT49S1[8]\ : NOR3C - port map(A => N_130, B => N_91, C => N_131, Y => N_16_i_0); - - \r.wb.addr_RNO_1[23]\ : OR2B - port map(A => maddress(23), B => addr_2_sqmuxa_0, Y => - N_216); - - \r.dstate_0_RNI5H7N9[7]\ : AOI1B - port map(A => dataout(10), B => rdatav_0_6_sqmuxa_0, C => - \rdatav_0_1_0_iv_0_1[10]\, Y => rdatav_0_1_0_iv_0_2_0); - - \r.wb.addr_RNO_4[5]\ : MX2 - port map(A => \paddress[5]\, B => \addr[5]\, S => N_484_0, - Y => \addr_1_1_iv_0_a3_0_0[5]\); - - \r.xaddress_RNIG9CSTI[22]\ : OA1A - port map(A => edata2_0_iv(22), B => \N_3254_0\, C => N_3864, - Y => \newtag_1_0[22]\); - - \r.wb.data1_RNO_0[6]\ : MX2B - port map(A => edata2_0_iv(6), B => \data2[6]\, S => N_3331, - Y => N_2104); - - \r.dstate_0_RNIS19ED[2]\ : NOR3C - port map(A => \ctxp_m[21]\, B => \rdatav_0_1_0_iv_1[23]\, C - => \rdatav_0_1_0_iv_3[23]\, Y => rdatav_0_1_0_iv_4_23); - - \r.wb.data1_RNO[4]\ : MX2A - port map(A => N_2102, B => maddress(4), S => req_0_sqmuxa_1, - Y => \data1_1[4]\); - - \r.valid_0_RNIE5BNG91[0]\ : OR2B - port map(A => N_3835, B => \valid_0_RNI7F6M2[0]\, Y => - N_301); - - \r.mmctrl1.ctx_RNIN0CR[6]\ : NOR2B - port map(A => rst, B => N_2669, Y => \ctx_RNIN0CR[6]\); - - \r.flush_0_1_RNI9GU5992\ : OR2B - port map(A => maddress(15), B => \N_329\, Y => N_257); - - \r.dstate_RNI0P3L7[2]\ : AOI1B - port map(A => diagdata_31, B => \dstate[2]\, C => - \dcramo_m_0[255]\, Y => \rdatav_0_1_0_iv_3[31]\); - - \r.mmctrl1.e_0_0_RNIUJMK\ : AO1C - port map(A => asi(2), B => \e_0\, C => N_590, Y => - holdn_3_sqmuxa_0_0_a2_2_0); - - \r.dstate_0_RNI2DT77_3[2]\ : AND2 - port map(A => \ico_m[138]\, B => \dcramo_m_0[228]\, Y => - \rdatav_0_1_0_iv_7[4]\); - - \r.dstate_RNIIL8UF[1]\ : MX2 - port map(A => maddress(25), B => edata2_iv_i_0(25), S => - edata_0_sqmuxa_i, Y => \edata[25]\); - - \r.dstate_i_0_RNIDS4F2[8]\ : OAI1 - port map(A => N_2047, B => un19_eholdn_3, C => - \rdatasel_1_i_a5_1[7]\, Y => N_2042); - - \dctrl.0.genmux.un6_validrawv_4_i\ : MX2 - port map(A => dataout_0(1), B => dataout_0(5), S => - maddress(4), Y => N_7); - - \r.wb.data2_RNO[4]\ : MX2A - port map(A => edata2_0_iv(4), B => hrdata_0_4, S => - \dstate_2[7]\, Y => \data2_1[4]\); - - \r.wb.addr_RNO[28]\ : AO1B - port map(A => \addr_1_1_iv_0_a3_1_0[28]\, B => N_2702_i_0, - C => \addr_1_1_iv_0_2[28]\, Y => \addr_1[28]\); - - \r.holdn_RNO_20\ : NOR3B - port map(A => lock, B => N_485, C => cctrlwr19_2_0_a2_1_1, - Y => holdn_RNO_20); - - \r.faddr[4]\ : DFN1E0 - port map(D => \faddr_1[4]\, CLK => lclk_c, E => - faddr_2_sqmuxa, Q => \faddr[4]\); - - \r.dstate_RNI59OG3_0[4]\ : OR2A - port map(A => \dstate[4]\, B => dwrite_1_sqmuxa, Y => - holdn_2_sqmuxa); - - \un1_r.faddr_I_19\ : NOR2B - port map(A => \faddr[3]\, B => \DWACT_FINC_E[0]\, Y => N_12); - - \r.dstate_RNO_12[1]\ : NOR2A - port map(A => N_3089_7, B => N_507, Y => - dstate_tr22_15_0_a2_0); - - \r.dstate_RNO_4[4]\ : NOR3B - port map(A => dstate_tr16_10_0_i_0, B => N_395, C => - N_581_i, Y => dstate_tr16_10_0_i_2); - - \r.dstate_0_RNIIC256_1[7]\ : OR2B - port map(A => dataout(25), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[249]\); - - \dctrl.0.un1_dci_2_0_RNI0AA4\ : AND2 - port map(A => un1_dci_13_i, B => un1_dci_2_i, Y => - un1_dci_NE_1); - - \r.wb.addr_RNO_3[28]\ : AOI1B - port map(A => N_3839, B => N_2165_0, C => N_213, Y => - \addr_1_1_iv_0_0[28]\); - - \r.xaddress_RNO[3]\ : MX2 - port map(A => \addr[3]\, B => maddress(3), S => N_486_0, Y - => N_719); - - \r.wb.addr_RNO_1[25]\ : NOR3C - port map(A => \dci_m[33]\, B => \addr_1_1_iv_0[25]\, C => - \addr_m[25]\, Y => \addr_1_1_iv_2[25]\); - - \r.vaddr_RNI8EHC[23]\ : MX2 - port map(A => maddress(23), B => \vaddr[23]\, S => - \dstate_i_1[8]\, Y => data(23)); - - \r.stpend_RNILN5ACQ1\ : NOR2B - port map(A => \vaddr_1_sqmuxa_0_a2_2\, B => - \stpend_RNI6P41NG3\, Y => \mmudci_trans_op_1_sqmuxa_1\); - - \r.dstate_RNIHILB6[7]\ : OR2B - port map(A => dataout(11), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[235]\); - - \r.xaddress_RNI2MLOE1[9]\ : NOR3 - port map(A => N_3294, B => N_3293, C => \address_i_0[7]\, Y - => N_26); - - \r.mmctrl1.ctx[2]\ : DFN1 - port map(D => \ctx_RNIFGBR[2]\, CLK => lclk_c, Q => - \ctx[2]\); - - \r.faddr_RNIIMO9[6]\ : OR2B - port map(A => \faddr[6]\, B => \un1_p0_2_0[498]\, Y => - flush_0_sqmuxa_0); - - \r.cctrl.ics_RNO_0[0]\ : OAI1 - port map(A => \N_523\, B => maddress(0), C => rst, Y => - \ics_0_i_0[0]\); - - \r.xaddress[30]\ : DFN1E1 - port map(D => maddress(30), CLK => lclk_c, E => N_486, Q - => \addr[30]\); - - \r.faddr_RNO[0]\ : NOR3B - port map(A => rst, B => flush_0, C => \faddr[0]\, Y => - \faddr_1[0]\); - - \r.wb.data1[24]\ : DFN1E0 - port map(D => \data1_1[24]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_12); - - \r.dstate_0_RNIIC256_9[7]\ : NAND2 - port map(A => rdatav_0_6_sqmuxa_0, B => dataout_0(28), Y - => \dcramo_m_0[252]\); - - \r.mmctrl1.ctx_0_0[4]\ : DFN1 - port map(D => \ctx_0_0_RNI7TTO[4]\, CLK => lclk_c, Q => - \ctx_0[4]\); - - \r.wb.addr_RNO_1[2]\ : NOR3C - port map(A => N_316, B => N_317, C => N_318, Y => - \addr_1_0_iv_0_1[2]\); - - \r.dstate_RNIF6E91_3[2]\ : OR2B - port map(A => diagdata_7, B => \dstate[2]\, Y => N_3312); - - \r.dstate_i_2_RNI22GL2[8]\ : OA1C - port map(A => un10_m_en, B => - dstate_tr8_4_9_0_a2_0_a2_0_a2_0, C => N_526, Y => - \dstate_ns_0_7_tz_0[3]\); - - \r.dstate_0_RNIG0R21_0[2]\ : NAND2 - port map(A => \dstate_0[2]\, B => diagdata_28, Y => - \ico_m[162]\); - - \un1_v.cctrlwr19_2_0_o2_0_0\ : OA1 - port map(A => N_223, B => N_3091_3, C => cctrlwr12, Y => - cctrlwr19_2_0_o2_0_0); - - \r.wb.addr_RNO_0[6]\ : AOI1B - port map(A => \paddress[6]\, B => N_3792, C => N_3731, Y - => \addr_1_1_iv_0_2[6]\); - - \r.dstate_RNI6285A[1]\ : NOR2B - port map(A => \edata[0]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[0]\); - - \r.wb.addr_RNO_4[3]\ : MX2 - port map(A => \paddress[3]\, B => \addr[3]\, S => N_484, Y - => N_675); - - \r.dstate_i_2_RNI86U12[8]\ : OR2B - port map(A => un1_m0_2_40, B => miscdata_3_sqmuxa, Y => - \mmudco_m[41]\); - - \r.xaddress_RNIN7J17S2[14]\ : OR3C - port map(A => N_239, B => N_237, C => \dci_m[86]\, Y => - xaddress_RNIN7J17S2(14)); - - \r.holdn_RNIBQEJ\ : NOR3B - port map(A => enaddr, B => \hold\, C => \dstate_i_1[8]\, Y - => N_486); - - \r.wb.addr_RNO_5[2]\ : OR3B - port map(A => N_115, B => N_421, C => data2_0_sqmuxa_1, Y - => N_317); - - \r.wb.addr_RNO_4[0]\ : MX2 - port map(A => \paddress_0[0]\, B => \addr[0]\, S => N_484, - Y => \paddress[0]\); - - \r.dstate_0_RNI1JGE7_1[2]\ : AOI1B - port map(A => diagdata_15, B => \dstate_0[2]\, C => - \dcramo_m_0[239]\, Y => \rdatav_0_1_0_iv_0_5[15]\); - - \r.xaddress[26]\ : DFN1E1 - port map(D => maddress(26), CLK => lclk_c, E => N_486, Q - => \addr[26]\); - - \r.req_RNO_3\ : NOR3A - port map(A => N_2471_i, B => req_0_sqmuxa_1_0, C => - addr_1_sqmuxa_0, Y => req_1_1); - - \r.wb.addr_RNO_0[16]\ : NOR3C - port map(A => \dci_m[24]\, B => \addr_1_1_iv_0[16]\, C => - \addr_m[16]\, Y => \addr_1_1_iv_2[16]\); - - \r.dstate_0_RNI1JGE7_5[2]\ : AOI1B - port map(A => diagdata_16, B => \dstate_0[2]\, C => - \dcramo_m_0[240]\, Y => \rdatav_0_1_1_iv_5[16]\); - - \r.wb.addr_RNO_4[30]\ : OR2B - port map(A => \address[30]\, B => N_514, Y => \addr_m[30]\); - - \r.vaddr_RNIEUHC[18]\ : MX2 - port map(A => maddress(18), B => \vaddr[18]\, S => - \dstate_i_1[8]\, Y => data(18)); - - \r.dstate_i_2_RNI1RM12[8]\ : OR2B - port map(A => un1_m0_2_71, B => miscdata_4_sqmuxa, Y => - \mmudco_m[72]\); - - \r.vaddr_RNI5AEE[9]\ : MX2 - port map(A => maddress(9), B => \vaddr[9]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[85]\); - - \r.dstate_RNIF38I3[4]\ : OR3A - port map(A => \dstate[4]\, B => enaddr, C => N_580, Y => - N_3682); - - \r.dstate_i_RNI9BVJ3[8]\ : MX2C - port map(A => \vmask_0_4[7]\, B => N_2027, S => - \dstate_i[8]\, Y => \vmask_0_5[7]\); - - \r.wb.data1_RNO_0[17]\ : MX2C - port map(A => edata2_0_iv(17), B => \data2[17]\, S => - N_3331_0, Y => N_2115); - - \r.dstate_i_0_RNIH0PPES[8]\ : OR3C - port map(A => N_305, B => N_304, C => N_306, Y => - dstate_i_0_RNIH0PPES(8)); - - \r.xaddress[19]\ : DFN1E1 - port map(D => maddress(19), CLK => lclk_c, E => N_486, Q - => \addr[19]\); - - \r.wb.data2_RNILJ3M3[0]\ : NOR3C - port map(A => \dcramo_m[408]\, B => \data2_m[0]\, C => - \dcramo_m[96]\, Y => \rdatav_0_1_0_iv_1[0]\); - - \r.wbinit_RNIA7FN3_1\ : NOR2A - port map(A => N_487, B => dwrite_1_sqmuxa, Y => - addr_1_sqmuxa); - - \r.xaddress_RNIQF6M2_5[0]\ : NAND2 - port map(A => N_2088, B => dataout(27), Y => - \dcramo_m_i[251]\); - - \r.read_RNITCGI61\ : AOI1B - port map(A => \N_425_0\, B => N_78_0, C => - \ddatainv_0_1_0_iv_0[25]\, Y => \ddatainv_0_1_0_iv_2[25]\); - - \r.holdn_RNO_22\ : OR2B - port map(A => un121_m_en_i_s_0, B => hit, Y => N_60); - - \dctrl.un1_eholdn_2_9_0\ : OR3A - port map(A => cctrlwr12, B => N_3779, C => cctrlwr13, Y => - un1_eholdn_2_9); - - \r.xaddress[15]\ : DFN1E1 - port map(D => maddress(15), CLK => lclk_c, E => N_486, Q - => \addr[15]\); - - \r.faddr_RNO[4]\ : NOR3C - port map(A => rst, B => flush_0, C => I_20_1, Y => - \faddr_1[4]\); - - \r.dstate_i_2_RNIMN842[8]\ : OR2B - port map(A => un1_m0_2_57, B => miscdata_4_sqmuxa, Y => - \mmudco_m[58]\); - - \r.mmctrl1.ctxp_RNI0LB66[23]\ : AOI1B - port map(A => \ctxp[23]\, B => N_3344_i_0_0, C => - \rdatav_0_1_0_iv_1[25]\, Y => \rdatav_0_1_0_iv_2[25]\); - - \r.dstate_2_RNIFOF68[7]\ : OR2B - port map(A => \dstate_2[7]\, B => hrdata_25, Y => - \mcdo_m_0[30]\); - - \r.wb.addr_RNO_2[30]\ : OR2B - port map(A => maddress(30), B => addr_2_sqmuxa, Y => - \dci_m[38]\); - - \r.mmctrl1.ctxp_RNIJ9F32[3]\ : OR2B - port map(A => \ctxp[3]\, B => N_3344_i_0, Y => N_3395); - - \r.nomds_RNI2PHA\ : NOR2 - port map(A => nomds, B => flush, Y => dstate_tr20_0); - - \r.paddress_RNIAJN31[2]\ : MX2 - port map(A => \paddress[2]\, B => \addr[2]\, S => N_484, Y - => N_115); - - \r.holdn_RNIL0894\ : NOR2 - port map(A => N_3665_1, B => N_582, Y => taddr_2_sqmuxa); - - \un1_v.cctrlwr19_2_0_o2_2\ : OR2A - port map(A => asi(3), B => N_481, Y => N_557); - - \r.dstate_i_2_RNIVQM12[8]\ : OR2B - port map(A => un1_m0_2_69, B => miscdata_4_sqmuxa, Y => - \mmudco_m[70]\); - - \r.xaddress_RNIPQFG1[1]\ : AO1C - port map(A => \addr[1]\, B => N_3782, C => N_3621, Y => - ddatainv_0_0_sqmuxa); - - \r.wb.addr_RNO[4]\ : AO1B - port map(A => maddress(4), B => N_2164, C => - \addr_1_1_iv_0_2[4]\, Y => \addr_1[4]\); - - \r.mmctrl1.e_0_0_RNITGT6\ : NOR2A - port map(A => \e_0\, B => read_0, Y => - cctrlwr19_2_0_a2_1_1_0); - - \r.faddr_RNO[6]\ : NOR3C - port map(A => rst, B => flush_0, C => I_31_1, Y => - \faddr_1_i[6]\); - - \r.dstate_RNITAO34[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[2]\, Y => \ddatainv_0_1_0_iv_1[18]\); - - \r.read_RNO_0\ : MX2 - port map(A => read, B => read_1, S => N_486_0, Y => N_2684); - - \r.wb.data1[10]\ : DFN1E0 - port map(D => \data1_1[10]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data(10)); - - \r.dstate_i_RNIEHMTN92[8]\ : NOR2A - port map(A => edata2_iv_i_0(24), B => \N_3254_0\, Y => - dci_m_88); - - \r.xaddress_RNIQF6M2_7[0]\ : OR2B - port map(A => dataout(22), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[246]\); - - \r.wb.addr_RNO_5[16]\ : MX2 - port map(A => \paddress_0[16]\, B => \addr[16]\, S => N_484, - Y => \paddress[16]\); - - \r.wb.addr_RNO_3[27]\ : AOI1B - port map(A => N_293, B => addr_1_sqmuxa_0, C => N_249, Y - => \addr_1_1_iv_0_0[27]\); - - \r.stpend_RNI0U832\ : NOR2A - port map(A => N_485, B => read_1, Y => - dstate_tr22_15_a2_1_1_0); - - \r.xaddress[2]\ : DFN1 - port map(D => \xaddress_1[2]\, CLK => lclk_c, Q => - \addr[2]\); - - \r.dstate_i_RNI6FTV1[8]\ : OR2A - port map(A => N_485, B => \dstate_i[8]\, Y => N_3331); - - \r.wb.data2[27]\ : DFN1E1 - port map(D => \data2_1[27]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[27]\); - - \r.wb.addr_RNO_2[29]\ : AND2 - port map(A => N_261, B => \addr_1_1_iv_0_0[29]\, Y => - \addr_1_1_iv_0_1[29]\); - - \r.stpend_RNIQH21992\ : OR2B - port map(A => dstate_tr22_15_a2_1_1_0, B => N_3583, Y => - dstate_tr22_15_a2_1); - - \r.dstate_RNI29EH[1]\ : OR2 - port map(A => \dstate[1]\, B => mexc_0_sqmuxa, Y => - mexc_0_sqmuxa_0); - - \r.dstate_i_RNID1NU1[8]\ : AO1B - port map(A => \vmask_0_1_2_o3_0_a2_0[3]\, B => - \dstate_i[8]\, C => N_348, Y => \dstate_i_RNID1NU1[8]\); - - \r.mmctrl1.ctxp[20]\ : DFN1E1 - port map(D => maddress(22), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[20]\); - - \r.wb.data2_RNI0S032[14]\ : AOI1B - port map(A => \data2[14]\, B => rdatav_012_0, C => - \dcramo_m[110]\, Y => \rdatav_0_1_0_iv_0[14]\); - - \r.mmctrl1wr\ : DFN1 - port map(D => mmctrl1wr_RNO, CLK => lclk_c, Q => mmctrl1wr); - - \r.read_RNIAQK32\ : NOR2B - port map(A => \N_425\, B => hrdata_0_13, Y => \mcdo_m[13]\); - - \r.dstate_RNIOE146[7]\ : NOR2A - port map(A => rdatav_0_6_sqmuxa_3, B => \dstate[7]\, Y => - rdatav_0_6_sqmuxa); - - \r.cctrl.dcs_RNO_0[1]\ : MX2C - port map(A => maddress(3), B => \dcs[1]\, S => \N_523\, Y - => N_672); - - \dctrl.un1_eholdn_2_9_0_a2\ : NOR2 - port map(A => N_2938_2, B => N_519, Y => N_3779); - - \r.read_RNI7CD8A\ : OR2B - port map(A => \N_425_0\, B => hrdata_0_18, Y => - \mcdo_m_i[18]\); - - \r.paddress[20]\ : DFN1E1 - port map(D => N_417, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[20]\); - - \r.dstate_RNIDKUIH[1]\ : AO1 - port map(A => \edata[10]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[234]\, Y => \ddatainv_0_1_1_iv_0[10]\); - - \r.dstate_i_0_RNIL7FGFS[8]\ : OR3C - port map(A => N_302, B => N_301, C => N_303, Y => - dstate_i_0_RNIL7FGFS(8)); - - \r.dstate_2[7]\ : DFN1 - port map(D => \dstate_nss[1]\, CLK => lclk_c, Q => - \dstate_2[7]\); - - \r.wb.data2_RNO[27]\ : MX2 - port map(A => edata2_iv_i_0(27), B => hrdata_0_27, S => - \dstate_1[7]\, Y => \data2_1[27]\); - - \r.holdn_RNO_1\ : NOR3B - port map(A => holdn_0_3, B => holdn_1_sqmuxa_3, C => - holdn_1_5, Y => holdn_0_5); - - \r.flush_0_1_RNIBGU5992\ : OR2B - port map(A => maddress(17), B => \N_329\, Y => N_3893); - - \r.dstate_ns_i_a4_i_o2_2[0]\ : OR2B - port map(A => N_3799, B => N_537, Y => N_665); - - \r.dstate_RNICPGHH[1]\ : AO1 - port map(A => \edata[12]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[236]\, Y => \ddatainv_0_1_1_iv_0[12]\); - - \r.req_RNO_2\ : NOR3B - port map(A => \req_0_sqmuxa[0]\, B => N_485, C => - \dstate_i_0[8]\, Y => req_0_sqmuxa_3_1); - - \r.dstate_i_2_RNITQRS1_3[8]\ : NOR2B - port map(A => maddress(8), B => N_3321, Y => N_3344_i_0_0); - - \r.vaddr_RNIJIIC[19]\ : MX2 - port map(A => maddress(19), B => \vaddr[19]\, S => - \dstate_i_2[8]\, Y => data(19)); - - \r.dstate_i_0_RNIVIRH6[8]\ : NOR2B - port map(A => \vmask_0_5[4]\, B => \dstate_RNIR2CO3[4]\, Y - => N_128_1); - - \r.dstate_i_0_RNIMF0H7[8]\ : OR2A - port map(A => addr_0_sqmuxa_1, B => addr_2_sqmuxa, Y => - N_2164); - - \r.valid_0_RNIS2NB[4]\ : NOR2B - port map(A => \valid_0[4]\, B => hit, Y => - \vmask_0_5_1_a4_0_0[4]\); - - \r.mmctrl1.ctx_0_0[0]\ : DFN1 - port map(D => \ctx_RNIB8BR[0]\, CLK => lclk_c, Q => - \ctx_0[0]\); - - \r.wb.addr[9]\ : DFN1 - port map(D => \addr_1[9]\, CLK => lclk_c, Q => \address[9]\); - - \r.vaddr_RNIGUHC[27]\ : MX2 - port map(A => maddress(27), B => \vaddr[27]\, S => - \dstate_i_1[8]\, Y => data(27)); - - \r.dstate_RNI4NKBG[1]\ : AOI1B - port map(A => \edata[19]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[243]\, Y => \ddatainv_0_1_0_iv_0[19]\); - - \r.wb.data1[8]\ : DFN1E0 - port map(D => N_8, CLK => lclk_c, E => data1_0_sqmuxa, Q - => data(8)); - - \r.dstate_0_RNI2VNA[7]\ : NOR2A - port map(A => \dstate_0[7]\, B => N_508, Y => mexc_0_sqmuxa); - - \r.read_RNICAQK41\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[16]\, B => - \mcdo_m_i[16]\, C => \ddatainv_0_1_0_iv_1[16]\, Y => - read_RNICAQK41); - - \r.mmctrl1.e_0_0_RNI2K342\ : OR3B - port map(A => N_557, B => cctrlwr19_2_0_a2_1_1_0, C => - cctrlwr13, Y => cctrlwr19_2_0_a2_1_1); - - \r.valid_0_RNO[1]\ : AO1B - port map(A => dataout_0(1), B => N_88, C => - \valid_0_1_1_0[1]\, Y => \valid_0_1[1]\); - - \r.read_RNIC70OF1\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[20]\, B => - \mcdo_m_i[20]\, C => \ddatainv_0_1_0_iv_1[20]\, Y => - read_RNIC70OF1); - - \r.dstate_2_RNILLB4J[7]\ : OR2B - port map(A => \dstate_2[7]\, B => N_262_0, Y => - \mcdo_m_0[20]\); - - \r.stpend_RNINHS9\ : NOR2 - port map(A => read_1, B => stpend, Y => N_3089_7); - - \r.wb.data2_RNI7BOB[24]\ : OR2B - port map(A => \data2[24]\, B => rdatav_012_0, Y => - \data2_m[24]\); - - \v.mmctrl1.ctxp_1_sqmuxa_2\ : NOR2 - port map(A => \addr[9]\, B => \addr[10]\, Y => e_0_sqmuxa_2); - - \r.wb.addr_RNO_3[5]\ : OR2B - port map(A => un1_m0_2_6, B => addr_1_sqmuxa, Y => N_288); - - \r.dstate_tr22_15_a2_6_i_o2\ : OR2A - port map(A => N_549, B => asi(2), Y => N_595); - - \r.wb.lock_RNO_2\ : OR3A - port map(A => \dstate_RNI5GFM4[5]\, B => N_56, C => - lock_1_iv_0_a2_0, Y => N_3553); - - \r.wb.addr_RNO_4[31]\ : MX2 - port map(A => \paddress[31]\, B => \addr[31]\, S => N_484, - Y => N_544); - - \r.wbinit_RNIA7FN3\ : OR2B - port map(A => dwrite_1_sqmuxa, B => N_487, Y => - addr_0_sqmuxa); - - \r.dstate_i_0_RNIE3RBE91[8]\ : OR3B - port map(A => N_3835, B => dataout_0(3), C => - \dstate_i_0[8]\, Y => N_305); - - \r.stpend_RNII1UI\ : OR2B - port map(A => stpend, B => N_487, Y => - ready_0_sqmuxa_0_a2_0_a2_0); - - \r.dstate_RNI4AS1D[1]\ : AO1 - port map(A => \edata[3]\, B => ddatainv_0_3_sqmuxa, C => - \dcramo_m[227]\, Y => \ddatainv_0_1_1_iv_0[3]\); - - \r.mmctrl1.ctx_0_0[5]\ : DFN1 - port map(D => \ctx_0_0_RNI91UO[5]\, CLK => lclk_c, Q => - \ctx_0[5]\); - - \r.dstate_0_RNI1JGE7_3[2]\ : AOI1B - port map(A => diagdata_21, B => \dstate_0[2]\, C => - \dcramo_m_0[245]\, Y => \rdatav_0_1_1_iv_5[21]\); - - \r.wb.data2_RNI3RN44[26]\ : NOR3C - port map(A => \dcramo_m[122]\, B => \data2_m[26]\, C => - \mmudco_m[69]\, Y => \rdatav_0_1_0_iv_1[26]\); - - \r.dstate_RNO_4[5]\ : OR3 - port map(A => N_3514, B => ready, C => - \dstate_ns_0_8_tz[3]\, Y => \dstate_RNO_4[5]\); - - \r.dstate_RNIH3CFG[1]\ : MX2 - port map(A => maddress(26), B => edata2_iv_i_0(26), S => - edata_0_sqmuxa_i, Y => \edata[26]\); - - \r.wb.data1_RNO[17]\ : MX2A - port map(A => N_2115, B => maddress(17), S => - req_0_sqmuxa_1, Y => \data1_1[17]\); - - \r.holdn_RNIQ28U\ : OR3A - port map(A => maddress(1), B => N_3763, C => maddress(0), Y - => N_3626); - - \r.wb.data2_RNITQN44[23]\ : NOR3C - port map(A => \dcramo_m[119]\, B => \data2_m[23]\, C => - \mmudco_m[66]\, Y => \rdatav_0_1_0_iv_1[23]\); - - \r.valid_0_RNO_0[4]\ : MX2C - port map(A => dataout_0(4), B => N_128_1, S => twrite_14, Y - => N_2364); - - \r.mmctrl1.ctxp_RNIULJ12[15]\ : OR2B - port map(A => \ctxp[15]\, B => N_3344_i_0, Y => - \ctxp_m[15]\); - - \dctrl.twrite_14_iv_0_a2_a0_RNIKNNUB1\ : NOR3 - port map(A => flush_RNICQGM51, B => flush_RNITKH06, C => - twrite_14_iv_0_a2_a0, Y => N_3322); - - \r.wb.addr_RNO_2[31]\ : OR2B - port map(A => maddress(31), B => addr_2_sqmuxa, Y => N_3652); - - \r.nomds\ : DFN1 - port map(D => nomds_RNO, CLK => lclk_c, Q => nomds); - - \r.dstate[5]\ : DFN1 - port map(D => \dstate_nss[3]\, CLK => lclk_c, Q => - \dstate[5]\); - - \r.wb.data2_RNI2S032[16]\ : NOR2B - port map(A => \data2_m[16]\, B => \dcramo_m[112]\, Y => - \rdatav_0_1_1_iv_0[16]\); - - \r.wb.addr_RNO_0[12]\ : OA1 - port map(A => \data[12]\, B => N_2709_i_0, C => - addr_1_sqmuxa_2_0, Y => \addr_1_1_iv_0_a3_2_0[12]\); - - \r.mmctrl1.nf_RNI57J42\ : OR2B - port map(A => \nf\, B => miscdata_0_sqmuxa, Y => nf_m); - - \r.dstate_i_0_RNIJU6E[8]\ : NOR2 - port map(A => asi(3), B => \dstate_i_0[8]\, Y => - \dstate_ns_i_a4_i_a2_7_0[0]\); - - \r.xaddress_RNIQF6M2_4[0]\ : NAND2 - port map(A => N_2088, B => dataout_0(31), Y => - \dcramo_m_i[255]\); - - \r.wb.data2_RNINR3M3[2]\ : NOR3C - port map(A => \dcramo_m[410]\, B => \data2_m[2]\, C => - \dcramo_m[98]\, Y => \rdatav_0_1_0_iv_1[2]\); - - \r.dstate_2_RNIN4AJL[7]\ : OR3C - port map(A => \rdatav_0_1_0_iv_3[8]\, B => - \rdatav_0_1_0_iv_2[8]\, C => \mcdo_m_0[8]\, Y => data_0_8); - - \r.dstate_i_RNI25CU792[8]\ : OR2 - port map(A => N_561, B => \N_121\, Y => N_3604); - - \r.wb.data1_RNO[9]\ : MX2A - port map(A => N_2107, B => maddress(9), S => req_0_sqmuxa_1, - Y => \data1_1[9]\); - - \r.wbinit_RNIE3VB\ : NOR2B - port map(A => wbinit, B => \dstate[4]\, Y => - \dstate_ns_i_a4_i_a2_15_0[0]\); - - \r.vaddr_RNI4AHC[13]\ : MX2 - port map(A => maddress(13), B => \vaddr[13]\, S => - \dstate_i_1[8]\, Y => data(13)); - - \r.vaddr[1]\ : DFN1E1 - port map(D => maddress(1), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[1]\); - - \r.flush_0_1_RNICKU5992\ : NOR2B - port map(A => maddress(25), B => \N_329\, Y => N_236); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.dstate_ns_i_a4_i_o2_6[0]\ : NOR2A - port map(A => \dcs[0]\, B => lock, Y => N_501); - - \r.dstate_i_2_RNIDAC82[8]\ : OR3B - port map(A => dstate_tr22_15_a2_2_m8_i_a5_0_0, B => asi(4), - C => N_526, Y => dstate_tr22_15_a2_2_m8_i_0_tz); - - \r.read_RNISLPNU\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[18]\, B => - \mcdo_m_i[18]\, C => \ddatainv_0_1_0_iv_1[18]\, Y => - read_RNISLPNU); - - \r.valid_0_RNO_2[7]\ : OR3 - port map(A => N_3286_1, B => flush_i, C => \N_3254_0\, Y - => N_3286); - - \r.vaddr[0]\ : DFN1E1 - port map(D => maddress(0), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[0]\); - - \r.flush_RNIMB2T1\ : OR2B - port map(A => flush_0, B => rdatav_0_0_sqmuxa, Y => flush_m); - - \r.ready_RNIAJ1U1\ : OR2A - port map(A => ready, B => N_508, Y => N_510); - - \r.wb.data2_RNIIJT36[8]\ : NOR3C - port map(A => \rdatav_0_1_0_iv_0[8]\, B => \mmudco_m[44]\, - C => \ctxp_m[6]\, Y => \rdatav_0_1_0_iv_2[8]\); - - \r.wb.data1_RNO_0[14]\ : MX2C - port map(A => edata2_0_iv(14), B => \data2[14]\, S => - N_3331_0, Y => N_2112); - - \r.dstate_RNIMHBNC[1]\ : MX2 - port map(A => maddress(23), B => edata2_0_iv(23), S => - edata_0_sqmuxa_i_0, Y => \edata[23]\); - - \r.wb.addr_RNO_3[23]\ : OR2B - port map(A => \address[23]\, B => N_514, Y => N_3889); - - \r.vaddr_RNI22HC[20]\ : MX2 - port map(A => maddress(20), B => \vaddr[20]\, S => - \dstate_i_1[8]\, Y => data(20)); - - \r.dstate_RNO_16[4]\ : NOR2B - port map(A => asi(4), B => asi(1), Y => - dstate_tr16_13_0_0_a2_0_0); - - \r.dstate_RNISEIMC[1]\ : MX2 - port map(A => maddress(13), B => edata2_0_iv(13), S => - edata_0_sqmuxa_i_0, Y => \edata[13]\); - - \r.wb.data2_RNISLJ16[24]\ : NOR3B - port map(A => \mmudco_m[67]\, B => \rdatav_0_1_0_iv_0[24]\, - C => miscdata_0_sqmuxa, Y => \rdatav_0_1_0_iv_2[24]\); - - \r.read_RNIAQJ831\ : OR3 - port map(A => \mcdo_m[9]\, B => \edata_m_1[1]\, C => - \ddatainv_0_1_1_iv_0[9]\, Y => read_RNIAQJ831); - - \r.dstate_RNI2MBNC[1]\ : MX2 - port map(A => maddress(19), B => edata2_0_iv(19), S => - edata_0_sqmuxa_i, Y => \edata[19]\); - - \r.read_RNIC9FCH\ : NOR2B - port map(A => \N_425\, B => hrdata_0_15, Y => \mcdo_m[15]\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNITIN93\ : OR2A - port map(A => dcs_1_i_s_0_0, B => N_527, Y => N_102); - - \r.mmctrl1.ctxp[16]\ : DFN1E1 - port map(D => maddress(18), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[16]\); - - \r.dstate_i_2_RNISK8N1_5[8]\ : OR2B - port map(A => dataout_0(22), B => rdatasel_1_sqmuxa_1, Y - => \dcramo_m[122]\); - - \v.mmctrl1.e_0_sqmuxa_RNO\ : NOR2A - port map(A => mmctrl1wr, B => \addr[8]\, Y => e_0_sqmuxa_0); - - \r.hit_RNIQDAT1\ : NOR2B - port map(A => twrite_11_m_0_a2_0_2, B => - twrite_11_m_0_a2_0_1, Y => hit_1_iv_0_a2_0); - - \dctrl.un30_m_en\ : OR2B - port map(A => maddress(8), B => un30_m_en_0, Y => un30_m_en); - - \r.wb.data1[4]\ : DFN1E0 - port map(D => \data1_1[4]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(4)); - - \r.wb.addr_RNO_5[12]\ : MX2 - port map(A => \paddress[12]\, B => \addr[12]\, S => N_484_0, - Y => N_676); - - \r.dstate_i_2_RNIM5U12[8]\ : OR2B - port map(A => un1_m0_2_41, B => miscdata_3_sqmuxa, Y => - \mmudco_m[42]\); - - \r.dstate_RNIKMHIJ[1]\ : AOI1B - port map(A => \edata[25]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[249]\, Y => \ddatainv_0_1_0_iv_0[25]\); - - \r.wb.addr_RNO_4[18]\ : MX2 - port map(A => \paddress[18]\, B => \addr[18]\, S => N_484_0, - Y => N_3841); - - \r.vaddr[22]\ : DFN1E1 - port map(D => maddress(22), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[22]\); - - \r.nomds_RNO_2\ : NOR3B - port map(A => \req\, B => \dstate_i_0[8]\, C => N_508, Y - => dstate_15_1); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_13\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_9, B => - eaddress_23, C => eaddress_19, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_13); - - \r.wb.addr_RNO[3]\ : AO1B - port map(A => maddress_0_2, B => N_2164, C => - \addr_1_1_iv_0_2[3]\, Y => \addr_1[3]\); - - \r.wb.lock_RNO\ : OR3C - port map(A => N_3553, B => N_3554, C => N_3555, Y => lock_1); - - \r.mmctrl1.e_RNIKN3D\ : NOR2 - port map(A => asi(3), B => \e\, Y => e_RNIKN3D); - - \r.xaddress_RNIEMDM4[11]\ : MX2 - port map(A => maddress(11), B => \addr[11]\, S => - un1_taddr_1_sqmuxa, Y => N_2238); - - \un1_v.cctrlwr19_2_0_o2_7_0\ : NOR2A - port map(A => N_3798, B => N_206_1, Y => - cctrlwr19_2_0_o2_7_0); - - \r.wb.addr_RNO_3[25]\ : AOI1B - port map(A => \paddress[25]\, B => N_2165_0, C => - \mmudco_m[27]\, Y => \addr_1_1_iv_0[25]\); - - \r.xaddress[29]\ : DFN1E1 - port map(D => maddress(29), CLK => lclk_c, E => N_486, Q - => \addr[29]\); - - \r.flush_RNIGUM2OH3\ : AO1C - port map(A => N_349, B => \vmask_0_5[4]\, C => - \vmask_0_1_2_0[4]\, Y => flush_RNIGUM2OH3); - - \r.wb.addr_RNO_4[29]\ : AOI1B - port map(A => N_2165_0, B => N_546, C => N_262, Y => - \addr_1_1_iv_0_0[29]\); - - \r.valid_0_RNIP2NB[1]\ : NOR2B - port map(A => \valid_0[1]\, B => hit, Y => N_95); - - \r.mmctrl1.ctx_0_0[6]\ : DFN1 - port map(D => \ctx_RNIN0CR[6]\, CLK => lclk_c, Q => - \ctx_0[6]\); - - \r.xaddress[25]\ : DFN1E1 - port map(D => maddress(25), CLK => lclk_c, E => N_486, Q - => \addr[25]\); - - \r.cctrl.ics_RNIIQS04[1]\ : AOI1B - port map(A => un1_m0_2_36, B => miscdata_3_sqmuxa, C => - N_3231, Y => \rdatav_0_1_0_iv_i_a4_3[1]\); - - \dctrl.vmaskraw_1_i_o2_i_a2_0[1]\ : NAND2 - port map(A => N_559, B => \vmaskraw_1_i_o2_i_a2_0_0[1]\, Y - => N_3654); - - \r.wb.data1[22]\ : DFN1E0 - port map(D => \data1_1[22]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_0_22); - - \r.dstate_1_RNI5ICU7[7]\ : OR2B - port map(A => \dstate_1[7]\, B => hrdata_24, Y => - \mcdo_m_0[29]\); - - \un1_r.faddr_I_13\ : XOR2 - port map(A => N_17, B => \faddr[3]\, Y => I_13_5); - - \r.wb.addr_RNO_1[9]\ : OR2B - port map(A => un1_m0_2_10, B => addr_1_sqmuxa, Y => - \mmudco_m[11]\); - - \r.flush_0_1_RNIAGU5992\ : OR2B - port map(A => maddress(16), B => \N_329\, Y => N_242); - - \r.dstate_i_2_RNIP3SSB92[8]\ : AOI1B - port map(A => dstate_tr22_15_a2_2_m8_i_0_tz, B => N_3576, C - => N_3583, Y => dstate_tr22_15_a2_2_m8_i_0_0); - - \r.wb.data1_RNO[5]\ : NOR3 - port map(A => N_3364, B => N_3365, C => N_3366, Y => N_21); - - \r.dstate_RNO_5[1]\ : AO1 - port map(A => N_3569, B => N_90, C => dstate_tr22_15_a2_1, - Y => \dstate_RNO_5[1]\); - - \r.vaddr[6]\ : DFN1E1 - port map(D => maddress(6), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[6]\); - - \r.wb.addr_RNO_0[11]\ : OR2B - port map(A => maddress(11), B => addr_2_sqmuxa, Y => N_282); - - \r.mmctrl1.ctx_0_0_RNID9UO[7]\ : NOR2B - port map(A => rst, B => N_2670, Y => \ctx_0_0_RNID9UO[7]\); - - \r.dstate_RNI65K2G[1]\ : MX2 - port map(A => maddress(24), B => edata2_iv_i_0(24), S => - edata_0_sqmuxa_i_0, Y => \edata[24]\); - - \r.dstate_i_RNI1701O92[8]\ : OR2A - port map(A => edata2_iv_i_0(29), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_93); - - \r.dstate_i_2_RNIJB842[8]\ : OR2B - port map(A => un1_m0_2_54, B => miscdata_4_sqmuxa, Y => - \mmudco_m[55]\); - - \r.wb.addr_RNO_1[18]\ : OR2B - port map(A => maddress(18), B => addr_2_sqmuxa_0, Y => - N_187); - - \r.wb.addr_RNO[0]\ : OR3C - port map(A => \addr_1_1_iv_1[0]\, B => \mmudco_m[2]\, C => - \dci_m[8]\, Y => \addr_1[0]\); - - \r.burst_RNO_6\ : OR2A - port map(A => req_2_sqmuxa_1_0, B => un47_m_en, Y => - burst_1_m8_i_o5_0); - - \r.dstate_i_RNITKBIK92[8]\ : OR2A - port map(A => edata2_0_iv(20), B => \N_3254_0\, Y => N_156); - - \r.hit_RNO_0\ : AO1 - port map(A => \cache\, B => N_84, C => N_486_0, Y => N_9); - - \r.flush_0_1_RNI8GU5992\ : OR2B - port map(A => maddress(14), B => \N_329\, Y => N_239); - - \r.ready_RNO_1\ : OA1B - port map(A => N_511, B => ready_0_sqmuxa_0_a2_1, C => N_572, - Y => ready_0_sqmuxa_0_0); - - \r.dstate_RNO_13[4]\ : NOR3C - port map(A => N_395, B => N_3505_i, C => N_16886_tz_tz, Y - => dstate_ns_0_2064_1); - - \r.mmctrl1.e_RNITD9PLG3\ : OR2A - port map(A => N_490, B => N_564, Y => N_3810); - - \r.dstate_i_0_RNI764QAD2[8]\ : OA1A - port map(A => N_611, B => \dstate_i_0[8]\, C => - \dstate_ns_i_a4_i_8[0]\, Y => \dstate_ns_i_a4_i_9[0]\); - - \r.cctrl.ics[0]\ : DFN1 - port map(D => N_25, CLK => lclk_c, Q => \ics[0]\); - - \r.wb.data1_RNO_0[16]\ : MX2C - port map(A => edata2_0_iv(16), B => \data2[16]\, S => - N_3331, Y => N_2114); - - \r.dstate_RNO_0[0]\ : AOI1B - port map(A => \dstate_ns_0_0_a2_0_3[8]\, B => - un1_m0_2_0(35), C => N_135, Y => \dstate_ns_0_0_0[8]\); - - \r.xaddress_RNICIF9O[1]\ : AOI1B - port map(A => \edata[14]\, B => ddatainv_0_4_sqmuxa, C => - \edata_m_4_i[6]\, Y => \ddatainv_0_1_0_iv_1[30]\); - - \r.wb.data1[9]\ : DFN1E0 - port map(D => \data1_1[9]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(9)); - - \r.dstate_i_2_RNISK8N1_1[8]\ : OR2B - port map(A => dataout(32), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[412]\); - - un1_taddr_1_sqmuxa_0_o2 : AO1C - port map(A => read_1, B => enaddr, C => hold_0, Y => N_582); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_11\ : NOR3B - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_3, B => - vaddr_1_sqmuxa_0_a2_4_m1_e_5, C => eaddress_15, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_11); - - \r.su\ : DFN1E1 - port map(D => msu, CLK => lclk_c, E => N_486_0, Q => su_0); - - \r.dstate_RNIVC9NC[1]\ : MX2 - port map(A => maddress(16), B => edata2_0_iv(16), S => - edata_0_sqmuxa_i_0, Y => \edata[16]\); - - \r.dstate[1]\ : DFN1 - port map(D => \dstate_nss[7]\, CLK => lclk_c, Q => - \dstate[1]\); - - \r.mmctrl1.ctxp[4]\ : DFN1E1 - port map(D => maddress(6), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[4]\); - - \r.size_RNIC6U21[1]\ : OA1C - port map(A => maddress(1), B => N_3757, C => N_3768, Y => - N_574); - - \r.dstate_RNI2KLDD[1]\ : OR2B - port map(A => ddatainv_0_4_sqmuxa, B => - \dstate_RNII450C[1]\, Y => \edata_m_0_i[8]\); - - \r.dstate_0_RNIIC256_3[7]\ : OR2B - port map(A => dataout(23), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[247]\); - - \r.dstate_0_RNIQSEE4[7]\ : AO1C - port map(A => burst_0_sqmuxa, B => \dstate_0[7]\, C => - data2_0_sqmuxa_1, Y => N_2165_0); - - \r.cctrl.dcs_RNO[0]\ : NOR2A - port map(A => rst, B => N_671, Y => \dcs_RNO[0]\); - - \r.dstate_i_2_RNIO4022[8]\ : OR2B - port map(A => un1_m0_2_38, B => miscdata_3_sqmuxa, Y => - N_3399); - - \dctrl.0.un1_dci_1_0\ : XNOR2 - port map(A => dataout_0(9), B => maddress(13), Y => - un1_dci_1_i); - - \r.wb.data1[18]\ : DFN1E0 - port map(D => \data1_1[18]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_0_18); - - \r.xaddress_RNIJH2O2_1[0]\ : NOR2B - port map(A => dataout(13), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[237]\); - - \r.wb.addr_RNO_5[11]\ : OR2B - port map(A => \un1_m0_2[87]\, B => addr_1_sqmuxa_2, Y => - N_284); - - \r.hit_RNIUCU42\ : OR3B - port map(A => \dstate[4]\, B => un1_m0_2_0(35), C => hit, Y - => N_3752); - - \dctrl.un19_eholdn_3_0_a2_0_a2\ : NOR2 - port map(A => N_537, B => N_490, Y => un19_eholdn_3); - - \r.wb.addr_RNO_4[17]\ : MX2 - port map(A => \paddress[17]\, B => \addr[17]\, S => N_484_0, - Y => N_553); - - \r.holdn_RNIPU251_0\ : OR2A - port map(A => N_534, B => maddress(3), Y => N_3662); - - \r.wb.data1[6]\ : DFN1E0 - port map(D => \data1_1[6]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data(6)); - - \r.paddress[16]\ : DFN1E1 - port map(D => data_RNIKU1T4(16), CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress_0[16]\); - - \r.xaddress_RNIJH2O2_8[0]\ : NOR2B - port map(A => dataout(1), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[225]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_9\ : NOR3A - port map(A => vaddr_1_sqmuxa_0_a2_4_m1_e_2, B => eaddress_2, - C => eaddress_24, Y => vaddr_1_sqmuxa_0_a2_4_m1_e_9); - - \r.wb.addr_RNO_2[18]\ : AOI1B - port map(A => N_3841, B => N_2165_0, C => N_189, Y => - \addr_1_1_iv_0_0[18]\); - - \r.stpend_RNITG0D5\ : NOR2A - port map(A => read_1, B => burst_0_sqmuxa_2, Y => - \un1_dci_5[0]\); - - \r.wb.addr_RNO_0[28]\ : OA1 - port map(A => \data[28]\, B => LVL_RNIT69H911(0), C => - addr_1_sqmuxa_2_0, Y => \addr_1_1_iv_0_a3_1_0[28]\); - - \r.dstate_i_RNIS0039J[8]\ : OR2B - port map(A => \dstate_i_RNII68N892_0[8]\, B => N_3246, Y - => N_3248); - - \r.wb.addr_RNO_1[6]\ : NOR3C - port map(A => N_3733, B => N_3628, C => N_3732, Y => - \addr_1_1_iv_0_1[6]\); - - \r.dstate_RNO_0[5]\ : NOR3C - port map(A => \dstate_ns_0_7_i[3]\, B => \dstate_ns_0_1[3]\, - C => \dstate_RNO_4[5]\, Y => \dstate_ns_0_6[3]\); - - \r.dstate_RNIS3GB3_0[6]\ : OR2A - port map(A => \dstate[6]\, B => N_506, Y => N_3707); - - \r.dstate_i_2_RNISK8N1_0[8]\ : OR2B - port map(A => dataout(35), B => rdatasel_3_sqmuxa, Y => - \dcramo_m[415]\); - - \r.wb.lock_RNO_0\ : NOR3C - port map(A => N_86, B => stpend_0_sqmuxa, C => - \dstate_RNI5GFM4[5]\, Y => lock_2_sqmuxa); - - \r.dstate_tr22_15_a2_2_0_i_o2\ : OR2B - port map(A => size_1_d0, B => size_0_0, Y => N_507); - - \r.dstate_i_RNIHNLHK92[8]\ : OR2A - port map(A => edata2_0_iv(14), B => - \dstate_i_RNII68N892_0[8]\, Y => \dci_m[86]\); - - \r.dstate_i_2_RNIRB942[8]\ : OR2B - port map(A => un1_m0_2_62, B => miscdata_4_sqmuxa, Y => - \mmudco_m[63]\); - - \r.dstate_RNO_6[4]\ : OR3 - port map(A => dstate_tr16_13_0_0_a2_0, B => N_3499, C => - N_3514, Y => \dstate_RNO_6[4]\); - - \r.dstate_0_RNIIC256_4[7]\ : OR2B - port map(A => dataout(13), B => rdatav_0_6_sqmuxa_0, Y => - \dcramo_m_0[237]\); - - \r.wb.addr_RNO_1[3]\ : AOI1B - port map(A => \dstate_RNIP22L4[7]\, B => N_675, C => N_294, - Y => \addr_1_1_iv_0_0[3]\); - - \r.mmctrl1.pso\ : DFN1 - port map(D => pso_RNO, CLK => lclk_c, Q => pso); - - \r.dstate_RNIGRE8D[7]\ : OR2B - port map(A => \dstate[7]\, B => hrdata_1, Y => mcdo_m_0_5); - - \r.xaddress_RNIV3V9992[22]\ : OR2B - port map(A => \addr[22]\, B => \N_330\, Y => N_3864); - - \r.dstate_RNIHILB6_4[7]\ : OR2B - port map(A => dataout(20), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[244]\); - - \r.wb.addr_RNO_1[17]\ : OR2B - port map(A => maddress(17), B => addr_2_sqmuxa_0, Y => - N_3640); - - \dctrl.twrite_14_iv_0_a2_a0\ : AND2 - port map(A => un1_addout_13_i, B => twrite_14_iv_0_a2_a0_4, - Y => twrite_14_iv_0_a2_a0); - - \r.wb.addr[1]\ : DFN1 - port map(D => \addr_1[1]\, CLK => lclk_c, Q => \address[1]\); - - \r.dstate_i_2_RNI3KVJ1_2[8]\ : NOR2A - port map(A => N_3253_i, B => N_526, Y => - rdatasel_1_sqmuxa_1_0); - - \dctrl.v.wb.addr_1_1_iv_0_a2_2[31]\ : NAND2 - port map(A => N_514, B => \address[31]\, Y => N_3715); - - \r.mmctrl1.ctx_RNIIRMN[6]\ : MX2 - port map(A => \ctx[6]\, B => maddress(6), S => ctx_1_sqmuxa, - Y => N_2669); - - \r.dstate_0_RNI2DT77[2]\ : AOI1B - port map(A => diagdata_23, B => \dstate_0[2]\, C => - \dcramo_m_0[247]\, Y => \rdatav_0_1_0_iv_3[23]\); - - \r.wb.addr_RNO[17]\ : AO1B - port map(A => un1_m0_2_92, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[17]\, Y => \addr_1[17]\); - - \r.nomds_RNO\ : NOR2B - port map(A => rst, B => N_2596, Y => nomds_RNO); - - \r.flush_RNILOUG8\ : OR3B - port map(A => un157_m_en, B => holdn_1_5, C => flush_i, Y - => un157_m_en_m); - - \r.xaddress_RNO[1]\ : MX2 - port map(A => \addr[1]\, B => maddress(1), S => N_486_0, Y - => N_709); - - \r.holdn\ : DFN1 - port map(D => holdn_RNO_0, CLK => lclk_c, Q => \hold\); - - \r.dstate_RNI3ICLD[1]\ : OR2B - port map(A => \edata[21]\, B => ddatainv_0_6_sqmuxa, Y => - \edata_m_i[21]\); - - \r.vaddr[20]\ : DFN1E1 - port map(D => maddress(20), CLK => lclk_c, E => - vaddr_1_sqmuxa_0, Q => \vaddr[20]\); - - \r.xaddress_RNI54V9992[28]\ : OR2B - port map(A => \addr[28]\, B => \N_330\, Y => N_3846); - - \r.wb.addr_RNO_6[2]\ : OR2B - port map(A => \un1_m0_2[78]\, B => addr_1_sqmuxa_2, Y => - N_318); - - \r.dstate_i_2_RNISK8N1_20[8]\ : OR2B - port map(A => dataout_0(27), B => rdatasel_1_sqmuxa_1_0, Y - => \dcramo_m[127]\); - - \r.xaddress_RNIQF6M2_6[0]\ : OR2B - port map(A => dataout(23), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[247]\); - - \r.wb.data1_RNO_0[3]\ : NOR3A - port map(A => N_3331_0, B => req_0_sqmuxa_1_0, C => - \data2[3]\, Y => N_3360); - - \r.dstate_RNO_6[1]\ : OR3A - port map(A => dstate_tr22_15_0_a2_1, B => N_2994_6, C => - N_581_i, Y => N_3086_i); - - \r.wb.data2_RNO[23]\ : MX2 - port map(A => edata2_0_iv(23), B => hrdata_0_23, S => - \dstate_1[7]\, Y => \data2_1[23]\); - - \r.wb.addr_RNO[13]\ : AO1B - port map(A => N_694, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[13]\, Y => \addr_1[13]\); - - \r.mmctrl1.ctx[1]\ : DFN1 - port map(D => \ctx_0_0_RNIQIPQ[1]\, CLK => lclk_c, Q => - ctx(1)); - - \r.xaddress_RNIL5KB1_0[0]\ : OA1B - port map(A => N_3763, B => maddress(0), C => N_3782, Y => - \ddatainv_0_1_3_0[0]\); - - \r.wb.addr_RNO_5[24]\ : OR2B - port map(A => N_421_0, B => addr_1_sqmuxa_0, Y => N_3740); - - \r.valid_0_RNI6F4J[0]\ : OR3C - port map(A => hit, B => \valid_0[0]\, C => \dstate_i_0[8]\, - Y => N_345); - - \r.dstate_i_0_RNIEGV07[8]\ : OR2 - port map(A => \dstate_i_0[8]\, B => un1_eholdn_2, Y => - burst_2_sqmuxa_2); - - \r.cache_RNO_0\ : NOR2 - port map(A => \e_0\, B => N_587, Y => N_3674); - - \dctrl.twrite_14_iv_0_a2_a0_RNO_0\ : NOR3A - port map(A => twrite_14_iv_0_a2_a0_1, B => me_nullify2_1_2, - C => nullify2_0_sqmuxa, Y => twrite_14_iv_0_a2_a0_3); - - \r.xaddress_RNI4CRK4[7]\ : MX2C - port map(A => maddress(7), B => \addr[7]\, S => - un1_taddr_1_sqmuxa, Y => N_2234); - - \r.wb.data2[26]\ : DFN1E1 - port map(D => \data2_1[26]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[26]\); - - \r.dstate_1[7]\ : DFN1 - port map(D => \dstate_nss[1]\, CLK => lclk_c, Q => - \dstate_1[7]\); - - \r.cctrl.ics_RNO_2[1]\ : OAI1 - port map(A => \N_523\, B => maddress_0_0, C => rst, Y => - \ics_0_i_0[1]\); - - \r.vaddr[4]\ : DFN1E1 - port map(D => maddress(4), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[4]\); - - \r.mmctrl1.ctx_RNI5HIP[3]\ : MX2 - port map(A => \ctx[3]\, B => maddress_0_2, S => - ctx_1_sqmuxa, Y => N_2666); - - \r.wb.data2_RNO[0]\ : MX2A - port map(A => edata2_0_iv(0), B => hrdata_0_0, S => - \dstate_1[7]\, Y => \data2_1[0]\); - - \r.wb.addr_RNO_2[17]\ : AOI1B - port map(A => N_2165_0, B => N_553, C => N_3722, Y => - \addr_1_1_iv_0_0[17]\); - - \r.dstate_i_2_RNISK8N1_16[8]\ : OR2B - port map(A => dataout_0(3), B => rdatasel_1_sqmuxa_1, Y => - N_3401); - - \r.wb.data1_RNO_0[23]\ : MX2C - port map(A => edata2_0_iv(23), B => \data2[23]\, S => - N_3331_0, Y => N_2121); - - \r.wb.addr_RNO_0[27]\ : AOI1B - port map(A => data_1_3_i_a3_6_2, B => LVL_RNIT69H911(0), C - => addr_1_sqmuxa_2_0, Y => \addr_1_1_iv_0_a3_2_0[27]\); - - \r.mmctrl1.ctxp_RNIUPJ12[22]\ : OR2B - port map(A => \ctxp[22]\, B => N_3344_i_0_0, Y => - \ctxp_m[22]\); - - \r.valid_0_RNIR2NB[3]\ : NOR2B - port map(A => \valid_0[3]\, B => hit, Y => - \vmask_0_1_2_o3_0_a2_0[3]\); - - \r.flush2\ : DFN1 - port map(D => lrr_1_sqmuxa, CLK => lclk_c, Q => flush2); - - \r.dstate_tr22_15_a2_6_i_o2_1\ : NOR2B - port map(A => asi(3), B => asi(1), Y => N_549); - - \r.wb.data2_RNI0RRU1[7]\ : NOR2B - port map(A => N_3314, B => \dcramo_m[415]\, Y => - \rdatav_0_1_1_iv_0_0[7]\); - - \r.dstate_tr8_1_8_0_a2_0_0\ : OR2A - port map(A => asi(0), B => asi(4), Y => - dstate_tr8_1_8_0_a2_0); - - \r.dstate_i_2_RNITVLGB92[8]\ : OR2A - port map(A => N_3745, B => N_511, Y => - \dstate_i_2_RNITVLGB92[8]\); - - \r.xaddress_RNI4PQR692[3]\ : OR3B - port map(A => flush_0_sqmuxa_0_o3_i_o2_5, B => - flush_0_sqmuxa_0_o3_i_o2_4, C => nullify, Y => \N_523\); - - \r.wb.data1_RNO[13]\ : MX2A - port map(A => N_2111, B => maddress(13), S => - req_0_sqmuxa_1_0, Y => \data1_1[13]\); - - \r.read_RNIM7KJ8\ : OR2B - port map(A => \N_425_0\, B => hrdata_24, Y => - \mcdo_m_i[29]\); - - \v.mmctrl1.e_0_sqmuxa_RNIQKNL\ : NOR2B - port map(A => rst, B => N_2676, Y => e_0_sqmuxa_RNIQKNL); - - \r.wb.data1[23]\ : DFN1E0 - port map(D => \data1_1[23]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_0_23); - - \r.wb.addr_RNO_4[13]\ : MX2 - port map(A => \paddress[13]\, B => \addr[13]\, S => N_484_0, - Y => N_677); - - \r.dstate_RNI1JGE7_1[2]\ : AOI1B - port map(A => diagdata_25, B => \dstate[2]\, C => - \dcramo_m_0[249]\, Y => \rdatav_0_1_0_iv_3[25]\); - - \r.dstate_i_2_RNISK8N1_2[8]\ : OR2B - port map(A => dataout(31), B => rdatasel_3_sqmuxa, Y => - N_3400); - - \v.wb.addr_0_sqmuxa_2_RNI88Q9P92\ : NOR3C - port map(A => data2_0_sqmuxa, B => burst_1_sqmuxa_1, C => - burst_0_sqmuxa_3, Y => burst_1_sqmuxa_3); - - \r.read_RNI76N8R\ : OR3 - port map(A => \mcdo_m[10]\, B => \edata_m_1[2]\, C => - \ddatainv_0_1_1_iv_0[10]\, Y => read_RNI76N8R); - - \r.wb.data2_RNO[7]\ : MX2A - port map(A => edata2_0_iv(7), B => hrdata_0_7, S => - \dstate[7]\, Y => \data2_1[7]\); - - \r.xaddress_RNI8MTIN[1]\ : AOI1B - port map(A => \edata[0]\, B => ddatainv_0_0_sqmuxa, C => - \edata_m_0_i[8]\, Y => \ddatainv_0_1_0_iv_1[24]\); - - \r.dstate_RNIADAQA[1]\ : NOR2B - port map(A => \edata[3]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[3]\); - - \r.dstate_2_RNI43L1M[7]\ : OR3C - port map(A => \rdatav_0_1_1_iv_3[11]\, B => - \dcramo_m_0[235]\, C => \mcdo_m_0[11]\, Y => data_0_11); - - \r.flush_0_1_RNIGKU5992\ : OR2B - port map(A => maddress(29), B => \N_329\, Y => N_259); - - \r.xaddress_RNIIOTFII[27]\ : AO1 - port map(A => maddress(27), B => \N_329\, C => N_3895, Y - => newtag_1_0_9); - - \r.mmctrl1.ctx_RNIFGBR[2]\ : NOR2B - port map(A => rst, B => N_2665, Y => \ctx_RNIFGBR[2]\); - - \r.mmctrl1.ctxp[0]\ : DFN1E1 - port map(D => maddress(2), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[0]\); - - \r.wb.data2_RNI1RN44[25]\ : NOR3C - port map(A => \dcramo_m[121]\, B => \data2_m[25]\, C => - \mmudco_m[68]\, Y => \rdatav_0_1_0_iv_1[25]\); - - \r.dstate_RNO_1[0]\ : OR3C - port map(A => N_3811, B => \dcs[0]\, C => N_162, Y => - N_3556); - - \un1_r.faddr_I_8\ : NOR2B - port map(A => \faddr[1]\, B => \faddr[0]\, Y => N_20); - - \r.wb.addr_RNO_3[16]\ : OR2B - port map(A => \address[16]\, B => N_514, Y => \addr_m[16]\); - - \r.holdn_RNO_14\ : OR3B - port map(A => \dcs[0]\, B => N_162, C => \req\, Y => N_3605); - - \r.dstate_i_2_RNI3KVJ1_1[8]\ : OR2 - port map(A => un19_eholdn, B => N_526, Y => - rdatasel_4_sqmuxa); - - \r.cache_RNO_2\ : MX2 - port map(A => cache_1, B => cache_0, S => dstate_25, Y => - N_2481); - - \r.dstate_i_2_RNISK8N1_13[8]\ : OR2B - port map(A => dataout_0(8), B => rdatasel_1_sqmuxa_1, Y => - N_159); - - \r.read_RNIGVNMA\ : NOR2B - port map(A => \N_425\, B => hrdata_0_4, Y => \mcdo_m[4]\); - - \r.mmctrl1.ctx_0_0_RNI52QE[6]\ : XA1A - port map(A => \ctx_0[6]\, B => dataout(34), C => ctx_7_i, Y - => ctx_NE_3); - - \r.wb.data2_RNIJVL64[11]\ : NOR3C - port map(A => rdatav_0_1_sqmuxa, B => \data2_m[11]\, C => - rdatav_0_2_sqmuxa, Y => \rdatav_0_1_1_iv_1[11]\); - - \r.mmctrl1.ctxp[15]\ : DFN1E1 - port map(D => maddress(17), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[15]\); - - \r.dstate_i_RNI72JE[8]\ : OR2B - port map(A => edata_0_sqmuxa_1, B => N_3153, Y => N_3151); - - \r.mmctrl1.ctxp[12]\ : DFN1E1 - port map(D => maddress(14), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[12]\); - - \r.xaddress_RNISHIV8[9]\ : NOR3B - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - \addr[9]\, Y => N_3294); - - \r.wb.addr_RNO_0[1]\ : NOR3C - port map(A => \addr_1_1_iv_0[1]\, B => \addr_m[1]\, C => - \mmudco_m[3]\, Y => \addr_1_1_iv_2[1]\); - - \r.paddress[11]\ : DFN1E1 - port map(D => un1_m0_2_12, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[11]\); - - \r.mmctrl1.ctxp_RNI3CR2A[12]\ : AOI1B - port map(A => \ctxp[12]\, B => N_3344_i_0_0, C => - \rdatav_0_1_0_iv_3[14]\, Y => \rdatav_0_1_0_iv_4[14]\); - - \r.wb.addr_RNO_4[15]\ : OR2B - port map(A => \address[15]\, B => N_514, Y => \addr_m[15]\); - - \r.wb.addr_RNO_1[13]\ : OR2B - port map(A => maddress(13), B => addr_2_sqmuxa, Y => N_272); - - \r.dstate_RNIOUJBG[1]\ : AND2 - port map(A => \edata_m_i[18]\, B => \dcramo_m_i[242]\, Y - => \ddatainv_0_1_0_iv_0[18]\); - - \r.dstate_i_2_RNIIOTQ3[8]\ : OR2B - port map(A => rdatav_0_2_sqmuxa, B => rdatav_0_1_sqmuxa, Y - => \rdatav_0_1_6[3]\); - - \r.wb.addr[31]\ : DFN1 - port map(D => \addr_1[31]\, CLK => lclk_c, Q => - \address[31]\); - - \r.read_RNIR1CL_0\ : NOR2 - port map(A => N_3749, B => N_3748, Y => \N_425_0\); - - \r.dstate_RNIFOA94[2]\ : NOR2B - port map(A => rdatav_0_6_sqmuxa_3_0, B => - rdatav_0_6_sqmuxa_3_1, Y => rdatav_0_6_sqmuxa_3_2); - - \r.xaddress_RNIJH2O2_12[0]\ : NOR2B - port map(A => dataout(2), B => \xaddress_RNIQDEG2_0[0]\, Y - => \dcramo_m[226]\); - - \r.nomds_RNO_1\ : AO1B - port map(A => dstate_15_1, B => ready, C => N_3588, Y => - nomds_1); - - \r.mmctrl1.tlbdis\ : DFN1 - port map(D => tlbdis_RNO, CLK => lclk_c, Q => \tlbdis\); - - \r.dstate_i_2_RNISQM12[8]\ : OR2B - port map(A => un1_m0_2_66, B => miscdata_4_sqmuxa, Y => - \mmudco_m[67]\); - - \v.burst_2_sqmuxa_m8_0_a4_0_RNIOK01QJ\ : AOI1 - port map(A => burst_1_sqmuxa_3, B => burst_1_sqmuxa, C => - grant, Y => burst_0_sqmuxa_5); - - \r.stpend\ : DFN1 - port map(D => stpend_RNO, CLK => lclk_c, Q => stpend); - - \r.wb.data2[5]\ : DFN1E1 - port map(D => N_3348, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[5]\); - - \r.wb.data1_RNO[8]\ : MX2 - port map(A => N_3260, B => maddress(8), S => req_0_sqmuxa_1, - Y => N_8); - - \r.stpend_RNI6P41NG3\ : OR3B - port map(A => vaddr_1_sqmuxa_0_a2_a0_0, B => fault_pro, C - => accexc_6, Y => \stpend_RNI6P41NG3\); - - \dctrl.v.burst_3_m_1\ : NOR3A - port map(A => read_0, B => maddress(2), C => N_507, Y => - burst_3_m_1); - - \r.wb.addr_RNO_4[8]\ : MX2 - port map(A => \paddress_0[8]\, B => \addr[8]\, S => N_484, - Y => \paddress[8]\); - - \r.dstate_RNI8KDD[6]\ : OR2 - port map(A => \dstate[6]\, B => \dstate[4]\, Y => N_487); - - \r.dstate_0_RNIG0R21_1[2]\ : NAND2 - port map(A => \dstate_0[2]\, B => diagdata_4, Y => - \ico_m[138]\); - - \r.flush_RNI2N929\ : NOR3A - port map(A => N_3319, B => un1_taddr_1_sqmuxa, C => - maddress(9), Y => N_3293); - - \r.dstate_tr22_15_o2_7_i_o2\ : OR2A - port map(A => asi(1), B => asi(0), Y => N_505); - - \r.xaddress_RNIJI2O22[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[31]\, B => - \mcdo_m_i[31]\, C => \ddatainv_0_1_0_iv_1[31]\, Y => - xaddress_RNIJI2O22(1)); - - \r.nomds_RNIC8EMD92\ : NOR2 - port map(A => N_511, B => N_503, Y => N_547); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.wb.data2_RNI4VN44[30]\ : AOI1B - port map(A => un1_m0_2_72, B => miscdata_4_sqmuxa, C => - \rdatav_0_1_0_iv_0[30]\, Y => \rdatav_0_1_0_iv_1[30]\); - - \r.ready_RNIVSAH\ : AOI1B - port map(A => ready_0, B => \dstate[5]\, C => stpend, Y => - \dstate_ns_i_a4_i_o2_11_0[0]\); - - \r.xaddress_RNI271B6[4]\ : NOR2A - port map(A => \dstate_RNIR2CO3[4]\, B => \vmask_0_5[2]\, Y - => \vmask_0_6[2]\); - - \r.wb.data2[19]\ : DFN1E1 - port map(D => \data2_1[19]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[19]\); - - \r.vaddr_RNI3IHC[11]\ : MX2 - port map(A => maddress(11), B => \vaddr[11]\, S => - \dstate_i_2[8]\, Y => \un1_m0_2[87]\); - - \r.dstate_RNI1JGE7_0[2]\ : AOI1B - port map(A => diagdata_27, B => \dstate[2]\, C => - \dcramo_m_0[251]\, Y => \rdatav_0_1_0_iv_3[27]\); - - \r.mmctrl1.ctxp[26]\ : DFN1E1 - port map(D => maddress(28), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[26]\); - - \r.xaddress_RNIVN7I[1]\ : OR2B - port map(A => \addr[1]\, B => N_3782, Y => N_3625); - - \r.mmctrl1wr_RNICO68\ : NOR2B - port map(A => mmctrl1wr, B => \addr[9]\, Y => - ctx_1_sqmuxa_0_a2_0); - - \r.wb.read_RNIVLJ2D\ : NOR2A - port map(A => grant, B => \read_2\, Y => N_56); - - \r.wb.addr_RNO_1[15]\ : NOR3C - port map(A => \dci_m[23]\, B => \addr_1_1_iv_0[15]\, C => - \addr_m[15]\, Y => \addr_1_1_iv_2[15]\); - - \r.req_RNO_0\ : AOI1B - port map(A => req_0_sqmuxa_3_1, B => N_547, C => req_1_1, Y - => req_1_2); - - \r.xaddress_RNI1CIE2_0[0]\ : OR2B - port map(A => \ddatainv_0_1_3_0[0]\, B => N_574, Y => - \xaddress_RNI1CIE2_0[0]\); - - \r.vaddr_RNI8IHC[15]\ : MX2 - port map(A => maddress(15), B => \vaddr[15]\, S => - \dstate_i_1[8]\, Y => \data[15]\); - - \r.dstate_0_RNI1JGE7_2[2]\ : AOI1B - port map(A => diagdata_26, B => \dstate_0[2]\, C => - \dcramo_m_0[250]\, Y => \rdatav_0_1_0_iv_3[26]\); - - \r.xaddress[4]\ : DFN1 - port map(D => N_715, CLK => lclk_c, Q => \addr[4]\); - - \r.wb.data2_RNO[6]\ : MX2A - port map(A => edata2_0_iv(6), B => hrdata_1, S => - \dstate_1[7]\, Y => \data2_1[6]\); - - \r.wb.data1[11]\ : DFN1E0 - port map(D => \data1_1[11]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data(11)); - - \r.paddress[26]\ : DFN1E1 - port map(D => N_192, CLK => lclk_c, E => paddress_1_sqmuxa, - Q => \paddress_0[26]\); - - \r.trans_op\ : DFN1 - port map(D => trans_op_RNO_1, CLK => lclk_c, Q => - \trans_op_0\); - - \r.faddr_RNI0MQ381[3]\ : NOR3 - port map(A => N_3288, B => N_3287, C => \address_i_1[6]\, Y - => N_24); - - \r.dstate_RNIET0O2[5]\ : AO1B - port map(A => un157_m_en, B => N_566, C => \dstate[5]\, Y - => \dstate_RNIET0O2[5]\); - - \r.holdn_RNO_8\ : OR2B - port map(A => e_0_0_RNI8APPC92, B => N_485, Y => N_3613); - - \r.holdn_RNO_28\ : NOR3A - port map(A => asi(1), B => \e_0\, C => read_0, Y => - holdns_iv_0_a2_2_1); - - \r.wb.addr_RNO_2[13]\ : AOI1B - port map(A => N_2165_0, B => N_677, C => N_273, Y => - \addr_1_1_iv_0_0[13]\); - - \r.burst_RNO_1\ : NOR3 - port map(A => burst_1_iv_2, B => burst_RNO_3, C => - burst_0_sqmuxa_5, Y => burst_1_N_12); - - \r.wb.addr_RNO_0[23]\ : NOR3C - port map(A => N_216, B => \addr_1_1_iv_0_0[23]\, C => - N_3889, Y => \addr_1_1_iv_0_2[23]\); - - \r.mmctrl1.e_0_0_RNI0T0A3\ : AOI1 - port map(A => \dstate_ns_0_0_o2_0[1]\, B => N_3746, C => - \e_0\, Y => \dstate_ns_0_0_a2_0[1]\); - - \dctrl.0.genmux.un6_validrawv_2\ : MX2 - port map(A => dataout_0(2), B => dataout_0(6), S => - maddress(4), Y => N_2013); - - \r.xaddress_RNI5DM3K[0]\ : AND2 - port map(A => \edata_m_i[31]\, B => \dcramo_m_i[255]\, Y - => \ddatainv_0_1_0_iv_0[31]\); - - \r.wb.addr_RNO_0[3]\ : NOR3C - port map(A => \addr_1_1_iv_0_0[3]\, B => N_295, C => - N_293_0, Y => \addr_1_1_iv_0_2[3]\); - - \r.paddress[15]\ : DFN1E1 - port map(D => N_351, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[15]\); - - \r.mmctrl1.nf_RNIOHLFF\ : NOR3C - port map(A => N_176, B => N_175, C => N_174, Y => - mexc_1_m_0_1); - - \r.mmctrl1.ctx_RNIPUJ8[7]\ : XNOR2 - port map(A => dataout(35), B => \ctx[7]\, Y => ctx_7_i); - - \r.dstate_RNI4T29H[1]\ : NAND2 - port map(A => ddatainv_0_6_sqmuxa, B => \edata[27]\, Y => - \edata_m_i[27]\); - - \r.burst_RNO\ : NOR3 - port map(A => burst_1_m8_i_0, B => burst_1_N_12, C => - burst_1_N_9, Y => burst_RNO); - - \un1_v.holdn_3_sqmuxa_0_0_o2\ : OR2B - port map(A => N_3743, B => N_3742, Y => N_492); - - \r.holdn_RNIJ4401\ : OR2B - port map(A => maddress_0_0, B => N_3785, Y => N_3598); - - \r.flush_RNITKH06\ : NOR2 - port map(A => flush_i, B => \dstate_RNIR2CO3[4]\, Y => - flush_RNITKH06); - - \r.dstate_i_0_RNIRK89F[8]\ : OR2A - port map(A => addr_0_sqmuxa_1, B => dstate_19, Y => N_514); - - \r.dstate_RNIV0G5E[1]\ : OR2B - port map(A => \edata[10]\, B => ddatainv_0_4_sqmuxa, Y => - \edata_m_0_i[10]\); - - \r.dstate_RNI1EIBG[1]\ : AOI1B - port map(A => \edata[16]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[240]\, Y => \ddatainv_0_1_0_iv_0[16]\); - - \r.valid_0_RNO[7]\ : OR3C - port map(A => N_3285, B => N_3283, C => N_3286, Y => - \valid_0_1[7]\); - - \r.xaddress_RNO[10]\ : MX2 - port map(A => \addr[10]\, B => maddress(10), S => N_486_0, - Y => N_718); - - \r.dstate_i_0_RNI16A62[8]\ : OR2A - port map(A => N_485, B => \dstate_i_0[8]\, Y => N_3331_0); - - \r.dstate_2_RNIRGNAI[7]\ : OR2B - port map(A => \dstate_2[7]\, B => N_78_0, Y => - \mcdo_m_0[25]\); - - \r.wb.lock_RNO_5\ : OR2B - port map(A => \lock_0\, B => \req\, Y => lock_1_iv_0_a2_0); - - \r.dstate_i_2_RNIH6U12[8]\ : OR2B - port map(A => un1_m0_2_42, B => miscdata_3_sqmuxa, Y => - N_3392); - - \un1_v.cctrlwr19_2_0_2072_0\ : OR2 - port map(A => N_3779, B => N_494, Y => cctrlwr19_2_0_2072_0); - - \r.dstate_0_RNITN6TH[7]\ : OR2B - port map(A => \dstate_0[7]\, B => hrdata_0_24, Y => - \mcdo_m_0[24]\); - - \r.wb.data1[25]\ : DFN1E0 - port map(D => \data1_1[25]\, CLK => lclk_c, E => - data1_0_sqmuxa, Q => data_1_13); - - \r.wb.data2_RNO[29]\ : MX2 - port map(A => edata2_iv_i_0(29), B => hrdata_24, S => - \dstate_1[7]\, Y => \data2_1[29]\); - - \r.dstate_i_RNI0I51[8]\ : NOR2A - port map(A => \dstate_i[8]\, B => \dstate_2[7]\, Y => - N_3153); - - \r.wb.data2[1]\ : DFN1E1 - port map(D => \data2_1[1]\, CLK => lclk_c, E => - mexc_0_sqmuxa_0_0, Q => \data2[1]\); - - \r.wb.data2[4]\ : DFN1E1 - port map(D => \data2_1[4]\, CLK => lclk_c, E => - \dstate_RNI5ED76[1]\, Q => \data2[4]\); - - \r.wb.addr_RNO_0[5]\ : NOR3C - port map(A => \addr_1_1_iv_0_0[5]\, B => N_290, C => N_288, - Y => \addr_1_1_iv_0_2[5]\); - - \r.wb.addr_RNO_2[15]\ : OR2B - port map(A => maddress(15), B => addr_2_sqmuxa_0, Y => - \dci_m[23]\); - - \r.vaddr[28]\ : DFN1E1 - port map(D => maddress(28), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[28]\); - - \r.wb.addr_RNO_0[25]\ : AOI1B - port map(A => data_1_3_i_a3_6_0, B => LVL_RNIT69H911(0), C - => addr_1_sqmuxa_2_0, Y => \mmudco_m_0[101]\); - - \r.valid_0_RNIV2PE2[6]\ : AOI1 - port map(A => hit, B => \valid_0[6]\, C => N_3244_i_0, Y - => N_2026); - - \r.dstate_RNI65L74[7]\ : NOR2B - port map(A => mexc, B => N_84, Y => mexc_1_m_0_a2_4_0); - - \r.wb.data1_RNO_0[5]\ : NOR3A - port map(A => N_3331_0, B => req_0_sqmuxa_1_0, C => - \data2[5]\, Y => N_3364); - - \r.mmctrl1.ctxp_RNI2QJ12[26]\ : OR2B - port map(A => \ctxp[26]\, B => N_3344_i_0_0, Y => - \ctxp_m[26]\); - - \r.flush_RNI0NBH\ : MX2 - port map(A => flush, B => flush_0, S => asi(1), Y => N_136); - - \dctrl.un18_m_en\ : NOR3A - port map(A => lock, B => read_0, C => un17_m_en, Y => - un18_m_en); - - \r.cctrl.dcs[1]\ : DFN1 - port map(D => N_51, CLK => lclk_c, Q => \dcs[1]\); - - \r.dstate_RNIEGRAG[1]\ : AOI1B - port map(A => \edata[17]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[241]\, Y => \ddatainv_0_1_0_iv_0[17]\); - - \r.dstate_RNI2NRIB[1]\ : OAI1 - port map(A => ddatainv_0_1_sqmuxa, B => ddatainv_0_4_sqmuxa, - C => \edata[5]\, Y => \ddatainv_0_1_0_iv_1[21]\); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0_RNIMMIH9\ : OR3 - port map(A => cctrlwr19_2_0_2072_0, B => N_3607, C => - N_3610, Y => dcs_1_i_s_0_o2_0_RNIMMIH9); - - \r.wb.addr_RNO_2[28]\ : OR2B - port map(A => maddress(28), B => addr_2_sqmuxa_0, Y => - N_3888); - - \r.read_RNII33M8\ : NOR2B - port map(A => \N_425\, B => hrdata_0_8, Y => \mcdo_m[8]\); - - \r.read_RNI3RIPJ\ : OR2B - port map(A => \N_425_0\, B => N_262_0, Y => \mcdo_m_i[20]\); - - \r.wb.addr_RNO_3[12]\ : AOI1B - port map(A => N_2165_0, B => N_676, C => N_278, Y => - \addr_1_1_iv_0_0[12]\); - - \r.dstate_RNIMRB5A[1]\ : NOR2B - port map(A => \edata[6]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[6]\); - - \r.dstate_RNO_1[6]\ : OAI1 - port map(A => \dstate_ns_0_0_a2_0[2]\, B => - \dstate_ns_0_0_a2_0_1[2]\, C => N_3781, Y => - \dstate_RNO_1[6]\); - - \r.dstate_i_2_RNIRUH12[8]\ : OR2B - port map(A => un1_m0_2_43, B => miscdata_3_sqmuxa, Y => - \mmudco_m[44]\); - - \r.cctrl.dcs_RNID9M04[1]\ : AOI1B - port map(A => \dcs[1]\, B => rdatav_0_0_sqmuxa, C => N_3399, - Y => \rdatav_0_1_1_iv_i_a2_2[3]\); - - \r.dstate_tr22_15_a2_1_0\ : OR2A - port map(A => enaddr, B => nullify, Y => N_581_i); - - \r.dstate_RNIVP6I3_2[6]\ : NOR2A - port map(A => N_487, B => N_506, Y => paddress_1_sqmuxa); - - \r.flush_RNIM7304\ : NOR2B - port map(A => flush_m, B => \rdatav_0_1_0_iv_0[14]\, Y => - \rdatav_0_1_0_iv_1[14]\); - - \r.xaddress_RNI2O5H[2]\ : AOI1B - port map(A => \addr[2]\, B => N_3747, C => N_3443_i, Y => - N_3793); - - \r.wb.data1_RNO[26]\ : MX2A - port map(A => N_2124, B => maddress(26), S => - req_0_sqmuxa_1, Y => \data1_1[26]\); - - \r.stpend_RNO_1\ : OR2A - port map(A => N_485, B => holdn_1_5, Y => stpend_1_0); - - \r.valid_0_RNO[3]\ : AO1B - port map(A => dataout_0(3), B => N_88, C => N_3380, Y => - \valid_0_1[3]\); - - \r.cctrl.dcs_RNILMPD[1]\ : OR2 - port map(A => \dcs[1]\, B => \dcs[0]\, Y => \cache\); - - \r.mmctrl1.e_0_0_RNIIAUC4Q1\ : AO1B - port map(A => dstate_tr22_15_a2_2_m8_i_a5_1_1, B => - dstate_tr22_15_a2_2_m1_e, C => - dstate_tr22_15_a2_2_m8_i_0_0, Y => e_0_0_RNIIAUC4Q1); - - \r.vaddr[26]\ : DFN1E1 - port map(D => maddress(26), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[26]\); - - \r.wb.data1_RNO[19]\ : MX2A - port map(A => N_2117, B => maddress(19), S => - req_0_sqmuxa_1_0, Y => \data1_1[19]\); - - \r.dstate_RNI1JGE7_4[2]\ : AOI1B - port map(A => dataout(6), B => rdatav_0_6_sqmuxa_0, C => - \ico_m[140]\, Y => \rdatav_0_1_1_iv_6[6]\); - - \r.wb.lock_RNO_1\ : OR2B - port map(A => \req\, B => N_56, Y => N_86); - - \r.stpend_RNIJ1FL692\ : OR3A - port map(A => stpend, B => read_1, C => nullify, Y => - N_3511); - - \r.xaddress_RNIJH2O2_2[0]\ : NOR2B - port map(A => dataout(12), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[236]\); - - \r.dstate_RNI5VRP7[7]\ : OR2B - port map(A => mexc_1_m_0_a2_4_0, B => mexc_0_sqmuxa_1, Y - => N_176); - - \r.vaddr[29]\ : DFN1E1 - port map(D => maddress(29), CLK => lclk_c, E => - vaddr_1_sqmuxa, Q => \vaddr[29]\); - - \r.mmctrl1.nf_RNO_0\ : MX2 - port map(A => \nf\, B => maddress_0_0, S => e_0_sqmuxa, Y - => N_2675); - - \r.mmctrl1.ctx[3]\ : DFN1 - port map(D => \ctx_RNIAM7T[3]\, CLK => lclk_c, Q => - \ctx[3]\); - - \r.xaddress[18]\ : DFN1E1 - port map(D => maddress(18), CLK => lclk_c, E => N_486, Q - => \addr[18]\); - - \r.wb.data2_RNI6VN44[31]\ : NOR3C - port map(A => \dcramo_m[127]\, B => \data2_m[31]\, C => - \mmudco_m[74]\, Y => \rdatav_0_1_0_iv_1[31]\); - - \r.dstate_RNIHILB6_11[7]\ : OR2B - port map(A => dataout(12), B => rdatav_0_6_sqmuxa, Y => - N_160); - - VCC_i : VCC - port map(Y => \VCC\); - - \dctrl.un19_eholdn_0_a2_0_a2_0_a2_0_a2\ : OR2A - port map(A => un19_eholdn_3, B => asi(2), Y => un19_eholdn); - - \r.xaddress_RNIQF6M2_0[0]\ : OR2B - port map(A => dataout_0(29), B => N_2088, Y => - \dcramo_m_i[253]\); - - \r.mmctrl1.ctx[5]\ : DFN1 - port map(D => \ctx_0_0_RNI91UO[5]\, CLK => lclk_c, Q => - \ctx[5]\); - - \r.dstate_tr16_10_0_i_o2_0_i_a2_0\ : NOR2A - port map(A => N_505, B => asi(4), Y => N_3572); - - \dctrl.v.wb.addr_1_1_iv_0_a2_1[10]\ : NAND2 - port map(A => N_514, B => \address[10]\, Y => N_3723); - - \r.mmctrl1.ctxp_RNITLJ12[14]\ : OR2B - port map(A => \ctxp[14]\, B => N_3344_i_0, Y => - \ctxp_m[14]\); - - \r.dstate_i_0_RNIU0NO[8]\ : OR2A - port map(A => un1_dci_12_0, B => \dstate_i_0[8]\, Y => - vaddr_1_sqmuxa_0_a2_0); - - \dctrl.vmaskraw_1_i_o2_i_a2_0_RNO[1]\ : NOR2A - port map(A => N_3443_i, B => \addr[3]\, Y => - \vmaskraw_1_i_o2_i_a2_0_0[1]\); - - \r.mmctrl1.e_RNI9F783\ : NOR2A - port map(A => un47_m_en, B => N_3331, Y => addr_2_sqmuxa_0); - - \r.flush_0_1_RNIBUA27S2\ : AO1B - port map(A => maddress(18), B => \N_329\, C => - \newtag_1_0[18]\, Y => flush_0_1_RNIBUA27S2); - - \r.faddr_RNO[2]\ : NOR3C - port map(A => rst, B => flush_0, C => I_9_1, Y => - \faddr_1[2]\); - - \r.xaddress_RNI18V9992[31]\ : OR2B - port map(A => \addr[31]\, B => \N_330\, Y => N_269); - - \r.wb.data1_RNO_0[20]\ : MX2C - port map(A => edata2_0_iv(20), B => \data2[20]\, S => - N_3331_0, Y => N_2118); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_0\ : NAND2 - port map(A => N_500_i, B => N_501, Y => N_502); - - \r.dstate_RNI6JA5A[1]\ : NOR2B - port map(A => \edata[4]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[4]\); - - \r.dstate_ns_i_a4_i_o2_5[0]\ : OR2A - port map(A => asi(3), B => asi(1), Y => N_490); - - \r.dstate_i_RNIP1BPN92[8]\ : NOR2A - port map(A => edata2_iv_i_0(25), B => - \dstate_i_RNII68N892_0[8]\, Y => dci_m_89); - - \r.valid_0_RNO_0[6]\ : MX2C - port map(A => dataout_0(6), B => \vmask_0_6[6]\, S => - twrite_14, Y => N_2366); - - \r.dstate_RNO_10[5]\ : OR3 - port map(A => N_2994_8, B => N_3002_9, C => N_2995_8, Y => - \dstate_ns_0_2_0_tz[3]\); - - \r.dstate_i_2_RNIUQM12[8]\ : OR2B - port map(A => un1_m0_2_68, B => miscdata_4_sqmuxa, Y => - \mmudco_m[69]\); - - \r.dstate_i_0_RNI6CL21[8]\ : NOR2 - port map(A => vaddr_1_sqmuxa_0_a2_0, B => un17_casaen_0_0, - Y => twrite_14_iv_0_a2_a1_0); - - \r.paddress[21]\ : DFN1E1 - port map(D => N_419, CLK => lclk_c, E => - paddress_1_sqmuxa_0, Q => \paddress[21]\); - - \r.hit_RNI17SC\ : NOR2B - port map(A => \dcs[0]\, B => hit, Y => N_58); - - \r.dstate_RNO[3]\ : NOR2B - port map(A => rst, B => \dstate_ns[5]\, Y => - \dstate_nss[5]\); - - \r.dstate_i_RNI0N99F92[8]\ : MX2A - port map(A => edata2_0_iv(2), B => \vmask_0_6[2]\, S => - \dstate_i_RNII68N892_0[8]\, Y => N_2381); - - \un1_v.cctrlwr19_2_0_o2_7\ : OR3C - port map(A => N_3770, B => N_3765, C => - cctrlwr19_2_0_o2_7_0, Y => N_576); - - \r.paddress[7]\ : DFN1E1 - port map(D => un1_m0_2_8, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress[7]\); - - \r.xaddress_RNILK99L1[1]\ : OR3C - port map(A => \ddatainv_0_1_0_iv_0[27]\, B => - \mcdo_m_i[27]\, C => \ddatainv_0_1_0_iv_1[27]\, Y => - xaddress_RNILK99L1(1)); - - \r.wb.addr_RNO_2[27]\ : OR2B - port map(A => maddress(27), B => addr_2_sqmuxa_0, Y => - N_250); - - \r.wb.addr_RNO[27]\ : AO1B - port map(A => \addr_1_1_iv_0_a3_2_0[27]\, B => N_2717, C - => \addr_1_1_iv_0_2[27]\, Y => \addr_1[27]\); - - \r.xaddress_RNIQF6M2_9[0]\ : OR2B - port map(A => dataout(17), B => \xaddress_RNI1CIE2_0[0]\, Y - => \dcramo_m_i[241]\); - - \r.wb.addr_RNO_3[11]\ : AOI1B - port map(A => \addr_1_1_iv_0_a3_0[11]\, B => - \dstate_RNIP22L4[7]\, C => N_284, Y => - \addr_1_1_iv_0_0[11]\); - - \r.wb.addr[6]\ : DFN1 - port map(D => \addr_1[6]\, CLK => lclk_c, Q => \address[6]\); - - \r.dstate_RNIC3QA81[1]\ : OR3 - port map(A => \edata_m[0]\, B => \dcramo_m[224]\, C => - \ddatainv_0_1_1_iv_1[0]\, Y => dstate_RNIC3QA81(1)); - - \r.mmctrl1.ctx_0_0_RNI2O8L[4]\ : MX2 - port map(A => \ctx_0[4]\, B => maddress(4), S => - ctx_1_sqmuxa, Y => N_2667); - - \r.dstate_0_RNIBQ8841[2]\ : OR3C - port map(A => \rdatav_0_1_0_iv_5[14]\, B => - \rdatav_0_1_0_iv_4[14]\, C => \mcdo_m_0[14]\, Y => - data_0_14); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_16\ : NOR2 - port map(A => eaddress_10, B => eaddress_25, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_16); - - \r.req_RNIDTDR692\ : NOR2A - port map(A => \req\, B => N_3511, Y => N_29); - - \r.cctrl.dfrz_RNI3VJJ7\ : NOR3C - port map(A => N_3392, B => N_3329, C => - \rdatav_0_1_1_iv_i_a2_1[5]\, Y => - \rdatav_0_1_1_iv_i_a2_3[5]\); - - \r.dstate_tr22_15_a2_2_m8_i_a5_0_0\ : AO1C - port map(A => N_459, B => dstate_tr22_15_a2_14_1_0, C => - dstate_tr22_15_a2_15_0, Y => - dstate_tr22_15_a2_2_m8_i_a5_0_0); - - \r.wb.data2_RNIU5E04[9]\ : AOI1B - port map(A => un1_m0_2_44, B => miscdata_3_sqmuxa, C => - \rdatav_0_1_0_iv_0[9]\, Y => \rdatav_0_1_0_iv_1[9]\); - - \r.xaddress_RNIOMT7A[1]\ : OR2B - port map(A => \edata[3]\, B => ddatainv_0_0_sqmuxa, Y => - \edata_m_4_i[3]\); - - \r.wb.addr_RNO[23]\ : AO1B - port map(A => un1_m0_2_98, B => addr_1_sqmuxa_2_0, C => - \addr_1_1_iv_0_2[23]\, Y => \addr_1[23]\); - - \r.vaddr_RNIAIHC[24]\ : MX2 - port map(A => maddress(24), B => \vaddr[24]\, S => - \dstate_i_1[8]\, Y => data(24)); - - \r.dstate[6]\ : DFN1 - port map(D => \dstate_nss[2]\, CLK => lclk_c, Q => - \dstate[6]\); - - \r.wb.addr_RNO[12]\ : AO1B - port map(A => \addr_1_1_iv_0_a3_2_0[12]\, B => N_2711_i_0, - C => \addr_1_1_iv_0_2[12]\, Y => \addr_1[12]\); - - \r.dstate_RNISDQ4R[1]\ : AO1 - port map(A => \edata[1]\, B => \size_RNIBHS22[0]\, C => - \mcdo_m[1]\, Y => \ddatainv_0_1_1_iv_1[1]\); - - \r.mmctrl1.ctxp_RNI713D7[9]\ : AOI1B - port map(A => \ctxp[9]\, B => N_3344_i_0_0, C => - \rdatav_0_1_1_iv_2[11]\, Y => \rdatav_0_1_1_iv_3[11]\); - - \r.wb.data2_RNI6EJ7[9]\ : OR2B - port map(A => \data2[9]\, B => rdatav_012, Y => - \data2_m[9]\); - - \r.dstate_RNIQSCNB[1]\ : MX2 - port map(A => maddress(9), B => edata2_0_iv(9), S => - edata_0_sqmuxa_i, Y => \edata[9]\); - - \r.dstate_2_RNIIH7OC[7]\ : OR2B - port map(A => \dstate_2[7]\, B => N_264_0, Y => mcdo_m_0_18); - - \r.xaddress[9]\ : DFN1E1 - port map(D => maddress(9), CLK => lclk_c, E => N_486, Q => - \addr[9]\); - - \r.wb.data1_RNO_0[31]\ : MX2C - port map(A => edata2_iv_i_0(31), B => \data2[31]\, S => - N_3331, Y => N_2129); - - \r.dstate_tr8_2_8_0_a2_1_a2_0\ : OR2 - port map(A => asi(4), B => asi(1), Y => - dstate_tr8_2_8_0_a2_1_a2_0); - - \r.read_RNIB23F8\ : NOR2B - port map(A => \N_425\, B => hrdata_0_9, Y => \mcdo_m[9]\); - - \r.wb.data2_RNIUDI7[1]\ : OR2B - port map(A => \data2[1]\, B => rdatav_012, Y => N_89); - - \r.mmctrl1.nf_RNI76UP3\ : OR2 - port map(A => \nf\, B => mexc_0_sqmuxa_1, Y => N_174); - - \r.dstate_RNIOIKBG[1]\ : AOI1B - port map(A => \edata[23]\, B => ddatainv_0_6_sqmuxa, C => - \dcramo_m_i[247]\, Y => \ddatainv_0_1_0_iv_0[23]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_3\ : NOR3B - port map(A => eaddress_4, B => eaddress_1, C => eaddress_8, - Y => vaddr_1_sqmuxa_0_a2_4_m1_e_3); - - \r.wb.addr_RNO_4[4]\ : MX2 - port map(A => \paddress[4]\, B => \addr[4]\, S => N_484, Y - => N_678); - - \r.holdn_RNO_6\ : OR3C - port map(A => ready, B => mexc_0_sqmuxa, C => N_3605, Y => - holdn_1_sqmuxa_3); - - \r.dstate_0_RNIP8ET5[7]\ : NOR2A - port map(A => rdatav_0_6_sqmuxa_3, B => \dstate_0[7]\, Y - => rdatav_0_6_sqmuxa_0); - - \r.cctrl.dfrz_RNIOGHR1\ : OR2B - port map(A => dfrz, B => rdatav_0_0_sqmuxa, Y => N_3329); - - \r.wb.addr_RNO[15]\ : AO1B - port map(A => \mmudco_m_0[91]\, B => N_2699_i_0, C => - \addr_1_1_iv_2[15]\, Y => \addr_1[15]\); - - \r.dstate_RNIEHR5G[1]\ : MX2 - port map(A => maddress(30), B => edata2_iv_i_0(30), S => - edata_0_sqmuxa_i, Y => \edata[30]\); - - \r.dstate_i_2_RNITQM12[8]\ : OR2B - port map(A => un1_m0_2_67, B => miscdata_4_sqmuxa, Y => - \mmudco_m[68]\); - - \r.mmctrl1.e_0_0\ : DFN1 - port map(D => e_0_sqmuxa_RNIQKNL, CLK => lclk_c, Q => \e_0\); - - \r.dstate_RNO[1]\ : AOI1B - port map(A => dstate_tr22_2, B => N_3564_i, C => rst, Y => - \dstate_nss[7]\); - - \r.dstate_RNIUQ9VC[1]\ : AO1 - port map(A => dataout(5), B => \xaddress_RNIQDEG2_0[0]\, C - => \edata_m[5]\, Y => \ddatainv_0_1_1_iv_0[5]\); - - \r.dstate_RNIOMT7A[1]\ : NOR2B - port map(A => \edata[3]\, B => ddatainv_0_2_sqmuxa, Y => - \edata_m_1[3]\); - - \r.read_RNIQM0I2\ : OR3A - port map(A => read, B => N_135, C => N_84, Y => N_179); - - \r.read_RNI6SUEH\ : OR2B - port map(A => \N_425\, B => hrdata_0_23, Y => - \mcdo_m_i[23]\); - - \r.dstate_RNICL8A6[7]\ : OR3B - port map(A => N_84, B => hit_1_iv_0_a2_0, C => flush_i, Y - => twrite_11_m); - - \r.dstate[7]\ : DFN1 - port map(D => \dstate_nss[1]\, CLK => lclk_c, Q => - \dstate[7]\); - - \r.paddress[25]\ : DFN1E1 - port map(D => N_190_0, CLK => lclk_c, E => - paddress_1_sqmuxa, Q => \paddress_0[25]\); - - \r.wb.addr_RNO_4[28]\ : OR2B - port map(A => \address[28]\, B => N_514, Y => N_214); - - \r.dstate_i_2_RNILAMC992[8]\ : AO1D - port map(A => cctrlwr13, B => mmudci_diag_op_1_0_a2_0, C - => N_3790, Y => vaddr_1_sqmuxa_0_0); - - \r.mmctrl1.ctx_0_0_RNIDSBP9[0]\ : NOR3C - port map(A => \rdatav_0_1_0_iv_2[0]\, B => - \rdatav_0_1_0_iv_1[0]\, C => \ctx_m[0]\, Y => - \rdatav_0_1_0_iv_4[0]\); - - \r.dstate_RNID2ELB1[4]\ : NOR3C - port map(A => \dstate_ns_i_a4_i_4[0]\, B => N_3683_i, C => - N_3815, Y => \dstate_ns_i_a4_i_6[0]\); - - \r.dstate_i_2_RNIRB2T1[8]\ : OR2B - port map(A => flush, B => rdatav_0_0_sqmuxa, Y => N_205); - - \r.size_RNIGFGD1[0]\ : OR2B - port map(A => N_3600, B => N_3599, Y => ddatainv_0_4_sqmuxa); - - \r.xaddress[31]\ : DFN1E1 - port map(D => maddress(31), CLK => lclk_c, E => N_486, Q - => \addr[31]\); - - \r.flush_RNIA3GPL\ : NOR2 - port map(A => eaddress_6, B => N_195, Y => N_3288); - - \r.dstate_1_RNIHNPT81[7]\ : OR3C - port map(A => N_3811, B => N_522, C => N_563, Y => N_3679); - - \r.dstate_RNI75ESQ1[7]\ : OA1A - port map(A => twrite_14_iv_0_o2_a1_3, B => - nullify2_0_sqmuxa, C => twrite_11_m, Y => - twrite_14_iv_0_o2_0_0); - - \r.ready_RNO_2\ : AOI1B - port map(A => ready_0_sqmuxa_0_a2_1_0, B => - \dstate_i_RNIF4S5B92[8]\, C => N_3697, Y => - ready_0_sqmuxa_0_2); - - \r.wb.data1[20]\ : DFN1E0 - port map(D => \data1_1[20]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_8); - - \r.dstate_RNIICAT5[2]\ : NOR2A - port map(A => rdatav_0_6_sqmuxa_3_2, B => rdatasel_3_sqmuxa, - Y => rdatav_0_6_sqmuxa_3); - - \r.wb.data2_RNO[1]\ : MX2A - port map(A => edata2_0_iv(1), B => hrdata_0_1, S => - \dstate_1[7]\, Y => \data2_1[1]\); - - \r.flush2_RNI9VSV2\ : NOR3 - port map(A => \un1_p0_2_0[498]\, B => flush2, C => - un1_dci_NE, Y => N_499); - - \r.dstate_0_RNIIC256[7]\ : OR2B - port map(A => dataout_0(29), B => rdatav_0_6_sqmuxa_0, Y - => \dcramo_m_0[253]\); - - \r.dstate_RNII6PNA[1]\ : NOR2B - port map(A => \edata[7]\, B => \size_RNIBHS22[0]\, Y => - \edata_m_0[7]\); - - \r.req_RNO_5\ : MX2C - port map(A => \req\, B => \burst\, S => grant, Y => - N_2471_i); - - \r.dstate_i_2_RNIPU7E[8]\ : OR2A - port map(A => asi(3), B => \dstate_i_2[8]\, Y => N_3788); - - \r.mmctrl1.e_0_0_RNIVJMK\ : OR2 - port map(A => \e_0\, B => N_595, Y => - dstate_tr8_5_9_0_a2_0_a2_0); - - \r.mmctrl1.ctxp[25]\ : DFN1E1 - port map(D => maddress(27), CLK => lclk_c, E => - ctxp_1_sqmuxa, Q => \ctxp[25]\); - - \r.valid_0[5]\ : DFN1E0 - port map(D => \valid_0_1[5]\, CLK => lclk_c, E => - valid_0_2_sqmuxa, Q => \valid_0[5]\); - - \r.mmctrl1.ctxp[22]\ : DFN1E1 - port map(D => maddress(24), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[22]\); - - \r.xaddress_RNI1R2NN[6]\ : MX2C - port map(A => N_2233, B => eaddress_4, S => taddr_2_sqmuxa, - Y => \taddr_7[6]\); - - \r.wb.data1[17]\ : DFN1E0 - port map(D => \data1_1[17]\, CLK => lclk_c, E => - data1_0_sqmuxa_0, Q => data_1_5); - - \r.wb.addr_RNO_2[0]\ : OR2B - port map(A => maddress(0), B => N_2164, Y => \dci_m[8]\); - - \r.dstate_i_RNI3BM3A92[8]\ : OR3A - port map(A => un1_eholdn_2_9, B => read_0, C => \N_121\, Y - => flush_1_sqmuxa); - - \r.mmctrl1.ctxp[1]\ : DFN1E1 - port map(D => maddress(3), CLK => lclk_c, E => - ctxp_1_sqmuxa_0_0, Q => \ctxp[1]\); - - \r.dstate_RNIHILB6_3[7]\ : OR2B - port map(A => dataout(21), B => rdatav_0_6_sqmuxa, Y => - \dcramo_m_0[245]\); - - \r.dstate_i_2_RNIQQM12[8]\ : OR2B - port map(A => un1_m0_2_64, B => miscdata_4_sqmuxa, Y => - \mmudco_m[65]\); - - \v.wb.addr_0_sqmuxa_2\ : NAND2 - port map(A => \dstate_0[7]\, B => burst_0_sqmuxa, Y => - addr_0_sqmuxa_2); - - \r.dstate_RNI4AIHH[1]\ : AO1 - port map(A => \edata[14]\, B => \size_RNIBHS22[0]\, C => - \dcramo_m[238]\, Y => \ddatainv_0_1_1_iv_0[14]\); - - \r.cache_RNO_3\ : OR2A - port map(A => N_512, B => \e_0\, Y => cache_1_0_a2_0_0); - - \dctrl.twrite_14_iv_0_o2_a0_RNI492373\ : OR3C - port map(A => N_1_28_i, B => twrite_14_iv_0_o2_0_0, C => - N_3322, Y => twrite_14); - - \r.cctrl.dcs_RNIPCLN1[0]\ : NOR3B - port map(A => \dstate_ns_i_a4_i_a2_3_0[0]\, B => N_481, C - => N_3788, Y => \dstate_ns_i_a4_i_a2_3_2[0]\); - - \r.asi[1]\ : DFN1E1 - port map(D => asi(1), CLK => lclk_c, E => N_486_0, Q => - \asi_0[1]\); - - \v.vaddr_1_sqmuxa_0_a2_4_m1_e_5\ : NOR2 - port map(A => eaddress_16, B => eaddress_12, Y => - vaddr_1_sqmuxa_0_a2_4_m1_e_5); - - \r.xaddress_RNIJH2O2_4[0]\ : NOR2B - port map(A => dataout(10), B => \xaddress_RNIQDEG2[0]\, Y - => \dcramo_m[234]\); - - \r.dstate_i_2_RNIFPVH[8]\ : OR2 - port map(A => \dstate_i_2[8]\, B => N_496, Y => N_526); - - \r.cctrlwr_RNIJD74\ : NOR2A - port map(A => cctrlwr, B => \addr[6]\, Y => - flush_0_sqmuxa_0_o3_i_o2_0); - - \r.xaddress_RNICSNRG[1]\ : AOI1B - port map(A => \edata[2]\, B => ddatainv_0_0_sqmuxa, C => - \edata_m_0_i[10]\, Y => \ddatainv_0_1_0_iv_1[26]\); - - \r.valid_0_RNO[2]\ : OA1B - port map(A => hit_1_iv_0_a2_0_0, B => twrite_14, C => - N_2362, Y => \valid_0_1[2]\); - - \r.dstate_tr22_15_a2_7_2_0_a2\ : OR3A - port map(A => asi(4), B => N_505, C => asi(3), Y => - N_3569_2); - - \r.holdn_RNO_16\ : AOI1B - port map(A => holdns_iv_0_a2_2_3, B => - \dstate_i_RNIF4S5B92[8]\, C => N_3614, Y => holdns_iv_0_0); - - \r.holdn_RNINK401_0\ : OR3A - port map(A => N_568, B => N_3443_i, C => maddress_0_2, Y - => N_3653); - - \r.dstate[2]\ : DFN1 - port map(D => \dstate_nss[6]\, CLK => lclk_c, Q => - \dstate[2]\); - - \r.cctrl.dcs_RNIV2LD[0]\ : NOR2B - port map(A => \dcs[0]\, B => enaddr, Y => un121_m_en_i_s_0); - - \dctrl.un1_r.cctrl.dcs_1_i_s_0_o2_1\ : NOR2A - port map(A => N_499, B => un6_validrawv, Y => N_500_i); - - \r.wb.addr_RNO_0[19]\ : NOR3C - port map(A => N_221, B => \addr_1_1_iv_0_0[19]\, C => N_224, - Y => \addr_1_1_iv_0_2[19]\); - - \r.dstate_RNO_9[1]\ : OR3A - port map(A => lock, B => N_666, C => N_526, Y => N_90); - - \r.wb.addr_RNO_2[23]\ : AOI1B - port map(A => N_3838, B => N_2165_0, C => N_218, Y => - \addr_1_1_iv_0_0[23]\); - - \r.mmctrl1.ctx_0_0[3]\ : DFN1 - port map(D => \ctx_RNIAM7T[3]\, CLK => lclk_c, Q => - \ctx_0[3]\); - - \r.dstate_RNIFPT581[1]\ : OR3 - port map(A => \edata_m[1]\, B => \dcramo_m[225]\, C => - \ddatainv_0_1_1_iv_1[1]\, Y => dstate_RNIFPT581(1)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu_acache is - - port( iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - hgrant : in std_logic_vector(0 to 0); - hsize_5 : out std_logic_vector(1 to 1); - size : in std_logic_vector(1 to 1); - iosn_1 : in std_logic_vector(93 to 93); - data_0_18 : in std_logic; - data_0_1 : in std_logic; - data_0_3 : in std_logic; - data_0_17 : in std_logic; - data_0_22 : in std_logic; - data_0_21 : in std_logic; - data_0_9 : in std_logic; - data_0_23 : in std_logic; - data_0_20 : in std_logic; - data_0_4 : in std_logic; - data_0_31 : in std_logic; - data_0_26 : in std_logic; - data_0_15 : in std_logic; - data_0_7 : in std_logic; - data_0_27 : in std_logic; - data_0_25 : in std_logic; - data_0_16 : in std_logic; - data_0_30 : in std_logic; - data_0_28 : in std_logic; - data_0_14 : in std_logic; - data_0_2 : in std_logic; - data_0_11 : in std_logic; - data_0_0 : in std_logic; - data_0_12 : in std_logic; - data_0_6 : in std_logic; - data_0_19 : in std_logic; - data_18 : in std_logic; - data_1 : in std_logic; - data_3 : in std_logic; - data_17 : in std_logic; - data_22 : in std_logic; - data_21 : in std_logic; - data_9 : in std_logic; - data_23 : in std_logic; - data_20 : in std_logic; - data_4 : in std_logic; - data_31 : in std_logic; - data_26 : in std_logic; - data_15 : in std_logic; - data_7 : in std_logic; - data_27 : in std_logic; - data_25 : in std_logic; - data_16 : in std_logic; - data_30 : in std_logic; - data_28 : in std_logic; - data_14 : in std_logic; - data_2 : in std_logic; - data_11 : in std_logic; - data_0_d0 : in std_logic; - data_12 : in std_logic; - data_6 : in std_logic; - data_19 : in std_logic; - hwdata_15 : out std_logic; - hwdata_0 : out std_logic; - hwdata_14 : out std_logic; - hwdata_1 : out std_logic; - hwdata_28 : out std_logic; - hwdata_23 : out std_logic; - hwdata_12 : out std_logic; - hwdata_4 : out std_logic; - hwdata_13 : out std_logic; - hwdata_27 : out std_logic; - hwdata_25 : out std_logic; - hwdata_11 : out std_logic; - hwdata_9 : out std_logic; - hwdata_3 : out std_logic; - hwdata_16 : out std_logic; - address_1 : in std_logic_vector(31 downto 2); - haddr : out std_logic_vector(31 downto 2); - address_0 : in std_logic_vector(31 downto 2); - htrans_tz : out std_logic_vector(1 to 1); - bo_d : out std_logic_vector(3 downto 2); - iosn_0 : in std_logic_vector(93 to 93); - address : in std_logic_vector(31 downto 2); - htrans : out std_logic_vector(1 to 1); - nbo_5_0 : out std_logic_vector(1 downto 0); - size_1z : in std_logic; - werr : out std_logic; - lclk_c : in std_logic; - ready_0 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - mexc_1 : out std_logic; - ready : out std_logic; - N_466 : out std_logic; - lock : in std_logic; - lock_m : in std_logic; - hwrite_1_m_0 : out std_logic; - N_468 : out std_logic; - N_463 : out std_logic; - N_461 : out std_logic; - N_459 : out std_logic; - N_458 : out std_logic; - bo_5842_d : out std_logic; - N_139 : out std_logic; - N_138 : out std_logic; - un91_nbo_i_0 : out std_logic; - grant_1 : out std_logic; - hcache_1 : out std_logic; - werr_2_m_0 : out std_logic; - N_467 : out std_logic; - N_462 : out std_logic; - N_457 : out std_logic; - mexc_0 : out std_logic; - read_0 : in std_logic; - mexc : out std_logic; - un60_nbo : out std_logic; - hbusreq : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - N_5054 : out std_logic; - burst_0 : in std_logic; - hlock : out std_logic; - un59_nbo : out std_logic; - ba : out std_logic; - cache : in std_logic; - read : in std_logic; - burst : in std_logic; - req_1 : in std_logic; - req_0 : in std_logic; - req : in std_logic; - N_6093_i : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - grant_0 : out std_logic; - grant : out std_logic; - rst : in std_logic; - bo_5842_d_0 : out std_logic - ); - -end mmu_acache; - -architecture DEF_ARCH of mmu_acache is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \nbo_5_1[0]\, N_5210_i_0, N_4258, N_6040_2, un14_dreq, - N_4259, \bo[1]\, \bo[0]\, ba_3, bg_m, ba_m, un15_dreq_i, - un3_dreq, nbo4, N_5618_i, nba_0_0, \htrans_4_sqmuxa_1_1\, - htrans_4_sqmuxa_1_1_0, un17_dreq, hbusreq_0, - htrans_4_sqmuxa_1_0, lb, hcache_1_0, htrans_1_sqmuxa_0, - un71_nbo, \nbo_5_0[0]\, lb_0_sqmuxa_0, dgrant_0_sqmuxa_1, - bg, mmgrant_0_sqmuxa_1, igrant_0_sqmuxa_1, - \hburst_1_i_0[0]\, \nbo_5_0[1]\, un6_dreq, \bo_ns_0_3[0]\, - N_6039, \bo_RNI35I6[0]\, N_6037, \bo_ns_0_2[0]\, N_6042, - N_6036, \nbo_m[0]\, nbo4_0, N_6043_1, \bo_ns_i_2[1]\, - \bo_RNO_8[1]\, N_6044, hlocken_1, hlocken_0, hlocken, - un88_nbo_0, \bo_ns_i_a7_0[1]\, nba, \nbo_m_0[0]\, - \nbo[0]\, un71_nbo_0, \bo_ns_i_o7_0_0[1]\, \ba\, - un6_dreq_0, \bo_ns_0_a7_0[0]\, un569_dec_hcache_NE_7, - un569_dec_hcache_NE_6, un569_dec_hcache_NE_6_0, - un569_dec_hcache_NE_3, un569_dec_hcache_NE_5, - un569_dec_hcache_NE_1, hcache, hcache_0, - un509_dec_hcache_NE, un569_dec_hcache_NE, \grant\, - un19_nbo, retry2_RNILAS7, un11_dreq, \bo_5842_d_0\, - dgrant_0_sqmuxa, N_6030, N_6049, N_6040, \bo_ns[0]\, - N_4302, hlock_0_sqmuxa, hlock_1_sqmuxa, N_6025_i_0, - \bo_RNO_2[1]\, N_6043, N_6027, \nbo_RNO[1]\, nbo95, - \nbo[1]\, N_5056, lb_0_sqmuxa, \htrans[1]\, un10_hbusreq, - \grant_0\, un30_nbo, \bo_RNO_5[1]\, - \un1_htrans_1_sqmuxa_0\, \htrans_tz[1]\, N_4986, N_4987, - N_4960, \haddr_6[4]\, \haddr_10[4]\, N_4992, \N_6093_i\, - hwrite_1_m, werr_2_m, werr_RNO, N_4978, N_4983, N_4974, - N_4982, N_5006, N_5014, N_4979, N_5011, \un59_nbo\, - hcache_RNO, N_5540, retry2, dgrant_1, retry2_RNO, N_6050, - N_5939s, N_5939, un87_nbo, \haddr_6[3]\, N_4985, N_5017, - N_4977, N_4980, N_4981, N_5009, N_5012, N_5013, N_4966, - N_4998, N_4965, N_4997, N_4959, \haddr_10[3]\, N_4991, - N_4968, N_5000, N_5010, N_4964, N_4996, N_4976, N_4961, - N_4993, N_5008, \nbo_5[1]\, N_4958, \haddr_6_i[2]\, - \haddr_10_i[2]\, N_4970, N_4971, N_4990, N_5002, N_5003, - N_4975, N_5007, \nbo_5[0]\, \bo_5842_d\, N_5016, N_4984, - N_5001, N_4969, CO1, N_5539, hlocken_2, N_5542, N_5940, - N_5940s, N_5018, N_5019, \hlock\, N_4967, N_4999, - \bo_d[2]\, \lb_0_sqmuxa_1\, N_5015, bg_RNO, hlocken_RNO, - N_5620_i, N_4963, N_4995, N_4962, N_4994, N_4972, N_4973, - N_5004, N_5005, ready_1, mmmexc_2_sqmuxa, \mexc\, - \mexc_0\, \bo_d[3]\, lb_RNO, N_5541, ba_RNO, un11_hbusreq, - \N_5054\, un5_hlock, \un60_nbo\, \hcache_1\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - htrans_tz(1) <= \htrans_tz[1]\; - bo_d(3) <= \bo_d[3]\; - bo_d(2) <= \bo_d[2]\; - htrans(1) <= \htrans[1]\; - nbo_5_0(1) <= \nbo_5_0[1]\; - nbo_5_0(0) <= \nbo_5_0[0]\; - bo_5842_d <= \bo_5842_d\; - hcache_1 <= \hcache_1\; - mexc_0 <= \mexc_0\; - mexc <= \mexc\; - un60_nbo <= \un60_nbo\; - lb_0_sqmuxa_1 <= \lb_0_sqmuxa_1\; - N_5054 <= \N_5054\; - hlock <= \hlock\; - un59_nbo <= \un59_nbo\; - ba <= \ba\; - N_6093_i <= \N_6093_i\; - un1_htrans_1_sqmuxa_0 <= \un1_htrans_1_sqmuxa_0\; - grant_0 <= \grant_0\; - grant <= \grant\; - bo_5842_d_0 <= \bo_5842_d_0\; - - \r.bo_RNIDH8P7[0]\ : MX2 - port map(A => address(14), B => address_0(14), S => - \nbo_5_1[0]\, Y => N_4970); - - \r.bo_RNIB98P7[0]\ : MX2 - port map(A => address_0(21), B => address(21), S => - \nbo_5_0[0]\, Y => N_4977); - - \r.bo_RNIFDOG[0]\ : MX2C - port map(A => data_20, B => data_0_20, S => \bo_5842_d\, Y - => N_458); - - \r.hlocken_RNI8OP6\ : OR2A - port map(A => req_0, B => hlocken, Y => hlocken_0); - - \r.bg\ : DFN1 - port map(D => bg_RNO, CLK => lclk_c, Q => bg); - - \r.bo_RNITQI7[0]\ : MX2C - port map(A => data_0_d0, B => data_0_0, S => \bo_5842_d_0\, - Y => N_457); - - \r.bo_RNID98P7[0]\ : MX2 - port map(A => address_0(30), B => address(30), S => - \nbo_5_0[0]\, Y => N_4986); - - \r.ba_RNI7OED\ : NOR2B - port map(A => req_1, B => \ba\, Y => un6_dreq_0); - - \r.bg_RNIMDNL1\ : OR3C - port map(A => req, B => bg, C => iosn_0(93), Y => - dgrant_0_sqmuxa_1); - - \r.nbo_RNISOR4J[1]\ : MX2C - port map(A => N_4976, B => N_5008, S => \nbo_5[1]\, Y => - haddr(20)); - - \r.nbo[0]\ : DFN1 - port map(D => N_5620_i, CLK => lclk_c, Q => \nbo[0]\); - - \r.bo_RNO_8[0]\ : OR3C - port map(A => \bo_ns_0_a7_0[0]\, B => N_6030, C => N_6049, - Y => N_6036); - - \r.lb_RNO_0\ : MX2 - port map(A => lb, B => lb_0_sqmuxa, S => iosn_1(93), Y => - N_5541); - - \r.bo_RNILPOG[0]\ : MX2 - port map(A => data_23, B => data_0_23, S => \bo_5842_d\, Y - => N_459); - - \r.bo_RNIBNJ7[0]\ : MX2C - port map(A => data_7, B => data_0_7, S => \bo_5842_d\, Y - => hwdata_4); - - \r.bo_RNO_0[0]\ : MX2 - port map(A => \bo[0]\, B => \bo_ns[0]\, S => iosn_1(93), Y - => N_5939); - - \r.retry2_RNIHCJF\ : AO1A - port map(A => \ba\, B => retry2, C => nba, Y => N_6040_2); - - \r.hcache_RNO_1\ : OR2B - port map(A => \grant\, B => \grant_0\, Y => hcache_1_0); - - un20_haddr_1_CO1 : OR2B - port map(A => address_0(3), B => address_0(2), Y => CO1); - - \r.nbo_RNIHN2CB[1]\ : OA1A - port map(A => size(1), B => \nbo_5[1]\, C => \nbo_5[0]\, Y - => hsize_5(1)); - - \r.bo_RNIFD8P7[0]\ : MX2 - port map(A => address_0(31), B => address(31), S => - \nbo_5_0[0]\, Y => N_4987); - - \r.bo_RNO_6[1]\ : AO1C - port map(A => req_0, B => \ba\, C => \bo[1]\, Y => - \bo_ns_i_o7_0_0[1]\); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_1\ : NOR2 - port map(A => address(22), B => address(23), Y => - un569_dec_hcache_NE_1); - - \r.bo_RNI8LOP7[0]\ : NOR2A - port map(A => address_1(19), B => \nbo_5[0]\, Y => N_5007); - - \r.ba_RNIRM3H\ : OR2A - port map(A => un71_nbo_0, B => \bo_d[2]\, Y => un71_nbo); - - \r.bo_RNIJPOG[0]\ : MX2C - port map(A => data_14, B => data_0_14, S => \bo_5842_d_0\, - Y => hwdata_11); - - \r.nbo_RNIFH3IK[1]\ : MX2C - port map(A => N_4960, B => N_4992, S => \nbo_5_0[1]\, Y => - haddr(4)); - - \r.bo_RNIFH8P7[0]\ : MX2 - port map(A => address_0(23), B => address(23), S => - \nbo_5_0[0]\, Y => N_4979); - - \r.retry2_RNO\ : NOR2A - port map(A => rst, B => retry2_RNILAS7, Y => retry2_RNO); - - \r.bo_RNI5G0Q7[0]\ : MX2 - port map(A => address_0(5), B => address_1(5), S => - \nbo_5_1[0]\, Y => N_4961); - - \r.ba_RNI2OED\ : NOR2B - port map(A => req, B => \ba\, Y => un71_nbo_0); - - \r.bo_RNIPUK3_0[0]\ : OR2A - port map(A => \bo[0]\, B => \bo[1]\, Y => \bo_d[2]\); - - \r.bo_RNI6DOP7[0]\ : NOR2A - port map(A => address_1(17), B => \nbo_5[0]\, Y => N_5005); - - \r.bo_RNI0HNP7[0]\ : NOR2A - port map(A => address_1(20), B => \nbo_5_1[0]\, Y => N_5008); - - \r.nbo_RNI29S4J[1]\ : MX2C - port map(A => N_4978, B => N_5010, S => \nbo_5_0[1]\, Y => - haddr(22)); - - \r.bg_RNIOE4OO\ : OA1A - port map(A => bg, B => un10_hbusreq, C => hbusreq_0, Y => - hbusreq); - - \r.bo_RNILLOG[0]\ : MX2 - port map(A => data_31, B => data_0_31, S => \bo_5842_d\, Y - => hwdata_28); - - \r.nbo_RNO[0]\ : OA1 - port map(A => nbo95, B => \nbo_5[0]\, C => rst, Y => - N_5620_i); - - \r.hlocken_RNO_0\ : MX2 - port map(A => hlocken, B => hlocken_2, S => iosn_1(93), Y - => N_5539); - - \r.bo_RNIV28P[0]\ : MX2 - port map(A => \bo[0]\, B => \nbo_m_0[0]\, S => - retry2_RNILAS7, Y => N_4258); - - \r.bo_RNIDNBJ7[0]\ : MX2 - port map(A => N_5210_i_0, B => N_4258, S => N_6040_2, Y => - \nbo_5[0]\); - - \r.nbo_RNII8CAK[1]\ : MX2C - port map(A => N_4959, B => N_4991, S => \nbo_5_0[1]\, Y => - haddr(3)); - - \r.nbo_RNIHDLAB[1]\ : AO1D - port map(A => burst, B => \nbo_5_0[0]\, C => \nbo_5_0[1]\, - Y => \hburst_1_i_0[0]\); - - \r.ba_RNITG7V1\ : OR2A - port map(A => hresp(0), B => ready_1, Y => mmmexc_2_sqmuxa); - - \r.nbo[1]\ : DFN1 - port map(D => \nbo_RNO[1]\, CLK => lclk_c, Q => \nbo[1]\); - - \r.bg_RNIR7VQC\ : OR2A - port map(A => igrant_0_sqmuxa_1, B => un30_nbo, Y => - \grant_0\); - - \r.ba_RNI6ANVJ\ : NOR2B - port map(A => un11_hbusreq, B => \N_5054\, Y => - un10_hbusreq); - - \r.bo_RNI69OP7[0]\ : NOR2A - port map(A => address_1(26), B => \nbo_5_0[0]\, Y => N_5014); - - \r.bo_RNO_3[1]\ : OAI1 - port map(A => N_6027, B => \bo_ns_i_o7_0_0[1]\, C => - \bo_ns_i_a7_0[1]\, Y => N_6043); - - \r.bo_RNIJLOG[0]\ : MX2 - port map(A => data_22, B => data_0_22, S => \bo_5842_d\, Y - => N_468); - - \r.bo_RNID01Q7[0]\ : MX2 - port map(A => address(9), B => address_0(9), S => - \nbo_5_1[0]\, Y => N_4965); - - \r.bo_RNIVGNP7[0]\ : OR2A - port map(A => address_1(10), B => \nbo_5_1[0]\, Y => N_4998); - - \r.bo_RNI998P7[0]\ : MX2 - port map(A => address(12), B => address_0(12), S => - \nbo_5_1[0]\, Y => N_4968); - - \r.nba_RNIMTLD\ : NOR2A - port map(A => req, B => nba, Y => N_6049); - - \r.bo_RNIT9PG[0]\ : MX2 - port map(A => data_27, B => data_0_27, S => \bo_5842_d_0\, - Y => N_139); - - \r.bo_RNI2TNP7[0]\ : NOR2A - port map(A => address(13), B => \nbo_5[0]\, Y => N_5001); - - \r.bo_RNI1HNP7[0]\ : NOR2A - port map(A => address_1(30), B => \nbo_5[0]\, Y => N_5018); - - \r.bo_RNIL19P7[0]\ : MX2 - port map(A => address(18), B => address_0(18), S => - \nbo_5_0[0]\, Y => N_4974); - - \r.retry2_RNILAS7\ : OR2A - port map(A => retry2, B => \ba\, Y => retry2_RNILAS7); - - \r.bo_RNI2PNP7[0]\ : NOR2A - port map(A => address_1(22), B => \nbo_5_1[0]\, Y => N_5010); - - \r.bo[1]\ : DFN1 - port map(D => N_5940s, CLK => lclk_c, Q => \bo[1]\); - - \r.bo_RNI758P7[0]\ : MX2C - port map(A => address(11), B => address_0(11), S => - \nbo_5[0]\, Y => N_4967); - - \r.ba_RNI0HBMB\ : OR2 - port map(A => un30_nbo, B => un6_dreq, Y => \lb_0_sqmuxa_1\); - - \r.bo_RNI958P7[0]\ : MX2 - port map(A => address_0(20), B => address(20), S => - \nbo_5_1[0]\, Y => N_4976); - - \r.werr_RNO_1\ : OR2A - port map(A => \mexc\, B => read_0, Y => hwrite_1_m); - - \r.bo_RNIHP8P7[0]\ : MX2 - port map(A => address(16), B => address_0(16), S => - \nbo_5[0]\, Y => N_4972); - - \r.hlocken_RNIU579\ : NOR2A - port map(A => hlocken, B => retry2_RNILAS7, Y => un5_hlock); - - \r.bo_RNI41OP7[0]\ : NOR2A - port map(A => address_1(24), B => \nbo_5_0[0]\, Y => N_5012); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_5\ : NOR3A - port map(A => un569_dec_hcache_NE_1, B => address(21), C - => address(20), Y => un569_dec_hcache_NE_5); - - \r.hcache\ : DFN1 - port map(D => hcache_RNO, CLK => lclk_c, Q => \hcache_1\); - - \r.bo_RNIN59P7[0]\ : MX2 - port map(A => address(19), B => address_0(19), S => - \nbo_5_1[0]\, Y => N_4975); - - \r.bo_RNO_11[0]\ : OR2A - port map(A => req_1, B => \bo[0]\, Y => N_6030); - - \r.bo_RNI9O0Q7[0]\ : MX2 - port map(A => address(7), B => address_0(7), S => - \nbo_5[0]\, Y => N_4963); - - \r.bg_RNIO1K8T\ : NOR3C - port map(A => iosn_0(93), B => bg, C => \htrans[1]\, Y => - bg_m); - - \r.retry2_RNI1QM9\ : MX2A - port map(A => retry2, B => \bo[0]\, S => \ba\, Y => N_6027); - - \r.nbo_RNICDT4J[1]\ : MX2C - port map(A => N_4973, B => N_5005, S => \nbo_5[1]\, Y => - haddr(17)); - - \r.ba_RNIJPV24\ : NOR2A - port map(A => un6_dreq, B => \nbo_5_0[1]\, Y => - htrans_1_sqmuxa_0); - - \r.bo_RNO_5[1]\ : NOR3B - port map(A => \ba\, B => \bo[1]\, C => req_0, Y => - \bo_RNO_5[1]\); - - \r.bo_RNO_7[1]\ : NOR2A - port map(A => N_6043_1, B => nba, Y => \bo_ns_i_a7_0[1]\); - - \r.bo_RNIL3KL7[0]\ : NOR2A - port map(A => address_1(7), B => \nbo_5[0]\, Y => N_4995); - - GND_i : GND - port map(Y => \GND\); - - \comb.un87_nbo\ : AO1B - port map(A => un88_nbo_0, B => hcache, C => size_1z, Y => - un87_nbo); - - \r.nba_0_RNO\ : AND2 - port map(A => \htrans[1]\, B => rst, Y => nba_0_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.bo_RNIMFS22_0[0]\ : NOR2 - port map(A => \bo_d[2]\, B => mmmexc_2_sqmuxa, Y => - \mexc_0\); - - \r.retry2\ : DFN1 - port map(D => retry2_RNO, CLK => lclk_c, Q => retry2); - - \r.bo_RNO_8[1]\ : OR3B - port map(A => nba, B => retry2_RNILAS7, C => \nbo[1]\, Y - => \bo_RNO_8[1]\); - - \r.bg_RNIRE7L1\ : NOR3C - port map(A => req_0, B => bg, C => iosn_0(93), Y => - mmgrant_0_sqmuxa_1); - - \r.nbo_RNI9O78B[1]\ : OR2 - port map(A => read, B => \un59_nbo\, Y => werr_2_m_0); - - \r.bo_RNIVUI7[0]\ : MX2 - port map(A => data_1, B => data_0_1, S => \bo_5842_d\, Y - => N_466); - - \r.bg_RNIR8FQC\ : OR2B - port map(A => mmgrant_0_sqmuxa_1, B => un19_nbo, Y => - \grant\); - - \r.bo_RNI5BJ7[0]\ : MX2 - port map(A => data_4, B => data_0_4, S => \bo_5842_d\, Y - => hwdata_1); - - \r.bo_RNIHHOG[0]\ : MX2 - port map(A => data_21, B => data_0_21, S => \bo_5842_d\, Y - => N_463); - - \r.bo_RNIP59P7[0]\ : MX2 - port map(A => address_1(28), B => address(28), S => - \nbo_5[0]\, Y => N_4984); - - \r.nbo_RNIJ2SH3_0[1]\ : MX2A - port map(A => un14_dreq, B => N_4259, S => N_6040_2, Y => - \nbo_5[1]\); - - \r.nbo_RNI1TR4J[1]\ : MX2C - port map(A => N_4986, B => N_5018, S => \nbo_5[1]\, Y => - haddr(30)); - - \r.bo_RNO_10[0]\ : NOR2A - port map(A => \ba\, B => \bo[1]\, Y => \bo_ns_0_a7_0[0]\); - - \r.bo[0]\ : DFN1 - port map(D => N_5939s, CLK => lclk_c, Q => \bo[0]\); - - \r.nbo_RNIT4S4J[1]\ : MX2C - port map(A => N_4968, B => N_5000, S => \nbo_5_0[1]\, Y => - haddr(12)); - - \r.ba_RNIR7F7C\ : MX2C - port map(A => htrans_1_sqmuxa_0, B => un71_nbo, S => - \nbo_5_0[0]\, Y => \un1_htrans_1_sqmuxa_0\); - - \r.nba_0\ : AND2 - port map(A => ba_3, B => nba_0_0, Y => N_5618_i); - - \r.ba_RNIFGDJ1\ : OR2 - port map(A => ready_1, B => \bo_d[3]\, Y => ready_0); - - \r.bo_RNIP5PG[0]\ : MX2C - port map(A => data_17, B => data_0_17, S => \bo_5842_d\, Y - => hwdata_14); - - \r.ba_RNI8OP11\ : AX1B - port map(A => CO1, B => un71_nbo, C => address_1(4), Y => - \haddr_10[4]\); - - \r.nbo_RNIBMG1J[1]\ : MX2C - port map(A => N_4961, B => N_4993, S => \nbo_5_0[1]\, Y => - haddr(5)); - - \r.bo_RNO_9[1]\ : AO1 - port map(A => N_6050, B => retry2_RNILAS7, C => \bo[1]\, Y - => N_6044); - - htrans_4_sqmuxa_1_1_RNISFROR : AO1B - port map(A => \un1_htrans_1_sqmuxa_0\, B => \un60_nbo\, C - => \htrans_tz[1]\, Y => \htrans[1]\); - - \r.bo_RNILT8P7[0]\ : MX2 - port map(A => address_0(26), B => address(26), S => - \nbo_5_0[0]\, Y => N_4982); - - \r.bo_RNIE2S29[0]\ : MX2C - port map(A => \haddr_6[3]\, B => \haddr_10[3]\, S => - \nbo_5_1[0]\, Y => N_4959); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.lb\ : DFN1 - port map(D => lb_RNO, CLK => lclk_c, Q => lb); - - \r.bo_RNIJT8P7[0]\ : MX2 - port map(A => address(17), B => address_0(17), S => - \nbo_5[0]\, Y => N_4973); - - \r.ba\ : DFN1 - port map(D => ba_RNO, CLK => lclk_c, Q => \ba\); - - htrans_4_sqmuxa_1_1 : NOR2 - port map(A => un15_dreq_i, B => htrans_4_sqmuxa_1_1_0, Y - => \htrans_4_sqmuxa_1_1\); - - \r.bo_RNIR5PG[0]\ : MX2 - port map(A => data_26, B => data_0_26, S => \bo_5842_d\, Y - => hwdata_23); - - \r.bo_RNO_4[1]\ : NOR3C - port map(A => \bo_RNO_8[1]\, B => \bo_RNI35I6[0]\, C => - N_6044, Y => \bo_ns_i_2[1]\); - - \r.bo_RNIJP8P7[0]\ : MX2 - port map(A => address_0(25), B => address(25), S => - \nbo_5_0[0]\, Y => N_4981); - - \r.bo_RNO[1]\ : NOR2B - port map(A => rst, B => N_5940, Y => N_5940s); - - \r.bo_RNO_2[0]\ : NOR3C - port map(A => N_6039, B => \bo_RNI35I6[0]\, C => N_6037, Y - => \bo_ns_0_3[0]\); - - \r.werr\ : DFN1 - port map(D => werr_RNO, CLK => lclk_c, Q => werr); - - \r.ba_RNIFGDJ1_0\ : NOR2 - port map(A => ready_1, B => \bo_d[2]\, Y => ready); - - \r.nbo_RNIITT4J[1]\ : MX2C - port map(A => N_4975, B => N_5007, S => \nbo_5[1]\, Y => - haddr(19)); - - \r.bo_RNIPOS8B[0]\ : XAI1A - port map(A => \nbo_5[1]\, B => \nbo_5[0]\, C => \bo_d[2]\, - Y => hlock_1_sqmuxa); - - \r.bo_RNIFVJ7[0]\ : MX2 - port map(A => data_9, B => data_0_9, S => \bo_5842_d\, Y - => N_461); - - \r.nbo_RNIQSR4J[1]\ : MX2C - port map(A => N_4967, B => N_4999, S => \nbo_5[1]\, Y => - haddr(11)); - - \r.bo_RNIMFS22_1[0]\ : NOR2 - port map(A => \bo_5842_d\, B => mmmexc_2_sqmuxa, Y => - \mexc\); - - \r.nbo_RNI0DS4J[1]\ : MX2C - port map(A => N_4969, B => N_5001, S => \nbo_5[1]\, Y => - haddr(13)); - - \r.bo_RNI7DOP7[0]\ : NOR2A - port map(A => address_1(27), B => \nbo_5[0]\, Y => N_5015); - - \r.ba_RNO\ : OA1 - port map(A => bg_m, B => ba_m, C => rst, Y => ba_RNO); - - \r.ba_RNIRGBMB\ : OR2 - port map(A => un71_nbo, B => \un59_nbo\, Y => - htrans_0_sqmuxa_2); - - \r.lb_RNO_2\ : OR3A - port map(A => address(2), B => address(3), C => \N_6093_i\, - Y => lb_0_sqmuxa_0); - - \r.bo_RNIR9PG[0]\ : MX2C - port map(A => data_18, B => data_0_18, S => \bo_5842_d\, Y - => hwdata_15); - - htrans_4_sqmuxa_1_1_RNO : OR2 - port map(A => N_6040_2, B => un17_dreq, Y => - htrans_4_sqmuxa_1_1_0); - - \r.bo_RNO_1[0]\ : OR3C - port map(A => \bo_ns_0_3[0]\, B => \bo_ns_0_2[0]\, C => - N_6040, Y => \bo_ns[0]\); - - \r.hlocken\ : DFN1 - port map(D => hlocken_RNO, CLK => lclk_c, Q => hlocken); - - \r.bo_RNIPOS8B_0[0]\ : OR2B - port map(A => \bo_d[2]\, B => un19_nbo, Y => hlock_0_sqmuxa); - - \r.bo_RNIN3KL7[0]\ : NOR2A - port map(A => address_1(9), B => \nbo_5_1[0]\, Y => N_4997); - - \r.bo_RNIDDOG[0]\ : MX2 - port map(A => data_11, B => data_0_11, S => \bo_5842_d_0\, - Y => N_462); - - \r.nbo_RNIE9T4J[1]\ : MX2C - port map(A => N_4982, B => N_5014, S => \nbo_5_0[1]\, Y => - haddr(26)); - - \r.bo_RNI1PNP7[0]\ : NOR2A - port map(A => address_1(12), B => \nbo_5_1[0]\, Y => N_5000); - - \r.bo_RNI7HOP7[0]\ : NOR2A - port map(A => address_1(18), B => \nbo_5_0[0]\, Y => N_5006); - - \r.ba_RNI436I\ : XOR2 - port map(A => address(2), B => un6_dreq, Y => - \haddr_6_i[2]\); - - \r.nba_RNILPKJ\ : OR2A - port map(A => N_6049, B => req_1, Y => N_6050); - - \r.bo_RNI8HOP7[0]\ : NOR2A - port map(A => address_0(28), B => \nbo_5[0]\, Y => N_5016); - - \r.bo_RNII3KL7[0]\ : OR2A - port map(A => address_0(4), B => \nbo_5_0[0]\, Y => N_4992); - - \r.hlocken_RNI4AJRB\ : OR2A - port map(A => lock_m, B => nbo95, Y => N_4302); - - \r.bo_RNI2LNP7[0]\ : NOR2A - port map(A => address_1(31), B => \nbo_5[0]\, Y => N_5019); - - \r.ba_RNI1R4B\ : OR2B - port map(A => \ba\, B => \bo_d[3]\, Y => un11_hbusreq); - - \r.ba_RNION7S\ : AX1A - port map(A => un71_nbo, B => address_0(2), C => - address_0(3), Y => \haddr_10[3]\); - - \r.bo_RNIN19P7[0]\ : MX2 - port map(A => address_0(27), B => address(27), S => - \nbo_5_0[0]\, Y => N_4983); - - \r.ba_RNI0N3H\ : OR2A - port map(A => un6_dreq_0, B => \bo_d[3]\, Y => un6_dreq); - - \r.nbo_RNIU8HF[0]\ : NOR2B - port map(A => \nbo[0]\, B => nba, Y => \nbo_m_0[0]\); - - \r.nbo_RNIB1T4J[1]\ : MX2C - port map(A => N_4981, B => N_5013, S => \nbo_5_0[1]\, Y => - haddr(25)); - - \r.ba_RNILRDL\ : MX2A - port map(A => \N_6093_i\, B => address(4), S => un6_dreq, Y - => \haddr_6[4]\); - - \r.bo_RNIHL8P7[0]\ : MX2 - port map(A => address_0(24), B => address(24), S => - \nbo_5_0[0]\, Y => N_4980); - - \r.bo_RNIK3KL7[0]\ : NOR2A - port map(A => address_1(6), B => \nbo_5[0]\, Y => N_4994); - - \r.retry2_RNI0GK4\ : OR2 - port map(A => retry2, B => un17_dreq, Y => dgrant_1); - - \r.ba_RNIK1T98\ : NOR3B - port map(A => un71_nbo, B => \nbo_5_0[0]\, C => burst_0, Y - => N_5056); - - \r.bo_RNIPUK3_2[0]\ : OR2 - port map(A => \bo[1]\, B => \bo[0]\, Y => \bo_d[3]\); - - \r.ba_RNIT7GA6\ : AO1D - port map(A => un3_dreq, B => nbo4, C => htrans_4_sqmuxa_1_0, - Y => N_5210_i_0); - - \r.hcache_RNO_0\ : MX2 - port map(A => \hcache_1\, B => hcache, S => dgrant_0_sqmuxa, - Y => N_5540); - - \r.nbo_RNIN1U4J[1]\ : MX2C - port map(A => N_4985, B => N_5017, S => \nbo_5_0[1]\, Y => - haddr(29)); - - \r.nbo_RNIJ2SH3[1]\ : MX2A - port map(A => un14_dreq, B => N_4259, S => N_6040_2, Y => - \nbo_5_0[1]\); - - \r.nbo_RNI0Q75B_0[1]\ : OR2A - port map(A => \nbo_5[0]\, B => \nbo_5[1]\, Y => \un59_nbo\); - - \r.nbo_RNI0Q75B[1]\ : OR2B - port map(A => \nbo_5[1]\, B => \nbo_5[0]\, Y => \un60_nbo\); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_6\ : NOR3A - port map(A => un569_dec_hcache_NE_3, B => address(25), C - => address(24), Y => un569_dec_hcache_NE_6_0); - - \r.retry2_RNIMNJVC\ : NOR2B - port map(A => dgrant_0_sqmuxa, B => dgrant_1, Y => grant_1); - - \r.bo_RNIJHOG[0]\ : MX2 - port map(A => data_30, B => data_0_30, S => \bo_5842_d_0\, - Y => hwdata_27); - - \r.nbo_RNIEQG1J[1]\ : MX2C - port map(A => N_4962, B => N_4994, S => \nbo_5[1]\, Y => - haddr(6)); - - \comb.ahb_slv_dec_cache.hcache_0\ : AO1A - port map(A => address(30), B => address(29), C => - address(31), Y => hcache_0); - - \r.bo_RNIM3KL7[0]\ : NOR2A - port map(A => address_1(8), B => \nbo_5_1[0]\, Y => N_4996); - - \r.ba_RNI9J8J\ : AX1A - port map(A => un6_dreq, B => address(2), C => address(3), Y - => \haddr_6[3]\); - - \comb.un15_dreq\ : OR2 - port map(A => un3_dreq, B => nbo4, Y => un15_dreq_i); - - \r.hlocken_RNO\ : NOR2B - port map(A => rst, B => N_5539, Y => hlocken_RNO); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_3\ : NOR2 - port map(A => address(26), B => address(27), Y => - un569_dec_hcache_NE_3); - - \r.bo_RNIABJA9[0]\ : MX2C - port map(A => \haddr_6[4]\, B => \haddr_10[4]\, S => - \nbo_5_0[0]\, Y => N_4960); - - \r.ba_RNI0OJG\ : NOR3B - port map(A => \ba\, B => req_0, C => \bo_5842_d_0\, Y => - un11_dreq); - - \r.werr_RNO\ : AOI1B - port map(A => werr_2_m, B => hwrite_1_m, C => rst, Y => - werr_RNO); - - \r.bo_RNIBS0Q7[0]\ : MX2 - port map(A => address(8), B => address_0(8), S => - \nbo_5_1[0]\, Y => N_4964); - - \r.bo_RNI9LOP7[0]\ : OR2A - port map(A => address_1(29), B => \nbo_5_0[0]\, Y => N_5017); - - \comb.ahb_slv_dec_cache.6.4.un509_dec_hcache_NE\ : OR3B - port map(A => address(28), B => un569_dec_hcache_NE_6, C - => address(29), Y => un509_dec_hcache_NE); - - \r.nbo_RNI6TS4J[1]\ : MX2C - port map(A => N_4971, B => N_5003, S => \nbo_5[1]\, Y => - haddr(15)); - - \r.lb_RNO_1\ : NOR2 - port map(A => lb_0_sqmuxa_0, B => \lb_0_sqmuxa_1\, Y => - lb_0_sqmuxa); - - \r.hlocken_RNO_1\ : NOR2 - port map(A => \hlock\, B => hgrant(0), Y => hlocken_2); - - \r.bo_RNIMFS22[0]\ : OR2 - port map(A => \bo_d[3]\, B => mmmexc_2_sqmuxa, Y => mexc_1); - - \r.bg_RNO\ : NOR2B - port map(A => rst, B => N_5542, Y => bg_RNO); - - \comb.v.ba_3_iv\ : NOR2 - port map(A => bg_m, B => ba_m, Y => ba_3); - - \r.nbo_RNI9H2GC[1]\ : OR2A - port map(A => un87_nbo, B => \un59_nbo\, Y => un91_nbo_i_0); - - \r.bo_RNO_7[0]\ : OR3 - port map(A => retry2, B => \ba\, C => N_6050, Y => N_6042); - - \r.bo_RNIQH7S8[0]\ : MX2C - port map(A => \haddr_6_i[2]\, B => \haddr_10_i[2]\, S => - \nbo_5_1[0]\, Y => N_4958); - - \r.bo_RNO_4[0]\ : OR3 - port map(A => req_1, B => req_0, C => N_6040_2, Y => N_6040); - - \r.bo_RNI7K0Q7[0]\ : MX2 - port map(A => address(6), B => address_0(6), S => - \nbo_5[0]\, Y => N_4962); - - \r.nbo_RNO[1]\ : NOR3B - port map(A => rst, B => \nbo_5_0[1]\, C => nbo95, Y => - \nbo_RNO[1]\); - - \r.lb_RNI48TG4\ : OA1C - port map(A => htrans_4_sqmuxa_1_0, B => N_6040_2, C => lb, - Y => hbusreq_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.bo_RNO_6[0]\ : AO1B - port map(A => N_6050, B => retry2_RNILAS7, C => \bo[0]\, Y - => N_6037); - - \r.bo_RNIFL8P7[0]\ : MX2 - port map(A => address(15), B => address_0(15), S => - \nbo_5_1[0]\, Y => N_4971); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE\ : OR3C - port map(A => un569_dec_hcache_NE_6_0, B => - un569_dec_hcache_NE_5, C => un569_dec_hcache_NE_7, Y => - un569_dec_hcache_NE); - - \r.bo_RNO_5[0]\ : OR3B - port map(A => hlocken, B => retry2_RNILAS7, C => nba, Y => - N_6039); - - \r.nbo_RNIMNB8B[1]\ : OR2A - port map(A => un19_nbo, B => read_0, Y => hwrite_1_m_0); - - \r.hlocken_RNI3EDO\ : OR2B - port map(A => N_6043_1, B => un71_nbo, Y => nbo4_0); - - \r.nba\ : DFN1 - port map(D => N_5618_i, CLK => lclk_c, Q => nba); - - \r.bo_RNO_2[1]\ : OAI1 - port map(A => N_6027, B => \bo_RNO_5[1]\, C => N_6049, Y - => \bo_RNO_2[1]\); - - \r.bo_RNI37J7[0]\ : MX2 - port map(A => data_3, B => data_0_3, S => \bo_5842_d\, Y - => hwdata_0); - - \r.bo_RNO[0]\ : NOR2B - port map(A => rst, B => N_5939, Y => N_5939s); - - \r.bo_RNI0LNP7[0]\ : OR2A - port map(A => address_1(11), B => \nbo_5[0]\, Y => N_4999); - - \r.nbo_RNI45S4J[1]\ : MX2C - port map(A => N_4987, B => N_5019, S => \nbo_5[1]\, Y => - haddr(31)); - - \r.nbo_RNIHUG1J[1]\ : MX2C - port map(A => N_4963, B => N_4995, S => \nbo_5[1]\, Y => - haddr(7)); - - \r.hlocken_RNI8FTN\ : OR2A - port map(A => un6_dreq, B => hlocken_0, Y => hlocken_1); - - \r.bo_RNIDNBJ7_1[0]\ : MX2 - port map(A => N_5210_i_0, B => N_4258, S => N_6040_2, Y => - \nbo_5_0[0]\); - - \r.ba_RNITGNG2\ : OR2A - port map(A => un3_dreq, B => nbo4, Y => un14_dreq); - - \r.nbo_RNIFLT4J[1]\ : MX2C - port map(A => N_4974, B => N_5006, S => \nbo_5_0[1]\, Y => - haddr(18)); - - \r.bo_RNIMRCD21[0]\ : OR3C - port map(A => N_4302, B => hlock_0_sqmuxa, C => - hlock_1_sqmuxa, Y => \hlock\); - - \r.bo_RNIJ3KL7[0]\ : NOR2A - port map(A => address(5), B => \nbo_5_1[0]\, Y => N_4993); - - \r.ba_RNIQAM71\ : OR3B - port map(A => un6_dreq, B => req, C => un11_dreq, Y => - un3_dreq); - - \r.nbo_RNI5HS4J[1]\ : MX2C - port map(A => N_4979, B => N_5011, S => \nbo_5_0[1]\, Y => - haddr(23)); - - \r.werr_RNO_0\ : OR2A - port map(A => \mexc_0\, B => read, Y => werr_2_m); - - \r.nbo_RNI55HH[1]\ : MX2 - port map(A => \bo[1]\, B => \nbo[1]\, S => retry2_RNILAS7, - Y => N_4259); - - \r.nbo_RNIKPT4J[1]\ : MX2C - port map(A => N_4984, B => N_5016, S => \nbo_5[1]\, Y => - haddr(28)); - - \r.nbo_RNIK2H1J[1]\ : MX2C - port map(A => N_4964, B => N_4996, S => \nbo_5_0[1]\, Y => - haddr(8)); - - \r.bo_RNI13J7[0]\ : MX2C - port map(A => data_2, B => data_0_2, S => \bo_5842_d_0\, Y - => N_467); - - \r.bo_RNIH3KL7[0]\ : NOR2A - port map(A => address_1(3), B => \nbo_5_1[0]\, Y => N_4991); - - \r.bo_RNO_1[1]\ : NOR3C - port map(A => \bo_RNO_2[1]\, B => N_6043, C => - \bo_ns_i_2[1]\, Y => N_6025_i_0); - - \r.bo_RNIFHOG[0]\ : MX2C - port map(A => data_12, B => data_0_12, S => \bo_5842_d_0\, - Y => hwdata_9); - - \r.ba_RNIMHOF1_0\ : NOR2A - port map(A => \ba\, B => iosn_2(93), Y => ba_m); - - \r.hlocken_RNIJ184\ : OR2A - port map(A => lock, B => hlocken, Y => un17_dreq); - - \r.bo_RNIVDPG[0]\ : MX2 - port map(A => data_28, B => data_0_28, S => \bo_5842_d_0\, - Y => hwdata_25); - - \r.bo_RNI1LNP7[0]\ : NOR2A - port map(A => address_1(21), B => \nbo_5_0[0]\, Y => N_5009); - - \r.bo_RNIR99P7[0]\ : MX2C - port map(A => address_0(29), B => address(29), S => - \nbo_5_0[0]\, Y => N_4985); - - \comb.ahb_slv_dec_cache.7.4.un569_dec_hcache_NE_7\ : NOR3B - port map(A => address(29), B => un569_dec_hcache_NE_6, C - => address(28), Y => un569_dec_hcache_NE_7); - - \comb.ahb_slv_dec_cache.6.4.un509_dec_hcache_NE_2\ : NOR2A - port map(A => address(31), B => address(30), Y => - un569_dec_hcache_NE_6); - - \r.hlocken_RNI1BPF\ : OA1B - port map(A => un5_hlock, B => lock, C => \bo_d[2]\, Y => - nbo95); - - \r.bo_RNITDPG[0]\ : MX2C - port map(A => data_19, B => data_0_19, S => \bo_5842_d_0\, - Y => hwdata_16); - - \r.nbo_RNI0Q75B_1[1]\ : NOR2A - port map(A => \nbo_5[1]\, B => \nbo_5[0]\, Y => un19_nbo); - - \r.ba_RNI9NLM\ : XOR2 - port map(A => address_0(2), B => un71_nbo, Y => - \haddr_10_i[2]\); - - \r.bo_RNIPUK3_1[0]\ : OR2A - port map(A => \bo[1]\, B => \bo[0]\, Y => \bo_5842_d\); - - \r.ba_RNI36191\ : NOR2 - port map(A => nbo4_0, B => un11_dreq, Y => nbo4); - - \r.ba_RNI5FIKJ\ : NOR2 - port map(A => \hburst_1_i_0[0]\, B => N_5056, Y => \N_5054\); - - \r.bo_RNILTOG[0]\ : MX2C - port map(A => data_15, B => data_0_15, S => \bo_5842_d\, Y - => hwdata_12); - - \r.bo_RNI59OP7[0]\ : NOR2A - port map(A => address_1(16), B => \nbo_5[0]\, Y => N_5004); - - \r.bo_RNO_9[0]\ : OR2B - port map(A => \nbo_m_0[0]\, B => retry2_RNILAS7, Y => - \nbo_m[0]\); - - \r.bo_RNI518P7[0]\ : MX2C - port map(A => address(10), B => address_0(10), S => - \nbo_5_1[0]\, Y => N_4966); - - \r.bo_RNO_0[1]\ : MX2 - port map(A => \bo[1]\, B => N_6025_i_0, S => iosn_1(93), Y - => N_5940); - - \r.bo_RNI31OP7[0]\ : NOR2A - port map(A => address_1(14), B => \nbo_5_1[0]\, Y => N_5002); - - \r.hlocken_RNI0NOP3\ : OA1C - port map(A => un71_nbo, B => hlocken_1, C => un14_dreq, Y - => htrans_4_sqmuxa_1_0); - - \r.bo_RNI3TNP7[0]\ : NOR2A - port map(A => address_1(23), B => \nbo_5_0[0]\, Y => N_5011); - - \r.nbo_RNIHHT4J[1]\ : MX2C - port map(A => N_4983, B => N_5015, S => \nbo_5[1]\, Y => - haddr(27)); - - \r.bo_RNIP1PG[0]\ : MX2 - port map(A => data_25, B => data_0_25, S => \bo_5842_d_0\, - Y => N_138); - - \r.bo_RNIN1PG[0]\ : MX2C - port map(A => data_16, B => data_0_16, S => \bo_5842_d_0\, - Y => hwdata_13); - - \r.bo_RNI55OP7[0]\ : NOR2A - port map(A => address_1(25), B => \nbo_5_1[0]\, Y => N_5013); - - \r.nbo_RNIV0S4J[1]\ : MX2C - port map(A => N_4977, B => N_5009, S => \nbo_5_0[1]\, Y => - haddr(21)); - - \r.ba_RNIMHOF1\ : OR2B - port map(A => iosn_2(93), B => \ba\, Y => ready_1); - - \r.bo_RNIDNBJ7_0[0]\ : MX2 - port map(A => N_5210_i_0, B => N_4258, S => N_6040_2, Y => - \nbo_5_1[0]\); - - \r.bo_RNI35I6[0]\ : OR2A - port map(A => lock, B => \bo_d[2]\, Y => \bo_RNI35I6[0]\); - - \r.nbo_RNI95T4J[1]\ : MX2C - port map(A => N_4972, B => N_5004, S => \nbo_5[1]\, Y => - haddr(16)); - - \r.nbo_RNITNN3K[1]\ : MX2C - port map(A => N_4958, B => N_4990, S => \nbo_5[1]\, Y => - haddr(2)); - - \comb.un88_nbo_0\ : NOR2B - port map(A => read, B => cache, Y => un88_nbo_0); - - \r.lb_RNO\ : NOR2B - port map(A => rst, B => N_5541, Y => lb_RNO); - - htrans_4_sqmuxa_1_1_RNI1E4C4 : AO1A - port map(A => N_6040_2, B => htrans_4_sqmuxa_1_0, C => - \htrans_4_sqmuxa_1_1\, Y => \htrans_tz[1]\); - - \comb.ahb_slv_dec_cache.hcache\ : OR3C - port map(A => hcache_0, B => un509_dec_hcache_NE, C => - un569_dec_hcache_NE, Y => hcache); - - \r.bg_RNIRDNL1\ : NOR3C - port map(A => req_1, B => bg, C => iosn_0(93), Y => - igrant_0_sqmuxa_1); - - \r.bo_RNI45OP7[0]\ : NOR2A - port map(A => address_1(15), B => \nbo_5_1[0]\, Y => N_5003); - - \r.hcache_RNO\ : OA1 - port map(A => N_5540, B => hcache_1_0, C => rst, Y => - hcache_RNO); - - \r.bg_RNIM7VQC\ : NOR2 - port map(A => dgrant_0_sqmuxa_1, B => \un59_nbo\, Y => - dgrant_0_sqmuxa); - - \r.bg_RNO_0\ : MX2B - port map(A => bg, B => hgrant(0), S => iosn_1(93), Y => - N_5542); - - \r.bo_RNIBD8P7[0]\ : MX2 - port map(A => address_0(13), B => address_1(13), S => - \nbo_5[0]\, Y => N_4969); - - \r.bo_RNI9JJ7[0]\ : MX2C - port map(A => data_6, B => data_0_6, S => \bo_5842_d_0\, Y - => hwdata_3); - - \r.nbo_RNI3LS4J[1]\ : MX2C - port map(A => N_4970, B => N_5002, S => \nbo_5[1]\, Y => - haddr(14)); - - \r.bo_RNIG3KL7[0]\ : NOR2A - port map(A => address_1(2), B => \nbo_5_1[0]\, Y => N_4990); - - \r.bo_RNO_3[0]\ : NOR3C - port map(A => N_6042, B => N_6036, C => \nbo_m[0]\, Y => - \bo_ns_0_2[0]\); - - \r.bo_RNIPUK3[0]\ : OR2A - port map(A => \bo[1]\, B => \bo[0]\, Y => \bo_5842_d_0\); - - un7_haddr_1_SUM2_0 : AX1E - port map(A => address(2), B => address(3), C => address(4), - Y => \N_6093_i\); - - \r.bo_RNIDD8P7[0]\ : MX2 - port map(A => address_0(22), B => address(22), S => - \nbo_5_0[0]\, Y => N_4978); - - \r.nbo_RNIN6H1J[1]\ : MX2C - port map(A => N_4965, B => N_4997, S => \nbo_5_0[1]\, Y => - haddr(9)); - - \r.nbo_RNI0Q75B_2[1]\ : OR2 - port map(A => \nbo_5_0[1]\, B => \nbo_5_1[0]\, Y => - un30_nbo); - - \r.nbo_RNINKR4J[1]\ : MX2C - port map(A => N_4966, B => N_4998, S => \nbo_5_0[1]\, Y => - haddr(10)); - - \r.hlocken_RNI8N97\ : NOR2A - port map(A => req_1, B => hlocken, Y => N_6043_1); - - \r.nbo_RNI8PS4J[1]\ : MX2C - port map(A => N_4980, B => N_5012, S => \nbo_5_0[1]\, Y => - haddr(24)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu_icache is - - port( istate_RNIJCMP6 : out std_logic_vector(0 to 0); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - ics : in std_logic_vector(1 downto 0); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - un1_p0_2_i_4 : out std_logic; - un1_p0_2_i_0 : out std_logic; - ctx_5 : in std_logic; - ctx_4 : in std_logic; - ctx_3 : in std_logic; - ctx_1 : in std_logic; - ctx_0_d0 : in std_logic; - istate_RNI6HPAI : out std_logic_vector(0 to 0); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - istate_RNI57KLB : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - un1_m0_30 : in std_logic; - un1_m0_5 : in std_logic; - un1_m0_9 : in std_logic; - un1_m0_8 : in std_logic; - un1_m0_1 : in std_logic; - un1_m0_22 : in std_logic; - un1_m0_6 : in std_logic; - un1_m0_0 : in std_logic; - un1_m0_17 : in std_logic; - un1_m0_16 : in std_logic; - un1_m0_7 : in std_logic; - un1_m0_4 : in std_logic; - un1_m0_2 : in std_logic; - un1_m0_3 : in std_logic; - istate_RNIH0NBI : out std_logic_vector(0 to 0); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - istate_RNI5V68H : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIEC82C : out std_logic_vector(0 to 0); - maddress_0_2 : in std_logic; - maddress_0_0 : in std_logic; - istate_RNIPSU8G : out std_logic_vector(0 to 0); - diagdata_6 : out std_logic; - diagdata_15 : out std_logic; - diagdata_4 : out std_logic; - diagdata_19 : out std_logic; - diagdata_18 : out std_logic; - diagdata_17 : out std_logic; - diagdata_16 : out std_logic; - diagdata_20 : out std_logic; - diagdata_26 : out std_logic; - diagdata_25 : out std_logic; - diagdata_22 : out std_logic; - diagdata_14 : out std_logic; - diagdata_12 : out std_logic; - diagdata_9 : out std_logic; - diagdata_8 : out std_logic; - diagdata_5 : out std_logic; - diagdata_3 : out std_logic; - diagdata_0 : out std_logic; - diagdata_7 : out std_logic; - diagdata_27 : out std_logic; - diagdata_23 : out std_logic; - diagdata_24 : out std_logic; - diagdata_31 : out std_logic; - diagdata_29 : out std_logic; - diagdata_28 : out std_logic; - diagdata_21 : out std_logic; - diagdata_13 : out std_logic; - diagdata_2 : out std_logic; - diagdata_30 : out std_logic; - diagdata_1 : out std_logic; - hrdata_26 : in std_logic; - hrdata_25 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - rpc_6 : in std_logic; - rpc_5 : in std_logic; - rpc_8 : in std_logic; - rpc_7 : in std_logic; - rpc_2 : in std_logic; - rpc_3 : in std_logic; - rpc_1 : in std_logic; - rpc_0 : in std_logic; - addr : in std_logic_vector(11 downto 2); - data_0 : out std_logic_vector(31 downto 0); - hrdata_0_3 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_15 : in std_logic; - istate_RNIA8N5H : out std_logic_vector(0 to 0); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - vitdatain_0_1_0 : in std_logic_vector(22 to 22); - fault_isid_1_i : in std_logic_vector(0 to 0); - dataout_1 : in std_logic_vector(31 downto 0); - dataout_0 : in std_logic_vector(35 downto 32); - ctx_0_5 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_4 : in std_logic; - address : out std_logic_vector(31 downto 2); - bo_d : in std_logic_vector(3 to 3); - un1_p0_6 : in std_logic_vector(0 to 0); - maddress : in std_logic_vector(31 downto 0); - dataout_2 : in std_logic_vector(31 downto 0); - fpc : in std_logic_vector(31 downto 2); - asi : in std_logic_vector(0 to 0); - un1_p0_2_0 : out std_logic_vector(148 to 148); - su_0 : in std_logic; - diagrdy : out std_logic; - hold_0 : out std_logic; - mexc_0 : out std_logic; - fbranch : in std_logic; - rbranch : in std_logic; - flush2_RNIFMGM2 : out std_logic; - N_425_1 : in std_logic; - flush2_RNI5I3N7 : out std_logic; - N_984 : out std_logic; - N_980 : out std_logic; - N_28 : in std_logic; - N_987 : out std_logic; - N_986 : out std_logic; - e : in std_logic; - flush2 : out std_logic; - N_26 : in std_logic; - flush2_0_0_RNI146O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - mds : out std_logic; - su : out std_logic; - nf : in std_logic; - N_981 : out std_logic; - N_429 : in std_logic; - N_359 : in std_logic; - N_2626 : in std_logic; - N_43 : in std_logic; - N_427 : in std_logic; - N_2625 : in std_logic; - N_6093_i : in std_logic; - N_423 : in std_logic; - N_425 : in std_logic; - N_45 : in std_logic; - N_2623 : in std_logic; - N_365 : in std_logic; - N_357 : in std_logic; - N_985 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_363 : in std_logic; - N_321 : in std_logic; - N_319 : in std_logic; - N_361 : in std_logic; - N_2624 : in std_logic; - N_264_0 : in std_logic; - N_262_0 : in std_logic; - N_78_0 : in std_logic; - inull : in std_logic; - hold : in std_logic; - ldlock_3_0 : in std_logic; - un9_icc_check_bp : in std_logic; - trans_op_0 : out std_logic; - flush_op_i_0 : in std_logic; - un2_m_tlb_type : in std_logic; - stpend_RNI6P41NG3 : in std_logic; - vaddr_1_sqmuxa_0_a2_2 : in std_logic; - ldlock_2 : in std_logic; - xc_exception_1_0 : in std_logic; - grant : in std_logic; - iflush_1_0_a2_0 : in std_logic; - N_121 : in std_logic; - un1_ici : out std_logic; - fault_trans_RNIA0K0D1 : in std_logic; - N_66_0 : in std_logic; - de_hold_pc_1 : in std_logic; - N_425_0 : in std_logic; - flush_0 : out std_logic; - flush : in std_logic; - trans_op : in std_logic; - ba : in std_logic; - hcache : in std_logic; - mexc : in std_logic; - req : out std_logic; - e_0 : in std_logic; - hold_pc_7 : in std_logic; - istate_0_sqmuxa : out std_logic; - flush_i_0 : in std_logic; - N_523 : in std_logic; - ready : in std_logic; - burst_0 : out std_logic; - burst : in std_logic; - rst : in std_logic; - un81_m_tlb_type : in std_logic; - holdn : out std_logic; - cdwrite_0_sqmuxa_i_0_0 : out std_logic; - N_66 : in std_logic; - enable : in std_logic; - lclk_c : in std_logic - ); - -end mmu_icache; - -architecture DEF_ARCH of mmu_icache is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \faddr_RNID788NI[6]\, idle_0, \istate[1]\, - \istate[0]\, diagen_0_sqmuxa_0, error_1_sqmuxa_0, - un5_m_en, N_1320, istate_1259_d_0, vaddress_0_sqmuxa_1, - un2_eholdn, vaddress_0_sqmuxa_0, holdn_RNIFCHA, N_20, - \faddr[1]\, \faddr[0]\, N_12, \faddr[3]\, - \DWACT_FINC_E[0]\, req_7_m, req_7, req_0_sqmuxa, - un1_ici_10_i_0, un1_ici_11_i_0, burst_1, burst_1_iv_0, - hit_1_6, burst_5_m, burst_2_m, req_1_0, N_1201, - \istate_ns_0_1[1]\, \istate_ns_0_0[1]\, underrun_1_sqmuxa, - N_1350, N_1348, trans_op_1_2, trans_op_1_0, - trans_op_RNO_4, trans_op_RNO_5, trans_op_0_a3_0, req_7_1, - un1_mcio_1_i_0, underrun_1_0, underrun2, overrun_4, - overrun_4_0, underrun, un1_ici_0, un1_mcio_4_0, overrun, - un2_eholdn_0_0, un2_eholdn_0, \istate_ns_0_0[0]\, - istate_0_sqmuxa_0_a3_m6_5, istate_0_sqmuxa_0_a3_m6_3, - un5_eholdn, istate_0_sqmuxa_0_a3_m6_1, - istate_0_sqmuxa_0_a3_m2_e, burst_5_m_0, twrite_3_iv_4, - twrite_3_iv_2, cacheon_1, twrite_3_iv_0, hit_RNIR2PJ, - cache, un1_mcio_1_0, hit_1_18, hit_1_10, hit_1_9, - hit_1_16, hit_1_17, hit_1_8, hit_1_7, hit_1_13, hit_1_2, - hit_1_1, hit_1_12, un1_ici_9_i_0, un1_ici_8_i_0, - un1_ici_5_i_0, un1_ici_4_i_0, hit_1_4, hit_1_0, - un1_ici_18_i_0, un1_ici_15_i_0, un1_ici_13_i_0, - un1_ici_7_i_0, un1_ici_3_i_0, un1_ici_0_i_0, - un1_icramo_NE_5, un1_icramo_5_i, un1_icramo_4_i, - un1_icramo_NE_3, un1_icramo_NE_4, un1_icramo_1_0_i, - un1_icramo_0_i, un1_icramo_NE_1, un1_icramo_7_i, - un1_icramo_3_i, taddr_1_sqmuxa_0, N_1346_1, - taddr_9_sn_m2_1, taddr_0_sqmuxa, \cdwrite_4_m_0[0]\, - twrite_3, underrun_1, N_1372, underrun_2, N_1312, N_1331, - overrun_0, un2_m_en, flush2_0_sqmuxa, valid_1, hit_1, - un1_icramo_1, \un1_p0_2_0[148]\, \faddr[6]\, I_31_0, - ctwrite_0_sqmuxa_1, N_1163_i, \istate_li[0]\, - \un4_validv[7]\, istate_5, burst_2_sqmuxa, N_1310, - \istate_0_sqmuxa\, trans_op_RNO_0, trans_op_0_a2_0, - trans_op_RNO, trans_op_RNO_2, hit, un1_dco_1, CO1, - \vaddress[3]\, \vaddress[2]\, N_971, \vaddress[15]\, - \un1_ici\, N_1121, N_1143, taddr_0_sqmuxa_1, - \cdwrite_0_sqmuxa_i_0_0\, N_969, \vaddress[13]\, idle, - istate_1259_d, N_973, \vaddress[17]\, N_974, - \vaddress[18]\, N_1122, N_1144, N_1042, N_1050, N_1063, - N_1064, N_1065, N_1066, \waddress_1[5]\, \waddress_1[13]\, - \waddress_1[26]\, \waddress_1[27]\, \waddress_1[28]\, - \waddress_1[29]\, N_1043, N_1046, \waddress_1[4]\, N_1041, - \waddress_1[6]\, \waddress_1[9]\, \vaddress_1[2]\, - \vaddress_4_i[2]\, \vaddress[26]\, \vaddress[27]\, - \vaddress[29]\, N_1052, N_1068, \waddress_1[15]\, - \waddress_1[31]\, N_1049, \waddress_1[12]\, N_1051, - N_1055, N_1056, \waddress_1[14]\, \waddress_1[18]\, - \waddress_1[19]\, N_1124, N_1146, \vaddress[5]\, - \taddr_9[5]\, \vaddress_1[3]\, \vaddress_4[3]\, - \un95_res[6]\, \address[3]\, \address[4]\, \un95_res[1]\, - \address[2]\, \un95_res[0]\, \un95_res[5]\, \un95_res[2]\, - \un95_res[3]\, \un95_res[4]\, \un95_res[7]\, - \waddress_4[2]\, \waddress_1[2]\, N_1039, error_1_sqmuxa, - \waddress_1[17]\, N_1054, \waddress_1[16]\, N_1053, - \waddress_1[8]\, N_1045, \waddress_4[4]\, - \waddress_1[20]\, N_1057, \waddress_1[24]\, N_1061, - \waddress_1[21]\, N_1058, \waddress_1[30]\, N_1067, - \waddress_1[25]\, N_1062, \waddress_1[23]\, N_1060, - \waddress_1[22]\, N_1059, \istate_nss[1]\, - istate_1_sqmuxa, overrun_1, holdn_1_i, holdn_RNO, - holdn_0_sqmuxa_1, \req\, N_1213, underrun_RNO, - vaddress_0_sqmuxa, N_970, \vaddress[14]\, N_978, - \vaddress[22]\, diagen_0_sqmuxa, \vaddress[25]\, - error_0_sqmuxa_1, un5_mds, \istate_RNI21Q02[0]\, - \waddress_1[3]\, N_1040, \waddress_4[3]\, N_1012, - \valid[2]\, N_1015, \valid[5]\, \vmask_6[2]\, N_1022, - N_1028_i, \vmask_6[5]\, N_1025, N_1011, \valid[1]\, - N_1013, \valid[3]\, N_1017, \valid[7]\, \vmask_6[1]\, - N_1021, \vmask_6[3]\, N_1023, \vmask_6[7]\, N_1027, - N_1102, \vmask_6[0]\, N_1103, N_1104, N_1105, N_1107, - N_1109, \valid_1[3]\, N_1123, N_1145, \vaddress[4]\, - cdwrite_0_sqmuxa_i_0, N_968, \vaddress[12]\, N_979, - \vaddress[23]\, N_972, \vaddress[16]\, N_1125, - \taddr_9[6]\, N_1147, N_1010, \valid[0]\, N_1014, - \valid[4]\, N_1020, \vmask_6[4]\, N_1024, N_1106, N_1130, - N_1152, \vaddress[11]\, \taddr_9[11]\, \faddr_1[0]\, - \faddr_1[1]\, I_5_0, \faddr_1[2]\, I_9_0, \faddr_1[3]\, - \flush2\, I_13_4, \faddr_1[4]\, I_20_0, \faddr_1[5]\, - I_24_0, \faddr_1[6]\, N_1047, \waddress_1[10]\, N_1128, - N_1150, \vaddress[9]\, \taddr_9[9]\, \faddr[4]\, - \vaddress_1[4]\, \vaddress_4[4]\, \vaddress[30]\, - \vaddress[31]\, N_1048, \waddress_1[11]\, N_1129, N_1151, - \vaddress[10]\, \taddr_9[10]\, \faddr[5]\, N_976, - \vaddress[20]\, N_1044, \waddress_1[7]\, N_1126, - \vaddress[6]\, N_1148, \vaddress[7]\, \taddr_9[7]\, - \faddr[2]\, N_964, N_965, N_963, N_962, \vaddress[24]\, - \flush_0\, N_975, \vaddress[19]\, N_977, \vaddress[21]\, - \vaddress[28]\, flush_RNO, N_1214, cache_RNO, N_1203, - N_1317, N_1333, \taddr_9[8]\, N_1149, N_1127, - \vaddress[8]\, pflushr_1_sqmuxa_1, N_960, N_961, hit_RNO, - N_1215, \valid_1[5]\, \valid_1[4]\, \valid_1[2]\, - \valid_1[0]\, \valid_1[7]\, \valid_1[1]\, N_1108, - \vmask_6[6]\, valid_1_sqmuxa, \istate_nss[0]\, N_1345, - N_1212, overrun_RNO, N_1016, \valid[6]\, N_1026, - \valid_1[6]\, N_1202, \burst_0\, burst_RNO_0, N_1230_i, - \su\, \hold_0\, \trans_op_0\, \address[5]\, \address[6]\, - \address[7]\, \address[8]\, \address[9]\, \address[10]\, - \address[11]\, \address[12]\, \address[13]\, - \address[14]\, \address[15]\, \address[16]\, - \address[17]\, \address[18]\, \address[19]\, - \address[20]\, \address[21]\, \address[22]\, - \address[23]\, \address[24]\, \address[25]\, - \address[26]\, \address[27]\, \address[28]\, - \address[29]\, \address[30]\, \address[31]\, N_4, - \DWACT_FINC_E[1]\, N_9, N_17, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - address(31) <= \address[31]\; - address(30) <= \address[30]\; - address(29) <= \address[29]\; - address(28) <= \address[28]\; - address(27) <= \address[27]\; - address(26) <= \address[26]\; - address(25) <= \address[25]\; - address(24) <= \address[24]\; - address(23) <= \address[23]\; - address(22) <= \address[22]\; - address(21) <= \address[21]\; - address(20) <= \address[20]\; - address(19) <= \address[19]\; - address(18) <= \address[18]\; - address(17) <= \address[17]\; - address(16) <= \address[16]\; - address(15) <= \address[15]\; - address(14) <= \address[14]\; - address(13) <= \address[13]\; - address(12) <= \address[12]\; - address(11) <= \address[11]\; - address(10) <= \address[10]\; - address(9) <= \address[9]\; - address(8) <= \address[8]\; - address(7) <= \address[7]\; - address(6) <= \address[6]\; - address(5) <= \address[5]\; - address(4) <= \address[4]\; - address(3) <= \address[3]\; - address(2) <= \address[2]\; - un1_p0_2_0(148) <= \un1_p0_2_0[148]\; - hold_0 <= \hold_0\; - flush2 <= \flush2\; - su <= \su\; - trans_op_0 <= \trans_op_0\; - un1_ici <= \un1_ici\; - flush_0 <= \flush_0\; - req <= \req\; - istate_0_sqmuxa <= \istate_0_sqmuxa\; - burst_0 <= \burst_0\; - cdwrite_0_sqmuxa_i_0_0 <= \cdwrite_0_sqmuxa_i_0_0\; - - \r.vaddress_RNIJG6QR7[4]\ : MX2C - port map(A => N_1145, B => N_1123, S => N_1163_i, Y => - vaddress_RNIJG6QR7(4)); - - \r.vaddress_RNI1CS1SD[10]\ : MX2C - port map(A => N_1151, B => N_1129, S => N_1163_i, Y => - \taddr_9[10]\); - - \r.waddress_RNO_0[5]\ : MX2C - port map(A => \address[5]\, B => fpc(5), S => - vaddress_0_sqmuxa_0, Y => N_1042); - - \r.valid_RNIITEC[0]\ : AOI1 - port map(A => hit, B => \valid[0]\, C => \un95_res[0]\, Y - => N_1010); - - \ictrl.hit_1_9\ : XA1A - port map(A => fpc(29), B => dataout_2(25), C => - un1_ici_18_i_0, Y => hit_1_9); - - \r.waddress_RNO[12]\ : MX2C - port map(A => N_1049, B => N_2623, S => error_1_sqmuxa_0, Y - => \waddress_1[12]\); - - \r.vaddress_RNITQAN[14]\ : MX2C - port map(A => \vaddress[14]\, B => maddress(14), S => - diagen_0_sqmuxa_0, Y => N_970); - - \r.su_RNIA1LEG1\ : OR3C - port map(A => fault_isid_1_i(0), B => un2_m_en, C => - fault_trans_RNIA0K0D1, Y => un5_m_en); - - \r.underrun_RNO_0\ : MX2 - port map(A => underrun_1, B => underrun, S => istate_1259_d, - Y => N_1213); - - \r.req_RNO\ : OA1 - port map(A => istate_1_sqmuxa, B => req_1_0, C => rst, Y - => N_1230_i); - - \r.istate_RNIRASC8[0]\ : MX2 - port map(A => hrdata_24, B => maddress(29), S => idle_0, Y - => istate_RNIRASC8(0)); - - \r.flush2_RNI5I3N7\ : MX2C - port map(A => pflushr_1_sqmuxa_1, B => N_425_1, S => - ctwrite_0_sqmuxa_1, Y => flush2_RNI5I3N7); - - \r.flush2_0_0_RNIRN5O2\ : NOR2A - port map(A => N_1103, B => \un1_p0_2_0[148]\, Y => - un1_p0_2_i_0); - - \ictrl.0.un1_ici_9_0\ : XNOR2 - port map(A => dataout_2(17), B => fpc(21), Y => - un1_ici_9_i_0); - - \r.vaddress_RNI1BBN[30]\ : MX2 - port map(A => \vaddress[30]\, B => maddress(30), S => - diagen_0_sqmuxa, Y => N_986); - - \r.istate_RNIEOB8D[0]\ : NOR2 - port map(A => grant, B => istate_1259_d, Y => req_0_sqmuxa); - - \ictrl.0.un1_icramo_NE_1\ : XA1A - port map(A => ctx_0_0, B => dataout_1(30), C => - un1_icramo_3_i, Y => un1_icramo_NE_1); - - \r.waddress_RNO_1[2]\ : XNOR2 - port map(A => ready, B => \address[2]\, Y => - \waddress_4[2]\); - - \r.waddress[6]\ : DFN1 - port map(D => \waddress_1[6]\, CLK => lclk_c, Q => - \address[6]\); - - \r.vaddress_RNII112ND[10]\ : MX2C - port map(A => rpc_8, B => \vaddress[10]\, S => - taddr_0_sqmuxa_1, Y => N_1151); - - \r.trans_op_RNO_1\ : NOR3C - port map(A => trans_op_1_0, B => trans_op_RNO_4, C => - trans_op_RNO_5, Y => trans_op_1_2); - - \r.req\ : DFN1 - port map(D => N_1230_i, CLK => lclk_c, Q => \req\); - - \r.istate_RNIP0SCH[0]\ : MX2 - port map(A => hrdata_0_23, B => dataout_1(23), S => - istate_1259_d, Y => data_0(23)); - - \r.istate_RNI3MVI[0]\ : MX2 - port map(A => fpc(7), B => addr(7), S => diagen_0_sqmuxa, Y - => N_1126); - - \r.valid_RNIKTEC[2]\ : AOI1 - port map(A => hit, B => \valid[2]\, C => \un95_res[2]\, Y - => N_1012); - - \r.vaddress_RNIG9T9T8[5]\ : MX2C - port map(A => N_1146, B => N_1124, S => N_1163_i, Y => - \taddr_9[5]\); - - \r.istate_RNI0L69F[0]\ : MX2 - port map(A => hrdata_0_21, B => dataout_1(21), S => - istate_1259_d_0, Y => data_0(21)); - - \r.faddr[5]\ : DFN1E1 - port map(D => \faddr_1[5]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[5]\); - - \ictrl.un2_eholdn_0\ : NOR2A - port map(A => hold, B => inull, Y => un2_eholdn_0); - - \r.istate_RNITUH12[0]\ : MX2 - port map(A => hrdata_0_13, B => dataout_1(13), S => - istate_1259_d, Y => data_0(13)); - - \r.req_RNO_1\ : MX2 - port map(A => \req\, B => req_7, S => req_0_sqmuxa, Y => - N_1201); - - \r.vaddress[14]\ : DFN1E1 - port map(D => fpc(14), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[14]\); - - \r.vaddress[11]\ : DFN1E1 - port map(D => fpc(11), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[11]\); - - \r.istate_RNO_0[1]\ : NOR2B - port map(A => \istate_ns_0_0[1]\, B => underrun_1_sqmuxa, Y - => \istate_ns_0_1[1]\); - - \r.istate_RNIV5VI[0]\ : MX2C - port map(A => fpc(5), B => addr(5), S => diagen_0_sqmuxa_0, - Y => N_1124); - - \r.istate_RNIEC82C[0]\ : MX2 - port map(A => hrdata_0_d0, B => maddress(5), S => idle_0, Y - => istate_RNIEC82C(0)); - - \r.vaddress_RNIJ5GUFB[8]\ : MX2C - port map(A => rpc_6, B => \vaddress[8]\, S => - taddr_0_sqmuxa_1, Y => N_1149); - - \r.istate_RNIK9NF8[0]\ : MX2 - port map(A => hrdata_0_16, B => maddress(16), S => idle, Y - => istate_RNIK9NF8(0)); - - \r.istate_RNIEON21_25[0]\ : MX2 - port map(A => dataout_2(3), B => dataout_1(3), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_3); - - \ictrl.0.un1_icramo_3_0\ : XNOR2 - port map(A => dataout_1(31), B => ctx_3, Y => - un1_icramo_3_i); - - \r.istate_RNIEON21_22[0]\ : MX2 - port map(A => dataout_2(17), B => dataout_1(21), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_21); - - \r.vaddress_RNO_0[2]\ : XOR2 - port map(A => ready, B => \vaddress[2]\, Y => - \vaddress_4_i[2]\); - - \r.faddr_RNO[2]\ : NOR2B - port map(A => \flush2\, B => I_9_0, Y => \faddr_1[2]\); - - \r.faddr_RNO[5]\ : NOR2B - port map(A => \flush2\, B => I_24_0, Y => \faddr_1[5]\); - - \r.waddress_RNO[14]\ : MX2C - port map(A => N_1051, B => N_45, S => error_1_sqmuxa_0, Y - => \waddress_1[14]\); - - \r.flush2_RNI1R3J2\ : OA1B - port map(A => N_1346_1, B => underrun2, C => istate_1259_d, - Y => taddr_0_sqmuxa_1); - - \r.valid[1]\ : DFN1E0 - port map(D => \valid_1[1]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[1]\); - - \ictrl.0.un1_ici_7_0\ : XNOR2 - port map(A => dataout_2(15), B => fpc(19), Y => - un1_ici_7_i_0); - - \r.valid_RNO[3]\ : MX2 - port map(A => \vmask_6[3]\, B => dataout_2(3), S => - twrite_3, Y => \valid_1[3]\); - - \r.vaddress_RNI1RAN[16]\ : MX2C - port map(A => \vaddress[16]\, B => maddress(16), S => - diagen_0_sqmuxa, Y => N_972); - - \r.istate_RNI9L8J1[0]\ : MX2 - port map(A => hrdata_0_26, B => dataout_1(26), S => - istate_1259_d_0, Y => data_0(26)); - - \r.hit_RNIR2PJ\ : OR2 - port map(A => hit, B => un1_dco_1, Y => hit_RNIR2PJ); - - \ictrl.un1_ici_0\ : OA1A - port map(A => maddress(21), B => N_523, C => flush_i_0, Y - => un1_ici_0); - - \un1_r.faddr_I_23\ : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \faddr[3]\, C => - \faddr[4]\, Y => N_9); - - \r.vaddress_RNI73BN[26]\ : MX2C - port map(A => \vaddress[26]\, B => maddress(26), S => - diagen_0_sqmuxa_0, Y => N_982); - - \r.vaddress_RNI2GAKMI[17]\ : NOR2 - port map(A => \un1_ici\, B => N_973, Y => - vaddress_RNI2GAKMI(17)); - - \ictrl.0.un1_ici_10_0\ : XNOR2 - port map(A => fpc(22), B => dataout_2(18), Y => - un1_ici_10_i_0); - - \ictrl.un1_ici\ : AO1C - port map(A => N_121, B => iflush_1_0_a2_0, C => un1_ici_0, - Y => \un1_ici\); - - \r.istate_RNIEON21_11[0]\ : MX2 - port map(A => dataout_2(8), B => dataout_1(12), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_12); - - \r.waddress[20]\ : DFN1 - port map(D => \waddress_1[20]\, CLK => lclk_c, Q => - \address[20]\); - - \r.vaddress_RNIQBKPKB[8]\ : MX2C - port map(A => N_1149, B => N_1127, S => N_1163_i, Y => - \taddr_9[8]\); - - \r.istate_RNIEON21_8[0]\ : MX2 - port map(A => dataout_2(10), B => dataout_1(14), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_14); - - \ictrl.valid_1_6\ : MX2C - port map(A => N_963, B => N_964, S => fpc(3), Y => N_965); - - \r.istate_RNIDP0S8[0]\ : MX2 - port map(A => hrdata_0_11, B => dataout_1(11), S => - istate_1259_d_0, Y => data_0(11)); - - \un1_r.faddr_I_24\ : XOR2 - port map(A => N_9, B => \faddr[5]\, Y => I_24_0); - - \r.waddress[24]\ : DFN1 - port map(D => \waddress_1[24]\, CLK => lclk_c, Q => - \address[24]\); - - \ictrl.valid_1_3\ : MX2C - port map(A => N_960, B => N_961, S => fpc(3), Y => N_962); - - \ictrl.0.un1_ici_10_0_RNISL5R7\ : NOR3C - port map(A => hit_1_18, B => hit_1_17, C => un1_icramo_1, Y - => hit_1); - - \r.vaddress_RNIKA3VM7[4]\ : MX2C - port map(A => rpc_2, B => \vaddress[4]\, S => - taddr_0_sqmuxa_1, Y => N_1145); - - \r.istate_RNIJGCD_1[0]\ : OR2A - port map(A => \istate[1]\, B => \istate[0]\, Y => - istate_1259_d_0); - - \r.valid[2]\ : DFN1E0 - port map(D => \valid_1[2]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[2]\); - - \r.vaddress_RNISNKBT9[6]\ : MX2C - port map(A => N_1147, B => N_1125, S => N_1163_i, Y => - \taddr_9[6]\); - - \r.req_RNIECCP1\ : OR2 - port map(A => ready, B => \req\, Y => underrun2); - - \r.cache_RNO\ : OA1A - port map(A => holdn_0_sqmuxa_1, B => N_1203, C => - \istate_0_sqmuxa\, Y => cache_RNO); - - \r.valid_RNO[4]\ : MX2A - port map(A => \vmask_6[4]\, B => dataout_2(4), S => - twrite_3, Y => \valid_1[4]\); - - \r.burst_RNO_1\ : OR3C - port map(A => burst_2_sqmuxa, B => \istate_li[0]\, C => - N_1310, Y => istate_5); - - \r.waddress_RNO[19]\ : MX2C - port map(A => N_1056, B => un1_m0_17, S => error_1_sqmuxa_0, - Y => \waddress_1[19]\); - - \r.su\ : DFN1E1 - port map(D => su_0, CLK => lclk_c, E => idle, Q => \su\); - - \r.waddress_RNO_0[17]\ : MX2C - port map(A => \address[17]\, B => fpc(17), S => - vaddress_0_sqmuxa_0, Y => N_1054); - - \r.vaddress[7]\ : DFN1E1 - port map(D => fpc(7), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[7]\); - - \ictrl.hit_1_4\ : XA1A - port map(A => fpc(18), B => dataout_2(14), C => - un1_ici_7_i_0, Y => hit_1_4); - - \r.waddress_RNI3LUL[4]\ : AO1D - port map(A => dataout_2(0), B => \un95_res[0]\, C => - cacheon_1, Y => N_1020); - - \r.vaddress[16]\ : DFN1E1 - port map(D => fpc(16), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[16]\); - - \r.istate_RNIEON21_9[0]\ : MX2 - port map(A => dataout_0(35), B => dataout_1(9), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_9); - - \r.istate_RNI34LKA[0]\ : MX2 - port map(A => hrdata_0_4, B => dataout_1(4), S => - istate_1259_d, Y => data_0(4)); - - \r.istate_RNI1L08M[0]\ : MX2 - port map(A => hrdata_26, B => dataout_2(31), S => - istate_1259_d_0, Y => data_0(31)); - - \r.holdn_RNO_0\ : MX2 - port map(A => overrun_1, B => N_1312, S => - underrun_1_sqmuxa, Y => holdn_1_i); - - \r.vaddress[12]\ : DFN1E1 - port map(D => fpc(12), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[12]\); - - \r.overrun_RNILCS93\ : AOI1B - port map(A => taddr_1_sqmuxa_0, B => overrun, C => - taddr_0_sqmuxa, Y => taddr_9_sn_m2_1); - - \r.waddress_RNO_1[3]\ : AX1 - port map(A => ready, B => \address[2]\, C => \address[3]\, - Y => \waddress_4[3]\); - - \r.valid_RNIN7DS1[3]\ : MX2C - port map(A => N_1013, B => N_1023, S => N_1028_i, Y => - \vmask_6[3]\); - - \r.vaddress_RNIDOSVU5[2]\ : MX2C - port map(A => rpc_0, B => \vaddress[2]\, S => - taddr_0_sqmuxa_1, Y => N_1143); - - \r.faddr_RNID788NI[6]\ : NOR3B - port map(A => rst, B => vitdatain_0_1_0(22), C => - flush2_0_sqmuxa, Y => \faddr_RNID788NI[6]\); - - \ictrl.0.un1_ici_13_0\ : XNOR2 - port map(A => dataout_2(21), B => fpc(25), Y => - un1_ici_13_i_0); - - \r.waddress_RNO[10]\ : MX2C - port map(A => N_1047, B => un1_m0_8, S => error_1_sqmuxa, Y - => \waddress_1[10]\); - - \r.faddr_RNIDN2CUE[6]\ : MX2A - port map(A => \taddr_9[11]\, B => \faddr[6]\, S => - \un1_p0_2_0[148]\, Y => faddr_RNIDN2CUE(6)); - - \r.trans_op_RNO_4\ : OR3A - port map(A => un81_m_tlb_type, B => un2_m_tlb_type, C => - flush, Y => trans_op_RNO_4); - - \r.waddress_RNIQKIL1[4]\ : OR2A - port map(A => un1_mcio_1_0, B => ready, Y => un1_mcio_1_i_0); - - \r.overrun_RNIMIJOU\ : NOR2A - port map(A => un2_eholdn, B => overrun, Y => overrun_0); - - \r.waddress[9]\ : DFN1 - port map(D => \waddress_1[9]\, CLK => lclk_c, Q => - \address[9]\); - - \r.flush2_RNI4S946\ : OA1B - port map(A => diagen_0_sqmuxa, B => twrite_3, C => \flush2\, - Y => pflushr_1_sqmuxa_1); - - \r.waddress_RNI3LUL_0[4]\ : OA1B - port map(A => \un95_res[1]\, B => dataout_2(1), C => - cacheon_1, Y => N_1021); - - \ictrl.v.burst_1_iv_RNO_4\ : OR3C - port map(A => fpc(3), B => fpc(2), C => fpc(4), Y => - \un4_validv[7]\); - - \un1_r.faddr_I_12\ : AND3 - port map(A => \faddr[0]\, B => \faddr[1]\, C => \faddr[2]\, - Y => N_17); - - \ictrl.valid_1_5\ : MX2 - port map(A => dataout_2(3), B => dataout_2(7), S => fpc(4), - Y => N_964); - - \r.flush_RNI41ED\ : XA1C - port map(A => fpc(13), B => dataout_2(9), C => \flush_0\, Y - => hit_1_0); - - \r.waddress_RNO_0[31]\ : MX2C - port map(A => \address[31]\, B => fpc(31), S => - vaddress_0_sqmuxa_0, Y => N_1068); - - \r.underrun_RNITDT4J1\ : MX2C - port map(A => error_0_sqmuxa_1, B => un5_mds, S => - \istate_RNI21Q02[0]\, Y => mds); - - \r.istate_RNI57KLB[0]\ : MX2 - port map(A => hrdata_0_3, B => maddress_0_2, S => idle, Y - => istate_RNI57KLB(0)); - - \r.vaddress[24]\ : DFN1E1 - port map(D => fpc(24), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[24]\); - - \r.waddress[11]\ : DFN1 - port map(D => \waddress_1[11]\, CLK => lclk_c, Q => - \address[11]\); - - \r.vaddress[21]\ : DFN1E1 - port map(D => fpc(21), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[21]\); - - \r.trans_op_RNO\ : NOR3C - port map(A => trans_op_RNO_0, B => trans_op_1_2, C => - trans_op_RNO_2, Y => trans_op_RNO); - - \r.flush_RNO_0\ : MX2 - port map(A => \flush2\, B => \flush_0\, S => N_1317, Y => - N_1214); - - \r.valid_RNISF2H2[5]\ : MX2A - port map(A => \vmask_6[5]\, B => maddress(5), S => - diagen_0_sqmuxa_0, Y => N_1107); - - \r.underrun_RNI7JVF01\ : AO1A - port map(A => un1_mcio_4_0, B => un2_eholdn, C => underrun, - Y => underrun_2); - - \r.waddress_RNIB452[4]\ : NOR2B - port map(A => \address[3]\, B => \address[4]\, Y => - un1_mcio_1_0); - - \r.istate_RNIDOS1V_1[0]\ : NOR2A - port map(A => idle_0, B => un2_eholdn, Y => - vaddress_0_sqmuxa_0); - - \r.trans_op_RNO_0\ : OR3C - port map(A => vaddr_1_sqmuxa_0_a2_2, B => trans_op_0_a2_0, - C => stpend_RNI6P41NG3, Y => trans_op_RNO_0); - - \r.istate_RNO[1]\ : OA1A - port map(A => \istate_ns_0_1[1]\, B => istate_1_sqmuxa, C - => rst, Y => \istate_nss[1]\); - - \r.underrun_RNI7JVF01_0\ : NOR2 - port map(A => overrun_4_0, B => overrun_0, Y => overrun_4); - - \r.holdn_RNIFCHA\ : OR2B - port map(A => \hold_0\, B => hold, Y => holdn_RNIFCHA); - - \r.waddress_RNO_0[6]\ : MX2C - port map(A => \address[6]\, B => fpc(6), S => - vaddress_0_sqmuxa_0, Y => N_1043); - - \ictrl.0.un1_ici_0_0\ : XNOR2 - port map(A => dataout_2(8), B => fpc(12), Y => - un1_ici_0_i_0); - - \r.valid_RNIOTEC[6]\ : AO1 - port map(A => hit, B => \valid[6]\, C => \un95_res[6]\, Y - => N_1016); - - \r.waddress_RNO_0[24]\ : MX2C - port map(A => \address[24]\, B => fpc(24), S => - vaddress_0_sqmuxa_1, Y => N_1061); - - \r.waddress_RNO[21]\ : MX2C - port map(A => N_1058, B => N_427, S => error_1_sqmuxa, Y - => \waddress_1[21]\); - - \r.valid_RNO[2]\ : MX2 - port map(A => \vmask_6[2]\, B => dataout_2(2), S => - twrite_3, Y => \valid_1[2]\); - - \r.istate_RNIPSU8G[0]\ : MX2 - port map(A => hrdata_0_1, B => maddress_0_0, S => idle_0, Y - => istate_RNIPSU8G(0)); - - \r.waddress_RNI3LUL_3[4]\ : OA1B - port map(A => \un95_res[5]\, B => dataout_2(5), C => - cacheon_1, Y => N_1025); - - \r.istate_RNI21Q02[0]\ : NOR2 - port map(A => ready, B => istate_1259_d, Y => - \istate_RNI21Q02[0]\); - - \ictrl.0.un1_icramo_4_0\ : XNOR2 - port map(A => dataout_0(32), B => ctx_4, Y => - un1_icramo_4_i); - - \r.vaddress[8]\ : DFN1E1 - port map(D => fpc(8), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[8]\); - - \r.burst\ : DFN1 - port map(D => burst_RNO_0, CLK => lclk_c, Q => \burst_0\); - - \un1_r.faddr_I_13\ : XOR2 - port map(A => N_17, B => \faddr[3]\, Y => I_13_4); - - \r.overrun_RNI28484\ : OR3B - port map(A => \istate_li[0]\, B => taddr_9_sn_m2_1, C => - diagen_0_sqmuxa_0, Y => N_1163_i); - - \un1_r.faddr_I_9\ : XOR2 - port map(A => N_20, B => \faddr[2]\, Y => I_9_0); - - un11_xaddr_inc_1_CO1 : OR2B - port map(A => \vaddress[3]\, B => \vaddress[2]\, Y => CO1); - - \r.waddress[12]\ : DFN1 - port map(D => \waddress_1[12]\, CLK => lclk_c, Q => - \address[12]\); - - \ictrl.0.un1_icramo_NE_5\ : NOR3C - port map(A => un1_icramo_5_i, B => un1_icramo_4_i, C => - un1_icramo_NE_3, Y => un1_icramo_NE_5); - - \ictrl.0.un1_ici_15_0\ : XNOR2 - port map(A => dataout_2(23), B => fpc(27), Y => - un1_ici_15_i_0); - - \r.waddress_RNO_0[2]\ : MX2C - port map(A => \waddress_4[2]\, B => fpc(2), S => - vaddress_0_sqmuxa_0, Y => N_1039); - - \r.waddress_RNO[17]\ : MX2C - port map(A => N_1054, B => N_425, S => error_1_sqmuxa, Y - => \waddress_1[17]\); - - \ictrl.0.un1_ici_10_0_RNIA8AL\ : NOR3C - port map(A => un1_ici_9_i_0, B => un1_ici_8_i_0, C => - hit_1_6, Y => hit_1_13); - - \r.valid[5]\ : DFN1E0 - port map(D => \valid_1[5]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[5]\); - - \r.vaddress_RNI3RAN[17]\ : MX2C - port map(A => \vaddress[17]\, B => maddress(17), S => - diagen_0_sqmuxa_0, Y => N_973); - - \r.valid_RNIP7DS1[5]\ : MX2C - port map(A => N_1015, B => N_1025, S => N_1028_i, Y => - \vmask_6[5]\); - - \r.valid_RNIK7DS1[0]\ : MX2C - port map(A => N_1010, B => N_1020, S => N_1028_i, Y => - \vmask_6[0]\); - - GND_i : GND - port map(Y => \GND\); - - \r.waddress_RNO_0[20]\ : MX2C - port map(A => \address[20]\, B => fpc(20), S => - vaddress_0_sqmuxa_1, Y => N_1057); - - \r.istate_RNIJGCD[0]\ : OR2B - port map(A => \istate[1]\, B => \istate[0]\, Y => - \istate_li[0]\); - - \r.flush_RNIPE0E5\ : OR2A - port map(A => twrite_3_iv_4, B => ready, Y => twrite_3); - - \r.flush2_0_0\ : DFN1 - port map(D => \faddr_RNID788NI[6]\, CLK => lclk_c, Q => - \un1_p0_2_0[148]\); - - \r.waddress[15]\ : DFN1 - port map(D => \waddress_1[15]\, CLK => lclk_c, Q => - \address[15]\); - - \r.vaddress_RNIQFAKMI[13]\ : NOR2 - port map(A => \un1_ici\, B => N_969, Y => - vaddress_RNIQFAKMI(13)); - - \r.istate_RNIJSOBE[0]\ : MX2 - port map(A => hrdata_23, B => maddress(28), S => idle_0, Y - => istate_RNIJSOBE(0)); - - \r.waddress_RNO_0[23]\ : MX2C - port map(A => \address[23]\, B => fpc(23), S => - vaddress_0_sqmuxa_1, Y => N_1060); - - \r.valid[7]\ : DFN1E0 - port map(D => \valid_1[7]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[7]\); - - \r.flush_RNICAO491\ : OR2A - port map(A => vaddress_0_sqmuxa_1, B => un5_eholdn, Y => - holdn_0_sqmuxa_1); - - \r.vaddress_RNIQNAKMI[20]\ : NOR2 - port map(A => \un1_ici\, B => N_976, Y => - vaddress_RNIQNAKMI(20)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.waddress_RNIFG73_4[4]\ : NOR3A - port map(A => \address[4]\, B => \address[2]\, C => - \address[3]\, Y => \un95_res[4]\); - - \ictrl.hit_1_7\ : XA1A - port map(A => fpc(24), B => dataout_2(20), C => - un1_ici_13_i_0, Y => hit_1_7); - - \r.vaddress_RNO_0[4]\ : AX1D - port map(A => CO1, B => ready, C => \vaddress[4]\, Y => - \vaddress_4[4]\); - - \r.istate_RNIN6957[0]\ : MX2 - port map(A => hrdata_0_12, B => maddress(12), S => idle_0, - Y => istate_RNIN6957(0)); - - \r.waddress_RNO[22]\ : MX2C - port map(A => N_1059, B => N_429, S => error_1_sqmuxa, Y - => \waddress_1[22]\); - - \ictrl.hit_1_16\ : NOR3C - port map(A => hit_1_2, B => hit_1_1, C => hit_1_12, Y => - hit_1_16); - - \ictrl.cdwrite_4_m_0[0]\ : NOR2A - port map(A => asi(0), B => N_425_0, Y => \cdwrite_4_m_0[0]\); - - \r.valid_RNIQ7DS1[6]\ : MX2C - port map(A => N_1016, B => N_1026, S => N_1028_i, Y => - \vmask_6[6]\); - - \r.istate_RNIEON21_24[0]\ : MX2 - port map(A => dataout_2(7), B => dataout_1(7), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_7); - - \r.vaddress[26]\ : DFN1E1 - port map(D => fpc(26), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[26]\); - - \r.waddress[16]\ : DFN1 - port map(D => \waddress_1[16]\, CLK => lclk_c, Q => - \address[16]\); - - \r.istate_RNI830H8[0]\ : MX2 - port map(A => hrdata_0_17, B => dataout_1(17), S => - istate_1259_d, Y => data_0(17)); - - \r.vaddress_RNIUFAKMI[15]\ : NOR2 - port map(A => \un1_ici\, B => N_971, Y => - vaddress_RNIUFAKMI(15)); - - \r.underrun_RNO_1\ : OA1B - port map(A => N_1372, B => underrun_2, C => underrun_1_0, Y - => underrun_1); - - \r.vaddress[22]\ : DFN1E1 - port map(D => fpc(22), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[22]\); - - \r.trans_op_0_a0_0\ : NOR2A - port map(A => un81_m_tlb_type, B => flush, Y => - trans_op_0_a2_0); - - \ictrl.un2_eholdn\ : OR2A - port map(A => un2_eholdn_0_0, B => de_hold_pc_1, Y => - un2_eholdn); - - \r.istate_RNIM2DE7[0]\ : MX2 - port map(A => hrdata_0_22, B => maddress(22), S => idle, Y - => istate_RNIM2DE7(0)); - - \r.istate_RNI6LOO6[0]\ : MX2 - port map(A => hrdata_0_10, B => maddress(10), S => idle_0, - Y => istate_RNI6LOO6(0)); - - \r.hit_RNO_0\ : MX2 - port map(A => hit, B => hit_1, S => idle, Y => N_1215); - - \r.vaddress_RNI5RAN[18]\ : MX2C - port map(A => \vaddress[18]\, B => maddress(18), S => - diagen_0_sqmuxa_0, Y => N_974); - - \r.trans_op_RNO_3\ : AOI1B - port map(A => trans_op_0_a3_0, B => un81_m_tlb_type, C => - rst, Y => trans_op_1_0); - - \r.istate_RNI580K8[0]\ : MX2 - port map(A => hrdata_0_8, B => dataout_1(8), S => - istate_1259_d, Y => data_0(8)); - - \r.trans_op_RNO_5\ : OR2A - port map(A => \istate_0_sqmuxa\, B => \trans_op_0\, Y => - trans_op_RNO_5); - - \r.istate_RNI05B4C[0]\ : MX2 - port map(A => hrdata_0_d0, B => dataout_1(5), S => - istate_1259_d_0, Y => data_0(5)); - - \r.vaddress_RNI93BN[27]\ : MX2C - port map(A => \vaddress[27]\, B => maddress(27), S => - diagen_0_sqmuxa_0, Y => N_983); - - \ictrl.0.un1_icramo_1\ : AO1B - port map(A => un1_icramo_NE_5, B => un1_icramo_NE_4, C => e, - Y => un1_icramo_1); - - \r.vaddress_RNI53BN[25]\ : MX2C - port map(A => \vaddress[25]\, B => maddress(25), S => - diagen_0_sqmuxa_0, Y => N_981); - - \r.vaddress_RNI0OAKMI[23]\ : NOR2 - port map(A => \un1_ici\, B => N_979, Y => - vaddress_RNI0OAKMI(23)); - - \r.istate_RNIEON21_15[0]\ : MX2 - port map(A => dataout_2(26), B => dataout_2(30), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_30); - - \r.istate_RNI9CHH8[0]\ : MX2 - port map(A => hrdata_24, B => dataout_2(29), S => - istate_1259_d_0, Y => data_0(29)); - - \r.holdn\ : DFN1 - port map(D => holdn_RNO, CLK => lclk_c, Q => \hold_0\); - - \r.istate_RNIS4VK8[0]\ : MX2 - port map(A => hrdata_25, B => maddress(30), S => idle_0, Y - => istate_RNIS4VK8(0)); - - \r.istate_RNIEON21_12[0]\ : MX2 - port map(A => dataout_2(4), B => dataout_1(4), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_4); - - \r.faddr[6]\ : DFN1E1 - port map(D => \faddr_1[6]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[6]\); - - \r.istate_RNIF2NN[0]\ : MX2 - port map(A => fpc(11), B => addr(11), S => diagen_0_sqmuxa, - Y => N_1130); - - \r.istate_RNIEON21_23[0]\ : MX2 - port map(A => dataout_2(9), B => dataout_1(13), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_13); - - \r.istate_RNIVR9M_0[0]\ : OR2A - port map(A => diagen_0_sqmuxa_0, B => asi(0), Y => - \cdwrite_0_sqmuxa_i_0_0\); - - \r.istate_RNIEON21_28[0]\ : MX2 - port map(A => dataout_2(0), B => dataout_1(0), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_0); - - \r.waddress[21]\ : DFN1 - port map(D => \waddress_1[21]\, CLK => lclk_c, Q => - \address[21]\); - - \r.istate_RNIR2JU8[0]\ : MX2 - port map(A => hrdata_0_27, B => maddress(27), S => idle_0, - Y => istate_RNIR2JU8(0)); - - \r.waddress_RNO[9]\ : MX2C - port map(A => N_1046, B => un1_m0_7, S => error_1_sqmuxa_0, - Y => \waddress_1[9]\); - - \r.waddress_RNO_0[15]\ : MX2C - port map(A => \address[15]\, B => fpc(15), S => - vaddress_0_sqmuxa_0, Y => N_1052); - - \r.waddress_RNIFG73_2[4]\ : NOR3B - port map(A => \address[2]\, B => \address[4]\, C => - \address[3]\, Y => \un95_res[5]\); - - \r.istate_RNIFCU97[0]\ : MX2 - port map(A => hrdata_0_12, B => dataout_1(12), S => - istate_1259_d_0, Y => data_0(12)); - - \r.waddress_RNO[24]\ : MX2C - port map(A => N_1061, B => un1_m0_22, S => error_1_sqmuxa, - Y => \waddress_1[24]\); - - \r.istate_RNIEON21_0[0]\ : MX2 - port map(A => dataout_2(21), B => dataout_1(25), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_25); - - \r.flush2_0_0_RNI6KDT\ : NOR3A - port map(A => diagen_0_sqmuxa_0, B => asi(0), C => - \un1_p0_2_0[148]\, Y => ctwrite_0_sqmuxa_1); - - \r.istate_RNILTAC8[0]\ : MX2 - port map(A => hrdata_0_17, B => maddress(17), S => idle, Y - => istate_RNILTAC8(0)); - - \r.flush_RNIVKVP\ : OR2A - port map(A => un1_dco_1, B => cacheon_1, Y => N_1028_i); - - \un1_r.faddr_I_27\ : AND2 - port map(A => \faddr[3]\, B => \faddr[4]\, Y => - \DWACT_FINC_E[1]\); - - \r.valid_RNILTEC[3]\ : AOI1 - port map(A => hit, B => \valid[3]\, C => \un95_res[3]\, Y - => N_1013); - - \r.req_RNO_0\ : OR2 - port map(A => error_1_sqmuxa_0, B => N_1201, Y => req_1_0); - - \r.cache\ : DFN1 - port map(D => cache_RNO, CLK => lclk_c, Q => cache); - - \r.waddress_RNO_1[4]\ : MX2A - port map(A => N_6093_i, B => \address[4]\, S => ready, Y - => \waddress_4[4]\); - - \r.istate_RNIEON21_6[0]\ : MX2 - port map(A => dataout_2(12), B => dataout_1(16), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_16); - - \r.faddr[2]\ : DFN1E1 - port map(D => \faddr_1[2]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[2]\); - - \ictrl.v.burst_1_iv_RNO_1\ : OR3C - port map(A => un1_mcio_1_i_0, B => burst_5_m_0, C => grant, - Y => burst_5_m); - - \r.waddress[22]\ : DFN1 - port map(D => \waddress_1[22]\, CLK => lclk_c, Q => - \address[22]\); - - \r.underrun_RNIH0CN1\ : OR2A - port map(A => ready, B => underrun, Y => overrun_4_0); - - \ictrl.0.un1_ici_18_0\ : XNOR2 - port map(A => dataout_2(26), B => fpc(30), Y => - un1_ici_18_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.waddress[19]\ : DFN1 - port map(D => \waddress_1[19]\, CLK => lclk_c, Q => - \address[19]\); - - \r.valid_RNIIR1H2[0]\ : MX2C - port map(A => \vmask_6[0]\, B => maddress(0), S => - diagen_0_sqmuxa_0, Y => N_1102); - - \r.istate_RNIMVFNJ[0]\ : MX2 - port map(A => N_262_0, B => dataout_1(20), S => - istate_1259_d, Y => data_0(20)); - - \r.waddress[18]\ : DFN1 - port map(D => \waddress_1[18]\, CLK => lclk_c, Q => - \address[18]\); - - \r.istate_RNI7BUID[0]\ : MX2 - port map(A => hrdata_1, B => maddress(6), S => idle_0, Y - => istate_RNI7BUID(0)); - - \r.vaddress[30]\ : DFN1E1 - port map(D => fpc(30), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[30]\); - - \r.su_RNI7H7D\ : OR2A - port map(A => nf, B => \su\, Y => un2_m_en); - - \ictrl.0.un1_ici_5_0\ : XNOR2 - port map(A => dataout_2(13), B => fpc(17), Y => - un1_ici_5_i_0); - - \r.waddress_RNO_0[28]\ : MX2C - port map(A => \address[28]\, B => fpc(28), S => - vaddress_0_sqmuxa_0, Y => N_1065); - - \r.waddress[25]\ : DFN1 - port map(D => \waddress_1[25]\, CLK => lclk_c, Q => - \address[25]\); - - \r.valid_RNO[1]\ : MX2A - port map(A => \vmask_6[1]\, B => dataout_2(1), S => - twrite_3, Y => \valid_1[1]\); - - \ictrl.hit_1_2\ : XA1A - port map(A => fpc(14), B => dataout_2(10), C => - un1_ici_3_i_0, Y => hit_1_2); - - \r.vaddress[18]\ : DFN1E1 - port map(D => fpc(18), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[18]\); - - \r.overrun_RNIBRGN1\ : OR2 - port map(A => overrun, B => ready, Y => un1_mcio_4_0); - - \r.flush2_0_0_RNIVV5O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1105, Y => - flush2_0_0_RNIVV5O2); - - \r.waddress_RNO[29]\ : MX2C - port map(A => N_1066, B => N_363, S => error_1_sqmuxa_0, Y - => \waddress_1[29]\); - - \r.waddress_RNIFG73_6[4]\ : NOR3 - port map(A => \address[2]\, B => \address[3]\, C => - \address[4]\, Y => \un95_res[0]\); - - \r.overrun_RNO\ : OA1A - port map(A => holdn_0_sqmuxa_1, B => N_1212, C => rst, Y - => overrun_RNO); - - \r.istate_RNO[0]\ : AOI1B - port map(A => \istate_ns_0_0[0]\, B => N_1345, C => rst, Y - => \istate_nss[0]\); - - \r.vaddress_RNID3BN[29]\ : MX2 - port map(A => \vaddress[29]\, B => maddress(29), S => - diagen_0_sqmuxa_0, Y => N_985); - - \r.istate_RNISQRTI[0]\ : MX2 - port map(A => N_78_0, B => dataout_1(25), S => - istate_1259_d_0, Y => data_0(25)); - - \r.istate_RNIKJBN8[0]\ : MX2 - port map(A => hrdata_0_11, B => maddress(11), S => idle_0, - Y => istate_RNIKJBN8(0)); - - \r.waddress_RNO[7]\ : MX2C - port map(A => N_1044, B => un1_m0_5, S => error_1_sqmuxa, Y - => \waddress_1[7]\); - - \r.istate_RNIEON21_26[0]\ : MX2 - port map(A => dataout_2(1), B => dataout_1(1), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_1); - - \ictrl.v.burst_1_iv_RNO_2\ : OR3C - port map(A => \un4_validv[7]\, B => burst, C => idle_0, Y - => burst_2_m); - - \r.waddress[26]\ : DFN1 - port map(D => \waddress_1[26]\, CLK => lclk_c, Q => - \address[26]\); - - \r.istate_RNILPRHG[0]\ : MX2 - port map(A => hrdata_0_0, B => dataout_1(0), S => - istate_1259_d_0, Y => data_0(0)); - - \r.istate_RNIEON21_2[0]\ : MX2 - port map(A => dataout_2(16), B => dataout_1(20), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_20); - - \r.waddress[3]\ : DFN1 - port map(D => \waddress_1[3]\, CLK => lclk_c, Q => - \address[3]\); - - \ictrl.0.un1_icramo_5_0\ : XNOR2 - port map(A => dataout_0(33), B => ctx_5, Y => - un1_icramo_5_i); - - \r.istate_RNITH1SG1[0]\ : OR2 - port map(A => un5_m_en, B => N_1320, Y => error_0_sqmuxa_1); - - \r.istate_RNIPMA0F[0]\ : NOR3B - port map(A => istate_0_sqmuxa_0_a3_m6_3, B => hold_pc_7, C - => un5_eholdn, Y => istate_0_sqmuxa_0_a3_m6_5); - - \r.waddress_RNO_0[4]\ : MX2C - port map(A => \waddress_4[4]\, B => fpc(4), S => - vaddress_0_sqmuxa_0, Y => N_1041); - - \r.istate_RNIRLUI[0]\ : MX2C - port map(A => fpc(3), B => addr(3), S => diagen_0_sqmuxa_0, - Y => N_1122); - - \r.istate_RNIOJJE1[0]\ : MX2 - port map(A => hrdata_0_26, B => maddress(26), S => idle_0, - Y => istate_RNIOJJE1(0)); - - \r.waddress_RNO[20]\ : MX2C - port map(A => N_1057, B => N_2625, S => error_1_sqmuxa, Y - => \waddress_1[20]\); - - \r.waddress_RNO[16]\ : MX2C - port map(A => N_1053, B => N_423, S => error_1_sqmuxa, Y - => \waddress_1[16]\); - - \v.istate_0_sqmuxa_0_a3_m6_1\ : NOR3C - port map(A => e_0, B => un2_eholdn_0, C => rst, Y => - istate_0_sqmuxa_0_a3_m6_1); - - \r.istate_RNIOVC5J[0]\ : MX2 - port map(A => hrdata_0_14, B => maddress(14), S => idle, Y - => istate_RNIOVC5J(0)); - - \r.underrun_RNIUQ18\ : OR2A - port map(A => overrun, B => underrun, Y => un5_mds); - - \r.faddr[3]\ : DFN1E1 - port map(D => \faddr_1[3]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[3]\); - - \r.vaddress[6]\ : DFN1E1 - port map(D => fpc(6), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[6]\); - - \r.istate_RNIJCMP6[0]\ : MX2A - port map(A => twrite_3, B => \cdwrite_4_m_0[0]\, S => - diagen_0_sqmuxa, Y => istate_RNIJCMP6(0)); - - \ictrl.valid_1_1\ : MX2 - port map(A => dataout_2(0), B => dataout_2(4), S => fpc(4), - Y => N_960); - - \r.istate[1]\ : DFN1 - port map(D => \istate_nss[1]\, CLK => lclk_c, Q => - \istate[1]\); - - \r.faddr_RNIUT72LB[3]\ : MX2 - port map(A => \taddr_9[8]\, B => \faddr[3]\, S => \flush2\, - Y => faddr_RNIUT72LB(3)); - - \r.waddress[4]\ : DFN1 - port map(D => \waddress_1[4]\, CLK => lclk_c, Q => - \address[4]\); - - \r.vaddress_RNIIE8DP6[3]\ : MX2C - port map(A => rpc_1, B => \vaddress[3]\, S => - taddr_0_sqmuxa_1, Y => N_1144); - - \r.istate_RNIJGCD_4[0]\ : NOR2 - port map(A => \istate[1]\, B => \istate[0]\, Y => idle_0); - - \r.istate_RNIFK51A[0]\ : MX2 - port map(A => hrdata_0_7, B => dataout_1(7), S => - istate_1259_d_0, Y => data_0(7)); - - \r.waddress_RNIFG73_0[4]\ : NOR3B - port map(A => \address[2]\, B => \address[3]\, C => - \address[4]\, Y => \un95_res[3]\); - - \r.vaddress_RNIUNAKMI[22]\ : NOR2 - port map(A => \un1_ici\, B => N_978, Y => - vaddress_RNIUNAKMI(22)); - - \un1_r.faddr_I_19\ : NOR2B - port map(A => \faddr[3]\, B => \DWACT_FINC_E[0]\, Y => N_12); - - \r.trans_op_RNO_6\ : NOR2A - port map(A => trans_op, B => flush, Y => trans_op_0_a3_0); - - \r.waddress_RNO_0[19]\ : MX2C - port map(A => \address[19]\, B => fpc(19), S => - vaddress_0_sqmuxa_0, Y => N_1056); - - \ictrl.v.burst_1_iv_RNO_0\ : AND2 - port map(A => burst_5_m, B => burst_2_m, Y => burst_1_iv_0); - - \r.waddress[2]\ : DFN1 - port map(D => \waddress_1[2]\, CLK => lclk_c, Q => - \address[2]\); - - \r.istate_RNIEON21[0]\ : MX2 - port map(A => dataout_2(22), B => dataout_1(26), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_26); - - \r.hit_RNO\ : OR2A - port map(A => twrite_3, B => N_1215, Y => hit_RNO); - - \r.waddress_RNO[3]\ : MX2C - port map(A => N_1040, B => un1_m0_1, S => error_1_sqmuxa, Y - => \waddress_1[3]\); - - \ictrl.0.un1_icramo_NE_3\ : XA1A - port map(A => ctx_0_4, B => dataout_0(34), C => - un1_icramo_7_i, Y => un1_icramo_NE_3); - - \r.waddress_RNO_0[11]\ : MX2C - port map(A => \address[11]\, B => fpc(11), S => - vaddress_0_sqmuxa_1, Y => N_1048); - - \r.waddress_RNI3LUL_1[4]\ : OA1B - port map(A => \un95_res[4]\, B => dataout_2(4), C => - cacheon_1, Y => N_1024); - - \r.vaddress_RNO[3]\ : MX2A - port map(A => \vaddress_4[3]\, B => fpc(3), S => - vaddress_0_sqmuxa_0, Y => \vaddress_1[3]\); - - \r.faddr[1]\ : DFN1E1 - port map(D => \faddr_1[1]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[1]\); - - \r.waddress_RNO[2]\ : MX2C - port map(A => N_1039, B => un1_m0_0, S => error_1_sqmuxa, Y - => \waddress_1[2]\); - - \r.req_RNI1TO62\ : OR2A - port map(A => underrun2, B => istate_1259_d, Y => - underrun_1_sqmuxa); - - \r.istate_RNIEON21_1[0]\ : MX2 - port map(A => dataout_2(18), B => dataout_1(22), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_22); - - \r.waddress_RNO[31]\ : MX2C - port map(A => N_1068, B => N_365, S => error_1_sqmuxa_0, Y - => \waddress_1[31]\); - - \r.vaddress_RNO[2]\ : MX2A - port map(A => \vaddress_4_i[2]\, B => fpc(2), S => - vaddress_0_sqmuxa_0, Y => \vaddress_1[2]\); - - \r.istate_RNIEON21_27[0]\ : MX2 - port map(A => dataout_2(2), B => dataout_1(2), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_2); - - \r.istate_RNIDOS1V[0]\ : NOR2A - port map(A => idle, B => un2_eholdn, Y => vaddress_0_sqmuxa); - - \r.flush2_RNI0UAC\ : NOR2A - port map(A => ics(0), B => \flush2\, Y => N_1346_1); - - \r.vaddress_RNIGFP1UE[11]\ : MX2C - port map(A => N_1152, B => N_1130, S => N_1163_i, Y => - \taddr_9[11]\); - - \r.istate_RNIDOS1V_0[0]\ : NOR2A - port map(A => idle_0, B => un2_eholdn, Y => - vaddress_0_sqmuxa_1); - - \r.underrun_RNO\ : NOR2B - port map(A => rst, B => N_1213, Y => underrun_RNO); - - \r.istate_RNICVCR5[0]\ : NOR2A - port map(A => twrite_3, B => idle, Y => valid_1_sqmuxa); - - \r.waddress_RNO[27]\ : MX2C - port map(A => N_1064, B => N_319, S => error_1_sqmuxa_0, Y - => \waddress_1[27]\); - - \r.istate_RNO_1[1]\ : NOR2B - port map(A => N_1350, B => N_1348, Y => \istate_ns_0_0[1]\); - - \r.waddress[29]\ : DFN1 - port map(D => \waddress_1[29]\, CLK => lclk_c, Q => - \address[29]\); - - \r.istate_RNIMRTH8[0]\ : MX2 - port map(A => hrdata_0_8, B => maddress(8), S => idle_0, Y - => istate_RNIMRTH8(0)); - - \r.burst_RNO_0\ : MX2 - port map(A => burst_1, B => \burst_0\, S => istate_5, Y => - N_1202); - - \r.waddress[5]\ : DFN1 - port map(D => \waddress_1[5]\, CLK => lclk_c, Q => - \address[5]\); - - \r.flush2_RNI1R3J2_0\ : NOR3 - port map(A => N_1346_1, B => underrun2, C => - istate_1259_d_0, Y => taddr_1_sqmuxa_0); - - \r.waddress_RNI3LUL_5[4]\ : AO1D - port map(A => dataout_2(3), B => \un95_res[3]\, C => - cacheon_1, Y => N_1023); - - \r.waddress[28]\ : DFN1 - port map(D => \waddress_1[28]\, CLK => lclk_c, Q => - \address[28]\); - - \r.istate_RNIEON21_14[0]\ : MX2 - port map(A => dataout_2(5), B => dataout_1(5), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_5); - - \r.vaddress_RNIV4U1PE[11]\ : MX2 - port map(A => N_26, B => \vaddress[11]\, S => - taddr_0_sqmuxa_1, Y => N_1152); - - \r.istate_RNIIMI4I1_0[0]\ : NOR3A - port map(A => un5_m_en, B => N_66, C => N_1320, Y => - error_1_sqmuxa); - - \r.waddress_RNO_0[16]\ : MX2C - port map(A => \address[16]\, B => fpc(16), S => - vaddress_0_sqmuxa_0, Y => N_1053); - - \r.vaddress[19]\ : DFN1E1 - port map(D => fpc(19), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[19]\); - - \r.istate_RNIQGA6A[0]\ : MX2 - port map(A => hrdata_0_18, B => dataout_1(18), S => - istate_1259_d, Y => data_0(18)); - - \r.faddr_RNI2LF01[6]\ : NOR3B - port map(A => \un1_p0_2_0[148]\, B => \faddr[6]\, C => - I_31_0, Y => flush2_0_sqmuxa); - - \r.waddress_RNO_0[27]\ : MX2C - port map(A => \address[27]\, B => fpc(27), S => - vaddress_0_sqmuxa_0, Y => N_1064); - - \r.vaddress[28]\ : DFN1E1 - port map(D => fpc(28), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[28]\); - - \r.waddress_RNIFG73[4]\ : NOR3C - port map(A => \address[2]\, B => \address[3]\, C => - \address[4]\, Y => \un95_res[7]\); - - \r.istate_RNIH0NBI[0]\ : MX2 - port map(A => hrdata_0_24, B => maddress(24), S => idle, Y - => istate_RNIH0NBI(0)); - - \r.burst_RNO_3\ : OR2B - port map(A => \istate[0]\, B => un5_m_en, Y => N_1310); - - \r.vaddress_RNIT2BN[21]\ : MX2C - port map(A => \vaddress[21]\, B => maddress(21), S => - diagen_0_sqmuxa, Y => N_977); - - \r.waddress_RNO[13]\ : MX2C - port map(A => N_1050, B => N_2624, S => error_1_sqmuxa_0, Y - => \waddress_1[13]\); - - \r.vaddress_RNIOFAKMI[12]\ : NOR2 - port map(A => \un1_ici\, B => N_968, Y => - vaddress_RNIOFAKMI(12)); - - \ictrl.un1_dco_1\ : OR2A - port map(A => ics(0), B => ics(1), Y => un1_dco_1); - - \r.flush_RNIR7JL\ : XA1A - port map(A => fpc(31), B => dataout_2(27), C => hit_1_0, Y - => hit_1_10); - - \r.istate_RNIJ1UUI1[0]\ : OR2B - port map(A => mexc, B => error_0_sqmuxa_1, Y => mexc_0); - - \r.istate_RNI6HPAI[0]\ : MX2 - port map(A => hrdata_0_2, B => maddress(2), S => idle, Y - => istate_RNI6HPAI(0)); - - \r.flush2_0_0_RNI7G6O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1109, Y => - flush2_0_0_RNI7G6O2); - - \r.vaddress_RNIP199QA[7]\ : MX2C - port map(A => N_1148, B => N_1126, S => N_1163_i, Y => - \taddr_9[7]\); - - \r.flush2_0_0_RNI386O2\ : NOR2A - port map(A => N_1107, B => \un1_p0_2_0[148]\, Y => - un1_p0_2_i_4); - - \r.valid_RNI0O2H2[7]\ : MX2B - port map(A => \vmask_6[7]\, B => maddress(7), S => - diagen_0_sqmuxa_0, Y => N_1109); - - \r.istate_RNIJRBBD[0]\ : MX2 - port map(A => N_264_0, B => dataout_1(19), S => - istate_1259_d, Y => data_0(19)); - - \r.istate_RNI6PSS1[0]\ : MX2 - port map(A => hrdata_0_13, B => maddress(13), S => idle, Y - => istate_RNI6PSS1(0)); - - \r.waddress_RNO_0[30]\ : MX2C - port map(A => \address[30]\, B => fpc(30), S => - vaddress_0_sqmuxa_1, Y => N_1067); - - \r.vaddress_RNIB3BN[28]\ : MX2 - port map(A => \vaddress[28]\, B => maddress(28), S => - diagen_0_sqmuxa, Y => N_984); - - \r.vaddress[9]\ : DFN1E1 - port map(D => fpc(9), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[9]\); - - \r.istate_RNIEON21_13[0]\ : MX2 - port map(A => dataout_2(6), B => dataout_1(6), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_6); - - \r.istate_RNIB4839[0]\ : MX2 - port map(A => hrdata_0_27, B => dataout_1(27), S => - istate_1259_d_0, Y => data_0(27)); - - \r.istate_RNIEON21_18[0]\ : MX2 - port map(A => dataout_2(25), B => dataout_2(29), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_29); - - \r.vaddress_RNIRQAN[13]\ : MX2C - port map(A => \vaddress[13]\, B => maddress(13), S => - diagen_0_sqmuxa_0, Y => N_969); - - \r.waddress_RNO[18]\ : MX2C - port map(A => N_1055, B => un1_m0_16, S => error_1_sqmuxa_0, - Y => \waddress_1[18]\); - - \r.waddress[13]\ : DFN1 - port map(D => \waddress_1[13]\, CLK => lclk_c, Q => - \address[13]\); - - \r.underrun\ : DFN1 - port map(D => underrun_RNO, CLK => lclk_c, Q => underrun); - - \r.istate_RNIRLSCI[0]\ : MX2 - port map(A => hrdata_0_2, B => dataout_1(2), S => - istate_1259_d_0, Y => data_0(2)); - - \un1_r.faddr_I_8\ : NOR2B - port map(A => \faddr[1]\, B => \faddr[0]\, Y => N_20); - - \r.waddress_RNO_0[12]\ : MX2C - port map(A => \address[12]\, B => fpc(12), S => - vaddress_0_sqmuxa_0, Y => N_1049); - - \r.valid_RNIR7DS1[7]\ : MX2C - port map(A => N_1017, B => N_1027, S => N_1028_i, Y => - \vmask_6[7]\); - - \r.vaddress_RNO_0[3]\ : AX1A - port map(A => ready, B => \vaddress[2]\, C => \vaddress[3]\, - Y => \vaddress_4[3]\); - - \ictrl.valid_1_2\ : MX2 - port map(A => dataout_2(2), B => dataout_2(6), S => fpc(4), - Y => N_961); - - \r.valid_RNIKV1H2[1]\ : MX2A - port map(A => \vmask_6[1]\, B => maddress(1), S => - diagen_0_sqmuxa_0, Y => N_1103); - - \r.vaddress_RNIV2BN[22]\ : MX2C - port map(A => \vaddress[22]\, B => maddress(22), S => - diagen_0_sqmuxa_0, Y => N_978); - - \r.istate_RNIEON21_5[0]\ : MX2 - port map(A => dataout_2(13), B => dataout_1(17), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_17); - - \r.istate_RNO_1[0]\ : AO1A - port map(A => N_66, B => un5_m_en, C => N_1320, Y => N_1345); - - \r.valid_RNIMTEC[4]\ : AO1 - port map(A => hit, B => \valid[4]\, C => \un95_res[4]\, Y - => N_1014); - - \r.valid_RNIJTEC[1]\ : AO1 - port map(A => hit, B => \valid[1]\, C => \un95_res[1]\, Y - => N_1011); - - \r.vaddress_RNIK35ELA[7]\ : MX2 - port map(A => rpc_5, B => \vaddress[7]\, S => - taddr_0_sqmuxa_1, Y => N_1148); - - \un1_r.faddr_I_20\ : XOR2 - port map(A => N_12, B => \faddr[4]\, Y => I_20_0); - - \r.waddress_RNIFG73_3[4]\ : NOR3A - port map(A => \address[3]\, B => \address[2]\, C => - \address[4]\, Y => \un95_res[2]\); - - \r.istate_RNI8BL1A[0]\ : MX2 - port map(A => hrdata_0_18, B => maddress(18), S => idle, Y - => istate_RNI8BL1A(0)); - - \r.waddress_RNO[4]\ : MX2C - port map(A => N_1041, B => un1_m0_2, S => error_1_sqmuxa_0, - Y => \waddress_1[4]\); - - \r.vaddress_RNIRS4BNE[9]\ : MX2C - port map(A => N_1150, B => N_1128, S => N_1163_i, Y => - \taddr_9[9]\); - - \r.vaddress_RNI7RAN[19]\ : MX2C - port map(A => \vaddress[19]\, B => maddress(19), S => - diagen_0_sqmuxa, Y => N_975); - - \r.vaddress_RNO[4]\ : MX2A - port map(A => \vaddress_4[4]\, B => fpc(4), S => - vaddress_0_sqmuxa_1, Y => \vaddress_1[4]\); - - \r.trans_op\ : DFN1 - port map(D => trans_op_RNO, CLK => lclk_c, Q => - \trans_op_0\); - - \r.cache_RNO_0\ : MX2 - port map(A => cache, B => un1_m0_30, S => error_1_sqmuxa, Y - => N_1203); - - \r.valid_RNO[6]\ : MX2A - port map(A => \vmask_6[6]\, B => dataout_2(6), S => - twrite_3, Y => \valid_1[6]\); - - \ictrl.0.un1_icramo_NE_4\ : NOR3C - port map(A => un1_icramo_1_0_i, B => un1_icramo_0_i, C => - un1_icramo_NE_1, Y => un1_icramo_NE_4); - - \r.istate[0]\ : DFN1 - port map(D => \istate_nss[0]\, CLK => lclk_c, Q => - \istate[0]\); - - \r.overrun\ : DFN1 - port map(D => overrun_RNO, CLK => lclk_c, Q => overrun); - - \r.flush_RNO_1\ : OR2B - port map(A => \istate[1]\, B => N_1333, Y => N_1317); - - \r.faddr[0]\ : DFN1E1 - port map(D => \faddr_1[0]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[0]\); - - \r.holdn_RNO_1\ : OR3 - port map(A => N_1372, B => underrun_2, C => overrun_4, Y - => overrun_1); - - \r.waddress[30]\ : DFN1 - port map(D => \waddress_1[30]\, CLK => lclk_c, Q => - \address[30]\); - - \ictrl.v.burst_1_iv_RNO\ : NAND2 - port map(A => req_7, B => req_0_sqmuxa, Y => req_7_m); - - \r.vaddress_RNI33BN[24]\ : MX2C - port map(A => \vaddress[24]\, B => maddress(24), S => - diagen_0_sqmuxa, Y => N_980); - - \r.istate_RNI5V68H[0]\ : MX2 - port map(A => hrdata_0_23, B => maddress(23), S => idle, Y - => istate_RNI5V68H(0)); - - \r.valid_RNIO7DS1[4]\ : MX2C - port map(A => N_1014, B => N_1024, S => N_1028_i, Y => - \vmask_6[4]\); - - \r.istate_RNIJGCD_3[0]\ : NOR2 - port map(A => \istate[1]\, B => \istate[0]\, Y => idle); - - \r.flush\ : DFN1 - port map(D => flush_RNO, CLK => lclk_c, Q => \flush_0\); - - \v.istate_0_sqmuxa_0_a3_m2_e\ : OR2A - port map(A => un9_icc_check_bp, B => ldlock_3_0, Y => - istate_0_sqmuxa_0_a3_m2_e); - - \r.istate_RNIG7IIA[0]\ : MX2 - port map(A => hrdata_0_4, B => maddress(4), S => idle, Y - => istate_RNIG7IIA(0)); - - \r.flush2_0_0_RNITR5O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1104, Y => - flush2_0_0_RNITR5O2); - - \r.waddress_RNO[15]\ : MX2C - port map(A => N_1052, B => N_357, S => error_1_sqmuxa_0, Y - => \waddress_1[15]\); - - \r.istate_RNIAJH4F[0]\ : MX2 - port map(A => hrdata_0_21, B => maddress(21), S => idle, Y - => istate_RNIAJH4F(0)); - - \r.vaddress_RNISFAKMI[14]\ : NOR2 - port map(A => \un1_ici\, B => N_970, Y => - vaddress_RNISFAKMI(14)); - - \r.burst_RNO\ : NOR2B - port map(A => rst, B => N_1202, Y => burst_RNO_0); - - \ictrl.v.burst_1_iv\ : NAND2 - port map(A => req_7_m, B => burst_1_iv_0, Y => burst_1); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.vaddress_RNI8EVQ36[2]\ : MX2C - port map(A => N_1143, B => N_1121, S => N_1163_i, Y => - vaddress_RNI8EVQ36(2)); - - \r.vaddress_RNI6GAKMI[19]\ : NOR2 - port map(A => \un1_ici\, B => N_975, Y => - vaddress_RNI6GAKMI(19)); - - \r.istate_RNIPDUI[0]\ : MX2C - port map(A => fpc(2), B => addr(2), S => diagen_0_sqmuxa_0, - Y => N_1121); - - \r.istate_RNIEON21_4[0]\ : MX2 - port map(A => dataout_2(14), B => dataout_1(18), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_18); - - \r.istate_RNIAP6PI[0]\ : MX2 - port map(A => N_78_0, B => maddress(25), S => idle_0, Y => - istate_RNIAP6PI(0)); - - \r.istate_RNIEON21_16[0]\ : MX2 - port map(A => dataout_2(24), B => dataout_2(28), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_28); - - \r.valid[4]\ : DFN1E0 - port map(D => \valid_1[4]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[4]\); - - \r.vaddress[29]\ : DFN1E1 - port map(D => fpc(29), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[29]\); - - \r.istate_RNIEON21_20[0]\ : MX2 - port map(A => dataout_2(20), B => dataout_1(24), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_24); - - \r.istate_RNIE52AJ[0]\ : MX2 - port map(A => hrdata_0_14, B => dataout_1(14), S => - istate_1259_d, Y => data_0(14)); - - \ictrl.0.un1_ici_8_0\ : XNOR2 - port map(A => dataout_2(16), B => fpc(20), Y => - un1_ici_8_i_0); - - \r.holdn_RNO_3\ : OR3 - port map(A => un5_eholdn, B => \istate[1]\, C => un2_eholdn, - Y => N_1331); - - \un1_r.faddr_I_16\ : AND3 - port map(A => \faddr[0]\, B => \faddr[1]\, C => \faddr[2]\, - Y => \DWACT_FINC_E[0]\); - - \r.flush_RNI0U5C\ : OR2A - port map(A => ics(0), B => \flush_0\, Y => cacheon_1); - - \r.istate_RNI2MM6D[0]\ : MX2 - port map(A => N_264_0, B => maddress(19), S => idle, Y => - istate_RNI2MM6D(0)); - - \r.istate_RNIM369G[0]\ : MX2 - port map(A => hrdata_0_1, B => dataout_1(1), S => - istate_1259_d_0, Y => data_0(1)); - - \r.istate_RNIJGCD_0[0]\ : OR2A - port map(A => \istate[1]\, B => \istate[0]\, Y => - istate_1259_d); - - \r.istate_RNID2NN[0]\ : MX2C - port map(A => fpc(10), B => addr(10), S => diagen_0_sqmuxa, - Y => N_1129); - - \r.faddr_RNO[3]\ : NOR2B - port map(A => \flush2\, B => I_13_4, Y => \faddr_1[3]\); - - \r.waddress_RNO[26]\ : MX2C - port map(A => N_1063, B => N_361, S => error_1_sqmuxa_0, Y - => \waddress_1[26]\); - - \ictrl.hit_1_12\ : NOR3C - port map(A => un1_ici_5_i_0, B => un1_ici_4_i_0, C => - hit_1_4, Y => hit_1_12); - - \un1_r.faddr_I_30\ : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \faddr[5]\, Y => N_4); - - \r.istate_RNIQARG[0]\ : NOR2B - port map(A => idle, B => enable, Y => diagen_0_sqmuxa); - - \ictrl.0.un1_icramo_7_0\ : XNOR2 - port map(A => dataout_0(35), B => ctx_0_5, Y => - un1_icramo_7_i); - - \r.waddress_RNO[30]\ : MX2C - port map(A => N_1067, B => N_43, S => error_1_sqmuxa, Y => - \waddress_1[30]\); - - \r.vaddress_RNIFRPEO8[5]\ : MX2C - port map(A => rpc_3, B => \vaddress[5]\, S => - taddr_0_sqmuxa_1, Y => N_1146); - - \r.waddress_RNO_0[7]\ : MX2C - port map(A => \address[7]\, B => fpc(7), S => - vaddress_0_sqmuxa_1, Y => N_1044); - - \un1_r.faddr_I_31\ : XOR2 - port map(A => N_4, B => \faddr[6]\, Y => I_31_0); - - \r.waddress_RNO[8]\ : MX2C - port map(A => N_1045, B => un1_m0_6, S => error_1_sqmuxa, Y - => \waddress_1[8]\); - - \r.vaddress_RNIPQAN[12]\ : MX2C - port map(A => \vaddress[12]\, B => maddress(12), S => - diagen_0_sqmuxa, Y => N_968); - - \r.cache_RNIKGGB1\ : NOR3B - port map(A => twrite_3_iv_0, B => hit_RNIR2PJ, C => bo_d(3), - Y => twrite_3_iv_2); - - \r.vaddress[17]\ : DFN1E1 - port map(D => fpc(17), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[17]\); - - \r.istate_RNIUCOFG[0]\ : MX2 - port map(A => hrdata_0_0, B => maddress(0), S => idle, Y - => istate_RNIUCOFG(0)); - - \r.vaddress_RNIVQAN[15]\ : MX2C - port map(A => \vaddress[15]\, B => maddress(15), S => - diagen_0_sqmuxa_0, Y => N_971); - - \r.vaddress[10]\ : DFN1E1 - port map(D => fpc(10), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[10]\); - - \ictrl.valid_1_7\ : MX2C - port map(A => N_962, B => N_965, S => fpc(2), Y => valid_1); - - \r.waddress[23]\ : DFN1 - port map(D => \waddress_1[23]\, CLK => lclk_c, Q => - \address[23]\); - - \r.valid[0]\ : DFN1E0 - port map(D => \valid_1[0]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[0]\); - - \r.faddr_RNO[4]\ : NOR2B - port map(A => \flush2\, B => I_20_0, Y => \faddr_1[4]\); - - \r.istate_RNI8FCK8[0]\ : MX2 - port map(A => hrdata_0_16, B => dataout_1(16), S => - istate_1259_d, Y => data_0(16)); - - \r.waddress[7]\ : DFN1 - port map(D => \waddress_1[7]\, CLK => lclk_c, Q => - \address[7]\); - - \r.vaddress[31]\ : DFN1E1 - port map(D => fpc(31), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[31]\); - - \ictrl.hit_1_8\ : XA1A - port map(A => fpc(26), B => dataout_2(22), C => - un1_ici_15_i_0, Y => hit_1_8); - - \r.overrun_RNI75H932\ : MX2 - port map(A => rbranch, B => fbranch, S => overrun, Y => - N_1372); - - \r.valid_RNIO72H2[3]\ : MX2C - port map(A => \vmask_6[3]\, B => maddress(3), S => - diagen_0_sqmuxa_0, Y => N_1105); - - \r.vaddress_RNIFCB8U6[3]\ : MX2C - port map(A => N_1144, B => N_1122, S => N_1163_i, Y => - vaddress_RNIFCB8U6(3)); - - \r.istate_RNIOV0LD[0]\ : MX2 - port map(A => hrdata_1, B => dataout_1(6), S => - istate_1259_d, Y => data_0(6)); - - \r.waddress_RNO_0[25]\ : MX2C - port map(A => \address[25]\, B => fpc(25), S => - vaddress_0_sqmuxa_1, Y => N_1062); - - \r.istate_RNIQARG_0[0]\ : NOR2B - port map(A => idle_0, B => enable, Y => diagen_0_sqmuxa_0); - - \r.istate_RNIEON21_17[0]\ : MX2 - port map(A => dataout_2(27), B => dataout_2(31), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_31); - - \r.faddr_RNO[0]\ : NOR2A - port map(A => \un1_p0_2_0[148]\, B => \faddr[0]\, Y => - \faddr_1[0]\); - - \r.faddr_RNI7UFASD[5]\ : MX2 - port map(A => \taddr_9[10]\, B => \faddr[5]\, S => \flush2\, - Y => faddr_RNI7UFASD(5)); - - \r.waddress_RNO_0[3]\ : MX2C - port map(A => \waddress_4[3]\, B => fpc(3), S => - vaddress_0_sqmuxa_1, Y => N_1040); - - \r.istate_RNI80L93[0]\ : NOR3C - port map(A => idle_0, B => istate_0_sqmuxa_0_a3_m6_1, C => - istate_0_sqmuxa_0_a3_m2_e, Y => istate_0_sqmuxa_0_a3_m6_3); - - \r.faddr_RNI7H6KT8[0]\ : MX2 - port map(A => \taddr_9[5]\, B => \faddr[0]\, S => - \un1_p0_2_0[148]\, Y => faddr_RNI7H6KT8(0)); - - \r.holdn_RNO_2\ : OR3C - port map(A => N_1350, B => N_1320, C => N_1331, Y => N_1312); - - \r.waddress_RNIFG73_1[4]\ : NOR3B - port map(A => \address[3]\, B => \address[4]\, C => - \address[2]\, Y => \un95_res[6]\); - - \r.vaddress_RNI0GAKMI[16]\ : NOR2 - port map(A => \un1_ici\, B => N_972, Y => - vaddress_RNI0GAKMI(16)); - - \r.vaddress_RNI13BN[23]\ : MX2C - port map(A => \vaddress[23]\, B => maddress(23), S => - diagen_0_sqmuxa, Y => N_979); - - \ictrl.0.un1_ici_4_0\ : XNOR2 - port map(A => dataout_2(12), B => fpc(16), Y => - un1_ici_4_i_0); - - \r.waddress_RNO_0[9]\ : MX2C - port map(A => \address[9]\, B => fpc(9), S => - vaddress_0_sqmuxa_0, Y => N_1046); - - \r.vaddress[13]\ : DFN1E1 - port map(D => fpc(13), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[13]\); - - \r.holdn_RNO\ : OR2B - port map(A => rst, B => holdn_1_i, Y => holdn_RNO); - - \r.valid_RNIPTEC[7]\ : AO1 - port map(A => hit, B => \valid[7]\, C => \un95_res[7]\, Y - => N_1017); - - \r.faddr_RNI0FOJNE[4]\ : MX2 - port map(A => \taddr_9[9]\, B => \faddr[4]\, S => \flush2\, - Y => faddr_RNI0FOJNE(4)); - - \r.cache_RNI0F2K\ : NOR3C - port map(A => hcache, B => ba, C => cache, Y => - twrite_3_iv_0); - - \r.istate_RNI42CGI[0]\ : MX2 - port map(A => hrdata_0_24, B => dataout_1(24), S => - istate_1259_d, Y => data_0(24)); - - \r.faddr_RNO[1]\ : NOR2B - port map(A => \un1_p0_2_0[148]\, B => I_5_0, Y => - \faddr_1[1]\); - - \r.waddress_RNIFG73_5[4]\ : NOR3A - port map(A => \address[2]\, B => \address[3]\, C => - \address[4]\, Y => \un95_res[1]\); - - \r.istate_RNIGUTA8[0]\ : MX2 - port map(A => hrdata_0_9, B => maddress(9), S => idle_0, Y - => istate_RNIGUTA8(0)); - - \r.istate_RNI2UDGE[0]\ : MX2 - port map(A => hrdata_23, B => dataout_2(28), S => - istate_1259_d_0, Y => data_0(28)); - - \r.waddress[17]\ : DFN1 - port map(D => \waddress_1[17]\, CLK => lclk_c, Q => - \address[17]\); - - \r.istate_RNIV33V9[0]\ : MX2 - port map(A => hrdata_0_7, B => maddress(7), S => idle_0, Y - => istate_RNIV33V9(0)); - - \ictrl.un2_eholdn_0_0\ : NOR2A - port map(A => un2_eholdn_0, B => un1_p0_6(0), Y => - un2_eholdn_0_0); - - \r.waddress_RNO[23]\ : MX2C - port map(A => N_1060, B => N_359, S => error_1_sqmuxa, Y - => \waddress_1[23]\); - - \r.valid[6]\ : DFN1E0 - port map(D => \valid_1[6]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[6]\); - - \r.flush_RNO_2\ : AO1D - port map(A => underrun2, B => N_1346_1, C => \istate[0]\, Y - => N_1333); - - \r.diagrdy\ : DFN1 - port map(D => diagen_0_sqmuxa, CLK => lclk_c, Q => diagrdy); - - \r.istate_RNIB42J7[0]\ : MX2 - port map(A => hrdata_0_22, B => dataout_1(22), S => - istate_1259_d, Y => data_0(22)); - - \r.istate_RNI1EVI[0]\ : MX2 - port map(A => fpc(6), B => addr(6), S => diagen_0_sqmuxa, Y - => N_1125); - - \r.istate_RNI0RDT6[0]\ : MX2 - port map(A => hrdata_0_10, B => dataout_1(10), S => - istate_1259_d_0, Y => data_0(10)); - - \r.flush2_RNIFMGM2\ : NOR2 - port map(A => \flush2\, B => N_1108, Y => flush2_RNIFMGM2); - - \r.flush2\ : DFN1 - port map(D => \faddr_RNID788NI[6]\, CLK => lclk_c, Q => - \flush2\); - - \r.waddress_RNO_0[14]\ : MX2C - port map(A => \address[14]\, B => fpc(14), S => - vaddress_0_sqmuxa_0, Y => N_1051); - - \r.underrun_RNO_2\ : OR2A - port map(A => underrun2, B => overrun_4, Y => underrun_1_0); - - \r.waddress_RNI3LUL_2[4]\ : AO1D - port map(A => dataout_2(2), B => \un95_res[2]\, C => - cacheon_1, Y => N_1022); - - \r.waddress[8]\ : DFN1 - port map(D => \waddress_1[8]\, CLK => lclk_c, Q => - \address[8]\); - - \r.istate_RNO_2[1]\ : OR3A - port map(A => \istate[0]\, B => \istate[1]\, C => N_66_0, Y - => N_1348); - - \r.flush_RNO\ : OA1 - port map(A => N_1214, B => \un1_ici\, C => rst, Y => - flush_RNO); - - \r.vaddress[3]\ : DFN1 - port map(D => \vaddress_1[3]\, CLK => lclk_c, Q => - \vaddress[3]\); - - \r.istate_RNIVDCAH[0]\ : MX2 - port map(A => hrdata_0_15, B => dataout_1(15), S => - istate_1259_d_0, Y => data_0(15)); - - \r.istate_RNIU60D8[0]\ : MX2 - port map(A => hrdata_0_9, B => dataout_1(9), S => - istate_1259_d_0, Y => data_0(9)); - - \r.valid_RNIQB2H2[4]\ : MX2B - port map(A => \vmask_6[4]\, B => maddress(4), S => - diagen_0_sqmuxa, Y => N_1106); - - \r.faddr_RNO[6]\ : NOR2B - port map(A => \flush2\, B => I_31_0, Y => \faddr_1[6]\); - - \r.vaddress[15]\ : DFN1E1 - port map(D => fpc(15), CLK => lclk_c, E => - vaddress_0_sqmuxa_1, Q => \vaddress[15]\); - - \r.istate_RNO_0[0]\ : OA1 - port map(A => N_1350, B => underrun2, C => - \istate_0_sqmuxa\, Y => \istate_ns_0_0[0]\); - - \r.istate_RNIEON21_19[0]\ : MX2 - port map(A => dataout_2(23), B => dataout_1(27), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_27); - - \r.istate_RNIEON21_21[0]\ : MX2 - port map(A => dataout_2(19), B => dataout_1(23), S => - \cdwrite_0_sqmuxa_i_0_0\, Y => diagdata_23); - - \r.waddress_RNO[5]\ : MX2C - port map(A => N_1042, B => un1_m0_3, S => error_1_sqmuxa_0, - Y => \waddress_1[5]\); - - \r.valid_RNIM32H2[2]\ : MX2C - port map(A => \vmask_6[2]\, B => maddress(2), S => - diagen_0_sqmuxa_0, Y => N_1104); - - \r.waddress_RNO_0[10]\ : MX2C - port map(A => \address[10]\, B => fpc(10), S => - vaddress_0_sqmuxa_1, Y => N_1047); - - \r.waddress_RNO[28]\ : MX2C - port map(A => N_1065, B => N_321, S => error_1_sqmuxa_0, Y - => \waddress_1[28]\); - - \r.vaddress[27]\ : DFN1E1 - port map(D => fpc(27), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[27]\); - - \r.istate_RNIA8N5H[0]\ : MX2 - port map(A => hrdata_0_15, B => maddress(15), S => idle_0, - Y => istate_RNIA8N5H(0)); - - \r.vaddress[4]\ : DFN1 - port map(D => \vaddress_1[4]\, CLK => lclk_c, Q => - \vaddress[4]\); - - \r.vaddress[20]\ : DFN1E1 - port map(D => fpc(20), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[20]\); - - \r.vaddress_RNI3BBN[31]\ : MX2 - port map(A => \vaddress[31]\, B => maddress(31), S => - diagen_0_sqmuxa, Y => N_987); - - \r.flush2_0_0_RNIPJ5O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1102, Y => - flush2_0_0_RNIPJ5O2); - - \r.waddress_RNO_0[29]\ : MX2C - port map(A => \address[29]\, B => fpc(29), S => - vaddress_0_sqmuxa_0, Y => N_1066); - - \r.waddress_RNO_0[13]\ : MX2C - port map(A => \address[13]\, B => fpc(13), S => - vaddress_0_sqmuxa_0, Y => N_1050); - - \r.waddress_RNO_0[8]\ : MX2C - port map(A => \address[8]\, B => fpc(8), S => - vaddress_0_sqmuxa_0, Y => N_1045); - - \r.valid_RNO[0]\ : MX2 - port map(A => \vmask_6[0]\, B => dataout_2(0), S => - twrite_3, Y => \valid_1[0]\); - - \r.istate_RNIEON21_3[0]\ : MX2 - port map(A => dataout_2(15), B => dataout_1(19), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_19); - - \r.waddress[31]\ : DFN1 - port map(D => \waddress_1[31]\, CLK => lclk_c, Q => - \address[31]\); - - \r.flush2_0_0_RNI146O2\ : NOR2 - port map(A => \un1_p0_2_0[148]\, B => N_1106, Y => - flush2_0_0_RNI146O2); - - \r.valid_RNIUJ2H2[6]\ : MX2B - port map(A => \vmask_6[6]\, B => maddress(6), S => - diagen_0_sqmuxa, Y => N_1108); - - \r.istate_RNITTUI[0]\ : MX2C - port map(A => fpc(4), B => addr(4), S => diagen_0_sqmuxa_0, - Y => N_1123); - - \r.waddress_RNO_0[21]\ : MX2C - port map(A => \address[21]\, B => fpc(21), S => - vaddress_0_sqmuxa_1, Y => N_1058); - - \r.valid_RNO[7]\ : MX2A - port map(A => \vmask_6[7]\, B => dataout_2(7), S => - twrite_3, Y => \valid_1[7]\); - - \r.vaddress[2]\ : DFN1 - port map(D => \vaddress_1[2]\, CLK => lclk_c, Q => - \vaddress[2]\); - - \r.overrun_RNO_0\ : MX2 - port map(A => overrun_4, B => overrun, S => istate_1259_d, - Y => N_1212); - - \ictrl.0.un1_icramo_0_0\ : XNOR2 - port map(A => dataout_1(28), B => ctx_0_d0, Y => - un1_icramo_0_i); - - \r.istate_RNI5UVI[0]\ : MX2C - port map(A => fpc(8), B => addr(8), S => diagen_0_sqmuxa, Y - => N_1127); - - \r.waddress_RNI3LUL_4[4]\ : OA1B - port map(A => \un95_res[6]\, B => dataout_2(6), C => - cacheon_1, Y => N_1026); - - \r.istate_RNIG2KP8[0]\ : MX2 - port map(A => hrdata_25, B => dataout_2(30), S => - istate_1259_d_0, Y => data_0(30)); - - \r.holdn_RNIFCHA_0\ : CLKINT - port map(A => holdn_RNIFCHA, Y => holdn); - - \r.waddress_RNI3LUL_6[4]\ : OA1B - port map(A => \un95_res[7]\, B => dataout_2(7), C => - cacheon_1, Y => N_1027); - - \r.flush2_RNIJENP\ : OR2A - port map(A => N_1346_1, B => istate_1259_d_0, Y => N_1350); - - \r.burst_RNIHK5U1\ : NOR3C - port map(A => burst, B => \burst_0\, C => un1_mcio_1_i_0, Y - => req_7_1); - - \r.hit\ : DFN1 - port map(D => hit_RNO, CLK => lclk_c, Q => hit); - - \r.faddr[4]\ : DFN1E1 - port map(D => \faddr_1[4]\, CLK => lclk_c, E => - vitdatain_0_1_0(22), Q => \faddr[4]\); - - \r.valid_RNIL7DS1[1]\ : MX2C - port map(A => N_1011, B => N_1021, S => N_1028_i, Y => - \vmask_6[1]\); - - \r.burst_RNIO5BQ21\ : AOI1B - port map(A => underrun_2, B => cacheon_1, C => req_7_1, Y - => req_7); - - \r.waddress_RNO[6]\ : MX2C - port map(A => N_1043, B => un1_m0_4, S => error_1_sqmuxa_0, - Y => \waddress_1[6]\); - - \r.istate_RNI06RLB[0]\ : MX2 - port map(A => hrdata_0_3, B => dataout_1(3), S => - istate_1259_d, Y => data_0(3)); - - \r.flush_RNIAUIQ3\ : NOR3B - port map(A => twrite_3_iv_2, B => mexc, C => cacheon_1, Y - => twrite_3_iv_4); - - \ictrl.0.un1_ici_3_0\ : XNOR2 - port map(A => dataout_2(11), B => fpc(15), Y => - un1_ici_3_i_0); - - \un1_r.faddr_I_5\ : XOR2 - port map(A => \faddr[0]\, B => \faddr[1]\, Y => I_5_0); - - \r.burst_RNO_2\ : OR3C - port map(A => ready, B => \istate[1]\, C => grant, Y => - burst_2_sqmuxa); - - \ictrl.valid_1_4\ : MX2 - port map(A => dataout_2(1), B => dataout_2(5), S => fpc(4), - Y => N_963); - - \r.flush_RNI1B573\ : NOR3C - port map(A => hit_1_10, B => hit_1_9, C => hit_1_16, Y => - hit_1_18); - - \r.faddr_RNISJSHQA[2]\ : MX2A - port map(A => \taddr_9[7]\, B => \faddr[2]\, S => \flush2\, - Y => faddr_RNISJSHQA(2)); - - \r.valid_RNINTEC[5]\ : AO1 - port map(A => hit, B => \valid[5]\, C => \un95_res[5]\, Y - => N_1015); - - \r.vaddress[23]\ : DFN1E1 - port map(D => fpc(23), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[23]\); - - \ictrl.0.un1_ici_10_0_RNICJUL1\ : NOR3C - port map(A => hit_1_8, B => hit_1_7, C => hit_1_13, Y => - hit_1_17); - - \r.vaddress[5]\ : DFN1E1 - port map(D => fpc(5), CLK => lclk_c, E => vaddress_0_sqmuxa, - Q => \vaddress[5]\); - - \r.istate_RNIJGCD_2[0]\ : OR2A - port map(A => \istate[0]\, B => \istate[1]\, Y => N_1320); - - \r.waddress_RNO[25]\ : MX2C - port map(A => N_1062, B => N_2626, S => error_1_sqmuxa, Y - => \waddress_1[25]\); - - \r.istate_RNI7E0781[0]\ : OR3A - port map(A => istate_0_sqmuxa_0_a3_m6_5, B => - xc_exception_1_0, C => ldlock_2, Y => \istate_0_sqmuxa\); - - \r.istate_RNIEON21_10[0]\ : MX2 - port map(A => dataout_0(35), B => dataout_1(8), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_8); - - \r.flush_RNIVHR2A\ : NOR3B - port map(A => valid_1, B => hit_1, C => cacheon_1, Y => - un5_eholdn); - - \ictrl.0.un1_icramo_1_0_0\ : XNOR2 - port map(A => dataout_1(29), B => ctx_1, Y => - un1_icramo_1_0_i); - - \r.waddress_RNO_0[26]\ : MX2C - port map(A => \address[26]\, B => fpc(26), S => - vaddress_0_sqmuxa_0, Y => N_1063); - - \r.trans_op_RNO_2\ : OR2B - port map(A => flush_op_i_0, B => trans_op_0_a2_0, Y => - trans_op_RNO_2); - - \r.flush_RNIRF2B91\ : NOR2 - port map(A => e, B => holdn_0_sqmuxa_1, Y => - istate_1_sqmuxa); - - \r.waddress[27]\ : DFN1 - port map(D => \waddress_1[27]\, CLK => lclk_c, Q => - \address[27]\); - - \ictrl.v.burst_1_iv_RNO_3\ : NOR2B - port map(A => \req\, B => \istate[1]\, Y => burst_5_m_0); - - \r.istate_RNIIMI4I1[0]\ : NOR3A - port map(A => un5_m_en, B => N_66, C => N_1320, Y => - error_1_sqmuxa_0); - - \r.vaddress_RNIP1HGO9[6]\ : MX2 - port map(A => N_28, B => \vaddress[6]\, S => - taddr_0_sqmuxa_1, Y => N_1147); - - \r.istate_RNI760J[0]\ : MX2C - port map(A => fpc(9), B => addr(9), S => diagen_0_sqmuxa, Y - => N_1128); - - \ictrl.0.un1_ici_10_0_RNI3305\ : AND2 - port map(A => un1_ici_11_i_0, B => un1_ici_10_i_0, Y => - hit_1_6); - - \r.valid[3]\ : DFN1E0 - port map(D => \valid_1[3]\, CLK => lclk_c, E => - valid_1_sqmuxa, Q => \valid[3]\); - - \ictrl.hit_1_1\ : XA1A - port map(A => fpc(28), B => dataout_2(24), C => - un1_ici_0_i_0, Y => hit_1_1); - - \r.istate_RNIEON21_7[0]\ : MX2 - port map(A => dataout_2(11), B => dataout_1(15), S => - cdwrite_0_sqmuxa_i_0, Y => diagdata_15); - - \r.faddr_RNIKVTLT9[1]\ : MX2A - port map(A => \taddr_9[6]\, B => \faddr[1]\, S => - \un1_p0_2_0[148]\, Y => faddr_RNIKVTLT9(1)); - - \r.waddress_RNO[11]\ : MX2C - port map(A => N_1048, B => un1_m0_9, S => error_1_sqmuxa, Y - => \waddress_1[11]\); - - \r.istate_RNIVR9M[0]\ : OR2A - port map(A => diagen_0_sqmuxa, B => asi(0), Y => - cdwrite_0_sqmuxa_i_0); - - \r.istate_RNIO6LI[0]\ : OR2A - port map(A => idle, B => hold, Y => taddr_0_sqmuxa); - - \r.valid_RNIM7DS1[2]\ : MX2C - port map(A => N_1012, B => N_1022, S => N_1028_i, Y => - \vmask_6[2]\); - - \r.vaddress_RNIIE0GIE[9]\ : MX2C - port map(A => rpc_7, B => \vaddress[9]\, S => - taddr_0_sqmuxa_1, Y => N_1150); - - \r.valid_RNO[5]\ : MX2A - port map(A => \vmask_6[5]\, B => dataout_2(5), S => - twrite_3, Y => \valid_1[5]\); - - \r.waddress[10]\ : DFN1 - port map(D => \waddress_1[10]\, CLK => lclk_c, Q => - \address[10]\); - - \r.waddress[14]\ : DFN1 - port map(D => \waddress_1[14]\, CLK => lclk_c, Q => - \address[14]\); - - \r.vaddress[25]\ : DFN1E1 - port map(D => fpc(25), CLK => lclk_c, E => - vaddress_0_sqmuxa, Q => \vaddress[25]\); - - \r.vaddress_RNISNAKMI[21]\ : NOR2 - port map(A => \un1_ici\, B => N_977, Y => - vaddress_RNISNAKMI(21)); - - \ictrl.0.un1_ici_11_0\ : XNOR2 - port map(A => fpc(23), B => dataout_2(19), Y => - un1_ici_11_i_0); - - \r.vaddress_RNI4GAKMI[18]\ : NOR2 - port map(A => \un1_ici\, B => N_974, Y => - vaddress_RNI4GAKMI(18)); - - \r.waddress_RNO_0[22]\ : MX2C - port map(A => \address[22]\, B => fpc(22), S => - vaddress_0_sqmuxa_1, Y => N_1059); - - \r.vaddress_RNIR2BN[20]\ : MX2C - port map(A => \vaddress[20]\, B => maddress(20), S => - diagen_0_sqmuxa, Y => N_976); - - \r.istate_RNIVTQIJ[0]\ : MX2 - port map(A => N_262_0, B => maddress(20), S => idle, Y => - istate_RNIVTQIJ(0)); - - \r.istate_RNIENB3M[0]\ : MX2 - port map(A => hrdata_26, B => maddress(31), S => idle_0, Y - => istate_RNIENB3M(0)); - - \r.waddress_RNO_0[18]\ : MX2C - port map(A => \address[18]\, B => fpc(18), S => - vaddress_0_sqmuxa_0, Y => N_1055); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutw is - - port( data_1 : out std_logic_vector(31 downto 12); - address : out std_logic_vector(31 downto 2); - twowner : in std_logic_vector(0 to 0); - twowner_2 : in std_logic_vector(0 to 0); - aaddr_0_25 : in std_logic; - aaddr_0_24 : in std_logic; - aaddr_0_29 : in std_logic; - aaddr_0_18 : in std_logic; - aaddr_0_17 : in std_logic; - aaddr_0_9 : in std_logic; - aaddr_0_8 : in std_logic; - aaddr_0_7 : in std_logic; - aaddr_0_4 : in std_logic; - aaddr_0_0 : in std_logic; - aaddr_0_21 : in std_logic; - aaddr_0_22 : in std_logic; - aaddr_0_23 : in std_logic; - aaddr_0_28 : in std_logic; - aaddr_0_27 : in std_logic; - aaddr_0_26 : in std_logic; - aaddr_0_20 : in std_logic; - aaddr_0_19 : in std_logic; - aaddr_0_16 : in std_logic; - aaddr_0_15 : in std_logic; - aaddr_0_14 : in std_logic; - aaddr_0_13 : in std_logic; - aaddr_0_12 : in std_logic; - aaddr_0_11 : in std_logic; - aaddr_0_10 : in std_logic; - aaddr_0_6 : in std_logic; - aaddr_0_3 : in std_logic; - aaddr_0_2 : in std_logic; - aaddr_0_1 : in std_logic; - aaddr_25 : in std_logic; - aaddr_24 : in std_logic; - aaddr_29 : in std_logic; - aaddr_18 : in std_logic; - aaddr_17 : in std_logic; - aaddr_9 : in std_logic; - aaddr_8 : in std_logic; - aaddr_7 : in std_logic; - aaddr_4 : in std_logic; - aaddr_0_d0 : in std_logic; - aaddr_21 : in std_logic; - aaddr_22 : in std_logic; - aaddr_23 : in std_logic; - aaddr_28 : in std_logic; - aaddr_27 : in std_logic; - aaddr_26 : in std_logic; - aaddr_20 : in std_logic; - aaddr_19 : in std_logic; - aaddr_16 : in std_logic; - aaddr_15 : in std_logic; - aaddr_14 : in std_logic; - aaddr_13 : in std_logic; - aaddr_12 : in std_logic; - aaddr_11 : in std_logic; - aaddr_10 : in std_logic; - aaddr_6 : in std_logic; - aaddr_3 : in std_logic; - aaddr_2 : in std_logic; - aaddr_1 : in std_logic; - twowner_1 : in std_logic_vector(0 to 0); - data_0 : in std_logic_vector(31 downto 12); - data_11 : out std_logic; - data_10 : out std_logic; - data_9 : out std_logic; - data_8 : out std_logic; - data_7 : out std_logic; - data_6 : out std_logic; - data_4 : out std_logic; - data_3 : out std_logic; - data_2 : out std_logic; - data_1_d0 : out std_logic; - data_0_d0 : out std_logic; - data_12 : in std_logic; - data_18 : in std_logic; - data_24 : in std_logic; - data_16 : in std_logic; - data_22 : in std_logic; - data_28 : in std_logic; - data_20 : in std_logic; - data_26 : in std_logic; - data_17 : in std_logic; - data_15 : in std_logic; - data_14 : in std_logic; - data_13 : in std_logic; - data_23 : in std_logic; - data_29 : in std_logic; - data_30 : in std_logic; - data_31 : in std_logic; - data_21 : in std_logic; - data_27 : in std_logic; - data_19 : in std_logic; - data_25 : in std_logic; - adata_0_19 : in std_logic; - adata_0_20 : in std_logic; - adata_0_18 : in std_logic; - adata_0_10 : in std_logic; - adata_0_2 : in std_logic; - adata_0_13 : in std_logic; - adata_0_14 : in std_logic; - adata_0_30 : in std_logic; - adata_0_29 : in std_logic; - adata_0_28 : in std_logic; - adata_0_6 : in std_logic; - adata_0_1 : in std_logic; - adata_0_0 : in std_logic; - adata_0_31 : in std_logic; - adata_0_17 : in std_logic; - adata_0_7 : in std_logic; - adata_0_25 : in std_logic; - adata_0_22 : in std_logic; - adata_0_11 : in std_logic; - adata_0_24 : in std_logic; - adata_0_23 : in std_logic; - adata_0_15 : in std_logic; - adata_0_12 : in std_logic; - adata_0_21 : in std_logic; - adata_0_16 : in std_logic; - adata_0_9 : in std_logic; - adata_0_8 : in std_logic; - adata_0_26 : in std_logic; - adata_0_27 : in std_logic; - adata_0_4 : in std_logic; - adata_0_3 : in std_logic; - adata_19 : in std_logic; - adata_20 : in std_logic; - adata_18 : in std_logic; - adata_10 : in std_logic; - adata_2 : in std_logic; - adata_13 : in std_logic; - adata_14 : in std_logic; - adata_30 : in std_logic; - adata_29 : in std_logic; - adata_28 : in std_logic; - adata_6 : in std_logic; - adata_1 : in std_logic; - adata_0_d0 : in std_logic; - adata_31 : in std_logic; - adata_17 : in std_logic; - adata_7 : in std_logic; - adata_25 : in std_logic; - adata_22 : in std_logic; - adata_11 : in std_logic; - adata_24 : in std_logic; - adata_23 : in std_logic; - adata_15 : in std_logic; - adata_12 : in std_logic; - adata_21 : in std_logic; - adata_16 : in std_logic; - adata_9 : in std_logic; - adata_8 : in std_logic; - adata_26 : in std_logic; - adata_27 : in std_logic; - adata_4 : in std_logic; - adata_3 : in std_logic; - twowner_0 : in std_logic_vector(0 to 0); - lvl_i_1 : out std_logic_vector(1 downto 0); - ctx_0_d0 : in std_logic; - ctx_1 : in std_logic; - ctx_2 : in std_logic; - ctx_3 : in std_logic; - ctx_6 : in std_logic; - ctx_7 : in std_logic; - hrdata : in std_logic_vector(6 downto 5); - iosn_0 : in std_logic_vector(93 to 93); - ctx_0 : in std_logic_vector(5 downto 4); - ctxp : in std_logic_vector(25 downto 0); - hrdata_0_3 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_27 : in std_logic; - lvl_i_1_0 : out std_logic_vector(1 to 1); - lclk_c : in std_logic; - grant : in std_logic; - N_264_0 : in std_logic; - N_262_0 : in std_logic; - N_82 : out std_logic; - N_80 : out std_logic; - N_709 : in std_logic; - finish : out std_logic; - N_78_0 : in std_logic; - d_N_6_1 : out std_logic; - N_2563_i_0_a4_m7_0_a2_1 : out std_logic; - fault_trans_i_2 : out std_logic; - walk_op_2_0_0_o2_0 : out std_logic; - N_2488 : in std_logic; - N_2487 : in std_logic; - read : out std_logic; - bo_5842_d_0 : in std_logic; - ba : in std_logic; - req : out std_logic; - inv_1_0_a2_0_a2_0 : out std_logic; - rst : in std_logic; - mexc : in std_logic; - fault_mexc : out std_logic; - N_2484 : in std_logic; - N_2485 : in std_logic; - N_207 : out std_logic - ); - -end mmutw; - -architecture DEF_ARCH of mmutw is - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_456_0, N_206, N_365, N_215_0, N_204_0, N_366, - N_366_0, N_388_0, N_210, \state_i[5]\, N_226, \state[4]\, - walk_op, \N_207\, fault_mexc_1_0_a2_0_a2_0, - \addr_1_i_i_0[31]\, N_610, \addr_1_i_i_0[26]\, N_622, - \addr_1_i_i_0[27]\, N_625, \addr_1_i_i_0[10]\, N_712, - N_652, \addr_1_i_i_0[11]\, N_309, \addr_1_i_i_0[19]\, - N_721, N_331, \addr_1_i_i_0[20]\, N_722, N_334, - \addr_1_i_i_0_0[9]\, \addr_1_i_i_0_tz[9]\, N_589, - \addr_1_1_0_0[2]\, N_369, N_626, N_355, - \addr_1_i_i_0[23]\, N_725, N_596, \addr_1_i_i_0[24]\, - N_726, N_599, \addr_1_i_i_0[21]\, N_592, - \addr_1_i_i_0[22]\, N_595, \addr_1_i_i_0[29]\, N_728, - N_602, \addr_1_i_i_0[30]\, N_729, N_605, - \addr_1_i_i_0[25]\, N_619, \addr_1_i_i_0[28]\, N_727, - N_627, \addr_1_i_i_0[12]\, N_714, N_310, - \addr_1_i_i_0[13]\, N_715, N_313, \addr_1_i_i_0[14]\, - N_716, N_316, \addr_1_i_i_0[15]\, N_321, - \addr_1_i_i_0[16]\, N_324, \addr_1_i_i_0[17]\, N_719, - N_325, \addr_1_i_i_0[18]\, N_330, \addr_1_i_i_0_0[8]\, - \addr_1_i_i_0_tz[8]\, N_586, \addr_1_1_0_0[5]\, N_629, - N_343, \addr_1_1_0_0[4]\, N_628, N_347, \addr_1_1_0_0[3]\, - N_627_0, N_351, \addr_1_i_0_0[6]\, \addr_1_i_0_a2_1[6]\, - N_339, \addr_1_i_i_1[7]\, \addr_1_i_i_o2_0[7]\, N_361, - \addr_1_i_i_0[7]\, N_647, N_358, \addr_1_i_i_a2_2_0[7]\, - N_225, addr_1_1_0_a2_3_5_m2_0, \state[1]\, - \state_ns_0_0_0_a2_0[0]\, walk_op_2_0_0_a2_1_0, - \state[0]\, fault_trans_1_i_0_0_0, req_2_0_0_a2_0_0, - \fault_lvl_1_0_iv_0_a2_i_o2_0[0]\, \req\, - \state_RNIP074T3_0[0]\, N_189, N_205, \addr_1[3]\, N_349, - N_352, \addr_1[4]\, N_345, N_348, \addr_1[5]\, N_341, - N_344, N_11, N_53_1, N_178, N_176, N_174, N_172, N_170, - N_168, N_166, N_582, N_579, N_43, N_39, N_17, N_15, N_651, - N_630, N_645, N_648, N_617, walk_op_RNO, N_646, N_35, - N_23, N_204, \addr_1[2]\, N_353, N_356, N_479, N_338, - N_340, N_13, N_56_1, N_182, N_180, N_164, N_159, N_581, - N_580, N_47, N_231, N_370, \state_i_RNIJP3JC1[5]\, - \state[3]\, N_592_0, N_611, \state_ns_i_0_0_0[2]\, N_386, - \walk_op_2_0_0_o2_0\, \state_nss[1]\, N_633, N_634, - \state_nss[2]\, N_637, \state_nss[4]\, N_642, N_641, - \state_nss[5]\, N_644, N_643, N_710, N_723, N_724, N_220, - N_737, N_388, N_639, N_364, N_367, \state[2]\, N_717, - N_718, N_720, N_230, N_707, N_229, N_706, N_228, N_705, - N_362, N_232, read_RNO, N_215, N_591, N_589_0, N_659, - N_648_0, N_619_0, N_590, N_660, N_618, N_100, N_101, - N_588, N_610_0, N_621, N_622_0, N_624, N_625_0, N_642_0, - N_644_0, N_645_0, N_646_0, N_652_0, N_654, N_655, N_668, - N_669, N_702, N_731, N_3142, N_3143, N_3144, N_3145, - N_3146, \adata_1[14]\, N_643_0, N_99, N_640, - \state_nss[3]\, \state_nss_i_0[0]\, \finish\, N_698, - N_649, N_609, N_623, N_697, N_670, N_653, N_649_0, - req_RNO_0, N_704, N_673, N_616, N_227, N_711, N_730, - N_3148, N_3149, N_713, N_708, \read\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - finish <= \finish\; - walk_op_2_0_0_o2_0 <= \walk_op_2_0_0_o2_0\; - read <= \read\; - req <= \req\; - N_207 <= \N_207\; - - \r.wb.data[11]\ : DFN1E0 - port map(D => N_652_0, CLK => lclk_c, E => N_215_0, Q => - data_11); - - \r.wb.addr_RNO_5[4]\ : MX2C - port map(A => N_659, B => N_648_0, S => twowner_0(0), Y => - N_229); - - \r.wb.addr_RNO_0[30]\ : OA1A - port map(A => N_729, B => N_388_0, C => N_605, Y => - \addr_1_i_i_0[30]\); - - \r.walk_op_2_0_0_o2_0\ : OR2A - port map(A => hrdata_0_0, B => mexc, Y => - \walk_op_2_0_0_o2_0\); - - \r.wb.addr_RNO_0[10]\ : OA1A - port map(A => N_712, B => N_388_0, C => N_652, Y => - \addr_1_i_i_0[10]\); - - \r.wb.data[10]\ : DFN1E0 - port map(D => N_623, CLK => lclk_c, E => N_215_0, Q => - data_10); - - \r.walk_op_RNO_2\ : OR3A - port map(A => rst, B => N_206, C => walk_op, Y => N_646); - - \r.wb.addr_RNO_2[27]\ : MX2 - port map(A => aaddr_25, B => aaddr_0_25, S => twowner(0), Y - => N_3149); - - \r.wb.data[22]\ : DFN1E0 - port map(D => N_654, CLK => lclk_c, E => N_215, Q => - data_1(22)); - - \r.req_RNO\ : AO1B - port map(A => req_2_0_0_a2_0_0, B => grant, C => N_649_0, Y - => req_RNO_0); - - \r.wb.data_RNO[6]\ : MX2 - port map(A => adata_6, B => adata_0_6, S => twowner_2(0), Y - => N_3143); - - \r.wb.data_RNO[15]\ : MX2 - port map(A => adata_15, B => adata_0_15, S => twowner_1(0), - Y => N_644_0); - - \r.wb.addr_RNO_7[4]\ : MX2C - port map(A => data_0(26), B => data_0(20), S => \state[2]\, - Y => N_659); - - \r.state_RNIODA9G2_0[0]\ : OR2A - port map(A => N_206, B => N_365, Y => N_366_0); - - \r.req\ : DFN1 - port map(D => req_RNO_0, CLK => lclk_c, Q => \req\); - - \r.wb.addr_RNO_0[13]\ : OA1A - port map(A => N_715, B => N_388_0, C => N_313, Y => - \addr_1_i_i_0[13]\); - - \r.wb.addr_RNO_1[15]\ : OR2A - port map(A => N_717, B => N_388, Y => N_321); - - \r.wb.addr_RNO[30]\ : AO1C - port map(A => N_204_0, B => ctxp(24), C => - \addr_1_i_i_0[30]\, Y => N_43); - - \r.state_RNO_0[4]\ : OA1B - port map(A => N_386, B => \state[4]\, C => \N_207\, Y => - N_633); - - \r.wb.addr_RNO_3[9]\ : OR2A - port map(A => N_711, B => N_388, Y => N_589); - - \r.walk_op_RNIO4TR1\ : NOR2 - port map(A => walk_op, B => \N_207\, Y => N_367); - - \r.wb.data_RNO[1]\ : MX2 - port map(A => adata_1, B => adata_0_1, S => twowner_2(0), Y - => N_3142); - - \r.wb.data[15]\ : DFN1E0 - port map(D => N_644_0, CLK => lclk_c, E => N_215_0, Q => - data_1(15)); - - \r.req_RNO_1\ : OR2B - port map(A => rst, B => N_456_0, Y => N_649_0); - - \r.state_RNIULR8[4]\ : OR3A - port map(A => walk_op, B => \state[0]\, C => \state[4]\, Y - => N_2563_i_0_a4_m7_0_a2_1); - - \r.wb.data_RNO[28]\ : MX2 - port map(A => adata_28, B => adata_0_28, S => twowner_2(0), - Y => N_3144); - - \r.wb.addr_RNO_2[3]\ : OR2A - port map(A => ctx_1, B => N_204, Y => N_352); - - \r.wb.addr_RNO_1[14]\ : MX2 - port map(A => aaddr_12, B => aaddr_0_12, S => twowner_2(0), - Y => N_716); - - \r.state_RNO_1[0]\ : OAI1 - port map(A => N_364, B => N_367, C => \state[1]\, Y => - N_643); - - \r.state_RNIMR2IG2[1]\ : NOR3 - port map(A => N_365, B => addr_1_1_0_a2_3_5_m2_0, C => - \state_i_RNIJP3JC1[5]\, Y => N_369); - - \r.walk_op_RNO_0\ : OR3A - port map(A => walk_op_2_0_0_a2_1_0, B => hrdata_0_1, C => - \walk_op_2_0_0_o2_0\, Y => N_648); - - \r.wb.addr_RNO_10[6]\ : MX2C - port map(A => data_16, B => data_0(16), S => twowner(0), Y - => N_609); - - \r.wb.data_RNO[19]\ : MX2 - port map(A => adata_19, B => adata_0_19, S => twowner(0), Y - => N_653); - - \r.wb.addr_RNO_2[11]\ : MX2 - port map(A => aaddr_9, B => aaddr_0_9, S => twowner(0), Y - => N_713); - - \r.wb.addr_RNO_1[30]\ : MX2 - port map(A => aaddr_28, B => aaddr_0_28, S => twowner_2(0), - Y => N_729); - - \r.wb.addr_RNO_0[26]\ : OA1A - port map(A => hrdata_0_22, B => N_366_0, C => N_622, Y => - \addr_1_i_i_0[26]\); - - \r.wb.addr[19]\ : DFN1E1 - port map(D => N_180, CLK => lclk_c, E => N_456_0, Q => - address(19)); - - \r.wb.addr[31]\ : DFN1E1 - port map(D => N_47, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(31)); - - \r.wb.addr_RNO_0[19]\ : OA1A - port map(A => N_721, B => N_388_0, C => N_331, Y => - \addr_1_i_i_0[19]\); - - \r.wb.addr_RNO_2[26]\ : MX2 - port map(A => aaddr_24, B => aaddr_0_24, S => twowner(0), Y - => N_3148); - - \r.wb.addr_RNO_0[20]\ : OA1A - port map(A => N_722, B => N_388_0, C => N_334, Y => - \addr_1_i_i_0[20]\); - - \r.wb.data[27]\ : DFN1E0 - port map(D => N_588, CLK => lclk_c, E => N_215, Q => - data_1(27)); - - \r.wb.addr_RNO_5[5]\ : MX2C - port map(A => N_619_0, B => N_590, S => twowner_0(0), Y => - N_230); - - \r.state_RNO[3]\ : NOR3A - port map(A => rst, B => N_637, C => \state_ns_i_0_0_0[2]\, - Y => \state_nss[2]\); - - \r.wb.read_RNO_0\ : OR3C - port map(A => rst, B => \read\, C => N_215_0, Y => N_651); - - \r.wb.addr_RNO_2[2]\ : OR2A - port map(A => ctx_0_d0, B => N_204, Y => N_356); - - \r.wb.addr_RNO_4[7]\ : MX2C - port map(A => N_660, B => N_618, S => twowner_0(0), Y => - N_232); - - \r.req_RNI7PUC\ : NOR2A - port map(A => ba, B => \req\, Y => - \fault_lvl_1_0_iv_0_a2_i_o2_0[0]\); - - \r.wb.addr_RNO_2[20]\ : OR2A - port map(A => hrdata_0_16, B => N_366, Y => N_334); - - \r.wb.addr_RNO[26]\ : AO1C - port map(A => N_204, B => ctxp(20), C => \addr_1_i_i_0[26]\, - Y => N_580); - - \r.wb.addr_RNO[23]\ : AO1C - port map(A => N_204, B => ctxp(17), C => \addr_1_i_i_0[23]\, - Y => N_23); - - \r.wb.addr_RNO[17]\ : AO1C - port map(A => N_204_0, B => ctxp(11), C => - \addr_1_i_i_0[17]\, Y => N_176); - - \r.wb.addr[11]\ : DFN1E1 - port map(D => N_164, CLK => lclk_c, E => N_456_0, Q => - address(11)); - - \r.wb.data_RNO[4]\ : MX2 - port map(A => adata_4, B => adata_0_4, S => twowner_0(0), Y - => N_101); - - \r.wb.addr_RNO_0[23]\ : OA1A - port map(A => N_725, B => N_388_0, C => N_596, Y => - \addr_1_i_i_0[23]\); - - \r.wb.data_RNO[25]\ : MX2 - port map(A => adata_25, B => adata_0_25, S => twowner_1(0), - Y => N_655); - - \r.wb.addr_RNO[21]\ : AO1C - port map(A => N_204_0, B => ctxp(15), C => - \addr_1_i_i_0[21]\, Y => N_15); - - \p0.fault_mexc_1_0_a2_0_o2\ : NOR2 - port map(A => \state[4]\, B => walk_op, Y => N_226); - - \r.state_RNIUDO8[1]\ : OR2A - port map(A => \state[1]\, B => N_210, Y => - addr_1_1_0_a2_3_5_m2_0); - - \r.wb.addr_RNO[9]\ : AO1C - port map(A => N_204, B => N_56_1, C => \addr_1_i_i_0_0[9]\, - Y => N_13); - - \r.wb.addr_RNO_5[7]\ : MX2 - port map(A => data_17, B => data_0(17), S => twowner_1(0), - Y => N_647); - - \r.wb.addr_RNO_2[30]\ : OR2A - port map(A => hrdata_0_26, B => N_366, Y => N_605); - - \r.wb.addr_RNO_1[7]\ : AOI1B - port map(A => \addr_1_i_i_o2_0[7]\, B => N_361, C => - \addr_1_i_i_0[7]\, Y => \addr_1_i_i_1[7]\); - - \r.wb.addr[29]\ : DFN1E1 - port map(D => N_39, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(29)); - - \r.wb.addr_RNO_1[17]\ : MX2 - port map(A => aaddr_15, B => aaddr_0_15, S => twowner_2(0), - Y => N_719); - - \r.wb.addr_RNO_2[23]\ : OR2A - port map(A => N_264_0, B => N_366, Y => N_596); - - \r.wb.addr[9]\ : DFN1E1 - port map(D => N_13, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(9)); - - \r.wb.addr[13]\ : DFN1E1 - port map(D => N_168, CLK => lclk_c, E => N_456_0, Q => - address(13)); - - \r.wb.addr_RNO[7]\ : AO1B - port map(A => N_210, B => N_205, C => \addr_1_i_i_1[7]\, Y - => N_189); - - \r.wb.data[29]\ : DFN1E0 - port map(D => N_3145, CLK => lclk_c, E => N_215, Q => - data_1(29)); - - \r.wb.addr_RNO_2[12]\ : OR2A - port map(A => hrdata_0_8, B => N_366, Y => N_310); - - \r.wb.addr_RNO_0[2]\ : AOI1B - port map(A => N_369, B => N_626, C => N_355, Y => - \addr_1_1_0_0[2]\); - - \r.wb.addr_RNO_4[3]\ : OR2A - port map(A => N_705, B => N_388, Y => N_351); - - \r.wb.addr_RNO[14]\ : AO1C - port map(A => N_204_0, B => ctxp(8), C => - \addr_1_i_i_0[14]\, Y => N_170); - - \r.state_RNO[2]\ : AOI1B - port map(A => N_640, B => N_639, C => rst, Y => - \state_nss[3]\); - - \r.req_RNIL0FNH\ : NOR2A - port map(A => hrdata_0_0, B => \N_207\, Y => - fault_trans_1_i_0_0_0); - - \r.state_i_RNI1JSQC1_0[5]\ : AO1 - port map(A => N_2485, B => N_2484, C => \state_i[5]\, Y => - N_215_0); - - \r.wb.data_RNO[29]\ : MX2 - port map(A => adata_29, B => adata_0_29, S => twowner_2(0), - Y => N_3145); - - \r.wb.addr_RNO_0[29]\ : OA1A - port map(A => N_728, B => N_388_0, C => N_602, Y => - \addr_1_i_i_0[29]\); - - \r.state[1]\ : DFN1 - port map(D => \state_nss[4]\, CLK => lclk_c, Q => - \state[1]\); - - \r.state_RNO_0[3]\ : NOR2A - port map(A => N_206, B => \state[3]\, Y => N_637); - - \r.wb.data[13]\ : DFN1E0 - port map(D => N_643_0, CLK => lclk_c, E => N_215_0, Q => - data_1(13)); - - \r.wb.addr_RNO_0[4]\ : AOI1B - port map(A => N_369, B => N_628, C => N_347, Y => - \addr_1_1_0_0[4]\); - - \r.wb.addr_RNO_4[2]\ : OR2A - port map(A => N_704, B => N_388, Y => N_355); - - \r.wb.addr[7]\ : DFN1E1 - port map(D => N_189, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(7)); - - \r.state[2]\ : DFN1 - port map(D => \state_nss[3]\, CLK => lclk_c, Q => - \state[2]\); - - \r.wb.addr_RNO_0[6]\ : NOR3 - port map(A => hrdata_0_2, B => N_231, C => N_370, Y => - N_338); - - \r.wb.addr_RNO_2[29]\ : OR2A - port map(A => N_78_0, B => N_366_0, Y => N_602); - - \r.wb.addr[21]\ : DFN1E1 - port map(D => N_15, CLK => lclk_c, E => N_456_0, Q => - address(21)); - - \r.wb.addr_RNO_1[25]\ : OR2A - port map(A => N_737, B => N_388, Y => N_619); - - \r.state_RNO_0[0]\ : OR2B - port map(A => \state[0]\, B => \N_207\, Y => N_644); - - \r.state_i_RNO_1[5]\ : OR3B - port map(A => N_2484, B => N_2485, C => \state_i[5]\, Y => - \state_ns_0_0_0_a2_0[0]\); - - \r.wb.data_RNO[30]\ : MX2 - port map(A => adata_30, B => adata_0_30, S => twowner_2(0), - Y => N_3146); - - \r.wb.addr_RNO[2]\ : OR3C - port map(A => \addr_1_1_0_0[2]\, B => N_353, C => N_356, Y - => \addr_1[2]\); - - \r.state_RNO[0]\ : AOI1B - port map(A => N_644, B => N_643, C => rst, Y => - \state_nss[5]\); - - \r.wb.data_RNO[7]\ : MX2 - port map(A => adata_7, B => adata_0_7, S => twowner_1(0), Y - => N_668); - - \r.wb.addr_RNO_1[24]\ : MX2 - port map(A => aaddr_22, B => aaddr_0_22, S => twowner(0), Y - => N_726); - - GND_i : GND - port map(Y => \GND\); - - \r.req_RNIL0FNH_0\ : NOR2 - port map(A => \N_207\, B => hrdata_0_0, Y => - inv_1_0_a2_0_a2_0); - - \r.wb.addr_RNO_1[16]\ : OR2A - port map(A => N_718, B => N_388, Y => N_324); - - \r.wb.addr[23]\ : DFN1E1 - port map(D => N_23, CLK => lclk_c, E => N_456_0, Q => - address(23)); - - \r.wb.addr_RNO_3[2]\ : MX2 - port map(A => data_12, B => data_0(12), S => twowner(0), Y - => N_626); - - \p0.fault_mexc_1_0_a2_0_a2\ : NOR2 - port map(A => \N_207\, B => fault_mexc_1_0_a2_0_a2_0, Y => - fault_mexc); - - \r.state_RNI673HG2[0]\ : OR2A - port map(A => N_365, B => N_215_0, Y => N_388_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.wb.addr_RNO_0[18]\ : OA1A - port map(A => hrdata_0_14, B => N_366_0, C => N_330, Y => - \addr_1_i_i_0[18]\); - - \r.state_RNIP074T3_0[0]\ : OR3C - port map(A => N_206, B => N_365, C => N_215_0, Y => - \state_RNIP074T3_0[0]\); - - \r.wb.data[7]\ : DFN1E0 - port map(D => N_668, CLK => lclk_c, E => N_215, Q => data_7); - - \r.wb.addr_RNO_1[3]\ : OR2A - port map(A => N_228, B => N_370, Y => N_349); - - \r.wb.addr[5]\ : DFN1E1 - port map(D => \addr_1[5]\, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(5)); - - \r.wb.data[24]\ : DFN1E0 - port map(D => N_646_0, CLK => lclk_c, E => N_215, Q => - data_1(24)); - - \r.wb.addr_RNO[4]\ : OR3C - port map(A => \addr_1_1_0_0[4]\, B => N_345, C => N_348, Y - => \addr_1[4]\); - - \r.wb.addr_RNO_2[7]\ : OR2 - port map(A => N_366, B => N_232, Y => N_362); - - \r.wb.addr_RNO_1[10]\ : MX2 - port map(A => aaddr_8, B => aaddr_0_8, S => twowner(0), Y - => N_712); - - \r.state_RNI3M7021[4]\ : NOR3 - port map(A => N_386, B => \state[4]\, C => \state[0]\, Y - => N_220); - - \r.wb.addr_RNO_0[8]\ : OR2 - port map(A => ctxp(2), B => ctx_6, Y => N_53_1); - - \r.wb.data_RNO[16]\ : MX2 - port map(A => adata_16, B => adata_0_16, S => twowner_0(0), - Y => N_624); - - \r.walk_op\ : DFN1 - port map(D => walk_op_RNO, CLK => lclk_c, Q => walk_op); - - \r.wb.data_RNO[10]\ : MX2 - port map(A => adata_10, B => adata_0_10, S => twowner(0), Y - => N_623); - - \r.state_RNI3CNU1_0[3]\ : NOR2A - port map(A => N_210, B => \N_207\, Y => lvl_i_1_0(1)); - - \r.wb.addr_RNO_1[13]\ : MX2 - port map(A => aaddr_11, B => aaddr_0_11, S => twowner_1(0), - Y => N_715); - - \r.wb.addr_RNO[3]\ : OR3C - port map(A => \addr_1_1_0_0[3]\, B => N_349, C => N_352, Y - => \addr_1[3]\); - - \r.state_RNO_1[4]\ : NOR2A - port map(A => N_215_0, B => \state[4]\, Y => N_634); - - \r.wb.data_RNO[13]\ : MX2 - port map(A => adata_13, B => adata_0_13, S => twowner_2(0), - Y => N_643_0); - - \r.wb.data[18]\ : DFN1E0 - port map(D => N_697, CLK => lclk_c, E => N_215_0, Q => - data_1(18)); - - \r.wb.data_RNO[3]\ : MX2 - port map(A => adata_3, B => adata_0_3, S => twowner_0(0), Y - => N_100); - - \r.wb.addr_RNO_2[9]\ : AO1 - port map(A => \state[3]\, B => N_592_0, C => hrdata(5), Y - => \addr_1_i_i_0_tz[9]\); - - \r.wb.data[4]\ : DFN1E0 - port map(D => N_101, CLK => lclk_c, E => N_215, Q => data_4); - - \r.wb.addr_RNO_1[27]\ : OR2A - port map(A => N_3149, B => N_388, Y => N_625); - - \r.wb.addr_RNO_0[31]\ : OA1A - port map(A => hrdata_0_27, B => N_366_0, C => N_610, Y => - \addr_1_i_i_0[31]\); - - \r.wb.addr_RNO_0[11]\ : OA1A - port map(A => hrdata_0_7, B => N_366_0, C => N_309, Y => - \addr_1_i_i_0[11]\); - - \r.req_RNO_0\ : NOR2B - port map(A => \req\, B => rst, Y => req_2_0_0_a2_0_0); - - \r.wb.addr_RNO_0[28]\ : OA1A - port map(A => N_727, B => N_388_0, C => N_627, Y => - \addr_1_i_i_0[28]\); - - \r.state_RNIH34P31[4]\ : OR2 - port map(A => N_220, B => \N_207\, Y => \finish\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.wb.addr_RNO_5[9]\ : MX2 - port map(A => aaddr_7, B => aaddr_0_7, S => twowner(0), Y - => N_711); - - \r.wb.addr_RNO_1[19]\ : MX2 - port map(A => aaddr_17, B => aaddr_0_17, S => twowner(0), Y - => N_721); - - \r.state_RNO_1[2]\ : OAI1 - port map(A => N_364, B => N_367, C => \state[3]\, Y => - N_639); - - \r.wb.data_RNO[2]\ : MX2 - port map(A => adata_2, B => adata_0_2, S => twowner_2(0), Y - => N_99); - - \r.wb.addr_RNO[10]\ : AO1C - port map(A => N_204, B => ctxp(4), C => \addr_1_i_i_0[10]\, - Y => N_159); - - \r.wb.addr_RNO_2[28]\ : OR2A - port map(A => hrdata_0_24, B => N_366, Y => N_627); - - \r.wb.data_RNO[12]\ : MX2 - port map(A => adata_12, B => adata_0_12, S => twowner_1(0), - Y => N_642_0); - - \r.wb.addr_RNO_3[8]\ : OR2A - port map(A => N_710, B => N_388_0, Y => N_586); - - \r.wb.data[21]\ : DFN1E0 - port map(D => N_625_0, CLK => lclk_c, E => N_215, Q => - data_1(21)); - - \r.wb.addr_RNO_1[5]\ : OR2A - port map(A => N_230, B => N_370, Y => N_341); - - \r.wb.data_RNO[26]\ : MX2 - port map(A => adata_26, B => adata_0_26, S => twowner_0(0), - Y => N_610_0); - - \r.wb.data[20]\ : DFN1E0 - port map(D => N_670, CLK => lclk_c, E => N_215, Q => - data_1(20)); - - \r.wb.addr_RNO_2[5]\ : OR2A - port map(A => ctx_3, B => N_204, Y => N_344); - - \r.wb.data[16]\ : DFN1E0 - port map(D => N_624, CLK => lclk_c, E => N_215_0, Q => - data_1(16)); - - \r.wb.addr[14]\ : DFN1E1 - port map(D => N_170, CLK => lclk_c, E => N_456_0, Q => - address(14)); - - \r.wb.addr_RNO_4[4]\ : OR2A - port map(A => N_706, B => N_388, Y => N_347); - - \r.wb.addr[16]\ : DFN1E1 - port map(D => N_174, CLK => lclk_c, E => N_456_0, Q => - address(16)); - - \r.wb.addr_RNO_1[31]\ : OR2A - port map(A => N_730, B => N_388, Y => N_610); - - \r.wb.data_RNO[20]\ : MX2 - port map(A => adata_20, B => adata_0_20, S => twowner(0), Y - => N_670); - - \r.wb.addr_RNO_1[26]\ : OR2A - port map(A => N_3148, B => N_388, Y => N_622); - - \r.wb.data_RNO[31]\ : MX2 - port map(A => adata_31, B => adata_0_31, S => twowner_1(0), - Y => N_702); - - \r.wb.data[9]\ : DFN1E0 - port map(D => N_622_0, CLK => lclk_c, E => N_215, Q => - data_9); - - \r.wb.data_RNO[23]\ : MX2 - port map(A => adata_23, B => adata_0_23, S => twowner_1(0), - Y => N_645_0); - - \r.wb.addr_RNO[27]\ : AO1C - port map(A => N_204, B => ctxp(21), C => \addr_1_i_i_0[27]\, - Y => N_581); - - \r.wb.addr_RNO_0[21]\ : OA1A - port map(A => hrdata_0_17, B => N_366_0, C => N_592, Y => - \addr_1_i_i_0[21]\); - - \r.wb.addr_RNO_8[2]\ : MX2C - port map(A => data_0(24), B => data_0(18), S => \state[2]\, - Y => N_616); - - \r.wb.addr_RNO_1[20]\ : MX2 - port map(A => aaddr_18, B => aaddr_0_18, S => twowner(0), Y - => N_722); - - \r.wb.addr_RNO_0[12]\ : OA1A - port map(A => N_714, B => N_388_0, C => N_310, Y => - \addr_1_i_i_0[12]\); - - \r.wb.data[25]\ : DFN1E0 - port map(D => N_655, CLK => lclk_c, E => N_215, Q => - data_1(25)); - - \r.wb.addr[15]\ : DFN1E1 - port map(D => N_172, CLK => lclk_c, E => N_456_0, Q => - address(15)); - - \r.state_RNIODA9G2[0]\ : OR2A - port map(A => N_206, B => N_365, Y => N_366); - - \r.wb.addr[12]\ : DFN1E1 - port map(D => N_166, CLK => lclk_c, E => N_456_0, Q => - address(12)); - - \r.wb.data[8]\ : DFN1E0 - port map(D => N_621, CLK => lclk_c, E => N_215, Q => data_8); - - \r.wb.addr_RNO_2[21]\ : MX2 - port map(A => aaddr_19, B => aaddr_0_19, S => twowner_2(0), - Y => N_723); - - \r.wb.addr_RNO[12]\ : AO1C - port map(A => N_204_0, B => ctxp(6), C => - \addr_1_i_i_0[12]\, Y => N_166); - - \r.wb.addr_RNO_0[3]\ : AOI1B - port map(A => N_369, B => N_627_0, C => N_351, Y => - \addr_1_1_0_0[3]\); - - \r.state_i_RNIP074T3_0[5]\ : OR2B - port map(A => N_366, B => N_215_0, Y => N_204_0); - - \r.wb.addr_RNO_6[6]\ : MX2C - port map(A => data_0(28), B => data_0(22), S => \state[2]\, - Y => N_649); - - \r.wb.addr_RNO_4[5]\ : OR2A - port map(A => N_707, B => N_388, Y => N_343); - - \r.wb.addr_RNO_3[4]\ : MX2 - port map(A => data_14, B => data_0(14), S => twowner_1(0), - Y => N_628); - - \r.wb.addr_RNO_2[15]\ : MX2 - port map(A => aaddr_13, B => aaddr_0_13, S => twowner_2(0), - Y => N_717); - - \r.wb.addr_RNO[31]\ : AO1C - port map(A => N_204, B => ctxp(25), C => \addr_1_i_i_0[31]\, - Y => N_47); - - \r.state_i_RNIV9NDT3[5]\ : OA1A - port map(A => N_215_0, B => \addr_1_i_i_a2_2_0[7]\, C => - N_366_0, Y => \addr_1_i_i_o2_0[7]\); - - \r.wb.addr_RNO[18]\ : AO1C - port map(A => N_204_0, B => ctxp(12), C => - \addr_1_i_i_0[18]\, Y => N_178); - - \r.state_RNO[4]\ : NOR3A - port map(A => rst, B => N_633, C => N_634, Y => - \state_nss[1]\); - - \r.wb.addr_RNO_1[23]\ : MX2 - port map(A => aaddr_21, B => aaddr_0_21, S => twowner(0), Y - => N_725); - - \r.wb.addr_RNO[24]\ : AO1C - port map(A => N_204_0, B => ctxp(18), C => - \addr_1_i_i_0[24]\, Y => N_35); - - \r.wb.addr_RNO_2[14]\ : OR2A - port map(A => hrdata_0_10, B => N_366, Y => N_316); - - \r.wb.addr[24]\ : DFN1E1 - port map(D => N_35, CLK => lclk_c, E => N_456_0, Q => - address(24)); - - \r.wb.data[6]\ : DFN1E0 - port map(D => N_3143, CLK => lclk_c, E => N_215, Q => - data_6); - - \r.wb.addr[26]\ : DFN1E1 - port map(D => N_580, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(26)); - - \r.wb.addr_RNO_8[5]\ : MX2C - port map(A => data_27, B => data_21, S => \state[2]\, Y => - N_590); - - \r.state_RNI5D9G11[0]\ : OR2B - port map(A => fault_trans_1_i_0_0_0, B => N_617, Y => - fault_trans_i_2); - - \r.wb.addr_RNO_5[2]\ : MX2C - port map(A => N_673, B => N_616, S => twowner(0), Y => - N_227); - - \r.wb.addr_RNO_2[31]\ : MX2 - port map(A => aaddr_29, B => aaddr_0_29, S => twowner(0), Y - => N_730); - - \r.wb.data_RNO[22]\ : MX2 - port map(A => adata_22, B => adata_0_22, S => twowner_1(0), - Y => N_654); - - \r.wb.addr_RNO_8[3]\ : MX2C - port map(A => data_25, B => data_19, S => \state[2]\, Y => - N_589_0); - - \r.wb.data_RNO[11]\ : MX2 - port map(A => adata_11, B => adata_0_11, S => twowner_1(0), - Y => N_652_0); - - \r.state_RNI673HG2_0[0]\ : OR2A - port map(A => N_365, B => N_215_0, Y => N_388); - - \r.wb.addr_RNO[15]\ : AO1C - port map(A => N_204_0, B => ctxp(9), C => - \addr_1_i_i_0[15]\, Y => N_172); - - \r.wb.addr_RNO_1[18]\ : OR2A - port map(A => N_720, B => N_388, Y => N_330); - - \r.wb.addr[25]\ : DFN1E1 - port map(D => N_579, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(25)); - - \r.state_RNIVBNU1[1]\ : OA1B - port map(A => \state[0]\, B => \state[1]\, C => \N_207\, Y - => N_82); - - \r.wb.addr_RNO_0[7]\ : AO1B - port map(A => \addr_1_i_i_o2_0[7]\, B => N_361, C => N_362, - Y => N_205); - - \r.state_RNI5K6M31[0]\ : OR3B - port map(A => walk_op, B => N_364, C => \state[0]\, Y => - N_365); - - \r.wb.addr_RNO_1[29]\ : MX2 - port map(A => aaddr_27, B => aaddr_0_27, S => twowner_2(0), - Y => N_728); - - \r.wb.addr[22]\ : DFN1E1 - port map(D => N_17, CLK => lclk_c, E => N_456_0, Q => - address(22)); - - \r.wb.addr_RNO_0[22]\ : OA1A - port map(A => hrdata_0_18, B => N_366_0, C => N_595, Y => - \addr_1_i_i_0[22]\); - - \r.wb.addr_RNO[19]\ : AO1C - port map(A => N_204, B => ctxp(13), C => \addr_1_i_i_0[19]\, - Y => N_180); - - \p0.fault_mexc_1_0_a2_0_a2_RNO\ : OR2A - port map(A => mexc, B => N_226, Y => - fault_mexc_1_0_a2_0_a2_0); - - \r.state_RNIDC5FG2[3]\ : OR2A - port map(A => N_210, B => N_366, Y => N_370); - - \r.wb.data_RNO[9]\ : MX2 - port map(A => adata_9, B => adata_0_9, S => twowner_0(0), Y - => N_622_0); - - \r.wb.addr_RNO_2[22]\ : MX2 - port map(A => aaddr_20, B => aaddr_0_20, S => twowner_2(0), - Y => N_724); - - \r.wb.addr[17]\ : DFN1E1 - port map(D => N_176, CLK => lclk_c, E => N_456_0, Q => - address(17)); - - \r.wb.data[12]\ : DFN1E0 - port map(D => N_642_0, CLK => lclk_c, E => N_215_0, Q => - data_1(12)); - - \r.wb.addr_RNO_2[17]\ : OR2A - port map(A => hrdata_0_13, B => N_366, Y => N_325); - - \r.wb.data[23]\ : DFN1E0 - port map(D => N_645_0, CLK => lclk_c, E => N_215, Q => - data_1(23)); - - \r.wb.addr_RNO_3[3]\ : MX2 - port map(A => data_13, B => data_0(13), S => twowner_1(0), - Y => N_627_0); - - \r.wb.addr_RNO_2[4]\ : OR2A - port map(A => ctx_2, B => N_204, Y => N_348); - - \r.wb.addr_RNO_1[11]\ : OR2A - port map(A => N_713, B => N_388, Y => N_309); - - \r.wb.addr_RNO[6]\ : NOR3 - port map(A => N_338, B => \addr_1_i_0_0[6]\, C => N_340, Y - => N_479); - - \r.state_RNO_1[3]\ : OA1B - port map(A => N_386, B => \state[3]\, C => \N_207\, Y => - \state_ns_i_0_0_0[2]\); - - \r.req_RNIEDSO1\ : OR3B - port map(A => \fault_lvl_1_0_iv_0_a2_i_o2_0[0]\, B => - iosn_0(93), C => bo_5842_d_0, Y => \N_207\); - - \r.state[4]\ : DFN1 - port map(D => \state_nss[1]\, CLK => lclk_c, Q => - \state[4]\); - - \r.wb.data_RNO[21]\ : MX2 - port map(A => adata_21, B => adata_0_21, S => twowner_0(0), - Y => N_625_0); - - \r.wb.addr_RNO_7[5]\ : MX2C - port map(A => data_0(27), B => data_0(21), S => \state[2]\, - Y => N_619_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.state_RNI2CNU1[1]\ : OA1B - port map(A => \state[1]\, B => \state[3]\, C => \N_207\, Y - => lvl_i_1(0)); - - \r.req_RNIJD8G31\ : NOR3 - port map(A => hrdata_0_1, B => \walk_op_2_0_0_o2_0\, C => - \N_207\, Y => N_364); - - \r.wb.addr_RNO_7[7]\ : MX2 - port map(A => data_0(29), B => data_0(23), S => \state[2]\, - Y => N_660); - - \r.wb.read_RNO\ : AO1C - port map(A => N_206, B => rst, C => N_651, Y => read_RNO); - - \r.wb.addr[27]\ : DFN1E1 - port map(D => N_581, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(27)); - - \r.walk_op_RNO\ : OR3C - port map(A => N_648, B => N_645, C => N_646, Y => - walk_op_RNO); - - \r.wb.addr_RNO_5[3]\ : MX2C - port map(A => N_591, B => N_589_0, S => twowner_0(0), Y => - N_228); - - \r.wb.addr_RNO[8]\ : AO1C - port map(A => N_204_0, B => N_53_1, C => - \addr_1_i_i_0_0[8]\, Y => N_11); - - \r.wb.data[17]\ : DFN1E0 - port map(D => N_669, CLK => lclk_c, E => N_215_0, Q => - data_1(17)); - - \r.wb.data[0]\ : DFN1E0 - port map(D => N_731, CLK => lclk_c, E => N_215_0, Q => - data_0_d0); - - \r.wb.addr_RNO_3[6]\ : MX2C - port map(A => N_649, B => N_698, S => twowner(0), Y => - N_231); - - \r.state[0]\ : DFN1 - port map(D => \state_nss[5]\, CLK => lclk_c, Q => - \state[0]\); - - \r.state_RNILUQ5[3]\ : OR2 - port map(A => \state[3]\, B => \state[2]\, Y => N_210); - - \r.wb.addr_RNO_2[16]\ : MX2 - port map(A => aaddr_14, B => aaddr_0_14, S => twowner_2(0), - Y => N_718); - - \r.state_RNO_1[1]\ : OAI1 - port map(A => N_364, B => N_367, C => \state[2]\, Y => - N_641); - - \r.wb.addr_RNO[20]\ : AO1C - port map(A => N_204, B => ctxp(14), C => \addr_1_i_i_0[20]\, - Y => N_182); - - \r.wb.addr_RNO_2[10]\ : OR2A - port map(A => hrdata(6), B => N_366, Y => N_652); - - \r.wb.addr_RNO_1[28]\ : MX2 - port map(A => aaddr_26, B => aaddr_0_26, S => twowner_2(0), - Y => N_727); - - \r.wb.addr[18]\ : DFN1E1 - port map(D => N_178, CLK => lclk_c, E => N_456_0, Q => - address(18)); - - \r.wb.addr_RNO_6[3]\ : MX2 - port map(A => aaddr_1, B => aaddr_0_1, S => twowner_1(0), Y - => N_705); - - \r.wb.addr_RNO_1[12]\ : MX2 - port map(A => aaddr_10, B => aaddr_0_10, S => twowner_1(0), - Y => N_714); - - \r.wb.addr_RNO_9[6]\ : MX2 - port map(A => aaddr_4, B => aaddr_0_4, S => twowner(0), Y - => N_708); - - \r.wb.data[28]\ : DFN1E0 - port map(D => N_3144, CLK => lclk_c, E => N_215, Q => - data_1(28)); - - \r.walk_op_RNIFNCQ11\ : OA1 - port map(A => hrdata_0_1, B => \walk_op_2_0_0_o2_0\, C => - walk_op, Y => N_386); - - \r.wb.data_RNO[14]\ : MX2 - port map(A => adata_14, B => adata_0_14, S => twowner_2(0), - Y => \adata_1[14]\); - - \r.wb.addr_RNO_0[15]\ : OA1A - port map(A => hrdata_0_11, B => N_366_0, C => N_321, Y => - \addr_1_i_i_0[15]\); - - \r.walk_op_RNO_3\ : NOR3B - port map(A => walk_op, B => rst, C => \state[0]\, Y => - walk_op_2_0_0_a2_1_0); - - \r.wb.addr_RNO_2[13]\ : OR2A - port map(A => hrdata_0_9, B => N_366, Y => N_313); - - \r.wb.data[1]\ : DFN1E0 - port map(D => N_3142, CLK => lclk_c, E => N_215_0, Q => - data_1_d0); - - \r.wb.data[19]\ : DFN1E0 - port map(D => N_653, CLK => lclk_c, E => N_215_0, Q => - data_1(19)); - - \r.state[3]\ : DFN1 - port map(D => \state_nss[2]\, CLK => lclk_c, Q => - \state[3]\); - - \r.wb.addr_RNO_6[7]\ : OR2A - port map(A => hrdata_0_3, B => N_366, Y => N_358); - - \r.wb.addr_RNO_0[9]\ : OR2 - port map(A => ctxp(3), B => ctx_7, Y => N_56_1); - - \r.wb.data_RNO[0]\ : MX2 - port map(A => adata_0_d0, B => adata_0_0, S => twowner_2(0), - Y => N_731); - - \r.wb.addr_RNO_4[6]\ : OR3 - port map(A => N_225, B => N_210, C => hrdata_0_2, Y => - \addr_1_i_0_a2_1[6]\); - - \r.wb.addr_RNO_0[14]\ : OA1A - port map(A => N_716, B => N_388_0, C => N_316, Y => - \addr_1_i_i_0[14]\); - - \r.wb.addr_RNO_4[8]\ : MX2 - port map(A => data_30, B => data_0(30), S => twowner_0(0), - Y => N_611); - - \r.wb.addr_RNO_2[6]\ : NOR3 - port map(A => ctx_0(4), B => ctxp(0), C => N_204, Y => - N_340); - - \r.wb.addr_RNO_8[6]\ : NOR2A - port map(A => \state[1]\, B => N_609, Y => N_225); - - \r.wb.addr_RNO[22]\ : AO1C - port map(A => N_204_0, B => ctxp(16), C => - \addr_1_i_i_0[22]\, Y => N_17); - - \r.state_i_RNO[5]\ : NOR3C - port map(A => N_630, B => \finish\, C => rst, Y => - \state_nss_i_0[0]\); - - \r.wb.addr_RNO_6[5]\ : MX2 - port map(A => aaddr_3, B => aaddr_0_3, S => twowner_1(0), Y - => N_707); - - \r.wb.data[31]\ : DFN1E0 - port map(D => N_702, CLK => lclk_c, E => N_215, Q => - data_1(31)); - - \r.wb.data[30]\ : DFN1E0 - port map(D => N_3146, CLK => lclk_c, E => N_215, Q => - data_1(30)); - - \r.state_RNI0CNU1[0]\ : OA1B - port map(A => \state[0]\, B => \state[2]\, C => \N_207\, Y - => N_80); - - \r.wb.addr_RNO[16]\ : AO1C - port map(A => N_204_0, B => ctxp(10), C => - \addr_1_i_i_0[16]\, Y => N_174); - - \r.wb.addr[28]\ : DFN1E1 - port map(D => N_582, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(28)); - - \r.state_i_RNI1JSQC1[5]\ : AO1 - port map(A => N_2485, B => N_2484, C => \state_i[5]\, Y => - N_215); - - \r.wb.addr_RNO_1[21]\ : OR2A - port map(A => N_723, B => N_388_0, Y => N_592); - - \r.wb.addr_RNO[28]\ : AO1C - port map(A => N_204_0, B => ctxp(22), C => - \addr_1_i_i_0[28]\, Y => N_582); - - \r.state_RNIGCQOF[0]\ : OR2 - port map(A => \state[0]\, B => hrdata_0_1, Y => N_617); - - \r.wb.addr_RNO_2[19]\ : OR2A - port map(A => hrdata_0_15, B => N_366, Y => N_331); - - \r.wb.addr_RNO[13]\ : AO1C - port map(A => N_204_0, B => ctxp(7), C => - \addr_1_i_i_0[13]\, Y => N_168); - - \r.walk_op_RNO_1\ : OR3C - port map(A => rst, B => walk_op, C => \N_207\, Y => N_645); - - \r.state_RNO_0[2]\ : OR2B - port map(A => \state[2]\, B => \N_207\, Y => N_640); - - \r.state_RNIULR8_0[4]\ : NOR3 - port map(A => \state[0]\, B => \state[4]\, C => walk_op, Y - => d_N_6_1); - - \r.wb.addr_RNO[11]\ : AO1C - port map(A => N_204, B => ctxp(5), C => \addr_1_i_i_0[11]\, - Y => N_164); - - \r.wb.data[26]\ : DFN1E0 - port map(D => N_610_0, CLK => lclk_c, E => N_215, Q => - data_1(26)); - - \r.wb.addr_RNO_1[4]\ : OR2A - port map(A => N_229, B => N_370, Y => N_345); - - \r.state_RNO_0[1]\ : OR2B - port map(A => \state[1]\, B => \N_207\, Y => N_642); - - \r.state_i_RNIJP3JC1[5]\ : AOI1 - port map(A => N_2488, B => N_2487, C => \state_i[5]\, Y => - \state_i_RNIJP3JC1[5]\); - - \r.wb.addr_RNO_7[6]\ : MX2C - port map(A => data_28, B => data_22, S => \state[2]\, Y => - N_698); - - \r.wb.addr_RNO_5[6]\ : NOR2 - port map(A => N_388, B => N_708, Y => N_339); - - \r.wb.data_RNO[17]\ : MX2 - port map(A => adata_17, B => adata_0_17, S => twowner_1(0), - Y => N_669); - - \r.state_i_RNIP074T3[5]\ : OR2B - port map(A => N_366, B => N_215_0, Y => N_204); - - \r.wb.addr_RNO_6[2]\ : MX2 - port map(A => aaddr_0_d0, B => aaddr_0_0, S => twowner(0), - Y => N_704); - - \r.wb.addr_RNO[25]\ : AO1C - port map(A => N_204_0, B => ctxp(19), C => - \addr_1_i_i_0[25]\, Y => N_579); - - \r.wb.addr[30]\ : DFN1E1 - port map(D => N_43, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(30)); - - \r.wb.data[2]\ : DFN1E0 - port map(D => N_99, CLK => lclk_c, E => N_215, Q => data_2); - - \r.wb.data[14]\ : DFN1E0 - port map(D => \adata_1[14]\, CLK => lclk_c, E => N_215_0, Q - => data_1(14)); - - \r.wb.addr_RNO_7[3]\ : MX2C - port map(A => data_0(25), B => data_0(19), S => \state[2]\, - Y => N_591); - - \r.wb.addr_RNO_0[25]\ : OA1A - port map(A => hrdata_0_21, B => N_366_0, C => N_619, Y => - \addr_1_i_i_0[25]\); - - \r.wb.addr[6]\ : DFN1E1 - port map(D => N_479, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(6)); - - \r.wb.data_RNO[24]\ : MX2 - port map(A => adata_24, B => adata_0_24, S => twowner_1(0), - Y => N_646_0); - - \r.wb.addr_RNO[29]\ : AO1C - port map(A => N_204_0, B => ctxp(23), C => - \addr_1_i_i_0[29]\, Y => N_39); - - \r.wb.addr_RNO_0[24]\ : OA1A - port map(A => N_726, B => N_388_0, C => N_599, Y => - \addr_1_i_i_0[24]\); - - \r.wb.addr_RNO_0[17]\ : OA1A - port map(A => N_719, B => N_388_0, C => N_325, Y => - \addr_1_i_i_0[17]\); - - \r.wb.addr[8]\ : DFN1E1 - port map(D => N_11, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(8)); - - \r.wb.addr_RNO_2[25]\ : MX2 - port map(A => aaddr_23, B => aaddr_0_23, S => twowner_2(0), - Y => N_737); - - \r.wb.addr_RNO_8[4]\ : MX2C - port map(A => data_26, B => data_20, S => \state[2]\, Y => - N_648_0); - - \r.wb.addr_RNO[5]\ : OR3C - port map(A => \addr_1_1_0_0[5]\, B => N_341, C => N_344, Y - => \addr_1[5]\); - - \r.wb.addr[4]\ : DFN1E1 - port map(D => \addr_1[4]\, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(4)); - - \r.wb.addr[10]\ : DFN1E1 - port map(D => N_159, CLK => lclk_c, E => N_456_0, Q => - address(10)); - - \r.wb.addr_RNO_2[24]\ : OR2A - port map(A => N_262_0, B => N_366, Y => N_599); - - \r.wb.addr_RNO_1[8]\ : OA1A - port map(A => \addr_1_i_i_0_tz[8]\, B => N_366_0, C => - N_586, Y => \addr_1_i_i_0_0[8]\); - - \r.wb.addr_RNO_0[5]\ : AOI1B - port map(A => N_369, B => N_629, C => N_343, Y => - \addr_1_1_0_0[5]\); - - \r.wb.addr_RNO_6[4]\ : MX2 - port map(A => aaddr_2, B => aaddr_0_2, S => twowner_1(0), Y - => N_706); - - \r.wb.addr_RNO_1[22]\ : OR2A - port map(A => N_724, B => N_388_0, Y => N_595); - - \r.wb.addr_RNO_1[6]\ : AO1D - port map(A => \addr_1_i_0_a2_1[6]\, B => N_366_0, C => - N_339, Y => \addr_1_i_0_0[6]\); - - \r.wb.addr_RNO_4[9]\ : MX2 - port map(A => data_31, B => data_0(31), S => twowner_0(0), - Y => N_592_0); - - \r.wb.addr_RNO_3[5]\ : MX2 - port map(A => data_15, B => data_0(15), S => twowner_1(0), - Y => N_629); - - \r.state_i_RNIS16DD1[5]\ : OR2A - port map(A => N_709, B => N_215_0, Y => N_361); - - \r.wb.addr_RNO_7[2]\ : MX2C - port map(A => data_24, B => data_18, S => \state[2]\, Y => - N_673); - - \r.state_RNIP074T3[0]\ : OR3C - port map(A => N_206, B => N_365, C => N_215_0, Y => N_456_0); - - \r.state_i_RNIJP3JC1_0[5]\ : AO1 - port map(A => N_2488, B => N_2487, C => \state_i[5]\, Y => - N_206); - - \r.wb.data_RNO[8]\ : MX2 - port map(A => adata_8, B => adata_0_8, S => twowner_0(0), Y - => N_621); - - \r.wb.data_RNO[18]\ : MX2 - port map(A => adata_18, B => adata_0_18, S => twowner(0), Y - => N_697); - - \r.state_i_RNO_0[5]\ : OR3B - port map(A => N_2487, B => N_2488, C => - \state_ns_0_0_0_a2_0[0]\, Y => N_630); - - \r.wb.addr[2]\ : DFN1E1 - port map(D => \addr_1[2]\, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(2)); - - \r.wb.addr_RNO_3[7]\ : AOI1B - port map(A => N_369, B => N_647, C => N_358, Y => - \addr_1_i_i_0[7]\); - - \r.state_RNO[1]\ : AOI1B - port map(A => N_642, B => N_641, C => rst, Y => - \state_nss[4]\); - - \r.state_i[5]\ : DFN1 - port map(D => \state_nss_i_0[0]\, CLK => lclk_c, Q => - \state_i[5]\); - - \r.wb.addr_RNO_1[9]\ : OA1A - port map(A => \addr_1_i_i_0_tz[9]\, B => N_366_0, C => - N_589, Y => \addr_1_i_i_0_0[9]\); - - \r.wb.data[3]\ : DFN1E0 - port map(D => N_100, CLK => lclk_c, E => N_215, Q => data_3); - - \r.wb.data_RNO[27]\ : MX2 - port map(A => adata_27, B => adata_0_27, S => twowner_0(0), - Y => N_588); - - \r.wb.addr_RNO_5[8]\ : MX2 - port map(A => aaddr_6, B => aaddr_0_6, S => twowner_1(0), Y - => N_710); - - \r.wb.addr_RNO_1[2]\ : OR2A - port map(A => N_227, B => N_370, Y => N_353); - - \r.wb.addr_RNO_0[16]\ : OA1A - port map(A => hrdata_0_12, B => N_366_0, C => N_324, Y => - \addr_1_i_i_0[16]\); - - \r.wb.addr[3]\ : DFN1E1 - port map(D => \addr_1[3]\, CLK => lclk_c, E => - \state_RNIP074T3_0[0]\, Q => address(3)); - - \r.state_RNI3CNU1[3]\ : NOR2A - port map(A => N_210, B => \N_207\, Y => lvl_i_1(1)); - - \r.wb.addr_RNO_2[8]\ : AO1 - port map(A => \state[3]\, B => N_611, C => hrdata_0_4, Y - => \addr_1_i_i_0_tz[8]\); - - \r.wb.addr_RNO_8[7]\ : MX2 - port map(A => data_29, B => data_23, S => \state[2]\, Y => - N_618); - - \r.wb.addr_RNO_2[18]\ : MX2 - port map(A => aaddr_16, B => aaddr_0_16, S => twowner_2(0), - Y => N_720); - - \r.wb.addr_RNO_0[27]\ : OA1A - port map(A => hrdata_0_23, B => N_366_0, C => N_625, Y => - \addr_1_i_i_0[27]\); - - \r.wb.addr[20]\ : DFN1E1 - port map(D => N_182, CLK => lclk_c, E => N_456_0, Q => - address(20)); - - \r.wb.read\ : DFN1 - port map(D => read_RNO, CLK => lclk_c, Q => \read\); - - \p0.v.wb.addr_1_i_i_a2_2_0[7]\ : OR2 - port map(A => ctxp(1), B => ctx_0(5), Y => - \addr_1_i_i_a2_2_0[7]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_2 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - data_0_11 : in std_logic; - data_0_9 : in std_logic; - data_0_8 : in std_logic; - data_0_7 : in std_logic; - data_0_4 : in std_logic; - data_0_3 : in std_logic; - data_0_2 : in std_logic; - data_0_0 : in std_logic; - tlbcam_write_op_1_1 : in std_logic_vector(0 to 0); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_17 : in std_logic; - hrdata_10 : in std_logic; - hrdata_7 : in std_logic; - hrdata_6 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_0_d0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(0 to 0); - TYP_1 : in std_logic_vector(2 downto 0); - s2_entry : in std_logic_vector(2 to 2); - LVL_1 : in std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - data : in std_logic_vector(31 downto 12); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_1 : in std_logic_vector(2 to 2); - pteout_1 : in std_logic_vector(4 downto 2); - s2_entry_0 : in std_logic_vector(2 to 2); - pteout_0_17 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - tlbcam_write_op_1_0 : in std_logic_vector(0 to 0); - cam_hitaddr_21 : in std_logic_vector(0 to 0); - pteout_3 : in std_logic; - pteout_2 : in std_logic; - pteout_4 : in std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_0 : out std_logic; - un1_m0_2_15 : out std_logic; - un2_wb_acc_iv_2 : in std_logic_vector(14 to 14); - un2_wb_acc_iv_3 : in std_logic_vector(14 to 14); - un2_wb_acc_iv_5 : in std_logic_vector(18 downto 16); - data_1_3_i_a3_0_5_3 : in std_logic; - data_1_3_i_a3_0_5_0 : in std_logic; - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - ctx_4 : in std_logic; - ctx_3 : in std_logic; - ctx_0_d0 : in std_logic; - ctx_1 : in std_logic; - ctx_0_7 : in std_logic; - ctx_0_3 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_6 : in std_logic; - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - pteout_m_i_1 : in std_logic_vector(15 to 15); - un2_wb_acc_iv_0_12 : out std_logic; - un2_wb_acc_iv_1_8 : in std_logic; - un2_wb_acc_iv_1_11 : in std_logic; - un2_wb_acc_iv_1_10 : in std_logic; - un2_wb_acc_iv_1_9 : in std_logic; - un2_wb_acc_iv_1_7 : in std_logic; - un2_wb_acc_iv_1_5 : in std_logic; - un2_wb_acc_iv_1_4 : in std_logic; - un2_wb_acc_iv_1_1 : in std_logic; - un2_wb_acc_iv_1_0 : in std_logic; - un2_wb_acc_iv_1_3 : in std_logic; - pteout_m_i_11 : in std_logic; - pteout_m_i_10 : in std_logic; - pteout_m_i_9 : in std_logic; - pteout_m_i_7 : in std_logic; - pteout_m_i_6 : in std_logic; - pteout_m_i_5 : in std_logic; - pteout_m_i_4 : in std_logic; - pteout_m_i_1_d0 : in std_logic; - pteout_m_i_0_d0 : in std_logic; - pteout_m_i_3 : in std_logic; - un2_wb_acc_iv_4_11 : out std_logic; - un2_wb_acc_iv_4_10 : out std_logic; - un2_wb_acc_iv_4_6 : out std_logic; - un2_wb_acc_iv_4_4 : out std_logic; - un2_wb_acc_iv_4_1 : out std_logic; - un2_wb_acc_iv_4_0 : out std_logic; - un2_wb_acc_iv_4_3 : out std_logic; - data_1_3_i_a3_0_1_0 : in std_logic; - data_1_3_i_a3_0_1_3 : in std_logic; - data_1_3_i_a3_2 : in std_logic_vector(29 to 29); - data_1_3_i_a3_3 : in std_logic_vector(29 to 29); - pteout_m_i_0_1 : in std_logic_vector(26 to 26); - pteout_m_i_0_9 : in std_logic; - pteout_m_i_0_7 : in std_logic; - pteout_m_i_0_19 : in std_logic; - pteout_m_i_0_0_d0 : in std_logic; - pteout_m_i_0_3 : in std_logic; - pteout_m_i_0_16 : in std_logic; - pteout_m_i_0_15 : in std_logic; - pteout_m_i_0_17 : in std_logic; - pteout_m_i_0_18 : in std_logic; - pteout_m_i_0_0_14 : in std_logic; - pteout_m_i_0_0_18 : in std_logic; - pteout_m_i_0_0_13 : in std_logic; - data_1_3_i_a3_5_5 : in std_logic; - data_1_3_i_a3_5_3 : in std_logic; - data_1_3_i_a3_5_2 : in std_logic; - data_1_3_i_a3_5_1 : in std_logic; - data_1_3_i_a3_5_0 : in std_logic; - data_1_3_i_a3_1 : in std_logic_vector(29 downto 25); - data_1_3_i_a3_6_2 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_0 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_2701 : out std_logic; - N_1104 : out std_logic; - N_1496 : in std_logic; - N_1506 : in std_logic; - N_1117 : out std_logic; - N_1481 : in std_logic; - N_1120 : out std_logic; - N_1103 : out std_logic; - M_1 : in std_logic; - N_2483 : in std_logic; - trans_op : in std_logic; - un1_tlbcami_3 : out std_logic; - fault_pro67 : out std_logic; - read : in std_logic; - M_m : out std_logic; - N_1133 : out std_logic; - N_1479 : in std_logic; - s2_flush : in std_logic; - e : in std_logic; - rst : in std_logic; - un1_rst_i_0 : out std_logic; - N_1505 : in std_logic; - N_1482 : in std_logic; - N_1495 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_1513 : out std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - N_2720 : out std_logic; - N_2717 : out std_logic; - N_2714 : out std_logic; - N_1132 : out std_logic; - N_1131 : out std_logic; - N_1130 : out std_logic; - N_1129 : out std_logic; - N_1128 : out std_logic; - N_1127 : out std_logic; - N_1126 : out std_logic; - N_1125 : out std_logic; - N_1124 : out std_logic; - N_1123 : out std_logic; - N_1122 : out std_logic; - N_1121 : out std_logic; - N_1119 : out std_logic; - N_1118 : out std_logic; - N_1116 : out std_logic; - N_1115 : out std_logic; - N_1114 : out std_logic; - N_1113 : out std_logic; - N_1112 : out std_logic; - N_1111 : out std_logic; - N_1110 : out std_logic; - N_1109 : out std_logic; - N_1108 : out std_logic; - N_1107 : out std_logic; - N_1106 : out std_logic; - N_1102 : out std_logic; - N_1101 : out std_logic; - N_1100 : out std_logic; - s2_flush_0 : in std_logic; - G_80_0 : out std_logic; - N_1467 : in std_logic; - N_1480 : in std_logic; - N_1466 : in std_logic; - cam_hit_all_5_sqmuxa_0_a2_0 : in std_logic; - N_2551 : in std_logic; - N_1468 : in std_logic; - N_2703_i_0 : out std_logic; - N_2699_i_0 : out std_logic; - su : in std_logic; - un54_fault_pro_m_0 : in std_logic; - un54_fault_pro_m : out std_logic; - accexc_6 : in std_logic; - fault_pro : out std_logic; - fault_pri : out std_logic; - N_2709_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2702_i_0 : out std_logic; - tlbcamo_needsync : out std_logic; - WBNEEDSYNC_m_0 : in std_logic; - cam_hit_all_1 : out std_logic; - accexc_6_4 : out std_logic; - cam_hit_all_5_sqmuxa : in std_logic - ); - -end mmutlbcam_2_0_2; - -architecture DEF_ARCH of mmutlbcam_2_0_2 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hf_1_i, h_l3_1_i, hf_1_1_0, h_l3_1_4, h_l2_1, hf_1_0, - un3_hf, \data_1_3_i_a3_0[25]\, \pteout_m_i_0[21]\, - \data_1_3_i_a3_4[30]\, \data_1_3_i_a3_0[30]\, - \pteout[26]\, \data_1_3_i_a3_0[26]\, \pteout_m_i_0[22]\, - \data_1_3_i_a3_4[29]\, \pteout_m_i_0_0[25]\, - \data_1_3_i_a3_0[27]\, \pteout[23]\, - \data_1_3_i_a3_4[28]\, \pteout_m_i_0_0[24]\, - \data_1_3_i_a3_0_4[15]\, \pteout_m_i_0_0[11]\, - \data_1_3_i_a3_0_4[12]\, \pteout_m_i_0_0[8]\, - WBNEEDSYNC_m, \pteout_m_i_0[12]\, \pteout_m_i[27]\, - \pteout_m_i_0[9]\, \pteout_m_i_0[10]\, \pteout_m_i_0[13]\, - \un2_wb_acc_iv_4[14]\, \pteout_m_i_0[14]\, - \un2_wb_acc_iv_0[15]\, \pteout[15]\, - \un2_wb_acc_iv_4[16]\, \pteout_m_i_0[16]\, - \un2_wb_acc_iv_0[17]\, \pteout_m_i[17]\, - \un2_wb_acc_iv_4[18]\, \pteout_m_i_0[18]\, - \pteout_m_i_0[19]\, \pteout_m_i_0[20]\, WBNEEDSYNC_m_0_0, - hm_1_1, cam_hit_all_1_0, un18_hm, \LVL[0]\, \LVL[1]\, - \I3_RNIDS1Q[4]\, \I3_RNI7G1Q[3]\, h_l3_1_3, - \un1_tag0[61]\, h_l3_1_1, \I3_RNIL8291[2]\, - \I3_RNITM55[1]\, \I3_RNIOB0Q[0]\, h_l2_1_3, - \I2_RNIM82Q[1]\, \I2_RNIEC1Q[0]\, h_l2_1_1, h_l2_1_2, - \un1_tag0[66]\, \I2_RNIQ4UU[5]\, \un1_tag0[64]\, - \I2_RNI0O0Q[3]\, h_i13_NE_4, \I1_RNI7G0Q[1]\, - \I1_RNIIO091[0]\, h_i13_NE_1, h_i13_NE_3, \un1_tag0[75]\, - \I1_RNI040Q[6]\, h_i13_NE_2, \un1_tag0[72]\, - \I1_RNIF5VU[5]\, \un1_tag0[70]\, \I1_RNIH81Q[3]\, - h_c2_NE_5, h_c2_5_i, h_c2_4_i, h_c2_NE_3, h_c2_NE_4, - h_c2_1_i, h_c2_0_i, h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, - \un1_tag0[37]\, h_c2_3_i, h_i13_NE, hf_2_i, hf_3, - \un45_res[3]\, hf_4, \un1_tag0[43]\, \SU\, h_c2_NE, - \un2_wb_acc[18]\, \un2_wb_acc[17]\, \un2_wb_acc[16]\, - \un2_wb_acc[14]\, \cam_hit_all_1\, N_1490, - \ACC_RNIN7OINV1[1]\, \fault_pri\, \N_2709_i_0\, - \LVL_RNIT69H911[0]\, hm_4, hm_3, hm_1, N_1485, - \ACC_RNI6GVGC7[2]\, \pteout_0[4]\, N_1483, - \ACC_RNI2GVGC7[0]\, \pteout_0[2]\, \ACC_RNI638B8Q[1]\, - \ACC_RNI4GVGC7[1]\, \pteout_0[3]\, N_1488, N_15, - \un1_tag0[56]\, \un1_tag0[59]\, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[74]\, \un1_tag0[35]\, - \un1_tag0[36]\, \un1_tag0[38]\, \un1_tag0[39]\, - \un1_tag0[40]\, \un1_tag0[42]\, \pteout[0]\, \pteout[1]\, - \pteout[6]\, \pteout[7]\, \pteout[8]\, \pteout[9]\, - \pteout[10]\, \pteout[11]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[16]\, \pteout[18]\, \pteout[19]\, - \pteout[21]\, \pteout[22]\, \pteout[24]\, \pteout[25]\, - \pteout[27]\, \pteout[28]\, \pteout[29]\, \pteout[30]\, - \pteout[31]\, \pteout[20]\, \un1_tag0[62]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, - \un1_tag0[57]\, \un1_tag0[58]\, \N_1513\, \un1_tag0[60]\, - \un1_tag0[68]\, \un1_tag0[73]\, N_1, N_3, N_8, N_1501, - N_1508, N_1512, VALID_RNO_9, \un1_rst_i_0\, hf_1_1, - fault_pro63, \fault_pro\, \G_80_0\, N_686, \M_m\, - \un54_fault_pro_m\, \fault_pro67\, M_1_sqmuxa, - \un1_tlbcami_3\, M_5, M_2, \tlbcamo_needsync\, N_9, N_6, - N_7, N_5, \pteout[17]\, N_1509, N_1502, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - LVL_RNIT69H911(0) <= \LVL_RNIT69H911[0]\; - un1_tlbcami_3 <= \un1_tlbcami_3\; - fault_pro67 <= \fault_pro67\; - M_m <= \M_m\; - un1_rst_i_0 <= \un1_rst_i_0\; - N_1513 <= \N_1513\; - G_80_0 <= \G_80_0\; - un54_fault_pro_m <= \un54_fault_pro_m\; - fault_pro <= \fault_pro\; - fault_pri <= \fault_pri\; - N_2709_i_0 <= \N_2709_i_0\; - tlbcamo_needsync <= \tlbcamo_needsync\; - cam_hit_all_1 <= \cam_hit_all_1\; - - \r.btag.PPN_RNIPGU5[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry_0(2), Y => N_1111); - - \r.btag.PPN_RNIQT9G263[16]\ : NOR3C - port map(A => pteout_m_i_0_16, B => \pteout_m_i_0_0[24]\, C - => data_1_3_i_a3_1(28), Y => \data_1_3_i_a3_4[28]\); - - \r.btag.CTX_RNIOJNA[2]\ : XA1A - port map(A => ctx_1, B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.PPN_RNIMNQ5263[6]\ : NOR3C - port map(A => pteout_m_i_5, B => \pteout_m_i_0[14]\, C => - un2_wb_acc_iv_1_5, Y => \un2_wb_acc_iv_4[14]\); - - \r.btag.I2_RNIFTRT1[4]\ : XA1 - port map(A => I2_1(4), B => \un1_tag0[66]\, C => - \I2_RNIQ4UU[5]\, Y => h_l2_1_2); - - \r.btag.LVL_RNI92HNDD1[0]\ : MX2C - port map(A => N_1495, B => N_1501, S => N_1482, Y => N_1508); - - \r.btag.SU_RNIAE73B\ : NOR2A - port map(A => TYP_1(2), B => N_8, Y => N_9); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[8]\); - - \r.btag.I2_RNIQ4UU[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => - \I2_RNIQ4UU[5]\); - - \r.btag.PPN_RNIPK8C3H[1]\ : OR2A - port map(A => \pteout[9]\, B => cam_hit_all_5_sqmuxa, Y => - \pteout_m_i_0[9]\); - - \r.btag.PPN_RNIABPKDD1[9]\ : NOR2B - port map(A => \pteout_m_i[17]\, B => pteout_m_i_0_9, Y => - \un2_wb_acc_iv_0[17]\); - - \r.btag.ACC_RNIF7OINV1[0]\ : MX2C - port map(A => N_1479, B => N_1483, S => cam_hitaddr_21(0), - Y => N_1488); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \LVL[1]\); - - \r.btag.PPN_RNI146B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_0(2), Y => N_1124); - - \r.btag.CTX_RNI7S44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[63]\); - - \r.btag.ACC_RNIA38B8Q[2]\ : MX2C - port map(A => \ACC_RNI6GVGC7[2]\, B => N_1468, S => N_2551, - Y => N_1485); - - \r.btag.PPN_RNIIQSE3H[19]\ : OR2A - port map(A => \pteout[27]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i[27]\); - - \r.btag.ACC_RNIV7OINV1[2]\ : MX2 - port map(A => N_1481, B => N_1485, S => cam_hitaddr_21(0), - Y => N_1490); - - \r.btag.VALID_RNIDRLBF\ : MX2 - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[19]\); - - \r.btag.PPN_RNIC2SE3H[13]\ : OR2A - port map(A => \pteout[21]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[21]\); - - \r.btag.PPN_RNIRGU5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_0(2), Y => N_1112); - - \r.btag.CTX_RNIFNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_d0, Y => h_c2_1_i); - - \r.btag.PPN_RNIDSOSBN2[13]\ : NOR3C - port map(A => data_1_3_i_a3_1(25), B => - \data_1_3_i_a3_0[25]\, C => data_1_3_i_a3_5_0, Y => - data_1_3_i_a3_6_0); - - \r.btag.C_RNIT346\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_0(2), Y => N_1107); - - \r.btag.LVL_RNIFGKD3H[1]\ : MX2C - port map(A => \LVL[1]\, B => LVL_1(1), S => - cam_hit_all_5_sqmuxa, Y => N_1502); - - \r.btag.VALID_RNI5MVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.PPN_RNI0S5B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_1(2), Y => N_1131); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[67]\); - - \r.btag.PPN_RNIQK8C3H[2]\ : OR2A - port map(A => \pteout[10]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[10]\); - - \r.btag.LVL_RNIB81HCE2[1]\ : MX2 - port map(A => N_1506, B => N_1509, S => cam_hitaddr_21(0), - Y => \N_1513\); - - \r.btag.ACC_RNI6RRTKG3[2]\ : OR3B - port map(A => \fault_pri\, B => \fault_pro\, C => accexc_6, - Y => un1_m0_2_15); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(0), Y => N_15); - - \r.btag.PPN_RNISV09[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry(2), Y => N_1120); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNIUDAG263[17]\ : NOR3C - port map(A => pteout_m_i_0_17, B => \pteout_m_i_0_0[25]\, C - => data_1_3_i_a3_1(29), Y => \data_1_3_i_a3_4[29]\); - - \r.btag.M_RNIH446\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_0(2), Y => N_1106); - - \r.btag.LVL_RNIOM8VD[1]\ : NOR3 - port map(A => un3_hf, B => \LVL[1]\, C => h_l2_1, Y => - hf_2_i); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \SU\); - - \r.btag.PPN_RNI4M0QDD1[15]\ : OA1A - port map(A => \pteout[23]\, B => cam_hit_all_5_sqmuxa, C - => pteout_m_i_0_15, Y => \data_1_3_i_a3_0[27]\); - - \r.btag.CTX_RNISO98[6]\ : XA1A - port map(A => ctx_0_6, B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[36]\); - - \r.btag.M_RNIUO73932\ : NOR3C - port map(A => WBNEEDSYNC_m, B => \cam_hit_all_1\, C => - WBNEEDSYNC_m_0, Y => accexc_6_4); - - \r.btag.LVL_RNID2HNDD1[1]\ : MX2C - port map(A => N_1496, B => N_1502, S => N_1482, Y => N_1509); - - \r.btag.LVL_RNI11RPD[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.I3_RNIAB882[0]\ : NOR3C - port map(A => \I3_RNIL8291[2]\, B => \I3_RNITM55[1]\, C => - \I3_RNIOB0Q[0]\, Y => h_l3_1_1); - - \r.btag.PPN_RNICM1QDD1[19]\ : NOR2B - port map(A => \pteout_m_i[27]\, B => pteout_m_i_0_19, Y => - un2_wb_acc_iv_0_12); - - \r.btag.I3_RNITM55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNITM55[1]\); - - \r.btag.ET_RNIP4SA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_0(2), Y => N_1100); - - \r.btag.LVL_RNIM356[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_1(2), - Y => N_1132); - - \r.btag.ACC_RNIS65RFU3[1]\ : NOR2 - port map(A => \M_m\, B => \un54_fault_pro_m\, Y => N_686); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[10]\); - - \r.btag.I3_RNIOB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIOB0Q[0]\); - - \r.btag.PPN_RNIANQ5263[3]\ : NOR3C - port map(A => pteout_m_i_0_3, B => \pteout_m_i_0_0[11]\, C - => data_1_3_i_a3_0_1_3, Y => \data_1_3_i_a3_0_4[15]\); - - \r.btag.PPN_RNI7GG5O51[9]\ : MX2 - port map(A => \un2_wb_acc[17]\, B => data(21), S => - \N_1513\, Y => un1_m0_2_3); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNILGU5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_0(2), Y => N_1109); - - \r.btag.M_RNI7DNKDI\ : OR2A - port map(A => WBNEEDSYNC_m_0_0, B => cam_hit_all_5_sqmuxa, - Y => WBNEEDSYNC_m); - - \r.btag.LVL_RNIT69H911[0]\ : OR2B - port map(A => \N_1513\, B => N_1512, Y => - \LVL_RNIT69H911[0]\); - - \r.btag.PPN_RNITGT7BN2[6]\ : OR3C - port map(A => un2_wb_acc_iv_3(14), B => un2_wb_acc_iv_2(14), - C => \un2_wb_acc_iv_4[14]\, Y => \un2_wb_acc[14]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN_RNILSPSBN2[14]\ : NOR3C - port map(A => data_1_3_i_a3_1(26), B => - \data_1_3_i_a3_0[26]\, C => data_1_3_i_a3_5_1, Y => - data_1_3_i_a3_6_1); - - \r.btag.CTX_RNI88FL[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.ACC_RNI2GVGC7[0]\ : MX2 - port map(A => pteout_2, B => \pteout_0[2]\, S => - cam_hit_all_5_sqmuxa_0_a2_0, Y => \ACC_RNI2GVGC7[0]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_0_21, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[21]\); - - \r.btag.I3_RNIL8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIL8291[2]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => \un1_rst_i_0\, B => N_15, Y => VALID_RNO_9); - - \r.btag.LVL_RNIQ1S291[0]\ : MX2C - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.PPN_RNI5K6B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_0(2), Y => N_1126); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[66]\); - - \r.btag.PPN_RNIUJ5B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_1(2), Y => N_1130); - - \r.btag.I2_RNIM82Q[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => - \I2_RNIM82Q[1]\); - - \r.btag.I1_RNI040Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI040Q[6]\); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[68]\); - - \r.btag.PPN_RNI7S6B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_0(2), Y => N_1127); - - \r.btag.M_RNI2HK9A1\ : NOR2B - port map(A => \tlbcamo_needsync\, B => hm_1_1, Y => - WBNEEDSYNC_m_0_0); - - \r.btag.PPN_RNI245ELO3[16]\ : OR3C - port map(A => data_1_3_i_a3_5_3, B => \data_1_3_i_a3_4[28]\, - C => \LVL_RNIT69H911[0]\, Y => N_2702_i_0); - - \r.btag.PPN_RNILJ4B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_0(2), Y => N_1118); - - \r.btag.LVL_RNIT69H911_0[0]\ : NOR2 - port map(A => \N_1513\, B => N_1512, Y => \N_2709_i_0\); - - \r.btag.PPN_RNI6NQ5263[2]\ : NOR3C - port map(A => pteout_m_i_1_d0, B => \pteout_m_i_0[10]\, C - => un2_wb_acc_iv_1_1, Y => un2_wb_acc_iv_4_1); - - \r.btag.I2_RNIOJ0K1[2]\ : XA1 - port map(A => I2_1(2), B => \un1_tag0[64]\, C => - \I2_RNI0O0Q[3]\, Y => h_l2_1_1); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_0_22, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[22]\); - - \r.btag.PPN_RNI3C6B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_0(2), Y => N_1125); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout_0[2]\); - - \r.btag.PPN_RNIRK8C3H[3]\ : OR2A - port map(A => \pteout[11]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0_0[11]\); - - \r.btag.PPN_RNIENQ5263[4]\ : NOR3C - port map(A => pteout_m_i_3, B => \pteout_m_i_0[12]\, C => - un2_wb_acc_iv_1_3, Y => un2_wb_acc_iv_4_3); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[29]\); - - \r.btag.I3_RNI35BR4[3]\ : NOR3C - port map(A => \I3_RNIDS1Q[4]\, B => \I3_RNI7G1Q[3]\, C => - h_l3_1_3, Y => h_l3_1_4); - - \r.btag.PPN_RNIJGU5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_0(2), Y => N_1108); - - \r.btag.PPN_RNIAE1QDD1[18]\ : OA1A - port map(A => \pteout[26]\, B => cam_hit_all_5_sqmuxa, C - => pteout_m_i_0_1(26), Y => \data_1_3_i_a3_0[30]\); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data_0_2, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[64]\); - - \r.btag.M_RNI8FO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => - \tlbcamo_needsync\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_9, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout_0[4]\); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[25]\); - - \r.btag.ACC_RNI5N8O6V1[0]\ : OR3B - port map(A => \ACC_RNIN7OINV1[1]\, B => N_1490, C => N_1488, - Y => \fault_pro67\); - - \r.btag.ACC_RNIN7OINV1[1]\ : MX2 - port map(A => N_1480, B => \ACC_RNI638B8Q[1]\, S => - cam_hitaddr_21(0), Y => \ACC_RNIN7OINV1[1]\); - - \r.btag.PPN_RNI3HU5[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_0(2), Y => N_1116); - - \r.btag.I1_RNIIO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIIO091[0]\); - - \r.btag.ACC_RNI6GVGC7[2]\ : MX2C - port map(A => pteout_4, B => \pteout_0[4]\, S => - cam_hit_all_5_sqmuxa_0_a2_0, Y => \ACC_RNI6GVGC7[2]\); - - \r.btag.ACC_RNI4GVGC7[1]\ : MX2 - port map(A => pteout_3, B => \pteout_0[3]\, S => - cam_hit_all_5_sqmuxa_0_a2_0, Y => \ACC_RNI4GVGC7[1]\); - - \r.btag.SU_RNI6AQJ1_0\ : AO1C - port map(A => \SU\, B => h_c2_NE, C => \un1_tag0[43]\, Y - => un3_hf); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout_0[3]\); - - \r.btag.PPN_RNIQ35B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_1(2), Y => N_1128); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[60]\); - - \r.btag.I2_RNI0O0Q[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => - \I2_RNI0O0Q[3]\); - - \r.btag.LVL_RNIGAHQ8[0]\ : NOR3 - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.I1_RNI3C547[4]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.PPN_RNID6SE3H[14]\ : OR2A - port map(A => \pteout[22]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[22]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_0_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[1]\); - - \r.btag.PPN_RNIBURE3H[12]\ : OR2A - port map(A => \pteout[20]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[20]\); - - \r.btag.PPN_RNI2E0QDD1[14]\ : NOR2B - port map(A => \pteout_m_i_0[22]\, B => pteout_m_i_0_0_14, Y - => \data_1_3_i_a3_0[26]\); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[11]\); - - \r.btag.LVL_RNIB1RT911[0]\ : OR2 - port map(A => \LVL_RNIT69H911[0]\, B => data(26), Y => - N_2701); - - \r.btag.LVL_RNIDGKD3H[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_1(0), S => - cam_hit_all_5_sqmuxa, Y => N_1501); - - \r.btag.VALID_RNI08E5R\ : NOR2A - port map(A => s2_flush, B => hf_1_1, Y => un18_hm); - - \r.btag.PPN_RNIUMQ5263[0]\ : NOR3C - port map(A => pteout_m_i_0_0_d0, B => \pteout_m_i_0_0[8]\, - C => data_1_3_i_a3_0_1_0, Y => \data_1_3_i_a3_0_4[12]\); - - \r.btag.PPN_RNILRLSBN2[10]\ : OR2B - port map(A => un2_wb_acc_iv_5(18), B => - \un2_wb_acc_iv_4[18]\, Y => \un2_wb_acc[18]\); - - \r.btag.I1_RNIF5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIF5VU[5]\); - - \p0.hf_1\ : AND2 - port map(A => h_l3_1_i, B => hf_1_1_0, Y => hf_1_i); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[20]\); - - \r.btag.CTX_RNIFS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0_7, Y => h_c2_7_i); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[42]\); - - \r.btag.I1_RNIT42K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIH81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[65]\); - - \r.btag.PPN_RNI2NQ5263[1]\ : NOR3C - port map(A => pteout_m_i_0_d0, B => \pteout_m_i_0[9]\, C - => un2_wb_acc_iv_1_0, Y => un2_wb_acc_iv_4_0); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_0_27, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[27]\); - - \r.btag.LVL_RNIOF04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_1133); - - \r.btag.CTX_RNILNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_3, Y => h_c2_4_i); - - \r.btag.I3_RNIFO773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_1, Y - => h_l3_1_3); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(0), - Y => M_5); - - \r.btag.LVL_RNIQ9A842[0]\ : OR2 - port map(A => hm_1_1, B => un18_hm, Y => cam_hit_all_1_0); - - \r.btag.PPN_RNI8DQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_1117); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[56]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data_0_9, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[71]\); - - \p0.h_l3_1\ : NOR2A - port map(A => h_l3_1_4, B => h_l2_1, Y => h_l3_1_i); - - \r.btag.PPN_RNITSQSBN2[15]\ : NOR3C - port map(A => data_1_3_i_a3_1(27), B => - \data_1_3_i_a3_0[27]\, C => data_1_3_i_a3_5_2, Y => - data_1_3_i_a3_6_2); - - \r.btag.PPN_RNIRB5B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_0(2), Y => N_1121); - - \r.btag.PPN_RNIOK8C3H[0]\ : OR2A - port map(A => \pteout[8]\, B => cam_hit_all_5_sqmuxa, Y => - \pteout_m_i_0_0[8]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[9]\); - - \r.btag.I1_RNI7G0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNI7G0Q[1]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[70]\); - - \r.btag.CTX_RNI1S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_0, Y => h_c2_0_i); - - \r.btag.VALID_RNII0II8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[24]\); - - \r.btag.LVL_RNID5RT911[0]\ : OR2 - port map(A => \LVL_RNIT69H911[0]\, B => data(27), Y => - N_2717); - - \r.btag.CTX_RNI87FL[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN_RNIQNQ5263[7]\ : NOR3C - port map(A => pteout_m_i_6, B => pteout_m_i_0_7, C => - \un2_wb_acc_iv_0[15]\, Y => un2_wb_acc_iv_4_6); - - \r.btag.PPN_RNIMNG5O51[6]\ : MX2 - port map(A => \un2_wb_acc[14]\, B => data(18), S => - \N_1513\, Y => un1_m0_2_0); - - \r.btag.VALID_RNIFKCE1\ : OR2A - port map(A => \un1_tag0[43]\, B => h_c2_NE, Y => hm_4); - - \r.btag.SU_RNI6AQJ1\ : NOR3A - port map(A => \un1_tag0[43]\, B => \SU\, C => h_c2_NE, Y - => hf_4); - - \r.btag.PPN_RNIINQ5263[5]\ : NOR3C - port map(A => pteout_m_i_4, B => \pteout_m_i_0[13]\, C => - un2_wb_acc_iv_1_4, Y => un2_wb_acc_iv_4_4); - - \r.btag.PPN_RNI6E8QO51[10]\ : MX2 - port map(A => \un2_wb_acc[18]\, B => data(22), S => - \N_1513\, Y => un1_m0_2_4); - - \r.btag.I1_RNIH81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIH81Q[3]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.ACC_RNIGEH8VU3[1]\ : OA1C - port map(A => \ACC_RNIN7OINV1[1]\, B => fault_pro63, C => - read, Y => \M_m\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data_0_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[40]\); - - \r.btag.LVL_RNIV5DJ7J[0]\ : OR2 - port map(A => cam_hit_all_1_0, B => cam_hit_all_5_sqmuxa, Y - => \cam_hit_all_1\); - - \r.btag.PPN_RNIUNQ5263[8]\ : NOR3C - port map(A => pteout_m_i_7, B => \pteout_m_i_0[16]\, C => - un2_wb_acc_iv_1_7, Y => \un2_wb_acc_iv_4[16]\); - - \r.btag.I2_RNIS8483[0]\ : NOR3C - port map(A => \I2_RNIM82Q[1]\, B => \I2_RNIEC1Q[0]\, C => - h_l2_1_1, Y => h_l2_1_3); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[37]\); - - \r.btag.PPN_RNISB5B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_1(2), Y => N_1129); - - \r.btag.PPN_RNI6BPKDD1[7]\ : OA1A - port map(A => \pteout[15]\, B => cam_hit_all_5_sqmuxa, C - => pteout_m_i_1(15), Y => \un2_wb_acc_iv_0[15]\); - - \r.btag.PPN_RNI2T6G263[10]\ : NOR3C - port map(A => pteout_m_i_9, B => \pteout_m_i_0[18]\, C => - un2_wb_acc_iv_1_9, Y => \un2_wb_acc_iv_4[18]\); - - \p0.un1_rst\ : NOR2B - port map(A => rst, B => e, Y => \un1_rst_i_0\); - - \r.btag.PPN_RNITGU5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_0(2), Y => N_1113); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_0_15, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[15]\); - - \r.btag.ET_RNIRCSA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_0(2), Y => N_1101); - - \r.btag.PPN_RNIQRF5O51[8]\ : MX2 - port map(A => \un2_wb_acc[16]\, B => data(20), S => - \N_1513\, Y => un1_m0_2_2); - - \r.btag.I3_RNIDS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIDS1Q[4]\); - - \r.btag.ACC_RNIL7H5[0]\ : MX2 - port map(A => \pteout_0[2]\, B => pteout_1(2), S => - s2_entry_0(2), Y => N_1102); - - \r.btag.ACC_RNI238B8Q[0]\ : MX2C - port map(A => \ACC_RNI2GVGC7[0]\, B => N_1466, S => N_2551, - Y => N_1483); - - \p0.hf_1_RNO\ : NOR2A - port map(A => hf_1_0, B => un3_hf, Y => hf_1_1_0); - - \r.btag.ACC_RNI5N8O6V1_1[0]\ : AO1B - port map(A => N_1490, B => \ACC_RNIN7OINV1[1]\, C => N_1488, - Y => \G_80_0\); - - \r.btag.LVL_RNIIU70TI2[0]\ : MX2C - port map(A => N_1505, B => N_1508, S => cam_hitaddr_21(0), - Y => N_1512); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[14]\); - - \r.btag.LVL_RNIPIA991[0]\ : NOR2B - port map(A => hm_1_1, B => trans_op, Y => \un1_tlbcami_3\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[7]\); - - \r.btag.PPN_RNINGU5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_0(2), Y => N_1110); - - \r.btag.ACC_RNIQ3D3[1]\ : MX2 - port map(A => \pteout_0[3]\, B => pteout_1(3), S => - s2_entry(2), Y => N_1103); - - \r.btag.ACC_RNIO83LFV3[2]\ : OR3A - port map(A => N_1490, B => \ACC_RNIN7OINV1[1]\, C => su, Y - => \fault_pri\); - - \r.btag.LVL_RNIM6O7R[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.ACC_RNI638B8Q[1]\ : MX2C - port map(A => \ACC_RNI4GVGC7[1]\, B => N_1467, S => N_2551, - Y => \ACC_RNI638B8Q[1]\); - - \r.btag.PPN_RNI9MRE3H[10]\ : OR2A - port map(A => \pteout[18]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[18]\); - - \r.btag.PPN_RNIUK8C3H[6]\ : OR2A - port map(A => \pteout[14]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[14]\); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \LVL[0]\); - - \r.btag.SU_RNIRCLRA\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1_0(0), Y => N_8); - - \r.btag.PPN_RNI2N6PKO3[3]\ : OR3C - port map(A => data_1_3_i_a3_0_5_3, B => - \data_1_3_i_a3_0_4[15]\, C => \N_2709_i_0\, Y => - N_2699_i_0); - - \r.btag.I2_RNIEC1Q[0]\ : XOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => - \I2_RNIEC1Q[0]\); - - \r.btag.I2_RNIEI5AC[4]\ : OR3B - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE, Y => - h_l2_1); - - \r.btag.PPN_RNI060QDD1[13]\ : NOR2B - port map(A => \pteout_m_i_0[21]\, B => pteout_m_i_0_0_13, Y - => \data_1_3_i_a3_0[25]\); - - \r.btag.PPN_RNIAM6PKO3[0]\ : OR3C - port map(A => data_1_3_i_a3_0_5_0, B => - \data_1_3_i_a3_0_4[12]\, C => \N_2709_i_0\, Y => - N_2711_i_0); - - \r.btag.LVL_RNI7KH2[0]\ : NOR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.PPN_RNIVGU5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_0(2), Y => N_1114); - - \r.btag.PPN_RNIAQRE3H[11]\ : OR2A - port map(A => \pteout[19]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[19]\); - - \r.btag.I1_RNI5Q0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIF5VU[5]\, Y => h_i13_NE_2); - - \r.btag.ACC_RNI6LMBTS3[0]\ : OA1A - port map(A => \G_80_0\, B => N_686, C => \fault_pro67\, Y - => \fault_pro\); - - \r.btag.I3_RNI7G1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNI7G1Q[3]\); - - \r.btag.PPN_RNIVR5B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_0(2), Y => N_1123); - - \r.btag.PPN_RNISK8C3H[4]\ : OR2A - port map(A => \pteout[12]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[12]\); - - \r.btag.PPN_RNI1L8C3H[9]\ : OR2A - port map(A => \pteout[17]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i[17]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[30]\); - - \r.btag.LVL_RNIHDRT911[0]\ : OR2 - port map(A => \LVL_RNIT69H911[0]\, B => data(29), Y => - N_2720); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[74]\); - - \r.btag.PPN_RNIAT7G263[12]\ : NOR3C - port map(A => pteout_m_i_11, B => \pteout_m_i_0[20]\, C => - un2_wb_acc_iv_1_11, Y => un2_wb_acc_iv_4_11); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_0_12, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[12]\); - - \r.btag.ACC_RNICOJIGV3[2]\ : NOR3B - port map(A => N_1490, B => \ACC_RNIN7OINV1[1]\, C => - un54_fault_pro_m_0, Y => \un54_fault_pro_m\); - - \r.btag.PPN_RNINR4B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_0(2), Y => N_1119); - - \r.btag.PPN_RNII47ELO3[18]\ : OR3C - port map(A => data_1_3_i_a3_5_5, B => \data_1_3_i_a3_4[30]\, - C => \LVL_RNIT69H911[0]\, Y => N_2703_i_0); - - \r.btag.PPN_RNI1HU5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_0(2), Y => N_1115); - - \r.btag.LVL_RNI9TQT911[0]\ : OR2 - port map(A => \LVL_RNIT69H911[0]\, B => data(25), Y => - N_2714); - - \r.btag.ACC_RNIS3D3[2]\ : MX2 - port map(A => \pteout_0[4]\, B => pteout_1(4), S => - s2_entry(2), Y => N_1104); - - \r.btag.PPN_RNIFESE3H[16]\ : OR2A - port map(A => \pteout[24]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0_0[24]\); - - \p0.hf_1_RNIP34IE\ : MX2 - port map(A => hf_2_i, B => hf_1_i, S => TYP_1(0), Y => N_5); - - \r.btag.CTX_RNIGFUA1[0]\ : OR2B - port map(A => h_c2_NE_5, B => h_c2_NE_4, Y => h_c2_NE); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_0_26, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_0_23, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_0_16, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => \un1_tlbcami_3\, B => tlbcam_write_op_1_0(0), - Y => M_1_sqmuxa); - - \r.btag.PPN_RNILHT7BN2[9]\ : OR3C - port map(A => un2_wb_acc_iv_1_8, B => \un2_wb_acc_iv_0[17]\, - C => un2_wb_acc_iv_5(17), Y => \un2_wb_acc[17]\); - - \r.btag.ACC_RNI5N8O6V1_0[0]\ : NOR3A - port map(A => \ACC_RNIN7OINV1[1]\, B => N_1488, C => N_1490, - Y => fault_pro63); - - \r.btag.VALID_RNIUQETQ\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[59]\); - - \r.btag.I1_RNIMD3N3[0]\ : NOR3C - port map(A => \I1_RNI7G0Q[1]\, B => \I1_RNIIO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN_RNITK8C3H[5]\ : OR2A - port map(A => \pteout[13]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[13]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[72]\); - - \r.btag.VALID_RNI0CTJI\ : NOR3A - port map(A => h_l3_1_4, B => h_l2_1, C => hm_4, Y => hm_1); - - \r.btag.PPN_RNI2UAG263[18]\ : NOR3C - port map(A => pteout_m_i_0_18, B => pteout_m_i_0_0_18, C - => \data_1_3_i_a3_0[30]\, Y => \data_1_3_i_a3_4[30]\); - - \r.btag.I1_RNI841K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI040Q[6]\, Y => h_i13_NE_3); - - \r.btag.PPN_RNIGISE3H[17]\ : OR2A - port map(A => \pteout[25]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0_0[25]\); - - \r.btag.PPN_RNIDHT7BN2[8]\ : OR2B - port map(A => un2_wb_acc_iv_5(16), B => - \un2_wb_acc_iv_4[16]\, Y => \un2_wb_acc[16]\); - - \r.btag.PPN_RNI6D7G263[11]\ : NOR3C - port map(A => pteout_m_i_10, B => \pteout_m_i_0[19]\, C => - un2_wb_acc_iv_1_10, Y => un2_wb_acc_iv_4_10); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \p0.hf_1_RNO_0\ : NOR2 - port map(A => \LVL[0]\, B => \LVL[1]\, Y => hf_1_0); - - \r.btag.PPN_RNIDTSSBN2[17]\ : NOR3C - port map(A => data_1_3_i_a3_3(29), B => data_1_3_i_a3_2(29), - C => \data_1_3_i_a3_4[29]\, Y => data_1_3_i_a3_6_4); - - \r.btag.PPN_RNITJ5B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_0(2), Y => N_1122); - - \r.btag.CTX_RNINNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_4, Y => h_c2_5_i); - - \r.btag.PPN_RNI0L8C3H[8]\ : OR2A - port map(A => \pteout[16]\, B => cam_hit_all_5_sqmuxa, Y - => \pteout_m_i_0[16]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data_0_11, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(0), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_4 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1 : in std_logic_vector(5 to 5); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_7 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(5 to 5); - pteout_0 : in std_logic_vector(4 downto 2); - cam_hitaddr_18 : in std_logic_vector(1 to 1); - LVL_0 : in std_logic_vector(0 to 0); - TYP_1 : in std_logic_vector(2 downto 0); - tlbcam_write_op_1_0 : in std_logic_vector(5 to 5); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - ctx : in std_logic_vector(7 downto 0); - I2_1 : in std_logic_vector(5 downto 0); - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I3_1_5 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - cam_hitaddr_21_1 : out std_logic_vector(0 to 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_11 : in std_logic; - pteout_m_i_10 : in std_logic; - pteout_m_i_9 : in std_logic; - pteout_m_i_7 : in std_logic; - pteout_m_i_4 : in std_logic; - pteout_m_i_1 : in std_logic; - pteout_m_i_0_d0 : in std_logic; - pteout_m_i_3 : in std_logic; - un2_wb_acc_iv_1_11 : out std_logic; - un2_wb_acc_iv_1_10 : out std_logic; - un2_wb_acc_iv_1_9 : out std_logic; - un2_wb_acc_iv_1_7 : out std_logic; - un2_wb_acc_iv_1_4 : out std_logic; - un2_wb_acc_iv_1_1 : out std_logic; - un2_wb_acc_iv_1_0 : out std_logic; - un2_wb_acc_iv_1_3 : out std_logic; - data_1_3_i_a3_0_1 : out std_logic_vector(12 to 12); - data_1_3_i_a3_1_0 : out std_logic; - data_1_3_i_a3_1_2 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(58 to 58); - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0_d0 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_24 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_6 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_13 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_12 : out std_logic; - pteout_8 : out std_logic; - pteout_23 : out std_logic; - pteout_25 : out std_logic; - pteout_11 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_0 : in std_logic; - pteout_m_i_0_15 : in std_logic; - pteout_m_i_0_17 : in std_logic; - pteout_m_i_0_3 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_1471 : out std_logic; - NEEDSYNC : out std_logic; - N_1470 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_1469 : out std_logic; - N_1497 : out std_logic; - s2_flush_1 : in std_logic; - trans_op : in std_logic; - N_2483 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - WBNEEDSYNC_m : out std_logic; - N_61 : in std_logic; - hit_1 : in std_logic; - hit_0 : out std_logic; - hit : in std_logic; - M_1 : in std_logic - ); - -end mmutlbcam_2_0_4; - -architecture DEF_ARCH of mmutlbcam_2_0_4 is - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal WBNEEDSYNC_m_0, hm_1_1, hf_1_1_1_a0_3_3, - hf_1_1_1_a0_3_2, h_l2_1_2, hf_1_1_1_a0_3_1, un3_hf, - hf_1_1_1_a1_2_1, \LVL[1]\, h_l3_1_4_2, \un1_tag0[59]\, - \I3_RNIIS1Q[4]\, h_l3_1_4_1, \un1_tag0[56]\, h_l3_1_4_0, - \un1_tag0[57]\, \I3_RNIQ8291[2]\, h_i13_NE_4, - \I1_RNICG0Q[1]\, \I1_RNINO091[0]\, h_i13_NE_1, h_i13_NE_3, - \un1_tag0[75]\, \I1_RNI540Q[6]\, h_i13_NE_2, - \un1_tag0[72]\, \I1_RNIK5VU[5]\, \un1_tag0[70]\, - \I1_RNIM81Q[3]\, h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, - hf_4_0, \un1_tag0[43]\, SU, h_c2_NE_5, h_c2_5_i, h_c2_4_i, - h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, - h_l2_1, h_l2_1_3, h_i13_NE, hf_3, \un45_res[3]\, hm_1, - h_l3_1_4_i, hm_4, hf_4, h_c2_NE_i_0, h_i22_1, h_i22_0, - \I3_RNIADVU[5]\, hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, hm_3, - N_5, h_i22_5, h_i22_4, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[74]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[62]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[66]\, \un1_tag0[67]\, - \un1_tag0[58]\, \un1_tag0[60]\, \un1_tag0[61]\, - \un1_tag0[68]\, \un1_tag0[73]\, M_2, \pteout[6]\, M_5, - un1_tlbcami_3, \hit_0\, hf_1_1, M_1_sqmuxa, \LVL[0]\, N_1, - N_3, N_7, N_6, N_8, N_9, VALID_RNO_11, N_15, \pteout[2]\, - \pteout[3]\, \pteout[4]\, \pteout[8]\, \pteout[9]\, - \pteout[10]\, \pteout[11]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[15]\, \pteout[16]\, \pteout[17]\, - \pteout[18]\, \pteout[19]\, \pteout[20]\, \pteout[21]\, - \pteout[22]\, \pteout[23]\, \pteout[24]\, \pteout[25]\, - \pteout[26]\, \pteout[27]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - pteout_17 <= \pteout[17]\; - pteout_4 <= \pteout[4]\; - pteout_3 <= \pteout[3]\; - pteout_2 <= \pteout[2]\; - pteout_27 <= \pteout[27]\; - pteout_26 <= \pteout[26]\; - pteout_24 <= \pteout[24]\; - pteout_22 <= \pteout[22]\; - pteout_21 <= \pteout[21]\; - pteout_15 <= \pteout[15]\; - pteout_14 <= \pteout[14]\; - pteout_6 <= \pteout[6]\; - pteout_20 <= \pteout[20]\; - pteout_19 <= \pteout[19]\; - pteout_18 <= \pteout[18]\; - pteout_16 <= \pteout[16]\; - pteout_13 <= \pteout[13]\; - pteout_10 <= \pteout[10]\; - pteout_9 <= \pteout[9]\; - pteout_12 <= \pteout[12]\; - pteout_8 <= \pteout[8]\; - pteout_23 <= \pteout[23]\; - pteout_25 <= \pteout[25]\; - pteout_11 <= \pteout[11]\; - hit_0 <= \hit_0\; - - \r.btag.PPN_RNIIN8MKO1[15]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[23]\, C => - pteout_m_i_0_15, Y => data_1_3_i_a3_1_0); - - \r.btag.I3_RNI8JOEC[0]\ : OR3B - port map(A => hf_1_1_1_a0_3_3, B => h_l2_1_3, C => - h_l3_1_4_i, Y => hf_1_1_1_a0_3_i); - - \r.btag.ACC_RNIPU6U49[2]\ : MX2C - port map(A => \pteout[4]\, B => pteout_0(4), S => - cam_hitaddr_18(1), Y => N_1471); - - \r.btag.LVL_RNI197RR[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.CTX_RNIKNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx(1), Y => h_c2_1_i); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[8]\); - - \r.btag.I2_RNIPTRT1[4]\ : NOR2 - port map(A => h_i22_5, B => h_i22_4, Y => h_l2_1_2); - - \r.btag.LVL_RNIIJ25R[1]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \LVL[1]\); - - \r.btag.I2_RNIR82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[63]\); - - \r.btag.I2_RNI5O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[19]\); - - \r.btag.I3_RNIQ8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIQ8291[2]\); - - \r.btag.PPN_RNIGC1HKO1[5]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[13]\, C => - pteout_m_i_4, Y => un2_wb_acc_iv_1_4); - - \r.btag.I3_RNI16BR4[0]\ : OR3C - port map(A => h_l3_1_4_1, B => \I3_RNIADVU[5]\, C => - h_l3_1_4_2, Y => h_l3_1_4_i); - - \r.btag.I3_RNISV7E1[1]\ : XA1 - port map(A => N_61, B => \un1_tag0[57]\, C => - \I3_RNIQ8291[2]\, Y => h_l3_1_4_0); - - \r.btag.LVL_RNIH6H6A1[0]\ : NOR2A - port map(A => trans_op, B => hm_1_1, Y => un1_tlbcami_3); - - \r.btag.VALID_RNIJ34581\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[67]\); - - \r.btag.M_RNIV4R6B1\ : NOR3 - port map(A => M_1, B => \pteout[6]\, C => hm_1_1, Y => - WBNEEDSYNC_m_0); - - \r.btag.I3_RNIUC3K1[3]\ : XA1 - port map(A => I3_1_i(3), B => \un1_tag0[59]\, C => - \I3_RNIIS1Q[4]\, Y => h_l3_1_4_2); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(5), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNIAC1HKO1[2]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[10]\, C => - pteout_m_i_1, Y => un2_wb_acc_iv_1_1); - - \r.btag.LVL_RNIMCRF[0]\ : NOR3A - port map(A => TYP_1_0(0), B => \LVL[1]\, C => \LVL[0]\, Y - => hf_1_1_1_a0_3_1); - - \r.btag.CTX_RNI8ULK1[0]\ : NOR2B - port map(A => h_c2_NE_5, B => h_c2_NE_4, Y => h_c2_NE_i_0); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => SU); - - \r.btag.CTX_RNIQNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx(4), Y => h_c2_4_i); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[36]\); - - \r.btag.PPN_RNIUR4BAS[19]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[27]\, Y => - pteout_m_i_18); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[10]\); - - \r.btag.I1_RNIM81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIM81Q[3]\); - - \r.btag.VALID_RNIBBKUR\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[57]\); - - \r.btag.CTX_RNIONI6[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx(3), Y => h_c2_3_i); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_28); - - \r.btag.VALID_RNING9S8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[38]\); - - \r.btag.PPN_RNIP74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[22]\, Y => - pteout_m_i_0_14); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_11); - - \r.btag.PPN_RNI8C1HKO1[1]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[9]\, C => - pteout_m_i_0_d0, Y => un2_wb_acc_iv_1_0); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[66]\); - - \r.btag.LVL_RNII5CGB[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1(0), Y => N_8); - - \r.btag.CTX_RNIKVAQ[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[68]\); - - \r.btag.PPN_RNIDMG8AS[9]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[17]\, Y => - pteout_m_i_8); - - \r.btag.VALID_RNIAMVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.PPN_RNIBMG8AS[7]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[15]\, Y => - pteout_m_i_6); - - \r.btag.LVL_RNIIL20A1[0]\ : MX2 - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.M_RNIUL9DB1\ : OR3A - port map(A => un1_tlbcami_3, B => M_1, C => \pteout[6]\, Y - => NEEDSYNC); - - \r.btag.CTX_RNISNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx(5), Y => h_c2_5_i); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[22]\); - - \r.btag.LVL_RNIVI4I7[1]\ : OR3C - port map(A => h_l2_1_2, B => hf_1_1_1_a1_2_1, C => h_l2_1_3, - Y => hf_1_1_1_a1_2_i); - - \r.btag.CTX_RNIUF5D[6]\ : XA1A - port map(A => ctx(6), B => \un1_tag0[41]\, C => h_c2_7_i, Y - => h_c2_NE_3); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_29); - - \r.btag.PPN_RNIAMG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[14]\, Y => - pteout_m_i_5); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[64]\); - - \r.btag.I2_RNIG9483[0]\ : NOR3 - port map(A => h_i22_1, B => h_i22_0, C => h_l2_1_3_1, Y => - h_l2_1_3); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_11, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.LVL_RNI9II3E[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \pteout[4]\); - - \r.btag.I1_RNIAE3N3[0]\ : NOR3C - port map(A => \I1_RNICG0Q[1]\, B => \I1_RNINO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.CTX_RNIKUAQ[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[25]\); - - \r.btag.PPN_RNIO34BAS[13]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[21]\, Y => - pteout_m_i_0_13); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \pteout[3]\); - - \r.btag.I2_RNIQOTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[60]\); - - \r.btag.I1_RNI752K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIM81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.LVL_RNIOA1DM6[0]\ : OR3 - port map(A => hit, B => \hit_0\, C => hit_1, Y => - cam_hitaddr_21_1(0)); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_1); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[11]\); - - \r.btag.SU_RNI8PHT1_0\ : OR2B - port map(A => hf_4_0, B => h_c2_NE_i_0, Y => hf_4); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_0_d0); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[20]\); - - \r.btag.I1_RNII41K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI540Q[6]\, Y => h_i13_NE_3); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_31); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[42]\); - - \r.btag.CTX_RNI0OI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx(7), Y => h_c2_7_i); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[65]\); - - \r.btag.I2_RNI2K0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.PPN_RNICV7MKO1[12]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[20]\, C => - pteout_m_i_11, Y => un2_wb_acc_iv_1_11); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(5), - Y => M_5); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[56]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNIEC1HKO1[4]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[12]\, C => - pteout_m_i_3, Y => un2_wb_acc_iv_1_3); - - \r.btag.SU_RNI8PHT1\ : OA1 - port map(A => h_c2_NE_i_0, B => SU, C => \un1_tag0[43]\, Y - => un3_hf); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[24]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[37]\); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[15]\); - - \r.btag.CTX_RNIEF5D[2]\ : XA1A - port map(A => ctx(2), B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.I3_RNIADVU[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => I3_1_5, Y => - \I3_RNIADVU[5]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_7); - - \r.btag.CTX_RNIINI6[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx(0), Y => h_c2_0_i); - - \r.btag.LVL_RNIU5DD2[0]\ : NOR2B - port map(A => hf_1_1_1_a0_3_1, B => un3_hf, Y => - hf_1_1_1_a0_3_2); - - \r.btag.PPN_RNIMC1HKO1[8]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[16]\, C => - pteout_m_i_7, Y => un2_wb_acc_iv_1_7); - - \r.btag.LVL_RNIMB4C2[1]\ : NOR3A - port map(A => un3_hf, B => TYP_1_0(0), C => \LVL[1]\, Y => - hf_1_1_1_a1_2_1); - - \r.btag.I1_RNIBD547[4]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.ACC_RNILU6U49[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0(2), S => - cam_hitaddr_18(1), Y => N_1469); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \LVL[0]\); - - \r.btag.VALID_RNI1UKTI\ : NOR3 - port map(A => h_l3_1_4_i, B => hm_4, C => h_l2_1, Y => hm_1); - - \r.btag.PPN_RNIAN7MKO1[11]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[19]\, C => - pteout_m_i_10, Y => un2_wb_acc_iv_1_10); - - \r.btag.M_RNIB26ELT\ : OR2B - port map(A => WBNEEDSYNC_m_0, B => un1_cam_hitaddr(58), Y - => WBNEEDSYNC_m); - - \r.btag.LVL_RNI4R849[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.SU_RNI0RR8\ : NOR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.LVL_RNIJAQU49[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => - cam_hitaddr_18(1), Y => N_1497); - - \r.btag.LVL_RNI7DUBI2[0]\ : AO1B - port map(A => hf_1_1, B => s2_flush_1, C => hm_1_1, Y => - \hit_0\); - - \r.btag.I1_RNINO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNINO091[0]\); - - \r.btag.ACC_RNINU6U49[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0(3), S => - cam_hitaddr_18(1), Y => N_1470); - - \r.btag.I3_RNIIS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIIS1Q[4]\); - - \r.btag.I1_RNIK5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIK5VU[5]\); - - \r.btag.PPN_RNI7MG8AS[3]\ : NAND2 - port map(A => \pteout[11]\, B => un1_cam_hitaddr(58), Y => - pteout_m_i_0_3); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_30); - - \r.btag.I2_RNIKK5AC[0]\ : OR3B - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE, Y => - h_l2_1); - - \r.btag.VALID_RNIC34O1\ : OR2B - port map(A => \un1_tag0[43]\, B => h_c2_NE_i_0, Y => hm_4); - - \r.btag.LVL_RNIHKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[12]\); - - \r.btag.LVL_RNIN39B4[0]\ : NOR2B - port map(A => hf_1_1_1_a0_3_2, B => h_l2_1_2, Y => - hf_1_1_1_a0_3_3); - - \r.btag.I1_RNI540Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI540Q[6]\); - - \r.btag.PPN_RNITN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[26]\, Y => - pteout_m_i_0_18); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => un1_tlbcami_3, B => tlbcam_write_op_1_0(5), Y - => M_1_sqmuxa); - - \r.btag.I1_RNICG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNICG0Q[1]\); - - \r.btag.PPN_RNI8F7MKO1[10]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[18]\, C => - pteout_m_i_9, Y => un2_wb_acc_iv_1_9); - - \r.btag.I3_RNIPB882[0]\ : XA1 - port map(A => I3_1_0, B => \un1_tag0[56]\, C => h_l3_1_4_0, - Y => h_l3_1_4_1); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[59]\); - - \r.btag.I1_RNIFQ0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIK5VU[5]\, Y => h_i13_NE_2); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[72]\); - - \r.btag.PPN_RNI6C1HKO1[0]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[8]\, C => - pteout_m_i_0_0, Y => data_1_3_i_a3_0_1(12)); - - \r.btag.I2_RNIV4UU[5]\ : XNOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => h_i22_5); - - \r.btag.I2_RNIJC1Q[0]\ : XNOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => h_i22_0); - - \r.btag.LVL_RNI17UNB[0]\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.PPN_RNIRF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(58), B => \pteout[24]\, Y => - pteout_m_i_0_16); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.PPN_RNIM79MKO1[17]\ : AOI1B - port map(A => un1_cam_hitaddr(58), B => \pteout[25]\, C => - pteout_m_i_0_17, Y => data_1_3_i_a3_1_2); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(5), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1_0 : in std_logic_vector(4 to 4); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_7 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(4 to 4); - un1_cam_hitaddr_1_0 : in std_logic; - un1_cam_hitaddr_1_6 : in std_logic; - un1_cam_hitaddr_1_5 : in std_logic; - un1_cam_hitaddr_0 : out std_logic; - un1_cam_hitaddr_2 : out std_logic; - un1_cam_hitaddr_4 : out std_logic; - un1_cam_hitaddr_5 : out std_logic; - un1_cam_hitaddr_6 : out std_logic; - un1_cam_hitaddr_1_d0 : out std_logic; - pteout_0 : in std_logic_vector(4 downto 2); - cam_hitaddr_18 : in std_logic_vector(1 to 1); - LVL_0 : in std_logic_vector(1 downto 0); - TYP_1 : in std_logic_vector(2 downto 1); - TYP_1_0 : in std_logic_vector(0 to 0); - tlbcam_write_op_1_0 : in std_logic_vector(4 to 4); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0_d0 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_27 : out std_logic; - pteout_6 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - ctx : in std_logic_vector(4 to 4); - I3_1_i : in std_logic_vector(3 to 3); - ctx_0_7 : in std_logic; - ctx_0_5 : in std_logic; - ctx_0_3 : in std_logic; - ctx_0_1 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_2 : in std_logic; - ctx_0_6 : in std_logic; - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - LVL : out std_logic_vector(1 downto 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_5 : in std_logic; - un2_wb_acc_iv_2 : out std_logic_vector(14 to 14); - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_0_d0 : out std_logic; - pteout_m_i_0_17 : in std_logic; - data_1_3_i_a3_2 : out std_logic_vector(29 to 29); - data_1_3_i_a3_3_2 : in std_logic; - data_1_3_i_a3_3_0 : in std_logic; - data_1_3_i_a3_5_2 : out std_logic; - data_1_3_i_a3_5_0 : out std_logic; - pteout_m_i_0_0_13 : in std_logic; - pteout_m_i_0_0_11 : in std_logic; - pteout_m_i_0_0_0 : in std_logic; - data_1_3_i_a3_0_2 : out std_logic_vector(15 to 15); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_1496 : out std_logic; - N_1468 : out std_logic; - NEEDSYNC : out std_logic; - N_1467 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_1466 : out std_logic; - N_1495 : out std_logic; - trans_op : in std_logic; - s2_flush_1 : in std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - hit_1 : in std_logic; - hit_0 : in std_logic; - N_2551 : out std_logic; - un1_cam_hitaddr_4_0 : in std_logic; - WBNEEDSYNC_m : out std_logic; - hit : in std_logic - ); - -end mmutlbcam_2_0; - -architecture DEF_ARCH of mmutlbcam_2_0 is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal h_c2_NE, h_c2_NE_4, h_c2_NE_5, hf_4, hf_4_0, - \un1_tag0[43]\, SU, \pteout_m_i_0[11]\, - \pteout_m_i_0[22]\, \pteout_m_i_0_0[25]\, - \pteout_m_i_0[24]\, \pteout_m_i_0[14]\, - \cam_hitaddr_12_i_a2_2[2]\, un18_hm, hm_1_1, hf_1_1_0, - hf_1_0, un3_hf, h_l3_1_4, \I3_RNIHS1Q[4]\, - \I3_RNIBG1Q[3]\, h_l3_1_3, \un1_tag0[61]\, h_l3_1_1, - \I3_RNIP8291[2]\, \I3_RNI1N55[1]\, \I3_RNISB0Q[0]\, - h_l2_1_3, \I2_RNIQ82Q[1]\, \I2_RNIIC1Q[0]\, h_l2_1_1, - h_l2_1_2, \un1_tag0[66]\, \I2_RNIU4UU[5]\, \un1_tag0[64]\, - \I2_RNI4O0Q[3]\, h_i13_NE_4, \I1_RNIBG0Q[1]\, - \I1_RNIMO091[0]\, h_i13_NE_1, h_i13_NE_3, \un1_tag0[75]\, - \I1_RNI440Q[6]\, h_i13_NE_2, \un1_tag0[72]\, - \I1_RNIJ5VU[5]\, \un1_tag0[70]\, \I1_RNIL81Q[3]\, - h_c2_5_i, h_c2_4_i, h_c2_NE_3, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, h_l2_1, h_i13_NE_i_0, hf_1, hf_3, \un45_res[3]\, - hf_2, \LVL[1]\, tlbcamo_needsync, \un1_cam_hitaddr[59]\, - \N_2551\, hm_4, hm_3, hm_1, \un1_tag0[56]\, - \un1_tag0[59]\, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[74]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[62]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[67]\, \un1_tag0[57]\, - \un1_tag0[58]\, \un1_tag0[60]\, \un1_tag0[68]\, - \un1_tag0[73]\, M_2, \pteout[6]\, M_5, h_su_cnt_1, hf_1_1, - M_1_sqmuxa, \LVL[0]\, N_89, N_90, N_92, N_94, N_93, N_95, - N_96, VALID_RNO_7, N_102, \pteout[2]\, \pteout[3]\, - \pteout[4]\, \pteout[8]\, \pteout[9]\, \pteout[10]\, - \pteout[11]\, \pteout[12]\, \pteout[13]\, \pteout[14]\, - \pteout[15]\, \pteout[16]\, \pteout[17]\, \pteout[18]\, - \pteout[19]\, \pteout[20]\, \pteout[21]\, \pteout[22]\, - \pteout[23]\, \pteout[24]\, \pteout[25]\, \pteout[26]\, - \pteout[27]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - pteout_17 <= \pteout[17]\; - pteout_4 <= \pteout[4]\; - pteout_3 <= \pteout[3]\; - pteout_2 <= \pteout[2]\; - pteout_27 <= \pteout[27]\; - pteout_6 <= \pteout[6]\; - pteout_26 <= \pteout[26]\; - pteout_25 <= \pteout[25]\; - pteout_24 <= \pteout[24]\; - pteout_23 <= \pteout[23]\; - pteout_22 <= \pteout[22]\; - pteout_21 <= \pteout[21]\; - pteout_20 <= \pteout[20]\; - pteout_19 <= \pteout[19]\; - pteout_18 <= \pteout[18]\; - pteout_16 <= \pteout[16]\; - pteout_15 <= \pteout[15]\; - pteout_14 <= \pteout[14]\; - pteout_13 <= \pteout[13]\; - pteout_12 <= \pteout[12]\; - pteout_11 <= \pteout[11]\; - pteout_10 <= \pteout[10]\; - pteout_9 <= \pteout[9]\; - pteout_8 <= \pteout[8]\; - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - N_2551 <= \N_2551\; - - \r.btag.LVL_RNIN7SP01[1]\ : MX2C - port map(A => hf_2, B => hf_1, S => TYP_1_0(0), Y => N_92); - - \r.btag.I3_RNIP8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIP8291[2]\); - - \r.btag.CTX_RNI4P98[6]\ : XA1A - port map(A => ctx_0_6, B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \p0.hf_4_RNI3FR49\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1_0(0), Y => N_95); - - \r.btag.PPN_RNILR3BAS[11]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[19]\, Y - => pteout_m_i_10); - - \r.btag.PPN_RNI3VGC9H3[14]\ : NOR3C - port map(A => \pteout_m_i_0[22]\, B => pteout_m_i_0_0_11, C - => data_1_3_i_a3_3_0, Y => data_1_3_i_a3_5_0); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[8]\); - - \r.btag.CTX_RNIJS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0_7, Y => h_c2_7_i); - - \r.btag.VALID_RNI8TNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1_0(0), Y => N_93); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \LVL[1]\); - - \r.btag.PPN_RNITR4BAS[19]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[27]\, Y - => pteout_m_i_18); - - \r.btag.LVL_RNITHHID[1]\ : OA1B - port map(A => h_l2_1, B => \LVL[1]\, C => hm_4, Y => N_90); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[63]\); - - \r.btag.I3_RNISB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNISB0Q[0]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[19]\); - - \r.btag.I1_RNIMO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIMO091[0]\); - - \r.btag.CTX_RNIFS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0_5, Y => h_c2_5_i); - - \r.btag.PPN_RNIO74BAS[14]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[22]\, Y - => \pteout_m_i_0[22]\); - - \r.btag.PPN_RNI4MG8AS[1]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[9]\, Y - => pteout_m_i_0_d0); - - \r.btag.LVL_RNIFKH2_0[0]\ : NOR2 - port map(A => \LVL[0]\, B => \LVL[1]\, Y => hf_1_0); - - \p0.hf_4\ : OR2 - port map(A => h_c2_NE, B => hf_4_0, Y => hf_4); - - \r.btag.PPN_RNICMG8AS[9]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[17]\, Y - => pteout_m_i_8); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[67]\); - - \p0.hf_4_RNIIGDC9\ : OR2B - port map(A => N_95, B => TYP_1(2), Y => N_96); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(4), Y => N_102); - - \r.btag.I2_RNIU4UU[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => - \I2_RNIU4UU[5]\); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNILC1HKO1[6]\ : NOR2B - port map(A => pteout_m_i_5, B => \pteout_m_i_0[14]\, Y => - un2_wb_acc_iv_2(14)); - - \r.btag.PPN_RNI3MG8AS[0]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[8]\, Y - => pteout_m_i_0_0_d0); - - \r.btag.LVL_RNIA85PQ[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_89); - - \r.btag.I3_RNIR5BR4[3]\ : NOR3C - port map(A => \I3_RNIHS1Q[4]\, B => \I3_RNIBG1Q[3]\, C => - h_l3_1_3, Y => h_l3_1_4); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[36]\); - - \r.btag.VALID_RNIGTJCI\ : OR3B - port map(A => h_l2_1, B => h_l3_1_4, C => hm_4, Y => hm_1); - - \r.btag.PPN_RNI7MG8AS[4]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[12]\, Y - => pteout_m_i_3); - - \r.btag.LVL_RNICTA7AS[0]\ : NOR2B - port map(A => un1_cam_hitaddr_4_0, B => \N_2551\, Y => - \un1_cam_hitaddr[59]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[10]\); - - \r.btag.VALID_RNIF3371\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_4); - - \r.btag.VALID_RNIIG8B8\ : OR2A - port map(A => h_i13_NE_i_0, B => hm_4, Y => hm_3); - - \r.btag.SU_RNI7K291\ : AO1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.CTX_RNI0HJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.I2_RNIC9483[0]\ : NOR3C - port map(A => \I2_RNIQ82Q[1]\, B => \I2_RNIIC1Q[0]\, C => - h_l2_1_1, Y => h_l2_1_3); - - \r.btag.LVL_RNIQ7JKI[0]\ : OR3C - port map(A => h_l2_1, B => h_l3_1_4, C => hf_1_1_0, Y => - hf_1); - - \r.btag.PPN_RNIP79MKO1[17]\ : NOR2B - port map(A => pteout_m_i_0_17, B => \pteout_m_i_0_0[25]\, Y - => data_1_3_i_a3_2(29)); - - \r.btag.PPN_RNI8MG8AS[5]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[13]\, Y - => pteout_m_i_4); - - \r.btag.M_RNI613RJT\ : OR3C - port map(A => hm_1_1, B => tlbcamo_needsync, C => - \un1_cam_hitaddr[59]\, Y => WBNEEDSYNC_m); - - \r.btag.LVL_RNICTA7AS_5[0]\ : NOR2A - port map(A => un1_cam_hitaddr_1_5, B => \N_2551\, Y => - un1_cam_hitaddr_5); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_28); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[17]\); - - \r.btag.I2_RNI0K0K1[2]\ : XA1 - port map(A => I2_1(2), B => \un1_tag0[64]\, C => - \I2_RNI4O0Q[3]\, Y => h_l2_1_1); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[21]\); - - \p0.h_c2_NE\ : NAND2 - port map(A => h_c2_NE_4, B => h_c2_NE_5, Y => h_c2_NE); - - \r.btag.LVL_RNIPD2F1[0]\ : NOR2B - port map(A => hf_1_0, B => un3_hf, Y => hf_1_1_0); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[38]\); - - \r.btag.ACC_RNIJU6U49[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0(2), S => - cam_hitaddr_18(1), Y => N_1466); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_102, B => un1_rst_i_0, Y => VALID_RNO_7); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[66]\); - - \r.btag.PPN_RNIQF4BAS[16]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[24]\, Y - => \pteout_m_i_0[24]\); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[68]\); - - \r.btag.CTX_RNIKO98[2]\ : XA1A - port map(A => ctx_0_2, B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.I2_RNINTRT1[4]\ : XA1 - port map(A => I2_1(4), B => \un1_tag0[66]\, C => - \I2_RNIU4UU[5]\, Y => h_l2_1_2); - - \r.btag.CTX_RNI7S44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_1, Y => h_c2_1_i); - - \r.btag.CTX_RNIPNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx(4), Y => h_c2_4_i); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_29); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[64]\); - - \r.btag.VALID_RNIE66I11\ : MX2C - port map(A => N_93, B => N_92, S => TYP_1(2), Y => N_94); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_7, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.LVL_RNIHAQU49[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => - cam_hitaddr_18(1), Y => N_1495); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \pteout[4]\); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[25]\); - - \r.btag.ACC_RNILU6U49[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0(3), S => - cam_hitaddr_18(1), Y => N_1467); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \pteout[3]\); - - \r.btag.LVL_RNIFKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[75]\); - - \r.btag.VALID_RNIAPGC1\ : NOR2B - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_1); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[11]\); - - \r.btag.M_RNIPK6Q91\ : OR3C - port map(A => trans_op, B => hm_1_1, C => tlbcamo_needsync, - Y => NEEDSYNC); - - \r.btag.CTX_RNICD1J[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.I1_RNIL81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIL81Q[3]\); - - \r.btag.I1_RNI440Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI440Q[6]\); - - \r.btag.I1_RNI552K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIL81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I1_RNIJ5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIJ5VU[5]\); - - \r.btag.I1_RNI3D547[4]\ : NOR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE_i_0); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_0_d0); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[20]\); - - \r.btag.I3_RNIMB882[0]\ : NOR3C - port map(A => \I3_RNIP8291[2]\, B => \I3_RNI1N55[1]\, C => - \I3_RNISB0Q[0]\, Y => h_l3_1_1); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_31); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[65]\); - - \r.btag.LVL_RNICTA7AS_1[0]\ : NOR2B - port map(A => un1_cam_hitaddr_1_6, B => \N_2551\, Y => - un1_cam_hitaddr_2); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(4), - Y => M_5); - - \r.btag.LVL_RNIO7VND[1]\ : OR3B - port map(A => un3_hf, B => h_l2_1, C => \LVL[1]\, Y => hf_2); - - \r.btag.LVL_RNIJAQU49[1]\ : MX2C - port map(A => \LVL[1]\, B => LVL_0(1), S => - cam_hitaddr_18(1), Y => N_1496); - - \r.btag.I3_RNIHS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIHS1Q[4]\); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[56]\); - - \r.btag.LVL_RNICTA7AS_0[0]\ : NOR2B - port map(A => un1_cam_hitaddr_1_5, B => \N_2551\, Y => - un1_cam_hitaddr_1_d0); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[71]\); - - \r.btag.LVL_RNICTA7AS_3[0]\ : NOR2A - port map(A => un1_cam_hitaddr_1_0, B => \N_2551\, Y => - un1_cam_hitaddr_4); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[9]\); - - \r.btag.PPN_RNI6MG8AS[3]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[11]\, Y - => \pteout_m_i_0[11]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[24]\); - - \r.btag.PPN_RNIBMG8AS[8]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[16]\, Y - => pteout_m_i_7); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.PPN_RNIMV3BAS[12]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[20]\, Y - => pteout_m_i_11); - - \r.btag.LVL_RNICTA7AS_4[0]\ : NOR2A - port map(A => un1_cam_hitaddr_1_6, B => \N_2551\, Y => - un1_cam_hitaddr_6); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[40]\); - - \r.btag.I1_RNI6E3N3[0]\ : NOR3C - port map(A => \I1_RNIBG0Q[1]\, B => \I1_RNIMO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.CTX_RNIBS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.I3_RNI1N55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNI1N55[1]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[37]\); - - \r.btag.LVL_RNIEKVC81[0]\ : MX2 - port map(A => N_89, B => N_90, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.PPN_RNIKN3BAS[10]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[18]\, Y - => pteout_m_i_9); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[15]\); - - \r.btag.LVL_RNIAURM25[0]\ : NOR3A - port map(A => un18_hm, B => hit, C => hm_1_1, Y => - \cam_hitaddr_12_i_a2_2[2]\); - - \r.btag.I1_RNIDQ0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIJ5VU[5]\, Y => h_i13_NE_2); - - \p0.hf_4_RNO\ : OR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[14]\); - - \r.btag.I2_RNI4O0Q[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => - \I2_RNI4O0Q[3]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_7); - - \r.btag.PPN_RNI9MG8AS[6]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[14]\, Y - => \pteout_m_i_0[14]\); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \LVL[0]\); - - \r.btag.LVL_RNISQ7J8[0]\ : OR3C - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE_i_0, - Y => hf_3); - - \r.btag.LVL_RNIDK1SM9[0]\ : OR3A - port map(A => \cam_hitaddr_12_i_a2_2[2]\, B => hit_0, C => - hit_1, Y => \N_2551\); - - \r.btag.ACC_RNINU6U49[2]\ : MX2C - port map(A => \pteout[4]\, B => pteout_0(4), S => - cam_hitaddr_18(1), Y => N_1468); - - \r.btag.I2_RNIQ82Q[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => - \I2_RNIQ82Q[1]\); - - \r.btag.PPN_RNIRJ4BAS[17]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[25]\, Y - => \pteout_m_i_0_0[25]\); - - \r.btag.CTX_RNI5S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_0, Y => h_c2_0_i); - - \r.btag.PPN_RNIN34BAS[13]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[21]\, Y - => pteout_m_i_0_13); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_30); - - \r.btag.PPN_RNIAMG8AS[7]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[15]\, Y - => pteout_m_i_6); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[12]\); - - \r.btag.PPN_RNI5MG8AS[2]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[10]\, Y - => pteout_m_i_1); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => \pteout[16]\); - - \r.btag.PPN_RNIPB4BAS[15]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[23]\, Y - => pteout_m_i_0_15); - - \r.btag.M_RNO_0\ : AOI1 - port map(A => hm_1_1, B => trans_op, C => - tlbcam_write_op_1_0(4), Y => M_1_sqmuxa); - - \r.btag.LVL_RNICTA7AS_2[0]\ : NOR2B - port map(A => un1_cam_hitaddr_1_0, B => \N_2551\, Y => - un1_cam_hitaddr_0); - - \r.btag.I1_RNIBG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNIBG0Q[1]\); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[59]\); - - \r.btag.M_RNICFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => tlbcamo_needsync); - - \r.btag.I1_RNIG41K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI440Q[6]\, Y => h_i13_NE_3); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[72]\); - - \r.btag.I3_RNIBG1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNIBG1Q[3]\); - - \r.btag.PPN_RNIBVHC9H3[16]\ : NOR3C - port map(A => \pteout_m_i_0[24]\, B => pteout_m_i_0_0_13, C - => data_1_3_i_a3_3_2, Y => data_1_3_i_a3_5_2); - - \r.btag.VALID_RNI9SSJB1\ : OR2B - port map(A => hf_1_1, B => s2_flush_1, Y => un18_hm); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.I2_RNI6K5AC[4]\ : NOR3C - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE_i_0, Y - => h_l2_1); - - \r.btag.PPN_RNISN4BAS[18]\ : OR2B - port map(A => \un1_cam_hitaddr[59]\, B => \pteout[26]\, Y - => pteout_m_i_0_18); - - \r.btag.PPN_RNIFC1HKO1[3]\ : AND2 - port map(A => \pteout_m_i_0[11]\, B => pteout_m_i_0_0_0, Y - => data_1_3_i_a3_0_2(15)); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(4), Q => \pteout[18]\); - - \r.btag.VALID_RNI785DB1\ : MX2C - port map(A => N_96, B => N_94, S => TYP_1(1), Y => hf_1_1); - - \r.btag.I3_RNIVO773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_1, Y - => h_l3_1_3); - - \r.btag.I2_RNIIC1Q[0]\ : XOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => - \I2_RNIIC1Q[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_5 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - tlbcam_write_op_1_1_0 : in std_logic_vector(1 to 1); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_17 : in std_logic; - hrdata_10 : in std_logic; - hrdata_7 : in std_logic; - hrdata_6 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_0_d0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(1 to 1); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - un1_cam_hitaddr_1_0 : out std_logic; - un1_cam_hitaddr_1_5 : out std_logic; - un1_cam_hitaddr_1_6 : out std_logic; - TYP_1 : in std_logic_vector(2 downto 0); - s2_entry : in std_logic_vector(2 to 2); - pteout_1 : in std_logic_vector(4 downto 2); - LVL_1 : in std_logic_vector(0 to 0); - tlbcam_write_op_1_0 : in std_logic_vector(1 to 1); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_3 : in std_logic_vector(2 to 2); - s2_entry_2 : in std_logic_vector(2 to 2); - pteout_0_17 : in std_logic; - pteout_0_4 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - ctx_0_d0 : in std_logic; - ctx_1 : in std_logic; - ctx_4 : in std_logic; - ctx_5 : in std_logic; - ctx_7 : in std_logic; - ctx_3 : in std_logic; - cam_hitaddr_21_1 : in std_logic_vector(0 to 0); - un1_cam_hitaddr : in std_logic_vector(62 to 62); - ctx_0_0 : in std_logic; - ctx_0_4 : in std_logic; - I1_1_6 : in std_logic; - I1_1_3 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_5 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I3_1_5 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - LVL_1_d0 : out std_logic; - cam_hitaddr_18 : in std_logic_vector(1 to 1); - cam_hitaddr_21 : out std_logic_vector(0 to 0); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_3043 : in std_logic; - s2_flush : in std_logic; - N_1206 : out std_logic; - un1_rst_i_0 : in std_logic; - N_1219 : out std_logic; - N_1482 : out std_logic; - N_1471 : in std_logic; - N_1481 : out std_logic; - N_1205 : out std_logic; - N_1470 : in std_logic; - N_1480 : out std_logic; - N_1235 : out std_logic; - N_1469 : in std_logic; - N_1479 : out std_logic; - N_1497 : in std_logic; - N_1505 : out std_logic; - NEEDSYNC : out std_logic; - s2_flush_1 : in std_logic; - trans_op : in std_logic; - N_2483 : in std_logic; - N_3046 : in std_logic; - N_1234 : out std_logic; - N_1233 : out std_logic; - N_1232 : out std_logic; - N_1231 : out std_logic; - N_1230 : out std_logic; - N_1229 : out std_logic; - N_1228 : out std_logic; - N_1227 : out std_logic; - N_1226 : out std_logic; - N_1225 : out std_logic; - N_1224 : out std_logic; - N_1223 : out std_logic; - N_1222 : out std_logic; - N_1221 : out std_logic; - N_1220 : out std_logic; - N_1218 : out std_logic; - N_1217 : out std_logic; - N_1216 : out std_logic; - N_1215 : out std_logic; - N_1214 : out std_logic; - N_1213 : out std_logic; - N_1212 : out std_logic; - N_1211 : out std_logic; - N_1210 : out std_logic; - N_1209 : out std_logic; - N_1208 : out std_logic; - N_1204 : out std_logic; - N_1203 : out std_logic; - N_1202 : out std_logic; - N_2551 : in std_logic; - cam_hit_all_5_sqmuxa : out std_logic; - cam_hit_all_5_sqmuxa_2 : in std_logic; - cam_hit_all_5_sqmuxa_0_a2_0 : out std_logic; - accexc_6_3 : in std_logic; - accexc_6_4 : in std_logic; - accexc_6 : out std_logic; - N_661 : in std_logic; - N_61 : in std_logic; - un1_cam_hitaddr_4_0 : out std_logic; - M_1 : in std_logic; - accexc_6_2 : in std_logic; - WBNEEDSYNC_m : in std_logic - ); - -end mmutlbcam_2_0_5; - -architecture DEF_ARCH of mmutlbcam_2_0_5 is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal accexc_6_5, WBNEEDSYNC_m_0, WBNEEDSYNC_m_0_0, hm_1_1, - \pteout[6]\, hf_1_0, \LVL[0]\, h_l3_1_4, h_l3_1_1, - \I3_RNI6DVU[5]\, h_l3_1_2, \un1_tag0[59]\, - \I3_RNIES1Q[4]\, \un1_tag0[56]\, h_l3_1_0, \un1_tag0[57]\, - \I3_RNIM8291[2]\, h_l2_1_4, h_l2_1_1, h_l2_1_0, h_l2_1_2, - \un1_tag0[66]\, \I2_RNIR4UU[5]\, \un1_tag0[64]\, - \I2_RNI1O0Q[3]\, \un1_tag0[62]\, \I2_RNIN82Q[1]\, - h_i13_NE_4, \I1_RNI8G0Q[1]\, \I1_RNIJO091[0]\, h_i13_NE_1, - h_i13_NE_3, \un1_tag0[74]\, \I1_RNI901Q[7]\, h_i13_NE_2, - \un1_tag0[73]\, \I1_RNINK1Q[4]\, \un1_tag0[70]\, - \I1_RNII81Q[3]\, h_c2_NE_5, h_c2_5_i, h_c2_4_i, h_c2_NE_3, - h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, \un1_tag0[41]\, - h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, h_l2_1, h_i13_NE, - h_l3_1, hf_4, \un1_tag0[43]\, SU, h_c2_NE, hf_3, un3_hf, - \un45_res[3]\, hf_2_i, \LVL[1]\, hf_1_i, - \cam_hitaddr_21[0]\, hit, hm_4, hm_3, hm_1, - \cam_hit_all_5_sqmuxa_0_a2_0\, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[72]\, \un1_tag0[75]\, - \un1_tag0[38]\, \pteout[0]\, \pteout[1]\, \pteout[2]\, - \pteout[7]\, \pteout[8]\, \pteout[9]\, \pteout[10]\, - \pteout[11]\, \pteout[12]\, \pteout[13]\, \pteout[14]\, - \pteout[15]\, \pteout[16]\, \pteout[18]\, \pteout[19]\, - \pteout[20]\, \pteout[21]\, \pteout[22]\, \pteout[23]\, - \pteout[24]\, \pteout[25]\, \pteout[26]\, \pteout[27]\, - \pteout[28]\, \pteout[29]\, \pteout[30]\, \pteout[31]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, - \un1_tag0[60]\, \un1_tag0[61]\, \un1_tag0[68]\, M_2, M_5, - un1_tlbcami_3, hf_1_1, M_1_sqmuxa, N_1, N_3, N_1493, - N_1463, N_1464, \pteout[3]\, N_9, N_8, N_6, N_7_i, N_5, - N_1465, \pteout[4]\, \pteout[17]\, VALID_RNO_12, N_15, - \un1_tag0[42]\, \un1_tag0[40]\, \un1_tag0[39]\, - \un1_tag0[36]\, \un1_tag0[35]\, \un1_tag0[58]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - LVL_1_d0 <= \LVL[1]\; - cam_hitaddr_21(0) <= \cam_hitaddr_21[0]\; - cam_hit_all_5_sqmuxa_0_a2_0 <= \cam_hit_all_5_sqmuxa_0_a2_0\; - - \r.btag.LVL_RNIA8FH91[0]\ : MX2C - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.CTX_RNIENI6[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_d0, Y => h_c2_0_i); - - \r.btag.LVL_RNIUI0FE9[0]\ : NOR2A - port map(A => hit, B => cam_hitaddr_21_1(0), Y => - \cam_hitaddr_21[0]\); - - \r.btag.ET_RNI3DTA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_2(2), Y => N_1203); - - \r.btag.VALID_RNIL3POI\ : NOR2 - port map(A => hm_4, B => h_l3_1, Y => hm_1); - - \r.btag.VALID_RNIGB8J1\ : OR2A - port map(A => \un1_tag0[43]\, B => h_c2_NE, Y => hm_4); - - \r.btag.I2_RNI1O0Q[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => - \I2_RNI1O0Q[3]\); - - \r.btag.VALID_RNI6MVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.M_RNII8MUA1\ : OR3A - port map(A => un1_tlbcami_3, B => M_1, C => \pteout[6]\, Y - => NEEDSYNC); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[8]\); - - \r.btag.PPN_RNIIR3BAS[11]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[19]\, Y => - pteout_m_i_10); - - \r.btag.I1_RNI901Q[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => I1_1_6, Y => - \I1_RNI901Q[7]\); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \LVL[1]\); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[63]\); - - \r.btag.ACC_RNIU3D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_1(4), S => - s2_entry(2), Y => N_1206); - - \r.btag.I1_RNIJO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIJO091[0]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[19]\); - - \r.btag.PPN_RNIPN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[26]\, Y => - pteout_m_i_0_18); - - \r.btag.PPN_RNI6K6B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_3(2), Y => N_1232); - - \r.btag.LVL_RNIV89BJI[0]\ : NOR2B - port map(A => \cam_hitaddr_21[0]\, B => cam_hitaddr_18(1), - Y => un1_cam_hitaddr_1_5); - - \r.btag.I1_RNIA41K1[6]\ : XA1 - port map(A => I1_1_5, B => \un1_tag0[74]\, C => - \I1_RNI901Q[7]\, Y => h_i13_NE_3); - - \r.btag.PPN_RNIJV3BAS[12]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[20]\, Y => - pteout_m_i_11); - - \r.btag.M_RNIK7HGLL3\ : NOR3C - port map(A => WBNEEDSYNC_m, B => WBNEEDSYNC_m_0, C => - accexc_6_2, Y => accexc_6_5); - - \r.btag.I3_RNIDB882[0]\ : XA1 - port map(A => I3_1_0, B => \un1_tag0[56]\, C => h_l3_1_0, Y - => h_l3_1_1); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[67]\); - - \r.btag.PPN_RNI6S6B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_3(2), Y => N_1223); - - \r.btag.I1_RNINK1Q[4]\ : XOR2 - port map(A => \un1_tag0[72]\, B => I1_1_3, Y => - \I1_RNINK1Q[4]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(1), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[41]\); - - \r.btag.CTX_RNISNI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_7, Y => h_c2_7_i); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[36]\); - - \r.btag.LVL_RNI9KH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.PPN_RNI4C6B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_3(2), Y => N_1231); - - \r.btag.LVL_RNI9E44E[1]\ : NOR3A - port map(A => un3_hf, B => \LVL[1]\, C => h_l2_1, Y => - hf_2_i); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[10]\); - - \r.btag.I1_RNI8G0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNI8G0Q[1]\); - - \r.btag.I2_RNIN82Q[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => - \I2_RNIN82Q[1]\); - - \r.btag.I2_RNIH6065[0]\ : NOR3C - port map(A => h_l2_1_1, B => h_l2_1_0, C => h_l2_1_2, Y => - h_l2_1_4); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.SU_RNIAKK6B\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1(0), Y => N_8); - - \r.btag.PPN_RNIHN3BAS[10]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[18]\, Y => - pteout_m_i_9); - - \r.btag.I3_RNIM8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIM8291[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.ACC_RNIFHFO0S[0]\ : MX2C - port map(A => N_1463, B => N_1469, S => N_2551, Y => N_1479); - - \r.btag.CTX_RNIMNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_4, Y => h_c2_4_i); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_0_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => un1_rst_i_0, B => N_15, Y => VALID_RNO_12); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[66]\); - - \r.btag.CTX_RNIKNI6[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_3, Y => h_c2_3_i); - - \r.btag.I1_RNIBC547[5]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[68]\); - - \r.btag.ACC_RNIHU6U49[2]\ : MX2C - port map(A => \pteout[4]\, B => pteout_0_4, S => - cam_hitaddr_18(1), Y => N_1465); - - \r.btag.LVL_RNI68V1O2[0]\ : AOI1 - port map(A => hf_1_1, B => s2_flush_1, C => hm_1_1, Y => - hit); - - \r.btag.I3_RNI5OG5H[0]\ : OR2A - port map(A => h_l3_1_4, B => h_l2_1, Y => h_l3_1); - - \r.btag.I3_RNIKV7E1[1]\ : XA1 - port map(A => N_61, B => \un1_tag0[57]\, C => - \I3_RNIM8291[2]\, Y => h_l3_1_0); - - \r.btag.I3_RNIMC3K1[3]\ : XA1 - port map(A => I3_1_i(3), B => \un1_tag0[59]\, C => - \I3_RNIES1Q[4]\, Y => h_l3_1_2); - - \r.btag.PPN_RNIE106[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_3(2), Y => N_1218); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_0_22, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[29]\); - - \r.btag.LVL_RNIU366[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_3(2), - Y => N_1234); - - \r.btag.ACC_RNIDU6U49[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_1(2), S => - cam_hitaddr_18(1), Y => N_1463); - - \r.btag.LVL_RNIB72B5J[0]\ : OR2B - port map(A => \cam_hitaddr_21[0]\, B => N_2551, Y => N_1482); - - \r.btag.SU_RNIPL6EB\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_12, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.PPN_RNIAC7B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_3(2), Y => N_1225); - - \r.btag.LVL_RNIB9MP0S[0]\ : MX2C - port map(A => N_1493, B => N_1497, S => N_2551, Y => N_1505); - - \r.btag.VALID_RNIQ40D21\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7_i); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[4]\); - - \r.btag.PPN_RNI7MG8AS[7]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[15]\, Y => - pteout_m_i_6); - - \r.btag.I1_RNIV42K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNII81Q[3]\, Y => h_i13_NE_1); - - \r.btag.PPN_RNI9HV5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_2(2), Y => N_1217); - - \r.btag.ACC_RNIFU6U49[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - cam_hitaddr_18(1), Y => N_1464); - - \r.btag.PPN_RNI9MG8AS[9]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[17]\, Y => - pteout_m_i_8); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[25]\); - - \r.btag.M_RNIVKIVKT\ : OR2B - port map(A => WBNEEDSYNC_m_0_0, B => un1_cam_hitaddr(62), Y - => WBNEEDSYNC_m_0); - - \r.btag.LVL_RNI9PTN91[0]\ : NOR2B - port map(A => hm_1_1, B => trans_op, Y => un1_tlbcami_3); - - \r.btag.I1_RNI7Q0P1[5]\ : XA1 - port map(A => N_661, B => \un1_tag0[73]\, C => - \I1_RNINK1Q[4]\, Y => h_i13_NE_2); - - \r.btag.LVL_RNI5S2B3H[0]\ : OR2A - port map(A => \cam_hit_all_5_sqmuxa_0_a2_0\, B => N_2551, Y - => cam_hit_all_5_sqmuxa); - - \r.btag.I2_RNIHTRT1[4]\ : XA1 - port map(A => I2_1(4), B => \un1_tag0[66]\, C => - \I2_RNIR4UU[5]\, Y => h_l2_1_2); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[3]\); - - \r.btag.SU_RNI81MO1\ : OR3A - port map(A => \un1_tag0[43]\, B => SU, C => h_c2_NE, Y => - hf_4); - - \r.btag.PPN_RNIL74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[22]\, Y => - pteout_m_i_0_14); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[60]\); - - \r.btag.ET_RNI15TA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_2(2), Y => N_1202); - - \r.btag.PPN_RNIIC8B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_3(2), Y => N_1229); - - \r.btag.LVL_RNI5DEJ11[1]\ : MX2 - port map(A => hf_2_i, B => hf_1_i, S => TYP_1(0), Y => N_5); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[75]\); - - \r.btag.CTX_RNIGNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_1, Y => h_c2_1_i); - - \r.btag.PPN_RNI1MG8AS[1]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[9]\, Y => - pteout_m_i_0_d0); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_0_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[1]\); - - \r.btag.SU_RNI81MO1_0\ : OA1A - port map(A => h_c2_NE, B => SU, C => \un1_tag0[43]\, Y => - un3_hf); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[11]\); - - \r.btag.PPN_RNIMB4BAS[15]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[23]\, Y => - pteout_m_i_0_15); - - \r.btag.PPN_RNIVGV5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_2(2), Y => N_1212); - - \r.btag.PPN_RNI8S6B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_3(2), Y => N_1233); - - \r.btag.PPN_RNITGV5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_2(2), Y => N_1211); - - \r.btag.PPN_RNI4K6B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_3(2), Y => N_1222); - - \r.btag.I2_RNISI5AC[0]\ : OR2A - port map(A => h_l2_1_4, B => h_i13_NE, Y => h_l2_1); - - \r.btag.PPN_RNI5HV5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_2(2), Y => N_1215); - - \r.btag.PPN_RNI2MG8AS[2]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[10]\, Y => - pteout_m_i_1); - - \r.btag.LVL_RNI9KH2_0[0]\ : NOR2 - port map(A => \LVL[0]\, B => \LVL[1]\, Y => hf_1_0); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[20]\); - - \r.btag.PPN_RNI4MG8AS[4]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[12]\, Y => - pteout_m_i_3); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[65]\); - - \r.btag.CTX_RNIO3TN[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_0_27, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(1), - Y => M_5); - - \r.btag.I3_RNIES1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIES1Q[4]\); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[56]\); - - \r.btag.LVL_RNIV89BJI_2[0]\ : NOR2 - port map(A => \cam_hitaddr_21[0]\, B => cam_hitaddr_18(1), - Y => un1_cam_hitaddr_1_6); - - \r.btag.CTX_RNIG6QF1[0]\ : OR2B - port map(A => h_c2_NE_5, B => h_c2_NE_4, Y => h_c2_NE); - - \r.btag.PPN_RNI0MG8AS[0]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[8]\, Y => - pteout_m_i_0_0); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[70]\); - - \r.btag.PPN_RNI046B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_3(2), Y => N_1220); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[24]\); - - \r.btag.LVL_RNIS1DV8[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.I1_RNIQD3N3[0]\ : NOR3C - port map(A => \I1_RNI8G0Q[1]\, B => \I1_RNIJO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.LVL_RNIQF04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_1235); - - \r.btag.ACC_RNIT7I5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_2(2), Y => N_1204); - - \r.btag.CTX_RNIO2TN[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.PPN_RNIG48B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_3(2), Y => N_1228); - - \r.btag.M_RNIP456\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_2(2), Y => N_1208); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[40]\); - - \r.btag.PPN_RNIOJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[25]\, Y => - pteout_m_i_0_17); - - \r.btag.I3_RNI6DVU[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => I3_1_5, Y => - \I3_RNI6DVU[5]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[37]\); - - \r.btag.LVL_RNIV89BJI_0[0]\ : NOR2A - port map(A => cam_hitaddr_18(1), B => \cam_hitaddr_21[0]\, - Y => un1_cam_hitaddr_1_0); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_0_15, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[15]\); - - \r.btag.PPN_RNINF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[24]\, Y => - pteout_m_i_0_16); - - \r.btag.PPN_RNI8MG8AS[8]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[16]\, Y => - pteout_m_i_7); - - \r.btag.PPN_RNIADQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_1219); - - \r.btag.ACC_RNINHFO0S[2]\ : MX2C - port map(A => N_1465, B => N_1471, S => N_2551, Y => N_1481); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[14]\); - - \r.btag.LVL_RNIBAQU49[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_1(0), S => - cam_hitaddr_18(1), Y => N_1493); - - \r.btag.I2_RNIQJ0K1[2]\ : XA1 - port map(A => I2_1(2), B => \un1_tag0[64]\, C => - \I2_RNI1O0Q[3]\, Y => h_l2_1_1); - - \r.btag.CTX_RNIAKNA[6]\ : XA1A - port map(A => ctx_0_4, B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[7]\); - - \r.btag.CTX_RNIQJNA[2]\ : XA1A - port map(A => ctx_0_0, B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.PPN_RNI847B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_3(2), Y => N_1224); - - \r.btag.PPN_RNI6MG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[14]\, Y => - pteout_m_i_5); - - \r.btag.PPN_RNIRGV5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_2(2), Y => N_1210); - - \r.btag.LVL_RNIMDO0J[0]\ : NOR3B - port map(A => un3_hf, B => hf_1_0, C => h_l3_1, Y => hf_1_i); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \LVL[0]\); - - \r.btag.PPN_RNIES7B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_3(2), Y => N_1227); - - \r.btag.ACC_RNIS3D3[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_1(3), S => - s2_entry(2), Y => N_1205); - - \r.btag.LVL_RNILLFHR[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.PPN_RNI1HV5[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry_2(2), Y => N_1213); - - \r.btag.PPN_RNIQR4BAS[19]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[27]\, Y => - pteout_m_i_18); - - \r.btag.PPN_RNI3HV5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_2(2), Y => N_1214); - - \r.btag.I3_RNI95BR4[0]\ : NOR3C - port map(A => h_l3_1_1, B => \I3_RNI6DVU[5]\, C => h_l3_1_2, - Y => h_l3_1_4); - - \r.btag.I2_RNI6L3K1[0]\ : XA1 - port map(A => I2_1(0), B => \un1_tag0[62]\, C => - \I2_RNIN82Q[1]\, Y => h_l2_1_0); - - \r.btag.VALID_RNIQBO9E1\ : MX2C - port map(A => N_9, B => N_7_i, S => TYP_1(1), Y => hf_1_1); - - \r.btag.LVL_RNIHOMUD[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.ACC_RNIJHFO0S[1]\ : MX2C - port map(A => N_1464, B => N_1470, S => N_2551, Y => N_1480); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[30]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[74]\); - - \r.btag.I1_RNII81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNII81Q[3]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_0_12, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[12]\); - - \r.btag.CTX_RNIONI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_5, Y => h_c2_5_i); - - \r.btag.LVL_RNIV89BJI_1[0]\ : NOR2A - port map(A => \cam_hitaddr_21[0]\, B => cam_hitaddr_18(1), - Y => un1_cam_hitaddr_4_0); - - \r.btag.C_RNI5456\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_2(2), Y => N_1209); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_0_26, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_0_23, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_0_16, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => un1_tlbcami_3, B => tlbcam_write_op_1_0(1), Y - => M_1_sqmuxa); - - \r.btag.M_RNI8T1T7K3\ : OR3C - port map(A => accexc_6_4, B => accexc_6_3, C => accexc_6_5, - Y => accexc_6); - - \r.btag.PPN_RNI2C6B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_3(2), Y => N_1221); - - \r.btag.PPN_RNICK7B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_3(2), Y => N_1226); - - \r.btag.PPN_RNI5MG8AS[5]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[13]\, Y => - pteout_m_i_4); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[72]\); - - \r.btag.PPN_RNIK34BAS[13]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[21]\, Y => - pteout_m_i_0_13); - - \r.btag.M_RNIJN7OA1\ : NOR3A - port map(A => hm_1_1, B => M_1, C => \pteout[6]\, Y => - WBNEEDSYNC_m_0_0); - - \r.btag.PPN_RNI7HV5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_2(2), Y => N_1216); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.LVL_RNIO71FC7[0]\ : NOR2B - port map(A => hit, B => cam_hit_all_5_sqmuxa_2, Y => - \cam_hit_all_5_sqmuxa_0_a2_0\); - - \r.btag.PPN_RNI3MG8AS[3]\ : OR2B - port map(A => un1_cam_hitaddr(62), B => \pteout[11]\, Y => - pteout_m_i_0_3); - - \r.btag.I2_RNIR4UU[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => - \I2_RNIR4UU[5]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \un1_tag0[73]\); - - \r.btag.PPN_RNI246B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_3(2), Y => N_1230); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(1), Q => \pteout[18]\); - - \r.btag.VALID_RNIRNDN8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_work_leon3mp_wfp_rtl_3 is - - port( clk : in std_logic; - address : in std_logic_vector(2 downto 0); - datain : in std_logic_vector(29 downto 0); - dataout : out std_logic_vector(29 downto 0); - enable : in std_logic; - write : in std_logic - ); - -end proasic3_syncram_work_leon3mp_wfp_rtl_3; - -architecture DEF_ARCH of proasic3_syncram_work_leon3mp_wfp_rtl_3 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ0_1 is - - port( address : in std_logic_vector(31 downto 2); - s2_entry : in std_logic_vector(2 downto 0); - twowner_1 : in std_logic_vector(0 to 0); - aaddr : inout std_logic_vector(31 downto 2) := (others => 'Z'); - dr1write_0_sqmuxa : in std_logic; - syncramZ0_1_VCC : in std_logic; - lclk_c : in std_logic; - N_709 : out std_logic - ); - -end syncramZ0_1; - -architecture DEF_ARCH of syncramZ0_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_3 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(2 downto 0) := (others => 'U'); - datain : in std_logic_vector(29 downto 0) := (others => 'U'); - dataout : out std_logic_vector(29 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \aaddr_0[7]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_3 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_3(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_3 - port map(clk => lclk_c, address(2) => s2_entry(2), - address(1) => s2_entry(1), address(0) => s2_entry(0), - datain(29) => address(31), datain(28) => address(30), - datain(27) => address(29), datain(26) => address(28), - datain(25) => address(27), datain(24) => address(26), - datain(23) => address(25), datain(22) => address(24), - datain(21) => address(23), datain(20) => address(22), - datain(19) => address(21), datain(18) => address(20), - datain(17) => address(19), datain(16) => address(18), - datain(15) => address(17), datain(14) => address(16), - datain(13) => address(15), datain(12) => address(14), - datain(11) => address(13), datain(10) => address(12), - datain(9) => address(11), datain(8) => address(10), - datain(7) => address(9), datain(6) => address(8), - datain(5) => address(7), datain(4) => address(6), - datain(3) => address(5), datain(2) => address(4), - datain(1) => address(3), datain(0) => address(2), - dataout(29) => aaddr(31), dataout(28) => aaddr(30), - dataout(27) => aaddr(29), dataout(26) => aaddr(28), - dataout(25) => aaddr(27), dataout(24) => aaddr(26), - dataout(23) => aaddr(25), dataout(22) => aaddr(24), - dataout(21) => aaddr(23), dataout(20) => aaddr(22), - dataout(19) => aaddr(21), dataout(18) => aaddr(20), - dataout(17) => aaddr(19), dataout(16) => aaddr(18), - dataout(15) => aaddr(17), dataout(14) => aaddr(16), - dataout(13) => aaddr(15), dataout(12) => aaddr(14), - dataout(11) => aaddr(13), dataout(10) => aaddr(12), - dataout(9) => aaddr(11), dataout(8) => aaddr(10), - dataout(7) => aaddr(9), dataout(6) => aaddr(8), - dataout(5) => \aaddr_0[7]\, dataout(4) => aaddr(6), - dataout(3) => aaddr(5), dataout(2) => aaddr(4), - dataout(1) => aaddr(3), dataout(0) => aaddr(2), enable - => syncramZ0_1_VCC, write => dr1write_0_sqmuxa); - - GND_i_0 : GND - port map(Y => GND_0); - - \proa3.x0_RNIRE9I\ : MX2C - port map(A => aaddr(7), B => \aaddr_0[7]\, S => - twowner_1(0), Y => N_709); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_3 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1_0 : in std_logic_vector(7 to 7); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_7 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(7 to 7); - cam_hitaddr_18 : in std_logic_vector(1 to 1); - LVL_0 : in std_logic_vector(1 to 1); - TYP_1 : in std_logic_vector(2 downto 0); - tlbcam_write_op_1_0 : in std_logic_vector(7 to 7); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - ctx_0_3 : in std_logic; - ctx_0_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - ctx_6 : in std_logic; - ctx_4 : in std_logic; - ctx_3 : in std_logic; - ctx_0_d0 : in std_logic; - ctx_1 : in std_logic; - ctx_5 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I1_1_6 : in std_logic; - I1_1_3 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_5 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_11 : in std_logic; - pteout_m_i_10 : in std_logic; - pteout_m_i_8 : in std_logic; - pteout_m_i_6 : in std_logic; - pteout_m_i_4 : in std_logic; - pteout_m_i_1 : in std_logic; - pteout_m_i_0_d0 : in std_logic; - pteout_m_i_18 : in std_logic; - pteout_m_i_3 : in std_logic; - un2_wb_acc_iv_2_11 : out std_logic; - un2_wb_acc_iv_2_10 : out std_logic; - un2_wb_acc_iv_2_8 : out std_logic; - un2_wb_acc_iv_2_6 : out std_logic; - un2_wb_acc_iv_2_4 : out std_logic; - un2_wb_acc_iv_2_1 : out std_logic; - un2_wb_acc_iv_2_0 : out std_logic; - un2_wb_acc_iv_2_18 : out std_logic; - un2_wb_acc_iv_2_3 : out std_logic; - data_1_3_i_a3_3 : in std_logic_vector(30 to 30); - data_1_3_i_a3_5 : out std_logic_vector(30 to 30); - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - pteout_m_i_0_18 : in std_logic; - pteout_m_i_0_13 : in std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_14 : out std_logic; - pteout_11 : out std_logic; - pteout_8 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_17 : out std_logic; - pteout_15 : out std_logic; - pteout_13 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_27 : out std_logic; - pteout_12 : out std_logic; - pteout_26 : out std_logic; - pteout_21 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(56 to 56); - data_1_3_i_a3_2_0 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_1498 : out std_logic; - NEEDSYNC : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - trans_op : in std_logic; - s2_flush_1 : in std_logic; - hit : out std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - WBNEEDSYNC_m : out std_logic; - N_661 : in std_logic - ); - -end mmutlbcam_2_0_3; - -architecture DEF_ARCH of mmutlbcam_2_0_3 is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \data_1_3_i_a3_2[30]\, hm_1_1_3_m8_i_1, - hf_1_1_1_a0_3_0, h_l3_1_4_i_0, hm_1_1_3_m8_i_0, h_c2_NE_4, - h_c2_NE_5, \un1_tag0[43]\, hm_1_1_3_m8_i_o5_0, h_l2_1_2, - h_l2_1_3, hf_1_1_1_a0_3_2, un3_hf, hf_1_1_1_a0_3_0_0, - hf_1_1_1_a1_2_2, hf_1_1_1_a1_2_1, h_l3_1_4_3, - \un1_tag0[61]\, h_l3_1_4_1, \I3_RNIS8291[2]\, - \I3_RNI4N55[1]\, \I3_RNIVB0Q[0]\, h_i13_NE_4, - \I1_RNIEG0Q[1]\, \I1_RNIPO091[0]\, h_i13_NE_1, h_i13_NE_3, - \un1_tag0[74]\, \I1_RNIF01Q[7]\, h_i13_NE_2, - \un1_tag0[73]\, \I1_RNITK1Q[4]\, \un1_tag0[70]\, - \I1_RNIO81Q[3]\, h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, - h_l2_1_3_0, \un1_tag0[62]\, h_i22_1, hf_4_0, SU, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, hf_3, - \un45_res[3]\, h_i13_NE, hf_4, tlbcamo_needsync, - hm_1_1_3_N_9, \I3_RNIKS1Q[4]\, \I3_RNIEG1Q[3]\, - hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, hm_1_1_3_N_14, - hm_1_1_3_N_12, \LVL[1]\, N_5, \LVL[0]\, h_i22_5, h_i22_4, - \un1_tag0[56]\, \un1_tag0[59]\, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[72]\, \un1_tag0[75]\, - \un1_tag0[35]\, \un1_tag0[36]\, \un1_tag0[38]\, - \un1_tag0[39]\, \un1_tag0[40]\, \un1_tag0[42]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[66]\, - \un1_tag0[67]\, \un1_tag0[57]\, \un1_tag0[58]\, - \un1_tag0[60]\, \un1_tag0[68]\, M_2, \pteout[6]\, M_5, - h_su_cnt_1, hf_1_1, M_1_sqmuxa, N_7, N_6, N_8, N_9, - VALID_RNO_10, N_15, \pteout[8]\, \pteout[9]\, - \pteout[10]\, \pteout[11]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[15]\, \pteout[16]\, \pteout[17]\, - \pteout[18]\, \pteout[19]\, \pteout[20]\, \pteout[21]\, - \pteout[22]\, \pteout[23]\, \pteout[24]\, \pteout[25]\, - \pteout[26]\, \pteout[27]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - pteout_6 <= \pteout[6]\; - pteout_25 <= \pteout[25]\; - pteout_24 <= \pteout[24]\; - pteout_23 <= \pteout[23]\; - pteout_22 <= \pteout[22]\; - pteout_18 <= \pteout[18]\; - pteout_16 <= \pteout[16]\; - pteout_14 <= \pteout[14]\; - pteout_11 <= \pteout[11]\; - pteout_8 <= \pteout[8]\; - pteout_20 <= \pteout[20]\; - pteout_19 <= \pteout[19]\; - pteout_17 <= \pteout[17]\; - pteout_15 <= \pteout[15]\; - pteout_13 <= \pteout[13]\; - pteout_10 <= \pteout[10]\; - pteout_9 <= \pteout[9]\; - pteout_27 <= \pteout[27]\; - pteout_12 <= \pteout[12]\; - pteout_26 <= \pteout[26]\; - pteout_21 <= \pteout[21]\; - - \r.btag.VALID_RNI43MO1\ : NOR2B - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.LVL_RNIKL872[1]\ : NOR3A - port map(A => un3_hf, B => TYP_1_0(0), C => \LVL[1]\, Y => - hf_1_1_1_a1_2_1); - - \r.btag.VALID_RNIV0TKR\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[8]\); - - \r.btag.SU_RNIUT7L1\ : AO1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \LVL[1]\); - - \r.btag.VALID_RNIIKDG71\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.CTX_RNISVAQ[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[63]\); - - \r.btag.I3_RNIVB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIVB0Q[0]\); - - \r.btag.I3_RNIEG1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNIEG1Q[3]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[19]\); - - \r.btag.VALID_RNIRDD64\ : NOR3C - port map(A => un3_hf, B => hf_1_1_1_a0_3_0_0, C => h_l2_1_2, - Y => hf_1_1_1_a0_3_2); - - \r.btag.PPN_RNIEMG8AS[8]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[16]\, Y => - pteout_m_i_7); - - \r.btag.LVL_RNIT0D5B[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1_0(0), Y => N_8); - - \r.btag.PPN_RNIUJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[25]\, Y => - pteout_m_i_0_17); - - \r.btag.PPN_RNIDN7MKO1[11]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[19]\, C => - pteout_m_i_10, Y => un2_wb_acc_iv_2_10); - - \r.btag.CTX_RNI48FL[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(7), Y => N_15); - - \r.btag.I1_RNI49BRQ[5]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.PPN_RNIHC1HKO1[4]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[12]\, C => - pteout_m_i_3, Y => un2_wb_acc_iv_2_3); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[41]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => SU); - - \r.btag.PPN_RNITN9MKO1[19]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[27]\, C => - pteout_m_i_18, Y => un2_wb_acc_iv_2_18); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[36]\); - - \r.btag.I2_RNIO9483[0]\ : NOR2 - port map(A => h_l2_1_3_1, B => h_l2_1_3_0, Y => h_l2_1_3); - - \r.btag.I3_RNIS8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIS8291[2]\); - - \r.btag.LVL_RNIC2VCB[0]\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[10]\); - - \r.btag.I3_RNI4N55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNI4N55[1]\); - - \r.btag.LVL_RNILKH2_0[0]\ : NOR2 - port map(A => \LVL[1]\, B => \LVL[0]\, Y => hf_1_1_1_a0_3_0); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNIJC1HKO1[5]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[13]\, C => - pteout_m_i_4, Y => un2_wb_acc_iv_2_4); - - \r.btag.LVL_RNIQCRF[0]\ : NOR2B - port map(A => hf_1_1_1_a0_3_0, B => TYP_1_0(0), Y => - hf_1_1_1_a0_3_0_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_28); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[21]\); - - \r.btag.CTX_RNI6KNA[2]\ : XA1A - port map(A => ctx_1, B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_10); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[66]\); - - \r.btag.CTX_RNI2G5D[6]\ : XA1A - port map(A => ctx_5, B => \un1_tag0[41]\, C => h_c2_7_i, Y - => h_c2_NE_3); - - \r.btag.I1_RNIM41K1[6]\ : XA1 - port map(A => I1_1_5, B => \un1_tag0[74]\, C => - \I1_RNIF01Q[7]\, Y => h_i13_NE_3); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[68]\); - - \r.btag.PPN_RNIH78MKO1[13]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[21]\, C => - pteout_m_i_0_13, Y => data_1_3_i_a3_2_0); - - \r.btag.LVL_RNIHJ454[1]\ : NOR2B - port map(A => hf_1_1_1_a1_2_1, B => h_l2_1_2, Y => - hf_1_1_1_a1_2_2); - - \r.btag.CTX_RNIMNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_d0, Y => h_c2_1_i); - - \r.btag.I2_RNI15UU[5]\ : XNOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => h_i22_5); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[22]\); - - \r.btag.SU_RNI4RR8\ : NOR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_2); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_29); - - \r.btag.LVL_RNIRFEBC[1]\ : AO1A - port map(A => h_i13_NE, B => hm_1_1_3_m8_i_o5_0, C => - \LVL[1]\, Y => hm_1_1_3_N_12); - - \r.btag.CTX_RNISNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_3, Y => h_c2_4_i); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_10, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.I2_RNI6K0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_4); - - \r.btag.LVL_RNIK5DV8[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.VALID_RNI0US9C\ : OR3B - port map(A => hf_1_1_1_a0_3_2, B => h_l2_1_3, C => - h_l3_1_4_i_0, Y => hf_1_1_1_a0_3_i); - - \r.btag.PPN_RNICMG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[14]\, Y => - pteout_m_i_5); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[25]\); - - \r.btag.PPN_RNIBC1HKO1[1]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[9]\, C => - pteout_m_i_0_d0, Y => un2_wb_acc_iv_2_0); - - \r.btag.I3_RNIKS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIKS1Q[4]\); - - \r.btag.I1_RNIB52K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIO81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I3_RNID6BR4[3]\ : OR3C - port map(A => \I3_RNIKS1Q[4]\, B => \I3_RNIEG1Q[3]\, C => - h_l3_1_4_3, Y => h_l3_1_4_i_0); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_3); - - \r.btag.I1_RNIRD547[5]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[60]\); - - \r.btag.LVL_RNILKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[75]\); - - \r.btag.I2_RNISOTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.CTX_RNIUNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_4, Y => h_c2_5_i); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_1); - - \r.btag.CTX_RNIES44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.PPN_RNIR74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[22]\, Y => - pteout_m_i_0_14); - - \r.btag.M_RNIM09FR\ : OR3B - port map(A => trans_op, B => tlbcamo_needsync, C => - hm_1_1_3_N_9, Y => NEEDSYNC); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[11]\); - - \r.btag.I1_RNIPO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIPO091[0]\); - - \r.btag.I1_RNIO81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIO81Q[3]\); - - \r.btag.PPN_RNIRF9MKO1[18]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[26]\, C => - pteout_m_i_0_18, Y => \data_1_3_i_a3_2[30]\); - - \r.btag.I1_RNITK1Q[4]\ : XOR2 - port map(A => \un1_tag0[72]\, B => I1_1_3, Y => - \I1_RNITK1Q[4]\); - - \r.btag.LVL_RNI8022Q[0]\ : OR3C - port map(A => hm_1_1_3_m8_i_1, B => hm_1_1_3_N_14, C => - hm_1_1_3_N_12, Y => hm_1_1_3_N_9); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_0); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[20]\); - - \r.btag.PPN_RNIFV7MKO1[12]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[20]\, C => - pteout_m_i_11, Y => un2_wb_acc_iv_2_11); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_31); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[65]\); - - \r.btag.I1_RNIIE3N3[0]\ : NOR3C - port map(A => \I1_RNIEG0Q[1]\, B => \I1_RNIPO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(7), - Y => M_5); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[56]\); - - \r.btag.PPN_RNINN3BAS[10]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[18]\, Y => - pteout_m_i_9); - - \r.btag.I2_RNITTRT1[4]\ : NOR2 - port map(A => h_i22_5, B => h_i22_4, Y => h_l2_1_2); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNI9MG8AS[3]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[11]\, Y => - pteout_m_i_0_3); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[70]\); - - \r.btag.I1_RNIJQ0P1[5]\ : XA1 - port map(A => N_661, B => \un1_tag0[73]\, C => - \I1_RNITK1Q[4]\, Y => h_i13_NE_2); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[24]\); - - \r.btag.I2_RNIIL3K1[0]\ : XO1A - port map(A => I2_1(0), B => \un1_tag0[62]\, C => h_i22_1, Y - => h_l2_1_3_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.M_RNI3D5G5T\ : OR3B - port map(A => tlbcamo_needsync, B => un1_cam_hitaddr(56), C - => hm_1_1_3_N_9, Y => WBNEEDSYNC_m); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[40]\); - - \r.btag.LVL_RNI9T8D7[1]\ : OR2B - port map(A => hf_1_1_1_a1_2_2, B => h_l2_1_3, Y => - hf_1_1_1_a1_2_i); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[37]\); - - \r.btag.M_RNIFFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => tlbcamo_needsync); - - \r.btag.VALID_RNI6D8J1\ : NOR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_1_1_3_m8_i_0); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[15]\); - - \r.btag.CTX_RNI8S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_0, Y => h_c2_0_i); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_7); - - \r.btag.I1_RNIEG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNIEG0Q[1]\); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \LVL[0]\); - - \r.btag.VALID_RNICMVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.PPN_RNITF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[24]\, Y => - pteout_m_i_0_16); - - \r.btag.PPN_RNI6MG8AS[0]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[8]\, Y => - pteout_m_i_0_0); - - \r.btag.SU_RNI43MO1\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => hf_4_0, Y => - hf_4); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_30); - - \r.btag.PPN_RNINC1HKO1[7]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[15]\, C => - pteout_m_i_6, Y => un2_wb_acc_iv_2_6); - - \r.btag.I3_RNIBP773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_4_1, - Y => h_l3_1_4_3); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[12]\); - - \r.btag.PPN_RNIDC1HKO1[2]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[10]\, C => - pteout_m_i_1, Y => un2_wb_acc_iv_2_1); - - \r.btag.LVL_RNI58E57[0]\ : OR2A - port map(A => h_i13_NE, B => \LVL[0]\, Y => hm_1_1_3_N_14); - - \r.btag.VALID_RNI885H6\ : AOI1B - port map(A => hf_1_1_1_a0_3_0, B => h_l3_1_4_i_0, C => - hm_1_1_3_m8_i_0, Y => hm_1_1_3_m8_i_1); - - \r.btag.I2_RNIT82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.PPN_RNIJVIC9H3[18]\ : NOR2B - port map(A => \data_1_3_i_a3_2[30]\, B => - data_1_3_i_a3_3(30), Y => data_1_3_i_a3_5(30)); - - \r.btag.PPN_RNIRC1HKO1[9]\ : AOI1B - port map(A => un1_cam_hitaddr(56), B => \pteout[17]\, C => - pteout_m_i_8, Y => un2_wb_acc_iv_2_8); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => \pteout[16]\); - - \r.btag.I1_RNIF01Q[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => I1_1_6, Y => - \I1_RNIF01Q[7]\); - - \r.btag.M_RNO_0\ : OA1C - port map(A => trans_op, B => hm_1_1_3_N_9, C => - tlbcam_write_op_1_0(7), Y => M_1_sqmuxa); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[72]\); - - \r.btag.LVL_RNIS87P12[0]\ : AO1B - port map(A => hf_1_1, B => s2_flush_1, C => hm_1_1_3_N_9, Y - => hit); - - \r.btag.I2_RNI7O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.I3_RNIVB882[0]\ : NOR3C - port map(A => \I3_RNIS8291[2]\, B => \I3_RNI4N55[1]\, C => - \I3_RNIVB0Q[0]\, Y => h_l3_1_4_1); - - \r.btag.CTX_RNI2OI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_6, Y => h_c2_7_i); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.PPN_RNISB4BAS[15]\ : OR2B - port map(A => un1_cam_hitaddr(56), B => \pteout[23]\, Y => - pteout_m_i_0_15); - - \r.btag.LVL_RNILAQU49[1]\ : MX2C - port map(A => LVL_0(1), B => \LVL[1]\, S => - cam_hitaddr_18(1), Y => N_1498); - - \r.btag.I2_RNIL7065[0]\ : NOR2B - port map(A => h_l2_1_2, B => h_l2_1_3, Y => - hm_1_1_3_m8_i_o5_0); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_6 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - data_0_18 : in std_logic; - data_0_11 : in std_logic; - data_0_10 : in std_logic; - data_0_6 : in std_logic; - data_0_4 : in std_logic; - data_0_3 : in std_logic; - data_0_1 : in std_logic; - data_0_0 : in std_logic; - tlbcam_write_op_1_1_0 : in std_logic_vector(2 to 2); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_23 : in std_logic; - hrdata_16 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(2 to 2); - TYP_1_2 : in std_logic; - TYP_1_0_d0 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - LVL_RNIT69H911 : in std_logic_vector(0 to 0); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - data_21 : in std_logic; - data_20 : in std_logic; - data_19 : in std_logic; - data_18 : in std_logic; - data_17 : in std_logic; - data_16 : in std_logic; - data_13 : in std_logic; - data_12 : in std_logic; - data_11 : in std_logic; - data_9 : in std_logic; - data_6 : in std_logic; - data_3 : in std_logic; - data_7 : in std_logic; - data_0_d0 : in std_logic; - data_22 : in std_logic; - data_8 : in std_logic; - data_15 : in std_logic; - data_5 : in std_logic; - data_4 : in std_logic; - data_14 : in std_logic; - data_10 : in std_logic; - un1_m0_2_0 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_3 : out std_logic; - I3_1_i_0_0 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_2 : in std_logic_vector(2 to 2); - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - s2_entry_1 : in std_logic_vector(2 to 2); - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - tlbcam_write_op_1_0 : in std_logic_vector(2 to 2); - cam_hitaddr_18 : out std_logic_vector(1 to 1); - un2_wb_acc_iv_4_3 : in std_logic; - un2_wb_acc_iv_4_18 : in std_logic; - un2_wb_acc_iv_4_0 : in std_logic; - un2_wb_acc_iv_4_1 : in std_logic; - un2_wb_acc_iv_4_4 : in std_logic; - un2_wb_acc_iv_4_6 : in std_logic; - un2_wb_acc_iv_4_10 : in std_logic; - un2_wb_acc_iv_4_11 : in std_logic; - ctx : in std_logic_vector(7 downto 0); - I2_1 : in std_logic_vector(5 downto 0); - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - un2_wb_acc_iv_2_3 : in std_logic; - un2_wb_acc_iv_2_18 : in std_logic; - un2_wb_acc_iv_2_0 : in std_logic; - un2_wb_acc_iv_2_1 : in std_logic; - un2_wb_acc_iv_2_4 : in std_logic; - un2_wb_acc_iv_2_6 : in std_logic; - un2_wb_acc_iv_2_10 : in std_logic; - un2_wb_acc_iv_2_11 : in std_logic; - un2_wb_acc_iv_2_8 : in std_logic; - pteout_m_i_1_2 : in std_logic; - pteout_m_i_1_0 : in std_logic; - un2_wb_acc_iv_5 : out std_logic_vector(18 downto 16); - un2_wb_acc_iv_3_5 : out std_logic; - pteout_m_i_11 : in std_logic; - pteout_m_i_10 : in std_logic; - pteout_m_i_9 : in std_logic; - pteout_m_i_8 : in std_logic; - pteout_m_i_7 : in std_logic; - pteout_m_i_6 : in std_logic; - pteout_m_i_4 : in std_logic; - pteout_m_i_1_d0 : in std_logic; - pteout_m_i_0_d0 : in std_logic; - pteout_m_i_18 : in std_logic; - pteout_m_i_3 : in std_logic; - pteout_m_i_0_1_0 : in std_logic; - pteout_m_i_0_1_15 : in std_logic; - pteout_m_i_0_0_0 : in std_logic; - pteout_m_i_0_0_16 : in std_logic; - pteout_m_i_0_0_15 : in std_logic; - pteout_m_i_0_0_17 : in std_logic; - pteout_m_i_0_0_14 : in std_logic; - pteout_m_i_0_0_18 : in std_logic; - data_1_3_i_a3_3_3 : out std_logic; - data_1_3_i_a3_3_4 : out std_logic; - data_1_3_i_a3_3_1 : out std_logic; - data_1_3_i_a3_3_5 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(61 to 61); - data_1_3_i_a3_2 : in std_logic_vector(25 to 25); - data_1_3_i_a3_5_2 : out std_logic; - data_1_3_i_a3_5_0 : out std_logic; - pteout_m_i_0_10 : in std_logic; - pteout_m_i_0_8 : in std_logic; - pteout_m_i_0_6 : in std_logic; - pteout_m_i_0_0_d0 : in std_logic; - pteout_m_i_0_15 : in std_logic; - pteout_m_i_0_13 : in std_logic; - pteout_m_i_0_3 : in std_logic; - data_1_3_i_a3_0_2 : in std_logic_vector(15 to 15); - data_1_3_i_a3_0_5_0 : out std_logic; - data_1_3_i_a3_0_5_3 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_1138 : out std_logic; - cam_hit_all_5_sqmuxa_2 : out std_logic; - N_1151 : out std_logic; - N_1154 : out std_logic; - s2_flush : in std_logic; - N_1137 : out std_logic; - NEEDSYNC : out std_logic; - N_1167 : out std_logic; - un1_rst_i_0 : in std_logic; - N_696 : out std_logic; - N_695 : out std_logic; - N_2709_i_0 : in std_logic; - N_694 : out std_logic; - trans_op : in std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_1513 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - N_1166 : out std_logic; - N_1165 : out std_logic; - N_1164 : out std_logic; - N_1163 : out std_logic; - N_1162 : out std_logic; - N_1161 : out std_logic; - N_1160 : out std_logic; - N_1159 : out std_logic; - N_1158 : out std_logic; - N_1157 : out std_logic; - N_1156 : out std_logic; - N_1155 : out std_logic; - N_1153 : out std_logic; - N_1152 : out std_logic; - N_1150 : out std_logic; - N_1149 : out std_logic; - N_1148 : out std_logic; - N_1147 : out std_logic; - N_1146 : out std_logic; - N_1145 : out std_logic; - N_1144 : out std_logic; - N_1143 : out std_logic; - N_1142 : out std_logic; - N_1141 : out std_logic; - N_1140 : out std_logic; - N_1136 : out std_logic; - N_1135 : out std_logic; - N_1134 : out std_logic; - s2_flush_0 : in std_logic; - hit_1 : in std_logic; - hit_0 : in std_logic; - hit : in std_logic; - WBNEEDSYNC_m : in std_logic; - accexc_6_3 : out std_logic - ); - -end mmutlbcam_2_0_6; - -architecture DEF_ARCH of mmutlbcam_2_0_6 is - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \data_1_3_i_a3_0_3[15]\, \pteout_m_i_0_0[11]\, - \data_1_3_i_a3_3[25]\, \pteout[21]\, \pteout_m_i_0[26]\, - \pteout_m_i_0[22]\, \pteout_m_i_0[25]\, - \data_1_3_i_a3_3[27]\, \pteout[23]\, \pteout_m_i_0[24]\, - \data_1_3_i_a3_0_3[12]\, \pteout[8]\, WBNEEDSYNC_m_0, - \un2_wb_acc_iv_3[12]\, \pteout[12]\, - \un2_wb_acc_iv_3[27]\, \pteout[27]\, \un2_wb_acc_iv_3[9]\, - \pteout[9]\, \un2_wb_acc_iv_3[10]\, \pteout[10]\, - \un2_wb_acc_iv_3[13]\, \pteout[13]\, \pteout_m_i[14]\, - \un2_wb_acc_iv_3[15]\, \pteout[15]\, - \un2_wb_acc_iv_3[16]\, \pteout[16]\, - \un2_wb_acc_iv_3[17]\, \pteout[17]\, - \un2_wb_acc_iv_3[18]\, \pteout[18]\, - \un2_wb_acc_iv_3[19]\, \pteout[19]\, - \un2_wb_acc_iv_3[20]\, \pteout[20]\, tlbcamo_needsync, - hm_1_1, \cam_hitaddr_18_0[1]\, un18_hm, hf_1_1_1_a0_3_3, - un3_hf, hf_1_1_1_a0_3_1, h_l2_1_2, hf_1_1_1_a1_2_1, - hf_1_1_1_a1_2_0, \LVL[1]\, h_l3_1_4_3, \un1_tag0[61]\, - h_l3_1_4_1, \I3_RNIN8291[2]\, \I3_RNIVM55[1]\, - \I3_RNIQB0Q[0]\, h_i13_NE_4, \I1_RNI9G0Q[1]\, - \I1_RNIKO091[0]\, h_i13_NE_1, h_i13_NE_3, \un1_tag0[75]\, - \I1_RNI240Q[6]\, h_i13_NE_2, \un1_tag0[72]\, - \I1_RNIH5VU[5]\, \un1_tag0[70]\, \I1_RNIJ81Q[3]\, - h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, hf_4_0, - \un1_tag0[43]\, SU, h_c2_NE_5, h_c2_5_i, h_c2_4_i, - h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, - h_l2_1, h_l2_1_3, h_i13_NE, hm_1, h_l3_1_4_i, hm_4, - \un2_wb_acc[20]\, \un2_wb_acc[19]\, \un2_wb_acc[15]\, - \un2_wb_acc[13]\, \un2_wb_acc[10]\, \un2_wb_acc[9]\, - \un2_wb_acc[27]\, hf_4, hf_3, \un45_res[3]\, - \un2_wb_acc[12]\, h_i22_1, h_i22_0, \I3_RNIFS1Q[4]\, - \I3_RNI9G1Q[3]\, hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, hm_3, - N_5, \un1_tag0[67]\, h_i22_4, N_15, \un1_tag0[56]\, - \un1_tag0[59]\, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[74]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \pteout[0]\, \pteout[1]\, \pteout[6]\, - \pteout[7]\, \pteout[11]\, \pteout[14]\, \pteout[22]\, - \pteout[24]\, \pteout[25]\, \pteout[26]\, \pteout[28]\, - \pteout[29]\, \pteout[30]\, \pteout[31]\, \LVL[0]\, - \un1_tag0[62]\, \un1_tag0[63]\, \un1_tag0[65]\, - \un1_tag0[57]\, \un1_tag0[58]\, \un1_tag0[60]\, - \un1_tag0[68]\, \un1_tag0[73]\, M_2, M_5, h_su_cnt_1, - M_1_sqmuxa, N_1, N_3, VALID_RNO_13, N_6, hf_1_1, N_7, N_9, - N_8, \un1_tag0[66]\, \pteout[2]\, \pteout[3]\, - \pteout[4]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - pteout_4 <= \pteout[4]\; - pteout_3 <= \pteout[3]\; - pteout_2 <= \pteout[2]\; - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - - \r.btag.LVL_RNIBKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.LVL_RNI8P849[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.PPN_RNIIN8MKO1[15]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[23]\, C => - pteout_m_i_0_1_15, Y => \data_1_3_i_a3_3[27]\); - - \r.btag.CTX_RNINNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx(4), Y => h_c2_4_i); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[8]\); - - \r.btag.LVL_RNIGCRF[0]\ : NOR3A - port map(A => TYP_1_0(0), B => \LVL[1]\, C => \LVL[0]\, Y - => hf_1_1_1_a0_3_1); - - \r.btag.PPN_RNIUB5B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_1(2), Y => N_1153); - - \r.btag.I2_RNI2O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.PPN_RNI01V5[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry_1(2), Y => N_1145); - - \r.btag.I2_RNIO82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \LVL[1]\); - - \r.btag.PPN_RNIKDO5LO3[4]\ : MX2 - port map(A => data_7, B => \un2_wb_acc[12]\, S => - N_2709_i_0, Y => un1_m0_2_0); - - \r.btag.PPN_RNIDC7B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_2(2), Y => N_1159); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data_0_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[63]\); - - \r.btag.I1_RNI9Q0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIH5VU[5]\, Y => h_i13_NE_2); - - \r.btag.LVL_RNIGO5R05[0]\ : NOR3A - port map(A => hm_1_1, B => un18_hm, C => hit, Y => - \cam_hitaddr_18_0[1]\); - - \r.btag.I1_RNI9G0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNI9G0Q[1]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[19]\); - - \r.btag.PPN_RNIGC1HKO1[5]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[13]\, C => - pteout_m_i_4, Y => \un2_wb_acc_iv_3[13]\); - - \r.btag.LVL_RNIQE20A1[0]\ : MX2 - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.LVL_RNIK47RR[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.PPN_RNIJUEC9H3[10]\ : NOR3C - port map(A => pteout_m_i_9, B => pteout_m_i_0_10, C => - \un2_wb_acc_iv_3[18]\, Y => un2_wb_acc_iv_5(18)); - - \r.btag.CTX_RNITNI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx(7), Y => h_c2_7_i); - - \r.btag.PPN_RNI9S6B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_2(2), Y => N_1157); - - \r.btag.VALID_RNI1F4T71\ : MX2C - port map(A => N_7, B => N_9, S => data_0_d0, Y => hf_1_1); - - \r.btag.PPN_RNIFK7B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_2(2), Y => N_1160); - - \r.btag.M_RNI3F9DB1\ : OR3B - port map(A => trans_op, B => tlbcamo_needsync, C => hm_1_1, - Y => NEEDSYNC); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data_0_10, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(2), Y => N_15); - - \r.btag.PPN_RNILGT7BN2[5]\ : OR3C - port map(A => \un2_wb_acc_iv_3[13]\, B => un2_wb_acc_iv_2_4, - C => un2_wb_acc_iv_4_4, Y => \un2_wb_acc[13]\); - - \r.btag.LVL_RNILA4C2[1]\ : NOR2B - port map(A => hf_1_1_1_a1_2_0, B => un3_hf, Y => - hf_1_1_1_a1_2_1); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNIKV8MKO1[16]\ : NOR2B - port map(A => \pteout_m_i_0[24]\, B => pteout_m_i_0_0_16, Y - => data_1_3_i_a3_3_3); - - \r.btag.LVL_RNI0HOEC[0]\ : OR3B - port map(A => hf_1_1_1_a0_3_3, B => h_l2_1_3, C => - h_l3_1_4_i, Y => hf_1_1_1_a0_3_i); - - \r.btag.PPN_RNIB47B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_2(2), Y => N_1158); - - \r.btag.CTX_RNI8F5D[2]\ : XA1A - port map(A => ctx(2), B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.PPN_RNIAC1HKO1[2]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[10]\, C => - pteout_m_i_1_d0, Y => \un2_wb_acc_iv_3[10]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => SU); - - \r.btag.ACC_RNISNH5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_1(2), Y => N_1136); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data_9, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[62]\); - - \r.btag.I2_RNISJ0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[36]\); - - \r.btag.CTX_RNI8VAQ[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIJP229H3[9]\ : NOR2B - port map(A => un2_wb_acc_iv_2_8, B => \un2_wb_acc_iv_3[17]\, - Y => un2_wb_acc_iv_5(17)); - - \r.btag.PPN_RNIPJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[25]\, Y => - \pteout_m_i_0[25]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[10]\); - - \r.btag.LVL_RNI74UNB[0]\ : OR2B - port map(A => N_8, B => TYP_1_2, Y => N_9); - - \r.btag.PPN_RNI4MG8AS[3]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[11]\, Y => - \pteout_m_i_0_0[11]\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[57]\); - - \r.btag.PPN_RNICLIQLO3[12]\ : MX2 - port map(A => data_15, B => \un2_wb_acc[20]\, S => - LVL_RNIT69H911(0), Y => N_696); - - \r.btag.PPN_RNIE78MKO1[13]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[21]\, C => - pteout_m_i_0_13, Y => \data_1_3_i_a3_3[25]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNIOF9MKO1[18]\ : NOR2B - port map(A => \pteout_m_i_0[26]\, B => pteout_m_i_0_0_18, Y - => data_1_3_i_a3_3_5); - - \r.btag.PPN_RNITTUSBN2[19]\ : OR3C - port map(A => \un2_wb_acc_iv_3[27]\, B => - un2_wb_acc_iv_2_18, C => un2_wb_acc_iv_4_18, Y => - \un2_wb_acc[27]\); - - \r.btag.I3_RNIN8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIN8291[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.M_RNI4UQ6B1\ : NOR2A - port map(A => tlbcamo_needsync, B => hm_1_1, Y => - WBNEEDSYNC_m_0); - - \r.btag.I3_RNIVM55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNIVM55[1]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_0_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[21]\); - - \r.btag.PPN_RNITFT7BN2[2]\ : OR3C - port map(A => \un2_wb_acc_iv_3[10]\, B => un2_wb_acc_iv_2_1, - C => un2_wb_acc_iv_4_1, Y => \un2_wb_acc[10]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data_0_1, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => un1_rst_i_0, B => N_15, Y => VALID_RNO_13); - - \r.btag.PPN_RNI8C1HKO1[1]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[9]\, C => - pteout_m_i_0_d0, Y => \un2_wb_acc_iv_3[9]\); - - \r.btag.PPN_RNIM0O5LO3[1]\ : MX2 - port map(A => data_4, B => \un2_wb_acc[9]\, S => N_2709_i_0, - Y => N_694); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data_13, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[66]\); - - \r.btag.PPN_RNI3S5B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_2(2), Y => N_1163); - - \r.btag.CTX_RNI8UAQ[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.LVL_RNI1GI3E[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.PPN_RNIGF8MKO1[14]\ : NOR2B - port map(A => \pteout_m_i_0[22]\, B => pteout_m_i_0_0_14, Y - => data_1_3_i_a3_3_1); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data_0_11, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[68]\); - - \r.btag.CTX_RNIPNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx(5), Y => h_c2_5_i); - - \r.btag.ACC_RNI04D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_1138); - - \r.btag.PPN_RNIGI9QO51[11]\ : MX2 - port map(A => \un2_wb_acc[19]\, B => data_14, S => N_1513, - Y => un1_m0_2_7); - - \r.btag.PPN_RNIFO229H3[0]\ : NOR3C - port map(A => pteout_m_i_0_0_d0, B => pteout_m_i_0_0_0, C - => \data_1_3_i_a3_0_3[12]\, Y => data_1_3_i_a3_0_5_0); - - \r.btag.I2_RNIVE25R[5]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.PPN_RNIQN9MKO1[19]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[27]\, C => - pteout_m_i_18, Y => \un2_wb_acc_iv_3[27]\); - - \r.btag.PPN_RNIU0V5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_1(2), Y => N_1144); - - \r.btag.PPN_RNIOF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[24]\, Y => - \pteout_m_i_0[24]\); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_0_22, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[22]\); - - \r.btag.I3_RNIGB882[0]\ : NOR3C - port map(A => \I3_RNIN8291[2]\, B => \I3_RNIVM55[1]\, C => - \I3_RNIQB0Q[0]\, Y => h_l3_1_4_1); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[2]\); - - \r.btag.PPN_RNIDGT7BN2[4]\ : OR3C - port map(A => \un2_wb_acc_iv_3[12]\, B => un2_wb_acc_iv_2_3, - C => un2_wb_acc_iv_4_3, Y => \un2_wb_acc[12]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[29]\); - - \r.btag.PPN_RNI7C6B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_2(2), Y => N_1165); - - \r.btag.ET_RNI0LSA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_1(2), Y => N_1134); - - \r.btag.PPN_RNIFP229H3[8]\ : NOR3C - port map(A => pteout_m_i_7, B => pteout_m_i_0_8, C => - \un2_wb_acc_iv_3[16]\, Y => un2_wb_acc_iv_5(16)); - - \r.btag.I2_RNIAJ5AC[5]\ : OR3B - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE, Y => - h_l2_1); - - \r.btag.PPN_RNI546B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_2(2), Y => N_1164); - - \r.btag.M_RNIOK46\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_1(2), Y => N_1140); - - \r.btag.PPN_RNI3CH5O51[7]\ : MX2 - port map(A => \un2_wb_acc[15]\, B => data_10, S => N_1513, - Y => un1_m0_2_3); - - \r.btag.LVL_RNID29B4[0]\ : NOR3C - port map(A => un3_hf, B => hf_1_1_1_a0_3_1, C => h_l2_1_2, - Y => hf_1_1_1_a0_3_3); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data_11, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_13, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[4]\); - - \r.btag.I1_RNI152K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIJ81Q[3]\, Y => h_i13_NE_1); - - \r.btag.SU_RNIAOHT1\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => hf_4_0, Y => - hf_4); - - \r.btag.CTX_RNIOF5D[6]\ : XA1A - port map(A => ctx(6), B => \un1_tag0[41]\, C => h_c2_7_i, Y - => h_c2_NE_3); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[25]\); - - \r.btag.VALID_RNIAOHT1\ : NOR2B - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.I1_RNIC41K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI240Q[6]\, Y => h_i13_NE_3); - - \r.btag.PPN_RNIQN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[26]\, Y => - \pteout_m_i_0[26]\); - - \r.btag.PPN_RNICC1HKO1[3]\ : AND2 - port map(A => pteout_m_i_0_3, B => \pteout_m_i_0_0[11]\, Y - => \data_1_3_i_a3_0_3[15]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[3]\); - - \r.btag.M_RNIMS899R1\ : AOI1B - port map(A => WBNEEDSYNC_m_0, B => un1_cam_hitaddr(61), C - => WBNEEDSYNC_m, Y => accexc_6_3); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data_0_3, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.PPN_RNIQ0V5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_1(2), Y => N_1142); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[1]\); - - \r.btag.LVL_RNIIV1DK4[0]\ : NOR3A - port map(A => hm_1_1, B => un18_hm, C => hit_1, Y => - cam_hit_all_5_sqmuxa_2); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[11]\); - - \r.btag.LVL_RNITJ56[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_2(2), - Y => N_1166); - - \r.btag.SU_RNIQQR8\ : NOR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.I3_RNI9G1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNI9G1Q[3]\); - - \r.btag.I3_RNIF5BR4[3]\ : OR3C - port map(A => \I3_RNIFS1Q[4]\, B => \I3_RNI9G1Q[3]\, C => - h_l3_1_4_3, Y => h_l3_1_4_i); - - \r.btag.PPN_RNI61V5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_1(2), Y => N_1148); - - \r.btag.LVL_RNI1M8S49[0]\ : OR3A - port map(A => \cam_hitaddr_18_0[1]\, B => hit_0, C => hit_1, - Y => cam_hitaddr_18(1)); - - \r.btag.I3_RNINO773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_4_1, - Y => h_l3_1_4_3); - - \r.btag.PPN_RNITRMSBN2[11]\ : OR3C - port map(A => \un2_wb_acc_iv_3[19]\, B => - un2_wb_acc_iv_2_10, C => un2_wb_acc_iv_4_10, Y => - \un2_wb_acc[19]\); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data_12, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[65]\); - - \r.btag.I1_RNIUD3N3[0]\ : NOR3C - port map(A => \I1_RNI9G0Q[1]\, B => \I1_RNIKO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN_RNICV7MKO1[12]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[20]\, C => - pteout_m_i_11, Y => \un2_wb_acc_iv_3[20]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_0_27, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[27]\); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(2), - Y => M_5); - - \r.btag.ET_RNI2TSA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_1(2), Y => N_1135); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data_3, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[56]\); - - \r.btag.CTX_RNIFNI6[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx(0), Y => h_c2_0_i); - - \r.btag.I1_RNIJC547[4]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.PPN_RNI41V5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_1(2), Y => N_1147); - - \r.btag.I1_RNIKO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIKO091[0]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data_18, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNIEC1HKO1[4]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[12]\, C => - pteout_m_i_3, Y => \un2_wb_acc_iv_3[12]\); - - \r.btag.LVL_RNISF04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_1167); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data_17, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[70]\); - - \r.btag.PPN_RNI21V5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_1(2), Y => N_1146); - - \r.btag.I3_RNIQB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIQB0Q[0]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[24]\); - - \r.btag.VALID_RNI4F9S8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.VALID_RNI3S3581\ : NOR2B - port map(A => hf_1_1, B => s2_flush, Y => un18_hm); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data_16, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[40]\); - - \r.btag.VALID_RNIH24O1\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_4); - - \r.btag.I2_RNIGC1Q[0]\ : XNOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => h_i22_0); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[37]\); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_0_15, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[15]\); - - \r.btag.PPN_RNI5VPQLO3[19]\ : MX2 - port map(A => data_22, B => \un2_wb_acc[27]\, S => - LVL_RNIT69H911(0), Y => un1_m0_2_15); - - \r.btag.PPN_RNIA1V5[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_1(2), Y => N_1150); - - \r.btag.CTX_RNIHNI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx(1), Y => h_c2_1_i); - - \r.btag.PPN_RNIS0V5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_1(2), Y => N_1143); - - \r.btag.PPN_RNI446B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_1(2), Y => N_1156); - - \r.btag.VALID_RNIARKTI\ : NOR3 - port map(A => h_l3_1_4_i, B => hm_4, C => h_l2_1, Y => hm_1); - - \r.btag.I2_RNIJTRT1[5]\ : XA1B - port map(A => I2_1(5), B => \un1_tag0[67]\, C => h_i22_4, Y - => h_l2_1_2); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[14]\); - - \r.btag.PPN_RNIM74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[22]\, Y => - \pteout_m_i_0[22]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[7]\); - - \r.btag.I1_RNIH5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIH5VU[5]\); - - \r.btag.PPN_RNIMC1HKO1[8]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[16]\, C => - pteout_m_i_1_0, Y => \un2_wb_acc_iv_3[16]\); - - \r.btag.I2_RNI49483[0]\ : NOR3 - port map(A => h_i22_1, B => h_i22_0, C => h_l2_1_3_1, Y => - h_l2_1_3); - - \r.btag.PPN_RNIKC1HKO1[7]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[15]\, C => - pteout_m_i_6, Y => \un2_wb_acc_iv_3[15]\); - - \r.btag.PPN_RNI5HT7BN2[7]\ : OR3C - port map(A => \un2_wb_acc_iv_3[15]\, B => un2_wb_acc_iv_2_6, - C => un2_wb_acc_iv_4_6, Y => \un2_wb_acc[15]\); - - \r.btag.C_RNI4K46\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_1(2), Y => N_1141); - - \r.btag.VALID_RNI7MVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1_0_d0, Y => N_6); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \LVL[0]\); - - \r.btag.PPN_RNIVEGC9H3[13]\ : NOR2B - port map(A => data_1_3_i_a3_2(25), B => - \data_1_3_i_a3_3[25]\, Y => data_1_3_i_a3_5_0); - - \r.btag.PPN_RNIUHO5LO3[5]\ : MX2 - port map(A => data_8, B => \un2_wb_acc[13]\, S => - N_2709_i_0, Y => un1_m0_2_1); - - \r.btag.PPN_RNIAN7MKO1[11]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[19]\, C => - pteout_m_i_10, Y => \un2_wb_acc_iv_3[19]\); - - \r.btag.LVL_RNIO2CGB[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1_0_d0, Y => N_8); - - \r.btag.PPN_RNIS35B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_1(2), Y => N_1152); - - \r.btag.PPN_RNI7FHC9H3[15]\ : NOR3C - port map(A => pteout_m_i_0_15, B => pteout_m_i_0_0_15, C - => \data_1_3_i_a3_3[27]\, Y => data_1_3_i_a3_5_2); - - \r.btag.I1_RNIJ81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIJ81Q[3]\); - - \r.btag.PPN_RNIIC1HKO1[6]\ : NOR2B - port map(A => \pteout_m_i[14]\, B => pteout_m_i_0_6, Y => - un2_wb_acc_iv_3_5); - - \r.btag.PPN_RNI0019[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry(2), Y => N_1154); - - \r.btag.VALID_RNIL6KUR\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1_2, Y => N_7); - - \r.btag.PPN_RNIHS7B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_2(2), Y => N_1161); - - \r.btag.M_RNIAFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => tlbcamo_needsync); - - \r.btag.PPN_RNICDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_1151); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[13]\); - - \r.btag.I1_RNI240Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI240Q[6]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[30]\); - - \r.btag.I2_RNICH4I7[5]\ : OR3C - port map(A => h_l2_1_2, B => hf_1_1_1_a1_2_1, C => h_l2_1_3, - Y => hf_1_1_1_a1_2_i); - - \r.btag.PPN_RNI3LO5LO3[2]\ : MX2 - port map(A => data_5, B => \un2_wb_acc[10]\, S => - N_2709_i_0, Y => N_695); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data_0_4, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_0_12, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[12]\); - - \r.btag.PPN_RNIRO229H3[3]\ : AND2 - port map(A => \data_1_3_i_a3_0_3[15]\, B => - data_1_3_i_a3_0_2(15), Y => data_1_3_i_a3_0_5_3); - - \r.btag.SU_RNI9J3Q1\ : AO1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_0_26, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_0_23, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_0_16, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : OA1C - port map(A => trans_op, B => hm_1_1, C => - tlbcam_write_op_1_0(2), Y => M_1_sqmuxa); - - \r.btag.PPN_RNIOC1HKO1[9]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[17]\, C => - pteout_m_i_8, Y => \un2_wb_acc_iv_3[17]\); - - \r.btag.PPN_RNI8F7MKO1[10]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[18]\, C => - pteout_m_i_1_2, Y => \un2_wb_acc_iv_3[18]\); - - \r.btag.I3_RNIFS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIFS1Q[4]\); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[59]\); - - \r.btag.PPN_RNI81V5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_1(2), Y => N_1149); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data_19, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[72]\); - - \r.btag.CTX_RNILNI6[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx(3), Y => h_c2_3_i); - - \r.btag.PPN_RNI6C1HKO1[0]\ : AOI1B - port map(A => un1_cam_hitaddr(61), B => \pteout[8]\, C => - pteout_m_i_0_1_0, Y => \data_1_3_i_a3_0_3[12]\); - - \r.btag.I2_RNINOTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.PPN_RNI1K5B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_2(2), Y => N_1162); - - \r.btag.PPN_RNI5SNSBN2[12]\ : OR3C - port map(A => \un2_wb_acc_iv_3[20]\, B => - un2_wb_acc_iv_2_11, C => un2_wb_acc_iv_4_11, Y => - \un2_wb_acc[20]\); - - \r.btag.PPN_RNI2S5B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_1(2), Y => N_1155); - - \r.btag.PPN_RNILFT7BN2[1]\ : OR3C - port map(A => \un2_wb_acc_iv_3[9]\, B => un2_wb_acc_iv_2_0, - C => un2_wb_acc_iv_4_0, Y => \un2_wb_acc[9]\); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.LVL_RNIBIIE[1]\ : NOR2 - port map(A => \LVL[1]\, B => TYP_1_0(0), Y => - hf_1_1_1_a1_2_0); - - \r.btag.PPN_RNIM79MKO1[17]\ : NOR2B - port map(A => \pteout_m_i_0[25]\, B => pteout_m_i_0_0_17, Y - => data_1_3_i_a3_3_4); - - \r.btag.PPN_RNI7MG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(61), B => \pteout[14]\, Y => - \pteout_m_i[14]\); - - \r.btag.ACC_RNIU3D3[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry(2), Y => N_1137); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data_20, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(2), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_7 is - - port( hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_0 : in std_logic; - lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1 : in std_logic_vector(3 to 3); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_23 : in std_logic; - hrdata_16 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_1 : in std_logic; - hrdata_6 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(3 to 3); - LVL_1 : in std_logic_vector(1 to 1); - TYP_1 : in std_logic_vector(2 downto 0); - s2_entry : in std_logic_vector(2 to 2); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_4 : in std_logic_vector(2 to 2); - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - s2_entry_3 : in std_logic_vector(2 to 2); - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - I3_1_i : in std_logic_vector(3 to 3); - tlbcam_write_op_1_0 : in std_logic_vector(3 to 3); - LVL_0_d0 : out std_logic; - ctx_7 : in std_logic; - ctx_6 : in std_logic; - ctx_5 : in std_logic; - ctx_3 : in std_logic; - ctx_1 : in std_logic; - ctx_0_d0 : in std_logic; - ctx_2 : in std_logic; - ctx_0 : in std_logic_vector(4 to 4); - I2_1 : in std_logic_vector(5 downto 0); - I1_1_6 : in std_logic; - I1_1_3 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_5 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - TYP_1_0 : in std_logic_vector(0 to 0); - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_8 : in std_logic; - pteout_m_i_5 : in std_logic; - un2_wb_acc_iv_1_3 : out std_logic; - un2_wb_acc_iv_1_0 : out std_logic; - un2_wb_acc_iv_0 : in std_logic_vector(27 to 27); - un2_wb_acc_iv_4 : out std_logic_vector(27 to 27); - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_0_d0 : out std_logic; - pteout_m_i_0_19 : in std_logic; - pteout_m_i_0_16 : in std_logic; - pteout_m_i_0_14 : in std_logic; - pteout_m_i_0_13 : in std_logic; - data_1_3_i_a3_1_3 : out std_logic; - data_1_3_i_a3_1_1 : out std_logic; - data_1_3_i_a3_1_0 : out std_logic; - pteout_m_i_0_0_0 : in std_logic; - data_1_3_i_a3_0_1 : out std_logic_vector(15 to 15); - un1_cam_hitaddr : in std_logic_vector(60 to 60); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - cam_hit_all_5_sqmuxa_2 : in std_logic; - N_2551 : in std_logic; - N_1498 : in std_logic; - N_1506 : out std_logic; - N_1240 : out std_logic; - N_1253 : out std_logic; - trans_op : in std_logic; - s2_flush : in std_logic; - hit : out std_logic; - N_1239 : out std_logic; - N_1269 : out std_logic; - N_1249 : out std_logic; - un1_rst_i_0 : in std_logic; - un1_tlbcami_3 : out std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - N_1268 : out std_logic; - N_1267 : out std_logic; - N_1266 : out std_logic; - N_1265 : out std_logic; - N_1264 : out std_logic; - N_1263 : out std_logic; - N_1262 : out std_logic; - N_1261 : out std_logic; - N_1260 : out std_logic; - N_1259 : out std_logic; - N_1258 : out std_logic; - N_1257 : out std_logic; - N_1256 : out std_logic; - N_1255 : out std_logic; - N_1254 : out std_logic; - N_1252 : out std_logic; - N_1251 : out std_logic; - N_1250 : out std_logic; - N_1248 : out std_logic; - N_1247 : out std_logic; - N_1246 : out std_logic; - N_1245 : out std_logic; - N_1244 : out std_logic; - N_1243 : out std_logic; - N_1242 : out std_logic; - N_1238 : out std_logic; - N_1237 : out std_logic; - N_1236 : out std_logic; - s2_flush_0 : in std_logic; - N_661 : in std_logic; - tlbcamo_needsync : out std_logic; - WBNEEDSYNC_m : in std_logic; - accexc_6_2 : out std_logic - ); - -end mmutlbcam_2_0_7; - -architecture DEF_ARCH of mmutlbcam_2_0_7 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \pteout_m_i_0[11]\, \pteout[11]\, - \pteout_m_i_0_0[21]\, \pteout_m_i_0_0[22]\, - \pteout_m_i_0_0[24]\, WBNEEDSYNC_m_0, \pteout_m_i[27]\, - \pteout_m_i_0[14]\, \pteout_m_i_0[17]\, hm_1_1_3_N_9, - hm_1_1_3_m8_i_1, hf_1_1_1_a0_3_0, h_l3_1_4_i_0, - hm_1_1_3_m8_i_0, h_c2_NE_4, h_c2_NE_5, \un1_tag0[43]\, - hm_1_1_3_m8_i_o5_0, h_l2_1_2, h_l2_1_3, hf_1_1_1_a0_3_2, - un3_hf, hf_1_1_1_a0_3_0_0, hf_1_1_1_a1_2_1, \LVL[1]\, - h_l3_1_4_3, \un1_tag0[61]\, h_l3_1_4_1, \I3_RNIO8291[2]\, - \I3_RNI0N55[1]\, \I3_RNIRB0Q[0]\, h_i13_NE_4, - \I1_RNIAG0Q[1]\, \I1_RNILO091[0]\, h_i13_NE_1, h_i13_NE_3, - \un1_tag0[74]\, \I1_RNIB01Q[7]\, h_i13_NE_2, - \un1_tag0[73]\, \I1_RNIPK1Q[4]\, \un1_tag0[70]\, - \I1_RNIK81Q[3]\, h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, - h_l2_1_3_0, \un1_tag0[62]\, h_i22_1, hf_4_0, SU, h_c2_7_i, - h_c2_6_i, h_c2_NE_2, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[39]\, h_c2_5_i, \un1_tag0[37]\, h_c2_3_i, - h_i13_NE, hf_4, hf_3, \un45_res[3]\, \I3_RNIGS1Q[4]\, - \I3_RNIAG1Q[3]\, hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, - hm_1_1_3_N_14, hm_1_1_3_N_12, N_5, \LVL[0]\, h_i22_5, - h_i22_4, N_15, \un1_tag0[56]\, \un1_tag0[59]\, - \un1_tag0[69]\, \un1_tag0[71]\, \un1_tag0[72]\, - \un1_tag0[75]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[40]\, \un1_tag0[41]\, - \un1_tag0[42]\, \pteout[0]\, \pteout[1]\, \pteout[6]\, - \pteout[7]\, \pteout[8]\, \pteout[9]\, \pteout[10]\, - \pteout[12]\, \pteout[14]\, \pteout[15]\, \pteout[16]\, - \pteout[18]\, \pteout[19]\, \pteout[20]\, \pteout[21]\, - \pteout[22]\, \pteout[23]\, \pteout[24]\, \pteout[25]\, - \pteout[26]\, \pteout[27]\, \pteout[28]\, \pteout[29]\, - \pteout[30]\, \pteout[31]\, \pteout[13]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[66]\, \un1_tag0[67]\, - \un1_tag0[57]\, \un1_tag0[58]\, \un1_tag0[68]\, M_2, - \tlbcamo_needsync\, M_5, M_1_sqmuxa, VALID_RNO_14, N_9, - N_8, N_6, hf_1_1, N_7, \un1_tlbcami_3\, \pteout[17]\, - h_su_cnt_1, \un1_tag0[60]\, N_1494, \pteout[2]\, - \pteout[3]\, \pteout[4]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - pteout_4 <= \pteout[4]\; - pteout_3 <= \pteout[3]\; - pteout_2 <= \pteout[2]\; - LVL_0_d0 <= \LVL[0]\; - un1_tlbcami_3 <= \un1_tlbcami_3\; - tlbcamo_needsync <= \tlbcamo_needsync\; - - \r.btag.PPN_RNIEDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_1253); - - \r.btag.CTX_RNIGNI6[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_d0, Y => h_c2_0_i); - - \r.btag.PPN_RNIDC7B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_4(2), Y => N_1257); - - \r.btag.VALID_RNI8T3R1\ : NOR2B - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.I1_RNI2E3N3[0]\ : NOR3C - port map(A => \I1_RNIAG0Q[1]\, B => \I1_RNILO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_0_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[8]\); - - \r.btag.ACC_RNI24D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_1240); - - \r.btag.PPN_RNIPS8B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_4(2), Y => N_1263); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \LVL[1]\); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[39]\); - - \r.btag.I3_RNIRB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIRB0Q[0]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[63]\); - - \r.btag.CTX_RNIAF5D[2]\ : XA1A - port map(A => ctx_2, B => \un1_tag0[37]\, C => h_c2_3_i, Y - => h_c2_NE_1); - - \r.btag.LVL_RNILKR722[0]\ : AO1B - port map(A => hf_1_1, B => s2_flush, C => hm_1_1_3_N_9, Y - => hit); - - \r.btag.LVL_RNIDE2JB[0]\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[19]\); - - \r.btag.LVL_RNIICRF[0]\ : NOR2B - port map(A => hf_1_1_1_a0_3_0, B => TYP_1_0(0), Y => - hf_1_1_1_a0_3_0_0); - - \r.btag.PPN_RNIJN3BAS[10]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[18]\, Y => - pteout_m_i_9); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[67]\); - - \r.btag.CTX_RNIQNI6[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_5, Y => h_c2_5_i); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(3), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[41]\); - - \r.btag.PPN_RNIKV8MKO1[16]\ : NOR2B - port map(A => pteout_m_i_0_16, B => \pteout_m_i_0_0[24]\, Y - => data_1_3_i_a3_1_3); - - \r.btag.ET_RNIATTA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_3(2), Y => N_1237); - - \r.btag.I1_RNI352K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIK81Q[3]\, Y => h_i13_NE_1); - - \r.btag.PPN_RNIAMG8AS[8]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[16]\, Y => - pteout_m_i_7); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[36]\); - - \r.btag.VALID_RNI3HCR71\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.SU_RNI6OLN1\ : AO1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - \r.btag.LVL_RNIF7UAQ[0]\ : NOR2A - port map(A => trans_op, B => hm_1_1_3_N_9, Y => - \un1_tlbcami_3\); - - \r.btag.VALID_RNIFHOPR\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.I2_RNIAL3K1[0]\ : XO1A - port map(A => I2_1(0), B => \un1_tag0[62]\, C => h_i22_1, Y - => h_l2_1_3_0); - - \r.btag.PPN_RNI9MG8AS[7]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[15]\, Y => - pteout_m_i_6); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[10]\); - - \r.btag.CTX_RNIINI6[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_1, Y => h_c2_1_i); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[57]\); - - \r.btag.PPN_RNIE78MKO1[13]\ : NOR2B - port map(A => pteout_m_i_0_13, B => \pteout_m_i_0_0[21]\, Y - => data_1_3_i_a3_1_0); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNIRN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[26]\, Y => - pteout_m_i_0_18); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.LVL_RNIUJJFK4[1]\ : MX2C - port map(A => \LVL[1]\, B => LVL_1(1), S => - cam_hit_all_5_sqmuxa_2, Y => N_1494); - - \r.btag.M_RNI0L56\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_3(2), Y => N_1242); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_0_21, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[21]\); - - \r.btag.PPN_RNIKR3BAS[11]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[19]\, Y => - pteout_m_i_10); - - \r.btag.PPN_RNI7MG8AS[5]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[13]\, Y => - pteout_m_i_4); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNICMACC\ : OR3B - port map(A => hf_1_1_1_a0_3_2, B => h_l2_1_3, C => - h_l3_1_4_i_0, Y => hf_1_1_1_a0_3_i); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => un1_rst_i_0, B => N_15, Y => VALID_RNO_14); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[66]\); - - \r.btag.ET_RNI8LTA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_3(2), Y => N_1236); - - \r.btag.CTX_RNIUNI6[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_7, Y => h_c2_7_i); - - \r.btag.PPN_RNIGF8MKO1[14]\ : NOR2B - port map(A => pteout_m_i_0_14, B => \pteout_m_i_0_0[22]\, Y - => data_1_3_i_a3_1_1); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[68]\); - - \r.btag.C_RNICK56\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_3(2), Y => N_1243); - - \r.btag.PPN_RNI2MG8AS[0]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[8]\, Y => - pteout_m_i_0_0_d0); - - \r.btag.PPN_RNIJH06[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_4(2), Y => N_1251); - - \r.btag.PPN_RNISR4BAS[19]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[27]\, Y => - \pteout_m_i[27]\); - - \r.btag.M_RNIAGO2BQ1\ : AOI1B - port map(A => WBNEEDSYNC_m_0, B => un1_cam_hitaddr(60), C - => WBNEEDSYNC_m, Y => accexc_6_2); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_0_22, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[29]\); - - \r.btag.PPN_RNI9S6B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_4(2), Y => N_1255); - - \r.btag.LVL_RNIGUQ19[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.M_RNIBFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => - \tlbcamo_needsync\); - - \r.btag.LVL_RNIUF04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_1269); - - \r.btag.PPN_RNI4106[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_3(2), Y => N_1245); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[64]\); - - \r.btag.I1_RNIRC547[5]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_14, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.LVL_RNIUCGBB[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1(0), Y => N_8); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[4]\); - - \r.btag.I1_RNIAG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNIAG0Q[1]\); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[25]\); - - \r.btag.ACC_RNI4OI5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_3(2), Y => N_1238); - - \r.btag.PPN_RNIFK7B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_4(2), Y => N_1258); - - \r.btag.PPN_RNICC1HKO1[3]\ : AND2 - port map(A => \pteout_m_i_0[11]\, B => pteout_m_i_0_0_0, Y - => data_1_3_i_a3_0_1(15)); - - \r.btag.PPN_RNI6DQ3[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry(2), Y => N_1249); - - \r.btag.I1_RNIB01Q[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => I1_1_6, Y => - \I1_RNIB01Q[7]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[3]\); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[60]\); - - \r.btag.PPN_RNI5MG8AS[3]\ : NAND2 - port map(A => \pteout[11]\, B => un1_cam_hitaddr(60), Y => - \pteout_m_i_0[11]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[75]\); - - \r.btag.I3_RNIGS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIGS1Q[4]\); - - \r.btag.PPN_RNI7K6B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_4(2), Y => N_1254); - - \r.btag.LVL_RNIKFM92[1]\ : NOR3A - port map(A => un3_hf, B => TYP_1_0(0), C => \LVL[1]\, Y => - hf_1_1_1_a1_2_1); - - \r.btag.I3_RNIJB882[0]\ : NOR3C - port map(A => \I3_RNIO8291[2]\, B => \I3_RNI0N55[1]\, C => - \I3_RNIRB0Q[0]\, Y => h_l3_1_4_1); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[1]\); - - \r.btag.PPN_RNIM34BAS[13]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[21]\, Y => - \pteout_m_i_0_0[21]\); - - \r.btag.PPN_RNIHS7B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_4(2), Y => N_1259); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[11]\); - - \r.btag.I1_RNIK81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIK81Q[3]\); - - \r.btag.I3_RNIL5BR4[3]\ : OR3C - port map(A => \I3_RNIGS1Q[4]\, B => \I3_RNIAG1Q[3]\, C => - h_l3_1_4_3, Y => h_l3_1_4_i_0); - - \r.btag.I2_RNI89483[0]\ : NOR2 - port map(A => h_l2_1_3_1, B => h_l2_1_3_0, Y => h_l2_1_3); - - \r.btag.VALID_RNIE7ML1\ : NOR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_1_1_3_m8_i_0); - - \r.btag.LVL_RNIDKH2_0[0]\ : NOR2 - port map(A => \LVL[1]\, B => \LVL[0]\, Y => hf_1_1_1_a0_3_0); - - \r.btag.I1_RNIBQ0P1[5]\ : XA1 - port map(A => N_661, B => \un1_tag0[73]\, C => - \I1_RNIPK1Q[4]\, Y => h_i13_NE_2); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[42]\); - - \r.btag.PPN_RNILH06[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_4(2), Y => N_1252); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[65]\); - - \r.btag.I3_RNI0N55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNI0N55[1]\); - - \r.btag.PPN_RNIBMG8AS[9]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[17]\, Y => - \pteout_m_i_0[17]\); - - \r.btag.I3_RNIO8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIO8291[2]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_0_27, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[27]\); - - \r.btag.I2_RNIOOTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(3), - Y => M_5); - - \r.btag.I3_RNIAG1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNIAG1Q[3]\); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[56]\); - - \r.btag.I1_RNIE41K1[6]\ : XA1 - port map(A => I1_1_5, B => \un1_tag0[74]\, C => - \I1_RNIB01Q[7]\, Y => h_i13_NE_3); - - \r.btag.PPN_RNI4MG8AS[2]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[10]\, Y => - pteout_m_i_1); - - \r.btag.CTX_RNIMNI6[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_3, Y => h_c2_3_i); - - \r.btag.PPN_RNI9H06[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_4(2), Y => N_1246); - - \r.btag.VALID_RNI8MVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[24]\); - - \r.btag.PPN_RNIPF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[24]\, Y => - \pteout_m_i_0_0[24]\); - - \r.btag.LVL_RNI5K66[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_4(2), - Y => N_1268); - - \r.btag.PPN_RNIQJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[25]\, Y => - pteout_m_i_0_17); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I1_RNIPK1Q[4]\ : XOR2 - port map(A => \un1_tag0[72]\, B => I1_1_3, Y => - \I1_RNIPK1Q[4]\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[69]\); - - \r.btag.CTX_RNI04TN[4]\ : NOR3C - port map(A => h_c2_7_i, B => h_c2_6_i, C => h_c2_NE_2, Y - => h_c2_NE_5); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[40]\); - - \r.btag.PPN_RNIBS6B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_4(2), Y => N_1265); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[37]\); - - \r.btag.PPN_RNIJ48B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_4(2), Y => N_1260); - - \r.btag.VALID_RNIG1JJ6\ : AOI1B - port map(A => hf_1_1_1_a0_3_0, B => h_l3_1_4_i_0, C => - hm_1_1_3_m8_i_0, Y => hm_1_1_3_m8_i_1); - - \r.btag.LVL_RNIGMF4Q[0]\ : OR3C - port map(A => hm_1_1_3_m8_i_1, B => hm_1_1_3_N_14, C => - hm_1_1_3_N_12, Y => hm_1_1_3_N_9); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_0_15, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[15]\); - - \r.btag.I2_RNIUJ0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.PPN_RNI6EBG263[19]\ : NOR3C - port map(A => \pteout_m_i[27]\, B => pteout_m_i_0_19, C => - un2_wb_acc_iv_0(27), Y => un2_wb_acc_iv_4(27)); - - \r.btag.I2_RNILTRT1[4]\ : NOR2 - port map(A => h_i22_5, B => h_i22_4, Y => h_l2_1_2); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[14]\); - - \r.btag.LVL_RNIVDEBC[1]\ : AO1A - port map(A => h_i13_NE, B => hm_1_1_3_m8_i_o5_0, C => - \LVL[1]\, Y => hm_1_1_3_N_12); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[7]\); - - \r.btag.I3_RNIRO773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_4_1, - Y => h_l3_1_4_3); - - \r.btag.LVL_RNI17E57[0]\ : OR2A - port map(A => h_i13_NE, B => \LVL[0]\, Y => hm_1_1_3_N_14); - - \r.btag.SU_RNISQR8\ : OR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.PPN_RNIN74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[22]\, Y => - \pteout_m_i_0_0[22]\); - - \r.btag.I1_RNILO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNILO091[0]\); - - \r.btag.PPN_RNIB47B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_4(2), Y => N_1256); - - \r.btag.PPN_RNILC8B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_4(2), Y => N_1261); - - \r.btag.PPN_RNIDH06[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_4(2), Y => N_1248); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \LVL[0]\); - - \r.btag.PPN_RNILV3BAS[12]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[20]\, Y => - pteout_m_i_11); - - \r.btag.PPN_RNIIC1HKO1[6]\ : NOR2B - port map(A => pteout_m_i_5, B => \pteout_m_i_0[14]\, Y => - un2_wb_acc_iv_1_0); - - \r.btag.LVL_RNI0JFAGN[1]\ : MX2C - port map(A => N_1494, B => N_1498, S => N_2551, Y => N_1506); - - \r.btag.PPN_RNIOB4BAS[15]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[23]\, Y => - pteout_m_i_0_15); - - \r.btag.PPN_RNI3MG8AS[1]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[9]\, Y => - pteout_m_i_0_d0); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[13]\); - - \r.btag.PPN_RNID47B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_4(2), Y => N_1266); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[30]\); - - \r.btag.PPN_RNI2106[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_3(2), Y => N_1244); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[74]\); - - \r.btag.I2_RNIT6065[0]\ : NOR2B - port map(A => h_l2_1_2, B => h_l2_1_3, Y => - hm_1_1_3_m8_i_o5_0); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_0_12, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[12]\); - - \r.btag.LVL_RNIDKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_0_26, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_0_23, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[23]\); - - \r.btag.CTX_RNICUAQ[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN_RNIBH06[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry_4(2), Y => N_1247); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_0_16, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => \un1_tlbcami_3\, B => tlbcam_write_op_1_0(3), - Y => M_1_sqmuxa); - - \r.btag.PPN_RNIOC1HKO1[9]\ : NOR2B - port map(A => pteout_m_i_8, B => \pteout_m_i_0[17]\, Y => - un2_wb_acc_iv_1_3); - - \r.btag.I2_RNIP82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.LVL_RNIHMMF7[1]\ : OR3C - port map(A => h_l2_1_2, B => hf_1_1_1_a1_2_1, C => h_l2_1_3, - Y => hf_1_1_1_a1_2_i); - - \r.btag.CTX_RNI6KNA[4]\ : XA1A - port map(A => ctx_0(4), B => \un1_tag0[39]\, C => h_c2_5_i, - Y => h_c2_NE_2); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[59]\); - - \r.btag.PPN_RNIHH06[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_4(2), Y => N_1250); - - \r.btag.I2_RNI3O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[72]\); - - \r.btag.I2_RNIT4UU[5]\ : XNOR2 - port map(A => \un1_tag0[67]\, B => I2_1(5), Y => h_i22_5); - - \r.btag.PPN_RNINK8B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_4(2), Y => N_1262); - - \r.btag.PPN_RNI9K6B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_4(2), Y => N_1264); - - \r.btag.PPN_RNI8MG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[14]\, Y => - \pteout_m_i_0[14]\); - - \r.btag.LVL_RNIOP60R[1]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.M_RNIR58BR\ : NOR2A - port map(A => \tlbcamo_needsync\, B => hm_1_1_3_N_9, Y => - WBNEEDSYNC_m_0); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[73]\); - - \r.btag.ACC_RNI04D3[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry(2), Y => N_1239); - - \r.btag.PPN_RNI6MG8AS[4]\ : OR2B - port map(A => un1_cam_hitaddr(60), B => \pteout[12]\, Y => - pteout_m_i_3); - - \r.btag.SU_RNI8T3R1\ : OR3B - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => hf_4_0, Y => - hf_4); - - \r.btag.PPN_RNIFC7B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_4(2), Y => N_1267); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_0_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[18]\); - - \r.btag.CTX_RNISNI6[6]\ : XNOR2 - port map(A => \un1_tag0[41]\, B => ctx_6, Y => h_c2_6_i); - - \r.btag.VALID_RNIF7R84\ : NOR3C - port map(A => un3_hf, B => hf_1_1_1_a0_3_0_0, C => h_l2_1_2, - Y => hf_1_1_1_a0_3_2); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_2_0_1 is - - port( lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1_1 : in std_logic_vector(6 to 6); - data : in std_logic_vector(31 downto 12); - s2_ctx : in std_logic_vector(7 downto 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_7 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(6 to 6); - TYP_1 : in std_logic_vector(2 downto 0); - tlbcam_write_op_1_0 : in std_logic_vector(6 to 6); - I1_1_i_0_0 : in std_logic_vector(0 to 0); - I3_1_i_0_0 : in std_logic_vector(2 to 2); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_27 : out std_logic; - pteout_6 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - ctx : in std_logic_vector(4 to 4); - I3_1_i : in std_logic_vector(3 to 3); - un1_cam_hitaddr : in std_logic_vector(57 to 57); - ctx_0_7 : in std_logic; - ctx_0_5 : in std_logic; - ctx_0_3 : in std_logic; - ctx_0_1 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_2 : in std_logic; - ctx_0_6 : in std_logic; - I2_1 : in std_logic_vector(5 downto 0); - I1_1_5 : in std_logic; - I1_1_2 : in std_logic; - I1_1_0 : in std_logic; - I1_1_1 : in std_logic; - I1_1_3 : in std_logic; - I1_1_6 : in std_logic; - I3_1_4 : in std_logic; - I3_1_0 : in std_logic; - I3_1_5 : in std_logic; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - trans_op : in std_logic; - hit : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - un1_tlbcami_3 : out std_logic; - N_2483 : in std_logic; - M_1 : in std_logic; - N_661 : in std_logic; - N_3046 : in std_logic; - N_3043 : in std_logic; - N_61 : in std_logic; - WBNEEDSYNC_m : out std_logic; - tlbcamo_needsync : out std_logic - ); - -end mmutlbcam_2_0_1; - -architecture DEF_ARCH of mmutlbcam_2_0_1 is - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal WBNEEDSYNC_m_0, hm_1_1, hf_1_1_1_a0_3_3, un3_hf, - hf_1_1_1_a0_3_1, h_l2_1_2, hf_1_1_1_a1_2_1, \LVL[1]\, - h_l3_1_4_3, \un1_tag0[61]\, h_l3_1_4_1, \I3_RNIR8291[2]\, - \I3_RNI3N55[1]\, \I3_RNIUB0Q[0]\, h_i13_NE_4, - \I1_RNIDG0Q[1]\, \I1_RNIOO091[0]\, h_i13_NE_1, h_i13_NE_3, - \un1_tag0[75]\, \I1_RNI640Q[6]\, h_i13_NE_2, - \un1_tag0[72]\, \I1_RNIL5VU[5]\, \un1_tag0[70]\, - \I1_RNIN81Q[3]\, h_l2_1_3_1, \un1_tag0[64]\, h_i22_3, - hf_4_0, \un1_tag0[43]\, SU, h_c2_NE_5, h_c2_5_i, h_c2_4_i, - h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, h_c2_3_i, - h_l2_1, h_l2_1_3, h_i13_NE, hf_4, hm_1, h_l3_1_4_i, hm_4, - hf_3, \un45_res[3]\, h_i22_1, h_i22_0, \I3_RNIJS1Q[4]\, - \I3_RNIDG1Q[3]\, hf_1_1_1_a1_2_i, hf_1_1_1_a0_3_i, hm_3, - N_5, \un1_tag0[67]\, h_i22_4, \un1_tag0[56]\, - \un1_tag0[59]\, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[74]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[62]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[66]\, \un1_tag0[57]\, - \un1_tag0[58]\, \un1_tag0[60]\, \un1_tag0[68]\, - \un1_tag0[73]\, M_2, \tlbcamo_needsync\, \pteout[6]\, M_5, - h_su_cnt_1, M_1_sqmuxa, VALID_RNO_8, N_15, N_9, N_8, N_6, - hf_1_1, N_7, N_1, N_3, \LVL[0]\, \un1_tlbcami_3\, - \pteout[8]\, \pteout[9]\, \pteout[10]\, \pteout[11]\, - \pteout[12]\, \pteout[13]\, \pteout[14]\, \pteout[15]\, - \pteout[16]\, \pteout[17]\, \pteout[18]\, \pteout[19]\, - \pteout[20]\, \pteout[21]\, \pteout[22]\, \pteout[23]\, - \pteout[24]\, \pteout[25]\, \pteout[26]\, \pteout[27]\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - pteout_17 <= \pteout[17]\; - pteout_27 <= \pteout[27]\; - pteout_6 <= \pteout[6]\; - pteout_26 <= \pteout[26]\; - pteout_25 <= \pteout[25]\; - pteout_24 <= \pteout[24]\; - pteout_23 <= \pteout[23]\; - pteout_22 <= \pteout[22]\; - pteout_21 <= \pteout[21]\; - pteout_20 <= \pteout[20]\; - pteout_19 <= \pteout[19]\; - pteout_18 <= \pteout[18]\; - pteout_16 <= \pteout[16]\; - pteout_15 <= \pteout[15]\; - pteout_14 <= \pteout[14]\; - pteout_13 <= \pteout[13]\; - pteout_12 <= \pteout[12]\; - pteout_11 <= \pteout[11]\; - pteout_10 <= \pteout[10]\; - pteout_9 <= \pteout[9]\; - pteout_8 <= \pteout[8]\; - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - un1_tlbcami_3 <= \un1_tlbcami_3\; - tlbcamo_needsync <= \tlbcamo_needsync\; - - \r.btag.PPN_RNIOV3BAS[12]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[20]\, Y => - pteout_m_i_11); - - \r.btag.VALID_RNIUPGC1\ : NOR2A - port map(A => \un1_tag0[43]\, B => h_su_cnt_1, Y => un3_hf); - - \r.btag.PPN_RNIEMG8AS[9]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[17]\, Y => - pteout_m_i_8); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[8]\); - - \r.btag.CTX_RNIKD1J[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIVR4BAS[19]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[27]\, Y => - pteout_m_i_18); - - \r.btag.I3_RNI7P773[5]\ : XA1 - port map(A => I3_1_5, B => \un1_tag0[61]\, C => h_l3_1_4_1, - Y => h_l3_1_4_3); - - \r.btag.LVL_RNI8B5PQ[1]\ : MX2C - port map(A => hm_1, B => hm_3, S => \LVL[1]\, Y => N_1); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \LVL[1]\); - - \r.btag.LVL_RNIJKH2[0]\ : OR2B - port map(A => \LVL[1]\, B => \LVL[0]\, Y => \un45_res[3]\); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[63]\); - - \r.btag.I2_RNIS82Q[1]\ : XNOR2 - port map(A => \un1_tag0[63]\, B => I2_1(1), Y => h_i22_1); - - \r.btag.LVL_RNIUOVC81[0]\ : MX2 - port map(A => N_1, B => N_3, S => \LVL[0]\, Y => hm_1_1); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[19]\); - - \r.btag.CTX_RNIDS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.LVL_RNIRL03Q[1]\ : AOI1 - port map(A => hf_1_1_1_a1_2_i, B => hf_1_1_1_a0_3_i, C => - h_i13_NE, Y => N_5); - - \r.btag.LVL_RNIDJHID[1]\ : AO1A - port map(A => \LVL[1]\, B => h_l2_1, C => hm_4, Y => N_3); - - \r.btag.I1_RNI640Q[6]\ : XOR2 - port map(A => \un1_tag0[74]\, B => I1_1_5, Y => - \I1_RNI640Q[6]\); - - \r.btag.M_RNIC8OJ91\ : NOR2A - port map(A => \tlbcamo_needsync\, B => hm_1_1, Y => - WBNEEDSYNC_m_0); - - \r.btag.PPN_RNITJ4BAS[17]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[25]\, Y => - pteout_m_i_0_17); - - \r.btag.I1_RNIDG0Q[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => I1_1_0, Y => - \I1_RNIDG0Q[1]\); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNIBMVH\ : NOR2B - port map(A => \un1_tag0[43]\, B => TYP_1(0), Y => N_6); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(6), Y => N_15); - - \r.btag.I2_RNI2L5AC[5]\ : OR3B - port map(A => h_l2_1_3, B => h_l2_1_2, C => h_i13_NE, Y => - h_l2_1); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[41]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[36]\); - - \r.btag.I1_RNIEE3N3[0]\ : NOR3C - port map(A => \I1_RNIDG0Q[1]\, B => \I1_RNIOO091[0]\, C => - h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.CTX_RNILS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0_7, Y => h_c2_7_i); - - \r.btag.CTX_RNI9S44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_1, Y => h_c2_1_i); - - \r.btag.CTX_RNIRNI6[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx(4), Y => h_c2_4_i); - - \r.btag.I3_RNIDG1Q[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => I3_1_i(3), Y => - \I3_RNIDG1Q[3]\); - - \r.btag.I1_RNIHQ0P1[4]\ : XA1 - port map(A => I1_1_3, B => \un1_tag0[72]\, C => - \I1_RNIL5VU[5]\, Y => h_i13_NE_2); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[10]\); - - \r.btag.LVL_RNI4S7J8[0]\ : OR3B - port map(A => un3_hf, B => \un45_res[3]\, C => h_i13_NE, Y - => hf_3); - - \r.btag.PPN_RNI7MG8AS[2]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[10]\, Y => - pteout_m_i_1); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[57]\); - - \r.btag.SU_RNIPK291\ : AOI1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => SU, Y => - h_su_cnt_1); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.I2_RNI6O0Q[3]\ : XNOR2 - port map(A => \un1_tag0[65]\, B => I2_1(3), Y => h_i22_3); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_28); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[58]\); - - \r.btag.CTX_RNI8P98[6]\ : XA1A - port map(A => ctx_0_6, B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_8); - - \r.btag.I2_RNIRTRT1[5]\ : XA1B - port map(A => I2_1(5), B => \un1_tag0[67]\, C => h_i22_4, Y - => h_l2_1_2); - - \r.btag.I3_RNIR8291[2]\ : AX1E - port map(A => N_3043, B => I3_1_i_0_0(2), C => - \un1_tag0[58]\, Y => \I3_RNIR8291[2]\); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[66]\); - - \r.btag.VALID_RNI14371\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => hm_4); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[68]\); - - \r.btag.SU_RNI2RR8\ : OR2A - port map(A => \un1_tag0[43]\, B => SU, Y => hf_4_0); - - \r.btag.I3_RNI3N55[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_61, Y => - \I3_RNI3N55[1]\); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_2); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_29); - - \r.btag.PPN_RNIDMG8AS[8]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[16]\, Y => - pteout_m_i_7); - - \r.btag.CTX_RNIOO98[2]\ : XA1A - port map(A => ctx_0_2, B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[64]\); - - \r.btag.VALID_RNILDISQ\ : MX2C - port map(A => N_6, B => N_5, S => TYP_1(2), Y => N_7); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_8, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.PPN_RNISF4BAS[16]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[24]\, Y => - pteout_m_i_0_16); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_4); - - \r.btag.VALID_RNIJ70161\ : MX2C - port map(A => N_9, B => N_7, S => TYP_1(1), Y => hf_1_1); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[25]\); - - \r.btag.LVL_RNIDC3R1[1]\ : NOR3A - port map(A => un3_hf, B => TYP_1_0(0), C => \LVL[1]\, Y => - hf_1_1_1_a1_2_1); - - \r.btag.I3_RNIUB0Q[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => I3_1_0, Y => - \I3_RNIUB0Q[0]\); - - \r.btag.I3_RNISB882[0]\ : NOR3C - port map(A => \I3_RNIR8291[2]\, B => \I3_RNI3N55[1]\, C => - \I3_RNIUB0Q[0]\, Y => h_l3_1_4_1); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_3); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E0 - port map(D => M_5, CLK => lclk_c, E => M_1_sqmuxa, Q => - \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_1); - - \r.btag.SU_RNIUPGC1\ : OR3B - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => hf_4_0, Y => - hf_4); - - \r.btag.PPN_RNI6MG8AS[1]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[9]\, Y => - pteout_m_i_0_d0); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[11]\); - - \r.btag.I1_RNIOO091[0]\ : AX1E - port map(A => N_3046, B => I1_1_i_0_0(0), C => - \un1_tag0[68]\, Y => \I1_RNIOO091[0]\); - - \r.btag.LVL_RNIOCRF[0]\ : NOR3A - port map(A => TYP_1_0(0), B => \LVL[1]\, C => \LVL[0]\, Y - => hf_1_1_1_a0_3_1); - - \r.btag.LVL_RNI87AEA[0]\ : MX2C - port map(A => hf_4, B => hf_3, S => TYP_1(0), Y => N_8); - - \r.btag.I1_RNIK41K1[7]\ : XA1 - port map(A => I1_1_6, B => \un1_tag0[75]\, C => - \I1_RNI640Q[6]\, Y => h_i13_NE_3); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_0); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_31); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[65]\); - - \r.btag.I2_RNI4K0K1[2]\ : XO1A - port map(A => I2_1(2), B => \un1_tag0[64]\, C => h_i22_3, Y - => h_l2_1_3_1); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[27]\); - - \r.btag.CTX_RNI8HJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.VALID_RNIAVJCI\ : NOR3 - port map(A => h_l3_1_4_i, B => hm_4, C => h_l2_1, Y => hm_1); - - \r.btag.M_RNO\ : MX2C - port map(A => M_2, B => N_2483, S => tlbcam_write_op_1_0(6), - Y => M_5); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[56]\); - - \r.btag.M_RNIO53RJT\ : OR2B - port map(A => WBNEEDSYNC_m_0, B => un1_cam_hitaddr(57), Y - => WBNEEDSYNC_m); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[9]\); - - \r.btag.I1_RNIL5VU[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_661, Y => - \I1_RNIL5VU[5]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[70]\); - - \r.btag.LVL_RNIH48Q3[0]\ : NOR3C - port map(A => un3_hf, B => hf_1_1_1_a0_3_1, C => h_l2_1_2, - Y => hf_1_1_1_a0_3_3); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[24]\); - - \r.btag.I2_RNIKC1Q[0]\ : XNOR2 - port map(A => \un1_tag0[62]\, B => I2_1(0), Y => h_i22_0); - - \r.btag.PPN_RNINR3BAS[11]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[19]\, Y => - pteout_m_i_10); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.M_RNIEFO61\ : NOR2 - port map(A => \pteout[6]\, B => M_1, Y => - \tlbcamo_needsync\); - - \r.btag.PPN_RNI5MG8AS[0]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[8]\, Y => - pteout_m_i_0_0); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[37]\); - - \r.btag.I1_RNIJD547[4]\ : OR3C - port map(A => h_i13_NE_3, B => h_i13_NE_2, C => h_i13_NE_4, - Y => h_i13_NE); - - \r.btag.LVL_RNIN8SLA[0]\ : OR2B - port map(A => N_8, B => TYP_1(2), Y => N_9); - - \r.btag.PPN_RNIMN3BAS[10]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[18]\, Y => - pteout_m_i_9); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[15]\); - - \r.btag.PPN_RNIP34BAS[13]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[21]\, Y => - pteout_m_i_0_13); - - \r.btag.PPN_RNIAMG8AS[5]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[13]\, Y => - pteout_m_i_4); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_7); - - \r.btag.CTX_RNIHS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0_5, Y => h_c2_5_i); - - \r.btag.LVL_RNIT9EJ81[0]\ : NOR2A - port map(A => trans_op, B => hm_1_1, Y => \un1_tlbcami_3\); - - \r.btag.I1_RNI952K1[2]\ : XA1 - port map(A => I1_1_1, B => \un1_tag0[70]\, C => - \I1_RNIN81Q[3]\, Y => h_i13_NE_1); - - \r.btag.I2_RNIK9483[0]\ : NOR3 - port map(A => h_i22_1, B => h_i22_0, C => h_l2_1_3_1, Y => - h_l2_1_3); - - \r.btag.I3_RNIJS1Q[4]\ : XOR2 - port map(A => \un1_tag0[60]\, B => I3_1_4, Y => - \I3_RNIJS1Q[4]\); - - \r.btag.I1_RNIN81Q[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => I1_1_2, Y => - \I1_RNIN81Q[3]\); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \LVL[0]\); - - \r.btag.I3_RNI76BR4[3]\ : OR3C - port map(A => \I3_RNIJS1Q[4]\, B => \I3_RNIDG1Q[3]\, C => - h_l3_1_4_3, Y => h_l3_1_4_i); - - \r.btag.LVL_RNIJDVLE2[0]\ : AO1B - port map(A => hf_1_1, B => s2_flush, C => hm_1_1, Y => hit); - - \r.btag.PPN_RNI8MG8AS[3]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[11]\, Y => - pteout_m_i_0_3); - - \r.btag.LVL_RNICKNTB[0]\ : OR3B - port map(A => hf_1_1_1_a0_3_3, B => h_l2_1_3, C => - h_l3_1_4_i, Y => hf_1_1_1_a0_3_i); - - \r.btag.PPN_RNIUN4BAS[18]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[26]\, Y => - pteout_m_i_0_18); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_30); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[12]\); - - \r.btag.CTX_RNI7S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0_0, Y => h_c2_0_i); - - \r.btag.VALID_RNIKH8B8\ : NOR2 - port map(A => hm_4, B => h_i13_NE, Y => hm_3); - - \r.btag.PPN_RNIBMG8AS[6]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[14]\, Y => - pteout_m_i_5); - - \r.btag.PPN_RNICMG8AS[7]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[15]\, Y => - pteout_m_i_6); - - \r.btag.LVL_RNISJ317[1]\ : OR3C - port map(A => h_l2_1_2, B => hf_1_1_1_a1_2_1, C => h_l2_1_3, - Y => hf_1_1_1_a1_2_i); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => \pteout[16]\); - - \r.btag.M_RNO_0\ : NOR2 - port map(A => \un1_tlbcami_3\, B => tlbcam_write_op_1_0(6), - Y => M_1_sqmuxa); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[72]\); - - \r.btag.PPN_RNIQ74BAS[14]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[22]\, Y => - pteout_m_i_0_14); - - \r.btag.PPN_RNIRB4BAS[15]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[23]\, Y => - pteout_m_i_0_15); - - \r.btag.I2_RNIROTU[4]\ : XNOR2 - port map(A => \un1_tag0[66]\, B => I2_1(4), Y => h_i22_4); - - \r.btag.M_RNO_1\ : NOR2A - port map(A => M_1, B => \pteout[6]\, Y => M_2); - - \r.btag.PPN_RNI9MG8AS[4]\ : OR2B - port map(A => un1_cam_hitaddr(57), B => \pteout[12]\, Y => - pteout_m_i_3); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(6), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlb_10_8_2_1_0 is - - port( aaddr : inout std_logic_vector(31 downto 2) := (others => 'Z'); - twowner_1 : in std_logic_vector(0 to 0); - address : in std_logic_vector(31 downto 2); - data_1_3_i_a3_6_0 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_2 : out std_logic; - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - ctx_0 : in std_logic_vector(7 downto 0); - ctx : in std_logic_vector(7 downto 0); - fault_lvl : out std_logic_vector(1 downto 0); - lvl_i_1 : in std_logic_vector(1 downto 0); - data_2_0 : in std_logic; - lvl_i_1_0 : in std_logic_vector(1 to 1); - data_1_17 : in std_logic; - data_1_5 : out std_logic; - data_1_11 : in std_logic; - data_1_10 : in std_logic; - data_1_9 : in std_logic; - data_1_8 : in std_logic; - data_1_7 : in std_logic; - data_1_4 : in std_logic; - data_1_12 : in std_logic; - data_1_15 : in std_logic; - hrdata_2 : in std_logic; - hrdata_3 : in std_logic; - hrdata_4 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_8 : in std_logic; - hrdata_9 : in std_logic; - hrdata_10 : in std_logic; - hrdata_11 : in std_logic; - hrdata_12 : in std_logic; - hrdata_13 : in std_logic; - hrdata_14 : in std_logic; - hrdata_15 : in std_logic; - hrdata_16 : in std_logic; - hrdata_17 : in std_logic; - hrdata_18 : in std_logic; - hrdata_21 : in std_logic; - hrdata_22 : in std_logic; - hrdata_23 : in std_logic; - hrdata_24 : in std_logic; - hrdata_26 : in std_logic; - hrdata_27 : in std_logic; - hrdata_28 : in std_logic; - hrdata_29 : in std_logic; - hrdata_30 : in std_logic; - hrdata_31 : in std_logic; - hrdata_7 : in std_logic; - hrdata_5 : in std_logic; - hrdata_6 : in std_logic; - maddress : in std_logic_vector(31 downto 12); - twowner_0 : in std_logic_vector(0 to 0); - data_RNIKU1T4 : out std_logic_vector(16 to 16); - un1_m0_2_94 : out std_logic; - un1_m0_2_98 : out std_logic; - un1_m0_2_92 : out std_logic; - un1_m0_2_106 : out std_logic; - un1_m0_2_91 : out std_logic; - un1_m0_2_108 : out std_logic; - un1_m0_2_93 : out std_logic; - un1_m0_2_95 : out std_logic; - un1_m0_2_96 : out std_logic; - un1_m0_2_97 : out std_logic; - un1_m0_2_86 : in std_logic; - un1_m0_2_85 : in std_logic; - un1_m0_2_84 : in std_logic; - un1_m0_2_83 : in std_logic; - un1_m0_2_82 : in std_logic; - un1_m0_2_81 : in std_logic; - un1_m0_2_80 : in std_logic; - un1_m0_2_79 : in std_logic; - un1_m0_2_78 : in std_logic; - un1_m0_2_77 : in std_logic; - un1_m0_2_76 : in std_logic; - un1_m0_2_75 : in std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_10 : out std_logic; - un1_m0_2_9 : out std_logic; - un1_m0_2_0_d0 : out std_logic; - un1_m0_2_19 : out std_logic; - un1_m0_2_29 : out std_logic; - un1_m0_2_18 : out std_logic; - un1_m0_2_12 : out std_logic; - un1_m0_2_11 : out std_logic; - un1_m0_2_8 : out std_logic; - un1_m0_2_6 : out std_logic; - un1_m0_2_5 : out std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_33 : out std_logic; - un1_m0_2_31 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_23 : out std_logic; - data_0_18 : in std_logic; - data_0_14 : in std_logic; - data_0_22 : out std_logic; - data_0_21 : out std_logic; - data_0_20 : out std_logic; - data_0_19 : out std_logic; - data_0_23 : out std_logic; - data_0_16 : out std_logic; - data_0_28 : in std_logic; - data_0_30 : in std_logic; - data_0_26 : in std_logic; - data_0_25 : in std_logic; - data_0_15 : in std_logic; - data_0_12 : in std_logic; - data_0_31 : in std_logic; - data_0_27 : out std_logic; - data_0_29 : out std_logic; - data_0_13 : out std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_1 : in std_logic; - un1_m0_2_0 : in std_logic_vector(35 to 35); - ft_1_i_a2_0 : out std_logic_vector(0 to 0); - twowner_2_0_a2_0_0 : out std_logic_vector(0 to 0); - data_18 : out std_logic; - data_28 : out std_logic; - data_30 : out std_logic; - data_25 : out std_logic; - data_26 : out std_logic; - data_31 : out std_logic; - data_24 : out std_logic; - data_14 : out std_logic; - data_15 : out std_logic; - data_12 : out std_logic; - data_13 : in std_logic; - adata_20 : out std_logic; - adata_13 : out std_logic; - adata_17 : out std_logic; - adata_31 : out std_logic; - adata_30 : out std_logic; - adata_29 : out std_logic; - adata_28 : out std_logic; - adata_26 : out std_logic; - adata_24 : out std_logic; - adata_19 : out std_logic; - adata_18 : out std_logic; - adata_16 : out std_logic; - adata_15 : out std_logic; - adata_14 : out std_logic; - adata_11 : out std_logic; - adata_8 : out std_logic; - adata_7 : out std_logic; - adata_6 : out std_logic; - adata_1 : out std_logic; - adata_0 : out std_logic; - adata_9 : out std_logic; - adata_12 : out std_logic; - adata_2 : out std_logic; - adata_3 : out std_logic; - adata_4 : out std_logic; - adata_10 : out std_logic; - adata_27 : out std_logic; - adata_22 : out std_logic; - adata_21 : out std_logic; - adata_25 : out std_logic; - adata_23 : out std_logic; - N_709 : out std_logic; - mmutlb_10_8_2_1_0_VCC : in std_logic; - N_694 : out std_logic; - N_695 : out std_logic; - N_696 : out std_logic; - N_2702_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2709_i_0 : out std_logic; - fault_pri_2 : out std_logic; - fault_pro_0 : out std_logic; - accexc_6 : out std_logic; - un54_fault_pro_m : out std_logic; - N_2699_i_0 : out std_logic; - N_2703_i_0 : out std_logic; - G_80_0 : out std_logic; - N_2714 : out std_logic; - N_2717 : out std_logic; - N_2720 : out std_logic; - e : in std_logic; - M_m : out std_logic; - fault_pro67 : out std_logic; - N_2701 : out std_logic; - un1_rst_i_0 : out std_logic; - N_264 : in std_logic; - N_262 : in std_logic; - N_78 : in std_logic; - N_82_0 : in std_logic; - N_80 : in std_logic; - fault_pro_1_0 : in std_logic; - fault_mexc_3_2 : out std_logic; - flush_op : in std_logic; - N_264_0 : in std_logic; - fault_mexc_0 : out std_logic; - tlbactive : in std_logic; - tlbdis : in std_logic; - trans_op : in std_logic; - N_78_0 : in std_logic; - N_3160 : out std_logic; - N_2571 : in std_logic; - N_262_0 : in std_logic; - fault_pri_m : in std_logic; - fault_pri_1 : out std_logic; - fault_pri : out std_logic; - trans_op_0 : in std_logic; - N_2488 : out std_logic; - N_2482 : out std_logic; - N_2886 : out std_logic; - N_2887 : out std_logic; - N_190 : out std_logic; - N_192 : out std_logic; - N_236 : out std_logic; - N_293 : out std_logic; - N_317 : out std_logic; - N_351 : out std_logic; - N_353 : out std_logic; - N_415 : out std_logic; - N_417 : out std_logic; - N_419 : out std_logic; - N_421 : out std_logic; - fault_trans_i_2 : in std_logic; - fault_su : out std_logic; - fault_read : out std_logic; - inv_1_0_a2_0_a2_0 : in std_logic; - fault_trans : out std_logic; - fault_inv : out std_logic; - fault_mexc : in std_logic; - areq_ur_1_0_a2_0_0 : out std_logic; - N_2550 : out std_logic; - N_2532 : out std_logic; - rst : in std_logic; - read : in std_logic; - su : in std_logic; - fault_pro_1_iv_1 : out std_logic; - fault_pro_1_iv_2 : out std_logic; - fault_pro_i : out std_logic; - N_82 : in std_logic; - s1finished_0 : out std_logic; - walk_use_0 : out std_logic; - lclk_c : in std_logic; - N_86_i : out std_logic - ); - -end mmutlb_10_8_2_1_0; - -architecture DEF_ARCH of mmutlb_10_8_2_1_0 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_2 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - data_0_11 : in std_logic := 'U'; - data_0_9 : in std_logic := 'U'; - data_0_8 : in std_logic := 'U'; - data_0_7 : in std_logic := 'U'; - data_0_4 : in std_logic := 'U'; - data_0_3 : in std_logic := 'U'; - data_0_2 : in std_logic := 'U'; - data_0_0 : in std_logic := 'U'; - tlbcam_write_op_1_1 : in std_logic_vector(0 to 0) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(0 to 0) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_1 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_1 : in std_logic_vector(4 downto 2) := (others => 'U'); - s2_entry_0 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_17 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - cam_hitaddr_21 : in std_logic_vector(0 to 0) := (others => 'U'); - pteout_3 : in std_logic := 'U'; - pteout_2 : in std_logic := 'U'; - pteout_4 : in std_logic := 'U'; - un1_m0_2_4 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_0 : out std_logic; - un1_m0_2_15 : out std_logic; - un2_wb_acc_iv_2 : in std_logic_vector(14 to 14) := (others => 'U'); - un2_wb_acc_iv_3 : in std_logic_vector(14 to 14) := (others => 'U'); - un2_wb_acc_iv_5 : in std_logic_vector(18 downto 16) := (others => 'U'); - data_1_3_i_a3_0_5_3 : in std_logic := 'U'; - data_1_3_i_a3_0_5_0 : in std_logic := 'U'; - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - ctx_4 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_0_7 : in std_logic := 'U'; - ctx_0_3 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_6 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - pteout_m_i_1 : in std_logic_vector(15 to 15) := (others => 'U'); - un2_wb_acc_iv_0_12 : out std_logic; - un2_wb_acc_iv_1_8 : in std_logic := 'U'; - un2_wb_acc_iv_1_11 : in std_logic := 'U'; - un2_wb_acc_iv_1_10 : in std_logic := 'U'; - un2_wb_acc_iv_1_9 : in std_logic := 'U'; - un2_wb_acc_iv_1_7 : in std_logic := 'U'; - un2_wb_acc_iv_1_5 : in std_logic := 'U'; - un2_wb_acc_iv_1_4 : in std_logic := 'U'; - un2_wb_acc_iv_1_1 : in std_logic := 'U'; - un2_wb_acc_iv_1_0 : in std_logic := 'U'; - un2_wb_acc_iv_1_3 : in std_logic := 'U'; - pteout_m_i_11 : in std_logic := 'U'; - pteout_m_i_10 : in std_logic := 'U'; - pteout_m_i_9 : in std_logic := 'U'; - pteout_m_i_7 : in std_logic := 'U'; - pteout_m_i_6 : in std_logic := 'U'; - pteout_m_i_5 : in std_logic := 'U'; - pteout_m_i_4 : in std_logic := 'U'; - pteout_m_i_1_d0 : in std_logic := 'U'; - pteout_m_i_0_d0 : in std_logic := 'U'; - pteout_m_i_3 : in std_logic := 'U'; - un2_wb_acc_iv_4_11 : out std_logic; - un2_wb_acc_iv_4_10 : out std_logic; - un2_wb_acc_iv_4_6 : out std_logic; - un2_wb_acc_iv_4_4 : out std_logic; - un2_wb_acc_iv_4_1 : out std_logic; - un2_wb_acc_iv_4_0 : out std_logic; - un2_wb_acc_iv_4_3 : out std_logic; - data_1_3_i_a3_0_1_0 : in std_logic := 'U'; - data_1_3_i_a3_0_1_3 : in std_logic := 'U'; - data_1_3_i_a3_2 : in std_logic_vector(29 to 29) := (others => 'U'); - data_1_3_i_a3_3 : in std_logic_vector(29 to 29) := (others => 'U'); - pteout_m_i_0_1 : in std_logic_vector(26 to 26) := (others => 'U'); - pteout_m_i_0_9 : in std_logic := 'U'; - pteout_m_i_0_7 : in std_logic := 'U'; - pteout_m_i_0_19 : in std_logic := 'U'; - pteout_m_i_0_0_d0 : in std_logic := 'U'; - pteout_m_i_0_3 : in std_logic := 'U'; - pteout_m_i_0_16 : in std_logic := 'U'; - pteout_m_i_0_15 : in std_logic := 'U'; - pteout_m_i_0_17 : in std_logic := 'U'; - pteout_m_i_0_18 : in std_logic := 'U'; - pteout_m_i_0_0_14 : in std_logic := 'U'; - pteout_m_i_0_0_18 : in std_logic := 'U'; - pteout_m_i_0_0_13 : in std_logic := 'U'; - data_1_3_i_a3_5_5 : in std_logic := 'U'; - data_1_3_i_a3_5_3 : in std_logic := 'U'; - data_1_3_i_a3_5_2 : in std_logic := 'U'; - data_1_3_i_a3_5_1 : in std_logic := 'U'; - data_1_3_i_a3_5_0 : in std_logic := 'U'; - data_1_3_i_a3_1 : in std_logic_vector(29 downto 25) := (others => 'U'); - data_1_3_i_a3_6_2 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_0 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_2701 : out std_logic; - N_1104 : out std_logic; - N_1496 : in std_logic := 'U'; - N_1506 : in std_logic := 'U'; - N_1117 : out std_logic; - N_1481 : in std_logic := 'U'; - N_1120 : out std_logic; - N_1103 : out std_logic; - M_1 : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - un1_tlbcami_3 : out std_logic; - fault_pro67 : out std_logic; - read : in std_logic := 'U'; - M_m : out std_logic; - N_1133 : out std_logic; - N_1479 : in std_logic := 'U'; - s2_flush : in std_logic := 'U'; - e : in std_logic := 'U'; - rst : in std_logic := 'U'; - un1_rst_i_0 : out std_logic; - N_1505 : in std_logic := 'U'; - N_1482 : in std_logic := 'U'; - N_1495 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_1513 : out std_logic; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - N_2720 : out std_logic; - N_2717 : out std_logic; - N_2714 : out std_logic; - N_1132 : out std_logic; - N_1131 : out std_logic; - N_1130 : out std_logic; - N_1129 : out std_logic; - N_1128 : out std_logic; - N_1127 : out std_logic; - N_1126 : out std_logic; - N_1125 : out std_logic; - N_1124 : out std_logic; - N_1123 : out std_logic; - N_1122 : out std_logic; - N_1121 : out std_logic; - N_1119 : out std_logic; - N_1118 : out std_logic; - N_1116 : out std_logic; - N_1115 : out std_logic; - N_1114 : out std_logic; - N_1113 : out std_logic; - N_1112 : out std_logic; - N_1111 : out std_logic; - N_1110 : out std_logic; - N_1109 : out std_logic; - N_1108 : out std_logic; - N_1107 : out std_logic; - N_1106 : out std_logic; - N_1102 : out std_logic; - N_1101 : out std_logic; - N_1100 : out std_logic; - s2_flush_0 : in std_logic := 'U'; - G_80_0 : out std_logic; - N_1467 : in std_logic := 'U'; - N_1480 : in std_logic := 'U'; - N_1466 : in std_logic := 'U'; - cam_hit_all_5_sqmuxa_0_a2_0 : in std_logic := 'U'; - N_2551 : in std_logic := 'U'; - N_1468 : in std_logic := 'U'; - N_2703_i_0 : out std_logic; - N_2699_i_0 : out std_logic; - su : in std_logic := 'U'; - un54_fault_pro_m_0 : in std_logic := 'U'; - un54_fault_pro_m : out std_logic; - accexc_6 : in std_logic := 'U'; - fault_pro : out std_logic; - fault_pri : out std_logic; - N_2709_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2702_i_0 : out std_logic; - tlbcamo_needsync : out std_logic; - WBNEEDSYNC_m_0 : in std_logic := 'U'; - cam_hit_all_1 : out std_logic; - accexc_6_4 : out std_logic; - cam_hit_all_5_sqmuxa : in std_logic := 'U' - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_4 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(5 to 5) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(5 to 5) := (others => 'U'); - pteout_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - cam_hitaddr_18 : in std_logic_vector(1 to 1) := (others => 'U'); - LVL_0 : in std_logic_vector(0 to 0) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(5 to 5) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - cam_hitaddr_21_1 : out std_logic_vector(0 to 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_11 : in std_logic := 'U'; - pteout_m_i_10 : in std_logic := 'U'; - pteout_m_i_9 : in std_logic := 'U'; - pteout_m_i_7 : in std_logic := 'U'; - pteout_m_i_4 : in std_logic := 'U'; - pteout_m_i_1 : in std_logic := 'U'; - pteout_m_i_0_d0 : in std_logic := 'U'; - pteout_m_i_3 : in std_logic := 'U'; - un2_wb_acc_iv_1_11 : out std_logic; - un2_wb_acc_iv_1_10 : out std_logic; - un2_wb_acc_iv_1_9 : out std_logic; - un2_wb_acc_iv_1_7 : out std_logic; - un2_wb_acc_iv_1_4 : out std_logic; - un2_wb_acc_iv_1_1 : out std_logic; - un2_wb_acc_iv_1_0 : out std_logic; - un2_wb_acc_iv_1_3 : out std_logic; - data_1_3_i_a3_0_1 : out std_logic_vector(12 to 12); - data_1_3_i_a3_1_0 : out std_logic; - data_1_3_i_a3_1_2 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(58 to 58) := (others => 'U'); - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0_d0 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_24 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_6 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_13 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_12 : out std_logic; - pteout_8 : out std_logic; - pteout_23 : out std_logic; - pteout_25 : out std_logic; - pteout_11 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_0 : in std_logic := 'U'; - pteout_m_i_0_15 : in std_logic := 'U'; - pteout_m_i_0_17 : in std_logic := 'U'; - pteout_m_i_0_3 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_1471 : out std_logic; - NEEDSYNC : out std_logic; - N_1470 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_1469 : out std_logic; - N_1497 : out std_logic; - s2_flush_1 : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - WBNEEDSYNC_m : out std_logic; - N_61 : in std_logic := 'U'; - hit_1 : in std_logic := 'U'; - hit_0 : out std_logic; - hit : in std_logic := 'U'; - M_1 : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(4 to 4) := (others => 'U'); - un1_cam_hitaddr_1_0 : in std_logic := 'U'; - un1_cam_hitaddr_1_6 : in std_logic := 'U'; - un1_cam_hitaddr_1_5 : in std_logic := 'U'; - un1_cam_hitaddr_0 : out std_logic; - un1_cam_hitaddr_2 : out std_logic; - un1_cam_hitaddr_4 : out std_logic; - un1_cam_hitaddr_5 : out std_logic; - un1_cam_hitaddr_6 : out std_logic; - un1_cam_hitaddr_1_d0 : out std_logic; - pteout_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - cam_hitaddr_18 : in std_logic_vector(1 to 1) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 1) := (others => 'U'); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0_d0 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_27 : out std_logic; - pteout_6 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - ctx : in std_logic_vector(4 to 4) := (others => 'U'); - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - ctx_0_7 : in std_logic := 'U'; - ctx_0_5 : in std_logic := 'U'; - ctx_0_3 : in std_logic := 'U'; - ctx_0_1 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_2 : in std_logic := 'U'; - ctx_0_6 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - LVL : out std_logic_vector(1 downto 0); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_5 : in std_logic := 'U'; - un2_wb_acc_iv_2 : out std_logic_vector(14 to 14); - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_0_d0 : out std_logic; - pteout_m_i_0_17 : in std_logic := 'U'; - data_1_3_i_a3_2 : out std_logic_vector(29 to 29); - data_1_3_i_a3_3_2 : in std_logic := 'U'; - data_1_3_i_a3_3_0 : in std_logic := 'U'; - data_1_3_i_a3_5_2 : out std_logic; - data_1_3_i_a3_5_0 : out std_logic; - pteout_m_i_0_0_13 : in std_logic := 'U'; - pteout_m_i_0_0_11 : in std_logic := 'U'; - pteout_m_i_0_0_0 : in std_logic := 'U'; - data_1_3_i_a3_0_2 : out std_logic_vector(15 to 15); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_1496 : out std_logic; - N_1468 : out std_logic; - NEEDSYNC : out std_logic; - N_1467 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_1466 : out std_logic; - N_1495 : out std_logic; - trans_op : in std_logic := 'U'; - s2_flush_1 : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - hit_1 : in std_logic := 'U'; - hit_0 : in std_logic := 'U'; - N_2551 : out std_logic; - un1_cam_hitaddr_4_0 : in std_logic := 'U'; - WBNEEDSYNC_m : out std_logic; - hit : in std_logic := 'U' - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component mmutlbcam_2_0_5 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - tlbcam_write_op_1_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(1 to 1) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - un1_cam_hitaddr_1_0 : out std_logic; - un1_cam_hitaddr_1_5 : out std_logic; - un1_cam_hitaddr_1_6 : out std_logic; - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_1 : in std_logic_vector(4 downto 2) := (others => 'U'); - LVL_1 : in std_logic_vector(0 to 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_3 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_2 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_17 : in std_logic := 'U'; - pteout_0_4 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_4 : in std_logic := 'U'; - ctx_5 : in std_logic := 'U'; - ctx_7 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - cam_hitaddr_21_1 : in std_logic_vector(0 to 0) := (others => 'U'); - un1_cam_hitaddr : in std_logic_vector(62 to 62) := (others => 'U'); - ctx_0_0 : in std_logic := 'U'; - ctx_0_4 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I3_1_5 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - LVL_1_d0 : out std_logic; - cam_hitaddr_18 : in std_logic_vector(1 to 1) := (others => 'U'); - cam_hitaddr_21 : out std_logic_vector(0 to 0); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - s2_flush : in std_logic := 'U'; - N_1206 : out std_logic; - un1_rst_i_0 : in std_logic := 'U'; - N_1219 : out std_logic; - N_1482 : out std_logic; - N_1471 : in std_logic := 'U'; - N_1481 : out std_logic; - N_1205 : out std_logic; - N_1470 : in std_logic := 'U'; - N_1480 : out std_logic; - N_1235 : out std_logic; - N_1469 : in std_logic := 'U'; - N_1479 : out std_logic; - N_1497 : in std_logic := 'U'; - N_1505 : out std_logic; - NEEDSYNC : out std_logic; - s2_flush_1 : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_1234 : out std_logic; - N_1233 : out std_logic; - N_1232 : out std_logic; - N_1231 : out std_logic; - N_1230 : out std_logic; - N_1229 : out std_logic; - N_1228 : out std_logic; - N_1227 : out std_logic; - N_1226 : out std_logic; - N_1225 : out std_logic; - N_1224 : out std_logic; - N_1223 : out std_logic; - N_1222 : out std_logic; - N_1221 : out std_logic; - N_1220 : out std_logic; - N_1218 : out std_logic; - N_1217 : out std_logic; - N_1216 : out std_logic; - N_1215 : out std_logic; - N_1214 : out std_logic; - N_1213 : out std_logic; - N_1212 : out std_logic; - N_1211 : out std_logic; - N_1210 : out std_logic; - N_1209 : out std_logic; - N_1208 : out std_logic; - N_1204 : out std_logic; - N_1203 : out std_logic; - N_1202 : out std_logic; - N_2551 : in std_logic := 'U'; - cam_hit_all_5_sqmuxa : out std_logic; - cam_hit_all_5_sqmuxa_2 : in std_logic := 'U'; - cam_hit_all_5_sqmuxa_0_a2_0 : out std_logic; - accexc_6_3 : in std_logic := 'U'; - accexc_6_4 : in std_logic := 'U'; - accexc_6 : out std_logic; - N_661 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - un1_cam_hitaddr_4_0 : out std_logic; - M_1 : in std_logic := 'U'; - accexc_6_2 : in std_logic := 'U'; - WBNEEDSYNC_m : in std_logic := 'U' - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ0_1 - port( address : in std_logic_vector(31 downto 2) := (others => 'U'); - s2_entry : in std_logic_vector(2 downto 0) := (others => 'U'); - twowner_1 : in std_logic_vector(0 to 0) := (others => 'U'); - aaddr : inout std_logic_vector(31 downto 2); - dr1write_0_sqmuxa : in std_logic := 'U'; - syncramZ0_1_VCC : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_709 : out std_logic - ); - end component; - - component mmutlbcam_2_0_3 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(7 to 7) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(7 to 7) := (others => 'U'); - cam_hitaddr_18 : in std_logic_vector(1 to 1) := (others => 'U'); - LVL_0 : in std_logic_vector(1 to 1) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(7 to 7) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - ctx_0_3 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - ctx_6 : in std_logic := 'U'; - ctx_4 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_5 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_6 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_11 : in std_logic := 'U'; - pteout_m_i_10 : in std_logic := 'U'; - pteout_m_i_8 : in std_logic := 'U'; - pteout_m_i_6 : in std_logic := 'U'; - pteout_m_i_4 : in std_logic := 'U'; - pteout_m_i_1 : in std_logic := 'U'; - pteout_m_i_0_d0 : in std_logic := 'U'; - pteout_m_i_18 : in std_logic := 'U'; - pteout_m_i_3 : in std_logic := 'U'; - un2_wb_acc_iv_2_11 : out std_logic; - un2_wb_acc_iv_2_10 : out std_logic; - un2_wb_acc_iv_2_8 : out std_logic; - un2_wb_acc_iv_2_6 : out std_logic; - un2_wb_acc_iv_2_4 : out std_logic; - un2_wb_acc_iv_2_1 : out std_logic; - un2_wb_acc_iv_2_0 : out std_logic; - un2_wb_acc_iv_2_18 : out std_logic; - un2_wb_acc_iv_2_3 : out std_logic; - data_1_3_i_a3_3 : in std_logic_vector(30 to 30) := (others => 'U'); - data_1_3_i_a3_5 : out std_logic_vector(30 to 30); - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - pteout_m_i_0_18 : in std_logic := 'U'; - pteout_m_i_0_13 : in std_logic := 'U'; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_14 : out std_logic; - pteout_11 : out std_logic; - pteout_8 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_17 : out std_logic; - pteout_15 : out std_logic; - pteout_13 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_27 : out std_logic; - pteout_12 : out std_logic; - pteout_26 : out std_logic; - pteout_21 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(56 to 56) := (others => 'U'); - data_1_3_i_a3_2_0 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_1498 : out std_logic; - NEEDSYNC : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - s2_flush_1 : in std_logic := 'U'; - hit : out std_logic; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - WBNEEDSYNC_m : out std_logic; - N_661 : in std_logic := 'U' - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_6 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - data_0_18 : in std_logic := 'U'; - data_0_11 : in std_logic := 'U'; - data_0_10 : in std_logic := 'U'; - data_0_6 : in std_logic := 'U'; - data_0_4 : in std_logic := 'U'; - data_0_3 : in std_logic := 'U'; - data_0_1 : in std_logic := 'U'; - data_0_0 : in std_logic := 'U'; - tlbcam_write_op_1_1_0 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(2 to 2) := (others => 'U'); - TYP_1_2 : in std_logic := 'U'; - TYP_1_0_d0 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_RNIT69H911 : in std_logic_vector(0 to 0) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - data_21 : in std_logic := 'U'; - data_20 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - data_18 : in std_logic := 'U'; - data_17 : in std_logic := 'U'; - data_16 : in std_logic := 'U'; - data_13 : in std_logic := 'U'; - data_12 : in std_logic := 'U'; - data_11 : in std_logic := 'U'; - data_9 : in std_logic := 'U'; - data_6 : in std_logic := 'U'; - data_3 : in std_logic := 'U'; - data_7 : in std_logic := 'U'; - data_0_d0 : in std_logic := 'U'; - data_22 : in std_logic := 'U'; - data_8 : in std_logic := 'U'; - data_15 : in std_logic := 'U'; - data_5 : in std_logic := 'U'; - data_4 : in std_logic := 'U'; - data_14 : in std_logic := 'U'; - data_10 : in std_logic := 'U'; - un1_m0_2_0 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_3 : out std_logic; - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_2 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - s2_entry_1 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(2 to 2) := (others => 'U'); - cam_hitaddr_18 : out std_logic_vector(1 to 1); - un2_wb_acc_iv_4_3 : in std_logic := 'U'; - un2_wb_acc_iv_4_18 : in std_logic := 'U'; - un2_wb_acc_iv_4_0 : in std_logic := 'U'; - un2_wb_acc_iv_4_1 : in std_logic := 'U'; - un2_wb_acc_iv_4_4 : in std_logic := 'U'; - un2_wb_acc_iv_4_6 : in std_logic := 'U'; - un2_wb_acc_iv_4_10 : in std_logic := 'U'; - un2_wb_acc_iv_4_11 : in std_logic := 'U'; - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - un2_wb_acc_iv_2_3 : in std_logic := 'U'; - un2_wb_acc_iv_2_18 : in std_logic := 'U'; - un2_wb_acc_iv_2_0 : in std_logic := 'U'; - un2_wb_acc_iv_2_1 : in std_logic := 'U'; - un2_wb_acc_iv_2_4 : in std_logic := 'U'; - un2_wb_acc_iv_2_6 : in std_logic := 'U'; - un2_wb_acc_iv_2_10 : in std_logic := 'U'; - un2_wb_acc_iv_2_11 : in std_logic := 'U'; - un2_wb_acc_iv_2_8 : in std_logic := 'U'; - pteout_m_i_1_2 : in std_logic := 'U'; - pteout_m_i_1_0 : in std_logic := 'U'; - un2_wb_acc_iv_5 : out std_logic_vector(18 downto 16); - un2_wb_acc_iv_3_5 : out std_logic; - pteout_m_i_11 : in std_logic := 'U'; - pteout_m_i_10 : in std_logic := 'U'; - pteout_m_i_9 : in std_logic := 'U'; - pteout_m_i_8 : in std_logic := 'U'; - pteout_m_i_7 : in std_logic := 'U'; - pteout_m_i_6 : in std_logic := 'U'; - pteout_m_i_4 : in std_logic := 'U'; - pteout_m_i_1_d0 : in std_logic := 'U'; - pteout_m_i_0_d0 : in std_logic := 'U'; - pteout_m_i_18 : in std_logic := 'U'; - pteout_m_i_3 : in std_logic := 'U'; - pteout_m_i_0_1_0 : in std_logic := 'U'; - pteout_m_i_0_1_15 : in std_logic := 'U'; - pteout_m_i_0_0_0 : in std_logic := 'U'; - pteout_m_i_0_0_16 : in std_logic := 'U'; - pteout_m_i_0_0_15 : in std_logic := 'U'; - pteout_m_i_0_0_17 : in std_logic := 'U'; - pteout_m_i_0_0_14 : in std_logic := 'U'; - pteout_m_i_0_0_18 : in std_logic := 'U'; - data_1_3_i_a3_3_3 : out std_logic; - data_1_3_i_a3_3_4 : out std_logic; - data_1_3_i_a3_3_1 : out std_logic; - data_1_3_i_a3_3_5 : out std_logic; - un1_cam_hitaddr : in std_logic_vector(61 to 61) := (others => 'U'); - data_1_3_i_a3_2 : in std_logic_vector(25 to 25) := (others => 'U'); - data_1_3_i_a3_5_2 : out std_logic; - data_1_3_i_a3_5_0 : out std_logic; - pteout_m_i_0_10 : in std_logic := 'U'; - pteout_m_i_0_8 : in std_logic := 'U'; - pteout_m_i_0_6 : in std_logic := 'U'; - pteout_m_i_0_0_d0 : in std_logic := 'U'; - pteout_m_i_0_15 : in std_logic := 'U'; - pteout_m_i_0_13 : in std_logic := 'U'; - pteout_m_i_0_3 : in std_logic := 'U'; - data_1_3_i_a3_0_2 : in std_logic_vector(15 to 15) := (others => 'U'); - data_1_3_i_a3_0_5_0 : out std_logic; - data_1_3_i_a3_0_5_3 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_1138 : out std_logic; - cam_hit_all_5_sqmuxa_2 : out std_logic; - N_1151 : out std_logic; - N_1154 : out std_logic; - s2_flush : in std_logic := 'U'; - N_1137 : out std_logic; - NEEDSYNC : out std_logic; - N_1167 : out std_logic; - un1_rst_i_0 : in std_logic := 'U'; - N_696 : out std_logic; - N_695 : out std_logic; - N_2709_i_0 : in std_logic := 'U'; - N_694 : out std_logic; - trans_op : in std_logic := 'U'; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_1513 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - N_1166 : out std_logic; - N_1165 : out std_logic; - N_1164 : out std_logic; - N_1163 : out std_logic; - N_1162 : out std_logic; - N_1161 : out std_logic; - N_1160 : out std_logic; - N_1159 : out std_logic; - N_1158 : out std_logic; - N_1157 : out std_logic; - N_1156 : out std_logic; - N_1155 : out std_logic; - N_1153 : out std_logic; - N_1152 : out std_logic; - N_1150 : out std_logic; - N_1149 : out std_logic; - N_1148 : out std_logic; - N_1147 : out std_logic; - N_1146 : out std_logic; - N_1145 : out std_logic; - N_1144 : out std_logic; - N_1143 : out std_logic; - N_1142 : out std_logic; - N_1141 : out std_logic; - N_1140 : out std_logic; - N_1136 : out std_logic; - N_1135 : out std_logic; - N_1134 : out std_logic; - s2_flush_0 : in std_logic := 'U'; - hit_1 : in std_logic := 'U'; - hit_0 : in std_logic := 'U'; - hit : in std_logic := 'U'; - WBNEEDSYNC_m : in std_logic := 'U'; - accexc_6_3 : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_7 - port( hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(3 to 3) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(3 to 3) := (others => 'U'); - LVL_1 : in std_logic_vector(1 to 1) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_4 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - s2_entry_3 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(3 to 3) := (others => 'U'); - LVL_0_d0 : out std_logic; - ctx_7 : in std_logic := 'U'; - ctx_6 : in std_logic := 'U'; - ctx_5 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - ctx_2 : in std_logic := 'U'; - ctx_0 : in std_logic_vector(4 to 4) := (others => 'U'); - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_6 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_5 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_m_i_8 : in std_logic := 'U'; - pteout_m_i_5 : in std_logic := 'U'; - un2_wb_acc_iv_1_3 : out std_logic; - un2_wb_acc_iv_1_0 : out std_logic; - un2_wb_acc_iv_0 : in std_logic_vector(27 to 27) := (others => 'U'); - un2_wb_acc_iv_4 : out std_logic_vector(27 to 27); - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_0_d0 : out std_logic; - pteout_m_i_0_19 : in std_logic := 'U'; - pteout_m_i_0_16 : in std_logic := 'U'; - pteout_m_i_0_14 : in std_logic := 'U'; - pteout_m_i_0_13 : in std_logic := 'U'; - data_1_3_i_a3_1_3 : out std_logic; - data_1_3_i_a3_1_1 : out std_logic; - data_1_3_i_a3_1_0 : out std_logic; - pteout_m_i_0_0_0 : in std_logic := 'U'; - data_1_3_i_a3_0_1 : out std_logic_vector(15 to 15); - un1_cam_hitaddr : in std_logic_vector(60 to 60) := (others => 'U'); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - cam_hit_all_5_sqmuxa_2 : in std_logic := 'U'; - N_2551 : in std_logic := 'U'; - N_1498 : in std_logic := 'U'; - N_1506 : out std_logic; - N_1240 : out std_logic; - N_1253 : out std_logic; - trans_op : in std_logic := 'U'; - s2_flush : in std_logic := 'U'; - hit : out std_logic; - N_1239 : out std_logic; - N_1269 : out std_logic; - N_1249 : out std_logic; - un1_rst_i_0 : in std_logic := 'U'; - un1_tlbcami_3 : out std_logic; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - N_1268 : out std_logic; - N_1267 : out std_logic; - N_1266 : out std_logic; - N_1265 : out std_logic; - N_1264 : out std_logic; - N_1263 : out std_logic; - N_1262 : out std_logic; - N_1261 : out std_logic; - N_1260 : out std_logic; - N_1259 : out std_logic; - N_1258 : out std_logic; - N_1257 : out std_logic; - N_1256 : out std_logic; - N_1255 : out std_logic; - N_1254 : out std_logic; - N_1252 : out std_logic; - N_1251 : out std_logic; - N_1250 : out std_logic; - N_1248 : out std_logic; - N_1247 : out std_logic; - N_1246 : out std_logic; - N_1245 : out std_logic; - N_1244 : out std_logic; - N_1243 : out std_logic; - N_1242 : out std_logic; - N_1238 : out std_logic; - N_1237 : out std_logic; - N_1236 : out std_logic; - s2_flush_0 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - tlbcamo_needsync : out std_logic; - WBNEEDSYNC_m : in std_logic := 'U'; - accexc_6_2 : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_2_0_1 - port( lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(6 to 6) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(6 to 6) := (others => 'U'); - TYP_1 : in std_logic_vector(2 downto 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(6 to 6) := (others => 'U'); - I1_1_i_0_0 : in std_logic_vector(0 to 0) := (others => 'U'); - I3_1_i_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_m_i_8 : out std_logic; - pteout_m_i_18 : out std_logic; - pteout_m_i_11 : out std_logic; - pteout_m_i_10 : out std_logic; - pteout_m_i_9 : out std_logic; - pteout_m_i_7 : out std_logic; - pteout_m_i_6 : out std_logic; - pteout_m_i_5 : out std_logic; - pteout_m_i_4 : out std_logic; - pteout_m_i_3 : out std_logic; - pteout_m_i_1 : out std_logic; - pteout_m_i_0_d0 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_7 : out std_logic; - pteout_17 : out std_logic; - pteout_27 : out std_logic; - pteout_6 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_m_i_0_18 : out std_logic; - pteout_m_i_0_17 : out std_logic; - pteout_m_i_0_16 : out std_logic; - pteout_m_i_0_15 : out std_logic; - pteout_m_i_0_14 : out std_logic; - pteout_m_i_0_13 : out std_logic; - pteout_m_i_0_3 : out std_logic; - pteout_m_i_0_0 : out std_logic; - ctx : in std_logic_vector(4 to 4) := (others => 'U'); - I3_1_i : in std_logic_vector(3 to 3) := (others => 'U'); - un1_cam_hitaddr : in std_logic_vector(57 to 57) := (others => 'U'); - ctx_0_7 : in std_logic := 'U'; - ctx_0_5 : in std_logic := 'U'; - ctx_0_3 : in std_logic := 'U'; - ctx_0_1 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_2 : in std_logic := 'U'; - ctx_0_6 : in std_logic := 'U'; - I2_1 : in std_logic_vector(5 downto 0) := (others => 'U'); - I1_1_5 : in std_logic := 'U'; - I1_1_2 : in std_logic := 'U'; - I1_1_0 : in std_logic := 'U'; - I1_1_1 : in std_logic := 'U'; - I1_1_3 : in std_logic := 'U'; - I1_1_6 : in std_logic := 'U'; - I3_1_4 : in std_logic := 'U'; - I3_1_0 : in std_logic := 'U'; - I3_1_5 : in std_logic := 'U'; - LVL : out std_logic_vector(1 downto 0); - TYP_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - hit : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - un1_tlbcami_3 : out std_logic; - N_2483 : in std_logic := 'U'; - M_1 : in std_logic := 'U'; - N_661 : in std_logic := 'U'; - N_3046 : in std_logic := 'U'; - N_3043 : in std_logic := 'U'; - N_61 : in std_logic := 'U'; - WBNEEDSYNC_m : out std_logic; - tlbcamo_needsync : out std_logic - ); - end component; - - signal dr1write_0_sqmuxa_0, cache_0_sqmuxa_0, s2_flush_1, - s2_flush_1_0, un1_rst_3, s2_flush_0, \s2_entry_1[0]\, - \s2_entry_1_0[0]\, N_53, \s2_entry_0[0]\, \s2_entry_1[1]\, - \s2_entry_1_0[1]\, \s2_entry_0[1]\, \s2_entry_4[2]\, - \s2_entry_1[2]\, \s2_entry_3[2]\, \s2_entry_2[2]\, - \s2_entry_1_0[2]\, \s2_entry_0[2]\, walk_use_1, - sync_isw_RNII96B91, s2_tlbstate_3, s1finished_1, N_2530, - N_93, \tlbcam_write_op_1_1_0[4]\, - \tlbcam_write_op_1_1[4]\, \tlbcam_write_op_1_0[4]\, - \tlbcam_write_op_1_1[6]\, \tlbcam_write_op_1_1[7]\, - \tlbcam_write_op_1_0[6]\, \tlbcam_write_op_1_1[0]\, - \tlbcam_write_op_1_1[1]\, \tlbcam_write_op_1_0[0]\, - \tlbcam_write_op_1_1_0[7]\, \tlbcam_write_op_1_0[7]\, - \tlbcam_write_op_1_1[5]\, \tlbcam_write_op_1_0[5]\, - \tlbcam_write_op_1_1_0[1]\, \tlbcam_write_op_1_0[1]\, - \tlbcam_write_op_1_1_0[2]\, \tlbcam_write_op_1_1[2]\, - \tlbcam_write_op_1_0[2]\, dr1write_0_sqmuxa, - \tlbcam_write_op_1_1[3]\, \tlbcam_write_op_1_0[3]\, - \TYP_1_0[0]\, \data[8]\, \s2_tlbstate[0]\, - \s2_tlbstate[1]\, N_2957, N_3060, N_2959, \walk_use_0\, - \data[27]\, N_2977, N_2978, \data[29]\, N_3040, N_3073, - N_61, \I3_1_i_0_0[1]\, N_3041, N_3039, - \data_1_i_m2_i_0[27]\, \data_1_i_0[29]\, - un54_fault_pro_m_0, sync_isw_1_i_0_0, - \s2_tlbstate_ns_0_0_0[0]\, N_166, N_2547, N_2538, - sync_isw, \s2_tlbstate_ns_0_0_0[1]\, N_2552, - cache_0_sqmuxa_0_a2_0, \s2_tlbstate_ns_0_0_a2_0_0[0]\, - N_95, s2_needsync_4, un1_tlbcami_3, tlbcamo_needsync, - NEEDSYNC, s2_needsync_3, NEEDSYNC_0, s2_needsync_0, - s2_needsync_2, un1_tlbcami_3_0, tlbcamo_needsync_0, - NEEDSYNC_1, un1_tlbcami_3_1, tlbcamo_needsync_1, - NEEDSYNC_2, un9_twneedsync_i_a2_i_o2_i_a4_0, - fault_pro_1_iv_0_a2_0, fault_pro_1_iv_0_a2_0_0, - \data_1_i_m2_i_0[25]\, N_2927, \data_1_i_m2_i_0[26]\, - N_2931, \data_1_i_0[31]\, N_2962, \data_1_i_m2_i_0[12]\, - N_3066, N_2904, \data_1_i_m2_i_0[13]\, N_2909, - \data_1_i_m2_i_0[16]\, \data[16]\, N_2912, - \data_1_i_0[15]\, N_805, \data_1_i_i_0[14]\, N_3065, - N_2955, \fault_pro_1_iv_2\, fault_pro_5_m_0_3, - fault_pro_5_m_0_2, \un1_dtlb0_1_m_0_i[45]\, - \un1_dtlb0_1_m_0_1[45]\, N_2241, \adata[4]\, - fault_pro_5_m_0_0, \fault_read\, fault_pri_1_m_1, - \fault_su\, fault_pro_1_m_0_4_0, \I3_1_i_0_0[2]\, N_3044, - \I1_1_i_0_0[0]\, N_3047, nrep_n1_0_i_0, \nrep[0]\, - \nrep[1]\, fault_pri_1_m, \adata[3]\, N_2499, N_97, - \N_86_i\, N_3038, N_3036, N_3037, N_3010, N_3011, N_3012, - N_3009, N_3006, N_3007, N_3005, N_3002, N_3003, N_3001, - N_2998, N_2999, N_3059, N_2976, N_2943, N_2940, N_2941, - N_2905, N_38, sync_isw_RNO_0, N_2494, \N_2532\, N_2509, - N_2539, N_55, N_2531, \N_2550\, fault_pro_1_m_0_4, - \adata[2]\, N_2954, s2_needsync, NEEDSYNC_3, N_2511, - N_2525, N_2922, N_2923, N_2924, N_1168, N_1100, N_1134, - N_1169, N_1101, N_1135, N_1170, N_1102, N_1136, N_1174, - N_1106, N_1140, N_1175, N_1107, N_1141, N_1176, N_1108, - N_1142, N_1177, N_1109, N_1143, N_1178, N_1110, N_1144, - N_1179, N_1111, N_1145, N_1180, N_1112, N_1146, N_1182, - N_1114, N_1148, N_1183, N_1115, N_1149, N_1184, N_1116, - N_1150, N_1186, N_1118, N_1152, N_1187, N_1119, N_1153, - N_1189, N_1121, N_1155, N_1190, N_1122, N_1156, N_1191, - N_1123, N_1157, N_1192, N_1124, N_1158, N_1193, N_1125, - N_1159, N_1194, N_1126, N_1160, N_1195, N_1127, N_1161, - N_1196, N_1128, N_1162, N_1197, N_1129, N_1163, N_1198, - N_1130, N_1164, N_1199, N_1131, N_1165, N_1200, N_1132, - N_1166, N_1270, N_1202, N_1236, N_1271, N_1203, N_1237, - N_1272, N_1204, N_1238, N_1276, N_1208, N_1242, N_1277, - N_1209, N_1243, N_1278, N_1210, N_1244, N_1279, N_1211, - N_1245, N_1280, N_1212, N_1246, N_1281, N_1213, N_1247, - N_1282, N_1214, N_1248, N_1284, N_1216, N_1250, N_1285, - N_1217, N_1251, N_1286, N_1218, N_1252, N_1288, N_1220, - N_1254, N_1289, N_1221, N_1255, N_1291, N_1223, N_1257, - N_1292, N_1224, N_1258, N_1293, N_1225, N_1259, N_1294, - N_1226, N_1260, N_1295, N_1227, N_1261, N_1296, N_1228, - N_1262, N_1297, N_1229, N_1263, \s2_entry[1]\, N_1298, - N_1230, N_1264, N_1299, N_1231, N_1265, N_1300, N_1232, - N_1266, N_1301, N_1233, N_1267, N_1302, N_1234, N_1268, - \adata[9]\, \adata[10]\, \adata[12]\, \adata[21]\, - \adata[22]\, \adata[23]\, \adata[25]\, \adata[27]\, - \s2_entry[0]\, \un1_acc[32]\, \cam_addr[31]_net_1\, - \fault_trans\, fault_trans_0, \fault_inv\, fault_inv_0, - fault_pri_0, \fault_pri\, \I1_1[7]\, \data[31]\, N_2483, - fault_pro_1, cache_0_sqmuxa, N_25, N_27, N_2523, N_29, - N_31, N_2276, s1finished, N_89, \I3_1[0]\, - \cam_addr[12]_net_1\, \data[12]\, \I3_1_i[3]\, - \cam_addr[15]_net_1\, \data[15]\, \I1_1[1]\, - \cam_addr[25]_net_1\, \data[25]\, \I1_1[2]\, - \cam_addr[26]_net_1\, \data[26]\, \I1_1[3]\, - \cam_addr[27]_net_1\, \data_0[27]\, \I1_1[6]\, - \cam_addr[30]_net_1\, \I1_1[4]\, \cam_addr[28]_net_1\, - N_2737, \data[24]\, N_2738, N_2739, N_2740, \data_1[12]\, - \adata[8]\, \data_1[13]\, \adata[26]\, \data_1[30]\, - \data[30]\, \data_1[25]\, \data_1[26]\, \data[23]\, - N_3063, N_3062, \adata[19]\, \data_1[31]\, \data_1[15]\, - \adata[11]\, \data[19]\, \adata[15]\, \data[20]\, - \adata[16]\, \data[21]\, \data_0[24]\, \data[22]\, - \adata[18]\, \data_0[13]\, N_3043, N_3046, N_550, N_19, - N_2735, \N_3160\, N_37, \data[14]\, N_2736, \data_0[16]\, - N_73, N_2747, \data_0[29]\, \adata[7]\, cache, \data[0]\, - \data_0[0]\, \data[1]\, \data_0[1]\, \data[2]\, - \data_0[2]\, \data[3]\, \data_0[3]\, \data[4]\, - \data_0[4]\, \data[5]\, \data_0[5]\, \data[7]\, - \data_0[7]\, walk_use, \data[10]\, \data_0[10]\, - \data[11]\, \data_0[11]\, N_691, \data_0[21]\, N_692, - \data_0[22]\, \I2_1[0]\, \cam_addr[18]_net_1\, \I2_1[1]\, - \cam_addr[19]_net_1\, \data_0[19]\, \I2_1[2]\, - \cam_addr[20]_net_1\, \data_0[20]\, \I2_1[3]\, - \cam_addr[21]_net_1\, \I2_1[4]\, \cam_addr[22]_net_1\, - \I2_1[5]\, \cam_addr[23]_net_1\, \data_0[23]\, \I3_1[4]\, - \cam_addr[16]_net_1\, \data_1[18]\, \adata[14]\, - \data[18]\, \un1_acc[33]\, \data[17]\, \data_0[17]\, - \data_1[28]\, \data_2[28]\, \I3_1[5]\, - \cam_addr[17]_net_1\, \data_2[18]\, N_661, N_701, - \TYP_1[2]\, \N_2482\, \data_2[31]\, \data_3[28]\, - \data[28]\, \data_2[30]\, \data_3[17]\, \data_1[17]\, - N_552, \adata[24]\, \tlbcam_write_op_1[6]\, - \tlbcam_write_op_1[5]\, \tlbcam_write_op_1[4]\, - \tlbcam_write_op_1[3]\, \tlbcam_write_op_1[2]\, - \tlbcam_write_op_1[0]\, \tlbcam_write_op_1[7]\, - \s2_entry[2]\, s2_hm, s2_needsync_1, N_2543, s2_flush, - N_2522, fault_mexc_1, \s2_tlbstate_nss[1]\, - \s2_tlbstate_nss[0]\, \adata[13]\, N_1181, N_1283, N_1215, - N_1249, N_1113, N_1147, N_700, N_693, N_690, N_2544, - N_2265, fault_pro_m, fault_pro, \data_1[14]\, N_1201, - N_1303, N_1235, N_1269, N_1133, N_1167, \TYP_1[0]\, - \data_0[8]\, M_1, N_1171, N_1273, N_1205, N_1239, N_1103, - N_1137, \TYP_1[1]\, \data[9]\, \data_0[9]\, \adata[20]\, - N_1188, N_1290, N_1222, N_1256, N_1120, N_1154, nrep_n0, - nrepe, N_2512, N_2513, \nrep[2]\, \cam_hitaddr_21[0]\, - \s1finished_0\, \cam_hitaddr_18[1]\, N_2551, N_699, - \adata[17]\, N_1185, N_1287, N_1219, N_1253, N_1117, - N_1151, \data[6]\, \data_0[6]\, \tlbcam_write_op_1[1]\, - N_1172, N_1274, N_1206, N_1240, N_1104, N_1138, - \fault_pri_1\, \fault_pro_1_iv_1\, cam_hit_all_1, - \s2_ctx[0]\, \s2_ctx[1]\, \s2_ctx[2]\, \s2_ctx[3]\, - \s2_ctx[4]\, \s2_ctx[5]\, \s2_ctx[6]\, \s2_ctx[7]\, - \un1_cam_hitaddr_1[56]\, \un1_cam_hitaddr_1[62]\, - \un1_cam_hitaddr_1[61]\, \un1_cam_hitaddr[56]\, - \un1_cam_hitaddr[58]\, \un1_cam_hitaddr[60]\, - \un1_cam_hitaddr[61]\, \un1_cam_hitaddr[62]\, - \un1_cam_hitaddr[57]\, \pteout[2]\, \pteout[3]\, - \pteout[4]\, \LVL[0]\, \LVL[1]\, \pteout[31]\, - \pteout[30]\, \pteout[29]\, \pteout[28]\, \pteout[1]\, - \pteout[0]\, \pteout[7]\, \pteout[17]\, \pteout_0[4]\, - \pteout_0[3]\, \pteout_0[2]\, \pteout[27]\, \pteout[6]\, - \pteout[26]\, \pteout[25]\, \pteout[24]\, \pteout[23]\, - \pteout[22]\, \pteout[21]\, \pteout[20]\, \pteout[19]\, - \pteout[18]\, \pteout[16]\, \pteout[15]\, \pteout[14]\, - \pteout[13]\, \pteout[12]\, \pteout[11]\, \pteout[10]\, - \pteout[9]\, \pteout[8]\, \LVL_0[0]\, \LVL_0[1]\, - \pteout_m_i[17]\, \pteout_m_i[27]\, \pteout_m_i[20]\, - \pteout_m_i[19]\, \pteout_m_i[18]\, \pteout_m_i[16]\, - \pteout_m_i[15]\, \pteout_m_i[13]\, \pteout_m_i[12]\, - \pteout_m_i[10]\, \pteout_m_i[9]\, \pteout_m_i[14]\, - \un2_wb_acc_iv_2[14]\, \pteout_m_i_0[26]\, - \pteout_m_i_0[23]\, \pteout_m_i_0[21]\, \pteout_m_i_0[8]\, - \pteout_m_i_0[25]\, \data_1_3_i_a3_2[29]\, - \data_1_3_i_a3_3[28]\, \data_1_3_i_a3_3[26]\, - \data_1_3_i_a3_5[28]\, \data_1_3_i_a3_5[26]\, - \pteout_m_i_0[24]\, \pteout_m_i_0[22]\, - \pteout_m_i_0[11]\, \data_1_3_i_a3_0_2[15]\, N_1496, - N_1468, N_1467, N_1466, N_1495, hit, hit_0, - un1_cam_hitaddr_4_0, WBNEEDSYNC_m, hit_1, - \pteout_m_i_0[17]\, \pteout_m_i_0[27]\, - \pteout_m_i_0[20]\, \pteout_m_i_0[19]\, - \pteout_m_i_0[18]\, \pteout_m_i_0[16]\, - \pteout_m_i_0[15]\, \pteout_m_i_0[14]\, - \pteout_m_i_0[13]\, \pteout_m_i_0[12]\, - \pteout_m_i_0[10]\, \pteout_m_i_0[9]\, \pteout_0[31]\, - \pteout_0[30]\, \pteout_0[29]\, \pteout_0[28]\, - \pteout_0[1]\, \pteout_0[0]\, \pteout_0[7]\, - \pteout_0[17]\, \pteout_0[27]\, \pteout_0[6]\, - \pteout_0[26]\, \pteout_0[25]\, \pteout_0[24]\, - \pteout_0[23]\, \pteout_0[22]\, \pteout_0[21]\, - \pteout_0[20]\, \pteout_0[19]\, \pteout_0[18]\, - \pteout_0[16]\, \pteout_0[15]\, \pteout_0[14]\, - \pteout_0[13]\, \pteout_0[12]\, \pteout_0[11]\, - \pteout_0[10]\, \pteout_0[9]\, \pteout_0[8]\, - \pteout_m_i_0_0[26]\, \pteout_m_i_0_0[25]\, - \pteout_m_i_0_0[24]\, \pteout_m_i_0_0[23]\, - \pteout_m_i_0_0[22]\, \pteout_m_i_0_0[21]\, - \pteout_m_i_0_0[11]\, \pteout_m_i_0_0[8]\, \un1_rst_i_0\, - WBNEEDSYNC_m_0, \LVL_1[0]\, \LVL_1[1]\, \pteout_1[3]\, - \pteout_1[2]\, \pteout_1[4]\, \un2_wb_acc_iv_3[14]\, - \un2_wb_acc_iv_5[16]\, \un2_wb_acc_iv_5[17]\, - \un2_wb_acc_iv_5[18]\, \data_1_3_i_a3_0_5[15]\, - \data_1_3_i_a3_0_5[12]\, \pteout_m_i_1[15]\, - \un2_wb_acc_iv_0[27]\, \un2_wb_acc_iv_1[17]\, - \un2_wb_acc_iv_1[20]\, \un2_wb_acc_iv_1[19]\, - \un2_wb_acc_iv_1[18]\, \un2_wb_acc_iv_1[16]\, - \un2_wb_acc_iv_1[14]\, \un2_wb_acc_iv_1[13]\, - \un2_wb_acc_iv_1[10]\, \un2_wb_acc_iv_1[9]\, - \un2_wb_acc_iv_1[12]\, \pteout_m_i_1[20]\, - \pteout_m_i_1[19]\, \pteout_m_i_1[18]\, - \pteout_m_i_1[16]\, \pteout_m_i_2[15]\, - \pteout_m_i_1[14]\, \pteout_m_i_1[13]\, - \pteout_m_i_1[10]\, \pteout_m_i_1[9]\, \pteout_m_i_1[12]\, - \un2_wb_acc_iv_4[20]\, \un2_wb_acc_iv_4[19]\, - \un2_wb_acc_iv_4[15]\, \un2_wb_acc_iv_4[13]\, - \un2_wb_acc_iv_4[10]\, \un2_wb_acc_iv_4[9]\, - \un2_wb_acc_iv_4[12]\, \data_1_3_i_a3_0_1[12]\, - \data_1_3_i_a3_0_1[15]\, \data_1_3_i_a3_3[29]\, - \pteout_m_i_0_1[26]\, \pteout_m_i_1[17]\, - \pteout_m_i_3[15]\, \pteout_m_i_1[27]\, - \pteout_m_i_0_1[8]\, \pteout_m_i_0_1[11]\, - \pteout_m_i_0_1[24]\, \pteout_m_i_0_1[23]\, - \pteout_m_i_0_1[25]\, \pteout_m_i_0_2[26]\, - \pteout_m_i_0_1[22]\, \pteout_m_i_0_3[26]\, - \pteout_m_i_0_1[21]\, \data_1_3_i_a3_5[30]\, - \data_1_3_i_a3_5[27]\, \data_1_3_i_a3_5[25]\, - \data_1_3_i_a3_1[25]\, \data_1_3_i_a3_1[26]\, - \data_1_3_i_a3_1[27]\, \data_1_3_i_a3_1[28]\, - \data_1_3_i_a3_1[29]\, N_1506, N_1481, N_1479, N_1505, - N_1482, N_1513, N_1480, cam_hit_all_5_sqmuxa_0_a2_0, - accexc_6_4, cam_hit_all_5_sqmuxa, \LVL_2[1]\, \LVL_2[0]\, - \LVL_3[1]\, \pteout_m_i_2[18]\, \pteout_m_i_2[16]\, - \un2_wb_acc_iv_2[20]\, \un2_wb_acc_iv_2[19]\, - \un2_wb_acc_iv_2[17]\, \un2_wb_acc_iv_2[15]\, - \un2_wb_acc_iv_2[13]\, \un2_wb_acc_iv_2[10]\, - \un2_wb_acc_iv_2[9]\, \un2_wb_acc_iv_2[27]\, - \un2_wb_acc_iv_2[12]\, \data_1_3_i_a3_3[30]\, - \pteout_m_i_0_2[23]\, \pteout_m_i_0_2[8]\, \pteout_1[31]\, - \pteout_1[30]\, \pteout_1[29]\, \pteout_1[28]\, - \pteout_1[1]\, \pteout_1[0]\, \pteout_2[4]\, - \pteout_2[3]\, \pteout_2[2]\, \pteout_1[7]\, - \pteout_1[6]\, \pteout_1[25]\, \pteout_1[24]\, - \pteout_1[23]\, \pteout_1[22]\, \pteout_1[18]\, - \pteout_1[16]\, \pteout_1[14]\, \pteout_1[11]\, - \pteout_1[8]\, \pteout_1[20]\, \pteout_1[19]\, - \pteout_1[17]\, \pteout_1[15]\, \pteout_1[13]\, - \pteout_1[10]\, \pteout_1[9]\, \pteout_1[27]\, - \pteout_1[12]\, \pteout_1[26]\, \pteout_1[21]\, - \data_1_3_i_a3_2[25]\, N_1498, WBNEEDSYNC_m_1, \LVL_3[0]\, - \cam_hitaddr_21_1[0]\, \pteout_m_i_2[17]\, - \pteout_m_i_2[27]\, \pteout_m_i_2[14]\, - \pteout_m_i_2[20]\, \pteout_m_i_2[19]\, - \pteout_m_i_3[18]\, \pteout_m_i_3[16]\, - \pteout_m_i_2[13]\, \pteout_m_i_2[10]\, \pteout_m_i_2[9]\, - \pteout_m_i_2[12]\, \pteout_2[31]\, \pteout_2[30]\, - \pteout_2[29]\, \pteout_2[28]\, \pteout_2[1]\, - \pteout_2[0]\, \pteout_2[7]\, \pteout_2[17]\, - \pteout_3[4]\, \pteout_3[3]\, \pteout_3[2]\, - \pteout_2[27]\, \pteout_2[26]\, \pteout_2[24]\, - \pteout_2[22]\, \pteout_2[21]\, \pteout_2[15]\, - \pteout_2[14]\, \pteout_2[6]\, \pteout_2[20]\, - \pteout_2[19]\, \pteout_2[18]\, \pteout_2[16]\, - \pteout_2[13]\, \pteout_2[10]\, \pteout_2[9]\, - \pteout_2[12]\, \pteout_2[8]\, \pteout_2[23]\, - \pteout_2[25]\, \pteout_2[11]\, \pteout_m_i_0_2[24]\, - \pteout_m_i_0_2[22]\, \pteout_m_i_0_2[21]\, - \pteout_m_i_0_3[8]\, \pteout_m_i_0_3[23]\, - \pteout_m_i_0_2[25]\, \pteout_m_i_0_2[11]\, N_1471, - N_1470, N_1469, N_1497, WBNEEDSYNC_m_2, hit_2, - \pteout_4[2]\, \LVL_4[0]\, \pteout_4[4]\, \pteout_4[3]\, - \LVL_4[1]\, cam_hit_all_5_sqmuxa_2, accexc_6_3, - \accexc_6\, accexc_6_2, \LVL_RNIT69H911[0]\, - \un2_wb_acc_iv_4[27]\, \N_2709_i_0\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : mmutlbcam_2_0_2 - Use entity work.mmutlbcam_2_0_2(DEF_ARCH); - for all : mmutlbcam_2_0_4 - Use entity work.mmutlbcam_2_0_4(DEF_ARCH); - for all : mmutlbcam_2_0 - Use entity work.mmutlbcam_2_0(DEF_ARCH); - for all : mmutlbcam_2_0_5 - Use entity work.mmutlbcam_2_0_5(DEF_ARCH); - for all : syncramZ0_1 - Use entity work.syncramZ0_1(DEF_ARCH); - for all : mmutlbcam_2_0_3 - Use entity work.mmutlbcam_2_0_3(DEF_ARCH); - for all : mmutlbcam_2_0_6 - Use entity work.mmutlbcam_2_0_6(DEF_ARCH); - for all : mmutlbcam_2_0_7 - Use entity work.mmutlbcam_2_0_7(DEF_ARCH); - for all : mmutlbcam_2_0_1 - Use entity work.mmutlbcam_2_0_1(DEF_ARCH); -begin - - LVL_RNIT69H911(0) <= \LVL_RNIT69H911[0]\; - data_1_5 <= \data_1[17]\; - data_0_22 <= \data_0[22]\; - data_0_21 <= \data_0[21]\; - data_0_20 <= \data_0[20]\; - data_0_19 <= \data_0[19]\; - data_0_23 <= \data_0[23]\; - data_0_16 <= \data_0[16]\; - data_0_27 <= \data_0[27]\; - data_0_29 <= \data_0[29]\; - data_0_13 <= \data_0[13]\; - data_18 <= \data[18]\; - data_28 <= \data[28]\; - data_30 <= \data[30]\; - data_25 <= \data[25]\; - data_26 <= \data[26]\; - data_31 <= \data[31]\; - data_24 <= \data[24]\; - data_14 <= \data[14]\; - data_15 <= \data[15]\; - data_12 <= \data[12]\; - adata_20 <= \adata[20]\; - adata_13 <= \adata[13]\; - adata_17 <= \adata[17]\; - adata_26 <= \adata[26]\; - adata_24 <= \adata[24]\; - adata_19 <= \adata[19]\; - adata_18 <= \adata[18]\; - adata_16 <= \adata[16]\; - adata_15 <= \adata[15]\; - adata_14 <= \adata[14]\; - adata_11 <= \adata[11]\; - adata_8 <= \adata[8]\; - adata_7 <= \adata[7]\; - adata_9 <= \adata[9]\; - adata_12 <= \adata[12]\; - adata_2 <= \adata[2]\; - adata_3 <= \adata[3]\; - adata_4 <= \adata[4]\; - adata_10 <= \adata[10]\; - adata_27 <= \adata[27]\; - adata_22 <= \adata[22]\; - adata_21 <= \adata[21]\; - adata_25 <= \adata[25]\; - adata_23 <= \adata[23]\; - N_2709_i_0 <= \N_2709_i_0\; - accexc_6 <= \accexc_6\; - un1_rst_i_0 <= \un1_rst_i_0\; - N_3160 <= \N_3160\; - fault_pri_1 <= \fault_pri_1\; - fault_pri <= \fault_pri\; - N_2482 <= \N_2482\; - fault_su <= \fault_su\; - fault_read <= \fault_read\; - fault_trans <= \fault_trans\; - fault_inv <= \fault_inv\; - N_2550 <= \N_2550\; - N_2532 <= \N_2532\; - fault_pro_1_iv_1 <= \fault_pro_1_iv_1\; - fault_pro_1_iv_2 <= \fault_pro_1_iv_2\; - s1finished_0 <= \s1finished_0\; - walk_use_0 <= \walk_use_0\; - N_86_i <= \N_86_i\; - - \r.s2_entry_1_RNICBOE[1]\ : MX2 - port map(A => N_1204, B => N_1238, S => \s2_entry_1[1]\, Y - => N_1272); - - \r.s2_entry_0_RNIHUSSN2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_1_0[7]\); - - \r.s2_data_RNIRH0O1[18]\ : MX2 - port map(A => \adata[14]\, B => \data[18]\, S => - \un1_acc[33]\, Y => \data_1[18]\); - - \cam_addr[17]\ : MX2 - port map(A => maddress(17), B => data_2_0, S => trans_op, Y - => \cam_addr[17]_net_1\); - - \r.s2_entry_RNI0N35_0[1]\ : NOR2A - port map(A => \s2_entry_4[2]\, B => \s2_entry[1]\, Y => - \tlbcam_write_op_1_1[4]\); - - \r.s2_entry_1_RNII44Q[1]\ : MX2 - port map(A => N_1228, B => N_1262, S => \s2_entry_1[1]\, Y - => N_1296); - - \r.s2_tlbstate_RNO_2[0]\ : OAI1 - port map(A => N_82, B => \N_2550\, C => \s2_tlbstate[0]\, Y - => N_2538); - - \cam_addr[28]\ : MX2 - port map(A => maddress(28), B => data_0_28, S => trans_op_0, - Y => \cam_addr[28]_net_1\); - - \r.s2_entry_RNIC1EK[0]\ : MX2 - port map(A => N_1201, B => N_1303, S => \s2_entry[0]\, Y - => \un1_acc[33]\); - - \r.s2_entry_RNIQVRN[1]\ : MX2 - port map(A => N_1231, B => N_1265, S => \s2_entry[1]\, Y - => N_1299); - - \r.s2_needsync_RNO_0\ : NOR3C - port map(A => NEEDSYNC_0, B => s2_needsync_0, C => - s2_needsync_2, Y => s2_needsync_3); - - \r.s2_data_RNITSTM[27]\ : MX2C - port map(A => \cam_addr[27]_net_1\, B => \data_0[27]\, S - => s2_flush_0, Y => \I1_1[3]\); - - \r.walk_use_RNI7P5M1_0\ : NOR2 - port map(A => walk_use, B => N_552, Y => N_3065); - - \r.s2_data_RNI11QR[23]\ : MX2C - port map(A => \cam_addr[23]_net_1\, B => \data_0[23]\, S - => s2_flush_1, Y => \I2_1[5]\); - - \r.walk_fault.fault_pro_RNO_1\ : OR3B - port map(A => N_97, B => fault_pro_1_iv_0_a2_0, C => - hrdata_0_3, Y => N_2499); - - \r.s2_flush_0_RNI64RC1\ : NOR2 - port map(A => N_2530, B => N_93, Y => s1finished_1); - - \r.walk_transdata.data_RNO[19]\ : MX2 - port map(A => hrdata_0_15, B => \data_0[19]\, S => - lvl_i_1_0(1), Y => N_699); - - \r.s2_entry_RNIVH39[1]\ : MX2 - port map(A => N_1117, B => N_1151, S => \s2_entry[1]\, Y - => N_1185); - - \cam_addr[30]\ : MX2 - port map(A => maddress(30), B => data_0_30, S => trans_op_0, - Y => \cam_addr[30]_net_1\); - - \r.walk_fault.fault_inv_RNIQ09E\ : NOR2B - port map(A => \walk_use_0\, B => fault_inv_0, Y => - \fault_inv\); - - \r.s2_entry_RNI20TN[1]\ : MX2 - port map(A => N_1233, B => N_1267, S => \s2_entry[1]\, Y - => N_1301); - - \tlbcam0.0.tag0\ : mmutlbcam_2_0_2 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - hrdata_0_27 => hrdata_0_27, hrdata_0_26 => hrdata_0_26, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_21 => hrdata_0_21, hrdata_0_18 => hrdata_0_18, - hrdata_0_16 => hrdata_0_16, hrdata_0_15 => hrdata_0_15, - hrdata_0_12 => hrdata_0_12, hrdata_0_8 => hrdata_0_8, - hrdata_0_1 => hrdata_0_1, hrdata_0_0 => hrdata_0_0, - hrdata_0_4 => hrdata_0_4, hrdata_0_3 => hrdata_0_3, - hrdata_0_2 => hrdata_0_2, data_0_11 => \data_0[29]\, - data_0_9 => \data_0[27]\, data_0_8 => \data[26]\, - data_0_7 => \data[25]\, data_0_4 => \data_0[22]\, - data_0_3 => \data_0[21]\, data_0_2 => \data_0[20]\, - data_0_0 => \data[18]\, tlbcam_write_op_1_1(0) => - \tlbcam_write_op_1_1[0]\, s2_ctx(7) => \s2_ctx[7]\, - s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => \s2_ctx[5]\, - s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => \s2_ctx[3]\, - s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => \s2_ctx[1]\, - s2_ctx(0) => \s2_ctx[0]\, hrdata_24 => hrdata_31, - hrdata_23 => hrdata_30, hrdata_22 => hrdata_29, hrdata_21 - => hrdata_28, hrdata_17 => hrdata_24, hrdata_10 => - hrdata_17, hrdata_7 => hrdata_14, hrdata_6 => hrdata_13, - hrdata_4 => hrdata_11, hrdata_3 => hrdata_10, hrdata_2 - => hrdata_9, hrdata_0_d0 => hrdata_7, - tlbcam_write_op_1(0) => \tlbcam_write_op_1[0]\, TYP_1(2) - => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, TYP_1(0) => - \TYP_1[0]\, s2_entry(2) => \s2_entry[2]\, LVL_1(1) => - \LVL_1[1]\, LVL_1(0) => \LVL_1[0]\, TYP_1_0(0) => - \TYP_1_0[0]\, I1_1_i_0_0(0) => \I1_1_i_0_0[0]\, - I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, data(31) => \data[31]\, - data(30) => \data[30]\, data(29) => data_1_17, data(28) - => \data[28]\, data(27) => data_1_15, data(26) => - data_0_26, data(25) => data_0_25, data(24) => \data[24]\, - data(23) => \data_0[23]\, data(22) => data_1_10, data(21) - => data_1_9, data(20) => data_1_8, data(19) => - \data_0[19]\, data(18) => data_0_18, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, LVL_0(1) => - \LVL_0[1]\, LVL_0(0) => \LVL_0[0]\, s2_entry_1(2) => - \s2_entry_1_0[2]\, pteout_1(4) => \pteout_0[4]\, - pteout_1(3) => \pteout_0[3]\, pteout_1(2) => - \pteout_0[2]\, s2_entry_0(2) => \s2_entry_0[2]\, - pteout_0_17 => \pteout[17]\, pteout_0_20 => \pteout[20]\, - pteout_0_31 => \pteout[31]\, pteout_0_30 => \pteout[30]\, - pteout_0_29 => \pteout[29]\, pteout_0_28 => \pteout[28]\, - pteout_0_27 => \pteout[27]\, pteout_0_26 => \pteout[26]\, - pteout_0_25 => \pteout[25]\, pteout_0_24 => \pteout[24]\, - pteout_0_23 => \pteout[23]\, pteout_0_22 => \pteout[22]\, - pteout_0_21 => \pteout[21]\, pteout_0_19 => \pteout[19]\, - pteout_0_18 => \pteout[18]\, pteout_0_16 => \pteout[16]\, - pteout_0_15 => \pteout[15]\, pteout_0_14 => \pteout[14]\, - pteout_0_13 => \pteout[13]\, pteout_0_12 => \pteout[12]\, - pteout_0_11 => \pteout[11]\, pteout_0_10 => \pteout[10]\, - pteout_0_9 => \pteout[9]\, pteout_0_8 => \pteout[8]\, - pteout_0_7 => \pteout[7]\, pteout_0_6 => \pteout[6]\, - pteout_0_1 => \pteout[1]\, pteout_0_0 => \pteout[0]\, - I3_1_i(3) => \I3_1_i[3]\, tlbcam_write_op_1_0(0) => - \tlbcam_write_op_1_0[0]\, cam_hitaddr_21(0) => - \cam_hitaddr_21[0]\, pteout_3 => \pteout_1[3]\, pteout_2 - => \pteout_1[2]\, pteout_4 => \pteout_1[4]\, un1_m0_2_4 - => un1_m0_2_97, un1_m0_2_3 => un1_m0_2_96, un1_m0_2_2 - => un1_m0_2_95, un1_m0_2_0 => un1_m0_2_93, un1_m0_2_15 - => un1_m0_2_108, un2_wb_acc_iv_2(14) => - \un2_wb_acc_iv_2[14]\, un2_wb_acc_iv_3(14) => - \un2_wb_acc_iv_3[14]\, un2_wb_acc_iv_5(18) => - \un2_wb_acc_iv_5[18]\, un2_wb_acc_iv_5(17) => - \un2_wb_acc_iv_5[17]\, un2_wb_acc_iv_5(16) => - \un2_wb_acc_iv_5[16]\, data_1_3_i_a3_0_5_3 => - \data_1_3_i_a3_0_5[15]\, data_1_3_i_a3_0_5_0 => - \data_1_3_i_a3_0_5[12]\, LVL_RNIT69H911(0) => - \LVL_RNIT69H911[0]\, ctx_4 => ctx(5), ctx_3 => ctx(4), - ctx_0_d0 => ctx(1), ctx_1 => ctx(2), ctx_0_7 => ctx_0(7), - ctx_0_3 => ctx_0(3), ctx_0_0 => ctx_0(0), ctx_0_6 => - ctx_0(6), I1_1_5 => \I1_1[6]\, I1_1_2 => \I1_1[3]\, - I1_1_0 => \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_3 => - \I1_1[4]\, I1_1_6 => \I1_1[7]\, I2_1(5) => \I2_1[5]\, - I2_1(4) => \I2_1[4]\, I2_1(3) => \I2_1[3]\, I2_1(2) => - \I2_1[2]\, I2_1(1) => \I2_1[1]\, I2_1(0) => \I2_1[0]\, - I3_1_4 => \I3_1[4]\, I3_1_0 => \I3_1[0]\, I3_1_5 => - \I3_1[5]\, pteout_m_i_1(15) => \pteout_m_i_1[15]\, - un2_wb_acc_iv_0_12 => \un2_wb_acc_iv_0[27]\, - un2_wb_acc_iv_1_8 => \un2_wb_acc_iv_1[17]\, - un2_wb_acc_iv_1_11 => \un2_wb_acc_iv_1[20]\, - un2_wb_acc_iv_1_10 => \un2_wb_acc_iv_1[19]\, - un2_wb_acc_iv_1_9 => \un2_wb_acc_iv_1[18]\, - un2_wb_acc_iv_1_7 => \un2_wb_acc_iv_1[16]\, - un2_wb_acc_iv_1_5 => \un2_wb_acc_iv_1[14]\, - un2_wb_acc_iv_1_4 => \un2_wb_acc_iv_1[13]\, - un2_wb_acc_iv_1_1 => \un2_wb_acc_iv_1[10]\, - un2_wb_acc_iv_1_0 => \un2_wb_acc_iv_1[9]\, - un2_wb_acc_iv_1_3 => \un2_wb_acc_iv_1[12]\, pteout_m_i_11 - => \pteout_m_i_1[20]\, pteout_m_i_10 => - \pteout_m_i_1[19]\, pteout_m_i_9 => \pteout_m_i_1[18]\, - pteout_m_i_7 => \pteout_m_i_1[16]\, pteout_m_i_6 => - \pteout_m_i_2[15]\, pteout_m_i_5 => \pteout_m_i_1[14]\, - pteout_m_i_4 => \pteout_m_i_1[13]\, pteout_m_i_1_d0 => - \pteout_m_i_1[10]\, pteout_m_i_0_d0 => \pteout_m_i_1[9]\, - pteout_m_i_3 => \pteout_m_i_1[12]\, un2_wb_acc_iv_4_11 - => \un2_wb_acc_iv_4[20]\, un2_wb_acc_iv_4_10 => - \un2_wb_acc_iv_4[19]\, un2_wb_acc_iv_4_6 => - \un2_wb_acc_iv_4[15]\, un2_wb_acc_iv_4_4 => - \un2_wb_acc_iv_4[13]\, un2_wb_acc_iv_4_1 => - \un2_wb_acc_iv_4[10]\, un2_wb_acc_iv_4_0 => - \un2_wb_acc_iv_4[9]\, un2_wb_acc_iv_4_3 => - \un2_wb_acc_iv_4[12]\, data_1_3_i_a3_0_1_0 => - \data_1_3_i_a3_0_1[12]\, data_1_3_i_a3_0_1_3 => - \data_1_3_i_a3_0_1[15]\, data_1_3_i_a3_2(29) => - \data_1_3_i_a3_2[29]\, data_1_3_i_a3_3(29) => - \data_1_3_i_a3_3[29]\, pteout_m_i_0_1(26) => - \pteout_m_i_0_1[26]\, pteout_m_i_0_9 => - \pteout_m_i_1[17]\, pteout_m_i_0_7 => \pteout_m_i_3[15]\, - pteout_m_i_0_19 => \pteout_m_i_1[27]\, pteout_m_i_0_0_d0 - => \pteout_m_i_0_1[8]\, pteout_m_i_0_3 => - \pteout_m_i_0_1[11]\, pteout_m_i_0_16 => - \pteout_m_i_0_1[24]\, pteout_m_i_0_15 => - \pteout_m_i_0_1[23]\, pteout_m_i_0_17 => - \pteout_m_i_0_1[25]\, pteout_m_i_0_18 => - \pteout_m_i_0_2[26]\, pteout_m_i_0_0_14 => - \pteout_m_i_0_1[22]\, pteout_m_i_0_0_18 => - \pteout_m_i_0_3[26]\, pteout_m_i_0_0_13 => - \pteout_m_i_0_1[21]\, data_1_3_i_a3_5_5 => - \data_1_3_i_a3_5[30]\, data_1_3_i_a3_5_3 => - \data_1_3_i_a3_5[28]\, data_1_3_i_a3_5_2 => - \data_1_3_i_a3_5[27]\, data_1_3_i_a3_5_1 => - \data_1_3_i_a3_5[26]\, data_1_3_i_a3_5_0 => - \data_1_3_i_a3_5[25]\, data_1_3_i_a3_1(29) => - \data_1_3_i_a3_1[29]\, data_1_3_i_a3_1(28) => - \data_1_3_i_a3_1[28]\, data_1_3_i_a3_1(27) => - \data_1_3_i_a3_1[27]\, data_1_3_i_a3_1(26) => - \data_1_3_i_a3_1[26]\, data_1_3_i_a3_1(25) => - \data_1_3_i_a3_1[25]\, data_1_3_i_a3_6_2 => - data_1_3_i_a3_6_2, data_1_3_i_a3_6_4 => data_1_3_i_a3_6_4, - data_1_3_i_a3_6_1 => data_1_3_i_a3_6_1, data_1_3_i_a3_6_0 - => data_1_3_i_a3_6_0, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, - N_2701 => N_2701, N_1104 => N_1104, N_1496 => N_1496, - N_1506 => N_1506, N_1117 => N_1117, N_1481 => N_1481, - N_1120 => N_1120, N_1103 => N_1103, M_1 => M_1, N_2483 - => N_2483, trans_op => trans_op, un1_tlbcami_3 => - un1_tlbcami_3, fault_pro67 => fault_pro67, read => read, - M_m => M_m, N_1133 => N_1133, N_1479 => N_1479, s2_flush - => s2_flush, e => e, rst => rst, un1_rst_i_0 => - \un1_rst_i_0\, N_1505 => N_1505, N_1482 => N_1482, N_1495 - => N_1495, N_661 => N_661, N_3046 => N_3046, N_1513 => - N_1513, N_3043 => N_3043, N_61 => N_61, N_2720 => N_2720, - N_2717 => N_2717, N_2714 => N_2714, N_1132 => N_1132, - N_1131 => N_1131, N_1130 => N_1130, N_1129 => N_1129, - N_1128 => N_1128, N_1127 => N_1127, N_1126 => N_1126, - N_1125 => N_1125, N_1124 => N_1124, N_1123 => N_1123, - N_1122 => N_1122, N_1121 => N_1121, N_1119 => N_1119, - N_1118 => N_1118, N_1116 => N_1116, N_1115 => N_1115, - N_1114 => N_1114, N_1113 => N_1113, N_1112 => N_1112, - N_1111 => N_1111, N_1110 => N_1110, N_1109 => N_1109, - N_1108 => N_1108, N_1107 => N_1107, N_1106 => N_1106, - N_1102 => N_1102, N_1101 => N_1101, N_1100 => N_1100, - s2_flush_0 => s2_flush_0, G_80_0 => G_80_0, N_1467 => - N_1467, N_1480 => N_1480, N_1466 => N_1466, - cam_hit_all_5_sqmuxa_0_a2_0 => - cam_hit_all_5_sqmuxa_0_a2_0, N_2551 => N_2551, N_1468 => - N_1468, N_2703_i_0 => N_2703_i_0, N_2699_i_0 => - N_2699_i_0, su => su, un54_fault_pro_m_0 => - un54_fault_pro_m_0, un54_fault_pro_m => un54_fault_pro_m, - accexc_6 => \accexc_6\, fault_pro => fault_pro_0, - fault_pri => fault_pri_2, N_2709_i_0 => \N_2709_i_0\, - N_2711_i_0 => N_2711_i_0, N_2702_i_0 => N_2702_i_0, - tlbcamo_needsync => tlbcamo_needsync, WBNEEDSYNC_m_0 => - WBNEEDSYNC_m_0, cam_hit_all_1 => cam_hit_all_1, - accexc_6_4 => accexc_6_4, cam_hit_all_5_sqmuxa => - cam_hit_all_5_sqmuxa); - - \r.walk_transdata.data_RNIJ4V9[10]\ : MX2 - port map(A => \data[10]\, B => \data_0[10]\, S => walk_use, - Y => un1_m0_2_11); - - \r.s2_entry_1_RNIEHEE2[0]\ : NOR2A - port map(A => N_3062, B => \adata[19]\, Y => N_2943); - - \r.sync_isw_RNO_1\ : AOI1B - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, C - => rst, Y => sync_isw_1_i_0_0); - - \r.s2_entry_0_RNI4IDM1[0]\ : MX2 - port map(A => N_1169, B => N_1271, S => \s2_entry_0[0]\, Y - => adata_1); - - \r.s2_entry_1_RNIA43Q[1]\ : MX2 - port map(A => N_1226, B => N_1260, S => \s2_entry_1[1]\, Y - => N_1294); - - \r.s2_data_RNILCTM[25]\ : MX2C - port map(A => \cam_addr[25]_net_1\, B => \data[25]\, S => - s2_flush_0, Y => \I1_1[1]\); - - \r.s2_entry_RNI7NGJ[1]\ : MX2 - port map(A => N_1120, B => N_1154, S => \s2_entry[1]\, Y - => N_1188); - - \r.s2_entry_RNIMFRN[1]\ : MX2 - port map(A => N_1230, B => N_1264, S => \s2_entry[1]\, Y - => N_1298); - - \r.walk_transdata.data_RNIKU1T4[16]\ : OA1C - port map(A => N_3065, B => \adata[12]\, C => - \data_1_i_m2_i_0[16]\, Y => data_RNIKU1T4(16)); - - \r.s2_read_RNIGT0OO\ : OAI1 - port map(A => hrdata_6, B => \fault_read\, C => hrdata_5, Y - => N_95); - - \r.s2_entry_0_RNIOJ0Q[1]\ : MX2 - port map(A => N_1125, B => N_1159, S => \s2_entry_0[1]\, Y - => N_1193); - - \r.walk_fault.fault_trans_RNIJMK7\ : NOR2B - port map(A => \walk_use_0\, B => fault_trans_0, Y => - \fault_trans\); - - \r.s2_needsync_RNO_2\ : AOI1B - port map(A => un1_tlbcami_3_1, B => tlbcamo_needsync_1, C - => NEEDSYNC_2, Y => s2_needsync_0); - - \cam_addr[27]\ : MX2 - port map(A => maddress(27), B => data_1_15, S => trans_op_0, - Y => \cam_addr[27]_net_1\); - - \r.nrep[0]\ : DFN1E1 - port map(D => nrep_n0, CLK => lclk_c, E => nrepe, Q => - \nrep[0]\); - - \r.walk_transdata.data[20]\ : DFN1E0 - port map(D => N_700, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data[20]\); - - \r.s2_data[13]\ : DFN1E1 - port map(D => data_13, CLK => lclk_c, E => s1finished_1, Q - => \data_0[13]\); - - \r.walk_transdata.data_RNI6G3D[21]\ : NOR2A - port map(A => walk_use_1, B => \data[21]\, Y => N_3006); - - \r.s2_entry_0_RNICT011[0]\ : MX2 - port map(A => N_1170, B => N_1272, S => \s2_entry_0[0]\, Y - => \adata[2]\); - - \r.s2_data_RNI1QRN5[31]\ : OA1C - port map(A => N_3059, B => \data[31]\, C => - \data_1_i_0[31]\, Y => N_317); - - \r.walk_fault.fault_trans_RNO\ : NOR2 - port map(A => fault_trans_i_2, B => N_2523, Y => N_27); - - \r.sync_isw_RNI7DR9\ : NOR2B - port map(A => sync_isw, B => \s2_tlbstate[1]\, Y => - \N_2550\); - - \r.s2_data_RNI23LE2[17]\ : MX2 - port map(A => \adata[13]\, B => \data_1[17]\, S => N_552, Y - => \data[17]\); - - \p0.transdata.data_1_i_a2_0[29]\ : NOR2A - port map(A => \walk_use_0\, B => \data[29]\, Y => N_2978); - - \r.s2_entry_1_RNIGFNN1[0]\ : MX2 - port map(A => N_1193, B => N_1295, S => \s2_entry_1[0]\, Y - => \adata[25]\); - - \r.walk_fault.fault_mexc_RNO_1\ : OA1B - port map(A => N_89, B => s2_flush, C => \s2_tlbstate[0]\, Y - => N_2531); - - \r.s2_data[17]\ : DFN1E1 - port map(D => data_2_0, CLK => lclk_c, E => s1finished_1, Q - => \data_1[17]\); - - \r.s2_data[22]\ : DFN1E1 - port map(D => data_1_10, CLK => lclk_c, E => s1finished_1, - Q => \data_0[22]\); - - \r.s2_ctx[1]\ : DFN1E1 - port map(D => ctx(1), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[1]\); - - \r.s2_entry_RNIUFSN[1]\ : MX2 - port map(A => N_1232, B => N_1266, S => \s2_entry[1]\, Y - => N_1300); - - \r.s2_entry_RNIM00O[1]\ : MX2 - port map(A => N_1229, B => N_1263, S => \s2_entry[1]\, Y - => N_1297); - - \r.s2_entry_1_RNILTFN1[0]\ : MX2 - port map(A => N_1186, B => N_1288, S => \s2_entry_1[0]\, Y - => \adata[18]\); - - \r.s2_entry[0]\ : DFN1E0 - port map(D => \s2_entry_1_0[0]\, CLK => lclk_c, E => N_53, - Q => \s2_entry[0]\); - - \r.walk_fault.fault_pri_RNIO7TIU\ : OR2 - port map(A => fault_pro_1_0, B => \fault_pri_1\, Y => - fault_mexc_3_2); - - \r.s2_entry_1_RNI242Q[1]\ : MX2 - port map(A => N_1224, B => N_1258, S => \s2_entry_1[1]\, Y - => N_1292); - - \r.s2_flush_0_RNIB9GG1\ : OR2A - port map(A => rst, B => \s1finished_0\, Y => un1_rst_3); - - \r.walk_transdata.data_RNIHEPD[1]\ : MX2 - port map(A => \data[1]\, B => \data_0[1]\, S => walk_use_1, - Y => un1_m0_2_2); - - \r.walk_use_RNI7P5M1\ : OR2A - port map(A => N_552, B => walk_use, Y => N_3066); - - \r.s2_tlbstate_RNO_0[1]\ : MX2C - port map(A => N_2552, B => \s2_tlbstate[1]\, S => - \s2_tlbstate[0]\, Y => \s2_tlbstate_ns_0_0_0[1]\); - - \r.walk_use_1\ : DFN1E1 - port map(D => sync_isw_RNII96B91, CLK => lclk_c, E => - s2_tlbstate_3, Q => walk_use_1); - - \r.s2_entry_1_RNIOFON1[0]\ : MX2 - port map(A => N_1194, B => N_1296, S => \s2_entry_1[0]\, Y - => \adata[26]\); - - \r.walk_transdata.data[1]\ : DFN1E0 - port map(D => \data[1]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[1]\); - - \r.s2_flush_0_RNI64RC1_1\ : NOR2 - port map(A => N_2530, B => N_93, Y => \s1finished_0\); - - \r.s2_entry_RNIEFRD[1]\ : MX2 - port map(A => N_1234, B => N_1268, S => \s2_entry[1]\, Y - => N_1302); - - \r.s2_entry_1_RNIA2N21[0]\ : MX2 - port map(A => N_1180, B => N_1282, S => \s2_entry_1[0]\, Y - => \adata[12]\); - - \r.walk_fault.fault_pro_RNIF8BA\ : OR2B - port map(A => walk_use, B => fault_pro, Y => fault_pro_m); - - \r.s2_data_RNI15UM[28]\ : MX2C - port map(A => \cam_addr[28]_net_1\, B => \data[28]\, S => - s2_flush_0, Y => \I1_1[4]\); - - \r.s2_tlbstate_RNI667LK_0[1]\ : OR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => N_82, Y => cache_0_sqmuxa_0); - - \r.walk_transdata.data_RNIFEPD[0]\ : MX2 - port map(A => \data[0]\, B => \data_0[0]\, S => walk_use_1, - Y => un1_m0_2_1); - - \r.s2_entry_0_RNIQ23VN2_2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[4]\, Y => - \tlbcam_write_op_1_0[5]\); - - \r.nrep_RNILFC969[1]\ : MX2 - port map(A => \nrep[1]\, B => \cam_hitaddr_18[1]\, S => - \s1finished_0\, Y => \s2_entry_1_0[1]\); - - \p0.tlbcam_tagin.I3_1_i_0_a2_0[1]\ : OR2 - port map(A => data_13, B => N_3073, Y => N_3040); - - \r.walk_fault.fault_trans\ : DFN1E1 - port map(D => N_27, CLK => lclk_c, E => N_2276, Q => - fault_trans_0); - - \r.s2_data_RNIICTM[16]\ : MX2C - port map(A => \cam_addr[16]_net_1\, B => \data_0[16]\, S - => s2_flush_1, Y => \I3_1[4]\); - - \r.s2_ctx[0]\ : DFN1E1 - port map(D => ctx(0), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[0]\); - - \r.walk_transdata.data_RNO[18]\ : MX2 - port map(A => hrdata_0_14, B => \data[18]\, S => - lvl_i_1_0(1), Y => N_690); - - \p0.transdata.data_1_i_a2_0_RNI5PC2[29]\ : OR2 - port map(A => N_2977, B => N_2978, Y => \data_1_i_0[29]\); - - \r.s2_flush\ : DFN1E1 - port map(D => s2_flush_1_0, CLK => lclk_c, E => un1_rst_3, - Q => s2_flush); - - \r.s2_entry_0_RNIGJVP[1]\ : MX2 - port map(A => N_1123, B => N_1157, S => \s2_entry_0[1]\, Y - => N_1191); - - \r.s2_data_RNIOM0N1[14]\ : OR2A - port map(A => \data[14]\, B => N_3066, Y => N_2954); - - \r.s2_data_RNIBM1T4[15]\ : NOR2 - port map(A => \data_1_i_0[15]\, B => N_2976, Y => N_351); - - \r.nrep_RNO_1[1]\ : XNOR2 - port map(A => \nrep[0]\, B => \nrep[1]\, Y => nrep_n1_0_i_0); - - \r.walk_fault.fault_pro_RNO\ : AO1C - port map(A => hrdata_0_2, B => fault_pro_1_iv_0_a2_0_0, C - => N_2499, Y => fault_pro_1); - - \r.walk_use_0_RNISPLU1\ : NOR3A - port map(A => \adata[4]\, B => N_2241, C => \walk_use_0\, Y - => \un1_dtlb0_1_m_0_1[45]\); - - \r.s2_flush_1_RNIOIQK\ : OR2 - port map(A => N_3073, B => data_1_12, Y => N_3046); - - \r.s2_entry_1_RNI7EJF[1]\ : MX2 - port map(A => N_1217, B => N_1251, S => \s2_entry_1[1]\, Y - => N_1285); - - \r.s2_su_RNIMK6L2\ : NOR3B - port map(A => fault_pro_5_m_0_0, B => \adata[2]\, C => - N_2241, Y => fault_pro_5_m_0_2); - - \r.walk_fault.fault_lvl[0]\ : DFN1E0 - port map(D => N_80, CLK => lclk_c, E => cache_0_sqmuxa_0, Q - => fault_lvl(0)); - - \r.s2_entry_RNI27MJ1_0[0]\ : NOR2B - port map(A => \un1_acc[33]\, B => \un1_acc[32]\, Y => N_550); - - \r.s2_entry_RNITUUSN2_2[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[2]\, C => \s2_entry[0]\, Y => - \tlbcam_write_op_1[2]\); - - \r.s2_su_RNIMHUE1\ : NOR3 - port map(A => \walk_use_0\, B => \fault_su\, C => N_2241, Y - => fault_pri_1_m_1); - - \r.s2_entry_RNITUUSN2_0[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry[0]\, C => - \tlbcam_write_op_1_1[4]\, Y => \tlbcam_write_op_1[5]\); - - \r.s2_entry_0_RNIQ23VN2_0[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[4]\, Y => - \tlbcam_write_op_1_1[5]\); - - \p0.transdata.data_1_i_m2_i_a2_0[27]\ : NOR2A - port map(A => \walk_use_0\, B => \data[27]\, Y => N_2959); - - \r.walk_transdata.data_RNI5C3D[20]\ : NOR2A - port map(A => walk_use_1, B => \data[20]\, Y => N_3002); - - \r.s2_hm_RNI84O9_0\ : NOR3B - port map(A => s2_hm, B => s2_needsync_1, C => tlbdis, Y => - N_2543); - - \r.s2_entry_1_RNIEUJF[1]\ : MX2 - port map(A => N_1218, B => N_1252, S => \s2_entry_1[1]\, Y - => N_1286); - - \r.s2_data[25]\ : DFN1E1 - port map(D => data_0_25, CLK => lclk_c, E => s1finished_1, - Q => \data[25]\); - - \r.walk_transdata.data[10]\ : DFN1E0 - port map(D => \data[10]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[10]\); - - \r.s2_entry_1_RNIQ1N21[0]\ : MX2 - port map(A => N_1178, B => N_1280, S => \s2_entry_1[0]\, Y - => \adata[10]\); - - \r.s2_data_RNIKRUQ1[30]\ : OR2B - port map(A => \data[30]\, B => N_3059, Y => N_2924); - - \r.s2_data[31]\ : DFN1E1 - port map(D => data_0_31, CLK => lclk_c, E => s1finished, Q - => \data[31]\); - - \r.walk_transdata.data[24]\ : DFN1E0 - port map(D => N_2737, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data_0[24]\); - - \r.s2_tlbstate_RNIN69E[0]\ : NOR2 - port map(A => \s2_tlbstate[0]\, B => s2_flush, Y => N_2544); - - \r.s2_entry_RNIKQOQN2_1[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[7]\, C => \s2_entry[0]\, Y => - \tlbcam_write_op_1[6]\); - - \r.s2_entry_0_RNI55CP[1]\ : MX2 - port map(A => N_1101, B => N_1135, S => \s2_entry_0[1]\, Y - => N_1169); - - \p0.tlb_checkfault.un14_two_error_i\ : NOR2B - port map(A => hrdata_0_4, B => hrdata_0_3, Y => \N_2482\); - - \r.s2_flush_1\ : DFN1E1 - port map(D => s2_flush_1_0, CLK => lclk_c, E => un1_rst_3, - Q => s2_flush_1); - - \r.s2_entry_1_RNINDJF[1]\ : MX2 - port map(A => N_1213, B => N_1247, S => \s2_entry_1[1]\, Y - => N_1281); - - \r.walk_transdata.cache\ : DFN1E0 - port map(D => hrdata_7, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => cache); - - \r.s2_entry_0_RNITCGF[1]\ : MX2 - port map(A => N_1110, B => N_1144, S => \s2_entry_0[1]\, Y - => N_1178); - - \r.s2_data_RNI5O9D[8]\ : OR2B - port map(A => \data[8]\, B => s2_flush_0, Y => \TYP_1_0[0]\); - - \r.s2_data[12]\ : DFN1E1 - port map(D => data_0_12, CLK => lclk_c, E => s1finished_1, - Q => \data[12]\); - - \r.s2_flush_1_RNIJGG9\ : OR3 - port map(A => trans_op_0, B => s2_flush_1, C => - maddress(14), Y => N_3044); - - \r.walk_fault.fault_inv\ : DFN1E1 - port map(D => N_31, CLK => lclk_c, E => N_2276, Q => - fault_inv_0); - - \r.nrep[2]\ : DFN1E1 - port map(D => N_2512, CLK => lclk_c, E => nrepe, Q => - \nrep[2]\); - - \r.s2_data_RNI7HHE[9]\ : OR2B - port map(A => \data[9]\, B => s2_flush, Y => \TYP_1[1]\); - - \r.walk_transdata.data_RNIRCRU3[25]\ : AO1A - port map(A => \adata[21]\, B => N_3060, C => N_2927, Y => - \data_1_i_m2_i_0[25]\); - - \r.walk_transdata.data_RNO[25]\ : MX2 - port map(A => \data[25]\, B => hrdata_0_21, S => N_2571, Y - => N_2738); - - \r.walk_transdata.data[31]\ : DFN1E0 - port map(D => \data_2[31]\, CLK => lclk_c, E => - cache_0_sqmuxa, Q => \data_1[31]\); - - \r.s2_read_RNIMCLB\ : OR2 - port map(A => \fault_read\, B => \walk_use_0\, Y => - fault_pro_1_m_0_4_0); - - \r.s2_data[3]\ : DFN1E1 - port map(D => un1_m0_2_78, CLK => lclk_c, E => s1finished, - Q => \data[3]\); - - \r.walk_transdata.data_RNI9S3D[24]\ : NOR2A - port map(A => walk_use_1, B => \data_0[24]\, Y => N_3011); - - \r.s2_ctx[4]\ : DFN1E1 - port map(D => ctx(4), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[4]\); - - GND_i : GND - port map(Y => \GND\); - - \r.s2_entry_0_RNILCGF[1]\ : MX2 - port map(A => N_1108, B => N_1142, S => \s2_entry_0[1]\, Y - => N_1176); - - \r.s2_flush_0_RNI64RC1_0\ : NOR2 - port map(A => N_2530, B => N_93, Y => s1finished); - - \r.s2_data_RNIPHRR[29]\ : MX2C - port map(A => N_701, B => \data_0[29]\, S => s2_flush_1, Y - => N_661); - - \r.s2_entry_0_RNIHDGF[1]\ : MX2 - port map(A => N_1115, B => N_1149, S => \s2_entry_0[1]\, Y - => N_1183); - - \r.s2_entry_0_RNI53UP[1]\ : MX2 - port map(A => N_1121, B => N_1155, S => \s2_entry_0[1]\, Y - => N_1189); - - \r.s2_ctx[6]\ : DFN1E1 - port map(D => ctx(6), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[6]\); - - \tlbcam0.5.tag0\ : mmutlbcam_2_0_4 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1(5) => \tlbcam_write_op_1_1[5]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0 => hrdata_0_d0, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_7 => hrdata_7, - tlbcam_write_op_1(5) => \tlbcam_write_op_1[5]\, - pteout_0(4) => \pteout_2[4]\, pteout_0(3) => - \pteout_2[3]\, pteout_0(2) => \pteout_2[2]\, - cam_hitaddr_18(1) => \cam_hitaddr_18[1]\, LVL_0(0) => - \LVL_2[0]\, TYP_1(2) => \TYP_1[2]\, TYP_1(1) => - \TYP_1[1]\, TYP_1(0) => \TYP_1[0]\, - tlbcam_write_op_1_0(5) => \tlbcam_write_op_1_0[5]\, - I1_1_i_0_0(0) => \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => - \I3_1_i_0_0[2]\, ctx(7) => ctx(7), ctx(6) => ctx(6), - ctx(5) => ctx(5), ctx(4) => ctx(4), ctx(3) => ctx(3), - ctx(2) => ctx(2), ctx(1) => ctx(1), ctx(0) => ctx(0), - I2_1(5) => \I2_1[5]\, I2_1(4) => \I2_1[4]\, I2_1(3) => - \I2_1[3]\, I2_1(2) => \I2_1[2]\, I2_1(1) => \I2_1[1]\, - I2_1(0) => \I2_1[0]\, I1_1_5 => \I1_1[6]\, I1_1_2 => - \I1_1[3]\, I1_1_0 => \I1_1[1]\, I1_1_1 => \I1_1[2]\, - I1_1_3 => \I1_1[4]\, I1_1_6 => \I1_1[7]\, I3_1_5 => - \I3_1[5]\, I3_1_4 => \I3_1[4]\, I3_1_0 => \I3_1[0]\, - I3_1_i(3) => \I3_1_i[3]\, LVL(1) => \LVL_2[1]\, LVL(0) - => \LVL_3[0]\, TYP_1_0(0) => \TYP_1_0[0]\, - cam_hitaddr_21_1(0) => \cam_hitaddr_21_1[0]\, - pteout_m_i_8 => \pteout_m_i_2[17]\, pteout_m_i_18 => - \pteout_m_i_2[27]\, pteout_m_i_6 => \pteout_m_i_3[15]\, - pteout_m_i_5 => \pteout_m_i_2[14]\, pteout_m_i_11 => - \pteout_m_i_2[20]\, pteout_m_i_10 => \pteout_m_i_2[19]\, - pteout_m_i_9 => \pteout_m_i_3[18]\, pteout_m_i_7 => - \pteout_m_i_3[16]\, pteout_m_i_4 => \pteout_m_i_2[13]\, - pteout_m_i_1 => \pteout_m_i_2[10]\, pteout_m_i_0_d0 => - \pteout_m_i_2[9]\, pteout_m_i_3 => \pteout_m_i_2[12]\, - un2_wb_acc_iv_1_11 => \un2_wb_acc_iv_1[20]\, - un2_wb_acc_iv_1_10 => \un2_wb_acc_iv_1[19]\, - un2_wb_acc_iv_1_9 => \un2_wb_acc_iv_1[18]\, - un2_wb_acc_iv_1_7 => \un2_wb_acc_iv_1[16]\, - un2_wb_acc_iv_1_4 => \un2_wb_acc_iv_1[13]\, - un2_wb_acc_iv_1_1 => \un2_wb_acc_iv_1[10]\, - un2_wb_acc_iv_1_0 => \un2_wb_acc_iv_1[9]\, - un2_wb_acc_iv_1_3 => \un2_wb_acc_iv_1[12]\, - data_1_3_i_a3_0_1(12) => \data_1_3_i_a3_0_1[12]\, - data_1_3_i_a3_1_0 => \data_1_3_i_a3_1[27]\, - data_1_3_i_a3_1_2 => \data_1_3_i_a3_1[29]\, - un1_cam_hitaddr(58) => \un1_cam_hitaddr[58]\, pteout_31 - => \pteout_2[31]\, pteout_30 => \pteout_2[30]\, - pteout_29 => \pteout_2[29]\, pteout_28 => \pteout_2[28]\, - pteout_1 => \pteout_2[1]\, pteout_0_d0 => \pteout_2[0]\, - pteout_7 => \pteout_2[7]\, pteout_17 => \pteout_2[17]\, - pteout_4 => \pteout_3[4]\, pteout_3 => \pteout_3[3]\, - pteout_2 => \pteout_3[2]\, pteout_27 => \pteout_2[27]\, - pteout_26 => \pteout_2[26]\, pteout_24 => \pteout_2[24]\, - pteout_22 => \pteout_2[22]\, pteout_21 => \pteout_2[21]\, - pteout_15 => \pteout_2[15]\, pteout_14 => \pteout_2[14]\, - pteout_6 => \pteout_2[6]\, pteout_20 => \pteout_2[20]\, - pteout_19 => \pteout_2[19]\, pteout_18 => \pteout_2[18]\, - pteout_16 => \pteout_2[16]\, pteout_13 => \pteout_2[13]\, - pteout_10 => \pteout_2[10]\, pteout_9 => \pteout_2[9]\, - pteout_12 => \pteout_2[12]\, pteout_8 => \pteout_2[8]\, - pteout_23 => \pteout_2[23]\, pteout_25 => \pteout_2[25]\, - pteout_11 => \pteout_2[11]\, pteout_m_i_0_18 => - \pteout_m_i_0_3[26]\, pteout_m_i_0_16 => - \pteout_m_i_0_2[24]\, pteout_m_i_0_14 => - \pteout_m_i_0_2[22]\, pteout_m_i_0_13 => - \pteout_m_i_0_2[21]\, pteout_m_i_0_0 => - \pteout_m_i_0_3[8]\, pteout_m_i_0_15 => - \pteout_m_i_0_3[23]\, pteout_m_i_0_17 => - \pteout_m_i_0_2[25]\, pteout_m_i_0_3 => - \pteout_m_i_0_2[11]\, N_78 => N_78, N_262 => N_262, N_264 - => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, N_1471 - => N_1471, NEEDSYNC => NEEDSYNC_1, N_1470 => N_1470, - s2_flush => s2_flush, un1_rst_i_0 => \un1_rst_i_0\, - N_1469 => N_1469, N_1497 => N_1497, s2_flush_1 => - s2_flush_1, trans_op => trans_op, N_2483 => N_2483, N_661 - => N_661, N_3046 => N_3046, N_3043 => N_3043, - WBNEEDSYNC_m => WBNEEDSYNC_m_2, N_61 => N_61, hit_1 => - hit_0, hit_0 => hit, hit => hit_2, M_1 => M_1); - - \r.s2_entry_0_RNILDGF[1]\ : MX2 - port map(A => N_1116, B => N_1150, S => \s2_entry_0[1]\, Y - => N_1184); - - \r.s2_tlbstate_RNIMSES[0]\ : OR2A - port map(A => N_2544, B => N_89, Y => N_2547); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.walk_transdata.data_RNI7K3D[22]\ : OR2B - port map(A => walk_use_1, B => \data[22]\, Y => N_3036); - - \r.s2_entry_RNI21VA7[0]\ : AOI1B - port map(A => fault_pro_5_m_0_3, B => fault_pro_5_m_0_2, C - => \un1_dtlb0_1_m_0_i[45]\, Y => \fault_pro_1_iv_2\); - - \r.walk_transdata.data[0]\ : DFN1E0 - port map(D => \data[0]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[0]\); - - \p0.tlbcam_tagin.I3_1_i_0_RNO_1[1]\ : OR2A - port map(A => s2_flush_0, B => \data_0[13]\, Y => N_3039); - - \p0.tlbcam_tagin.I3_1_i_0_RNO[1]\ : AND2 - port map(A => N_3041, B => N_3039, Y => \I3_1_i_0_0[1]\); - - \r.s2_entry_1_RNIDUIN1[0]\ : MX2 - port map(A => N_1189, B => N_1291, S => \s2_entry_1[0]\, Y - => \adata[21]\); - - \r.s2_entry_1[0]\ : DFN1E0 - port map(D => \s2_entry_1_0[0]\, CLK => lclk_c, E => N_53, - Q => \s2_entry_1[0]\); - - \r.s2_data_RNI2DON[23]\ : NOR2A - port map(A => N_3063, B => \data_0[23]\, Y => N_2941); - - \r.walk_transdata.data_RNI904D[25]\ : NOR2A - port map(A => \walk_use_0\, B => \data_1[25]\, Y => N_2927); - - \r.s2_entry_RNIBQRC1[0]\ : MX2 - port map(A => N_1188, B => N_1290, S => \s2_entry[0]\, Y - => \adata[20]\); - - \r.s2_data[26]\ : DFN1E1 - port map(D => data_0_26, CLK => lclk_c, E => s1finished_1, - Q => \data[26]\); - - \tlbcam0.4.tag0\ : mmutlbcam_2_0 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1_0(4) => \tlbcam_write_op_1_1_0[4]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0 => hrdata_0_d0, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_7 => hrdata_7, - tlbcam_write_op_1(4) => \tlbcam_write_op_1[4]\, - un1_cam_hitaddr_1_0 => \un1_cam_hitaddr_1[56]\, - un1_cam_hitaddr_1_6 => \un1_cam_hitaddr_1[62]\, - un1_cam_hitaddr_1_5 => \un1_cam_hitaddr_1[61]\, - un1_cam_hitaddr_0 => \un1_cam_hitaddr[56]\, - un1_cam_hitaddr_2 => \un1_cam_hitaddr[58]\, - un1_cam_hitaddr_4 => \un1_cam_hitaddr[60]\, - un1_cam_hitaddr_5 => \un1_cam_hitaddr[61]\, - un1_cam_hitaddr_6 => \un1_cam_hitaddr[62]\, - un1_cam_hitaddr_1_d0 => \un1_cam_hitaddr[57]\, - pteout_0(4) => \pteout[4]\, pteout_0(3) => \pteout[3]\, - pteout_0(2) => \pteout[2]\, cam_hitaddr_18(1) => - \cam_hitaddr_18[1]\, LVL_0(1) => \LVL[1]\, LVL_0(0) => - \LVL[0]\, TYP_1(2) => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, - TYP_1_0(0) => \TYP_1_0[0]\, tlbcam_write_op_1_0(4) => - \tlbcam_write_op_1_0[4]\, I1_1_i_0_0(0) => - \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, - pteout_31 => \pteout[31]\, pteout_30 => \pteout[30]\, - pteout_29 => \pteout[29]\, pteout_28 => \pteout[28]\, - pteout_1 => \pteout[1]\, pteout_0_d0 => \pteout[0]\, - pteout_7 => \pteout[7]\, pteout_17 => \pteout[17]\, - pteout_4 => \pteout_0[4]\, pteout_3 => \pteout_0[3]\, - pteout_2 => \pteout_0[2]\, pteout_27 => \pteout[27]\, - pteout_6 => \pteout[6]\, pteout_26 => \pteout[26]\, - pteout_25 => \pteout[25]\, pteout_24 => \pteout[24]\, - pteout_23 => \pteout[23]\, pteout_22 => \pteout[22]\, - pteout_21 => \pteout[21]\, pteout_20 => \pteout[20]\, - pteout_19 => \pteout[19]\, pteout_18 => \pteout[18]\, - pteout_16 => \pteout[16]\, pteout_15 => \pteout[15]\, - pteout_14 => \pteout[14]\, pteout_13 => \pteout[13]\, - pteout_12 => \pteout[12]\, pteout_11 => \pteout[11]\, - pteout_10 => \pteout[10]\, pteout_9 => \pteout[9]\, - pteout_8 => \pteout[8]\, ctx(4) => ctx(4), I3_1_i(3) => - \I3_1_i[3]\, ctx_0_7 => ctx_0(7), ctx_0_5 => ctx_0(5), - ctx_0_3 => ctx_0(3), ctx_0_1 => ctx_0(1), ctx_0_0 => - ctx_0(0), ctx_0_2 => ctx_0(2), ctx_0_6 => ctx_0(6), - I1_1_5 => \I1_1[6]\, I1_1_2 => \I1_1[3]\, I1_1_0 => - \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_3 => \I1_1[4]\, - I1_1_6 => \I1_1[7]\, I2_1(5) => \I2_1[5]\, I2_1(4) => - \I2_1[4]\, I2_1(3) => \I2_1[3]\, I2_1(2) => \I2_1[2]\, - I2_1(1) => \I2_1[1]\, I2_1(0) => \I2_1[0]\, I3_1_4 => - \I3_1[4]\, I3_1_0 => \I3_1[0]\, I3_1_5 => \I3_1[5]\, - LVL(1) => \LVL_0[1]\, LVL(0) => \LVL_0[0]\, pteout_m_i_8 - => \pteout_m_i[17]\, pteout_m_i_18 => \pteout_m_i[27]\, - pteout_m_i_11 => \pteout_m_i[20]\, pteout_m_i_10 => - \pteout_m_i[19]\, pteout_m_i_9 => \pteout_m_i[18]\, - pteout_m_i_7 => \pteout_m_i[16]\, pteout_m_i_6 => - \pteout_m_i[15]\, pteout_m_i_4 => \pteout_m_i[13]\, - pteout_m_i_3 => \pteout_m_i[12]\, pteout_m_i_1 => - \pteout_m_i[10]\, pteout_m_i_0_d0 => \pteout_m_i[9]\, - pteout_m_i_5 => \pteout_m_i[14]\, un2_wb_acc_iv_2(14) => - \un2_wb_acc_iv_2[14]\, pteout_m_i_0_18 => - \pteout_m_i_0[26]\, pteout_m_i_0_15 => \pteout_m_i_0[23]\, - pteout_m_i_0_13 => \pteout_m_i_0[21]\, pteout_m_i_0_0_d0 - => \pteout_m_i_0[8]\, pteout_m_i_0_17 => - \pteout_m_i_0[25]\, data_1_3_i_a3_2(29) => - \data_1_3_i_a3_2[29]\, data_1_3_i_a3_3_2 => - \data_1_3_i_a3_3[28]\, data_1_3_i_a3_3_0 => - \data_1_3_i_a3_3[26]\, data_1_3_i_a3_5_2 => - \data_1_3_i_a3_5[28]\, data_1_3_i_a3_5_0 => - \data_1_3_i_a3_5[26]\, pteout_m_i_0_0_13 => - \pteout_m_i_0[24]\, pteout_m_i_0_0_11 => - \pteout_m_i_0[22]\, pteout_m_i_0_0_0 => - \pteout_m_i_0[11]\, data_1_3_i_a3_0_2(15) => - \data_1_3_i_a3_0_2[15]\, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, - N_1496 => N_1496, N_1468 => N_1468, NEEDSYNC => - NEEDSYNC_3, N_1467 => N_1467, s2_flush => s2_flush, - un1_rst_i_0 => \un1_rst_i_0\, N_1466 => N_1466, N_1495 - => N_1495, trans_op => trans_op, s2_flush_1 => - s2_flush_1, N_2483 => N_2483, M_1 => M_1, N_661 => N_661, - N_3046 => N_3046, N_3043 => N_3043, N_61 => N_61, hit_1 - => hit, hit_0 => hit_0, N_2551 => N_2551, - un1_cam_hitaddr_4_0 => un1_cam_hitaddr_4_0, WBNEEDSYNC_m - => WBNEEDSYNC_m, hit => hit_1); - - \r.s2_entry_RNIG3141[0]\ : NOR2A - port map(A => \adata[4]\, B => \adata[3]\, Y => - fault_pro_5_m_0_3); - - \r.s2_data_RNIOMAJ3[23]\ : NOR3 - port map(A => N_2943, B => N_2940, C => N_2941, Y => N_236); - - \r.s2_tlbstate_RNILVMNK[1]\ : OR3A - port map(A => twowner_0(0), B => \s2_tlbstate[1]\, C => - \N_2532\, Y => N_2488); - - \r.walk_transdata.data[23]\ : DFN1E0 - port map(D => N_693, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[23]\); - - \r.s2_tlbstate_RNIBBSOK[1]\ : OR2B - port map(A => rst, B => cache_0_sqmuxa_0, Y => nrepe); - - \r.s2_data_RNI30FF2[21]\ : NOR3 - port map(A => N_3009, B => N_3006, C => N_3007, Y => N_419); - - \r.s2_data[15]\ : DFN1E1 - port map(D => data_0_15, CLK => lclk_c, E => s1finished_1, - Q => \data[15]\); - - \r.s2_data_RNIT4SP5[26]\ : OA1C - port map(A => N_3059, B => \data[26]\, C => - \data_1_i_m2_i_0[26]\, Y => N_192); - - \r.s2_data_RNI6HHE[8]\ : OR2B - port map(A => \data[8]\, B => s2_flush, Y => \TYP_1[0]\); - - \r.s2_entry_1_RNI3EJF[1]\ : MX2 - port map(A => N_1216, B => N_1250, S => \s2_entry_1[1]\, Y - => N_1284); - - \r.s2_data_RNIV2D32[27]\ : OA1C - port map(A => N_3059, B => \data_0[27]\, C => - \data_1_i_m2_i_0[27]\, Y => N_293); - - \r.s2_data_RNIJSQP5[25]\ : OA1C - port map(A => N_3059, B => \data[25]\, C => - \data_1_i_m2_i_0[25]\, Y => N_190); - - \r.s2_data_RNI75PN[19]\ : NOR2A - port map(A => N_3063, B => \data_0[19]\, Y => N_2999); - - \r.walk_transdata.data[14]\ : DFN1E0 - port map(D => N_37, CLK => lclk_c, E => cache_0_sqmuxa_0, Q - => \data_1[14]\); - - \r.s2_tlbstate_RNITSPN91[1]\ : OR2 - port map(A => sync_isw_RNII96B91, B => N_2522, Y => - s2_tlbstate_3); - - \cam_addr[12]\ : MX2 - port map(A => maddress(12), B => data_0_12, S => trans_op_0, - Y => \cam_addr[12]_net_1\); - - \r.s2_entry_0_RNIHUSSN2_6[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[1]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_0[0]\); - - \r.s2_tlbstate_RNO[1]\ : AOI1B - port map(A => \s2_tlbstate_ns_0_0_0[1]\, B => N_2509, C => - rst, Y => \s2_tlbstate_nss[1]\); - - \r.s2_data[28]\ : DFN1E1 - port map(D => data_0_28, CLK => lclk_c, E => s1finished, Q - => \data[28]\); - - \r.s2_entry_0_RNI73UP[1]\ : MX2 - port map(A => N_1129, B => N_1163, S => \s2_entry_0[1]\, Y - => N_1197); - - \r.walk_transdata.data[21]\ : DFN1E0 - port map(D => N_691, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[21]\); - - \r.walk_fault.fault_pro_RNO_0\ : NOR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => \fault_read\, Y => fault_pro_1_iv_0_a2_0_0); - - \r.s2_entry_RNIG8073[0]\ : NOR2A - port map(A => N_3060, B => \adata[20]\, Y => N_3010); - - \r.s2_entry_1_RNIOLEP[1]\ : MX2 - port map(A => N_1203, B => N_1237, S => \s2_entry_1[1]\, Y - => N_1271); - - \r.walk_transdata.data_RNO[29]\ : MX2 - port map(A => \data_0[29]\, B => N_78_0, S => N_2571, Y => - N_2747); - - \r.s2_entry_1_RNII30Q[1]\ : MX2 - port map(A => N_1220, B => N_1254, S => \s2_entry_1[1]\, Y - => N_1288); - - \r.s2_entry_1_RNI7HM21[0]\ : MX2 - port map(A => N_1176, B => N_1278, S => \s2_entry_1[0]\, Y - => \adata[8]\); - - \r.s2_entry_RNIKQOQN2_2[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[1]\, C => \s2_entry[0]\, Y => - \tlbcam_write_op_1[0]\); - - \r.s2_entry_RNIKQOQN2_0[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry[0]\, C => - \tlbcam_write_op_1_1[1]\, Y => \tlbcam_write_op_1[1]\); - - \r.s2_entry[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry[2]\); - - \r.s2_data[6]\ : DFN1E1 - port map(D => un1_m0_2_81, CLK => lclk_c, E => s1finished, - Q => \data[6]\); - - \r.walk_fault.fault_pro_RNO_3\ : NOR3B - port map(A => \s2_tlbstate[0]\, B => hrdata_0_4, C => - \s2_tlbstate[1]\, Y => fault_pro_1_iv_0_a2_0); - - \r.s2_data_RNIQU0N1[16]\ : NOR2 - port map(A => \data_0[16]\, B => N_3066, Y => N_2912); - - \r.s2_data_RNINBVQ1[24]\ : NOR2A - port map(A => N_3059, B => \data[24]\, Y => N_3012); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.s2_flush_0_RNIB92J1\ : NOR2B - port map(A => \s1finished_0\, B => flush_op, Y => - s2_flush_1_0); - - \r.s2_data_RNID4TM[15]\ : MX2C - port map(A => \cam_addr[15]_net_1\, B => \data[15]\, S => - s2_flush_0, Y => \I3_1_i[3]\); - - \r.s2_entry_RNI3NF9[1]\ : MX2 - port map(A => N_1235, B => N_1269, S => \s2_entry[1]\, Y - => N_1303); - - \p0.un9_twneedsync_i_a2_i_o2_i_a4\ : OR2B - port map(A => un9_twneedsync_i_a2_i_o2_i_a4_0, B => - fault_trans_i_2, Y => \N_86_i\); - - \r.s2_entry_1_RNI6K2Q[1]\ : MX2 - port map(A => N_1225, B => N_1259, S => \s2_entry_1[1]\, Y - => N_1293); - - \r.s2_data_RNIR2442[12]\ : AO1D - port map(A => \data[12]\, B => N_3066, C => N_2904, Y => - \data_1_i_m2_i_0[12]\); - - \r.walk_transdata.data[7]\ : DFN1E0 - port map(D => \data[7]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[7]\); - - \r.s2_entry_RNIKH0I[0]\ : MX2 - port map(A => N_1171, B => N_1273, S => \s2_entry[0]\, Y - => \adata[3]\); - - \r.walk_use_RNIHJTM_0\ : NOR2 - port map(A => \un1_acc[33]\, B => walk_use, Y => N_3062); - - \cam_addr[31]\ : MX2 - port map(A => maddress(31), B => data_0_31, S => trans_op_0, - Y => \cam_addr[31]_net_1\); - - \r.s2_tlbstate_RNI9HRIO2[0]\ : OR2A - port map(A => N_2547, B => dr1write_0_sqmuxa, Y => N_25); - - \r.s2_entry_RNIC9CD[1]\ : MX2 - port map(A => N_1113, B => N_1147, S => \s2_entry[1]\, Y - => N_1181); - - \r.s2_entry_1_RNIDJN21[0]\ : MX2 - port map(A => N_1184, B => N_1286, S => \s2_entry_1[0]\, Y - => \adata[16]\); - - \cam_addr[22]\ : MX2 - port map(A => maddress(22), B => data_1_10, S => trans_op, - Y => \cam_addr[22]_net_1\); - - \r.s2_tlbstate_RNO[0]\ : AOI1B - port map(A => \s2_tlbstate_ns_0_0_0[0]\, B => N_2539, C => - rst, Y => \s2_tlbstate_nss[0]\); - - \r.s2_entry_1_RNI8FMN1[0]\ : MX2 - port map(A => N_1192, B => N_1294, S => \s2_entry_1[0]\, Y - => \adata[24]\); - - \p0.tlbcam_tagin.I3_1_i_0[1]\ : NAND2 - port map(A => N_3040, B => \I3_1_i_0_0[1]\, Y => N_61); - - \r.s2_data[16]\ : DFN1E1 - port map(D => data_1_4, CLK => lclk_c, E => s1finished_1, Q - => \data_0[16]\); - - \r.walk_transdata.data_RNIDG4D[19]\ : NOR2A - port map(A => walk_use_1, B => \data[19]\, Y => N_2998); - - \r.s2_read_RNI0BTI2\ : NOR3 - port map(A => N_2241, B => fault_pro_1_m_0_4_0, C => - \adata[2]\, Y => fault_pro_1_m_0_4); - - \p0.tlbcam_tagin.I3_1_i_0_RNO_0[1]\ : OR3 - port map(A => trans_op_0, B => s2_flush_0, C => - maddress(13), Y => N_3041); - - \r.walk_fault.fault_trans_RNIH26E2\ : OAI1 - port map(A => \fault_inv\, B => \fault_trans\, C => - un1_m0_2_0(35), Y => ft_1_i_a2_0(0)); - - \r.s2_entry_0_RNIDDGF[1]\ : MX2 - port map(A => N_1114, B => N_1148, S => \s2_entry_0[1]\, Y - => N_1182); - - \r.walk_fault.fault_pro\ : DFN1E1 - port map(D => fault_pro_1, CLK => lclk_c, E => N_25, Q => - fault_pro); - - \r.s2_needsync\ : DFN1E1 - port map(D => s2_needsync, CLK => lclk_c, E => s1finished, - Q => s2_needsync_1); - - \r.s2_entry_0_RNIK30Q[1]\ : MX2 - port map(A => N_1124, B => N_1158, S => \s2_entry_0[1]\, Y - => N_1192); - - \r.s2_data_RNIV0ON[20]\ : NOR2A - port map(A => N_3063, B => \data_0[20]\, Y => N_3003); - - \r.walk_transdata.data[13]\ : DFN1E0 - port map(D => N_2735, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data_1[13]\); - - \r.s2_flush_RNI97TV\ : OA1B - port map(A => N_2543, B => s2_flush, C => N_89, Y => N_2552); - - \r.s2_entry_1_RNITTSH3[0]\ : OR2B - port map(A => \adata[26]\, B => N_3060, Y => N_2922); - - \r.s2_tlbstate[1]\ : DFN1 - port map(D => \s2_tlbstate_nss[1]\, CLK => lclk_c, Q => - \s2_tlbstate[1]\); - - \r.walk_transdata.data[28]\ : DFN1E0 - port map(D => \data_3[28]\, CLK => lclk_c, E => - cache_0_sqmuxa, Q => \data_2[28]\); - - \r.s2_su\ : DFN1E1 - port map(D => su, CLK => lclk_c, E => s1finished, Q => - \fault_su\); - - \r.s2_entry_1_RNI8TIF[1]\ : MX2 - port map(A => N_1210, B => N_1244, S => \s2_entry_1[1]\, Y - => N_1278); - - \r.s2_data_RNIJL0T4[13]\ : OA1C - port map(A => N_3065, B => \adata[9]\, C => - \data_1_i_m2_i_0[13]\, Y => N_2887); - - \r.s2_entry_0_RNIQ23VN2_1[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[2]\, Y => - \tlbcam_write_op_1_0[3]\); - - \r.s2_data[18]\ : DFN1E1 - port map(D => data_0_18, CLK => lclk_c, E => s1finished_1, - Q => \data[18]\); - - \p0.transdata.data_1_i_m2_i_a2_RNI5BD8[27]\ : OR2 - port map(A => N_2957, B => N_2959, Y => - \data_1_i_m2_i_0[27]\); - - \r.walk_use_0_RNIS8NH3\ : OR3A - port map(A => \un1_dtlb0_1_m_0_1[45]\, B => \adata[3]\, C - => \adata[2]\, Y => \un1_dtlb0_1_m_0_i[45]\); - - \r.walk_transdata.data[11]\ : DFN1E0 - port map(D => \data[11]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[11]\); - - \r.walk_fault.fault_pro_RNO_2\ : OAI1 - port map(A => \fault_read\, B => \fault_su\, C => - hrdata_0_2, Y => N_97); - - \r.s2_entry_0_RNI0K1Q[1]\ : MX2 - port map(A => N_1127, B => N_1161, S => \s2_entry_0[1]\, Y - => N_1195); - - \p0.tlb_checkfault.un54_fault_pro_m_0\ : OR2 - port map(A => su, B => read, Y => un54_fault_pro_m_0); - - \r.walk_transdata.data_RNO[28]\ : MX2 - port map(A => \data[28]\, B => hrdata_0_24, S => N_2571, Y - => \data_3[28]\); - - \r.s2_data[5]\ : DFN1E1 - port map(D => un1_m0_2_80, CLK => lclk_c, E => s1finished, - Q => \data[5]\); - - \r.walk_transdata.data[25]\ : DFN1E0 - port map(D => N_2738, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data_1[25]\); - - \tlbcam0.1.tag0\ : mmutlbcam_2_0_5 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - hrdata_0_27 => hrdata_0_27, hrdata_0_26 => hrdata_0_26, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_21 => hrdata_0_21, hrdata_0_18 => hrdata_0_18, - hrdata_0_16 => hrdata_0_16, hrdata_0_15 => hrdata_0_15, - hrdata_0_12 => hrdata_0_12, hrdata_0_8 => hrdata_0_8, - hrdata_0_1 => hrdata_0_1, hrdata_0_0 => hrdata_0_0, - hrdata_0_4 => hrdata_0_4, hrdata_0_3 => hrdata_0_3, - hrdata_0_2 => hrdata_0_2, tlbcam_write_op_1_1_0(1) => - \tlbcam_write_op_1_1_0[1]\, data(31) => \data[31]\, - data(30) => \data[30]\, data(29) => \data_0[29]\, - data(28) => \data[28]\, data(27) => \data_0[27]\, - data(26) => \data[26]\, data(25) => \data[25]\, data(24) - => \data[24]\, data(23) => \data_0[23]\, data(22) => - \data_0[22]\, data(21) => \data_0[21]\, data(20) => - \data_0[20]\, data(19) => \data_0[19]\, data(18) => - \data[18]\, data(17) => \data_1[17]\, data(16) => - \data_0[16]\, data(15) => \data[15]\, data(14) => - \data[14]\, data(13) => \data_0[13]\, data(12) => - \data[12]\, s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => - \s2_ctx[6]\, s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => - \s2_ctx[4]\, s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => - \s2_ctx[2]\, s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => - \s2_ctx[0]\, hrdata_24 => hrdata_31, hrdata_23 => - hrdata_30, hrdata_22 => hrdata_29, hrdata_21 => hrdata_28, - hrdata_17 => hrdata_24, hrdata_10 => hrdata_17, hrdata_7 - => hrdata_14, hrdata_6 => hrdata_13, hrdata_4 => - hrdata_11, hrdata_3 => hrdata_10, hrdata_2 => hrdata_9, - hrdata_0_d0 => hrdata_7, tlbcam_write_op_1(1) => - \tlbcam_write_op_1[1]\, I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, - un1_cam_hitaddr_1_0 => \un1_cam_hitaddr_1[56]\, - un1_cam_hitaddr_1_5 => \un1_cam_hitaddr_1[61]\, - un1_cam_hitaddr_1_6 => \un1_cam_hitaddr_1[62]\, TYP_1(2) - => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, TYP_1(0) => - \TYP_1[0]\, s2_entry(2) => \s2_entry[2]\, pteout_1(4) => - \pteout_3[4]\, pteout_1(3) => \pteout_3[3]\, pteout_1(2) - => \pteout_4[2]\, LVL_1(0) => \LVL_4[0]\, - tlbcam_write_op_1_0(1) => \tlbcam_write_op_1_0[1]\, - I1_1_i_0_0(0) => \I1_1_i_0_0[0]\, pteout_m_i_8 => - \pteout_m_i_1[17]\, pteout_m_i_18 => \pteout_m_i_1[27]\, - pteout_m_i_11 => \pteout_m_i_1[20]\, pteout_m_i_10 => - \pteout_m_i_1[19]\, pteout_m_i_9 => \pteout_m_i_1[18]\, - pteout_m_i_7 => \pteout_m_i_1[16]\, pteout_m_i_6 => - \pteout_m_i_1[15]\, pteout_m_i_5 => \pteout_m_i_1[14]\, - pteout_m_i_4 => \pteout_m_i_1[13]\, pteout_m_i_3 => - \pteout_m_i_1[12]\, pteout_m_i_1 => \pteout_m_i_1[10]\, - pteout_m_i_0_d0 => \pteout_m_i_1[9]\, pteout_m_i_0_18 => - \pteout_m_i_0_1[26]\, pteout_m_i_0_17 => - \pteout_m_i_0_1[25]\, pteout_m_i_0_16 => - \pteout_m_i_0_1[24]\, pteout_m_i_0_15 => - \pteout_m_i_0_1[23]\, pteout_m_i_0_14 => - \pteout_m_i_0_1[22]\, pteout_m_i_0_13 => - \pteout_m_i_0_1[21]\, pteout_m_i_0_3 => - \pteout_m_i_0_1[11]\, pteout_m_i_0_0 => - \pteout_m_i_0_1[8]\, LVL_0(1) => \LVL_2[1]\, LVL_0(0) => - \LVL_3[0]\, s2_entry_3(2) => \s2_entry_3[2]\, - s2_entry_2(2) => \s2_entry_2[2]\, pteout_0_17 => - \pteout_2[17]\, pteout_0_4 => \pteout_4[4]\, pteout_0_3 - => \pteout_4[3]\, pteout_0_31 => \pteout_2[31]\, - pteout_0_30 => \pteout_2[30]\, pteout_0_29 => - \pteout_2[29]\, pteout_0_28 => \pteout_2[28]\, - pteout_0_27 => \pteout_2[27]\, pteout_0_26 => - \pteout_2[26]\, pteout_0_25 => \pteout_2[25]\, - pteout_0_24 => \pteout_2[24]\, pteout_0_23 => - \pteout_2[23]\, pteout_0_22 => \pteout_2[22]\, - pteout_0_21 => \pteout_2[21]\, pteout_0_20 => - \pteout_2[20]\, pteout_0_19 => \pteout_2[19]\, - pteout_0_18 => \pteout_2[18]\, pteout_0_16 => - \pteout_2[16]\, pteout_0_15 => \pteout_2[15]\, - pteout_0_14 => \pteout_2[14]\, pteout_0_13 => - \pteout_2[13]\, pteout_0_12 => \pteout_2[12]\, - pteout_0_11 => \pteout_2[11]\, pteout_0_10 => - \pteout_2[10]\, pteout_0_9 => \pteout_2[9]\, pteout_0_8 - => \pteout_2[8]\, pteout_0_7 => \pteout_2[7]\, - pteout_0_6 => \pteout_2[6]\, pteout_0_2 => \pteout_3[2]\, - pteout_0_1 => \pteout_2[1]\, pteout_0_0 => \pteout_2[0]\, - ctx_0_d0 => ctx(0), ctx_1 => ctx(1), ctx_4 => ctx(4), - ctx_5 => ctx(5), ctx_7 => ctx(7), ctx_3 => ctx(3), - cam_hitaddr_21_1(0) => \cam_hitaddr_21_1[0]\, - un1_cam_hitaddr(62) => \un1_cam_hitaddr[62]\, ctx_0_0 => - ctx_0(2), ctx_0_4 => ctx_0(6), I1_1_6 => \I1_1[7]\, - I1_1_3 => \I1_1[4]\, I1_1_2 => \I1_1[3]\, I1_1_0 => - \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_5 => \I1_1[6]\, - I2_1(5) => \I2_1[5]\, I2_1(4) => \I2_1[4]\, I2_1(3) => - \I2_1[3]\, I2_1(2) => \I2_1[2]\, I2_1(1) => \I2_1[1]\, - I2_1(0) => \I2_1[0]\, I3_1_5 => \I3_1[5]\, I3_1_4 => - \I3_1[4]\, I3_1_0 => \I3_1[0]\, I3_1_i(3) => \I3_1_i[3]\, - LVL_1_d0 => \LVL_4[1]\, cam_hitaddr_18(1) => - \cam_hitaddr_18[1]\, cam_hitaddr_21(0) => - \cam_hitaddr_21[0]\, N_78 => N_78, N_262 => N_262, N_264 - => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, N_3043 - => N_3043, s2_flush => s2_flush, N_1206 => N_1206, - un1_rst_i_0 => \un1_rst_i_0\, N_1219 => N_1219, N_1482 - => N_1482, N_1471 => N_1471, N_1481 => N_1481, N_1205 - => N_1205, N_1470 => N_1470, N_1480 => N_1480, N_1235 - => N_1235, N_1469 => N_1469, N_1479 => N_1479, N_1497 - => N_1497, N_1505 => N_1505, NEEDSYNC => NEEDSYNC, - s2_flush_1 => s2_flush_1, trans_op => trans_op, N_2483 - => N_2483, N_3046 => N_3046, N_1234 => N_1234, N_1233 - => N_1233, N_1232 => N_1232, N_1231 => N_1231, N_1230 - => N_1230, N_1229 => N_1229, N_1228 => N_1228, N_1227 - => N_1227, N_1226 => N_1226, N_1225 => N_1225, N_1224 - => N_1224, N_1223 => N_1223, N_1222 => N_1222, N_1221 - => N_1221, N_1220 => N_1220, N_1218 => N_1218, N_1217 - => N_1217, N_1216 => N_1216, N_1215 => N_1215, N_1214 - => N_1214, N_1213 => N_1213, N_1212 => N_1212, N_1211 - => N_1211, N_1210 => N_1210, N_1209 => N_1209, N_1208 - => N_1208, N_1204 => N_1204, N_1203 => N_1203, N_1202 - => N_1202, N_2551 => N_2551, cam_hit_all_5_sqmuxa => - cam_hit_all_5_sqmuxa, cam_hit_all_5_sqmuxa_2 => - cam_hit_all_5_sqmuxa_2, cam_hit_all_5_sqmuxa_0_a2_0 => - cam_hit_all_5_sqmuxa_0_a2_0, accexc_6_3 => accexc_6_3, - accexc_6_4 => accexc_6_4, accexc_6 => \accexc_6\, N_661 - => N_661, N_61 => N_61, un1_cam_hitaddr_4_0 => - un1_cam_hitaddr_4_0, M_1 => M_1, accexc_6_2 => accexc_6_2, - WBNEEDSYNC_m => WBNEEDSYNC_m_2); - - \r.nrep_RNI2I59O9[2]\ : MX2 - port map(A => \nrep[2]\, B => N_2551, S => \s1finished_0\, - Y => \s2_entry_1[2]\); - - \p0.tlb_mergedata.v.walk_transdata.data_3_e[17]\ : OR2 - port map(A => lvl_i_1_0(1), B => lvl_i_1(0), Y => \N_3160\); - - \r.s2_entry_RNIKQOQN2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry[0]\, C => - \tlbcam_write_op_1_1[7]\, Y => \tlbcam_write_op_1[7]\); - - \r.walk_transdata.data_RNI6O3D[13]\ : NOR2A - port map(A => \walk_use_0\, B => \data_1[13]\, Y => N_2909); - - \r.s2_tlbstate_RNIJQGC1[1]\ : AOI1 - port map(A => N_2544, B => N_2265, C => N_2522, Y => - un1_m0_2_0_d0); - - \r.s2_needsync_RNO_3\ : AOI1B - port map(A => un1_tlbcami_3_0, B => tlbcamo_needsync_0, C - => NEEDSYNC_1, Y => s2_needsync_2); - - \r.s2_entry_1[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_1_0[2]\); - - \r.s2_entry_0_RNIQ23VN2_5[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[2]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_0[2]\); - - \r.walk_transdata.data_RNIFRDL3[28]\ : MX2 - port map(A => \data_1[28]\, B => \data_2[28]\, S => - walk_use, Y => un1_m0_2_29); - - \r.s2_su_RNICMUD\ : NOR3 - port map(A => \fault_read\, B => \fault_su\, C => - \walk_use_0\, Y => fault_pro_5_m_0_0); - - \r.s2_data[7]\ : DFN1E1 - port map(D => un1_m0_2_82, CLK => lclk_c, E => s1finished, - Q => \data[7]\); - - \r.s2_tlbstate_RNIU0761[1]\ : OAI1 - port map(A => N_2265, B => \s2_tlbstate[1]\, C => N_2544, Y - => N_2241); - - \r.walk_transdata.data_RNO[13]\ : MX2 - port map(A => hrdata_0_9, B => \data_0[13]\, S => \N_3160\, - Y => N_2735); - - \r.walk_transdata.data[27]\ : DFN1E0 - port map(D => N_2740, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[27]\); - - \r.s2_entry_1_RNI9RSO2[0]\ : NOR2A - port map(A => N_3065, B => \adata[11]\, Y => N_2976); - - \r.walk_use_1_RNI5E4Q1\ : NOR2A - port map(A => N_550, B => walk_use_1, Y => N_3059); - - \r.s2_tlbstate_RNI667LK[1]\ : OR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => N_82, Y => cache_0_sqmuxa); - - \r.s2_entry_0_RNIHUSSN2_3[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[7]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_1[6]\); - - \r.walk_transdata.data_RNO[16]\ : MX2 - port map(A => hrdata_0_12, B => \data_0[16]\, S => \N_3160\, - Y => N_2736); - - \r.s2_entry_RNIBV88[1]\ : MX2 - port map(A => N_1206, B => N_1240, S => \s2_entry[1]\, Y - => N_1274); - - \r.s2_entry_1_RNIIJVP[1]\ : MX2 - port map(A => N_1131, B => N_1165, S => \s2_entry_1[1]\, Y - => N_1199); - - \r.s2_ctx[5]\ : DFN1E1 - port map(D => ctx(5), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[5]\); - - dataram : syncramZ0_1 - port map(address(31) => address(31), address(30) => - address(30), address(29) => address(29), address(28) => - address(28), address(27) => address(27), address(26) => - address(26), address(25) => address(25), address(24) => - address(24), address(23) => address(23), address(22) => - address(22), address(21) => address(21), address(20) => - address(20), address(19) => address(19), address(18) => - address(18), address(17) => address(17), address(16) => - address(16), address(15) => address(15), address(14) => - address(14), address(13) => address(13), address(12) => - address(12), address(11) => address(11), address(10) => - address(10), address(9) => address(9), address(8) => - address(8), address(7) => address(7), address(6) => - address(6), address(5) => address(5), address(4) => - address(4), address(3) => address(3), address(2) => - address(2), s2_entry(2) => \s2_entry[2]\, s2_entry(1) => - \s2_entry[1]\, s2_entry(0) => \s2_entry[0]\, twowner_1(0) - => twowner_1(0), aaddr(31) => aaddr(31), aaddr(30) => - aaddr(30), aaddr(29) => aaddr(29), aaddr(28) => aaddr(28), - aaddr(27) => aaddr(27), aaddr(26) => aaddr(26), aaddr(25) - => aaddr(25), aaddr(24) => aaddr(24), aaddr(23) => - aaddr(23), aaddr(22) => aaddr(22), aaddr(21) => aaddr(21), - aaddr(20) => aaddr(20), aaddr(19) => aaddr(19), aaddr(18) - => aaddr(18), aaddr(17) => aaddr(17), aaddr(16) => - aaddr(16), aaddr(15) => aaddr(15), aaddr(14) => aaddr(14), - aaddr(13) => aaddr(13), aaddr(12) => aaddr(12), aaddr(11) - => aaddr(11), aaddr(10) => aaddr(10), aaddr(9) => - aaddr(9), aaddr(8) => aaddr(8), aaddr(7) => aaddr(7), - aaddr(6) => aaddr(6), aaddr(5) => aaddr(5), aaddr(4) => - aaddr(4), aaddr(3) => aaddr(3), aaddr(2) => aaddr(2), - dr1write_0_sqmuxa => dr1write_0_sqmuxa, syncramZ0_1_VCC - => mmutlb_10_8_2_1_0_VCC, lclk_c => lclk_c, N_709 => - N_709); - - \tlbcam0.7.tag0\ : mmutlbcam_2_0_3 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1_0(7) => \tlbcam_write_op_1_1_0[7]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0 => hrdata_0_d0, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_7 => hrdata_7, - tlbcam_write_op_1(7) => \tlbcam_write_op_1[7]\, - cam_hitaddr_18(1) => \cam_hitaddr_18[1]\, LVL_0(1) => - \LVL_2[1]\, TYP_1(2) => \TYP_1[2]\, TYP_1(1) => - \TYP_1[1]\, TYP_1(0) => \TYP_1[0]\, - tlbcam_write_op_1_0(7) => \tlbcam_write_op_1_0[7]\, - I1_1_i_0_0(0) => \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => - \I3_1_i_0_0[2]\, ctx_0_3 => ctx_0(3), ctx_0_0 => ctx_0(0), - I3_1_i(3) => \I3_1_i[3]\, ctx_6 => ctx(7), ctx_4 => - ctx(5), ctx_3 => ctx(4), ctx_0_d0 => ctx(1), ctx_1 => - ctx(2), ctx_5 => ctx(6), I2_1(5) => \I2_1[5]\, I2_1(4) - => \I2_1[4]\, I2_1(3) => \I2_1[3]\, I2_1(2) => \I2_1[2]\, - I2_1(1) => \I2_1[1]\, I2_1(0) => \I2_1[0]\, I1_1_6 => - \I1_1[7]\, I1_1_3 => \I1_1[4]\, I1_1_2 => \I1_1[3]\, - I1_1_0 => \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_5 => - \I1_1[6]\, I3_1_4 => \I3_1[4]\, I3_1_0 => \I3_1[0]\, - I3_1_5 => \I3_1[5]\, LVL(1) => \LVL_3[1]\, LVL(0) => - \LVL_2[0]\, TYP_1_0(0) => \TYP_1_0[0]\, pteout_m_i_9 => - \pteout_m_i_2[18]\, pteout_m_i_7 => \pteout_m_i_2[16]\, - pteout_m_i_5 => \pteout_m_i[14]\, pteout_m_i_11 => - \pteout_m_i[20]\, pteout_m_i_10 => \pteout_m_i[19]\, - pteout_m_i_8 => \pteout_m_i[17]\, pteout_m_i_6 => - \pteout_m_i[15]\, pteout_m_i_4 => \pteout_m_i[13]\, - pteout_m_i_1 => \pteout_m_i[10]\, pteout_m_i_0_d0 => - \pteout_m_i[9]\, pteout_m_i_18 => \pteout_m_i[27]\, - pteout_m_i_3 => \pteout_m_i[12]\, un2_wb_acc_iv_2_11 => - \un2_wb_acc_iv_2[20]\, un2_wb_acc_iv_2_10 => - \un2_wb_acc_iv_2[19]\, un2_wb_acc_iv_2_8 => - \un2_wb_acc_iv_2[17]\, un2_wb_acc_iv_2_6 => - \un2_wb_acc_iv_2[15]\, un2_wb_acc_iv_2_4 => - \un2_wb_acc_iv_2[13]\, un2_wb_acc_iv_2_1 => - \un2_wb_acc_iv_2[10]\, un2_wb_acc_iv_2_0 => - \un2_wb_acc_iv_2[9]\, un2_wb_acc_iv_2_18 => - \un2_wb_acc_iv_2[27]\, un2_wb_acc_iv_2_3 => - \un2_wb_acc_iv_2[12]\, data_1_3_i_a3_3(30) => - \data_1_3_i_a3_3[30]\, data_1_3_i_a3_5(30) => - \data_1_3_i_a3_5[30]\, pteout_m_i_0_17 => - \pteout_m_i_0[25]\, pteout_m_i_0_16 => \pteout_m_i_0[24]\, - pteout_m_i_0_15 => \pteout_m_i_0_2[23]\, pteout_m_i_0_14 - => \pteout_m_i_0[22]\, pteout_m_i_0_3 => - \pteout_m_i_0[11]\, pteout_m_i_0_0 => \pteout_m_i_0_2[8]\, - pteout_m_i_0_18 => \pteout_m_i_0[26]\, pteout_m_i_0_13 - => \pteout_m_i_0[21]\, pteout_31 => \pteout_1[31]\, - pteout_30 => \pteout_1[30]\, pteout_29 => \pteout_1[29]\, - pteout_28 => \pteout_1[28]\, pteout_1 => \pteout_1[1]\, - pteout_0 => \pteout_1[0]\, pteout_4 => \pteout_2[4]\, - pteout_3 => \pteout_2[3]\, pteout_2 => \pteout_2[2]\, - pteout_7 => \pteout_1[7]\, pteout_6 => \pteout_1[6]\, - pteout_25 => \pteout_1[25]\, pteout_24 => \pteout_1[24]\, - pteout_23 => \pteout_1[23]\, pteout_22 => \pteout_1[22]\, - pteout_18 => \pteout_1[18]\, pteout_16 => \pteout_1[16]\, - pteout_14 => \pteout_1[14]\, pteout_11 => \pteout_1[11]\, - pteout_8 => \pteout_1[8]\, pteout_20 => \pteout_1[20]\, - pteout_19 => \pteout_1[19]\, pteout_17 => \pteout_1[17]\, - pteout_15 => \pteout_1[15]\, pteout_13 => \pteout_1[13]\, - pteout_10 => \pteout_1[10]\, pteout_9 => \pteout_1[9]\, - pteout_27 => \pteout_1[27]\, pteout_12 => \pteout_1[12]\, - pteout_26 => \pteout_1[26]\, pteout_21 => \pteout_1[21]\, - un1_cam_hitaddr(56) => \un1_cam_hitaddr[56]\, - data_1_3_i_a3_2_0 => \data_1_3_i_a3_2[25]\, N_78 => N_78, - N_262 => N_262, N_264 => N_264, N_2482 => \N_2482\, - lclk_c => lclk_c, N_1498 => N_1498, NEEDSYNC => - NEEDSYNC_2, s2_flush => s2_flush, un1_rst_i_0 => - \un1_rst_i_0\, trans_op => trans_op, s2_flush_1 => - s2_flush_1, hit => hit_0, N_2483 => N_2483, M_1 => M_1, - N_3046 => N_3046, N_3043 => N_3043, N_61 => N_61, - WBNEEDSYNC_m => WBNEEDSYNC_m_1, N_661 => N_661); - - \r.s2_needsync_RNO\ : OR3C - port map(A => NEEDSYNC_3, B => s2_needsync_3, C => - s2_needsync_4, Y => s2_needsync); - - \r.s2_entry_1_RNIEASO2[0]\ : NOR2A - port map(A => N_3065, B => \adata[8]\, Y => N_2905); - - \r.s2_entry_0_RNIHKRF[1]\ : MX2 - port map(A => N_1106, B => N_1140, S => \s2_entry_0[1]\, Y - => N_1174); - - \r.s2_entry_4[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_4[2]\); - - \r.s2_data_RNI19ON[22]\ : OR2B - port map(A => \data_0[22]\, B => N_3063, Y => N_3037); - - \r.walk_transdata.data_RNITPQ9[6]\ : MX2 - port map(A => \data[6]\, B => \data_0[6]\, S => walk_use, Y - => un1_m0_2_7); - - \r.s2_entry_0_RNI1LBP[1]\ : MX2 - port map(A => N_1100, B => N_1134, S => \s2_entry_0[1]\, Y - => N_1168); - - \r.walk_use\ : DFN1E1 - port map(D => sync_isw_RNII96B91, CLK => lclk_c, E => - s2_tlbstate_3, Q => walk_use); - - \r.walk_transdata.data_RNILEPD[3]\ : MX2 - port map(A => \data[3]\, B => \data_0[3]\, S => walk_use_1, - Y => un1_m0_2_4); - - \r.walk_transdata.data_RNI99612[18]\ : MX2 - port map(A => \data_1[18]\, B => \data_2[18]\, S => - walk_use, Y => un1_m0_2_19); - - \r.s2_entry_1_RNIK5EP[1]\ : MX2 - port map(A => N_1202, B => N_1236, S => \s2_entry_1[1]\, Y - => N_1270); - - \r.s2_data[2]\ : DFN1E1 - port map(D => un1_m0_2_77, CLK => lclk_c, E => s1finished, - Q => \data[2]\); - - \r.s2_data_RNI9CSM[30]\ : MX2C - port map(A => \cam_addr[30]_net_1\, B => \data[30]\, S => - s2_flush_0, Y => \I1_1[6]\); - - \r.walk_transdata.data_RNO[20]\ : MX2 - port map(A => hrdata_0_16, B => \data_0[20]\, S => - lvl_i_1_0(1), Y => N_700); - - \r.walk_fault.fault_inv_RNO\ : NOR3A - port map(A => inv_1_0_a2_0_a2_0, B => hrdata_0_1, C => - N_2523, Y => N_31); - - \r.walk_transdata.data[4]\ : DFN1E0 - port map(D => \data[4]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[4]\); - - \r.s2_entry_RNICI3Q[0]\ : MX2 - port map(A => N_1181, B => N_1283, S => \s2_entry[0]\, Y - => \adata[13]\); - - \r.s2_entry_1_RNI23N21[0]\ : MX2 - port map(A => N_1183, B => N_1285, S => \s2_entry_1[0]\, Y - => \adata[15]\); - - \r.s2_entry_0_RNI5DGF[1]\ : MX2 - port map(A => N_1112, B => N_1146, S => \s2_entry_0[1]\, Y - => N_1180); - - \r.s2_data[0]\ : DFN1E1 - port map(D => un1_m0_2_75, CLK => lclk_c, E => - \s1finished_0\, Q => \data[0]\); - - \cam_addr[20]\ : MX2 - port map(A => maddress(20), B => data_1_8, S => trans_op_0, - Y => \cam_addr[20]_net_1\); - - \r.walk_transdata.data[18]\ : DFN1E0 - port map(D => N_690, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data_2[18]\); - - \r.sync_isw_RNISM17\ : OR2A - port map(A => fault_mexc, B => sync_isw, Y => - cache_0_sqmuxa_0_a2_0); - - \r.s2_hm_RNIH0KH\ : NOR2A - port map(A => tlbactive, B => N_166, Y => N_2265); - - \r.s2_entry_0_RNIQ23VN2_6[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[4]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_0[4]\); - - \r.s2_data_RNI3P2P4[14]\ : OR2B - port map(A => \data_1_i_i_0[14]\, B => N_2954, Y => - un1_m0_2_15); - - \r.s2_data[20]\ : DFN1E1 - port map(D => data_1_8, CLK => lclk_c, E => s1finished_1, Q - => \data_0[20]\); - - \r.s2_data_RNIG4TM[31]\ : MX2C - port map(A => \cam_addr[31]_net_1\, B => \data[31]\, S => - s2_flush_0, Y => \I1_1[7]\); - - \r.s2_data_RNI7CIU2[19]\ : NOR3 - port map(A => N_3001, B => N_2998, C => N_2999, Y => N_415); - - \r.s2_data_RNI1LUM[19]\ : MX2C - port map(A => \cam_addr[19]_net_1\, B => \data_0[19]\, S - => s2_flush_1, Y => \I2_1[1]\); - - \r.s2_entry_1_RNI0SKL1[0]\ : MX2 - port map(A => N_1195, B => N_1297, S => \s2_entry_1[0]\, Y - => \adata[27]\); - - \r.walk_transdata.data[15]\ : DFN1E0 - port map(D => N_73, CLK => lclk_c, E => cache_0_sqmuxa_0, Q - => \data_1[15]\); - - \r.s2_entry_0_RNISGC31[0]\ : MX2 - port map(A => N_1174, B => N_1276, S => \s2_entry_0[0]\, Y - => adata_6); - - \r.s2_entry_0_RNIHUSSN2_0[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[1]\, Y => - \tlbcam_write_op_1_1_0[1]\); - - \r.s2_data_RNIGG3F5[24]\ : NOR3 - port map(A => N_3010, B => N_3011, C => N_3012, Y => N_421); - - \r.s2_data_RNIQSTM[18]\ : MX2C - port map(A => \cam_addr[18]_net_1\, B => \data[18]\, S => - s2_flush_1, Y => \I2_1[0]\); - - \r.s2_data_RNI9D0T4[12]\ : NOR2 - port map(A => \data_1_i_m2_i_0[12]\, B => N_2905, Y => - N_2886); - - \r.s2_entry_RNITAJA1[0]\ : NOR2A - port map(A => N_3062, B => \adata[17]\, Y => N_3009); - - \p0.transdata.data_1_i_a2[29]\ : NOR2A - port map(A => N_3060, B => \adata[25]\, Y => N_2977); - - \r.walk_fault.fault_pri_RNI73Q9B\ : AO1B - port map(A => un1_m0_2_0(35), B => \fault_pri\, C => - fault_pri_m, Y => \fault_pri_1\); - - \r.sync_isw_RNII96B91\ : OAI1 - port map(A => N_2509, B => cache_0_sqmuxa_0_a2_0, C => - cache_0_sqmuxa_0, Y => sync_isw_RNII96B91); - - \r.s2_entry_RNI27MJ1[0]\ : OR2 - port map(A => \un1_acc[33]\, B => \un1_acc[32]\, Y => N_552); - - \r.walk_transdata.data[26]\ : DFN1E0 - port map(D => N_2739, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data_1[26]\); - - \r.walk_transdata.cache_RNIA6TE1\ : MX2C - port map(A => \adata[7]\, B => cache, S => walk_use_1, Y - => un1_m0_2_33); - - \r.walk_transdata.data[17]\ : DFN1E0 - port map(D => \data_3[17]\, CLK => lclk_c, E => - cache_0_sqmuxa_0, Q => \data_0[17]\); - - \r.walk_fault.fault_mexc\ : DFN1E0 - port map(D => N_29, CLK => lclk_c, E => N_55, Q => - fault_mexc_1); - - \r.s2_tlbstate_RNIJKCMN2_0[1]\ : NOR2 - port map(A => cache_0_sqmuxa_0, B => \N_86_i\, Y => - dr1write_0_sqmuxa_0); - - \r.s2_entry_RNIVMF9[1]\ : MX2 - port map(A => N_1133, B => N_1167, S => \s2_entry[1]\, Y - => N_1201); - - \r.s2_entry_0_RNISHCM1[0]\ : MX2 - port map(A => N_1168, B => N_1270, S => \s2_entry_0[0]\, Y - => adata_0); - - \r.walk_use_0\ : DFN1E1 - port map(D => sync_isw_RNII96B91, CLK => lclk_c, E => - s2_tlbstate_3, Q => \walk_use_0\); - - \r.walk_transdata.data[5]\ : DFN1E0 - port map(D => \data[5]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[5]\); - - \r.walk_transdata.data_RNO[12]\ : MX2 - port map(A => hrdata_0_8, B => \data[12]\, S => \N_3160\, Y - => N_19); - - \r.walk_transdata.data[6]\ : DFN1E0 - port map(D => \data[6]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[6]\); - - \r.s2_tlbstate_RNIJKCMN2[1]\ : NOR2 - port map(A => cache_0_sqmuxa_0, B => \N_86_i\, Y => - dr1write_0_sqmuxa); - - \r.sync_isw\ : DFN1 - port map(D => sync_isw_RNO_0, CLK => lclk_c, Q => sync_isw); - - \r.s2_tlbstate_RNO_1[0]\ : OR2A - port map(A => \s2_tlbstate_ns_0_0_a2_0_0[0]\, B => \N_86_i\, - Y => N_2539); - - \r.s2_tlbstate[0]\ : DFN1 - port map(D => \s2_tlbstate_nss[0]\, CLK => lclk_c, Q => - \s2_tlbstate[0]\); - - \r.s2_entry_0_RNIT2TP[1]\ : MX2 - port map(A => N_1119, B => N_1153, S => \s2_entry_0[1]\, Y - => N_1187); - - \r.s2_hm\ : DFN1E1 - port map(D => cam_hit_all_1, CLK => lclk_c, E => s1finished, - Q => s2_hm); - - \r.walk_transdata.data_RNI5K3D[12]\ : NOR2A - port map(A => \walk_use_0\, B => \data_1[12]\, Y => N_2904); - - \r.s2_entry_1_RNIFUC31[0]\ : MX2 - port map(A => N_1175, B => N_1277, S => \s2_entry_1[0]\, Y - => \adata[7]\); - - \r.s2_entry_0_RNI9JUP[1]\ : MX2 - port map(A => N_1122, B => N_1156, S => \s2_entry_0[1]\, Y - => N_1190); - - \r.s2_data[1]\ : DFN1E1 - port map(D => un1_m0_2_76, CLK => lclk_c, E => s1finished_1, - Q => \data[1]\); - - \r.walk_transdata.data_RNI904D[15]\ : NOR2A - port map(A => walk_use_1, B => \data_1[15]\, Y => N_805); - - \r.walk_fault.fault_mexc_RNI5NF5\ : NOR2B - port map(A => walk_use, B => fault_mexc_1, Y => - fault_mexc_0); - - \r.walk_transdata.data[8]\ : DFN1E0 - port map(D => \data[8]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[8]\); - - \r.s2_su_RNI6LVI2\ : NOR3C - port map(A => \adata[4]\, B => fault_pri_1_m_1, C => - \adata[3]\, Y => fault_pri_1_m); - - \r.walk_transdata.data_RNO[14]\ : MX2 - port map(A => hrdata_0_10, B => \data[14]\, S => \N_3160\, - Y => N_37); - - \r.s2_entry_RNIML8B[1]\ : MX2 - port map(A => N_1215, B => N_1249, S => \s2_entry[1]\, Y - => N_1283); - - \r.s2_entry_1_RNICTIF[1]\ : MX2 - port map(A => N_1211, B => N_1245, S => \s2_entry_1[1]\, Y - => N_1279); - - \r.walk_fault.fault_pri_RNO\ : NOR3B - port map(A => N_2547, B => \N_2482\, C => \fault_su\, Y => - N_38); - - \r.s2_entry_1_RNIRDJF[1]\ : MX2 - port map(A => N_1214, B => N_1248, S => \s2_entry_1[1]\, Y - => N_1282); - - \r.nrep_RNO[0]\ : NOR2A - port map(A => rst, B => \nrep[0]\, Y => nrep_n0); - - \r.s2_entry_0_RNIPCGF[1]\ : MX2 - port map(A => N_1109, B => N_1143, S => \s2_entry_0[1]\, Y - => N_1177); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.walk_transdata.data_RNIPEPD[5]\ : MX2 - port map(A => \data[5]\, B => \data_0[5]\, S => walk_use_1, - Y => un1_m0_2_6); - - \r.s2_entry_2[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_2[2]\); - - \r.s2_data[10]\ : DFN1E1 - port map(D => un1_m0_2_85, CLK => lclk_c, E => - \s1finished_0\, Q => \data[10]\); - - \r.walk_transdata.data_RNO[30]\ : MX2 - port map(A => \data[30]\, B => hrdata_0_26, S => N_2571, Y - => \data_2[30]\); - - \r.s2_data[29]\ : DFN1E1 - port map(D => data_1_17, CLK => lclk_c, E => s1finished, Q - => \data_0[29]\); - - \r.walk_transdata.data_RNI8O3D[23]\ : NOR2A - port map(A => walk_use_1, B => \data[23]\, Y => N_2940); - - \r.sync_isw_RNO\ : OA1A - port map(A => N_2494, B => sync_isw, C => sync_isw_1_i_0_0, - Y => sync_isw_RNO_0); - - \tlbcam0.2.tag0\ : mmutlbcam_2_0_6 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - hrdata_0_27 => hrdata_0_27, hrdata_0_26 => hrdata_0_26, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_21 => hrdata_0_21, hrdata_0_18 => hrdata_0_18, - hrdata_0_16 => hrdata_0_16, hrdata_0_15 => hrdata_0_15, - hrdata_0_12 => hrdata_0_12, hrdata_0_8 => hrdata_0_8, - hrdata_0_0 => hrdata_0_0, hrdata_0_4 => hrdata_0_4, - hrdata_0_3 => hrdata_0_3, hrdata_0_2 => hrdata_0_2, - data_0_18 => \data[31]\, data_0_11 => \data[24]\, - data_0_10 => \data_0[23]\, data_0_6 => \data_0[19]\, - data_0_4 => \data_1[17]\, data_0_3 => \data_0[16]\, - data_0_1 => \data[14]\, data_0_0 => \data_0[13]\, - tlbcam_write_op_1_1_0(2) => \tlbcam_write_op_1_1_0[2]\, - s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - hrdata_30 => hrdata_31, hrdata_29 => hrdata_30, hrdata_28 - => hrdata_29, hrdata_27 => hrdata_28, hrdata_23 => - hrdata_24, hrdata_16 => hrdata_17, hrdata_13 => hrdata_14, - hrdata_12 => hrdata_13, hrdata_10 => hrdata_11, hrdata_9 - => hrdata_10, hrdata_8 => hrdata_9, hrdata_0_d0 => - hrdata_1, hrdata_6 => hrdata_7, tlbcam_write_op_1(2) => - \tlbcam_write_op_1[2]\, TYP_1_2 => \TYP_1[2]\, TYP_1_0_d0 - => \TYP_1[0]\, s2_entry(2) => \s2_entry[2]\, - LVL_RNIT69H911(0) => \LVL_RNIT69H911[0]\, I1_1_i_0_0(0) - => \I1_1_i_0_0[0]\, data_21 => \data[30]\, data_20 => - \data_0[29]\, data_19 => \data[28]\, data_18 => - \data_0[27]\, data_17 => \data[26]\, data_16 => - \data[25]\, data_13 => \data_0[22]\, data_12 => - \data_0[21]\, data_11 => \data_0[20]\, data_9 => - \data[18]\, data_6 => \data[15]\, data_3 => \data[12]\, - data_7 => data_1_4, data_0_d0 => \data[9]\, data_22 => - data_0_31, data_8 => data_2_0, data_15 => data_1_12, - data_5 => data_0_14, data_4 => data_13, data_14 => - data_1_11, data_10 => data_1_7, un1_m0_2_0 => un1_m0_2_91, - un1_m0_2_15 => un1_m0_2_106, un1_m0_2_1 => un1_m0_2_92, - un1_m0_2_7 => un1_m0_2_98, un1_m0_2_3 => un1_m0_2_94, - I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, LVL_0(1) => \LVL[1]\, - LVL_0(0) => \LVL[0]\, s2_entry_2(2) => \s2_entry_2[2]\, - pteout_4 => \pteout_1[4]\, pteout_3 => \pteout_1[3]\, - pteout_2 => \pteout_1[2]\, s2_entry_1(2) => - \s2_entry_1_0[2]\, pteout_0_4 => \pteout[4]\, pteout_0_17 - => \pteout_0[17]\, pteout_0_20 => \pteout_0[20]\, - pteout_0_3 => \pteout[3]\, pteout_0_31 => \pteout_0[31]\, - pteout_0_30 => \pteout_0[30]\, pteout_0_29 => - \pteout_0[29]\, pteout_0_28 => \pteout_0[28]\, - pteout_0_27 => \pteout_0[27]\, pteout_0_26 => - \pteout_0[26]\, pteout_0_25 => \pteout_0[25]\, - pteout_0_24 => \pteout_0[24]\, pteout_0_23 => - \pteout_0[23]\, pteout_0_22 => \pteout_0[22]\, - pteout_0_21 => \pteout_0[21]\, pteout_0_19 => - \pteout_0[19]\, pteout_0_18 => \pteout_0[18]\, - pteout_0_16 => \pteout_0[16]\, pteout_0_15 => - \pteout_0[15]\, pteout_0_14 => \pteout_0[14]\, - pteout_0_13 => \pteout_0[13]\, pteout_0_12 => - \pteout_0[12]\, pteout_0_11 => \pteout_0[11]\, - pteout_0_10 => \pteout_0[10]\, pteout_0_9 => - \pteout_0[9]\, pteout_0_8 => \pteout_0[8]\, pteout_0_7 - => \pteout_0[7]\, pteout_0_6 => \pteout_0[6]\, - pteout_0_2 => \pteout[2]\, pteout_0_1 => \pteout_0[1]\, - pteout_0_0 => \pteout_0[0]\, I3_1_i(3) => \I3_1_i[3]\, - tlbcam_write_op_1_0(2) => \tlbcam_write_op_1_0[2]\, - cam_hitaddr_18(1) => \cam_hitaddr_18[1]\, - un2_wb_acc_iv_4_3 => \un2_wb_acc_iv_4[12]\, - un2_wb_acc_iv_4_18 => \un2_wb_acc_iv_4[27]\, - un2_wb_acc_iv_4_0 => \un2_wb_acc_iv_4[9]\, - un2_wb_acc_iv_4_1 => \un2_wb_acc_iv_4[10]\, - un2_wb_acc_iv_4_4 => \un2_wb_acc_iv_4[13]\, - un2_wb_acc_iv_4_6 => \un2_wb_acc_iv_4[15]\, - un2_wb_acc_iv_4_10 => \un2_wb_acc_iv_4[19]\, - un2_wb_acc_iv_4_11 => \un2_wb_acc_iv_4[20]\, ctx(7) => - ctx(7), ctx(6) => ctx(6), ctx(5) => ctx(5), ctx(4) => - ctx(4), ctx(3) => ctx(3), ctx(2) => ctx(2), ctx(1) => - ctx(1), ctx(0) => ctx(0), I2_1(5) => \I2_1[5]\, I2_1(4) - => \I2_1[4]\, I2_1(3) => \I2_1[3]\, I2_1(2) => \I2_1[2]\, - I2_1(1) => \I2_1[1]\, I2_1(0) => \I2_1[0]\, I1_1_5 => - \I1_1[6]\, I1_1_2 => \I1_1[3]\, I1_1_0 => \I1_1[1]\, - I1_1_1 => \I1_1[2]\, I1_1_3 => \I1_1[4]\, I1_1_6 => - \I1_1[7]\, I3_1_4 => \I3_1[4]\, I3_1_0 => \I3_1[0]\, - I3_1_5 => \I3_1[5]\, LVL(1) => \LVL_1[1]\, LVL(0) => - \LVL_1[0]\, TYP_1_0(0) => \TYP_1_0[0]\, un2_wb_acc_iv_2_3 - => \un2_wb_acc_iv_2[12]\, un2_wb_acc_iv_2_18 => - \un2_wb_acc_iv_2[27]\, un2_wb_acc_iv_2_0 => - \un2_wb_acc_iv_2[9]\, un2_wb_acc_iv_2_1 => - \un2_wb_acc_iv_2[10]\, un2_wb_acc_iv_2_4 => - \un2_wb_acc_iv_2[13]\, un2_wb_acc_iv_2_6 => - \un2_wb_acc_iv_2[15]\, un2_wb_acc_iv_2_10 => - \un2_wb_acc_iv_2[19]\, un2_wb_acc_iv_2_11 => - \un2_wb_acc_iv_2[20]\, un2_wb_acc_iv_2_8 => - \un2_wb_acc_iv_2[17]\, pteout_m_i_1_2 => - \pteout_m_i_0[18]\, pteout_m_i_1_0 => \pteout_m_i_0[16]\, - un2_wb_acc_iv_5(18) => \un2_wb_acc_iv_5[18]\, - un2_wb_acc_iv_5(17) => \un2_wb_acc_iv_5[17]\, - un2_wb_acc_iv_5(16) => \un2_wb_acc_iv_5[16]\, - un2_wb_acc_iv_3_5 => \un2_wb_acc_iv_3[14]\, pteout_m_i_11 - => \pteout_m_i_0[20]\, pteout_m_i_10 => - \pteout_m_i_0[19]\, pteout_m_i_9 => \pteout_m_i[18]\, - pteout_m_i_8 => \pteout_m_i_0[17]\, pteout_m_i_7 => - \pteout_m_i[16]\, pteout_m_i_6 => \pteout_m_i_0[15]\, - pteout_m_i_4 => \pteout_m_i_0[13]\, pteout_m_i_1_d0 => - \pteout_m_i_0[10]\, pteout_m_i_0_d0 => \pteout_m_i_0[9]\, - pteout_m_i_18 => \pteout_m_i_0[27]\, pteout_m_i_3 => - \pteout_m_i_0[12]\, pteout_m_i_0_1_0 => - \pteout_m_i_0_0[8]\, pteout_m_i_0_1_15 => - \pteout_m_i_0_0[23]\, pteout_m_i_0_0_0 => - \pteout_m_i_0_2[8]\, pteout_m_i_0_0_16 => - \pteout_m_i_0_0[24]\, pteout_m_i_0_0_15 => - \pteout_m_i_0_2[23]\, pteout_m_i_0_0_17 => - \pteout_m_i_0_0[25]\, pteout_m_i_0_0_14 => - \pteout_m_i_0_0[22]\, pteout_m_i_0_0_18 => - \pteout_m_i_0_0[26]\, data_1_3_i_a3_3_3 => - \data_1_3_i_a3_3[28]\, data_1_3_i_a3_3_4 => - \data_1_3_i_a3_3[29]\, data_1_3_i_a3_3_1 => - \data_1_3_i_a3_3[26]\, data_1_3_i_a3_3_5 => - \data_1_3_i_a3_3[30]\, un1_cam_hitaddr(61) => - \un1_cam_hitaddr[61]\, data_1_3_i_a3_2(25) => - \data_1_3_i_a3_2[25]\, data_1_3_i_a3_5_2 => - \data_1_3_i_a3_5[27]\, data_1_3_i_a3_5_0 => - \data_1_3_i_a3_5[25]\, pteout_m_i_0_10 => - \pteout_m_i_2[18]\, pteout_m_i_0_8 => \pteout_m_i_2[16]\, - pteout_m_i_0_6 => \pteout_m_i_0[14]\, pteout_m_i_0_0_d0 - => \pteout_m_i_0[8]\, pteout_m_i_0_15 => - \pteout_m_i_0[23]\, pteout_m_i_0_13 => - \pteout_m_i_0_0[21]\, pteout_m_i_0_3 => - \pteout_m_i_0_0[11]\, data_1_3_i_a3_0_2(15) => - \data_1_3_i_a3_0_2[15]\, data_1_3_i_a3_0_5_0 => - \data_1_3_i_a3_0_5[12]\, data_1_3_i_a3_0_5_3 => - \data_1_3_i_a3_0_5[15]\, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, - N_1138 => N_1138, cam_hit_all_5_sqmuxa_2 => - cam_hit_all_5_sqmuxa_2, N_1151 => N_1151, N_1154 => - N_1154, s2_flush => s2_flush, N_1137 => N_1137, NEEDSYNC - => NEEDSYNC_0, N_1167 => N_1167, un1_rst_i_0 => - \un1_rst_i_0\, N_696 => N_696, N_695 => N_695, N_2709_i_0 - => \N_2709_i_0\, N_694 => N_694, trans_op => trans_op, - N_2483 => N_2483, M_1 => M_1, N_661 => N_661, N_3046 => - N_3046, N_1513 => N_1513, N_3043 => N_3043, N_61 => N_61, - N_1166 => N_1166, N_1165 => N_1165, N_1164 => N_1164, - N_1163 => N_1163, N_1162 => N_1162, N_1161 => N_1161, - N_1160 => N_1160, N_1159 => N_1159, N_1158 => N_1158, - N_1157 => N_1157, N_1156 => N_1156, N_1155 => N_1155, - N_1153 => N_1153, N_1152 => N_1152, N_1150 => N_1150, - N_1149 => N_1149, N_1148 => N_1148, N_1147 => N_1147, - N_1146 => N_1146, N_1145 => N_1145, N_1144 => N_1144, - N_1143 => N_1143, N_1142 => N_1142, N_1141 => N_1141, - N_1140 => N_1140, N_1136 => N_1136, N_1135 => N_1135, - N_1134 => N_1134, s2_flush_0 => s2_flush_0, hit_1 => - hit_2, hit_0 => hit_0, hit => hit_1, WBNEEDSYNC_m => - WBNEEDSYNC_m, accexc_6_3 => accexc_6_3); - - \r.walk_transdata.data_RNIA759[14]\ : OR2B - port map(A => walk_use, B => \data_1[14]\, Y => N_2955); - - \r.walk_fault.fault_mexc_RNO\ : NOR2A - port map(A => fault_mexc, B => N_2523, Y => N_29); - - \r.s2_entry_RNICNLJ[0]\ : MX2 - port map(A => N_1185, B => N_1287, S => \s2_entry[0]\, Y - => \adata[17]\); - - \r.s2_entry_1[1]\ : DFN1E0 - port map(D => \s2_entry_1_0[1]\, CLK => lclk_c, E => N_53, - Q => \s2_entry_1[1]\); - - \cam_addr[16]\ : MX2 - port map(A => maddress(16), B => data_1_4, S => trans_op_0, - Y => \cam_addr[16]_net_1\); - - \r.walk_transdata.data_RNI4HSU3[26]\ : AO1A - port map(A => \adata[22]\, B => N_3060, C => N_2931, Y => - \data_1_i_m2_i_0[26]\); - - \r.s2_entry_1_RNIBADL1[0]\ : MX2 - port map(A => N_1197, B => N_1299, S => \s2_entry_1[0]\, Y - => adata_29); - - \r.s2_data_RNI048C3[28]\ : MX2 - port map(A => \adata[24]\, B => \data[28]\, S => N_550, Y - => \data_1[28]\); - - \r.s2_entry_1_RNIE3VP[1]\ : MX2 - port map(A => N_1130, B => N_1164, S => \s2_entry_1[1]\, Y - => N_1198); - - \r.walk_transdata.data_RNO[17]\ : MX2 - port map(A => hrdata_0_13, B => \data_1[17]\, S => \N_3160\, - Y => \data_3[17]\); - - \r.walk_transdata.data[22]\ : DFN1E0 - port map(D => N_692, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[22]\); - - \r.s2_entry_1_RNI0FLN1[0]\ : MX2 - port map(A => N_1191, B => N_1293, S => \s2_entry_1[0]\, Y - => \adata[23]\); - - \r.walk_use_1_RNI5E4Q1_0\ : NOR2 - port map(A => walk_use_1, B => N_550, Y => N_3060); - - \r.walk_transdata.data_RNI5C3D[30]\ : OR2B - port map(A => \walk_use_0\, B => \data_1[30]\, Y => N_2923); - - \r.s2_tlbstate_RNO_0[0]\ : OA1A - port map(A => N_166, B => N_2547, C => N_2538, Y => - \s2_tlbstate_ns_0_0_0[0]\); - - \r.s2_entry_1_RNIUJ1Q[1]\ : MX2 - port map(A => N_1223, B => N_1257, S => \s2_entry_1[1]\, Y - => N_1291); - - \r.s2_entry_RNI3I39[1]\ : MX2 - port map(A => N_1219, B => N_1253, S => \s2_entry[1]\, Y - => N_1287); - - \r.nrep_RNO[1]\ : NOR3A - port map(A => rst, B => N_2525, C => nrep_n1_0_i_0, Y => - N_2511); - - \r.walk_transdata.data[16]\ : DFN1E0 - port map(D => N_2736, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data[16]\); - - \r.s2_entry_RNI7V88[1]\ : MX2 - port map(A => N_1205, B => N_1239, S => \s2_entry[1]\, Y - => N_1273); - - \r.s2_entry_1_RNI22N21[0]\ : MX2 - port map(A => N_1179, B => N_1281, S => \s2_entry_1[0]\, Y - => \adata[11]\); - - \r.s2_flush_RNIMSF51\ : OR2 - port map(A => s2_flush, B => read, Y => M_1); - - \r.walk_fault.fault_pri_RNICI913\ : AO1 - port map(A => \walk_use_0\, B => fault_pri_0, C => - fault_pri_1_m, Y => \fault_pri\); - - \r.s2_read_RNIUUU6D\ : NOR2A - port map(A => \fault_read\, B => hrdata_6, Y => N_2483); - - \r.s2_tlbstate_RNIUL5E[0]\ : NOR2B - port map(A => \s2_tlbstate[0]\, B => tlbactive, Y => N_2530); - - \r.walk_transdata.data_RNICQSS3[31]\ : AO1A - port map(A => \adata[27]\, B => N_3060, C => N_2962, Y => - \data_1_i_0[31]\); - - \r.s2_entry_RNINIT2[2]\ : NOR2B - port map(A => \s2_entry[2]\, B => \s2_entry[1]\, Y => - \tlbcam_write_op_1_1[7]\); - - \r.walk_transdata.data[3]\ : DFN1E0 - port map(D => \data[3]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[3]\); - - \r.s2_tlbstate_RNIBJJC[1]\ : NOR2A - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => N_2522); - - \r.s2_entry_1_RNIQ2N21[0]\ : MX2 - port map(A => N_1182, B => N_1284, S => \s2_entry_1[0]\, Y - => \adata[14]\); - - \cam_addr[19]\ : MX2 - port map(A => maddress(19), B => data_1_7, S => trans_op_0, - Y => \cam_addr[19]_net_1\); - - \r.s2_entry_1_RNIEK3Q[1]\ : MX2 - port map(A => N_1227, B => N_1261, S => \s2_entry_1[1]\, Y - => N_1295); - - \r.s2_data_RNI9SSM[21]\ : MX2C - port map(A => \cam_addr[21]_net_1\, B => \data_0[21]\, S - => s2_flush_1, Y => \I2_1[3]\); - - \r.s2_data[9]\ : DFN1E1 - port map(D => un1_m0_2_84, CLK => lclk_c, E => s1finished, - Q => \data[9]\); - - \r.s2_tlbstate_RNIVL5E[1]\ : OR2A - port map(A => tlbactive, B => \s2_tlbstate[1]\, Y => N_89); - - \r.walk_transdata.data_RNIVPQ9[7]\ : MX2 - port map(A => \data[7]\, B => \data_0[7]\, S => walk_use, Y - => un1_m0_2_8); - - \cam_addr[26]\ : MX2 - port map(A => maddress(26), B => data_0_26, S => trans_op_0, - Y => \cam_addr[26]_net_1\); - - \r.walk_transdata.data_RNI7G3D[31]\ : NOR2A - port map(A => walk_use_1, B => \data_1[31]\, Y => N_2962); - - \r.s2_data_RNIEE9J3[22]\ : OR3C - port map(A => N_3038, B => N_3036, C => N_3037, Y => - un1_m0_2_23); - - \r.s2_entry_RNIM58V[0]\ : MX2 - port map(A => N_1200, B => N_1302, S => \s2_entry[0]\, Y - => \un1_acc[32]\); - - \r.s2_entry_0_RNIQ23VN2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[2]\, Y => - \tlbcam_write_op_1_1[3]\); - - \r.s2_entry_1_RNIJMKP1[0]\ : NOR2A - port map(A => N_3062, B => \adata[15]\, Y => N_3001); - - \r.s2_data_RNI1CSM[12]\ : MX2C - port map(A => \cam_addr[12]_net_1\, B => \data[12]\, S => - s2_flush_0, Y => \I3_1[0]\); - - \cam_addr_i_m4[29]\ : MX2 - port map(A => maddress(29), B => data_1_17, S => trans_op, - Y => N_701); - - \r.s2_tlbstate_RNO_3[0]\ : NOR3B - port map(A => \s2_tlbstate[0]\, B => N_95, C => - \s2_tlbstate[1]\, Y => \s2_tlbstate_ns_0_0_a2_0_0[0]\); - - \r.s2_entry_0_RNIQ23VN2_4[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[4]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_1_0[4]\); - - \r.s2_flush_1_RNINUQK\ : OR2 - port map(A => N_3073, B => data_0_14, Y => N_3043); - - \r.s2_entry_1_RNIU2UF[1]\ : MX2 - port map(A => N_1132, B => N_1166, S => \s2_entry_1[1]\, Y - => N_1200); - - \r.s2_entry_1_RNIU6LP1[0]\ : NOR2A - port map(A => N_3062, B => \adata[16]\, Y => N_3005); - - \r.s2_entry_0[1]\ : DFN1E0 - port map(D => \s2_entry_1_0[1]\, CLK => lclk_c, E => N_53, - Q => \s2_entry_0[1]\); - - \r.s2_data_RNI9PQR[17]\ : MX2C - port map(A => \cam_addr[17]_net_1\, B => \data_1[17]\, S - => s2_flush_1, Y => \I3_1[5]\); - - \r.s2_entry_0_RNIS31Q[1]\ : MX2 - port map(A => N_1126, B => N_1160, S => \s2_entry_0[1]\, Y - => N_1194); - - \r.walk_transdata.data_RNO[23]\ : MX2 - port map(A => N_264_0, B => \data_0[23]\, S => lvl_i_1_0(1), - Y => N_693); - - \r.sync_isw_RNISUDSK\ : NOR3A - port map(A => rst, B => \N_2532\, C => \N_2550\, Y => - twowner_2_0_a2_0_0(0)); - - \r.s2_entry_0[0]\ : DFN1E0 - port map(D => \s2_entry_1_0[0]\, CLK => lclk_c, E => N_53, - Q => \s2_entry_0[0]\); - - \r.walk_transdata.data_RNI1QQ9[8]\ : MX2 - port map(A => \data[8]\, B => \data_0[8]\, S => walk_use, Y - => un1_m0_2_9); - - \r.s2_data[19]\ : DFN1E1 - port map(D => data_1_7, CLK => lclk_c, E => s1finished_1, Q - => \data_0[19]\); - - \r.walk_transdata.data[29]\ : DFN1E0 - port map(D => N_2747, CLK => lclk_c, E => cache_0_sqmuxa, Q - => \data[29]\); - - \r.s2_entry_3[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_3[2]\); - - \r.s2_needsync_RNO_1\ : AOI1B - port map(A => un1_tlbcami_3, B => tlbcamo_needsync, C => - NEEDSYNC, Y => s2_needsync_4); - - \r.s2_entry_1_RNIJDJF[1]\ : MX2 - port map(A => N_1212, B => N_1246, S => \s2_entry_1[1]\, Y - => N_1280); - - \r.walk_transdata.data_RNO[21]\ : MX2 - port map(A => hrdata_0_17, B => \data_0[21]\, S => - lvl_i_1_0(1), Y => N_691); - - \r.walk_transdata.data[12]\ : DFN1E0 - port map(D => N_19, CLK => lclk_c, E => cache_0_sqmuxa_0, Q - => \data_1[12]\); - - \r.s2_entry_1_RNILUJN1[0]\ : MX2 - port map(A => N_1190, B => N_1292, S => \s2_entry_1[0]\, Y - => \adata[22]\); - - \r.walk_transdata.data_RNO[26]\ : MX2 - port map(A => \data[26]\, B => hrdata_0_22, S => N_2571, Y - => N_2739); - - \r.walk_fault.fault_mexc_RNO_0\ : OR3A - port map(A => \N_2532\, B => N_2531, C => \N_2550\, Y => - N_55); - - \r.s2_entry_1_RNI3ACL1[0]\ : MX2 - port map(A => N_1196, B => N_1298, S => \s2_entry_1[0]\, Y - => adata_28); - - \r.s2_data[4]\ : DFN1E1 - port map(D => un1_m0_2_79, CLK => lclk_c, E => s1finished, - Q => \data[4]\); - - \p0.transdata.data_1_i_m2_i_a2[27]\ : NOR2A - port map(A => N_3060, B => \adata[23]\, Y => N_2957); - - \r.walk_transdata.data_RNIJEPD[2]\ : MX2 - port map(A => \data[2]\, B => \data_0[2]\, S => walk_use_1, - Y => un1_m0_2_3); - - \r.s2_data[21]\ : DFN1E1 - port map(D => data_1_9, CLK => lclk_c, E => s1finished_1, Q - => \data_0[21]\); - - \r.sync_isw_RNO_0\ : OR3A - port map(A => N_95, B => \N_86_i\, C => N_2509, Y => N_2494); - - \r.s2_data[24]\ : DFN1E1 - port map(D => data_1_12, CLK => lclk_c, E => s1finished_1, - Q => \data[24]\); - - \r.s2_entry_RNITUUSN2_1[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => - \tlbcam_write_op_1_1[4]\, C => \s2_entry[0]\, Y => - \tlbcam_write_op_1[4]\); - - \r.s2_ctx[3]\ : DFN1E1 - port map(D => ctx(3), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[3]\); - - \r.s2_tlbstate_RNIBJJC_0[1]\ : NOR2 - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => N_2523); - - \r.s2_entry_0_RNIQ23VN2_3[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[2]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_1_0[2]\); - - \r.s2_entry_0_RNIHUSSN2_1[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[1]\, Y => - \tlbcam_write_op_1_0[1]\); - - \r.nrep_RNIH84SF9[0]\ : MX2B - port map(A => \nrep[0]\, B => \cam_hitaddr_21[0]\, S => - \s1finished_0\, Y => \s2_entry_1_0[0]\); - - \r.s2_entry_0_RNIPQLE[1]\ : MX2 - port map(A => N_1102, B => N_1136, S => \s2_entry_0[1]\, Y - => N_1170); - - \r.s2_data_RNI523H[14]\ : OA1A - port map(A => s2_flush_0, B => \data[14]\, C => N_3044, Y - => \I3_1_i_0_0[2]\); - - \tlbcam0.3.tag0\ : mmutlbcam_2_0_7 - port map(hrdata_0_27 => hrdata_0_27, hrdata_0_26 => - hrdata_0_26, hrdata_0_23 => hrdata_0_23, hrdata_0_22 => - hrdata_0_22, hrdata_0_21 => hrdata_0_21, hrdata_0_18 => - hrdata_0_18, hrdata_0_16 => hrdata_0_16, hrdata_0_15 => - hrdata_0_15, hrdata_0_12 => hrdata_0_12, hrdata_0_8 => - hrdata_0_8, hrdata_0_0 => hrdata_0_0, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1(3) => \tlbcam_write_op_1_1[3]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_30 => - hrdata_31, hrdata_29 => hrdata_30, hrdata_28 => hrdata_29, - hrdata_27 => hrdata_28, hrdata_23 => hrdata_24, hrdata_16 - => hrdata_17, hrdata_13 => hrdata_14, hrdata_12 => - hrdata_13, hrdata_10 => hrdata_11, hrdata_9 => hrdata_10, - hrdata_8 => hrdata_9, hrdata_0_d0 => hrdata_1, hrdata_3 - => hrdata_4, hrdata_2 => hrdata_3, hrdata_1 => hrdata_2, - hrdata_6 => hrdata_7, tlbcam_write_op_1(3) => - \tlbcam_write_op_1[3]\, LVL_1(1) => \LVL_4[1]\, TYP_1(2) - => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, TYP_1(0) => - \TYP_1[0]\, s2_entry(2) => \s2_entry[2]\, I1_1_i_0_0(0) - => \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, - LVL_0(1) => \LVL_3[1]\, LVL_0(0) => \LVL_2[0]\, - s2_entry_4(2) => \s2_entry_4[2]\, pteout_4 => - \pteout_4[4]\, pteout_3 => \pteout_4[3]\, pteout_2 => - \pteout_4[2]\, s2_entry_3(2) => \s2_entry_3[2]\, - pteout_0_4 => \pteout_2[4]\, pteout_0_17 => - \pteout_1[17]\, pteout_0_3 => \pteout_2[3]\, pteout_0_13 - => \pteout_1[13]\, pteout_0_31 => \pteout_1[31]\, - pteout_0_30 => \pteout_1[30]\, pteout_0_29 => - \pteout_1[29]\, pteout_0_28 => \pteout_1[28]\, - pteout_0_27 => \pteout_1[27]\, pteout_0_26 => - \pteout_1[26]\, pteout_0_25 => \pteout_1[25]\, - pteout_0_24 => \pteout_1[24]\, pteout_0_23 => - \pteout_1[23]\, pteout_0_22 => \pteout_1[22]\, - pteout_0_21 => \pteout_1[21]\, pteout_0_20 => - \pteout_1[20]\, pteout_0_19 => \pteout_1[19]\, - pteout_0_18 => \pteout_1[18]\, pteout_0_16 => - \pteout_1[16]\, pteout_0_15 => \pteout_1[15]\, - pteout_0_14 => \pteout_1[14]\, pteout_0_12 => - \pteout_1[12]\, pteout_0_11 => \pteout_1[11]\, - pteout_0_10 => \pteout_1[10]\, pteout_0_9 => - \pteout_1[9]\, pteout_0_8 => \pteout_1[8]\, pteout_0_7 - => \pteout_1[7]\, pteout_0_6 => \pteout_1[6]\, - pteout_0_2 => \pteout_2[2]\, pteout_0_1 => \pteout_1[1]\, - pteout_0_0 => \pteout_1[0]\, I3_1_i(3) => \I3_1_i[3]\, - tlbcam_write_op_1_0(3) => \tlbcam_write_op_1_0[3]\, - LVL_0_d0 => \LVL_4[0]\, ctx_7 => ctx(7), ctx_6 => ctx(6), - ctx_5 => ctx(5), ctx_3 => ctx(3), ctx_1 => ctx(1), - ctx_0_d0 => ctx(0), ctx_2 => ctx(2), ctx_0(4) => ctx_0(4), - I2_1(5) => \I2_1[5]\, I2_1(4) => \I2_1[4]\, I2_1(3) => - \I2_1[3]\, I2_1(2) => \I2_1[2]\, I2_1(1) => \I2_1[1]\, - I2_1(0) => \I2_1[0]\, I1_1_6 => \I1_1[7]\, I1_1_3 => - \I1_1[4]\, I1_1_2 => \I1_1[3]\, I1_1_0 => \I1_1[1]\, - I1_1_1 => \I1_1[2]\, I1_1_5 => \I1_1[6]\, I3_1_4 => - \I3_1[4]\, I3_1_0 => \I3_1[0]\, I3_1_5 => \I3_1[5]\, - TYP_1_0(0) => \TYP_1_0[0]\, pteout_m_i_11 => - \pteout_m_i_2[20]\, pteout_m_i_10 => \pteout_m_i_2[19]\, - pteout_m_i_9 => \pteout_m_i_3[18]\, pteout_m_i_7 => - \pteout_m_i_3[16]\, pteout_m_i_6 => \pteout_m_i_2[15]\, - pteout_m_i_4 => \pteout_m_i_2[13]\, pteout_m_i_3 => - \pteout_m_i_2[12]\, pteout_m_i_1 => \pteout_m_i_2[10]\, - pteout_m_i_0_d0 => \pteout_m_i_2[9]\, pteout_m_i_8 => - \pteout_m_i_2[17]\, pteout_m_i_5 => \pteout_m_i_2[14]\, - un2_wb_acc_iv_1_3 => \un2_wb_acc_iv_1[17]\, - un2_wb_acc_iv_1_0 => \un2_wb_acc_iv_1[14]\, - un2_wb_acc_iv_0(27) => \un2_wb_acc_iv_0[27]\, - un2_wb_acc_iv_4(27) => \un2_wb_acc_iv_4[27]\, - pteout_m_i_0_18 => \pteout_m_i_0_2[26]\, pteout_m_i_0_17 - => \pteout_m_i_0_2[25]\, pteout_m_i_0_15 => - \pteout_m_i_0_3[23]\, pteout_m_i_0_0_d0 => - \pteout_m_i_0_3[8]\, pteout_m_i_0_19 => - \pteout_m_i_2[27]\, pteout_m_i_0_16 => - \pteout_m_i_0_2[24]\, pteout_m_i_0_14 => - \pteout_m_i_0_2[22]\, pteout_m_i_0_13 => - \pteout_m_i_0_2[21]\, data_1_3_i_a3_1_3 => - \data_1_3_i_a3_1[28]\, data_1_3_i_a3_1_1 => - \data_1_3_i_a3_1[26]\, data_1_3_i_a3_1_0 => - \data_1_3_i_a3_1[25]\, pteout_m_i_0_0_0 => - \pteout_m_i_0_2[11]\, data_1_3_i_a3_0_1(15) => - \data_1_3_i_a3_0_1[15]\, un1_cam_hitaddr(60) => - \un1_cam_hitaddr[60]\, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => \N_2482\, lclk_c => lclk_c, - cam_hit_all_5_sqmuxa_2 => cam_hit_all_5_sqmuxa_2, N_2551 - => N_2551, N_1498 => N_1498, N_1506 => N_1506, N_1240 - => N_1240, N_1253 => N_1253, trans_op => trans_op, - s2_flush => s2_flush, hit => hit_2, N_1239 => N_1239, - N_1269 => N_1269, N_1249 => N_1249, un1_rst_i_0 => - \un1_rst_i_0\, un1_tlbcami_3 => un1_tlbcami_3_1, N_2483 - => N_2483, M_1 => M_1, N_3046 => N_3046, N_3043 => - N_3043, N_61 => N_61, N_1268 => N_1268, N_1267 => N_1267, - N_1266 => N_1266, N_1265 => N_1265, N_1264 => N_1264, - N_1263 => N_1263, N_1262 => N_1262, N_1261 => N_1261, - N_1260 => N_1260, N_1259 => N_1259, N_1258 => N_1258, - N_1257 => N_1257, N_1256 => N_1256, N_1255 => N_1255, - N_1254 => N_1254, N_1252 => N_1252, N_1251 => N_1251, - N_1250 => N_1250, N_1248 => N_1248, N_1247 => N_1247, - N_1246 => N_1246, N_1245 => N_1245, N_1244 => N_1244, - N_1243 => N_1243, N_1242 => N_1242, N_1238 => N_1238, - N_1237 => N_1237, N_1236 => N_1236, s2_flush_0 => - s2_flush_0, N_661 => N_661, tlbcamo_needsync => - tlbcamo_needsync_1, WBNEEDSYNC_m => WBNEEDSYNC_m_1, - accexc_6_2 => accexc_6_2); - - \r.s2_read\ : DFN1E1 - port map(D => read, CLK => lclk_c, E => s1finished, Q => - \fault_read\); - - \r.s2_entry_1_RNIMJ0Q[1]\ : MX2 - port map(A => N_1221, B => N_1255, S => \s2_entry_1[1]\, Y - => N_1289); - - \r.walk_transdata.data_RNI3QQ9[9]\ : MX2 - port map(A => \data[9]\, B => \data_0[9]\, S => walk_use, Y - => un1_m0_2_10); - - \r.s2_flush_1_RNIE098\ : OR2A - port map(A => trans_op_0, B => s2_flush_1, Y => N_3073); - - \r.s2_flush_RNI7T2E1\ : OR2 - port map(A => N_2552, B => N_2530, Y => N_53); - - \r.s2_entry_1_RNITTGN1[0]\ : MX2 - port map(A => N_1187, B => N_1289, S => \s2_entry_1[0]\, Y - => \adata[19]\); - - \r.s2_entry_0[2]\ : DFN1E0 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => N_53, Q - => \s2_entry_0[2]\); - - \r.s2_data_RNIM5VP5[30]\ : OR3C - port map(A => N_2922, B => N_2923, C => N_2924, Y => - un1_m0_2_31); - - \cam_addr[23]\ : MX2 - port map(A => maddress(23), B => data_1_11, S => trans_op, - Y => \cam_addr[23]_net_1\); - - \r.s2_hm_RNI84O9\ : OR3A - port map(A => s2_hm, B => tlbdis, C => s2_needsync_1, Y => - N_166); - - \r.s2_data_RNIPKTM[26]\ : MX2C - port map(A => \cam_addr[26]_net_1\, B => \data[26]\, S => - s2_flush_0, Y => \I1_1[2]\); - - \r.s2_entry_RNIM6AJ1[0]\ : MX2 - port map(A => N_1198, B => N_1300, S => \s2_entry[0]\, Y - => adata_30); - - \r.s2_ctx[7]\ : DFN1E1 - port map(D => ctx(7), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[7]\); - - \r.s2_ctx[2]\ : DFN1E1 - port map(D => ctx(2), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[2]\); - - \r.nrep_RNO[2]\ : XA1 - port map(A => N_2513, B => \nrep[2]\, C => rst, Y => N_2512); - - \r.s2_entry_1_RNIS3UF[1]\ : MX2 - port map(A => N_1209, B => N_1243, S => \s2_entry_1[1]\, Y - => N_1277); - - \r.sync_isw_RNI7DR9_0\ : NOR2A - port map(A => \s2_tlbstate[1]\, B => sync_isw, Y => - areq_ur_1_0_a2_0_0); - - \r.s2_entry_RNIQFSN[1]\ : MX2 - port map(A => N_1222, B => N_1256, S => \s2_entry[1]\, Y - => N_1290); - - \r.s2_entry_0_RNI1DGF[1]\ : MX2 - port map(A => N_1111, B => N_1145, S => \s2_entry_0[1]\, Y - => N_1179); - - \tlbcam0.6.tag0\ : mmutlbcam_2_0_1 - port map(lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1_1(6) => \tlbcam_write_op_1_1[6]\, - data(31) => \data[31]\, data(30) => \data[30]\, data(29) - => \data_0[29]\, data(28) => \data[28]\, data(27) => - \data_0[27]\, data(26) => \data[26]\, data(25) => - \data[25]\, data(24) => \data[24]\, data(23) => - \data_0[23]\, data(22) => \data_0[22]\, data(21) => - \data_0[21]\, data(20) => \data_0[20]\, data(19) => - \data_0[19]\, data(18) => \data[18]\, data(17) => - \data_1[17]\, data(16) => \data_0[16]\, data(15) => - \data[15]\, data(14) => \data[14]\, data(13) => - \data_0[13]\, data(12) => \data[12]\, s2_ctx(7) => - \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, s2_ctx(5) => - \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, s2_ctx(3) => - \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, s2_ctx(1) => - \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0 => hrdata_0_d0, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_7 => hrdata_7, - tlbcam_write_op_1(6) => \tlbcam_write_op_1[6]\, TYP_1(2) - => \TYP_1[2]\, TYP_1(1) => \TYP_1[1]\, TYP_1(0) => - \TYP_1[0]\, tlbcam_write_op_1_0(6) => - \tlbcam_write_op_1_0[6]\, I1_1_i_0_0(0) => - \I1_1_i_0_0[0]\, I3_1_i_0_0(2) => \I3_1_i_0_0[2]\, - pteout_m_i_8 => \pteout_m_i_0[17]\, pteout_m_i_18 => - \pteout_m_i_0[27]\, pteout_m_i_11 => \pteout_m_i_0[20]\, - pteout_m_i_10 => \pteout_m_i_0[19]\, pteout_m_i_9 => - \pteout_m_i_0[18]\, pteout_m_i_7 => \pteout_m_i_0[16]\, - pteout_m_i_6 => \pteout_m_i_0[15]\, pteout_m_i_5 => - \pteout_m_i_0[14]\, pteout_m_i_4 => \pteout_m_i_0[13]\, - pteout_m_i_3 => \pteout_m_i_0[12]\, pteout_m_i_1 => - \pteout_m_i_0[10]\, pteout_m_i_0_d0 => \pteout_m_i_0[9]\, - pteout_31 => \pteout_0[31]\, pteout_30 => \pteout_0[30]\, - pteout_29 => \pteout_0[29]\, pteout_28 => \pteout_0[28]\, - pteout_1 => \pteout_0[1]\, pteout_0 => \pteout_0[0]\, - pteout_4 => \pteout[4]\, pteout_3 => \pteout[3]\, - pteout_2 => \pteout[2]\, pteout_7 => \pteout_0[7]\, - pteout_17 => \pteout_0[17]\, pteout_27 => \pteout_0[27]\, - pteout_6 => \pteout_0[6]\, pteout_26 => \pteout_0[26]\, - pteout_25 => \pteout_0[25]\, pteout_24 => \pteout_0[24]\, - pteout_23 => \pteout_0[23]\, pteout_22 => \pteout_0[22]\, - pteout_21 => \pteout_0[21]\, pteout_20 => \pteout_0[20]\, - pteout_19 => \pteout_0[19]\, pteout_18 => \pteout_0[18]\, - pteout_16 => \pteout_0[16]\, pteout_15 => \pteout_0[15]\, - pteout_14 => \pteout_0[14]\, pteout_13 => \pteout_0[13]\, - pteout_12 => \pteout_0[12]\, pteout_11 => \pteout_0[11]\, - pteout_10 => \pteout_0[10]\, pteout_9 => \pteout_0[9]\, - pteout_8 => \pteout_0[8]\, pteout_m_i_0_18 => - \pteout_m_i_0_0[26]\, pteout_m_i_0_17 => - \pteout_m_i_0_0[25]\, pteout_m_i_0_16 => - \pteout_m_i_0_0[24]\, pteout_m_i_0_15 => - \pteout_m_i_0_0[23]\, pteout_m_i_0_14 => - \pteout_m_i_0_0[22]\, pteout_m_i_0_13 => - \pteout_m_i_0_0[21]\, pteout_m_i_0_3 => - \pteout_m_i_0_0[11]\, pteout_m_i_0_0 => - \pteout_m_i_0_0[8]\, ctx(4) => ctx(4), I3_1_i(3) => - \I3_1_i[3]\, un1_cam_hitaddr(57) => \un1_cam_hitaddr[57]\, - ctx_0_7 => ctx_0(7), ctx_0_5 => ctx_0(5), ctx_0_3 => - ctx_0(3), ctx_0_1 => ctx_0(1), ctx_0_0 => ctx_0(0), - ctx_0_2 => ctx_0(2), ctx_0_6 => ctx_0(6), I2_1(5) => - \I2_1[5]\, I2_1(4) => \I2_1[4]\, I2_1(3) => \I2_1[3]\, - I2_1(2) => \I2_1[2]\, I2_1(1) => \I2_1[1]\, I2_1(0) => - \I2_1[0]\, I1_1_5 => \I1_1[6]\, I1_1_2 => \I1_1[3]\, - I1_1_0 => \I1_1[1]\, I1_1_1 => \I1_1[2]\, I1_1_3 => - \I1_1[4]\, I1_1_6 => \I1_1[7]\, I3_1_4 => \I3_1[4]\, - I3_1_0 => \I3_1[0]\, I3_1_5 => \I3_1[5]\, LVL(1) => - \LVL[1]\, LVL(0) => \LVL[0]\, TYP_1_0(0) => \TYP_1_0[0]\, - N_78 => N_78, N_262 => N_262, N_264 => N_264, N_2482 => - \N_2482\, lclk_c => lclk_c, trans_op => trans_op, hit => - hit_1, s2_flush => s2_flush, un1_rst_i_0 => \un1_rst_i_0\, - un1_tlbcami_3 => un1_tlbcami_3_0, N_2483 => N_2483, M_1 - => M_1, N_661 => N_661, N_3046 => N_3046, N_3043 => - N_3043, N_61 => N_61, WBNEEDSYNC_m => WBNEEDSYNC_m_0, - tlbcamo_needsync => tlbcamo_needsync_0); - - \r.s2_entry_0_RNIHUSSN2_5[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[7]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_0[6]\); - - \r.s2_data_RNIF1I7[10]\ : OR2B - port map(A => \data[10]\, B => s2_flush_1, Y => \TYP_1[2]\); - - \r.s2_entry_1_RNIFHM21[0]\ : MX2 - port map(A => N_1177, B => N_1279, S => \s2_entry_1[0]\, Y - => \adata[9]\); - - \r.s2_data_RNI24SM[20]\ : MX2C - port map(A => \cam_addr[20]_net_1\, B => \data_0[20]\, S - => s2_flush_1, Y => \I2_1[2]\); - - \r.nrep_RNO_0[1]\ : NOR2B - port map(A => \nrep[2]\, B => N_2513, Y => N_2525); - - \cam_addr[21]\ : MX2 - port map(A => maddress(21), B => data_1_9, S => trans_op_0, - Y => \cam_addr[21]_net_1\); - - \r.s2_entry_RNINIT2_0[2]\ : NOR2 - port map(A => \s2_entry[2]\, B => \s2_entry[1]\, Y => - \tlbcam_write_op_1_1[1]\); - - \r.walk_fault.fault_pri\ : DFN1E1 - port map(D => N_38, CLK => lclk_c, E => N_25, Q => - fault_pri_0); - - \r.s2_flush_0\ : DFN1E1 - port map(D => s2_flush_1_0, CLK => lclk_c, E => un1_rst_3, - Q => s2_flush_0); - - \r.walk_transdata.data[19]\ : DFN1E0 - port map(D => N_699, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => \data[19]\); - - \r.walk_fault.fault_pro_RNIFJ8T2\ : NOR2A - port map(A => fault_pro_m, B => fault_pro_1_m_0_4, Y => - \fault_pro_1_iv_1\); - - \r.walk_transdata.data_RNO[22]\ : MX2 - port map(A => hrdata_0_18, B => \data_0[22]\, S => - lvl_i_1_0(1), Y => N_692); - - \r.s2_data[8]\ : DFN1E1 - port map(D => un1_m0_2_83, CLK => lclk_c, E => s1finished, - Q => \data[8]\); - - \cam_addr[15]\ : MX2 - port map(A => maddress(15), B => data_0_15, S => trans_op_0, - Y => \cam_addr[15]_net_1\); - - \r.s2_tlbstate_RNIS2MHL[1]\ : OR2B - port map(A => cache_0_sqmuxa_0, B => N_2547, Y => N_2276); - - \r.s2_entry_RNI3V88[1]\ : MX2 - port map(A => N_1103, B => N_1137, S => \s2_entry[1]\, Y - => N_1171); - - \r.s2_data_RNI2R442[15]\ : AO1D - port map(A => \data[15]\, B => N_3066, C => N_805, Y => - \data_1_i_0[15]\); - - \r.walk_fault.fault_lvl[1]\ : DFN1E0 - port map(D => N_82_0, CLK => lclk_c, E => cache_0_sqmuxa_0, - Q => fault_lvl(1)); - - \r.walk_transdata.data[2]\ : DFN1E0 - port map(D => \data[2]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[2]\); - - \r.s2_data[11]\ : DFN1E1 - port map(D => un1_m0_2_86, CLK => lclk_c, E => s1finished_1, - Q => \data[11]\); - - \r.s2_entry_0_RNIHUSSN2_4[0]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => - \tlbcam_write_op_1_1[1]\, C => \s2_entry_0[0]\, Y => - \tlbcam_write_op_1_1[0]\); - - \r.walk_transdata.data_RNINEPD[4]\ : MX2 - port map(A => \data[4]\, B => \data_0[4]\, S => walk_use_1, - Y => un1_m0_2_5); - - \r.s2_flush_1_RNIMKG9\ : OR3 - port map(A => trans_op_0, B => s2_flush_1, C => - maddress(24), Y => N_3047); - - \r.s2_data_RNI05ON[21]\ : NOR2A - port map(A => N_3063, B => \data_0[21]\, Y => N_3007); - - \r.s2_data[14]\ : DFN1E1 - port map(D => data_0_14, CLK => lclk_c, E => s1finished_1, - Q => \data[14]\); - - \r.s2_entry_RNIU6BJ1[0]\ : MX2 - port map(A => N_1199, B => N_1301, S => \s2_entry[0]\, Y - => adata_31); - - \r.s2_entry_1_RNI45UF[1]\ : MX2 - port map(A => N_1208, B => N_1242, S => \s2_entry_1[1]\, Y - => N_1276); - - \r.walk_transdata.data_RNO[31]\ : MX2 - port map(A => \data[31]\, B => hrdata_0_27, S => N_2571, Y - => \data_2[31]\); - - \r.walk_transdata.data_RNO[15]\ : MX2 - port map(A => hrdata_0_11, B => \data[15]\, S => \N_3160\, - Y => N_73); - - \cam_addr[18]\ : MX2 - port map(A => maddress(18), B => data_0_18, S => trans_op_0, - Y => \cam_addr[18]_net_1\); - - \r.s2_entry_RNI0N35[1]\ : NOR2A - port map(A => \s2_entry[1]\, B => \s2_entry_4[2]\, Y => - \tlbcam_write_op_1_1[2]\); - - \r.s2_entry_0_RNIHUSSN2_2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[0]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_0[7]\); - - \r.walk_transdata.data_RNO[24]\ : MX2 - port map(A => \data[24]\, B => N_262_0, S => N_2571, Y => - N_2737); - - \r.s2_data[30]\ : DFN1E1 - port map(D => data_0_30, CLK => lclk_c, E => s1finished, Q - => \data[30]\); - - \r.s2_flush_0_RNI8ELU\ : OA1B - port map(A => N_166, B => s2_flush_0, C => N_89, Y => N_93); - - \r.walk_transdata.data_RNI33542[16]\ : AO1A - port map(A => \data[16]\, B => \walk_use_0\, C => N_2912, Y - => \data_1_i_m2_i_0[16]\); - - \r.s2_entry_RNISH0I[0]\ : MX2 - port map(A => N_1172, B => N_1274, S => \s2_entry[0]\, Y - => \adata[4]\); - - \r.s2_entry_1_RNI6HDE2[0]\ : OR2B - port map(A => \adata[18]\, B => N_3062, Y => N_3038); - - \r.nrep_RNIR6H[1]\ : NOR2B - port map(A => \nrep[1]\, B => \nrep[0]\, Y => N_2513); - - \r.s2_entry_0_RNI3JTP[1]\ : MX2 - port map(A => N_1128, B => N_1162, S => \s2_entry_0[1]\, Y - => N_1196); - - \p0.fault.fault_pro_1_iv\ : NOR2B - port map(A => \fault_pro_1_iv_2\, B => \fault_pro_1_iv_1\, - Y => fault_pro_i); - - \r.s2_data_RNITA442[13]\ : AO1D - port map(A => \data_0[13]\, B => N_3066, C => N_2909, Y => - \data_1_i_m2_i_0[13]\); - - \p0.un9_twneedsync_i_a2_i_o2_i_a4_0\ : OA1C - port map(A => inv_1_0_a2_0_a2_0, B => hrdata_0_1, C => - fault_mexc, Y => un9_twneedsync_i_a2_i_o2_i_a4_0); - - \r.walk_transdata.data_RNILCV9[11]\ : MX2 - port map(A => \data[11]\, B => \data_0[11]\, S => walk_use, - Y => un1_m0_2_12); - - \r.s2_data_RNITOPR[22]\ : MX2C - port map(A => \cam_addr[22]_net_1\, B => \data_0[22]\, S - => s2_flush_1, Y => \I2_1[4]\); - - \r.s2_data_RNI2KGU2[20]\ : NOR3 - port map(A => N_3005, B => N_3002, C => N_3003, Y => N_417); - - \r.walk_transdata.data_RNIFMQN2[17]\ : MX2 - port map(A => \data[17]\, B => \data_0[17]\, S => walk_use, - Y => un1_m0_2_18); - - \r.s2_entry[1]\ : DFN1E0 - port map(D => \s2_entry_1_0[1]\, CLK => lclk_c, E => N_53, - Q => \s2_entry[1]\); - - \r.s2_tlbstate_RNIGCTEK[0]\ : OR2B - port map(A => \s2_tlbstate[0]\, B => N_82, Y => \N_2532\); - - \r.s2_data[23]\ : DFN1E1 - port map(D => data_1_11, CLK => lclk_c, E => s1finished_1, - Q => \data_0[23]\); - - \r.s2_tlbstate_RNIGCTEK_0[0]\ : OR2A - port map(A => \s2_tlbstate[0]\, B => N_82, Y => N_2509); - - \r.nrep[1]\ : DFN1E1 - port map(D => N_2511, CLK => lclk_c, E => nrepe, Q => - \nrep[1]\); - - \r.s2_entry_RNI7V88_0[1]\ : MX2 - port map(A => N_1104, B => N_1138, S => \s2_entry[1]\, Y - => N_1172); - - \r.s2_entry_0_RNI9JRF[1]\ : MX2 - port map(A => N_1107, B => N_1141, S => \s2_entry_0[1]\, Y - => N_1175); - - \r.walk_transdata.data_RNIB2223[14]\ : AOI1B - port map(A => \adata[10]\, B => N_3065, C => N_2955, Y => - \data_1_i_i_0[14]\); - - \r.walk_transdata.data_RNO[27]\ : MX2 - port map(A => \data_0[27]\, B => hrdata_0_23, S => N_2571, - Y => N_2740); - - \r.s2_data[27]\ : DFN1E1 - port map(D => data_1_15, CLK => lclk_c, E => s1finished, Q - => \data_0[27]\); - - \r.walk_transdata.data[9]\ : DFN1E0 - port map(D => \data[9]\, CLK => lclk_c, E => cache_0_sqmuxa, - Q => \data_0[9]\); - - \r.s2_entry_RNITUUSN2[0]\ : NOR3C - port map(A => dr1write_0_sqmuxa, B => \s2_entry[0]\, C => - \tlbcam_write_op_1_1[2]\, Y => \tlbcam_write_op_1[3]\); - - \r.s2_entry_0_RNIPISP[1]\ : MX2 - port map(A => N_1118, B => N_1152, S => \s2_entry_0[1]\, Y - => N_1186); - - \cam_addr[25]\ : MX2 - port map(A => maddress(25), B => data_0_25, S => trans_op_0, - Y => \cam_addr[25]_net_1\); - - \r.walk_transdata.data[30]\ : DFN1E0 - port map(D => \data_2[30]\, CLK => lclk_c, E => - cache_0_sqmuxa, Q => \data_1[30]\); - - \r.walk_use_RNIHJTM\ : NOR2A - port map(A => \un1_acc[33]\, B => walk_use, Y => N_3063); - - \r.s2_data_RNI963H[24]\ : OA1A - port map(A => s2_flush_0, B => \data[24]\, C => N_3047, Y - => \I1_1_i_0_0[0]\); - - \r.s2_data_RNI1PCT1[29]\ : OA1C - port map(A => N_3059, B => \data_0[29]\, C => - \data_1_i_0[29]\, Y => N_353); - - \r.walk_transdata.data_RNIA44D[26]\ : NOR2A - port map(A => \walk_use_0\, B => \data_1[26]\, Y => N_2931); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_2 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_17 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_6 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(0 to 0); - tlbcam_write_op_1_1_0 : in std_logic_vector(0 to 0); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - s2_entry_5 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_1 : in std_logic_vector(2 to 2); - s2_entry_0 : in std_logic_vector(2 to 2); - pteout_0_17 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_4 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(0 to 0); - data_14 : in std_logic; - data_13 : in std_logic; - data_12 : in std_logic; - data_11 : in std_logic; - data_10 : in std_logic; - data_9 : in std_logic; - data_8 : in std_logic; - data_7 : in std_logic; - data_6 : in std_logic; - data_5 : in std_logic; - data_4 : in std_logic; - data_3 : in std_logic; - data_22 : in std_logic; - data_21 : in std_logic; - data_20 : in std_logic; - data_19 : in std_logic; - data_18 : in std_logic; - data_17 : in std_logic; - data_16 : in std_logic; - data_15 : in std_logic; - data_0 : in std_logic; - ctx_0 : in std_logic_vector(7 downto 0); - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_749 : out std_logic; - N_743 : out std_logic; - N_765 : out std_logic; - s2_flush : in std_logic; - N_764 : out std_logic; - N_596 : in std_logic; - un1_rst_i_0 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_763 : out std_logic; - N_762 : out std_logic; - N_761 : out std_logic; - N_760 : out std_logic; - N_759 : out std_logic; - N_758 : out std_logic; - N_757 : out std_logic; - N_756 : out std_logic; - N_755 : out std_logic; - N_754 : out std_logic; - N_753 : out std_logic; - N_752 : out std_logic; - N_751 : out std_logic; - N_750 : out std_logic; - N_748 : out std_logic; - N_747 : out std_logic; - N_746 : out std_logic; - N_745 : out std_logic; - N_744 : out std_logic; - N_742 : out std_logic; - N_741 : out std_logic; - N_740 : out std_logic; - N_739 : out std_logic; - N_738 : out std_logic; - N_736 : out std_logic; - N_735 : out std_logic; - N_734 : out std_logic; - N_733 : out std_logic; - N_732 : out std_logic; - N_634 : in std_logic; - N_632 : in std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - SU_RNIAA5O8 : out std_logic; - hit_0_a3_0 : out std_logic; - s2_flush_0 : in std_logic; - N_169_1 : out std_logic; - N_200 : in std_logic; - N_32_i : out std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - hit_0_a3_2_0 : out std_logic; - N_17_i_0 : out std_logic; - N_204 : in std_logic; - N_170_1 : out std_logic; - N_170 : out std_logic; - N_200_0 : in std_logic; - N_42 : out std_logic - ); - -end mmutlbcam_0_0_2; - -architecture DEF_ARCH of mmutlbcam_0_0_2 is - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_165, N_41, N_40, N_16, N_163, N_39, hit_0_a3_3_0, - hit_0_a3_0_0, h_i32_NE, hit_0_a3_7_0, \un1_tag0[43]\, - \LVL[0]\, N_159, M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNISE6H[5]\, \un1_tag0[64]\, \I2_RNIL5UF[3]\, - \un1_tag0[62]\, \I2_RNIVPUF[1]\, hit_0_a3_5_0, SU, - \LVL[1]\, h_i13_NE_5, h_i13_NE_2, h_i13_NE_3, h_i13_NE_4, - h_i13_NE_0, h_i13_NE_1, \un1_tag0[74]\, \I1_RNIQ9UF[7]\, - \un1_tag0[72]\, \I1_RNI5N6H[5]\, \un1_tag0[70]\, - \I1_RNIUDUF[3]\, \un1_tag0[68]\, \I1_RNIOTTF[1]\, - h_i32_NE_2, \un1_tag0[60]\, \I3_RNI3B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNIS1VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNIMHUF[1]\, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, N_43, N_160, h_i13_NE_i_0, N_162, N_44, - \N_17_i_0\, \N_169_1\, \hit_0_a3_0\, N_15, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[57]\, \un1_tag0[59]\, - \pteout[0]\, \pteout[1]\, \pteout[2]\, \pteout[3]\, - \pteout[4]\, \pteout[6]\, \pteout[7]\, \pteout[8]\, - \pteout[9]\, \pteout[10]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[15]\, \pteout[16]\, \pteout[18]\, - \pteout[19]\, \pteout[20]\, \pteout[21]\, \pteout[22]\, - \pteout[23]\, \pteout[24]\, \pteout[25]\, \pteout[26]\, - \pteout[27]\, \pteout[28]\, \pteout[29]\, \pteout[30]\, - \pteout[31]\, \un1_tag0[73]\, \un1_tag0[75]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, - VALID_RNO_1, N_38, \un1_tag0[61]\, \N_170_1\, - \pteout[11]\, \N_42\, \pteout[17]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - hit_0_a3_0 <= \hit_0_a3_0\; - N_169_1 <= \N_169_1\; - N_17_i_0 <= \N_17_i_0\; - N_170_1 <= \N_170_1\; - N_42 <= \N_42\; - - \r.btag.LVL_RNIL7784[0]\ : OA1C - port map(A => h_i32_NE, B => \LVL[0]\, C => N_159, Y => - hit_0_a3_2_0); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[8]\); - - \r.btag.PPN_RNI745B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_1(2), Y => N_750); - - \r.btag.LVL_RNI7CI44[0]\ : NOR2 - port map(A => \LVL[0]\, B => h_i13_NE_i_0, Y => N_162); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \LVL[1]\); - - \r.btag.CTX_RNI6S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.I2_RNIKS411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNISE6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data_10, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[63]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[19]\); - - \r.btag.I3_RNILRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNIS1VF[3]\, Y => h_i32_NE_1); - - \r.btag.CTX_RNIES44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0(4), Y => h_c2_4_i); - - \r.btag.I2_RNIN4623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.ET_RNIADSA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_0(2), Y => N_733); - - \r.btag.PPN_RNINDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_749); - - \r.btag.PPN_RNIHC6B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_1(2), Y => N_755); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data_14, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(0), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[41]\); - - \r.btag.C_RNIC446\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_0(2), Y => N_739); - - \r.btag.I1_RNIQ9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIQ9UF[7]\); - - \r.btag.CTX_RNIKS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.PPN_RNIH1V5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_1(2), Y => N_746); - - \r.btag.SU_RNIAA5O8\ : AO1 - port map(A => N_44, B => N_43, C => \hit_0_a3_0\, Y => - SU_RNIAA5O8); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data_9, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[36]\); - - \r.btag.I1_RNIVH934[0]\ : NOR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => - h_i13_NE_i_0); - - \r.btag.PPN_RNILS6B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_1(2), Y => N_757); - - \r.btag.CTX_RNI8S44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[10]\); - - \r.btag.PPN_RNIL1V5[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_1(2), Y => N_748); - - \tlbcamo.hit_0_a3_3_RNO\ : NOR2B - port map(A => N_204, B => \N_17_i_0\, Y => hit_0_a3_3_0); - - \r.btag.ACC_RNI88H5[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry_0(2), Y => N_736); - - \r.btag.I3_RNIMHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIMHUF[1]\); - - \tlbcamo.hit_0_a3_8\ : NOR2 - port map(A => N_200_0, B => N_16, Y => N_40); - - \r.btag.SU_RNIH3KE1\ : AO1C - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data_4, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[57]\); - - \r.btag.I3_RNI3B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI3B7H[5]\); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.I3_RNI15923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.LVL_RNISEGA5[1]\ : OR3A - port map(A => \LVL[1]\, B => N_159, C => N_162, Y => N_32_i); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[28]\); - - \r.btag.CTX_RNIGS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_0_10, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data_5, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_1); - - \r.btag.LVL_RNIH476[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_5(2), - Y => N_764); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data_13, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[66]\); - - \r.btag.ACC_RNI48H5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_0(2), Y => N_734); - - \tlbcamo.hit_0_a3_0_RNO\ : NOR2A - port map(A => \un1_tag0[43]\, B => \N_170_1\, Y => - hit_0_a3_0_0); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data_15, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[68]\); - - \r.btag.PPN_RNIJK6B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_1(2), Y => N_756); - - \r.btag.PPN_RNIN47B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_1(2), Y => N_758); - - \r.btag.PPN_RNIBC5B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_1(2), Y => N_761); - - \tlbcamo.hit_0_a3_3\ : NAND2 - port map(A => N_163, B => hit_0_a3_3_0, Y => N_41); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[22]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[29]\); - - \r.btag.I1_RNI67OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN_RNIDS5B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_1(2), Y => N_753); - - \r.btag.PPN_RNI91V5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_1(2), Y => N_742); - - \r.btag.PPN_RNIDK5B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_1(2), Y => N_762); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data_11, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[64]\); - - \r.btag.I2_RNIS4511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNIVPUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_1, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[4]\); - - \r.btag.PPN_RNIF46B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_1(2), Y => N_754); - - \r.btag.PPN_RNI51V5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_1(2), Y => N_740); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78_0, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[25]\); - - \r.btag.VALID_RNI3JL26\ : OR3C - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE_i_0, - Y => N_43); - - \r.btag.CTX_RNI4IJG[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIBK5B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_1(2), Y => N_752); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[3]\); - - \tlbcamo.hit_0_a3_0\ : NAND2 - port map(A => N_165, B => hit_0_a3_0_0, Y => N_170); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data_7, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[60]\); - - \r.btag.I1_RNIPJSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNIUDUF[3]\, Y => h_i13_NE_1); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data_22, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[75]\); - - \r.btag.ACC_RNI68H5[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry_0(2), Y => N_735); - - \r.btag.I3_RNIS1VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNIS1VF[3]\); - - \r.btag.PPN_RNIBDQ3[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry(2), Y => N_743); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[1]\); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[11]\); - - \r.btag.LVL_RNI5GM6[1]\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.I2_RNIVPUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNIVPUF[1]\); - - \r.btag.PPN_RNIFS5B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_1(2), Y => N_763); - - \r.btag.I3_RNI3EE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI3B7H[5]\, Y => h_i32_NE_2); - - \r.btag.PPN_RNIJ1V5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_1(2), Y => N_747); - - \tlbcamo.hit_0_a3_4\ : OR2A - port map(A => N_200, B => N_204, Y => \N_42\); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data_12, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[65]\); - - \r.btag.VALID_RNIJTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[27]\); - - \r.btag.M_RNI0546\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_0(2), Y => N_738); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data_3, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[56]\); - - \r.btag.PPN_RNIPC7B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_1(2), Y => N_759); - - \r.btag.I1_RNI5N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI5N6H[5]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data_18, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNI9C5B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_1(2), Y => N_751); - - \r.btag.PPN_RNID1V5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_1(2), Y => N_744); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[9]\); - - \tlbcamo.hit_0_a3_7_RNO\ : OR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data_17, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_0_17, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[24]\); - - \r.btag.I1_RNIDJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIOTTF[1]\, Y => h_i13_NE_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data_16, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[37]\); - - \r.btag.I1_RNI76D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNI5N6H[5]\, Y => h_i13_NE_2); - - \tlbcamo.hit_0_a3_0_1\ : OR2A - port map(A => s2_flush, B => data_0, Y => \N_170_1\); - - \r.btag.CTX_RNICS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.PPN_RNI71V5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_1(2), Y => N_741); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[15]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_0_7, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \pteout[7]\); - - \r.btag.I2_RNIMMF57[0]\ : NOR2B - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE_i_0, Y => - \N_17_i_0\); - - \r.btag.PPN_RNI945B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_1(2), Y => N_760); - - \r.btag.I2_RNI73SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIL5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.PPN_RNIF1V5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_1(2), Y => N_745); - - \r.btag.ET_RNI85SA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_0(2), Y => N_732); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \LVL[0]\); - - \tlbcamo.hit_0_a3_1_0\ : NOR3C - port map(A => s2_flush_0, B => data_0, C => N_204, Y => - \N_169_1\); - - \r.btag.LVL_RNIDJT71[1]\ : AOI1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => N_38, Y => - N_16); - - \r.btag.LVL_RNI7G04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_765); - - \r.btag.I3_RNI9RSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNIMHUF[1]\, Y => h_i32_NE_0); - - \r.btag.I1_RNIPAH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \tlbcamo.hit_0_o3_0\ : NAND2 - port map(A => N_41, B => \N_42\, Y => N_165); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_0_6, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[30]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data_21, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[12]\); - - \r.btag.I1_RNIUDUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNIUDUF[3]\); - - \r.btag.I1_RNII4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIQ9UF[7]\, Y => h_i13_NE_3); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(0), Q => \pteout[16]\); - - \r.btag.I1_RNIOTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIOTTF[1]\); - - \r.btag.VALID_RNIC8L41\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => N_159); - - \tlbcamo.hit_0_o3_4\ : OR2 - port map(A => N_39, B => N_40, Y => N_163); - - \r.btag.SU_RNIOFKO1\ : OR3 - port map(A => N_200, B => SU, C => N_159, Y => N_44); - - \r.btag.CTX_RNI6P98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data_19, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[72]\); - - \tlbcamo.hit_0_a3_0_0\ : OR2B - port map(A => \N_169_1\, B => s2_flush_0, Y => \hit_0_a3_0\); - - \r.btag.CTX_RNI4HJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.I2_RNISE6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNISE6H[5]\); - - \r.btag.I2_RNIL5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIL5UF[3]\); - - \tlbcamo.hit_0_a3_7\ : NOR2 - port map(A => h_i32_NE, B => hit_0_a3_7_0, Y => N_39); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data_20, CLK => lclk_c, E => - tlbcam_write_op_1_0(0), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(0), Q => \pteout[18]\); - - \r.btag.CTX_RNIMO98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_4 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0 : in std_logic_vector(7 to 7); - tlbcam_write_op_1 : in std_logic_vector(5 to 5); - tlbcam_write_op_1_1_0 : in std_logic_vector(5 to 5); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(5 to 5); - ctx_0 : in std_logic_vector(7 downto 0); - LVL : out std_logic_vector(1 downto 0); - s2_entry_1_i_a2_1 : out std_logic_vector(0 to 0); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_2937_1 : in std_logic; - cam_hit_all_1_sqmuxa : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_42 : in std_logic; - N_635 : in std_logic; - N_639 : in std_logic; - N_632 : in std_logic; - N_634 : in std_logic; - N_594 : in std_logic; - N_596 : in std_logic; - N_620 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - hit_0_a3_0 : in std_logic; - N_200 : in std_logic; - N_170_1 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_204 : in std_logic; - hit : in std_logic - ); - -end mmutlbcam_0_0_4; - -architecture DEF_ARCH of mmutlbcam_0_0_4 is - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hit_0, hit_0_1, N_33, N_32_i, N_169_i, hit_0_a3_3_0, - N_17_i_0, M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNI1F6H[5]\, \un1_tag0[64]\, \I2_RNIQ5UF[3]\, - \un1_tag0[62]\, \I2_RNI4QUF[1]\, hit_0_a3_5_0, - \un1_tag0[43]\, hit_0_a3_7_0, SU, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI8B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNI12VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNIRHUF[1]\, h_i13_NE_5, h_i13_NE_2, - h_i13_NE_3, h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, - \un1_tag0[74]\, \I1_RNIV9UF[7]\, \un1_tag0[72]\, - \I1_RNIAN6H[5]\, \un1_tag0[70]\, \I1_RNI3EUF[3]\, - \un1_tag0[68]\, \I1_RNITTTF[1]\, h_c2_NE_5, h_c2_NE_2, - h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, h_c2_NE_1, - \un1_tag0[41]\, h_c2_7_i, \un1_tag0[39]\, h_c2_5_i, - \un1_tag0[37]\, h_c2_3_i, N_43, N_160, h_i13_NE_i_0, - h_c2_NE, h_i32_NE, N_161, N_159, N_170_i, N_165, N_44, - \LVL[1]\, N_162, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[40]\, \un1_tag0[42]\, - \un1_tag0[73]\, \un1_tag0[75]\, \un1_tag0[63]\, - \un1_tag0[67]\, N_38, N_16, \LVL[0]\, \un1_tag0[61]\, - \un1_tag0[65]\, \un1_tag0[59]\, \un1_tag0[57]\, - \un1_tag0[71]\, \un1_tag0[69]\, N_163, N_40, VALID_RNO_3, - N_15, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - - \r.btag.SU_RNI5F5O8\ : AO1 - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => - N_169_i); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_30); - - \r.btag.I2_RNILJ9E7[0]\ : NOR2B - port map(A => N_204, B => N_17_i_0, Y => hit_0_a3_3_0); - - \r.btag.I1_RNIQ7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.VALID_RNITCGSE2\ : NOR2 - port map(A => hit, B => hit_0, Y => s2_entry_1_i_a2_1(0)); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_12); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_20); - - \r.btag.I2_RNISOF57[0]\ : NOR2B - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE_i_0, Y => - N_17_i_0); - - \r.btag.I1_RNIV9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIV9UF[7]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[73]\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[69]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[38]\); - - \r.btag.I3_RNI12VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNI12VF[3]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.VALID_RNI3IP871\ : OR2B - port map(A => hit_0_1, B => N_170_i, Y => hit_0); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[57]\); - - \r.btag.VALID_RNI2ECOD\ : OR3B - port map(A => \un1_tag0[43]\, B => N_165, C => N_170_1, Y - => N_170_i); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_28); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_6); - - \r.btag.CTX_RNIOHJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_17); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_24); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_8); - - \r.btag.I1_RNITTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNITTTF[1]\); - - \r.btag.I1_RNIS4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIV9UF[7]\, Y => h_i13_NE_3); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[42]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_13); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[40]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_18); - - \r.btag.I1_RNIAN6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNIAN6H[5]\); - - \r.btag.CTX_RNI0P98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.SU_RNIAHKO1\ : OR3 - port map(A => N_200, B => SU, C => N_159, Y => N_44); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[59]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[35]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_16); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[41]\); - - \r.btag.I1_RNIDBH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_0); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_7); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_23); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[68]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_14); - - \r.btag.CTX_RNIDS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_31); - - \r.btag.LVL_RNIKDI44[0]\ : NOR2 - port map(A => \LVL[0]\, B => h_i13_NE_i_0, Y => N_162); - - \r.btag.I3_RNIV5923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[74]\); - - \r.btag.CTX_RNIBS44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_22); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[72]\); - - \r.btag.CTX_RNIOIJG[4]\ : NOR2B - port map(A => h_c2_NE_2, B => h_c2_NE_3, Y => h_c2_NE_5); - - \r.btag.CTX_RNIGP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.VALID_RNIP9L41\ : OR2A - port map(A => \un1_tag0[43]\, B => h_c2_NE, Y => N_159); - - \r.btag.LVL_RNIVKT71[1]\ : NOR2A - port map(A => h_c2_NE, B => N_38, Y => N_16); - - \r.btag.I2_RNI1F6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNI1F6H[5]\); - - \r.btag.CTX_RNIPS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.I1_RNIH6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNIAN6H[5]\, Y => h_i13_NE_2); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_27); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_21); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[66]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[75]\); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_15); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[60]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[65]\); - - \r.btag.I1_RNI7J934[0]\ : NOR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => - h_i13_NE_i_0); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_29); - - \r.btag.LVL_RNI8NC6D[1]\ : AO1B - port map(A => hit_0_a3_3_0, B => N_163, C => N_42, Y => - N_165); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \LVL[1]\); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[67]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_10); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[56]\); - - \r.btag.I2_RNIUS411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNI1F6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[63]\); - - \r.btag.I1_RNI3KSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI3EUF[3]\, Y => h_i13_NE_1); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_3, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.I2_RNI65511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI4QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => pteout_19); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_9); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_25); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[58]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_1); - - \r.btag.LVL_RNI14DGP[1]\ : NOR3C - port map(A => N_33, B => N_32_i, C => N_169_i, Y => hit_0_1); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[61]\); - - \r.btag.I3_RNIJRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNIRHUF[1]\, Y => h_i32_NE_0); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[64]\); - - \r.btag.I1_RNINJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNITTTF[1]\, Y => h_i13_NE_0); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[37]\); - - \r.btag.SU_RNID5KE1\ : AO1C - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.LVL_RNIC0I33[0]\ : OR2A - port map(A => h_i32_NE, B => \LVL[0]\, Y => N_161); - - \r.btag.I3_RNIDEE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI8B7H[5]\, Y => h_i32_NE_2); - - \r.btag.I2_RNIQ5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIQ5UF[3]\); - - \r.btag.I2_RNIL5623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.CTX_RNIG4711[0]\ : OR2B - port map(A => h_c2_NE_5, B => h_c2_NE_4, Y => h_c2_NE); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \un1_tag0[62]\); - - \r.btag.I3_RNIRHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIRHUF[1]\); - - \r.btag.LVL_RNI13NDB[0]\ : OR3B - port map(A => N_161, B => N_17_i_0, C => N_159, Y => N_33); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(5), Q => \LVL[0]\); - - \r.btag.CTX_RNIHS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.VALID_RNIU75PL3\ : NOR2 - port map(A => hit_0, B => N_2937_1, Y => - cam_hit_all_1_sqmuxa); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(5), Y => N_15); - - \r.btag.VALID_RNICML26\ : OR3C - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE_i_0, - Y => N_43); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_3); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[39]\); - - \r.btag.I2_RNI4QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI4QUF[1]\); - - \r.btag.CTX_RNI8P98[4]\ : XA1A - port map(A => ctx_0(4), B => \un1_tag0[39]\, C => h_c2_5_i, - Y => h_c2_NE_2); - - \r.btag.LVL_RNISAV7[1]\ : OR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.I2_RNIH3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIQ5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[71]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[36]\); - - \r.btag.LVL_RNIFGM6[1]\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.VALID_RNIOTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_26); - - \r.btag.I3_RNIVRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNI12VF[3]\, Y => h_i32_NE_1); - - \r.btag.LVL_RNIF6FM1[1]\ : OR2 - port map(A => N_16, B => N_200, Y => N_40); - - \r.btag.I1_RNI3EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI3EUF[3]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_3); - - \r.btag.LVL_RNIRHGA5[1]\ : OR3A - port map(A => \LVL[1]\, B => N_159, C => N_162, Y => N_32_i); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => pteout_2); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(5), Q => \un1_tag0[70]\); - - \r.btag.CTX_RNILS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => SU); - - \r.btag.I3_RNI8B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI8B7H[5]\); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(5), Q => pteout_11); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.LVL_RNIANN05[1]\ : OAI1 - port map(A => h_i32_NE, B => hit_0_a3_7_0, C => N_40, Y => - N_163); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1_0 : in std_logic_vector(1 to 1); - lvl_i_1 : in std_logic_vector(0 to 0); - hrdata_0_17 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_6 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(4 to 4); - tlbcam_write_op_1_1 : in std_logic_vector(4 to 4); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(4 to 4); - cam_hitaddr_12 : out std_logic_vector(2 to 2); - ctx_0 : in std_logic_vector(7 downto 0); - LVL : out std_logic_vector(1 downto 0); - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_634 : in std_logic; - N_594 : in std_logic; - N_596 : in std_logic; - N_169_1 : in std_logic; - un1_rst_i_0 : in std_logic; - s2_flush : in std_logic; - cam_hit_all_1_sqmuxa : in std_logic; - N_635 : in std_logic; - N_639 : in std_logic; - N_665 : in std_logic; - N_597 : in std_logic; - N_620 : in std_logic; - N_593 : in std_logic; - N_632 : in std_logic; - N_204 : in std_logic; - N_200 : in std_logic; - N_42 : in std_logic; - hit_i : out std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_170_1 : in std_logic - ); - -end mmutlbcam_0_0; - -architecture DEF_ARCH of mmutlbcam_0_0 is - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hit_0_0, N_233, N_234, hit_0_a3_0_0, \un1_tag0[43]\, - hit_0_a3_2_0, h_i32_NE, N_11, hit_0_a3_1_0, - M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNI0F6H[5]\, \un1_tag0[64]\, \I2_RNIP5UF[3]\, - \un1_tag0[62]\, \I2_RNI3QUF[1]\, hit_0_a3_5_0, - hit_0_a3_7_0, SU, \LVL[0]\, \LVL[1]\, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI7B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNI02VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNIQHUF[1]\, h_i13_NE_5, h_i13_NE_2, - h_i13_NE_3, h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, - \un1_tag0[74]\, \I1_RNIU9UF[7]\, \un1_tag0[72]\, - \I1_RNI9N6H[5]\, \un1_tag0[70]\, \I1_RNI2EUF[3]\, - \un1_tag0[68]\, \I1_RNISTTF[1]\, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, h_i13_NE, N_10, N_231, N_232, N_36, N_12, - N_34_i, N_37, N_15, N_32, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[57]\, \un1_tag0[63]\, - \un1_tag0[67]\, N_239, \un1_tag0[75]\, \un1_tag0[73]\, - \un1_tag0[71]\, \un1_tag0[69]\, \hit_i\, N_99, VALID_RNO, - N_9, \un1_tag0[61]\, \un1_tag0[65]\, \un1_tag0[59]\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - hit_i <= \hit_i\; - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_30); - - \r.btag.I1_RNI9BH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.I1_RNI1KSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI2EUF[3]\, Y => h_i13_NE_1); - - \r.btag.I2_RNIEOF57[0]\ : OR2A - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE, Y => N_10); - - \r.btag.LVL_RNIBQ1271[0]\ : NOR3 - port map(A => hit_0_0, B => N_231, C => N_232, Y => \hit_i\); - - \r.btag.I1_RNIQ4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIU9UF[7]\, Y => h_i13_NE_3); - - \r.btag.LVL_RNINMN05[1]\ : OA1C - port map(A => N_9, B => N_200, C => N_32, Y => N_15); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_12); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262_0, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_20); - - \r.btag.VALID_RNINTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.I2_RNIF5623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.I1_RNISTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNISTTF[1]\); - - \r.btag.I2_RNI0F6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNI0F6H[5]\); - - \r.btag.I1_RNILJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNISTTF[1]\, Y => h_i13_NE_0); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[73]\); - - \r.btag.I2_RNIP5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIP5UF[3]\); - - \r.btag.I1_RNIM7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[69]\); - - \r.btag.CTX_RNIOS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.I3_RNI02VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNI02VF[3]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[38]\); - - \r.btag.SU_RNI0QDH8\ : OA1 - port map(A => N_36, B => N_37, C => N_169_1, Y => N_231); - - \r.btag.I3_RNIHRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNIQHUF[1]\, Y => h_i32_NE_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[57]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_28); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_6); - - \r.btag.LVL_RNI32NDB[0]\ : NOR2 - port map(A => hit_0_a3_2_0, B => N_10, Y => N_234); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_0_10, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_17); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_0_17, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_24); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_8); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[42]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_0_6, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_13); - - \r.btag.I1_RNI2EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI2EUF[3]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[40]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_18); - - \r.btag.LVL_RNILKT71[1]\ : AO1B - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => N_239, Y => - N_9); - - \r.btag.I2_RNI45511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI3QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[59]\); - - \r.btag.CTX_RNIEP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[35]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_16); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[41]\); - - \r.btag.VALID_RNINLL26\ : NOR3B - port map(A => N_12, B => hit_0_a3_5_0, C => h_i13_NE, Y => - N_36); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_0); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_7); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_23); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[68]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_0_7, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_14); - - \r.btag.CTX_RNIIS44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0(4), Y => h_c2_4_i); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_31); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[74]\); - - \r.btag.CTX_RNIUO98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_22); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[72]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_27); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_21); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[66]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[75]\); - - \r.btag.I2_RNIF3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIP5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_15); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[60]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[65]\); - - \r.btag.I3_RNI7B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI7B7H[5]\); - - \r.btag.CTX_RNIAS44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.SU_RNI15KE1\ : AO1A - port map(A => \LVL[0]\, B => SU, C => N_9, Y => N_12); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_29); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1_0(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \LVL[1]\); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[67]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_10); - - \r.btag.LVL_RNI927RS4[0]\ : OR2B - port map(A => \hit_i\, B => cam_hit_all_1_sqmuxa, Y => - cam_hitaddr_12(2)); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[56]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[63]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO, CLK => lclk_c, Q => \un1_tag0[43]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264_0, CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => pteout_19); - - \r.btag.LVL_RNIT3U51[1]\ : NOR2A - port map(A => \LVL[1]\, B => N_11, Y => hit_0_a3_1_0); - - \r.btag.LVL_RNI8HGA5[0]\ : OA1A - port map(A => h_i13_NE, B => \LVL[0]\, C => hit_0_a3_1_0, Y - => N_233); - - \r.btag.I1_RNI9N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI9N6H[5]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_9); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78_0, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_25); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[58]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_1); - - \r.btag.VALID_RNIG9L41\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => N_11); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[61]\); - - \r.btag.LVL_RNIDGM6[1]\ : OR2A - port map(A => SU, B => \LVL[1]\, Y => N_239); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[64]\); - - \r.btag.CTX_RNIKHJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[37]\); - - \r.btag.I3_RNITRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNI02VF[3]\, Y => h_i32_NE_1); - - \r.btag.LVL_RNIIG8A3[1]\ : NOR2A - port map(A => hit_0_a3_7_0, B => h_i32_NE, Y => N_32); - - \r.btag.LVL_RNIBJ7OG[0]\ : OR2 - port map(A => N_233, B => N_234, Y => hit_0_0); - - \r.btag.I3_RNIBEE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI7B7H[5]\, Y => h_i32_NE_2); - - \r.btag.CTX_RNICS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \un1_tag0[62]\); - - \r.btag.LVL_RNIPAV7[1]\ : NOR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(4), Q => \LVL[0]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(4), Y => N_99); - - \r.btag.I3_RNIP5923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_99, B => un1_rst_i_0, Y => VALID_RNO); - - \r.btag.I1_RNIF6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNI9N6H[5]\, Y => h_i13_NE_2); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[39]\); - - \r.btag.LVL_RNIU91FC[1]\ : OR3A - port map(A => N_204, B => N_10, C => N_15, Y => N_34_i); - - \r.btag.I2_RNI3QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI3QUF[1]\); - - \r.btag.I1_RNIU9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIU9UF[7]\); - - \r.btag.CTX_RNIGS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[71]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[36]\); - - \r.btag.LVL_RNIL9784[0]\ : AO1A - port map(A => \LVL[0]\, B => h_i32_NE, C => N_11, Y => - hit_0_a3_2_0); - - \r.btag.CTX_RNIKIJG[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_26); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_3); - - \r.btag.VALID_RNIPMVH\ : NOR2A - port map(A => \un1_tag0[43]\, B => N_170_1, Y => - hit_0_a3_0_0); - - \r.btag.I3_RNIQHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIQHUF[1]\); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => pteout_2); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(4), Q => \un1_tag0[70]\); - - \r.btag.I2_RNISS411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNI0F6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.CTX_RNIKS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.SU_RNI0HKO1\ : NOR3 - port map(A => N_200, B => SU, C => N_11, Y => N_37); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => SU); - - \r.btag.I1_RNIVI934[0]\ : OR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => h_i13_NE); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1(4), Q => pteout_11); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.VALID_RNI0DCOD\ : AOI1B - port map(A => N_34_i, B => N_42, C => hit_0_a3_0_0, Y => - N_232); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_5 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0 : in std_logic_vector(7 to 7); - tlbcam_write_op_1 : in std_logic_vector(1 to 1); - tlbcam_write_op_1_1 : in std_logic_vector(1 to 1); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - tlbcam_write_op_1_0 : in std_logic_vector(1 to 1); - s2_entry_5 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_4 : in std_logic_vector(2 to 2); - s2_entry_3 : in std_logic_vector(2 to 2); - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - ctx_0 : in std_logic_vector(7 downto 0); - s2_entry_1_i_a2_0 : out std_logic_vector(0 to 0); - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_838 : out std_logic; - N_851 : out std_logic; - N_852 : out std_logic; - N_845 : out std_logic; - N_867 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_200 : in std_logic; - N_42 : in std_logic; - N_866 : out std_logic; - N_596 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_651 : in std_logic; - N_865 : out std_logic; - N_864 : out std_logic; - N_863 : out std_logic; - N_862 : out std_logic; - N_861 : out std_logic; - N_860 : out std_logic; - N_859 : out std_logic; - N_858 : out std_logic; - N_857 : out std_logic; - N_856 : out std_logic; - N_855 : out std_logic; - N_854 : out std_logic; - N_853 : out std_logic; - N_850 : out std_logic; - N_849 : out std_logic; - N_848 : out std_logic; - N_847 : out std_logic; - N_846 : out std_logic; - N_844 : out std_logic; - N_843 : out std_logic; - N_842 : out std_logic; - N_841 : out std_logic; - N_840 : out std_logic; - N_837 : out std_logic; - N_836 : out std_logic; - N_835 : out std_logic; - N_834 : out std_logic; - N_634 : in std_logic; - N_632 : in std_logic; - N_662 : in std_logic; - N_650 : in std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - hit_0_a3_0 : in std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_612 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_204 : in std_logic; - N_170_1 : in std_logic; - hit_i_0 : out std_logic; - N_557 : in std_logic - ); - -end mmutlbcam_0_0_5; - -architecture DEF_ARCH of mmutlbcam_0_0_5 is - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hit_0_1, N_33, N_32, N_169, hit_0_a3_0_0, - \un1_tag0[43]\, hit_0_a3_3_0, h_i13_NE_i_0, - M_1_sqmuxa_0_o3_1_4, hit_0_a3_2_0, \LVL[0]\, h_i32_NE_i_0, - N_159, \I2_RNITE6H[5]\, \I2_RNIPDUF[4]\, - M_1_sqmuxa_0_o3_1_3, \I2_RNIM5UF[3]\, \I2_RNIJTTF[2]\, - M_1_sqmuxa_0_o3_1_0, \un1_tag0[62]\, \I2_RNI0QUF[1]\, - hit_0_a3_5_0, hit_0_a3_7_0, SU, \LVL[1]\, h_i13_NE_5, - \I1_RNI6N6H[5]\, \I1_RNI3F6H[4]\, h_i13_NE_3, - \un1_tag0[74]\, \I1_RNIR9UF[7]\, h_i13_NE_1, - \un1_tag0[70]\, \I1_RNIVDUF[3]\, h_i13_NE_0, - \un1_tag0[68]\, \I1_RNIPTTF[1]\, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI4B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNIT1VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNINHUF[1]\, h_c2_NE_4, h_c2_1_i, - h_c2_0_i, h_c2_NE_1, h_c2_NE_3, \un1_tag0[41]\, h_c2_7_i, - h_c2_NE_2, \un1_tag0[39]\, h_c2_5_i, \un1_tag0[37]\, - h_c2_3_i, h_c2_NE_i_0, N_44, N_43, N_160, N_39, N_162, - \hit_i_0\, N_165, \un1_tag0[69]\, \un1_tag0[71]\, - \un1_tag0[35]\, \un1_tag0[36]\, \un1_tag0[38]\, - \un1_tag0[40]\, \un1_tag0[42]\, \un1_tag0[64]\, - \un1_tag0[66]\, \un1_tag0[57]\, \un1_tag0[59]\, - \pteout[0]\, \pteout[1]\, \pteout[2]\, \pteout[3]\, - \pteout[6]\, \pteout[7]\, \pteout[8]\, \pteout[9]\, - \pteout[10]\, \pteout[12]\, \pteout[13]\, \pteout[14]\, - \pteout[15]\, \pteout[16]\, \pteout[19]\, \pteout[20]\, - \pteout[21]\, \pteout[22]\, \pteout[23]\, \pteout[24]\, - \pteout[25]\, \pteout[26]\, \pteout[27]\, \pteout[28]\, - \pteout[29]\, \pteout[30]\, \pteout[31]\, \un1_tag0[72]\, - \un1_tag0[73]\, \un1_tag0[75]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[67]\, \un1_tag0[61]\, N_16, - N_163, VALID_RNO_4, N_15, \pteout[11]\, \pteout[18]\, - \pteout[17]\, \pteout[4]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - hit_i_0 <= \hit_i_0\; - - \r.btag.LVL_RNI4JC6D[1]\ : OA1 - port map(A => N_163, B => hit_0_a3_3_0, C => N_42, Y => - N_165); - - \r.btag.LVL_RNIFFGA5[1]\ : NOR3A - port map(A => \LVL[1]\, B => N_159, C => N_162, Y => N_32); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[8]\); - - \r.btag.I2_RNIJTTF[2]\ : XOR2 - port map(A => \un1_tag0[64]\, B => N_650, Y => - \I2_RNIJTTF[2]\); - - \r.btag.I1_RNI7I934[0]\ : NOR3C - port map(A => h_i13_NE_1, B => h_i13_NE_0, C => h_i13_NE_5, - Y => h_i13_NE_i_0); - - \r.btag.PPN_RNIL106[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_3(2), Y => N_846); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \LVL[1]\); - - \r.btag.I2_RNITH9E7[4]\ : OR3C - port map(A => h_i13_NE_i_0, B => M_1_sqmuxa_0_o3_1_4, C => - N_204, Y => hit_0_a3_3_0); - - \r.btag.I2_RNIU4511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI0QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.LVL_RNIUKN05[1]\ : OA1C - port map(A => N_16, B => N_200, C => N_39, Y => N_163); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[63]\); - - \r.btag.I3_RNINRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNIT1VF[3]\, Y => h_i32_NE_1); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[19]\); - - \r.btag.CTX_RNIDS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.ACC_RNIHOI5[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry_3(2), Y => N_837); - - \r.btag.I1_RNI3F6H[4]\ : XOR2 - port map(A => \un1_tag0[72]\, B => N_651, Y => - \I1_RNI3F6H[4]\); - - \r.btag.I1_RNIR9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIR9UF[7]\); - - \r.btag.LVL_RNINF8A3[1]\ : NOR2B - port map(A => hit_0_a3_7_0, B => h_i32_NE_i_0, Y => N_39); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[67]\); - - \r.btag.SU_RNI1NCN1\ : OR3 - port map(A => N_200_0, B => SU, C => N_159, Y => N_44); - - \r.btag.I2_RNIPDUF[4]\ : XOR2 - port map(A => \un1_tag0[66]\, B => N_662, Y => - \I2_RNIPDUF[4]\); - - \r.btag.I1_RNI6N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI6N6H[5]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(1), Y => N_15); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[41]\); - - \r.btag.VALID_RNIQ9NA81\ : NOR2B - port map(A => N_557, B => \hit_i_0\, Y => - s2_entry_1_i_a2_0(0)); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => SU); - - \r.btag.PPN_RNI0D8B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_4(2), Y => N_859); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[36]\); - - \r.btag.CTX_RNILS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.CTX_RNI9S44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.PPN_RNIKK6B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_4(2), Y => N_862); - - \r.btag.ACC_RNID4D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_838); - - \r.btag.VALID_RNIKTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[10]\); - - \r.btag.PPN_RNIF106[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_3(2), Y => N_843); - - \r.btag.ACC_RNIFOI5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_3(2), Y => N_836); - - \r.btag.PPN_RNIHC6B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_3(2), Y => N_853); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN_RNIT106[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_3(2), Y => N_850); - - \r.btag.I3_RNIT1VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNIT1VF[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.C_RNINK56\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_3(2), Y => N_841); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[58]\); - - \r.btag.CTX_RNI8P98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_4); - - \r.btag.M_RNIBL56\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_3(2), Y => N_840); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[66]\); - - \r.btag.I1_RNIRJSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNIVDUF[3]\, Y => h_i13_NE_1); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[68]\); - - \r.btag.SU_RNI8ITM8\ : AOI1 - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => N_169); - - \r.btag.PPN_RNID106[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_3(2), Y => N_842); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[22]\); - - \r.btag.LVL_RNI9VMDB[0]\ : NOR3B - port map(A => h_i13_NE_i_0, B => M_1_sqmuxa_0_o3_1_4, C => - hit_0_a3_2_0, Y => N_33); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[29]\); - - \r.btag.CTX_RNIOO98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_4, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[4]\); - - \r.btag.VALID_RNIQAH771\ : OA1B - port map(A => N_165, B => hit_0_a3_0_0, C => hit_0_1, Y => - \hit_i_0\); - - \r.btag.PPN_RNIO47B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_4(2), Y => N_864); - - \r.btag.PPN_RNIMS6B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_4(2), Y => N_863); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[25]\); - - \r.btag.I2_RNITE6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNITE6H[5]\); - - \r.btag.VALID_RNIL8L41\ : OR2B - port map(A => \un1_tag0[43]\, B => h_c2_NE_i_0, Y => N_159); - - \r.btag.PPN_RNI2L8B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_4(2), Y => N_860); - - \r.btag.PPN_RNIN47B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_3(2), Y => N_856); - - \r.btag.I2_RNIT4623[4]\ : NOR3C - port map(A => \I2_RNITE6H[5]\, B => \I2_RNIPDUF[4]\, C => - M_1_sqmuxa_0_o3_1_3, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.PPN_RNIQC7B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_4(2), Y => N_865); - - \r.btag.PPN_RNIPDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_851); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[3]\); - - \r.btag.ET_RNIJLTA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_3(2), Y => N_834); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[1]\); - - \r.btag.CTX_RNI0P98[4]\ : XA1A - port map(A => ctx_0(4), B => \un1_tag0[39]\, C => h_c2_5_i, - Y => h_c2_NE_2); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[11]\); - - \r.btag.I1_RNIK4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIR9UF[7]\, Y => h_i13_NE_3); - - \r.btag.I2_RNIM5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIM5UF[3]\); - - \r.btag.PPN_RNISS7B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_4(2), Y => N_857); - - \r.btag.LVL_RNIGCI44[0]\ : NOR2 - port map(A => \LVL[0]\, B => h_i13_NE_i_0, Y => N_162); - - \r.btag.CTX_RNIG3711[4]\ : NOR3C - port map(A => h_c2_NE_3, B => h_c2_NE_2, C => h_c2_NE_4, Y - => h_c2_NE_i_0); - - \r.btag.PPN_RNIP106[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_3(2), Y => N_848); - - \r.btag.PPN_RNIDDQ3[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry(2), Y => N_845); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[20]\); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[42]\); - - \r.btag.I2_RNI0QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI0QUF[1]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[65]\); - - \r.btag.LVL_RNIJ476[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_5(2), - Y => N_866); - - \r.btag.PPN_RNI9G09[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry(2), Y => N_852); - - \r.btag.LVL_RNI58784[0]\ : AO1D - port map(A => \LVL[0]\, B => h_i32_NE_i_0, C => N_159, Y - => hit_0_a3_2_0); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[27]\); - - \r.btag.CTX_RNI8HJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[56]\); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[9]\); - - \r.btag.I2_RNI78112[0]\ : NOR3C - port map(A => \I2_RNIM5UF[3]\, B => \I2_RNIJTTF[2]\, C => - M_1_sqmuxa_0_o3_1_0, Y => M_1_sqmuxa_0_o3_1_3); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[24]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I3_RNI5EE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI4B7H[5]\, Y => h_i32_NE_2); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[37]\); - - \r.btag.I1_RNIVDUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNIVDUF[3]\); - - \r.btag.I1_RNITAH32[4]\ : NOR3C - port map(A => \I1_RNI6N6H[5]\, B => \I1_RNI3F6H[4]\, C => - h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[15]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[14]\); - - \r.btag.LVL_RNI9G04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_867); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \pteout[7]\); - - \r.btag.I3_RNINHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNINHUF[1]\); - - \r.btag.I1_RNIPTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIPTTF[1]\); - - \r.btag.PPN_RNILS6B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_3(2), Y => N_855); - - \r.btag.CTX_RNIHS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.I1_RNIFJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIPTTF[1]\, Y => h_i13_NE_0); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \LVL[0]\); - - \r.btag.PPN_RNI4T8B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_4(2), Y => N_861); - - \r.btag.I3_RNIBRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNINHUF[1]\, Y => h_i32_NE_0); - - \r.btag.I3_RNI75923[0]\ : NOR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE_i_0); - - \r.btag.LVL_RNINJT71[1]\ : AO1A - port map(A => \LVL[1]\, B => SU, C => h_c2_NE_i_0, Y => - N_16); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[30]\); - - \r.btag.SU_RNIT3KE1\ : AO1A - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.PPN_RNIR106[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_3(2), Y => N_849); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[12]\); - - \r.btag.VALID_RNIMMVH\ : OR2A - port map(A => \un1_tag0[43]\, B => N_170_1, Y => - hit_0_a3_0_0); - - \r.btag.CTX_RNI7S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(1), Q => \pteout[16]\); - - \r.btag.PPN_RNIH106[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_3(2), Y => N_844); - - \r.btag.VALID_RNIOJL26\ : OR3C - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE_i_0, - Y => N_43); - - \r.btag.PPN_RNIU48B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_4(2), Y => N_858); - - \r.btag.ET_RNILTTA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_3(2), Y => N_835); - - \r.btag.PPN_RNIN106[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_3(2), Y => N_847); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[72]\); - - \r.btag.PPN_RNIJK6B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_3(2), Y => N_854); - - \r.btag.LVL_RNIGAV7[1]\ : NOR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.LVL_RNI015FP[1]\ : OR3 - port map(A => N_33, B => N_32, C => N_169, Y => hit_0_1); - - \r.btag.I3_RNI4B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI4B7H[5]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(1), Q => \un1_tag0[73]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(1), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ0 is - - port( aaddr : out std_logic_vector(31 downto 2); - address : in std_logic_vector(31 downto 2); - s2_entry : in std_logic_vector(2 downto 0); - dr1write_0_sqmuxa : in std_logic; - syncramZ0_VCC : in std_logic; - lclk_c : in std_logic - ); - -end syncramZ0; - -architecture DEF_ARCH of syncramZ0 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_3 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(2 downto 0) := (others => 'U'); - datain : in std_logic_vector(29 downto 0) := (others => 'U'); - dataout : out std_logic_vector(29 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_3 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_3(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_3 - port map(clk => lclk_c, address(2) => s2_entry(2), - address(1) => s2_entry(1), address(0) => s2_entry(0), - datain(29) => address(31), datain(28) => address(30), - datain(27) => address(29), datain(26) => address(28), - datain(25) => address(27), datain(24) => address(26), - datain(23) => address(25), datain(22) => address(24), - datain(21) => address(23), datain(20) => address(22), - datain(19) => address(21), datain(18) => address(20), - datain(17) => address(19), datain(16) => address(18), - datain(15) => address(17), datain(14) => address(16), - datain(13) => address(15), datain(12) => address(14), - datain(11) => address(13), datain(10) => address(12), - datain(9) => address(11), datain(8) => address(10), - datain(7) => address(9), datain(6) => address(8), - datain(5) => address(7), datain(4) => address(6), - datain(3) => address(5), datain(2) => address(4), - datain(1) => address(3), datain(0) => address(2), - dataout(29) => aaddr(31), dataout(28) => aaddr(30), - dataout(27) => aaddr(29), dataout(26) => aaddr(28), - dataout(25) => aaddr(27), dataout(24) => aaddr(26), - dataout(23) => aaddr(25), dataout(22) => aaddr(24), - dataout(21) => aaddr(23), dataout(20) => aaddr(22), - dataout(19) => aaddr(21), dataout(18) => aaddr(20), - dataout(17) => aaddr(19), dataout(16) => aaddr(18), - dataout(15) => aaddr(17), dataout(14) => aaddr(16), - dataout(13) => aaddr(15), dataout(12) => aaddr(14), - dataout(11) => aaddr(13), dataout(10) => aaddr(12), - dataout(9) => aaddr(11), dataout(8) => aaddr(10), - dataout(7) => aaddr(9), dataout(6) => aaddr(8), - dataout(5) => aaddr(7), dataout(4) => aaddr(6), - dataout(3) => aaddr(5), dataout(2) => aaddr(4), - dataout(1) => aaddr(3), dataout(0) => aaddr(2), enable - => syncramZ0_VCC, write => dr1write_0_sqmuxa); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_3 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_17 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_6 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(7 to 7); - tlbcam_write_op_1_1_0 : in std_logic_vector(7 to 7); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(7 to 7); - s2_entry_1_i_a2_1_2 : in std_logic_vector(1 to 1); - ctx_0 : in std_logic_vector(7 downto 0); - LVL : out std_logic_vector(1 downto 0); - s2_entry_1_i_a2_0 : in std_logic_vector(0 to 0); - s2_entry_1_i_a2_2 : out std_logic_vector(0 to 0); - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_42 : in std_logic; - N_200 : in std_logic; - un1_rst_i_0 : in std_logic; - N_596 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_634 : in std_logic; - N_632 : in std_logic; - N_631_i : in std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - s2_flush_0 : in std_logic; - hit_0_a3_0 : in std_logic; - N_2937_1 : out std_logic; - N_170_1 : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_204 : in std_logic - ); - -end mmutlbcam_0_0_3; - -architecture DEF_ARCH of mmutlbcam_0_0_3 is - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_170, hit_0_1, N_33, N_32, N_169, hit_0_a3_3_0, N_17, - hit_0_a3_1_0, N_159, M_1_sqmuxa_0_o3_1_4, - M_1_sqmuxa_0_o3_1_1, M_1_sqmuxa_0_o3_1_0, - M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, \I2_RNI3F6H[5]\, - \un1_tag0[64]\, \I2_RNIS5UF[3]\, \un1_tag0[62]\, - \I2_RNI6QUF[1]\, hit_0_a3_5_0, \un1_tag0[43]\, - hit_0_a3_7_0, SU, \LVL[1]\, h_i13_NE_5, h_i13_NE_2, - h_i13_NE_3, h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, - \un1_tag0[74]\, \I1_RNI1AUF[7]\, \un1_tag0[72]\, - \I1_RNICN6H[5]\, \un1_tag0[70]\, \I1_RNI5EUF[3]\, - \un1_tag0[68]\, \I1_RNIVTTF[1]\, h_i32_NE_3, - \I3_RNITHUF[1]\, \I3_RNIQ9UF[0]\, h_i32_NE_1, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNIAB7H[5]\, \un1_tag0[58]\, - \I3_RNI32VF[3]\, hit_0_a3_6_0, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, h_i13_NE, N_165, N_44, N_39, \LVL[0]\, N_43, - N_160, \LVL_RNIQ0I33[0]\, N_15, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \un1_tag0[56]\, \un1_tag0[57]\, - \un1_tag0[59]\, \un1_tag0[73]\, \un1_tag0[75]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, - \un1_tag0[61]\, VALID_RNO_2, N_38, N_16, N_163, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - LVL(1) <= \LVL[1]\; - LVL(0) <= \LVL[0]\; - - \r.btag.I3_RNIAB7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNIAB7H[5]\); - - \r.btag.VALID_RNIQTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_30); - - \r.btag.VALID_RNIMNL26\ : NOR3B - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE, Y - => N_43); - - \r.btag.I1_RNIL6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNICN6H[5]\, Y => h_i13_NE_2); - - \r.btag.LVL_RNIT4NDB[0]\ : NOR3A - port map(A => \LVL_RNIQ0I33[0]\, B => N_159, C => N_17, Y - => N_33); - - \r.btag.VALID_RNIRLBGE2\ : OR3A - port map(A => s2_entry_1_i_a2_1_2(1), B => N_170, C => - hit_0_1, Y => N_2937_1); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_12); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_20); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[73]\); - - \r.btag.I2_RNI6QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI6QUF[1]\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[69]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[38]\); - - \r.btag.I2_RNI16623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[57]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_28); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_6); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_0_10, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_17); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_0_17, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_24); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_8); - - \r.btag.I2_RNI3F6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNI3F6H[5]\); - - \r.btag.CTX_RNILS44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0(4), Y => h_c2_4_i); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[42]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_0_6, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_13); - - \r.btag.CTX_RNI0IJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[40]\); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_18); - - \r.btag.I2_RNI2T411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNI3F6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.LVL_RNI0G5FP[0]\ : OR3 - port map(A => N_33, B => N_32, C => N_169, Y => hit_0_1); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[59]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[35]\); - - \r.btag.I2_RNIA5511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI6QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_16); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[41]\); - - \r.btag.I3_RNIHEE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNIAB7H[5]\, Y => h_i32_NE_2); - - \r.btag.I2_RNIHK9E7[0]\ : OR2A - port map(A => N_204, B => N_17, Y => hit_0_a3_3_0); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_0); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_7); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_23); - - \r.btag.SU_RNIIENI\ : OR2 - port map(A => SU, B => N_200_0, Y => hit_0_a3_6_0); - - \r.btag.I1_RNI28OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[68]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_0_7, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_14); - - \r.btag.LVL_RNIR4U51[1]\ : NOR2A - port map(A => \LVL[1]\, B => N_159, Y => hit_0_a3_1_0); - - \r.btag.LVL_RNIAPC6D[1]\ : OA1 - port map(A => N_163, B => hit_0_a3_3_0, C => N_42, Y => - N_165); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_31); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[74]\); - - \r.btag.I3_RNI3STV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNI32VF[3]\, Y => h_i32_NE_1); - - \r.btag.CTX_RNIRS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.CTX_RNIFS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.LVL_RNIQ0I33[0]\ : AO1 - port map(A => h_i32_NE_3, B => h_i32_NE_2, C => \LVL[0]\, Y - => \LVL_RNIQ0I33[0]\); - - \r.btag.I2_RNIS5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIS5UF[3]\); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_22); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[72]\); - - \r.btag.I1_RNIVTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIVTTF[1]\); - - \r.btag.CTX_RNINS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.VALID_RNIBAL41\ : OR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => N_159); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_27); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_21); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[66]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[75]\); - - \r.btag.VALID_RNI0A9IF2\ : NOR3A - port map(A => s2_entry_1_i_a2_0(0), B => N_170, C => - hit_0_1, Y => s2_entry_1_i_a2_2(0)); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_15); - - \r.btag.I3_RNIQ9UF[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => N_631_i, Y => - \I3_RNIQ9UF[0]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[60]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[65]\); - - \r.btag.I1_RNICN6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNICN6H[5]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_29); - - \r.btag.LVL_RNIDH8A3[1]\ : NOR3C - port map(A => h_i32_NE_2, B => h_i32_NE_3, C => - hit_0_a3_7_0, Y => N_39); - - \r.btag.LVL_RNI2BV7[1]\ : NOR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.LVL_RNI1JGA5[0]\ : OA1A - port map(A => h_i13_NE, B => \LVL[0]\, C => hit_0_a3_1_0, Y - => N_32); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \LVL[1]\); - - \r.btag.I3_RNIQNQV1[0]\ : NOR3C - port map(A => \I3_RNITHUF[1]\, B => \I3_RNIQ9UF[0]\, C => - h_i32_NE_1, Y => h_i32_NE_3); - - \r.btag.I1_RNI7KSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI5EUF[3]\, Y => h_i13_NE_1); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[67]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_10); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[56]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[63]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_2, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.VALID_RNI6GCOD\ : NOR3A - port map(A => \un1_tag0[43]\, B => N_170_1, C => N_165, Y - => N_170); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => pteout_19); - - \r.btag.CTX_RNI4P98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_9); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78_0, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_25); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[58]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_1); - - \r.btag.LVL_RNIGON05[1]\ : OA1B - port map(A => N_200, B => N_16, C => N_39, Y => N_163); - - \r.btag.I3_RNI32VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNI32VF[3]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[61]\); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[64]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[37]\); - - \r.btag.I1_RNINJ934[0]\ : OR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => h_i13_NE); - - \r.btag.I1_RNI5EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI5EUF[3]\); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \un1_tag0[62]\); - - \r.btag.I1_RNIRJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIVTTF[1]\, Y => h_i13_NE_0); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(7), Q => \LVL[0]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(7), Y => N_15); - - \r.btag.LVL_RNIJLT71[1]\ : AOI1 - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => N_38, Y => - N_16); - - \r.btag.CTX_RNIDS44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_2); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[39]\); - - \r.btag.LVL_RNIJGM6[1]\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.I3_RNITHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNITHUF[1]\); - - \r.btag.I2_RNIOPF57[0]\ : OR2A - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE, Y => N_17); - - \r.btag.CTX_RNIKP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[71]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[36]\); - - \r.btag.SU_RNITOCN1\ : NOR2 - port map(A => hit_0_a3_6_0, B => N_159, Y => N_44); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_26); - - \r.btag.CTX_RNIJS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.I1_RNI1AUF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNI1AUF[7]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_3); - - \r.btag.I1_RNILBH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.VALID_RNI2OTM8\ : OA1B - port map(A => N_43, B => N_44, C => hit_0_a3_0, Y => N_169); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => pteout_2); - - \r.btag.SU_RNI56KE1\ : AO1C - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.I1_RNI05411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNI1AUF[7]\, Y => h_i13_NE_3); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(7), Q => \un1_tag0[70]\); - - \r.btag.I2_RNIL3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIS5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.CTX_RNI0JJG[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => SU); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1(7), Q => pteout_11); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_6 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1 : in std_logic_vector(2 to 2); - tlbcam_write_op_1_1 : in std_logic_vector(2 to 2); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_7 : in std_logic; - hrdata_6 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - tlbcam_write_op_1_0 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(1 to 1); - s2_entry_3 : in std_logic_vector(2 to 2); - s2_entry_2 : in std_logic_vector(2 to 2); - s2_entry_1 : in std_logic_vector(2 to 2); - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_7 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - ctx_0 : in std_logic_vector(7 downto 0); - LVL_0_d0 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_770 : out std_logic; - N_783 : out std_logic; - N_777 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_631_i : in std_logic; - N_632 : in std_logic; - N_634 : in std_logic; - N_596 : in std_logic; - N_42 : in std_logic; - N_200 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_799 : out std_logic; - N_797 : out std_logic; - N_796 : out std_logic; - N_795 : out std_logic; - N_794 : out std_logic; - N_793 : out std_logic; - N_792 : out std_logic; - N_791 : out std_logic; - N_790 : out std_logic; - N_789 : out std_logic; - N_788 : out std_logic; - N_787 : out std_logic; - N_786 : out std_logic; - N_785 : out std_logic; - N_784 : out std_logic; - N_782 : out std_logic; - N_781 : out std_logic; - N_780 : out std_logic; - N_779 : out std_logic; - N_778 : out std_logic; - N_776 : out std_logic; - N_775 : out std_logic; - N_774 : out std_logic; - N_773 : out std_logic; - N_772 : out std_logic; - N_769 : out std_logic; - N_768 : out std_logic; - N_767 : out std_logic; - N_766 : out std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - hit_0_a3_0 : in std_logic; - N_2937_1 : in std_logic; - N_557 : in std_logic; - N_2937 : out std_logic; - hit : in std_logic; - N_3068 : out std_logic; - N_170_1 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_204 : in std_logic - ); - -end mmutlbcam_0_0_6; - -architecture DEF_ARCH of mmutlbcam_0_0_6 is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal cam_hit_all_1_2_i_a4_1, N_33, N_32, VALID_RNI7JTM8, - hit_0_a3_3_0, N_17_i_0, hit_0_a3_1_0, \LVL[1]\, N_159, - M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNIUE6H[5]\, \un1_tag0[64]\, \I2_RNIN5UF[3]\, - \un1_tag0[62]\, \I2_RNI1QUF[1]\, hit_0_a3_5_0, - \un1_tag0[43]\, hit_0_a3_7_0, SU, h_i32_NE_3, - \I3_RNIOHUF[1]\, \I3_RNIL9UF[0]\, h_i32_NE_1, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI5B7H[5]\, \un1_tag0[58]\, - \I3_RNIU1VF[3]\, h_i13_NE_5, h_i13_NE_2, h_i13_NE_3, - h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, \un1_tag0[74]\, - \I1_RNIS9UF[7]\, \un1_tag0[72]\, \I1_RNI7N6H[5]\, - \un1_tag0[70]\, \I1_RNI0EUF[3]\, \un1_tag0[68]\, - \I1_RNIQTTF[1]\, hit_0_a3_6_0, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, h_c2_NE_4, h_c2_1_i, h_c2_0_i, - h_c2_NE_1, \un1_tag0[41]\, h_c2_7_i, \un1_tag0[37]\, - h_c2_3_i, h_i13_NE_i_0, N_43, N_160, N_170, N_165, N_44, - N_39, N_161, \LVL[0]\, \N_3068\, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[35]\, \un1_tag0[36]\, - \un1_tag0[38]\, \un1_tag0[39]\, \un1_tag0[40]\, - \un1_tag0[42]\, \pteout[0]\, \pteout[1]\, \pteout[2]\, - \pteout[3]\, \pteout[6]\, \pteout[7]\, \pteout[8]\, - \pteout[9]\, \pteout[10]\, \pteout[12]\, \pteout[13]\, - \pteout[14]\, \pteout[15]\, \pteout[16]\, \pteout[18]\, - \pteout[19]\, \pteout[20]\, \pteout[21]\, \pteout[22]\, - \pteout[23]\, \pteout[24]\, \pteout[25]\, \pteout[26]\, - \pteout[27]\, \pteout[28]\, \pteout[29]\, \pteout[30]\, - \pteout[31]\, \un1_tag0[73]\, \un1_tag0[75]\, - \un1_tag0[63]\, \un1_tag0[65]\, \un1_tag0[67]\, N_38, - N_16, N_163, \un1_tag0[61]\, \un1_tag0[59]\, - \un1_tag0[57]\, \un1_tag0[56]\, VALID_RNO_5, N_15, - \pteout[11]\, \pteout[17]\, \pteout[4]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - LVL_0_d0 <= \LVL[0]\; - N_3068 <= \N_3068\; - - \r.btag.I1_RNI1BH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.LVL_RNI2GGA5[0]\ : OAI1 - port map(A => h_i13_NE_i_0, B => \LVL[0]\, C => - hit_0_a3_1_0, Y => N_32); - - \r.btag.PPN_RNIGHV5[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_2(2), Y => N_776); - - \r.btag.CTX_RNICHJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[8]\); - - \r.btag.LVL_RNIJAV7[1]\ : NOR3A - port map(A => SU, B => \LVL[0]\, C => \LVL[1]\, Y => - hit_0_a3_7_0); - - \r.btag.I1_RNI0EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI0EUF[3]\); - - \r.btag.PPN_RNIEK5B[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry_2(2), Y => N_784); - - \r.btag.PPN_RNIKHV5[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_2(2), Y => N_778); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \LVL[1]\); - - \r.btag.I2_RNIN5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIN5UF[3]\); - - \r.btag.I2_RNI35623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.PPN_RNIMHV5[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_2(2), Y => N_779); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[63]\); - - \r.btag.LVL_RNI9GM6[1]\ : OR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.LVL_RNI70NDB[0]\ : OR3C - port map(A => N_161, B => N_159, C => N_17_i_0, Y => N_33); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[19]\); - - \r.btag.I2_RNIB3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIN5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.PPN_RNIQHV5[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_2(2), Y => N_781); - - \r.btag.PPN_RNI0T7B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_2(2), Y => N_793); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(2), Y => N_15); - - \r.btag.PPN_RNIRDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_783); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[41]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[36]\); - - \r.btag.I3_RNI7EE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI5B7H[5]\, Y => h_i32_NE_2); - - \r.btag.PPN_RNIGS5B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_2(2), Y => N_785); - - \r.btag.PPN_RNINK6B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_3(2), Y => N_796); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[10]\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[57]\); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.I3_RNIU1VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNIU1VF[3]\); - - \r.btag.PPN_RNIQ47B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_2(2), Y => N_790); - - \r.btag.LVL_RNI0G8A3[1]\ : OR3C - port map(A => h_i32_NE_2, B => h_i32_NE_3, C => - hit_0_a3_7_0, Y => N_39); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.I1_RNIE7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[21]\); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[58]\); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[38]\); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_5); - - \r.btag.I1_RNIHJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIQTTF[1]\, Y => h_i13_NE_0); - - \r.btag.CTX_RNIGS44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0(4), Y => h_c2_4_i); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[66]\); - - \r.btag.I3_RNIOHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIOHUF[1]\); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[68]\); - - \r.btag.CTX_RNIIS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.M_RNIA556\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_2(2), Y => N_772); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[22]\); - - \r.btag.LVL_RNI1KT71[1]\ : AO1B - port map(A => h_c2_NE_5, B => h_c2_NE_4, C => N_38, Y => - N_16); - - \r.btag.LVL_RNIH466[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry_3(2), - Y => N_799); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[29]\); - - \r.btag.LVL_RNI5KC6D[1]\ : AO1B - port map(A => hit_0_a3_3_0, B => N_163, C => N_42, Y => - N_165); - - \r.btag.PPN_RNICHV5[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_2(2), Y => N_774); - - \r.btag.CTX_RNIMS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.ACC_RNIG8I5[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry_2(2), Y => N_769); - - \r.btag.CTX_RNIQO98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[64]\); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_5, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[4]\); - - \r.btag.I1_RNI7N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI7N6H[5]\); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[25]\); - - \r.btag.PPN_RNIPS6B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_3(2), Y => N_797); - - \r.btag.PPN_RNILC6B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_3(2), Y => N_795); - - \r.btag.CTX_RNIAP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[3]\); - - \r.btag.VALID_RNILTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.I3_RNI6NQV1[0]\ : NOR3C - port map(A => \I3_RNIOHUF[1]\, B => \I3_RNIL9UF[0]\, C => - h_i32_NE_1, Y => h_i32_NE_3); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[60]\); - - \r.btag.I3_RNI5B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI5B7H[5]\); - - \r.btag.C_RNIM456\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry_2(2), Y => N_773); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[75]\); - - \r.btag.PPN_RNISC7B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_2(2), Y => N_791); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[1]\); - - \r.btag.CTX_RNIES44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.PPN_RNIFDQ3[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry(2), Y => N_777); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[11]\); - - \r.btag.I2_RNI1QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI1QUF[1]\); - - \r.btag.LVL_RNIHLN05[1]\ : AO1C - port map(A => N_200, B => N_16, C => N_39, Y => N_163); - - \r.btag.CTX_RNICIJG[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIEHV5[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_2(2), Y => N_775); - - \r.btag.VALID_RNI698RE2\ : NOR3B - port map(A => N_170, B => cam_hit_all_1_2_i_a4_1, C => hit, - Y => \N_3068\); - - \r.btag.PPN_RNIKC6B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_2(2), Y => N_787); - - \r.btag.I3_RNIPRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNIU1VF[3]\, Y => h_i32_NE_1); - - \r.btag.VALID_RNI1UPEU4\ : OR3B - port map(A => N_557, B => \N_3068\, C => N_2937_1, Y => - N_2937); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[0]\); - - \r.btag.PPN_RNIOHV5[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_2(2), Y => N_780); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[20]\); - - \r.btag.I2_RNIOS411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNIUE6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[42]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[65]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[27]\); - - \r.btag.PPN_RNIOS6B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_2(2), Y => N_789); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[56]\); - - \r.btag.I2_RNIUE6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNIUE6H[5]\); - - \r.btag.I2_RNIBI9E7[0]\ : NOR2B - port map(A => N_204, B => N_17_i_0, Y => hit_0_a3_3_0); - - \r.btag.I1_RNIB6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNI7N6H[5]\, Y => h_i13_NE_2); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[71]\); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[9]\); - - \r.btag.PPN_RNIMK6B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_2(2), Y => N_788); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[24]\); - - \r.btag.VALID_RNISACOD\ : OR3B - port map(A => \un1_tag0[43]\, B => N_165, C => N_170_1, Y - => N_170); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.I1_RNITJSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI0EUF[3]\, Y => h_i13_NE_1); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[40]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[37]\); - - \r.btag.PPN_RNISHV5[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_2(2), Y => N_782); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[15]\); - - \r.btag.PPN_RNIUK7B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_2(2), Y => N_792); - - \r.btag.ET_RNIKDTA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_2(2), Y => N_767); - - \r.btag.SU_RNIBNCN1\ : OR2B - port map(A => hit_0_a3_6_0, B => N_159, Y => N_44); - - \r.btag.CTX_RNI8S44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \pteout[7]\); - - \r.btag.PPN_RNII46B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_2(2), Y => N_786); - - \r.btag.ACC_RNIE8I5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_2(2), Y => N_768); - - \r.btag.I2_RNI05511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI1QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.SU_RNIDENI\ : NOR2 - port map(A => SU, B => N_200_0, Y => hit_0_a3_6_0); - - \r.btag.LVL_RNINVH33[0]\ : AO1 - port map(A => h_i32_NE_3, B => h_i32_NE_2, C => \LVL[0]\, Y - => N_161); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \LVL[0]\); - - \r.btag.I1_RNIQTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIQTTF[1]\); - - \r.btag.I1_RNIFI934[0]\ : NOR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => - h_i13_NE_i_0); - - \r.btag.PPN_RNIJ46B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_3(2), Y => N_794); - - \r.btag.I3_RNIL9UF[0]\ : XOR2 - port map(A => \un1_tag0[56]\, B => N_631_i, Y => - \I3_RNIL9UF[0]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[30]\); - - \r.btag.LVL_RNIG35FP[0]\ : NOR3C - port map(A => N_33, B => N_32, C => VALID_RNI7JTM8, Y => - cam_hit_all_1_2_i_a4_1); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[12]\); - - \r.btag.VALID_RNIU8L41\ : NOR3C - port map(A => h_c2_NE_4, B => h_c2_NE_5, C => - \un1_tag0[43]\, Y => N_159); - - \r.btag.I2_RNIINF57[0]\ : NOR2B - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE_i_0, Y => - N_17_i_0); - - \r.btag.LVL_RNI93U51[1]\ : NOR2B - port map(A => \LVL[1]\, B => N_159, Y => hit_0_a3_1_0); - - \r.btag.VALID_RNIDKL26\ : OR3C - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE_i_0, - Y => N_43); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(2), Q => \pteout[16]\); - - \r.btag.VALID_RNI7JTM8\ : AO1 - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => - VALID_RNI7JTM8); - - \r.btag.I1_RNIS9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIS9UF[7]\); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \un1_tag0[59]\); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[72]\); - - \r.btag.I1_RNIM4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIS9UF[7]\, Y => h_i13_NE_3); - - \r.btag.CTX_RNIAS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.ACC_RNIF4D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_770); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(2), Q => \un1_tag0[73]\); - - \r.btag.ET_RNIFLSA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_1(2), Y => N_766); - - \r.btag.SU_RNI94KE1\ : AO1A - port map(A => \LVL[0]\, B => SU, C => N_16, Y => N_160); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(2), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_7 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - tlbcam_write_op_1 : in std_logic_vector(3 to 3); - tlbcam_write_op_1_1 : in std_logic_vector(3 to 3); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_17 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_12 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0 : in std_logic; - hrdata_7 : in std_logic; - hrdata_6 : in std_logic; - s2_entry : in std_logic_vector(2 to 2); - tlbcam_write_op_1_0 : in std_logic_vector(3 to 3); - LVL_0 : in std_logic_vector(1 downto 0); - s2_entry_5 : in std_logic_vector(2 to 2); - s2_entry_4 : in std_logic_vector(2 to 2); - pteout_0_7 : in std_logic; - pteout_0_4 : in std_logic; - pteout_0_17 : in std_logic; - pteout_0_18 : in std_logic; - pteout_0_11 : in std_logic; - pteout_0_31 : in std_logic; - pteout_0_30 : in std_logic; - pteout_0_29 : in std_logic; - pteout_0_28 : in std_logic; - pteout_0_27 : in std_logic; - pteout_0_26 : in std_logic; - pteout_0_25 : in std_logic; - pteout_0_24 : in std_logic; - pteout_0_23 : in std_logic; - pteout_0_22 : in std_logic; - pteout_0_21 : in std_logic; - pteout_0_20 : in std_logic; - pteout_0_19 : in std_logic; - pteout_0_16 : in std_logic; - pteout_0_15 : in std_logic; - pteout_0_14 : in std_logic; - pteout_0_13 : in std_logic; - pteout_0_12 : in std_logic; - pteout_0_10 : in std_logic; - pteout_0_9 : in std_logic; - pteout_0_8 : in std_logic; - pteout_0_6 : in std_logic; - pteout_0_3 : in std_logic; - pteout_0_2 : in std_logic; - pteout_0_1 : in std_logic; - pteout_0_0 : in std_logic; - ctx : in std_logic_vector(6 to 6); - ctx_0_5 : in std_logic; - ctx_0_4 : in std_logic; - ctx_0_3 : in std_logic; - ctx_0_1 : in std_logic; - ctx_0_0 : in std_logic; - ctx_0_2 : in std_logic; - ctx_0_7 : in std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - C_RNIL004 : out std_logic; - N_872 : out std_logic; - N_885 : out std_logic; - N_886 : out std_logic; - N_879 : out std_logic; - N_901 : out std_logic; - s2_flush : in std_logic; - un1_rst_i_0 : in std_logic; - N_900 : out std_logic; - N_200 : in std_logic; - N_596 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - N_597 : in std_logic; - N_665 : in std_logic; - N_899 : out std_logic; - N_898 : out std_logic; - N_897 : out std_logic; - N_896 : out std_logic; - N_895 : out std_logic; - N_894 : out std_logic; - N_893 : out std_logic; - N_892 : out std_logic; - N_891 : out std_logic; - N_890 : out std_logic; - N_889 : out std_logic; - N_888 : out std_logic; - N_887 : out std_logic; - N_884 : out std_logic; - N_883 : out std_logic; - N_882 : out std_logic; - N_881 : out std_logic; - N_880 : out std_logic; - N_878 : out std_logic; - N_877 : out std_logic; - N_876 : out std_logic; - N_874 : out std_logic; - N_871 : out std_logic; - N_870 : out std_logic; - N_869 : out std_logic; - N_868 : out std_logic; - N_634 : in std_logic; - N_632 : in std_logic; - N_662 : in std_logic; - N_639 : in std_logic; - N_635 : in std_logic; - hit_0_a3_0 : in std_logic; - N_204 : in std_logic; - N_42 : in std_logic; - hit : out std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_620 : in std_logic; - N_170_1 : in std_logic - ); - -end mmutlbcam_0_0_7; - -architecture DEF_ARCH of mmutlbcam_0_0_7 is - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal hit_0_0, hit_0_a3_2_0, N_17_i_0, N_32_i, hit_0_a3_0_0, - \un1_tag0[43]\, h_i32_NE, \LVL[0]\, N_159, hit_0_a3_1_0, - \LVL[1]\, M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[67]\, - \I2_RNIRDUF[4]\, \un1_tag0[64]\, \I2_RNIO5UF[3]\, - \un1_tag0[62]\, \I2_RNI2QUF[1]\, hit_0_a3_5_0, - hit_0_a3_7_0, N_45, h_i13_NE_5, h_i13_NE_2, h_i13_NE_3, - h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, \un1_tag0[74]\, - \I1_RNIT9UF[7]\, \un1_tag0[72]\, \I1_RNI8N6H[5]\, - \un1_tag0[70]\, \I1_RNI1EUF[3]\, \un1_tag0[68]\, - \I1_RNIRTTF[1]\, h_i32_NE_2, \un1_tag0[60]\, - \I3_RNI6B7H[5]\, h_i32_NE_1, \un1_tag0[58]\, - \I3_RNIV1VF[3]\, h_i32_NE_0, \un1_tag0[56]\, - \I3_RNIPHUF[1]\, hit_0_a3_6_0, SU, h_c2_NE_5, h_c2_5_i, - h_c2_4_i, h_c2_NE_3, \un1_tag0[42]\, h_c2_6_i, h_c2_NE_1, - \un1_tag0[37]\, h_c2_3_i, h_c2_NE_0, \un1_tag0[35]\, - h_c2_1_i, h_i13_NE, N_169, N_170, N_41, N_163, - h_c2_NE_i_0, N_44, N_43, N_160, \un1_tag0[69]\, - \un1_tag0[71]\, \un1_tag0[36]\, \un1_tag0[38]\, - \un1_tag0[39]\, \un1_tag0[40]\, \un1_tag0[41]\, - \un1_tag0[66]\, \un1_tag0[57]\, \un1_tag0[59]\, - \pteout[0]\, \pteout[1]\, \pteout[2]\, \pteout[3]\, - \pteout[6]\, \pteout[8]\, \pteout[9]\, \pteout[10]\, - \pteout[12]\, \pteout[13]\, \pteout[14]\, \pteout[15]\, - \pteout[16]\, \pteout[19]\, \pteout[20]\, \pteout[21]\, - \pteout[22]\, \pteout[23]\, \pteout[24]\, \pteout[25]\, - \pteout[26]\, \pteout[27]\, \pteout[28]\, \pteout[29]\, - \pteout[30]\, \pteout[31]\, \un1_tag0[73]\, - \un1_tag0[75]\, \un1_tag0[63]\, \un1_tag0[65]\, - \un1_tag0[61]\, N_38, N_40, VALID_RNO_6, N_15, - \pteout[11]\, \pteout[18]\, \pteout[17]\, \pteout[4]\, - \pteout[7]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \r.btag.I2_RNI25511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI2QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.PPN_RNITDQ3[9]\ : MX2 - port map(A => \pteout[17]\, B => pteout_0_17, S => - s2_entry(2), Y => N_885); - - \r.btag.I1_RNID6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNI8N6H[5]\, Y => h_i13_NE_2); - - \r.btag.LVL_RNI94FHC[1]\ : OR3C - port map(A => N_17_i_0, B => N_204, C => N_163, Y => N_41); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[8]\); - - \r.btag.PPN_RNIUH06[5]\ : MX2 - port map(A => \pteout[13]\, B => pteout_0_13, S => - s2_entry_4(2), Y => N_881); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \LVL[1]\); - - \r.btag.SU_RNIEENI\ : NOR2 - port map(A => SU, B => N_200_0, Y => hit_0_a3_6_0); - - \r.btag.I1_RNIT9UF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNIT9UF[7]\); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[39]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[63]\); - - \r.btag.CTX_RNIOKNA[7]\ : XA1A - port map(A => ctx_0_7, B => \un1_tag0[42]\, C => h_c2_6_i, - Y => h_c2_NE_3); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[19]\); - - \r.btag.PPN_RNIVK7B[22]\ : MX2 - port map(A => \pteout[30]\, B => pteout_0_30, S => - s2_entry_5(2), Y => N_898); - - \r.btag.I3_RNIRRTV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNIV1VF[3]\, Y => h_i32_NE_1); - - \r.btag.LVL_RNIVUB81[1]\ : OR2A - port map(A => \LVL[1]\, B => N_159, Y => hit_0_a3_1_0); - - \r.btag.LVL_RNIN476[0]\ : MX2 - port map(A => \LVL[0]\, B => LVL_0(0), S => s2_entry_5(2), - Y => N_900); - - \r.btag.LVL_RNIH4LA4[0]\ : OA1C - port map(A => h_i32_NE, B => \LVL[0]\, C => N_159, Y => - hit_0_a3_2_0); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[67]\); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(3), Y => N_15); - - \r.btag.PPN_RNIKH06[0]\ : MX2 - port map(A => \pteout[8]\, B => pteout_0_8, S => - s2_entry_4(2), Y => N_876); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[41]\); - - \r.btag.I1_RNIJJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIRTTF[1]\, Y => h_i13_NE_0); - - \r.btag.VALID_RNIUAPR8\ : AO1D - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => N_169); - - \r.btag.I1_RNI5BH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => SU); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[62]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[36]\); - - \r.btag.LVL_RNI1CUC5[0]\ : AO1A - port map(A => \LVL[0]\, B => h_i13_NE, C => hit_0_a3_1_0, Y - => N_32_i); - - \r.btag.SU_RNIAGM6\ : NOR2A - port map(A => SU, B => \LVL[0]\, Y => N_45); - - \r.btag.PPN_RNISH06[4]\ : MX2 - port map(A => \pteout[12]\, B => pteout_0_12, S => - s2_entry_4(2), Y => N_880); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_10, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[10]\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[57]\); - - \r.btag.PPN_RNI3D8B[15]\ : MX2 - port map(A => \pteout[23]\, B => pteout_0_23, S => - s2_entry_5(2), Y => N_891); - - \r.btag.PPN_RNIMH06[1]\ : MX2 - port map(A => \pteout[9]\, B => pteout_0_9, S => - s2_entry_4(2), Y => N_877); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.btag.PPN_RNI5L8B[16]\ : MX2 - port map(A => \pteout[24]\, B => pteout_0_24, S => - s2_entry_5(2), Y => N_892); - - \r.btag.I1_RNIRTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIRTTF[1]\); - - \r.btag.VALID_RNIEG356\ : NOR3B - port map(A => N_160, B => hit_0_a3_5_0, C => h_i13_NE, Y - => N_43); - - \r.btag.SU_RNI102H1\ : OR3 - port map(A => N_38, B => h_c2_NE_i_0, C => N_45, Y => N_160); - - \r.btag.PPN_RNI4I06[8]\ : MX2 - port map(A => \pteout[16]\, B => pteout_0_16, S => - s2_entry_4(2), Y => N_884); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[28]\); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_17, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[17]\); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[21]\); - - \r.btag.CTX_RNIKO98[0]\ : XA1A - port map(A => ctx_0_0, B => \un1_tag0[35]\, C => h_c2_1_i, - Y => h_c2_NE_0); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[58]\); - - \r.btag.I2_RNI95623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[38]\); - - \r.btag.I3_RNIJ5923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_6); - - \r.btag.PPN_RNI158B[14]\ : MX2 - port map(A => \pteout[22]\, B => pteout_0_22, S => - s2_entry_5(2), Y => N_890); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[66]\); - - \r.btag.VALID_RNIOMVH\ : NOR2A - port map(A => \un1_tag0[43]\, B => N_170_1, Y => - hit_0_a3_0_0); - - \r.btag.PPN_RNIBD9B[19]\ : MX2 - port map(A => \pteout[27]\, B => pteout_0_27, S => - s2_entry_5(2), Y => N_895); - - \r.btag.I3_RNIV1VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNIV1VF[3]\); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[68]\); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[22]\); - - \r.btag.PPN_RNITK7B[12]\ : MX2 - port map(A => \pteout[20]\, B => pteout_0_20, S => - s2_entry_5(2), Y => N_888); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[2]\); - - \r.btag.PPN_RNI959B[18]\ : MX2 - port map(A => \pteout[26]\, B => pteout_0_26, S => - s2_entry_5(2), Y => N_894); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[29]\); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[64]\); - - \r.btag.ACC_RNIM8J5[0]\ : MX2 - port map(A => \pteout[2]\, B => pteout_0_2, S => - s2_entry_4(2), Y => N_870); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_6, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[4]\); - - \r.btag.SU_RNIBGM6\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - \r.btag.I2_RNIRDUF[4]\ : XOR2 - port map(A => \un1_tag0[66]\, B => N_662, Y => - \I2_RNIRDUF[4]\); - - \r.btag.PPN_RNIVS7B[13]\ : MX2 - port map(A => \pteout[21]\, B => pteout_0_21, S => - s2_entry_5(2), Y => N_889); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[25]\); - - \r.btag.PPN_RNIDG09[10]\ : MX2 - port map(A => \pteout[18]\, B => pteout_0_18, S => - s2_entry(2), Y => N_886); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[35]\); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[3]\); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[60]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[75]\); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[6]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[1]\); - - \r.btag.PPN_RNIHDQ3[3]\ : MX2 - port map(A => \pteout[11]\, B => pteout_0_11, S => - s2_entry(2), Y => N_879); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_11, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[11]\); - - \r.btag.CTX_RNIFS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0_3, Y => h_c2_3_i); - - \r.btag.C_RNIL004\ : MX2 - port map(A => \pteout[7]\, B => pteout_0_7, S => - s2_entry(2), Y => C_RNIL004); - - \r.btag.ACC_RNIO8J5[1]\ : MX2 - port map(A => \pteout[3]\, B => pteout_0_3, S => - s2_entry_4(2), Y => N_871); - - \r.btag.I1_RNINI934[0]\ : OR2B - port map(A => h_i13_NE_5, B => h_i13_NE_4, Y => h_i13_NE); - - \r.btag.VALID_RNIA7QQD\ : AO1B - port map(A => N_42, B => N_41, C => hit_0_a3_0_0, Y => - N_170); - - \r.btag.CTX_RNIJS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0_5, Y => h_c2_5_i); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[0]\); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[20]\); - - \r.btag.SU_RNI71TO1\ : OA1B - port map(A => N_38, B => h_c2_NE_i_0, C => N_200, Y => N_40); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[31]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[42]\); - - \r.btag.ACC_RNIH4D3[2]\ : MX2 - port map(A => \pteout[4]\, B => pteout_0_4, S => - s2_entry(2), Y => N_872); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[65]\); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[27]\); - - \r.btag.I2_RNI2QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI2QUF[1]\); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[56]\); - - \r.btag.PPN_RNI0I06[6]\ : MX2 - port map(A => \pteout[14]\, B => pteout_0_14, S => - s2_entry_4(2), Y => N_882); - - \r.btag.I2_RNIO5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIO5UF[3]\); - - \r.btag.SU_RNI1JQP1\ : NOR2A - port map(A => hit_0_a3_6_0, B => N_159, Y => N_44); - - \r.btag.I2_RNI0OF57[0]\ : NOR2A - port map(A => M_1_sqmuxa_0_o3_1_4, B => h_i13_NE, Y => - N_17_i_0); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[71]\); - - \r.btag.PPN_RNI2I06[7]\ : MX2 - port map(A => \pteout[15]\, B => pteout_0_15, S => - s2_entry_4(2), Y => N_883); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_9, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[9]\); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[70]\); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_24, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[24]\); - - \r.btag.CTX_RNI1OI6[6]\ : XNOR2 - port map(A => \un1_tag0[41]\, B => ctx(6), Y => h_c2_6_i); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.btag.VALID_RNIMTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[69]\); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[40]\); - - \r.btag.PPN_RNI1T7B[23]\ : MX2 - port map(A => \pteout[31]\, B => pteout_0_31, S => - s2_entry_5(2), Y => N_899); - - \r.btag.LVL_RNIGH535[1]\ : AO1A - port map(A => h_i32_NE, B => hit_0_a3_7_0, C => N_40, Y => - N_163); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[37]\); - - \r.btag.LVL_RNIMAV7[1]\ : NOR2A - port map(A => N_45, B => \LVL[1]\, Y => hit_0_a3_7_0); - - \r.btag.PPN_RNIOH06[2]\ : MX2 - port map(A => \pteout[10]\, B => pteout_0_10, S => - s2_entry_4(2), Y => N_878); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[15]\); - - \r.btag.LVL_RNIQQMJ71[0]\ : OR3C - port map(A => hit_0_0, B => N_169, C => N_170, Y => hit); - - \r.btag.I1_RNIVJSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI1EUF[3]\, Y => h_i13_NE_1); - - \r.btag.ET_RNISDUA[1]\ : MX2 - port map(A => \pteout[1]\, B => pteout_0_1, S => - s2_entry_4(2), Y => N_869); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_14, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[14]\); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_7, CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \pteout[7]\); - - \r.btag.I3_RNI9EE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI6B7H[5]\, Y => h_i32_NE_2); - - \r.btag.VALID_RNIJ4371\ : OR2B - port map(A => \un1_tag0[43]\, B => h_c2_NE_i_0, Y => N_159); - - \r.btag.CTX_RNIHS44[4]\ : XNOR2 - port map(A => \un1_tag0[39]\, B => ctx_0_4, Y => h_c2_4_i); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \LVL[0]\); - - \r.btag.ET_RNIQ5UA[0]\ : MX2 - port map(A => \pteout[0]\, B => pteout_0_0, S => - s2_entry_4(2), Y => N_868); - - \r.btag.CTX_RNISD1J[4]\ : NOR3C - port map(A => h_c2_5_i, B => h_c2_4_i, C => h_c2_NE_3, Y - => h_c2_NE_5); - - \r.btag.PPN_RNIR47B[20]\ : MX2 - port map(A => \pteout[28]\, B => pteout_0_28, S => - s2_entry_5(2), Y => N_896); - - \r.btag.CTX_RNISO98[2]\ : XA1A - port map(A => ctx_0_2, B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.CTX_RNICVK31[0]\ : NOR3C - port map(A => h_c2_NE_1, B => h_c2_NE_0, C => h_c2_NE_5, Y - => h_c2_NE_i_0); - - \r.btag.LVL_RNII83TG[0]\ : AOI1B - port map(A => hit_0_a3_2_0, B => N_17_i_0, C => N_32_i, Y - => hit_0_0); - - \r.btag.I1_RNIO4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNIT9UF[7]\, Y => h_i13_NE_3); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_13, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[13]\); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[30]\); - - \r.btag.PPN_RNIOS6B[11]\ : MX2 - port map(A => \pteout[19]\, B => pteout_0_19, S => - s2_entry_4(2), Y => N_887); - - \r.btag.I3_RNIFRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNIPHUF[1]\, Y => h_i32_NE_0); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[61]\); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[74]\); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[12]\); - - \r.btag.I3_RNI6B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI6B7H[5]\); - - \r.btag.I3_RNIPHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNIPHUF[1]\); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[26]\); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[23]\); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(3), Q => \pteout[16]\); - - \r.btag.I1_RNII7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.PPN_RNITC7B[21]\ : MX2 - port map(A => \pteout[29]\, B => pteout_0_29, S => - s2_entry_5(2), Y => N_897); - - \r.btag.LVL_RNIDG04[1]\ : MX2 - port map(A => \LVL[1]\, B => LVL_0(1), S => s2_entry(2), Y - => N_901); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \un1_tag0[59]\); - - \r.btag.M_RNII566\ : MX2 - port map(A => \pteout[6]\, B => pteout_0_6, S => - s2_entry_4(2), Y => N_874); - - \r.btag.PPN_RNI7T8B[17]\ : MX2 - port map(A => \pteout[25]\, B => pteout_0_25, S => - s2_entry_5(2), Y => N_893); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[72]\); - - \r.btag.I1_RNI8N6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNI8N6H[5]\); - - \r.btag.CTX_RNIBS44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0_1, Y => h_c2_1_i); - - \r.btag.I2_RNIQS411[5]\ : XA1 - port map(A => N_620, B => \un1_tag0[67]\, C => - \I2_RNIRDUF[4]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.I1_RNI1EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI1EUF[3]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(3), Q => \un1_tag0[73]\); - - \r.btag.I2_RNID3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIO5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1(3), Q => \pteout[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlbcam_0_0_1 is - - port( s2_ctx : in std_logic_vector(7 downto 0); - data : in std_logic_vector(31 downto 12); - lvl_i_1 : in std_logic_vector(1 downto 0); - hrdata_0_17 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_6 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_0 : in std_logic; - tlbcam_write_op_1 : in std_logic_vector(6 to 6); - tlbcam_write_op_1_1_0 : in std_logic_vector(6 to 6); - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - s2_entry_5 : in std_logic_vector(2 to 2); - LVL_0 : in std_logic_vector(0 to 0); - tlbcam_write_op_1_0 : in std_logic_vector(6 to 6); - ctx_0 : in std_logic_vector(7 downto 0); - LVL_1 : out std_logic; - s2_entry_1_i_a2_1_2 : out std_logic_vector(1 to 1); - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_2482 : in std_logic; - lclk_c : in std_logic; - N_635 : in std_logic; - N_639 : in std_logic; - N_665 : in std_logic; - N_597 : in std_logic; - N_798 : out std_logic; - N_632 : in std_logic; - N_634 : in std_logic; - N_596 : in std_logic; - un1_rst_i_0 : in std_logic; - N_620 : in std_logic; - N_594 : in std_logic; - N_593 : in std_logic; - s2_flush_0 : in std_logic; - hit_0_a3_0 : in std_logic; - N_42 : in std_logic; - N_200 : in std_logic; - N_204 : in std_logic; - N_631_i : in std_logic; - N_633 : in std_logic; - N_595 : in std_logic; - N_663 : in std_logic; - N_664 : in std_logic; - N_651 : in std_logic; - N_612 : in std_logic; - N_200_0 : in std_logic; - N_617 : in std_logic; - N_650 : in std_logic; - N_662 : in std_logic; - N_170_1 : in std_logic - ); - -end mmutlbcam_0_0_1; - -architecture DEF_ARCH of mmutlbcam_0_0_1 is - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \s2_entry_1_i_a2_1_1[1]\, N_170, N_33, N_32_i_0, - SU_RNI4G5O8, hit_0_a3_0_0, \un1_tag0[43]\, - M_1_sqmuxa_0_o3_1_4, M_1_sqmuxa_0_o3_1_1, - M_1_sqmuxa_0_o3_1_0, M_1_sqmuxa_0_o3_1_2, \un1_tag0[66]\, - \I2_RNI2F6H[5]\, \un1_tag0[64]\, \I2_RNIR5UF[3]\, - \un1_tag0[62]\, \I2_RNI5QUF[1]\, hit_0_a3_5_1, N_45, N_16, - hit_0_a3_5_0, hit_0_a3_7_0, h_i13_NE_5, h_i13_NE_2, - h_i13_NE_3, h_i13_NE_4, h_i13_NE_0, h_i13_NE_1, - \un1_tag0[74]\, \I1_RNI0AUF[7]\, \un1_tag0[72]\, - \I1_RNIBN6H[5]\, \un1_tag0[70]\, \I1_RNI4EUF[3]\, - \un1_tag0[68]\, \I1_RNIUTTF[1]\, h_i32_NE_2, - \un1_tag0[60]\, \I3_RNI9B7H[5]\, h_i32_NE_1, - \un1_tag0[58]\, \I3_RNI22VF[3]\, h_i32_NE_0, - \un1_tag0[56]\, \I3_RNISHUF[1]\, h_c2_NE_4, h_c2_1_i, - h_c2_0_i, h_c2_NE_1, h_c2_NE_3, \un1_tag0[41]\, h_c2_7_i, - h_c2_NE_2, \un1_tag0[39]\, h_c2_5_i, \un1_tag0[37]\, - h_c2_3_i, N_17_i_0, h_c2_NE_i_0, h_i32_NE, N_161, N_159, - \LVL[1]\, N_162, N_41, N_163, N_44, SU, N_43, N_15, - \un1_tag0[35]\, \un1_tag0[36]\, \un1_tag0[38]\, - \un1_tag0[40]\, \un1_tag0[42]\, \un1_tag0[63]\, - \un1_tag0[65]\, \un1_tag0[67]\, VALID_RNO_0, N_38, - \LVL[0]\, N_40, \un1_tag0[61]\, \un1_tag0[59]\, - \un1_tag0[57]\, \un1_tag0[75]\, \un1_tag0[73]\, - \un1_tag0[71]\, \un1_tag0[69]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - LVL_1 <= \LVL[1]\; - - \r.btag.VALID_RNI4FCOD\ : AO1B - port map(A => N_41, B => N_42, C => hit_0_a3_0_0, Y => - N_170); - - \r.btag.VALID_RNI2AL41\ : OR2B - port map(A => \un1_tag0[43]\, B => h_c2_NE_i_0, Y => N_159); - - \r.btag.I1_RNIPJRV[0]\ : XA1 - port map(A => N_663, B => \un1_tag0[68]\, C => - \I1_RNIUTTF[1]\, Y => h_i13_NE_0); - - \r.btag.PPN[22]\ : DFN1E1 - port map(D => hrdata_30, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_30); - - \r.btag.I1_RNIHBH32[4]\ : NOR2B - port map(A => h_i13_NE_2, B => h_i13_NE_3, Y => h_i13_NE_5); - - \r.btag.LVL_RNITNN05[1]\ : AO1D - port map(A => hit_0_a3_7_0, B => h_i32_NE, C => N_40, Y => - N_163); - - \r.btag.PPN[4]\ : DFN1E1 - port map(D => hrdata_12, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_12); - - \r.btag.PPN[12]\ : DFN1E1 - port map(D => N_262_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_20); - - \r.btag.VALID_RNI1NL26\ : OR3C - port map(A => h_i13_NE_4, B => h_i13_NE_5, C => - hit_0_a3_5_1, Y => N_43); - - \r.btag.LVL_RNI0C1FC[1]\ : OR3C - port map(A => N_17_i_0, B => N_204, C => N_163, Y => N_41); - - \r.btag.CTX_RNIMS44[5]\ : XNOR2 - port map(A => \un1_tag0[40]\, B => ctx_0(5), Y => h_c2_5_i); - - \r.btag.LVL_RNILLP871[1]\ : NOR2B - port map(A => \s2_entry_1_i_a2_1_1[1]\, B => N_170, Y => - s2_entry_1_i_a2_1_2(1)); - - \r.btag.CTX_RNICS44[0]\ : XNOR2 - port map(A => \un1_tag0[35]\, B => ctx_0(0), Y => h_c2_0_i); - - \r.btag.I1_RNI0AUF[7]\ : XOR2 - port map(A => \un1_tag0[75]\, B => N_597, Y => - \I1_RNI0AUF[7]\); - - \r.btag.I1[5]\ : DFN1E1 - port map(D => data(29), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[73]\); - - \r.btag.I1[1]\ : DFN1E1 - port map(D => data(25), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[69]\); - - \r.btag.CTX_RNIAP98[4]\ : XA1A - port map(A => ctx_0(4), B => \un1_tag0[39]\, C => h_c2_5_i, - Y => h_c2_NE_2); - - \r.btag.LVL_RNIL476[0]\ : MX2 - port map(A => LVL_0(0), B => \LVL[0]\, S => s2_entry_5(2), - Y => N_798); - - \r.btag.CTX[3]\ : DFN1E1 - port map(D => s2_ctx(3), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[38]\); - - \r.btag.I3_RNI22VF[3]\ : XOR2 - port map(A => \un1_tag0[59]\, B => N_634, Y => - \I3_RNI22VF[3]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.btag.I3[1]\ : DFN1E1 - port map(D => data(13), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[57]\); - - \r.btag.PPN[20]\ : DFN1E1 - port map(D => hrdata_28, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_28); - - \r.btag.M\ : DFN1E1 - port map(D => hrdata_6, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_6); - - \r.btag.PPN[9]\ : DFN1E1 - port map(D => hrdata_0_10, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_17); - - \r.btag.PPN[16]\ : DFN1E1 - port map(D => hrdata_0_17, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_24); - - \r.btag.PPN[0]\ : DFN1E1 - port map(D => hrdata_8, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_8); - - \r.btag.I2_RNI2F6H[5]\ : XOR2 - port map(A => \un1_tag0[67]\, B => N_620, Y => - \I2_RNI2F6H[5]\); - - \r.btag.LVL_RNIH6DGP[1]\ : NOR3C - port map(A => N_33, B => N_32_i_0, C => SU_RNI4G5O8, Y => - \s2_entry_1_i_a2_1_1[1]\); - - \r.btag.CTX[7]\ : DFN1E1 - port map(D => s2_ctx(7), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[42]\); - - \r.btag.PPN[5]\ : DFN1E1 - port map(D => hrdata_0_6, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_13); - - \r.btag.I2_RNIJ3SV[2]\ : XA1 - port map(A => N_650, B => \un1_tag0[64]\, C => - \I2_RNIR5UF[3]\, Y => M_1_sqmuxa_0_o3_1_1); - - \r.btag.CTX[5]\ : DFN1E1 - port map(D => s2_ctx(5), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[40]\); - - \r.btag.VALID_RNII3CV1\ : AOI1B - port map(A => N_45, B => N_16, C => hit_0_a3_5_0, Y => - hit_0_a3_5_1); - - \r.btag.PPN[10]\ : DFN1E1 - port map(D => hrdata_18, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_18); - - \r.btag.LVL_RNIV3NDB[0]\ : OR3B - port map(A => N_161, B => N_17_i_0, C => N_159, Y => N_33); - - \r.btag.I3[3]\ : DFN1E1 - port map(D => data(15), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[59]\); - - \r.btag.CTX[0]\ : DFN1E1 - port map(D => s2_ctx(0), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[35]\); - - \r.btag.I3_RNILRSV[0]\ : XA1 - port map(A => N_631_i, B => \un1_tag0[56]\, C => - \I3_RNISHUF[1]\, Y => h_i32_NE_0); - - \r.btag.PPN[8]\ : DFN1E1 - port map(D => hrdata_16, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_16); - - \r.btag.I1_RNI5KSV[2]\ : XA1 - port map(A => N_664, B => \un1_tag0[70]\, C => - \I1_RNI4EUF[3]\, Y => h_i13_NE_1); - - \r.btag.CTX[6]\ : DFN1E1 - port map(D => s2_ctx(6), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[41]\); - - \r.btag.LVL_RNITDI44[0]\ : AOI1 - port map(A => h_i13_NE_5, B => h_i13_NE_4, C => \LVL[0]\, Y - => N_162); - - \r.btag.ET[0]\ : DFN1E1 - port map(D => hrdata_0_d0, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_0); - - \r.btag.C\ : DFN1E1 - port map(D => hrdata_0_0, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_7); - - \r.btag.SU_RNIGGM6\ : OR2A - port map(A => SU, B => \LVL[0]\, Y => N_45); - - \r.btag.PPN[15]\ : DFN1E1 - port map(D => hrdata_23, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_23); - - \r.btag.I2_RNI0T411[4]\ : XA1 - port map(A => N_662, B => \un1_tag0[66]\, C => - \I2_RNI2F6H[5]\, Y => M_1_sqmuxa_0_o3_1_2); - - \r.btag.I1[0]\ : DFN1E1 - port map(D => data(24), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[68]\); - - \r.btag.PPN[6]\ : DFN1E1 - port map(D => hrdata_0_7, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_14); - - \r.btag.SU_RNI9LT71\ : NOR2 - port map(A => h_c2_NE_i_0, B => N_38, Y => N_16); - - \r.btag.PPN[23]\ : DFN1E1 - port map(D => hrdata_31, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_31); - - \r.btag.LVL_RNIJ0I33[0]\ : OR2A - port map(A => h_i32_NE, B => \LVL[0]\, Y => N_161); - - \r.btag.I1[6]\ : DFN1E1 - port map(D => data(30), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[74]\); - - \r.btag.CTX_RNIIS44[3]\ : XNOR2 - port map(A => \un1_tag0[38]\, B => ctx_0(3), Y => h_c2_3_i); - - \r.btag.SU_RNIKHKO1\ : OR3 - port map(A => N_200, B => SU, C => N_159, Y => N_44); - - \r.btag.PPN[14]\ : DFN1E1 - port map(D => hrdata_22, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_22); - - \r.btag.I1[4]\ : DFN1E1 - port map(D => data(28), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[72]\); - - \r.btag.VALID_RNIRMVH\ : NOR2A - port map(A => \un1_tag0[43]\, B => N_170_1, Y => - hit_0_a3_0_0); - - \r.btag.I3_RNI9B7H[5]\ : XOR2 - port map(A => \un1_tag0[61]\, B => N_596, Y => - \I3_RNI9B7H[5]\); - - \r.btag.I3_RNIFEE21[4]\ : XA1 - port map(A => N_595, B => \un1_tag0[60]\, C => - \I3_RNI9B7H[5]\, Y => h_i32_NE_2); - - \r.btag.I2_RNIAPF57[0]\ : NOR3C - port map(A => h_i13_NE_4, B => h_i13_NE_5, C => - M_1_sqmuxa_0_o3_1_4, Y => N_17_i_0); - - \r.btag.VALID_RNIPTNG\ : NOR2B - port map(A => \un1_tag0[43]\, B => N_200_0, Y => - hit_0_a3_5_0); - - \r.btag.PPN[19]\ : DFN1E1 - port map(D => hrdata_27, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_27); - - \r.btag.PPN[13]\ : DFN1E1 - port map(D => hrdata_21, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_21); - - \r.btag.I2_RNI85511[0]\ : XA1 - port map(A => N_617, B => \un1_tag0[62]\, C => - \I2_RNI5QUF[1]\, Y => M_1_sqmuxa_0_o3_1_0); - - \r.btag.I2[4]\ : DFN1E1 - port map(D => data(22), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[66]\); - - \r.btag.I1[7]\ : DFN1E1 - port map(D => data(31), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[75]\); - - \r.btag.CTX_RNIQS44[7]\ : XNOR2 - port map(A => \un1_tag0[42]\, B => ctx_0(7), Y => h_c2_7_i); - - \r.btag.PPN[7]\ : DFN1E1 - port map(D => hrdata_15, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_15); - - \r.btag.ACC[2]\ : DFN1E1 - port map(D => hrdata_4, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_4); - - \r.btag.I3[4]\ : DFN1E1 - port map(D => data(16), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[60]\); - - \r.btag.I2[3]\ : DFN1E1 - port map(D => data(21), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[65]\); - - \r.btag.I1_RNIBN6H[5]\ : XOR2 - port map(A => \un1_tag0[73]\, B => N_665, Y => - \I1_RNIBN6H[5]\); - - \r.btag.SU_RNIHGM6\ : NOR2A - port map(A => SU, B => \LVL[1]\, Y => N_38); - - GND_i : GND - port map(Y => \GND\); - - \r.btag.PPN[21]\ : DFN1E1 - port map(D => hrdata_29, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_29); - - \r.btag.LVL[1]\ : DFN1E1 - port map(D => lvl_i_1(1), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \LVL[1]\); - - \r.btag.I2_RNIR5UF[3]\ : XOR2 - port map(A => \un1_tag0[65]\, B => N_594, Y => - \I2_RNIR5UF[3]\); - - \r.btag.I2[5]\ : DFN1E1 - port map(D => data(23), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[67]\); - - \r.btag.PPN[2]\ : DFN1E1 - port map(D => hrdata_0_3, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_10); - - \r.btag.I3[0]\ : DFN1E1 - port map(D => data(12), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[56]\); - - \r.btag.I2[1]\ : DFN1E1 - port map(D => data(19), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[63]\); - - \r.btag.I1_RNIU4411[6]\ : XA1 - port map(A => N_612, B => \un1_tag0[74]\, C => - \I1_RNI0AUF[7]\, Y => h_i13_NE_3); - - \r.btag.VALID\ : DFN1 - port map(D => VALID_RNO_0, CLK => lclk_c, Q => - \un1_tag0[43]\); - - \r.btag.I3_RNISHUF[1]\ : XOR2 - port map(A => \un1_tag0[57]\, B => N_632, Y => - \I3_RNISHUF[1]\); - - \r.btag.PPN[11]\ : DFN1E1 - port map(D => N_264_0, CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => pteout_19); - - \r.btag.PPN[1]\ : DFN1E1 - port map(D => hrdata_0_2, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_9); - - \r.btag.PPN[17]\ : DFN1E1 - port map(D => N_78_0, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_25); - - \r.btag.I3[2]\ : DFN1E1 - port map(D => data(14), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[58]\); - - \r.btag.ET[1]\ : DFN1E1 - port map(D => hrdata_1, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_1); - - \r.btag.I2_RNI5QUF[1]\ : XOR2 - port map(A => \un1_tag0[63]\, B => N_593, Y => - \I2_RNI5QUF[1]\); - - \r.btag.I3[5]\ : DFN1E1 - port map(D => data(17), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[61]\); - - \r.btag.I2[2]\ : DFN1E1 - port map(D => data(20), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[64]\); - - \r.btag.CTX[2]\ : DFN1E1 - port map(D => s2_ctx(2), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[37]\); - - \r.btag.I2_RNIR5623[0]\ : NOR3C - port map(A => M_1_sqmuxa_0_o3_1_1, B => M_1_sqmuxa_0_o3_1_0, - C => M_1_sqmuxa_0_o3_1_2, Y => M_1_sqmuxa_0_o3_1_4); - - \r.btag.CTX_RNISHJG[0]\ : NOR3C - port map(A => h_c2_1_i, B => h_c2_0_i, C => h_c2_NE_1, Y - => h_c2_NE_4); - - \r.btag.CTX_RNI2P98[2]\ : XA1A - port map(A => ctx_0(2), B => \un1_tag0[37]\, C => h_c2_3_i, - Y => h_c2_NE_1); - - \r.btag.CTX_RNIES44[1]\ : XNOR2 - port map(A => \un1_tag0[36]\, B => ctx_0(1), Y => h_c2_1_i); - - \r.btag.I3_RNI1STV[2]\ : XA1 - port map(A => N_633, B => \un1_tag0[58]\, C => - \I3_RNI22VF[3]\, Y => h_i32_NE_1); - - \r.btag.CTX_RNIO4711[4]\ : NOR3C - port map(A => h_c2_NE_3, B => h_c2_NE_2, C => h_c2_NE_4, Y - => h_c2_NE_i_0); - - \r.btag.I2[0]\ : DFN1E1 - port map(D => data(18), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \un1_tag0[62]\); - - \r.btag.SU_RNIP6FM1\ : NOR2 - port map(A => N_16, B => N_200, Y => N_40); - - \r.btag.I3_RNI56923[0]\ : OR3C - port map(A => h_i32_NE_1, B => h_i32_NE_0, C => h_i32_NE_2, - Y => h_i32_NE); - - \r.btag.LVL[0]\ : DFN1E1 - port map(D => lvl_i_1(0), CLK => lclk_c, E => - tlbcam_write_op_1_1_0(6), Q => \LVL[0]\); - - \r.btag.I1_RNIU7OV1[0]\ : NOR2B - port map(A => h_i13_NE_0, B => h_i13_NE_1, Y => h_i13_NE_4); - - \r.btag.VALID_RNO_0\ : AO1A - port map(A => s2_flush_0, B => \un1_tag0[43]\, C => - tlbcam_write_op_1_0(6), Y => N_15); - - \r.btag.VALID_RNO\ : NOR2B - port map(A => N_15, B => un1_rst_i_0, Y => VALID_RNO_0); - - \r.btag.CTX[4]\ : DFN1E1 - port map(D => s2_ctx(4), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[39]\); - - \r.btag.I1_RNIUTTF[1]\ : XOR2 - port map(A => \un1_tag0[69]\, B => N_635, Y => - \I1_RNIUTTF[1]\); - - \r.btag.LVL_RNIEIGA5[1]\ : OR3A - port map(A => \LVL[1]\, B => N_159, C => N_162, Y => - N_32_i_0); - - \r.btag.I1[3]\ : DFN1E1 - port map(D => data(27), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[71]\); - - \r.btag.CTX[1]\ : DFN1E1 - port map(D => s2_ctx(1), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[36]\); - - \r.btag.I1_RNIJ6D21[4]\ : XA1 - port map(A => N_651, B => \un1_tag0[72]\, C => - \I1_RNIBN6H[5]\, Y => h_i13_NE_2); - - \r.btag.PPN[18]\ : DFN1E1 - port map(D => hrdata_26, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_26); - - \r.btag.I1_RNI4EUF[3]\ : XOR2 - port map(A => \un1_tag0[71]\, B => N_639, Y => - \I1_RNI4EUF[3]\); - - \r.btag.CTX_RNIIP98[6]\ : XA1A - port map(A => ctx_0(6), B => \un1_tag0[41]\, C => h_c2_7_i, - Y => h_c2_NE_3); - - \r.btag.ACC[1]\ : DFN1E1 - port map(D => hrdata_3, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_3); - - \r.btag.LVL_RNIVAV7[1]\ : OR2 - port map(A => \LVL[1]\, B => N_45, Y => hit_0_a3_7_0); - - \r.btag.SU_RNI4G5O8\ : AO1 - port map(A => N_44, B => N_43, C => hit_0_a3_0, Y => - SU_RNI4G5O8); - - \r.btag.ACC[0]\ : DFN1E1 - port map(D => hrdata_2, CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => pteout_2); - - \r.btag.I1[2]\ : DFN1E1 - port map(D => data(26), CLK => lclk_c, E => - tlbcam_write_op_1_0(6), Q => \un1_tag0[70]\); - - \r.btag.SU\ : DFN1E1 - port map(D => N_2482, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => SU); - - \r.btag.PPN[3]\ : DFN1E1 - port map(D => hrdata_0_4, CLK => lclk_c, E => - tlbcam_write_op_1(6), Q => pteout_11); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmutlb_10_8_0_1_0 is - - port( address_0 : in std_logic_vector(31 downto 2); - aaddr : out std_logic_vector(31 downto 2); - ctx_0 : in std_logic_vector(7 downto 0); - ctx : in std_logic_vector(7 downto 0); - fault_lvl_1 : out std_logic; - lvl_i_1 : in std_logic_vector(1 downto 0); - lvl_i_1_0 : in std_logic_vector(1 to 1); - un1_m0_30 : out std_logic; - un1_m0_9 : out std_logic; - un1_m0_8 : out std_logic; - un1_m0_5 : out std_logic; - un1_m0_1 : out std_logic; - un1_m0_22 : out std_logic; - un1_m0_6 : out std_logic; - un1_m0_0 : out std_logic; - un1_m0_17 : out std_logic; - un1_m0_16 : out std_logic; - un1_m0_7 : out std_logic; - un1_m0_4 : out std_logic; - un1_m0_3 : out std_logic; - un1_m0_2 : out std_logic; - un1_itlb0_1 : out std_logic_vector(41 to 41); - un1_m0_2_0 : in std_logic_vector(35 to 35); - data_0_29 : out std_logic; - data_0_27 : out std_logic; - data_0_26 : out std_logic; - data_0_20 : out std_logic; - data_0_12 : out std_logic; - address : in std_logic_vector(31 downto 2); - data_14 : out std_logic; - data_21 : out std_logic; - data_16 : out std_logic; - data_19 : out std_logic; - data_17 : out std_logic; - data_15 : out std_logic; - data_24 : out std_logic; - data_22 : out std_logic; - data_18 : out std_logic; - data_25 : out std_logic; - data_13 : out std_logic; - data_11 : out std_logic; - data_10 : out std_logic; - data_23 : out std_logic; - data_28 : out std_logic; - fault_isid_1_i : in std_logic_vector(0 to 0); - ft_1_i_a2_0 : in std_logic_vector(0 to 0); - hrdata_0_6 : in std_logic; - hrdata_0_25 : in std_logic; - hrdata_0_20 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_9 : in std_logic; - hrdata_10 : in std_logic; - hrdata_11 : in std_logic; - hrdata_13 : in std_logic; - hrdata_14 : in std_logic; - hrdata_17 : in std_logic; - hrdata_24 : in std_logic; - hrdata_6 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_8 : in std_logic; - hrdata_12 : in std_logic; - hrdata_15 : in std_logic; - hrdata_16 : in std_logic; - hrdata_18 : in std_logic; - hrdata_21 : in std_logic; - hrdata_22 : in std_logic; - hrdata_23 : in std_logic; - hrdata_26 : in std_logic; - hrdata_27 : in std_logic; - hrdata_28 : in std_logic; - hrdata_29 : in std_logic; - hrdata_30 : in std_logic; - hrdata_31 : in std_logic; - hrdata_2 : in std_logic; - hrdata_3 : in std_logic; - hrdata_4 : in std_logic; - hrdata_7 : in std_logic; - hrdata_5 : in std_logic; - adata_11 : out std_logic; - adata_31 : out std_logic; - adata_30 : out std_logic; - adata_29 : out std_logic; - adata_28 : out std_logic; - adata_27 : out std_logic; - adata_25 : out std_logic; - adata_24 : out std_logic; - adata_23 : out std_logic; - adata_22 : out std_logic; - adata_20 : out std_logic; - adata_17 : out std_logic; - adata_16 : out std_logic; - adata_15 : out std_logic; - adata_14 : out std_logic; - adata_13 : out std_logic; - adata_12 : out std_logic; - adata_10 : out std_logic; - adata_9 : out std_logic; - adata_8 : out std_logic; - adata_7 : out std_logic; - adata_6 : out std_logic; - adata_2 : out std_logic; - adata_1 : out std_logic; - adata_0 : out std_logic; - adata_18 : out std_logic; - adata_21 : out std_logic; - adata_26 : out std_logic; - adata_4 : out std_logic; - adata_3 : out std_logic; - adata_19 : out std_logic; - s2_tlbstate_0 : out std_logic; - mmutlb_10_8_0_1_0_VCC : in std_logic; - N_264 : in std_logic; - N_262 : in std_logic; - N_78 : in std_logic; - un1_rst_i_0 : in std_logic; - N_82 : in std_logic; - N_80 : in std_logic; - su : in std_logic; - N_2625 : out std_logic; - walk_use : out std_logic; - flush_op : in std_logic; - N_2933 : out std_logic; - tlbactive : in std_logic; - N_180 : out std_logic; - walk_op_ur : out std_logic; - fault_pro_m : in std_logic; - fault_pro_1 : out std_logic; - N_2899 : out std_logic; - tlbdis : in std_logic; - inv_1_0_a2_0_a2_0 : in std_logic; - fault_mexc_2 : in std_logic; - fault_trans_i_2 : in std_logic; - N_264_0 : in std_logic; - N_78_0 : in std_logic; - N_3160 : in std_logic; - N_2571 : out std_logic; - N_262_0 : in std_logic; - fault_pri_m_0 : out std_logic; - fault_mexc_0 : in std_logic; - fault_trans_RNIA0K0D1 : out std_logic; - N_429 : out std_logic; - N_427 : out std_logic; - N_2626 : out std_logic; - N_43 : out std_logic; - N_2482 : in std_logic; - N_423 : out std_logic; - N_425 : out std_logic; - N_2623 : out std_logic; - N_2624 : out std_logic; - N_45 : out std_logic; - N_319 : out std_logic; - N_321 : out std_logic; - N_361 : out std_logic; - N_363 : out std_logic; - N_365 : out std_logic; - N_357 : out std_logic; - N_1629 : out std_logic; - fault_su : out std_logic; - twi_areq_ur_1_0_a3_i_0 : out std_logic; - fault_mexc_3_2 : in std_logic; - fault_mexc_1 : out std_logic; - rst : in std_logic; - N_359 : out std_logic; - N_2563_i : in std_logic; - s1finished_0 : out std_logic; - lclk_c : in std_logic; - N_86_i : in std_logic - ); - -end mmutlb_10_8_0_1_0; - -architecture DEF_ARCH of mmutlb_10_8_0_1_0 is - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_2 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(0 to 0) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_5 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_1 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_0 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_17 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_4 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - tlbcam_write_op_1_0 : in std_logic_vector(0 to 0) := (others => 'U'); - data_14 : in std_logic := 'U'; - data_13 : in std_logic := 'U'; - data_12 : in std_logic := 'U'; - data_11 : in std_logic := 'U'; - data_10 : in std_logic := 'U'; - data_9 : in std_logic := 'U'; - data_8 : in std_logic := 'U'; - data_7 : in std_logic := 'U'; - data_6 : in std_logic := 'U'; - data_5 : in std_logic := 'U'; - data_4 : in std_logic := 'U'; - data_3 : in std_logic := 'U'; - data_22 : in std_logic := 'U'; - data_21 : in std_logic := 'U'; - data_20 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - data_18 : in std_logic := 'U'; - data_17 : in std_logic := 'U'; - data_16 : in std_logic := 'U'; - data_15 : in std_logic := 'U'; - data_0 : in std_logic := 'U'; - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_749 : out std_logic; - N_743 : out std_logic; - N_765 : out std_logic; - s2_flush : in std_logic := 'U'; - N_764 : out std_logic; - N_596 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_763 : out std_logic; - N_762 : out std_logic; - N_761 : out std_logic; - N_760 : out std_logic; - N_759 : out std_logic; - N_758 : out std_logic; - N_757 : out std_logic; - N_756 : out std_logic; - N_755 : out std_logic; - N_754 : out std_logic; - N_753 : out std_logic; - N_752 : out std_logic; - N_751 : out std_logic; - N_750 : out std_logic; - N_748 : out std_logic; - N_747 : out std_logic; - N_746 : out std_logic; - N_745 : out std_logic; - N_744 : out std_logic; - N_742 : out std_logic; - N_741 : out std_logic; - N_740 : out std_logic; - N_739 : out std_logic; - N_738 : out std_logic; - N_736 : out std_logic; - N_735 : out std_logic; - N_734 : out std_logic; - N_733 : out std_logic; - N_732 : out std_logic; - N_634 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - SU_RNIAA5O8 : out std_logic; - hit_0_a3_0 : out std_logic; - s2_flush_0 : in std_logic := 'U'; - N_169_1 : out std_logic; - N_200 : in std_logic := 'U'; - N_32_i : out std_logic; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - hit_0_a3_2_0 : out std_logic; - N_17_i_0 : out std_logic; - N_204 : in std_logic := 'U'; - N_170_1 : out std_logic; - N_170 : out std_logic; - N_200_0 : in std_logic := 'U'; - N_42 : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_4 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0 : in std_logic_vector(7 to 7) := (others => 'U'); - tlbcam_write_op_1 : in std_logic_vector(5 to 5) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(5 to 5) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(5 to 5) := (others => 'U'); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL : out std_logic_vector(1 downto 0); - s2_entry_1_i_a2_1 : out std_logic_vector(0 to 0); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_2937_1 : in std_logic := 'U'; - cam_hit_all_1_sqmuxa : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - hit : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component mmutlbcam_0_0 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - lvl_i_1 : in std_logic_vector(0 to 0) := (others => 'U'); - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(4 to 4) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(4 to 4) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - cam_hitaddr_12 : out std_logic_vector(2 to 2); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL : out std_logic_vector(1 downto 0); - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_169_1 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - s2_flush : in std_logic := 'U'; - cam_hit_all_1_sqmuxa : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - hit_i : out std_logic; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U' - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_5 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0 : in std_logic_vector(7 to 7) := (others => 'U'); - tlbcam_write_op_1 : in std_logic_vector(1 to 1) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - s2_entry_5 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_4 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_3 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - s2_entry_1_i_a2_0 : out std_logic_vector(0 to 0); - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_838 : out std_logic; - N_851 : out std_logic; - N_852 : out std_logic; - N_845 : out std_logic; - N_867 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_866 : out std_logic; - N_596 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_865 : out std_logic; - N_864 : out std_logic; - N_863 : out std_logic; - N_862 : out std_logic; - N_861 : out std_logic; - N_860 : out std_logic; - N_859 : out std_logic; - N_858 : out std_logic; - N_857 : out std_logic; - N_856 : out std_logic; - N_855 : out std_logic; - N_854 : out std_logic; - N_853 : out std_logic; - N_850 : out std_logic; - N_849 : out std_logic; - N_848 : out std_logic; - N_847 : out std_logic; - N_846 : out std_logic; - N_844 : out std_logic; - N_843 : out std_logic; - N_842 : out std_logic; - N_841 : out std_logic; - N_840 : out std_logic; - N_837 : out std_logic; - N_836 : out std_logic; - N_835 : out std_logic; - N_834 : out std_logic; - N_634 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U'; - hit_i_0 : out std_logic; - N_557 : in std_logic := 'U' - ); - end component; - - component syncramZ0 - port( aaddr : out std_logic_vector(31 downto 2); - address : in std_logic_vector(31 downto 2) := (others => 'U'); - s2_entry : in std_logic_vector(2 downto 0) := (others => 'U'); - dr1write_0_sqmuxa : in std_logic := 'U'; - syncramZ0_VCC : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component mmutlbcam_0_0_3 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(7 to 7) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(7 to 7) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - tlbcam_write_op_1_0 : in std_logic_vector(7 to 7) := (others => 'U'); - s2_entry_1_i_a2_1_2 : in std_logic_vector(1 to 1) := (others => 'U'); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL : out std_logic_vector(1 downto 0); - s2_entry_1_i_a2_0 : in std_logic_vector(0 to 0) := (others => 'U'); - s2_entry_1_i_a2_2 : out std_logic_vector(0 to 0); - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - s2_flush_0 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_2937_1 : out std_logic; - N_170_1 : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_204 : in std_logic := 'U' - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_6 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1 : in std_logic_vector(2 to 2) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(2 to 2) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(1 to 1) := (others => 'U'); - s2_entry_3 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_2 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_1 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_7 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL_0_d0 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_770 : out std_logic; - N_783 : out std_logic; - N_777 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_799 : out std_logic; - N_797 : out std_logic; - N_796 : out std_logic; - N_795 : out std_logic; - N_794 : out std_logic; - N_793 : out std_logic; - N_792 : out std_logic; - N_791 : out std_logic; - N_790 : out std_logic; - N_789 : out std_logic; - N_788 : out std_logic; - N_787 : out std_logic; - N_786 : out std_logic; - N_785 : out std_logic; - N_784 : out std_logic; - N_782 : out std_logic; - N_781 : out std_logic; - N_780 : out std_logic; - N_779 : out std_logic; - N_778 : out std_logic; - N_776 : out std_logic; - N_775 : out std_logic; - N_774 : out std_logic; - N_773 : out std_logic; - N_772 : out std_logic; - N_769 : out std_logic; - N_768 : out std_logic; - N_767 : out std_logic; - N_766 : out std_logic; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_2937_1 : in std_logic := 'U'; - N_557 : in std_logic := 'U'; - N_2937 : out std_logic; - hit : in std_logic := 'U'; - N_3068 : out std_logic; - N_170_1 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_204 : in std_logic := 'U' - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_7 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - tlbcam_write_op_1 : in std_logic_vector(3 to 3) := (others => 'U'); - tlbcam_write_op_1_1 : in std_logic_vector(3 to 3) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - s2_entry : in std_logic_vector(2 to 2) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(3 to 3) := (others => 'U'); - LVL_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - s2_entry_5 : in std_logic_vector(2 to 2) := (others => 'U'); - s2_entry_4 : in std_logic_vector(2 to 2) := (others => 'U'); - pteout_0_7 : in std_logic := 'U'; - pteout_0_4 : in std_logic := 'U'; - pteout_0_17 : in std_logic := 'U'; - pteout_0_18 : in std_logic := 'U'; - pteout_0_11 : in std_logic := 'U'; - pteout_0_31 : in std_logic := 'U'; - pteout_0_30 : in std_logic := 'U'; - pteout_0_29 : in std_logic := 'U'; - pteout_0_28 : in std_logic := 'U'; - pteout_0_27 : in std_logic := 'U'; - pteout_0_26 : in std_logic := 'U'; - pteout_0_25 : in std_logic := 'U'; - pteout_0_24 : in std_logic := 'U'; - pteout_0_23 : in std_logic := 'U'; - pteout_0_22 : in std_logic := 'U'; - pteout_0_21 : in std_logic := 'U'; - pteout_0_20 : in std_logic := 'U'; - pteout_0_19 : in std_logic := 'U'; - pteout_0_16 : in std_logic := 'U'; - pteout_0_15 : in std_logic := 'U'; - pteout_0_14 : in std_logic := 'U'; - pteout_0_13 : in std_logic := 'U'; - pteout_0_12 : in std_logic := 'U'; - pteout_0_10 : in std_logic := 'U'; - pteout_0_9 : in std_logic := 'U'; - pteout_0_8 : in std_logic := 'U'; - pteout_0_6 : in std_logic := 'U'; - pteout_0_3 : in std_logic := 'U'; - pteout_0_2 : in std_logic := 'U'; - pteout_0_1 : in std_logic := 'U'; - pteout_0_0 : in std_logic := 'U'; - ctx : in std_logic_vector(6 to 6) := (others => 'U'); - ctx_0_5 : in std_logic := 'U'; - ctx_0_4 : in std_logic := 'U'; - ctx_0_3 : in std_logic := 'U'; - ctx_0_1 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_2 : in std_logic := 'U'; - ctx_0_7 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - C_RNIL004 : out std_logic; - N_872 : out std_logic; - N_885 : out std_logic; - N_886 : out std_logic; - N_879 : out std_logic; - N_901 : out std_logic; - s2_flush : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_900 : out std_logic; - N_200 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_899 : out std_logic; - N_898 : out std_logic; - N_897 : out std_logic; - N_896 : out std_logic; - N_895 : out std_logic; - N_894 : out std_logic; - N_893 : out std_logic; - N_892 : out std_logic; - N_891 : out std_logic; - N_890 : out std_logic; - N_889 : out std_logic; - N_888 : out std_logic; - N_887 : out std_logic; - N_884 : out std_logic; - N_883 : out std_logic; - N_882 : out std_logic; - N_881 : out std_logic; - N_880 : out std_logic; - N_878 : out std_logic; - N_877 : out std_logic; - N_876 : out std_logic; - N_874 : out std_logic; - N_871 : out std_logic; - N_870 : out std_logic; - N_869 : out std_logic; - N_868 : out std_logic; - N_634 : in std_logic := 'U'; - N_632 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - hit : out std_logic; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U' - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlbcam_0_0_1 - port( s2_ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - data : in std_logic_vector(31 downto 12) := (others => 'U'); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - tlbcam_write_op_1 : in std_logic_vector(6 to 6) := (others => 'U'); - tlbcam_write_op_1_1_0 : in std_logic_vector(6 to 6) := (others => 'U'); - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - pteout_4 : out std_logic; - pteout_3 : out std_logic; - pteout_2 : out std_logic; - pteout_31 : out std_logic; - pteout_30 : out std_logic; - pteout_29 : out std_logic; - pteout_28 : out std_logic; - pteout_27 : out std_logic; - pteout_26 : out std_logic; - pteout_25 : out std_logic; - pteout_24 : out std_logic; - pteout_23 : out std_logic; - pteout_22 : out std_logic; - pteout_21 : out std_logic; - pteout_20 : out std_logic; - pteout_19 : out std_logic; - pteout_18 : out std_logic; - pteout_17 : out std_logic; - pteout_16 : out std_logic; - pteout_15 : out std_logic; - pteout_14 : out std_logic; - pteout_13 : out std_logic; - pteout_12 : out std_logic; - pteout_11 : out std_logic; - pteout_10 : out std_logic; - pteout_9 : out std_logic; - pteout_8 : out std_logic; - pteout_1 : out std_logic; - pteout_0 : out std_logic; - pteout_7 : out std_logic; - pteout_6 : out std_logic; - s2_entry_5 : in std_logic_vector(2 to 2) := (others => 'U'); - LVL_0 : in std_logic_vector(0 to 0) := (others => 'U'); - tlbcam_write_op_1_0 : in std_logic_vector(6 to 6) := (others => 'U'); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - LVL_1 : out std_logic; - s2_entry_1_i_a2_1_2 : out std_logic_vector(1 to 1); - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_2482 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_635 : in std_logic := 'U'; - N_639 : in std_logic := 'U'; - N_665 : in std_logic := 'U'; - N_597 : in std_logic := 'U'; - N_798 : out std_logic; - N_632 : in std_logic := 'U'; - N_634 : in std_logic := 'U'; - N_596 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_620 : in std_logic := 'U'; - N_594 : in std_logic := 'U'; - N_593 : in std_logic := 'U'; - s2_flush_0 : in std_logic := 'U'; - hit_0_a3_0 : in std_logic := 'U'; - N_42 : in std_logic := 'U'; - N_200 : in std_logic := 'U'; - N_204 : in std_logic := 'U'; - N_631_i : in std_logic := 'U'; - N_633 : in std_logic := 'U'; - N_595 : in std_logic := 'U'; - N_663 : in std_logic := 'U'; - N_664 : in std_logic := 'U'; - N_651 : in std_logic := 'U'; - N_612 : in std_logic := 'U'; - N_200_0 : in std_logic := 'U'; - N_617 : in std_logic := 'U'; - N_650 : in std_logic := 'U'; - N_662 : in std_logic := 'U'; - N_170_1 : in std_logic := 'U' - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal dr1write_0_sqmuxa_0, N_6_i_0, s2_flush_0, s2_flush_1, - un1_rst_2, \s2_entry_0[0]\, N_208, s2_entry_0_sqmuxa, - \s2_entry_1[1]\, N_212_i_0, \s2_entry_0[1]\, - \s2_entry_5[2]\, \s2_entry_1[2]\, \s2_entry_4[2]\, - \s2_entry_3[2]\, \s2_entry_2[2]\, \s2_entry_1_0[2]\, - \s2_entry_0[2]\, walk_use_1, cache_0_sqmuxa_1_1, - s2_tlbstate_3, walk_use_0, N_553, N_2355, N_572, - \s2_tlbstate[1]\, \tlbcam_write_op_1_1[4]\, - \tlbcam_write_op_1_1[0]\, \tlbcam_write_op_1_0[4]\, - \tlbcam_write_op_1_1_0[6]\, \tlbcam_write_op_1_1[6]\, - \tlbcam_write_op_1_0[6]\, \tlbcam_write_op_1_1_0[0]\, - \tlbcam_write_op_1_0[0]\, \tlbcam_write_op_1_1_0[7]\, - \tlbcam_write_op_1_1[7]\, \tlbcam_write_op_1_0[7]\, - \tlbcam_write_op_1_1_0[5]\, \tlbcam_write_op_1_1[5]\, - \tlbcam_write_op_1_0[5]\, \tlbcam_write_op_1_1[1]\, - \tlbcam_write_op_1_0[1]\, \tlbcam_write_op_1_1[2]\, - \tlbcam_write_op_1_0[2]\, \tlbcam_write_op_1_1[3]\, - dr1write_0_sqmuxa, \tlbcam_write_op_1_0[3]\, N_200_0, - \data[8]\, N_2987, N_3069, \data_1_i_0[23]\, N_2985, - N_2984, sync_isw_1_i_i_a2_0_0, \s2_tlbstate_ns_0_0_1[0]\, - \s2_tlbstate[0]\, \s2_tlbstate_ns_0_0_0[0]\, sync_isw, - N_2568, N_557, \s2_tlbstate_ns_0_0_a2_2_0[0]\, - fault_mexc_3_0, fault_mexc_1_sqmuxa_1_0_i_i_a2_0, - N_1637_i_i_0, cam_hit_all_1_4, hit_i_0, cam_hit_all_1_2, - hit_i, cam_hit_all_1_0, SU_RNIAA5O8, N_170, hit_0_a3_2_0, - N_17_i_0, N_32_i, \data_1_i_0[14]\, \data[14]\, N_2667, - \data_1_i_0[22]\, \data[22]\, N_3026, fault_pri_6_m_1, - un11_finish_li, fault_inv_m, fault_trans_m, fault_pri_6_m, - N_2593, N_2981, N_2982, N_2983, N_2995, N_2996, N_2997, - N_2992, N_2993, N_2994, N_2988, N_2989, N_2990, N_2968, - N_2969, N_2970, N_2964, N_2965, N_2966, N_2669, N_2664, - N_2665, N_2666, N_2661, N_2662, N_2663, fault_inv, - fault_mexc_m, fault_mexc, N_3017, N_3019, N_3020, N_839, - N_3016, N_3014, cam_hit_all_1, N_3068, - cam_hit_all_1_sqmuxa, N_1633, \adata[3]\, N_2492, N_206, - N_556, \fault_su\, N_2559, N_2602, N_3162, N_2604, N_2603, - N_2673, N_2675, N_2674, N_3022, N_3021, N_3024, \N_1629\, - fault_trans, N_2611, nrep_n2, \nrep[2]\, nrep_494_0, - \nrep[1]\, \nrep[0]\, N_800, N_732, N_766, N_801, N_733, - N_767, N_802, N_734, N_768, N_803, N_735, N_769, N_806, - N_738, N_772, N_807, N_739, N_773, N_808, N_740, N_774, - N_809, N_741, N_775, N_810, N_742, N_776, N_812, N_744, - N_778, N_813, N_745, N_779, N_814, N_746, N_780, N_815, - N_747, N_781, N_816, N_748, N_782, N_817, N_749, N_783, - N_818, N_750, N_784, N_819, N_751, N_785, N_820, N_752, - N_786, N_821, N_753, N_787, N_822, N_754, N_788, N_823, - N_755, N_789, N_824, N_756, N_790, N_825, N_757, N_791, - N_826, N_758, N_792, N_827, N_759, N_793, N_828, N_760, - N_794, N_829, N_761, N_795, N_830, N_762, N_796, N_831, - N_763, N_797, N_902, N_834, N_868, N_903, N_835, N_869, - N_904, N_836, N_870, N_905, N_837, N_871, N_908, N_840, - N_874, N_909, N_841, C_RNIL004, N_910, N_842, N_876, - N_911, N_843, N_877, N_912, N_844, N_878, N_914, N_846, - N_880, N_915, N_847, N_881, N_916, N_848, N_882, N_917, - N_849, N_883, N_918, N_850, N_884, N_921, N_853, N_887, - N_922, N_854, N_888, N_923, N_855, N_889, N_924, N_856, - N_890, N_925, N_857, N_891, N_926, N_858, N_892, - \s2_entry[1]\, N_927, N_859, N_893, N_928, N_860, N_894, - N_929, N_861, N_895, N_930, N_862, N_896, N_931, N_863, - N_897, N_932, N_864, N_898, N_933, N_865, N_899, N_919, - \adata[19]\, \adata[21]\, \s2_entry[0]\, \adata[26]\, - N_631_i, N_632, N_633, N_634, N_635, \data[25]\, N_639, - N_650, N_662, N_663, N_664, fault_pri_m, fault_pri, - \fault_mexc_1\, N_554, \data[12]\, \data_0[12]\, - \adata[8]\, \data[13]\, \data_0[13]\, \adata[9]\, - \data_0[14]\, \adata[10]\, \fault_lvl[0]\, N_2728, - \data[24]\, N_2730, \data[26]\, \N_2571\, N_2731, - \data[27]\, \adata[23]\, N_3064, \data_0[27]\, N_3061, - \adata[24]\, \data[28]\, \adata[22]\, \data_0[26]\, - \adata[25]\, \data[29]\, \adata[27]\, \data[31]\, N_70, - \data_0[31]\, N_2621, N_2622, N_15, N_17, \data[15]\, - N_331, \data_0[29]\, N_67, N_593, N_594, N_597, \data[4]\, - \data_0[4]\, \data[5]\, \data_0[5]\, \data[6]\, - \data_0[6]\, \data[9]\, \data_0[9]\, N_612, \data[30]\, - s2_flush, N_617, N_620, N_630, \adata[16]\, \data[20]\, - \un1_acc[33]\, N_636, \data[19]\, N_640, N_651, - \data_0[28]\, N_665, N_667, \adata[15]\, N_2890, - \data[18]\, N_687, \data[21]\, N_689, \data[23]\, N_1039, - \adata[14]\, \data_0[18]\, \data_0[19]\, \data_0[15]\, - N_595, N_14, N_2917, N_16, N_18, N_175, N_573, N_204, - \data[10]\, sync_isw_RNO, \data_1[28]\, - \tlbcam_write_op_1[4]\, \tlbcam_write_op_1[3]\, - \tlbcam_write_op_1[2]\, \tlbcam_write_op_1[1]\, - \tlbcam_write_op_1[0]\, s2_hm, \data[2]\, \data_0[2]\, - N_562, N_596, \data[17]\, \adata[12]\, \data_0[16]\, - \data[16]\, N_2727, \adata[13]\, \data_0[17]\, - \un1_acc[32]\, N_832, N_934, N_866, N_900, N_764, N_798, - \tlbcam_write_op_1[6]\, \tlbcam_write_op_1[7]\, N_6_i, - N_198, N_2577, fault_pro, \adata[4]\, \adata[2]\, nrep_n1, - nrep_n0, nrepe, \cam_hitaddr_12[2]\, N_2937, - \s2_entry_1_i_a2_2[0]\, \s2_entry_1_i_a2_1[0]\, - \nrep_RNIIGE31[0]\, N_3058, N_167, N_555, - \twi_areq_ur_1_0_a3_i_0\, \walk_op_ur\, \N_2933\, - \s2_tlbstate_nss[1]\, \s1finished_0\, s1finished, N_688, - \data_0[22]\, N_833, N_935, N_867, N_901, N_765, N_799, - \tlbcam_write_op_1[5]\, \s2_entry[2]\, \adata[11]\, N_811, - N_913, N_845, N_879, N_743, N_777, N_200, \data_0[8]\, - \data_0[20]\, \walk_use\, \data_0[24]\, \adata[20]\, - \adata[17]\, \data_0[21]\, \data_0[23]\, N_2729, - \data_1[24]\, \data_0[25]\, \data_0[30]\, \adata[18]\, - N_920, N_852, N_886, N_2554, N_851, N_885, N_804, N_906, - N_838, N_872, N_736, N_770, \data[3]\, \data_0[3]\, - \data[7]\, \data_0[7]\, \data_0[10]\, \data[11]\, - \data_0[11]\, \adata[7]\, cache, \s2_tlbstate_nss[0]\, - \s2_ctx[0]\, \s2_ctx[1]\, \s2_ctx[2]\, \s2_ctx[3]\, - \s2_ctx[4]\, \s2_ctx[5]\, \s2_ctx[6]\, \s2_ctx[7]\, - \pteout[4]\, \pteout[3]\, \pteout[2]\, \pteout[31]\, - \pteout[30]\, \pteout[29]\, \pteout[28]\, \pteout[27]\, - \pteout[26]\, \pteout[25]\, \pteout[24]\, \pteout[23]\, - \pteout[22]\, \pteout[21]\, \pteout[20]\, \pteout[19]\, - \pteout[18]\, \pteout[17]\, \pteout[16]\, \pteout[15]\, - \pteout[14]\, \pteout[13]\, \pteout[12]\, \pteout[11]\, - \pteout[10]\, \pteout[9]\, \pteout[8]\, \pteout[1]\, - \pteout[0]\, \pteout[7]\, \pteout[6]\, \LVL[0]\, \LVL[1]\, - N_169_1, N_42, N_170_1, \pteout_0[4]\, \pteout_0[3]\, - \pteout_0[2]\, \pteout_0[31]\, \pteout_0[30]\, - \pteout_0[29]\, \pteout_0[28]\, \pteout_0[27]\, - \pteout_0[26]\, \pteout_0[25]\, \pteout_0[24]\, - \pteout_0[23]\, \pteout_0[22]\, \pteout_0[21]\, - \pteout_0[20]\, \pteout_0[19]\, \pteout_0[18]\, - \pteout_0[17]\, \pteout_0[16]\, \pteout_0[15]\, - \pteout_0[14]\, \pteout_0[13]\, \pteout_0[12]\, - \pteout_0[11]\, \pteout_0[10]\, \pteout_0[9]\, - \pteout_0[8]\, \pteout_0[1]\, \pteout_0[0]\, - \pteout_0[7]\, \pteout_0[6]\, \LVL_0[0]\, \LVL_0[1]\, - \s2_entry_1_i_a2_1_2[1]\, hit_0_a3_0, \pteout_1[4]\, - \pteout_1[3]\, \pteout_1[2]\, \pteout_1[31]\, - \pteout_1[30]\, \pteout_1[29]\, \pteout_1[28]\, - \pteout_1[27]\, \pteout_1[26]\, \pteout_1[25]\, - \pteout_1[24]\, \pteout_1[23]\, \pteout_1[22]\, - \pteout_1[21]\, \pteout_1[20]\, \pteout_1[19]\, - \pteout_1[18]\, \pteout_1[17]\, \pteout_1[16]\, - \pteout_1[15]\, \pteout_1[14]\, \pteout_1[13]\, - \pteout_1[12]\, \pteout_1[11]\, \pteout_1[10]\, - \pteout_1[9]\, \pteout_1[8]\, \pteout_1[1]\, - \pteout_1[0]\, \pteout_1[7]\, \pteout_1[6]\, \LVL_1[0]\, - \LVL_1[1]\, \s2_entry_1_i_a2_0[0]\, N_2937_1, - \pteout_2[4]\, \pteout_2[3]\, \pteout_2[2]\, - \pteout_2[31]\, \pteout_2[30]\, \pteout_2[29]\, - \pteout_2[28]\, \pteout_2[27]\, \pteout_2[26]\, - \pteout_2[25]\, \pteout_2[24]\, \pteout_2[23]\, - \pteout_2[22]\, \pteout_2[21]\, \pteout_2[20]\, - \pteout_2[19]\, \pteout_2[18]\, \pteout_2[17]\, - \pteout_2[16]\, \pteout_2[15]\, \pteout_2[14]\, - \pteout_2[13]\, \pteout_2[12]\, \pteout_2[11]\, - \pteout_2[10]\, \pteout_2[9]\, \pteout_2[8]\, - \pteout_2[1]\, \pteout_2[0]\, \pteout_2[7]\, - \pteout_2[6]\, \LVL_2[0]\, \LVL_2[1]\, hit, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : mmutlbcam_0_0_2 - Use entity work.mmutlbcam_0_0_2(DEF_ARCH); - for all : mmutlbcam_0_0_4 - Use entity work.mmutlbcam_0_0_4(DEF_ARCH); - for all : mmutlbcam_0_0 - Use entity work.mmutlbcam_0_0(DEF_ARCH); - for all : mmutlbcam_0_0_5 - Use entity work.mmutlbcam_0_0_5(DEF_ARCH); - for all : syncramZ0 - Use entity work.syncramZ0(DEF_ARCH); - for all : mmutlbcam_0_0_3 - Use entity work.mmutlbcam_0_0_3(DEF_ARCH); - for all : mmutlbcam_0_0_6 - Use entity work.mmutlbcam_0_0_6(DEF_ARCH); - for all : mmutlbcam_0_0_7 - Use entity work.mmutlbcam_0_0_7(DEF_ARCH); - for all : mmutlbcam_0_0_1 - Use entity work.mmutlbcam_0_0_1(DEF_ARCH); -begin - - data_0_29 <= \data_0[31]\; - data_0_27 <= \data_0[29]\; - data_0_26 <= \data_0[28]\; - data_0_20 <= \data_0[22]\; - data_0_12 <= \data_0[14]\; - data_14 <= \data[16]\; - data_21 <= \data[23]\; - data_16 <= \data[18]\; - data_19 <= \data[21]\; - data_17 <= \data[19]\; - data_15 <= \data[17]\; - data_24 <= \data[26]\; - data_22 <= \data[24]\; - data_18 <= \data[20]\; - data_25 <= \data[27]\; - data_13 <= \data[15]\; - data_11 <= \data[13]\; - data_10 <= \data[12]\; - data_23 <= \data[25]\; - data_28 <= \data[30]\; - adata_11 <= \adata[11]\; - adata_27 <= \adata[27]\; - adata_25 <= \adata[25]\; - adata_24 <= \adata[24]\; - adata_23 <= \adata[23]\; - adata_22 <= \adata[22]\; - adata_20 <= \adata[20]\; - adata_17 <= \adata[17]\; - adata_16 <= \adata[16]\; - adata_15 <= \adata[15]\; - adata_14 <= \adata[14]\; - adata_13 <= \adata[13]\; - adata_12 <= \adata[12]\; - adata_10 <= \adata[10]\; - adata_9 <= \adata[9]\; - adata_8 <= \adata[8]\; - adata_7 <= \adata[7]\; - adata_2 <= \adata[2]\; - adata_18 <= \adata[18]\; - adata_21 <= \adata[21]\; - adata_26 <= \adata[26]\; - adata_4 <= \adata[4]\; - adata_3 <= \adata[3]\; - adata_19 <= \adata[19]\; - s2_tlbstate_0 <= \s2_tlbstate[0]\; - walk_use <= \walk_use\; - N_2933 <= \N_2933\; - walk_op_ur <= \walk_op_ur\; - N_2571 <= \N_2571\; - N_1629 <= \N_1629\; - fault_su <= \fault_su\; - twi_areq_ur_1_0_a3_i_0 <= \twi_areq_ur_1_0_a3_i_0\; - fault_mexc_1 <= \fault_mexc_1\; - s1finished_0 <= \s1finished_0\; - - \r.s2_entry_5_RNIA2ARQ2[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => \tlbcam_write_op_1[7]\); - - \r.s2_entry_0_RNI61LN1[0]\ : MX2 - port map(A => N_822, B => N_924, S => \s2_entry_0[0]\, Y - => \adata[22]\); - - \r.s2_data_RNIPDQC[13]\ : MX2C - port map(A => address(13), B => \data[13]\, S => s2_flush_0, - Y => N_632); - - \p0.transdata.data_1_i_RNO_1[23]\ : OR2A - port map(A => \walk_use\, B => \data_0[23]\, Y => N_2984); - - \r.s2_entry_RNIVAT2_0[0]\ : OR2A - port map(A => \s2_entry[1]\, B => \s2_entry[0]\, Y => - \tlbcam_write_op_1_1[6]\); - - \r.s2_data_RNISVTP[22]\ : OR3A - port map(A => \un1_acc[33]\, B => \walk_use\, C => - \data_0[22]\, Y => N_3026); - - \r.s2_tlbstate_RNO_2[0]\ : OA1A - port map(A => sync_isw, B => N_2568, C => N_557, Y => - \s2_tlbstate_ns_0_0_0[0]\); - - \r.s2_entry_RNI2PQ93[0]\ : OR2 - port map(A => \adata[24]\, B => N_3064, Y => N_2968); - - \r.s2_entry_1_RNI9L2Q[1]\ : MX2 - port map(A => N_759, B => N_793, S => \s2_entry_1[1]\, Y - => N_827); - - \r.s2_data_RNITLQC[15]\ : MX2C - port map(A => address(15), B => \data[15]\, S => s2_flush_0, - Y => N_634); - - \r.s2_hm_RNO\ : OR3C - port map(A => cam_hit_all_1_4, B => N_3068, C => - cam_hit_all_1_sqmuxa, Y => cam_hit_all_1); - - \r.s2_entry_RNINAIJ1[0]\ : MX2 - port map(A => N_827, B => N_929, S => \s2_entry[0]\, Y => - \adata[27]\); - - \r.walk_transdata.data_RNO[19]\ : MX2 - port map(A => hrdata_0_14, B => \data[19]\, S => - lvl_i_1_0(1), Y => N_636); - - \r.s2_entry_0_RNI487L1[0]\ : NOR2A - port map(A => \adata[4]\, B => \adata[2]\, Y => N_2492); - - \r.s2_data_RNI0J2E[16]\ : MX2C - port map(A => address(16), B => \data[16]\, S => s2_flush, - Y => N_595); - - \tlbcam0.0.tag0\ : mmutlbcam_0_0_2 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - lvl_i_1(1) => lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - hrdata_0_17 => hrdata_0_23, hrdata_0_10 => hrdata_0_16, - hrdata_0_7 => hrdata_0_13, hrdata_0_6 => hrdata_0_12, - hrdata_0_4 => hrdata_0_10, hrdata_0_3 => hrdata_0_9, - hrdata_0_2 => hrdata_0_8, hrdata_0_0 => hrdata_0_6, - tlbcam_write_op_1(0) => \tlbcam_write_op_1[0]\, - tlbcam_write_op_1_1_0(0) => \tlbcam_write_op_1_1_0[0]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 - => hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => - hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 => - hrdata_0_d0, hrdata_6 => hrdata_6, s2_entry(2) => - \s2_entry[2]\, s2_entry_5(2) => \s2_entry_5[2]\, LVL_0(1) - => \LVL[1]\, LVL_0(0) => \LVL[0]\, s2_entry_1(2) => - \s2_entry_1_0[2]\, s2_entry_0(2) => \s2_entry_0[2]\, - pteout_0_17 => \pteout[17]\, pteout_0_11 => \pteout[11]\, - pteout_0_31 => \pteout[31]\, pteout_0_30 => \pteout[30]\, - pteout_0_29 => \pteout[29]\, pteout_0_28 => \pteout[28]\, - pteout_0_27 => \pteout[27]\, pteout_0_26 => \pteout[26]\, - pteout_0_25 => \pteout[25]\, pteout_0_24 => \pteout[24]\, - pteout_0_23 => \pteout[23]\, pteout_0_22 => \pteout[22]\, - pteout_0_21 => \pteout[21]\, pteout_0_20 => \pteout[20]\, - pteout_0_19 => \pteout[19]\, pteout_0_18 => \pteout[18]\, - pteout_0_16 => \pteout[16]\, pteout_0_15 => \pteout[15]\, - pteout_0_14 => \pteout[14]\, pteout_0_13 => \pteout[13]\, - pteout_0_12 => \pteout[12]\, pteout_0_10 => \pteout[10]\, - pteout_0_9 => \pteout[9]\, pteout_0_8 => \pteout[8]\, - pteout_0_7 => \pteout[7]\, pteout_0_6 => \pteout[6]\, - pteout_0_4 => \pteout[4]\, pteout_0_3 => \pteout[3]\, - pteout_0_2 => \pteout[2]\, pteout_0_1 => \pteout[1]\, - pteout_0_0 => \pteout[0]\, tlbcam_write_op_1_0(0) => - \tlbcam_write_op_1_0[0]\, data_14 => \data[23]\, data_13 - => \data_0[22]\, data_12 => \data[21]\, data_11 => - \data[20]\, data_10 => \data[19]\, data_9 => \data[18]\, - data_8 => \data[17]\, data_7 => \data[16]\, data_6 => - \data[15]\, data_5 => \data_0[14]\, data_4 => \data[13]\, - data_3 => \data[12]\, data_22 => \data_0[31]\, data_21 - => \data[30]\, data_20 => \data_0[29]\, data_19 => - \data_0[28]\, data_18 => \data[27]\, data_17 => - \data[26]\, data_16 => \data[25]\, data_15 => \data[24]\, - data_0 => \data[9]\, ctx_0(7) => ctx_0(7), ctx_0(6) => - ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), - ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => - ctx_0(1), ctx_0(0) => ctx_0(0), N_78_0 => N_78_0, N_262_0 - => N_262_0, N_264_0 => N_264_0, N_2482 => N_2482, lclk_c - => lclk_c, N_749 => N_749, N_743 => N_743, N_765 => - N_765, s2_flush => s2_flush, N_764 => N_764, N_596 => - N_596, un1_rst_i_0 => un1_rst_i_0, N_620 => N_620, N_594 - => N_594, N_593 => N_593, N_597 => N_597, N_665 => N_665, - N_763 => N_763, N_762 => N_762, N_761 => N_761, N_760 => - N_760, N_759 => N_759, N_758 => N_758, N_757 => N_757, - N_756 => N_756, N_755 => N_755, N_754 => N_754, N_753 => - N_753, N_752 => N_752, N_751 => N_751, N_750 => N_750, - N_748 => N_748, N_747 => N_747, N_746 => N_746, N_745 => - N_745, N_744 => N_744, N_742 => N_742, N_741 => N_741, - N_740 => N_740, N_739 => N_739, N_738 => N_738, N_736 => - N_736, N_735 => N_735, N_734 => N_734, N_733 => N_733, - N_732 => N_732, N_634 => N_634, N_632 => N_632, N_639 => - N_639, N_635 => N_635, SU_RNIAA5O8 => SU_RNIAA5O8, - hit_0_a3_0 => hit_0_a3_0, s2_flush_0 => s2_flush_0, - N_169_1 => N_169_1, N_200 => N_200, N_32_i => N_32_i, - N_631_i => N_631_i, N_633 => N_633, N_595 => N_595, N_663 - => N_663, N_664 => N_664, N_651 => N_651, N_612 => N_612, - N_617 => N_617, N_650 => N_650, N_662 => N_662, - hit_0_a3_2_0 => hit_0_a3_2_0, N_17_i_0 => N_17_i_0, N_204 - => N_204, N_170_1 => N_170_1, N_170 => N_170, N_200_0 - => N_200_0, N_42 => N_42); - - \r.sync_isw_RNO_1\ : OR3C - port map(A => N_2568, B => sync_isw, C => rst, Y => N_2593); - - \r.walk_fault.fault_mexc_RNIEUV75\ : AO1B - port map(A => un1_m0_2_0(35), B => fault_mexc_0, C => - fault_mexc_m, Y => \fault_mexc_1\); - - \r.s2_entry_1_RNIPCPE[1]\ : MX2 - port map(A => N_837, B => N_871, S => \s2_entry_1[1]\, Y - => N_905); - - \r.s2_entry_0_RNIIKVP[1]\ : MX2 - port map(A => N_754, B => N_788, S => \s2_entry_0[1]\, Y - => N_822); - - \r.s2_entry_0_RNIRH7RQ2_2[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => - \tlbcam_write_op_1_1[4]\); - - \r.s2_entry_RNI4QFJ1[0]\ : MX2 - port map(A => N_825, B => N_927, S => \s2_entry[0]\, Y => - \adata[25]\); - - \r.s2_entry_0_RNI8G211[0]\ : MX2 - port map(A => N_803, B => N_905, S => \s2_entry_0[0]\, Y - => \adata[3]\); - - \r.s2_su_RNI2GTB1\ : NOR3 - port map(A => walk_use_0, B => \fault_su\, C => - un11_finish_li, Y => fault_pri_6_m_1); - - \r.s2_entry_RNI7HTN[1]\ : MX2 - port map(A => N_864, B => N_898, S => \s2_entry[1]\, Y => - N_932); - - \r.s2_entry_5_RNIA2ARQ2_2[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => \tlbcam_write_op_1[3]\); - - \r.s2_entry_1_RNI452Q[1]\ : MX2 - port map(A => N_855, B => N_889, S => \s2_entry_1[1]\, Y - => N_923); - - \r.s2_entry_RNIUD3PQ2[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => \s2_entry[2]\, C => - \tlbcam_write_op_1_1[5]\, Y => \tlbcam_write_op_1[5]\); - - \r.nrep[0]\ : DFN1E1 - port map(D => nrep_n0, CLK => lclk_c, E => nrepe, Q => - \nrep[0]\); - - \r.walk_transdata.data[20]\ : DFN1E0 - port map(D => N_640, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[20]\); - - \r.s2_entry_0_RNIR4O21[0]\ : MX2 - port map(A => N_812, B => N_914, S => \s2_entry_0[0]\, Y - => \adata[12]\); - - \r.s2_data[13]\ : DFN1E1 - port map(D => address(13), CLK => lclk_c, E => - \s1finished_0\, Q => \data[13]\); - - \r.s2_data_RNI3UQC[26]\ : MX2C - port map(A => address(26), B => \data[26]\, S => s2_flush_0, - Y => N_664); - - \r.walk_fault.fault_trans_RNO\ : NOR2 - port map(A => fault_trans_i_2, B => N_2917, Y => N_14); - - \r.s2_entry_RNIVAT2_1[0]\ : OR2A - port map(A => \s2_entry[0]\, B => \s2_entry[1]\, Y => - \tlbcam_write_op_1_1[5]\); - - \r.s2_entry_0_RNI34O21[0]\ : MX2 - port map(A => N_809, B => N_911, S => \s2_entry_0[0]\, Y - => \adata[9]\); - - \r.s2_entry_0_RNIF4SF[1]\ : MX2 - port map(A => N_739, B => N_773, S => \s2_entry_0[1]\, Y - => N_807); - - \r.walk_transdata.cache_RNIUFP81\ : MX2 - port map(A => \adata[7]\, B => cache, S => \walk_use\, Y - => un1_m0_30); - - \r.s2_entry_0_RNIUDHF[1]\ : MX2 - port map(A => N_740, B => N_774, S => \s2_entry_0[1]\, Y - => N_808); - - \r.walk_fault.fault_mexc_RNO_1\ : OR2A - port map(A => \s2_tlbstate[0]\, B => sync_isw, Y => - fault_mexc_1_sqmuxa_1_0_i_i_a2_0); - - \r.s2_data[17]\ : DFN1E1 - port map(D => address(17), CLK => lclk_c, E => - \s1finished_0\, Q => \data[17]\); - - \r.walk_fault.fault_pri_RNIGT9E\ : NOR2B - port map(A => walk_use_0, B => fault_pri, Y => fault_pri_m); - - \r.s2_data[22]\ : DFN1E1 - port map(D => address(22), CLK => lclk_c, E => s1finished, - Q => \data_0[22]\); - - \r.s2_ctx[1]\ : DFN1E1 - port map(D => ctx(1), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[1]\); - - \r.s2_entry[0]\ : DFN1E1 - port map(D => N_208, CLK => lclk_c, E => s2_entry_0_sqmuxa, - Q => \s2_entry[0]\); - - \r.s2_data_RNIP9QC[21]\ : MX2C - port map(A => address(21), B => \data[21]\, S => s2_flush_0, - Y => N_594); - - \r.s2_entry_RNI6OF9[1]\ : MX2 - port map(A => N_867, B => N_901, S => \s2_entry[1]\, Y => - N_935); - - \r.s2_entry_0_RNIMEHF[1]\ : MX2 - port map(A => N_746, B => N_780, S => \s2_entry_0[1]\, Y - => N_814); - - \r.s2_data_RNITDQC[31]\ : MX2C - port map(A => address(31), B => \data_0[31]\, S => - s2_flush_0, Y => N_597); - - \r.s2_hm_RNO_2\ : AOI1B - port map(A => hit_0_a3_2_0, B => N_17_i_0, C => N_32_i, Y - => cam_hit_all_1_0); - - \r.s2_tlbstate_RNO_0[1]\ : AOI1 - port map(A => s2_flush, B => N_555, C => \s2_tlbstate[0]\, - Y => N_167); - - \r.s2_entry_0_RNIAKUP[1]\ : MX2 - port map(A => N_752, B => N_786, S => \s2_entry_0[1]\, Y - => N_820); - - \r.walk_use_1\ : DFN1E1 - port map(D => cache_0_sqmuxa_1_1, CLK => lclk_c, E => - s2_tlbstate_3, Q => walk_use_1); - - \r.s2_entry_0_RNIRH7RQ2_4[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => - \tlbcam_write_op_1_0[5]\); - - \r.walk_use_0_RNI6O2T2\ : OR3 - port map(A => N_554, B => walk_use_0, C => \adata[9]\, Y - => N_2666); - - \r.s2_tlbstate_RNI1PHJN[1]\ : OR3B - port map(A => \s2_tlbstate[0]\, B => N_2563_i, C => - \s2_tlbstate[1]\, Y => N_6_i); - - \r.s2_tlbstate_RNI3O7FO[1]\ : OR2B - port map(A => N_556, B => N_6_i_0, Y => N_573); - - \r.s2_entry_0_RNINS711[0]\ : MX2 - port map(A => N_807, B => N_909, S => \s2_entry_0[0]\, Y - => \adata[7]\); - - \r.nrep_RNO_0[2]\ : OR2B - port map(A => \nrep[1]\, B => \nrep[0]\, Y => nrep_494_0); - - \r.s2_entry_0_RNIRH7RQ2_12[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => - \tlbcam_write_op_1_0[1]\); - - \r.s2_data_RNI56RC[19]\ : MX2C - port map(A => address(19), B => \data[19]\, S => s2_flush_0, - Y => N_593); - - \r.walk_fault.fault_trans\ : DFN1E1 - port map(D => N_14, CLK => lclk_c, E => N_573, Q => - fault_trans); - - \r.s2_entry_0_RNIB5O21[0]\ : MX2 - port map(A => N_814, B => N_916, S => \s2_entry_0[0]\, Y - => \adata[14]\); - - \r.s2_ctx[0]\ : DFN1E1 - port map(D => ctx(0), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[0]\); - - \r.walk_transdata.data_RNO[18]\ : MX2 - port map(A => hrdata_0_13, B => \data[18]\, S => - lvl_i_1_0(1), Y => N_2890); - - \r.s2_entry_0_RNIRH7RQ2[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_1_0[7]\); - - \r.s2_flush\ : DFN1E1 - port map(D => s2_flush_1, CLK => lclk_c, E => un1_rst_2, Q - => s2_flush); - - \r.s2_data_RNIPQP8[10]\ : OR2B - port map(A => \data[10]\, B => s2_flush, Y => N_204); - - \r.s2_entry_RNI7OLJ[0]\ : MX2 - port map(A => N_811, B => N_913, S => \s2_entry[0]\, Y => - \adata[11]\); - - \r.walk_transdata.data_RNIEQQ9[7]\ : MX2C - port map(A => \data[7]\, B => \data_0[7]\, S => \walk_use\, - Y => un1_m0_5); - - \r.walk_fault.fault_pro_RNO\ : OA1C - port map(A => hrdata_0_3, B => hrdata_0_1, C => - N_1637_i_i_0, Y => N_2559); - - \r.s2_entry_1_RNID6VF[1]\ : MX2 - port map(A => N_840, B => N_874, S => \s2_entry_1[1]\, Y - => N_908); - - \r.s2_entry_RNIV11O[1]\ : MX2 - port map(A => N_861, B => N_895, S => \s2_entry[1]\, Y => - N_929); - - \r.walk_use_0_RNIUN2T2\ : OR3 - port map(A => N_554, B => walk_use_0, C => \adata[8]\, Y - => N_2663); - - \r.sync_isw_RNI1N17\ : NOR2A - port map(A => fault_mexc_2, B => sync_isw, Y => N_3058); - - \r.s2_entry_1_RNI1VJF[1]\ : MX2 - port map(A => N_846, B => N_880, S => \s2_entry_1[1]\, Y - => N_914); - - \r.s2_entry_5_RNIA2ARQ2_0[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => \tlbcam_write_op_1[6]\); - - \r.walk_fault.fault_lvl[0]\ : DFN1E0 - port map(D => N_80, CLK => lclk_c, E => N_6_i_0, Q => - \fault_lvl[0]\); - - \r.s2_tlbstate_RNILJJC[1]\ : OR2B - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => N_2568); - - \r.s2_tlbstate_RNIRHMJ[1]\ : NOR2B - port map(A => tlbactive, B => \N_2933\, Y => N_572); - - \r.s2_data[25]\ : DFN1E1 - port map(D => address(25), CLK => lclk_c, E => s1finished, - Q => \data[25]\); - - \r.walk_transdata.data[10]\ : DFN1E0 - port map(D => \data[10]\, CLK => lclk_c, E => N_6_i_0, Q - => \data_0[10]\); - - \r.s2_entry_RNIEI39[1]\ : MX2 - port map(A => N_845, B => N_879, S => \s2_entry[1]\, Y => - N_913); - - \r.walk_use_0_RNI1LUH3\ : OR3A - port map(A => N_3162, B => \adata[21]\, C => walk_use_0, Y - => N_2673); - - \r.walk_transdata.data_RNIL84D[17]\ : OR2A - port map(A => walk_use_1, B => \data_0[17]\, Y => N_3019); - - \r.s2_entry_0_RNIRH7RQ2_14[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => - \tlbcam_write_op_1_0[0]\); - - \r.s2_data[31]\ : DFN1E1 - port map(D => address(31), CLK => lclk_c, E => s1finished, - Q => \data_0[31]\); - - \r.s2_entry_0_RNIOB1H1[0]\ : OR2 - port map(A => \adata[17]\, B => N_3069, Y => N_3024); - - \r.walk_transdata.data[24]\ : DFN1E0 - port map(D => N_2728, CLK => lclk_c, E => N_6_i, Q => - \data_1[24]\); - - \r.s2_data_RNIFNC55[16]\ : OR3C - port map(A => N_839, B => N_3016, C => N_3014, Y => N_423); - - \r.s2_data_RNIQI6E5[28]\ : OR3C - port map(A => N_2968, B => N_2969, C => N_2970, Y => N_321); - - \r.walk_transdata.data_RNIAFPD[6]\ : MX2C - port map(A => \data[6]\, B => \data_0[6]\, S => walk_use_1, - Y => un1_m0_4); - - \r.s2_hm_RNIQOF91_0\ : OAI1 - port map(A => N_553, B => N_2355, C => N_572, Y => - \s1finished_0\); - - \r.walk_use_0_RNIFERD3\ : OR3A - port map(A => N_3162, B => \adata[26]\, C => walk_use_0, Y - => N_2602); - - \r.walk_transdata.cache\ : DFN1E0 - port map(D => hrdata_7, CLK => lclk_c, E => N_6_i_0, Q => - cache); - - \r.s2_data[12]\ : DFN1E1 - port map(D => address(12), CLK => lclk_c, E => - \s1finished_0\, Q => \data[12]\); - - \p0.tlb_mergedata.v.walk_transdata.data_3_i_o2_0_o2[30]\ : - OR2B - port map(A => lvl_i_1_0(1), B => lvl_i_1(0), Y => \N_2571\); - - \r.walk_fault.fault_inv\ : DFN1E1 - port map(D => N_18, CLK => lclk_c, E => N_573, Q => - fault_inv); - - \r.s2_data_RNIVLQC[24]\ : MX2C - port map(A => address(24), B => \data[24]\, S => s2_flush_0, - Y => N_663); - - \r.s2_entry_0_RNIM0JN1[0]\ : MX2 - port map(A => N_820, B => N_922, S => \s2_entry_0[0]\, Y - => \adata[20]\); - - \r.nrep[2]\ : DFN1E1 - port map(D => nrep_n2, CLK => lclk_c, E => nrepe, Q => - \nrep[2]\); - - \r.walk_transdata.data_RNIJ04D[15]\ : OR2A - port map(A => walk_use_1, B => \data_0[15]\, Y => N_2982); - - \r.s2_tlbstate_RNIMALJ[1]\ : OA1A - port map(A => \s2_tlbstate[1]\, B => N_3058, C => - \s2_tlbstate[0]\, Y => cache_0_sqmuxa_1_1); - - \r.s2_entry_0_RNIH1UN[0]\ : MX2 - port map(A => N_817, B => N_919, S => \s2_entry_0[0]\, Y - => \adata[17]\); - - \r.s2_data_RNIRHQC[14]\ : MX2C - port map(A => address(14), B => \data_0[14]\, S => - s2_flush_0, Y => N_633); - - \r.walk_transdata.data_RNO[25]\ : MX2 - port map(A => \data[25]\, B => hrdata_0_20, S => \N_2571\, - Y => N_2729); - - \r.walk_transdata.data_RNIGQQ9[8]\ : MX2C - port map(A => \data[8]\, B => \data_0[8]\, S => \walk_use\, - Y => un1_m0_6); - - \r.walk_transdata.data[31]\ : DFN1E0 - port map(D => N_70, CLK => lclk_c, E => N_6_i, Q => - \data[31]\); - - \r.s2_data[3]\ : DFN1E1 - port map(D => address(3), CLK => lclk_c, E => s1finished, Q - => \data[3]\); - - \r.walk_transdata.data_RNIGO3D[13]\ : OR2A - port map(A => walk_use_0, B => \data_0[13]\, Y => N_2665); - - \r.s2_hm_RNI4UIE\ : NOR2A - port map(A => tlbactive, B => N_2355, Y => N_562); - - \r.s2_entry_RNIVAT2[0]\ : OR2B - port map(A => \s2_entry[1]\, B => \s2_entry[0]\, Y => - \tlbcam_write_op_1_1[7]\); - - \r.s2_ctx[4]\ : DFN1E1 - port map(D => ctx(4), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[4]\); - - \r.s2_tlbstate_RNI179E[0]\ : OR2 - port map(A => \s2_tlbstate[0]\, B => s2_flush, Y => N_553); - - GND_i : GND - port map(Y => \GND\); - - \r.s2_entry_5_RNIA2ARQ2_5[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => \tlbcam_write_op_1[0]\); - - \r.s2_entry_0_RNIN5SF[1]\ : MX2 - port map(A => N_738, B => N_772, S => \s2_entry_0[1]\, Y - => N_806); - - \r.s2_data_RNI534K2[21]\ : OR3C - port map(A => N_3022, B => N_3021, C => N_3024, Y => N_427); - - \r.s2_ctx[6]\ : DFN1E1 - port map(D => ctx(6), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[6]\); - - \tlbcam0.5.tag0\ : mmutlbcam_0_0_4 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0(7) => - hrdata_0_6, tlbcam_write_op_1(5) => - \tlbcam_write_op_1[5]\, tlbcam_write_op_1_1_0(5) => - \tlbcam_write_op_1_1_0[5]\, hrdata_4 => hrdata_4, - hrdata_3 => hrdata_3, hrdata_2 => hrdata_2, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0_d0 => hrdata_0_d0, hrdata_6 => hrdata_6, - pteout_4 => \pteout_2[4]\, pteout_3 => \pteout_2[3]\, - pteout_2 => \pteout_2[2]\, pteout_31 => \pteout_2[31]\, - pteout_30 => \pteout_2[30]\, pteout_29 => \pteout_2[29]\, - pteout_28 => \pteout_2[28]\, pteout_27 => \pteout_2[27]\, - pteout_26 => \pteout_2[26]\, pteout_25 => \pteout_2[25]\, - pteout_24 => \pteout_2[24]\, pteout_23 => \pteout_2[23]\, - pteout_22 => \pteout_2[22]\, pteout_21 => \pteout_2[21]\, - pteout_20 => \pteout_2[20]\, pteout_19 => \pteout_2[19]\, - pteout_18 => \pteout_2[18]\, pteout_17 => \pteout_2[17]\, - pteout_16 => \pteout_2[16]\, pteout_15 => \pteout_2[15]\, - pteout_14 => \pteout_2[14]\, pteout_13 => \pteout_2[13]\, - pteout_12 => \pteout_2[12]\, pteout_11 => \pteout_2[11]\, - pteout_10 => \pteout_2[10]\, pteout_9 => \pteout_2[9]\, - pteout_8 => \pteout_2[8]\, pteout_1 => \pteout_2[1]\, - pteout_0 => \pteout_2[0]\, pteout_7 => \pteout_2[7]\, - pteout_6 => \pteout_2[6]\, tlbcam_write_op_1_0(5) => - \tlbcam_write_op_1_0[5]\, ctx_0(7) => ctx_0(7), ctx_0(6) - => ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), - ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => - ctx_0(1), ctx_0(0) => ctx_0(0), LVL(1) => \LVL_2[1]\, - LVL(0) => \LVL_2[0]\, s2_entry_1_i_a2_1(0) => - \s2_entry_1_i_a2_1[0]\, N_78 => N_78, N_262 => N_262, - N_264 => N_264, N_2482 => N_2482, lclk_c => lclk_c, - N_2937_1 => N_2937_1, cam_hit_all_1_sqmuxa => - cam_hit_all_1_sqmuxa, s2_flush => s2_flush, un1_rst_i_0 - => un1_rst_i_0, N_42 => N_42, N_635 => N_635, N_639 => - N_639, N_632 => N_632, N_634 => N_634, N_594 => N_594, - N_596 => N_596, N_620 => N_620, N_593 => N_593, N_597 => - N_597, N_665 => N_665, hit_0_a3_0 => hit_0_a3_0, N_200 - => N_200, N_170_1 => N_170_1, N_663 => N_663, N_664 => - N_664, N_651 => N_651, N_612 => N_612, N_631_i => N_631_i, - N_633 => N_633, N_595 => N_595, N_200_0 => N_200_0, N_617 - => N_617, N_650 => N_650, N_662 => N_662, N_204 => N_204, - hit => hit); - - \r.s2_entry_RNIRH0O[1]\ : MX2 - port map(A => N_860, B => N_894, S => \s2_entry[1]\, Y => - N_928); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.s2_entry_0_RNIRH7RQ2_6[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => - \tlbcam_write_op_1_0[4]\); - - \r.walk_transdata.data_RNIAU0F3[22]\ : OAI1 - port map(A => N_3069, B => \adata[18]\, C => - \data_1_i_0[22]\, Y => N_429); - - \r.s2_entry_0_RNI64UP[1]\ : MX2 - port map(A => N_751, B => N_785, S => \s2_entry_0[1]\, Y - => N_819); - - \r.s2_tlbstate_RNILJJC_0[1]\ : OR2A - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => \N_2933\); - - \r.s2_data[26]\ : DFN1E1 - port map(D => address(26), CLK => lclk_c, E => s1finished, - Q => \data[26]\); - - \tlbcam0.4.tag0\ : mmutlbcam_0_0 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1_0(1) => - lvl_i_1_0(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0_17 => - hrdata_0_23, hrdata_0_10 => hrdata_0_16, hrdata_0_7 => - hrdata_0_13, hrdata_0_6 => hrdata_0_12, hrdata_0_4 => - hrdata_0_10, hrdata_0_3 => hrdata_0_9, hrdata_0_2 => - hrdata_0_8, hrdata_0_0 => hrdata_0_6, - tlbcam_write_op_1(4) => \tlbcam_write_op_1[4]\, - tlbcam_write_op_1_1(4) => \tlbcam_write_op_1_1[4]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 - => hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => - hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 => - hrdata_0_d0, hrdata_6 => hrdata_6, pteout_4 => - \pteout[4]\, pteout_3 => \pteout[3]\, pteout_2 => - \pteout[2]\, pteout_31 => \pteout[31]\, pteout_30 => - \pteout[30]\, pteout_29 => \pteout[29]\, pteout_28 => - \pteout[28]\, pteout_27 => \pteout[27]\, pteout_26 => - \pteout[26]\, pteout_25 => \pteout[25]\, pteout_24 => - \pteout[24]\, pteout_23 => \pteout[23]\, pteout_22 => - \pteout[22]\, pteout_21 => \pteout[21]\, pteout_20 => - \pteout[20]\, pteout_19 => \pteout[19]\, pteout_18 => - \pteout[18]\, pteout_17 => \pteout[17]\, pteout_16 => - \pteout[16]\, pteout_15 => \pteout[15]\, pteout_14 => - \pteout[14]\, pteout_13 => \pteout[13]\, pteout_12 => - \pteout[12]\, pteout_11 => \pteout[11]\, pteout_10 => - \pteout[10]\, pteout_9 => \pteout[9]\, pteout_8 => - \pteout[8]\, pteout_1 => \pteout[1]\, pteout_0 => - \pteout[0]\, pteout_7 => \pteout[7]\, pteout_6 => - \pteout[6]\, tlbcam_write_op_1_0(4) => - \tlbcam_write_op_1_0[4]\, cam_hitaddr_12(2) => - \cam_hitaddr_12[2]\, ctx_0(7) => ctx_0(7), ctx_0(6) => - ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), - ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => - ctx_0(1), ctx_0(0) => ctx_0(0), LVL(1) => \LVL[1]\, - LVL(0) => \LVL[0]\, N_78_0 => N_78_0, N_262_0 => N_262_0, - N_264_0 => N_264_0, N_2482 => N_2482, lclk_c => lclk_c, - N_634 => N_634, N_594 => N_594, N_596 => N_596, N_169_1 - => N_169_1, un1_rst_i_0 => un1_rst_i_0, s2_flush => - s2_flush, cam_hit_all_1_sqmuxa => cam_hit_all_1_sqmuxa, - N_635 => N_635, N_639 => N_639, N_665 => N_665, N_597 => - N_597, N_620 => N_620, N_593 => N_593, N_632 => N_632, - N_204 => N_204, N_200 => N_200, N_42 => N_42, hit_i => - hit_i, N_663 => N_663, N_664 => N_664, N_651 => N_651, - N_612 => N_612, N_631_i => N_631_i, N_633 => N_633, N_595 - => N_595, N_200_0 => N_200_0, N_617 => N_617, N_650 => - N_650, N_662 => N_662, N_170_1 => N_170_1); - - \r.s2_entry_RNI4O4K[0]\ : MX2 - port map(A => N_804, B => N_906, S => \s2_entry[0]\, Y => - \adata[4]\); - - \r.s2_entry_0_RNIRH7RQ2_13[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => - \tlbcam_write_op_1_0[2]\); - - \r.walk_transdata.data_RNIHG3D[31]\ : OR2A - port map(A => walk_use_1, B => \data[31]\, Y => N_2996); - - \r.s2_entry_0_RNIRH7RQ2_8[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => - \tlbcam_write_op_1_1[1]\); - - \r.walk_transdata.data_RNICK171[22]\ : OA1A - port map(A => walk_use_0, B => \data[22]\, C => N_3026, Y - => \data_1_i_0[22]\); - - \r.walk_transdata.data[23]\ : DFN1E0 - port map(D => N_689, CLK => lclk_c, E => N_6_i, Q => - \data_0[23]\); - - \r.walk_transdata.data_RNIK44D[16]\ : OR2A - port map(A => walk_use_1, B => \data_0[16]\, Y => N_3016); - - \r.s2_data[15]\ : DFN1E1 - port map(D => address(15), CLK => lclk_c, E => - \s1finished_0\, Q => \data[15]\); - - \r.walk_transdata.data_RNIGFPD[9]\ : MX2C - port map(A => \data[9]\, B => \data_0[9]\, S => walk_use_1, - Y => un1_m0_7); - - \r.s2_entry_RNIQO9J1[0]\ : MX2 - port map(A => N_828, B => N_930, S => \s2_entry[0]\, Y => - adata_28); - - \r.walk_transdata.data[14]\ : DFN1E0 - port map(D => N_15, CLK => lclk_c, E => N_6_i_0, Q => - \data[14]\); - - \r.nrep_RNIIGE31[0]\ : NOR2 - port map(A => \nrep[0]\, B => N_557, Y => - \nrep_RNIIGE31[0]\); - - \r.s2_data_RNIA33E[29]\ : MX2C - port map(A => address(29), B => \data_0[29]\, S => s2_flush, - Y => N_665); - - \p0.transdata.data_1_i_a2_1[23]\ : OR2 - port map(A => N_3069, B => \adata[19]\, Y => N_2987); - - \r.nrep_RNIF78IV4[0]\ : AOI1 - port map(A => \s2_entry_1_i_a2_2[0]\, B => - \s2_entry_1_i_a2_1[0]\, C => \nrep_RNIIGE31[0]\, Y => - N_208); - - \r.s2_entry_1_RNIHVJF[1]\ : MX2 - port map(A => N_850, B => N_884, S => \s2_entry_1[1]\, Y - => N_918); - - \r.s2_tlbstate_RNO[1]\ : NOR3A - port map(A => rst, B => N_167, C => \walk_op_ur\, Y => - \s2_tlbstate_nss[1]\); - - \r.s2_data[28]\ : DFN1E1 - port map(D => address(28), CLK => lclk_c, E => s1finished, - Q => \data_0[28]\); - - \p0.transdata.data_1_i_RNO_0[23]\ : OR3A - port map(A => \un1_acc[33]\, B => \walk_use\, C => - \data[23]\, Y => N_2985); - - \r.walk_transdata.data[21]\ : DFN1E0 - port map(D => N_687, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[21]\); - - \r.s2_entry_1_RNIG4VP[1]\ : MX2 - port map(A => N_761, B => N_795, S => \s2_entry_1[1]\, Y - => N_829); - - \r.s2_data_RNIRG6N1[31]\ : OR2A - port map(A => N_3061, B => \data_0[31]\, Y => N_2997); - - \r.walk_use_1_RNIVO2T2\ : OR3 - port map(A => N_554, B => walk_use_1, C => \adata[12]\, Y - => N_839); - - \r.s2_entry_1_RNIDVJF[1]\ : MX2 - port map(A => N_849, B => N_883, S => \s2_entry_1[1]\, Y - => N_917); - - \r.s2_entry_0_RNIO4FM1[0]\ : MX2 - port map(A => N_801, B => N_903, S => \s2_entry_0[0]\, Y - => adata_1); - - \r.walk_use_RNI6VBM1\ : OR2A - port map(A => N_3162, B => \walk_use\, Y => N_3064); - - \r.walk_fault.fault_pro_RNO_0\ : OR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => hrdata_0_2, Y => N_1637_i_i_0); - - \r.walk_transdata.data_RNIIR49[21]\ : OR2A - port map(A => \walk_use\, B => \data_0[21]\, Y => N_3021); - - \r.s2_entry_1_RNIT6FP[1]\ : MX2 - port map(A => N_834, B => N_868, S => \s2_entry_1[1]\, Y - => N_902); - - \r.s2_data_RNIV47N1[26]\ : OR2A - port map(A => N_3061, B => \data[26]\, Y => N_2990); - - \r.s2_entry_0_RNIRH7RQ2_11[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_0[3]\); - - \r.walk_transdata.data_RNO[29]\ : MX2 - port map(A => \data_0[29]\, B => N_78_0, S => \N_2571\, Y - => N_331); - - \r.s2_entry[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry[2]\); - - \r.walk_transdata.data_RNIFK3D[12]\ : OR2A - port map(A => walk_use_0, B => \data_0[12]\, Y => N_2662); - - \r.walk_transdata.data_RNIONB72[18]\ : MX2C - port map(A => N_1039, B => \data_0[18]\, S => walk_use_1, Y - => un1_m0_16); - - \r.s2_data[6]\ : DFN1E1 - port map(D => address(6), CLK => lclk_c, E => s1finished, Q - => \data[6]\); - - \r.s2_hm_RNI0V531\ : OR2A - port map(A => N_2355, B => N_556, Y => N_557); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.s2_data_RNI2B7Q1[18]\ : MX2 - port map(A => \adata[14]\, B => \data[18]\, S => - \un1_acc[33]\, Y => N_1039); - - \r.walk_transdata.data[7]\ : DFN1E0 - port map(D => \data[7]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[7]\); - - \r.s2_tlbstate_RNI0V531[1]\ : AO1D - port map(A => \s2_tlbstate[1]\, B => N_562, C => N_553, Y - => un11_finish_li); - - \r.s2_data_RNIIM9M5[25]\ : OR3C - port map(A => N_2673, B => N_2674, C => N_2675, Y => N_2626); - - \r.s2_entry_0_RNIBMCP[1]\ : MX2 - port map(A => N_733, B => N_767, S => \s2_entry_0[1]\, Y - => N_801); - - \r.s2_tlbstate_RNO[0]\ : AOI1B - port map(A => \s2_tlbstate_ns_0_0_1[0]\, B => N_2611, C => - rst, Y => \s2_tlbstate_nss[0]\); - - \r.s2_entry_RNI2PAJ1[0]\ : MX2 - port map(A => N_829, B => N_931, S => \s2_entry[0]\, Y => - adata_29); - - \r.walk_use_1_RNIBC0E2\ : OR3 - port map(A => N_554, B => walk_use_1, C => \adata[11]\, Y - => N_2983); - - \r.s2_hm_RNIQOF91\ : OAI1 - port map(A => N_553, B => N_2355, C => N_572, Y => - s1finished); - - \r.s2_entry_RNIM0TD[1]\ : MX2 - port map(A => N_764, B => N_798, S => \s2_entry[1]\, Y => - N_832); - - \r.s2_data[16]\ : DFN1E1 - port map(D => address(16), CLK => lclk_c, E => - \s1finished_0\, Q => \data[16]\); - - \r.walk_transdata.data_RNI6FPD[4]\ : MX2C - port map(A => \data[4]\, B => \data_0[4]\, S => walk_use_1, - Y => un1_m0_2); - - \r.walk_fault.fault_mexc_RNI66TQ31\ : NOR2 - port map(A => \fault_mexc_1\, B => fault_mexc_3_2, Y => - fault_mexc_3_0); - - \r.s2_entry_1_RNIFL3Q[1]\ : MX2 - port map(A => N_857, B => N_891, S => \s2_entry_1[1]\, Y - => N_925); - - \r.s2_entry_0_RNIB4O21[0]\ : MX2 - port map(A => N_810, B => N_912, S => \s2_entry_0[0]\, Y - => \adata[10]\); - - \r.walk_fault.fault_pro\ : DFN1E1 - port map(D => N_2559, CLK => lclk_c, E => N_198, Q => - fault_pro); - - \r.walk_fault.fault_lvl_RNI1M09[0]\ : NOR2B - port map(A => walk_use_0, B => \fault_lvl[0]\, Y => - un1_itlb0_1(41)); - - \r.walk_transdata.data[13]\ : DFN1E0 - port map(D => N_2622, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[13]\); - - \r.s2_entry_1_RNIPUJF[1]\ : MX2 - port map(A => N_844, B => N_878, S => \s2_entry_1[1]\, Y - => N_912); - - \r.s2_tlbstate[1]\ : DFN1 - port map(D => \s2_tlbstate_nss[1]\, CLK => lclk_c, Q => - \s2_tlbstate[1]\); - - \r.s2_entry_0_RNIDKDM1[0]\ : MX2 - port map(A => N_800, B => N_902, S => \s2_entry_0[0]\, Y - => adata_0); - - \r.walk_transdata.data[28]\ : DFN1E0 - port map(D => \data_1[28]\, CLK => lclk_c, E => N_6_i, Q - => \data[28]\); - - \p0.transdata.data_1_i_RNO[23]\ : AND2 - port map(A => N_2985, B => N_2984, Y => \data_1_i_0[23]\); - - \r.s2_su\ : DFN1E1 - port map(D => su, CLK => lclk_c, E => s1finished, Q => - \fault_su\); - - \r.s2_entry_5_RNIA2ARQ2_3[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => \tlbcam_write_op_1[2]\); - - \r.s2_data_RNI8V2E[28]\ : MX2C - port map(A => address(28), B => \data_0[28]\, S => s2_flush, - Y => N_651); - - \r.s2_data[18]\ : DFN1E1 - port map(D => address(18), CLK => lclk_c, E => - \s1finished_0\, Q => \data[18]\); - - \r.s2_entry_0_RNIRH7RQ2_1[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => - \tlbcam_write_op_1_1_0[6]\); - - \r.s2_data_RNI4R2E[18]\ : MX2C - port map(A => address(18), B => \data[18]\, S => s2_flush, - Y => N_617); - - \r.walk_transdata.data[11]\ : DFN1E0 - port map(D => \data[11]\, CLK => lclk_c, E => N_6_i_0, Q - => \data_0[11]\); - - \r.s2_entry_1_RNIKKVP[1]\ : MX2 - port map(A => N_762, B => N_796, S => \s2_entry_1[1]\, Y - => N_830); - - \r.walk_transdata.data_RNO[28]\ : MX2 - port map(A => \data_0[28]\, B => hrdata_0_23, S => \N_2571\, - Y => \data_1[28]\); - - \r.s2_entry_RNIAPR93[0]\ : OR2 - port map(A => \adata[25]\, B => N_3064, Y => N_2992); - - \r.s2_data[5]\ : DFN1E1 - port map(D => address(5), CLK => lclk_c, E => s1finished, Q - => \data[5]\); - - \r.walk_transdata.data[25]\ : DFN1E0 - port map(D => N_2729, CLK => lclk_c, E => N_6_i, Q => - \data_0[25]\); - - \r.s2_entry_RNISCSJ1_0[0]\ : OR2 - port map(A => \un1_acc[33]\, B => \un1_acc[32]\, Y => N_554); - - \r.s2_data_RNI2N2E[17]\ : MX2C - port map(A => address(17), B => \data[17]\, S => s2_flush, - Y => N_596); - - \r.s2_data_RNI097N1[27]\ : OR2A - port map(A => N_3061, B => \data[27]\, Y => N_2966); - - \tlbcam0.1.tag0\ : mmutlbcam_0_0_5 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0(7) => - hrdata_0_6, tlbcam_write_op_1(1) => - \tlbcam_write_op_1[1]\, tlbcam_write_op_1_1(1) => - \tlbcam_write_op_1_1[1]\, hrdata_4 => hrdata_4, hrdata_3 - => hrdata_3, hrdata_2 => hrdata_2, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_27 => hrdata_27, hrdata_26 - => hrdata_26, hrdata_24 => hrdata_24, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_17 => hrdata_17, hrdata_16 - => hrdata_16, hrdata_15 => hrdata_15, hrdata_14 => - hrdata_14, hrdata_13 => hrdata_13, hrdata_12 => hrdata_12, - hrdata_11 => hrdata_11, hrdata_10 => hrdata_10, hrdata_9 - => hrdata_9, hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, - hrdata_0_d0 => hrdata_0_d0, hrdata_6 => hrdata_6, - s2_entry(2) => \s2_entry[2]\, tlbcam_write_op_1_0(1) => - \tlbcam_write_op_1_0[1]\, s2_entry_5(2) => - \s2_entry_5[2]\, LVL_0(1) => \LVL_2[1]\, LVL_0(0) => - \LVL_2[0]\, s2_entry_4(2) => \s2_entry_4[2]\, - s2_entry_3(2) => \s2_entry_3[2]\, pteout_0_4 => - \pteout_2[4]\, pteout_0_17 => \pteout_2[17]\, pteout_0_18 - => \pteout_2[18]\, pteout_0_11 => \pteout_2[11]\, - pteout_0_31 => \pteout_2[31]\, pteout_0_30 => - \pteout_2[30]\, pteout_0_29 => \pteout_2[29]\, - pteout_0_28 => \pteout_2[28]\, pteout_0_27 => - \pteout_2[27]\, pteout_0_26 => \pteout_2[26]\, - pteout_0_25 => \pteout_2[25]\, pteout_0_24 => - \pteout_2[24]\, pteout_0_23 => \pteout_2[23]\, - pteout_0_22 => \pteout_2[22]\, pteout_0_21 => - \pteout_2[21]\, pteout_0_20 => \pteout_2[20]\, - pteout_0_19 => \pteout_2[19]\, pteout_0_16 => - \pteout_2[16]\, pteout_0_15 => \pteout_2[15]\, - pteout_0_14 => \pteout_2[14]\, pteout_0_13 => - \pteout_2[13]\, pteout_0_12 => \pteout_2[12]\, - pteout_0_10 => \pteout_2[10]\, pteout_0_9 => - \pteout_2[9]\, pteout_0_8 => \pteout_2[8]\, pteout_0_7 - => \pteout_2[7]\, pteout_0_6 => \pteout_2[6]\, - pteout_0_3 => \pteout_2[3]\, pteout_0_2 => \pteout_2[2]\, - pteout_0_1 => \pteout_2[1]\, pteout_0_0 => \pteout_2[0]\, - ctx_0(7) => ctx_0(7), ctx_0(6) => ctx_0(6), ctx_0(5) => - ctx_0(5), ctx_0(4) => ctx_0(4), ctx_0(3) => ctx_0(3), - ctx_0(2) => ctx_0(2), ctx_0(1) => ctx_0(1), ctx_0(0) => - ctx_0(0), s2_entry_1_i_a2_0(0) => \s2_entry_1_i_a2_0[0]\, - N_78 => N_78, N_262 => N_262, N_264 => N_264, N_2482 => - N_2482, lclk_c => lclk_c, N_838 => N_838, N_851 => N_851, - N_852 => N_852, N_845 => N_845, N_867 => N_867, s2_flush - => s2_flush, un1_rst_i_0 => un1_rst_i_0, N_200 => N_200, - N_42 => N_42, N_866 => N_866, N_596 => N_596, N_620 => - N_620, N_594 => N_594, N_593 => N_593, N_597 => N_597, - N_665 => N_665, N_651 => N_651, N_865 => N_865, N_864 => - N_864, N_863 => N_863, N_862 => N_862, N_861 => N_861, - N_860 => N_860, N_859 => N_859, N_858 => N_858, N_857 => - N_857, N_856 => N_856, N_855 => N_855, N_854 => N_854, - N_853 => N_853, N_850 => N_850, N_849 => N_849, N_848 => - N_848, N_847 => N_847, N_846 => N_846, N_844 => N_844, - N_843 => N_843, N_842 => N_842, N_841 => N_841, N_840 => - N_840, N_837 => N_837, N_836 => N_836, N_835 => N_835, - N_834 => N_834, N_634 => N_634, N_632 => N_632, N_662 => - N_662, N_650 => N_650, N_639 => N_639, N_635 => N_635, - hit_0_a3_0 => hit_0_a3_0, N_631_i => N_631_i, N_633 => - N_633, N_595 => N_595, N_663 => N_663, N_664 => N_664, - N_612 => N_612, N_200_0 => N_200_0, N_617 => N_617, N_204 - => N_204, N_170_1 => N_170_1, hit_i_0 => hit_i_0, N_557 - => N_557); - - \r.s2_entry_RNIQ0TD[1]\ : MX2 - port map(A => N_866, B => N_900, S => \s2_entry[1]\, Y => - N_934); - - \r.s2_entry_RNIB1UN[1]\ : MX2 - port map(A => N_865, B => N_899, S => \s2_entry[1]\, Y => - N_933); - - \r.walk_fault.fault_pro_RNI3LP74\ : MX2 - port map(A => N_1633, B => fault_pro, S => walk_use_1, Y - => N_2577); - - \r.s2_entry_1[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_1_0[2]\); - - \r.s2_entry_0_RNIRH7RQ2_0[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => - \tlbcam_write_op_1_1_0[5]\); - - \r.s2_data_RNIBF7Q1[19]\ : MX2 - port map(A => \adata[15]\, B => \data[19]\, S => - \un1_acc[33]\, Y => N_667); - - \r.s2_data_RNITT5R1[17]\ : OR3A - port map(A => N_554, B => walk_use_1, C => \data[17]\, Y - => N_3017); - - \r.s2_data[7]\ : DFN1E1 - port map(D => address(7), CLK => lclk_c, E => s1finished, Q - => \data[7]\); - - \r.s2_entry_1_RNI5VJF[1]\ : MX2 - port map(A => N_847, B => N_881, S => \s2_entry_1[1]\, Y - => N_915); - - \r.s2_entry_0_RNI4MBP[1]\ : MX2 - port map(A => N_732, B => N_766, S => \s2_entry_0[1]\, Y - => N_800); - - \r.walk_transdata.data_RNO[13]\ : MX2 - port map(A => hrdata_0_8, B => \data[13]\, S => N_3160, Y - => N_2622); - - \r.walk_transdata.data[27]\ : DFN1E0 - port map(D => N_2731, CLK => lclk_c, E => N_6_i, Q => - \data_0[27]\); - - \r.s2_data_RNI4R7E5[29]\ : OR3C - port map(A => N_2992, B => N_2993, C => N_2994, Y => N_363); - - \r.s2_data_RNI9B8E5[31]\ : OR3C - port map(A => N_2995, B => N_2996, C => N_2997, Y => N_365); - - \r.s2_entry_1_RNIHUJF[1]\ : MX2 - port map(A => N_842, B => N_876, S => \s2_entry_1[1]\, Y - => N_910); - - \r.s2_entry_0_RNIRH7RQ2_3[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_0[7]\); - - \r.walk_transdata.data_RNO[16]\ : MX2 - port map(A => hrdata_0_11, B => \data[16]\, S => N_3160, Y - => N_2727); - - \r.s2_ctx[5]\ : DFN1E1 - port map(D => ctx(5), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[5]\); - - dataram : syncramZ0 - port map(aaddr(31) => aaddr(31), aaddr(30) => aaddr(30), - aaddr(29) => aaddr(29), aaddr(28) => aaddr(28), aaddr(27) - => aaddr(27), aaddr(26) => aaddr(26), aaddr(25) => - aaddr(25), aaddr(24) => aaddr(24), aaddr(23) => aaddr(23), - aaddr(22) => aaddr(22), aaddr(21) => aaddr(21), aaddr(20) - => aaddr(20), aaddr(19) => aaddr(19), aaddr(18) => - aaddr(18), aaddr(17) => aaddr(17), aaddr(16) => aaddr(16), - aaddr(15) => aaddr(15), aaddr(14) => aaddr(14), aaddr(13) - => aaddr(13), aaddr(12) => aaddr(12), aaddr(11) => - aaddr(11), aaddr(10) => aaddr(10), aaddr(9) => aaddr(9), - aaddr(8) => aaddr(8), aaddr(7) => aaddr(7), aaddr(6) => - aaddr(6), aaddr(5) => aaddr(5), aaddr(4) => aaddr(4), - aaddr(3) => aaddr(3), aaddr(2) => aaddr(2), address(31) - => address_0(31), address(30) => address_0(30), - address(29) => address_0(29), address(28) => - address_0(28), address(27) => address_0(27), address(26) - => address_0(26), address(25) => address_0(25), - address(24) => address_0(24), address(23) => - address_0(23), address(22) => address_0(22), address(21) - => address_0(21), address(20) => address_0(20), - address(19) => address_0(19), address(18) => - address_0(18), address(17) => address_0(17), address(16) - => address_0(16), address(15) => address_0(15), - address(14) => address_0(14), address(13) => - address_0(13), address(12) => address_0(12), address(11) - => address_0(11), address(10) => address_0(10), - address(9) => address_0(9), address(8) => address_0(8), - address(7) => address_0(7), address(6) => address_0(6), - address(5) => address_0(5), address(4) => address_0(4), - address(3) => address_0(3), address(2) => address_0(2), - s2_entry(2) => \s2_entry[2]\, s2_entry(1) => - \s2_entry[1]\, s2_entry(0) => \s2_entry[0]\, - dr1write_0_sqmuxa => dr1write_0_sqmuxa, syncramZ0_VCC => - mmutlb_10_8_0_1_0_VCC, lclk_c => lclk_c); - - \r.s2_entry_RNITNJM[0]\ : MX2 - port map(A => N_833, B => N_935, S => \s2_entry[0]\, Y => - \un1_acc[33]\); - - \tlbcam0.7.tag0\ : mmutlbcam_0_0_3 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0_17 => - hrdata_0_23, hrdata_0_10 => hrdata_0_16, hrdata_0_7 => - hrdata_0_13, hrdata_0_6 => hrdata_0_12, hrdata_0_4 => - hrdata_0_10, hrdata_0_3 => hrdata_0_9, hrdata_0_2 => - hrdata_0_8, hrdata_0_0 => hrdata_0_6, - tlbcam_write_op_1(7) => \tlbcam_write_op_1[7]\, - tlbcam_write_op_1_1_0(7) => \tlbcam_write_op_1_1_0[7]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 - => hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => - hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 => - hrdata_0_d0, hrdata_6 => hrdata_6, pteout_4 => - \pteout_1[4]\, pteout_3 => \pteout_1[3]\, pteout_2 => - \pteout_1[2]\, pteout_31 => \pteout_1[31]\, pteout_30 => - \pteout_1[30]\, pteout_29 => \pteout_1[29]\, pteout_28 - => \pteout_1[28]\, pteout_27 => \pteout_1[27]\, - pteout_26 => \pteout_1[26]\, pteout_25 => \pteout_1[25]\, - pteout_24 => \pteout_1[24]\, pteout_23 => \pteout_1[23]\, - pteout_22 => \pteout_1[22]\, pteout_21 => \pteout_1[21]\, - pteout_20 => \pteout_1[20]\, pteout_19 => \pteout_1[19]\, - pteout_18 => \pteout_1[18]\, pteout_17 => \pteout_1[17]\, - pteout_16 => \pteout_1[16]\, pteout_15 => \pteout_1[15]\, - pteout_14 => \pteout_1[14]\, pteout_13 => \pteout_1[13]\, - pteout_12 => \pteout_1[12]\, pteout_11 => \pteout_1[11]\, - pteout_10 => \pteout_1[10]\, pteout_9 => \pteout_1[9]\, - pteout_8 => \pteout_1[8]\, pteout_1 => \pteout_1[1]\, - pteout_0 => \pteout_1[0]\, pteout_7 => \pteout_1[7]\, - pteout_6 => \pteout_1[6]\, tlbcam_write_op_1_0(7) => - \tlbcam_write_op_1_0[7]\, s2_entry_1_i_a2_1_2(1) => - \s2_entry_1_i_a2_1_2[1]\, ctx_0(7) => ctx_0(7), ctx_0(6) - => ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), - ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => - ctx_0(1), ctx_0(0) => ctx_0(0), LVL(1) => \LVL_1[1]\, - LVL(0) => \LVL_1[0]\, s2_entry_1_i_a2_0(0) => - \s2_entry_1_i_a2_0[0]\, s2_entry_1_i_a2_2(0) => - \s2_entry_1_i_a2_2[0]\, N_78_0 => N_78_0, N_262_0 => - N_262_0, N_264_0 => N_264_0, N_2482 => N_2482, lclk_c => - lclk_c, N_42 => N_42, N_200 => N_200, un1_rst_i_0 => - un1_rst_i_0, N_596 => N_596, N_620 => N_620, N_594 => - N_594, N_593 => N_593, N_597 => N_597, N_665 => N_665, - N_634 => N_634, N_632 => N_632, N_631_i => N_631_i, N_639 - => N_639, N_635 => N_635, s2_flush_0 => s2_flush_0, - hit_0_a3_0 => hit_0_a3_0, N_2937_1 => N_2937_1, N_170_1 - => N_170_1, N_633 => N_633, N_595 => N_595, N_663 => - N_663, N_664 => N_664, N_651 => N_651, N_612 => N_612, - N_200_0 => N_200_0, N_617 => N_617, N_650 => N_650, N_662 - => N_662, N_204 => N_204); - - \r.walk_transdata.data_RNIL44D[26]\ : OR2A - port map(A => walk_use_1, B => \data_0[26]\, Y => N_2989); - - \r.sync_isw_RNIO5LAF1\ : AO1D - port map(A => \twi_areq_ur_1_0_a3_i_0\, B => N_2563_i, C - => \walk_op_ur\, Y => N_180); - - \r.s2_entry_RNIE098[1]\ : MX2 - port map(A => N_838, B => N_872, S => \s2_entry[1]\, Y => - N_906); - - \r.s2_entry_5[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_5[2]\); - - \r.sync_isw_RNIB75G\ : OR2 - port map(A => sync_isw, B => N_2568, Y => - \twi_areq_ur_1_0_a3_i_0\); - - \r.s2_entry_4[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_4[2]\); - - \r.s2_tlbstate_RNI65SS[1]\ : AO1A - port map(A => s2_flush, B => N_562, C => \s2_tlbstate[1]\, - Y => N_2899); - - \r.s2_hm_RNIVT4D1\ : OR2A - port map(A => rst, B => \s1finished_0\, Y => un1_rst_2); - - \r.walk_use\ : DFN1E1 - port map(D => cache_0_sqmuxa_1_1, CLK => lclk_c, E => - s2_tlbstate_3, Q => \walk_use\); - - \r.s2_data_RNI9BAC3[24]\ : MX2 - port map(A => \data[24]\, B => \adata[20]\, S => N_3162, Y - => \data_0[24]\); - - \r.s2_data[2]\ : DFN1E1 - port map(D => address(2), CLK => lclk_c, E => s1finished, Q - => \data[2]\); - - \r.walk_transdata.data_RNO[20]\ : MX2 - port map(A => hrdata_0_15, B => \data[20]\, S => - lvl_i_1_0(1), Y => N_640); - - \r.walk_fault.fault_inv_RNO\ : NOR3A - port map(A => inv_1_0_a2_0_a2_0, B => hrdata_0_0, C => - N_2917, Y => N_18); - - \r.walk_transdata.data[4]\ : DFN1E0 - port map(D => \data[4]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[4]\); - - \r.s2_data_RNIPH5R1[14]\ : OR3A - port map(A => N_554, B => walk_use_0, C => \data_0[14]\, Y - => N_2667); - - \r.walk_use_0_RNIO6C55\ : OR2B - port map(A => \data_1_i_0[14]\, B => N_2669, Y => N_45); - - \r.s2_entry_0_RNIBGHN1[0]\ : MX2 - port map(A => N_819, B => N_921, S => \s2_entry_0[0]\, Y - => \adata[19]\); - - \r.walk_transdata.data[18]\ : DFN1E0 - port map(D => N_2890, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[18]\); - - \r.s2_entry_1_RNI0L1Q[1]\ : MX2 - port map(A => N_854, B => N_888, S => \s2_entry_1[1]\, Y - => N_922); - - \r.s2_tlbstate_RNICNFP3[1]\ : NOR3 - port map(A => \adata[3]\, B => un11_finish_li, C => N_2492, - Y => N_1633); - - \r.s2_entry_0_RNIQK0Q[1]\ : MX2 - port map(A => N_756, B => N_790, S => \s2_entry_0[1]\, Y - => N_824); - - \r.s2_data[20]\ : DFN1E1 - port map(D => address(20), CLK => lclk_c, E => s1finished, - Q => \data[20]\); - - \r.s2_entry_5_RNIA2ARQ2_1[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => \tlbcam_write_op_1[4]\); - - \r.walk_transdata.data[15]\ : DFN1E0 - port map(D => N_17, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[15]\); - - \r.s2_data_RNIEUB55[13]\ : OR3C - port map(A => N_2664, B => N_2665, C => N_2666, Y => N_2624); - - \r.s2_tlbstate_RNI6U6NN[1]\ : OR2B - port map(A => rst, B => N_6_i_0, Y => nrepe); - - \r.s2_data_RNISP5R1[16]\ : OR3A - port map(A => N_554, B => walk_use_1, C => \data[16]\, Y - => N_3014); - - \r.walk_transdata.data[26]\ : DFN1E0 - port map(D => N_2730, CLK => lclk_c, E => N_6_i, Q => - \data_0[26]\); - - \r.s2_data_RNIRDQC[22]\ : MX2C - port map(A => address(22), B => \data_0[22]\, S => - s2_flush_0, Y => N_662); - - \r.walk_transdata.data_RNIOG4D[29]\ : OR2A - port map(A => walk_use_1, B => \data[29]\, Y => N_2993); - - \r.walk_transdata.data[17]\ : DFN1E0 - port map(D => N_67, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[17]\); - - \r.s2_entry_0_RNI3CME[1]\ : MX2 - port map(A => N_735, B => N_769, S => \s2_entry_0[1]\, Y - => N_803); - - \r.walk_fault.fault_mexc\ : DFN1E1 - port map(D => N_16, CLK => lclk_c, E => N_175, Q => - fault_mexc); - - \r.s2_entry_RNIQCUB3[0]\ : OR2 - port map(A => \adata[23]\, B => N_3064, Y => N_2964); - - \r.s2_data_RNIO75I5[30]\ : OR3C - port map(A => N_2602, B => N_2603, C => N_2604, Y => N_43); - - \r.s2_data_RNI1QQC[25]\ : MX2C - port map(A => address(25), B => \data[25]\, S => s2_flush_0, - Y => N_635); - - \r.s2_entry_RNIKDIL1[0]\ : MX2 - port map(A => N_823, B => N_925, S => \s2_entry[0]\, Y => - \adata[23]\); - - \r.walk_transdata.data_RNIUIFL3[24]\ : MX2C - port map(A => \data_0[24]\, B => \data_1[24]\, S => - \walk_use\, Y => un1_m0_22); - - \r.s2_hm_RNIMNCD1\ : NOR2B - port map(A => \s1finished_0\, B => flush_op, Y => - s2_flush_1); - - \r.walk_use_0\ : DFN1E1 - port map(D => cache_0_sqmuxa_1_1, CLK => lclk_c, E => - s2_tlbstate_3, Q => walk_use_0); - - \r.walk_transdata.data[5]\ : DFN1E0 - port map(D => \data[5]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[5]\); - - \r.s2_entry_RNIAI39[1]\ : MX2 - port map(A => N_743, B => N_777, S => \s2_entry[1]\, Y => - N_811); - - \r.s2_data_RNI1D7N1[28]\ : OR2A - port map(A => N_3061, B => \data_0[28]\, Y => N_2970); - - \r.walk_transdata.data_RNO[12]\ : MX2 - port map(A => hrdata_0_7, B => \data[12]\, S => N_3160, Y - => N_2621); - - \r.walk_transdata.data[6]\ : DFN1E0 - port map(D => \data[6]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[6]\); - - \r.s2_entry_0_RNI2EHF[1]\ : MX2 - port map(A => N_741, B => N_775, S => \s2_entry_0[1]\, Y - => N_809); - - \r.sync_isw\ : DFN1 - port map(D => sync_isw_RNO, CLK => lclk_c, Q => sync_isw); - - \r.s2_tlbstate_RNO_1[0]\ : OR2A - port map(A => \s2_tlbstate_ns_0_0_a2_2_0[0]\, B => N_86_i, - Y => N_2611); - - \r.s2_entry_RNI6OFJ[1]\ : MX2 - port map(A => N_852, B => N_886, S => \s2_entry[1]\, Y => - N_920); - - \r.s2_tlbstate[0]\ : DFN1 - port map(D => \s2_tlbstate_nss[0]\, CLK => lclk_c, Q => - \s2_tlbstate[0]\); - - \r.s2_data_RNIPVC55[17]\ : OR3C - port map(A => N_3017, B => N_3019, C => N_3020, Y => N_425); - - \r.s2_entry_1_RNIPK0Q[1]\ : MX2 - port map(A => N_853, B => N_887, S => \s2_entry_1[1]\, Y - => N_921); - - \r.s2_data_RNIFU9G5[27]\ : OR3C - port map(A => N_2964, B => N_2965, C => N_2966, Y => N_319); - - \r.s2_entry_0_RNIU41Q[1]\ : MX2 - port map(A => N_757, B => N_791, S => \s2_entry_0[1]\, Y - => N_825); - - \r.s2_hm\ : DFN1E1 - port map(D => cam_hit_all_1, CLK => lclk_c, E => s1finished, - Q => s2_hm); - - \r.s2_entry_1_RNI1NFP[1]\ : MX2 - port map(A => N_835, B => N_869, S => \s2_entry_1[1]\, Y - => N_903); - - \r.walk_transdata.data[8]\ : DFN1E0 - port map(D => \data[8]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[8]\); - - \r.s2_entry_0_RNIIEHF[1]\ : MX2 - port map(A => N_745, B => N_779, S => \s2_entry_0[1]\, Y - => N_813); - - \r.walk_transdata.data_RNO[14]\ : MX2 - port map(A => hrdata_0_9, B => \data_0[14]\, S => N_3160, Y - => N_15); - - \r.s2_hm_RNIUVF7\ : OR2A - port map(A => s2_hm, B => tlbdis, Y => N_2355); - - \r.walk_fault.fault_pri_RNO\ : NOR3B - port map(A => N_556, B => N_2482, C => \fault_su\, Y => - N_206); - - \r.s2_entry_0_RNI2KTP[1]\ : MX2 - port map(A => N_750, B => N_784, S => \s2_entry_0[1]\, Y - => N_818); - - \r.walk_transdata.data_RNI25V9[10]\ : MX2C - port map(A => \data[10]\, B => \data_0[10]\, S => - \walk_use\, Y => un1_m0_8); - - \r.s2_tlbstate_RNIG6DGR2[1]\ : OR2A - port map(A => N_556, B => dr1write_0_sqmuxa, Y => N_198); - - \r.s2_entry_1_RNIS0PD[1]\ : MX2 - port map(A => N_841, B => C_RNIL004, S => \s2_entry_1[1]\, - Y => N_909); - - \r.nrep_RNO[0]\ : NOR2A - port map(A => rst, B => \nrep[0]\, Y => nrep_n0); - - \r.s2_hm_RNO_1\ : NOR3C - port map(A => cam_hit_all_1_0, B => SU_RNIAA5O8, C => N_170, - Y => cam_hit_all_1_2); - - \r.s2_entry_RNIVAT2_2[0]\ : OR2 - port map(A => \s2_entry[1]\, B => \s2_entry[0]\, Y => - \tlbcam_write_op_1_1[0]\); - - \r.s2_data_RNI52RC[27]\ : MX2C - port map(A => address(27), B => \data[27]\, S => s2_flush_0, - Y => N_639); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.walk_transdata.data_RNI20C72[19]\ : MX2C - port map(A => N_667, B => \data_0[19]\, S => walk_use_1, Y - => un1_m0_17); - - \r.walk_transdata.data_RNIIN49[30]\ : OR2A - port map(A => \walk_use\, B => \data_0[30]\, Y => N_2603); - - \r.s2_entry_2[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_2[2]\); - - \r.s2_data[10]\ : DFN1E1 - port map(D => address(10), CLK => lclk_c, E => - \s1finished_0\, Q => \data[10]\); - - \r.walk_transdata.data_RNO[30]\ : MX2 - port map(A => \data[30]\, B => hrdata_0_25, S => \N_2571\, - Y => N_2554); - - \r.s2_entry_0_RNIC01E3[0]\ : OR2 - port map(A => \adata[22]\, B => N_3064, Y => N_2988); - - \r.s2_data[29]\ : DFN1E1 - port map(D => address(29), CLK => lclk_c, E => s1finished, - Q => \data_0[29]\); - - \r.sync_isw_RNO\ : AO1B - port map(A => sync_isw_1_i_i_a2_0_0, B => dr1write_0_sqmuxa, - C => N_2593, Y => sync_isw_RNO); - - \tlbcam0.2.tag0\ : mmutlbcam_0_0_6 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1(2) => \tlbcam_write_op_1[2]\, - tlbcam_write_op_1_1(2) => \tlbcam_write_op_1_1[2]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_24 => - hrdata_24, hrdata_23 => hrdata_23, hrdata_22 => hrdata_22, - hrdata_21 => hrdata_21, hrdata_18 => hrdata_18, hrdata_17 - => hrdata_17, hrdata_16 => hrdata_16, hrdata_15 => - hrdata_15, hrdata_14 => hrdata_14, hrdata_13 => hrdata_13, - hrdata_12 => hrdata_12, hrdata_11 => hrdata_11, hrdata_10 - => hrdata_10, hrdata_9 => hrdata_9, hrdata_8 => hrdata_8, - hrdata_1 => hrdata_1, hrdata_0 => hrdata_0_d0, hrdata_7 - => hrdata_7, hrdata_6 => hrdata_6, s2_entry(2) => - \s2_entry[2]\, tlbcam_write_op_1_0(2) => - \tlbcam_write_op_1_0[2]\, LVL_0(1) => \LVL_0[1]\, - s2_entry_3(2) => \s2_entry_3[2]\, s2_entry_2(2) => - \s2_entry_2[2]\, s2_entry_1(2) => \s2_entry_1_0[2]\, - pteout_0_4 => \pteout_0[4]\, pteout_0_17 => - \pteout_0[17]\, pteout_0_11 => \pteout_0[11]\, - pteout_0_31 => \pteout_0[31]\, pteout_0_30 => - \pteout_0[30]\, pteout_0_29 => \pteout_0[29]\, - pteout_0_28 => \pteout_0[28]\, pteout_0_27 => - \pteout_0[27]\, pteout_0_26 => \pteout_0[26]\, - pteout_0_25 => \pteout_0[25]\, pteout_0_24 => - \pteout_0[24]\, pteout_0_23 => \pteout_0[23]\, - pteout_0_22 => \pteout_0[22]\, pteout_0_21 => - \pteout_0[21]\, pteout_0_20 => \pteout_0[20]\, - pteout_0_19 => \pteout_0[19]\, pteout_0_18 => - \pteout_0[18]\, pteout_0_16 => \pteout_0[16]\, - pteout_0_15 => \pteout_0[15]\, pteout_0_14 => - \pteout_0[14]\, pteout_0_13 => \pteout_0[13]\, - pteout_0_12 => \pteout_0[12]\, pteout_0_10 => - \pteout_0[10]\, pteout_0_9 => \pteout_0[9]\, pteout_0_8 - => \pteout_0[8]\, pteout_0_7 => \pteout_0[7]\, - pteout_0_6 => \pteout_0[6]\, pteout_0_3 => \pteout_0[3]\, - pteout_0_2 => \pteout_0[2]\, pteout_0_1 => \pteout_0[1]\, - pteout_0_0 => \pteout_0[0]\, ctx_0(7) => ctx_0(7), - ctx_0(6) => ctx_0(6), ctx_0(5) => ctx_0(5), ctx_0(4) => - ctx_0(4), ctx_0(3) => ctx_0(3), ctx_0(2) => ctx_0(2), - ctx_0(1) => ctx_0(1), ctx_0(0) => ctx_0(0), LVL_0_d0 => - \LVL_0[0]\, N_78 => N_78, N_262 => N_262, N_264 => N_264, - N_2482 => N_2482, lclk_c => lclk_c, N_770 => N_770, N_783 - => N_783, N_777 => N_777, s2_flush => s2_flush, - un1_rst_i_0 => un1_rst_i_0, N_631_i => N_631_i, N_632 => - N_632, N_634 => N_634, N_596 => N_596, N_42 => N_42, - N_200 => N_200, N_620 => N_620, N_594 => N_594, N_593 => - N_593, N_597 => N_597, N_665 => N_665, N_799 => N_799, - N_797 => N_797, N_796 => N_796, N_795 => N_795, N_794 => - N_794, N_793 => N_793, N_792 => N_792, N_791 => N_791, - N_790 => N_790, N_789 => N_789, N_788 => N_788, N_787 => - N_787, N_786 => N_786, N_785 => N_785, N_784 => N_784, - N_782 => N_782, N_781 => N_781, N_780 => N_780, N_779 => - N_779, N_778 => N_778, N_776 => N_776, N_775 => N_775, - N_774 => N_774, N_773 => N_773, N_772 => N_772, N_769 => - N_769, N_768 => N_768, N_767 => N_767, N_766 => N_766, - N_639 => N_639, N_635 => N_635, hit_0_a3_0 => hit_0_a3_0, - N_2937_1 => N_2937_1, N_557 => N_557, N_2937 => N_2937, - hit => hit, N_3068 => N_3068, N_170_1 => N_170_1, N_663 - => N_663, N_664 => N_664, N_651 => N_651, N_612 => N_612, - N_633 => N_633, N_595 => N_595, N_200_0 => N_200_0, N_617 - => N_617, N_650 => N_650, N_662 => N_662, N_204 => N_204); - - \r.walk_fault.fault_mexc_RNO\ : NOR2A - port map(A => fault_mexc_2, B => N_2917, Y => N_16); - - \r.s2_tlbstate_RNI1PHJN_1[1]\ : NOR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => N_2563_i, Y => \walk_op_ur\); - - \r.s2_entry_1[1]\ : DFN1E1 - port map(D => N_212_i_0, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_1[1]\); - - \r.nrep_RNIKI8IV4[1]\ : OA1 - port map(A => N_557, B => \nrep[1]\, C => N_2937, Y => - N_212_i_0); - - \r.walk_transdata.data_RNIMB59[25]\ : OR2A - port map(A => \walk_use\, B => \data_0[25]\, Y => N_2674); - - \r.walk_fault.fault_trans_RNI4QM59\ : NOR3C - port map(A => fault_inv_m, B => ft_1_i_a2_0(0), C => - fault_trans_m, Y => \N_1629\); - - \r.walk_transdata.data_RNO[17]\ : MX2 - port map(A => hrdata_0_12, B => \data[17]\, S => N_3160, Y - => N_67); - - \r.walk_transdata.data[22]\ : DFN1E0 - port map(D => N_688, CLK => lclk_c, E => N_6_i, Q => - \data[22]\); - - \r.s2_tlbstate_RNO_0[0]\ : OA1A - port map(A => \s2_tlbstate[0]\, B => N_2563_i, C => - \s2_tlbstate_ns_0_0_0[0]\, Y => \s2_tlbstate_ns_0_0_1[0]\); - - \r.nrep_RNO[1]\ : XA1 - port map(A => \nrep[1]\, B => \nrep[0]\, C => rst, Y => - nrep_n1); - - \r.walk_transdata.data[16]\ : DFN1E0 - port map(D => N_2727, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[16]\); - - \r.s2_tlbstate_RNIN377O[1]\ : AO1B - port map(A => cache_0_sqmuxa_1_1, B => N_2563_i, C => - \N_2933\, Y => s2_tlbstate_3); - - \r.s2_entry_RNIVGSN[1]\ : MX2 - port map(A => N_862, B => N_896, S => \s2_entry[1]\, Y => - N_930); - - \r.s2_entry_0_RNIUEHF[1]\ : MX2 - port map(A => N_748, B => N_782, S => \s2_entry_0[1]\, Y - => N_816); - - \r.s2_entry_0_RNI0G211[0]\ : MX2 - port map(A => N_802, B => N_904, S => \s2_entry_0[0]\, Y - => \adata[2]\); - - \r.s2_entry_1_RNIO40Q[1]\ : MX2 - port map(A => N_763, B => N_797, S => \s2_entry_1[1]\, Y - => N_831); - - \r.s2_entry_0_RNI6EHF[1]\ : MX2 - port map(A => N_742, B => N_776, S => \s2_entry_0[1]\, Y - => N_810); - - \r.walk_transdata.data[3]\ : DFN1E0 - port map(D => \data[3]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[3]\); - - \r.walk_transdata.data_RNIAE982[14]\ : OA1A - port map(A => walk_use_0, B => \data[14]\, C => N_2667, Y - => \data_1_i_0[14]\); - - \r.s2_entry_1_RNILCPE[1]\ : MX2 - port map(A => N_836, B => N_870, S => \s2_entry_1[1]\, Y - => N_904); - - \r.s2_data_RNIN95R1[12]\ : OR3A - port map(A => N_554, B => walk_use_0, C => \data[12]\, Y - => N_2661); - - \r.s2_data[9]\ : DFN1E1 - port map(D => address(9), CLK => lclk_c, E => s1finished, Q - => \data[9]\); - - \r.s2_entry_0_RNIEEHF[1]\ : MX2 - port map(A => N_744, B => N_778, S => \s2_entry_0[1]\, Y - => N_812); - - \r.walk_transdata.data_RNIS2B32[20]\ : MX2B - port map(A => N_630, B => \data_0[20]\, S => \walk_use\, Y - => N_2625); - - \r.walk_transdata.data_RNI2FPD[2]\ : MX2C - port map(A => \data[2]\, B => \data_0[2]\, S => walk_use_1, - Y => un1_m0_0); - - \r.walk_fault.fault_pro_RNIH439J\ : AO1B - port map(A => fault_isid_1_i(0), B => N_2577, C => - fault_pro_m, Y => fault_pro_1); - - \r.s2_tlbstate_RNIE7NKQ2[1]\ : NOR2 - port map(A => N_86_i, B => N_6_i_0, Y => dr1write_0_sqmuxa); - - \r.s2_entry_RNINVRE1[0]\ : MX2 - port map(A => N_818, B => N_920, S => \s2_entry[0]\, Y => - \adata[18]\); - - \r.walk_use_1_RNI7P2T2\ : OR3 - port map(A => N_554, B => walk_use_1, C => \adata[13]\, Y - => N_3020); - - \r.s2_tlbstate_RNO_3[0]\ : NOR3A - port map(A => \s2_tlbstate[0]\, B => \s2_tlbstate[1]\, C - => hrdata_5, Y => \s2_tlbstate_ns_0_0_a2_2_0[0]\); - - \r.s2_entry_0_RNI2L1Q[1]\ : MX2 - port map(A => N_758, B => N_792, S => \s2_entry_0[1]\, Y - => N_826); - - \r.s2_entry_0[1]\ : DFN1E1 - port map(D => N_212_i_0, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_0[1]\); - - \r.walk_fault.fault_trans_RNIM6E83\ : OR3C - port map(A => walk_use_0, B => fault_trans, C => - fault_isid_1_i(0), Y => fault_trans_m); - - \r.s2_entry_5_RNIA2ARQ2_4[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_5[2]\, C - => \tlbcam_write_op_1_1[5]\, Y => \tlbcam_write_op_1[1]\); - - \r.walk_transdata.data_RNIL84D[27]\ : OR2A - port map(A => walk_use_0, B => \data_0[27]\, Y => N_2965); - - \r.s2_tlbstate_RNI2VLR[1]\ : OR2A - port map(A => N_555, B => N_553, Y => N_556); - - \r.s2_entry_0_RNIM40Q[1]\ : MX2 - port map(A => N_755, B => N_789, S => \s2_entry_0[1]\, Y - => N_823); - - \r.walk_transdata.data_RNO[23]\ : MX2 - port map(A => N_264_0, B => \data[23]\, S => lvl_i_1_0(1), - Y => N_689); - - \r.s2_entry_0[0]\ : DFN1E1 - port map(D => N_208, CLK => lclk_c, E => s2_entry_0_sqmuxa, - Q => \s2_entry_0[0]\); - - \r.s2_data[19]\ : DFN1E1 - port map(D => address(19), CLK => lclk_c, E => - \s1finished_0\, Q => \data[19]\); - - \r.s2_entry_1_RNI9VJF[1]\ : MX2 - port map(A => N_848, B => N_882, S => \s2_entry_1[1]\, Y - => N_916); - - \r.s2_data_RNIRL5R1[25]\ : OR3 - port map(A => walk_use_0, B => \data[25]\, C => N_3162, Y - => N_2675); - - \r.s2_data_RNIN15R1[30]\ : OR3 - port map(A => walk_use_0, B => \data[30]\, C => N_3162, Y - => N_2604); - - \r.walk_use_RNI7A3P\ : OR2 - port map(A => \un1_acc[33]\, B => \walk_use\, Y => N_3069); - - \r.walk_transdata.data[29]\ : DFN1E0 - port map(D => N_331, CLK => lclk_c, E => N_6_i, Q => - \data[29]\); - - \r.s2_entry_RNIAPBJ1[0]\ : MX2 - port map(A => N_830, B => N_932, S => \s2_entry[0]\, Y => - adata_30); - - \r.s2_entry_3[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_3[2]\); - - \r.walk_transdata.data_RNO[21]\ : MX2 - port map(A => hrdata_0_16, B => \data[21]\, S => - lvl_i_1_0(1), Y => N_687); - - \r.walk_transdata.data[12]\ : DFN1E0 - port map(D => N_2621, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[12]\); - - \r.walk_fault.fault_pri_RNIN58G6\ : OAI1 - port map(A => fault_pri_6_m, B => fault_pri_m, C => - fault_isid_1_i(0), Y => fault_pri_m_0); - - \r.walk_transdata.data_RNO[26]\ : MX2 - port map(A => \data[26]\, B => hrdata_0_21, S => \N_2571\, - Y => N_2730); - - \r.walk_fault.fault_mexc_RNO_0\ : AO1A - port map(A => fault_mexc_1_sqmuxa_1_0_i_i_a2_0, B => - N_2563_i, C => N_573, Y => N_175); - - \r.s2_entry_RNISPEJ1[0]\ : MX2 - port map(A => N_824, B => N_926, S => \s2_entry[0]\, Y => - \adata[24]\); - - \r.s2_entry_RNISCSJ1[0]\ : OR2B - port map(A => \un1_acc[33]\, B => \un1_acc[32]\, Y => - N_3162); - - \r.s2_data_RNIRRTP[21]\ : OR3A - port map(A => \un1_acc[33]\, B => \walk_use\, C => - \data[21]\, Y => N_3022); - - \r.s2_data[4]\ : DFN1E1 - port map(D => address(4), CLK => lclk_c, E => s1finished, Q - => \data[4]\); - - \r.s2_data_RNIOD5R1[13]\ : OR3A - port map(A => N_554, B => walk_use_0, C => \data[13]\, Y - => N_2664); - - \r.s2_data[21]\ : DFN1E1 - port map(D => address(21), CLK => lclk_c, E => s1finished, - Q => \data[21]\); - - \r.sync_isw_RNO_0\ : NOR2A - port map(A => rst, B => hrdata_5, Y => - sync_isw_1_i_i_a2_0_0); - - \r.s2_entry_RNIIPCJ1[0]\ : MX2 - port map(A => N_831, B => N_933, S => \s2_entry[0]\, Y => - adata_31); - - \r.s2_data_RNIUA2E[23]\ : MX2C - port map(A => address(23), B => \data[23]\, S => s2_flush, - Y => N_620); - - \r.walk_use_0_RNIEO2T2\ : OR3 - port map(A => N_554, B => walk_use_0, C => \adata[10]\, Y - => N_2669); - - \r.s2_entry_0_RNIR5O21[0]\ : MX2 - port map(A => N_816, B => N_918, S => \s2_entry_0[0]\, Y - => \adata[16]\); - - \r.s2_data[24]\ : DFN1E1 - port map(D => address(24), CLK => lclk_c, E => s1finished, - Q => \data[24]\); - - \r.walk_fault.fault_inv_RNITG2F3\ : OR3C - port map(A => walk_use_0, B => fault_inv, C => - fault_isid_1_i(0), Y => fault_inv_m); - - \r.s2_tlbstate_RNI1PHJN_0[1]\ : OR3B - port map(A => \s2_tlbstate[0]\, B => N_2563_i, C => - \s2_tlbstate[1]\, Y => N_6_i_0); - - \r.s2_entry_0_RNIVBME[1]\ : MX2 - port map(A => N_734, B => N_768, S => \s2_entry_0[1]\, Y - => N_802); - - \r.s2_data_RNIBB6Q1[20]\ : MX2C - port map(A => \adata[16]\, B => \data[20]\, S => - \un1_acc[33]\, Y => N_630); - - \r.s2_ctx[3]\ : DFN1E1 - port map(D => ctx(3), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[3]\); - - \r.s2_entry_0_RNI35O21[0]\ : MX2 - port map(A => N_813, B => N_915, S => \s2_entry_0[0]\, Y - => \adata[13]\); - - \r.walk_transdata.data_RNI8FPD[5]\ : MX2C - port map(A => \data[5]\, B => \data_0[5]\, S => walk_use_1, - Y => un1_m0_3); - - \r.s2_entry_0_RNIRH7RQ2_7[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[7]\, Y => - \tlbcam_write_op_1_1[3]\); - - \r.s2_entry_0_RNIR3O21[0]\ : MX2 - port map(A => N_808, B => N_910, S => \s2_entry_0[0]\, Y - => \adata[8]\); - - \r.s2_entry_RNI74DA[1]\ : MX2 - port map(A => N_736, B => N_770, S => \s2_entry[1]\, Y => - N_804); - - \r.s2_data_RNI0ACI5[26]\ : OR3C - port map(A => N_2988, B => N_2989, C => N_2990, Y => N_361); - - \tlbcam0.3.tag0\ : mmutlbcam_0_0_7 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), - tlbcam_write_op_1(3) => \tlbcam_write_op_1[3]\, - tlbcam_write_op_1_1(3) => \tlbcam_write_op_1_1[3]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_24 => - hrdata_24, hrdata_23 => hrdata_23, hrdata_22 => hrdata_22, - hrdata_21 => hrdata_21, hrdata_18 => hrdata_18, hrdata_17 - => hrdata_17, hrdata_16 => hrdata_16, hrdata_15 => - hrdata_15, hrdata_14 => hrdata_14, hrdata_13 => hrdata_13, - hrdata_12 => hrdata_12, hrdata_11 => hrdata_11, hrdata_10 - => hrdata_10, hrdata_9 => hrdata_9, hrdata_8 => hrdata_8, - hrdata_1 => hrdata_1, hrdata_0 => hrdata_0_d0, hrdata_7 - => hrdata_7, hrdata_6 => hrdata_6, s2_entry(2) => - \s2_entry[2]\, tlbcam_write_op_1_0(3) => - \tlbcam_write_op_1_0[3]\, LVL_0(1) => \LVL_1[1]\, - LVL_0(0) => \LVL_1[0]\, s2_entry_5(2) => \s2_entry_5[2]\, - s2_entry_4(2) => \s2_entry_4[2]\, pteout_0_7 => - \pteout_1[7]\, pteout_0_4 => \pteout_1[4]\, pteout_0_17 - => \pteout_1[17]\, pteout_0_18 => \pteout_1[18]\, - pteout_0_11 => \pteout_1[11]\, pteout_0_31 => - \pteout_1[31]\, pteout_0_30 => \pteout_1[30]\, - pteout_0_29 => \pteout_1[29]\, pteout_0_28 => - \pteout_1[28]\, pteout_0_27 => \pteout_1[27]\, - pteout_0_26 => \pteout_1[26]\, pteout_0_25 => - \pteout_1[25]\, pteout_0_24 => \pteout_1[24]\, - pteout_0_23 => \pteout_1[23]\, pteout_0_22 => - \pteout_1[22]\, pteout_0_21 => \pteout_1[21]\, - pteout_0_20 => \pteout_1[20]\, pteout_0_19 => - \pteout_1[19]\, pteout_0_16 => \pteout_1[16]\, - pteout_0_15 => \pteout_1[15]\, pteout_0_14 => - \pteout_1[14]\, pteout_0_13 => \pteout_1[13]\, - pteout_0_12 => \pteout_1[12]\, pteout_0_10 => - \pteout_1[10]\, pteout_0_9 => \pteout_1[9]\, pteout_0_8 - => \pteout_1[8]\, pteout_0_6 => \pteout_1[6]\, - pteout_0_3 => \pteout_1[3]\, pteout_0_2 => \pteout_1[2]\, - pteout_0_1 => \pteout_1[1]\, pteout_0_0 => \pteout_1[0]\, - ctx(6) => ctx(6), ctx_0_5 => ctx_0(5), ctx_0_4 => - ctx_0(4), ctx_0_3 => ctx_0(3), ctx_0_1 => ctx_0(1), - ctx_0_0 => ctx_0(0), ctx_0_2 => ctx_0(2), ctx_0_7 => - ctx_0(7), N_78 => N_78, N_262 => N_262, N_264 => N_264, - N_2482 => N_2482, lclk_c => lclk_c, C_RNIL004 => - C_RNIL004, N_872 => N_872, N_885 => N_885, N_886 => N_886, - N_879 => N_879, N_901 => N_901, s2_flush => s2_flush, - un1_rst_i_0 => un1_rst_i_0, N_900 => N_900, N_200 => - N_200, N_596 => N_596, N_594 => N_594, N_593 => N_593, - N_597 => N_597, N_665 => N_665, N_899 => N_899, N_898 => - N_898, N_897 => N_897, N_896 => N_896, N_895 => N_895, - N_894 => N_894, N_893 => N_893, N_892 => N_892, N_891 => - N_891, N_890 => N_890, N_889 => N_889, N_888 => N_888, - N_887 => N_887, N_884 => N_884, N_883 => N_883, N_882 => - N_882, N_881 => N_881, N_880 => N_880, N_878 => N_878, - N_877 => N_877, N_876 => N_876, N_874 => N_874, N_871 => - N_871, N_870 => N_870, N_869 => N_869, N_868 => N_868, - N_634 => N_634, N_632 => N_632, N_662 => N_662, N_639 => - N_639, N_635 => N_635, hit_0_a3_0 => hit_0_a3_0, N_204 - => N_204, N_42 => N_42, hit => hit, N_631_i => N_631_i, - N_633 => N_633, N_595 => N_595, N_663 => N_663, N_664 => - N_664, N_651 => N_651, N_612 => N_612, N_200_0 => N_200_0, - N_617 => N_617, N_650 => N_650, N_620 => N_620, N_170_1 - => N_170_1); - - \r.s2_tlbstate_RNIE7NKQ2_0[1]\ : NOR2 - port map(A => N_86_i, B => N_6_i_0, Y => - dr1write_0_sqmuxa_0); - - \r.s2_tlbstate_RNI1OCD[1]\ : NOR2A - port map(A => tlbactive, B => \s2_tlbstate[1]\, Y => N_555); - - \r.s2_entry_1_RNI8L2Q[1]\ : MX2 - port map(A => N_856, B => N_890, S => \s2_entry_1[1]\, Y - => N_924); - - \r.s2_entry_0[2]\ : DFN1E1 - port map(D => \s2_entry_1[2]\, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry_0[2]\); - - \r.s2_data_RNIP2AM4[15]\ : OR3C - port map(A => N_2981, B => N_2982, C => N_2983, Y => N_357); - - \r.s2_ctx[7]\ : DFN1E1 - port map(D => ctx(7), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[7]\); - - \r.s2_data_RNIN9QC[12]\ : MX2C - port map(A => address(12), B => \data[12]\, S => s2_flush_0, - Y => N_631_i); - - \r.s2_ctx[2]\ : DFN1E1 - port map(D => ctx(2), CLK => lclk_c, E => \s1finished_0\, Q - => \s2_ctx[2]\); - - \r.nrep_RNO[2]\ : XA1A - port map(A => \nrep[2]\, B => nrep_494_0, C => rst, Y => - nrep_n2); - - \r.s2_tlbstate_RNISOV11[0]\ : OR2B - port map(A => N_572, B => N_553, Y => s2_entry_0_sqmuxa); - - \r.walk_fault.fault_mexc_RNI5S7A3\ : OR3C - port map(A => walk_use_0, B => fault_mexc, C => - fault_isid_1_i(0), Y => fault_mexc_m); - - \r.s2_entry_0_RNIU0KN1[0]\ : MX2 - port map(A => N_821, B => N_923, S => \s2_entry_0[0]\, Y - => \adata[21]\); - - \r.s2_entry_0_RNIJ5O21[0]\ : MX2 - port map(A => N_815, B => N_917, S => \s2_entry_0[0]\, Y - => \adata[15]\); - - \tlbcam0.6.tag0\ : mmutlbcam_0_0_1 - port map(s2_ctx(7) => \s2_ctx[7]\, s2_ctx(6) => \s2_ctx[6]\, - s2_ctx(5) => \s2_ctx[5]\, s2_ctx(4) => \s2_ctx[4]\, - s2_ctx(3) => \s2_ctx[3]\, s2_ctx(2) => \s2_ctx[2]\, - s2_ctx(1) => \s2_ctx[1]\, s2_ctx(0) => \s2_ctx[0]\, - data(31) => \data_0[31]\, data(30) => \data[30]\, - data(29) => \data_0[29]\, data(28) => \data_0[28]\, - data(27) => \data[27]\, data(26) => \data[26]\, data(25) - => \data[25]\, data(24) => \data[24]\, data(23) => - \data[23]\, data(22) => \data_0[22]\, data(21) => - \data[21]\, data(20) => \data[20]\, data(19) => - \data[19]\, data(18) => \data[18]\, data(17) => - \data[17]\, data(16) => \data[16]\, data(15) => - \data[15]\, data(14) => \data_0[14]\, data(13) => - \data[13]\, data(12) => \data[12]\, lvl_i_1(1) => - lvl_i_1(1), lvl_i_1(0) => lvl_i_1(0), hrdata_0_17 => - hrdata_0_23, hrdata_0_10 => hrdata_0_16, hrdata_0_7 => - hrdata_0_13, hrdata_0_6 => hrdata_0_12, hrdata_0_4 => - hrdata_0_10, hrdata_0_3 => hrdata_0_9, hrdata_0_2 => - hrdata_0_8, hrdata_0_0 => hrdata_0_6, - tlbcam_write_op_1(6) => \tlbcam_write_op_1[6]\, - tlbcam_write_op_1_1_0(6) => \tlbcam_write_op_1_1_0[6]\, - hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, hrdata_2 => - hrdata_2, hrdata_31 => hrdata_31, hrdata_30 => hrdata_30, - hrdata_29 => hrdata_29, hrdata_28 => hrdata_28, hrdata_27 - => hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => - hrdata_23, hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, - hrdata_18 => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 - => hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => - hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 => - hrdata_0_d0, hrdata_6 => hrdata_6, pteout_4 => - \pteout_0[4]\, pteout_3 => \pteout_0[3]\, pteout_2 => - \pteout_0[2]\, pteout_31 => \pteout_0[31]\, pteout_30 => - \pteout_0[30]\, pteout_29 => \pteout_0[29]\, pteout_28 - => \pteout_0[28]\, pteout_27 => \pteout_0[27]\, - pteout_26 => \pteout_0[26]\, pteout_25 => \pteout_0[25]\, - pteout_24 => \pteout_0[24]\, pteout_23 => \pteout_0[23]\, - pteout_22 => \pteout_0[22]\, pteout_21 => \pteout_0[21]\, - pteout_20 => \pteout_0[20]\, pteout_19 => \pteout_0[19]\, - pteout_18 => \pteout_0[18]\, pteout_17 => \pteout_0[17]\, - pteout_16 => \pteout_0[16]\, pteout_15 => \pteout_0[15]\, - pteout_14 => \pteout_0[14]\, pteout_13 => \pteout_0[13]\, - pteout_12 => \pteout_0[12]\, pteout_11 => \pteout_0[11]\, - pteout_10 => \pteout_0[10]\, pteout_9 => \pteout_0[9]\, - pteout_8 => \pteout_0[8]\, pteout_1 => \pteout_0[1]\, - pteout_0 => \pteout_0[0]\, pteout_7 => \pteout_0[7]\, - pteout_6 => \pteout_0[6]\, s2_entry_5(2) => - \s2_entry_5[2]\, LVL_0(0) => \LVL_0[0]\, - tlbcam_write_op_1_0(6) => \tlbcam_write_op_1_0[6]\, - ctx_0(7) => ctx_0(7), ctx_0(6) => ctx_0(6), ctx_0(5) => - ctx_0(5), ctx_0(4) => ctx_0(4), ctx_0(3) => ctx_0(3), - ctx_0(2) => ctx_0(2), ctx_0(1) => ctx_0(1), ctx_0(0) => - ctx_0(0), LVL_1 => \LVL_0[1]\, s2_entry_1_i_a2_1_2(1) => - \s2_entry_1_i_a2_1_2[1]\, N_78_0 => N_78_0, N_262_0 => - N_262_0, N_264_0 => N_264_0, N_2482 => N_2482, lclk_c => - lclk_c, N_635 => N_635, N_639 => N_639, N_665 => N_665, - N_597 => N_597, N_798 => N_798, N_632 => N_632, N_634 => - N_634, N_596 => N_596, un1_rst_i_0 => un1_rst_i_0, N_620 - => N_620, N_594 => N_594, N_593 => N_593, s2_flush_0 => - s2_flush_0, hit_0_a3_0 => hit_0_a3_0, N_42 => N_42, N_200 - => N_200, N_204 => N_204, N_631_i => N_631_i, N_633 => - N_633, N_595 => N_595, N_663 => N_663, N_664 => N_664, - N_651 => N_651, N_612 => N_612, N_200_0 => N_200_0, N_617 - => N_617, N_650 => N_650, N_662 => N_662, N_170_1 => - N_170_1); - - \r.s2_hm_RNO_0\ : NOR3C - port map(A => hit_i_0, B => cam_hit_all_1_2, C => hit_i, Y - => cam_hit_all_1_4); - - \r.s2_entry_RNIVK8T[0]\ : MX2 - port map(A => N_832, B => N_934, S => \s2_entry[0]\, Y => - \un1_acc[32]\); - - \r.walk_fault.fault_trans_RNIA0K0D1\ : OR2B - port map(A => fault_mexc_3_0, B => \N_1629\, Y => - fault_trans_RNIA0K0D1); - - \r.s2_entry_RNI8CLB[1]\ : MX2 - port map(A => N_765, B => N_799, S => \s2_entry[1]\, Y => - N_833); - - \r.walk_fault.fault_pri\ : DFN1E1 - port map(D => N_206, CLK => lclk_c, E => N_198, Q => - fault_pri); - - \r.s2_data_RNIRL5R1[15]\ : OR3A - port map(A => N_554, B => walk_use_1, C => \data[15]\, Y - => N_2981); - - \r.s2_flush_0\ : DFN1E1 - port map(D => s2_flush_1, CLK => lclk_c, E => un1_rst_2, Q - => s2_flush_0); - - \r.s2_data_RNIFO9D[8]\ : OR2B - port map(A => \data[8]\, B => s2_flush_0, Y => N_200_0); - - \r.walk_transdata.data[19]\ : DFN1E0 - port map(D => N_636, CLK => lclk_c, E => N_6_i_0, Q => - \data_0[19]\); - - \r.s2_entry_RNICQGJ1[0]\ : MX2 - port map(A => N_826, B => N_928, S => \s2_entry[0]\, Y => - \adata[26]\); - - \r.s2_entry_0_RNIRH7RQ2_9[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => - \tlbcam_write_op_1_1[2]\); - - \r.s2_data_RNIS22E[30]\ : MX2C - port map(A => address(30), B => \data[30]\, S => s2_flush, - Y => N_612); - - \r.walk_transdata.data_RNO[22]\ : MX2 - port map(A => hrdata_0_17, B => \data_0[22]\, S => - lvl_i_1_0(1), Y => N_688); - - \r.s2_data[8]\ : DFN1E1 - port map(D => address(8), CLK => lclk_c, E => s1finished, Q - => \data[8]\); - - \r.walk_transdata.data_RNI6QQ9[3]\ : MX2C - port map(A => \data[3]\, B => \data_0[3]\, S => \walk_use\, - Y => un1_m0_1); - - \r.s2_entry_0_RNIQEHF[1]\ : MX2 - port map(A => N_747, B => N_781, S => \s2_entry_0[1]\, Y - => N_815); - - \r.s2_entry_0_RNIG3E31[0]\ : MX2 - port map(A => N_806, B => N_908, S => \s2_entry_0[0]\, Y - => adata_6); - - \r.walk_transdata.data_RNI4DV9[11]\ : MX2C - port map(A => \data[11]\, B => \data_0[11]\, S => - \walk_use\, Y => un1_m0_9); - - \r.walk_fault.fault_lvl[1]\ : DFN1E0 - port map(D => N_82, CLK => lclk_c, E => N_6_i_0, Q => - fault_lvl_1); - - \r.walk_transdata.data[2]\ : DFN1E0 - port map(D => \data[2]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[2]\); - - \r.s2_data[11]\ : DFN1E1 - port map(D => address(11), CLK => lclk_c, E => - \s1finished_0\, Q => \data[11]\); - - \r.s2_entry_RNIT9U93[0]\ : OR2 - port map(A => \adata[27]\, B => N_3064, Y => N_2995); - - \r.s2_entry_0_RNIE4VP[1]\ : MX2 - port map(A => N_753, B => N_787, S => \s2_entry_0[1]\, Y - => N_821); - - \r.s2_data_RNI2H7N1[29]\ : OR2A - port map(A => N_3061, B => \data_0[29]\, Y => N_2994); - - \r.s2_data[14]\ : DFN1E1 - port map(D => address(14), CLK => lclk_c, E => - \s1finished_0\, Q => \data_0[14]\); - - \r.s2_data_RNIGHHE[8]\ : OR2B - port map(A => \data[8]\, B => s2_flush, Y => N_200); - - \r.s2_entry_RNIN10O[1]\ : MX2 - port map(A => N_859, B => N_893, S => \s2_entry[1]\, Y => - N_927); - - \r.nrep_RNITQLUT4[2]\ : MX2 - port map(A => \nrep[2]\, B => \cam_hitaddr_12[2]\, S => - N_557, Y => \s2_entry_1[2]\); - - \r.walk_transdata.data_RNO[31]\ : MX2 - port map(A => \data_0[31]\, B => hrdata_0_26, S => \N_2571\, - Y => N_70); - - \r.walk_transdata.data_RNO[15]\ : MX2 - port map(A => hrdata_0_10, B => \data[15]\, S => N_3160, Y - => N_17); - - \r.walk_transdata.data_RNO[24]\ : MX2 - port map(A => \data[24]\, B => N_262_0, S => \N_2571\, Y - => N_2728); - - \r.s2_data[30]\ : DFN1E1 - port map(D => address(30), CLK => lclk_c, E => s1finished, - Q => \data[30]\); - - \r.s2_su_RNIEO413\ : NOR3C - port map(A => \adata[3]\, B => fault_pri_6_m_1, C => - \adata[4]\, Y => fault_pri_6_m); - - \p0.transdata.data_1_i[23]\ : NAND2 - port map(A => N_2987, B => \data_1_i_0[23]\, Y => N_359); - - \r.s2_entry_1_RNICKUP[1]\ : MX2 - port map(A => N_760, B => N_794, S => \s2_entry_1[1]\, Y - => N_828); - - \r.s2_entry_1_RNILUJF[1]\ : MX2 - port map(A => N_843, B => N_877, S => \s2_entry_1[1]\, Y - => N_911); - - \r.s2_tlbstate_RNILJJC_1[1]\ : NOR2 - port map(A => \s2_tlbstate[1]\, B => \s2_tlbstate[0]\, Y - => N_2917); - - \r.walk_use_RNI6VBM1_0\ : NOR2 - port map(A => \walk_use\, B => N_3162, Y => N_3061); - - \r.s2_entry_0_RNIVM7B[1]\ : MX2 - port map(A => N_749, B => N_783, S => \s2_entry_0[1]\, Y - => N_817); - - \r.s2_entry_0_RNIRH7RQ2_10[2]\ : NOR3A - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[0]\, Y => - \tlbcam_write_op_1_1_0[0]\); - - \r.s2_entry[1]\ : DFN1E1 - port map(D => N_212_i_0, CLK => lclk_c, E => - s2_entry_0_sqmuxa, Q => \s2_entry[1]\); - - \r.s2_data_RNIN5QC[20]\ : MX2C - port map(A => address(20), B => \data[20]\, S => s2_flush_0, - Y => N_650); - - \r.s2_data_RNI4MB55[12]\ : OR3C - port map(A => N_2661, B => N_2662, C => N_2663, Y => N_2623); - - \r.s2_entry_0_RNIRH7RQ2_5[2]\ : NOR3B - port map(A => dr1write_0_sqmuxa_0, B => \s2_entry_0[2]\, C - => \tlbcam_write_op_1_1[6]\, Y => - \tlbcam_write_op_1_0[6]\); - - \r.s2_data[23]\ : DFN1E1 - port map(D => address(23), CLK => lclk_c, E => s1finished, - Q => \data[23]\); - - \r.walk_transdata.data_RNINC4D[28]\ : OR2A - port map(A => walk_use_1, B => \data[28]\, Y => N_2969); - - \r.nrep[1]\ : DFN1E1 - port map(D => nrep_n1, CLK => lclk_c, E => nrepe, Q => - \nrep[1]\); - - \r.s2_entry_RNIJHVN[1]\ : MX2 - port map(A => N_858, B => N_892, S => \s2_entry[1]\, Y => - N_926); - - \r.walk_transdata.data_RNO[27]\ : MX2 - port map(A => \data[27]\, B => hrdata_0_22, S => \N_2571\, - Y => N_2731); - - \r.s2_data[27]\ : DFN1E1 - port map(D => address(27), CLK => lclk_c, E => s1finished, - Q => \data[27]\); - - \r.walk_transdata.data[9]\ : DFN1E0 - port map(D => \data[9]\, CLK => lclk_c, E => N_6_i, Q => - \data_0[9]\); - - \r.walk_transdata.data[30]\ : DFN1E0 - port map(D => N_2554, CLK => lclk_c, E => N_6_i, Q => - \data_0[30]\); - - \r.s2_entry_RNI6J39[1]\ : MX2 - port map(A => N_851, B => N_885, S => \s2_entry[1]\, Y => - N_919); - - \r.s2_entry_RNI31TN[1]\ : MX2 - port map(A => N_863, B => N_897, S => \s2_entry[1]\, Y => - N_931); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu is - - port( ctxp : in std_logic_vector(25 downto 0); - iosn_0 : in std_logic_vector(93 to 93); - data_0 : out std_logic; - data_1_d0 : out std_logic; - data_2_d0 : out std_logic; - data_3 : out std_logic; - data_4 : out std_logic; - data_6 : out std_logic; - data_7 : out std_logic; - data_8 : out std_logic; - data_9 : out std_logic; - data_10 : out std_logic; - data_11 : out std_logic; - data_2 : out std_logic_vector(31 downto 12); - data_RNIKU1T4 : out std_logic_vector(16 to 16); - maddress : in std_logic_vector(31 downto 12); - data_1 : in std_logic_vector(31 downto 12); - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - data_1_3_i_a3_6_2 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_0 : out std_logic; - hrdata_5 : in std_logic; - hrdata_7 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_6 : in std_logic; - hrdata_24 : in std_logic; - hrdata_17 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_7 : in std_logic; - address_0 : in std_logic_vector(31 downto 2); - un1_m0_2_d0 : out std_logic; - un1_m0_3 : out std_logic; - un1_m0_4 : out std_logic; - un1_m0_7 : out std_logic; - un1_m0_16 : out std_logic; - un1_m0_17 : out std_logic; - un1_m0_0 : out std_logic; - un1_m0_6 : out std_logic; - un1_m0_22 : out std_logic; - un1_m0_1 : out std_logic; - un1_m0_5 : out std_logic; - un1_m0_8 : out std_logic; - un1_m0_9 : out std_logic; - un1_m0_30 : out std_logic; - ctx : in std_logic_vector(7 downto 0); - ctx_0 : in std_logic_vector(7 downto 0); - address : out std_logic_vector(31 downto 2); - hrdata_1_0_1 : in std_logic_vector(1 to 1); - un1_m0_2_23 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_31 : out std_logic; - un1_m0_2_33 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_5 : out std_logic; - un1_m0_2_6 : out std_logic; - un1_m0_2_8 : out std_logic; - un1_m0_2_11 : out std_logic; - un1_m0_2_12 : out std_logic; - un1_m0_2_18 : out std_logic; - un1_m0_2_29 : out std_logic; - un1_m0_2_19 : out std_logic; - un1_m0_2_9 : out std_logic; - un1_m0_2_10 : out std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_75 : in std_logic; - un1_m0_2_76 : in std_logic; - un1_m0_2_77 : in std_logic; - un1_m0_2_78 : in std_logic; - un1_m0_2_79 : in std_logic; - un1_m0_2_80 : in std_logic; - un1_m0_2_81 : in std_logic; - un1_m0_2_82 : in std_logic; - un1_m0_2_83 : in std_logic; - un1_m0_2_84 : in std_logic; - un1_m0_2_85 : in std_logic; - un1_m0_2_86 : in std_logic; - un1_m0_2_97 : out std_logic; - un1_m0_2_96 : out std_logic; - un1_m0_2_95 : out std_logic; - un1_m0_2_93 : out std_logic; - un1_m0_2_108 : out std_logic; - un1_m0_2_91 : out std_logic; - un1_m0_2_106 : out std_logic; - un1_m0_2_92 : out std_logic; - un1_m0_2_98 : out std_logic; - un1_m0_2_94 : out std_logic; - un1_m0_2_44 : out std_logic; - un1_m0_2_43 : out std_logic; - un1_m0_2_73 : out std_logic; - un1_m0_2_72 : out std_logic; - un1_m0_2_71 : out std_logic; - un1_m0_2_70 : out std_logic; - un1_m0_2_69 : out std_logic; - un1_m0_2_68 : out std_logic; - un1_m0_2_67 : out std_logic; - un1_m0_2_66 : out std_logic; - un1_m0_2_65 : out std_logic; - un1_m0_2_64 : out std_logic; - un1_m0_2_63 : out std_logic; - un1_m0_2_62 : out std_logic; - un1_m0_2_61 : out std_logic; - un1_m0_2_60 : out std_logic; - un1_m0_2_59 : out std_logic; - un1_m0_2_58 : out std_logic; - un1_m0_2_57 : out std_logic; - un1_m0_2_56 : out std_logic; - un1_m0_2_55 : out std_logic; - un1_m0_2_54 : out std_logic; - un1_m0_2_40 : out std_logic; - un1_m0_2_42 : out std_logic; - un1_m0_2_35 : out std_logic; - un1_m0_2_36 : out std_logic; - un1_m0_2_34 : out std_logic; - un1_m0_2_39 : out std_logic; - un1_m0_2_38 : out std_logic; - un1_m0_2_37 : out std_logic; - un1_m0_2_0_d0 : out std_logic; - un1_m0_2_41 : out std_logic; - fault_isid_1_i : out std_logic_vector(0 to 0); - un1_m0_2_0 : out std_logic_vector(35 to 35); - mexc : in std_logic; - req : out std_logic; - ba : in std_logic; - bo_5842_d_0 : in std_logic; - read_0 : out std_logic; - grant : in std_logic; - su_0 : in std_logic; - read : in std_logic; - N_421 : out std_logic; - N_419 : out std_logic; - N_417 : out std_logic; - N_415 : out std_logic; - N_353 : out std_logic; - N_351 : out std_logic; - N_317 : out std_logic; - N_293 : out std_logic; - N_236 : out std_logic; - N_192 : out std_logic; - N_190 : out std_logic; - N_2887 : out std_logic; - N_2886 : out std_logic; - N_2701 : out std_logic; - fault_pro67 : out std_logic; - M_m : out std_logic; - e : in std_logic; - N_2720 : out std_logic; - N_2717 : out std_logic; - N_2714 : out std_logic; - G_80_0 : out std_logic; - N_2703_i_0 : out std_logic; - N_2699_i_0 : out std_logic; - un54_fault_pro_m : out std_logic; - accexc_6 : out std_logic; - fault_pro : out std_logic; - fault_pri_0 : out std_logic; - N_2709_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2702_i_0 : out std_logic; - N_696 : out std_logic; - N_695 : out std_logic; - N_694 : out std_logic; - N_359 : out std_logic; - N_357 : out std_logic; - N_365 : out std_logic; - N_363 : out std_logic; - N_361 : out std_logic; - N_321 : out std_logic; - N_319 : out std_logic; - N_45 : out std_logic; - N_2624 : out std_logic; - N_2623 : out std_logic; - N_425 : out std_logic; - N_423 : out std_logic; - N_43 : out std_logic; - N_2626 : out std_logic; - N_427 : out std_logic; - N_429 : out std_logic; - N_262_0 : in std_logic; - N_78_0 : in std_logic; - N_264_0 : in std_logic; - tlbdis : in std_logic; - N_2625 : out std_logic; - su : in std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - mmu_VCC : in std_logic; - fsread_i_0 : in std_logic; - trans_op_2 : in std_logic; - flush_op_i_0 : in std_logic; - mmudci_trans_op_1_sqmuxa_1 : in std_logic; - N_66 : out std_logic; - trans_op_1 : in std_logic; - un2_m_tlb_type : out std_logic; - flush : out std_logic; - trans_op : in std_logic; - istate_0_sqmuxa : in std_logic; - un81_m_tlb_type : out std_logic; - rst : in std_logic; - N_546 : in std_logic; - N_66_0 : out std_logic; - fault_trans_RNIA0K0D1 : out std_logic; - lclk_c : in std_logic - ); - -end mmu; - -architecture DEF_ARCH of mmu is - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutw - port( data_1 : out std_logic_vector(31 downto 12); - address : out std_logic_vector(31 downto 2); - twowner : in std_logic_vector(0 to 0) := (others => 'U'); - twowner_2 : in std_logic_vector(0 to 0) := (others => 'U'); - aaddr_0_25 : in std_logic := 'U'; - aaddr_0_24 : in std_logic := 'U'; - aaddr_0_29 : in std_logic := 'U'; - aaddr_0_18 : in std_logic := 'U'; - aaddr_0_17 : in std_logic := 'U'; - aaddr_0_9 : in std_logic := 'U'; - aaddr_0_8 : in std_logic := 'U'; - aaddr_0_7 : in std_logic := 'U'; - aaddr_0_4 : in std_logic := 'U'; - aaddr_0_0 : in std_logic := 'U'; - aaddr_0_21 : in std_logic := 'U'; - aaddr_0_22 : in std_logic := 'U'; - aaddr_0_23 : in std_logic := 'U'; - aaddr_0_28 : in std_logic := 'U'; - aaddr_0_27 : in std_logic := 'U'; - aaddr_0_26 : in std_logic := 'U'; - aaddr_0_20 : in std_logic := 'U'; - aaddr_0_19 : in std_logic := 'U'; - aaddr_0_16 : in std_logic := 'U'; - aaddr_0_15 : in std_logic := 'U'; - aaddr_0_14 : in std_logic := 'U'; - aaddr_0_13 : in std_logic := 'U'; - aaddr_0_12 : in std_logic := 'U'; - aaddr_0_11 : in std_logic := 'U'; - aaddr_0_10 : in std_logic := 'U'; - aaddr_0_6 : in std_logic := 'U'; - aaddr_0_3 : in std_logic := 'U'; - aaddr_0_2 : in std_logic := 'U'; - aaddr_0_1 : in std_logic := 'U'; - aaddr_25 : in std_logic := 'U'; - aaddr_24 : in std_logic := 'U'; - aaddr_29 : in std_logic := 'U'; - aaddr_18 : in std_logic := 'U'; - aaddr_17 : in std_logic := 'U'; - aaddr_9 : in std_logic := 'U'; - aaddr_8 : in std_logic := 'U'; - aaddr_7 : in std_logic := 'U'; - aaddr_4 : in std_logic := 'U'; - aaddr_0_d0 : in std_logic := 'U'; - aaddr_21 : in std_logic := 'U'; - aaddr_22 : in std_logic := 'U'; - aaddr_23 : in std_logic := 'U'; - aaddr_28 : in std_logic := 'U'; - aaddr_27 : in std_logic := 'U'; - aaddr_26 : in std_logic := 'U'; - aaddr_20 : in std_logic := 'U'; - aaddr_19 : in std_logic := 'U'; - aaddr_16 : in std_logic := 'U'; - aaddr_15 : in std_logic := 'U'; - aaddr_14 : in std_logic := 'U'; - aaddr_13 : in std_logic := 'U'; - aaddr_12 : in std_logic := 'U'; - aaddr_11 : in std_logic := 'U'; - aaddr_10 : in std_logic := 'U'; - aaddr_6 : in std_logic := 'U'; - aaddr_3 : in std_logic := 'U'; - aaddr_2 : in std_logic := 'U'; - aaddr_1 : in std_logic := 'U'; - twowner_1 : in std_logic_vector(0 to 0) := (others => 'U'); - data_0 : in std_logic_vector(31 downto 12) := (others => 'U'); - data_11 : out std_logic; - data_10 : out std_logic; - data_9 : out std_logic; - data_8 : out std_logic; - data_7 : out std_logic; - data_6 : out std_logic; - data_4 : out std_logic; - data_3 : out std_logic; - data_2 : out std_logic; - data_1_d0 : out std_logic; - data_0_d0 : out std_logic; - data_12 : in std_logic := 'U'; - data_18 : in std_logic := 'U'; - data_24 : in std_logic := 'U'; - data_16 : in std_logic := 'U'; - data_22 : in std_logic := 'U'; - data_28 : in std_logic := 'U'; - data_20 : in std_logic := 'U'; - data_26 : in std_logic := 'U'; - data_17 : in std_logic := 'U'; - data_15 : in std_logic := 'U'; - data_14 : in std_logic := 'U'; - data_13 : in std_logic := 'U'; - data_23 : in std_logic := 'U'; - data_29 : in std_logic := 'U'; - data_30 : in std_logic := 'U'; - data_31 : in std_logic := 'U'; - data_21 : in std_logic := 'U'; - data_27 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - data_25 : in std_logic := 'U'; - adata_0_19 : in std_logic := 'U'; - adata_0_20 : in std_logic := 'U'; - adata_0_18 : in std_logic := 'U'; - adata_0_10 : in std_logic := 'U'; - adata_0_2 : in std_logic := 'U'; - adata_0_13 : in std_logic := 'U'; - adata_0_14 : in std_logic := 'U'; - adata_0_30 : in std_logic := 'U'; - adata_0_29 : in std_logic := 'U'; - adata_0_28 : in std_logic := 'U'; - adata_0_6 : in std_logic := 'U'; - adata_0_1 : in std_logic := 'U'; - adata_0_0 : in std_logic := 'U'; - adata_0_31 : in std_logic := 'U'; - adata_0_17 : in std_logic := 'U'; - adata_0_7 : in std_logic := 'U'; - adata_0_25 : in std_logic := 'U'; - adata_0_22 : in std_logic := 'U'; - adata_0_11 : in std_logic := 'U'; - adata_0_24 : in std_logic := 'U'; - adata_0_23 : in std_logic := 'U'; - adata_0_15 : in std_logic := 'U'; - adata_0_12 : in std_logic := 'U'; - adata_0_21 : in std_logic := 'U'; - adata_0_16 : in std_logic := 'U'; - adata_0_9 : in std_logic := 'U'; - adata_0_8 : in std_logic := 'U'; - adata_0_26 : in std_logic := 'U'; - adata_0_27 : in std_logic := 'U'; - adata_0_4 : in std_logic := 'U'; - adata_0_3 : in std_logic := 'U'; - adata_19 : in std_logic := 'U'; - adata_20 : in std_logic := 'U'; - adata_18 : in std_logic := 'U'; - adata_10 : in std_logic := 'U'; - adata_2 : in std_logic := 'U'; - adata_13 : in std_logic := 'U'; - adata_14 : in std_logic := 'U'; - adata_30 : in std_logic := 'U'; - adata_29 : in std_logic := 'U'; - adata_28 : in std_logic := 'U'; - adata_6 : in std_logic := 'U'; - adata_1 : in std_logic := 'U'; - adata_0_d0 : in std_logic := 'U'; - adata_31 : in std_logic := 'U'; - adata_17 : in std_logic := 'U'; - adata_7 : in std_logic := 'U'; - adata_25 : in std_logic := 'U'; - adata_22 : in std_logic := 'U'; - adata_11 : in std_logic := 'U'; - adata_24 : in std_logic := 'U'; - adata_23 : in std_logic := 'U'; - adata_15 : in std_logic := 'U'; - adata_12 : in std_logic := 'U'; - adata_21 : in std_logic := 'U'; - adata_16 : in std_logic := 'U'; - adata_9 : in std_logic := 'U'; - adata_8 : in std_logic := 'U'; - adata_26 : in std_logic := 'U'; - adata_27 : in std_logic := 'U'; - adata_4 : in std_logic := 'U'; - adata_3 : in std_logic := 'U'; - twowner_0 : in std_logic_vector(0 to 0) := (others => 'U'); - lvl_i_1 : out std_logic_vector(1 downto 0); - ctx_0_d0 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_2 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_6 : in std_logic := 'U'; - ctx_7 : in std_logic := 'U'; - hrdata : in std_logic_vector(6 downto 5) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - ctx_0 : in std_logic_vector(5 downto 4) := (others => 'U'); - ctxp : in std_logic_vector(25 downto 0) := (others => 'U'); - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - lvl_i_1_0 : out std_logic_vector(1 to 1); - lclk_c : in std_logic := 'U'; - grant : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_82 : out std_logic; - N_80 : out std_logic; - N_709 : in std_logic := 'U'; - finish : out std_logic; - N_78_0 : in std_logic := 'U'; - d_N_6_1 : out std_logic; - N_2563_i_0_a4_m7_0_a2_1 : out std_logic; - fault_trans_i_2 : out std_logic; - walk_op_2_0_0_o2_0 : out std_logic; - N_2488 : in std_logic := 'U'; - N_2487 : in std_logic := 'U'; - read : out std_logic; - bo_5842_d_0 : in std_logic := 'U'; - ba : in std_logic := 'U'; - req : out std_logic; - inv_1_0_a2_0_a2_0 : out std_logic; - rst : in std_logic := 'U'; - mexc : in std_logic := 'U'; - fault_mexc : out std_logic; - N_2484 : in std_logic := 'U'; - N_2485 : in std_logic := 'U'; - N_207 : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component mmutlb_10_8_2_1_0 - port( aaddr : inout std_logic_vector(31 downto 2); - twowner_1 : in std_logic_vector(0 to 0) := (others => 'U'); - address : in std_logic_vector(31 downto 2) := (others => 'U'); - data_1_3_i_a3_6_0 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_2 : out std_logic; - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - fault_lvl : out std_logic_vector(1 downto 0); - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - data_2_0 : in std_logic := 'U'; - lvl_i_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - data_1_17 : in std_logic := 'U'; - data_1_5 : out std_logic; - data_1_11 : in std_logic := 'U'; - data_1_10 : in std_logic := 'U'; - data_1_9 : in std_logic := 'U'; - data_1_8 : in std_logic := 'U'; - data_1_7 : in std_logic := 'U'; - data_1_4 : in std_logic := 'U'; - data_1_12 : in std_logic := 'U'; - data_1_15 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - maddress : in std_logic_vector(31 downto 12) := (others => 'U'); - twowner_0 : in std_logic_vector(0 to 0) := (others => 'U'); - data_RNIKU1T4 : out std_logic_vector(16 to 16); - un1_m0_2_94 : out std_logic; - un1_m0_2_98 : out std_logic; - un1_m0_2_92 : out std_logic; - un1_m0_2_106 : out std_logic; - un1_m0_2_91 : out std_logic; - un1_m0_2_108 : out std_logic; - un1_m0_2_93 : out std_logic; - un1_m0_2_95 : out std_logic; - un1_m0_2_96 : out std_logic; - un1_m0_2_97 : out std_logic; - un1_m0_2_86 : in std_logic := 'U'; - un1_m0_2_85 : in std_logic := 'U'; - un1_m0_2_84 : in std_logic := 'U'; - un1_m0_2_83 : in std_logic := 'U'; - un1_m0_2_82 : in std_logic := 'U'; - un1_m0_2_81 : in std_logic := 'U'; - un1_m0_2_80 : in std_logic := 'U'; - un1_m0_2_79 : in std_logic := 'U'; - un1_m0_2_78 : in std_logic := 'U'; - un1_m0_2_77 : in std_logic := 'U'; - un1_m0_2_76 : in std_logic := 'U'; - un1_m0_2_75 : in std_logic := 'U'; - un1_m0_2_7 : out std_logic; - un1_m0_2_10 : out std_logic; - un1_m0_2_9 : out std_logic; - un1_m0_2_0_d0 : out std_logic; - un1_m0_2_19 : out std_logic; - un1_m0_2_29 : out std_logic; - un1_m0_2_18 : out std_logic; - un1_m0_2_12 : out std_logic; - un1_m0_2_11 : out std_logic; - un1_m0_2_8 : out std_logic; - un1_m0_2_6 : out std_logic; - un1_m0_2_5 : out std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_33 : out std_logic; - un1_m0_2_31 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_23 : out std_logic; - data_0_18 : in std_logic := 'U'; - data_0_14 : in std_logic := 'U'; - data_0_22 : out std_logic; - data_0_21 : out std_logic; - data_0_20 : out std_logic; - data_0_19 : out std_logic; - data_0_23 : out std_logic; - data_0_16 : out std_logic; - data_0_28 : in std_logic := 'U'; - data_0_30 : in std_logic := 'U'; - data_0_26 : in std_logic := 'U'; - data_0_25 : in std_logic := 'U'; - data_0_15 : in std_logic := 'U'; - data_0_12 : in std_logic := 'U'; - data_0_31 : in std_logic := 'U'; - data_0_27 : out std_logic; - data_0_29 : out std_logic; - data_0_13 : out std_logic; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - un1_m0_2_0 : in std_logic_vector(35 to 35) := (others => 'U'); - ft_1_i_a2_0 : out std_logic_vector(0 to 0); - twowner_2_0_a2_0_0 : out std_logic_vector(0 to 0); - data_18 : out std_logic; - data_28 : out std_logic; - data_30 : out std_logic; - data_25 : out std_logic; - data_26 : out std_logic; - data_31 : out std_logic; - data_24 : out std_logic; - data_14 : out std_logic; - data_15 : out std_logic; - data_12 : out std_logic; - data_13 : in std_logic := 'U'; - adata_20 : out std_logic; - adata_13 : out std_logic; - adata_17 : out std_logic; - adata_31 : out std_logic; - adata_30 : out std_logic; - adata_29 : out std_logic; - adata_28 : out std_logic; - adata_26 : out std_logic; - adata_24 : out std_logic; - adata_19 : out std_logic; - adata_18 : out std_logic; - adata_16 : out std_logic; - adata_15 : out std_logic; - adata_14 : out std_logic; - adata_11 : out std_logic; - adata_8 : out std_logic; - adata_7 : out std_logic; - adata_6 : out std_logic; - adata_1 : out std_logic; - adata_0 : out std_logic; - adata_9 : out std_logic; - adata_12 : out std_logic; - adata_2 : out std_logic; - adata_3 : out std_logic; - adata_4 : out std_logic; - adata_10 : out std_logic; - adata_27 : out std_logic; - adata_22 : out std_logic; - adata_21 : out std_logic; - adata_25 : out std_logic; - adata_23 : out std_logic; - N_709 : out std_logic; - mmutlb_10_8_2_1_0_VCC : in std_logic := 'U'; - N_694 : out std_logic; - N_695 : out std_logic; - N_696 : out std_logic; - N_2702_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2709_i_0 : out std_logic; - fault_pri_2 : out std_logic; - fault_pro_0 : out std_logic; - accexc_6 : out std_logic; - un54_fault_pro_m : out std_logic; - N_2699_i_0 : out std_logic; - N_2703_i_0 : out std_logic; - G_80_0 : out std_logic; - N_2714 : out std_logic; - N_2717 : out std_logic; - N_2720 : out std_logic; - e : in std_logic := 'U'; - M_m : out std_logic; - fault_pro67 : out std_logic; - N_2701 : out std_logic; - un1_rst_i_0 : out std_logic; - N_264 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - N_82_0 : in std_logic := 'U'; - N_80 : in std_logic := 'U'; - fault_pro_1_0 : in std_logic := 'U'; - fault_mexc_3_2 : out std_logic; - flush_op : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - fault_mexc_0 : out std_logic; - tlbactive : in std_logic := 'U'; - tlbdis : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_3160 : out std_logic; - N_2571 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - fault_pri_m : in std_logic := 'U'; - fault_pri_1 : out std_logic; - fault_pri : out std_logic; - trans_op_0 : in std_logic := 'U'; - N_2488 : out std_logic; - N_2482 : out std_logic; - N_2886 : out std_logic; - N_2887 : out std_logic; - N_190 : out std_logic; - N_192 : out std_logic; - N_236 : out std_logic; - N_293 : out std_logic; - N_317 : out std_logic; - N_351 : out std_logic; - N_353 : out std_logic; - N_415 : out std_logic; - N_417 : out std_logic; - N_419 : out std_logic; - N_421 : out std_logic; - fault_trans_i_2 : in std_logic := 'U'; - fault_su : out std_logic; - fault_read : out std_logic; - inv_1_0_a2_0_a2_0 : in std_logic := 'U'; - fault_trans : out std_logic; - fault_inv : out std_logic; - fault_mexc : in std_logic := 'U'; - areq_ur_1_0_a2_0_0 : out std_logic; - N_2550 : out std_logic; - N_2532 : out std_logic; - rst : in std_logic := 'U'; - read : in std_logic := 'U'; - su : in std_logic := 'U'; - fault_pro_1_iv_1 : out std_logic; - fault_pro_1_iv_2 : out std_logic; - fault_pro_i : out std_logic; - N_82 : in std_logic := 'U'; - s1finished_0 : out std_logic; - walk_use_0 : out std_logic; - lclk_c : in std_logic := 'U'; - N_86_i : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component mmutlb_10_8_0_1_0 - port( address_0 : in std_logic_vector(31 downto 2) := (others => 'U'); - aaddr : out std_logic_vector(31 downto 2); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - fault_lvl_1 : out std_logic; - lvl_i_1 : in std_logic_vector(1 downto 0) := (others => 'U'); - lvl_i_1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - un1_m0_30 : out std_logic; - un1_m0_9 : out std_logic; - un1_m0_8 : out std_logic; - un1_m0_5 : out std_logic; - un1_m0_1 : out std_logic; - un1_m0_22 : out std_logic; - un1_m0_6 : out std_logic; - un1_m0_0 : out std_logic; - un1_m0_17 : out std_logic; - un1_m0_16 : out std_logic; - un1_m0_7 : out std_logic; - un1_m0_4 : out std_logic; - un1_m0_3 : out std_logic; - un1_m0_2 : out std_logic; - un1_itlb0_1 : out std_logic_vector(41 to 41); - un1_m0_2_0 : in std_logic_vector(35 to 35) := (others => 'U'); - data_0_29 : out std_logic; - data_0_27 : out std_logic; - data_0_26 : out std_logic; - data_0_20 : out std_logic; - data_0_12 : out std_logic; - address : in std_logic_vector(31 downto 2) := (others => 'U'); - data_14 : out std_logic; - data_21 : out std_logic; - data_16 : out std_logic; - data_19 : out std_logic; - data_17 : out std_logic; - data_15 : out std_logic; - data_24 : out std_logic; - data_22 : out std_logic; - data_18 : out std_logic; - data_25 : out std_logic; - data_13 : out std_logic; - data_11 : out std_logic; - data_10 : out std_logic; - data_23 : out std_logic; - data_28 : out std_logic; - fault_isid_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - ft_1_i_a2_0 : in std_logic_vector(0 to 0) := (others => 'U'); - hrdata_0_6 : in std_logic := 'U'; - hrdata_0_25 : in std_logic := 'U'; - hrdata_0_20 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - adata_11 : out std_logic; - adata_31 : out std_logic; - adata_30 : out std_logic; - adata_29 : out std_logic; - adata_28 : out std_logic; - adata_27 : out std_logic; - adata_25 : out std_logic; - adata_24 : out std_logic; - adata_23 : out std_logic; - adata_22 : out std_logic; - adata_20 : out std_logic; - adata_17 : out std_logic; - adata_16 : out std_logic; - adata_15 : out std_logic; - adata_14 : out std_logic; - adata_13 : out std_logic; - adata_12 : out std_logic; - adata_10 : out std_logic; - adata_9 : out std_logic; - adata_8 : out std_logic; - adata_7 : out std_logic; - adata_6 : out std_logic; - adata_2 : out std_logic; - adata_1 : out std_logic; - adata_0 : out std_logic; - adata_18 : out std_logic; - adata_21 : out std_logic; - adata_26 : out std_logic; - adata_4 : out std_logic; - adata_3 : out std_logic; - adata_19 : out std_logic; - s2_tlbstate_0 : out std_logic; - mmutlb_10_8_0_1_0_VCC : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - un1_rst_i_0 : in std_logic := 'U'; - N_82 : in std_logic := 'U'; - N_80 : in std_logic := 'U'; - su : in std_logic := 'U'; - N_2625 : out std_logic; - walk_use : out std_logic; - flush_op : in std_logic := 'U'; - N_2933 : out std_logic; - tlbactive : in std_logic := 'U'; - N_180 : out std_logic; - walk_op_ur : out std_logic; - fault_pro_m : in std_logic := 'U'; - fault_pro_1 : out std_logic; - N_2899 : out std_logic; - tlbdis : in std_logic := 'U'; - inv_1_0_a2_0_a2_0 : in std_logic := 'U'; - fault_mexc_2 : in std_logic := 'U'; - fault_trans_i_2 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_3160 : in std_logic := 'U'; - N_2571 : out std_logic; - N_262_0 : in std_logic := 'U'; - fault_pri_m_0 : out std_logic; - fault_mexc_0 : in std_logic := 'U'; - fault_trans_RNIA0K0D1 : out std_logic; - N_429 : out std_logic; - N_427 : out std_logic; - N_2626 : out std_logic; - N_43 : out std_logic; - N_2482 : in std_logic := 'U'; - N_423 : out std_logic; - N_425 : out std_logic; - N_2623 : out std_logic; - N_2624 : out std_logic; - N_45 : out std_logic; - N_319 : out std_logic; - N_321 : out std_logic; - N_361 : out std_logic; - N_363 : out std_logic; - N_365 : out std_logic; - N_357 : out std_logic; - N_1629 : out std_logic; - fault_su : out std_logic; - twi_areq_ur_1_0_a3_i_0 : out std_logic; - fault_mexc_3_2 : in std_logic := 'U'; - fault_mexc_1 : out std_logic; - rst : in std_logic := 'U'; - N_359 : out std_logic; - N_2563_i : in std_logic := 'U'; - s1finished_0 : out std_logic; - lclk_c : in std_logic := 'U'; - N_86_i : in std_logic := 'U' - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_m0_2_1[35]\, fault_access_0_sqmuxa_0, - un207_m_tlb_type_i, trans_op_0, trans_op_RNIFAOCEQ1, - \twowner_2[0]\, twactive_RNI0KM7C4, \twowner_1[0]\, - \twowner_0[0]\, fav_0_sqmuxa_0, ow_2_sqmuxa, N_2899, - \s2_tlbstate[0]\, flush_op, ow_2_sqmuxa_1, fault_mexc_1, - valid_2, fav_1_sqmuxa, ft, fav_1_sqmuxa_RNO, - finish_1_i_o2_m7_0_a2, finish_1_i_o2_m7_0_a2_2, - \twowner_0_RNIK5713[0]\, N_2563_i_0_a4_m7_0_a2_2, - fault_pro_i, un207_m_tlb_type_2, ow_1_sqmuxa, - ow_1_sqmuxa_1, un207_m_tlb_type_1, fault_pri, - N_2563_i_0_a4_m7_0_a2_1_0, N_207, finish_1_i_o2_m7_0_a2_1, - ow_1_sqmuxa_0, flush_0_0, tlbactive_1_2, - \un81_m_tlb_type\, tlbactive_1_0, flush_op_2_m6_i_3, - flush_op_2_m6_i_1, \flush\, \twowner_2_0_a2_0[0]\, - twactive_1_i_a2_0, N_2550, N_2532, N_180, - \ft_1_i_a3_0[0]\, fault_pro_1, fault_pri_1, - N_2563_i_0_a4_m7_0_a2_1, fault_mexc, fault_inv, - fault_trans, N_2485, areq_ur_1_0_a2_0_0, N_2497, - twactive_2, flush_RNO_0, flush_1_sqmuxa, flush_op_RNO_1, - N_4_5_i, d_N_6_1, d_N_5_1, N_2563_i, walk_op_2_0_0_o2_0, - N_82, flush_op_RNO, flush_op_RNO_0, flush_op_RNO_2, - flush_op_0, \fault_isid_1_i[0]\, \un1_m0_2[42]\, N_1576, - \data[12]\, \data_0[12]\, \un1_m0_2_0[35]\, N_1578, - \data[14]\, \data_0[14]\, N_1579, \data[15]\, - \data_0[15]\, N_1580, \data[16]\, \data_0[16]\, N_1581, - \data[17]\, \data_0[17]\, N_1582, \data[18]\, - \data_0[18]\, N_1591, \data[27]\, \data_0[27]\, N_1592, - \data[28]\, \data_0[28]\, N_1594, \data[30]\, - \data_0[30]\, \fault_addr_1[12]\, \N_66_0\, - \fault_addr_1[14]\, \fault_addr_1[15]\, - \fault_addr_1[16]\, \fault_addr_1[17]\, - \fault_addr_1[18]\, \fault_addr_1[27]\, - \fault_addr_1[28]\, \fault_addr_1[30]\, N_2490, fault_su, - fault_read_1, fault_read, fault_su_1, fault_su_0, N_2575, - walk_use_0, \fault_lvl[1]\, \un1_dtlb0_1_i_m[41]\, - \fault_lvl[0]\, \fault_lvl_1_iv[0]\, \un1_itlb0_1[41]\, - \fault_addr_1[23]\, N_582, \fault_addr_1[29]\, N_586, - \fault_addr_1[31]\, \N_66\, N_587, \data[23]\, - \data_0[23]\, \data[29]\, \data_0[29]\, \data[31]\, - \data_0[31]\, N_1584, \data[20]\, \data_0[20]\, N_1586, - \data[22]\, \data_0[22]\, \fault_addr_1[20]\, - \fault_addr_1[22]\, \fault_addr_1[24]\, \un1_m0_2[35]\, - N_583, \fault_addr_1[25]\, N_584, \fault_addr_1[26]\, - N_585, \data[24]\, \data_0[24]\, \data[25]\, \data_0[25]\, - \data[26]\, \data_0[26]\, fav_0_sqmuxa, - \fault_trans_RNIA0K0D1\, N_2484, twi_areq_ur_1_0_a3_i_0, - \fault_addr_1[13]\, N_1577, \data[13]\, \data_0[13]\, - fault_pro_m, fault_pro_1_iv_2, fault_pro_1_iv_1, - \twowner_2_0_a2_0_0[0]\, N_46, N_2487, walk_op_ur, - \twowner[0]\, finish, twactive, tlbactive, s1finished_0, - N_57, N_1748, flush_op_RNO_3, N_1750, N_2933, N_1755, - tlbactive_0, tlbactive_1, s1finished_0_0, N_1757, - flush_op_1, un76_m_tlb_type, \un2_m_tlb_type\, - un75_m_tlb_type, trans_op_RNIA539EQ1, trans_op_3, N_47, - N_49, N_51, N_1583, \data[19]\, \data_0[19]\, - \fault_addr_1[19]\, \fault_addr_1[21]\, N_1585, - \data[21]\, \data_0[21]\, \un1_m0_2[54]\, \ft_RNO[0]\, - N_1629, \ft_1[1]\, fault_mexc_3_2, \ft_1[2]\, N_1744, - N_1947_i, fav_RNO, N_2588, walk_use, \fault_lvl_0[1]\, - \fault_lvl_1_iv[1]\, tlbactive_RNO, \un1_m0_2[37]\, - tlbactive_2, \un1_m0_2[38]\, \un1_m0_2[39]\, - \un1_m0_2[40]\, \aaddr[2]\, \aaddr[3]\, \aaddr[4]\, - \aaddr[5]\, \aaddr[6]\, \aaddr[7]\, \aaddr[8]\, - \aaddr[9]\, \aaddr[10]\, \aaddr[11]\, \aaddr[12]\, - \aaddr[13]\, \aaddr[14]\, \aaddr[15]\, \aaddr[16]\, - \aaddr[17]\, \aaddr[18]\, \aaddr[19]\, \aaddr[20]\, - \aaddr[21]\, \aaddr[22]\, \aaddr[23]\, \aaddr[24]\, - \aaddr[25]\, \aaddr[26]\, \aaddr[27]\, \aaddr[28]\, - \aaddr[29]\, \aaddr[30]\, \aaddr[31]\, \lvl_i_1[0]\, - \lvl_i_1[1]\, \lvl_i_1_0[1]\, \ft_1_i_a2_0[0]\, - \adata[11]\, \adata[31]\, \adata[30]\, \adata[29]\, - \adata[28]\, \adata[27]\, \adata[25]\, \adata[24]\, - \adata[23]\, \adata[22]\, \adata[20]\, \adata[17]\, - \adata[16]\, \adata[15]\, \adata[14]\, \adata[13]\, - \adata[12]\, \adata[10]\, \adata[9]\, \adata[8]\, - \adata[7]\, \adata[6]\, \adata[2]\, \adata[1]\, - \adata[0]\, \adata[18]\, \adata[21]\, \adata[26]\, - \adata[4]\, \adata[3]\, \adata[19]\, un1_rst_i_0, N_82_0, - N_80, inv_1_0_a2_0_a2_0, fault_mexc_0, fault_trans_i_2, - N_3160, N_2571, fault_pri_m, N_2482, N_86_i, \aaddr_0[2]\, - \aaddr_0[3]\, \aaddr_0[4]\, \aaddr_0[5]\, \aaddr_0[6]\, - \aaddr_0[8]\, \aaddr_0[9]\, \aaddr_0[10]\, \aaddr_0[11]\, - \aaddr_0[12]\, \aaddr_0[13]\, \aaddr_0[14]\, - \aaddr_0[15]\, \aaddr_0[16]\, \aaddr_0[17]\, - \aaddr_0[18]\, \aaddr_0[19]\, \aaddr_0[20]\, - \aaddr_0[21]\, \aaddr_0[22]\, \aaddr_0[23]\, - \aaddr_0[24]\, \aaddr_0[25]\, \aaddr_0[26]\, - \aaddr_0[27]\, \aaddr_0[28]\, \aaddr_0[29]\, - \aaddr_0[30]\, \aaddr_0[31]\, \address[2]\, \address[3]\, - \address[4]\, \address[5]\, \address[6]\, \address[7]\, - \address[8]\, \address[9]\, \address[10]\, \address[11]\, - \address[12]\, \address[13]\, \address[14]\, - \address[15]\, \address[16]\, \address[17]\, - \address[18]\, \address[19]\, \address[20]\, - \address[21]\, \address[22]\, \address[23]\, - \address[24]\, \address[25]\, \address[26]\, - \address[27]\, \address[28]\, \address[29]\, - \address[30]\, \address[31]\, \un1_m0_2[1]\, - \adata_0[20]\, \adata_0[13]\, \adata_0[17]\, - \adata_0[31]\, \adata_0[30]\, \adata_0[29]\, - \adata_0[28]\, \adata_0[26]\, \adata_0[24]\, - \adata_0[19]\, \adata_0[18]\, \adata_0[16]\, - \adata_0[15]\, \adata_0[14]\, \adata_0[11]\, \adata_0[8]\, - \adata_0[7]\, \adata_0[6]\, \adata_0[1]\, \adata_0[0]\, - \adata_0[9]\, \adata_0[12]\, \adata_0[2]\, \adata_0[3]\, - \adata_0[4]\, \adata_0[10]\, \adata_0[27]\, \adata_0[22]\, - \adata_0[21]\, \adata_0[25]\, \adata_0[23]\, N_709, - N_2488, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : mmutw - Use entity work.mmutw(DEF_ARCH); - for all : mmutlb_10_8_2_1_0 - Use entity work.mmutlb_10_8_2_1_0(DEF_ARCH); - for all : mmutlb_10_8_0_1_0 - Use entity work.mmutlb_10_8_0_1_0(DEF_ARCH); -begin - - address(31) <= \address[31]\; - address(30) <= \address[30]\; - address(29) <= \address[29]\; - address(28) <= \address[28]\; - address(27) <= \address[27]\; - address(26) <= \address[26]\; - address(25) <= \address[25]\; - address(24) <= \address[24]\; - address(23) <= \address[23]\; - address(22) <= \address[22]\; - address(21) <= \address[21]\; - address(20) <= \address[20]\; - address(19) <= \address[19]\; - address(18) <= \address[18]\; - address(17) <= \address[17]\; - address(16) <= \address[16]\; - address(15) <= \address[15]\; - address(14) <= \address[14]\; - address(13) <= \address[13]\; - address(12) <= \address[12]\; - address(11) <= \address[11]\; - address(10) <= \address[10]\; - address(9) <= \address[9]\; - address(8) <= \address[8]\; - address(7) <= \address[7]\; - address(6) <= \address[6]\; - address(5) <= \address[5]\; - address(4) <= \address[4]\; - address(3) <= \address[3]\; - address(2) <= \address[2]\; - un1_m0_2_36 <= \un1_m0_2[37]\; - un1_m0_2_34 <= \un1_m0_2[35]\; - un1_m0_2_39 <= \un1_m0_2[40]\; - un1_m0_2_38 <= \un1_m0_2[39]\; - un1_m0_2_37 <= \un1_m0_2[38]\; - un1_m0_2_0_d0 <= \un1_m0_2[1]\; - un1_m0_2_41 <= \un1_m0_2[42]\; - fault_isid_1_i(0) <= \fault_isid_1_i[0]\; - un1_m0_2_0(35) <= \un1_m0_2_0[35]\; - N_66 <= \N_66\; - un2_m_tlb_type <= \un2_m_tlb_type\; - flush <= \flush\; - un81_m_tlb_type <= \un81_m_tlb_type\; - N_66_0 <= \N_66_0\; - fault_trans_RNIA0K0D1 <= \fault_trans_RNIA0K0D1\; - - \r.mmctrl2.fs.l_RNO[1]\ : OA1C - port map(A => \un1_m0_2[35]\, B => N_2575, C => N_2588, Y - => \fault_lvl_1_iv[1]\); - - \r.mmctrl2.fa[9]\ : DFN1E1 - port map(D => \fault_addr_1[21]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_63); - - \p0.twod.finish_1_i_o2_m7_0_a2\ : AND2 - port map(A => N_546, B => finish_1_i_o2_m7_0_a2_2, Y => - finish_1_i_o2_m7_0_a2); - - \p0.twod.finish_1_i_o2_m7_0_a2_RNIRIJ8K\ : MX2B - port map(A => N_4_5_i, B => walk_op_2_0_0_o2_0, S => - finish_1_i_o2_m7_0_a2, Y => N_82); - - \r.splt_ds2.tlbactive\ : DFN1 - port map(D => N_51, CLK => lclk_c, Q => tlbactive_0); - - \r.mmctrl2.valid_RNIE60N892\ : OR2B - port map(A => \un1_m0_2[54]\, B => fsread_i_0, Y => valid_2); - - \r.mmctrl2.fa_RNO_0[17]\ : MX2C - port map(A => \data[29]\, B => \data_0[29]\, S => - \un1_m0_2_1[35]\, Y => N_586); - - \r.splt_is1.op.flush_op_RNO_2\ : MX2 - port map(A => flush_op_0, B => \flush\, S => - \un81_m_tlb_type\, Y => flush_op_RNO_2); - - \r.mmctrl2.fa[5]\ : DFN1E1 - port map(D => \fault_addr_1[17]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_59); - - \r.mmctrl2.fs.ft_RNIHTCF[0]\ : OR3A - port map(A => \un1_m0_2[38]\, B => \un1_m0_2[39]\, C => - \un1_m0_2[40]\, Y => ft); - - \r.mmctrl2.fa_RNO_0[18]\ : MX2C - port map(A => \data[30]\, B => \data_0[30]\, S => - \un1_m0_2_0[35]\, Y => N_1594); - - \r.twowner_0_RNIK5713[0]\ : AND2 - port map(A => N_546, B => N_2563_i_0_a4_m7_0_a2_2, Y => - \twowner_0_RNIK5713[0]\); - - \r.mmctrl2.fs.l_RNO[0]\ : OA1C - port map(A => \fault_isid_1_i[0]\, B => \un1_itlb0_1[41]\, - C => \un1_dtlb0_1_i_m[41]\, Y => \fault_lvl_1_iv[0]\); - - \r.mmctrl2.fs.ft[1]\ : DFN1E1 - port map(D => \ft_1[1]\, CLK => lclk_c, E => fav_0_sqmuxa, - Q => \un1_m0_2[39]\); - - \r.twactive_RNIC87T31\ : OR2B - port map(A => finish, B => twactive, Y => twactive_2); - - \r.splt_is2.tlbactive_RNO_0\ : MX2 - port map(A => N_2933, B => tlbactive, S => s1finished_0, Y - => N_1748); - - \r.splt_is2.op.flush_op_RNO\ : NOR2B - port map(A => rst, B => N_1750, Y => flush_op_RNO_3); - - \r.mmctrl2.fs.at_ls_RNO\ : MX2B - port map(A => \N_66_0\, B => fault_read, S => - \un1_m0_2_1[35]\, Y => fault_read_1); - - \r.mmctrl2.fs.ft_RNO[1]\ : AO1 - port map(A => fault_mexc_3_2, B => N_1629, C => - fault_mexc_1, Y => \ft_1[1]\); - - \r.mmctrl2.fa[2]\ : DFN1E1 - port map(D => \fault_addr_1[14]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_56); - - \r.mmctrl2.fs.at_su_RNO_0\ : OR2B - port map(A => fault_su, B => \fault_isid_1_i[0]\, Y => - N_2490); - - \r.mmctrl2.fa_RNO[3]\ : AO1C - port map(A => \un1_m0_2_0[35]\, B => \N_66_0\, C => N_1579, - Y => \fault_addr_1[15]\); - - \r.splt_is1.tlbactive\ : DFN1 - port map(D => tlbactive_RNO, CLK => lclk_c, Q => tlbactive); - - \r.twactive\ : DFN1 - port map(D => N_46, CLK => lclk_c, Q => twactive); - - \r.mmctrl2.fs.l_RNO_0[0]\ : AOI1B - port map(A => walk_use_0, B => \fault_lvl[0]\, C => - \un1_m0_2_1[35]\, Y => \un1_dtlb0_1_i_m[41]\); - - \r.mmctrl2.fa_RNO[16]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1592, - Y => \fault_addr_1[28]\); - - \r.splt_ds1.op.trans_op_0\ : DFN1 - port map(D => trans_op_RNIFAOCEQ1, CLK => lclk_c, Q => - trans_op_0); - - \p0.un207_m_tlb_type\ : AND2 - port map(A => fault_pro_i, B => un207_m_tlb_type_2, Y => - un207_m_tlb_type_i); - - \r.splt_is1.tlbactive_RNIDB3G1\ : OR2A - port map(A => tlbactive, B => s1finished_0, Y => - \un81_m_tlb_type\); - - tw0 : mmutw - port map(data_1(31) => data_2(31), data_1(30) => data_2(30), - data_1(29) => data_2(29), data_1(28) => data_2(28), - data_1(27) => data_2(27), data_1(26) => data_2(26), - data_1(25) => data_2(25), data_1(24) => data_2(24), - data_1(23) => data_2(23), data_1(22) => data_2(22), - data_1(21) => data_2(21), data_1(20) => data_2(20), - data_1(19) => data_2(19), data_1(18) => data_2(18), - data_1(17) => data_2(17), data_1(16) => data_2(16), - data_1(15) => data_2(15), data_1(14) => data_2(14), - data_1(13) => data_2(13), data_1(12) => data_2(12), - address(31) => \address[31]\, address(30) => - \address[30]\, address(29) => \address[29]\, address(28) - => \address[28]\, address(27) => \address[27]\, - address(26) => \address[26]\, address(25) => - \address[25]\, address(24) => \address[24]\, address(23) - => \address[23]\, address(22) => \address[22]\, - address(21) => \address[21]\, address(20) => - \address[20]\, address(19) => \address[19]\, address(18) - => \address[18]\, address(17) => \address[17]\, - address(16) => \address[16]\, address(15) => - \address[15]\, address(14) => \address[14]\, address(13) - => \address[13]\, address(12) => \address[12]\, - address(11) => \address[11]\, address(10) => - \address[10]\, address(9) => \address[9]\, address(8) => - \address[8]\, address(7) => \address[7]\, address(6) => - \address[6]\, address(5) => \address[5]\, address(4) => - \address[4]\, address(3) => \address[3]\, address(2) => - \address[2]\, twowner(0) => \twowner[0]\, twowner_2(0) - => \twowner_2[0]\, aaddr_0_25 => \aaddr_0[27]\, - aaddr_0_24 => \aaddr_0[26]\, aaddr_0_29 => \aaddr_0[31]\, - aaddr_0_18 => \aaddr_0[20]\, aaddr_0_17 => \aaddr_0[19]\, - aaddr_0_9 => \aaddr_0[11]\, aaddr_0_8 => \aaddr_0[10]\, - aaddr_0_7 => \aaddr_0[9]\, aaddr_0_4 => \aaddr_0[6]\, - aaddr_0_0 => \aaddr_0[2]\, aaddr_0_21 => \aaddr_0[23]\, - aaddr_0_22 => \aaddr_0[24]\, aaddr_0_23 => \aaddr_0[25]\, - aaddr_0_28 => \aaddr_0[30]\, aaddr_0_27 => \aaddr_0[29]\, - aaddr_0_26 => \aaddr_0[28]\, aaddr_0_20 => \aaddr_0[22]\, - aaddr_0_19 => \aaddr_0[21]\, aaddr_0_16 => \aaddr_0[18]\, - aaddr_0_15 => \aaddr_0[17]\, aaddr_0_14 => \aaddr_0[16]\, - aaddr_0_13 => \aaddr_0[15]\, aaddr_0_12 => \aaddr_0[14]\, - aaddr_0_11 => \aaddr_0[13]\, aaddr_0_10 => \aaddr_0[12]\, - aaddr_0_6 => \aaddr_0[8]\, aaddr_0_3 => \aaddr_0[5]\, - aaddr_0_2 => \aaddr_0[4]\, aaddr_0_1 => \aaddr_0[3]\, - aaddr_25 => \aaddr[27]\, aaddr_24 => \aaddr[26]\, - aaddr_29 => \aaddr[31]\, aaddr_18 => \aaddr[20]\, - aaddr_17 => \aaddr[19]\, aaddr_9 => \aaddr[11]\, aaddr_8 - => \aaddr[10]\, aaddr_7 => \aaddr[9]\, aaddr_4 => - \aaddr[6]\, aaddr_0_d0 => \aaddr[2]\, aaddr_21 => - \aaddr[23]\, aaddr_22 => \aaddr[24]\, aaddr_23 => - \aaddr[25]\, aaddr_28 => \aaddr[30]\, aaddr_27 => - \aaddr[29]\, aaddr_26 => \aaddr[28]\, aaddr_20 => - \aaddr[22]\, aaddr_19 => \aaddr[21]\, aaddr_16 => - \aaddr[18]\, aaddr_15 => \aaddr[17]\, aaddr_14 => - \aaddr[16]\, aaddr_13 => \aaddr[15]\, aaddr_12 => - \aaddr[14]\, aaddr_11 => \aaddr[13]\, aaddr_10 => - \aaddr[12]\, aaddr_6 => \aaddr[8]\, aaddr_3 => \aaddr[5]\, - aaddr_2 => \aaddr[4]\, aaddr_1 => \aaddr[3]\, - twowner_1(0) => \twowner_1[0]\, data_0(31) => - \data_0[31]\, data_0(30) => \data_0[30]\, data_0(29) => - \data[29]\, data_0(28) => \data[28]\, data_0(27) => - \data[27]\, data_0(26) => \data[26]\, data_0(25) => - \data[25]\, data_0(24) => \data_0[24]\, data_0(23) => - \data[23]\, data_0(22) => \data[22]\, data_0(21) => - \data[21]\, data_0(20) => \data[20]\, data_0(19) => - \data[19]\, data_0(18) => \data_0[18]\, data_0(17) => - \data_0[17]\, data_0(16) => \data_0[16]\, data_0(15) => - \data_0[15]\, data_0(14) => \data_0[14]\, data_0(13) => - \data_0[13]\, data_0(12) => \data_0[12]\, data_11 => - data_11, data_10 => data_10, data_9 => data_9, data_8 => - data_8, data_7 => data_7, data_6 => data_6, data_4 => - data_4, data_3 => data_3, data_2 => data_2_d0, data_1_d0 - => data_1_d0, data_0_d0 => data_0, data_12 => \data[12]\, - data_18 => \data[18]\, data_24 => \data[24]\, data_16 => - \data[16]\, data_22 => \data_0[22]\, data_28 => - \data_0[28]\, data_20 => \data_0[20]\, data_26 => - \data_0[26]\, data_17 => \data[17]\, data_15 => - \data[15]\, data_14 => \data[14]\, data_13 => \data[13]\, - data_23 => \data_0[23]\, data_29 => \data_0[29]\, data_30 - => \data[30]\, data_31 => \data[31]\, data_21 => - \data_0[21]\, data_27 => \data_0[27]\, data_19 => - \data_0[19]\, data_25 => \data_0[25]\, adata_0_19 => - \adata_0[19]\, adata_0_20 => \adata_0[20]\, adata_0_18 - => \adata_0[18]\, adata_0_10 => \adata_0[10]\, adata_0_2 - => \adata_0[2]\, adata_0_13 => \adata_0[13]\, adata_0_14 - => \adata_0[14]\, adata_0_30 => \adata_0[30]\, - adata_0_29 => \adata_0[29]\, adata_0_28 => \adata_0[28]\, - adata_0_6 => \adata_0[6]\, adata_0_1 => \adata_0[1]\, - adata_0_0 => \adata_0[0]\, adata_0_31 => \adata_0[31]\, - adata_0_17 => \adata_0[17]\, adata_0_7 => \adata_0[7]\, - adata_0_25 => \adata_0[25]\, adata_0_22 => \adata_0[22]\, - adata_0_11 => \adata_0[11]\, adata_0_24 => \adata_0[24]\, - adata_0_23 => \adata_0[23]\, adata_0_15 => \adata_0[15]\, - adata_0_12 => \adata_0[12]\, adata_0_21 => \adata_0[21]\, - adata_0_16 => \adata_0[16]\, adata_0_9 => \adata_0[9]\, - adata_0_8 => \adata_0[8]\, adata_0_26 => \adata_0[26]\, - adata_0_27 => \adata_0[27]\, adata_0_4 => \adata_0[4]\, - adata_0_3 => \adata_0[3]\, adata_19 => \adata[19]\, - adata_20 => \adata[20]\, adata_18 => \adata[18]\, - adata_10 => \adata[10]\, adata_2 => \adata[2]\, adata_13 - => \adata[13]\, adata_14 => \adata[14]\, adata_30 => - \adata[30]\, adata_29 => \adata[29]\, adata_28 => - \adata[28]\, adata_6 => \adata[6]\, adata_1 => \adata[1]\, - adata_0_d0 => \adata[0]\, adata_31 => \adata[31]\, - adata_17 => \adata[17]\, adata_7 => \adata[7]\, adata_25 - => \adata[25]\, adata_22 => \adata[22]\, adata_11 => - \adata[11]\, adata_24 => \adata[24]\, adata_23 => - \adata[23]\, adata_15 => \adata[15]\, adata_12 => - \adata[12]\, adata_21 => \adata[21]\, adata_16 => - \adata[16]\, adata_9 => \adata[9]\, adata_8 => \adata[8]\, - adata_26 => \adata[26]\, adata_27 => \adata[27]\, adata_4 - => \adata[4]\, adata_3 => \adata[3]\, twowner_0(0) => - \twowner_0[0]\, lvl_i_1(1) => \lvl_i_1[1]\, lvl_i_1(0) - => \lvl_i_1[0]\, ctx_0_d0 => ctx(0), ctx_1 => ctx(1), - ctx_2 => ctx(2), ctx_3 => ctx(3), ctx_6 => ctx(6), ctx_7 - => ctx(7), hrdata(6) => hrdata_6, hrdata(5) => hrdata_5, - iosn_0(93) => iosn_0(93), ctx_0(5) => ctx_0(5), ctx_0(4) - => ctx_0(4), ctxp(25) => ctxp(25), ctxp(24) => ctxp(24), - ctxp(23) => ctxp(23), ctxp(22) => ctxp(22), ctxp(21) => - ctxp(21), ctxp(20) => ctxp(20), ctxp(19) => ctxp(19), - ctxp(18) => ctxp(18), ctxp(17) => ctxp(17), ctxp(16) => - ctxp(16), ctxp(15) => ctxp(15), ctxp(14) => ctxp(14), - ctxp(13) => ctxp(13), ctxp(12) => ctxp(12), ctxp(11) => - ctxp(11), ctxp(10) => ctxp(10), ctxp(9) => ctxp(9), - ctxp(8) => ctxp(8), ctxp(7) => ctxp(7), ctxp(6) => - ctxp(6), ctxp(5) => ctxp(5), ctxp(4) => ctxp(4), ctxp(3) - => ctxp(3), ctxp(2) => ctxp(2), ctxp(1) => ctxp(1), - ctxp(0) => ctxp(0), hrdata_0_3 => hrdata_0_3, hrdata_0_16 - => hrdata_0_16, hrdata_0_15 => hrdata_0_15, hrdata_0_13 - => hrdata_0_13, hrdata_0_10 => hrdata_0_10, hrdata_0_9 - => hrdata_0_9, hrdata_0_8 => hrdata_0_8, hrdata_0_24 => - hrdata_0_24, hrdata_0_26 => hrdata_0_26, hrdata_0_4 => - hrdata_0_4, hrdata_0_1 => hrdata_0_1, hrdata_0_0 => - hrdata_0_0, hrdata_0_2 => hrdata_0_2, hrdata_0_14 => - hrdata_0_14, hrdata_0_12 => hrdata_0_12, hrdata_0_11 => - hrdata_0_11, hrdata_0_21 => hrdata_0_21, hrdata_0_18 => - hrdata_0_18, hrdata_0_17 => hrdata_0_17, hrdata_0_7 => - hrdata_0_7, hrdata_0_23 => hrdata_0_23, hrdata_0_22 => - hrdata_0_22, hrdata_0_27 => hrdata_0_27, lvl_i_1_0(1) => - \lvl_i_1_0[1]\, lclk_c => lclk_c, grant => grant, N_264_0 - => N_264_0, N_262_0 => N_262_0, N_82 => N_82_0, N_80 => - N_80, N_709 => N_709, finish => finish, N_78_0 => N_78_0, - d_N_6_1 => d_N_6_1, N_2563_i_0_a4_m7_0_a2_1 => - N_2563_i_0_a4_m7_0_a2_1, fault_trans_i_2 => - fault_trans_i_2, walk_op_2_0_0_o2_0 => walk_op_2_0_0_o2_0, - N_2488 => N_2488, N_2487 => N_2487, read => read_0, - bo_5842_d_0 => bo_5842_d_0, ba => ba, req => req, - inv_1_0_a2_0_a2_0 => inv_1_0_a2_0_a2_0, rst => rst, mexc - => mexc, fault_mexc => fault_mexc_0, N_2484 => N_2484, - N_2485 => N_2485, N_207 => N_207); - - \v.mmctrl2.fs.ow_1_sqmuxa_RNO\ : AND2 - port map(A => \fault_isid_1_i[0]\, B => ow_1_sqmuxa_0, Y - => ow_1_sqmuxa_1); - - \r.splt_ds1.tlbactive_RNO\ : OA1A - port map(A => \un2_m_tlb_type\, B => un75_m_tlb_type, C => - rst, Y => N_49); - - \r.mmctrl2.fa_RNO_0[10]\ : MX2C - port map(A => \data[22]\, B => \data_0[22]\, S => - \un1_m0_2_1[35]\, Y => N_1586); - - \r.mmctrl2.fa[17]\ : DFN1E1 - port map(D => \fault_addr_1[29]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_71); - - \r.splt_ds1.tlbactive_RNO_0\ : OR2B - port map(A => trans_op_2, B => flush_op_i_0, Y => - un75_m_tlb_type); - - \r.twowner_2[0]\ : DFN1 - port map(D => twactive_RNI0KM7C4, CLK => lclk_c, Q => - \twowner_2[0]\); - - \r.twactive_RNO_0\ : AO1D - port map(A => N_2550, B => N_2532, C => N_180, Y => - twactive_1_i_a2_0); - - \r.splt_ds1.op.trans_op_RNIFAOCEQ1\ : NOR2A - port map(A => rst, B => trans_op_RNIA539EQ1, Y => - trans_op_RNIFAOCEQ1); - - \r.flush_RNO_0\ : OR2A - port map(A => rst, B => \un81_m_tlb_type\, Y => flush_0_0); - - \r.mmctrl2.fa_RNO_0[16]\ : MX2C - port map(A => \data[28]\, B => \data_0[28]\, S => - \un1_m0_2_0[35]\, Y => N_1592); - - \r.mmctrl2.fa_RNO[7]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_1583, Y - => \fault_addr_1[19]\); - - \p0.un207_m_tlb_type_RNI4B8O1\ : NOR2 - port map(A => fault_access_0_sqmuxa_0, B => - un207_m_tlb_type_i, Y => \un1_m0_2_0[35]\); - - \p0.twod.finish_1_i_o2_m7_0_a2_RNO\ : NOR2A - port map(A => finish_1_i_o2_m7_0_a2_1, B => N_207, Y => - finish_1_i_o2_m7_0_a2_2); - - \r.splt_is1.op.flush_op_RNO_4\ : NOR3A - port map(A => rst, B => \flush\, C => trans_op_1, Y => - flush_op_2_m6_i_1); - - \r.mmctrl2.fa_RNO[14]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_585, Y - => \fault_addr_1[26]\); - - GND_i : GND - port map(Y => \GND\); - - \r.splt_is1.op.flush_op_RNO_3\ : NOR3C - port map(A => \un2_m_tlb_type\, B => flush_op_2_m6_i_1, C - => \un81_m_tlb_type\, Y => flush_op_2_m6_i_3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.mmctrl2.fa_RNO[9]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_1585, Y - => \fault_addr_1[21]\); - - \r.splt_ds2.tlbactive_RNO\ : NOR2B - port map(A => rst, B => N_1755, Y => N_51); - - \r.splt_is2.op.flush_op_RNO_0\ : MX2 - port map(A => flush_op, B => flush_op_0, S => s1finished_0, - Y => N_1750); - - \r.mmctrl2.fa_RNO[0]\ : AO1C - port map(A => \un1_m0_2_0[35]\, B => \N_66_0\, C => N_1576, - Y => \fault_addr_1[12]\); - - \r.mmctrl2.fa_RNO_0[4]\ : MX2C - port map(A => \data[16]\, B => \data_0[16]\, S => - \un1_m0_2_0[35]\, Y => N_1580); - - \r.mmctrl2.fa[7]\ : DFN1E1 - port map(D => \fault_addr_1[19]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_61); - - \tlbsplit0.dtlb0\ : mmutlb_10_8_2_1_0 - port map(aaddr(31) => \aaddr_0[31]\, aaddr(30) => - \aaddr_0[30]\, aaddr(29) => \aaddr_0[29]\, aaddr(28) => - \aaddr_0[28]\, aaddr(27) => \aaddr_0[27]\, aaddr(26) => - \aaddr_0[26]\, aaddr(25) => \aaddr_0[25]\, aaddr(24) => - \aaddr_0[24]\, aaddr(23) => \aaddr_0[23]\, aaddr(22) => - \aaddr_0[22]\, aaddr(21) => \aaddr_0[21]\, aaddr(20) => - \aaddr_0[20]\, aaddr(19) => \aaddr_0[19]\, aaddr(18) => - \aaddr_0[18]\, aaddr(17) => \aaddr_0[17]\, aaddr(16) => - \aaddr_0[16]\, aaddr(15) => \aaddr_0[15]\, aaddr(14) => - \aaddr_0[14]\, aaddr(13) => \aaddr_0[13]\, aaddr(12) => - \aaddr_0[12]\, aaddr(11) => \aaddr_0[11]\, aaddr(10) => - \aaddr_0[10]\, aaddr(9) => \aaddr_0[9]\, aaddr(8) => - \aaddr_0[8]\, aaddr(7) => \aaddr[7]\, aaddr(6) => - \aaddr_0[6]\, aaddr(5) => \aaddr_0[5]\, aaddr(4) => - \aaddr_0[4]\, aaddr(3) => \aaddr_0[3]\, aaddr(2) => - \aaddr_0[2]\, twowner_1(0) => \twowner_1[0]\, address(31) - => \address[31]\, address(30) => \address[30]\, - address(29) => \address[29]\, address(28) => - \address[28]\, address(27) => \address[27]\, address(26) - => \address[26]\, address(25) => \address[25]\, - address(24) => \address[24]\, address(23) => - \address[23]\, address(22) => \address[22]\, address(21) - => \address[21]\, address(20) => \address[20]\, - address(19) => \address[19]\, address(18) => - \address[18]\, address(17) => \address[17]\, address(16) - => \address[16]\, address(15) => \address[15]\, - address(14) => \address[14]\, address(13) => - \address[13]\, address(12) => \address[12]\, address(11) - => \address[11]\, address(10) => \address[10]\, - address(9) => \address[9]\, address(8) => \address[8]\, - address(7) => \address[7]\, address(6) => \address[6]\, - address(5) => \address[5]\, address(4) => \address[4]\, - address(3) => \address[3]\, address(2) => \address[2]\, - data_1_3_i_a3_6_0 => data_1_3_i_a3_6_0, data_1_3_i_a3_6_1 - => data_1_3_i_a3_6_1, data_1_3_i_a3_6_4 => - data_1_3_i_a3_6_4, data_1_3_i_a3_6_2 => data_1_3_i_a3_6_2, - LVL_RNIT69H911(0) => LVL_RNIT69H911(0), ctx_0(7) => - ctx_0(7), ctx_0(6) => ctx_0(6), ctx_0(5) => ctx_0(5), - ctx_0(4) => ctx_0(4), ctx_0(3) => ctx_0(3), ctx_0(2) => - ctx_0(2), ctx_0(1) => ctx_0(1), ctx_0(0) => ctx_0(0), - ctx(7) => ctx(7), ctx(6) => ctx(6), ctx(5) => ctx(5), - ctx(4) => ctx(4), ctx(3) => ctx(3), ctx(2) => ctx(2), - ctx(1) => ctx(1), ctx(0) => ctx(0), fault_lvl(1) => - \fault_lvl[1]\, fault_lvl(0) => \fault_lvl[0]\, - lvl_i_1(1) => \lvl_i_1[1]\, lvl_i_1(0) => \lvl_i_1[0]\, - data_2_0 => data_1(17), lvl_i_1_0(1) => \lvl_i_1_0[1]\, - data_1_17 => data_1(29), data_1_5 => \data_0[17]\, - data_1_11 => data_1(23), data_1_10 => data_1(22), - data_1_9 => data_1(21), data_1_8 => data_1(20), data_1_7 - => data_1(19), data_1_4 => data_1(16), data_1_12 => - data_1(24), data_1_15 => data_1(27), hrdata_2 => hrdata_2, - hrdata_3 => hrdata_3, hrdata_4 => hrdata_4, hrdata_0_d0 - => hrdata_0_d0, hrdata_1 => hrdata_1, hrdata_8 => - hrdata_8, hrdata_9 => hrdata_9, hrdata_10 => hrdata_10, - hrdata_11 => hrdata_11, hrdata_12 => hrdata_12, hrdata_13 - => hrdata_13, hrdata_14 => hrdata_14, hrdata_15 => - hrdata_15, hrdata_16 => hrdata_16, hrdata_17 => hrdata_17, - hrdata_18 => hrdata_18, hrdata_21 => hrdata_21, hrdata_22 - => hrdata_22, hrdata_23 => hrdata_23, hrdata_24 => - hrdata_24, hrdata_26 => hrdata_26, hrdata_27 => hrdata_27, - hrdata_28 => hrdata_28, hrdata_29 => hrdata_29, hrdata_30 - => hrdata_30, hrdata_31 => hrdata_31, hrdata_7 => - hrdata_7, hrdata_5 => hrdata_5, hrdata_6 => hrdata_6, - maddress(31) => maddress(31), maddress(30) => - maddress(30), maddress(29) => maddress(29), maddress(28) - => maddress(28), maddress(27) => maddress(27), - maddress(26) => maddress(26), maddress(25) => - maddress(25), maddress(24) => maddress(24), maddress(23) - => maddress(23), maddress(22) => maddress(22), - maddress(21) => maddress(21), maddress(20) => - maddress(20), maddress(19) => maddress(19), maddress(18) - => maddress(18), maddress(17) => maddress(17), - maddress(16) => maddress(16), maddress(15) => - maddress(15), maddress(14) => maddress(14), maddress(13) - => maddress(13), maddress(12) => maddress(12), - twowner_0(0) => \twowner_0[0]\, data_RNIKU1T4(16) => - data_RNIKU1T4(16), un1_m0_2_94 => un1_m0_2_94, - un1_m0_2_98 => un1_m0_2_98, un1_m0_2_92 => un1_m0_2_92, - un1_m0_2_106 => un1_m0_2_106, un1_m0_2_91 => un1_m0_2_91, - un1_m0_2_108 => un1_m0_2_108, un1_m0_2_93 => un1_m0_2_93, - un1_m0_2_95 => un1_m0_2_95, un1_m0_2_96 => un1_m0_2_96, - un1_m0_2_97 => un1_m0_2_97, un1_m0_2_86 => un1_m0_2_86, - un1_m0_2_85 => un1_m0_2_85, un1_m0_2_84 => un1_m0_2_84, - un1_m0_2_83 => un1_m0_2_83, un1_m0_2_82 => un1_m0_2_82, - un1_m0_2_81 => un1_m0_2_81, un1_m0_2_80 => un1_m0_2_80, - un1_m0_2_79 => un1_m0_2_79, un1_m0_2_78 => un1_m0_2_78, - un1_m0_2_77 => un1_m0_2_77, un1_m0_2_76 => un1_m0_2_76, - un1_m0_2_75 => un1_m0_2_75, un1_m0_2_7 => un1_m0_2_7, - un1_m0_2_10 => un1_m0_2_10, un1_m0_2_9 => un1_m0_2_9, - un1_m0_2_0_d0 => \un1_m0_2[1]\, un1_m0_2_19 => - un1_m0_2_19, un1_m0_2_29 => un1_m0_2_29, un1_m0_2_18 => - un1_m0_2_18, un1_m0_2_12 => un1_m0_2_12, un1_m0_2_11 => - un1_m0_2_11, un1_m0_2_8 => un1_m0_2_8, un1_m0_2_6 => - un1_m0_2_6, un1_m0_2_5 => un1_m0_2_5, un1_m0_2_4 => - un1_m0_2_4, un1_m0_2_3 => un1_m0_2_3, un1_m0_2_2 => - un1_m0_2_2, un1_m0_2_1 => un1_m0_2_1, un1_m0_2_33 => - un1_m0_2_33, un1_m0_2_31 => un1_m0_2_31, un1_m0_2_15 => - un1_m0_2_15, un1_m0_2_23 => un1_m0_2_23, data_0_18 => - data_1(18), data_0_14 => data_1(14), data_0_22 => - \data_0[22]\, data_0_21 => \data_0[21]\, data_0_20 => - \data_0[20]\, data_0_19 => \data_0[19]\, data_0_23 => - \data_0[23]\, data_0_16 => \data_0[16]\, data_0_28 => - data_1(28), data_0_30 => data_1(30), data_0_26 => - data_1(26), data_0_25 => data_1(25), data_0_15 => - data_1(15), data_0_12 => data_1(12), data_0_31 => - data_1(31), data_0_27 => \data_0[27]\, data_0_29 => - \data_0[29]\, data_0_13 => \data_0[13]\, hrdata_0_0 => - hrdata_0_0, hrdata_0_15 => hrdata_0_15, hrdata_0_14 => - hrdata_0_14, hrdata_0_16 => hrdata_0_16, hrdata_0_13 => - hrdata_0_13, hrdata_0_26 => hrdata_0_26, hrdata_0_24 => - hrdata_0_24, hrdata_0_27 => hrdata_0_27, hrdata_0_18 => - hrdata_0_18, hrdata_0_17 => hrdata_0_17, hrdata_0_11 => - hrdata_0_11, hrdata_0_12 => hrdata_0_12, hrdata_0_10 => - hrdata_0_10, hrdata_0_9 => hrdata_0_9, hrdata_0_8 => - hrdata_0_8, hrdata_0_23 => hrdata_0_23, hrdata_0_22 => - hrdata_0_22, hrdata_0_21 => hrdata_0_21, hrdata_0_2 => - hrdata_0_2, hrdata_0_3 => hrdata_0_3, hrdata_0_4 => - hrdata_0_4, hrdata_0_1 => hrdata_0_1, un1_m0_2_0(35) => - \un1_m0_2_0[35]\, ft_1_i_a2_0(0) => \ft_1_i_a2_0[0]\, - twowner_2_0_a2_0_0(0) => \twowner_2_0_a2_0_0[0]\, data_18 - => \data_0[18]\, data_28 => \data_0[28]\, data_30 => - \data_0[30]\, data_25 => \data_0[25]\, data_26 => - \data_0[26]\, data_31 => \data_0[31]\, data_24 => - \data_0[24]\, data_14 => \data_0[14]\, data_15 => - \data_0[15]\, data_12 => \data_0[12]\, data_13 => - data_1(13), adata_20 => \adata_0[20]\, adata_13 => - \adata_0[13]\, adata_17 => \adata_0[17]\, adata_31 => - \adata_0[31]\, adata_30 => \adata_0[30]\, adata_29 => - \adata_0[29]\, adata_28 => \adata_0[28]\, adata_26 => - \adata_0[26]\, adata_24 => \adata_0[24]\, adata_19 => - \adata_0[19]\, adata_18 => \adata_0[18]\, adata_16 => - \adata_0[16]\, adata_15 => \adata_0[15]\, adata_14 => - \adata_0[14]\, adata_11 => \adata_0[11]\, adata_8 => - \adata_0[8]\, adata_7 => \adata_0[7]\, adata_6 => - \adata_0[6]\, adata_1 => \adata_0[1]\, adata_0 => - \adata_0[0]\, adata_9 => \adata_0[9]\, adata_12 => - \adata_0[12]\, adata_2 => \adata_0[2]\, adata_3 => - \adata_0[3]\, adata_4 => \adata_0[4]\, adata_10 => - \adata_0[10]\, adata_27 => \adata_0[27]\, adata_22 => - \adata_0[22]\, adata_21 => \adata_0[21]\, adata_25 => - \adata_0[25]\, adata_23 => \adata_0[23]\, N_709 => N_709, - mmutlb_10_8_2_1_0_VCC => mmu_VCC, N_694 => N_694, N_695 - => N_695, N_696 => N_696, N_2702_i_0 => N_2702_i_0, - N_2711_i_0 => N_2711_i_0, N_2709_i_0 => N_2709_i_0, - fault_pri_2 => fault_pri_0, fault_pro_0 => fault_pro, - accexc_6 => accexc_6, un54_fault_pro_m => - un54_fault_pro_m, N_2699_i_0 => N_2699_i_0, N_2703_i_0 - => N_2703_i_0, G_80_0 => G_80_0, N_2714 => N_2714, - N_2717 => N_2717, N_2720 => N_2720, e => e, M_m => M_m, - fault_pro67 => fault_pro67, N_2701 => N_2701, un1_rst_i_0 - => un1_rst_i_0, N_264 => N_264, N_262 => N_262, N_78 => - N_78, N_82_0 => N_82_0, N_80 => N_80, fault_pro_1_0 => - fault_pro_1, fault_mexc_3_2 => fault_mexc_3_2, flush_op - => flush_op_1, N_264_0 => N_264_0, fault_mexc_0 => - fault_mexc, tlbactive => tlbactive_0, tlbdis => tlbdis, - trans_op => trans_op_3, N_78_0 => N_78_0, N_3160 => - N_3160, N_2571 => N_2571, N_262_0 => N_262_0, fault_pri_m - => fault_pri_m, fault_pri_1 => fault_pri_1, fault_pri - => fault_pri, trans_op_0 => trans_op_0, N_2488 => N_2488, - N_2482 => N_2482, N_2886 => N_2886, N_2887 => N_2887, - N_190 => N_190, N_192 => N_192, N_236 => N_236, N_293 => - N_293, N_317 => N_317, N_351 => N_351, N_353 => N_353, - N_415 => N_415, N_417 => N_417, N_419 => N_419, N_421 => - N_421, fault_trans_i_2 => fault_trans_i_2, fault_su => - fault_su_0, fault_read => fault_read, inv_1_0_a2_0_a2_0 - => inv_1_0_a2_0_a2_0, fault_trans => fault_trans, - fault_inv => fault_inv, fault_mexc => fault_mexc_0, - areq_ur_1_0_a2_0_0 => areq_ur_1_0_a2_0_0, N_2550 => - N_2550, N_2532 => N_2532, rst => rst, read => read, su - => su_0, fault_pro_1_iv_1 => fault_pro_1_iv_1, - fault_pro_1_iv_2 => fault_pro_1_iv_2, fault_pro_i => - fault_pro_i, N_82 => N_82, s1finished_0 => s1finished_0_0, - walk_use_0 => walk_use_0, lclk_c => lclk_c, N_86_i => - N_86_i); - - \un1_v.mmctrl2.fs.fav_1_sqmuxa_RNO\ : NOR2A - port map(A => \fault_isid_1_i[0]\, B => \un1_m0_2[42]\, Y - => fav_1_sqmuxa_RNO); - - \r.mmctrl2.fa[18]\ : DFN1E1 - port map(D => \fault_addr_1[30]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_72); - - \r.mmctrl2.fa_RNO_0[1]\ : MX2C - port map(A => \data[13]\, B => \data_0[13]\, S => - \un1_m0_2[35]\, Y => N_1577); - - \r.twowner_0_RNIKU46[0]\ : NOR2B - port map(A => \twowner_0[0]\, B => rst, Y => - \twowner_2_0_a2_0[0]\); - - \r.mmctrl2.fa_RNO_0[8]\ : MX2C - port map(A => \data[20]\, B => \data_0[20]\, S => - \un1_m0_2_1[35]\, Y => N_1584); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.mmctrl2.fa_RNO_0[3]\ : MX2C - port map(A => \data[15]\, B => \data_0[15]\, S => - \un1_m0_2_0[35]\, Y => N_1579); - - \r.mmctrl2.fa_RNO[18]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1594, - Y => \fault_addr_1[30]\); - - \p0.twod.finish_1_i_o2_m7_0_a2_RNO_0\ : NOR3B - port map(A => \twowner_0[0]\, B => hrdata_1_0_1(1), C => - N_2563_i_0_a4_m7_0_a2_1, Y => finish_1_i_o2_m7_0_a2_1); - - \r.splt_is2.tlbactive\ : DFN1 - port map(D => N_57, CLK => lclk_c, Q => tlbactive_2); - - \r.mmctrl2.fa_RNO_0[9]\ : MX2C - port map(A => \data[21]\, B => \data_0[21]\, S => - \un1_m0_2[35]\, Y => N_1585); - - \r.mmctrl2.fa[4]\ : DFN1E1 - port map(D => \fault_addr_1[16]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_58); - - \r.mmctrl2.fa[11]\ : DFN1E1 - port map(D => \fault_addr_1[23]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_65); - - \r.splt_ds1.op.flush_op\ : DFN1 - port map(D => N_47, CLK => lclk_c, Q => flush_op_1); - - \r.mmctrl2.fa_RNO[2]\ : AO1C - port map(A => \un1_m0_2_0[35]\, B => \N_66_0\, C => N_1578, - Y => \fault_addr_1[14]\); - - \r.splt_ds1.tlbactive_RNISK7K1\ : OR2A - port map(A => tlbactive_1, B => s1finished_0_0, Y => - \un2_m_tlb_type\); - - \r.mmctrl2.valid_RNO\ : OA1A - port map(A => valid_2, B => \fault_trans_RNIA0K0D1\, C => - rst, Y => N_1947_i); - - \r.mmctrl2.fa_RNO[6]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1582, - Y => \fault_addr_1[18]\); - - \r.mmctrl2.fa_RNO_0[11]\ : MX2C - port map(A => \data[23]\, B => \data_0[23]\, S => - \un1_m0_2_1[35]\, Y => N_582); - - \r.mmctrl2.fa[15]\ : DFN1E1 - port map(D => \fault_addr_1[27]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_69); - - \r.twactive_RNO\ : OA1A - port map(A => twactive_2, B => twactive_1_i_a2_0, C => rst, - Y => N_46); - - \r.mmctrl2.fa[13]\ : DFN1E1 - port map(D => \fault_addr_1[25]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_67); - - \r.splt_is1.op.flush_op_RNO\ : MX2C - port map(A => flush_op_i_0, B => flush_op_RNO_0, S => - flush_op_RNO_1, Y => flush_op_RNO); - - \r.mmctrl2.fa_RNO[11]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_582, - Y => \fault_addr_1[23]\); - - \r.mmctrl2.fa_RNO_0[13]\ : MX2C - port map(A => \data[25]\, B => \data_0[25]\, S => - \un1_m0_2[35]\, Y => N_584); - - \r.mmctrl2.fa_RNO[19]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66\, C => N_587, Y - => \fault_addr_1[31]\); - - \r.mmctrl2.fa_RNO[17]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_586, - Y => \fault_addr_1[29]\); - - \r.mmctrl2.fs.l[1]\ : DFN1E1 - port map(D => \fault_lvl_1_iv[1]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_44); - - \r.mmctrl2.fa[8]\ : DFN1E1 - port map(D => \fault_addr_1[20]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_62); - - \p0.un207_m_tlb_type_RNO\ : NOR2A - port map(A => un207_m_tlb_type_1, B => fault_pri, Y => - un207_m_tlb_type_2); - - \r.splt_is2.tlbactive_RNO\ : NOR2B - port map(A => rst, B => N_1748, Y => N_57); - - \r.splt_ds1.op.flush_op_RNO_0\ : MX2 - port map(A => flush_op_1, B => un76_m_tlb_type, S => - \un2_m_tlb_type\, Y => N_1757); - - \r.mmctrl2.fa_RNO[13]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_584, Y - => \fault_addr_1[25]\); - - \v.mmctrl2.fs.ow_2_sqmuxa_RNIBOO1D1\ : NOR2A - port map(A => \fault_trans_RNIA0K0D1\, B => ow_2_sqmuxa, Y - => fav_0_sqmuxa); - - \r.twowner_0_RNIRS742[0]\ : OR3A - port map(A => \twowner_0[0]\, B => d_N_6_1, C => N_207, Y - => N_4_5_i); - - \r.mmctrl2.fa_RNO[15]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1591, - Y => \fault_addr_1[27]\); - - \r.mmctrl2.fa[1]\ : DFN1E1 - port map(D => \fault_addr_1[13]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_55); - - \r.mmctrl2.fa_RNO_0[12]\ : MX2C - port map(A => \data[24]\, B => \data_0[24]\, S => - \un1_m0_2[35]\, Y => N_583); - - \r.mmctrl2.fa_RNO[4]\ : AO1C - port map(A => \un1_m0_2_0[35]\, B => \N_66_0\, C => N_1580, - Y => \fault_addr_1[16]\); - - \r.splt_is2.op.flush_op_RNIL4H81\ : OR3A - port map(A => N_2899, B => \s2_tlbstate[0]\, C => flush_op, - Y => \N_66\); - - \v.mmctrl2.fs.ow_2_sqmuxa_1\ : NOR2 - port map(A => fault_mexc_1, B => valid_2, Y => - ow_2_sqmuxa_1); - - \r.mmctrl2.fs.l[0]\ : DFN1E1 - port map(D => \fault_lvl_1_iv[0]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_43); - - \r.mmctrl2.fs.at_ls\ : DFN1E1 - port map(D => fault_read_1, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_40); - - \r.mmctrl2.fa[3]\ : DFN1E1 - port map(D => \fault_addr_1[15]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_57); - - \r.mmctrl2.valid\ : DFN1 - port map(D => N_1947_i, CLK => lclk_c, Q => \un1_m0_2[54]\); - - \r.mmctrl2.fs.at_su\ : DFN1E1 - port map(D => fault_su_1, CLK => lclk_c, E => fav_0_sqmuxa, - Q => un1_m0_2_42); - - \r.mmctrl2.fa_RNO_0[7]\ : MX2C - port map(A => \data[19]\, B => \data_0[19]\, S => - \un1_m0_2[35]\, Y => N_1583); - - \r.splt_is1.op.flush_op_RNO_0\ : OR2B - port map(A => rst, B => flush_op_RNO_2, Y => flush_op_RNO_0); - - \r.mmctrl2.fa_RNO_0[19]\ : MX2C - port map(A => \data[31]\, B => \data_0[31]\, S => - \un1_m0_2_1[35]\, Y => N_587); - - \r.mmctrl2.fa_RNO[1]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_1577, Y - => \fault_addr_1[13]\); - - \r.twowner_0_RNIRS742_0[0]\ : NOR3 - port map(A => \twowner_0[0]\, B => d_N_6_1, C => N_207, Y - => d_N_5_1); - - \p0.un207_m_tlb_type_RNILVF0C\ : AO1B - port map(A => fault_pro_1_iv_2, B => fault_pro_1_iv_1, C - => \un1_m0_2[35]\, Y => fault_pro_m); - - \r.mmctrl2.fa_RNO[8]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66\, C => N_1584, Y - => \fault_addr_1[20]\); - - \r.flush\ : DFN1 - port map(D => flush_RNO_0, CLK => lclk_c, Q => \flush\); - - \r.twowner_1[0]\ : DFN1 - port map(D => twactive_RNI0KM7C4, CLK => lclk_c, Q => - \twowner_1[0]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.mmctrl2.fs.l_RNO_1[1]\ : AOI1B - port map(A => walk_use, B => \fault_lvl_0[1]\, C => - \fault_isid_1_i[0]\, Y => N_2588); - - \r.mmctrl2.fa_RNO[5]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66_0\, C => N_1581, - Y => \fault_addr_1[17]\); - - \r.twowner_0_RNIOC1EJ2[0]\ : AO1B - port map(A => twactive_2, B => N_180, C => - \twowner_2_0_a2_0[0]\, Y => N_2497); - - \p0.un207_m_tlb_type_RNI4B8O1_0\ : NOR2 - port map(A => fault_access_0_sqmuxa_0, B => - un207_m_tlb_type_i, Y => \un1_m0_2_1[35]\); - - \r.splt_is2.op.flush_op_RNIL4H81_0\ : OR3A - port map(A => N_2899, B => \s2_tlbstate[0]\, C => flush_op, - Y => \N_66_0\); - - \r.splt_is2.op.flush_op\ : DFN1 - port map(D => flush_op_RNO_3, CLK => lclk_c, Q => flush_op); - - \r.twactive_RNI0KM7C4\ : AO1B - port map(A => \twowner_2_0_a2_0_0[0]\, B => twactive_2, C - => N_2497, Y => twactive_RNI0KM7C4); - - \r.splt_is1.tlbactive_RNO_1\ : NOR2 - port map(A => trans_op, B => \flush\, Y => tlbactive_1_0); - - \r.twowner[0]\ : DFN1 - port map(D => twactive_RNI0KM7C4, CLK => lclk_c, Q => - \twowner[0]\); - - \r.splt_ds1.tlbactive\ : DFN1 - port map(D => N_49, CLK => lclk_c, Q => tlbactive_1); - - \r.mmctrl2.fa[16]\ : DFN1E1 - port map(D => \fault_addr_1[28]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_70); - - \r.mmctrl2.fa[6]\ : DFN1E1 - port map(D => \fault_addr_1[18]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => un1_m0_2_60); - - \r.mmctrl2.fa[14]\ : DFN1E1 - port map(D => \fault_addr_1[26]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_68); - - \p0.un207_m_tlb_type_RNO_0\ : NOR3 - port map(A => fault_mexc, B => fault_inv, C => fault_trans, - Y => un207_m_tlb_type_1); - - \r.mmctrl2.fa_RNO_0[2]\ : MX2C - port map(A => \data[14]\, B => \data_0[14]\, S => - \un1_m0_2_0[35]\, Y => N_1578); - - \r.splt_is1.tlbactive_RNO_0\ : NOR3C - port map(A => \un81_m_tlb_type\, B => tlbactive_1_0, C => - istate_0_sqmuxa, Y => tlbactive_1_2); - - \r.twowner_0[0]\ : DFN1 - port map(D => twactive_RNI0KM7C4, CLK => lclk_c, Q => - \twowner_0[0]\); - - \r.splt_is2.op.flush_op_RNIPFP03\ : NOR2 - port map(A => \un1_m0_2[35]\, B => \N_66\, Y => - \fault_isid_1_i[0]\); - - \r.mmctrl2.fs.ft[0]\ : DFN1E1 - port map(D => \ft_RNO[0]\, CLK => lclk_c, E => fav_0_sqmuxa, - Q => \un1_m0_2[38]\); - - \r.mmctrl2.fa_RNO_0[5]\ : MX2C - port map(A => \data[17]\, B => \data_0[17]\, S => - \un1_m0_2_0[35]\, Y => N_1581); - - \r.twowner_0_RNIU0661[0]\ : NOR3A - port map(A => hrdata_1_0_1(1), B => \twowner_0[0]\, C => - N_2563_i_0_a4_m7_0_a2_1, Y => N_2563_i_0_a4_m7_0_a2_1_0); - - \r.mmctrl2.fs.fav_RNO_0\ : NOR2B - port map(A => \un1_m0_2[37]\, B => fsread_i_0, Y => N_1744); - - \r.mmctrl2.fs.ow\ : DFN1E1 - port map(D => ow_1_sqmuxa, CLK => lclk_c, E => fav_0_sqmuxa, - Q => un1_m0_2_35); - - \r.splt_ds1.op.trans_op\ : DFN1 - port map(D => trans_op_RNIFAOCEQ1, CLK => lclk_c, Q => - trans_op_3); - - \r.mmctrl2.fs.at_su_RNO\ : AO1B - port map(A => \un1_m0_2_1[35]\, B => fault_su_0, C => - N_2490, Y => fault_su_1); - - \r.splt_ds2.tlbactive_RNO_0\ : MX2 - port map(A => tlbactive_0, B => tlbactive_1, S => - s1finished_0_0, Y => N_1755); - - \r.mmctrl2.fs.ft_RNO[0]\ : AOI1 - port map(A => \ft_1_i_a3_0[0]\, B => N_1629, C => - fault_mexc_1, Y => \ft_RNO[0]\); - - \r.splt_is1.op.flush_op_RNO_1\ : OR2A - port map(A => flush_op_2_m6_i_3, B => - mmudci_trans_op_1_sqmuxa_1, Y => flush_op_RNO_1); - - \v.mmctrl2.fs.ow_1_sqmuxa_RNO_0\ : NOR2B - port map(A => \un1_m0_2[42]\, B => ft, Y => ow_1_sqmuxa_0); - - \un1_v.mmctrl2.fs.fav_1_sqmuxa\ : OR2A - port map(A => ft, B => fav_1_sqmuxa_RNO, Y => fav_1_sqmuxa); - - \r.flush_RNO\ : OA1B - port map(A => \flush\, B => flush_1_sqmuxa, C => flush_0_0, - Y => flush_RNO_0); - - \r.twowner_0_RNIC5U6N[0]\ : MX2 - port map(A => d_N_5_1, B => walk_op_2_0_0_o2_0, S => - \twowner_0_RNIK5713[0]\, Y => N_2563_i); - - \r.mmctrl2.fa_RNO_0[6]\ : MX2C - port map(A => \data[18]\, B => \data_0[18]\, S => - \un1_m0_2_0[35]\, Y => N_1582); - - \r.mmctrl2.fs.fav_RNO\ : OR2 - port map(A => fav_0_sqmuxa_0, B => N_1744, Y => fav_RNO); - - \tlbsplit0.itlb0\ : mmutlb_10_8_0_1_0 - port map(address_0(31) => \address[31]\, address_0(30) => - \address[30]\, address_0(29) => \address[29]\, - address_0(28) => \address[28]\, address_0(27) => - \address[27]\, address_0(26) => \address[26]\, - address_0(25) => \address[25]\, address_0(24) => - \address[24]\, address_0(23) => \address[23]\, - address_0(22) => \address[22]\, address_0(21) => - \address[21]\, address_0(20) => \address[20]\, - address_0(19) => \address[19]\, address_0(18) => - \address[18]\, address_0(17) => \address[17]\, - address_0(16) => \address[16]\, address_0(15) => - \address[15]\, address_0(14) => \address[14]\, - address_0(13) => \address[13]\, address_0(12) => - \address[12]\, address_0(11) => \address[11]\, - address_0(10) => \address[10]\, address_0(9) => - \address[9]\, address_0(8) => \address[8]\, address_0(7) - => \address[7]\, address_0(6) => \address[6]\, - address_0(5) => \address[5]\, address_0(4) => - \address[4]\, address_0(3) => \address[3]\, address_0(2) - => \address[2]\, aaddr(31) => \aaddr[31]\, aaddr(30) => - \aaddr[30]\, aaddr(29) => \aaddr[29]\, aaddr(28) => - \aaddr[28]\, aaddr(27) => \aaddr[27]\, aaddr(26) => - \aaddr[26]\, aaddr(25) => \aaddr[25]\, aaddr(24) => - \aaddr[24]\, aaddr(23) => \aaddr[23]\, aaddr(22) => - \aaddr[22]\, aaddr(21) => \aaddr[21]\, aaddr(20) => - \aaddr[20]\, aaddr(19) => \aaddr[19]\, aaddr(18) => - \aaddr[18]\, aaddr(17) => \aaddr[17]\, aaddr(16) => - \aaddr[16]\, aaddr(15) => \aaddr[15]\, aaddr(14) => - \aaddr[14]\, aaddr(13) => \aaddr[13]\, aaddr(12) => - \aaddr[12]\, aaddr(11) => \aaddr[11]\, aaddr(10) => - \aaddr[10]\, aaddr(9) => \aaddr[9]\, aaddr(8) => - \aaddr[8]\, aaddr(7) => \aaddr[7]\, aaddr(6) => - \aaddr[6]\, aaddr(5) => \aaddr[5]\, aaddr(4) => - \aaddr[4]\, aaddr(3) => \aaddr[3]\, aaddr(2) => - \aaddr[2]\, ctx_0(7) => ctx_0(7), ctx_0(6) => ctx_0(6), - ctx_0(5) => ctx_0(5), ctx_0(4) => ctx_0(4), ctx_0(3) => - ctx_0(3), ctx_0(2) => ctx_0(2), ctx_0(1) => ctx_0(1), - ctx_0(0) => ctx_0(0), ctx(7) => ctx(7), ctx(6) => ctx(6), - ctx(5) => ctx(5), ctx(4) => ctx(4), ctx(3) => ctx(3), - ctx(2) => ctx(2), ctx(1) => ctx(1), ctx(0) => ctx(0), - fault_lvl_1 => \fault_lvl_0[1]\, lvl_i_1(1) => - \lvl_i_1[1]\, lvl_i_1(0) => \lvl_i_1[0]\, lvl_i_1_0(1) - => \lvl_i_1_0[1]\, un1_m0_30 => un1_m0_30, un1_m0_9 => - un1_m0_9, un1_m0_8 => un1_m0_8, un1_m0_5 => un1_m0_5, - un1_m0_1 => un1_m0_1, un1_m0_22 => un1_m0_22, un1_m0_6 - => un1_m0_6, un1_m0_0 => un1_m0_0, un1_m0_17 => - un1_m0_17, un1_m0_16 => un1_m0_16, un1_m0_7 => un1_m0_7, - un1_m0_4 => un1_m0_4, un1_m0_3 => un1_m0_3, un1_m0_2 => - un1_m0_2_d0, un1_itlb0_1(41) => \un1_itlb0_1[41]\, - un1_m0_2_0(35) => \un1_m0_2_0[35]\, data_0_29 => - \data[31]\, data_0_27 => \data[29]\, data_0_26 => - \data[28]\, data_0_20 => \data[22]\, data_0_12 => - \data[14]\, address(31) => address_0(31), address(30) => - address_0(30), address(29) => address_0(29), address(28) - => address_0(28), address(27) => address_0(27), - address(26) => address_0(26), address(25) => - address_0(25), address(24) => address_0(24), address(23) - => address_0(23), address(22) => address_0(22), - address(21) => address_0(21), address(20) => - address_0(20), address(19) => address_0(19), address(18) - => address_0(18), address(17) => address_0(17), - address(16) => address_0(16), address(15) => - address_0(15), address(14) => address_0(14), address(13) - => address_0(13), address(12) => address_0(12), - address(11) => address_0(11), address(10) => - address_0(10), address(9) => address_0(9), address(8) => - address_0(8), address(7) => address_0(7), address(6) => - address_0(6), address(5) => address_0(5), address(4) => - address_0(4), address(3) => address_0(3), address(2) => - address_0(2), data_14 => \data[16]\, data_21 => - \data[23]\, data_16 => \data[18]\, data_19 => \data[21]\, - data_17 => \data[19]\, data_15 => \data[17]\, data_24 => - \data[26]\, data_22 => \data[24]\, data_18 => \data[20]\, - data_25 => \data[27]\, data_13 => \data[15]\, data_11 => - \data[13]\, data_10 => \data[12]\, data_23 => \data[25]\, - data_28 => \data[30]\, fault_isid_1_i(0) => - \fault_isid_1_i[0]\, ft_1_i_a2_0(0) => \ft_1_i_a2_0[0]\, - hrdata_0_6 => hrdata_0_7, hrdata_0_25 => hrdata_0_26, - hrdata_0_20 => hrdata_0_21, hrdata_0_17 => hrdata_0_18, - hrdata_0_11 => hrdata_0_12, hrdata_0_23 => hrdata_0_24, - hrdata_0_0 => hrdata_0_1, hrdata_0_16 => hrdata_0_17, - hrdata_0_13 => hrdata_0_14, hrdata_0_15 => hrdata_0_16, - hrdata_0_14 => hrdata_0_15, hrdata_0_12 => hrdata_0_13, - hrdata_0_10 => hrdata_0_11, hrdata_0_9 => hrdata_0_10, - hrdata_0_8 => hrdata_0_9, hrdata_0_7 => hrdata_0_8, - hrdata_0_26 => hrdata_0_27, hrdata_0_22 => hrdata_0_23, - hrdata_0_21 => hrdata_0_22, hrdata_0_1 => hrdata_0_2, - hrdata_0_3 => hrdata_0_4, hrdata_0_2 => hrdata_0_3, - hrdata_9 => hrdata_9, hrdata_10 => hrdata_10, hrdata_11 - => hrdata_11, hrdata_13 => hrdata_13, hrdata_14 => - hrdata_14, hrdata_17 => hrdata_17, hrdata_24 => hrdata_24, - hrdata_6 => hrdata_6, hrdata_0_d0 => hrdata_0_d0, - hrdata_1 => hrdata_1, hrdata_8 => hrdata_8, hrdata_12 => - hrdata_12, hrdata_15 => hrdata_15, hrdata_16 => hrdata_16, - hrdata_18 => hrdata_18, hrdata_21 => hrdata_21, hrdata_22 - => hrdata_22, hrdata_23 => hrdata_23, hrdata_26 => - hrdata_26, hrdata_27 => hrdata_27, hrdata_28 => hrdata_28, - hrdata_29 => hrdata_29, hrdata_30 => hrdata_30, hrdata_31 - => hrdata_31, hrdata_2 => hrdata_2, hrdata_3 => hrdata_3, - hrdata_4 => hrdata_4, hrdata_7 => hrdata_7, hrdata_5 => - hrdata_5, adata_11 => \adata[11]\, adata_31 => - \adata[31]\, adata_30 => \adata[30]\, adata_29 => - \adata[29]\, adata_28 => \adata[28]\, adata_27 => - \adata[27]\, adata_25 => \adata[25]\, adata_24 => - \adata[24]\, adata_23 => \adata[23]\, adata_22 => - \adata[22]\, adata_20 => \adata[20]\, adata_17 => - \adata[17]\, adata_16 => \adata[16]\, adata_15 => - \adata[15]\, adata_14 => \adata[14]\, adata_13 => - \adata[13]\, adata_12 => \adata[12]\, adata_10 => - \adata[10]\, adata_9 => \adata[9]\, adata_8 => \adata[8]\, - adata_7 => \adata[7]\, adata_6 => \adata[6]\, adata_2 => - \adata[2]\, adata_1 => \adata[1]\, adata_0 => \adata[0]\, - adata_18 => \adata[18]\, adata_21 => \adata[21]\, - adata_26 => \adata[26]\, adata_4 => \adata[4]\, adata_3 - => \adata[3]\, adata_19 => \adata[19]\, s2_tlbstate_0 - => \s2_tlbstate[0]\, mmutlb_10_8_0_1_0_VCC => mmu_VCC, - N_264 => N_264, N_262 => N_262, N_78 => N_78, un1_rst_i_0 - => un1_rst_i_0, N_82 => N_82_0, N_80 => N_80, su => su, - N_2625 => N_2625, walk_use => walk_use, flush_op => - flush_op_0, N_2933 => N_2933, tlbactive => tlbactive_2, - N_180 => N_180, walk_op_ur => walk_op_ur, fault_pro_m => - fault_pro_m, fault_pro_1 => fault_pro_1, N_2899 => N_2899, - tlbdis => tlbdis, inv_1_0_a2_0_a2_0 => inv_1_0_a2_0_a2_0, - fault_mexc_2 => fault_mexc_0, fault_trans_i_2 => - fault_trans_i_2, N_264_0 => N_264_0, N_78_0 => N_78_0, - N_3160 => N_3160, N_2571 => N_2571, N_262_0 => N_262_0, - fault_pri_m_0 => fault_pri_m, fault_mexc_0 => fault_mexc, - fault_trans_RNIA0K0D1 => \fault_trans_RNIA0K0D1\, N_429 - => N_429, N_427 => N_427, N_2626 => N_2626, N_43 => N_43, - N_2482 => N_2482, N_423 => N_423, N_425 => N_425, N_2623 - => N_2623, N_2624 => N_2624, N_45 => N_45, N_319 => - N_319, N_321 => N_321, N_361 => N_361, N_363 => N_363, - N_365 => N_365, N_357 => N_357, N_1629 => N_1629, - fault_su => fault_su, twi_areq_ur_1_0_a3_i_0 => - twi_areq_ur_1_0_a3_i_0, fault_mexc_3_2 => fault_mexc_3_2, - fault_mexc_1 => fault_mexc_1, rst => rst, N_359 => N_359, - N_2563_i => N_2563_i, s1finished_0 => s1finished_0, - lclk_c => lclk_c, N_86_i => N_86_i); - - \r.mmctrl2.fa_RNO_0[14]\ : MX2C - port map(A => \data[26]\, B => \data_0[26]\, S => - \un1_m0_2[35]\, Y => N_585); - - \r.mmctrl2.fa[10]\ : DFN1E1 - port map(D => \fault_addr_1[22]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_64); - - \r.splt_ds1.tlbactive_RNIC0BHM3\ : NOR2B - port map(A => un76_m_tlb_type, B => \un2_m_tlb_type\, Y => - flush_1_sqmuxa); - - \r.mmctrl2.fa_RNO_0[15]\ : MX2C - port map(A => \data[27]\, B => \data_0[27]\, S => - \un1_m0_2_0[35]\, Y => N_1591); - - \r.mmctrl2.fs.ft_RNO_0[0]\ : NOR2A - port map(A => fault_pro_1, B => fault_pri_1, Y => - \ft_1_i_a3_0[0]\); - - \r.twowner_0_RNI6J8RK[0]\ : OR3B - port map(A => \twowner_0[0]\, B => areq_ur_1_0_a2_0_0, C - => N_2532, Y => N_2485); - - \r.splt_is1.op.flush_op\ : DFN1 - port map(D => flush_op_RNO, CLK => lclk_c, Q => flush_op_0); - - \r.mmctrl2.fs.ft[2]\ : DFN1E1 - port map(D => \ft_1[2]\, CLK => lclk_c, E => fav_0_sqmuxa, - Q => \un1_m0_2[40]\); - - \r.twowner_RNIB0CLN[0]\ : OR2A - port map(A => walk_op_ur, B => \twowner[0]\, Y => N_2487); - - \r.mmctrl2.fs.l_RNO_0[1]\ : NOR2B - port map(A => walk_use_0, B => \fault_lvl[1]\, Y => N_2575); - - \p0.un207_m_tlb_type_RNI4B8O1_1\ : NOR2 - port map(A => fault_access_0_sqmuxa_0, B => - un207_m_tlb_type_i, Y => \un1_m0_2[35]\); - - \r.twowner_2_RNI86JPN[0]\ : OR3 - port map(A => N_2563_i, B => twi_areq_ur_1_0_a3_i_0, C => - \twowner_2[0]\, Y => N_2484); - - \r.splt_ds1.op.trans_op_RNIA539EQ1\ : MX2A - port map(A => trans_op_3, B => trans_op_2, S => - \un2_m_tlb_type\, Y => trans_op_RNIA539EQ1); - - \r.mmctrl2.fa_RNO_0[0]\ : MX2C - port map(A => \data[12]\, B => \data_0[12]\, S => - \un1_m0_2_0[35]\, Y => N_1576); - - \v.mmctrl2.fs.ow_1_sqmuxa\ : NOR2B - port map(A => ow_1_sqmuxa_1, B => ow_2_sqmuxa_1, Y => - ow_1_sqmuxa); - - \r.splt_is1.tlbactive_RNO\ : OA1A - port map(A => tlbactive_1_2, B => flush_1_sqmuxa, C => rst, - Y => tlbactive_RNO); - - \p0.un76_m_tlb_type\ : NOR2A - port map(A => trans_op_2, B => flush_op_i_0, Y => - un76_m_tlb_type); - - \r.splt_is2.op.flush_op_RNI80SH1\ : OR2 - port map(A => flush_op, B => \un1_m0_2[1]\, Y => - fault_access_0_sqmuxa_0); - - \r.mmctrl2.fs.ft_RNO[2]\ : AO1A - port map(A => fault_mexc_3_2, B => N_1629, C => - fault_mexc_1, Y => \ft_1[2]\); - - \r.mmctrl2.fa_RNO[10]\ : AO1C - port map(A => \un1_m0_2_1[35]\, B => \N_66\, C => N_1586, Y - => \fault_addr_1[22]\); - - \r.mmctrl2.fa[0]\ : DFN1E1 - port map(D => \fault_addr_1[12]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_54); - - \r.splt_ds1.op.flush_op_RNO\ : NOR2B - port map(A => rst, B => N_1757, Y => N_47); - - \r.mmctrl2.fa[12]\ : DFN1E1 - port map(D => \fault_addr_1[24]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_66); - - \r.twowner_0_RNICE2V2[0]\ : NOR2A - port map(A => N_2563_i_0_a4_m7_0_a2_1_0, B => N_207, Y => - N_2563_i_0_a4_m7_0_a2_2); - - \r.mmctrl2.fa_RNO[12]\ : AO1C - port map(A => \un1_m0_2[35]\, B => \N_66\, C => N_583, Y - => \fault_addr_1[24]\); - - \r.mmctrl2.fs.at_id\ : DFN1E1 - port map(D => \fault_isid_1_i[0]\, CLK => lclk_c, E => - fav_0_sqmuxa, Q => \un1_m0_2[42]\); - - \v.mmctrl2.fs.ow_2_sqmuxa_RNIBOO1D1_0\ : NOR2A - port map(A => \fault_trans_RNIA0K0D1\, B => ow_2_sqmuxa, Y - => fav_0_sqmuxa_0); - - \r.mmctrl2.fs.fav\ : DFN1 - port map(D => fav_RNO, CLK => lclk_c, Q => \un1_m0_2[37]\); - - \r.mmctrl2.fa[19]\ : DFN1E1 - port map(D => \fault_addr_1[31]\, CLK => lclk_c, E => - fav_0_sqmuxa_0, Q => un1_m0_2_73); - - \v.mmctrl2.fs.ow_2_sqmuxa\ : AND2 - port map(A => fav_1_sqmuxa, B => ow_2_sqmuxa_1, Y => - ow_2_sqmuxa); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mmu_cache is - - port( hrdata_1_0_1 : in std_logic_vector(1 to 1); - data_2_17 : out std_logic; - data_2_12 : out std_logic; - data_2_1 : out std_logic; - data_1_10 : out std_logic; - data_1_8 : out std_logic; - nbo_5_0 : out std_logic_vector(1 downto 0); - htrans : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - htrans_tz : out std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 2); - hwdata_16 : out std_logic; - hwdata_3 : out std_logic; - hwdata_9 : out std_logic; - hwdata_11 : out std_logic; - hwdata_25 : out std_logic; - hwdata_27 : out std_logic; - hwdata_13 : out std_logic; - hwdata_4 : out std_logic; - hwdata_12 : out std_logic; - hwdata_23 : out std_logic; - hwdata_28 : out std_logic; - hwdata_1 : out std_logic; - hwdata_14 : out std_logic; - hwdata_0 : out std_logic; - hwdata_15 : out std_logic; - iosn_1 : in std_logic_vector(93 to 93); - hsize_5 : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(0 to 0); - hresp : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - addr_28 : out std_logic; - address_1 : out std_logic; - address_0 : out std_logic; - dataout : in std_logic_vector(35 downto 0); - data_0_0_31 : out std_logic; - data_0_0_24 : out std_logic; - data_0_0_29 : out std_logic; - data_0_0_13 : out std_logic; - data_0_0_30 : out std_logic; - data_0_0_27 : out std_logic; - data_0_0_20 : out std_logic; - data_0_0_14 : out std_logic; - data_0_0_25 : out std_logic; - data_0_0_16 : out std_logic; - data_0_0_17 : out std_logic; - data_0_0_28 : out std_logic; - data_0_0_8 : out std_logic; - data_0_0_11 : out std_logic; - data_0_0_21 : out std_logic; - data_0_0_4 : out std_logic; - data_0_0_26 : out std_logic; - data_0_0_0 : out std_logic; - data_0_0_12 : out std_logic; - data_0_0_15 : out std_logic; - data_0_0_7 : out std_logic; - mcdo_m_0_29 : out std_logic; - mcdo_m_0_22 : out std_logic; - mcdo_m_0_27 : out std_logic; - mcdo_m_0_0 : out std_logic; - mcdo_m_0_16 : out std_logic; - mcdo_m_0_21 : out std_logic; - mcdo_m_0_20 : out std_logic; - mcdo_m_0_17 : out std_logic; - mcdo_m_0_4 : out std_logic; - mcdo_m_0_7 : out std_logic; - rdatav_0_1_0_iv_4_22 : out std_logic; - rdatav_0_1_0_iv_4_20 : out std_logic; - rdatav_0_1_0_iv_4_0 : out std_logic; - rdatav_0_1_0_iv_4_14 : out std_logic; - rdatav_0_1_0_iv_5_6 : out std_logic; - rdatav_0_1_0_iv_5_1 : out std_logic; - rdatav_0_1_0_iv_5_0 : out std_logic; - rdatav_0_1_0_iv_5_4 : out std_logic; - eaddress_29 : in std_logic; - eaddress_22 : in std_logic; - eaddress_21 : in std_logic; - eaddress_13 : in std_logic; - eaddress_28 : in std_logic; - eaddress_18 : in std_logic; - eaddress_6 : in std_logic; - eaddress_10 : in std_logic; - eaddress_25 : in std_logic; - eaddress_23 : in std_logic; - eaddress_19 : in std_logic; - eaddress_9 : in std_logic; - eaddress_17 : in std_logic; - eaddress_27 : in std_logic; - eaddress_15 : in std_logic; - eaddress_5 : in std_logic; - eaddress_20 : in std_logic; - eaddress_2 : in std_logic; - eaddress_24 : in std_logic; - eaddress_16 : in std_logic; - eaddress_12 : in std_logic; - eaddress_4 : in std_logic; - eaddress_1 : in std_logic; - eaddress_8 : in std_logic; - eaddress_0 : in std_logic; - eaddress_3 : in std_logic; - eaddress_7 : in std_logic; - asi_4 : in std_logic; - asi_3 : in std_logic; - asi_2 : in std_logic; - asi_1 : in std_logic; - asi_0 : in std_logic_vector(0 to 0); - rdatav_0_1_0_iv_7 : out std_logic_vector(2 to 2); - rdatav_0_1_0_iv_0_2 : out std_logic_vector(10 to 10); - rdatav_0_1_1_iv_7 : out std_logic_vector(6 to 6); - edata2_0_iv : in std_logic_vector(23 downto 0); - newtag_1_0 : out std_logic_vector(27 downto 24); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dco_i_2 : out std_logic_vector(132 to 132); - size_0 : in std_logic_vector(1 downto 0); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 downto 24); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - faddr_RNI7879K : out std_logic_vector(0 to 0); - dci_m_0 : out std_logic; - dci_m_1 : out std_logic; - dci_m_2 : out std_logic; - dci_m_3 : out std_logic; - dci_m_5 : out std_logic; - dci_m_6 : out std_logic; - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - size_0_d0 : out std_logic; - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - data_10 : out std_logic; - data_8 : out std_logic; - data_5 : out std_logic; - data_13 : out std_logic; - data_24 : out std_logic; - data_29 : out std_logic; - un1_p0_2_0_350 : out std_logic; - un1_p0_2_0_0 : out std_logic; - fpc : in std_logic_vector(31 downto 2); - dataout_2 : in std_logic_vector(31 downto 0); - maddress : in std_logic_vector(31 downto 0); - un1_p0_6 : in std_logic_vector(0 to 0); - dataout_0 : in std_logic_vector(35 downto 0); - dataout_1 : in std_logic_vector(31 downto 0); - vitdatain_0_1_0 : in std_logic_vector(22 to 22); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - istate_RNIA8N5H : out std_logic_vector(0 to 0); - hrdata_0_15 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_3 : in std_logic; - data_0 : out std_logic_vector(31 downto 0); - rpc_0 : in std_logic; - rpc_1 : in std_logic; - rpc_3 : in std_logic; - rpc_2 : in std_logic; - rpc_7 : in std_logic; - rpc_8 : in std_logic; - rpc_5 : in std_logic; - rpc_6 : in std_logic; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - hrdata_9 : in std_logic; - hrdata_10 : in std_logic; - hrdata_11 : in std_logic; - hrdata_13 : in std_logic; - hrdata_14 : in std_logic; - hrdata_17 : in std_logic; - hrdata_24 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_8 : in std_logic; - hrdata_12 : in std_logic; - hrdata_15 : in std_logic; - hrdata_16 : in std_logic; - hrdata_18 : in std_logic; - hrdata_21 : in std_logic; - hrdata_22 : in std_logic; - hrdata_23 : in std_logic; - hrdata_26 : in std_logic; - hrdata_27 : in std_logic; - hrdata_2 : in std_logic; - hrdata_3 : in std_logic; - hrdata_4 : in std_logic; - hrdata_7 : in std_logic; - hrdata_5 : in std_logic; - hrdata_6 : in std_logic; - hrdata_28 : in std_logic; - hrdata_29 : in std_logic; - hrdata_30 : in std_logic; - hrdata_31 : in std_logic; - istate_RNIPSU8G : out std_logic_vector(0 to 0); - maddress_0_0 : in std_logic; - maddress_0_2 : in std_logic; - istate_RNIEC82C : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNI5V68H : out std_logic_vector(0 to 0); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - istate_RNIH0NBI : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - istate_RNI57KLB : out std_logic_vector(0 to 0); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - istate_RNI6HPAI : out std_logic_vector(0 to 0); - ctx : out std_logic_vector(7 downto 0); - un1_p0_2_i_0 : out std_logic; - un1_p0_2_i_4 : out std_logic; - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - istate_RNIJCMP6 : out std_logic_vector(0 to 0); - N_546 : in std_logic; - mmu_cache_VCC : in std_logic; - N_264 : in std_logic; - N_262 : in std_logic; - N_78 : in std_logic; - bo_5842_d_0 : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - hlock : out std_logic; - N_5054 : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - hbusreq : out std_logic; - un60_nbo : out std_logic; - N_457 : out std_logic; - N_462 : out std_logic; - N_467 : out std_logic; - werr_2_m_0 : out std_logic; - un91_nbo_i_0 : out std_logic; - N_138 : out std_logic; - N_139 : out std_logic; - bo_5842_d : out std_logic; - N_458 : out std_logic; - N_459 : out std_logic; - N_461 : out std_logic; - N_463 : out std_logic; - N_468 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_466 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - werr : out std_logic; - N_3254_0 : out std_logic; - enaddr : in std_logic; - lock_0 : in std_logic; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : out std_logic; - un1_addout_12 : in std_logic; - read_0_0 : in std_logic; - nullify : in std_logic; - intack : in std_logic; - nullify2_0_sqmuxa : in std_logic; - me_nullify2_1_2 : in std_logic; - un17_casaen_0_0 : in std_logic; - N_330 : out std_logic; - N_329 : out std_logic; - N_24 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - N_16_i_0 : out std_logic; - N_12_i_0 : out std_logic; - read_RNIEEGDD1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNICAQK41 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNIC9O9B1 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIEKS231 : out std_logic; - N_26_0 : out std_logic; - N_3387_i_0 : out std_logic; - N_3227_i_0 : out std_logic; - N_3239_i_0 : out std_logic; - mexc_1 : out std_logic; - un59_nbo : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - read_RNICKHE91 : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI0IQ7R : out std_logic; - N_3389_i_0 : out std_logic; - read_RNIRO4K31 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIQH64D1 : out std_logic; - read_1 : in std_logic; - r_N_6 : in std_logic; - N_3305 : out std_logic; - N_3846 : out std_logic; - N_144 : out std_logic; - N_258 : out std_logic; - N_259 : out std_logic; - N_267 : out std_logic; - N_269 : out std_logic; - N_270 : out std_logic; - flush_RNIGBB873 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - msu : in std_logic; - eenaddr : in std_logic; - write : in std_logic; - N_10 : out std_logic; - lclk_c : in std_logic; - holdn : out std_logic; - rst : in std_logic; - flush_i_0 : in std_logic; - hold_pc_7 : in std_logic; - de_hold_pc_1 : in std_logic; - un1_ici : out std_logic; - xc_exception_1_0 : in std_logic; - ldlock_2 : in std_logic; - un9_icc_check_bp : in std_logic; - ldlock_3_0 : in std_logic; - inull : in std_logic; - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - N_982 : out std_logic; - N_983 : out std_logic; - N_985 : out std_logic; - N_981 : out std_logic; - mds : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNI146O2 : out std_logic; - N_26 : in std_logic; - flush2 : out std_logic; - N_986 : out std_logic; - N_987 : out std_logic; - N_28 : in std_logic; - N_980 : out std_logic; - N_984 : out std_logic; - flush2_RNI5I3N7 : out std_logic; - flush2_RNIFMGM2 : out std_logic; - rbranch : in std_logic; - fbranch : in std_logic; - mexc : out std_logic; - su : in std_logic - ); - -end mmu_cache; - -architecture DEF_ARCH of mmu_cache is - - component VCC - port( Y : out std_logic - ); - end component; - - component mmu_dcache - port( data_1_19 : out std_logic; - data_1_18 : out std_logic; - data_1_17 : out std_logic; - data_1_16 : out std_logic; - data_1_15 : out std_logic; - data_1_14 : out std_logic; - data_1_13 : out std_logic; - data_1_12 : out std_logic; - data_1_9 : out std_logic; - data_1_8 : out std_logic; - data_1_5 : out std_logic; - data_1_4 : out std_logic; - data_1_3 : out std_logic; - data_1_2 : out std_logic; - data_1_1 : out std_logic; - data_1_0 : out std_logic; - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - size_1 : out std_logic_vector(1 downto 0); - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - dci_m_94 : out std_logic; - dci_m_93 : out std_logic; - dci_m_91 : out std_logic; - dci_m_90 : out std_logic; - dci_m_89 : out std_logic; - dci_m_88 : out std_logic; - faddr_RNI7879K : out std_logic_vector(0 to 0); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 downto 24) := (others => 'U'); - ctx : out std_logic_vector(7 downto 0); - hrdata_0_d0 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_25 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - size_0_0 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - dco_i_2 : out std_logic_vector(132 to 132); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - newtag_1_0_9 : out std_logic; - newtag_1_0_8 : out std_logic; - newtag_1_0_7 : out std_logic; - newtag_1_0_6 : out std_logic; - edata2_0_iv : in std_logic_vector(23 downto 0) := (others => 'U'); - asi_0_0 : out std_logic; - dataout_1 : in std_logic_vector(11 downto 10) := (others => 'U'); - size_1_d0 : in std_logic := 'U'; - bo_d : in std_logic_vector(2 to 2) := (others => 'U'); - rdatav_0_1_1_iv_7 : out std_logic_vector(6 to 6); - rdatav_0_1_0_iv_0_2_0 : out std_logic; - rdatav_0_1_0_iv_7_2 : out std_logic; - un1_m0_2_0 : in std_logic_vector(35 to 35) := (others => 'U'); - ics : out std_logic_vector(1 downto 0); - maddress_0_2 : in std_logic := 'U'; - maddress_0_0 : in std_logic := 'U'; - asi : in std_logic_vector(4 downto 0) := (others => 'U'); - data : out std_logic_vector(31 downto 0); - LVL_RNIT69H911 : in std_logic_vector(0 to 0) := (others => 'U'); - data_1_3_i_a3_6_2 : in std_logic := 'U'; - data_1_3_i_a3_6_4 : in std_logic := 'U'; - data_1_3_i_a3_6_0 : in std_logic := 'U'; - data_1_3_i_a3_6_1 : in std_logic := 'U'; - data_RNIKU1T4 : in std_logic_vector(16 to 16) := (others => 'U'); - un1_m0_2_73 : in std_logic := 'U'; - un1_m0_2_2 : in std_logic := 'U'; - un1_m0_2_4 : in std_logic := 'U'; - un1_m0_2_10 : in std_logic := 'U'; - un1_m0_2_9 : in std_logic := 'U'; - un1_m0_2_40 : in std_logic := 'U'; - un1_m0_2_5 : in std_logic := 'U'; - un1_m0_2_1 : in std_logic := 'U'; - un1_m0_2_7 : in std_logic := 'U'; - un1_m0_2_68 : in std_logic := 'U'; - un1_m0_2_38 : in std_logic := 'U'; - un1_m0_2_42 : in std_logic := 'U'; - un1_m0_2_59 : in std_logic := 'U'; - un1_m0_2_58 : in std_logic := 'U'; - un1_m0_2_67 : in std_logic := 'U'; - un1_m0_2_43 : in std_logic := 'U'; - un1_m0_2_65 : in std_logic := 'U'; - un1_m0_2_77 : out std_logic; - un1_m0_2_34 : in std_logic := 'U'; - un1_m0_2_78 : out std_logic; - un1_m0_2_75 : out std_logic; - un1_m0_2_6 : in std_logic := 'U'; - un1_m0_2_29 : in std_logic := 'U'; - un1_m0_2_19 : in std_logic := 'U'; - un1_m0_2_23 : in std_logic := 'U'; - un1_m0_2_60 : in std_logic := 'U'; - un1_m0_2_79 : out std_logic; - un1_m0_2_80 : out std_logic; - un1_m0_2_81 : out std_logic; - un1_m0_2_84 : out std_logic; - un1_m0_2_83 : out std_logic; - un1_m0_2_86 : out std_logic; - un1_m0_2_76 : out std_logic; - un1_m0_2_15 : in std_logic := 'U'; - un1_m0_2_11 : in std_logic := 'U'; - un1_m0_2_18 : in std_logic := 'U'; - un1_m0_2_85 : out std_logic; - un1_m0_2_54 : in std_logic := 'U'; - un1_m0_2_71 : in std_logic := 'U'; - un1_m0_2_55 : in std_logic := 'U'; - un1_m0_2_70 : in std_logic := 'U'; - un1_m0_2_61 : in std_logic := 'U'; - un1_m0_2_69 : in std_logic := 'U'; - un1_m0_2_37 : in std_logic := 'U'; - un1_m0_2_66 : in std_logic := 'U'; - un1_m0_2_56 : in std_logic := 'U'; - un1_m0_2_64 : in std_logic := 'U'; - un1_m0_2_62 : in std_logic := 'U'; - un1_m0_2_57 : in std_logic := 'U'; - un1_m0_2_41 : in std_logic := 'U'; - un1_m0_2_94 : in std_logic := 'U'; - un1_m0_2_91 : in std_logic := 'U'; - un1_m0_2_106 : in std_logic := 'U'; - un1_m0_2_96 : in std_logic := 'U'; - un1_m0_2_92 : in std_logic := 'U'; - un1_m0_2_95 : in std_logic := 'U'; - un1_m0_2_97 : in std_logic := 'U'; - un1_m0_2_93 : in std_logic := 'U'; - un1_m0_2_98 : in std_logic := 'U'; - un1_m0_2_33 : in std_logic := 'U'; - un1_m0_2_72 : in std_logic := 'U'; - un1_m0_2_39 : in std_logic := 'U'; - un1_m0_2_63 : in std_logic := 'U'; - un1_m0_2_44 : in std_logic := 'U'; - un1_m0_2_35 : in std_logic := 'U'; - un1_m0_2_36 : in std_logic := 'U'; - un1_m0_2_0_d0 : in std_logic := 'U'; - un1_m0_2_3 : in std_logic := 'U'; - un1_m0_2_12 : in std_logic := 'U'; - un1_m0_2_82 : out std_logic; - un1_m0_2_8 : in std_logic := 'U'; - un1_m0_2_31 : in std_logic := 'U'; - un1_m0_2_108 : in std_logic := 'U'; - eaddress_7 : in std_logic := 'U'; - eaddress_3 : in std_logic := 'U'; - eaddress_0 : in std_logic := 'U'; - eaddress_8 : in std_logic := 'U'; - eaddress_1 : in std_logic := 'U'; - eaddress_4 : in std_logic := 'U'; - eaddress_12 : in std_logic := 'U'; - eaddress_16 : in std_logic := 'U'; - eaddress_24 : in std_logic := 'U'; - eaddress_2 : in std_logic := 'U'; - eaddress_20 : in std_logic := 'U'; - eaddress_5 : in std_logic := 'U'; - eaddress_15 : in std_logic := 'U'; - eaddress_27 : in std_logic := 'U'; - eaddress_17 : in std_logic := 'U'; - eaddress_9 : in std_logic := 'U'; - eaddress_19 : in std_logic := 'U'; - eaddress_23 : in std_logic := 'U'; - eaddress_25 : in std_logic := 'U'; - eaddress_10 : in std_logic := 'U'; - eaddress_6 : in std_logic := 'U'; - eaddress_18 : in std_logic := 'U'; - eaddress_28 : in std_logic := 'U'; - eaddress_13 : in std_logic := 'U'; - eaddress_21 : in std_logic := 'U'; - eaddress_22 : in std_logic := 'U'; - eaddress_29 : in std_logic := 'U'; - rdatav_0_1_0_iv_5_18 : out std_logic; - rdatav_0_1_0_iv_5_14 : out std_logic; - rdatav_0_1_0_iv_5_15 : out std_logic; - rdatav_0_1_0_iv_5_20 : out std_logic; - rdatav_0_1_0_iv_4_23 : out std_logic; - rdatav_0_1_0_iv_4_9 : out std_logic; - rdatav_0_1_0_iv_4_29 : out std_logic; - rdatav_0_1_0_iv_4_31 : out std_logic; - mcdo_m_0_8 : out std_logic; - mcdo_m_0_5 : out std_logic; - mcdo_m_0_18 : out std_logic; - mcdo_m_0_21 : out std_logic; - mcdo_m_0_22 : out std_logic; - mcdo_m_0_17 : out std_logic; - mcdo_m_0_1 : out std_logic; - mcdo_m_0_28 : out std_logic; - mcdo_m_0_23 : out std_logic; - mcdo_m_0_30 : out std_logic; - data_0_23 : out std_logic; - data_0_22 : out std_logic; - data_0_19 : out std_logic; - data_0_18 : out std_logic; - data_0_7 : out std_logic; - data_0_15 : out std_logic; - data_0_12 : out std_logic; - data_0_0 : out std_logic; - data_0_26 : out std_logic; - data_0_4 : out std_logic; - data_0_21 : out std_logic; - data_0_11 : out std_logic; - data_0_8 : out std_logic; - data_0_28 : out std_logic; - data_0_17 : out std_logic; - data_0_16 : out std_logic; - data_0_25 : out std_logic; - data_0_14 : out std_logic; - data_0_20 : out std_logic; - data_0_27 : out std_logic; - data_0_30 : out std_logic; - data_0_13 : out std_logic; - data_0_29 : out std_logic; - data_0_24 : out std_logic; - data_0_31 : out std_logic; - dataout : in std_logic_vector(35 downto 0) := (others => 'U'); - ctxp_13 : out std_logic; - ctxp_16 : out std_logic; - ctxp_7 : out std_logic; - ctxp_10 : out std_logic; - ctxp_3 : out std_logic; - ctxp_8 : out std_logic; - ctxp_19 : out std_logic; - ctxp_17 : out std_logic; - ctxp_15 : out std_logic; - ctxp_14 : out std_logic; - ctxp_20 : out std_logic; - ctxp_18 : out std_logic; - ctxp_6 : out std_logic; - ctxp_21 : out std_logic; - ctxp_11 : out std_logic; - ctxp_4 : out std_logic; - ctxp_25 : out std_logic; - ctxp_0 : out std_logic; - ctxp_22 : out std_logic; - ctxp_23 : out std_logic; - ctxp_24 : out std_logic; - ctxp_5 : out std_logic; - ctxp_12 : out std_logic; - ctxp_9 : out std_logic; - ctxp_1 : out std_logic; - ctxp_2 : out std_logic; - diagdata_6 : in std_logic := 'U'; - diagdata_7 : in std_logic := 'U'; - diagdata_1 : in std_logic := 'U'; - diagdata_3 : in std_logic := 'U'; - diagdata_5 : in std_logic := 'U'; - diagdata_29 : in std_logic := 'U'; - diagdata_22 : in std_logic := 'U'; - diagdata_27 : in std_logic := 'U'; - diagdata_20 : in std_logic := 'U'; - diagdata_8 : in std_logic := 'U'; - diagdata_25 : in std_logic := 'U'; - diagdata_18 : in std_logic := 'U'; - diagdata_31 : in std_logic := 'U'; - diagdata_17 : in std_logic := 'U'; - diagdata_24 : in std_logic := 'U'; - diagdata_23 : in std_logic := 'U'; - diagdata_21 : in std_logic := 'U'; - diagdata_16 : in std_logic := 'U'; - diagdata_12 : in std_logic := 'U'; - diagdata_9 : in std_logic := 'U'; - diagdata_26 : in std_logic := 'U'; - diagdata_0 : in std_logic := 'U'; - diagdata_19 : in std_logic := 'U'; - diagdata_14 : in std_logic := 'U'; - diagdata_15 : in std_logic := 'U'; - diagdata_2 : in std_logic := 'U'; - diagdata_13 : in std_logic := 'U'; - diagdata_30 : in std_logic := 'U'; - diagdata_4 : in std_logic := 'U'; - diagdata_28 : in std_logic := 'U'; - address : out std_logic_vector(31 downto 0); - addr_30 : out std_logic; - addr_11 : out std_logic; - addr_6 : out std_logic; - addr_4 : out std_logic; - addr_7 : out std_logic; - addr_5 : out std_logic; - addr_3 : out std_logic; - addr_8 : out std_logic; - addr_10 : out std_logic; - addr_9 : out std_logic; - addr_2 : out std_logic; - dataout_0 : in std_logic_vector(31 downto 0) := (others => 'U'); - maddress : in std_logic_vector(31 downto 0) := (others => 'U'); - un1_p0_2_0 : out std_logic_vector(498 to 498); - ctx_0 : out std_logic_vector(7 downto 0); - size_1z : out std_logic; - enable : out std_logic; - N_10 : out std_logic; - write : in std_logic := 'U'; - eenaddr : in std_logic := 'U'; - msu : in std_logic := 'U'; - su : out std_logic; - read_3 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - N_415 : in std_logic := 'U'; - N_351 : in std_logic := 'U'; - flush_RNIGBB873 : out std_logic; - N_192 : in std_logic := 'U'; - N_190_0 : in std_logic := 'U'; - diagrdy : in std_logic := 'U'; - burst_0 : out std_logic; - N_264_0 : in std_logic := 'U'; - N_425 : out std_logic; - trans_op_0 : out std_logic; - flush_op_i_0 : out std_logic; - trans_op : out std_logic; - un2_m_tlb_type : in std_logic := 'U'; - tlbdis : out std_logic; - read_2 : out std_logic; - grant : in std_logic := 'U'; - N_317_0 : in std_logic := 'U'; - N_2886 : in std_logic := 'U'; - N_2887 : in std_logic := 'U'; - N_270 : out std_logic; - N_269 : out std_logic; - N_267 : out std_logic; - N_353 : in std_logic := 'U'; - N_259 : out std_logic; - N_258 : out std_logic; - N_236_0 : in std_logic := 'U'; - N_417 : in std_logic := 'U'; - N_144 : out std_logic; - N_3846 : out std_logic; - e : out std_logic; - N_421_0 : in std_logic := 'U'; - N_3305 : out std_logic; - nf : out std_logic; - N_262_0 : in std_logic := 'U'; - un54_fault_pro_m : in std_logic := 'U'; - M_m : in std_logic := 'U'; - r_N_6 : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_2 : out std_logic; - fault_pro : in std_logic := 'U'; - stpend_RNI6P41NG3 : out std_logic; - read_1 : in std_logic := 'U'; - read_RNIQH64D1 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIRO4K31 : out std_logic; - N_3389_i_0 : out std_logic; - read_RNI0IQ7R : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNICKHE91 : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - un59_nbo : in std_logic := 'U'; - lock_m : out std_logic; - N_2699_i_0 : in std_logic := 'U'; - mexc_1 : out std_logic; - N_3239_i_0 : out std_logic; - N_2701 : in std_logic := 'U'; - N_2703_i_0 : in std_logic := 'U'; - N_2714 : in std_logic := 'U'; - N_3227_i_0 : out std_logic; - N_3387_i_0 : out std_logic; - N_26 : out std_logic; - read_RNIEKS231 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIC9O9B1 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNICAQK41 : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIEEGDD1 : out std_logic; - N_12_i_0 : out std_logic; - N_16_i_0 : out std_logic; - N_696 : in std_logic := 'U'; - N_695 : in std_logic := 'U'; - flush_0_1_RNIBUA27S2 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - N_2702_i_0 : in std_logic := 'U'; - N_2717 : in std_logic := 'U'; - N_2720 : in std_logic := 'U'; - N_694 : in std_logic := 'U'; - N_2711_i_0 : in std_logic := 'U'; - fsread_i_0 : out std_logic; - N_24 : out std_logic; - N_329 : out std_logic; - N_330 : out std_logic; - N_78_0 : in std_logic := 'U'; - ba : in std_logic := 'U'; - hcache : in std_logic := 'U'; - cache : out std_logic; - cdwrite_0_sqmuxa_i_0_0 : in std_logic := 'U'; - lock_0 : out std_logic; - un17_casaen_0_0 : in std_logic := 'U'; - mexc : in std_logic := 'U'; - me_nullify2_1_2 : in std_logic := 'U'; - nullify2_0_sqmuxa : in std_logic := 'U'; - flush : in std_logic := 'U'; - hold_0 : in std_logic := 'U'; - fault_pro67 : in std_logic := 'U'; - req : out std_logic; - intack : in std_logic := 'U'; - N_523 : out std_logic; - fault_pri : in std_logic := 'U'; - iflush_1_0_a2_0 : out std_logic; - N_419 : in std_logic := 'U'; - N_2709_i_0 : in std_logic := 'U'; - nullify : in std_logic := 'U'; - flush_i_0 : in std_logic := 'U'; - N_293 : in std_logic := 'U'; - read_0 : in std_logic := 'U'; - rst : in std_logic := 'U'; - burst : out std_logic; - accexc_6 : in std_logic := 'U'; - un1_addout_12 : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : out std_logic; - G_80_0 : in std_logic := 'U'; - lock : in std_logic := 'U'; - ready : in std_logic := 'U'; - mmudci_trans_op_1_sqmuxa_1 : out std_logic; - hold : out std_logic; - enaddr : in std_logic := 'U'; - N_425_0 : out std_logic; - N_121 : out std_logic; - N_3254_0 : out std_logic; - e_0 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component mmu_acache - port( iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - hgrant : in std_logic_vector(0 to 0) := (others => 'U'); - hsize_5 : out std_logic_vector(1 to 1); - size : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - data_0_18 : in std_logic := 'U'; - data_0_1 : in std_logic := 'U'; - data_0_3 : in std_logic := 'U'; - data_0_17 : in std_logic := 'U'; - data_0_22 : in std_logic := 'U'; - data_0_21 : in std_logic := 'U'; - data_0_9 : in std_logic := 'U'; - data_0_23 : in std_logic := 'U'; - data_0_20 : in std_logic := 'U'; - data_0_4 : in std_logic := 'U'; - data_0_31 : in std_logic := 'U'; - data_0_26 : in std_logic := 'U'; - data_0_15 : in std_logic := 'U'; - data_0_7 : in std_logic := 'U'; - data_0_27 : in std_logic := 'U'; - data_0_25 : in std_logic := 'U'; - data_0_16 : in std_logic := 'U'; - data_0_30 : in std_logic := 'U'; - data_0_28 : in std_logic := 'U'; - data_0_14 : in std_logic := 'U'; - data_0_2 : in std_logic := 'U'; - data_0_11 : in std_logic := 'U'; - data_0_0 : in std_logic := 'U'; - data_0_12 : in std_logic := 'U'; - data_0_6 : in std_logic := 'U'; - data_0_19 : in std_logic := 'U'; - data_18 : in std_logic := 'U'; - data_1 : in std_logic := 'U'; - data_3 : in std_logic := 'U'; - data_17 : in std_logic := 'U'; - data_22 : in std_logic := 'U'; - data_21 : in std_logic := 'U'; - data_9 : in std_logic := 'U'; - data_23 : in std_logic := 'U'; - data_20 : in std_logic := 'U'; - data_4 : in std_logic := 'U'; - data_31 : in std_logic := 'U'; - data_26 : in std_logic := 'U'; - data_15 : in std_logic := 'U'; - data_7 : in std_logic := 'U'; - data_27 : in std_logic := 'U'; - data_25 : in std_logic := 'U'; - data_16 : in std_logic := 'U'; - data_30 : in std_logic := 'U'; - data_28 : in std_logic := 'U'; - data_14 : in std_logic := 'U'; - data_2 : in std_logic := 'U'; - data_11 : in std_logic := 'U'; - data_0_d0 : in std_logic := 'U'; - data_12 : in std_logic := 'U'; - data_6 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - hwdata_15 : out std_logic; - hwdata_0 : out std_logic; - hwdata_14 : out std_logic; - hwdata_1 : out std_logic; - hwdata_28 : out std_logic; - hwdata_23 : out std_logic; - hwdata_12 : out std_logic; - hwdata_4 : out std_logic; - hwdata_13 : out std_logic; - hwdata_27 : out std_logic; - hwdata_25 : out std_logic; - hwdata_11 : out std_logic; - hwdata_9 : out std_logic; - hwdata_3 : out std_logic; - hwdata_16 : out std_logic; - address_1 : in std_logic_vector(31 downto 2) := (others => 'U'); - haddr : out std_logic_vector(31 downto 2); - address_0 : in std_logic_vector(31 downto 2) := (others => 'U'); - htrans_tz : out std_logic_vector(1 to 1); - bo_d : out std_logic_vector(3 downto 2); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - address : in std_logic_vector(31 downto 2) := (others => 'U'); - htrans : out std_logic_vector(1 to 1); - nbo_5_0 : out std_logic_vector(1 downto 0); - size_1z : in std_logic := 'U'; - werr : out std_logic; - lclk_c : in std_logic := 'U'; - ready_0 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - mexc_1 : out std_logic; - ready : out std_logic; - N_466 : out std_logic; - lock : in std_logic := 'U'; - lock_m : in std_logic := 'U'; - hwrite_1_m_0 : out std_logic; - N_468 : out std_logic; - N_463 : out std_logic; - N_461 : out std_logic; - N_459 : out std_logic; - N_458 : out std_logic; - bo_5842_d : out std_logic; - N_139 : out std_logic; - N_138 : out std_logic; - un91_nbo_i_0 : out std_logic; - grant_1 : out std_logic; - hcache_1 : out std_logic; - werr_2_m_0 : out std_logic; - N_467 : out std_logic; - N_462 : out std_logic; - N_457 : out std_logic; - mexc_0 : out std_logic; - read_0 : in std_logic := 'U'; - mexc : out std_logic; - un60_nbo : out std_logic; - hbusreq : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - N_5054 : out std_logic; - burst_0 : in std_logic := 'U'; - hlock : out std_logic; - un59_nbo : out std_logic; - ba : out std_logic; - cache : in std_logic := 'U'; - read : in std_logic := 'U'; - burst : in std_logic := 'U'; - req_1 : in std_logic := 'U'; - req_0 : in std_logic := 'U'; - req : in std_logic := 'U'; - N_6093_i : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - grant_0 : out std_logic; - grant : out std_logic; - rst : in std_logic := 'U'; - bo_5842_d_0 : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component mmu_icache - port( istate_RNIJCMP6 : out std_logic_vector(0 to 0); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - ics : in std_logic_vector(1 downto 0) := (others => 'U'); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - un1_p0_2_i_4 : out std_logic; - un1_p0_2_i_0 : out std_logic; - ctx_5 : in std_logic := 'U'; - ctx_4 : in std_logic := 'U'; - ctx_3 : in std_logic := 'U'; - ctx_1 : in std_logic := 'U'; - ctx_0_d0 : in std_logic := 'U'; - istate_RNI6HPAI : out std_logic_vector(0 to 0); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - istate_RNI57KLB : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - un1_m0_30 : in std_logic := 'U'; - un1_m0_5 : in std_logic := 'U'; - un1_m0_9 : in std_logic := 'U'; - un1_m0_8 : in std_logic := 'U'; - un1_m0_1 : in std_logic := 'U'; - un1_m0_22 : in std_logic := 'U'; - un1_m0_6 : in std_logic := 'U'; - un1_m0_0 : in std_logic := 'U'; - un1_m0_17 : in std_logic := 'U'; - un1_m0_16 : in std_logic := 'U'; - un1_m0_7 : in std_logic := 'U'; - un1_m0_4 : in std_logic := 'U'; - un1_m0_2 : in std_logic := 'U'; - un1_m0_3 : in std_logic := 'U'; - istate_RNIH0NBI : out std_logic_vector(0 to 0); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - istate_RNI5V68H : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIEC82C : out std_logic_vector(0 to 0); - maddress_0_2 : in std_logic := 'U'; - maddress_0_0 : in std_logic := 'U'; - istate_RNIPSU8G : out std_logic_vector(0 to 0); - diagdata_6 : out std_logic; - diagdata_15 : out std_logic; - diagdata_4 : out std_logic; - diagdata_19 : out std_logic; - diagdata_18 : out std_logic; - diagdata_17 : out std_logic; - diagdata_16 : out std_logic; - diagdata_20 : out std_logic; - diagdata_26 : out std_logic; - diagdata_25 : out std_logic; - diagdata_22 : out std_logic; - diagdata_14 : out std_logic; - diagdata_12 : out std_logic; - diagdata_9 : out std_logic; - diagdata_8 : out std_logic; - diagdata_5 : out std_logic; - diagdata_3 : out std_logic; - diagdata_0 : out std_logic; - diagdata_7 : out std_logic; - diagdata_27 : out std_logic; - diagdata_23 : out std_logic; - diagdata_24 : out std_logic; - diagdata_31 : out std_logic; - diagdata_29 : out std_logic; - diagdata_28 : out std_logic; - diagdata_21 : out std_logic; - diagdata_13 : out std_logic; - diagdata_2 : out std_logic; - diagdata_30 : out std_logic; - diagdata_1 : out std_logic; - hrdata_26 : in std_logic := 'U'; - hrdata_25 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - rpc_6 : in std_logic := 'U'; - rpc_5 : in std_logic := 'U'; - rpc_8 : in std_logic := 'U'; - rpc_7 : in std_logic := 'U'; - rpc_2 : in std_logic := 'U'; - rpc_3 : in std_logic := 'U'; - rpc_1 : in std_logic := 'U'; - rpc_0 : in std_logic := 'U'; - addr : in std_logic_vector(11 downto 2) := (others => 'U'); - data_0 : out std_logic_vector(31 downto 0); - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - istate_RNIA8N5H : out std_logic_vector(0 to 0); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - vitdatain_0_1_0 : in std_logic_vector(22 to 22) := (others => 'U'); - fault_isid_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - dataout_1 : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout_0 : in std_logic_vector(35 downto 32) := (others => 'U'); - ctx_0_5 : in std_logic := 'U'; - ctx_0_0 : in std_logic := 'U'; - ctx_0_4 : in std_logic := 'U'; - address : out std_logic_vector(31 downto 2); - bo_d : in std_logic_vector(3 to 3) := (others => 'U'); - un1_p0_6 : in std_logic_vector(0 to 0) := (others => 'U'); - maddress : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout_2 : in std_logic_vector(31 downto 0) := (others => 'U'); - fpc : in std_logic_vector(31 downto 2) := (others => 'U'); - asi : in std_logic_vector(0 to 0) := (others => 'U'); - un1_p0_2_0 : out std_logic_vector(148 to 148); - su_0 : in std_logic := 'U'; - diagrdy : out std_logic; - hold_0 : out std_logic; - mexc_0 : out std_logic; - fbranch : in std_logic := 'U'; - rbranch : in std_logic := 'U'; - flush2_RNIFMGM2 : out std_logic; - N_425_1 : in std_logic := 'U'; - flush2_RNI5I3N7 : out std_logic; - N_984 : out std_logic; - N_980 : out std_logic; - N_28 : in std_logic := 'U'; - N_987 : out std_logic; - N_986 : out std_logic; - e : in std_logic := 'U'; - flush2 : out std_logic; - N_26 : in std_logic := 'U'; - flush2_0_0_RNI146O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - mds : out std_logic; - su : out std_logic; - nf : in std_logic := 'U'; - N_981 : out std_logic; - N_429 : in std_logic := 'U'; - N_359 : in std_logic := 'U'; - N_2626 : in std_logic := 'U'; - N_43 : in std_logic := 'U'; - N_427 : in std_logic := 'U'; - N_2625 : in std_logic := 'U'; - N_6093_i : in std_logic := 'U'; - N_423 : in std_logic := 'U'; - N_425 : in std_logic := 'U'; - N_45 : in std_logic := 'U'; - N_2623 : in std_logic := 'U'; - N_365 : in std_logic := 'U'; - N_357 : in std_logic := 'U'; - N_985 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_363 : in std_logic := 'U'; - N_321 : in std_logic := 'U'; - N_319 : in std_logic := 'U'; - N_361 : in std_logic := 'U'; - N_2624 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - inull : in std_logic := 'U'; - hold : in std_logic := 'U'; - ldlock_3_0 : in std_logic := 'U'; - un9_icc_check_bp : in std_logic := 'U'; - trans_op_0 : out std_logic; - flush_op_i_0 : in std_logic := 'U'; - un2_m_tlb_type : in std_logic := 'U'; - stpend_RNI6P41NG3 : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_2 : in std_logic := 'U'; - ldlock_2 : in std_logic := 'U'; - xc_exception_1_0 : in std_logic := 'U'; - grant : in std_logic := 'U'; - iflush_1_0_a2_0 : in std_logic := 'U'; - N_121 : in std_logic := 'U'; - un1_ici : out std_logic; - fault_trans_RNIA0K0D1 : in std_logic := 'U'; - N_66_0 : in std_logic := 'U'; - de_hold_pc_1 : in std_logic := 'U'; - N_425_0 : in std_logic := 'U'; - flush_0 : out std_logic; - flush : in std_logic := 'U'; - trans_op : in std_logic := 'U'; - ba : in std_logic := 'U'; - hcache : in std_logic := 'U'; - mexc : in std_logic := 'U'; - req : out std_logic; - e_0 : in std_logic := 'U'; - hold_pc_7 : in std_logic := 'U'; - istate_0_sqmuxa : out std_logic; - flush_i_0 : in std_logic := 'U'; - N_523 : in std_logic := 'U'; - ready : in std_logic := 'U'; - burst_0 : out std_logic; - burst : in std_logic := 'U'; - rst : in std_logic := 'U'; - un81_m_tlb_type : in std_logic := 'U'; - holdn : out std_logic; - cdwrite_0_sqmuxa_i_0_0 : out std_logic; - N_66 : in std_logic := 'U'; - enable : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component mmu - port( ctxp : in std_logic_vector(25 downto 0) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - data_0 : out std_logic; - data_1_d0 : out std_logic; - data_2_d0 : out std_logic; - data_3 : out std_logic; - data_4 : out std_logic; - data_6 : out std_logic; - data_7 : out std_logic; - data_8 : out std_logic; - data_9 : out std_logic; - data_10 : out std_logic; - data_11 : out std_logic; - data_2 : out std_logic_vector(31 downto 12); - data_RNIKU1T4 : out std_logic_vector(16 to 16); - maddress : in std_logic_vector(31 downto 12) := (others => 'U'); - data_1 : in std_logic_vector(31 downto 12) := (others => 'U'); - LVL_RNIT69H911 : out std_logic_vector(0 to 0); - data_1_3_i_a3_6_2 : out std_logic; - data_1_3_i_a3_6_4 : out std_logic; - data_1_3_i_a3_6_1 : out std_logic; - data_1_3_i_a3_6_0 : out std_logic; - hrdata_5 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - address_0 : in std_logic_vector(31 downto 2) := (others => 'U'); - un1_m0_2_d0 : out std_logic; - un1_m0_3 : out std_logic; - un1_m0_4 : out std_logic; - un1_m0_7 : out std_logic; - un1_m0_16 : out std_logic; - un1_m0_17 : out std_logic; - un1_m0_0 : out std_logic; - un1_m0_6 : out std_logic; - un1_m0_22 : out std_logic; - un1_m0_1 : out std_logic; - un1_m0_5 : out std_logic; - un1_m0_8 : out std_logic; - un1_m0_9 : out std_logic; - un1_m0_30 : out std_logic; - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - ctx_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - address : out std_logic_vector(31 downto 2); - hrdata_1_0_1 : in std_logic_vector(1 to 1) := (others => 'U'); - un1_m0_2_23 : out std_logic; - un1_m0_2_15 : out std_logic; - un1_m0_2_31 : out std_logic; - un1_m0_2_33 : out std_logic; - un1_m0_2_1 : out std_logic; - un1_m0_2_2 : out std_logic; - un1_m0_2_3 : out std_logic; - un1_m0_2_4 : out std_logic; - un1_m0_2_5 : out std_logic; - un1_m0_2_6 : out std_logic; - un1_m0_2_8 : out std_logic; - un1_m0_2_11 : out std_logic; - un1_m0_2_12 : out std_logic; - un1_m0_2_18 : out std_logic; - un1_m0_2_29 : out std_logic; - un1_m0_2_19 : out std_logic; - un1_m0_2_9 : out std_logic; - un1_m0_2_10 : out std_logic; - un1_m0_2_7 : out std_logic; - un1_m0_2_75 : in std_logic := 'U'; - un1_m0_2_76 : in std_logic := 'U'; - un1_m0_2_77 : in std_logic := 'U'; - un1_m0_2_78 : in std_logic := 'U'; - un1_m0_2_79 : in std_logic := 'U'; - un1_m0_2_80 : in std_logic := 'U'; - un1_m0_2_81 : in std_logic := 'U'; - un1_m0_2_82 : in std_logic := 'U'; - un1_m0_2_83 : in std_logic := 'U'; - un1_m0_2_84 : in std_logic := 'U'; - un1_m0_2_85 : in std_logic := 'U'; - un1_m0_2_86 : in std_logic := 'U'; - un1_m0_2_97 : out std_logic; - un1_m0_2_96 : out std_logic; - un1_m0_2_95 : out std_logic; - un1_m0_2_93 : out std_logic; - un1_m0_2_108 : out std_logic; - un1_m0_2_91 : out std_logic; - un1_m0_2_106 : out std_logic; - un1_m0_2_92 : out std_logic; - un1_m0_2_98 : out std_logic; - un1_m0_2_94 : out std_logic; - un1_m0_2_44 : out std_logic; - un1_m0_2_43 : out std_logic; - un1_m0_2_73 : out std_logic; - un1_m0_2_72 : out std_logic; - un1_m0_2_71 : out std_logic; - un1_m0_2_70 : out std_logic; - un1_m0_2_69 : out std_logic; - un1_m0_2_68 : out std_logic; - un1_m0_2_67 : out std_logic; - un1_m0_2_66 : out std_logic; - un1_m0_2_65 : out std_logic; - un1_m0_2_64 : out std_logic; - un1_m0_2_63 : out std_logic; - un1_m0_2_62 : out std_logic; - un1_m0_2_61 : out std_logic; - un1_m0_2_60 : out std_logic; - un1_m0_2_59 : out std_logic; - un1_m0_2_58 : out std_logic; - un1_m0_2_57 : out std_logic; - un1_m0_2_56 : out std_logic; - un1_m0_2_55 : out std_logic; - un1_m0_2_54 : out std_logic; - un1_m0_2_40 : out std_logic; - un1_m0_2_42 : out std_logic; - un1_m0_2_35 : out std_logic; - un1_m0_2_36 : out std_logic; - un1_m0_2_34 : out std_logic; - un1_m0_2_39 : out std_logic; - un1_m0_2_38 : out std_logic; - un1_m0_2_37 : out std_logic; - un1_m0_2_0_d0 : out std_logic; - un1_m0_2_41 : out std_logic; - fault_isid_1_i : out std_logic_vector(0 to 0); - un1_m0_2_0 : out std_logic_vector(35 to 35); - mexc : in std_logic := 'U'; - req : out std_logic; - ba : in std_logic := 'U'; - bo_5842_d_0 : in std_logic := 'U'; - read_0 : out std_logic; - grant : in std_logic := 'U'; - su_0 : in std_logic := 'U'; - read : in std_logic := 'U'; - N_421 : out std_logic; - N_419 : out std_logic; - N_417 : out std_logic; - N_415 : out std_logic; - N_353 : out std_logic; - N_351 : out std_logic; - N_317 : out std_logic; - N_293 : out std_logic; - N_236 : out std_logic; - N_192 : out std_logic; - N_190 : out std_logic; - N_2887 : out std_logic; - N_2886 : out std_logic; - N_2701 : out std_logic; - fault_pro67 : out std_logic; - M_m : out std_logic; - e : in std_logic := 'U'; - N_2720 : out std_logic; - N_2717 : out std_logic; - N_2714 : out std_logic; - G_80_0 : out std_logic; - N_2703_i_0 : out std_logic; - N_2699_i_0 : out std_logic; - un54_fault_pro_m : out std_logic; - accexc_6 : out std_logic; - fault_pro : out std_logic; - fault_pri_0 : out std_logic; - N_2709_i_0 : out std_logic; - N_2711_i_0 : out std_logic; - N_2702_i_0 : out std_logic; - N_696 : out std_logic; - N_695 : out std_logic; - N_694 : out std_logic; - N_359 : out std_logic; - N_357 : out std_logic; - N_365 : out std_logic; - N_363 : out std_logic; - N_361 : out std_logic; - N_321 : out std_logic; - N_319 : out std_logic; - N_45 : out std_logic; - N_2624 : out std_logic; - N_2623 : out std_logic; - N_425 : out std_logic; - N_423 : out std_logic; - N_43 : out std_logic; - N_2626 : out std_logic; - N_427 : out std_logic; - N_429 : out std_logic; - N_262_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - tlbdis : in std_logic := 'U'; - N_2625 : out std_logic; - su : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - mmu_VCC : in std_logic := 'U'; - fsread_i_0 : in std_logic := 'U'; - trans_op_2 : in std_logic := 'U'; - flush_op_i_0 : in std_logic := 'U'; - mmudci_trans_op_1_sqmuxa_1 : in std_logic := 'U'; - N_66 : out std_logic; - trans_op_1 : in std_logic := 'U'; - un2_m_tlb_type : out std_logic; - flush : out std_logic; - trans_op : in std_logic := 'U'; - istate_0_sqmuxa : in std_logic := 'U'; - un81_m_tlb_type : out std_logic; - rst : in std_logic := 'U'; - N_546 : in std_logic := 'U'; - N_66_0 : out std_logic; - fault_trans_RNIA0K0D1 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - signal \ics[0]\, \ics[1]\, \un1_m0[34]\, \un1_m0[9]\, - \un1_m0[13]\, \un1_m0[12]\, \un1_m0[5]\, \un1_m0[26]\, - \un1_m0[10]\, \un1_m0[4]\, \un1_m0[21]\, \un1_m0[20]\, - \un1_m0[11]\, \un1_m0[8]\, \un1_m0[6]\, \un1_m0[7]\, - \diagdata[6]\, \diagdata[15]\, \diagdata[4]\, - \diagdata[19]\, \diagdata[18]\, \diagdata[17]\, - \diagdata[16]\, \diagdata[20]\, \diagdata[26]\, - \diagdata[25]\, \diagdata[22]\, \diagdata[14]\, - \diagdata[12]\, \diagdata[9]\, \diagdata[8]\, - \diagdata[5]\, \diagdata[3]\, \diagdata[0]\, - \diagdata[7]\, \diagdata[27]\, \diagdata[23]\, - \diagdata[24]\, \diagdata[31]\, \diagdata[29]\, - \diagdata[28]\, \diagdata[21]\, \diagdata[13]\, - \diagdata[2]\, \diagdata[30]\, \diagdata[1]\, \addr[2]\, - \addr[3]\, \addr[4]\, \addr[5]\, \addr[6]\, \addr[7]\, - \addr[8]\, \addr[9]\, \addr[10]\, \addr[11]\, - \fault_isid_1_i[0]\, \ctx_0[7]\, \ctx_0[2]\, \ctx_0[6]\, - \address[2]\, \address[3]\, \address[4]\, \address[5]\, - \address[6]\, \address[7]\, \address[8]\, \address[9]\, - \address[10]\, \address[11]\, \address[12]\, - \address[13]\, \address[14]\, \address[15]\, - \address[16]\, \address[17]\, \address[18]\, - \address[19]\, \address[20]\, \address[21]\, - \address[22]\, \address[23]\, \address[24]\, - \address[25]\, \address[26]\, \address[27]\, - \address[28]\, \address[29]\, \address[30]\, - \address[31]\, \bo_d[3]\, \asi[0]\, diagrdy, hold, N_425, - e, su_0, nf, N_429, N_359, N_2626, N_43, N_427, N_2625, - N_6093_i, N_423, N_425_0, N_45, N_2623, N_365, N_357, - N_363, N_321, N_319, N_361, N_2624, hold_0, trans_op, - flush_op_i_0, un2_m_tlb_type, stpend_RNI6P41NG3, - vaddr_1_sqmuxa_0_a2_2, grant, iflush_1_0_a2_0, N_121, - fault_trans_RNIA0K0D1, N_66_0, N_425_0_0, flush, flush_0, - trans_op_0, ba, hcache, mexc_0, req, e_0, istate_0_sqmuxa, - N_523, ready, burst, burst_0, un81_m_tlb_type, - cdwrite_0_sqmuxa_i_0_0, N_66, enable, \data[31]\, - \data[30]\, \data[28]\, \data[27]\, \data[26]\, - \data[25]\, \data[21]\, \data[20]\, \data[17]\, - \data[16]\, \data[15]\, \data[14]\, \data[12]\, \size[1]\, - \ctx[0]\, \ctx[1]\, \ctx[3]\, \ctx[4]\, \ctx[5]\, - \bo_d[2]\, \un1_m0_2_0[35]\, \data[0]\, \data[1]\, - \data[2]\, \data[3]\, \data[4]\, \data[6]\, \data[7]\, - \data[9]\, \data[11]\, \data_1[12]\, \data_1[13]\, - \data_1[14]\, \data_1[15]\, \data_1[16]\, \data_1[17]\, - \data[18]\, \data[19]\, \data_1[20]\, \data_1[21]\, - \data[22]\, \data[23]\, \data_1[24]\, \data_1[25]\, - \data_1[26]\, \data_1[27]\, \data_1[28]\, \data_1[29]\, - \data_1[30]\, \data_1[31]\, \LVL_RNIT69H911[0]\, - \data_1_3_i_a3_6[27]\, \data_1_3_i_a3_6[29]\, - \data_1_3_i_a3_6[25]\, \data_1_3_i_a3_6[26]\, - \data_RNIKU1T4[16]\, \un1_m0_2[74]\, \un1_m0_2[3]\, - \un1_m0_2[5]\, \un1_m0_2[11]\, \un1_m0_2[10]\, - \un1_m0_2[41]\, \un1_m0_2[6]\, \un1_m0_2[2]\, - \un1_m0_2[8]\, \un1_m0_2[69]\, \un1_m0_2[39]\, - \un1_m0_2[43]\, \un1_m0_2[60]\, \un1_m0_2[59]\, - \un1_m0_2[68]\, \un1_m0_2[44]\, \un1_m0_2[66]\, - \un1_m0_2[78]\, \un1_m0_2[35]\, \un1_m0_2[79]\, - \un1_m0_2[76]\, \un1_m0_2[7]\, \un1_m0_2[30]\, - \un1_m0_2[20]\, \un1_m0_2[24]\, \un1_m0_2[61]\, - \un1_m0_2[80]\, \un1_m0_2[81]\, \un1_m0_2[82]\, - \un1_m0_2[85]\, \un1_m0_2[84]\, \un1_m0_2[87]\, - \un1_m0_2[77]\, \un1_m0_2[16]\, \un1_m0_2[12]\, - \un1_m0_2[19]\, \un1_m0_2[86]\, \un1_m0_2[55]\, - \un1_m0_2[72]\, \un1_m0_2[56]\, \un1_m0_2[71]\, - \un1_m0_2[62]\, \un1_m0_2[70]\, \un1_m0_2[38]\, - \un1_m0_2[67]\, \un1_m0_2[57]\, \un1_m0_2[65]\, - \un1_m0_2[63]\, \un1_m0_2[58]\, \un1_m0_2[42]\, - \un1_m0_2[95]\, \un1_m0_2[92]\, \un1_m0_2[107]\, - \un1_m0_2[97]\, \un1_m0_2[93]\, \un1_m0_2[96]\, - \un1_m0_2[98]\, \un1_m0_2[94]\, \un1_m0_2[99]\, - \un1_m0_2[34]\, \un1_m0_2[73]\, \un1_m0_2[40]\, - \un1_m0_2[64]\, \un1_m0_2[45]\, \un1_m0_2[36]\, - \un1_m0_2[37]\, \un1_m0_2[1]\, \un1_m0_2[4]\, - \un1_m0_2[13]\, \un1_m0_2[83]\, \un1_m0_2[9]\, - \un1_m0_2[32]\, \un1_m0_2[109]\, \data_1[23]\, - \data_1[22]\, \data_1[19]\, \data_1[18]\, \ctxp[13]\, - \ctxp[16]\, \ctxp[7]\, \ctxp[10]\, \ctxp[3]\, \ctxp[8]\, - \ctxp[19]\, \ctxp[17]\, \ctxp[15]\, \ctxp[14]\, - \ctxp[20]\, \ctxp[18]\, \ctxp[6]\, \ctxp[21]\, \ctxp[11]\, - \ctxp[4]\, \ctxp[25]\, \ctxp[0]\, \ctxp[22]\, \ctxp[23]\, - \ctxp[24]\, \ctxp[5]\, \ctxp[12]\, \ctxp[9]\, \ctxp[1]\, - \ctxp[2]\, \address_0[2]\, \address_0[3]\, \address_0[4]\, - \address_0[5]\, \address_0[6]\, \address_0[7]\, - \address_0[8]\, \address_0[9]\, \address_0[10]\, - \address_0[11]\, \address_0[12]\, \address_0[13]\, - \address_0[14]\, \address_0[15]\, \address_0[16]\, - \address_0[17]\, \address_0[18]\, \address_0[19]\, - \address_0[20]\, \address_0[21]\, \address_0[22]\, - \address_0[23]\, \address_0[24]\, \address_0[25]\, - \address_0[26]\, \address_0[27]\, \address_0[28]\, - \address_0[29]\, \address_0[30]\, \address_0[31]\, - \ctx_0[0]\, \ctx_0[1]\, \ctx_0[3]\, \ctx_0[4]\, - \ctx_0[5]\, size, su_1, read, N_415, N_351, N_192, N_190, - trans_op_1, tlbdis, read_0, grant_0, N_317, N_2886, - N_2887, N_353, N_236, N_417, N_421, un54_fault_pro_m, M_m, - fault_pro, lock_m, N_2699_i_0, N_2701, N_2703_i_0, N_2714, - N_696, N_695, N_2702_i_0, N_2717, N_2720, N_694, - N_2711_i_0, fsread_i_0, cache, lock, mexc_2, fault_pro67, - req_0, fault_pri, N_419, N_2709_i_0, N_293, burst_1, - accexc_6, G_80_0, ready_0, mmudci_trans_op_1_sqmuxa_1, - \data_2[18]\, \data_1[1]\, \data_1[3]\, \data_2[17]\, - \data_2[22]\, \data_2[21]\, \data_1[9]\, \data_2[23]\, - \data_2[20]\, \data_1[4]\, \data_2[31]\, \data_2[26]\, - \data_2[15]\, \data_1[7]\, \data_2[27]\, \data_2[25]\, - \data_2[16]\, \data_2[30]\, \data_2[28]\, \data_2[14]\, - \data_1[2]\, \data_1[11]\, \data_1[0]\, \data_2[12]\, - \data_1[6]\, \data_2[19]\, \address_1[2]\, \address_1[3]\, - \address_1[6]\, \address_1[7]\, \address_1[8]\, - \address_1[9]\, \address_1[10]\, \address_1[11]\, - \address_1[12]\, \address_1[14]\, \address_1[15]\, - \address_1[16]\, \address_1[17]\, \address_1[18]\, - \address_1[19]\, \address_1[20]\, \address_1[21]\, - \address_1[22]\, \address_1[23]\, \address_1[24]\, - \address_1[25]\, \address_1[26]\, \address_1[27]\, - \address_1[29]\, \address_1[30]\, \address_1[31]\, - \address_1[4]\, \address_1[28]\, \address_1[5]\, - \address_1[13]\, read_2, mexc_3, \un59_nbo\, req_1, - grant_1, \ctx[2]\, \ctx[6]\, \ctx[7]\, \bo_5842_d_0\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : mmu_dcache - Use entity work.mmu_dcache(DEF_ARCH); - for all : mmu_acache - Use entity work.mmu_acache(DEF_ARCH); - for all : mmu_icache - Use entity work.mmu_icache(DEF_ARCH); - for all : mmu - Use entity work.mmu(DEF_ARCH); -begin - - ctx(7) <= \ctx[7]\; - ctx(6) <= \ctx[6]\; - ctx(5) <= \ctx[5]\; - ctx(4) <= \ctx[4]\; - ctx(3) <= \ctx[3]\; - ctx(2) <= \ctx[2]\; - ctx(1) <= \ctx[1]\; - ctx(0) <= \ctx[0]\; - bo_5842_d_0 <= \bo_5842_d_0\; - un59_nbo <= \un59_nbo\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - dcache0 : mmu_dcache - port map(data_1_19 => \data[31]\, data_1_18 => \data[30]\, - data_1_17 => data_29, data_1_16 => \data[28]\, data_1_15 - => \data[27]\, data_1_14 => \data[26]\, data_1_13 => - \data[25]\, data_1_12 => data_24, data_1_9 => \data[21]\, - data_1_8 => \data[20]\, data_1_5 => \data[17]\, data_1_4 - => \data[16]\, data_1_3 => \data[15]\, data_1_2 => - \data[14]\, data_1_1 => data_13, data_1_0 => \data[12]\, - faddr_RNIB0UOO(2) => faddr_RNIB0UOO(2), - dstate_i_RNI29QQ7J3(8) => dstate_i_RNI29QQ7J3(8), - xaddress_RNITFTTE(3) => xaddress_RNITFTTE(3), - xaddress_RNIFP43F(2) => xaddress_RNIFP43F(2), size_1(1) - => \size[1]\, size_1(0) => size_0_d0, faddr_RNI7MK691(6) - => faddr_RNI7MK691(6), dci_m_94 => dci_m_6, dci_m_93 => - dci_m_5, dci_m_91 => dci_m_3, dci_m_90 => dci_m_2, - dci_m_89 => dci_m_1, dci_m_88 => dci_m_0, - faddr_RNI7879K(0) => faddr_RNI7879K(0), faddr_RNIEHR0O(1) - => faddr_RNIEHR0O(1), edata2_iv_i_0(31) => - edata2_iv_i_0(31), edata2_iv_i_0(30) => edata2_iv_i_0(30), - edata2_iv_i_0(29) => edata2_iv_i_0(29), edata2_iv_i_0(28) - => edata2_iv_i_0(28), edata2_iv_i_0(27) => - edata2_iv_i_0(27), edata2_iv_i_0(26) => edata2_iv_i_0(26), - edata2_iv_i_0(25) => edata2_iv_i_0(25), edata2_iv_i_0(24) - => edata2_iv_i_0(24), ctx(7) => \ctx[7]\, ctx(6) => - \ctx[6]\, ctx(5) => \ctx[5]\, ctx(4) => \ctx[4]\, ctx(3) - => \ctx[3]\, ctx(2) => \ctx[2]\, ctx(1) => \ctx[1]\, - ctx(0) => \ctx[0]\, hrdata_0_d0 => hrdata_5, hrdata_24 - => hrdata_29, hrdata_26 => hrdata_31, hrdata_25 => - hrdata_30, hrdata_23 => hrdata_28, hrdata_1 => hrdata_6, - dstate_RNIC3QA81(1) => dstate_RNIC3QA81(1), - dstate_RNIFPT581(1) => dstate_RNIFPT581(1), size_0_0 => - size_0(0), hrdata_0_7 => hrdata_0_7, hrdata_0_11 => - hrdata_0_11, hrdata_0_9 => hrdata_0_9, hrdata_0_21 => - hrdata_0_21, hrdata_0_4 => hrdata_0_4, hrdata_0_3 => - hrdata_0_3, hrdata_0_8 => hrdata_0_8, hrdata_0_15 => - hrdata_0_15, hrdata_0_27 => hrdata_0_27, hrdata_0_23 => - hrdata_0_23, hrdata_0_1 => hrdata_0_1, hrdata_0_13 => - hrdata_0_13, hrdata_0_12 => hrdata_0_12, hrdata_0_10 => - hrdata_0_10, hrdata_0_2 => hrdata_0_2, hrdata_0_14 => - hrdata_0_14, hrdata_0_26 => hrdata_0_26, hrdata_0_24 => - hrdata_0_24, hrdata_0_22 => hrdata_0_22, hrdata_0_18 => - hrdata_0_18, hrdata_0_17 => hrdata_0_17, hrdata_0_16 => - hrdata_0_16, hrdata_0_0 => hrdata_0_0, dco_i_2(132) => - dco_i_2(132), dstate_i_0_RNIH0PPES(8) => - dstate_i_0_RNIH0PPES(8), dstate_RNI1G47MJ(1) => - dstate_RNI1G47MJ(1), dstate_RNIFS6E51(1) => - dstate_RNIFS6E51(1), xaddress_RNI1Q9ST1(1) => - xaddress_RNI1Q9ST1(1), xaddress_RNIEHIUT1(1) => - xaddress_RNIEHIUT1(1), xaddress_RNILHOK61(1) => - xaddress_RNILHOK61(1), xaddress_RNILK99L1(1) => - xaddress_RNILK99L1(1), xaddress_RNI1I3MQ1(0) => - xaddress_RNI1I3MQ1(0), xaddress_RNIK99NK1(1) => - xaddress_RNIK99NK1(1), xaddress_RNIP2BVK1(1) => - xaddress_RNIP2BVK1(1), xaddress_RNIJI2O22(1) => - xaddress_RNIJI2O22(1), xaddress_RNITMH17S2(12) => - xaddress_RNITMH17S2(12), xaddress_RNICFI17S2(13) => - xaddress_RNICFI17S2(13), xaddress_RNI1D927S2(20) => - xaddress_RNI1D927S2(20), xaddress_RNI9MB27S2(23) => - xaddress_RNI9MB27S2(23), xaddress_RNI0GI17S2(17) => - xaddress_RNI0GI17S2(17), xaddress_RNIC5A27S2(21) => - xaddress_RNIC5A27S2(21), xaddress_RNIN7J17S2(14) => - xaddress_RNIN7J17S2(14), xaddress_RNIID927S2(16) => - xaddress_RNIID927S2(16), xaddress_RNI2MB27S2(15) => - xaddress_RNI2MB27S2(15), dstate_i_0_RNIL7FGFS(8) => - dstate_i_0_RNIL7FGFS(8), xaddress_RNID252J1(10) => - xaddress_RNID252J1(10), newtag_1_0_9 => newtag_1_0(27), - newtag_1_0_8 => newtag_1_0(26), newtag_1_0_7 => - newtag_1_0(25), newtag_1_0_6 => newtag_1_0(24), - edata2_0_iv(23) => edata2_0_iv(23), edata2_0_iv(22) => - edata2_0_iv(22), edata2_0_iv(21) => edata2_0_iv(21), - edata2_0_iv(20) => edata2_0_iv(20), edata2_0_iv(19) => - edata2_0_iv(19), edata2_0_iv(18) => edata2_0_iv(18), - edata2_0_iv(17) => edata2_0_iv(17), edata2_0_iv(16) => - edata2_0_iv(16), edata2_0_iv(15) => edata2_0_iv(15), - edata2_0_iv(14) => edata2_0_iv(14), edata2_0_iv(13) => - edata2_0_iv(13), edata2_0_iv(12) => edata2_0_iv(12), - edata2_0_iv(11) => edata2_0_iv(11), edata2_0_iv(10) => - edata2_0_iv(10), edata2_0_iv(9) => edata2_0_iv(9), - edata2_0_iv(8) => edata2_0_iv(8), edata2_0_iv(7) => - edata2_0_iv(7), edata2_0_iv(6) => edata2_0_iv(6), - edata2_0_iv(5) => edata2_0_iv(5), edata2_0_iv(4) => - edata2_0_iv(4), edata2_0_iv(3) => edata2_0_iv(3), - edata2_0_iv(2) => edata2_0_iv(2), edata2_0_iv(1) => - edata2_0_iv(1), edata2_0_iv(0) => edata2_0_iv(0), asi_0_0 - => \asi[0]\, dataout_1(11) => dataout_1(11), - dataout_1(10) => dataout_1(10), size_1_d0 => size_0(1), - bo_d(2) => \bo_d[2]\, rdatav_0_1_1_iv_7(6) => - rdatav_0_1_1_iv_7(6), rdatav_0_1_0_iv_0_2_0 => - rdatav_0_1_0_iv_0_2(10), rdatav_0_1_0_iv_7_2 => - rdatav_0_1_0_iv_7(2), un1_m0_2_0(35) => \un1_m0_2_0[35]\, - ics(1) => \ics[1]\, ics(0) => \ics[0]\, maddress_0_2 => - maddress_0_2, maddress_0_0 => maddress_0_0, asi(4) => - asi_4, asi(3) => asi_3, asi(2) => asi_2, asi(1) => asi_1, - asi(0) => asi_0(0), data(31) => \data_1[31]\, data(30) - => \data_1[30]\, data(29) => \data_1[29]\, data(28) => - \data_1[28]\, data(27) => \data_1[27]\, data(26) => - \data_1[26]\, data(25) => \data_1[25]\, data(24) => - \data_1[24]\, data(23) => \data[23]\, data(22) => - \data[22]\, data(21) => \data_1[21]\, data(20) => - \data_1[20]\, data(19) => \data[19]\, data(18) => - \data[18]\, data(17) => \data_1[17]\, data(16) => - \data_1[16]\, data(15) => \data_1[15]\, data(14) => - \data_1[14]\, data(13) => \data_1[13]\, data(12) => - \data_1[12]\, data(11) => \data[11]\, data(10) => data_10, - data(9) => \data[9]\, data(8) => data_8, data(7) => - \data[7]\, data(6) => \data[6]\, data(5) => data_5, - data(4) => \data[4]\, data(3) => \data[3]\, data(2) => - \data[2]\, data(1) => \data[1]\, data(0) => \data[0]\, - LVL_RNIT69H911(0) => \LVL_RNIT69H911[0]\, - data_1_3_i_a3_6_2 => \data_1_3_i_a3_6[27]\, - data_1_3_i_a3_6_4 => \data_1_3_i_a3_6[29]\, - data_1_3_i_a3_6_0 => \data_1_3_i_a3_6[25]\, - data_1_3_i_a3_6_1 => \data_1_3_i_a3_6[26]\, - data_RNIKU1T4(16) => \data_RNIKU1T4[16]\, un1_m0_2_73 => - \un1_m0_2[74]\, un1_m0_2_2 => \un1_m0_2[3]\, un1_m0_2_4 - => \un1_m0_2[5]\, un1_m0_2_10 => \un1_m0_2[11]\, - un1_m0_2_9 => \un1_m0_2[10]\, un1_m0_2_40 => - \un1_m0_2[41]\, un1_m0_2_5 => \un1_m0_2[6]\, un1_m0_2_1 - => \un1_m0_2[2]\, un1_m0_2_7 => \un1_m0_2[8]\, - un1_m0_2_68 => \un1_m0_2[69]\, un1_m0_2_38 => - \un1_m0_2[39]\, un1_m0_2_42 => \un1_m0_2[43]\, - un1_m0_2_59 => \un1_m0_2[60]\, un1_m0_2_58 => - \un1_m0_2[59]\, un1_m0_2_67 => \un1_m0_2[68]\, - un1_m0_2_43 => \un1_m0_2[44]\, un1_m0_2_65 => - \un1_m0_2[66]\, un1_m0_2_77 => \un1_m0_2[78]\, - un1_m0_2_34 => \un1_m0_2[35]\, un1_m0_2_78 => - \un1_m0_2[79]\, un1_m0_2_75 => \un1_m0_2[76]\, un1_m0_2_6 - => \un1_m0_2[7]\, un1_m0_2_29 => \un1_m0_2[30]\, - un1_m0_2_19 => \un1_m0_2[20]\, un1_m0_2_23 => - \un1_m0_2[24]\, un1_m0_2_60 => \un1_m0_2[61]\, - un1_m0_2_79 => \un1_m0_2[80]\, un1_m0_2_80 => - \un1_m0_2[81]\, un1_m0_2_81 => \un1_m0_2[82]\, - un1_m0_2_84 => \un1_m0_2[85]\, un1_m0_2_83 => - \un1_m0_2[84]\, un1_m0_2_86 => \un1_m0_2[87]\, - un1_m0_2_76 => \un1_m0_2[77]\, un1_m0_2_15 => - \un1_m0_2[16]\, un1_m0_2_11 => \un1_m0_2[12]\, - un1_m0_2_18 => \un1_m0_2[19]\, un1_m0_2_85 => - \un1_m0_2[86]\, un1_m0_2_54 => \un1_m0_2[55]\, - un1_m0_2_71 => \un1_m0_2[72]\, un1_m0_2_55 => - \un1_m0_2[56]\, un1_m0_2_70 => \un1_m0_2[71]\, - un1_m0_2_61 => \un1_m0_2[62]\, un1_m0_2_69 => - \un1_m0_2[70]\, un1_m0_2_37 => \un1_m0_2[38]\, - un1_m0_2_66 => \un1_m0_2[67]\, un1_m0_2_56 => - \un1_m0_2[57]\, un1_m0_2_64 => \un1_m0_2[65]\, - un1_m0_2_62 => \un1_m0_2[63]\, un1_m0_2_57 => - \un1_m0_2[58]\, un1_m0_2_41 => \un1_m0_2[42]\, - un1_m0_2_94 => \un1_m0_2[95]\, un1_m0_2_91 => - \un1_m0_2[92]\, un1_m0_2_106 => \un1_m0_2[107]\, - un1_m0_2_96 => \un1_m0_2[97]\, un1_m0_2_92 => - \un1_m0_2[93]\, un1_m0_2_95 => \un1_m0_2[96]\, - un1_m0_2_97 => \un1_m0_2[98]\, un1_m0_2_93 => - \un1_m0_2[94]\, un1_m0_2_98 => \un1_m0_2[99]\, - un1_m0_2_33 => \un1_m0_2[34]\, un1_m0_2_72 => - \un1_m0_2[73]\, un1_m0_2_39 => \un1_m0_2[40]\, - un1_m0_2_63 => \un1_m0_2[64]\, un1_m0_2_44 => - \un1_m0_2[45]\, un1_m0_2_35 => \un1_m0_2[36]\, - un1_m0_2_36 => \un1_m0_2[37]\, un1_m0_2_0_d0 => - \un1_m0_2[1]\, un1_m0_2_3 => \un1_m0_2[4]\, un1_m0_2_12 - => \un1_m0_2[13]\, un1_m0_2_82 => \un1_m0_2[83]\, - un1_m0_2_8 => \un1_m0_2[9]\, un1_m0_2_31 => - \un1_m0_2[32]\, un1_m0_2_108 => \un1_m0_2[109]\, - eaddress_7 => eaddress_7, eaddress_3 => eaddress_3, - eaddress_0 => eaddress_0, eaddress_8 => eaddress_8, - eaddress_1 => eaddress_1, eaddress_4 => eaddress_4, - eaddress_12 => eaddress_12, eaddress_16 => eaddress_16, - eaddress_24 => eaddress_24, eaddress_2 => eaddress_2, - eaddress_20 => eaddress_20, eaddress_5 => eaddress_5, - eaddress_15 => eaddress_15, eaddress_27 => eaddress_27, - eaddress_17 => eaddress_17, eaddress_9 => eaddress_9, - eaddress_19 => eaddress_19, eaddress_23 => eaddress_23, - eaddress_25 => eaddress_25, eaddress_10 => eaddress_10, - eaddress_6 => eaddress_6, eaddress_18 => eaddress_18, - eaddress_28 => eaddress_28, eaddress_13 => eaddress_13, - eaddress_21 => eaddress_21, eaddress_22 => eaddress_22, - eaddress_29 => eaddress_29, rdatav_0_1_0_iv_5_18 => - rdatav_0_1_0_iv_5_4, rdatav_0_1_0_iv_5_14 => - rdatav_0_1_0_iv_5_0, rdatav_0_1_0_iv_5_15 => - rdatav_0_1_0_iv_5_1, rdatav_0_1_0_iv_5_20 => - rdatav_0_1_0_iv_5_6, rdatav_0_1_0_iv_4_23 => - rdatav_0_1_0_iv_4_14, rdatav_0_1_0_iv_4_9 => - rdatav_0_1_0_iv_4_0, rdatav_0_1_0_iv_4_29 => - rdatav_0_1_0_iv_4_20, rdatav_0_1_0_iv_4_31 => - rdatav_0_1_0_iv_4_22, mcdo_m_0_8 => mcdo_m_0_7, - mcdo_m_0_5 => mcdo_m_0_4, mcdo_m_0_18 => mcdo_m_0_17, - mcdo_m_0_21 => mcdo_m_0_20, mcdo_m_0_22 => mcdo_m_0_21, - mcdo_m_0_17 => mcdo_m_0_16, mcdo_m_0_1 => mcdo_m_0_0, - mcdo_m_0_28 => mcdo_m_0_27, mcdo_m_0_23 => mcdo_m_0_22, - mcdo_m_0_30 => mcdo_m_0_29, data_0_23 => \data_1[23]\, - data_0_22 => \data_1[22]\, data_0_19 => \data_1[19]\, - data_0_18 => \data_1[18]\, data_0_7 => data_0_0_7, - data_0_15 => data_0_0_15, data_0_12 => data_0_0_12, - data_0_0 => data_0_0_0, data_0_26 => data_0_0_26, - data_0_4 => data_0_0_4, data_0_21 => data_0_0_21, - data_0_11 => data_0_0_11, data_0_8 => data_0_0_8, - data_0_28 => data_0_0_28, data_0_17 => data_0_0_17, - data_0_16 => data_0_0_16, data_0_25 => data_0_0_25, - data_0_14 => data_0_0_14, data_0_20 => data_0_0_20, - data_0_27 => data_0_0_27, data_0_30 => data_0_0_30, - data_0_13 => data_0_0_13, data_0_29 => data_0_0_29, - data_0_24 => data_0_0_24, data_0_31 => data_0_0_31, - dataout(35) => dataout(35), dataout(34) => dataout(34), - dataout(33) => dataout(33), dataout(32) => dataout(32), - dataout(31) => dataout(31), dataout(30) => dataout(30), - dataout(29) => dataout(29), dataout(28) => dataout(28), - dataout(27) => dataout(27), dataout(26) => dataout(26), - dataout(25) => dataout(25), dataout(24) => dataout(24), - dataout(23) => dataout(23), dataout(22) => dataout(22), - dataout(21) => dataout(21), dataout(20) => dataout(20), - dataout(19) => dataout(19), dataout(18) => dataout(18), - dataout(17) => dataout(17), dataout(16) => dataout(16), - dataout(15) => dataout(15), dataout(14) => dataout(14), - dataout(13) => dataout(13), dataout(12) => dataout(12), - dataout(11) => dataout(11), dataout(10) => dataout(10), - dataout(9) => dataout(9), dataout(8) => dataout(8), - dataout(7) => dataout(7), dataout(6) => dataout(6), - dataout(5) => dataout(5), dataout(4) => dataout(4), - dataout(3) => dataout(3), dataout(2) => dataout(2), - dataout(1) => dataout(1), dataout(0) => dataout(0), - ctxp_13 => \ctxp[13]\, ctxp_16 => \ctxp[16]\, ctxp_7 => - \ctxp[7]\, ctxp_10 => \ctxp[10]\, ctxp_3 => \ctxp[3]\, - ctxp_8 => \ctxp[8]\, ctxp_19 => \ctxp[19]\, ctxp_17 => - \ctxp[17]\, ctxp_15 => \ctxp[15]\, ctxp_14 => \ctxp[14]\, - ctxp_20 => \ctxp[20]\, ctxp_18 => \ctxp[18]\, ctxp_6 => - \ctxp[6]\, ctxp_21 => \ctxp[21]\, ctxp_11 => \ctxp[11]\, - ctxp_4 => \ctxp[4]\, ctxp_25 => \ctxp[25]\, ctxp_0 => - \ctxp[0]\, ctxp_22 => \ctxp[22]\, ctxp_23 => \ctxp[23]\, - ctxp_24 => \ctxp[24]\, ctxp_5 => \ctxp[5]\, ctxp_12 => - \ctxp[12]\, ctxp_9 => \ctxp[9]\, ctxp_1 => \ctxp[1]\, - ctxp_2 => \ctxp[2]\, diagdata_6 => \diagdata[6]\, - diagdata_7 => \diagdata[7]\, diagdata_1 => \diagdata[1]\, - diagdata_3 => \diagdata[3]\, diagdata_5 => \diagdata[5]\, - diagdata_29 => \diagdata[29]\, diagdata_22 => - \diagdata[22]\, diagdata_27 => \diagdata[27]\, - diagdata_20 => \diagdata[20]\, diagdata_8 => - \diagdata[8]\, diagdata_25 => \diagdata[25]\, diagdata_18 - => \diagdata[18]\, diagdata_31 => \diagdata[31]\, - diagdata_17 => \diagdata[17]\, diagdata_24 => - \diagdata[24]\, diagdata_23 => \diagdata[23]\, - diagdata_21 => \diagdata[21]\, diagdata_16 => - \diagdata[16]\, diagdata_12 => \diagdata[12]\, diagdata_9 - => \diagdata[9]\, diagdata_26 => \diagdata[26]\, - diagdata_0 => \diagdata[0]\, diagdata_19 => - \diagdata[19]\, diagdata_14 => \diagdata[14]\, - diagdata_15 => \diagdata[15]\, diagdata_2 => - \diagdata[2]\, diagdata_13 => \diagdata[13]\, diagdata_30 - => \diagdata[30]\, diagdata_4 => \diagdata[4]\, - diagdata_28 => \diagdata[28]\, address(31) => - \address_0[31]\, address(30) => \address_0[30]\, - address(29) => \address_0[29]\, address(28) => - \address_0[28]\, address(27) => \address_0[27]\, - address(26) => \address_0[26]\, address(25) => - \address_0[25]\, address(24) => \address_0[24]\, - address(23) => \address_0[23]\, address(22) => - \address_0[22]\, address(21) => \address_0[21]\, - address(20) => \address_0[20]\, address(19) => - \address_0[19]\, address(18) => \address_0[18]\, - address(17) => \address_0[17]\, address(16) => - \address_0[16]\, address(15) => \address_0[15]\, - address(14) => \address_0[14]\, address(13) => - \address_0[13]\, address(12) => \address_0[12]\, - address(11) => \address_0[11]\, address(10) => - \address_0[10]\, address(9) => \address_0[9]\, address(8) - => \address_0[8]\, address(7) => \address_0[7]\, - address(6) => \address_0[6]\, address(5) => - \address_0[5]\, address(4) => \address_0[4]\, address(3) - => \address_0[3]\, address(2) => \address_0[2]\, - address(1) => address_1, address(0) => address_0, addr_30 - => addr_28, addr_11 => \addr[11]\, addr_6 => \addr[6]\, - addr_4 => \addr[4]\, addr_7 => \addr[7]\, addr_5 => - \addr[5]\, addr_3 => \addr[3]\, addr_8 => \addr[8]\, - addr_10 => \addr[10]\, addr_9 => \addr[9]\, addr_2 => - \addr[2]\, dataout_0(31) => dataout_0(31), dataout_0(30) - => dataout_0(30), dataout_0(29) => dataout_0(29), - dataout_0(28) => dataout_0(28), dataout_0(27) => - dataout_0(27), dataout_0(26) => dataout_0(26), - dataout_0(25) => dataout_0(25), dataout_0(24) => - dataout_0(24), dataout_0(23) => dataout_0(23), - dataout_0(22) => dataout_0(22), dataout_0(21) => - dataout_0(21), dataout_0(20) => dataout_0(20), - dataout_0(19) => dataout_0(19), dataout_0(18) => - dataout_0(18), dataout_0(17) => dataout_0(17), - dataout_0(16) => dataout_0(16), dataout_0(15) => - dataout_0(15), dataout_0(14) => dataout_0(14), - dataout_0(13) => dataout_0(13), dataout_0(12) => - dataout_0(12), dataout_0(11) => dataout_0(11), - dataout_0(10) => dataout_0(10), dataout_0(9) => - dataout_0(9), dataout_0(8) => dataout_0(8), dataout_0(7) - => dataout_0(7), dataout_0(6) => dataout_0(6), - dataout_0(5) => dataout_0(5), dataout_0(4) => - dataout_0(4), dataout_0(3) => dataout_0(3), dataout_0(2) - => dataout_0(2), dataout_0(1) => dataout_0(1), - dataout_0(0) => dataout_0(0), maddress(31) => - maddress(31), maddress(30) => maddress(30), maddress(29) - => maddress(29), maddress(28) => maddress(28), - maddress(27) => maddress(27), maddress(26) => - maddress(26), maddress(25) => maddress(25), maddress(24) - => maddress(24), maddress(23) => maddress(23), - maddress(22) => maddress(22), maddress(21) => - maddress(21), maddress(20) => maddress(20), maddress(19) - => maddress(19), maddress(18) => maddress(18), - maddress(17) => maddress(17), maddress(16) => - maddress(16), maddress(15) => maddress(15), maddress(14) - => maddress(14), maddress(13) => maddress(13), - maddress(12) => maddress(12), maddress(11) => - maddress(11), maddress(10) => maddress(10), maddress(9) - => maddress(9), maddress(8) => maddress(8), maddress(7) - => maddress(7), maddress(6) => maddress(6), maddress(5) - => maddress(5), maddress(4) => maddress(4), maddress(3) - => maddress(3), maddress(2) => maddress(2), maddress(1) - => maddress(1), maddress(0) => maddress(0), - un1_p0_2_0(498) => un1_p0_2_0_350, ctx_0(7) => \ctx_0[7]\, - ctx_0(6) => \ctx_0[6]\, ctx_0(5) => \ctx_0[5]\, ctx_0(4) - => \ctx_0[4]\, ctx_0(3) => \ctx_0[3]\, ctx_0(2) => - \ctx_0[2]\, ctx_0(1) => \ctx_0[1]\, ctx_0(0) => - \ctx_0[0]\, size_1z => size, enable => enable, N_10 => - N_10, write => write, eenaddr => eenaddr, msu => msu, su - => su_1, read_3 => read, flush_RNIJEN4SI3 => - flush_RNIJEN4SI3, N_415 => N_415, N_351 => N_351, - flush_RNIGBB873 => flush_RNIGBB873, N_192 => N_192, - N_190_0 => N_190, diagrdy => diagrdy, burst_0 => burst_0, - N_264_0 => N_264_0, N_425 => N_425, trans_op_0 => - trans_op_0, flush_op_i_0 => flush_op_i_0, trans_op => - trans_op_1, un2_m_tlb_type => un2_m_tlb_type, tlbdis => - tlbdis, read_2 => read_0, grant => grant_0, N_317_0 => - N_317, N_2886 => N_2886, N_2887 => N_2887, N_270 => N_270, - N_269 => N_269, N_267 => N_267, N_353 => N_353, N_259 => - N_259, N_258 => N_258, N_236_0 => N_236, N_417 => N_417, - N_144 => N_144, N_3846 => N_3846, e => e, N_421_0 => - N_421, N_3305 => N_3305, nf => nf, N_262_0 => N_262_0, - un54_fault_pro_m => un54_fault_pro_m, M_m => M_m, r_N_6 - => r_N_6, vaddr_1_sqmuxa_0_a2_2 => vaddr_1_sqmuxa_0_a2_2, - fault_pro => fault_pro, stpend_RNI6P41NG3 => - stpend_RNI6P41NG3, read_1 => read_1, read_RNIQH64D1 => - read_RNIQH64D1, read_RNIQPCQ11 => read_RNIQPCQ11, - read_RNIRO4K31 => read_RNIRO4K31, N_3389_i_0 => - N_3389_i_0, read_RNI0IQ7R => read_RNI0IQ7R, - read_RNIQFOD21 => read_RNIQFOD21, read_RNI8DFM31 => - read_RNI8DFM31, read_RNIAQJ831 => read_RNIAQJ831, - read_RNI76N8R => read_RNI76N8R, read_RNI7G7G41 => - read_RNI7G7G41, read_RNIMJHQT => read_RNIMJHQT, - read_RNIL633F1 => read_RNIL633F1, read_RNICKHE91 => - read_RNICKHE91, flush_0_1_RNIOMB27S2 => - flush_0_1_RNIOMB27S2, un59_nbo => \un59_nbo\, lock_m => - lock_m, N_2699_i_0 => N_2699_i_0, mexc_1 => mexc_1, - N_3239_i_0 => N_3239_i_0, N_2701 => N_2701, N_2703_i_0 - => N_2703_i_0, N_2714 => N_2714, N_3227_i_0 => - N_3227_i_0, N_3387_i_0 => N_3387_i_0, N_26 => N_26_0, - read_RNIEKS231 => read_RNIEKS231, read_RNIFPFT31 => - read_RNIFPFT31, read_RNIC9O9B1 => read_RNIC9O9B1, - flush_RNIGUM2OH3 => flush_RNIGUM2OH3, read_RNICAQK41 => - read_RNICAQK41, read_RNIQMJI41 => read_RNIQMJI41, - read_RNISLPNU => read_RNISLPNU, read_RNIC70OF1 => - read_RNIC70OF1, read_RNI75LJ31 => read_RNI75LJ31, - read_RNIEEGDD1 => read_RNIEEGDD1, N_12_i_0 => N_12_i_0, - N_16_i_0 => N_16_i_0, N_696 => N_696, N_695 => N_695, - flush_0_1_RNIBUA27S2 => flush_0_1_RNIBUA27S2, - flush_0_1_RNIPTA27S2 => flush_0_1_RNIPTA27S2, N_2702_i_0 - => N_2702_i_0, N_2717 => N_2717, N_2720 => N_2720, N_694 - => N_694, N_2711_i_0 => N_2711_i_0, fsread_i_0 => - fsread_i_0, N_24 => N_24, N_329 => N_329, N_330 => N_330, - N_78_0 => N_78_0, ba => ba, hcache => hcache, cache => - cache, cdwrite_0_sqmuxa_i_0_0 => cdwrite_0_sqmuxa_i_0_0, - lock_0 => lock, un17_casaen_0_0 => un17_casaen_0_0, mexc - => mexc_2, me_nullify2_1_2 => me_nullify2_1_2, - nullify2_0_sqmuxa => nullify2_0_sqmuxa, flush => flush, - hold_0 => hold, fault_pro67 => fault_pro67, req => req_0, - intack => intack, N_523 => N_523, fault_pri => fault_pri, - iflush_1_0_a2_0 => iflush_1_0_a2_0, N_419 => N_419, - N_2709_i_0 => N_2709_i_0, nullify => nullify, flush_i_0 - => flush_i_0, N_293 => N_293, read_0 => read_0_0, rst - => rst, burst => burst_1, accexc_6 => accexc_6, - un1_addout_12 => un1_addout_12, - vaddr_1_sqmuxa_0_a2_4_m1_e_24 => - vaddr_1_sqmuxa_0_a2_4_m1_e_24, G_80_0 => G_80_0, lock => - lock_0, ready => ready_0, mmudci_trans_op_1_sqmuxa_1 => - mmudci_trans_op_1_sqmuxa_1, hold => hold_0, enaddr => - enaddr, N_425_0 => N_425_0_0, N_121 => N_121, N_3254_0 - => N_3254_0, e_0 => e_0, lclk_c => lclk_c); - - a0 : mmu_acache - port map(iosn_2(93) => iosn_2(93), hresp(0) => hresp(0), - hgrant(0) => hgrant(0), hsize_5(1) => hsize_5(1), size(1) - => \size[1]\, iosn_1(93) => iosn_1(93), data_0_18 => - \data_1[18]\, data_0_1 => \data[1]\, data_0_3 => - \data[3]\, data_0_17 => \data[17]\, data_0_22 => - \data_1[22]\, data_0_21 => \data[21]\, data_0_9 => - \data[9]\, data_0_23 => \data_1[23]\, data_0_20 => - \data[20]\, data_0_4 => \data[4]\, data_0_31 => - \data[31]\, data_0_26 => \data[26]\, data_0_15 => - \data[15]\, data_0_7 => \data[7]\, data_0_27 => - \data[27]\, data_0_25 => \data[25]\, data_0_16 => - \data[16]\, data_0_30 => \data[30]\, data_0_28 => - \data[28]\, data_0_14 => \data[14]\, data_0_2 => - \data[2]\, data_0_11 => \data[11]\, data_0_0 => \data[0]\, - data_0_12 => \data[12]\, data_0_6 => \data[6]\, data_0_19 - => \data_1[19]\, data_18 => \data_2[18]\, data_1 => - \data_1[1]\, data_3 => \data_1[3]\, data_17 => - \data_2[17]\, data_22 => \data_2[22]\, data_21 => - \data_2[21]\, data_9 => \data_1[9]\, data_23 => - \data_2[23]\, data_20 => \data_2[20]\, data_4 => - \data_1[4]\, data_31 => \data_2[31]\, data_26 => - \data_2[26]\, data_15 => \data_2[15]\, data_7 => - \data_1[7]\, data_27 => \data_2[27]\, data_25 => - \data_2[25]\, data_16 => \data_2[16]\, data_30 => - \data_2[30]\, data_28 => \data_2[28]\, data_14 => - \data_2[14]\, data_2 => \data_1[2]\, data_11 => - \data_1[11]\, data_0_d0 => \data_1[0]\, data_12 => - \data_2[12]\, data_6 => \data_1[6]\, data_19 => - \data_2[19]\, hwdata_15 => hwdata_15, hwdata_0 => - hwdata_0, hwdata_14 => hwdata_14, hwdata_1 => hwdata_1, - hwdata_28 => hwdata_28, hwdata_23 => hwdata_23, hwdata_12 - => hwdata_12, hwdata_4 => hwdata_4, hwdata_13 => - hwdata_13, hwdata_27 => hwdata_27, hwdata_25 => hwdata_25, - hwdata_11 => hwdata_11, hwdata_9 => hwdata_9, hwdata_3 - => hwdata_3, hwdata_16 => hwdata_16, address_1(31) => - \address_1[31]\, address_1(30) => \address_1[30]\, - address_1(29) => \address_1[29]\, address_1(28) => - \address[28]\, address_1(27) => \address_1[27]\, - address_1(26) => \address_1[26]\, address_1(25) => - \address_1[25]\, address_1(24) => \address_1[24]\, - address_1(23) => \address_1[23]\, address_1(22) => - \address_1[22]\, address_1(21) => \address_1[21]\, - address_1(20) => \address_1[20]\, address_1(19) => - \address_1[19]\, address_1(18) => \address_1[18]\, - address_1(17) => \address_1[17]\, address_1(16) => - \address_1[16]\, address_1(15) => \address_1[15]\, - address_1(14) => \address_1[14]\, address_1(13) => - \address_0[13]\, address_1(12) => \address_1[12]\, - address_1(11) => \address_1[11]\, address_1(10) => - \address_1[10]\, address_1(9) => \address_1[9]\, - address_1(8) => \address_1[8]\, address_1(7) => - \address_1[7]\, address_1(6) => \address_1[6]\, - address_1(5) => \address_0[5]\, address_1(4) => - \address_0[4]\, address_1(3) => \address_1[3]\, - address_1(2) => \address_1[2]\, haddr(31) => haddr(31), - haddr(30) => haddr(30), haddr(29) => haddr(29), haddr(28) - => haddr(28), haddr(27) => haddr(27), haddr(26) => - haddr(26), haddr(25) => haddr(25), haddr(24) => haddr(24), - haddr(23) => haddr(23), haddr(22) => haddr(22), haddr(21) - => haddr(21), haddr(20) => haddr(20), haddr(19) => - haddr(19), haddr(18) => haddr(18), haddr(17) => haddr(17), - haddr(16) => haddr(16), haddr(15) => haddr(15), haddr(14) - => haddr(14), haddr(13) => haddr(13), haddr(12) => - haddr(12), haddr(11) => haddr(11), haddr(10) => haddr(10), - haddr(9) => haddr(9), haddr(8) => haddr(8), haddr(7) => - haddr(7), haddr(6) => haddr(6), haddr(5) => haddr(5), - haddr(4) => haddr(4), haddr(3) => haddr(3), haddr(2) => - haddr(2), address_0(31) => \address[31]\, address_0(30) - => \address[30]\, address_0(29) => \address[29]\, - address_0(28) => \address_1[28]\, address_0(27) => - \address[27]\, address_0(26) => \address[26]\, - address_0(25) => \address[25]\, address_0(24) => - \address[24]\, address_0(23) => \address[23]\, - address_0(22) => \address[22]\, address_0(21) => - \address[21]\, address_0(20) => \address[20]\, - address_0(19) => \address_0[19]\, address_0(18) => - \address_0[18]\, address_0(17) => \address_0[17]\, - address_0(16) => \address_0[16]\, address_0(15) => - \address_0[15]\, address_0(14) => \address_0[14]\, - address_0(13) => \address[13]\, address_0(12) => - \address_0[12]\, address_0(11) => \address_0[11]\, - address_0(10) => \address_0[10]\, address_0(9) => - \address_0[9]\, address_0(8) => \address_0[8]\, - address_0(7) => \address_0[7]\, address_0(6) => - \address_0[6]\, address_0(5) => \address[5]\, - address_0(4) => \address_1[4]\, address_0(3) => - \address_0[3]\, address_0(2) => \address_0[2]\, - htrans_tz(1) => htrans_tz(1), bo_d(3) => \bo_d[3]\, - bo_d(2) => \bo_d[2]\, iosn_0(93) => iosn_0(93), - address(31) => \address_0[31]\, address(30) => - \address_0[30]\, address(29) => \address_0[29]\, - address(28) => \address_0[28]\, address(27) => - \address_0[27]\, address(26) => \address_0[26]\, - address(25) => \address_0[25]\, address(24) => - \address_0[24]\, address(23) => \address_0[23]\, - address(22) => \address_0[22]\, address(21) => - \address_0[21]\, address(20) => \address_0[20]\, - address(19) => \address[19]\, address(18) => - \address[18]\, address(17) => \address[17]\, address(16) - => \address[16]\, address(15) => \address[15]\, - address(14) => \address[14]\, address(13) => - \address_1[13]\, address(12) => \address[12]\, - address(11) => \address[11]\, address(10) => - \address[10]\, address(9) => \address[9]\, address(8) => - \address[8]\, address(7) => \address[7]\, address(6) => - \address[6]\, address(5) => \address_1[5]\, address(4) - => \address[4]\, address(3) => \address[3]\, address(2) - => \address[2]\, htrans(1) => htrans(1), nbo_5_0(1) => - nbo_5_0(1), nbo_5_0(0) => nbo_5_0(0), size_1z => size, - werr => werr, lclk_c => lclk_c, ready_0 => ready, - htrans_0_sqmuxa_2 => htrans_0_sqmuxa_2, mexc_1 => mexc_0, - ready => ready_0, N_466 => N_466, lock => lock, lock_m - => lock_m, hwrite_1_m_0 => hwrite_1_m_0, N_468 => N_468, - N_463 => N_463, N_461 => N_461, N_459 => N_459, N_458 => - N_458, bo_5842_d => bo_5842_d, N_139 => N_139, N_138 => - N_138, un91_nbo_i_0 => un91_nbo_i_0, grant_1 => grant_0, - hcache_1 => hcache, werr_2_m_0 => werr_2_m_0, N_467 => - N_467, N_462 => N_462, N_457 => N_457, mexc_0 => mexc_2, - read_0 => read_2, mexc => mexc_3, un60_nbo => un60_nbo, - hbusreq => hbusreq, lb_0_sqmuxa_1 => lb_0_sqmuxa_1, - N_5054 => N_5054, burst_0 => burst_1, hlock => hlock, - un59_nbo => \un59_nbo\, ba => ba, cache => cache, read - => read_0, burst => burst, req_1 => req, req_0 => req_1, - req => req_0, N_6093_i => N_6093_i, un1_htrans_1_sqmuxa_0 - => un1_htrans_1_sqmuxa_0, grant_0 => grant, grant => - grant_1, rst => rst, bo_5842_d_0 => \bo_5842_d_0\); - - GND_i_0 : GND - port map(Y => GND_0); - - icache0 : mmu_icache - port map(istate_RNIJCMP6(0) => istate_RNIJCMP6(0), - faddr_RNIUT72LB(3) => faddr_RNIUT72LB(3), - vaddress_RNISNAKMI(21) => vaddress_RNISNAKMI(21), - vaddress_RNI6GAKMI(19) => vaddress_RNI6GAKMI(19), - faddr_RNISJSHQA(2) => faddr_RNISJSHQA(2), - vaddress_RNIQNAKMI(20) => vaddress_RNIQNAKMI(20), - faddr_RNI7UFASD(5) => faddr_RNI7UFASD(5), - faddr_RNI0FOJNE(4) => faddr_RNI0FOJNE(4), - faddr_RNIDN2CUE(6) => faddr_RNIDN2CUE(6), ics(1) => - \ics[1]\, ics(0) => \ics[0]\, faddr_RNIKVTLT9(1) => - faddr_RNIKVTLT9(1), vaddress_RNI0GAKMI(16) => - vaddress_RNI0GAKMI(16), vaddress_RNI0OAKMI(23) => - vaddress_RNI0OAKMI(23), vaddress_RNIOFAKMI(12) => - vaddress_RNIOFAKMI(12), vaddress_RNIJG6QR7(4) => - vaddress_RNIJG6QR7(4), un1_p0_2_i_4 => un1_p0_2_i_4, - un1_p0_2_i_0 => un1_p0_2_i_0, ctx_5 => \ctx[5]\, ctx_4 - => \ctx[4]\, ctx_3 => \ctx[3]\, ctx_1 => \ctx[1]\, - ctx_0_d0 => \ctx[0]\, istate_RNI6HPAI(0) => - istate_RNI6HPAI(0), istate_RNIAJH4F(0) => - istate_RNIAJH4F(0), vaddress_RNIUNAKMI(22) => - vaddress_RNIUNAKMI(22), vaddress_RNISFAKMI(14) => - vaddress_RNISFAKMI(14), istate_RNI57KLB(0) => - istate_RNI57KLB(0), istate_RNIUCOFG(0) => - istate_RNIUCOFG(0), faddr_RNI7H6KT8(0) => - faddr_RNI7H6KT8(0), un1_m0_30 => \un1_m0[34]\, un1_m0_5 - => \un1_m0[9]\, un1_m0_9 => \un1_m0[13]\, un1_m0_8 => - \un1_m0[12]\, un1_m0_1 => \un1_m0[5]\, un1_m0_22 => - \un1_m0[26]\, un1_m0_6 => \un1_m0[10]\, un1_m0_0 => - \un1_m0[4]\, un1_m0_17 => \un1_m0[21]\, un1_m0_16 => - \un1_m0[20]\, un1_m0_7 => \un1_m0[11]\, un1_m0_4 => - \un1_m0[8]\, un1_m0_2 => \un1_m0[6]\, un1_m0_3 => - \un1_m0[7]\, istate_RNIH0NBI(0) => istate_RNIH0NBI(0), - istate_RNIG7IIA(0) => istate_RNIG7IIA(0), - vaddress_RNIFCB8U6(3) => vaddress_RNIFCB8U6(3), - istate_RNI2MM6D(0) => istate_RNI2MM6D(0), - istate_RNI8BL1A(0) => istate_RNI8BL1A(0), - istate_RNILTAC8(0) => istate_RNILTAC8(0), - istate_RNIK9NF8(0) => istate_RNIK9NF8(0), - vaddress_RNI4GAKMI(18) => vaddress_RNI4GAKMI(18), - vaddress_RNI2GAKMI(17) => vaddress_RNI2GAKMI(17), - istate_RNI5V68H(0) => istate_RNI5V68H(0), - istate_RNIM2DE7(0) => istate_RNIM2DE7(0), - istate_RNIVTQIJ(0) => istate_RNIVTQIJ(0), - istate_RNIOVC5J(0) => istate_RNIOVC5J(0), - istate_RNI6PSS1(0) => istate_RNI6PSS1(0), - istate_RNIGUTA8(0) => istate_RNIGUTA8(0), - istate_RNIMRTH8(0) => istate_RNIMRTH8(0), - vaddress_RNIQFAKMI(13) => vaddress_RNIQFAKMI(13), - istate_RNIAP6PI(0) => istate_RNIAP6PI(0), - istate_RNIENB3M(0) => istate_RNIENB3M(0), - istate_RNIS4VK8(0) => istate_RNIS4VK8(0), - istate_RNIRASC8(0) => istate_RNIRASC8(0), - istate_RNIJSOBE(0) => istate_RNIJSOBE(0), - istate_RNIR2JU8(0) => istate_RNIR2JU8(0), - istate_RNIOJJE1(0) => istate_RNIOJJE1(0), - istate_RNIN6957(0) => istate_RNIN6957(0), - istate_RNIKJBN8(0) => istate_RNIKJBN8(0), - istate_RNI6LOO6(0) => istate_RNI6LOO6(0), - istate_RNIV33V9(0) => istate_RNIV33V9(0), - istate_RNI7BUID(0) => istate_RNI7BUID(0), - istate_RNIEC82C(0) => istate_RNIEC82C(0), maddress_0_2 - => maddress_0_2, maddress_0_0 => maddress_0_0, - istate_RNIPSU8G(0) => istate_RNIPSU8G(0), diagdata_6 => - \diagdata[6]\, diagdata_15 => \diagdata[15]\, diagdata_4 - => \diagdata[4]\, diagdata_19 => \diagdata[19]\, - diagdata_18 => \diagdata[18]\, diagdata_17 => - \diagdata[17]\, diagdata_16 => \diagdata[16]\, - diagdata_20 => \diagdata[20]\, diagdata_26 => - \diagdata[26]\, diagdata_25 => \diagdata[25]\, - diagdata_22 => \diagdata[22]\, diagdata_14 => - \diagdata[14]\, diagdata_12 => \diagdata[12]\, diagdata_9 - => \diagdata[9]\, diagdata_8 => \diagdata[8]\, - diagdata_5 => \diagdata[5]\, diagdata_3 => \diagdata[3]\, - diagdata_0 => \diagdata[0]\, diagdata_7 => \diagdata[7]\, - diagdata_27 => \diagdata[27]\, diagdata_23 => - \diagdata[23]\, diagdata_24 => \diagdata[24]\, - diagdata_31 => \diagdata[31]\, diagdata_29 => - \diagdata[29]\, diagdata_28 => \diagdata[28]\, - diagdata_21 => \diagdata[21]\, diagdata_13 => - \diagdata[13]\, diagdata_2 => \diagdata[2]\, diagdata_30 - => \diagdata[30]\, diagdata_1 => \diagdata[1]\, - hrdata_26 => hrdata_31, hrdata_25 => hrdata_30, hrdata_24 - => hrdata_29, hrdata_23 => hrdata_28, hrdata_1 => - hrdata_6, hrdata_0_d0 => hrdata_5, vaddress_RNI8EVQ36(2) - => vaddress_RNI8EVQ36(2), rpc_6 => rpc_6, rpc_5 => rpc_5, - rpc_8 => rpc_8, rpc_7 => rpc_7, rpc_2 => rpc_2, rpc_3 => - rpc_3, rpc_1 => rpc_1, rpc_0 => rpc_0, addr(11) => - \addr[11]\, addr(10) => \addr[10]\, addr(9) => \addr[9]\, - addr(8) => \addr[8]\, addr(7) => \addr[7]\, addr(6) => - \addr[6]\, addr(5) => \addr[5]\, addr(4) => \addr[4]\, - addr(3) => \addr[3]\, addr(2) => \addr[2]\, data_0(31) - => data_0(31), data_0(30) => data_0(30), data_0(29) => - data_0(29), data_0(28) => data_0(28), data_0(27) => - data_0(27), data_0(26) => data_0(26), data_0(25) => - data_0(25), data_0(24) => data_0(24), data_0(23) => - data_0(23), data_0(22) => data_0(22), data_0(21) => - data_0(21), data_0(20) => data_0(20), data_0(19) => - data_0(19), data_0(18) => data_0(18), data_0(17) => - data_0(17), data_0(16) => data_0(16), data_0(15) => - data_0(15), data_0(14) => data_0(14), data_0(13) => - data_0(13), data_0(12) => data_0(12), data_0(11) => - data_0(11), data_0(10) => data_0(10), data_0(9) => - data_0(9), data_0(8) => data_0(8), data_0(7) => data_0(7), - data_0(6) => data_0(6), data_0(5) => data_0(5), data_0(4) - => data_0(4), data_0(3) => data_0(3), data_0(2) => - data_0(2), data_0(1) => data_0(1), data_0(0) => data_0(0), - hrdata_0_3 => hrdata_0_3, hrdata_0_24 => hrdata_0_24, - hrdata_0_4 => hrdata_0_4, hrdata_0_18 => hrdata_0_18, - hrdata_0_17 => hrdata_0_17, hrdata_0_16 => hrdata_0_16, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_14 => hrdata_0_14, hrdata_0_13 => hrdata_0_13, - hrdata_0_9 => hrdata_0_9, hrdata_0_8 => hrdata_0_8, - hrdata_0_21 => hrdata_0_21, hrdata_0_27 => hrdata_0_27, - hrdata_0_12 => hrdata_0_12, hrdata_0_11 => hrdata_0_11, - hrdata_0_10 => hrdata_0_10, hrdata_0_7 => hrdata_0_7, - hrdata_0_1 => hrdata_0_1, hrdata_0_2 => hrdata_0_2, - hrdata_0_26 => hrdata_0_26, hrdata_0_0 => hrdata_0_0, - hrdata_0_15 => hrdata_0_15, istate_RNIA8N5H(0) => - istate_RNIA8N5H(0), vaddress_RNIUFAKMI(15) => - vaddress_RNIUFAKMI(15), vitdatain_0_1_0(22) => - vitdatain_0_1_0(22), fault_isid_1_i(0) => - \fault_isid_1_i[0]\, dataout_1(31) => dataout_1(31), - dataout_1(30) => dataout_1(30), dataout_1(29) => - dataout_1(29), dataout_1(28) => dataout_1(28), - dataout_1(27) => dataout_1(27), dataout_1(26) => - dataout_1(26), dataout_1(25) => dataout_1(25), - dataout_1(24) => dataout_1(24), dataout_1(23) => - dataout_1(23), dataout_1(22) => dataout_1(22), - dataout_1(21) => dataout_1(21), dataout_1(20) => - dataout_1(20), dataout_1(19) => dataout_1(19), - dataout_1(18) => dataout_1(18), dataout_1(17) => - dataout_1(17), dataout_1(16) => dataout_1(16), - dataout_1(15) => dataout_1(15), dataout_1(14) => - dataout_1(14), dataout_1(13) => dataout_1(13), - dataout_1(12) => dataout_1(12), dataout_1(11) => - dataout_1(11), dataout_1(10) => dataout_1(10), - dataout_1(9) => dataout_1(9), dataout_1(8) => - dataout_1(8), dataout_1(7) => dataout_1(7), dataout_1(6) - => dataout_1(6), dataout_1(5) => dataout_1(5), - dataout_1(4) => dataout_1(4), dataout_1(3) => - dataout_1(3), dataout_1(2) => dataout_1(2), dataout_1(1) - => dataout_1(1), dataout_1(0) => dataout_1(0), - dataout_0(35) => dataout_0(35), dataout_0(34) => - dataout_0(34), dataout_0(33) => dataout_0(33), - dataout_0(32) => dataout_0(32), ctx_0_5 => \ctx_0[7]\, - ctx_0_0 => \ctx_0[2]\, ctx_0_4 => \ctx_0[6]\, address(31) - => \address[31]\, address(30) => \address[30]\, - address(29) => \address[29]\, address(28) => - \address[28]\, address(27) => \address[27]\, address(26) - => \address[26]\, address(25) => \address[25]\, - address(24) => \address[24]\, address(23) => - \address[23]\, address(22) => \address[22]\, address(21) - => \address[21]\, address(20) => \address[20]\, - address(19) => \address[19]\, address(18) => - \address[18]\, address(17) => \address[17]\, address(16) - => \address[16]\, address(15) => \address[15]\, - address(14) => \address[14]\, address(13) => - \address[13]\, address(12) => \address[12]\, address(11) - => \address[11]\, address(10) => \address[10]\, - address(9) => \address[9]\, address(8) => \address[8]\, - address(7) => \address[7]\, address(6) => \address[6]\, - address(5) => \address[5]\, address(4) => \address[4]\, - address(3) => \address[3]\, address(2) => \address[2]\, - bo_d(3) => \bo_d[3]\, un1_p0_6(0) => un1_p0_6(0), - maddress(31) => maddress(31), maddress(30) => - maddress(30), maddress(29) => maddress(29), maddress(28) - => maddress(28), maddress(27) => maddress(27), - maddress(26) => maddress(26), maddress(25) => - maddress(25), maddress(24) => maddress(24), maddress(23) - => maddress(23), maddress(22) => maddress(22), - maddress(21) => maddress(21), maddress(20) => - maddress(20), maddress(19) => maddress(19), maddress(18) - => maddress(18), maddress(17) => maddress(17), - maddress(16) => maddress(16), maddress(15) => - maddress(15), maddress(14) => maddress(14), maddress(13) - => maddress(13), maddress(12) => maddress(12), - maddress(11) => maddress(11), maddress(10) => - maddress(10), maddress(9) => maddress(9), maddress(8) => - maddress(8), maddress(7) => maddress(7), maddress(6) => - maddress(6), maddress(5) => maddress(5), maddress(4) => - maddress(4), maddress(3) => maddress(3), maddress(2) => - maddress(2), maddress(1) => maddress(1), maddress(0) => - maddress(0), dataout_2(31) => dataout_2(31), - dataout_2(30) => dataout_2(30), dataout_2(29) => - dataout_2(29), dataout_2(28) => dataout_2(28), - dataout_2(27) => dataout_2(27), dataout_2(26) => - dataout_2(26), dataout_2(25) => dataout_2(25), - dataout_2(24) => dataout_2(24), dataout_2(23) => - dataout_2(23), dataout_2(22) => dataout_2(22), - dataout_2(21) => dataout_2(21), dataout_2(20) => - dataout_2(20), dataout_2(19) => dataout_2(19), - dataout_2(18) => dataout_2(18), dataout_2(17) => - dataout_2(17), dataout_2(16) => dataout_2(16), - dataout_2(15) => dataout_2(15), dataout_2(14) => - dataout_2(14), dataout_2(13) => dataout_2(13), - dataout_2(12) => dataout_2(12), dataout_2(11) => - dataout_2(11), dataout_2(10) => dataout_2(10), - dataout_2(9) => dataout_2(9), dataout_2(8) => - dataout_2(8), dataout_2(7) => dataout_2(7), dataout_2(6) - => dataout_2(6), dataout_2(5) => dataout_2(5), - dataout_2(4) => dataout_2(4), dataout_2(3) => - dataout_2(3), dataout_2(2) => dataout_2(2), dataout_2(1) - => dataout_2(1), dataout_2(0) => dataout_2(0), fpc(31) - => fpc(31), fpc(30) => fpc(30), fpc(29) => fpc(29), - fpc(28) => fpc(28), fpc(27) => fpc(27), fpc(26) => - fpc(26), fpc(25) => fpc(25), fpc(24) => fpc(24), fpc(23) - => fpc(23), fpc(22) => fpc(22), fpc(21) => fpc(21), - fpc(20) => fpc(20), fpc(19) => fpc(19), fpc(18) => - fpc(18), fpc(17) => fpc(17), fpc(16) => fpc(16), fpc(15) - => fpc(15), fpc(14) => fpc(14), fpc(13) => fpc(13), - fpc(12) => fpc(12), fpc(11) => fpc(11), fpc(10) => - fpc(10), fpc(9) => fpc(9), fpc(8) => fpc(8), fpc(7) => - fpc(7), fpc(6) => fpc(6), fpc(5) => fpc(5), fpc(4) => - fpc(4), fpc(3) => fpc(3), fpc(2) => fpc(2), asi(0) => - \asi[0]\, un1_p0_2_0(148) => un1_p0_2_0_0, su_0 => su, - diagrdy => diagrdy, hold_0 => hold, mexc_0 => mexc, - fbranch => fbranch, rbranch => rbranch, flush2_RNIFMGM2 - => flush2_RNIFMGM2, N_425_1 => N_425, flush2_RNI5I3N7 - => flush2_RNI5I3N7, N_984 => N_984, N_980 => N_980, N_28 - => N_28, N_987 => N_987, N_986 => N_986, e => e, flush2 - => flush2, N_26 => N_26, flush2_0_0_RNI146O2 => - flush2_0_0_RNI146O2, flush2_0_0_RNI7G6O2 => - flush2_0_0_RNI7G6O2, flush2_0_0_RNIVV5O2 => - flush2_0_0_RNIVV5O2, flush2_0_0_RNITR5O2 => - flush2_0_0_RNITR5O2, flush2_0_0_RNIPJ5O2 => - flush2_0_0_RNIPJ5O2, mds => mds, su => su_0, nf => nf, - N_981 => N_981, N_429 => N_429, N_359 => N_359, N_2626 - => N_2626, N_43 => N_43, N_427 => N_427, N_2625 => - N_2625, N_6093_i => N_6093_i, N_423 => N_423, N_425 => - N_425_0, N_45 => N_45, N_2623 => N_2623, N_365 => N_365, - N_357 => N_357, N_985 => N_985, N_983 => N_983, N_982 => - N_982, N_363 => N_363, N_321 => N_321, N_319 => N_319, - N_361 => N_361, N_2624 => N_2624, N_264_0 => N_264_0, - N_262_0 => N_262_0, N_78_0 => N_78_0, inull => inull, - hold => hold_0, ldlock_3_0 => ldlock_3_0, - un9_icc_check_bp => un9_icc_check_bp, trans_op_0 => - trans_op, flush_op_i_0 => flush_op_i_0, un2_m_tlb_type - => un2_m_tlb_type, stpend_RNI6P41NG3 => - stpend_RNI6P41NG3, vaddr_1_sqmuxa_0_a2_2 => - vaddr_1_sqmuxa_0_a2_2, ldlock_2 => ldlock_2, - xc_exception_1_0 => xc_exception_1_0, grant => grant, - iflush_1_0_a2_0 => iflush_1_0_a2_0, N_121 => N_121, - un1_ici => un1_ici, fault_trans_RNIA0K0D1 => - fault_trans_RNIA0K0D1, N_66_0 => N_66_0, de_hold_pc_1 => - de_hold_pc_1, N_425_0 => N_425_0_0, flush_0 => flush, - flush => flush_0, trans_op => trans_op_0, ba => ba, - hcache => hcache, mexc => mexc_0, req => req, e_0 => e_0, - hold_pc_7 => hold_pc_7, istate_0_sqmuxa => - istate_0_sqmuxa, flush_i_0 => flush_i_0, N_523 => N_523, - ready => ready, burst_0 => burst, burst => burst_0, rst - => rst, un81_m_tlb_type => un81_m_tlb_type, holdn => - holdn, cdwrite_0_sqmuxa_i_0_0 => cdwrite_0_sqmuxa_i_0_0, - N_66 => N_66, enable => enable, lclk_c => lclk_c); - - VCC_i : VCC - port map(Y => \VCC\); - - \mmugen.m0\ : mmu - port map(ctxp(25) => \ctxp[25]\, ctxp(24) => \ctxp[24]\, - ctxp(23) => \ctxp[23]\, ctxp(22) => \ctxp[22]\, ctxp(21) - => \ctxp[21]\, ctxp(20) => \ctxp[20]\, ctxp(19) => - \ctxp[19]\, ctxp(18) => \ctxp[18]\, ctxp(17) => - \ctxp[17]\, ctxp(16) => \ctxp[16]\, ctxp(15) => - \ctxp[15]\, ctxp(14) => \ctxp[14]\, ctxp(13) => - \ctxp[13]\, ctxp(12) => \ctxp[12]\, ctxp(11) => - \ctxp[11]\, ctxp(10) => \ctxp[10]\, ctxp(9) => \ctxp[9]\, - ctxp(8) => \ctxp[8]\, ctxp(7) => \ctxp[7]\, ctxp(6) => - \ctxp[6]\, ctxp(5) => \ctxp[5]\, ctxp(4) => \ctxp[4]\, - ctxp(3) => \ctxp[3]\, ctxp(2) => \ctxp[2]\, ctxp(1) => - \ctxp[1]\, ctxp(0) => \ctxp[0]\, iosn_0(93) => iosn_0(93), - data_0 => \data_1[0]\, data_1_d0 => \data_1[1]\, - data_2_d0 => \data_1[2]\, data_3 => \data_1[3]\, data_4 - => \data_1[4]\, data_6 => \data_1[6]\, data_7 => - \data_1[7]\, data_8 => data_1_8, data_9 => \data_1[9]\, - data_10 => data_1_10, data_11 => \data_1[11]\, data_2(31) - => \data_2[31]\, data_2(30) => \data_2[30]\, data_2(29) - => data_2_17, data_2(28) => \data_2[28]\, data_2(27) => - \data_2[27]\, data_2(26) => \data_2[26]\, data_2(25) => - \data_2[25]\, data_2(24) => data_2_12, data_2(23) => - \data_2[23]\, data_2(22) => \data_2[22]\, data_2(21) => - \data_2[21]\, data_2(20) => \data_2[20]\, data_2(19) => - \data_2[19]\, data_2(18) => \data_2[18]\, data_2(17) => - \data_2[17]\, data_2(16) => \data_2[16]\, data_2(15) => - \data_2[15]\, data_2(14) => \data_2[14]\, data_2(13) => - data_2_1, data_2(12) => \data_2[12]\, data_RNIKU1T4(16) - => \data_RNIKU1T4[16]\, maddress(31) => maddress(31), - maddress(30) => maddress(30), maddress(29) => - maddress(29), maddress(28) => maddress(28), maddress(27) - => maddress(27), maddress(26) => maddress(26), - maddress(25) => maddress(25), maddress(24) => - maddress(24), maddress(23) => maddress(23), maddress(22) - => maddress(22), maddress(21) => maddress(21), - maddress(20) => maddress(20), maddress(19) => - maddress(19), maddress(18) => maddress(18), maddress(17) - => maddress(17), maddress(16) => maddress(16), - maddress(15) => maddress(15), maddress(14) => - maddress(14), maddress(13) => maddress(13), maddress(12) - => maddress(12), data_1(31) => \data_1[31]\, data_1(30) - => \data_1[30]\, data_1(29) => \data_1[29]\, data_1(28) - => \data_1[28]\, data_1(27) => \data_1[27]\, data_1(26) - => \data_1[26]\, data_1(25) => \data_1[25]\, data_1(24) - => \data_1[24]\, data_1(23) => \data[23]\, data_1(22) - => \data[22]\, data_1(21) => \data_1[21]\, data_1(20) - => \data_1[20]\, data_1(19) => \data[19]\, data_1(18) - => \data[18]\, data_1(17) => \data_1[17]\, data_1(16) - => \data_1[16]\, data_1(15) => \data_1[15]\, data_1(14) - => \data_1[14]\, data_1(13) => \data_1[13]\, data_1(12) - => \data_1[12]\, LVL_RNIT69H911(0) => - \LVL_RNIT69H911[0]\, data_1_3_i_a3_6_2 => - \data_1_3_i_a3_6[27]\, data_1_3_i_a3_6_4 => - \data_1_3_i_a3_6[29]\, data_1_3_i_a3_6_1 => - \data_1_3_i_a3_6[26]\, data_1_3_i_a3_6_0 => - \data_1_3_i_a3_6[25]\, hrdata_5 => hrdata_5, hrdata_7 => - hrdata_7, hrdata_4 => hrdata_4, hrdata_3 => hrdata_3, - hrdata_2 => hrdata_2, hrdata_31 => hrdata_31, hrdata_30 - => hrdata_30, hrdata_29 => hrdata_29, hrdata_28 => - hrdata_28, hrdata_27 => hrdata_27, hrdata_26 => hrdata_26, - hrdata_23 => hrdata_23, hrdata_22 => hrdata_22, hrdata_21 - => hrdata_21, hrdata_18 => hrdata_18, hrdata_16 => - hrdata_16, hrdata_15 => hrdata_15, hrdata_12 => hrdata_12, - hrdata_8 => hrdata_8, hrdata_1 => hrdata_1, hrdata_0_d0 - => hrdata_0_d0, hrdata_6 => hrdata_6, hrdata_24 => - hrdata_24, hrdata_17 => hrdata_17, hrdata_14 => hrdata_14, - hrdata_13 => hrdata_13, hrdata_11 => hrdata_11, hrdata_10 - => hrdata_10, hrdata_9 => hrdata_9, hrdata_0_0 => - hrdata_0_0, hrdata_0_3 => hrdata_0_3, hrdata_0_4 => - hrdata_0_4, hrdata_0_2 => hrdata_0_2, hrdata_0_22 => - hrdata_0_22, hrdata_0_23 => hrdata_0_23, hrdata_0_27 => - hrdata_0_27, hrdata_0_8 => hrdata_0_8, hrdata_0_9 => - hrdata_0_9, hrdata_0_10 => hrdata_0_10, hrdata_0_11 => - hrdata_0_11, hrdata_0_13 => hrdata_0_13, hrdata_0_15 => - hrdata_0_15, hrdata_0_16 => hrdata_0_16, hrdata_0_14 => - hrdata_0_14, hrdata_0_17 => hrdata_0_17, hrdata_0_1 => - hrdata_0_1, hrdata_0_24 => hrdata_0_24, hrdata_0_12 => - hrdata_0_12, hrdata_0_18 => hrdata_0_18, hrdata_0_21 => - hrdata_0_21, hrdata_0_26 => hrdata_0_26, hrdata_0_7 => - hrdata_0_7, address_0(31) => \address[31]\, address_0(30) - => \address[30]\, address_0(29) => \address[29]\, - address_0(28) => \address[28]\, address_0(27) => - \address[27]\, address_0(26) => \address[26]\, - address_0(25) => \address[25]\, address_0(24) => - \address[24]\, address_0(23) => \address[23]\, - address_0(22) => \address[22]\, address_0(21) => - \address[21]\, address_0(20) => \address[20]\, - address_0(19) => \address[19]\, address_0(18) => - \address[18]\, address_0(17) => \address[17]\, - address_0(16) => \address[16]\, address_0(15) => - \address[15]\, address_0(14) => \address[14]\, - address_0(13) => \address[13]\, address_0(12) => - \address[12]\, address_0(11) => \address[11]\, - address_0(10) => \address[10]\, address_0(9) => - \address[9]\, address_0(8) => \address[8]\, address_0(7) - => \address[7]\, address_0(6) => \address[6]\, - address_0(5) => \address[5]\, address_0(4) => - \address[4]\, address_0(3) => \address[3]\, address_0(2) - => \address[2]\, un1_m0_2_d0 => \un1_m0[6]\, un1_m0_3 - => \un1_m0[7]\, un1_m0_4 => \un1_m0[8]\, un1_m0_7 => - \un1_m0[11]\, un1_m0_16 => \un1_m0[20]\, un1_m0_17 => - \un1_m0[21]\, un1_m0_0 => \un1_m0[4]\, un1_m0_6 => - \un1_m0[10]\, un1_m0_22 => \un1_m0[26]\, un1_m0_1 => - \un1_m0[5]\, un1_m0_5 => \un1_m0[9]\, un1_m0_8 => - \un1_m0[12]\, un1_m0_9 => \un1_m0[13]\, un1_m0_30 => - \un1_m0[34]\, ctx(7) => \ctx[7]\, ctx(6) => \ctx[6]\, - ctx(5) => \ctx[5]\, ctx(4) => \ctx[4]\, ctx(3) => - \ctx[3]\, ctx(2) => \ctx[2]\, ctx(1) => \ctx[1]\, ctx(0) - => \ctx[0]\, ctx_0(7) => \ctx_0[7]\, ctx_0(6) => - \ctx_0[6]\, ctx_0(5) => \ctx_0[5]\, ctx_0(4) => - \ctx_0[4]\, ctx_0(3) => \ctx_0[3]\, ctx_0(2) => - \ctx_0[2]\, ctx_0(1) => \ctx_0[1]\, ctx_0(0) => - \ctx_0[0]\, address(31) => \address_1[31]\, address(30) - => \address_1[30]\, address(29) => \address_1[29]\, - address(28) => \address_1[28]\, address(27) => - \address_1[27]\, address(26) => \address_1[26]\, - address(25) => \address_1[25]\, address(24) => - \address_1[24]\, address(23) => \address_1[23]\, - address(22) => \address_1[22]\, address(21) => - \address_1[21]\, address(20) => \address_1[20]\, - address(19) => \address_1[19]\, address(18) => - \address_1[18]\, address(17) => \address_1[17]\, - address(16) => \address_1[16]\, address(15) => - \address_1[15]\, address(14) => \address_1[14]\, - address(13) => \address_1[13]\, address(12) => - \address_1[12]\, address(11) => \address_1[11]\, - address(10) => \address_1[10]\, address(9) => - \address_1[9]\, address(8) => \address_1[8]\, address(7) - => \address_1[7]\, address(6) => \address_1[6]\, - address(5) => \address_1[5]\, address(4) => - \address_1[4]\, address(3) => \address_1[3]\, address(2) - => \address_1[2]\, hrdata_1_0_1(1) => hrdata_1_0_1(1), - un1_m0_2_23 => \un1_m0_2[24]\, un1_m0_2_15 => - \un1_m0_2[16]\, un1_m0_2_31 => \un1_m0_2[32]\, - un1_m0_2_33 => \un1_m0_2[34]\, un1_m0_2_1 => - \un1_m0_2[2]\, un1_m0_2_2 => \un1_m0_2[3]\, un1_m0_2_3 - => \un1_m0_2[4]\, un1_m0_2_4 => \un1_m0_2[5]\, - un1_m0_2_5 => \un1_m0_2[6]\, un1_m0_2_6 => \un1_m0_2[7]\, - un1_m0_2_8 => \un1_m0_2[9]\, un1_m0_2_11 => - \un1_m0_2[12]\, un1_m0_2_12 => \un1_m0_2[13]\, - un1_m0_2_18 => \un1_m0_2[19]\, un1_m0_2_29 => - \un1_m0_2[30]\, un1_m0_2_19 => \un1_m0_2[20]\, un1_m0_2_9 - => \un1_m0_2[10]\, un1_m0_2_10 => \un1_m0_2[11]\, - un1_m0_2_7 => \un1_m0_2[8]\, un1_m0_2_75 => - \un1_m0_2[76]\, un1_m0_2_76 => \un1_m0_2[77]\, - un1_m0_2_77 => \un1_m0_2[78]\, un1_m0_2_78 => - \un1_m0_2[79]\, un1_m0_2_79 => \un1_m0_2[80]\, - un1_m0_2_80 => \un1_m0_2[81]\, un1_m0_2_81 => - \un1_m0_2[82]\, un1_m0_2_82 => \un1_m0_2[83]\, - un1_m0_2_83 => \un1_m0_2[84]\, un1_m0_2_84 => - \un1_m0_2[85]\, un1_m0_2_85 => \un1_m0_2[86]\, - un1_m0_2_86 => \un1_m0_2[87]\, un1_m0_2_97 => - \un1_m0_2[98]\, un1_m0_2_96 => \un1_m0_2[97]\, - un1_m0_2_95 => \un1_m0_2[96]\, un1_m0_2_93 => - \un1_m0_2[94]\, un1_m0_2_108 => \un1_m0_2[109]\, - un1_m0_2_91 => \un1_m0_2[92]\, un1_m0_2_106 => - \un1_m0_2[107]\, un1_m0_2_92 => \un1_m0_2[93]\, - un1_m0_2_98 => \un1_m0_2[99]\, un1_m0_2_94 => - \un1_m0_2[95]\, un1_m0_2_44 => \un1_m0_2[45]\, - un1_m0_2_43 => \un1_m0_2[44]\, un1_m0_2_73 => - \un1_m0_2[74]\, un1_m0_2_72 => \un1_m0_2[73]\, - un1_m0_2_71 => \un1_m0_2[72]\, un1_m0_2_70 => - \un1_m0_2[71]\, un1_m0_2_69 => \un1_m0_2[70]\, - un1_m0_2_68 => \un1_m0_2[69]\, un1_m0_2_67 => - \un1_m0_2[68]\, un1_m0_2_66 => \un1_m0_2[67]\, - un1_m0_2_65 => \un1_m0_2[66]\, un1_m0_2_64 => - \un1_m0_2[65]\, un1_m0_2_63 => \un1_m0_2[64]\, - un1_m0_2_62 => \un1_m0_2[63]\, un1_m0_2_61 => - \un1_m0_2[62]\, un1_m0_2_60 => \un1_m0_2[61]\, - un1_m0_2_59 => \un1_m0_2[60]\, un1_m0_2_58 => - \un1_m0_2[59]\, un1_m0_2_57 => \un1_m0_2[58]\, - un1_m0_2_56 => \un1_m0_2[57]\, un1_m0_2_55 => - \un1_m0_2[56]\, un1_m0_2_54 => \un1_m0_2[55]\, - un1_m0_2_40 => \un1_m0_2[41]\, un1_m0_2_42 => - \un1_m0_2[43]\, un1_m0_2_35 => \un1_m0_2[36]\, - un1_m0_2_36 => \un1_m0_2[37]\, un1_m0_2_34 => - \un1_m0_2[35]\, un1_m0_2_39 => \un1_m0_2[40]\, - un1_m0_2_38 => \un1_m0_2[39]\, un1_m0_2_37 => - \un1_m0_2[38]\, un1_m0_2_0_d0 => \un1_m0_2[1]\, - un1_m0_2_41 => \un1_m0_2[42]\, fault_isid_1_i(0) => - \fault_isid_1_i[0]\, un1_m0_2_0(35) => \un1_m0_2_0[35]\, - mexc => mexc_3, req => req_1, ba => ba, bo_5842_d_0 => - \bo_5842_d_0\, read_0 => read_2, grant => grant_1, su_0 - => su_1, read => read, N_421 => N_421, N_419 => N_419, - N_417 => N_417, N_415 => N_415, N_353 => N_353, N_351 => - N_351, N_317 => N_317, N_293 => N_293, N_236 => N_236, - N_192 => N_192, N_190 => N_190, N_2887 => N_2887, N_2886 - => N_2886, N_2701 => N_2701, fault_pro67 => fault_pro67, - M_m => M_m, e => e, N_2720 => N_2720, N_2717 => N_2717, - N_2714 => N_2714, G_80_0 => G_80_0, N_2703_i_0 => - N_2703_i_0, N_2699_i_0 => N_2699_i_0, un54_fault_pro_m - => un54_fault_pro_m, accexc_6 => accexc_6, fault_pro => - fault_pro, fault_pri_0 => fault_pri, N_2709_i_0 => - N_2709_i_0, N_2711_i_0 => N_2711_i_0, N_2702_i_0 => - N_2702_i_0, N_696 => N_696, N_695 => N_695, N_694 => - N_694, N_359 => N_359, N_357 => N_357, N_365 => N_365, - N_363 => N_363, N_361 => N_361, N_321 => N_321, N_319 => - N_319, N_45 => N_45, N_2624 => N_2624, N_2623 => N_2623, - N_425 => N_425_0, N_423 => N_423, N_43 => N_43, N_2626 - => N_2626, N_427 => N_427, N_429 => N_429, N_262_0 => - N_262_0, N_78_0 => N_78_0, N_264_0 => N_264_0, tlbdis => - tlbdis, N_2625 => N_2625, su => su_0, N_78 => N_78, N_262 - => N_262, N_264 => N_264, mmu_VCC => mmu_cache_VCC, - fsread_i_0 => fsread_i_0, trans_op_2 => trans_op_1, - flush_op_i_0 => flush_op_i_0, mmudci_trans_op_1_sqmuxa_1 - => mmudci_trans_op_1_sqmuxa_1, N_66 => N_66, trans_op_1 - => trans_op_0, un2_m_tlb_type => un2_m_tlb_type, flush - => flush_0, trans_op => trans_op, istate_0_sqmuxa => - istate_0_sqmuxa, un81_m_tlb_type => un81_m_tlb_type, rst - => rst, N_546 => N_546, N_66_0 => N_66_0, - fault_trans_RNIA0K0D1 => fault_trans_RNIA0K0D1, lclk_c - => lclk_c); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proc3 is - - port( istate_RNIJCMP6 : out std_logic_vector(0 to 0); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - un1_p0_2_i_4 : out std_logic; - un1_p0_2_i_0 : out std_logic; - ctx : out std_logic_vector(7 downto 0); - istate_RNI6HPAI : out std_logic_vector(0 to 0); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - istate_RNI57KLB : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - istate_RNIH0NBI : out std_logic_vector(0 to 0); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - istate_RNI5V68H : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIEC82C : out std_logic_vector(0 to 0); - istate_RNIPSU8G : out std_logic_vector(0 to 0); - hrdata_31 : in std_logic; - hrdata_30 : in std_logic; - hrdata_29 : in std_logic; - hrdata_28 : in std_logic; - hrdata_6 : in std_logic; - hrdata_5 : in std_logic; - hrdata_7 : in std_logic; - hrdata_4 : in std_logic; - hrdata_3 : in std_logic; - hrdata_2 : in std_logic; - hrdata_27 : in std_logic; - hrdata_26 : in std_logic; - hrdata_23 : in std_logic; - hrdata_22 : in std_logic; - hrdata_21 : in std_logic; - hrdata_18 : in std_logic; - hrdata_16 : in std_logic; - hrdata_15 : in std_logic; - hrdata_12 : in std_logic; - hrdata_8 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_24 : in std_logic; - hrdata_17 : in std_logic; - hrdata_14 : in std_logic; - hrdata_13 : in std_logic; - hrdata_11 : in std_logic; - hrdata_10 : in std_logic; - hrdata_9 : in std_logic; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - hrdata_0_3 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_15 : in std_logic; - istate_RNIA8N5H : out std_logic_vector(0 to 0); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - vitdatain_0_1_0 : in std_logic_vector(22 to 22); - dataout_1 : in std_logic_vector(31 downto 0); - dataout_0 : in std_logic_vector(35 downto 0); - dataout_2 : in std_logic_vector(31 downto 0); - un1_p0_2_0_0 : out std_logic; - un1_p0_2_0_350 : out std_logic; - data_1_21 : out std_logic; - data_1_16 : out std_logic; - data_1_5 : out std_logic; - data_1_0 : out std_logic; - data_1_2 : out std_logic; - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - size_0 : out std_logic_vector(0 to 0); - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - dci_m_6 : out std_logic; - dci_m_5 : out std_logic; - dci_m_3 : out std_logic; - dci_m_2 : out std_logic; - dci_m_1 : out std_logic; - dci_m_0 : out std_logic; - faddr_RNI7879K : out std_logic_vector(0 to 0); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - newtag_1_0 : out std_logic_vector(27 downto 24); - dataout : in std_logic_vector(35 downto 0); - address : out std_logic_vector(1 downto 0); - addr : out std_logic_vector(30 to 30); - iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - hgrant : in std_logic_vector(0 to 0); - hsize_5 : out std_logic_vector(1 to 1); - iosn_1 : in std_logic_vector(93 to 93); - hwdata_15 : out std_logic; - hwdata_0 : out std_logic; - hwdata_14 : out std_logic; - hwdata_1 : out std_logic; - hwdata_28 : out std_logic; - hwdata_23 : out std_logic; - hwdata_12 : out std_logic; - hwdata_4 : out std_logic; - hwdata_13 : out std_logic; - hwdata_27 : out std_logic; - hwdata_25 : out std_logic; - hwdata_11 : out std_logic; - hwdata_9 : out std_logic; - hwdata_3 : out std_logic; - hwdata_16 : out std_logic; - haddr : out std_logic_vector(31 downto 2); - htrans_tz : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - htrans : out std_logic_vector(1 to 1); - nbo_5_0 : out std_logic_vector(1 downto 0); - data_0 : out std_logic; - data_3 : out std_logic; - data_5 : out std_logic; - data_8 : out std_logic; - data_19 : out std_logic; - data_24 : out std_logic; - hrdata_1_0_1 : in std_logic_vector(1 to 1); - data1 : in std_logic_vector(31 downto 0); - maddress_28 : out std_logic; - data2 : in std_logic_vector(31 downto 0); - irl_0 : out std_logic_vector(3 downto 0); - irl : in std_logic_vector(3 downto 0); - edata2_iv_i_0_7 : out std_logic; - raddr1 : out std_logic_vector(7 downto 0); - rfa1 : out std_logic_vector(7 downto 0); - raddr2 : out std_logic_vector(7 downto 0); - rfa2 : out std_logic_vector(7 downto 0); - waddr : out std_logic_vector(7 downto 0); - wdata : out std_logic_vector(31 downto 0); - flush2_RNIFMGM2 : out std_logic; - flush2_RNI5I3N7 : out std_logic; - N_984 : out std_logic; - N_980 : out std_logic; - N_987 : out std_logic; - N_986 : out std_logic; - flush2 : out std_logic; - flush2_0_0_RNI146O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - N_981 : out std_logic; - N_985 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_264_0 : in std_logic; - N_262_0 : in std_logic; - N_78_0 : in std_logic; - un1_ici : out std_logic; - N_10 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - flush_RNIGBB873 : out std_logic; - N_270 : out std_logic; - N_269 : out std_logic; - N_267 : out std_logic; - N_259 : out std_logic; - N_258 : out std_logic; - N_144 : out std_logic; - N_3846 : out std_logic; - read_RNIQH64D1 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIRO4K31 : out std_logic; - read_RNI0IQ7R : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNICKHE91 : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - un59_nbo : out std_logic; - N_3239_i_0 : out std_logic; - N_26_0 : out std_logic; - read_RNIEKS231 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIC9O9B1 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNICAQK41 : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIEEGDD1 : out std_logic; - N_12_i_0 : out std_logic; - N_16_i_0 : out std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - N_24 : out std_logic; - N_329 : out std_logic; - N_330 : out std_logic; - N_3254_0 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - N_466 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_468 : out std_logic; - N_463 : out std_logic; - N_461 : out std_logic; - N_459 : out std_logic; - N_458 : out std_logic; - bo_5842_d : out std_logic; - N_139 : out std_logic; - N_138 : out std_logic; - un91_nbo_i_0 : out std_logic; - werr_2_m_0 : out std_logic; - N_467 : out std_logic; - N_462 : out std_logic; - N_457 : out std_logic; - un60_nbo : out std_logic; - hbusreq : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - N_5054 : out std_logic; - hlock : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - bo_5842_d_0 : out std_logic; - N_78 : in std_logic; - N_262 : in std_logic; - N_264 : in std_logic; - proc3_VCC : in std_logic; - N_546 : in std_logic; - lclk_c : in std_logic; - ra_bpmiss_1_0 : out std_logic; - rst : in std_logic; - d_m5_0_a3_2 : out std_logic; - rst_RNIINI1H : in std_logic; - rstate_1188n : in std_logic; - ren1 : out std_logic; - rfe1 : out std_logic; - wren : out std_logic; - intack : out std_logic; - ren2 : out std_logic; - rfe2 : out std_logic; - error_i_2 : out std_logic - ); - -end proc3; - -architecture DEF_ARCH of proc3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component iu3 - port( asi_0 : out std_logic_vector(4 downto 0); - wdata : out std_logic_vector(31 downto 0); - size_0_1 : out std_logic; - size_1_0 : out std_logic; - rdatav_0_1_1_iv_7 : in std_logic_vector(6 to 6) := (others => 'U'); - rdatav_0_1_0_iv_7 : in std_logic_vector(2 to 2) := (others => 'U'); - rdatav_0_1_0_iv_0_2 : in std_logic_vector(10 to 10) := (others => 'U'); - rdatav_0_1_0_iv_5_4 : in std_logic := 'U'; - rdatav_0_1_0_iv_5_1 : in std_logic := 'U'; - rdatav_0_1_0_iv_5_0 : in std_logic := 'U'; - rdatav_0_1_0_iv_5_6 : in std_logic := 'U'; - waddr : out std_logic_vector(7 downto 0); - rfa2 : out std_logic_vector(7 downto 0); - raddr2 : out std_logic_vector(7 downto 0); - rfa1 : out std_logic_vector(7 downto 0); - raddr1 : out std_logic_vector(7 downto 0); - data_0_2_13 : in std_logic := 'U'; - data_0_2_14 : in std_logic := 'U'; - data_0_2_17 : in std_logic := 'U'; - data_0_2_16 : in std_logic := 'U'; - data_0_2_8 : in std_logic := 'U'; - data_0_2_24 : in std_logic := 'U'; - data_0_2_31 : in std_logic := 'U'; - data_0_2_30 : in std_logic := 'U'; - data_0_2_29 : in std_logic := 'U'; - data_0_2_28 : in std_logic := 'U'; - data_0_2_27 : in std_logic := 'U'; - data_0_2_26 : in std_logic := 'U'; - data_0_2_25 : in std_logic := 'U'; - data_0_2_21 : in std_logic := 'U'; - data_0_2_4 : in std_logic := 'U'; - data_0_2_0 : in std_logic := 'U'; - edata2_iv_i_0 : out std_logic_vector(31 downto 24); - rpc_6 : out std_logic; - rpc_8 : out std_logic; - rpc_5 : out std_logic; - rpc_7 : out std_logic; - rpc_2 : out std_logic; - rpc_0 : out std_logic; - rpc_1 : out std_logic; - rpc_3 : out std_logic; - irl_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - irl : out std_logic_vector(3 downto 0); - data2 : in std_logic_vector(31 downto 0) := (others => 'U'); - mcdo_m_0_27 : in std_logic := 'U'; - mcdo_m_0_29 : in std_logic := 'U'; - mcdo_m_0_4 : in std_logic := 'U'; - mcdo_m_0_20 : in std_logic := 'U'; - mcdo_m_0_17 : in std_logic := 'U'; - mcdo_m_0_0 : in std_logic := 'U'; - mcdo_m_0_16 : in std_logic := 'U'; - mcdo_m_0_7 : in std_logic := 'U'; - mcdo_m_0_22 : in std_logic := 'U'; - mcdo_m_0_21 : in std_logic := 'U'; - rdatav_0_1_0_iv_4_20 : in std_logic := 'U'; - rdatav_0_1_0_iv_4_22 : in std_logic := 'U'; - rdatav_0_1_0_iv_4_0 : in std_logic := 'U'; - rdatav_0_1_0_iv_4_14 : in std_logic := 'U'; - maddress : out std_logic_vector(31 downto 0); - data1 : in std_logic_vector(31 downto 0) := (others => 'U'); - un1_p0_6_0 : out std_logic; - edata2_0_iv : out std_logic_vector(23 downto 0); - fpc : out std_logic_vector(31 downto 2); - data_0_0_15 : in std_logic := 'U'; - data_0_0_20 : in std_logic := 'U'; - data_0_0_11 : in std_logic := 'U'; - data_0_0_6 : in std_logic := 'U'; - data_0_0_23 : in std_logic := 'U'; - data_0_0_19 : in std_logic := 'U'; - data_0_0_17 : in std_logic := 'U'; - data_0_0_16 : in std_logic := 'U'; - data_0_0_14 : in std_logic := 'U'; - data_0_0_13 : in std_logic := 'U'; - data_0_0_12 : in std_logic := 'U'; - data_0_0_10 : in std_logic := 'U'; - data_0_0_9 : in std_logic := 'U'; - data_0_0_7 : in std_logic := 'U'; - data_0_0_5 : in std_logic := 'U'; - data_0_0_3 : in std_logic := 'U'; - data_0_0_2 : in std_logic := 'U'; - data_0_0_1 : in std_logic := 'U'; - data_0_0_0 : in std_logic := 'U'; - data_0_0_4 : in std_logic := 'U'; - data_0_0_26 : in std_logic := 'U'; - data_0_0_8 : in std_logic := 'U'; - data_0_0_28 : in std_logic := 'U'; - data_0_0_27 : in std_logic := 'U'; - data_0_0_30 : in std_logic := 'U'; - data_0_0_25 : in std_logic := 'U'; - data_0_0_24 : in std_logic := 'U'; - data_0_0_21 : in std_logic := 'U'; - eaddress_4 : out std_logic; - eaddress_2 : out std_logic; - eaddress_12 : out std_logic; - eaddress_24 : out std_logic; - eaddress_5 : out std_logic; - eaddress_11 : out std_logic; - eaddress_30 : out std_logic; - eaddress_6 : out std_logic; - eaddress_3 : out std_logic; - eaddress_27 : out std_logic; - eaddress_31 : out std_logic; - eaddress_15 : out std_logic; - eaddress_17 : out std_logic; - eaddress_20 : out std_logic; - eaddress_18 : out std_logic; - eaddress_26 : out std_logic; - eaddress_14 : out std_logic; - eaddress_21 : out std_logic; - eaddress_25 : out std_logic; - eaddress_29 : out std_logic; - eaddress_19 : out std_logic; - eaddress_23 : out std_logic; - eaddress_22 : out std_logic; - eaddress_9 : out std_logic; - eaddress_10 : out std_logic; - eaddress_7 : out std_logic; - eaddress_8 : out std_logic; - data_0_22 : in std_logic := 'U'; - data_0_20 : in std_logic := 'U'; - data_0_18 : in std_logic := 'U'; - data_0_15 : in std_logic := 'U'; - data_0_11 : in std_logic := 'U'; - data_0_7 : in std_logic := 'U'; - data_0_12 : in std_logic := 'U'; - data_0_31 : in std_logic := 'U'; - data_0_29 : in std_logic := 'U'; - dco_i_2 : in std_logic_vector(132 to 132) := (others => 'U'); - maddress_0_2 : out std_logic; - maddress_0_0 : out std_logic; - msu : out std_logic; - error_i_2 : out std_logic; - read_1 : out std_logic; - write_0 : out std_logic; - mexc_2 : in std_logic := 'U'; - enaddr : out std_logic; - eenaddr : out std_logic; - N_26 : out std_logic; - lock : out std_logic; - N_28 : out std_logic; - su_0 : out std_logic; - rfe2 : out std_logic; - ren2 : out std_logic; - mexc : in std_logic := 'U'; - N_3305_0 : in std_logic := 'U'; - intack_2 : out std_logic; - wren : out std_logic; - rfe1 : out std_logic; - ren1 : out std_logic; - werr_2 : in std_logic := 'U'; - rstate_1188n : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : in std_logic := 'U'; - ldlock_3_0 : out std_logic; - rst_RNIINI1H : in std_logic := 'U'; - rbranch : out std_logic; - r_N_6 : out std_logic; - un1_addout_12 : out std_logic; - flush_i_0 : out std_logic; - N_3389_i_0 : in std_logic := 'U'; - N_3227_i_0 : in std_logic := 'U'; - N_3387_i_0 : in std_logic := 'U'; - nullify : out std_logic; - ldlock_2 : out std_logic; - fbranch : out std_logic; - d_m5_0_a3_2 : out std_logic; - hold_pc_7 : out std_logic; - nullify2_0_sqmuxa : out std_logic; - me_nullify2_1_2 : out std_logic; - un9_icc_check_bp : out std_logic; - inull : out std_logic; - de_hold_pc_1 : out std_logic; - rst : in std_logic := 'U'; - un17_casaen_0_0 : out std_logic; - xc_exception_1_0 : out std_logic; - mds : in std_logic := 'U'; - ra_bpmiss_1_0 : out std_logic; - read_0 : out std_logic; - holdn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component mmu_cache - port( hrdata_1_0_1 : in std_logic_vector(1 to 1) := (others => 'U'); - data_2_17 : out std_logic; - data_2_12 : out std_logic; - data_2_1 : out std_logic; - data_1_10 : out std_logic; - data_1_8 : out std_logic; - nbo_5_0 : out std_logic_vector(1 downto 0); - htrans : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans_tz : out std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 2); - hwdata_16 : out std_logic; - hwdata_3 : out std_logic; - hwdata_9 : out std_logic; - hwdata_11 : out std_logic; - hwdata_25 : out std_logic; - hwdata_27 : out std_logic; - hwdata_13 : out std_logic; - hwdata_4 : out std_logic; - hwdata_12 : out std_logic; - hwdata_23 : out std_logic; - hwdata_28 : out std_logic; - hwdata_1 : out std_logic; - hwdata_14 : out std_logic; - hwdata_0 : out std_logic; - hwdata_15 : out std_logic; - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hsize_5 : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(0 to 0) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - addr_28 : out std_logic; - address_1 : out std_logic; - address_0 : out std_logic; - dataout : in std_logic_vector(35 downto 0) := (others => 'U'); - data_0_0_31 : out std_logic; - data_0_0_24 : out std_logic; - data_0_0_29 : out std_logic; - data_0_0_13 : out std_logic; - data_0_0_30 : out std_logic; - data_0_0_27 : out std_logic; - data_0_0_20 : out std_logic; - data_0_0_14 : out std_logic; - data_0_0_25 : out std_logic; - data_0_0_16 : out std_logic; - data_0_0_17 : out std_logic; - data_0_0_28 : out std_logic; - data_0_0_8 : out std_logic; - data_0_0_11 : out std_logic; - data_0_0_21 : out std_logic; - data_0_0_4 : out std_logic; - data_0_0_26 : out std_logic; - data_0_0_0 : out std_logic; - data_0_0_12 : out std_logic; - data_0_0_15 : out std_logic; - data_0_0_7 : out std_logic; - mcdo_m_0_29 : out std_logic; - mcdo_m_0_22 : out std_logic; - mcdo_m_0_27 : out std_logic; - mcdo_m_0_0 : out std_logic; - mcdo_m_0_16 : out std_logic; - mcdo_m_0_21 : out std_logic; - mcdo_m_0_20 : out std_logic; - mcdo_m_0_17 : out std_logic; - mcdo_m_0_4 : out std_logic; - mcdo_m_0_7 : out std_logic; - rdatav_0_1_0_iv_4_22 : out std_logic; - rdatav_0_1_0_iv_4_20 : out std_logic; - rdatav_0_1_0_iv_4_0 : out std_logic; - rdatav_0_1_0_iv_4_14 : out std_logic; - rdatav_0_1_0_iv_5_6 : out std_logic; - rdatav_0_1_0_iv_5_1 : out std_logic; - rdatav_0_1_0_iv_5_0 : out std_logic; - rdatav_0_1_0_iv_5_4 : out std_logic; - eaddress_29 : in std_logic := 'U'; - eaddress_22 : in std_logic := 'U'; - eaddress_21 : in std_logic := 'U'; - eaddress_13 : in std_logic := 'U'; - eaddress_28 : in std_logic := 'U'; - eaddress_18 : in std_logic := 'U'; - eaddress_6 : in std_logic := 'U'; - eaddress_10 : in std_logic := 'U'; - eaddress_25 : in std_logic := 'U'; - eaddress_23 : in std_logic := 'U'; - eaddress_19 : in std_logic := 'U'; - eaddress_9 : in std_logic := 'U'; - eaddress_17 : in std_logic := 'U'; - eaddress_27 : in std_logic := 'U'; - eaddress_15 : in std_logic := 'U'; - eaddress_5 : in std_logic := 'U'; - eaddress_20 : in std_logic := 'U'; - eaddress_2 : in std_logic := 'U'; - eaddress_24 : in std_logic := 'U'; - eaddress_16 : in std_logic := 'U'; - eaddress_12 : in std_logic := 'U'; - eaddress_4 : in std_logic := 'U'; - eaddress_1 : in std_logic := 'U'; - eaddress_8 : in std_logic := 'U'; - eaddress_0 : in std_logic := 'U'; - eaddress_3 : in std_logic := 'U'; - eaddress_7 : in std_logic := 'U'; - asi_4 : in std_logic := 'U'; - asi_3 : in std_logic := 'U'; - asi_2 : in std_logic := 'U'; - asi_1 : in std_logic := 'U'; - asi_0 : in std_logic_vector(0 to 0) := (others => 'U'); - rdatav_0_1_0_iv_7 : out std_logic_vector(2 to 2); - rdatav_0_1_0_iv_0_2 : out std_logic_vector(10 to 10); - rdatav_0_1_1_iv_7 : out std_logic_vector(6 to 6); - edata2_0_iv : in std_logic_vector(23 downto 0) := (others => 'U'); - newtag_1_0 : out std_logic_vector(27 downto 24); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dco_i_2 : out std_logic_vector(132 to 132); - size_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - edata2_iv_i_0 : in std_logic_vector(31 downto 24) := (others => 'U'); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - faddr_RNI7879K : out std_logic_vector(0 to 0); - dci_m_0 : out std_logic; - dci_m_1 : out std_logic; - dci_m_2 : out std_logic; - dci_m_3 : out std_logic; - dci_m_5 : out std_logic; - dci_m_6 : out std_logic; - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - size_0_d0 : out std_logic; - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - data_10 : out std_logic; - data_8 : out std_logic; - data_5 : out std_logic; - data_13 : out std_logic; - data_24 : out std_logic; - data_29 : out std_logic; - un1_p0_2_0_350 : out std_logic; - un1_p0_2_0_0 : out std_logic; - fpc : in std_logic_vector(31 downto 2) := (others => 'U'); - dataout_2 : in std_logic_vector(31 downto 0) := (others => 'U'); - maddress : in std_logic_vector(31 downto 0) := (others => 'U'); - un1_p0_6 : in std_logic_vector(0 to 0) := (others => 'U'); - dataout_0 : in std_logic_vector(35 downto 0) := (others => 'U'); - dataout_1 : in std_logic_vector(31 downto 0) := (others => 'U'); - vitdatain_0_1_0 : in std_logic_vector(22 to 22) := (others => 'U'); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - istate_RNIA8N5H : out std_logic_vector(0 to 0); - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - data_0 : out std_logic_vector(31 downto 0); - rpc_0 : in std_logic := 'U'; - rpc_1 : in std_logic := 'U'; - rpc_3 : in std_logic := 'U'; - rpc_2 : in std_logic := 'U'; - rpc_7 : in std_logic := 'U'; - rpc_8 : in std_logic := 'U'; - rpc_5 : in std_logic := 'U'; - rpc_6 : in std_logic := 'U'; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - hrdata_9 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - istate_RNIPSU8G : out std_logic_vector(0 to 0); - maddress_0_0 : in std_logic := 'U'; - maddress_0_2 : in std_logic := 'U'; - istate_RNIEC82C : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNI5V68H : out std_logic_vector(0 to 0); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - istate_RNIH0NBI : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - istate_RNI57KLB : out std_logic_vector(0 to 0); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - istate_RNI6HPAI : out std_logic_vector(0 to 0); - ctx : out std_logic_vector(7 downto 0); - un1_p0_2_i_0 : out std_logic; - un1_p0_2_i_4 : out std_logic; - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - istate_RNIJCMP6 : out std_logic_vector(0 to 0); - N_546 : in std_logic := 'U'; - mmu_cache_VCC : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - bo_5842_d_0 : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - hlock : out std_logic; - N_5054 : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - hbusreq : out std_logic; - un60_nbo : out std_logic; - N_457 : out std_logic; - N_462 : out std_logic; - N_467 : out std_logic; - werr_2_m_0 : out std_logic; - un91_nbo_i_0 : out std_logic; - N_138 : out std_logic; - N_139 : out std_logic; - bo_5842_d : out std_logic; - N_458 : out std_logic; - N_459 : out std_logic; - N_461 : out std_logic; - N_463 : out std_logic; - N_468 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_466 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - werr : out std_logic; - N_3254_0 : out std_logic; - enaddr : in std_logic := 'U'; - lock_0 : in std_logic := 'U'; - vaddr_1_sqmuxa_0_a2_4_m1_e_24 : out std_logic; - un1_addout_12 : in std_logic := 'U'; - read_0_0 : in std_logic := 'U'; - nullify : in std_logic := 'U'; - intack : in std_logic := 'U'; - nullify2_0_sqmuxa : in std_logic := 'U'; - me_nullify2_1_2 : in std_logic := 'U'; - un17_casaen_0_0 : in std_logic := 'U'; - N_330 : out std_logic; - N_329 : out std_logic; - N_24 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - N_16_i_0 : out std_logic; - N_12_i_0 : out std_logic; - read_RNIEEGDD1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNICAQK41 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNIC9O9B1 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIEKS231 : out std_logic; - N_26_0 : out std_logic; - N_3387_i_0 : out std_logic; - N_3227_i_0 : out std_logic; - N_3239_i_0 : out std_logic; - mexc_1 : out std_logic; - un59_nbo : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - read_RNICKHE91 : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI0IQ7R : out std_logic; - N_3389_i_0 : out std_logic; - read_RNIRO4K31 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIQH64D1 : out std_logic; - read_1 : in std_logic := 'U'; - r_N_6 : in std_logic := 'U'; - N_3305 : out std_logic; - N_3846 : out std_logic; - N_144 : out std_logic; - N_258 : out std_logic; - N_259 : out std_logic; - N_267 : out std_logic; - N_269 : out std_logic; - N_270 : out std_logic; - flush_RNIGBB873 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - msu : in std_logic := 'U'; - eenaddr : in std_logic := 'U'; - write : in std_logic := 'U'; - N_10 : out std_logic; - lclk_c : in std_logic := 'U'; - holdn : out std_logic; - rst : in std_logic := 'U'; - flush_i_0 : in std_logic := 'U'; - hold_pc_7 : in std_logic := 'U'; - de_hold_pc_1 : in std_logic := 'U'; - un1_ici : out std_logic; - xc_exception_1_0 : in std_logic := 'U'; - ldlock_2 : in std_logic := 'U'; - un9_icc_check_bp : in std_logic := 'U'; - ldlock_3_0 : in std_logic := 'U'; - inull : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - N_982 : out std_logic; - N_983 : out std_logic; - N_985 : out std_logic; - N_981 : out std_logic; - mds : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNI146O2 : out std_logic; - N_26 : in std_logic := 'U'; - flush2 : out std_logic; - N_986 : out std_logic; - N_987 : out std_logic; - N_28 : in std_logic := 'U'; - N_980 : out std_logic; - N_984 : out std_logic; - flush2_RNI5I3N7 : out std_logic; - flush2_RNIFMGM2 : out std_logic; - rbranch : in std_logic := 'U'; - fbranch : in std_logic := 'U'; - mexc : out std_logic; - su : in std_logic := 'U' - ); - end component; - - signal \asi[0]\, \asi[1]\, \asi[2]\, \asi[3]\, \asi[4]\, - \size[1]\, \size[0]\, \rdatav_0_1_1_iv_7[6]\, - \rdatav_0_1_0_iv_7[2]\, \rdatav_0_1_0_iv_0_2[10]\, - \rdatav_0_1_0_iv_5[22]\, \rdatav_0_1_0_iv_5[19]\, - \rdatav_0_1_0_iv_5[18]\, \rdatav_0_1_0_iv_5[24]\, - \data_0[13]\, \data_0[14]\, \data_0[17]\, \data_0[16]\, - \data_0[8]\, \data_0[24]\, \data_0[31]\, \data_0[30]\, - \data_0[29]\, \data_0[28]\, \data_0[27]\, \data_0[26]\, - \data_0[25]\, \data_0[21]\, \data_0[4]\, \data_0[0]\, - \edata2_iv_i_0[24]\, \edata2_iv_i_0[25]\, - \edata2_iv_i_0[26]\, \edata2_iv_i_0[27]\, - \edata2_iv_i_0[28]\, \edata2_iv_i_0[29]\, - \edata2_iv_i_0[30]\, \rpc[8]\, \rpc[10]\, \rpc[7]\, - \rpc[9]\, \rpc[4]\, \rpc[2]\, \rpc[3]\, \rpc[5]\, - \mcdo_m_0[29]\, \mcdo_m_0[31]\, \mcdo_m_0[6]\, - \mcdo_m_0[22]\, \mcdo_m_0[19]\, \mcdo_m_0[2]\, - \mcdo_m_0[18]\, \mcdo_m_0[9]\, \mcdo_m_0[24]\, - \mcdo_m_0[23]\, \rdatav_0_1_0_iv_4[29]\, - \rdatav_0_1_0_iv_4[31]\, \rdatav_0_1_0_iv_4[9]\, - \rdatav_0_1_0_iv_4[23]\, \maddress[0]\, \maddress[1]\, - \maddress[2]\, \maddress[3]\, \maddress[4]\, - \maddress[5]\, \maddress[6]\, \maddress[7]\, - \maddress[8]\, \maddress[9]\, \maddress[10]\, - \maddress[11]\, \maddress[12]\, \maddress[13]\, - \maddress[14]\, \maddress[15]\, \maddress[16]\, - \maddress[17]\, \maddress[18]\, \maddress[19]\, - \maddress[20]\, \maddress[21]\, \maddress[22]\, - \maddress[23]\, \maddress[24]\, \maddress[25]\, - \maddress[26]\, \maddress[27]\, \maddress[29]\, - \maddress[30]\, \maddress[31]\, \un1_p0_6[0]\, - \edata2_0_iv[0]\, \edata2_0_iv[1]\, \edata2_0_iv[2]\, - \edata2_0_iv[3]\, \edata2_0_iv[4]\, \edata2_0_iv[5]\, - \edata2_0_iv[6]\, \edata2_0_iv[7]\, \edata2_0_iv[8]\, - \edata2_0_iv[9]\, \edata2_0_iv[10]\, \edata2_0_iv[11]\, - \edata2_0_iv[12]\, \edata2_0_iv[13]\, \edata2_0_iv[14]\, - \edata2_0_iv[15]\, \edata2_0_iv[16]\, \edata2_0_iv[17]\, - \edata2_0_iv[18]\, \edata2_0_iv[19]\, \edata2_0_iv[20]\, - \edata2_0_iv[21]\, \edata2_0_iv[22]\, \edata2_0_iv[23]\, - \fpc[2]\, \fpc[3]\, \fpc[4]\, \fpc[5]\, \fpc[6]\, - \fpc[7]\, \fpc[8]\, \fpc[9]\, \fpc[10]\, \fpc[11]\, - \fpc[12]\, \fpc[13]\, \fpc[14]\, \fpc[15]\, \fpc[16]\, - \fpc[17]\, \fpc[18]\, \fpc[19]\, \fpc[20]\, \fpc[21]\, - \fpc[22]\, \fpc[23]\, \fpc[24]\, \fpc[25]\, \fpc[26]\, - \fpc[27]\, \fpc[28]\, \fpc[29]\, \fpc[30]\, \fpc[31]\, - \data_0[15]\, \data_0[20]\, \data_0[11]\, \data_0[6]\, - \data_0[23]\, \data_0[19]\, \data_0_0[17]\, - \data_0_0[16]\, \data_0_0[14]\, \data_0_0[13]\, - \data_0[12]\, \data_0[10]\, \data_0[9]\, \data_0[7]\, - \data_0[5]\, \data_0[3]\, \data_0[2]\, \data_0[1]\, - \data_0_0[0]\, \data_0_0[4]\, \data_0_0[26]\, - \data_0_0[8]\, \data_0_0[28]\, \data_0_0[27]\, - \data_0_0[30]\, \data_0_0[25]\, \data_0_0[24]\, - \data_0_0[21]\, \eaddress[4]\, \eaddress[2]\, - \eaddress[12]\, \eaddress[24]\, \eaddress[5]\, - \eaddress[11]\, \eaddress[30]\, \eaddress[6]\, - \eaddress[3]\, \eaddress[27]\, \eaddress[31]\, - \eaddress[15]\, \eaddress[17]\, \eaddress[20]\, - \eaddress[18]\, \eaddress[26]\, \eaddress[14]\, - \eaddress[21]\, \eaddress[25]\, \eaddress[29]\, - \eaddress[19]\, \eaddress[23]\, \eaddress[22]\, - \eaddress[9]\, \eaddress[10]\, \eaddress[7]\, - \eaddress[8]\, \data_0[22]\, \data_0_0[20]\, \data_0[18]\, - \data_0_0[15]\, \data_0_0[11]\, \data_0_0[7]\, - \data_0_0[12]\, \data_0_0[31]\, \data_0_0[29]\, - \dco_i_2[132]\, \maddress_0[3]\, \maddress_0[1]\, msu, - read, write, mexc, enaddr, eenaddr, N_26, lock, N_28, su, - mexc_0, N_3305, werr, vaddr_1_sqmuxa_0_a2_4_m1_e_24, - ldlock_3_0, rbranch, r_N_6, un1_addout_12, flush_i_0, - N_3389_i_0, N_3227_i_0, N_3387_i_0, nullify, ldlock_2, - fbranch, hold_pc_7, nullify2_0_sqmuxa, me_nullify2_1_2, - un9_icc_check_bp, inull, de_hold_pc_1, un17_casaen_0_0, - xc_exception_1_0, mds, read_0, holdn, \edata2_iv_i_0[31]\, - \maddress[28]\, \intack\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : iu3 - Use entity work.iu3(DEF_ARCH); - for all : mmu_cache - Use entity work.mmu_cache(DEF_ARCH); -begin - - maddress_28 <= \maddress[28]\; - edata2_iv_i_0_7 <= \edata2_iv_i_0[31]\; - intack <= \intack\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - iu0 : iu3 - port map(asi_0(4) => \asi[4]\, asi_0(3) => \asi[3]\, - asi_0(2) => \asi[2]\, asi_0(1) => \asi[1]\, asi_0(0) => - \asi[0]\, wdata(31) => wdata(31), wdata(30) => wdata(30), - wdata(29) => wdata(29), wdata(28) => wdata(28), wdata(27) - => wdata(27), wdata(26) => wdata(26), wdata(25) => - wdata(25), wdata(24) => wdata(24), wdata(23) => wdata(23), - wdata(22) => wdata(22), wdata(21) => wdata(21), wdata(20) - => wdata(20), wdata(19) => wdata(19), wdata(18) => - wdata(18), wdata(17) => wdata(17), wdata(16) => wdata(16), - wdata(15) => wdata(15), wdata(14) => wdata(14), wdata(13) - => wdata(13), wdata(12) => wdata(12), wdata(11) => - wdata(11), wdata(10) => wdata(10), wdata(9) => wdata(9), - wdata(8) => wdata(8), wdata(7) => wdata(7), wdata(6) => - wdata(6), wdata(5) => wdata(5), wdata(4) => wdata(4), - wdata(3) => wdata(3), wdata(2) => wdata(2), wdata(1) => - wdata(1), wdata(0) => wdata(0), size_0_1 => \size[1]\, - size_1_0 => \size[0]\, rdatav_0_1_1_iv_7(6) => - \rdatav_0_1_1_iv_7[6]\, rdatav_0_1_0_iv_7(2) => - \rdatav_0_1_0_iv_7[2]\, rdatav_0_1_0_iv_0_2(10) => - \rdatav_0_1_0_iv_0_2[10]\, rdatav_0_1_0_iv_5_4 => - \rdatav_0_1_0_iv_5[22]\, rdatav_0_1_0_iv_5_1 => - \rdatav_0_1_0_iv_5[19]\, rdatav_0_1_0_iv_5_0 => - \rdatav_0_1_0_iv_5[18]\, rdatav_0_1_0_iv_5_6 => - \rdatav_0_1_0_iv_5[24]\, waddr(7) => waddr(7), waddr(6) - => waddr(6), waddr(5) => waddr(5), waddr(4) => waddr(4), - waddr(3) => waddr(3), waddr(2) => waddr(2), waddr(1) => - waddr(1), waddr(0) => waddr(0), rfa2(7) => rfa2(7), - rfa2(6) => rfa2(6), rfa2(5) => rfa2(5), rfa2(4) => - rfa2(4), rfa2(3) => rfa2(3), rfa2(2) => rfa2(2), rfa2(1) - => rfa2(1), rfa2(0) => rfa2(0), raddr2(7) => raddr2(7), - raddr2(6) => raddr2(6), raddr2(5) => raddr2(5), raddr2(4) - => raddr2(4), raddr2(3) => raddr2(3), raddr2(2) => - raddr2(2), raddr2(1) => raddr2(1), raddr2(0) => raddr2(0), - rfa1(7) => rfa1(7), rfa1(6) => rfa1(6), rfa1(5) => - rfa1(5), rfa1(4) => rfa1(4), rfa1(3) => rfa1(3), rfa1(2) - => rfa1(2), rfa1(1) => rfa1(1), rfa1(0) => rfa1(0), - raddr1(7) => raddr1(7), raddr1(6) => raddr1(6), raddr1(5) - => raddr1(5), raddr1(4) => raddr1(4), raddr1(3) => - raddr1(3), raddr1(2) => raddr1(2), raddr1(1) => raddr1(1), - raddr1(0) => raddr1(0), data_0_2_13 => \data_0[13]\, - data_0_2_14 => \data_0[14]\, data_0_2_17 => \data_0[17]\, - data_0_2_16 => \data_0[16]\, data_0_2_8 => \data_0[8]\, - data_0_2_24 => \data_0[24]\, data_0_2_31 => \data_0[31]\, - data_0_2_30 => \data_0[30]\, data_0_2_29 => \data_0[29]\, - data_0_2_28 => \data_0[28]\, data_0_2_27 => \data_0[27]\, - data_0_2_26 => \data_0[26]\, data_0_2_25 => \data_0[25]\, - data_0_2_21 => \data_0[21]\, data_0_2_4 => \data_0[4]\, - data_0_2_0 => \data_0[0]\, edata2_iv_i_0(31) => - \edata2_iv_i_0[31]\, edata2_iv_i_0(30) => - \edata2_iv_i_0[30]\, edata2_iv_i_0(29) => - \edata2_iv_i_0[29]\, edata2_iv_i_0(28) => - \edata2_iv_i_0[28]\, edata2_iv_i_0(27) => - \edata2_iv_i_0[27]\, edata2_iv_i_0(26) => - \edata2_iv_i_0[26]\, edata2_iv_i_0(25) => - \edata2_iv_i_0[25]\, edata2_iv_i_0(24) => - \edata2_iv_i_0[24]\, rpc_6 => \rpc[8]\, rpc_8 => - \rpc[10]\, rpc_5 => \rpc[7]\, rpc_7 => \rpc[9]\, rpc_2 - => \rpc[4]\, rpc_0 => \rpc[2]\, rpc_1 => \rpc[3]\, rpc_3 - => \rpc[5]\, irl_0(3) => irl(3), irl_0(2) => irl(2), - irl_0(1) => irl(1), irl_0(0) => irl(0), irl(3) => - irl_0(3), irl(2) => irl_0(2), irl(1) => irl_0(1), irl(0) - => irl_0(0), data2(31) => data2(31), data2(30) => - data2(30), data2(29) => data2(29), data2(28) => data2(28), - data2(27) => data2(27), data2(26) => data2(26), data2(25) - => data2(25), data2(24) => data2(24), data2(23) => - data2(23), data2(22) => data2(22), data2(21) => data2(21), - data2(20) => data2(20), data2(19) => data2(19), data2(18) - => data2(18), data2(17) => data2(17), data2(16) => - data2(16), data2(15) => data2(15), data2(14) => data2(14), - data2(13) => data2(13), data2(12) => data2(12), data2(11) - => data2(11), data2(10) => data2(10), data2(9) => - data2(9), data2(8) => data2(8), data2(7) => data2(7), - data2(6) => data2(6), data2(5) => data2(5), data2(4) => - data2(4), data2(3) => data2(3), data2(2) => data2(2), - data2(1) => data2(1), data2(0) => data2(0), mcdo_m_0_27 - => \mcdo_m_0[29]\, mcdo_m_0_29 => \mcdo_m_0[31]\, - mcdo_m_0_4 => \mcdo_m_0[6]\, mcdo_m_0_20 => - \mcdo_m_0[22]\, mcdo_m_0_17 => \mcdo_m_0[19]\, mcdo_m_0_0 - => \mcdo_m_0[2]\, mcdo_m_0_16 => \mcdo_m_0[18]\, - mcdo_m_0_7 => \mcdo_m_0[9]\, mcdo_m_0_22 => - \mcdo_m_0[24]\, mcdo_m_0_21 => \mcdo_m_0[23]\, - rdatav_0_1_0_iv_4_20 => \rdatav_0_1_0_iv_4[29]\, - rdatav_0_1_0_iv_4_22 => \rdatav_0_1_0_iv_4[31]\, - rdatav_0_1_0_iv_4_0 => \rdatav_0_1_0_iv_4[9]\, - rdatav_0_1_0_iv_4_14 => \rdatav_0_1_0_iv_4[23]\, - maddress(31) => \maddress[31]\, maddress(30) => - \maddress[30]\, maddress(29) => \maddress[29]\, - maddress(28) => \maddress[28]\, maddress(27) => - \maddress[27]\, maddress(26) => \maddress[26]\, - maddress(25) => \maddress[25]\, maddress(24) => - \maddress[24]\, maddress(23) => \maddress[23]\, - maddress(22) => \maddress[22]\, maddress(21) => - \maddress[21]\, maddress(20) => \maddress[20]\, - maddress(19) => \maddress[19]\, maddress(18) => - \maddress[18]\, maddress(17) => \maddress[17]\, - maddress(16) => \maddress[16]\, maddress(15) => - \maddress[15]\, maddress(14) => \maddress[14]\, - maddress(13) => \maddress[13]\, maddress(12) => - \maddress[12]\, maddress(11) => \maddress[11]\, - maddress(10) => \maddress[10]\, maddress(9) => - \maddress[9]\, maddress(8) => \maddress[8]\, maddress(7) - => \maddress[7]\, maddress(6) => \maddress[6]\, - maddress(5) => \maddress[5]\, maddress(4) => - \maddress[4]\, maddress(3) => \maddress[3]\, maddress(2) - => \maddress[2]\, maddress(1) => \maddress[1]\, - maddress(0) => \maddress[0]\, data1(31) => data1(31), - data1(30) => data1(30), data1(29) => data1(29), data1(28) - => data1(28), data1(27) => data1(27), data1(26) => - data1(26), data1(25) => data1(25), data1(24) => data1(24), - data1(23) => data1(23), data1(22) => data1(22), data1(21) - => data1(21), data1(20) => data1(20), data1(19) => - data1(19), data1(18) => data1(18), data1(17) => data1(17), - data1(16) => data1(16), data1(15) => data1(15), data1(14) - => data1(14), data1(13) => data1(13), data1(12) => - data1(12), data1(11) => data1(11), data1(10) => data1(10), - data1(9) => data1(9), data1(8) => data1(8), data1(7) => - data1(7), data1(6) => data1(6), data1(5) => data1(5), - data1(4) => data1(4), data1(3) => data1(3), data1(2) => - data1(2), data1(1) => data1(1), data1(0) => data1(0), - un1_p0_6_0 => \un1_p0_6[0]\, edata2_0_iv(23) => - \edata2_0_iv[23]\, edata2_0_iv(22) => \edata2_0_iv[22]\, - edata2_0_iv(21) => \edata2_0_iv[21]\, edata2_0_iv(20) => - \edata2_0_iv[20]\, edata2_0_iv(19) => \edata2_0_iv[19]\, - edata2_0_iv(18) => \edata2_0_iv[18]\, edata2_0_iv(17) => - \edata2_0_iv[17]\, edata2_0_iv(16) => \edata2_0_iv[16]\, - edata2_0_iv(15) => \edata2_0_iv[15]\, edata2_0_iv(14) => - \edata2_0_iv[14]\, edata2_0_iv(13) => \edata2_0_iv[13]\, - edata2_0_iv(12) => \edata2_0_iv[12]\, edata2_0_iv(11) => - \edata2_0_iv[11]\, edata2_0_iv(10) => \edata2_0_iv[10]\, - edata2_0_iv(9) => \edata2_0_iv[9]\, edata2_0_iv(8) => - \edata2_0_iv[8]\, edata2_0_iv(7) => \edata2_0_iv[7]\, - edata2_0_iv(6) => \edata2_0_iv[6]\, edata2_0_iv(5) => - \edata2_0_iv[5]\, edata2_0_iv(4) => \edata2_0_iv[4]\, - edata2_0_iv(3) => \edata2_0_iv[3]\, edata2_0_iv(2) => - \edata2_0_iv[2]\, edata2_0_iv(1) => \edata2_0_iv[1]\, - edata2_0_iv(0) => \edata2_0_iv[0]\, fpc(31) => \fpc[31]\, - fpc(30) => \fpc[30]\, fpc(29) => \fpc[29]\, fpc(28) => - \fpc[28]\, fpc(27) => \fpc[27]\, fpc(26) => \fpc[26]\, - fpc(25) => \fpc[25]\, fpc(24) => \fpc[24]\, fpc(23) => - \fpc[23]\, fpc(22) => \fpc[22]\, fpc(21) => \fpc[21]\, - fpc(20) => \fpc[20]\, fpc(19) => \fpc[19]\, fpc(18) => - \fpc[18]\, fpc(17) => \fpc[17]\, fpc(16) => \fpc[16]\, - fpc(15) => \fpc[15]\, fpc(14) => \fpc[14]\, fpc(13) => - \fpc[13]\, fpc(12) => \fpc[12]\, fpc(11) => \fpc[11]\, - fpc(10) => \fpc[10]\, fpc(9) => \fpc[9]\, fpc(8) => - \fpc[8]\, fpc(7) => \fpc[7]\, fpc(6) => \fpc[6]\, fpc(5) - => \fpc[5]\, fpc(4) => \fpc[4]\, fpc(3) => \fpc[3]\, - fpc(2) => \fpc[2]\, data_0_0_15 => \data_0[15]\, - data_0_0_20 => \data_0[20]\, data_0_0_11 => \data_0[11]\, - data_0_0_6 => \data_0[6]\, data_0_0_23 => \data_0[23]\, - data_0_0_19 => \data_0[19]\, data_0_0_17 => - \data_0_0[17]\, data_0_0_16 => \data_0_0[16]\, - data_0_0_14 => \data_0_0[14]\, data_0_0_13 => - \data_0_0[13]\, data_0_0_12 => \data_0[12]\, data_0_0_10 - => \data_0[10]\, data_0_0_9 => \data_0[9]\, data_0_0_7 - => \data_0[7]\, data_0_0_5 => \data_0[5]\, data_0_0_3 - => \data_0[3]\, data_0_0_2 => \data_0[2]\, data_0_0_1 - => \data_0[1]\, data_0_0_0 => \data_0_0[0]\, data_0_0_4 - => \data_0_0[4]\, data_0_0_26 => \data_0_0[26]\, - data_0_0_8 => \data_0_0[8]\, data_0_0_28 => - \data_0_0[28]\, data_0_0_27 => \data_0_0[27]\, - data_0_0_30 => \data_0_0[30]\, data_0_0_25 => - \data_0_0[25]\, data_0_0_24 => \data_0_0[24]\, - data_0_0_21 => \data_0_0[21]\, eaddress_4 => - \eaddress[4]\, eaddress_2 => \eaddress[2]\, eaddress_12 - => \eaddress[12]\, eaddress_24 => \eaddress[24]\, - eaddress_5 => \eaddress[5]\, eaddress_11 => - \eaddress[11]\, eaddress_30 => \eaddress[30]\, eaddress_6 - => \eaddress[6]\, eaddress_3 => \eaddress[3]\, - eaddress_27 => \eaddress[27]\, eaddress_31 => - \eaddress[31]\, eaddress_15 => \eaddress[15]\, - eaddress_17 => \eaddress[17]\, eaddress_20 => - \eaddress[20]\, eaddress_18 => \eaddress[18]\, - eaddress_26 => \eaddress[26]\, eaddress_14 => - \eaddress[14]\, eaddress_21 => \eaddress[21]\, - eaddress_25 => \eaddress[25]\, eaddress_29 => - \eaddress[29]\, eaddress_19 => \eaddress[19]\, - eaddress_23 => \eaddress[23]\, eaddress_22 => - \eaddress[22]\, eaddress_9 => \eaddress[9]\, eaddress_10 - => \eaddress[10]\, eaddress_7 => \eaddress[7]\, - eaddress_8 => \eaddress[8]\, data_0_22 => \data_0[22]\, - data_0_20 => \data_0_0[20]\, data_0_18 => \data_0[18]\, - data_0_15 => \data_0_0[15]\, data_0_11 => \data_0_0[11]\, - data_0_7 => \data_0_0[7]\, data_0_12 => \data_0_0[12]\, - data_0_31 => \data_0_0[31]\, data_0_29 => \data_0_0[29]\, - dco_i_2(132) => \dco_i_2[132]\, maddress_0_2 => - \maddress_0[3]\, maddress_0_0 => \maddress_0[1]\, msu => - msu, error_i_2 => error_i_2, read_1 => read, write_0 => - write, mexc_2 => mexc, enaddr => enaddr, eenaddr => - eenaddr, N_26 => N_26, lock => lock, N_28 => N_28, su_0 - => su, rfe2 => rfe2, ren2 => ren2, mexc => mexc_0, - N_3305_0 => N_3305, intack_2 => \intack\, wren => wren, - rfe1 => rfe1, ren1 => ren1, werr_2 => werr, rstate_1188n - => rstate_1188n, vaddr_1_sqmuxa_0_a2_4_m1_e_24 => - vaddr_1_sqmuxa_0_a2_4_m1_e_24, ldlock_3_0 => ldlock_3_0, - rst_RNIINI1H => rst_RNIINI1H, rbranch => rbranch, r_N_6 - => r_N_6, un1_addout_12 => un1_addout_12, flush_i_0 => - flush_i_0, N_3389_i_0 => N_3389_i_0, N_3227_i_0 => - N_3227_i_0, N_3387_i_0 => N_3387_i_0, nullify => nullify, - ldlock_2 => ldlock_2, fbranch => fbranch, d_m5_0_a3_2 => - d_m5_0_a3_2, hold_pc_7 => hold_pc_7, nullify2_0_sqmuxa - => nullify2_0_sqmuxa, me_nullify2_1_2 => me_nullify2_1_2, - un9_icc_check_bp => un9_icc_check_bp, inull => inull, - de_hold_pc_1 => de_hold_pc_1, rst => rst, un17_casaen_0_0 - => un17_casaen_0_0, xc_exception_1_0 => xc_exception_1_0, - mds => mds, ra_bpmiss_1_0 => ra_bpmiss_1_0, read_0 => - read_0, holdn => holdn, lclk_c => lclk_c); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - c0mmu : mmu_cache - port map(hrdata_1_0_1(1) => hrdata_1_0_1(1), data_2_17 => - data_24, data_2_12 => data_19, data_2_1 => data_8, - data_1_10 => data_5, data_1_8 => data_3, nbo_5_0(1) => - nbo_5_0(1), nbo_5_0(0) => nbo_5_0(0), htrans(1) => - htrans(1), iosn_0(93) => iosn_0(93), htrans_tz(1) => - htrans_tz(1), haddr(31) => haddr(31), haddr(30) => - haddr(30), haddr(29) => haddr(29), haddr(28) => haddr(28), - haddr(27) => haddr(27), haddr(26) => haddr(26), haddr(25) - => haddr(25), haddr(24) => haddr(24), haddr(23) => - haddr(23), haddr(22) => haddr(22), haddr(21) => haddr(21), - haddr(20) => haddr(20), haddr(19) => haddr(19), haddr(18) - => haddr(18), haddr(17) => haddr(17), haddr(16) => - haddr(16), haddr(15) => haddr(15), haddr(14) => haddr(14), - haddr(13) => haddr(13), haddr(12) => haddr(12), haddr(11) - => haddr(11), haddr(10) => haddr(10), haddr(9) => - haddr(9), haddr(8) => haddr(8), haddr(7) => haddr(7), - haddr(6) => haddr(6), haddr(5) => haddr(5), haddr(4) => - haddr(4), haddr(3) => haddr(3), haddr(2) => haddr(2), - hwdata_16 => hwdata_16, hwdata_3 => hwdata_3, hwdata_9 - => hwdata_9, hwdata_11 => hwdata_11, hwdata_25 => - hwdata_25, hwdata_27 => hwdata_27, hwdata_13 => hwdata_13, - hwdata_4 => hwdata_4, hwdata_12 => hwdata_12, hwdata_23 - => hwdata_23, hwdata_28 => hwdata_28, hwdata_1 => - hwdata_1, hwdata_14 => hwdata_14, hwdata_0 => hwdata_0, - hwdata_15 => hwdata_15, iosn_1(93) => iosn_1(93), - hsize_5(1) => hsize_5(1), hgrant(0) => hgrant(0), - hresp(0) => hresp(0), iosn_2(93) => iosn_2(93), addr_28 - => addr(30), address_1 => address(1), address_0 => - address(0), dataout(35) => dataout(35), dataout(34) => - dataout(34), dataout(33) => dataout(33), dataout(32) => - dataout(32), dataout(31) => dataout(31), dataout(30) => - dataout(30), dataout(29) => dataout(29), dataout(28) => - dataout(28), dataout(27) => dataout(27), dataout(26) => - dataout(26), dataout(25) => dataout(25), dataout(24) => - dataout(24), dataout(23) => dataout(23), dataout(22) => - dataout(22), dataout(21) => dataout(21), dataout(20) => - dataout(20), dataout(19) => dataout(19), dataout(18) => - dataout(18), dataout(17) => dataout(17), dataout(16) => - dataout(16), dataout(15) => dataout(15), dataout(14) => - dataout(14), dataout(13) => dataout(13), dataout(12) => - dataout(12), dataout(11) => dataout(11), dataout(10) => - dataout(10), dataout(9) => dataout(9), dataout(8) => - dataout(8), dataout(7) => dataout(7), dataout(6) => - dataout(6), dataout(5) => dataout(5), dataout(4) => - dataout(4), dataout(3) => dataout(3), dataout(2) => - dataout(2), dataout(1) => dataout(1), dataout(0) => - dataout(0), data_0_0_31 => \data_0_0[31]\, data_0_0_24 - => \data_0_0[24]\, data_0_0_29 => \data_0_0[29]\, - data_0_0_13 => \data_0[13]\, data_0_0_30 => - \data_0_0[30]\, data_0_0_27 => \data_0_0[27]\, - data_0_0_20 => \data_0[20]\, data_0_0_14 => \data_0[14]\, - data_0_0_25 => \data_0_0[25]\, data_0_0_16 => - \data_0[16]\, data_0_0_17 => \data_0[17]\, data_0_0_28 - => \data_0_0[28]\, data_0_0_8 => \data_0_0[8]\, - data_0_0_11 => \data_0[11]\, data_0_0_21 => - \data_0_0[21]\, data_0_0_4 => \data_0_0[4]\, data_0_0_26 - => \data_0_0[26]\, data_0_0_0 => \data_0_0[0]\, - data_0_0_12 => \data_0_0[12]\, data_0_0_15 => - \data_0[15]\, data_0_0_7 => \data_0_0[7]\, mcdo_m_0_29 - => \mcdo_m_0[31]\, mcdo_m_0_22 => \mcdo_m_0[24]\, - mcdo_m_0_27 => \mcdo_m_0[29]\, mcdo_m_0_0 => - \mcdo_m_0[2]\, mcdo_m_0_16 => \mcdo_m_0[18]\, mcdo_m_0_21 - => \mcdo_m_0[23]\, mcdo_m_0_20 => \mcdo_m_0[22]\, - mcdo_m_0_17 => \mcdo_m_0[19]\, mcdo_m_0_4 => - \mcdo_m_0[6]\, mcdo_m_0_7 => \mcdo_m_0[9]\, - rdatav_0_1_0_iv_4_22 => \rdatav_0_1_0_iv_4[31]\, - rdatav_0_1_0_iv_4_20 => \rdatav_0_1_0_iv_4[29]\, - rdatav_0_1_0_iv_4_0 => \rdatav_0_1_0_iv_4[9]\, - rdatav_0_1_0_iv_4_14 => \rdatav_0_1_0_iv_4[23]\, - rdatav_0_1_0_iv_5_6 => \rdatav_0_1_0_iv_5[24]\, - rdatav_0_1_0_iv_5_1 => \rdatav_0_1_0_iv_5[19]\, - rdatav_0_1_0_iv_5_0 => \rdatav_0_1_0_iv_5[18]\, - rdatav_0_1_0_iv_5_4 => \rdatav_0_1_0_iv_5[22]\, - eaddress_29 => \eaddress[31]\, eaddress_22 => - \eaddress[24]\, eaddress_21 => \eaddress[23]\, - eaddress_13 => \eaddress[15]\, eaddress_28 => - \eaddress[30]\, eaddress_18 => \eaddress[20]\, eaddress_6 - => \eaddress[8]\, eaddress_10 => \eaddress[12]\, - eaddress_25 => \eaddress[27]\, eaddress_23 => - \eaddress[25]\, eaddress_19 => \eaddress[21]\, eaddress_9 - => \eaddress[11]\, eaddress_17 => \eaddress[19]\, - eaddress_27 => \eaddress[29]\, eaddress_15 => - \eaddress[17]\, eaddress_5 => \eaddress[7]\, eaddress_20 - => \eaddress[22]\, eaddress_2 => \eaddress[4]\, - eaddress_24 => \eaddress[26]\, eaddress_16 => - \eaddress[18]\, eaddress_12 => \eaddress[14]\, eaddress_4 - => \eaddress[6]\, eaddress_1 => \eaddress[3]\, - eaddress_8 => \eaddress[10]\, eaddress_0 => \eaddress[2]\, - eaddress_3 => \eaddress[5]\, eaddress_7 => \eaddress[9]\, - asi_4 => \asi[4]\, asi_3 => \asi[3]\, asi_2 => \asi[2]\, - asi_1 => \asi[1]\, asi_0(0) => \asi[0]\, - rdatav_0_1_0_iv_7(2) => \rdatav_0_1_0_iv_7[2]\, - rdatav_0_1_0_iv_0_2(10) => \rdatav_0_1_0_iv_0_2[10]\, - rdatav_0_1_1_iv_7(6) => \rdatav_0_1_1_iv_7[6]\, - edata2_0_iv(23) => \edata2_0_iv[23]\, edata2_0_iv(22) => - \edata2_0_iv[22]\, edata2_0_iv(21) => \edata2_0_iv[21]\, - edata2_0_iv(20) => \edata2_0_iv[20]\, edata2_0_iv(19) => - \edata2_0_iv[19]\, edata2_0_iv(18) => \edata2_0_iv[18]\, - edata2_0_iv(17) => \edata2_0_iv[17]\, edata2_0_iv(16) => - \edata2_0_iv[16]\, edata2_0_iv(15) => \edata2_0_iv[15]\, - edata2_0_iv(14) => \edata2_0_iv[14]\, edata2_0_iv(13) => - \edata2_0_iv[13]\, edata2_0_iv(12) => \edata2_0_iv[12]\, - edata2_0_iv(11) => \edata2_0_iv[11]\, edata2_0_iv(10) => - \edata2_0_iv[10]\, edata2_0_iv(9) => \edata2_0_iv[9]\, - edata2_0_iv(8) => \edata2_0_iv[8]\, edata2_0_iv(7) => - \edata2_0_iv[7]\, edata2_0_iv(6) => \edata2_0_iv[6]\, - edata2_0_iv(5) => \edata2_0_iv[5]\, edata2_0_iv(4) => - \edata2_0_iv[4]\, edata2_0_iv(3) => \edata2_0_iv[3]\, - edata2_0_iv(2) => \edata2_0_iv[2]\, edata2_0_iv(1) => - \edata2_0_iv[1]\, edata2_0_iv(0) => \edata2_0_iv[0]\, - newtag_1_0(27) => newtag_1_0(27), newtag_1_0(26) => - newtag_1_0(26), newtag_1_0(25) => newtag_1_0(25), - newtag_1_0(24) => newtag_1_0(24), xaddress_RNID252J1(10) - => xaddress_RNID252J1(10), dstate_i_0_RNIL7FGFS(8) => - dstate_i_0_RNIL7FGFS(8), xaddress_RNI2MB27S2(15) => - xaddress_RNI2MB27S2(15), xaddress_RNIID927S2(16) => - xaddress_RNIID927S2(16), xaddress_RNIN7J17S2(14) => - xaddress_RNIN7J17S2(14), xaddress_RNIC5A27S2(21) => - xaddress_RNIC5A27S2(21), xaddress_RNI0GI17S2(17) => - xaddress_RNI0GI17S2(17), xaddress_RNI9MB27S2(23) => - xaddress_RNI9MB27S2(23), xaddress_RNI1D927S2(20) => - xaddress_RNI1D927S2(20), xaddress_RNICFI17S2(13) => - xaddress_RNICFI17S2(13), xaddress_RNITMH17S2(12) => - xaddress_RNITMH17S2(12), xaddress_RNIJI2O22(1) => - xaddress_RNIJI2O22(1), xaddress_RNIP2BVK1(1) => - xaddress_RNIP2BVK1(1), xaddress_RNIK99NK1(1) => - xaddress_RNIK99NK1(1), xaddress_RNI1I3MQ1(0) => - xaddress_RNI1I3MQ1(0), xaddress_RNILK99L1(1) => - xaddress_RNILK99L1(1), xaddress_RNILHOK61(1) => - xaddress_RNILHOK61(1), xaddress_RNIEHIUT1(1) => - xaddress_RNIEHIUT1(1), xaddress_RNI1Q9ST1(1) => - xaddress_RNI1Q9ST1(1), dstate_RNIFS6E51(1) => - dstate_RNIFS6E51(1), dstate_RNI1G47MJ(1) => - dstate_RNI1G47MJ(1), dstate_i_0_RNIH0PPES(8) => - dstate_i_0_RNIH0PPES(8), dco_i_2(132) => \dco_i_2[132]\, - size_0(1) => \size[1]\, size_0(0) => \size[0]\, - dstate_RNIFPT581(1) => dstate_RNIFPT581(1), - dstate_RNIC3QA81(1) => dstate_RNIC3QA81(1), - edata2_iv_i_0(31) => \edata2_iv_i_0[31]\, - edata2_iv_i_0(30) => \edata2_iv_i_0[30]\, - edata2_iv_i_0(29) => \edata2_iv_i_0[29]\, - edata2_iv_i_0(28) => \edata2_iv_i_0[28]\, - edata2_iv_i_0(27) => \edata2_iv_i_0[27]\, - edata2_iv_i_0(26) => \edata2_iv_i_0[26]\, - edata2_iv_i_0(25) => \edata2_iv_i_0[25]\, - edata2_iv_i_0(24) => \edata2_iv_i_0[24]\, - faddr_RNIEHR0O(1) => faddr_RNIEHR0O(1), faddr_RNI7879K(0) - => faddr_RNI7879K(0), dci_m_0 => dci_m_0, dci_m_1 => - dci_m_1, dci_m_2 => dci_m_2, dci_m_3 => dci_m_3, dci_m_5 - => dci_m_5, dci_m_6 => dci_m_6, faddr_RNI7MK691(6) => - faddr_RNI7MK691(6), size_0_d0 => size_0(0), - xaddress_RNIFP43F(2) => xaddress_RNIFP43F(2), - xaddress_RNITFTTE(3) => xaddress_RNITFTTE(3), - dstate_i_RNI29QQ7J3(8) => dstate_i_RNI29QQ7J3(8), - faddr_RNIB0UOO(2) => faddr_RNIB0UOO(2), data_10 => - data_1_2, data_8 => data_1_0, data_5 => data_0, data_13 - => data_1_5, data_24 => data_1_16, data_29 => data_1_21, - un1_p0_2_0_350 => un1_p0_2_0_350, un1_p0_2_0_0 => - un1_p0_2_0_0, fpc(31) => \fpc[31]\, fpc(30) => \fpc[30]\, - fpc(29) => \fpc[29]\, fpc(28) => \fpc[28]\, fpc(27) => - \fpc[27]\, fpc(26) => \fpc[26]\, fpc(25) => \fpc[25]\, - fpc(24) => \fpc[24]\, fpc(23) => \fpc[23]\, fpc(22) => - \fpc[22]\, fpc(21) => \fpc[21]\, fpc(20) => \fpc[20]\, - fpc(19) => \fpc[19]\, fpc(18) => \fpc[18]\, fpc(17) => - \fpc[17]\, fpc(16) => \fpc[16]\, fpc(15) => \fpc[15]\, - fpc(14) => \fpc[14]\, fpc(13) => \fpc[13]\, fpc(12) => - \fpc[12]\, fpc(11) => \fpc[11]\, fpc(10) => \fpc[10]\, - fpc(9) => \fpc[9]\, fpc(8) => \fpc[8]\, fpc(7) => - \fpc[7]\, fpc(6) => \fpc[6]\, fpc(5) => \fpc[5]\, fpc(4) - => \fpc[4]\, fpc(3) => \fpc[3]\, fpc(2) => \fpc[2]\, - dataout_2(31) => dataout_2(31), dataout_2(30) => - dataout_2(30), dataout_2(29) => dataout_2(29), - dataout_2(28) => dataout_2(28), dataout_2(27) => - dataout_2(27), dataout_2(26) => dataout_2(26), - dataout_2(25) => dataout_2(25), dataout_2(24) => - dataout_2(24), dataout_2(23) => dataout_2(23), - dataout_2(22) => dataout_2(22), dataout_2(21) => - dataout_2(21), dataout_2(20) => dataout_2(20), - dataout_2(19) => dataout_2(19), dataout_2(18) => - dataout_2(18), dataout_2(17) => dataout_2(17), - dataout_2(16) => dataout_2(16), dataout_2(15) => - dataout_2(15), dataout_2(14) => dataout_2(14), - dataout_2(13) => dataout_2(13), dataout_2(12) => - dataout_2(12), dataout_2(11) => dataout_2(11), - dataout_2(10) => dataout_2(10), dataout_2(9) => - dataout_2(9), dataout_2(8) => dataout_2(8), dataout_2(7) - => dataout_2(7), dataout_2(6) => dataout_2(6), - dataout_2(5) => dataout_2(5), dataout_2(4) => - dataout_2(4), dataout_2(3) => dataout_2(3), dataout_2(2) - => dataout_2(2), dataout_2(1) => dataout_2(1), - dataout_2(0) => dataout_2(0), maddress(31) => - \maddress[31]\, maddress(30) => \maddress[30]\, - maddress(29) => \maddress[29]\, maddress(28) => - \maddress[28]\, maddress(27) => \maddress[27]\, - maddress(26) => \maddress[26]\, maddress(25) => - \maddress[25]\, maddress(24) => \maddress[24]\, - maddress(23) => \maddress[23]\, maddress(22) => - \maddress[22]\, maddress(21) => \maddress[21]\, - maddress(20) => \maddress[20]\, maddress(19) => - \maddress[19]\, maddress(18) => \maddress[18]\, - maddress(17) => \maddress[17]\, maddress(16) => - \maddress[16]\, maddress(15) => \maddress[15]\, - maddress(14) => \maddress[14]\, maddress(13) => - \maddress[13]\, maddress(12) => \maddress[12]\, - maddress(11) => \maddress[11]\, maddress(10) => - \maddress[10]\, maddress(9) => \maddress[9]\, maddress(8) - => \maddress[8]\, maddress(7) => \maddress[7]\, - maddress(6) => \maddress[6]\, maddress(5) => - \maddress[5]\, maddress(4) => \maddress[4]\, maddress(3) - => \maddress[3]\, maddress(2) => \maddress[2]\, - maddress(1) => \maddress[1]\, maddress(0) => - \maddress[0]\, un1_p0_6(0) => \un1_p0_6[0]\, - dataout_0(35) => dataout_0(35), dataout_0(34) => - dataout_0(34), dataout_0(33) => dataout_0(33), - dataout_0(32) => dataout_0(32), dataout_0(31) => - dataout_0(31), dataout_0(30) => dataout_0(30), - dataout_0(29) => dataout_0(29), dataout_0(28) => - dataout_0(28), dataout_0(27) => dataout_0(27), - dataout_0(26) => dataout_0(26), dataout_0(25) => - dataout_0(25), dataout_0(24) => dataout_0(24), - dataout_0(23) => dataout_0(23), dataout_0(22) => - dataout_0(22), dataout_0(21) => dataout_0(21), - dataout_0(20) => dataout_0(20), dataout_0(19) => - dataout_0(19), dataout_0(18) => dataout_0(18), - dataout_0(17) => dataout_0(17), dataout_0(16) => - dataout_0(16), dataout_0(15) => dataout_0(15), - dataout_0(14) => dataout_0(14), dataout_0(13) => - dataout_0(13), dataout_0(12) => dataout_0(12), - dataout_0(11) => dataout_0(11), dataout_0(10) => - dataout_0(10), dataout_0(9) => dataout_0(9), dataout_0(8) - => dataout_0(8), dataout_0(7) => dataout_0(7), - dataout_0(6) => dataout_0(6), dataout_0(5) => - dataout_0(5), dataout_0(4) => dataout_0(4), dataout_0(3) - => dataout_0(3), dataout_0(2) => dataout_0(2), - dataout_0(1) => dataout_0(1), dataout_0(0) => - dataout_0(0), dataout_1(31) => dataout_1(31), - dataout_1(30) => dataout_1(30), dataout_1(29) => - dataout_1(29), dataout_1(28) => dataout_1(28), - dataout_1(27) => dataout_1(27), dataout_1(26) => - dataout_1(26), dataout_1(25) => dataout_1(25), - dataout_1(24) => dataout_1(24), dataout_1(23) => - dataout_1(23), dataout_1(22) => dataout_1(22), - dataout_1(21) => dataout_1(21), dataout_1(20) => - dataout_1(20), dataout_1(19) => dataout_1(19), - dataout_1(18) => dataout_1(18), dataout_1(17) => - dataout_1(17), dataout_1(16) => dataout_1(16), - dataout_1(15) => dataout_1(15), dataout_1(14) => - dataout_1(14), dataout_1(13) => dataout_1(13), - dataout_1(12) => dataout_1(12), dataout_1(11) => - dataout_1(11), dataout_1(10) => dataout_1(10), - dataout_1(9) => dataout_1(9), dataout_1(8) => - dataout_1(8), dataout_1(7) => dataout_1(7), dataout_1(6) - => dataout_1(6), dataout_1(5) => dataout_1(5), - dataout_1(4) => dataout_1(4), dataout_1(3) => - dataout_1(3), dataout_1(2) => dataout_1(2), dataout_1(1) - => dataout_1(1), dataout_1(0) => dataout_1(0), - vitdatain_0_1_0(22) => vitdatain_0_1_0(22), - vaddress_RNIUFAKMI(15) => vaddress_RNIUFAKMI(15), - istate_RNIA8N5H(0) => istate_RNIA8N5H(0), hrdata_0_15 => - hrdata_0_15, hrdata_0_0 => hrdata_0_0, hrdata_0_26 => - hrdata_0_26, hrdata_0_2 => hrdata_0_2, hrdata_0_1 => - hrdata_0_1, hrdata_0_7 => hrdata_0_7, hrdata_0_10 => - hrdata_0_10, hrdata_0_11 => hrdata_0_11, hrdata_0_12 => - hrdata_0_12, hrdata_0_27 => hrdata_0_27, hrdata_0_21 => - hrdata_0_21, hrdata_0_8 => hrdata_0_8, hrdata_0_9 => - hrdata_0_9, hrdata_0_13 => hrdata_0_13, hrdata_0_14 => - hrdata_0_14, hrdata_0_22 => hrdata_0_22, hrdata_0_23 => - hrdata_0_23, hrdata_0_16 => hrdata_0_16, hrdata_0_17 => - hrdata_0_17, hrdata_0_18 => hrdata_0_18, hrdata_0_4 => - hrdata_0_4, hrdata_0_24 => hrdata_0_24, hrdata_0_3 => - hrdata_0_3, data_0(31) => \data_0[31]\, data_0(30) => - \data_0[30]\, data_0(29) => \data_0[29]\, data_0(28) => - \data_0[28]\, data_0(27) => \data_0[27]\, data_0(26) => - \data_0[26]\, data_0(25) => \data_0[25]\, data_0(24) => - \data_0[24]\, data_0(23) => \data_0[23]\, data_0(22) => - \data_0[22]\, data_0(21) => \data_0[21]\, data_0(20) => - \data_0_0[20]\, data_0(19) => \data_0[19]\, data_0(18) - => \data_0[18]\, data_0(17) => \data_0_0[17]\, - data_0(16) => \data_0_0[16]\, data_0(15) => - \data_0_0[15]\, data_0(14) => \data_0_0[14]\, data_0(13) - => \data_0_0[13]\, data_0(12) => \data_0[12]\, - data_0(11) => \data_0_0[11]\, data_0(10) => \data_0[10]\, - data_0(9) => \data_0[9]\, data_0(8) => \data_0[8]\, - data_0(7) => \data_0[7]\, data_0(6) => \data_0[6]\, - data_0(5) => \data_0[5]\, data_0(4) => \data_0[4]\, - data_0(3) => \data_0[3]\, data_0(2) => \data_0[2]\, - data_0(1) => \data_0[1]\, data_0(0) => \data_0[0]\, rpc_0 - => \rpc[2]\, rpc_1 => \rpc[3]\, rpc_3 => \rpc[5]\, rpc_2 - => \rpc[4]\, rpc_7 => \rpc[9]\, rpc_8 => \rpc[10]\, - rpc_5 => \rpc[7]\, rpc_6 => \rpc[8]\, - vaddress_RNI8EVQ36(2) => vaddress_RNI8EVQ36(2), hrdata_9 - => hrdata_9, hrdata_10 => hrdata_10, hrdata_11 => - hrdata_11, hrdata_13 => hrdata_13, hrdata_14 => hrdata_14, - hrdata_17 => hrdata_17, hrdata_24 => hrdata_24, - hrdata_0_d0 => hrdata_0_d0, hrdata_1 => hrdata_1, - hrdata_8 => hrdata_8, hrdata_12 => hrdata_12, hrdata_15 - => hrdata_15, hrdata_16 => hrdata_16, hrdata_18 => - hrdata_18, hrdata_21 => hrdata_21, hrdata_22 => hrdata_22, - hrdata_23 => hrdata_23, hrdata_26 => hrdata_26, hrdata_27 - => hrdata_27, hrdata_2 => hrdata_2, hrdata_3 => hrdata_3, - hrdata_4 => hrdata_4, hrdata_7 => hrdata_7, hrdata_5 => - hrdata_5, hrdata_6 => hrdata_6, hrdata_28 => hrdata_28, - hrdata_29 => hrdata_29, hrdata_30 => hrdata_30, hrdata_31 - => hrdata_31, istate_RNIPSU8G(0) => istate_RNIPSU8G(0), - maddress_0_0 => \maddress_0[1]\, maddress_0_2 => - \maddress_0[3]\, istate_RNIEC82C(0) => istate_RNIEC82C(0), - istate_RNI7BUID(0) => istate_RNI7BUID(0), - istate_RNIV33V9(0) => istate_RNIV33V9(0), - istate_RNI6LOO6(0) => istate_RNI6LOO6(0), - istate_RNIKJBN8(0) => istate_RNIKJBN8(0), - istate_RNIN6957(0) => istate_RNIN6957(0), - istate_RNIOJJE1(0) => istate_RNIOJJE1(0), - istate_RNIR2JU8(0) => istate_RNIR2JU8(0), - istate_RNIJSOBE(0) => istate_RNIJSOBE(0), - istate_RNIRASC8(0) => istate_RNIRASC8(0), - istate_RNIS4VK8(0) => istate_RNIS4VK8(0), - istate_RNIENB3M(0) => istate_RNIENB3M(0), - istate_RNIAP6PI(0) => istate_RNIAP6PI(0), - vaddress_RNIQFAKMI(13) => vaddress_RNIQFAKMI(13), - istate_RNIMRTH8(0) => istate_RNIMRTH8(0), - istate_RNIGUTA8(0) => istate_RNIGUTA8(0), - istate_RNI6PSS1(0) => istate_RNI6PSS1(0), - istate_RNIOVC5J(0) => istate_RNIOVC5J(0), - istate_RNIVTQIJ(0) => istate_RNIVTQIJ(0), - istate_RNIM2DE7(0) => istate_RNIM2DE7(0), - istate_RNI5V68H(0) => istate_RNI5V68H(0), - vaddress_RNI2GAKMI(17) => vaddress_RNI2GAKMI(17), - vaddress_RNI4GAKMI(18) => vaddress_RNI4GAKMI(18), - istate_RNIK9NF8(0) => istate_RNIK9NF8(0), - istate_RNILTAC8(0) => istate_RNILTAC8(0), - istate_RNI8BL1A(0) => istate_RNI8BL1A(0), - istate_RNI2MM6D(0) => istate_RNI2MM6D(0), - vaddress_RNIFCB8U6(3) => vaddress_RNIFCB8U6(3), - istate_RNIG7IIA(0) => istate_RNIG7IIA(0), - istate_RNIH0NBI(0) => istate_RNIH0NBI(0), - faddr_RNI7H6KT8(0) => faddr_RNI7H6KT8(0), - istate_RNIUCOFG(0) => istate_RNIUCOFG(0), - istate_RNI57KLB(0) => istate_RNI57KLB(0), - vaddress_RNISFAKMI(14) => vaddress_RNISFAKMI(14), - vaddress_RNIUNAKMI(22) => vaddress_RNIUNAKMI(22), - istate_RNIAJH4F(0) => istate_RNIAJH4F(0), - istate_RNI6HPAI(0) => istate_RNI6HPAI(0), ctx(7) => - ctx(7), ctx(6) => ctx(6), ctx(5) => ctx(5), ctx(4) => - ctx(4), ctx(3) => ctx(3), ctx(2) => ctx(2), ctx(1) => - ctx(1), ctx(0) => ctx(0), un1_p0_2_i_0 => un1_p0_2_i_0, - un1_p0_2_i_4 => un1_p0_2_i_4, vaddress_RNIJG6QR7(4) => - vaddress_RNIJG6QR7(4), vaddress_RNIOFAKMI(12) => - vaddress_RNIOFAKMI(12), vaddress_RNI0OAKMI(23) => - vaddress_RNI0OAKMI(23), vaddress_RNI0GAKMI(16) => - vaddress_RNI0GAKMI(16), faddr_RNIKVTLT9(1) => - faddr_RNIKVTLT9(1), faddr_RNIDN2CUE(6) => - faddr_RNIDN2CUE(6), faddr_RNI0FOJNE(4) => - faddr_RNI0FOJNE(4), faddr_RNI7UFASD(5) => - faddr_RNI7UFASD(5), vaddress_RNIQNAKMI(20) => - vaddress_RNIQNAKMI(20), faddr_RNISJSHQA(2) => - faddr_RNISJSHQA(2), vaddress_RNI6GAKMI(19) => - vaddress_RNI6GAKMI(19), vaddress_RNISNAKMI(21) => - vaddress_RNISNAKMI(21), faddr_RNIUT72LB(3) => - faddr_RNIUT72LB(3), istate_RNIJCMP6(0) => - istate_RNIJCMP6(0), N_546 => N_546, mmu_cache_VCC => - proc3_VCC, N_264 => N_264, N_262 => N_262, N_78 => N_78, - bo_5842_d_0 => bo_5842_d_0, un1_htrans_1_sqmuxa_0 => - un1_htrans_1_sqmuxa_0, hlock => hlock, N_5054 => N_5054, - lb_0_sqmuxa_1 => lb_0_sqmuxa_1, hbusreq => hbusreq, - un60_nbo => un60_nbo, N_457 => N_457, N_462 => N_462, - N_467 => N_467, werr_2_m_0 => werr_2_m_0, un91_nbo_i_0 - => un91_nbo_i_0, N_138 => N_138, N_139 => N_139, - bo_5842_d => bo_5842_d, N_458 => N_458, N_459 => N_459, - N_461 => N_461, N_463 => N_463, N_468 => N_468, - hwrite_1_m_0 => hwrite_1_m_0, N_466 => N_466, - htrans_0_sqmuxa_2 => htrans_0_sqmuxa_2, werr => werr, - N_3254_0 => N_3254_0, enaddr => enaddr, lock_0 => lock, - vaddr_1_sqmuxa_0_a2_4_m1_e_24 => - vaddr_1_sqmuxa_0_a2_4_m1_e_24, un1_addout_12 => - un1_addout_12, read_0_0 => read_0, nullify => nullify, - intack => \intack\, nullify2_0_sqmuxa => - nullify2_0_sqmuxa, me_nullify2_1_2 => me_nullify2_1_2, - un17_casaen_0_0 => un17_casaen_0_0, N_330 => N_330, N_329 - => N_329, N_24 => N_24, flush_0_1_RNIPTA27S2 => - flush_0_1_RNIPTA27S2, flush_0_1_RNIBUA27S2 => - flush_0_1_RNIBUA27S2, N_16_i_0 => N_16_i_0, N_12_i_0 => - N_12_i_0, read_RNIEEGDD1 => read_RNIEEGDD1, - read_RNI75LJ31 => read_RNI75LJ31, read_RNIC70OF1 => - read_RNIC70OF1, read_RNISLPNU => read_RNISLPNU, - read_RNIQMJI41 => read_RNIQMJI41, read_RNICAQK41 => - read_RNICAQK41, flush_RNIGUM2OH3 => flush_RNIGUM2OH3, - read_RNIC9O9B1 => read_RNIC9O9B1, read_RNIFPFT31 => - read_RNIFPFT31, read_RNIEKS231 => read_RNIEKS231, N_26_0 - => N_26_0, N_3387_i_0 => N_3387_i_0, N_3227_i_0 => - N_3227_i_0, N_3239_i_0 => N_3239_i_0, mexc_1 => mexc_0, - un59_nbo => un59_nbo, flush_0_1_RNIOMB27S2 => - flush_0_1_RNIOMB27S2, read_RNICKHE91 => read_RNICKHE91, - read_RNIL633F1 => read_RNIL633F1, read_RNIMJHQT => - read_RNIMJHQT, read_RNI7G7G41 => read_RNI7G7G41, - read_RNI76N8R => read_RNI76N8R, read_RNIAQJ831 => - read_RNIAQJ831, read_RNI8DFM31 => read_RNI8DFM31, - read_RNIQFOD21 => read_RNIQFOD21, read_RNI0IQ7R => - read_RNI0IQ7R, N_3389_i_0 => N_3389_i_0, read_RNIRO4K31 - => read_RNIRO4K31, read_RNIQPCQ11 => read_RNIQPCQ11, - read_RNIQH64D1 => read_RNIQH64D1, read_1 => read, r_N_6 - => r_N_6, N_3305 => N_3305, N_3846 => N_3846, N_144 => - N_144, N_258 => N_258, N_259 => N_259, N_267 => N_267, - N_269 => N_269, N_270 => N_270, flush_RNIGBB873 => - flush_RNIGBB873, flush_RNIJEN4SI3 => flush_RNIJEN4SI3, - msu => msu, eenaddr => eenaddr, write => write, N_10 => - N_10, lclk_c => lclk_c, holdn => holdn, rst => rst, - flush_i_0 => flush_i_0, hold_pc_7 => hold_pc_7, - de_hold_pc_1 => de_hold_pc_1, un1_ici => un1_ici, - xc_exception_1_0 => xc_exception_1_0, ldlock_2 => - ldlock_2, un9_icc_check_bp => un9_icc_check_bp, - ldlock_3_0 => ldlock_3_0, inull => inull, N_78_0 => - N_78_0, N_262_0 => N_262_0, N_264_0 => N_264_0, N_982 => - N_982, N_983 => N_983, N_985 => N_985, N_981 => N_981, - mds => mds, flush2_0_0_RNIPJ5O2 => flush2_0_0_RNIPJ5O2, - flush2_0_0_RNITR5O2 => flush2_0_0_RNITR5O2, - flush2_0_0_RNIVV5O2 => flush2_0_0_RNIVV5O2, - flush2_0_0_RNI7G6O2 => flush2_0_0_RNI7G6O2, - flush2_0_0_RNI146O2 => flush2_0_0_RNI146O2, N_26 => N_26, - flush2 => flush2, N_986 => N_986, N_987 => N_987, N_28 - => N_28, N_980 => N_980, N_984 => N_984, flush2_RNI5I3N7 - => flush2_RNI5I3N7, flush2_RNIFMGM2 => flush2_RNIFMGM2, - rbranch => rbranch, fbranch => fbranch, mexc => mexc, su - => su); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 is - - port( rclk : in std_logic; - rena : in std_logic; - raddr : in std_logic_vector(7 downto 0); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic; - waddr : in std_logic_vector(7 downto 0); - din : in std_logic_vector(31 downto 0); - write : in std_logic - ); - -end proasic3_syncram_2p_work_leon3mp_wfp_rtl_1; - -architecture DEF_ARCH of - proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ0_1 is - - port( wdata : in std_logic_vector(31 downto 0); - waddr_0 : in std_logic_vector(7 downto 0); - raddr2 : in std_logic_vector(7 downto 0); - datain : in std_logic_vector(31 downto 0); - data2 : out std_logic_vector(31 downto 0); - waddr : in std_logic_vector(7 downto 0); - rfa2 : in std_logic_vector(7 downto 0); - wren : in std_logic; - ren2 : in std_logic; - lclk_c : in std_logic; - rfe2 : in std_logic; - write : in std_logic - ); - -end syncram_2pZ0_1; - -architecture DEF_ARCH of syncram_2pZ0_1 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - port( rclk : in std_logic := 'U'; - rena : in std_logic := 'U'; - raddr : in std_logic_vector(7 downto 0) := (others => 'U'); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic := 'U'; - waddr : in std_logic_vector(7 downto 0) := (others => 'U'); - din : in std_logic_vector(31 downto 0) := (others => 'U'); - write : in std_logic := 'U' - ); - end component; - - signal un4_scantestbp_0, un4_scantestbp_3, un4_scantestbp_2, - un4_scantestbp_7, un4_scantestbp_1, un5_scantestbp_7_0, - un4_scantestbp_4, un5_scantestbp_6_i_0, - un5_scantestbp_4_i_0, un5_scantestbp_2_i_0, - un5_scantestbp_0_i_0, un4_scantestbp, \dataoutx[1]\, - \dataoutx[2]\, \dataoutx[3]\, \dataoutx[25]\, - \dataoutx[26]\, \dataoutx[27]\, \dataoutx[28]\, - \dataoutx[29]\, \dataoutx[30]\, \dataoutx[31]\, - \dataoutx[18]\, \dataoutx[19]\, \dataoutx[20]\, - \dataoutx[21]\, \dataoutx[22]\, \dataoutx[23]\, - \dataoutx[24]\, \dataoutx[11]\, \dataoutx[12]\, - \dataoutx[13]\, \dataoutx[14]\, \dataoutx[15]\, - \dataoutx[16]\, \dataoutx[17]\, \dataoutx[4]\, - \dataoutx[5]\, \dataoutx[6]\, \dataoutx[7]\, - \dataoutx[8]\, \dataoutx[9]\, \dataoutx[10]\, - \dataoutx[0]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - Use entity work. - proasic3_syncram_2p_work_leon3mp_wfp_rtl_1(DEF_ARCH); -begin - - - \proa3.x0_RNI49JG2\ : MX2 - port map(A => \dataoutx[24]\, B => datain(24), S => - un4_scantestbp, Y => data2(24)); - - \proa3.x0_RNI25JG2\ : MX2 - port map(A => \dataoutx[15]\, B => datain(15), S => - un4_scantestbp, Y => data2(15)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_2\ : - XA1A - port map(A => rfa2(1), B => waddr(1), C => - un5_scantestbp_2_i_0, Y => un4_scantestbp_2); - - \proa3.x0_RNI89JG2\ : MX2 - port map(A => \dataoutx[28]\, B => datain(28), S => - un4_scantestbp_0, Y => data2(28)); - - \proa3.x0_RNI45JG2\ : MX2 - port map(A => \dataoutx[17]\, B => datain(17), S => - un4_scantestbp, Y => data2(17)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_1\ : - NOR3C - port map(A => write, B => rfe2, C => un5_scantestbp_0_i_0, - Y => un4_scantestbp_1); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_4_0\ : - XNOR2 - port map(A => waddr(4), B => rfa2(4), Y => - un5_scantestbp_4_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_3\ : - XA1A - port map(A => rfa2(3), B => waddr(3), C => - un5_scantestbp_4_i_0, Y => un4_scantestbp_3); - - \proa3.x0_RNIT4JG2\ : MX2 - port map(A => \dataoutx[10]\, B => datain(10), S => - un4_scantestbp, Y => data2(10)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_0_0\ : - XNOR2 - port map(A => waddr(0), B => rfa2(0), Y => - un5_scantestbp_0_i_0); - - \proa3.x0_RNIV4JG2\ : MX2 - port map(A => \dataoutx[12]\, B => datain(12), S => - un4_scantestbp, Y => data2(12)); - - \proa3.x0_RNI79JG2\ : MX2 - port map(A => \dataoutx[27]\, B => datain(27), S => - un4_scantestbp_0, Y => data2(27)); - - \proa3.x0_RNI3DJG2\ : MX2 - port map(A => \dataoutx[30]\, B => datain(30), S => - un4_scantestbp_0, Y => data2(30)); - - \proa3.x0_RNI99JG2\ : MX2 - port map(A => \dataoutx[29]\, B => datain(29), S => - un4_scantestbp_0, Y => data2(29)); - - \proa3.x0_RNI39JG2\ : MX2 - port map(A => \dataoutx[23]\, B => datain(23), S => - un4_scantestbp_0, Y => data2(23)); - - \proa3.x0_RNIU4JG2\ : MX2 - port map(A => \dataoutx[11]\, B => datain(11), S => - un4_scantestbp, Y => data2(11)); - - \proa3.x0_RNIEQ5J2\ : MX2 - port map(A => \dataoutx[0]\, B => datain(0), S => - un4_scantestbp, Y => data2(0)); - - \proa3.x0_RNI35JG2\ : MX2 - port map(A => \dataoutx[16]\, B => datain(16), S => - un4_scantestbp, Y => data2(16)); - - GND_i : GND - port map(Y => \GND\); - - \proa3.x0_RNI69JG2\ : MX2 - port map(A => \dataoutx[26]\, B => datain(26), S => - un4_scantestbp_0, Y => data2(26)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_6_0\ : - XNOR2 - port map(A => waddr(6), B => rfa2(6), Y => - un5_scantestbp_6_i_0); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_0\ : - NOR3C - port map(A => un4_scantestbp_3, B => un4_scantestbp_2, C - => un4_scantestbp_7, Y => un4_scantestbp_0); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_4\ : - XA1A - port map(A => rfa2(5), B => waddr(5), C => - un5_scantestbp_6_i_0, Y => un4_scantestbp_4); - - \proa3.x0_RNIKI6J2\ : MX2 - port map(A => \dataoutx[6]\, B => datain(6), S => - un4_scantestbp, Y => data2(6)); - - \proa3.x0_RNI65JG2\ : MX2 - port map(A => \dataoutx[19]\, B => datain(19), S => - un4_scantestbp_0, Y => data2(19)); - - \proa3.x0_RNIFU5J2\ : MX2 - port map(A => \dataoutx[1]\, B => datain(1), S => - un4_scantestbp_0, Y => data2(1)); - - \proa3.x0_RNIMQ6J2\ : MX2 - port map(A => \dataoutx[8]\, B => datain(8), S => - un4_scantestbp, Y => data2(8)); - - \proa3.x0\ : proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - port map(rclk => lclk_c, rena => ren2, raddr(7) => - raddr2(7), raddr(6) => raddr2(6), raddr(5) => raddr2(5), - raddr(4) => raddr2(4), raddr(3) => raddr2(3), raddr(2) - => raddr2(2), raddr(1) => raddr2(1), raddr(0) => - raddr2(0), dout(31) => \dataoutx[31]\, dout(30) => - \dataoutx[30]\, dout(29) => \dataoutx[29]\, dout(28) => - \dataoutx[28]\, dout(27) => \dataoutx[27]\, dout(26) => - \dataoutx[26]\, dout(25) => \dataoutx[25]\, dout(24) => - \dataoutx[24]\, dout(23) => \dataoutx[23]\, dout(22) => - \dataoutx[22]\, dout(21) => \dataoutx[21]\, dout(20) => - \dataoutx[20]\, dout(19) => \dataoutx[19]\, dout(18) => - \dataoutx[18]\, dout(17) => \dataoutx[17]\, dout(16) => - \dataoutx[16]\, dout(15) => \dataoutx[15]\, dout(14) => - \dataoutx[14]\, dout(13) => \dataoutx[13]\, dout(12) => - \dataoutx[12]\, dout(11) => \dataoutx[11]\, dout(10) => - \dataoutx[10]\, dout(9) => \dataoutx[9]\, dout(8) => - \dataoutx[8]\, dout(7) => \dataoutx[7]\, dout(6) => - \dataoutx[6]\, dout(5) => \dataoutx[5]\, dout(4) => - \dataoutx[4]\, dout(3) => \dataoutx[3]\, dout(2) => - \dataoutx[2]\, dout(1) => \dataoutx[1]\, dout(0) => - \dataoutx[0]\, wclk => lclk_c, waddr(7) => waddr_0(7), - waddr(6) => waddr_0(6), waddr(5) => waddr_0(5), waddr(4) - => waddr_0(4), waddr(3) => waddr_0(3), waddr(2) => - waddr_0(2), waddr(1) => waddr_0(1), waddr(0) => - waddr_0(0), din(31) => wdata(31), din(30) => wdata(30), - din(29) => wdata(29), din(28) => wdata(28), din(27) => - wdata(27), din(26) => wdata(26), din(25) => wdata(25), - din(24) => wdata(24), din(23) => wdata(23), din(22) => - wdata(22), din(21) => wdata(21), din(20) => wdata(20), - din(19) => wdata(19), din(18) => wdata(18), din(17) => - wdata(17), din(16) => wdata(16), din(15) => wdata(15), - din(14) => wdata(14), din(13) => wdata(13), din(12) => - wdata(12), din(11) => wdata(11), din(10) => wdata(10), - din(9) => wdata(9), din(8) => wdata(8), din(7) => - wdata(7), din(6) => wdata(6), din(5) => wdata(5), din(4) - => wdata(4), din(3) => wdata(3), din(2) => wdata(2), - din(1) => wdata(1), din(0) => wdata(0), write => wren); - - \proa3.x0_RNI19JG2\ : MX2 - port map(A => \dataoutx[21]\, B => datain(21), S => - un4_scantestbp_0, Y => data2(21)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp\ : - NOR3C - port map(A => un4_scantestbp_3, B => un4_scantestbp_2, C - => un4_scantestbp_7, Y => un4_scantestbp); - - \proa3.x0_RNIJE6J2\ : MX2 - port map(A => \dataoutx[5]\, B => datain(5), S => - un4_scantestbp, Y => data2(5)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_2_0\ : - XNOR2 - port map(A => waddr(2), B => rfa2(2), Y => - un5_scantestbp_2_i_0); - - \proa3.x0_RNI15JG2\ : MX2 - port map(A => \dataoutx[14]\, B => datain(14), S => - un4_scantestbp, Y => data2(14)); - - \proa3.x0_RNIG26J2\ : MX2 - port map(A => \dataoutx[2]\, B => datain(2), S => - un4_scantestbp_0, Y => data2(2)); - - \proa3.x0_RNI09JG2\ : MX2 - port map(A => \dataoutx[20]\, B => datain(20), S => - un4_scantestbp_0, Y => data2(20)); - - \proa3.x0_RNINU6J2\ : MX2 - port map(A => \dataoutx[9]\, B => datain(9), S => - un4_scantestbp, Y => data2(9)); - - \proa3.x0_RNIIA6J2\ : MX2 - port map(A => \dataoutx[4]\, B => datain(4), S => - un4_scantestbp, Y => data2(4)); - - \proa3.x0_RNI59JG2\ : MX2 - port map(A => \dataoutx[25]\, B => datain(25), S => - un4_scantestbp_0, Y => data2(25)); - - \proa3.x0_RNI05JG2\ : MX2 - port map(A => \dataoutx[13]\, B => datain(13), S => - un4_scantestbp, Y => data2(13)); - - \proa3.x0_RNILM6J2\ : MX2 - port map(A => \dataoutx[7]\, B => datain(7), S => - un4_scantestbp, Y => data2(7)); - - \proa3.x0_RNI4DJG2\ : MX2 - port map(A => \dataoutx[31]\, B => datain(31), S => - un4_scantestbp_0, Y => data2(31)); - - \proa3.x0_RNIH66J2\ : MX2 - port map(A => \dataoutx[3]\, B => datain(3), S => - un4_scantestbp_0, Y => data2(3)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un5_scantestbp_7_0\ : - XNOR2 - port map(A => waddr(7), B => rfa2(7), Y => - un5_scantestbp_7_0); - - \proa3.x0_RNI55JG2\ : MX2 - port map(A => \dataoutx[18]\, B => datain(18), S => - un4_scantestbp_0, Y => data2(18)); - - \proa3.x0_RNI29JG2\ : MX2 - port map(A => \dataoutx[22]\, B => datain(22), S => - un4_scantestbp_0, Y => data2(22)); - - - \wrfst_gen.no_contention_check.wfrstblocknoc.comb.un4_scantestbp_7\ : - NOR3C - port map(A => un4_scantestbp_1, B => un5_scantestbp_7_0, C - => un4_scantestbp_4, Y => un4_scantestbp_7); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ0 is - - port( raddr1 : in std_logic_vector(7 downto 0); - wdata : in std_logic_vector(31 downto 0); - waddr_0 : in std_logic_vector(7 downto 0); - datain : out std_logic_vector(31 downto 0); - data1 : out std_logic_vector(31 downto 0); - waddr : out std_logic_vector(7 downto 0); - rfa1 : in std_logic_vector(7 downto 0); - ren1 : in std_logic; - wren : in std_logic; - lclk_c : in std_logic; - rfe1 : in std_logic; - write : out std_logic - ); - -end syncram_2pZ0; - -architecture DEF_ARCH of syncram_2pZ0 is - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - port( rclk : in std_logic := 'U'; - rena : in std_logic := 'U'; - raddr : in std_logic_vector(7 downto 0) := (others => 'U'); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic := 'U'; - waddr : in std_logic_vector(7 downto 0) := (others => 'U'); - din : in std_logic_vector(31 downto 0) := (others => 'U'); - write : in std_logic := 'U' - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un4_scantestbp_0, un4_scantestbp_3, un4_scantestbp_2, - un4_scantestbp_7, un4_scantestbp_1, un5_scantestbp_7_i_0, - un4_scantestbp_4, un5_scantestbp_6_i_0, - un5_scantestbp_4_i_0, un5_scantestbp_2_i_0, - un5_scantestbp_0_i_0, un4_scantestbp, \dataoutx[0]\, - \dataoutx[1]\, \dataoutx[3]\, \dataoutx[25]\, - \dataoutx[26]\, \dataoutx[27]\, \dataoutx[28]\, - \dataoutx[29]\, \dataoutx[30]\, \dataoutx[19]\, - \dataoutx[21]\, \dataoutx[22]\, \dataoutx[23]\, - \dataoutx[24]\, \dataoutx[11]\, \dataoutx[12]\, - \dataoutx[13]\, \dataoutx[14]\, \dataoutx[15]\, - \dataoutx[16]\, \dataoutx[17]\, \dataoutx[4]\, - \dataoutx[5]\, \dataoutx[6]\, \dataoutx[7]\, - \dataoutx[8]\, \dataoutx[9]\, \dataoutx[10]\, - \dataoutx[2]\, \dataoutx[20]\, \dataoutx[31]\, - \dataoutx[18]\, \write\, \waddr[0]\, \waddr[1]\, - \waddr[2]\, \waddr[3]\, \waddr[4]\, \waddr[5]\, - \waddr[6]\, \waddr[7]\, \datain[0]\, \datain[1]\, - \datain[2]\, \datain[3]\, \datain[4]\, \datain[5]\, - \datain[6]\, \datain[7]\, \datain[8]\, \datain[9]\, - \datain[10]\, \datain[11]\, \datain[12]\, \datain[13]\, - \datain[14]\, \datain[15]\, \datain[16]\, \datain[17]\, - \datain[18]\, \datain[19]\, \datain[20]\, \datain[21]\, - \datain[22]\, \datain[23]\, \datain[24]\, \datain[25]\, - \datain[26]\, \datain[27]\, \datain[28]\, \datain[29]\, - \datain[30]\, \datain[31]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - Use entity work. - proasic3_syncram_2p_work_leon3mp_wfp_rtl_1(DEF_ARCH); -begin - - datain(31) <= \datain[31]\; - datain(30) <= \datain[30]\; - datain(29) <= \datain[29]\; - datain(28) <= \datain[28]\; - datain(27) <= \datain[27]\; - datain(26) <= \datain[26]\; - datain(25) <= \datain[25]\; - datain(24) <= \datain[24]\; - datain(23) <= \datain[23]\; - datain(22) <= \datain[22]\; - datain(21) <= \datain[21]\; - datain(20) <= \datain[20]\; - datain(19) <= \datain[19]\; - datain(18) <= \datain[18]\; - datain(17) <= \datain[17]\; - datain(16) <= \datain[16]\; - datain(15) <= \datain[15]\; - datain(14) <= \datain[14]\; - datain(13) <= \datain[13]\; - datain(12) <= \datain[12]\; - datain(11) <= \datain[11]\; - datain(10) <= \datain[10]\; - datain(9) <= \datain[9]\; - datain(8) <= \datain[8]\; - datain(7) <= \datain[7]\; - datain(6) <= \datain[6]\; - datain(5) <= \datain[5]\; - datain(4) <= \datain[4]\; - datain(3) <= \datain[3]\; - datain(2) <= \datain[2]\; - datain(1) <= \datain[1]\; - datain(0) <= \datain[0]\; - waddr(7) <= \waddr[7]\; - waddr(6) <= \waddr[6]\; - waddr(5) <= \waddr[5]\; - waddr(4) <= \waddr[4]\; - waddr(3) <= \waddr[3]\; - waddr(2) <= \waddr[2]\; - waddr(1) <= \waddr[1]\; - waddr(0) <= \waddr[0]\; - write <= \write\; - - \wrfst_gen.no_contention_check.r.waddr_RNIEBBH[1]\ : XA1A - port map(A => rfa1(1), B => \waddr[1]\, C => - un5_scantestbp_2_i_0, Y => un4_scantestbp_2); - - \wrfst_gen.no_contention_check.r.datain[23]\ : DFN1 - port map(D => wdata(23), CLK => lclk_c, Q => \datain[23]\); - - \wrfst_gen.no_contention_check.r.waddr_RNI08M8[6]\ : XNOR2 - port map(A => \waddr[6]\, B => rfa1(6), Y => - un5_scantestbp_6_i_0); - - \wrfst_gen.no_contention_check.r.datain[26]\ : DFN1 - port map(D => wdata(26), CLK => lclk_c, Q => \datain[26]\); - - \wrfst_gen.no_contention_check.r.waddr_RNIDAN82[1]\ : NOR3C - port map(A => un4_scantestbp_3, B => un4_scantestbp_2, C - => un4_scantestbp_7, Y => un4_scantestbp); - - \proa3.x0_RNI74FG2\ : MX2 - port map(A => \dataoutx[14]\, B => \datain[14]\, S => - un4_scantestbp, Y => data1(14)); - - \proa3.x0_RNI68FG2\ : MX2 - port map(A => \dataoutx[20]\, B => \datain[20]\, S => - un4_scantestbp, Y => data1(20)); - - \wrfst_gen.no_contention_check.r.datain[4]\ : DFN1 - port map(D => wdata(4), CLK => lclk_c, Q => \datain[4]\); - - \wrfst_gen.no_contention_check.r.datain[27]\ : DFN1 - port map(D => wdata(27), CLK => lclk_c, Q => \datain[27]\); - - \wrfst_gen.no_contention_check.r.write\ : DFN1 - port map(D => wren, CLK => lclk_c, Q => \write\); - - \wrfst_gen.no_contention_check.r.datain[13]\ : DFN1 - port map(D => wdata(13), CLK => lclk_c, Q => \datain[13]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \wrfst_gen.no_contention_check.r.waddr_RNI2CM8[7]\ : XNOR2 - port map(A => \waddr[7]\, B => rfa1(7), Y => - un5_scantestbp_7_i_0); - - \wrfst_gen.no_contention_check.r.datain[16]\ : DFN1 - port map(D => wdata(16), CLK => lclk_c, Q => \datain[16]\); - - \proa3.x0_RNI94FG2\ : MX2 - port map(A => \dataoutx[16]\, B => \datain[16]\, S => - un4_scantestbp, Y => data1(16)); - - \proa3.x0_RNIF8FG2\ : MX2 - port map(A => \dataoutx[29]\, B => \datain[29]\, S => - un4_scantestbp_0, Y => data1(29)); - - \proa3.x0_RNI84FG2\ : MX2 - port map(A => \dataoutx[15]\, B => \datain[15]\, S => - un4_scantestbp, Y => data1(15)); - - \wrfst_gen.no_contention_check.r.waddr[6]\ : DFN1 - port map(D => waddr_0(6), CLK => lclk_c, Q => \waddr[6]\); - - \proa3.x0_RNID8FG2\ : MX2 - port map(A => \dataoutx[27]\, B => \datain[27]\, S => - un4_scantestbp_0, Y => data1(27)); - - \wrfst_gen.no_contention_check.r.datain[8]\ : DFN1 - port map(D => wdata(8), CLK => lclk_c, Q => \datain[8]\); - - \wrfst_gen.no_contention_check.r.datain[25]\ : DFN1 - port map(D => wdata(25), CLK => lclk_c, Q => \datain[25]\); - - \wrfst_gen.no_contention_check.r.waddr[5]\ : DFN1 - port map(D => waddr_0(5), CLK => lclk_c, Q => \waddr[5]\); - - \wrfst_gen.no_contention_check.r.datain[17]\ : DFN1 - port map(D => wdata(17), CLK => lclk_c, Q => \datain[17]\); - - \wrfst_gen.no_contention_check.r.waddr[3]\ : DFN1 - port map(D => waddr_0(3), CLK => lclk_c, Q => \waddr[3]\); - - \wrfst_gen.no_contention_check.r.waddr_RNIONL8[2]\ : XNOR2 - port map(A => \waddr[2]\, B => rfa1(2), Y => - un5_scantestbp_2_i_0); - - \proa3.x0_RNISP2J2\ : MX2 - port map(A => \dataoutx[8]\, B => \datain[8]\, S => - un4_scantestbp, Y => data1(8)); - - \proa3.x0_RNIA8FG2\ : MX2 - port map(A => \dataoutx[24]\, B => \datain[24]\, S => - un4_scantestbp_0, Y => data1(24)); - - \wrfst_gen.no_contention_check.r.waddr_RNIUBCH[5]\ : XA1A - port map(A => rfa1(5), B => \waddr[5]\, C => - un5_scantestbp_6_i_0, Y => un4_scantestbp_4); - - \wrfst_gen.no_contention_check.r.datain[2]\ : DFN1 - port map(D => wdata(2), CLK => lclk_c, Q => \datain[2]\); - - \wrfst_gen.no_contention_check.r.datain[22]\ : DFN1 - port map(D => wdata(22), CLK => lclk_c, Q => \datain[22]\); - - \wrfst_gen.no_contention_check.r.waddr[4]\ : DFN1 - port map(D => waddr_0(4), CLK => lclk_c, Q => \waddr[4]\); - - \wrfst_gen.no_contention_check.r.datain[31]\ : DFN1 - port map(D => wdata(31), CLK => lclk_c, Q => \datain[31]\); - - \wrfst_gen.no_contention_check.r.datain[30]\ : DFN1 - port map(D => wdata(30), CLK => lclk_c, Q => \datain[30]\); - - \wrfst_gen.no_contention_check.r.datain[7]\ : DFN1 - port map(D => wdata(7), CLK => lclk_c, Q => \datain[7]\); - - \proa3.x0_RNI64FG2\ : MX2 - port map(A => \dataoutx[13]\, B => \datain[13]\, S => - un4_scantestbp, Y => data1(13)); - - \wrfst_gen.no_contention_check.r.waddr[2]\ : DFN1 - port map(D => waddr_0(2), CLK => lclk_c, Q => \waddr[2]\); - - \wrfst_gen.no_contention_check.r.datain[24]\ : DFN1 - port map(D => wdata(24), CLK => lclk_c, Q => \datain[24]\); - - \wrfst_gen.no_contention_check.r.datain[28]\ : DFN1 - port map(D => wdata(28), CLK => lclk_c, Q => \datain[28]\); - - \wrfst_gen.no_contention_check.r.datain[15]\ : DFN1 - port map(D => wdata(15), CLK => lclk_c, Q => \datain[15]\); - - \wrfst_gen.no_contention_check.r.waddr_RNIMRBH[3]\ : XA1A - port map(A => rfa1(3), B => \waddr[3]\, C => - un5_scantestbp_4_i_0, Y => un4_scantestbp_3); - - \wrfst_gen.no_contention_check.r.datain[3]\ : DFN1 - port map(D => wdata(3), CLK => lclk_c, Q => \datain[3]\); - - \proa3.x0_RNI9CFG2\ : MX2 - port map(A => \dataoutx[30]\, B => \datain[30]\, S => - un4_scantestbp_0, Y => data1(30)); - - \proa3.x0_RNI44FG2\ : MX2 - port map(A => \dataoutx[11]\, B => \datain[11]\, S => - un4_scantestbp_0, Y => data1(11)); - - \proa3.x0_RNIQH2J2\ : MX2 - port map(A => \dataoutx[6]\, B => \datain[6]\, S => - un4_scantestbp, Y => data1(6)); - - \proa3.x0_RNIRL2J2\ : MX2 - port map(A => \dataoutx[7]\, B => \datain[7]\, S => - un4_scantestbp, Y => data1(7)); - - GND_i : GND - port map(Y => \GND\); - - \wrfst_gen.no_contention_check.r.datain[12]\ : DFN1 - port map(D => wdata(12), CLK => lclk_c, Q => \datain[12]\); - - \proa3.x0_RNIO92J2\ : MX2 - port map(A => \dataoutx[4]\, B => \datain[4]\, S => - un4_scantestbp, Y => data1(4)); - - \wrfst_gen.no_contention_check.r.write_RNI93061\ : NOR3C - port map(A => un4_scantestbp_1, B => un5_scantestbp_7_i_0, - C => un4_scantestbp_4, Y => un4_scantestbp_7); - - \wrfst_gen.no_contention_check.r.waddr[7]\ : DFN1 - port map(D => waddr_0(7), CLK => lclk_c, Q => \waddr[7]\); - - \wrfst_gen.no_contention_check.r.datain[14]\ : DFN1 - port map(D => wdata(14), CLK => lclk_c, Q => \datain[14]\); - - \proa3.x0_RNIB8FG2\ : MX2 - port map(A => \dataoutx[25]\, B => \datain[25]\, S => - un4_scantestbp_0, Y => data1(25)); - - \wrfst_gen.no_contention_check.r.datain[18]\ : DFN1 - port map(D => wdata(18), CLK => lclk_c, Q => \datain[18]\); - - \wrfst_gen.no_contention_check.r.datain[29]\ : DFN1 - port map(D => wdata(29), CLK => lclk_c, Q => \datain[29]\); - - \proa3.x0_RNILT1J2\ : MX2 - port map(A => \dataoutx[1]\, B => \datain[1]\, S => - un4_scantestbp_0, Y => data1(1)); - - \proa3.x0_RNIA4FG2\ : MX2 - port map(A => \dataoutx[17]\, B => \datain[17]\, S => - un4_scantestbp, Y => data1(17)); - - \proa3.x0_RNIM12J2\ : MX2 - port map(A => \dataoutx[2]\, B => \datain[2]\, S => - un4_scantestbp, Y => data1(2)); - - \proa3.x0\ : proasic3_syncram_2p_work_leon3mp_wfp_rtl_1 - port map(rclk => lclk_c, rena => ren1, raddr(7) => - raddr1(7), raddr(6) => raddr1(6), raddr(5) => raddr1(5), - raddr(4) => raddr1(4), raddr(3) => raddr1(3), raddr(2) - => raddr1(2), raddr(1) => raddr1(1), raddr(0) => - raddr1(0), dout(31) => \dataoutx[31]\, dout(30) => - \dataoutx[30]\, dout(29) => \dataoutx[29]\, dout(28) => - \dataoutx[28]\, dout(27) => \dataoutx[27]\, dout(26) => - \dataoutx[26]\, dout(25) => \dataoutx[25]\, dout(24) => - \dataoutx[24]\, dout(23) => \dataoutx[23]\, dout(22) => - \dataoutx[22]\, dout(21) => \dataoutx[21]\, dout(20) => - \dataoutx[20]\, dout(19) => \dataoutx[19]\, dout(18) => - \dataoutx[18]\, dout(17) => \dataoutx[17]\, dout(16) => - \dataoutx[16]\, dout(15) => \dataoutx[15]\, dout(14) => - \dataoutx[14]\, dout(13) => \dataoutx[13]\, dout(12) => - \dataoutx[12]\, dout(11) => \dataoutx[11]\, dout(10) => - \dataoutx[10]\, dout(9) => \dataoutx[9]\, dout(8) => - \dataoutx[8]\, dout(7) => \dataoutx[7]\, dout(6) => - \dataoutx[6]\, dout(5) => \dataoutx[5]\, dout(4) => - \dataoutx[4]\, dout(3) => \dataoutx[3]\, dout(2) => - \dataoutx[2]\, dout(1) => \dataoutx[1]\, dout(0) => - \dataoutx[0]\, wclk => lclk_c, waddr(7) => waddr_0(7), - waddr(6) => waddr_0(6), waddr(5) => waddr_0(5), waddr(4) - => waddr_0(4), waddr(3) => waddr_0(3), waddr(2) => - waddr_0(2), waddr(1) => waddr_0(1), waddr(0) => - waddr_0(0), din(31) => wdata(31), din(30) => wdata(30), - din(29) => wdata(29), din(28) => wdata(28), din(27) => - wdata(27), din(26) => wdata(26), din(25) => wdata(25), - din(24) => wdata(24), din(23) => wdata(23), din(22) => - wdata(22), din(21) => wdata(21), din(20) => wdata(20), - din(19) => wdata(19), din(18) => wdata(18), din(17) => - wdata(17), din(16) => wdata(16), din(15) => wdata(15), - din(14) => wdata(14), din(13) => wdata(13), din(12) => - wdata(12), din(11) => wdata(11), din(10) => wdata(10), - din(9) => wdata(9), din(8) => wdata(8), din(7) => - wdata(7), din(6) => wdata(6), din(5) => wdata(5), din(4) - => wdata(4), din(3) => wdata(3), din(2) => wdata(2), - din(1) => wdata(1), din(0) => wdata(0), write => wren); - - \wrfst_gen.no_contention_check.r.waddr_RNIDAN82_0[1]\ : NOR3C - port map(A => un4_scantestbp_3, B => un4_scantestbp_2, C - => un4_scantestbp_7, Y => un4_scantestbp_0); - - \wrfst_gen.no_contention_check.r.datain[5]\ : DFN1 - port map(D => wdata(5), CLK => lclk_c, Q => \datain[5]\); - - \proa3.x0_RNIC8FG2\ : MX2 - port map(A => \dataoutx[26]\, B => \datain[26]\, S => - un4_scantestbp_0, Y => data1(26)); - - \proa3.x0_RNIN52J2\ : MX2 - port map(A => \dataoutx[3]\, B => \datain[3]\, S => - un4_scantestbp_0, Y => data1(3)); - - \wrfst_gen.no_contention_check.r.datain[21]\ : DFN1 - port map(D => wdata(21), CLK => lclk_c, Q => \datain[21]\); - - \wrfst_gen.no_contention_check.r.datain[20]\ : DFN1 - port map(D => wdata(20), CLK => lclk_c, Q => \datain[20]\); - - \wrfst_gen.no_contention_check.r.datain[0]\ : DFN1 - port map(D => wdata(0), CLK => lclk_c, Q => \datain[0]\); - - \proa3.x0_RNITT2J2\ : MX2 - port map(A => \dataoutx[9]\, B => \datain[9]\, S => - un4_scantestbp, Y => data1(9)); - - \wrfst_gen.no_contention_check.r.datain[19]\ : DFN1 - port map(D => wdata(19), CLK => lclk_c, Q => \datain[19]\); - - \proa3.x0_RNIPD2J2\ : MX2C - port map(A => \dataoutx[5]\, B => \datain[5]\, S => - un4_scantestbp, Y => data1(5)); - - \wrfst_gen.no_contention_check.r.datain[6]\ : DFN1 - port map(D => wdata(6), CLK => lclk_c, Q => \datain[6]\); - - \proa3.x0_RNI78FG2\ : MX2 - port map(A => \dataoutx[21]\, B => \datain[21]\, S => - un4_scantestbp_0, Y => data1(21)); - - \proa3.x0_RNIKP1J2\ : MX2 - port map(A => \dataoutx[0]\, B => \datain[0]\, S => - un4_scantestbp_0, Y => data1(0)); - - \wrfst_gen.no_contention_check.r.waddr_RNISVL8[4]\ : XNOR2 - port map(A => \waddr[4]\, B => rfa1(4), Y => - un5_scantestbp_4_i_0); - - \wrfst_gen.no_contention_check.r.waddr[0]\ : DFN1 - port map(D => waddr_0(0), CLK => lclk_c, Q => \waddr[0]\); - - \wrfst_gen.no_contention_check.r.waddr[1]\ : DFN1 - port map(D => waddr_0(1), CLK => lclk_c, Q => \waddr[1]\); - - \proa3.x0_RNIB4FG2\ : MX2 - port map(A => \dataoutx[18]\, B => \datain[18]\, S => - un4_scantestbp, Y => data1(18)); - - \wrfst_gen.no_contention_check.r.datain[11]\ : DFN1 - port map(D => wdata(11), CLK => lclk_c, Q => \datain[11]\); - - \wrfst_gen.no_contention_check.r.datain[10]\ : DFN1 - port map(D => wdata(10), CLK => lclk_c, Q => \datain[10]\); - - \proa3.x0_RNIE8FG2\ : MX2 - port map(A => \dataoutx[28]\, B => \datain[28]\, S => - un4_scantestbp_0, Y => data1(28)); - - \proa3.x0_RNIACFG2\ : MX2 - port map(A => \dataoutx[31]\, B => \datain[31]\, S => - un4_scantestbp, Y => data1(31)); - - \proa3.x0_RNI54FG2\ : MX2 - port map(A => \dataoutx[12]\, B => \datain[12]\, S => - un4_scantestbp_0, Y => data1(12)); - - \wrfst_gen.no_contention_check.r.datain[9]\ : DFN1 - port map(D => wdata(9), CLK => lclk_c, Q => \datain[9]\); - - \wrfst_gen.no_contention_check.r.write_RNI9BTB\ : NOR3C - port map(A => \write\, B => rfe1, C => un5_scantestbp_0_i_0, - Y => un4_scantestbp_1); - - \wrfst_gen.no_contention_check.r.waddr_RNIKFL8[0]\ : XNOR2 - port map(A => \waddr[0]\, B => rfa1(0), Y => - un5_scantestbp_0_i_0); - - \proa3.x0_RNI98FG2\ : MX2 - port map(A => \dataoutx[23]\, B => \datain[23]\, S => - un4_scantestbp_0, Y => data1(23)); - - \wrfst_gen.no_contention_check.r.datain[1]\ : DFN1 - port map(D => wdata(1), CLK => lclk_c, Q => \datain[1]\); - - \proa3.x0_RNIC4FG2\ : MX2 - port map(A => \dataoutx[19]\, B => \datain[19]\, S => - un4_scantestbp_0, Y => data1(19)); - - \proa3.x0_RNI88FG2\ : MX2 - port map(A => \dataoutx[22]\, B => \datain[22]\, S => - un4_scantestbp_0, Y => data1(22)); - - \proa3.x0_RNI34FG2\ : MX2 - port map(A => \dataoutx[10]\, B => \datain[10]\, S => - un4_scantestbp, Y => data1(10)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity regfile_3p is - - port( rfa2 : in std_logic_vector(7 downto 0); - data2 : out std_logic_vector(31 downto 0); - raddr2 : in std_logic_vector(7 downto 0); - rfa1 : in std_logic_vector(7 downto 0); - data1 : out std_logic_vector(31 downto 0); - waddr : in std_logic_vector(7 downto 0); - wdata : in std_logic_vector(31 downto 0); - raddr1 : in std_logic_vector(7 downto 0); - rfe2 : in std_logic; - ren2 : in std_logic; - rfe1 : in std_logic; - lclk_c : in std_logic; - wren : in std_logic; - ren1 : in std_logic - ); - -end regfile_3p; - -architecture DEF_ARCH of regfile_3p is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component syncram_2pZ0_1 - port( wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - waddr_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - raddr2 : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(31 downto 0) := (others => 'U'); - data2 : out std_logic_vector(31 downto 0); - waddr : in std_logic_vector(7 downto 0) := (others => 'U'); - rfa2 : in std_logic_vector(7 downto 0) := (others => 'U'); - wren : in std_logic := 'U'; - ren2 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - rfe2 : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component syncram_2pZ0 - port( raddr1 : in std_logic_vector(7 downto 0) := (others => 'U'); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - waddr_0 : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : out std_logic_vector(31 downto 0); - data1 : out std_logic_vector(31 downto 0); - waddr : out std_logic_vector(7 downto 0); - rfa1 : in std_logic_vector(7 downto 0) := (others => 'U'); - ren1 : in std_logic := 'U'; - wren : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - rfe1 : in std_logic := 'U'; - write : out std_logic - ); - end component; - - signal \datain[0]\, \datain[1]\, \datain[2]\, \datain[3]\, - \datain[4]\, \datain[5]\, \datain[6]\, \datain[7]\, - \datain[8]\, \datain[9]\, \datain[10]\, \datain[11]\, - \datain[12]\, \datain[13]\, \datain[14]\, \datain[15]\, - \datain[16]\, \datain[17]\, \datain[18]\, \datain[19]\, - \datain[20]\, \datain[21]\, \datain[22]\, \datain[23]\, - \datain[24]\, \datain[25]\, \datain[26]\, \datain[27]\, - \datain[28]\, \datain[29]\, \datain[30]\, \datain[31]\, - \waddr_0[0]\, \waddr_0[1]\, \waddr_0[2]\, \waddr_0[3]\, - \waddr_0[4]\, \waddr_0[5]\, \waddr_0[6]\, \waddr_0[7]\, - write, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : syncram_2pZ0_1 - Use entity work.syncram_2pZ0_1(DEF_ARCH); - for all : syncram_2pZ0 - Use entity work.syncram_2pZ0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \s1.dp.x1\ : syncram_2pZ0_1 - port map(wdata(31) => wdata(31), wdata(30) => wdata(30), - wdata(29) => wdata(29), wdata(28) => wdata(28), wdata(27) - => wdata(27), wdata(26) => wdata(26), wdata(25) => - wdata(25), wdata(24) => wdata(24), wdata(23) => wdata(23), - wdata(22) => wdata(22), wdata(21) => wdata(21), wdata(20) - => wdata(20), wdata(19) => wdata(19), wdata(18) => - wdata(18), wdata(17) => wdata(17), wdata(16) => wdata(16), - wdata(15) => wdata(15), wdata(14) => wdata(14), wdata(13) - => wdata(13), wdata(12) => wdata(12), wdata(11) => - wdata(11), wdata(10) => wdata(10), wdata(9) => wdata(9), - wdata(8) => wdata(8), wdata(7) => wdata(7), wdata(6) => - wdata(6), wdata(5) => wdata(5), wdata(4) => wdata(4), - wdata(3) => wdata(3), wdata(2) => wdata(2), wdata(1) => - wdata(1), wdata(0) => wdata(0), waddr_0(7) => waddr(7), - waddr_0(6) => waddr(6), waddr_0(5) => waddr(5), - waddr_0(4) => waddr(4), waddr_0(3) => waddr(3), - waddr_0(2) => waddr(2), waddr_0(1) => waddr(1), - waddr_0(0) => waddr(0), raddr2(7) => raddr2(7), raddr2(6) - => raddr2(6), raddr2(5) => raddr2(5), raddr2(4) => - raddr2(4), raddr2(3) => raddr2(3), raddr2(2) => raddr2(2), - raddr2(1) => raddr2(1), raddr2(0) => raddr2(0), - datain(31) => \datain[31]\, datain(30) => \datain[30]\, - datain(29) => \datain[29]\, datain(28) => \datain[28]\, - datain(27) => \datain[27]\, datain(26) => \datain[26]\, - datain(25) => \datain[25]\, datain(24) => \datain[24]\, - datain(23) => \datain[23]\, datain(22) => \datain[22]\, - datain(21) => \datain[21]\, datain(20) => \datain[20]\, - datain(19) => \datain[19]\, datain(18) => \datain[18]\, - datain(17) => \datain[17]\, datain(16) => \datain[16]\, - datain(15) => \datain[15]\, datain(14) => \datain[14]\, - datain(13) => \datain[13]\, datain(12) => \datain[12]\, - datain(11) => \datain[11]\, datain(10) => \datain[10]\, - datain(9) => \datain[9]\, datain(8) => \datain[8]\, - datain(7) => \datain[7]\, datain(6) => \datain[6]\, - datain(5) => \datain[5]\, datain(4) => \datain[4]\, - datain(3) => \datain[3]\, datain(2) => \datain[2]\, - datain(1) => \datain[1]\, datain(0) => \datain[0]\, - data2(31) => data2(31), data2(30) => data2(30), data2(29) - => data2(29), data2(28) => data2(28), data2(27) => - data2(27), data2(26) => data2(26), data2(25) => data2(25), - data2(24) => data2(24), data2(23) => data2(23), data2(22) - => data2(22), data2(21) => data2(21), data2(20) => - data2(20), data2(19) => data2(19), data2(18) => data2(18), - data2(17) => data2(17), data2(16) => data2(16), data2(15) - => data2(15), data2(14) => data2(14), data2(13) => - data2(13), data2(12) => data2(12), data2(11) => data2(11), - data2(10) => data2(10), data2(9) => data2(9), data2(8) - => data2(8), data2(7) => data2(7), data2(6) => data2(6), - data2(5) => data2(5), data2(4) => data2(4), data2(3) => - data2(3), data2(2) => data2(2), data2(1) => data2(1), - data2(0) => data2(0), waddr(7) => \waddr_0[7]\, waddr(6) - => \waddr_0[6]\, waddr(5) => \waddr_0[5]\, waddr(4) => - \waddr_0[4]\, waddr(3) => \waddr_0[3]\, waddr(2) => - \waddr_0[2]\, waddr(1) => \waddr_0[1]\, waddr(0) => - \waddr_0[0]\, rfa2(7) => rfa2(7), rfa2(6) => rfa2(6), - rfa2(5) => rfa2(5), rfa2(4) => rfa2(4), rfa2(3) => - rfa2(3), rfa2(2) => rfa2(2), rfa2(1) => rfa2(1), rfa2(0) - => rfa2(0), wren => wren, ren2 => ren2, lclk_c => lclk_c, - rfe2 => rfe2, write => write); - - VCC_i : VCC - port map(Y => \VCC\); - - \s1.dp.x0\ : syncram_2pZ0 - port map(raddr1(7) => raddr1(7), raddr1(6) => raddr1(6), - raddr1(5) => raddr1(5), raddr1(4) => raddr1(4), raddr1(3) - => raddr1(3), raddr1(2) => raddr1(2), raddr1(1) => - raddr1(1), raddr1(0) => raddr1(0), wdata(31) => wdata(31), - wdata(30) => wdata(30), wdata(29) => wdata(29), wdata(28) - => wdata(28), wdata(27) => wdata(27), wdata(26) => - wdata(26), wdata(25) => wdata(25), wdata(24) => wdata(24), - wdata(23) => wdata(23), wdata(22) => wdata(22), wdata(21) - => wdata(21), wdata(20) => wdata(20), wdata(19) => - wdata(19), wdata(18) => wdata(18), wdata(17) => wdata(17), - wdata(16) => wdata(16), wdata(15) => wdata(15), wdata(14) - => wdata(14), wdata(13) => wdata(13), wdata(12) => - wdata(12), wdata(11) => wdata(11), wdata(10) => wdata(10), - wdata(9) => wdata(9), wdata(8) => wdata(8), wdata(7) => - wdata(7), wdata(6) => wdata(6), wdata(5) => wdata(5), - wdata(4) => wdata(4), wdata(3) => wdata(3), wdata(2) => - wdata(2), wdata(1) => wdata(1), wdata(0) => wdata(0), - waddr_0(7) => waddr(7), waddr_0(6) => waddr(6), - waddr_0(5) => waddr(5), waddr_0(4) => waddr(4), - waddr_0(3) => waddr(3), waddr_0(2) => waddr(2), - waddr_0(1) => waddr(1), waddr_0(0) => waddr(0), - datain(31) => \datain[31]\, datain(30) => \datain[30]\, - datain(29) => \datain[29]\, datain(28) => \datain[28]\, - datain(27) => \datain[27]\, datain(26) => \datain[26]\, - datain(25) => \datain[25]\, datain(24) => \datain[24]\, - datain(23) => \datain[23]\, datain(22) => \datain[22]\, - datain(21) => \datain[21]\, datain(20) => \datain[20]\, - datain(19) => \datain[19]\, datain(18) => \datain[18]\, - datain(17) => \datain[17]\, datain(16) => \datain[16]\, - datain(15) => \datain[15]\, datain(14) => \datain[14]\, - datain(13) => \datain[13]\, datain(12) => \datain[12]\, - datain(11) => \datain[11]\, datain(10) => \datain[10]\, - datain(9) => \datain[9]\, datain(8) => \datain[8]\, - datain(7) => \datain[7]\, datain(6) => \datain[6]\, - datain(5) => \datain[5]\, datain(4) => \datain[4]\, - datain(3) => \datain[3]\, datain(2) => \datain[2]\, - datain(1) => \datain[1]\, datain(0) => \datain[0]\, - data1(31) => data1(31), data1(30) => data1(30), data1(29) - => data1(29), data1(28) => data1(28), data1(27) => - data1(27), data1(26) => data1(26), data1(25) => data1(25), - data1(24) => data1(24), data1(23) => data1(23), data1(22) - => data1(22), data1(21) => data1(21), data1(20) => - data1(20), data1(19) => data1(19), data1(18) => data1(18), - data1(17) => data1(17), data1(16) => data1(16), data1(15) - => data1(15), data1(14) => data1(14), data1(13) => - data1(13), data1(12) => data1(12), data1(11) => data1(11), - data1(10) => data1(10), data1(9) => data1(9), data1(8) - => data1(8), data1(7) => data1(7), data1(6) => data1(6), - data1(5) => data1(5), data1(4) => data1(4), data1(3) => - data1(3), data1(2) => data1(2), data1(1) => data1(1), - data1(0) => data1(0), waddr(7) => \waddr_0[7]\, waddr(6) - => \waddr_0[6]\, waddr(5) => \waddr_0[5]\, waddr(4) => - \waddr_0[4]\, waddr(3) => \waddr_0[3]\, waddr(2) => - \waddr_0[2]\, waddr(1) => \waddr_0[1]\, waddr(0) => - \waddr_0[0]\, rfa1(7) => rfa1(7), rfa1(6) => rfa1(6), - rfa1(5) => rfa1(5), rfa1(4) => rfa1(4), rfa1(3) => - rfa1(3), rfa1(2) => rfa1(2), rfa1(1) => rfa1(1), rfa1(0) - => rfa1(0), ren1 => ren1, wren => wren, lclk_c => lclk_c, - rfe1 => rfe1, write => write); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity leon3s is - - port( irl_0 : in std_logic_vector(3 downto 0); - irl : out std_logic_vector(3 downto 0); - hrdata_1_0_1 : in std_logic_vector(1 to 1); - data_0_21 : out std_logic; - data_0_16 : out std_logic; - data_0_5 : out std_logic; - data_0_2 : out std_logic; - data_0_0 : out std_logic; - nbo_5_0 : out std_logic_vector(1 downto 0); - htrans : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - htrans_tz : out std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 2); - hwdata_16 : out std_logic; - hwdata_3 : out std_logic; - hwdata_9 : out std_logic; - hwdata_11 : out std_logic; - hwdata_25 : out std_logic; - hwdata_27 : out std_logic; - hwdata_13 : out std_logic; - hwdata_4 : out std_logic; - hwdata_12 : out std_logic; - hwdata_23 : out std_logic; - hwdata_28 : out std_logic; - hwdata_1 : out std_logic; - hwdata_14 : out std_logic; - hwdata_0 : out std_logic; - hwdata_15 : out std_logic; - iosn_1 : in std_logic_vector(93 to 93); - hsize_5 : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(0 to 0); - hresp : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - address : out std_logic_vector(1 downto 0); - size : out std_logic_vector(0 to 0); - data_0_d0 : out std_logic; - data_5 : out std_logic; - data_3 : out std_logic; - data_8 : out std_logic; - data_19 : out std_logic; - data_24 : out std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_0 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_9 : in std_logic; - hrdata_10 : in std_logic; - hrdata_11 : in std_logic; - hrdata_13 : in std_logic; - hrdata_14 : in std_logic; - hrdata_17 : in std_logic; - hrdata_24 : in std_logic; - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_8 : in std_logic; - hrdata_12 : in std_logic; - hrdata_15 : in std_logic; - hrdata_16 : in std_logic; - hrdata_18 : in std_logic; - hrdata_21 : in std_logic; - hrdata_22 : in std_logic; - hrdata_23 : in std_logic; - hrdata_26 : in std_logic; - hrdata_27 : in std_logic; - hrdata_2 : in std_logic; - hrdata_3 : in std_logic; - hrdata_4 : in std_logic; - hrdata_7 : in std_logic; - hrdata_5 : in std_logic; - hrdata_6 : in std_logic; - hrdata_28 : in std_logic; - hrdata_29 : in std_logic; - hrdata_30 : in std_logic; - hrdata_31 : in std_logic; - error_i_2 : out std_logic; - intack : out std_logic; - N_546 : in std_logic; - leon3s_VCC : in std_logic; - N_264 : in std_logic; - N_262 : in std_logic; - N_78 : in std_logic; - bo_5842_d_0 : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - hlock : out std_logic; - N_5054 : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - hbusreq : out std_logic; - un60_nbo : out std_logic; - N_457 : out std_logic; - N_462 : out std_logic; - N_467 : out std_logic; - werr_2_m_0 : out std_logic; - un91_nbo_i_0 : out std_logic; - N_138 : out std_logic; - N_139 : out std_logic; - bo_5842_d : out std_logic; - N_458 : out std_logic; - N_459 : out std_logic; - N_461 : out std_logic; - N_463 : out std_logic; - N_468 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_466 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - un59_nbo : out std_logic; - N_78_0 : in std_logic; - N_262_0 : in std_logic; - N_264_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end leon3s; - -architecture DEF_ARCH of leon3s is - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component cachemem - port( xaddress_RNIFP43F : in std_logic_vector(2 to 2) := (others => 'U'); - xaddress_RNITFTTE : in std_logic_vector(3 to 3) := (others => 'U'); - dstate_RNIC3QA81 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIFPT581 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNIFS6E51 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNI1Q9ST1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIEHIUT1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNILHOK61 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNILK99L1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNI1I3MQ1 : in std_logic_vector(0 to 0) := (others => 'U'); - xaddress_RNIK99NK1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIP2BVK1 : in std_logic_vector(1 to 1) := (others => 'U'); - xaddress_RNIJI2O22 : in std_logic_vector(1 to 1) := (others => 'U'); - dstate_RNI1G47MJ : in std_logic_vector(1 to 1) := (others => 'U'); - edata2_iv_i_0 : in std_logic_vector(31 to 31) := (others => 'U'); - addr : in std_logic_vector(30 to 30) := (others => 'U'); - maddress : in std_logic_vector(28 to 28) := (others => 'U'); - newtag_1_0 : in std_logic_vector(27 downto 24) := (others => 'U'); - faddr_RNI7879K : in std_logic_vector(0 to 0) := (others => 'U'); - faddr_RNIEHR0O : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNIB0UOO : in std_logic_vector(2 to 2) := (others => 'U'); - xaddress_RNID252J1 : in std_logic_vector(10 to 10) := (others => 'U'); - faddr_RNI7MK691 : in std_logic_vector(6 to 6) := (others => 'U'); - dstate_i_0_RNIL7FGFS : in std_logic_vector(8 to 8) := (others => 'U'); - dstate_i_0_RNIH0PPES : in std_logic_vector(8 to 8) := (others => 'U'); - dstate_i_RNI29QQ7J3 : in std_logic_vector(8 to 8) := (others => 'U'); - xaddress_RNITMH17S2 : in std_logic_vector(12 to 12) := (others => 'U'); - xaddress_RNICFI17S2 : in std_logic_vector(13 to 13) := (others => 'U'); - xaddress_RNIN7J17S2 : in std_logic_vector(14 to 14) := (others => 'U'); - xaddress_RNI2MB27S2 : in std_logic_vector(15 to 15) := (others => 'U'); - xaddress_RNIID927S2 : in std_logic_vector(16 to 16) := (others => 'U'); - xaddress_RNI0GI17S2 : in std_logic_vector(17 to 17) := (others => 'U'); - xaddress_RNI1D927S2 : in std_logic_vector(20 to 20) := (others => 'U'); - xaddress_RNIC5A27S2 : in std_logic_vector(21 to 21) := (others => 'U'); - xaddress_RNI9MB27S2 : in std_logic_vector(23 to 23) := (others => 'U'); - dataout : out std_logic_vector(35 downto 0); - vaddress_RNI8EVQ36 : in std_logic_vector(2 to 2) := (others => 'U'); - vaddress_RNIFCB8U6 : in std_logic_vector(3 to 3) := (others => 'U'); - vaddress_RNIJG6QR7 : in std_logic_vector(4 to 4) := (others => 'U'); - istate_RNIUCOFG : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIPSU8G : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6HPAI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI57KLB : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIG7IIA : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIEC82C : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI7BUID : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIV33V9 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIMRTH8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIGUTA8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6LOO6 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIKJBN8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIN6957 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI6PSS1 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIOVC5J : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIA8N5H : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIK9NF8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNILTAC8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI8BL1A : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI2MM6D : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIVTQIJ : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIAJH4F : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIM2DE7 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNI5V68H : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIH0NBI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIAP6PI : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIOJJE1 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIR2JU8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIJSOBE : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIRASC8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIS4VK8 : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIENB3M : in std_logic_vector(0 to 0) := (others => 'U'); - istate_RNIJCMP6 : in std_logic_vector(0 to 0) := (others => 'U'); - faddr_RNI7H6KT8 : in std_logic_vector(0 to 0) := (others => 'U'); - faddr_RNIKVTLT9 : in std_logic_vector(1 to 1) := (others => 'U'); - faddr_RNISJSHQA : in std_logic_vector(2 to 2) := (others => 'U'); - faddr_RNIUT72LB : in std_logic_vector(3 to 3) := (others => 'U'); - faddr_RNI0FOJNE : in std_logic_vector(4 to 4) := (others => 'U'); - faddr_RNI7UFASD : in std_logic_vector(5 to 5) := (others => 'U'); - faddr_RNIDN2CUE : in std_logic_vector(6 to 6) := (others => 'U'); - un1_p0_2_i_0 : in std_logic := 'U'; - un1_p0_2_i_4 : in std_logic := 'U'; - vaddress_RNIOFAKMI : in std_logic_vector(12 to 12) := (others => 'U'); - vaddress_RNIQFAKMI : in std_logic_vector(13 to 13) := (others => 'U'); - vaddress_RNISFAKMI : in std_logic_vector(14 to 14) := (others => 'U'); - vaddress_RNIUFAKMI : in std_logic_vector(15 to 15) := (others => 'U'); - vaddress_RNI0GAKMI : in std_logic_vector(16 to 16) := (others => 'U'); - vaddress_RNI2GAKMI : in std_logic_vector(17 to 17) := (others => 'U'); - vaddress_RNI4GAKMI : in std_logic_vector(18 to 18) := (others => 'U'); - vaddress_RNI6GAKMI : in std_logic_vector(19 to 19) := (others => 'U'); - vaddress_RNIQNAKMI : in std_logic_vector(20 to 20) := (others => 'U'); - vaddress_RNISNAKMI : in std_logic_vector(21 to 21) := (others => 'U'); - vaddress_RNIUNAKMI : in std_logic_vector(22 to 22) := (others => 'U'); - vaddress_RNI0OAKMI : in std_logic_vector(23 to 23) := (others => 'U'); - ctx : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout_2 : out std_logic_vector(31 downto 0); - dataout_1 : out std_logic_vector(31 downto 0); - dataout_0 : out std_logic_vector(35 downto 0); - vitdatain_0_1_0 : out std_logic_vector(22 to 22); - un1_p0_2_0_0 : in std_logic := 'U'; - un1_p0_2_0_350 : in std_logic := 'U'; - dci_m_6 : in std_logic := 'U'; - dci_m_0 : in std_logic := 'U'; - dci_m_1 : in std_logic := 'U'; - dci_m_2 : in std_logic := 'U'; - dci_m_3 : in std_logic := 'U'; - dci_m_5 : in std_logic := 'U'; - N_10 : in std_logic := 'U'; - read_RNI0IQ7R : in std_logic := 'U'; - read_RNIRO4K31 : in std_logic := 'U'; - read_RNIQFOD21 : in std_logic := 'U'; - read_RNIFPFT31 : in std_logic := 'U'; - read_RNIQPCQ11 : in std_logic := 'U'; - read_RNI8DFM31 : in std_logic := 'U'; - read_RNIAQJ831 : in std_logic := 'U'; - read_RNI76N8R : in std_logic := 'U'; - read_RNI7G7G41 : in std_logic := 'U'; - read_RNIEKS231 : in std_logic := 'U'; - read_RNIMJHQT : in std_logic := 'U'; - read_RNIL633F1 : in std_logic := 'U'; - read_RNIQH64D1 : in std_logic := 'U'; - read_RNICAQK41 : in std_logic := 'U'; - read_RNIQMJI41 : in std_logic := 'U'; - read_RNISLPNU : in std_logic := 'U'; - read_RNICKHE91 : in std_logic := 'U'; - read_RNIC70OF1 : in std_logic := 'U'; - read_RNIC9O9B1 : in std_logic := 'U'; - read_RNI75LJ31 : in std_logic := 'U'; - read_RNIEEGDD1 : in std_logic := 'U'; - N_3254_0 : in std_logic := 'U'; - N_330 : in std_logic := 'U'; - N_267 : in std_logic := 'U'; - N_329 : in std_logic := 'U'; - N_144 : in std_logic := 'U'; - N_3846 : in std_logic := 'U'; - N_270 : in std_logic := 'U'; - N_269 : in std_logic := 'U'; - N_24 : in std_logic := 'U'; - N_26 : in std_logic := 'U'; - N_12_i_0 : in std_logic := 'U'; - flush_RNIJEN4SI3 : in std_logic := 'U'; - flush_RNIGUM2OH3 : in std_logic := 'U'; - N_16_i_0 : in std_logic := 'U'; - N_3239_i_0 : in std_logic := 'U'; - flush_0_1_RNIBUA27S2 : in std_logic := 'U'; - flush_0_1_RNIOMB27S2 : in std_logic := 'U'; - flush_0_1_RNIPTA27S2 : in std_logic := 'U'; - flush_RNIGBB873 : in std_logic := 'U'; - N_980 : in std_logic := 'U'; - N_981 : in std_logic := 'U'; - N_983 : in std_logic := 'U'; - N_982 : in std_logic := 'U'; - N_985 : in std_logic := 'U'; - N_986 : in std_logic := 'U'; - flush2 : in std_logic := 'U'; - N_987 : in std_logic := 'U'; - N_984 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - flush2_0_0_RNIPJ5O2 : in std_logic := 'U'; - flush2_0_0_RNITR5O2 : in std_logic := 'U'; - flush2_0_0_RNIVV5O2 : in std_logic := 'U'; - flush2_0_0_RNI146O2 : in std_logic := 'U'; - flush2_RNIFMGM2 : in std_logic := 'U'; - flush2_0_0_RNI7G6O2 : in std_logic := 'U'; - cachemem_VCC : in std_logic := 'U'; - flush2_RNI5I3N7 : in std_logic := 'U'; - un1_ici : in std_logic := 'U'; - N_258 : in std_logic := 'U'; - N_259 : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component proc3 - port( istate_RNIJCMP6 : out std_logic_vector(0 to 0); - faddr_RNIUT72LB : out std_logic_vector(3 to 3); - vaddress_RNISNAKMI : out std_logic_vector(21 to 21); - vaddress_RNI6GAKMI : out std_logic_vector(19 to 19); - faddr_RNISJSHQA : out std_logic_vector(2 to 2); - vaddress_RNIQNAKMI : out std_logic_vector(20 to 20); - faddr_RNI7UFASD : out std_logic_vector(5 to 5); - faddr_RNI0FOJNE : out std_logic_vector(4 to 4); - faddr_RNIDN2CUE : out std_logic_vector(6 to 6); - faddr_RNIKVTLT9 : out std_logic_vector(1 to 1); - vaddress_RNI0GAKMI : out std_logic_vector(16 to 16); - vaddress_RNI0OAKMI : out std_logic_vector(23 to 23); - vaddress_RNIOFAKMI : out std_logic_vector(12 to 12); - vaddress_RNIJG6QR7 : out std_logic_vector(4 to 4); - un1_p0_2_i_4 : out std_logic; - un1_p0_2_i_0 : out std_logic; - ctx : out std_logic_vector(7 downto 0); - istate_RNI6HPAI : out std_logic_vector(0 to 0); - istate_RNIAJH4F : out std_logic_vector(0 to 0); - vaddress_RNIUNAKMI : out std_logic_vector(22 to 22); - vaddress_RNISFAKMI : out std_logic_vector(14 to 14); - istate_RNI57KLB : out std_logic_vector(0 to 0); - istate_RNIUCOFG : out std_logic_vector(0 to 0); - faddr_RNI7H6KT8 : out std_logic_vector(0 to 0); - istate_RNIH0NBI : out std_logic_vector(0 to 0); - istate_RNIG7IIA : out std_logic_vector(0 to 0); - vaddress_RNIFCB8U6 : out std_logic_vector(3 to 3); - istate_RNI2MM6D : out std_logic_vector(0 to 0); - istate_RNI8BL1A : out std_logic_vector(0 to 0); - istate_RNILTAC8 : out std_logic_vector(0 to 0); - istate_RNIK9NF8 : out std_logic_vector(0 to 0); - vaddress_RNI4GAKMI : out std_logic_vector(18 to 18); - vaddress_RNI2GAKMI : out std_logic_vector(17 to 17); - istate_RNI5V68H : out std_logic_vector(0 to 0); - istate_RNIM2DE7 : out std_logic_vector(0 to 0); - istate_RNIVTQIJ : out std_logic_vector(0 to 0); - istate_RNIOVC5J : out std_logic_vector(0 to 0); - istate_RNI6PSS1 : out std_logic_vector(0 to 0); - istate_RNIGUTA8 : out std_logic_vector(0 to 0); - istate_RNIMRTH8 : out std_logic_vector(0 to 0); - vaddress_RNIQFAKMI : out std_logic_vector(13 to 13); - istate_RNIAP6PI : out std_logic_vector(0 to 0); - istate_RNIENB3M : out std_logic_vector(0 to 0); - istate_RNIS4VK8 : out std_logic_vector(0 to 0); - istate_RNIRASC8 : out std_logic_vector(0 to 0); - istate_RNIJSOBE : out std_logic_vector(0 to 0); - istate_RNIR2JU8 : out std_logic_vector(0 to 0); - istate_RNIOJJE1 : out std_logic_vector(0 to 0); - istate_RNIN6957 : out std_logic_vector(0 to 0); - istate_RNIKJBN8 : out std_logic_vector(0 to 0); - istate_RNI6LOO6 : out std_logic_vector(0 to 0); - istate_RNIV33V9 : out std_logic_vector(0 to 0); - istate_RNI7BUID : out std_logic_vector(0 to 0); - istate_RNIEC82C : out std_logic_vector(0 to 0); - istate_RNIPSU8G : out std_logic_vector(0 to 0); - hrdata_31 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - vaddress_RNI8EVQ36 : out std_logic_vector(2 to 2); - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - istate_RNIA8N5H : out std_logic_vector(0 to 0); - vaddress_RNIUFAKMI : out std_logic_vector(15 to 15); - vitdatain_0_1_0 : in std_logic_vector(22 to 22) := (others => 'U'); - dataout_1 : in std_logic_vector(31 downto 0) := (others => 'U'); - dataout_0 : in std_logic_vector(35 downto 0) := (others => 'U'); - dataout_2 : in std_logic_vector(31 downto 0) := (others => 'U'); - un1_p0_2_0_0 : out std_logic; - un1_p0_2_0_350 : out std_logic; - data_1_21 : out std_logic; - data_1_16 : out std_logic; - data_1_5 : out std_logic; - data_1_0 : out std_logic; - data_1_2 : out std_logic; - faddr_RNIB0UOO : out std_logic_vector(2 to 2); - dstate_i_RNI29QQ7J3 : out std_logic_vector(8 to 8); - xaddress_RNITFTTE : out std_logic_vector(3 to 3); - xaddress_RNIFP43F : out std_logic_vector(2 to 2); - size_0 : out std_logic_vector(0 to 0); - faddr_RNI7MK691 : out std_logic_vector(6 to 6); - dci_m_6 : out std_logic; - dci_m_5 : out std_logic; - dci_m_3 : out std_logic; - dci_m_2 : out std_logic; - dci_m_1 : out std_logic; - dci_m_0 : out std_logic; - faddr_RNI7879K : out std_logic_vector(0 to 0); - faddr_RNIEHR0O : out std_logic_vector(1 to 1); - dstate_RNIC3QA81 : out std_logic_vector(1 to 1); - dstate_RNIFPT581 : out std_logic_vector(1 to 1); - dstate_i_0_RNIH0PPES : out std_logic_vector(8 to 8); - dstate_RNI1G47MJ : out std_logic_vector(1 to 1); - dstate_RNIFS6E51 : out std_logic_vector(1 to 1); - xaddress_RNI1Q9ST1 : out std_logic_vector(1 to 1); - xaddress_RNIEHIUT1 : out std_logic_vector(1 to 1); - xaddress_RNILHOK61 : out std_logic_vector(1 to 1); - xaddress_RNILK99L1 : out std_logic_vector(1 to 1); - xaddress_RNI1I3MQ1 : out std_logic_vector(0 to 0); - xaddress_RNIK99NK1 : out std_logic_vector(1 to 1); - xaddress_RNIP2BVK1 : out std_logic_vector(1 to 1); - xaddress_RNIJI2O22 : out std_logic_vector(1 to 1); - xaddress_RNITMH17S2 : out std_logic_vector(12 to 12); - xaddress_RNICFI17S2 : out std_logic_vector(13 to 13); - xaddress_RNI1D927S2 : out std_logic_vector(20 to 20); - xaddress_RNI9MB27S2 : out std_logic_vector(23 to 23); - xaddress_RNI0GI17S2 : out std_logic_vector(17 to 17); - xaddress_RNIC5A27S2 : out std_logic_vector(21 to 21); - xaddress_RNIN7J17S2 : out std_logic_vector(14 to 14); - xaddress_RNIID927S2 : out std_logic_vector(16 to 16); - xaddress_RNI2MB27S2 : out std_logic_vector(15 to 15); - dstate_i_0_RNIL7FGFS : out std_logic_vector(8 to 8); - xaddress_RNID252J1 : out std_logic_vector(10 to 10); - newtag_1_0 : out std_logic_vector(27 downto 24); - dataout : in std_logic_vector(35 downto 0) := (others => 'U'); - address : out std_logic_vector(1 downto 0); - addr : out std_logic_vector(30 to 30); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - hgrant : in std_logic_vector(0 to 0) := (others => 'U'); - hsize_5 : out std_logic_vector(1 to 1); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hwdata_15 : out std_logic; - hwdata_0 : out std_logic; - hwdata_14 : out std_logic; - hwdata_1 : out std_logic; - hwdata_28 : out std_logic; - hwdata_23 : out std_logic; - hwdata_12 : out std_logic; - hwdata_4 : out std_logic; - hwdata_13 : out std_logic; - hwdata_27 : out std_logic; - hwdata_25 : out std_logic; - hwdata_11 : out std_logic; - hwdata_9 : out std_logic; - hwdata_3 : out std_logic; - hwdata_16 : out std_logic; - haddr : out std_logic_vector(31 downto 2); - htrans_tz : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : out std_logic_vector(1 to 1); - nbo_5_0 : out std_logic_vector(1 downto 0); - data_0 : out std_logic; - data_3 : out std_logic; - data_5 : out std_logic; - data_8 : out std_logic; - data_19 : out std_logic; - data_24 : out std_logic; - hrdata_1_0_1 : in std_logic_vector(1 to 1) := (others => 'U'); - data1 : in std_logic_vector(31 downto 0) := (others => 'U'); - maddress_28 : out std_logic; - data2 : in std_logic_vector(31 downto 0) := (others => 'U'); - irl_0 : out std_logic_vector(3 downto 0); - irl : in std_logic_vector(3 downto 0) := (others => 'U'); - edata2_iv_i_0_7 : out std_logic; - raddr1 : out std_logic_vector(7 downto 0); - rfa1 : out std_logic_vector(7 downto 0); - raddr2 : out std_logic_vector(7 downto 0); - rfa2 : out std_logic_vector(7 downto 0); - waddr : out std_logic_vector(7 downto 0); - wdata : out std_logic_vector(31 downto 0); - flush2_RNIFMGM2 : out std_logic; - flush2_RNI5I3N7 : out std_logic; - N_984 : out std_logic; - N_980 : out std_logic; - N_987 : out std_logic; - N_986 : out std_logic; - flush2 : out std_logic; - flush2_0_0_RNI146O2 : out std_logic; - flush2_0_0_RNI7G6O2 : out std_logic; - flush2_0_0_RNIVV5O2 : out std_logic; - flush2_0_0_RNITR5O2 : out std_logic; - flush2_0_0_RNIPJ5O2 : out std_logic; - N_981 : out std_logic; - N_985 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_264_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - un1_ici : out std_logic; - N_10 : out std_logic; - flush_RNIJEN4SI3 : out std_logic; - flush_RNIGBB873 : out std_logic; - N_270 : out std_logic; - N_269 : out std_logic; - N_267 : out std_logic; - N_259 : out std_logic; - N_258 : out std_logic; - N_144 : out std_logic; - N_3846 : out std_logic; - read_RNIQH64D1 : out std_logic; - read_RNIQPCQ11 : out std_logic; - read_RNIRO4K31 : out std_logic; - read_RNI0IQ7R : out std_logic; - read_RNIQFOD21 : out std_logic; - read_RNI8DFM31 : out std_logic; - read_RNIAQJ831 : out std_logic; - read_RNI76N8R : out std_logic; - read_RNI7G7G41 : out std_logic; - read_RNIMJHQT : out std_logic; - read_RNIL633F1 : out std_logic; - read_RNICKHE91 : out std_logic; - flush_0_1_RNIOMB27S2 : out std_logic; - un59_nbo : out std_logic; - N_3239_i_0 : out std_logic; - N_26_0 : out std_logic; - read_RNIEKS231 : out std_logic; - read_RNIFPFT31 : out std_logic; - read_RNIC9O9B1 : out std_logic; - flush_RNIGUM2OH3 : out std_logic; - read_RNICAQK41 : out std_logic; - read_RNIQMJI41 : out std_logic; - read_RNISLPNU : out std_logic; - read_RNIC70OF1 : out std_logic; - read_RNI75LJ31 : out std_logic; - read_RNIEEGDD1 : out std_logic; - N_12_i_0 : out std_logic; - N_16_i_0 : out std_logic; - flush_0_1_RNIBUA27S2 : out std_logic; - flush_0_1_RNIPTA27S2 : out std_logic; - N_24 : out std_logic; - N_329 : out std_logic; - N_330 : out std_logic; - N_3254_0 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - N_466 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_468 : out std_logic; - N_463 : out std_logic; - N_461 : out std_logic; - N_459 : out std_logic; - N_458 : out std_logic; - bo_5842_d : out std_logic; - N_139 : out std_logic; - N_138 : out std_logic; - un91_nbo_i_0 : out std_logic; - werr_2_m_0 : out std_logic; - N_467 : out std_logic; - N_462 : out std_logic; - N_457 : out std_logic; - un60_nbo : out std_logic; - hbusreq : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - N_5054 : out std_logic; - hlock : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - bo_5842_d_0 : out std_logic; - N_78 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - proc3_VCC : in std_logic := 'U'; - N_546 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - ra_bpmiss_1_0 : out std_logic; - rst : in std_logic := 'U'; - d_m5_0_a3_2 : out std_logic; - rst_RNIINI1H : in std_logic := 'U'; - rstate_1188n : in std_logic := 'U'; - ren1 : out std_logic; - rfe1 : out std_logic; - wren : out std_logic; - intack : out std_logic; - ren2 : out std_logic; - rfe2 : out std_logic; - error_i_2 : out std_logic - ); - end component; - - component regfile_3p - port( rfa2 : in std_logic_vector(7 downto 0) := (others => 'U'); - data2 : out std_logic_vector(31 downto 0); - raddr2 : in std_logic_vector(7 downto 0) := (others => 'U'); - rfa1 : in std_logic_vector(7 downto 0) := (others => 'U'); - data1 : out std_logic_vector(31 downto 0); - waddr : in std_logic_vector(7 downto 0) := (others => 'U'); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - raddr1 : in std_logic_vector(7 downto 0) := (others => 'U'); - rfe2 : in std_logic := 'U'; - ren2 : in std_logic := 'U'; - rfe1 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - wren : in std_logic := 'U'; - ren1 : in std_logic := 'U' - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \rst\, rst_0, rstate_1188n, \rst_RNIINI1H\, - d_m5_0_a3_2, ra_bpmiss_1_0, \istate_RNIJCMP6[0]\, - \faddr_RNIUT72LB[3]\, \vaddress_RNISNAKMI[21]\, - \vaddress_RNI6GAKMI[19]\, \faddr_RNISJSHQA[2]\, - \vaddress_RNIQNAKMI[20]\, \faddr_RNI7UFASD[5]\, - \faddr_RNI0FOJNE[4]\, \faddr_RNIDN2CUE[6]\, - \faddr_RNIKVTLT9[1]\, \vaddress_RNI0GAKMI[16]\, - \vaddress_RNI0OAKMI[23]\, \vaddress_RNIOFAKMI[12]\, - \vaddress_RNIJG6QR7[4]\, \un1_p0_2_i[121]\, - \un1_p0_2_i[117]\, \ctx[0]\, \ctx[1]\, \ctx[2]\, \ctx[3]\, - \ctx[4]\, \ctx[5]\, \ctx[6]\, \ctx[7]\, - \istate_RNI6HPAI[0]\, \istate_RNIAJH4F[0]\, - \vaddress_RNIUNAKMI[22]\, \vaddress_RNISFAKMI[14]\, - \istate_RNI57KLB[0]\, \istate_RNIUCOFG[0]\, - \faddr_RNI7H6KT8[0]\, \istate_RNIH0NBI[0]\, - \istate_RNIG7IIA[0]\, \vaddress_RNIFCB8U6[3]\, - \istate_RNI2MM6D[0]\, \istate_RNI8BL1A[0]\, - \istate_RNILTAC8[0]\, \istate_RNIK9NF8[0]\, - \vaddress_RNI4GAKMI[18]\, \vaddress_RNI2GAKMI[17]\, - \istate_RNI5V68H[0]\, \istate_RNIM2DE7[0]\, - \istate_RNIVTQIJ[0]\, \istate_RNIOVC5J[0]\, - \istate_RNI6PSS1[0]\, \istate_RNIGUTA8[0]\, - \istate_RNIMRTH8[0]\, \vaddress_RNIQFAKMI[13]\, - \istate_RNIAP6PI[0]\, \istate_RNIENB3M[0]\, - \istate_RNIS4VK8[0]\, \istate_RNIRASC8[0]\, - \istate_RNIJSOBE[0]\, \istate_RNIR2JU8[0]\, - \istate_RNIOJJE1[0]\, \istate_RNIN6957[0]\, - \istate_RNIKJBN8[0]\, \istate_RNI6LOO6[0]\, - \istate_RNIV33V9[0]\, \istate_RNI7BUID[0]\, - \istate_RNIEC82C[0]\, \istate_RNIPSU8G[0]\, - \vaddress_RNI8EVQ36[2]\, \istate_RNIA8N5H[0]\, - \vaddress_RNIUFAKMI[15]\, \vitdatain_0_1_0[22]\, - \dataout_1[0]\, \dataout_1[1]\, \dataout_1[2]\, - \dataout_1[3]\, \dataout_1[4]\, \dataout_1[5]\, - \dataout_1[6]\, \dataout_1[7]\, \dataout_1[8]\, - \dataout_1[9]\, \dataout_1[10]\, \dataout_1[11]\, - \dataout_1[12]\, \dataout_1[13]\, \dataout_1[14]\, - \dataout_1[15]\, \dataout_1[16]\, \dataout_1[17]\, - \dataout_1[18]\, \dataout_1[19]\, \dataout_1[20]\, - \dataout_1[21]\, \dataout_1[22]\, \dataout_1[23]\, - \dataout_1[24]\, \dataout_1[25]\, \dataout_1[26]\, - \dataout_1[27]\, \dataout_1[28]\, \dataout_1[29]\, - \dataout_1[30]\, \dataout_1[31]\, \dataout_0[0]\, - \dataout_0[1]\, \dataout_0[2]\, \dataout_0[3]\, - \dataout_0[4]\, \dataout_0[5]\, \dataout_0[6]\, - \dataout_0[7]\, \dataout_0[8]\, \dataout_0[9]\, - \dataout_0[10]\, \dataout_0[11]\, \dataout_0[12]\, - \dataout_0[13]\, \dataout_0[14]\, \dataout_0[15]\, - \dataout_0[16]\, \dataout_0[17]\, \dataout_0[18]\, - \dataout_0[19]\, \dataout_0[20]\, \dataout_0[21]\, - \dataout_0[22]\, \dataout_0[23]\, \dataout_0[24]\, - \dataout_0[25]\, \dataout_0[26]\, \dataout_0[27]\, - \dataout_0[28]\, \dataout_0[29]\, \dataout_0[30]\, - \dataout_0[31]\, \dataout_0[32]\, \dataout_0[33]\, - \dataout_0[34]\, \dataout_0[35]\, \dataout_2[0]\, - \dataout_2[1]\, \dataout_2[2]\, \dataout_2[3]\, - \dataout_2[4]\, \dataout_2[5]\, \dataout_2[6]\, - \dataout_2[7]\, \dataout_2[8]\, \dataout_2[9]\, - \dataout_2[10]\, \dataout_2[11]\, \dataout_2[12]\, - \dataout_2[13]\, \dataout_2[14]\, \dataout_2[15]\, - \dataout_2[16]\, \dataout_2[17]\, \dataout_2[18]\, - \dataout_2[19]\, \dataout_2[20]\, \dataout_2[21]\, - \dataout_2[22]\, \dataout_2[23]\, \dataout_2[24]\, - \dataout_2[25]\, \dataout_2[26]\, \dataout_2[27]\, - \dataout_2[28]\, \dataout_2[29]\, \dataout_2[30]\, - \dataout_2[31]\, \un1_p0_2_0[148]\, \un1_p0_2_0[498]\, - \faddr_RNIB0UOO[2]\, \dstate_i_RNI29QQ7J3[8]\, - \xaddress_RNITFTTE[3]\, \xaddress_RNIFP43F[2]\, - \faddr_RNI7MK691[6]\, \dci_m[102]\, \dci_m[101]\, - \dci_m[99]\, \dci_m[98]\, \dci_m[97]\, \dci_m[96]\, - \faddr_RNI7879K[0]\, \faddr_RNIEHR0O[1]\, - \dstate_RNIC3QA81[1]\, \dstate_RNIFPT581[1]\, - \dstate_i_0_RNIH0PPES[8]\, \dstate_RNI1G47MJ[1]\, - \dstate_RNIFS6E51[1]\, \xaddress_RNI1Q9ST1[1]\, - \xaddress_RNIEHIUT1[1]\, \xaddress_RNILHOK61[1]\, - \xaddress_RNILK99L1[1]\, \xaddress_RNI1I3MQ1[0]\, - \xaddress_RNIK99NK1[1]\, \xaddress_RNIP2BVK1[1]\, - \xaddress_RNIJI2O22[1]\, \xaddress_RNITMH17S2[12]\, - \xaddress_RNICFI17S2[13]\, \xaddress_RNI1D927S2[20]\, - \xaddress_RNI9MB27S2[23]\, \xaddress_RNI0GI17S2[17]\, - \xaddress_RNIC5A27S2[21]\, \xaddress_RNIN7J17S2[14]\, - \xaddress_RNIID927S2[16]\, \xaddress_RNI2MB27S2[15]\, - \dstate_i_0_RNIL7FGFS[8]\, \xaddress_RNID252J1[10]\, - \newtag_1_0[24]\, \newtag_1_0[25]\, \newtag_1_0[26]\, - \newtag_1_0[27]\, \dataout[0]\, \dataout[1]\, - \dataout[2]\, \dataout[3]\, \dataout[4]\, \dataout[5]\, - \dataout[6]\, \dataout[7]\, \dataout[8]\, \dataout[9]\, - \dataout[10]\, \dataout[11]\, \dataout[12]\, - \dataout[13]\, \dataout[14]\, \dataout[15]\, - \dataout[16]\, \dataout[17]\, \dataout[18]\, - \dataout[19]\, \dataout[20]\, \dataout[21]\, - \dataout[22]\, \dataout[23]\, \dataout[24]\, - \dataout[25]\, \dataout[26]\, \dataout[27]\, - \dataout[28]\, \dataout[29]\, \dataout[30]\, - \dataout[31]\, \dataout[32]\, \dataout[33]\, - \dataout[34]\, \dataout[35]\, \addr[30]\, \data1[0]\, - \data1[1]\, \data1[2]\, \data1[3]\, \data1[4]\, - \data1[5]\, \data1[6]\, \data1[7]\, \data1[8]\, - \data1[9]\, \data1[10]\, \data1[11]\, \data1[12]\, - \data1[13]\, \data1[14]\, \data1[15]\, \data1[16]\, - \data1[17]\, \data1[18]\, \data1[19]\, \data1[20]\, - \data1[21]\, \data1[22]\, \data1[23]\, \data1[24]\, - \data1[25]\, \data1[26]\, \data1[27]\, \data1[28]\, - \data1[29]\, \data1[30]\, \data1[31]\, \maddress[28]\, - \data2[0]\, \data2[1]\, \data2[2]\, \data2[3]\, - \data2[4]\, \data2[5]\, \data2[6]\, \data2[7]\, - \data2[8]\, \data2[9]\, \data2[10]\, \data2[11]\, - \data2[12]\, \data2[13]\, \data2[14]\, \data2[15]\, - \data2[16]\, \data2[17]\, \data2[18]\, \data2[19]\, - \data2[20]\, \data2[21]\, \data2[22]\, \data2[23]\, - \data2[24]\, \data2[25]\, \data2[26]\, \data2[27]\, - \data2[28]\, \data2[29]\, \data2[30]\, \data2[31]\, - \edata2_iv_i_0[31]\, \raddr1[0]\, \raddr1[1]\, - \raddr1[2]\, \raddr1[3]\, \raddr1[4]\, \raddr1[5]\, - \raddr1[6]\, \raddr1[7]\, \rfa1[0]\, \rfa1[1]\, \rfa1[2]\, - \rfa1[3]\, \rfa1[4]\, \rfa1[5]\, \rfa1[6]\, \rfa1[7]\, - \raddr2[0]\, \raddr2[1]\, \raddr2[2]\, \raddr2[3]\, - \raddr2[4]\, \raddr2[5]\, \raddr2[6]\, \raddr2[7]\, - \rfa2[0]\, \rfa2[1]\, \rfa2[2]\, \rfa2[3]\, \rfa2[4]\, - \rfa2[5]\, \rfa2[6]\, \rfa2[7]\, \waddr[0]\, \waddr[1]\, - \waddr[2]\, \waddr[3]\, \waddr[4]\, \waddr[5]\, - \waddr[6]\, \waddr[7]\, \wdata[0]\, \wdata[1]\, - \wdata[2]\, \wdata[3]\, \wdata[4]\, \wdata[5]\, - \wdata[6]\, \wdata[7]\, \wdata[8]\, \wdata[9]\, - \wdata[10]\, \wdata[11]\, \wdata[12]\, \wdata[13]\, - \wdata[14]\, \wdata[15]\, \wdata[16]\, \wdata[17]\, - \wdata[18]\, \wdata[19]\, \wdata[20]\, \wdata[21]\, - \wdata[22]\, \wdata[23]\, \wdata[24]\, \wdata[25]\, - \wdata[26]\, \wdata[27]\, \wdata[28]\, \wdata[29]\, - \wdata[30]\, \wdata[31]\, flush2_RNIFMGM2, - flush2_RNI5I3N7, N_984, N_980, N_987, N_986, flush2, - flush2_0_0_RNI146O2, flush2_0_0_RNI7G6O2, - flush2_0_0_RNIVV5O2, flush2_0_0_RNITR5O2, - flush2_0_0_RNIPJ5O2, N_981, N_985, N_983, N_982, un1_ici, - N_10, flush_RNIJEN4SI3, flush_RNIGBB873, N_270, N_269, - N_267, N_259, N_258, N_144, N_3846, read_RNIQH64D1, - read_RNIQPCQ11, read_RNIRO4K31, read_RNI0IQ7R, - read_RNIQFOD21, read_RNI8DFM31, read_RNIAQJ831, - read_RNI76N8R, read_RNI7G7G41, read_RNIMJHQT, - read_RNIL633F1, read_RNICKHE91, flush_0_1_RNIOMB27S2, - N_3239_i_0, N_26, read_RNIEKS231, read_RNIFPFT31, - read_RNIC9O9B1, flush_RNIGUM2OH3, read_RNICAQK41, - read_RNIQMJI41, read_RNISLPNU, read_RNIC70OF1, - read_RNI75LJ31, read_RNIEEGDD1, N_12_i_0, N_16_i_0, - flush_0_1_RNIBUA27S2, flush_0_1_RNIPTA27S2, N_24, N_329, - N_330, N_3254_0, ren1, rfe1, wren, ren2, rfe2, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : cachemem - Use entity work.cachemem(DEF_ARCH); - for all : proc3 - Use entity work.proc3(DEF_ARCH); - for all : regfile_3p - Use entity work.regfile_3p(DEF_ARCH); -begin - - - rst_RNI55L3 : CLKINT - port map(A => rst_0, Y => \rst\); - - rst : DFN1 - port map(D => rstn, CLK => lclk_c, Q => rst_0); - - cmem0 : cachemem - port map(xaddress_RNIFP43F(2) => \xaddress_RNIFP43F[2]\, - xaddress_RNITFTTE(3) => \xaddress_RNITFTTE[3]\, - dstate_RNIC3QA81(1) => \dstate_RNIC3QA81[1]\, - dstate_RNIFPT581(1) => \dstate_RNIFPT581[1]\, - dstate_RNIFS6E51(1) => \dstate_RNIFS6E51[1]\, - xaddress_RNI1Q9ST1(1) => \xaddress_RNI1Q9ST1[1]\, - xaddress_RNIEHIUT1(1) => \xaddress_RNIEHIUT1[1]\, - xaddress_RNILHOK61(1) => \xaddress_RNILHOK61[1]\, - xaddress_RNILK99L1(1) => \xaddress_RNILK99L1[1]\, - xaddress_RNI1I3MQ1(0) => \xaddress_RNI1I3MQ1[0]\, - xaddress_RNIK99NK1(1) => \xaddress_RNIK99NK1[1]\, - xaddress_RNIP2BVK1(1) => \xaddress_RNIP2BVK1[1]\, - xaddress_RNIJI2O22(1) => \xaddress_RNIJI2O22[1]\, - dstate_RNI1G47MJ(1) => \dstate_RNI1G47MJ[1]\, - edata2_iv_i_0(31) => \edata2_iv_i_0[31]\, addr(30) => - \addr[30]\, maddress(28) => \maddress[28]\, - newtag_1_0(27) => \newtag_1_0[27]\, newtag_1_0(26) => - \newtag_1_0[26]\, newtag_1_0(25) => \newtag_1_0[25]\, - newtag_1_0(24) => \newtag_1_0[24]\, faddr_RNI7879K(0) => - \faddr_RNI7879K[0]\, faddr_RNIEHR0O(1) => - \faddr_RNIEHR0O[1]\, faddr_RNIB0UOO(2) => - \faddr_RNIB0UOO[2]\, xaddress_RNID252J1(10) => - \xaddress_RNID252J1[10]\, faddr_RNI7MK691(6) => - \faddr_RNI7MK691[6]\, dstate_i_0_RNIL7FGFS(8) => - \dstate_i_0_RNIL7FGFS[8]\, dstate_i_0_RNIH0PPES(8) => - \dstate_i_0_RNIH0PPES[8]\, dstate_i_RNI29QQ7J3(8) => - \dstate_i_RNI29QQ7J3[8]\, xaddress_RNITMH17S2(12) => - \xaddress_RNITMH17S2[12]\, xaddress_RNICFI17S2(13) => - \xaddress_RNICFI17S2[13]\, xaddress_RNIN7J17S2(14) => - \xaddress_RNIN7J17S2[14]\, xaddress_RNI2MB27S2(15) => - \xaddress_RNI2MB27S2[15]\, xaddress_RNIID927S2(16) => - \xaddress_RNIID927S2[16]\, xaddress_RNI0GI17S2(17) => - \xaddress_RNI0GI17S2[17]\, xaddress_RNI1D927S2(20) => - \xaddress_RNI1D927S2[20]\, xaddress_RNIC5A27S2(21) => - \xaddress_RNIC5A27S2[21]\, xaddress_RNI9MB27S2(23) => - \xaddress_RNI9MB27S2[23]\, dataout(35) => \dataout[35]\, - dataout(34) => \dataout[34]\, dataout(33) => - \dataout[33]\, dataout(32) => \dataout[32]\, dataout(31) - => \dataout[31]\, dataout(30) => \dataout[30]\, - dataout(29) => \dataout[29]\, dataout(28) => - \dataout[28]\, dataout(27) => \dataout[27]\, dataout(26) - => \dataout[26]\, dataout(25) => \dataout[25]\, - dataout(24) => \dataout[24]\, dataout(23) => - \dataout[23]\, dataout(22) => \dataout[22]\, dataout(21) - => \dataout[21]\, dataout(20) => \dataout[20]\, - dataout(19) => \dataout[19]\, dataout(18) => - \dataout[18]\, dataout(17) => \dataout[17]\, dataout(16) - => \dataout[16]\, dataout(15) => \dataout[15]\, - dataout(14) => \dataout[14]\, dataout(13) => - \dataout[13]\, dataout(12) => \dataout[12]\, dataout(11) - => \dataout[11]\, dataout(10) => \dataout[10]\, - dataout(9) => \dataout[9]\, dataout(8) => \dataout[8]\, - dataout(7) => \dataout[7]\, dataout(6) => \dataout[6]\, - dataout(5) => \dataout[5]\, dataout(4) => \dataout[4]\, - dataout(3) => \dataout[3]\, dataout(2) => \dataout[2]\, - dataout(1) => \dataout[1]\, dataout(0) => \dataout[0]\, - vaddress_RNI8EVQ36(2) => \vaddress_RNI8EVQ36[2]\, - vaddress_RNIFCB8U6(3) => \vaddress_RNIFCB8U6[3]\, - vaddress_RNIJG6QR7(4) => \vaddress_RNIJG6QR7[4]\, - istate_RNIUCOFG(0) => \istate_RNIUCOFG[0]\, - istate_RNIPSU8G(0) => \istate_RNIPSU8G[0]\, - istate_RNI6HPAI(0) => \istate_RNI6HPAI[0]\, - istate_RNI57KLB(0) => \istate_RNI57KLB[0]\, - istate_RNIG7IIA(0) => \istate_RNIG7IIA[0]\, - istate_RNIEC82C(0) => \istate_RNIEC82C[0]\, - istate_RNI7BUID(0) => \istate_RNI7BUID[0]\, - istate_RNIV33V9(0) => \istate_RNIV33V9[0]\, - istate_RNIMRTH8(0) => \istate_RNIMRTH8[0]\, - istate_RNIGUTA8(0) => \istate_RNIGUTA8[0]\, - istate_RNI6LOO6(0) => \istate_RNI6LOO6[0]\, - istate_RNIKJBN8(0) => \istate_RNIKJBN8[0]\, - istate_RNIN6957(0) => \istate_RNIN6957[0]\, - istate_RNI6PSS1(0) => \istate_RNI6PSS1[0]\, - istate_RNIOVC5J(0) => \istate_RNIOVC5J[0]\, - istate_RNIA8N5H(0) => \istate_RNIA8N5H[0]\, - istate_RNIK9NF8(0) => \istate_RNIK9NF8[0]\, - istate_RNILTAC8(0) => \istate_RNILTAC8[0]\, - istate_RNI8BL1A(0) => \istate_RNI8BL1A[0]\, - istate_RNI2MM6D(0) => \istate_RNI2MM6D[0]\, - istate_RNIVTQIJ(0) => \istate_RNIVTQIJ[0]\, - istate_RNIAJH4F(0) => \istate_RNIAJH4F[0]\, - istate_RNIM2DE7(0) => \istate_RNIM2DE7[0]\, - istate_RNI5V68H(0) => \istate_RNI5V68H[0]\, - istate_RNIH0NBI(0) => \istate_RNIH0NBI[0]\, - istate_RNIAP6PI(0) => \istate_RNIAP6PI[0]\, - istate_RNIOJJE1(0) => \istate_RNIOJJE1[0]\, - istate_RNIR2JU8(0) => \istate_RNIR2JU8[0]\, - istate_RNIJSOBE(0) => \istate_RNIJSOBE[0]\, - istate_RNIRASC8(0) => \istate_RNIRASC8[0]\, - istate_RNIS4VK8(0) => \istate_RNIS4VK8[0]\, - istate_RNIENB3M(0) => \istate_RNIENB3M[0]\, - istate_RNIJCMP6(0) => \istate_RNIJCMP6[0]\, - faddr_RNI7H6KT8(0) => \faddr_RNI7H6KT8[0]\, - faddr_RNIKVTLT9(1) => \faddr_RNIKVTLT9[1]\, - faddr_RNISJSHQA(2) => \faddr_RNISJSHQA[2]\, - faddr_RNIUT72LB(3) => \faddr_RNIUT72LB[3]\, - faddr_RNI0FOJNE(4) => \faddr_RNI0FOJNE[4]\, - faddr_RNI7UFASD(5) => \faddr_RNI7UFASD[5]\, - faddr_RNIDN2CUE(6) => \faddr_RNIDN2CUE[6]\, un1_p0_2_i_0 - => \un1_p0_2_i[117]\, un1_p0_2_i_4 => \un1_p0_2_i[121]\, - vaddress_RNIOFAKMI(12) => \vaddress_RNIOFAKMI[12]\, - vaddress_RNIQFAKMI(13) => \vaddress_RNIQFAKMI[13]\, - vaddress_RNISFAKMI(14) => \vaddress_RNISFAKMI[14]\, - vaddress_RNIUFAKMI(15) => \vaddress_RNIUFAKMI[15]\, - vaddress_RNI0GAKMI(16) => \vaddress_RNI0GAKMI[16]\, - vaddress_RNI2GAKMI(17) => \vaddress_RNI2GAKMI[17]\, - vaddress_RNI4GAKMI(18) => \vaddress_RNI4GAKMI[18]\, - vaddress_RNI6GAKMI(19) => \vaddress_RNI6GAKMI[19]\, - vaddress_RNIQNAKMI(20) => \vaddress_RNIQNAKMI[20]\, - vaddress_RNISNAKMI(21) => \vaddress_RNISNAKMI[21]\, - vaddress_RNIUNAKMI(22) => \vaddress_RNIUNAKMI[22]\, - vaddress_RNI0OAKMI(23) => \vaddress_RNI0OAKMI[23]\, - ctx(7) => \ctx[7]\, ctx(6) => \ctx[6]\, ctx(5) => - \ctx[5]\, ctx(4) => \ctx[4]\, ctx(3) => \ctx[3]\, ctx(2) - => \ctx[2]\, ctx(1) => \ctx[1]\, ctx(0) => \ctx[0]\, - dataout_2(31) => \dataout_2[31]\, dataout_2(30) => - \dataout_2[30]\, dataout_2(29) => \dataout_2[29]\, - dataout_2(28) => \dataout_2[28]\, dataout_2(27) => - \dataout_2[27]\, dataout_2(26) => \dataout_2[26]\, - dataout_2(25) => \dataout_2[25]\, dataout_2(24) => - \dataout_2[24]\, dataout_2(23) => \dataout_2[23]\, - dataout_2(22) => \dataout_2[22]\, dataout_2(21) => - \dataout_2[21]\, dataout_2(20) => \dataout_2[20]\, - dataout_2(19) => \dataout_2[19]\, dataout_2(18) => - \dataout_2[18]\, dataout_2(17) => \dataout_2[17]\, - dataout_2(16) => \dataout_2[16]\, dataout_2(15) => - \dataout_2[15]\, dataout_2(14) => \dataout_2[14]\, - dataout_2(13) => \dataout_2[13]\, dataout_2(12) => - \dataout_2[12]\, dataout_2(11) => \dataout_2[11]\, - dataout_2(10) => \dataout_2[10]\, dataout_2(9) => - \dataout_2[9]\, dataout_2(8) => \dataout_2[8]\, - dataout_2(7) => \dataout_2[7]\, dataout_2(6) => - \dataout_2[6]\, dataout_2(5) => \dataout_2[5]\, - dataout_2(4) => \dataout_2[4]\, dataout_2(3) => - \dataout_2[3]\, dataout_2(2) => \dataout_2[2]\, - dataout_2(1) => \dataout_2[1]\, dataout_2(0) => - \dataout_2[0]\, dataout_1(31) => \dataout_1[31]\, - dataout_1(30) => \dataout_1[30]\, dataout_1(29) => - \dataout_1[29]\, dataout_1(28) => \dataout_1[28]\, - dataout_1(27) => \dataout_1[27]\, dataout_1(26) => - \dataout_1[26]\, dataout_1(25) => \dataout_1[25]\, - dataout_1(24) => \dataout_1[24]\, dataout_1(23) => - \dataout_1[23]\, dataout_1(22) => \dataout_1[22]\, - dataout_1(21) => \dataout_1[21]\, dataout_1(20) => - \dataout_1[20]\, dataout_1(19) => \dataout_1[19]\, - dataout_1(18) => \dataout_1[18]\, dataout_1(17) => - \dataout_1[17]\, dataout_1(16) => \dataout_1[16]\, - dataout_1(15) => \dataout_1[15]\, dataout_1(14) => - \dataout_1[14]\, dataout_1(13) => \dataout_1[13]\, - dataout_1(12) => \dataout_1[12]\, dataout_1(11) => - \dataout_1[11]\, dataout_1(10) => \dataout_1[10]\, - dataout_1(9) => \dataout_1[9]\, dataout_1(8) => - \dataout_1[8]\, dataout_1(7) => \dataout_1[7]\, - dataout_1(6) => \dataout_1[6]\, dataout_1(5) => - \dataout_1[5]\, dataout_1(4) => \dataout_1[4]\, - dataout_1(3) => \dataout_1[3]\, dataout_1(2) => - \dataout_1[2]\, dataout_1(1) => \dataout_1[1]\, - dataout_1(0) => \dataout_1[0]\, dataout_0(35) => - \dataout_0[35]\, dataout_0(34) => \dataout_0[34]\, - dataout_0(33) => \dataout_0[33]\, dataout_0(32) => - \dataout_0[32]\, dataout_0(31) => \dataout_0[31]\, - dataout_0(30) => \dataout_0[30]\, dataout_0(29) => - \dataout_0[29]\, dataout_0(28) => \dataout_0[28]\, - dataout_0(27) => \dataout_0[27]\, dataout_0(26) => - \dataout_0[26]\, dataout_0(25) => \dataout_0[25]\, - dataout_0(24) => \dataout_0[24]\, dataout_0(23) => - \dataout_0[23]\, dataout_0(22) => \dataout_0[22]\, - dataout_0(21) => \dataout_0[21]\, dataout_0(20) => - \dataout_0[20]\, dataout_0(19) => \dataout_0[19]\, - dataout_0(18) => \dataout_0[18]\, dataout_0(17) => - \dataout_0[17]\, dataout_0(16) => \dataout_0[16]\, - dataout_0(15) => \dataout_0[15]\, dataout_0(14) => - \dataout_0[14]\, dataout_0(13) => \dataout_0[13]\, - dataout_0(12) => \dataout_0[12]\, dataout_0(11) => - \dataout_0[11]\, dataout_0(10) => \dataout_0[10]\, - dataout_0(9) => \dataout_0[9]\, dataout_0(8) => - \dataout_0[8]\, dataout_0(7) => \dataout_0[7]\, - dataout_0(6) => \dataout_0[6]\, dataout_0(5) => - \dataout_0[5]\, dataout_0(4) => \dataout_0[4]\, - dataout_0(3) => \dataout_0[3]\, dataout_0(2) => - \dataout_0[2]\, dataout_0(1) => \dataout_0[1]\, - dataout_0(0) => \dataout_0[0]\, vitdatain_0_1_0(22) => - \vitdatain_0_1_0[22]\, un1_p0_2_0_0 => \un1_p0_2_0[148]\, - un1_p0_2_0_350 => \un1_p0_2_0[498]\, dci_m_6 => - \dci_m[102]\, dci_m_0 => \dci_m[96]\, dci_m_1 => - \dci_m[97]\, dci_m_2 => \dci_m[98]\, dci_m_3 => - \dci_m[99]\, dci_m_5 => \dci_m[101]\, N_10 => N_10, - read_RNI0IQ7R => read_RNI0IQ7R, read_RNIRO4K31 => - read_RNIRO4K31, read_RNIQFOD21 => read_RNIQFOD21, - read_RNIFPFT31 => read_RNIFPFT31, read_RNIQPCQ11 => - read_RNIQPCQ11, read_RNI8DFM31 => read_RNI8DFM31, - read_RNIAQJ831 => read_RNIAQJ831, read_RNI76N8R => - read_RNI76N8R, read_RNI7G7G41 => read_RNI7G7G41, - read_RNIEKS231 => read_RNIEKS231, read_RNIMJHQT => - read_RNIMJHQT, read_RNIL633F1 => read_RNIL633F1, - read_RNIQH64D1 => read_RNIQH64D1, read_RNICAQK41 => - read_RNICAQK41, read_RNIQMJI41 => read_RNIQMJI41, - read_RNISLPNU => read_RNISLPNU, read_RNICKHE91 => - read_RNICKHE91, read_RNIC70OF1 => read_RNIC70OF1, - read_RNIC9O9B1 => read_RNIC9O9B1, read_RNI75LJ31 => - read_RNI75LJ31, read_RNIEEGDD1 => read_RNIEEGDD1, - N_3254_0 => N_3254_0, N_330 => N_330, N_267 => N_267, - N_329 => N_329, N_144 => N_144, N_3846 => N_3846, N_270 - => N_270, N_269 => N_269, N_24 => N_24, N_26 => N_26, - N_12_i_0 => N_12_i_0, flush_RNIJEN4SI3 => - flush_RNIJEN4SI3, flush_RNIGUM2OH3 => flush_RNIGUM2OH3, - N_16_i_0 => N_16_i_0, N_3239_i_0 => N_3239_i_0, - flush_0_1_RNIBUA27S2 => flush_0_1_RNIBUA27S2, - flush_0_1_RNIOMB27S2 => flush_0_1_RNIOMB27S2, - flush_0_1_RNIPTA27S2 => flush_0_1_RNIPTA27S2, - flush_RNIGBB873 => flush_RNIGBB873, N_980 => N_980, N_981 - => N_981, N_983 => N_983, N_982 => N_982, N_985 => N_985, - N_986 => N_986, flush2 => flush2, N_987 => N_987, N_984 - => N_984, lclk_c => lclk_c, flush2_0_0_RNIPJ5O2 => - flush2_0_0_RNIPJ5O2, flush2_0_0_RNITR5O2 => - flush2_0_0_RNITR5O2, flush2_0_0_RNIVV5O2 => - flush2_0_0_RNIVV5O2, flush2_0_0_RNI146O2 => - flush2_0_0_RNI146O2, flush2_RNIFMGM2 => flush2_RNIFMGM2, - flush2_0_0_RNI7G6O2 => flush2_0_0_RNI7G6O2, cachemem_VCC - => leon3s_VCC, flush2_RNI5I3N7 => flush2_RNI5I3N7, - un1_ici => un1_ici, N_258 => N_258, N_259 => N_259); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - p0 : proc3 - port map(istate_RNIJCMP6(0) => \istate_RNIJCMP6[0]\, - faddr_RNIUT72LB(3) => \faddr_RNIUT72LB[3]\, - vaddress_RNISNAKMI(21) => \vaddress_RNISNAKMI[21]\, - vaddress_RNI6GAKMI(19) => \vaddress_RNI6GAKMI[19]\, - faddr_RNISJSHQA(2) => \faddr_RNISJSHQA[2]\, - vaddress_RNIQNAKMI(20) => \vaddress_RNIQNAKMI[20]\, - faddr_RNI7UFASD(5) => \faddr_RNI7UFASD[5]\, - faddr_RNI0FOJNE(4) => \faddr_RNI0FOJNE[4]\, - faddr_RNIDN2CUE(6) => \faddr_RNIDN2CUE[6]\, - faddr_RNIKVTLT9(1) => \faddr_RNIKVTLT9[1]\, - vaddress_RNI0GAKMI(16) => \vaddress_RNI0GAKMI[16]\, - vaddress_RNI0OAKMI(23) => \vaddress_RNI0OAKMI[23]\, - vaddress_RNIOFAKMI(12) => \vaddress_RNIOFAKMI[12]\, - vaddress_RNIJG6QR7(4) => \vaddress_RNIJG6QR7[4]\, - un1_p0_2_i_4 => \un1_p0_2_i[121]\, un1_p0_2_i_0 => - \un1_p0_2_i[117]\, ctx(7) => \ctx[7]\, ctx(6) => \ctx[6]\, - ctx(5) => \ctx[5]\, ctx(4) => \ctx[4]\, ctx(3) => - \ctx[3]\, ctx(2) => \ctx[2]\, ctx(1) => \ctx[1]\, ctx(0) - => \ctx[0]\, istate_RNI6HPAI(0) => \istate_RNI6HPAI[0]\, - istate_RNIAJH4F(0) => \istate_RNIAJH4F[0]\, - vaddress_RNIUNAKMI(22) => \vaddress_RNIUNAKMI[22]\, - vaddress_RNISFAKMI(14) => \vaddress_RNISFAKMI[14]\, - istate_RNI57KLB(0) => \istate_RNI57KLB[0]\, - istate_RNIUCOFG(0) => \istate_RNIUCOFG[0]\, - faddr_RNI7H6KT8(0) => \faddr_RNI7H6KT8[0]\, - istate_RNIH0NBI(0) => \istate_RNIH0NBI[0]\, - istate_RNIG7IIA(0) => \istate_RNIG7IIA[0]\, - vaddress_RNIFCB8U6(3) => \vaddress_RNIFCB8U6[3]\, - istate_RNI2MM6D(0) => \istate_RNI2MM6D[0]\, - istate_RNI8BL1A(0) => \istate_RNI8BL1A[0]\, - istate_RNILTAC8(0) => \istate_RNILTAC8[0]\, - istate_RNIK9NF8(0) => \istate_RNIK9NF8[0]\, - vaddress_RNI4GAKMI(18) => \vaddress_RNI4GAKMI[18]\, - vaddress_RNI2GAKMI(17) => \vaddress_RNI2GAKMI[17]\, - istate_RNI5V68H(0) => \istate_RNI5V68H[0]\, - istate_RNIM2DE7(0) => \istate_RNIM2DE7[0]\, - istate_RNIVTQIJ(0) => \istate_RNIVTQIJ[0]\, - istate_RNIOVC5J(0) => \istate_RNIOVC5J[0]\, - istate_RNI6PSS1(0) => \istate_RNI6PSS1[0]\, - istate_RNIGUTA8(0) => \istate_RNIGUTA8[0]\, - istate_RNIMRTH8(0) => \istate_RNIMRTH8[0]\, - vaddress_RNIQFAKMI(13) => \vaddress_RNIQFAKMI[13]\, - istate_RNIAP6PI(0) => \istate_RNIAP6PI[0]\, - istate_RNIENB3M(0) => \istate_RNIENB3M[0]\, - istate_RNIS4VK8(0) => \istate_RNIS4VK8[0]\, - istate_RNIRASC8(0) => \istate_RNIRASC8[0]\, - istate_RNIJSOBE(0) => \istate_RNIJSOBE[0]\, - istate_RNIR2JU8(0) => \istate_RNIR2JU8[0]\, - istate_RNIOJJE1(0) => \istate_RNIOJJE1[0]\, - istate_RNIN6957(0) => \istate_RNIN6957[0]\, - istate_RNIKJBN8(0) => \istate_RNIKJBN8[0]\, - istate_RNI6LOO6(0) => \istate_RNI6LOO6[0]\, - istate_RNIV33V9(0) => \istate_RNIV33V9[0]\, - istate_RNI7BUID(0) => \istate_RNI7BUID[0]\, - istate_RNIEC82C(0) => \istate_RNIEC82C[0]\, - istate_RNIPSU8G(0) => \istate_RNIPSU8G[0]\, hrdata_31 => - hrdata_31, hrdata_30 => hrdata_30, hrdata_29 => hrdata_29, - hrdata_28 => hrdata_28, hrdata_6 => hrdata_6, hrdata_5 - => hrdata_5, hrdata_7 => hrdata_7, hrdata_4 => hrdata_4, - hrdata_3 => hrdata_3, hrdata_2 => hrdata_2, hrdata_27 => - hrdata_27, hrdata_26 => hrdata_26, hrdata_23 => hrdata_23, - hrdata_22 => hrdata_22, hrdata_21 => hrdata_21, hrdata_18 - => hrdata_18, hrdata_16 => hrdata_16, hrdata_15 => - hrdata_15, hrdata_12 => hrdata_12, hrdata_8 => hrdata_8, - hrdata_1 => hrdata_1, hrdata_0_d0 => hrdata_0_d0, - hrdata_24 => hrdata_24, hrdata_17 => hrdata_17, hrdata_14 - => hrdata_14, hrdata_13 => hrdata_13, hrdata_11 => - hrdata_11, hrdata_10 => hrdata_10, hrdata_9 => hrdata_9, - vaddress_RNI8EVQ36(2) => \vaddress_RNI8EVQ36[2]\, - hrdata_0_3 => hrdata_0_3, hrdata_0_24 => hrdata_0_24, - hrdata_0_4 => hrdata_0_4, hrdata_0_18 => hrdata_0_18, - hrdata_0_17 => hrdata_0_17, hrdata_0_16 => hrdata_0_16, - hrdata_0_23 => hrdata_0_23, hrdata_0_22 => hrdata_0_22, - hrdata_0_14 => hrdata_0_14, hrdata_0_13 => hrdata_0_13, - hrdata_0_9 => hrdata_0_9, hrdata_0_8 => hrdata_0_8, - hrdata_0_21 => hrdata_0_21, hrdata_0_27 => hrdata_0_27, - hrdata_0_12 => hrdata_0_12, hrdata_0_11 => hrdata_0_11, - hrdata_0_10 => hrdata_0_10, hrdata_0_7 => hrdata_0_7, - hrdata_0_1 => hrdata_0_1, hrdata_0_2 => hrdata_0_2, - hrdata_0_26 => hrdata_0_26, hrdata_0_0 => hrdata_0_0, - hrdata_0_15 => hrdata_0_15, istate_RNIA8N5H(0) => - \istate_RNIA8N5H[0]\, vaddress_RNIUFAKMI(15) => - \vaddress_RNIUFAKMI[15]\, vitdatain_0_1_0(22) => - \vitdatain_0_1_0[22]\, dataout_1(31) => \dataout_1[31]\, - dataout_1(30) => \dataout_1[30]\, dataout_1(29) => - \dataout_1[29]\, dataout_1(28) => \dataout_1[28]\, - dataout_1(27) => \dataout_1[27]\, dataout_1(26) => - \dataout_1[26]\, dataout_1(25) => \dataout_1[25]\, - dataout_1(24) => \dataout_1[24]\, dataout_1(23) => - \dataout_1[23]\, dataout_1(22) => \dataout_1[22]\, - dataout_1(21) => \dataout_1[21]\, dataout_1(20) => - \dataout_1[20]\, dataout_1(19) => \dataout_1[19]\, - dataout_1(18) => \dataout_1[18]\, dataout_1(17) => - \dataout_1[17]\, dataout_1(16) => \dataout_1[16]\, - dataout_1(15) => \dataout_1[15]\, dataout_1(14) => - \dataout_1[14]\, dataout_1(13) => \dataout_1[13]\, - dataout_1(12) => \dataout_1[12]\, dataout_1(11) => - \dataout_1[11]\, dataout_1(10) => \dataout_1[10]\, - dataout_1(9) => \dataout_1[9]\, dataout_1(8) => - \dataout_1[8]\, dataout_1(7) => \dataout_1[7]\, - dataout_1(6) => \dataout_1[6]\, dataout_1(5) => - \dataout_1[5]\, dataout_1(4) => \dataout_1[4]\, - dataout_1(3) => \dataout_1[3]\, dataout_1(2) => - \dataout_1[2]\, dataout_1(1) => \dataout_1[1]\, - dataout_1(0) => \dataout_1[0]\, dataout_0(35) => - \dataout_0[35]\, dataout_0(34) => \dataout_0[34]\, - dataout_0(33) => \dataout_0[33]\, dataout_0(32) => - \dataout_0[32]\, dataout_0(31) => \dataout_0[31]\, - dataout_0(30) => \dataout_0[30]\, dataout_0(29) => - \dataout_0[29]\, dataout_0(28) => \dataout_0[28]\, - dataout_0(27) => \dataout_0[27]\, dataout_0(26) => - \dataout_0[26]\, dataout_0(25) => \dataout_0[25]\, - dataout_0(24) => \dataout_0[24]\, dataout_0(23) => - \dataout_0[23]\, dataout_0(22) => \dataout_0[22]\, - dataout_0(21) => \dataout_0[21]\, dataout_0(20) => - \dataout_0[20]\, dataout_0(19) => \dataout_0[19]\, - dataout_0(18) => \dataout_0[18]\, dataout_0(17) => - \dataout_0[17]\, dataout_0(16) => \dataout_0[16]\, - dataout_0(15) => \dataout_0[15]\, dataout_0(14) => - \dataout_0[14]\, dataout_0(13) => \dataout_0[13]\, - dataout_0(12) => \dataout_0[12]\, dataout_0(11) => - \dataout_0[11]\, dataout_0(10) => \dataout_0[10]\, - dataout_0(9) => \dataout_0[9]\, dataout_0(8) => - \dataout_0[8]\, dataout_0(7) => \dataout_0[7]\, - dataout_0(6) => \dataout_0[6]\, dataout_0(5) => - \dataout_0[5]\, dataout_0(4) => \dataout_0[4]\, - dataout_0(3) => \dataout_0[3]\, dataout_0(2) => - \dataout_0[2]\, dataout_0(1) => \dataout_0[1]\, - dataout_0(0) => \dataout_0[0]\, dataout_2(31) => - \dataout_2[31]\, dataout_2(30) => \dataout_2[30]\, - dataout_2(29) => \dataout_2[29]\, dataout_2(28) => - \dataout_2[28]\, dataout_2(27) => \dataout_2[27]\, - dataout_2(26) => \dataout_2[26]\, dataout_2(25) => - \dataout_2[25]\, dataout_2(24) => \dataout_2[24]\, - dataout_2(23) => \dataout_2[23]\, dataout_2(22) => - \dataout_2[22]\, dataout_2(21) => \dataout_2[21]\, - dataout_2(20) => \dataout_2[20]\, dataout_2(19) => - \dataout_2[19]\, dataout_2(18) => \dataout_2[18]\, - dataout_2(17) => \dataout_2[17]\, dataout_2(16) => - \dataout_2[16]\, dataout_2(15) => \dataout_2[15]\, - dataout_2(14) => \dataout_2[14]\, dataout_2(13) => - \dataout_2[13]\, dataout_2(12) => \dataout_2[12]\, - dataout_2(11) => \dataout_2[11]\, dataout_2(10) => - \dataout_2[10]\, dataout_2(9) => \dataout_2[9]\, - dataout_2(8) => \dataout_2[8]\, dataout_2(7) => - \dataout_2[7]\, dataout_2(6) => \dataout_2[6]\, - dataout_2(5) => \dataout_2[5]\, dataout_2(4) => - \dataout_2[4]\, dataout_2(3) => \dataout_2[3]\, - dataout_2(2) => \dataout_2[2]\, dataout_2(1) => - \dataout_2[1]\, dataout_2(0) => \dataout_2[0]\, - un1_p0_2_0_0 => \un1_p0_2_0[148]\, un1_p0_2_0_350 => - \un1_p0_2_0[498]\, data_1_21 => data_24, data_1_16 => - data_19, data_1_5 => data_8, data_1_0 => data_3, data_1_2 - => data_5, faddr_RNIB0UOO(2) => \faddr_RNIB0UOO[2]\, - dstate_i_RNI29QQ7J3(8) => \dstate_i_RNI29QQ7J3[8]\, - xaddress_RNITFTTE(3) => \xaddress_RNITFTTE[3]\, - xaddress_RNIFP43F(2) => \xaddress_RNIFP43F[2]\, size_0(0) - => size(0), faddr_RNI7MK691(6) => \faddr_RNI7MK691[6]\, - dci_m_6 => \dci_m[102]\, dci_m_5 => \dci_m[101]\, dci_m_3 - => \dci_m[99]\, dci_m_2 => \dci_m[98]\, dci_m_1 => - \dci_m[97]\, dci_m_0 => \dci_m[96]\, faddr_RNI7879K(0) - => \faddr_RNI7879K[0]\, faddr_RNIEHR0O(1) => - \faddr_RNIEHR0O[1]\, dstate_RNIC3QA81(1) => - \dstate_RNIC3QA81[1]\, dstate_RNIFPT581(1) => - \dstate_RNIFPT581[1]\, dstate_i_0_RNIH0PPES(8) => - \dstate_i_0_RNIH0PPES[8]\, dstate_RNI1G47MJ(1) => - \dstate_RNI1G47MJ[1]\, dstate_RNIFS6E51(1) => - \dstate_RNIFS6E51[1]\, xaddress_RNI1Q9ST1(1) => - \xaddress_RNI1Q9ST1[1]\, xaddress_RNIEHIUT1(1) => - \xaddress_RNIEHIUT1[1]\, xaddress_RNILHOK61(1) => - \xaddress_RNILHOK61[1]\, xaddress_RNILK99L1(1) => - \xaddress_RNILK99L1[1]\, xaddress_RNI1I3MQ1(0) => - \xaddress_RNI1I3MQ1[0]\, xaddress_RNIK99NK1(1) => - \xaddress_RNIK99NK1[1]\, xaddress_RNIP2BVK1(1) => - \xaddress_RNIP2BVK1[1]\, xaddress_RNIJI2O22(1) => - \xaddress_RNIJI2O22[1]\, xaddress_RNITMH17S2(12) => - \xaddress_RNITMH17S2[12]\, xaddress_RNICFI17S2(13) => - \xaddress_RNICFI17S2[13]\, xaddress_RNI1D927S2(20) => - \xaddress_RNI1D927S2[20]\, xaddress_RNI9MB27S2(23) => - \xaddress_RNI9MB27S2[23]\, xaddress_RNI0GI17S2(17) => - \xaddress_RNI0GI17S2[17]\, xaddress_RNIC5A27S2(21) => - \xaddress_RNIC5A27S2[21]\, xaddress_RNIN7J17S2(14) => - \xaddress_RNIN7J17S2[14]\, xaddress_RNIID927S2(16) => - \xaddress_RNIID927S2[16]\, xaddress_RNI2MB27S2(15) => - \xaddress_RNI2MB27S2[15]\, dstate_i_0_RNIL7FGFS(8) => - \dstate_i_0_RNIL7FGFS[8]\, xaddress_RNID252J1(10) => - \xaddress_RNID252J1[10]\, newtag_1_0(27) => - \newtag_1_0[27]\, newtag_1_0(26) => \newtag_1_0[26]\, - newtag_1_0(25) => \newtag_1_0[25]\, newtag_1_0(24) => - \newtag_1_0[24]\, dataout(35) => \dataout[35]\, - dataout(34) => \dataout[34]\, dataout(33) => - \dataout[33]\, dataout(32) => \dataout[32]\, dataout(31) - => \dataout[31]\, dataout(30) => \dataout[30]\, - dataout(29) => \dataout[29]\, dataout(28) => - \dataout[28]\, dataout(27) => \dataout[27]\, dataout(26) - => \dataout[26]\, dataout(25) => \dataout[25]\, - dataout(24) => \dataout[24]\, dataout(23) => - \dataout[23]\, dataout(22) => \dataout[22]\, dataout(21) - => \dataout[21]\, dataout(20) => \dataout[20]\, - dataout(19) => \dataout[19]\, dataout(18) => - \dataout[18]\, dataout(17) => \dataout[17]\, dataout(16) - => \dataout[16]\, dataout(15) => \dataout[15]\, - dataout(14) => \dataout[14]\, dataout(13) => - \dataout[13]\, dataout(12) => \dataout[12]\, dataout(11) - => \dataout[11]\, dataout(10) => \dataout[10]\, - dataout(9) => \dataout[9]\, dataout(8) => \dataout[8]\, - dataout(7) => \dataout[7]\, dataout(6) => \dataout[6]\, - dataout(5) => \dataout[5]\, dataout(4) => \dataout[4]\, - dataout(3) => \dataout[3]\, dataout(2) => \dataout[2]\, - dataout(1) => \dataout[1]\, dataout(0) => \dataout[0]\, - address(1) => address(1), address(0) => address(0), - addr(30) => \addr[30]\, iosn_2(93) => iosn_2(93), - hresp(0) => hresp(0), hgrant(0) => hgrant(0), hsize_5(1) - => hsize_5(1), iosn_1(93) => iosn_1(93), hwdata_15 => - hwdata_15, hwdata_0 => hwdata_0, hwdata_14 => hwdata_14, - hwdata_1 => hwdata_1, hwdata_28 => hwdata_28, hwdata_23 - => hwdata_23, hwdata_12 => hwdata_12, hwdata_4 => - hwdata_4, hwdata_13 => hwdata_13, hwdata_27 => hwdata_27, - hwdata_25 => hwdata_25, hwdata_11 => hwdata_11, hwdata_9 - => hwdata_9, hwdata_3 => hwdata_3, hwdata_16 => - hwdata_16, haddr(31) => haddr(31), haddr(30) => haddr(30), - haddr(29) => haddr(29), haddr(28) => haddr(28), haddr(27) - => haddr(27), haddr(26) => haddr(26), haddr(25) => - haddr(25), haddr(24) => haddr(24), haddr(23) => haddr(23), - haddr(22) => haddr(22), haddr(21) => haddr(21), haddr(20) - => haddr(20), haddr(19) => haddr(19), haddr(18) => - haddr(18), haddr(17) => haddr(17), haddr(16) => haddr(16), - haddr(15) => haddr(15), haddr(14) => haddr(14), haddr(13) - => haddr(13), haddr(12) => haddr(12), haddr(11) => - haddr(11), haddr(10) => haddr(10), haddr(9) => haddr(9), - haddr(8) => haddr(8), haddr(7) => haddr(7), haddr(6) => - haddr(6), haddr(5) => haddr(5), haddr(4) => haddr(4), - haddr(3) => haddr(3), haddr(2) => haddr(2), htrans_tz(1) - => htrans_tz(1), iosn_0(93) => iosn_0(93), htrans(1) => - htrans(1), nbo_5_0(1) => nbo_5_0(1), nbo_5_0(0) => - nbo_5_0(0), data_0 => data_0_d0, data_3 => data_0_0, - data_5 => data_0_2, data_8 => data_0_5, data_19 => - data_0_16, data_24 => data_0_21, hrdata_1_0_1(1) => - hrdata_1_0_1(1), data1(31) => \data1[31]\, data1(30) => - \data1[30]\, data1(29) => \data1[29]\, data1(28) => - \data1[28]\, data1(27) => \data1[27]\, data1(26) => - \data1[26]\, data1(25) => \data1[25]\, data1(24) => - \data1[24]\, data1(23) => \data1[23]\, data1(22) => - \data1[22]\, data1(21) => \data1[21]\, data1(20) => - \data1[20]\, data1(19) => \data1[19]\, data1(18) => - \data1[18]\, data1(17) => \data1[17]\, data1(16) => - \data1[16]\, data1(15) => \data1[15]\, data1(14) => - \data1[14]\, data1(13) => \data1[13]\, data1(12) => - \data1[12]\, data1(11) => \data1[11]\, data1(10) => - \data1[10]\, data1(9) => \data1[9]\, data1(8) => - \data1[8]\, data1(7) => \data1[7]\, data1(6) => - \data1[6]\, data1(5) => \data1[5]\, data1(4) => - \data1[4]\, data1(3) => \data1[3]\, data1(2) => - \data1[2]\, data1(1) => \data1[1]\, data1(0) => - \data1[0]\, maddress_28 => \maddress[28]\, data2(31) => - \data2[31]\, data2(30) => \data2[30]\, data2(29) => - \data2[29]\, data2(28) => \data2[28]\, data2(27) => - \data2[27]\, data2(26) => \data2[26]\, data2(25) => - \data2[25]\, data2(24) => \data2[24]\, data2(23) => - \data2[23]\, data2(22) => \data2[22]\, data2(21) => - \data2[21]\, data2(20) => \data2[20]\, data2(19) => - \data2[19]\, data2(18) => \data2[18]\, data2(17) => - \data2[17]\, data2(16) => \data2[16]\, data2(15) => - \data2[15]\, data2(14) => \data2[14]\, data2(13) => - \data2[13]\, data2(12) => \data2[12]\, data2(11) => - \data2[11]\, data2(10) => \data2[10]\, data2(9) => - \data2[9]\, data2(8) => \data2[8]\, data2(7) => - \data2[7]\, data2(6) => \data2[6]\, data2(5) => - \data2[5]\, data2(4) => \data2[4]\, data2(3) => - \data2[3]\, data2(2) => \data2[2]\, data2(1) => - \data2[1]\, data2(0) => \data2[0]\, irl_0(3) => irl(3), - irl_0(2) => irl(2), irl_0(1) => irl(1), irl_0(0) => - irl(0), irl(3) => irl_0(3), irl(2) => irl_0(2), irl(1) - => irl_0(1), irl(0) => irl_0(0), edata2_iv_i_0_7 => - \edata2_iv_i_0[31]\, raddr1(7) => \raddr1[7]\, raddr1(6) - => \raddr1[6]\, raddr1(5) => \raddr1[5]\, raddr1(4) => - \raddr1[4]\, raddr1(3) => \raddr1[3]\, raddr1(2) => - \raddr1[2]\, raddr1(1) => \raddr1[1]\, raddr1(0) => - \raddr1[0]\, rfa1(7) => \rfa1[7]\, rfa1(6) => \rfa1[6]\, - rfa1(5) => \rfa1[5]\, rfa1(4) => \rfa1[4]\, rfa1(3) => - \rfa1[3]\, rfa1(2) => \rfa1[2]\, rfa1(1) => \rfa1[1]\, - rfa1(0) => \rfa1[0]\, raddr2(7) => \raddr2[7]\, raddr2(6) - => \raddr2[6]\, raddr2(5) => \raddr2[5]\, raddr2(4) => - \raddr2[4]\, raddr2(3) => \raddr2[3]\, raddr2(2) => - \raddr2[2]\, raddr2(1) => \raddr2[1]\, raddr2(0) => - \raddr2[0]\, rfa2(7) => \rfa2[7]\, rfa2(6) => \rfa2[6]\, - rfa2(5) => \rfa2[5]\, rfa2(4) => \rfa2[4]\, rfa2(3) => - \rfa2[3]\, rfa2(2) => \rfa2[2]\, rfa2(1) => \rfa2[1]\, - rfa2(0) => \rfa2[0]\, waddr(7) => \waddr[7]\, waddr(6) - => \waddr[6]\, waddr(5) => \waddr[5]\, waddr(4) => - \waddr[4]\, waddr(3) => \waddr[3]\, waddr(2) => - \waddr[2]\, waddr(1) => \waddr[1]\, waddr(0) => - \waddr[0]\, wdata(31) => \wdata[31]\, wdata(30) => - \wdata[30]\, wdata(29) => \wdata[29]\, wdata(28) => - \wdata[28]\, wdata(27) => \wdata[27]\, wdata(26) => - \wdata[26]\, wdata(25) => \wdata[25]\, wdata(24) => - \wdata[24]\, wdata(23) => \wdata[23]\, wdata(22) => - \wdata[22]\, wdata(21) => \wdata[21]\, wdata(20) => - \wdata[20]\, wdata(19) => \wdata[19]\, wdata(18) => - \wdata[18]\, wdata(17) => \wdata[17]\, wdata(16) => - \wdata[16]\, wdata(15) => \wdata[15]\, wdata(14) => - \wdata[14]\, wdata(13) => \wdata[13]\, wdata(12) => - \wdata[12]\, wdata(11) => \wdata[11]\, wdata(10) => - \wdata[10]\, wdata(9) => \wdata[9]\, wdata(8) => - \wdata[8]\, wdata(7) => \wdata[7]\, wdata(6) => - \wdata[6]\, wdata(5) => \wdata[5]\, wdata(4) => - \wdata[4]\, wdata(3) => \wdata[3]\, wdata(2) => - \wdata[2]\, wdata(1) => \wdata[1]\, wdata(0) => - \wdata[0]\, flush2_RNIFMGM2 => flush2_RNIFMGM2, - flush2_RNI5I3N7 => flush2_RNI5I3N7, N_984 => N_984, N_980 - => N_980, N_987 => N_987, N_986 => N_986, flush2 => - flush2, flush2_0_0_RNI146O2 => flush2_0_0_RNI146O2, - flush2_0_0_RNI7G6O2 => flush2_0_0_RNI7G6O2, - flush2_0_0_RNIVV5O2 => flush2_0_0_RNIVV5O2, - flush2_0_0_RNITR5O2 => flush2_0_0_RNITR5O2, - flush2_0_0_RNIPJ5O2 => flush2_0_0_RNIPJ5O2, N_981 => - N_981, N_985 => N_985, N_983 => N_983, N_982 => N_982, - N_264_0 => N_264_0, N_262_0 => N_262_0, N_78_0 => N_78_0, - un1_ici => un1_ici, N_10 => N_10, flush_RNIJEN4SI3 => - flush_RNIJEN4SI3, flush_RNIGBB873 => flush_RNIGBB873, - N_270 => N_270, N_269 => N_269, N_267 => N_267, N_259 => - N_259, N_258 => N_258, N_144 => N_144, N_3846 => N_3846, - read_RNIQH64D1 => read_RNIQH64D1, read_RNIQPCQ11 => - read_RNIQPCQ11, read_RNIRO4K31 => read_RNIRO4K31, - read_RNI0IQ7R => read_RNI0IQ7R, read_RNIQFOD21 => - read_RNIQFOD21, read_RNI8DFM31 => read_RNI8DFM31, - read_RNIAQJ831 => read_RNIAQJ831, read_RNI76N8R => - read_RNI76N8R, read_RNI7G7G41 => read_RNI7G7G41, - read_RNIMJHQT => read_RNIMJHQT, read_RNIL633F1 => - read_RNIL633F1, read_RNICKHE91 => read_RNICKHE91, - flush_0_1_RNIOMB27S2 => flush_0_1_RNIOMB27S2, un59_nbo - => un59_nbo, N_3239_i_0 => N_3239_i_0, N_26_0 => N_26, - read_RNIEKS231 => read_RNIEKS231, read_RNIFPFT31 => - read_RNIFPFT31, read_RNIC9O9B1 => read_RNIC9O9B1, - flush_RNIGUM2OH3 => flush_RNIGUM2OH3, read_RNICAQK41 => - read_RNICAQK41, read_RNIQMJI41 => read_RNIQMJI41, - read_RNISLPNU => read_RNISLPNU, read_RNIC70OF1 => - read_RNIC70OF1, read_RNI75LJ31 => read_RNI75LJ31, - read_RNIEEGDD1 => read_RNIEEGDD1, N_12_i_0 => N_12_i_0, - N_16_i_0 => N_16_i_0, flush_0_1_RNIBUA27S2 => - flush_0_1_RNIBUA27S2, flush_0_1_RNIPTA27S2 => - flush_0_1_RNIPTA27S2, N_24 => N_24, N_329 => N_329, N_330 - => N_330, N_3254_0 => N_3254_0, htrans_0_sqmuxa_2 => - htrans_0_sqmuxa_2, N_466 => N_466, hwrite_1_m_0 => - hwrite_1_m_0, N_468 => N_468, N_463 => N_463, N_461 => - N_461, N_459 => N_459, N_458 => N_458, bo_5842_d => - bo_5842_d, N_139 => N_139, N_138 => N_138, un91_nbo_i_0 - => un91_nbo_i_0, werr_2_m_0 => werr_2_m_0, N_467 => - N_467, N_462 => N_462, N_457 => N_457, un60_nbo => - un60_nbo, hbusreq => hbusreq, lb_0_sqmuxa_1 => - lb_0_sqmuxa_1, N_5054 => N_5054, hlock => hlock, - un1_htrans_1_sqmuxa_0 => un1_htrans_1_sqmuxa_0, - bo_5842_d_0 => bo_5842_d_0, N_78 => N_78, N_262 => N_262, - N_264 => N_264, proc3_VCC => leon3s_VCC, N_546 => N_546, - lclk_c => lclk_c, ra_bpmiss_1_0 => ra_bpmiss_1_0, rst => - \rst\, d_m5_0_a3_2 => d_m5_0_a3_2, rst_RNIINI1H => - \rst_RNIINI1H\, rstate_1188n => rstate_1188n, ren1 => - ren1, rfe1 => rfe1, wren => wren, intack => intack, ren2 - => ren2, rfe2 => rfe2, error_i_2 => error_i_2); - - VCC_i : VCC - port map(Y => \VCC\); - - rf0 : regfile_3p - port map(rfa2(7) => \rfa2[7]\, rfa2(6) => \rfa2[6]\, - rfa2(5) => \rfa2[5]\, rfa2(4) => \rfa2[4]\, rfa2(3) => - \rfa2[3]\, rfa2(2) => \rfa2[2]\, rfa2(1) => \rfa2[1]\, - rfa2(0) => \rfa2[0]\, data2(31) => \data2[31]\, data2(30) - => \data2[30]\, data2(29) => \data2[29]\, data2(28) => - \data2[28]\, data2(27) => \data2[27]\, data2(26) => - \data2[26]\, data2(25) => \data2[25]\, data2(24) => - \data2[24]\, data2(23) => \data2[23]\, data2(22) => - \data2[22]\, data2(21) => \data2[21]\, data2(20) => - \data2[20]\, data2(19) => \data2[19]\, data2(18) => - \data2[18]\, data2(17) => \data2[17]\, data2(16) => - \data2[16]\, data2(15) => \data2[15]\, data2(14) => - \data2[14]\, data2(13) => \data2[13]\, data2(12) => - \data2[12]\, data2(11) => \data2[11]\, data2(10) => - \data2[10]\, data2(9) => \data2[9]\, data2(8) => - \data2[8]\, data2(7) => \data2[7]\, data2(6) => - \data2[6]\, data2(5) => \data2[5]\, data2(4) => - \data2[4]\, data2(3) => \data2[3]\, data2(2) => - \data2[2]\, data2(1) => \data2[1]\, data2(0) => - \data2[0]\, raddr2(7) => \raddr2[7]\, raddr2(6) => - \raddr2[6]\, raddr2(5) => \raddr2[5]\, raddr2(4) => - \raddr2[4]\, raddr2(3) => \raddr2[3]\, raddr2(2) => - \raddr2[2]\, raddr2(1) => \raddr2[1]\, raddr2(0) => - \raddr2[0]\, rfa1(7) => \rfa1[7]\, rfa1(6) => \rfa1[6]\, - rfa1(5) => \rfa1[5]\, rfa1(4) => \rfa1[4]\, rfa1(3) => - \rfa1[3]\, rfa1(2) => \rfa1[2]\, rfa1(1) => \rfa1[1]\, - rfa1(0) => \rfa1[0]\, data1(31) => \data1[31]\, data1(30) - => \data1[30]\, data1(29) => \data1[29]\, data1(28) => - \data1[28]\, data1(27) => \data1[27]\, data1(26) => - \data1[26]\, data1(25) => \data1[25]\, data1(24) => - \data1[24]\, data1(23) => \data1[23]\, data1(22) => - \data1[22]\, data1(21) => \data1[21]\, data1(20) => - \data1[20]\, data1(19) => \data1[19]\, data1(18) => - \data1[18]\, data1(17) => \data1[17]\, data1(16) => - \data1[16]\, data1(15) => \data1[15]\, data1(14) => - \data1[14]\, data1(13) => \data1[13]\, data1(12) => - \data1[12]\, data1(11) => \data1[11]\, data1(10) => - \data1[10]\, data1(9) => \data1[9]\, data1(8) => - \data1[8]\, data1(7) => \data1[7]\, data1(6) => - \data1[6]\, data1(5) => \data1[5]\, data1(4) => - \data1[4]\, data1(3) => \data1[3]\, data1(2) => - \data1[2]\, data1(1) => \data1[1]\, data1(0) => - \data1[0]\, waddr(7) => \waddr[7]\, waddr(6) => - \waddr[6]\, waddr(5) => \waddr[5]\, waddr(4) => - \waddr[4]\, waddr(3) => \waddr[3]\, waddr(2) => - \waddr[2]\, waddr(1) => \waddr[1]\, waddr(0) => - \waddr[0]\, wdata(31) => \wdata[31]\, wdata(30) => - \wdata[30]\, wdata(29) => \wdata[29]\, wdata(28) => - \wdata[28]\, wdata(27) => \wdata[27]\, wdata(26) => - \wdata[26]\, wdata(25) => \wdata[25]\, wdata(24) => - \wdata[24]\, wdata(23) => \wdata[23]\, wdata(22) => - \wdata[22]\, wdata(21) => \wdata[21]\, wdata(20) => - \wdata[20]\, wdata(19) => \wdata[19]\, wdata(18) => - \wdata[18]\, wdata(17) => \wdata[17]\, wdata(16) => - \wdata[16]\, wdata(15) => \wdata[15]\, wdata(14) => - \wdata[14]\, wdata(13) => \wdata[13]\, wdata(12) => - \wdata[12]\, wdata(11) => \wdata[11]\, wdata(10) => - \wdata[10]\, wdata(9) => \wdata[9]\, wdata(8) => - \wdata[8]\, wdata(7) => \wdata[7]\, wdata(6) => - \wdata[6]\, wdata(5) => \wdata[5]\, wdata(4) => - \wdata[4]\, wdata(3) => \wdata[3]\, wdata(2) => - \wdata[2]\, wdata(1) => \wdata[1]\, wdata(0) => - \wdata[0]\, raddr1(7) => \raddr1[7]\, raddr1(6) => - \raddr1[6]\, raddr1(5) => \raddr1[5]\, raddr1(4) => - \raddr1[4]\, raddr1(3) => \raddr1[3]\, raddr1(2) => - \raddr1[2]\, raddr1(1) => \raddr1[1]\, raddr1(0) => - \raddr1[0]\, rfe2 => rfe2, ren2 => ren2, rfe1 => rfe1, - lclk_c => lclk_c, wren => wren, ren1 => ren1); - - rst_RNIINI1H : AO1B - port map(A => d_m5_0_a3_2, B => ra_bpmiss_1_0, C => \rst\, - Y => \rst_RNIINI1H\); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - rst_RNI55L3_0 : INV - port map(A => \rst\, Y => rstate_1188n); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity irqmp is - - port( irl_2 : out std_logic_vector(2 to 2); - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - pwdata_1_0 : in std_logic; - irl_3 : in std_logic; - irl_1 : in std_logic; - irl_0_d0 : in std_logic; - irl_0 : inout std_logic_vector(3 downto 0) := (others => 'Z'); - ipend_10 : out std_logic; - pwdata_4 : in std_logic; - pwdata_0_d0 : in std_logic; - pwdata_17 : in std_logic; - pwdata_21 : in std_logic; - pwdata_23 : in std_logic; - pwdata_26 : in std_logic; - pwdata_16 : in std_logic; - pwdata_18 : in std_logic; - pwdata_15 : in std_logic; - pwdata_25 : in std_logic; - pwdata_27 : in std_logic; - pwdata_28 : in std_logic; - pwdata_29 : in std_logic; - pwdata_20 : in std_logic; - pwdata_19 : in std_logic; - pwdata_24 : in std_logic; - pwdata_22 : in std_logic; - iforce_0_11 : out std_logic; - iforce_0_5 : out std_logic; - iforce_0_9 : out std_logic; - iforce_0_4 : out std_logic; - iforce_0_6 : out std_logic; - ipend_m : out std_logic_vector(4 to 4); - prdata_0 : out std_logic; - prdata_13 : out std_logic; - prdata_1 : out std_logic; - iforce_0_m : out std_logic_vector(4 to 4); - ilevel_5 : out std_logic; - ilevel_4 : out std_logic; - ilevel_6 : out std_logic; - ilevel_3 : out std_logic; - ilevel_11 : out std_logic; - ilevel_7 : out std_logic; - ilevel_9 : out std_logic; - prdata_11_m_1_0 : out std_logic_vector(4 to 4); - prdata_13_m_1_0 : out std_logic_vector(4 to 4); - paddr : in std_logic_vector(7 downto 3); - prdata_0_iv_0_0_0_12 : out std_logic; - prdata_0_iv_0_0_0_0 : out std_logic; - prdata_0_iv_0_0_0_13 : out std_logic; - prdata_0_iv_0_0_1_12 : out std_logic; - prdata_0_iv_0_0_1_0 : out std_logic; - prdata_0_iv_0_0_1_13 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 1); - pirq_10 : in std_logic; - pirq_11 : in std_logic; - pirq_13 : in std_logic; - pirq_7 : in std_logic; - pirq_6 : in std_logic; - pirq_0 : in std_logic; - paddr_0 : in std_logic_vector(4 downto 2); - lclk_c : in std_logic; - N_365 : out std_logic; - N_367 : out std_logic; - N_863 : out std_logic; - intack : in std_logic; - N_865 : out std_logic; - N_861 : out std_logic; - N_859 : out std_logic; - N_478 : out std_logic; - N_476 : out std_logic; - N_474 : out std_logic; - N_473 : out std_logic; - N_472 : out std_logic; - N_471 : out std_logic; - N_470 : out std_logic; - N_468 : out std_logic; - N_467 : out std_logic; - N_842 : out std_logic; - N_841 : out std_logic; - N_839 : out std_logic; - N_363 : out std_logic; - N_361 : out std_logic; - N_773 : in std_logic; - N_769 : in std_logic; - rstn : in std_logic; - un1_apbi_0 : in std_logic; - N_749 : in std_logic; - prdata_0_sqmuxa : out std_logic; - N_898 : out std_logic; - prdata_1_sqmuxa : out std_logic - ); - -end irqmp; - -architecture DEF_ARCH of irqmp is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_262_0, N_258, N_258_0, un1_apbi_1, N_257, N_264, - N_261, \ipend_0_i_0_a6[15]\, \ipend_0_i_0_a6_0[15]\, - N_831, \ipend_0_i_0_a6_2_0[9]\, N_830, N_894, - \ipend_0_i_0_a6_1_0[9]\, N_828, \ipend_0_i_0_a6_0[9]\, - \ipend_0_i_0_a6_2[8]\, \ipend_0_i_0_a6_2_0[8]\, - \ipend_0_i_0_a6_1[8]\, \ipend_0_i_0_a6_1_0[8]\, - \ipend_0_i_0_a6[8]\, \ipend_0_i_0_a6_0[8]\, N_818_i, - \ipend_0_i_0_a6_0[2]\, N_820, \ipend_0_i_0_a6_1_0[2]\, - N_403, \ipend_0_i_0_a6_2_0[2]\, \ipend_0_i_a2_0[5]\, - N_876, \ipend_0_i_0_a6_2_0[13]\, N_875, - \ipend_0_i_0_a6_1_0[13]\, \ipend_0_i_0_a6[13]\, - \ipend_0_i_0_a6_0[13]\, \ipend_0_i_0_a6_2[15]\, - \ipend_0_i_0_a6_2_0[15]\, \ipend_0_i_0_a6_1[15]\, - \ipend_0_i_0_a6_1_0[15]\, \ipend[2]\, \ipend[8]\, - \ipend[15]\, \ipend[13]\, \ipend[9]\, \ipend_0_i_0_1[2]\, - \ipend_0_i_0_1[12]\, N_877_i, N_881, N_882, - \ipend_0_i_0_1[6]\, \ipend_RNO_2[6]\, N_410, N_411, - \ipend_0_i_1[5]\, N_359, N_358, N_356, \ipend_0_i_0_1[3]\, - N_371, N_370, N_368, \ipend_0_i_0_1[7]\, \ipend_RNO_2[7]\, - N_374, N_375, \ipend_0_i_0_1[8]\, \ipend_0_i_0_1[4]\, - N_407, N_406, \ipend_RNO_4[4]\, \iforce_0_0_i_0_1[8]\, - N_822, N_413, \iforce_0_RNO_3[8]\, \iforce_0_0_i_0_1[10]\, - N_826, N_416, \iforce_0_RNO_3[10]\, \ipend_0_i_0_1[9]\, - \iforce_0_0_i_0_1[5]\, N_835, N_834, \iforce_0_RNO_3[5]\, - \iforce_0_0_i_0_1[6]\, N_838, N_837, \iforce_0_RNO_3[6]\, - \iforce_0_0_i_0_1[15]\, N_442, N_441, - \iforce_0_RNO_3[15]\, \iforce_0_0_i_0_1[14]\, N_445, - N_444, \iforce_0_RNO_3[14]\, \iforce_0_0_i_0_1[13]\, - N_448, N_447, \iforce_0_RNO_3[13]\, - \iforce_0_0_i_0_1[11]\, N_451, N_450, - \iforce_0_RNO_3[11]\, \iforce_0_0_i_0_1[1]\, N_454, N_453, - \iforce_0_RNO_3[1]\, \ipend_0_i_0_1[14]\, N_458, N_457, - N_455, \ipend_0_i_0_1[11]\, N_462, N_461, N_459, - \iforce_0_0_i_0_1[4]\, N_489, N_488, \iforce_0_RNO_3[4]\, - \iforce_0_0_i_0_1[2]\, N_492, N_491, \iforce_0_RNO_3[2]\, - \ipend_0_i_0_1[15]\, \ipend_0_i_0_1[10]\, N_500, N_499, - N_497, \iforce_0_0_i_0_1[12]\, N_510, N_509, - \iforce_0_RNO_3[12]\, \iforce_0_0_i_0_1[9]\, N_513, N_512, - \iforce_0_RNO_3[9]\, \ipend_0_i_0_1[1]\, N_517, N_516, - N_514, \iforce_0_0_i_0_1[7]\, N_868, N_867, - \iforce_0_RNO_3[7]\, \iforce_0_0_i_0_1[3]\, N_871, N_870, - \iforce_0_RNO_3[3]\, \ipend_0_i_0_1[13]\, - \ipend_0_i_0_a6_2_0[12]\, \ipend_0_i_0_a6_0[12]\, - \ipend[12]\, \ipend_0_i_0_a6_1_0[12]\, \ipend[14]\, N_439, - \iforce_0[14]\, N_438, \ilevel[1]\, N_504, \iforce_0[1]\, - \N_898\, N_502, \prdata_0_iv_0_0_0[2]\, N_463, N_464, - \imask_0[13]\, N_895, N_481, \iforce_0[13]\, N_480, - \prdata_0_iv_0_0_1[15]\, \ilevel[15]\, \prdata_0_sqmuxa\, - N_486, \prdata_0_iv_0_0_0[3]\, N_519, N_520, irl_02_1, - \irl[2]\, N_400, \irl_i_0[0]\, N_885, \irl_0_0_i_0[1]\, - N_311, \irl_0_0_i_a6_1[1]\, N_506, - \prdata_0_iv_0_a2_0[6]_net_1\, \irl_0_1[0]\, N_198, N_384, - \irl_0_0[0]\, \a[14]\, \a_i_0[13]\, \a[15]\, - \irl_1_0_1[0]\, \irl_0_RNO_4[0]\, N_426, \a_1[15]\, - \irl_0_1[2]\, \irl_0_0[2]\, \irl_1_0_1[1]\, N_431_1, - N_422, \irl_1_0_0[1]\, \a_1[14]\, \irl_1_0_1[2]\, N_417, - \irl_1_0_0[2]\, \a_1[13]\, un1_apbi_1_0, - \irl_1_i_a2_1[3]\, N_19, \a_1[11]\, \a_i_0[6]\, \a[7]\, - \irl_0_0_i_a6_0[1]\, N_310, N_271, \irl_0_0_i_1_tz_1[1]\, - \a_i_i[9]\, N_883, N_165, \irl_0_a2_0[2]\, N_614, - \irl_i_a2_0[3]\, \irl_1_0_a2_0_1[1]\, \irl_1_0_a2_0_0[1]\, - N_792, \irl_i_a2_0_0[3]\, \irl_1_0_a2_1[2]\, N_434, - \irl_1_0_3_tz_0[0]\, \a_1_i_0[6]\, \a_1[5]\, \a_1[7]\, - \irl_0_3_tz_0[0]\, \a[5]\, \irl_1_0_a2_1_0_0[0]\, - \a_1[4]\, \irl_0_a2_1_0_0[0]\, \a[4]\, \a_1_0[11]\, - \imask_0[11]\, \ilevel[11]\, \iforce_0[4]\, \imask_0[4]\, - \a_i_0_o6_0[13]\, \ilevel[13]\, \a_1_0_a3_i_0[10]\, - \imask_0[10]\, \a_1_i_s_0_0[9]\, \imask_0[9]\, - \ilevel[9]\, \a_i_i_o2_0_o6_0[10]\, \ilevel[10]\, - \a_1_0[13]\, \a_1_0[14]\, \imask_0[14]\, \ilevel[14]\, - \irl_0_a2_1[0]\, N_402_i, \irl_1_0_a2_1[0]\, \a_1[3]\, - N_435_i, N_306, N_896, \irl_1[2]\, N_419_i, \irl_1_i[0]\, - \irl_0_RNO_2[0]\, \irl_1_0_3[0]\, N_433, N_437, N_386, - N_394, \irl_0_3[0]\, N_404, irl_02_i, N_240, N_892, N_631, - N_290, N_600_i_0, N_874, N_601_i_0, N_923, N_602_i_0, - N_930, N_857, N_856, N_70_i_0, N_515, N_82_i_0, N_919, - N_628_i_0, N_922, N_15_i_0, \ipend_RNO_0[10]\, N_648_i_0, - N_494, N_649_i_0, N_925, N_21_i_0, N_924, N_484, N_483, - N_466, N_465, N_703_i_0, \ipend_RNO_0[11]\, N_704_i_0, - \ipend_RNO_0[14]\, N_705_i_0, N_928, N_708_i_0, N_927, - N_709_i_0, N_926, N_710_i_0, N_931, N_711_i_0, N_917, - N_707_i_0, N_918, N_706_i_0, N_920, N_702_i_0, - \ipend_RNO_0[9]\, N_84_i_0, N_921, N_80_i_0, N_929, - N_76_i_0, \ipend_RNO_0[4]\, N_598_i_0, \ipend_RNO_0[8]\, - N_25_i_0, \ipend_RNO_0[7]\, N_23_i_0, \ipend_RNO_0[3]\, - N_794_i_0, \ipend_RNO_0[5]\, N_285, N_795, \imask_0[8]\, - N_291, \imask_0[12]\, N_298, \ilevel[8]\, N_17, - \imask_0[2]\, \ilevel[2]\, N_383, N_4, N_270, N_13, - \ilevel[12]\, \irl_0_0_i_1_tz[1]\, \irl_1[1]\, N_421, - N_289, N_78_i_0, \ipend_RNO_0[6]\, N_599_i_0, - \ipend_RNO_0[12]\, N_266_i, N_259, N_263, N_627_i_0, - \ipend_RNO_0[2]\, N_884, \irl_0_0_i_a6_1_0[1]\, N_385, - N_521, \imask_0[1]\, imask_0_1_sqmuxa, N_523, - \imask_0[3]\, N_524, N_525, \imask_0[5]\, N_526, - \imask_0[6]\, N_527, \imask_0[7]\, N_528, N_529, N_530, - N_533, N_535, \imask_0[15]\, \un1_temp[4]\, \ipend[4]\, - \temp_0_1[15]\, \iforce_0[15]\, N_350, N_269, \ilevel[3]\, - \ilevel[4]\, \ilevel[7]\, \prdata_1_sqmuxa\, N_414, N_415, - N_418, \irl_0_1_0[0]\, \irl_0_1_0[2]\, \irl_0_1[3]\, N_20, - N_24, \ilevel[5]\, \ilevel[6]\, \ipend[7]\, \ipend[5]\, - \ipend[6]\, \ipend[3]\, \iforce_0[3]\, \iforce_0[7]\, - \iforce_0[8]\, \imask_0_RNO[1]\, \imask_0_RNO[3]\, N_388, - N_389, N_390, \imask_0_RNO[7]\, \imask_0_RNO[8]\, - \imask_0_RNO[9]\, \imask_0_RNO[10]\, N_397, - \imask_0_RNO[15]\, N_827, \iforce_0[9]\, \iforce_0[5]\, - \iforce_0[11]\, N_262, \ipend[10]\, \iforce_0[10]\, - \ipend[1]\, N_886, N_889, N_899, N_904, N_905, N_908, - N_910, \iforce_0_0_i_0_a2_0[15]\, \iforce_0[6]\, - \ipend[11]\, \iforce_0[12]\, \iforce_0[2]\, N_915_i, - N_398, N_534, \imask_0_RNO[12]\, N_532, \irl_0_1[1]\, - \imask_0_RNO[11]\, N_531, \imask_0_RNO[2]\, N_522, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - ipend_10 <= \ipend[11]\; - iforce_0_11 <= \iforce_0[12]\; - iforce_0_5 <= \iforce_0[6]\; - iforce_0_9 <= \iforce_0[10]\; - iforce_0_4 <= \iforce_0[5]\; - iforce_0_6 <= \iforce_0[7]\; - ilevel_5 <= \ilevel[6]\; - ilevel_4 <= \ilevel[5]\; - ilevel_6 <= \ilevel[7]\; - ilevel_3 <= \ilevel[4]\; - ilevel_11 <= \ilevel[12]\; - ilevel_7 <= \ilevel[8]\; - ilevel_9 <= \ilevel[10]\; - prdata_0_sqmuxa <= \prdata_0_sqmuxa\; - N_898 <= \N_898\; - prdata_1_sqmuxa <= \prdata_1_sqmuxa\; - - \r.imask_0_RNO[3]\ : NOR2B - port map(A => rstn, B => N_523, Y => \imask_0_RNO[3]\); - - \r.ipend_RNO[9]\ : NOR3C - port map(A => \ipend_RNO_0[9]\, B => \ipend_0_i_0_1[9]\, C - => rstn, Y => N_702_i_0); - - \r.ipend_0_i_0_a6_2_RNO[2]\ : NOR2 - port map(A => pwdata_0(2), B => pirq_0, Y => - \ipend_0_i_0_a6_2_0[2]\); - - \r.ilevel_RNI84GN[12]\ : OR2A - port map(A => N_13, B => \a_1[14]\, Y => N_417); - - \r.irl_0_RNO_2[0]\ : OR3A - port map(A => N_795, B => N_19, C => N_417, Y => - \irl_0_RNO_2[0]\); - - \r.ipend_RNO[7]\ : NOR3C - port map(A => \ipend_RNO_0[7]\, B => \ipend_0_i_0_1[7]\, C - => rstn, Y => N_25_i_0); - - \r.ipend[10]\ : DFN1 - port map(D => N_15_i_0, CLK => lclk_c, Q => \ipend[10]\); - - \r.ilevel_RNI5U95[14]\ : OR2A - port map(A => \imask_0[14]\, B => \ilevel[14]\, Y => - \a_1_0[14]\); - - \r.iforce_0_RNO_2[10]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(10), Y => - N_416); - - \r.ipend_0_i_o2_0_0[5]\ : OR2 - port map(A => un1_apbi_1, B => N_257, Y => N_258_0); - - \r.ilevel_RNISHGN1[11]\ : NOR2B - port map(A => N_614, B => \irl_i_a2_0[3]\, Y => - \irl_0_a2_0[2]\); - - \r.ipend_RNO_1[7]\ : NOR3C - port map(A => \ipend_RNO_2[7]\, B => N_374, C => N_375, Y - => \ipend_0_i_0_1[7]\); - - \r.ilevel[14]\ : DFN1E1 - port map(D => pwdata_0(14), CLK => lclk_c, E => N_827, Q - => \ilevel[14]\); - - \r.iforce_0_RNO_2[12]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(12), Y => - N_509); - - \r.ipend_0_i_0_a6_2_RNO[8]\ : OR2 - port map(A => pwdata_0(8), B => pirq_6, Y => - \ipend_0_i_0_a6_2_0[8]\); - - \r.iforce_0_RNO_0[13]\ : NOR3C - port map(A => N_448, B => N_447, C => \iforce_0_RNO_3[13]\, - Y => \iforce_0_0_i_0_1[13]\); - - \r.iforce_0_RNIEFHJ[3]\ : OR2B - port map(A => \iforce_0[3]\, B => \N_898\, Y => N_519); - - \r.iforce_0_RNO[2]\ : NOR3C - port map(A => N_925, B => \iforce_0_0_i_0_1[2]\, C => rstn, - Y => N_649_i_0); - - \r.iforce_0_0_i_0_a2[8]\ : OR3B - port map(A => irl_3, B => N_910, C => irl_1, Y => N_929); - - \r.irl_0[3]\ : DFN1 - port map(D => \irl_0_1[3]\, CLK => lclk_c, Q => irl_0(3)); - - \r.ipend_0_i_0_a6_2[9]\ : NAND2 - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[9]\, Y => - N_831); - - \r.ilevel_RNIA6VF[2]\ : OR3B - port map(A => \imask_0[2]\, B => \ilevel[2]\, C => N_383, Y - => N_310); - - \r.ipend_RNO_0[4]\ : OR2 - port map(A => \iforce_0[4]\, B => N_924, Y => - \ipend_RNO_0[4]\); - - \r.iforce_0_RNO_2[3]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(3), Y => - N_870); - - \r.iforce_0_0_i_0_a2[4]\ : OR3A - port map(A => N_905, B => irl_1, C => irl_3, Y => N_924); - - \r.iforce_0[6]\ : DFN1 - port map(D => N_707_i_0, CLK => lclk_c, Q => \iforce_0[6]\); - - \r.imask_0[14]\ : DFN1 - port map(D => N_398, CLK => lclk_c, Q => \imask_0[14]\); - - \r.iforce_0_RNO_1[11]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_25, Y => N_451); - - \r.imask_0_RNIT60B[12]\ : OR2B - port map(A => \imask_0[12]\, B => N_895, Y => N_865); - - \r.iforce_0_RNO_3[13]\ : AO1 - port map(A => N_266_i, B => pwdata_0(13), C => - \iforce_0[13]\, Y => \iforce_0_RNO_3[13]\); - - \r.imask_0_RNIHLO8[15]\ : OA1 - port map(A => \iforce_0[15]\, B => \ipend[15]\, C => - \imask_0[15]\, Y => \temp_0_1[15]\); - - \r.iforce_0_0_i_0_a2[5]\ : OR3A - port map(A => N_908, B => irl_1, C => irl_3, Y => N_920); - - \r.ipend_RNO_4[1]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[1]\, Y => - N_514); - - \r.ipend_RNI9LH8[2]\ : NOR2 - port map(A => \ipend[2]\, B => \iforce_0[2]\, Y => N_383); - - \r.ipend_RNO_2[4]\ : OR3 - port map(A => N_258_0, B => N_261, C => pwdata_0(4), Y => - N_407); - - \r.ipend_RNO_1[15]\ : NOR3C - port map(A => \ipend_0_i_0_a6[15]\, B => - \ipend_0_i_0_a6_1[15]\, C => \ipend_0_i_0_a6_2[15]\, Y - => \ipend_0_i_0_1[15]\); - - \r.ipend_RNIUQ2A[4]\ : OR2B - port map(A => \ipend[4]\, B => \prdata_1_sqmuxa\, Y => - ipend_m(4)); - - \r.iforce_0_RNO_3[8]\ : AO1 - port map(A => N_266_i, B => pwdata_0(8), C => \iforce_0[8]\, - Y => \iforce_0_RNO_3[8]\); - - \r.ipend_RNISQ2A[2]\ : OR2B - port map(A => \ipend[2]\, B => \prdata_1_sqmuxa\, Y => - N_464); - - \r.ipend_RNIRQ2A[1]\ : OR2B - port map(A => \ipend[1]\, B => \prdata_1_sqmuxa\, Y => - N_502); - - \r.irl_0_RNO_2[2]\ : OR3A - port map(A => N_19, B => \a_1[11]\, C => N_434, Y => - \irl_1_0_a2_1[2]\); - - \r.ipend_RNID0DC[12]\ : OR2B - port map(A => \ipend[12]\, B => \prdata_1_sqmuxa\, Y => - N_863); - - \r.ipend_0_i_0_a6_2[15]\ : OR2A - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[15]\, Y => - \ipend_0_i_0_a6_2[15]\); - - \r.iforce_0_RNIJ3IJ[8]\ : OR2B - port map(A => \iforce_0[8]\, B => \N_898\, Y => N_467); - - \r.ilevel_RNIO9NB_0[10]\ : OR2B - port map(A => \a_i_i_o2_0_o6_0[10]\, B => N_290, Y => N_631); - - \r.iforce_0_RNILK3F[15]\ : OR2B - port map(A => \iforce_0[15]\, B => \N_898\, Y => N_483); - - \r.ipend_RNO_1[3]\ : NOR3C - port map(A => N_371, B => N_370, C => N_368, Y => - \ipend_0_i_0_1[3]\); - - \r.ilevel_RNIEEVF_0[3]\ : OR2A - port map(A => N_269, B => \ilevel[3]\, Y => \a_1[3]\); - - \r.ipend_RNIGCDC[15]\ : OR2B - port map(A => \ipend[15]\, B => \prdata_1_sqmuxa\, Y => - N_484); - - \r.ipend_0_i_0_a6_2[2]\ : NAND2 - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[2]\, Y => - N_403); - - \r.imask_0_RNO[14]\ : NOR2B - port map(A => rstn, B => N_534, Y => N_398); - - \r.ilevel_RNIKL631[11]\ : AO1 - port map(A => N_631, B => N_198, C => N_883, Y => N_915_i); - - \r.ipend_0_i_o2[5]\ : NOR2 - port map(A => N_258_0, B => N_261, Y => N_264); - - \r.imask_0_RNIVE0B[14]\ : OR2B - port map(A => \imask_0[14]\, B => N_895, Y => N_439); - - \r.irl_0_RNO_2[1]\ : AO1A - port map(A => N_418, B => N_415, C => N_414, Y => N_421); - - \r.iforce_0_RNO_3[6]\ : AO1 - port map(A => N_266_i, B => pwdata_0(6), C => \iforce_0[6]\, - Y => \iforce_0_RNO_3[6]\); - - \r.iforce_0_0_i_0_a2[11]\ : OR2B - port map(A => \iforce_0_0_i_0_a2_0[15]\, B => N_904, Y => - N_927); - - \r.ipend_RNIRRD6[10]\ : OR2 - port map(A => \ipend[10]\, B => \iforce_0[10]\, Y => N_290); - - \r.ipend_0_i_0_a6_1_RNO[9]\ : AND2 - port map(A => pwdata_0(9), B => pirq_7, Y => - \ipend_0_i_0_a6_1_0[9]\); - - \r.iforce_0_RNO[6]\ : NOR3C - port map(A => N_918, B => \iforce_0_0_i_0_1[6]\, C => rstn, - Y => N_707_i_0); - - \r.iforce_0[1]\ : DFN1 - port map(D => N_705_i_0, CLK => lclk_c, Q => \iforce_0[1]\); - - \r.imask_0[2]\ : DFN1 - port map(D => \imask_0_RNO[2]\, CLK => lclk_c, Q => - \imask_0[2]\); - - \r.ilevel[10]\ : DFN1E1 - port map(D => pwdata_0(10), CLK => lclk_c, E => N_827, Q - => \ilevel[10]\); - - \r.ilevel_RNIIMVF_0[4]\ : OR3B - port map(A => \un1_temp[4]\, B => \imask_0[4]\, C => - \ilevel[4]\, Y => \a_1[4]\); - - \r.imask_0[15]\ : DFN1 - port map(D => \imask_0_RNO[15]\, CLK => lclk_c, Q => - \imask_0[15]\); - - \r.ipend_RNO_1[2]\ : NOR3C - port map(A => N_403, B => N_820, C => N_818_i, Y => - \ipend_0_i_0_1[2]\); - - \r.iforce_0_RNO[7]\ : NOR3C - port map(A => N_930, B => \iforce_0_0_i_0_1[7]\, C => rstn, - Y => N_602_i_0); - - \r.ilevel_RNI09H4A[14]\ : AO1D - port map(A => \irl_0_0_i_1_tz[1]\, B => N_311, C => - \irl_0_0_i_0[1]\, Y => N_240); - - \r.iforce_0_RNO[15]\ : NOR3B - port map(A => \iforce_0_0_i_0_1[15]\, B => rstn, C => N_917, - Y => N_711_i_0); - - \r.iforce_0_0_i_0_a2[12]\ : OR3B - port map(A => irl_3, B => N_905, C => irl_1, Y => N_922); - - \r.ipend_RNO_0[6]\ : OR2 - port map(A => \iforce_0[6]\, B => N_918, Y => - \ipend_RNO_0[6]\); - - \r.ipend[1]\ : DFN1 - port map(D => N_70_i_0, CLK => lclk_c, Q => \ipend[1]\); - - \r.ilevel_RNIQ0OR[8]\ : NOR2A - port map(A => N_631, B => N_165, Y => N_614); - - \r.imask_0[11]\ : DFN1 - port map(D => \imask_0_RNO[11]\, CLK => lclk_c, Q => - \imask_0[11]\); - - \r.ipend_RNIBPH8[3]\ : NOR2 - port map(A => \ipend[3]\, B => \iforce_0[3]\, Y => N_886); - - \r.iforce_0_RNO_3[3]\ : AO1 - port map(A => N_266_i, B => pwdata_0(3), C => \iforce_0[3]\, - Y => \iforce_0_RNO_3[3]\); - - \r.imask_0[6]\ : DFN1 - port map(D => N_390, CLK => lclk_c, Q => \imask_0[6]\); - - \r.ilevel_RNI8INQ1[14]\ : OR3B - port map(A => \a[15]\, B => N_915_i, C => \a[14]\, Y => - N_311); - - \prdata_0_iv_0_a2_0[6]\ : OA1 - port map(A => N_885, B => N_892, C => N_896, Y => \N_898\); - - \r.ilevel_RNI4SFN[12]\ : NOR2B - port map(A => \a_1[13]\, B => N_13, Y => N_431_1); - - \r.iforce_0_RNO[1]\ : NOR3B - port map(A => \iforce_0_0_i_0_1[1]\, B => rstn, C => N_928, - Y => N_705_i_0); - - \r.iforce_0_RNO_1[4]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_18, Y => N_489); - - \r.ipend_RNIVQ2A[5]\ : OR2B - port map(A => \ipend[5]\, B => \prdata_1_sqmuxa\, Y => - N_365); - - \r.ipend[8]\ : DFN1 - port map(D => N_598_i_0, CLK => lclk_c, Q => \ipend[8]\); - - \r.ipend[6]\ : DFN1 - port map(D => N_78_i_0, CLK => lclk_c, Q => \ipend[6]\); - - \r.ilevel_RNIUE0G[7]\ : OR3B - port map(A => \imask_0[7]\, B => \ilevel[7]\, C => N_350, Y - => \a[7]\); - - \r.iforce_0_RNO_1[10]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_24, Y => - N_826); - - \r.ipend_RNILDI8[8]\ : OR2 - port map(A => \ipend[8]\, B => \iforce_0[8]\, Y => N_291); - - \r.imask_0_RNO_0[7]\ : MX2 - port map(A => \imask_0[7]\, B => pwdata_0(7), S => - imask_0_1_sqmuxa, Y => N_527); - - \r.ilevel[12]\ : DFN1E1 - port map(D => pwdata_0(12), CLK => lclk_c, E => N_827, Q - => \ilevel[12]\); - - \r.ipend_0_i_0_a6_1[13]\ : NAND2 - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[13]\, Y => - N_875); - - \r.ilevel_RNIEEVF[3]\ : OR2B - port map(A => \ilevel[3]\, B => N_269, Y => N_271); - - \r.iforce_0_RNO_1[12]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_26, Y => N_510); - - \r.iforce_0_0_i_0_a2_1[9]\ : NOR2A - port map(A => irl_0_d0, B => N_899, Y => N_904); - - \r.ipend_RNIBOCC[10]\ : OR2B - port map(A => \ipend[10]\, B => \prdata_1_sqmuxa\, Y => - N_476); - - \r.iforce_0_RNO[10]\ : NOR3C - port map(A => N_921, B => \iforce_0_0_i_0_1[10]\, C => rstn, - Y => N_84_i_0); - - \r.imask_0_RNO[12]\ : NOR2B - port map(A => rstn, B => N_532, Y => \imask_0_RNO[12]\); - - \r.imask_0[10]\ : DFN1 - port map(D => \imask_0_RNO[10]\, CLK => lclk_c, Q => - \imask_0[10]\); - - \r.ilevel[15]\ : DFN1E1 - port map(D => pwdata_0(15), CLK => lclk_c, E => N_827, Q - => \ilevel[15]\); - - \r.ipend_0_i_0_a6_RNO[9]\ : NOR2A - port map(A => pirq_7, B => \ipend[9]\, Y => - \ipend_0_i_0_a6_0[9]\); - - \r.ilevel_RNICIOB_0[15]\ : NOR2A - port map(A => \temp_0_1[15]\, B => \ilevel[15]\, Y => - \a_1[15]\); - - \r.ilevel_RNIQ96J5[1]\ : AO1B - port map(A => \irl_0_3_tz_0[0]\, B => \irl_0_a2_1[0]\, C - => N_404, Y => \irl_0_3[0]\); - - \r.ipend_RNI1R2A[7]\ : OR2B - port map(A => \ipend[7]\, B => \prdata_1_sqmuxa\, Y => - N_859); - - \r.iforce_0_RNIDBHJ[2]\ : OR2B - port map(A => \iforce_0[2]\, B => \N_898\, Y => N_463); - - \r.ilevel_RNI7IEC[2]\ : OR2B - port map(A => \ilevel[2]\, B => \prdata_0_sqmuxa\, Y => - N_465); - - \r.ilevel_RNI8LVV_0[4]\ : OR2A - port map(A => \a[4]\, B => \a[5]\, Y => N_385); - - \r.iforce_0_RNIHK3F[11]\ : OR2B - port map(A => \iforce_0[11]\, B => \N_898\, Y => N_839); - - \r.imask_0_RNO_0[6]\ : MX2 - port map(A => \imask_0[6]\, B => pwdata_0(6), S => - imask_0_1_sqmuxa, Y => N_526); - - \r.iforce_0_RNO_0[11]\ : NOR3C - port map(A => N_451, B => N_450, C => \iforce_0_RNO_3[11]\, - Y => \iforce_0_0_i_0_1[11]\); - - \r.ilevel_RNI6V0G_0[9]\ : OR2B - port map(A => \a_1_i_s_0_0[9]\, B => N_285, Y => N_19); - - \r.irl_0_RNO[2]\ : MX2C - port map(A => \irl_1[2]\, B => \irl[2]\, S => irl_02_i, Y - => \irl_0_1_0[2]\); - - \r.imask_0_RNIC5LB[2]\ : OR2B - port map(A => \imask_0[2]\, B => N_895, Y => N_466); - - \r.iforce_0_RNO[11]\ : NOR3C - port map(A => N_927, B => \iforce_0_0_i_0_1[11]\, C => rstn, - Y => N_708_i_0); - - \r.imask_0_RNI3T45[4]\ : NOR2A - port map(A => \imask_0[4]\, B => paddr(7), Y => - prdata_11_m_1_0(4)); - - \r.iforce_0_0_i_0_a2_0[10]\ : NOR2 - port map(A => irl_0_d0, B => N_899, Y => N_910); - - \r.iforce_0[15]\ : DFN1 - port map(D => N_711_i_0, CLK => lclk_c, Q => \iforce_0[15]\); - - \r.ipend_0_i_0_a6_1_RNO[2]\ : NOR2A - port map(A => pwdata_0(2), B => pirq_0, Y => - \ipend_0_i_0_a6_1_0[2]\); - - \r.imask_0[9]\ : DFN1 - port map(D => \imask_0_RNO[9]\, CLK => lclk_c, Q => - \imask_0[9]\); - - \r.ipend_0_i_0_a6_2_RNO[15]\ : OR2 - port map(A => pwdata_0(15), B => pirq_13, Y => - \ipend_0_i_0_a6_2_0[15]\); - - \r.imask_0[3]\ : DFN1 - port map(D => \imask_0_RNO[3]\, CLK => lclk_c, Q => - \imask_0[3]\); - - \r.ipend_RNO_0[7]\ : OR2 - port map(A => \iforce_0[7]\, B => N_930, Y => - \ipend_RNO_0[7]\); - - \r.iforce_0_RNO_3[11]\ : AO1 - port map(A => N_266_i, B => pwdata_0(11), C => - \iforce_0[11]\, Y => \iforce_0_RNO_3[11]\); - - \v.ilevel_0_sqmuxa_i_i_o2\ : OR2 - port map(A => paddr(7), B => paddr_0(3), Y => N_259); - - \r.ipend_RNO_2[10]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(10), Y => - N_500); - - \r.iforce_0_RNO[4]\ : NOR3C - port map(A => N_924, B => \iforce_0_0_i_0_1[4]\, C => rstn, - Y => N_21_i_0); - - \r.irl_0_RNO_3[2]\ : OR2 - port map(A => N_417, B => \irl_1_0_0[2]\, Y => - \irl_1_0_1[2]\); - - \r.iforce_0_RNO_0[2]\ : NOR3C - port map(A => N_492, B => N_491, C => \iforce_0_RNO_3[2]\, - Y => \iforce_0_0_i_0_1[2]\); - - GND_i : GND - port map(Y => \GND\); - - \r.ipend_0_i_0_a6_1_RNO[8]\ : OR2A - port map(A => pwdata_0(8), B => pirq_6, Y => - \ipend_0_i_0_a6_1_0[8]\); - - \r.imask_0[13]\ : DFN1 - port map(D => N_397, CLK => lclk_c, Q => \imask_0[13]\); - - \r.iforce_0_RNO_1[9]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_23, Y => N_513); - - \r.ipend_RNO_0[5]\ : OR2 - port map(A => \iforce_0[5]\, B => N_920, Y => - \ipend_RNO_0[5]\); - - \r.ipend_0_i_0_a6_1_RNO[13]\ : NOR2A - port map(A => pwdata_0(13), B => pirq_11, Y => - \ipend_0_i_0_a6_1_0[13]\); - - \r.ipend[13]\ : DFN1 - port map(D => N_600_i_0, CLK => lclk_c, Q => \ipend[13]\); - - \r.iforce_0_0_i_0_a2_1[15]\ : NOR2A - port map(A => irl_0_d0, B => N_889, Y => N_908); - - \r.ipend_RNO_0[12]\ : OR2 - port map(A => \iforce_0[12]\, B => N_922, Y => - \ipend_RNO_0[12]\); - - \r.ipend_RNO_4[12]\ : OR3A - port map(A => \ipend_0_i_0_a6_2_0[12]\, B => N_258_0, C => - N_261, Y => N_882); - - \r.ipend_RNO[11]\ : NOR3C - port map(A => \ipend_RNO_0[11]\, B => \ipend_0_i_0_1[11]\, - C => rstn, Y => N_703_i_0); - - \r.irl_0_RNO_1[3]\ : NOR3B - port map(A => N_19, B => \a_1[13]\, C => \a_1[11]\, Y => - \irl_1_i_a2_1[3]\); - - \r.ipend_RNO_3[1]\ : OR3A - port map(A => pwdata_0(1), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_516); - - \r.ipend[4]\ : DFN1 - port map(D => N_76_i_0, CLK => lclk_c, Q => \ipend[4]\); - - \r.iforce_0_RNO[3]\ : NOR3C - port map(A => N_923, B => \iforce_0_0_i_0_1[3]\, C => rstn, - Y => N_601_i_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.irl_0_RNO[1]\ : AO1B - port map(A => \irl_1[1]\, B => irl_02_1, C => N_240, Y => - \irl_0_1[1]\); - - \r.iforce_0_RNO_3[2]\ : AO1 - port map(A => N_266_i, B => pwdata_0(2), C => \iforce_0[2]\, - Y => \iforce_0_RNO_3[2]\); - - \r.ilevel_RNIOO0F1[15]\ : OR2 - port map(A => N_384, B => \irl_0_0[2]\, Y => \irl_0_1[2]\); - - \r.iforce_0_0_i_0_a2[15]\ : NOR2B - port map(A => N_908, B => \iforce_0_0_i_0_a2_0[15]\, Y => - N_917); - - \r.ipend_RNO_2[14]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(14), Y => - N_458); - - \r.iforce_0_RNO_1[8]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_22, Y => - N_822); - - \r.ipend_RNO_1[6]\ : NOR3C - port map(A => \ipend_RNO_2[6]\, B => N_410, C => N_411, Y - => \ipend_0_i_0_1[6]\); - - \r.ilevel_RNIQ60G[6]\ : OR2A - port map(A => \ilevel[6]\, B => N_24, Y => \a_i_0[6]\); - - \r.ilevel_RNILLVA[11]\ : OR2B - port map(A => \ilevel[11]\, B => \prdata_0_sqmuxa\, Y => - N_841); - - \r.iforce_0[11]\ : DFN1 - port map(D => N_708_i_0, CLK => lclk_c, Q => \iforce_0[11]\); - - \r.ipend_RNO_0[9]\ : OR2 - port map(A => \iforce_0[9]\, B => N_919, Y => - \ipend_RNO_0[9]\); - - \r.ipend_RNITQ2A[3]\ : OR2B - port map(A => \ipend[3]\, B => \prdata_1_sqmuxa\, Y => - N_520); - - \r.ipend_RNO_3[3]\ : OR3A - port map(A => pwdata_0(3), B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_370); - - \r.ipend_RNO[13]\ : NOR3C - port map(A => N_874, B => \ipend_0_i_0_1[13]\, C => rstn, Y - => N_600_i_0); - - \r.ilevel_RNIGKGN[15]\ : OR2B - port map(A => \a_i_0[13]\, B => \a[15]\, Y => \irl_0_0[2]\); - - \r.iforce_0[2]\ : DFN1 - port map(D => N_649_i_0, CLK => lclk_c, Q => \iforce_0[2]\); - - \r.ilevel_RNI42OB[13]\ : OR2B - port map(A => \a_1_0[13]\, B => N_306, Y => \a_1[13]\); - - \r.iforce_0_0_i_0_a2_2[8]\ : NOR3A - port map(A => paddr(7), B => paddr(5), C => paddr_0(3), Y - => N_892); - - \r.ipend_RNO_3[10]\ : OR3A - port map(A => pwdata_0(10), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_499); - - \r.iforce_0_0_i_0_m2[8]\ : MX2C - port map(A => paddr(5), B => paddr(7), S => paddr(3), Y => - N_263); - - \r.irl_0_RNO_1[1]\ : NOR2B - port map(A => \irl_1_0_a2_0_0[1]\, B => N_431_1, Y => - \irl_1_0_a2_0_1[1]\); - - \r.irl_0_RNO[0]\ : MX2C - port map(A => \irl_1_i[0]\, B => \irl_i_0[0]\, S => - irl_02_i, Y => \irl_0_1_0[0]\); - - \r.imask_0[5]\ : DFN1 - port map(D => N_389, CLK => lclk_c, Q => \imask_0[5]\); - - \r.iforce_0_RNO_2[14]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(14), Y => - N_444); - - \r.ipend_0_i_a2_0[5]\ : OR2B - port map(A => paddr_0(2), B => N_885, Y => - \ipend_0_i_a2_0[5]\); - - \r.ipend_RNO_0[1]\ : OR2A - port map(A => N_928, B => \iforce_0[1]\, Y => N_515); - - \r.iforce_0_RNO_2[6]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(6), Y => - N_837); - - \r.ilevel_RNICIOB[15]\ : OR2B - port map(A => \ilevel[15]\, B => \temp_0_1[15]\, Y => - \a[15]\); - - \r.iforce_0_RNO_2[2]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(2), Y => - N_491); - - prdata_0_sqmuxa_0_a2_0_a2 : NOR2 - port map(A => N_884, B => N_257, Y => \prdata_0_sqmuxa\); - - \r.iforce_0_0_i_0_a2_2[9]\ : OR2 - port map(A => irl_0(2), B => intack, Y => N_899); - - \r.iforce_0[8]\ : DFN1 - port map(D => N_80_i_0, CLK => lclk_c, Q => \iforce_0[8]\); - - \r.ipend[12]\ : DFN1 - port map(D => N_599_i_0, CLK => lclk_c, Q => \ipend[12]\); - - \r.iforce_0_RNO_0[10]\ : NOR3C - port map(A => N_826, B => N_416, C => \iforce_0_RNO_3[10]\, - Y => \iforce_0_0_i_0_1[10]\); - - \r.imask_0_RNO[1]\ : NOR2B - port map(A => rstn, B => N_521, Y => \imask_0_RNO[1]\); - - \r.ipend_RNO_3[14]\ : OR3A - port map(A => pwdata_0(14), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_457); - - \r.ilevel_RNIHJ3O[1]\ : AOI1B - port map(A => \ilevel[1]\, B => \prdata_0_sqmuxa\, C => - N_504, Y => prdata_0_iv_0_0_1_0); - - \r.iforce_0_RNO_0[8]\ : NOR3C - port map(A => N_822, B => N_413, C => \iforce_0_RNO_3[8]\, - Y => \iforce_0_0_i_0_1[8]\); - - \r.iforce_0_RNO_0[12]\ : NOR3C - port map(A => N_510, B => N_509, C => \iforce_0_RNO_3[12]\, - Y => \iforce_0_0_i_0_1[12]\); - - \r.iforce_0_0_i_0_a2[14]\ : OR2B - port map(A => \iforce_0_0_i_0_a2_0[15]\, B => N_905, Y => - N_931); - - \r.iforce_0_RNO_1[6]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_20, Y => - N_838); - - \r.iforce_0[13]\ : DFN1 - port map(D => N_709_i_0, CLK => lclk_c, Q => \iforce_0[13]\); - - \r.imask_0_RNIS20B[11]\ : OR2B - port map(A => \imask_0[11]\, B => N_895, Y => N_842); - - \r.ipend_RNO_1[13]\ : NOR3C - port map(A => \ipend_0_i_0_a6[13]\, B => N_875, C => N_876, - Y => \ipend_0_i_0_1[13]\); - - \r.ipend[7]\ : DFN1 - port map(D => N_25_i_0, CLK => lclk_c, Q => \ipend[7]\); - - \r.iforce_0_RNO_3[7]\ : AO1 - port map(A => N_266_i, B => pwdata_0(7), C => \iforce_0[7]\, - Y => \iforce_0_RNO_3[7]\); - - \r.iforce_0[9]\ : DFN1 - port map(D => N_82_i_0, CLK => lclk_c, Q => \iforce_0[9]\); - - \r.iforce_0_RNO_3[10]\ : AO1 - port map(A => N_266_i, B => pwdata_0(10), C => - \iforce_0[10]\, Y => \iforce_0_RNO_3[10]\); - - \r.ilevel_RNI8RPB3[7]\ : NOR2 - port map(A => \irl_0_0_i_1_tz_1[1]\, B => - \irl_0_0_i_a6_1_0[1]\, Y => \irl_0_0_i_1_tz[1]\); - - \r.ilevel[3]\ : DFN1E1 - port map(D => pwdata_1_2, CLK => lclk_c, E => N_827, Q => - \ilevel[3]\); - - \r.imask_0_RNO[8]\ : NOR2B - port map(A => rstn, B => N_528, Y => \imask_0_RNO[8]\); - - \r.iforce_0_RNO_3[12]\ : AO1 - port map(A => N_266_i, B => pwdata_0(12), C => - \iforce_0[12]\, Y => \iforce_0_RNO_3[12]\); - - \r.ipend_RNO_1[10]\ : NOR3C - port map(A => N_500, B => N_499, C => N_497, Y => - \ipend_0_i_0_1[10]\); - - \r.ilevel_RNI258J1[8]\ : NOR2A - port map(A => N_614, B => N_384, Y => N_404); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.ilevel_RNI2HOR[11]\ : NOR2B - port map(A => \a_i_i[9]\, B => N_198, Y => \irl_i_a2_0[3]\); - - \r.iforce_0_0_i_0_a2[10]\ : OR2B - port map(A => N_910, B => \iforce_0_0_i_0_a2_0[15]\, Y => - N_921); - - \r.ipend_0_i_0_a6_2[8]\ : OR2A - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[8]\, Y => - \ipend_0_i_0_a6_2[8]\); - - \r.ilevel_RNIG4UV[1]\ : OR3B - port map(A => \ilevel[1]\, B => N_310, C => N_4, Y => - N_402_i); - - \r.iforce_0_RNO_3[5]\ : AO1 - port map(A => N_266_i, B => pwdata_0(5), C => \iforce_0[5]\, - Y => \iforce_0_RNO_3[5]\); - - \r.ipend_RNO_4[6]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(6), Y => - N_411); - - \r.ipend_RNO_2[6]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[6]\, Y => - \ipend_RNO_2[6]\); - - \r.iforce_0[4]\ : DFN1 - port map(D => N_21_i_0, CLK => lclk_c, Q => \iforce_0[4]\); - - \r.ipend_RNO_2[3]\ : OR3 - port map(A => N_258_0, B => N_261, C => pwdata_0(3), Y => - N_371); - - \r.irl_0_RNO_4[0]\ : OR2 - port map(A => \a_1[14]\, B => \a_1[13]\, Y => - \irl_0_RNO_4[0]\); - - \r.imask_0_RNI06OL1[3]\ : OR3C - port map(A => N_857, B => N_856, C => - \prdata_0_iv_0_0_0[3]\, Y => prdata_1); - - prdata_0_sqmuxa_0_a2_0_o2 : OR2 - port map(A => paddr(6), B => paddr(4), Y => N_257); - - \r.ilevel[4]\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => N_827, Q => - \ilevel[4]\); - - \r.iforce_0_0_i_0_a2_0[15]\ : NOR2B - port map(A => irl_3, B => irl_1, Y => - \iforce_0_0_i_0_a2_0[15]\); - - \r.imask_0_RNIG5LB[6]\ : OR2B - port map(A => \imask_0[6]\, B => N_895, Y => N_363); - - \r.iforce_0_RNO_2[8]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(8), Y => - N_413); - - \r.ipend_RNO_1[14]\ : NOR3C - port map(A => N_458, B => N_457, C => N_455, Y => - \ipend_0_i_0_1[14]\); - - \r.ilevel_RNISHNB_0[11]\ : NOR2B - port map(A => \a_1_0[11]\, B => N_289, Y => \a_1[11]\); - - \r.irl_0_RNO_7[0]\ : AO1B - port map(A => \a_1[3]\, B => N_435_i, C => - \irl_1_0_a2_1_0_0[0]\, Y => \irl_1_0_a2_1[0]\); - - \r.iforce_0_0_i_0_a2[3]\ : OR3B - port map(A => irl_1, B => N_904, C => irl_3, Y => N_923); - - \r.ipend_RNO_3[5]\ : OR3A - port map(A => pwdata_0(5), B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_358); - - \r.ipend_0_i_0_a6_RNO[8]\ : OR2 - port map(A => pirq_6, B => \ipend[8]\, Y => - \ipend_0_i_0_a6_0[8]\); - - \comb.un1_apbi_1_0\ : NOR2 - port map(A => N_749, B => un1_apbi_0, Y => un1_apbi_1_0); - - \r.irl_0_RNO_7[1]\ : NOR2 - port map(A => \a_1[14]\, B => \a_1[15]\, Y => - \irl_1_0_0[1]\); - - \r.ipend_RNO_2[11]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(11), Y => - N_462); - - \r.imask_0_RNO_0[4]\ : MX2 - port map(A => \imask_0[4]\, B => pwdata_0(4), S => - imask_0_1_sqmuxa, Y => N_524); - - \r.ipend_RNO_1[5]\ : NOR3C - port map(A => N_359, B => N_358, C => N_356, Y => - \ipend_0_i_1[5]\); - - \r.imask_0_RNO[4]\ : NOR2B - port map(A => rstn, B => N_524, Y => N_388); - - \r.ipend_RNI2R2A[8]\ : OR2B - port map(A => \ipend[8]\, B => \prdata_1_sqmuxa\, Y => - N_468); - - \r.ilevel_RNIO9NB[10]\ : OR2B - port map(A => \a_1_0_a3_i_0[10]\, B => N_290, Y => N_795); - - \r.ilevel[6]\ : DFN1E1 - port map(D => pwdata_4, CLK => lclk_c, E => N_827, Q => - \ilevel[6]\); - - \r.irl_0[1]\ : DFN1 - port map(D => \irl_0_1[1]\, CLK => lclk_c, Q => irl_0(1)); - - \r.iforce_0_RNO_3[4]\ : AO1 - port map(A => N_266_i, B => pwdata_0(4), C => \iforce_0[4]\, - Y => \iforce_0_RNO_3[4]\); - - \r.iforce_0_RNO[13]\ : NOR3B - port map(A => \iforce_0_0_i_0_1[13]\, B => rstn, C => N_926, - Y => N_709_i_0); - - \r.ipend_0_i_0_a6_1[15]\ : OR2A - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[15]\, Y => - \ipend_0_i_0_a6_1[15]\); - - \r.ilevel[8]\ : DFN1E1 - port map(D => pwdata_0(8), CLK => lclk_c, E => N_827, Q => - \ilevel[8]\); - - \r.imask_0_RNISTNL1[2]\ : OR3C - port map(A => N_466, B => N_465, C => - \prdata_0_iv_0_0_0[2]\, Y => prdata_0); - - \r.ipend_0_i_0_a6[15]\ : OR2 - port map(A => N_264, B => \ipend_0_i_0_a6_0[15]\, Y => - \ipend_0_i_0_a6[15]\); - - \comb.un1_apbi_1\ : OR3C - port map(A => N_769, B => N_773, C => un1_apbi_1_0, Y => - un1_apbi_1); - - \r.irl_0_RNO_5[1]\ : OR2B - port map(A => \a_1[3]\, B => N_17, Y => N_415); - - \r.irl_0_RNO_4[2]\ : OR2A - port map(A => \a_1[13]\, B => \a_1[15]\, Y => - \irl_1_0_0[2]\); - - \r.ilevel_RNIKAH63[15]\ : NOR3C - port map(A => \irl_i_a2_0_0[3]\, B => \irl_i_a2_0[3]\, C - => N_404, Y => N_400); - - \r.ipend_RNI0R2A[6]\ : OR2B - port map(A => \ipend[6]\, B => \prdata_1_sqmuxa\, Y => - N_361); - - \r.ipend[3]\ : DFN1 - port map(D => N_23_i_0, CLK => lclk_c, Q => \ipend[3]\); - - \r.imask_0_RNIH5LB[7]\ : OR2B - port map(A => \imask_0[7]\, B => N_895, Y => N_861); - - \r.imask_0[4]\ : DFN1 - port map(D => N_388, CLK => lclk_c, Q => \imask_0[4]\); - - \r.iforce_0_RNO_1[14]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_28, Y => - N_445); - - \r.ilevel_RNIOU831_0[14]\ : NOR3A - port map(A => \a[15]\, B => \a[14]\, C => \a_i_0[13]\, Y - => N_506); - - \r.iforce_0_RNO_2[9]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(9), Y => - N_512); - - prdata_2_sqmuxa_0_a2_0_a2_0 : NOR2 - port map(A => N_257, B => paddr_0(2), Y => N_896); - - \r.ipend_RNIAPGB[5]\ : OAI1 - port map(A => \iforce_0[5]\, B => \ipend[5]\, C => - \imask_0[5]\, Y => N_20); - - \r.iforce_0_RNO_2[15]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(15), Y => - N_441); - - \r.irl_0_RNO_0[3]\ : NOR3B - port map(A => \irl_1_i_a2_1[3]\, B => N_437, C => \a_1[15]\, - Y => N_433); - - \r.ipend_RNO_3[11]\ : OR3A - port map(A => pwdata_0(11), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_461); - - \r.ipend_RNO_1[9]\ : NOR3C - port map(A => N_831, B => N_830, C => N_828, Y => - \ipend_0_i_0_1[9]\); - - \r.ipend_RNI3R2A[9]\ : OR2B - port map(A => \ipend[9]\, B => \prdata_1_sqmuxa\, Y => - N_472); - - \r.iforce_0_0_i_0_o2_0[8]\ : NOR3C - port map(A => N_259, B => N_263, C => N_262_0, Y => N_266_i); - - \r.iforce_0_RNO_0[5]\ : NOR3C - port map(A => N_835, B => N_834, C => \iforce_0_RNO_3[5]\, - Y => \iforce_0_0_i_0_1[5]\); - - \r.iforce_0_0_i_0_a2[1]\ : NOR3A - port map(A => N_904, B => irl_1, C => irl_3, Y => N_928); - - \r.ipend_0_i_0_a6_RNO[15]\ : OR2 - port map(A => \ipend[15]\, B => pirq_13, Y => - \ipend_0_i_0_a6_0[15]\); - - \r.ipend[11]\ : DFN1 - port map(D => N_703_i_0, CLK => lclk_c, Q => \ipend[11]\); - - \r.imask_0_RNO_0[15]\ : MX2 - port map(A => \imask_0[15]\, B => pwdata_0(15), S => - imask_0_1_sqmuxa, Y => N_535); - - \r.imask_0_RNO_0[10]\ : MX2 - port map(A => \imask_0[10]\, B => pwdata_0(10), S => - imask_0_1_sqmuxa, Y => N_530); - - \r.ilevel_RNIMUVF[5]\ : NOR2A - port map(A => \ilevel[5]\, B => N_20, Y => \a[5]\); - - \r.ilevel_RNIQ0OR_0[8]\ : OR2B - port map(A => N_795, B => N_792, Y => N_434); - - \r.cpurst_0_0_a3_0_a2[0]\ : OR2 - port map(A => N_259, B => paddr_0(2), Y => N_884); - - \r.ilevel[7]\ : DFN1E1 - port map(D => pwdata_0(7), CLK => lclk_c, E => N_827, Q => - \ilevel[7]\); - - \r.ilevel_RNI6V0G[9]\ : OR3C - port map(A => \imask_0[9]\, B => \ilevel[9]\, C => N_285, Y - => \a_i_i[9]\); - - \r.ipend_0_i_0_a6_2_RNO[9]\ : NOR2A - port map(A => pirq_7, B => pwdata_0(9), Y => - \ipend_0_i_0_a6_2_0[9]\); - - \r.ipend_0_i_0_a6_1[2]\ : NAND2 - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[2]\, Y => - N_820); - - \r.iforce_0_RNO_1[5]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_19, Y => - N_835); - - \r.ipend_RNO_0[15]\ : OR2A - port map(A => N_917, B => \iforce_0[15]\, Y => N_494); - - \r.iforce_0[7]\ : DFN1 - port map(D => N_602_i_0, CLK => lclk_c, Q => \iforce_0[7]\); - - \v.ilevel_0_sqmuxa_i_i_o2_0\ : NOR2 - port map(A => N_258, B => paddr_0(2), Y => N_262); - - \r.irl_0[2]\ : DFN1 - port map(D => \irl_0_1_0[2]\, CLK => lclk_c, Q => irl_2(2)); - - \r.ipend_RNO_0[8]\ : OR2 - port map(A => \iforce_0[8]\, B => N_929, Y => - \ipend_RNO_0[8]\); - - \r.ipend_RNO_0[3]\ : OR2 - port map(A => \iforce_0[3]\, B => N_923, Y => - \ipend_RNO_0[3]\); - - \r.iforce_0_0_i_0_a2_2[6]\ : OR2A - port map(A => irl_0(2), B => intack, Y => N_889); - - \r.iforce_0[12]\ : DFN1 - port map(D => N_628_i_0, CLK => lclk_c, Q => \iforce_0[12]\); - - \r.ilevel_RNI258J1_0[8]\ : NOR2 - port map(A => N_434, B => N_417, Y => N_437); - - \r.iforce_0_RNO_1[3]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_17, Y => N_871); - - \r.ilevel_RNI3Q95[13]\ : NOR2B - port map(A => \ilevel[13]\, B => \imask_0[13]\, Y => - \a_i_0_o6_0[13]\); - - \r.imask_0_RNIRUVA[10]\ : OR2B - port map(A => \imask_0[10]\, B => N_895, Y => N_478); - - \r.ilevel_RNIOU831[14]\ : OA1 - port map(A => \a[14]\, B => \a_i_0[13]\, C => \a[15]\, Y - => \irl_0_0[0]\); - - \r.ipend_0_i_0_a6_1[8]\ : OR2A - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[8]\, Y => - \ipend_0_i_0_a6_1[8]\); - - \r.irl_0_RNO_9[0]\ : NOR2B - port map(A => \a_1[4]\, B => \a_1_i_0[6]\, Y => - \irl_1_0_a2_1_0_0[0]\); - - \r.ilevel_RNIIMVF[4]\ : OR3C - port map(A => \un1_temp[4]\, B => \imask_0[4]\, C => - \ilevel[4]\, Y => \a[4]\); - - \r.ilevel_RNIGAVV1[7]\ : NOR3C - port map(A => \a_i_0[6]\, B => \a[7]\, C => - \irl_0_0_i_a6_0[1]\, Y => \irl_0_0_i_a6_1[1]\); - - \r.ilevel_RNI0QNB_0[12]\ : NOR3C - port map(A => \imask_0[12]\, B => \ilevel[12]\, C => N_298, - Y => N_883); - - \r.iforce_0_RNI72KT[1]\ : AOI1B - port map(A => \iforce_0[1]\, B => \N_898\, C => N_502, Y - => prdata_0_iv_0_0_0_0); - - \r.ipend_RNO_1[11]\ : NOR3C - port map(A => N_462, B => N_461, C => N_459, Y => - \ipend_0_i_0_1[11]\); - - \r.ilevel_RNIOLVA[14]\ : OR2B - port map(A => \ilevel[14]\, B => \prdata_0_sqmuxa\, Y => - N_438); - - \r.ipend_0_i_0_a6[8]\ : OR2 - port map(A => N_264, B => \ipend_0_i_0_a6_0[8]\, Y => - \ipend_0_i_0_a6[8]\); - - \r.iforce_0_RNO[12]\ : NOR3C - port map(A => N_922, B => \iforce_0_0_i_0_1[12]\, C => rstn, - Y => N_628_i_0); - - \r.imask_0_RNO_0[12]\ : MX2 - port map(A => \imask_0[12]\, B => pwdata_0(12), S => - imask_0_1_sqmuxa, Y => N_532); - - \r.imask_0_RNO_0[1]\ : MX2 - port map(A => \imask_0[1]\, B => pwdata_0(1), S => - imask_0_1_sqmuxa, Y => N_521); - - \r.ipend_RNO[8]\ : NOR3C - port map(A => \ipend_RNO_0[8]\, B => \ipend_0_i_0_1[8]\, C - => rstn, Y => N_598_i_0); - - \r.ipend_RNO[12]\ : NOR3C - port map(A => \ipend_RNO_0[12]\, B => \ipend_0_i_0_1[12]\, - C => rstn, Y => N_599_i_0); - - \r.ilevel_RNITD95_0[10]\ : NOR2A - port map(A => \imask_0[10]\, B => \ilevel[10]\, Y => - \a_1_0_a3_i_0[10]\); - - \r.ilevel[1]\ : DFN1E1 - port map(D => pwdata_1_0, CLK => lclk_c, E => N_827, Q => - \ilevel[1]\); - - \r.ipend_0_i_0_a6_2_RNO[13]\ : NOR2 - port map(A => pirq_11, B => pwdata_0(13), Y => - \ipend_0_i_0_a6_2_0[13]\); - - \r.ilevel_RNI8MEC[3]\ : OR2B - port map(A => \ilevel[3]\, B => \prdata_0_sqmuxa\, Y => - N_856); - - \r.iforce_0_RNO[5]\ : NOR3C - port map(A => N_920, B => \iforce_0_0_i_0_1[5]\, C => rstn, - Y => N_706_i_0); - - \r.imask_0[7]\ : DFN1 - port map(D => \imask_0_RNO[7]\, CLK => lclk_c, Q => - \imask_0[7]\); - - \r.ilevel[11]\ : DFN1E1 - port map(D => pwdata_0(11), CLK => lclk_c, E => N_827, Q - => \ilevel[11]\); - - \r.irl_0_RNO_6[0]\ : AOI1B - port map(A => \a_1_i_0[6]\, B => \a_1[5]\, C => \a_1[7]\, Y - => \irl_1_0_3_tz_0[0]\); - - \r.iforce_0_RNO_0[9]\ : NOR3C - port map(A => N_513, B => N_512, C => \iforce_0_RNO_3[9]\, - Y => \iforce_0_0_i_0_1[9]\); - - \r.imask_0[8]\ : DFN1 - port map(D => \imask_0_RNO[8]\, CLK => lclk_c, Q => - \imask_0[8]\); - - \r.iforce_0_0_i_0_a2[13]\ : NOR3B - port map(A => irl_3, B => N_908, C => irl_1, Y => N_926); - - \r.ipend_RNO_4[7]\ : OR3 - port map(A => N_258_0, B => N_261, C => pwdata_0(7), Y => - N_375); - - \r.ipend_0_i_o2_1[5]\ : OR2A - port map(A => paddr_0(2), B => N_259, Y => N_261); - - \v.ilevel_0_sqmuxa_i_i_o2_0_0\ : NOR2 - port map(A => N_258, B => paddr_0(2), Y => N_262_0); - - \r.iforce_0_RNO_1[1]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_15, Y => N_454); - - \r.ilevel[9]\ : DFN1E1 - port map(D => pwdata_0(9), CLK => lclk_c, E => N_827, Q => - \ilevel[9]\); - - \r.ilevel[2]\ : DFN1E1 - port map(D => pwdata_0_d0, CLK => lclk_c, E => N_827, Q => - \ilevel[2]\); - - \r.ilevel_RNISBVC9[11]\ : NOR3C - port map(A => \irl_0_1[0]\, B => N_394, C => \irl_0_3[0]\, - Y => \irl_i_0[0]\); - - \r.irl_0[0]\ : DFN1 - port map(D => \irl_0_1_0[0]\, CLK => lclk_c, Q => irl_0(0)); - - \r.ilevel_RNIP80M[15]\ : AOI1B - port map(A => \ilevel[15]\, B => \prdata_0_sqmuxa\, C => - N_486, Y => \prdata_0_iv_0_0_1[15]\); - - \r.ilevel[13]\ : DFN1E1 - port map(D => pwdata_0(13), CLK => lclk_c, E => N_827, Q - => \ilevel[13]\); - - \r.iforce_0_RNO_0[3]\ : NOR3C - port map(A => N_871, B => N_870, C => \iforce_0_RNO_3[3]\, - Y => \iforce_0_0_i_0_1[3]\); - - \r.ilevel_RNI6D8J1[9]\ : OR3A - port map(A => N_631, B => \a_i_i[9]\, C => N_384, Y => - N_394); - - \r.ilevel_RNI8AOB[14]\ : NOR3B - port map(A => \imask_0[14]\, B => \ilevel[14]\, C => N_270, - Y => \a[14]\); - - \prdata_0_iv_0_a2_0_0[6]\ : NOR3A - port map(A => paddr(6), B => paddr(5), C => paddr_0(4), Y - => \prdata_0_iv_0_a2_0[6]_net_1\); - - \r.iforce_0_RNIK7IJ[9]\ : OR2B - port map(A => \iforce_0[9]\, B => \N_898\, Y => N_471); - - \r.iforce_0_0_i_0_a2[6]\ : OR3B - port map(A => irl_1, B => N_905, C => irl_3, Y => N_918); - - \r.iforce_0_RNO_1[15]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_29, Y => - N_442); - - \r.iforce_0_RNO_0[14]\ : NOR3C - port map(A => N_445, B => N_444, C => \iforce_0_RNO_3[14]\, - Y => \iforce_0_0_i_0_1[14]\); - - \r.ipend_RNO_6[12]\ : NOR2A - port map(A => pwdata_0(12), B => pirq_10, Y => - \ipend_0_i_0_a6_1_0[12]\); - - \r.imask_0_RNO_0[14]\ : MX2 - port map(A => \imask_0[14]\, B => pwdata_0(14), S => - imask_0_1_sqmuxa, Y => N_534); - - \r.irl_0_RNO_0[2]\ : OA1B - port map(A => N_419_i, B => \irl_1_0_a2_1[2]\, C => - \irl_1_0_1[2]\, Y => \irl_1[2]\); - - \r.imask_0_RNI4HGB[3]\ : NOR2A - port map(A => \imask_0[3]\, B => N_886, Y => N_269); - - \r.ipend_0_i_0_a6[13]\ : OR2 - port map(A => N_264, B => \ipend_0_i_0_a6_0[13]\, Y => - \ipend_0_i_0_a6[13]\); - - \r.iforce_0[5]\ : DFN1 - port map(D => N_706_i_0, CLK => lclk_c, Q => \iforce_0[5]\); - - \r.ipend_RNIV3E6[12]\ : OR2 - port map(A => \ipend[12]\, B => \iforce_0[12]\, Y => N_298); - - \r.ipend_RNO_3[4]\ : OR3A - port map(A => pwdata_0(4), B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_406); - - \r.irl_0_RNO_4[1]\ : NOR2B - port map(A => N_792, B => N_19, Y => \irl_1_0_a2_0_0[1]\); - - \r.irl_0_RNO[3]\ : MX2C - port map(A => N_433, B => N_400, S => irl_02_i, Y => - \irl_0_1[3]\); - - \r.iforce_0_RNO_3[1]\ : AO1 - port map(A => N_266_i, B => pwdata_1_0, C => \iforce_0[1]\, - Y => \iforce_0_RNO_3[1]\); - - \r.ipend[5]\ : DFN1 - port map(D => N_794_i_0, CLK => lclk_c, Q => \ipend[5]\); - - \r.iforce_0_RNO_0[7]\ : NOR3C - port map(A => N_868, B => N_867, C => \iforce_0_RNO_3[7]\, - Y => \iforce_0_0_i_0_1[7]\); - - \r.ilevel_RNISHNB[11]\ : OR3C - port map(A => \imask_0[11]\, B => \ilevel[11]\, C => N_289, - Y => N_198); - - \r.iforce_0_0_i_0_a2[7]\ : OR3B - port map(A => irl_1, B => N_908, C => irl_3, Y => N_930); - - \r.imask_0[12]\ : DFN1 - port map(D => \imask_0_RNO[12]\, CLK => lclk_c, Q => - \imask_0[12]\); - - \r.iforce_0_RNO_3[14]\ : AO1 - port map(A => N_266_i, B => pwdata_0(14), C => - \iforce_0[14]\, Y => \iforce_0_RNO_3[14]\); - - \r.iforce_0_RNO_1[7]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_21, Y => N_868); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.imask_0_RNO_0[9]\ : MX2 - port map(A => \imask_0[9]\, B => pwdata_0(9), S => - imask_0_1_sqmuxa, Y => N_529); - - \r.imask_0_RNIJ5LB[9]\ : OR2B - port map(A => \imask_0[9]\, B => N_895, Y => N_474); - - \r.ipend_RNO_2[5]\ : OR3 - port map(A => N_258_0, B => N_261, C => pwdata_0(5), Y => - N_359); - - \r.ipend_RNO_1[1]\ : NOR3C - port map(A => N_517, B => N_516, C => N_514, Y => - \ipend_0_i_0_1[1]\); - - \r.iforce_0_RNO_1[2]\ : OR3C - port map(A => N_262, B => N_892, C => pwdata_16, Y => N_492); - - \r.ipend_RNO_4[5]\ : AO1D - port map(A => N_261, B => N_258_0, C => \ipend[5]\, Y => - N_356); - - \r.iforce_0_0_i_0_a2[2]\ : OR3B - port map(A => irl_1, B => N_910, C => irl_3, Y => N_925); - - \r.ipend_RNO_7[12]\ : NOR2 - port map(A => pirq_10, B => pwdata_0(12), Y => - \ipend_0_i_0_a6_2_0[12]\); - - \r.ipend_RNIU8GB[1]\ : OAI1 - port map(A => \iforce_0[1]\, B => \ipend[1]\, C => - \imask_0[1]\, Y => N_4); - - \r.imask_0_RNID5LB[3]\ : OR2B - port map(A => \imask_0[3]\, B => N_895, Y => N_857); - - \r.ipend_RNO_2[12]\ : AO1D - port map(A => N_261, B => N_258_0, C => - \ipend_0_i_0_a6_0[12]\, Y => N_877_i); - - \r.ipend_RNIENDN[14]\ : AOI1B - port map(A => \ipend[14]\, B => \prdata_1_sqmuxa\, C => - N_439, Y => prdata_0_iv_0_0_1_13); - - \r.ilevel_RNI8AOB_0[14]\ : NOR2 - port map(A => \a_1_0[14]\, B => N_270, Y => \a_1[14]\); - - \r.ilevel_RNIOKUV[2]\ : NOR2B - port map(A => N_310, B => N_271, Y => \irl_0_0_i_a6_0[1]\); - - \r.imask_0_RNO[6]\ : NOR2B - port map(A => rstn, B => N_526, Y => N_390); - - \r.iforce_0_RNO_2[13]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(13), Y => - N_447); - - \r.iforce_0_RNO[9]\ : NOR3C - port map(A => N_919, B => \iforce_0_0_i_0_1[9]\, C => rstn, - Y => N_82_i_0); - - \v.ilevel_0_sqmuxa_i_i_a6\ : NOR2A - port map(A => N_262_0, B => N_259, Y => N_827); - - \r.ilevel_RNIVH95[11]\ : NOR2A - port map(A => \imask_0[11]\, B => \ilevel[11]\, Y => - \a_1_0[11]\); - - \r.ipend_RNO_3[7]\ : OR3A - port map(A => pwdata_0(7), B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_374); - - \r.ipend_RNO_1[8]\ : NOR3C - port map(A => \ipend_0_i_0_a6[8]\, B => - \ipend_0_i_0_a6_1[8]\, C => \ipend_0_i_0_a6_2[8]\, Y => - \ipend_0_i_0_1[8]\); - - \r.imask_0_RNO[9]\ : NOR2B - port map(A => rstn, B => N_529, Y => \imask_0_RNO[9]\); - - \r.ipend_RNO[3]\ : NOR3C - port map(A => \ipend_RNO_0[3]\, B => \ipend_0_i_0_1[3]\, C - => rstn, Y => N_23_i_0); - - \r.ipend[15]\ : DFN1 - port map(D => N_648_i_0, CLK => lclk_c, Q => \ipend[15]\); - - \r.imask_0_RNO_0[5]\ : MX2 - port map(A => \imask_0[5]\, B => pwdata_0(5), S => - imask_0_1_sqmuxa, Y => N_525); - - \r.ipend_RNO[6]\ : NOR3C - port map(A => \ipend_RNO_0[6]\, B => \ipend_0_i_0_1[6]\, C - => rstn, Y => N_78_i_0); - - \r.ipend_0_i_0_a6[9]\ : OR2A - port map(A => \ipend_0_i_0_a6_0[9]\, B => N_264, Y => N_828); - - \r.imask_0_RNO[11]\ : NOR2B - port map(A => rstn, B => N_531, Y => \imask_0_RNO[11]\); - - \r.imask_0_RNO[10]\ : NOR2B - port map(A => rstn, B => N_530, Y => \imask_0_RNO[10]\); - - \r.ilevel_RNI8LVV[4]\ : OR2A - port map(A => \a_1[4]\, B => \a_1[5]\, Y => N_418); - - \r.imask_0_RNIL00M[13]\ : AOI1B - port map(A => \imask_0[13]\, B => N_895, C => N_481, Y => - prdata_0_iv_0_0_1_12); - - \r.ilevel_RNIA6VF_0[2]\ : OR3A - port map(A => \imask_0[2]\, B => \ilevel[2]\, C => N_383, Y - => N_17); - - \v.imask_0_1_sqmuxa_0_a2_1_a6\ : NOR2A - port map(A => N_895, B => un1_apbi_1, Y => imask_0_1_sqmuxa); - - \r.iforce_0_RNO_2[4]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(4), Y => - N_488); - - \r.ipend_RNO_3[12]\ : OR3A - port map(A => \ipend_0_i_0_a6_1_0[12]\, B => N_258_0, C => - \ipend_0_i_a2_0[5]\, Y => N_881); - - \r.imask_0_RNO_0[8]\ : MX2 - port map(A => \imask_0[8]\, B => pwdata_0(8), S => - imask_0_1_sqmuxa, Y => N_528); - - \r.ipend_RNO_2[1]\ : OR3 - port map(A => N_258, B => N_261, C => pwdata_0(1), Y => - N_517); - - \r.ilevel_RNI0B002_0[7]\ : NOR3C - port map(A => \a_i_0[6]\, B => \a[7]\, C => N_385, Y => - \irl_0_0_i_a6_1_0[1]\); - - \r.ilevel_RNISKG62[11]\ : OA1 - port map(A => N_198, B => N_384, C => \irl_0_0[0]\, Y => - \irl_0_1[0]\); - - \r.ilevel_RNIKLH65[7]\ : AOI1 - port map(A => \irl_0_a2_0[2]\, B => N_386, C => - \irl_0_1[2]\, Y => \irl[2]\); - - \r.ipend_RNO[1]\ : NOR3C - port map(A => N_515, B => \ipend_0_i_0_1[1]\, C => rstn, Y - => N_70_i_0); - - \r.ipend_RNIDTH8[4]\ : OR2 - port map(A => \ipend[4]\, B => \iforce_0[4]\, Y => - \un1_temp[4]\); - - \r.ilevel_RNICTVV[4]\ : NOR2B - port map(A => \a[4]\, B => \a_i_0[6]\, Y => - \irl_0_a2_1_0_0[0]\); - - \r.iforce_0_0_i_0_a2[9]\ : OR3B - port map(A => irl_3, B => N_904, C => irl_1, Y => N_919); - - \r.ipend_RNO_1[4]\ : NOR3C - port map(A => N_407, B => N_406, C => \ipend_RNO_4[4]\, Y - => \ipend_0_i_0_1[4]\); - - \r.ilevel_RNI2N0G_0[8]\ : NOR3C - port map(A => \imask_0[8]\, B => \ilevel[8]\, C => N_291, Y - => N_165); - - \r.ilevel_RNIEEFC[9]\ : OR2B - port map(A => \ilevel[9]\, B => \prdata_0_sqmuxa\, Y => - N_473); - - prdata_2_sqmuxa_0_a2_0_a2 : NOR2A - port map(A => paddr_0(3), B => paddr(7), Y => N_885); - - \r.ipend_RNO_0[2]\ : OR2 - port map(A => \iforce_0[2]\, B => N_925, Y => - \ipend_RNO_0[2]\); - - \r.ipend_RNO[10]\ : NOR3C - port map(A => \ipend_RNO_0[10]\, B => \ipend_0_i_0_1[10]\, - C => rstn, Y => N_15_i_0); - - \r.imask_0_RNO[15]\ : NOR2B - port map(A => rstn, B => N_535, Y => \imask_0_RNO[15]\); - - \r.ilevel_RNIUE0G_0[7]\ : OR3A - port map(A => \imask_0[7]\, B => N_350, C => \ilevel[7]\, Y - => \a_1[7]\); - - \r.ilevel_RNIOL001[7]\ : OR2B - port map(A => \a_1[7]\, B => \a_1_i_0[6]\, Y => N_414); - - \r.ilevel_RNI8GPB1[8]\ : OR3A - port map(A => \a_i_i[9]\, B => N_883, C => N_165, Y => - \irl_0_0_i_1_tz_1[1]\); - - \r.ilevel_RNI4LJUR[14]\ : OR2B - port map(A => irl_02_1, B => N_240, Y => irl_02_i); - - \r.ipend_0_i_0_a6_2[13]\ : NAND2 - port map(A => N_264, B => \ipend_0_i_0_a6_2_0[13]\, Y => - N_876); - - \r.ilevel_RNITD95[10]\ : NOR2B - port map(A => \ilevel[10]\, B => \imask_0[10]\, Y => - \a_i_i_o2_0_o6_0[10]\); - - \r.ilevel_RNI0QNB[12]\ : OR3B - port map(A => \imask_0[12]\, B => N_298, C => \ilevel[12]\, - Y => N_13); - - \r.iforce_0_RNO_0[15]\ : NOR3C - port map(A => N_442, B => N_441, C => \iforce_0_RNO_3[15]\, - Y => \iforce_0_0_i_0_1[15]\); - - \r.ipend_RNINHI8[9]\ : OR2 - port map(A => \ipend[9]\, B => \iforce_0[9]\, Y => N_285); - - \r.ilevel_RNIAGTF2[1]\ : AO1B - port map(A => N_402_i, B => N_271, C => \irl_0_a2_1_0_0[0]\, - Y => \irl_0_a2_1[0]\); - - \r.ipend_RNO_2[7]\ : AO1D - port map(A => N_261, B => N_258_0, C => \ipend[7]\, Y => - \ipend_RNO_2[7]\); - - \r.ipend_RNO_0[13]\ : OR2A - port map(A => N_926, B => \iforce_0[13]\, Y => N_874); - - \r.ipend_RNO_1[12]\ : NOR3C - port map(A => N_877_i, B => N_881, C => N_882, Y => - \ipend_0_i_0_1[12]\); - - \r.irl_0_RNO_1[2]\ : NOR2 - port map(A => N_418, B => N_414, Y => N_419_i); - - \r.iforce_0_RNO_2[5]\ : OR3B - port map(A => N_262_0, B => N_885, C => pwdata_0(5), Y => - N_834); - - \r.imask_0_RNIF5LB[5]\ : OR2B - port map(A => \imask_0[5]\, B => N_895, Y => N_367); - - \r.iforce_0_RNIM0L8[4]\ : NOR2B - port map(A => \iforce_0[4]\, B => paddr(7), Y => - prdata_13_m_1_0(4)); - - \r.ipend_RNO_0[10]\ : OR2 - port map(A => \iforce_0[10]\, B => N_921, Y => - \ipend_RNO_0[10]\); - - \r.imask_0_RNI0J0B[15]\ : OR2B - port map(A => \imask_0[15]\, B => N_895, Y => N_486); - - \r.ipend_RNO_4[10]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[10]\, Y => - N_497); - - \r.imask_0_RNO[13]\ : NOR2B - port map(A => rstn, B => N_533, Y => N_397); - - \r.ilevel_RNIFDE7[9]\ : NOR2A - port map(A => \imask_0[9]\, B => \ilevel[9]\, Y => - \a_1_i_s_0_0[9]\); - - \r.iforce_0_RNO_3[15]\ : AO1 - port map(A => N_266_i, B => pwdata_0(15), C => - \iforce_0[15]\, Y => \iforce_0_RNO_3[15]\); - - \r.ilevel_RNI84GN_0[12]\ : OR2 - port map(A => \a[14]\, B => N_883, Y => N_384); - - \r.irl_0_RNO_5[0]\ : OR2A - port map(A => \a_1[11]\, B => N_417, Y => N_426); - - \r.ipend_RNO[4]\ : NOR3C - port map(A => \ipend_RNO_0[4]\, B => \ipend_0_i_0_1[4]\, C - => rstn, Y => N_76_i_0); - - \r.ilevel_RNI3Q95_0[13]\ : NOR2A - port map(A => \imask_0[13]\, B => \ilevel[13]\, Y => - \a_1_0[13]\); - - \r.ilevel_RNIGKGN_0[15]\ : NOR2B - port map(A => \a_i_0[13]\, B => \a[15]\, Y => - \irl_i_a2_0_0[3]\); - - \r.ilevel_RNIEK0G1[5]\ : AOI1B - port map(A => \a_i_0[6]\, B => \a[5]\, C => \a[7]\, Y => - \irl_0_3_tz_0[0]\); - - \r.imask_0_RNII5LB[8]\ : OR2B - port map(A => \imask_0[8]\, B => N_895, Y => N_470); - - \r.ilevel_RNIGRVT4[14]\ : AO1A - port map(A => N_311, B => \irl_0_0_i_a6_1[1]\, C => N_506, - Y => \irl_0_0_i_0[1]\); - - \r.ilevel[5]\ : DFN1E1 - port map(D => pwdata_0(5), CLK => lclk_c, E => N_827, Q => - \ilevel[5]\); - - \r.ilevel_RNIQ60G_0[6]\ : OR2 - port map(A => \ilevel[6]\, B => N_24, Y => \a_1_i_0[6]\); - - \r.irl_0_RNO_8[0]\ : OR3A - port map(A => N_17, B => N_4, C => \ilevel[1]\, Y => - N_435_i); - - \r.ipend[2]\ : DFN1 - port map(D => N_627_i_0, CLK => lclk_c, Q => \ipend[2]\); - - \r.iforce_0_RNO_1[13]\ : OR3C - port map(A => N_262_0, B => N_892, C => pwdata_27, Y => - N_448); - - \r.ipend_RNO[5]\ : NOR3C - port map(A => \ipend_RNO_0[5]\, B => \ipend_0_i_1[5]\, C - => rstn, Y => N_794_i_0); - - \r.ipend_RNI3CE6[14]\ : NOR2 - port map(A => \ipend[14]\, B => \iforce_0[14]\, Y => N_270); - - \r.imask_0_RNO_0[3]\ : MX2 - port map(A => \imask_0[3]\, B => pwdata_0(3), S => - imask_0_1_sqmuxa, Y => N_523); - - \r.ipend_RNO_0[14]\ : OR2 - port map(A => \iforce_0[14]\, B => N_931, Y => - \ipend_RNO_0[14]\); - - \r.ipend_RNO_4[14]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[14]\, Y => - N_455); - - \r.ipend_0_i_0_a6[2]\ : OR2 - port map(A => N_264, B => \ipend_0_i_0_a6_0[2]\, Y => - N_818_i); - - \r.imask_0_RNO_0[11]\ : MX2 - port map(A => \imask_0[11]\, B => pwdata_0(11), S => - imask_0_1_sqmuxa, Y => N_531); - - \r.imask_0_RNIB5LB[1]\ : OR2B - port map(A => \imask_0[1]\, B => N_895, Y => N_504); - - \r.ilevel_RNI2N0G[8]\ : OR3B - port map(A => \imask_0[8]\, B => N_291, C => \ilevel[8]\, Y - => N_792); - - \r.iforce_0[14]\ : DFN1 - port map(D => N_710_i_0, CLK => lclk_c, Q => \iforce_0[14]\); - - \r.ipend_RNI18E6[13]\ : OR2 - port map(A => \ipend[13]\, B => \iforce_0[13]\, Y => N_306); - - \r.irl_0_RNO_0[1]\ : AO1B - port map(A => \irl_1_0_a2_0_1[1]\, B => N_421, C => - \irl_1_0_1[1]\, Y => \irl_1[1]\); - - \r.imask_0_RNO_0[13]\ : MX2 - port map(A => \imask_0[13]\, B => pwdata_0(13), S => - imask_0_1_sqmuxa, Y => N_533); - - \r.ipend_RNO_4[3]\ : AO1D - port map(A => N_261, B => N_258_0, C => \ipend[3]\, Y => - N_368); - - \r.ipend_RNIDTGB[6]\ : OAI1 - port map(A => \iforce_0[6]\, B => \ipend[6]\, C => - \imask_0[6]\, Y => N_24); - - \r.ipend_RNO_5[12]\ : OR2 - port map(A => pirq_10, B => \ipend[12]\, Y => - \ipend_0_i_0_a6_0[12]\); - - \r.ipend_0_i_a2[5]\ : NOR2 - port map(A => N_258_0, B => \ipend_0_i_a2_0[5]\, Y => N_894); - - \r.irl_0_RNO_6[1]\ : OR2A - port map(A => N_795, B => \a_1[11]\, Y => N_422); - - \r.iforce_0_RNO_2[11]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(11), Y => - N_450); - - \r.ipend_RNIE4DC[13]\ : OR2B - port map(A => \ipend[13]\, B => \prdata_1_sqmuxa\, Y => - N_480); - - \r.ipend_0_i_0_a6_1[9]\ : NAND2 - port map(A => N_894, B => \ipend_0_i_0_a6_1_0[9]\, Y => - N_830); - - \r.iforce_0_RNIU9HH1[15]\ : OR3C - port map(A => N_484, B => N_483, C => - \prdata_0_iv_0_0_1[15]\, Y => prdata_13); - - \r.ipend[9]\ : DFN1 - port map(D => N_702_i_0, CLK => lclk_c, Q => \ipend[9]\); - - \r.ipend_RNO[14]\ : NOR3C - port map(A => \ipend_RNO_0[14]\, B => \ipend_0_i_0_1[14]\, - C => rstn, Y => N_704_i_0); - - \r.iforce_0_RNO_0[6]\ : NOR3C - port map(A => N_838, B => N_837, C => \iforce_0_RNO_3[6]\, - Y => \iforce_0_0_i_0_1[6]\); - - \r.irl_0_RNO_0[0]\ : NOR3C - port map(A => \irl_1_0_1[0]\, B => \irl_0_RNO_2[0]\, C => - \irl_1_0_3[0]\, Y => \irl_1_i[0]\); - - \r.ipend_0_i_o2_0[5]\ : OR2 - port map(A => un1_apbi_1, B => N_257, Y => N_258); - - \r.imask_0_RNO[7]\ : NOR2B - port map(A => rstn, B => N_527, Y => \imask_0_RNO[7]\); - - \r.irl_0_RNO_3[0]\ : AO1B - port map(A => \irl_1_0_3_tz_0[0]\, B => \irl_1_0_a2_1[0]\, - C => N_437, Y => \irl_1_0_3[0]\); - - \r.iforce_0_RNO_0[1]\ : NOR3C - port map(A => N_454, B => N_453, C => \iforce_0_RNO_3[1]\, - Y => \iforce_0_0_i_0_1[1]\); - - \r.ilevel_RNI42OB_0[13]\ : OR2B - port map(A => \a_i_0_o6_0[13]\, B => N_306, Y => - \a_i_0[13]\); - - \r.iforce_0_RNO_0[4]\ : NOR3C - port map(A => N_489, B => N_488, C => \iforce_0_RNO_3[4]\, - Y => \iforce_0_0_i_0_1[4]\); - - \prdata_0_iv_0_a2[6]\ : NOR2A - port map(A => \prdata_0_iv_0_a2_0[6]_net_1\, B => N_884, Y - => N_895); - - \r.irl_0_RNO_3[1]\ : AOI1B - port map(A => N_431_1, B => N_422, C => \irl_1_0_0[1]\, Y - => \irl_1_0_1[1]\); - - \r.ipend_RNO[15]\ : NOR3C - port map(A => N_494, B => \ipend_0_i_0_1[15]\, C => rstn, Y - => N_648_i_0); - - \r.iforce_0_RNIBKEE[4]\ : OR3C - port map(A => N_885, B => \iforce_0[4]\, C => N_896, Y => - iforce_0_m(4)); - - \r.iforce_0_0_i_0_a2_1[6]\ : NOR2 - port map(A => irl_0_d0, B => N_889, Y => N_905); - - \r.ipend_RNIJ9I8[7]\ : NOR2 - port map(A => \ipend[7]\, B => \iforce_0[7]\, Y => N_350); - - \r.iforce_0_RNO_2[7]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(7), Y => - N_867); - - \r.ipend_0_i_0_a6_1_RNO[15]\ : OR2A - port map(A => pwdata_0(15), B => pirq_13, Y => - \ipend_0_i_0_a6_1_0[15]\); - - \r.imask_0[1]\ : DFN1 - port map(D => \imask_0_RNO[1]\, CLK => lclk_c, Q => - \imask_0[1]\); - - \r.ipend_RNO_3[6]\ : OR3A - port map(A => pwdata_0(6), B => N_258, C => - \ipend_0_i_a2_0[5]\, Y => N_410); - - \r.ipend_0_i_0_a6_RNO[13]\ : OR2 - port map(A => \ipend[13]\, B => pirq_11, Y => - \ipend_0_i_0_a6_0[13]\); - - \r.ipend[14]\ : DFN1 - port map(D => N_704_i_0, CLK => lclk_c, Q => \ipend[14]\); - - \r.iforce_0_RNICA3Q[14]\ : AOI1B - port map(A => \iforce_0[14]\, B => \N_898\, C => N_438, Y - => prdata_0_iv_0_0_0_13); - - \r.imask_0_RNO[5]\ : NOR2B - port map(A => rstn, B => N_525, Y => N_389); - - \r.ilevel_RNIMUVF_0[5]\ : NOR2 - port map(A => \ilevel[5]\, B => N_20, Y => \a_1[5]\); - - \r.iforce_0[10]\ : DFN1 - port map(D => N_84_i_0, CLK => lclk_c, Q => \iforce_0[10]\); - - \r.ilevel_RNI0B002[7]\ : OR3B - port map(A => \a_i_0[6]\, B => \a[7]\, C => N_385, Y => - N_386); - - \r.iforce_0_RNO_3[9]\ : AO1 - port map(A => N_266_i, B => pwdata_0(9), C => \iforce_0[9]\, - Y => \iforce_0_RNO_3[9]\); - - \r.irl_0_RNO_1[0]\ : NOR3B - port map(A => \irl_0_RNO_4[0]\, B => N_426, C => \a_1[15]\, - Y => \irl_1_0_1[0]\); - - \r.imask_0_RNO_0[2]\ : MX2 - port map(A => \imask_0[2]\, B => pwdata_0(2), S => - imask_0_1_sqmuxa, Y => N_522); - - \r.imask_0_RNO[2]\ : NOR2B - port map(A => rstn, B => N_522, Y => \imask_0_RNO[2]\); - - \r.ipend_RNO[2]\ : NOR3C - port map(A => \ipend_RNO_0[2]\, B => \ipend_0_i_0_1[2]\, C - => rstn, Y => N_627_i_0); - - \r.ilevel_RNI4C2QH[11]\ : NOR3C - port map(A => \irl[2]\, B => N_400, C => \irl_i_0[0]\, Y - => irl_02_1); - - prdata_1_sqmuxa_0_a2_0_a2 : NOR2 - port map(A => N_261, B => N_257, Y => \prdata_1_sqmuxa\); - - \r.ipend_RNO_4[4]\ : AO1D - port map(A => N_261, B => N_258_0, C => \ipend[4]\, Y => - \ipend_RNO_4[4]\); - - \r.ipend_RNI96KT[2]\ : NOR2B - port map(A => N_463, B => N_464, Y => - \prdata_0_iv_0_0_0[2]\); - - \r.iforce_0_RNO_2[1]\ : OR3B - port map(A => N_262, B => N_885, C => pwdata_0(1), Y => - N_453); - - \r.ipend_0_i_0_a6_RNO[2]\ : OR2 - port map(A => \ipend[2]\, B => pirq_0, Y => - \ipend_0_i_0_a6_0[2]\); - - \r.ipend_RNIBAKT[3]\ : NOR2B - port map(A => N_519, B => N_520, Y => - \prdata_0_iv_0_0_0[3]\); - - \r.iforce_0_RNI1PGR[13]\ : AOI1B - port map(A => \iforce_0[13]\, B => \N_898\, C => N_480, Y - => prdata_0_iv_0_0_0_12); - - \r.ilevel_RNINLVA[13]\ : OR2B - port map(A => \ilevel[13]\, B => \prdata_0_sqmuxa\, Y => - N_481); - - \r.ipend_RNO_0[11]\ : OR2 - port map(A => \iforce_0[11]\, B => N_927, Y => - \ipend_RNO_0[11]\); - - \r.ipend_RNO_4[11]\ : AO1D - port map(A => N_261, B => N_258, C => \ipend[11]\, Y => - N_459); - - \r.ipend_RNITVD6[11]\ : OR2 - port map(A => \ipend[11]\, B => \iforce_0[11]\, Y => N_289); - - \r.iforce_0_RNO[8]\ : NOR3C - port map(A => N_929, B => \iforce_0_0_i_0_1[8]\, C => rstn, - Y => N_80_i_0); - - \r.iforce_0_RNO[14]\ : NOR3C - port map(A => N_931, B => \iforce_0_0_i_0_1[14]\, C => rstn, - Y => N_710_i_0); - - \r.iforce_0[3]\ : DFN1 - port map(D => N_601_i_0, CLK => lclk_c, Q => \iforce_0[3]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity apbuart is - - port( pwdata_12 : in std_logic; - pwdata_13 : in std_logic; - pwdata_14 : in std_logic; - pwdata_0_d0 : in std_logic; - pwdata_2 : in std_logic; - pwdata_5 : in std_logic; - pwdata_6 : in std_logic; - pwdata_7 : in std_logic; - pwdata_8 : in std_logic; - pwdata_9 : in std_logic; - pwdata_10 : in std_logic; - pwdata_11 : in std_logic; - pirq : out std_logic_vector(2 to 2); - rcnt_RNI8FBM3 : out std_logic_vector(1 to 1); - rdata_2_0 : out std_logic; - pwdata_1_0 : in std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - paddr : in std_logic_vector(4 to 4); - rdata_2_m_3 : out std_logic; - rdata_2_m_4 : out std_logic; - rdata_2_m_2 : out std_logic; - brate_0 : out std_logic; - brate_10 : out std_logic; - brate_9 : out std_logic; - brate_8 : out std_logic; - brate_7 : out std_logic; - brate_6 : out std_logic; - brate_m_3 : out std_logic; - brate_m_2 : out std_logic; - brate_m_9 : out std_logic; - pwdata_0 : in std_logic_vector(11 downto 0); - rcnt_0 : out std_logic; - rcnt_1 : out std_logic; - rdata_17_m_0_d0 : out std_logic; - rdata_17_m_5 : out std_logic; - rdata_17_m_4 : out std_logic; - un1_uart1_34 : out std_logic; - rdata_17_m_0_4 : out std_logic; - rdata_iv_0_a2_3_0 : out std_logic_vector(7 to 7); - tcnt_0 : out std_logic; - tcnt_1 : out std_logic; - rdata_iv_2 : out std_logic_vector(3 downto 2); - rdata_iv_0_2 : out std_logic_vector(1 to 1); - prdata_6 : out std_logic; - prdata_0 : out std_logic; - prdata_9 : out std_logic; - paddr_0 : in std_logic_vector(4 to 4); - apbuart_VCC : in std_logic; - apbuart_GND : in std_logic; - rxd1_c : in std_logic; - lclk_c : in std_logic; - txd1_c : out std_logic; - N_227 : out std_logic; - thempty_1_m : out std_logic; - debug_m : out std_logic; - N_232 : in std_logic; - rdata60 : in std_logic; - frame : out std_logic; - rdata59 : in std_logic; - parerr_m : out std_logic; - rdata60_4 : out std_logic; - rdata62 : out std_logic; - N_6455_0 : in std_logic; - rdata59_4 : out std_logic; - parsel_m_0 : out std_logic; - ovf_m : out std_logic; - break_m : out std_logic; - N_223 : out std_logic; - N_220 : out std_logic; - rfifoirqen_m : out std_logic; - tfifoirqen_m : out std_logic; - N_156 : out std_logic; - rhalffull_1_m : out std_logic; - rdata_3_sqmuxa : out std_logic; - ctrl2 : in std_logic; - rstn : in std_logic; - tsemptyirqen_0 : out std_logic; - N_773 : in std_logic; - N_769 : in std_logic; - paren : out std_logic; - N_750 : in std_logic; - penable : in std_logic; - breakirqen : out std_logic; - delayirqen : out std_logic; - rdata_4_sqmuxa : out std_logic; - rdata_0_sqmuxa : out std_logic; - tcnt_i : out std_logic; - flow_m : out std_logic; - extclken_m : out std_logic; - rdata61 : in std_logic; - pwrite : in std_logic; - un1_apbi_8 : in std_logic; - rdata62_0 : out std_logic; - rdata60_1 : in std_logic; - rdata61_2 : in std_logic; - rdata60_4_0 : out std_logic - ); - -end apbuart; - -architecture DEF_ARCH of apbuart is - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component RAM512X18 - generic (MEMORYFILE:string := ""); - - port( RADDR8 : in std_logic := 'U'; - RADDR7 : in std_logic := 'U'; - RADDR6 : in std_logic := 'U'; - RADDR5 : in std_logic := 'U'; - RADDR4 : in std_logic := 'U'; - RADDR3 : in std_logic := 'U'; - RADDR2 : in std_logic := 'U'; - RADDR1 : in std_logic := 'U'; - RADDR0 : in std_logic := 'U'; - WADDR8 : in std_logic := 'U'; - WADDR7 : in std_logic := 'U'; - WADDR6 : in std_logic := 'U'; - WADDR5 : in std_logic := 'U'; - WADDR4 : in std_logic := 'U'; - WADDR3 : in std_logic := 'U'; - WADDR2 : in std_logic := 'U'; - WADDR1 : in std_logic := 'U'; - WADDR0 : in std_logic := 'U'; - WD17 : in std_logic := 'U'; - WD16 : in std_logic := 'U'; - WD15 : in std_logic := 'U'; - WD14 : in std_logic := 'U'; - WD13 : in std_logic := 'U'; - WD12 : in std_logic := 'U'; - WD11 : in std_logic := 'U'; - WD10 : in std_logic := 'U'; - WD9 : in std_logic := 'U'; - WD8 : in std_logic := 'U'; - WD7 : in std_logic := 'U'; - WD6 : in std_logic := 'U'; - WD5 : in std_logic := 'U'; - WD4 : in std_logic := 'U'; - WD3 : in std_logic := 'U'; - WD2 : in std_logic := 'U'; - WD1 : in std_logic := 'U'; - WD0 : in std_logic := 'U'; - RW0 : in std_logic := 'U'; - RW1 : in std_logic := 'U'; - WW0 : in std_logic := 'U'; - WW1 : in std_logic := 'U'; - PIPE : in std_logic := 'U'; - REN : in std_logic := 'U'; - WEN : in std_logic := 'U'; - RCLK : in std_logic := 'U'; - WCLK : in std_logic := 'U'; - RESET : in std_logic := 'U'; - RD17 : out std_logic; - RD16 : out std_logic; - RD15 : out std_logic; - RD14 : out std_logic; - RD13 : out std_logic; - RD12 : out std_logic; - RD11 : out std_logic; - RD10 : out std_logic; - RD9 : out std_logic; - RD8 : out std_logic; - RD7 : out std_logic; - RD6 : out std_logic; - RD5 : out std_logic; - RD4 : out std_logic; - RD3 : out std_logic; - RD2 : out std_logic; - RD1 : out std_logic; - RD0 : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal brate_1_sqmuxa_0, un1_apbi_2, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_12[0]\, \irqcnt[2]\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, \irqcnt[4]\, - \DWACT_ADD_CI_0_TMP[0]\, \irqcnt[1]\, N_45, - \un1_uart1[3]\, \un1_uart1[2]\, N_37, \un1_uart1[5]\, - \DWACT_FDEC_E[0]\, N_14, \un1_uart1[10]\, - \DWACT_FDEC_E[4]\, un1_apbi_1_i, \un1_apbi_1\, un1_apbi_6, - N_194, \thold[7]\, N_134, CO1, \rxclk[0]\, \rxclk[1]\, - extclken, \prdata[31]\, flow, \tshift_13[7]\, - \tshift_13_0_iv_0_0[7]\, twaddr_0_sqmuxa, - twaddr_0_sqmuxa_0, rxtick_0_0, tick, \rxclk[2]\, - rxtick_0_1, N_193, N_192, thold_32, \tcnt[2]\, - \rxstate_srsts_0_a3_0_0[2]\, rxtick, N_876, - \tshift_1_0_0[0]\, \tshift_1_0_a2_0[0]\, N_260, N_218, - irq_1_0, un4_thalffull_0, un4_rhalffull, \un1_uart1[34]\, - \rdata_iv_0_1[1]\, N_165, \rdata_iv_0_0[1]\, - traddr_1_sqmuxa, \thold[2]\, N_225, \rdata_iv_0[2]\, - \rdata_2_m[2]\, rirqen_m, \rdata_17_m_0[2]\, \brate_m[2]\, - tirqen, \rdata_iv_1[3]\, \rdata_17_m[3]\, \brate_m[3]\, - \rdata_2_m[3]\, un6_thempty_1, \tcnt_11[0]\, thempty_1, - \tcnt_11[1]\, SUM2_0_1, N_914, \rcnt[2]\, rraddr_0_sqmuxa, - SUM2_0_0, N_22, SUM1_0_0, N_913_i, irq_10_1, irq_5, - irq_10_0, rirqen_m_1, SUM1_0_0_0, irq_6_m_0, \delayirqen\, - irq10, rhold_1_0_sqmuxa_0, \rwaddr[0]\, \rwaddr[1]\, - rhold_2_0_sqmuxa_0, \thold[3]\, N_155, \thold[8]\, - \tshift_13_0_iv_0_0[6]\, txtick_1_sqmuxa, \tshift[6]\, - N_189, traddr_1_sqmuxa_0, \rdata62_0\, txtick_0_i_1, - \txclk[2]\, CO1_0, un1_apbi_2_0, \txstate_ns_i_0_0[0]\, - \txstate_ns_i_0_a2_3_1[0]\, N_209, txtick_1, txtick, - debug, frame_1_sqmuxa_0, \rxdb[0]\, frame_1_sqmuxa_1, - \rxstate_nss_i_0_0_0_tz_0[0]\, \rxstate[0]\, \rxstate[1]\, - tpar, N_247, \paren\, \txstate[0]\, \tshift[1]\, - dpar_4_m_0, N_906, dpar_4, \txstate_ns_i_0_1_tz_0[0]\, - break6_5, break6_3, \rshift[3]\, \rshift[0]\, break6_4, - break6_1, \rshift[2]\, \rshift[1]\, \rshift[6]\, - \rshift[4]\, \rshift[5]\, \rshift[7]\, - rwaddr_0_sqmuxa_1_1, dpar, rwaddr_0_sqmuxa_1_0, - tfifoirqen, \txstate_ns_i_0_a2_4_5[0]\, - \txstate_ns_i_0_a2_4_2[0]\, \txstate_ns_i_0_a2_4_3[0]\, - \tshift[8]\, \tshift[9]\, \tshift[7]\, - \txstate_ns_i_0_a2_4_1[0]\, \tshift[4]\, \tshift[5]\, - \txstate_ns_i_0_a2_4_0[0]\, \tshift[2]\, \tshift[3]\, - un4_rhalffull_0, rfifoirqen, I_5_0, \WADDR_REG1[1]\, - \traddr[1]\, N_5, \thold[4]\, \rdata_4_sqmuxa\, - \thold[5]\, tick_1, txen, tick_2_i, \tshift_13[4]\, N_184, - N_183, N_185, \tshift_13[1]\, N_175, N_174, N_176, - un1_apbi_5, \tshift_13[8]\, N_196, N_195, N_197, - tsemptyirqen, tsempty, tsempty_4, un6_thempty, CO1_1, - irq_1, irq_16_i, rhalffull_1, \tshift_13[6]\, \thold[6]\, - rxtick_RNO, rshift_0_sqmuxa_1, N_98, irqpend_0_sqmuxa, - irqpend_1_sqmuxa, irqpend_1, rirqen, irq_10_i, irq_6_m, - rirqen_m_0, break_0_sqmuxa, delayirqen_0, irq_14, irq_7_m, - irq_10_m, \rxstate_nss_i[0]\, N_78, - \rxstate_nss_i_0_0_0[0]\, N_897, rxdb_1, \un1_uart1[36]\, - \rxdb[1]\, N_86, N_204, N_205, ovf_0_sqmuxa, \rcnt_1\, - \rxstate_i[4]\, N_69, N_199, \tcnt[1]\, N_9, txtick_0, - un2_ctsn_1, irq_5_2, \thold[1]\, N_167, \tshift[0]\, - loopb, N_929, N_210, \txstate_ns_i_0_1[0]\, N_133, - N_210_1, N_17_i_0, N_172, N_171, N_170, \rxf[2]\, - \rxf[3]\, \rxf[4]\, N_143, N_214, N_243, \tshift_13[3]\, - N_181, N_180, N_182, \tshift_13[5]\, N_187, N_186, N_188, - \tshift_1[0]\, N_219, N_7, \WADDR_REG1[0]\, \traddr[0]\, - break6, N_898, N_88, N_206, N_207, N_142, rwaddr_0_sqmuxa, - rsempty, rcnt, \tshift_13[2]\, N_178, N_177, N_179, - rhold_2_0_sqmuxa, rwaddr_0_sqmuxa_0, rhold_1_0_sqmuxa, - \rxstate_nss_i_0_a3_0[0]\, CO1_i_o3_0, N_16, CO1_i_o3_0_0, - N_16_0, \txstate_ns_i_0_a2_2_0[0]\, \rxstate_nss[1]\, - \rxstate_RNO_0[3]\, \rxstate[3]\, \tcnt_i\, \tcnt[0]\, - CO1_2, N_9_0, N_649, breakirqen_1_sqmuxa, \DIN_REG1[0]\, - \DOUT_TMP[0]\, \DIN_REG1[1]\, \DOUT_TMP[1]\, - \DIN_REG1[2]\, \DOUT_TMP[2]\, \DIN_REG1[3]\, - \DOUT_TMP[3]\, \DIN_REG1[4]\, \DOUT_TMP[4]\, - \DIN_REG1[6]\, \DOUT_TMP[6]\, \DIN_REG1[7]\, - \DOUT_TMP[7]\, \brate[11]\, N_503, \brate[1]\, I_5_4, - N_504, \brate[2]\, I_9_4, \scaler_1[1]\, \scaler_1[2]\, - I_66_1, \un1_uart1[13]\, N_505, \brate[3]\, I_13_8, N_507, - \brate[5]\, I_24_4, N_508, I_31_3, N_509, I_38_1, N_510, - I_45_1, N_511, I_52_1, N_512, I_56_1, N_513, - \scaler_1[3]\, \scaler_1[5]\, \scaler_1[6]\, - \scaler_1[7]\, \scaler_1[8]\, \scaler_1[9]\, - \scaler_1[10]\, \scaler_1[11]\, \rdata_2[7]\, - \rdata_0_sqmuxa\, N_100, scaler_2_sqmuxa, N_479, - \rhold_0[6]\, \rhold_2[6]\, \rraddr[1]\, \rdata_2[6]\, - N_487, \rraddr[0]\, \rdata_2[3]\, break, \N_156\, - rdata_3_sqmuxa_net_1, \rdata_2[4]\, ovf, parsel, - \brate[4]\, N_502, \scaler_1[0]\, brate_1_sqmuxa, N_477, - N_485, N_480, N_488, N_506, I_20_4, \scaler_1[4]\, - \txstate_RNIURTC6[1]\, \rdata62\, tsempty_RNO_0, - \tcnt_RNO[2]\, \tcnt_RNO_0[1]\, \tcnt_RNO_0[0]\, - \rhold_1[6]\, \rhold_3[6]\, \rdata_2[5]\, N_478, N_486, - parerr, \rhold_0[5]\, \rhold_2[5]\, \DIN_REG1[5]\, - \DOUT_TMP[5]\, N_666, N_860, \rshift_RNO_0[5]\, N_484, - \rhold_1[3]\, \rhold_3[3]\, \rhold_1[5]\, \rhold_3[5]\, - \rhold_0_1[3]\, rhold_0_1_sqmuxa_1, \rhold_3_1[4]\, - rhold_3_1_sqmuxa_1, \rhold_3_1[6]\, N_973_i, - rxclk_1_sqmuxa_1, N_869, \rxclk_1[0]\, \rxclk_1[1]\, - \rxclk_1[2]\, N_161, N_476, \rhold_0[3]\, \rhold_2[3]\, - dpar_RNI4PT94, \rhold_1_1[4]\, \rhold_1[7]\, \rhold_3[7]\, - N_483, \rhold_1[2]\, \rhold_3[2]\, \rhold_0[7]\, - \rhold_2[7]\, N_475, \rhold_0[2]\, \rhold_2[2]\, - \rdata_2[2]\, \rhold_0_1[4]\, \rhold_1[4]\, \rhold_3[4]\, - \rhold_0[4]\, \rhold_2[4]\, \rshift_RNO_0[4]\, N_665, - \rshift_RNO_0[3]\, N_664, N_638, rsempty_1, rxstate_5, - N_216, rsempty_1_sqmuxa, N_442, N_897_1, N_441, dpar_m_1, - \irqcnt[5]\, N_643, irqpend, N_110, rxtick_0, irq_7, - break_1_sqmuxa, N_641, frame_1, frame_0_sqmuxa, N_644, - parerr_1, parerr_0_sqmuxa_1, N_108, N_112, parerr_5, - parerr_0_sqmuxa, break_1, break_0_sqmuxa_1, \irqcnt_1[5]\, - I_26, \irqcnt_1[4]\, I_24_5, \irqcnt_1[3]\, I_23, - \irqcnt_1[2]\, I_22, \irqcnt_1[1]\, I_21, \irqcnt_1[0]\, - \DWACT_ADD_CI_0_partial_sum[0]\, N_114, N_640, ovf_RNO_0, - N_645, \txclk[1]\, N_976_i_2, N_29, N_29_1, N_473, - \rhold_0[0]\, \rhold_2[0]\, N_481, \rhold_1[0]\, - \rhold_3[0]\, N_163, N_164, \rhold_1[1]\, \rhold_3[1]\, - \rhold_0[1]\, \rhold_2[1]\, N_27, N_25, N_801, N_801s, - tpar_3_i, \txstate[1]\, txtick_0_sqmuxa_1, tpar_1, - txstate_1, \txstate_ns[1]\, \tshift_13_0_iv[9]\, N_802s, - N_802, N_661, \rshift_RNO_0[0]\, \rhold_0_1[6]\, - \rhold_3_1[0]\, \rhold_3_1[3]\, \rhold_3_1[5]\, N_667, - \rshift_RNO_0[6]\, \un26_rxd[0]\, rhold_0_0_sqmuxa, - \un26_rxd[3]\, rhold_3_0_sqmuxa, N_668, \rshift_RNO_0[7]\, - dpar_1, parsel_m, N_140, \rxstate[2]\, N_875, N_893, - \rxstate_nss[2]\, \rhold_0_1[1]\, N_235, \rhold_0_1[7]\, - \rhold_0_1[2]\, \rshift_RNO_0[2]\, N_663, - \rshift_RNO_0[1]\, N_662, \rcnt[1]\, N_646, N_647, N_104, - N_106, \rcnt[0]\, N_940_1, \rcnt_RNO[0]\, \rcnt_RNO[1]\, - \rcnt_RNO[2]\, N_102, N_648, \rraddr_RNO[1]\, I_10_2, - \rraddr_RNO[0]\, \DWACT_ADD_CI_0_partial_sum_0[0]\, - \rwaddr_RNO[1]\, I_10_0, \rwaddr_RNO[0]\, - \DWACT_ADD_CI_0_partial_sum_1[0]\, N_37_0, I_10, N_35, - \DWACT_ADD_CI_0_partial_sum_2[0]\, N_33, I_10_1, N_31, - \DWACT_ADD_CI_0_partial_sum_3[0]\, \irqcnt[0]\, - \irqcnt[3]\, \twaddr[0]\, \twaddr[1]\, \rxf[0]\, \rxf[1]\, - \brate[10]\, \brate[9]\, \brate[8]\, \brate[7]\, - \brate[6]\, \brate[0]\, \un1_uart1[12]\, \un1_uart1[11]\, - \un1_uart1[9]\, \un1_uart1[8]\, \un1_uart1[7]\, - \un1_uart1[6]\, \un1_uart1[4]\, \tsemptyirqen_0\, - \breakirqen\, \frame\, N_4, \DWACT_FDEC_E[6]\, - \DWACT_FDEC_E[2]\, \DWACT_FDEC_E[5]\, N_11, - \DWACT_FDEC_E[3]\, N_19, N_24, N_29_0, \DWACT_FDEC_E[1]\, - N_34, N_42, \DWACT_ADD_CI_0_TMP_0[0]\, - \DWACT_ADD_CI_0_TMP_1[0]\, \DWACT_ADD_CI_0_TMP_2[0]\, - \DWACT_ADD_CI_0_TMP_3[0]\, \DOUT_TMP[8]\, \DOUT_TMP[9]\, - \DOUT_TMP[10]\, \DOUT_TMP[11]\, \DOUT_TMP[12]\, - \DOUT_TMP[13]\, \DOUT_TMP[14]\, \DOUT_TMP[15]\, - \DOUT_TMP[16]\, \DOUT_TMP[17]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - brate_0 <= \brate[0]\; - brate_10 <= \brate[10]\; - brate_9 <= \brate[9]\; - brate_8 <= \brate[8]\; - brate_7 <= \brate[7]\; - brate_6 <= \brate[6]\; - rcnt_0 <= \rcnt[0]\; - rcnt_1 <= \rcnt[1]\; - un1_uart1_34 <= \un1_uart1[36]\; - tcnt_0 <= \tcnt[0]\; - tcnt_1 <= \tcnt[1]\; - prdata_9 <= \prdata[31]\; - frame <= \frame\; - rdata62 <= \rdata62\; - N_156 <= \N_156\; - rdata_3_sqmuxa <= rdata_3_sqmuxa_net_1; - tsemptyirqen_0 <= \tsemptyirqen_0\; - paren <= \paren\; - breakirqen <= \breakirqen\; - delayirqen <= \delayirqen\; - rdata_4_sqmuxa <= \rdata_4_sqmuxa\; - rdata_0_sqmuxa <= \rdata_0_sqmuxa\; - tcnt_i <= \tcnt_i\; - rdata62_0 <= \rdata62_0\; - - \r.rxen_RNIKPF53\ : NOR2A - port map(A => txen, B => brate_1_sqmuxa_0, Y => - scaler_2_sqmuxa); - - \r.thold_tile_I_1_RNI4VRO\ : MX2 - port map(A => \DIN_REG1[5]\, B => \DOUT_TMP[5]\, S => N_7, - Y => \thold[6]\); - - \r.irqcnt_RNO[0]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => - \DWACT_ADD_CI_0_partial_sum[0]\, Y => \irqcnt_1[0]\); - - \r.flow_RNICI551\ : OR2B - port map(A => flow, B => N_210_1, Y => un2_ctsn_1); - - \r.txstate_RNO_1[1]\ : AO1C - port map(A => \txstate[0]\, B => \txstate[1]\, C => N_214, - Y => \txstate_ns[1]\); - - \r.tshift_RNO_0[4]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[4]\, Y => N_184); - - \r.rsempty_RNO_2\ : OR2B - port map(A => frame_1_sqmuxa_1, B => \rxstate_i[4]\, Y => - rxstate_5); - - \r.rxstate_i[4]\ : DFN1 - port map(D => \rxstate_nss_i[0]\, CLK => lclk_c, Q => - \rxstate_i[4]\); - - \un1_r.irqcnt_I_33\ : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - \r.txtick_RNI1BJL2\ : AO1B - port map(A => txtick_0, B => N_133, C => txtick, Y => - txtick_1_sqmuxa); - - \r.thold_tile_I_1_RNI3RRO\ : MX2 - port map(A => \DIN_REG1[4]\, B => \DOUT_TMP[4]\, S => N_7, - Y => \thold[5]\); - - \r.rxstate_RNO[3]\ : OA1A - port map(A => rshift_0_sqmuxa_1, B => \rxstate_RNO_0[3]\, C - => rstn, Y => \rxstate_nss[1]\); - - \r.thold_tile_I_1_RNIHCSI4\ : OR3C - port map(A => N_155, B => \thold[6]\, C => \rdata_4_sqmuxa\, - Y => rdata_17_m_5); - - \r.tick_RNO\ : NOR3 - port map(A => txen, B => extclken, C => tick_2_i, Y => - tick_1); - - \r.tcnt_RNIQEOL[2]\ : NOR3 - port map(A => \tcnt[2]\, B => \tcnt[0]\, C => \tcnt[1]\, Y - => thempty_1); - - \r.flow_RNII2133\ : NAND2 - port map(A => \prdata[31]\, B => flow, Y => flow_m); - - \r.scaler_RNO[1]\ : MX2A - port map(A => N_503, B => pwdata_0(1), S => - brate_1_sqmuxa_0, Y => \scaler_1[1]\); - - \r.tshift_RNO_1[6]\ : OR3B - port map(A => txtick, B => \tshift[7]\, C => N_133, Y => - N_189); - - \r.rwaddr_RNI3BBD1_0[1]\ : NOR2B - port map(A => rwaddr_0_sqmuxa_0, B => \un26_rxd[0]\, Y => - rhold_3_1_sqmuxa_1); - - un4_scaler_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \un1_uart1[11]\, C - => \un1_uart1[12]\, Y => N_4); - - \r.scaler[2]\ : DFN1E0 - port map(D => \scaler_1[2]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[4]\); - - rdata_1_sqmuxa_i_o2 : OR2 - port map(A => un1_apbi_5, B => rdata59, Y => \N_156\); - - \r.brate[9]\ : DFN1E1 - port map(D => pwdata_9, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[9]\); - - \r.rshift_RNIL9DD1[6]\ : MX2 - port map(A => pwdata_0(6), B => \rshift[6]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_0_1[6]\); - - \rdata_3_sqmuxa\ : NOR2A - port map(A => rdata61, B => un1_apbi_5, Y => - rdata_3_sqmuxa_net_1); - - \r.irq_RNO_1\ : OA1C - port map(A => un4_thalffull_0, B => \tcnt_i\, C => - un4_rhalffull, Y => irq_1_0); - - \r.txstate_RNO_0[1]\ : MX2 - port map(A => \txstate[1]\, B => \txstate_ns[1]\, S => - txtick, Y => N_802); - - \r.rxdb[1]\ : DFN1 - port map(D => \rxdb[0]\, CLK => lclk_c, Q => \rxdb[1]\); - - \r.parsel_RNILR733\ : OR2B - port map(A => parsel, B => \prdata[31]\, Y => parsel_m_0); - - \r.tcnt_RNO[1]\ : NOR2B - port map(A => \tcnt_11[1]\, B => rstn, Y => \tcnt_RNO_0[1]\); - - \un1_r.irqcnt_I_22\ : XOR2 - port map(A => \irqcnt[2]\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_22); - - \r.break_RNO_2\ : OA1C - port map(A => break_0_sqmuxa, B => frame_1_sqmuxa_1, C => - break_1_sqmuxa, Y => break_0_sqmuxa_1); - - \r.rhold_0_RNIEH39[3]\ : MX2C - port map(A => \rhold_0[3]\, B => \rhold_2[3]\, S => - \rraddr[1]\, Y => N_476); - - \r.rcnt_RNI1K6F3[1]\ : OR2 - port map(A => rhalffull_1, B => \N_156\, Y => rhalffull_1_m); - - \r.txstate_RNO_0[0]\ : MX2 - port map(A => \txstate[0]\, B => N_929, S => txtick, Y => - N_801); - - \r.txd_RNO\ : OR3 - port map(A => debug, B => \tshift[0]\, C => loopb, Y => - N_167); - - \uartop.un1_apbi_6\ : NAND2 - port map(A => pwrite, B => un1_apbi_2, Y => un1_apbi_6); - - \r.scaler_RNO[4]\ : MX2A - port map(A => N_506, B => pwdata_0(4), S => - brate_1_sqmuxa_0, Y => \scaler_1[4]\); - - \r.parerr_RNO_0\ : MX2 - port map(A => parerr_1, B => parerr, S => parerr_0_sqmuxa_1, - Y => N_644); - - \un1_r.rcnt_1_0_1_CO1_i_o3_0\ : AO1B - port map(A => N_16, B => N_913_i, C => rraddr_0_sqmuxa, Y - => CO1_i_o3_0); - - un4_scaler_I_24 : XNOR2 - port map(A => N_34, B => \un1_uart1[7]\, Y => I_24_4); - - \r.rhold_3[1]\ : DFN1E0 - port map(D => \rhold_0_1[1]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[1]\); - - \r.rhold_0_RNO[4]\ : MX2 - port map(A => pwdata_1_3, B => \rshift[4]\, S => - rhold_0_1_sqmuxa_1, Y => \rhold_0_1[4]\); - - \r.brate[10]\ : DFN1E1 - port map(D => pwdata_10, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[10]\); - - \r.brate[4]\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => - brate_1_sqmuxa, Q => \brate[4]\); - - \v.tshift_13_0_iv_0[7]\ : NAND2 - port map(A => N_194, B => \tshift_13_0_iv_0_0[7]\, Y => - \tshift_13[7]\); - - \r.rshift_RNO_0[1]\ : MX2 - port map(A => \rshift[2]\, B => \rshift[1]\, S => N_860, Y - => N_662); - - \r.scaler_RNO_0[8]\ : MX2C - port map(A => \brate[8]\, B => I_45_1, S => tick_2_i, Y => - N_510); - - \r.rxdb_RNO_2[0]\ : OR3 - port map(A => loopb, B => \rxf[4]\, C => N_143, Y => N_170); - - \r.rshift_RNISEI8[1]\ : NOR2B - port map(A => break6_5, B => break6_4, Y => break6); - - \r.txclk_RNO[1]\ : XA1B - port map(A => N_976_i_2, B => \txclk[1]\, C => N_29_1, Y - => N_27); - - \r.rxen_RNO_0\ : MX2 - port map(A => \un1_uart1[36]\, B => pwdata_0(0), S => - breakirqen_1_sqmuxa, Y => N_647); - - \r.txstate_RNO_3[0]\ : OA1 - port map(A => \txstate_ns_i_0_a2_2_0[0]\, B => - \txstate_ns_i_0_1_tz_0[0]\, C => N_133, Y => - \txstate_ns_i_0_1[0]\); - - \r.scaler_RNO[8]\ : MX2A - port map(A => N_510, B => pwdata_0(8), S => - brate_1_sqmuxa_0, Y => \scaler_1[8]\); - - \r.rxstate_RNO_1[1]\ : NOR2 - port map(A => rxtick, B => \rxstate[1]\, Y => N_207); - - \r.rxdb_RNO_0[0]\ : OR3 - port map(A => \rxf[2]\, B => \rxf[3]\, C => loopb, Y => - N_172); - - \r.tshift_RNI6SH5[6]\ : NOR2B - port map(A => \txstate_ns_i_0_a2_4_2[0]\, B => - \txstate_ns_i_0_a2_4_3[0]\, Y => - \txstate_ns_i_0_a2_4_5[0]\); - - \r.rxdb_RNIKLUE[0]\ : OR2 - port map(A => \rxdb[0]\, B => frame_1_sqmuxa_1, Y => - frame_1_sqmuxa_0); - - \r.tshift_RNI5UO2[8]\ : NOR2B - port map(A => \tshift[8]\, B => \tshift[9]\, Y => - \txstate_ns_i_0_a2_4_3[0]\); - - \r.thold_tile_I_1\ : RAM512X18 - port map(RADDR8 => apbuart_GND, RADDR7 => apbuart_GND, - RADDR6 => apbuart_GND, RADDR5 => apbuart_GND, RADDR4 => - apbuart_GND, RADDR3 => apbuart_GND, RADDR2 => apbuart_GND, - RADDR1 => N_37_0, RADDR0 => N_35, WADDR8 => apbuart_GND, - WADDR7 => apbuart_GND, WADDR6 => apbuart_GND, WADDR5 => - apbuart_GND, WADDR4 => apbuart_GND, WADDR3 => apbuart_GND, - WADDR2 => apbuart_GND, WADDR1 => \twaddr[1]\, WADDR0 => - \twaddr[0]\, WD17 => apbuart_GND, WD16 => apbuart_GND, - WD15 => apbuart_GND, WD14 => apbuart_GND, WD13 => - apbuart_GND, WD12 => apbuart_GND, WD11 => apbuart_GND, - WD10 => apbuart_GND, WD9 => apbuart_GND, WD8 => - apbuart_GND, WD7 => pwdata_7, WD6 => pwdata_6, WD5 => - pwdata_5, WD4 => pwdata_1_3, WD3 => pwdata_1_2, WD2 => - pwdata_2, WD1 => pwdata_1_0, WD0 => pwdata_0_d0, RW0 => - apbuart_VCC, RW1 => apbuart_GND, WW0 => apbuart_VCC, WW1 - => apbuart_GND, PIPE => apbuart_GND, REN => apbuart_GND, - WEN => un1_apbi_1_i, RCLK => lclk_c, WCLK => lclk_c, - RESET => apbuart_VCC, RD17 => \DOUT_TMP[17]\, RD16 => - \DOUT_TMP[16]\, RD15 => \DOUT_TMP[15]\, RD14 => - \DOUT_TMP[14]\, RD13 => \DOUT_TMP[13]\, RD12 => - \DOUT_TMP[12]\, RD11 => \DOUT_TMP[11]\, RD10 => - \DOUT_TMP[10]\, RD9 => \DOUT_TMP[9]\, RD8 => - \DOUT_TMP[8]\, RD7 => \DOUT_TMP[7]\, RD6 => \DOUT_TMP[6]\, - RD5 => \DOUT_TMP[5]\, RD4 => \DOUT_TMP[4]\, RD3 => - \DOUT_TMP[3]\, RD2 => \DOUT_TMP[2]\, RD1 => \DOUT_TMP[1]\, - RD0 => \DOUT_TMP[0]\); - - \v.tshift_13_0_iv_0_a2_1[7]\ : OR2A - port map(A => \thold[7]\, B => N_134, Y => N_194); - - \r.loopb_RNI4NC73\ : OR2B - port map(A => loopb, B => \prdata[31]\, Y => N_220); - - \r.scaler[0]\ : DFN1E0 - port map(D => \scaler_1[0]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[2]\); - - \r.rxf[4]\ : DFN1E1 - port map(D => \rxf[3]\, CLK => lclk_c, E => tick, Q => - \rxf[4]\); - - \uartop.v.tcnt_11_0_0_1_CO1_i_o3_0\ : AO1C - port map(A => \tcnt[1]\, B => N_16_0, C => N_22, Y => - CO1_i_o3_0_0); - - \r.rhold_2[3]\ : DFN1E0 - port map(D => \rhold_3_1[3]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[3]\); - - \r.parerr_RNO_3\ : NOR2 - port map(A => parerr, B => dpar, Y => parerr_5); - - \r.thold_tile_I_1_RNI4KUK1\ : NOR2B - port map(A => \thold[7]\, B => N_155, Y => rdata_17_m_0_4); - - \r.scaler[6]\ : DFN1E0 - port map(D => \scaler_1[6]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[8]\); - - \r.thold_tile_I_1_RNI53SO\ : MX2 - port map(A => \DIN_REG1[6]\, B => \DOUT_TMP[6]\, S => N_7, - Y => \thold[7]\); - - \r.thold_tile_DIN_REG1[1]\ : DFN1 - port map(D => pwdata_1_0, CLK => lclk_c, Q => \DIN_REG1[1]\); - - \r.irqcnt_RNO[3]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_23, Y => - \irqcnt_1[3]\); - - \r.txstate_RNIVPSC_0[1]\ : NOR2 - port map(A => \txstate[1]\, B => \txstate[0]\, Y => N_133); - - \r.rhold_0_RNIGP39[4]\ : MX2C - port map(A => \rhold_0[4]\, B => \rhold_2[4]\, S => - \rraddr[1]\, Y => N_477); - - \r.thold_tile_DIN_REG1[7]\ : DFN1 - port map(D => pwdata_7, CLK => lclk_c, Q => \DIN_REG1[7]\); - - \un1_r.rcnt_1_0_1_SUM2_0_1\ : XOR3 - port map(A => N_914, B => \rcnt[2]\, C => rraddr_0_sqmuxa, - Y => SUM2_0_1); - - \r.tshift_RNO[9]\ : OA1A - port map(A => txtick_1_sqmuxa, B => \tshift[9]\, C => N_134, - Y => \tshift_13_0_iv[9]\); - - \r.rshift_RNIQJ42[6]\ : NOR2 - port map(A => \rshift[6]\, B => \rshift[4]\, Y => break6_3); - - \r.rhold_2[2]\ : DFN1E0 - port map(D => \rhold_0_1[2]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[2]\); - - \r.scaler_RNO_0[9]\ : MX2C - port map(A => \brate[9]\, B => I_52_1, S => tick_2_i, Y => - N_511); - - \r.brate[6]\ : DFN1E1 - port map(D => pwdata_6, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[6]\); - - \r.scaler_RNO[10]\ : MX2A - port map(A => N_512, B => pwdata_0(10), S => - brate_1_sqmuxa_0, Y => \scaler_1[10]\); - - \r.scaler[9]\ : DFN1E0 - port map(D => \scaler_1[9]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[11]\); - - \r.brate[2]\ : DFN1E1 - port map(D => pwdata_2, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[2]\); - - \r.txtick_RNO\ : NOR2B - port map(A => txtick_0_i_1, B => N_134, Y => N_98); - - un1_apbi_1 : NOR3B - port map(A => pwrite, B => un1_apbi_2, C => thold_32, Y => - \un1_apbi_1\); - - \r.brate_RNIASBR7[2]\ : AOI1B - port map(A => \rdata_17_m_0[2]\, B => \rdata_4_sqmuxa\, C - => \brate_m[2]\, Y => \rdata_iv_0[2]\); - - \r.irqpend_RNO_1\ : NOR3A - port map(A => rirqen, B => un4_rhalffull, C => - irqpend_0_sqmuxa, Y => irqpend_1); - - \r.irqpend_RNO\ : NOR2B - port map(A => N_643, B => rstn, Y => N_110); - - \r.rirqen\ : DFN1E1 - port map(D => pwdata_2, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => rirqen); - - \r.rsempty_RNO_0\ : MX2 - port map(A => rsempty, B => rsempty_1, S => rxstate_5, Y - => N_638); - - \r.thold_tile_I_1_RNI0FRO\ : MX2 - port map(A => \DIN_REG1[1]\, B => \DOUT_TMP[1]\, S => N_7, - Y => \thold[2]\); - - \r.txclk_RNO_0[0]\ : OR2B - port map(A => N_976_i_2, B => N_134, Y => N_199); - - \r.parerr_RNO_1\ : MX2B - port map(A => pwdata_0(5), B => parerr_5, S => - parerr_0_sqmuxa, Y => parerr_1); - - \r.rshift_RNO_0[4]\ : MX2 - port map(A => \rshift[5]\, B => \rshift[4]\, S => N_860, Y - => N_665); - - \r.rxstate_i_RNIVC7N[4]\ : OR2B - port map(A => rshift_0_sqmuxa_1, B => rstn, Y => N_869); - - \r.rshift_RNO[5]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_666, Y => - \rshift_RNO_0[5]\); - - \r.irqcnt[4]\ : DFN1 - port map(D => \irqcnt_1[4]\, CLK => lclk_c, Q => - \irqcnt[4]\); - - \r.txstate_RNI831J2[1]\ : OR2A - port map(A => N_133, B => txtick_0, Y => N_134); - - \un1_r.irqcnt_I_26\ : XOR2 - port map(A => \irqcnt[5]\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_26); - - un4_scaler_I_12 : OR3 - port map(A => \un1_uart1[2]\, B => \un1_uart1[3]\, C => - \un1_uart1[4]\, Y => N_42); - - \r.tsempty_RNILMPS2\ : MX2C - port map(A => txtick_0, B => tsempty, S => txstate_1, Y => - tsempty_4); - - un4_scaler_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \r.tcnt_RNIT9GE[2]\ : OR2 - port map(A => \tcnt[2]\, B => \tcnt[1]\, Y => \tcnt_i\); - - \r.txstate_RNO[0]\ : NOR2B - port map(A => N_801, B => rstn, Y => N_801s); - - \r.rraddr_RNO[1]\ : NOR2B - port map(A => I_10_2, B => rstn, Y => \rraddr_RNO[1]\); - - \uartop.v.tcnt_11_0_0_1_CO0_i_a3_0\ : NOR2 - port map(A => twaddr_0_sqmuxa, B => \tcnt[0]\, Y => N_16_0); - - \r.txstate_RNIURTC6[1]\ : AO1A - port map(A => N_134, B => rstn, C => traddr_1_sqmuxa, Y => - \txstate_RNIURTC6[1]\); - - \r.rxstate_RNO[0]\ : NOR3A - port map(A => rstn, B => N_204, C => N_205, Y => N_86); - - \r.rraddr_RNIRPSI[0]\ : MX2C - port map(A => N_163, B => N_164, S => \rraddr[0]\, Y => - N_165); - - \r.brate_RNIU3G83[4]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[4]\, Y => - brate_m_2); - - \r.scaler_RNO[0]\ : MX2A - port map(A => N_502, B => pwdata_0(0), S => - brate_1_sqmuxa_0, Y => \scaler_1[0]\); - - \r.rwaddr_RNI3BBD1[1]\ : NOR2B - port map(A => rwaddr_0_sqmuxa_0, B => \un26_rxd[3]\, Y => - rhold_0_1_sqmuxa_1); - - \r.rshift_RNIIDDD1[3]\ : MX2 - port map(A => pwdata_1_2, B => \rshift[3]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_3_1[3]\); - - \r.rxstate_RNO_1[2]\ : AO1A - port map(A => \rshift[0]\, B => rxtick, C => N_78, Y => - N_893); - - \r.extclken\ : DFN1 - port map(D => N_100, CLK => lclk_c, Q => extclken); - - \r.tshift_RNO[3]\ : OR3C - port map(A => N_181, B => N_180, C => N_182, Y => - \tshift_13[3]\); - - \r.rhold_1_RNIMP49[4]\ : MX2C - port map(A => \rhold_1[4]\, B => \rhold_3[4]\, S => - \rraddr[1]\, Y => N_485); - - \r.loopb\ : DFN1E1 - port map(D => pwdata_7, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => loopb); - - \r.rxstate_RNINFI6[2]\ : OR2A - port map(A => \rxstate[2]\, B => \rshift[0]\, Y => N_140); - - \r.tshift_RNO_2[4]\ : OR2A - port map(A => \thold[4]\, B => N_134, Y => N_185); - - \r.txclk[2]\ : DFN1E1 - port map(D => N_29, CLK => lclk_c, E => N_25, Q => - \txclk[2]\); - - \r.rhold_0[6]\ : DFN1E0 - port map(D => \rhold_0_1[6]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[6]\); - - \r.brate_RNIN3SP7[1]\ : AOI1B - port map(A => traddr_1_sqmuxa, B => \thold[2]\, C => N_225, - Y => \rdata_iv_0_0[1]\); - - \v.twaddr_0_sqmuxa_RNO\ : OR2 - port map(A => thold_32, B => \tcnt[2]\, Y => - twaddr_0_sqmuxa_0); - - \r.irqcnt_RNIF1F[5]\ : NOR2B - port map(A => \irqcnt[5]\, B => \irqcnt[4]\, Y => irq10); - - \r.scaler_RNO_0[3]\ : MX2C - port map(A => \brate[3]\, B => I_13_8, S => tick_2_i, Y => - N_505); - - \r.rcnt_RNI6ECJ3[1]\ : NOR3 - port map(A => un1_apbi_5, B => rcnt, C => ctrl2, Y => - rraddr_0_sqmuxa); - - \r.rhold_3[0]\ : DFN1E0 - port map(D => \rhold_3_1[0]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[0]\); - - \r.rcnt_RNO[0]\ : XA1 - port map(A => N_940_1, B => rraddr_0_sqmuxa, C => rstn, Y - => \rcnt_RNO[0]\); - - \r.rhold_0_RNII149[5]\ : MX2C - port map(A => \rhold_0[5]\, B => \rhold_2[5]\, S => - \rraddr[1]\, Y => N_478); - - \r.tpar_RNO_1\ : XNOR2 - port map(A => \tshift[1]\, B => tpar, Y => tpar_3_i); - - rdata_0_sqmuxa_0_a2_0 : OR2A - port map(A => un1_apbi_8, B => un1_apbi_5, Y => N_235); - - \r.rhold_0[0]\ : DFN1E0 - port map(D => \rhold_3_1[0]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[0]\); - - \r.txen_RNILLTDE\ : AOI1B - port map(A => \un1_uart1[34]\, B => \prdata[31]\, C => - \rdata_iv_0_1[1]\, Y => rdata_iv_0_2(1)); - - \uartop.rdata60_4\ : OR2 - port map(A => rdata61_2, B => rdata60_1, Y => rdata60_4); - - \r.rxstate_i_RNO_2[4]\ : AOI1B - port map(A => rxtick, B => \rxdb[0]\, C => \rxstate[3]\, Y - => \rxstate_nss_i_0_a3_0[0]\); - - \r.tpar_RNO_0\ : OR2A - port map(A => N_134, B => N_247, Y => txtick_0_sqmuxa_1); - - \r.rhold_1[6]\ : DFN1E0 - port map(D => \rhold_0_1[6]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[6]\); - - un4_scaler_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \un1_uart1[8]\, Y => N_24); - - \r.rraddr[0]\ : DFN1 - port map(D => \rraddr_RNO[0]\, CLK => lclk_c, Q => - \rraddr[0]\); - - \r.delayirqen_RNIGVAM\ : OR3B - port map(A => \rxdb[0]\, B => \delayirqen\, C => - frame_1_sqmuxa_1, Y => irqpend_0_sqmuxa); - - \uartop.v.irq_5_2\ : NOR3B - port map(A => pwrite, B => un1_apbi_2, C => \rdata62\, Y - => irq_5_2); - - \r.tsempty_RNO\ : OR2B - port map(A => tsempty_4, B => rstn, Y => tsempty_RNO_0); - - un4_scaler_I_45 : XNOR2 - port map(A => N_19, B => \un1_uart1[10]\, Y => I_45_1); - - \r.irqcnt_RNO[1]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_21, Y => - \irqcnt_1[1]\); - - \r.scaler_RNO_0[10]\ : MX2C - port map(A => \brate[10]\, B => I_56_1, S => tick_2_i, Y - => N_512); - - \r.irqpend_RNIP55E\ : NOR2B - port map(A => irqpend, B => \delayirqen\, Y => delayirqen_0); - - \r.rxstate_RNIT70B[2]\ : OR2 - port map(A => \rxstate[2]\, B => \rxstate[1]\, Y => N_906); - - \r.rhold_3[2]\ : DFN1E0 - port map(D => \rhold_0_1[2]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[2]\); - - \r.scaler_RNO_0[0]\ : MX2A - port map(A => \brate[0]\, B => \un1_uart1[2]\, S => - tick_2_i, Y => N_502); - - \r.rxf_RNO[3]\ : MX2 - port map(A => \rxf[3]\, B => \rxf[2]\, S => tick, Y => - N_161); - - \r.txstate_RNO_2[1]\ : OR3B - port map(A => N_243, B => N_260, C => \tshift[1]\, Y => - N_214); - - \r.ovf_RNO_0\ : MX2 - port map(A => ovf, B => pwdata_1_3, S => break_1_sqmuxa, Y - => N_645); - - \r.rraddr_RNIFAVI[0]\ : MX2C - port map(A => N_479, B => N_487, S => \rraddr[0]\, Y => - \rdata_2[6]\); - - \r.frame_RNO_1\ : AO1D - port map(A => frame_1_sqmuxa_0, B => break6, C => - pwdata_0(6), Y => frame_1); - - \r.brate[8]\ : DFN1E1 - port map(D => pwdata_8, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[8]\); - - \r.rshift[5]\ : DFN1 - port map(D => \rshift_RNO_0[5]\, CLK => lclk_c, Q => - \rshift[5]\); - - \r.debug\ : DFN1E1 - port map(D => pwdata_11, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => debug); - - un2_rxclk_1_SUM2_0 : AX1E - port map(A => \rxclk[0]\, B => \rxclk[1]\, C => \rxclk[2]\, - Y => N_973_i); - - \r.rshift_RNO[6]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_667, Y => - \rshift_RNO_0[6]\); - - \r.tshift_RNI1UO2[6]\ : NOR2B - port map(A => \tshift[6]\, B => \tshift[7]\, Y => - \txstate_ns_i_0_a2_4_2[0]\); - - \r.rxstate[1]\ : DFN1 - port map(D => N_88, CLK => lclk_c, Q => \rxstate[1]\); - - \r.rwaddr[1]\ : DFN1 - port map(D => \rwaddr_RNO[1]\, CLK => lclk_c, Q => - \rwaddr[1]\); - - \uartop.rdata62_0_a2_0\ : OR2B - port map(A => un1_apbi_8, B => paddr_0(4), Y => \rdata62_0\); - - \r.tshift[5]\ : DFN1 - port map(D => \tshift_13[5]\, CLK => lclk_c, Q => - \tshift[5]\); - - \v.tshift_13_0_iv_0_RNO_0[7]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[7]\, Y => N_193); - - \r.rxclk_RNO[0]\ : NOR2 - port map(A => \rxclk[0]\, B => N_869, Y => \rxclk_1[0]\); - - un4_scaler_I_38 : XNOR2 - port map(A => N_24, B => \un1_uart1[9]\, Y => I_38_1); - - \r.rsempty_RNO_1\ : MX2C - port map(A => N_442, B => N_897_1, S => N_441, Y => - rsempty_1); - - \r.rxstate_RNINPR6[0]\ : NOR2A - port map(A => rstn, B => \rxstate[0]\, Y => N_897_1); - - \r.irq_RNO_9\ : NOR3B - port map(A => break_0_sqmuxa, B => irq_10_i, C => - frame_1_sqmuxa_1, Y => irq_10_m); - - \uartop.rdata59_4\ : NOR2 - port map(A => rdata61_2, B => N_6455_0, Y => rdata59_4); - - \r.tshift_RNISN3B[2]\ : NOR3C - port map(A => \txstate_ns_i_0_a2_4_1[0]\, B => - \txstate_ns_i_0_a2_4_0[0]\, C => - \txstate_ns_i_0_a2_4_5[0]\, Y => N_260); - - \r.rxtick_RNO\ : NOR2B - port map(A => rxtick_0_1, B => rshift_0_sqmuxa_1, Y => - rxtick_RNO); - - \r.flow\ : DFN1 - port map(D => N_102, CLK => lclk_c, Q => flow); - - \r.rcnt_RNO[1]\ : XA1 - port map(A => N_9_0, B => SUM1_0_0, C => rstn, Y => - \rcnt_RNO[1]\); - - GND_i : GND - port map(Y => \GND\); - - \r.txtick_RNIO1FF_0\ : NOR2B - port map(A => txtick, B => N_243, Y => N_247); - - \uartop.v.tcnt_11_0_0_1_SUM2_0_0\ : XOR2 - port map(A => \tcnt[2]\, B => N_22, Y => SUM2_0_0); - - \r.rfifoirqen\ : DFN1E1 - port map(D => pwdata_10, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => rfifoirqen); - - \r.rshift_RNO_0[7]\ : MX2 - port map(A => \rxdb[0]\, B => \rshift[7]\, S => N_860, Y - => N_668); - - \r.rhold_0_RNI8P29[0]\ : MX2C - port map(A => \rhold_0[0]\, B => \rhold_2[0]\, S => - \rraddr[1]\, Y => N_473); - - \r.txen\ : DFN1 - port map(D => N_106, CLK => lclk_c, Q => \un1_uart1[34]\); - - \r.rxf[1]\ : DFN1 - port map(D => \rxf[0]\, CLK => lclk_c, Q => \rxf[1]\); - - \r.rwaddr_RNIDEB1_2[1]\ : NOR2 - port map(A => \rwaddr[1]\, B => \rwaddr[0]\, Y => - \un26_rxd[3]\); - - \r.tshift_RNO_1[5]\ : OR3B - port map(A => txtick, B => \tshift[6]\, C => N_133, Y => - N_186); - - \r.tcnt[0]\ : DFN1 - port map(D => \tcnt_RNO_0[0]\, CLK => lclk_c, Q => - \tcnt[0]\); - - \un1_r.rwaddr_I_8\ : XOR2 - port map(A => \rwaddr[0]\, B => dpar_RNI4PT94, Y => - \DWACT_ADD_CI_0_partial_sum_1[0]\); - - \r.rxstate_RNO_1[0]\ : NOR2 - port map(A => rxtick, B => \rxstate[0]\, Y => N_205); - - \r.rhold_2[4]\ : DFN1E0 - port map(D => \rhold_1_1[4]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[4]\); - - \r.break_RNO_1\ : AO1A - port map(A => frame_1_sqmuxa_1, B => break_0_sqmuxa, C => - pwdata_1_2, Y => break_1); - - \r.rraddr_RNIT6TG3[0]\ : OR2B - port map(A => \rdata_2[6]\, B => \rdata_0_sqmuxa\, Y => - rdata_2_m_4); - - \r.brate[11]\ : DFN1E1 - port map(D => pwdata_11, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[11]\); - - \r.frame_RNO_2\ : OA1B - port map(A => break6, B => frame_1_sqmuxa_0, C => - break_1_sqmuxa, Y => frame_0_sqmuxa); - - \r.tshift[8]\ : DFN1 - port map(D => \tshift_13[8]\, CLK => lclk_c, Q => - \tshift[8]\); - - \r.rxclk_RNO[1]\ : XA1B - port map(A => \rxclk[0]\, B => \rxclk[1]\, C => N_869, Y - => \rxclk_1[1]\); - - \r.rxstate_RNIM7FK[2]\ : OAI1 - port map(A => N_876, B => \rxstate[2]\, C => rxtick, Y => - N_860); - - un4_scaler_I_5 : XNOR2 - port map(A => \un1_uart1[2]\, B => \un1_uart1[3]\, Y => - I_5_4); - - \r.txen_RNO_0\ : MX2 - port map(A => \un1_uart1[34]\, B => pwdata_1_0, S => - breakirqen_1_sqmuxa, Y => N_646); - - \r.brate_RNISRF83[2]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[2]\, Y => - \brate_m[2]\); - - \r.scaler[7]\ : DFN1E0 - port map(D => \scaler_1[7]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[9]\); - - \r.scaler_RNO_0[7]\ : MX2C - port map(A => \brate[7]\, B => I_38_1, S => tick_2_i, Y => - N_509); - - \r.tsemptyirqen\ : DFN1E1 - port map(D => pwdata_14, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => \tsemptyirqen_0\); - - \r.rwaddr_RNO[1]\ : NOR2B - port map(A => I_10_0, B => rstn, Y => \rwaddr_RNO[1]\); - - rdata_0_sqmuxa_0_a2 : NOR2 - port map(A => N_235, B => paddr(4), Y => \rdata_0_sqmuxa\); - - \r.rxstate_i_RNO[4]\ : OR3C - port map(A => N_78, B => \rxstate_nss_i_0_0_0[0]\, C => - N_897, Y => \rxstate_nss_i[0]\); - - \r.rhold_2[6]\ : DFN1E0 - port map(D => \rhold_0_1[6]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[6]\); - - \r.txclk[0]\ : DFN1E1 - port map(D => N_69, CLK => lclk_c, E => N_25, Q => - N_976_i_2); - - \r.rsempty_RNO\ : OR2A - port map(A => rstn, B => N_638, Y => N_216); - - \un1_r.rwaddr_I_10\ : XOR2 - port map(A => \rwaddr[1]\, B => \DWACT_ADD_CI_0_TMP_2[0]\, - Y => I_10_0); - - \un1_r.rcnt_1_0_1_CO1_i_o3\ : OAI1 - port map(A => N_913_i, B => N_9_0, C => CO1_i_o3_0, Y => - CO1_2); - - \r.rxf[3]\ : DFN1 - port map(D => N_161, CLK => lclk_c, Q => \rxf[3]\); - - un4_scaler_I_8 : OR2 - port map(A => \un1_uart1[3]\, B => \un1_uart1[2]\, Y => - N_45); - - \r.tcnt_RNIACLM3[2]\ : OR2A - port map(A => thempty_1, B => \N_156\, Y => thempty_1_m); - - \r.rshift[0]\ : DFN1 - port map(D => \rshift_RNO_0[0]\, CLK => lclk_c, Q => - \rshift[0]\); - - \r.rhold_0[7]\ : DFN1E0 - port map(D => \rhold_0_1[7]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[7]\); - - \r.twaddr_RNO[1]\ : NOR2B - port map(A => I_10_1, B => rstn, Y => N_33); - - \r.thold_tile_I_1_RNIG8SI4\ : OR3C - port map(A => N_155, B => \thold[5]\, C => \rdata_4_sqmuxa\, - Y => rdata_17_m_4); - - \r.tshift[0]\ : DFN1 - port map(D => \tshift_1[0]\, CLK => lclk_c, Q => - \tshift[0]\); - - \r.debug_RNIVG2S\ : NOR2A - port map(A => debug, B => thempty_1, Y => N_155); - - \r.txstate_RNO_6[0]\ : OR2A - port map(A => \un1_uart1[34]\, B => debug, Y => - \txstate_ns_i_0_1_tz_0[0]\); - - \r.rraddr_RNIV9TI[0]\ : MX2C - port map(A => N_475, B => N_483, S => \rraddr[0]\, Y => - \rdata_2[2]\); - - \r.rhold_1[2]\ : DFN1E0 - port map(D => \rhold_0_1[2]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[2]\); - - \r.rxdb_RNI0F8G[1]\ : NOR3B - port map(A => \un1_uart1[36]\, B => \rxdb[1]\, C => - \rxdb[0]\, Y => rxdb_1); - - \r.rshift_RNINDDD1[7]\ : MX2 - port map(A => pwdata_0(7), B => \rshift[7]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_0_1[7]\); - - \r.tshift_RNO_2[5]\ : OR2A - port map(A => \thold[5]\, B => N_134, Y => N_188); - - \r.rhold_2[7]\ : DFN1E0 - port map(D => \rhold_0_1[7]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[7]\); - - \uartop.v.tcnt_11_0_0_1_CO0_i\ : MAJ3 - port map(A => \tcnt[0]\, B => twaddr_0_sqmuxa, C => N_22, Y - => N_9); - - \r.rraddr_RNIHMRG3[0]\ : OR2B - port map(A => \rdata_2[3]\, B => \rdata_0_sqmuxa\, Y => - \rdata_2_m[3]\); - - \r.rwaddr_RNIDEB1[1]\ : NOR2B - port map(A => \rwaddr[1]\, B => \rwaddr[0]\, Y => - \un26_rxd[0]\); - - \r.brate[0]\ : DFN1E1 - port map(D => pwdata_0_d0, CLK => lclk_c, E => - brate_1_sqmuxa, Q => \brate[0]\); - - \r.thold_tile_I_1_RNI04UK1\ : NOR2B - port map(A => \thold[3]\, B => N_155, Y => - \rdata_17_m_0[2]\); - - \r.rxstate_RNI4TU7[0]\ : OR2B - port map(A => rxtick, B => \rxstate[0]\, Y => - frame_1_sqmuxa_1); - - \r.rshift_RNI9HCD1[0]\ : MX2 - port map(A => pwdata_0(0), B => \rshift[0]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_3_1[0]\); - - \r.tcnt_RNO[2]\ : XA1 - port map(A => CO1_1, B => SUM2_0_0, C => rstn, Y => - \tcnt_RNO[2]\); - - \r.rcnt_RNIHM9E[1]\ : NOR2 - port map(A => \rcnt[2]\, B => \rcnt[1]\, Y => rhalffull_1); - - \r.rxclk[2]\ : DFN1E0 - port map(D => \rxclk_1[2]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[2]\); - - \r.tshift_RNO_2[3]\ : OR2A - port map(A => \thold[3]\, B => N_134, Y => N_182); - - \r.rxstate_RNO[1]\ : NOR3A - port map(A => rstn, B => N_206, C => N_207, Y => N_88); - - \r.rhold_1[3]\ : DFN1E0 - port map(D => \rhold_3_1[3]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[3]\); - - \r.rshift_RNO[2]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_663, Y => - \rshift_RNO_0[2]\); - - \uartop.v.tcnt_11_0_0_1_SUM1_0\ : XOR2 - port map(A => SUM1_0_0_0, B => N_9, Y => \tcnt_11[1]\); - - \r.rsempty_RNICVQJ\ : OR3 - port map(A => \rxstate_i[4]\, B => rsempty, C => \rcnt[2]\, - Y => rwaddr_0_sqmuxa); - - \r.rhold_2[0]\ : DFN1E0 - port map(D => \rhold_3_1[0]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[0]\); - - \r.irq_RNO_8\ : NOR3A - port map(A => rirqen_m_1, B => frame_1_sqmuxa_1, C => - break_0_sqmuxa, Y => rirqen_m_0); - - \un1_r.rraddr_I_10\ : XOR2 - port map(A => \rraddr[1]\, B => \DWACT_ADD_CI_0_TMP_1[0]\, - Y => I_10_2); - - \uartop.v.tcnt_11_0_0_1_CO1_i_o3\ : AO1B - port map(A => N_9, B => \tcnt[1]\, C => CO1_i_o3_0_0, Y => - CO1_1); - - \r.rxen\ : DFN1 - port map(D => N_104, CLK => lclk_c, Q => \un1_uart1[36]\); - - \r.traddr[0]\ : DFN1 - port map(D => N_35, CLK => lclk_c, Q => \traddr[0]\); - - \r.txtick\ : DFN1 - port map(D => N_98, CLK => lclk_c, Q => txtick); - - \r.rirqen_RNII5M63\ : NOR3C - port map(A => debug, B => rirqen, C => irq_5_2, Y => irq_5); - - \un1_r.irqcnt_I_27\ : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \irqcnt[2]\, Y => \DWACT_ADD_CI_0_g_array_12[0]\); - - \r.scaler[10]\ : DFN1E0 - port map(D => \scaler_1[10]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[12]\); - - \r.dpar_RNI4PT94\ : OR2 - port map(A => rwaddr_0_sqmuxa_0, B => irq_5_2, Y => - dpar_RNI4PT94); - - \r.rhold_3[7]\ : DFN1E0 - port map(D => \rhold_0_1[7]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[7]\); - - \r.scaler_RNO[5]\ : MX2A - port map(A => N_507, B => pwdata_0(5), S => - brate_1_sqmuxa_0, Y => \scaler_1[5]\); - - \r.thold_tile_I_1_RNICORI4\ : OR3C - port map(A => N_155, B => \thold[1]\, C => \rdata_4_sqmuxa\, - Y => rdata_17_m_0_d0); - - \r.rxstate_RNO_0[3]\ : NOR2A - port map(A => \rxstate[3]\, B => rxtick, Y => - \rxstate_RNO_0[3]\); - - \r.rxstate_i_RNO_0[4]\ : OAI1 - port map(A => \rxstate_nss_i_0_a3_0[0]\, B => - \rxstate_nss_i_0_0_0_tz_0[0]\, C => rstn, Y => - \rxstate_nss_i_0_0_0[0]\); - - \r.rraddr_RNID6RG3[0]\ : OR2B - port map(A => \rdata_2[2]\, B => \rdata_0_sqmuxa\, Y => - \rdata_2_m[2]\); - - \r.rhold_0[4]\ : DFN1E0 - port map(D => \rhold_0_1[4]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[4]\); - - \r.delayirqen\ : DFN1E1 - port map(D => pwdata_13, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => \delayirqen\); - - \r.tfifoirqen_RNIN2T63\ : NOR2B - port map(A => tfifoirqen, B => \prdata[31]\, Y => - tfifoirqen_m); - - \r.tshift_RNO[5]\ : OR3C - port map(A => N_187, B => N_186, C => N_188, Y => - \tshift_13[5]\); - - \r.thold_tile_WADDR_REG1[0]\ : DFN1 - port map(D => \twaddr[0]\, CLK => lclk_c, Q => - \WADDR_REG1[0]\); - - \r.rirqen_RNIF4B33\ : OR2B - port map(A => rirqen, B => \prdata[31]\, Y => rirqen_m); - - \un1_r.irqcnt_I_30\ : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \irqcnt[4]\, Y => \DWACT_ADD_CI_0_g_array_12_1[0]\); - - \r.ovf_RNO_1\ : NOR3B - port map(A => \rcnt_1\, B => rxdb_1, C => \rxstate_i[4]\, Y - => ovf_0_sqmuxa); - - \r.rshift[3]\ : DFN1 - port map(D => \rshift_RNO_0[3]\, CLK => lclk_c, Q => - \rshift[3]\); - - \r.tshift[3]\ : DFN1 - port map(D => \tshift_13[3]\, CLK => lclk_c, Q => - \tshift[3]\); - - \r.txclk_RNO[0]\ : NOR3C - port map(A => N_199, B => tick, C => rstn, Y => N_69); - - \r.rhold_1_RNIQ959[6]\ : MX2C - port map(A => \rhold_1[6]\, B => \rhold_3[6]\, S => - \rraddr[1]\, Y => N_487); - - \r.twaddr[1]\ : DFN1 - port map(D => N_33, CLK => lclk_c, Q => \twaddr[1]\); - - \r.tshift_RNO_1[1]\ : OR3B - port map(A => txtick, B => \tshift[2]\, C => N_133, Y => - N_174); - - \r.thold_tile_WADDR_REG1_RNI16OE[0]\ : XAI1A - port map(A => \WADDR_REG1[0]\, B => \traddr[0]\, C => I_5_0, - Y => N_7); - - \r.parerr\ : DFN1 - port map(D => N_108, CLK => lclk_c, Q => parerr); - - un4_scaler_I_31 : XNOR2 - port map(A => N_29_0, B => \un1_uart1[8]\, Y => I_31_3); - - \r.tfifoirqen\ : DFN1E1 - port map(D => pwdata_9, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => tfifoirqen); - - \r.irqcnt_RNO[4]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_24_5, Y - => \irqcnt_1[4]\); - - \r.tshift_RNO_0[0]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[0]\, Y => N_219); - - \r.rxen_RNO\ : NOR2B - port map(A => N_647, B => rstn, Y => N_104); - - \r.tshift_RNO_0[6]\ : AOI1B - port map(A => txtick_1_sqmuxa, B => \tshift[6]\, C => N_189, - Y => \tshift_13_0_iv_0_0[6]\); - - \r.rwaddr_RNIULKC4_0[1]\ : AOI1 - port map(A => irq_5_2, B => \un26_rxd[0]\, C => - rhold_3_1_sqmuxa_1, Y => rhold_3_0_sqmuxa); - - \r.txclk_RNO[2]\ : XA1B - port map(A => \txclk[2]\, B => CO1_0, C => N_29_1, Y => - N_29); - - \r.rirqen_RNI67IFE\ : NOR3C - port map(A => \rdata_iv_0[2]\, B => \rdata_2_m[2]\, C => - rirqen_m, Y => rdata_iv_2(2)); - - \r.extclken_RNO_0\ : MX2 - port map(A => extclken, B => pwdata_0(8), S => - breakirqen_1_sqmuxa, Y => N_649); - - \r.txstate_RNO_5[0]\ : NOR2 - port map(A => \tcnt_i\, B => \tcnt[0]\, Y => - \txstate_ns_i_0_a2_2_0[0]\); - - \r.rraddr_RNIBQUI[0]\ : MX2C - port map(A => N_478, B => N_486, S => \rraddr[0]\, Y => - \rdata_2[5]\); - - \uartop.v.traddr_1_i[1]\ : NOR2B - port map(A => I_10, B => rstn, Y => N_37_0); - - \r.rxstate_i_RNO_3[4]\ : AO1A - port map(A => rxtick, B => \rxstate[0]\, C => \rxstate[1]\, - Y => \rxstate_nss_i_0_0_0_tz_0[0]\); - - un4_scaler_I_56 : XNOR2 - port map(A => N_11, B => \un1_uart1[12]\, Y => I_56_1); - - \r.rhold_3_RNO[6]\ : MX2 - port map(A => pwdata_0(6), B => \rshift[6]\, S => - rhold_3_1_sqmuxa_1, Y => \rhold_3_1[6]\); - - \uartop.v.tcnt_11_0_0_1_SUM1_0_0\ : XOR2 - port map(A => \tcnt[1]\, B => N_22, Y => SUM1_0_0_0); - - \r.rhold_1[0]\ : DFN1E0 - port map(D => \rhold_3_1[0]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[0]\); - - un4_scaler_I_51 : OR2 - port map(A => \un1_uart1[10]\, B => \DWACT_FDEC_E[4]\, Y - => N_14); - - \r.scaler_RNO_0[1]\ : MX2C - port map(A => \brate[1]\, B => I_5_4, S => tick_2_i, Y => - N_503); - - \un1_r.rcnt_1_0_1_CO0_i\ : AO1A - port map(A => rraddr_0_sqmuxa, B => N_940_1, C => N_16, Y - => N_9_0); - - un4_scaler_I_34 : OR3 - port map(A => \un1_uart1[5]\, B => \un1_uart1[6]\, C => - \un1_uart1[7]\, Y => \DWACT_FDEC_E[2]\); - - \r.rshift_RNO[7]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_668, Y => - \rshift_RNO_0[7]\); - - \r.dpar_RNIT6LB\ : OR3A - port map(A => rxtick, B => dpar, C => \rcnt[2]\, Y => - rwaddr_0_sqmuxa_1_1); - - \r.thold_tile_I_1_RNI67SO\ : MX2 - port map(A => \DIN_REG1[7]\, B => \DOUT_TMP[7]\, S => N_7, - Y => \thold[8]\); - - \r.tcnt[1]\ : DFN1 - port map(D => \tcnt_RNO_0[1]\, CLK => lclk_c, Q => - \tcnt[1]\); - - \r.tcnt[2]\ : DFN1 - port map(D => \tcnt_RNO[2]\, CLK => lclk_c, Q => \tcnt[2]\); - - \r.rshift_RNIF794[1]\ : NOR3A - port map(A => break6_1, B => \rshift[2]\, C => \rshift[1]\, - Y => break6_4); - - \r.rwaddr_RNO[0]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_1[0]\, B => rstn, - Y => \rwaddr_RNO[0]\); - - \r.rxstate_RNO_0[1]\ : OA1A - port map(A => \paren\, B => N_140, C => rxtick, Y => N_206); - - \r.break_RNO\ : NOR2B - port map(A => N_640, B => rstn, Y => N_114); - - \r.txclk[1]\ : DFN1E1 - port map(D => N_27, CLK => lclk_c, E => N_25, Q => - \txclk[1]\); - - \r.rshift_RNIDPCD1[2]\ : MX2 - port map(A => pwdata_0(2), B => \rshift[2]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_0_1[2]\); - - \r.rxstate_RNO_0[2]\ : NOR2B - port map(A => rxtick, B => N_876, Y => - \rxstate_srsts_0_a3_0_0[2]\); - - \r.rhold_0[3]\ : DFN1E0 - port map(D => \rhold_0_1[3]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[3]\); - - \v.tshift_13_0_iv_0_RNO[7]\ : AND2 - port map(A => N_193, B => N_192, Y => - \tshift_13_0_iv_0_0[7]\); - - \r.twaddr_RNO[0]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_3[0]\, B => rstn, - Y => N_31); - - \r.scaler[11]\ : DFN1E0 - port map(D => \scaler_1[11]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[13]\); - - \r.irqcnt[1]\ : DFN1 - port map(D => \irqcnt_1[1]\, CLK => lclk_c, Q => - \irqcnt[1]\); - - \r.rraddr_RNIN9SI[0]\ : MX2C - port map(A => N_473, B => N_481, S => \rraddr[0]\, Y => - rdata_2_0); - - \r.tshift_RNIPTO2[2]\ : NOR2B - port map(A => \tshift[2]\, B => \tshift[3]\, Y => - \txstate_ns_i_0_a2_4_0[0]\); - - \r.tsempty_RNI49383\ : OR2A - port map(A => tsempty, B => \N_156\, Y => N_227); - - \uartop.rdata60_4_0\ : OR2 - port map(A => rdata61_2, B => rdata60_1, Y => rdata60_4_0); - - \r.rhold_0[1]\ : DFN1E0 - port map(D => \rhold_0_1[1]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[1]\); - - \r.extclken_RNIMU723\ : NAND2 - port map(A => \prdata[31]\, B => extclken, Y => extclken_m); - - un2_rxclk_1_CO1 : AND2 - port map(A => \rxclk[0]\, B => \rxclk[1]\, Y => CO1); - - \r.tshift_RNO[6]\ : AO1C - port map(A => N_134, B => \thold[6]\, C => - \tshift_13_0_iv_0_0[6]\, Y => \tshift_13[6]\); - - \r.debug_RNIJUO41\ : OR2A - port map(A => N_155, B => \rdata62_0\, Y => - traddr_1_sqmuxa_0); - - \r.rxdb_RNO[0]\ : NOR3C - port map(A => N_172, B => N_171, C => N_170, Y => N_17_i_0); - - \r.parerr_RNO\ : NOR2B - port map(A => N_644, B => rstn, Y => N_108); - - \r.rhold_3_RNO[4]\ : MX2 - port map(A => pwdata_1_3, B => \rshift[4]\, S => - rhold_3_1_sqmuxa_1, Y => \rhold_3_1[4]\); - - \r.rshift_RNO[4]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_665, Y => - \rshift_RNO_0[4]\); - - un4_scaler_I_59 : OR3 - port map(A => \un1_uart1[8]\, B => \un1_uart1[9]\, C => - \un1_uart1[10]\, Y => \DWACT_FDEC_E[5]\); - - \r.ovf_RNO\ : OA1 - port map(A => N_645, B => ovf_0_sqmuxa, C => rstn, Y => - ovf_RNO_0); - - \uartop.un1_apbi_2_0\ : NOR2A - port map(A => penable, B => N_750, Y => un1_apbi_2_0); - - \r.rraddr_RNI3QTI[0]\ : MX2C - port map(A => N_476, B => N_484, S => \rraddr[0]\, Y => - \rdata_2[3]\); - - \r.txstate[0]\ : DFN1 - port map(D => N_801s, CLK => lclk_c, Q => \txstate[0]\); - - \r.tshift_RNO_0[3]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[3]\, Y => N_181); - - \r.brate_RNI6GS63[11]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[11]\, Y => - brate_m_9); - - \r.rcnt_RNIOHEL[1]\ : NOR3 - port map(A => \rcnt[1]\, B => \rcnt[0]\, C => \rcnt[2]\, Y - => rcnt); - - \r.ovf\ : DFN1 - port map(D => ovf_RNO_0, CLK => lclk_c, Q => ovf); - - \r.rshift[6]\ : DFN1 - port map(D => \rshift_RNO_0[6]\, CLK => lclk_c, Q => - \rshift[6]\); - - \r.rirqen_RNIRGQ9\ : NOR2A - port map(A => rirqen, B => \delayirqen\, Y => rirqen_m_1); - - \r.thold_tile_DIN_REG1[6]\ : DFN1 - port map(D => pwdata_6, CLK => lclk_c, Q => \DIN_REG1[6]\); - - \r.rhold_1_RNIO159[5]\ : MX2C - port map(A => \rhold_1[5]\, B => \rhold_3[5]\, S => - \rraddr[1]\, Y => N_486); - - \r.tshift[6]\ : DFN1 - port map(D => \tshift_13[6]\, CLK => lclk_c, Q => - \tshift[6]\); - - \r.frame\ : DFN1 - port map(D => N_112, CLK => lclk_c, Q => \frame\); - - \un1_r.rwaddr_I_1\ : AND2 - port map(A => \rwaddr[0]\, B => dpar_RNI4PT94, Y => - \DWACT_ADD_CI_0_TMP_2[0]\); - - \r.thold_tile_WADDR_REG1[1]\ : DFN1 - port map(D => \twaddr[1]\, CLK => lclk_c, Q => - \WADDR_REG1[1]\); - - \r.scaler_RNO_0[5]\ : MX2C - port map(A => \brate[5]\, B => I_24_4, S => tick_2_i, Y => - N_507); - - \r.irq_RNO_4\ : XA1C - port map(A => CO1_1, B => SUM2_0_0, C => un6_thempty_1, Y - => un6_thempty); - - \r.rwaddr_RNIH79B4[1]\ : OAI1 - port map(A => irq_5_2, B => rwaddr_0_sqmuxa_0, C => - rhold_1_0_sqmuxa_0, Y => rhold_1_0_sqmuxa); - - un4_scaler_I_20 : XNOR2 - port map(A => N_37, B => \un1_uart1[6]\, Y => I_20_4); - - \r.tshift_RNO[8]\ : OR3C - port map(A => N_196, B => N_195, C => N_197, Y => - \tshift_13[8]\); - - \r.rshift[1]\ : DFN1 - port map(D => \rshift_RNO_0[1]\, CLK => lclk_c, Q => - \rshift[1]\); - - \r.rxstate_RNIG2GC[3]\ : NOR2A - port map(A => \rxstate[3]\, B => \rxdb[0]\, Y => N_876); - - \r.tshift_RNO_1[0]\ : AOI1B - port map(A => \tshift_1_0_a2_0[0]\, B => N_260, C => N_218, - Y => \tshift_1_0_0[0]\); - - \r.tshift[1]\ : DFN1 - port map(D => \tshift_13[1]\, CLK => lclk_c, Q => - \tshift[1]\); - - \r.rshift[2]\ : DFN1 - port map(D => \rshift_RNO_0[2]\, CLK => lclk_c, Q => - \rshift[2]\); - - \r.tshift[2]\ : DFN1 - port map(D => \tshift_13[2]\, CLK => lclk_c, Q => - \tshift[2]\); - - \r.rshift_RNO_0[0]\ : MX2 - port map(A => \rshift[1]\, B => \rshift[0]\, S => N_860, Y - => N_661); - - \r.txtick_RNO_0\ : NOR3C - port map(A => tick, B => \txclk[2]\, C => CO1_0, Y => - txtick_0_i_1); - - \r.rshift_RNO_0[6]\ : MX2 - port map(A => \rshift[7]\, B => \rshift[6]\, S => N_860, Y - => N_667); - - \r.txstate_RNO_7[0]\ : NOR3B - port map(A => \paren\, B => \txstate[0]\, C => \tshift[1]\, - Y => \txstate_ns_i_0_a2_3_1[0]\); - - \un1_r.twaddr_I_8\ : XOR2 - port map(A => \twaddr[0]\, B => twaddr_0_sqmuxa, Y => - \DWACT_ADD_CI_0_partial_sum_3[0]\); - - \r.rraddr[1]\ : DFN1 - port map(D => \rraddr_RNO[1]\, CLK => lclk_c, Q => - \rraddr[1]\); - - \r.rshift_RNIJ5DD1[5]\ : MX2 - port map(A => pwdata_0(5), B => \rshift[5]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_3_1[5]\); - - \r.rxstate_i_RNO_1[4]\ : OR2B - port map(A => rxdb_1, B => N_897_1, Y => N_897); - - \r.rxf[2]\ : DFN1E1 - port map(D => \rxf[1]\, CLK => lclk_c, E => tick, Q => - \rxf[2]\); - - \r.brate_RNITVF83[3]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[3]\, Y => - \brate_m[3]\); - - \r.rfifoirqen_RNI4MA7\ : OR2B - port map(A => rfifoirqen, B => \un1_uart1[36]\, Y => - un4_rhalffull_0); - - \r.rhold_0_RNIK949[6]\ : MX2C - port map(A => \rhold_0[6]\, B => \rhold_2[6]\, S => - \rraddr[1]\, Y => N_479); - - \r.irqpend_RNO_2\ : NOR3A - port map(A => irqpend_0_sqmuxa, B => un4_rhalffull, C => - irq10, Y => irqpend_1_sqmuxa); - - \r.scaler_RNO[9]\ : MX2A - port map(A => N_511, B => pwdata_0(9), S => - brate_1_sqmuxa_0, Y => \scaler_1[9]\); - - \r.rxstate_RNO[2]\ : AO1B - port map(A => \rxstate_srsts_0_a3_0_0[2]\, B => rstn, C => - N_893, Y => \rxstate_nss[2]\); - - \un1_r.rraddr_I_1\ : AND2 - port map(A => \rraddr[0]\, B => rraddr_0_sqmuxa, Y => - \DWACT_ADD_CI_0_TMP_1[0]\); - - \r.irqcnt[2]\ : DFN1 - port map(D => \irqcnt_1[2]\, CLK => lclk_c, Q => - \irqcnt[2]\); - - \r.brate_RNIV7G83[5]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[5]\, Y => - brate_m_3); - - \r.rcnt_RNO[2]\ : XA1 - port map(A => CO1_2, B => SUM2_0_1, C => rstn, Y => - \rcnt_RNO[2]\); - - rdata_2_sqmuxa : NOR2A - port map(A => rdata60, B => un1_apbi_5, Y => \prdata[31]\); - - \r.tshift_RNO_2[2]\ : OR2A - port map(A => \thold[2]\, B => N_134, Y => N_179); - - \r.rxf[0]\ : DFN1 - port map(D => rxd1_c, CLK => lclk_c, Q => \rxf[0]\); - - \r.rraddr_RNIJQVI[0]\ : MX2C - port map(A => N_480, B => N_488, S => \rraddr[0]\, Y => - \rdata_2[7]\); - - \v.tshift_13_0_iv_0_RNO_1[7]\ : OR3B - port map(A => txtick, B => \tshift[8]\, C => N_133, Y => - N_192); - - \r.rxstate_RNIKLUE[0]\ : NOR3C - port map(A => \rxdb[0]\, B => rxtick, C => \rxstate[0]\, Y - => parerr_0_sqmuxa); - - \r.dpar_RNO_4\ : XOR2 - port map(A => \rxdb[0]\, B => dpar, Y => dpar_4); - - \r.txstate_RNO_1[0]\ : NOR3 - port map(A => N_210, B => \txstate_ns_i_0_1[0]\, C => - \txstate_ns_i_0_0[0]\, Y => N_929); - - \r.tick_RNIJKMM2\ : OR2 - port map(A => tick, B => N_29_1, Y => N_25); - - \r.txen_RNI386B\ : NOR3B - port map(A => \un1_uart1[34]\, B => txtick, C => debug, Y - => txtick_1); - - \r.rsempty_RNI7T7E\ : NOR2A - port map(A => \rcnt[2]\, B => rsempty, Y => \rcnt_1\); - - \r.rhold_1_RNII949[2]\ : MX2C - port map(A => \rhold_1[2]\, B => \rhold_3[2]\, S => - \rraddr[1]\, Y => N_483); - - \r.thold_tile_I_1_RNI5OUK1\ : NOR2B - port map(A => \thold[8]\, B => N_155, Y => - rdata_iv_0_a2_3_0(7)); - - \r.tshift_RNO[2]\ : OR3C - port map(A => N_178, B => N_177, C => N_179, Y => - \tshift_13[2]\); - - \r.rhold_0[5]\ : DFN1E0 - port map(D => \rhold_3_1[5]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[5]\); - - \r.rshift[4]\ : DFN1 - port map(D => \rshift_RNO_0[4]\, CLK => lclk_c, Q => - \rshift[4]\); - - \r.rraddr_RNIL6SG3[0]\ : OR2B - port map(A => \rdata_2[4]\, B => \rdata_0_sqmuxa\, Y => - rdata_2_m_2); - - \r.tshift[4]\ : DFN1 - port map(D => \tshift_13[4]\, CLK => lclk_c, Q => - \tshift[4]\); - - \v.breakirqen_1_sqmuxa\ : NOR3C - port map(A => pwrite, B => un1_apbi_2, C => rdata60, Y => - breakirqen_1_sqmuxa); - - \r.tirqen_RNIU7MFE\ : AOI1B - port map(A => tirqen, B => \prdata[31]\, C => - \rdata_iv_1[3]\, Y => rdata_iv_2(3)); - - \r.rxstate_RNO_2[0]\ : NOR2 - port map(A => \paren\, B => N_140, Y => N_142); - - \r.paren\ : DFN1E1 - port map(D => pwdata_5, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => \paren\); - - \r.irq_RNO\ : OR3C - port map(A => tsemptyirqen, B => irq_1_0, C => irq_16_i, Y - => irq_1); - - \r.tshift[9]\ : DFN1 - port map(D => \tshift_13_0_iv[9]\, CLK => lclk_c, Q => - \tshift[9]\); - - \r.thold_tile_DIN_REG1[0]\ : DFN1 - port map(D => pwdata_0_d0, CLK => lclk_c, Q => - \DIN_REG1[0]\); - - \r.scaler_RNO[11]\ : MX2A - port map(A => N_513, B => pwdata_0(11), S => - brate_1_sqmuxa_0, Y => \scaler_1[11]\); - - \r.irq\ : DFN1 - port map(D => irq_1, CLK => lclk_c, Q => pirq(2)); - - \r.irq_RNO_3\ : NOR2B - port map(A => tfifoirqen, B => \un1_uart1[34]\, Y => - un4_thalffull_0); - - \v.brate_1_sqmuxa\ : NOR3C - port map(A => pwrite, B => un1_apbi_2, C => rdata61, Y => - brate_1_sqmuxa); - - \r.irq_RNO_13\ : OA1 - port map(A => delayirqen_0, B => irq_5, C => irq_6_m_0, Y - => irq_6_m); - - \r.tshift_RNO_2[0]\ : OA1A - port map(A => \paren\, B => tpar, C => N_247, Y => - \tshift_1_0_a2_0[0]\); - - \r.tshift_RNO_1[4]\ : OR3B - port map(A => txtick, B => \tshift[5]\, C => N_133, Y => - N_183); - - \r.rraddr_RNI1NTG3[0]\ : OR2B - port map(A => \rdata_2[7]\, B => \rdata_0_sqmuxa\, Y => - N_223); - - \r.rxstate_RNO_0[0]\ : NOR3A - port map(A => rxtick, B => \rxstate[1]\, C => N_142, Y => - N_204); - - \r.txstate_RNO_2[0]\ : NOR3C - port map(A => N_133, B => flow, C => N_210_1, Y => N_210); - - \r.rcnt_RNI8FBM3[1]\ : OR2 - port map(A => rcnt, B => \N_156\, Y => rcnt_RNI8FBM3(1)); - - \r.thold_tile_I_1_RNI2NRO\ : MX2 - port map(A => \DIN_REG1[3]\, B => \DOUT_TMP[3]\, S => N_7, - Y => \thold[4]\); - - \r.scaler[1]\ : DFN1E0 - port map(D => \scaler_1[1]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[3]\); - - \r.rshift_RNISJ42[5]\ : NOR2 - port map(A => \rshift[5]\, B => \rshift[7]\, Y => break6_1); - - \r.irq_RNO_7\ : OA1B - port map(A => rxtick_0, B => frame_1_sqmuxa_1, C => irq_7, - Y => irq_7_m); - - \r.rxstate_i_RNI5HRL[4]\ : OR2A - port map(A => rxdb_1, B => \rxstate_i[4]\, Y => - rshift_0_sqmuxa_1); - - \r.dpar_RNO_2\ : OR3 - port map(A => \rxstate[1]\, B => \rshift[0]\, C => \paren\, - Y => N_898); - - \r.rshift_RNO_0[3]\ : MX2 - port map(A => \rshift[4]\, B => \rshift[3]\, S => N_860, Y - => N_664); - - \r.rxen_RNI4SI4\ : NOR2 - port map(A => \un1_uart1[36]\, B => \un1_uart1[34]\, Y => - txen); - - \r.tirqen\ : DFN1E1 - port map(D => pwdata_1_2, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => tirqen); - - \r.rxtick_RNO_1\ : AND2 - port map(A => tick, B => \rxclk[2]\, Y => rxtick_0_0); - - \r.rxclk[0]\ : DFN1E0 - port map(D => \rxclk_1[0]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[0]\); - - \r.txstate_RNO_4[0]\ : AO1 - port map(A => \txstate_ns_i_0_a2_3_1[0]\, B => N_260, C => - N_209, Y => \txstate_ns_i_0_0[0]\); - - \r.rraddr_RNIPMSG3[0]\ : OR2B - port map(A => \rdata_2[5]\, B => \rdata_0_sqmuxa\, Y => - rdata_2_m_3); - - \r.rxdb_RNO_1[0]\ : OR2A - port map(A => loopb, B => \tshift[0]\, Y => N_171); - - \r.brate_RNIRNF83[1]\ : OR2B - port map(A => rdata_3_sqmuxa_net_1, B => \brate[1]\, Y => - N_225); - - \r.irq_RNO_6\ : OR3 - port map(A => \tcnt_11[0]\, B => thempty_1, C => - \tcnt_11[1]\, Y => un6_thempty_1); - - \un1_r.irqcnt_I_1\ : AND2 - port map(A => \irqcnt[0]\, B => rxtick_0, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - \r.rhold_1_RNISH59[7]\ : MX2C - port map(A => \rhold_1[7]\, B => \rhold_3[7]\, S => - \rraddr[1]\, Y => N_488); - - \r.txstate_RNO[1]\ : NOR2B - port map(A => N_802, B => rstn, Y => N_802s); - - \r.tshift_RNO_1[8]\ : OR3B - port map(A => txtick, B => \tshift[9]\, C => N_133, Y => - N_195); - - \r.extclken_RNO\ : NOR2B - port map(A => N_649, B => rstn, Y => N_100); - - \r.rsempty\ : DFN1 - port map(D => N_216, CLK => lclk_c, Q => rsempty); - - \un1_r.irqcnt_I_15\ : XOR2 - port map(A => \irqcnt[0]\, B => rxtick_0, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \r.tshift_RNO_0[2]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[2]\, Y => N_178); - - \uartop.v.thold_32\ : OR2 - port map(A => N_232, B => paddr(4), Y => thold_32); - - \r.irqpend\ : DFN1 - port map(D => N_110, CLK => lclk_c, Q => irqpend); - - \r.rwaddr_RNIULKC4[1]\ : AOI1 - port map(A => irq_5_2, B => \un26_rxd[3]\, C => - rhold_0_1_sqmuxa_1, Y => rhold_0_0_sqmuxa); - - un4_scaler_I_13 : XNOR2 - port map(A => N_42, B => \un1_uart1[5]\, Y => I_13_8); - - \r.brate[1]\ : DFN1E1 - port map(D => pwdata_1_0, CLK => lclk_c, E => - brate_1_sqmuxa, Q => \brate[1]\); - - \un1_r.rraddr_I_8\ : XOR2 - port map(A => \rraddr[0]\, B => rraddr_0_sqmuxa, Y => - \DWACT_ADD_CI_0_partial_sum_0[0]\); - - \r.rhold_1_RNIKH49[3]\ : MX2C - port map(A => \rhold_1[3]\, B => \rhold_3[3]\, S => - \rraddr[1]\, Y => N_484); - - \un1_r.rcnt_1_0_1_SUM0_0_1\ : XOR3 - port map(A => \rcnt[0]\, B => rwaddr_0_sqmuxa_0, C => - irq_5_2, Y => N_940_1); - - \r.irq_RNO_15\ : NOR2B - port map(A => \delayirqen\, B => irq10, Y => irq_6_m_0); - - \r.irqcnt[3]\ : DFN1 - port map(D => \irqcnt_1[3]\, CLK => lclk_c, Q => - \irqcnt[3]\); - - \r.rshift_RNO[1]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_662, Y => - \rshift_RNO_0[1]\); - - \r.thold_tile_DIN_REG1[4]\ : DFN1 - port map(D => pwdata_1_3, CLK => lclk_c, Q => \DIN_REG1[4]\); - - \r.rhold_2[5]\ : DFN1E0 - port map(D => \rhold_3_1[5]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[5]\); - - \r.flow_RNO\ : NOR2B - port map(A => N_648, B => rstn, Y => N_102); - - \r.tshift_RNO_1[2]\ : OR3B - port map(A => txtick, B => \tshift[3]\, C => N_133, Y => - N_177); - - un4_scaler_I_16 : OR3 - port map(A => \un1_uart1[2]\, B => \un1_uart1[3]\, C => - \un1_uart1[4]\, Y => \DWACT_FDEC_E[0]\); - - un4_scaler_I_66 : XNOR2 - port map(A => N_4, B => \un1_uart1[13]\, Y => I_66_1); - - \r.tick_RNIG2HP\ : NOR2 - port map(A => tick, B => N_869, Y => rxclk_1_sqmuxa_1); - - \r.rshift_RNO[0]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_661, Y => - \rshift_RNO_0[0]\); - - \r.rhold_0_RNIA139[1]\ : MX2C - port map(A => \rhold_0[1]\, B => \rhold_2[1]\, S => - \rraddr[1]\, Y => N_163); - - \r.txstate[1]\ : DFN1 - port map(D => N_802s, CLK => lclk_c, Q => \txstate[1]\); - - \r.rxdb_RNIC7IF[0]\ : NOR2A - port map(A => break6, B => \rxdb[0]\, Y => break_0_sqmuxa); - - \r.rsempty_RNO_5\ : NOR2B - port map(A => \rxstate[0]\, B => dpar, Y => dpar_m_1); - - \r.irqcnt_RNO[5]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_26, Y => - \irqcnt_1[5]\); - - \r.rshift_RNID794[3]\ : NOR3A - port map(A => break6_3, B => \rshift[3]\, C => \rshift[0]\, - Y => break6_5); - - \r.frame_RNO\ : NOR2B - port map(A => N_641, B => rstn, Y => N_112); - - \r.scaler_RNO[7]\ : MX2A - port map(A => N_509, B => pwdata_0(7), S => - brate_1_sqmuxa_0, Y => \scaler_1[7]\); - - \r.rraddr_RNI7AUI[0]\ : MX2C - port map(A => N_477, B => N_485, S => \rraddr[0]\, Y => - \rdata_2[4]\); - - \r.traddr[1]\ : DFN1 - port map(D => N_37_0, CLK => lclk_c, Q => \traddr[1]\); - - \r.scaler_RNO[2]\ : MX2A - port map(A => N_504, B => pwdata_0(2), S => - brate_1_sqmuxa_0, Y => \scaler_1[2]\); - - \r.irq_RNO_2\ : AOI1B - port map(A => un6_thempty, B => tirqen, C => irq_14, Y => - irq_16_i); - - \r.thold_tile_WADDR_REG1_RNI0OG9[1]\ : XA1A - port map(A => \WADDR_REG1[1]\, B => \traddr[1]\, C => N_5, - Y => I_5_0); - - \r.irq_RNO_14\ : OR2 - port map(A => \breakirqen\, B => rirqen_m_1, Y => irq_10_0); - - \r.txstate_RNI2VCK2[1]\ : OR2B - port map(A => N_134, B => rstn, Y => N_29_1); - - \r.dpar_RNO\ : AO1B - port map(A => dpar_4_m_0, B => N_898, C => parsel_m, Y => - dpar_1); - - \r.scaler_RNO_0[2]\ : MX2C - port map(A => \brate[2]\, B => I_9_4, S => tick_2_i, Y => - N_504); - - \r.rwaddr[0]\ : DFN1 - port map(D => \rwaddr_RNO[0]\, CLK => lclk_c, Q => - \rwaddr[0]\); - - \r.scaler[4]\ : DFN1E0 - port map(D => \scaler_1[4]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[6]\); - - \r.flow_RNO_0\ : MX2 - port map(A => flow, B => pwdata_0(6), S => - breakirqen_1_sqmuxa, Y => N_648); - - un4_scaler_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \un1_uart1[10]\, C - => \un1_uart1[11]\, Y => N_11); - - \r.rhold_3[3]\ : DFN1E0 - port map(D => \rhold_3_1[3]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[3]\); - - \r.tshift_RNO[4]\ : OR3C - port map(A => N_184, B => N_183, C => N_185, Y => - \tshift_13[4]\); - - \r.tick\ : DFN1 - port map(D => tick_1, CLK => lclk_c, Q => tick); - - \r.break_RNI9B673\ : OR2A - port map(A => break, B => \N_156\, Y => break_m); - - \r.irq_RNO_0\ : OR3A - port map(A => \tsemptyirqen_0\, B => tsempty, C => - tsempty_4, Y => tsemptyirqen); - - \un1_r.irqcnt_I_24\ : XOR2 - port map(A => \irqcnt[4]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_24_5); - - \r.txen_RNO\ : NOR2B - port map(A => N_646, B => rstn, Y => N_106); - - \r.rhold_1[7]\ : DFN1E0 - port map(D => \rhold_0_1[7]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[7]\); - - \r.break_RNO_0\ : MX2 - port map(A => break_1, B => break, S => break_0_sqmuxa_1, Y - => N_640); - - \r.irqcnt_RNO[2]\ : NOR3C - port map(A => rstn, B => irqpend_0_sqmuxa, C => I_22, Y => - \irqcnt_1[2]\); - - \r.tshift_RNO_0[5]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[5]\, Y => N_187); - - \r.brate[3]\ : DFN1E1 - port map(D => pwdata_1_2, CLK => lclk_c, E => - brate_1_sqmuxa, Q => \brate[3]\); - - un4_scaler_I_9 : XNOR2 - port map(A => N_45, B => \un1_uart1[4]\, Y => I_9_4); - - \r.thold_tile_I_3\ : DFN1 - port map(D => \un1_apbi_1\, CLK => lclk_c, Q => N_5); - - \r.rhold_3[6]\ : DFN1E0 - port map(D => \rhold_3_1[6]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[6]\); - - \r.debug_RNILV673\ : OR2B - port map(A => debug, B => \prdata[31]\, Y => debug_m); - - \r.thold_tile_I_1_RNIVARO\ : MX2 - port map(A => \DIN_REG1[0]\, B => \DOUT_TMP[0]\, S => N_7, - Y => \thold[1]\); - - \r.rcnt_RNIPO183[2]\ : OR2A - port map(A => \rcnt[2]\, B => \N_156\, Y => prdata_6); - - un4_scaler_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - \r.tsempty\ : DFN1 - port map(D => tsempty_RNO_0, CLK => lclk_c, Q => tsempty); - - \r.tpar\ : DFN1E1 - port map(D => tpar_1, CLK => lclk_c, E => txtick_0_sqmuxa_1, - Q => tpar); - - \r.rraddr_RNI0QMAB[0]\ : AOI1B - port map(A => \rdata_0_sqmuxa\, B => N_165, C => - \rdata_iv_0_0[1]\, Y => \rdata_iv_0_1[1]\); - - \r.rsempty_RNO_3\ : OA1B - port map(A => \rxstate_i[4]\, B => \rcnt_1\, C => dpar_m_1, - Y => N_442); - - \r.rxdb[0]\ : DFN1 - port map(D => N_17_i_0, CLK => lclk_c, Q => \rxdb[0]\); - - un4_scaler_I_19 : OR2 - port map(A => \un1_uart1[5]\, B => \DWACT_FDEC_E[0]\, Y => - N_37); - - \r.irq_RNO_5\ : NOR3 - port map(A => irq_7_m, B => rirqen_m_0, C => irq_10_m, Y - => irq_14); - - \r.parsel\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => parsel); - - \v.break_1_sqmuxa\ : NOR3B - port map(A => pwrite, B => un1_apbi_2, C => rdata59, Y => - break_1_sqmuxa); - - \r.irqcnt[5]\ : DFN1 - port map(D => \irqcnt_1[5]\, CLK => lclk_c, Q => - \irqcnt[5]\); - - \r.delayirqen_RNI39R9\ : NOR2B - port map(A => rxtick, B => \delayirqen\, Y => rxtick_0); - - \un1_r.irqcnt_I_34\ : AND2 - port map(A => \irqcnt[2]\, B => \irqcnt[3]\, Y => - \DWACT_ADD_CI_0_pog_array_1[0]\); - - \r.thold_tile_I_1_RNO\ : INV - port map(A => \un1_apbi_1\, Y => un1_apbi_1_i); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.rxclk_RNO[2]\ : AOI1B - port map(A => N_973_i, B => rshift_0_sqmuxa_1, C => rstn, Y - => \rxclk_1[2]\); - - \r.rhold_2[1]\ : DFN1E0 - port map(D => \rhold_0_1[1]\, CLK => lclk_c, E => - rhold_2_0_sqmuxa, Q => \rhold_2[1]\); - - \r.rcnt[0]\ : DFN1 - port map(D => \rcnt_RNO[0]\, CLK => lclk_c, Q => \rcnt[0]\); - - \r.rcnt_RNI5J9Q1[1]\ : NOR3C - port map(A => \rcnt[0]\, B => rwaddr_0_sqmuxa_0, C => - \rcnt[1]\, Y => N_914); - - \r.rshift_RNO_0[2]\ : MX2 - port map(A => \rshift[3]\, B => \rshift[2]\, S => N_860, Y - => N_663); - - \r.rwaddr_RNIH79B4_0[1]\ : OAI1 - port map(A => irq_5_2, B => rwaddr_0_sqmuxa_0, C => - rhold_2_0_sqmuxa_0, Y => rhold_2_0_sqmuxa); - - \v.twaddr_0_sqmuxa\ : NOR2 - port map(A => un1_apbi_6, B => twaddr_0_sqmuxa_0, Y => - twaddr_0_sqmuxa); - - \r.rxstate[0]\ : DFN1 - port map(D => N_86, CLK => lclk_c, Q => \rxstate[0]\); - - \r.rsempty_RNIAD131\ : NOR3A - port map(A => loopb, B => rsempty, C => rcnt, Y => N_210_1); - - \un1_r.twaddr_I_1\ : AND2 - port map(A => \twaddr[0]\, B => twaddr_0_sqmuxa, Y => - \DWACT_ADD_CI_0_TMP_0[0]\); - - \r.rxtick\ : DFN1 - port map(D => rxtick_RNO, CLK => lclk_c, Q => rxtick); - - \r.rwaddr_RNIDEB1_0[1]\ : NOR2A - port map(A => \rwaddr[1]\, B => \rwaddr[0]\, Y => - rhold_2_0_sqmuxa_0); - - \r.irq_RNO_11\ : OR2 - port map(A => irq_10_1, B => irq_6_m, Y => irq_10_i); - - \r.rraddr_RNO[0]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_0[0]\, B => rstn, - Y => \rraddr_RNO[0]\); - - rdata_4_sqmuxa_0_a2 : NOR2A - port map(A => paddr(4), B => N_235, Y => \rdata_4_sqmuxa\); - - un4_scaler_I_27 : OR2 - port map(A => \un1_uart1[5]\, B => \un1_uart1[6]\, Y => - \DWACT_FDEC_E[1]\); - - \r.thold_tile_I_1_RNI1JRO\ : MX2 - port map(A => \DIN_REG1[2]\, B => \DOUT_TMP[2]\, S => N_7, - Y => \thold[3]\); - - \r.parerr_RNIQF933\ : OR2A - port map(A => parerr, B => \N_156\, Y => parerr_m); - - \r.rhold_1[4]\ : DFN1E0 - port map(D => \rhold_1_1[4]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[4]\); - - \r.rhold_3[5]\ : DFN1E0 - port map(D => \rhold_3_1[5]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[5]\); - - \r.dpar_RNIMSVB1\ : OAI1 - port map(A => rwaddr_0_sqmuxa_1_0, B => rwaddr_0_sqmuxa_1_1, - C => rwaddr_0_sqmuxa, Y => rwaddr_0_sqmuxa_0); - - \r.thold_tile_I_1_RNIF4SI4\ : OR3C - port map(A => N_155, B => \thold[4]\, C => \rdata_4_sqmuxa\, - Y => \rdata_17_m[3]\); - - \r.rhold_1_RNIEP39[0]\ : MX2C - port map(A => \rhold_1[0]\, B => \rhold_3[0]\, S => - \rraddr[1]\, Y => N_481); - - \r.txtick_RNIO1FF\ : OR2B - port map(A => txtick, B => N_133, Y => txstate_1); - - \r.dpar_RNO_1\ : NOR2B - port map(A => N_906, B => dpar_4, Y => dpar_4_m_0); - - \r.tshift_RNO_0[8]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[8]\, Y => N_196); - - \r.scaler[3]\ : DFN1E0 - port map(D => \scaler_1[3]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[5]\); - - \un1_r.irqcnt_I_21\ : XOR2 - port map(A => \irqcnt[1]\, B => \DWACT_ADD_CI_0_TMP[0]\, Y - => I_21); - - \uartop.v.traddr_1_i[0]\ : NOR2B - port map(A => \DWACT_ADD_CI_0_partial_sum_2[0]\, B => rstn, - Y => N_35); - - \r.dpar_RNO_0\ : OAI1 - port map(A => N_876, B => N_906, C => rxtick, Y => N_875); - - \r.thold_tile_DIN_REG1[2]\ : DFN1 - port map(D => pwdata_2, CLK => lclk_c, Q => \DIN_REG1[2]\); - - \r.rhold_0_RNIC939[2]\ : MX2C - port map(A => \rhold_0[2]\, B => \rhold_2[2]\, S => - \rraddr[1]\, Y => N_475); - - \r.txd\ : DFN1 - port map(D => N_167, CLK => lclk_c, Q => txd1_c); - - \r.brate[7]\ : DFN1E1 - port map(D => pwdata_7, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[7]\); - - \un1_r.traddr_I_1\ : AND2 - port map(A => \traddr[0]\, B => \txstate_RNIURTC6[1]\, Y - => \DWACT_ADD_CI_0_TMP_3[0]\); - - \r.dpar\ : DFN1E0 - port map(D => dpar_1, CLK => lclk_c, E => N_875, Q => dpar); - - \r.irq_RNO_10\ : AOI1 - port map(A => irq10, B => delayirqen_0, C => irq_5, Y => - irq_7); - - \r.rwaddr_RNIDEB1_1[1]\ : NOR2A - port map(A => \rwaddr[0]\, B => \rwaddr[1]\, Y => - rhold_1_0_sqmuxa_0); - - \r.rhold_1_RNIG149[1]\ : MX2C - port map(A => \rhold_1[1]\, B => \rhold_3[1]\, S => - \rraddr[1]\, Y => N_164); - - \r.scaler[5]\ : DFN1E0 - port map(D => \scaler_1[5]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[7]\); - - \r.thold_tile_DIN_REG1[5]\ : DFN1 - port map(D => pwdata_5, CLK => lclk_c, Q => \DIN_REG1[5]\); - - \uartop.v.tcnt_11_0_0_1_SUM0_0\ : XOR3 - port map(A => \tcnt[0]\, B => twaddr_0_sqmuxa, C => N_22, Y - => \tcnt_11[0]\); - - \v.brate_1_sqmuxa_0\ : NOR3C - port map(A => pwrite, B => un1_apbi_2, C => rdata61, Y => - brate_1_sqmuxa_0); - - \un1_r.twaddr_I_10\ : XOR2 - port map(A => \twaddr[1]\, B => \DWACT_ADD_CI_0_TMP_0[0]\, - Y => I_10_1); - - un4_scaler_I_52 : XNOR2 - port map(A => N_14, B => \un1_uart1[11]\, Y => I_52_1); - - \r.brate[5]\ : DFN1E1 - port map(D => pwdata_5, CLK => lclk_c, E => brate_1_sqmuxa, - Q => \brate[5]\); - - \un1_r.irqcnt_I_31\ : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => \irqcnt[1]\, Y - => \DWACT_ADD_CI_0_g_array_1[0]\); - - \r.rxclk[1]\ : DFN1E0 - port map(D => \rxclk_1[1]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[1]\); - - \r.tshift_RNO_2[8]\ : OR2A - port map(A => \thold[8]\, B => N_134, Y => N_197); - - \r.rsempty_RNO_4\ : AO1C - port map(A => rsempty_1_sqmuxa, B => \rxstate[0]\, C => - rshift_0_sqmuxa_1, Y => N_441); - - \r.parerr_RNO_2\ : NOR2 - port map(A => break_1_sqmuxa, B => parerr_0_sqmuxa, Y => - parerr_0_sqmuxa_1); - - \r.break\ : DFN1 - port map(D => N_114, CLK => lclk_c, Q => break); - - \r.twaddr[0]\ : DFN1 - port map(D => N_31, CLK => lclk_c, Q => \twaddr[0]\); - - \r.rshift_RNO_0[5]\ : MX2 - port map(A => \rshift[6]\, B => \rshift[5]\, S => N_860, Y - => N_666); - - \r.irq_RNO_12\ : AO1 - port map(A => irq_5, B => \delayirqen\, C => irq_10_0, Y - => irq_10_1); - - \r.rcnt_RNI5J9Q1_0[1]\ : AX1E - port map(A => \rcnt[0]\, B => rwaddr_0_sqmuxa_0, C => - \rcnt[1]\, Y => N_913_i); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.tpar_RNO\ : MX2B - port map(A => parsel, B => tpar_3_i, S => \txstate[0]\, Y - => tpar_1); - - \r.txstate_RNO_8[0]\ : NOR2B - port map(A => \txstate[1]\, B => \txstate[0]\, Y => N_209); - - \r.breakirqen\ : DFN1E1 - port map(D => pwdata_12, CLK => lclk_c, E => - breakirqen_1_sqmuxa, Q => \breakirqen\); - - \r.dpar_RNO_3\ : OR2B - port map(A => \rxstate[3]\, B => parsel, Y => parsel_m); - - \uartop.un1_apbi_2\ : NOR3C - port map(A => N_769, B => N_773, C => un1_apbi_2_0, Y => - un1_apbi_2); - - \r.brate_RNITQ7CB[3]\ : NOR3C - port map(A => \rdata_17_m[3]\, B => \brate_m[3]\, C => - \rdata_2_m[3]\, Y => \rdata_iv_1[3]\); - - \r.rshift_RNIE5DD1[1]\ : MX2 - port map(A => pwdata_1_0, B => \rshift[1]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_0_1[1]\); - - \r.rhold_0_RNIMH49[7]\ : MX2C - port map(A => \rhold_0[7]\, B => \rhold_2[7]\, S => - \rraddr[1]\, Y => N_480); - - \r.tshift_RNO_0[1]\ : OR2B - port map(A => txtick_1_sqmuxa, B => \tshift[1]\, Y => N_175); - - \r.rfifoirqen_RNILLU53\ : OR2B - port map(A => rfifoirqen, B => \prdata[31]\, Y => - rfifoirqen_m); - - \r.tcnt_RNIF2583[2]\ : NOR2A - port map(A => \tcnt[2]\, B => \N_156\, Y => prdata_0); - - \r.thold_tile_DIN_REG1[3]\ : DFN1 - port map(D => pwdata_1_2, CLK => lclk_c, Q => \DIN_REG1[3]\); - - un4_scaler_I_41 : OR2 - port map(A => \un1_uart1[8]\, B => \un1_uart1[9]\, Y => - \DWACT_FDEC_E[3]\); - - un2_txclk_1_CO1 : NOR2B - port map(A => \txclk[1]\, B => N_976_i_2, Y => CO1_0); - - \r.tshift_RNO[1]\ : OR3C - port map(A => N_175, B => N_174, C => N_176, Y => - \tshift_13[1]\); - - un4_scaler_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \un1_uart1[7]\, Y => N_29_0); - - \r.rhold_0_RNO[3]\ : MX2 - port map(A => pwdata_1_2, B => \rshift[3]\, S => - rhold_0_1_sqmuxa_1, Y => \rhold_0_1[3]\); - - \r.rhold_1[5]\ : DFN1E0 - port map(D => \rhold_3_1[5]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[5]\); - - \r.flow_RNI99462\ : OR3B - port map(A => txtick_1, B => un2_ctsn_1, C => thempty_1, Y - => txtick_0); - - \un1_r.traddr_I_10\ : XOR2 - port map(A => \traddr[1]\, B => \DWACT_ADD_CI_0_TMP_3[0]\, - Y => I_10); - - \r.rxstate[2]\ : DFN1 - port map(D => \rxstate_nss[2]\, CLK => lclk_c, Q => - \rxstate[2]\); - - \r.frame_RNO_0\ : MX2 - port map(A => frame_1, B => \frame\, S => frame_0_sqmuxa, Y - => N_641); - - \r.rshift_RNO[3]\ : OR2A - port map(A => rshift_0_sqmuxa_1, B => N_664, Y => - \rshift_RNO_0[3]\); - - \r.scaler[8]\ : DFN1E0 - port map(D => \scaler_1[8]\, CLK => lclk_c, E => - scaler_2_sqmuxa, Q => \un1_uart1[10]\); - - \uartop.rdata62_0_a2\ : OR2B - port map(A => un1_apbi_8, B => paddr(4), Y => \rdata62\); - - \r.tshift_RNO[0]\ : OR3C - port map(A => N_219, B => \tshift_1_0_0[0]\, C => rstn, Y - => \tshift_1[0]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.rxstate_RNIDMFC[0]\ : OR2B - port map(A => \rxstate[0]\, B => \rxdb[0]\, Y => - rwaddr_0_sqmuxa_1_0); - - \r.rxdb_RNO_3[0]\ : NOR2B - port map(A => \rxf[3]\, B => \rxf[2]\, Y => N_143); - - \uartop.un1_apbi_5\ : OR2A - port map(A => un1_apbi_2, B => pwrite, Y => un1_apbi_5); - - \r.ovf_RNIN7223\ : OR2A - port map(A => ovf, B => \N_156\, Y => ovf_m); - - \r.scaler_RNO_0[6]\ : MX2C - port map(A => \brate[6]\, B => I_31_3, S => tick_2_i, Y => - N_508); - - \r.scaler_RNO[3]\ : MX2A - port map(A => N_505, B => pwdata_0(3), S => - brate_1_sqmuxa_0, Y => \scaler_1[3]\); - - \r.irqpend_RNO_0\ : MX2 - port map(A => irqpend_1, B => irqpend, S => - irqpend_1_sqmuxa, Y => N_643); - - \r.rhold_1[1]\ : DFN1E0 - port map(D => \rhold_0_1[1]\, CLK => lclk_c, E => - rhold_1_0_sqmuxa, Q => \rhold_1[1]\); - - \r.scaler_RNI6J3I[11]\ : OR2A - port map(A => I_66_1, B => \un1_uart1[13]\, Y => tick_2_i); - - \r.rshift_RNIKHDD1[4]\ : MX2 - port map(A => pwdata_1_3, B => \rshift[4]\, S => - rwaddr_0_sqmuxa_0, Y => \rhold_1_1[4]\); - - \r.rxstate_RNIP1S6[2]\ : OR2B - port map(A => \rxstate[2]\, B => rstn, Y => N_78); - - \r.rhold_3[4]\ : DFN1E0 - port map(D => \rhold_3_1[4]\, CLK => lclk_c, E => - rhold_3_0_sqmuxa, Q => \rhold_3[4]\); - - un4_scaler_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_19); - - \r.rshift[7]\ : DFN1 - port map(D => \rshift_RNO_0[7]\, CLK => lclk_c, Q => - \rshift[7]\); - - \r.tshift_RNO_2[1]\ : OR2A - port map(A => \thold[1]\, B => N_134, Y => N_176); - - \r.tshift_RNO_1[3]\ : OR3B - port map(A => txtick, B => \tshift[4]\, C => N_133, Y => - N_180); - - \un1_r.traddr_I_8\ : XOR2 - port map(A => \traddr[0]\, B => \txstate_RNIURTC6[1]\, Y - => \DWACT_ADD_CI_0_partial_sum_2[0]\); - - \r.scaler_RNO[6]\ : MX2A - port map(A => N_508, B => pwdata_0(6), S => - brate_1_sqmuxa_0, Y => \scaler_1[6]\); - - \r.txstate_RNIVPSC[1]\ : NOR2A - port map(A => \txstate[0]\, B => \txstate[1]\, Y => N_243); - - \r.tshift[7]\ : DFN1 - port map(D => \tshift_13[7]\, CLK => lclk_c, Q => - \tshift[7]\); - - \r.rfifoirqen_RNILCKL\ : NOR2 - port map(A => un4_rhalffull_0, B => rhalffull_1, Y => - un4_rhalffull); - - \r.rsempty_RNO_6\ : OA1 - port map(A => dpar, B => \rcnt[2]\, C => \rxdb[0]\, Y => - rsempty_1_sqmuxa); - - \r.debug_RNISSGO3\ : NOR2 - port map(A => traddr_1_sqmuxa_0, B => un1_apbi_5, Y => - traddr_1_sqmuxa); - - \un1_r.irqcnt_I_23\ : XOR2 - port map(A => \irqcnt[3]\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_23); - - \r.rxstate[3]\ : DFN1 - port map(D => \rxstate_nss[1]\, CLK => lclk_c, Q => - \rxstate[3]\); - - \r.rcnt[1]\ : DFN1 - port map(D => \rcnt_RNO[1]\, CLK => lclk_c, Q => \rcnt[1]\); - - \r.rcnt[2]\ : DFN1 - port map(D => \rcnt_RNO[2]\, CLK => lclk_c, Q => \rcnt[2]\); - - \r.rhold_0[2]\ : DFN1E0 - port map(D => \rhold_0_1[2]\, CLK => lclk_c, E => - rhold_0_0_sqmuxa, Q => \rhold_0[2]\); - - \r.tcnt_RNO[0]\ : NOR2B - port map(A => \tcnt_11[0]\, B => rstn, Y => \tcnt_RNO_0[0]\); - - \r.tshift_RNO_3[0]\ : OR3B - port map(A => txtick, B => \tshift[1]\, C => N_133, Y => - N_218); - - \r.scaler_RNO_0[11]\ : OAI1 - port map(A => \un1_uart1[13]\, B => \brate[11]\, C => - I_66_1, Y => N_513); - - \r.scaler_RNO_0[4]\ : MX2C - port map(A => \brate[4]\, B => I_20_4, S => tick_2_i, Y => - N_506); - - \r.irqcnt[0]\ : DFN1 - port map(D => \irqcnt_1[0]\, CLK => lclk_c, Q => - \irqcnt[0]\); - - un4_scaler_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \un1_uart1[5]\, C => - \un1_uart1[6]\, Y => N_34); - - \un1_r.rcnt_1_0_1_SUM1_0_0\ : XOR2 - port map(A => N_913_i, B => rraddr_0_sqmuxa, Y => SUM1_0_0); - - \r.rxtick_RNO_0\ : AND2 - port map(A => rxtick_0_0, B => CO1, Y => rxtick_0_1); - - \un1_r.rcnt_1_0_1_CO0_i_a3_0\ : XA1C - port map(A => \rcnt[0]\, B => rwaddr_0_sqmuxa_0, C => - irq_5_2, Y => N_16); - - \r.tshift_RNITTO2[4]\ : NOR2B - port map(A => \tshift[4]\, B => \tshift[5]\, Y => - \txstate_ns_i_0_a2_4_1[0]\); - - \r.txstate_RNI40IB6[1]\ : OR2A - port map(A => N_134, B => traddr_1_sqmuxa, Y => N_22); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity apbctrl is - - port( hrdata : out std_logic_vector(31 downto 0); - pwdata : out std_logic_vector(31 downto 0); - psel_1 : out std_logic_vector(7 to 7); - prdata_4 : in std_logic_vector(31 to 31); - rdata_iv_0_2 : in std_logic_vector(1 to 1); - prdata_iv_0_0 : in std_logic_vector(2 to 2); - ramrws : in std_logic_vector(1 to 1); - ramwws : in std_logic_vector(1 downto 0); - romrws : in std_logic_vector(3 downto 1); - prdata_iv_0_2 : in std_logic; - prdata_iv_0_0_d0 : in std_logic; - un1_grgpio0_0 : in std_logic; - un1_grgpio0_2 : in std_logic; - ramwidth : in std_logic_vector(1 downto 0); - rdata_iv_2 : in std_logic_vector(3 downto 2); - readdata_iv_3 : in std_logic_vector(3 downto 2); - tcnt : in std_logic_vector(1 downto 0); - prdata_3_29 : in std_logic; - prdata_3_12 : in std_logic; - prdata_3_0 : in std_logic; - prdata_3_1 : in std_logic; - prdata_3_14 : in std_logic; - prdata_3_13 : in std_logic; - prdata_3_26 : in std_logic; - prdata_3_23 : in std_logic; - prdata_3_16 : in std_logic; - prdata_3_28 : in std_logic; - prdata_3_27 : in std_logic; - prdata_3_17 : in std_logic; - prdata_3_15 : in std_logic; - romwws : in std_logic_vector(3 downto 0); - romwidth : in std_logic_vector(1 downto 0); - rambanksz_0 : in std_logic; - rambanksz_1 : in std_logic; - rambanksz_3 : in std_logic; - prdata_0_iv_0_0_0_13 : in std_logic; - prdata_0_iv_0_0_0_0 : in std_logic; - prdata_0_iv_0_0_0_12 : in std_logic; - prdata_0_iv_0_0_1_13 : in std_logic; - prdata_0_iv_0_0_1_0 : in std_logic; - prdata_0_iv_0_0_1_12 : in std_logic; - readdata_1_iv_0_13 : in std_logic; - readdata_1_iv_0_2 : in std_logic; - readdata_1_iv_0_0 : in std_logic; - readdata_1_iv_0_9 : in std_logic; - readdata_1_iv_0_11 : in std_logic; - prdata_2_20 : in std_logic; - prdata_2_31 : in std_logic; - prdata_2_14 : in std_logic; - prdata_2_1 : in std_logic; - prdata_2_2 : in std_logic; - prdata_2_5 : in std_logic; - prdata_2_0 : in std_logic; - prdata_2_3 : in std_logic; - prdata_2_16 : in std_logic; - prdata_2_21 : in std_logic; - prdata_2_23 : in std_logic; - prdata_2_15 : in std_logic; - prdata_2_27 : in std_logic; - prdata_2_28 : in std_logic; - prdata_2_25 : in std_logic; - prdata_2_18 : in std_logic; - prdata_2_30 : in std_logic; - prdata_2_29 : in std_logic; - prdata_2_19 : in std_logic; - prdata_2_17 : in std_logic; - prdata_2_9 : in std_logic; - prdata_2_13 : in std_logic; - prdata_2_22 : in std_logic; - prdata_2_24 : in std_logic; - prdata_2_26 : in std_logic; - prdata_11_m_1_0 : in std_logic_vector(4 to 4); - prdata_13_m_1_0 : in std_logic_vector(4 to 4); - psel_0 : out std_logic; - psel_15 : out std_logic; - psel_11 : out std_logic; - reload_RNI6SNI : in std_logic_vector(1 to 1); - readdata_9_i_m : in std_logic_vector(1 to 1); - un1_uart1 : in std_logic_vector(36 to 36); - reload_m_0 : in std_logic_vector(0 to 0); - reload_0 : in std_logic_vector(7 downto 6); - un1_dcom0 : in std_logic_vector(19 downto 12); - iows : in std_logic_vector(3 downto 2); - ipend : in std_logic_vector(11 to 11); - iforce_0_m : in std_logic_vector(4 to 4); - ipend_m : in std_logic_vector(4 to 4); - iforce_0_5 : in std_logic; - iforce_0_2 : in std_logic; - iforce_0_1 : in std_logic; - iforce_0_7 : in std_logic; - iforce_0_0 : in std_logic; - ilevel_6 : in std_logic; - ilevel_4 : in std_logic; - ilevel_3 : in std_logic; - ilevel_2 : in std_logic; - ilevel_0 : in std_logic; - ilevel_8 : in std_logic; - ilevel_1 : in std_logic; - oen : in std_logic_vector(7 to 7); - readdata_2_m : in std_logic_vector(5 to 5); - dout_2 : in std_logic; - dout_0 : in std_logic; - dout_6 : in std_logic; - dout_5 : in std_logic; - dout_4 : in std_logic; - value_RNIBAHH : in std_logic_vector(1 to 1); - reload_RNIRDRG : in std_logic_vector(1 to 1); - scaler_i_m : in std_logic_vector(1 to 1); - scaler : in std_logic_vector(4 to 4); - value_6 : in std_logic; - value_0 : in std_logic; - reload_8 : in std_logic; - reload_7 : in std_logic; - reload_6 : in std_logic; - reload_24 : in std_logic; - reload_4 : in std_logic; - reload_3 : in std_logic; - reload_2 : in std_logic; - reload_0_d0 : in std_logic; - reload_1 : in std_logic; - scaler_m_7 : in std_logic; - scaler_m_6 : in std_logic; - scaler_m_0 : in std_logic; - scaler_m_5 : in std_logic; - rcnt : in std_logic_vector(1 downto 0); - rdata_2 : in std_logic_vector(0 to 0); - rcnt_RNI8FBM3 : in std_logic_vector(1 to 1); - rdata_iv_0_a2_3_0 : in std_logic_vector(7 to 7); - brate_9 : in std_logic; - brate_8 : in std_logic; - brate_0 : in std_logic; - brate_10 : in std_logic; - brate_7 : in std_logic; - brate_6 : in std_logic; - rdata_17_m_0 : in std_logic_vector(6 to 6); - brate_m_7 : in std_logic; - brate_m_0 : in std_logic; - brate_m_1 : in std_logic; - rdata_17_m_0_d0 : in std_logic; - rdata_17_m_4 : in std_logic; - rdata_17_m_5 : in std_logic; - rdata_2_m : in std_logic_vector(6 downto 4); - prdata_1_20 : in std_logic; - prdata_1_5 : in std_logic; - prdata_1_12 : in std_logic; - prdata_1_21 : in std_logic; - prdata_1_23 : in std_logic; - prdata_1_27 : in std_logic; - prdata_1_0 : in std_logic; - prdata_1_4 : in std_logic; - prdata_1_6 : in std_logic; - prdata_1_7 : in std_logic; - prdata_1_8 : in std_logic; - prdata_1_9 : in std_logic; - prdata_1_10 : in std_logic; - prdata_1_11 : in std_logic; - prdata_1_22 : in std_logic; - prdata_1_28 : in std_logic; - paddr_5 : out std_logic; - paddr_2_d0 : out std_logic; - paddr_0_d0 : out std_logic; - paddr_1_d0 : out std_logic; - paddr_3 : out std_logic; - paddr_4 : out std_logic; - htrans : in std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - readdata_9_4 : in std_logic; - readdata_9_0 : in std_logic; - readdata_9_5 : in std_logic; - readdata_9_27 : in std_logic; - reload_m_2 : in std_logic; - reload_m_3 : in std_logic; - reload_m_21 : in std_logic; - reload_m_9 : in std_logic; - reload_m_0_d0 : in std_logic; - reload_m_5 : in std_logic; - reload_m_27 : in std_logic; - reload_m_20 : in std_logic; - reload_m_4 : in std_logic; - value_m_22 : in std_logic; - value_m_11 : in std_logic; - value_m_9 : in std_logic; - value_m_18 : in std_logic; - value_m_20 : in std_logic; - value_m_17 : in std_logic; - value_m_4 : in std_logic; - value_m_5 : in std_logic; - value_m_3 : in std_logic; - value_m_0 : in std_logic; - value_m_1 : in std_logic; - value_m_8 : in std_logic; - value_m_7 : in std_logic; - value_m_6 : in std_logic; - value_m_23 : in std_logic; - value_m_24 : in std_logic; - value_m_16 : in std_logic; - prdata_0_1 : in std_logic; - prdata_0_23 : in std_logic; - prdata_0_18 : in std_logic; - prdata_0_30 : in std_logic; - prdata_0_29 : in std_logic; - prdata_0_0 : in std_logic; - prdata_0_8 : in std_logic; - prdata_0_10 : in std_logic; - prdata_0_11 : in std_logic; - prdata_0_12 : in std_logic; - prdata_0_13 : in std_logic; - prdata_0_24 : in std_logic; - prdata_0_26 : in std_logic; - prdata_0_17 : in std_logic; - prdata_0_19 : in std_logic; - prdata_0_25 : in std_logic; - prdata_0_16 : in std_logic; - prdata_0_22 : in std_logic; - prdata_0_15 : in std_logic; - prdata_0_31 : in std_logic; - prdata_0_14 : in std_logic; - prdata_0_21 : in std_logic; - prdata_0_27 : in std_logic; - prdata_0_20 : in std_logic; - prdata_0_4 : in std_logic; - prdata_0_6 : in std_logic; - prdata_0_7 : in std_logic; - prdata_0_5 : in std_logic; - prdata_0_3 : in std_logic; - prdata_0_2 : in std_logic; - prdata_0_28 : in std_logic; - prdata : in std_logic_vector(31 downto 0); - pwdata_i : out std_logic_vector(7 downto 0); - pwdata_1_3 : out std_logic; - pwdata_1_2 : out std_logic; - pwdata_1_0 : out std_logic; - hwdata : in std_logic_vector(31 downto 0); - pwdata_0 : out std_logic_vector(15 downto 0); - paddr_0 : out std_logic_vector(4 downto 2); - paddr_1 : out std_logic_vector(2 to 2); - haddr : in std_logic_vector(19 downto 2); - paddr_2 : out std_logic_vector(2 to 2); - hready : out std_logic; - readdata51_1 : in std_logic; - N_227 : in std_logic; - thempty_1_m : in std_logic; - N_6432 : in std_logic; - rmw : in std_logic; - penable : out std_logic; - un1_apbi_2 : in std_logic; - N_5062 : in std_logic; - break_m : in std_logic; - N_332 : in std_logic; - N_333 : in std_logic; - N_334 : in std_logic; - N_335 : in std_logic; - N_336 : in std_logic; - N_5070 : in std_logic; - breakirqen : in std_logic; - N_6455_0 : in std_logic; - N_773 : out std_logic; - hwrite : in std_logic; - un1_apbi_7_3 : out std_logic; - N_330 : in std_logic; - parerr_m : in std_logic; - rdata60_1 : in std_logic; - N_331 : in std_logic; - N_86 : in std_logic; - N_85 : in std_logic; - un1_apbi_7_1 : in std_logic; - rstn : in std_logic; - bexcen : in std_logic; - ioen : in std_logic; - ovf_m : in std_logic; - parsel_m_0 : in std_logic; - frame : in std_logic; - tcnt_i : in std_logic; - N_156 : in std_logic; - readdata56 : in std_logic; - tfifoirqen_m : in std_logic; - rfifoirqen_m : in std_logic; - debug_m : in std_logic; - delayirqen : in std_logic; - N_127 : in std_logic; - N_78 : out std_logic; - N_232_0 : in std_logic; - brdyen : in std_logic; - N_839 : in std_logic; - prdata_1_sqmuxa : in std_logic; - N_842 : in std_logic; - N_841 : in std_logic; - N_476 : in std_logic; - N_478 : in std_logic; - N_474 : in std_logic; - N_473 : in std_logic; - N_471 : in std_logic; - N_472 : in std_logic; - N_470 : in std_logic; - N_467 : in std_logic; - N_468 : in std_logic; - N_859 : in std_logic; - N_861 : in std_logic; - N_361 : in std_logic; - N_363 : in std_logic; - readdata55_3 : in std_logic; - N_863 : in std_logic; - N_865 : in std_logic; - N_365 : in std_logic; - N_898 : in std_logic; - N_367 : in std_logic; - prdata_0_sqmuxa : in std_logic; - rdata60_4_0 : in std_logic; - N_6437 : in std_logic; - N_6439 : in std_logic; - N_6435 : in std_logic; - N_6436 : in std_logic; - N_6434 : in std_logic; - N_6429 : in std_logic; - N_6430 : in std_logic; - N_6428 : in std_logic; - rdata59_4 : in std_logic; - N_220_0 : in std_logic; - N_219 : in std_logic; - N_240 : in std_logic; - N_218 : in std_logic; - N_236 : in std_logic; - N_229 : in std_logic; - N_228 : in std_logic; - N_216 : in std_logic; - N_217 : in std_logic; - dishlt : in std_logic; - restart_RNIIKBB : in std_logic; - N_215 : in std_logic; - N_214 : in std_logic; - N_240_0 : in std_logic; - readdata57 : in std_logic; - irqpen_m : in std_logic; - readdata55 : in std_logic; - enable_m : in std_logic; - value_0_sqmuxa_0 : in std_logic; - chain_m : in std_logic; - readdata_1_sqmuxa_1_0 : in std_logic; - tsemptyirqen : in std_logic; - rdata_0_sqmuxa : in std_logic; - N_223 : in std_logic; - N_220 : in std_logic; - rdata_3_sqmuxa : in std_logic; - rdata_4_sqmuxa : in std_logic; - paren : in std_logic; - N_770 : in std_logic; - rhalffull_1_m : in std_logic; - flow_m : in std_logic; - extclken_m : in std_logic; - N_769 : out std_logic; - N_116 : out std_logic; - N_796 : out std_logic; - N_750 : out std_logic; - N_749 : out std_logic; - lclk_c : in std_logic; - pwrite : out std_logic; - un51_ioen_NE : in std_logic - ); - -end apbctrl; - -architecture DEF_ARCH of apbctrl is - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal hready_0_sqmuxa_0, hready_0_sqmuxa_0_a3_0_a2_0, - N_12_0_1, \state[0]\, N_12_0_0, \pwrite\, N_751_0, N_745, - N_752_0, N_12_0, \pwdata_0[0]\, \pwdata_0[1]\, - \pwdata_0[2]\, \pwdata_0[3]\, \pwdata_0[4]\, - \pwdata_0[5]\, \pwdata_0[6]\, \pwdata_0[7]\, - \prdata_1_i_0_a11[20]\, N_782_i, \prdata_1_i_0_a11[28]\, - N_678, N_756, \prdata_1_i_0_a11[27]\, - \prdata_1_i_0_a11[21]\, N_111, cfgsel, N_156_i, N_786, - N_101, N_710, \prdata_1_i_0_a11_2_1[20]\, N_50_i_0, - \prdata_1_i_0_4[28]\, N_585, \prdata_1_i_0_a11_6_1[8]\, - N_619_i, \prdata_1_i_0_a11_3_4[4]\, N_675, - \prdata_1_i_0_a11_1_1[28]\, N_681, - \prdata_1_i_0_a11_1_1[27]\, \prdata_1_i_0_a11_2_0[20]\, - \prdata_1_i_0_a11_1_0[27]\, N_761, - \prdata_1_i_0_a11_3_3[4]\, \prdata_1_i_0_a11_3_2[4]\, - \prdata_1_i_0_a11_8_3[6]\, \prdata_1_i_0_a11_8_2[6]\, - \prdata_1_i_0_a11_8_1[6]\, \prdata_1_i_0_a11_8_0[6]\, - \prdata_1_i_0_a11_6_0[8]\, \prdata_1_i_0_3[28]\, - \prdata_1_i_0_2[28]\, \prdata_1_i_0_3[27]\, - \prdata_1_0_0_7[1]\, \prdata_1_0_0_3[1]\, - \prdata_1_0_0_2[1]\, N_630_i, \prdata_1_0_0_6[1]\, N_628, - N_632, N_629, N_633, N_624, \prdata_1_0_0_0[1]\, N_627, - \prdata_1_0_0_a11_1_0[1]\, N_776, N_625, - \prdata_1_0_0_6[2]\, N_735, \prdata_1_0_0_3[2]\, - \prdata_1_0_0_4[2]\, N_733, \prdata_1_0_0_0[2]\, - \prdata_1_0_0_2[2]\, N_762, N_734, N_739, N_722, N_732, - \prdata_1_0_0_7[3]\, N_726, \prdata_1_0_0_4[3]\, - \prdata_1_0_0_5[3]\, N_724, \prdata_1_0_0_1[3]\, - \prdata_1_0_0_3[3]\, N_725, N_730, \prdata_1_0_0_0[3]\, - N_721, N_777, \prdata_1_i_0_8[5]\, - \prdata_1_i_0_a11_4_4[5]\, \prdata_1_i_0_7[5]\, - \prdata_1_i_0_3[5]\, \prdata_1_i_0_2[5]\, - \prdata_1_i_0_6[5]\, \prdata_1_i_0_a11_3_1[5]\, N_771, - \prdata_1_i_0_4[5]\, \prdata_RNO_21[5]\, N_755, N_612_i, - \prdata_RNO_12[5]\, \prdata_1_i_0_0[5]\, - \prdata_RNO_14[5]\, N_544, \prdata_1_i_0_6[7]\, - \prdata_1_i_0_2[7]\, \prdata_1_i_0_1[7]\, - \prdata_1_i_0_5[7]\, \prdata_1_i_0_a11_2_1[7]\, - \prdata_1_i_0_3[7]\, \prdata_RNO_20[7]\, N_592_i, - \prdata_RNO_9[7]\, \prdata_RNO_10[7]\, N_554_i, - \prdata_1_i_0_7[6]\, \prdata_1_i_0_3[6]\, - \prdata_1_i_0_2[6]\, \prdata_1_i_0_6[6]\, - \prdata_1_i_0_a11_3_1[6]\, \prdata_1_i_0_4[6]\, - \prdata_RNO_23[6]\, N_602_i, \prdata_RNO_12[6]\, - \prdata_1_i_0_0[6]\, \prdata_RNO_14[6]\, N_595, N_139, - \prdata_1_i_0_6[4]\, \prdata_1_i_0_2[4]\, - \prdata_1_i_0_1[4]\, \prdata_1_i_0_5[4]\, - \prdata_1_i_0_a11_2_1[4]\, \prdata_1_i_0_3[4]\, - \prdata_RNO_15[4]\, N_621_i, \prdata_RNO_7[4]\, - \prdata_RNO_8[4]\, \prdata_1_i_0_6[10]\, - \prdata_1_i_0_a11_1_1[10]\, \prdata_1_i_0_4[10]\, - \prdata_1_i_0_5[10]\, N_567_i, \prdata_1_i_0_2[10]\, - \prdata_RNO_9[10]\, \prdata_1_i_0_0[10]\, - \prdata_RNO_13[10]\, \prdata_RNO_14[10]\, - \prdata_RNO_15[10]\, \prdata_1_i_0_8[0]\, - \prdata_1_i_0_4[0]\, N_641, \prdata_1_i_0_7[0]\, - \prdata_1_i_0_a11_6_1[0]\, \prdata_1_i_0_5[0]\, - \prdata_RNO_18[0]\, \prdata_1_i_0_2[0]\, - \prdata_RNO_10[0]\, \prdata_1_i_0_0[0]\, - \prdata_1_i_0_1[0]\, N_790, N_82, N_638, - \prdata_1_i_0_1[28]\, \prdata_1_i_0_RNO_3[28]\, - \prdata_1_i_0_RNO_4[28]\, \prdata_1_i_0_6[20]\, - \prdata_RNO_3[20]\, \prdata_1_i_0_3[20]\, - \prdata_1_i_0_5[20]\, \prdata_1_i_0_1[20]\, - \prdata_RNO_6[20]\, N_708, N_789, N_760, - \prdata_1_i_0_2[27]\, \prdata_1_i_0_1[27]\, - \prdata_RNO_4[27]\, \prdata_RNO_5[27]\, - \prdata_1_i_0_6[21]\, \prdata_RNO_3[21]\, - \prdata_1_i_0_3[21]\, N_703, \prdata_1_i_0_5[21]\, - \prdata_1_i_0_1[21]\, \prdata_RNO_7[21]\, N_84, - \prdata_1_i_0_0[21]\, \paddr_0[4]\, \prdata_1_i_0_6[11]\, - \prdata_1_i_0_a11_2_1[11]\, \prdata_1_i_0_4[11]\, - \prdata_1_i_0_5[11]\, N_559_i, \prdata_1_i_0_2[11]\, - \prdata_RNO_8[11]\, \prdata_1_i_0_0[11]\, - \prdata_RNO_12[11]\, \prdata_RNO_13[11]\, - \prdata_RNO_14[11]\, \prdata_1_i_0_6[9]\, - \prdata_1_i_0_3[9]\, \prdata_1_i_0_2[9]\, - \prdata_1_i_0_4[9]\, \prdata_RNO_12[9]\, - \prdata_1_i_0_a11_4_2[9]\, \prdata_1_i_0_0[9]\, - \prdata_RNO_11[9]\, N_778_i, \prdata_0[9]\, - \prdata_RNO_15[9]\, \prdata_1_i_0_6[8]\, - \prdata_RNO_2[8]\, \prdata_RNO_3[8]\, N_580_i, - \prdata_1_i_0_5[8]\, \prdata_RNO_5[8]\, - \prdata_1_i_0_1[8]\, \prdata_1_i_0_3[8]\, - \prdata_1_i_0_a11_4_2[8]\, \prdata_RNO_10[8]\, - \prdata_RNO_11[8]\, \prdata_1_i_0_7[12]\, - \prdata_1_i_0_a11_3_1[12]\, \prdata_1_i_0_5[12]\, - \prdata_1_i_0_6[12]\, N_550_i, \prdata_1_i_0_3[12]\, - \prdata_RNO_8[12]\, \prdata_1_i_0_1[12]\, - \prdata_RNO_12[12]\, \prdata_RNO_13[12]\, - \prdata_RNO_14[12]\, N_543, \prdata_1_i_0_a11_8_3[5]\, - \prdata_1_i_0_a11_8_2[5]\, \prdata_1_i_0_a11_8_0[5]\, - \prdata_1_i_0_a11_7_2[4]\, \prdata_1_i_0_a11_7_0[4]\, - \prdata_1_i_0_a11_7_3[7]\, \prdata_1_i_0_a11_7_1[7]\, - \prdata_1_i_0_a11_7_0[7]\, \prdata_1_0_0_3[26]\, N_516, - \prdata_1_0_0_0[26]\, \prdata_1_0_0_2[26]\, N_519, - \prdata_1_0_0_a11_0[26]\, N_767, N_515, - \prdata_1_i_0_a11_6_0[10]\, \prdata_1_0_0_0_7[14]\, N_758, - \prdata_1_0_0_0_6[14]\, N_207, N_498, - \prdata_1_0_0_0_5[14]\, N_204, \prdata_1_0_0_0_1[14]\, - \prdata_1_0_0_0_3[14]\, N_499, N_202, \prdata_RNO_9[14]\, - N_138, \prdata_1_0_0_6[13]\, N_537, N_540, - \prdata_1_0_0_5[13]\, N_536, \prdata_1_0_0_1[13]\, - \prdata_1_0_0_3[13]\, N_541, \prdata_RNO_9[13]\, N_534, - \prdata_1_0_0_0_2[31]\, \prdata_1_0_0_0_1[31]\, N_509, - N_507, N_510, \prdata_1_i_0_a11_9_3[0]\, - \prdata_1_i_0_a11_9_1[0]\, \prdata_1_i_0_a11_9_0[0]\, - \prdata_1_i_i_5[22]\, \prdata_1_i_i_3[22]\, - \prdata_1_i_i_2[22]\, N_530, N_532, N_527, - \prdata_1_i_i_0[22]\, N_529, N_781, N_526, - \prdata_1_i_0_a11_6_0[9]\, \prdata_1_0_0_a11_5_0[26]\, - \prdata_1_0_0_a11_7_0[14]\, \prdata_1_0_0_2[24]\, N_751, - N_525, \prdata_1_0_0_1[24]\, N_521, N_522, - \prdata_1_0_0_2[17]\, N_649, N_646, \prdata_1_0_0_1[17]\, - N_647, \prdata_1_0_0_2[19]\, N_655, N_654, - \prdata_1_0_0_0[19]\, N_651, \prdata_1_0_0_2[25]\, N_669, - N_668, \prdata_1_0_0_1[25]\, N_672, \prdata_1_0_0_6[15]\, - N_688, \prdata_1_0_0_2[15]\, \prdata_1_0_0_4[15]\, - \prdata_1_0_0_5[15]\, N_689, N_693, \prdata_RNO_7[15]\, - \prdata_1_0_0_0[15]\, \prdata_1_0_0_a11_1_0[15]\, N_766, - N_685, \prdata_1_i_i_4[23]\, N_699, N_698, - \prdata_1_i_i_2[23]\, N_694, \prdata_1_i_i_0[23]\, N_696, - \paddr[6]\, \prdata_1_0_0_4[16]\, \prdata_1_0_0_1[16]\, - N_717, \prdata_1_0_0_2[16]\, N_720, N_715, N_714, N_716, - \prdata_1_0_0_1[29]\, N_658, N_656, N_659, - \prdata_1_0_0_1[30]\, N_662, N_660, N_663, - \prdata_1_0_0_1[18]\, N_666, N_664, N_667, - \prdata_1_i_0_a11_4_1[5]\, \prdata_1_i_0_a11_4_2[5]\, - \prdata_1_i_0_a11_3_4[0]\, \prdata_1_i_0_a11_3_3[0]\, - \prdata_1_i_0_a11_3_1[0]\, \paddr[9]\, N_747, - \prdata_1_i_0_a11_3_1[4]\, \prdata_1_i_0_a11_4_4[6]\, - \prdata_1_i_0_a11_4_1[6]\, \prdata_1_i_0_a11_4_0[6]\, - \prdata_1_i_0_a11_4_2[6]\, \prdata_1_i_0_a11_3_3[7]\, - \prdata_1_i_0_a11_3_0[7]\, \prdata_1_i_0_a11_3_1[7]\, - \prdata_1_0_0_a11_5_3[1]\, \prdata_1_0_0_a11_5_1[1]\, - \prdata_1_i_0_a11_1_2[9]\, \prdata_1_i_0_a11_1_0[9]\, - \prdata_1_i_0_a11_1_2[8]\, \prdata_1_i_0_a11_1_0[8]\, - \prdata_1_i_0_a11_2_0[21]\, \prdata_1_i_0_a11_1_0[28]\, - \prdata_1_i_0_a11_1_0[10]\, \prdata_1_i_0_a11_2_0[11]\, - \prdata_1_i_0_a11_3_0[12]\, \prdata_1_i_0_a11_3_0[5]\, - \un1_grgpio0_m[69]\, \prdata_1_i_0_a11_3_0[6]\, - \prdata_1_i_0_a11_2_0[7]\, \un1_grgpio0_m[71]\, - \prdata_1_i_0_a11_6_1[5]\, \prdata_1_i_0_a11_6_0[5]\, - \prdata_1_i_0_a11_6_1[12]\, \prdata_1_i_0_a11_6_0[12]\, - \prdata_1_i_0_a11_5_1[4]\, \prdata_RNO_16[4]\, - \prdata_1_i_0_a11_5_0[4]\, \prdata_1_i_0_a11_6_1[6]\, - \prdata_1_i_0_a11_6_0[6]\, \prdata_1_i_0_a11_5_1[7]\, - \prdata_1_i_0_a11_5_0[7]\, \prdata_1_i_0_a11_4_1[8]\, - \prdata_1_i_0_a11_4_1[9]\, \prdata_1_i_0_a11_4_1[10]\, - \prdata_1_i_0_a11_4_0[10]\, \prdata_1_i_0_a11_5_1[11]\, - \prdata_1_i_0_a11_5_0[11]\, \prdata_1_i_0_o2_0[11]\, N_90, - \prdata_1_0_0_a11_0[13]\, \prdata_1_i_0_a2_0[21]\, - \paddr[10]\, \paddr[11]\, \psel_0_a3_0_a2_0_a11_0[11]\, - N_772, \prdata_1_i_0_o2_1_0[12]\, \N_78\, - \prdata_1_0_0_0_a2_0[14]\, \paddr_0[3]\, - penable_1_0_0_i_0_a11_0_4, \paddr[13]\, \paddr[12]\, - penable_1_0_0_i_0_a11_0_1, penable_1_0_0_i_0_a11_0_3, - \paddr[18]\, \paddr[19]\, penable_1_0_0_i_0_a11_0_2, - \paddr[16]\, \paddr[17]\, \paddr[14]\, \paddr[15]\, - \prdata_1_i_0_o2_1_5[0]\, \prdata_1_i_0_o2_1_3[0]\, - \prdata_1_i_0_o2_1_4[0]\, \prdata_1_i_0_o2_1_1[0]\, N_763, - N_542, N_561, N_569, N_572_i, N_577_i, N_590_i, N_594_i, - N_600_i, N_604_i, N_623_i, \prdata_1[3]\, N_727, N_731, - \prdata_1[16]\, N_41_i_0, \prdata_RNO_2[21]\, N_60, - \prdata_1[15]\, N_690, N_46_i_0, \prdata_RNO_2[27]\, - \prdata_1[25]\, \prdata_1[18]\, \prdata_1[30]\, - \prdata_1[29]\, \prdata_1[19]\, \prdata_1[17]\, N_58_i_0, - N_639_i, N_645_i, N_61_i_0, N_65_i_0, N_100_i_0, - N_102_i_0, N_104_i_0, N_106_i_0, N_108_i_0, N_110_i_0, - \prdata_RNO_2[12]\, \prdata_1[13]\, N_538, N_30, - \prdata_1[24]\, N_523, penable_RNO, cfgsel2, N_199, N_774, - \paddr_0[2]\, N_117, N_5065, N_63_i_0, hready_0_sqmuxa, - N_5063, \prdata_1[31]\, \prdata_1[2]\, N_736, N_740, - N_6427, \prdata_1[1]\, N_634, \prdata_1[14]\, N_176, - N_794, \N_769\, N_39_i_0, \prdata_RNO_2[20]\, - \prdata_1[26]\, N_517, N_520, \un1_apbi_7_3\, \paddr[5]\, - N_793, \prdata_1_i_0_a11_0[0]\, \prdata_1_i_0_a11_1_0[0]\, - \paddr[8]\, \N_116\, N_5913, \state_nss[0]\, N_795, N_788, - N_131, N_743, N_455, N_132, N_791, N_752, N_744, \N_749\, - N_748, \state[1]\, N_12, N_17, psel_RNO_0, N_5069, - \paddr_2[2]\, \dout_m[1]\, \dout_m[3]\, N_133, \paddr[2]\, - \paddr[3]\, \N_750\, \paddr[4]\, N_155_i, N_746, \N_773\, - psel, N_5860, \state_nss[1]\, N_198, N_34, N_168, - \penable\, \hready\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - paddr_2_d0 <= \paddr[4]\; - paddr_0_d0 <= \paddr[2]\; - paddr_1_d0 <= \paddr[3]\; - paddr_3 <= \paddr[5]\; - paddr_4 <= \paddr[6]\; - pwdata_0(7) <= \pwdata_0[7]\; - pwdata_0(6) <= \pwdata_0[6]\; - pwdata_0(5) <= \pwdata_0[5]\; - pwdata_0(4) <= \pwdata_0[4]\; - pwdata_0(3) <= \pwdata_0[3]\; - pwdata_0(2) <= \pwdata_0[2]\; - pwdata_0(1) <= \pwdata_0[1]\; - pwdata_0(0) <= \pwdata_0[0]\; - paddr_0(4) <= \paddr_0[4]\; - paddr_0(3) <= \paddr_0[3]\; - paddr_0(2) <= \paddr_0[2]\; - paddr_2(2) <= \paddr_2[2]\; - hready <= \hready\; - penable <= \penable\; - N_773 <= \N_773\; - un1_apbi_7_3 <= \un1_apbi_7_3\; - N_78 <= \N_78\; - N_769 <= \N_769\; - N_116 <= \N_116\; - N_750 <= \N_750\; - N_749 <= \N_749\; - pwrite <= \pwrite\; - - \r.pwdata[15]\ : DFN1E0 - port map(D => hwdata(15), CLK => lclk_c, E => N_12_0, Q => - pwdata(15)); - - \r.prdata_RNO_16[0]\ : AOI1B - port map(A => N_790, B => N_82, C => N_638, Y => - \prdata_1_i_0_0[0]\); - - \r.prdata_RNO_0[10]\ : AOI1B - port map(A => \prdata_1_i_0_a11_1_1[10]\, B => value_m_6, C - => \prdata_1_i_0_4[10]\, Y => \prdata_1_i_0_6[10]\); - - \r.prdata_RNO[6]\ : NOR3C - port map(A => N_600_i, B => \prdata_1_i_0_7[6]\, C => - N_604_i, Y => N_65_i_0); - - \r.prdata_RNO_3[29]\ : OR2B - port map(A => prdata_3_27, B => N_752, Y => N_659); - - \r.prdata_RNO_15[9]\ : OR3A - port map(A => N_772, B => N_743, C => prdata_1_9, Y => - \prdata_RNO_15[9]\); - - \r.prdata_RNO_2[10]\ : OR3C - port map(A => rfifoirqen_m, B => \prdata_1_i_0_a11_6_0[10]\, - C => prdata_0_28, Y => N_569); - - \r.prdata_RNO_8[12]\ : OR2A - port map(A => N_752, B => prdata_1_12, Y => - \prdata_RNO_8[12]\); - - \r.prdata_RNO_2[9]\ : OR3 - port map(A => prdata_0_22, B => \prdata_1_i_0_a11_6_0[9]\, - C => tfifoirqen_m, Y => N_577_i); - - \r.prdata_RNO_3[23]\ : NOR3C - port map(A => N_694, B => \prdata_1_i_i_0[23]\, C => N_696, - Y => \prdata_1_i_i_2[23]\); - - \r.prdata_RNO[8]\ : NOR3C - port map(A => \prdata_1_i_0_6[8]\, B => \prdata_1_i_0_5[8]\, - C => N_585, Y => N_102_i_0); - - \r.prdata_RNO_4[14]\ : AO1B - port map(A => prdata_0_iv_0_0_1_13, B => - prdata_0_iv_0_0_0_13, C => N_762, Y => N_498); - - \r.prdata_RNO_0[0]\ : NOR3C - port map(A => \prdata_1_i_0_4[0]\, B => N_641, C => - \prdata_1_i_0_7[0]\, Y => \prdata_1_i_0_8[0]\); - - \r.pwdata[30]\ : DFN1E0 - port map(D => hwdata(30), CLK => lclk_c, E => N_12, Q => - pwdata(30)); - - \r.prdata_RNO_7[14]\ : NOR3C - port map(A => N_202, B => \prdata_RNO_9[14]\, C => N_138, Y - => \prdata_1_0_0_0_1[14]\); - - \r.prdata_RNO[19]\ : AO1B - port map(A => prdata_0_19, B => N_758, C => - \prdata_1_0_0_2[19]\, Y => \prdata_1[19]\); - - \r.prdata[2]\ : DFN1 - port map(D => \prdata_1[2]\, CLK => lclk_c, Q => hrdata(2)); - - \r.prdata_RNO_3[27]\ : NOR3C - port map(A => \prdata_RNO_4[27]\, B => - \prdata_1_i_0_a11[27]\, C => \prdata_RNO_5[27]\, Y => - \prdata_1_i_0_1[27]\); - - \r.prdata_RNO_1[31]\ : NOR3C - port map(A => N_509, B => N_507, C => N_510, Y => - \prdata_1_0_0_0_1[31]\); - - \r.prdata_RNO_5[7]\ : AOI1B - port map(A => \prdata_1_i_0_a11_2_1[7]\, B => N_771, C => - \prdata_1_i_0_3[7]\, Y => \prdata_1_i_0_5[7]\); - - \r.prdata_RNO_12[6]\ : AO1C - port map(A => \paddr_0[3]\, B => N_455, C => N_767, Y => - \prdata_RNO_12[6]\); - - \r.prdata_RNO_12[0]\ : OA1A - port map(A => N_751_0, B => prdata(0), C => - \prdata_RNO_18[0]\, Y => \prdata_1_i_0_5[0]\); - - \r.prdata_RNO_4[23]\ : OR3B - port map(A => iows(3), B => N_767, C => N_232_0, Y => N_694); - - \r.pwdata_0[11]\ : DFN1E0 - port map(D => hwdata(11), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(11)); - - \r.prdata_RNO_4[0]\ : OR2A - port map(A => prdata_0_0, B => N_763, Y => N_641); - - \r.cfgsel_RNIESL4\ : OR2B - port map(A => cfgsel, B => N_90, Y => N_793); - - \r.hwrite_RNO\ : NOR2B - port map(A => rstn, B => N_5913, Y => N_17); - - \r.prdata_RNO_11[10]\ : AOI1B - port map(A => iforce_0_5, B => N_898, C => N_476, Y => - \prdata_1_i_0_a11_4_0[10]\); - - \r.prdata_RNO_4[27]\ : OR3A - port map(A => N_744, B => \N_78\, C => prdata_1_27, Y => - \prdata_RNO_4[27]\); - - \r.prdata_RNO_1[18]\ : OR2B - port map(A => prdata_2_18, B => N_751, Y => N_666); - - \r.prdata_RNO[17]\ : AO1B - port map(A => prdata_0_17, B => N_758, C => - \prdata_1_0_0_2[17]\, Y => \prdata_1[17]\); - - \r.prdata_RNO_6[11]\ : NOR3B - port map(A => \prdata_1_i_0_0[11]\, B => - \prdata_RNO_12[11]\, C => N_554_i, Y => - \prdata_1_i_0_2[11]\); - - \r.haddr[17]\ : DFN1E1 - port map(D => haddr(17), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[17]\); - - \r.prdata_RNO_1[0]\ : OR3C - port map(A => \prdata_1_i_0_a11_3_4[0]\, B => - \prdata_1_i_0_a11_3_3[0]\, C => reload_m_0(0), Y => - N_639_i); - - \r.prdata_RNO_13[7]\ : AOI1B - port map(A => N_240_0, B => N_215, C => N_758, Y => - \prdata_1_i_0_a11_3_0[7]\); - - \r.prdata_RNO_0[22]\ : NOR3C - port map(A => \prdata_1_i_i_3[22]\, B => - \prdata_1_i_i_2[22]\, C => N_530, Y => - \prdata_1_i_i_5[22]\); - - \r.prdata_RNO_7[3]\ : OR3B - port map(A => N_331, B => rdata60_1, C => N_763, Y => N_725); - - \r.prdata_RNO_11[12]\ : NOR3B - port map(A => \prdata_RNO_14[12]\, B => N_543, C => N_544, - Y => \prdata_1_i_0_1[12]\); - - \r.prdata_RNO_4[3]\ : AOI1B - port map(A => prdata(3), B => N_762, C => N_725, Y => - \prdata_1_0_0_4[3]\); - - \r.prdata_RNO_8[16]\ : XOR2 - port map(A => \paddr[4]\, B => \paddr[3]\, Y => N_155_i); - - \r.prdata_RNO_3[10]\ : OA1A - port map(A => reload_6, B => readdata_1_sqmuxa_1_0, C => - \prdata_1_i_0_a11_1_0[10]\, Y => - \prdata_1_i_0_a11_1_1[10]\); - - \comb.v.prdata_1_i_0_RNO_0[28]\ : AND2 - port map(A => N_156_i, B => N_675, Y => - \prdata_1_i_0_3[28]\); - - \r.prdata_RNO_5[3]\ : NOR3C - port map(A => N_724, B => \prdata_1_0_0_1[3]\, C => - \prdata_1_0_0_3[3]\, Y => \prdata_1_0_0_5[3]\); - - \r.prdata_RNO_5[15]\ : AOI1B - port map(A => prdata_0_15, B => N_751, C => N_693, Y => - \prdata_1_0_0_4[15]\); - - \r.prdata_RNO_2[0]\ : AO1B - port map(A => un1_uart1(36), B => prdata(31), C => - \prdata_1_i_0_a11_9_3[0]\, Y => N_645_i); - - \r.prdata_RNO_9[8]\ : OA1A - port map(A => reload_4, B => readdata_1_sqmuxa_1_0, C => - value_m_4, Y => \prdata_1_i_0_a11_1_2[8]\); - - \r.prdata_RNO_9[6]\ : AOI1B - port map(A => N_240_0, B => N_214, C => N_758, Y => - \prdata_1_i_0_a11_4_0[6]\); - - \r.prdata[1]\ : DFN1 - port map(D => \prdata_1[1]\, CLK => lclk_c, Q => hrdata(1)); - - \r.haddr[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[2]\); - - \r.prdata_RNO[16]\ : AO1B - port map(A => prdata_0_16, B => N_758, C => - \prdata_1_0_0_4[16]\, Y => \prdata_1[16]\); - - \r.haddr[3]\ : DFN1E1 - port map(D => haddr(3), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[3]\); - - \r.prdata_RNO_4[11]\ : OA1A - port map(A => N_751_0, B => prdata(11), C => - \prdata_RNO_8[11]\, Y => \prdata_1_i_0_4[11]\); - - \comb.v.prdata_1_i_0_a2_1_RNO[28]\ : XA1C - port map(A => \paddr[10]\, B => \paddr[11]\, C => N_82, Y - => N_111); - - \r.prdata_RNO_0[26]\ : AO1B - port map(A => readdata_1_iv_0_13, B => value_m_22, C => - N_758, Y => N_517); - - \r.prdata_RNO_7[11]\ : AOI1B - port map(A => N_240, B => N_219, C => N_761, Y => - \prdata_1_i_0_a11_2_0[11]\); - - \r.cfgsel_RNIR01K\ : AOI1B - port map(A => \paddr[2]\, B => N_176, C => cfgsel, Y => - N_554_i); - - \r.prdata_RNO_7[5]\ : OA1A - port map(A => reload_1, B => readdata_1_sqmuxa_1_0, C => - value_m_1, Y => \prdata_1_i_0_a11_4_2[5]\); - - \r.prdata_RNO[25]\ : AO1B - port map(A => prdata_0_25, B => N_758, C => - \prdata_1_0_0_2[25]\, Y => \prdata_1[25]\); - - \r.pwdata_1[4]\ : DFN1E0 - port map(D => hwdata(4), CLK => lclk_c, E => N_12_0_1, Q - => pwdata_1_3); - - \comb.v.prdata_1_i_0_a11_2[20]\ : NAND2 - port map(A => value_m_16, B => \prdata_1_i_0_a11_2_1[20]\, - Y => N_710); - - \r.prdata_RNO_13[0]\ : NOR3B - port map(A => \paddr[9]\, B => enable_m, C => N_747, Y => - \prdata_1_i_0_a11_3_1[0]\); - - \r.haddr_RNIPGOP1[8]\ : OR3C - port map(A => \prdata_1_i_0_o2_1_4[0]\, B => - \prdata_1_i_0_o2_1_5[0]\, C => N_788, Y => N_82); - - \r.prdata_RNO_11[3]\ : OA1A - port map(A => N_777, B => N_770, C => N_722, Y => - \prdata_1_0_0_0[3]\); - - \r.prdata[14]\ : DFN1 - port map(D => \prdata_1[14]\, CLK => lclk_c, Q => - hrdata(14)); - - \r.haddr_RNIBMI7[4]\ : OR3B - port map(A => N_766, B => \paddr[4]\, C => N_760, Y => - N_722); - - \r.prdata_RNO_1[22]\ : AOI1B - port map(A => prdata(22), B => N_751_0, C => N_532, Y => - \prdata_1_i_i_3[22]\); - - \r.prdata_RNO_2[5]\ : NOR3C - port map(A => rdata_2_m(5), B => rdata_17_m_5, C => - \prdata_1_i_0_a11_8_0[5]\, Y => \prdata_1_i_0_a11_8_2[5]\); - - \r.prdata_RNO_9[13]\ : OR2A - port map(A => N_84, B => N_793, Y => \prdata_RNO_9[13]\); - - \r.prdata_RNO_10[1]\ : OR3B - port map(A => N_5063, B => N_767, C => \paddr_0[3]\, Y => - N_624); - - \r.prdata_RNO_25[6]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_6, C => N_756, Y - => \prdata_1_i_0_a11_8_0[6]\); - - \r.cfgsel_RNINRQH\ : NOR2A - port map(A => cfgsel, B => N_176, Y => N_544); - - \r.pwdata_0[15]\ : DFN1E0 - port map(D => hwdata(15), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(15)); - - \r.hwrite\ : DFN1 - port map(D => N_17, CLK => lclk_c, Q => \pwrite\); - - \r.prdata[22]\ : DFN1 - port map(D => N_30, CLK => lclk_c, Q => hrdata(22)); - - \r.prdata[8]\ : DFN1 - port map(D => N_102_i_0, CLK => lclk_c, Q => hrdata(8)); - - \r.pwdata[27]\ : DFN1E0 - port map(D => hwdata(27), CLK => lclk_c, E => N_12, Q => - pwdata(27)); - - \r.prdata_RNO_11[4]\ : NOR2B - port map(A => N_756, B => brate_m_0, Y => - \prdata_1_i_0_a11_7_0[4]\); - - \r.prdata_RNO_6[9]\ : AOI1B - port map(A => N_240_0, B => N_217, C => N_761, Y => - \prdata_1_i_0_a11_1_0[9]\); - - \r.prdata_RNO_8[15]\ : AOI1B - port map(A => \prdata_1_0_0_a11_1_0[15]\, B => N_766, C => - N_685, Y => \prdata_1_0_0_0[15]\); - - \r.prdata_RNO_3[24]\ : OR2B - port map(A => prdata_2_24, B => N_752_0, Y => N_525); - - \r.prdata_RNO_18[0]\ : OR2A - port map(A => N_752, B => prdata_1_0, Y => - \prdata_RNO_18[0]\); - - \r.prdata_RNO_14[6]\ : AO1 - port map(A => rdata60_1, B => N_333, C => N_763, Y => - \prdata_RNO_14[6]\); - - \r.prdata_RNO_8[7]\ : OR3C - port map(A => \prdata_1_i_0_a11_5_1[7]\, B => - \prdata_1_i_0_a11_5_0[7]\, C => N_762, Y => N_592_i); - - \comb.v.prdata_1_i_0_a11_1_RNO[28]\ : OA1A - port map(A => reload_24, B => readdata_1_sqmuxa_1_0, C => - \prdata_1_i_0_a11_1_0[28]\, Y => - \prdata_1_i_0_a11_1_1[28]\); - - \v.hready_0_sqmuxa_0_a3_0_a2_0\ : NOR2B - port map(A => iosn_0(93), B => htrans(1), Y => - hready_0_sqmuxa_0_a3_0_a2_0); - - \r.prdata_RNO_1[26]\ : NOR3C - port map(A => N_516, B => \prdata_1_0_0_0[26]\, C => - \prdata_1_0_0_2[26]\, Y => \prdata_1_0_0_3[26]\); - - \r.prdata_RNO_10[15]\ : NOR3B - port map(A => cfgsel, B => \paddr_0[3]\, C => \paddr_0[4]\, - Y => \prdata_1_0_0_a11_1_0[15]\); - - \r.prdata[0]\ : DFN1 - port map(D => N_58_i_0, CLK => lclk_c, Q => hrdata(0)); - - \r.prdata_RNO_4[24]\ : OR3A - port map(A => un1_apbi_7_1, B => N_760, C => N_84, Y => - N_521); - - \r.prdata_RNO_1[4]\ : OR3C - port map(A => parsel_m_0, B => \prdata_1_i_0_a11_7_2[4]\, C - => ovf_m, Y => N_623_i); - - \comb.v.prdata_1_i_0_a11_1_RNO_0[28]\ : AOI1B - port map(A => N_240_0, B => N_236, C => N_761, Y => - \prdata_1_i_0_a11_1_0[28]\); - - \r.haddr_0[4]\ : DFN1E1 - port map(D => haddr(4), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr_0[4]\); - - \comb.v.prdata_1_i_0_a11_1[27]\ : NAND2 - port map(A => value_m_23, B => \prdata_1_i_0_a11_1_1[27]\, - Y => N_681); - - \r.pwdata[12]\ : DFN1E0 - port map(D => hwdata(12), CLK => lclk_c, E => N_12_0, Q => - pwdata(12)); - - \r.prdata[31]\ : DFN1 - port map(D => \prdata_1[31]\, CLK => lclk_c, Q => - hrdata(31)); - - \r.prdata_RNO_2[20]\ : AO1C - port map(A => N_156, B => tcnt(0), C => N_756, Y => - \prdata_RNO_2[20]\); - - \r.prdata_RNO_1[10]\ : NOR3B - port map(A => N_567_i, B => \prdata_1_i_0_2[10]\, C => - N_771, Y => \prdata_1_i_0_5[10]\); - - \comb.v.prdata_1_i_0_a11_3[4]\ : NAND2 - port map(A => reload_m_4, B => \prdata_1_i_0_a11_3_4[4]\, Y - => N_619_i); - - \r.psel\ : DFN1 - port map(D => N_34, CLK => lclk_c, Q => psel); - - \r.prdata_RNO_11[0]\ : NOR3C - port map(A => N_6428, B => N_6430, C => N_6429, Y => - \prdata_1_i_0_a11_6_1[0]\); - - \r.prdata_RNO_0[25]\ : NOR3C - port map(A => N_669, B => N_668, C => \prdata_1_0_0_1[25]\, - Y => \prdata_1_0_0_2[25]\); - - \r.prdata_RNO_12[3]\ : OR3B - port map(A => N_5065, B => N_767, C => \paddr_0[3]\, Y => - N_721); - - \r.prdata_RNO_6[7]\ : NOR3C - port map(A => \prdata_1_i_0_a11_3_0[7]\, B => scaler_m_7, C - => \prdata_1_i_0_a11_3_1[7]\, Y => - \prdata_1_i_0_a11_3_3[7]\); - - \r.haddr[12]\ : DFN1E1 - port map(D => haddr(12), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[12]\); - - \r.pwdata[6]\ : DFN1E0 - port map(D => hwdata(6), CLK => lclk_c, E => N_12, Q => - pwdata(6)); - - \r.prdata_RNO_7[20]\ : OR3B - port map(A => cfgsel, B => N_84, C => \paddr[4]\, Y => - N_708); - - \r.pwdata_0[9]\ : DFN1E0 - port map(D => hwdata(9), CLK => lclk_c, E => N_12_0_1, Q - => pwdata_0(9)); - - \r.prdata_RNO_5[6]\ : NOR3C - port map(A => \prdata_RNO_12[6]\, B => \prdata_1_i_0_0[6]\, - C => \prdata_RNO_14[6]\, Y => \prdata_1_i_0_2[6]\); - - \r.pwdata[0]\ : DFN1E0 - port map(D => hwdata(0), CLK => lclk_c, E => N_12_0, Q => - pwdata(0)); - - \r.prdata_RNO_12[1]\ : OR2B - port map(A => prdata_0_1, B => N_755, Y => N_627); - - \r.haddr_RNI3SB72_1[11]\ : NOR2 - port map(A => \N_750\, B => N_747, Y => N_756); - - \r.pwdata_0_RNI13B[6]\ : INV - port map(A => \pwdata_0[6]\, Y => pwdata_i(6)); - - \r.prdata_RNO_6[23]\ : OR2B - port map(A => prdata_0_23, B => N_755, Y => N_696); - - \r.pwdata[23]\ : DFN1E0 - port map(D => hwdata(23), CLK => lclk_c, E => N_12_0_0, Q - => pwdata(23)); - - \r.prdata_RNO_12[8]\ : NOR3C - port map(A => N_468, B => N_467, C => - \prdata_1_i_0_a11_4_1[8]\, Y => \prdata_1_i_0_a11_4_2[8]\); - - \r.pwdata_0[8]\ : DFN1E0 - port map(D => hwdata(8), CLK => lclk_c, E => N_12_0_1, Q - => pwdata_0(8)); - - \r.prdata_RNO_9[26]\ : OR2B - port map(A => prdata_2_26, B => N_752_0, Y => N_519); - - \r.haddr_RNIBAC4[3]\ : NOR2B - port map(A => \paddr[4]\, B => \paddr[3]\, Y => N_90); - - \r.prdata_RNO_20[6]\ : MX2 - port map(A => romwws(2), B => rmw, S => \paddr_2[2]\, Y => - N_455); - - \r.prdata_RNO_23[6]\ : OR2A - port map(A => N_752_0, B => prdata_1_6, Y => - \prdata_RNO_23[6]\); - - \r.prdata_RNO_16[6]\ : OA1A - port map(A => N_751_0, B => prdata(6), C => - \prdata_RNO_23[6]\, Y => \prdata_1_i_0_4[6]\); - - \r.cfgsel_RNI7OLL1\ : OR3B - port map(A => \prdata_1_i_0_o2_1_4[0]\, B => - \prdata_1_i_0_o2_1_5[0]\, C => cfgsel, Y => N_743); - - \r.prdata_RNO_3[21]\ : OR2A - port map(A => N_751, B => prdata_2_21, Y => - \prdata_RNO_3[21]\); - - \comb.v.prdata_1_i_0_a11_1_RNO_0[27]\ : AND2 - port map(A => readdata_9_27, B => N_761, Y => - \prdata_1_i_0_a11_1_0[27]\); - - \r.prdata_RNO_13[9]\ : NOR2B - port map(A => N_473, B => N_474, Y => - \prdata_1_i_0_a11_4_1[9]\); - - \r.prdata_RNO_6[6]\ : AOI1B - port map(A => \prdata_1_i_0_a11_3_1[6]\, B => N_771, C => - \prdata_1_i_0_4[6]\, Y => \prdata_1_i_0_6[6]\); - - \r.pwdata[8]\ : DFN1E0 - port map(D => hwdata(8), CLK => lclk_c, E => N_12, Q => - pwdata(8)); - - \r.prdata_RNO_1[8]\ : NOR3C - port map(A => \prdata_RNO_5[8]\, B => \prdata_1_i_0_1[8]\, - C => \prdata_1_i_0_3[8]\, Y => \prdata_1_i_0_5[8]\); - - \r.prdata_RNO_5[13]\ : NOR3C - port map(A => N_536, B => \prdata_1_0_0_1[13]\, C => - \prdata_1_0_0_3[13]\, Y => \prdata_1_0_0_5[13]\); - - \r.prdata_RNO_4[21]\ : NOR3C - port map(A => \prdata_1_i_0_a11[21]\, B => - \prdata_1_i_0_1[21]\, C => \prdata_RNO_7[21]\, Y => - \prdata_1_i_0_3[21]\); - - \r.haddr[10]\ : DFN1E1 - port map(D => haddr(10), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[10]\); - - \r.prdata_RNO_0[2]\ : AO1B - port map(A => readdata_iv_3(2), B => reload_m_2, C => N_758, - Y => N_736); - - \r.prdata[15]\ : DFN1 - port map(D => \prdata_1[15]\, CLK => lclk_c, Q => - hrdata(15)); - - \r.state[1]\ : DFN1 - port map(D => \state_nss[1]\, CLK => lclk_c, Q => - \state[1]\); - - \r.prdata_RNO_3[2]\ : AO1B - port map(A => prdata_iv_0_0(2), B => N_6432, C => N_771, Y - => N_735); - - \r.haddr[8]\ : DFN1E1 - port map(D => haddr(8), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[8]\); - - \comb.v.prdata_1_i_0_a11_3_RNO[4]\ : AND2 - port map(A => \prdata_1_i_0_a11_3_3[4]\, B => - \prdata_1_i_0_a11_3_2[4]\, Y => \prdata_1_i_0_a11_3_4[4]\); - - \r.state_RNI4KU3_2[0]\ : OR2B - port map(A => \pwrite\, B => \state[0]\, Y => N_12_0); - - \r.cfgsel_RNIM601_0\ : NOR2B - port map(A => \paddr_0[2]\, B => cfgsel, Y => N_774); - - \r.haddr[9]\ : DFN1E1 - port map(D => haddr(9), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[9]\); - - \r.prdata_RNO_1[25]\ : OR2B - port map(A => prdata_2_25, B => N_755, Y => N_669); - - \r.cfgsel_RNI1HC5\ : NOR2B - port map(A => N_774, B => N_90, Y => N_781); - - \r.prdata_RNO_9[14]\ : OR2 - port map(A => readdata51_1, B => N_793, Y => - \prdata_RNO_9[14]\); - - \r.prdata_RNO_13[1]\ : NOR3C - port map(A => N_758, B => \prdata_1_0_0_a11_5_1[1]\, C => - scaler_i_m(1), Y => \prdata_1_0_0_a11_5_3[1]\); - - \r.haddr_RNIFPAD[14]\ : NOR2B - port map(A => \paddr[14]\, B => \paddr[15]\, Y => - penable_1_0_0_i_0_a11_0_1); - - \r.prdata_RNO_14[3]\ : MX2 - port map(A => romrws(3), B => ramwws(1), S => \paddr[2]\, Y - => N_5065); - - \r.prdata_RNO_5[9]\ : OA1A - port map(A => N_751_0, B => prdata(9), C => - \prdata_RNO_12[9]\, Y => \prdata_1_i_0_4[9]\); - - \r.prdata_RNO_1[9]\ : OR3C - port map(A => reload_m_9, B => \prdata_1_i_0_a11_1_0[9]\, C - => \prdata_1_i_0_a11_1_2[9]\, Y => N_572_i); - - \r.prdata_RNO_18[5]\ : AOI1B - port map(A => iforce_0_0, B => N_898, C => N_365, Y => - \prdata_1_i_0_a11_6_0[5]\); - - \r.haddr_RNI991B[11]\ : NOR2A - port map(A => \paddr[11]\, B => \N_78\, Y => N_772); - - \r.state_RNO[1]\ : NOR3B - port map(A => \state[0]\, B => rstn, C => \state[1]\, Y => - \state_nss[1]\); - - \r.pwdata[3]\ : DFN1E0 - port map(D => hwdata(3), CLK => lclk_c, E => N_12, Q => - pwdata(3)); - - \comb.v.prdata_1_i_0_o11[28]\ : NOR2B - port map(A => N_786, B => N_101, Y => N_156_i); - - \r.prdata_RNO_8[9]\ : AO1B - port map(A => rdata_3_sqmuxa, B => brate_9, C => N_756, Y - => \prdata_1_i_0_a11_6_0[9]\); - - \r.prdata_RNO_9[9]\ : NOR3C - port map(A => N_472, B => N_471, C => - \prdata_1_i_0_a11_4_1[9]\, Y => \prdata_1_i_0_a11_4_2[9]\); - - \r.pwdata[29]\ : DFN1E0 - port map(D => hwdata(29), CLK => lclk_c, E => N_12, Q => - pwdata(29)); - - \r.prdata_RNO_3[31]\ : OR2B - port map(A => prdata_4(31), B => N_755, Y => N_507); - - \r.haddr_RNIS3MH_1[10]\ : AXOI5 - port map(A => \N_78\, B => \paddr[10]\, C => \paddr[11]\, Y - => \prdata_1_i_0_o2_1_0[12]\); - - \r.prdata_RNO_14[1]\ : OR2B - port map(A => rdata59_4, B => dout_0, Y => \dout_m[1]\); - - \r.prdata_RNO_21[6]\ : AO1A - port map(A => \paddr[6]\, B => \paddr_0[4]\, C => N_760, Y - => N_595); - - \r.haddr_RNILAC4[8]\ : OR2B - port map(A => \paddr[9]\, B => \paddr[8]\, Y => \N_78\); - - \r.prdata_RNO[23]\ : AO1B - port map(A => prdata(23), B => N_758, C => - \prdata_1_i_i_4[23]\, Y => N_60); - - \r.hwrite_RNO_0\ : MX2 - port map(A => \pwrite\, B => hwrite, S => hready_0_sqmuxa_0, - Y => N_5913); - - GND_i : GND - port map(Y => \GND\); - - \r.prdata_RNO_11[7]\ : AOI1B - port map(A => rdata59_4, B => dout_6, C => - \prdata_1_i_0_a11_2_0[7]\, Y => \prdata_1_i_0_a11_2_1[7]\); - - \r.prdata_RNO_15[10]\ : AO1A - port map(A => N_6455_0, B => rambanksz_1, C => N_778_i, Y - => \prdata_RNO_15[10]\); - - \r.prdata[28]\ : DFN1 - port map(D => N_50_i_0, CLK => lclk_c, Q => hrdata(28)); - - \r.prdata_RNO_5[8]\ : AO1 - port map(A => rdata60_1, B => N_335, C => N_763, Y => - \prdata_RNO_5[8]\); - - \r.prdata_RNO_5[22]\ : OR3B - port map(A => iows(2), B => N_767, C => N_232_0, Y => N_527); - - \r.prdata_RNO_15[12]\ : AO1C - port map(A => \paddr[6]\, B => \paddr_0[4]\, C => N_776, Y - => N_543); - - \r.pwdata_0[1]\ : DFN1E0 - port map(D => hwdata(1), CLK => lclk_c, E => N_12_0_0, Q - => \pwdata_0[1]\); - - \r.prdata_RNO_4[8]\ : OR3C - port map(A => readdata57, B => \prdata_1_i_0_a11_1_0[8]\, C - => \prdata_1_i_0_a11_1_2[8]\, Y => N_580_i); - - \r.state_RNO[0]\ : NOR3C - port map(A => N_795, B => hready_0_sqmuxa_0, C => rstn, Y - => \state_nss[0]\); - - \r.pwdata_0[14]\ : DFN1E0 - port map(D => hwdata(14), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(14)); - - \r.pwdata_0[5]\ : DFN1E0 - port map(D => hwdata(5), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[5]\); - - \r.prdata_RNO_1[30]\ : OR2B - port map(A => prdata_2_30, B => N_751, Y => N_662); - - \comb.v.prdata_1_i_0_RNO_1[28]\ : OA1A - port map(A => N_752_0, B => prdata_1_28, C => - \prdata_1_i_0_1[28]\, Y => \prdata_1_i_0_2[28]\); - - \r.prdata_RNO_8[26]\ : OR2A - port map(A => \un1_apbi_7_3\, B => N_760, Y => N_515); - - \r.haddr[18]\ : DFN1E1 - port map(D => haddr(18), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[18]\); - - \r.prdata_RNO_8[13]\ : AOI1B - port map(A => prdata(13), B => N_751_0, C => N_541, Y => - \prdata_1_0_0_3[13]\); - - \r.prdata_RNO_7[6]\ : AND2 - port map(A => flow_m, B => \prdata_1_i_0_a11_8_2[6]\, Y => - \prdata_1_i_0_a11_8_3[6]\); - - \r.prdata_RNO_0[12]\ : AOI1B - port map(A => \prdata_1_i_0_a11_3_1[12]\, B => value_m_8, C - => \prdata_1_i_0_5[12]\, Y => \prdata_1_i_0_7[12]\); - - \r.prdata_RNO_16[7]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_7, C => N_756, Y - => \prdata_1_i_0_a11_7_0[7]\); - - \r.prdata_RNO_9[11]\ : NOR2B - port map(A => N_841, B => N_842, Y => - \prdata_1_i_0_a11_5_1[11]\); - - \r.prdata_RNO_2[12]\ : AO1B - port map(A => breakirqen, B => prdata(31), C => N_756, Y - => \prdata_RNO_2[12]\); - - \r.pwdata[18]\ : DFN1E0 - port map(D => hwdata(18), CLK => lclk_c, E => N_12_0, Q => - pwdata(18)); - - \r.haddr_RNIBAC4_0[3]\ : NOR2A - port map(A => \paddr[4]\, B => \paddr[3]\, Y => N_791); - - \r.prdata_RNO_6[10]\ : NOR3B - port map(A => \prdata_1_i_0_0[10]\, B => - \prdata_RNO_13[10]\, C => N_554_i, Y => - \prdata_1_i_0_2[10]\); - - \r.haddr[16]\ : DFN1E1 - port map(D => haddr(16), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[16]\); - - \r.prdata_RNO_8[6]\ : OA1A - port map(A => reload_2, B => readdata_1_sqmuxa_1_0, C => - readdata57, Y => \prdata_1_i_0_a11_4_1[6]\); - - \r.haddr[19]\ : DFN1E1 - port map(D => haddr(19), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[19]\); - - \r.prdata_RNO_10[13]\ : AO1C - port map(A => \paddr_0[2]\, B => un1_apbi_7_1, C => - \prdata_1_0_0_a11_0[13]\, Y => N_534); - - \r.prdata_RNO_12[11]\ : AO1 - port map(A => un1_dcom0(13), B => N_127, C => N_763, Y => - \prdata_RNO_12[11]\); - - \r.prdata_RNO_9[5]\ : NOR3C - port map(A => \prdata_RNO_12[5]\, B => \prdata_1_i_0_0[5]\, - C => \prdata_RNO_14[5]\, Y => \prdata_1_i_0_2[5]\); - - \r.prdata_RNO_5[26]\ : AOI1B - port map(A => prdata(26), B => N_751_0, C => N_519, Y => - \prdata_1_0_0_2[26]\); - - \r.penable_RNO_1\ : NOR2A - port map(A => \state[1]\, B => \penable\, Y => N_131); - - \r.haddr_RNI3SB72[8]\ : NOR2 - port map(A => \N_749\, B => N_745, Y => N_751); - - \r.prdata_RNO_0[29]\ : NOR3C - port map(A => N_658, B => N_656, C => N_659, Y => - \prdata_1_0_0_1[29]\); - - \r.haddr_RNIQIAS1[10]\ : NOR2A - port map(A => \paddr[10]\, B => N_743, Y => N_744); - - \r.state_RNO_0[0]\ : NOR2 - port map(A => \state[1]\, B => \state[0]\, Y => N_795); - - \r.prdata_RNO_0[23]\ : NOR3C - port map(A => N_699, B => N_698, C => \prdata_1_i_i_2[23]\, - Y => \prdata_1_i_i_4[23]\); - - \r.prdata[4]\ : DFN1 - port map(D => N_61_i_0, CLK => lclk_c, Q => hrdata(4)); - - \r.cfgsel_RNIISL4\ : OR2A - port map(A => cfgsel, B => N_770, Y => - \prdata_1_0_0_0_a2_0[14]\); - - \r.pwdata_0_RNIVQA[4]\ : INV - port map(A => \pwdata_0[4]\, Y => pwdata_i(4)); - - \r.prdata_RNO_3[4]\ : NOR3B - port map(A => \prdata_RNO_7[4]\, B => \prdata_RNO_8[4]\, C - => N_554_i, Y => \prdata_1_i_0_1[4]\); - - \r.psel_RNO_1\ : MX2A - port map(A => \state[0]\, B => \penable\, S => \state[1]\, - Y => N_168); - - \r.prdata_RNO_0[27]\ : AND2 - port map(A => N_156_i, B => N_681, Y => - \prdata_1_i_0_3[27]\); - - \r.pwdata[26]\ : DFN1E0 - port map(D => hwdata(26), CLK => lclk_c, E => N_12_0_1, Q - => pwdata(26)); - - \r.prdata_RNO_0[16]\ : NOR3C - port map(A => \prdata_1_0_0_1[16]\, B => N_717, C => - \prdata_1_0_0_2[16]\, Y => \prdata_1_0_0_4[16]\); - - \r.prdata_RNO_12[4]\ : OA1 - port map(A => \prdata_RNO_16[4]\, B => readdata55_3, C => - ipend_m(4), Y => \prdata_1_i_0_a11_5_1[4]\); - - \r.prdata_RNO[21]\ : NOR3C - port map(A => \prdata_1_i_0_6[21]\, B => - \prdata_1_i_0_5[21]\, C => \prdata_RNO_2[21]\, Y => - N_41_i_0); - - \r.prdata_RNO_5[14]\ : NOR3C - port map(A => N_204, B => \prdata_1_0_0_0_1[14]\, C => - \prdata_1_0_0_0_3[14]\, Y => \prdata_1_0_0_0_5[14]\); - - \r.haddr_RNIEHV22_0[11]\ : OR2A - port map(A => N_746, B => \paddr[11]\, Y => N_747); - - \r.haddr_RNI3SB72_0[11]\ : NOR2B - port map(A => \paddr[11]\, B => N_761, Y => N_771); - - \r.prdata_RNO_2[16]\ : OR3B - port map(A => N_127, B => un1_dcom0(18), C => N_763, Y => - N_717); - - \r.prdata_RNO_4[10]\ : OA1A - port map(A => N_751_0, B => prdata(10), C => - \prdata_RNO_9[10]\, Y => \prdata_1_i_0_4[10]\); - - \r.prdata[21]\ : DFN1 - port map(D => N_41_i_0, CLK => lclk_c, Q => hrdata(21)); - - \r.prdata_RNO_3[12]\ : OA1A - port map(A => reload_8, B => readdata_1_sqmuxa_1_0, C => - \prdata_1_i_0_a11_3_0[12]\, Y => - \prdata_1_i_0_a11_3_1[12]\); - - \r.prdata_RNO_1[3]\ : NOR3C - port map(A => N_726, B => \prdata_1_0_0_4[3]\, C => - \prdata_1_0_0_5[3]\, Y => \prdata_1_0_0_7[3]\); - - \r.prdata_RNO_7[10]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_10, C => N_756, Y - => \prdata_1_i_0_a11_6_0[10]\); - - \r.prdata_RNO[4]\ : NOR3C - port map(A => \prdata_1_i_0_6[4]\, B => N_619_i, C => - N_623_i, Y => N_61_i_0); - - \r.pwdata[7]\ : DFN1E0 - port map(D => hwdata(7), CLK => lclk_c, E => N_12, Q => - pwdata(7)); - - \r.prdata_RNO[22]\ : AO1B - port map(A => prdata_0_22, B => N_756, C => - \prdata_1_i_i_5[22]\, Y => N_30); - - \r.haddr_RNIFTM02[10]\ : NOR2A - port map(A => N_746, B => \N_78\, Y => N_761); - - \r.prdata_RNO_3[6]\ : NOR3C - port map(A => \prdata_1_i_0_a11_4_1[6]\, B => - \prdata_1_i_0_a11_4_0[6]\, C => \prdata_1_i_0_a11_4_2[6]\, - Y => \prdata_1_i_0_a11_4_4[6]\); - - \r.prdata_RNO_17[5]\ : AOI1B - port map(A => ilevel_1, B => prdata_0_sqmuxa, C => N_367, Y - => \prdata_1_i_0_a11_6_1[5]\); - - \r.haddr_RNIPNNE2_0[10]\ : OR3B - port map(A => \N_116\, B => \N_769\, C => \N_78\, Y => - psel_15); - - \r.prdata_RNO_4[9]\ : NOR3B - port map(A => \prdata_1_i_0_0[9]\, B => \prdata_RNO_11[9]\, - C => N_554_i, Y => \prdata_1_i_0_2[9]\); - - \r.prdata_RNO_16[4]\ : MX2C - port map(A => prdata_13_m_1_0(4), B => prdata_11_m_1_0(4), - S => \paddr[6]\, Y => \prdata_RNO_16[4]\); - - \r.prdata_RNO_3[1]\ : AOI1B - port map(A => prdata(1), B => N_751_0, C => N_633, Y => - \prdata_1_0_0_3[1]\); - - \r.prdata_RNO_0[4]\ : NOR3C - port map(A => \prdata_1_i_0_2[4]\, B => \prdata_1_i_0_1[4]\, - C => \prdata_1_i_0_5[4]\, Y => \prdata_1_i_0_6[4]\); - - \r.prdata_RNO_7[9]\ : OA1A - port map(A => dishlt, B => readdata57, C => value_m_5, Y - => \prdata_1_i_0_a11_1_2[9]\); - - \r.pwdata[20]\ : DFN1E0 - port map(D => hwdata(20), CLK => lclk_c, E => N_12_0_0, Q - => pwdata(20)); - - \r.pwdata[9]\ : DFN1E0 - port map(D => hwdata(9), CLK => lclk_c, E => N_12, Q => - pwdata(9)); - - \r.prdata_RNO_6[21]\ : OA1A - port map(A => N_84, B => N_789, C => \prdata_1_i_0_0[21]\, - Y => \prdata_1_i_0_1[21]\); - - \r.prdata_RNO_9[0]\ : NOR3C - port map(A => \prdata_1_i_0_0[0]\, B => \prdata_1_i_0_1[0]\, - C => N_139, Y => \prdata_1_i_0_2[0]\); - - \r.prdata_RNO_0[31]\ : AOI1B - port map(A => prdata_0_31, B => N_758, C => - \prdata_1_0_0_0_1[31]\, Y => \prdata_1_0_0_0_2[31]\); - - \r.prdata_RNO[20]\ : NOR3C - port map(A => \prdata_1_i_0_6[20]\, B => - \prdata_1_i_0_5[20]\, C => \prdata_RNO_2[20]\, Y => - N_39_i_0); - - \r.prdata_RNO_5[4]\ : NOR3C - port map(A => rdata_2_m(4), B => rdata_17_m_4, C => - \prdata_1_i_0_a11_7_0[4]\, Y => \prdata_1_i_0_a11_7_2[4]\); - - \r.pwdata[4]\ : DFN1E0 - port map(D => hwdata(4), CLK => lclk_c, E => N_12, Q => - pwdata(4)); - - \r.prdata_RNO_22[6]\ : NOR2B - port map(A => N_6439, B => N_6437, Y => - \prdata_1_i_0_a11_3_0[6]\); - - \r.pwdata[11]\ : DFN1E0 - port map(D => hwdata(11), CLK => lclk_c, E => N_12_0, Q => - pwdata(11)); - - \r.prdata_RNO_1[29]\ : OR2B - port map(A => prdata_2_29, B => N_751, Y => N_658); - - \r.prdata[12]\ : DFN1 - port map(D => N_110_i_0, CLK => lclk_c, Q => hrdata(12)); - - \r.pwdata_0[0]\ : DFN1E0 - port map(D => hwdata(0), CLK => lclk_c, E => N_12_0_0, Q - => \pwdata_0[0]\); - - \comb.v.prdata_1_i_0_a11_2_RNO[20]\ : AND2 - port map(A => reload_m_20, B => \prdata_1_i_0_a11_2_0[20]\, - Y => \prdata_1_i_0_a11_2_1[20]\); - - \r.prdata_RNO_2[8]\ : OR2A - port map(A => N_752_0, B => prdata_1_8, Y => - \prdata_RNO_2[8]\); - - \r.haddr_RNINPBD[18]\ : NOR2B - port map(A => \paddr[18]\, B => \paddr[19]\, Y => - penable_1_0_0_i_0_a11_0_3); - - \r.prdata_RNO_4[31]\ : OR2B - port map(A => prdata_2_31, B => N_752, Y => N_510); - - \r.prdata_RNO_1[23]\ : OR2B - port map(A => prdata_2_23, B => N_752, Y => N_699); - - \r.prdata_RNO_11[11]\ : NOR2B - port map(A => \prdata_RNO_13[11]\, B => \prdata_RNO_14[11]\, - Y => \prdata_1_i_0_0[11]\); - - \r.prdata_RNO_3[16]\ : AOI1B - port map(A => prdata(16), B => N_751, C => N_720, Y => - \prdata_1_0_0_2[16]\); - - \r.prdata_RNO_8[8]\ : AOI1B - port map(A => N_240_0, B => N_216, C => N_761, Y => - \prdata_1_i_0_a11_1_0[8]\); - - \r.prdata_RNO_3[9]\ : AOI1 - port map(A => \prdata_1_i_0_a11_4_2[9]\, B => N_762, C => - N_771, Y => \prdata_1_i_0_3[9]\); - - \r.prdata_RNO_2[3]\ : AO1B - port map(A => rdata_iv_2(3), B => break_m, C => N_756, Y - => N_731); - - \r.prdata_RNO_14[0]\ : AOI1B - port map(A => rdata_2(0), B => rdata_0_sqmuxa, C => - rdata_17_m_0_d0, Y => \prdata_1_i_0_a11_9_1[0]\); - - \r.haddr[15]\ : DFN1E1 - port map(D => haddr(15), CLK => lclk_c, E => - hready_0_sqmuxa, Q => \paddr[15]\); - - \r.prdata_RNO_13[4]\ : AOI1B - port map(A => ilevel_0, B => prdata_0_sqmuxa, C => - iforce_0_m(4), Y => \prdata_1_i_0_a11_5_0[4]\); - - \r.prdata_RNO_1[27]\ : OA1A - port map(A => N_752_0, B => prdata_0_27, C => - \prdata_1_i_0_1[27]\, Y => \prdata_1_i_0_2[27]\); - - \comb.v.prdata_1_i_0_a11[27]\ : OR2 - port map(A => N_782_i, B => prdata(27), Y => - \prdata_1_i_0_a11[27]\); - - \r.prdata_RNO_0[6]\ : AO1C - port map(A => readdata56, B => reload_0(6), C => - \prdata_1_i_0_a11_4_4[6]\, Y => N_600_i); - - \r.prdata_RNO_17[1]\ : OR3B - port map(A => N_766, B => N_791, C => N_760, Y => N_625); - - \r.prdata_RNO[18]\ : AO1B - port map(A => prdata(18), B => N_758, C => - \prdata_1_0_0_1[18]\, Y => \prdata_1[18]\); - - \r.haddr_RNIQ2LQ[12]\ : NOR3C - port map(A => \paddr[13]\, B => \paddr[12]\, C => - penable_1_0_0_i_0_a11_0_1, Y => penable_1_0_0_i_0_a11_0_4); - - \r.prdata_RNO_5[11]\ : OR3C - port map(A => \prdata_1_i_0_a11_5_1[11]\, B => - \prdata_1_i_0_a11_5_0[11]\, C => N_762, Y => N_559_i); - - \r.prdata_RNO_18[6]\ : AOI1B - port map(A => ilevel_2, B => prdata_0_sqmuxa, C => N_363, Y - => \prdata_1_i_0_a11_6_1[6]\); - - \r.haddr[14]\ : DFN1E1 - port map(D => haddr(14), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[14]\); - - \r.pwdata_0_RNIUMA[3]\ : INV - port map(A => \pwdata_0[3]\, Y => pwdata_i(3)); - - \r.haddr[6]\ : DFN1E1 - port map(D => haddr(6), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[6]\); - - \r.prdata_RNO_8[14]\ : AOI1B - port map(A => prdata_0_14, B => N_751_0, C => N_499, Y => - \prdata_1_0_0_0_3[14]\); - - \r.prdata_RNO_0[15]\ : NOR3C - port map(A => N_688, B => \prdata_1_0_0_2[15]\, C => - \prdata_1_0_0_4[15]\, Y => \prdata_1_0_0_6[15]\); - - \r.pwdata_0_RNI27B[7]\ : INV - port map(A => \pwdata_0[7]\, Y => pwdata_i(7)); - - \r.prdata_RNO_2[15]\ : AO1B - port map(A => readdata_1_iv_0_2, B => value_m_11, C => - N_758, Y => N_690); - - \r.haddr_RNILAC4_0[8]\ : OR2A - port map(A => \paddr[8]\, B => \paddr[9]\, Y => \N_750\); - - \r.prdata_RNO_3[8]\ : OR2A - port map(A => N_751, B => prdata_0_8, Y => - \prdata_RNO_3[8]\); - - \r.prdata_RNO[15]\ : OR3C - port map(A => \prdata_1_0_0_6[15]\, B => - \prdata_1_0_0_5[15]\, C => N_690, Y => \prdata_1[15]\); - - \r.prdata_RNO_11[8]\ : OR3A - port map(A => N_772, B => N_743, C => prdata(8), Y => - \prdata_RNO_11[8]\); - - \r.haddr_RNIQIAS1_0[10]\ : NOR2 - port map(A => \paddr[10]\, B => N_743, Y => N_746); - - \r.haddr_RNI46CL1[12]\ : NOR3C - port map(A => penable_1_0_0_i_0_a11_0_3, B => - penable_1_0_0_i_0_a11_0_2, C => penable_1_0_0_i_0_a11_0_4, - Y => cfgsel2); - - \r.pwdata_0_RNI0VA[5]\ : INV - port map(A => \pwdata_0[5]\, Y => pwdata_i(5)); - - \r.prdata_RNO_10[2]\ : OR3B - port map(A => N_6427, B => N_767, C => \paddr_0[3]\, Y => - N_732); - - \comb.v.prdata_1_i_0_a11_1[28]\ : NAND2 - port map(A => value_m_24, B => \prdata_1_i_0_a11_1_1[28]\, - Y => N_675); - - \r.hready_RNO\ : OR2A - port map(A => rstn, B => N_5860, Y => N_198); - - \comb.v.prdata_1_i_0_a11_6_RNO[8]\ : AND2 - port map(A => rhalffull_1_m, B => \prdata_1_i_0_a11_6_0[8]\, - Y => \prdata_1_i_0_a11_6_1[8]\); - - \comb.v.prdata_1_i_0_a11[20]\ : OR2 - port map(A => N_782_i, B => prdata(20), Y => - \prdata_1_i_0_a11[20]\); - - \r.prdata_RNO_0[24]\ : AOI1B - port map(A => prdata(24), B => N_751, C => N_525, Y => - \prdata_1_0_0_2[24]\); - - \r.state[0]\ : DFN1 - port map(D => \state_nss[0]\, CLK => lclk_c, Q => - \state[0]\); - - \r.pwdata_1[3]\ : DFN1E0 - port map(D => hwdata(3), CLK => lclk_c, E => N_12_0_1, Q - => pwdata_1_2); - - \r.prdata_RNO_5[5]\ : NOR2B - port map(A => N_756, B => brate_m_1, Y => - \prdata_1_i_0_a11_8_0[5]\); - - \r.prdata_RNO_6[8]\ : NOR3B - port map(A => \prdata_RNO_10[8]\, B => \prdata_RNO_11[8]\, - C => N_554_i, Y => \prdata_1_i_0_1[8]\); - - \r.prdata_RNO_2[1]\ : AO1B - port map(A => rdata_iv_0_2(1), B => N_227, C => N_756, Y - => N_634); - - \r.prdata_RNO_7[8]\ : AOI1 - port map(A => \prdata_1_i_0_a11_4_2[8]\, B => N_762, C => - N_771, Y => \prdata_1_i_0_3[8]\); - - \r.haddr_1[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => paddr_1(2)); - - \r.prdata_RNO_2[7]\ : OAI1 - port map(A => N_156, B => tcnt_i, C => - \prdata_1_i_0_a11_7_3[7]\, Y => N_594_i); - - \r.prdata_RNO_2[22]\ : NOR3C - port map(A => N_527, B => \prdata_1_i_i_0[22]\, C => N_529, - Y => \prdata_1_i_i_2[22]\); - - \r.prdata_RNO_1[12]\ : NOR3B - port map(A => N_550_i, B => \prdata_1_i_0_3[12]\, C => - N_771, Y => \prdata_1_i_0_6[12]\); - - \r.prdata[9]\ : DFN1 - port map(D => N_104_i_0, CLK => lclk_c, Q => hrdata(9)); - - \r.prdata_RNO_8[0]\ : NOR3C - port map(A => \prdata_1_i_0_a11_9_1[0]\, B => - \prdata_1_i_0_a11_9_0[0]\, C => rcnt_RNI8FBM3(1), Y => - \prdata_1_i_0_a11_9_3[0]\); - - \r.haddr_RNI3SB72_2[8]\ : NOR2 - port map(A => \N_750\, B => N_745, Y => N_752_0); - - \r.prdata_RNO_1[5]\ : AOI1B - port map(A => \prdata_1_i_0_a11_4_4[5]\, B => reload_m_5, C - => \prdata_1_i_0_7[5]\, Y => \prdata_1_i_0_8[5]\); - - \comb.v.prdata_1_i_0_RNO[28]\ : AND2 - port map(A => \prdata_1_i_0_3[28]\, B => - \prdata_1_i_0_2[28]\, Y => \prdata_1_i_0_4[28]\); - - \r.prdata_RNO_15[4]\ : OR2A - port map(A => N_752_0, B => prdata_1_4, Y => - \prdata_RNO_15[4]\); - - \r.prdata_RNO_10[5]\ : AOI1B - port map(A => \prdata_1_i_0_a11_3_1[5]\, B => N_771, C => - \prdata_1_i_0_4[5]\, Y => \prdata_1_i_0_6[5]\); - - \r.cfgsel_RNIO6OB2\ : OA1B - port map(A => N_82, B => N_748, C => cfgsel, Y => N_767); - - \r.prdata_RNO_7[22]\ : OR2B - port map(A => prdata_1_22, B => N_755, Y => N_529); - - \r.prdata_RNO_3[20]\ : OR2A - port map(A => N_751, B => prdata_1_20, Y => - \prdata_RNO_3[20]\); - - \r.prdata_RNO_3[15]\ : OR2B - port map(A => prdata_2_15, B => N_755, Y => N_688); - - \r.prdata_RNO_13[10]\ : AO1 - port map(A => un1_dcom0(12), B => N_127, C => N_763, Y => - \prdata_RNO_13[10]\); - - \r.prdata_RNO_6[3]\ : OR2B - port map(A => rdata59_4, B => dout_2, Y => \dout_m[3]\); - - \r.prdata_RNO_9[1]\ : OR2B - port map(A => prdata_2_1, B => N_752, Y => N_633); - - \r.haddr_RNIFPAD_0[14]\ : NOR2 - port map(A => \paddr[14]\, B => \paddr[15]\, Y => - \prdata_1_i_0_o2_1_1[0]\); - - \r.pwdata[1]\ : DFN1E0 - port map(D => hwdata(1), CLK => lclk_c, E => N_12_0, Q => - pwdata(1)); - - \r.pwdata[24]\ : DFN1E0 - port map(D => hwdata(24), CLK => lclk_c, E => N_12_0_1, Q - => pwdata(24)); - - \v.hready_0_sqmuxa_0_a3_0_a2_0_0\ : NOR2A - port map(A => hready_0_sqmuxa_0_a3_0_a2_0, B => - un51_ioen_NE, Y => hready_0_sqmuxa_0); - - \r.prdata_RNO_4[20]\ : NOR3C - port map(A => \prdata_1_i_0_a11[20]\, B => - \prdata_1_i_0_1[20]\, C => \prdata_RNO_6[20]\, Y => - \prdata_1_i_0_3[20]\); - - \r.prdata_RNO_13[12]\ : AO1 - port map(A => un1_dcom0(14), B => N_127, C => N_763, Y => - \prdata_RNO_13[12]\); - - \r.prdata_RNO_8[11]\ : OR2A - port map(A => N_752_0, B => prdata_1_11, Y => - \prdata_RNO_8[11]\); - - \r.prdata_RNO_2[2]\ : AO1B - port map(A => rdata_iv_2(2), B => thempty_1_m, C => N_756, - Y => N_740); - - \r.cfgsel_RNIGRO9\ : OR2B - port map(A => N_794, B => N_774, Y => N_526); - - \r.prdata_RNO_24[6]\ : AOI1B - port map(A => rdata_17_m_0(6), B => rdata_4_sqmuxa, C => - rdata_2_m(6), Y => \prdata_1_i_0_a11_8_1[6]\); - - \r.prdata_RNO_2[26]\ : OR2A - port map(A => \prdata_1_0_0_a11_5_0[26]\, B => N_156, Y => - N_520); - - \r.prdata_RNO_1[16]\ : NOR3C - port map(A => N_715, B => N_714, C => N_716, Y => - \prdata_1_0_0_1[16]\); - - \r.prdata_RNO_0[1]\ : NOR3C - port map(A => \prdata_1_0_0_3[1]\, B => \prdata_1_0_0_2[1]\, - C => N_630_i, Y => \prdata_1_0_0_7[1]\); - - \r.prdata_RNO_16[5]\ : OA1A - port map(A => N_751_0, B => prdata(5), C => - \prdata_RNO_21[5]\, Y => \prdata_1_i_0_4[5]\); - - \r.haddr_RNILAC4_2[8]\ : OR2 - port map(A => \paddr[9]\, B => \paddr[8]\, Y => N_788); - - \r.prdata_RNO_13[8]\ : AOI1B - port map(A => ilevel_4, B => prdata_0_sqmuxa, C => N_470, Y - => \prdata_1_i_0_a11_4_1[8]\); - - \r.prdata_RNO_7[26]\ : NOR2A - port map(A => brdyen, B => N_232_0, Y => - \prdata_1_0_0_a11_0[26]\); - - \r.prdata_RNO_2[31]\ : OR2B - port map(A => prdata_3_29, B => N_751, Y => N_509); - - \r.prdata_RNO[24]\ : OR3C - port map(A => \prdata_1_0_0_2[24]\, B => - \prdata_1_0_0_1[24]\, C => N_523, Y => \prdata_1[24]\); - - \r.prdata_RNO_1[24]\ : NOR3B - port map(A => N_521, B => N_522, C => N_777, Y => - \prdata_1_0_0_1[24]\); - - \r.pwdata[5]\ : DFN1E0 - port map(D => hwdata(5), CLK => lclk_c, E => N_12, Q => - pwdata(5)); - - \r.haddr_RNIPNNE2[8]\ : OR3B - port map(A => \N_769\, B => \N_773\, C => N_788, Y => - psel_0); - - \r.prdata_RNO_3[30]\ : OR2B - port map(A => prdata_3_28, B => N_752, Y => N_663); - - \r.haddr_RNIPNNE2[10]\ : OR2B - port map(A => \psel_0_a3_0_a2_0_a11_0[11]\, B => \N_769\, Y - => psel_11); - - \r.prdata_RNO_21[0]\ : XA1B - port map(A => \paddr[10]\, B => \paddr[11]\, C => - \paddr[9]\, Y => \prdata_1_i_0_a11_1_0[0]\); - - \r.pwdata_0[3]\ : DFN1E0 - port map(D => hwdata(3), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[3]\); - - \r.prdata_RNO_0[21]\ : NOR3C - port map(A => \prdata_RNO_3[21]\, B => \prdata_1_i_0_3[21]\, - C => N_703, Y => \prdata_1_i_0_6[21]\); - - \r.prdata_RNO_3[5]\ : NOR3C - port map(A => \prdata_1_i_0_a11_4_1[5]\, B => scaler_m_5, C - => \prdata_1_i_0_a11_4_2[5]\, Y => - \prdata_1_i_0_a11_4_4[5]\); - - \r.haddr_RNIQKO8[5]\ : NOR2B - port map(A => un1_apbi_7_1, B => N_766, Y => N_794); - - \r.haddr_0[3]\ : DFN1E1 - port map(D => haddr(3), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr_0[3]\); - - \r.prdata[27]\ : DFN1 - port map(D => N_46_i_0, CLK => lclk_c, Q => hrdata(27)); - - \r.haddr_0_RNIN601[3]\ : OR2A - port map(A => cfgsel, B => \paddr_0[3]\, Y => N_789); - - \r.prdata_RNO_7[7]\ : NOR3C - port map(A => \prdata_1_i_0_a11_7_1[7]\, B => - \prdata_1_i_0_a11_7_0[7]\, C => N_220, Y => - \prdata_1_i_0_a11_7_3[7]\); - - \r.prdata_RNO_18[7]\ : AOI1B - port map(A => iforce_0_2, B => N_898, C => N_859, Y => - \prdata_1_i_0_a11_5_0[7]\); - - \r.prdata[18]\ : DFN1 - port map(D => \prdata_1[18]\, CLK => lclk_c, Q => - hrdata(18)); - - \r.prdata_RNO_17[7]\ : AOI1B - port map(A => ilevel_3, B => prdata_0_sqmuxa, C => N_861, Y - => \prdata_1_i_0_a11_5_1[7]\); - - \r.haddr_RNIRB63[3]\ : NOR2A - port map(A => \paddr[3]\, B => N_760, Y => N_776); - - \r.prdata_RNO_4[5]\ : NOR3C - port map(A => \prdata_1_i_0_3[5]\, B => \prdata_1_i_0_2[5]\, - C => \prdata_1_i_0_6[5]\, Y => \prdata_1_i_0_7[5]\); - - \r.haddr_RNIFAC4[5]\ : XOR2 - port map(A => \paddr[5]\, B => \paddr[6]\, Y => N_84); - - \r.haddr[13]\ : DFN1E1 - port map(D => haddr(13), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[13]\); - - \r.prdata_RNO_4[6]\ : OA1A - port map(A => N_755, B => prdata_0_6, C => N_602_i, Y => - \prdata_1_i_0_3[6]\); - - \r.pwdata_0[13]\ : DFN1E0 - port map(D => hwdata(13), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(13)); - - \r.prdata_RNO_0[5]\ : AOI1B - port map(A => paren, B => prdata(31), C => - \prdata_1_i_0_a11_8_2[5]\, Y => \prdata_1_i_0_a11_8_3[5]\); - - \r.prdata_RNO_14[10]\ : OR3A - port map(A => N_772, B => N_743, C => prdata_0_10, Y => - \prdata_RNO_14[10]\); - - \r.pwdata[17]\ : DFN1E0 - port map(D => hwdata(17), CLK => lclk_c, E => N_12_0, Q => - pwdata(17)); - - \r.prdata_RNO_5[23]\ : AOI1B - port map(A => \paddr[6]\, B => N_781, C => N_526, Y => - \prdata_1_i_i_0[23]\); - - \r.prdata_RNO_14[12]\ : OR3A - port map(A => N_772, B => N_743, C => prdata_0_12, Y => - \prdata_RNO_14[12]\); - - \r.prdata_RNO_9[10]\ : OR2A - port map(A => N_752_0, B => prdata_1_10, Y => - \prdata_RNO_9[10]\); - - \r.prdata_RNO_12[2]\ : MX2 - port map(A => romrws(2), B => ramwws(0), S => \paddr[2]\, Y - => N_6427); - - \r.prdata_RNO_5[27]\ : OR2A - port map(A => N_751, B => prdata_2_27, Y => - \prdata_RNO_5[27]\); - - \r.haddr_RNIS3MH[10]\ : XO1A - port map(A => \paddr[10]\, B => \paddr[11]\, C => \N_78\, Y - => \prdata_1_i_0_a2_0[21]\); - - \r.prdata_RNO_13[3]\ : OR2B - port map(A => prdata_3_1, B => N_752, Y => N_730); - - \r.prdata_RNO_16[9]\ : MX2 - port map(A => romwidth(1), B => rambanksz_0, S => - \paddr_2[2]\, Y => N_5069); - - \r.prdata_RNO_0[19]\ : NOR3C - port map(A => N_655, B => N_654, C => \prdata_1_0_0_0[19]\, - Y => \prdata_1_0_0_2[19]\); - - \r.prdata_RNO_10[8]\ : AO1A - port map(A => N_232_0, B => romwidth(0), C => N_778_i, Y - => \prdata_RNO_10[8]\); - - \r.prdata_RNO_8[2]\ : NOR2B - port map(A => N_722, B => N_732, Y => \prdata_1_0_0_0[2]\); - - \r.prdata[30]\ : DFN1 - port map(D => \prdata_1[30]\, CLK => lclk_c, Q => - hrdata(30)); - - \r.prdata[23]\ : DFN1 - port map(D => N_60, CLK => lclk_c, Q => hrdata(23)); - - \r.prdata_RNO_2[25]\ : OR3B - port map(A => bexcen, B => N_767, C => N_232_0, Y => N_668); - - \r.prdata_RNO_1[15]\ : AOI1B - port map(A => prdata(15), B => N_762, C => N_689, Y => - \prdata_1_0_0_5[15]\); - - \r.prdata_RNO_2[19]\ : OR2B - port map(A => prdata_2_19, B => N_751, Y => N_654); - - \r.prdata_RNO_0[7]\ : NOR3C - port map(A => \prdata_1_i_0_2[7]\, B => \prdata_1_i_0_1[7]\, - C => \prdata_1_i_0_5[7]\, Y => \prdata_1_i_0_6[7]\); - - \comb.v.prdata_1_i_0_a11_3_RNO_0[4]\ : AOI1B - port map(A => scaler(4), B => readdata55, C => - \prdata_1_i_0_a11_3_1[4]\, Y => \prdata_1_i_0_a11_3_3[4]\); - - \r.prdata_RNO_1[21]\ : OA1A - port map(A => N_752_0, B => prdata_0_21, C => N_101, Y => - \prdata_1_i_0_5[21]\); - - \r.prdata_RNO_0[13]\ : AO1B - port map(A => readdata_1_iv_0_0, B => value_m_9, C => N_758, - Y => N_538); - - \r.pwdata[2]\ : DFN1E0 - port map(D => hwdata(2), CLK => lclk_c, E => N_12, Q => - pwdata(2)); - - \r.prdata_RNO_0[3]\ : AO1B - port map(A => readdata_iv_3(3), B => reload_m_3, C => N_758, - Y => N_727); - - \r.prdata_RNO_10[10]\ : AOI1B - port map(A => ilevel_6, B => prdata_0_sqmuxa, C => N_478, Y - => \prdata_1_i_0_a11_4_1[10]\); - - \r.prdata_RNO_15[0]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_0, C => N_756, Y - => \prdata_1_i_0_a11_9_0[0]\); - - \r.prdata_RNO_2[13]\ : OR3C - port map(A => N_756, B => delayirqen, C => prdata(31), Y - => N_542); - - \r.prdata_RNO_19[0]\ : OR2 - port map(A => \paddr[6]\, B => N_760, Y => N_638); - - \r.cfgsel_RNIO6OB2_0\ : AO1D - port map(A => \prdata_1_i_0_o2_1_0[12]\, B => N_82, C => - cfgsel, Y => N_778_i); - - \r.prdata_RNO_0[17]\ : NOR3C - port map(A => N_649, B => N_646, C => \prdata_1_0_0_1[17]\, - Y => \prdata_1_0_0_2[17]\); - - \comb.v.prdata_1_i_0_a11[28]\ : OR2 - port map(A => N_782_i, B => prdata(28), Y => - \prdata_1_i_0_a11[28]\); - - \r.haddr_RNIS3MH_2[10]\ : NOR2A - port map(A => N_772, B => \paddr[10]\, Y => - \psel_0_a3_0_a2_0_a11_0[11]\); - - \r.prdata_RNO_10[12]\ : AOI1B - port map(A => iforce_0_7, B => N_898, C => N_863, Y => - \prdata_1_i_0_a11_6_0[12]\); - - \r.prdata_RNO_2[17]\ : OR2B - port map(A => prdata_2_17, B => N_755, Y => N_646); - - \r.prdata_RNO_7[2]\ : OR2B - port map(A => prdata_3_0, B => N_755, Y => N_733); - - \r.pwdata[25]\ : DFN1E0 - port map(D => hwdata(25), CLK => lclk_c, E => N_12_0_1, Q - => pwdata(25)); - - \r.prdata_RNO_6[12]\ : NOR3C - port map(A => \prdata_1_i_0_1[12]\, B => - \prdata_RNO_12[12]\, C => \prdata_RNO_13[12]\, Y => - \prdata_1_i_0_3[12]\); - - \r.pwdata_0[4]\ : DFN1E0 - port map(D => hwdata(4), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[4]\); - - \r.cfgsel_RNII71L\ : NOR2 - port map(A => N_776, B => N_544, Y => N_139); - - \comb.v.prdata_1_0_0_a11_0_0[26]\ : NOR2 - port map(A => un1_apbi_7_1, B => N_770, Y => \un1_apbi_7_3\); - - \r.haddr_RNI7P9D[10]\ : NOR2B - port map(A => \paddr[11]\, B => \paddr[10]\, Y => \N_116\); - - \r.prdata_RNO[9]\ : NOR3C - port map(A => \prdata_1_i_0_6[9]\, B => N_572_i, C => - N_577_i, Y => N_104_i_0); - - \r.prdata[11]\ : DFN1 - port map(D => N_108_i_0, CLK => lclk_c, Q => hrdata(11)); - - \r.prdata_RNO[13]\ : OR3C - port map(A => N_538, B => \prdata_1_0_0_6[13]\, C => N_542, - Y => \prdata_1[13]\); - - \r.pwdata[13]\ : DFN1E0 - port map(D => hwdata(13), CLK => lclk_c, E => N_12_0, Q => - pwdata(13)); - - \r.prdata_RNO_6[2]\ : OR3B - port map(A => N_330, B => rdata60_1, C => N_763, Y => N_734); - - \comb.v.prdata_1_i_0[28]\ : AND2 - port map(A => N_678, B => \prdata_1_i_0_4[28]\, Y => - N_50_i_0); - - \r.prdata_RNO_9[21]\ : OA1A - port map(A => cfgsel, B => \paddr_0[4]\, C => N_760, Y => - \prdata_1_i_0_0[21]\); - - \r.prdata_RNO_5[1]\ : OR3C - port map(A => readdata_9_i_m(1), B => reload_RNI6SNI(1), C - => \prdata_1_0_0_a11_5_3[1]\, Y => N_630_i); - - \r.prdata_RNO_11[5]\ : OR3C - port map(A => \prdata_1_i_0_a11_6_1[5]\, B => - \prdata_1_i_0_a11_6_0[5]\, C => N_762, Y => N_612_i); - - \r.prdata[5]\ : DFN1 - port map(D => N_63_i_0, CLK => lclk_c, Q => hrdata(5)); - - \r.prdata_RNO_21[7]\ : OR2A - port map(A => un1_grgpio0_2, B => readdata55_3, Y => - \un1_grgpio0_m[71]\); - - \r.prdata_RNO_3[19]\ : AOI1B - port map(A => prdata(19), B => N_755, C => N_651, Y => - \prdata_1_0_0_0[19]\); - - \r.prdata_RNO_6[5]\ : NOR3C - port map(A => readdata_9_5, B => chain_m, C => N_758, Y => - \prdata_1_i_0_a11_4_1[5]\); - - \r.pwdata[31]\ : DFN1E0 - port map(D => hwdata(31), CLK => lclk_c, E => N_12, Q => - pwdata(31)); - - \r.prdata_RNO_3[13]\ : OR3B - port map(A => N_127, B => un1_dcom0(15), C => N_763, Y => - N_537); - - \r.prdata_RNO_1[2]\ : NOR3C - port map(A => N_735, B => \prdata_1_0_0_3[2]\, C => - \prdata_1_0_0_4[2]\, Y => \prdata_1_0_0_6[2]\); - - \r.prdata_RNO_6[20]\ : OR3A - port map(A => N_744, B => \N_78\, C => prdata_2_20, Y => - \prdata_RNO_6[20]\); - - \r.prdata_RNO_11[15]\ : OR3C - port map(A => N_766, B => \paddr_0[4]\, C => N_774, Y => - N_685); - - \r.pwdata_0_RNISEA[1]\ : INV - port map(A => \pwdata_0[1]\, Y => pwdata_i(1)); - - \r.prdata_RNO_0[30]\ : NOR3C - port map(A => N_662, B => N_660, C => N_663, Y => - \prdata_1_0_0_1[30]\); - - \r.prdata_RNO_10[7]\ : AO1 - port map(A => rdata60_1, B => N_334, C => N_763, Y => - \prdata_RNO_10[7]\); - - \r.prdata_RNO_4[12]\ : OA1A - port map(A => N_751_0, B => prdata(12), C => - \prdata_RNO_8[12]\, Y => \prdata_1_i_0_5[12]\); - - \r.prdata_RNO_6[16]\ : OR2B - port map(A => prdata_2_16, B => N_755, Y => N_716); - - \r.prdata_RNO_3[17]\ : AOI1B - port map(A => prdata(17), B => N_752_0, C => N_647, Y => - \prdata_1_0_0_1[17]\); - - \r.prdata_RNO_10[0]\ : OR2A - port map(A => N_755, B => prdata_2_0, Y => - \prdata_RNO_10[0]\); - - \r.haddr_RNIA3NQ[16]\ : NOR3A - port map(A => \prdata_1_i_0_o2_1_3[0]\, B => \paddr[17]\, C - => \paddr[16]\, Y => \prdata_1_i_0_o2_1_5[0]\); - - \r.prdata_RNO_7[12]\ : AOI1B - port map(A => N_240, B => N_220_0, C => N_761, Y => - \prdata_1_i_0_a11_3_0[12]\); - - \r.haddr_RNIEHV22[11]\ : OR2B - port map(A => \paddr[11]\, B => N_744, Y => N_745); - - \r.prdata[29]\ : DFN1 - port map(D => \prdata_1[29]\, CLK => lclk_c, Q => - hrdata(29)); - - \comb.v.prdata_1_i_0_a11_3_RNO_2[4]\ : NOR3C - port map(A => readdata_9_4, B => irqpen_m, C => N_758, Y - => \prdata_1_i_0_a11_3_1[4]\); - - \r.prdata_RNO_0[8]\ : NOR3C - port map(A => \prdata_RNO_2[8]\, B => \prdata_RNO_3[8]\, C - => N_580_i, Y => \prdata_1_i_0_6[8]\); - - \r.cfgsel_RNIM601\ : OR2A - port map(A => cfgsel, B => \paddr_0[2]\, Y => N_760); - - \r.prdata_RNO_13[5]\ : OA1C - port map(A => N_777, B => \paddr[6]\, C => N_544, Y => - \prdata_1_i_0_0[5]\); - - \r.pwdata_0[7]\ : DFN1E0 - port map(D => hwdata(7), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[7]\); - - \comb.v.prdata_1_i_0_a11_3_RNO_1[4]\ : OA1A - port map(A => reload_0_d0, B => readdata_1_sqmuxa_1_0, C - => value_m_0, Y => \prdata_1_i_0_a11_3_2[4]\); - - \r.prdata_RNO_10[14]\ : OR2B - port map(A => prdata_2_14, B => N_752, Y => N_499); - - \r.prdata_RNO[3]\ : OR3C - port map(A => N_727, B => \prdata_1_0_0_7[3]\, C => N_731, - Y => \prdata_1[3]\); - - \r.prdata_RNO[1]\ : OR3C - port map(A => \prdata_1_0_0_7[1]\, B => \prdata_1_0_0_6[1]\, - C => N_634, Y => \prdata_1[1]\); - - \r.prdata_RNO_12[5]\ : AO1C - port map(A => \paddr[3]\, B => N_133, C => N_767, Y => - \prdata_RNO_12[5]\); - - \r.prdata_RNO_5[10]\ : OR3C - port map(A => \prdata_1_i_0_a11_4_1[10]\, B => - \prdata_1_i_0_a11_4_0[10]\, C => N_762, Y => N_567_i); - - \r.prdata_RNO_4[4]\ : AOI1B - port map(A => \prdata_1_i_0_a11_2_1[4]\, B => N_771, C => - \prdata_1_i_0_3[4]\, Y => \prdata_1_i_0_5[4]\); - - \r.prdata_RNO_5[24]\ : OR2B - port map(A => prdata_0_24, B => N_755, Y => N_522); - - \r.pwdata[19]\ : DFN1E0 - port map(D => hwdata(19), CLK => lclk_c, E => N_12_0, Q => - pwdata(19)); - - \r.prdata_RNO_4[16]\ : OR2A - port map(A => N_777, B => \paddr[5]\, Y => N_715); - - \r.prdata_RNO[11]\ : NOR3C - port map(A => \prdata_1_i_0_6[11]\, B => - \prdata_1_i_0_5[11]\, C => N_561, Y => N_108_i_0); - - \r.prdata_RNO_7[16]\ : OR2B - port map(A => prdata_3_14, B => N_752, Y => N_720); - - \r.prdata_RNO_9[4]\ : NOR3C - port map(A => N_6434, B => N_6436, C => N_6435, Y => - \prdata_1_i_0_a11_2_1[4]\); - - \r.prdata_RNO[12]\ : NOR3C - port map(A => \prdata_1_i_0_7[12]\, B => - \prdata_1_i_0_6[12]\, C => \prdata_RNO_2[12]\, Y => - N_110_i_0); - - \r.cfgsel_RNIJD2A\ : MX2B - port map(A => \prdata_1_0_0_0_a2_0[14]\, B => N_774, S => - N_90, Y => N_138); - - \r.prdata_RNO_10[4]\ : OA1A - port map(A => N_751_0, B => prdata(4), C => - \prdata_RNO_15[4]\, Y => \prdata_1_i_0_3[4]\); - - \r.prdata_RNO_2[4]\ : OA1A - port map(A => N_755, B => prdata_0_4, C => N_621_i, Y => - \prdata_1_i_0_2[4]\); - - \r.hready\ : DFN1 - port map(D => N_198, CLK => lclk_c, Q => \hready\); - - \r.prdata_RNO_0[14]\ : NOR2B - port map(A => tsemptyirqen, B => N_756, Y => - \prdata_1_0_0_a11_7_0[14]\); - - \r.prdata[3]\ : DFN1 - port map(D => \prdata_1[3]\, CLK => lclk_c, Q => hrdata(3)); - - \r.prdata_RNO_3[7]\ : OA1A - port map(A => N_755, B => prdata_0_7, C => N_592_i, Y => - \prdata_1_i_0_2[7]\); - - \r.prdata_RNO_2[14]\ : NOR3C - port map(A => N_207, B => N_498, C => - \prdata_1_0_0_0_5[14]\, Y => \prdata_1_0_0_0_6[14]\); - - \r.prdata_RNO[29]\ : AO1B - port map(A => prdata(29), B => N_758, C => - \prdata_1_0_0_1[29]\, Y => \prdata_1[29]\); - - \r.prdata_RNO[10]\ : NOR3C - port map(A => \prdata_1_i_0_6[10]\, B => - \prdata_1_i_0_5[10]\, C => N_569, Y => N_106_i_0); - - \r.pwdata_0_RNITIA[2]\ : INV - port map(A => \pwdata_0[2]\, Y => pwdata_i(2)); - - \r.prdata_RNO_12[13]\ : NOR2A - port map(A => cfgsel, B => N_770, Y => - \prdata_1_0_0_a11_0[13]\); - - \r.prdata_RNO_8[21]\ : AOI1B - port map(A => N_240_0, B => N_229, C => N_761, Y => - \prdata_1_i_0_a11_2_0[21]\); - - \r.prdata_RNO_6[15]\ : OR3B - port map(A => N_127, B => un1_dcom0(17), C => N_763, Y => - N_689); - - \r.prdata_RNO_14[4]\ : MX2 - port map(A => romwws(0), B => ramwidth(0), S => - \paddr_2[2]\, Y => N_132); - - \r.haddr[4]\ : DFN1E1 - port map(D => haddr(4), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[4]\); - - \r.prdata_RNO[31]\ : AO1B - port map(A => prdata(31), B => N_756, C => - \prdata_1_0_0_0_2[31]\, Y => \prdata_1[31]\); - - \r.prdata_RNO_16[1]\ : NOR2 - port map(A => \paddr_0[4]\, B => N_770, Y => - \prdata_1_0_0_a11_1_0[1]\); - - \r.prdata_RNO_2[29]\ : OR2B - port map(A => prdata_0_29, B => N_755, Y => N_656); - - \r.prdata_RNO_1[19]\ : OR2B - port map(A => prdata_3_17, B => N_752, Y => N_655); - - \r.prdata_RNO[27]\ : NOR3C - port map(A => \prdata_1_i_0_3[27]\, B => - \prdata_1_i_0_2[27]\, C => \prdata_RNO_2[27]\, Y => - N_46_i_0); - - \r.haddr_2[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr_2[2]\); - - \r.prdata_RNO_0[9]\ : NOR3C - port map(A => \prdata_1_i_0_3[9]\, B => \prdata_1_i_0_2[9]\, - C => \prdata_1_i_0_4[9]\, Y => \prdata_1_i_0_6[9]\); - - \r.prdata_RNO_9[3]\ : NOR2B - port map(A => \prdata_1_0_0_0[3]\, B => N_721, Y => - \prdata_1_0_0_1[3]\); - - \r.psel_RNO\ : AOI1B - port map(A => psel_RNO_0, B => N_168, C => rstn, Y => N_34); - - \r.prdata[26]\ : DFN1 - port map(D => \prdata_1[26]\, CLK => lclk_c, Q => - hrdata(26)); - - \r.prdata_RNO_2[23]\ : OR2B - port map(A => prdata_1_23, B => N_751, Y => N_698); - - \r.prdata_RNO_1[13]\ : NOR3C - port map(A => N_537, B => N_540, C => \prdata_1_0_0_5[13]\, - Y => \prdata_1_0_0_6[13]\); - - \r.prdata_RNO_11[1]\ : AOI1B - port map(A => \prdata_1_0_0_a11_1_0[1]\, B => N_776, C => - N_625, Y => \prdata_1_0_0_0[1]\); - - \r.prdata_RNO_2[27]\ : AO1C - port map(A => N_156, B => rcnt(1), C => N_756, Y => - \prdata_RNO_2[27]\); - - \r.prdata_RNO_1[17]\ : OR2B - port map(A => prdata_3_15, B => N_751, Y => N_649); - - \r.prdata_RNO_8[10]\ : AOI1B - port map(A => N_240_0, B => N_218, C => N_761, Y => - \prdata_1_i_0_a11_1_0[10]\); - - \r.prdata_RNO_5[21]\ : OR3C - port map(A => reload_m_21, B => \prdata_1_i_0_a11_2_0[21]\, - C => value_m_17, Y => N_703); - - \r.pwdata_0[12]\ : DFN1E0 - port map(D => hwdata(12), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(12)); - - \r.prdata_RNO_3[14]\ : OR3B - port map(A => N_127, B => un1_dcom0(16), C => N_763, Y => - N_207); - - \r.prdata_RNO[30]\ : AO1B - port map(A => prdata(30), B => N_758, C => - \prdata_1_0_0_1[30]\, Y => \prdata_1[30]\); - - \comb.v.prdata_1_i_0_a11_4[28]\ : NAND2 - port map(A => N_756, B => prdata_0_28, Y => N_678); - - \r.pwdata[22]\ : DFN1E0 - port map(D => hwdata(22), CLK => lclk_c, E => N_12_0_0, Q - => pwdata(22)); - - \r.prdata_RNO_3[22]\ : AO1B - port map(A => readdata_1_iv_0_9, B => value_m_18, C => - N_758, Y => N_530); - - \r.prdata_RNO_4[15]\ : NOR3C - port map(A => \prdata_RNO_7[15]\, B => \prdata_1_0_0_0[15]\, - C => N_138, Y => \prdata_1_0_0_2[15]\); - - \r.prdata_RNO_15[1]\ : MX2 - port map(A => romrws(1), B => ramrws(1), S => \paddr[2]\, Y - => N_5063); - - \v.hready_0_sqmuxa_0_a3_0_a2\ : NOR2A - port map(A => hready_0_sqmuxa_0_a3_0_a2_0, B => - un51_ioen_NE, Y => hready_0_sqmuxa); - - \r.prdata[20]\ : DFN1 - port map(D => N_39_i_0, CLK => lclk_c, Q => hrdata(20)); - - \r.pwdata[16]\ : DFN1E0 - port map(D => hwdata(16), CLK => lclk_c, E => N_12_0, Q => - pwdata(16)); - - \r.haddr_RNILAC4_1[8]\ : OR2A - port map(A => \paddr[9]\, B => \paddr[8]\, Y => \N_749\); - - \r.prdata_RNO_7[15]\ : OR3A - port map(A => \paddr[6]\, B => \paddr[5]\, C => N_793, Y - => \prdata_RNO_7[15]\); - - \r.prdata_RNO[26]\ : OR3C - port map(A => N_517, B => \prdata_1_0_0_3[26]\, C => N_520, - Y => \prdata_1[26]\); - - \r.pwdata_0_RNIRAA[0]\ : INV - port map(A => \pwdata_0[0]\, Y => pwdata_i(0)); - - \r.prdata_RNO_1[6]\ : NOR3C - port map(A => \prdata_1_i_0_3[6]\, B => \prdata_1_i_0_2[6]\, - C => \prdata_1_i_0_6[6]\, Y => \prdata_1_i_0_7[6]\); - - \r.prdata_RNO_0[11]\ : AOI1B - port map(A => \prdata_1_i_0_a11_2_1[11]\, B => value_m_7, C - => \prdata_1_i_0_4[11]\, Y => \prdata_1_i_0_6[11]\); - - \r.prdata_RNO_14[9]\ : NOR2A - port map(A => N_5069, B => \paddr[3]\, Y => \prdata_0[9]\); - - \r.prdata[7]\ : DFN1 - port map(D => N_100_i_0, CLK => lclk_c, Q => hrdata(7)); - - \r.prdata_RNO_2[30]\ : OR2B - port map(A => prdata_0_30, B => N_755, Y => N_660); - - \r.prdata_RNO_2[11]\ : OR3C - port map(A => brate_m_7, B => N_756, C => debug_m, Y => - N_561); - - \r.prdata_RNO_19[6]\ : AOI1B - port map(A => iforce_0_1, B => N_898, C => N_361, Y => - \prdata_1_i_0_a11_6_0[6]\); - - \r.haddr_0_RNI0QIB[3]\ : OA1C - port map(A => N_5062, B => \paddr_0[3]\, C => cfgsel, Y => - N_790); - - \r.prdata_RNO_4[22]\ : OR2B - port map(A => prdata_2_22, B => N_752_0, Y => N_532); - - \comb.v.prdata_1_i_0_RNO_2[28]\ : NOR3C - port map(A => \prdata_1_i_0_RNO_3[28]\, B => - \prdata_1_i_0_a11[28]\, C => \prdata_1_i_0_RNO_4[28]\, Y - => \prdata_1_i_0_1[28]\); - - \r.cfgsel_RNI6HED\ : OR3C - port map(A => N_766, B => cfgsel, C => N_117, Y => N_202); - - \comb.v.prdata_1_i_0_RNO_3[28]\ : OR3A - port map(A => N_744, B => \N_78\, C => prdata_2_28, Y => - \prdata_1_i_0_RNO_3[28]\); - - \r.prdata_RNO[7]\ : NOR3C - port map(A => \prdata_1_i_0_6[7]\, B => N_590_i, C => - N_594_i, Y => N_100_i_0); - - \r.prdata_RNO_0[20]\ : NOR3C - port map(A => \prdata_RNO_3[20]\, B => \prdata_1_i_0_3[20]\, - C => N_710, Y => \prdata_1_i_0_6[20]\); - - \r.prdata[17]\ : DFN1 - port map(D => \prdata_1[17]\, CLK => lclk_c, Q => - hrdata(17)); - - \r.haddr_RNI3SB72_1[8]\ : NOR2 - port map(A => \N_750\, B => N_745, Y => N_752); - - \r.haddr_0[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr_0[2]\); - - \r.penable_RNO_0\ : OA1C - port map(A => \state[0]\, B => \pwrite\, C => N_131, Y => - N_199); - - \r.haddr_RNIKKO8[3]\ : OR2A - port map(A => un1_apbi_2, B => N_791, Y => N_117); - - \r.prdata_RNO_6[0]\ : OA1A - port map(A => value_0, B => value_0_sqmuxa_0, C => - scaler_m_0, Y => \prdata_1_i_0_a11_3_4[0]\); - - \r.prdata_RNO_11[13]\ : OR2B - port map(A => prdata_2_13, B => N_752_0, Y => N_541); - - \r.prdata_RNO_15[6]\ : AOI1B - port map(A => rdata59_4, B => dout_5, C => - \prdata_1_i_0_a11_3_0[6]\, Y => \prdata_1_i_0_a11_3_1[6]\); - - \r.haddr_RNI7P9D_0[10]\ : NOR2A - port map(A => \paddr[10]\, B => \paddr[11]\, Y => psel_1(7)); - - \r.pwdata[10]\ : DFN1E0 - port map(D => hwdata(10), CLK => lclk_c, E => N_12_0, Q => - pwdata(10)); - - \r.prdata_RNO_4[7]\ : NOR3B - port map(A => \prdata_RNO_9[7]\, B => \prdata_RNO_10[7]\, C - => N_554_i, Y => \prdata_1_i_0_1[7]\); - - \r.cfgsel\ : DFN1 - port map(D => cfgsel2, CLK => lclk_c, Q => cfgsel); - - \r.prdata_RNO_3[26]\ : OR2B - port map(A => prdata_0_26, B => N_755, Y => N_516); - - \r.haddr_RNI3SB72_4[11]\ : NOR2 - port map(A => N_745, B => \N_78\, Y => N_755); - - \r.prdata_RNO_8[5]\ : OA1A - port map(A => N_755, B => prdata_0_5, C => N_612_i, Y => - \prdata_1_i_0_3[5]\); - - \r.prdata_RNO_19[5]\ : MX2 - port map(A => romwws(1), B => ramwidth(1), S => \paddr[2]\, - Y => N_133); - - \r.haddr_RNI3SB72[11]\ : OR3A - port map(A => N_744, B => \N_78\, C => \paddr[11]\, Y => - N_763); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.prdata_RNO_9[2]\ : AOI1B - port map(A => prdata_0_2, B => N_751_0, C => N_739, Y => - \prdata_1_0_0_2[2]\); - - \r.prdata_RNO_20[5]\ : NOR2B - port map(A => readdata_2_m(5), B => \un1_grgpio0_m[69]\, Y - => \prdata_1_i_0_a11_3_0[5]\); - - \r.prdata_RNO_4[26]\ : AOI1B - port map(A => \prdata_1_0_0_a11_0[26]\, B => N_767, C => - N_515, Y => \prdata_1_0_0_0[26]\); - - \apbi.psel_0_a3_1_a2_2_a2[15]\ : NAND2 - port map(A => \N_116\, B => \N_769\, Y => N_796); - - \r.prdata_RNO_3[11]\ : OA1A - port map(A => reload_7, B => readdata_1_sqmuxa_1_0, C => - \prdata_1_i_0_a11_2_0[11]\, Y => - \prdata_1_i_0_a11_2_1[11]\); - - \r.prdata_RNO_13[11]\ : OR3A - port map(A => N_772, B => N_743, C => prdata_0_11, Y => - \prdata_RNO_13[11]\); - - \r.prdata_RNO_4[1]\ : NOR3C - port map(A => N_624, B => \prdata_1_0_0_0[1]\, C => N_627, - Y => \prdata_1_0_0_2[1]\); - - \r.prdata[13]\ : DFN1 - port map(D => \prdata_1[13]\, CLK => lclk_c, Q => - hrdata(13)); - - \r.haddr_RNIS3MH_0[10]\ : XA1 - port map(A => \paddr[10]\, B => \paddr[11]\, C => \N_78\, Y - => N_748); - - \r.prdata_RNO_8[1]\ : AO1B - port map(A => prdata_iv_0_0_d0, B => \dout_m[1]\, C => - N_771, Y => N_629); - - \r.prdata_RNO_8[4]\ : AO1 - port map(A => rdata60_1, B => N_332, C => N_763, Y => - \prdata_RNO_8[4]\); - - \r.haddr_RNIQ2LQ_0[12]\ : NOR3A - port map(A => \prdata_1_i_0_o2_1_1[0]\, B => \paddr[13]\, C - => \paddr[12]\, Y => \prdata_1_i_0_o2_1_4[0]\); - - \r.prdata_RNO_1[20]\ : OA1A - port map(A => N_752_0, B => prdata_0_20, C => N_101, Y => - \prdata_1_i_0_5[20]\); - - \comb.v.prdata_1_i_0_a11[21]\ : OR2 - port map(A => N_782_i, B => prdata(21), Y => - \prdata_1_i_0_a11[21]\); - - \r.prdata_RNO_1[1]\ : NOR3C - port map(A => N_628, B => N_632, C => N_629, Y => - \prdata_1_0_0_6[1]\); - - \r.pwdata_0[10]\ : DFN1E0 - port map(D => hwdata(10), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_0(10)); - - \r.prdata_RNO[14]\ : AO1B - port map(A => \prdata_1_0_0_a11_7_0[14]\, B => prdata(31), - C => \prdata_1_0_0_0_7[14]\, Y => \prdata_1[14]\); - - \r.prdata_RNO_18[1]\ : NOR3C - port map(A => reload_RNIRDRG(1), B => restart_RNIIKBB, C - => value_RNIBAHH(1), Y => \prdata_1_0_0_a11_5_1[1]\); - - \r.prdata_RNO[0]\ : NOR3C - port map(A => \prdata_1_i_0_8[0]\, B => N_639_i, C => - N_645_i, Y => N_58_i_0); - - \r.prdata_RNO[2]\ : OR3C - port map(A => N_736, B => \prdata_1_0_0_6[2]\, C => N_740, - Y => \prdata_1[2]\); - - \r.prdata_RNO_19[7]\ : OA1 - port map(A => oen(7), B => rdata60_4_0, C => - \un1_grgpio0_m[71]\, Y => \prdata_1_i_0_a11_2_0[7]\); - - \r.prdata_RNO_9[12]\ : AOI1B - port map(A => ilevel_8, B => prdata_0_sqmuxa, C => N_865, Y - => \prdata_1_i_0_a11_6_1[12]\); - - \r.prdata_RNO_2[24]\ : AO1B - port map(A => readdata_1_iv_0_11, B => value_m_20, C => - N_758, Y => N_523); - - \r.prdata_RNO_1[14]\ : AOI1B - port map(A => prdata(14), B => N_758, C => - \prdata_1_0_0_0_6[14]\, Y => \prdata_1_0_0_0_7[14]\); - - \r.prdata_RNO_10[9]\ : OA1 - port map(A => N_778_i, B => \prdata_0[9]\, C => - \prdata_RNO_15[9]\, Y => \prdata_1_i_0_0[9]\); - - \comb.v.prdata_1_i_0_a11_6_RNO_0[8]\ : AOI1B - port map(A => rdata_3_sqmuxa, B => brate_8, C => N_756, Y - => \prdata_1_i_0_a11_6_0[8]\); - - \r.prdata_RNO_14[7]\ : OA1A - port map(A => reload_3, B => readdata_1_sqmuxa_1_0, C => - value_m_3, Y => \prdata_1_i_0_a11_3_1[7]\); - - \r.prdata_RNO_10[6]\ : OA1A - port map(A => value_6, B => value_0_sqmuxa_0, C => - scaler_m_6, Y => \prdata_1_i_0_a11_4_2[6]\); - - \r.haddr_RNINPBD_0[18]\ : NOR2 - port map(A => \paddr[18]\, B => \paddr[19]\, Y => - \prdata_1_i_0_o2_1_3[0]\); - - \r.prdata_RNO_13[6]\ : NOR2B - port map(A => N_595, B => N_139, Y => \prdata_1_i_0_0[6]\); - - \r.prdata[24]\ : DFN1 - port map(D => \prdata_1[24]\, CLK => lclk_c, Q => - hrdata(24)); - - \r.prdata_RNO_3[0]\ : NOR3B - port map(A => \prdata_1_i_0_2[0]\, B => \prdata_RNO_10[0]\, - C => N_762, Y => \prdata_1_i_0_4[0]\); - - \r.prdata_RNO_17[0]\ : OAI1 - port map(A => \prdata_1_i_0_a11_0[0]\, B => - \prdata_1_i_0_a11_1_0[0]\, C => N_790, Y => - \prdata_1_i_0_1[0]\); - - \r.prdata_RNO_6[13]\ : OR2B - port map(A => prdata_0_13, B => N_755, Y => N_536); - - \r.hready_RNO_0\ : AO1A - port map(A => hready_0_sqmuxa_0, B => \hready\, C => - \state[1]\, Y => N_5860); - - \r.haddr_RNI3SB72_2[11]\ : NOR2 - port map(A => N_747, B => \N_78\, Y => N_758); - - \r.prdata_RNO_3[25]\ : AOI1B - port map(A => prdata(25), B => N_751, C => N_672, Y => - \prdata_1_0_0_1[25]\); - - \comb.v.prdata_1_i_0_a11_6[8]\ : NAND2 - port map(A => extclken_m, B => \prdata_1_i_0_a11_6_1[8]\, Y - => N_585); - - \comb.v.prdata_1_i_0_RNO_4[28]\ : OR2A - port map(A => N_751, B => prdata_3_26, Y => - \prdata_1_i_0_RNO_4[28]\); - - \r.prdata_RNO_3[3]\ : AO1B - port map(A => prdata_iv_0_2, B => \dout_m[3]\, C => N_771, - Y => N_726); - - \r.haddr_RNI3SB72_3[11]\ : NOR2 - port map(A => \N_749\, B => N_747, Y => N_762); - - \r.haddr[7]\ : DFN1E1 - port map(D => haddr(7), CLK => lclk_c, E => hready_0_sqmuxa, - Q => paddr_5); - - \r.prdata_RNO_4[25]\ : OR2B - port map(A => prdata_3_23, B => N_752, Y => N_672); - - \r.state_RNI4KU3[0]\ : OR2B - port map(A => \pwrite\, B => \state[0]\, Y => N_12_0_1); - - \r.prdata_RNO_14[11]\ : AO1A - port map(A => \paddr_0[3]\, B => N_5070, C => N_778_i, Y - => \prdata_RNO_14[11]\); - - \r.prdata_RNO_7[4]\ : AO1C - port map(A => \paddr_0[3]\, B => N_132, C => N_767, Y => - \prdata_RNO_7[4]\); - - \r.pwdata[28]\ : DFN1E0 - port map(D => hwdata(28), CLK => lclk_c, E => N_12, Q => - pwdata(28)); - - \r.prdata[19]\ : DFN1 - port map(D => \prdata_1[19]\, CLK => lclk_c, Q => - hrdata(19)); - - \r.haddr_RNI6ONE4[10]\ : OA1B - port map(A => N_743, B => \prdata_1_i_0_a2_0[21]\, C => - N_762, Y => N_101); - - \r.haddr[5]\ : DFN1E1 - port map(D => haddr(5), CLK => lclk_c, E => hready_0_sqmuxa, - Q => \paddr[5]\); - - \r.prdata_RNO_17[6]\ : AND2 - port map(A => \prdata_1_i_0_a11_8_1[6]\, B => - \prdata_1_i_0_a11_8_0[6]\, Y => \prdata_1_i_0_a11_8_2[6]\); - - \r.pwdata[14]\ : DFN1E0 - port map(D => hwdata(14), CLK => lclk_c, E => N_12_0, Q => - pwdata(14)); - - \r.psel_RNO_0\ : OR2A - port map(A => hready_0_sqmuxa_0, B => hwrite, Y => - psel_RNO_0); - - \comb.v.prdata_1_i_0_a11_1_RNO[27]\ : AND2 - port map(A => reload_m_27, B => \prdata_1_i_0_a11_1_0[27]\, - Y => \prdata_1_i_0_a11_1_1[27]\); - - \r.prdata_RNO_0[18]\ : NOR3C - port map(A => N_666, B => N_664, C => N_667, Y => - \prdata_1_0_0_1[18]\); - - \r.prdata_RNO_4[19]\ : OR3B - port map(A => ioen, B => N_767, C => N_232_0, Y => N_651); - - \r.state_RNI4KU3_1[0]\ : OR2B - port map(A => \pwrite\, B => \state[0]\, Y => N_12); - - \r.prdata_RNO_2[18]\ : OR2B - port map(A => prdata_0_18, B => N_755, Y => N_664); - - \r.prdata_RNO_14[5]\ : OR2 - port map(A => prdata_2_5, B => N_763, Y => - \prdata_RNO_14[5]\); - - \r.prdata_RNO_5[0]\ : AOI1B - port map(A => \prdata_1_i_0_a11_6_1[0]\, B => N_771, C => - \prdata_1_i_0_5[0]\, Y => \prdata_1_i_0_7[0]\); - - \r.prdata_RNO_9[7]\ : AO1C - port map(A => N_232_0, B => romwws(3), C => N_767, Y => - \prdata_RNO_9[7]\); - - \r.prdata_RNO_12[7]\ : OA1A - port map(A => N_751_0, B => prdata(7), C => - \prdata_RNO_20[7]\, Y => \prdata_1_i_0_3[7]\); - - \r.prdata_RNO_4[13]\ : AO1B - port map(A => prdata_0_iv_0_0_1_12, B => - prdata_0_iv_0_0_0_12, C => N_762, Y => N_540); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.prdata_RNO_5[2]\ : NOR3C - port map(A => N_733, B => \prdata_1_0_0_0[2]\, C => - \prdata_1_0_0_2[2]\, Y => \prdata_1_0_0_4[2]\); - - \r.haddr_RNIJ9BD[16]\ : NOR2B - port map(A => \paddr[16]\, B => \paddr[17]\, Y => - penable_1_0_0_i_0_a11_0_2); - - \r.prdata_RNO_10[3]\ : AOI1B - port map(A => prdata_0_3, B => N_751_0, C => N_730, Y => - \prdata_1_0_0_3[3]\); - - \comb.v.prdata_1_i_0_o11_RNO[28]\ : AO1C - port map(A => \paddr_0[2]\, B => N_794, C => cfgsel, Y => - N_786); - - \r.prdata_RNO_6[22]\ : AOI1B - port map(A => \paddr[5]\, B => N_781, C => N_526, Y => - \prdata_1_i_i_0[22]\); - - \r.prdata_RNO_2[21]\ : AO1C - port map(A => N_156, B => tcnt(1), C => N_756, Y => - \prdata_RNO_2[21]\); - - \r.prdata_RNO_1[11]\ : NOR3B - port map(A => N_559_i, B => \prdata_1_i_0_2[11]\, C => - N_771, Y => \prdata_1_i_0_5[11]\); - - \r.prdata_RNO_7[13]\ : NOR3C - port map(A => \prdata_RNO_9[13]\, B => N_534, C => N_202, Y - => \prdata_1_0_0_1[13]\); - - \r.prdata_RNO_4[17]\ : OR3B - port map(A => N_127, B => un1_dcom0(19), C => N_763, Y => - N_647); - - \r.prdata_RNO_8[3]\ : OR2B - port map(A => prdata_2_3, B => N_755, Y => N_724); - - \r.haddr_RNIFAC4_0[5]\ : NOR2B - port map(A => \paddr[6]\, B => \paddr[5]\, Y => N_766); - - \r.prdata_RNO_10[11]\ : AOI1B - port map(A => ipend(11), B => prdata_1_sqmuxa, C => N_839, - Y => \prdata_1_i_0_a11_5_0[11]\); - - \r.haddr[11]\ : DFN1E1 - port map(D => haddr(11), CLK => lclk_c, E => - hready_0_sqmuxa_0, Q => \paddr[11]\); - - \r.prdata_RNO_11[6]\ : OR3C - port map(A => \prdata_1_i_0_a11_6_1[6]\, B => - \prdata_1_i_0_a11_6_0[6]\, C => N_762, Y => N_602_i); - - \r.prdata_RNO_15[5]\ : AOI1B - port map(A => rdata59_4, B => dout_4, C => - \prdata_1_i_0_a11_3_0[5]\, Y => \prdata_1_i_0_a11_3_1[5]\); - - \r.prdata_RNO_7[21]\ : OR3A - port map(A => N_744, B => \N_78\, C => prdata_1_21, Y => - \prdata_RNO_7[21]\); - - \comb.v.prdata_1_i_0_a11_2_RNO_0[20]\ : AOI1B - port map(A => N_240_0, B => N_228, C => N_761, Y => - \prdata_1_i_0_a11_2_0[20]\); - - \r.prdata_RNO_11[9]\ : AO1 - port map(A => rdata60_1, B => N_336, C => N_763, Y => - \prdata_RNO_11[9]\); - - \r.haddr_RNIK9HH[3]\ : OR2 - port map(A => \prdata_1_i_0_o2_0[11]\, B => N_794, Y => - N_176); - - \comb.v.prdata_1_i_0_a2_1[28]\ : OR2 - port map(A => N_111, B => cfgsel, Y => N_782_i); - - \r.prdata_RNO_7[1]\ : AO1B - port map(A => prdata_0_iv_0_0_1_0, B => prdata_0_iv_0_0_0_0, - C => N_762, Y => N_632); - - \r.haddr_RNI1HC5[3]\ : NOR2A - port map(A => N_90, B => N_760, Y => N_777); - - \r.prdata_RNO_3[18]\ : OR2B - port map(A => prdata_3_16, B => N_752, Y => N_667); - - \r.prdata_RNO_12[9]\ : OR2A - port map(A => N_752_0, B => prdata_2_9, Y => - \prdata_RNO_12[9]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.prdata_RNO_5[12]\ : OR3C - port map(A => \prdata_1_i_0_a11_6_1[12]\, B => - \prdata_1_i_0_a11_6_0[12]\, C => N_762, Y => N_550_i); - - \r.prdata_RNO_6[26]\ : NOR2B - port map(A => rcnt(0), B => N_756, Y => - \prdata_1_0_0_a11_5_0[26]\); - - \r.prdata_RNO_21[5]\ : OR2A - port map(A => N_752, B => prdata_1_5, Y => - \prdata_RNO_21[5]\); - - \r.haddr_RNIQKO8[3]\ : OR2A - port map(A => N_770, B => N_90, Y => - \prdata_1_i_0_o2_0[11]\); - - \r.pwdata_0[6]\ : DFN1E0 - port map(D => hwdata(6), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[6]\); - - \r.prdata_RNO_6[1]\ : OR3B - port map(A => N_85, B => N_86, C => N_763, Y => N_628); - - \r.prdata_RNO_2[6]\ : AO1C - port map(A => N_156, B => frame, C => - \prdata_1_i_0_a11_8_3[6]\, Y => N_604_i); - - \r.prdata_RNO_9[15]\ : OR2B - port map(A => prdata_3_13, B => N_752, Y => N_693); - - \r.prdata_RNO_6[4]\ : OR3C - port map(A => \prdata_1_i_0_a11_5_1[4]\, B => - \prdata_1_i_0_a11_5_0[4]\, C => N_762, Y => N_621_i); - - \r.prdata_RNO_15[7]\ : AOI1B - port map(A => rdata_iv_0_a2_3_0(7), B => rdata_4_sqmuxa, C - => N_223, Y => \prdata_1_i_0_a11_7_1[7]\); - - \r.pwdata[21]\ : DFN1E0 - port map(D => hwdata(21), CLK => lclk_c, E => N_12_0_0, Q - => pwdata(21)); - - \r.prdata_RNO[5]\ : AOI1B - port map(A => \prdata_1_i_0_a11_8_3[5]\, B => parerr_m, C - => \prdata_1_i_0_8[5]\, Y => N_63_i_0); - - \r.prdata[6]\ : DFN1 - port map(D => N_65_i_0, CLK => lclk_c, Q => hrdata(6)); - - \r.penable\ : DFN1 - port map(D => penable_RNO, CLK => lclk_c, Q => \penable\); - - \r.prdata_RNO_20[7]\ : OR2A - port map(A => N_752_0, B => prdata_1_7, Y => - \prdata_RNO_20[7]\); - - \r.prdata_RNO_12[10]\ : NOR2B - port map(A => \prdata_RNO_14[10]\, B => \prdata_RNO_15[10]\, - Y => \prdata_1_i_0_0[10]\); - - \r.prdata[16]\ : DFN1 - port map(D => \prdata_1[16]\, CLK => lclk_c, Q => - hrdata(16)); - - \r.haddr_RNI3SB72_0[8]\ : NOR2 - port map(A => \N_749\, B => N_745, Y => N_751_0); - - \r.pwdata_1[1]\ : DFN1E0 - port map(D => hwdata(1), CLK => lclk_c, E => N_12_0_0, Q - => pwdata_1_0); - - \r.prdata_RNO_20[0]\ : NOR2 - port map(A => \paddr[8]\, B => \N_116\, Y => - \prdata_1_i_0_a11_0[0]\); - - \r.prdata[25]\ : DFN1 - port map(D => \prdata_1[25]\, CLK => lclk_c, Q => - hrdata(25)); - - \r.haddr_RNI7P9D_1[10]\ : NOR2 - port map(A => \paddr[11]\, B => \paddr[10]\, Y => \N_773\); - - \r.prdata_RNO_7[0]\ : NOR3C - port map(A => readdata_9_0, B => \prdata_1_i_0_a11_3_1[0]\, - C => reload_m_0_d0, Y => \prdata_1_i_0_a11_3_3[0]\); - - \r.prdata_RNO_12[12]\ : AO1A - port map(A => N_6455_0, B => rambanksz_3, C => N_778_i, Y - => \prdata_RNO_12[12]\); - - \r.state_RNI4KU3_0[0]\ : OR2B - port map(A => \pwrite\, B => \state[0]\, Y => N_12_0_0); - - \r.prdata_RNO_6[14]\ : OR2B - port map(A => prdata_3_12, B => N_755, Y => N_204); - - \r.penable_RNO\ : NOR3A - port map(A => rstn, B => cfgsel2, C => N_199, Y => - penable_RNO); - - \r.pwdata_0[2]\ : DFN1E0 - port map(D => hwdata(2), CLK => lclk_c, E => N_12_0_1, Q - => \pwdata_0[2]\); - - \r.prdata_RNO_5[16]\ : OR3B - port map(A => N_766, B => N_155_i, C => N_760, Y => N_714); - - \r.prdata_RNO_5[20]\ : NOR3C - port map(A => N_708, B => N_789, C => N_760, Y => - \prdata_1_i_0_1[20]\); - - \r.prdata_RNO_11[2]\ : OR2B - port map(A => prdata_2_2, B => N_752, Y => N_739); - - \r.prdata_RNO_4[2]\ : AOI1B - port map(A => prdata(2), B => N_762, C => N_734, Y => - \prdata_1_0_0_3[2]\); - - \r.psel_RNITJ1T1\ : NOR3C - port map(A => \prdata_1_i_0_o2_1_4[0]\, B => - \prdata_1_i_0_o2_1_5[0]\, C => psel, Y => \N_769\); - - \r.prdata_RNO_1[7]\ : AO1C - port map(A => readdata56, B => reload_0(7), C => - \prdata_1_i_0_a11_3_3[7]\, Y => N_590_i); - - \r.prdata[10]\ : DFN1 - port map(D => N_106_i_0, CLK => lclk_c, Q => hrdata(10)); - - \r.prdata_RNO_22[5]\ : OR2A - port map(A => un1_grgpio0_0, B => readdata55_3, Y => - \un1_grgpio0_m[69]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_work_leon3mp_wfp_rtl_0 is - - port( clk : in std_logic; - address : in std_logic_vector(7 downto 0); - datain : in std_logic_vector(7 downto 0); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic; - write : in std_logic - ); - -end proasic3_syncram_work_leon3mp_wfp_rtl_0; - -architecture DEF_ARCH of proasic3_syncram_work_leon3mp_wfp_rtl_0 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ3 is - - port( hrdata : out std_logic_vector(15 downto 8); - hwdata : in std_logic_vector(15 downto 8); - haddr_1 : in std_logic_vector(7 downto 0); - N_17 : in std_logic; - lclk_c : in std_logic; - N_18 : in std_logic; - N_22 : in std_logic; - N_14 : in std_logic - ); - -end syncramZ3; - -architecture DEF_ARCH of syncramZ3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_0 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_8, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_0 - port map(clk => lclk_c, address(7) => haddr_1(7), - address(6) => haddr_1(6), address(5) => haddr_1(5), - address(4) => haddr_1(4), address(3) => haddr_1(3), - address(2) => haddr_1(2), address(1) => haddr_1(1), - address(0) => haddr_1(0), datain(7) => hwdata(15), - datain(6) => hwdata(14), datain(5) => hwdata(13), - datain(4) => hwdata(12), datain(3) => hwdata(11), - datain(2) => hwdata(10), datain(1) => hwdata(9), - datain(0) => hwdata(8), dataout(7) => hrdata(15), - dataout(6) => hrdata(14), dataout(5) => hrdata(13), - dataout(4) => hrdata(12), dataout(3) => hrdata(11), - dataout(2) => hrdata(10), dataout(1) => hrdata(9), - dataout(0) => hrdata(8), enable => N_17, write => N_8); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO\ : NOR3B - port map(A => N_14, B => N_22, C => N_18, Y => N_8); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ3_3 is - - port( hrdata : out std_logic_vector(7 downto 0); - hwdata : in std_logic_vector(7 downto 0); - haddr_1 : in std_logic_vector(7 downto 0); - N_17 : in std_logic; - lclk_c : in std_logic; - N_18 : in std_logic; - N_21 : in std_logic; - N_14 : in std_logic - ); - -end syncramZ3_3; - -architecture DEF_ARCH of syncramZ3_3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_0 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_6, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_0 - port map(clk => lclk_c, address(7) => haddr_1(7), - address(6) => haddr_1(6), address(5) => haddr_1(5), - address(4) => haddr_1(4), address(3) => haddr_1(3), - address(2) => haddr_1(2), address(1) => haddr_1(1), - address(0) => haddr_1(0), datain(7) => hwdata(7), - datain(6) => hwdata(6), datain(5) => hwdata(5), datain(4) - => hwdata(4), datain(3) => hwdata(3), datain(2) => - hwdata(2), datain(1) => hwdata(1), datain(0) => hwdata(0), - dataout(7) => hrdata(7), dataout(6) => hrdata(6), - dataout(5) => hrdata(5), dataout(4) => hrdata(4), - dataout(3) => hrdata(3), dataout(2) => hrdata(2), - dataout(1) => hrdata(1), dataout(0) => hrdata(0), enable - => N_17, write => N_6); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO\ : NOR3B - port map(A => N_14, B => N_21, C => N_18, Y => N_6); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ3_2 is - - port( hrdata : out std_logic_vector(31 downto 24); - hwdata : in std_logic_vector(31 downto 24); - haddr_1 : in std_logic_vector(7 downto 0); - N_17 : in std_logic; - lclk_c : in std_logic; - N_19 : in std_logic; - N_22 : in std_logic; - N_14 : in std_logic - ); - -end syncramZ3_2; - -architecture DEF_ARCH of syncramZ3_2 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_0 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_0 - port map(clk => lclk_c, address(7) => haddr_1(7), - address(6) => haddr_1(6), address(5) => haddr_1(5), - address(4) => haddr_1(4), address(3) => haddr_1(3), - address(2) => haddr_1(2), address(1) => haddr_1(1), - address(0) => haddr_1(0), datain(7) => hwdata(31), - datain(6) => hwdata(30), datain(5) => hwdata(29), - datain(4) => hwdata(28), datain(3) => hwdata(27), - datain(2) => hwdata(26), datain(1) => hwdata(25), - datain(0) => hwdata(24), dataout(7) => hrdata(31), - dataout(6) => hrdata(30), dataout(5) => hrdata(29), - dataout(4) => hrdata(28), dataout(3) => hrdata(27), - dataout(2) => hrdata(26), dataout(1) => hrdata(25), - dataout(0) => hrdata(24), enable => N_17, write => N_12); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO\ : NOR3B - port map(A => N_14, B => N_22, C => N_19, Y => N_12); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncramZ3_1 is - - port( hrdata : out std_logic_vector(23 downto 16); - hwdata : in std_logic_vector(23 downto 16); - haddr_1 : in std_logic_vector(7 downto 0); - N_17 : in std_logic; - lclk_c : in std_logic; - N_19 : in std_logic; - N_21 : in std_logic; - N_14 : in std_logic - ); - -end syncramZ3_1; - -architecture DEF_ARCH of syncramZ3_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_work_leon3mp_wfp_rtl_0 - port( clk : in std_logic := 'U'; - address : in std_logic_vector(7 downto 0) := (others => 'U'); - datain : in std_logic_vector(7 downto 0) := (others => 'U'); - dataout : out std_logic_vector(7 downto 0); - enable : in std_logic := 'U'; - write : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_10, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0\ : proasic3_syncram_work_leon3mp_wfp_rtl_0 - port map(clk => lclk_c, address(7) => haddr_1(7), - address(6) => haddr_1(6), address(5) => haddr_1(5), - address(4) => haddr_1(4), address(3) => haddr_1(3), - address(2) => haddr_1(2), address(1) => haddr_1(1), - address(0) => haddr_1(0), datain(7) => hwdata(23), - datain(6) => hwdata(22), datain(5) => hwdata(21), - datain(4) => hwdata(20), datain(3) => hwdata(19), - datain(2) => hwdata(18), datain(1) => hwdata(17), - datain(0) => hwdata(16), dataout(7) => hrdata(23), - dataout(6) => hrdata(22), dataout(5) => hrdata(21), - dataout(4) => hrdata(20), dataout(3) => hrdata(19), - dataout(2) => hrdata(18), dataout(1) => hrdata(17), - dataout(0) => hrdata(16), enable => N_17, write => N_10); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO\ : NOR3B - port map(A => N_14, B => N_21, C => N_19, Y => N_10); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbram is - - port( hwdata : in std_logic_vector(31 downto 0); - hrdata : out std_logic_vector(31 downto 0); - hsize : in std_logic_vector(1 downto 0); - iosn : in std_logic_vector(93 to 93); - htrans : in std_logic_vector(1 to 1); - iosn_1 : in std_logic_vector(93 to 93); - haddr : in std_logic_vector(9 downto 0); - lclk_c : in std_logic; - un315_ioen_NE : in std_logic; - hready : out std_logic; - hwrite_1 : in std_logic; - rstn : in std_logic - ); - -end ahbram; - -architecture DEF_ARCH of ahbram is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ3 - port( hrdata : out std_logic_vector(15 downto 8); - hwdata : in std_logic_vector(15 downto 8) := (others => 'U'); - haddr_1 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_17 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_18 : in std_logic := 'U'; - N_22 : in std_logic := 'U'; - N_14 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component syncramZ3_3 - port( hrdata : out std_logic_vector(7 downto 0); - hwdata : in std_logic_vector(7 downto 0) := (others => 'U'); - haddr_1 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_17 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_18 : in std_logic := 'U'; - N_21 : in std_logic := 'U'; - N_14 : in std_logic := 'U' - ); - end component; - - component syncramZ3_2 - port( hrdata : out std_logic_vector(31 downto 24); - hwdata : in std_logic_vector(31 downto 24) := (others => 'U'); - haddr_1 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_17 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_19 : in std_logic := 'U'; - N_22 : in std_logic := 'U'; - N_14 : in std_logic := 'U' - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component syncramZ3_1 - port( hrdata : out std_logic_vector(23 downto 16); - hwdata : in std_logic_vector(23 downto 16) := (others => 'U'); - haddr_1 : in std_logic_vector(7 downto 0) := (others => 'U'); - N_17 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_19 : in std_logic := 'U'; - N_21 : in std_logic := 'U'; - N_14 : in std_logic := 'U' - ); - end component; - - signal hready_RNO, hsel, hwrite, hwrite_RNO, hwrite_3, - \haddr_1[1]\, \addr[3]\, hwrite_0, \haddr_1[2]\, - \addr[4]\, \haddr_1[3]\, \addr[5]\, \haddr_1[4]\, - \addr[6]\, \haddr_1[5]\, \addr[7]\, \haddr_1[6]\, - \addr[8]\, \haddr_1[7]\, \addr[9]\, \haddr_1[0]\, - \addr[2]\, N_17, hsel_1, hsel_2, hsel_0, N_21, \size[0]\, - \size[1]\, \addr[0]\, N_22, N_14, N_18, \addr[1]\, N_19, - \hready\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : syncramZ3 - Use entity work.syncramZ3(DEF_ARCH); - for all : syncramZ3_3 - Use entity work.syncramZ3_3(DEF_ARCH); - for all : syncramZ3_2 - Use entity work.syncramZ3_2(DEF_ARCH); - for all : syncramZ3_1 - Use entity work.syncramZ3_1(DEF_ARCH); -begin - - hready <= \hready\; - - \r.addr_RNI9NSIJ[7]\ : MX2 - port map(A => haddr(7), B => \addr[7]\, S => hwrite_0, Y - => \haddr_1[5]\); - - \r.hready_RNI8IE2\ : OR2A - port map(A => \hready\, B => hwrite, Y => hwrite_0); - - \r.addr_RNIJ1QKJ[8]\ : MX2 - port map(A => haddr(8), B => \addr[8]\, S => hwrite_0, Y - => \haddr_1[6]\); - - \r.addr[6]\ : DFN1E1 - port map(D => haddr(6), CLK => lclk_c, E => iosn(93), Q => - \addr[6]\); - - \r.addr[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => iosn(93), Q => - \addr[2]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.addr_RNI27LTK[3]\ : MX2 - port map(A => haddr(3), B => \addr[3]\, S => hwrite_0, Y - => \haddr_1[1]\); - - \r.size[0]\ : DFN1E1 - port map(D => hsize(0), CLK => lclk_c, E => iosn(93), Q => - \size[0]\); - - \r.addr[3]\ : DFN1E1 - port map(D => haddr(3), CLK => lclk_c, E => iosn(93), Q => - \addr[3]\); - - \r.addr[4]\ : DFN1E1 - port map(D => haddr(4), CLK => lclk_c, E => iosn(93), Q => - \addr[4]\); - - \comb.v.hsel_2\ : NOR2A - port map(A => htrans(1), B => un315_ioen_NE, Y => hsel_2); - - \r.addr_RNIMME2_0[1]\ : NOR2 - port map(A => \size[1]\, B => \addr[1]\, Y => N_18); - - \r.addr[0]\ : DFN1E1 - port map(D => haddr(0), CLK => lclk_c, E => iosn(93), Q => - \addr[0]\); - - \r.hsel\ : DFN1E1 - port map(D => hsel_2, CLK => lclk_c, E => iosn(93), Q => - hsel_0); - - \r.addr_RNI3JSIJ[6]\ : MX2 - port map(A => haddr(6), B => \addr[6]\, S => hwrite_0, Y - => \haddr_1[4]\); - - \r.hsel_RNI91NO19\ : NOR2A - port map(A => hsel_1, B => hwrite_1, Y => hsel); - - \r.addr_RNI2FLVK[4]\ : MX2 - port map(A => haddr(4), B => \addr[4]\, S => hwrite_0, Y - => \haddr_1[2]\); - - \r.addr_RNI0A9OK[2]\ : MX2 - port map(A => haddr(2), B => \addr[2]\, S => hwrite_0, Y - => \haddr_1[0]\); - - \r.addr_RNIHGA4_0[0]\ : OR3 - port map(A => \size[0]\, B => \size[1]\, C => \addr[0]\, Y - => N_21); - - \ra.1.aram\ : syncramZ3 - port map(hrdata(15) => hrdata(15), hrdata(14) => hrdata(14), - hrdata(13) => hrdata(13), hrdata(12) => hrdata(12), - hrdata(11) => hrdata(11), hrdata(10) => hrdata(10), - hrdata(9) => hrdata(9), hrdata(8) => hrdata(8), - hwdata(15) => hwdata(15), hwdata(14) => hwdata(14), - hwdata(13) => hwdata(13), hwdata(12) => hwdata(12), - hwdata(11) => hwdata(11), hwdata(10) => hwdata(10), - hwdata(9) => hwdata(9), hwdata(8) => hwdata(8), - haddr_1(7) => \haddr_1[7]\, haddr_1(6) => \haddr_1[6]\, - haddr_1(5) => \haddr_1[5]\, haddr_1(4) => \haddr_1[4]\, - haddr_1(3) => \haddr_1[3]\, haddr_1(2) => \haddr_1[2]\, - haddr_1(1) => \haddr_1[1]\, haddr_1(0) => \haddr_1[0]\, - N_17 => N_17, lclk_c => lclk_c, N_18 => N_18, N_22 => - N_22, N_14 => N_14); - - \r.addr[5]\ : DFN1E1 - port map(D => haddr(5), CLK => lclk_c, E => iosn(93), Q => - \addr[5]\); - - GND_i : GND - port map(Y => \GND\); - - \r.size[1]\ : DFN1E1 - port map(D => hsize(1), CLK => lclk_c, E => iosn(93), Q => - \size[1]\); - - \ra.0.aram\ : syncramZ3_3 - port map(hrdata(7) => hrdata(7), hrdata(6) => hrdata(6), - hrdata(5) => hrdata(5), hrdata(4) => hrdata(4), hrdata(3) - => hrdata(3), hrdata(2) => hrdata(2), hrdata(1) => - hrdata(1), hrdata(0) => hrdata(0), hwdata(7) => hwdata(7), - hwdata(6) => hwdata(6), hwdata(5) => hwdata(5), hwdata(4) - => hwdata(4), hwdata(3) => hwdata(3), hwdata(2) => - hwdata(2), hwdata(1) => hwdata(1), hwdata(0) => hwdata(0), - haddr_1(7) => \haddr_1[7]\, haddr_1(6) => \haddr_1[6]\, - haddr_1(5) => \haddr_1[5]\, haddr_1(4) => \haddr_1[4]\, - haddr_1(3) => \haddr_1[3]\, haddr_1(2) => \haddr_1[2]\, - haddr_1(1) => \haddr_1[1]\, haddr_1(0) => \haddr_1[0]\, - N_17 => N_17, lclk_c => lclk_c, N_18 => N_18, N_21 => - N_21, N_14 => N_14); - - \ra.3.aram\ : syncramZ3_2 - port map(hrdata(31) => hrdata(31), hrdata(30) => hrdata(30), - hrdata(29) => hrdata(29), hrdata(28) => hrdata(28), - hrdata(27) => hrdata(27), hrdata(26) => hrdata(26), - hrdata(25) => hrdata(25), hrdata(24) => hrdata(24), - hwdata(31) => hwdata(31), hwdata(30) => hwdata(30), - hwdata(29) => hwdata(29), hwdata(28) => hwdata(28), - hwdata(27) => hwdata(27), hwdata(26) => hwdata(26), - hwdata(25) => hwdata(25), hwdata(24) => hwdata(24), - haddr_1(7) => \haddr_1[7]\, haddr_1(6) => \haddr_1[6]\, - haddr_1(5) => \haddr_1[5]\, haddr_1(4) => \haddr_1[4]\, - haddr_1(3) => \haddr_1[3]\, haddr_1(2) => \haddr_1[2]\, - haddr_1(1) => \haddr_1[1]\, haddr_1(0) => \haddr_1[0]\, - N_17 => N_17, lclk_c => lclk_c, N_19 => N_19, N_22 => - N_22, N_14 => N_14); - - \r.hwrite\ : DFN1 - port map(D => hwrite_RNO, CLK => lclk_c, Q => hwrite); - - \r.hwrite_RNINTSGA8\ : OR2 - port map(A => hwrite, B => hsel_1, Y => N_17); - - \r.addr_RNI1LPKJ[5]\ : MX2 - port map(A => haddr(5), B => \addr[5]\, S => hwrite_0, Y - => \haddr_1[3]\); - - \r.addr[7]\ : DFN1E1 - port map(D => haddr(7), CLK => lclk_c, E => iosn(93), Q => - \addr[7]\); - - \r.addr[1]\ : DFN1E1 - port map(D => haddr(1), CLK => lclk_c, E => iosn(93), Q => - \addr[1]\); - - \r.addr_RNIMME2[1]\ : NOR2A - port map(A => \addr[1]\, B => \size[1]\, Y => N_19); - - \r.hwrite_RNO_0\ : MX2C - port map(A => hwrite, B => hsel_2, S => iosn_1(93), Y => - hwrite_3); - - \r.hready_RNO\ : OR3C - port map(A => hsel, B => hwrite, C => rstn, Y => hready_RNO); - - \r.addr_RNIP5QKJ[9]\ : MX2 - port map(A => haddr(9), B => \addr[9]\, S => hwrite_0, Y - => \haddr_1[7]\); - - \r.hsel_RNIRBHFA8\ : MX2 - port map(A => hsel_0, B => hsel_2, S => iosn_1(93), Y => - hsel_1); - - \r.size_RNIL535[0]\ : AOI1B - port map(A => \size[1]\, B => \size[0]\, C => hwrite, Y => - N_14); - - \r.hready\ : DFN1 - port map(D => hready_RNO, CLK => lclk_c, Q => \hready\); - - \r.addr_RNIHGA4[0]\ : OR3A - port map(A => \addr[0]\, B => \size[0]\, C => \size[1]\, Y - => N_22); - - \r.hwrite_RNO\ : NOR3A - port map(A => rstn, B => hsel, C => hwrite_3, Y => - hwrite_RNO); - - \r.addr[9]\ : DFN1E1 - port map(D => haddr(9), CLK => lclk_c, E => iosn(93), Q => - \addr[9]\); - - \r.addr[8]\ : DFN1E1 - port map(D => haddr(8), CLK => lclk_c, E => iosn(93), Q => - \addr[8]\); - - \ra.2.aram\ : syncramZ3_1 - port map(hrdata(23) => hrdata(23), hrdata(22) => hrdata(22), - hrdata(21) => hrdata(21), hrdata(20) => hrdata(20), - hrdata(19) => hrdata(19), hrdata(18) => hrdata(18), - hrdata(17) => hrdata(17), hrdata(16) => hrdata(16), - hwdata(23) => hwdata(23), hwdata(22) => hwdata(22), - hwdata(21) => hwdata(21), hwdata(20) => hwdata(20), - hwdata(19) => hwdata(19), hwdata(18) => hwdata(18), - hwdata(17) => hwdata(17), hwdata(16) => hwdata(16), - haddr_1(7) => \haddr_1[7]\, haddr_1(6) => \haddr_1[6]\, - haddr_1(5) => \haddr_1[5]\, haddr_1(4) => \haddr_1[4]\, - haddr_1(3) => \haddr_1[3]\, haddr_1(2) => \haddr_1[2]\, - haddr_1(1) => \haddr_1[1]\, haddr_1(0) => \haddr_1[0]\, - N_17 => N_17, lclk_c => lclk_c, N_19 => N_19, N_21 => - N_21, N_14 => N_14); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbrom is - - port( hrdata_12 : out std_logic; - hrdata_10 : out std_logic; - hrdata_11 : out std_logic; - hrdata_2 : out std_logic; - hrdata_15 : out std_logic; - hrdata_22 : out std_logic; - hrdata_14 : out std_logic; - hrdata_28 : out std_logic; - hrdata_4 : out std_logic; - hrdata_23 : out std_logic; - hrdata_1 : out std_logic; - hrdata_0 : out std_logic; - hrdata_3 : out std_logic; - hrdata_21 : out std_logic; - hrdata_27 : out std_logic; - hrdata_25 : out std_logic; - hrdata_9 : out std_logic; - hrdata_30 : out std_logic; - hrdata_16 : out std_logic; - hrdata_7 : out std_logic; - hrdata_17 : out std_logic; - hrdata_19 : out std_logic; - hrdata_6 : out std_logic; - hrdata_18 : out std_logic; - hrdata_29 : out std_logic; - hrdata_5 : out std_logic; - hrdata_8 : out std_logic; - hrdata_13 : out std_logic; - hrdata_26 : out std_logic; - haddr : in std_logic_vector(9 downto 2); - N_95_i_0 : out std_logic; - N_90_i_0 : out std_logic; - N_103_i_0 : out std_logic; - lclk_c : in std_logic - ); - -end ahbrom; - -architecture DEF_ARCH of ahbrom is - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI4 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component ZOR3I - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \addr_0[2]_net_1\, \addr_0[3]_net_1\, - \addr_0[4]_net_1\, \addr_0[5]_net_1\, \addr_0[6]_net_1\, - \addr_0[9]_net_1\, N_430_0, \addr[7]_net_1\, - \addr[8]_net_1\, N_491_i, N_114, N_133_i, N_443, N_236, - \romdata_0_8[26]\, \romdata_0_9[26]\, N_289, - \romdata_0_8[13]\, N_297, \romdata_0_a19_5_0[14]\, - \romdata_0_RNO_1[26]_net_1\, N_392, \romdata_0_7[26]\, - \romdata_0_6[26]\, \romdata_0_7[13]\, - \romdata_0_RNO_2[13]_net_1\, \romdata_0_6[13]\, - \romdata_0_5[13]\, \romdata_0_6[21]\, \romdata_0_4[21]\, - \romdata_0_2[21]\, N_344, \romdata_0_2[13]\, N_290, N_285, - N_286_i, N_281, N_287, N_438, \romdata_0_a19_2_0[13]\, - \romdata_0_1[13]\, N_282, N_288, N_284, \romdata_0_3[3]\, - \romdata_0_1[3]\, \romdata_0_0[3]\, N_525, N_256_1, N_160, - N_494, N_117_i, N_469, N_250, \romdata_0_0[11]\, N_278, - N_134, \romdata_0_7[1]\, N_495, N_259, N_342, - \romdata_0_5[1]\, \romdata_0_a19_5_0[1]\, N_472, N_240, - \romdata_0_4[1]\, \romdata_0_2[1]\, \romdata_0_1[1]\, - N_243, N_242, N_245, N_247, N_241, N_244, - \romdata_0_4[19]\, \romdata_0_3[19]\, N_316, N_315, N_317, - \romdata_0_2[19]\, N_313, \addr_0_RNIP7M91[5]_net_1\, - N_302, \romdata_0_6[0]\, \romdata_0_3[0]\, - \romdata_0_2[0]\, \romdata_0_4[0]\, N_235, N_234, N_238, - \romdata_0_a19_1_0[0]\, N_343_1, N_232, N_237, N_239, - \romdata_0_0[6]\, N_264, N_265, \romdata_0_0[5]\, N_270, - N_439, N_262, \romdata_0_6[2]\, N_248, \romdata_0_2[2]\, - N_148, \romdata_0_5[2]\, N_255, N_251, \romdata_0_0[2]\, - N_253, N_249, \romdata_0_a19_5_0[2]\, N_482, N_252, - \romdata_0_8[21]\, N_345, \romdata_0_3[21]\, N_336, - \romdata_0_7[21]\, N_105, N_465, N_338, \romdata_0_0[21]\, - N_341, \romdata_0_a19_0_1[21]\, N_343, N_463, - \romdata_0_6[15]\, N_479, N_304, \romdata_0_5[15]\, N_301, - \romdata_0_1[15]\, \romdata_0_4[15]\, N_258, N_300, N_303, - \romdata_0_2[4]\, N_260, N_515, \romdata_0_1[4]\, N_261, - \romdata_0_7[23]\, \romdata_0_4[23]\, \romdata_0_3[23]\, - \romdata_0_6[23]\, N_509, N_471, N_351, N_352, N_347, - \romdata_0_0[23]\, N_354, N_156, \romdata_0_a19_1[23]\, - \romdata_0_0[7]\, N_268, N_267, N_379, \romdata_0_2[26]\, - \romdata_0_5[26]\, N_523, N_390, N_153_i, - \romdata_0_1[26]\, N_393, N_387, N_388, N_481, N_437, - N_385, \romdata_0_8[14]\, \romdata_0_4[14]\, N_294, - \romdata_0_5[14]\, N_292, N_291, N_299, \romdata_0_1[14]\, - N_298, N_296, N_293, N_295, \romdata_0_1[9]\, N_276, - \romdata_0_o19_0_0[5]\, N_457, \romdata_0_1[18]\, N_306, - N_312, N_311, \romdata_0_11[25]\, \romdata_0_5[25]\, - N_373, \romdata_0_9[25]\, \romdata_0_10[25]\, - \romdata_0_4[25]\, \romdata_0_7[25]\, N_512, N_448, N_384, - N_383, N_377, N_375, \romdata_0_1[25]\, \romdata_0_0[25]\, - N_380, \romdata_0_a19_9_0[25]\, N_428, N_378, - \romdata_0_a19_1[25]\, N_108, N_376, \romdata_0_1[8]\, - N_138, N_271, \romdata_0_0[8]\, N_516, \romdata_i_16[20]\, - \romdata_i_9[20]\, N_485, \romdata_i_15[20]\, - \romdata_i_8[20]\, N_328, N_334, \romdata_i_14[20]\, - \romdata_i_6[20]\, \romdata_i_11[20]\, N_493, - \addr_0_RNI1PM21[4]_net_1\, N_332, N_331, - \romdata_i_a19_0[20]\, N_329, \romdata_i_2[20]\, N_322, - \romdata_i_4[20]\, N_323, N_330, N_320, N_326, N_324, - N_327, N_319, \addr_RNIGR5M[3]_net_1\, - \addr_RNIER5M_0[9]_net_1\, \romdata_i_15[31]\, - \romdata_i_10[31]\, \romdata_i_9[31]\, N_427, - \romdata_i_12[31]\, N_414, \romdata_i_4[31]\, - \romdata_i_8[31]\, \romdata_i_11[31]\, - \romdata_i_a19_5_0[31]\, N_436, N_412, - \romdata_i_a19_11_0[31]\, \romdata_i_6[31]\, - \romdata_i_2[31]\, N_422, N_425, N_170, N_132, N_417, - N_420, N_421, N_426, N_362, \romdata_i_0[31]\, - \romdata_i_a19_3_1[31]\, N_110, N_419, - \romdata_i_a19_10_0[31]\, N_415, \romdata_0_1[22]\, N_348, - \romdata_0_6[28]\, \romdata_0_2[28]\, N_401, - \romdata_0_5[28]\, N_405, \romdata_0_1[28]\, - \addr_RNIMM7F1[9]_net_1\, N_442, N_398, N_403, N_402, - N_508, \romdata_0_a19_0[11]\, N_109, - \romdata_0_a19_0[21]\, N_136_i, \romdata_i_14[24]\, - \romdata_i_8[24]\, N_364, N_369, \romdata_i_13[24]\, - N_358, \romdata_i_7[24]\, N_367, \romdata_i_12[24]\, - \romdata_i_6[24]\, \romdata_i_5[24]\, N_519, N_489, N_359, - N_370, N_360, \romdata_i_3[24]\, N_361, N_355, N_371, - \romdata_i_a19_10_0[24]\, N_368, N_356, \romdata_i_0[24]\, - \romdata_i_a19_1_1[24]\, N_131, N_363, \romdata_0_0[30]\, - \romdata_0_a19_0_0[30]\, N_410, \romdata_0_a19_1_0[21]\, - \romdata_0_1[17]\, N_172, \romdata_0_0[17]\, N_127, - \romdata_0_a19_1_0[17]\, \addr_0_RNIQ9T21[9]_net_1\, - \romdata_0_a19_3_0[8]\, N_445, \romdata_0_3[27]\, N_112, - \romdata_0_1[27]\, N_397, \romdata_0_0[27]\, - \romdata_0_a19_0_0[27]\, \romdata_0_a19_2_1[28]\, N_399, - \romdata_0_a19_2_0[19]\, \romdata_0_1[29]\, - \romdata_0_a19_0[29]\, \romdata_0_0[29]\, N_450, N_503, - N_407, \romdata_0_o19_0[14]\, N_461, - \romdata_0_a19_0[18]\, \romdata_0_a19_11_0[25]\, N_124, - \romdata_0_a19_0_0[0]\, N_135, \romdata_i_a19_0[31]\, - N_449, N_446, N_107, \romdata_0_a19_0[19]\, N_207, - \romdata_0_a19_0_0[23]\, N_116, \romdata_i_a19_15_0[24]\, - N_500, \romdata_0_a19_3_0[13]\, \romdata_0_a19_0_0[17]\, - N_151, \romdata_0_a19_5_0[21]\, \romdata_0_a19_5_0[25]\, - N_480, \romdata_i_a19_0[24]\, \romdata_i_a19_6_0[31]\, - N_468, \romdata_0_a19_0[25]\, N_499, - \romdata_0_a19_2_0[28]\, N_166, \romdata_i_a19_2_0[31]\, - N_122, \romdata_i_a19_4_0[20]\, \romdata_0_a19_1_0[28]\, - \romdata_i_a19_0_0[24]\, N_273, N_263, N_196, N_185, - N_488, N_408, N_310, N_440, N_184, N_496, N_266, N_441, - N_451, N_511, N_431, N_507, N_453, N_505, N_126, N_470, - N_484, N_277, N_274, N_143, N_275, N_374, N_149_i_i_0, - N_478, \addr_RNIMM7F1[4]_net_1\, N_257, - \addr_RNIPMPD1[4]_net_1\, N_155_i, N_197_i, N_404, - N_291_1, N_293_1, N_16427_tz, N_459, - \addr_0_RNI7CUK_0[6]_net_1\, N_198_i, \addr[2]_net_1\, - N_162_i_i_0, N_400_1, N_106_i, \addr_0_RNIIC2I[4]_net_1\, - N_514, N_279, N_490, \addr_0_RNIP9101_1[6]_net_1\, N_473, - \addr_RNI2ANR_0[3]_net_1\, N_433, N_475, N_476, N_171, - N_432, N_452, \addr[9]_net_1\, N_227, N_130, - \addr[4]_net_1\, \addr[6]_net_1\, N_430, N_497, - \addr_RNIMM7F1_0[2]_net_1\, \romdata_0_RNO_5[13]_net_1\, - N_492, N_502, \addr_RNI7R5M[3]_net_1\, \addr[3]_net_1\, - \addr[5]_net_1\, N_460, N_462, N_454, N_455, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - - \addr_0_RNI5KOR1[9]\ : NOR2A - port map(A => N_397, B => N_398, Y => \romdata_0_1[27]\); - - \addr_RNIMR5M_0[6]\ : OR2 - port map(A => N_449, B => N_431, Y => N_503); - - \addr_RNIER5M[6]\ : OR2B - port map(A => \addr[6]_net_1\, B => N_459, Y => N_364); - - \addr_0_RNIBM8G6[6]\ : OR3C - port map(A => N_275, B => \romdata_0_1[9]\, C => N_274, Y - => hrdata_9); - - \addr_RNIJR5M[9]\ : OR2 - port map(A => N_431, B => N_110, Y => N_475); - - \addr_0_RNIU7881[6]\ : OR3B - port map(A => N_451, B => \addr_0[6]_net_1\, C => N_438, Y - => N_299); - - \addr_0_RNIJUFN2[6]\ : OA1A - port map(A => \romdata_0_a19_0_1[21]\, B => N_438, C => - N_343, Y => \romdata_0_2[21]\); - - \addr_0_RNIBTUD[2]\ : NOR2A - port map(A => \addr_0[3]_net_1\, B => \addr_0[2]_net_1\, Y - => \romdata_0_a19_5_0[25]\); - - \addr_RNIT7Q61_0[7]\ : OR3A - port map(A => N_468, B => N_143, C => N_437, Y => N_425); - - \addr_RNIO44Q6[4]\ : NOR3C - port map(A => N_315, B => N_317, C => \romdata_0_2[19]\, Y - => \romdata_0_3[19]\); - - \addr_RNIFCKG[6]\ : NOR2A - port map(A => \addr[6]_net_1\, B => N_126, Y => N_482); - - \addr_RNIMM7F1_0[2]\ : NOR2A - port map(A => N_511, B => N_471, Y => - \addr_RNIMM7F1_0[2]_net_1\); - - \addr_RNILR5M[5]\ : NOR2A - port map(A => \addr[5]_net_1\, B => N_430, Y => N_343_1); - - \addr_0_RNIV95T[2]\ : OR3A - port map(A => N_108, B => N_437, C => \addr_0[2]_net_1\, Y - => N_453); - - \addr_0_RNIIL1NB[2]\ : OR2A - port map(A => \romdata_0_4[19]\, B => N_134, Y => hrdata_19); - - \addr_0_RNIGM3I1[4]\ : OR3A - port map(A => N_484, B => N_109, C => N_114, Y => N_277); - - \addr_0_RNIERJN[4]\ : OA1C - port map(A => \addr_0[4]_net_1\, B => \addr[7]_net_1\, C - => N_138, Y => \romdata_i_a19_0[20]\); - - \addr_RNI1P811[7]\ : OR2B - port map(A => N_480, B => N_256_1, Y => N_370); - - \addr_0_RNIF3EU1[5]\ : AO1B - port map(A => N_433, B => N_432, C => \addr_0[5]_net_1\, Y - => N_294); - - \romdata_0_RNO_1[13]\ : AND2 - port map(A => \romdata_0_6[13]\, B => \romdata_0_5[13]\, Y - => \romdata_0_7[13]\); - - \addr_RNI1ID52[9]\ : OA1A - port map(A => \romdata_0_a19_9_0[25]\, B => N_428, C => - N_378, Y => \romdata_0_1[25]\); - - \addr_RNINT2B_0[5]\ : OR2A - port map(A => \addr[5]_net_1\, B => \addr[6]_net_1\, Y => - N_437); - - \addr_0_RNICCUK[9]\ : OR2A - port map(A => \addr_0[9]_net_1\, B => N_151, Y => - \romdata_0_a19_0_0[17]\); - - \addr[7]\ : DFN1 - port map(D => haddr(7), CLK => lclk_c, Q => \addr[7]_net_1\); - - \addr_RNIK6SS3[2]\ : NOR3B - port map(A => N_258, B => N_260, C => N_515, Y => - \romdata_0_2[4]\); - - \addr_0_RNIU7881_0[6]\ : OR2B - port map(A => \addr_0[6]_net_1\, B => N_514, Y => N_275); - - \addr_0_RNIMM7F1_0[5]\ : OR3 - port map(A => N_116, B => N_430_0, C => N_442, Y => N_271); - - \addr_RNIA18Q4[9]\ : OR3 - port map(A => N_306, B => N_312, C => N_311, Y => - \romdata_0_1[18]\); - - \addr_0_RNIU9101[9]\ : OR3A - port map(A => \addr_0[9]_net_1\, B => N_109, C => N_114, Y - => N_420); - - \addr_RNID2T07[7]\ : OR2 - port map(A => \romdata_0_0[30]\, B => N_185, Y => hrdata_30); - - \addr_RNIP7Q61[5]\ : AOI1 - port map(A => N_446, B => N_110, C => N_107, Y => - \romdata_0_a19_0[29]\); - - \romdata_0_RNO_0[26]\ : AND2 - port map(A => \romdata_0_RNO_1[26]_net_1\, B => N_392, Y - => \romdata_0_9[26]\); - - \addr_RNISMBC1_1[3]\ : NOR2 - port map(A => N_465, B => N_143, Y => N_259); - - \addr_0_RNIJRJN[6]\ : NOR2 - port map(A => \addr_0[6]_net_1\, B => N_436, Y => N_509); - - \addr_RNIOT2B[3]\ : NOR2B - port map(A => \addr[9]_net_1\, B => \addr[3]_net_1\, Y => - N_156); - - \addr_RNIJCKG[5]\ : OR2B - port map(A => \addr[5]_net_1\, B => N_156, Y => N_324); - - \addr_0_RNI2QLD3[5]\ : NOR3C - port map(A => N_296, B => N_293, C => N_295, Y => - \romdata_0_1[14]\); - - \addr_RNI2P811[9]\ : NOR2A - port map(A => N_463, B => N_428, Y => N_494); - - \addr_RNIUNSL3[2]\ : NOR3B - port map(A => N_237, B => N_239, C => N_236, Y => - \romdata_0_2[0]\); - - \addr_RNIQ7M91[2]\ : NOR3 - port map(A => N_122, B => N_430_0, C => N_107, Y => N_515); - - \romdata_0_RNO_4[26]\ : OA1A - port map(A => N_523, B => \addr_0[3]_net_1\, C => N_390, Y - => \romdata_0_6[26]\); - - \romdata_0_RNO_3[13]\ : NOR3C - port map(A => \romdata_0_2[13]\, B => N_290, C => N_285, Y - => \romdata_0_6[13]\); - - \addr_RNIDCPE5[5]\ : NOR3C - port map(A => \romdata_i_2[20]\, B => N_322, C => - \romdata_i_4[20]\, Y => \romdata_i_8[20]\); - - \addr_RNI1HQCH[2]\ : OR3C - port map(A => N_374, B => \romdata_0_10[25]\, C => - \romdata_0_11[25]\, Y => hrdata_25); - - \addr_0_RNI5VO65[9]\ : NOR3C - port map(A => N_370, B => N_360, C => \romdata_i_3[24]\, Y - => \romdata_i_7[24]\); - - \addr_0_RNI1PM21[4]\ : OR2 - port map(A => N_446, B => \addr_0_RNIIC2I[4]_net_1\, Y => - \addr_0_RNI1PM21[4]_net_1\); - - \addr_RNIRT2B_0[7]\ : NOR2B - port map(A => \addr[8]_net_1\, B => \addr[7]_net_1\, Y => - N_468); - - \addr_RNIER5M_0[9]\ : OR2A - port map(A => N_126, B => N_490, Y => - \addr_RNIER5M_0[9]_net_1\); - - \addr_0_RNIUO5P3[9]\ : AOI1B - port map(A => \addr_0[9]_net_1\, B => N_172, C => - \romdata_0_0[17]\, Y => \romdata_0_1[17]\); - - \addr_0_RNIAC2I[3]\ : NOR2 - port map(A => \addr_0[3]_net_1\, B => N_109, Y => - \romdata_0_a19_0[11]\); - - \addr_RNIRT2B_0[9]\ : NOR2A - port map(A => \addr[9]_net_1\, B => \addr[6]_net_1\, Y => - N_489); - - \addr_RNIGR5M[3]\ : OR2 - port map(A => N_449, B => N_207, Y => - \addr_RNIGR5M[3]_net_1\); - - \addr_0_RNIT7M91_0[4]\ : OR2A - port map(A => N_485, B => \addr_0[4]_net_1\, Y => N_265); - - \addr_RNINCKG[6]\ : OR2A - port map(A => N_480, B => \addr[6]_net_1\, Y => N_363); - - \addr_RNIAO77G[5]\ : OR3C - port map(A => \romdata_0_7[23]\, B => \romdata_0_6[23]\, C - => N_197_i, Y => hrdata_23); - - \addr_RNINVDP9[3]\ : OR3B - port map(A => \romdata_0_3[3]\, B => N_257, C => N_240, Y - => hrdata_3); - - \addr_RNI170Q3[6]\ : NOR3C - port map(A => N_255, B => N_250, C => N_251, Y => - \romdata_0_5[2]\); - - \addr_0_RNIG6AU3[3]\ : NOR3 - port map(A => N_270, B => N_439, C => - \addr_RNIMM7F1_0[2]_net_1\, Y => N_184); - - \addr_0_RNINC2I[9]\ : OR3B - port map(A => \addr[7]_net_1\, B => \addr[8]_net_1\, C => - \addr_0[9]_net_1\, Y => N_430_0); - - \addr_RNIQ7881[7]\ : OR3B - port map(A => N_116, B => \romdata_i_a19_2_0[31]\, C => - N_449, Y => N_415); - - \addr_0_RNIOO071[2]\ : OR3C - port map(A => N_468, B => \romdata_i_a19_0_0[24]\, C => - N_151, Y => N_356); - - \addr_RNIHCKG[5]\ : NOR2 - port map(A => \addr[5]_net_1\, B => N_445, Y => N_502); - - \addr_0_RNIRHR62[9]\ : AOI1 - port map(A => \addr_0[9]_net_1\, B => N_463, C => N_342, Y - => \romdata_0_0[21]\); - - \addr_RNI5P811[7]\ : OR3B - port map(A => N_110, B => N_468, C => N_116, Y => N_322); - - \addr_RNI4P811[7]\ : OR3A - port map(A => N_105, B => N_132, C => N_110, Y => N_361); - - \addr_RNIVR043[3]\ : NOR3C - port map(A => N_420, B => N_421, C => N_426, Y => - \romdata_i_6[31]\); - - \addr_RNISMBC1_0[8]\ : OR3 - port map(A => N_143, B => N_437, C => N_470, Y => N_405); - - \addr_RNIHR5M[4]\ : NOR2A - port map(A => N_499, B => N_138, Y => - \romdata_i_a19_10_0[31]\); - - \addr_RNIFR5M[9]\ : NOR2 - port map(A => N_428, B => N_116, Y => - \romdata_0_a19_5_0[2]\); - - \addr_RNI15CK6[9]\ : OR3 - port map(A => N_259, B => N_306, C => N_134, Y => hrdata_16); - - \addr_0_RNI3CUK[2]\ : NOR2A - port map(A => \addr_0[2]_net_1\, B => N_114, Y => - \romdata_0_a19_2_0[19]\); - - \addr_RNIQPITF[9]\ : OR3C - port map(A => N_197_i, B => \romdata_0_5[15]\, C => - \romdata_0_6[15]\, Y => hrdata_15); - - \addr_RNIPF2F2[6]\ : AOI1B - port map(A => \romdata_0_a19_5_0[2]\, B => N_482, C => - N_252, Y => \romdata_0_0[2]\); - - \addr_RNISMBC1[3]\ : OR3A - port map(A => N_451, B => N_110, C => N_438, Y => N_250); - - \addr_RNI7Q7C3[4]\ : OR2B - port map(A => N_440, B => N_304, Y => N_134); - - \romdata_0_RNO_12[13]\ : OR3 - port map(A => N_105, B => N_132, C => N_448, Y => N_288); - - \addr_0_RNIUO441[2]\ : OR3A - port map(A => \romdata_0_a19_5_0[25]\, B => N_110, C => - N_428, Y => N_378); - - \addr_0_RNIP9101_0[6]\ : NOR2B - port map(A => \addr_0[6]_net_1\, B => N_450, Y => N_130); - - \addr_RNI7HOA7[3]\ : NOR3C - port map(A => N_358, B => \romdata_i_7[24]\, C => N_367, Y - => \romdata_i_13[24]\); - - \romdata_0_RNO_5[26]\ : NOR3C - port map(A => N_393, B => N_387, C => N_388, Y => - \romdata_0_2[26]\); - - \addr_0_RNIO74B1[3]\ : OR2B - port map(A => \romdata_0_a19_0[11]\, B => N_484, Y => N_278); - - \addr_0_RNIIDJR2[5]\ : NOR2B - port map(A => N_241, B => N_244, Y => \romdata_0_1[1]\); - - \addr_0_RNIJC2I[4]\ : NOR2A - port map(A => \addr_0[4]_net_1\, B => N_428, Y => - \romdata_0_a19_11_0[25]\); - - \addr_0_RNI2L584[5]\ : NOR3C - port map(A => N_292, B => N_291, C => N_285, Y => - \romdata_0_5[14]\); - - \addr_RNI5ANR[9]\ : OR2A - port map(A => N_459, B => N_126, Y => N_242); - - \addr_0_RNIKN6Q3[9]\ : NOR3B - port map(A => N_351, B => N_352, C => N_347, Y => - \romdata_0_4[23]\); - - \addr_0_RNIBRPA8[2]\ : NOR2B - port map(A => \romdata_0_3[19]\, B => N_316, Y => - \romdata_0_4[19]\); - - \addr_0_RNI46P09[3]\ : NOR3C - port map(A => \romdata_0_4[25]\, B => N_379, C => - \romdata_0_7[25]\, Y => \romdata_0_10[25]\); - - \addr_RNI7ANR[3]\ : OR3A - port map(A => N_499, B => N_110, C => \addr[3]_net_1\, Y - => N_421); - - \addr_RNI48Q61[5]\ : OR3A - port map(A => N_107, B => N_448, C => N_438, Y => N_408); - - \addr_RNI43T07[2]\ : NOR3C - port map(A => \romdata_0_5[25]\, B => N_373, C => - \romdata_0_9[25]\, Y => \romdata_0_11[25]\); - - \addr_RNI5A5T[2]\ : OR2A - port map(A => N_508, B => \addr[2]_net_1\, Y => N_245); - - \addr_RNIO7Q61[5]\ : OR2 - port map(A => N_502, B => \addr_RNI7R5M[3]_net_1\, Y => - N_170); - - \addr_RNI7R5M[4]\ : NOR2A - port map(A => N_127, B => N_124, Y => - \romdata_0_a19_1_0[0]\); - - \addr_0_RNIPMPD1_0[5]\ : OR3 - port map(A => N_438, B => N_442, C => N_107, Y => N_244); - - \addr_RNIKJFGG[6]\ : OR3C - port map(A => \romdata_0_6[2]\, B => \romdata_0_5[2]\, C - => N_155_i, Y => hrdata_2); - - \addr_RNI2DTV2[5]\ : AOI1B - port map(A => \romdata_0_a19_1_0[0]\, B => N_343_1, C => - N_232, Y => \romdata_0_3[0]\); - - \addr_0_RNINC2I_0[9]\ : NOR2A - port map(A => N_132, B => \addr_0[9]_net_1\, Y => - \romdata_0_a19_0_0[23]\); - - \romdata_0_RNO_13[13]\ : OR3A - port map(A => \romdata_0_a19_3_0[13]\, B => N_114, C => - N_428, Y => N_284); - - \addr_RNIQNEK3[8]\ : NOR2 - port map(A => N_462, B => N_240, Y => N_155_i); - - \addr_RNIHT2B_0[2]\ : OR2 - port map(A => \addr[3]_net_1\, B => \addr[2]_net_1\, Y => - N_124); - - \addr_0_RNIARJN[9]\ : OR2B - port map(A => \addr_0[9]_net_1\, B => N_478, Y => N_397); - - \addr_RNINCKG_0[7]\ : NOR2 - port map(A => \addr[7]_net_1\, B => N_449, Y => - \romdata_i_a19_0[31]\); - - \addr_0_RNI0LJ94[6]\ : OA1A - port map(A => \romdata_i_a19_11_0[31]\, B => N_436, C => - \romdata_i_6[31]\, Y => \romdata_i_10[31]\); - - \addr_RNIQUJK2[2]\ : AOI1 - port map(A => N_256_1, B => N_160, C => N_494, Y => - \romdata_0_1[3]\); - - \addr_0_RNIUHV32[2]\ : AOI1 - port map(A => N_453, B => N_452, C => N_400_1, Y => N_488); - - \addr_0_RNI1SA83[9]\ : NOR3C - port map(A => N_356, B => \romdata_i_0[24]\, C => N_362, Y - => \romdata_i_3[24]\); - - \addr_RNISMBC1_0[6]\ : OR3A - port map(A => N_482, B => N_108, C => N_430, Y => N_238); - - \addr_RNIU7Q61[6]\ : OR3B - port map(A => N_293_1, B => N_131, C => N_116, Y => N_293); - - \addr_RNI7ANR[8]\ : OR3 - port map(A => N_126, B => \addr[8]_net_1\, C => N_445, Y - => N_327); - - \addr_RNI59TE3[9]\ : NOR2A - port map(A => N_261, B => N_148, Y => \romdata_0_1[4]\); - - \addr_0[4]\ : DFN1 - port map(D => haddr(4), CLK => lclk_c, Q => - \addr_0[4]_net_1\); - - \addr_RNIDANR[9]\ : OR2 - port map(A => N_430, B => N_107, Y => N_472); - - \addr_0_RNIKFGG2[2]\ : OA1A - port map(A => \romdata_i_a19_3_1[31]\, B => N_110, C => - N_419, Y => \romdata_i_2[31]\); - - \addr_RNIGANR[4]\ : NOR2 - port map(A => N_445, B => N_438, Y => N_511); - - \addr_0_RNIQH982[6]\ : AO1C - port map(A => N_514, B => N_286_i, C => \addr_0[6]_net_1\, - Y => N_496); - - \addr_RNISMBC1[2]\ : OR3 - port map(A => N_116, B => N_441, C => N_438, Y => N_239); - - \addr_0_RNIML5KB[4]\ : OR3B - port map(A => N_184, B => \romdata_0_0[6]\, C => N_196, Y - => hrdata_6); - - GND_i : GND - port map(Y => \GND\); - - \addr_0_RNI3A5T[4]\ : OR3A - port map(A => \addr[7]_net_1\, B => \addr_0[4]_net_1\, C - => N_441, Y => N_331); - - \addr[8]\ : DFN1 - port map(D => haddr(8), CLK => lclk_c, Q => \addr[8]_net_1\); - - \addr_RNIQ7881_0[7]\ : OR3A - port map(A => N_480, B => N_107, C => N_442, Y => N_426); - - \addr_0_RNINNOO3[3]\ : NOR3B - port map(A => N_244, B => N_276, C => N_270, Y => - \romdata_0_1[9]\); - - \addr_RNIL65O8[3]\ : OR3B - port map(A => \romdata_0_1[4]\, B => \romdata_0_2[4]\, C - => N_259, Y => hrdata_4); - - \addr_RNI8ANR[4]\ : OR2B - port map(A => \addr[4]_net_1\, B => N_493, Y => N_249); - - \addr_RNI1BR48[4]\ : OR3C - port map(A => N_184, B => \romdata_0_0[7]\, C => N_266, Y - => hrdata_7); - - \addr_RNIER5M[9]\ : NOR2A - port map(A => \addr[9]_net_1\, B => N_446, Y => N_493); - - \addr_0_RNI553P1[5]\ : OA1A - port map(A => N_489, B => N_471, C => N_359, Y => - \romdata_i_8[24]\); - - \addr_0_RNI1CVL5[6]\ : NOR3C - port map(A => \romdata_0_2[28]\, B => N_153_i, C => N_401, - Y => \romdata_0_6[28]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \addr_RNIMT2B[3]\ : OR2A - port map(A => \addr[3]_net_1\, B => \addr[7]_net_1\, Y => - N_207); - - \addr_RNI9ANR[5]\ : OR2A - port map(A => N_459, B => N_448, Y => N_235); - - \addr_RNI6B853[2]\ : NOR3C - port map(A => N_242, B => N_245, C => N_247, Y => - \romdata_0_2[1]\); - - \addr_0_RNI7A5T[6]\ : OR3 - port map(A => N_132, B => \addr_0[6]_net_1\, C => N_107, Y - => N_330); - - \addr_RNI7RJN[4]\ : NOR2A - port map(A => N_112, B => N_437, Y => - \romdata_i_a19_5_0[31]\); - - \addr_RNI2A5T[8]\ : OR3A - port map(A => \addr_0[6]_net_1\, B => \addr[8]_net_1\, C - => N_143, Y => N_329); - - \addr_0_RNI88881[6]\ : NOR2B - port map(A => N_476, B => N_475, Y => N_171); - - \addr_RNIKT2B[2]\ : OR2A - port map(A => \addr[2]_net_1\, B => \addr[6]_net_1\, Y => - N_109); - - \addr_RNI9P811[6]\ : OR3 - port map(A => N_116, B => N_430, C => \addr[6]_net_1\, Y - => N_251); - - \addr_RNIH6AU3[8]\ : NOR3A - port map(A => N_258, B => N_494, C => N_302, Y => - \romdata_0_4[15]\); - - \addr_RNI18Q61[9]\ : OR3 - port map(A => N_116, B => N_430, C => N_109, Y => N_261); - - \addr_0_RNIGM3I1[2]\ : OR3A - port map(A => \romdata_0_a19_3_0[8]\, B => N_114, C => - N_430_0, Y => N_273); - - \addr_RNIRT2B[7]\ : OR2 - port map(A => \addr[8]_net_1\, B => \addr[7]_net_1\, Y => - N_132); - - \addr_RNIR83M3[8]\ : OA1A - port map(A => N_523, B => N_112, C => \romdata_0_1[27]\, Y - => \romdata_0_3[27]\); - - \addr_RNI3RJN[2]\ : OR2 - port map(A => N_122, B => N_107, Y => N_505); - - \addr_RNIICKG[9]\ : NOR2A - port map(A => \addr[9]_net_1\, B => N_108, Y => N_459); - - \addr_RNI08881[4]\ : OR2A - port map(A => N_512, B => N_442, Y => N_276); - - \addr_0_RNIV7881[3]\ : NOR2 - port map(A => N_519, B => N_430, Y => N_443); - - \addr_RNISMBC1[8]\ : OR3A - port map(A => N_143, B => N_437, C => N_470, Y => N_407); - - \addr_RNIT7Q61[7]\ : AO1B - port map(A => N_126, B => N_116, C => \romdata_i_a19_0[24]\, - Y => N_355); - - \addr_RNIMUFN2[2]\ : OA1 - port map(A => N_105, B => N_465, C => N_338, Y => - \romdata_0_7[21]\); - - \addr_RNI91H92[4]\ : OA1A - port map(A => N_512, B => N_448, C => N_287, Y => - \romdata_0_9[25]\); - - \addr_RNI8P811_0[5]\ : OR2B - port map(A => \addr[5]_net_1\, B => N_492, Y => N_334); - - \addr_RNI3THD5[6]\ : NOR3C - port map(A => \romdata_0_1[25]\, B => \romdata_0_0[25]\, C - => N_380, Y => \romdata_0_4[25]\); - - \addr_0_RNIMC2I[9]\ : OR2 - port map(A => \addr_0[9]_net_1\, B => N_449, Y => - \romdata_0_a19_5_0[21]\); - - \addr_0_RNIHTUD[2]\ : NOR2B - port map(A => \addr_0[2]_net_1\, B => \addr_0[9]_net_1\, Y - => \romdata_0_a19_0_0[0]\); - - \addr_0_RNIUOM21[3]\ : NOR3A - port map(A => N_105, B => \addr_0[3]_net_1\, C => N_469, Y - => N_270); - - \addr_RNI2ANR[3]\ : NOR2A - port map(A => N_451, B => N_448, Y => N_516); - - \addr_0_RNIJMLG1[2]\ : OR2B - port map(A => \romdata_0_a19_2_0[19]\, B => N_511, Y => - N_316); - - \addr_0_RNIGUP7A[4]\ : NOR3C - port map(A => \romdata_i_10[31]\, B => \romdata_i_9[31]\, C - => N_427, Y => \romdata_i_15[31]\); - - \addr_0_RNIV9JU[5]\ : OR3B - port map(A => N_291_1, B => \addr_0[5]_net_1\, C => N_112, - Y => N_417); - - \addr_RNI9ANR[9]\ : NOR2A - port map(A => N_459, B => N_437, Y => N_497); - - \addr_RNI08Q61_0[2]\ : OR3 - port map(A => N_116, B => N_430, C => N_126, Y => N_404); - - \addr_RNIIT2B[2]\ : XOR2 - port map(A => \addr[4]_net_1\, B => \addr[2]_net_1\, Y => - N_117_i); - - \addr_0_RNIT7M91[4]\ : OR2B - port map(A => \addr_0[4]_net_1\, B => N_485, Y => N_427); - - \addr_RNIP7M91[4]\ : OR2A - port map(A => N_227, B => N_507, Y => N_300); - - \addr_RNIJMLG1[2]\ : OR3 - port map(A => N_471, B => N_445, C => N_430_0, Y => N_310); - - \addr_0_RNIMUFN2[4]\ : NOR2B - port map(A => N_264, B => N_265, Y => \romdata_0_0[6]\); - - \addr_RNIHCKG[8]\ : NOR2A - port map(A => \addr[8]_net_1\, B => N_107, Y => - \romdata_i_a19_10_0[24]\); - - \addr_RNI3RP2I[5]\ : NOR3C - port map(A => \romdata_i_15[20]\, B => \romdata_i_14[20]\, - C => \romdata_i_16[20]\, Y => N_90_i_0); - - \addr_RNI1P811[6]\ : OR2B - port map(A => N_482, B => N_459, Y => N_380); - - \addr_0_RNI0G2F2[3]\ : AOI1B - port map(A => \romdata_0_a19_0_0[27]\, B => - \romdata_0_a19_2_1[28]\, C => N_399, Y => - \romdata_0_0[27]\); - - \addr_RNIMR5M[6]\ : NOR2 - port map(A => N_431, B => N_138, Y => - \romdata_0_a19_2_1[28]\); - - \addr_RNINT2B[5]\ : OR2B - port map(A => \addr[6]_net_1\, B => \addr[5]_net_1\, Y => - N_110); - - \addr[5]\ : DFN1 - port map(D => haddr(5), CLK => lclk_c, Q => \addr[5]_net_1\); - - \addr_RNIMM7F1[9]\ : OR3 - port map(A => N_400_1, B => N_198_i, C => N_519, Y => - \addr_RNIMM7F1[9]_net_1\); - - \addr_RNI9MQE6[9]\ : NOR3B - port map(A => \romdata_i_6[20]\, B => \romdata_i_11[20]\, C - => N_493, Y => \romdata_i_14[20]\); - - \addr_0_RNIDC2I[4]\ : NOR2A - port map(A => N_207, B => \addr_0[4]_net_1\, Y => - \romdata_0_a19_0[19]\); - - \addr_RNIMT2B[4]\ : XNOR2 - port map(A => \addr[4]_net_1\, B => \addr[6]_net_1\, Y => - N_127); - - \addr_0_RNILD5Q2[9]\ : NOR2B - port map(A => N_268, B => N_267, Y => \romdata_0_0[7]\); - - \addr_0_RNI7CUK_0[6]\ : NOR2 - port map(A => \addr_0[6]_net_1\, B => N_114, Y => - \addr_0_RNI7CUK_0[6]_net_1\); - - \romdata_0_RNO_2[26]\ : NOR3C - port map(A => N_379, B => \romdata_0_2[26]\, C => - \romdata_0_5[26]\, Y => \romdata_0_7[26]\); - - \addr_RNIQT2B[6]\ : XOR2 - port map(A => \addr[8]_net_1\, B => \addr[6]_net_1\, Y => - N_106_i); - - \addr_0_RNIGM3I1[6]\ : NOR3 - port map(A => N_114, B => N_430_0, C => - \romdata_0_a19_0[18]\, Y => N_311); - - \addr_0_RNIP9101[6]\ : NOR3B - port map(A => \addr_0[6]_net_1\, B => N_135, C => N_105, Y - => \romdata_0_a19_0_1[21]\); - - \romdata_0_RNO_2[13]\ : OR2 - port map(A => N_465, B => \romdata_0_RNO_5[13]_net_1\, Y - => \romdata_0_RNO_2[13]_net_1\); - - \addr_RNIHFDK7[4]\ : OR3C - port map(A => \addr_RNIMM7F1[4]_net_1\, B => - \romdata_0_0[27]\, C => \romdata_0_3[27]\, Y => hrdata_27); - - \addr_RNIRT2B_1[7]\ : NOR2A - port map(A => \addr[7]_net_1\, B => \addr[8]_net_1\, Y => - N_480); - - \addr_0_RNIPMPD1[9]\ : OR3A - port map(A => \romdata_0_a19_0_0[23]\, B => N_116, C => - N_441, Y => N_351); - - \addr_RNISMBC1_1[6]\ : OR3A - port map(A => N_482, B => N_108, C => N_438, Y => N_247); - - \addr_RNI0I427[5]\ : NOR3C - port map(A => \romdata_0_2[1]\, B => \romdata_0_1[1]\, C - => N_243, Y => \romdata_0_4[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \addr_RNICMLG1[2]\ : OAI1 - port map(A => N_478, B => \addr_0_RNI7CUK_0[6]_net_1\, C - => N_291_1, Y => N_291); - - \addr_0_RNI2AJU[2]\ : OR3B - port map(A => N_149_i_i_0, B => N_468, C => - \addr_0[2]_net_1\, Y => N_319); - - \addr_RNI2ID52[3]\ : OA1B - port map(A => N_450, B => N_503, C => N_460, Y => N_153_i); - - \addr_0[9]\ : DFN1 - port map(D => haddr(9), CLK => lclk_c, Q => - \addr_0[9]_net_1\); - - \addr_0_RNI6MHJ1[2]\ : OAI1 - port map(A => N_478, B => \addr_0_RNI7CUK_0[6]_net_1\, C - => \romdata_0_a19_0_0[0]\, Y => N_232); - - \romdata_0_RNO_9[13]\ : OR3B - port map(A => \addr_0[3]_net_1\, B => \addr_0[5]_net_1\, C - => N_127, Y => \romdata_0_a19_2_0[13]\); - - \addr_RNIR7881[4]\ : OR3 - port map(A => N_446, B => N_431, C => N_112, Y => N_315); - - \addr_RNIJ5GH6[5]\ : OR3C - port map(A => N_408, B => \romdata_0_0[29]\, C => - \romdata_0_1[29]\, Y => hrdata_29); - - \addr_0_RNIU7881_1[6]\ : OR2B - port map(A => N_509, B => N_451, Y => N_287); - - \addr_0_RNILC2I[5]\ : NOR2B - port map(A => \addr_0[5]_net_1\, B => N_500, Y => - \romdata_i_a19_15_0[24]\); - - \addr_0_RNIPMPD1[4]\ : OR3B - port map(A => \romdata_0_a19_0[19]\, B => N_500, C => N_441, - Y => N_313); - - \addr_RNIQCKG[8]\ : OR2A - port map(A => \addr[8]_net_1\, B => N_431, Y => N_470); - - \addr_RNI0R1P[4]\ : AXOI4 - port map(A => \addr[4]_net_1\, B => N_122, C => - \addr_0[3]_net_1\, Y => N_227); - - \addr_0_RNIETUD_0[5]\ : OR2 - port map(A => \addr_0[5]_net_1\, B => \addr_0[3]_net_1\, Y - => N_114); - - \addr_RNIOCKG[6]\ : NOR2 - port map(A => \addr[6]_net_1\, B => N_431, Y => N_293_1); - - \addr_RNIIA5T[9]\ : OR2B - port map(A => N_490, B => N_430_0, Y => N_160); - - \addr_RNI9P811_0[6]\ : OR3 - port map(A => N_107, B => N_428, C => N_106_i, Y => N_433); - - \addr_RNI2ANR[2]\ : OR2 - port map(A => N_441, B => N_108, Y => N_473); - - \addr_0_RNIL74B1[3]\ : OR3A - port map(A => \romdata_0_a19_11_0[25]\, B => N_442, C => - \addr_0[3]_net_1\, Y => N_384); - - \addr_RNI6R5M[5]\ : NOR2A - port map(A => N_166, B => N_124, Y => - \romdata_0_a19_0_0[27]\); - - \addr_0_RNIK0ED7[9]\ : OR3A - port map(A => \romdata_0_0[11]\, B => N_259, C => N_342, Y - => hrdata_11); - - \addr_0_RNI3A5T[2]\ : NOR3B - port map(A => N_480, B => N_116, C => \addr_0[2]_net_1\, Y - => \romdata_i_a19_3_1[31]\); - - \addr_RNI0P441[4]\ : OR3 - port map(A => N_114, B => N_428, C => N_445, Y => N_296); - - \addr_RNIRO441_0[9]\ : OR2A - port map(A => N_489, B => N_450, Y => N_383); - - \romdata_0_RNO_3[26]\ : OR2 - port map(A => \addr[5]_net_1\, B => N_472, Y => N_392); - - \addr_RNI08H36[2]\ : NOR3B - port map(A => \romdata_0_1[3]\, B => \romdata_0_0[3]\, C - => N_525, Y => \romdata_0_3[3]\); - - \addr_RNI38Q61[4]\ : OR2A - port map(A => N_512, B => N_446, Y => N_455); - - \addr_0_RNIRO441[9]\ : NOR3C - port map(A => N_479, B => \addr_0[9]_net_1\, C => N_451, Y - => N_347); - - \romdata_0_RNO[26]\ : AND2 - port map(A => \romdata_0_7[26]\, B => \romdata_0_6[26]\, Y - => \romdata_0_8[26]\); - - \romdata_0_a19_5[14]\ : NAND2 - port map(A => N_491_i, B => \romdata_0_a19_5_0[14]\, Y => - N_297); - - \addr_0_RNIQ9T21[9]\ : OR2 - port map(A => \romdata_0_a19_0_0[17]\, B => N_135, Y => - \addr_0_RNIQ9T21[9]_net_1\); - - \romdata_0[26]\ : NAND2 - port map(A => \romdata_0_8[26]\, B => \romdata_0_9[26]\, Y - => hrdata_26); - - \romdata_0_RNO_10[13]\ : NOR3C - port map(A => N_282, B => N_288, C => N_284, Y => - \romdata_0_1[13]\); - - \addr_0_RNILC2I[6]\ : OR2 - port map(A => \addr_0[6]_net_1\, B => N_428, Y => N_476); - - \addr_0_RNIDVA55[3]\ : OR3B - port map(A => N_310, B => N_440, C => N_279, Y => hrdata_12); - - \addr_RNIST2B[9]\ : OR2A - port map(A => \addr[7]_net_1\, B => \addr[9]_net_1\, Y => - N_428); - - \addr_0_RNIJTUD[4]\ : NOR2A - port map(A => \addr_0[9]_net_1\, B => \addr_0[4]_net_1\, Y - => \romdata_0_a19_1_0[28]\); - - \addr_0_RNICC2I[5]\ : OR2A - port map(A => \addr_0[5]_net_1\, B => N_109, Y => N_442); - - \romdata_0_RNO_12[26]\ : OR3A - port map(A => N_198_i, B => \addr_0[2]_net_1\, C => N_507, - Y => N_385); - - \addr_RNICL954[5]\ : AND2 - port map(A => \romdata_0_2[21]\, B => N_344, Y => - \romdata_0_4[21]\); - - \addr_RNIMCKG[9]\ : OR2A - port map(A => \addr[9]_net_1\, B => N_437, Y => N_469); - - \addr_RNIST2B_0[9]\ : OR2 - port map(A => \addr[9]_net_1\, B => \addr[7]_net_1\, Y => - N_431); - - \addr_RNIG7M91[5]\ : AO1A - port map(A => N_109, B => N_114, C => N_478, Y => N_172); - - \addr_RNIFCKG[2]\ : OR2A - port map(A => \addr[2]_net_1\, B => N_110, Y => N_441); - - \addr_RNI6PM21[8]\ : NOR2 - port map(A => N_442, B => N_436, Y => N_485); - - \addr_0_RNI8C2I_0[4]\ : NOR2A - port map(A => \addr_0[4]_net_1\, B => N_124, Y => N_481); - - \romdata_0_RNO_14[13]\ : NOR2B - port map(A => \addr_0[6]_net_1\, B => N_117_i, Y => - \romdata_0_a19_3_0[13]\); - - \addr_RNIUOM21[9]\ : OR3B - port map(A => N_489, B => N_107, C => N_122, Y => N_303); - - \addr_RNIFCKG[5]\ : OR2 - port map(A => \addr[5]_net_1\, B => N_109, Y => N_446); - - \addr_RNICDFU2[3]\ : OR2 - port map(A => N_461, B => N_302, Y => \romdata_0_o19_0[14]\); - - \addr_RNIBCKG_0[3]\ : NOR2A - port map(A => \addr[3]_net_1\, B => N_105, Y => N_451); - - \addr_0_RNIBC2I[5]\ : XNOR2 - port map(A => \addr_0[5]_net_1\, B => N_107, Y => - N_162_i_i_0); - - \addr_RNIBANR[6]\ : OR2A - port map(A => N_482, B => N_431, Y => N_332); - - \addr_RNIPTDSC[2]\ : OR3C - port map(A => N_404, B => \romdata_0_5[28]\, C => - \romdata_0_6[28]\, Y => hrdata_28); - - \addr_0_RNIT5K24[9]\ : NOR3C - port map(A => \romdata_0_0[21]\, B => N_341, C => N_286_i, - Y => \romdata_0_3[21]\); - - \addr_RNIDC2I[7]\ : NOR2A - port map(A => \addr[7]_net_1\, B => N_122, Y => - \romdata_i_a19_2_0[31]\); - - \addr_0_RNIPHR62[6]\ : AO1D - port map(A => N_463, B => \addr_0_RNIP9101_1[6]_net_1\, C - => N_430, Y => N_248); - - \addr_0[6]\ : DFN1 - port map(D => haddr(6), CLK => lclk_c, Q => - \addr_0[6]_net_1\); - - \addr_RNIUOM21_0[9]\ : OR2A - port map(A => N_481, B => N_469, Y => N_237); - - \romdata_0_a19_5_RNII17T7[14]\ : NOR3C - port map(A => \romdata_0_4[14]\, B => N_294, C => N_297, Y - => \romdata_0_8[14]\); - - \addr_RNITT2B[9]\ : OR2A - port map(A => \addr[8]_net_1\, B => \addr[9]_net_1\, Y => - N_400_1); - - \addr_RNIGCKG[7]\ : OR2 - port map(A => \addr[7]_net_1\, B => N_116, Y => - \romdata_0_a19_0_0[30]\); - - \addr_0_RNI0A5T[2]\ : OR3B - port map(A => \addr[7]_net_1\, B => N_478, C => - \addr_0[2]_net_1\, Y => N_328); - - \romdata_0_RNO_5[13]\ : NOR2B - port map(A => \addr_0[3]_net_1\, B => N_117_i, Y => - \romdata_0_RNO_5[13]_net_1\); - - \addr_0_RNICC2I[6]\ : NOR2B - port map(A => \addr_0[6]_net_1\, B => N_108, Y => - \romdata_0_a19_1_0[21]\); - - \addr_0_RNITR043[4]\ : NOR3C - port map(A => N_383, B => N_377, C => N_375, Y => - \romdata_0_5[25]\); - - \addr_RNI6NPD1[8]\ : NOR2 - port map(A => \addr[8]_net_1\, B => N_171, Y => N_523); - - \addr_RNIO7M91[6]\ : OR2A - port map(A => N_293_1, B => N_450, Y => N_317); - - \addr_0_RNI4RFQ[5]\ : OR3C - port map(A => \addr_0[5]_net_1\, B => \addr_0[9]_net_1\, C - => N_112, Y => N_359); - - \addr_RNIGFQ0A[9]\ : NOR3C - port map(A => N_301, B => \romdata_0_1[15]\, C => - \romdata_0_4[15]\, Y => \romdata_0_5[15]\); - - \addr_RNI2A5T[9]\ : OR2A - port map(A => \addr[9]_net_1\, B => N_505, Y => N_422); - - \addr_0_RNIKTGC[5]\ : NOR2A - port map(A => \addr[6]_net_1\, B => \addr_0[5]_net_1\, Y - => N_479); - - \romdata_0_RNO_7[26]\ : OR3A - port map(A => \addr[5]_net_1\, B => N_108, C => N_430, Y - => N_390); - - \addr_RNI9NPD1[6]\ : OA1C - port map(A => N_106_i, B => N_428, C => N_509, Y => - N_16427_tz); - - \addr_0[5]\ : DFN1 - port map(D => haddr(5), CLK => lclk_c, Q => - \addr_0[5]_net_1\); - - \addr[9]\ : DFN1 - port map(D => haddr(9), CLK => lclk_c, Q => \addr[9]_net_1\); - - \addr_RNIQCKG_0[8]\ : OR2 - port map(A => \addr[8]_net_1\, B => N_428, Y => N_438); - - \addr_0_RNIIFGG2[5]\ : OA1A - port map(A => N_170, B => N_132, C => N_417, Y => - \romdata_i_8[31]\); - - \addr_RNIRT2B[9]\ : OR2B - port map(A => \addr[9]_net_1\, B => \addr[6]_net_1\, Y => - N_490); - - \addr_RNIU5BJ1[2]\ : OR2B - port map(A => \addr[2]_net_1\, B => N_523, Y => N_373); - - \addr_RNIPK029[4]\ : NOR3B - port map(A => N_248, B => \romdata_0_2[2]\, C => N_148, Y - => \romdata_0_6[2]\); - - \addr_RNIMT2B_0[4]\ : OR2B - port map(A => \addr[6]_net_1\, B => \addr[4]_net_1\, Y => - N_445); - - \addr_0_RNIU7M91[6]\ : OR3A - port map(A => N_162_i_i_0, B => \addr_0[6]_net_1\, C => - N_438, Y => N_401); - - \addr_0_RNI2RFQ[9]\ : OR2A - port map(A => \addr_0[9]_net_1\, B => N_471, Y => - \romdata_0_a19_1_0[17]\); - - \addr_RNI8P811[5]\ : OR3 - port map(A => N_116, B => N_430, C => \addr[5]_net_1\, Y - => N_243); - - \addr_0_RNIBC2I[6]\ : OR2 - port map(A => \addr_0[6]_net_1\, B => N_117_i, Y => - \romdata_0_a19_0[18]\); - - \addr_0_RNI1IR62[5]\ : OA1B - port map(A => N_438, B => N_442, C => N_398, Y => - \romdata_0_2[28]\); - - \romdata_0_RNO[13]\ : OR2 - port map(A => \addr[6]_net_1\, B => N_495, Y => N_289); - - \addr_RNIO9KV5[8]\ : NOR3C - port map(A => N_405, B => \romdata_0_1[28]\, C => - \addr_RNIMM7F1[9]_net_1\, Y => \romdata_0_5[28]\); - - \addr_0_RNICCGJ[3]\ : NOR3B - port map(A => \addr_0[3]_net_1\, B => \addr[7]_net_1\, C - => \addr_0[6]_net_1\, Y => \romdata_i_a19_1_1[24]\); - - \addr_RNIJ1GK4[9]\ : NOR3C - port map(A => \romdata_i_2[31]\, B => N_422, C => N_425, Y - => \romdata_i_9[31]\); - - \addr_0_RNIJ6SS3[9]\ : OR3 - port map(A => N_312, B => N_347, C => N_348, Y => - \romdata_0_1[22]\); - - \addr_0_RNIJC2I[9]\ : OR2A - port map(A => \addr_0[9]_net_1\, B => N_110, Y => N_362); - - \addr_0_RNIPMPD1[5]\ : OR3B - port map(A => N_451, B => N_479, C => N_436, Y => N_241); - - \romdata_0_RNO_11[26]\ : OA1A - port map(A => N_481, B => N_437, C => N_385, Y => - \romdata_0_1[26]\); - - \addr_RNI08Q61[2]\ : OR3A - port map(A => N_126, B => N_116, C => N_436, Y => N_358); - - \addr_0_RNIMM7F1[5]\ : OR3A - port map(A => N_107, B => N_442, C => N_430_0, Y => N_457); - - \addr_RNI8P811_1[5]\ : OR2A - port map(A => N_478, B => N_438, Y => N_379); - - \addr_0_RNIITGC[5]\ : XNOR2 - port map(A => \addr_0[5]_net_1\, B => \addr[4]_net_1\, Y - => N_149_i_i_0); - - \addr_RNIN7M91[7]\ : AO1C - port map(A => N_122, B => N_112, C => \romdata_i_a19_0[31]\, - Y => N_412); - - \addr_0_RNIRO441[4]\ : OR3B - port map(A => N_124, B => \romdata_0_a19_1_0[28]\, C => - N_448, Y => N_402); - - \addr_RNIJT2B[3]\ : OR2B - port map(A => \addr[4]_net_1\, B => \addr[3]_net_1\, Y => - N_107); - - \addr_0_RNIGGBU4[6]\ : OR2B - port map(A => \romdata_0_o19_0_0[5]\, B => N_496, Y => - N_196); - - \addr_0_RNID67M6[9]\ : OR3C - port map(A => \romdata_0_1[17]\, B => N_310, C => N_267, Y - => hrdata_17); - - \romdata_0[13]\ : NAND2 - port map(A => N_289, B => \romdata_0_8[13]\, Y => hrdata_13); - - \addr_RNIJT2B_0[2]\ : OR2A - port map(A => \addr[2]_net_1\, B => \addr[5]_net_1\, Y => - N_126); - - \romdata_0_a2_0[8]\ : NOR2 - port map(A => N_114, B => N_430_0, Y => N_491_i); - - \addr_RNIJT2B_1[3]\ : OR2 - port map(A => \addr[4]_net_1\, B => \addr[3]_net_1\, Y => - N_108); - - \addr_RNI7R5M[2]\ : NOR2 - port map(A => N_124, B => N_445, Y => - \romdata_0_a19_9_0[25]\); - - \addr_RNI08Q61[5]\ : OR2A - port map(A => N_343_1, B => N_143, Y => N_343); - - \addr_0[2]\ : DFN1 - port map(D => haddr(2), CLK => lclk_c, Q => - \addr_0[2]_net_1\); - - \addr_0_RNIAVE25[2]\ : OR2 - port map(A => \romdata_0_o19_0[14]\, B => N_488, Y => N_185); - - \addr_RNIQCKG_1[8]\ : OR2 - port map(A => \addr[8]_net_1\, B => N_431, Y => N_436); - - \addr_RNIPMPD1[5]\ : OR3 - port map(A => N_108, B => N_430_0, C => N_446, Y => N_344); - - \addr_RNIIDJR2[8]\ : OA1 - port map(A => N_450, B => N_503, C => N_407, Y => - \romdata_0_0[29]\); - - \addr_RNI5LN64[8]\ : NOR3B - port map(A => N_235, B => \romdata_i_9[20]\, C => N_485, Y - => \romdata_i_16[20]\); - - \addr_RNIPMPD1[2]\ : OR2 - port map(A => N_505, B => N_503, Y => N_264); - - \addr_0_RNIKTGC[3]\ : NOR2A - port map(A => \addr_0[3]_net_1\, B => \addr[8]_net_1\, Y - => \romdata_i_a19_4_0[20]\); - - \addr_RNIUP7C3[7]\ : NOR3C - port map(A => N_361, B => N_355, C => N_371, Y => - \romdata_i_6[24]\); - - \addr_RNI8K2OG[3]\ : NOR3C - port map(A => \romdata_i_13[24]\, B => \romdata_i_12[24]\, - C => \romdata_i_14[24]\, Y => N_95_i_0); - - \addr_0_RNIBC2I[2]\ : NOR2A - port map(A => \addr_0[2]_net_1\, B => N_445, Y => - \romdata_0_a19_3_0[8]\); - - \addr_RNIU0382[8]\ : OA1C - port map(A => N_473, B => \addr_RNI2ANR_0[3]_net_1\, C => - N_436, Y => N_240); - - \addr_RNISMBC1_4[8]\ : NOR2 - port map(A => N_473, B => N_438, Y => N_348); - - \addr_0_RNIKTGC[4]\ : XOR2 - port map(A => \addr[7]_net_1\, B => \addr_0[4]_net_1\, Y - => N_198_i); - - \addr_RNINCKG[7]\ : NOR2A - port map(A => \addr[7]_net_1\, B => N_449, Y => - \romdata_i_a19_0[24]\); - - \addr_0_RNIJMLG1_0[6]\ : NOR2 - port map(A => N_470, B => N_130, Y => N_302); - - \addr_RNIBANR[3]\ : OR3A - port map(A => N_132, B => N_110, C => \addr[3]_net_1\, Y - => N_320); - - \addr_RNIE4IR6[3]\ : NOR3C - port map(A => N_345, B => \romdata_0_3[21]\, C => N_336, Y - => \romdata_0_8[21]\); - - \addr_0_RNIL5PK1[5]\ : OR3B - port map(A => N_451, B => N_160, C => \addr_0[5]_net_1\, Y - => N_292); - - \addr_RNITT2B_0[9]\ : NOR2 - port map(A => \addr[9]_net_1\, B => \addr[8]_net_1\, Y => - N_500); - - \addr_RNIOFUH2[8]\ : OA1A - port map(A => \romdata_i_a19_5_0[31]\, B => N_436, C => - N_412, Y => \romdata_i_11[31]\); - - \addr_0[3]\ : DFN1 - port map(D => haddr(3), CLK => lclk_c, Q => - \addr_0[3]_net_1\); - - \addr_RNI41382[2]\ : OA1A - port map(A => N_117_i, B => N_469, C => N_250, Y => - \romdata_0_0[3]\); - - \addr_0_RNISHD52[9]\ : AOI1 - port map(A => \addr_0[9]_net_1\, B => N_516, C => N_270, Y - => \romdata_0_0[8]\); - - \addr_0_RNI8AJU[2]\ : NOR2B - port map(A => N_500, B => \romdata_0_a19_0[25]\, Y => - \romdata_0_a19_1[25]\); - - \addr_0_RNI4PM21[5]\ : OR3 - port map(A => N_108, B => \addr_0[5]_net_1\, C => N_507, Y - => N_295); - - \romdata_0_RNO_6[13]\ : OA1 - port map(A => N_438, B => \romdata_0_a19_2_0[13]\, C => - \romdata_0_1[13]\, Y => \romdata_0_2[13]\); - - \addr_RNIHIMCE[3]\ : OR3C - port map(A => \romdata_0_5[1]\, B => \romdata_0_4[1]\, C - => \romdata_0_7[1]\, Y => hrdata_1); - - \addr_RNIHANR[5]\ : OR2 - port map(A => N_437, B => N_430, Y => N_465); - - \addr_RNIGTGC[2]\ : OR2 - port map(A => \addr_0[5]_net_1\, B => \addr[2]_net_1\, Y - => N_122); - - \addr_RNI5P811[2]\ : NOR2A - port map(A => \addr[2]_net_1\, B => N_472, Y => N_514); - - \addr_0_RNIER1P[4]\ : NOR2A - port map(A => \addr_0[4]_net_1\, B => N_430_0, Y => N_484); - - \addr_RNILF7D7[5]\ : NOR3C - port map(A => \romdata_i_8[20]\, B => N_328, C => N_334, Y - => \romdata_i_15[20]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \addr_0_RNIE9OS5[3]\ : NOR3C - port map(A => \romdata_i_6[24]\, B => \romdata_i_5[24]\, C - => N_519, Y => \romdata_i_12[24]\); - - \addr_RNIUJOR1[9]\ : OA1 - port map(A => \addr_0_RNIP9101_1[6]_net_1\, B => N_463, C - => \addr[9]_net_1\, Y => N_306); - - \addr_0_RNIQ7881[2]\ : OR3B - port map(A => \romdata_i_a19_6_0[31]\, B => N_110, C => - N_116, Y => N_419); - - \addr_0_RNI4PM21[3]\ : OR3A - port map(A => \addr_0[3]_net_1\, B => N_109, C => N_470, Y - => N_399); - - \addr_0_RNI1PM21[3]\ : OR2 - port map(A => N_519, B => N_428, Y => N_285); - - \romdata_0_RNO_6[26]\ : NOR3C - port map(A => N_153_i, B => \romdata_0_1[26]\, C => N_286_i, - Y => \romdata_0_5[26]\); - - \addr_RNI2ANR_0[3]\ : NOR2A - port map(A => N_451, B => N_437, Y => - \addr_RNI2ANR_0[3]_net_1\); - - \addr_RNILT2B[5]\ : OR2 - port map(A => \addr[5]_net_1\, B => \addr[4]_net_1\, Y => - N_166); - - \addr_RNIQT2B_1[6]\ : OR2A - port map(A => \addr[8]_net_1\, B => \addr[6]_net_1\, Y => - N_138); - - \addr_RNIBKSO1[8]\ : OA1A - port map(A => \romdata_i_a19_10_0[24]\, B => N_110, C => - N_368, Y => \romdata_i_5[24]\); - - \addr_0_RNIPFUH2[3]\ : NOR2B - port map(A => N_298, B => N_384, Y => \romdata_0_7[25]\); - - \addr_0_RNIP0DC2[5]\ : OA1A - port map(A => \romdata_i_a19_10_0[31]\, B => N_114, C => - N_415, Y => \romdata_i_0[31]\); - - \addr_0_RNIBCGJ[2]\ : OA1A - port map(A => \addr_0[6]_net_1\, B => \addr[7]_net_1\, C - => \addr_0[2]_net_1\, Y => \romdata_0_a19_0[25]\); - - \addr_RNIMU1M2[8]\ : OA1A - port map(A => N_463, B => N_438, C => N_457, Y => - \romdata_0_o19_0_0[5]\); - - \addr_RNIER5M[7]\ : OR2A - port map(A => N_502, B => \addr[7]_net_1\, Y => N_326); - - \addr_RNI1VF3A[6]\ : OR3 - port map(A => N_263, B => \romdata_0_0[5]\, C => N_196, Y - => hrdata_5); - - \addr_RNI0R1P[2]\ : OR2 - port map(A => N_114, B => N_105, Y => N_450); - - \addr_0_RNIR7881[4]\ : OR3A - port map(A => N_481, B => N_110, C => N_428, Y => N_252); - - \addr_RNIT7M91[4]\ : OR3 - port map(A => N_122, B => N_430_0, C => N_445, Y => N_304); - - \addr_RNI7ANR_0[3]\ : NOR2A - port map(A => N_156, B => N_446, Y => N_410); - - \addr_0_RNIJMLG1[6]\ : OR3A - port map(A => \romdata_0_a19_1_0[21]\, B => N_122, C => - N_430_0, Y => N_338); - - \addr_0_RNIDRJN[4]\ : NOR2A - port map(A => \addr_0[4]_net_1\, B => N_469, Y => N_508); - - \addr_0_RNI6A5T[4]\ : OR3 - port map(A => N_126, B => \addr_0[4]_net_1\, C => N_428, Y - => N_376); - - \romdata_0_RNO_0[13]\ : AND2 - port map(A => \romdata_0_7[13]\, B => - \romdata_0_RNO_2[13]_net_1\, Y => \romdata_0_8[13]\); - - \addr_RNIGN6Q3[4]\ : NOR3C - port map(A => N_300, B => N_303, C => N_241, Y => - \romdata_0_1[15]\); - - \addr_0_RNI3A5T[9]\ : OR3B - port map(A => \addr_0[9]_net_1\, B => N_108, C => N_109, Y - => N_360); - - \addr_RNI0P811[8]\ : OR3B - port map(A => N_116, B => \addr[8]_net_1\, C => N_441, Y - => N_414); - - \romdata_0_RNO_4[13]\ : NOR3C - port map(A => N_286_i, B => N_281, C => N_287, Y => - \romdata_0_5[13]\); - - \addr_RNIRO441[9]\ : NOR2 - port map(A => N_490, B => N_450, Y => N_398); - - \addr_RNIPMPD1[4]\ : AO1A - port map(A => \addr[4]_net_1\, B => \addr[6]_net_1\, C => - N_495, Y => \addr_RNIPMPD1[4]_net_1\); - - \addr_RNIONOO3[3]\ : NOR3A - port map(A => N_495, B => N_259, C => N_342, Y => - \romdata_0_7[1]\); - - \addr_0_RNIV1CN4[3]\ : NOR2A - port map(A => N_278, B => N_134, Y => \romdata_0_0[11]\); - - \addr_0_RNIQO441[3]\ : OR3C - port map(A => N_479, B => \romdata_i_a19_4_0[20]\, C => - N_105, Y => N_323); - - \romdata_0_RNO_11[13]\ : OR3B - port map(A => \addr[9]_net_1\, B => N_162_i_i_0, C => N_109, - Y => N_282); - - \addr_0_RNI5RJN[3]\ : OR2A - port map(A => \addr_0[3]_net_1\, B => N_441, Y => N_519); - - \addr_RNI3PM21[3]\ : OR3A - port map(A => \addr[3]_net_1\, B => N_122, C => N_430, Y - => N_495); - - \addr_0_RNIP9101_1[6]\ : NOR2A - port map(A => \addr_0[6]_net_1\, B => N_450, Y => - \addr_0_RNIP9101_1[6]_net_1\); - - \addr_0_RNIETUD[2]\ : NOR2A - port map(A => \addr_0[6]_net_1\, B => \addr_0[2]_net_1\, Y - => \romdata_0_a19_5_0[1]\); - - \addr_0_RNI9A5T[4]\ : OR3A - port map(A => \addr_0[4]_net_1\, B => N_448, C => N_132, Y - => \romdata_0_a19_1[23]\); - - \addr[4]\ : DFN1 - port map(D => haddr(4), CLK => lclk_c, Q => \addr[4]_net_1\); - - \addr_RNIFH982[9]\ : AO1C - port map(A => N_172, B => N_450, C => \addr[9]_net_1\, Y - => N_301); - - \romdata_0_o19_RNIJDSPD[21]\ : OR3C - port map(A => \romdata_0_7[21]\, B => \romdata_0_6[21]\, C - => \romdata_0_8[21]\, Y => hrdata_21); - - \addr_RNI41382[3]\ : OR2B - port map(A => N_455, B => N_454, Y => N_148); - - \addr_RNIECKG[5]\ : NOR2A - port map(A => \addr[5]_net_1\, B => N_107, Y => N_478); - - \addr_RNIDANR[8]\ : NOR2 - port map(A => N_436, B => N_108, Y => N_492); - - \romdata_0_o19[21]\ : NOR2 - port map(A => N_443, B => N_236, Y => N_133_i); - - \addr_0_RNIP7M91[5]\ : OR3 - port map(A => N_507, B => N_105, C => N_135, Y => - \addr_0_RNIP7M91[5]_net_1\); - - \addr[2]\ : DFN1 - port map(D => haddr(2), CLK => lclk_c, Q => \addr[2]_net_1\); - - \addr_RNIJT2B_0[3]\ : OR2A - port map(A => \addr[3]_net_1\, B => \addr[4]_net_1\, Y => - N_116); - - \romdata_0_RNO_9[26]\ : OR2B - port map(A => N_489, B => N_149_i_i_0, Y => N_387); - - \addr_RNIME455[8]\ : NOR3C - port map(A => \romdata_0_0[23]\, B => N_264, C => N_354, Y - => \romdata_0_3[23]\); - - \addr_0_RNIGTUD[4]\ : OR2 - port map(A => \addr_0[6]_net_1\, B => \addr_0[4]_net_1\, Y - => N_151); - - \addr_0_RNI5L584[4]\ : NOR3B - port map(A => N_313, B => \addr_0_RNIP7M91[5]_net_1\, C => - N_302, Y => \romdata_0_2[19]\); - - \addr_RNICD1T2[3]\ : NOR3C - port map(A => N_323, B => N_330, C => N_320, Y => - \romdata_i_6[20]\); - - \addr_0_RNIETUD[5]\ : XNOR2 - port map(A => \addr_0[3]_net_1\, B => \addr_0[5]_net_1\, Y - => N_135); - - \addr_RNIS12J4[4]\ : NOR3C - port map(A => \romdata_0_0[2]\, B => N_253, C => N_249, Y - => \romdata_0_2[2]\); - - \addr_RNI28Q61[2]\ : NOR2 - port map(A => N_465, B => N_136_i, Y => N_525); - - \addr_RNI33EU1[7]\ : AO1D - port map(A => \romdata_0_a19_0_0[30]\, B => N_442, C => - N_410, Y => \romdata_0_0[30]\); - - \addr_RNI6R5M[2]\ : NOR2 - port map(A => N_131, B => N_107, Y => N_463); - - \addr_0_RNI6S043[4]\ : NOR3B - port map(A => N_403, B => N_402, C => N_508, Y => - \romdata_0_1[28]\); - - \addr_RNI3VJ0A[5]\ : NOR3C - port map(A => \romdata_0_3[0]\, B => \romdata_0_2[0]\, C - => \romdata_0_4[0]\, Y => \romdata_0_6[0]\); - - \addr_RNISMBC1_3[8]\ : NOR2A - port map(A => N_516, B => N_436, Y => N_439); - - \romdata_0_RNO_8[26]\ : OR3 - port map(A => N_114, B => N_428, C => N_109, Y => N_393); - - \addr_RNISMBC1[5]\ : OR2A - port map(A => N_492, B => N_446, Y => N_255); - - \addr_RNIJT2B[2]\ : OR2B - port map(A => \addr[5]_net_1\, B => \addr[2]_net_1\, Y => - N_131); - - \addr_RNIKR5M[4]\ : NOR2 - port map(A => \addr[4]_net_1\, B => N_430, Y => N_512); - - \addr_RNISMBC1[4]\ : OR2A - port map(A => N_525, B => \addr[4]_net_1\, Y => N_266); - - \addr_RNI6CGJ[2]\ : OR2 - port map(A => \addr[2]_net_1\, B => N_114, Y => N_471); - - \addr_0_RNISFGG2[4]\ : OA1 - port map(A => N_156, B => \romdata_0_a19_1[23]\, C => N_252, - Y => \romdata_0_0[23]\); - - \addr_RNI2ANR[5]\ : OR2 - port map(A => N_446, B => N_107, Y => N_452); - - \addr_0_RNIRNSL3[3]\ : OR3 - port map(A => N_270, B => N_439, C => N_262, Y => - \romdata_0_0[5]\); - - \addr_0_RNITS0GA[9]\ : NOR3C - port map(A => \romdata_0_4[23]\, B => \romdata_0_3[23]\, C - => N_316, Y => \romdata_0_7[23]\); - - \addr_0_RNIUOM21[2]\ : OR3C - port map(A => N_110, B => \addr_0[2]_net_1\, C => N_459, Y - => N_234); - - \addr_0_RNIIC2I[4]\ : ZOR3I - port map(A => \addr[7]_net_1\, B => \addr[8]_net_1\, C => - \addr_0[4]_net_1\, Y => \addr_0_RNIIC2I[4]_net_1\); - - \addr_0_RNIDVA55[4]\ : OR3C - port map(A => N_310, B => N_440, C => N_277, Y => hrdata_10); - - \addr_0_RNI4AOS5[6]\ : NOR3C - port map(A => N_299, B => \romdata_0_1[14]\, C => N_298, Y - => \romdata_0_4[14]\); - - \addr_RNIPMPD1[3]\ : OR2A - port map(A => N_127, B => N_495, Y => N_257); - - \addr_0_RNIO74B1[6]\ : OR2B - port map(A => \romdata_0_a19_0[21]\, B => N_484, Y => N_336); - - \addr_RNINT2B[4]\ : NOR2B - port map(A => \addr[7]_net_1\, B => \addr[4]_net_1\, Y => - N_499); - - \addr_RNIBCKG[3]\ : OR2 - port map(A => \addr[3]_net_1\, B => N_105, Y => N_143); - - \addr_0_RNIP8PH3[2]\ : OA1C - port map(A => \romdata_0_a19_5_0[1]\, B => N_472, C => - N_240, Y => \romdata_0_5[1]\); - - \addr_0_RNIU7881[4]\ : OR2B - port map(A => \romdata_0_a19_2_0[28]\, B => - \romdata_0_a19_2_1[28]\, Y => N_403); - - \addr_RNIPMPD1_1[3]\ : OR2A - port map(A => N_485, B => N_116, Y => N_345); - - \addr_RNI18Q61[2]\ : NOR2A - port map(A => N_511, B => N_124, Y => N_262); - - \addr_RNIU7Q61[2]\ : OR3 - port map(A => N_107, B => N_428, C => N_441, Y => N_260); - - \romdata_0_RNO_10[26]\ : OR3A - port map(A => N_114, B => \addr[2]_net_1\, C => N_507, Y - => N_388); - - \addr_RNIHT2B[2]\ : XOR2 - port map(A => \addr[3]_net_1\, B => \addr[2]_net_1\, Y => - N_136_i); - - \addr_RNI0T5EK[8]\ : NOR3C - port map(A => \romdata_i_12[31]\, B => \romdata_i_11[31]\, - C => \romdata_i_15[31]\, Y => N_103_i_0); - - \romdata_0_a19_5_RNO[14]\ : AND2 - port map(A => \addr_0[6]_net_1\, B => \addr_0[2]_net_1\, Y - => \romdata_0_a19_5_0[14]\); - - \addr_RNI48Q61_1[5]\ : OR2A - port map(A => N_492, B => N_110, Y => N_298); - - \addr_RNISMBC1_2[8]\ : OR2 - port map(A => N_473, B => N_436, Y => N_258); - - \addr_RNIGTGC[4]\ : XNOR2 - port map(A => \addr_0[3]_net_1\, B => \addr[4]_net_1\, Y - => N_112); - - \addr_RNIQT2B_0[6]\ : OR2B - port map(A => \addr[8]_net_1\, B => \addr[6]_net_1\, Y => - N_449); - - \addr_RNINT2B_1[5]\ : OR2 - port map(A => \addr[6]_net_1\, B => \addr[5]_net_1\, Y => - N_448); - - \addr_RNIQCKG[9]\ : OR3B - port map(A => \addr[7]_net_1\, B => \addr[8]_net_1\, C => - \addr[9]_net_1\, Y => N_430); - - \addr_0_RNIP74B1[9]\ : OR3A - port map(A => N_109, B => N_114, C => N_430_0, Y => N_374); - - \romdata_0_RNO_1[26]\ : OR2A - port map(A => \addr[3]_net_1\, B => N_465, Y => - \romdata_0_RNO_1[26]_net_1\); - - \addr_0_RNIR7881[5]\ : OR3 - port map(A => N_107, B => N_428, C => N_442, Y => N_253); - - \addr_0_RNII2G82[9]\ : OA1 - port map(A => N_127, B => \romdata_0_a19_1_0[17]\, C => - \addr_0_RNIQ9T21[9]_net_1\, Y => \romdata_0_0[17]\); - - \addr_0_RNI8C2I[4]\ : NOR2B - port map(A => \addr_0[4]_net_1\, B => N_124, Y => - \romdata_0_a19_2_0[28]\); - - \addr[6]\ : DFN1 - port map(D => haddr(6), CLK => lclk_c, Q => \addr[6]_net_1\); - - \addr_0_RNIP7M91[9]\ : NOR2 - port map(A => \romdata_0_a19_5_0[21]\, B => N_505, Y => - N_342); - - \addr_0_RNI7CUK[6]\ : NOR2A - port map(A => \addr_0[6]_net_1\, B => N_114, Y => - \romdata_i_a19_11_0[31]\); - - \addr_0_RNIGM3I1[3]\ : NOR3A - port map(A => N_484, B => N_442, C => \addr_0[3]_net_1\, Y - => N_279); - - \addr_RNISMBC1[6]\ : OR2A - port map(A => N_494, B => N_106_i, Y => N_267); - - \addr_RNIAIH22[6]\ : AO1 - port map(A => N_433, B => N_432, C => N_131, Y => N_440); - - \addr_RNICQPA3[9]\ : NOR3 - port map(A => N_236, B => N_443, C => N_497, Y => N_197_i); - - \addr_0_RNI1AJU[4]\ : OR3 - port map(A => \addr_0[4]_net_1\, B => \addr[8]_net_1\, C - => N_442, Y => N_377); - - \addr_RNI1P811[9]\ : OR2B - port map(A => N_493, B => N_108, Y => N_375); - - \addr_0_RNIDTUD[2]\ : NOR2A - port map(A => \addr_0[5]_net_1\, B => \addr_0[2]_net_1\, Y - => \romdata_i_a19_0_0[24]\); - - \addr_0_RNIAC2I[6]\ : NOR2 - port map(A => \addr_0[6]_net_1\, B => N_136_i, Y => - \romdata_0_a19_0[21]\); - - \addr[3]\ : DFN1 - port map(D => haddr(3), CLK => lclk_c, Q => \addr[3]_net_1\); - - \addr_RNIMM7F1_0[6]\ : AOI1B - port map(A => \romdata_i_a19_1_1[24]\, B => N_131, C => - N_363, Y => \romdata_i_0[24]\); - - \addr_RNI18Q61[8]\ : OR3 - port map(A => N_109, B => N_116, C => N_436, Y => N_354); - - \addr_RNI48Q61_0[5]\ : NOR3 - port map(A => N_107, B => N_437, C => N_438, Y => N_236); - - \addr_0_RNIUFUH2[5]\ : OA1A - port map(A => N_479, B => N_472, C => N_304, Y => - \romdata_0_6[15]\); - - \addr_RNIPCKG[9]\ : OR2 - port map(A => \addr[9]_net_1\, B => N_138, Y => N_507); - - \addr_RNIMM7F1[6]\ : NOR2A - port map(A => N_515, B => \addr[6]_net_1\, Y => N_263); - - \addr_0_RNI1IR62[4]\ : OA1A - port map(A => \romdata_0_a19_1[25]\, B => N_108, C => N_376, - Y => \romdata_0_0[25]\); - - \addr_RNIPMPD1_0[3]\ : NOR3 - port map(A => N_110, B => N_143, C => N_430_0, Y => N_461); - - \addr_RNIOEDK7[8]\ : NOR3C - port map(A => N_414, B => \romdata_i_4[31]\, C => - \romdata_i_8[31]\, Y => \romdata_i_12[31]\); - - \addr_0_RNIPMPD1_0[9]\ : OR2 - port map(A => N_473, B => N_430_0, Y => N_268); - - \addr_0_RNI01VA2[2]\ : NOR3C - port map(A => N_319, B => \addr_RNIGR5M[3]_net_1\, C => - \addr_RNIER5M_0[9]_net_1\, Y => \romdata_i_2[20]\); - - \addr_RNI3A5T[7]\ : OR2B - port map(A => N_481, B => N_480, Y => N_368); - - \addr_0_RNITF2F2[9]\ : OA1A - port map(A => \romdata_0_a19_0[29]\, B => N_436, C => N_397, - Y => \romdata_0_1[29]\); - - \addr_0_RNIGC2I[2]\ : NOR2B - port map(A => \addr_0[2]_net_1\, B => N_468, Y => - \romdata_i_a19_6_0[31]\); - - \addr_RNIJPHG3[6]\ : NOR3C - port map(A => \romdata_i_8[24]\, B => N_364, C => N_369, Y - => \romdata_i_14[24]\); - - \addr_RNIMM7F1[2]\ : OR3B - port map(A => N_136_i, B => N_484, C => N_448, Y => N_274); - - \addr_0_RNIUL4J6[9]\ : OR3C - port map(A => N_273, B => \romdata_0_0[8]\, C => - \romdata_0_1[8]\, Y => hrdata_8); - - \addr_RNI11DC2[5]\ : OA1A - port map(A => N_509, B => N_471, C => N_243, Y => - \romdata_0_6[23]\); - - \addr_0_RNI3QPA3[2]\ : NOR3C - port map(A => N_235, B => N_234, C => N_238, Y => - \romdata_0_4[0]\); - - \addr_RNIER5M_0[6]\ : OR2A - port map(A => N_459, B => \addr[6]_net_1\, Y => N_432); - - \addr_RNICR5M[3]\ : NOR2A - port map(A => N_156, B => N_109, Y => N_460); - - \addr_0_RNI08881[5]\ : OR3A - port map(A => N_479, B => N_105, C => N_438, Y => N_352); - - \addr_0_RNITO441[5]\ : OR2B - port map(A => \romdata_i_a19_15_0[24]\, B => N_481, Y => - N_371); - - \addr_RNI7AFD8[9]\ : OR3B - port map(A => N_310, B => N_440, C => \romdata_0_1[18]\, Y - => hrdata_18); - - \addr_RNI0P811_0[8]\ : OR2A - port map(A => N_516, B => \addr[8]_net_1\, Y => N_369); - - \addr_RNINT2B[2]\ : NOR2A - port map(A => \addr[9]_net_1\, B => \addr[2]_net_1\, Y => - N_291_1); - - \addr_RNIMM7F1[4]\ : OR3A - port map(A => N_112, B => N_122, C => N_503, Y => - \addr_RNIMM7F1[4]_net_1\); - - \romdata_0_o19_RNIFAQ64[21]\ : AND2 - port map(A => N_133_i, B => \romdata_0_4[21]\, Y => - \romdata_0_6[21]\); - - \addr_RNIMH982[8]\ : OA1A - port map(A => \romdata_i_a19_0[20]\, B => N_471, C => N_329, - Y => \romdata_i_9[20]\); - - \addr_RNI6R5M_0[2]\ : NOR2 - port map(A => N_126, B => N_108, Y => N_256_1); - - \addr_RNISON36[6]\ : AO1D - port map(A => N_450, B => N_16427_tz, C => - \romdata_0_1[22]\, Y => hrdata_22); - - \addr_RNISMBC1_1[8]\ : NOR3 - port map(A => N_116, B => N_441, C => N_470, Y => N_462); - - \addr_RNIMDS2F[4]\ : OR3C - port map(A => \addr_RNIPMPD1[4]_net_1\, B => - \romdata_0_6[0]\, C => N_155_i, Y => hrdata_0); - - \addr_RNI8IH22[5]\ : NOR3C - port map(A => N_326, B => N_324, C => N_327, Y => - \romdata_i_4[20]\); - - \addr_0_RNIS9101[9]\ : OR2A - port map(A => \addr_0[9]_net_1\, B => N_450, Y => N_286_i); - - \addr_RNISMBC1_0[3]\ : NOR3 - port map(A => N_110, B => N_143, C => N_436, Y => N_312); - - \addr_RNIIDJR2[6]\ : AOI1B - port map(A => N_494, B => N_138, C => N_271, Y => - \romdata_0_1[8]\); - - \addr_RNI1P811[3]\ : OR3A - port map(A => N_117_i, B => N_469, C => \addr[3]_net_1\, Y - => N_454); - - \addr_0_RNI66K24[9]\ : NOR3C - port map(A => N_362, B => N_323, C => \romdata_i_0[31]\, Y - => \romdata_i_4[31]\); - - \romdata_0_RNO_7[13]\ : OR2A - port map(A => N_492, B => N_131, Y => N_290); - - \addr_RNIIT2B_0[2]\ : OR2 - port map(A => \addr[4]_net_1\, B => \addr[2]_net_1\, Y => - N_105); - - \addr_RNI6ANR[9]\ : OR2A - port map(A => N_459, B => N_109, Y => N_341); - - \addr_RNI2A5T[3]\ : OR3A - port map(A => \addr[7]_net_1\, B => N_442, C => - \addr[3]_net_1\, Y => N_367); - - \romdata_0_a19_5_RNIULR7H[14]\ : OR3B - port map(A => \romdata_0_5[14]\, B => \romdata_0_8[14]\, C - => N_185, Y => hrdata_14); - - \addr_RNI7R5M[3]\ : NOR2 - port map(A => N_109, B => N_108, Y => - \addr_RNI7R5M[3]_net_1\); - - \addr_0_RNIFDJR2[4]\ : NOR3C - port map(A => \addr_0_RNI1PM21[4]_net_1\, B => N_332, C => - N_331, Y => \romdata_i_11[20]\); - - \romdata_0_RNO_8[13]\ : OR2A - port map(A => N_170, B => N_430, Y => N_281); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_bootloader is - - port( haddr : in std_logic_vector(9 downto 2); - hrdata_26 : out std_logic; - hrdata_13 : out std_logic; - hrdata_8 : out std_logic; - hrdata_5 : out std_logic; - hrdata_29 : out std_logic; - hrdata_18 : out std_logic; - hrdata_6 : out std_logic; - hrdata_19 : out std_logic; - hrdata_17 : out std_logic; - hrdata_7 : out std_logic; - hrdata_16 : out std_logic; - hrdata_30 : out std_logic; - hrdata_9 : out std_logic; - hrdata_25 : out std_logic; - hrdata_27 : out std_logic; - hrdata_21 : out std_logic; - hrdata_3 : out std_logic; - hrdata_0 : out std_logic; - hrdata_1 : out std_logic; - hrdata_23 : out std_logic; - hrdata_4 : out std_logic; - hrdata_28 : out std_logic; - hrdata_14 : out std_logic; - hrdata_22 : out std_logic; - hrdata_15 : out std_logic; - hrdata_2 : out std_logic; - hrdata_11 : out std_logic; - hrdata_10 : out std_logic; - hrdata_12 : out std_logic; - prdata : out std_logic_vector(31 downto 0); - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - pwdata_1_0 : in std_logic; - pwdata_31 : in std_logic; - pwdata_30 : in std_logic; - pwdata_29 : in std_logic; - pwdata_28 : in std_logic; - pwdata_27 : in std_logic; - pwdata_26 : in std_logic; - pwdata_25 : in std_logic; - pwdata_24 : in std_logic; - pwdata_23 : in std_logic; - pwdata_22 : in std_logic; - pwdata_21 : in std_logic; - pwdata_20 : in std_logic; - pwdata_19 : in std_logic; - pwdata_18 : in std_logic; - pwdata_17 : in std_logic; - pwdata_16 : in std_logic; - pwdata_15 : in std_logic; - pwdata_14 : in std_logic; - pwdata_13 : in std_logic; - pwdata_12 : in std_logic; - pwdata_11 : in std_logic; - pwdata_10 : in std_logic; - pwdata_9 : in std_logic; - pwdata_8 : in std_logic; - pwdata_7 : in std_logic; - pwdata_6 : in std_logic; - pwdata_5 : in std_logic; - pwdata_2 : in std_logic; - pwdata_0 : in std_logic; - N_103_i_0 : out std_logic; - N_90_i_0 : out std_logic; - N_95_i_0 : out std_logic; - rstraw_c : in std_logic; - lclk_c : in std_logic; - rdata60_4 : in std_logic; - N_6459 : in std_logic; - rdata59_4 : in std_logic; - readdata55_3 : in std_logic; - rdata62_3 : in std_logic; - N_750 : in std_logic; - un1_apbi_0 : in std_logic; - rdata60_4_0 : in std_logic; - N_796 : in std_logic - ); - -end lpp_bootloader; - -architecture DEF_ARCH of lpp_bootloader is - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component ahbrom - port( hrdata_12 : out std_logic; - hrdata_10 : out std_logic; - hrdata_11 : out std_logic; - hrdata_2 : out std_logic; - hrdata_15 : out std_logic; - hrdata_22 : out std_logic; - hrdata_14 : out std_logic; - hrdata_28 : out std_logic; - hrdata_4 : out std_logic; - hrdata_23 : out std_logic; - hrdata_1 : out std_logic; - hrdata_0 : out std_logic; - hrdata_3 : out std_logic; - hrdata_21 : out std_logic; - hrdata_27 : out std_logic; - hrdata_25 : out std_logic; - hrdata_9 : out std_logic; - hrdata_30 : out std_logic; - hrdata_16 : out std_logic; - hrdata_7 : out std_logic; - hrdata_17 : out std_logic; - hrdata_19 : out std_logic; - hrdata_6 : out std_logic; - hrdata_18 : out std_logic; - hrdata_29 : out std_logic; - hrdata_5 : out std_logic; - hrdata_8 : out std_logic; - hrdata_13 : out std_logic; - hrdata_26 : out std_logic; - haddr : in std_logic_vector(9 downto 2) := (others => 'U'); - N_95_i_0 : out std_logic; - N_90_i_0 : out std_logic; - N_103_i_0 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1E1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_6452_0, config_start_execution_1_sqmuxa_0_a2_0_0, - addr_start_execution_1_sqmuxa_0, N_6452, - config_wait_on_boot_0_sqmuxa, N_6440, config_wait_on_boot, - N_6441, config_start_execution, \prdata_8[0]\, N_6442, - addr_start_execution_1_sqmuxa, - config_start_execution_1_sqmuxa, \prdata_8[1]\, - \addr_start_execution[1]\, \prdata_8[2]\, - \addr_start_execution[2]\, \prdata_8[3]\, - \addr_start_execution[3]\, \prdata_8[4]\, - \addr_start_execution[4]\, \prdata_8[5]\, - \addr_start_execution[5]\, \prdata_8[6]\, - \addr_start_execution[6]\, \prdata_8[7]\, - \addr_start_execution[7]\, \prdata_8[8]\, - \addr_start_execution[8]\, \prdata_8[9]\, - \addr_start_execution[9]\, \prdata_8[10]\, - \addr_start_execution[10]\, \prdata_8[11]\, - \addr_start_execution[11]\, \prdata_8[12]\, - \addr_start_execution[12]\, \prdata_8[13]\, - \addr_start_execution[13]\, \prdata_8[14]\, - \addr_start_execution[14]\, \prdata_8[16]\, - \addr_start_execution[16]\, \prdata_8[17]\, - \addr_start_execution[17]\, \prdata_8[18]\, - \addr_start_execution[18]\, \prdata_8[19]\, - \addr_start_execution[19]\, \prdata_8[20]\, - \addr_start_execution[20]\, \prdata_8[21]\, - \addr_start_execution[21]\, \prdata_8[22]\, - \addr_start_execution[22]\, \prdata_8[23]\, - \addr_start_execution[23]\, \prdata_8[24]\, - \addr_start_execution[24]\, \prdata_8[25]\, - \addr_start_execution[25]\, \prdata_8[26]\, - \addr_start_execution[26]\, \prdata_8[27]\, - \addr_start_execution[27]\, \prdata_8[28]\, - \addr_start_execution[28]\, \prdata_8[29]\, - \addr_start_execution[29]\, \prdata_8[30]\, - \addr_start_execution[30]\, \prdata_8[31]\, - \addr_start_execution[31]\, \prdata_8[15]\, - \addr_start_execution[15]\, \addr_start_execution[0]\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : ahbrom - Use entity work.ahbrom(DEF_ARCH); -begin - - - \prdata_RNO[30]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[30]\, C - => rdata60_4, Y => \prdata_8[30]\); - - \prdata_RNO[7]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[7]\, C - => rdata60_4_0, Y => \prdata_8[7]\); - - \prdata_RNO[16]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[16]\, C - => rdata60_4_0, Y => \prdata_8[16]\); - - \prdata_RNO[6]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[6]\, C - => rdata60_4_0, Y => \prdata_8[6]\); - - \reg.addr_start_execution[1]\ : DFN1E1C0 - port map(D => pwdata_1_0, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[1]\); - - \prdata_RNO[24]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[24]\, C - => rdata60_4, Y => \prdata_8[24]\); - - \reg.addr_start_execution[23]\ : DFN1E1C0 - port map(D => pwdata_23, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[23]\); - - \prdata[29]\ : DFN1C0 - port map(D => \prdata_8[29]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(29)); - - \prdata[14]\ : DFN1C0 - port map(D => \prdata_8[14]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(14)); - - \reg.config_start_execution_RNO\ : NOR2A - port map(A => N_6452_0, B => N_6459, Y => - config_start_execution_1_sqmuxa); - - \reg.addr_start_execution[20]\ : DFN1E1C0 - port map(D => pwdata_20, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[20]\); - - \reg.addr_start_execution[29]\ : DFN1E1C0 - port map(D => pwdata_29, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[29]\); - - \reg.addr_start_execution[28]\ : DFN1E1C0 - port map(D => pwdata_28, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[28]\); - - \prdata_RNO[3]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[3]\, C - => rdata60_4_0, Y => \prdata_8[3]\); - - \prdata[4]\ : DFN1C0 - port map(D => \prdata_8[4]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(4)); - - \prdata_RNO[27]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[27]\, C - => rdata60_4, Y => \prdata_8[27]\); - - ahbrom_1 : ahbrom - port map(hrdata_12 => hrdata_12, hrdata_10 => hrdata_10, - hrdata_11 => hrdata_11, hrdata_2 => hrdata_2, hrdata_15 - => hrdata_15, hrdata_22 => hrdata_22, hrdata_14 => - hrdata_14, hrdata_28 => hrdata_28, hrdata_4 => hrdata_4, - hrdata_23 => hrdata_23, hrdata_1 => hrdata_1, hrdata_0 - => hrdata_0, hrdata_3 => hrdata_3, hrdata_21 => - hrdata_21, hrdata_27 => hrdata_27, hrdata_25 => hrdata_25, - hrdata_9 => hrdata_9, hrdata_30 => hrdata_30, hrdata_16 - => hrdata_16, hrdata_7 => hrdata_7, hrdata_17 => - hrdata_17, hrdata_19 => hrdata_19, hrdata_6 => hrdata_6, - hrdata_18 => hrdata_18, hrdata_29 => hrdata_29, hrdata_5 - => hrdata_5, hrdata_8 => hrdata_8, hrdata_13 => - hrdata_13, hrdata_26 => hrdata_26, haddr(9) => haddr(9), - haddr(8) => haddr(8), haddr(7) => haddr(7), haddr(6) => - haddr(6), haddr(5) => haddr(5), haddr(4) => haddr(4), - haddr(3) => haddr(3), haddr(2) => haddr(2), N_95_i_0 => - N_95_i_0, N_90_i_0 => N_90_i_0, N_103_i_0 => N_103_i_0, - lclk_c => lclk_c); - - \reg.config_wait_on_boot_RNO\ : NOR3A - port map(A => N_6452_0, B => un1_apbi_0, C => readdata55_3, - Y => config_wait_on_boot_0_sqmuxa); - - \prdata_RNO[15]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[15]\, C - => rdata60_4, Y => \prdata_8[15]\); - - \reg.addr_start_execution[25]\ : DFN1E1C0 - port map(D => pwdata_25, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[25]\); - - \prdata_RNO[19]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[19]\, C - => rdata60_4, Y => \prdata_8[19]\); - - \prdata[25]\ : DFN1C0 - port map(D => \prdata_8[25]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(25)); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg.addr_start_execution[26]\ : DFN1E1C0 - port map(D => pwdata_26, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[26]\); - - \prdata[10]\ : DFN1C0 - port map(D => \prdata_8[10]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(10)); - - \prdata_RNO[11]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[11]\, C - => rdata60_4_0, Y => \prdata_8[11]\); - - \prdata[2]\ : DFN1C0 - port map(D => \prdata_8[2]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(2)); - - \prdata_RNO[28]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[28]\, C - => rdata60_4, Y => \prdata_8[28]\); - - \reg.addr_start_execution[11]\ : DFN1E1C0 - port map(D => pwdata_11, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[11]\); - - \prdata[31]\ : DFN1C0 - port map(D => \prdata_8[31]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(31)); - - \reg.addr_start_execution[2]\ : DFN1E1C0 - port map(D => pwdata_2, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[2]\); - - \prdata[1]\ : DFN1C0 - port map(D => \prdata_8[1]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(1)); - - \prdata_RNO[4]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[4]\, C - => rdata60_4_0, Y => \prdata_8[4]\); - - \reg.addr_start_execution[9]\ : DFN1E1C0 - port map(D => pwdata_9, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[9]\); - - \prdata[8]\ : DFN1C0 - port map(D => \prdata_8[8]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(8)); - - \reg.addr_start_execution[31]\ : DFN1E1C0 - port map(D => pwdata_31, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[31]\); - - \reg.addr_start_execution[14]\ : DFN1E1C0 - port map(D => pwdata_14, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[14]\); - - \prdata_RNO[2]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[2]\, C - => rdata60_4_0, Y => \prdata_8[2]\); - - \prdata_RNO[10]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[10]\, C - => rdata60_4_0, Y => \prdata_8[10]\); - - \prdata[12]\ : DFN1C0 - port map(D => \prdata_8[12]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(12)); - - \prdata_RNO_2[0]\ : OR3B - port map(A => N_6452, B => \addr_start_execution[0]\, C => - rdata60_4, Y => N_6442); - - \prdata_RNO[12]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[12]\, C - => rdata60_4_0, Y => \prdata_8[12]\); - - \reg.config_start_execution_1_sqmuxa_0_a2_0_RNIS3CH_0\ : - NOR3A - port map(A => N_6452_0, B => rdata60_4_0, C => un1_apbi_0, - Y => addr_start_execution_1_sqmuxa_0); - - \prdata[27]\ : DFN1C0 - port map(D => \prdata_8[27]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(27)); - - \prdata_RNO[13]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[13]\, C - => rdata60_4_0, Y => \prdata_8[13]\); - - \reg.addr_start_execution[8]\ : DFN1E1C0 - port map(D => pwdata_8, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[8]\); - - \reg.addr_start_execution[17]\ : DFN1E1C0 - port map(D => pwdata_17, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[17]\); - - \prdata[19]\ : DFN1C0 - port map(D => \prdata_8[19]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(19)); - - \prdata_RNO[9]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[9]\, C - => rdata60_4_0, Y => \prdata_8[9]\); - - \reg.addr_start_execution[5]\ : DFN1E1C0 - port map(D => pwdata_5, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[5]\); - - \prdata_RNO[1]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[1]\, C - => rdata60_4_0, Y => \prdata_8[1]\); - - \prdata[23]\ : DFN1C0 - port map(D => \prdata_8[23]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(23)); - - \reg.addr_start_execution[6]\ : DFN1E1C0 - port map(D => pwdata_6, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[6]\); - - \prdata_RNO[26]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[26]\, C - => rdata60_4, Y => \prdata_8[26]\); - - \prdata[5]\ : DFN1C0 - port map(D => \prdata_8[5]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(5)); - - \reg.config_start_execution_1_sqmuxa_0_a2_0\ : NOR2 - port map(A => N_796, B => - config_start_execution_1_sqmuxa_0_a2_0_0, Y => N_6452); - - \prdata[26]\ : DFN1C0 - port map(D => \prdata_8[26]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(26)); - - \reg.addr_start_execution[3]\ : DFN1E1C0 - port map(D => pwdata_1_2, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[3]\); - - \prdata_RNO[8]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[8]\, C - => rdata60_4_0, Y => \prdata_8[8]\); - - \reg.addr_start_execution[12]\ : DFN1E1C0 - port map(D => pwdata_12, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[12]\); - - \prdata[30]\ : DFN1C0 - port map(D => \prdata_8[30]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(30)); - - \prdata[15]\ : DFN1C0 - port map(D => \prdata_8[15]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(15)); - - GND_i : GND - port map(Y => \GND\); - - \reg.addr_start_execution[7]\ : DFN1E1C0 - port map(D => pwdata_7, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[7]\); - - \prdata[0]\ : DFN1C0 - port map(D => \prdata_8[0]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(0)); - - \prdata[3]\ : DFN1C0 - port map(D => \prdata_8[3]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(3)); - - \prdata[28]\ : DFN1C0 - port map(D => \prdata_8[28]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(28)); - - \reg.addr_start_execution[21]\ : DFN1E1C0 - port map(D => pwdata_21, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[21]\); - - \prdata_RNO[14]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[14]\, C - => rdata60_4_0, Y => \prdata_8[14]\); - - \reg.config_wait_on_boot\ : DFN1E1P0 - port map(D => pwdata_0, CLK => lclk_c, PRE => rstraw_c, E - => config_wait_on_boot_0_sqmuxa, Q => - config_wait_on_boot); - - \reg.config_start_execution_1_sqmuxa_0_a2_0_0\ : OR2 - port map(A => N_750, B => rdata62_3, Y => - config_start_execution_1_sqmuxa_0_a2_0_0); - - \prdata_RNO[25]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[25]\, C - => rdata60_4, Y => \prdata_8[25]\); - - \prdata_RNO[29]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[29]\, C - => rdata60_4, Y => \prdata_8[29]\); - - \prdata[21]\ : DFN1C0 - port map(D => \prdata_8[21]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(21)); - - \prdata_RNO[21]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[21]\, C - => rdata60_4, Y => \prdata_8[21]\); - - \reg.addr_start_execution[24]\ : DFN1E1C0 - port map(D => pwdata_24, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[24]\); - - \reg.addr_start_execution[13]\ : DFN1E1C0 - port map(D => pwdata_13, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[13]\); - - \prdata[17]\ : DFN1C0 - port map(D => \prdata_8[17]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(17)); - - \reg.config_start_execution_1_sqmuxa_0_a2_0_1_RNIS3CH\ : - NOR3A - port map(A => N_6452_0, B => rdata60_4_0, C => un1_apbi_0, - Y => addr_start_execution_1_sqmuxa); - - \reg.config_start_execution_1_sqmuxa_0_a2_0_1\ : NOR2 - port map(A => N_796, B => - config_start_execution_1_sqmuxa_0_a2_0_0, Y => N_6452_0); - - \reg.addr_start_execution[10]\ : DFN1E1C0 - port map(D => pwdata_10, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[10]\); - - \prdata_RNO[17]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[17]\, C - => rdata60_4_0, Y => \prdata_8[17]\); - - \reg.addr_start_execution[19]\ : DFN1E1C0 - port map(D => pwdata_19, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[19]\); - - \reg.addr_start_execution[18]\ : DFN1E1C0 - port map(D => pwdata_18, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[18]\); - - \prdata_RNO[5]\ : NOR3B - port map(A => N_6452_0, B => \addr_start_execution[5]\, C - => rdata60_4_0, Y => \prdata_8[5]\); - - \prdata[24]\ : DFN1C0 - port map(D => \prdata_8[24]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(24)); - - \prdata_RNO[20]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[20]\, C - => rdata60_4, Y => \prdata_8[20]\); - - \reg.addr_start_execution[27]\ : DFN1E1C0 - port map(D => pwdata_27, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[27]\); - - \prdata[9]\ : DFN1C0 - port map(D => \prdata_8[9]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(9)); - - \prdata_RNO[22]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[22]\, C - => rdata60_4, Y => \prdata_8[22]\); - - \prdata[6]\ : DFN1C0 - port map(D => \prdata_8[6]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(6)); - - \prdata[13]\ : DFN1C0 - port map(D => \prdata_8[13]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(13)); - - \reg.config_start_execution\ : DFN1E1C0 - port map(D => pwdata_0, CLK => lclk_c, CLR => rstraw_c, E - => config_start_execution_1_sqmuxa, Q => - config_start_execution); - - \prdata_RNO_1[0]\ : OR3B - port map(A => N_6452_0, B => config_wait_on_boot, C => - readdata55_3, Y => N_6440); - - \reg.addr_start_execution[30]\ : DFN1E1P0 - port map(D => pwdata_30, CLK => lclk_c, PRE => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[30]\); - - \prdata[16]\ : DFN1C0 - port map(D => \prdata_8[16]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(16)); - - \prdata_RNO[23]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[23]\, C - => rdata60_4, Y => \prdata_8[23]\); - - \prdata_RNO[18]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[18]\, C - => rdata60_4, Y => \prdata_8[18]\); - - \reg.addr_start_execution[15]\ : DFN1E1C0 - port map(D => pwdata_15, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[15]\); - - \reg.addr_start_execution[16]\ : DFN1E1C0 - port map(D => pwdata_16, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[16]\); - - \reg.addr_start_execution[22]\ : DFN1E1C0 - port map(D => pwdata_22, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[22]\); - - \prdata_RNO_0[0]\ : OR3C - port map(A => N_6452_0, B => config_start_execution, C => - rdata59_4, Y => N_6441); - - \prdata[20]\ : DFN1C0 - port map(D => \prdata_8[20]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(20)); - - \prdata_RNO[31]\ : NOR3B - port map(A => N_6452, B => \addr_start_execution[31]\, C - => rdata60_4, Y => \prdata_8[31]\); - - \reg.addr_start_execution[0]\ : DFN1E1C0 - port map(D => pwdata_0, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa_0, Q => - \addr_start_execution[0]\); - - \prdata_RNO[0]\ : OR3C - port map(A => N_6441, B => N_6440, C => N_6442, Y => - \prdata_8[0]\); - - \prdata[7]\ : DFN1C0 - port map(D => \prdata_8[7]\, CLK => lclk_c, CLR => rstraw_c, - Q => prdata(7)); - - \prdata[18]\ : DFN1C0 - port map(D => \prdata_8[18]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(18)); - - \reg.addr_start_execution[4]\ : DFN1E1C0 - port map(D => pwdata_1_3, CLK => lclk_c, CLR => rstraw_c, E - => addr_start_execution_1_sqmuxa, Q => - \addr_start_execution[4]\); - - \prdata[11]\ : DFN1C0 - port map(D => \prdata_8[11]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(11)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \prdata[22]\ : DFN1C0 - port map(D => \prdata_8[22]\, CLK => lclk_c, CLR => - rstraw_c, Q => prdata(22)); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_apbreg is - - port( status_full_ack : out std_logic_vector(3 downto 0); - prdata : out std_logic_vector(31 downto 0); - pirq : out std_logic_vector(15 to 15); - pwdata : in std_logic_vector(31 downto 0); - pwdata_1_0 : in std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - paddr_2 : in std_logic_vector(2 to 2); - addr_data_f2 : out std_logic_vector(31 downto 0); - status_new_err_0 : in std_logic_vector(3 downto 0); - status_full_err_0 : in std_logic_vector(3 downto 0); - status_full_0 : in std_logic_vector(3 downto 0); - addr_data_f3 : out std_logic_vector(31 downto 0); - addr_data_f1 : out std_logic_vector(31 downto 0); - nb_burst_available : out std_logic_vector(10 downto 0); - addr_data_f0 : out std_logic_vector(31 downto 0); - nb_snapshot_param : out std_logic_vector(10 downto 0); - delta_snapshot : out std_logic_vector(15 downto 0); - delta_f2_f0 : out std_logic_vector(9 downto 0); - delta_f2_f1 : out std_logic_vector(9 downto 0); - paddr : in std_logic_vector(7 downto 3); - paddr_0 : in std_logic_vector(4 downto 2); - pwdata_0 : in std_logic_vector(11 downto 0); - data_shaping_R0 : out std_logic; - data_shaping_R1 : out std_logic; - un1_apbi_0 : in std_logic; - N_6455 : in std_logic; - rdata61_2 : in std_logic; - burst_f2 : out std_logic; - burst_f0 : out std_logic; - N_232_1 : in std_logic; - enable_f3 : out std_logic; - enable_f2 : out std_logic; - data_shaping_SP1 : out std_logic; - enable_f1 : out std_logic; - N_232_0 : in std_logic; - enable_f0 : out std_logic; - N_769 : in std_logic; - N_116 : in std_logic; - N_749 : in std_logic; - burst_f1 : out std_logic; - data_shaping_SP0 : out std_logic; - Bias_Fails_c : out std_logic; - N_6455_0 : in std_logic; - N_232 : in std_logic; - data_shaping_R1_0 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - data_shaping_R0_0 : out std_logic - ); - -end lpp_top_apbreg; - -architecture DEF_ARCH of lpp_top_apbreg is - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal data_shaping_BW_1_sqmuxa, addr_data_f2_1_sqmuxa_0, - N_168, N_162, prdata_2_sqmuxa_0, N_159, N_69, - prdata_3_sqmuxa_0, prdata_4_sqmuxa_0, - addr_matrix_f1_1_sqmuxa_0_a2_1_0, prdata_5_sqmuxa_0, - prdata_9_sqmuxa_0, N_72, prdata_10_sqmuxa_0, - prdata_12_sqmuxa_0, addr_matrix_f0_0_1_sqmuxa_0, N_71, - addr_matrix_f0_1_1_sqmuxa_0, N_166, - addr_matrix_f1_1_sqmuxa_0, addr_matrix_f2_1_sqmuxa_0, - N_160, addr_data_f0_1_sqmuxa_0, N_168_0, - addr_data_f3_1_sqmuxa_0, addr_data_f1_1_sqmuxa_0, - \delta_f2_f1_m_i[2]\, prdata_15_sqmuxa, - \delta_f2_f0_m_i[2]\, prdata_16_sqmuxa, - \delta_snapshot_m_i[6]\, prdata_14_sqmuxa, - \delta_snapshot_m_i[15]\, \prdata_39_0_iv_2[15]\, - \prdata_39_0_iv_1[15]\, \prdata_39_0_iv_0[15]\, - \prdata_39_0_iv_0[2]\, \prdata_39_0_iv_9[6]\, - \prdata_39_0_iv_6[6]\, \prdata_39_0_iv_4[6]\, - \prdata_39_0_iv_3[6]\, \prdata_39_0_iv_4[15]\, - \prdata_39_0_iv_15[0]\, \addr_data_f1_m_i[0]\, - \addr_data_f0_m_i[0]\, \prdata_39_0_iv_12[0]\, - \prdata_39_0_iv_7[0]\, \prdata_39_0_iv_6[0]\, - \delta_snapshot_m_i[0]\, \prdata_39_0_iv_11[0]\, - \prdata_39_0_iv_5[0]\, \prdata_39_0_iv_4[0]\, - \addr_data_f3_m_i[0]\, \prdata_39_0_iv_10[0]\, - \status_full[0]\, prdata_13_sqmuxa, \addr_data_f2_m_i[0]\, - \addr_matrix_f0_0[0]\, \addr_matrix_f0_1_m_i[0]\, - \addr_matrix_f2[0]\, enable_f0_m_i, prdata_7_sqmuxa, - \addr_matrix_f1_m_i[0]\, \prdata_39_0_iv_1[0]\, - \prdata_39_0_iv_0[0]\, \prdata_39_0_iv_2[0]\, - prdata_18_sqmuxa, status_ready_matrix_f0_0_m_i, - \nb_burst_available_m_i[0]\, prdata_0_sqmuxa, - config_active_interruption_onNewMatrix, - \delta_f2_f0_m_i[0]\, \prdata_39_0_iv_15[1]\, - \addr_data_f1_m_i[1]\, \addr_data_f0_m_i[1]\, - \prdata_39_0_iv_12[1]\, \prdata_39_0_iv_7[1]\, - \prdata_39_0_iv_6[1]\, \delta_snapshot_m_i[1]\, - \prdata_39_0_iv_11[1]\, \prdata_39_0_iv_5[1]\, - \prdata_39_0_iv_4[1]\, \addr_data_f3_m_i[1]\, - \prdata_39_0_iv_10[1]\, \status_full[1]\, - \addr_data_f2_m_i[1]\, \addr_matrix_f0_0[1]\, - \addr_matrix_f0_1_m_i[1]\, \addr_matrix_f2[1]\, - enable_f1_m_i, \addr_matrix_f1_m_i[1]\, - \prdata_39_0_iv_1[1]\, \prdata_39_0_iv_0[1]\, - \prdata_39_0_iv_2[1]\, status_ready_matrix_f0_1_m_i, - \nb_burst_available_m_i[1]\, - config_active_interruption_onError, \delta_f2_f0_m_i[1]\, - \prdata_39_0_iv_13[2]\, \prdata_39_0_iv_7[2]\, - \addr_data_f3_m_i[2]\, \prdata_39_0_iv_9[2]\, - \prdata_39_0_iv_12[2]\, \addr_data_f1_m_i[2]\, - \prdata_39_0_iv_11[2]\, \prdata_39_0_iv_6[2]\, - \prdata_39_0_iv_5[2]\, \delta_snapshot_m_i[2]\, - \status_full[2]\, \addr_data_f2_m_i[2]\, - \prdata_39_0_iv_2[2]\, \prdata_39_0_iv_1[2]\, - \prdata_39_0_iv_4[2]\, \addr_matrix_f0_0[2]\, - \addr_matrix_f0_1_m_i[2]\, \addr_matrix_f2[2]\, - enable_f2_m_i, data_shaping_SP1_m_i, - \addr_matrix_f1_m_i[2]\, status_ready_matrix_f1, - prdata_1_sqmuxa, prdata_17_sqmuxa, - \nb_snapshot_param_m_i[2]\, \prdata_39_0_iv_13[3]\, - \prdata_39_0_iv_7[3]\, \addr_data_f3_m_i[3]\, - \prdata_39_0_iv_9[3]\, \prdata_39_0_iv_12[3]\, - \addr_data_f1_m_i[3]\, \prdata_39_0_iv_11[3]\, - \prdata_39_0_iv_6[3]\, \prdata_39_0_iv_5[3]\, - \delta_snapshot_m_i[3]\, \status_full[3]\, - \addr_data_f2_m_i[3]\, \prdata_39_0_iv_2[3]\, - \prdata_39_0_iv_1[3]\, \prdata_39_0_iv_4[3]\, - \addr_matrix_f0_0[3]\, \addr_matrix_f0_1_m_i[3]\, - \addr_matrix_f2[3]\, enable_f3_m_i, data_shaping_R0_m_i, - \addr_matrix_f1_m_i[3]\, \delta_f2_f1_m_i[3]\, - \delta_f2_f0_m_i[3]\, status_ready_matrix_f2_m_i, - \nb_snapshot_param_m_i[3]\, \prdata_39_0_iv_13[4]\, - \addr_data_f2_m_i[4]\, \status_full_err_m_i[0]\, - \prdata_39_0_iv_10[4]\, \prdata_39_0_iv_12[4]\, - \addr_data_f1_m_i[4]\, \prdata_39_0_iv_11[4]\, - \prdata_39_0_iv_6[4]\, \prdata_39_0_iv_5[4]\, - \delta_snapshot_m_i[4]\, \prdata_39_0_iv_4[4]\, - \prdata_39_0_iv_3[4]\, \addr_data_f3_m_i[4]\, - \addr_matrix_f0_0[4]\, \addr_matrix_f0_1_m_i[4]\, - \addr_matrix_f2[4]\, burst_f0_m_i, \data_shaping_R1_0\, - \addr_matrix_f1_m_i[4]\, \nb_snapshot_param_m_i[4]\, - \nb_burst_available_m_i[4]\, \prdata_39_0_iv_2[4]\, - status_error_anticipating_empty_fifo_m_i, - \prdata_39_0_iv_0[4]\, \delta_f2_f1_m_i[4]\, - \prdata_39_0_iv_12[5]\, \prdata_39_0_iv_9[5]\, - \prdata_39_0_iv_11[5]\, \status_full_err_m_i[1]\, - \prdata_39_0_iv_6[5]\, \addr_data_f0_m_i[5]\, - \prdata_39_0_iv_10[5]\, \prdata_39_0_iv_5[5]\, - \prdata_39_0_iv_4[5]\, \delta_snapshot_m_i[5]\, - \addr_data_f2_m_i[5]\, \prdata_39_0_iv_2[5]\, - \prdata_39_0_iv_1[5]\, \addr_matrix_f0_1_m_i[5]\, - prdata_8_sqmuxa, \addr_matrix_f0_0_m_i[5]\, - \addr_matrix_f1[5]\, \addr_matrix_f2_m_i[5]\, - status_error_bad_component_error_m_i, - \prdata_39_0_iv_0[5]\, \nb_burst_available_m_i[5]\, - \nb_snapshot_param_m_i[5]\, \delta_f2_f1_m_i[5]\, - \prdata_39_0_iv_11[6]\, \addr_data_f3_m_i[6]\, - \addr_data_f2_m_i[6]\, \addr_data_f1_m_i[6]\, - \prdata_39_0_iv_10[6]\, \status_full_err_m_i[2]\, - \prdata_39_0_iv_5[6]\, \addr_data_f0_m_i[6]\, - \addr_matrix_f0_0[6]\, \addr_matrix_f0_1_m_i[6]\, - \addr_matrix_f2[6]\, burst_f2_m_i, \prdata_39_0_iv_1[6]\, - \prdata_39_0_iv_0[6]\, \addr_matrix_f1_m_i[6]\, - \nb_snapshot_param_m_i[6]\, \delta_f2_f1_m_i[6]\, - \prdata_39_0_iv_10[7]\, \prdata_39_0_iv_7[7]\, - \prdata_39_0_iv_9[7]\, \prdata_39_0_iv_6[7]\, - \prdata_39_0_iv_8[7]\, \prdata_39_0_iv_3[7]\, - \addr_matrix_f0_1_m_i[7]\, \delta_snapshot_m_i[7]\, - \addr_data_f2_m_i[7]\, \addr_matrix_f0_0_m_i[7]\, - \addr_matrix_f2_m_i[7]\, \status_full_err_m_i[3]\, - \prdata_39_0_iv_1[7]\, \prdata_39_0_iv_0[7]\, - \addr_matrix_f1_m_i[7]\, \nb_snapshot_param_m_i[7]\, - \delta_f2_f1_m_i[7]\, \prdata_39_0_iv_10[8]\, - \addr_data_f3_m_i[8]\, \addr_data_f2_m_i[8]\, - \addr_data_f1_m_i[8]\, \prdata_39_0_iv_9[8]\, - \prdata_39_0_iv_6[8]\, \prdata_39_0_iv_8[8]\, - \prdata_39_0_iv_3[8]\, \addr_matrix_f0_1_m_i[8]\, - \delta_snapshot_m_i[8]\, \addr_matrix_f0_0_m_i[8]\, - \addr_matrix_f2_m_i[8]\, \status_new_err_m_i[0]\, - \prdata_39_0_iv_1[8]\, \prdata_39_0_iv_0[8]\, - \addr_matrix_f1_m_i[8]\, \nb_burst_available_m_i[8]\, - \nb_snapshot_param_m_i[8]\, \delta_f2_f0_m_i[8]\, - \prdata_39_0_iv_10[9]\, \addr_data_f3_m_i[9]\, - \addr_data_f2_m_i[9]\, \addr_data_f1_m_i[9]\, - \prdata_39_0_iv_9[9]\, \prdata_39_0_iv_6[9]\, - \prdata_39_0_iv_8[9]\, \prdata_39_0_iv_3[9]\, - \addr_matrix_f0_1_m_i[9]\, \delta_snapshot_m_i[9]\, - \addr_matrix_f0_0_m_i[9]\, \addr_matrix_f2_m_i[9]\, - \status_new_err_m_i[1]\, \prdata_39_0_iv_1[9]\, - \prdata_39_0_iv_0[9]\, \addr_matrix_f1_m_i[9]\, - \nb_snapshot_param_m_i[9]\, \delta_f2_f1_m_i[9]\, - \prdata_39_0_iv_8[10]\, \prdata_39_0_iv_5[10]\, - \prdata_39_0_iv_7[10]\, \prdata_39_0_iv_4[10]\, - \prdata_39_0_iv_6[10]\, \prdata_39_0_iv_1[10]\, - \addr_matrix_f0_1_m_i[10]\, \delta_snapshot_m_i[10]\, - \addr_data_f2_m_i[10]\, \addr_matrix_f0_0_m_i[10]\, - \addr_matrix_f2_m_i[10]\, \status_new_err_m_i[2]\, - \nb_snapshot_param_m_i[10]\, \nb_burst_available_m_i[10]\, - \addr_matrix_f1_m_i[10]\, \prdata_39_0_iv_6[11]\, - \addr_data_f2_m_i[11]\, \status_new_err_m_i[3]\, - \addr_data_f1_m_i[11]\, \prdata_39_0_iv_5[11]\, - \prdata_39_0_iv_1[11]\, \prdata_39_0_iv_0[11]\, - \addr_data_f0_m_i[11]\, \prdata_39_0_iv_4[11]\, - \delta_snapshot_m_i[11]\, \addr_matrix_f0_0[11]\, - \addr_matrix_f0_1_m_i[11]\, \addr_matrix_f1[11]\, - \addr_matrix_f2_m_i[11]\, \prdata_39_0_iv_4[30]\, - \prdata_39_0_iv_1[30]\, \prdata_39_0_iv_0[30]\, - \addr_data_f0_m_i[30]\, \prdata_39_0_iv_3[30]\, - \addr_data_f2_m_i[30]\, \addr_matrix_f0_0[30]\, - \addr_matrix_f0_1_m_i[30]\, \addr_matrix_f1[30]\, - \addr_matrix_f2_m_i[30]\, \prdata_39_0_iv_4[20]\, - \prdata_39_0_iv_1[20]\, \prdata_39_0_iv_0[20]\, - \addr_data_f0_m_i[20]\, \prdata_39_0_iv_3[20]\, - \addr_data_f2_m_i[20]\, \addr_matrix_f0_0[20]\, - \addr_matrix_f0_1_m_i[20]\, \addr_matrix_f1[20]\, - \addr_matrix_f2_m_i[20]\, \prdata_39_0_iv_5[12]\, - \addr_data_f1_m_i[12]\, \prdata_39_0_iv_4[12]\, - \prdata_39_0_iv_1[12]\, \prdata_39_0_iv_0[12]\, - \delta_snapshot_m_i[12]\, \prdata_39_0_iv_3[12]\, - \addr_data_f2_m_i[12]\, \addr_matrix_f0_0[12]\, - \addr_matrix_f0_1_m_i[12]\, \addr_matrix_f1[12]\, - \addr_matrix_f2_m_i[12]\, \prdata_39_0_iv_5[13]\, - \addr_data_f1_m_i[13]\, \prdata_39_0_iv_4[13]\, - \prdata_39_0_iv_1[13]\, \prdata_39_0_iv_0[13]\, - \delta_snapshot_m_i[13]\, \prdata_39_0_iv_3[13]\, - \addr_data_f2_m_i[13]\, \addr_matrix_f0_0[13]\, - \addr_matrix_f0_1_m_i[13]\, \addr_matrix_f1[13]\, - \addr_matrix_f2_m_i[13]\, \prdata_39_0_iv_5[14]\, - \addr_data_f1_m_i[14]\, \prdata_39_0_iv_4[14]\, - \prdata_39_0_iv_1[14]\, \prdata_39_0_iv_0[14]\, - \delta_snapshot_m_i[14]\, \prdata_39_0_iv_3[14]\, - \addr_data_f2_m_i[14]\, \addr_matrix_f0_0[14]\, - \addr_matrix_f0_1_m_i[14]\, \addr_matrix_f1[14]\, - \addr_matrix_f2_m_i[14]\, \prdata_39_0_iv_5[15]\, - \addr_data_f1_m_i[15]\, \prdata_39_0_iv_3[15]\, - \addr_data_f2_m_i[15]\, \addr_matrix_f0_0[15]\, - \addr_matrix_f0_1_m_i[15]\, \addr_matrix_f1[15]\, - \addr_matrix_f2_m_i[15]\, \prdata_39_0_iv_4[16]\, - \prdata_39_0_iv_1[16]\, \prdata_39_0_iv_0[16]\, - \addr_data_f0_m_i[16]\, \prdata_39_0_iv_3[16]\, - \addr_data_f2_m_i[16]\, \addr_matrix_f0_0[16]\, - \addr_matrix_f0_1_m_i[16]\, \addr_matrix_f1[16]\, - \addr_matrix_f2_m_i[16]\, \prdata_39_0_iv_4[17]\, - \prdata_39_0_iv_1[17]\, \prdata_39_0_iv_0[17]\, - \addr_data_f0_m_i[17]\, \prdata_39_0_iv_3[17]\, - \addr_data_f2_m_i[17]\, \addr_matrix_f0_0[17]\, - \addr_matrix_f0_1_m_i[17]\, \addr_matrix_f1[17]\, - \addr_matrix_f2_m_i[17]\, \prdata_39_0_iv_4[18]\, - \prdata_39_0_iv_1[18]\, \prdata_39_0_iv_0[18]\, - \addr_data_f0_m_i[18]\, \prdata_39_0_iv_3[18]\, - \addr_data_f2_m_i[18]\, \addr_matrix_f0_0[18]\, - \addr_matrix_f0_1_m_i[18]\, \addr_matrix_f1[18]\, - \addr_matrix_f2_m_i[18]\, \prdata_39_0_iv_4[19]\, - \prdata_39_0_iv_1[19]\, \prdata_39_0_iv_0[19]\, - \addr_data_f0_m_i[19]\, \prdata_39_0_iv_3[19]\, - \addr_data_f2_m_i[19]\, prdata_2_sqmuxa, - \addr_matrix_f0_0[19]\, \addr_matrix_f0_1_m_i[19]\, - \addr_matrix_f1[19]\, \addr_matrix_f2_m_i[19]\, - \prdata_39_0_iv_4[21]\, \prdata_39_0_iv_1[21]\, - \prdata_39_0_iv_0[21]\, \addr_data_f0_m_i[21]\, - \prdata_39_0_iv_3[21]\, \addr_data_f2_m_i[21]\, - \addr_matrix_f0_0[21]\, \addr_matrix_f0_1_m_i[21]\, - \addr_matrix_f1[21]\, \addr_matrix_f2_m_i[21]\, - \prdata_39_0_iv_4[22]\, \prdata_39_0_iv_1[22]\, - \prdata_39_0_iv_0[22]\, \addr_data_f0_m_i[22]\, - \prdata_39_0_iv_3[22]\, \addr_data_f2_m_i[22]\, - \addr_matrix_f0_0[22]\, \addr_matrix_f0_1_m_i[22]\, - \addr_matrix_f1[22]\, \addr_matrix_f2_m_i[22]\, - \prdata_39_0_iv_4[23]\, \prdata_39_0_iv_1[23]\, - \prdata_39_0_iv_0[23]\, \addr_data_f0_m_i[23]\, - \prdata_39_0_iv_3[23]\, prdata_12_sqmuxa, - \addr_data_f2_m_i[23]\, \addr_matrix_f0_0[23]\, - \addr_matrix_f0_1_m_i[23]\, \addr_matrix_f1[23]\, - \addr_matrix_f2_m_i[23]\, \prdata_39_0_iv_4[24]\, - \prdata_39_0_iv_1[24]\, \prdata_39_0_iv_0[24]\, - \addr_data_f0_m_i[24]\, \prdata_39_0_iv_3[24]\, - \addr_data_f2_m_i[24]\, \addr_matrix_f0_0[24]\, - \addr_matrix_f0_1_m_i[24]\, \addr_matrix_f1[24]\, - \addr_matrix_f2_m_i[24]\, \prdata_39_0_iv_4[25]\, - \prdata_39_0_iv_1[25]\, \prdata_39_0_iv_0[25]\, - \addr_data_f0_m_i[25]\, \prdata_39_0_iv_3[25]\, - \addr_data_f2_m_i[25]\, \addr_matrix_f0_0[25]\, - \addr_matrix_f0_1_m_i[25]\, prdata_4_sqmuxa, - \addr_matrix_f1[25]\, \addr_matrix_f2_m_i[25]\, - \prdata_39_0_iv_4[26]\, \prdata_39_0_iv_1[26]\, - \prdata_39_0_iv_0[26]\, \addr_data_f0_m_i[26]\, - \prdata_39_0_iv_3[26]\, \addr_data_f2_m_i[26]\, - \addr_matrix_f0_0[26]\, \addr_matrix_f0_1_m_i[26]\, - \addr_matrix_f1[26]\, \addr_matrix_f2_m_i[26]\, - \prdata_39_0_iv_4[27]\, \prdata_39_0_iv_1[27]\, - \prdata_39_0_iv_0[27]\, \addr_data_f0_m_i[27]\, - \prdata_39_0_iv_3[27]\, \addr_data_f2_m_i[27]\, - \addr_matrix_f0_0[27]\, \addr_matrix_f0_1_m_i[27]\, - \addr_matrix_f1[27]\, \addr_matrix_f2_m_i[27]\, - \prdata_39_0_iv_4[28]\, \prdata_39_0_iv_1[28]\, - \prdata_39_0_iv_0[28]\, \addr_data_f0_m_i[28]\, - \prdata_39_0_iv_3[28]\, \addr_data_f2_m_i[28]\, - \addr_matrix_f0_0[28]\, \addr_matrix_f0_1_m_i[28]\, - \addr_matrix_f1[28]\, \addr_matrix_f2_m_i[28]\, - \prdata_39_0_iv_4[29]\, \prdata_39_0_iv_1[29]\, - \prdata_39_0_iv_0[29]\, \addr_data_f0_m_i[29]\, - \prdata_39_0_iv_3[29]\, \addr_data_f2_m_i[29]\, - \addr_matrix_f0_0[29]\, \addr_matrix_f0_1_m_i[29]\, - \addr_matrix_f1[29]\, \addr_matrix_f2_m_i[29]\, - \prdata_39_0_iv_4[31]\, \prdata_39_0_iv_1[31]\, - \prdata_39_0_iv_0[31]\, \addr_data_f0_m_i[31]\, - \prdata_39_0_iv_3[31]\, \addr_data_f2_m_i[31]\, - \addr_matrix_f0_0[31]\, \addr_matrix_f0_1_m_i[31]\, - \addr_matrix_f1[31]\, \addr_matrix_f2_m_i[31]\, - \status_full_5_i_a2_0[0]\, \status_full_5_i_a2_0[1]\, - \status_full_5_i_a2_0[2]\, \status_full_5_i_a2_0[3]\, - \status_full_err_5_i_a2_0[0]\, \status_full_err[0]\, - \status_full_err_5_i_a2_0[1]\, \status_full_err[1]\, - \status_full_err_5_i_a2_0[2]\, \status_full_err[2]\, - \status_full_err_5_i_a2_0[3]\, \status_full_err[3]\, - \status_new_err_5_i_a2_0[0]\, \status_new_err[0]\, - \status_new_err_5_i_a2_0[1]\, \status_new_err[1]\, - \status_new_err_5_i_a2_0[2]\, \status_new_err[2]\, - \status_new_err_5_i_a2_0[3]\, \status_new_err[3]\, - config_active_interruption_onError_0_sqmuxa_0_o2_0_0, - \pirq_2_i_a2_8[15]\, \pirq_2_i_a2_5[15]\, - \pirq_2_i_a2_7[15]\, \pirq_2_i_a2_3[15]\, - \pirq_2_i_a2_6[15]\, \pirq_2_i_a2_0[15]\, - \pirq_2_i_a2_1[15]\, N_68, N_1016_i_0, \prdata_39[31]\, - \addr_data_f1_m_i[31]\, \prdata_39[29]\, - \addr_data_f1_m_i[29]\, \prdata_39[28]\, - \addr_data_f1_m_i[28]\, \prdata_39[27]\, - \addr_data_f1_m_i[27]\, \prdata_39[26]\, - \addr_data_f1_m_i[26]\, \prdata_39[25]\, - \addr_data_f1_m_i[25]\, \prdata_39[24]\, - \addr_data_f1_m_i[24]\, \prdata_39[23]\, - \addr_data_f1_m_i[23]\, \prdata_39[22]\, - \addr_data_f1_m_i[22]\, \prdata_39[21]\, - \addr_data_f1_m_i[21]\, \prdata_39[19]\, - \addr_data_f1_m_i[19]\, \prdata_39[18]\, - \addr_data_f1_m_i[18]\, \prdata_39[17]\, - \addr_data_f1_m_i[17]\, \prdata_39[16]\, - \addr_data_f1_m_i[16]\, \prdata_39[15]\, \prdata_39[14]\, - \prdata_39[13]\, \prdata_39[12]\, \prdata_39[11]\, - \prdata_39[10]\, \prdata_39[9]\, \prdata_39[8]\, - \prdata_39[7]\, \prdata_39[6]\, \prdata_39[5]\, - \prdata_39[4]\, \prdata_39[3]\, \prdata_39[2]\, - \prdata_39[1]\, \prdata_39[0]\, \prdata_39[20]\, - \addr_data_f1_m_i[20]\, \prdata_39[30]\, - \addr_data_f1_m_i[30]\, status_ready_matrix_f0_0, - \addr_matrix_f0_1[0]\, \addr_matrix_f1[0]\, - status_ready_matrix_f0_1, \addr_matrix_f0_1[1]\, - \addr_matrix_f1[1]\, \addr_matrix_f0_1[2]\, - \addr_matrix_f1[2]\, status_ready_matrix_f2, - \addr_matrix_f0_1[3]\, \addr_matrix_f1[3]\, - \data_shaping_R0_0\, status_error_anticipating_empty_fifo, - status_error_bad_component_error, \addr_matrix_f0_0[5]\, - \addr_matrix_f0_1[5]\, \addr_matrix_f2[5]\, - \addr_matrix_f0_1[6]\, \addr_matrix_f1[6]\, - \addr_matrix_f0_0[7]\, \addr_matrix_f0_1[7]\, - \addr_matrix_f1[7]\, \addr_matrix_f2[7]\, - \addr_matrix_f0_0[8]\, \addr_matrix_f0_1[8]\, - \addr_matrix_f1[8]\, \addr_matrix_f2[8]\, - \addr_matrix_f0_0[9]\, \addr_matrix_f0_1[9]\, - \addr_matrix_f1[9]\, \addr_matrix_f2[9]\, - \addr_matrix_f0_0[10]\, \addr_matrix_f0_1[10]\, - \addr_matrix_f1[10]\, \addr_matrix_f2[10]\, - \addr_matrix_f0_1[11]\, \addr_matrix_f2[11]\, - \addr_matrix_f0_1[12]\, \addr_matrix_f2[12]\, - \addr_matrix_f0_1[13]\, \addr_matrix_f2[13]\, - \addr_matrix_f0_1[14]\, \addr_matrix_f2[14]\, - \addr_matrix_f0_1[15]\, \addr_matrix_f2[15]\, - \addr_matrix_f0_1[16]\, prdata_5_sqmuxa, - \addr_matrix_f2[16]\, prdata_9_sqmuxa, prdata_10_sqmuxa, - prdata_3_sqmuxa, \addr_matrix_f0_1[17]\, - \addr_matrix_f2[17]\, \addr_matrix_f0_1[18]\, - \addr_matrix_f2[18]\, \addr_matrix_f0_1[19]\, - \addr_matrix_f2[19]\, \addr_matrix_f0_1[21]\, - \addr_matrix_f2[21]\, \addr_matrix_f0_1[22]\, - \addr_matrix_f2[22]\, \addr_matrix_f0_1[23]\, - \addr_matrix_f2[23]\, \addr_matrix_f0_1[24]\, - \addr_matrix_f2[24]\, \addr_matrix_f0_1[25]\, - \addr_matrix_f2[25]\, \addr_matrix_f0_1[26]\, - \addr_matrix_f2[26]\, \addr_matrix_f0_1[27]\, - \addr_matrix_f2[27]\, \addr_matrix_f0_1[28]\, - \addr_matrix_f2[28]\, \addr_matrix_f0_1[29]\, - \addr_matrix_f2[29]\, \addr_matrix_f0_1[31]\, - \addr_matrix_f2[31]\, addr_matrix_f0_0_1_sqmuxa, - addr_matrix_f0_1_1_sqmuxa, addr_matrix_f1_1_sqmuxa, - addr_matrix_f2_1_sqmuxa, - config_active_interruption_onError_0_sqmuxa, - status_error_anticipating_empty_fifo_1_sqmuxa, - addr_data_f0_1_sqmuxa, addr_data_f1_1_sqmuxa, - addr_data_f2_1_sqmuxa, addr_data_f3_1_sqmuxa, - burst_f0_1_sqmuxa, N_163, delta_f2_f0_1_sqmuxa, N_158, - delta_f2_f1_1_sqmuxa, delta_snapshot_1_sqmuxa, - nb_snapshot_param_1_sqmuxa, \status_full_ack_8[3]\, N_74, - \status_full_ack_8[2]\, \status_full_ack_8[1]\, - \status_full_ack_8[0]\, N_43, N_45, N_47, N_49, N_51, - N_53, N_55, N_57, N_59, N_61, N_63, N_65, - nb_burst_available_1_sqmuxa, \addr_matrix_f1[4]\, - \addr_matrix_f0_1[4]\, \addr_matrix_f2[30]\, - \addr_matrix_f0_1[30]\, \addr_matrix_f2[20]\, - \addr_matrix_f0_1[20]\, \enable_f3\, \enable_f2\, - \enable_f1\, \enable_f0\, \data_shaping_SP1\, - \data_shaping_SP0\, \Bias_Fails_c\, \burst_f2\, - \burst_f1\, \burst_f0\, \addr_data_f1[0]\, - \addr_data_f1[1]\, \addr_data_f1[2]\, \addr_data_f1[3]\, - \addr_data_f1[4]\, \addr_data_f1[5]\, \addr_data_f1[6]\, - \addr_data_f1[7]\, \addr_data_f1[8]\, \addr_data_f1[9]\, - \addr_data_f1[10]\, \addr_data_f1[11]\, - \addr_data_f1[12]\, \addr_data_f1[13]\, - \addr_data_f1[14]\, \addr_data_f1[15]\, - \addr_data_f1[16]\, \addr_data_f1[17]\, - \addr_data_f1[18]\, \addr_data_f1[19]\, - \addr_data_f1[20]\, \addr_data_f1[21]\, - \addr_data_f1[22]\, \addr_data_f1[23]\, - \addr_data_f1[24]\, \addr_data_f1[25]\, - \addr_data_f1[26]\, \addr_data_f1[27]\, - \addr_data_f1[28]\, \addr_data_f1[29]\, - \addr_data_f1[30]\, \addr_data_f1[31]\, \addr_data_f0[0]\, - \addr_data_f0[1]\, \addr_data_f0[2]\, \addr_data_f0[3]\, - \addr_data_f0[4]\, \addr_data_f0[5]\, \addr_data_f0[6]\, - \addr_data_f0[7]\, \addr_data_f0[8]\, \addr_data_f0[9]\, - \addr_data_f0[10]\, \addr_data_f0[11]\, - \addr_data_f0[12]\, \addr_data_f0[13]\, - \addr_data_f0[14]\, \addr_data_f0[15]\, - \addr_data_f0[16]\, \addr_data_f0[17]\, - \addr_data_f0[18]\, \addr_data_f0[19]\, - \addr_data_f0[20]\, \addr_data_f0[21]\, - \addr_data_f0[22]\, \addr_data_f0[23]\, - \addr_data_f0[24]\, \addr_data_f0[25]\, - \addr_data_f0[26]\, \addr_data_f0[27]\, - \addr_data_f0[28]\, \addr_data_f0[29]\, - \addr_data_f0[30]\, \addr_data_f0[31]\, - \delta_snapshot[0]\, \delta_snapshot[1]\, - \delta_snapshot[2]\, \delta_snapshot[3]\, - \delta_snapshot[4]\, \delta_snapshot[5]\, - \delta_snapshot[6]\, \delta_snapshot[7]\, - \delta_snapshot[8]\, \delta_snapshot[9]\, - \delta_snapshot[10]\, \delta_snapshot[11]\, - \delta_snapshot[12]\, \delta_snapshot[13]\, - \delta_snapshot[14]\, \delta_snapshot[15]\, - \nb_snapshot_param[0]\, \nb_snapshot_param[1]\, - \nb_snapshot_param[2]\, \nb_snapshot_param[3]\, - \nb_snapshot_param[4]\, \nb_snapshot_param[5]\, - \nb_snapshot_param[6]\, \nb_snapshot_param[7]\, - \nb_snapshot_param[8]\, \nb_snapshot_param[9]\, - \nb_snapshot_param[10]\, \nb_burst_available[0]\, - \nb_burst_available[1]\, \nb_burst_available[2]\, - \nb_burst_available[3]\, \nb_burst_available[4]\, - \nb_burst_available[5]\, \nb_burst_available[6]\, - \nb_burst_available[7]\, \nb_burst_available[8]\, - \nb_burst_available[9]\, \nb_burst_available[10]\, - \delta_f2_f1[0]\, \delta_f2_f1[1]\, \delta_f2_f1[2]\, - \delta_f2_f1[3]\, \delta_f2_f1[4]\, \delta_f2_f1[5]\, - \delta_f2_f1[6]\, \delta_f2_f1[7]\, \delta_f2_f1[8]\, - \delta_f2_f1[9]\, \delta_f2_f0[0]\, \delta_f2_f0[1]\, - \delta_f2_f0[2]\, \delta_f2_f0[3]\, \delta_f2_f0[4]\, - \delta_f2_f0[5]\, \delta_f2_f0[6]\, \delta_f2_f0[7]\, - \delta_f2_f0[8]\, \delta_f2_f0[9]\, \addr_data_f3[0]\, - \addr_data_f3[1]\, \addr_data_f3[2]\, \addr_data_f3[3]\, - \addr_data_f3[4]\, \addr_data_f3[5]\, \addr_data_f3[6]\, - \addr_data_f3[7]\, \addr_data_f3[8]\, \addr_data_f3[9]\, - \addr_data_f3[10]\, \addr_data_f3[11]\, - \addr_data_f3[12]\, \addr_data_f3[13]\, - \addr_data_f3[14]\, \addr_data_f3[15]\, - \addr_data_f3[16]\, \addr_data_f3[17]\, - \addr_data_f3[18]\, \addr_data_f3[19]\, - \addr_data_f3[20]\, \addr_data_f3[21]\, - \addr_data_f3[22]\, \addr_data_f3[23]\, - \addr_data_f3[24]\, \addr_data_f3[25]\, - \addr_data_f3[26]\, \addr_data_f3[27]\, - \addr_data_f3[28]\, \addr_data_f3[29]\, - \addr_data_f3[30]\, \addr_data_f3[31]\, \addr_data_f2[0]\, - \addr_data_f2[1]\, \addr_data_f2[2]\, \addr_data_f2[3]\, - \addr_data_f2[4]\, \addr_data_f2[5]\, \addr_data_f2[6]\, - \addr_data_f2[7]\, \addr_data_f2[8]\, \addr_data_f2[9]\, - \addr_data_f2[10]\, \addr_data_f2[11]\, - \addr_data_f2[12]\, \addr_data_f2[13]\, - \addr_data_f2[14]\, \addr_data_f2[15]\, - \addr_data_f2[16]\, \addr_data_f2[17]\, - \addr_data_f2[18]\, \addr_data_f2[19]\, - \addr_data_f2[20]\, \addr_data_f2[21]\, - \addr_data_f2[22]\, \addr_data_f2[23]\, - \addr_data_f2[24]\, \addr_data_f2[25]\, - \addr_data_f2[26]\, \addr_data_f2[27]\, - \addr_data_f2[28]\, \addr_data_f2[29]\, - \addr_data_f2[30]\, \addr_data_f2[31]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - addr_data_f2(31) <= \addr_data_f2[31]\; - addr_data_f2(30) <= \addr_data_f2[30]\; - addr_data_f2(29) <= \addr_data_f2[29]\; - addr_data_f2(28) <= \addr_data_f2[28]\; - addr_data_f2(27) <= \addr_data_f2[27]\; - addr_data_f2(26) <= \addr_data_f2[26]\; - addr_data_f2(25) <= \addr_data_f2[25]\; - addr_data_f2(24) <= \addr_data_f2[24]\; - addr_data_f2(23) <= \addr_data_f2[23]\; - addr_data_f2(22) <= \addr_data_f2[22]\; - addr_data_f2(21) <= \addr_data_f2[21]\; - addr_data_f2(20) <= \addr_data_f2[20]\; - addr_data_f2(19) <= \addr_data_f2[19]\; - addr_data_f2(18) <= \addr_data_f2[18]\; - addr_data_f2(17) <= \addr_data_f2[17]\; - addr_data_f2(16) <= \addr_data_f2[16]\; - addr_data_f2(15) <= \addr_data_f2[15]\; - addr_data_f2(14) <= \addr_data_f2[14]\; - addr_data_f2(13) <= \addr_data_f2[13]\; - addr_data_f2(12) <= \addr_data_f2[12]\; - addr_data_f2(11) <= \addr_data_f2[11]\; - addr_data_f2(10) <= \addr_data_f2[10]\; - addr_data_f2(9) <= \addr_data_f2[9]\; - addr_data_f2(8) <= \addr_data_f2[8]\; - addr_data_f2(7) <= \addr_data_f2[7]\; - addr_data_f2(6) <= \addr_data_f2[6]\; - addr_data_f2(5) <= \addr_data_f2[5]\; - addr_data_f2(4) <= \addr_data_f2[4]\; - addr_data_f2(3) <= \addr_data_f2[3]\; - addr_data_f2(2) <= \addr_data_f2[2]\; - addr_data_f2(1) <= \addr_data_f2[1]\; - addr_data_f2(0) <= \addr_data_f2[0]\; - addr_data_f3(31) <= \addr_data_f3[31]\; - addr_data_f3(30) <= \addr_data_f3[30]\; - addr_data_f3(29) <= \addr_data_f3[29]\; - addr_data_f3(28) <= \addr_data_f3[28]\; - addr_data_f3(27) <= \addr_data_f3[27]\; - addr_data_f3(26) <= \addr_data_f3[26]\; - addr_data_f3(25) <= \addr_data_f3[25]\; - addr_data_f3(24) <= \addr_data_f3[24]\; - addr_data_f3(23) <= \addr_data_f3[23]\; - addr_data_f3(22) <= \addr_data_f3[22]\; - addr_data_f3(21) <= \addr_data_f3[21]\; - addr_data_f3(20) <= \addr_data_f3[20]\; - addr_data_f3(19) <= \addr_data_f3[19]\; - addr_data_f3(18) <= \addr_data_f3[18]\; - addr_data_f3(17) <= \addr_data_f3[17]\; - addr_data_f3(16) <= \addr_data_f3[16]\; - addr_data_f3(15) <= \addr_data_f3[15]\; - addr_data_f3(14) <= \addr_data_f3[14]\; - addr_data_f3(13) <= \addr_data_f3[13]\; - addr_data_f3(12) <= \addr_data_f3[12]\; - addr_data_f3(11) <= \addr_data_f3[11]\; - addr_data_f3(10) <= \addr_data_f3[10]\; - addr_data_f3(9) <= \addr_data_f3[9]\; - addr_data_f3(8) <= \addr_data_f3[8]\; - addr_data_f3(7) <= \addr_data_f3[7]\; - addr_data_f3(6) <= \addr_data_f3[6]\; - addr_data_f3(5) <= \addr_data_f3[5]\; - addr_data_f3(4) <= \addr_data_f3[4]\; - addr_data_f3(3) <= \addr_data_f3[3]\; - addr_data_f3(2) <= \addr_data_f3[2]\; - addr_data_f3(1) <= \addr_data_f3[1]\; - addr_data_f3(0) <= \addr_data_f3[0]\; - addr_data_f1(31) <= \addr_data_f1[31]\; - addr_data_f1(30) <= \addr_data_f1[30]\; - addr_data_f1(29) <= \addr_data_f1[29]\; - addr_data_f1(28) <= \addr_data_f1[28]\; - addr_data_f1(27) <= \addr_data_f1[27]\; - addr_data_f1(26) <= \addr_data_f1[26]\; - addr_data_f1(25) <= \addr_data_f1[25]\; - addr_data_f1(24) <= \addr_data_f1[24]\; - addr_data_f1(23) <= \addr_data_f1[23]\; - addr_data_f1(22) <= \addr_data_f1[22]\; - addr_data_f1(21) <= \addr_data_f1[21]\; - addr_data_f1(20) <= \addr_data_f1[20]\; - addr_data_f1(19) <= \addr_data_f1[19]\; - addr_data_f1(18) <= \addr_data_f1[18]\; - addr_data_f1(17) <= \addr_data_f1[17]\; - addr_data_f1(16) <= \addr_data_f1[16]\; - addr_data_f1(15) <= \addr_data_f1[15]\; - addr_data_f1(14) <= \addr_data_f1[14]\; - addr_data_f1(13) <= \addr_data_f1[13]\; - addr_data_f1(12) <= \addr_data_f1[12]\; - addr_data_f1(11) <= \addr_data_f1[11]\; - addr_data_f1(10) <= \addr_data_f1[10]\; - addr_data_f1(9) <= \addr_data_f1[9]\; - addr_data_f1(8) <= \addr_data_f1[8]\; - addr_data_f1(7) <= \addr_data_f1[7]\; - addr_data_f1(6) <= \addr_data_f1[6]\; - addr_data_f1(5) <= \addr_data_f1[5]\; - addr_data_f1(4) <= \addr_data_f1[4]\; - addr_data_f1(3) <= \addr_data_f1[3]\; - addr_data_f1(2) <= \addr_data_f1[2]\; - addr_data_f1(1) <= \addr_data_f1[1]\; - addr_data_f1(0) <= \addr_data_f1[0]\; - nb_burst_available(10) <= \nb_burst_available[10]\; - nb_burst_available(9) <= \nb_burst_available[9]\; - nb_burst_available(8) <= \nb_burst_available[8]\; - nb_burst_available(7) <= \nb_burst_available[7]\; - nb_burst_available(6) <= \nb_burst_available[6]\; - nb_burst_available(5) <= \nb_burst_available[5]\; - nb_burst_available(4) <= \nb_burst_available[4]\; - nb_burst_available(3) <= \nb_burst_available[3]\; - nb_burst_available(2) <= \nb_burst_available[2]\; - nb_burst_available(1) <= \nb_burst_available[1]\; - nb_burst_available(0) <= \nb_burst_available[0]\; - addr_data_f0(31) <= \addr_data_f0[31]\; - addr_data_f0(30) <= \addr_data_f0[30]\; - addr_data_f0(29) <= \addr_data_f0[29]\; - addr_data_f0(28) <= \addr_data_f0[28]\; - addr_data_f0(27) <= \addr_data_f0[27]\; - addr_data_f0(26) <= \addr_data_f0[26]\; - addr_data_f0(25) <= \addr_data_f0[25]\; - addr_data_f0(24) <= \addr_data_f0[24]\; - addr_data_f0(23) <= \addr_data_f0[23]\; - addr_data_f0(22) <= \addr_data_f0[22]\; - addr_data_f0(21) <= \addr_data_f0[21]\; - addr_data_f0(20) <= \addr_data_f0[20]\; - addr_data_f0(19) <= \addr_data_f0[19]\; - addr_data_f0(18) <= \addr_data_f0[18]\; - addr_data_f0(17) <= \addr_data_f0[17]\; - addr_data_f0(16) <= \addr_data_f0[16]\; - addr_data_f0(15) <= \addr_data_f0[15]\; - addr_data_f0(14) <= \addr_data_f0[14]\; - addr_data_f0(13) <= \addr_data_f0[13]\; - addr_data_f0(12) <= \addr_data_f0[12]\; - addr_data_f0(11) <= \addr_data_f0[11]\; - addr_data_f0(10) <= \addr_data_f0[10]\; - addr_data_f0(9) <= \addr_data_f0[9]\; - addr_data_f0(8) <= \addr_data_f0[8]\; - addr_data_f0(7) <= \addr_data_f0[7]\; - addr_data_f0(6) <= \addr_data_f0[6]\; - addr_data_f0(5) <= \addr_data_f0[5]\; - addr_data_f0(4) <= \addr_data_f0[4]\; - addr_data_f0(3) <= \addr_data_f0[3]\; - addr_data_f0(2) <= \addr_data_f0[2]\; - addr_data_f0(1) <= \addr_data_f0[1]\; - addr_data_f0(0) <= \addr_data_f0[0]\; - nb_snapshot_param(10) <= \nb_snapshot_param[10]\; - nb_snapshot_param(9) <= \nb_snapshot_param[9]\; - nb_snapshot_param(8) <= \nb_snapshot_param[8]\; - nb_snapshot_param(7) <= \nb_snapshot_param[7]\; - nb_snapshot_param(6) <= \nb_snapshot_param[6]\; - nb_snapshot_param(5) <= \nb_snapshot_param[5]\; - nb_snapshot_param(4) <= \nb_snapshot_param[4]\; - nb_snapshot_param(3) <= \nb_snapshot_param[3]\; - nb_snapshot_param(2) <= \nb_snapshot_param[2]\; - nb_snapshot_param(1) <= \nb_snapshot_param[1]\; - nb_snapshot_param(0) <= \nb_snapshot_param[0]\; - delta_snapshot(15) <= \delta_snapshot[15]\; - delta_snapshot(14) <= \delta_snapshot[14]\; - delta_snapshot(13) <= \delta_snapshot[13]\; - delta_snapshot(12) <= \delta_snapshot[12]\; - delta_snapshot(11) <= \delta_snapshot[11]\; - delta_snapshot(10) <= \delta_snapshot[10]\; - delta_snapshot(9) <= \delta_snapshot[9]\; - delta_snapshot(8) <= \delta_snapshot[8]\; - delta_snapshot(7) <= \delta_snapshot[7]\; - delta_snapshot(6) <= \delta_snapshot[6]\; - delta_snapshot(5) <= \delta_snapshot[5]\; - delta_snapshot(4) <= \delta_snapshot[4]\; - delta_snapshot(3) <= \delta_snapshot[3]\; - delta_snapshot(2) <= \delta_snapshot[2]\; - delta_snapshot(1) <= \delta_snapshot[1]\; - delta_snapshot(0) <= \delta_snapshot[0]\; - delta_f2_f0(9) <= \delta_f2_f0[9]\; - delta_f2_f0(8) <= \delta_f2_f0[8]\; - delta_f2_f0(7) <= \delta_f2_f0[7]\; - delta_f2_f0(6) <= \delta_f2_f0[6]\; - delta_f2_f0(5) <= \delta_f2_f0[5]\; - delta_f2_f0(4) <= \delta_f2_f0[4]\; - delta_f2_f0(3) <= \delta_f2_f0[3]\; - delta_f2_f0(2) <= \delta_f2_f0[2]\; - delta_f2_f0(1) <= \delta_f2_f0[1]\; - delta_f2_f0(0) <= \delta_f2_f0[0]\; - delta_f2_f1(9) <= \delta_f2_f1[9]\; - delta_f2_f1(8) <= \delta_f2_f1[8]\; - delta_f2_f1(7) <= \delta_f2_f1[7]\; - delta_f2_f1(6) <= \delta_f2_f1[6]\; - delta_f2_f1(5) <= \delta_f2_f1[5]\; - delta_f2_f1(4) <= \delta_f2_f1[4]\; - delta_f2_f1(3) <= \delta_f2_f1[3]\; - delta_f2_f1(2) <= \delta_f2_f1[2]\; - delta_f2_f1(1) <= \delta_f2_f1[1]\; - delta_f2_f1(0) <= \delta_f2_f1[0]\; - burst_f2 <= \burst_f2\; - burst_f0 <= \burst_f0\; - enable_f3 <= \enable_f3\; - enable_f2 <= \enable_f2\; - data_shaping_SP1 <= \data_shaping_SP1\; - enable_f1 <= \enable_f1\; - enable_f0 <= \enable_f0\; - burst_f1 <= \burst_f1\; - data_shaping_SP0 <= \data_shaping_SP0\; - Bias_Fails_c <= \Bias_Fails_c\; - data_shaping_R1_0 <= \data_shaping_R1_0\; - data_shaping_R0_0 <= \data_shaping_R0_0\; - - \prdata_RNO_7[29]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[29]\, - Y => \addr_matrix_f0_1_m_i[29]\); - - \reg_wp.addr_data_f3[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[17]\); - - \reg_wp.delta_f2_f1[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[1]\); - - \reg_sp.addr_matrix_f1[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[6]\); - - \prdata_RNO_5[14]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[14]\, - Y => \delta_snapshot_m_i[14]\); - - \prdata_RNO_2[14]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[14]\, C - => \addr_data_f1_m_i[14]\, Y => \prdata_39_0_iv_5[14]\); - - \reg_sp.addr_matrix_f0_0[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[2]\); - - \reg_wp.addr_data_f3[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[25]\); - - \prdata_RNO_0[8]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[8]\, C - => \prdata_39_0_iv_6[8]\, Y => \prdata_39_0_iv_9[8]\); - - \reg_wp.addr_data_f3[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[26]\); - - \reg_wp.nb_snapshot_param[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[2]\); - - \reg_wp.delta_f2_f0[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[2]\); - - \reg_wp.addr_data_f3_1_sqmuxa_0_a2\ : NOR2B - port map(A => N_168, B => N_160, Y => addr_data_f3_1_sqmuxa); - - \prdata_RNO_5[7]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[7]\, - Y => \addr_matrix_f0_1_m_i[7]\); - - \reg_wp.addr_data_f2[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[29]\); - - prdata_18_sqmuxa_0_a2 : NOR3C - port map(A => N_158, B => N_159, C => paddr_2(2), Y => - prdata_18_sqmuxa); - - \reg_sp.addr_matrix_f0_1[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[22]\); - - \prdata_RNO_7[3]\ : NOR3C - port map(A => \prdata_39_0_iv_2[3]\, B => - \prdata_39_0_iv_1[3]\, C => \prdata_39_0_iv_4[3]\, Y => - \prdata_39_0_iv_7[3]\); - - \prdata_RNO_8[28]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[28]\, Y - => \addr_matrix_f2_m_i[28]\); - - \prdata_RNO_6[1]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[1]\, C => N_232_0, - Y => \addr_data_f2_m_i[1]\); - - \prdata_RNO_4[29]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[29]\, - C => \addr_matrix_f0_1_m_i[29]\, Y => - \prdata_39_0_iv_1[29]\); - - \reg_wp.nb_snapshot_param[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[9]\); - - \reg_wp.nb_burst_available[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[7]\); - - \prdata_RNO[8]\ : OR3C - port map(A => \prdata_39_0_iv_9[8]\, B => - \prdata_39_0_iv_8[8]\, C => \prdata_39_0_iv_10[8]\, Y => - \prdata_39[8]\); - - \prdata_RNO_1[13]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[13]\, - C => \addr_data_f2_m_i[13]\, Y => \prdata_39_0_iv_3[13]\); - - \prdata_RNO_6[18]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[18]\, Y - => \addr_data_f0_m_i[18]\); - - \prdata[26]\ : DFN1C0 - port map(D => \prdata_39[26]\, CLK => lclk_c, CLR => rstn, - Q => prdata(26)); - - \prdata_RNO_19[0]\ : OR2B - port map(A => status_ready_matrix_f0_0, B => - prdata_1_sqmuxa, Y => status_ready_matrix_f0_0_m_i); - - \reg_sp.addr_matrix_f0_0[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[4]\); - - \prdata_RNO_0[29]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[29]\, C - => \addr_data_f2_m_i[29]\, Y => \prdata_39_0_iv_3[29]\); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2_2\ : NOR2B - port map(A => N_68, B => paddr(6), Y => N_158); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_1_0\ : OR2A - port map(A => paddr_0(4), B => paddr(5), Y => - addr_matrix_f1_1_sqmuxa_0_a2_1_0); - - \reg_wp.addr_data_f0_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_71, B => paddr_0(4), C => N_72, Y => - addr_data_f0_1_sqmuxa); - - \prdata_RNO_7[10]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[10]\, - C => \addr_data_f2_m_i[10]\, Y => \prdata_39_0_iv_5[10]\); - - \reg_wp.addr_data_f2[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[13]\); - - \reg_wp.addr_data_f2[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[10]\); - - \reg_sp.addr_matrix_f0_1[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[2]\); - - \reg_wp.addr_data_f3[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[2]\); - - \reg_wp.addr_data_f3_1_sqmuxa_0_a2_0\ : NOR2B - port map(A => N_168_0, B => N_160, Y => - addr_data_f3_1_sqmuxa_0); - - \reg_sp.addr_matrix_f0_1[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[1]\); - - \prdata_RNO_11[1]\ : AOI1B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[1]\, C - => \nb_burst_available_m_i[1]\, Y => - \prdata_39_0_iv_1[1]\); - - \apbo.pirq_RNO_4[15]\ : NOR2 - port map(A => status_new_err_0(0), B => status_new_err_0(1), - Y => \pirq_2_i_a2_0[15]\); - - \prdata_RNO_4[14]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[14]\, - C => \addr_matrix_f2_m_i[14]\, Y => - \prdata_39_0_iv_0[14]\); - - \reg_sp.addr_matrix_f0_0[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[31]\); - - \prdata_RNO_13[6]\ : NOR3C - port map(A => \prdata_39_0_iv_1[6]\, B => - \prdata_39_0_iv_0[6]\, C => \addr_matrix_f1_m_i[6]\, Y - => \prdata_39_0_iv_3[6]\); - - \prdata_RNO_16[6]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[6]\, C - => \delta_f2_f1_m_i[6]\, Y => \prdata_39_0_iv_0[6]\); - - \reg_sp.addr_matrix_f0_1[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[19]\); - - \reg_sp.status_ready_matrix_f2\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f2); - - \prdata_RNO_6[20]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[20]\, Y - => \addr_data_f0_m_i[20]\); - - \reg_wp.addr_data_f0[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[8]\); - - \prdata_RNO_6[4]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[4]\, Y - => \delta_snapshot_m_i[4]\); - - \prdata_RNO_6[31]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[31]\, Y - => \addr_data_f0_m_i[31]\); - - \apbo.pirq_RNO_0[15]\ : NOR3A - port map(A => \pirq_2_i_a2_3[15]\, B => - status_full_err_0(1), C => status_full_err_0(0), Y => - \pirq_2_i_a2_7[15]\); - - \reg_sp.addr_matrix_f0_1[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[9]\); - - \prdata_RNO_3[6]\ : OR2B - port map(A => \status_full_err[2]\, B => prdata_13_sqmuxa, - Y => \status_full_err_m_i[2]\); - - \prdata_RNO_18[1]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[1]\, Y - => \delta_f2_f0_m_i[1]\); - - \reg_wp.delta_snapshot_1_sqmuxa_0_o2_0\ : OR3B - port map(A => paddr(5), B => paddr(3), C => N_69, Y => N_72); - - \reg_sp.addr_matrix_f0_0[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[24]\); - - \prdata_RNO_11[10]\ : OR2B - port map(A => \nb_snapshot_param[10]\, B => - prdata_18_sqmuxa, Y => \nb_snapshot_param_m_i[10]\); - - \reg_wp.addr_data_f2[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[11]\); - - \reg_sp.addr_matrix_f0_0[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[25]\); - - \reg_sp.addr_matrix_f0_0[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[16]\); - - \prdata_RNO_9[6]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[6]\, C => N_232_1, - Y => \addr_data_f2_m_i[6]\); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2_0\ : NOR2A - port map(A => paddr_2(2), B => un1_apbi_0, Y => N_166); - - \prdata_RNO_9[7]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[7]\, - Y => \addr_matrix_f2_m_i[7]\); - - \prdata_RNO_8[0]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[0]\, Y - => \addr_data_f0_m_i[0]\); - - \prdata_RNO_16[9]\ : OR2B - port map(A => \nb_snapshot_param[9]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[9]\); - - \prdata_RNO[7]\ : OR3C - port map(A => \prdata_39_0_iv_9[7]\, B => - \prdata_39_0_iv_8[7]\, C => \prdata_39_0_iv_10[7]\, Y => - \prdata_39[7]\); - - \prdata_RNO_5[13]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[13]\, - Y => \delta_snapshot_m_i[13]\); - - \prdata_RNO_2[13]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[13]\, C - => \addr_data_f1_m_i[13]\, Y => \prdata_39_0_iv_5[13]\); - - prdata_16_sqmuxa_0_a2 : NOR3A - port map(A => N_158, B => rdata61_2, C => N_6455, Y => - prdata_16_sqmuxa); - - \prdata_RNO_7[1]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[1]\, Y - => \addr_data_f1_m_i[1]\); - - \reg_wp.addr_data_f3[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[5]\); - - \prdata_RNO_9[15]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[15]\, Y => \addr_matrix_f0_1_m_i[15]\); - - \prdata_RNO_7[25]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[25]\, - Y => \addr_matrix_f0_1_m_i[25]\); - - \prdata_RNO_10[2]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[2]\, - Y => \addr_matrix_f0_1_m_i[2]\); - - \reg_wp.addr_data_f3[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[22]\); - - \reg_wp.status_new_err_RNO_0[3]\ : OR2 - port map(A => \status_new_err[3]\, B => status_new_err_0(3), - Y => \status_new_err_5_i_a2_0[3]\); - - \prdata_RNO_8[27]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[27]\, Y - => \addr_matrix_f2_m_i[27]\); - - \reg_sp.addr_matrix_f0_1[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[4]\); - - \reg_wp.burst_f2\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \burst_f2\); - - \reg_sp.addr_matrix_f1[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[0]\); - - \prdata_RNO_11[7]\ : AOI1B - port map(A => \nb_burst_available[7]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[7]\, Y => - \prdata_39_0_iv_1[7]\); - - \reg_wp.status_full_err[3]\ : DFN1C0 - port map(D => N_57, CLK => lclk_c, CLR => rstn, Q => - \status_full_err[3]\); - - \prdata_RNO_20[1]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[1]\, - Y => \addr_matrix_f0_1_m_i[1]\); - - \prdata_RNO_19[4]\ : OR2B - port map(A => status_error_anticipating_empty_fifo, B => - prdata_1_sqmuxa, Y => - status_error_anticipating_empty_fifo_m_i); - - \prdata_RNO_2[24]\ : NOR3C - port map(A => \prdata_39_0_iv_1[24]\, B => - \prdata_39_0_iv_0[24]\, C => \addr_data_f0_m_i[24]\, Y - => \prdata_39_0_iv_4[24]\); - - \prdata_RNO_8[4]\ : OR2B - port map(A => \status_full_err[0]\, B => prdata_13_sqmuxa, - Y => \status_full_err_m_i[0]\); - - \prdata_RNO[18]\ : OR3C - port map(A => \prdata_39_0_iv_3[18]\, B => - \addr_data_f1_m_i[18]\, C => \prdata_39_0_iv_4[18]\, Y - => \prdata_39[18]\); - - \status_full_ack[1]\ : DFN1C0 - port map(D => \status_full_ack_8[1]\, CLK => lclk_c, CLR - => rstn, Q => status_full_ack(1)); - - \prdata_RNO_1[30]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[30]\, Y - => \addr_data_f1_m_i[30]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_o2\ : NOR2 - port map(A => un1_apbi_0, B => paddr_2(2), Y => N_71); - - \prdata_RNO_6[17]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[17]\, Y - => \addr_data_f0_m_i[17]\); - - \reg_sp.addr_matrix_f1[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[8]\); - - \prdata_RNO_14[10]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[10]\, C => - N_232_1, Y => \addr_data_f2_m_i[10]\); - - \prdata_RNO_4[25]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[25]\, - C => \addr_matrix_f0_1_m_i[25]\, Y => - \prdata_39_0_iv_1[25]\); - - \prdata_RNO_1[3]\ : NOR3C - port map(A => \prdata_39_0_iv_6[3]\, B => - \prdata_39_0_iv_5[3]\, C => \delta_snapshot_m_i[3]\, Y - => \prdata_39_0_iv_11[3]\); - - \prdata_RNO_16[8]\ : OR2B - port map(A => \nb_burst_available[8]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[8]\); - - \prdata_RNO_5[21]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[21]\, - C => \addr_matrix_f2_m_i[21]\, Y => - \prdata_39_0_iv_0[21]\); - - \prdata_RNO_5[26]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[26]\, C - => \addr_matrix_f2_m_i[26]\, Y => \prdata_39_0_iv_0[26]\); - - \prdata[7]\ : DFN1C0 - port map(D => \prdata_39[7]\, CLK => lclk_c, CLR => rstn, Q - => prdata(7)); - - \reg_sp.config_active_interruption_onError\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - config_active_interruption_onError_0_sqmuxa, Q => - config_active_interruption_onError); - - \prdata_RNO_21[4]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[4]\, Y - => \delta_f2_f1_m_i[4]\); - - \prdata_RNO_3[19]\ : OR3B - port map(A => N_168, B => \addr_data_f2[19]\, C => N_232_1, - Y => \addr_data_f2_m_i[19]\); - - \prdata_RNO_4[5]\ : NOR3C - port map(A => \prdata_39_0_iv_2[5]\, B => - \prdata_39_0_iv_1[5]\, C => \addr_matrix_f0_1_m_i[5]\, Y - => \prdata_39_0_iv_6[5]\); - - \prdata_RNO_7[28]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[28]\, - Y => \addr_matrix_f0_1_m_i[28]\); - - \reg_wp.delta_f2_f1[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[7]\); - - \prdata_RNO_12[0]\ : AOI1B - port map(A => prdata_0_sqmuxa, B => - config_active_interruption_onNewMatrix, C => - \delta_f2_f0_m_i[0]\, Y => \prdata_39_0_iv_0[0]\); - - \prdata_RNO_0[25]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[25]\, C - => \addr_data_f2_m_i[25]\, Y => \prdata_39_0_iv_3[25]\); - - \prdata[14]\ : DFN1C0 - port map(D => \prdata_39[14]\, CLK => lclk_c, CLR => rstn, - Q => prdata(14)); - - \prdata_RNO_11[3]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f3\, Y => - enable_f3_m_i); - - \prdata_RNO_4[13]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[13]\, - C => \addr_matrix_f2_m_i[13]\, Y => - \prdata_39_0_iv_0[13]\); - - \prdata_RNO_2[9]\ : NOR3C - port map(A => \addr_data_f3_m_i[9]\, B => - \addr_data_f2_m_i[9]\, C => \addr_data_f1_m_i[9]\, Y => - \prdata_39_0_iv_10[9]\); - - prdata_12_sqmuxa_0_a2_0 : NOR2A - port map(A => N_168, B => N_6455_0, Y => prdata_12_sqmuxa_0); - - \reg_wp.status_full_RNO_0[2]\ : OR2 - port map(A => \status_full[2]\, B => status_full_0(2), Y - => \status_full_5_i_a2_0[2]\); - - \prdata_RNO_12[4]\ : AOI1B - port map(A => prdata_7_sqmuxa, B => \data_shaping_R1_0\, C - => \addr_matrix_f1_m_i[4]\, Y => \prdata_39_0_iv_4[4]\); - - \prdata_RNO_5[22]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[22]\, - C => \addr_matrix_f2_m_i[22]\, Y => - \prdata_39_0_iv_0[22]\); - - \reg_wp.addr_data_f2[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[15]\); - - \reg_wp.addr_data_f2[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[16]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_a2\ : - NOR3A - port map(A => N_162, B => rdata61_2, C => N_69, Y => - config_active_interruption_onError_0_sqmuxa); - - \reg_sp.addr_matrix_f2[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[15]\); - - \prdata_RNO[23]\ : OR3C - port map(A => \prdata_39_0_iv_3[23]\, B => - \addr_data_f1_m_i[23]\, C => \prdata_39_0_iv_4[23]\, Y - => \prdata_39[23]\); - - \reg_wp.burst_f0_1_sqmuxa_0_a2\ : NOR2B - port map(A => N_163, B => N_160, Y => burst_f0_1_sqmuxa); - - \reg_wp.addr_data_f0[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[7]\); - - \reg_sp.addr_matrix_f0_0[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[10]\); - - \prdata_RNO_6[0]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[0]\, C => N_232_0, - Y => \addr_data_f2_m_i[0]\); - - \reg_wp.addr_data_f1[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[27]\); - - \reg_wp.nb_burst_available[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[9]\); - - \reg_wp.addr_data_f1[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[8]\); - - \prdata_RNO_4[28]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[28]\, - C => \addr_matrix_f0_1_m_i[28]\, Y => - \prdata_39_0_iv_1[28]\); - - \reg_sp.addr_matrix_f0_0[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[13]\); - - \apbo.pirq_RNO[15]\ : OR3C - port map(A => \pirq_2_i_a2_7[15]\, B => \pirq_2_i_a2_6[15]\, - C => \pirq_2_i_a2_8[15]\, Y => N_1016_i_0); - - \reg_sp.addr_matrix_f2[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[12]\); - - \prdata_RNO_1[10]\ : NOR3C - port map(A => \prdata_39_0_iv_1[10]\, B => - \addr_matrix_f0_1_m_i[10]\, C => \delta_snapshot_m_i[10]\, - Y => \prdata_39_0_iv_6[10]\); - - \reg_wp.addr_data_f1[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[5]\); - - \prdata_RNO_3[21]\ : OR3B - port map(A => N_168, B => \addr_data_f2[21]\, C => N_232_1, - Y => \addr_data_f2_m_i[21]\); - - \prdata_RNO_15[3]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[3]\, C => N_232_1, - Y => \addr_data_f2_m_i[3]\); - - \prdata_RNO_3[26]\ : OR3B - port map(A => N_168, B => \addr_data_f2[26]\, C => N_232, Y - => \addr_data_f2_m_i[26]\); - - \prdata_RNO_8[19]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[19]\, Y - => \addr_matrix_f2_m_i[19]\); - - \prdata_RNO_3[1]\ : AOI1B - port map(A => prdata_7_sqmuxa, B => \data_shaping_SP0\, C - => \addr_matrix_f1_m_i[1]\, Y => \prdata_39_0_iv_5[1]\); - - \prdata_RNO_20[0]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[0]\, - Y => \addr_matrix_f0_1_m_i[0]\); - - \prdata[27]\ : DFN1C0 - port map(D => \prdata_39[27]\, CLK => lclk_c, CLR => rstn, - Q => prdata(27)); - - \prdata_RNO[12]\ : OR3C - port map(A => \prdata_39_0_iv_4[12]\, B => - \prdata_39_0_iv_3[12]\, C => \prdata_39_0_iv_5[12]\, Y - => \prdata_39[12]\); - - \reg_sp.addr_matrix_f2[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[17]\); - - \reg_wp.addr_data_f2[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[4]\); - - \prdata_RNO_2[3]\ : NOR3C - port map(A => \prdata_39_0_iv_7[3]\, B => - \addr_data_f3_m_i[3]\, C => \prdata_39_0_iv_9[3]\, Y => - \prdata_39_0_iv_13[3]\); - - \prdata_RNO_15[4]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[4]\, Y - => \addr_matrix_f1_m_i[4]\); - - \prdata[28]\ : DFN1C0 - port map(D => \prdata_39[28]\, CLK => lclk_c, CLR => rstn, - Q => prdata(28)); - - \prdata_RNO_0[28]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[28]\, C - => \addr_data_f2_m_i[28]\, Y => \prdata_39_0_iv_3[28]\); - - \reg_wp.addr_data_f3[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[13]\); - - \prdata_RNO_2[23]\ : NOR3C - port map(A => \prdata_39_0_iv_1[23]\, B => - \prdata_39_0_iv_0[23]\, C => \addr_data_f0_m_i[23]\, Y - => \prdata_39_0_iv_4[23]\); - - \reg_sp.addr_matrix_f2[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[25]\); - - \reg_wp.addr_data_f3[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[10]\); - - \prdata_RNO_9[8]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[8]\, Y - => \addr_data_f1_m_i[8]\); - - \prdata_RNO_13[0]\ : AOI1B - port map(A => \nb_snapshot_param[0]\, B => prdata_18_sqmuxa, - C => status_ready_matrix_f0_0_m_i, Y => - \prdata_39_0_iv_2[0]\); - - \reg_wp.data_shaping_R0\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => data_shaping_R0); - - \reg_wp.addr_data_f2[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[6]\); - - \prdata_RNO_14[7]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[7]\, C => N_232_1, - Y => \addr_data_f2_m_i[7]\); - - \prdata_RNO[24]\ : OR3C - port map(A => \prdata_39_0_iv_3[24]\, B => - \addr_data_f1_m_i[24]\, C => \prdata_39_0_iv_4[24]\, Y - => \prdata_39[24]\); - - \prdata_RNO_7[0]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[0]\, Y - => \addr_data_f1_m_i[0]\); - - \prdata_RNO[10]\ : OR3C - port map(A => \prdata_39_0_iv_7[10]\, B => - \prdata_39_0_iv_6[10]\, C => \prdata_39_0_iv_8[10]\, Y - => \prdata_39[10]\); - - \reg_sp.addr_matrix_f0_1[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[17]\); - - \reg_wp.data_shaping_SP1\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => \data_shaping_SP1\); - - \reg_sp.addr_matrix_f2[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[22]\); - - \prdata_RNO_3[22]\ : OR3B - port map(A => N_168, B => \addr_data_f2[22]\, C => N_232, Y - => \addr_data_f2_m_i[22]\); - - \reg_wp.status_full_err_RNO[1]\ : MX2 - port map(A => pwdata_0(5), B => - \status_full_err_5_i_a2_0[1]\, S => N_74, Y => N_53); - - \reg_wp.delta_snapshot[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[1]\); - - \reg_sp.addr_matrix_f0_1[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[21]\); - - prdata_2_sqmuxa_0_a2_0 : NOR3A - port map(A => N_159, B => N_69, C => paddr_0(2), Y => - prdata_2_sqmuxa_0); - - \prdata_RNO_0[11]\ : NOR3C - port map(A => \prdata_39_0_iv_1[11]\, B => - \prdata_39_0_iv_0[11]\, C => \addr_data_f0_m_i[11]\, Y - => \prdata_39_0_iv_5[11]\); - - \prdata_RNO_7[27]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[27]\, - Y => \addr_matrix_f0_1_m_i[27]\); - - \prdata_RNO_0[16]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[16]\, - C => \addr_data_f2_m_i[16]\, Y => \prdata_39_0_iv_3[16]\); - - \reg_wp.addr_data_f3[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[11]\); - - \reg_sp.addr_matrix_f2[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[27]\); - - \reg_sp.addr_matrix_f1[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[29]\); - - \reg_wp.delta_f2_f0[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[1]\); - - \reg_wp.burst_f0_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => paddr(5), B => N_69, C => paddr(4), Y => - N_163); - - \reg_wp.addr_data_f1[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[17]\); - - \reg_wp.status_new_err_RNO[3]\ : MX2 - port map(A => pwdata_0(11), B => - \status_new_err_5_i_a2_0[3]\, S => N_74, Y => N_65); - - \prdata_RNO_6[6]\ : NAND2 - port map(A => \delta_snapshot[6]\, B => prdata_14_sqmuxa, Y - => \delta_snapshot_m_i[6]\); - - \reg_sp.addr_matrix_f2[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[4]\); - - \reg_wp.delta_f2_f1[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[2]\); - - \prdata_RNO_5[10]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[10]\, Y => \addr_matrix_f0_1_m_i[10]\); - - \prdata_RNO_2[10]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[10]\, - C => \prdata_39_0_iv_5[10]\, Y => \prdata_39_0_iv_8[10]\); - - \prdata_RNO_16[5]\ : OR2B - port map(A => status_error_bad_component_error, B => - prdata_1_sqmuxa, Y => - status_error_bad_component_error_m_i); - - \prdata_RNO_3[15]\ : AND2 - port map(A => \prdata_39_0_iv_1[15]\, B => - \prdata_39_0_iv_0[15]\, Y => \prdata_39_0_iv_2[15]\); - - \apbo.pirq_RNO_3[15]\ : NOR2 - port map(A => status_full_err_0(2), B => - status_full_err_0(3), Y => \pirq_2_i_a2_3[15]\); - - \prdata_RNO_2[4]\ : NOR3C - port map(A => \addr_data_f2_m_i[4]\, B => - \status_full_err_m_i[0]\, C => \prdata_39_0_iv_10[4]\, Y - => \prdata_39_0_iv_13[4]\); - - \prdata_RNO_16[3]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[3]\, Y - => \delta_f2_f1_m_i[3]\); - - \prdata_RNO_12[9]\ : OR2B - port map(A => \status_new_err[1]\, B => prdata_13_sqmuxa, Y - => \status_new_err_m_i[1]\); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2_0_0\ : NOR3A - port map(A => N_160, B => N_69, C => - addr_matrix_f1_1_sqmuxa_0_a2_1_0, Y => - addr_matrix_f2_1_sqmuxa_0); - - \reg_sp.addr_matrix_f0_1[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[0]\); - - \reg_wp.addr_data_f2[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[0]\); - - \reg_wp.addr_data_f2[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[12]\); - - \reg_sp.addr_matrix_f1[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[23]\); - - \prdata_RNO_4[27]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[27]\, - C => \addr_matrix_f0_1_m_i[27]\, Y => - \prdata_39_0_iv_1[27]\); - - \prdata_RNO_0[1]\ : NOR3C - port map(A => \prdata_39_0_iv_5[1]\, B => - \prdata_39_0_iv_4[1]\, C => \addr_data_f3_m_i[1]\, Y => - \prdata_39_0_iv_11[1]\); - - \prdata[10]\ : DFN1C0 - port map(D => \prdata_39[10]\, CLK => lclk_c, CLR => rstn, - Q => prdata(10)); - - \reg_sp.status_ready_matrix_f1\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f1); - - \prdata_RNO_0[12]\ : NOR3C - port map(A => \prdata_39_0_iv_1[12]\, B => - \prdata_39_0_iv_0[12]\, C => \delta_snapshot_m_i[12]\, Y - => \prdata_39_0_iv_4[12]\); - - \prdata_RNO_2[7]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[7]\, C - => \prdata_39_0_iv_7[7]\, Y => \prdata_39_0_iv_10[7]\); - - \reg_wp.addr_data_f0[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[4]\); - - prdata_2_sqmuxa_0_a2 : NOR3A - port map(A => N_159, B => N_69, C => paddr_2(2), Y => - prdata_2_sqmuxa); - - \prdata_RNO[1]\ : OR3C - port map(A => \prdata_39_0_iv_11[1]\, B => - \prdata_39_0_iv_10[1]\, C => \prdata_39_0_iv_15[1]\, Y - => \prdata_39[1]\); - - \prdata_RNO_1[5]\ : NOR3C - port map(A => \prdata_39_0_iv_5[5]\, B => - \prdata_39_0_iv_4[5]\, C => \delta_snapshot_m_i[5]\, Y - => \prdata_39_0_iv_10[5]\); - - \reg_sp.addr_matrix_f0_1[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[28]\); - - \reg_sp.addr_matrix_f0_0[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[14]\); - - \prdata_RNO_1[2]\ : NOR3C - port map(A => \prdata_39_0_iv_6[2]\, B => - \prdata_39_0_iv_5[2]\, C => \delta_snapshot_m_i[2]\, Y - => \prdata_39_0_iv_11[2]\); - - \reg_sp.addr_matrix_f0_0[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[15]\); - - \reg_sp.addr_matrix_f0_0[1]\ : DFN1E1C0 - port map(D => pwdata_1_0, CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[1]\); - - \prdata_RNO_1[24]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[24]\, Y - => \addr_data_f1_m_i[24]\); - - \reg_sp.addr_matrix_f0_1[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[30]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_162, B => N_69, C => - addr_matrix_f1_1_sqmuxa_0_a2_1_0, Y => - addr_matrix_f1_1_sqmuxa); - - \prdata_RNO_0[27]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[27]\, C - => \addr_data_f2_m_i[27]\, Y => \prdata_39_0_iv_3[27]\); - - \prdata[13]\ : DFN1C0 - port map(D => \prdata_39[13]\, CLK => lclk_c, CLR => rstn, - Q => prdata(13)); - - \reg_wp.delta_f2_f0[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[3]\); - - \reg_wp.enable_f0\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \enable_f0\); - - \reg_sp.addr_matrix_f1[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[15]\); - - \prdata_RNO_8[15]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[15]\, - C => \addr_matrix_f2_m_i[15]\, Y => - \prdata_39_0_iv_0[15]\); - - \prdata_RNO_3[18]\ : OR3B - port map(A => N_168, B => \addr_data_f2[18]\, C => N_232_1, - Y => \addr_data_f2_m_i[18]\); - - \prdata_RNO[15]\ : OR3C - port map(A => \prdata_39_0_iv_4[15]\, B => - \prdata_39_0_iv_3[15]\, C => \prdata_39_0_iv_5[15]\, Y - => \prdata_39[15]\); - - \prdata_RNO_4[10]\ : NOR3C - port map(A => \nb_snapshot_param_m_i[10]\, B => - \nb_burst_available_m_i[10]\, C => - \addr_matrix_f1_m_i[10]\, Y => \prdata_39_0_iv_1[10]\); - - \reg_wp.addr_data_f3[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[0]\); - - \prdata_RNO_7[11]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[11]\, C => - N_232_1, Y => \addr_data_f2_m_i[11]\); - - \reg_wp.addr_data_f0[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[5]\); - - \prdata_RNO_7[16]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[16]\, Y => \addr_matrix_f0_1_m_i[16]\); - - \reg_sp.addr_matrix_f1[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[12]\); - - \prdata[3]\ : DFN1C0 - port map(D => \prdata_39[3]\, CLK => lclk_c, CLR => rstn, Q - => prdata(3)); - - \reg_wp.addr_data_f2[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[27]\); - - \reg_wp.burst_f0\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \burst_f0\); - - \prdata_RNO_10[4]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[4]\, - Y => \addr_matrix_f0_1_m_i[4]\); - - \reg_wp.addr_data_f3[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[15]\); - - \prdata[5]\ : DFN1C0 - port map(D => \prdata_39[5]\, CLK => lclk_c, CLR => rstn, Q - => prdata(5)); - - \reg_sp.addr_matrix_f1[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[17]\); - - \reg_wp.addr_data_f3[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[16]\); - - \prdata_RNO_6[21]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[21]\, Y - => \addr_data_f0_m_i[21]\); - - \prdata_RNO_11[8]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[8]\, - Y => \addr_matrix_f2_m_i[8]\); - - \prdata_RNO_6[26]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[26]\, Y - => \addr_data_f0_m_i[26]\); - - \reg_wp.addr_data_f0[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[24]\); - - \prdata_RNO_15[7]\ : OR2B - port map(A => \nb_snapshot_param[7]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[7]\); - - \reg_sp.addr_matrix_f2[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[9]\); - - \prdata_RNO_7[5]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[5]\, - C => \addr_matrix_f2_m_i[5]\, Y => \prdata_39_0_iv_4[5]\); - - GND_i : GND - port map(Y => \GND\); - - \prdata_RNO_2[1]\ : NOR3C - port map(A => \addr_data_f1_m_i[1]\, B => - \addr_data_f0_m_i[1]\, C => \prdata_39_0_iv_12[1]\, Y => - \prdata_39_0_iv_15[1]\); - - \reg_wp.status_new_err[0]\ : DFN1C0 - port map(D => N_59, CLK => lclk_c, CLR => rstn, Q => - \status_new_err[0]\); - - \reg_wp.status_new_err_RNO[0]\ : MX2 - port map(A => pwdata_0(8), B => - \status_new_err_5_i_a2_0[0]\, S => N_74, Y => N_59); - - \prdata_RNO_7[12]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[12]\, - Y => \addr_data_f1_m_i[12]\); - - \prdata_RNO_9[2]\ : AOI1B - port map(A => \status_full[2]\, B => prdata_13_sqmuxa, C - => \addr_data_f2_m_i[2]\, Y => \prdata_39_0_iv_9[2]\); - - \reg_wp.status_full[1]\ : DFN1C0 - port map(D => N_45, CLK => lclk_c, CLR => rstn, Q => - \status_full[1]\); - - \reg_wp.addr_data_f0[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[0]\); - - \prdata_RNO_8[18]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[18]\, Y - => \addr_matrix_f2_m_i[18]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_o2\ : - OR2A - port map(A => N_68, B => paddr(6), Y => N_69); - - \reg_sp.addr_matrix_f1[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[28]\); - - \prdata_RNO_7[8]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[8]\, Y - => \addr_data_f3_m_i[8]\); - - \reg_wp.addr_data_f0[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[28]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_o2_0_0\ : - OR2 - port map(A => paddr(7), B => N_749, Y => - config_active_interruption_onError_0_sqmuxa_0_o2_0_0); - - \prdata_RNO_14[1]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[1]\, - C => \addr_matrix_f0_1_m_i[1]\, Y => - \prdata_39_0_iv_7[1]\); - - \reg_wp.delta_snapshot[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[5]\); - - \prdata_RNO_2[20]\ : NOR3C - port map(A => \prdata_39_0_iv_1[20]\, B => - \prdata_39_0_iv_0[20]\, C => \addr_data_f0_m_i[20]\, Y - => \prdata_39_0_iv_4[20]\); - - \prdata_RNO_6[22]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[22]\, Y - => \addr_data_f0_m_i[22]\); - - \prdata_RNO_10[11]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[11]\, Y => \addr_matrix_f0_1_m_i[11]\); - - \reg_wp.nb_snapshot_param[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[0]\); - - \prdata_RNO_3[9]\ : NOR3C - port map(A => \addr_matrix_f0_0_m_i[9]\, B => - \addr_matrix_f2_m_i[9]\, C => \status_new_err_m_i[1]\, Y - => \prdata_39_0_iv_6[9]\); - - \reg_wp.addr_data_f0[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[14]\); - - \prdata_RNO_1[31]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[31]\, Y - => \addr_data_f1_m_i[31]\); - - \prdata_RNO_6[8]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[8]\, Y - => \delta_snapshot_m_i[8]\); - - \prdata_RNO_5[30]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[30]\, - C => \addr_matrix_f2_m_i[30]\, Y => - \prdata_39_0_iv_0[30]\); - - \prdata_RNO_4[7]\ : NOR3C - port map(A => \prdata_39_0_iv_1[7]\, B => - \prdata_39_0_iv_0[7]\, C => \addr_matrix_f1_m_i[7]\, Y - => \prdata_39_0_iv_3[7]\); - - \reg_sp.addr_matrix_f0_1[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[16]\); - - \prdata_RNO_5[29]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[29]\, C - => \addr_matrix_f2_m_i[29]\, Y => \prdata_39_0_iv_0[29]\); - - \prdata_RNO_5[4]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[4]\, - C => burst_f0_m_i, Y => \prdata_39_0_iv_5[4]\); - - \prdata_RNO_1[9]\ : NOR3C - port map(A => \prdata_39_0_iv_3[9]\, B => - \addr_matrix_f0_1_m_i[9]\, C => \delta_snapshot_m_i[9]\, - Y => \prdata_39_0_iv_8[9]\); - - \reg_wp.addr_data_f2[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[1]\); - - \reg_wp.delta_f2_f0[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[5]\); - - \prdata_RNO_3[17]\ : OR3B - port map(A => N_168, B => \addr_data_f2[17]\, C => N_232_1, - Y => \addr_data_f2_m_i[17]\); - - \prdata_RNO_1[23]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[23]\, Y - => \addr_data_f1_m_i[23]\); - - \prdata_RNO[2]\ : OR3C - port map(A => \prdata_39_0_iv_12[2]\, B => - \prdata_39_0_iv_11[2]\, C => \prdata_39_0_iv_13[2]\, Y - => \prdata_39[2]\); - - \reg_wp.delta_snapshot[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[6]\); - - \prdata[15]\ : DFN1C0 - port map(D => \prdata_39[15]\, CLK => lclk_c, CLR => rstn, - Q => prdata(15)); - - \reg_wp.delta_snapshot[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[8]\); - - \reg_wp.nb_burst_available[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[6]\); - - \reg_wp.status_full_err_RNO[2]\ : MX2 - port map(A => pwdata_0(6), B => - \status_full_err_5_i_a2_0[2]\, S => N_74, Y => N_55); - - \reg_wp.addr_data_f1[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[23]\); - - \reg_wp.addr_data_f0[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[18]\); - - \reg_wp.addr_data_f1[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[20]\); - - \prdata[6]\ : DFN1C0 - port map(D => \prdata_39[6]\, CLK => lclk_c, CLR => rstn, Q - => prdata(6)); - - \prdata_RNO_4[3]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[3]\, - C => \addr_matrix_f0_1_m_i[3]\, Y => - \prdata_39_0_iv_6[3]\); - - \prdata_RNO_10[9]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[9]\, - Y => \addr_matrix_f0_0_m_i[9]\); - - \reg_wp.status_new_err_RNO[2]\ : MX2 - port map(A => pwdata_0(10), B => - \status_new_err_5_i_a2_0[2]\, S => N_74, Y => N_63); - - \prdata_RNO_11[6]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[6]\, - Y => \addr_matrix_f0_1_m_i[6]\); - - \reg_sp.addr_matrix_f0_0[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[22]\); - - \reg_wp.status_new_err[2]\ : DFN1C0 - port map(D => N_63, CLK => lclk_c, CLR => rstn, Q => - \status_new_err[2]\); - - \prdata_RNO_17[4]\ : OR2B - port map(A => \nb_burst_available[4]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[4]\); - - \prdata_RNO_21[2]\ : NAND2 - port map(A => \delta_f2_f0[2]\, B => prdata_16_sqmuxa, Y - => \delta_f2_f0_m_i[2]\); - - \reg_wp.addr_data_f0[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[3]\); - - \reg_wp.addr_data_f3[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[12]\); - - \prdata_RNO_0[6]\ : NOR3C - port map(A => \status_full_err_m_i[2]\, B => - \prdata_39_0_iv_5[6]\, C => \addr_data_f0_m_i[6]\, Y => - \prdata_39_0_iv_10[6]\); - - prdata_4_sqmuxa_0_a2_0 : NOR3 - port map(A => N_69, B => addr_matrix_f1_1_sqmuxa_0_a2_1_0, - C => N_232, Y => prdata_4_sqmuxa_0); - - \reg_wp.delta_f2_f1[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[3]\); - - \prdata_RNO_8[24]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[24]\, Y - => \addr_matrix_f2_m_i[24]\); - - \reg_wp.addr_data_f1[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[21]\); - - \prdata_RNO_2[0]\ : NOR3C - port map(A => \addr_data_f1_m_i[0]\, B => - \addr_data_f0_m_i[0]\, C => \prdata_39_0_iv_12[0]\, Y => - \prdata_39_0_iv_15[0]\); - - \reg_wp.delta_f2_f0[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[8]\); - - \reg_wp.addr_data_f2[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[9]\); - - \prdata_RNO[27]\ : OR3C - port map(A => \prdata_39_0_iv_3[27]\, B => - \addr_data_f1_m_i[27]\, C => \prdata_39_0_iv_4[27]\, Y - => \prdata_39[27]\); - - \prdata_RNO_8[30]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[30]\, Y - => \addr_matrix_f2_m_i[30]\); - - \prdata_RNO_3[29]\ : OR3B - port map(A => N_168, B => \addr_data_f2[29]\, C => N_232, Y - => \addr_data_f2_m_i[29]\); - - prdata_4_sqmuxa_0_a2 : NOR3 - port map(A => N_69, B => addr_matrix_f1_1_sqmuxa_0_a2_1_0, - C => N_232, Y => prdata_4_sqmuxa); - - \prdata_RNO_8[17]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[17]\, Y - => \addr_matrix_f2_m_i[17]\); - - \reg_wp.status_full_RNO_0[3]\ : OR2 - port map(A => \status_full[3]\, B => status_full_0(3), Y - => \status_full_5_i_a2_0[3]\); - - \prdata_RNO_20[5]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[5]\, Y - => \delta_f2_f1_m_i[5]\); - - \prdata_RNO_18[2]\ : OR2B - port map(A => prdata_7_sqmuxa, B => \data_shaping_SP1\, Y - => data_shaping_SP1_m_i); - - \apbo.pirq_RNO_1[15]\ : NOR2B - port map(A => \pirq_2_i_a2_0[15]\, B => \pirq_2_i_a2_1[15]\, - Y => \pirq_2_i_a2_6[15]\); - - \reg_wp.status_full_err_RNO_0[0]\ : OR2 - port map(A => \status_full_err[0]\, B => - status_full_err_0(0), Y => \status_full_err_5_i_a2_0[0]\); - - \prdata_RNO_6[14]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[14]\, C => - N_232_1, Y => \addr_data_f2_m_i[14]\); - - \prdata_RNO_1[11]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[11]\, - C => \delta_snapshot_m_i[11]\, Y => - \prdata_39_0_iv_4[11]\); - - \prdata_RNO_1[16]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[16]\, Y - => \addr_data_f1_m_i[16]\); - - \apbo.pirq[15]\ : DFN1C0 - port map(D => N_1016_i_0, CLK => lclk_c, CLR => rstn, Q => - pirq(15)); - - \reg_wp.addr_data_f1[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[4]\); - - \prdata_RNO[19]\ : OR3C - port map(A => \prdata_39_0_iv_3[19]\, B => - \addr_data_f1_m_i[19]\, C => \prdata_39_0_iv_4[19]\, Y - => \prdata_39[19]\); - - \reg_wp.data_shaping_BW\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => \Bias_Fails_c\); - - \prdata_RNO_17[1]\ : OR2B - port map(A => \nb_burst_available[1]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[1]\); - - \reg_sp.addr_matrix_f2[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[0]\); - - \prdata_RNO_9[1]\ : NOR3C - port map(A => \prdata_39_0_iv_7[1]\, B => - \prdata_39_0_iv_6[1]\, C => \delta_snapshot_m_i[1]\, Y - => \prdata_39_0_iv_12[1]\); - - \prdata_RNO_1[0]\ : AOI1B - port map(A => \status_full[0]\, B => prdata_13_sqmuxa, C - => \addr_data_f2_m_i[0]\, Y => \prdata_39_0_iv_10[0]\); - - \prdata_RNO_10[1]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[1]\, Y - => \addr_matrix_f1_m_i[1]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_a2_0\ : NOR3B - port map(A => N_159, B => N_71, C => N_69, Y => - addr_matrix_f0_0_1_sqmuxa_0); - - \reg_wp.addr_data_f1[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[13]\); - - \reg_wp.delta_snapshot[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[4]\); - - \reg_wp.addr_data_f1[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[10]\); - - \reg_wp.status_full_RNO_0[0]\ : OR2 - port map(A => \status_full[0]\, B => status_full_0(0), Y - => \status_full_5_i_a2_0[0]\); - - \reg_sp.addr_matrix_f1[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[9]\); - - \reg_wp.delta_f2_f1[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[8]\); - - \reg_sp.addr_matrix_f0_1[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[10]\); - - \prdata_RNO_19[3]\ : OR2B - port map(A => \nb_snapshot_param[3]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[3]\); - - \prdata_RNO_2[5]\ : AOI1B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[5]\, C - => \prdata_39_0_iv_9[5]\, Y => \prdata_39_0_iv_12[5]\); - - \prdata_RNO_2[6]\ : NOR3C - port map(A => \addr_data_f3_m_i[6]\, B => - \addr_data_f2_m_i[6]\, C => \addr_data_f1_m_i[6]\, Y => - \prdata_39_0_iv_11[6]\); - - prdata_8_sqmuxa_0_a2 : NOR2A - port map(A => N_163, B => N_6455, Y => prdata_8_sqmuxa); - - \prdata_RNO_0[19]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[19]\, - C => \addr_data_f2_m_i[19]\, Y => \prdata_39_0_iv_3[19]\); - - \prdata[12]\ : DFN1C0 - port map(D => \prdata_39[12]\, CLK => lclk_c, CLR => rstn, - Q => prdata(12)); - - \reg_sp.addr_matrix_f0_1[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[13]\); - - \prdata_RNO_1[12]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[12]\, - C => \addr_data_f2_m_i[12]\, Y => \prdata_39_0_iv_3[12]\); - - \reg_sp.addr_matrix_f0_0[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[9]\); - - \reg_wp.addr_data_f1[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[11]\); - - prdata_0_sqmuxa_0_a2 : NOR3 - port map(A => rdata61_2, B => N_69, C => N_232, Y => - prdata_0_sqmuxa); - - \prdata_RNO_5[25]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[25]\, C - => \addr_matrix_f2_m_i[25]\, Y => \prdata_39_0_iv_0[25]\); - - \prdata[19]\ : DFN1C0 - port map(D => \prdata_39[19]\, CLK => lclk_c, CLR => rstn, - Q => prdata(19)); - - \prdata_RNO_11[4]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f0\, Y => - burst_f0_m_i); - - \reg_wp.delta_f2_f0[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[7]\); - - \prdata_RNO_11[11]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[11]\, - Y => \addr_matrix_f2_m_i[11]\); - - \reg_sp.addr_matrix_f0_1[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[29]\); - - \reg_wp.status_full_RNO[1]\ : MX2 - port map(A => pwdata_0(1), B => \status_full_5_i_a2_0[1]\, - S => N_74, Y => N_45); - - \reg_wp.nb_burst_available[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[5]\); - - \prdata_RNO_7[30]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[30]\, - Y => \addr_matrix_f0_1_m_i[30]\); - - \reg_wp.addr_data_f3[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[8]\); - - \prdata_RNO_5[11]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[11]\, Y - => \addr_data_f0_m_i[11]\); - - \reg_wp.addr_data_f0[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[29]\); - - \prdata_RNO_5[16]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[16]\, - C => \addr_matrix_f2_m_i[16]\, Y => - \prdata_39_0_iv_0[16]\); - - \prdata_RNO_2[11]\ : NOR3C - port map(A => \addr_data_f2_m_i[11]\, B => - \status_new_err_m_i[3]\, C => \addr_data_f1_m_i[11]\, Y - => \prdata_39_0_iv_6[11]\); - - \prdata_RNO_2[16]\ : NOR3C - port map(A => \prdata_39_0_iv_1[16]\, B => - \prdata_39_0_iv_0[16]\, C => \addr_data_f0_m_i[16]\, Y - => \prdata_39_0_iv_4[16]\); - - \prdata_RNO_13[10]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[10]\, Y - => \addr_matrix_f1_m_i[10]\); - - \reg_wp.nb_burst_available[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[8]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2\ : NOR2B - port map(A => N_168, B => N_162, Y => addr_data_f2_1_sqmuxa); - - prdata_13_sqmuxa_0_a2 : NOR3A - port map(A => paddr(4), B => N_72, C => paddr_2(2), Y => - prdata_13_sqmuxa); - - \reg_wp.delta_f2_f0[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[0]\); - - \reg_sp.status_error_bad_component_error\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_error_bad_component_error); - - \prdata_RNO_12[10]\ : OR2B - port map(A => \nb_burst_available[10]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[10]\); - - \reg_wp.addr_data_f3[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[24]\); - - \reg_wp.nb_burst_available[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[4]\); - - prdata_10_sqmuxa_0_a2_0 : NOR3A - port map(A => paddr_0(2), B => paddr_0(4), C => N_72, Y => - prdata_10_sqmuxa_0); - - \reg_wp.addr_data_f1[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[25]\); - - \reg_wp.addr_data_f1[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[26]\); - - \prdata_RNO_0[30]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[30]\, - C => \addr_data_f2_m_i[30]\, Y => \prdata_39_0_iv_3[30]\); - - \reg_wp.addr_data_f1[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[1]\); - - \prdata_RNO_8[23]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[23]\, Y - => \addr_matrix_f2_m_i[23]\); - - \reg_sp.addr_matrix_f2[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[3]\); - - \reg_sp.addr_matrix_f2[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[19]\); - - \status_full_ack[0]\ : DFN1C0 - port map(D => \status_full_ack_8[0]\, CLK => lclk_c, CLR - => rstn, Q => status_full_ack(0)); - - \prdata[21]\ : DFN1C0 - port map(D => \prdata_39[21]\, CLK => lclk_c, CLR => rstn, - Q => prdata(21)); - - \prdata_RNO_3[8]\ : NOR3C - port map(A => \addr_matrix_f0_0_m_i[8]\, B => - \addr_matrix_f2_m_i[8]\, C => \status_new_err_m_i[0]\, Y - => \prdata_39_0_iv_6[8]\); - - \prdata_RNO_5[12]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[12]\, - Y => \delta_snapshot_m_i[12]\); - - \reg_wp.addr_data_f3[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[28]\); - - \reg_wp.addr_data_f2[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[23]\); - - \prdata_RNO_5[28]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[28]\, C - => \addr_matrix_f2_m_i[28]\, Y => \prdata_39_0_iv_0[28]\); - - \prdata_RNO_2[12]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[12]\, C - => \addr_data_f1_m_i[12]\, Y => \prdata_39_0_iv_5[12]\); - - \reg_wp.addr_data_f2[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[20]\); - - \prdata_RNO_1[20]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[20]\, Y - => \addr_data_f1_m_i[20]\); - - \prdata_RNO_10[0]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[0]\, Y - => \addr_matrix_f1_m_i[0]\); - - \reg_wp.data_shaping_SP0\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => \data_shaping_SP0\); - - \prdata_RNO_6[13]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[13]\, C => - N_232_1, Y => \addr_data_f2_m_i[13]\); - - \prdata_RNO_3[25]\ : OR3B - port map(A => N_168, B => \addr_data_f2[25]\, C => N_232, Y - => \addr_data_f2_m_i[25]\); - - \reg_wp.addr_data_f0[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[19]\); - - \prdata_RNO_11[9]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[9]\, - Y => \addr_matrix_f2_m_i[9]\); - - \prdata_RNO_17[9]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[9]\, Y - => \delta_f2_f1_m_i[9]\); - - \reg_wp.data_shaping_R1_0\ : DFN1E1C0 - port map(D => pwdata_0(4), CLK => lclk_c, CLR => rstn, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_R1_0\); - - \prdata_RNO_8[5]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[5]\, Y - => \delta_snapshot_m_i[5]\); - - \prdata_RNO_6[3]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[3]\, Y - => \delta_snapshot_m_i[3]\); - - \reg_sp.addr_matrix_f2[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[13]\); - - \prdata_RNO_17[6]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[6]\, Y - => \addr_matrix_f1_m_i[6]\); - - \prdata_RNO_7[19]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[19]\, - Y => \addr_matrix_f0_1_m_i[19]\); - - \prdata_RNO_9[14]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[14]\, - Y => \addr_matrix_f2_m_i[14]\); - - \prdata_RNO_7[24]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[24]\, - Y => \addr_matrix_f0_1_m_i[24]\); - - \prdata_RNO[21]\ : OR3C - port map(A => \prdata_39_0_iv_3[21]\, B => - \addr_data_f1_m_i[21]\, C => \prdata_39_0_iv_4[21]\, Y - => \prdata_39[21]\); - - \prdata[1]\ : DFN1C0 - port map(D => \prdata_39[1]\, CLK => lclk_c, CLR => rstn, Q - => prdata(1)); - - \reg_wp.delta_snapshot[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[10]\); - - \reg_sp.addr_matrix_f2[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[29]\); - - \reg_wp.addr_data_f2[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[21]\); - - \reg_wp.addr_data_f3[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[7]\); - - \prdata_RNO_4[11]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[11]\, - C => \addr_matrix_f2_m_i[11]\, Y => - \prdata_39_0_iv_0[11]\); - - \prdata_RNO_4[16]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[16]\, C => \addr_matrix_f0_1_m_i[16]\, - Y => \prdata_39_0_iv_1[16]\); - - \prdata_RNO_1[7]\ : NOR3C - port map(A => \prdata_39_0_iv_3[7]\, B => - \addr_matrix_f0_1_m_i[7]\, C => \delta_snapshot_m_i[7]\, - Y => \prdata_39_0_iv_8[7]\); - - \prdata_RNO_7[9]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[9]\, Y - => \addr_data_f3_m_i[9]\); - - \prdata_RNO_6[29]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[29]\, Y - => \addr_data_f0_m_i[29]\); - - \prdata_RNO_19[2]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[2]\, Y - => \addr_matrix_f1_m_i[2]\); - - \reg_wp.addr_data_f1[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[15]\); - - \prdata_RNO_16[2]\ : AND2 - port map(A => \delta_f2_f1_m_i[2]\, B => - \delta_f2_f0_m_i[2]\, Y => \prdata_39_0_iv_0[2]\); - - \reg_wp.status_full_err_RNO[0]\ : MX2 - port map(A => pwdata_1_3, B => - \status_full_err_5_i_a2_0[0]\, S => N_74, Y => N_51); - - \reg_wp.addr_data_f1[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[16]\); - - \prdata_RNO_5[9]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[9]\, - Y => \addr_matrix_f0_1_m_i[9]\); - - \reg_sp.addr_matrix_f1[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[26]\); - - prdata_7_sqmuxa_0_a2 : NOR2A - port map(A => N_163, B => N_232, Y => prdata_7_sqmuxa); - - \reg_sp.addr_matrix_f2[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[2]\); - - \reg_sp.addr_matrix_f0_1[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[14]\); - - \reg_sp.addr_matrix_f0_1[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[15]\); - - \prdata_RNO[26]\ : OR3C - port map(A => \prdata_39_0_iv_3[26]\, B => - \addr_data_f1_m_i[26]\, C => \prdata_39_0_iv_4[26]\, Y - => \prdata_39[26]\); - - \prdata_RNO_0[15]\ : AND2 - port map(A => \prdata_39_0_iv_2[15]\, B => - \delta_snapshot_m_i[15]\, Y => \prdata_39_0_iv_4[15]\); - - \prdata[31]\ : DFN1C0 - port map(D => \prdata_39[31]\, CLK => lclk_c, CLR => rstn, - Q => prdata(31)); - - \reg_wp.addr_data_f1_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_166, B => paddr_0(4), C => N_72, Y => - addr_data_f1_1_sqmuxa); - - \reg_wp.addr_data_f2[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[30]\); - - \reg_sp.addr_matrix_f0_1[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[7]\); - - \prdata_RNO_4[24]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[24]\, - C => \addr_matrix_f0_1_m_i[24]\, Y => - \prdata_39_0_iv_1[24]\); - - \reg_sp.addr_matrix_f1[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[21]\); - - \reg_sp.addr_matrix_f2[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[23]\); - - \reg_wp.addr_data_f3[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[3]\); - - \prdata_RNO_3[28]\ : OR3B - port map(A => N_168, B => \addr_data_f2[28]\, C => N_232, Y - => \addr_data_f2_m_i[28]\); - - \reg_sp.addr_matrix_f1[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[20]\); - - prdata_1_sqmuxa_0_a2 : NOR3 - port map(A => rdata61_2, B => N_69, C => N_6455, Y => - prdata_1_sqmuxa); - - \prdata[16]\ : DFN1C0 - port map(D => \prdata_39[16]\, CLK => lclk_c, CLR => rstn, - Q => prdata(16)); - - \prdata_RNO_4[0]\ : NOR3C - port map(A => \prdata_39_0_iv_1[0]\, B => - \prdata_39_0_iv_0[0]\, C => \prdata_39_0_iv_2[0]\, Y => - \prdata_39_0_iv_4[0]\); - - \status_full_ack[2]\ : DFN1C0 - port map(D => \status_full_ack_8[2]\, CLK => lclk_c, CLR - => rstn, Q => status_full_ack(2)); - - \prdata_RNO_4[12]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[12]\, - C => \addr_matrix_f2_m_i[12]\, Y => - \prdata_39_0_iv_0[12]\); - - \prdata_RNO[0]\ : OR3C - port map(A => \prdata_39_0_iv_11[0]\, B => - \prdata_39_0_iv_10[0]\, C => \prdata_39_0_iv_15[0]\, Y - => \prdata_39[0]\); - - \reg_wp.addr_data_f1[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[22]\); - - \prdata_RNO_12[5]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[5]\, - Y => \addr_matrix_f0_1_m_i[5]\); - - \reg_wp.addr_data_f2[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[31]\); - - \reg_wp.nb_snapshot_param[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[3]\); - - \reg_sp.addr_matrix_f0_0[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[12]\); - - \prdata_RNO_0[24]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[24]\, C - => \addr_data_f2_m_i[24]\, Y => \prdata_39_0_iv_3[24]\); - - \reg_sp.status_error_anticipating_empty_fifo\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_error_anticipating_empty_fifo); - - \reg_sp.addr_matrix_f0_0[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[8]\); - - \status_full_ack_RNO[0]\ : NOR3A - port map(A => \status_full[0]\, B => pwdata_0(0), C => N_74, - Y => \status_full_ack_8[0]\); - - \prdata_RNO_2[21]\ : NOR3C - port map(A => \prdata_39_0_iv_1[21]\, B => - \prdata_39_0_iv_0[21]\, C => \addr_data_f0_m_i[21]\, Y - => \prdata_39_0_iv_4[21]\); - - \reg_sp.addr_matrix_f0_0[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[21]\); - - \prdata_RNO_2[26]\ : NOR3C - port map(A => \prdata_39_0_iv_1[26]\, B => - \prdata_39_0_iv_0[26]\, C => \addr_data_f0_m_i[26]\, Y - => \prdata_39_0_iv_4[26]\); - - \prdata_RNO_5[27]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[27]\, C - => \addr_matrix_f2_m_i[27]\, Y => \prdata_39_0_iv_0[27]\); - - \reg_wp.addr_data_f0[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[2]\); - - \reg_sp.addr_matrix_f0_0[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[0]\); - - \prdata_RNO_5[1]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[1]\, Y - => \addr_data_f3_m_i[1]\); - - \prdata_RNO_15[8]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[8]\, Y - => \addr_matrix_f1_m_i[8]\); - - \prdata_RNO_15[6]\ : AOI1B - port map(A => \nb_burst_available[6]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[6]\, Y => - \prdata_39_0_iv_1[6]\); - - \reg_wp.status_full[3]\ : DFN1C0 - port map(D => N_49, CLK => lclk_c, CLR => rstn, Q => - \status_full[3]\); - - \prdata_RNO_16[1]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[1]\, Y - => \delta_snapshot_m_i[1]\); - - \prdata[2]\ : DFN1C0 - port map(D => \prdata_39[2]\, CLK => lclk_c, CLR => rstn, Q - => prdata(2)); - - \reg_wp.delta_snapshot[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[2]\); - - \prdata_RNO_5[31]\ : AOI1B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[31]\, C - => \addr_matrix_f2_m_i[31]\, Y => \prdata_39_0_iv_0[31]\); - - prdata_9_sqmuxa_0_a2 : NOR3 - port map(A => paddr_0(4), B => N_72, C => paddr_2(2), Y => - prdata_9_sqmuxa); - - \prdata_RNO_5[2]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[2]\, - C => enable_f2_m_i, Y => \prdata_39_0_iv_5[2]\); - - \prdata_RNO_0[18]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[18]\, - C => \addr_data_f2_m_i[18]\, Y => \prdata_39_0_iv_3[18]\); - - \reg_wp.nb_snapshot_param[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[6]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0_1\ : NOR2B - port map(A => N_168, B => N_162, Y => - addr_data_f2_1_sqmuxa_0); - - \reg_sp.addr_matrix_f2[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[18]\); - - \lpp_top_apbreg.reg_wp.status_full_5_i_o2[0]\ : OR3B - port map(A => paddr(4), B => N_71, C => N_72, Y => N_74); - - \reg_wp.status_new_err_RNO_0[0]\ : OR2 - port map(A => \status_new_err[0]\, B => status_new_err_0(0), - Y => \status_new_err_5_i_a2_0[0]\); - - \reg_wp.delta_f2_f1[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[6]\); - - \reg_sp.addr_matrix_f0_1[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[27]\); - - \reg_wp.status_full_err[0]\ : DFN1C0 - port map(D => N_51, CLK => lclk_c, CLR => rstn, Q => - \status_full_err[0]\); - - \prdata_RNO_18[3]\ : OR2B - port map(A => status_ready_matrix_f2, B => prdata_1_sqmuxa, - Y => status_ready_matrix_f2_m_i); - - \reg_sp.addr_matrix_f1[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[4]\); - - \reg_sp.addr_matrix_f1[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[19]\); - - \reg_wp.addr_data_f2[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[25]\); - - \prdata_RNO_9[9]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[9]\, Y - => \addr_data_f1_m_i[9]\); - - \prdata_RNO_9[13]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[13]\, - Y => \addr_matrix_f2_m_i[13]\); - - \prdata_RNO_3[5]\ : OR2B - port map(A => \status_full_err[1]\, B => prdata_13_sqmuxa, - Y => \status_full_err_m_i[1]\); - - \prdata_RNO_0[4]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[4]\, C - => \addr_data_f1_m_i[4]\, Y => \prdata_39_0_iv_12[4]\); - - \prdata_RNO_7[23]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[23]\, - Y => \addr_matrix_f0_1_m_i[23]\); - - \reg_wp.addr_data_f2[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[26]\); - - \prdata_RNO_2[22]\ : NOR3C - port map(A => \prdata_39_0_iv_1[22]\, B => - \prdata_39_0_iv_0[22]\, C => \addr_data_f0_m_i[22]\, Y - => \prdata_39_0_iv_4[22]\); - - \reg_sp.addr_matrix_f0_1[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[8]\); - - \reg_wp.delta_snapshot[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[7]\); - - \reg_sp.addr_matrix_f0_0[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[3]\); - - \prdata_RNO_18[6]\ : OR2B - port map(A => \nb_snapshot_param[6]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[6]\); - - \reg_wp.burst_f1\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \burst_f1\); - - \prdata_RNO_7[15]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[15]\, C => \addr_matrix_f0_1_m_i[15]\, - Y => \prdata_39_0_iv_1[15]\); - - \reg_wp.addr_data_f1[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[12]\); - - \reg_sp.addr_matrix_f1[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[7]\); - - \reg_wp.status_full_RNO[2]\ : MX2 - port map(A => pwdata_0(2), B => \status_full_5_i_a2_0[2]\, - S => N_74, Y => N_47); - - \reg_wp.nb_burst_available[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[1]\); - - \prdata_RNO_8[20]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[20]\, Y - => \addr_matrix_f2_m_i[20]\); - - \prdata_RNO_0[5]\ : NOR3C - port map(A => \status_full_err_m_i[1]\, B => - \prdata_39_0_iv_6[5]\, C => \addr_data_f0_m_i[5]\, Y => - \prdata_39_0_iv_11[5]\); - - \reg_wp.addr_data_f2[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[14]\); - - \reg_sp.addr_matrix_f0_0[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[28]\); - - \reg_wp.addr_data_f3[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[30]\); - - \prdata_RNO_3[27]\ : OR3B - port map(A => N_168, B => \addr_data_f2[27]\, C => N_232, Y - => \addr_data_f2_m_i[27]\); - - \reg_wp.addr_data_f0[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[1]\); - - \reg_sp.addr_matrix_f1[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[13]\); - - \prdata_RNO_6[25]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[25]\, Y - => \addr_data_f0_m_i[25]\); - - \reg_wp.addr_data_f3[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[29]\); - - \reg_sp.addr_matrix_f2[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[28]\); - - \prdata_RNO_12[8]\ : OR2B - port map(A => \status_new_err[0]\, B => prdata_13_sqmuxa, Y - => \status_new_err_m_i[0]\); - - \prdata_RNO_4[23]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[23]\, - C => \addr_matrix_f0_1_m_i[23]\, Y => - \prdata_39_0_iv_1[23]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_0_0\ : NOR3A - port map(A => N_162, B => N_69, C => - addr_matrix_f1_1_sqmuxa_0_a2_1_0, Y => - addr_matrix_f1_1_sqmuxa_0); - - \prdata_RNO_1[19]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[19]\, Y - => \addr_data_f1_m_i[19]\); - - \prdata_RNO_8[31]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[31]\, Y - => \addr_matrix_f2_m_i[31]\); - - \prdata_RNO_7[2]\ : NOR3C - port map(A => \prdata_39_0_iv_2[2]\, B => - \prdata_39_0_iv_1[2]\, C => \prdata_39_0_iv_4[2]\, Y => - \prdata_39_0_iv_7[2]\); - - \prdata_RNO_6[10]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[10]\, - Y => \delta_snapshot_m_i[10]\); - - \reg_sp.addr_matrix_f1[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[24]\); - - \prdata_RNO_7[6]\ : AND2 - port map(A => \prdata_39_0_iv_4[6]\, B => - \prdata_39_0_iv_3[6]\, Y => \prdata_39_0_iv_6[6]\); - - \reg_wp.data_shaping_BW_1_sqmuxa_0_a2\ : NOR2B - port map(A => N_163, B => N_162, Y => - data_shaping_BW_1_sqmuxa); - - \reg_wp.addr_data_f3[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[31]\); - - \reg_wp.addr_data_f2[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[18]\); - - \prdata_RNO[5]\ : OR3C - port map(A => \prdata_39_0_iv_11[5]\, B => - \prdata_39_0_iv_10[5]\, C => \prdata_39_0_iv_12[5]\, Y - => \prdata_39[5]\); - - \prdata_RNO_3[14]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[14]\, C => \addr_matrix_f0_1_m_i[14]\, - Y => \prdata_39_0_iv_1[14]\); - - \reg_wp.status_full[2]\ : DFN1C0 - port map(D => N_47, CLK => lclk_c, CLR => rstn, Q => - \status_full[2]\); - - \prdata_RNO_0[23]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[23]\, C - => \addr_data_f2_m_i[23]\, Y => \prdata_39_0_iv_3[23]\); - - \reg_wp.status_full_RNO[0]\ : MX2 - port map(A => pwdata_0(0), B => \status_full_5_i_a2_0[0]\, - S => N_74, Y => N_43); - - \prdata_RNO_7[18]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[18]\, - Y => \addr_matrix_f0_1_m_i[18]\); - - \prdata_RNO_13[9]\ : AOI1B - port map(A => \nb_burst_available[9]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[9]\, Y => - \prdata_39_0_iv_1[9]\); - - \reg_wp.addr_data_f1[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[2]\); - - \reg_sp.addr_matrix_f2[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[6]\); - - \prdata_RNO_0[17]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[17]\, - C => \addr_data_f2_m_i[17]\, Y => \prdata_39_0_iv_3[17]\); - - \reg_wp.addr_data_f1[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[3]\); - - \prdata_RNO_0[9]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[9]\, C - => \prdata_39_0_iv_6[9]\, Y => \prdata_39_0_iv_9[9]\); - - \reg_sp.addr_matrix_f0_0[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[30]\); - - \prdata_RNO_6[28]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[28]\, Y - => \addr_data_f0_m_i[28]\); - - \reg_wp.addr_data_f2[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[3]\); - - \prdata_RNO[31]\ : OR3C - port map(A => \prdata_39_0_iv_3[31]\, B => - \addr_data_f1_m_i[31]\, C => \prdata_39_0_iv_4[31]\, Y - => \prdata_39[31]\); - - \reg_sp.addr_matrix_f0_0[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[6]\); - - \prdata_RNO_17[5]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[5]\, C - => \delta_f2_f1_m_i[5]\, Y => \prdata_39_0_iv_0[5]\); - - \prdata_RNO_10[7]\ : OR2B - port map(A => \status_full_err[3]\, B => prdata_13_sqmuxa, - Y => \status_full_err_m_i[3]\); - - \prdata_RNO_13[4]\ : NOR3C - port map(A => \nb_snapshot_param_m_i[4]\, B => - \nb_burst_available_m_i[4]\, C => \prdata_39_0_iv_2[4]\, - Y => \prdata_39_0_iv_3[4]\); - - \reg_sp.addr_matrix_f1_1_sqmuxa_0_a2_0\ : NOR2A - port map(A => N_71, B => paddr(3), Y => N_162); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_159, B => N_166, C => N_69, Y => - addr_matrix_f0_1_1_sqmuxa); - - \prdata_RNO_5[19]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[19]\, - C => \addr_matrix_f2_m_i[19]\, Y => - \prdata_39_0_iv_0[19]\); - - \prdata_RNO_2[19]\ : NOR3C - port map(A => \prdata_39_0_iv_1[19]\, B => - \prdata_39_0_iv_0[19]\, C => \addr_data_f0_m_i[19]\, Y - => \prdata_39_0_iv_4[19]\); - - \prdata_RNO_3[2]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[2]\, Y - => \addr_data_f1_m_i[2]\); - - \prdata_RNO_0[7]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[7]\, C - => \prdata_39_0_iv_6[7]\, Y => \prdata_39_0_iv_9[7]\); - - \reg_wp.addr_data_f2[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[22]\); - - \reg_wp.delta_f2_f0[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[9]\); - - \prdata[17]\ : DFN1C0 - port map(D => \prdata_39[17]\, CLK => lclk_c, CLR => rstn, - Q => prdata(17)); - - \reg_wp.addr_data_f0[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[30]\); - - \prdata_RNO_7[31]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[31]\, - Y => \addr_matrix_f0_1_m_i[31]\); - - \prdata_RNO_8[2]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[2]\, Y - => \addr_data_f3_m_i[2]\); - - \reg_wp.status_full_err[2]\ : DFN1C0 - port map(D => N_55, CLK => lclk_c, CLR => rstn, Q => - \status_full_err[2]\); - - \prdata_RNO_11[2]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f2\, Y => - enable_f2_m_i); - - \prdata_RNO_8[14]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[14]\, Y => \addr_matrix_f0_1_m_i[14]\); - - \reg_sp.addr_matrix_f2[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[31]\); - - \prdata_RNO_15[2]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[2]\, C => N_232_0, - Y => \addr_data_f2_m_i[2]\); - - \prdata[18]\ : DFN1C0 - port map(D => \prdata_39[18]\, CLK => lclk_c, CLR => rstn, - Q => prdata(18)); - - \reg_sp.addr_matrix_f2[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[30]\); - - \reg_wp.addr_data_f2[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[7]\); - - \prdata_RNO[13]\ : OR3C - port map(A => \prdata_39_0_iv_4[13]\, B => - \prdata_39_0_iv_3[13]\, C => \prdata_39_0_iv_5[13]\, Y - => \prdata_39[13]\); - - \reg_wp.data_shaping_R0_0\ : DFN1E1C0 - port map(D => pwdata_0(3), CLK => lclk_c, CLR => rstn, E - => data_shaping_BW_1_sqmuxa, Q => \data_shaping_R0_0\); - - \reg_sp.addr_matrix_f1[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[2]\); - - \reg_sp.addr_matrix_f1[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[18]\); - - \prdata_RNO_9[3]\ : AOI1B - port map(A => \status_full[3]\, B => prdata_13_sqmuxa, C - => \addr_data_f2_m_i[3]\, Y => \prdata_39_0_iv_9[3]\); - - \prdata_RNO_21[0]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f0\, Y => - enable_f0_m_i); - - \prdata_RNO_15[9]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[9]\, Y - => \addr_matrix_f1_m_i[9]\); - - \prdata_RNO_0[31]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[31]\, C - => \addr_data_f2_m_i[31]\, Y => \prdata_39_0_iv_3[31]\); - - \prdata_RNO_0[3]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[3]\, C - => \addr_data_f1_m_i[3]\, Y => \prdata_39_0_iv_12[3]\); - - \prdata_RNO[3]\ : OR3C - port map(A => \prdata_39_0_iv_12[3]\, B => - \prdata_39_0_iv_11[3]\, C => \prdata_39_0_iv_13[3]\, Y - => \prdata_39[3]\); - - \reg_wp.enable_f2\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \enable_f2\); - - \reg_wp.addr_data_f0[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[6]\); - - \reg_wp.addr_data_f0[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[31]\); - - \prdata_RNO[6]\ : OR3C - port map(A => \prdata_39_0_iv_10[6]\, B => - \prdata_39_0_iv_9[6]\, C => \prdata_39_0_iv_11[6]\, Y => - \prdata_39[6]\); - - \reg_wp.status_new_err_RNO_0[1]\ : OR2 - port map(A => \status_new_err[1]\, B => status_new_err_0(1), - Y => \status_new_err_5_i_a2_0[1]\); - - \reg_wp.addr_data_f3[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[9]\); - - \reg_wp.status_new_err[1]\ : DFN1C0 - port map(D => N_61, CLK => lclk_c, CLR => rstn, Q => - \status_new_err[1]\); - - \prdata_RNO_10[5]\ : NOR2B - port map(A => status_error_bad_component_error_m_i, B => - \prdata_39_0_iv_0[5]\, Y => \prdata_39_0_iv_2[5]\); - - \prdata_RNO_16[7]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[7]\, Y - => \delta_f2_f1_m_i[7]\); - - \prdata_RNO_1[1]\ : AOI1B - port map(A => \status_full[1]\, B => prdata_13_sqmuxa, C - => \addr_data_f2_m_i[1]\, Y => \prdata_39_0_iv_10[1]\); - - \reg_wp.status_full_RNO_0[1]\ : OR2 - port map(A => \status_full[1]\, B => status_full_0(1), Y - => \status_full_5_i_a2_0[1]\); - - \prdata_RNO_14[6]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \burst_f2\, Y => - burst_f2_m_i); - - \prdata_RNO_1[21]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[21]\, Y - => \addr_data_f1_m_i[21]\); - - \prdata_RNO_1[26]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[26]\, Y - => \addr_data_f1_m_i[26]\); - - \prdata_RNO_1[15]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[15]\, - C => \addr_data_f2_m_i[15]\, Y => \prdata_39_0_iv_3[15]\); - - \prdata_RNO_14[2]\ : NOR2B - port map(A => data_shaping_SP1_m_i, B => - \addr_matrix_f1_m_i[2]\, Y => \prdata_39_0_iv_4[2]\); - - \prdata_RNO_7[17]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[17]\, - Y => \addr_matrix_f0_1_m_i[17]\); - - \prdata_RNO_13[1]\ : AOI1B - port map(A => \nb_snapshot_param[1]\, B => prdata_18_sqmuxa, - C => status_ready_matrix_f0_1_m_i, Y => - \prdata_39_0_iv_2[1]\); - - \reg_sp.addr_matrix_f0_1[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[26]\); - - \prdata_RNO_9[10]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[10]\, - Y => \addr_matrix_f2_m_i[10]\); - - \prdata_RNO_3[13]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[13]\, C => \addr_matrix_f0_1_m_i[13]\, - Y => \prdata_39_0_iv_1[13]\); - - \prdata_RNO_7[20]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[20]\, - Y => \addr_matrix_f0_1_m_i[20]\); - - \status_full_ack_RNO[1]\ : NOR3A - port map(A => \status_full[1]\, B => pwdata_0(1), C => N_74, - Y => \status_full_ack_8[1]\); - - \reg_wp.addr_data_f1[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[9]\); - - \reg_wp.addr_data_f0[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[27]\); - - \prdata_RNO_17[0]\ : OR2B - port map(A => \nb_burst_available[0]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[0]\); - - \reg_wp.delta_snapshot[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[3]\); - - \prdata_RNO_4[19]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[19]\, - C => \addr_matrix_f0_1_m_i[19]\, Y => - \prdata_39_0_iv_1[19]\); - - \prdata_RNO[14]\ : OR3C - port map(A => \prdata_39_0_iv_4[14]\, B => - \prdata_39_0_iv_3[14]\, C => \prdata_39_0_iv_5[14]\, Y - => \prdata_39[14]\); - - \reg_wp.status_full_err_RNO_0[3]\ : OR2 - port map(A => \status_full_err[3]\, B => - status_full_err_0(3), Y => \status_full_err_5_i_a2_0[3]\); - - \prdata_RNO_2[30]\ : NOR3C - port map(A => \prdata_39_0_iv_1[30]\, B => - \prdata_39_0_iv_0[30]\, C => \addr_data_f0_m_i[30]\, Y - => \prdata_39_0_iv_4[30]\); - - \reg_sp.addr_matrix_f1[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[1]\); - - \prdata_RNO_6[27]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[27]\, Y - => \addr_data_f0_m_i[27]\); - - \prdata_RNO_3[30]\ : OR3B - port map(A => N_168, B => \addr_data_f2[30]\, C => N_232, Y - => \addr_data_f2_m_i[30]\); - - \prdata_RNO_6[7]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[7]\, Y - => \delta_snapshot_m_i[7]\); - - \reg_sp.addr_matrix_f0_0[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[11]\); - - \reg_wp.addr_data_f3[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[14]\); - - \prdata_RNO_1[22]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[22]\, Y - => \addr_data_f1_m_i[22]\); - - \prdata_RNO_18[8]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[8]\, Y - => \delta_f2_f0_m_i[8]\); - - \prdata_RNO[28]\ : OR3C - port map(A => \prdata_39_0_iv_3[28]\, B => - \addr_data_f1_m_i[28]\, C => \prdata_39_0_iv_4[28]\, Y - => \prdata_39[28]\); - - \prdata_RNO_4[20]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[20]\, C => \addr_matrix_f0_1_m_i[20]\, - Y => \prdata_39_0_iv_1[20]\); - - \status_full_ack_RNO[3]\ : NOR3A - port map(A => \status_full[3]\, B => pwdata_1_2, C => N_74, - Y => \status_full_ack_8[3]\); - - \reg_wp.nb_burst_available_1_sqmuxa_0_a2_1\ : NOR2A - port map(A => paddr_0(3), B => rdata61_2, Y => N_159); - - \reg_wp.addr_data_f2[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[8]\); - - \prdata_RNO_14[8]\ : AOI1B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[8]\, C - => \delta_f2_f0_m_i[8]\, Y => \prdata_39_0_iv_0[8]\); - - \prdata_RNO_13[7]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[7]\, Y - => \addr_matrix_f1_m_i[7]\); - - \reg_wp.delta_f2_f1[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[5]\); - - \prdata_RNO_19[5]\ : OR2B - port map(A => \nb_snapshot_param[5]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[5]\); - - \reg_wp.nb_snapshot_param[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[5]\); - - \reg_wp.addr_data_f2[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[19]\); - - \prdata_RNO_1[18]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[18]\, Y - => \addr_data_f1_m_i[18]\); - - \reg_wp.addr_data_f0[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[17]\); - - \prdata_RNO_14[4]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[4]\, Y - => \addr_data_f3_m_i[4]\); - - \prdata_RNO_5[15]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[15]\, C => - N_232_1, Y => \addr_data_f2_m_i[15]\); - - \reg_wp.status_full_err_RNO_0[2]\ : OR2 - port map(A => \status_full_err[2]\, B => - status_full_err_0(2), Y => \status_full_err_5_i_a2_0[2]\); - - \prdata_RNO_6[2]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[2]\, Y - => \delta_snapshot_m_i[2]\); - - \prdata_RNO_2[15]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[15]\, C - => \addr_data_f1_m_i[15]\, Y => \prdata_39_0_iv_5[15]\); - - \prdata_RNO_8[13]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[13]\, Y => \addr_matrix_f0_1_m_i[13]\); - - \reg_wp.addr_data_f3[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[18]\); - - prdata_5_sqmuxa_0_a2_0 : NOR3 - port map(A => N_69, B => addr_matrix_f1_1_sqmuxa_0_a2_1_0, - C => N_6455_0, Y => prdata_5_sqmuxa_0); - - \prdata_RNO_4[2]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[2]\, - C => \addr_matrix_f0_1_m_i[2]\, Y => - \prdata_39_0_iv_6[2]\); - - \prdata_RNO_2[29]\ : NOR3C - port map(A => \prdata_39_0_iv_1[29]\, B => - \prdata_39_0_iv_0[29]\, C => \addr_data_f0_m_i[29]\, Y - => \prdata_39_0_iv_4[29]\); - - \prdata_RNO_0[20]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[20]\, - C => \addr_data_f2_m_i[20]\, Y => \prdata_39_0_iv_3[20]\); - - \reg_sp.addr_matrix_f2[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[16]\); - - \reg_wp.delta_f2_f1[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[0]\); - - \prdata_RNO_15[0]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[0]\, - C => enable_f0_m_i, Y => \prdata_39_0_iv_6[0]\); - - \reg_wp.status_new_err_RNO[1]\ : MX2 - port map(A => pwdata_0(9), B => - \status_new_err_5_i_a2_0[1]\, S => N_74, Y => N_61); - - \prdata_RNO_1[6]\ : AND2 - port map(A => \delta_snapshot_m_i[6]\, B => - \prdata_39_0_iv_6[6]\, Y => \prdata_39_0_iv_9[6]\); - - \reg_sp.addr_matrix_f2[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[11]\); - - \reg_sp.addr_matrix_f2[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[10]\); - - \reg_sp.addr_matrix_f0_0[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[18]\); - - \prdata_RNO_20[3]\ : OR2B - port map(A => prdata_7_sqmuxa, B => \data_shaping_R0_0\, Y - => data_shaping_R0_m_i); - - \reg_sp.addr_matrix_f0_0[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[29]\); - - \prdata_RNO_10[8]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[8]\, - Y => \addr_matrix_f0_0_m_i[8]\); - - \prdata_RNO_3[7]\ : NOR3C - port map(A => \addr_matrix_f0_0_m_i[7]\, B => - \addr_matrix_f2_m_i[7]\, C => \status_full_err_m_i[3]\, Y - => \prdata_39_0_iv_6[7]\); - - \reg_wp.delta_f2_f1[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[4]\); - - \reg_sp.addr_matrix_f0_1[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[20]\); - - \prdata_RNO_4[30]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[30]\, C => \addr_matrix_f0_1_m_i[30]\, - Y => \prdata_39_0_iv_1[30]\); - - \reg_sp.addr_matrix_f2[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[26]\); - - \reg_sp.addr_matrix_f0_1[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[23]\); - - \prdata_RNO_5[18]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[18]\, - C => \addr_matrix_f2_m_i[18]\, Y => - \prdata_39_0_iv_0[18]\); - - \reg_wp.delta_snapshot[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[15]\); - - \prdata_RNO_2[18]\ : NOR3C - port map(A => \prdata_39_0_iv_1[18]\, B => - \prdata_39_0_iv_0[18]\, C => \addr_data_f0_m_i[18]\, Y - => \prdata_39_0_iv_4[18]\); - - \reg_wp.data_shaping_R1\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - data_shaping_BW_1_sqmuxa, Q => data_shaping_R1); - - \prdata_RNO_12[6]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[6]\, - C => burst_f2_m_i, Y => \prdata_39_0_iv_4[6]\); - - \reg_sp.addr_matrix_f0_1[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[12]\); - - \reg_wp.delta_snapshot[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[0]\); - - \reg_sp.addr_matrix_f2[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[21]\); - - \reg_sp.addr_matrix_f0_0_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_159, B => N_71, C => N_69, Y => - addr_matrix_f0_0_1_sqmuxa); - - \prdata_RNO_0[0]\ : NOR3C - port map(A => \prdata_39_0_iv_5[0]\, B => - \prdata_39_0_iv_4[0]\, C => \addr_data_f3_m_i[0]\, Y => - \prdata_39_0_iv_11[0]\); - - \prdata_RNO_8[1]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[1]\, Y - => \addr_data_f0_m_i[1]\); - - \reg_wp.enable_f3\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \enable_f3\); - - \prdata[24]\ : DFN1C0 - port map(D => \prdata_39[24]\, CLK => lclk_c, CLR => rstn, - Q => prdata(24)); - - \prdata_RNO[22]\ : OR3C - port map(A => \prdata_39_0_iv_3[22]\, B => - \addr_data_f1_m_i[22]\, C => \prdata_39_0_iv_4[22]\, Y - => \prdata_39[22]\); - - \apbo.pirq_RNO_6[15]\ : NOR2 - port map(A => status_full_0(2), B => status_full_0(3), Y - => \pirq_2_i_a2_5[15]\); - - \reg_sp.addr_matrix_f2[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[20]\); - - \prdata_RNO_4[15]\ : NAND2 - port map(A => \delta_snapshot[15]\, B => prdata_14_sqmuxa, - Y => \delta_snapshot_m_i[15]\); - - \prdata_RNO_18[0]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[0]\, Y - => \delta_f2_f0_m_i[0]\); - - \prdata_RNO_13[2]\ : AOI1B - port map(A => \nb_burst_available[2]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[2]\, Y => - \prdata_39_0_iv_1[2]\); - - \prdata_RNO_8[8]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[8]\, C => N_232_1, - Y => \addr_data_f2_m_i[8]\); - - \prdata_RNO_8[21]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[21]\, Y - => \addr_matrix_f2_m_i[21]\); - - \prdata_RNO_8[26]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[26]\, Y - => \addr_matrix_f2_m_i[26]\); - - \prdata_RNO_1[17]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[17]\, Y - => \addr_data_f1_m_i[17]\); - - \prdata_RNO_14[9]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[9]\, C - => \delta_f2_f1_m_i[9]\, Y => \prdata_39_0_iv_0[9]\); - - \prdata_RNO[20]\ : OR3C - port map(A => \prdata_39_0_iv_3[20]\, B => - \addr_data_f1_m_i[20]\, C => \prdata_39_0_iv_4[20]\, Y - => \prdata_39[20]\); - - \prdata_RNO_15[5]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[5]\, C => N_232_1, - Y => \addr_data_f2_m_i[5]\); - - \prdata_RNO_12[3]\ : NOR3C - port map(A => \delta_f2_f1_m_i[3]\, B => - \delta_f2_f0_m_i[3]\, C => status_ready_matrix_f2_m_i, Y - => \prdata_39_0_iv_2[3]\); - - \reg_sp.addr_matrix_f0_1[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[31]\); - - \prdata_RNO_5[24]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[24]\, - C => \addr_matrix_f2_m_i[24]\, Y => - \prdata_39_0_iv_0[24]\); - - \reg_sp.addr_matrix_f1[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[5]\); - - prdata_15_sqmuxa_0_a2 : NOR3A - port map(A => N_158, B => rdata61_2, C => N_232, Y => - prdata_15_sqmuxa); - - \reg_wp.delta_snapshot[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[12]\); - - \prdata_RNO_19[1]\ : OR2B - port map(A => status_ready_matrix_f0_1, B => - prdata_1_sqmuxa, Y => status_ready_matrix_f0_1_m_i); - - \reg_wp.status_new_err_RNO_0[2]\ : OR2 - port map(A => \status_new_err[2]\, B => status_new_err_0(2), - Y => \status_new_err_5_i_a2_0[2]\); - - \prdata_RNO_6[11]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[11]\, - Y => \delta_snapshot_m_i[11]\); - - \prdata_RNO_6[16]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[16]\, Y - => \addr_data_f0_m_i[16]\); - - \prdata_RNO_3[10]\ : NOR3C - port map(A => \addr_matrix_f0_0_m_i[10]\, B => - \addr_matrix_f2_m_i[10]\, C => \status_new_err_m_i[2]\, Y - => \prdata_39_0_iv_4[10]\); - - \prdata_RNO_14[5]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[5]\, - Y => \addr_matrix_f2_m_i[5]\); - - \prdata_RNO_19[6]\ : OR2B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[6]\, Y - => \delta_f2_f1_m_i[6]\); - - \prdata_RNO_17[3]\ : OR2B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[3]\, Y - => \delta_f2_f0_m_i[3]\); - - \prdata_RNO_8[22]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[22]\, Y - => \addr_matrix_f2_m_i[22]\); - - prdata_17_sqmuxa_0_a2 : NOR3B - port map(A => N_158, B => N_159, C => paddr_2(2), Y => - prdata_17_sqmuxa); - - \reg_sp.addr_matrix_f0_1_1_sqmuxa_0_a2_0_0\ : NOR3B - port map(A => N_159, B => N_166, C => N_69, Y => - addr_matrix_f0_1_1_sqmuxa_0); - - \reg_wp.addr_data_f1[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[30]\); - - \prdata_RNO_2[25]\ : NOR3C - port map(A => \prdata_39_0_iv_1[25]\, B => - \prdata_39_0_iv_0[25]\, C => \addr_data_f0_m_i[25]\, Y - => \prdata_39_0_iv_4[25]\); - - \prdata_RNO_4[18]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[18]\, C => \addr_matrix_f0_1_m_i[18]\, - Y => \prdata_39_0_iv_1[18]\); - - \reg_wp.nb_burst_available[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[2]\); - - \prdata_RNO_8[6]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[6]\, Y - => \addr_data_f3_m_i[6]\); - - \prdata_RNO_3[3]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[3]\, Y - => \addr_data_f1_m_i[3]\); - - \reg_wp.delta_snapshot[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[14]\); - - \reg_wp.delta_f2_f1[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - delta_f2_f1_1_sqmuxa, Q => \delta_f2_f1[9]\); - - \reg_sp.addr_matrix_f2[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[14]\); - - \prdata_RNO_6[12]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[12]\, C => - N_232_1, Y => \addr_data_f2_m_i[12]\); - - \prdata_RNO_9[5]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[5]\, C - => \addr_data_f2_m_i[5]\, Y => \prdata_39_0_iv_9[5]\); - - \prdata_RNO_5[0]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[0]\, Y - => \addr_data_f3_m_i[0]\); - - \reg_wp.addr_data_f3[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[27]\); - - \prdata_RNO_5[17]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[17]\, - C => \addr_matrix_f2_m_i[17]\, Y => - \prdata_39_0_iv_0[17]\); - - \prdata_RNO_2[17]\ : NOR3C - port map(A => \prdata_39_0_iv_1[17]\, B => - \prdata_39_0_iv_0[17]\, C => \addr_data_f0_m_i[17]\, Y - => \prdata_39_0_iv_4[17]\); - - \reg_wp.nb_snapshot_param[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[10]\); - - \reg_sp.addr_matrix_f1[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[16]\); - - \reg_wp.delta_snapshot[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[11]\); - - \reg_sp.config_active_interruption_onNewMatrix\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - config_active_interruption_onError_0_sqmuxa, Q => - config_active_interruption_onNewMatrix); - - \reg_wp.addr_data_f1[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[31]\); - - \reg_wp.status_full_RNO[3]\ : MX2 - port map(A => pwdata_1_2, B => \status_full_5_i_a2_0[3]\, S - => N_74, Y => N_49); - - \prdata_RNO_3[24]\ : OR3B - port map(A => N_168, B => \addr_data_f2[24]\, C => N_232, Y - => \addr_data_f2_m_i[24]\); - - \reg_wp.addr_data_f3[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[19]\); - - \prdata_RNO_2[8]\ : NOR3C - port map(A => \addr_data_f3_m_i[8]\, B => - \addr_data_f2_m_i[8]\, C => \addr_data_f1_m_i[8]\, Y => - \prdata_39_0_iv_10[8]\); - - \reg_sp.addr_matrix_f1[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[11]\); - - \status_full_ack_RNO[2]\ : NOR3A - port map(A => \status_full[2]\, B => pwdata_0(2), C => N_74, - Y => \status_full_ack_8[2]\); - - \reg_sp.addr_matrix_f0_1[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[24]\); - - \reg_sp.addr_matrix_f0_1[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[3]\); - - \reg_sp.addr_matrix_f0_1[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[25]\); - - \prdata_RNO_8[10]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[10]\, - Y => \addr_matrix_f0_0_m_i[10]\); - - \reg_sp.addr_matrix_f1[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[10]\); - - \reg_sp.status_error_anticipating_empty_fifo_1_sqmuxa_0_a2\ : - NOR3A - port map(A => N_160, B => rdata61_2, C => N_69, Y => - status_error_anticipating_empty_fifo_1_sqmuxa); - - prdata_3_sqmuxa_0_a2 : NOR3B - port map(A => N_159, B => paddr_2(2), C => N_69, Y => - prdata_3_sqmuxa); - - \prdata_RNO_3[0]\ : AOI1B - port map(A => prdata_7_sqmuxa, B => \Bias_Fails_c\, C => - \addr_matrix_f1_m_i[0]\, Y => \prdata_39_0_iv_5[0]\); - - \prdata_RNO_2[2]\ : NOR3C - port map(A => \prdata_39_0_iv_7[2]\, B => - \addr_data_f3_m_i[2]\, C => \prdata_39_0_iv_9[2]\, Y => - \prdata_39_0_iv_13[2]\); - - \prdata_RNO_7[7]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[7]\, C - => \addr_data_f2_m_i[7]\, Y => \prdata_39_0_iv_7[7]\); - - \prdata_RNO_13[5]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[5]\, - Y => \addr_matrix_f0_0_m_i[5]\); - - \prdata_RNO_3[4]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[4]\, Y - => \addr_data_f1_m_i[4]\); - - \reg_wp.status_full_err_RNO[3]\ : MX2 - port map(A => pwdata_0(7), B => - \status_full_err_5_i_a2_0[3]\, S => N_74, Y => N_57); - - \reg_sp.addr_matrix_f2[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[7]\); - - \reg_sp.addr_matrix_f2[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[24]\); - - \reg_wp.addr_data_f1[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[24]\); - - \prdata_RNO_5[6]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[6]\, Y - => \addr_data_f0_m_i[6]\); - - \prdata_RNO_2[28]\ : NOR3C - port map(A => \prdata_39_0_iv_1[28]\, B => - \prdata_39_0_iv_0[28]\, C => \addr_data_f0_m_i[28]\, Y - => \prdata_39_0_iv_4[28]\); - - \prdata_RNO_16[4]\ : OR2B - port map(A => \nb_snapshot_param[4]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[4]\); - - \prdata_RNO[17]\ : OR3C - port map(A => \prdata_39_0_iv_3[17]\, B => - \addr_data_f1_m_i[17]\, C => \prdata_39_0_iv_4[17]\, Y - => \prdata_39[17]\); - - \reg_wp.addr_data_f0[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[23]\); - - \prdata_RNO[25]\ : OR3C - port map(A => \prdata_39_0_iv_3[25]\, B => - \addr_data_f1_m_i[25]\, C => \prdata_39_0_iv_4[25]\, Y - => \prdata_39[25]\); - - \prdata[20]\ : DFN1C0 - port map(D => \prdata_39[20]\, CLK => lclk_c, CLR => rstn, - Q => prdata(20)); - - \reg_wp.addr_data_f0[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[20]\); - - \prdata_RNO_1[4]\ : NOR3C - port map(A => \prdata_39_0_iv_6[4]\, B => - \prdata_39_0_iv_5[4]\, C => \delta_snapshot_m_i[4]\, Y - => \prdata_39_0_iv_11[4]\); - - \prdata_RNO_21[1]\ : OR2B - port map(A => prdata_8_sqmuxa, B => \enable_f1\, Y => - enable_f1_m_i); - - \reg_wp.addr_data_f3[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[1]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \prdata_RNO_8[3]\ : OR2B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[3]\, Y - => \addr_data_f3_m_i[3]\); - - \reg_sp.addr_matrix_f0_0[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[27]\); - - \prdata_RNO_1[29]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[29]\, Y - => \addr_data_f1_m_i[29]\); - - \prdata_RNO_5[23]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[23]\, - C => \addr_matrix_f2_m_i[23]\, Y => - \prdata_39_0_iv_0[23]\); - - \prdata_RNO_17[8]\ : OR2B - port map(A => \nb_snapshot_param[8]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[8]\); - - \prdata_RNO_10[6]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[6]\, Y - => \addr_data_f1_m_i[6]\); - - \prdata_RNO_0[14]\ : NOR3C - port map(A => \prdata_39_0_iv_1[14]\, B => - \prdata_39_0_iv_0[14]\, C => \delta_snapshot_m_i[14]\, Y - => \prdata_39_0_iv_4[14]\); - - prdata_14_sqmuxa_0_a2 : NOR3B - port map(A => paddr(4), B => paddr_2(2), C => N_72, Y => - prdata_14_sqmuxa); - - \reg_wp.addr_data_f1[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[28]\); - - \reg_wp.delta_snapshot[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[13]\); - - \prdata_RNO_8[7]\ : OR2B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[7]\, - Y => \addr_matrix_f0_0_m_i[7]\); - - \reg_wp.addr_data_f0[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[21]\); - - prdata_3_sqmuxa_0_a2_0 : NOR3B - port map(A => N_159, B => paddr_0(2), C => N_69, Y => - prdata_3_sqmuxa_0); - - \prdata[23]\ : DFN1C0 - port map(D => \prdata_39[23]\, CLK => lclk_c, CLR => rstn, - Q => prdata(23)); - - \prdata_RNO_4[17]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[17]\, C => \addr_matrix_f0_1_m_i[17]\, - Y => \prdata_39_0_iv_1[17]\); - - \reg_wp.delta_f2_f0[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[6]\); - - \prdata_RNO_9[11]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[11]\, - Y => \addr_data_f1_m_i[11]\); - - \prdata_RNO_7[21]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[21]\, - Y => \addr_matrix_f0_1_m_i[21]\); - - \prdata_RNO_7[26]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[26]\, - Y => \addr_matrix_f0_1_m_i[26]\); - - \prdata_RNO[9]\ : OR3C - port map(A => \prdata_39_0_iv_9[9]\, B => - \prdata_39_0_iv_8[9]\, C => \prdata_39_0_iv_10[9]\, Y => - \prdata_39[9]\); - - \reg_wp.addr_data_f0[13]\ : DFN1E1C0 - port map(D => pwdata(13), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[13]\); - - \prdata_RNO_20[2]\ : NAND2 - port map(A => \delta_f2_f1[2]\, B => prdata_15_sqmuxa, Y - => \delta_f2_f1_m_i[2]\); - - \prdata_RNO_12[7]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[7]\, C - => \delta_f2_f1_m_i[7]\, Y => \prdata_39_0_iv_0[7]\); - - \reg_wp.addr_data_f0[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[10]\); - - \prdata_RNO_2[31]\ : NOR3C - port map(A => \prdata_39_0_iv_1[31]\, B => - \prdata_39_0_iv_0[31]\, C => \addr_data_f0_m_i[31]\, Y - => \prdata_39_0_iv_4[31]\); - - \prdata_RNO_13[3]\ : AOI1B - port map(A => \nb_burst_available[3]\, B => - prdata_17_sqmuxa, C => \nb_snapshot_param_m_i[3]\, Y => - \prdata_39_0_iv_1[3]\); - - \reg_sp.config_active_interruption_onError_0_sqmuxa_0_o2_0\ : - NOR3B - port map(A => N_116, B => N_769, C => - config_active_interruption_onError_0_sqmuxa_0_o2_0_0, Y - => N_68); - - \prdata_RNO_14[3]\ : NOR2B - port map(A => data_shaping_R0_m_i, B => - \addr_matrix_f1_m_i[3]\, Y => \prdata_39_0_iv_4[3]\); - - \prdata_RNO_3[31]\ : OR3B - port map(A => N_168, B => \addr_data_f2[31]\, C => N_232, Y - => \addr_data_f2_m_i[31]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0\ : NOR3B - port map(A => paddr(5), B => paddr(4), C => N_69, Y => - N_168); - - \prdata_RNO_5[5]\ : OR2B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[5]\, Y - => \addr_data_f0_m_i[5]\); - - \reg_wp.addr_data_f1[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[14]\); - - \reg_sp.addr_matrix_f2[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa_0, Q => \addr_matrix_f2[1]\); - - \reg_wp.delta_snapshot[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - delta_snapshot_1_sqmuxa, Q => \delta_snapshot[9]\); - - \prdata[30]\ : DFN1C0 - port map(D => \prdata_39[30]\, CLK => lclk_c, CLR => rstn, - Q => prdata(30)); - - \prdata_RNO_13[8]\ : NOR2B - port map(A => \nb_burst_available_m_i[8]\, B => - \nb_snapshot_param_m_i[8]\, Y => \prdata_39_0_iv_1[8]\); - - \reg_wp.status_new_err[3]\ : DFN1C0 - port map(D => N_65, CLK => lclk_c, CLR => rstn, Q => - \status_new_err[3]\); - - \reg_wp.addr_data_f1[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[0]\); - - \prdata_RNO_12[2]\ : AOI1B - port map(A => status_ready_matrix_f1, B => prdata_1_sqmuxa, - C => \prdata_39_0_iv_0[2]\, Y => \prdata_39_0_iv_2[2]\); - - \reg_wp.delta_f2_f0[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - delta_f2_f0_1_sqmuxa, Q => \delta_f2_f0[4]\); - - \prdata_RNO_12[1]\ : AOI1B - port map(A => prdata_0_sqmuxa, B => - config_active_interruption_onError, C => - \delta_f2_f0_m_i[1]\, Y => \prdata_39_0_iv_0[1]\); - - \prdata[11]\ : DFN1C0 - port map(D => \prdata_39[11]\, CLK => lclk_c, CLR => rstn, - Q => prdata(11)); - - \reg_sp.addr_matrix_f0_0[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[19]\); - - \reg_wp.addr_data_f2_1_sqmuxa_0_a2_0_0\ : NOR3B - port map(A => paddr(5), B => paddr_0(4), C => N_69, Y => - N_168_0); - - \reg_wp.addr_data_f0[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[11]\); - - \prdata_RNO_4[21]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[21]\, - C => \addr_matrix_f0_1_m_i[21]\, Y => - \prdata_39_0_iv_1[21]\); - - \prdata_RNO_4[26]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[26]\, - C => \addr_matrix_f0_1_m_i[26]\, Y => - \prdata_39_0_iv_1[26]\); - - \prdata_RNO_9[12]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[12]\, - Y => \addr_matrix_f2_m_i[12]\); - - \prdata_RNO_3[23]\ : OR3B - port map(A => N_168, B => \addr_data_f2[23]\, C => N_232, Y - => \addr_data_f2_m_i[23]\); - - \prdata_RNO_7[22]\ : OR2B - port map(A => prdata_3_sqmuxa, B => \addr_matrix_f0_1[22]\, - Y => \addr_matrix_f0_1_m_i[22]\); - - \reg_sp.addr_matrix_f0_1[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[5]\); - - \reg_wp.addr_data_f1[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[18]\); - - \prdata_RNO_2[27]\ : NOR3C - port map(A => \prdata_39_0_iv_1[27]\, B => - \prdata_39_0_iv_0[27]\, C => \addr_data_f0_m_i[27]\, Y - => \prdata_39_0_iv_4[27]\); - - \prdata_RNO_9[0]\ : NOR3C - port map(A => \prdata_39_0_iv_7[0]\, B => - \prdata_39_0_iv_6[0]\, C => \delta_snapshot_m_i[0]\, Y - => \prdata_39_0_iv_12[0]\); - - \reg_sp.status_ready_matrix_f0_1\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f0_1); - - \reg_sp.addr_matrix_f1[14]\ : DFN1E1C0 - port map(D => pwdata(14), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[14]\); - - \prdata_RNO_5[8]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[8]\, - Y => \addr_matrix_f0_1_m_i[8]\); - - \prdata_RNO[30]\ : OR3C - port map(A => \prdata_39_0_iv_3[30]\, B => - \addr_data_f1_m_i[30]\, C => \prdata_39_0_iv_4[30]\, Y - => \prdata_39[30]\); - - \apbo.pirq_RNO_2[15]\ : NOR3A - port map(A => \pirq_2_i_a2_5[15]\, B => status_full_0(1), C - => status_full_0(0), Y => \pirq_2_i_a2_8[15]\); - - \prdata_RNO_0[21]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[21]\, - C => \addr_data_f2_m_i[21]\, Y => \prdata_39_0_iv_3[21]\); - - \reg_sp.addr_matrix_f0_1[11]\ : DFN1E1C0 - port map(D => pwdata(11), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[11]\); - - \prdata_RNO_7[14]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[14]\, - Y => \addr_data_f1_m_i[14]\); - - \prdata_RNO_11[0]\ : AOI1B - port map(A => prdata_15_sqmuxa, B => \delta_f2_f1[0]\, C - => \nb_burst_available_m_i[0]\, Y => - \prdata_39_0_iv_1[0]\); - - \prdata_RNO_0[26]\ : AOI1B - port map(A => prdata_12_sqmuxa, B => \addr_data_f3[26]\, C - => \addr_data_f2_m_i[26]\, Y => \prdata_39_0_iv_3[26]\); - - \prdata_RNO_4[8]\ : NOR3C - port map(A => \prdata_39_0_iv_1[8]\, B => - \prdata_39_0_iv_0[8]\, C => \addr_matrix_f1_m_i[8]\, Y - => \prdata_39_0_iv_3[8]\); - - \reg_sp.addr_matrix_f0_0[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[5]\); - - prdata_12_sqmuxa_0_a2 : NOR2A - port map(A => N_168, B => N_6455, Y => prdata_12_sqmuxa); - - \prdata_RNO_21[3]\ : OR2B - port map(A => prdata_4_sqmuxa, B => \addr_matrix_f1[3]\, Y - => \addr_matrix_f1_m_i[3]\); - - \prdata_RNO_4[22]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[22]\, - C => \addr_matrix_f0_1_m_i[22]\, Y => - \prdata_39_0_iv_1[22]\); - - \reg_wp.addr_data_f0[9]\ : DFN1E1C0 - port map(D => pwdata(9), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[9]\); - - prdata_5_sqmuxa_0_a2 : NOR3 - port map(A => N_69, B => addr_matrix_f1_1_sqmuxa_0_a2_1_0, - C => N_6455, Y => prdata_5_sqmuxa); - - \reg_wp.addr_data_f2[2]\ : DFN1E1C0 - port map(D => pwdata(2), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[2]\); - - \prdata_RNO_6[30]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[30]\, Y - => \addr_data_f0_m_i[30]\); - - \prdata_RNO_6[24]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[24]\, Y - => \addr_data_f0_m_i[24]\); - - \reg_wp.addr_data_f0[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[25]\); - - \reg_sp.addr_matrix_f0_0[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[7]\); - - \prdata_RNO_17[2]\ : OR2B - port map(A => \nb_snapshot_param[2]\, B => prdata_18_sqmuxa, - Y => \nb_snapshot_param_m_i[2]\); - - \prdata_RNO_0[13]\ : NOR3C - port map(A => \prdata_39_0_iv_1[13]\, B => - \prdata_39_0_iv_0[13]\, C => \delta_snapshot_m_i[13]\, Y - => \prdata_39_0_iv_4[13]\); - - \reg_wp.nb_snapshot_param[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[8]\); - - \reg_wp.addr_data_f0[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa, Q => \addr_data_f0[26]\); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2\ : NOR3A - port map(A => N_160, B => N_69, C => - addr_matrix_f1_1_sqmuxa_0_a2_1_0, Y => - addr_matrix_f2_1_sqmuxa); - - \reg_wp.delta_snapshot_1_sqmuxa_0_a2\ : NOR3B - port map(A => paddr_0(4), B => N_166, C => N_72, Y => - delta_snapshot_1_sqmuxa); - - \reg_sp.addr_matrix_f0_1[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa, Q => \addr_matrix_f0_1[6]\); - - \prdata_RNO_1[25]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[25]\, Y - => \addr_data_f1_m_i[25]\); - - \reg_wp.addr_data_f1_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_166, B => paddr_0(4), C => N_72, Y => - addr_data_f1_1_sqmuxa_0); - - \prdata_RNO_15[1]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[1]\, - C => enable_f1_m_i, Y => \prdata_39_0_iv_6[1]\); - - \reg_wp.addr_data_f2[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa_0, Q => \addr_data_f2[17]\); - - \prdata_RNO[11]\ : OR3C - port map(A => \prdata_39_0_iv_5[11]\, B => - \prdata_39_0_iv_4[11]\, C => \prdata_39_0_iv_6[11]\, Y - => \prdata_39[11]\); - - \prdata[25]\ : DFN1C0 - port map(D => \prdata_39[25]\, CLK => lclk_c, CLR => rstn, - Q => prdata(25)); - - \prdata_RNO_1[8]\ : NOR3C - port map(A => \prdata_39_0_iv_3[8]\, B => - \addr_matrix_f0_1_m_i[8]\, C => \delta_snapshot_m_i[8]\, - Y => \prdata_39_0_iv_8[8]\); - - \prdata_RNO_0[22]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[22]\, - C => \addr_data_f2_m_i[22]\, Y => \prdata_39_0_iv_3[22]\); - - \prdata_RNO_4[31]\ : AOI1B - port map(A => prdata_2_sqmuxa, B => \addr_matrix_f0_0[31]\, - C => \addr_matrix_f0_1_m_i[31]\, Y => - \prdata_39_0_iv_1[31]\); - - \reg_wp.addr_data_f2[24]\ : DFN1E1C0 - port map(D => pwdata(24), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[24]\); - - \reg_wp.status_full_err_RNO_0[1]\ : OR2 - port map(A => \status_full_err[1]\, B => - status_full_err_0(1), Y => \status_full_err_5_i_a2_0[1]\); - - \reg_sp.addr_matrix_f2_1_sqmuxa_0_a2_0\ : NOR2 - port map(A => un1_apbi_0, B => N_6455, Y => N_160); - - \reg_sp.addr_matrix_f2[8]\ : DFN1E1C0 - port map(D => pwdata(8), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[8]\); - - \prdata_RNO_8[9]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[9]\, C => N_232_1, - Y => \addr_data_f2_m_i[9]\); - - \status_full_ack[3]\ : DFN1C0 - port map(D => \status_full_ack_8[3]\, CLK => lclk_c, CLR - => rstn, Q => status_full_ack(3)); - - \reg_wp.delta_f2_f0_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_158, B => N_160, C => rdata61_2, Y => - delta_f2_f0_1_sqmuxa); - - \prdata_RNO[29]\ : OR3C - port map(A => \prdata_39_0_iv_3[29]\, B => - \addr_data_f1_m_i[29]\, C => \prdata_39_0_iv_4[29]\, Y - => \prdata_39[29]\); - - \prdata_RNO_14[0]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[0]\, - C => \addr_matrix_f0_1_m_i[0]\, Y => - \prdata_39_0_iv_7[0]\); - - \prdata_RNO_6[5]\ : AOI1B - port map(A => prdata_8_sqmuxa, B => \burst_f1\, C => - \addr_matrix_f0_0_m_i[5]\, Y => \prdata_39_0_iv_5[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \prdata_RNO_8[29]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[29]\, Y - => \addr_matrix_f2_m_i[29]\); - - \reg_wp.status_full[0]\ : DFN1C0 - port map(D => N_43, CLK => lclk_c, CLR => rstn, Q => - \status_full[0]\); - - \reg_sp.addr_matrix_f0_1[18]\ : DFN1E1C0 - port map(D => pwdata(18), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_1_1_sqmuxa_0, Q => \addr_matrix_f0_1[18]\); - - \prdata_RNO[16]\ : OR3C - port map(A => \prdata_39_0_iv_3[16]\, B => - \addr_data_f1_m_i[16]\, C => \prdata_39_0_iv_4[16]\, Y - => \prdata_39[16]\); - - \prdata[0]\ : DFN1C0 - port map(D => \prdata_39[0]\, CLK => lclk_c, CLR => rstn, Q - => prdata(0)); - - \apbo.pirq_RNO_5[15]\ : NOR2 - port map(A => status_new_err_0(2), B => status_new_err_0(3), - Y => \pirq_2_i_a2_1[15]\); - - \reg_wp.addr_data_f0_1_sqmuxa_0_a2_0\ : NOR3A - port map(A => N_71, B => paddr_0(4), C => N_72, Y => - addr_data_f0_1_sqmuxa_0); - - \reg_wp.addr_data_f0[15]\ : DFN1E1C0 - port map(D => pwdata(15), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[15]\); - - prdata_9_sqmuxa_0_a2_0 : NOR3 - port map(A => paddr_0(4), B => N_72, C => paddr_0(2), Y => - prdata_9_sqmuxa_0); - - \reg_wp.addr_data_f3[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[6]\); - - \reg_wp.addr_data_f2[28]\ : DFN1E1C0 - port map(D => pwdata(28), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[28]\); - - \reg_wp.addr_data_f0[16]\ : DFN1E1C0 - port map(D => pwdata(16), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[16]\); - - \reg_wp.status_full_err[1]\ : DFN1C0 - port map(D => N_53, CLK => lclk_c, CLR => rstn, Q => - \status_full_err[1]\); - - \reg_wp.nb_burst_available[10]\ : DFN1E1C0 - port map(D => pwdata(10), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => - \nb_burst_available[10]\); - - \reg_wp.nb_snapshot_param[1]\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[1]\); - - \reg_wp.addr_data_f1[29]\ : DFN1E1C0 - port map(D => pwdata(29), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[29]\); - - \reg_sp.addr_matrix_f0_0[26]\ : DFN1E1C0 - port map(D => pwdata(26), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa, Q => \addr_matrix_f0_0[26]\); - - \prdata_RNO_7[4]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[4]\, C => N_232_1, - Y => \addr_data_f2_m_i[4]\); - - \prdata_RNO_5[20]\ : AOI1B - port map(A => prdata_4_sqmuxa_0, B => \addr_matrix_f1[20]\, - C => \addr_matrix_f2_m_i[20]\, Y => - \prdata_39_0_iv_0[20]\); - - \prdata_RNO_6[19]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[19]\, Y - => \addr_data_f0_m_i[19]\); - - \reg_wp.delta_f2_f1_1_sqmuxa_0_a2\ : NOR3B - port map(A => N_158, B => N_162, C => rdata61_2, Y => - delta_f2_f1_1_sqmuxa); - - \reg_wp.addr_data_f2[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_data_f2_1_sqmuxa, Q => \addr_data_f2[5]\); - - \reg_sp.addr_matrix_f1[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[3]\); - - \prdata_RNO_1[28]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[28]\, Y - => \addr_data_f1_m_i[28]\); - - \reg_sp.addr_matrix_f1[25]\ : DFN1E1C0 - port map(D => pwdata(25), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[25]\); - - \prdata_RNO_16[0]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[0]\, Y - => \delta_snapshot_m_i[0]\); - - \reg_wp.addr_data_f3[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[23]\); - - \reg_wp.addr_data_f3[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[20]\); - - \reg_wp.nb_burst_available[0]\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[0]\); - - \prdata_RNO_3[11]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[11]\, C => \addr_matrix_f0_1_m_i[11]\, - Y => \prdata_39_0_iv_1[11]\); - - \prdata_RNO_3[16]\ : OR3B - port map(A => N_168_0, B => \addr_data_f2[16]\, C => - N_232_1, Y => \addr_data_f2_m_i[16]\); - - \reg_wp.addr_data_f3[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa, Q => \addr_data_f3[4]\); - - \reg_sp.addr_matrix_f1[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa_0, Q => \addr_matrix_f1[22]\); - - \prdata_RNO_4[4]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[4]\, - C => \addr_matrix_f0_1_m_i[4]\, Y => - \prdata_39_0_iv_6[4]\); - - \prdata_RNO_7[13]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[13]\, - Y => \addr_data_f1_m_i[13]\); - - \prdata[9]\ : DFN1C0 - port map(D => \prdata_39[9]\, CLK => lclk_c, CLR => rstn, Q - => prdata(9)); - - \prdata[8]\ : DFN1C0 - port map(D => \prdata_39[8]\, CLK => lclk_c, CLR => rstn, Q - => prdata(8)); - - \prdata_RNO_10[3]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => \addr_matrix_f0_1[3]\, - Y => \addr_matrix_f0_1_m_i[3]\); - - \reg_sp.addr_matrix_f1[27]\ : DFN1E1C0 - port map(D => pwdata(27), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[27]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg_wp.addr_data_f3[21]\ : DFN1E1C0 - port map(D => pwdata(21), CLK => lclk_c, CLR => rstn, E => - addr_data_f3_1_sqmuxa_0, Q => \addr_data_f3[21]\); - - \prdata_RNO_6[23]\ : OR2B - port map(A => prdata_9_sqmuxa, B => \addr_data_f0[23]\, Y - => \addr_data_f0_m_i[23]\); - - \prdata_RNO_18[5]\ : OR2B - port map(A => \nb_burst_available[5]\, B => - prdata_17_sqmuxa, Y => \nb_burst_available_m_i[5]\); - - \reg_wp.addr_data_f0[22]\ : DFN1E1C0 - port map(D => pwdata(22), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[22]\); - - \prdata[22]\ : DFN1C0 - port map(D => \prdata_39[22]\, CLK => lclk_c, CLR => rstn, - Q => prdata(22)); - - \prdata_RNO_5[3]\ : AOI1B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[3]\, - C => enable_f3_m_i, Y => \prdata_39_0_iv_5[3]\); - - \prdata_RNO_11[5]\ : NOR2B - port map(A => \nb_burst_available_m_i[5]\, B => - \nb_snapshot_param_m_i[5]\, Y => \prdata_39_0_iv_1[5]\); - - \reg_sp.addr_matrix_f0_0[17]\ : DFN1E1C0 - port map(D => pwdata(17), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[17]\); - - prdata_10_sqmuxa_0_a2 : NOR3A - port map(A => paddr_2(2), B => paddr_0(4), C => N_72, Y => - prdata_10_sqmuxa); - - \prdata[29]\ : DFN1C0 - port map(D => \prdata_39[29]\, CLK => lclk_c, CLR => rstn, - Q => prdata(29)); - - \prdata_RNO_4[6]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => \addr_matrix_f0_0[6]\, - C => \addr_matrix_f0_1_m_i[6]\, Y => - \prdata_39_0_iv_5[6]\); - - \reg_wp.nb_snapshot_param[4]\ : DFN1E1C0 - port map(D => pwdata(4), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[4]\); - - \reg_wp.nb_snapshot_param[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - nb_snapshot_param_1_sqmuxa, Q => \nb_snapshot_param[7]\); - - \reg_wp.addr_data_f1[19]\ : DFN1E1C0 - port map(D => pwdata(19), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa_0, Q => \addr_data_f1[19]\); - - \prdata_RNO_3[20]\ : OR3B - port map(A => N_168, B => \addr_data_f2[20]\, C => N_232, Y - => \addr_data_f2_m_i[20]\); - - \prdata_RNO_3[12]\ : AOI1B - port map(A => prdata_2_sqmuxa_0, B => - \addr_matrix_f0_0[12]\, C => \addr_matrix_f0_1_m_i[12]\, - Y => \prdata_39_0_iv_1[12]\); - - \reg_sp.addr_matrix_f2[5]\ : DFN1E1C0 - port map(D => pwdata(5), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f2_1_sqmuxa, Q => \addr_matrix_f2[5]\); - - \prdata_RNO_9[4]\ : NOR3C - port map(A => \prdata_39_0_iv_4[4]\, B => - \prdata_39_0_iv_3[4]\, C => \addr_data_f3_m_i[4]\, Y => - \prdata_39_0_iv_10[4]\); - - \prdata_RNO[4]\ : OR3C - port map(A => \prdata_39_0_iv_12[4]\, B => - \prdata_39_0_iv_11[4]\, C => \prdata_39_0_iv_13[4]\, Y - => \prdata_39[4]\); - - \prdata_RNO_1[14]\ : AOI1B - port map(A => prdata_12_sqmuxa_0, B => \addr_data_f3[14]\, - C => \addr_data_f2_m_i[14]\, Y => \prdata_39_0_iv_3[14]\); - - \prdata_RNO_6[9]\ : OR2B - port map(A => prdata_14_sqmuxa, B => \delta_snapshot[9]\, Y - => \delta_snapshot_m_i[9]\); - - \reg_sp.addr_matrix_f1[31]\ : DFN1E1C0 - port map(D => pwdata(31), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[31]\); - - \prdata_RNO_4[1]\ : NOR3C - port map(A => \prdata_39_0_iv_1[1]\, B => - \prdata_39_0_iv_0[1]\, C => \prdata_39_0_iv_2[1]\, Y => - \prdata_39_0_iv_4[1]\); - - \reg_wp.nb_burst_available[3]\ : DFN1E1C0 - port map(D => pwdata(3), CLK => lclk_c, CLR => rstn, E => - nb_burst_available_1_sqmuxa, Q => \nb_burst_available[3]\); - - \reg_sp.addr_matrix_f1[30]\ : DFN1E1C0 - port map(D => pwdata(30), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f1_1_sqmuxa, Q => \addr_matrix_f1[30]\); - - \prdata_RNO_8[11]\ : OR2B - port map(A => \status_new_err[3]\, B => prdata_13_sqmuxa, Y - => \status_new_err_m_i[3]\); - - \prdata_RNO_8[16]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[16]\, Y - => \addr_matrix_f2_m_i[16]\); - - \reg_wp.nb_burst_available_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_158, B => N_159, C => N_71, Y => - nb_burst_available_1_sqmuxa); - - \reg_sp.status_ready_matrix_f0_0\ : DFN1E1C0 - port map(D => pwdata(0), CLK => lclk_c, CLR => rstn, E => - status_error_anticipating_empty_fifo_1_sqmuxa, Q => - status_ready_matrix_f0_0); - - \prdata_RNO_0[2]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[2]\, C - => \addr_data_f1_m_i[2]\, Y => \prdata_39_0_iv_12[2]\); - - \reg_wp.addr_data_f1[6]\ : DFN1E1C0 - port map(D => pwdata(6), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[6]\); - - \prdata_RNO_10[10]\ : OR2B - port map(A => \status_new_err[2]\, B => prdata_13_sqmuxa, Y - => \status_new_err_m_i[2]\); - - \reg_wp.addr_data_f1[7]\ : DFN1E1C0 - port map(D => pwdata(7), CLK => lclk_c, CLR => rstn, E => - addr_data_f1_1_sqmuxa, Q => \addr_data_f1[7]\); - - \reg_wp.addr_data_f0[12]\ : DFN1E1C0 - port map(D => pwdata(12), CLK => lclk_c, CLR => rstn, E => - addr_data_f0_1_sqmuxa_0, Q => \addr_data_f0[12]\); - - \prdata_RNO_8[25]\ : OR2B - port map(A => prdata_5_sqmuxa, B => \addr_matrix_f2[25]\, Y - => \addr_matrix_f2_m_i[25]\); - - \prdata_RNO_1[27]\ : OR2B - port map(A => prdata_10_sqmuxa, B => \addr_data_f1[27]\, Y - => \addr_data_f1_m_i[27]\); - - \reg_sp.addr_matrix_f0_0[20]\ : DFN1E1C0 - port map(D => pwdata(20), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[20]\); - - \prdata_RNO_18[4]\ : NOR2B - port map(A => status_error_anticipating_empty_fifo_m_i, B - => \prdata_39_0_iv_0[4]\, Y => \prdata_39_0_iv_2[4]\); - - \prdata_RNO_20[4]\ : AOI1B - port map(A => prdata_16_sqmuxa, B => \delta_f2_f0[4]\, C - => \delta_f2_f1_m_i[4]\, Y => \prdata_39_0_iv_0[4]\); - - \prdata_RNO_0[10]\ : AOI1B - port map(A => prdata_9_sqmuxa_0, B => \addr_data_f0[10]\, C - => \prdata_39_0_iv_4[10]\, Y => \prdata_39_0_iv_7[10]\); - - \reg_wp.nb_snapshot_param_1_sqmuxa_0_a2\ : NOR3C - port map(A => N_158, B => N_159, C => N_166, Y => - nb_snapshot_param_1_sqmuxa); - - \reg_wp.enable_f1\ : DFN1E1C0 - port map(D => pwdata(1), CLK => lclk_c, CLR => rstn, E => - burst_f0_1_sqmuxa, Q => \enable_f1\); - - \reg_sp.addr_matrix_f0_0[23]\ : DFN1E1C0 - port map(D => pwdata(23), CLK => lclk_c, CLR => rstn, E => - addr_matrix_f0_0_1_sqmuxa_0, Q => \addr_matrix_f0_0[23]\); - - \prdata_RNO_4[9]\ : NOR3C - port map(A => \prdata_39_0_iv_1[9]\, B => - \prdata_39_0_iv_0[9]\, C => \addr_matrix_f1_m_i[9]\, Y - => \prdata_39_0_iv_3[9]\); - - \prdata_RNO_10[15]\ : OR2B - port map(A => prdata_5_sqmuxa_0, B => \addr_matrix_f2[15]\, - Y => \addr_matrix_f2_m_i[15]\); - - \prdata_RNO_8[12]\ : OR2B - port map(A => prdata_3_sqmuxa_0, B => - \addr_matrix_f0_1[12]\, Y => \addr_matrix_f0_1_m_i[12]\); - - \prdata[4]\ : DFN1C0 - port map(D => \prdata_39[4]\, CLK => lclk_c, CLR => rstn, Q - => prdata(4)); - - \prdata_RNO_6[15]\ : OR2B - port map(A => prdata_10_sqmuxa_0, B => \addr_data_f1[15]\, - Y => \addr_data_f1_m_i[15]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_2 is - - port( S_0 : in std_logic_vector(8 to 8); - S_i : in std_logic_vector(1 to 1); - alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff : in std_logic_vector(4 downto 2); - S_26 : in std_logic; - S_6 : in std_logic; - S_15 : in std_logic; - S_22 : in std_logic; - S_8 : in std_logic; - S_12 : in std_logic; - S_20 : in std_logic; - S_2 : in std_logic; - S_33 : in std_logic; - S_11 : in std_logic; - S_19 : in std_logic; - S_0_d0 : in std_logic; - S_17 : in std_logic; - S_51 : in std_logic; - S_10 : in std_logic; - S_9 : in std_logic; - S_25 : in std_logic; - S_7 : in std_logic; - S_16 : in std_logic; - S_13 : in std_logic; - S_23 : in std_logic; - S_5 : in std_logic - ); - -end MUXN_9_2; - -architecture DEF_ARCH of MUXN_9_2 is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_47, N_28, N_19, N_43, N_40, N_37, N_25, N_16, N_56, - N_55, N_52, N_53, N_49, N_50, N_48, N_44, N_45, N_42, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \NB_STAGE_2.all_input.6.RES_8_1[6]\ : MX2C - port map(A => S_2, B => S_20, S => alu_sel_coeff(4), Y => - N_52); - - \NB_STAGE_2.all_input.7.RES_6_3[7]\ : MX2 - port map(A => N_55, B => N_37, S => alu_sel_coeff(3), Y => - alu_coef_s(7)); - - \NB_STAGE_2.all_input.7.RES_6_2[7]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_10, Y => N_37); - - \NB_STAGE_2.all_input.4.RES_12_1[4]\ : MX2 - port map(A => S_2, B => S_22, S => alu_sel_coeff(4), Y => - N_48); - - \NB_STAGE_2.all_input.0.RES_20_2[0]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_17, Y => N_16); - - \NB_STAGE_2.all_input.2.RES_16_2[2]\ : MX2C - port map(A => S_15, B => S_33, S => alu_sel_coeff(4), Y => - N_45); - - \NB_STAGE_2.all_input.1.RES_18_1[1]\ : MX2C - port map(A => S_7, B => S_25, S => alu_sel_coeff(4), Y => - N_43); - - GND_i_0 : GND - port map(Y => GND_0); - - \NB_STAGE_2.all_input.2.RES_16_3[2]\ : MX2 - port map(A => N_44, B => N_45, S => alu_sel_coeff(3), Y => - alu_coef_s(2)); - - \NB_STAGE_2.all_input.2.RES_16_1[2]\ : MX2C - port map(A => S_6, B => S_11, S => alu_sel_coeff(4), Y => - N_44); - - VCC_i : VCC - port map(Y => \VCC\); - - \NB_STAGE_2.all_input.6.RES_8_2[6]\ : MX2B - port map(A => S_11, B => S_33, S => alu_sel_coeff(4), Y => - N_53); - - \NB_STAGE_2.all_input.3.RES_14_1[3]\ : MX2C - port map(A => S_5, B => S_23, S => alu_sel_coeff(4), Y => - N_47); - - \NB_STAGE_2.all_input.3.RES_14_2[3]\ : OA1C - port map(A => S_51, B => alu_sel_coeff(2), C => - alu_sel_coeff(4), Y => N_25); - - GND_i : GND - port map(Y => \GND\); - - \NB_STAGE_2.all_input.3.RES_14_3[3]\ : MX2 - port map(A => N_47, B => N_25, S => alu_sel_coeff(3), Y => - alu_coef_s(3)); - - \NB_STAGE_2.all_input.8.RES_4_3[8]\ : MX2 - port map(A => N_56, B => N_40, S => alu_sel_coeff(3), Y => - alu_coef_s(8)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \NB_STAGE_2.all_input.1.RES_18_3[1]\ : MX2 - port map(A => N_43, B => N_19, S => alu_sel_coeff(3), Y => - alu_coef_s(1)); - - \NB_STAGE_2.all_input.6.RES_8_3[6]\ : MX2 - port map(A => N_52, B => N_53, S => alu_sel_coeff(3), Y => - alu_coef_s(6)); - - \NB_STAGE_2.all_input.8.RES_4_1[8]\ : MX2C - port map(A => S_0_d0, B => S_19, S => alu_sel_coeff(4), Y - => N_56); - - \NB_STAGE_2.all_input.4.RES_12_3[4]\ : MX2 - port map(A => N_48, B => N_28, S => alu_sel_coeff(3), Y => - alu_coef_s(4)); - - \NB_STAGE_2.all_input.4.RES_12_2[4]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_13, Y => N_28); - - \NB_STAGE_2.all_input.0.RES_20_3[0]\ : MX2 - port map(A => N_42, B => N_16, S => alu_sel_coeff(3), Y => - alu_coef_s(0)); - - \NB_STAGE_2.all_input.8.RES_4_2[8]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_9, Y => N_40); - - \NB_STAGE_2.all_input.7.RES_6_1[7]\ : MX2C - port map(A => S_i(1), B => S_19, S => alu_sel_coeff(4), Y - => N_55); - - \NB_STAGE_2.all_input.1.RES_18_2[1]\ : NOR2 - port map(A => alu_sel_coeff(4), B => S_16, Y => N_19); - - \NB_STAGE_2.all_input.5.RES_10_1[5]\ : MX2C - port map(A => S_5, B => S_8, S => alu_sel_coeff(4), Y => - N_49); - - \NB_STAGE_2.all_input.5.RES_10_2[5]\ : MX2C - port map(A => S_12, B => S_33, S => alu_sel_coeff(4), Y => - N_50); - - \NB_STAGE_2.all_input.5.RES_10_3[5]\ : MX2 - port map(A => N_49, B => N_50, S => alu_sel_coeff(3), Y => - alu_coef_s(5)); - - \NB_STAGE_2.all_input.0.RES_20_1[0]\ : MX2C - port map(A => S_0(8), B => S_26, S => alu_sel_coeff(4), Y - => N_42); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_3 is - - port( S_0 : in std_logic_vector(8 to 8); - alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff : in std_logic_vector(4 downto 0); - S_51 : in std_logic; - S_44 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff_0_2 : in std_logic - ); - -end MUXN_9_3; - -architecture DEF_ARCH of MUXN_9_3 is - - component MUXN_9_2 - port( S_0 : in std_logic_vector(8 to 8) := (others => 'U'); - S_i : in std_logic_vector(1 to 1) := (others => 'U'); - alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff : in std_logic_vector(4 downto 2) := (others => 'U'); - S_26 : in std_logic := 'U'; - S_6 : in std_logic := 'U'; - S_15 : in std_logic := 'U'; - S_22 : in std_logic := 'U'; - S_8 : in std_logic := 'U'; - S_12 : in std_logic := 'U'; - S_20 : in std_logic := 'U'; - S_2 : in std_logic := 'U'; - S_33 : in std_logic := 'U'; - S_11 : in std_logic := 'U'; - S_19 : in std_logic := 'U'; - S_0_d0 : in std_logic := 'U'; - S_17 : in std_logic := 'U'; - S_51 : in std_logic := 'U'; - S_10 : in std_logic := 'U'; - S_9 : in std_logic := 'U'; - S_25 : in std_logic := 'U'; - S_7 : in std_logic := 'U'; - S_16 : in std_logic := 'U'; - S_13 : in std_logic := 'U'; - S_23 : in std_logic := 'U'; - S_5 : in std_logic := 'U' - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO14 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO6 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AO16 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO17 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \S[23]_net_1\, \S[16]_net_1\, \S[25]_net_1\, - \S[13]_net_1\, \S[7]_net_1\, \S[12]_net_1\, \S[2]_net_1\, - \S[33]\, \S[19]\, \S[10]_net_1\, \S[9]_net_1\, \S_i[1]\, - \S[0]_net_1\, \S[22]_net_1\, \S[20]_net_1\, \S[17]_net_1\, - \S[5]\, \S[26]_net_1\, \S[15]_net_1\, \S[11]_net_1\, - \S[8]_net_1\, \S[6]_net_1\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : MUXN_9_2 - Use entity work.MUXN_9_2(DEF_ARCH); -begin - - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_2 - port map(S_0(8) => \S[8]_net_1\, S_i(1) => \S_i[1]\, - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_sel_coeff(4) => alu_sel_coeff(4), alu_sel_coeff(3) - => alu_sel_coeff(3), alu_sel_coeff(2) => - alu_sel_coeff(2), S_26 => \S[26]_net_1\, S_6 => - \S[6]_net_1\, S_15 => \S[15]_net_1\, S_22 => - \S[22]_net_1\, S_8 => S_0(8), S_12 => \S[12]_net_1\, S_20 - => \S[20]_net_1\, S_2 => \S[2]_net_1\, S_33 => \S[33]\, - S_11 => \S[11]_net_1\, S_19 => \S[19]\, S_0_d0 => - \S[0]_net_1\, S_17 => \S[17]_net_1\, S_51 => S_51, S_10 - => \S[10]_net_1\, S_9 => \S[9]_net_1\, S_25 => - \S[25]_net_1\, S_7 => \S[7]_net_1\, S_16 => \S[16]_net_1\, - S_13 => \S[13]_net_1\, S_23 => \S[23]_net_1\, S_5 => - \S[5]\); - - \S[26]\ : AX1B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[26]_net_1\); - - \S[13]\ : XO1A - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[13]_net_1\); - - \S[3]\ : XA1 - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(2), C - => alu_sel_coeff(1), Y => \S[5]\); - - \S[9]\ : AO14 - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[9]_net_1\); - - \S[23]\ : NOR2 - port map(A => alu_sel_coeff_0_2, B => S_44, Y => - \S[23]_net_1\); - - \S[15]\ : AXOI5 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[15]_net_1\); - - \S[11]\ : XA1 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[11]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \S[8]\ : AXO5 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(0), C - => alu_sel_coeff(2), Y => \S[8]_net_1\); - - \S[6]\ : AXO6 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[6]_net_1\); - - \S[25]\ : AXOI3 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[25]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \S[17]\ : AO16 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(1), C - => alu_sel_coeff(0), Y => \S[17]_net_1\); - - \S[10]\ : AO17 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[10]_net_1\); - - \S[20]\ : AO1C - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(2), C - => alu_sel_coeff(1), Y => \S[20]_net_1\); - - \S[7]\ : AO16 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_0, C - => alu_sel_coeff_0_2, Y => \S[7]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \S[18]\ : XAI1A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff_0_2, C - => alu_sel_coeff(1), Y => \S[19]\); - - \S[0]\ : AXO5 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff(2), C - => alu_sel_coeff(0), Y => \S[0]_net_1\); - - \S[29]\ : OR3 - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), C - => alu_sel_coeff_0_2, Y => \S[33]\); - - \S[1]\ : XNOR2 - port map(A => alu_sel_coeff(2), B => alu_sel_coeff(0), Y - => \S_i[1]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \S[12]\ : AO1A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), C - => alu_sel_coeff_0_2, Y => \S[12]_net_1\); - - \S[22]\ : AXOI5 - port map(A => alu_sel_coeff(0), B => alu_sel_coeff(2), C - => alu_sel_coeff(1), Y => \S[22]_net_1\); - - \S[2]\ : OR3B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_2, C - => alu_sel_coeff_0_0, Y => \S[2]_net_1\); - - \S[16]\ : MX2B - port map(A => alu_sel_coeff_0_2, B => alu_sel_coeff_0_0, S - => alu_sel_coeff(1), Y => \S[16]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_4 is - - port( alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0); - S_0 : out std_logic; - S_36 : out std_logic - ); - -end MUXN_9_4; - -architecture DEF_ARCH of MUXN_9_4 is - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MUXN_9_3 - port( S_0 : in std_logic_vector(8 to 8) := (others => 'U'); - alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - S_51 : in std_logic := 'U'; - S_44 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : in std_logic := 'U' - ); - end component; - - signal \S[51]\, \S[8]_net_1\, \S[44]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : MUXN_9_3 - Use entity work.MUXN_9_3(DEF_ARCH); -begin - - S_0 <= \S[8]_net_1\; - S_36 <= \S[44]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \S_0[28]\ : XOR2 - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_0, Y - => \S[44]\); - - \S[8]\ : OR2B - port map(A => alu_sel_coeff(1), B => alu_sel_coeff_0_0, Y - => \S[8]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \S[23]\ : NOR2A - port map(A => alu_sel_coeff_0_0, B => alu_sel_coeff(1), Y - => \S[51]\); - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_3 - port map(S_0(8) => \S[8]_net_1\, alu_coef_s(8) => - alu_coef_s(8), alu_coef_s(7) => alu_coef_s(7), - alu_coef_s(6) => alu_coef_s(6), alu_coef_s(5) => - alu_coef_s(5), alu_coef_s(4) => alu_coef_s(4), - alu_coef_s(3) => alu_coef_s(3), alu_coef_s(2) => - alu_coef_s(2), alu_coef_s(1) => alu_coef_s(1), - alu_coef_s(0) => alu_coef_s(0), alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_sel_coeff(2) => alu_sel_coeff(2), alu_sel_coeff(1) - => alu_sel_coeff(1), alu_sel_coeff(0) => - alu_sel_coeff(0), S_51 => \S[51]\, S_44 => \S[44]\, - alu_sel_coeff_0_0 => alu_sel_coeff_0_0, alu_sel_coeff_0_2 - => alu_sel_coeff_0_2); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MUXN_9_5 is - - port( S_36 : out std_logic; - S_0 : out std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0); - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff_0_2 : in std_logic; - alu_coef_s : out std_logic_vector(8 downto 0) - ); - -end MUXN_9_5; - -architecture DEF_ARCH of MUXN_9_5 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MUXN_9_4 - port( alu_coef_s : out std_logic_vector(8 downto 0); - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - S_0 : out std_logic; - S_36 : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : MUXN_9_4 - Use entity work.MUXN_9_4(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \NB_STAGE_PLUS.MUXN_1\ : MUXN_9_4 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_sel_coeff_0_2 => alu_sel_coeff_0_2, alu_sel_coeff_0_0 - => alu_sel_coeff_0_0, alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_sel_coeff(2) => alu_sel_coeff(2), alu_sel_coeff(1) - => alu_sel_coeff(1), alu_sel_coeff(0) => - alu_sel_coeff(0), S_0 => S_0, S_36 => S_36); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_18 is - - port( alu_sample : in std_logic_vector(17 downto 0); - OP1_2C_D : out std_logic_vector(17 downto 0); - rstn : in std_logic; - lclk_c : in std_logic - ); - -end MAC_REG_18; - -architecture DEF_ARCH of MAC_REG_18 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[6]\ : DFN1C0 - port map(D => alu_sample(6), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(6)); - - \Q[13]\ : DFN1C0 - port map(D => alu_sample(13), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(13)); - - \Q[14]\ : DFN1C0 - port map(D => alu_sample(14), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(14)); - - \Q[15]\ : DFN1C0 - port map(D => alu_sample(15), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(15)); - - \Q[11]\ : DFN1C0 - port map(D => alu_sample(11), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(11)); - - GND_i_0 : GND - port map(Y => GND_0); - - \Q[2]\ : DFN1C0 - port map(D => alu_sample(2), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(2)); - - \Q[4]\ : DFN1C0 - port map(D => alu_sample(4), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(4)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[17]\ : DFN1C0 - port map(D => alu_sample(17), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(17)); - - \Q[10]\ : DFN1C0 - port map(D => alu_sample(10), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(10)); - - GND_i : GND - port map(Y => \GND\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[3]\ : DFN1C0 - port map(D => alu_sample(3), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(3)); - - \Q[7]\ : DFN1C0 - port map(D => alu_sample(7), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(7)); - - \Q[12]\ : DFN1C0 - port map(D => alu_sample(12), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(12)); - - \Q[8]\ : DFN1C0 - port map(D => alu_sample(8), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(8)); - - \Q[1]\ : DFN1C0 - port map(D => alu_sample(1), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(1)); - - \Q[0]\ : DFN1C0 - port map(D => alu_sample(0), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(0)); - - \Q[9]\ : DFN1C0 - port map(D => alu_sample(9), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(9)); - - \Q[5]\ : DFN1C0 - port map(D => alu_sample(5), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(5)); - - \Q[16]\ : DFN1C0 - port map(D => alu_sample(16), CLK => lclk_c, CLR => rstn, Q - => OP1_2C_D(16)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_9 is - - port( alu_coef_s : in std_logic_vector(8 downto 0); - OP2_2C_D : out std_logic_vector(8 downto 0); - rstn : in std_logic; - lclk_c : in std_logic - ); - -end MAC_REG_9; - -architecture DEF_ARCH of MAC_REG_9 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[5]\ : DFN1C0 - port map(D => alu_coef_s(5), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(5)); - - \Q[3]\ : DFN1C0 - port map(D => alu_coef_s(3), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(3)); - - \Q[8]\ : DFN1C0 - port map(D => alu_coef_s(8), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(8)); - - \Q[7]\ : DFN1C0 - port map(D => alu_coef_s(7), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(7)); - - \Q[1]\ : DFN1C0 - port map(D => alu_coef_s(1), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(1)); - - \Q[2]\ : DFN1C0 - port map(D => alu_coef_s(2), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(2)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[6]\ : DFN1C0 - port map(D => alu_coef_s(6), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(6)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[0]\ : DFN1C0 - port map(D => alu_coef_s(0), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(0)); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \Q[4]\ : DFN1C0 - port map(D => alu_coef_s(4), CLK => lclk_c, CLR => rstn, Q - => OP2_2C_D(4)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_4 is - - port( MACMUX2sel_D : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - MACMUX2sel_D_D : out std_logic - ); - -end MAC_REG_1_4; - -architecture DEF_ARCH of MAC_REG_1_4 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[0]\ : DFN1C0 - port map(D => MACMUX2sel_D, CLK => lclk_c, CLR => rstn, Q - => MACMUX2sel_D_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_CONTROLER is - - port( alu_ctrl : in std_logic_vector(1 downto 0); - mult : out std_logic; - N_4 : out std_logic; - MACMUX2sel : out std_logic; - mult_0 : out std_logic - ); - -end MAC_CONTROLER; - -architecture DEF_ARCH of MAC_CONTROLER is - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_mult_i : NOR2B - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => N_4); - - GND_i_0 : GND - port map(Y => GND_0); - - un2_mult_i_x2 : XOR2 - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => mult); - - VCC_i : VCC - port map(Y => \VCC\); - - un2_mult_i_x2_0 : XOR2 - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => mult_0); - - un1_add_0_a2 : NOR2A - port map(A => alu_ctrl(1), B => alu_ctrl(0), Y => - MACMUX2sel); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_MUX is - - port( OP1_2C_D : in std_logic_vector(17 downto 0); - MULTout : in std_logic_vector(24 downto 0); - ADDERinB : out std_logic_vector(24 downto 0); - OP2_2C_D : in std_logic_vector(8 downto 0); - ADDERout : in std_logic_vector(24 downto 0); - ADDERinA : out std_logic_vector(24 downto 0); - MACMUXsel_D : in std_logic; - MACMUXsel_D_1 : in std_logic; - MACMUXsel_D_0 : in std_logic - ); - -end MAC_MUX; - -architecture DEF_ARCH of MAC_MUX is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \OUTA[24]\ : MX2C - port map(A => ADDERout(24), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA(24)); - - \OUTB[3]\ : MX2 - port map(A => MULTout(3), B => OP1_2C_D(3), S => - MACMUXsel_D_1, Y => ADDERinB(3)); - - \OUTB[9]\ : MX2 - port map(A => MULTout(9), B => OP1_2C_D(9), S => - MACMUXsel_D_1, Y => ADDERinB(9)); - - \OUTA[0]\ : MX2 - port map(A => ADDERout(0), B => OP2_2C_D(0), S => - MACMUXsel_D_0, Y => ADDERinA(0)); - - \OUTA[3]\ : MX2 - port map(A => ADDERout(3), B => OP2_2C_D(3), S => - MACMUXsel_D_0, Y => ADDERinA(3)); - - \OUTB[11]\ : MX2 - port map(A => MULTout(11), B => OP1_2C_D(11), S => - MACMUXsel_D_1, Y => ADDERinB(11)); - - \OUTB[23]\ : MX2 - port map(A => MULTout(23), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(23)); - - \OUTB[12]\ : MX2 - port map(A => MULTout(12), B => OP1_2C_D(12), S => - MACMUXsel_D_1, Y => ADDERinB(12)); - - \OUTB[20]\ : MX2 - port map(A => MULTout(20), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(20)); - - \OUTB[19]\ : MX2 - port map(A => MULTout(19), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(19)); - - \OUTA[13]\ : MX2 - port map(A => ADDERout(13), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(13)); - - \OUTB[8]\ : MX2 - port map(A => MULTout(8), B => OP1_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinB(8)); - - \OUTA[10]\ : MX2 - port map(A => ADDERout(10), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(10)); - - VCC_i : VCC - port map(Y => \VCC\); - - \OUTB[6]\ : MX2 - port map(A => MULTout(6), B => OP1_2C_D(6), S => - MACMUXsel_D, Y => ADDERinB(6)); - - \OUTA[6]\ : MX2 - port map(A => ADDERout(6), B => OP2_2C_D(6), S => - MACMUXsel_D, Y => ADDERinA(6)); - - \OUTB[24]\ : MX2 - port map(A => MULTout(24), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(24)); - - \OUTA[14]\ : MX2 - port map(A => ADDERout(14), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(14)); - - \OUTB[2]\ : MX2 - port map(A => MULTout(2), B => OP1_2C_D(2), S => - MACMUXsel_D_1, Y => ADDERinB(2)); - - \OUTB[13]\ : MX2 - port map(A => MULTout(13), B => OP1_2C_D(13), S => - MACMUXsel_D_1, Y => ADDERinB(13)); - - \OUTB[10]\ : MX2 - port map(A => MULTout(10), B => OP1_2C_D(10), S => - MACMUXsel_D_1, Y => ADDERinB(10)); - - \OUTA[9]\ : MX2 - port map(A => ADDERout(9), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(9)); - - \OUTA[15]\ : MX2C - port map(A => ADDERout(15), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(15)); - - \OUTA[16]\ : MX2 - port map(A => ADDERout(16), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(16)); - - \OUTA[7]\ : MX2 - port map(A => ADDERout(7), B => OP2_2C_D(7), S => - MACMUXsel_D_0, Y => ADDERinA(7)); - - \OUTB[5]\ : MX2 - port map(A => MULTout(5), B => OP1_2C_D(5), S => - MACMUXsel_D_1, Y => ADDERinB(5)); - - \OUTB[14]\ : MX2 - port map(A => MULTout(14), B => OP1_2C_D(14), S => - MACMUXsel_D_1, Y => ADDERinB(14)); - - GND_i : GND - port map(Y => \GND\); - - \OUTA[18]\ : MX2 - port map(A => ADDERout(18), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(18)); - - \OUTB[4]\ : MX2 - port map(A => MULTout(4), B => OP1_2C_D(4), S => - MACMUXsel_D_1, Y => ADDERinB(4)); - - \OUTB[15]\ : MX2 - port map(A => MULTout(15), B => OP1_2C_D(15), S => - MACMUXsel_D_1, Y => ADDERinB(15)); - - \OUTB[16]\ : MX2 - port map(A => MULTout(16), B => OP1_2C_D(16), S => - MACMUXsel_D, Y => ADDERinB(16)); - - \OUTA[21]\ : MX2 - port map(A => ADDERout(21), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA(21)); - - \OUTA[22]\ : MX2C - port map(A => ADDERout(22), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA(22)); - - \OUTA[17]\ : MX2C - port map(A => ADDERout(17), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA(17)); - - \OUTB[18]\ : MX2 - port map(A => MULTout(18), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(18)); - - \OUTA[4]\ : MX2 - port map(A => ADDERout(4), B => OP2_2C_D(4), S => - MACMUXsel_D_0, Y => ADDERinA(4)); - - \OUTA[1]\ : MX2C - port map(A => ADDERout(1), B => OP2_2C_D(1), S => - MACMUXsel_D, Y => ADDERinA(1)); - - \OUTB[7]\ : MX2 - port map(A => MULTout(7), B => OP1_2C_D(7), S => - MACMUXsel_D_1, Y => ADDERinB(7)); - - \OUTA[2]\ : MX2 - port map(A => ADDERout(2), B => OP2_2C_D(2), S => - MACMUXsel_D_0, Y => ADDERinA(2)); - - \OUTA[23]\ : MX2 - port map(A => ADDERout(23), B => OP2_2C_D(8), S => - MACMUXsel_D_1, Y => ADDERinA(23)); - - \OUTA[20]\ : MX2 - port map(A => ADDERout(20), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(20)); - - \OUTB[17]\ : MX2 - port map(A => MULTout(17), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(17)); - - \OUTB[21]\ : MX2 - port map(A => MULTout(21), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(21)); - - \OUTA[8]\ : MX2 - port map(A => ADDERout(8), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(8)); - - \OUTB[22]\ : MX2 - port map(A => MULTout(22), B => OP1_2C_D(17), S => - MACMUXsel_D, Y => ADDERinB(22)); - - \OUTB[0]\ : MX2 - port map(A => MULTout(0), B => OP1_2C_D(0), S => - MACMUXsel_D_1, Y => ADDERinB(0)); - - \OUTA[11]\ : MX2 - port map(A => ADDERout(11), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(11)); - - \OUTB[1]\ : MX2 - port map(A => MULTout(1), B => OP1_2C_D(1), S => - MACMUXsel_D_1, Y => ADDERinB(1)); - - \OUTA[5]\ : MX2 - port map(A => ADDERout(5), B => OP2_2C_D(5), S => - MACMUXsel_D_0, Y => ADDERinA(5)); - - \OUTA[12]\ : MX2 - port map(A => ADDERout(12), B => OP2_2C_D(8), S => - MACMUXsel_D_0, Y => ADDERinA(12)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \OUTA[19]\ : MX2 - port map(A => ADDERout(19), B => OP2_2C_D(8), S => - MACMUXsel_D, Y => ADDERinA(19)); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_27 is - - port( MULTout : in std_logic_vector(24 downto 7); - MULTout_D : out std_logic_vector(24 downto 7); - rstn : in std_logic; - lclk_c : in std_logic - ); - -end MAC_REG_27; - -architecture DEF_ARCH of MAC_REG_27 is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \Q[24]\ : DFN1C0 - port map(D => MULTout(24), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(24)); - - \Q[21]\ : DFN1C0 - port map(D => MULTout(21), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(21)); - - \Q[13]\ : DFN1C0 - port map(D => MULTout(13), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(13)); - - \Q[14]\ : DFN1C0 - port map(D => MULTout(14), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(14)); - - \Q[15]\ : DFN1C0 - port map(D => MULTout(15), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(15)); - - \Q[11]\ : DFN1C0 - port map(D => MULTout(11), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(11)); - - GND_i_0 : GND - port map(Y => GND_0); - - \Q[20]\ : DFN1C0 - port map(D => MULTout(20), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(20)); - - VCC_i : VCC - port map(Y => \VCC\); - - \Q[17]\ : DFN1C0 - port map(D => MULTout(17), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(17)); - - \Q[10]\ : DFN1C0 - port map(D => MULTout(10), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(10)); - - \Q[19]\ : DFN1C0 - port map(D => MULTout(19), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(19)); - - GND_i : GND - port map(Y => \GND\); - - \Q[18]\ : DFN1C0 - port map(D => MULTout(18), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(18)); - - \Q[22]\ : DFN1C0 - port map(D => MULTout(22), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(22)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[7]\ : DFN1C0 - port map(D => MULTout(7), CLK => lclk_c, CLR => rstn, Q => - MULTout_D(7)); - - \Q[12]\ : DFN1C0 - port map(D => MULTout(12), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(12)); - - \Q[8]\ : DFN1C0 - port map(D => MULTout(8), CLK => lclk_c, CLR => rstn, Q => - MULTout_D(8)); - - \Q[9]\ : DFN1C0 - port map(D => MULTout(9), CLK => lclk_c, CLR => rstn, Q => - MULTout_D(9)); - - \Q[23]\ : DFN1C0 - port map(D => MULTout(23), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(23)); - - \Q[16]\ : DFN1C0 - port map(D => MULTout(16), CLK => lclk_c, CLR => rstn, Q - => MULTout_D(16)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_1 is - - port( alu_ctrl : in std_logic_vector(0 to 0); - add_D : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - add_D_0 : out std_logic - ); - -end MAC_REG_1_1; - -architecture DEF_ARCH of MAC_REG_1_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_0[0]\ : DFN1C0 - port map(D => alu_ctrl(0), CLK => lclk_c, CLR => rstn, Q - => add_D_0); - - \Q[0]\ : DFN1C0 - port map(D => alu_ctrl(0), CLK => lclk_c, CLR => rstn, Q - => add_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_3 is - - port( MACMUX2sel : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - MACMUX2sel_D : out std_logic - ); - -end MAC_REG_1_3; - -architecture DEF_ARCH of MAC_REG_1_3 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q[0]\ : DFN1C0 - port map(D => MACMUX2sel, CLK => lclk_c, CLR => rstn, Q => - MACMUX2sel_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1 is - - port( alu_ctrl : in std_logic_vector(2 to 2); - clr_MAC_D : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - clr_MAC_D_0 : out std_logic - ); - -end MAC_REG_1; - -architecture DEF_ARCH of MAC_REG_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_0[0]\ : DFN1C0 - port map(D => alu_ctrl(2), CLK => lclk_c, CLR => rstn, Q - => clr_MAC_D_0); - - \Q[0]\ : DFN1C0 - port map(D => alu_ctrl(2), CLK => lclk_c, CLR => rstn, Q - => clr_MAC_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Adder is - - port( ADDERout : out std_logic_vector(24 downto 0); - ADDERinB : in std_logic_vector(24 downto 0); - ADDERinA : in std_logic_vector(24 downto 0); - rstn : in std_logic; - lclk_c : in std_logic; - clr_MAC_D : in std_logic; - add_D : in std_logic; - clr_MAC_D_0 : in std_logic; - MACMUX2sel_D : in std_logic; - add_D_0 : in std_logic - ); - -end Adder; - -architecture DEF_ARCH of Adder is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_clr_1_0\, ADD_27x27_fast_I247_Y_0_0, - ADD_27x27_fast_I253_Y_0_0, ADD_27x27_fast_I254_Y_0_0, - ADD_27x27_fast_I208_Y_3, N534, N519, - ADD_27x27_fast_I208_Y_2, N472, N465, - ADD_27x27_fast_I208_Y_1, N412, N415, - ADD_27x27_fast_I208_Y_0, N388, ADD_27x27_fast_I251_Y_0_0, - ADD_27x27_fast_I243_Y_0_0, ADD_27x27_fast_I207_Y_3, N517, - N532, ADD_27x27_fast_I207_Y_2, N470, N463, - ADD_27x27_fast_I207_Y_1, N413, N410, - ADD_27x27_fast_I207_Y_0, N391, ADD_27x27_fast_I239_Y_0_0, - ADD_27x27_fast_I249_Y_0_0, ADD_27x27_fast_I196_Y_0_0, - N496, N_73, N439, ADD_27x27_fast_I241_Y_0_0, - ADD_27x27_fast_I250_Y_0_0, ADD_27x27_fast_I242_Y_0_0, - ADD_27x27_fast_I252_Y_0_0, ADD_27x27_fast_I212_Y_1, N542, - N527, ADD_27x27_fast_I212_Y_0, N480, N473, - ADD_27x27_fast_I164_Y_i_0, N_58, - ADD_27x27_fast_I248_Y_0_0, ADD_27x27_fast_I211_Y_1, N540, - N525, ADD_27x27_fast_I211_Y_0, N478, N471, - ADD_27x27_fast_I209_Y_2, N536, N521, - ADD_27x27_fast_I209_Y_1, N467_i, N474, - ADD_27x27_fast_I209_Y_0, N417, N414, - ADD_27x27_fast_I240_Y_0_0, ADD_27x27_fast_I213_Y_1, - ADD_27x27_fast_I213_un1_Y_0, N529, - ADD_27x27_fast_I213_Y_0, N482, N475, - ADD_27x27_fast_I236_Y_0_0, N499, N_47, N491, - ADD_27x27_fast_I115_Y_0, N340, ADD_27x27_fast_I99_Y_0, - N364, ADD_27x27_fast_I91_Y_0, N376, - ADD_27x27_fast_I107_Y_0, N352, - ADD_27x27_fast_I115_un1_Y_0, N_108, - ADD_27x27_fast_I116_Y_0, ADD_27x27_fast_I100_Y_0, N362, - I207_un1_Y, N533, N548, I209_un1_Y, N537, N552, - I211_un1_Y_i, N541, N502, N431, N428, N481, N488, N436, - N444, N497, I208_un1_Y, N535, N550, N_33, N_48, - \un1_clr_1\, \un2_resadd[23]\, \un2_resadd[22]\, - \un2_resadd[20]\, \un2_resadd[18]\, I185_un1_Y, - \un2_resadd[16]\, N648, \un2_resadd[15]\, N651, - \un2_resadd[14]\, N654_i, \un2_resadd[13]\, - ADD_27x27_fast_I192_Y_0_a2, N361, \un2_resadd[12]\, - I193_un1_Y, \un2_resadd[11]\, ADD_27x27_fast_I194_un1_Y, - \un2_resadd[10]\, ADD_27x27_fast_I195_un1_Y, N544, - \un2_resadd[9]\, N_78_i, \un2_resadd[8]\, \un2_resadd[7]\, - \un2_resadd[5]\, \un2_resadd[4]\, \un2_resadd[3]\, - \un2_resadd[2]\, \un2_resadd[24]\, \un2_resadd[17]\, N423, - N_98_i, N420, \un2_resadd[1]\, N325, \un2_resadd[6]\, - \un2_resadd[19]\, I212_un1_Y, \un2_resadd[21]\, N_105, - N543, N392, N355, N356, N425, N367, N429, N437, N349, - N441, N343, N445, N_52_i_0, N449, N_72, N450, N422, N421, - N426, N433, N430, N483, N434, N490, N438, N442, N494, - N498, N446, N486, N479, N487, N495, N371, N365, N350, - N344, N341, N418, N346, N370, N489, I162_un1_Y, - I190_un1_Y, N_59, N_50, N_9, N_11, N_16, N_18, N_23, N_30, - \REG_4[1]\, \REG_4[3]\, \REG_4[8]\, \REG_4[10]\, - \REG_4[15]\, \REG_4[22]\, N_8, N_12, N_15, N_19, N_22, - N_26, \REG_4[0]\, \REG_4[4]\, \REG_4[7]\, \REG_4[11]\, - \REG_4[14]\, \REG_4[18]\, N_10, N_13, N_17, N_20, N_21, - N_24, N_28, N_31, \REG_4[2]\, \REG_4[5]\, \REG_4[9]\, - \REG_4[12]\, \REG_4[13]\, \REG_4[16]\, \REG_4[20]\, - \REG_4[23]\, \REG_4[24]\, N_32, N_23_0, \REG_4[17]\, N_25, - N374, N373, N380, N_43, \REG_4[19]\, N_27, \REG_4[6]\, - N_14, \REG_4[21]\, N_29, N386, N382, N385, N379, - I163_un1_Y, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - un2_resadd_ADD_27x27_fast_I8_G0N : NOR2B - port map(A => ADDERinB(8), B => ADDERinA(8), Y => N349); - - un2_resadd_ADD_27x27_fast_I241_Y_0_0 : XOR2 - port map(A => ADDERinA(11), B => ADDERinB(11), Y => - ADD_27x27_fast_I241_Y_0_0); - - un2_resadd_ADD_27x27_fast_I134_Y : NOR2 - port map(A => N475, B => N467_i, Y => N521); - - un2_resadd_ADD_27x27_fast_I208_Y_1 : OA1A - port map(A => N412, B => N415, C => ADD_27x27_fast_I208_Y_0, - Y => ADD_27x27_fast_I208_Y_1); - - un2_resadd_ADD_27x27_fast_I156_Y : NOR2A - port map(A => N497, B => N489, Y => N543); - - un2_resadd_ADD_27x27_fast_I21_G0N : NOR2B - port map(A => ADDERinB(21), B => ADDERinA(21), Y => N388); - - \REG[14]\ : DFN1E0C0 - port map(D => \REG_4[14]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(14)); - - un2_resadd_ADD_27x27_fast_I214_Y_0_a2 : OR2A - port map(A => N651, B => N_23_0, Y => N_98_i); - - un2_resadd_ADD_27x27_fast_I12_G0N : OR2B - port map(A => ADDERinB(12), B => ADDERinA(12), Y => N361); - - un2_resadd_ADD_27x27_fast_I99_Y : AO1B - port map(A => N431, B => N428, C => ADD_27x27_fast_I99_Y_0, - Y => N480); - - un2_resadd_ADD_27x27_fast_I149_Y : AO1A - port map(A => N483, B => N490, C => N482, Y => N536); - - un2_resadd_ADD_27x27_fast_I68_Y : OA1 - port map(A => ADDERinA(4), B => ADDERinB(4), C => N341, Y - => N446); - - un2_resadd_ADD_27x27_fast_I5_P0N : OR2 - port map(A => ADDERinB(5), B => ADDERinA(5), Y => N341); - - un2_resadd_ADD_27x27_fast_I11_G0N_0_o2 : OR2B - port map(A => ADDERinB(11), B => ADDERinA(11), Y => N_50); - - un2_resadd_ADD_27x27_fast_I209_Y_0 : AOI1 - port map(A => N417, B => N414, C => N413, Y => - ADD_27x27_fast_I209_Y_0); - - un2_resadd_ADD_27x27_fast_I132_Y : NOR2B - port map(A => N473, B => N465, Y => N519); - - un2_resadd_ADD_27x27_fast_I122_Y_i_o2 : MAJ3 - port map(A => ADDERinA(2), B => ADDERinB(2), C => N_47, Y - => N_48); - - un2_resadd_ADD_27x27_fast_I93_Y : AOI1 - port map(A => N425, B => N422, C => N421, Y => N474); - - un2_resadd_ADD_27x27_fast_I52_Y : NOR2B - port map(A => N365, B => N362, Y => N430); - - un2_resadd_ADD_27x27_fast_I254_Y_0 : AX1C - port map(A => I207_un1_Y, B => ADD_27x27_fast_I207_Y_3, C - => ADD_27x27_fast_I254_Y_0_0, Y => \un2_resadd[24]\); - - \REG_RNO[11]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_19, Y => \REG_4[11]\); - - \REG[22]\ : DFN1E0C0 - port map(D => \REG_4[22]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1\, Q => ADDERout(22)); - - un2_resadd_ADD_27x27_fast_I51_Y : AO13 - port map(A => ADDERinB(13), B => ADDERinA(13), C => N361, Y - => N429); - - \REG_RNO[20]\ : NOR2 - port map(A => clr_MAC_D, B => N_28, Y => \REG_4[20]\); - - \REG_RNO[15]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_23, Y => \REG_4[15]\); - - \REG_RNO_0[17]\ : MX2C - port map(A => ADDERinB(17), B => \un2_resadd[17]\, S => - add_D, Y => N_25); - - un2_resadd_ADD_27x27_fast_I196_Y_0_a2 : OR2A - port map(A => I162_un1_Y, B => N_73, Y => N_78_i); - - un2_resadd_ADD_27x27_fast_I240_Y_0_0 : XOR2 - port map(A => ADDERinA(10), B => ADDERinB(10), Y => - ADD_27x27_fast_I240_Y_0_0); - - un2_resadd_ADD_27x27_fast_I13_P0N : OR2 - port map(A => ADDERinB(13), B => ADDERinA(13), Y => N365); - - un2_resadd_ADD_27x27_fast_I6_G0N : NOR2B - port map(A => ADDERinB(6), B => ADDERinA(6), Y => N343); - - un2_resadd_ADD_27x27_fast_I163_Y : OR2 - port map(A => N498, B => I163_un1_Y, Y => N552); - - un2_resadd_ADD_27x27_fast_I90_Y : OR2B - port map(A => N422, B => N418, Y => N471); - - un2_resadd_ADD_27x27_fast_I35_Y : MAJ3 - port map(A => ADDERinA(21), B => ADDERinB(21), C => N385, Y - => N413); - - un2_resadd_ADD_27x27_fast_I48_Y : OA1 - port map(A => ADDERinA(14), B => ADDERinB(14), C => N371, Y - => N426); - - \REG_RNO[9]\ : NOR2 - port map(A => clr_MAC_D, B => N_17, Y => \REG_4[9]\); - - \REG_RNO_0[8]\ : MX2C - port map(A => ADDERinB(8), B => \un2_resadd[8]\, S => - add_D_0, Y => N_16); - - \REG[11]\ : DFN1E0C0 - port map(D => \REG_4[11]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(11)); - - un2_resadd_ADD_27x27_fast_I99_Y_0 : MIN3 - port map(A => ADDERinA(14), B => ADDERinB(14), C => N364, Y - => ADD_27x27_fast_I99_Y_0); - - un2_resadd_ADD_27x27_fast_I6_P0N : OR2 - port map(A => ADDERinB(6), B => ADDERinA(6), Y => N344); - - un2_resadd_ADD_27x27_fast_I15_G0N : NOR2A - port map(A => ADDERinB(15), B => ADDERinA(15), Y => N370); - - un2_resadd_ADD_27x27_fast_I207_Y_1 : AOI1B - port map(A => N413, B => N410, C => ADD_27x27_fast_I207_Y_0, - Y => ADD_27x27_fast_I207_Y_1); - - un2_resadd_ADD_27x27_fast_I207_Y_0 : MIN3 - port map(A => ADDERinA(23), B => ADDERinB(23), C => N391, Y - => ADD_27x27_fast_I207_Y_0); - - un2_resadd_ADD_27x27_fast_I116_Y : NOR2B - port map(A => ADD_27x27_fast_I116_Y_0, B => N444, Y => N497); - - un2_resadd_ADD_27x27_fast_I242_Y_0_0 : XOR2 - port map(A => ADDERinA(12), B => ADDERinB(12), Y => - ADD_27x27_fast_I242_Y_0_0); - - un2_resadd_ADD_27x27_fast_I163_un1_Y : NOR2B - port map(A => N_47, B => N499, Y => I163_un1_Y); - - un2_resadd_ADD_27x27_fast_I238_Y_0 : XNOR3 - port map(A => ADDERinB(8), B => ADDERinA(8), C => N548, Y - => \un2_resadd[8]\); - - \REG_RNO[4]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_12, Y => \REG_4[4]\); - - \REG_RNO[12]\ : NOR2 - port map(A => clr_MAC_D, B => N_20, Y => \REG_4[12]\); - - un2_resadd_ADD_27x27_fast_I140_Y : NOR2A - port map(A => N473, B => N481, Y => N527); - - un2_resadd_ADD_27x27_fast_I248_Y_0 : AX1E - port map(A => I185_un1_Y, B => ADD_27x27_fast_I213_Y_1, C - => ADD_27x27_fast_I248_Y_0_0, Y => \un2_resadd[18]\); - - \REG_RNO_0[11]\ : MX2C - port map(A => ADDERinB(11), B => \un2_resadd[11]\, S => - add_D_0, Y => N_19); - - un2_resadd_ADD_27x27_fast_I66_Y : NOR2B - port map(A => N344, B => N341, Y => N444); - - un2_resadd_ADD_27x27_fast_I247_Y_0_0 : XOR2 - port map(A => ADDERinA(17), B => ADDERinB(17), Y => - ADD_27x27_fast_I247_Y_0_0); - - un2_resadd_ADD_27x27_fast_I162_Y : OR2 - port map(A => N496, B => I162_un1_Y, Y => N550); - - un2_resadd_ADD_27x27_fast_I36_Y : OA1 - port map(A => ADDERinA(21), B => ADDERinB(21), C => N386, Y - => N414); - - un2_resadd_ADD_27x27_fast_I209_Y_2 : AOI1B - port map(A => N536, B => N521, C => ADD_27x27_fast_I209_Y_1, - Y => ADD_27x27_fast_I209_Y_2); - - un2_resadd_ADD_27x27_fast_I236_Y_0_0 : XOR2 - port map(A => ADDERinA(6), B => ADDERinB(6), Y => - ADD_27x27_fast_I236_Y_0_0); - - un2_resadd_ADD_27x27_fast_I212_Y_1 : AO1 - port map(A => N542, B => N527, C => ADD_27x27_fast_I212_Y_0, - Y => ADD_27x27_fast_I212_Y_1); - - un2_resadd_ADD_27x27_fast_I19_G0N : NOR2B - port map(A => ADDERinB(19), B => ADDERinA(19), Y => N382); - - \REG_RNO_0[10]\ : MX2C - port map(A => ADDERinB(10), B => \un2_resadd[10]\, S => - add_D_0, Y => N_18); - - \REG[12]\ : DFN1E0C0 - port map(D => \REG_4[12]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(12)); - - un2_resadd_ADD_27x27_fast_I84_Y : NOR2A - port map(A => N412, B => N_43, Y => N465); - - un2_resadd_ADD_27x27_fast_I107_Y_0 : MIN3 - port map(A => ADDERinA(10), B => ADDERinB(10), C => N352, Y - => ADD_27x27_fast_I107_Y_0); - - un2_resadd_ADD_27x27_fast_I185_un1_Y : OR2B - port map(A => N544, B => N529, Y => I185_un1_Y); - - un2_resadd_ADD_27x27_fast_I115_un1_Y_0 : OA1B - port map(A => ADDERinA(4), B => ADDERinB(4), C => N_108, Y - => ADD_27x27_fast_I115_un1_Y_0); - - un2_resadd_ADD_27x27_fast_I207_Y_2 : OA1A - port map(A => N470, B => N463, C => ADD_27x27_fast_I207_Y_1, - Y => ADD_27x27_fast_I207_Y_2); - - un2_resadd_ADD_27x27_fast_I118_Y : NOR2B - port map(A => N450, B => N446, Y => N499); - - un2_resadd_ADD_27x27_fast_I207_Y_3 : OA1A - port map(A => N517, B => N532, C => ADD_27x27_fast_I207_Y_2, - Y => ADD_27x27_fast_I207_Y_3); - - GND_i : GND - port map(Y => \GND\); - - \REG_RNO_0[21]\ : MX2C - port map(A => ADDERinB(21), B => \un2_resadd[21]\, S => - add_D, Y => N_29); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un2_resadd_ADD_27x27_fast_I63_Y : MAJ3 - port map(A => ADDERinA(7), B => ADDERinB(7), C => N343, Y - => N441); - - un2_resadd_ADD_27x27_fast_I236_Y_0 : XOR2 - port map(A => ADD_27x27_fast_I236_Y_0_0, B => N552, Y => - \un2_resadd[6]\); - - un2_resadd_ADD_27x27_fast_I45_Y_0_o2 : AO1 - port map(A => N374, B => N370, C => N373, Y => N423); - - un2_resadd_ADD_27x27_fast_I10_G0N : NOR2B - port map(A => ADDERinB(10), B => ADDERinA(10), Y => N355); - - un2_resadd_ADD_27x27_fast_I246_Y_0 : XOR3 - port map(A => ADDERinB(16), B => ADDERinA(16), C => N648, Y - => \un2_resadd[16]\); - - \REG_RNO[14]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_22, Y => \REG_4[14]\); - - un2_resadd_ADD_27x27_fast_I92_Y : NOR2A - port map(A => N420, B => N_23_0, Y => N473); - - un2_resadd_ADD_27x27_fast_I39_Y : MAJ3 - port map(A => ADDERinA(19), B => ADDERinB(19), C => N379, Y - => N417); - - un2_resadd_ADD_27x27_fast_I150_Y : NOR2 - port map(A => N491, B => N483, Y => N537); - - un2_resadd_ADD_27x27_fast_I235_Y_0 : XNOR3 - port map(A => ADDERinB(5), B => ADDERinA(5), C => N_33, Y - => \un2_resadd[5]\); - - un2_resadd_ADD_27x27_fast_I164_Y_i_0 : MAJ3 - port map(A => ADDERinA(4), B => ADDERinB(4), C => N_58, Y - => ADD_27x27_fast_I164_Y_i_0); - - un2_resadd_ADD_27x27_fast_I212_Y_0 : AO1 - port map(A => N480, B => N473, C => N472, Y => - ADD_27x27_fast_I212_Y_0); - - un2_resadd_ADD_27x27_fast_I196_Y_0_0 : OA1C - port map(A => N496, B => N_73, C => N439, Y => - ADD_27x27_fast_I196_Y_0_0); - - un2_resadd_ADD_27x27_fast_I245_Y_0 : XNOR3 - port map(A => ADDERinB(15), B => ADDERinA(15), C => N651, Y - => \un2_resadd[15]\); - - \REG[0]\ : DFN1E0C0 - port map(D => \REG_4[0]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1_0\, Q => ADDERout(0)); - - \REG_RNO[7]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_15, Y => \REG_4[7]\); - - un2_resadd_ADD_27x27_fast_I9_G0N : NOR2B - port map(A => ADDERinB(9), B => ADDERinA(9), Y => N352); - - un2_resadd_ADD_27x27_fast_I91_Y : AO1B - port map(A => N423, B => N420, C => ADD_27x27_fast_I91_Y_0, - Y => N472); - - \REG_RNO_0[20]\ : MX2C - port map(A => ADDERinB(20), B => \un2_resadd[20]\, S => - add_D, Y => N_28); - - un2_resadd_ADD_27x27_fast_I212_un1_Y : NOR3C - port map(A => N543, B => N527, C => N_48, Y => I212_un1_Y); - - un2_resadd_ADD_27x27_fast_I106_Y : OR2B - port map(A => N438, B => N434, Y => N487); - - un2_resadd_ADD_27x27_fast_I3_G0N_i_o2 : NOR2B - port map(A => ADDERinB(3), B => ADDERinA(3), Y => N_59); - - un2_resadd_ADD_27x27_fast_I60_Y : OA1 - port map(A => ADDERinA(9), B => ADDERinB(9), C => N350, Y - => N438); - - \REG[23]\ : DFN1E0C0 - port map(D => \REG_4[23]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1\, Q => ADDERout(23)); - - un2_resadd_ADD_27x27_fast_I208_Y_0 : AO18 - port map(A => N388, B => ADDERinA(22), C => ADDERinB(22), Y - => ADD_27x27_fast_I208_Y_0); - - \REG_RNO[1]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_9, Y => \REG_4[1]\); - - un2_resadd_ADD_27x27_fast_I43_Y : AO13 - port map(A => N373, B => ADDERinB(17), C => ADDERinA(17), Y - => N421); - - un2_resadd_ADD_27x27_fast_I190_un1_Y : NOR2B - port map(A => N550, B => N535, Y => I190_un1_Y); - - un2_resadd_ADD_27x27_fast_I20_P0N : OR2 - port map(A => ADDERinB(20), B => ADDERinA(20), Y => N386); - - un2_resadd_ADD_27x27_fast_I208_Y_2 : AOI1B - port map(A => N472, B => N465, C => ADD_27x27_fast_I208_Y_1, - Y => ADD_27x27_fast_I208_Y_2); - - un2_resadd_ADD_27x27_fast_I101_Y : AO1 - port map(A => N433, B => N430, C => N429, Y => N482); - - \REG_RNO[21]\ : NOR2 - port map(A => clr_MAC_D, B => N_29, Y => \REG_4[21]\); - - un2_resadd_ADD_27x27_fast_I162_un1_Y : NOR2B - port map(A => N_48, B => N497, Y => I162_un1_Y); - - un2_resadd_ADD_27x27_fast_I16_G0N : NOR2B - port map(A => ADDERinB(16), B => ADDERinA(16), Y => N373); - - VCC_i : VCC - port map(Y => \VCC\); - - un2_resadd_ADD_27x27_fast_I91_Y_0 : MIN3 - port map(A => ADDERinA(18), B => ADDERinB(18), C => N376, Y - => ADD_27x27_fast_I91_Y_0); - - un2_resadd_ADD_27x27_fast_I211_Y_0 : OA1C - port map(A => N478, B => N471, C => N470, Y => - ADD_27x27_fast_I211_Y_0); - - un2_resadd_ADD_27x27_fast_I97_Y : AO1 - port map(A => N429, B => N426, C => N425, Y => N478); - - un2_resadd_ADD_27x27_fast_I40_Y : OA1 - port map(A => ADDERinA(19), B => ADDERinB(19), C => N380, Y - => N418); - - un2_resadd_ADD_27x27_fast_I2_G0N_i_o2 : OR2B - port map(A => ADDERinB(2), B => ADDERinA(2), Y => N_72); - - \REG_RNO[13]\ : NOR2 - port map(A => clr_MAC_D, B => N_21, Y => \REG_4[13]\); - - un2_resadd_ADD_27x27_fast_I145_Y : OA1C - port map(A => N486, B => N479, C => N478, Y => N532); - - un2_resadd_ADD_27x27_fast_I108_Y : OR2A - port map(A => N436, B => N_73, Y => N489); - - \REG_RNO_0[19]\ : MX2C - port map(A => ADDERinB(19), B => \un2_resadd[19]\, S => - add_D, Y => N_27); - - un2_resadd_ADD_27x27_fast_I110_Y : OR2B - port map(A => N442, B => N438, Y => N491); - - \REG_RNO_0[6]\ : MX2C - port map(A => ADDERinB(6), B => \un2_resadd[6]\, S => add_D, - Y => N_14); - - un2_resadd_ADD_27x27_fast_I22_P0N : OR2A - port map(A => ADDERinA(22), B => ADDERinB(22), Y => N392); - - un2_resadd_ADD_27x27_fast_I213_Y_1 : AOI1B - port map(A => ADD_27x27_fast_I213_un1_Y_0, B => N529, C => - ADD_27x27_fast_I213_Y_0, Y => ADD_27x27_fast_I213_Y_1); - - un2_resadd_ADD_27x27_fast_I72_Y : OA1 - port map(A => ADDERinA(2), B => ADDERinB(2), C => N_58, Y - => N450); - - un2_resadd_ADD_27x27_fast_I116_Y_0 : OA1 - port map(A => ADDERinA(4), B => ADDERinB(4), C => N_58, Y - => ADD_27x27_fast_I116_Y_0); - - un2_resadd_ADD_27x27_fast_I109_Y : AO1 - port map(A => N441, B => N438, C => N437, Y => N490); - - \REG[9]\ : DFN1E0C0 - port map(D => \REG_4[9]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(9)); - - un1_clr_1_0 : NOR3 - port map(A => add_D_0, B => MACMUX2sel_D, C => clr_MAC_D_0, - Y => \un1_clr_1_0\); - - un2_resadd_ADD_27x27_fast_I142_Y : NOR2 - port map(A => N483, B => N475, Y => N529); - - \REG_RNO_0[9]\ : MX2C - port map(A => ADDERinB(9), B => \un2_resadd[9]\, S => add_D, - Y => N_17); - - un2_resadd_ADD_27x27_fast_I71_Y : AO13 - port map(A => ADDERinB(3), B => ADDERinA(3), C => N_72, Y - => N449); - - \REG_RNO[22]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_30, Y => \REG_4[22]\); - - \REG[5]\ : DFN1E0C0 - port map(D => \REG_4[5]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(5)); - - un2_resadd_ADD_27x27_fast_I210_Y_0_a2 : AO1D - port map(A => ADD_27x27_fast_I212_Y_1, B => I212_un1_Y, C - => N_43, Y => N_105); - - \REG_RNO[2]\ : NOR2 - port map(A => clr_MAC_D, B => N_10, Y => \REG_4[2]\); - - \REG[13]\ : DFN1E0C0 - port map(D => \REG_4[13]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(13)); - - un2_resadd_ADD_27x27_fast_I153_Y : AO1A - port map(A => N487, B => N494, C => N486, Y => N540); - - un2_resadd_ADD_27x27_fast_I232_Y_0 : XOR3 - port map(A => ADDERinB(2), B => ADDERinA(2), C => N_47, Y - => \un2_resadd[2]\); - - un2_resadd_ADD_27x27_fast_I100_Y_0 : OA1 - port map(A => ADDERinA(11), B => ADDERinB(11), C => N362, Y - => ADD_27x27_fast_I100_Y_0); - - \REG[6]\ : DFN1E0C0 - port map(D => \REG_4[6]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(6)); - - \REG[18]\ : DFN1E0C0 - port map(D => \REG_4[18]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(18)); - - un2_resadd_ADD_27x27_fast_I8_P0N : OR2 - port map(A => ADDERinB(8), B => ADDERinA(8), Y => N350); - - un2_resadd_ADD_27x27_fast_I14_G0N : NOR2B - port map(A => ADDERinB(14), B => ADDERinA(14), Y => N367); - - un2_resadd_ADD_27x27_fast_I242_Y_0 : AX1D - port map(A => I193_un1_Y, B => N540, C => - ADD_27x27_fast_I242_Y_0_0, Y => \un2_resadd[12]\); - - un2_resadd_ADD_27x27_fast_I211_un1_Y : OR3C - port map(A => N525, B => N541, C => N502, Y => I211_un1_Y_i); - - un2_resadd_ADD_27x27_fast_I46_Y_i : OR2B - port map(A => N374, B => N371, Y => N_23_0); - - un2_resadd_ADD_27x27_fast_I239_Y_0_0 : XOR2 - port map(A => ADDERinA(9), B => ADDERinB(9), Y => - ADD_27x27_fast_I239_Y_0_0); - - un2_resadd_ADD_27x27_fast_I155_Y : AO1A - port map(A => N489, B => N496, C => N488, Y => N542); - - un2_resadd_ADD_27x27_fast_I191_Y : AOI1 - port map(A => N552, B => N537, C => N536, Y => N654_i); - - \REG_RNO_0[13]\ : MX2C - port map(A => ADDERinB(13), B => \un2_resadd[13]\, S => - add_D, Y => N_21); - - un2_resadd_ADD_27x27_fast_I249_Y_0_0 : XOR2 - port map(A => ADDERinA(19), B => ADDERinB(19), Y => - ADD_27x27_fast_I249_Y_0_0); - - \REG_RNO_0[18]\ : MX2C - port map(A => ADDERinB(18), B => \un2_resadd[18]\, S => - add_D_0, Y => N_26); - - \REG_RNO[18]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_26, Y => \REG_4[18]\); - - \REG[19]\ : DFN1E0C0 - port map(D => \REG_4[19]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(19)); - - un2_resadd_ADD_27x27_fast_I32_Y : OA1 - port map(A => ADDERinA(23), B => ADDERinB(23), C => N392, Y - => N410); - - un2_resadd_ADD_27x27_fast_I53_Y_0 : AO1C - port map(A => N_50, B => N362, C => N361, Y => N431); - - un2_resadd_ADD_27x27_fast_I209_un1_Y : OR3C - port map(A => N537, B => N521, C => N552, Y => I209_un1_Y); - - un2_resadd_ADD_27x27_fast_I147_Y : AO1A - port map(A => N481, B => N488, C => N480, Y => N534); - - un2_resadd_ADD_27x27_fast_I253_Y_0_0 : XOR2 - port map(A => ADDERinA(23), B => ADDERinB(23), Y => - ADD_27x27_fast_I253_Y_0_0); - - un2_resadd_ADD_27x27_fast_I7_G0N : NOR2B - port map(A => ADDERinB(7), B => ADDERinA(7), Y => N346); - - un2_resadd_ADD_27x27_fast_I5_G0N : NOR2B - port map(A => ADDERinB(5), B => ADDERinA(5), Y => N340); - - un2_resadd_ADD_27x27_fast_I138_Y : NOR2 - port map(A => N479, B => N471, Y => N525); - - un2_resadd_ADD_27x27_fast_I154_Y : NOR2A - port map(A => N495, B => N487, Y => N541); - - un2_resadd_ADD_27x27_fast_I37_Y_0_o2 : AOI1 - port map(A => N386, B => N382, C => N385, Y => N415); - - \REG_RNO[19]\ : NOR2 - port map(A => clr_MAC_D, B => N_27, Y => \REG_4[19]\); - - un2_resadd_ADD_27x27_fast_I58_Y : OA1 - port map(A => ADDERinA(9), B => ADDERinB(9), C => N356, Y - => N436); - - \REG_RNO_0[1]\ : MX2C - port map(A => ADDERinB(1), B => \un2_resadd[1]\, S => - add_D_0, Y => N_9); - - un2_resadd_ADD_27x27_fast_I94_Y : OR2B - port map(A => N426, B => N422, Y => N475); - - un2_resadd_ADD_27x27_fast_I42_Y : OA1A - port map(A => ADDERinA(17), B => ADDERinB(17), C => N380, Y - => N420); - - un2_resadd_ADD_27x27_fast_I86_Y : OR2B - port map(A => N418, B => N414, Y => N467_i); - - un2_resadd_ADD_27x27_fast_I75_Y_i_o2 : AO18 - port map(A => ADDERinA(1), B => ADDERinB(1), C => N325, Y - => N_47); - - un2_resadd_ADD_27x27_fast_I231_Y_0 : XOR3 - port map(A => ADDERinB(1), B => ADDERinA(1), C => N325, Y - => \un2_resadd[1]\); - - \REG[1]\ : DFN1E0C0 - port map(D => \REG_4[1]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1_0\, Q => ADDERout(1)); - - un2_resadd_ADD_27x27_fast_I241_Y_0 : AX1D - port map(A => ADD_27x27_fast_I194_un1_Y, B => N542, C => - ADD_27x27_fast_I241_Y_0_0, Y => \un2_resadd[11]\); - - un2_resadd_ADD_27x27_fast_I17_G0N : NOR2A - port map(A => ADDERinB(17), B => ADDERinA(17), Y => N376); - - un2_resadd_ADD_27x27_fast_I100_Y : OR2B - port map(A => ADD_27x27_fast_I100_Y_0, B => N428, Y => N481); - - \REG_RNO[24]\ : NOR2 - port map(A => clr_MAC_D, B => N_32, Y => \REG_4[24]\); - - un2_resadd_ADD_27x27_fast_I55_Y : MAJ3 - port map(A => ADDERinA(11), B => ADDERinB(11), C => N355, Y - => N433); - - un2_resadd_ADD_27x27_fast_I193_un1_Y : NOR2B - port map(A => N541, B => N502, Y => I193_un1_Y); - - un2_resadd_ADD_27x27_fast_I164_Y_i : AO1C - port map(A => N_48, B => N_108, C => - ADD_27x27_fast_I164_Y_i_0, Y => N_33); - - \REG[20]\ : DFN1E0C0 - port map(D => \REG_4[20]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(20)); - - un2_resadd_ADD_27x27_fast_I252_Y_0 : AX1C - port map(A => I209_un1_Y, B => ADD_27x27_fast_I209_Y_2, C - => ADD_27x27_fast_I252_Y_0_0, Y => \un2_resadd[22]\); - - \REG_RNO[8]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_16, Y => \REG_4[8]\); - - \REG_RNO_0[7]\ : MX2C - port map(A => ADDERinB(7), B => \un2_resadd[7]\, S => - add_D_0, Y => N_15); - - un2_resadd_ADD_27x27_fast_I67_Y : MAJ3 - port map(A => ADDERinA(5), B => ADDERinB(5), C => N_52_i_0, - Y => N445); - - \REG_RNO_0[23]\ : MX2C - port map(A => ADDERinB(23), B => \un2_resadd[23]\, S => - add_D, Y => N_31); - - \REG[3]\ : DFN1E0C0 - port map(D => \REG_4[3]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(3)); - - un2_resadd_ADD_27x27_fast_I248_Y_0_0 : XOR2 - port map(A => ADDERinA(18), B => ADDERinB(18), Y => - ADD_27x27_fast_I248_Y_0_0); - - \REG_RNO[3]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_11, Y => \REG_4[3]\); - - un2_resadd_ADD_27x27_fast_I121_Y : AO1 - port map(A => N_47, B => N450, C => N449, Y => N502); - - un2_resadd_ADD_27x27_fast_I113_Y : AO1 - port map(A => N445, B => N442, C => N441, Y => N494); - - \REG[17]\ : DFN1E0C0 - port map(D => \REG_4[17]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(17)); - - un2_resadd_ADD_27x27_fast_I161_Y : AOI1 - port map(A => N502, B => N495, C => N494, Y => N548); - - un2_resadd_ADD_27x27_fast_I22_G0N : NOR2A - port map(A => ADDERinB(22), B => ADDERinA(22), Y => N391); - - un2_resadd_ADD_27x27_fast_I157_Y : AO1A - port map(A => N491, B => N498, C => N490, Y => N544); - - GND_i_0 : GND - port map(Y => GND_0); - - un2_resadd_ADD_27x27_fast_I195_un1_Y : NOR3B - port map(A => N499, B => N_47, C => N491, Y => - ADD_27x27_fast_I195_un1_Y); - - un2_resadd_ADD_27x27_fast_I115_Y : AO1 - port map(A => ADD_27x27_fast_I115_un1_Y_0, B => N444, C => - ADD_27x27_fast_I115_Y_0, Y => N496); - - un2_resadd_ADD_27x27_fast_I89_Y : AO1 - port map(A => N421, B => N418, C => N417, Y => N470); - - \REG_RNO_0[16]\ : MX2C - port map(A => ADDERinB(16), B => \un2_resadd[16]\, S => - add_D, Y => N_24); - - un2_resadd_ADD_27x27_fast_I213_Y_0 : OA1A - port map(A => N482, B => N475, C => N474, Y => - ADD_27x27_fast_I213_Y_0); - - un2_resadd_ADD_27x27_fast_I16_P0N : OR2 - port map(A => ADDERinB(16), B => ADDERinA(16), Y => N374); - - \REG_RNO[16]\ : NOR2 - port map(A => clr_MAC_D, B => N_24, Y => \REG_4[16]\); - - un2_resadd_ADD_27x27_fast_I115_Y_0 : MAJ3 - port map(A => ADDERinA(6), B => ADDERinB(6), C => N340, Y - => ADD_27x27_fast_I115_Y_0); - - un2_resadd_ADD_27x27_fast_I47_Y : AO13 - port map(A => N367, B => ADDERinB(15), C => ADDERinA(15), Y - => N425); - - \REG_RNO_0[0]\ : AX1E - port map(A => ADDERinA(0), B => add_D_0, C => ADDERinB(0), - Y => N_8); - - un2_resadd_ADD_27x27_fast_I114_Y : NOR2B - port map(A => N446, B => N442, Y => N495); - - un2_resadd_ADD_27x27_fast_I251_Y_0 : AX1E - port map(A => N415, B => N_105, C => - ADD_27x27_fast_I251_Y_0_0, Y => \un2_resadd[21]\); - - \REG_RNO[6]\ : NOR2 - port map(A => clr_MAC_D, B => N_14, Y => \REG_4[6]\); - - \REG_RNO[5]\ : NOR2 - port map(A => clr_MAC_D, B => N_13, Y => \REG_4[5]\); - - un2_resadd_ADD_27x27_fast_I56_Y : OA1 - port map(A => ADDERinA(11), B => ADDERinB(11), C => N356, Y - => N434); - - \REG[2]\ : DFN1E0C0 - port map(D => \REG_4[2]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(2)); - - un2_resadd_ADD_27x27_fast_I254_Y_0_0 : XOR2 - port map(A => ADDERinA(24), B => ADDERinB(24), Y => - ADD_27x27_fast_I254_Y_0_0); - - un2_resadd_ADD_27x27_fast_I10_P0N : OR2 - port map(A => ADDERinB(10), B => ADDERinA(10), Y => N356); - - \REG_RNO[23]\ : NOR2 - port map(A => clr_MAC_D, B => N_31, Y => \REG_4[23]\); - - un2_resadd_ADD_27x27_fast_I130_Y : NOR2 - port map(A => N471, B => N463, Y => N517); - - un2_resadd_ADD_27x27_fast_I209_Y_1 : OA1 - port map(A => N467_i, B => N474, C => - ADD_27x27_fast_I209_Y_0, Y => ADD_27x27_fast_I209_Y_1); - - \REG[7]\ : DFN1E0C0 - port map(D => \REG_4[7]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(7)); - - un2_resadd_ADD_27x27_fast_I211_Y_1 : AOI1B - port map(A => N540, B => N525, C => ADD_27x27_fast_I211_Y_0, - Y => ADD_27x27_fast_I211_Y_1); - - un2_resadd_ADD_27x27_fast_I61_Y_0_o2 : AO1 - port map(A => N350, B => N346, C => N349, Y => N439); - - \REG_RNO[10]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_18, Y => \REG_4[10]\); - - \REG[4]\ : DFN1E0C0 - port map(D => \REG_4[4]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(4)); - - \REG[10]\ : DFN1E0C0 - port map(D => \REG_4[10]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(10)); - - un2_resadd_ADD_27x27_fast_I243_Y_0_0 : XOR2 - port map(A => ADDERinA(13), B => ADDERinB(13), Y => - ADD_27x27_fast_I243_Y_0_0); - - un2_resadd_ADD_27x27_fast_I208_Y_3 : AOI1B - port map(A => N534, B => N519, C => ADD_27x27_fast_I208_Y_2, - Y => ADD_27x27_fast_I208_Y_3); - - un2_resadd_ADD_27x27_fast_I192_Y_0_a2 : OA1 - port map(A => I193_un1_Y, B => N540, C => N362, Y => - ADD_27x27_fast_I192_Y_0_a2); - - un2_resadd_ADD_27x27_fast_I190_Y : OR2 - port map(A => N534, B => I190_un1_Y, Y => N651); - - un2_resadd_ADD_27x27_fast_I18_P0N : OR2 - port map(A => ADDERinB(18), B => ADDERinA(18), Y => N380); - - un2_resadd_ADD_27x27_fast_I207_un1_Y : OR3B - port map(A => N533, B => N517, C => N548, Y => I207_un1_Y); - - un2_resadd_ADD_27x27_fast_I59_Y : MAJ3 - port map(A => ADDERinA(9), B => ADDERinB(9), C => N349, Y - => N437); - - un2_resadd_ADD_27x27_fast_I251_Y_0_0 : XOR2 - port map(A => ADDERinA(21), B => ADDERinB(21), Y => - ADD_27x27_fast_I251_Y_0_0); - - un2_resadd_ADD_27x27_fast_I208_un1_Y : OR3C - port map(A => N519, B => N535, C => N550, Y => I208_un1_Y); - - \REG_RNO[17]\ : NOR2 - port map(A => clr_MAC_D, B => N_25, Y => \REG_4[17]\); - - un1_clr_1 : NOR3 - port map(A => add_D_0, B => MACMUX2sel_D, C => clr_MAC_D_0, - Y => \un1_clr_1\); - - un2_resadd_ADD_27x27_fast_I98_Y : OR2B - port map(A => N430, B => N426, Y => N479); - - un2_resadd_ADD_27x27_fast_I12_P0N : OR2 - port map(A => ADDERinB(12), B => ADDERinA(12), Y => N362); - - un2_resadd_ADD_27x27_fast_I117_Y : AO1 - port map(A => N449, B => N446, C => N445, Y => N498); - - un2_resadd_ADD_27x27_fast_I64_Y : OA1 - port map(A => ADDERinA(7), B => ADDERinB(7), C => N344, Y - => N442); - - \REG[8]\ : DFN1E0C0 - port map(D => \REG_4[8]\, CLK => lclk_c, CLR => rstn, E => - \un1_clr_1\, Q => ADDERout(8)); - - un2_resadd_ADD_27x27_fast_I240_Y_0 : AX1D - port map(A => ADD_27x27_fast_I195_un1_Y, B => N544, C => - ADD_27x27_fast_I240_Y_0_0, Y => \un2_resadd[10]\); - - un2_resadd_ADD_27x27_fast_I0_CO1 : OR2B - port map(A => ADDERinB(0), B => ADDERinA(0), Y => N325); - - un2_resadd_ADD_27x27_fast_I38_Y_i : OAI1 - port map(A => ADDERinA(19), B => ADDERinB(19), C => N386, Y - => N_43); - - un2_resadd_ADD_27x27_fast_I34_Y : OA1 - port map(A => ADDERinA(21), B => ADDERinB(21), C => N392, Y - => N412); - - un2_resadd_ADD_27x27_fast_I105_Y : AO1 - port map(A => N437, B => N434, C => N433, Y => N486); - - \REG_RNO_0[3]\ : MX2C - port map(A => ADDERinB(3), B => \un2_resadd[3]\, S => - add_D_0, Y => N_11); - - un2_resadd_ADD_27x27_fast_I50_Y : OA1 - port map(A => ADDERinA(14), B => ADDERinB(14), C => N365, Y - => N428); - - un2_resadd_ADD_27x27_fast_I239_Y_0 : AX1E - port map(A => N_78_i, B => ADD_27x27_fast_I196_Y_0_0, C => - ADD_27x27_fast_I239_Y_0_0, Y => \un2_resadd[9]\); - - \REG[24]\ : DFN1E0C0 - port map(D => \REG_4[24]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1\, Q => ADDERout(24)); - - un2_resadd_ADD_27x27_fast_I3_P0N_i_o2 : OR2 - port map(A => ADDERinB(3), B => ADDERinA(3), Y => N_58); - - un2_resadd_ADD_27x27_fast_I15_P0N : OR2A - port map(A => ADDERinA(15), B => ADDERinB(15), Y => N371); - - un2_resadd_ADD_27x27_fast_I249_Y_0 : AX1D - port map(A => I212_un1_Y, B => ADD_27x27_fast_I212_Y_1, C - => ADD_27x27_fast_I249_Y_0_0, Y => \un2_resadd[19]\); - - un2_resadd_ADD_27x27_fast_I189_Y : AO1C - port map(A => N548, B => N533, C => N532, Y => N648); - - un2_resadd_ADD_27x27_fast_I4_G0N_i_o2 : NOR2B - port map(A => ADDERinB(4), B => ADDERinA(4), Y => N_52_i_0); - - un2_resadd_ADD_27x27_fast_I250_Y_0_0 : XOR2 - port map(A => ADDERinA(20), B => ADDERinB(20), Y => - ADD_27x27_fast_I250_Y_0_0); - - \REG_RNO_0[12]\ : MX2C - port map(A => ADDERinB(12), B => \un2_resadd[12]\, S => - add_D, Y => N_20); - - un2_resadd_ADD_27x27_fast_I44_Y : OA1A - port map(A => ADDERinA(17), B => ADDERinB(17), C => N374, Y - => N422); - - un2_resadd_ADD_27x27_fast_I233_Y_0 : XOR3 - port map(A => ADDERinB(3), B => ADDERinA(3), C => N_48, Y - => \un2_resadd[3]\); - - un2_resadd_ADD_27x27_fast_I194_un1_Y : NOR2B - port map(A => N_48, B => N543, Y => - ADD_27x27_fast_I194_un1_Y); - - un2_resadd_ADD_27x27_fast_I243_Y_0 : AX1A - port map(A => ADD_27x27_fast_I192_Y_0_a2, B => N361, C => - ADD_27x27_fast_I243_Y_0_0, Y => \un2_resadd[13]\); - - un2_resadd_ADD_27x27_fast_I146_Y : NOR2 - port map(A => N487, B => N479, Y => N533); - - \REG_RNO_0[14]\ : MX2C - port map(A => ADDERinB(14), B => \un2_resadd[14]\, S => - add_D_0, Y => N_22); - - \REG[16]\ : DFN1E0C0 - port map(D => \REG_4[16]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(16)); - - un2_resadd_ADD_27x27_fast_I62_Y_i_o2 : OAI1 - port map(A => ADDERinA(7), B => ADDERinB(7), C => N350, Y - => N_73); - - un2_resadd_ADD_27x27_fast_I102_Y : OR2B - port map(A => N434, B => N430, Y => N483); - - \REG_RNO_0[4]\ : MX2C - port map(A => ADDERinB(4), B => \un2_resadd[4]\, S => - add_D_0, Y => N_12); - - un2_resadd_ADD_27x27_fast_I20_G0N : NOR2B - port map(A => ADDERinB(20), B => ADDERinA(20), Y => N385); - - \REG_RNO_0[2]\ : MX2C - port map(A => ADDERinB(2), B => \un2_resadd[2]\, S => add_D, - Y => N_10); - - un2_resadd_ADD_27x27_fast_I82_Y : OR2B - port map(A => N414, B => N410, Y => N463); - - un2_resadd_ADD_27x27_fast_I234_Y_0 : XOR3 - port map(A => ADDERinB(4), B => ADDERinA(4), C => N502, Y - => \un2_resadd[4]\); - - un2_resadd_ADD_27x27_fast_I250_Y_0 : AX1E - port map(A => I211_un1_Y_i, B => ADD_27x27_fast_I211_Y_1, C - => ADD_27x27_fast_I250_Y_0_0, Y => \un2_resadd[20]\); - - un2_resadd_ADD_27x27_fast_I252_Y_0_0 : XOR2 - port map(A => ADDERinA(22), B => ADDERinB(22), Y => - ADD_27x27_fast_I252_Y_0_0); - - un2_resadd_ADD_27x27_fast_I244_Y_0 : XNOR3 - port map(A => ADDERinB(14), B => ADDERinA(14), C => N654_i, - Y => \un2_resadd[14]\); - - un2_resadd_ADD_27x27_fast_I69_Y_i_a2 : NOR2 - port map(A => N_59, B => N_52_i_0, Y => N_108); - - un2_resadd_ADD_27x27_fast_I18_G0N : NOR2B - port map(A => ADDERinB(18), B => ADDERinA(18), Y => N379); - - un2_resadd_ADD_27x27_fast_I13_G0N : NOR2B - port map(A => ADDERinB(13), B => ADDERinA(13), Y => N364); - - \REG_RNO_0[5]\ : MX2C - port map(A => ADDERinB(5), B => \un2_resadd[5]\, S => add_D, - Y => N_13); - - \REG[21]\ : DFN1E0C0 - port map(D => \REG_4[21]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1\, Q => ADDERout(21)); - - un2_resadd_ADD_27x27_fast_I237_Y_0 : XOR3 - port map(A => ADDERinB(7), B => ADDERinA(7), C => N550, Y - => \un2_resadd[7]\); - - \REG_RNO_0[22]\ : MX2C - port map(A => ADDERinB(22), B => \un2_resadd[22]\, S => - add_D_0, Y => N_30); - - un2_resadd_ADD_27x27_fast_I107_Y : AO1B - port map(A => N439, B => N436, C => ADD_27x27_fast_I107_Y_0, - Y => N488); - - un2_resadd_ADD_27x27_fast_I247_Y_0 : AX1 - port map(A => N423, B => N_98_i, C => - ADD_27x27_fast_I247_Y_0_0, Y => \un2_resadd[17]\); - - \REG_RNO[0]\ : NOR2 - port map(A => clr_MAC_D_0, B => N_8, Y => \REG_4[0]\); - - \REG_RNO_0[15]\ : MX2C - port map(A => ADDERinB(15), B => \un2_resadd[15]\, S => - add_D_0, Y => N_23); - - un2_resadd_ADD_27x27_fast_I148_Y : NOR2 - port map(A => N489, B => N481, Y => N535); - - \REG_RNO_0[24]\ : MX2C - port map(A => ADDERinB(24), B => \un2_resadd[24]\, S => - add_D, Y => N_32); - - un2_resadd_ADD_27x27_fast_I253_Y_0 : AX1E - port map(A => I208_un1_Y, B => ADD_27x27_fast_I208_Y_3, C - => ADD_27x27_fast_I253_Y_0_0, Y => \un2_resadd[23]\); - - un2_resadd_ADD_27x27_fast_I213_un1_Y_0 : NOR3B - port map(A => N499, B => N_47, C => N491, Y => - ADD_27x27_fast_I213_un1_Y_0); - - \REG[15]\ : DFN1E0C0 - port map(D => \REG_4[15]\, CLK => lclk_c, CLR => rstn, E - => \un1_clr_1_0\, Q => ADDERout(15)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_MUX2 is - - port( MULTout_D : in std_logic_vector(24 downto 7); - ADDERout : in std_logic_vector(24 downto 7); - sample_out_s : out std_logic_vector(17 downto 0); - MACMUX2sel_D_D : in std_logic - ); - -end MAC_MUX2; - -architecture DEF_ARCH of MAC_MUX2 is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \RES[19]\ : MX2 - port map(A => ADDERout(19), B => MULTout_D(19), S => - MACMUX2sel_D_D, Y => sample_out_s(12)); - - \RES[9]\ : MX2 - port map(A => ADDERout(9), B => MULTout_D(9), S => - MACMUX2sel_D_D, Y => sample_out_s(2)); - - GND_i_0 : GND - port map(Y => GND_0); - - \RES[12]\ : MX2 - port map(A => ADDERout(12), B => MULTout_D(12), S => - MACMUX2sel_D_D, Y => sample_out_s(5)); - - VCC_i : VCC - port map(Y => \VCC\); - - \RES[17]\ : MX2 - port map(A => ADDERout(17), B => MULTout_D(17), S => - MACMUX2sel_D_D, Y => sample_out_s(10)); - - \RES[22]\ : MX2 - port map(A => ADDERout(22), B => MULTout_D(22), S => - MACMUX2sel_D_D, Y => sample_out_s(15)); - - \RES[11]\ : MX2 - port map(A => ADDERout(11), B => MULTout_D(11), S => - MACMUX2sel_D_D, Y => sample_out_s(4)); - - \RES[18]\ : MX2 - port map(A => ADDERout(18), B => MULTout_D(18), S => - MACMUX2sel_D_D, Y => sample_out_s(11)); - - \RES[21]\ : MX2 - port map(A => ADDERout(21), B => MULTout_D(21), S => - MACMUX2sel_D_D, Y => sample_out_s(14)); - - \RES[14]\ : MX2 - port map(A => ADDERout(14), B => MULTout_D(14), S => - MACMUX2sel_D_D, Y => sample_out_s(7)); - - GND_i : GND - port map(Y => \GND\); - - \RES[24]\ : MX2 - port map(A => ADDERout(24), B => MULTout_D(24), S => - MACMUX2sel_D_D, Y => sample_out_s(17)); - - \RES[10]\ : MX2 - port map(A => ADDERout(10), B => MULTout_D(10), S => - MACMUX2sel_D_D, Y => sample_out_s(3)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \RES[8]\ : MX2 - port map(A => ADDERout(8), B => MULTout_D(8), S => - MACMUX2sel_D_D, Y => sample_out_s(1)); - - \RES[16]\ : MX2 - port map(A => ADDERout(16), B => MULTout_D(16), S => - MACMUX2sel_D_D, Y => sample_out_s(9)); - - \RES[20]\ : MX2 - port map(A => ADDERout(20), B => MULTout_D(20), S => - MACMUX2sel_D_D, Y => sample_out_s(13)); - - \RES[13]\ : MX2 - port map(A => ADDERout(13), B => MULTout_D(13), S => - MACMUX2sel_D_D, Y => sample_out_s(6)); - - \RES[7]\ : MX2 - port map(A => ADDERout(7), B => MULTout_D(7), S => - MACMUX2sel_D_D, Y => sample_out_s(0)); - - \RES[23]\ : MX2 - port map(A => ADDERout(23), B => MULTout_D(23), S => - MACMUX2sel_D_D, Y => sample_out_s(16)); - - \RES[15]\ : MX2 - port map(A => ADDERout(15), B => MULTout_D(15), S => - MACMUX2sel_D_D, Y => sample_out_s(8)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC_REG_1_2 is - - port( MACMUXsel_D : out std_logic; - MACMUXsel_D_0 : out std_logic; - N_4 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - MACMUXsel_D_1 : out std_logic - ); - -end MAC_REG_1_2; - -architecture DEF_ARCH of MAC_REG_1_2 is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Q_1[0]\ : DFN1C0 - port map(D => N_4, CLK => lclk_c, CLR => rstn, Q => - MACMUXsel_D_1); - - \Q_0[0]\ : DFN1C0 - port map(D => N_4, CLK => lclk_c, CLR => rstn, Q => - MACMUXsel_D_0); - - \Q[0]\ : DFN1C0 - port map(D => N_4, CLK => lclk_c, CLR => rstn, Q => - MACMUXsel_D); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Multiplier is - - port( MULTout : out std_logic_vector(24 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - mult : in std_logic; - mult_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end Multiplier; - -architecture DEF_ARCH of Multiplier is - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - signal I118_un1_Y, N398, N405, N397_i, I78_un1_Y_i, N352, - ADD_22x22_fast_I153_Y_0, ADD_22x22_fast_I209_Y_0_2, N_252, - ADD_22x22_fast_I209_Y_0_0, N_254, \a17_b_i[7]\, - ADD_22x22_fast_I207_Y_0_0, madd_583_0, madd_572, - ADD_22x22_fast_I206_Y_0_0, madd_568_0, madd_552, - ADD_22x22_fast_I172_Y_2, N453, N438, - ADD_22x22_fast_I172_Y_1, N399, N392, - ADD_22x22_fast_I172_Y_0, I72_un1_Y, - ADD_22x22_fast_I30_un1_Y, N321, ADD_22x22_fast_I170_Y_2, - I68_un1_Y, ADD_22x22_fast_I170_Y_0, I108_un1_Y, N324, - madd_587, N_253, ADD_22x22_fast_I171_Y_1, N348, N345, - ADD_22x22_fast_I171_Y_0, ADD_22x22_fast_I173_Y_2, N455, - N440, ADD_22x22_fast_I173_Y_1, N401, N394, - ADD_22x22_fast_I173_Y_0, N349, ADD_22x22_fast_I199_Y_0_0, - madd_347_0, madd_311, ADD_22x22_fast_I152_Y_0, N403, N396, - N395, ADD_22x22_fast_I170_Y_3_0, N388, - ADD_22x22_fast_I153_un1_Y_0, N568, N406, - ADD_22x22_fast_I196_Y_0_0, madd_200, madd_236_0, - ADD_22x22_fast_I155_un1_Y_0, N417, I135_un1_Y, N402, - ADD_22x22_fast_I194_Y_0_0, madd_124, madd_157_0, madd_126, - madd_194_0_0, N_81_i, madd_194_12, madd_416_0_0, - madd_416_8, N_179, madd_231_0_0, N_97_i, madd_231_12, - madd_268_0_0, N_113_i, madd_268_12, madd_342_0_0, N_145_i, - madd_342_12, madd_305_0_0, N_129_i, madd_305_12, - madd_194_12_0, madd_194_10, madd_151, madd_231_12_0, - N_82_i, madd_231_10, madd_194_10_0, madd_131, madd_136, - madd_578_0_0, madd_573_0, madd_305_8_0, madd_305_2, - madd_305_4, madd_493_6_0, \a11_b[7]\, \a_i10_b[8]\, - madd_543_2_0, \a16_b[4]\, \a15_b[5]\, madd_342_4_0, - \a11_b[3]\, \a9_b[5]\, madd_305_4_0, \a10_b[3]\, - \a8_b[5]\, madd_305_7_0, \a7_b[6]\, \a6_b[7]\, - madd_268_4_0, \a9_b[3]\, \a7_b[5]\, madd_39_2_0, - \a5_b[0]\, \a3_b[2]\, madd_342_2_0, \a14_b[0]\, - \a12_b[2]\, madd_305_2_0, \a13_b[0]\, \a11_b[2]\, - madd_268_2_0, \a12_b[0]\, \a10_b[2]\, madd_157_7_0, - \a3_b[6]\, \a2_b[7]\, madd_0_s_0, \a2_b[0]\, \a1_b[1]\, - madd_39_4_0, \a2_b[3]\, \a1_b[4]\, N544, I155_un1_Y, N365, - N369, N550, I122_un1_Y, I172_un1_Y, N454, N378, - I173_un1_Y, N456, madd_28, N535, I110_un1_Y, - ADD_22x22_fast_I171_Y_3, I152_un1_Y, N565, N404, N541, - I154_un1_Y, N400, N408, N461, N547, I120_un1_Y, N_251, - \a16_b[7]\, \a_i15_b[8]\, \a17_b_i[6]\, madd_416_0, - madd_378, N_175_i, madd_358, N_154_i, madd_363, madd_368, - madd_373, N_57, \a7_b[2]\, \a9_b[0]\, \a8_b[1]\, N_59_i, - \a4_b[5]\, \a6_b[3]\, \a5_b[4]\, madd_157_11, N_48, - madd_115_0, N_47, N_45_i, madd_82, \a3_b[5]\, \a5_b[3]\, - \a4_b[4]\, \a1_b[7]\, \a2_b[6]\, \a0_b[8]\, madd_39_0, - madd_39_2, N_15, N_8, \a0_b[5]\, N_7_i, \a2_b[2]\, - \a4_b[0]\, \a3_b[1]\, \RESMULT[23]\, \RESMULT[22]\, - \RESMULT[21]\, \RESMULT[20]\, madd_527, madd_548_0, - \RESMULT[19]\, madd_497, madd_523_0, \RESMULT[18]\, - madd_462, madd_493_0, \RESMULT[17]\, madd_458_0, madd_422, - \RESMULT[16]\, madd_385, madd_421_0, N553_i, - \RESMULT[15]\, madd_348, madd_384_0, N556_i, - \RESMULT[14]\, ADD_22x22_fast_I158_un1_Y, \RESMULT[13]\, - madd_274, madd_310_0, N562_i, \RESMULT[12]\, madd_237, - madd_273_0, \RESMULT[11]\, \RESMULT[10]\, madd_163, - madd_199_0, \RESMULT[9]\, \RESMULT[8]\, madd_125_0, - madd_120_0, N419, \RESMULT[7]\, madd_93_0, madd_67, N421, - \RESMULT[6]\, madd_66_0, madd_61_0, \RESMULT[5]\, CO3, - madd_44_0, \RESMULT[24]\, ADD_22x22_fast_I170_Y_3, - madd_577, madd_582, madd_543_4, \a13_b[7]\, \a14_b[6]\, - \a_i12_b[8]\, \a16_b[6]\, \a15_b[7]\, \a17_b_i[5]\, - madd_458_2, \a16_b[1]\, madd_458_14, madd_458_9, - madd_458_10, madd_415, madd_458_13, madd_405, madd_458_7, - madd_410, madd_458_4, madd_400, madd_390, \a_i9_b[8]\, - madd_395, \a10_b[7]\, \a12_b[5]\, \a11_b[6]\, \a13_b[4]\, - \a15_b[2]\, \a14_b[3]\, madd_420, madd_4_0, \a1_b[2]\, - \a3_b[0]\, \a2_b[1]\, madd_9_0, \a0_b[3]\, madd_3, - madd_24_4, \a0_b[4]\, \a1_b[3]\, madd_8, madd_24_0, - madd_13, \a4_b[1]\, madd_61_4, \a1_b[5]\, \a3_b[3]\, - \a2_b[4]\, madd_61_2, \a4_b[2]\, \a6_b[0]\, \a5_b[1]\, - madd_43, madd_56_0, madd_33, \a0_b[6]\, madd_38, - madd_88_8, madd_88_4, madd_88_2, madd_55, madd_88_7, - \a0_b[7]\, \a1_b[6]\, madd_50, \a2_b[5]\, \a4_b[3]\, - \a3_b[4]\, \a5_b[2]\, \a7_b[0]\, \a6_b[1]\, madd_88_0, - madd_60, madd_95_0, \a6_b[2]\, \a8_b[0]\, \a7_b[1]\, - madd_110_0, madd_72, madd_77, N_38_i, madd_92, - madd_157_12, madd_157_9, madd_157_7, madd_114, madd_99, - \a_i0_b[8]\, madd_104, \a_i1_b[8]\, madd_119, madd_146, - madd_141, madd_194_4, madd_194_2, madd_194_7, \a3_b[7]\, - \a4_b[6]\, \a_i2_b[8]\, \a5_b[5]\, \a7_b[3]\, \a6_b[4]\, - \a8_b[2]\, \a10_b[0]\, \a9_b[1]\, madd_183, madd_173, - N_74_i, madd_178, madd_231_4, madd_231_2, madd_231_7, - \a4_b[7]\, \a5_b[6]\, \a_i3_b[8]\, \a6_b[5]\, \a8_b[3]\, - \a7_b[4]\, \a9_b[2]\, \a11_b[0]\, \a10_b[1]\, madd_268_10, - N_98_i, madd_220, madd_210, N_90_i, madd_215, madd_268_4, - madd_268_2, madd_268_7, \a5_b[7]\, \a6_b[6]\, \a_i4_b[8]\, - \a8_b[4]\, \a11_b[1]\, madd_305_10, N_114_i, madd_257, - madd_247, N_106_i, madd_252, madd_305_7, \a_i5_b[8]\, - \a9_b[4]\, \a12_b[1]\, madd_342_10, N_130_i, madd_294, - madd_284, N_122_i, madd_289, madd_342_4, madd_342_2, - madd_342_7, \a7_b[7]\, \a8_b[6]\, \a_i6_b[8]\, \a10_b[4]\, - \a13_b[1]\, madd_379_12, madd_379_10, madd_336, madd_331, - madd_321, N_138_i, madd_326, N_161_i, madd_379_4, - madd_379_2, madd_379_7, \a8_b[7]\, \a9_b[6]\, \a_i7_b[8]\, - \a10_b[5]\, \a12_b[3]\, \a11_b[4]\, \a13_b[2]\, - \a15_b[0]\, \a14_b[1]\, madd_379_0, madd_341, madd_416_4, - madd_416_2, madd_416_7, \a9_b[7]\, \a10_b[6]\, - \a_i8_b[8]\, \a11_b[5]\, \a13_b[3]\, \a12_b[4]\, - \a14_b[2]\, \a16_b[0]\, \a15_b[1]\, madd_493_12, - madd_493_8, madd_493_6, madd_452, madd_493_11, madd_442, - madd_493_4, madd_447, madd_432, madd_493_2, madd_437, - madd_427_1, \a12_b[6]\, \a14_b[4]\, \a13_b[5]\, - \a15_b[3]\, \a16_b[2]\, \a17_b_i[1]\, madd_457, - madd_523_10, madd_482, madd_523_7, madd_487, madd_523_8, - madd_523_4, madd_523_2, madd_477, madd_472, \a_i11_b[8]\, - madd_467, \a12_b[7]\, \a14_b[5]\, \a13_b[6]\, \a15_b[4]\, - \a16_b[3]\, \a17_b_i[2]\, madd_492, madd_543_6, madd_507, - madd_543_2, madd_502, \a17_b_i[3]\, madd_543_0, madd_512, - madd_517, madd_522, madd_568_6, madd_537, madd_568_2, - madd_542, madd_568_4, \a_i13_b[8]\, \a14_b[7]\, madd_532, - \a15_b[6]\, \a16_b[5]\, \a17_b_i[4]\, madd_547, - madd_578_0, madd_557, madd_562, madd_567, - ADD_22x22_fast_I170_un1_Y_0, N449, N390, - ADD_22x22_fast_I171_Y_3_tz, N452, N451, madd_582_0, - madd_582_0_tz, N450, madd_334, madd_383, madd_346, - madd_304, madd_309, madd_267, madd_272, madd_230, - madd_235, madd_193, madd_198, madd_156, madd_161, madd_65, - madd_23, \a0_b[2]\, CO0, \a1_b[0]\, CO2, CO1, - \RESMULT[1]\, \RESMULT[3]\, \RESMULT[4]\, N276, N277, - N319, N322, N350, ADD_22x22_fast_I90_un1_Y, N368, N413, - N372, N376, N373, N418, N377, I101_un1_Y, N364, - I130_un1_Y, I157_un1_Y, N343, I76_un1_Y, N411, N412, N351, - \RESMULT[0]\, N328, \RESMULT[2]\, N416, N375, N371, N295, - N298, N367, N407, N362, I88_un1_Y, N359, N355, N280, N286, - N292, N289, N366, N288, N304, N301, N358, N303, I42_un1_Y, - N310, N307, N316, N313, N415, N374, N370, I38_un1_Y_i, - I80_un1_Y_i, N309, I54_un1_Y_i, N285, N282, N312, N325, - N315, N361, N360, N297, I133_un1_Y, I126_un1_Y, N357, - N356, N353, N274, N273, N279, I48_un1_Y_i, N294, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - RESMULT_madd_606_ADD_22x22_fast_I68_un1_Y : OAI1 - port map(A => ADD_22x22_fast_I30_un1_Y, B => N321, C => - N343, Y => I68_un1_Y); - - RESMULT_madd_120_0 : XOR3 - port map(A => N_38_i, B => madd_110_0, C => madd_92, Y => - madd_120_0); - - RESMULT_madd_452 : MAJ3 - port map(A => madd_458_7, B => madd_405, C => madd_410, Y - => madd_452); - - \RESMULT_a9_b[1]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(1), Y => - \a9_b[1]\); - - RESMULT_madd_65 : MIN3 - port map(A => madd_61_2, B => madd_43, C => madd_61_4, Y - => madd_65); - - RESMULT_madd_420 : MAJ3 - port map(A => madd_416_8, B => madd_378, C => N_179, Y => - madd_420); - - RESMULT_madd_523_0 : XOR3 - port map(A => madd_523_10, B => madd_523_8, C => madd_492, - Y => madd_523_0); - - \RESMULT_a4_b[2]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(2), Y => - \a4_b[2]\); - - RESMULT_madd_552 : MIN3 - port map(A => madd_517, B => madd_522, C => madd_543_0, Y - => madd_552); - - RESMULT_madd_231_0_0 : XOR2 - port map(A => N_97_i, B => madd_231_12, Y => madd_231_0_0); - - \RESMULT_a9_b[4]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(4), Y => - \a9_b[4]\); - - RESMULT_madd_267 : AO13 - port map(A => madd_220, B => N_98_i, C => madd_268_10, Y - => madd_267); - - \RESMULT_a11_b[5]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(5), Y => - \a11_b[5]\); - - \RESMULT_a10_b[7]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(7), Y => - \a10_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I58_Y : MAJ3 - port map(A => madd_67, B => madd_93_0, C => N276, Y => N374); - - RESMULT_madd_606_ADD_22x22_fast_I55_Y : OA1 - port map(A => madd_120_0, B => madd_125_0, C => N286, Y => - N371); - - RESMULT_madd_606_ADD_22x22_fast_I99_Y : OR2B - port map(A => N377, B => N373, Y => N418); - - RESMULT_madd_146 : MAJ3 - port map(A => \a_i0_b[8]\, B => madd_99, C => madd_104, Y - => madd_146); - - RESMULT_madd_378 : MAJ3 - port map(A => madd_336, B => madd_331, C => madd_379_10, Y - => madd_378); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_0 : OA1C - port map(A => N352, B => N349, C => N348, Y => - ADD_22x22_fast_I173_Y_0); - - \RESMULT_a11_b[0]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(0), Y => - \a11_b[0]\); - - \RESMULT_a13_b[7]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(7), Y => - \a13_b[7]\); - - RESMULT_madd_43 : MAJ3 - port map(A => N_15, B => N_8, C => madd_39_2, Y => madd_43); - - RESMULT_madd_310_0 : XNOR3 - port map(A => madd_267, B => madd_305_0_0, C => madd_272, Y - => madd_310_0); - - RESMULT_madd_141 : MAJ3 - port map(A => \a3_b[6]\, B => \a2_b[7]\, C => \a_i1_b[8]\, - Y => madd_141); - - \RESMULT_a7_b[7]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(7), Y => - \a7_b[7]\); - - RESMULT_madd_235 : AO13 - port map(A => madd_193, B => N_97_i, C => madd_231_12, Y - => madd_235); - - RESMULT_madd_38 : MAJ3 - port map(A => \a2_b[3]\, B => \a0_b[5]\, C => \a1_b[4]\, Y - => madd_38); - - \REG[6]\ : DFN1E1C0 - port map(D => \RESMULT[6]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(6)); - - RESMULT_madd_231_12_0 : XOR2 - port map(A => N_82_i, B => madd_231_10, Y => madd_231_12_0); - - RESMULT_madd_200 : XA1B - port map(A => madd_156, B => madd_194_0_0, C => madd_161, Y - => madd_200); - - RESMULT_madd_104 : MAJ3 - port map(A => \a5_b[3]\, B => \a3_b[5]\, C => \a4_b[4]\, Y - => madd_104); - - \RESMULT_a14_b[7]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(7), Y => - \a14_b[7]\); - - \RESMULT_a6_b[7]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(7), Y => - \a6_b[7]\); - - \RESMULT_a0_b[3]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(3), Y => - \a0_b[3]\); - - \RESMULT_a4_b[3]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(3), Y => - \a4_b[3]\); - - \RESMULT_a15_b[4]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(4), Y => - \a15_b[4]\); - - RESMULT_madd_247 : MIN3 - port map(A => \a9_b[3]\, B => \a7_b[5]\, C => \a8_b[4]\, Y - => madd_247); - - RESMULT_madd_93_0 : XNOR2 - port map(A => madd_88_0, B => madd_65, Y => madd_93_0); - - RESMULT_madd_606_ADD_22x22_fast_I122_un1_Y : OAI1 - port map(A => ADD_22x22_fast_I90_un1_Y, B => N364, C => - N402, Y => I122_un1_Y); - - RESMULT_madd_523_8 : XOR3 - port map(A => madd_523_4, B => madd_523_2, C => madd_477, Y - => madd_523_8); - - \RESMULT_a16_b[7]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(7), Y => - \a16_b[7]\); - - RESMULT_madd_458_0 : XOR3 - port map(A => madd_458_14, B => madd_458_13, C => madd_420, - Y => madd_458_0); - - RESMULT_madd_61_0 : XOR3 - port map(A => madd_61_4, B => madd_61_2, C => madd_43, Y - => madd_61_0); - - \RESMULT_a9_b[0]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(0), Y => - \a9_b[0]\); - - \RESMULT_a6_b[1]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(1), Y => - \a6_b[1]\); - - \RESMULT_a13_b[0]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(0), Y => - \a13_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I73_Y : NOR3C - port map(A => N319, B => N322, C => N351, Y => N392); - - RESMULT_madd_507 : MAJ3 - port map(A => \a14_b[5]\, B => \a12_b[7]\, C => \a13_b[6]\, - Y => madd_507); - - RESMULT_madd_606_ADD_22x22_fast_I155_un1_Y : OR3C - port map(A => N365, B => N369, C => - ADD_22x22_fast_I155_un1_Y_0, Y => I155_un1_Y); - - RESMULT_madd_458_10 : XOR3 - port map(A => madd_458_4, B => madd_458_2, C => madd_400, Y - => madd_458_10); - - RESMULT_madd_252 : MIN3 - port map(A => \a6_b[6]\, B => \a5_b[7]\, C => \a_i4_b[8]\, - Y => madd_252); - - RESMULT_madd_472 : MAJ3 - port map(A => \a14_b[4]\, B => \a12_b[6]\, C => \a13_b[5]\, - Y => madd_472); - - RESMULT_madd_67 : NOR3B - port map(A => madd_39_0, B => madd_56_0, C => madd_23, Y - => madd_67); - - RESMULT_madd_95_0 : XOR3 - port map(A => \a6_b[2]\, B => \a8_b[0]\, C => \a7_b[1]\, Y - => madd_95_0); - - \REG[18]\ : DFN1E1C0 - port map(D => \RESMULT[18]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(18)); - - RESMULT_madd_568_4 : XOR3 - port map(A => \a_i13_b[8]\, B => \a14_b[7]\, C => madd_532, - Y => madd_568_4); - - \RESMULT_a1_b[6]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(6), Y => - \a1_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I197_Y_0 : XOR3 - port map(A => madd_237, B => madd_273_0, C => N565, Y => - \RESMULT[12]\); - - RESMULT_madd_572 : MAJ3 - port map(A => madd_568_4, B => madd_547, C => madd_568_6, Y - => madd_572); - - \RESMULT_a7_b[0]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(0), Y => - \a7_b[0]\); - - RESMULT_madd_88_4 : XOR3 - port map(A => \a2_b[5]\, B => \a4_b[3]\, C => \a3_b[4]\, Y - => madd_88_4); - - RESMULT_madd_72 : MAJ3 - port map(A => \a7_b[0]\, B => \a5_b[2]\, C => \a6_b[1]\, Y - => madd_72); - - RESMULT_madd_230 : AO13 - port map(A => madd_183, B => N_82_i, C => madd_231_10, Y - => madd_230); - - RESMULT_madd_88_8 : XOR3 - port map(A => madd_88_4, B => madd_88_2, C => madd_55, Y - => madd_88_8); - - RESMULT_madd_606_ADD_22x22_fast_I80_un1_Y : OR2B - port map(A => N358, B => N355, Y => I80_un1_Y_i); - - RESMULT_madd_66_0 : AX1 - port map(A => madd_23, B => madd_39_0, C => madd_56_0, Y - => madd_66_0); - - RESMULT_madd_606_ADD_22x22_fast_I204_Y_0 : XNOR3 - port map(A => madd_497, B => madd_523_0, C => N544, Y => - \RESMULT[19]\); - - RESMULT_madd_606_ADD_22x22_fast_I131_Y : NOR3B - port map(A => N365, B => N369, C => N418, Y => N456); - - RESMULT_madd_231_12 : XOR2 - port map(A => madd_231_12_0, B => madd_183, Y => - madd_231_12); - - RESMULT_madd_194_4 : XOR3 - port map(A => \a5_b[5]\, B => \a7_b[3]\, C => \a6_b[4]\, Y - => madd_194_4); - - RESMULT_madd_458_2 : AX1E - port map(A => alu_coef_s(0), B => alu_sample(17), C => - \a16_b[1]\, Y => madd_458_2); - - \RESMULT_a_i13_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(13), Y => - \a_i13_b[8]\); - - \REG[19]\ : DFN1E1C0 - port map(D => \RESMULT[19]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(19)); - - \RESMULT_a6_b[0]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(0), Y => - \a6_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I34_Y : AO13 - port map(A => N312, B => madd_523_0, C => madd_497, Y => - N350); - - RESMULT_madd_606_ADD_22x22_fast_I5_P0N : OR2 - port map(A => madd_199_0, B => madd_163, Y => N289); - - RESMULT_madd_606_ADD_22x22_fast_I83_Y : NOR2B - port map(A => N361, B => N357, Y => N402); - - RESMULT_madd_537 : MAJ3 - port map(A => \a14_b[6]\, B => \a13_b[7]\, C => - \a_i12_b[8]\, Y => madd_537); - - RESMULT_madd_606_ADD_22x22_fast_I152_Y_0 : AO1 - port map(A => N403, B => N396, C => N395, Y => - ADD_22x22_fast_I152_Y_0); - - \RESMULT_a13_b[2]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(2), Y => - \a13_b[2]\); - - RESMULT_madd_416_4 : XOR3 - port map(A => \a11_b[5]\, B => \a13_b[3]\, C => \a12_b[4]\, - Y => madd_416_4); - - RESMULT_madd_606_ADD_22x22_fast_I42_Y : OR2 - port map(A => N303, B => I42_un1_Y, Y => N358); - - RESMULT_madd_606_ADD_22x22_fast_I16_G0N : NOR2A - port map(A => madd_568_0, B => madd_552, Y => N321); - - \RESMULT_a_i0_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(0), Y => - \a_i0_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I30_un1_Y : NOR3B - port map(A => madd_548_0, B => N322, C => madd_527, Y => - ADD_22x22_fast_I30_un1_Y); - - RESMULT_madd_437 : MAJ3 - port map(A => \a12_b[5]\, B => \a10_b[7]\, C => \a11_b[6]\, - Y => madd_437); - - RESMULT_madd_606_ADD_22x22_fast_I100_Y : AO1 - port map(A => N378, B => N375, C => N374, Y => N419); - - RESMULT_madd_606_ADD_22x22_fast_I199_Y_0_0 : XOR2 - port map(A => madd_347_0, B => madd_311, Y => - ADD_22x22_fast_I199_Y_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I98_Y : AOI1 - port map(A => N376, B => N373, C => N372, Y => N417); - - \RESMULT_a4_b[7]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(7), Y => - \a4_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I9_P0N : OR2 - port map(A => madd_347_0, B => madd_311, Y => N301); - - RESMULT_madd_304 : AO13 - port map(A => madd_257, B => N_114_i, C => madd_305_10, Y - => madd_304); - - \RESMULT_a_i9_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(9), Y => - \a_i9_b[8]\); - - \REG[1]\ : DFN1E1C0 - port map(D => \RESMULT[1]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(1)); - - \RESMULT_a5_b[1]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(1), Y => - \a5_b[1]\); - - \RESMULT_a1_b[7]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(7), Y => - \a1_b[7]\); - - \RESMULT_a1_b[4]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(4), Y => - \a1_b[4]\); - - RESMULT_madd_39_2_0 : XOR2 - port map(A => \a5_b[0]\, B => \a3_b[2]\, Y => madd_39_2_0); - - RESMULT_madd_606_ADD_22x22_fast_I133_un1_Y : NOR3C - port map(A => N369, B => N373, C => N421, Y => I133_un1_Y); - - RESMULT_madd_583_0 : XOR3 - port map(A => madd_562, B => madd_578_0, C => madd_567, Y - => madd_583_0); - - RESMULT_madd_18 : MAJ3 - port map(A => \a4_b[0]\, B => \a2_b[2]\, C => \a3_b[1]\, Y - => N_8); - - \RESMULT_a9_b[7]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(7), Y => - \a9_b[7]\); - - RESMULT_madd_492 : MAJ3 - port map(A => madd_493_6, B => madd_452, C => madd_493_8, Y - => madd_492); - - \RESMULT_a0_b[5]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(5), Y => - \a0_b[5]\); - - \RESMULT_a2_b[4]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(4), Y => - \a2_b[4]\); - - RESMULT_madd_272 : AO13 - port map(A => madd_230, B => N_113_i, C => madd_268_12, Y - => madd_272); - - \RESMULT_a9_b[5]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(5), Y => - \a9_b[5]\); - - RESMULT_madd_225 : MIN3 - port map(A => madd_231_2, B => madd_231_4, C => madd_231_7, - Y => N_98_i); - - RESMULT_madd_606_ADD_22x22_fast_I194_Y_0 : AX1E - port map(A => I135_un1_Y, B => N417, C => - ADD_22x22_fast_I194_Y_0_0, Y => \RESMULT[9]\); - - RESMULT_madd_592 : MAJ3 - port map(A => \a_i15_b[8]\, B => \a16_b[7]\, C => - \a17_b_i[6]\, Y => N_252); - - RESMULT_madd_194_10_0 : XOR2 - port map(A => madd_131, B => madd_136, Y => madd_194_10_0); - - RESMULT_madd_458_7 : XOR3 - port map(A => \a10_b[7]\, B => \a12_b[5]\, C => \a11_b[6]\, - Y => madd_458_7); - - \RESMULT_a10_b[4]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(4), Y => - \a10_b[4]\); - - \RESMULT_a0_b[7]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(7), Y => - \a0_b[7]\); - - RESMULT_madd_588_0 : XNOR3 - port map(A => \a16_b[7]\, B => \a_i15_b[8]\, C => - \a17_b_i[6]\, Y => N_251); - - \RESMULT_a15_b[1]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(1), Y => - \a15_b[1]\); - - \RESMULT_a0_b[8]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(8), Y => - \a0_b[8]\); - - RESMULT_madd_24_4 : XNOR3 - port map(A => \a0_b[4]\, B => \a1_b[3]\, C => madd_8, Y => - madd_24_4); - - RESMULT_madd_606_ADD_22x22_fast_I198_Y_0 : XNOR3 - port map(A => madd_274, B => madd_310_0, C => N562_i, Y => - \RESMULT[13]\); - - \REG[15]\ : DFN1E1C0 - port map(D => \RESMULT[15]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(15)); - - RESMULT_madd_39_4_0 : XOR2 - port map(A => \a2_b[3]\, B => \a1_b[4]\, Y => madd_39_4_0); - - \RESMULT_a_i5_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(5), Y => - \a_i5_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I134_Y : AO1 - port map(A => N416, B => N378, C => N415, Y => N461); - - RESMULT_madd_606_ADD_22x22_fast_I8_P0N : OR2 - port map(A => madd_310_0, B => madd_274, Y => N298); - - \REG[3]\ : DFN1E1C0 - port map(D => \RESMULT[3]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(3)); - - RESMULT_madd_606_ADD_22x22_fast_I80_Y : OR3B - port map(A => I38_un1_Y_i, B => I80_un1_Y_i, C => N309, Y - => N399); - - RESMULT_madd_606_ADD_22x22_fast_I52_Y : MAJ3 - port map(A => madd_163, B => madd_199_0, C => N285, Y => - N368); - - RESMULT_madd_606_ADD_22x22_fast_I27_Y : NOR2B - port map(A => N328, B => N325, Y => N343); - - \RESMULT_a_i12_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(12), Y => - \a_i12_b[8]\); - - \RESMULT_a16_b[1]\ : OR2B - port map(A => alu_sample(16), B => alu_coef_s(1), Y => - \a16_b[1]\); - - RESMULT_madd_273_0 : XNOR3 - port map(A => madd_230, B => madd_268_0_0, C => madd_235, Y - => madd_273_0); - - \RESMULT_a10_b[6]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(6), Y => - \a10_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I71_Y : NOR2 - port map(A => N349, B => N345, Y => N390); - - RESMULT_madd_119 : AO18 - port map(A => madd_82, B => N_47, C => N_45_i, Y => - madd_119); - - RESMULT_madd_61_2 : XOR3 - port map(A => \a4_b[2]\, B => \a6_b[0]\, C => \a5_b[1]\, Y - => madd_61_2); - - RESMULT_madd_606_ADD_22x22_fast_I199_Y_0 : AX1D - port map(A => ADD_22x22_fast_I158_un1_Y, B => N453, C => - ADD_22x22_fast_I199_Y_0_0, Y => \RESMULT[14]\); - - \RESMULT_a6_b[5]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(5), Y => - \a6_b[5]\); - - RESMULT_madd_305_2 : XOR2 - port map(A => madd_305_2_0, B => \a12_b[1]\, Y => - madd_305_2); - - \RESMULT_a15_b[3]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(3), Y => - \a15_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I39_Y : NOR2B - port map(A => N310, B => N307, Y => N355); - - \RESMULT_a3_b[6]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(6), Y => - \a3_b[6]\); - - RESMULT_madd_342_2 : XOR2 - port map(A => madd_342_2_0, B => \a13_b[1]\, Y => - madd_342_2); - - \RESMULT_a5_b[6]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(6), Y => - \a5_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_2 : AOI1B - port map(A => N453, B => N438, C => ADD_22x22_fast_I172_Y_1, - Y => ADD_22x22_fast_I172_Y_2); - - RESMULT_madd_331 : MIN3 - port map(A => N_122_i, B => madd_284, C => madd_289, Y => - madd_331); - - RESMULT_madd_606_ADD_22x22_fast_I5_G0N : NOR2B - port map(A => madd_199_0, B => madd_163, Y => N288); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_3 : OR3C - port map(A => N398, B => N390, C => - ADD_22x22_fast_I171_Y_3_tz, Y => ADD_22x22_fast_I171_Y_3); - - RESMULT_madd_410 : MAJ3 - port map(A => madd_416_2, B => madd_416_4, C => madd_416_7, - Y => madd_410); - - RESMULT_madd_220 : MAJ3 - port map(A => N_74_i, B => madd_173, C => madd_178, Y => - madd_220); - - RESMULT_madd_124 : AO13 - port map(A => madd_92, B => N_38_i, C => madd_110_0, Y => - madd_124); - - RESMULT_madd_606_ADD_22x22_fast_I108_un1_Y : OR2B - port map(A => N395, B => N388, Y => I108_un1_Y); - - RESMULT_madd_24_0 : XOR3 - port map(A => madd_24_4, B => N_7_i, C => madd_13, Y => - madd_24_0); - - RESMULT_madd_416_10 : XOR3 - port map(A => madd_358, B => N_154_i, C => madd_363, Y => - N_175_i); - - \RESMULT_a6_b[6]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(6), Y => - \a6_b[6]\); - - RESMULT_madd_363 : MIN3 - port map(A => \a9_b[6]\, B => \a8_b[7]\, C => \a_i7_b[8]\, - Y => madd_363); - - \RESMULT_a17_b_i[3]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(3), Y => - \a17_b_i[3]\); - - \RESMULT_a8_b[2]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(2), Y => - \a8_b[2]\); - - RESMULT_madd_268_2 : XOR2 - port map(A => madd_268_2_0, B => \a11_b[1]\, Y => - madd_268_2); - - RESMULT_madd_606_ADD_22x22_fast_I62_Y : MAJ3 - port map(A => madd_44_0, B => CO3, C => madd_28, Y => N378); - - \REG[10]\ : DFN1E1C0 - port map(D => \RESMULT[10]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(10)); - - RESMULT_madd_606_ADD_22x22_fast_I135_un1_Y : OR2A - port map(A => madd_28, B => N418, Y => I135_un1_Y); - - RESMULT_madd_110_0 : XOR3 - port map(A => madd_72, B => madd_95_0, C => madd_77, Y => - madd_110_0); - - RESMULT_madd_606_ADD_22x22_fast_I81_Y : NOR2B - port map(A => N359, B => N355, Y => N400); - - \RESMULT_a11_b[6]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(6), Y => - \a11_b[6]\); - - \REG[12]\ : DFN1E1C0 - port map(D => \RESMULT[12]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(12)); - - \RESMULT_a11_b[3]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(3), Y => - \a11_b[3]\); - - RESMULT_madd_55 : MAJ3 - port map(A => \a3_b[3]\, B => \a1_b[5]\, C => \a2_b[4]\, Y - => madd_55); - - RESMULT_madd_527 : MIN3 - port map(A => madd_523_8, B => madd_492, C => madd_523_10, - Y => madd_527); - - \RESMULT_a_i4_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(4), Y => - \a_i4_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I6_P0N : OR2 - port map(A => madd_236_0, B => madd_200, Y => N292); - - RESMULT_madd_567 : MAJ3 - port map(A => madd_537, B => madd_542, C => madd_568_2, Y - => madd_567); - - RESMULT_madd_421_0 : XNOR2 - port map(A => madd_416_0, B => madd_383, Y => madd_421_0); - - \RESMULT_a_i11_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(11), Y => - \a_i11_b[8]\); - - RESMULT_madd_342_12 : XOR3 - port map(A => madd_342_10, B => N_130_i, C => madd_294, Y - => madd_342_12); - - RESMULT_madd_467 : MAJ3 - port map(A => \a16_b[2]\, B => \a15_b[3]\, C => - \a17_b_i[1]\, Y => madd_467); - - RESMULT_madd_236_0 : XNOR3 - port map(A => madd_193, B => madd_231_0_0, C => madd_198, Y - => madd_236_0); - - RESMULT_madd_383 : AO13 - port map(A => madd_341, B => N_161_i, C => madd_379_12, Y - => madd_383); - - RESMULT_madd_606_ADD_22x22_fast_I170_un1_Y_0 : NOR2B - port map(A => N450, B => N419, Y => - ADD_22x22_fast_I170_un1_Y_0); - - RESMULT_madd_379_0 : XOR3 - port map(A => madd_379_12, B => N_161_i, C => madd_341, Y - => madd_379_0); - - RESMULT_madd_606_ADD_22x22_fast_I54_un1_Y : OR2B - port map(A => N286, B => N282, Y => I54_un1_Y_i); - - RESMULT_madd_606_ADD_22x22_fast_I46_Y : MAJ3 - port map(A => madd_274, B => madd_310_0, C => N294, Y => - N362); - - RESMULT_madd_194_12_0 : XOR2 - port map(A => madd_194_10, B => madd_151, Y => - madd_194_12_0); - - RESMULT_madd_606_ADD_22x22_fast_I155_Y : OR3B - port map(A => I155_un1_Y, B => I122_un1_Y, C => N401, Y => - N550); - - \REG[11]\ : DFN1E1C0 - port map(D => \RESMULT[11]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(11)); - - RESMULT_madd_587 : MIN3 - port map(A => madd_562, B => madd_567, C => madd_578_0, Y - => madd_587); - - RESMULT_madd_543_2_0 : XOR2 - port map(A => \a16_b[4]\, B => \a15_b[5]\, Y => - madd_543_2_0); - - GND_i : GND - port map(Y => \GND\); - - \RESMULT_a7_b[3]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(3), Y => - \a7_b[3]\); - - \RESMULT_a8_b[6]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(6), Y => - \a8_b[6]\); - - \RESMULT_a3_b[3]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(3), Y => - \a3_b[3]\); - - RESMULT_madd_231_10 : XNOR3 - port map(A => madd_173, B => N_74_i, C => madd_178, Y => - madd_231_10); - - RESMULT_madd_157_4 : XNOR3 - port map(A => \a4_b[5]\, B => \a6_b[3]\, C => \a5_b[4]\, Y - => N_59_i); - - RESMULT_madd_487 : MAJ3 - port map(A => madd_493_4, B => madd_442, C => madd_447, Y - => madd_487); - - RESMULT_madd_385 : NOR2A - port map(A => madd_379_0, B => madd_346, Y => madd_385); - - RESMULT_madd_157_9 : XOR3 - port map(A => madd_99, B => \a_i0_b[8]\, C => madd_104, Y - => madd_157_9); - - RESMULT_madd_606_ADD_22x22_fast_I206_Y_0_0 : XNOR2 - port map(A => madd_568_0, B => madd_552, Y => - ADD_22x22_fast_I206_Y_0_0); - - RESMULT_madd_305_2_0 : XOR2 - port map(A => \a13_b[0]\, B => \a11_b[2]\, Y => - madd_305_2_0); - - RESMULT_madd_606_ADD_22x22_fast_I126_un1_Y : NOR2A - port map(A => N413, B => N406, Y => I126_un1_Y); - - RESMULT_madd_547 : MAJ3 - port map(A => madd_543_4, B => madd_512, C => madd_543_6, Y - => madd_547); - - \RESMULT_a5_b[7]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(7), Y => - \a5_b[7]\); - - \REG[20]\ : DFN1E1C0 - port map(D => \RESMULT[20]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(20)); - - RESMULT_madd_60 : MAJ3 - port map(A => \a0_b[6]\, B => madd_33, C => madd_38, Y => - madd_60); - - \RESMULT_a10_b[0]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(0), Y => - \a10_b[0]\); - - \REG[22]\ : DFN1E1C0 - port map(D => \RESMULT[22]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(22)); - - RESMULT_madd_447 : MAJ3 - port map(A => madd_458_2, B => madd_400, C => madd_458_4, Y - => madd_447); - - RESMULT_madd_502 : MAJ3 - port map(A => \a16_b[3]\, B => \a15_b[4]\, C => - \a17_b_i[2]\, Y => madd_502); - - RESMULT_madd_305_0_0 : XOR2 - port map(A => N_129_i, B => madd_305_12, Y => madd_305_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I92_Y : AO1 - port map(A => N370, B => N367, C => N366, Y => N411); - - RESMULT_madd_606_ADD_22x22_fast_I84_Y : AO1 - port map(A => N362, B => N359, C => N358, Y => N403); - - RESMULT_madd_194_12 : XOR2 - port map(A => madd_194_12_0, B => madd_146, Y => - madd_194_12); - - \RESMULT_a15_b[0]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(0), Y => - \a15_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I190_Y_0 : XOR3 - port map(A => CO3, B => madd_44_0, C => madd_28, Y => - \RESMULT[5]\); - - \RESMULT_a14_b[0]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(0), Y => - \a14_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I201_Y_0 : XNOR3 - port map(A => madd_385, B => madd_421_0, C => N553_i, Y => - \RESMULT[16]\); - - RESMULT_madd_606_ADD_22x22_fast_I155_un1_Y_0 : AOI1B - port map(A => N417, B => I135_un1_Y, C => N402, Y => - ADD_22x22_fast_I155_un1_Y_0); - - \REG[8]\ : DFN1E1C0 - port map(D => \RESMULT[8]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(8)); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_0 : NOR3A - port map(A => I72_un1_Y, B => ADD_22x22_fast_I30_un1_Y, C - => N321, Y => ADD_22x22_fast_I172_Y_0); - - \RESMULT_a16_b[3]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(3), Y => - \a16_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I153_Y : AO1B - port map(A => ADD_22x22_fast_I153_un1_Y_0, B => N398, C => - ADD_22x22_fast_I153_Y_0, Y => N544); - - RESMULT_madd_606_ADD_22x22_fast_I191_Y_0 : XOR3 - port map(A => madd_66_0, B => madd_61_0, C => N378, Y => - \RESMULT[6]\); - - \RESMULT_a5_b[3]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(3), Y => - \a5_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I35_Y : NOR2B - port map(A => N316, B => N313, Y => N351); - - RESMULT_madd_274 : XA1B - port map(A => madd_230, B => madd_268_0_0, C => madd_235, Y - => madd_274); - - RESMULT_madd_606_ADD_22x22_fast_I56_Y : MAJ3 - port map(A => madd_120_0, B => madd_125_0, C => N279, Y => - N372); - - RESMULT_madd_279 : MIN3 - port map(A => \a13_b[0]\, B => \a11_b[2]\, C => \a12_b[1]\, - Y => N_122_i); - - RESMULT_madd_606_ADD_22x22_fast_I10_G0N : NOR2B - port map(A => madd_384_0, B => madd_348, Y => N303); - - \REG[21]\ : DFN1E1C0 - port map(D => \RESMULT[21]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(21)); - - RESMULT_madd_493_12 : XOR3 - port map(A => madd_493_8, B => madd_493_6, C => madd_452, Y - => madd_493_12); - - RESMULT_madd_321 : MIN3 - port map(A => \a11_b[3]\, B => \a9_b[5]\, C => \a10_b[4]\, - Y => madd_321); - - RESMULT_madd_342_7 : XOR3 - port map(A => \a7_b[7]\, B => \a8_b[6]\, C => \a_i6_b[8]\, - Y => madd_342_7); - - RESMULT_madd_432 : MAJ3 - port map(A => \a15_b[2]\, B => \a13_b[4]\, C => \a14_b[3]\, - Y => madd_432); - - RESMULT_madd_268_7 : XOR3 - port map(A => \a5_b[7]\, B => \a6_b[6]\, C => \a_i4_b[8]\, - Y => madd_268_7); - - \REG[16]\ : DFN1E1C0 - port map(D => \RESMULT[16]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(16)); - - RESMULT_madd_23 : MAJ3 - port map(A => \a1_b[3]\, B => madd_8, C => \a0_b[4]\, Y => - madd_23); - - \RESMULT_a14_b[4]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(4), Y => - \a14_b[4]\); - - RESMULT_madd_532 : MAJ3 - port map(A => \a16_b[4]\, B => \a15_b[5]\, C => - \a17_b_i[3]\, Y => madd_532); - - RESMULT_madd_24_2 : XNOR3 - port map(A => \a2_b[2]\, B => \a4_b[0]\, C => \a3_b[1]\, Y - => N_7_i); - - \RESMULT_a16_b[4]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(4), Y => - \a16_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I79_Y : NOR2B - port map(A => N357, B => N353, Y => N398); - - RESMULT_madd_606_ADD_22x22_fast_I17_P0N : OR2 - port map(A => madd_583_0, B => madd_572, Y => N325); - - RESMULT_madd_305_12 : XOR3 - port map(A => madd_305_10, B => N_114_i, C => madd_257, Y - => madd_305_12); - - RESMULT_madd_543_4 : XOR3 - port map(A => \a13_b[7]\, B => \a14_b[6]\, C => - \a_i12_b[8]\, Y => madd_543_4); - - \RESMULT_a14_b[3]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(3), Y => - \a14_b[3]\); - - RESMULT_madd_0_s_0 : XOR2 - port map(A => \a2_b[0]\, B => \a1_b[1]\, Y => madd_0_s_0); - - RESMULT_madd_606_ADD_22x22_fast_I157_Y : NOR2 - port map(A => N451, B => I157_un1_Y, Y => N556_i); - - \RESMULT_a_i6_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(6), Y => - \a_i6_b[8]\); - - \REG[4]\ : DFN1E1C0 - port map(D => \RESMULT[4]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(4)); - - \REG[13]\ : DFN1E1C0 - port map(D => \RESMULT[13]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(13)); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0 : AX1E - port map(A => ADD_22x22_fast_I170_Y_3, B => - ADD_22x22_fast_I170_Y_2, C => ADD_22x22_fast_I209_Y_0_2, - Y => \RESMULT[24]\); - - RESMULT_madd_336 : MAJ3 - port map(A => madd_342_2, B => madd_342_4, C => madd_342_7, - Y => madd_336); - - RESMULT_madd_215 : MIN3 - port map(A => \a5_b[6]\, B => \a4_b[7]\, C => \a_i3_b[8]\, - Y => madd_215); - - RESMULT_madd_305_4_0 : XOR2 - port map(A => \a10_b[3]\, B => \a8_b[5]\, Y => madd_305_4_0); - - RESMULT_madd_416_2 : XOR3 - port map(A => \a14_b[2]\, B => \a16_b[0]\, C => \a15_b[1]\, - Y => madd_416_2); - - RESMULT_madd_44_0 : XNOR2 - port map(A => madd_39_0, B => madd_23, Y => madd_44_0); - - \RESMULT_a16_b[2]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(2), Y => - \a16_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_Y_1 : AOI1B - port map(A => N399, B => N392, C => ADD_22x22_fast_I172_Y_0, - Y => ADD_22x22_fast_I172_Y_1); - - RESMULT_madd_341 : AO13 - port map(A => madd_294, B => N_130_i, C => madd_342_10, Y - => madd_341); - - \RESMULT_a17_b_i[5]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(5), Y => - \a17_b_i[5]\); - - RESMULT_madd_568_2 : XOR3 - port map(A => \a15_b[6]\, B => \a16_b[5]\, C => - \a17_b_i[4]\, Y => madd_568_2); - - \RESMULT_a7_b[6]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(6), Y => - \a7_b[6]\); - - RESMULT_madd_305_7 : XOR2 - port map(A => madd_305_7_0, B => \a_i5_b[8]\, Y => - madd_305_7); - - RESMULT_madd_606_ADD_22x22_fast_I0_P0N : OR2 - port map(A => CO3, B => madd_44_0, Y => N274); - - RESMULT_madd_606_ADD_22x22_fast_I2_G0N : NOR2B - port map(A => madd_93_0, B => madd_67, Y => N279); - - RESMULT_madd_606_ADD_22x22_fast_I89_Y : NOR3C - port map(A => N295, B => N298, C => N367, Y => N408); - - RESMULT_madd_493_6_0 : XOR2 - port map(A => \a11_b[7]\, B => \a_i10_b[8]\, Y => - madd_493_6_0); - - RESMULT_madd_384_0 : XNOR2 - port map(A => madd_379_0, B => madd_346, Y => madd_384_0); - - RESMULT_madd_294 : MAJ3 - port map(A => N_106_i, B => madd_247, C => madd_252, Y => - madd_294); - - RESMULT_madd_231_8 : XNOR3 - port map(A => madd_231_4, B => madd_231_2, C => madd_231_7, - Y => N_97_i); - - RESMULT_madd_268_2_0 : XOR2 - port map(A => \a12_b[0]\, B => \a10_b[2]\, Y => - madd_268_2_0); - - RESMULT_madd_299 : MIN3 - port map(A => madd_305_2, B => madd_305_4, C => madd_305_7, - Y => N_130_i); - - RESMULT_madd_578_0_0 : AX1 - port map(A => alu_sample(14), B => alu_coef_s(8), C => - madd_573_0, Y => madd_578_0_0); - - RESMULT_madd_368 : MAJ3 - port map(A => N_138_i, B => madd_321, C => madd_326, Y => - madd_368); - - \RESMULT_a11_b[1]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(1), Y => - \a11_b[1]\); - - \REG[7]\ : DFN1E1C0 - port map(D => \RESMULT[7]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(7)); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y : OR3C - port map(A => I110_un1_Y, B => ADD_22x22_fast_I171_Y_1, C - => ADD_22x22_fast_I171_Y_3, Y => N535); - - \RESMULT_a5_b[2]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(2), Y => - \a5_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I76_un1_Y : OA1A - port map(A => I38_un1_Y_i, B => N309, C => N351, Y => - I76_un1_Y); - - RESMULT_madd_405 : MIN3 - port map(A => N_154_i, B => madd_358, C => madd_363, Y => - madd_405); - - \RESMULT_a1_b[5]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(5), Y => - \a1_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I172_un1_Y : OR3C - port map(A => N454, B => N378, C => N438, Y => I172_un1_Y); - - \REG[23]\ : DFN1E1C0 - port map(D => \RESMULT[23]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(23)); - - RESMULT_madd_606_ADD_22x22_fast_I10_P0N : OR2 - port map(A => madd_384_0, B => madd_348, Y => N304); - - RESMULT_madd_210 : MIN3 - port map(A => \a8_b[3]\, B => \a6_b[5]\, C => \a7_b[4]\, Y - => madd_210); - - RESMULT_madd_114 : MAJ3 - port map(A => madd_72, B => madd_77, C => madd_95_0, Y => - madd_114); - - \RESMULT_a12_b[0]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(0), Y => - \a12_b[0]\); - - \RESMULT_a_i15_b[8]\ : OR2A - port map(A => alu_coef_s(8), B => alu_sample(15), Y => - \a_i15_b[8]\); - - \RESMULT_a7_b[5]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(5), Y => - \a7_b[5]\); - - RESMULT_madd_379_10 : XNOR3 - port map(A => madd_321, B => N_138_i, C => madd_326, Y => - madd_379_10); - - RESMULT_madd_39_4 : XOR2 - port map(A => madd_39_4_0, B => \a0_b[5]\, Y => N_15); - - \REG[0]\ : DFN1E1C0 - port map(D => \RESMULT[0]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(0)); - - RESMULT_madd_606_ADD_22x22_fast_I153_un1_Y_0 : NOR2A - port map(A => N568, B => N406, Y => - ADD_22x22_fast_I153_un1_Y_0); - - RESMULT_madd_458_9 : XOR3 - port map(A => madd_390, B => \a_i9_b[8]\, C => madd_395, Y - => madd_458_9); - - RESMULT_madd_606_ADD_22x22_fast_I101_Y : OR2 - port map(A => N376, B => I101_un1_Y, Y => N421); - - RESMULT_madd_157_11 : XOR3 - port map(A => N_57, B => N_59_i, C => N_48, Y => - madd_157_11); - - \REG[5]\ : DFN1E1C0 - port map(D => \RESMULT[5]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(5)); - - RESMULT_madd_606_ADD_22x22_fast_I125_Y : NOR2B - port map(A => N412, B => N404, Y => N450); - - RESMULT_madd_125_0 : AX1 - port map(A => madd_65, B => madd_88_0, C => madd_115_0, Y - => madd_125_0); - - \RESMULT_a8_b[1]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(1), Y => - \a8_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I96_Y : AO1 - port map(A => N374, B => N371, C => N370, Y => N415); - - RESMULT_madd_606_ADD_22x22_fast_I159_Y : AOI1 - port map(A => N456, B => madd_28, C => N455, Y => N562_i); - - RESMULT_madd_493_8 : XOR3 - port map(A => madd_432, B => madd_493_2, C => madd_437, Y - => madd_493_8); - - \RESMULT_a12_b[6]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(6), Y => - \a12_b[6]\); - - RESMULT_madd_348 : XA1B - port map(A => madd_304, B => madd_342_0_0, C => madd_309, Y - => madd_348); - - RESMULT_madd_606_ADD_22x22_fast_I132_Y : AO1 - port map(A => N419, B => N412, C => N411, Y => N565); - - RESMULT_madd_517 : MAJ3 - port map(A => madd_523_2, B => madd_477, C => madd_523_4, Y - => madd_517); - - RESMULT_madd_606_ADD_22x22_fast_I207_Y_0_0 : XOR2 - port map(A => madd_583_0, B => madd_572, Y => - ADD_22x22_fast_I207_Y_0_0); - - \RESMULT_a12_b[7]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(7), Y => - \a12_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_2 : AOI1B - port map(A => N455, B => N440, C => ADD_22x22_fast_I173_Y_1, - Y => ADD_22x22_fast_I173_Y_2); - - \RESMULT_a12_b[3]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(3), Y => - \a12_b[3]\); - - RESMULT_madd_88_2 : XOR3 - port map(A => \a5_b[2]\, B => \a7_b[0]\, C => \a6_b[1]\, Y - => madd_88_2); - - RESMULT_madd_523_7 : XOR3 - port map(A => madd_472, B => \a_i11_b[8]\, C => madd_467, Y - => madd_523_7); - - RESMULT_madd_422 : NOR2A - port map(A => madd_416_0, B => madd_383, Y => madd_422); - - RESMULT_madd_462 : MAJ3 - port map(A => madd_458_13, B => madd_420, C => madd_458_14, - Y => madd_462); - - \RESMULT_a4_b[5]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(5), Y => - \a4_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I42_un1_Y : NOR3C - port map(A => madd_311, B => madd_347_0, C => N304, Y => - I42_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I110_un1_Y : AO1C - port map(A => N352, B => I78_un1_Y_i, C => N390, Y => - I110_un1_Y); - - RESMULT_madd_157_0 : XOR3 - port map(A => madd_157_12, B => madd_157_11, C => madd_119, - Y => madd_157_0); - - RESMULT_madd_606_ADD_22x22_fast_I78_Y : NOR2A - port map(A => I78_un1_Y_i, B => N352, Y => N397_i); - - RESMULT_madd_606_ADD_22x22_fast_I75_Y : NOR2A - port map(A => N353, B => N349, Y => N394); - - RESMULT_madd_522 : MAJ3 - port map(A => madd_482, B => madd_487, C => madd_523_7, Y - => madd_522); - - RESMULT_madd_305_8 : XNOR2 - port map(A => madd_305_8_0, B => madd_305_7, Y => N_129_i); - - RESMULT_madd_562 : MAJ3 - port map(A => \a14_b[7]\, B => madd_532, C => \a_i13_b[8]\, - Y => madd_562); - - \REG[14]\ : DFN1E1C0 - port map(D => \RESMULT[14]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(14)); - - \RESMULT_a2_b[6]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(6), Y => - \a2_b[6]\); - - \RESMULT_a12_b[2]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(2), Y => - \a12_b[2]\); - - RESMULT_madd_157_7 : XOR2 - port map(A => madd_157_7_0, B => \a_i1_b[8]\, Y => - madd_157_7); - - RESMULT_madd_606_ADD_22x22_fast_I11_P0N : OR2 - port map(A => madd_421_0, B => madd_385, Y => N307); - - RESMULT_madd_1_605_SUM3_0 : XOR2 - port map(A => CO2, B => madd_24_0, Y => \RESMULT[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I157_un1_Y : NOR2B - port map(A => N452, B => N421, Y => I157_un1_Y); - - RESMULT_madd_178 : MIN3 - port map(A => \a4_b[6]\, B => \a3_b[7]\, C => \a_i2_b[8]\, - Y => madd_178); - - RESMULT_madd_326 : MIN3 - port map(A => \a8_b[6]\, B => \a7_b[7]\, C => \a_i6_b[8]\, - Y => madd_326); - - RESMULT_madd_482 : MAJ3 - port map(A => madd_432, B => madd_437, C => madd_493_2, Y - => madd_482); - - RESMULT_madd_342_0_0 : XOR2 - port map(A => N_145_i, B => madd_342_12, Y => madd_342_0_0); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_3_tz : AO1 - port map(A => N452, B => N421, C => N451, Y => - ADD_22x22_fast_I171_Y_3_tz); - - RESMULT_madd_606_ADD_22x22_fast_I32_Y : AO13 - port map(A => N315, B => madd_548_0, C => madd_527, Y => - N348); - - RESMULT_madd_28 : AO18 - port map(A => madd_13, B => madd_24_4, C => N_7_i, Y => - madd_28); - - RESMULT_madd_582 : OR2 - port map(A => madd_582_0, B => madd_334, Y => madd_582); - - RESMULT_madd_543_2 : XOR2 - port map(A => madd_543_2_0, B => \a17_b_i[3]\, Y => - madd_543_2); - - RESMULT_madd_194_8 : XNOR3 - port map(A => madd_194_4, B => madd_194_2, C => madd_194_7, - Y => N_81_i); - - \RESMULT_a17_b_i[1]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(1), Y => - \a17_b_i[1]\); - - \RESMULT_a0_b[4]\ : OR2B - port map(A => alu_sample(0), B => alu_coef_s(4), Y => - \a0_b[4]\); - - \RESMULT_a13_b[3]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(3), Y => - \a13_b[3]\); - - RESMULT_madd_442 : MAJ3 - port map(A => \a_i9_b[8]\, B => madd_390, C => madd_395, Y - => madd_442); - - RESMULT_madd_606_ADD_22x22_fast_I90_un1_Y : NOR2B - port map(A => N368, B => N365, Y => - ADD_22x22_fast_I90_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I88_Y : OR2 - port map(A => N362, B => I88_un1_Y, Y => N407); - - RESMULT_madd_606_ADD_22x22_fast_I85_Y : NOR3C - port map(A => N295, B => N298, C => N359, Y => N404); - - RESMULT_madd_542 : MAJ3 - port map(A => madd_507, B => madd_502, C => madd_543_2, Y - => madd_542); - - RESMULT_madd_606_ADD_22x22_fast_I57_Y : OA1 - port map(A => madd_120_0, B => madd_125_0, C => N280, Y => - N373); - - \RESMULT_a4_b[6]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(6), Y => - \a4_b[6]\); - - \RESMULT_a0_b[2]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(2), Y => - \a0_b[2]\); - - RESMULT_madd_157_12 : XOR3 - port map(A => madd_157_9, B => madd_157_7, C => madd_114, Y - => madd_157_12); - - \REG[24]\ : DFN1E1C0 - port map(D => \RESMULT[24]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(24)); - - RESMULT_madd_606_ADD_22x22_fast_I8_G0N : NOR2B - port map(A => madd_310_0, B => madd_274, Y => N297); - - RESMULT_madd_606_ADD_22x22_fast_I127_Y : NOR3B - port map(A => N369, B => N373, C => N406, Y => N452); - - RESMULT_madd_199_0 : XNOR3 - port map(A => madd_156, B => madd_194_0_0, C => madd_161, Y - => madd_199_0); - - RESMULT_madd_50 : MAJ3 - port map(A => \a6_b[0]\, B => \a4_b[2]\, C => \a5_b[1]\, Y - => madd_50); - - RESMULT_madd_8 : MAJ3 - port map(A => \a3_b[0]\, B => \a1_b[2]\, C => \a2_b[1]\, Y - => madd_8); - - RESMULT_madd_346 : AO13 - port map(A => madd_304, B => N_145_i, C => madd_342_12, Y - => madd_346); - - RESMULT_madd_606_ADD_22x22_fast_I72_un1_Y : OR3C - port map(A => N319, B => N322, C => N350, Y => I72_un1_Y); - - RESMULT_madd_262 : MIN3 - port map(A => madd_268_2, B => madd_268_4, C => madd_268_7, - Y => N_114_i); - - RESMULT_madd_231_7 : XOR3 - port map(A => \a4_b[7]\, B => \a5_b[6]\, C => \a_i3_b[8]\, - Y => madd_231_7); - - RESMULT_madd_311 : XA1B - port map(A => madd_267, B => madd_305_0_0, C => madd_272, Y - => madd_311); - - \RESMULT_a3_b[7]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(7), Y => - \a3_b[7]\); - - \RESMULT_a8_b[3]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(3), Y => - \a8_b[3]\); - - RESMULT_madd_173 : MIN3 - port map(A => \a7_b[3]\, B => \a5_b[5]\, C => \a6_b[4]\, Y - => madd_173); - - \RESMULT_a14_b[6]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(6), Y => - \a14_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I4_P0N : XO1A - port map(A => madd_124, B => madd_157_0, C => madd_126, Y - => N286); - - RESMULT_madd_157_7_0 : XOR2 - port map(A => \a3_b[6]\, B => \a2_b[7]\, Y => madd_157_7_0); - - RESMULT_madd_1_605_SUM2_0 : XOR2 - port map(A => CO1, B => madd_9_0, Y => \RESMULT[3]\); - - RESMULT_madd_194_10 : XOR2 - port map(A => madd_194_10_0, B => madd_141, Y => - madd_194_10); - - \RESMULT_a13_b[1]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(1), Y => - \a13_b[1]\); - - \RESMULT_a9_b[2]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(2), Y => - \a9_b[2]\); - - RESMULT_madd_198 : AO13 - port map(A => madd_156, B => N_81_i, C => madd_194_12, Y - => madd_198); - - RESMULT_madd_156 : MIN3 - port map(A => madd_157_7, B => madd_114, C => madd_157_9, Y - => madd_156); - - \RESMULT_a3_b[1]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(1), Y => - \a3_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I88_un1_Y : NOR3C - port map(A => N295, B => N298, C => N366, Y => I88_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_1 : OA1A - port map(A => N348, B => N345, C => ADD_22x22_fast_I171_Y_0, - Y => ADD_22x22_fast_I171_Y_1); - - RESMULT_madd_268_10 : XNOR3 - port map(A => madd_210, B => N_90_i, C => madd_215, Y => - madd_268_10); - - RESMULT_madd_342_4 : XOR2 - port map(A => madd_342_4_0, B => \a10_b[4]\, Y => - madd_342_4); - - RESMULT_madd_606_ADD_22x22_fast_I7_P0N : OR2 - port map(A => madd_273_0, B => madd_237, Y => N295); - - RESMULT_madd_151 : AO18 - port map(A => N_48, B => N_57, C => N_59_i, Y => madd_151); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0_0 : AX1A - port map(A => alu_sample(16), B => alu_coef_s(8), C => - \a17_b_i[7]\, Y => ADD_22x22_fast_I209_Y_0_0); - - \RESMULT_a12_b[5]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(5), Y => - \a12_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I206_Y_0 : AX1E - port map(A => I173_un1_Y, B => ADD_22x22_fast_I173_Y_2, C - => ADD_22x22_fast_I206_Y_0_0, Y => \RESMULT[21]\); - - \RESMULT_a17_b_i[4]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(4), Y => - \a17_b_i[4]\); - - RESMULT_madd_99 : MAJ3 - port map(A => \a8_b[0]\, B => \a6_b[2]\, C => \a7_b[1]\, Y - => madd_99); - - \RESMULT_a16_b[6]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(6), Y => - \a16_b[6]\); - - RESMULT_madd_582_0_tz : OR2 - port map(A => madd_573_0, B => madd_557, Y => madd_582_0_tz); - - RESMULT_madd_242 : MIN3 - port map(A => \a12_b[0]\, B => \a10_b[2]\, C => \a11_b[1]\, - Y => N_106_i); - - \RESMULT_a1_b[3]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(3), Y => - \a1_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_3_0 : NOR2B - port map(A => N388, B => N396, Y => - ADD_22x22_fast_I170_Y_3_0); - - RESMULT_madd_606_ADD_22x22_fast_I13_G0N : NOR2B - port map(A => madd_493_0, B => madd_462, Y => N312); - - RESMULT_madd_568_6 : XOR3 - port map(A => madd_537, B => madd_568_2, C => madd_542, Y - => madd_568_6); - - \RESMULT_a10_b[5]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(5), Y => - \a10_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I205_Y_0 : XOR3 - port map(A => madd_527, B => madd_548_0, C => N541, Y => - \RESMULT[20]\); - - RESMULT_madd_606_ADD_22x22_fast_I154_Y : NOR3 - port map(A => I120_un1_Y, B => N399, C => I154_un1_Y, Y => - N547); - - RESMULT_madd_606_ADD_22x22_fast_I38_un1_Y : OR3C - port map(A => madd_385, B => madd_421_0, C => N310, Y => - I38_un1_Y_i); - - RESMULT_madd_3 : MAJ3 - port map(A => \a2_b[0]\, B => \a0_b[2]\, C => \a1_b[1]\, Y - => madd_3); - - RESMULT_madd_379_4 : XOR3 - port map(A => \a10_b[5]\, B => \a12_b[3]\, C => \a11_b[4]\, - Y => madd_379_4); - - RESMULT_madd_257 : MAJ3 - port map(A => N_90_i, B => madd_210, C => madd_215, Y => - madd_257); - - RESMULT_madd_231_4 : XOR3 - port map(A => \a6_b[5]\, B => \a8_b[3]\, C => \a7_b[4]\, Y - => madd_231_4); - - RESMULT_madd_115_2 : XNOR3 - port map(A => \a3_b[5]\, B => \a5_b[3]\, C => \a4_b[4]\, Y - => N_45_i); - - RESMULT_madd_606_ADD_22x22_fast_I14_P0N : OR2A - port map(A => madd_497, B => madd_523_0, Y => N316); - - RESMULT_madd_606_ADD_22x22_fast_I200_Y_0 : XNOR3 - port map(A => madd_348, B => madd_384_0, C => N556_i, Y => - \RESMULT[15]\); - - \RESMULT_a2_b[1]\ : OR2B - port map(A => alu_sample(2), B => alu_coef_s(1), Y => - \a2_b[1]\); - - RESMULT_madd_88_7 : XOR3 - port map(A => \a0_b[7]\, B => \a1_b[6]\, C => madd_50, Y - => madd_88_7); - - RESMULT_madd_606_ADD_22x22_fast_I29_Y : OR2B - port map(A => N325, B => N322, Y => N345); - - RESMULT_madd_606_ADD_22x22_fast_I43_Y : NOR2B - port map(A => N304, B => N301, Y => N359); - - RESMULT_madd_606_ADD_22x22_fast_I129_Y : NOR2B - port map(A => N416, B => N408, Y => N454); - - RESMULT_madd_581 : NOR2B - port map(A => madd_573_0, B => madd_557, Y => madd_334); - - RESMULT_madd_606_ADD_22x22_fast_I173_un1_Y : OR3C - port map(A => N456, B => madd_28, C => N440, Y => - I173_un1_Y); - - RESMULT_madd_523_4 : XOR3 - port map(A => \a12_b[7]\, B => \a14_b[5]\, C => \a13_b[6]\, - Y => madd_523_4); - - RESMULT_madd_56_0 : XOR3 - port map(A => madd_33, B => \a0_b[6]\, C => madd_38, Y => - madd_56_0); - - RESMULT_madd_606_ADD_22x22_fast_I13_P0N : OR2 - port map(A => madd_493_0, B => madd_462, Y => N313); - - RESMULT_madd_193 : MIN3 - port map(A => madd_146, B => madd_151, C => madd_194_10, Y - => madd_193); - - RESMULT_madd_87 : MIN3 - port map(A => madd_88_2, B => madd_55, C => madd_88_4, Y - => N_38_i); - - \RESMULT_a8_b[5]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(5), Y => - \a8_b[5]\); - - RESMULT_madd_606_ADD_22x22_fast_I36_Y : MAJ3 - port map(A => madd_462, B => madd_493_0, C => N309, Y => - N352); - - RESMULT_madd_606_ADD_22x22_fast_I14_G0N : NOR2A - port map(A => madd_523_0, B => madd_497, Y => N315); - - RESMULT_madd_606_ADD_22x22_fast_I193_Y_0 : XOR3 - port map(A => madd_125_0, B => madd_120_0, C => N419, Y => - \RESMULT[8]\); - - RESMULT_madd_1_605_CO2 : NOR2B - port map(A => CO1, B => madd_9_0, Y => CO2); - - RESMULT_madd_606_ADD_22x22_fast_I97_Y : NOR2B - port map(A => N375, B => N371, Y => N416); - - \RESMULT_a_i3_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(3), Y => - \a_i3_b[8]\); - - RESMULT_madd_115_4 : XOR3 - port map(A => \a1_b[7]\, B => \a2_b[6]\, C => \a0_b[8]\, Y - => N_47); - - \RESMULT_a16_b[5]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(5), Y => - \a16_b[5]\); - - \RESMULT_a6_b[3]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(3), Y => - \a6_b[3]\); - - \RESMULT_a11_b[2]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(2), Y => - \a11_b[2]\); - - RESMULT_madd_493_2 : XOR3 - port map(A => \a15_b[3]\, B => \a16_b[2]\, C => - \a17_b_i[1]\, Y => madd_493_2); - - RESMULT_madd_606_ADD_22x22_fast_I130_un1_Y : OR3B - port map(A => N365, B => N369, C => N417, Y => I130_un1_Y); - - RESMULT_madd_268_0_0 : XOR2 - port map(A => N_113_i, B => madd_268_12, Y => madd_268_0_0); - - \RESMULT_a3_b[5]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(5), Y => - \a3_b[5]\); - - \RESMULT_a2_b[5]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(5), Y => - \a2_b[5]\); - - \RESMULT_a16_b[0]\ : NOR2B - port map(A => alu_sample(16), B => alu_coef_s(0), Y => - \a16_b[0]\); - - RESMULT_madd_194_2 : XOR3 - port map(A => \a8_b[2]\, B => \a10_b[0]\, C => \a9_b[1]\, Y - => madd_194_2); - - RESMULT_madd_305_10 : XNOR3 - port map(A => madd_247, B => N_106_i, C => madd_252, Y => - madd_305_10); - - RESMULT_madd_9_0 : XOR3 - port map(A => madd_4_0, B => \a0_b[3]\, C => madd_3, Y => - madd_9_0); - - \REG[2]\ : DFN1E1C0 - port map(D => \RESMULT[2]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(2)); - - \REG[17]\ : DFN1E1C0 - port map(D => \RESMULT[17]\, CLK => lclk_c, CLR => rstn, E - => mult_0, Q => MULTout(17)); - - RESMULT_madd_606_ADD_22x22_fast_I53_Y : NOR2B - port map(A => N289, B => N286, Y => N369); - - RESMULT_madd_268_4 : XOR2 - port map(A => madd_268_4_0, B => \a8_b[4]\, Y => madd_268_4); - - RESMULT_madd_512 : MAJ3 - port map(A => \a_i11_b[8]\, B => madd_467, C => madd_472, Y - => madd_512); - - RESMULT_madd_606_ADD_22x22_fast_I40_Y : MAJ3 - port map(A => madd_385, B => madd_421_0, C => N303, Y => - N356); - - RESMULT_madd_606_ADD_22x22_fast_I202_Y_0 : XOR3 - port map(A => madd_458_0, B => madd_422, C => N550, Y => - \RESMULT[17]\); - - RESMULT_madd_606_ADD_22x22_fast_I82_Y : AO1 - port map(A => N360, B => N357, C => N356, Y => N401); - - RESMULT_madd_115_0 : XOR3 - port map(A => N_47, B => N_45_i, C => madd_82, Y => - madd_115_0); - - RESMULT_madd_493_4 : XOR3 - port map(A => \a12_b[6]\, B => \a14_b[4]\, C => \a13_b[5]\, - Y => madd_493_4); - - RESMULT_madd_606_ADD_22x22_fast_I48_un1_Y : OR3C - port map(A => madd_200, B => madd_236_0, C => N295, Y => - I48_un1_Y_i); - - RESMULT_madd_416_7 : XOR3 - port map(A => \a9_b[7]\, B => \a10_b[6]\, C => \a_i8_b[8]\, - Y => madd_416_7); - - RESMULT_madd_458_4 : XOR3 - port map(A => \a13_b[4]\, B => \a15_b[2]\, C => \a14_b[3]\, - Y => madd_458_4); - - \RESMULT_a9_b[6]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(6), Y => - \a9_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I1_P0N : OR2 - port map(A => madd_66_0, B => madd_61_0, Y => N277); - - \RESMULT_a14_b[2]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(2), Y => - \a14_b[2]\); - - RESMULT_madd_523_10 : XOR3 - port map(A => madd_482, B => madd_523_7, C => madd_487, Y - => madd_523_10); - - RESMULT_madd_316 : MIN3 - port map(A => \a14_b[0]\, B => \a12_b[2]\, C => \a13_b[1]\, - Y => N_138_i); - - RESMULT_madd_606_ADD_22x22_fast_I156_Y : AOI1 - port map(A => N450, B => N419, C => N449, Y => N553_i); - - \RESMULT_a14_b[1]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(1), Y => - \a14_b[1]\); - - \RESMULT_a15_b[6]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(6), Y => - \a15_b[6]\); - - RESMULT_madd_342_8 : XNOR3 - port map(A => madd_342_4, B => madd_342_2, C => madd_342_7, - Y => N_145_i); - - \RESMULT_a13_b[4]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(4), Y => - \a13_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I4_G0N : XA1A - port map(A => madd_124, B => madd_157_0, C => madd_126, Y - => N285); - - RESMULT_madd_606_ADD_22x22_fast_I16_P0N : OR2A - port map(A => madd_552, B => madd_568_0, Y => N322); - - \RESMULT_a_i2_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(2), Y => - \a_i2_b[8]\); - - RESMULT_madd_39_2 : XOR2 - port map(A => madd_39_2_0, B => \a4_b[1]\, Y => madd_39_2); - - \RESMULT_a6_b[2]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(2), Y => - \a6_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I41_Y : NOR2B - port map(A => N307, B => N304, Y => N357); - - RESMULT_madd_606_ADD_22x22_fast_I50_Y : MAJ3 - port map(A => madd_200, B => madd_236_0, C => N288, Y => - N366); - - RESMULT_madd_284 : MIN3 - port map(A => \a10_b[3]\, B => \a8_b[5]\, C => \a9_b[4]\, Y - => madd_284); - - RESMULT_madd_289 : MIN3 - port map(A => \a7_b[6]\, B => \a6_b[7]\, C => \a_i5_b[8]\, - Y => madd_289); - - RESMULT_madd_606_ADD_22x22_fast_I209_Y_0_2 : XOR3 - port map(A => N_252, B => ADD_22x22_fast_I209_Y_0_0, C => - N_254, Y => ADD_22x22_fast_I209_Y_0_2); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_0 : AO18 - port map(A => N324, B => madd_587, C => N_253, Y => - ADD_22x22_fast_I170_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I115_Y : NOR2B - port map(A => N402, B => N394, Y => N440); - - \RESMULT_a3_b[0]\ : OR2B - port map(A => alu_sample(3), B => alu_coef_s(0), Y => - \a3_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_2 : NOR3C - port map(A => I68_un1_Y, B => ADD_22x22_fast_I170_Y_0, C - => I108_un1_Y, Y => ADD_22x22_fast_I170_Y_2); - - \RESMULT_a7_b[1]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(1), Y => - \a7_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I171_Y_0 : MIN3 - port map(A => madd_572, B => madd_583_0, C => N321, Y => - ADD_22x22_fast_I171_Y_0); - - RESMULT_madd_606_ADD_22x22_fast_I78_un1_Y : OR2B - port map(A => N356, B => N353, Y => I78_un1_Y_i); - - RESMULT_madd_606_ADD_22x22_fast_I124_Y : AO1 - port map(A => N411, B => N404, C => N403, Y => N449); - - \RESMULT_a0_b[6]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(6), Y => - \a0_b[6]\); - - RESMULT_madd_523_2 : XOR3 - port map(A => \a15_b[4]\, B => \a16_b[3]\, C => - \a17_b_i[2]\, Y => madd_523_2); - - RESMULT_madd_77 : MAJ3 - port map(A => \a4_b[3]\, B => \a2_b[5]\, C => \a3_b[4]\, Y - => madd_77); - - RESMULT_madd_606_ADD_22x22_fast_I2_P0N : OR2 - port map(A => madd_93_0, B => madd_67, Y => N280); - - RESMULT_madd_157_2 : XOR3 - port map(A => \a7_b[2]\, B => \a9_b[0]\, C => \a8_b[1]\, Y - => N_57); - - RESMULT_madd_606_ADD_22x22_fast_I120_un1_Y : NOR2B - port map(A => N407, B => N400, Y => I120_un1_Y); - - \RESMULT_a2_b[0]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(0), Y => - \a2_b[0]\); - - RESMULT_madd_379_7 : XOR3 - port map(A => \a8_b[7]\, B => \a9_b[6]\, C => \a_i7_b[8]\, - Y => madd_379_7); - - \RESMULT_a8_b[4]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(4), Y => - \a8_b[4]\); - - \RESMULT_a2_b[3]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(3), Y => - \a2_b[3]\); - - \RESMULT_a17_b_i[6]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(6), Y => - \a17_b_i[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I173_Y_1 : AOI1B - port map(A => N401, B => N394, C => ADD_22x22_fast_I173_Y_0, - Y => ADD_22x22_fast_I173_Y_1); - - \RESMULT_a12_b[1]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(1), Y => - \a12_b[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I76_Y : OR2 - port map(A => N350, B => I76_un1_Y, Y => N395); - - RESMULT_madd_309 : AO13 - port map(A => madd_267, B => N_129_i, C => madd_305_12, Y - => madd_309); - - RESMULT_madd_1_605_SUM0_0 : AX1C - port map(A => alu_coef_s(1), B => alu_sample(0), C => - \a1_b[0]\, Y => \RESMULT[1]\); - - RESMULT_madd_606_ADD_22x22_fast_I60_Y : MAJ3 - port map(A => madd_61_0, B => madd_66_0, C => N273, Y => - N376); - - RESMULT_madd_606_ADD_22x22_fast_I154_un1_Y : NOR3C - port map(A => N400, B => N408, C => N461, Y => I154_un1_Y); - - \RESMULT_a2_b[2]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(2), Y => - \a2_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I1_G0N : NOR2B - port map(A => madd_66_0, B => madd_61_0, Y => N276); - - RESMULT_madd_606_ADD_22x22_fast_I113_Y : NOR2B - port map(A => N400, B => N392, Y => N438); - - RESMULT_madd_415 : MIN3 - port map(A => N_175_i, B => madd_368, C => madd_373, Y => - madd_415); - - RESMULT_madd_606_ADD_22x22_fast_I93_Y : NOR2B - port map(A => N371, B => N367, Y => N412); - - RESMULT_madd_606_ADD_22x22_fast_I51_Y : NOR2B - port map(A => N292, B => N289, Y => N367); - - RESMULT_madd_543_0 : XOR3 - port map(A => madd_543_6, B => madd_543_4, C => madd_512, Y - => madd_543_0); - - \RESMULT_a3_b[2]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(2), Y => - \a3_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I118_un1_Y : NAND2 - port map(A => N398, B => N405, Y => I118_un1_Y); - - RESMULT_madd_493_11 : XOR3 - port map(A => madd_442, B => madd_493_4, C => madd_447, Y - => madd_493_11); - - RESMULT_madd_342_4_0 : XOR2 - port map(A => \a11_b[3]\, B => \a9_b[5]\, Y => madd_342_4_0); - - RESMULT_madd_606_ADD_22x22_fast_I44_Y : MAJ3 - port map(A => madd_311, B => madd_347_0, C => N297, Y => - N360); - - \RESMULT_a9_b[3]\ : NOR2B - port map(A => alu_sample(9), B => alu_coef_s(3), Y => - \a9_b[3]\); - - RESMULT_madd_416_0 : XOR2 - port map(A => madd_416_0_0, B => madd_378, Y => madd_416_0); - - RESMULT_madd_548_0 : XOR3 - port map(A => madd_543_0, B => madd_517, C => madd_522, Y - => madd_548_0); - - RESMULT_madd_606_ADD_22x22_fast_I196_Y_0_0 : XOR2 - port map(A => madd_200, B => madd_236_0, Y => - ADD_22x22_fast_I196_Y_0_0); - - \RESMULT_a4_b[4]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(4), Y => - \a4_b[4]\); - - \RESMULT_a15_b[7]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(7), Y => - \a15_b[7]\); - - RESMULT_madd_353 : MIN3 - port map(A => \a15_b[0]\, B => \a13_b[2]\, C => \a14_b[1]\, - Y => N_154_i); - - \RESMULT_a_i10_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(10), Y => - \a_i10_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I86_Y : AO1 - port map(A => N364, B => N361, C => N360, Y => N405); - - RESMULT_madd_268_12 : XOR3 - port map(A => madd_268_10, B => N_98_i, C => madd_220, Y - => madd_268_12); - - RESMULT_madd_1_605_CO1 : XA1 - port map(A => \a0_b[2]\, B => madd_0_s_0, C => CO0, Y => - CO1); - - RESMULT_madd_4_0 : XNOR3 - port map(A => \a1_b[2]\, B => \a3_b[0]\, C => \a2_b[1]\, Y - => madd_4_0); - - \RESMULT_a17_b_i[2]\ : NOR2A - port map(A => alu_sample(17), B => alu_coef_s(2), Y => - \a17_b_i[2]\); - - RESMULT_madd_379_12 : XOR3 - port map(A => madd_379_10, B => madd_336, C => madd_331, Y - => madd_379_12); - - RESMULT_madd_1_605_CO3 : NOR2B - port map(A => CO2, B => madd_24_0, Y => CO3); - - RESMULT_madd_606_ADD_22x22_fast_I158_un1_Y : NOR2B - port map(A => N454, B => N378, Y => - ADD_22x22_fast_I158_un1_Y); - - RESMULT_madd_194_0_0 : XOR2 - port map(A => N_81_i, B => madd_194_12, Y => madd_194_0_0); - - GND_i_0 : GND - port map(Y => GND_0); - - RESMULT_madd_606_ADD_22x22_fast_I37_Y : NOR2B - port map(A => N313, B => N310, Y => N353); - - RESMULT_madd_557 : MAJ3 - port map(A => \a16_b[5]\, B => \a15_b[6]\, C => - \a17_b_i[4]\, Y => madd_557); - - RESMULT_madd_458_13 : XOR3 - port map(A => madd_405, B => madd_458_7, C => madd_410, Y - => madd_458_13); - - RESMULT_madd_606_ADD_22x22_fast_I101_un1_Y : NOR2B - port map(A => N377, B => madd_28, Y => I101_un1_Y); - - \RESMULT_a1_b[0]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(0), Y => - \a1_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I152_un1_Y : NOR3C - port map(A => N565, B => N404, C => N396, Y => I152_un1_Y); - - RESMULT_madd_606_ADD_22x22_fast_I17_G0N : NOR2B - port map(A => madd_583_0, B => madd_572, Y => N324); - - RESMULT_madd_606_ADD_22x22_fast_I61_Y : NOR2B - port map(A => N277, B => N274, Y => N377); - - RESMULT_madd_457 : MAJ3 - port map(A => madd_458_9, B => madd_415, C => madd_458_10, - Y => madd_457); - - RESMULT_madd_88_0 : XOR3 - port map(A => madd_88_8, B => madd_88_7, C => madd_60, Y - => madd_88_0); - - RESMULT_madd_606_ADD_22x22_fast_I130_Y : OR3A - port map(A => I130_un1_Y, B => ADD_22x22_fast_I90_un1_Y, C - => N364, Y => N455); - - \RESMULT_a4_b[1]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(1), Y => - \a4_b[1]\); - - \RESMULT_a13_b[6]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(6), Y => - \a13_b[6]\); - - RESMULT_madd_606_ADD_22x22_fast_I54_Y : OR2A - port map(A => I54_un1_Y_i, B => N285, Y => N370); - - \RESMULT_a2_b[7]\ : NOR2B - port map(A => alu_sample(2), B => alu_coef_s(7), Y => - \a2_b[7]\); - - RESMULT_madd_168 : MIN3 - port map(A => \a10_b[0]\, B => \a8_b[2]\, C => \a9_b[1]\, Y - => N_74_i); - - RESMULT_madd_606_ADD_22x22_fast_I152_Y : NOR2 - port map(A => ADD_22x22_fast_I152_Y_0, B => I152_un1_Y, Y - => N541); - - RESMULT_madd_606_ADD_22x22_fast_I196_Y_0 : XOR2 - port map(A => ADD_22x22_fast_I196_Y_0_0, B => N568, Y => - \RESMULT[11]\); - - RESMULT_madd_109 : MIN3 - port map(A => \a2_b[6]\, B => \a0_b[8]\, C => \a1_b[7]\, Y - => N_48); - - \RESMULT_a11_b[7]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(7), Y => - \a11_b[7]\); - - \RESMULT_a10_b[2]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(2), Y => - \a10_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I126_Y : OR2 - port map(A => N405, B => I126_un1_Y, Y => N451); - - \RESMULT_a17_b_i[7]\ : OR2A - port map(A => alu_sample(17), B => alu_coef_s(7), Y => - \a17_b_i[7]\); - - RESMULT_madd_1_605_CO0 : NOR3C - port map(A => alu_coef_s(1), B => alu_sample(0), C => - \a1_b[0]\, Y => CO0); - - RESMULT_madd_573_0 : XOR3 - port map(A => \a16_b[6]\, B => \a15_b[7]\, C => - \a17_b_i[5]\, Y => madd_573_0); - - \RESMULT_a7_b[2]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(2), Y => - \a7_b[2]\); - - \RESMULT_a6_b[4]\ : NOR2B - port map(A => alu_sample(6), B => alu_coef_s(4), Y => - \a6_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I153_Y_0 : AND2 - port map(A => I118_un1_Y, B => N397_i, Y => - ADD_22x22_fast_I153_Y_0); - - RESMULT_madd_92 : MIN3 - port map(A => madd_88_7, B => madd_60, C => madd_88_8, Y - => madd_92); - - RESMULT_madd_416_0_0 : XOR2 - port map(A => madd_416_8, B => N_179, Y => madd_416_0_0); - - RESMULT_madd_400 : MAJ3 - port map(A => \a10_b[6]\, B => \a9_b[7]\, C => \a_i8_b[8]\, - Y => madd_400); - - RESMULT_madd_390 : MAJ3 - port map(A => \a16_b[0]\, B => \a14_b[2]\, C => \a15_b[1]\, - Y => madd_390); - - \RESMULT_a_i7_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(7), Y => - \a_i7_b[8]\); - - RESMULT_madd_606_ADD_22x22_fast_I49_Y : NOR2B - port map(A => N295, B => N292, Y => N365); - - RESMULT_madd_606_ADD_22x22_fast_I12_G0N : NOR2B - port map(A => madd_458_0, B => madd_422, Y => N309); - - RESMULT_madd_568_0 : XOR3 - port map(A => madd_568_6, B => madd_568_4, C => madd_547, Y - => madd_568_0); - - RESMULT_madd_427_1 : AOI1B - port map(A => alu_coef_s(0), B => \a16_b[1]\, C => - alu_sample(17), Y => madd_427_1); - - RESMULT_madd_188 : MIN3 - port map(A => madd_194_2, B => madd_194_4, C => madd_194_7, - Y => N_82_i); - - \RESMULT_a8_b[7]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(7), Y => - \a8_b[7]\); - - RESMULT_madd_606_ADD_22x22_fast_I15_P0N : OR2A - port map(A => madd_527, B => madd_548_0, Y => N319); - - RESMULT_madd_543_6 : XOR3 - port map(A => madd_507, B => madd_543_2, C => madd_502, Y - => madd_543_6); - - RESMULT_madd_136 : MAJ3 - port map(A => \a6_b[3]\, B => \a4_b[5]\, C => \a5_b[4]\, Y - => madd_136); - - \RESMULT_a3_b[4]\ : NOR2B - port map(A => alu_sample(3), B => alu_coef_s(4), Y => - \a3_b[4]\); - - RESMULT_madd_373 : MIN3 - port map(A => madd_379_2, B => madd_379_4, C => madd_379_7, - Y => madd_373); - - RESMULT_madd_578_0 : XOR2 - port map(A => madd_578_0_0, B => madd_557, Y => madd_578_0); - - \RESMULT_a5_b[5]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(5), Y => - \a5_b[5]\); - - \RESMULT_a15_b[5]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(5), Y => - \a15_b[5]\); - - RESMULT_madd_231_2 : XOR3 - port map(A => \a9_b[2]\, B => \a11_b[0]\, C => \a10_b[1]\, - Y => madd_231_2); - - \RESMULT_a5_b[0]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(0), Y => - \a5_b[0]\); - - RESMULT_madd_131 : MAJ3 - port map(A => \a9_b[0]\, B => \a7_b[2]\, C => \a8_b[1]\, Y - => madd_131); - - RESMULT_madd_606_ADD_22x22_fast_I128_Y : AO1 - port map(A => N415, B => N408, C => N407, Y => N453); - - RESMULT_madd_577 : MAJ3 - port map(A => \a15_b[7]\, B => \a16_b[6]\, C => - \a17_b_i[5]\, Y => madd_577); - - RESMULT_madd_342_2_0 : XOR2 - port map(A => \a14_b[0]\, B => \a12_b[2]\, Y => - madd_342_2_0); - - RESMULT_madd_305_4 : XOR2 - port map(A => madd_305_4_0, B => \a9_b[4]\, Y => madd_305_4); - - RESMULT_madd_61_4 : XOR3 - port map(A => \a1_b[5]\, B => \a3_b[3]\, C => \a2_b[4]\, Y - => madd_61_4); - - RESMULT_madd_477 : MAJ3 - port map(A => \a11_b[7]\, B => madd_427_1, C => - \a_i10_b[8]\, Y => madd_477); - - RESMULT_madd_416_12 : XNOR3 - port map(A => madd_368, B => N_175_i, C => madd_373, Y => - N_179); - - RESMULT_madd_606_ADD_22x22_fast_I192_Y_0 : XOR3 - port map(A => madd_93_0, B => madd_67, C => N421, Y => - \RESMULT[7]\); - - RESMULT_madd_305_8_0 : XOR2 - port map(A => madd_305_2, B => madd_305_4, Y => - madd_305_8_0); - - RESMULT_madd_194_7 : XOR3 - port map(A => \a3_b[7]\, B => \a4_b[6]\, C => \a_i2_b[8]\, - Y => madd_194_7); - - RESMULT_madd_163 : NOR2A - port map(A => madd_157_0, B => madd_124, Y => madd_163); - - \RESMULT_a13_b[5]\ : NOR2B - port map(A => alu_sample(13), B => alu_coef_s(5), Y => - \a13_b[5]\); - - \RESMULT_a1_b[1]\ : NOR2B - port map(A => alu_sample(1), B => alu_coef_s(1), Y => - \a1_b[1]\); - - RESMULT_madd_237 : XA1B - port map(A => madd_193, B => madd_231_0_0, C => madd_198, Y - => madd_237); - - RESMULT_madd_606_ADD_22x22_fast_I18_P0N : OR2A - port map(A => madd_587, B => N_253, Y => N328); - - RESMULT_madd_593_0 : XOR3 - port map(A => madd_577, B => N_251, C => madd_582, Y => - N_253); - - RESMULT_madd_268_4_0 : XOR2 - port map(A => \a9_b[3]\, B => \a7_b[5]\, Y => madd_268_4_0); - - RESMULT_madd_379_2 : XOR3 - port map(A => \a13_b[2]\, B => \a15_b[0]\, C => \a14_b[1]\, - Y => madd_379_2); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - RESMULT_madd_606_ADD_22x22_fast_I3_G0N : NOR2B - port map(A => madd_125_0, B => madd_120_0, Y => N282); - - RESMULT_madd_493_0 : XOR3 - port map(A => madd_493_12, B => madd_493_11, C => madd_457, - Y => madd_493_0); - - RESMULT_madd_33 : MAJ3 - port map(A => \a5_b[0]\, B => \a3_b[2]\, C => \a4_b[1]\, Y - => madd_33); - - RESMULT_madd_305_7_0 : XOR2 - port map(A => \a7_b[6]\, B => \a6_b[7]\, Y => madd_305_7_0); - - RESMULT_madd_606_ADD_22x22_fast_I59_Y : NOR2B - port map(A => N280, B => N277, Y => N375); - - \RESMULT_a8_b[0]\ : NOR2B - port map(A => alu_sample(8), B => alu_coef_s(0), Y => - \a8_b[0]\); - - RESMULT_madd_606_ADD_22x22_fast_I133_Y : OR2 - port map(A => N413, B => I133_un1_Y, Y => N568); - - RESMULT_madd_183 : MIN3 - port map(A => madd_131, B => madd_136, C => madd_141, Y => - madd_183); - - RESMULT_madd_606_ADD_22x22_fast_I0_G0N : NOR2B - port map(A => CO3, B => madd_44_0, Y => N273); - - \RESMULT_a11_b[4]\ : NOR2B - port map(A => alu_sample(11), B => alu_coef_s(4), Y => - \a11_b[4]\); - - RESMULT_madd_606_ADD_22x22_fast_I170_Y_3 : OAI1 - port map(A => ADD_22x22_fast_I170_un1_Y_0, B => N449, C => - ADD_22x22_fast_I170_Y_3_0, Y => ADD_22x22_fast_I170_Y_3); - - RESMULT_madd_606_ADD_22x22_fast_I94_Y : AO1 - port map(A => N372, B => N369, C => N368, Y => N413); - - RESMULT_madd_606_ADD_22x22_fast_I77_Y : NOR2B - port map(A => N355, B => N351, Y => N396); - - \RESMULT_a0_b[0]\ : NOR2B - port map(A => alu_sample(0), B => alu_coef_s(0), Y => - \RESMULT[0]\); - - RESMULT_madd_39_0 : XOR3 - port map(A => madd_39_2, B => N_15, C => N_8, Y => - madd_39_0); - - RESMULT_madd_606_ADD_22x22_fast_I33_Y : OR2B - port map(A => N319, B => N316, Y => N349); - - RESMULT_madd_606_ADD_22x22_fast_I208_Y_0 : XNOR3 - port map(A => madd_587, B => N_253, C => N535, Y => - \RESMULT[23]\); - - \RESMULT_a_i1_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(1), Y => - \a_i1_b[8]\); - - RESMULT_madd_458_14 : XOR3 - port map(A => madd_458_9, B => madd_458_10, C => madd_415, - Y => madd_458_14); - - RESMULT_madd_342_10 : XNOR3 - port map(A => madd_284, B => N_122_i, C => madd_289, Y => - madd_342_10); - - VCC_i : VCC - port map(Y => \VCC\); - - RESMULT_madd_597 : MIN3 - port map(A => madd_577, B => madd_582, C => N_251, Y => - N_254); - - RESMULT_madd_582_0 : NOR3B - port map(A => alu_coef_s(8), B => madd_582_0_tz, C => - alu_sample(14), Y => madd_582_0); - - \RESMULT_a7_b[4]\ : NOR2B - port map(A => alu_sample(7), B => alu_coef_s(4), Y => - \a7_b[4]\); - - RESMULT_madd_358 : MIN3 - port map(A => \a12_b[3]\, B => \a10_b[5]\, C => \a11_b[4]\, - Y => madd_358); - - \RESMULT_a10_b[1]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(1), Y => - \a10_b[1]\); - - RESMULT_madd_497 : MIN3 - port map(A => madd_493_11, B => madd_457, C => madd_493_12, - Y => madd_497); - - RESMULT_madd_395 : MAJ3 - port map(A => \a13_b[3]\, B => \a11_b[5]\, C => \a12_b[4]\, - Y => madd_395); - - \RESMULT_a10_b[3]\ : NOR2B - port map(A => alu_sample(10), B => alu_coef_s(3), Y => - \a10_b[3]\); - - RESMULT_madd_606_ADD_22x22_fast_I69_Y : NOR3C - port map(A => N319, B => N322, C => N343, Y => N388); - - RESMULT_madd_268_8 : XNOR3 - port map(A => madd_268_4, B => madd_268_2, C => madd_268_7, - Y => N_113_i); - - RESMULT_madd_1_605_SUM1_0 : XOR3 - port map(A => \a0_b[2]\, B => madd_0_s_0, C => CO0, Y => - \RESMULT[2]\); - - \REG[9]\ : DFN1E1C0 - port map(D => \RESMULT[9]\, CLK => lclk_c, CLR => rstn, E - => mult, Q => MULTout(9)); - - RESMULT_madd_606_ADD_22x22_fast_I203_Y_0 : XNOR3 - port map(A => madd_462, B => madd_493_0, C => N547, Y => - \RESMULT[18]\); - - \RESMULT_a15_b[2]\ : NOR2B - port map(A => alu_sample(15), B => alu_coef_s(2), Y => - \a15_b[2]\); - - RESMULT_madd_379_8 : XNOR3 - port map(A => madd_379_4, B => madd_379_2, C => madd_379_7, - Y => N_161_i); - - RESMULT_madd_82 : MIN3 - port map(A => \a1_b[6]\, B => madd_50, C => \a0_b[7]\, Y - => madd_82); - - RESMULT_madd_606_ADD_22x22_fast_I48_Y : OR2A - port map(A => I48_un1_Y_i, B => N294, Y => N364); - - RESMULT_madd_606_ADD_22x22_fast_I45_Y : NOR2B - port map(A => N301, B => N298, Y => N361); - - \RESMULT_a5_b[4]\ : NOR2B - port map(A => alu_sample(5), B => alu_coef_s(4), Y => - \a5_b[4]\); - - RESMULT_madd_416_8 : XOR3 - port map(A => madd_416_4, B => madd_416_2, C => madd_416_7, - Y => madd_416_8); - - RESMULT_madd_606_ADD_22x22_fast_I12_P0N : OR2 - port map(A => madd_458_0, B => madd_422, Y => N310); - - RESMULT_madd_606_ADD_22x22_fast_I195_Y_0 : XOR3 - port map(A => madd_163, B => madd_199_0, C => N461, Y => - \RESMULT[10]\); - - \RESMULT_a1_b[2]\ : OR2B - port map(A => alu_sample(1), B => alu_coef_s(2), Y => - \a1_b[2]\); - - RESMULT_madd_606_ADD_22x22_fast_I87_Y : OR2B - port map(A => N365, B => N361, Y => N406); - - RESMULT_madd_126 : NOR3B - port map(A => madd_88_0, B => madd_115_0, C => madd_65, Y - => madd_126); - - RESMULT_madd_493_6 : XOR2 - port map(A => madd_493_6_0, B => madd_427_1, Y => - madd_493_6); - - \RESMULT_a14_b[5]\ : NOR2B - port map(A => alu_sample(14), B => alu_coef_s(5), Y => - \a14_b[5]\); - - RESMULT_madd_161 : MIN3 - port map(A => madd_157_11, B => madd_119, C => madd_157_12, - Y => madd_161); - - RESMULT_madd_606_ADD_22x22_fast_I194_Y_0_0 : XNOR3 - port map(A => madd_124, B => madd_157_0, C => madd_126, Y - => ADD_22x22_fast_I194_Y_0_0); - - \RESMULT_a4_b[0]\ : NOR2B - port map(A => alu_sample(4), B => alu_coef_s(0), Y => - \a4_b[0]\); - - \RESMULT_a12_b[4]\ : NOR2B - port map(A => alu_sample(12), B => alu_coef_s(4), Y => - \a12_b[4]\); - - RESMULT_madd_347_0 : XNOR3 - port map(A => madd_304, B => madd_342_0_0, C => madd_309, Y - => madd_347_0); - - RESMULT_madd_205 : MIN3 - port map(A => \a11_b[0]\, B => \a9_b[2]\, C => \a10_b[1]\, - Y => N_90_i); - - RESMULT_madd_13 : MIN3 - port map(A => \a0_b[3]\, B => madd_3, C => madd_4_0, Y => - madd_13); - - RESMULT_madd_606_ADD_22x22_fast_I207_Y_0 : AX1E - port map(A => I172_un1_Y, B => ADD_22x22_fast_I172_Y_2, C - => ADD_22x22_fast_I207_Y_0_0, Y => \RESMULT[22]\); - - RESMULT_madd_606_ADD_22x22_fast_I7_G0N : NOR2B - port map(A => madd_273_0, B => madd_237, Y => N294); - - \RESMULT_a_i8_b[8]\ : NOR2A - port map(A => alu_coef_s(8), B => alu_sample(8), Y => - \a_i8_b[8]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity MAC is - - port( sample_out_s : out std_logic_vector(17 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_ctrl : in std_logic_vector(2 downto 0); - lclk_c : in std_logic; - rstn : in std_logic - ); - -end MAC; - -architecture DEF_ARCH of MAC is - - component MAC_REG_18 - port( alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - OP1_2C_D : out std_logic_vector(17 downto 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MAC_REG_9 - port( alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - OP2_2C_D : out std_logic_vector(8 downto 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MAC_REG_1_4 - port( MACMUX2sel_D : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - MACMUX2sel_D_D : out std_logic - ); - end component; - - component MAC_CONTROLER - port( alu_ctrl : in std_logic_vector(1 downto 0) := (others => 'U'); - mult : out std_logic; - N_4 : out std_logic; - MACMUX2sel : out std_logic; - mult_0 : out std_logic - ); - end component; - - component MAC_MUX - port( OP1_2C_D : in std_logic_vector(17 downto 0) := (others => 'U'); - MULTout : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinB : out std_logic_vector(24 downto 0); - OP2_2C_D : in std_logic_vector(8 downto 0) := (others => 'U'); - ADDERout : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinA : out std_logic_vector(24 downto 0); - MACMUXsel_D : in std_logic := 'U'; - MACMUXsel_D_1 : in std_logic := 'U'; - MACMUXsel_D_0 : in std_logic := 'U' - ); - end component; - - component MAC_REG_27 - port( MULTout : in std_logic_vector(24 downto 7) := (others => 'U'); - MULTout_D : out std_logic_vector(24 downto 7); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component MAC_REG_1_1 - port( alu_ctrl : in std_logic_vector(0 to 0) := (others => 'U'); - add_D : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - add_D_0 : out std_logic - ); - end component; - - component MAC_REG_1_3 - port( MACMUX2sel : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - MACMUX2sel_D : out std_logic - ); - end component; - - component MAC_REG_1 - port( alu_ctrl : in std_logic_vector(2 to 2) := (others => 'U'); - clr_MAC_D : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - clr_MAC_D_0 : out std_logic - ); - end component; - - component Adder - port( ADDERout : out std_logic_vector(24 downto 0); - ADDERinB : in std_logic_vector(24 downto 0) := (others => 'U'); - ADDERinA : in std_logic_vector(24 downto 0) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - clr_MAC_D : in std_logic := 'U'; - add_D : in std_logic := 'U'; - clr_MAC_D_0 : in std_logic := 'U'; - MACMUX2sel_D : in std_logic := 'U'; - add_D_0 : in std_logic := 'U' - ); - end component; - - component MAC_MUX2 - port( MULTout_D : in std_logic_vector(24 downto 7) := (others => 'U'); - ADDERout : in std_logic_vector(24 downto 7) := (others => 'U'); - sample_out_s : out std_logic_vector(17 downto 0); - MACMUX2sel_D_D : in std_logic := 'U' - ); - end component; - - component MAC_REG_1_2 - port( MACMUXsel_D : out std_logic; - MACMUXsel_D_0 : out std_logic; - N_4 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - MACMUXsel_D_1 : out std_logic - ); - end component; - - component Multiplier - port( MULTout : out std_logic_vector(24 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - mult : in std_logic := 'U'; - mult_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal mult, N_4, MACMUX2sel, mult_0, \MULTout[0]\, - \MULTout[1]\, \MULTout[2]\, \MULTout[3]\, \MULTout[4]\, - \MULTout[5]\, \MULTout[6]\, \MULTout[7]\, \MULTout[8]\, - \MULTout[9]\, \MULTout[10]\, \MULTout[11]\, \MULTout[12]\, - \MULTout[13]\, \MULTout[14]\, \MULTout[15]\, - \MULTout[16]\, \MULTout[17]\, \MULTout[18]\, - \MULTout[19]\, \MULTout[20]\, \MULTout[21]\, - \MULTout[22]\, \MULTout[23]\, \MULTout[24]\, - \ADDERout[0]\, \ADDERout[1]\, \ADDERout[2]\, - \ADDERout[3]\, \ADDERout[4]\, \ADDERout[5]\, - \ADDERout[6]\, \ADDERout[7]\, \ADDERout[8]\, - \ADDERout[9]\, \ADDERout[10]\, \ADDERout[11]\, - \ADDERout[12]\, \ADDERout[13]\, \ADDERout[14]\, - \ADDERout[15]\, \ADDERout[16]\, \ADDERout[17]\, - \ADDERout[18]\, \ADDERout[19]\, \ADDERout[20]\, - \ADDERout[21]\, \ADDERout[22]\, \ADDERout[23]\, - \ADDERout[24]\, \ADDERinB[0]\, \ADDERinB[1]\, - \ADDERinB[2]\, \ADDERinB[3]\, \ADDERinB[4]\, - \ADDERinB[5]\, \ADDERinB[6]\, \ADDERinB[7]\, - \ADDERinB[8]\, \ADDERinB[9]\, \ADDERinB[10]\, - \ADDERinB[11]\, \ADDERinB[12]\, \ADDERinB[13]\, - \ADDERinB[14]\, \ADDERinB[15]\, \ADDERinB[16]\, - \ADDERinB[17]\, \ADDERinB[18]\, \ADDERinB[19]\, - \ADDERinB[20]\, \ADDERinB[21]\, \ADDERinB[22]\, - \ADDERinB[23]\, \ADDERinB[24]\, \ADDERinA[0]\, - \ADDERinA[1]\, \ADDERinA[2]\, \ADDERinA[3]\, - \ADDERinA[4]\, \ADDERinA[5]\, \ADDERinA[6]\, - \ADDERinA[7]\, \ADDERinA[8]\, \ADDERinA[9]\, - \ADDERinA[10]\, \ADDERinA[11]\, \ADDERinA[12]\, - \ADDERinA[13]\, \ADDERinA[14]\, \ADDERinA[15]\, - \ADDERinA[16]\, \ADDERinA[17]\, \ADDERinA[18]\, - \ADDERinA[19]\, \ADDERinA[20]\, \ADDERinA[21]\, - \ADDERinA[22]\, \ADDERinA[23]\, \ADDERinA[24]\, clr_MAC_D, - add_D, clr_MAC_D_0, MACMUX2sel_D, add_D_0, \OP1_2C_D[0]\, - \OP1_2C_D[1]\, \OP1_2C_D[2]\, \OP1_2C_D[3]\, - \OP1_2C_D[4]\, \OP1_2C_D[5]\, \OP1_2C_D[6]\, - \OP1_2C_D[7]\, \OP1_2C_D[8]\, \OP1_2C_D[9]\, - \OP1_2C_D[10]\, \OP1_2C_D[11]\, \OP1_2C_D[12]\, - \OP1_2C_D[13]\, \OP1_2C_D[14]\, \OP1_2C_D[15]\, - \OP1_2C_D[16]\, \OP1_2C_D[17]\, \OP2_2C_D[0]\, - \OP2_2C_D[1]\, \OP2_2C_D[2]\, \OP2_2C_D[3]\, - \OP2_2C_D[4]\, \OP2_2C_D[5]\, \OP2_2C_D[6]\, - \OP2_2C_D[7]\, \OP2_2C_D[8]\, \MULTout_D[7]\, - \MULTout_D[8]\, \MULTout_D[9]\, \MULTout_D[10]\, - \MULTout_D[11]\, \MULTout_D[12]\, \MULTout_D[13]\, - \MULTout_D[14]\, \MULTout_D[15]\, \MULTout_D[16]\, - \MULTout_D[17]\, \MULTout_D[18]\, \MULTout_D[19]\, - \MULTout_D[20]\, \MULTout_D[21]\, \MULTout_D[22]\, - \MULTout_D[23]\, \MULTout_D[24]\, MACMUXsel_D, - MACMUXsel_D_0, MACMUXsel_D_1, MACMUX2sel_D_D, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : MAC_REG_18 - Use entity work.MAC_REG_18(DEF_ARCH); - for all : MAC_REG_9 - Use entity work.MAC_REG_9(DEF_ARCH); - for all : MAC_REG_1_4 - Use entity work.MAC_REG_1_4(DEF_ARCH); - for all : MAC_CONTROLER - Use entity work.MAC_CONTROLER(DEF_ARCH); - for all : MAC_MUX - Use entity work.MAC_MUX(DEF_ARCH); - for all : MAC_REG_27 - Use entity work.MAC_REG_27(DEF_ARCH); - for all : MAC_REG_1_1 - Use entity work.MAC_REG_1_1(DEF_ARCH); - for all : MAC_REG_1_3 - Use entity work.MAC_REG_1_3(DEF_ARCH); - for all : MAC_REG_1 - Use entity work.MAC_REG_1(DEF_ARCH); - for all : Adder - Use entity work.Adder(DEF_ARCH); - for all : MAC_MUX2 - Use entity work.MAC_MUX2(DEF_ARCH); - for all : MAC_REG_1_2 - Use entity work.MAC_REG_1_2(DEF_ARCH); - for all : Multiplier - Use entity work.Multiplier(DEF_ARCH); -begin - - - OP1REG : MAC_REG_18 - port map(alu_sample(17) => alu_sample(17), alu_sample(16) - => alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), - OP1_2C_D(17) => \OP1_2C_D[17]\, OP1_2C_D(16) => - \OP1_2C_D[16]\, OP1_2C_D(15) => \OP1_2C_D[15]\, - OP1_2C_D(14) => \OP1_2C_D[14]\, OP1_2C_D(13) => - \OP1_2C_D[13]\, OP1_2C_D(12) => \OP1_2C_D[12]\, - OP1_2C_D(11) => \OP1_2C_D[11]\, OP1_2C_D(10) => - \OP1_2C_D[10]\, OP1_2C_D(9) => \OP1_2C_D[9]\, OP1_2C_D(8) - => \OP1_2C_D[8]\, OP1_2C_D(7) => \OP1_2C_D[7]\, - OP1_2C_D(6) => \OP1_2C_D[6]\, OP1_2C_D(5) => - \OP1_2C_D[5]\, OP1_2C_D(4) => \OP1_2C_D[4]\, OP1_2C_D(3) - => \OP1_2C_D[3]\, OP1_2C_D(2) => \OP1_2C_D[2]\, - OP1_2C_D(1) => \OP1_2C_D[1]\, OP1_2C_D(0) => - \OP1_2C_D[0]\, rstn => rstn, lclk_c => lclk_c); - - GND_i_0 : GND - port map(Y => GND_0); - - OP2REG : MAC_REG_9 - port map(alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - OP2_2C_D(8) => \OP2_2C_D[8]\, OP2_2C_D(7) => - \OP2_2C_D[7]\, OP2_2C_D(6) => \OP2_2C_D[6]\, OP2_2C_D(5) - => \OP2_2C_D[5]\, OP2_2C_D(4) => \OP2_2C_D[4]\, - OP2_2C_D(3) => \OP2_2C_D[3]\, OP2_2C_D(2) => - \OP2_2C_D[2]\, OP2_2C_D(1) => \OP2_2C_D[1]\, OP2_2C_D(0) - => \OP2_2C_D[0]\, rstn => rstn, lclk_c => lclk_c); - - VCC_i : VCC - port map(Y => \VCC\); - - MACMUX2selREG2 : MAC_REG_1_4 - port map(MACMUX2sel_D => MACMUX2sel_D, rstn => rstn, lclk_c - => lclk_c, MACMUX2sel_D_D => MACMUX2sel_D_D); - - MAC_CONTROLER1 : MAC_CONTROLER - port map(alu_ctrl(1) => alu_ctrl(1), alu_ctrl(0) => - alu_ctrl(0), mult => mult, N_4 => N_4, MACMUX2sel => - MACMUX2sel, mult_0 => mult_0); - - MACMUX_inst : MAC_MUX - port map(OP1_2C_D(17) => \OP1_2C_D[17]\, OP1_2C_D(16) => - \OP1_2C_D[16]\, OP1_2C_D(15) => \OP1_2C_D[15]\, - OP1_2C_D(14) => \OP1_2C_D[14]\, OP1_2C_D(13) => - \OP1_2C_D[13]\, OP1_2C_D(12) => \OP1_2C_D[12]\, - OP1_2C_D(11) => \OP1_2C_D[11]\, OP1_2C_D(10) => - \OP1_2C_D[10]\, OP1_2C_D(9) => \OP1_2C_D[9]\, OP1_2C_D(8) - => \OP1_2C_D[8]\, OP1_2C_D(7) => \OP1_2C_D[7]\, - OP1_2C_D(6) => \OP1_2C_D[6]\, OP1_2C_D(5) => - \OP1_2C_D[5]\, OP1_2C_D(4) => \OP1_2C_D[4]\, OP1_2C_D(3) - => \OP1_2C_D[3]\, OP1_2C_D(2) => \OP1_2C_D[2]\, - OP1_2C_D(1) => \OP1_2C_D[1]\, OP1_2C_D(0) => - \OP1_2C_D[0]\, MULTout(24) => \MULTout[24]\, MULTout(23) - => \MULTout[23]\, MULTout(22) => \MULTout[22]\, - MULTout(21) => \MULTout[21]\, MULTout(20) => - \MULTout[20]\, MULTout(19) => \MULTout[19]\, MULTout(18) - => \MULTout[18]\, MULTout(17) => \MULTout[17]\, - MULTout(16) => \MULTout[16]\, MULTout(15) => - \MULTout[15]\, MULTout(14) => \MULTout[14]\, MULTout(13) - => \MULTout[13]\, MULTout(12) => \MULTout[12]\, - MULTout(11) => \MULTout[11]\, MULTout(10) => - \MULTout[10]\, MULTout(9) => \MULTout[9]\, MULTout(8) => - \MULTout[8]\, MULTout(7) => \MULTout[7]\, MULTout(6) => - \MULTout[6]\, MULTout(5) => \MULTout[5]\, MULTout(4) => - \MULTout[4]\, MULTout(3) => \MULTout[3]\, MULTout(2) => - \MULTout[2]\, MULTout(1) => \MULTout[1]\, MULTout(0) => - \MULTout[0]\, ADDERinB(24) => \ADDERinB[24]\, - ADDERinB(23) => \ADDERinB[23]\, ADDERinB(22) => - \ADDERinB[22]\, ADDERinB(21) => \ADDERinB[21]\, - ADDERinB(20) => \ADDERinB[20]\, ADDERinB(19) => - \ADDERinB[19]\, ADDERinB(18) => \ADDERinB[18]\, - ADDERinB(17) => \ADDERinB[17]\, ADDERinB(16) => - \ADDERinB[16]\, ADDERinB(15) => \ADDERinB[15]\, - ADDERinB(14) => \ADDERinB[14]\, ADDERinB(13) => - \ADDERinB[13]\, ADDERinB(12) => \ADDERinB[12]\, - ADDERinB(11) => \ADDERinB[11]\, ADDERinB(10) => - \ADDERinB[10]\, ADDERinB(9) => \ADDERinB[9]\, ADDERinB(8) - => \ADDERinB[8]\, ADDERinB(7) => \ADDERinB[7]\, - ADDERinB(6) => \ADDERinB[6]\, ADDERinB(5) => - \ADDERinB[5]\, ADDERinB(4) => \ADDERinB[4]\, ADDERinB(3) - => \ADDERinB[3]\, ADDERinB(2) => \ADDERinB[2]\, - ADDERinB(1) => \ADDERinB[1]\, ADDERinB(0) => - \ADDERinB[0]\, OP2_2C_D(8) => \OP2_2C_D[8]\, OP2_2C_D(7) - => \OP2_2C_D[7]\, OP2_2C_D(6) => \OP2_2C_D[6]\, - OP2_2C_D(5) => \OP2_2C_D[5]\, OP2_2C_D(4) => - \OP2_2C_D[4]\, OP2_2C_D(3) => \OP2_2C_D[3]\, OP2_2C_D(2) - => \OP2_2C_D[2]\, OP2_2C_D(1) => \OP2_2C_D[1]\, - OP2_2C_D(0) => \OP2_2C_D[0]\, ADDERout(24) => - \ADDERout[24]\, ADDERout(23) => \ADDERout[23]\, - ADDERout(22) => \ADDERout[22]\, ADDERout(21) => - \ADDERout[21]\, ADDERout(20) => \ADDERout[20]\, - ADDERout(19) => \ADDERout[19]\, ADDERout(18) => - \ADDERout[18]\, ADDERout(17) => \ADDERout[17]\, - ADDERout(16) => \ADDERout[16]\, ADDERout(15) => - \ADDERout[15]\, ADDERout(14) => \ADDERout[14]\, - ADDERout(13) => \ADDERout[13]\, ADDERout(12) => - \ADDERout[12]\, ADDERout(11) => \ADDERout[11]\, - ADDERout(10) => \ADDERout[10]\, ADDERout(9) => - \ADDERout[9]\, ADDERout(8) => \ADDERout[8]\, ADDERout(7) - => \ADDERout[7]\, ADDERout(6) => \ADDERout[6]\, - ADDERout(5) => \ADDERout[5]\, ADDERout(4) => - \ADDERout[4]\, ADDERout(3) => \ADDERout[3]\, ADDERout(2) - => \ADDERout[2]\, ADDERout(1) => \ADDERout[1]\, - ADDERout(0) => \ADDERout[0]\, ADDERinA(24) => - \ADDERinA[24]\, ADDERinA(23) => \ADDERinA[23]\, - ADDERinA(22) => \ADDERinA[22]\, ADDERinA(21) => - \ADDERinA[21]\, ADDERinA(20) => \ADDERinA[20]\, - ADDERinA(19) => \ADDERinA[19]\, ADDERinA(18) => - \ADDERinA[18]\, ADDERinA(17) => \ADDERinA[17]\, - ADDERinA(16) => \ADDERinA[16]\, ADDERinA(15) => - \ADDERinA[15]\, ADDERinA(14) => \ADDERinA[14]\, - ADDERinA(13) => \ADDERinA[13]\, ADDERinA(12) => - \ADDERinA[12]\, ADDERinA(11) => \ADDERinA[11]\, - ADDERinA(10) => \ADDERinA[10]\, ADDERinA(9) => - \ADDERinA[9]\, ADDERinA(8) => \ADDERinA[8]\, ADDERinA(7) - => \ADDERinA[7]\, ADDERinA(6) => \ADDERinA[6]\, - ADDERinA(5) => \ADDERinA[5]\, ADDERinA(4) => - \ADDERinA[4]\, ADDERinA(3) => \ADDERinA[3]\, ADDERinA(2) - => \ADDERinA[2]\, ADDERinA(1) => \ADDERinA[1]\, - ADDERinA(0) => \ADDERinA[0]\, MACMUXsel_D => MACMUXsel_D, - MACMUXsel_D_1 => MACMUXsel_D_1, MACMUXsel_D_0 => - MACMUXsel_D_0); - - MULToutREG : MAC_REG_27 - port map(MULTout(24) => \MULTout[24]\, MULTout(23) => - \MULTout[23]\, MULTout(22) => \MULTout[22]\, MULTout(21) - => \MULTout[21]\, MULTout(20) => \MULTout[20]\, - MULTout(19) => \MULTout[19]\, MULTout(18) => - \MULTout[18]\, MULTout(17) => \MULTout[17]\, MULTout(16) - => \MULTout[16]\, MULTout(15) => \MULTout[15]\, - MULTout(14) => \MULTout[14]\, MULTout(13) => - \MULTout[13]\, MULTout(12) => \MULTout[12]\, MULTout(11) - => \MULTout[11]\, MULTout(10) => \MULTout[10]\, - MULTout(9) => \MULTout[9]\, MULTout(8) => \MULTout[8]\, - MULTout(7) => \MULTout[7]\, MULTout_D(24) => - \MULTout_D[24]\, MULTout_D(23) => \MULTout_D[23]\, - MULTout_D(22) => \MULTout_D[22]\, MULTout_D(21) => - \MULTout_D[21]\, MULTout_D(20) => \MULTout_D[20]\, - MULTout_D(19) => \MULTout_D[19]\, MULTout_D(18) => - \MULTout_D[18]\, MULTout_D(17) => \MULTout_D[17]\, - MULTout_D(16) => \MULTout_D[16]\, MULTout_D(15) => - \MULTout_D[15]\, MULTout_D(14) => \MULTout_D[14]\, - MULTout_D(13) => \MULTout_D[13]\, MULTout_D(12) => - \MULTout_D[12]\, MULTout_D(11) => \MULTout_D[11]\, - MULTout_D(10) => \MULTout_D[10]\, MULTout_D(9) => - \MULTout_D[9]\, MULTout_D(8) => \MULTout_D[8]\, - MULTout_D(7) => \MULTout_D[7]\, rstn => rstn, lclk_c => - lclk_c); - - GND_i : GND - port map(Y => \GND\); - - addREG : MAC_REG_1_1 - port map(alu_ctrl(0) => alu_ctrl(0), add_D => add_D, rstn - => rstn, lclk_c => lclk_c, add_D_0 => add_D_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - MACMUX2selREG : MAC_REG_1_3 - port map(MACMUX2sel => MACMUX2sel, rstn => rstn, lclk_c => - lclk_c, MACMUX2sel_D => MACMUX2sel_D); - - clr_MACREG1 : MAC_REG_1 - port map(alu_ctrl(2) => alu_ctrl(2), clr_MAC_D => clr_MAC_D, - rstn => rstn, lclk_c => lclk_c, clr_MAC_D_0 => - clr_MAC_D_0); - - adder_inst : Adder - port map(ADDERout(24) => \ADDERout[24]\, ADDERout(23) => - \ADDERout[23]\, ADDERout(22) => \ADDERout[22]\, - ADDERout(21) => \ADDERout[21]\, ADDERout(20) => - \ADDERout[20]\, ADDERout(19) => \ADDERout[19]\, - ADDERout(18) => \ADDERout[18]\, ADDERout(17) => - \ADDERout[17]\, ADDERout(16) => \ADDERout[16]\, - ADDERout(15) => \ADDERout[15]\, ADDERout(14) => - \ADDERout[14]\, ADDERout(13) => \ADDERout[13]\, - ADDERout(12) => \ADDERout[12]\, ADDERout(11) => - \ADDERout[11]\, ADDERout(10) => \ADDERout[10]\, - ADDERout(9) => \ADDERout[9]\, ADDERout(8) => - \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, ADDERout(6) - => \ADDERout[6]\, ADDERout(5) => \ADDERout[5]\, - ADDERout(4) => \ADDERout[4]\, ADDERout(3) => - \ADDERout[3]\, ADDERout(2) => \ADDERout[2]\, ADDERout(1) - => \ADDERout[1]\, ADDERout(0) => \ADDERout[0]\, - ADDERinB(24) => \ADDERinB[24]\, ADDERinB(23) => - \ADDERinB[23]\, ADDERinB(22) => \ADDERinB[22]\, - ADDERinB(21) => \ADDERinB[21]\, ADDERinB(20) => - \ADDERinB[20]\, ADDERinB(19) => \ADDERinB[19]\, - ADDERinB(18) => \ADDERinB[18]\, ADDERinB(17) => - \ADDERinB[17]\, ADDERinB(16) => \ADDERinB[16]\, - ADDERinB(15) => \ADDERinB[15]\, ADDERinB(14) => - \ADDERinB[14]\, ADDERinB(13) => \ADDERinB[13]\, - ADDERinB(12) => \ADDERinB[12]\, ADDERinB(11) => - \ADDERinB[11]\, ADDERinB(10) => \ADDERinB[10]\, - ADDERinB(9) => \ADDERinB[9]\, ADDERinB(8) => - \ADDERinB[8]\, ADDERinB(7) => \ADDERinB[7]\, ADDERinB(6) - => \ADDERinB[6]\, ADDERinB(5) => \ADDERinB[5]\, - ADDERinB(4) => \ADDERinB[4]\, ADDERinB(3) => - \ADDERinB[3]\, ADDERinB(2) => \ADDERinB[2]\, ADDERinB(1) - => \ADDERinB[1]\, ADDERinB(0) => \ADDERinB[0]\, - ADDERinA(24) => \ADDERinA[24]\, ADDERinA(23) => - \ADDERinA[23]\, ADDERinA(22) => \ADDERinA[22]\, - ADDERinA(21) => \ADDERinA[21]\, ADDERinA(20) => - \ADDERinA[20]\, ADDERinA(19) => \ADDERinA[19]\, - ADDERinA(18) => \ADDERinA[18]\, ADDERinA(17) => - \ADDERinA[17]\, ADDERinA(16) => \ADDERinA[16]\, - ADDERinA(15) => \ADDERinA[15]\, ADDERinA(14) => - \ADDERinA[14]\, ADDERinA(13) => \ADDERinA[13]\, - ADDERinA(12) => \ADDERinA[12]\, ADDERinA(11) => - \ADDERinA[11]\, ADDERinA(10) => \ADDERinA[10]\, - ADDERinA(9) => \ADDERinA[9]\, ADDERinA(8) => - \ADDERinA[8]\, ADDERinA(7) => \ADDERinA[7]\, ADDERinA(6) - => \ADDERinA[6]\, ADDERinA(5) => \ADDERinA[5]\, - ADDERinA(4) => \ADDERinA[4]\, ADDERinA(3) => - \ADDERinA[3]\, ADDERinA(2) => \ADDERinA[2]\, ADDERinA(1) - => \ADDERinA[1]\, ADDERinA(0) => \ADDERinA[0]\, rstn => - rstn, lclk_c => lclk_c, clr_MAC_D => clr_MAC_D, add_D => - add_D, clr_MAC_D_0 => clr_MAC_D_0, MACMUX2sel_D => - MACMUX2sel_D, add_D_0 => add_D_0); - - MAC_MUX2_inst : MAC_MUX2 - port map(MULTout_D(24) => \MULTout_D[24]\, MULTout_D(23) - => \MULTout_D[23]\, MULTout_D(22) => \MULTout_D[22]\, - MULTout_D(21) => \MULTout_D[21]\, MULTout_D(20) => - \MULTout_D[20]\, MULTout_D(19) => \MULTout_D[19]\, - MULTout_D(18) => \MULTout_D[18]\, MULTout_D(17) => - \MULTout_D[17]\, MULTout_D(16) => \MULTout_D[16]\, - MULTout_D(15) => \MULTout_D[15]\, MULTout_D(14) => - \MULTout_D[14]\, MULTout_D(13) => \MULTout_D[13]\, - MULTout_D(12) => \MULTout_D[12]\, MULTout_D(11) => - \MULTout_D[11]\, MULTout_D(10) => \MULTout_D[10]\, - MULTout_D(9) => \MULTout_D[9]\, MULTout_D(8) => - \MULTout_D[8]\, MULTout_D(7) => \MULTout_D[7]\, - ADDERout(24) => \ADDERout[24]\, ADDERout(23) => - \ADDERout[23]\, ADDERout(22) => \ADDERout[22]\, - ADDERout(21) => \ADDERout[21]\, ADDERout(20) => - \ADDERout[20]\, ADDERout(19) => \ADDERout[19]\, - ADDERout(18) => \ADDERout[18]\, ADDERout(17) => - \ADDERout[17]\, ADDERout(16) => \ADDERout[16]\, - ADDERout(15) => \ADDERout[15]\, ADDERout(14) => - \ADDERout[14]\, ADDERout(13) => \ADDERout[13]\, - ADDERout(12) => \ADDERout[12]\, ADDERout(11) => - \ADDERout[11]\, ADDERout(10) => \ADDERout[10]\, - ADDERout(9) => \ADDERout[9]\, ADDERout(8) => - \ADDERout[8]\, ADDERout(7) => \ADDERout[7]\, - sample_out_s(17) => sample_out_s(17), sample_out_s(16) - => sample_out_s(16), sample_out_s(15) => - sample_out_s(15), sample_out_s(14) => sample_out_s(14), - sample_out_s(13) => sample_out_s(13), sample_out_s(12) - => sample_out_s(12), sample_out_s(11) => - sample_out_s(11), sample_out_s(10) => sample_out_s(10), - sample_out_s(9) => sample_out_s(9), sample_out_s(8) => - sample_out_s(8), sample_out_s(7) => sample_out_s(7), - sample_out_s(6) => sample_out_s(6), sample_out_s(5) => - sample_out_s(5), sample_out_s(4) => sample_out_s(4), - sample_out_s(3) => sample_out_s(3), sample_out_s(2) => - sample_out_s(2), sample_out_s(1) => sample_out_s(1), - sample_out_s(0) => sample_out_s(0), MACMUX2sel_D_D => - MACMUX2sel_D_D); - - MACMUXselREG : MAC_REG_1_2 - port map(MACMUXsel_D => MACMUXsel_D, MACMUXsel_D_0 => - MACMUXsel_D_0, N_4 => N_4, rstn => rstn, lclk_c => lclk_c, - MACMUXsel_D_1 => MACMUXsel_D_1); - - Multiplieri_nst : Multiplier - port map(MULTout(24) => \MULTout[24]\, MULTout(23) => - \MULTout[23]\, MULTout(22) => \MULTout[22]\, MULTout(21) - => \MULTout[21]\, MULTout(20) => \MULTout[20]\, - MULTout(19) => \MULTout[19]\, MULTout(18) => - \MULTout[18]\, MULTout(17) => \MULTout[17]\, MULTout(16) - => \MULTout[16]\, MULTout(15) => \MULTout[15]\, - MULTout(14) => \MULTout[14]\, MULTout(13) => - \MULTout[13]\, MULTout(12) => \MULTout[12]\, MULTout(11) - => \MULTout[11]\, MULTout(10) => \MULTout[10]\, - MULTout(9) => \MULTout[9]\, MULTout(8) => \MULTout[8]\, - MULTout(7) => \MULTout[7]\, MULTout(6) => \MULTout[6]\, - MULTout(5) => \MULTout[5]\, MULTout(4) => \MULTout[4]\, - MULTout(3) => \MULTout[3]\, MULTout(2) => \MULTout[2]\, - MULTout(1) => \MULTout[1]\, MULTout(0) => \MULTout[0]\, - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_sample(17) => alu_sample(17), alu_sample(16) => - alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), mult => - mult, mult_0 => mult_0, rstn => rstn, lclk_c => lclk_c); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ALU is - - port( alu_ctrl : in std_logic_vector(2 downto 0); - alu_coef_s : in std_logic_vector(8 downto 0); - alu_sample : in std_logic_vector(17 downto 0); - sample_out_s : out std_logic_vector(17 downto 0); - rstn : in std_logic; - lclk_c : in std_logic - ); - -end ALU; - -architecture DEF_ARCH of ALU is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MAC - port( sample_out_s : out std_logic_vector(17 downto 0); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - lclk_c : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : MAC - Use entity work.MAC(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \arith.MACinst\ : MAC - port map(sample_out_s(17) => sample_out_s(17), - sample_out_s(16) => sample_out_s(16), sample_out_s(15) - => sample_out_s(15), sample_out_s(14) => - sample_out_s(14), sample_out_s(13) => sample_out_s(13), - sample_out_s(12) => sample_out_s(12), sample_out_s(11) - => sample_out_s(11), sample_out_s(10) => - sample_out_s(10), sample_out_s(9) => sample_out_s(9), - sample_out_s(8) => sample_out_s(8), sample_out_s(7) => - sample_out_s(7), sample_out_s(6) => sample_out_s(6), - sample_out_s(5) => sample_out_s(5), sample_out_s(4) => - sample_out_s(4), sample_out_s(3) => sample_out_s(3), - sample_out_s(2) => sample_out_s(2), sample_out_s(1) => - sample_out_s(1), sample_out_s(0) => sample_out_s(0), - alu_sample(17) => alu_sample(17), alu_sample(16) => - alu_sample(16), alu_sample(15) => alu_sample(15), - alu_sample(14) => alu_sample(14), alu_sample(13) => - alu_sample(13), alu_sample(12) => alu_sample(12), - alu_sample(11) => alu_sample(11), alu_sample(10) => - alu_sample(10), alu_sample(9) => alu_sample(9), - alu_sample(8) => alu_sample(8), alu_sample(7) => - alu_sample(7), alu_sample(6) => alu_sample(6), - alu_sample(5) => alu_sample(5), alu_sample(4) => - alu_sample(4), alu_sample(3) => alu_sample(3), - alu_sample(2) => alu_sample(2), alu_sample(1) => - alu_sample(1), alu_sample(0) => alu_sample(0), - alu_coef_s(8) => alu_coef_s(8), alu_coef_s(7) => - alu_coef_s(7), alu_coef_s(6) => alu_coef_s(6), - alu_coef_s(5) => alu_coef_s(5), alu_coef_s(4) => - alu_coef_s(4), alu_coef_s(3) => alu_coef_s(3), - alu_coef_s(2) => alu_coef_s(2), alu_coef_s(1) => - alu_coef_s(1), alu_coef_s(0) => alu_coef_s(0), - alu_ctrl(2) => alu_ctrl(2), alu_ctrl(1) => alu_ctrl(1), - alu_ctrl(0) => alu_ctrl(0), lclk_c => lclk_c, rstn => - rstn); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity generic_syncram_2p is - - port( ram_input : in std_logic_vector(17 downto 0); - counter : in std_logic_vector(7 downto 0); - ram_output : out std_logic_vector(17 downto 0); - ram_write_i : in std_logic; - generic_syncram_2p_VCC : in std_logic; - generic_syncram_2p_GND : in std_logic; - ADD_8x8_medium_area_I30_Y_0 : in std_logic; - ADD_8x8_medium_area_I29_Y_0 : in std_logic; - ADD_8x8_medium_area_I28_Y_0 : in std_logic; - ADD_8x8_medium_area_I27_Y_0 : in std_logic; - ADD_8x8_medium_area_I26_Y_0 : in std_logic; - ADD_8x8_medium_area_I25_Y_0 : in std_logic; - ADD_8x8_medium_area_I24_Y_0 : in std_logic; - ADD_8x8_medium_area_I0_S_0 : in std_logic; - ram_write : in std_logic; - lclk_c : in std_logic - ); - -end generic_syncram_2p; - -architecture DEF_ARCH of generic_syncram_2p is - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component RAM512X18 - generic (MEMORYFILE:string := ""); - - port( RADDR8 : in std_logic := 'U'; - RADDR7 : in std_logic := 'U'; - RADDR6 : in std_logic := 'U'; - RADDR5 : in std_logic := 'U'; - RADDR4 : in std_logic := 'U'; - RADDR3 : in std_logic := 'U'; - RADDR2 : in std_logic := 'U'; - RADDR1 : in std_logic := 'U'; - RADDR0 : in std_logic := 'U'; - WADDR8 : in std_logic := 'U'; - WADDR7 : in std_logic := 'U'; - WADDR6 : in std_logic := 'U'; - WADDR5 : in std_logic := 'U'; - WADDR4 : in std_logic := 'U'; - WADDR3 : in std_logic := 'U'; - WADDR2 : in std_logic := 'U'; - WADDR1 : in std_logic := 'U'; - WADDR0 : in std_logic := 'U'; - WD17 : in std_logic := 'U'; - WD16 : in std_logic := 'U'; - WD15 : in std_logic := 'U'; - WD14 : in std_logic := 'U'; - WD13 : in std_logic := 'U'; - WD12 : in std_logic := 'U'; - WD11 : in std_logic := 'U'; - WD10 : in std_logic := 'U'; - WD9 : in std_logic := 'U'; - WD8 : in std_logic := 'U'; - WD7 : in std_logic := 'U'; - WD6 : in std_logic := 'U'; - WD5 : in std_logic := 'U'; - WD4 : in std_logic := 'U'; - WD3 : in std_logic := 'U'; - WD2 : in std_logic := 'U'; - WD1 : in std_logic := 'U'; - WD0 : in std_logic := 'U'; - RW0 : in std_logic := 'U'; - RW1 : in std_logic := 'U'; - WW0 : in std_logic := 'U'; - WW1 : in std_logic := 'U'; - PIPE : in std_logic := 'U'; - REN : in std_logic := 'U'; - WEN : in std_logic := 'U'; - RCLK : in std_logic := 'U'; - WCLK : in std_logic := 'U'; - RESET : in std_logic := 'U'; - RD17 : out std_logic; - RD16 : out std_logic; - RD15 : out std_logic; - RD14 : out std_logic; - RD13 : out std_logic; - RD12 : out std_logic; - RD11 : out std_logic; - RD10 : out std_logic; - RD9 : out std_logic; - RD8 : out std_logic; - RD7 : out std_logic; - RD6 : out std_logic; - RD5 : out std_logic; - RD4 : out std_logic; - RD3 : out std_logic; - RD2 : out std_logic; - RD1 : out std_logic; - RD0 : out std_logic - ); - end component; - - signal I_5_5, I_4_2_i_0, I_4_1_i_0, I_5_2, I_5_4, - \RADDR_REG1[7]\, \WADDR_REG1[7]\, I_5_0, I_5_3, - \RADDR_REG1[5]\, \WADDR_REG1[5]\, I_4_6_i_0, - \RADDR_REG1[3]\, \WADDR_REG1[3]\, I_4_4_i_0, - \RADDR_REG1[0]\, \WADDR_REG1[0]\, N_5, N_7, - \WADDR_REG1[1]\, \RADDR_REG1[1]\, \WADDR_REG1[2]\, - \RADDR_REG1[2]\, \WADDR_REG1[4]\, \RADDR_REG1[4]\, - \WADDR_REG1[6]\, \RADDR_REG1[6]\, \DOUT_TMP[0]\, - \DIN_REG1[0]\, \DOUT_TMP[3]\, \DIN_REG1[3]\, - \DOUT_TMP[4]\, \DIN_REG1[4]\, \DOUT_TMP[5]\, - \DIN_REG1[5]\, \DOUT_TMP[6]\, \DIN_REG1[6]\, - \DOUT_TMP[7]\, \DIN_REG1[7]\, \DOUT_TMP[8]\, - \DIN_REG1[8]\, \DOUT_TMP[9]\, \DIN_REG1[9]\, - \DOUT_TMP[10]\, \DIN_REG1[10]\, \DOUT_TMP[11]\, - \DIN_REG1[11]\, \DOUT_TMP[12]\, \DIN_REG1[12]\, - \DOUT_TMP[13]\, \DIN_REG1[13]\, \DOUT_TMP[14]\, - \DIN_REG1[14]\, \DOUT_TMP[15]\, \DIN_REG1[15]\, - \DOUT_TMP[16]\, \DIN_REG1[16]\, \DOUT_TMP[17]\, - \DIN_REG1[17]\, \DOUT_TMP[2]\, \DIN_REG1[2]\, - \DOUT_TMP[1]\, \DIN_REG1[1]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \rfd_tile_DIN_REG1[9]\ : DFN1 - port map(D => ram_input(9), CLK => lclk_c, Q => - \DIN_REG1[9]\); - - \rfd_tile_RADDR_REG1[5]\ : DFN1 - port map(D => counter(5), CLK => lclk_c, Q => - \RADDR_REG1[5]\); - - \rfd_tile_WADDR_REG1[6]\ : DFN1 - port map(D => ADD_8x8_medium_area_I29_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[6]\); - - rfd_tile_I_3 : DFN1 - port map(D => ram_write, CLK => lclk_c, Q => N_5); - - \rfd_tile_DIN_REG1_RNI7EOE2[2]\ : MX2 - port map(A => \DOUT_TMP[2]\, B => \DIN_REG1[2]\, S => N_7, - Y => ram_output(2)); - - \rfd_tile_DIN_REG1[10]\ : DFN1 - port map(D => ram_input(10), CLK => lclk_c, Q => - \DIN_REG1[10]\); - - \rfd_tile_WADDR_REG1_RNIGU611[1]\ : NOR3C - port map(A => I_4_2_i_0, B => I_4_1_i_0, C => I_5_2, Y => - I_5_5); - - \rfd_tile_WADDR_REG1[4]\ : DFN1 - port map(D => ADD_8x8_medium_area_I27_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[4]\); - - \rfd_tile_WADDR_REG1_RNIJN98[2]\ : XNOR2 - port map(A => \WADDR_REG1[2]\, B => \RADDR_REG1[2]\, Y => - I_4_2_i_0); - - rfd_tile_I_1_RNINVIJ2 : MX2 - port map(A => \DOUT_TMP[11]\, B => \DIN_REG1[11]\, S => N_7, - Y => ram_output(11)); - - VCC_i : VCC - port map(Y => \VCC\); - - \rfd_tile_DIN_REG1_RNIBEOE2[6]\ : MX2 - port map(A => \DOUT_TMP[6]\, B => \DIN_REG1[6]\, S => N_7, - Y => ram_output(6)); - - \rfd_tile_DIN_REG1_RNIEEOE2[9]\ : MX2 - port map(A => \DOUT_TMP[9]\, B => \DIN_REG1[9]\, S => N_7, - Y => ram_output(9)); - - \rfd_tile_DIN_REG1[0]\ : DFN1 - port map(D => ram_input(0), CLK => lclk_c, Q => - \DIN_REG1[0]\); - - \rfd_tile_DIN_REG1[5]\ : DFN1 - port map(D => ram_input(5), CLK => lclk_c, Q => - \DIN_REG1[5]\); - - \rfd_tile_WADDR_REG1_RNICFJG[3]\ : XA1A - port map(A => \RADDR_REG1[3]\, B => \WADDR_REG1[3]\, C => - I_4_4_i_0, Y => I_5_2); - - \rfd_tile_DIN_REG1[4]\ : DFN1 - port map(D => ram_input(4), CLK => lclk_c, Q => - \DIN_REG1[4]\); - - \rfd_tile_DIN_REG1[3]\ : DFN1 - port map(D => ram_input(3), CLK => lclk_c, Q => - \DIN_REG1[3]\); - - \rfd_tile_DIN_REG1[2]\ : DFN1 - port map(D => ram_input(2), CLK => lclk_c, Q => - \DIN_REG1[2]\); - - \rfd_tile_DIN_REG1_RNICEOE2[7]\ : MX2 - port map(A => \DOUT_TMP[7]\, B => \DIN_REG1[7]\, S => N_7, - Y => ram_output(7)); - - \rfd_tile_DIN_REG1[12]\ : DFN1 - port map(D => ram_input(12), CLK => lclk_c, Q => - \DIN_REG1[12]\); - - \rfd_tile_WADDR_REG1[7]\ : DFN1 - port map(D => ADD_8x8_medium_area_I30_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[7]\); - - rfd_tile_I_1_RNIO3JJ2 : MX2 - port map(A => \DOUT_TMP[12]\, B => \DIN_REG1[12]\, S => N_7, - Y => ram_output(12)); - - rfd_tile_I_1_RNIMRIJ2 : MX2 - port map(A => \DOUT_TMP[10]\, B => \DIN_REG1[10]\, S => N_7, - Y => ram_output(10)); - - \rfd_tile_WADDR_REG1_RNINN98[4]\ : XNOR2 - port map(A => \WADDR_REG1[4]\, B => \RADDR_REG1[4]\, Y => - I_4_4_i_0); - - \rfd_tile_DIN_REG1[15]\ : DFN1 - port map(D => ram_input(15), CLK => lclk_c, Q => - \DIN_REG1[15]\); - - \rfd_tile_RADDR_REG1[0]\ : DFN1 - port map(D => counter(0), CLK => lclk_c, Q => - \RADDR_REG1[0]\); - - rfd_tile_I_1_RNIRFJJ2 : MX2 - port map(A => \DOUT_TMP[15]\, B => \DIN_REG1[15]\, S => N_7, - Y => ram_output(15)); - - \rfd_tile_DIN_REG1_RNI8EOE2[3]\ : MX2 - port map(A => \DOUT_TMP[3]\, B => \DIN_REG1[3]\, S => N_7, - Y => ram_output(3)); - - \rfd_tile_WADDR_REG1_RNIVTTL[7]\ : XA1A - port map(A => \RADDR_REG1[7]\, B => \WADDR_REG1[7]\, C => - I_5_0, Y => I_5_4); - - \rfd_tile_WADDR_REG1[5]\ : DFN1 - port map(D => ADD_8x8_medium_area_I28_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[5]\); - - rfd_tile_I_1_RNITNJJ2 : MX2 - port map(A => \DOUT_TMP[17]\, B => \DIN_REG1[17]\, S => N_7, - Y => ram_output(17)); - - \rfd_tile_DIN_REG1_RNI5EOE2[0]\ : MX2 - port map(A => \DOUT_TMP[0]\, B => \DIN_REG1[0]\, S => N_7, - Y => ram_output(0)); - - \rfd_tile_RADDR_REG1[2]\ : DFN1 - port map(D => counter(2), CLK => lclk_c, Q => - \RADDR_REG1[2]\); - - \rfd_tile_DIN_REG1[1]\ : DFN1 - port map(D => ram_input(1), CLK => lclk_c, Q => - \DIN_REG1[1]\); - - \rfd_tile_RADDR_REG1[3]\ : DFN1 - port map(D => counter(3), CLK => lclk_c, Q => - \RADDR_REG1[3]\); - - \rfd_tile_WADDR_REG1_RNIHN98[1]\ : XNOR2 - port map(A => \WADDR_REG1[1]\, B => \RADDR_REG1[1]\, Y => - I_4_1_i_0); - - \rfd_tile_DIN_REG1_RNIAEOE2[5]\ : MX2 - port map(A => \DOUT_TMP[5]\, B => \DIN_REG1[5]\, S => N_7, - Y => ram_output(5)); - - GND_i : GND - port map(Y => \GND\); - - \rfd_tile_RADDR_REG1[1]\ : DFN1 - port map(D => counter(1), CLK => lclk_c, Q => - \RADDR_REG1[1]\); - - \rfd_tile_DIN_REG1[14]\ : DFN1 - port map(D => ram_input(14), CLK => lclk_c, Q => - \DIN_REG1[14]\); - - rfd_tile_I_1_RNIP7JJ2 : MX2 - port map(A => \DOUT_TMP[13]\, B => \DIN_REG1[13]\, S => N_7, - Y => ram_output(13)); - - \rfd_tile_DIN_REG1_RNI6EOE2[1]\ : MX2 - port map(A => \DOUT_TMP[1]\, B => \DIN_REG1[1]\, S => N_7, - Y => ram_output(1)); - - \rfd_tile_RADDR_REG1[6]\ : DFN1 - port map(D => counter(6), CLK => lclk_c, Q => - \RADDR_REG1[6]\); - - \rfd_tile_DIN_REG1_RNIDEOE2[8]\ : MX2 - port map(A => \DOUT_TMP[8]\, B => \DIN_REG1[8]\, S => N_7, - Y => ram_output(8)); - - \rfd_tile_WADDR_REG1_RNIRN98[6]\ : XNOR2 - port map(A => \WADDR_REG1[6]\, B => \RADDR_REG1[6]\, Y => - I_4_6_i_0); - - \rfd_tile_DIN_REG1_RNI9EOE2[4]\ : MX2 - port map(A => \DOUT_TMP[4]\, B => \DIN_REG1[4]\, S => N_7, - Y => ram_output(4)); - - \rfd_tile_DIN_REG1[8]\ : DFN1 - port map(D => ram_input(8), CLK => lclk_c, Q => - \DIN_REG1[8]\); - - \rfd_tile_WADDR_REG1_RNIKFJG[5]\ : XA1A - port map(A => \RADDR_REG1[5]\, B => \WADDR_REG1[5]\, C => - I_4_6_i_0, Y => I_5_3); - - \rfd_tile_WADDR_REG1[0]\ : DFN1 - port map(D => ADD_8x8_medium_area_I0_S_0, CLK => lclk_c, Q - => \WADDR_REG1[0]\); - - \rfd_tile_RADDR_REG1[4]\ : DFN1 - port map(D => counter(4), CLK => lclk_c, Q => - \RADDR_REG1[4]\); - - \rfd_tile_DIN_REG1[6]\ : DFN1 - port map(D => ram_input(6), CLK => lclk_c, Q => - \DIN_REG1[6]\); - - \rfd_tile_WADDR_REG1[2]\ : DFN1 - port map(D => ADD_8x8_medium_area_I25_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[2]\); - - \rfd_tile_DIN_REG1[11]\ : DFN1 - port map(D => ram_input(11), CLK => lclk_c, Q => - \DIN_REG1[11]\); - - \rfd_tile_WADDR_REG1[3]\ : DFN1 - port map(D => ADD_8x8_medium_area_I26_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[3]\); - - rfd_tile_I_1_RNIQBJJ2 : MX2 - port map(A => \DOUT_TMP[14]\, B => \DIN_REG1[14]\, S => N_7, - Y => ram_output(14)); - - \rfd_tile_DIN_REG1[13]\ : DFN1 - port map(D => ram_input(13), CLK => lclk_c, Q => - \DIN_REG1[13]\); - - \rfd_tile_WADDR_REG1_RNI26KD[0]\ : XA1A - port map(A => \RADDR_REG1[0]\, B => \WADDR_REG1[0]\, C => - N_5, Y => I_5_0); - - rfd_tile_I_1_RNISJJJ2 : MX2 - port map(A => \DOUT_TMP[16]\, B => \DIN_REG1[16]\, S => N_7, - Y => ram_output(16)); - - rfd_tile_I_1 : RAM512X18 - port map(RADDR8 => generic_syncram_2p_GND, RADDR7 => - counter(7), RADDR6 => counter(6), RADDR5 => counter(5), - RADDR4 => counter(4), RADDR3 => counter(3), RADDR2 => - counter(2), RADDR1 => counter(1), RADDR0 => counter(0), - WADDR8 => generic_syncram_2p_GND, WADDR7 => - ADD_8x8_medium_area_I30_Y_0, WADDR6 => - ADD_8x8_medium_area_I29_Y_0, WADDR5 => - ADD_8x8_medium_area_I28_Y_0, WADDR4 => - ADD_8x8_medium_area_I27_Y_0, WADDR3 => - ADD_8x8_medium_area_I26_Y_0, WADDR2 => - ADD_8x8_medium_area_I25_Y_0, WADDR1 => - ADD_8x8_medium_area_I24_Y_0, WADDR0 => - ADD_8x8_medium_area_I0_S_0, WD17 => ram_input(17), WD16 - => ram_input(16), WD15 => ram_input(15), WD14 => - ram_input(14), WD13 => ram_input(13), WD12 => - ram_input(12), WD11 => ram_input(11), WD10 => - ram_input(10), WD9 => ram_input(9), WD8 => ram_input(8), - WD7 => ram_input(7), WD6 => ram_input(6), WD5 => - ram_input(5), WD4 => ram_input(4), WD3 => ram_input(3), - WD2 => ram_input(2), WD1 => ram_input(1), WD0 => - ram_input(0), RW0 => generic_syncram_2p_GND, RW1 => - generic_syncram_2p_VCC, WW0 => generic_syncram_2p_GND, - WW1 => generic_syncram_2p_VCC, PIPE => - generic_syncram_2p_GND, REN => generic_syncram_2p_GND, - WEN => ram_write_i, RCLK => lclk_c, WCLK => lclk_c, RESET - => generic_syncram_2p_VCC, RD17 => \DOUT_TMP[17]\, RD16 - => \DOUT_TMP[16]\, RD15 => \DOUT_TMP[15]\, RD14 => - \DOUT_TMP[14]\, RD13 => \DOUT_TMP[13]\, RD12 => - \DOUT_TMP[12]\, RD11 => \DOUT_TMP[11]\, RD10 => - \DOUT_TMP[10]\, RD9 => \DOUT_TMP[9]\, RD8 => - \DOUT_TMP[8]\, RD7 => \DOUT_TMP[7]\, RD6 => \DOUT_TMP[6]\, - RD5 => \DOUT_TMP[5]\, RD4 => \DOUT_TMP[4]\, RD3 => - \DOUT_TMP[3]\, RD2 => \DOUT_TMP[2]\, RD1 => \DOUT_TMP[1]\, - RD0 => \DOUT_TMP[0]\); - - \rfd_tile_RADDR_REG1[7]\ : DFN1 - port map(D => counter(7), CLK => lclk_c, Q => - \RADDR_REG1[7]\); - - \rfd_tile_DIN_REG1[16]\ : DFN1 - port map(D => ram_input(16), CLK => lclk_c, Q => - \DIN_REG1[16]\); - - \rfd_tile_WADDR_REG1[1]\ : DFN1 - port map(D => ADD_8x8_medium_area_I24_Y_0, CLK => lclk_c, Q - => \WADDR_REG1[1]\); - - \rfd_tile_DIN_REG1[17]\ : DFN1 - port map(D => ram_input(17), CLK => lclk_c, Q => - \DIN_REG1[17]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \rfd_tile_WADDR_REG1_RNI3CO72[5]\ : NOR3C - port map(A => I_5_4, B => I_5_3, C => I_5_5, Y => N_7); - - \rfd_tile_DIN_REG1[7]\ : DFN1 - port map(D => ram_input(7), CLK => lclk_c, Q => - \DIN_REG1[7]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ1 is - - port( ram_output : out std_logic_vector(17 downto 0); - counter : in std_logic_vector(7 downto 0); - ram_input : in std_logic_vector(17 downto 0); - lclk_c : in std_logic; - ram_write : in std_logic; - ADD_8x8_medium_area_I0_S_0 : in std_logic; - ADD_8x8_medium_area_I24_Y_0 : in std_logic; - ADD_8x8_medium_area_I25_Y_0 : in std_logic; - ADD_8x8_medium_area_I26_Y_0 : in std_logic; - ADD_8x8_medium_area_I27_Y_0 : in std_logic; - ADD_8x8_medium_area_I28_Y_0 : in std_logic; - ADD_8x8_medium_area_I29_Y_0 : in std_logic; - ADD_8x8_medium_area_I30_Y_0 : in std_logic; - syncram_2pZ1_GND : in std_logic; - syncram_2pZ1_VCC : in std_logic; - ram_write_i : in std_logic - ); - -end syncram_2pZ1; - -architecture DEF_ARCH of syncram_2pZ1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component generic_syncram_2p - port( ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - counter : in std_logic_vector(7 downto 0) := (others => 'U'); - ram_output : out std_logic_vector(17 downto 0); - ram_write_i : in std_logic := 'U'; - generic_syncram_2p_VCC : in std_logic := 'U'; - generic_syncram_2p_GND : in std_logic := 'U'; - ADD_8x8_medium_area_I30_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I29_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I28_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I27_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I26_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I25_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I24_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I0_S_0 : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : generic_syncram_2p - Use entity work.generic_syncram_2p(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \inf.x0\ : generic_syncram_2p - port map(ram_input(17) => ram_input(17), ram_input(16) => - ram_input(16), ram_input(15) => ram_input(15), - ram_input(14) => ram_input(14), ram_input(13) => - ram_input(13), ram_input(12) => ram_input(12), - ram_input(11) => ram_input(11), ram_input(10) => - ram_input(10), ram_input(9) => ram_input(9), ram_input(8) - => ram_input(8), ram_input(7) => ram_input(7), - ram_input(6) => ram_input(6), ram_input(5) => - ram_input(5), ram_input(4) => ram_input(4), ram_input(3) - => ram_input(3), ram_input(2) => ram_input(2), - ram_input(1) => ram_input(1), ram_input(0) => - ram_input(0), counter(7) => counter(7), counter(6) => - counter(6), counter(5) => counter(5), counter(4) => - counter(4), counter(3) => counter(3), counter(2) => - counter(2), counter(1) => counter(1), counter(0) => - counter(0), ram_output(17) => ram_output(17), - ram_output(16) => ram_output(16), ram_output(15) => - ram_output(15), ram_output(14) => ram_output(14), - ram_output(13) => ram_output(13), ram_output(12) => - ram_output(12), ram_output(11) => ram_output(11), - ram_output(10) => ram_output(10), ram_output(9) => - ram_output(9), ram_output(8) => ram_output(8), - ram_output(7) => ram_output(7), ram_output(6) => - ram_output(6), ram_output(5) => ram_output(5), - ram_output(4) => ram_output(4), ram_output(3) => - ram_output(3), ram_output(2) => ram_output(2), - ram_output(1) => ram_output(1), ram_output(0) => - ram_output(0), ram_write_i => ram_write_i, - generic_syncram_2p_VCC => syncram_2pZ1_VCC, - generic_syncram_2p_GND => syncram_2pZ1_GND, - ADD_8x8_medium_area_I30_Y_0 => - ADD_8x8_medium_area_I30_Y_0, ADD_8x8_medium_area_I29_Y_0 - => ADD_8x8_medium_area_I29_Y_0, - ADD_8x8_medium_area_I28_Y_0 => - ADD_8x8_medium_area_I28_Y_0, ADD_8x8_medium_area_I27_Y_0 - => ADD_8x8_medium_area_I27_Y_0, - ADD_8x8_medium_area_I26_Y_0 => - ADD_8x8_medium_area_I26_Y_0, ADD_8x8_medium_area_I25_Y_0 - => ADD_8x8_medium_area_I25_Y_0, - ADD_8x8_medium_area_I24_Y_0 => - ADD_8x8_medium_area_I24_Y_0, ADD_8x8_medium_area_I0_S_0 - => ADD_8x8_medium_area_I0_S_0, ram_write => ram_write, - lclk_c => lclk_c); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity RAM_CTRLR_v2 is - - port( ram_input : in std_logic_vector(17 downto 0); - ram_output : out std_logic_vector(17 downto 0); - waddr_previous : in std_logic_vector(1 downto 0); - ram_write_i : in std_logic; - RAM_CTRLR_v2_VCC : in std_logic; - RAM_CTRLR_v2_GND : in std_logic; - ram_write : in std_logic; - raddr_add1 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - raddr_rst : in std_logic - ); - -end RAM_CTRLR_v2; - -architecture DEF_ARCH of RAM_CTRLR_v2 is - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component syncram_2pZ1 - port( ram_output : out std_logic_vector(17 downto 0); - counter : in std_logic_vector(7 downto 0) := (others => 'U'); - ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - lclk_c : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - ADD_8x8_medium_area_I0_S_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I24_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I25_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I26_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I27_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I28_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I29_Y_0 : in std_logic := 'U'; - ADD_8x8_medium_area_I30_Y_0 : in std_logic := 'U'; - syncram_2pZ1_GND : in std_logic := 'U'; - syncram_2pZ1_VCC : in std_logic := 'U'; - ram_write_i : in std_logic := 'U' - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_TMP[0]\, \counter[1]_net_1\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, \counter[4]_net_1\, - \DWACT_ADD_CI_0_g_array_12[0]\, \counter[2]_net_1\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, \counter[6]_net_1\, - ADD_8x8_medium_area_I20_Y_0, \counter[5]_net_1\, N_5_i, - ADD_8x8_medium_area_I20_un1_Y_0, - ADD_8x8_medium_area_I13_Y_0, \counter[3]_net_1\, - ADD_8x8_medium_area_I13_un1_Y_0, N145_i, N135_i, N147, - ADD_8x8_medium_area_I24_Y_0, N116, - ADD_8x8_medium_area_I25_Y_0, ADD_8x8_medium_area_I27_Y_0, - ADD_8x8_medium_area_I30_Y_0, \counter[7]_net_1\, N149, - ADD_8x8_medium_area_I29_Y_0, \counter[0]_net_1\, N120, - N124, ADD_8x8_medium_area_I0_S_0, - ADD_8x8_medium_area_I26_Y_0, N121, - ADD_8x8_medium_area_I28_Y_0, N125, \counter_3[7]\, I_34, - \counter_3[6]\, I_30, \counter_3[5]\, I_33, - \counter_3[4]\, I_28, \counter_3[3]\, I_31_9, - \counter_3[2]\, I_32, \counter_3[1]\, I_27, - \counter_3[0]\, \DWACT_ADD_CI_0_partial_sum[0]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : syncram_2pZ1 - Use entity work.syncram_2pZ1(DEF_ARCH); -begin - - - un1_counter_1_ADD_8x8_medium_area_I20_Y_0 : OAI1 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - C => N_5_i, Y => ADD_8x8_medium_area_I20_Y_0); - - un1_counter_I_45 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => - \counter[6]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_2[0]\); - - un1_counter_I_31 : XOR2 - port map(A => \counter[3]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_31_9); - - un1_counter_I_36 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - un1_counter_1_ADD_8x8_medium_area_I12_Y : MX2B - port map(A => N116, B => N_5_i, S => \counter[1]_net_1\, Y - => N135_i); - - un1_counter_1_ADD_8x8_medium_area_I13_Y_0 : OAI1 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - C => N_5_i, Y => ADD_8x8_medium_area_I13_Y_0); - - un1_counter_I_44 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \counter[2]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12[0]\); - - \counter[2]\ : DFN1C0 - port map(D => \counter_3[2]\, CLK => lclk_c, CLR => rstn, Q - => \counter[2]_net_1\); - - \counter[7]\ : DFN1C0 - port map(D => \counter_3[7]\, CLK => lclk_c, CLR => rstn, Q - => \counter[7]_net_1\); - - un1_counter_1_ADD_8x8_medium_area_I29_Y_0 : XOR3 - port map(A => N_5_i, B => \counter[6]_net_1\, C => N147, Y - => ADD_8x8_medium_area_I29_Y_0); - - un1_counter_I_48 : AND2 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - Y => \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - un1_counter_1_ADD_8x8_medium_area_I20_Y : OAI1 - port map(A => N145_i, B => ADD_8x8_medium_area_I20_un1_Y_0, - C => ADD_8x8_medium_area_I20_Y_0, Y => N147); - - \counter_RNO[0]\ : NOR2A - port map(A => \DWACT_ADD_CI_0_partial_sum[0]\, B => - raddr_rst, Y => \counter_3[0]\); - - \counter[6]\ : DFN1C0 - port map(D => \counter_3[6]\, CLK => lclk_c, CLR => rstn, Q - => \counter[6]_net_1\); - - \counter_RNO[4]\ : NOR2A - port map(A => I_28, B => raddr_rst, Y => \counter_3[4]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \memRAM.SRAM\ : syncram_2pZ1 - port map(ram_output(17) => ram_output(17), ram_output(16) - => ram_output(16), ram_output(15) => ram_output(15), - ram_output(14) => ram_output(14), ram_output(13) => - ram_output(13), ram_output(12) => ram_output(12), - ram_output(11) => ram_output(11), ram_output(10) => - ram_output(10), ram_output(9) => ram_output(9), - ram_output(8) => ram_output(8), ram_output(7) => - ram_output(7), ram_output(6) => ram_output(6), - ram_output(5) => ram_output(5), ram_output(4) => - ram_output(4), ram_output(3) => ram_output(3), - ram_output(2) => ram_output(2), ram_output(1) => - ram_output(1), ram_output(0) => ram_output(0), counter(7) - => \counter[7]_net_1\, counter(6) => \counter[6]_net_1\, - counter(5) => \counter[5]_net_1\, counter(4) => - \counter[4]_net_1\, counter(3) => \counter[3]_net_1\, - counter(2) => \counter[2]_net_1\, counter(1) => - \counter[1]_net_1\, counter(0) => \counter[0]_net_1\, - ram_input(17) => ram_input(17), ram_input(16) => - ram_input(16), ram_input(15) => ram_input(15), - ram_input(14) => ram_input(14), ram_input(13) => - ram_input(13), ram_input(12) => ram_input(12), - ram_input(11) => ram_input(11), ram_input(10) => - ram_input(10), ram_input(9) => ram_input(9), ram_input(8) - => ram_input(8), ram_input(7) => ram_input(7), - ram_input(6) => ram_input(6), ram_input(5) => - ram_input(5), ram_input(4) => ram_input(4), ram_input(3) - => ram_input(3), ram_input(2) => ram_input(2), - ram_input(1) => ram_input(1), ram_input(0) => - ram_input(0), lclk_c => lclk_c, ram_write => ram_write, - ADD_8x8_medium_area_I0_S_0 => ADD_8x8_medium_area_I0_S_0, - ADD_8x8_medium_area_I24_Y_0 => - ADD_8x8_medium_area_I24_Y_0, ADD_8x8_medium_area_I25_Y_0 - => ADD_8x8_medium_area_I25_Y_0, - ADD_8x8_medium_area_I26_Y_0 => - ADD_8x8_medium_area_I26_Y_0, ADD_8x8_medium_area_I27_Y_0 - => ADD_8x8_medium_area_I27_Y_0, - ADD_8x8_medium_area_I28_Y_0 => - ADD_8x8_medium_area_I28_Y_0, ADD_8x8_medium_area_I29_Y_0 - => ADD_8x8_medium_area_I29_Y_0, - ADD_8x8_medium_area_I30_Y_0 => - ADD_8x8_medium_area_I30_Y_0, syncram_2pZ1_GND => - RAM_CTRLR_v2_GND, syncram_2pZ1_VCC => RAM_CTRLR_v2_VCC, - ram_write_i => ram_write_i); - - un1_counter_1_ADD_8x8_medium_area_I26_Y_0 : AX1E - port map(A => N120, B => N135_i, C => N121, Y => - ADD_8x8_medium_area_I26_Y_0); - - \counter_RNO[1]\ : NOR2A - port map(A => I_27, B => raddr_rst, Y => \counter_3[1]\); - - un1_counter_1_ADD_8x8_medium_area_I0_CO1 : OR3B - port map(A => waddr_previous(0), B => \counter[0]_net_1\, C - => waddr_previous(1), Y => N116); - - \un2_waddr_0_x2[6]\ : XOR2 - port map(A => waddr_previous(1), B => waddr_previous(0), Y - => N_5_i); - - un1_counter_1_ADD_8x8_medium_area_I4_CO1 : OR2B - port map(A => \counter[4]_net_1\, B => N_5_i, Y => N124); - - un1_counter_I_28 : XOR2 - port map(A => \counter[4]_net_1\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_28); - - un1_counter_1_ADD_8x8_medium_area_I3_S_0 : XOR2 - port map(A => \counter[3]_net_1\, B => N_5_i, Y => N121); - - un1_counter_1_ADD_8x8_medium_area_I25_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[2]_net_1\, C => N135_i, - Y => ADD_8x8_medium_area_I25_Y_0); - - un1_counter_I_42 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \counter[4]_net_1\, Y => \DWACT_ADD_CI_0_g_array_12_1[0]\); - - un1_counter_1_ADD_8x8_medium_area_I30_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[7]_net_1\, C => N149, Y - => ADD_8x8_medium_area_I30_Y_0); - - un1_counter_I_35 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => - \counter[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1[0]\); - - \counter[4]\ : DFN1C0 - port map(D => \counter_3[4]\, CLK => lclk_c, CLR => rstn, Q - => \counter[4]_net_1\); - - un1_counter_1_ADD_8x8_medium_area_I20_un1_Y_0 : OR2 - port map(A => \counter[4]_net_1\, B => \counter[5]_net_1\, - Y => ADD_8x8_medium_area_I20_un1_Y_0); - - \counter[5]\ : DFN1C0 - port map(D => \counter_3[5]\, CLK => lclk_c, CLR => rstn, Q - => \counter[5]_net_1\); - - un1_counter_I_34 : XOR2 - port map(A => \counter[7]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => I_34); - - un1_counter_1_ADD_8x8_medium_area_I21_Y : MX2C - port map(A => N147, B => N_5_i, S => \counter[6]_net_1\, Y - => N149); - - \counter_RNO[2]\ : NOR2A - port map(A => I_32, B => raddr_rst, Y => \counter_3[2]\); - - GND_i : GND - port map(Y => \GND\); - - un1_counter_I_30 : XOR2 - port map(A => \counter[6]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_30); - - \counter_RNO[5]\ : NOR2A - port map(A => I_33, B => raddr_rst, Y => \counter_3[5]\); - - \counter_RNO[3]\ : NOR2A - port map(A => I_31_9, B => raddr_rst, Y => \counter_3[3]\); - - un1_counter_1_ADD_8x8_medium_area_I13_un1_Y_0 : OR2 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - Y => ADD_8x8_medium_area_I13_un1_Y_0); - - \counter[1]\ : DFN1C0 - port map(D => \counter_3[1]\, CLK => lclk_c, CLR => rstn, Q - => \counter[1]_net_1\); - - \counter[3]\ : DFN1C0 - port map(D => \counter_3[3]\, CLK => lclk_c, CLR => rstn, Q - => \counter[3]_net_1\); - - un1_counter_I_39 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - un1_counter_1_ADD_8x8_medium_area_I0_S_0 : AX1 - port map(A => waddr_previous(1), B => waddr_previous(0), C - => \counter[0]_net_1\, Y => ADD_8x8_medium_area_I0_S_0); - - un1_counter_I_47 : AND2 - port map(A => \counter[2]_net_1\, B => \counter[3]_net_1\, - Y => \DWACT_ADD_CI_0_pog_array_1[0]\); - - un1_counter_I_19 : XOR2 - port map(A => \counter[0]_net_1\, B => raddr_add1, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \counter_RNO[6]\ : NOR2A - port map(A => I_30, B => raddr_rst, Y => \counter_3[6]\); - - un1_counter_I_1 : AND2 - port map(A => \counter[0]_net_1\, B => raddr_add1, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - un1_counter_1_ADD_8x8_medium_area_I5_S_0 : XOR2 - port map(A => \counter[5]_net_1\, B => N_5_i, Y => N125); - - un1_counter_1_ADD_8x8_medium_area_I13_Y : OA1 - port map(A => N135_i, B => ADD_8x8_medium_area_I13_un1_Y_0, - C => ADD_8x8_medium_area_I13_Y_0, Y => N145_i); - - un1_counter_I_33 : XOR2 - port map(A => \counter[5]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_33); - - un1_counter_I_32 : XOR2 - port map(A => \counter[2]_net_1\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_32); - - un1_counter_I_27 : XOR2 - port map(A => \counter[1]_net_1\, B => - \DWACT_ADD_CI_0_TMP[0]\, Y => I_27); - - un1_counter_1_ADD_8x8_medium_area_I27_Y_0 : XNOR3 - port map(A => N_5_i, B => \counter[4]_net_1\, C => N145_i, - Y => ADD_8x8_medium_area_I27_Y_0); - - un1_counter_1_ADD_8x8_medium_area_I28_Y_0 : AX1E - port map(A => N124, B => N145_i, C => N125, Y => - ADD_8x8_medium_area_I28_Y_0); - - un1_counter_1_ADD_8x8_medium_area_I24_Y_0 : XNOR3 - port map(A => N116, B => \counter[1]_net_1\, C => N_5_i, Y - => ADD_8x8_medium_area_I24_Y_0); - - \counter_RNO[7]\ : NOR2A - port map(A => I_34, B => raddr_rst, Y => \counter_3[7]\); - - un1_counter_1_ADD_8x8_medium_area_I2_CO1 : OR2B - port map(A => \counter[2]_net_1\, B => N_5_i, Y => N120); - - \counter[0]\ : DFN1C0 - port map(D => \counter_3[0]\, CLK => lclk_c, CLR => rstn, Q - => \counter[0]_net_1\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2_DATAFLOW is - - port( alu_ctrl : in std_logic_vector(2 downto 0); - alu_sel_coeff_0_2 : in std_logic; - alu_sel_coeff_0_0 : in std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0); - S_0 : out std_logic; - S_36 : out std_logic; - waddr_previous : in std_logic_vector(1 downto 0); - sample_0 : in std_logic_vector(14 downto 0); - sample_in_buf : in std_logic_vector(143 downto 129); - ram_sel_Wdata : in std_logic_vector(1 downto 0); - sample_out_s_1 : out std_logic; - sample_out_s_2 : out std_logic; - sample_out_s_0 : out std_logic; - sample_out_s_3 : out std_logic; - sample_out_s_15 : out std_logic; - sample_out_s_14 : out std_logic; - sample_out_s_13 : out std_logic; - sample_out_s_12 : out std_logic; - sample_out_s_11 : out std_logic; - sample_out_s_10 : out std_logic; - sample_out_s_9 : out std_logic; - sample_out_s_8 : out std_logic; - sample_out_s_7 : out std_logic; - sample_out_s_6 : out std_logic; - sample_out_s_5 : out std_logic; - sample_out_s_4 : out std_logic; - sample_in_s_1 : in std_logic_vector(17 to 17); - in_sel_src : in std_logic_vector(1 downto 0); - raddr_rst : in std_logic; - raddr_add1 : in std_logic; - ram_write : in std_logic; - IIR_CEL_CTRLR_v2_DATAFLOW_GND : in std_logic; - IIR_CEL_CTRLR_v2_DATAFLOW_VCC : in std_logic; - ram_write_i : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_val_delay_5 : in std_logic; - sample_val_delay_1 : in std_logic; - sample_val_delay_0 : in std_logic; - alu_sel_input : in std_logic - ); - -end IIR_CEL_CTRLR_v2_DATAFLOW; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2_DATAFLOW is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component MUXN_9_5 - port( S_36 : out std_logic; - S_0 : out std_logic; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_coef_s : out std_logic_vector(8 downto 0) - ); - end component; - - component ALU - port( alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - alu_coef_s : in std_logic_vector(8 downto 0) := (others => 'U'); - alu_sample : in std_logic_vector(17 downto 0) := (others => 'U'); - sample_out_s : out std_logic_vector(17 downto 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component RAM_CTRLR_v2 - port( ram_input : in std_logic_vector(17 downto 0) := (others => 'U'); - ram_output : out std_logic_vector(17 downto 0); - waddr_previous : in std_logic_vector(1 downto 0) := (others => 'U'); - ram_write_i : in std_logic := 'U'; - RAM_CTRLR_v2_VCC : in std_logic := 'U'; - RAM_CTRLR_v2_GND : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - raddr_add1 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - raddr_rst : in std_logic := 'U' - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \reg_sample_in6\, N_850, \ram_output[4]\, - \sample_in_s_27[4]\, N_851, \ram_output[5]\, - \sample_in_s_25[5]\, N_852, \ram_output[6]\, - \sample_in_s_23[6]\, N_853, \ram_output[7]\, - \sample_in_s_21[7]\, N_854, \ram_output[8]\, - \sample_in_s_19[8]\, N_855, \ram_output[9]\, - \sample_in_s_17[9]\, N_856, \ram_output[10]\, - \sample_in_s_15[10]\, N_857, \ram_output[11]\, - \sample_in_s_13[11]\, N_858, \ram_output[12]\, - \sample_in_s_11[12]\, N_859, \ram_output[13]\, - \sample_in_s_9[13]\, N_860, \ram_output[14]\, - \sample_in_s_7[14]\, N_861, \ram_output[15]\, N_862, - \ram_output[16]\, N_863, \ram_output[17]\, - \reg_sample_in_5[4]\, reg_sample_in_5_sn_N_2_i, - \reg_sample_in_5[5]\, \reg_sample_in_5[6]\, - \reg_sample_in_5[7]\, \reg_sample_in_5[8]\, - \reg_sample_in_5[9]\, \reg_sample_in_5[10]\, - \reg_sample_in_5[11]\, \reg_sample_in_5[12]\, - \reg_sample_in_5[13]\, \reg_sample_in_5[14]\, - \reg_sample_in_5[15]\, \reg_sample_in_5[16]\, - \sample_out_s[16]\, \reg_sample_in_5[17]\, - \sample_out_s[17]\, N_890, \reg_sample_in[4]_net_1\, - \sample_out_s[4]\, N_891, \reg_sample_in[5]_net_1\, - \sample_out_s[5]\, N_892, \reg_sample_in[6]_net_1\, - \sample_out_s[6]\, N_893, \reg_sample_in[7]_net_1\, - \sample_out_s[7]\, N_894, \reg_sample_in[8]_net_1\, - \sample_out_s[8]\, N_895, \reg_sample_in[9]_net_1\, - \sample_out_s[9]\, N_896, \reg_sample_in[10]_net_1\, - \sample_out_s[10]\, N_897, \reg_sample_in[11]_net_1\, - \sample_out_s[11]\, N_898, \reg_sample_in[12]_net_1\, - \sample_out_s[12]\, N_899, \reg_sample_in[13]_net_1\, - \sample_out_s[13]\, N_900, \reg_sample_in[14]_net_1\, - \sample_out_s[14]\, N_901, \reg_sample_in[15]_net_1\, - \sample_out_s[15]\, N_902, \reg_sample_in[16]_net_1\, - N_903, \reg_sample_in[17]_net_1\, \ram_input[4]\, - \ram_input[5]\, \ram_input[6]\, \ram_input[7]\, - \ram_input[8]\, \ram_input[9]\, \ram_input[10]\, - \ram_input[11]\, \ram_input[12]\, \ram_input[13]\, - \ram_input[14]\, \ram_input[15]\, \ram_input[16]\, - \ram_input[17]\, \alu_sample[0]\, - \reg_sample_in[0]_net_1\, \ram_output[0]\, - \alu_sample[3]\, \reg_sample_in[3]_net_1\, - \ram_output[3]\, \alu_sample[4]\, \alu_sample[5]\, - \alu_sample[6]\, \alu_sample[7]\, \alu_sample[8]\, - \alu_sample[9]\, \alu_sample[10]\, \alu_sample[11]\, - \alu_sample[12]\, \alu_sample[13]\, \alu_sample[14]\, - \alu_sample[15]\, \alu_sample[16]\, \alu_sample[17]\, - N_849, \sample_in_s_29[3]\, \reg_sample_in_5[3]\, N_889, - \sample_out_s[3]\, \ram_input[3]\, N_846, - \sample_in_s_35[0]\, \reg_sample_in_5[0]\, N_886, - \sample_out_s[0]\, \ram_input[0]\, \sample_in_s_33[1]\, - \sample_in_s_31[2]\, \ram_input[2]\, N_888, - \ram_output[2]\, \reg_sample_in[2]_net_1\, - \reg_sample_in_5[2]\, \sample_out_s[2]\, N_848, - \alu_sample[2]\, \ram_input[1]\, N_887, \ram_output[1]\, - \reg_sample_in[1]_net_1\, \reg_sample_in_5[1]\, - \sample_out_s[1]\, N_847, \alu_sample[1]\, - \alu_coef_s[0]\, \alu_coef_s[1]\, \alu_coef_s[2]\, - \alu_coef_s[3]\, \alu_coef_s[4]\, \alu_coef_s[5]\, - \alu_coef_s[6]\, \alu_coef_s[7]\, \alu_coef_s[8]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - - for all : MUXN_9_5 - Use entity work.MUXN_9_5(DEF_ARCH); - for all : ALU - Use entity work.ALU(DEF_ARCH); - for all : RAM_CTRLR_v2 - Use entity work.RAM_CTRLR_v2(DEF_ARCH); -begin - - sample_out_s_1 <= \sample_out_s[1]\; - sample_out_s_2 <= \sample_out_s[2]\; - sample_out_s_0 <= \sample_out_s[0]\; - sample_out_s_3 <= \sample_out_s[3]\; - sample_out_s_15 <= \sample_out_s[15]\; - sample_out_s_14 <= \sample_out_s[14]\; - sample_out_s_13 <= \sample_out_s[13]\; - sample_out_s_12 <= \sample_out_s[12]\; - sample_out_s_11 <= \sample_out_s[11]\; - sample_out_s_10 <= \sample_out_s[10]\; - sample_out_s_9 <= \sample_out_s[9]\; - sample_out_s_8 <= \sample_out_s[8]\; - sample_out_s_7 <= \sample_out_s[7]\; - sample_out_s_6 <= \sample_out_s[6]\; - sample_out_s_5 <= \sample_out_s[5]\; - sample_out_s_4 <= \sample_out_s[4]\; - - \reg_sample_in_RNO_1[10]\ : MX2 - port map(A => sample_in_buf(133), B => sample_0(10), S => - sample_val_delay_1, Y => \sample_in_s_15[10]\); - - \reg_sample_in_RNO[2]\ : MX2 - port map(A => \sample_out_s[2]\, B => N_848, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[2]\); - - \reg_sample_in_RNISFS13[10]\ : MX2 - port map(A => N_896, B => \ram_output[10]\, S => - ram_sel_Wdata(1), Y => \ram_input[10]\); - - \reg_sample_in_RNI3APO2[2]\ : MX2 - port map(A => \reg_sample_in[2]_net_1\, B => - \ram_output[2]\, S => alu_sel_input, Y => \alu_sample[2]\); - - \reg_sample_in_RNO_1[1]\ : MX2 - port map(A => sample_in_buf(142), B => sample_0(1), S => - sample_val_delay_1, Y => \sample_in_s_33[1]\); - - \reg_sample_in_RNIAPCV2[2]\ : MX2 - port map(A => N_888, B => \ram_output[2]\, S => - ram_sel_Wdata(1), Y => \ram_input[2]\); - - \reg_sample_in_RNI65PT2[8]\ : MX2 - port map(A => N_894, B => \ram_output[8]\, S => - ram_sel_Wdata(1), Y => \ram_input[8]\); - - \reg_sample_in_RNIFAPO2[8]\ : MX2 - port map(A => \reg_sample_in[8]_net_1\, B => - \ram_output[8]\, S => alu_sel_input, Y => \alu_sample[8]\); - - \reg_sample_in_RNO_0[7]\ : MX2 - port map(A => \ram_output[7]\, B => \sample_in_s_21[7]\, S - => in_sel_src(0), Y => N_853); - - \reg_sample_in[5]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[5]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[5]_net_1\); - - \reg_sample_in_RNIA1VB[12]\ : MX2 - port map(A => \reg_sample_in[12]_net_1\, B => - \sample_out_s[12]\, S => ram_sel_Wdata(0), Y => N_898); - - \reg_sample_in_RNI5APO2[3]\ : MX2 - port map(A => \reg_sample_in[3]_net_1\, B => - \ram_output[3]\, S => alu_sel_input, Y => \alu_sample[3]\); - - \reg_sample_in_RNO_0[0]\ : MX2 - port map(A => \ram_output[0]\, B => \sample_in_s_35[0]\, S - => in_sel_src(0), Y => N_846); - - \reg_sample_in_RNI20U13[15]\ : MX2 - port map(A => N_901, B => \ram_output[15]\, S => - ram_sel_Wdata(1), Y => \ram_input[15]\); - - \reg_sample_in_RNO_0[1]\ : MX2 - port map(A => \ram_output[1]\, B => \sample_in_s_33[1]\, S - => in_sel_src(0), Y => N_847); - - \reg_sample_in_RNI8PVB[16]\ : MX2 - port map(A => \reg_sample_in[16]_net_1\, B => - \sample_out_s[16]\, S => ram_sel_Wdata(0), Y => N_902); - - \reg_sample_in_RNO_0[2]\ : MX2 - port map(A => \ram_output[2]\, B => \sample_in_s_31[2]\, S - => in_sel_src(0), Y => N_848); - - \reg_sample_in_RNI68U13[16]\ : MX2 - port map(A => N_902, B => \ram_output[16]\, S => - ram_sel_Wdata(1), Y => \ram_input[16]\); - - \reg_sample_in_RNIM4PT2[4]\ : MX2 - port map(A => N_890, B => \ram_output[4]\, S => - ram_sel_Wdata(1), Y => \ram_input[4]\); - - \reg_sample_in_RNO[11]\ : MX2 - port map(A => \sample_out_s[11]\, B => N_857, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[11]\); - - \reg_sample_in_RNO_1[2]\ : MX2 - port map(A => sample_in_buf(141), B => sample_0(2), S => - sample_val_delay_1, Y => \sample_in_s_31[2]\); - - \reg_sample_in_RNO_0[11]\ : MX2 - port map(A => \ram_output[11]\, B => \sample_in_s_13[11]\, - S => in_sel_src(0), Y => N_857); - - \reg_sample_in_RNI9LTS2[14]\ : MX2 - port map(A => \reg_sample_in[14]_net_1\, B => - \ram_output[14]\, S => alu_sel_input, Y => - \alu_sample[14]\); - - \reg_sample_in_RNI8RLC[3]\ : MX2 - port map(A => \reg_sample_in[3]_net_1\, B => - \sample_out_s[3]\, S => ram_sel_Wdata(0), Y => N_889); - - \reg_sample_in_RNI7TUB[11]\ : MX2 - port map(A => \reg_sample_in[11]_net_1\, B => - \sample_out_s[11]\, S => ram_sel_Wdata(0), Y => N_897); - - reg_sample_in6 : NOR2 - port map(A => in_sel_src(1), B => in_sel_src(0), Y => - \reg_sample_in6\); - - VCC_i : VCC - port map(Y => \VCC\); - - \reg_sample_in_RNO[13]\ : MX2 - port map(A => \sample_out_s[13]\, B => N_859, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[13]\); - - \reg_sample_in[3]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[3]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[3]_net_1\); - - \reg_sample_in_RNO_1[9]\ : MX2 - port map(A => sample_in_buf(134), B => sample_0(9), S => - sample_val_delay_0, Y => \sample_in_s_17[9]\); - - \reg_sample_in_RNIU79E[1]\ : MX2 - port map(A => \reg_sample_in[1]_net_1\, B => - \sample_out_s[1]\, S => ram_sel_Wdata(0), Y => N_887); - - \reg_sample_in_RNI1APO2[1]\ : MX2 - port map(A => \reg_sample_in[1]_net_1\, B => - \ram_output[1]\, S => alu_sel_input, Y => \alu_sample[1]\); - - \reg_sample_in_RNO[4]\ : MX2 - port map(A => \sample_out_s[4]\, B => N_850, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[4]\); - - \reg_sample_in_RNI0OS13[11]\ : MX2 - port map(A => N_897, B => \ram_output[11]\, S => - ram_sel_Wdata(1), Y => \ram_input[11]\); - - \reg_sample_in[7]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[7]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[7]_net_1\); - - \reg_sample_in_RNI5LVB[15]\ : MX2 - port map(A => \reg_sample_in[15]_net_1\, B => - \sample_out_s[15]\, S => ram_sel_Wdata(0), Y => N_901); - - \reg_sample_in[14]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[14]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[14]_net_1\); - - \reg_sample_in_RNIHRLC[6]\ : MX2 - port map(A => \reg_sample_in[6]_net_1\, B => - \sample_out_s[6]\, S => ram_sel_Wdata(0), Y => N_892); - - \reg_sample_in_RNIKRLC[7]\ : MX2 - port map(A => \reg_sample_in[7]_net_1\, B => - \sample_out_s[7]\, S => ram_sel_Wdata(0), Y => N_893); - - \reg_sample_in_RNI6HCV2[1]\ : MX2 - port map(A => N_887, B => \ram_output[1]\, S => - ram_sel_Wdata(1), Y => \ram_input[1]\); - - \reg_sample_in_RNI1G9E[2]\ : MX2 - port map(A => \reg_sample_in[2]_net_1\, B => - \sample_out_s[2]\, S => ram_sel_Wdata(0), Y => N_888); - - \reg_sample_in_RNO[3]\ : MX2 - port map(A => \sample_out_s[3]\, B => N_849, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[3]\); - - \reg_sample_in_RNIQ4PT2[5]\ : MX2 - port map(A => N_891, B => \ram_output[5]\, S => - ram_sel_Wdata(1), Y => \ram_input[5]\); - - \reg_sample_in_RNO_1[11]\ : MX2 - port map(A => sample_in_buf(132), B => sample_0(11), S => - sample_val_delay_0, Y => \sample_in_s_13[11]\); - - \reg_sample_in_RNO[1]\ : MX2 - port map(A => \sample_out_s[1]\, B => N_847, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[1]\); - - \reg_sample_in_RNI9APO2[5]\ : MX2 - port map(A => \reg_sample_in[5]_net_1\, B => - \ram_output[5]\, S => alu_sel_input, Y => \alu_sample[5]\); - - \reg_sample_in[9]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[9]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[9]_net_1\); - - \reg_sample_in_RNO_0[15]\ : MX2 - port map(A => \ram_output[15]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_861); - - \reg_sample_in_RNIBRLC[4]\ : MX2 - port map(A => \reg_sample_in[4]_net_1\, B => - \sample_out_s[4]\, S => ram_sel_Wdata(0), Y => N_890); - - \reg_sample_in_RNI4PUB[10]\ : MX2 - port map(A => \reg_sample_in[10]_net_1\, B => - \sample_out_s[10]\, S => ram_sel_Wdata(0), Y => N_896); - - \reg_sample_in_RNO[8]\ : MX2 - port map(A => \sample_out_s[8]\, B => N_854, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[8]\); - - \reg_sample_in_RNO[12]\ : MX2 - port map(A => \sample_out_s[12]\, B => N_858, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[12]\); - - \reg_sample_in_RNO_0[16]\ : MX2 - port map(A => \ram_output[16]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_862); - - \reg_sample_in[16]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[16]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[16]_net_1\); - - \reg_sample_in_RNO_1[5]\ : MX2 - port map(A => sample_in_buf(138), B => sample_0(5), S => - sample_val_delay_5, Y => \sample_in_s_25[5]\); - - Coeff_Mux : MUXN_9_5 - port map(S_36 => S_36, S_0 => S_0, alu_sel_coeff(4) => - alu_sel_coeff(4), alu_sel_coeff(3) => alu_sel_coeff(3), - alu_sel_coeff(2) => alu_sel_coeff(2), alu_sel_coeff(1) - => alu_sel_coeff(1), alu_sel_coeff(0) => - alu_sel_coeff(0), alu_sel_coeff_0_0 => alu_sel_coeff_0_0, - alu_sel_coeff_0_2 => alu_sel_coeff_0_2, alu_coef_s(8) => - \alu_coef_s[8]\, alu_coef_s(7) => \alu_coef_s[7]\, - alu_coef_s(6) => \alu_coef_s[6]\, alu_coef_s(5) => - \alu_coef_s[5]\, alu_coef_s(4) => \alu_coef_s[4]\, - alu_coef_s(3) => \alu_coef_s[3]\, alu_coef_s(2) => - \alu_coef_s[2]\, alu_coef_s(1) => \alu_coef_s[1]\, - alu_coef_s(0) => \alu_coef_s[0]\); - - ALU_1 : ALU - port map(alu_ctrl(2) => alu_ctrl(2), alu_ctrl(1) => - alu_ctrl(1), alu_ctrl(0) => alu_ctrl(0), alu_coef_s(8) - => \alu_coef_s[8]\, alu_coef_s(7) => \alu_coef_s[7]\, - alu_coef_s(6) => \alu_coef_s[6]\, alu_coef_s(5) => - \alu_coef_s[5]\, alu_coef_s(4) => \alu_coef_s[4]\, - alu_coef_s(3) => \alu_coef_s[3]\, alu_coef_s(2) => - \alu_coef_s[2]\, alu_coef_s(1) => \alu_coef_s[1]\, - alu_coef_s(0) => \alu_coef_s[0]\, alu_sample(17) => - \alu_sample[17]\, alu_sample(16) => \alu_sample[16]\, - alu_sample(15) => \alu_sample[15]\, alu_sample(14) => - \alu_sample[14]\, alu_sample(13) => \alu_sample[13]\, - alu_sample(12) => \alu_sample[12]\, alu_sample(11) => - \alu_sample[11]\, alu_sample(10) => \alu_sample[10]\, - alu_sample(9) => \alu_sample[9]\, alu_sample(8) => - \alu_sample[8]\, alu_sample(7) => \alu_sample[7]\, - alu_sample(6) => \alu_sample[6]\, alu_sample(5) => - \alu_sample[5]\, alu_sample(4) => \alu_sample[4]\, - alu_sample(3) => \alu_sample[3]\, alu_sample(2) => - \alu_sample[2]\, alu_sample(1) => \alu_sample[1]\, - alu_sample(0) => \alu_sample[0]\, sample_out_s(17) => - \sample_out_s[17]\, sample_out_s(16) => - \sample_out_s[16]\, sample_out_s(15) => - \sample_out_s[15]\, sample_out_s(14) => - \sample_out_s[14]\, sample_out_s(13) => - \sample_out_s[13]\, sample_out_s(12) => - \sample_out_s[12]\, sample_out_s(11) => - \sample_out_s[11]\, sample_out_s(10) => - \sample_out_s[10]\, sample_out_s(9) => \sample_out_s[9]\, - sample_out_s(8) => \sample_out_s[8]\, sample_out_s(7) => - \sample_out_s[7]\, sample_out_s(6) => \sample_out_s[6]\, - sample_out_s(5) => \sample_out_s[5]\, sample_out_s(4) => - \sample_out_s[4]\, sample_out_s(3) => \sample_out_s[3]\, - sample_out_s(2) => \sample_out_s[2]\, sample_out_s(1) => - \sample_out_s[1]\, sample_out_s(0) => \sample_out_s[0]\, - rstn => rstn, lclk_c => lclk_c); - - \reg_sample_in_RNIRV8E[0]\ : MX2 - port map(A => \reg_sample_in[0]_net_1\, B => - \sample_out_s[0]\, S => ram_sel_Wdata(0), Y => N_886); - - \reg_sample_in[8]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[8]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[8]_net_1\); - - \reg_sample_in[13]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[13]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[13]_net_1\); - - \reg_sample_in_RNI3TSS2[11]\ : MX2 - port map(A => \reg_sample_in[11]_net_1\, B => - \ram_output[11]\, S => alu_sel_input, Y => - \alu_sample[11]\); - - \reg_sample_in_RNIVCVB[13]\ : MX2 - port map(A => \reg_sample_in[13]_net_1\, B => - \sample_out_s[13]\, S => ram_sel_Wdata(0), Y => N_899); - - \reg_sample_in[12]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[12]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[12]_net_1\); - - \reg_sample_in_RNIBAPO2[6]\ : MX2 - port map(A => \reg_sample_in[6]_net_1\, B => - \ram_output[6]\, S => alu_sel_input, Y => \alu_sample[6]\); - - \reg_sample_in[10]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[10]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[10]_net_1\); - - \reg_sample_in_RNIUNT13[14]\ : MX2 - port map(A => N_900, B => \ram_output[14]\, S => - ram_sel_Wdata(1), Y => \ram_input[14]\); - - \reg_sample_in[6]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[6]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[6]_net_1\); - - \reg_sample_in[1]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[1]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[1]_net_1\); - - GND_i : GND - port map(Y => \GND\); - - \reg_sample_in_RNO[10]\ : MX2 - port map(A => \sample_out_s[10]\, B => N_856, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[10]\); - - \reg_sample_in_RNI55TS2[12]\ : MX2 - port map(A => \reg_sample_in[12]_net_1\, B => - \ram_output[12]\, S => alu_sel_input, Y => - \alu_sample[12]\); - - \reg_sample_in_RNI25PT2[7]\ : MX2 - port map(A => N_893, B => \ram_output[7]\, S => - ram_sel_Wdata(1), Y => \ram_input[7]\); - - \reg_sample_in_RNO_0[5]\ : MX2 - port map(A => \ram_output[5]\, B => \sample_in_s_25[5]\, S - => in_sel_src(0), Y => N_851); - - \reg_sample_in[2]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[2]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[2]_net_1\); - - \reg_sample_in_RNO_1[4]\ : MX2 - port map(A => sample_in_buf(139), B => sample_0(4), S => - sample_val_delay_1, Y => \sample_in_s_27[4]\); - - \reg_sample_in_RNIDAPO2[7]\ : MX2 - port map(A => \reg_sample_in[7]_net_1\, B => - \ram_output[7]\, S => alu_sel_input, Y => \alu_sample[7]\); - - \reg_sample_in_RNIA5PT2[9]\ : MX2 - port map(A => N_895, B => \ram_output[9]\, S => - ram_sel_Wdata(1), Y => \ram_input[9]\); - - \reg_sample_in_RNIQRLC[9]\ : MX2 - port map(A => \reg_sample_in[9]_net_1\, B => - \sample_out_s[9]\, S => ram_sel_Wdata(0), Y => N_895); - - \reg_sample_in[17]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[17]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[17]_net_1\); - - \reg_sample_in_RNIV9PO2[0]\ : MX2 - port map(A => \reg_sample_in[0]_net_1\, B => - \ram_output[0]\, S => alu_sel_input, Y => \alu_sample[0]\); - - \reg_sample_in_RNIQFT13[13]\ : MX2 - port map(A => N_899, B => \ram_output[13]\, S => - ram_sel_Wdata(1), Y => \ram_input[13]\); - - \reg_sample_in_RNO[7]\ : MX2 - port map(A => \sample_out_s[7]\, B => N_853, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[7]\); - - \reg_sample_in_RNO[16]\ : MX2 - port map(A => \sample_out_s[16]\, B => N_862, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[16]\); - - \reg_sample_in[4]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[4]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[4]_net_1\); - - \reg_sample_in_RNO_1[7]\ : MX2 - port map(A => sample_in_buf(136), B => sample_0(7), S => - sample_val_delay_0, Y => \sample_in_s_21[7]\); - - \reg_sample_in_RNO_1[3]\ : MX2 - port map(A => sample_in_buf(140), B => sample_0(3), S => - sample_val_delay_1, Y => \sample_in_s_29[3]\); - - \reg_sample_in_RNO_0[12]\ : MX2 - port map(A => \ram_output[12]\, B => \sample_in_s_11[12]\, - S => in_sel_src(0), Y => N_858); - - \reg_sample_in_RNO[6]\ : MX2 - port map(A => \sample_out_s[6]\, B => N_852, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[6]\); - - \reg_sample_in_RNIHAPO2[9]\ : MX2 - port map(A => \reg_sample_in[9]_net_1\, B => - \ram_output[9]\, S => alu_sel_input, Y => \alu_sample[9]\); - - \reg_sample_in[15]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[15]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[15]_net_1\); - - \reg_sample_in_RNO_0[4]\ : MX2 - port map(A => \ram_output[4]\, B => \sample_in_s_27[4]\, S - => in_sel_src(0), Y => N_850); - - \reg_sample_in_RNO_0[3]\ : MX2 - port map(A => \ram_output[3]\, B => \sample_in_s_29[3]\, S - => in_sel_src(0), Y => N_849); - - \reg_sample_in_RNO_0[17]\ : MX2 - port map(A => \ram_output[17]\, B => sample_in_s_1(17), S - => in_sel_src(0), Y => N_863); - - \reg_sample_in_RNO[17]\ : MX2 - port map(A => \sample_out_s[17]\, B => N_863, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[17]\); - - \reg_sample_in_RNO[14]\ : MX2 - port map(A => \sample_out_s[14]\, B => N_860, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[14]\); - - \reg_sample_in_RNINRLC[8]\ : MX2 - port map(A => \reg_sample_in[8]_net_1\, B => - \sample_out_s[8]\, S => ram_sel_Wdata(0), Y => N_894); - - \reg_sample_in_RNI2HVB[14]\ : MX2 - port map(A => \reg_sample_in[14]_net_1\, B => - \sample_out_s[14]\, S => ram_sel_Wdata(0), Y => N_900); - - \reg_sample_in_RNI1LSS2[10]\ : MX2 - port map(A => \reg_sample_in[10]_net_1\, B => - \ram_output[10]\, S => alu_sel_input, Y => - \alu_sample[10]\); - - \reg_sample_in_RNO_1[8]\ : MX2 - port map(A => sample_in_buf(135), B => sample_0(8), S => - sample_val_delay_0, Y => \sample_in_s_19[8]\); - - \reg_sample_in_RNI7DTS2[13]\ : MX2 - port map(A => \reg_sample_in[13]_net_1\, B => - \ram_output[13]\, S => alu_sel_input, Y => - \alu_sample[13]\); - - \reg_sample_in_RNI40T13[12]\ : MX2 - port map(A => N_898, B => \ram_output[12]\, S => - ram_sel_Wdata(1), Y => \ram_input[12]\); - - \reg_sample_in[11]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[11]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[11]_net_1\); - - \reg_sample_in_RNO[5]\ : MX2 - port map(A => \sample_out_s[5]\, B => N_851, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[5]\); - - \reg_sample_in_RNO_0[9]\ : MX2 - port map(A => \ram_output[9]\, B => \sample_in_s_17[9]\, S - => in_sel_src(0), Y => N_855); - - \reg_sample_in_RNO[9]\ : MX2 - port map(A => \sample_out_s[9]\, B => N_855, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[9]\); - - RAM_CTRLR_v2_1 : RAM_CTRLR_v2 - port map(ram_input(17) => \ram_input[17]\, ram_input(16) - => \ram_input[16]\, ram_input(15) => \ram_input[15]\, - ram_input(14) => \ram_input[14]\, ram_input(13) => - \ram_input[13]\, ram_input(12) => \ram_input[12]\, - ram_input(11) => \ram_input[11]\, ram_input(10) => - \ram_input[10]\, ram_input(9) => \ram_input[9]\, - ram_input(8) => \ram_input[8]\, ram_input(7) => - \ram_input[7]\, ram_input(6) => \ram_input[6]\, - ram_input(5) => \ram_input[5]\, ram_input(4) => - \ram_input[4]\, ram_input(3) => \ram_input[3]\, - ram_input(2) => \ram_input[2]\, ram_input(1) => - \ram_input[1]\, ram_input(0) => \ram_input[0]\, - ram_output(17) => \ram_output[17]\, ram_output(16) => - \ram_output[16]\, ram_output(15) => \ram_output[15]\, - ram_output(14) => \ram_output[14]\, ram_output(13) => - \ram_output[13]\, ram_output(12) => \ram_output[12]\, - ram_output(11) => \ram_output[11]\, ram_output(10) => - \ram_output[10]\, ram_output(9) => \ram_output[9]\, - ram_output(8) => \ram_output[8]\, ram_output(7) => - \ram_output[7]\, ram_output(6) => \ram_output[6]\, - ram_output(5) => \ram_output[5]\, ram_output(4) => - \ram_output[4]\, ram_output(3) => \ram_output[3]\, - ram_output(2) => \ram_output[2]\, ram_output(1) => - \ram_output[1]\, ram_output(0) => \ram_output[0]\, - waddr_previous(1) => waddr_previous(1), waddr_previous(0) - => waddr_previous(0), ram_write_i => ram_write_i, - RAM_CTRLR_v2_VCC => IIR_CEL_CTRLR_v2_DATAFLOW_VCC, - RAM_CTRLR_v2_GND => IIR_CEL_CTRLR_v2_DATAFLOW_GND, - ram_write => ram_write, raddr_add1 => raddr_add1, rstn - => rstn, lclk_c => lclk_c, raddr_rst => raddr_rst); - - \reg_sample_in_RNI7APO2[4]\ : MX2 - port map(A => \reg_sample_in[4]_net_1\, B => - \ram_output[4]\, S => alu_sel_input, Y => \alu_sample[4]\); - - \reg_sample_in_RNIFDUS2[17]\ : MX2 - port map(A => \reg_sample_in[17]_net_1\, B => - \ram_output[17]\, S => alu_sel_input, Y => - \alu_sample[17]\); - - \reg_sample_in_RNIBTVB[17]\ : MX2 - port map(A => \reg_sample_in[17]_net_1\, B => - \sample_out_s[17]\, S => ram_sel_Wdata(0), Y => N_903); - - reg_sample_in_5_sn_m1 : OR2B - port map(A => in_sel_src(1), B => in_sel_src(0), Y => - reg_sample_in_5_sn_N_2_i); - - \reg_sample_in_RNO[15]\ : MX2 - port map(A => \sample_out_s[15]\, B => N_861, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[15]\); - - \reg_sample_in_RNO_0[14]\ : MX2 - port map(A => \ram_output[14]\, B => \sample_in_s_7[14]\, S - => in_sel_src(0), Y => N_860); - - \reg_sample_in_RNI29CV2[0]\ : MX2 - port map(A => N_886, B => \ram_output[0]\, S => - ram_sel_Wdata(1), Y => \ram_input[0]\); - - \reg_sample_in_RNO_1[12]\ : MX2 - port map(A => sample_in_buf(131), B => sample_0(12), S => - sample_val_delay_1, Y => \sample_in_s_11[12]\); - - \reg_sample_in_RNII4PT2[3]\ : MX2 - port map(A => N_889, B => \ram_output[3]\, S => - ram_sel_Wdata(1), Y => \ram_input[3]\); - - \reg_sample_in_RNIU4PT2[6]\ : MX2 - port map(A => N_892, B => \ram_output[6]\, S => - ram_sel_Wdata(1), Y => \ram_input[6]\); - - \reg_sample_in_RNO_0[8]\ : MX2 - port map(A => \ram_output[8]\, B => \sample_in_s_19[8]\, S - => in_sel_src(0), Y => N_854); - - \reg_sample_in_RNO_0[13]\ : MX2 - port map(A => \ram_output[13]\, B => \sample_in_s_9[13]\, S - => in_sel_src(0), Y => N_859); - - \reg_sample_in_RNO[0]\ : MX2 - port map(A => \sample_out_s[0]\, B => N_846, S => - reg_sample_in_5_sn_N_2_i, Y => \reg_sample_in_5[0]\); - - \reg_sample_in_RNID5US2[16]\ : MX2 - port map(A => \reg_sample_in[16]_net_1\, B => - \ram_output[16]\, S => alu_sel_input, Y => - \alu_sample[16]\); - - \reg_sample_in[0]\ : DFN1E0C0 - port map(D => \reg_sample_in_5[0]\, CLK => lclk_c, CLR => - rstn, E => \reg_sample_in6\, Q => - \reg_sample_in[0]_net_1\); - - \reg_sample_in_RNIAGU13[17]\ : MX2 - port map(A => N_903, B => \ram_output[17]\, S => - ram_sel_Wdata(1), Y => \ram_input[17]\); - - \reg_sample_in_RNO_0[10]\ : MX2 - port map(A => \ram_output[10]\, B => \sample_in_s_15[10]\, - S => in_sel_src(0), Y => N_856); - - \reg_sample_in_RNO_1[14]\ : MX2 - port map(A => sample_in_buf(129), B => sample_0(14), S => - sample_val_delay_1, Y => \sample_in_s_7[14]\); - - \reg_sample_in_RNIERLC[5]\ : MX2 - port map(A => \reg_sample_in[5]_net_1\, B => - \sample_out_s[5]\, S => ram_sel_Wdata(0), Y => N_891); - - \reg_sample_in_RNO_1[6]\ : MX2 - port map(A => sample_in_buf(137), B => sample_0(6), S => - sample_val_delay_1, Y => \sample_in_s_23[6]\); - - \reg_sample_in_RNIBTTS2[15]\ : MX2 - port map(A => \reg_sample_in[15]_net_1\, B => - \ram_output[15]\, S => alu_sel_input, Y => - \alu_sample[15]\); - - \reg_sample_in_RNO_0[6]\ : MX2 - port map(A => \ram_output[6]\, B => \sample_in_s_23[6]\, S - => in_sel_src(0), Y => N_852); - - \reg_sample_in_RNO_1[13]\ : MX2 - port map(A => sample_in_buf(130), B => sample_0(13), S => - sample_val_delay_0, Y => \sample_in_s_9[13]\); - - \reg_sample_in_RNO_1[0]\ : MX2 - port map(A => sample_in_buf(143), B => sample_0(0), S => - sample_val_delay_0, Y => \sample_in_s_35[0]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2_CONTROL is - - port( alu_ctrl : out std_logic_vector(2 downto 0); - ram_sel_Wdata : out std_logic_vector(1 downto 0); - waddr_previous : out std_logic_vector(1 downto 0); - in_sel_src : out std_logic_vector(1 downto 0); - alu_sel_coeff : out std_logic_vector(4 downto 0); - S_36 : in std_logic; - S_0 : in std_logic; - alu_sel_coeff_0_2 : out std_logic; - alu_sel_coeff_0_0 : out std_logic; - sample_out_rot_s : out std_logic; - sample_out_val_s : out std_logic; - raddr_rst : out std_logic; - alu_sel_input : out std_logic; - raddr_add1 : out std_logic; - un1_sample_in_rotate : out std_logic; - sample_val_delay_2 : in std_logic; - sample_val_delay_1 : in std_logic; - ram_write : out std_logic; - ram_write_i : out std_logic; - un1_sample_in_rotate_0 : out std_logic; - un1_sample_in_rotate_1 : out std_logic; - un1_sample_in_rotate_2 : out std_logic; - un1_sample_in_rotate_3 : out std_logic; - sample_val_delay_0 : in std_logic; - un1_sample_in_rotate_4 : out std_logic; - sample_out_rot_s_0 : out std_logic; - sample_out_rot_s_1 : out std_logic; - sample_out_rot_s_2 : out std_logic; - sample_out_rot_s_3 : out std_logic; - sample_out_rot_s_4 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end IIR_CEL_CTRLR_v2_CONTROL; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2_CONTROL is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal Chanel_ongoing_n6_0_i_0_o2_0, - \Chanel_ongoing[6]_net_1\, \Chanel_ongoing[5]_net_1\, - Chanel_ongoing_n29, \Chanel_ongoing[29]_net_1\, N_295, - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Chanel_ongoing_n30, - \Chanel_ongoing[30]_net_1\, N_327, Chanel_ongoing_n31, - \Chanel_ongoing[31]_net_1\, N_335, N_250, - \Chanel_ongoing[0]_net_1\, \Chanel_ongoing[1]_net_1\, - \Chanel_ongoing[2]_net_1\, N_270, - \Chanel_ongoing[13]_net_1\, N_265, N_271, - \Chanel_ongoing[14]_net_1\, N_279, - \Chanel_ongoing[20]_net_1\, N_278, N_290, - \Chanel_ongoing[24]_net_1\, N_288, - \Chanel_ongoing[28]_net_1\, N_293, N_252_i_0, - \Chanel_ongoing[3]_net_1\, \Chanel_ongoing[4]_net_1\, - N_255, \Chanel_ongoing[7]_net_1\, - \Chanel_ongoing[27]_net_1\, N_292, N_291, - \Chanel_ongoing[26]_net_1\, \Chanel_ongoing[25]_net_1\, - \Chanel_ongoing[23]_net_1\, N_286, - \Chanel_ongoing[22]_net_1\, - \Chanel_ongoing_RNIV67U4[21]_net_1\, - \Chanel_ongoing[21]_net_1\, \Chanel_ongoing[19]_net_1\, - N_276, \Chanel_ongoing[18]_net_1\, N_275, - \Chanel_ongoing[17]_net_1\, N_273, - \Chanel_ongoing[16]_net_1\, N_272, - \Chanel_ongoing[15]_net_1\, \Chanel_ongoing[12]_net_1\, - N_264, \Chanel_ongoing[10]_net_1\, N_257, - \Chanel_ongoing[11]_net_1\, \Chanel_ongoing[8]_net_1\, - \Chanel_ongoing[9]_net_1\, alu_selected_coeff_n0, - alu_selected_coeffe, N_713, N_567_i_0, - \IIR_CEL_STATE[8]_net_1\, sample_in_rotate, N_127_0, - N_478, N_480, N_274, - un1_alu_sel_input_0_sqmuxa_1_i_0_s_0_0, N_452, N_480_0, - \IIR_CEL_STATE[4]_net_1\, N_328, N_478_0, N_326, - \DWACT_ADD_CI_0_g_array_4[0]\, - \DWACT_ADD_CI_0_g_array_3[0]\, - \DWACT_ADD_CI_0_pog_array_3[0]\, - \DWACT_ADD_CI_0_g_array_9[0]\, - \DWACT_ADD_CI_0_pog_array_3_1[0]\, - \DWACT_ADD_CI_0_g_array_10[0]\, - \DWACT_ADD_CI_0_pog_array_2_1[0]\, - \DWACT_ADD_CI_0_g_array_10_1[0]\, - \DWACT_ADD_CI_0_pog_array_2_3[0]\, - \DWACT_ADD_CI_0_g_array_11_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_5[0]\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_2[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_11_1[0]\, - \DWACT_ADD_CI_0_pog_array_1_3[0]\, - \DWACT_ADD_CI_0_g_array_10_2[0]\, - \DWACT_ADD_CI_0_pog_array_2_5[0]\, - \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, \Cel_ongoing[6]_net_1\, - \DWACT_ADD_CI_0_g_array_12_9[0]\, \Cel_ongoing[20]_net_1\, - \DWACT_ADD_CI_0_g_array_12_3[0]\, \Cel_ongoing[8]_net_1\, - \DWACT_ADD_CI_0_g_array_12_4[0]\, \Cel_ongoing[10]_net_1\, - \DWACT_ADD_CI_0_g_array_11_3[0]\, - \DWACT_ADD_CI_0_pog_array_1_7[0]\, - \DWACT_ADD_CI_0_g_array_11_4[0]\, - \DWACT_ADD_CI_0_pog_array_1_9[0]\, - \DWACT_ADD_CI_0_g_array_11_5[0]\, - \DWACT_ADD_CI_0_pog_array_1_11[0]\, - \DWACT_ADD_CI_0_g_array_11_6[0]\, - \DWACT_ADD_CI_0_pog_array_1_13[0]\, - \DWACT_ADD_CI_0_g_array_12[0]\, \Cel_ongoing[2]_net_1\, - \DWACT_ADD_CI_0_g_array_12_7[0]\, \Cel_ongoing[16]_net_1\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, \Cel_ongoing[4]_net_1\, - \DWACT_ADD_CI_0_g_array_12_13[0]\, - \Cel_ongoing[28]_net_1\, - \DWACT_ADD_CI_0_g_array_12_14[0]\, - \Cel_ongoing[30]_net_1\, \DWACT_ADD_CI_0_g_array_12_5[0]\, - \Cel_ongoing[12]_net_1\, \DWACT_ADD_CI_0_g_array_12_6[0]\, - \Cel_ongoing[14]_net_1\, \DWACT_ADD_CI_0_g_array_12_8[0]\, - \Cel_ongoing[18]_net_1\, - \DWACT_ADD_CI_0_g_array_12_10[0]\, - \Cel_ongoing[22]_net_1\, - \DWACT_ADD_CI_0_g_array_12_11[0]\, - \Cel_ongoing[24]_net_1\, - \DWACT_ADD_CI_0_g_array_12_12[0]\, - \Cel_ongoing[26]_net_1\, \DWACT_ADD_CI_0_TMP[0]\, - \Cel_ongoing[1]_net_1\, \IIR_CEL_STATE_i_i[9]\, - \IIR_CEL_STATE_i[9]_net_1\, Chanel_ongoing_n8_0_i_0_0, - Chanel_ongoing_n2_0_i_0_0, Chanel_ongoing_n4_0_i_0_0, - Chanel_ongoing_n7_0_i_0_0, Chanel_ongoing_n6_0_i_0_0, - Chanel_ongoing_n5_0_i_0_0, Chanel_ongoing_n1_0_i_0_0, - N_294, N_451_1, N_453, alu_selected_coeff_n2_0_i_0, - \alu_sel_coeff_0[2]\, alu_selected_coeff_n3_0_i_0, N_717, - un1_IIR_CEL_STATE_20_0_0, \IIR_CEL_STATE[0]_net_1\, - \IIR_CEL_STATE[5]_net_1\, raddr_add1_2_i_a2_0_0, - \IIR_CEL_STATE[3]_net_1\, \in_sel_src_8_i_a2_0_a2_0_0[1]\, - \IIR_CEL_STATE[6]_net_1\, \IIR_CEL_STATE[7]_net_1\, - Cel_ongoing_0_sqmuxa_0_a2_0_27, - Cel_ongoing_0_sqmuxa_0_a2_0_16, - Cel_ongoing_0_sqmuxa_0_a2_0_15, - Cel_ongoing_0_sqmuxa_0_a2_0_24, - Cel_ongoing_0_sqmuxa_0_a2_0_26, - Cel_ongoing_0_sqmuxa_0_a2_0_12, - Cel_ongoing_0_sqmuxa_0_a2_0_11, - Cel_ongoing_0_sqmuxa_0_a2_0_22, - Cel_ongoing_0_sqmuxa_0_a2_0_25, - Cel_ongoing_0_sqmuxa_0_a2_0_8, - Cel_ongoing_0_sqmuxa_0_a2_0_7, - Cel_ongoing_0_sqmuxa_0_a2_0_20, N_479, - Cel_ongoing_0_sqmuxa_0_a2_0_4, - Cel_ongoing_0_sqmuxa_0_a2_0_18, - Cel_ongoing_0_sqmuxa_0_a2_0_14, - Cel_ongoing_0_sqmuxa_0_a2_0_10, - Cel_ongoing_0_sqmuxa_0_a2_0_6, - Cel_ongoing_0_sqmuxa_0_a2_0_3, - Cel_ongoing_0_sqmuxa_0_a2_0_1, - \in_sel_src_8_i_a2_0_o2_0_27[1]\, - \in_sel_src_8_i_a2_0_o2_0_18[1]\, - \in_sel_src_8_i_a2_0_o2_0_17[1]\, - \in_sel_src_8_i_a2_0_o2_0_23[1]\, - \in_sel_src_8_i_a2_0_o2_0_26[1]\, - \in_sel_src_8_i_a2_0_o2_0_12[1]\, - \in_sel_src_8_i_a2_0_o2_0_11[1]\, - \in_sel_src_8_i_a2_0_o2_0_22[1]\, - \in_sel_src_8_i_a2_0_o2_0_25[1]\, - \in_sel_src_8_i_a2_0_o2_0_8[1]\, - \in_sel_src_8_i_a2_0_o2_0_7[1]\, - \in_sel_src_8_i_a2_0_o2_0_20[1]\, - \in_sel_src_8_i_a2_0_o2_0_2[1]\, - \in_sel_src_8_i_a2_0_o2_0_1[1]\, - \in_sel_src_8_i_a2_0_o2_0_15[1]\, - \in_sel_src_8_i_a2_0_o2_0_14[1]\, \Cel_ongoing[27]_net_1\, - \in_sel_src_8_i_a2_0_o2_0_10[1]\, \Cel_ongoing[19]_net_1\, - \in_sel_src_8_i_a2_0_o2_0_6[1]\, \Cel_ongoing[11]_net_1\, - \in_sel_src_8_i_a2_0_o2_0_4[1]\, \Cel_ongoing[7]_net_1\, - \Cel_ongoing[0]_net_1\, \Cel_ongoing[31]_net_1\, - \Cel_ongoing[29]_net_1\, \Cel_ongoing[25]_net_1\, - \Cel_ongoing[23]_net_1\, \Cel_ongoing[21]_net_1\, - \Cel_ongoing[17]_net_1\, \Cel_ongoing[15]_net_1\, - \Cel_ongoing[13]_net_1\, \Cel_ongoing[9]_net_1\, - \Cel_ongoing[5]_net_1\, \Cel_ongoing[3]_net_1\, - ram_write_2_0_a2_0, N_736, \raddr_add1_RNO\, N_737, N_735, - N_289, un1_alu_sel_input_0_sqmuxa_1_i_0, N_206, - \Cel_ongoing_6_i_i_0[0]\, N_457, N_454, - un1_IIR_CEL_STATE_20, N_796_i, N_18, N_703, N_714, N_20, - N_22, N_650, N_11, N_325, N_651_i_0, - \Cel_ongoing_6_i_i_a2_0_0[0]\, - \DWACT_ADD_CI_0_partial_sum[0]\, N_216_i, - \Chanel_ongoing_RNO_0[12]_net_1\, sample_in_rot_2, - N_568_i_0, N_334, N_729, N_269, N_332, N_268, N_512_i_0, - N_180, N_569, N_465, I_120, \IIR_CEL_STATE[2]_net_1\, - \IIR_CEL_STATE[1]_net_1\, un1_IIR_CEL_STATE_24, N_523, - un1_IIR_CEL_STATE_22, N_204, N_353, N_227, - \IIR_CEL_STATE_ns[8]\, alu_sel_input_1, - \IIR_CEL_STATE_RNI87UP_1[4]_net_1\, un1_IIR_CEL_STATE_18, - ram_write_2, N_477, N_450, I_121, N_449, I_115_4, N_448, - I_109, N_447, I_116, N_446, I_110, N_445, I_129_4, N_444, - I_125, N_443, I_130, N_442, I_127, N_441, I_126, N_440, - I_124, N_439, I_122_4, N_438, I_128, N_437, I_123, N_436, - I_117, N_435, I_111, \Cel_ongoing_RNO[15]_net_1\, I_118, - \Cel_ongoing_RNO[14]_net_1\, I_112, - \Cel_ongoing_RNO[13]_net_1\, I_106, - \Cel_ongoing_RNO[12]_net_1\, I_101, - \Cel_ongoing_RNO[11]_net_1\, I_107, - \Cel_ongoing_RNO[10]_net_1\, I_105_4, - \Cel_ongoing_RNO[9]_net_1\, I_103, - \Cel_ongoing_RNO[8]_net_1\, I_102, - \Cel_ongoing_RNO[7]_net_1\, I_99, - \Cel_ongoing_RNO[6]_net_1\, I_104, - \Cel_ongoing_RNO[5]_net_1\, I_100, - \Cel_ongoing_RNO[4]_net_1\, I_119, - \Cel_ongoing_RNO[3]_net_1\, I_113, - \Cel_ongoing_RNO[1]_net_1\, I_114, N_127, - Chanel_ongoing_n0, Chanel_ongoing_n20, Chanel_ongoing_n24, - Chanel_ongoing_n28, N_224, N_724, N_336_i_i_0, N_15_i, - \alu_sel_coeff[3]\, N_715, N_712, \alu_sel_coeff_0[0]\, - N_221, N_461, N_373_i, N_374_i, N_372_i, N_232, N_229, - Chanel_ongoing_n27, Chanel_ongoing_n26, - Chanel_ongoing_n25, Chanel_ongoing_n23, - Chanel_ongoing_n22, Chanel_ongoing_n21, - Chanel_ongoing_n19, Chanel_ongoing_n18, - Chanel_ongoing_n17, N_462, N_460, \alu_sel_coeff[4]\, - ram_write_net_1, \DWACT_ADD_CI_0_pog_array_2_4[0]\, - \DWACT_ADD_CI_0_pog_array_1_10[0]\, - \DWACT_ADD_CI_0_pog_array_1_8[0]\, - \DWACT_ADD_CI_0_pog_array_1_4[0]\, - \DWACT_ADD_CI_0_pog_array_1_6[0]\, - \DWACT_ADD_CI_0_pog_array_1_12[0]\, - \DWACT_ADD_CI_0_pog_array_2_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_2[0]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - alu_sel_coeff(4) <= \alu_sel_coeff[4]\; - alu_sel_coeff(3) <= \alu_sel_coeff[3]\; - alu_sel_coeff_0_2 <= \alu_sel_coeff_0[2]\; - alu_sel_coeff_0_0 <= \alu_sel_coeff_0[0]\; - ram_write <= ram_write_net_1; - - un1_Cel_ongoing_1_I_148 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \Cel_ongoing[4]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_1[0]\); - - \IIR_CEL_STATE_i_RNI151I[9]\ : OR2B - port map(A => N_294, B => \IIR_CEL_STATE_i[9]_net_1\, Y => - N_326); - - sample_in_rot_RNO : NOR2A - port map(A => \IIR_CEL_STATE[7]_net_1\, B => N_328, Y => - sample_in_rot_2); - - \Cel_ongoing_RNO[9]\ : NOR3C - port map(A => N_478, B => N_480, C => I_103, Y => - \Cel_ongoing_RNO[9]_net_1\); - - \Chanel_ongoing_RNIV67U4[21]\ : OR2A - port map(A => \Chanel_ongoing[21]_net_1\, B => N_279, Y => - \Chanel_ongoing_RNIV67U4[21]_net_1\); - - \in_sel_src[0]\ : DFN1E0C0 - port map(D => N_268, CLK => lclk_c, CLR => rstn, E => - un1_IIR_CEL_STATE_24, Q => in_sel_src(0)); - - \IIR_CEL_STATE_RNI3IM46_0[4]\ : OR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_328, Y => - N_480_0); - - \Chanel_ongoing[1]\ : DFN1E1C0 - port map(D => N_18, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[1]_net_1\); - - \Cel_ongoing_RNI8SOP5[7]\ : OR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_26[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_25[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_27[1]\, Y => N_325); - - \in_sel_src_RNO_0[1]\ : OR2 - port map(A => \IIR_CEL_STATE[6]_net_1\, B => - \IIR_CEL_STATE[7]_net_1\, Y => - \in_sel_src_8_i_a2_0_a2_0_0[1]\); - - \IIR_CEL_STATE_RNI87UP_0[4]\ : OR2A - port map(A => N_326, B => \IIR_CEL_STATE[4]_net_1\, Y => - N_478_0); - - \Cel_ongoing[23]\ : DFN1C0 - port map(D => N_442, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[23]_net_1\); - - \Cel_ongoing[22]\ : DFN1C0 - port map(D => N_441, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[22]_net_1\); - - \Chanel_ongoing[29]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n29, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[29]_net_1\); - - \Cel_ongoing_RNO[17]\ : NOR3C - port map(A => N_478_0, B => N_480, C => I_117, Y => N_436); - - \IIR_CEL_STATE_i_RNI4P117_0[9]\ : OR3B - port map(A => N_478, B => N_480, C => N_274, Y => N_127); - - un1_Cel_ongoing_1_I_123 : XOR2 - port map(A => \Cel_ongoing[18]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_3[0]\, Y => I_123); - - un1_Cel_ongoing_1_I_109 : XOR2 - port map(A => \Cel_ongoing[29]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_13[0]\, Y => I_109); - - \Cel_ongoing[15]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[15]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[15]_net_1\); - - \Cel_ongoing_RNO[16]\ : NOR3C - port map(A => N_478_0, B => N_480, C => I_111, Y => N_435); - - \Chanel_ongoing_RNO[30]\ : XA1C - port map(A => \Chanel_ongoing[30]_net_1\, B => N_327, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n30); - - \Cel_ongoing_RNO[21]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_124, Y => N_440); - - \alu_selected_coeff[4]\ : DFN1E1C0 - port map(D => N_715, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => \alu_sel_coeff[4]\); - - un1_Cel_ongoing_1_I_187 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - \Cel_ongoing[2]\ : DFN1C0 - port map(D => N_227, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[2]_net_1\); - - \IIR_CEL_STATE_i_RNI8T27D[9]\ : OR2A - port map(A => \IIR_CEL_STATE_ns[8]\, B => N_274, Y => N_452); - - \alu_selected_coeff_RNO[3]\ : NOR3B - port map(A => N_478_0, B => N_480_0, C => - alu_selected_coeff_n3_0_i_0, Y => N_714); - - \Chanel_ongoing_RNO_0[9]\ : AX1A - port map(A => N_255, B => \Chanel_ongoing[8]_net_1\, C => - \Chanel_ongoing[9]_net_1\, Y => N_372_i); - - \alu_selected_coeff_0_RNIU2Q27[2]\ : NOR3B - port map(A => N_478_0, B => N_480_0, C => - alu_selected_coeff_n2_0_i_0, Y => N_713); - - \IIR_CEL_STATE_RNO[2]\ : NOR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_523, Y => - N_477); - - sample_in_rot_RNIVMA4_1 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_1); - - alu_sel_input_RNO : NOR2 - port map(A => \IIR_CEL_STATE[6]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => alu_sel_input_1); - - un1_Cel_ongoing_1_I_146 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \Cel_ongoing[2]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12[0]\); - - \Chanel_ongoing_RNO_0[3]\ : XNOR2 - port map(A => N_250, B => \Chanel_ongoing[3]_net_1\, Y => - N_336_i_i_0); - - \Cel_ongoing_RNO_1[0]\ : OR3B - port map(A => N_294, B => N_274, C => - \IIR_CEL_STATE[4]_net_1\, Y => N_457); - - \Chanel_ongoing[30]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n30, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[30]_net_1\); - - un1_Cel_ongoing_1_I_122 : XOR2 - port map(A => \Cel_ongoing[20]_net_1\, B => - \DWACT_ADD_CI_0_g_array_10_1[0]\, Y => I_122_4); - - \Cel_ongoing_RNO[5]\ : NOR3C - port map(A => N_478, B => N_480, C => I_100, Y => - \Cel_ongoing_RNO[5]_net_1\); - - un1_Cel_ongoing_1_I_99 : XOR2 - port map(A => \Cel_ongoing[7]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => I_99); - - un1_Cel_ongoing_1_I_158 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_2[0]\, B => - \Cel_ongoing[14]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_6[0]\); - - \Cel_ongoing[24]\ : DFN1C0 - port map(D => N_443, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[24]_net_1\); - - \IIR_CEL_STATE_i[9]\ : DFN1 - port map(D => N_512_i_0, CLK => lclk_c, Q => - \IIR_CEL_STATE_i[9]_net_1\); - - un1_Cel_ongoing_1_I_103 : XOR2 - port map(A => \Cel_ongoing[9]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_3[0]\, Y => I_103); - - \Chanel_ongoing_RNIHSTH5[24]\ : OR2A - port map(A => \Chanel_ongoing[24]_net_1\, B => N_288, Y => - N_290); - - \Chanel_ongoing[8]\ : DFN1E1C0 - port map(D => N_651_i_0, CLK => lclk_c, CLR => rstn, E => - N_127, Q => \Chanel_ongoing[8]_net_1\); - - \Chanel_ongoing_RNO[13]\ : XA1C - port map(A => \Chanel_ongoing[13]_net_1\, B => N_265, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_224); - - un1_Cel_ongoing_1_I_162 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_3[0]\, B => - \Cel_ongoing[18]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_8[0]\); - - un1_Cel_ongoing_1_I_131 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => - \Cel_ongoing[6]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_2[0]\); - - \Cel_ongoing_RNO[11]\ : NOR3C - port map(A => N_478, B => N_480, C => I_107, Y => - \Cel_ongoing_RNO[11]_net_1\); - - \alu_selected_coeff_RNO_0[4]\ : AX1E - port map(A => N_717, B => \alu_sel_coeff[3]\, C => - \alu_sel_coeff[4]\, Y => N_15_i); - - \IIR_CEL_STATE_i_RNIF6BBE_0[9]\ : OR2B - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0_s_0_0, B => - N_452, Y => un1_alu_sel_input_0_sqmuxa_1_i_0); - - \Chanel_ongoing[3]\ : DFN1E1C0 - port map(D => N_221, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[3]_net_1\); - - \Chanel_ongoing_RNO_0[6]\ : AX1E - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252_i_0, C - => \Chanel_ongoing[6]_net_1\, Y => - Chanel_ongoing_n6_0_i_0_0); - - \Chanel_ongoing_RNI4AP45[22]\ : OR2A - port map(A => \Chanel_ongoing[22]_net_1\, B => - \Chanel_ongoing_RNIV67U4[21]_net_1\, Y => N_286); - - ram_write_RNO : OAI1 - port map(A => N_451_1, B => ram_write_2_0_a2_0, C => - N_480_0, Y => ram_write_2); - - \IIR_CEL_STATE_RNIEAGK6[0]\ : OR2B - port map(A => un1_IIR_CEL_STATE_20_0_0, B => N_480_0, Y => - un1_IIR_CEL_STATE_20); - - \Cel_ongoing[0]\ : DFN1C0 - port map(D => N_206, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[0]_net_1\); - - un1_Cel_ongoing_1_I_102 : XOR2 - port map(A => \Cel_ongoing[8]_net_1\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, Y => I_102); - - \alu_selected_coeff_0_RNIJ954[2]\ : XOR2 - port map(A => S_0, B => \alu_sel_coeff_0[2]\, Y => - alu_selected_coeff_n2_0_i_0); - - sample_out_rot_3 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_3); - - \Chanel_ongoing_RNIDI4D[23]\ : NOR2 - port map(A => \Chanel_ongoing[23]_net_1\, B => - \Chanel_ongoing[24]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_11); - - un1_Cel_ongoing_1_I_117 : XOR2 - port map(A => \Cel_ongoing[17]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_7[0]\, Y => I_117); - - un1_Cel_ongoing_1_I_156 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10[0]\, B => - \Cel_ongoing[12]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_5[0]\); - - un1_Cel_ongoing_1_I_171 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => - \Cel_ongoing[1]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_1[0]\); - - \Chanel_ongoing_RNI8U3D[31]\ : NOR2 - port map(A => \Chanel_ongoing[11]_net_1\, B => - \Chanel_ongoing[31]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_4); - - \Cel_ongoing_RNISFPS5[2]\ : OR2A - port map(A => \Cel_ongoing[2]_net_1\, B => N_325, Y => - N_328); - - \IIR_CEL_STATE[2]\ : DFN1E1 - port map(D => N_477, CLK => lclk_c, E => rstn, Q => - \IIR_CEL_STATE[2]_net_1\); - - \Chanel_ongoing_RNIQQAT3[16]\ : OR2A - port map(A => \Chanel_ongoing[16]_net_1\, B => N_272, Y => - N_273); - - \Chanel_ongoing[13]\ : DFN1E1C0 - port map(D => N_224, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[13]_net_1\); - - \Chanel_ongoing[12]\ : DFN1E1C0 - port map(D => N_216_i, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[12]_net_1\); - - ram_write_RNO_0 : OR2 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[7]_net_1\, Y => ram_write_2_0_a2_0); - - \Chanel_ongoing_RNIJMNV[2]\ : NOR3B - port map(A => \Chanel_ongoing[3]_net_1\, B => - Cel_ongoing_0_sqmuxa_0_a2_0_1, C => - \Chanel_ongoing[2]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_15); - - un1_Cel_ongoing_1_I_197 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2[0]\); - - \Cel_ongoing_RNO_0[0]\ : AO1B - port map(A => N_326, B => \Cel_ongoing_6_i_i_a2_0_0[0]\, C - => \DWACT_ADD_CI_0_partial_sum[0]\, Y => - \Cel_ongoing_6_i_i_0[0]\); - - \Chanel_ongoing_RNIAHBB5[23]\ : OR2A - port map(A => \Chanel_ongoing[23]_net_1\, B => N_286, Y => - N_288); - - sample_out_rot_1 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_1); - - un1_Cel_ongoing_1_I_144 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_13[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_6[0]\); - - un1_Cel_ongoing_1_I_140 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_9[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_4[0]\); - - \Chanel_ongoing_RNIMOPN[2]\ : OR3C - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, C => \Chanel_ongoing[2]_net_1\, - Y => N_250); - - \Chanel_ongoing_RNIDRRF[6]\ : NOR2B - port map(A => \Chanel_ongoing[6]_net_1\, B => - \Chanel_ongoing[5]_net_1\, Y => - Chanel_ongoing_n6_0_i_0_o2_0); - - \Cel_ongoing_RNO[31]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_121, Y => N_450); - - un1_Cel_ongoing_1_I_200 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_7[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_8[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_3[0]\); - - \Chanel_ongoing_RNO[31]\ : XA1C - port map(A => \Chanel_ongoing[31]_net_1\, B => N_335, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n31); - - un1_Cel_ongoing_1_I_133 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \Cel_ongoing[8]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_3[0]\); - - \IIR_CEL_STATE_RNI9GPF[1]\ : OR2 - port map(A => \IIR_CEL_STATE[2]_net_1\, B => - \IIR_CEL_STATE[1]_net_1\, Y => N_567_i_0); - - \Chanel_ongoing_RNI32KK1[23]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_12, B => - Cel_ongoing_0_sqmuxa_0_a2_0_11, C => - Cel_ongoing_0_sqmuxa_0_a2_0_22, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_26); - - \Chanel_ongoing[11]\ : DFN1E1C0 - port map(D => N_462, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[11]_net_1\); - - \Chanel_ongoing_RNI06133[12]\ : OR2A - port map(A => \Chanel_ongoing[12]_net_1\, B => N_264, Y => - N_265); - - un1_Cel_ongoing_1_I_212 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_9[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_10[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_4[0]\); - - \IIR_CEL_STATE[4]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[3]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[4]_net_1\); - - \alu_selected_coeff_RNO[1]\ : NOR3C - port map(A => N_478, B => N_480, C => S_36, Y => N_712); - - \Cel_ongoing_RNI8ROSC[2]\ : OR2A - port map(A => N_796_i, B => N_328, Y => N_523); - - \Cel_ongoing_RNIF326[5]\ : NOR2 - port map(A => \Cel_ongoing[5]_net_1\, B => - \Cel_ongoing[6]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_2[1]\); - - un1_Cel_ongoing_1_I_132 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10_1[0]\, B => - \Cel_ongoing[20]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_9[0]\); - - \Chanel_ongoing_RNO[20]\ : XA1C - port map(A => \Chanel_ongoing[20]_net_1\, B => N_278, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n20); - - \Chanel_ongoing[20]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n20, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[20]_net_1\); - - \IIR_CEL_STATE_i_RNIV1AA[9]\ : OR3 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay_1, C => \IIR_CEL_STATE[4]_net_1\, Y => - N_453); - - \IIR_CEL_STATE_i_RNIF6BBE[9]\ : OR2B - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0_s_0_0, B => - N_452, Y => un1_alu_sel_input_0_sqmuxa_1_i_0_0); - - \IIR_CEL_STATE_i_RNI1V4A[9]\ : OR2A - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => N_451_1); - - GND_i : GND - port map(Y => \GND\); - - \Chanel_ongoing[27]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n27, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[27]_net_1\); - - \Cel_ongoing_RNO[25]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_125, Y => N_444); - - \Cel_ongoing_RNI4OF62[7]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_18[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_17[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_23[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_27[1]\); - - \Chanel_ongoing_RNO_0[7]\ : AX1E - port map(A => N_252_i_0, B => Chanel_ongoing_n6_0_i_0_o2_0, - C => \Chanel_ongoing[7]_net_1\, Y => - Chanel_ongoing_n7_0_i_0_0); - - \Cel_ongoing_RNISFPS5_0[2]\ : OR2 - port map(A => N_325, B => \Cel_ongoing[2]_net_1\, Y => - N_332); - - \Chanel_ongoing_RNIH25D[25]\ : NOR2 - port map(A => \Chanel_ongoing[25]_net_1\, B => - \Chanel_ongoing[26]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_12); - - un1_Cel_ongoing_1_I_154 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_4[0]\, B => - \DWACT_ADD_CI_0_pog_array_3_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_9[0]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - raddr_add1_RNO_0 : NOR3 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay_1, C => \IIR_CEL_STATE[3]_net_1\, Y => - N_737); - - \IIR_CEL_STATE_i_RNIV76I[9]\ : OAI1 - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - sample_val_delay_1, C => N_294, Y => un1_IIR_CEL_STATE_18); - - \Chanel_ongoing_RNO_0[12]\ : XOR2 - port map(A => \Chanel_ongoing[12]_net_1\, B => N_264, Y => - \Chanel_ongoing_RNO_0[12]_net_1\); - - sample_out_rot_0 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_0); - - \Chanel_ongoing_RNIGCKO1[31]\ : NOR3C - port map(A => N_479, B => Cel_ongoing_0_sqmuxa_0_a2_0_4, C - => Cel_ongoing_0_sqmuxa_0_a2_0_18, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_24); - - \IIR_CEL_STATE_RNIBOPF[0]\ : NOR2 - port map(A => \IIR_CEL_STATE[0]_net_1\, B => - \IIR_CEL_STATE[5]_net_1\, Y => un1_IIR_CEL_STATE_20_0_0); - - \IIR_CEL_STATE[5]\ : DFN1E1 - port map(D => N_204, CLK => lclk_c, E => rstn, Q => - \IIR_CEL_STATE[5]_net_1\); - - \Cel_ongoing_RNISU7A[9]\ : NOR2 - port map(A => \Cel_ongoing[9]_net_1\, B => - \Cel_ongoing[10]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_4[1]\); - - un1_Cel_ongoing_1_I_172 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - \Cel_ongoing[25]\ : DFN1C0 - port map(D => N_444, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[25]_net_1\); - - ram_write_RNI8DD3 : INV - port map(A => ram_write_net_1, Y => ram_write_i); - - \IIR_CEL_STATE_RNO[5]\ : AO1 - port map(A => N_328, B => \IIR_CEL_STATE[4]_net_1\, C => - N_353, Y => N_204); - - \IIR_CEL_STATE_RNIKNICD[2]\ : AO1 - port map(A => N_523, B => \IIR_CEL_STATE[4]_net_1\, C => - \IIR_CEL_STATE[2]_net_1\, Y => un1_IIR_CEL_STATE_24); - - \Chanel_ongoing[18]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n18, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[18]_net_1\); - - \Chanel_ongoing_RNI2V2V5[26]\ : OR2B - port map(A => N_291, B => \Chanel_ongoing[26]_net_1\, Y => - N_292); - - \Cel_ongoing_RNO_0[2]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_120, Y => N_465); - - \Chanel_ongoing[16]\ : DFN1E1C0 - port map(D => N_232, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[16]_net_1\); - - \alu_selected_coeff[3]\ : DFN1E1C0 - port map(D => N_714, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => \alu_sel_coeff[3]\); - - un1_Cel_ongoing_1_I_127 : XOR2 - port map(A => \Cel_ongoing[23]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_10[0]\, Y => I_127); - - \Cel_ongoing_RNO[15]\ : NOR3C - port map(A => N_478, B => N_480, C => I_118, Y => - \Cel_ongoing_RNO[15]_net_1\); - - \alu_ctrl[0]\ : DFN1E0C0 - port map(D => N_568_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(0)); - - \Chanel_ongoing_RNI5DJ93[13]\ : NOR2A - port map(A => \Chanel_ongoing[13]_net_1\, B => N_265, Y => - N_270); - - un1_Cel_ongoing_1_I_188 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_5[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_6[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_2[0]\); - - raddr_add1_RNO_1 : NOR3A - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => - \IIR_CEL_STATE[3]_net_1\, C => N_289, Y => N_735); - - un1_Cel_ongoing_1_I_1 : AND2 - port map(A => \Cel_ongoing[0]_net_1\, B => - \IIR_CEL_STATE_RNI87UP_1[4]_net_1\, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - \Chanel_ongoing[14]\ : DFN1E1C0 - port map(D => N_724, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[14]_net_1\); - - \alu_ctrl[2]\ : DFN1E0C0 - port map(D => \IIR_CEL_STATE_i_i[9]\, CLK => lclk_c, CLR - => rstn, E => \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(2)); - - \Chanel_ongoing_RNO[10]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0, B => - N_373_i, Y => N_461); - - \ram_sel_Wdata[1]\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_20, CLK => lclk_c, CLR => - rstn, E => \IIR_CEL_STATE[8]_net_1\, Q => - ram_sel_Wdata(1)); - - \IIR_CEL_STATE_RNI87UP_1[4]\ : OR2 - port map(A => N_326, B => \IIR_CEL_STATE[4]_net_1\, Y => - \IIR_CEL_STATE_RNI87UP_1[4]_net_1\); - - \Cel_ongoing_RNO[4]\ : NOR3C - port map(A => N_478, B => N_480, C => I_119, Y => - \Cel_ongoing_RNO[4]_net_1\); - - \Cel_ongoing_RNIDUKP1[23]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_12[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_11[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_22[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_26[1]\); - - un1_Cel_ongoing_1_I_107 : XOR2 - port map(A => \Cel_ongoing[11]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_4[0]\, Y => I_107); - - \IIR_CEL_STATE_RNIIKQF[5]\ : NOR2 - port map(A => \IIR_CEL_STATE[7]_net_1\, B => - \IIR_CEL_STATE[5]_net_1\, Y => N_289); - - VCC_i : VCC - port map(Y => \VCC\); - - \IIR_CEL_STATE_RNI78PF[1]\ : NOR2 - port map(A => \IIR_CEL_STATE[1]_net_1\, B => - \IIR_CEL_STATE[0]_net_1\, Y => N_294); - - un1_Cel_ongoing_1_I_211 : AND2 - port map(A => \Cel_ongoing[28]_net_1\, B => - \Cel_ongoing[29]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_13[0]\); - - \Chanel_ongoing_RNO_0[11]\ : AX1E - port map(A => \Chanel_ongoing[10]_net_1\, B => N_257, C => - \Chanel_ongoing[11]_net_1\, Y => N_374_i); - - \Cel_ongoing[4]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[4]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[4]_net_1\); - - \IIR_CEL_STATE_RNIFTL4D[4]\ : NOR2 - port map(A => N_796_i, B => N_480_0, Y => - \IIR_CEL_STATE_ns[8]\); - - un1_Cel_ongoing_1_I_186 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_4[0]\); - - \Chanel_ongoing_RNO[21]\ : XA1C - port map(A => \Chanel_ongoing[21]_net_1\, B => N_279, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n21); - - \Chanel_ongoing_RNO[29]\ : XA1C - port map(A => \Chanel_ongoing[29]_net_1\, B => N_295, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n29); - - \IIR_CEL_STATE_RNIGCQF[2]\ : OR2 - port map(A => \IIR_CEL_STATE[8]_net_1\, B => - \IIR_CEL_STATE[2]_net_1\, Y => N_353); - - \Chanel_ongoing_RNIN8BF2[9]\ : NOR3B - port map(A => \Chanel_ongoing[8]_net_1\, B => - \Chanel_ongoing[9]_net_1\, C => N_255, Y => N_257); - - \IIR_CEL_STATE_i_RNI79841[9]\ : OA1 - port map(A => N_294, B => N_451_1, C => N_453, Y => - un1_alu_sel_input_0_sqmuxa_1_i_0_s_0_0); - - \alu_ctrl[1]\ : DFN1E0C0 - port map(D => N_569, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[2]_net_1\, Q => alu_ctrl(1)); - - sample_out_val : DFN1E0C0 - port map(D => \IIR_CEL_STATE[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => N_353, Q => sample_out_val_s); - - \alu_selected_coeff_0_RNIJ954_0[2]\ : NOR2A - port map(A => \alu_sel_coeff_0[2]\, B => S_0, Y => N_717); - - raddr_add1_RNO_3 : NOR2A - port map(A => \IIR_CEL_STATE[3]_net_1\, B => N_274, Y => - raddr_add1_2_i_a2_0_0); - - \Chanel_ongoing[31]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n31, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[31]_net_1\); - - un1_Cel_ongoing_1_I_118 : XOR2 - port map(A => \Cel_ongoing[15]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_6[0]\, Y => I_118); - - un1_Cel_ongoing_1_I_203 : AND2 - port map(A => \Cel_ongoing[20]_net_1\, B => - \Cel_ongoing[21]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_9[0]\); - - sample_out_rot_2 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_2); - - \Chanel_ongoing_RNIS2FS2[11]\ : OR3C - port map(A => \Chanel_ongoing[10]_net_1\, B => N_257, C => - \Chanel_ongoing[11]_net_1\, Y => N_264); - - un1_Cel_ongoing_1_I_202 : AND2 - port map(A => \Cel_ongoing[26]_net_1\, B => - \Cel_ongoing[27]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_12[0]\); - - un1_Cel_ongoing_1_I_198 : AND2 - port map(A => \Cel_ongoing[24]_net_1\, B => - \Cel_ongoing[25]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_11[0]\); - - un1_Cel_ongoing_1_I_151 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10_2[0]\, B => - \Cel_ongoing[28]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_13[0]\); - - \Chanel_ongoing_RNINH8C6[28]\ : OR2A - port map(A => \Chanel_ongoing[28]_net_1\, B => N_293, Y => - N_295); - - \waddr_previous[1]\ : DFN1E0C0 - port map(D => N_729, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => waddr_previous(1)); - - un1_Cel_ongoing_1_I_143 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_3[0]\); - - sample_in_rot_RNIVMA4_2 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_2); - - \Cel_ongoing_RNIFIAG[7]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_4[1]\, B => - \Cel_ongoing[8]_net_1\, C => \Cel_ongoing[7]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_17[1]\); - - \IIR_CEL_STATE_RNI3IM46[4]\ : OR2A - port map(A => \IIR_CEL_STATE[4]_net_1\, B => N_328, Y => - N_480); - - raddr_add1_RNO : NOR3 - port map(A => N_737, B => N_735, C => N_736, Y => - \raddr_add1_RNO\); - - \Chanel_ongoing_RNIDKBU[7]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_3, B => - \Chanel_ongoing[8]_net_1\, C => \Chanel_ongoing[7]_net_1\, - Y => Cel_ongoing_0_sqmuxa_0_a2_0_16); - - \Cel_ongoing_RNIBJ16[3]\ : NOR2 - port map(A => \Cel_ongoing[3]_net_1\, B => - \Cel_ongoing[4]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_1[1]\); - - \alu_selected_coeff_0_RNI88QV6[0]\ : NOR3B - port map(A => N_478, B => N_480, C => \alu_sel_coeff_0[0]\, - Y => alu_selected_coeff_n0); - - \Chanel_ongoing_RNIF25D[15]\ : NOR2 - port map(A => \Chanel_ongoing[15]_net_1\, B => - \Chanel_ongoing[16]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_7); - - \Chanel_ongoing_RNINS8Q[20]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_10, B => - \Chanel_ongoing[20]_net_1\, C => - \Chanel_ongoing[19]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_20); - - un1_Cel_ongoing_1_I_116 : XOR2 - port map(A => \Cel_ongoing[28]_net_1\, B => - \DWACT_ADD_CI_0_g_array_10_2[0]\, Y => I_116); - - \IIR_CEL_STATE_i_RNI4P117[9]\ : OR3B - port map(A => N_478, B => N_480, C => N_274, Y => N_127_0); - - \IIR_CEL_STATE[7]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[6]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[7]_net_1\); - - \Cel_ongoing_RNIESPS[11]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_6[1]\, B => - \Cel_ongoing[12]_net_1\, C => \Cel_ongoing[11]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_18[1]\); - - \Cel_ongoing_RNI9UCE[13]\ : NOR2 - port map(A => \Cel_ongoing[13]_net_1\, B => - \Cel_ongoing[14]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_6[1]\); - - \Cel_ongoing[19]\ : DFN1C0 - port map(D => N_438, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[19]_net_1\); - - un1_Cel_ongoing_1_I_142 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_9[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_11[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_5[0]\); - - \Chanel_ongoing_RNO[11]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0, B => - N_374_i, Y => N_462); - - \Chanel_ongoing_RNO[24]\ : XA1C - port map(A => \Chanel_ongoing[24]_net_1\, B => N_288, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n24); - - \Chanel_ongoing_RNO[19]\ : XA1C - port map(A => \Chanel_ongoing[19]_net_1\, B => N_276, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n19); - - un1_Cel_ongoing_1_I_196 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_2_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_3_1[0]\); - - un1_Cel_ongoing_1_I_184 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_4[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_10_1[0]\); - - \Chanel_ongoing[15]\ : DFN1E1C0 - port map(D => N_229, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[15]_net_1\); - - \Cel_ongoing[31]\ : DFN1C0 - port map(D => N_450, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[31]_net_1\); - - \alu_selected_coeff_RNO[4]\ : NOR3B - port map(A => N_478, B => N_480, C => N_15_i, Y => N_715); - - \Cel_ongoing[30]\ : DFN1C0 - port map(D => N_449, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[30]_net_1\); - - \Chanel_ongoing_RNIOC3H4[19]\ : OR2A - port map(A => \Chanel_ongoing[19]_net_1\, B => N_276, Y => - N_278); - - \Chanel_ongoing_RNO_0[5]\ : XNOR2 - port map(A => \Chanel_ongoing[5]_net_1\, B => N_252_i_0, Y - => Chanel_ongoing_n5_0_i_0_0); - - \Chanel_ongoing[6]\ : DFN1E1C0 - port map(D => N_22, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[6]_net_1\); - - \Chanel_ongoing_RNIVJL71[4]\ : NOR3B - port map(A => \Chanel_ongoing[3]_net_1\, B => - \Chanel_ongoing[4]_net_1\, C => N_250, Y => N_252_i_0); - - \alu_selected_coeff_RNO_0[3]\ : XNOR2 - port map(A => N_717, B => \alu_sel_coeff[3]\, Y => - alu_selected_coeff_n3_0_i_0); - - sample_out_rot : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s); - - \Chanel_ongoing[23]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n23, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[23]_net_1\); - - \Chanel_ongoing[22]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n22, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[22]_net_1\); - - un1_Cel_ongoing_1_I_153 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_6[0]\, B => - \Cel_ongoing[30]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_14[0]\); - - sample_out_rot_4 : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => sample_out_rot_s_4); - - \Cel_ongoing_RNO[7]\ : NOR3C - port map(A => N_478, B => N_480, C => I_99, Y => - \Cel_ongoing_RNO[7]_net_1\); - - sample_in_rot_RNIVMA4_3 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_3); - - un1_Cel_ongoing_1_I_205 : AND2 - port map(A => \Cel_ongoing[16]_net_1\, B => - \Cel_ongoing[17]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_7[0]\); - - \in_sel_src_RNO[0]\ : MX2 - port map(A => N_334, B => N_332, S => - \IIR_CEL_STATE[5]_net_1\, Y => N_268); - - \waddr_previous[0]\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_22, CLK => lclk_c, CLR => - rstn, E => \IIR_CEL_STATE[8]_net_1\, Q => - waddr_previous(0)); - - \Chanel_ongoing_RNIBI4D[13]\ : NOR2 - port map(A => \Chanel_ongoing[13]_net_1\, B => - \Chanel_ongoing[14]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_6); - - \alu_selected_coeff_0[2]\ : DFN1E1C0 - port map(D => N_713, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => \alu_sel_coeff_0[2]\); - - \Chanel_ongoing[21]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n21, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[21]_net_1\); - - \Cel_ongoing_RNIDI7D[31]\ : NOR3A - port map(A => \Cel_ongoing[0]_net_1\, B => - \Cel_ongoing[1]_net_1\, C => \Cel_ongoing[31]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_15[1]\); - - \Chanel_ongoing_RNI3IT34[17]\ : OR2A - port map(A => \Chanel_ongoing[17]_net_1\, B => N_273, Y => - N_275); - - \alu_selected_coeff_0[0]\ : DFN1E1C0 - port map(D => alu_selected_coeff_n0, CLK => lclk_c, CLR => - rstn, E => alu_selected_coeffe, Q => \alu_sel_coeff_0[0]\); - - \Chanel_ongoing_RNIJI5D[17]\ : NOR2 - port map(A => \Chanel_ongoing[17]_net_1\, B => - \Chanel_ongoing[18]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_8); - - un1_Cel_ongoing_1_I_128 : XOR2 - port map(A => \Cel_ongoing[19]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_8[0]\, Y => I_128); - - \Cel_ongoing_RNIKADE[29]\ : NOR2 - port map(A => \Cel_ongoing[29]_net_1\, B => - \Cel_ongoing[30]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_14[1]\); - - \Cel_ongoing_RNO[22]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_126, Y => N_441); - - \Chanel_ongoing_RNIGQ4D[30]\ : NOR2 - port map(A => \Chanel_ongoing[29]_net_1\, B => - \Chanel_ongoing[30]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_14); - - un1_Cel_ongoing_1_I_201 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_2_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_3[0]\); - - un1_Cel_ongoing_1_I_114 : XOR2 - port map(A => \Cel_ongoing[1]_net_1\, B => - \DWACT_ADD_CI_0_TMP[0]\, Y => I_114); - - un1_Cel_ongoing_1_I_110 : XOR2 - port map(A => \Cel_ongoing[27]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_12[0]\, Y => I_110); - - \Chanel_ongoing_RNO[14]\ : XA1B - port map(A => \Chanel_ongoing[14]_net_1\, B => N_270, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => N_724); - - un1_Cel_ongoing_1_I_168 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_9[0]\, B => - \Cel_ongoing[24]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_11[0]\); - - \raddr_rst\ : DFN1E0C0 - port map(D => un1_IIR_CEL_STATE_18, CLK => lclk_c, CLR => - rstn, E => N_353, Q => raddr_rst); - - \Cel_ongoing_RNO[3]\ : NOR3C - port map(A => N_478, B => N_480, C => I_113, Y => - \Cel_ongoing_RNO[3]_net_1\); - - \Cel_ongoing_RNIB6DE[21]\ : NOR2 - port map(A => \Cel_ongoing[21]_net_1\, B => - \Cel_ongoing[22]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_10[1]\); - - un1_Cel_ongoing_1_I_115 : XOR2 - port map(A => \Cel_ongoing[30]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_6[0]\, Y => I_115_4); - - \IIR_CEL_STATE_i_RNO[9]\ : MX2B - port map(A => \IIR_CEL_STATE_i[9]_net_1\, B => N_180, S => - rstn, Y => N_512_i_0); - - un1_Cel_ongoing_1_I_190 : AND2 - port map(A => \Cel_ongoing[2]_net_1\, B => - \Cel_ongoing[3]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1[0]\); - - \Chanel_ongoing_RNI3HRI6[29]\ : OR2A - port map(A => \Chanel_ongoing[29]_net_1\, B => N_295, Y => - N_327); - - \Cel_ongoing_RNIJ6DE[25]\ : NOR2 - port map(A => \Cel_ongoing[25]_net_1\, B => - \Cel_ongoing[26]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_12[1]\); - - \Chanel_ongoing_RNO[26]\ : XA1B - port map(A => \Chanel_ongoing[26]_net_1\, B => N_291, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n26); - - \Cel_ongoing[18]\ : DFN1C0 - port map(D => N_437, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[18]_net_1\); - - \Chanel_ongoing_RNICRRF[4]\ : NOR2 - port map(A => \Chanel_ongoing[4]_net_1\, B => - \Chanel_ongoing[6]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_1); - - un1_Cel_ongoing_1_I_195 : AND2 - port map(A => \Cel_ongoing[8]_net_1\, B => - \Cel_ongoing[9]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_3[0]\); - - un1_Cel_ongoing_1_I_209 : AND2 - port map(A => \Cel_ongoing[18]_net_1\, B => - \Cel_ongoing[19]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_8[0]\); - - \Chanel_ongoing_RNIPHJK1[20]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_8, B => - Cel_ongoing_0_sqmuxa_0_a2_0_7, C => - Cel_ongoing_0_sqmuxa_0_a2_0_20, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_25); - - un1_Cel_ongoing_1_I_126 : XOR2 - port map(A => \Cel_ongoing[22]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_4[0]\, Y => I_126); - - \Cel_ongoing_RNO[12]\ : NOR3C - port map(A => N_478, B => N_480, C => I_101, Y => - \Cel_ongoing_RNO[12]_net_1\); - - \alu_selected_coeff[0]\ : DFN1E1C0 - port map(D => alu_selected_coeff_n0, CLK => lclk_c, CLR => - rstn, E => alu_selected_coeffe, Q => alu_sel_coeff(0)); - - \Chanel_ongoing[19]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n19, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[19]_net_1\); - - \Cel_ongoing[16]\ : DFN1C0 - port map(D => N_435, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[16]_net_1\); - - \Chanel_ongoing_RNO[0]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0_0, B => - \Chanel_ongoing[0]_net_1\, Y => Chanel_ongoing_n0); - - sample_in_rot_RNIVMA4 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_4); - - GND_i_0 : GND - port map(Y => GND_0); - - \Chanel_ongoing_RNO[25]\ : XA1C - port map(A => \Chanel_ongoing[25]_net_1\, B => N_290, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n25); - - \Chanel_ongoing_RNIR7LN4[20]\ : OR2A - port map(A => \Chanel_ongoing[20]_net_1\, B => N_278, Y => - N_279); - - \Chanel_ongoing_RNI5DAQ[27]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_14, B => - \Chanel_ongoing[28]_net_1\, C => - \Chanel_ongoing[27]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_22); - - \Cel_ongoing_RNIN5KP1[15]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_8[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_7[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_20[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_25[1]\); - - \in_sel_src_RNO[1]\ : MX2B - port map(A => \in_sel_src_8_i_a2_0_a2_0_0[1]\, B => N_289, - S => N_332, Y => N_269); - - \Cel_ongoing_RNO[23]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_127, Y => N_442); - - un1_Cel_ongoing_1_I_166 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_4[0]\, B => - \Cel_ongoing[22]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_10[0]\); - - \Chanel_ongoing[28]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n28, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[28]_net_1\); - - \Chanel_ongoing[26]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n26, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[26]_net_1\); - - \Chanel_ongoing_RNO[4]\ : NOR2 - port map(A => Chanel_ongoing_n4_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_11); - - \Chanel_ongoing[2]\ : DFN1E1C0 - port map(D => N_703, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[2]_net_1\); - - un1_Cel_ongoing_1_I_106 : XOR2 - port map(A => \Cel_ongoing[13]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_5[0]\, Y => I_106); - - \Chanel_ongoing_RNO[6]\ : NOR2 - port map(A => Chanel_ongoing_n6_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_22); - - \Chanel_ongoing_RNI5JKR[12]\ : NOR3A - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_6, B => - \Chanel_ongoing[12]_net_1\, C => - \Chanel_ongoing[5]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_18); - - \IIR_CEL_STATE[6]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[5]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[6]_net_1\); - - \Cel_ongoing[17]\ : DFN1C0 - port map(D => N_436, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[17]_net_1\); - - \Chanel_ongoing[24]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n24, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[24]_net_1\); - - \Cel_ongoing_RNO[2]\ : OR2 - port map(A => N_465, B => \IIR_CEL_STATE_ns[8]\, Y => N_227); - - sample_in_rot_RNIVMA4_0 : OR2 - port map(A => sample_val_delay_0, B => sample_in_rotate, Y - => un1_sample_in_rotate_0); - - \Cel_ongoing[11]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[11]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[11]_net_1\); - - \Chanel_ongoing_RNO[2]\ : NOR2A - port map(A => Chanel_ongoing_n2_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_703); - - \Cel_ongoing[10]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[10]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[10]_net_1\); - - un1_Cel_ongoing_1_I_189 : AND2 - port map(A => \Cel_ongoing[6]_net_1\, B => - \Cel_ongoing[7]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_2[0]\); - - sample_in_rot_RNI1NA4 : OR2 - port map(A => sample_val_delay_2, B => sample_in_rotate, Y - => un1_sample_in_rotate); - - un1_Cel_ongoing_1_I_147 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_4[0]\, B => - \Cel_ongoing[16]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_7[0]\); - - \Cel_ongoing_RNO[13]\ : NOR3C - port map(A => N_478, B => N_480, C => I_106, Y => - \Cel_ongoing_RNO[13]_net_1\); - - \Cel_ongoing_RNO[24]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_130, Y => N_443); - - \Chanel_ongoing_RNO[16]\ : XA1C - port map(A => \Chanel_ongoing[16]_net_1\, B => N_272, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => N_232); - - \Cel_ongoing_RNO[20]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_122_4, Y => - N_439); - - \Cel_ongoing[5]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[5]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[5]_net_1\); - - \Cel_ongoing[29]\ : DFN1C0 - port map(D => N_448, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[29]_net_1\); - - \Chanel_ongoing_RNO_0[1]\ : XNOR2 - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, Y => Chanel_ongoing_n1_0_i_0_0); - - \Chanel_ongoing_RNO[27]\ : XA1C - port map(A => \Chanel_ongoing[27]_net_1\, B => N_292, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n27); - - \waddr_previous_RNO[0]\ : AO1B - port map(A => N_328, B => \IIR_CEL_STATE[4]_net_1\, C => - N_334, Y => un1_IIR_CEL_STATE_22); - - \ram_sel_Wdata[0]\ : DFN1E0C0 - port map(D => N_567_i_0, CLK => lclk_c, CLR => rstn, E => - \IIR_CEL_STATE[8]_net_1\, Q => ram_sel_Wdata(0)); - - un1_Cel_ongoing_1_I_138 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_4[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_7[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_3[0]\); - - \Chanel_ongoing[4]\ : DFN1E1C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[4]_net_1\); - - \Cel_ongoing_RNO[0]\ : OR3C - port map(A => \Cel_ongoing_6_i_i_0[0]\, B => N_457, C => - N_454, Y => N_206); - - \Chanel_ongoing_RNO_0[31]\ : OR2A - port map(A => \Chanel_ongoing[30]_net_1\, B => N_327, Y => - N_335); - - \Chanel_ongoing_RNO_0[10]\ : XNOR2 - port map(A => N_257, B => \Chanel_ongoing[10]_net_1\, Y => - N_373_i); - - \Chanel_ongoing_RNO[8]\ : NOR2A - port map(A => Chanel_ongoing_n8_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_651_i_0); - - \Chanel_ongoing_RNO[15]\ : XA1C - port map(A => \Chanel_ongoing[15]_net_1\, B => N_271, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => N_229); - - \Chanel_ongoing[7]\ : DFN1E1C0 - port map(D => N_650, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[7]_net_1\); - - \Cel_ongoing_RNO[8]\ : NOR3C - port map(A => N_478, B => N_480, C => I_102, Y => - \Cel_ongoing_RNO[8]_net_1\); - - un1_Cel_ongoing_1_I_124 : XOR2 - port map(A => \Cel_ongoing[21]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_9[0]\, Y => I_124); - - un1_Cel_ongoing_1_I_120 : XOR2 - port map(A => \Cel_ongoing[2]_net_1\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_120); - - un1_Cel_ongoing_1_I_111 : XOR2 - port map(A => \Cel_ongoing[16]_net_1\, B => - \DWACT_ADD_CI_0_g_array_4[0]\, Y => I_111); - - \Cel_ongoing[13]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[13]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[13]_net_1\); - - \Cel_ongoing[12]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[12]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[12]_net_1\); - - \Chanel_ongoing_RNO[22]\ : XA1C - port map(A => \Chanel_ongoing[22]_net_1\, B => - \Chanel_ongoing_RNIV67U4[21]_net_1\, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n22); - - un1_Cel_ongoing_1_I_125 : XOR2 - port map(A => \Cel_ongoing[25]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_11[0]\, Y => I_125); - - \Chanel_ongoing_RNO[28]\ : XA1C - port map(A => \Chanel_ongoing[28]_net_1\, B => N_293, C => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => - Chanel_ongoing_n28); - - \Chanel_ongoing_RNIGNNM3[2]\ : NOR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_16, B => - Cel_ongoing_0_sqmuxa_0_a2_0_15, C => - Cel_ongoing_0_sqmuxa_0_a2_0_24, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_27); - - un1_Cel_ongoing_1_I_178 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_10[0]\); - - \Chanel_ongoing_RNIDDGA4[18]\ : OR2A - port map(A => \Chanel_ongoing[18]_net_1\, B => N_275, Y => - N_276); - - \Cel_ongoing_RNO[14]\ : NOR3C - port map(A => N_478, B => N_480, C => I_112, Y => - \Cel_ongoing_RNO[14]_net_1\); - - \Cel_ongoing_RNO[1]\ : NOR3C - port map(A => N_478, B => N_480, C => I_114, Y => - \Cel_ongoing_RNO[1]_net_1\); - - \Cel_ongoing_RNO[10]\ : NOR3C - port map(A => N_478, B => N_480, C => I_105_4, Y => - \Cel_ongoing_RNO[10]_net_1\); - - un1_Cel_ongoing_1_I_191 : AND2 - port map(A => \Cel_ongoing[12]_net_1\, B => - \Cel_ongoing[13]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_5[0]\); - - \IIR_CEL_STATE_RNIR5FE7[2]\ : OR3C - port map(A => N_478, B => N_480, C => N_353, Y => - alu_selected_coeffe); - - \Chanel_ongoing_RNICBVV6[20]\ : OR3C - port map(A => Cel_ongoing_0_sqmuxa_0_a2_0_26, B => - Cel_ongoing_0_sqmuxa_0_a2_0_25, C => - Cel_ongoing_0_sqmuxa_0_a2_0_27, Y => N_796_i); - - un1_Cel_ongoing_1_I_136 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_2[0]\); - - \Chanel_ongoing_RNICML56[27]\ : OR2A - port map(A => \Chanel_ongoing[27]_net_1\, B => N_292, Y => - N_293); - - un1_Cel_ongoing_1_I_182 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_9[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_10_2[0]\); - - un1_Cel_ongoing_1_I_71 : XOR2 - port map(A => \Cel_ongoing[0]_net_1\, B => - \IIR_CEL_STATE_RNI87UP_1[4]_net_1\, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - un1_Cel_ongoing_1_I_119 : XOR2 - port map(A => \Cel_ongoing[4]_net_1\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_119); - - un1_Cel_ongoing_1_I_104 : XOR2 - port map(A => \Cel_ongoing[6]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_104); - - un1_Cel_ongoing_1_I_100 : XOR2 - port map(A => \Cel_ongoing[5]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_100); - - \Chanel_ongoing_RNI3RRF[1]\ : NOR2 - port map(A => \Chanel_ongoing[1]_net_1\, B => - \Chanel_ongoing[0]_net_1\, Y => N_479); - - \Cel_ongoing[6]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[6]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[6]_net_1\); - - \IIR_CEL_STATE[3]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[7]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[3]_net_1\); - - \Cel_ongoing_RNO[29]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_109, Y => N_448); - - raddr_add1_RNO_2 : NOR2B - port map(A => raddr_add1_2_i_a2_0_0, B => N_328, Y => N_736); - - \IIR_CEL_STATE_RNIPMNN[6]\ : NOR3 - port map(A => \IIR_CEL_STATE[3]_net_1\, B => - \IIR_CEL_STATE[6]_net_1\, C => \IIR_CEL_STATE[7]_net_1\, - Y => N_334); - - \Chanel_ongoing_RNIBO5G3[14]\ : OR2B - port map(A => N_270, B => \Chanel_ongoing[14]_net_1\, Y => - N_271); - - \Chanel_ongoing[0]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n0, CLK => lclk_c, CLR => rstn, - E => N_127_0, Q => \Chanel_ongoing[0]_net_1\); - - \Cel_ongoing_RNO[6]\ : NOR3C - port map(A => N_478, B => N_480, C => I_104, Y => - \Cel_ongoing_RNO[6]_net_1\); - - un1_Cel_ongoing_1_I_206 : AND2 - port map(A => \Cel_ongoing[14]_net_1\, B => - \Cel_ongoing[15]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_6[0]\); - - un1_Cel_ongoing_1_I_105 : XOR2 - port map(A => \Cel_ongoing[10]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_1[0]\, Y => I_105_4); - - \Cel_ongoing[14]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[14]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[14]_net_1\); - - \Cel_ongoing_RNIHUCE[17]\ : NOR2 - port map(A => \Cel_ongoing[17]_net_1\, B => - \Cel_ongoing[18]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_8[1]\); - - \Cel_ongoing[9]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[9]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[9]_net_1\); - - sample_in_rot : DFN1E0C0 - port map(D => sample_in_rot_2, CLK => lclk_c, CLR => rstn, - E => N_353, Q => sample_in_rotate); - - un1_Cel_ongoing_1_I_199 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_11[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_12[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_5[0]\); - - \Chanel_ongoing_RNO[17]\ : XA1C - port map(A => \Chanel_ongoing[17]_net_1\, B => N_273, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n17); - - \alu_selected_coeff[1]\ : DFN1E1C0 - port map(D => N_712, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => alu_sel_coeff(1)); - - \Cel_ongoing_RNI79BP[3]\ : NOR3C - port map(A => \in_sel_src_8_i_a2_0_o2_0_2[1]\, B => - \in_sel_src_8_i_a2_0_o2_0_1[1]\, C => - \in_sel_src_8_i_a2_0_o2_0_15[1]\, Y => - \in_sel_src_8_i_a2_0_o2_0_23[1]\); - - \Cel_ongoing[8]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[8]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[8]_net_1\); - - \IIR_CEL_STATE[8]\ : DFN1E1 - port map(D => N_274, CLK => lclk_c, E => rstn, Q => - \IIR_CEL_STATE[8]_net_1\); - - \Cel_ongoing_RNIDUCE[15]\ : NOR2 - port map(A => \Cel_ongoing[15]_net_1\, B => - \Cel_ongoing[16]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_7[1]\); - - \raddr_add1\ : DFN1C0 - port map(D => \raddr_add1_RNO\, CLK => lclk_c, CLR => rstn, - Q => raddr_add1); - - \IIR_CEL_STATE[1]\ : DFN1E1 - port map(D => \IIR_CEL_STATE_ns[8]\, CLK => lclk_c, E => - rstn, Q => \IIR_CEL_STATE[1]_net_1\); - - \alu_sel_input\ : DFN1E0C0 - port map(D => alu_sel_input_1, CLK => lclk_c, CLR => rstn, - E => un1_IIR_CEL_STATE_18, Q => alu_sel_input); - - \ram_write\ : DFN1E0C0 - port map(D => ram_write_2, CLK => lclk_c, CLR => rstn, E - => \IIR_CEL_STATE[8]_net_1\, Q => ram_write_net_1); - - \IIR_CEL_STATE_i_RNO_0[9]\ : AO1D - port map(A => sample_val_delay_1, B => - \IIR_CEL_STATE_i[9]_net_1\, C => \IIR_CEL_STATE[0]_net_1\, - Y => N_180); - - \Chanel_ongoing[10]\ : DFN1E1C0 - port map(D => N_461, CLK => lclk_c, CLR => rstn, E => - N_127_0, Q => \Chanel_ongoing[10]_net_1\); - - \in_sel_src[1]\ : DFN1E0C0 - port map(D => N_269, CLK => lclk_c, CLR => rstn, E => - un1_IIR_CEL_STATE_24, Q => in_sel_src(1)); - - un1_Cel_ongoing_1_I_204 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_1[0]\); - - un1_Cel_ongoing_1_I_113 : XOR2 - port map(A => \Cel_ongoing[3]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_113); - - \Chanel_ongoing[17]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n17, CLK => lclk_c, CLR => - rstn, E => N_127_0, Q => \Chanel_ongoing[17]_net_1\); - - \IIR_CEL_STATE_RNI87UP[4]\ : OR2A - port map(A => N_326, B => \IIR_CEL_STATE[4]_net_1\, Y => - N_478); - - \Cel_ongoing[7]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[7]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[7]_net_1\); - - \Cel_ongoing_RNO[30]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_115_4, Y => - N_449); - - \Cel_ongoing[28]\ : DFN1C0 - port map(D => N_447, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[28]_net_1\); - - \Chanel_ongoing_RNO[12]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0_0, B => - \Chanel_ongoing_RNO_0[12]_net_1\, Y => N_216_i); - - \Chanel_ongoing[25]\ : DFN1E1C0 - port map(D => Chanel_ongoing_n25, CLK => lclk_c, CLR => - rstn, E => N_127, Q => \Chanel_ongoing[25]_net_1\); - - \Cel_ongoing_RNO[19]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_128, Y => N_438); - - \Cel_ongoing_RNIBHQS[27]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_14[1]\, B => - \Cel_ongoing[28]_net_1\, C => \Cel_ongoing[27]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_22[1]\); - - \Cel_ongoing_RNO[28]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_116, Y => N_447); - - \Cel_ongoing_RNIF6DE[23]\ : NOR2 - port map(A => \Cel_ongoing[23]_net_1\, B => - \Cel_ongoing[24]_net_1\, Y => - \in_sel_src_8_i_a2_0_o2_0_11[1]\); - - \IIR_CEL_STATE_i_RNIPVC2[9]\ : NOR2A - port map(A => sample_val_delay_2, B => - \IIR_CEL_STATE_i[9]_net_1\, Y => N_274); - - \Chanel_ongoing_RNO[18]\ : XA1C - port map(A => \Chanel_ongoing[18]_net_1\, B => N_275, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n18); - - \Chanel_ongoing_RNIPBGO5[25]\ : NOR2A - port map(A => \Chanel_ongoing[25]_net_1\, B => N_290, Y => - N_291); - - un1_Cel_ongoing_1_I_193 : AND2 - port map(A => \Cel_ongoing[4]_net_1\, B => - \Cel_ongoing[5]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - \Cel_ongoing_RNIP8QS[19]\ : NOR3A - port map(A => \in_sel_src_8_i_a2_0_o2_0_10[1]\, B => - \Cel_ongoing[20]_net_1\, C => \Cel_ongoing[19]_net_1\, Y - => \in_sel_src_8_i_a2_0_o2_0_20[1]\); - - \Chanel_ongoing_RNO[1]\ : NOR2 - port map(A => Chanel_ongoing_n1_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_18); - - \Chanel_ongoing_RNII7OM3[15]\ : OR2A - port map(A => \Chanel_ongoing[15]_net_1\, B => N_271, Y => - N_272); - - \Cel_ongoing[26]\ : DFN1C0 - port map(D => N_445, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[26]_net_1\); - - un1_Cel_ongoing_1_I_112 : XOR2 - port map(A => \Cel_ongoing[14]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_2[0]\, Y => I_112); - - un1_Cel_ongoing_1_I_207 : AND2 - port map(A => \Cel_ongoing[10]_net_1\, B => - \Cel_ongoing[11]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_4[0]\); - - \Chanel_ongoing_RNISOFE[9]\ : NOR2 - port map(A => \Chanel_ongoing[9]_net_1\, B => - \Chanel_ongoing[10]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_3); - - \Chanel_ongoing[9]\ : DFN1E1C0 - port map(D => N_460, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[9]_net_1\); - - \Chanel_ongoing_RNO[3]\ : AO1A - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0, B => - N_336_i_i_0, C => \IIR_CEL_STATE_ns[8]\, Y => N_221); - - \Chanel_ongoing_RNO[5]\ : NOR2 - port map(A => Chanel_ongoing_n5_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_20); - - un1_Cel_ongoing_1_I_130 : XOR2 - port map(A => \Cel_ongoing[24]_net_1\, B => - \DWACT_ADD_CI_0_g_array_9[0]\, Y => I_130); - - \Chanel_ongoing_RNI924D[21]\ : NOR2 - port map(A => \Chanel_ongoing[21]_net_1\, B => - \Chanel_ongoing[22]_net_1\, Y => - Cel_ongoing_0_sqmuxa_0_a2_0_10); - - \alu_ctrl_RNO[1]\ : OR2 - port map(A => \IIR_CEL_STATE[8]_net_1\, B => - \IIR_CEL_STATE[4]_net_1\, Y => N_569); - - \Cel_ongoing[3]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[3]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[3]_net_1\); - - \Chanel_ongoing_RNO_0[2]\ : AX1C - port map(A => \Chanel_ongoing[0]_net_1\, B => - \Chanel_ongoing[1]_net_1\, C => \Chanel_ongoing[2]_net_1\, - Y => Chanel_ongoing_n2_0_i_0_0); - - \Chanel_ongoing_RNO[9]\ : NOR2 - port map(A => un1_alu_sel_input_0_sqmuxa_1_i_0, B => - N_372_i, Y => N_460); - - un1_Cel_ongoing_1_I_121 : XOR2 - port map(A => \Cel_ongoing[31]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_14[0]\, Y => I_121); - - \Cel_ongoing_RNO[18]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_123, Y => N_437); - - un1_Cel_ongoing_1_I_135 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_1[0]\, B => - \Cel_ongoing[10]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_4[0]\); - - \IIR_CEL_STATE[0]\ : DFN1E1 - port map(D => \IIR_CEL_STATE[1]_net_1\, CLK => lclk_c, E - => rstn, Q => \IIR_CEL_STATE[0]_net_1\); - - \Cel_ongoing[27]\ : DFN1C0 - port map(D => N_446, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[27]_net_1\); - - \alu_selected_coeff[2]\ : DFN1E1C0 - port map(D => N_713, CLK => lclk_c, CLR => rstn, E => - alu_selected_coeffe, Q => alu_sel_coeff(2)); - - \alu_ctrl_RNO[2]\ : INV - port map(A => \IIR_CEL_STATE_i[9]_net_1\, Y => - \IIR_CEL_STATE_i_i[9]\); - - \Chanel_ongoing_RNI4DFV1[7]\ : OR3C - port map(A => N_252_i_0, B => Chanel_ongoing_n6_0_i_0_o2_0, - C => \Chanel_ongoing[7]_net_1\, Y => N_255); - - \Cel_ongoing[21]\ : DFN1C0 - port map(D => N_440, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[21]_net_1\); - - \Cel_ongoing_RNO_2[0]\ : OR2 - port map(A => un1_IIR_CEL_STATE_18, B => N_480_0, Y => - N_454); - - \Cel_ongoing_RNO[27]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_110, Y => N_446); - - \Cel_ongoing[20]\ : DFN1C0 - port map(D => N_439, CLK => lclk_c, CLR => rstn, Q => - \Cel_ongoing[20]_net_1\); - - un1_Cel_ongoing_1_I_210 : AND2 - port map(A => \Cel_ongoing[22]_net_1\, B => - \Cel_ongoing[23]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_10[0]\); - - \Chanel_ongoing_RNO_0[8]\ : XNOR2 - port map(A => \Chanel_ongoing[8]_net_1\, B => N_255, Y => - Chanel_ongoing_n8_0_i_0_0); - - \Cel_ongoing[1]\ : DFN1C0 - port map(D => \Cel_ongoing_RNO[1]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \Cel_ongoing[1]_net_1\); - - un1_Cel_ongoing_1_I_174 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_1[0]\); - - un1_Cel_ongoing_1_I_170 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_5[0]\, B => - \Cel_ongoing[26]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_12[0]\); - - \Cel_ongoing_RNO[26]\ : NOR3C - port map(A => N_478_0, B => N_480_0, C => I_129_4, Y => - N_445); - - un1_Cel_ongoing_1_I_129 : XOR2 - port map(A => \Cel_ongoing[26]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_5[0]\, Y => I_129_4); - - \Chanel_ongoing_RNO_0[4]\ : AX1A - port map(A => N_250, B => \Chanel_ongoing[3]_net_1\, C => - \Chanel_ongoing[4]_net_1\, Y => Chanel_ongoing_n4_0_i_0_0); - - \Chanel_ongoing_RNO[7]\ : NOR2 - port map(A => Chanel_ongoing_n7_0_i_0_0, B => - un1_alu_sel_input_0_sqmuxa_1_i_0_0, Y => N_650); - - \waddr_previous_RNO[1]\ : OR2 - port map(A => un1_IIR_CEL_STATE_20, B => N_567_i_0, Y => - N_729); - - \alu_ctrl_RNO[0]\ : OR3A - port map(A => N_289, B => \IIR_CEL_STATE[3]_net_1\, C => - \IIR_CEL_STATE[6]_net_1\, Y => N_568_i_0); - - \Chanel_ongoing_RNO[23]\ : XA1C - port map(A => \Chanel_ongoing[23]_net_1\, B => N_286, C => - un1_alu_sel_input_0_sqmuxa_1_i_0, Y => Chanel_ongoing_n23); - - \Chanel_ongoing[5]\ : DFN1E1C0 - port map(D => N_20, CLK => lclk_c, CLR => rstn, E => N_127, - Q => \Chanel_ongoing[5]_net_1\); - - un1_Cel_ongoing_1_I_101 : XOR2 - port map(A => \Cel_ongoing[12]_net_1\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, Y => I_101); - - \Cel_ongoing_RNO_3[0]\ : OR2B - port map(A => N_328, B => \IIR_CEL_STATE[4]_net_1\, Y => - \Cel_ongoing_6_i_i_a2_0_0[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity IIR_CEL_CTRLR_v2 is - - port( sample_filter_v2_out_0 : out std_logic; - sample_filter_v2_out_1 : out std_logic; - sample_filter_v2_out_2 : out std_logic; - sample_filter_v2_out_3 : out std_logic; - sample_filter_v2_out_4 : out std_logic; - sample_filter_v2_out_5 : out std_logic; - sample_filter_v2_out_6 : out std_logic; - sample_filter_v2_out_7 : out std_logic; - sample_filter_v2_out_8 : out std_logic; - sample_filter_v2_out_9 : out std_logic; - sample_filter_v2_out_10 : out std_logic; - sample_filter_v2_out_11 : out std_logic; - sample_filter_v2_out_12 : out std_logic; - sample_filter_v2_out_13 : out std_logic; - sample_filter_v2_out_14 : out std_logic; - sample_filter_v2_out_15 : out std_logic; - sample_filter_v2_out_18 : out std_logic; - sample_filter_v2_out_19 : out std_logic; - sample_filter_v2_out_20 : out std_logic; - sample_filter_v2_out_21 : out std_logic; - sample_filter_v2_out_22 : out std_logic; - sample_filter_v2_out_23 : out std_logic; - sample_filter_v2_out_24 : out std_logic; - sample_filter_v2_out_25 : out std_logic; - sample_filter_v2_out_26 : out std_logic; - sample_filter_v2_out_27 : out std_logic; - sample_filter_v2_out_28 : out std_logic; - sample_filter_v2_out_29 : out std_logic; - sample_filter_v2_out_30 : out std_logic; - sample_filter_v2_out_31 : out std_logic; - sample_filter_v2_out_32 : out std_logic; - sample_filter_v2_out_33 : out std_logic; - sample_filter_v2_out_36 : out std_logic; - sample_filter_v2_out_37 : out std_logic; - sample_filter_v2_out_38 : out std_logic; - sample_filter_v2_out_39 : out std_logic; - sample_filter_v2_out_40 : out std_logic; - sample_filter_v2_out_41 : out std_logic; - sample_filter_v2_out_42 : out std_logic; - sample_filter_v2_out_43 : out std_logic; - sample_filter_v2_out_44 : out std_logic; - sample_filter_v2_out_45 : out std_logic; - sample_filter_v2_out_46 : out std_logic; - sample_filter_v2_out_47 : out std_logic; - sample_filter_v2_out_48 : out std_logic; - sample_filter_v2_out_49 : out std_logic; - sample_filter_v2_out_50 : out std_logic; - sample_filter_v2_out_51 : out std_logic; - sample_filter_v2_out_54 : out std_logic; - sample_filter_v2_out_55 : out std_logic; - sample_filter_v2_out_56 : out std_logic; - sample_filter_v2_out_57 : out std_logic; - sample_filter_v2_out_58 : out std_logic; - sample_filter_v2_out_59 : out std_logic; - sample_filter_v2_out_60 : out std_logic; - sample_filter_v2_out_61 : out std_logic; - sample_filter_v2_out_62 : out std_logic; - sample_filter_v2_out_63 : out std_logic; - sample_filter_v2_out_64 : out std_logic; - sample_filter_v2_out_65 : out std_logic; - sample_filter_v2_out_66 : out std_logic; - sample_filter_v2_out_67 : out std_logic; - sample_filter_v2_out_68 : out std_logic; - sample_filter_v2_out_69 : out std_logic; - sample_filter_v2_out_90 : out std_logic; - sample_filter_v2_out_91 : out std_logic; - sample_filter_v2_out_92 : out std_logic; - sample_filter_v2_out_93 : out std_logic; - sample_filter_v2_out_94 : out std_logic; - sample_filter_v2_out_95 : out std_logic; - sample_filter_v2_out_96 : out std_logic; - sample_filter_v2_out_97 : out std_logic; - sample_filter_v2_out_98 : out std_logic; - sample_filter_v2_out_99 : out std_logic; - sample_filter_v2_out_100 : out std_logic; - sample_filter_v2_out_101 : out std_logic; - sample_filter_v2_out_102 : out std_logic; - sample_filter_v2_out_103 : out std_logic; - sample_filter_v2_out_104 : out std_logic; - sample_filter_v2_out_105 : out std_logic; - sample_filter_v2_out_108 : out std_logic; - sample_filter_v2_out_126 : out std_logic; - sample_filter_v2_out_109 : out std_logic; - sample_filter_v2_out_127 : out std_logic; - sample_filter_v2_out_110 : out std_logic; - sample_filter_v2_out_128 : out std_logic; - sample_filter_v2_out_111 : out std_logic; - sample_filter_v2_out_129 : out std_logic; - sample_filter_v2_out_112 : out std_logic; - sample_filter_v2_out_130 : out std_logic; - sample_filter_v2_out_113 : out std_logic; - sample_filter_v2_out_131 : out std_logic; - sample_filter_v2_out_114 : out std_logic; - sample_filter_v2_out_132 : out std_logic; - sample_filter_v2_out_115 : out std_logic; - sample_filter_v2_out_133 : out std_logic; - sample_filter_v2_out_116 : out std_logic; - sample_filter_v2_out_134 : out std_logic; - sample_filter_v2_out_117 : out std_logic; - sample_filter_v2_out_135 : out std_logic; - sample_filter_v2_out_118 : out std_logic; - sample_filter_v2_out_136 : out std_logic; - sample_filter_v2_out_119 : out std_logic; - sample_filter_v2_out_137 : out std_logic; - sample_filter_v2_out_120 : out std_logic; - sample_filter_v2_out_138 : out std_logic; - sample_filter_v2_out_121 : out std_logic; - sample_filter_v2_out_139 : out std_logic; - sample_filter_v2_out_122 : out std_logic; - sample_filter_v2_out_140 : out std_logic; - sample_filter_v2_out_123 : out std_logic; - sample_filter_v2_out_141 : out std_logic; - sample_4 : in std_logic_vector(15 downto 0); - sample_5 : in std_logic_vector(15 downto 0); - sample_3 : in std_logic_vector(15 downto 0); - sample_2 : in std_logic_vector(15 downto 0); - sample_6 : in std_logic_vector(15 downto 0); - sample_1 : in std_logic_vector(15 downto 0); - sample_0 : in std_logic_vector(15 downto 0); - sample_7 : in std_logic_vector(15 downto 0); - IIR_CEL_CTRLR_v2_VCC : in std_logic; - IIR_CEL_CTRLR_v2_GND : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_filter_v2_out_val : out std_logic; - sample_val_delay : in std_logic; - sample_val_delay_5 : in std_logic; - sample_val_delay_4 : in std_logic; - sample_val_delay_3 : in std_logic; - sample_val_delay_2 : in std_logic; - sample_val_delay_1 : in std_logic; - sample_val_delay_0 : in std_logic - ); - -end IIR_CEL_CTRLR_v2; - -architecture DEF_ARCH of IIR_CEL_CTRLR_v2 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2_DATAFLOW - port( alu_ctrl : in std_logic_vector(2 downto 0) := (others => 'U'); - alu_sel_coeff_0_2 : in std_logic := 'U'; - alu_sel_coeff_0_0 : in std_logic := 'U'; - alu_sel_coeff : in std_logic_vector(4 downto 0) := (others => 'U'); - S_0 : out std_logic; - S_36 : out std_logic; - waddr_previous : in std_logic_vector(1 downto 0) := (others => 'U'); - sample_0 : in std_logic_vector(14 downto 0) := (others => 'U'); - sample_in_buf : in std_logic_vector(143 downto 129) := (others => 'U'); - ram_sel_Wdata : in std_logic_vector(1 downto 0) := (others => 'U'); - sample_out_s_1 : out std_logic; - sample_out_s_2 : out std_logic; - sample_out_s_0 : out std_logic; - sample_out_s_3 : out std_logic; - sample_out_s_15 : out std_logic; - sample_out_s_14 : out std_logic; - sample_out_s_13 : out std_logic; - sample_out_s_12 : out std_logic; - sample_out_s_11 : out std_logic; - sample_out_s_10 : out std_logic; - sample_out_s_9 : out std_logic; - sample_out_s_8 : out std_logic; - sample_out_s_7 : out std_logic; - sample_out_s_6 : out std_logic; - sample_out_s_5 : out std_logic; - sample_out_s_4 : out std_logic; - sample_in_s_1 : in std_logic_vector(17 to 17) := (others => 'U'); - in_sel_src : in std_logic_vector(1 downto 0) := (others => 'U'); - raddr_rst : in std_logic := 'U'; - raddr_add1 : in std_logic := 'U'; - ram_write : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_DATAFLOW_GND : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_DATAFLOW_VCC : in std_logic := 'U'; - ram_write_i : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_val_delay_5 : in std_logic := 'U'; - sample_val_delay_1 : in std_logic := 'U'; - sample_val_delay_0 : in std_logic := 'U'; - alu_sel_input : in std_logic := 'U' - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2_CONTROL - port( alu_ctrl : out std_logic_vector(2 downto 0); - ram_sel_Wdata : out std_logic_vector(1 downto 0); - waddr_previous : out std_logic_vector(1 downto 0); - in_sel_src : out std_logic_vector(1 downto 0); - alu_sel_coeff : out std_logic_vector(4 downto 0); - S_36 : in std_logic := 'U'; - S_0 : in std_logic := 'U'; - alu_sel_coeff_0_2 : out std_logic; - alu_sel_coeff_0_0 : out std_logic; - sample_out_rot_s : out std_logic; - sample_out_val_s : out std_logic; - raddr_rst : out std_logic; - alu_sel_input : out std_logic; - raddr_add1 : out std_logic; - un1_sample_in_rotate : out std_logic; - sample_val_delay_2 : in std_logic := 'U'; - sample_val_delay_1 : in std_logic := 'U'; - ram_write : out std_logic; - ram_write_i : out std_logic; - un1_sample_in_rotate_0 : out std_logic; - un1_sample_in_rotate_1 : out std_logic; - un1_sample_in_rotate_2 : out std_logic; - un1_sample_in_rotate_3 : out std_logic; - sample_val_delay_0 : in std_logic := 'U'; - un1_sample_in_rotate_4 : out std_logic; - sample_out_rot_s_0 : out std_logic; - sample_out_rot_s_1 : out std_logic; - sample_out_rot_s_2 : out std_logic; - sample_out_rot_s_3 : out std_logic; - sample_out_rot_s_4 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal \sample_in_buf_581[9]\, \sample_in_buf[135]\, - \sample_in_buf_637[135]\, \sample_in_buf[117]\, - \sample_in_buf_645[10]\, \sample_in_buf[136]\, - \sample_in_buf_701[136]\, \sample_in_buf[118]\, - \sample_in_buf_389[6]\, \sample_in_buf[132]\, - \sample_in_buf_445[132]\, \sample_in_buf[114]\, - \sample_in_buf_261[4]\, \sample_in_buf[130]\, - \sample_in_buf_317[130]\, \sample_in_buf[112]\, - \sample_in_buf_517[8]\, \sample_in_buf[134]\, - \sample_in_buf_573[134]\, \sample_in_buf[116]\, - \sample_in_buf_325[5]\, \sample_in_buf[131]\, - \sample_in_buf_381[131]\, \sample_in_buf[113]\, - \sample_in_buf_837[13]\, \sample_in_buf[139]\, - \sample_in_buf_197[3]\, \sample_in_buf[129]\, - \sample_in_buf_253[129]\, \sample_in_buf[111]\, - \sample_in_buf_1029[16]\, \sample_in_buf[142]\, - \sample_in_buf_1085[142]\, \sample_in_buf[124]\, - \sample_in_buf_709[11]\, \sample_in_buf[137]\, - \sample_in_buf_5[0]\, \sample_in_buf[127]\, - \sample_in_buf_61[126]\, \sample_in_buf[109]\, - \sample_in_s_1[17]\, \sample_in_buf_453[7]\, - \sample_in_buf[133]\, \sample_in_buf_509[133]\, - \sample_in_buf[115]\, \sample_in_buf_1021[141]\, - \sample_in_buf[123]\, \sample_in_buf_1013[123]\, - \sample_in_buf[105]\, \sample_in_buf_973[33]\, - \sample_in_buf[15]\, \sample_in_buf_885[121]\, - \sample_in_buf[103]\, \sample_in_buf_53[108]\, - \sample_in_buf[90]\, \sample_in_buf_685[100]\, - \sample_in_buf[82]\, \sample_in_buf_357[77]\, - \sample_in_buf[59]\, \sample_in_buf_229[75]\, - \sample_in_buf[57]\, \sample_in_buf_1109[53]\, - \sample_in_buf[35]\, \sample_in_buf_661[46]\, - \sample_in_buf[28]\, \sample_in_buf_717[29]\, - \sample_in_buf[11]\, \sample_in_buf_13[18]\, - \sample_in_buf[1]\, \sample_in_buf_1005[105]\, - \sample_in_buf[87]\, \sample_in_buf_413[60]\, - \sample_in_buf[42]\, \sample_in_buf_205[21]\, - \sample_in_buf[3]\, \sample_in_buf_693[118]\, - \sample_in_buf[100]\, \sample_in_buf_629[117]\, - \sample_in_buf[99]\, \sample_in_buf_309[112]\, - \sample_in_buf[94]\, \sample_in_buf_621[99]\, - \sample_in_buf[81]\, \sample_in_buf_557[98]\, - \sample_in_buf[80]\, \sample_in_buf_1061[88]\, - \sample_in_buf[70]\, \sample_in_buf_1053[70]\, - \sample_in_buf[52]\, \sample_in_buf_925[68]\, - \sample_in_buf[50]\, \sample_in_buf_541[62]\, - \sample_in_buf[44]\, \sample_in_buf_597[45]\, - \sample_in_buf[27]\, \sample_in_buf_333[23]\, - \sample_in_buf[5]\, \sample_in_buf_269[22]\, - \sample_in_buf[4]\, \sample_in_buf_765[137]\, - \sample_in_buf[119]\, \sample_in_buf_1077[124]\, - \sample_in_buf[106]\, \sample_in_buf_485[79]\, - \sample_in_buf[61]\, \sample_in_buf_733[65]\, - \sample_in_buf[47]\, \sample_in_buf_397[24]\, - \sample_in_buf[6]\, \sample_in_buf_957[140]\, - \sample_in_buf[122]\, \sample_in_buf_429[96]\, - \sample_in_buf[78]\, \sample_in_buf_1037[34]\, - \sample_in_buf[16]\, \sample_in_buf_461[25]\, - \sample_in_buf[7]\, \sample_in_buf_901[14]\, - \sample_in_buf[140]\, \sample_in_buf_1141[125]\, - \sample_in_buf[107]\, \sample_in_buf_677[82]\, - \sample_in_buf[64]\, \sample_in_buf_797[66]\, - \sample_in_buf[48]\, \sample_in_buf_405[42]\, - \sample_in_buf[24]\, \sample_in_buf_525[26]\, - \sample_in_buf[8]\, \sample_in_buf_565[116]\, - \sample_in_buf[98]\, \sample_in_buf_941[104]\, - \sample_in_buf[86]\, \sample_in_buf_301[94]\, - \sample_in_buf[76]\, \sample_in_buf_45[90]\, - \sample_in_buf[72]\, \sample_in_buf_869[85]\, - \sample_in_buf[67]\, \sample_in_buf_989[69]\, - \sample_in_buf[51]\, \sample_in_buf_861[67]\, - \sample_in_buf[49]\, \sample_in_buf_533[44]\, - \sample_in_buf[26]\, \sample_in_buf_589[27]\, - \sample_in_buf[9]\, \sample_in_buf_893[139]\, - \sample_in_buf[121]\, \sample_in_buf_877[103]\, - \sample_in_buf[85]\, \sample_in_buf_37[72]\, - \sample_in_buf[54]\, \sample_in_buf_469[43]\, - \sample_in_buf[25]\, \sample_in_buf_653[28]\, - \sample_in_buf[10]\, \sample_in_buf_949[122]\, - \sample_in_buf[104]\, \sample_in_buf_365[95]\, - \sample_in_buf[77]\, \sample_in_buf_997[87]\, - \sample_in_buf[69]\, \sample_in_buf_613[81]\, - \sample_in_buf[63]\, \sample_in_buf_549[80]\, - \sample_in_buf[62]\, \sample_in_buf_917[50]\, - \sample_in_buf[32]\, \sample_in_buf_789[48]\, - \sample_in_buf[30]\, \sample_in_buf_781[30]\, - \sample_in_buf[12]\, \sample_in_buf_245[111]\, - \sample_in_buf[93]\, \sample_in_buf_237[93]\, - \sample_in_buf[75]\, \sample_in_buf_1125[89]\, - \sample_in_buf[71]\, \sample_in_buf_933[86]\, - \sample_in_buf[68]\, \sample_in_buf_741[83]\, - \sample_in_buf[65]\, \sample_in_buf_981[51]\, - \sample_in_buf[33]\, \sample_in_buf_909[32]\, - \sample_in_buf[14]\, \sample_in_buf_845[31]\, - \sample_in_buf[13]\, \sample_in_buf_829[138]\, - \sample_in_buf[120]\, \sample_in_buf_1069[106]\, - \sample_in_buf[88]\, \sample_in_buf_477[61]\, - \sample_in_buf[43]\, \sample_in_buf_213[39]\, - \sample_in_buf[21]\, \sample_in_buf_1101[35]\, - \sample_in_buf[17]\, \sample_in_buf_773[12]\, - \sample_in_buf[138]\, \sample_in_buf_1133[107]\, - \sample_in_buf[89]\, \sample_in_buf_749[101]\, - \sample_in_buf[83]\, \sample_in_buf_221[57]\, - \sample_in_buf[39]\, \sample_in_buf_21[36]\, - \sample_in_buf[18]\, \sample_in_buf_1149[143]\, - \sample_in_buf[125]\, \sample_in_buf_373[113]\, - \sample_in_buf[95]\, \sample_in_buf_421[78]\, - \sample_in_buf[60]\, \sample_in_buf_725[47]\, - \sample_in_buf[29]\, \sample_in_buf_277[40]\, - \sample_in_buf[22]\, \sample_in_buf_1093[17]\, - \sample_in_buf[143]\, \sample_in_buf_757[119]\, - \sample_in_buf[101]\, \sample_in_buf_1117[71]\, - \sample_in_buf[53]\, \sample_in_buf_605[63]\, - \sample_in_buf[45]\, \sample_in_buf_341[41]\, - \sample_in_buf[23]\, \sample_in_buf_493[97]\, - \sample_in_buf[79]\, \sample_in_buf_805[84]\, - \sample_in_buf[66]\, \sample_in_buf_1045[52]\, - \sample_in_buf[34]\, \sample_in_buf_853[49]\, - \sample_in_buf[31]\, \sample_in_buf_437[114]\, - \sample_in_buf[96]\, \sample_in_buf_813[102]\, - \sample_in_buf[84]\, \sample_in_buf_285[58]\, - \sample_in_buf[40]\, \sample_in_buf_29[54]\, - \sample_in_buf[36]\, \sample_in_buf_965[15]\, - \sample_in_buf[141]\, \sample_in_buf_821[120]\, - \sample_in_buf[102]\, \sample_in_buf_501[115]\, - \sample_in_buf[97]\, \sample_in_buf_293[76]\, - \sample_in_buf[58]\, \sample_in_buf_669[64]\, - \sample_in_buf[46]\, \sample_in_buf_349[59]\, - \sample_in_buf[41]\, \sample_out_val_s2\, - sample_out_val_s, sample_out_rot_s_0, sample_out_rot_s_1, - \sample_filter_v2_out[125]\, \sample_filter_v2_out[124]\, - \sample_filter_v2_out[123]\, \sample_filter_v2_out[122]\, - \sample_filter_v2_out[121]\, \sample_filter_v2_out[120]\, - \sample_filter_v2_out[119]\, sample_out_rot_s_2, - \sample_filter_v2_out[118]\, \sample_filter_v2_out[117]\, - \sample_filter_v2_out[116]\, \sample_filter_v2_out[115]\, - \sample_filter_v2_out[114]\, \sample_filter_v2_out[113]\, - \sample_filter_v2_out[112]\, \sample_filter_v2_out[111]\, - \sample_filter_v2_out[110]\, \sample_filter_v2_out[107]\, - \sample_filter_v2_out[89]\, \sample_filter_v2_out[106]\, - \sample_filter_v2_out[88]\, \sample_filter_v2_out[105]\, - \sample_filter_v2_out[87]\, \sample_filter_v2_out[104]\, - \sample_filter_v2_out[86]\, \sample_filter_v2_out[103]\, - \sample_filter_v2_out[85]\, \sample_filter_v2_out[102]\, - \sample_filter_v2_out[84]\, \sample_filter_v2_out[101]\, - \sample_filter_v2_out[83]\, \sample_filter_v2_out[100]\, - \sample_filter_v2_out[82]\, \sample_filter_v2_out[99]\, - \sample_filter_v2_out[81]\, \sample_filter_v2_out[98]\, - \sample_filter_v2_out[80]\, \sample_filter_v2_out[97]\, - \sample_filter_v2_out[79]\, \sample_filter_v2_out[96]\, - \sample_filter_v2_out[78]\, \sample_filter_v2_out[95]\, - \sample_filter_v2_out[77]\, \sample_filter_v2_out[94]\, - \sample_filter_v2_out[76]\, \sample_filter_v2_out[93]\, - \sample_filter_v2_out[75]\, \sample_filter_v2_out[92]\, - \sample_filter_v2_out[74]\, sample_out_rot_s_3, - \sample_filter_v2_out[71]\, \sample_filter_v2_out[70]\, - \sample_filter_v2_out[69]\, sample_out_rot_s_4, - \sample_filter_v2_out[68]\, \sample_filter_v2_out[67]\, - \sample_filter_v2_out[66]\, \sample_filter_v2_out[65]\, - \sample_filter_v2_out[64]\, \sample_filter_v2_out[63]\, - \sample_filter_v2_out[62]\, \sample_filter_v2_out[61]\, - \sample_filter_v2_out[60]\, \sample_filter_v2_out[59]\, - \sample_filter_v2_out[58]\, \sample_filter_v2_out[57]\, - \sample_filter_v2_out[56]\, \sample_filter_v2_out[53]\, - \sample_filter_v2_out[52]\, \sample_filter_v2_out[51]\, - \sample_filter_v2_out[50]\, \sample_filter_v2_out[49]\, - \sample_filter_v2_out[48]\, \sample_filter_v2_out[47]\, - \sample_filter_v2_out[46]\, \sample_filter_v2_out[45]\, - sample_out_rot_s, \sample_filter_v2_out[44]\, - \sample_filter_v2_out[43]\, \sample_filter_v2_out[42]\, - \sample_filter_v2_out[41]\, \sample_filter_v2_out[40]\, - \sample_filter_v2_out[39]\, \sample_filter_v2_out[38]\, - un1_sample_in_rotate_0, un1_sample_in_rotate_2, - un1_sample_in_rotate_3, un1_sample_in_rotate_4, - un1_sample_in_rotate, un1_sample_in_rotate_1, - \sample_filter_v2_out[35]\, \sample_filter_v2_out[34]\, - \sample_filter_v2_out[33]\, \sample_filter_v2_out[32]\, - \sample_filter_v2_out[31]\, \sample_filter_v2_out[30]\, - \sample_filter_v2_out[29]\, \sample_filter_v2_out[28]\, - \sample_filter_v2_out[27]\, \sample_filter_v2_out[26]\, - \sample_filter_v2_out[25]\, \sample_filter_v2_out[24]\, - \sample_filter_v2_out[23]\, \sample_filter_v2_out[22]\, - \sample_filter_v2_out[21]\, \sample_filter_v2_out[20]\, - \sample_filter_v2_out[17]\, \sample_out_s[0]\, - \sample_filter_v2_out[16]\, \sample_out_s[1]\, - \sample_filter_v2_out[15]\, \sample_out_s[2]\, - \sample_filter_v2_out[14]\, \sample_out_s[3]\, - \sample_filter_v2_out[13]\, \sample_out_s[4]\, - \sample_filter_v2_out[12]\, \sample_out_s[5]\, - \sample_filter_v2_out[11]\, \sample_out_s[6]\, - \sample_filter_v2_out[10]\, \sample_out_s[7]\, - \sample_filter_v2_out[9]\, \sample_out_s[8]\, - \sample_filter_v2_out[8]\, \sample_out_s[9]\, - \sample_filter_v2_out[7]\, \sample_out_s[10]\, - \sample_filter_v2_out[6]\, \sample_out_s[11]\, - \sample_filter_v2_out[5]\, \sample_out_s[12]\, - \sample_filter_v2_out[4]\, \sample_out_s[13]\, - \sample_filter_v2_out[3]\, \sample_out_s[14]\, - \sample_filter_v2_out[2]\, \sample_out_s[15]\, - \alu_ctrl[0]\, \alu_ctrl[1]\, \alu_ctrl[2]\, - \alu_sel_coeff_0[2]\, \alu_sel_coeff_0[0]\, - \alu_sel_coeff[0]\, \alu_sel_coeff[1]\, - \alu_sel_coeff[2]\, \alu_sel_coeff[3]\, - \alu_sel_coeff[4]\, \S[8]\, \S[44]\, \waddr_previous[0]\, - \waddr_previous[1]\, \ram_sel_Wdata[0]\, - \ram_sel_Wdata[1]\, \in_sel_src[0]\, \in_sel_src[1]\, - raddr_rst, raddr_add1, ram_write, ram_write_i, - alu_sel_input, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : IIR_CEL_CTRLR_v2_DATAFLOW - Use entity work.IIR_CEL_CTRLR_v2_DATAFLOW(DEF_ARCH); - for all : IIR_CEL_CTRLR_v2_CONTROL - Use entity work.IIR_CEL_CTRLR_v2_CONTROL(DEF_ARCH); -begin - - sample_filter_v2_out_0 <= \sample_filter_v2_out[2]\; - sample_filter_v2_out_1 <= \sample_filter_v2_out[3]\; - sample_filter_v2_out_2 <= \sample_filter_v2_out[4]\; - sample_filter_v2_out_3 <= \sample_filter_v2_out[5]\; - sample_filter_v2_out_4 <= \sample_filter_v2_out[6]\; - sample_filter_v2_out_5 <= \sample_filter_v2_out[7]\; - sample_filter_v2_out_6 <= \sample_filter_v2_out[8]\; - sample_filter_v2_out_7 <= \sample_filter_v2_out[9]\; - sample_filter_v2_out_8 <= \sample_filter_v2_out[10]\; - sample_filter_v2_out_9 <= \sample_filter_v2_out[11]\; - sample_filter_v2_out_10 <= \sample_filter_v2_out[12]\; - sample_filter_v2_out_11 <= \sample_filter_v2_out[13]\; - sample_filter_v2_out_12 <= \sample_filter_v2_out[14]\; - sample_filter_v2_out_13 <= \sample_filter_v2_out[15]\; - sample_filter_v2_out_14 <= \sample_filter_v2_out[16]\; - sample_filter_v2_out_15 <= \sample_filter_v2_out[17]\; - sample_filter_v2_out_18 <= \sample_filter_v2_out[20]\; - sample_filter_v2_out_19 <= \sample_filter_v2_out[21]\; - sample_filter_v2_out_20 <= \sample_filter_v2_out[22]\; - sample_filter_v2_out_21 <= \sample_filter_v2_out[23]\; - sample_filter_v2_out_22 <= \sample_filter_v2_out[24]\; - sample_filter_v2_out_23 <= \sample_filter_v2_out[25]\; - sample_filter_v2_out_24 <= \sample_filter_v2_out[26]\; - sample_filter_v2_out_25 <= \sample_filter_v2_out[27]\; - sample_filter_v2_out_26 <= \sample_filter_v2_out[28]\; - sample_filter_v2_out_27 <= \sample_filter_v2_out[29]\; - sample_filter_v2_out_28 <= \sample_filter_v2_out[30]\; - sample_filter_v2_out_29 <= \sample_filter_v2_out[31]\; - sample_filter_v2_out_30 <= \sample_filter_v2_out[32]\; - sample_filter_v2_out_31 <= \sample_filter_v2_out[33]\; - sample_filter_v2_out_32 <= \sample_filter_v2_out[34]\; - sample_filter_v2_out_33 <= \sample_filter_v2_out[35]\; - sample_filter_v2_out_36 <= \sample_filter_v2_out[38]\; - sample_filter_v2_out_37 <= \sample_filter_v2_out[39]\; - sample_filter_v2_out_38 <= \sample_filter_v2_out[40]\; - sample_filter_v2_out_39 <= \sample_filter_v2_out[41]\; - sample_filter_v2_out_40 <= \sample_filter_v2_out[42]\; - sample_filter_v2_out_41 <= \sample_filter_v2_out[43]\; - sample_filter_v2_out_42 <= \sample_filter_v2_out[44]\; - sample_filter_v2_out_43 <= \sample_filter_v2_out[45]\; - sample_filter_v2_out_44 <= \sample_filter_v2_out[46]\; - sample_filter_v2_out_45 <= \sample_filter_v2_out[47]\; - sample_filter_v2_out_46 <= \sample_filter_v2_out[48]\; - sample_filter_v2_out_47 <= \sample_filter_v2_out[49]\; - sample_filter_v2_out_48 <= \sample_filter_v2_out[50]\; - sample_filter_v2_out_49 <= \sample_filter_v2_out[51]\; - sample_filter_v2_out_50 <= \sample_filter_v2_out[52]\; - sample_filter_v2_out_51 <= \sample_filter_v2_out[53]\; - sample_filter_v2_out_54 <= \sample_filter_v2_out[56]\; - sample_filter_v2_out_55 <= \sample_filter_v2_out[57]\; - sample_filter_v2_out_56 <= \sample_filter_v2_out[58]\; - sample_filter_v2_out_57 <= \sample_filter_v2_out[59]\; - sample_filter_v2_out_58 <= \sample_filter_v2_out[60]\; - sample_filter_v2_out_59 <= \sample_filter_v2_out[61]\; - sample_filter_v2_out_60 <= \sample_filter_v2_out[62]\; - sample_filter_v2_out_61 <= \sample_filter_v2_out[63]\; - sample_filter_v2_out_62 <= \sample_filter_v2_out[64]\; - sample_filter_v2_out_63 <= \sample_filter_v2_out[65]\; - sample_filter_v2_out_64 <= \sample_filter_v2_out[66]\; - sample_filter_v2_out_65 <= \sample_filter_v2_out[67]\; - sample_filter_v2_out_66 <= \sample_filter_v2_out[68]\; - sample_filter_v2_out_67 <= \sample_filter_v2_out[69]\; - sample_filter_v2_out_68 <= \sample_filter_v2_out[70]\; - sample_filter_v2_out_69 <= \sample_filter_v2_out[71]\; - sample_filter_v2_out_90 <= \sample_filter_v2_out[92]\; - sample_filter_v2_out_91 <= \sample_filter_v2_out[93]\; - sample_filter_v2_out_92 <= \sample_filter_v2_out[94]\; - sample_filter_v2_out_93 <= \sample_filter_v2_out[95]\; - sample_filter_v2_out_94 <= \sample_filter_v2_out[96]\; - sample_filter_v2_out_95 <= \sample_filter_v2_out[97]\; - sample_filter_v2_out_96 <= \sample_filter_v2_out[98]\; - sample_filter_v2_out_97 <= \sample_filter_v2_out[99]\; - sample_filter_v2_out_98 <= \sample_filter_v2_out[100]\; - sample_filter_v2_out_99 <= \sample_filter_v2_out[101]\; - sample_filter_v2_out_100 <= \sample_filter_v2_out[102]\; - sample_filter_v2_out_101 <= \sample_filter_v2_out[103]\; - sample_filter_v2_out_102 <= \sample_filter_v2_out[104]\; - sample_filter_v2_out_103 <= \sample_filter_v2_out[105]\; - sample_filter_v2_out_104 <= \sample_filter_v2_out[106]\; - sample_filter_v2_out_105 <= \sample_filter_v2_out[107]\; - sample_filter_v2_out_108 <= \sample_filter_v2_out[110]\; - sample_filter_v2_out_109 <= \sample_filter_v2_out[111]\; - sample_filter_v2_out_110 <= \sample_filter_v2_out[112]\; - sample_filter_v2_out_111 <= \sample_filter_v2_out[113]\; - sample_filter_v2_out_112 <= \sample_filter_v2_out[114]\; - sample_filter_v2_out_113 <= \sample_filter_v2_out[115]\; - sample_filter_v2_out_114 <= \sample_filter_v2_out[116]\; - sample_filter_v2_out_115 <= \sample_filter_v2_out[117]\; - sample_filter_v2_out_116 <= \sample_filter_v2_out[118]\; - sample_filter_v2_out_117 <= \sample_filter_v2_out[119]\; - sample_filter_v2_out_118 <= \sample_filter_v2_out[120]\; - sample_filter_v2_out_119 <= \sample_filter_v2_out[121]\; - sample_filter_v2_out_120 <= \sample_filter_v2_out[122]\; - sample_filter_v2_out_121 <= \sample_filter_v2_out[123]\; - sample_filter_v2_out_122 <= \sample_filter_v2_out[124]\; - sample_filter_v2_out_123 <= \sample_filter_v2_out[125]\; - - \loop_all_sample.2.loop_all_chanel.6.sample_in_buf[33]\ : - DFN1E1C0 - port map(D => \sample_in_buf_973[33]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[33]\); - - \loop_all_sample.13.loop_all_chanel.7.sample_in_buf[4]\ : - DFN1E1C0 - port map(D => \sample_in_buf_261[4]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[4]\); - - \loop_all_sample.9.loop_all_chanel.4.sample_in_buf_RNO[62]\ : - MX2 - port map(A => \sample_in_buf[44]\, B => sample_4(9), S => - sample_val_delay_3, Y => \sample_in_buf_541[62]\); - - \loop_all_sample.10.loop_all_chanel.2.sample_in_buf_RNO[97]\ : - MX2 - port map(A => \sample_in_buf[79]\, B => sample_2(10), S => - sample_val_delay, Y => \sample_in_buf_493[97]\); - - \chanel_more.all_chanel.2.all_bit.3.sample_out_s2[122]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[104]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[122]\); - - \loop_all_sample.5.loop_all_chanel.4.sample_in_buf_RNO[66]\ : - MX2 - port map(A => \sample_in_buf[48]\, B => sample_4(5), S => - sample_val_delay_3, Y => \sample_in_buf_797[66]\); - - \loop_all_sample.1.loop_all_chanel.6.sample_in_buf[34]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1037[34]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[34]\); - - \chanel_more.all_chanel.3.all_bit.1.sample_out_s2[106]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[88]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[106]\); - - \loop_all_sample.6.loop_all_chanel.1.sample_in_buf_RNO[119]\ : - MX2 - port map(A => \sample_in_buf[101]\, B => sample_1(6), S => - sample_val_delay_5, Y => \sample_in_buf_757[119]\); - - \loop_all_sample.12.loop_all_chanel.4.sample_in_buf_RNO[59]\ : - MX2 - port map(A => \sample_in_buf[41]\, B => sample_4(12), S => - sample_val_delay, Y => \sample_in_buf_349[59]\); - - \chanel_more.all_chanel.1.all_bit.6.sample_out_s2[137]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[119]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_135); - - \chanel_more.all_chanel.7.all_bit.3.sample_out_s2[32]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[14]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[32]\); - - \chanel_more.all_chanel.5.all_bit.10.sample_out_s2[61]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[43]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[61]\); - - \loop_all_sample.6.loop_all_chanel.0.sample_in_buf_RNO[137]\ : - MX2 - port map(A => \sample_in_buf[119]\, B => sample_0(6), S => - sample_val_delay_3, Y => \sample_in_buf_765[137]\); - - \chanel_more.all_chanel.6.all_bit.0.sample_out_s2[53]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[35]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[53]\); - - \chanel_more.all_chanel.4.all_bit.13.sample_out_s2[76]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[58]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[76]\); - - \loop_all_sample.9.loop_all_chanel.0.sample_in_buf_RNO[134]\ : - MX2 - port map(A => \sample_in_buf[116]\, B => sample_0(9), S => - sample_val_delay_0, Y => \sample_in_buf_573[134]\); - - \loop_all_sample.8.loop_all_chanel.2.sample_in_buf[99]\ : - DFN1E1C0 - port map(D => \sample_in_buf_621[99]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[99]\); - - \chanel_more.all_chanel.3.all_bit.11.sample_out_s2[96]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[78]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[96]\); - - \chanel_more.all_chanel.6.all_bit.2.sample_out_s2[51]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[33]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[51]\); - - \loop_all_sample.12.loop_all_chanel.5.sample_in_buf_RNO[41]\ : - MX2 - port map(A => \sample_in_buf[23]\, B => sample_5(12), S => - sample_val_delay, Y => \sample_in_buf_341[41]\); - - \loop_all_sample.1.loop_all_chanel.2.sample_in_buf[106]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1069[106]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[106]\); - - \loop_all_sample.17.loop_all_chanel.7.sample_in_buf_RNO[0]\ : - MX2 - port map(A => \sample_in_buf[127]\, B => sample_7(15), S - => sample_val_delay_1, Y => \sample_in_buf_5[0]\); - - \loop_all_sample.13.loop_all_chanel.5.sample_in_buf[40]\ : - DFN1E1C0 - port map(D => \sample_in_buf_277[40]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[40]\); - - \loop_all_sample.13.loop_all_chanel.0.sample_in_buf_RNO[130]\ : - MX2 - port map(A => \sample_in_buf[112]\, B => sample_0(13), S - => sample_val_delay_0, Y => \sample_in_buf_317[130]\); - - \loop_all_sample.3.loop_all_chanel.4.sample_in_buf_RNO[68]\ : - MX2 - port map(A => \sample_in_buf[50]\, B => sample_4(3), S => - sample_val_delay_3, Y => \sample_in_buf_925[68]\); - - \chanel_more.all_chanel.1.all_bit.3.sample_out_s2[140]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[122]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_138); - - \loop_all_sample.13.loop_all_chanel.2.sample_in_buf_RNO[94]\ : - MX2 - port map(A => \sample_in_buf[76]\, B => sample_2(13), S => - sample_val_delay_4, Y => \sample_in_buf_301[94]\); - - \loop_all_sample.11.loop_all_chanel.3.sample_in_buf_RNO[78]\ : - MX2 - port map(A => \sample_in_buf[60]\, B => sample_3(11), S => - sample_val_delay_5, Y => \sample_in_buf_421[78]\); - - \chanel_more.all_chanel.4.all_bit.1.sample_out_s2[88]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[70]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[88]\); - - \chanel_more.all_chanel.3.all_bit.4.sample_out_s2[103]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[85]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[103]\); - - \loop_all_sample.7.loop_all_chanel.4.sample_in_buf_RNO[64]\ : - MX2 - port map(A => \sample_in_buf[46]\, B => sample_4(7), S => - sample_val_delay, Y => \sample_in_buf_669[64]\); - - \loop_all_sample.5.loop_all_chanel.3.sample_in_buf[84]\ : - DFN1E1C0 - port map(D => \sample_in_buf_805[84]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[84]\); - - \chanel_more.all_chanel.6.all_bit.15.sample_out_s2[38]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[20]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[38]\); - - \loop_all_sample.12.loop_all_chanel.5.sample_in_buf[41]\ : - DFN1E1C0 - port map(D => \sample_in_buf_341[41]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[41]\); - - \chanel_more.all_chanel.5.all_bit.7.sample_out_s2[64]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[46]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[64]\); - - \chanel_more.all_chanel.5.all_bit.6.sample_out_s2[65]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[47]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[65]\); - - \chanel_more.all_chanel.7.all_bit.2.sample_out_s2[33]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[15]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[33]\); - - \loop_all_sample.9.loop_all_chanel.3.sample_in_buf_RNO[80]\ : - MX2 - port map(A => \sample_in_buf[62]\, B => sample_3(9), S => - sample_val_delay_4, Y => \sample_in_buf_549[80]\); - - \loop_all_sample.2.loop_all_chanel.4.sample_in_buf_RNO[69]\ : - MX2 - port map(A => \sample_in_buf[51]\, B => sample_4(2), S => - sample_val_delay_4, Y => \sample_in_buf_989[69]\); - - \loop_all_sample.14.loop_all_chanel.6.sample_in_buf[21]\ : - DFN1E1C0 - port map(D => \sample_in_buf_205[21]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[21]\); - - \loop_all_sample.9.loop_all_chanel.5.sample_in_buf[44]\ : - DFN1E1C0 - port map(D => \sample_in_buf_533[44]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[44]\); - - \loop_all_sample.11.loop_all_chanel.5.sample_in_buf[42]\ : - DFN1E1C0 - port map(D => \sample_in_buf_405[42]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[42]\); - - \loop_all_sample.9.loop_all_chanel.2.sample_in_buf_RNO[98]\ : - MX2 - port map(A => \sample_in_buf[80]\, B => sample_2(9), S => - sample_val_delay_2, Y => \sample_in_buf_557[98]\); - - \loop_all_sample.10.loop_all_chanel.4.sample_in_buf_RNO[61]\ : - MX2 - port map(A => \sample_in_buf[43]\, B => sample_4(10), S => - sample_val_delay_5, Y => \sample_in_buf_477[61]\); - - \chanel_more.all_chanel.1.all_bit.8.sample_out_s2[135]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[117]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_133); - - \loop_all_sample.9.loop_all_chanel.6.sample_in_buf[26]\ : - DFN1E1C0 - port map(D => \sample_in_buf_525[26]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[26]\); - - \chanel_more.all_chanel.1.all_bit.9.sample_out_s2[134]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[116]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_132); - - \loop_all_sample.11.loop_all_chanel.7.sample_in_buf_RNO[6]\ : - MX2 - port map(A => \sample_in_buf[132]\, B => sample_7(11), S - => sample_val_delay_0, Y => \sample_in_buf_389[6]\); - - \loop_all_sample.1.loop_all_chanel.6.sample_in_buf_RNO[34]\ : - MX2 - port map(A => \sample_in_buf[16]\, B => sample_6(1), S => - sample_val_delay_3, Y => \sample_in_buf_1037[34]\); - - \loop_all_sample.3.loop_all_chanel.3.sample_in_buf[86]\ : - DFN1E1C0 - port map(D => \sample_in_buf_933[86]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[86]\); - - \chanel_more.all_chanel.6.all_bit.1.sample_out_s2[52]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[34]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[52]\); - - \chanel_HIGH.6.sample_out_s2[11]\ : DFN1E1C0 - port map(D => \sample_out_s[6]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[11]\); - - \loop_all_sample.11.loop_all_chanel.2.sample_in_buf_RNO[96]\ : - MX2 - port map(A => \sample_in_buf[78]\, B => sample_2(11), S => - sample_val_delay_3, Y => \sample_in_buf_429[96]\); - - \chanel_more.all_chanel.1.all_bit.5.sample_out_s2[138]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[120]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_136); - - \loop_all_sample.2.loop_all_chanel.7.sample_in_buf_RNO[15]\ : - MX2 - port map(A => \sample_in_buf[141]\, B => sample_7(2), S => - sample_val_delay, Y => \sample_in_buf_965[15]\); - - \loop_all_sample.13.loop_all_chanel.2.sample_in_buf[94]\ : - DFN1E1C0 - port map(D => \sample_in_buf_301[94]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[94]\); - - \loop_all_sample.17.loop_all_chanel.1.sample_in_buf[108]\ : - DFN1E1C0 - port map(D => \sample_in_buf_53[108]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[109]\); - - \loop_all_sample.0.loop_all_chanel.6.sample_in_buf_RNO[35]\ : - MX2 - port map(A => \sample_in_buf[17]\, B => sample_6(0), S => - sample_val_delay_5, Y => \sample_in_buf_1101[35]\); - - \loop_all_sample.4.loop_all_chanel.0.sample_in_buf_RNO[139]\ : - MX2 - port map(A => \sample_in_buf[121]\, B => sample_0(4), S => - sample_val_delay_4, Y => \sample_in_buf_893[139]\); - - \loop_all_sample.0.loop_all_chanel.3.sample_in_buf[89]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1125[89]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[89]\); - - \chanel_more.all_chanel.5.all_bit.9.sample_out_s2[62]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[44]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[62]\); - - \loop_all_sample.11.loop_all_chanel.2.sample_in_buf[96]\ : - DFN1E1C0 - port map(D => \sample_in_buf_429[96]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[96]\); - - \loop_all_sample.1.loop_all_chanel.3.sample_in_buf[88]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1061[88]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[88]\); - - \chanel_more.all_chanel.4.all_bit.11.sample_out_s2[78]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[60]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[78]\); - - \chanel_HIGH.15.sample_out_s2[2]\ : DFN1E1C0 - port map(D => \sample_out_s[15]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[2]\); - - \loop_all_sample.0.loop_all_chanel.5.sample_in_buf_RNO[53]\ : - MX2 - port map(A => \sample_in_buf[35]\, B => sample_5(0), S => - sample_val_delay_2, Y => \sample_in_buf_1109[53]\); - - \loop_all_sample.6.loop_all_chanel.4.sample_in_buf[65]\ : - DFN1E1C0 - port map(D => \sample_in_buf_733[65]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[65]\); - - \loop_all_sample.7.loop_all_chanel.7.sample_in_buf_RNO[10]\ : - MX2 - port map(A => \sample_in_buf[136]\, B => sample_7(7), S => - sample_val_delay_0, Y => \sample_in_buf_645[10]\); - - \loop_all_sample.17.loop_all_chanel.4.sample_in_buf[54]\ : - DFN1E1C0 - port map(D => \sample_in_buf_29[54]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[54]\); - - \loop_all_sample.4.loop_all_chanel.1.sample_in_buf_RNO[121]\ : - MX2 - port map(A => \sample_in_buf[103]\, B => sample_1(4), S => - sample_val_delay_2, Y => \sample_in_buf_885[121]\); - - \loop_all_sample.13.loop_all_chanel.6.sample_in_buf[22]\ : - DFN1E1C0 - port map(D => \sample_in_buf_269[22]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[22]\); - - \loop_all_sample.17.loop_all_chanel.2.sample_in_buf_RNO[90]\ : - MX2 - port map(A => \sample_in_buf[72]\, B => sample_2(15), S => - sample_val_delay_4, Y => \sample_in_buf_45[90]\); - - \loop_all_sample.11.loop_all_chanel.6.sample_in_buf_RNO[24]\ : - MX2 - port map(A => \sample_in_buf[6]\, B => sample_6(11), S => - sample_val_delay_3, Y => \sample_in_buf_397[24]\); - - \loop_all_sample.1.loop_all_chanel.7.sample_in_buf_RNO[16]\ : - MX2 - port map(A => \sample_in_buf[142]\, B => sample_7(1), S => - sample_val_delay_1, Y => \sample_in_buf_1029[16]\); - - \loop_all_sample.6.loop_all_chanel.7.sample_in_buf[11]\ : - DFN1E1C0 - port map(D => \sample_in_buf_709[11]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[11]\); - - \chanel_more.all_chanel.6.all_bit.8.sample_out_s2[45]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[27]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[45]\); - - \loop_all_sample.7.loop_all_chanel.0.sample_in_buf_RNO[136]\ : - MX2 - port map(A => \sample_in_buf[118]\, B => sample_0(7), S => - sample_val_delay_0, Y => \sample_in_buf_701[136]\); - - \chanel_more.all_chanel.3.all_bit.10.sample_out_s2[97]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[79]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[97]\); - - \loop_all_sample.4.loop_all_chanel.5.sample_in_buf_RNO[49]\ : - MX2 - port map(A => \sample_in_buf[31]\, B => sample_5(4), S => - sample_val_delay, Y => \sample_in_buf_853[49]\); - - \chanel_more.all_chanel.1.all_bit.13.sample_out_s2[130]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[112]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_128); - - \loop_all_sample.13.loop_all_chanel.5.sample_in_buf_RNO[40]\ : - MX2 - port map(A => \sample_in_buf[22]\, B => sample_5(13), S => - sample_val_delay_5, Y => \sample_in_buf_277[40]\); - - \loop_all_sample.17.loop_all_chanel.3.sample_in_buf[72]\ : - DFN1E1C0 - port map(D => \sample_in_buf_37[72]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[72]\); - - \chanel_more.all_chanel.6.all_bit.12.sample_out_s2[41]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[23]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[41]\); - - \chanel_more.all_chanel.4.all_bit.4.sample_out_s2[85]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[67]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[85]\); - - \loop_all_sample.5.loop_all_chanel.1.sample_in_buf[120]\ : - DFN1E1C0 - port map(D => \sample_in_buf_821[120]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[120]\); - - \loop_all_sample.11.loop_all_chanel.4.sample_in_buf_RNO[60]\ : - MX2 - port map(A => \sample_in_buf[42]\, B => sample_4(11), S => - sample_val_delay_2, Y => \sample_in_buf_413[60]\); - - \loop_all_sample.0.loop_all_chanel.1.sample_in_buf_RNO[125]\ : - MX2 - port map(A => \sample_in_buf[107]\, B => sample_1(0), S => - sample_val_delay_3, Y => \sample_in_buf_1141[125]\); - - \loop_all_sample.7.loop_all_chanel.2.sample_in_buf[100]\ : - DFN1E1C0 - port map(D => \sample_in_buf_685[100]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[100]\); - - \loop_all_sample.9.loop_all_chanel.7.sample_in_buf[8]\ : - DFN1E1C0 - port map(D => \sample_in_buf_517[8]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[8]\); - - \chanel_more.all_chanel.2.all_bit.7.sample_out_s2[118]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[100]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[118]\); - - \chanel_HIGH.9.sample_out_s2[8]\ : DFN1E1C0 - port map(D => \sample_out_s[9]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[8]\); - - \loop_all_sample.6.loop_all_chanel.5.sample_in_buf[47]\ : - DFN1E1C0 - port map(D => \sample_in_buf_725[47]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[47]\); - - \loop_all_sample.13.loop_all_chanel.4.sample_in_buf[58]\ : - DFN1E1C0 - port map(D => \sample_in_buf_285[58]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[58]\); - - \chanel_more.all_chanel.4.all_bit.5.sample_out_s2[84]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[66]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[84]\); - - \loop_all_sample.4.loop_all_chanel.2.sample_in_buf[103]\ : - DFN1E1C0 - port map(D => \sample_in_buf_877[103]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[103]\); - - \loop_all_sample.1.loop_all_chanel.7.sample_in_buf[16]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1029[16]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[16]\); - - \chanel_HIGH.7.sample_out_s2[10]\ : DFN1E1C0 - port map(D => \sample_out_s[7]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[10]\); - - \loop_all_sample.13.loop_all_chanel.7.sample_in_buf_RNO[4]\ : - MX2 - port map(A => \sample_in_buf[130]\, B => sample_7(13), S - => sample_val_delay_0, Y => \sample_in_buf_261[4]\); - - \loop_all_sample.11.loop_all_chanel.7.sample_in_buf[6]\ : - DFN1E1C0 - port map(D => \sample_in_buf_389[6]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[6]\); - - GND_i : GND - port map(Y => \GND\); - - \loop_all_sample.1.loop_all_chanel.3.sample_in_buf_RNO[88]\ : - MX2 - port map(A => \sample_in_buf[70]\, B => sample_3(1), S => - sample_val_delay_2, Y => \sample_in_buf_1061[88]\); - - \loop_all_sample.13.loop_all_chanel.4.sample_in_buf_RNO[58]\ : - MX2 - port map(A => \sample_in_buf[40]\, B => sample_4(13), S => - sample_val_delay, Y => \sample_in_buf_285[58]\); - - \chanel_more.all_chanel.1.all_bit.4.sample_out_s2[139]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[121]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_137); - - \chanel_more.all_chanel.7.all_bit.6.sample_out_s2[29]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[11]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[29]\); - - \loop_all_sample.2.loop_all_chanel.2.sample_in_buf_RNO[105]\ : - MX2 - port map(A => \sample_in_buf[87]\, B => sample_2(2), S => - sample_val_delay_2, Y => \sample_in_buf_1005[105]\); - - \loop_all_sample.10.loop_all_chanel.2.sample_in_buf[97]\ : - DFN1E1C0 - port map(D => \sample_in_buf_493[97]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[97]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \loop_all_sample.2.loop_all_chanel.5.sample_in_buf_RNO[51]\ : - MX2 - port map(A => \sample_in_buf[33]\, B => sample_5(2), S => - sample_val_delay_5, Y => \sample_in_buf_981[51]\); - - \loop_all_sample.17.loop_all_chanel.5.sample_in_buf[36]\ : - DFN1E1C0 - port map(D => \sample_in_buf_21[36]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[36]\); - - \loop_all_sample.17.loop_all_chanel.3.sample_in_buf_RNO[72]\ : - MX2 - port map(A => \sample_in_buf[54]\, B => sample_3(15), S => - sample_val_delay_4, Y => \sample_in_buf_37[72]\); - - \chanel_more.all_chanel.2.all_bit.9.sample_out_s2[116]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[98]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[116]\); - - \loop_all_sample.7.loop_all_chanel.1.sample_in_buf_RNO[118]\ : - MX2 - port map(A => \sample_in_buf[100]\, B => sample_1(7), S => - sample_val_delay_2, Y => \sample_in_buf_693[118]\); - - \chanel_more.all_chanel.2.all_bit.10.sample_out_s2[115]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[97]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[115]\); - - \chanel_more.all_chanel.3.all_bit.6.sample_out_s2[101]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[83]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[101]\); - - \loop_all_sample.9.loop_all_chanel.4.sample_in_buf[62]\ : - DFN1E1C0 - port map(D => \sample_in_buf_541[62]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[62]\); - - \loop_all_sample.14.loop_all_chanel.0.sample_in_buf[129]\ : - DFN1E1C0 - port map(D => \sample_in_buf_253[129]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[129]\); - - \loop_all_sample.7.loop_all_chanel.0.sample_in_buf[136]\ : - DFN1E1C0 - port map(D => \sample_in_buf_701[136]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[136]\); - - \chanel_more.all_chanel.4.all_bit.0.sample_out_s2[89]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[71]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[89]\); - - \loop_all_sample.3.loop_all_chanel.2.sample_in_buf[104]\ : - DFN1E1C0 - port map(D => \sample_in_buf_941[104]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[104]\); - - \loop_all_sample.5.loop_all_chanel.2.sample_in_buf_RNO[102]\ : - MX2 - port map(A => \sample_in_buf[84]\, B => sample_2(5), S => - sample_val_delay, Y => \sample_in_buf_813[102]\); - - \loop_all_sample.4.loop_all_chanel.1.sample_in_buf[121]\ : - DFN1E1C0 - port map(D => \sample_in_buf_885[121]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[121]\); - - \chanel_more.all_chanel.6.all_bit.11.sample_out_s2[42]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[24]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[42]\); - - \loop_all_sample.10.loop_all_chanel.5.sample_in_buf[43]\ : - DFN1E1C0 - port map(D => \sample_in_buf_469[43]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[43]\); - - \chanel_more.all_chanel.5.all_bit.0.sample_out_s2[71]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[53]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[71]\); - - \loop_all_sample.11.loop_all_chanel.0.sample_in_buf_RNO[132]\ : - MX2 - port map(A => \sample_in_buf[114]\, B => sample_0(11), S - => sample_val_delay_0, Y => \sample_in_buf_445[132]\); - - \chanel_more.all_chanel.6.all_bit.6.sample_out_s2[47]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[29]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[47]\); - - \loop_all_sample.12.loop_all_chanel.2.sample_in_buf[95]\ : - DFN1E1C0 - port map(D => \sample_in_buf_365[95]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[95]\); - - \chanel_more.all_chanel.7.all_bit.1.sample_out_s2[34]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[16]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[34]\); - - \loop_all_sample.6.loop_all_chanel.2.sample_in_buf[101]\ : - DFN1E1C0 - port map(D => \sample_in_buf_749[101]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[101]\); - - \loop_all_sample.9.loop_all_chanel.1.sample_in_buf_RNO[116]\ : - MX2 - port map(A => \sample_in_buf[98]\, B => sample_1(9), S => - sample_val_delay_3, Y => \sample_in_buf_565[116]\); - - \loop_all_sample.4.loop_all_chanel.2.sample_in_buf_RNO[103]\ : - MX2 - port map(A => \sample_in_buf[85]\, B => sample_2(4), S => - sample_val_delay_4, Y => \sample_in_buf_877[103]\); - - \loop_all_sample.10.loop_all_chanel.1.sample_in_buf_RNO[115]\ : - MX2 - port map(A => \sample_in_buf[97]\, B => sample_1(10), S => - sample_val_delay, Y => \sample_in_buf_501[115]\); - - \loop_all_sample.5.loop_all_chanel.5.sample_in_buf_RNO[48]\ : - MX2 - port map(A => \sample_in_buf[30]\, B => sample_5(5), S => - sample_val_delay_4, Y => \sample_in_buf_789[48]\); - - \loop_all_sample.3.loop_all_chanel.2.sample_in_buf_RNO[104]\ : - MX2 - port map(A => \sample_in_buf[86]\, B => sample_2(3), S => - sample_val_delay_3, Y => \sample_in_buf_941[104]\); - - \chanel_more.all_chanel.7.all_bit.15.sample_out_s2[20]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[2]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[20]\); - - \loop_all_sample.2.loop_all_chanel.1.sample_in_buf[123]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1013[123]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[123]\); - - \chanel_HIGH.13.sample_out_s2[4]\ : DFN1E1C0 - port map(D => \sample_out_s[13]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[4]\); - - \loop_all_sample.10.loop_all_chanel.6.sample_in_buf[25]\ : - DFN1E1C0 - port map(D => \sample_in_buf_461[25]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[25]\); - - \chanel_more.all_chanel.3.all_bit.13.sample_out_s2[94]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[76]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[94]\); - - \loop_all_sample.3.loop_all_chanel.1.sample_in_buf_RNO[122]\ : - MX2 - port map(A => \sample_in_buf[104]\, B => sample_1(3), S => - sample_val_delay_4, Y => \sample_in_buf_949[122]\); - - \loop_all_sample.2.loop_all_chanel.1.sample_in_buf_RNO[123]\ : - MX2 - port map(A => \sample_in_buf[105]\, B => sample_1(2), S => - sample_val_delay_2, Y => \sample_in_buf_1013[123]\); - - \loop_all_sample.3.loop_all_chanel.0.sample_in_buf_RNO[140]\ : - MX2 - port map(A => \sample_in_buf[122]\, B => sample_0(3), S => - sample_val_delay_3, Y => \sample_in_buf_957[140]\); - - \loop_all_sample.7.loop_all_chanel.6.sample_in_buf_RNO[28]\ : - MX2 - port map(A => \sample_in_buf[10]\, B => sample_6(7), S => - sample_val_delay_4, Y => \sample_in_buf_653[28]\); - - \loop_all_sample.8.loop_all_chanel.3.sample_in_buf_RNO[81]\ : - MX2 - port map(A => \sample_in_buf[63]\, B => sample_3(8), S => - sample_val_delay_4, Y => \sample_in_buf_613[81]\); - - \loop_all_sample.14.loop_all_chanel.5.sample_in_buf_RNO[39]\ : - MX2 - port map(A => \sample_in_buf[21]\, B => sample_5(14), S => - sample_val_delay_5, Y => \sample_in_buf_213[39]\); - - \loop_all_sample.12.loop_all_chanel.7.sample_in_buf_RNO[5]\ : - MX2 - port map(A => \sample_in_buf[131]\, B => sample_7(12), S - => sample_val_delay_0, Y => \sample_in_buf_325[5]\); - - \loop_all_sample.0.loop_all_chanel.2.sample_in_buf_RNO[107]\ : - MX2 - port map(A => \sample_in_buf[89]\, B => sample_2(0), S => - sample_val_delay_5, Y => \sample_in_buf_1133[107]\); - - \chanel_more.all_chanel.1.all_bit.15.sample_out_s2[128]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[110]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_126); - - \loop_all_sample.8.loop_all_chanel.1.sample_in_buf[117]\ : - DFN1E1C0 - port map(D => \sample_in_buf_629[117]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[117]\); - - \loop_all_sample.11.loop_all_chanel.1.sample_in_buf_RNO[114]\ : - MX2 - port map(A => \sample_in_buf[96]\, B => sample_1(11), S => - sample_val_delay, Y => \sample_in_buf_437[114]\); - - \loop_all_sample.5.loop_all_chanel.3.sample_in_buf_RNO[84]\ : - MX2 - port map(A => \sample_in_buf[66]\, B => sample_3(5), S => - sample_val_delay, Y => \sample_in_buf_805[84]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \chanel_more.all_chanel.6.all_bit.3.sample_out_s2[50]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[32]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[50]\); - - \loop_all_sample.2.loop_all_chanel.5.sample_in_buf[51]\ : - DFN1E1C0 - port map(D => \sample_in_buf_981[51]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[51]\); - - \chanel_more.all_chanel.7.all_bit.7.sample_out_s2[28]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[10]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[28]\); - - \chanel_more.all_chanel.2.all_bit.15.sample_out_s2[110]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[92]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[110]\); - - \loop_all_sample.8.loop_all_chanel.5.sample_in_buf[45]\ : - DFN1E1C0 - port map(D => \sample_in_buf_597[45]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[45]\); - - \loop_all_sample.9.loop_all_chanel.7.sample_in_buf_RNO[8]\ : - MX2 - port map(A => \sample_in_buf[134]\, B => sample_7(9), S => - sample_val_delay_0, Y => \sample_in_buf_517[8]\); - - \loop_all_sample.4.loop_all_chanel.6.sample_in_buf_RNO[31]\ : - MX2 - port map(A => \sample_in_buf[13]\, B => sample_6(4), S => - sample_val_delay_5, Y => \sample_in_buf_845[31]\); - - \loop_all_sample.8.loop_all_chanel.5.sample_in_buf_RNO[45]\ : - MX2 - port map(A => \sample_in_buf[27]\, B => sample_5(8), S => - sample_val_delay_3, Y => \sample_in_buf_597[45]\); - - \loop_all_sample.11.loop_all_chanel.1.sample_in_buf[114]\ : - DFN1E1C0 - port map(D => \sample_in_buf_437[114]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[114]\); - - \loop_all_sample.2.loop_all_chanel.0.sample_in_buf[141]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1021[141]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[141]\); - - \loop_all_sample.14.loop_all_chanel.4.sample_in_buf[57]\ : - DFN1E1C0 - port map(D => \sample_in_buf_221[57]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[57]\); - - IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW - port map(alu_ctrl(2) => \alu_ctrl[2]\, alu_ctrl(1) => - \alu_ctrl[1]\, alu_ctrl(0) => \alu_ctrl[0]\, - alu_sel_coeff_0_2 => \alu_sel_coeff_0[2]\, - alu_sel_coeff_0_0 => \alu_sel_coeff_0[0]\, - alu_sel_coeff(4) => \alu_sel_coeff[4]\, alu_sel_coeff(3) - => \alu_sel_coeff[3]\, alu_sel_coeff(2) => - \alu_sel_coeff[2]\, alu_sel_coeff(1) => - \alu_sel_coeff[1]\, alu_sel_coeff(0) => - \alu_sel_coeff[0]\, S_0 => \S[8]\, S_36 => \S[44]\, - waddr_previous(1) => \waddr_previous[1]\, - waddr_previous(0) => \waddr_previous[0]\, sample_0(14) - => sample_0(14), sample_0(13) => sample_0(13), - sample_0(12) => sample_0(12), sample_0(11) => - sample_0(11), sample_0(10) => sample_0(10), sample_0(9) - => sample_0(9), sample_0(8) => sample_0(8), sample_0(7) - => sample_0(7), sample_0(6) => sample_0(6), sample_0(5) - => sample_0(5), sample_0(4) => sample_0(4), sample_0(3) - => sample_0(3), sample_0(2) => sample_0(2), sample_0(1) - => sample_0(1), sample_0(0) => sample_0(0), - sample_in_buf(143) => \sample_in_buf[143]\, - sample_in_buf(142) => \sample_in_buf[142]\, - sample_in_buf(141) => \sample_in_buf[141]\, - sample_in_buf(140) => \sample_in_buf[140]\, - sample_in_buf(139) => \sample_in_buf[139]\, - sample_in_buf(138) => \sample_in_buf[138]\, - sample_in_buf(137) => \sample_in_buf[137]\, - sample_in_buf(136) => \sample_in_buf[136]\, - sample_in_buf(135) => \sample_in_buf[135]\, - sample_in_buf(134) => \sample_in_buf[134]\, - sample_in_buf(133) => \sample_in_buf[133]\, - sample_in_buf(132) => \sample_in_buf[132]\, - sample_in_buf(131) => \sample_in_buf[131]\, - sample_in_buf(130) => \sample_in_buf[130]\, - sample_in_buf(129) => \sample_in_buf[129]\, - ram_sel_Wdata(1) => \ram_sel_Wdata[1]\, ram_sel_Wdata(0) - => \ram_sel_Wdata[0]\, sample_out_s_1 => - \sample_out_s[1]\, sample_out_s_2 => \sample_out_s[2]\, - sample_out_s_0 => \sample_out_s[0]\, sample_out_s_3 => - \sample_out_s[3]\, sample_out_s_15 => \sample_out_s[15]\, - sample_out_s_14 => \sample_out_s[14]\, sample_out_s_13 - => \sample_out_s[13]\, sample_out_s_12 => - \sample_out_s[12]\, sample_out_s_11 => \sample_out_s[11]\, - sample_out_s_10 => \sample_out_s[10]\, sample_out_s_9 => - \sample_out_s[9]\, sample_out_s_8 => \sample_out_s[8]\, - sample_out_s_7 => \sample_out_s[7]\, sample_out_s_6 => - \sample_out_s[6]\, sample_out_s_5 => \sample_out_s[5]\, - sample_out_s_4 => \sample_out_s[4]\, sample_in_s_1(17) - => \sample_in_s_1[17]\, in_sel_src(1) => \in_sel_src[1]\, - in_sel_src(0) => \in_sel_src[0]\, raddr_rst => raddr_rst, - raddr_add1 => raddr_add1, ram_write => ram_write, - IIR_CEL_CTRLR_v2_DATAFLOW_GND => IIR_CEL_CTRLR_v2_GND, - IIR_CEL_CTRLR_v2_DATAFLOW_VCC => IIR_CEL_CTRLR_v2_VCC, - ram_write_i => ram_write_i, rstn => rstn, lclk_c => - lclk_c, sample_val_delay_5 => sample_val_delay_5, - sample_val_delay_1 => sample_val_delay_1, - sample_val_delay_0 => sample_val_delay_0, alu_sel_input - => alu_sel_input); - - sample_out_val : DFN1C0 - port map(D => \sample_out_val_s2\, CLK => lclk_c, CLR => - rstn, Q => sample_filter_v2_out_val); - - \loop_all_sample.8.loop_all_chanel.3.sample_in_buf[81]\ : - DFN1E1C0 - port map(D => \sample_in_buf_613[81]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[81]\); - - \loop_all_sample.17.loop_all_chanel.4.sample_in_buf_RNO[54]\ : - MX2 - port map(A => \sample_in_buf[36]\, B => sample_4(15), S => - sample_val_delay, Y => \sample_in_buf_29[54]\); - - \loop_all_sample.4.loop_all_chanel.3.sample_in_buf[85]\ : - DFN1E1C0 - port map(D => \sample_in_buf_869[85]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[85]\); - - \loop_all_sample.3.loop_all_chanel.4.sample_in_buf[68]\ : - DFN1E1C0 - port map(D => \sample_in_buf_925[68]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[68]\); - - \loop_all_sample.10.loop_all_chanel.7.sample_in_buf_RNO[7]\ : - MX2 - port map(A => \sample_in_buf[133]\, B => sample_7(10), S - => sample_val_delay_1, Y => \sample_in_buf_453[7]\); - - \loop_all_sample.10.loop_all_chanel.4.sample_in_buf[61]\ : - DFN1E1C0 - port map(D => \sample_in_buf_477[61]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[61]\); - - \loop_all_sample.10.loop_all_chanel.3.sample_in_buf[79]\ : - DFN1E1C0 - port map(D => \sample_in_buf_485[79]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[79]\); - - \chanel_more.all_chanel.4.all_bit.15.sample_out_s2[74]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[56]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[74]\); - - \chanel_more.all_chanel.2.all_bit.5.sample_out_s2[120]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[102]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[120]\); - - \chanel_more.all_chanel.2.all_bit.14.sample_out_s2[111]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[93]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[111]\); - - \chanel_more.all_chanel.2.all_bit.6.sample_out_s2[119]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[101]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[119]\); - - \loop_all_sample.11.loop_all_chanel.0.sample_in_buf[132]\ : - DFN1E1C0 - port map(D => \sample_in_buf_445[132]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[132]\); - - \chanel_more.all_chanel.7.all_bit.13.sample_out_s2[22]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[4]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[22]\); - - \loop_all_sample.6.loop_all_chanel.5.sample_in_buf_RNO[47]\ : - MX2 - port map(A => \sample_in_buf[29]\, B => sample_5(6), S => - sample_val_delay_5, Y => \sample_in_buf_725[47]\); - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf_RNO[126]\ : - MX2 - port map(A => \sample_in_buf[109]\, B => sample_0(15), S - => sample_val_delay_1, Y => \sample_in_buf_61[126]\); - - \loop_all_sample.6.loop_all_chanel.6.sample_in_buf[29]\ : - DFN1E1C0 - port map(D => \sample_in_buf_717[29]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[29]\); - - \loop_all_sample.1.loop_all_chanel.2.sample_in_buf_RNO[106]\ : - MX2 - port map(A => \sample_in_buf[88]\, B => sample_2(1), S => - sample_val_delay_5, Y => \sample_in_buf_1069[106]\); - - \loop_all_sample.0.loop_all_chanel.6.sample_in_buf[35]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1101[35]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[35]\); - - \chanel_more.all_chanel.3.all_bit.0.sample_out_s2[107]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[89]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[107]\); - - \loop_all_sample.4.loop_all_chanel.6.sample_in_buf[31]\ : - DFN1E1C0 - port map(D => \sample_in_buf_845[31]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[31]\); - - \chanel_more.all_chanel.4.all_bit.8.sample_out_s2[81]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[63]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[81]\); - - \chanel_more.all_chanel.6.all_bit.14.sample_out_s2[39]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[21]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[39]\); - - \loop_all_sample.12.loop_all_chanel.3.sample_in_buf_RNO[77]\ : - MX2 - port map(A => \sample_in_buf[59]\, B => sample_3(12), S => - sample_val_delay_2, Y => \sample_in_buf_357[77]\); - - \loop_all_sample.1.loop_all_chanel.5.sample_in_buf_RNO[52]\ : - MX2 - port map(A => \sample_in_buf[34]\, B => sample_5(1), S => - sample_val_delay, Y => \sample_in_buf_1045[52]\); - - \chanel_more.all_chanel.7.all_bit.14.sample_out_s2[21]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[3]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[21]\); - - \loop_all_sample.2.loop_all_chanel.2.sample_in_buf[105]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1005[105]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[105]\); - - \loop_all_sample.10.loop_all_chanel.6.sample_in_buf_RNO[25]\ : - MX2 - port map(A => \sample_in_buf[7]\, B => sample_6(10), S => - sample_val_delay_3, Y => \sample_in_buf_461[25]\); - - \chanel_more.all_chanel.3.all_bit.14.sample_out_s2[93]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[75]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[93]\); - - \loop_all_sample.2.loop_all_chanel.0.sample_in_buf_RNO[141]\ : - MX2 - port map(A => \sample_in_buf[123]\, B => sample_0(2), S => - sample_val_delay_2, Y => \sample_in_buf_1021[141]\); - - \loop_all_sample.3.loop_all_chanel.1.sample_in_buf[122]\ : - DFN1E1C0 - port map(D => \sample_in_buf_949[122]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[122]\); - - \chanel_more.all_chanel.4.all_bit.9.sample_out_s2[80]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[62]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[80]\); - - \chanel_more.all_chanel.4.all_bit.6.sample_out_s2[83]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[65]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[83]\); - - \loop_all_sample.13.loop_all_chanel.6.sample_in_buf_RNO[22]\ : - MX2 - port map(A => \sample_in_buf[4]\, B => sample_6(13), S => - sample_val_delay_3, Y => \sample_in_buf_269[22]\); - - \loop_all_sample.8.loop_all_chanel.6.sample_in_buf[27]\ : - DFN1E1C0 - port map(D => \sample_in_buf_589[27]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[27]\); - - \loop_all_sample.2.loop_all_chanel.3.sample_in_buf[87]\ : - DFN1E1C0 - port map(D => \sample_in_buf_997[87]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[87]\); - - \chanel_more.all_chanel.3.all_bit.15.sample_out_s2[92]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[74]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[92]\); - - \loop_all_sample.3.loop_all_chanel.3.sample_in_buf_RNO[86]\ : - MX2 - port map(A => \sample_in_buf[68]\, B => sample_3(3), S => - sample_val_delay_5, Y => \sample_in_buf_933[86]\); - - \chanel_more.all_chanel.6.all_bit.10.sample_out_s2[43]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[25]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[43]\); - - \loop_all_sample.6.loop_all_chanel.4.sample_in_buf_RNO[65]\ : - MX2 - port map(A => \sample_in_buf[47]\, B => sample_4(6), S => - sample_val_delay_3, Y => \sample_in_buf_733[65]\); - - \loop_all_sample.0.loop_all_chanel.0.sample_in_buf[143]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1149[143]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[143]\); - - \loop_all_sample.3.loop_all_chanel.0.sample_in_buf[140]\ : - DFN1E1C0 - port map(D => \sample_in_buf_957[140]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[140]\); - - \loop_all_sample.1.loop_all_chanel.4.sample_in_buf[70]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1053[70]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[70]\); - - \loop_all_sample.14.loop_all_chanel.2.sample_in_buf[93]\ : - DFN1E1C0 - port map(D => \sample_in_buf_237[93]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[93]\); - - \chanel_HIGH.14.sample_out_s2[3]\ : DFN1E1C0 - port map(D => \sample_out_s[14]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[3]\); - - \loop_all_sample.9.loop_all_chanel.1.sample_in_buf[116]\ : - DFN1E1C0 - port map(D => \sample_in_buf_565[116]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[116]\); - - \loop_all_sample.17.loop_all_chanel.2.sample_in_buf[90]\ : - DFN1E1C0 - port map(D => \sample_in_buf_45[90]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[90]\); - - \loop_all_sample.0.loop_all_chanel.2.sample_in_buf[107]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1133[107]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[107]\); - - \loop_all_sample.4.loop_all_chanel.4.sample_in_buf_RNO[67]\ : - MX2 - port map(A => \sample_in_buf[49]\, B => sample_4(4), S => - sample_val_delay_4, Y => \sample_in_buf_861[67]\); - - \loop_all_sample.8.loop_all_chanel.0.sample_in_buf[135]\ : - DFN1E1C0 - port map(D => \sample_in_buf_637[135]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[135]\); - - \chanel_more.all_chanel.5.all_bit.13.sample_out_s2[58]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[40]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[58]\); - - \chanel_HIGH.2.sample_out_s2[15]\ : DFN1E1C0 - port map(D => \sample_out_s[2]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[15]\); - - \chanel_more.all_chanel.4.all_bit.10.sample_out_s2[79]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[61]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[79]\); - - \loop_all_sample.12.loop_all_chanel.2.sample_in_buf_RNO[95]\ : - MX2 - port map(A => \sample_in_buf[77]\, B => sample_2(12), S => - sample_val_delay_4, Y => \sample_in_buf_365[95]\); - - \loop_all_sample.5.loop_all_chanel.5.sample_in_buf[48]\ : - DFN1E1C0 - port map(D => \sample_in_buf_789[48]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[48]\); - - \loop_all_sample.14.loop_all_chanel.7.sample_in_buf[3]\ : - DFN1E1C0 - port map(D => \sample_in_buf_197[3]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[3]\); - - \chanel_more.all_chanel.7.all_bit.10.sample_out_s2[25]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[7]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[25]\); - - \loop_all_sample.12.loop_all_chanel.3.sample_in_buf[77]\ : - DFN1E1C0 - port map(D => \sample_in_buf_357[77]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[77]\); - - \chanel_more.all_chanel.3.all_bit.3.sample_out_s2[104]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[86]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[104]\); - - sample_out_val_s2 : DFN1C0 - port map(D => sample_out_val_s, CLK => lclk_c, CLR => rstn, - Q => \sample_out_val_s2\); - - \chanel_more.all_chanel.7.all_bit.9.sample_out_s2[26]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[8]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[26]\); - - \loop_all_sample.5.loop_all_chanel.6.sample_in_buf_RNO[30]\ : - MX2 - port map(A => \sample_in_buf[12]\, B => sample_6(5), S => - sample_val_delay_4, Y => \sample_in_buf_781[30]\); - - \loop_all_sample.14.loop_all_chanel.5.sample_in_buf[39]\ : - DFN1E1C0 - port map(D => \sample_in_buf_213[39]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[39]\); - - \chanel_more.all_chanel.2.all_bit.0.sample_out_s2[125]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[107]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[125]\); - - \chanel_more.all_chanel.2.all_bit.2.sample_out_s2[123]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[105]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[123]\); - - \chanel_more.all_chanel.3.all_bit.7.sample_out_s2[100]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[82]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[100]\); - - \loop_all_sample.4.loop_all_chanel.7.sample_in_buf_RNO[13]\ : - MX2 - port map(A => \sample_in_buf[139]\, B => sample_7(4), S => - sample_val_delay_1, Y => \sample_in_buf_837[13]\); - - \loop_all_sample.14.loop_all_chanel.6.sample_in_buf_RNO[21]\ : - MX2 - port map(A => \sample_in_buf[3]\, B => sample_6(14), S => - sample_val_delay_2, Y => \sample_in_buf_205[21]\); - - \chanel_more.all_chanel.2.all_bit.13.sample_out_s2[112]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[94]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[112]\); - - \loop_all_sample.9.loop_all_chanel.6.sample_in_buf_RNO[26]\ : - MX2 - port map(A => \sample_in_buf[8]\, B => sample_6(9), S => - sample_val_delay_3, Y => \sample_in_buf_525[26]\); - - \loop_all_sample.9.loop_all_chanel.3.sample_in_buf[80]\ : - DFN1E1C0 - port map(D => \sample_in_buf_549[80]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[80]\); - - \loop_all_sample.7.loop_all_chanel.7.sample_in_buf[10]\ : - DFN1E1C0 - port map(D => \sample_in_buf_645[10]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[10]\); - - \loop_all_sample.12.loop_all_chanel.1.sample_in_buf_RNO[113]\ : - MX2 - port map(A => \sample_in_buf[95]\, B => sample_1(12), S => - sample_val_delay_5, Y => \sample_in_buf_373[113]\); - - \chanel_HIGH.1.sample_out_s2[16]\ : DFN1E1C0 - port map(D => \sample_out_s[1]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[16]\); - - \loop_all_sample.8.loop_all_chanel.4.sample_in_buf_RNO[63]\ : - MX2 - port map(A => \sample_in_buf[45]\, B => sample_4(8), S => - sample_val_delay, Y => \sample_in_buf_605[63]\); - - \loop_all_sample.6.loop_all_chanel.7.sample_in_buf_RNO[11]\ : - MX2 - port map(A => \sample_in_buf[137]\, B => sample_7(6), S => - sample_val_delay_1, Y => \sample_in_buf_709[11]\); - - \loop_all_sample.14.loop_all_chanel.0.sample_in_buf_RNO[129]\ : - MX2 - port map(A => \sample_in_buf[111]\, B => sample_0(14), S - => sample_val_delay_1, Y => \sample_in_buf_253[129]\); - - \chanel_HIGH.12.sample_out_s2[5]\ : DFN1E1C0 - port map(D => \sample_out_s[12]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[5]\); - - \loop_all_sample.3.loop_all_chanel.6.sample_in_buf[32]\ : - DFN1E1C0 - port map(D => \sample_in_buf_909[32]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[32]\); - - \loop_all_sample.17.loop_all_chanel.5.sample_in_buf_RNO[36]\ : - MX2 - port map(A => \sample_in_buf[18]\, B => sample_5(15), S => - sample_val_delay_5, Y => \sample_in_buf_21[36]\); - - \chanel_more.all_chanel.5.all_bit.8.sample_out_s2[63]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[45]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[63]\); - - \loop_all_sample.8.loop_all_chanel.7.sample_in_buf_RNO[9]\ : - MX2 - port map(A => \sample_in_buf[135]\, B => sample_7(8), S => - sample_val_delay_0, Y => \sample_in_buf_581[9]\); - - \loop_all_sample.5.loop_all_chanel.7.sample_in_buf_RNO[12]\ : - MX2 - port map(A => \sample_in_buf[138]\, B => sample_7(5), S => - sample_val_delay_5, Y => \sample_in_buf_773[12]\); - - \loop_all_sample.1.loop_all_chanel.4.sample_in_buf_RNO[70]\ : - MX2 - port map(A => \sample_in_buf[52]\, B => sample_4(1), S => - sample_val_delay_3, Y => \sample_in_buf_1053[70]\); - - \loop_all_sample.7.loop_all_chanel.6.sample_in_buf[28]\ : - DFN1E1C0 - port map(D => \sample_in_buf_653[28]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[28]\); - - \loop_all_sample.13.loop_all_chanel.3.sample_in_buf[76]\ : - DFN1E1C0 - port map(D => \sample_in_buf_293[76]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[76]\); - - \loop_all_sample.17.loop_all_chanel.6.sample_in_buf[18]\ : - DFN1E1C0 - port map(D => \sample_in_buf_13[18]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[18]\); - - \loop_all_sample.0.loop_all_chanel.3.sample_in_buf_RNO[89]\ : - MX2 - port map(A => \sample_in_buf[71]\, B => sample_3(0), S => - sample_val_delay_4, Y => \sample_in_buf_1125[89]\); - - \chanel_more.all_chanel.2.all_bit.11.sample_out_s2[114]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[96]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[114]\); - - \loop_all_sample.12.loop_all_chanel.1.sample_in_buf[113]\ : - DFN1E1C0 - port map(D => \sample_in_buf_373[113]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[113]\); - - \loop_all_sample.0.loop_all_chanel.4.sample_in_buf_RNO[71]\ : - MX2 - port map(A => \sample_in_buf[53]\, B => sample_4(0), S => - sample_val_delay, Y => \sample_in_buf_1117[71]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \loop_all_sample.13.loop_all_chanel.1.sample_in_buf[112]\ : - DFN1E1C0 - port map(D => \sample_in_buf_309[112]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[112]\); - - \chanel_more.all_chanel.6.all_bit.9.sample_out_s2[44]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[26]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[44]\); - - \chanel_more.all_chanel.2.all_bit.1.sample_out_s2[124]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[106]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[124]\); - - \loop_all_sample.12.loop_all_chanel.4.sample_in_buf[59]\ : - DFN1E1C0 - port map(D => \sample_in_buf_349[59]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[59]\); - - \loop_all_sample.8.loop_all_chanel.7.sample_in_buf[9]\ : - DFN1E1C0 - port map(D => \sample_in_buf_581[9]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[9]\); - - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf_RNIP7V4[126]\ : - MX2 - port map(A => \sample_in_buf[127]\, B => sample_0(15), S - => sample_val_delay_1, Y => \sample_in_s_1[17]\); - - \chanel_HIGH.5.sample_out_s2[12]\ : DFN1E1C0 - port map(D => \sample_out_s[5]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[12]\); - - \loop_all_sample.5.loop_all_chanel.0.sample_in_buf[138]\ : - DFN1E1C0 - port map(D => \sample_in_buf_829[138]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[138]\); - - \loop_all_sample.3.loop_all_chanel.5.sample_in_buf[50]\ : - DFN1E1C0 - port map(D => \sample_in_buf_917[50]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[50]\); - - \loop_all_sample.0.loop_all_chanel.1.sample_in_buf[125]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1141[125]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[125]\); - - \loop_all_sample.9.loop_all_chanel.2.sample_in_buf[98]\ : - DFN1E1C0 - port map(D => \sample_in_buf_557[98]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[98]\); - - \loop_all_sample.6.loop_all_chanel.0.sample_in_buf[137]\ : - DFN1E1C0 - port map(D => \sample_in_buf_765[137]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[137]\); - - \loop_all_sample.3.loop_all_chanel.5.sample_in_buf_RNO[50]\ : - MX2 - port map(A => \sample_in_buf[32]\, B => sample_5(3), S => - sample_val_delay_4, Y => \sample_in_buf_917[50]\); - - \loop_all_sample.1.loop_all_chanel.1.sample_in_buf[124]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1077[124]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[124]\); - - \loop_all_sample.14.loop_all_chanel.3.sample_in_buf_RNO[75]\ : - MX2 - port map(A => \sample_in_buf[57]\, B => sample_3(14), S => - sample_val_delay_2, Y => \sample_in_buf_229[75]\); - - \chanel_HIGH.4.sample_out_s2[13]\ : DFN1E1C0 - port map(D => \sample_out_s[4]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[13]\); - - \chanel_HIGH.0.sample_out_s2[17]\ : DFN1E1C0 - port map(D => \sample_out_s[0]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[17]\); - - \loop_all_sample.7.loop_all_chanel.4.sample_in_buf[64]\ : - DFN1E1C0 - port map(D => \sample_in_buf_669[64]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[64]\); - - \chanel_more.all_chanel.1.all_bit.1.sample_out_s2[142]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[124]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_140); - - \loop_all_sample.6.loop_all_chanel.6.sample_in_buf_RNO[29]\ : - MX2 - port map(A => \sample_in_buf[11]\, B => sample_6(6), S => - sample_val_delay_2, Y => \sample_in_buf_717[29]\); - - \loop_all_sample.14.loop_all_chanel.4.sample_in_buf_RNO[57]\ : - MX2 - port map(A => \sample_in_buf[39]\, B => sample_4(14), S => - sample_val_delay_5, Y => \sample_in_buf_221[57]\); - - \loop_all_sample.12.loop_all_chanel.6.sample_in_buf_RNO[23]\ : - MX2 - port map(A => \sample_in_buf[5]\, B => sample_6(12), S => - sample_val_delay_3, Y => \sample_in_buf_333[23]\); - - \chanel_more.all_chanel.5.all_bit.4.sample_out_s2[67]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[49]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[67]\); - - \chanel_more.all_chanel.3.all_bit.9.sample_out_s2[98]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[80]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[98]\); - - \loop_all_sample.7.loop_all_chanel.5.sample_in_buf[46]\ : - DFN1E1C0 - port map(D => \sample_in_buf_661[46]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[46]\); - - \loop_all_sample.9.loop_all_chanel.0.sample_in_buf[134]\ : - DFN1E1C0 - port map(D => \sample_in_buf_573[134]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[134]\); - - \chanel_more.all_chanel.4.all_bit.3.sample_out_s2[86]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[68]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[86]\); - - \loop_all_sample.5.loop_all_chanel.7.sample_in_buf[12]\ : - DFN1E1C0 - port map(D => \sample_in_buf_773[12]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[12]\); - - \loop_all_sample.4.loop_all_chanel.7.sample_in_buf[13]\ : - DFN1E1C0 - port map(D => \sample_in_buf_837[13]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[13]\); - - \loop_all_sample.2.loop_all_chanel.4.sample_in_buf[69]\ : - DFN1E1C0 - port map(D => \sample_in_buf_989[69]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[69]\); - - \loop_all_sample.12.loop_all_chanel.0.sample_in_buf[131]\ : - DFN1E1C0 - port map(D => \sample_in_buf_381[131]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[131]\); - - \loop_all_sample.4.loop_all_chanel.5.sample_in_buf[49]\ : - DFN1E1C0 - port map(D => \sample_in_buf_853[49]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[49]\); - - \loop_all_sample.11.loop_all_chanel.6.sample_in_buf[24]\ : - DFN1E1C0 - port map(D => \sample_in_buf_397[24]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[24]\); - - \loop_all_sample.3.loop_all_chanel.7.sample_in_buf_RNO[14]\ : - MX2 - port map(A => \sample_in_buf[140]\, B => sample_7(3), S => - sample_val_delay_3, Y => \sample_in_buf_901[14]\); - - \loop_all_sample.1.loop_all_chanel.0.sample_in_buf[142]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1085[142]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[142]\); - - \loop_all_sample.8.loop_all_chanel.4.sample_in_buf[63]\ : - DFN1E1C0 - port map(D => \sample_in_buf_605[63]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate, Q => - \sample_in_buf[63]\); - - \loop_all_sample.10.loop_all_chanel.1.sample_in_buf[115]\ : - DFN1E1C0 - port map(D => \sample_in_buf_501[115]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[115]\); - - \loop_all_sample.0.loop_all_chanel.4.sample_in_buf[71]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1117[71]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[71]\); - - \loop_all_sample.4.loop_all_chanel.3.sample_in_buf_RNO[85]\ : - MX2 - port map(A => \sample_in_buf[67]\, B => sample_3(4), S => - sample_val_delay_4, Y => \sample_in_buf_869[85]\); - - \loop_all_sample.13.loop_all_chanel.3.sample_in_buf_RNO[76]\ : - MX2 - port map(A => \sample_in_buf[58]\, B => sample_3(13), S => - sample_val_delay, Y => \sample_in_buf_293[76]\); - - \loop_all_sample.14.loop_all_chanel.1.sample_in_buf[111]\ : - DFN1E1C0 - port map(D => \sample_in_buf_245[111]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[111]\); - - \chanel_more.all_chanel.3.all_bit.5.sample_out_s2[102]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[84]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[102]\); - - \loop_all_sample.2.loop_all_chanel.7.sample_in_buf[15]\ : - DFN1E1C0 - port map(D => \sample_in_buf_965[15]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[15]\); - - \loop_all_sample.14.loop_all_chanel.7.sample_in_buf_RNO[3]\ : - MX2 - port map(A => \sample_in_buf[129]\, B => sample_7(14), S - => sample_val_delay_1, Y => \sample_in_buf_197[3]\); - - \chanel_more.all_chanel.7.all_bit.4.sample_out_s2[31]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[13]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[31]\); - - \loop_all_sample.7.loop_all_chanel.2.sample_in_buf_RNO[100]\ : - MX2 - port map(A => \sample_in_buf[82]\, B => sample_2(7), S => - sample_val_delay_2, Y => \sample_in_buf_685[100]\); - - \loop_all_sample.8.loop_all_chanel.0.sample_in_buf_RNO[135]\ : - MX2 - port map(A => \sample_in_buf[117]\, B => sample_0(8), S => - sample_val_delay_0, Y => \sample_in_buf_637[135]\); - - \loop_all_sample.7.loop_all_chanel.5.sample_in_buf_RNO[46]\ : - MX2 - port map(A => \sample_in_buf[28]\, B => sample_5(7), S => - sample_val_delay_2, Y => \sample_in_buf_661[46]\); - - \loop_all_sample.7.loop_all_chanel.1.sample_in_buf[118]\ : - DFN1E1C0 - port map(D => \sample_in_buf_693[118]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[118]\); - - \chanel_more.all_chanel.5.all_bit.3.sample_out_s2[68]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[50]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[68]\); - - \loop_all_sample.11.loop_all_chanel.5.sample_in_buf_RNO[42]\ : - MX2 - port map(A => \sample_in_buf[24]\, B => sample_5(11), S => - sample_val_delay_3, Y => \sample_in_buf_405[42]\); - - \chanel_more.all_chanel.3.all_bit.12.sample_out_s2[95]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[77]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[95]\); - - \loop_all_sample.1.loop_all_chanel.0.sample_in_buf_RNO[142]\ : - MX2 - port map(A => \sample_in_buf[124]\, B => sample_0(1), S => - sample_val_delay_1, Y => \sample_in_buf_1085[142]\); - - \loop_all_sample.12.loop_all_chanel.6.sample_in_buf[23]\ : - DFN1E1C0 - port map(D => \sample_in_buf_333[23]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[23]\); - - \chanel_more.all_chanel.5.all_bit.15.sample_out_s2[56]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[38]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[56]\); - - \loop_all_sample.4.loop_all_chanel.0.sample_in_buf[139]\ : - DFN1E1C0 - port map(D => \sample_in_buf_893[139]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[139]\); - - \chanel_more.all_chanel.6.all_bit.5.sample_out_s2[48]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[30]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[48]\); - - \loop_all_sample.4.loop_all_chanel.4.sample_in_buf[67]\ : - DFN1E1C0 - port map(D => \sample_in_buf_861[67]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[67]\); - - \loop_all_sample.12.loop_all_chanel.0.sample_in_buf_RNO[131]\ : - MX2 - port map(A => \sample_in_buf[113]\, B => sample_0(12), S - => sample_val_delay_0, Y => \sample_in_buf_381[131]\); - - \chanel_more.all_chanel.4.all_bit.2.sample_out_s2[87]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[69]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[87]\); - - \loop_all_sample.5.loop_all_chanel.0.sample_in_buf_RNO[138]\ : - MX2 - port map(A => \sample_in_buf[120]\, B => sample_0(5), S => - sample_val_delay_5, Y => \sample_in_buf_829[138]\); - - \chanel_more.all_chanel.7.all_bit.5.sample_out_s2[30]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[12]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[30]\); - - \chanel_more.all_chanel.5.all_bit.14.sample_out_s2[57]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[39]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[57]\); - - \loop_all_sample.9.loop_all_chanel.5.sample_in_buf_RNO[44]\ : - MX2 - port map(A => \sample_in_buf[26]\, B => sample_5(9), S => - sample_val_delay_4, Y => \sample_in_buf_533[44]\); - - \chanel_more.all_chanel.3.all_bit.2.sample_out_s2[105]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[87]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[105]\); - - \loop_all_sample.5.loop_all_chanel.2.sample_in_buf[102]\ : - DFN1E1C0 - port map(D => \sample_in_buf_813[102]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[102]\); - - \chanel_HIGH.10.sample_out_s2[7]\ : DFN1E1C0 - port map(D => \sample_out_s[10]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[7]\); - - \chanel_more.all_chanel.6.all_bit.13.sample_out_s2[40]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[22]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[40]\); - - \chanel_more.all_chanel.5.all_bit.12.sample_out_s2[59]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[41]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[59]\); - - \loop_all_sample.14.loop_all_chanel.3.sample_in_buf[75]\ : - DFN1E1C0 - port map(D => \sample_in_buf_229[75]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[75]\); - - \loop_all_sample.14.loop_all_chanel.2.sample_in_buf_RNO[93]\ : - MX2 - port map(A => \sample_in_buf[75]\, B => sample_2(14), S => - sample_val_delay_4, Y => \sample_in_buf_237[93]\); - - \loop_all_sample.10.loop_all_chanel.5.sample_in_buf_RNO[43]\ : - MX2 - port map(A => \sample_in_buf[25]\, B => sample_5(10), S => - sample_val_delay_4, Y => \sample_in_buf_469[43]\); - - \loop_all_sample.0.loop_all_chanel.7.sample_in_buf[17]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1093[17]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[17]\); - - \loop_all_sample.6.loop_all_chanel.3.sample_in_buf_RNO[83]\ : - MX2 - port map(A => \sample_in_buf[65]\, B => sample_3(6), S => - sample_val_delay_5, Y => \sample_in_buf_741[83]\); - - \loop_all_sample.5.loop_all_chanel.6.sample_in_buf[30]\ : - DFN1E1C0 - port map(D => \sample_in_buf_781[30]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[30]\); - - \loop_all_sample.13.loop_all_chanel.0.sample_in_buf[130]\ : - DFN1E1C0 - port map(D => \sample_in_buf_317[130]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[130]\); - - \loop_all_sample.10.loop_all_chanel.7.sample_in_buf[7]\ : - DFN1E1C0 - port map(D => \sample_in_buf_453[7]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[7]\); - - \loop_all_sample.0.loop_all_chanel.0.sample_in_buf_RNO[143]\ : - MX2 - port map(A => \sample_in_buf[125]\, B => sample_0(0), S => - sample_val_delay_5, Y => \sample_in_buf_1149[143]\); - - \chanel_more.all_chanel.4.all_bit.12.sample_out_s2[77]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[59]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[77]\); - - \loop_all_sample.2.loop_all_chanel.6.sample_in_buf_RNO[33]\ : - MX2 - port map(A => \sample_in_buf[15]\, B => sample_6(2), S => - sample_val_delay_2, Y => \sample_in_buf_973[33]\); - - \chanel_more.all_chanel.5.all_bit.5.sample_out_s2[66]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[48]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[66]\); - - \loop_all_sample.6.loop_all_chanel.1.sample_in_buf[119]\ : - DFN1E1C0 - port map(D => \sample_in_buf_757[119]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[119]\); - - \loop_all_sample.0.loop_all_chanel.5.sample_in_buf[53]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1109[53]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[53]\); - - \loop_all_sample.17.loop_all_chanel.6.sample_in_buf_RNO[18]\ : - MX2 - port map(A => \sample_in_buf[1]\, B => sample_6(15), S => - sample_val_delay_2, Y => \sample_in_buf_13[18]\); - - \chanel_more.all_chanel.6.all_bit.4.sample_out_s2[49]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[31]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[49]\); - - \chanel_more.all_chanel.5.all_bit.1.sample_out_s2[70]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[52]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[70]\); - - \loop_all_sample.17.loop_all_chanel.7.sample_in_buf[0]\ : - DFN1E1C0 - port map(D => \sample_in_buf_5[0]\, CLK => lclk_c, CLR => - rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[1]\); - - \chanel_more.all_chanel.1.all_bit.14.sample_out_s2[129]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[111]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_127); - - \loop_all_sample.5.loop_all_chanel.1.sample_in_buf_RNO[120]\ : - MX2 - port map(A => \sample_in_buf[102]\, B => sample_1(5), S => - sample_val_delay, Y => \sample_in_buf_821[120]\); - - \loop_all_sample.0.loop_all_chanel.7.sample_in_buf_RNO[17]\ : - MX2 - port map(A => \sample_in_buf[143]\, B => sample_7(0), S => - sample_val_delay_5, Y => \sample_in_buf_1093[17]\); - - \loop_all_sample.12.loop_all_chanel.7.sample_in_buf[5]\ : - DFN1E1C0 - port map(D => \sample_in_buf_325[5]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_1, Q => - \sample_in_buf[5]\); - - \chanel_more.all_chanel.3.all_bit.8.sample_out_s2[99]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[81]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[99]\); - - \chanel_more.all_chanel.4.all_bit.7.sample_out_s2[82]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[64]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[82]\); - - \loop_all_sample.10.loop_all_chanel.0.sample_in_buf[133]\ : - DFN1E1C0 - port map(D => \sample_in_buf_509[133]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[133]\); - - \loop_all_sample.3.loop_all_chanel.7.sample_in_buf[14]\ : - DFN1E1C0 - port map(D => \sample_in_buf_901[14]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_3, Q => - \sample_in_buf[14]\); - - \chanel_HIGH.8.sample_out_s2[9]\ : DFN1E1C0 - port map(D => \sample_out_s[8]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[9]\); - - \chanel_more.all_chanel.5.all_bit.2.sample_out_s2[69]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[51]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[69]\); - - \chanel_more.all_chanel.1.all_bit.0.sample_out_s2[143]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[125]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_141); - - \chanel_more.all_chanel.1.all_bit.12.sample_out_s2[131]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[113]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_129); - - \chanel_HIGH.3.sample_out_s2[14]\ : DFN1E1C0 - port map(D => \sample_out_s[3]\, CLK => lclk_c, CLR => rstn, - E => sample_out_rot_s_0, Q => \sample_filter_v2_out[14]\); - - \chanel_more.all_chanel.7.all_bit.12.sample_out_s2[23]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[5]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[23]\); - - \loop_all_sample.8.loop_all_chanel.1.sample_in_buf_RNO[117]\ : - MX2 - port map(A => \sample_in_buf[99]\, B => sample_1(8), S => - sample_val_delay_2, Y => \sample_in_buf_629[117]\); - - \loop_all_sample.10.loop_all_chanel.0.sample_in_buf_RNO[133]\ : - MX2 - port map(A => \sample_in_buf[115]\, B => sample_0(10), S - => sample_val_delay_1, Y => \sample_in_buf_509[133]\); - - \loop_all_sample.11.loop_all_chanel.3.sample_in_buf[78]\ : - DFN1E1C0 - port map(D => \sample_in_buf_421[78]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[78]\); - - \chanel_HIGH.11.sample_out_s2[6]\ : DFN1E1C0 - port map(D => \sample_out_s[11]\, CLK => lclk_c, CLR => - rstn, E => sample_out_rot_s_0, Q => - \sample_filter_v2_out[6]\); - - \loop_all_sample.10.loop_all_chanel.3.sample_in_buf_RNO[79]\ : - MX2 - port map(A => \sample_in_buf[61]\, B => sample_3(10), S => - sample_val_delay_3, Y => \sample_in_buf_485[79]\); - - \chanel_more.all_chanel.1.all_bit.11.sample_out_s2[132]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[114]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_130); - - \chanel_more.all_chanel.1.all_bit.10.sample_out_s2[133]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[115]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_0, Q => - sample_filter_v2_out_131); - - \loop_all_sample.13.loop_all_chanel.1.sample_in_buf_RNO[112]\ : - MX2 - port map(A => \sample_in_buf[94]\, B => sample_1(13), S => - sample_val_delay_2, Y => \sample_in_buf_309[112]\); - - \loop_all_sample.6.loop_all_chanel.3.sample_in_buf[83]\ : - DFN1E1C0 - port map(D => \sample_in_buf_741[83]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[83]\); - - \loop_all_sample.2.loop_all_chanel.3.sample_in_buf_RNO[87]\ : - MX2 - port map(A => \sample_in_buf[69]\, B => sample_3(2), S => - sample_val_delay_4, Y => \sample_in_buf_997[87]\); - - \loop_all_sample.1.loop_all_chanel.5.sample_in_buf[52]\ : - DFN1E1C0 - port map(D => \sample_in_buf_1045[52]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[52]\); - - \chanel_more.all_chanel.7.all_bit.0.sample_out_s2[35]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[17]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[35]\); - - \chanel_more.all_chanel.4.all_bit.14.sample_out_s2[75]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[57]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[75]\); - - \chanel_more.all_chanel.2.all_bit.4.sample_out_s2[121]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[103]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[121]\); - - \chanel_more.all_chanel.2.all_bit.12.sample_out_s2[113]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[95]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - \sample_filter_v2_out[113]\); - - \chanel_more.all_chanel.1.all_bit.7.sample_out_s2[136]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[118]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_134); - - \chanel_more.all_chanel.1.all_bit.2.sample_out_s2[141]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[123]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_1, Q => - sample_filter_v2_out_139); - - \loop_all_sample.6.loop_all_chanel.2.sample_in_buf_RNO[101]\ : - MX2 - port map(A => \sample_in_buf[83]\, B => sample_2(6), S => - sample_val_delay_5, Y => \sample_in_buf_749[101]\); - - \chanel_more.all_chanel.5.all_bit.11.sample_out_s2[60]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[42]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_3, Q => - \sample_filter_v2_out[60]\); - - \loop_all_sample.1.loop_all_chanel.1.sample_in_buf_RNO[124]\ : - MX2 - port map(A => \sample_in_buf[106]\, B => sample_1(1), S => - sample_val_delay_3, Y => \sample_in_buf_1077[124]\); - - IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL - port map(alu_ctrl(2) => \alu_ctrl[2]\, alu_ctrl(1) => - \alu_ctrl[1]\, alu_ctrl(0) => \alu_ctrl[0]\, - ram_sel_Wdata(1) => \ram_sel_Wdata[1]\, ram_sel_Wdata(0) - => \ram_sel_Wdata[0]\, waddr_previous(1) => - \waddr_previous[1]\, waddr_previous(0) => - \waddr_previous[0]\, in_sel_src(1) => \in_sel_src[1]\, - in_sel_src(0) => \in_sel_src[0]\, alu_sel_coeff(4) => - \alu_sel_coeff[4]\, alu_sel_coeff(3) => - \alu_sel_coeff[3]\, alu_sel_coeff(2) => - \alu_sel_coeff[2]\, alu_sel_coeff(1) => - \alu_sel_coeff[1]\, alu_sel_coeff(0) => - \alu_sel_coeff[0]\, S_36 => \S[44]\, S_0 => \S[8]\, - alu_sel_coeff_0_2 => \alu_sel_coeff_0[2]\, - alu_sel_coeff_0_0 => \alu_sel_coeff_0[0]\, - sample_out_rot_s => sample_out_rot_s, sample_out_val_s - => sample_out_val_s, raddr_rst => raddr_rst, - alu_sel_input => alu_sel_input, raddr_add1 => raddr_add1, - un1_sample_in_rotate => un1_sample_in_rotate, - sample_val_delay_2 => sample_val_delay_2, - sample_val_delay_1 => sample_val_delay_1, ram_write => - ram_write, ram_write_i => ram_write_i, - un1_sample_in_rotate_0 => un1_sample_in_rotate_0, - un1_sample_in_rotate_1 => un1_sample_in_rotate_1, - un1_sample_in_rotate_2 => un1_sample_in_rotate_2, - un1_sample_in_rotate_3 => un1_sample_in_rotate_3, - sample_val_delay_0 => sample_val_delay_0, - un1_sample_in_rotate_4 => un1_sample_in_rotate_4, - sample_out_rot_s_0 => sample_out_rot_s_0, - sample_out_rot_s_1 => sample_out_rot_s_1, - sample_out_rot_s_2 => sample_out_rot_s_2, - sample_out_rot_s_3 => sample_out_rot_s_3, - sample_out_rot_s_4 => sample_out_rot_s_4, rstn => rstn, - lclk_c => lclk_c); - - \loop_all_sample.7.loop_all_chanel.3.sample_in_buf_RNO[82]\ : - MX2 - port map(A => \sample_in_buf[64]\, B => sample_3(7), S => - sample_val_delay_3, Y => \sample_in_buf_677[82]\); - - \chanel_more.all_chanel.7.all_bit.8.sample_out_s2[27]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[9]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[27]\); - - \chanel_more.all_chanel.6.all_bit.7.sample_out_s2[46]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[28]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_4, Q => - \sample_filter_v2_out[46]\); - - \loop_all_sample.7.loop_all_chanel.3.sample_in_buf[82]\ : - DFN1E1C0 - port map(D => \sample_in_buf_677[82]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[82]\); - - \loop_all_sample.17.loop_all_chanel.0.sample_in_buf[126]\ : - DFN1E1C0 - port map(D => \sample_in_buf_61[126]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_2, Q => - \sample_in_buf[127]\); - - \loop_all_sample.11.loop_all_chanel.4.sample_in_buf[60]\ : - DFN1E1C0 - port map(D => \sample_in_buf_413[60]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_0, Q => - \sample_in_buf[60]\); - - \loop_all_sample.3.loop_all_chanel.6.sample_in_buf_RNO[32]\ : - MX2 - port map(A => \sample_in_buf[14]\, B => sample_6(3), S => - sample_val_delay_5, Y => \sample_in_buf_909[32]\); - - \loop_all_sample.17.loop_all_chanel.1.sample_in_buf_RNO[108]\ : - MX2 - port map(A => \sample_in_buf[90]\, B => sample_1(15), S => - sample_val_delay_2, Y => \sample_in_buf_53[108]\); - - \loop_all_sample.8.loop_all_chanel.6.sample_in_buf_RNO[27]\ : - MX2 - port map(A => \sample_in_buf[9]\, B => sample_6(8), S => - sample_val_delay_4, Y => \sample_in_buf_589[27]\); - - \loop_all_sample.5.loop_all_chanel.4.sample_in_buf[66]\ : - DFN1E1C0 - port map(D => \sample_in_buf_797[66]\, CLK => lclk_c, CLR - => rstn, E => un1_sample_in_rotate_4, Q => - \sample_in_buf[66]\); - - \loop_all_sample.14.loop_all_chanel.1.sample_in_buf_RNO[111]\ : - MX2 - port map(A => \sample_in_buf[93]\, B => sample_1(14), S => - sample_val_delay_4, Y => \sample_in_buf_245[111]\); - - \chanel_more.all_chanel.2.all_bit.8.sample_out_s2[117]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[99]\, CLK => lclk_c, - CLR => rstn, E => sample_out_rot_s_2, Q => - \sample_filter_v2_out[117]\); - - \chanel_more.all_chanel.7.all_bit.11.sample_out_s2[24]\ : - DFN1E1C0 - port map(D => \sample_filter_v2_out[6]\, CLK => lclk_c, CLR - => rstn, E => sample_out_rot_s, Q => - \sample_filter_v2_out[24]\); - - \loop_all_sample.8.loop_all_chanel.2.sample_in_buf_RNO[99]\ : - MX2 - port map(A => \sample_in_buf[81]\, B => sample_2(8), S => - sample_val_delay_2, Y => \sample_in_buf_621[99]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_6_16_256 is - - port( sample_f1 : in std_logic_vector(111 downto 80); - sample_f1_wdata_95 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_0 : in std_logic; - sample_f3_wdata : out std_logic_vector(95 downto 0); - sample_f1_val : in std_logic; - lclk_c : in std_logic; - sample_f3_val : out std_logic; - sample_f1_val_0 : in std_logic; - rstn : in std_logic - ); - -end Downsampling_6_16_256; - -architecture DEF_ARCH of Downsampling_6_16_256 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal sample_out_0_sqmuxa_2, sample_out_val_4, - sample_out_0_sqmuxa_1, sample_out_0_sqmuxa_0, N_137, - \counter[1]_net_1\, \counter[0]_net_1\, N_129, - \counter[3]_net_1\, \DWACT_FDEC_E[0]\, N_106, - \counter[8]_net_1\, \DWACT_FDEC_E[4]\, N_91, - \DWACT_FDEC_E[7]\, \DWACT_FDEC_E[6]\, - un2_sample_in_val_24, un2_sample_in_val_15, - un2_sample_in_val_14, un2_sample_in_val_20, - un2_sample_in_val_23, un2_sample_in_val_9, - un2_sample_in_val_8, un2_sample_in_val_19, - un2_sample_in_val_22, un2_sample_in_val_5, - un2_sample_in_val_4, un2_sample_in_val_17, - un2_sample_in_val_13, \counter[24]_net_1\, - un2_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un2_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un2_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un2_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un2_sample_in_val_i_0, - sample_out_0_sqmuxa, \counter_4[0]\, I_45_9, - \counter_4[1]\, I_52_9, \counter_4[2]\, I_56_10, - \counter_4[4]\, I_73_8, \counter_4[5]\, I_77_8, - \counter_4[7]\, I_91_8, \counter_4[8]\, I_98_8, - \counter_4[10]\, I_115_8, \counter_4[11]\, I_122_8, - \counter_4[13]\, I_136_7, \counter_4[14]\, I_143_7, - \counter_4[3]\, I_66_10, \counter_4[12]\, I_129_8, - \counter_4[15]\, I_156_7, \counter_4[16]\, I_166_7, - \counter_4[17]\, I_173_7, \counter_4[18]\, I_186_7, - \counter_4[19]\, I_196_7, \counter_4[9]\, I_105_8, - \counter_4[6]\, I_84_8, I_4_2, I_5_13, I_9_13, I_13_17, - I_20_13, I_24_14, I_31_13, I_38_10, N_4, - \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val_0, Q => \counter[19]_net_1\); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f1_wdata_73, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(73)); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f1_wdata_75, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(75)); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f1_wdata_82, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(82)); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f1_wdata_94, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(94)); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f1_wdata_76, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(76)); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f1(93), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(34)); - - \sample_out[66]\ : DFN1E1 - port map(D => sample_f1(98), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(29)); - - \sample_out[73]\ : DFN1E1 - port map(D => sample_f1(105), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(22)); - - \sample_out[79]\ : DFN1E1 - port map(D => sample_f1(111), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(16)); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f1_wdata_57, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(57)); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f1_wdata_0, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(0)); - - \counter_RNO[11]\ : NOR2B - port map(A => I_66_10, B => un2_sample_in_val_i_0, Y => - \counter_4[3]\); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f1_wdata_61, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(61)); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_2); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[11]_net_1\); - - \counter_RNIQ01S[12]\ : NOR3C - port map(A => un2_sample_in_val_9, B => un2_sample_in_val_8, - C => un2_sample_in_val_19, Y => un2_sample_in_val_23); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \counter_RNIU2M9[20]\ : NOR3A - port map(A => un2_sample_in_val_3, B => \counter[23]_net_1\, - C => \counter[20]_net_1\, Y => un2_sample_in_val_15); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_7); - - \counter_RNO[15]\ : NOR2B - port map(A => I_91_8, B => un2_sample_in_val_i_0, Y => - \counter_4[7]\); - - \counter_RNITFBJ2_0[10]\ : NOR2B - port map(A => sample_out_val_4, B => rstn, Y => - sample_out_0_sqmuxa_1); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f1(83), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(44)); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f1(88), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(39)); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f1_wdata_95, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(95)); - - \counter[6]\ : DFN1E1C0 - port map(D => I_31_13, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_17); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f1_wdata_14, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(14)); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f1_wdata_9, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(9)); - - \counter[3]\ : DFN1E1C0 - port map(D => I_13_17, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_13, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_8); - - \counter_RNO[8]\ : NOR2B - port map(A => I_45_9, B => un2_sample_in_val_i_0, Y => - \counter_4[0]\); - - \counter_RNO[13]\ : NOR2B - port map(A => I_77_8, B => un2_sample_in_val_i_0, Y => - \counter_4[5]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_9); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f1_wdata_83, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(83)); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f1_wdata_85, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(85)); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f1_wdata_50, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(50)); - - \counter_RNO[12]\ : NOR2B - port map(A => I_73_8, B => un2_sample_in_val_i_0, Y => - \counter_4[4]\); - - \counter_RNIBHB5[12]\ : NOR3A - port map(A => un2_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un2_sample_in_val_19); - - \sample_out[72]\ : DFN1E1 - port map(D => sample_f1(104), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(23)); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f1_wdata_62, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(62)); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f1_wdata_56, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(56)); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[17]_net_1\); - - \sample_out[70]\ : DFN1E1 - port map(D => sample_f1(102), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(25)); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => I_20_13, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_13); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f1_wdata_90, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(90)); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f1_wdata_48, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(48)); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \sample_out[65]\ : DFN1E1 - port map(D => sample_f1(97), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(30)); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f1_wdata_74, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(74)); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f1_wdata_69, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(69)); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f1_wdata_93, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(93)); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[27]_net_1\); - - \counter_RNIK9AB[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un2_sample_in_val_8); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \sample_out[67]\ : DFN1E1 - port map(D => sample_f1(99), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(28)); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f1_wdata_1, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(1)); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_7); - - \counter_RNO[17]\ : NOR2B - port map(A => I_105_8, B => un2_sample_in_val_i_0, Y => - \counter_4[9]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \counter_RNILML2[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un2_sample_in_val_5); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f1(87), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(40)); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \counter_RNI9407[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un2_sample_in_val_3); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_7); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f1_wdata_63, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(63)); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_8); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f1(89), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(38)); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f1_wdata_65, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(65)); - - \counter_RNO[14]\ : NOR2B - port map(A => I_84_8, B => un2_sample_in_val_i_0, Y => - \counter_4[6]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f1_wdata_10, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(10)); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_13, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => I_186_7, B => un2_sample_in_val_i_0, Y => - \counter_4[18]\); - - \counter_RNIR5BB[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un2_sample_in_val_9); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f1_wdata_91, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(91)); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[25]_net_1\); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_4, CLK => lclk_c, CLR => rstn, - Q => sample_f3_val); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f1_wdata_8, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(8)); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_8); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_7); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f1(80), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(47)); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_10); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f1_wdata_2, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(2)); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f1_wdata_84, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(84)); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f1_wdata_79, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(79)); - - \counter[5]\ : DFN1E1C0 - port map(D => I_24_14, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f1_wdata_51, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(51)); - - \sample_out[71]\ : DFN1E1 - port map(D => sample_f1(103), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(24)); - - \sample_out[76]\ : DFN1E1 - port map(D => sample_f1(108), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(19)); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : NOR2B - port map(A => I_56_10, B => un2_sample_in_val_i_0, Y => - \counter_4[2]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_13); - - \counter_RNO[21]\ : NOR2B - port map(A => I_136_7, B => un2_sample_in_val_i_0, Y => - \counter_4[13]\); - - \counter_RNISLA11[20]\ : NOR3C - port map(A => un2_sample_in_val_15, B => - un2_sample_in_val_14, C => un2_sample_in_val_20, Y => - un2_sample_in_val_24); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_13); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[68]\ : DFN1E1 - port map(D => sample_f1(100), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(27)); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f1_wdata_70, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(70)); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_10); - - \counter_RNI3KVH2[10]\ : NOR2A - port map(A => sample_f1_val_0, B => un2_sample_in_val_i_0, - Y => sample_out_val_4); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => I_173_7, B => un2_sample_in_val_i_0, Y => - \counter_4[17]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - \sample_out[64]\ : DFN1E1 - port map(D => sample_f1(96), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(31)); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_13); - - \counter_RNITFBJ2[10]\ : NOR2B - port map(A => sample_out_val_4, B => rstn, Y => - sample_out_0_sqmuxa_2); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_8); - - \counter_RNIEHB5[27]\ : NOR3A - port map(A => un2_sample_in_val_1, B => \counter[11]_net_1\, - C => \counter[27]_net_1\, Y => un2_sample_in_val_14); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f1_wdata_68, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(68)); - - \counter_RNI5OV6[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un2_sample_in_val_7); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_7); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f1(90), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(37)); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_10); - - \counter_RNO[23]\ : NOR2B - port map(A => I_156_7, B => un2_sample_in_val_i_0, Y => - \counter_4[15]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f1(86), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(41)); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f1_wdata_52, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(52)); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f1(81), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(46)); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_9); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_14); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f1_wdata_3, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(3)); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val_0, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_7); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f1_wdata_7, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(7)); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f1_wdata_5, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(5)); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_8); - - \counter_RNO[22]\ : NOR2B - port map(A => I_143_7, B => un2_sample_in_val_i_0, Y => - \counter_4[14]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f1_wdata_64, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(64)); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f1_wdata_59, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(59)); - - \counter_RNIG19I[24]\ : NOR3A - port map(A => un2_sample_in_val_13, B => \counter[1]_net_1\, - C => \counter[24]_net_1\, Y => un2_sample_in_val_20); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f1_wdata_11, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(11)); - - \counter_RNIMHBJ[10]\ : NOR3C - port map(A => un2_sample_in_val_5, B => un2_sample_in_val_4, - C => un2_sample_in_val_17, Y => un2_sample_in_val_22); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f1(95), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(32)); - - \sample_out[69]\ : DFN1E1 - port map(D => sample_f1(101), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(26)); - - \counter_RNIC8NG2[10]\ : OR3C - port map(A => un2_sample_in_val_23, B => - un2_sample_in_val_22, C => un2_sample_in_val_24, Y => - un2_sample_in_val_i_0); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f1_wdata_80, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(80)); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_8); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[75]\ : DFN1E1 - port map(D => sample_f1(107), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(20)); - - \counter_RNITFBJ2_1[10]\ : NOR2B - port map(A => sample_out_val_4, B => rstn, Y => - sample_out_0_sqmuxa); - - \counter_RNITFBJ2_2[10]\ : NOR2B - port map(A => sample_out_val_4, B => rstn, Y => - sample_out_0_sqmuxa_0); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_8); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f1_wdata_78, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(78)); - - \counter_RNO[18]\ : NOR2B - port map(A => I_115_8, B => un2_sample_in_val_i_0, Y => - \counter_4[10]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[77]\ : DFN1E1 - port map(D => sample_f1(109), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(18)); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f1(85), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(42)); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f1_wdata_67, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(67)); - - \counter_RNO[27]\ : NOR2B - port map(A => I_196_7, B => un2_sample_in_val_i_0, Y => - \counter_4[19]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f1(91), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(36)); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f1_wdata_71, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(71)); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f1_wdata_53, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(53)); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f1_wdata_55, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(55)); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f1_wdata_12, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(12)); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f1_wdata_6, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(6)); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => I_166_7, B => un2_sample_in_val_i_0, Y => - \counter_4[16]\); - - \counter[7]\ : DFN1E1C0 - port map(D => I_38_10, CLK => lclk_c, CLR => rstn, E => - sample_f1_val, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_8); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f1_wdata_89, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(89)); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f1(94), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(33)); - - \counter_RNIVIL9[19]\ : NOR3A - port map(A => un2_sample_in_val_7, B => \counter[22]_net_1\, - C => \counter[19]_net_1\, Y => un2_sample_in_val_17); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f1(92), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(35)); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f1_wdata_60, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(60)); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f1_wdata_4, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(4)); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : NOR2B - port map(A => I_129_8, B => un2_sample_in_val_i_0, Y => - \counter_4[12]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f1_wdata_58, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(58)); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f1_wdata_72, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(72)); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f1(84), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(43)); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f1_wdata_66, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(66)); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f1(82), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(45)); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f1_wdata_77, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(77)); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f1_wdata_86, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(86)); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f1_wdata_88, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(88)); - - \sample_out[78]\ : DFN1E1 - port map(D => sample_f1(110), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(17)); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f1_wdata_81, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f3_wdata(81)); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f1_wdata_13, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(13)); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val, Q => \counter[9]_net_1\); - - \counter_RNIDD9B[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un2_sample_in_val_13); - - \sample_out[74]\ : DFN1E1 - port map(D => sample_f1(106), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f3_wdata(21)); - - \counter_RNI2807[10]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un2_sample_in_val_4); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f1_wdata_15, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(15)); - - \counter_RNO[19]\ : NOR2B - port map(A => I_122_8, B => un2_sample_in_val_i_0, Y => - \counter_4[11]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNINML2[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un2_sample_in_val_1); - - \counter_RNO[9]\ : NOR2B - port map(A => I_52_9, B => un2_sample_in_val_i_0, Y => - \counter_4[1]\); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[0]\, CLK => lclk_c, CLR => rstn, E - => sample_f1_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_8); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_7); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => lclk_c, CLR => rstn, - E => sample_f1_val_0, Q => \counter[18]_net_1\); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f1_wdata_87, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f3_wdata(87)); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f1_wdata_54, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(54)); - - \counter_RNO[16]\ : NOR2B - port map(A => I_98_8, B => un2_sample_in_val_i_0, Y => - \counter_4[8]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_2, CLK => lclk_c, CLR => rstn, E => - sample_f1_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f1_wdata_49, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(49)); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f1_wdata_92, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f3_wdata(92)); - - \counter_RNIOQL2[18]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un2_sample_in_val_11); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_6_16_96 is - - port( sample_f0 : in std_logic_vector(111 downto 80); - sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f2_wdata : out std_logic_vector(95 downto 0); - sample_f0_val : in std_logic; - sample_f0_val_2 : in std_logic; - lclk_c : in std_logic; - sample_f2_val : out std_logic; - sample_f0_val_0 : in std_logic; - rstn : in std_logic - ); - -end Downsampling_6_16_96; - -architecture DEF_ARCH of Downsampling_6_16_96 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un6_sample_in_val_0, un6_sample_in_val_23, - un6_sample_in_val_22, un6_sample_in_val_24, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1, - sample_out_0_sqmuxa_0, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un6_sample_in_val_15, - un6_sample_in_val_14, un6_sample_in_val_20, - un6_sample_in_val_9, un6_sample_in_val_8, - un6_sample_in_val_19, un6_sample_in_val_5, - un6_sample_in_val_4, un6_sample_in_val_17, - un6_sample_in_val_13, \counter[24]_net_1\, - un6_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un6_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un6_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un6_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un6_sample_in_val, - sample_out_0_sqmuxa, \counter_4[20]\, I_196_6, - \counter_4[19]\, I_186_6, \counter_4[18]\, I_173_6, - \counter_4[17]\, I_166_6, \counter_4[16]\, I_156_6, - \counter_4[15]\, I_143_6, \counter_4[14]\, I_136_6, - \counter_4[13]\, I_129_7, \counter_4[12]\, I_122_7, - \counter_4[11]\, I_115_7, \counter_4[10]\, I_105_7, - \counter_4[9]\, I_98_7, \counter_4[8]\, I_91_7, - \counter_4[7]\, I_84_7, \counter_4[6]\, I_77_7, - \counter_4[5]\, I_73_7, \counter_4[4]\, I_66_9, - \counter_4[3]\, I_56_9, \counter_4[2]\, I_52_8, - \counter_4[1]\, I_45_8, \counter_4[0]\, I_38_9, - \counter_4_1[5]\, I_24_13, sample_out_val_9, I_4_1, - I_5_12, I_9_12, I_13_16, I_20_12, I_31_12, N_4, - \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_2, Q => \counter[19]_net_1\); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f0_wdata_73, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(73)); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f0_wdata_75, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(75)); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f0_wdata_82, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(82)); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f0_wdata_94, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(94)); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f0_wdata_76, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(76)); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f0(93), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(34)); - - \sample_out[66]\ : DFN1E1 - port map(D => sample_f0(98), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(29)); - - \sample_out[73]\ : DFN1E1 - port map(D => sample_f0(105), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(22)); - - \sample_out[79]\ : DFN1E1 - port map(D => sample_f0(111), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(16)); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f0_wdata_57, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(57)); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f0_wdata_0, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(0)); - - \counter_RNO[11]\ : NOR2B - port map(A => un6_sample_in_val, B => I_66_9, Y => - \counter_4[4]\); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f0_wdata_61, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(61)); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_1); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_6); - - \counter_RNO[15]\ : NOR2B - port map(A => un6_sample_in_val, B => I_91_7, Y => - \counter_4[8]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f0(83), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(44)); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f0(88), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(39)); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f0_wdata_95, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(95)); - - \counter_RNO[7]\ : NOR2B - port map(A => un6_sample_in_val, B => I_38_9, Y => - \counter_4[0]\); - - \counter[6]\ : DFN1E1C0 - port map(D => I_31_12, CLK => lclk_c, CLR => rstn, E => - sample_f0_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_16); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f0_wdata_14, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(14)); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f0_wdata_9, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(9)); - - \counter[3]\ : DFN1E1C0 - port map(D => I_13_16, CLK => lclk_c, CLR => rstn, E => - sample_f0_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_12, CLK => lclk_c, CLR => rstn, E => - sample_f0_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_7); - - \counter_RNO[8]\ : NOR2B - port map(A => un6_sample_in_val, B => I_45_8, Y => - \counter_4[1]\); - - \counter_RNO[13]\ : NOR2B - port map(A => un6_sample_in_val, B => I_77_7, Y => - \counter_4[6]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_8); - - \counter_RNIAMIV[27]\ : NOR3A - port map(A => un6_sample_in_val_1, B => \counter[11]_net_1\, - C => \counter[27]_net_1\, Y => un6_sample_in_val_14); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f0_wdata_83, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(83)); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f0_wdata_85, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(85)); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f0_wdata_50, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(50)); - - \counter_RNO[12]\ : NOR2B - port map(A => un6_sample_in_val, B => I_73_7, Y => - \counter_4[5]\); - - \sample_out[72]\ : DFN1E1 - port map(D => sample_f0(104), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(23)); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f0_wdata_62, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(62)); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f0_wdata_56, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(56)); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_2, Q => \counter[17]_net_1\); - - \sample_out[70]\ : DFN1E1 - port map(D => sample_f0(102), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(25)); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => I_20_12, CLK => lclk_c, CLR => rstn, E => - sample_f0_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_12); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f0_wdata_90, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(90)); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f0_wdata_48, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(48)); - - \counter_RNI812G2[20]\ : NOR3C - port map(A => un6_sample_in_val_15, B => - un6_sample_in_val_14, C => un6_sample_in_val_20, Y => - un6_sample_in_val_24); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - \sample_out[65]\ : DFN1E1 - port map(D => sample_f0(97), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(30)); - - \counter_RNISODS5_1[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un6_sample_in_val_0, Y => sample_out_0_sqmuxa_2); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f0_wdata_74, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(74)); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f0_wdata_69, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(69)); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f0_wdata_93, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(93)); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[27]_net_1\); - - \counter_RNIC2EO5_0[4]\ : OR3C - port map(A => un6_sample_in_val_23, B => - un6_sample_in_val_22, C => un6_sample_in_val_24, Y => - un6_sample_in_val); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \sample_out[67]\ : DFN1E1 - port map(D => sample_f0(99), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(28)); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f0_wdata_1, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(1)); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_6); - - \counter_RNO[17]\ : NOR2B - port map(A => un6_sample_in_val, B => I_105_7, Y => - \counter_4[10]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[23]_net_1\); - - \counter_RNI17TR[19]\ : NOR3A - port map(A => un6_sample_in_val_7, B => \counter[22]_net_1\, - C => \counter[19]_net_1\, Y => un6_sample_in_val_17); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f0(87), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(40)); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_6); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f0_wdata_63, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(63)); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_7); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f0(89), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(38)); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f0_wdata_65, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(65)); - - \counter_RNO[14]\ : NOR2B - port map(A => un6_sample_in_val, B => I_84_7, Y => - \counter_4[7]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f0_wdata_10, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(10)); - - \counter_RNISODS5[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un6_sample_in_val_0, Y => sample_out_0_sqmuxa); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_12, CLK => lclk_c, CLR => rstn, E => - sample_f0_val_2, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_186_6, Y => - \counter_4[19]\); - - \counter_RNIQPQN1[7]\ : NOR3C - port map(A => un6_sample_in_val_5, B => un6_sample_in_val_4, - C => un6_sample_in_val_17, Y => un6_sample_in_val_22); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f0_wdata_91, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(91)); - - \counter_RNO[5]\ : NOR2B - port map(A => un6_sample_in_val, B => I_24_13, Y => - \counter_4_1[5]\); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[25]_net_1\); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_9, CLK => lclk_c, CLR => rstn, - Q => sample_f2_val); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f0_wdata_8, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(8)); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_7); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_6); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f0(80), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(47)); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_9); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f0_wdata_2, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(2)); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f0_wdata_84, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(84)); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f0_wdata_79, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(79)); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4_1[5]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f0_wdata_51, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(51)); - - \sample_out[71]\ : DFN1E1 - port map(D => sample_f0(103), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(24)); - - \sample_out[76]\ : DFN1E1 - port map(D => sample_f0(108), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(19)); - - \counter_RNIT54C[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un6_sample_in_val_3); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNI7MIV[12]\ : NOR3A - port map(A => un6_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un6_sample_in_val_19); - - \counter_RNO[10]\ : NOR2B - port map(A => un6_sample_in_val, B => I_56_9, Y => - \counter_4[3]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_12); - - \counter_RNO[21]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_136_6, Y => - \counter_4[14]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_12); - - \counter_RNIC2EO5[4]\ : OR3C - port map(A => un6_sample_in_val_23, B => - un6_sample_in_val_22, C => un6_sample_in_val_24, Y => - un6_sample_in_val_0); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[68]\ : DFN1E1 - port map(D => sample_f0(100), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(27)); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f0_wdata_70, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(70)); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_9); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_173_6, Y => - \counter_4[18]\); - - \counter_RNI6DPF[18]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un6_sample_in_val_11); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - \sample_out[64]\ : DFN1E1 - port map(D => sample_f0(96), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(31)); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_12); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_7); - - \counter_RNISODS5_0[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un6_sample_in_val_0, Y => sample_out_0_sqmuxa_0); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f0_wdata_68, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(68)); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_6); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f0(90), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(37)); - - \counter_RNIEQE8[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un6_sample_in_val_8); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_9); - - \counter_RNO[23]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_156_6, Y => - \counter_4[16]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f0(86), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(41)); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f0_wdata_52, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(52)); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f0(81), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(46)); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_8); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_13); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f0_wdata_3, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(3)); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_6); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f0_wdata_7, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(7)); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f0_wdata_5, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(5)); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_7); - - \counter_RNO[22]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_143_6, Y => - \counter_4[15]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f0_wdata_64, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(64)); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f0_wdata_59, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(59)); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \counter_RNIM94C[7]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un6_sample_in_val_4); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f0_wdata_11, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(11)); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f0(95), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(32)); - - \sample_out[69]\ : DFN1E1 - port map(D => sample_f0(101), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(26)); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f0_wdata_80, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(80)); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_7); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \counter_RNI7UD8[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un6_sample_in_val_13); - - \sample_out[75]\ : DFN1E1 - port map(D => sample_f0(107), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(20)); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_7); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f0_wdata_78, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(78)); - - \counter_RNO[18]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_115_7, Y => - \counter_4[11]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[77]\ : DFN1E1 - port map(D => sample_f0(109), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(18)); - - sample_out_val_RNO : NOR2A - port map(A => sample_f0_val_0, B => un6_sample_in_val, Y - => sample_out_val_9); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f0(85), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(42)); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f0_wdata_67, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(67)); - - \counter_RNO[27]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_196_6, Y => - \counter_4[20]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f0(91), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(36)); - - \counter_RNIPP3C[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un6_sample_in_val_7); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f0_wdata_71, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(71)); - - \counter_RNISODS5_2[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un6_sample_in_val_0, Y => sample_out_0_sqmuxa_1); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f0_wdata_53, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(53)); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f0_wdata_55, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(55)); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f0_wdata_12, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(12)); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f0_wdata_6, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(6)); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_166_6, Y => - \counter_4[17]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[0]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val, Q => \counter[7]_net_1\); - - \counter_RNI59PF[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un6_sample_in_val_1); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_7); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f0_wdata_89, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(89)); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f0(94), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(33)); - - \counter_RNILMF8[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un6_sample_in_val_9); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f0(92), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(35)); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \counter_RNI0NTR[20]\ : NOR3A - port map(A => un6_sample_in_val_3, B => \counter[23]_net_1\, - C => \counter[20]_net_1\, Y => un6_sample_in_val_15); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f0_wdata_60, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(60)); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f0_wdata_4, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(4)); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNIUJHK[24]\ : NOR3A - port map(A => un6_sample_in_val_13, B => \counter[1]_net_1\, - C => \counter[24]_net_1\, Y => un6_sample_in_val_20); - - \counter_RNI39PF[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un6_sample_in_val_5); - - \counter_RNO[20]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_129_7, Y => - \counter_4[13]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f0_wdata_58, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(58)); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f0_wdata_72, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(72)); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f0(84), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(43)); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f0_wdata_66, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(66)); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f0(82), CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(45)); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f0_wdata_77, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(77)); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f0_wdata_86, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(86)); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f0_wdata_88, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(88)); - - \sample_out[78]\ : DFN1E1 - port map(D => sample_f0(110), CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(17)); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f0_wdata_81, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f2_wdata(81)); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f0_wdata_13, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(13)); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val, Q => \counter[9]_net_1\); - - \sample_out[74]\ : DFN1E1 - port map(D => sample_f0(106), CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f2_wdata(21)); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f0_wdata_15, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(15)); - - \counter_RNO[19]\ : NOR2B - port map(A => un6_sample_in_val_0, B => I_122_7, Y => - \counter_4[12]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : NOR2B - port map(A => un6_sample_in_val, B => I_52_8, Y => - \counter_4[2]\); - - \counter_RNIA7HG1[4]\ : NOR3C - port map(A => un6_sample_in_val_9, B => un6_sample_in_val_8, - C => un6_sample_in_val_19, Y => un6_sample_in_val_23); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_7); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_6); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_2, Q => \counter[18]_net_1\); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f0_wdata_87, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f2_wdata(87)); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f0_wdata_54, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(54)); - - \counter_RNO[16]\ : NOR2B - port map(A => un6_sample_in_val, B => I_98_7, Y => - \counter_4[9]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_1, CLK => lclk_c, CLR => rstn, E => - sample_f0_val_2, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f0_wdata_49, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(49)); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f0_wdata_92, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f2_wdata(92)); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_12 is - - port( sample_f1_wdata_95 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_0 : in std_logic; - data_f1_out : out std_logic_vector(159 downto 64); - sample_f1_37 : in std_logic; - sample_f1_5 : in std_logic; - sample_f1_38 : in std_logic; - sample_f1_6 : in std_logic; - sample_f1_39 : in std_logic; - sample_f1_7 : in std_logic; - sample_f1_40 : in std_logic; - sample_f1_8 : in std_logic; - sample_f1_41 : in std_logic; - sample_f1_9 : in std_logic; - sample_f1_42 : in std_logic; - sample_f1_10 : in std_logic; - sample_f1_43 : in std_logic; - sample_f1_11 : in std_logic; - sample_f1_61 : in std_logic; - sample_f1_62 : in std_logic; - sample_f1_63 : in std_logic; - sample_f1_32 : in std_logic; - sample_f1_0 : in std_logic; - sample_f1_33 : in std_logic; - sample_f1_1 : in std_logic; - sample_f1_34 : in std_logic; - sample_f1_2 : in std_logic; - sample_f1_35 : in std_logic; - sample_f1_3 : in std_logic; - sample_f1_36 : in std_logic; - sample_f1_4 : in std_logic; - sample_f1_48 : in std_logic; - sample_f1_49 : in std_logic; - sample_f1_50 : in std_logic; - sample_f1_51 : in std_logic; - sample_f1_52 : in std_logic; - sample_f1_53 : in std_logic; - sample_f1_54 : in std_logic; - sample_f1_55 : in std_logic; - sample_f1_56 : in std_logic; - sample_f1_57 : in std_logic; - sample_f1_58 : in std_logic; - sample_f1_59 : in std_logic; - sample_f1_60 : in std_logic; - sample_f1_44 : in std_logic; - sample_f1_12 : in std_logic; - sample_f1_45 : in std_logic; - sample_f1_13 : in std_logic; - sample_f1_46 : in std_logic; - sample_f1_14 : in std_logic; - sample_f1_47 : in std_logic; - sample_f1_15 : in std_logic; - nb_snapshot_param : in std_logic_vector(0 to 0); - rstn : in std_logic; - lclk_c : in std_logic; - data_f1_out_valid : out std_logic; - data_shaping_R1 : in std_logic; - data_shaping_R1_0 : in std_logic; - I_9_31 : in std_logic; - I_45_11 : in std_logic; - I_52_11 : in std_logic; - I_56_12 : in std_logic; - I_24_16 : in std_logic; - N_4 : in std_logic; - I_20_23 : in std_logic; - I_13_35 : in std_logic; - I_38_12 : in std_logic; - I_31_15 : in std_logic; - I_5_31 : in std_logic; - enable_f1 : in std_logic; - burst_f1 : in std_logic; - sample_f1_val_0 : in std_logic; - start_snapshot_f1 : in std_logic - ); - -end lpp_waveform_snapshot_160_12; - -architecture DEF_ARCH of lpp_waveform_snapshot_160_12 is - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal counter_points_snapshot_0_sqmuxa_1_0, N_47_2, - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, N_59, - N_47_1, N_47_0, ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I296_Y_0_0, - \counter_points_snapshot[16]_net_1\, - ADD_32x32_fast_I309_Y_0_0, - \un1_counter_points_snapshot[2]\, - ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, - ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, ADD_32x32_fast_I250_Y_2, - ADD_32x32_fast_I250_Y_0, N479, N546, - \un1_counter_points_snapshot[1]\, - ADD_32x32_fast_I295_Y_0_0, - \counter_points_snapshot[15]_net_1\, - ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I292_Y_0_0, - \counter_points_snapshot[12]_net_1\, - ADD_32x32_fast_I310_Y_0_0, ADD_32x32_fast_I252_Y_1, N550, - N543, ADD_32x32_fast_I252_Y_0, N483_i, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot_i[5]\, - ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I288_Y_0_0, - \un1_counter_points_snapshot_i[23]\, - ADD_32x32_fast_I254_Y_1, N626, N611, - ADD_32x32_fast_I254_Y_0, N547, N554, - ADD_32x32_fast_I256_Y_1, N630, N615, - ADD_32x32_fast_I256_Y_0, N558, N551, - ADD_32x32_fast_I300_Y_0_0, - \un1_counter_points_snapshot[11]\, - ADD_32x32_fast_I251_Y_3, ADD_32x32_fast_I251_Y_2, N620, - N481, ADD_32x32_fast_I251_Y_0, N548, - ADD_32x32_fast_I302_Y_0_0, - \un1_counter_points_snapshot[9]\, - ADD_32x32_fast_I301_Y_0_0, - \un1_counter_points_snapshot[10]\, - ADD_32x32_fast_I255_Y_0, N556, N549, - ADD_32x32_fast_I254_un1_Y_3, ADD_32x32_fast_I254_un1_Y_1, - ADD_32x32_fast_I254_un1_Y_0, N420, N423, N512, N504, N500, - ADD_32x32_fast_I294_Y_0_0, - \counter_points_snapshot[14]_net_1\, - ADD_32x32_fast_I293_Y_0_0, - \counter_points_snapshot[13]_net_1\, - ADD_32x32_fast_I252_un1_Y_0, N496, N567, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot_i[12]\, - ADD_32x32_fast_I256_un1_Y_2, ADD_32x32_fast_I256_un1_Y_0, - \un1_counter_points_snapshot_i[21]\, - \un1_counter_points_snapshot[22]\, - ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I289_Y_0_0, ADD_32x32_fast_I255_un1_Y_7, - ADD_32x32_fast_I255_un1_Y_5, ADD_32x32_fast_I255_un1_Y_4, - N613, ADD_32x32_fast_I255_un1_Y_3, N429, N417, - ADD_32x32_fast_I255_un1_Y_1, - \un1_counter_points_snapshot[20]\, N426, - ADD_32x32_fast_I286_Y_0_0, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I290_Y_0_0, ADD_32x32_fast_I284_Y_0_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I263_Y_0, N533, N644, - ADD_32x32_fast_I283_Y_0_0, - \un1_counter_points_snapshot_i[28]\, - ADD_32x32_fast_I161_Y_1, ADD_32x32_fast_I161_Y_0, - ADD_32x32_fast_I126_Y_1, N419, ADD_32x32_fast_I126_Y_0, - N416, ADD_32x32_fast_I134_Y_1, N401, - ADD_32x32_fast_I134_Y_0, ADD_32x32_fast_I118_Y_1, N425, - ADD_32x32_fast_I118_Y_0, N422, N428, - ADD_32x32_fast_I103_Y_1, ADD_32x32_fast_I103_Y_0, - ADD_32x32_fast_I110_Y_0, data_out_valid_9_i_0, - un1_data_in_validlt30_27, un1_data_in_validlt30_18, - un1_data_in_validlt30_17, un1_data_in_validlt30_23, - un1_data_in_validlt30_26, un1_data_in_validlt30_12, - un1_data_in_validlt30_11, un1_data_in_validlt30_22, - un1_data_in_validlt30_25, un1_data_in_validlt30_8, - un1_data_in_validlt30_7, un1_data_in_validlt30_20, - un1_data_in_validlt30_2, un1_data_in_validlt30_1, - un1_data_in_validlt30_15, un1_data_in_validlt30_14, - \counter_points_snapshot[27]_net_1\, - \counter_points_snapshot[26]_net_1\, - un1_data_in_validlt30_10, - \counter_points_snapshot[19]_net_1\, - \counter_points_snapshot[18]_net_1\, - un1_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un1_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[30]_net_1\, - \counter_points_snapshot[28]_net_1\, - \counter_points_snapshot[29]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[22]_net_1\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[20]_net_1\, - \counter_points_snapshot[21]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, N758, N638, N622, - N654, N740, N774, N756, N636, N652, - \un1_data_out_valid_0_sqmuxa_2[7]\, - \un1_counter_points_snapshot[24]\, N650_i, - \un1_data_out_valid_0_sqmuxa_2[6]\, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, N380, N434, N437, N744, - N485, N752, \un1_data_out_valid_0_sqmuxa_2[3]\, N594, - un1_data_in_validlto30_i, N738, N618, N_57, N766, N646, - N754, N634, N762, N642, - \un1_data_out_valid_0_sqmuxa_2[10]\, - \un1_data_out_valid_0_sqmuxa_2[11]\, N783, N492, N572, - N588, N529, N395, N392, N764, N628, I255_un1_Y, - \un1_data_out_valid_0_sqmuxa_2[8]\, N_52, N_60, N_49, - N_47, counter_points_snapshot_0_sqmuxa_1, N750, - I256_un1_Y_i, N789, N746, N742, I208_un1_Y, - ADD_32x32_fast_I252_un1_Y, N607, N777_i, - \un1_data_out_valid_0_sqmuxa_2[9]\, - \un1_data_out_valid_0_sqmuxa_2[4]\, - \un1_data_out_valid_0_sqmuxa_2[5]\, - \un1_counter_points_snapshot[26]\, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_counter_points_snapshot_i[29]\, N748, I214_un1_Y, - ADD_32x32_fast_I97_Y_0_tz, N484, N499, N495, N566, N503, - N511, N515, N_273, counter_points_snapshot_2_sqmuxa, - N_278, N_279, \counter_points_snapshot_10[1]\, - \counter_points_snapshot_10[6]\, - \counter_points_snapshot_10[7]\, N_9, N_25, N_43, N_23, - N760, N_21, N443, N_39, N446, - \counter_points_snapshot_10[3]\, N_275, N_45, N527, N531, - N582, N_17, N_13, N_11, N578, N570, N487, N488, N449, - N_27, N_31, N_19, \counter_points_snapshot_10[11]\, N_283, - \counter_points_snapshot_10[10]\, N_282, N586, N523_i, - N519_i, \un1_counter_points_snapshot[31]\, - \un1_data_out_valid_0_sqmuxa_2[0]\, N_272, - \counter_points_snapshot_10[0]\, N_280, - \counter_points_snapshot_10[8]\, \sample_f1_wdata[32]\, - \sample_f1_wdata[33]\, \sample_f1_wdata[34]\, - \sample_f1_wdata[35]\, \sample_f1_wdata[19]\, - \sample_f1_wdata[20]\, \sample_f1_wdata[21]\, - \sample_f1_wdata[22]\, \sample_f1_wdata[23]\, - \sample_f1_wdata[24]\, \sample_f1_wdata[25]\, - \sample_f1_wdata[26]\, \sample_f1_wdata[27]\, - \sample_f1_wdata[28]\, \sample_f1_wdata[29]\, - \sample_f1_wdata[30]\, \sample_f1_wdata[31]\, - \sample_f1_wdata[43]\, \sample_f1_wdata[44]\, - \sample_f1_wdata[45]\, \sample_f1_wdata[46]\, - \sample_f1_wdata[47]\, \sample_f1_wdata[16]\, - \sample_f1_wdata[17]\, \sample_f1_wdata[18]\, - \sample_f1_wdata[36]\, \sample_f1_wdata[37]\, - \sample_f1_wdata[38]\, \sample_f1_wdata[39]\, - \sample_f1_wdata[40]\, \sample_f1_wdata[41]\, - \sample_f1_wdata[42]\, N_29, N_37, N_33, N_41, N_15, N768, - N_7, N780_i, N_281, \counter_points_snapshot_10[9]\, - N_276, \counter_points_snapshot_10[4]\, N_277, - \counter_points_snapshot_10[5]\, N_35, - \counter_points_snapshot_10[2]\, N_274, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y : OA1 - port map(A => N533, B => N644, C => - ADD_32x32_fast_I255_un1_Y_7, Y => I255_un1_Y); - - \counter_points_snapshot_RNILOM6[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un1_data_in_validlt30_14); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => N_9, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : AX1A - port map(A => N533, B => N529, C => - ADD_32x32_fast_I284_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - \counter_points_snapshot_RNI6U3D[20]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[20]_net_1\, Y => - \un1_counter_points_snapshot[11]\); - - \data_out[110]\ : DFN1C0 - port map(D => \sample_f1_wdata[46]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(110)); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[10]\, B => - I_56_12, S => counter_points_snapshot_2_sqmuxa, Y => - N_282); - - \counter_points_snapshot_RNO[27]\ : XA1B - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - N_52, Y => N_37); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => N_39, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[28]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y_0 : - OR3 - port map(A => N496, B => N500, C => N567, Y => - ADD_32x32_fast_I252_un1_Y_0); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762, B => ADD_32x32_fast_I299_Y_0_0, C => - N_52, Y => N_21); - - \counter_points_snapshot_RNIF38F3[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_0); - - \data_out_RNO[96]\ : MX2 - port map(A => sample_f1_15, B => sample_f1_47, S => - data_shaping_R1_0, Y => \sample_f1_wdata[32]\); - - \data_out[91]\ : DFN1C0 - port map(D => \sample_f1_wdata[27]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(91)); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f1_wdata_56, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1C - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - N_52, Y => N_31); - - \counter_points_snapshot_RNIG2MI[0]\ : NOR3C - port map(A => un1_data_in_validlt30_2, B => - un1_data_in_validlt30_1, C => un1_data_in_validlt30_15, Y - => un1_data_in_validlt30_23); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : AOI1 - port map(A => ADD_32x32_fast_I254_un1_Y_3, B => N783, C => - ADD_32x32_fast_I254_Y_1, Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : NOR2 - port map(A => N586, B => N578, Y => N642); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I101_Y : OR2A - port map(A => N484, B => N488, Y => N547); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f1_wdata_66, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => \sample_f1_wdata[40]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : OR3C - port map(A => N443, B => N446, C => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => I_20_23, B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => N_60, Y => N_276); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[1]\, B => - I_5_31, S => counter_points_snapshot_2_sqmuxa, Y => N_273); - - \counter_points_snapshot_RNIF38F3_2[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47); - - \counter_points_snapshot_RNI9U3D[23]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - \data_out[102]\ : DFN1C0 - port map(D => \sample_f1_wdata[38]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3C - port map(A => I208_un1_Y, B => ADD_32x32_fast_I252_Y_1, C - => ADD_32x32_fast_I252_un1_Y, Y => N742); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_279, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[2]\, B => N_47_0, - Y => ADD_32x32_fast_I309_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_P0N : AOI1B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[15]_net_1\, C => N_47_2, Y => - N426); - - \counter_points_snapshot_RNO[12]\ : XA1C - port map(A => N780_i, B => ADD_32x32_fast_I292_Y_0_0, C => - N_52, Y => N_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : OR2B - port map(A => N650_i, B => N634, Y => N_57); - - \data_out[93]\ : DFN1C0 - port map(D => \sample_f1_wdata[29]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(93)); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[4]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_5 : - NOR3B - port map(A => N423, B => ADD_32x32_fast_I255_un1_Y_3, C => - N429, Y => ADD_32x32_fast_I255_un1_Y_5); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_1 : - AOI1 - port map(A => \un1_counter_points_snapshot_i[21]\, B => - N_47_1, C => N426, Y => ADD_32x32_fast_I255_un1_Y_1); - - \counter_points_snapshot_RNI20DD[10]\ : NOR3A - port map(A => un1_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un1_data_in_validlt30_18); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - N_47_0, Y => ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f1_wdata_95, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => \sample_f1_wdata[41]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(105)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I16_P0N : AOI1B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[16]_net_1\, C => N_47_2, Y => - N429); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f1_wdata_77, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y_2 : - NOR3A - port map(A => ADD_32x32_fast_I256_un1_Y_0, B => N512, C => - N567, Y => ADD_32x32_fast_I256_un1_Y_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR3C - port map(A => N443, B => N446, C => N495, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2A - port map(A => N523_i, B => N527, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => \sample_f1_wdata[17]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(81)); - - counter_points_snapshot_10_12_i_o2 : OR3B - port map(A => enable_f1, B => N_60, C => burst_f1, Y => - N_52); - - \data_out_RNO[99]\ : MX2 - port map(A => sample_f1_12, B => sample_f1_44, S => - data_shaping_R1_0, Y => \sample_f1_wdata[35]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[1]\, B => N_47_0, - Y => ADD_32x32_fast_I310_Y_0_0); - - \data_out_RNO[104]\ : MX2 - port map(A => sample_f1_7, B => sample_f1_39, S => - data_shaping_R1, Y => \sample_f1_wdata[40]\); - - \counter_points_snapshot_RNISS2K[5]\ : MX2 - port map(A => I_24_16, B => - \counter_points_snapshot[5]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[26]\); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : AOI1 - port map(A => N558, B => N551, C => N550, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - NOR2A - port map(A => N425, B => N_57, Y => N768); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f1_wdata_50, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I97_Y : OA1A - port map(A => N_47_2, B => ADD_32x32_fast_I97_Y_0_tz, C => - N484, Y => N543); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : NOR2 - port map(A => N578, B => N570, Y => N634); - - \counter_points_snapshot_RNIBQ3D[18]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : NOR3C - port map(A => N419, B => N422, C => N503, Y => N566); - - \counter_points_snapshot_RNIT045[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un1_data_in_validlt30_2); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => N_37, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f1_wdata_79, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_4 : - NOR3C - port map(A => N420, B => N417, C => - ADD_32x32_fast_I255_un1_Y_1, Y => - ADD_32x32_fast_I255_un1_Y_4); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : OR3 - port map(A => N527, B => N531, C => N533, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3A - port map(A => ADD_32x32_fast_I110_Y_0, B => N434, C => N437, - Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f1_wdata_48, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f1_wdata_60, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(124)); - - \counter_points_snapshot_RNIJSFH[3]\ : MX2C - port map(A => I_13_35, B => - \counter_points_snapshot[3]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot_i[28]\); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f1_wdata_70, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : OA1B - port map(A => N_47, B => \un1_counter_points_snapshot[25]\, - C => N395, Y => N523_i); - - \counter_points_snapshot_RNO[28]\ : XA1C - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - N_52, Y => N_39); - - \data_out[83]\ : DFN1C0 - port map(D => \sample_f1_wdata[19]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : NOR3A - port map(A => ADD_32x32_fast_I250_Y_0, B => N479, C => N546, - Y => ADD_32x32_fast_I250_Y_2); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f1_wdata_58, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f1_wdata_51, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(115)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : OA1B - port map(A => N_47_2, B => \un1_counter_points_snapshot[7]\, - C => N449, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : - AO1A - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot_i[5]\, C => N_47_2, Y => - N481); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : NOR2B - port map(A => N422, B => N428, Y => ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f1_wdata_68, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(132)); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => N_43, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[30]_net_1\); - - \counter_points_snapshot_RNI5155[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un1_data_in_validlt30_4); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I69_Y : AO1B - port map(A => \un1_counter_points_snapshot[20]\, B => N_47, - C => N417, Y => N512); - - \data_out[96]\ : DFN1C0 - port map(D => \sample_f1_wdata[32]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(96)); - - \counter_points_snapshot_RNI69QQ[14]\ : NOR3C - port map(A => un1_data_in_validlt30_8, B => - un1_data_in_validlt30_7, C => un1_data_in_validlt30_20, Y - => un1_data_in_validlt30_25); - - \counter_points_snapshot_RNIDCJD[0]\ : MX2A - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : NOR3 - port map(A => I214_un1_Y, B => ADD_32x32_fast_I255_Y_0, C - => I255_un1_Y, Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[14]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f1_wdata_61, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(125)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f1_wdata_71, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(135)); - - \data_out_RNO[87]\ : NOR2B - port map(A => sample_f1_56, B => data_shaping_R1_0, Y => - \sample_f1_wdata[23]\); - - \data_out_RNO[108]\ : MX2 - port map(A => sample_f1_3, B => sample_f1_35, S => - data_shaping_R1, Y => \sample_f1_wdata[44]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I15_G0N : OR3B - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47_2, Y => - N425); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0_0 : - XOR2 - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[21]\, Y => - ADD_32x32_fast_I290_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : OR3C - port map(A => N481, B => N485, C => N752, Y => N744); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y_1 : - NOR3B - port map(A => N420, B => N423, C => N512, Y => - ADD_32x32_fast_I254_un1_Y_1); - - \counter_points_snapshot_RNIBHF53[31]\ : AO1D - port map(A => un1_data_in_validlto30_i, B => - \counter_points_snapshot[31]_net_1\, C => - start_snapshot_f1, Y => N_59); - - \counter_points_snapshot_RNI924D[30]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[30]_net_1\, Y => - \un1_counter_points_snapshot[1]\); - - data_out_valid : DFN1C0 - port map(D => N_49, CLK => lclk_c, CLR => rstn, Q => - data_f1_out_valid); - - \data_out_RNO[90]\ : NOR2B - port map(A => sample_f1_53, B => data_shaping_R1_0, Y => - \sample_f1_wdata[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : NOR3B - port map(A => N499, B => N503, C => N570, Y => N626); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f1_wdata_7, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f1_wdata_1, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => N_19, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : OR3A - port map(A => N638, B => N622, C => N654, Y => N758); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I45_Y : OA1 - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[8]\, C => N_47, Y => N488); - - \data_out_RNO[98]\ : MX2 - port map(A => sample_f1_13, B => sample_f1_45, S => - data_shaping_R1_0, Y => \sample_f1_wdata[34]\); - - \data_out[86]\ : DFN1C0 - port map(D => \sample_f1_wdata[22]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot_i[23]\, B => - N_47_0, Y => ADD_32x32_fast_I288_Y_0_0); - - \counter_points_snapshot_RNIF38F3_1[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : NOR3B - port map(A => N499, B => N503, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f1_wdata_86, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(150)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_0, Y => ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[16]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f1_wdata_84, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(148)); - - GND_i : GND - port map(Y => \GND\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I49_Y : OA1A - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_counter_points_snapshot[10]\, C => N_47_2, Y => N492); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_7 : - NOR3C - port map(A => ADD_32x32_fast_I255_un1_Y_5, B => - ADD_32x32_fast_I255_un1_Y_4, C => N613, Y => - ADD_32x32_fast_I255_un1_Y_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_G0N : OR3B - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47_2, Y => - N419); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[8]_net_1\); - - \counter_points_snapshot_RNIQGE8[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[30]_net_1\, Y => - un1_data_in_validlt30_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I61_Y : NOR2 - port map(A => N429, B => N426, Y => N504); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : OR3C - port map(A => N511, B => N515, C => N566, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR2B - port map(A => N523_i, B => N519_i, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f1_wdata_9, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot_i[28]\, B => - N_47_1, Y => ADD_32x32_fast_I283_Y_0_0); - - \data_out[92]\ : DFN1C0 - port map(D => \sample_f1_wdata[28]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f1_wdata_3, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => \sample_f1_wdata[43]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I14_G0N : OR3B - port map(A => \counter_points_snapshot[14]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47_2, Y => - N422); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OR2 - port map(A => N533, B => N644, Y => ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_278, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : AX1D - port map(A => N533, B => N644, C => - ADD_32x32_fast_I290_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => N_41, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[29]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_3 : NOR2A - port map(A => ADD_32x32_fast_I251_Y_2, B => N620, Y => - ADD_32x32_fast_I251_Y_3); - - \counter_points_snapshot_RNIS1RQ[22]\ : NOR3C - port map(A => un1_data_in_validlt30_12, B => - un1_data_in_validlt30_11, C => un1_data_in_validlt30_22, - Y => un1_data_in_validlt30_26); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I161_Y_1 : AO1C - port map(A => \un1_counter_points_snapshot[10]\, B => - \un1_counter_points_snapshot[11]\, C => N_47_1, Y => - ADD_32x32_fast_I161_Y_1); - - \data_out_RNO[94]\ : NOR2B - port map(A => sample_f1_49, B => data_shaping_R1_0, Y => - \sample_f1_wdata[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[11]\, B => - N_47_0, Y => ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1C - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - N_52, Y => N_33); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => N_23, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[9]\, B => N_47_0, - Y => ADD_32x32_fast_I302_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y_0 : - AO1C - port map(A => \un1_counter_points_snapshot_i[21]\, B => - \un1_counter_points_snapshot[22]\, C => N_47_0, Y => - ADD_32x32_fast_I256_un1_Y_0); - - \data_out_RNO[95]\ : NOR2B - port map(A => sample_f1_48, B => data_shaping_R1, Y => - \sample_f1_wdata[31]\); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => N_17, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : OR3 - port map(A => N527, B => N531, C => N582, Y => N646); - - \counter_points_snapshot_RNIM4UQ[10]\ : MX2C - port map(A => I_56_12, B => - \counter_points_snapshot[10]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot_i[21]\); - - \counter_points_snapshot_RNI9TLM[7]\ : MX2C - port map(A => I_38_12, B => - \counter_points_snapshot[7]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : OA1C - port map(A => \un1_counter_points_snapshot_i[29]\, B => - \un1_counter_points_snapshot[30]\, C => N_47, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[12]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : OR3B - port map(A => N618, B => ADD_32x32_fast_I250_Y_2, C => N_57, - Y => N738); - - \data_out_RNO[93]\ : NOR2B - port map(A => sample_f1_50, B => data_shaping_R1_0, Y => - \sample_f1_wdata[29]\); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f1_wdata_90, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(154)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - OR3A - port map(A => N764, B => N434, C => N437, Y => N760); - - \data_out[82]\ : DFN1C0 - port map(D => \sample_f1_wdata[18]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f1_wdata_53, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1C - port map(A => N760, B => ADD_32x32_fast_I300_Y_0_0, C => - N_52, Y => N_23); - - \counter_points_snapshot_RNIQV103[6]\ : NOR3C - port map(A => un1_data_in_validlt30_26, B => - un1_data_in_validlt30_25, C => un1_data_in_validlt30_27, - Y => un1_data_in_validlto30_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : AO1A - port map(A => N547, B => N554, C => N546, Y => - ADD_32x32_fast_I254_Y_0); - - \counter_points_snapshot_RNI7GM6[14]\ : NOR2 - port map(A => \counter_points_snapshot[14]_net_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - un1_data_in_validlt30_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I41_Y : AO1C - port map(A => \un1_counter_points_snapshot_i[5]\, B => - \un1_counter_points_snapshot[6]\, C => N_47_2, Y => N484); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f1_wdata_12, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f1_wdata_88, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(152)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_1 : OA1A - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_1, C => N425, Y => ADD_32x32_fast_I118_Y_1); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f1_wdata_85, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(149)); - - \counter_points_snapshot_RNI3GM6[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un1_data_in_validlt30_6); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f1_wdata_63, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : NOR2A - port map(A => N638, B => N654, Y => N777_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : NOR2 - port map(A => N652, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2 - port map(A => N588, B => N533, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f1_wdata_73, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(137)); - - \data_out_RNO[81]\ : NOR2B - port map(A => sample_f1_62, B => data_shaping_R1, Y => - \sample_f1_wdata[17]\); - - \counter_points_snapshot_RNIDOM6[24]\ : NOR2 - port map(A => \counter_points_snapshot[24]_net_1\, B => - \counter_points_snapshot[25]_net_1\, Y => - un1_data_in_validlt30_12); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f1_wdata_91, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(155)); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_277, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1B - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - N_52, Y => N_17); - - data_out_valid_RNO_0 : NOR2B - port map(A => enable_f1, B => sample_f1_val_0, Y => - data_out_valid_9_i_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I121_Y : OR3C - port map(A => N420, B => N423, C => N504, Y => N567); - - \data_out[90]\ : DFN1C0 - port map(D => \sample_f1_wdata[26]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_0 : OA1B - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[21]\, C => N416, Y => - ADD_32x32_fast_I126_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR3C - port map(A => N419, B => N422, C => N511, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR2B - port map(A => ADD_32x32_fast_I251_Y_3, B => N774, Y => N740); - - \counter_points_snapshot_RNO[14]\ : XA1B - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - N_52, Y => N_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR2B - port map(A => N519_i, B => N515, Y => N578); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot_i[29]\, C => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - \data_out_RNO[92]\ : NOR2B - port map(A => sample_f1_51, B => data_shaping_R1_0, Y => - \sample_f1_wdata[28]\); - - counter_points_snapshot_2_sqmuxa_0_a2 : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_60, Y => - counter_points_snapshot_2_sqmuxa); - - \data_out[99]\ : DFN1C0 - port map(D => \sample_f1_wdata[35]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(99)); - - \data_out_RNO[100]\ : MX2 - port map(A => sample_f1_11, B => sample_f1_43, S => - data_shaping_R1, Y => \sample_f1_wdata[36]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I76_Y : OA1B - port map(A => N_47, B => - \un1_counter_points_snapshot_i[23]\, C => N401, Y => - N519_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : OR3C - port map(A => N618, B => N634, C => N650_i, Y => N754); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I12_P0N : AO1B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[12]_net_1\, C => N_47, Y => N417); - - \data_out[106]\ : DFN1C0 - port map(D => \sample_f1_wdata[42]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1B - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - N_52, Y => N_25); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_0 : AO1D - port map(A => \un1_counter_points_snapshot[2]\, B => - \un1_counter_points_snapshot[1]\, C => N_47_0, Y => - ADD_32x32_fast_I250_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y : - OR3C - port map(A => N615, B => ADD_32x32_fast_I256_un1_Y_2, C => - N789, Y => I256_un1_Y_i); - - \data_out_RNO[103]\ : MX2 - port map(A => sample_f1_8, B => sample_f1_40, S => - data_shaping_R1, Y => \sample_f1_wdata[39]\); - - \data_out[98]\ : DFN1C0 - port map(D => \sample_f1_wdata[34]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(98)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y_3 : - NOR3C - port map(A => ADD_32x32_fast_I254_un1_Y_1, B => - ADD_32x32_fast_I254_un1_Y_0, C => N611, Y => - ADD_32x32_fast_I254_un1_Y_3); - - \data_out[80]\ : DFN1C0 - port map(D => \sample_f1_wdata[16]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f1_wdata_8, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : OR2B - port map(A => ADD_32x32_fast_I256_Y_1, B => I256_un1_Y_i, Y - => N750); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_G0N : OR2A - port map(A => \un1_counter_points_snapshot[9]\, B => N_47, - Y => N446); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AO1A - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47_2, Y => N499); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : AX1A - port map(A => N401, B => N650_i, C => - ADD_32x32_fast_I288_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - \data_out_RNO[107]\ : MX2 - port map(A => sample_f1_4, B => sample_f1_36, S => - data_shaping_R1, Y => \sample_f1_wdata[43]\); - - counter_points_snapshot_2_sqmuxa_0_a2_0 : OR2A - port map(A => start_snapshot_f1, B => sample_f1_val_0, Y - => N_60); - - \data_out[89]\ : DFN1C0 - port map(D => \sample_f1_wdata[25]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(89)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : NOR2 - port map(A => ADD_32x32_fast_I263_Y_0, B => N628, Y => N764); - - \counter_points_snapshot_RNICQ3D[19]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot_i[12]\); - - \counter_points_snapshot_RNINCPI[4]\ : MX2C - port map(A => I_20_23, B => - \counter_points_snapshot[4]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[27]\); - - counter_points_snapshot_0_sqmuxa_1_0_a2 : OR3B - port map(A => start_snapshot_f1, B => sample_f1_val_0, C - => burst_f1, Y => counter_points_snapshot_0_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I289_Y_0_0, B => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out_RNO[101]\ : MX2 - port map(A => sample_f1_10, B => sample_f1_42, S => - data_shaping_R1, Y => \sample_f1_wdata[37]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f1_wdata_52, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => N_21, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => I_9_31, B => - \un1_data_out_valid_0_sqmuxa_2[2]\, S => N_60, Y => N_274); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - N_47_1, Y => ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I16_G0N : OR3B - port map(A => \counter_points_snapshot[16]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_2, Y => - N428); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : NOR2 - port map(A => N594, B => N586, Y => N650_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[26]\, C => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1B - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - N_52, Y => N_19); - - \counter_points_snapshot_RNIDU3D[27]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - \data_out[88]\ : DFN1C0 - port map(D => \sample_f1_wdata[24]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XNOR2 - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f1_wdata_62, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => \sample_f1_wdata[30]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f1_wdata_76, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f1_wdata_72, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(136)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I14_P0N : AO1B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[14]_net_1\, C => N_47_2, Y => - N423); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[13]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I293_Y_0_0); - - \un1_data_out_valid_0_sqmuxa_1_i_0[31]\ : AOI1B - port map(A => start_snapshot_f1, B => burst_f1, C => - sample_f1_val_0, Y => - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I208_un1_Y : - OR2A - port map(A => N622, B => N607, Y => I208_un1_Y); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => N_27, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[22]_net_1\); - - \data_out_RNO[86]\ : NOR2B - port map(A => sample_f1_57, B => data_shaping_R1_0, Y => - \sample_f1_wdata[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2A - port map(A => N380, B => N531, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => N_47_0, - Y => ADD_32x32_fast_I304_Y_0_0); - - \data_out[101]\ : DFN1C0 - port map(D => \sample_f1_wdata[37]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(101)); - - \counter_points_snapshot_RNI8U3D[22]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[22]_net_1\, Y => - \un1_counter_points_snapshot[9]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I102_Y : OR3B - port map(A => N446, B => N485, C => N449, Y => N548); - - \counter_points_snapshot_RNI9OM6[22]\ : NOR2 - port map(A => \counter_points_snapshot[22]_net_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - un1_data_in_validlt30_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I13_P0N : AO1B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[13]_net_1\, C => N_47_2, Y => - N420); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I155_Y : OR2B - port map(A => N551, B => N543, Y => N607); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f1_wdata_93, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_276, Y => - \counter_points_snapshot_10[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I163_Y : NOR3A - port map(A => N551, B => N496, C => N500, Y => N615); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot[10]\, C => N_47_1, Y => - ADD_32x32_fast_I110_Y_0); - - \counter_points_snapshot_RNO[30]\ : XA1C - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - N_52, Y => N_43); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[6]_net_1\); - - \counter_points_snapshot_RNIQT8P[9]\ : MX2 - port map(A => I_52_11, B => - \counter_points_snapshot[9]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR3B - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N572, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot_i[23]\, B => - \un1_counter_points_snapshot[25]\, C => N_47_1, Y => - ADD_32x32_fast_I134_Y_0); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f1_wdata_6, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => I_24_16, B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => N_60, Y => N_277); - - \counter_points_snapshot_RNIAU3D[24]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - \data_out[84]\ : DFN1C0 - port map(D => \sample_f1_wdata[20]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => \sample_f1_wdata[39]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I7_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[24]\, B => - N_47_2, Y => N401); - - \counter_points_snapshot_RNIPG35[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un1_data_in_validlt30_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : AOI1 - port map(A => \un1_counter_points_snapshot_i[28]\, B => - \un1_counter_points_snapshot[27]\, C => N_47, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - N_52, Y => N_35); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0_0 : - XOR2 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, Y => - ADD_32x32_fast_I289_Y_0_0); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f1_wdata_15, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(79)); - - \counter_points_snapshot_RNIFU3D[29]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[29]_net_1\, Y => - \un1_counter_points_snapshot[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \counter_points_snapshot_RNIAQ3D[17]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f1_wdata_80, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(144)); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0 : OR3B - port map(A => start_snapshot_f1, B => sample_f1_val_0, C - => burst_f1, Y => counter_points_snapshot_0_sqmuxa_1_0); - - \data_out_RNO[89]\ : NOR2B - port map(A => sample_f1_54, B => data_shaping_R1_0, Y => - \sample_f1_wdata[25]\); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_280, Y => - \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => \sample_f1_wdata[47]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I105_Y : NOR2 - port map(A => N492, B => N488, Y => N551); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - AX1C - port map(A => \counter_points_snapshot[15]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2A - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f1_wdata_78, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f1_wdata_14, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - N_52, Y => N_29); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : OR3 - port map(A => ADD_32x32_fast_I134_Y_0, B => - ADD_32x32_fast_I134_Y_1, C => N572, Y => N636); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_1 : AO1A - port map(A => N_47_1, B => - \un1_counter_points_snapshot[22]\, C => N401, Y => - ADD_32x32_fast_I134_Y_1); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => I_13_35, B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => N_60, Y => N_275); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => N_35, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => N_47_0, - Y => ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : AOI1B - port map(A => N550, B => N543, C => ADD_32x32_fast_I252_Y_0, - Y => ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y_1 : AO1B - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_counter_points_snapshot[6]\, C => N_47_1, Y => - ADD_32x32_fast_I103_Y_1); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f1_wdata_57, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : NOR2B - port map(A => N428, B => N425, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_272, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f1_wdata_67, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f1_wdata_49, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(113)); - - \counter_points_snapshot_RNIF38F3_0[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_1); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f1_wdata_81, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(145)); - - \counter_points_snapshot_RNIOKCA1[6]\ : NOR3C - port map(A => un1_data_in_validlt30_18, B => - un1_data_in_validlt30_17, C => un1_data_in_validlt30_23, - Y => un1_data_in_validlt30_27); - - \counter_points_snapshot_RNI6HDD[26]\ : NOR3A - port map(A => un1_data_in_validlt30_14, B => - \counter_points_snapshot[27]_net_1\, C => - \counter_points_snapshot[26]_net_1\, Y => - un1_data_in_validlt30_22); - - \counter_points_snapshot_RNIBGM6[17]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un1_data_in_validlt30_8); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f1_wdata_2, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[1]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_1 : AO1A - port map(A => N626, B => N611, C => ADD_32x32_fast_I254_Y_0, - Y => ADD_32x32_fast_I254_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y_0 : OAI1 - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => N_47_1, Y => - ADD_32x32_fast_I103_Y_0); - - \counter_points_snapshot_RNO[31]\ : XA1B - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - N_52, Y => N_45); - - \data_out_RNO[109]\ : MX2 - port map(A => sample_f1_2, B => sample_f1_34, S => - data_shaping_R1, Y => \sample_f1_wdata[45]\); - - \counter_points_snapshot_RNO_0[0]\ : MX2B - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => N_60, Y => N_272); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N_57, B => ADD_32x32_fast_I295_Y_0_0, C => - N_52, Y => N_13); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f1_wdata_59, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(123)); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f1_wdata_69, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : OR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - N_47_2, Y => N443); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I4_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => N_47, - Y => N392); - - \counter_points_snapshot_RNO[29]\ : XA1C - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - N_52, Y => N_41); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => N_45, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : OA1B - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_counter_points_snapshot[4]\, C => N_47_2, Y => N479); - - \data_out_RNO[97]\ : MX2 - port map(A => sample_f1_14, B => sample_f1_46, S => - data_shaping_R1_0, Y => \sample_f1_wdata[33]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_1 : AOI1B - port map(A => N630, B => N615, C => ADD_32x32_fast_I256_Y_0, - Y => ADD_32x32_fast_I256_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I19_G0N : NOR2 - port map(A => \un1_counter_points_snapshot_i[12]\, B => - N_47_2, Y => N437); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f1_wdata_10, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(74)); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_282, Y => - \counter_points_snapshot_10[10]\); - - \data_out[108]\ : DFN1C0 - port map(D => \sample_f1_wdata[44]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[6]\, B => - I_31_15, S => counter_points_snapshot_2_sqmuxa, Y => - N_278); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f1_wdata_92, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(156)); - - \data_out_RNO[106]\ : MX2 - port map(A => sample_f1_5, B => sample_f1_37, S => - data_shaping_R1, Y => \sample_f1_wdata[42]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_3 : - AO1C - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_counter_points_snapshot[14]\, C => N_47_1, Y => - ADD_32x32_fast_I255_un1_Y_3); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[8]\, B => - I_45_11, S => counter_points_snapshot_2_sqmuxa, Y => - N_280); - - \data_out_RNO[80]\ : NOR2B - port map(A => sample_f1_63, B => data_shaping_R1, Y => - \sample_f1_wdata[16]\); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_273, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_0, - Y => ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : AO1A - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot_i[5]\, C => N_47_2, Y => - N483_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - NOR3A - port map(A => N446, B => N449, C => N756, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - N_52, Y => N_27); - - \data_out_RNO[88]\ : NOR2B - port map(A => sample_f1_55, B => data_shaping_R1_0, Y => - \sample_f1_wdata[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y : NOR2B - port map(A => ADD_32x32_fast_I103_Y_1, B => - ADD_32x32_fast_I103_Y_0, Y => N549); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => N_7, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => N_31, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[24]_net_1\); - - \data_out[95]\ : DFN1C0 - port map(D => \sample_f1_wdata[31]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(95)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_0 : NOR2A - port map(A => N483_i, B => N479, Y => - ADD_32x32_fast_I252_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y : OR3 - port map(A => N607, B => ADD_32x32_fast_I252_un1_Y_0, C => - N777_i, Y => ADD_32x32_fast_I252_un1_Y); - - \counter_points_snapshot_RNI7U3D[21]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[21]_net_1\, Y => - \un1_counter_points_snapshot[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR2B - port map(A => ADD_32x32_fast_I126_Y_1, B => - ADD_32x32_fast_I126_Y_0, Y => N572); - - \data_out_RNO[110]\ : MX2 - port map(A => sample_f1_1, B => sample_f1_33, S => - data_shaping_R1, Y => \sample_f1_wdata[46]\); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => I_52_11, B => - \un1_data_out_valid_0_sqmuxa_2[9]\, S => N_60, Y => N_281); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : OA1 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[20]\, C => N419, Y => - ADD_32x32_fast_I126_Y_1); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_275, Y => - \counter_points_snapshot_10[3]\); - - \counter_points_snapshot_RNIGC6G[2]\ : MX2C - port map(A => I_9_31, B => - \counter_points_snapshot[2]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot_i[29]\); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f1_wdata_54, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(118)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I5_G0N : NOR2A - port map(A => \un1_counter_points_snapshot[26]\, B => N_47, - Y => N395); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR2A - port map(A => N380, B => N646, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot_i[5]\, B => - N_47_0, Y => ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2A - port map(A => N642, B => N594, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[24]\, C => N650_i, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I286_Y_0_0, B => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0 : XOR3 - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N783, Y => - \un1_data_out_valid_0_sqmuxa_2[11]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I23_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_2, - Y => N449); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I100_Y : OR2B - port map(A => N487, B => N483_i, Y => N546); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f1_wdata_64, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(128)); - - \counter_points_snapshot_RNO[11]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_283, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => \sample_f1_wdata[33]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f1_wdata_74, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(138)); - - \data_out_RNO[84]\ : NOR2B - port map(A => sample_f1_59, B => data_shaping_R1_0, Y => - \sample_f1_wdata[20]\); - - \counter_points_snapshot_RNIESSE[1]\ : MX2 - port map(A => I_5_31, B => - \counter_points_snapshot[1]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[30]\); - - \data_out[85]\ : DFN1C0 - port map(D => \sample_f1_wdata[21]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[3]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I18_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => N_47, - Y => N434); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I159_Y : NOR3 - port map(A => N496, B => N492, C => N547, Y => N611); - - \data_out_RNO[85]\ : NOR2B - port map(A => sample_f1_58, B => data_shaping_R1_0, Y => - \sample_f1_wdata[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => \sample_f1_wdata[45]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(109)); - - \counter_points_snapshot_RNIK8DD[18]\ : NOR3A - port map(A => un1_data_in_validlt30_10, B => - \counter_points_snapshot[19]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un1_data_in_validlt30_20); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : OA1B - port map(A => N_47, B => \un1_counter_points_snapshot[20]\, - C => N416, Y => N511); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I192_Y : OR3 - port map(A => ADD_32x32_fast_I134_Y_0, B => - ADD_32x32_fast_I134_Y_1, C => N588, Y => N644); - - \data_out_RNO[111]\ : MX2 - port map(A => sample_f1_0, B => sample_f1_32, S => - data_shaping_R1, Y => \sample_f1_wdata[47]\); - - \counter_points_snapshot_RNICU3D[26]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot_i[5]\); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => N_29, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => N_25, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot_RNI6I9A[6]\ : NOR3A - port map(A => un1_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un1_data_in_validlt30_17); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : AO1 - port map(A => N556, B => N549, C => N548, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f1_wdata_83, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(147)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f1_wdata_87, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(151)); - - \data_out_RNO[83]\ : NOR2B - port map(A => sample_f1_60, B => data_shaping_R1_0, Y => - \sample_f1_wdata[19]\); - - \counter_points_snapshot_RNI2DCL[6]\ : MX2C - port map(A => I_31_15, B => - \counter_points_snapshot[6]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[25]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot_i[12]\, B => - N_47_0, Y => ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => N_47_0, - Y => ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => \sample_f1_wdata[23]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(87)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f1_wdata_89, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(153)); - - \counter_points_snapshot_RNIN4UQ[11]\ : MX2C - port map(A => N_4, B => \counter_points_snapshot[11]_net_1\, - S => counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I283_Y_0_0, B => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR3 - port map(A => N636, B => N620, C => N652, Y => N756); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AO1 - port map(A => \un1_counter_points_snapshot_i[29]\, B => - \un1_counter_points_snapshot_i[28]\, C => N_47, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : OR3A - port map(A => N529, B => N395, C => N392, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => N_47_0, - Y => ADD_32x32_fast_I307_Y_0_0); - - \data_out_RNO[91]\ : NOR2B - port map(A => sample_f1_52, B => data_shaping_R1_0, Y => - \sample_f1_wdata[27]\); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f1_wdata_55, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I53_Y : OA1A - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot_i[12]\, C => N_47_2, Y => - N496); - - \data_out_RNO[102]\ : MX2 - port map(A => sample_f1_9, B => sample_f1_41, S => - data_shaping_R1, Y => \sample_f1_wdata[38]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AO1A - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot_i[21]\, C => N_47, Y => N515); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I161_Y : NOR3C - port map(A => ADD_32x32_fast_I161_Y_1, B => - ADD_32x32_fast_I161_Y_0, C => N549, Y => N613); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[7]\, B => - I_38_12, S => counter_points_snapshot_2_sqmuxa, Y => - N_279); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_281, Y => - \counter_points_snapshot_10[9]\); - - \counter_points_snapshot_RNIHDVN[8]\ : MX2C - port map(A => I_45_11, B => - \counter_points_snapshot[8]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot_i[23]\); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f1_wdata_5, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f1_wdata_65, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I112_Y : OR2B - port map(A => N499, B => N495, Y => N558); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1_0, C => N_47_0, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y_0 : - NOR2A - port map(A => N504, B => N500, Y => - ADD_32x32_fast_I254_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : NOR3B - port map(A => N481, B => ADD_32x32_fast_I251_Y_0, C => N548, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f1_wdata_75, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => N_33, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[25]_net_1\); - - \data_out_RNO[82]\ : NOR2B - port map(A => sample_f1_61, B => data_shaping_R1, Y => - \sample_f1_wdata[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I161_Y_0 : OAI1 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot_i[12]\, C => N_47_1, Y => - ADD_32x32_fast_I161_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[20]\, B => N_47, - C => N783, Y => N780_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : AO1C - port map(A => N_47, B => \un1_counter_points_snapshot[30]\, - C => N380, Y => N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : AO1A - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[7]\, C => N_47, Y => N485); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f1_wdata_11, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(75)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I97_Y_0_tz : - NOR2B - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[3]\, Y => - ADD_32x32_fast_I97_Y_0_tz); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => - N_47_1, Y => ADD_32x32_fast_I284_Y_0_0); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f1_wdata_4, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(68)); - - \counter_points_snapshot_RNO_0[11]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[11]\, B => N_4, - S => counter_points_snapshot_2_sqmuxa, Y => N_283); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_0 : AO1D - port map(A => \un1_counter_points_snapshot[2]\, B => - \un1_counter_points_snapshot[3]\, C => N_47_0, Y => - ADD_32x32_fast_I251_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I12_G0N : NOR3B - port map(A => \counter_points_snapshot[12]_net_1\, B => - counter_points_snapshot_0_sqmuxa_1, C => N_47, Y => N416); - - \counter_points_snapshot_RNIEU3D[28]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : OA1C - port map(A => \un1_counter_points_snapshot[11]\, B => - N_47_2, C => N437, Y => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OR3B - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N556, Y => N620); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : NOR3A - port map(A => N380, B => N646, C => N630, Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768, B => ADD_32x32_fast_I296_Y_0_0, C => - N_52, Y => N_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I57_Y : OA1A - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47_2, Y => N500); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : OR2A - port map(A => N566, B => N558, Y => N622); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I214_un1_Y : - NOR2B - port map(A => N628, B => N613, Y => I214_un1_Y); - - \counter_points_snapshot_RNI5OM6[20]\ : NOR2 - port map(A => \counter_points_snapshot[20]_net_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - un1_data_in_validlt30_10); - - data_out_valid_RNO : OA1 - port map(A => burst_f1, B => N_59, C => - data_out_valid_9_i_0, Y => N_49); - - \data_out[100]\ : DFN1C0 - port map(D => \sample_f1_wdata[36]\, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : OR3B - port map(A => N642, B => N626, C => N594, Y => N762); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f1_wdata_13, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f1_wdata_82, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f1, B => burst_f1, C => N_274, Y => - \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : NOR3B - port map(A => N511, B => N515, C => N582, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1B - port map(A => N777_i, B => ADD_32x32_fast_I293_Y_0_0, C => - N_52, Y => N_9); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f1_wdata_94, CLK => lclk_c, CLR => - rstn, Q => data_f1_out(158)); - - \data_out_RNO[105]\ : MX2 - port map(A => sample_f1_6, B => sample_f1_38, S => - data_shaping_R1, Y => \sample_f1_wdata[41]\); - - \counter_points_snapshot_RNIBU3D[25]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f1_wdata_0, CLK => lclk_c, CLR => rstn, - Q => data_f1_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[25]\, B => - N_47_1, Y => ADD_32x32_fast_I286_Y_0_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_controler is - - port( coarse_time_i : in std_logic_vector(0 to 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - coarse_time : in std_logic_vector(0 to 0); - start_snapshot_f2 : out std_logic; - start_snapshot_f1 : out std_logic; - start_snapshot_f0 : out std_logic; - sample_f2_val : in std_logic; - sample_f0_val_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_waveform_snapshot_controler; - -architecture DEF_ARCH of lpp_waveform_snapshot_controler is - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \counter_delta_snapshot_0[26]_net_1\, - counter_delta_snapshot_e26, N_9_0, - counter_delta_f0lde_i_a2_0_1_i, N_57_0, - start_snapshot_f22, \start_snapshot_fothers_temp\, - un2_coarse_time_0_0, coarse_time_0_r_i, N_504_0, N_406, - N_406_0, \counter_delta_snapshot[25]_net_1\, N_405, - start_snapshot_f12, N_322, start_snapshot_f12_0_a2_8, - un1_start_snapshot_f22_i_a2_0_4, - un1_start_snapshot_f22_i_a2_0_5, - start_snapshot_f12_0_a2_7, start_snapshot_f12_0_a2_6, - counter_delta_snapshot_e9_i_0, - \counter_delta_snapshot[9]_net_1\, N_469, - counter_delta_snapshot_e6_i_0, - \counter_delta_snapshot[6]_net_1\, N_455, - counter_delta_snapshot_e2_i_0, - \counter_delta_snapshot[2]_net_1\, N_239, - counter_delta_snapshot_e3_i_0, - \counter_delta_snapshot[3]_net_1\, N_440, - counter_delta_snapshot_e7_i_0, - \counter_delta_snapshot[7]_net_1\, N_460, - counter_delta_snapshot_e8_i_0, - \counter_delta_snapshot[8]_net_1\, N_465, - counter_delta_snapshot_e4_i_0, - \counter_delta_snapshot[4]_net_1\, N_445, - counter_delta_snapshot_e5_i_0, - \counter_delta_snapshot_i[5]\, N_450, - counter_delta_snapshot_e15_i_0_0, - \counter_delta_snapshot_i[15]\, N_478, - counter_delta_snapshot_e14_i_0_0, - \counter_delta_snapshot[14]_net_1\, N_484, - counter_delta_snapshot_e13_i_0_0, - \counter_delta_snapshot[13]_net_1\, N_285, - counter_delta_snapshot_e12_i_0_0, - \counter_delta_snapshot[12]_net_1\, N_493, - counter_delta_snapshot_e11_i_0_0, - \counter_delta_snapshot_i[11]\, N_499, - counter_delta_snapshot_e21_0_0_0, - \counter_delta_snapshot[21]_net_1\, N_183, - counter_delta_snapshot_e10_i_0, - \counter_delta_snapshot[10]_net_1\, un2_coarse_time_0, - N_474, counter_delta_snapshot_e24_0_0_0, - \counter_delta_snapshot[24]_net_1\, N_192, - counter_delta_snapshot_e0_i_0, N_505, N_429, - counter_delta_snapshot_e23_0_0_0, - \counter_delta_snapshot[23]_net_1\, N_189, - counter_delta_snapshot_e19_i_i_0, - \counter_delta_snapshot[19]_net_1\, N_177, - counter_delta_snapshot_e17_i_i_0, - \counter_delta_snapshot[17]_net_1\, N_171, - counter_delta_snapshot_e9_i_a2_0, N_389, - counter_delta_snapshot_e6_i_a2_0, N_386, - counter_delta_snapshot_e2_i_a2_0, N_382, - counter_delta_snapshot_e3_i_a2_0, N_383, - counter_delta_snapshot_e7_i_a2_0, N_387, - counter_delta_snapshot_e8_i_a2_0, N_388, - counter_delta_snapshot_e10_i_a2_0, N_390, - counter_delta_snapshot_e24_0_0_a2_0, N_404, - counter_delta_snapshot_e16_i_i_a2_0, - \counter_delta_snapshot[16]_net_1\, N_396, - counter_delta_snapshot_e17_i_i_a2_0, - counter_delta_snapshot_e18_i_i_a2_0, - \counter_delta_snapshot[18]_net_1\, N_398, - counter_delta_snapshot_e19_i_i_a2_0, - counter_delta_snapshot_e20_i_i_a2_0, - \counter_delta_snapshot[20]_net_1\, N_400, - counter_delta_snapshot_e21_0_0_a2_0, - counter_delta_snapshot_e22_0_0_a2_0, - \counter_delta_snapshot[22]_net_1\, N_402, - counter_delta_snapshot_e23_0_0_a2_0, - counter_delta_snapshot_e4_i_a2_0, N_384, - counter_delta_snapshot_e5_i_a2_0, N_385, - counter_delta_snapshot_e15_i_0_a2_0, N_395, - counter_delta_snapshot_e14_i_0_a2_0, N_394, - counter_delta_snapshot_e13_i_0_a2_0, N_393, - counter_delta_snapshot_e12_i_0_a2_0, - \counter_delta_snapshot_RNI01E2[7]_net_1\, - counter_delta_snapshot_e11_i_0_a2_0, N_391, - counter_delta_f0lde_i_a2_0_1_3, - counter_delta_f0lde_i_a2_0_1_2, N_89, - \counter_delta_f0[3]_net_1\, N_273, - counter_delta_f0_1_0_a2_2_0, counter_delta_f0_1_0_a2_7, - N_108_i_i_0, N_84_i_i_0, start_snapshot_f12_0_a2_5, - N_83_i_i_0, N_274_i_0, start_snapshot_f12_0_a2_2, - N_82_i_i_0, N_81_i_i_0, start_snapshot_f12_0_a2_1, - \counter_delta_f0[4]_net_1\, N_113_i_i_0, - \counter_delta_f0[1]_net_1\, N_111_i_i_0, - start_snapshot_f22_0_a2_1, - start_snapshot_f22_0_a2_11_0_a2_4, - start_snapshot_f22_0_a2_11_0_a2_5, - start_snapshot_f22_0_a2_0, \start_snapshot_f2_temp\, - start_snapshot_f22_10, start_snapshot_f2_temp3_0_a2_0, - counter_delta_snapshot_e12_i_0_o2_m6_e_6, - counter_delta_snapshot_e12_i_0_o2_m6_e_4, - counter_delta_snapshot_e12_i_0_o2_m6_e_5, - counter_delta_snapshot_e12_i_0_o2_m6_e_2, - un12_start_snapshot_fothers_temp_NE_13, - un12_start_snapshot_fothers_temp_NE_5, - un12_start_snapshot_fothers_temp_NE_4, - un12_start_snapshot_fothers_temp_NE_11, - un12_start_snapshot_fothers_temp_NE_12, - un12_start_snapshot_fothers_temp_NE_1, - un12_start_snapshot_fothers_temp_NE_0, - un12_start_snapshot_fothers_temp_NE_9, N_506_i, N_166_i_i, - un12_start_snapshot_fothers_temp_NE_7, N_507_i, N_137_i_i, - un12_start_snapshot_fothers_temp_NE_3, N_509_i, N_164_i_i, - N_510_i, \counter_delta_snapshot_RNIFJ31[15]_net_1\, - N_136_i_i, N_133_i_i, counter_delta_f0_1_0_a2_12, - counter_delta_f0_1_0_a2_3, counter_delta_f0_1_0_a2_8, - counter_delta_f0_1_8, counter_delta_f0_1_0_a2_11, - counter_delta_f0_1_0_a2_6, counter_delta_f0_1_0_a2_5, - counter_delta_f0_1_0_a2_10, counter_delta_f0_1_0_a2_5_0, - counter_delta_f0_1_0_a2_0, N_272, - \counter_delta_f0[0]_net_1\, \counter_delta_f0[2]_net_1\, - \counter_delta_f0[21]_net_1\, - \counter_delta_f0[25]_net_1\, counter_delta_f0_1_0_a2_2, - \counter_delta_f0[14]_net_1\, - \counter_delta_f0[15]_net_1\, - \counter_delta_f0[20]_net_1\, \counter_delta_f0[8]_net_1\, - \counter_delta_f0[9]_net_1\, - start_snapshot_f22_0_a2_11_0_a2_3, - start_snapshot_f22_0_a2_11_0_a2_1, - counter_delta_f0_1_0_a2_8_0, \counter_delta_f0[16]_net_1\, - \counter_delta_f0[17]_net_1\, - \counter_delta_snapshot_RNO[16]_net_1\, N_168, N_169, - N_170, \counter_delta_snapshot_RNO[17]_net_1\, - \counter_delta_snapshot_RNO[18]_net_1\, N_174, N_175, - N_176, N_20, \counter_delta_snapshot_RNO[20]_net_1\, - N_180, N_181, N_182, counter_delta_snapshot_e21, - counter_delta_snapshot_e22, N_186, N_187, N_188, - counter_delta_snapshot_e23, counter_delta_snapshot_e25, - N_421, N_422, N_423, N_19, N_65, - \counter_delta_f0[10]_net_1\, N_275, N_67, - \counter_delta_f0[11]_net_1\, N_34, N_80, - \counter_delta_f0[26]_net_1\, start_snapshot_f2_temp3, - \counter_delta_f0[19]_net_1\, - \counter_delta_f0[18]_net_1\, counter_delta_f0_1, - N_22_i_0, N_501, N_503, N_195_i_0, N_496, N_498, N_26_i_0, - N_287, N_288, N_6_i_0, N_486, N_488, N_8_i_0, N_480, - N_482, \counter_delta_snapshot_RNO[10]_net_1\, N_476, - N_477, \counter_delta_snapshot_RNO[8]_net_1\, N_467, - N_468, \counter_delta_snapshot_RNO[7]_net_1\, N_462, - N_463, N_376_i_0, N_452, N_453, N_375_i_0, N_447, N_448, - \counter_delta_snapshot_RNO[3]_net_1\, N_442, N_443, N_54, - N_437, N_438, \counter_delta_snapshot_RNO[1]_net_1\, - N_433, counter_delta_snapshot_e1_i_0, N_435, - \counter_delta_snapshot_RNO[0]_net_1\, - \counter_delta_snapshot[0]_net_1\, N_472, N_504, - \counter_delta_snapshot[1]_net_1\, - \counter_delta_snapshot[26]_net_1\, N_458, - \counter_delta_snapshot_RNO[6]_net_1\, N_457, - \counter_delta_snapshot_RNO[9]_net_1\, N_471, - counter_delta_snapshot_e24, \counter_delta_f0[7]_net_1\, - \counter_delta_f0[6]_net_1\, \counter_delta_f0[23]_net_1\, - \counter_delta_f0[22]_net_1\, - \counter_delta_f0[24]_net_1\, N_284, N_9, - \counter_delta_f0[13]_net_1\, - \counter_delta_f0[12]_net_1\, \counter_delta_f0[5]_net_1\, - N_21, N_23, N_107_i_i, N_227, N_114_i_i, N_228, N_115_i_i, - N_229, N_116_i_i, N_230, N_117_i_i, counter_delta_f0_n12, - N_98, counter_delta_f0_n13, N_99, counter_delta_f0_n14, - N_100, counter_delta_f0_n15, N_101, counter_delta_f0_n16, - N_102, N_57, counter_delta_f0_n17, N_103, - counter_delta_f0_n18, N_104, counter_delta_f0_n19, N_105, - counter_delta_f0_n20, N_106, N_55, N_13, N_89_i_i, N_15, - N_99_i_i, N_17, N_324_i, N_276, N_58, N_277, N_60, N_28, - N_62, N_30, N_64, N_32, N_66, N_59, N_63, N_87_i_i, N_11, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter_delta_snapshot_RNO_1[11]\ : AOI1B - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot_i[11]\, C => N_499, Y => - counter_delta_snapshot_e11_i_0_0); - - \counter_delta_snapshot_RNO[21]\ : OAI1 - port map(A => N_402, B => N_504_0, C => - counter_delta_snapshot_e21_0_0_0, Y => - counter_delta_snapshot_e21); - - \counter_delta_snapshot[19]\ : DFN1C0 - port map(D => N_20, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[19]_net_1\); - - start_snapshot_f0_RNO_1 : NOR3A - port map(A => counter_delta_f0_1_0_a2_5_0, B => - counter_delta_f0_1_0_a2_0, C => N_272, Y => - counter_delta_f0_1_0_a2_10); - - \counter_delta_f0_RNO[14]\ : XA1A - port map(A => \counter_delta_f0[14]_net_1\, B => N_100, C - => N_57_0, Y => counter_delta_f0_n14); - - \counter_delta_snapshot_RNO_0[17]\ : AOI1B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[17]_net_1\, C => N_171, Y => - counter_delta_snapshot_e17_i_i_0); - - \counter_delta_f0_RNI3797[16]\ : NOR2 - port map(A => \counter_delta_f0[16]_net_1\, B => - \counter_delta_f0[17]_net_1\, Y => - counter_delta_f0_1_0_a2_8_0); - - start_snapshot_fothers_temp_RNISVED5_0 : AOI1B - port map(A => sample_f0_val_0, B => - counter_delta_f0lde_i_a2_0_1_i, C => N_57_0, Y => N_9); - - \op_eq.start_snapshot_f12_0_a2_RNO_2\ : XNOR2 - port map(A => \counter_delta_f0[0]_net_1\, B => - delta_f2_f1(0), Y => N_108_i_i_0); - - \counter_delta_f0_RNIBN261[4]\ : NOR3B - port map(A => N_273, B => counter_delta_f0_1_0_a2_2_0, C - => counter_delta_f0_1_0_a2_7, Y => - counter_delta_f0lde_i_a2_0_1_2); - - \counter_delta_snapshot_RNO[19]\ : OAI1 - port map(A => N_400, B => N_504_0, C => - counter_delta_snapshot_e19_i_i_0, Y => N_20); - - un1_start_snapshot_f22_i_a2_0 : AND2 - port map(A => un1_start_snapshot_f22_i_a2_0_4, B => - un1_start_snapshot_f22_i_a2_0_5, Y => N_322); - - \counter_delta_snapshot_RNO_1[2]\ : AO1A - port map(A => \counter_delta_snapshot[2]_net_1\, B => - un2_coarse_time_0_0, C => N_239, Y => - counter_delta_snapshot_e2_i_0); - - \counter_delta_snapshot_RNIA82J_1[26]\ : AO1A - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => un2_coarse_time_0, Y => N_504); - - \counter_delta_f0_RNO[11]\ : XA1A - port map(A => N_67, B => \counter_delta_f0[11]_net_1\, C - => N_57_0, Y => N_275); - - \counter_delta_f0_RNO_0[4]\ : AX1B - port map(A => N_89, B => \counter_delta_f0[3]_net_1\, C => - \counter_delta_f0[4]_net_1\, Y => N_116_i_i); - - \counter_delta_snapshot_RNO_1[12]\ : OA1A - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[12]_net_1\, C => N_493, Y => - counter_delta_snapshot_e12_i_0_0); - - \counter_delta_f0_RNI2NDI3[23]\ : OR2 - port map(A => \counter_delta_f0[23]_net_1\, B => N_62, Y - => N_64); - - start_snapshot_f2_temp_RNO : NOR3B - port map(A => un12_start_snapshot_fothers_temp_NE_12, B => - un12_start_snapshot_fothers_temp_NE_13, C => - start_snapshot_f2_temp3_0_a2_0, Y => - start_snapshot_f2_temp3); - - \counter_delta_f0_RNO[26]\ : XA1 - port map(A => N_80, B => \counter_delta_f0[26]_net_1\, C - => N_57_0, Y => N_34); - - \counter_delta_snapshot_RNI0R62[10]\ : OR2 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - N_390, Y => N_391); - - \counter_delta_snapshot_RNI01E2[7]\ : OR3B - port map(A => counter_delta_snapshot_e12_i_0_o2_m6_e_6, B - => counter_delta_snapshot_e12_i_0_o2_m6_e_5, C => N_383, - Y => \counter_delta_snapshot_RNI01E2[7]_net_1\); - - \counter_delta_snapshot_RNO_1[19]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e19_i_i_a2_0, Y => - N_177); - - \counter_delta_f0_RNITNMC[8]\ : NOR2 - port map(A => \counter_delta_f0[8]_net_1\, B => - \counter_delta_f0[9]_net_1\, Y => - counter_delta_f0_1_0_a2_2_0); - - \counter_delta_snapshot_RNO[5]\ : OR3C - port map(A => N_452, B => counter_delta_snapshot_e5_i_0, C - => N_453, Y => N_376_i_0); - - \counter_delta_snapshot[16]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[16]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[16]_net_1\); - - \counter_delta_snapshot_RNO_0[20]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e20_i_i_a2_0, Y => - N_180); - - \counter_delta_snapshot_RNO_1[16]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[16]_net_1\, Y => N_169); - - \counter_delta_snapshot_RNO_0[10]\ : NOR2 - port map(A => N_505, B => delta_snapshot(10), Y => N_476); - - \counter_delta_snapshot_RNI5J31[10]\ : XNOR2 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - delta_snapshot(10), Y => N_510_i); - - \counter_delta_snapshot_RNI3T11[7]\ : NOR3A - port map(A => counter_delta_snapshot_e12_i_0_o2_m6_e_4, B - => \counter_delta_snapshot[8]_net_1\, C => - \counter_delta_snapshot[7]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_6); - - \counter_delta_snapshot_0_RNI70LQ[26]\ : AO1A - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406, C => un2_coarse_time_0_0, Y => N_504_0); - - \counter_delta_snapshot[25]\ : DFN1C0 - port map(D => counter_delta_snapshot_e25, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[25]_net_1\); - - \counter_delta_f0_RNO[7]\ : MX2 - port map(A => delta_f2_f0(7), B => N_89_i_i, S => N_57, Y - => N_13); - - \counter_delta_snapshot_RNO_2[13]\ : OR3A - port map(A => \counter_delta_snapshot[13]_net_1\, B => - N_393, C => N_504_0, Y => N_288); - - \counter_delta_snapshot_RNO_3[5]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e5_i_a2_0, Y => - N_450); - - \counter_delta_snapshot[14]\ : DFN1C0 - port map(D => N_6_i_0, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[14]_net_1\); - - \counter_delta_snapshot_RNO_1[17]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e17_i_i_a2_0, Y => - N_171); - - \counter_delta_f0_RNI3UIE[21]\ : NOR3 - port map(A => \counter_delta_f0[21]_net_1\, B => - \counter_delta_f0[25]_net_1\, C => - counter_delta_f0_1_0_a2_2, Y => - counter_delta_f0_1_0_a2_5_0); - - \counter_delta_f0[14]\ : DFN1E0C0 - port map(D => counter_delta_f0_n14, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[14]_net_1\); - - \counter_delta_snapshot_RNO_0[2]\ : NOR2 - port map(A => N_505, B => delta_snapshot(2), Y => N_437); - - \counter_delta_snapshot_RNIQOS[17]\ : NOR3A - port map(A => start_snapshot_f22_0_a2_11_0_a2_1, B => - \counter_delta_snapshot[17]_net_1\, C => - \counter_delta_snapshot[16]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_4); - - \counter_delta_f0_RNO[18]\ : XA1A - port map(A => \counter_delta_f0[18]_net_1\, B => N_104, C - => N_57, Y => counter_delta_f0_n18); - - \counter_delta_snapshot_RNO[17]\ : OAI1 - port map(A => N_398, B => N_504_0, C => - counter_delta_snapshot_e17_i_i_0, Y => - \counter_delta_snapshot_RNO[17]_net_1\); - - \counter_delta_snapshot[2]\ : DFN1C0 - port map(D => N_54, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[2]_net_1\); - - \counter_delta_f0_RNIEKGP[12]\ : NOR3A - port map(A => counter_delta_f0_1_0_a2_3, B => - counter_delta_f0_1_0_a2_0, C => N_272, Y => - un1_start_snapshot_f22_i_a2_0_4); - - \counter_delta_snapshot_RNO_2[15]\ : OR3 - port map(A => N_395, B => \counter_delta_snapshot_i[15]\, C - => N_504_0, Y => N_482); - - \counter_delta_snapshot_RNIA82J[26]\ : OR3A - port map(A => N_406, B => - \counter_delta_snapshot[26]_net_1\, C => - un2_coarse_time_0, Y => N_505); - - \counter_delta_f0_RNIA81P1[8]\ : OR3 - port map(A => N_59, B => \counter_delta_f0[7]_net_1\, C => - \counter_delta_f0[8]_net_1\, Y => N_63); - - \counter_delta_f0_RNI9MCV1[3]\ : NOR3A - port map(A => counter_delta_f0lde_i_a2_0_1_2, B => N_89, C - => \counter_delta_f0[3]_net_1\, Y => - counter_delta_f0lde_i_a2_0_1_3); - - \counter_delta_snapshot_RNO_2[14]\ : OR3A - port map(A => \counter_delta_snapshot[14]_net_1\, B => - N_394, C => N_504_0, Y => N_488); - - \counter_delta_snapshot_RNIJ7B1[6]\ : NOR2 - port map(A => \counter_delta_snapshot[6]_net_1\, B => N_386, - Y => N_387); - - \counter_delta_f0_RNO[20]\ : XA1A - port map(A => \counter_delta_f0[20]_net_1\, B => N_106, C - => N_57, Y => counter_delta_f0_n20); - - \counter_delta_snapshot_RNO_3[7]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e7_i_a2_0, Y => N_460); - - \counter_delta_snapshot_RNI1LV1[9]\ : OR2A - port map(A => N_389, B => \counter_delta_snapshot[9]_net_1\, - Y => N_390); - - \counter_delta_snapshot[21]\ : DFN1C0 - port map(D => counter_delta_snapshot_e21, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[21]_net_1\); - - \counter_delta_snapshot_RNIOJO3[2]\ : XA1A - port map(A => delta_snapshot(2), B => - \counter_delta_snapshot[2]_net_1\, C => N_510_i, Y => - un12_start_snapshot_fothers_temp_NE_4); - - \counter_delta_f0[15]\ : DFN1E0C0 - port map(D => counter_delta_f0_n15, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[15]_net_1\); - - \counter_delta_snapshot_RNO_2[11]\ : OR3 - port map(A => N_391, B => \counter_delta_snapshot_i[11]\, C - => N_504_0, Y => N_503); - - \counter_delta_snapshot_RNIRL41[5]\ : OR2A - port map(A => \counter_delta_snapshot_i[5]\, B => N_385, Y - => N_386); - - \counter_delta_snapshot_RNO[20]\ : OR3C - port map(A => N_180, B => N_181, C => N_182, Y => - \counter_delta_snapshot_RNO[20]_net_1\); - - \counter_delta_snapshot_RNI48U[4]\ : OR2 - port map(A => \counter_delta_snapshot[4]_net_1\, B => N_384, - Y => N_385); - - \counter_delta_snapshot_RNO_1[10]\ : AO1A - port map(A => \counter_delta_snapshot[10]_net_1\, B => - un2_coarse_time_0, C => N_474, Y => - counter_delta_snapshot_e10_i_0); - - \counter_delta_f0_RNIAEIE[18]\ : OR3A - port map(A => counter_delta_f0_1_0_a2_8_0, B => - \counter_delta_f0[19]_net_1\, C => - \counter_delta_f0[18]_net_1\, Y => counter_delta_f0_1_8); - - \counter_delta_snapshot_RNO[25]\ : OR3C - port map(A => N_421, B => N_422, C => N_423, Y => - counter_delta_snapshot_e25); - - \counter_delta_f0_RNIOOKV[4]\ : NOR3 - port map(A => N_89, B => \counter_delta_f0[3]_net_1\, C => - \counter_delta_f0[4]_net_1\, Y => N_55); - - \counter_delta_f0_RNI4JE41[10]\ : NOR3A - port map(A => counter_delta_f0_1_0_a2_5_0, B => - counter_delta_f0_1_8, C => counter_delta_f0_1_0_a2_5, Y - => un1_start_snapshot_f22_i_a2_0_5); - - \counter_delta_snapshot_RNO[4]\ : NOR3C - port map(A => N_447, B => counter_delta_snapshot_e4_i_0, C - => N_448, Y => N_375_i_0); - - \counter_delta_snapshot[23]\ : DFN1C0 - port map(D => counter_delta_snapshot_e23, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[23]_net_1\); - - \counter_delta_snapshot_RNO_4[8]\ : OR2 - port map(A => \counter_delta_snapshot[8]_net_1\, B => N_388, - Y => counter_delta_snapshot_e8_i_a2_0); - - \counter_delta_snapshot_RNO[23]\ : OAI1 - port map(A => N_404, B => N_504_0, C => - counter_delta_snapshot_e23_0_0_0, Y => - counter_delta_snapshot_e23); - - \counter_delta_snapshot[17]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[17]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[17]_net_1\); - - \counter_delta_f0[4]\ : DFN1E0C0 - port map(D => N_229, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[4]_net_1\); - - \counter_delta_snapshot_RNI9KE[23]\ : NOR2 - port map(A => \counter_delta_snapshot[22]_net_1\, B => - \counter_delta_snapshot[23]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_3); - - \counter_delta_f0[13]\ : DFN1E0C0 - port map(D => counter_delta_f0_n13, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[13]_net_1\); - - \counter_delta_snapshot_RNO_2[12]\ : OR3A - port map(A => \counter_delta_snapshot[12]_net_1\, B => - \counter_delta_snapshot_RNI01E2[7]_net_1\, C => N_504_0, - Y => N_498); - - \counter_delta_snapshot_RNO_2[19]\ : OA1 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot[19]_net_1\, Y => - counter_delta_snapshot_e19_i_i_a2_0); - - \counter_delta_f0_RNI9MCV1[9]\ : NOR2 - port map(A => \counter_delta_f0[9]_net_1\, B => N_63, Y => - N_65); - - \counter_delta_f0_RNO_0[3]\ : XNOR2 - port map(A => \counter_delta_f0[3]_net_1\, B => N_89, Y => - N_115_i_i); - - \counter_delta_snapshot_RNI6NO1[8]\ : NOR2A - port map(A => N_388, B => \counter_delta_snapshot[8]_net_1\, - Y => N_389); - - \counter_delta_snapshot_RNO_2[16]\ : OR3 - port map(A => N_396, B => - \counter_delta_snapshot[16]_net_1\, C => N_504, Y => - N_170); - - \counter_delta_snapshot_RNICTH1[7]\ : NOR2A - port map(A => N_387, B => \counter_delta_snapshot[7]_net_1\, - Y => N_388); - - start_snapshot_fothers_temp : DFN1E0C0 - port map(D => start_snapshot_f22, CLK => lclk_c, CLR => - rstn, E => N_284, Q => \start_snapshot_fothers_temp\); - - \counter_delta_snapshot_RNO_1[5]\ : AOI1B - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot_i[5]\, C => N_450, Y => - counter_delta_snapshot_e5_i_0); - - \counter_delta_snapshot_RNINGL2[4]\ : XNOR2 - port map(A => \counter_delta_snapshot[4]_net_1\, B => - delta_snapshot(4), Y => N_507_i); - - \counter_delta_snapshot_RNO_2[17]\ : OA1 - port map(A => N_396, B => - \counter_delta_snapshot[16]_net_1\, C => - \counter_delta_snapshot[17]_net_1\, Y => - counter_delta_snapshot_e17_i_i_a2_0); - - \counter_delta_snapshot_RNO[7]\ : NOR3 - port map(A => N_462, B => counter_delta_snapshot_e7_i_0, C - => N_463, Y => \counter_delta_snapshot_RNO[7]_net_1\); - - \counter_delta_f0_RNI0TL62[11]\ : OR2 - port map(A => \counter_delta_f0[11]_net_1\, B => N_67, Y - => N_98); - - GND_i : GND - port map(Y => \GND\); - - \counter_delta_snapshot[10]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[10]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[10]_net_1\); - - \counter_delta_snapshot_RNO_4[3]\ : OR2A - port map(A => N_383, B => \counter_delta_snapshot[3]_net_1\, - Y => counter_delta_snapshot_e3_i_a2_0); - - \counter_delta_snapshot_RNIEQGD[12]\ : NOR3C - port map(A => un12_start_snapshot_fothers_temp_NE_1, B => - un12_start_snapshot_fothers_temp_NE_0, C => - un12_start_snapshot_fothers_temp_NE_9, Y => - un12_start_snapshot_fothers_temp_NE_12); - - start_snapshot_f2_temp_RNIEAF61 : NOR3B - port map(A => un12_start_snapshot_fothers_temp_NE_12, B => - un12_start_snapshot_fothers_temp_NE_13, C => - start_snapshot_f22_0_a2_1, Y => start_snapshot_f22); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \counter_delta_snapshot_RNO_0[6]\ : NOR2 - port map(A => N_505, B => delta_snapshot(6), Y => N_457); - - \counter_delta_snapshot_RNI3DS2[13]\ : OR2 - port map(A => \counter_delta_snapshot[13]_net_1\, B => - N_393, Y => N_394); - - \counter_delta_snapshot[3]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[3]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[3]_net_1\); - - \counter_delta_f0_RNO_0[7]\ : XNOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => N_59, Y => - N_89_i_i); - - \counter_delta_snapshot_RNO_3[18]\ : NOR2B - port map(A => \counter_delta_snapshot[18]_net_1\, B => - N_398, Y => counter_delta_snapshot_e18_i_i_a2_0); - - \start_snapshot_f0\ : DFN1C0 - port map(D => counter_delta_f0_1, CLK => lclk_c, CLR => - rstn, Q => start_snapshot_f0); - - \counter_delta_snapshot[12]\ : DFN1C0 - port map(D => N_195_i_0, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[12]_net_1\); - - start_snapshot_f0_RNO_0 : NOR3A - port map(A => counter_delta_f0_1_0_a2_6, B => - counter_delta_f0_1_0_a2_7, C => counter_delta_f0_1_0_a2_5, - Y => counter_delta_f0_1_0_a2_11); - - \counter_delta_snapshot_RNO_0[0]\ : AO1D - port map(A => N_505, B => delta_snapshot(0), C => N_429, Y - => counter_delta_snapshot_e0_i_0); - - \counter_delta_snapshot_RNO_2[10]\ : NOR3A - port map(A => \counter_delta_snapshot[10]_net_1\, B => - N_390, C => N_504_0, Y => N_477); - - \counter_delta_f0_RNITHHS2[17]\ : OR2 - port map(A => \counter_delta_f0[17]_net_1\, B => N_103, Y - => N_104); - - \counter_delta_f0_RNO[25]\ : XA1A - port map(A => N_66, B => \counter_delta_f0[25]_net_1\, C - => N_57, Y => N_32); - - \counter_delta_snapshot_RNO[12]\ : NOR3C - port map(A => N_496, B => counter_delta_snapshot_e12_i_0_0, - C => N_498, Y => N_195_i_0); - - start_snapshot_f2_temp : DFN1C0 - port map(D => start_snapshot_f2_temp3, CLK => lclk_c, CLR - => rstn, Q => \start_snapshot_f2_temp\); - - \counter_delta_f0_RNI1F97[22]\ : OR2 - port map(A => \counter_delta_f0[23]_net_1\, B => - \counter_delta_f0[22]_net_1\, Y => - counter_delta_f0_1_0_a2_2); - - \counter_delta_f0[20]\ : DFN1E0C0 - port map(D => counter_delta_f0_n20, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[20]_net_1\); - - \counter_delta_snapshot_RNO_4[13]\ : NOR2A - port map(A => N_393, B => - \counter_delta_snapshot[13]_net_1\, Y => - counter_delta_snapshot_e13_i_0_a2_0); - - \counter_delta_f0_RNIR697[12]\ : OR2 - port map(A => \counter_delta_f0[13]_net_1\, B => - \counter_delta_f0[12]_net_1\, Y => N_272); - - \counter_delta_snapshot_RNO_0[1]\ : NOR2 - port map(A => N_505, B => delta_snapshot(1), Y => N_433); - - \counter_delta_f0_RNIBUSO2[16]\ : OR2 - port map(A => \counter_delta_f0[16]_net_1\, B => N_102, Y - => N_103); - - \counter_delta_f0[17]\ : DFN1E0C0 - port map(D => counter_delta_f0_n17, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[17]_net_1\); - - \counter_delta_f0_RNO_0[26]\ : NOR2 - port map(A => \counter_delta_f0[25]_net_1\, B => N_66, Y - => N_80); - - \counter_delta_snapshot_RNO_4[15]\ : NOR2B - port map(A => \counter_delta_snapshot_i[15]\, B => N_395, Y - => counter_delta_snapshot_e15_i_0_a2_0); - - \counter_delta_snapshot_RNIT8M2[7]\ : XNOR2 - port map(A => \counter_delta_snapshot[7]_net_1\, B => - delta_snapshot(7), Y => N_164_i_i); - - \counter_delta_snapshot_RNIBJ31[13]\ : XNOR2 - port map(A => \counter_delta_snapshot[13]_net_1\, B => - delta_snapshot(13), Y => N_133_i_i); - - \counter_delta_f0[2]\ : DFN1E0C0 - port map(D => N_227, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[2]_net_1\); - - \counter_delta_snapshot_RNO[18]\ : OR3C - port map(A => N_174, B => N_175, C => N_176, Y => - \counter_delta_snapshot_RNO[18]_net_1\); - - \counter_delta_snapshot_RNO_4[14]\ : NOR2A - port map(A => N_394, B => - \counter_delta_snapshot[14]_net_1\, Y => - counter_delta_snapshot_e14_i_0_a2_0); - - \counter_delta_f0[21]\ : DFN1E0C0 - port map(D => N_276, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[21]_net_1\); - - \counter_delta_f0_RNO[1]\ : MX2 - port map(A => delta_f2_f0(1), B => N_107_i_i, S => N_57_0, - Y => N_23); - - \counter_delta_snapshot_RNIAPA3[15]\ : OR2A - port map(A => \counter_delta_snapshot_i[15]\, B => N_395, Y - => N_396); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_delta_snapshot_RNO_1[9]\ : AO1A - port map(A => \counter_delta_snapshot[9]_net_1\, B => - un2_coarse_time_0_0, C => N_469, Y => - counter_delta_snapshot_e9_i_0); - - \counter_delta_snapshot_RNO_4[2]\ : OR2 - port map(A => \counter_delta_snapshot[2]_net_1\, B => N_382, - Y => counter_delta_snapshot_e2_i_a2_0); - - \counter_delta_f0_RNI4PQ33[19]\ : OR2A - port map(A => N_105, B => \counter_delta_f0[19]_net_1\, Y - => N_106); - - start_snapshot_f0_RNO_4 : NOR3B - port map(A => \counter_delta_f0[0]_net_1\, B => - counter_delta_f0_1_0_a2_2_0, C => - \counter_delta_f0[3]_net_1\, Y => - counter_delta_f0_1_0_a2_8); - - \counter_delta_snapshot_RNO_1[3]\ : AO1A - port map(A => \counter_delta_snapshot[3]_net_1\, B => - un2_coarse_time_0_0, C => N_440, Y => - counter_delta_snapshot_e3_i_0); - - \counter_delta_snapshot_RNO_0[3]\ : NOR2 - port map(A => N_505, B => delta_snapshot(3), Y => N_442); - - \counter_delta_snapshot_RNIIQ45[23]\ : OR3 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => - \counter_delta_snapshot[23]_net_1\, Y => N_404); - - \counter_delta_snapshot_RNO_4[11]\ : NOR2B - port map(A => \counter_delta_snapshot_i[11]\, B => N_391, Y - => counter_delta_snapshot_e11_i_0_a2_0); - - \counter_delta_snapshot_RNO_1[23]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e23_0_0_a2_0, Y => - N_189); - - \counter_delta_f0_RNO[16]\ : XA1A - port map(A => \counter_delta_f0[16]_net_1\, B => N_102, C - => N_57, Y => counter_delta_f0_n16); - - \counter_delta_snapshot_RNO_1[0]\ : NOR2A - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[0]_net_1\, Y => N_429); - - \counter_delta_snapshot_RNIFVC[5]\ : NOR2A - port map(A => \counter_delta_snapshot_i[5]\, B => - \counter_delta_snapshot[6]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_2); - - \counter_delta_f0_RNO[8]\ : MX2 - port map(A => delta_f2_f0(8), B => N_99_i_i, S => N_57, Y - => N_15); - - \op_eq.start_snapshot_f12_0_a2_RNO_9\ : XNOR2 - port map(A => \counter_delta_f0[6]_net_1\, B => - delta_f2_f1(6), Y => N_81_i_i_0); - - \counter_delta_snapshot_RNI4BQ[11]\ : NOR3B - port map(A => \counter_delta_snapshot_i[11]\, B => - counter_delta_snapshot_e12_i_0_o2_m6_e_2, C => - \counter_delta_snapshot[3]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_5); - - \counter_delta_snapshot_RNO_1[25]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[25]_net_1\, Y => N_422); - - \counter_delta_snapshot_RNO[2]\ : NOR3 - port map(A => N_437, B => counter_delta_snapshot_e2_i_0, C - => N_438, Y => N_54); - - \counter_delta_snapshot[26]\ : DFN1C0 - port map(D => counter_delta_snapshot_e26, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[26]_net_1\); - - \counter_delta_f0_RNIHVOE3[22]\ : OR2 - port map(A => \counter_delta_f0[22]_net_1\, B => N_60, Y - => N_62); - - \start_snapshot_f1\ : DFN1C0 - port map(D => start_snapshot_f12, CLK => lclk_c, CLR => - rstn, Q => start_snapshot_f1); - - \counter_delta_snapshot_RNIA82J_0[26]\ : OA1A - port map(A => N_406, B => un2_coarse_time_0, C => - \counter_delta_snapshot[26]_net_1\, Y => - counter_delta_snapshot_e26); - - \counter_delta_f0_RNI184B3[21]\ : OR2 - port map(A => \counter_delta_f0[21]_net_1\, B => N_58, Y - => N_60); - - \counter_delta_snapshot_RNO_1[7]\ : AO1A - port map(A => \counter_delta_snapshot[7]_net_1\, B => - un2_coarse_time_0_0, C => N_460, Y => - counter_delta_snapshot_e7_i_0); - - \counter_delta_f0_RNO[5]\ : MX2 - port map(A => delta_f2_f0(5), B => N_117_i_i, S => N_57_0, - Y => N_230); - - \counter_delta_snapshot_RNO_1[24]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e24_0_0_a2_0, Y => - N_192); - - \counter_delta_snapshot_RNO[6]\ : NOR3 - port map(A => N_457, B => counter_delta_snapshot_e6_i_0, C - => N_458, Y => \counter_delta_snapshot_RNO[6]_net_1\); - - \counter_delta_f0_RNIFOAC1[6]\ : OR3A - port map(A => N_55, B => \counter_delta_f0[5]_net_1\, C => - \counter_delta_f0[6]_net_1\, Y => N_59); - - \counter_delta_snapshot_RNO_4[12]\ : NOR2A - port map(A => \counter_delta_snapshot_RNI01E2[7]_net_1\, B - => \counter_delta_snapshot[12]_net_1\, Y => - counter_delta_snapshot_e12_i_0_a2_0); - - \counter_delta_snapshot[24]\ : DFN1C0 - port map(D => counter_delta_snapshot_e24, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[24]_net_1\); - - \op_eq.start_snapshot_f12_0_a2_RNO_6\ : XNOR2 - port map(A => \counter_delta_f0[2]_net_1\, B => - delta_f2_f1(2), Y => N_274_i_0); - - \counter_delta_snapshot_RNO_3[13]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e13_i_0_a2_0, Y => - N_285); - - \counter_delta_f0_RNO[4]\ : MX2 - port map(A => delta_f2_f0(4), B => N_116_i_i, S => N_57_0, - Y => N_229); - - \counter_delta_snapshot_RNO_3[3]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e3_i_a2_0, Y => N_440); - - \counter_delta_snapshot_RNO_1[21]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e21_0_0_a2_0, Y => - N_183); - - \op_eq.start_snapshot_f12_0_a2_RNO_3\ : XNOR2 - port map(A => \counter_delta_f0[9]_net_1\, B => - delta_f2_f1(9), Y => N_84_i_i_0); - - \counter_delta_snapshot_RNIEUN[3]\ : OR2 - port map(A => \counter_delta_snapshot[3]_net_1\, B => N_383, - Y => N_384); - - \counter_delta_f0[12]\ : DFN1E0C0 - port map(D => counter_delta_f0_n12, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[12]_net_1\); - - \counter_delta_snapshot_RNIVEJ5_0[25]\ : NOR2 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - N_405, Y => N_406_0); - - \counter_delta_f0_RNIG5603[18]\ : NOR2 - port map(A => \counter_delta_f0[18]_net_1\, B => N_104, Y - => N_105); - - \counter_delta_snapshot_RNO_3[15]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e15_i_0_a2_0, Y => - N_478); - - \counter_delta_snapshot_RNO_1[6]\ : AO1A - port map(A => \counter_delta_snapshot[6]_net_1\, B => - un2_coarse_time_0_0, C => N_455, Y => - counter_delta_snapshot_e6_i_0); - - \counter_delta_snapshot_RNI96M4[21]\ : OR3 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - \counter_delta_snapshot[21]_net_1\, Y => N_402); - - \counter_delta_f0_RNO[10]\ : XA1 - port map(A => N_65, B => \counter_delta_f0[10]_net_1\, C - => N_57_0, Y => N_19); - - \op_eq.start_snapshot_f12_0_a2_RNO_10\ : XA1A - port map(A => delta_f2_f1(1), B => - \counter_delta_f0[1]_net_1\, C => N_111_i_i_0, Y => - start_snapshot_f12_0_a2_1); - - \counter_delta_snapshot_RNO_3[22]\ : NOR2B - port map(A => \counter_delta_snapshot[22]_net_1\, B => - N_402, Y => counter_delta_snapshot_e22_0_0_a2_0); - - \counter_delta_snapshot_RNO_2[8]\ : NOR3B - port map(A => N_388, B => \counter_delta_snapshot[8]_net_1\, - C => N_504_0, Y => N_468); - - \counter_delta_snapshot_RNIO4C5[24]\ : OR2 - port map(A => \counter_delta_snapshot[24]_net_1\, B => - N_404, Y => N_405); - - \counter_delta_snapshot_RNIHOK2[1]\ : XNOR2 - port map(A => \counter_delta_snapshot[1]_net_1\, B => - delta_snapshot(1), Y => N_137_i_i); - - \counter_delta_snapshot_RNO_3[14]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e14_i_0_a2_0, Y => - N_484); - - \counter_delta_f0[3]\ : DFN1E0C0 - port map(D => N_228, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[3]_net_1\); - - \op_eq.start_snapshot_f12_0_a2_RNO_7\ : XA1A - port map(A => delta_f2_f1(4), B => - \counter_delta_f0[4]_net_1\, C => N_113_i_i_0, Y => - start_snapshot_f12_0_a2_2); - - \counter_delta_snapshot_RNO_0[8]\ : NOR2 - port map(A => N_505, B => delta_snapshot(8), Y => N_467); - - \counter_delta_snapshot_RNO_0[4]\ : OR2 - port map(A => N_505, B => delta_snapshot(4), Y => N_447); - - \counter_delta_f0_RNO_0[8]\ : AX1B - port map(A => N_59, B => \counter_delta_f0[7]_net_1\, C => - \counter_delta_f0[8]_net_1\, Y => N_99_i_i); - - \counter_delta_f0[24]\ : DFN1E0C0 - port map(D => N_30, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[24]_net_1\); - - \counter_delta_snapshot_RNO_1[22]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[22]_net_1\, Y => N_187); - - \counter_delta_f0_RNO[23]\ : XA1A - port map(A => N_62, B => \counter_delta_f0[23]_net_1\, C - => N_57, Y => N_28); - - \counter_delta_snapshot_RNO_3[11]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e11_i_0_a2_0, Y => - N_499); - - \counter_delta_snapshot_RNO_2[1]\ : NOR3A - port map(A => \counter_delta_snapshot[1]_net_1\, B => - \counter_delta_snapshot[0]_net_1\, C => N_504, Y => N_435); - - \counter_delta_f0_RNO_0[6]\ : AX1 - port map(A => \counter_delta_f0[5]_net_1\, B => N_55, C => - \counter_delta_f0[6]_net_1\, Y => N_87_i_i); - - \counter_delta_f0_RNO_0[2]\ : AX1B - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[1]_net_1\, C => - \counter_delta_f0[2]_net_1\, Y => N_114_i_i); - - \counter_delta_snapshot_RNO[22]\ : OR3C - port map(A => N_186, B => N_187, C => N_188, Y => - counter_delta_snapshot_e22); - - \counter_delta_snapshot_RNO[1]\ : NOR3 - port map(A => N_433, B => counter_delta_snapshot_e1_i_0, C - => N_435, Y => \counter_delta_snapshot_RNO[1]_net_1\); - - \counter_delta_snapshot_RNO[14]\ : NOR3C - port map(A => N_486, B => counter_delta_snapshot_e14_i_0_0, - C => N_488, Y => N_6_i_0); - - \counter_delta_f0_RNIQA8L2[15]\ : OR2 - port map(A => \counter_delta_f0[15]_net_1\, B => N_101, Y - => N_102); - - \counter_delta_f0_RNIDUTA[14]\ : NOR3 - port map(A => \counter_delta_f0[14]_net_1\, B => - \counter_delta_f0[15]_net_1\, C => - \counter_delta_f0[20]_net_1\, Y => - counter_delta_f0_1_0_a2_3); - - \counter_delta_snapshot_RNO_2[7]\ : NOR3B - port map(A => N_387, B => \counter_delta_snapshot[7]_net_1\, - C => N_504, Y => N_463); - - \counter_delta_f0_RNO[3]\ : MX2 - port map(A => delta_f2_f0(3), B => N_115_i_i, S => N_57_0, - Y => N_228); - - \counter_delta_snapshot_RNO_2[23]\ : OA1 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => - \counter_delta_snapshot[23]_net_1\, Y => - counter_delta_snapshot_e23_0_0_a2_0); - - \counter_delta_snapshot_RNIL8L2[3]\ : XNOR2 - port map(A => \counter_delta_snapshot[3]_net_1\, B => - delta_snapshot(3), Y => N_506_i); - - \start_snapshot_f2\ : DFN1C0 - port map(D => start_snapshot_f22, CLK => lclk_c, CLR => - rstn, Q => start_snapshot_f2); - - \counter_delta_snapshot_RNIPOH[2]\ : OR2A - port map(A => N_382, B => \counter_delta_snapshot[2]_net_1\, - Y => N_383); - - \counter_delta_snapshot_RNIFGK2[0]\ : XNOR2 - port map(A => \counter_delta_snapshot[0]_net_1\, B => - delta_snapshot(0), Y => N_136_i_i); - - \counter_delta_snapshot_RNO_2[6]\ : NOR3A - port map(A => \counter_delta_snapshot[6]_net_1\, B => N_386, - C => N_504, Y => N_458); - - \counter_delta_snapshot_RNO_4[10]\ : OR2A - port map(A => N_390, B => - \counter_delta_snapshot[10]_net_1\, Y => - counter_delta_snapshot_e10_i_a2_0); - - \op_eq.start_snapshot_f12_0_a2_RNO_5\ : XNOR2 - port map(A => \counter_delta_f0[8]_net_1\, B => - delta_f2_f1(8), Y => N_83_i_i_0); - - \counter_delta_f0[25]\ : DFN1E0C0 - port map(D => N_32, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[25]_net_1\); - - \counter_delta_snapshot_RNIE8T[21]\ : NOR3A - port map(A => start_snapshot_f22_0_a2_11_0_a2_3, B => - \counter_delta_snapshot[21]_net_1\, C => - \counter_delta_snapshot[20]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_5); - - \counter_delta_snapshot_RNO_2[25]\ : OR2A - port map(A => N_406, B => N_504, Y => N_423); - - \counter_delta_snapshot_RNIFCE[19]\ : NOR2 - port map(A => \counter_delta_snapshot[18]_net_1\, B => - \counter_delta_snapshot[19]_net_1\, Y => - start_snapshot_f22_0_a2_11_0_a2_1); - - \counter_delta_snapshot_RNO_3[12]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e12_i_0_a2_0, Y => - N_493); - - coarse_time_0_r_RNI3F7D : OR2B - port map(A => coarse_time_0_r_i, B => coarse_time(0), Y => - un2_coarse_time_0); - - \counter_delta_f0_RNO[9]\ : MX2 - port map(A => delta_f2_f0(9), B => N_324_i, S => N_57, Y - => N_17); - - \counter_delta_f0[16]\ : DFN1E0C0 - port map(D => counter_delta_f0_n16, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[16]_net_1\); - - \counter_delta_snapshot_RNO_2[24]\ : NOR2B - port map(A => \counter_delta_snapshot[24]_net_1\, B => - N_404, Y => counter_delta_snapshot_e24_0_0_a2_0); - - start_snapshot_f0_RNO_3 : NOR3A - port map(A => N_273, B => \counter_delta_f0[2]_net_1\, C - => \counter_delta_f0[1]_net_1\, Y => - counter_delta_f0_1_0_a2_6); - - \counter_delta_snapshot_RNIGJOA[3]\ : NOR3C - port map(A => N_506_i, B => N_166_i_i, C => - un12_start_snapshot_fothers_temp_NE_7, Y => - un12_start_snapshot_fothers_temp_NE_11); - - \counter_delta_snapshot_RNO_3[8]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e8_i_a2_0, Y => N_465); - - \counter_delta_snapshot_RNO_3[20]\ : NOR2B - port map(A => \counter_delta_snapshot[20]_net_1\, B => - N_400, Y => counter_delta_snapshot_e20_i_i_a2_0); - - \counter_delta_snapshot_RNO_3[16]\ : NOR2B - port map(A => \counter_delta_snapshot[16]_net_1\, B => - N_396, Y => counter_delta_snapshot_e16_i_i_a2_0); - - \counter_delta_snapshot_RNO_3[9]\ : OA1C - port map(A => N_406, B => - \counter_delta_snapshot[26]_net_1\, C => - counter_delta_snapshot_e9_i_a2_0, Y => N_469); - - \counter_delta_snapshot_RNO_2[3]\ : NOR3A - port map(A => \counter_delta_snapshot[3]_net_1\, B => N_383, - C => N_504, Y => N_443); - - \counter_delta_f0_RNO[19]\ : XA1 - port map(A => \counter_delta_f0[19]_net_1\, B => N_105, C - => N_57, Y => counter_delta_f0_n19); - - \counter_delta_snapshot_RNI1PM2[9]\ : XNOR2 - port map(A => \counter_delta_snapshot[9]_net_1\, B => - delta_snapshot(9), Y => N_166_i_i); - - \counter_delta_snapshot_RNI17L2[12]\ : OR2 - port map(A => \counter_delta_snapshot_RNI01E2[7]_net_1\, B - => \counter_delta_snapshot[12]_net_1\, Y => N_393); - - \counter_delta_f0_RNO_0[1]\ : XNOR2 - port map(A => \counter_delta_f0[1]_net_1\, B => - \counter_delta_f0[0]_net_1\, Y => N_107_i_i); - - \counter_delta_snapshot_RNO_2[21]\ : OA1 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => - \counter_delta_snapshot[21]_net_1\, Y => - counter_delta_snapshot_e21_0_0_a2_0); - - \counter_delta_f0_RNIDGAA2[12]\ : OR2 - port map(A => \counter_delta_f0[12]_net_1\, B => N_98, Y - => N_99); - - \counter_delta_snapshot[20]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[20]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[20]_net_1\); - - \counter_delta_f0[0]\ : DFN1E0C0 - port map(D => N_21, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[0]_net_1\); - - \counter_delta_f0[23]\ : DFN1E0C0 - port map(D => N_28, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[23]_net_1\); - - \counter_delta_f0_RNO[22]\ : XA1A - port map(A => N_60, B => \counter_delta_f0[22]_net_1\, C - => N_57, Y => N_277); - - \counter_delta_f0[8]\ : DFN1E0C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[8]_net_1\); - - coarse_time_0_r_RNI3F7D_0 : OR2B - port map(A => coarse_time_0_r_i, B => coarse_time(0), Y => - un2_coarse_time_0_0); - - \counter_delta_snapshot_RNO_1[20]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[20]_net_1\, Y => N_181); - - \counter_delta_snapshot_RNO_0[9]\ : NOR2 - port map(A => N_505, B => delta_snapshot(9), Y => N_471); - - \counter_delta_f0_RNO[2]\ : MX2 - port map(A => delta_f2_f0(2), B => N_114_i_i, S => N_57_0, - Y => N_227); - - start_snapshot_f0_RNO_2 : NOR3B - port map(A => counter_delta_f0_1_0_a2_3, B => - counter_delta_f0_1_0_a2_8, C => counter_delta_f0_1_8, Y - => counter_delta_f0_1_0_a2_12); - - \counter_delta_snapshot_RNO_1[4]\ : OA1A - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[4]_net_1\, C => N_445, Y => - counter_delta_snapshot_e4_i_0); - - \counter_delta_f0_RNIN697[10]\ : OR2 - port map(A => \counter_delta_f0[11]_net_1\, B => - \counter_delta_f0[10]_net_1\, Y => - counter_delta_f0_1_0_a2_5); - - start_snapshot_fothers_temp_RNISVED5 : AOI1B - port map(A => sample_f0_val_0, B => - counter_delta_f0lde_i_a2_0_1_i, C => N_57_0, Y => N_9_0); - - \counter_delta_snapshot_RNIM1C5[5]\ : XA1 - port map(A => delta_snapshot(5), B => - \counter_delta_snapshot_i[5]\, C => N_164_i_i, Y => - un12_start_snapshot_fothers_temp_NE_5); - - start_snapshot_f0_RNO : NOR3C - port map(A => counter_delta_f0_1_0_a2_11, B => - counter_delta_f0_1_0_a2_10, C => - counter_delta_f0_1_0_a2_12, Y => counter_delta_f0_1); - - \counter_delta_snapshot_RNO_2[22]\ : OR3 - port map(A => N_402, B => - \counter_delta_snapshot[22]_net_1\, C => N_504, Y => - N_188); - - \counter_delta_snapshot_0[26]\ : DFN1C0 - port map(D => counter_delta_snapshot_e26, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot_0[26]_net_1\); - - start_snapshot_f2_temp_RNIQ573 : OR2 - port map(A => \start_snapshot_f2_temp\, B => - start_snapshot_f22_10, Y => start_snapshot_f22_0_a2_0); - - \op_eq.start_snapshot_f12_0_a2_RNO_8\ : XNOR2 - port map(A => \counter_delta_f0[7]_net_1\, B => - delta_f2_f1(7), Y => N_82_i_i_0); - - \counter_delta_snapshot_RNO[9]\ : NOR3 - port map(A => N_471, B => counter_delta_snapshot_e9_i_0, C - => N_472, Y => \counter_delta_snapshot_RNO[9]_net_1\); - - \counter_delta_f0[1]\ : DFN1E0C0 - port map(D => N_23, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[1]_net_1\); - - \counter_delta_snapshot[22]\ : DFN1C0 - port map(D => counter_delta_snapshot_e22, CLK => lclk_c, - CLR => rstn, Q => \counter_delta_snapshot[22]_net_1\); - - \counter_delta_snapshot_RNIU8TJ[2]\ : NOR3C - port map(A => un12_start_snapshot_fothers_temp_NE_5, B => - un12_start_snapshot_fothers_temp_NE_4, C => - un12_start_snapshot_fothers_temp_NE_11, Y => - un12_start_snapshot_fothers_temp_NE_13); - - \counter_delta_f0_RNO[15]\ : XA1A - port map(A => \counter_delta_f0[15]_net_1\, B => N_101, C - => N_57_0, Y => counter_delta_f0_n15); - - \counter_delta_f0[19]\ : DFN1E0C0 - port map(D => counter_delta_f0_n19, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[19]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \counter_delta_snapshot_RNO_0[5]\ : OR2 - port map(A => N_505, B => delta_snapshot(5), Y => N_452); - - \counter_delta_snapshot_RNILUL[24]\ : OR3 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - \counter_delta_snapshot[24]_net_1\, C => - \counter_delta_snapshot[26]_net_1\, Y => - start_snapshot_f22_10); - - \counter_delta_f0_RNO[24]\ : XA1A - port map(A => N_64, B => \counter_delta_f0[24]_net_1\, C - => N_57, Y => N_30); - - \counter_delta_snapshot_RNO[3]\ : NOR3 - port map(A => N_442, B => counter_delta_snapshot_e3_i_0, C - => N_443, Y => \counter_delta_snapshot_RNO[3]_net_1\); - - start_snapshot_f2_temp_RNO_0 : OR3B - port map(A => start_snapshot_f22_0_a2_11_0_a2_4, B => - start_snapshot_f22_0_a2_11_0_a2_5, C => - start_snapshot_f22_10, Y => - start_snapshot_f2_temp3_0_a2_0); - - \counter_delta_snapshot_RNI6J33[14]\ : OR2 - port map(A => \counter_delta_snapshot[14]_net_1\, B => - N_394, Y => N_395); - - \counter_delta_snapshot[6]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[6]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[6]_net_1\); - - \counter_delta_f0[18]\ : DFN1E0C0 - port map(D => counter_delta_f0_n18, CLK => lclk_c, CLR => - rstn, E => N_9_0, Q => \counter_delta_f0[18]_net_1\); - - \op_eq.start_snapshot_f12_0_a2_RNO_1\ : NOR3C - port map(A => N_83_i_i_0, B => N_274_i_0, C => - start_snapshot_f12_0_a2_2, Y => start_snapshot_f12_0_a2_6); - - \op_eq.start_snapshot_f12_0_a2_RNO\ : AND2 - port map(A => start_snapshot_f12_0_a2_7, B => - start_snapshot_f12_0_a2_6, Y => start_snapshot_f12_0_a2_8); - - \counter_delta_snapshot_RNO_3[10]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e10_i_a2_0, Y => N_474); - - \counter_delta_f0_RNILNLC[4]\ : NOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => - \counter_delta_f0[4]_net_1\, Y => N_273); - - \counter_delta_snapshot_RNIK672[12]\ : XA1A - port map(A => delta_snapshot(12), B => - \counter_delta_snapshot[12]_net_1\, C => N_133_i_i, Y => - un12_start_snapshot_fothers_temp_NE_0); - - \counter_delta_f0[6]\ : DFN1E0C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[6]_net_1\); - - \counter_delta_snapshot[8]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[8]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[8]_net_1\); - - \counter_delta_snapshot_RNO_0[18]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e18_i_i_a2_0, Y => - N_174); - - \counter_delta_snapshot_RNIQHC5[6]\ : XA1A - port map(A => delta_snapshot(6), B => - \counter_delta_snapshot[6]_net_1\, C => N_509_i, Y => - un12_start_snapshot_fothers_temp_NE_7); - - \counter_delta_f0_RNO[21]\ : XA1A - port map(A => N_58, B => \counter_delta_f0[21]_net_1\, C - => N_57, Y => N_276); - - \counter_delta_snapshot_RNIVGM2[8]\ : XNOR2 - port map(A => \counter_delta_snapshot[8]_net_1\, B => - delta_snapshot(8), Y => N_509_i); - - \counter_delta_snapshot_RNO_4[7]\ : OR2 - port map(A => \counter_delta_snapshot[7]_net_1\, B => N_387, - Y => counter_delta_snapshot_e7_i_a2_0); - - \counter_delta_f0_RNIIGF73[20]\ : OR2 - port map(A => \counter_delta_f0[20]_net_1\, B => N_106, Y - => N_58); - - \counter_delta_snapshot_RNIGDK[4]\ : NOR3 - port map(A => \counter_delta_snapshot[10]_net_1\, B => - \counter_delta_snapshot[4]_net_1\, C => - \counter_delta_snapshot[9]_net_1\, Y => - counter_delta_snapshot_e12_i_0_o2_m6_e_4); - - \counter_delta_snapshot[4]\ : DFN1C0 - port map(D => N_375_i_0, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[4]_net_1\); - - \counter_delta_snapshot_RNO[24]\ : OAI1 - port map(A => N_405, B => N_504, C => - counter_delta_snapshot_e24_0_0_0, Y => - counter_delta_snapshot_e24); - - \counter_delta_snapshot[15]\ : DFN1P0 - port map(D => N_8_i_0, CLK => lclk_c, PRE => rstn, Q => - \counter_delta_snapshot_i[15]\); - - \counter_delta_snapshot_RNO_1[1]\ : OA1B - port map(A => \counter_delta_snapshot[0]_net_1\, B => - un2_coarse_time_0, C => \counter_delta_snapshot[1]_net_1\, - Y => counter_delta_snapshot_e1_i_0); - - \counter_delta_snapshot_RNI5NB[1]\ : NOR2 - port map(A => \counter_delta_snapshot[1]_net_1\, B => - \counter_delta_snapshot[0]_net_1\, Y => N_382); - - \counter_delta_snapshot_RNO_3[2]\ : OA1C - port map(A => N_406_0, B => - \counter_delta_snapshot_0[26]_net_1\, C => - counter_delta_snapshot_e2_i_a2_0, Y => N_239); - - \counter_delta_snapshot_RNI4I74[19]\ : OR3 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => - \counter_delta_snapshot[19]_net_1\, Y => N_400); - - \counter_delta_f0[9]\ : DFN1E0C0 - port map(D => N_17, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[9]_net_1\); - - \counter_delta_snapshot_RNO[0]\ : OA1C - port map(A => \counter_delta_snapshot[0]_net_1\, B => - N_504_0, C => counter_delta_snapshot_e0_i_0, Y => - \counter_delta_snapshot_RNO[0]_net_1\); - - \counter_delta_f0_RNIR3VD2[13]\ : OR2 - port map(A => \counter_delta_f0[13]_net_1\, B => N_99, Y - => N_100); - - \counter_delta_f0_RNIANJH2[14]\ : OR2 - port map(A => \counter_delta_f0[14]_net_1\, B => N_100, Y - => N_101); - - \counter_delta_snapshot_RNO_2[20]\ : OR3 - port map(A => N_400, B => - \counter_delta_snapshot[20]_net_1\, C => N_504, Y => - N_182); - - \counter_delta_f0_RNIP7MC[6]\ : OR2 - port map(A => \counter_delta_f0[7]_net_1\, B => - \counter_delta_f0[6]_net_1\, Y => - counter_delta_f0_1_0_a2_7); - - \counter_delta_snapshot_RNO_4[5]\ : NOR2B - port map(A => \counter_delta_snapshot_i[5]\, B => N_385, Y - => counter_delta_snapshot_e5_i_a2_0); - - \counter_delta_snapshot_RNO_1[18]\ : OR2B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[18]_net_1\, Y => N_175); - - \op_eq.start_snapshot_f12_0_a2\ : AND2 - port map(A => N_322, B => start_snapshot_f12_0_a2_8, Y => - start_snapshot_f12); - - \counter_delta_f0_RNO_0[9]\ : XNOR2 - port map(A => \counter_delta_f0[9]_net_1\, B => N_63, Y => - N_324_i); - - \counter_delta_snapshot_RNIVEJ5[25]\ : NOR2 - port map(A => \counter_delta_snapshot[25]_net_1\, B => - N_405, Y => N_406); - - \op_eq.start_snapshot_f12_0_a2_RNO_11\ : XNOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => - delta_f2_f1(5), Y => N_113_i_i_0); - - \counter_delta_snapshot[11]\ : DFN1P0 - port map(D => N_22_i_0, CLK => lclk_c, PRE => rstn, Q => - \counter_delta_snapshot_i[11]\); - - \counter_delta_snapshot_RNO_4[9]\ : OR2 - port map(A => \counter_delta_snapshot[9]_net_1\, B => N_389, - Y => counter_delta_snapshot_e9_i_a2_0); - - \counter_delta_f0_RNO_0[5]\ : XOR2 - port map(A => \counter_delta_f0[5]_net_1\, B => N_55, Y => - N_117_i_i); - - \counter_delta_f0_RNIRTBT3[3]\ : OR3C - port map(A => un1_start_snapshot_f22_i_a2_0_4, B => - un1_start_snapshot_f22_i_a2_0_5, C => - counter_delta_f0lde_i_a2_0_1_3, Y => - counter_delta_f0lde_i_a2_0_1_i); - - \counter_delta_snapshot_RNO_1[8]\ : AO1A - port map(A => \counter_delta_snapshot[8]_net_1\, B => - un2_coarse_time_0_0, C => N_465, Y => - counter_delta_snapshot_e8_i_0); - - \counter_delta_f0_RNI59VI[2]\ : OR3 - port map(A => \counter_delta_f0[0]_net_1\, B => - \counter_delta_f0[1]_net_1\, C => - \counter_delta_f0[2]_net_1\, Y => N_89); - - \op_eq.start_snapshot_f12_0_a2_RNO_12\ : XNOR2 - port map(A => \counter_delta_f0[3]_net_1\, B => - delta_f2_f1(3), Y => N_111_i_i_0); - - \counter_delta_snapshot_RNO_2[5]\ : OR3 - port map(A => N_385, B => \counter_delta_snapshot_i[5]\, C - => N_504, Y => N_453); - - \counter_delta_snapshot_RNO[11]\ : OR3C - port map(A => N_501, B => counter_delta_snapshot_e11_i_0_0, - C => N_503, Y => N_22_i_0); - - \counter_delta_snapshot[18]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[18]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[18]_net_1\); - - \op_eq.start_snapshot_f12_0_a2_RNO_4\ : NOR3C - port map(A => N_82_i_i_0, B => N_81_i_i_0, C => - start_snapshot_f12_0_a2_1, Y => start_snapshot_f12_0_a2_5); - - \counter_delta_snapshot_RNO_2[2]\ : NOR3B - port map(A => N_382, B => \counter_delta_snapshot[2]_net_1\, - C => N_504, Y => N_438); - - \counter_delta_snapshot[13]\ : DFN1C0 - port map(D => N_26_i_0, CLK => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[13]_net_1\); - - \counter_delta_snapshot_RNO_2[4]\ : OR3A - port map(A => \counter_delta_snapshot[4]_net_1\, B => N_384, - C => N_504, Y => N_448); - - \counter_delta_snapshot_RNIL5P3[17]\ : OR3 - port map(A => N_396, B => - \counter_delta_snapshot[16]_net_1\, C => - \counter_delta_snapshot[17]_net_1\, Y => N_398); - - \counter_delta_snapshot_RNIS3O3[14]\ : XA1A - port map(A => delta_snapshot(14), B => - \counter_delta_snapshot[14]_net_1\, C => N_136_i_i, Y => - un12_start_snapshot_fothers_temp_NE_1); - - \counter_delta_f0_RNO[17]\ : XA1A - port map(A => \counter_delta_f0[17]_net_1\, B => N_103, C - => N_57, Y => counter_delta_f0_n17); - - \counter_delta_snapshot_RNO_0[23]\ : AOI1B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[23]_net_1\, C => N_189, Y => - counter_delta_snapshot_e23_0_0_0); - - \counter_delta_f0_RNO[13]\ : XA1A - port map(A => \counter_delta_f0[13]_net_1\, B => N_99, C - => N_57_0, Y => counter_delta_f0_n13); - - \counter_delta_snapshot_RNO_0[13]\ : OR2 - port map(A => N_505, B => delta_snapshot(13), Y => N_287); - - \counter_delta_snapshot_RNO[8]\ : NOR3 - port map(A => N_467, B => counter_delta_snapshot_e8_i_0, C - => N_468, Y => \counter_delta_snapshot_RNO[8]_net_1\); - - \counter_delta_f0_RNO[0]\ : MX2B - port map(A => delta_f2_f0(0), B => - \counter_delta_f0[0]_net_1\, S => N_57_0, Y => N_21); - - \counter_delta_snapshot[1]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[1]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[1]_net_1\); - - \counter_delta_f0[22]\ : DFN1E0C0 - port map(D => N_277, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[22]_net_1\); - - \counter_delta_snapshot_RNO_0[25]\ : OR2B - port map(A => N_405, B => - \counter_delta_snapshot[25]_net_1\, Y => N_421); - - \counter_delta_snapshot_RNO_0[15]\ : OR2 - port map(A => N_505, B => delta_snapshot(15), Y => N_480); - - \counter_delta_snapshot_RNIFJ31[15]\ : XOR2 - port map(A => \counter_delta_snapshot_i[15]\, B => - delta_snapshot(15), Y => - \counter_delta_snapshot_RNIFJ31[15]_net_1\); - - \counter_delta_snapshot_RNO_0[24]\ : AOI1B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[24]_net_1\, C => N_192, Y => - counter_delta_snapshot_e24_0_0_0); - - start_snapshot_f2_temp_RNI2715 : OR3B - port map(A => start_snapshot_f22_0_a2_11_0_a2_4, B => - start_snapshot_f22_0_a2_11_0_a2_5, C => - start_snapshot_f22_0_a2_0, Y => start_snapshot_f22_0_a2_1); - - \counter_delta_snapshot_RNO_0[14]\ : OR2 - port map(A => N_505, B => delta_snapshot(14), Y => N_486); - - start_snapshot_fothers_temp_RNO : NOR2 - port map(A => start_snapshot_f22, B => - counter_delta_f0lde_i_a2_0_1_i, Y => N_284); - - \counter_delta_snapshot_RNIM672[11]\ : XA1 - port map(A => delta_snapshot(11), B => - \counter_delta_snapshot_i[11]\, C => - \counter_delta_snapshot_RNIFJ31[15]_net_1\, Y => - un12_start_snapshot_fothers_temp_NE_3); - - \counter_delta_snapshot_RNIUFH7[1]\ : NOR3C - port map(A => N_507_i, B => N_137_i_i, C => - un12_start_snapshot_fothers_temp_NE_3, Y => - un12_start_snapshot_fothers_temp_NE_9); - - \counter_delta_f0_RNIK9132[10]\ : OR2A - port map(A => N_65, B => \counter_delta_f0[10]_net_1\, Y - => N_67); - - \counter_delta_snapshot_RNO[16]\ : OR3C - port map(A => N_168, B => N_169, C => N_170, Y => - \counter_delta_snapshot_RNO[16]_net_1\); - - \counter_delta_f0[7]\ : DFN1E0C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[7]_net_1\); - - \counter_delta_snapshot_RNO_0[21]\ : AOI1B - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[21]_net_1\, C => N_183, Y => - counter_delta_snapshot_e21_0_0_0); - - \counter_delta_f0[5]\ : DFN1E0C0 - port map(D => N_230, CLK => lclk_c, CLR => rstn, E => N_9, - Q => \counter_delta_f0[5]_net_1\); - - coarse_time_0_r : DFN1P0 - port map(D => coarse_time_i(0), CLK => lclk_c, PRE => rstn, - Q => coarse_time_0_r_i); - - \counter_delta_snapshot_RNO_4[4]\ : NOR2A - port map(A => N_384, B => \counter_delta_snapshot[4]_net_1\, - Y => counter_delta_snapshot_e4_i_a2_0); - - \counter_delta_snapshot_RNO_3[6]\ : OA1C - port map(A => N_406, B => - \counter_delta_snapshot[26]_net_1\, C => - counter_delta_snapshot_e6_i_a2_0, Y => N_455); - - \counter_delta_f0[10]\ : DFN1E0C0 - port map(D => N_19, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[10]_net_1\); - - \counter_delta_snapshot_RNO_0[11]\ : OR2 - port map(A => N_505, B => delta_snapshot(11), Y => N_501); - - \counter_delta_f0_RNO[6]\ : MX2 - port map(A => delta_f2_f0(6), B => N_87_i_i, S => N_57, Y - => N_11); - - \counter_delta_snapshot[5]\ : DFN1P0 - port map(D => N_376_i_0, CLK => lclk_c, PRE => rstn, Q => - \counter_delta_snapshot_i[5]\); - - \counter_delta_snapshot_RNO_3[4]\ : AO1C - port map(A => \counter_delta_snapshot_0[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e4_i_a2_0, Y => - N_445); - - \counter_delta_snapshot_RNO_2[18]\ : OR3 - port map(A => N_398, B => - \counter_delta_snapshot[18]_net_1\, C => N_504, Y => - N_176); - - \counter_delta_snapshot[0]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[0]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[0]_net_1\); - - \counter_delta_f0_RNI6F97[26]\ : OR2 - port map(A => \counter_delta_f0[26]_net_1\, B => - \counter_delta_f0[24]_net_1\, Y => - counter_delta_f0_1_0_a2_0); - - \op_eq.start_snapshot_f12_0_a2_RNO_0\ : NOR3C - port map(A => N_108_i_i_0, B => N_84_i_i_0, C => - start_snapshot_f12_0_a2_5, Y => start_snapshot_f12_0_a2_7); - - \counter_delta_snapshot[7]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[7]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[7]_net_1\); - - \counter_delta_snapshot_RNO_1[13]\ : OA1A - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[13]_net_1\, C => N_285, Y => - counter_delta_snapshot_e13_i_0_0); - - \counter_delta_snapshot_RNO_2[9]\ : NOR3B - port map(A => N_389, B => \counter_delta_snapshot[9]_net_1\, - C => N_504_0, Y => N_472); - - start_snapshot_fothers_temp_RNIB7FD1_0 : OAI1 - port map(A => start_snapshot_f22, B => - \start_snapshot_fothers_temp\, C => sample_f2_val, Y => - N_57_0); - - \counter_delta_f0_RNO[12]\ : XA1A - port map(A => \counter_delta_f0[12]_net_1\, B => N_98, C - => N_57_0, Y => counter_delta_f0_n12); - - \counter_delta_snapshot[9]\ : DFN1C0 - port map(D => \counter_delta_snapshot_RNO[9]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_delta_snapshot[9]_net_1\); - - \counter_delta_snapshot_RNO_1[15]\ : AOI1B - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot_i[15]\, C => N_478, Y => - counter_delta_snapshot_e15_i_0_0); - - \counter_delta_snapshot_RNO[10]\ : NOR3 - port map(A => N_476, B => counter_delta_snapshot_e10_i_0, C - => N_477, Y => \counter_delta_snapshot_RNO[10]_net_1\); - - \counter_delta_f0[11]\ : DFN1E0C0 - port map(D => N_275, CLK => lclk_c, CLR => rstn, E => N_9_0, - Q => \counter_delta_f0[11]_net_1\); - - \counter_delta_snapshot_RNO_0[22]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406_0, C => counter_delta_snapshot_e22_0_0_a2_0, Y => - N_186); - - \counter_delta_f0_RNIKE2M3[24]\ : OR2 - port map(A => \counter_delta_f0[24]_net_1\, B => N_64, Y - => N_66); - - \counter_delta_snapshot_RNO_0[12]\ : OR2 - port map(A => N_505, B => delta_snapshot(12), Y => N_496); - - \counter_delta_snapshot_RNO[15]\ : OR3C - port map(A => N_480, B => counter_delta_snapshot_e15_i_0_0, - C => N_482, Y => N_8_i_0); - - \counter_delta_snapshot_RNO_1[14]\ : OA1A - port map(A => un2_coarse_time_0_0, B => - \counter_delta_snapshot[14]_net_1\, C => N_484, Y => - counter_delta_snapshot_e14_i_0_0); - - start_snapshot_fothers_temp_RNIB7FD1 : OAI1 - port map(A => start_snapshot_f22, B => - \start_snapshot_fothers_temp\, C => sample_f2_val, Y => - N_57); - - \counter_delta_snapshot_RNO_0[19]\ : AOI1B - port map(A => un2_coarse_time_0, B => - \counter_delta_snapshot[19]_net_1\, C => N_177, Y => - counter_delta_snapshot_e19_i_i_0); - - \counter_delta_f0[26]\ : DFN1E0C0 - port map(D => N_34, CLK => lclk_c, CLR => rstn, E => N_9, Q - => \counter_delta_f0[26]_net_1\); - - \counter_delta_snapshot_RNO_4[6]\ : OR2A - port map(A => N_386, B => \counter_delta_snapshot[6]_net_1\, - Y => counter_delta_snapshot_e6_i_a2_0); - - \counter_delta_snapshot_RNO[13]\ : NOR3C - port map(A => N_287, B => counter_delta_snapshot_e13_i_0_0, - C => N_288, Y => N_26_i_0); - - \counter_delta_snapshot_RNO_0[7]\ : NOR2 - port map(A => N_505, B => delta_snapshot(7), Y => N_462); - - \counter_delta_snapshot_RNO_0[16]\ : AO1C - port map(A => \counter_delta_snapshot[26]_net_1\, B => - N_406, C => counter_delta_snapshot_e16_i_i_a2_0, Y => - N_168); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ is - - port( status_new_err : out std_logic_vector(3 to 3); - valid_ack : in std_logic_vector(3 to 3); - valid_out : out std_logic_vector(3 to 3); - rstn : in std_logic; - lclk_c : in std_logic; - data_f3_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1_i, N_6_i_i_0, \valid_out[3]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(3) <= \valid_out[3]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1_i, CLK => lclk_c, CLR => - rstn, Q => status_new_err(3)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => lclk_c, CLR => rstn, Q => - \valid_out[3]\); - - error_RNO : NOR3B - port map(A => \valid_out[3]\, B => data_f3_out_valid, C => - valid_ack(3), Y => state_1_sqmuxa_1_i); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(3), B => \valid_out[3]\, C => - data_f3_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ is - - port( status_new_err : out std_logic_vector(1 to 1); - valid_out_i : out std_logic_vector(1 to 1); - valid_ack : in std_logic_vector(1 to 1); - rstn : in std_logic; - lclk_c : in std_logic; - data_f1_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out_i[1]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out_i(1) <= \valid_out_i[1]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => lclk_c, CLR => rstn, - Q => status_new_err(1)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1P0 - port map(D => N_6_i_i_0, CLK => lclk_c, PRE => rstn, Q => - \valid_out_i[1]\); - - error_RNO : NOR3A - port map(A => data_f1_out_valid, B => valid_ack(1), C => - \valid_out_i[1]\, Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1D - port map(A => valid_ack(1), B => \valid_out_i[1]\, C => - data_f1_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_burst is - - port( sample_f3_wdata : in std_logic_vector(95 downto 0); - data_f3_out : out std_logic_vector(159 downto 64); - rstn : in std_logic; - lclk_c : in std_logic; - data_f3_out_valid : out std_logic; - enable_f3 : in std_logic; - sample_f3_val : in std_logic - ); - -end lpp_waveform_burst; - -architecture DEF_ARCH of lpp_waveform_burst is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal data_out_valid_3, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - \data_out[91]\ : DFN1C0 - port map(D => sample_f3_wdata(27), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(91)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f3_wdata(60), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(124)); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f3_wdata(56), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(120)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f3_wdata(74), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(138)); - - \data_out[105]\ : DFN1C0 - port map(D => sample_f3_wdata(41), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(105)); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f3_wdata(62), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(126)); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f3_wdata(10), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(74)); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f3_wdata(90), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(154)); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f3_wdata(86), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(150)); - - \data_out[102]\ : DFN1C0 - port map(D => sample_f3_wdata(38), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(102)); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f3_wdata(92), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(156)); - - \data_out[93]\ : DFN1C0 - port map(D => sample_f3_wdata(29), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(93)); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f3_wdata(64), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(128)); - - data_out_valid : DFN1C0 - port map(D => data_out_valid_3, CLK => lclk_c, CLR => rstn, - Q => data_f3_out_valid); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f3_wdata(5), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(69)); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f3_wdata(77), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(141)); - - \data_out[99]\ : DFN1C0 - port map(D => sample_f3_wdata(35), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(99)); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f3_wdata(83), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(147)); - - \data_out[87]\ : DFN1C0 - port map(D => sample_f3_wdata(23), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(87)); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f3_wdata(85), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(149)); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_out[86]\ : DFN1C0 - port map(D => sample_f3_wdata(22), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(86)); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f3_wdata(94), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(158)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f3_wdata(49), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(113)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f3_wdata(1), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(65)); - - \data_out[95]\ : DFN1C0 - port map(D => sample_f3_wdata(31), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(95)); - - \data_out[92]\ : DFN1C0 - port map(D => sample_f3_wdata(28), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(92)); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f3_wdata(13), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(77)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f3_wdata(81), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(145)); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f3_wdata(67), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(131)); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f3_wdata(12), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(76)); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f3_wdata(73), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(137)); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f3_wdata(75), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(139)); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f3_wdata(50), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(114)); - - \data_out[80]\ : DFN1C0 - port map(D => sample_f3_wdata(16), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(80)); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f3_wdata(0), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(64)); - - \data_out[110]\ : DFN1C0 - port map(D => sample_f3_wdata(46), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(110)); - - \data_out[103]\ : DFN1C0 - port map(D => sample_f3_wdata(39), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(103)); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f3_wdata(78), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(142)); - - \data_out[94]\ : DFN1C0 - port map(D => sample_f3_wdata(30), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(94)); - - \data_out[88]\ : DFN1C0 - port map(D => sample_f3_wdata(24), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(88)); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f3_wdata(52), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(116)); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f3_wdata(57), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(121)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f3_wdata(63), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(127)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f3_wdata(65), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(129)); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f3_wdata(71), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(135)); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f3_wdata(6), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(70)); - - data_out_valid_RNO : NOR2B - port map(A => sample_f3_val, B => enable_f3, Y => - data_out_valid_3); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f3_wdata(54), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(118)); - - \data_out[104]\ : DFN1C0 - port map(D => sample_f3_wdata(40), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(104)); - - \data_out[100]\ : DFN1C0 - port map(D => sample_f3_wdata(36), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(100)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f3_wdata(14), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(78)); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f3_wdata(87), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(151)); - - GND_i : GND - port map(Y => \GND\); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f3_wdata(93), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(157)); - - \data_out[106]\ : DFN1C0 - port map(D => sample_f3_wdata(42), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(106)); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f3_wdata(95), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(159)); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f3_wdata(68), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(132)); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f3_wdata(61), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(125)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f3_wdata(3), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(67)); - - \data_out[81]\ : DFN1C0 - port map(D => sample_f3_wdata(17), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(81)); - - \data_out[97]\ : DFN1C0 - port map(D => sample_f3_wdata(33), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(97)); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f3_wdata(2), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(66)); - - \data_out[108]\ : DFN1C0 - port map(D => sample_f3_wdata(44), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(108)); - - \data_out[96]\ : DFN1C0 - port map(D => sample_f3_wdata(32), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(96)); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f3_wdata(79), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(143)); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f3_wdata(58), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(122)); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f3_wdata(91), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(155)); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f3_wdata(7), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(71)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f3_wdata(88), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(152)); - - \data_out[83]\ : DFN1C0 - port map(D => sample_f3_wdata(19), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(83)); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f3_wdata(80), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(144)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f3_wdata(76), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(140)); - - \data_out[111]\ : DFN1C0 - port map(D => sample_f3_wdata(47), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(111)); - - \data_out[90]\ : DFN1C0 - port map(D => sample_f3_wdata(26), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(90)); - - \data_out[89]\ : DFN1C0 - port map(D => sample_f3_wdata(25), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(89)); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f3_wdata(4), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(68)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f3_wdata(53), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(117)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f3_wdata(82), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(146)); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f3_wdata(69), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(133)); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f3_wdata(55), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(119)); - - \data_out[98]\ : DFN1C0 - port map(D => sample_f3_wdata(34), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(98)); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f3_wdata(9), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(73)); - - \data_out[85]\ : DFN1C0 - port map(D => sample_f3_wdata(21), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(85)); - - \data_out[82]\ : DFN1C0 - port map(D => sample_f3_wdata(18), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(82)); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f3_wdata(15), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(79)); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f3_wdata(84), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(148)); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f3_wdata(59), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(123)); - - \data_out[101]\ : DFN1C0 - port map(D => sample_f3_wdata(37), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(101)); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f3_wdata(70), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(134)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f3_wdata(51), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(115)); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f3_wdata(66), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(130)); - - \data_out[107]\ : DFN1C0 - port map(D => sample_f3_wdata(43), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(107)); - - \data_out[109]\ : DFN1C0 - port map(D => sample_f3_wdata(45), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(109)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f3_wdata(72), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(136)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[84]\ : DFN1C0 - port map(D => sample_f3_wdata(20), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(84)); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f3_wdata(11), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(75)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f3_wdata(8), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(72)); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f3_wdata(89), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(153)); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f3_wdata(48), CLK => lclk_c, CLR => - rstn, Q => data_f3_out(112)); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ is - - port( status_new_err : out std_logic_vector(2 to 2); - valid_ack : in std_logic_vector(2 to 2); - valid_out : out std_logic_vector(2 to 2); - rstn : in std_logic; - lclk_c : in std_logic; - data_f2_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out[2]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(2) <= \valid_out[2]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => lclk_c, CLR => rstn, - Q => status_new_err(2)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => lclk_c, CLR => rstn, Q => - \valid_out[2]\); - - error_RNO : NOR3B - port map(A => \valid_out[2]\, B => data_f2_out_valid, C => - valid_ack(2), Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(2), B => \valid_out[2]\, C => - data_f2_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ is - - port( status_new_err : out std_logic_vector(0 to 0); - valid_ack : in std_logic_vector(0 to 0); - valid_out : out std_logic_vector(0 to 0); - rstn : in std_logic; - lclk_c : in std_logic; - data_f0_out_valid : in std_logic - ); - -end - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\; - -architecture DEF_ARCH of - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ is - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal state_1_sqmuxa_1, N_6_i_i_0, \valid_out[0]\, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - valid_out(0) <= \valid_out[0]\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - error : DFN1C0 - port map(D => state_1_sqmuxa_1, CLK => lclk_c, CLR => rstn, - Q => status_new_err(0)); - - VCC_i : VCC - port map(Y => \VCC\); - - \state[0]\ : DFN1C0 - port map(D => N_6_i_i_0, CLK => lclk_c, CLR => rstn, Q => - \valid_out[0]\); - - error_RNO : NOR3B - port map(A => \valid_out[0]\, B => data_f0_out_valid, C => - valid_ack(0), Y => state_1_sqmuxa_1); - - \state_RNO[0]\ : AX1 - port map(A => valid_ack(0), B => \valid_out[0]\, C => - data_f0_out_valid, Y => N_6_i_i_0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ1 is - - port( ready_i_0_i_0 : out std_logic_vector(1 to 1); - data_mem_wen_i_0 : out std_logic_vector(1 to 1); - data_ren : in std_logic_vector(1 to 1); - data_mem_ren_i_0 : out std_logic_vector(1 to 1); - data_wen : in std_logic_vector(1 to 1); - data_mem_addr_r_1 : out std_logic_vector(4 downto 0); - data_mem_addr_w_1 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - N_158 : in std_logic; - sFull_RNIE8AH1 : out std_logic; - sEmpty_RNI6M6A4J_0 : in std_logic; - sEmpty_RNIU5CB661 : out std_logic; - un20_time_write : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ1; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ1 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, N_4, \DWACT_FINC_E[0]\, N_12_0, N_4_0, - \DWACT_FINC_E_0[0]\, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \data_mem_addr_w_1[3]\, - \un10_raddr_vect_s[3]\, sEmpty_RNO_6_2, - \data_mem_addr_w_1[1]\, \un10_raddr_vect_s[1]\, - sEmpty_RNO_5_1, \data_mem_addr_w_1[0]\, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \data_mem_addr_r_1[3]\, \un8_waddr_vect_s[3]\, - sFull_RNO_8_0, un5_sfull_s_4_1, \data_mem_addr_r_1[1]\, - \un8_waddr_vect_s[1]\, sFull_RNO_5_1, un5_sfull_s_4_0, - \data_mem_addr_r_1[0]\, \un8_waddr_vect_s[0]\, - ADD_7x7_fast_I23_Y_0_o2_0, N165_1, N_89_i, N_73, - ADD_5x5_fast_I17_un1_Y_1, N130, ADD_5x5_fast_I13_Y_0, - ADD_5x5_fast_I17_un1_Y_0, ADD_5x5_fast_I5_un1_Y_0, - ADD_5x5_fast_I11_Y_0, N80, N91, N94, N_84_1, - ADD_7x7_fast_I19_Y_i_o4_1_0, N_72, - ADD_5x5_fast_I9_un1_Y_0, un1_waddr_vect_slto3_0, - \data_mem_addr_w_1[2]\, \data_mem_addr_r_1[2]\, - un2_raddr_vect_slto3_0, I11_un1_Y, N81, N77, N98, - un5_sfull_s_4, N_11, \sEmpty\, Waddr_vect_n4, - Waddr_vect_14_0, un1_waddr_vect_s, Waddr_vect_c2, - Waddr_vect_n3, Waddr_vect_n2, Waddr_vect_c1_i_0, - sFull_RNO_12, \sFull\, I_5_28, I_13_32, I_9_28, I_20_20, - N_71, N165, Waddr_vect_n1_i, Waddr_vect_e1, Waddr_vect_e0, - \data_mem_wen_i_0[1]\, un2_raddr_vect_s, I_5_29, - \un10_raddr_vect_s[2]\, I_9_29, I_13_33, - \un10_raddr_vect_s[4]\, I_20_21, \data_mem_addr_w_1[4]\, - \data_mem_ren_i_0[1]\, un2_raddr_vect_slto1, - \data_mem_addr_r_1[4]\, Waddr_vect_e4, Waddr_vect_e3, - Waddr_vect_e2, sEmpty_RNO_12, un1_sempty_s, N_75_1, - \un75_ready1[4]\, N111, \un75_ready0[4]\, un62_readylto4, - un77_ready, un69_ready, N_166, N107, N161, N_165, - \un75_ready1[5]\, N_16_i_i_0, N_164, N_24, I12_un1_Y, N87, - N102, N_9, N_13, N_12_1, N_11_0, N_8, N_10, N_9_0, N_7, - N_4_1, N_5, N_6, N_9_1, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - data_mem_wen_i_0(1) <= \data_mem_wen_i_0[1]\; - data_mem_ren_i_0(1) <= \data_mem_ren_i_0[1]\; - data_mem_addr_r_1(4) <= \data_mem_addr_r_1[4]\; - data_mem_addr_r_1(3) <= \data_mem_addr_r_1[3]\; - data_mem_addr_r_1(2) <= \data_mem_addr_r_1[2]\; - data_mem_addr_r_1(1) <= \data_mem_addr_r_1[1]\; - data_mem_addr_r_1(0) <= \data_mem_addr_r_1[0]\; - data_mem_addr_w_1(4) <= \data_mem_addr_w_1[4]\; - data_mem_addr_w_1(3) <= \data_mem_addr_w_1[3]\; - data_mem_addr_w_1(2) <= \data_mem_addr_w_1[2]\; - data_mem_addr_w_1(1) <= \data_mem_addr_w_1[1]\; - data_mem_addr_w_1(0) <= \data_mem_addr_w_1[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => N_9_1); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4 : OR2A - port map(A => N165_1, B => N80, Y => N165); - - \Waddr_vect_RNIVSRF[3]\ : NOR2 - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_w_1[2]\, Y => un1_waddr_vect_slto3_0); - - \ready_gen.un69_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_1[4]\, B => - \data_mem_addr_r_1[4]\, Y => N_11_0); - - \ready_gen.un69_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, Y => N_5); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXOI5 - port map(A => N_72, B => \data_mem_addr_r_1[2]\, C => - \data_mem_addr_w_1[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - un60_ready_0_0_ADD_5x5_fast_I1_G0N : OR2A - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_r_1[1]\, Y => N87); - - un60_ready_0_0_ADD_5x5_fast_I17_un1_Y_1 : OA1 - port map(A => N130, B => ADD_5x5_fast_I13_Y_0, C => - ADD_5x5_fast_I17_un1_Y_0, Y => ADD_5x5_fast_I17_un1_Y_1); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, C => \data_mem_addr_r_1[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, Y => N_12); - - un60_ready_0_0_ADD_5x5_fast_I2_P0N : OR2A - port map(A => \data_mem_addr_r_1[2]\, B => - \data_mem_addr_w_1[2]\, Y => N91); - - sEmpty_RNO : AO1A - port map(A => data_ren(1), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_12); - - \Raddr_vect_RNIKT47[4]\ : NOR2B - port map(A => I_20_21, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[3]\); - - un75_ready_0_0_0_ADD_7x7_fast_I20_Y_i_o2_0 : AO13 - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, C => \data_mem_addr_r_1[1]\, Y - => N_11); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_1[2]\, Y => - I_9_29); - - \Raddr_vect_RNI7MARL[0]\ : MX2 - port map(A => un62_readylto4, B => un77_ready, S => - un69_ready, Y => ready_i_0_i_0(1)); - - \Raddr_vect_RNIAB94[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_1[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Waddr_vect_RNO[4]\ : MX2B - port map(A => \data_mem_addr_w_1[4]\, B => Waddr_vect_n4, S - => \data_mem_wen_i_0[1]\, Y => Waddr_vect_e4); - - un75_ready_1_16_ADD_5x5_fast_I1_P0N : OR2A - port map(A => N_71, B => N_72, Y => N81); - - un75_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : XOR3 - port map(A => N_73, B => N_89_i, C => N165, Y => - \un75_ready0[4]\); - - \sFull_RNIE8AH1\ : OR2A - port map(A => N_158, B => \data_mem_wen_i_0[1]\, Y => - sFull_RNIE8AH1); - - \ready_gen.un69_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, Y => N_4_1); - - un75_ready_1_16_ADD_5x5_fast_I10_Y : AO1B - port map(A => N111, B => N98, C => N_75_1, Y => N107); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_12, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Raddr_vect_RNI5RK8_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_1[4]\, B => - \data_mem_addr_w_1[4]\, Y => N_75_1); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[1]\, - C => \data_mem_addr_w_1[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[2]\); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \data_mem_addr_w_1[1]\, B => Waddr_vect_n1_i, - S => \data_mem_wen_i_0[1]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AO1 - port map(A => N165_1, B => N_89_i, C => N_73, Y => - ADD_7x7_fast_I23_Y_0_o2_0); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : OR2A - port map(A => N165, B => N_89_i, Y => N_24); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_1[2]\, B => - Waddr_vect_c1_i_0, C => un1_waddr_vect_s, Y => - Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, Y => I_5_28); - - \Raddr_vect_RNI01E6[4]\ : NOR2B - port map(A => I_13_33, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - \Waddr_vect_RNIRSRF[0]\ : OR2B - port map(A => \data_mem_addr_w_1[1]\, B => - \data_mem_addr_w_1[0]\, Y => Waddr_vect_c1_i_0); - - un75_ready_1_16_ADD_5x5_fast_I1_G0N : NOR2A - port map(A => N_72, B => N_71, Y => N80); - - un60_ready_0_0_ADD_5x5_fast_I0_P0N : NOR2A - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_w_1[0]\, Y => N130); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[3]\); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_1[1]\, B => - \un10_raddr_vect_s[1]\, C => sEmpty_RNO_5_1, Y => - un7_sempty_s_1); - - un75_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO13 - port map(A => N_89_i, B => N_73, C => N80, Y => - ADD_5x5_fast_I11_Y_0); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_1[3]\, Y => - I_13_32); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(1), - Y => sFull_RNO_12); - - \Raddr_vect_RNI5PD1[3]\ : NOR2 - port map(A => \data_mem_addr_r_1[3]\, B => - \data_mem_addr_r_1[2]\, Y => un2_raddr_vect_slto3_0); - - un60_ready_0_0_ADD_5x5_fast_I12_un1_Y : OR3B - port map(A => N91, B => N94, C => N102, Y => I12_un1_Y); - - \ready_gen.un69_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, C => N_5, Y => N_9_0); - - sFull_RNO_4 : OR2B - port map(A => I_5_28, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - un60_ready_0_0_ADD_5x5_fast_I13_Y_0 : OR3C - port map(A => N91, B => N94, C => N_84_1, Y => - ADD_5x5_fast_I13_Y_0); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_1[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_1[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(1), Y => - un7_sempty_s_0); - - un60_ready_0_0_ADD_5x5_fast_I25_Y_0 : AX1E - port map(A => I12_un1_Y, B => ADD_5x5_fast_I17_un1_Y_1, C - => N_89_i, Y => un62_readylto4); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[2]\); - - \ready_gen.un69_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, C => N_6, Y => N_8); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[0]\); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_20, C => - \data_mem_addr_r_1[4]\, Y => sFull_RNO_8_0); - - sFull_RNIDOE8 : NOR2 - port map(A => \sFull\, B => data_wen(1), Y => - \data_mem_wen_i_0[1]\); - - \sEmpty_RNIU5CB661\ : OR2A - port map(A => sEmpty_RNI6M6A4J_0, B => - \data_mem_ren_i_0[1]\, Y => sEmpty_RNIU5CB661); - - \Raddr_vect_RNI5RK8[4]\ : XNOR2 - port map(A => \data_mem_addr_w_1[4]\, B => - \data_mem_addr_r_1[4]\, Y => N_89_i); - - un75_ready_1_16_ADD_5x5_fast_I15_Y_0 : XOR3 - port map(A => N_73, B => N_89_i, C => N111, Y => - \un75_ready1[4]\); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_1[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - \Raddr_vect_RNIIUK5G[0]\ : AOI1 - port map(A => N_165, B => N_164, C => N_166, Y => - un77_ready); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_28, C => - \data_mem_addr_r_1[2]\, Y => sFull_RNO_5_1); - - \Raddr_vect_RNIR705[4]\ : NOR2B - port map(A => I_5_29, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \data_mem_addr_w_1[2]\, B => Waddr_vect_n2, S - => \data_mem_wen_i_0[1]\, Y => Waddr_vect_e2); - - un75_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75_1, Y => N_16_i_i_0); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_1[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_6_2, Y => - un7_sempty_s_2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_1[3]\, Y - => Waddr_vect_14_0); - - \Waddr_vect_RNIBOL71[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => - Waddr_vect_c1_i_0, C => \data_mem_addr_w_1[4]\, Y => - un1_waddr_vect_s); - - \Waddr_vect_RNIARPN[2]\ : NOR2A - port map(A => \data_mem_addr_w_1[2]\, B => - Waddr_vect_c1_i_0, Y => Waddr_vect_c2); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_1[3]\, B => - \un8_waddr_vect_s[3]\, C => sFull_RNO_8_0, Y => - un5_sfull_s_4_2); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - un75_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_89_i, B => N_73, Y => N98); - - un75_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR3C - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75_1, Y => N161); - - un75_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1 : OR2B - port map(A => ADD_7x7_fast_I19_Y_i_o4_1_0, B => N_11, Y => - N165_1); - - \Raddr_vect_RNIOQ3P3[0]\ : MX2C - port map(A => \un75_ready1[4]\, B => \un75_ready0[4]\, S - => \data_mem_addr_r_1[0]\, Y => N_164); - - \Raddr_vect_RNI1RK8[2]\ : NOR2A - port map(A => \data_mem_addr_r_1[2]\, B => - \data_mem_addr_w_1[2]\, Y => N_71); - - \ready_gen.un69_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_w_1[0]\, Y => N_6); - - un60_ready_0_0_ADD_5x5_fast_I9_un1_Y_0 : NOR2B - port map(A => \data_mem_addr_w_1[0]\, B => N_84_1, Y => - ADD_5x5_fast_I9_un1_Y_0); - - \Raddr_vect_RNI3RK8[3]\ : XNOR2 - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, Y => N_72); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[0]\); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_r_1[0]\, Y => N_12_0); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_1[2]\, Y => - I_9_28); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_1[3]\, Y => - I_13_33); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, C => \data_mem_addr_r_1[2]\, Y - => N_9); - - un60_ready_0_0_ADD_5x5_fast_I9_Y : OA1A - port map(A => ADD_5x5_fast_I9_un1_Y_0, B => - \data_mem_addr_r_1[0]\, C => N87, Y => N102); - - un60_ready_0_0_ADD_5x5_fast_I3_G0N : OR2A - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, Y => N_73); - - \Raddr_vect_RNINRUK5[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_1[0]\, - Y => N_166); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(1), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_1[4]\, Y => - I_20_21); - - un60_ready_0_0_ADD_5x5_fast_I5_un1_Y_0 : NOR2A - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, Y => ADD_5x5_fast_I5_un1_Y_0); - - \Raddr_vect_RNID4N5[4]\ : NOR2B - port map(A => I_9_29, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - un75_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1 - port map(A => \data_mem_addr_r_1[2]\, B => - \data_mem_addr_w_1[2]\, C => N_84_1, Y => N77); - - un75_ready_1_16_ADD_5x5_fast_I8_Y : AO13 - port map(A => N77, B => N_72, C => N_71, Y => N111); - - un75_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75_1, Y => \un75_ready1[5]\); - - un60_ready_0_0_ADD_5x5_fast_I17_un1_Y_0 : AO18 - port map(A => ADD_5x5_fast_I5_un1_Y_0, B => - \data_mem_addr_r_1[3]\, C => \data_mem_addr_w_1[3]\, Y - => ADD_5x5_fast_I17_un1_Y_0); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_1[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_1, Y => - un5_sfull_s_4_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_1[0]\, B => - \data_mem_addr_r_1[1]\, Y => I_5_29); - - un75_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - \ready_gen.un69_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_1[4]\, B => - \data_mem_addr_w_1[4]\, Y => N_7); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_1[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[4]\); - - sFull_RNO_7 : OR2B - port map(A => I_13_32, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - un60_ready_0_0_ADD_5x5_fast_I3_P0N : OR2A - port map(A => \data_mem_addr_r_1[3]\, B => - \data_mem_addr_w_1[3]\, Y => N94); - - \Raddr_vect_RNIQEI3[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_1[4]\, Y => - un2_raddr_vect_s); - - \Raddr_vect_RNI1PD1[1]\ : OR2B - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_r_1[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect_RNO[3]\ : MX2B - port map(A => \data_mem_addr_w_1[3]\, B => Waddr_vect_n3, S - => \data_mem_wen_i_0[1]\, Y => Waddr_vect_e3); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_1[4]\, Y => sEmpty_RNO_6_2); - - sEmpty_RNIOF512J : NOR3 - port map(A => un20_time_write, B => \sEmpty\, C => - data_ren_1z, Y => \data_mem_ren_i_0[1]\); - - \Raddr_vect_RNI38IN6[0]\ : MX2C - port map(A => \un75_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_1[0]\, Y => N_165); - - sFull : DFN1C0 - port map(D => sFull_RNO_12, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \ready_gen.un69_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_1[2]\, B => - \data_mem_addr_r_1[2]\, C => N_4_1, Y => N_10); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_1[4]\, Y => - I_20_20); - - \ready_gen.un69_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13); - - un60_ready_0_0_ADD_5x5_fast_I1_P0N : OR2A - port map(A => \data_mem_addr_r_1[1]\, B => - \data_mem_addr_w_1[1]\, Y => N_84_1); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_1[1]\); - - \ready_gen.un69_ready_0_I_11\ : OA1 - port map(A => N_13, B => N_12_1, C => N_11_0, Y => - un69_ready); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[1]\, Q => - \data_mem_addr_r_1[4]\); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_1[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(1), Y => - un5_sfull_s_4_0); - - \ready_gen.un69_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_1[3]\, B => - \data_mem_addr_r_1[3]\, C => N_7, Y => N_12_1); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_1[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_1[2]\, Y => sEmpty_RNO_5_1); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_1[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_1[0]\, B => - \data_mem_addr_w_1[1]\, C => \data_mem_addr_w_1[2]\, Y - => \DWACT_FINC_E[0]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ7 is - - port( time_mem_wen_i_0 : out std_logic_vector(3 to 3); - time_mem_ren_i_0 : out std_logic_vector(3 to 3); - time_mem_addr_w_3_i_0_3 : out std_logic; - time_mem_addr_w_3_i_0_0 : out std_logic; - time_mem_addr_r_3_i_0_3 : out std_logic; - time_mem_addr_r_3_i_0_0 : out std_logic; - time_wen : in std_logic_vector(3 to 3); - time_ren : in std_logic_vector(3 to 3); - time_mem_addr_w_3_3 : out std_logic; - time_mem_addr_w_3_0 : out std_logic; - time_mem_addr_w_3_1 : out std_logic; - time_mem_addr_r_3_3 : out std_logic; - time_mem_addr_r_3_0 : out std_logic; - time_mem_addr_r_3_1 : out std_logic; - time_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - N_156 : in std_logic; - N_157 : out std_logic; - sFull_RNIODA01_0 : out std_logic; - N_117 : out std_logic; - un5_time_write : in std_logic; - N_89 : out std_logic; - N_88 : in std_logic; - N_37 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ7; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ7 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO6 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_7, N_7_0, \un10_sempty_s_3_0\, - \un10_raddr_vect_s[3]\, \Waddr_vect_i[3]\, - \un2_sfull_s_3_0\, \un8_waddr_vect_s[3]\, - \Raddr_vect_i[3]\, un7_sempty_s_2, un5_sfull_s_2, - un7_sempty_s_3, sEmpty_RNO_3_0, sEmpty_RNO_4_0, - un7_sempty_s_0, \un10_raddr_vect_s[0]\, - \time_mem_addr_w_3[0]\, un5_sfull_s_3, \sFull_RNO_3\, - \sFull_RNO_4\, un5_sfull_s_0, \un8_waddr_vect_s[0]\, - \time_mem_addr_r_3[0]\, un2_raddr_vect_slt3, - \time_mem_addr_r_3[1]\, un1_waddr_vect_slt3, - \time_mem_addr_w_3[1]\, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, - \time_mem_addr_w_3_i_0[2]\, \time_mem_addr_r_3_i_0[2]\, - Raddr_vect_n2, un2_raddr_vect_s, Raddr_vect_n2_tz, - Waddr_vect_n2, un1_waddr_vect_s, Waddr_vect_n2_tz, - \time_mem_ren_i_0[3]\, I_9_15, I_5_15, Raddr_vect_n1_i, - Raddr_vect_e2, Raddr_vect_e1, Raddr_vect_e0, I_13_19, - \sEmpty\, \time_mem_addr_r_3_i_0[5]\, I_9_14, I_5_14, - Waddr_vect_e2, I_13_18, \sFull_RNO\, un8_sfull_s, \sFull\, - \time_mem_addr_w_3_i_0[5]\, \time_mem_wen_i_0[3]\, - sFull_RNIODA01_0_net_1, un2_sempty_s, \sEmpty_RNO\, - Waddr_vect_e0, Waddr_vect_e1, Waddr_vect_n1_i, N_4, N_4_0, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - time_mem_wen_i_0(3) <= \time_mem_wen_i_0[3]\; - time_mem_ren_i_0(3) <= \time_mem_ren_i_0[3]\; - time_mem_addr_w_3_i_0_3 <= \time_mem_addr_w_3_i_0[5]\; - time_mem_addr_w_3_i_0_0 <= \time_mem_addr_w_3_i_0[2]\; - time_mem_addr_r_3_i_0_3 <= \time_mem_addr_r_3_i_0[5]\; - time_mem_addr_r_3_i_0_0 <= \time_mem_addr_r_3_i_0[2]\; - time_mem_addr_w_3_0 <= \time_mem_addr_w_3[0]\; - time_mem_addr_w_3_1 <= \time_mem_addr_w_3[1]\; - time_mem_addr_r_3_0 <= \time_mem_addr_r_3[0]\; - time_mem_addr_r_3_1 <= \time_mem_addr_r_3[1]\; - sFull_RNIODA01_0 <= sFull_RNIODA01_0_net_1; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_3[1]\, B => - \time_mem_addr_w_3[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => N_4); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_3[1]\, B => - \time_mem_addr_r_3[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - sFull_RNIODA01 : OR2B - port map(A => \time_mem_wen_i_0[3]\, B => N_156, Y => N_157); - - un43_mem_addr_ren_1_SUM1_0 : XNOR2 - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \Raddr_vect_i[3]\, Y => time_mem_addr_r_3_3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_3[1]\, B => - \time_mem_addr_w_3[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_3[1]\); - - \Waddr_vect[3]\ : DFN1E0P0 - port map(D => Waddr_vect_n3, CLK => lclk_c, PRE => rstn, E - => \time_mem_wen_i_0[3]\, Q => \Waddr_vect_i[3]\); - - sEmpty_RNI3SGD2 : NOR3A - port map(A => N_88, B => \time_mem_ren_i_0[3]\, C => - \time_mem_addr_r_3_i_0[5]\, Y => N_37); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \time_mem_addr_r_3_i_0[2]\, Y => - I_9_15); - - un2_sfull_s_3_0_RNO : OR2B - port map(A => I_13_18, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO\, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[3]\, - C => \time_mem_addr_w_3[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_3_i_0[2]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_3[1]\, - S => \time_mem_wen_i_0[3]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, Y => I_5_14); - - sFull_RNIK4V7 : OR2 - port map(A => time_wen(3), B => \sFull\, Y => - \time_mem_wen_i_0[3]\); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - \Waddr_vect_RNIQ6UJ[3]\ : OR2A - port map(A => un1_waddr_vect_slt3, B => \Waddr_vect_i[3]\, - Y => un1_waddr_vect_s); - - \Waddr_vect_RNI2LUE[1]\ : OR3 - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => un1_waddr_vect_slt3); - - \sFull_RNIODA01_0\ : OR2A - port map(A => N_156, B => \time_mem_wen_i_0[3]\, Y => - sFull_RNIODA01_0_net_1); - - \Raddr_vect[3]\ : DFN1E0P0 - port map(D => Raddr_vect_n3, CLK => lclk_c, PRE => rstn, E - => \time_mem_ren_i_0[3]\, Q => \Raddr_vect_i[3]\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(3), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XNOR2 - port map(A => \Waddr_vect_i[3]\, B => N_4, Y => I_13_18); - - un2_sfull_s_3_0 : XNOR2 - port map(A => \un8_waddr_vect_s[3]\, B => \Raddr_vect_i[3]\, - Y => \un2_sfull_s_3_0\); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[3]\, - C => \time_mem_addr_r_3[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNI6V1N[3]\ : OR2A - port map(A => un2_raddr_vect_slt3, B => \Raddr_vect_i[3]\, - Y => un2_raddr_vect_s); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_3[1]\, - S => \time_mem_ren_i_0[3]\, Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_14, C => - \time_mem_addr_r_3[1]\, Y => \sFull_RNO_4\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_3[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_15, C => - \time_mem_addr_w_3_i_0[2]\, Y => sEmpty_RNO_3_0); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_3_i_0[2]\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_3[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_3[0]\, C => time_wen(3), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => - \time_mem_addr_w_3_i_0[2]\, S => \time_mem_wen_i_0[3]\, Y - => Waddr_vect_e2); - - \Raddr_vect_RNIBF9H[1]\ : OR3 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => un2_raddr_vect_slt3); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_15, C => - \time_mem_addr_w_3[1]\, Y => sEmpty_RNO_4_0); - - un50_mem_addr_wen_1_SUM1_0 : XNOR2 - port map(A => \time_mem_addr_w_3_i_0[2]\, B => - \Waddr_vect_i[3]\, Y => time_mem_addr_w_3_3); - - un10_sempty_s_3_0 : XNOR2 - port map(A => \un10_raddr_vect_s[3]\, B => - \Waddr_vect_i[3]\, Y => \un10_sempty_s_3_0\); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_14, C => - \time_mem_addr_r_3_i_0[2]\, Y => \sFull_RNO_3\); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_0, B => sEmpty_RNO_4_0, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => Waddr_vect_n2_tz); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => Raddr_vect_n2_tz); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => - \time_mem_addr_r_3_i_0[2]\, S => \time_mem_ren_i_0[3]\, Y - => Raddr_vect_e2); - - sFull_RNI7H9A1 : NOR2 - port map(A => \time_mem_addr_w_3_i_0[5]\, B => - sFull_RNIODA01_0_net_1, Y => N_117); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_3[0]\); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_3[1]\, B => - \time_mem_addr_r_3[0]\, Y => N_7); - - un10_sempty_s_3_0_RNO : OR2B - port map(A => I_13_19, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \time_mem_addr_w_3_i_0[2]\, Y => - I_9_14); - - un8_raddr_vect_s_I_13 : XNOR2 - port map(A => \Raddr_vect_i[3]\, B => N_4_0, Y => I_13_19); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => N_4_0); - - sEmpty_RNO_1 : NOR2A - port map(A => \un10_sempty_s_3_0\, B => time_ren(3), Y => - un7_sempty_s_2); - - sEmpty_RNI8S0D : OR3A - port map(A => time_ren_1z, B => un5_time_write, C => - \sEmpty\, Y => \time_mem_ren_i_0[3]\); - - sFull_RNO_1 : AND2 - port map(A => time_ren(3), B => \un2_sfull_s_3_0\, Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, Y => I_5_15); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_3[0]\, B => - \time_mem_addr_w_3[1]\, C => \time_mem_addr_w_3_i_0[2]\, - Y => Waddr_vect_15_0); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_3[0]\, B => - \time_mem_addr_r_3[1]\, C => \time_mem_addr_r_3_i_0[2]\, - Y => Raddr_vect_7_0); - - sEmpty_RNIESV12 : OR2B - port map(A => \time_mem_ren_i_0[3]\, B => N_88, Y => N_89); - - \Waddr_vect_RNO[3]\ : AXO6 - port map(A => un1_waddr_vect_slt3, B => \Waddr_vect_i[3]\, - C => Waddr_vect_15_0, Y => Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => \sFull_RNO_3\, B => \sFull_RNO_4\, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_3[0]\, - Y => \un10_raddr_vect_s[0]\); - - un43_mem_addr_ren_1_CO1 : OR2A - port map(A => \time_mem_addr_r_3_i_0[2]\, B => - \Raddr_vect_i[3]\, Y => \time_mem_addr_r_3_i_0[5]\); - - sFull : DFN1C0 - port map(D => \sFull_RNO\, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - un50_mem_addr_wen_1_CO1 : OR2A - port map(A => \time_mem_addr_w_3_i_0[2]\, B => - \Waddr_vect_i[3]\, Y => \time_mem_addr_w_3_i_0[5]\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_3[1]\); - - sFull_RNO_2 : OA1A - port map(A => time_ren_1z, B => un5_time_write, C => - \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_3[0]\, C => time_wen(3), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXO6 - port map(A => un2_raddr_vect_slt3, B => \Raddr_vect_i[3]\, - C => Raddr_vect_7_0, Y => Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 is - - port( rclk : in std_logic; - rena : in std_logic; - raddr : in std_logic_vector(6 downto 0); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic; - waddr : in std_logic_vector(6 downto 0); - din : in std_logic_vector(31 downto 0); - write : in std_logic - ); - -end proasic3_syncram_2p_work_leon3mp_wfp_rtl_0; - -architecture DEF_ARCH of - proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 is - - -begin - - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity syncram_2pZ2 is - - port( wdata : in std_logic_vector(31 downto 0); - hwdata : out std_logic_vector(31 downto 0); - Waddr_vect_1 : in std_logic_vector(2 to 2); - Waddr_vect_0 : in std_logic_vector(2 to 2); - time_mem_addr_w_1_0 : in std_logic; - time_mem_addr_w_1_1 : in std_logic; - time_mem_addr_w_1_3 : in std_logic; - time_mem_addr_w_3_0 : in std_logic; - time_mem_addr_w_3_1 : in std_logic; - time_mem_addr_w_3_3 : in std_logic; - DWACT_FINC_E_0 : in std_logic_vector(0 to 0); - data_mem_addr_w_3 : in std_logic_vector(4 downto 0); - data_mem_addr_w_1 : in std_logic_vector(4 downto 0); - time_mem_addr_r_3_3 : in std_logic; - time_mem_addr_r_3_0 : in std_logic; - time_mem_addr_r_3_1 : in std_logic; - Raddr_vect_1 : in std_logic_vector(2 to 2); - Raddr_vect_0 : in std_logic_vector(2 to 2); - time_mem_addr_r_1_1 : in std_logic; - time_mem_addr_r_1_0 : in std_logic; - time_mem_addr_r_1_3 : in std_logic; - data_mem_addr_r_3 : in std_logic_vector(4 downto 0); - data_mem_addr_r_1 : in std_logic_vector(4 downto 0); - DWACT_FINC_E : in std_logic_vector(0 to 0); - Raddr_vect : in std_logic_vector(2 to 2); - time_mem_addr_r_2_0 : in std_logic; - time_mem_addr_r_2_1 : in std_logic; - time_mem_addr_r_2_3 : in std_logic; - time_mem_addr_r_2_4 : in std_logic; - data_mem_ren_i_0 : in std_logic_vector(3 downto 0); - time_mem_addr_r_3_i_0_0 : in std_logic; - time_mem_addr_r_3_i_0_3 : in std_logic; - time_mem_addr_w_3_i_0_0 : in std_logic; - time_mem_addr_w_3_i_0_3 : in std_logic; - data_mem_wen_i_0 : in std_logic_vector(3 downto 0); - Waddr_vect : in std_logic_vector(2 to 2); - data_mem_addr_w_0 : in std_logic_vector(4 downto 0); - time_mem_wen_i_0_1 : in std_logic; - time_mem_wen_i_0_3 : in std_logic; - time_mem_wen_i_0_0 : in std_logic; - time_mem_addr_w_0_1 : in std_logic; - time_mem_addr_w_0_3 : in std_logic; - time_mem_addr_w_0_4 : in std_logic; - time_mem_addr_w_0_0 : in std_logic; - time_mem_addr_w_2_4 : in std_logic; - time_mem_addr_w_2_3 : in std_logic; - time_mem_addr_w_2_1 : in std_logic; - time_mem_addr_w_2_0 : in std_logic; - data_mem_addr_w_2 : in std_logic_vector(4 downto 0); - time_mem_ren_i_0_3 : in std_logic; - time_mem_ren_i_0_1 : in std_logic; - time_mem_ren_i_0_0 : in std_logic; - time_mem_addr_r_0_4 : in std_logic; - time_mem_addr_r_0_3 : in std_logic; - time_mem_addr_r_0_0 : in std_logic; - time_mem_addr_r_0_1 : in std_logic; - data_mem_addr_r_0 : in std_logic_vector(4 downto 0); - data_mem_addr_r_2 : in std_logic_vector(4 downto 0); - N_64_i_0 : in std_logic; - lclk_c : in std_logic; - sFull_RNIODA01_0 : in std_logic; - sFull_RNIKQ9G : in std_logic; - sFull_RNIE8AH1 : in std_logic; - N_158 : in std_logic; - N_4_0 : in std_logic; - N_88 : in std_logic; - sEmpty_RNIU5CB661 : in std_logic; - sEmpty_RNI6M6A4J_0 : in std_logic; - N_4 : in std_logic; - N_115 : in std_logic; - N_117 : in std_logic; - N_93 : in std_logic; - N_35 : in std_logic; - N_37 : in std_logic; - N_157 : in std_logic; - N_162 : in std_logic; - N_161 : in std_logic; - N_165 : in std_logic; - sEmpty_RNI6M6A4J : in std_logic; - sEmpty_RNIPJ7A8P1 : in std_logic - ); - -end syncram_2pZ2; - -architecture DEF_ARCH of syncram_2pZ2 is - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 - port( rclk : in std_logic := 'U'; - rena : in std_logic := 'U'; - raddr : in std_logic_vector(6 downto 0) := (others => 'U'); - dout : out std_logic_vector(31 downto 0); - wclk : in std_logic := 'U'; - waddr : in std_logic_vector(6 downto 0) := (others => 'U'); - din : in std_logic_vector(31 downto 0) := (others => 'U'); - write : in std_logic := 'U' - ); - end component; - - signal \data_addr_r_iv_i_4[1]\, x0_RNO_81, N_72, - \data_addr_r_iv_i_0[1]\, \data_addr_r_iv_i_3[1]\, N_77, - \data_addr_r_iv_i_2[1]\, N_75, x0_RNO_108, - \data_addr_w_iv_i_5[0]\, N_151, x0_RNO_76, - \data_addr_w_iv_i_3[0]\, x0_RNO_106, - \data_addr_w_iv_i_1[0]\, x0_RNO_51, - \data_addr_w_iv_i_0[0]\, x0_RNO_62, - \data_addr_r_iv_i_4[0]\, x0_RNO_78, N_80, - \data_addr_r_iv_i_0[0]\, \data_addr_r_iv_i_3[0]\, N_85, - \data_addr_r_iv_i_2[0]\, N_83, x0_RNO_107, - \data_addr_w_iv_i_4[2]\, x0_RNO_94, x0_RNO_95, - \data_addr_w_iv_i_1[2]\, \data_addr_w_iv_i_3[2]\, N_137, - \data_addr_w_iv_i_2[2]\, N_135, x0_RNO_113, - \data_addr_w_iv_i_4[1]\, x0_RNO_91, N_138, - \data_addr_w_iv_i_1[1]\, \data_addr_w_iv_i_3[1]\, N_145, - \data_addr_w_iv_i_2[1]\, N_143, x0_RNO_112, - \data_addr_w_iv_i_4[3]\, x0_RNO_97, x0_RNO_98, - \data_addr_w_iv_i_1[3]\, \data_addr_w_iv_i_3[3]\, N_129, - \data_addr_w_iv_i_2[3]\, N_127, x0_RNO_114, - \data_addr_w_1_iv_i_s_0[6]\, - \data_addr_w_1_iv_i_a2_0_0[6]\, N_106, - \data_addr_w_1_iv_i_a2_1_0[6]\, - \data_addr_r_1_iv_i_a2_0_0[6]\, - \data_addr_w_0_iv_i_a2_3_0[5]\, - \data_addr_r_1_iv_i_a2_1_0[6]\, - \data_addr_r_1_iv_i_s_0[6]\, N_31, - \data_addr_r_iv_i_4[4]\, \data_addr_r_iv_i_1[4]\, - \data_addr_r_iv_i_3[4]\, N_46, \data_addr_r_iv_i_2[4]\, - N_44, x0_RNO_111, \data_addr_r_iv_i_4[3]\, x0_RNO_87, - x0_RNO_88, \data_addr_r_iv_i_0[3]\, - \data_addr_r_iv_i_3[3]\, N_54, \data_addr_r_iv_i_2[3]\, - N_52, x0_RNO_110, \data_addr_r_iv_i_4[2]\, x0_RNO_84, - x0_RNO_85, \data_addr_r_iv_i_0[2]\, - \data_addr_r_iv_i_3[2]\, N_62, \data_addr_r_iv_i_2[2]\, - N_60, x0_RNO_109, \data_addr_w_0_iv_i_2[5]\, - \data_addr_w_0_iv_i_1[5]\, \data_addr_w_0_iv_i_0[5]\, - x0_RNO_63, \data_addr_w_iv_i_4[4]\, x0_RNO_100, - \data_addr_w_iv_i_1[4]\, \data_addr_w_iv_i_3[4]\, N_121, - \data_addr_w_iv_i_2[4]\, N_119, N_101_i_0, N_100_i_0, - N_67_i_0, N_66_i_0, N_65_i_0, x0_RNO_5, N_33, N_108, - x0_RNO_12, N_102_i_0, N_104_i_0, N_103_i_0, N_69_i_0, - N_105_i_0, N_68_i_0, x0_RNO, x0_RNO_13, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 - Use entity work. - proasic3_syncram_2p_work_leon3mp_wfp_rtl_0(DEF_ARCH); -begin - - - \proa3.x0_RNO_28\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(1), - C => N_75, Y => \data_addr_r_iv_i_2[1]\); - - \proa3.x0_RNO_13\ : OR3B - port map(A => data_mem_wen_i_0(2), B => data_mem_wen_i_0(3), - C => sFull_RNIE8AH1, Y => x0_RNO_13); - - \proa3.x0_RNO_80\ : OA1 - port map(A => time_mem_addr_r_0_0, B => time_mem_ren_i_0_0, - C => x0_RNO_107, Y => \data_addr_r_iv_i_0[0]\); - - \proa3.x0_RNO_75\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(0), Y => N_151); - - \proa3.x0_RNO_40\ : NOR3C - port map(A => x0_RNO_78, B => N_80, C => - \data_addr_r_iv_i_0[0]\, Y => \data_addr_r_iv_i_4[0]\); - - \proa3.x0_RNO_9\ : NOR3C - port map(A => \data_addr_w_iv_i_3[3]\, B => - \data_addr_w_iv_i_2[3]\, C => \data_addr_w_iv_i_4[3]\, Y - => N_102_i_0); - - \proa3.x0_RNO_6\ : NOR3C - port map(A => \data_addr_w_iv_i_1[0]\, B => - \data_addr_w_iv_i_0[0]\, C => \data_addr_w_iv_i_5[0]\, Y - => N_105_i_0); - - \proa3.x0_RNO_3\ : NOR3C - port map(A => \data_addr_r_iv_i_3[3]\, B => - \data_addr_r_iv_i_2[3]\, C => \data_addr_r_iv_i_4[3]\, Y - => N_66_i_0); - - \proa3.x0_RNO_12\ : OR3C - port map(A => N_161, B => N_108, C => - \data_addr_w_1_iv_i_s_0[6]\, Y => x0_RNO_12); - - \proa3.x0_RNO_27\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(0), - C => N_83, Y => \data_addr_r_iv_i_2[0]\); - - \proa3.x0_RNO_114\ : OR2 - port map(A => time_mem_addr_w_3_3, B => sFull_RNIODA01_0, Y - => x0_RNO_114); - - \proa3.x0_RNO_91\ : OR2 - port map(A => time_mem_addr_w_1_1, B => sFull_RNIKQ9G, Y - => x0_RNO_91); - - \proa3.x0_RNO_61\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(4), Y => N_121); - - \proa3.x0_RNO_103\ : OR3C - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => DWACT_FINC_E(0), Y => N_31); - - \proa3.x0_RNO_102\ : NOR3B - port map(A => time_mem_ren_i_0_0, B => - time_mem_addr_r_3_i_0_3, C => time_mem_ren_i_0_1, Y => - \data_addr_r_1_iv_i_a2_0_0[6]\); - - \proa3.x0_RNO_79\ : OR2 - port map(A => time_mem_addr_r_2_0, B => N_93, Y => N_80); - - \proa3.x0_RNO_31\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(4), - C => N_44, Y => \data_addr_r_iv_i_2[4]\); - - \proa3.x0_RNO_100\ : OR2 - port map(A => time_mem_wen_i_0_0, B => time_mem_addr_w_0_4, - Y => x0_RNO_100); - - \proa3.x0_RNO_8\ : NOR3C - port map(A => \data_addr_w_iv_i_3[2]\, B => - \data_addr_w_iv_i_2[2]\, C => \data_addr_w_iv_i_4[2]\, Y - => N_103_i_0); - - \proa3.x0_RNO_54\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(1), Y => N_77); - - \proa3.x0_RNO_4\ : NOR3C - port map(A => \data_addr_r_iv_i_3[4]\, B => - \data_addr_r_iv_i_2[4]\, C => \data_addr_r_iv_i_4[4]\, Y - => N_65_i_0); - - \proa3.x0_RNO_101\ : OA1B - port map(A => N_161, B => time_mem_addr_w_2_4, C => N_117, - Y => \data_addr_w_iv_i_1[4]\); - - \proa3.x0_RNO_20\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(4), - C => N_46, Y => \data_addr_r_iv_i_3[4]\); - - \proa3.x0_RNO_81\ : OR3A - port map(A => N_88, B => time_mem_ren_i_0_3, C => - time_mem_addr_r_3_1, Y => x0_RNO_81); - - \proa3.x0_RNO_41\ : NOR3C - port map(A => x0_RNO_81, B => N_72, C => - \data_addr_r_iv_i_0[1]\, Y => \data_addr_r_iv_i_4[1]\); - - \proa3.x0_RNO_14\ : OA1 - port map(A => N_161, B => time_mem_addr_w_2_0, C => - x0_RNO_51, Y => \data_addr_w_iv_i_1[0]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \proa3.x0_RNO_58\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(1), Y => N_145); - - \proa3.x0_RNO_95\ : OR2A - port map(A => Waddr_vect_0(2), B => time_mem_wen_i_0_0, Y - => x0_RNO_95); - - \proa3.x0_RNO_65\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(1), Y => N_75); - - \proa3.x0_RNO_76\ : OR2A - port map(A => N_162, B => data_mem_addr_w_0(0), Y => - x0_RNO_76); - - \proa3.x0_RNO_35\ : OA1A - port map(A => N_162, B => data_mem_addr_w_0(4), C => N_119, - Y => \data_addr_w_iv_i_2[4]\); - - \proa3.x0_RNO_2\ : NOR3C - port map(A => \data_addr_r_iv_i_3[2]\, B => - \data_addr_r_iv_i_2[2]\, C => \data_addr_r_iv_i_4[2]\, Y - => N_67_i_0); - - \proa3.x0_RNO_113\ : OR2A - port map(A => time_mem_addr_w_3_i_0_0, B => - sFull_RNIODA01_0, Y => x0_RNO_113); - - \proa3.x0_RNO_112\ : OR2 - port map(A => time_mem_addr_w_3_1, B => sFull_RNIODA01_0, Y - => x0_RNO_112); - - \proa3.x0_RNO_110\ : OR3B - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => time_mem_addr_r_1_3, Y => x0_RNO_110); - - \proa3.x0_RNO_57\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(4), Y => N_46); - - \proa3.x0_RNO_111\ : OR2 - port map(A => time_mem_ren_i_0_0, B => time_mem_addr_r_0_4, - Y => x0_RNO_111); - - \proa3.x0_RNO_105\ : OR2A - port map(A => DWACT_FINC_E_0(0), B => sFull_RNIKQ9G, Y => - N_106); - - \proa3.x0_RNO_73\ : NOR3A - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => data_mem_ren_i_0(0), Y => - \data_addr_r_1_iv_i_a2_1_0[6]\); - - \proa3.x0_RNO_18\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(2), - C => N_62, Y => \data_addr_r_iv_i_3[2]\); - - \proa3.x0_RNO_21\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(1), C => N_145, - Y => \data_addr_w_iv_i_3[1]\); - - \proa3.x0_RNO_99\ : OA1 - port map(A => N_161, B => time_mem_addr_w_2_3, C => - x0_RNO_114, Y => \data_addr_w_iv_i_1[3]\); - - \proa3.x0_RNO_85\ : OR2A - port map(A => Raddr_vect_1(2), B => N_93, Y => x0_RNO_85); - - \proa3.x0_RNO_72\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(4), Y => N_119); - - \proa3.x0_RNO_69\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(1), Y => N_143); - - \proa3.x0_RNO_45\ : NOR3C - port map(A => x0_RNO_91, B => N_138, C => - \data_addr_w_iv_i_1[1]\, Y => \data_addr_w_iv_i_4[1]\); - - \proa3.x0_RNO_39\ : NOR2 - port map(A => N_117, B => N_162, Y => - \data_addr_w_0_iv_i_2[5]\); - - \proa3.x0_RNO_17\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(1), - C => N_77, Y => \data_addr_r_iv_i_3[1]\); - - \proa3.x0_RNO_50\ : OA1A - port map(A => \data_addr_w_1_iv_i_a2_0_0[6]\, B => - time_mem_wen_i_0_3, C => N_106, Y => - \data_addr_w_1_iv_i_s_0[6]\); - - \proa3.x0_RNO_89\ : OA1 - port map(A => time_mem_addr_r_0_3, B => time_mem_ren_i_0_0, - C => x0_RNO_110, Y => \data_addr_r_iv_i_0[3]\); - - \proa3.x0_RNO_49\ : OA1A - port map(A => \data_addr_r_1_iv_i_a2_0_0[6]\, B => - time_mem_ren_i_0_3, C => N_31, Y => - \data_addr_r_1_iv_i_s_0[6]\); - - \proa3.x0_RNO_10\ : NOR3C - port map(A => \data_addr_w_iv_i_3[4]\, B => - \data_addr_w_iv_i_2[4]\, C => \data_addr_w_iv_i_4[4]\, Y - => N_101_i_0); - - \proa3.x0_RNO_25\ : OA1 - port map(A => time_mem_addr_w_0_0, B => time_mem_wen_i_0_0, - C => x0_RNO_62, Y => \data_addr_w_iv_i_0[0]\); - - \proa3.x0_RNO_96\ : OA1A - port map(A => Waddr_vect(2), B => N_161, C => x0_RNO_113, Y - => \data_addr_w_iv_i_1[2]\); - - \proa3.x0_RNO_74\ : NOR3A - port map(A => time_mem_wen_i_0_0, B => time_mem_wen_i_0_1, - C => data_mem_wen_i_0(0), Y => - \data_addr_w_1_iv_i_a2_1_0[6]\); - - \proa3.x0_RNO_66\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(2), Y => N_60); - - \proa3.x0_RNO_5\ : OR3C - port map(A => N_93, B => N_33, C => - \data_addr_r_1_iv_i_s_0[6]\, Y => x0_RNO_5); - - \proa3.x0_RNO_36\ : OR3B - port map(A => time_mem_ren_i_0_3, B => - \data_addr_r_1_iv_i_a2_1_0[6]\, C => data_mem_ren_i_0(1), - Y => N_33); - - \proa3.x0_RNO_108\ : OR3B - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => time_mem_addr_r_1_1, Y => x0_RNO_108); - - \proa3.x0_RNO_93\ : OA1 - port map(A => N_161, B => time_mem_addr_w_2_1, C => - x0_RNO_112, Y => \data_addr_w_iv_i_1[1]\); - - \proa3.x0_RNO_63\ : OR2 - port map(A => time_mem_wen_i_0_0, B => N_4_0, Y => - x0_RNO_63); - - \proa3.x0_RNO_33\ : OA1A - port map(A => N_162, B => data_mem_addr_w_0(2), C => N_135, - Y => \data_addr_w_iv_i_2[2]\); - - GND_i : GND - port map(Y => \GND\); - - \proa3.x0_RNO_51\ : OR2 - port map(A => time_mem_addr_w_3_0, B => sFull_RNIODA01_0, Y - => x0_RNO_51); - - \proa3.x0_RNO_92\ : OR2 - port map(A => time_mem_wen_i_0_0, B => time_mem_addr_w_0_1, - Y => N_138); - - \proa3.x0_RNO_62\ : OR2 - port map(A => time_mem_addr_w_1_0, B => sFull_RNIKQ9G, Y - => x0_RNO_62); - - \proa3.x0_RNO_29\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(2), - C => N_60, Y => \data_addr_r_iv_i_2[2]\); - - \proa3.x0_RNO_1\ : NOR3C - port map(A => \data_addr_r_iv_i_3[1]\, B => - \data_addr_r_iv_i_2[1]\, C => \data_addr_r_iv_i_4[1]\, Y - => N_68_i_0); - - \proa3.x0_RNO_86\ : OA1A - port map(A => Raddr_vect(2), B => time_mem_ren_i_0_0, C => - x0_RNO_109, Y => \data_addr_r_iv_i_0[2]\); - - \proa3.x0_RNO_46\ : NOR3C - port map(A => x0_RNO_94, B => x0_RNO_95, C => - \data_addr_w_iv_i_1[2]\, Y => \data_addr_w_iv_i_4[2]\); - - \proa3.x0_RNO_32\ : OA1A - port map(A => N_162, B => data_mem_addr_w_0(1), C => N_143, - Y => \data_addr_w_iv_i_2[1]\); - - \proa3.x0_RNO_78\ : OR3A - port map(A => N_88, B => time_mem_ren_i_0_3, C => - time_mem_addr_r_3_0, Y => x0_RNO_78); - - \proa3.x0_RNO_83\ : OA1 - port map(A => time_mem_addr_r_0_1, B => time_mem_ren_i_0_0, - C => x0_RNO_108, Y => \data_addr_r_iv_i_0[1]\); - - \proa3.x0_RNO_43\ : NOR3C - port map(A => x0_RNO_87, B => x0_RNO_88, C => - \data_addr_r_iv_i_0[3]\, Y => \data_addr_r_iv_i_4[3]\); - - \proa3.x0_RNO_11\ : NOR3C - port map(A => \data_addr_w_0_iv_i_1[5]\, B => - \data_addr_w_0_iv_i_0[5]\, C => \data_addr_w_0_iv_i_2[5]\, - Y => N_100_i_0); - - \proa3.x0_RNO_82\ : OR2 - port map(A => time_mem_addr_r_2_1, B => N_93, Y => N_72); - - \proa3.x0_RNO_42\ : NOR3C - port map(A => x0_RNO_84, B => x0_RNO_85, C => - \data_addr_r_iv_i_0[2]\, Y => \data_addr_r_iv_i_4[2]\); - - \proa3.x0_RNO_77\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(0), C => - x0_RNO_106, Y => \data_addr_w_iv_i_3[0]\); - - \proa3.x0_RNO_0\ : NOR3C - port map(A => \data_addr_r_iv_i_3[0]\, B => - \data_addr_r_iv_i_2[0]\, C => \data_addr_r_iv_i_4[0]\, Y - => N_69_i_0); - - \proa3.x0\ : proasic3_syncram_2p_work_leon3mp_wfp_rtl_0 - port map(rclk => lclk_c, rena => x0_RNO, raddr(6) => - x0_RNO_5, raddr(5) => N_64_i_0, raddr(4) => N_65_i_0, - raddr(3) => N_66_i_0, raddr(2) => N_67_i_0, raddr(1) => - N_68_i_0, raddr(0) => N_69_i_0, dout(31) => hwdata(31), - dout(30) => hwdata(30), dout(29) => hwdata(29), dout(28) - => hwdata(28), dout(27) => hwdata(27), dout(26) => - hwdata(26), dout(25) => hwdata(25), dout(24) => - hwdata(24), dout(23) => hwdata(23), dout(22) => - hwdata(22), dout(21) => hwdata(21), dout(20) => - hwdata(20), dout(19) => hwdata(19), dout(18) => - hwdata(18), dout(17) => hwdata(17), dout(16) => - hwdata(16), dout(15) => hwdata(15), dout(14) => - hwdata(14), dout(13) => hwdata(13), dout(12) => - hwdata(12), dout(11) => hwdata(11), dout(10) => - hwdata(10), dout(9) => hwdata(9), dout(8) => hwdata(8), - dout(7) => hwdata(7), dout(6) => hwdata(6), dout(5) => - hwdata(5), dout(4) => hwdata(4), dout(3) => hwdata(3), - dout(2) => hwdata(2), dout(1) => hwdata(1), dout(0) => - hwdata(0), wclk => lclk_c, waddr(6) => x0_RNO_12, - waddr(5) => N_100_i_0, waddr(4) => N_101_i_0, waddr(3) - => N_102_i_0, waddr(2) => N_103_i_0, waddr(1) => - N_104_i_0, waddr(0) => N_105_i_0, din(31) => wdata(31), - din(30) => wdata(30), din(29) => wdata(29), din(28) => - wdata(28), din(27) => wdata(27), din(26) => wdata(26), - din(25) => wdata(25), din(24) => wdata(24), din(23) => - wdata(23), din(22) => wdata(22), din(21) => wdata(21), - din(20) => wdata(20), din(19) => wdata(19), din(18) => - wdata(18), din(17) => wdata(17), din(16) => wdata(16), - din(15) => wdata(15), din(14) => wdata(14), din(13) => - wdata(13), din(12) => wdata(12), din(11) => wdata(11), - din(10) => wdata(10), din(9) => wdata(9), din(8) => - wdata(8), din(7) => wdata(7), din(6) => wdata(6), din(5) - => wdata(5), din(4) => wdata(4), din(3) => wdata(3), - din(2) => wdata(2), din(1) => wdata(1), din(0) => - wdata(0), write => x0_RNO_13); - - \proa3.x0_RNO_55\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(2), Y => N_62); - - \proa3.x0_RNO_94\ : OR2A - port map(A => Waddr_vect_1(2), B => sFull_RNIKQ9G, Y => - x0_RNO_94); - - \proa3.x0_RNO_64\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(0), Y => N_83); - - \proa3.x0_RNO_26\ : OA1 - port map(A => N_161, B => N_4, C => x0_RNO_63, Y => - \data_addr_w_0_iv_i_0[5]\); - - \proa3.x0_RNO_34\ : OA1A - port map(A => N_162, B => data_mem_addr_w_0(3), C => N_127, - Y => \data_addr_w_iv_i_2[3]\); - - \proa3.x0_RNO_109\ : OR3C - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => Raddr_vect_0(2), Y => x0_RNO_109); - - \proa3.x0_RNO_107\ : OR3B - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => time_mem_addr_r_1_0, Y => x0_RNO_107); - - \proa3.x0_RNO_70\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(2), Y => N_135); - - \proa3.x0_RNO_23\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(3), C => N_129, - Y => \data_addr_w_iv_i_3[3]\); - - \proa3.x0_RNO_15\ : OA1B - port map(A => data_mem_wen_i_0(2), B => - \data_addr_w_0_iv_i_a2_3_0[5]\, C => N_115, Y => - \data_addr_w_0_iv_i_1[5]\); - - \proa3.x0_RNO_59\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(2), Y => N_137); - - \proa3.x0_RNO_22\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(2), C => N_137, - Y => \data_addr_w_iv_i_3[2]\); - - \proa3.x0_RNO_84\ : OR3B - port map(A => N_88, B => time_mem_addr_r_3_i_0_0, C => - time_mem_ren_i_0_3, Y => x0_RNO_84); - - \proa3.x0_RNO_44\ : NOR3A - port map(A => \data_addr_r_iv_i_1[4]\, B => N_37, C => N_35, - Y => \data_addr_r_iv_i_4[4]\); - - \proa3.x0_RNO_106\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(0), Y => x0_RNO_106); - - \proa3.x0_RNO_98\ : OR2 - port map(A => time_mem_wen_i_0_0, B => time_mem_addr_w_0_3, - Y => x0_RNO_98); - - \proa3.x0_RNO_68\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(4), Y => N_44); - - \proa3.x0_RNO_38\ : NOR3C - port map(A => N_151, B => x0_RNO_76, C => - \data_addr_w_iv_i_3[0]\, Y => \data_addr_w_iv_i_5[0]\); - - \proa3.x0_RNO_7\ : NOR3C - port map(A => \data_addr_w_iv_i_3[1]\, B => - \data_addr_w_iv_i_2[1]\, C => \data_addr_w_iv_i_4[1]\, Y - => N_104_i_0); - - \proa3.x0_RNO_19\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(3), - C => N_54, Y => \data_addr_r_iv_i_3[3]\); - - \proa3.x0_RNO_97\ : OR2 - port map(A => time_mem_addr_w_1_3, B => sFull_RNIKQ9G, Y - => x0_RNO_97); - - \proa3.x0_RNO_67\ : OR3B - port map(A => sEmpty_RNI6M6A4J_0, B => data_mem_ren_i_0(1), - C => data_mem_addr_r_1(3), Y => N_52); - - \proa3.x0_RNO_37\ : OR3B - port map(A => time_mem_wen_i_0_3, B => - \data_addr_w_1_iv_i_a2_1_0[6]\, C => data_mem_wen_i_0(1), - Y => N_108); - - \proa3.x0_RNO_88\ : OR2 - port map(A => time_mem_addr_r_2_3, B => N_93, Y => - x0_RNO_88); - - \proa3.x0_RNO_71\ : OR3B - port map(A => N_158, B => data_mem_wen_i_0(1), C => - data_mem_addr_w_1(3), Y => N_127); - - \proa3.x0_RNO_48\ : NOR3B - port map(A => x0_RNO_100, B => \data_addr_w_iv_i_1[4]\, C - => N_115, Y => \data_addr_w_iv_i_4[4]\); - - \proa3.x0_RNO_56\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(3), Y => N_54); - - \proa3.x0_RNO_24\ : OA1A - port map(A => N_165, B => data_mem_addr_w_2(4), C => N_121, - Y => \data_addr_w_iv_i_3[4]\); - - \proa3.x0_RNO_104\ : NOR3B - port map(A => time_mem_wen_i_0_0, B => - time_mem_addr_w_3_i_0_3, C => time_mem_wen_i_0_1, Y => - \data_addr_w_1_iv_i_a2_0_0[6]\); - - \proa3.x0_RNO_87\ : OR3A - port map(A => N_88, B => time_mem_ren_i_0_3, C => - time_mem_addr_r_3_3, Y => x0_RNO_87); - - \proa3.x0_RNO_47\ : NOR3C - port map(A => x0_RNO_97, B => x0_RNO_98, C => - \data_addr_w_iv_i_1[3]\, Y => \data_addr_w_iv_i_4[3]\); - - \proa3.x0_RNO_90\ : OA1 - port map(A => N_93, B => time_mem_addr_r_2_4, C => - x0_RNO_111, Y => \data_addr_r_iv_i_1[4]\); - - \proa3.x0_RNO_60\ : OR3A - port map(A => data_mem_wen_i_0(2), B => sFull_RNIE8AH1, C - => data_mem_addr_w_3(3), Y => N_129); - - \proa3.x0_RNO_53\ : OR3 - port map(A => sEmpty_RNIU5CB661, B => data_mem_ren_i_0(2), - C => data_mem_addr_r_3(0), Y => N_85); - - \proa3.x0_RNO\ : OR3A - port map(A => data_mem_ren_i_0(3), B => sEmpty_RNIU5CB661, - C => data_mem_ren_i_0(2), Y => x0_RNO); - - \proa3.x0_RNO_30\ : OA1A - port map(A => sEmpty_RNI6M6A4J, B => data_mem_addr_r_0(3), - C => N_52, Y => \data_addr_r_iv_i_2[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \proa3.x0_RNO_52\ : OR2 - port map(A => N_157, B => data_mem_wen_i_0(1), Y => - \data_addr_w_0_iv_i_a2_3_0[5]\); - - \proa3.x0_RNO_16\ : OA1A - port map(A => sEmpty_RNIPJ7A8P1, B => data_mem_addr_r_2(0), - C => N_85, Y => \data_addr_r_iv_i_3[0]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ2 is - - port( ready_i_0 : out std_logic_vector(2 to 2); - data_mem_wen_i_0 : out std_logic_vector(2 to 2); - data_ren : in std_logic_vector(2 to 2); - data_mem_ren_i_0 : out std_logic_vector(2 to 2); - data_wen : in std_logic_vector(2 to 2); - data_mem_addr_r_2 : out std_logic_vector(4 downto 0); - data_mem_addr_w_2 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sFull_RNIE8AH1 : in std_logic; - N_165 : out std_logic; - sEmpty_RNIU5CB661 : in std_logic; - sEmpty_RNIPJ7A8P1 : out std_logic; - un13_time_write : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ2; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ2 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, N_4, \DWACT_FINC_E[0]\, N_12_0, N_4_0, - \DWACT_FINC_E_0[0]\, un7_sempty_s_4, un7_sempty_s_3, - un7_sempty_s_2, un7_sempty_s_1, un7_sempty_s_0, - sEmpty_RNO_6_1, \sEmpty_RNO_7\, \data_mem_addr_w_2[1]\, - \Raddr_vect_RNI0RUI[4]_net_1\, \sEmpty_RNO_8\, - \data_mem_addr_w_2[0]\, \Raddr_vect_RNIS48G[0]_net_1\, - un5_sfull_s_4_2, \data_mem_addr_r_2[3]\, - \un8_waddr_vect_s[3]\, sFull_RNO_8_1, un5_sfull_s_4_1, - \data_mem_addr_r_2[1]\, \un8_waddr_vect_s[1]\, - sFull_RNO_5_2, un5_sfull_s_4_0, \data_mem_addr_r_2[0]\, - \un8_waddr_vect_s[0]\, ADD_7x7_fast_I23_Y_0_o2_0, N_21, - N_89_i, N_73, ADD_5x5_fast_I17_un1_Y_1, N130, - ADD_5x5_fast_I13_Y_0, ADD_5x5_fast_I17_un1_Y_0, - ADD_5x5_fast_I5_un1_Y_0, \data_mem_addr_w_2[3]\, - ADD_7x7_fast_I19_Y_i_o4_0, N_11, N91, N_72_i, - ADD_5x5_fast_I11_Y_0, N80, N94, N88, - ADD_5x5_fast_I9_un1_Y_0, un1_waddr_vect_slto3_0, - \data_mem_addr_w_2[2]\, un2_raddr_vect_slto3_0, - \data_mem_addr_r_2[2]\, I11_un1_Y, N98, N77, N81, - un5_sfull_s_4, \sEmpty\, Waddr_vect_n4, Waddr_vect_14_0, - un1_waddr_vect_s, Waddr_vect_c2, sFull_RNO_11, \sFull\, - Waddr_vect_n3, Waddr_vect_n2, Waddr_vect_c1_i_0, - un2_raddr_vect_s, I_5_27, \Raddr_vect_RNI5HLL[4]_net_1\, - I_9_27, \Raddr_vect_RNIB7CO[4]_net_1\, I_13_31, - \Raddr_vect_RNIIT2R[4]_net_1\, I_20_19, I_5_26, I_9_26, - I_20_18, \data_mem_ren_i_0[2]\, \data_mem_wen_i_0[2]\, - Waddr_vect_n1_i, un2_raddr_vect_slto1, - \data_mem_addr_r_2[4]\, Waddr_vect_e4, - \data_mem_addr_w_2[4]\, Waddr_vect_e3, Waddr_vect_e2, - Waddr_vect_e1, Waddr_vect_e0, I8_un1_Y, N_75, N87, N102, - \un132_ready0_1[4]\, I_13_30, un1_sempty_s, sEmpty_RNO_11, - N96, \un132_ready1_i[5]\, I12_un1_Y, un119_readylto4, - N_24, N_16_i, un134_ready, N_164, N_165_0, - \un132_ready1[4]\, \un132_ready0[4]\, un126_ready, N_9, - N_13, N_12_1, N_11_0, N_8, N_10, N_9_0, N_7, N_4_1, N_5, - N_6, N_9_1, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - data_mem_wen_i_0(2) <= \data_mem_wen_i_0[2]\; - data_mem_ren_i_0(2) <= \data_mem_ren_i_0[2]\; - data_mem_addr_r_2(4) <= \data_mem_addr_r_2[4]\; - data_mem_addr_r_2(3) <= \data_mem_addr_r_2[3]\; - data_mem_addr_r_2(2) <= \data_mem_addr_r_2[2]\; - data_mem_addr_r_2(1) <= \data_mem_addr_r_2[1]\; - data_mem_addr_r_2(0) <= \data_mem_addr_r_2[0]\; - data_mem_addr_w_2(4) <= \data_mem_addr_w_2[4]\; - data_mem_addr_w_2(3) <= \data_mem_addr_w_2[3]\; - data_mem_addr_w_2(2) <= \data_mem_addr_w_2[2]\; - data_mem_addr_w_2(1) <= \data_mem_addr_w_2[1]\; - data_mem_addr_w_2(0) <= \data_mem_addr_w_2[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, C => \data_mem_addr_w_2[2]\, Y - => N_9_1); - - un132_ready_1_16_ADD_5x5_fast_I4_Y : OA1B - port map(A => N_73, B => N_89_i, C => N_75, Y => N96); - - \ready_gen.un126_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_2[4]\, B => - \data_mem_addr_w_2[4]\, Y => N_7); - - sEmpty_RNO_8 : XNOR2 - port map(A => \Raddr_vect_RNI5HLL[4]_net_1\, B => - \data_mem_addr_w_2[2]\, Y => \sEmpty_RNO_8\); - - \Waddr_vect_RNI1GR3[0]\ : OR2B - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, Y => Waddr_vect_c1_i_0); - - un117_ready_0_0_ADD_5x5_fast_I25_Y_0 : AX1E - port map(A => I12_un1_Y, B => ADD_5x5_fast_I17_un1_Y_1, C - => N_89_i, Y => un119_readylto4); - - un132_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO1A - port map(A => N80, B => N_73, C => N_89_i, Y => - ADD_5x5_fast_I11_Y_0); - - \ready_gen.un126_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, C => N_5, Y => N_9_0); - - \Raddr_vect_RNIBEK4_0[4]\ : OR2A - port map(A => \data_mem_addr_r_2[4]\, B => - \data_mem_addr_w_2[4]\, Y => N_75); - - un132_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N98, B => N77, C => N81, Y => I11_un1_Y); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_r_2[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_w_2[0]\, Y => N_12); - - sEmpty_RNO : AO1A - port map(A => data_ren(2), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_11); - - \ready_gen.un126_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13); - - \Raddr_vect_RNIGUJ86[0]\ : OA1B - port map(A => N_164, B => N_165_0, C => N96, Y => - un134_ready); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNI0RUI[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[3]\); - - \Raddr_vect_RNIPEHD[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_2[4]\, Y => - un2_raddr_vect_s); - - un132_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1B - port map(A => \data_mem_addr_r_2[2]\, B => - \data_mem_addr_w_2[2]\, C => N88, Y => N77); - - \Raddr_vect_RNI9EK4[3]\ : XOR2 - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, Y => N_72_i); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_2[2]\, Y => - I_9_27); - - sFull_RNIVMMP1 : NOR2 - port map(A => \data_mem_wen_i_0[2]\, B => sFull_RNIE8AH1, Y - => N_165); - - \Waddr_vect_RNO[4]\ : MX2A - port map(A => Waddr_vect_n4, B => \data_mem_addr_w_2[4]\, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e4); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_11, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[2]\, - C => \data_mem_addr_w_2[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[2]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \data_mem_addr_w_2[1]\, - S => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_2[2]\, B => - Waddr_vect_c1_i_0, C => un1_waddr_vect_s, Y => - Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, Y => I_5_26); - - sEmpty_RNIRDRU1J : NOR3 - port map(A => un13_time_write, B => \sEmpty\, C => - data_ren_1z, Y => \data_mem_ren_i_0[2]\); - - \Raddr_vect_RNIBCD5[3]\ : NOR2 - port map(A => \data_mem_addr_r_2[3]\, B => - \data_mem_addr_r_2[2]\, Y => un2_raddr_vect_slto3_0); - - \Raddr_vect_RNI9EK4_0[3]\ : OR2A - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, Y => N_73); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIB7CO[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[3]\); - - un117_ready_0_0_ADD_5x5_fast_I1_G0N : OR2A - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_r_2[1]\, Y => N87); - - sEmpty_RNO_2 : AND2 - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, Y => - un7_sempty_s_3); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_2[3]\, Y => - I_13_30); - - un132_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75, Y => \un132_ready1_i[5]\); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(2), - Y => sFull_RNO_11); - - \ready_gen.un126_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_2[4]\, B => - \data_mem_addr_r_2[4]\, Y => N_11_0); - - un117_ready_0_0_ADD_5x5_fast_I5_un1_Y_0 : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => ADD_5x5_fast_I5_un1_Y_0); - - sFull_RNO_4 : OR2B - port map(A => I_5_26, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_2[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AND2 - port map(A => sEmpty_RNO_6_1, B => \sEmpty_RNO_7\, Y => - un7_sempty_s_2); - - un132_ready_0_0_0_ADD_7x7_fast_I20_Y_i_o2_0 : AO18 - port map(A => \data_mem_addr_w_2[1]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_w_2[0]\, Y - => N_11); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNI5HLL[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[2]\); - - \Waddr_vect_RNI5GR3[3]\ : NOR2 - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_w_2[2]\, Y => un1_waddr_vect_slto3_0); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[0]\); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_18, C => - \data_mem_addr_r_2[4]\, Y => sFull_RNO_8_1); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_2[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - un132_ready_1_16_ADD_5x5_fast_I15_Y_0 : AX1D - port map(A => I8_un1_Y, B => N80, C => \un132_ready0_1[4]\, - Y => \un132_ready1[4]\); - - sFull_RNIHEC8 : OR2 - port map(A => \sFull\, B => data_wen(2), Y => - \data_mem_wen_i_0[2]\); - - \Raddr_vect_RNI0RUI[4]\ : NOR2B - port map(A => I_5_27, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNI0RUI[4]_net_1\); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_26, C => - \data_mem_addr_r_2[2]\, Y => sFull_RNO_5_2); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \data_mem_addr_w_2[2]\, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e2); - - un117_ready_0_0_ADD_5x5_fast_I17_un1_Y_1 : OA1 - port map(A => N130, B => ADD_5x5_fast_I13_Y_0, C => - ADD_5x5_fast_I17_un1_Y_0, Y => ADD_5x5_fast_I17_un1_Y_1); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_2[1]\, B => - \Raddr_vect_RNI0RUI[4]_net_1\, C => \sEmpty_RNO_8\, Y => - un7_sempty_s_1); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_2[3]\, Y - => Waddr_vect_14_0); - - un132_ready_1_16_ADD_5x5_fast_I8_un1_Y : NOR2B - port map(A => N81, B => N77, Y => I8_un1_Y); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_2[3]\, B => - \un8_waddr_vect_s[3]\, C => sFull_RNO_8_1, Y => - un5_sfull_s_4_2); - - sEmpty_RNO_0 : AND2 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, Y => - un7_sempty_s_4); - - un117_ready_0_0_ADD_5x5_fast_I12_un1_Y : OR3B - port map(A => N91, B => N94, C => N102, Y => I12_un1_Y); - - \Raddr_vect_RNIBEK4[4]\ : XNOR2 - port map(A => \data_mem_addr_w_2[4]\, B => - \data_mem_addr_r_2[4]\, Y => N_89_i); - - sEmpty_RNO_7 : XNOR2 - port map(A => \Raddr_vect_RNIB7CO[4]_net_1\, B => - \data_mem_addr_w_2[3]\, Y => \sEmpty_RNO_7\); - - un132_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_24, B => ADD_7x7_fast_I23_Y_0_o2_0, C => - N_75, Y => N_16_i); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4_0 : AO1D - port map(A => ADD_7x7_fast_I19_Y_i_o4_0, B => N_21, C => - N_89_i, Y => N_24); - - \ready_gen.un126_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, C => N_6, Y => N_8); - - \ready_gen.un126_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, Y => N_4_1); - - GND_i : GND - port map(Y => \GND\); - - un132_ready_1_16_ADD_5x5_fast_I1_G0N : NOR2A - port map(A => N91, B => N_72_i, Y => N80); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIS48G[0]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[0]\); - - \Raddr_vect_RNIPNHE3[0]\ : MX2C - port map(A => \un132_ready1_i[5]\, B => N_16_i, S => - \data_mem_addr_r_2[0]\, Y => N_165_0); - - un132_ready_0_0_0_ADD_7x7_fast_I19_Y_i_a2_0 : NOR3A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, C => N_11, Y => N_21); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_r_2[0]\, Y => N_12_0); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_2[2]\, Y => - I_9_26); - - un132_ready_1_16_ADD_5x5_fast_I1_P0N : OR2A - port map(A => N_72_i, B => N91, Y => N81); - - \ready_gen.un126_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_2[3]\, B => - \data_mem_addr_r_2[3]\, C => N_7, Y => N_12_1); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_2[3]\, Y => - I_13_31); - - \Raddr_vect_RNIOR4C2[0]\ : MX2 - port map(A => \un132_ready1[4]\, B => \un132_ready0[4]\, S - => \data_mem_addr_r_2[0]\, Y => N_164); - - \Raddr_vect_RNI7CD5[1]\ : OR2B - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_r_2[0]\, Y => un2_raddr_vect_slto1); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, C => \data_mem_addr_r_2[2]\, Y - => N_9); - - un132_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : AX1D - port map(A => N_21, B => ADD_7x7_fast_I19_Y_i_o4_0, C => - \un132_ready0_1[4]\, Y => \un132_ready0[4]\); - - \Raddr_vect_RNI5HLL[4]\ : NOR2B - port map(A => I_9_27, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNI5HLL[4]_net_1\); - - \ready_gen.un126_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_w_2[0]\, Y => N_6); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(2), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_2[4]\, Y => - I_20_19); - - \Raddr_vect_RNI391A9[0]\ : MX2 - port map(A => un119_readylto4, B => un134_ready, S => - un126_ready, Y => ready_i_0(2)); - - un117_ready_0_0_ADD_5x5_fast_I3_P0N : OR2A - port map(A => \data_mem_addr_r_2[3]\, B => - \data_mem_addr_w_2[3]\, Y => N94); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_2[1]\, B => - \un8_waddr_vect_s[1]\, C => sFull_RNO_5_2, Y => - un5_sfull_s_4_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_r_2[1]\, Y => I_5_27); - - un117_ready_0_0_ADD_5x5_fast_I2_P0N : OR2A - port map(A => \data_mem_addr_r_2[2]\, B => - \data_mem_addr_w_2[2]\, Y => N91); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_2[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[4]\); - - sFull_RNO_7 : OR2B - port map(A => I_13_30, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \ready_gen.un126_ready_0_I_11\ : OA1 - port map(A => N_13, B => N_12_1, C => N_11_0, Y => - un126_ready); - - un132_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_0 : AO1A - port map(A => N_21, B => N_89_i, C => N_73, Y => - ADD_7x7_fast_I23_Y_0_o2_0); - - \Waddr_vect_RNO[3]\ : MX2A - port map(A => Waddr_vect_n3, B => \data_mem_addr_w_2[3]\, S - => \data_mem_wen_i_0[2]\, Y => Waddr_vect_e3); - - \ready_gen.un126_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, Y => N_5); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \Raddr_vect_RNIIT2R[4]_net_1\, B => - \data_mem_addr_w_2[4]\, Y => sEmpty_RNO_6_1); - - \Raddr_vect_RNIS48G[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_2[0]\, - Y => \Raddr_vect_RNIS48G[0]_net_1\); - - \Waddr_vect_RNIAOK9[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => - Waddr_vect_c1_i_0, C => \data_mem_addr_w_2[4]\, Y => - un1_waddr_vect_s); - - sFull : DFN1C0 - port map(D => sFull_RNO_11, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_2[4]\, Y => - I_20_18); - - un132_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_89_i, B => N_73, Y => N98); - - un132_ready_0_0_0_ADD_7x7_fast_I32_Y_0_1 : XOR2 - port map(A => N_89_i, B => N_73, Y => \un132_ready0_1[4]\); - - un117_ready_0_0_ADD_5x5_fast_I0_P0N : NOR2A - port map(A => \data_mem_addr_r_2[0]\, B => - \data_mem_addr_w_2[0]\, Y => N130); - - \ready_gen.un126_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_2[2]\, B => - \data_mem_addr_r_2[2]\, C => N_4_1, Y => N_10); - - un132_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_0 : OA1C - port map(A => N_11, B => N91, C => N_72_i, Y => - ADD_7x7_fast_I19_Y_i_o4_0); - - un117_ready_0_0_ADD_5x5_fast_I9_Y : OA1 - port map(A => \data_mem_addr_r_2[0]\, B => - ADD_5x5_fast_I9_un1_Y_0, C => N87, Y => N102); - - \sEmpty_RNIPJ7A8P1\ : NOR2A - port map(A => \data_mem_ren_i_0[2]\, B => sEmpty_RNIU5CB661, - Y => sEmpty_RNIPJ7A8P1); - - \Raddr_vect_RNIIT2R[4]\ : NOR2B - port map(A => I_20_19, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNIIT2R[4]_net_1\); - - un117_ready_0_0_ADD_5x5_fast_I9_un1_Y_0 : OR2A - port map(A => \data_mem_addr_w_2[0]\, B => N88, Y => - ADD_5x5_fast_I9_un1_Y_0); - - un117_ready_0_0_ADD_5x5_fast_I1_P0N : NOR2A - port map(A => \data_mem_addr_r_2[1]\, B => - \data_mem_addr_w_2[1]\, Y => N88); - - un117_ready_0_0_ADD_5x5_fast_I17_un1_Y_0 : AO18 - port map(A => ADD_5x5_fast_I5_un1_Y_0, B => - \data_mem_addr_r_2[3]\, C => \data_mem_addr_w_2[3]\, Y - => ADD_5x5_fast_I17_un1_Y_0); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_2[1]\); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIIT2R[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[2]\, Q => - \data_mem_addr_r_2[4]\); - - \Waddr_vect_RNI38P5[2]\ : NOR2A - port map(A => \data_mem_addr_w_2[2]\, B => - Waddr_vect_c1_i_0, Y => Waddr_vect_c2); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_2[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(2), Y => - un5_sfull_s_4_0); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_2[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - sEmpty_RNO_5 : XA1A - port map(A => \data_mem_addr_w_2[0]\, B => - \Raddr_vect_RNIS48G[0]_net_1\, C => data_wen(2), Y => - un7_sempty_s_0); - - \Raddr_vect_RNIB7CO[4]\ : NOR2B - port map(A => I_13_31, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNIB7CO[4]_net_1\); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_2[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_2[0]\, B => - \data_mem_addr_w_2[1]\, C => \data_mem_addr_w_2[2]\, Y - => \DWACT_FINC_E[0]\); - - un117_ready_0_0_ADD_5x5_fast_I13_Y_0 : OR3B - port map(A => N91, B => N94, C => N88, Y => - ADD_5x5_fast_I13_Y_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ5 is - - port( time_mem_wen_i_0 : inout std_logic_vector(1 downto 0) := (others => 'Z'); - time_mem_ren_i_0 : inout std_logic_vector(1 downto 0) := (others => 'Z'); - time_wen : in std_logic_vector(1 to 1); - time_ren : in std_logic_vector(1 to 1); - time_mem_addr_w_1_3 : out std_logic; - time_mem_addr_w_1_0 : out std_logic; - time_mem_addr_w_1_1 : out std_logic; - time_mem_addr_r_1_3 : out std_logic; - time_mem_addr_r_1_0 : out std_logic; - time_mem_addr_r_1_1 : out std_logic; - DWACT_FINC_E_0 : out std_logic_vector(0 to 0); - Waddr_vect_0 : out std_logic; - DWACT_FINC_E : out std_logic_vector(0 to 0); - Raddr_vect_0 : out std_logic; - time_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - un20_time_write : in std_logic; - sFull_RNIKQ9G : out std_logic; - N_115 : out std_logic; - N_35 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ5; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ5 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \time_mem_addr_r_1[5]\, \Raddr_vect[3]_net_1\, - \Raddr_vect[2]_net_1\, \time_mem_addr_w_1[5]\, - \Waddr_vect[3]_net_1\, \Waddr_vect[2]_net_1\, N_7, N_7_0, - un10_sempty_s_3_0_1, \un10_raddr_vect_s[3]\, - un2_sfull_s_3_0_1, \un8_waddr_vect_s[3]\, un5_sfull_s_2, - un7_sempty_s_2, un5_sfull_s_3, sFull_RNO_3_2, - sFull_RNO_4_2, un5_sfull_s_0, \un8_waddr_vect_s[0]\, - \time_mem_addr_r_1[0]\, un7_sempty_s_3, sEmpty_RNO_3_2, - sEmpty_RNO_4_2, un7_sempty_s_0, \un10_raddr_vect_s[0]\, - \time_mem_addr_w_1[0]\, un1_waddr_vect_slt3, - \time_mem_addr_w_1[1]\, un2_raddr_vect_slt3, - \time_mem_addr_r_1[1]\, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, Raddr_vect_n2, - un2_raddr_vect_s, Raddr_vect_n2_tz, Waddr_vect_n2, - un1_waddr_vect_s, Waddr_vect_n2_tz, sFull_RNIKQ9G_net_1, - I_13_24, I_9_20, I_9_21, I_5_21, Raddr_vect_n1_i, - Raddr_vect_e2, Raddr_vect_e1, Raddr_vect_e0, I_13_25, - \sEmpty_RNO_2\, un2_sempty_s, \sEmpty\, Waddr_vect_e0, - Waddr_vect_e1, Waddr_vect_n1_i, Waddr_vect_e2, \sFull\, - un8_sfull_s, sFull_RNO_7, I_5_20, N_4, N_4_0, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - time_mem_addr_w_1_0 <= \time_mem_addr_w_1[0]\; - time_mem_addr_w_1_1 <= \time_mem_addr_w_1[1]\; - time_mem_addr_r_1_0 <= \time_mem_addr_r_1[0]\; - time_mem_addr_r_1_1 <= \time_mem_addr_r_1[1]\; - Waddr_vect_0 <= \Waddr_vect[2]_net_1\; - Raddr_vect_0 <= \Raddr_vect[2]_net_1\; - sFull_RNIKQ9G <= sFull_RNIKQ9G_net_1; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_1[1]\, B => - \time_mem_addr_w_1[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4); - - \Waddr_vect_RNI2QV3[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_1[1]\, B => - \time_mem_addr_r_1[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - un36_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => \time_mem_addr_w_1[5]\); - - sFull_RNINN9I : NOR2 - port map(A => \time_mem_addr_w_1[5]\, B => - sFull_RNIKQ9G_net_1, Y => N_115); - - sEmpty_RNI20LH : NOR3A - port map(A => time_ren_1z, B => un20_time_write, C => - \sEmpty\, Y => time_mem_ren_i_0(1)); - - un36_mem_addr_wen_I_16 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => DWACT_FINC_E_0(0)); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_1[1]\, B => - \time_mem_addr_w_1[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_2\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_1[1]\); - - \Waddr_vect[3]\ : DFN1E1C0 - port map(D => Waddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => time_mem_wen_i_0(1), Q => \Waddr_vect[3]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_21); - - un2_sfull_s_3_0_RNO : OR2B - port map(A => I_13_24, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_2\, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => un1_waddr_vect_s, B => time_mem_wen_i_0(1), C - => \time_mem_addr_w_1[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Waddr_vect[2]_net_1\); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \time_mem_addr_w_1[1]\, B => Waddr_vect_n1_i, - S => time_mem_wen_i_0(1), Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, Y => I_5_20); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => Raddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => time_mem_ren_i_0(1), Q => \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(1), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4, B => \Waddr_vect[3]_net_1\, Y => I_13_24); - - un31_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_1_3); - - un2_sfull_s_3_0 : XOR2 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, Y => un2_sfull_s_3_0_1); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => sFull_RNO_7); - - \Raddr_vect_RNO[0]\ : AXOI5 - port map(A => un2_raddr_vect_s, B => time_mem_ren_i_0(1), C - => \time_mem_addr_r_1[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2B - port map(A => \time_mem_addr_r_1[1]\, B => Raddr_vect_n1_i, - S => time_mem_ren_i_0(1), Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_20, C => - \time_mem_addr_r_1[1]\, Y => sFull_RNO_4_2); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_1[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_21, C => - \Waddr_vect[2]_net_1\, Y => sEmpty_RNO_3_2); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Raddr_vect[2]_net_1\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_1[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_1[0]\, C => time_wen(1), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \Waddr_vect[2]_net_1\, B => Waddr_vect_n2, S - => time_mem_wen_i_0(1), Y => Waddr_vect_e2); - - un31_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => \time_mem_addr_r_1[5]\); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_21, C => - \time_mem_addr_w_1[1]\, Y => sEmpty_RNO_4_2); - - un10_sempty_s_3_0 : XOR2 - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, Y => un10_sempty_s_3_0_1); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_20, C => - \Raddr_vect[2]_net_1\, Y => sFull_RNO_3_2); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_2, B => sEmpty_RNO_4_2, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un36_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_1_3); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2B - port map(A => \Raddr_vect[2]_net_1\, B => Raddr_vect_n2, S - => time_mem_ren_i_0(1), Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_1[0]\); - - sFull_RNICO38 : NOR2 - port map(A => time_wen(1), B => \sFull\, Y => - time_mem_wen_i_0(1)); - - sEmpty_RNIAR591 : NOR3B - port map(A => time_mem_ren_i_0(0), B => time_mem_ren_i_0(1), - C => \time_mem_addr_r_1[5]\, Y => N_35); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_1[1]\, B => - \time_mem_addr_r_1[0]\, Y => N_7); - - un10_sempty_s_3_0_RNO : OR2B - port map(A => I_13_25, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => - I_9_20); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_0, B => \Raddr_vect[3]_net_1\, Y => - I_13_25); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_0); - - sEmpty_RNO_1 : NOR2A - port map(A => un10_sempty_s_3_0_1, B => time_ren(1), Y => - un7_sempty_s_2); - - sFull_RNO_1 : AND2 - port map(A => time_ren(1), B => un2_sfull_s_3_0_1, Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, Y => I_5_21); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - \Waddr_vect_RNIGRV2[1]\ : OR3 - port map(A => \time_mem_addr_w_1[0]\, B => - \time_mem_addr_w_1[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - \sFull_RNIKQ9G\ : OR2B - port map(A => time_mem_wen_i_0(1), B => time_mem_wen_i_0(0), - Y => sFull_RNIKQ9G_net_1); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - \Raddr_vect_RNIPLA5[1]\ : OR3 - port map(A => \time_mem_addr_r_1[0]\, B => - \time_mem_addr_r_1[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - un31_mem_addr_ren_I_16 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => DWACT_FINC_E(0)); - - sFull_RNO_0 : NOR3C - port map(A => sFull_RNO_3_2, B => sFull_RNO_4_2, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_1[0]\, - Y => \un10_raddr_vect_s[0]\); - - \Raddr_vect_RNIEI37[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - sFull : DFN1C0 - port map(D => sFull_RNO_7, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_1[1]\); - - sFull_RNO_2 : OA1A - port map(A => time_ren_1z, B => un20_time_write, C => - \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_1[0]\, C => time_wen(1), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ3 is - - port( ready_i_0 : out std_logic_vector(3 to 3); - data_mem_wen_i_0 : out std_logic_vector(3 to 3); - data_ren : in std_logic_vector(3 to 3); - data_mem_ren_i_0 : out std_logic_vector(3 to 3); - data_wen : in std_logic_vector(3 to 3); - data_mem_addr_r_3 : out std_logic_vector(4 downto 0); - data_mem_addr_w_3 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - un5_time_write : in std_logic - ); - -end lpp_waveform_fifo_ctrlZ3; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ3 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI4 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, N_4, \DWACT_FINC_E[0]\, N_12_0, N_4_0, - \DWACT_FINC_E_0[0]\, I16_un1_Y, N111, N115, N_73_i, - N_74_i, N_71_1, N_72_i, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \data_mem_addr_w_3[3]\, - \un10_raddr_vect_s[3]\, \sEmpty_RNO_6\, - \data_mem_addr_w_3[1]\, \un10_raddr_vect_s[1]\, - \sEmpty_RNO_5\, \data_mem_addr_w_3[0]\, - \un10_raddr_vect_s[0]\, un5_sfull_s_4_2, - \data_mem_addr_r_3[3]\, \un8_waddr_vect_s[3]\, - \sFull_RNO_8\, un5_sfull_s_4_1, \data_mem_addr_r_3[1]\, - \un8_waddr_vect_s[1]\, \sFull_RNO_5\, un5_sfull_s_4_0, - \data_mem_addr_r_3[0]\, \un8_waddr_vect_s[0]\, - ADD_7x7_fast_I26_Y_0, N114, ADD_7x7_fast_I27_un1_Y_0, - N151, ADD_5x5_fast_I17_un1_Y_1, I5_un1_Y, N110, - ADD_7x7_fast_I25_un1_Y_0, N135, un1_waddr_vect_slto3_0, - ADD_7x7_fast_I13_un1_Y_0, N101, un2_raddr_vect_slto3_0, - \data_mem_addr_w_3[2]\, N94, \data_mem_addr_r_3[2]\, - \un189_ready_i[4]\, I27_un1_Y, N139, I25_un1_Y, N140, - N146, N_75_1_i_0, un5_sfull_s_4, \sEmpty\, Waddr_vect_n4, - Waddr_vect_14_0, un1_waddr_vect_s, Waddr_vect_c2, - sFull_RNO_9, \sFull\, Waddr_vect_n2, Waddr_vect_c1, - Waddr_vect_n3, sEmpty_RNO_9, un1_sempty_s, - un2_raddr_vect_s, I_5_23, \un10_raddr_vect_s[2]\, I_9_23, - I_13_27, \un10_raddr_vect_s[4]\, I_20_15, - \data_mem_addr_w_3[4]\, I_20_14, I_9_22, I_13_26, I_5_22, - un2_raddr_vect_slto1, \data_mem_addr_r_3[4]\, - un176_readylto4, un191_ready_i_0, un183_ready, - \un189_ready_i[5]\, I12_un1_Y, N99, Waddr_vect_e0, - \data_mem_wen_i_0[3]\, Waddr_vect_e1, Waddr_vect_n1_i, - Waddr_vect_e2, Waddr_vect_e3, Waddr_vect_e4, N141, N100, - \data_mem_ren_i_0[3]\, N_9, N_13, N_12_1, N_11, N_8, N_10, - N_9_0, N_7, N_4_1, N_5, N_6, N_9_1, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - data_mem_wen_i_0(3) <= \data_mem_wen_i_0[3]\; - data_mem_ren_i_0(3) <= \data_mem_ren_i_0[3]\; - data_mem_addr_r_3(4) <= \data_mem_addr_r_3[4]\; - data_mem_addr_r_3(3) <= \data_mem_addr_r_3[3]\; - data_mem_addr_r_3(2) <= \data_mem_addr_r_3[2]\; - data_mem_addr_r_3(1) <= \data_mem_addr_r_3[1]\; - data_mem_addr_r_3(0) <= \data_mem_addr_r_3[0]\; - data_mem_addr_w_3(4) <= \data_mem_addr_w_3[4]\; - data_mem_addr_w_3(3) <= \data_mem_addr_w_3[3]\; - data_mem_addr_w_3(2) <= \data_mem_addr_w_3[2]\; - data_mem_addr_w_3(1) <= \data_mem_addr_w_3[1]\; - data_mem_addr_w_3(0) <= \data_mem_addr_w_3[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, C => \data_mem_addr_w_3[2]\, Y - => N_9_1); - - un189_ready_0_0_ADD_7x7_fast_I1_G0N : NOR2A - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_r_3[1]\, Y => N100); - - \ready_gen.un183_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, C => N_7, Y => N_12_1); - - un189_ready_0_0_ADD_7x7_fast_I35_Y_0 : XOR3 - port map(A => N_74_i, B => N_73_i, C => I27_un1_Y, Y => - \un189_ready_i[4]\); - - un189_ready_0_0_ADD_7x7_fast_I13_un1_Y_0 : NOR2B - port map(A => \data_mem_addr_w_3[0]\, B => N101, Y => - ADD_7x7_fast_I13_un1_Y_0); - - \ready_gen.un183_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_w_3[0]\, Y => N_6); - - \Raddr_vect_RNIGT0F1[4]\ : NOR2B - port map(A => I_20_15, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, C => \data_mem_addr_r_3[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, Y => N_12); - - sEmpty_RNO : AO1A - port map(A => data_ren(3), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_9); - - \ready_gen.un183_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, Y => N_4_1); - - \Raddr_vect_RNIH1K8[4]\ : XNOR2 - port map(A => \data_mem_addr_w_3[4]\, B => - \data_mem_addr_r_3[4]\, Y => N_74_i); - - \Raddr_vect[1]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[1]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[3]\); - - \ready_gen.un183_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, Y => N_5); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_3[2]\, Y => - I_9_23); - - un189_ready_0_0_ADD_7x7_fast_I13_Y : OA1C - port map(A => ADD_7x7_fast_I13_un1_Y_0, B => - \data_mem_addr_r_3[0]\, C => N100, Y => N139); - - un174_ready_0_0_ADD_5x5_fast_I13_Y : OR2A - port map(A => N99, B => N140, Y => N110); - - \Waddr_vect_RNO[4]\ : MX2A - port map(A => Waddr_vect_n4, B => \data_mem_addr_w_3[4]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e4); - - un189_ready_0_0_ADD_7x7_fast_I26_Y_0 : NOR2B - port map(A => N114, B => I16_un1_Y, Y => - ADD_7x7_fast_I26_Y_0); - - un189_ready_0_0_ADD_7x7_fast_I25_un1_Y_0 : AOI1B - port map(A => N_74_i, B => N_73_i, C => N135, Y => - ADD_7x7_fast_I25_un1_Y_0); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_9, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[3]\, - C => \data_mem_addr_w_3[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[2]\); - - un189_ready_0_0_ADD_7x7_fast_I0_P0N : OR2A - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_w_3[0]\, Y => N141); - - \ready_gen.un183_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, C => N_5, Y => N_9_0); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \data_mem_addr_w_3[1]\, - S => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - un189_ready_0_0_ADD_7x7_fast_I1_P0N : OR2A - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, Y => N101); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_3[2]\, B => Waddr_vect_c1, C - => un1_waddr_vect_s, Y => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, Y => I_5_22); - - un189_ready_0_0_ADD_7x7_fast_I27_un1_Y : OA1C - port map(A => N135, B => N139, C => - ADD_7x7_fast_I27_un1_Y_0, Y => I27_un1_Y); - - \ready_gen.un183_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_3[2]\, B => - \data_mem_addr_r_3[2]\, C => N_4_1, Y => N_10); - - \Raddr_vect_RNITTJ51[4]\ : NOR2B - port map(A => I_9_23, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[3]\); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_3[1]\, B => - \un10_raddr_vect_s[1]\, C => \sEmpty_RNO_5\, Y => - un7_sempty_s_1); - - \ready_gen.un183_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_3[4]\, B => - \data_mem_addr_w_3[4]\, Y => N_7); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_3[3]\, Y => - I_13_26); - - un174_ready_0_0_ADD_5x5_fast_I12_un1_Y : OR2A - port map(A => N99, B => N139, Y => I12_un1_Y); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(3), - Y => sFull_RNO_9); - - \Waddr_vect_RNIB3R7[3]\ : NOR2 - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_w_3[2]\, Y => un1_waddr_vect_slto3_0); - - \Raddr_vect_RNIDVC9[0]\ : OR2B - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_r_3[0]\, Y => un2_raddr_vect_slto1); - - sFull_RNO_4 : OR2B - port map(A => I_5_22, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[1]\); - - sFull_RNO_6 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_3[0]\, - Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_3[0]\, B => - \un10_raddr_vect_s[0]\, C => data_wen(3), Y => - un7_sempty_s_0); - - \ready_gen.un191_readylto6\ : AOI1B - port map(A => \un189_ready_i[4]\, B => \un189_ready_i[5]\, - C => N146, Y => un191_ready_i_0); - - \Raddr_vect[2]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[2]\); - - \Raddr_vect_RNID1K8[2]\ : NOR2A - port map(A => \data_mem_addr_r_3[2]\, B => - \data_mem_addr_w_3[2]\, Y => N_71_1); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[0]\); - - sFull_RNO_8 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_14, C => - \data_mem_addr_r_3[4]\, Y => \sFull_RNO_8\); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_3[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - un174_ready_0_0_ADD_5x5_fast_I3_P0N : OR2A - port map(A => \data_mem_addr_r_3[3]\, B => - \data_mem_addr_w_3[3]\, Y => N94); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_22, C => - \data_mem_addr_r_3[2]\, Y => \sFull_RNO_5\); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \data_mem_addr_w_3[2]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e2); - - un189_ready_0_0_ADD_7x7_fast_I14_Y : OR2B - port map(A => N141, B => N101, Y => N140); - - m2 : MX2 - port map(A => un176_readylto4, B => un191_ready_i_0, S => - un183_ready, Y => ready_i_0(3)); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_3[3]\, B => - \un10_raddr_vect_s[3]\, C => \sEmpty_RNO_6\, Y => - un7_sempty_s_2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_3[3]\, Y - => Waddr_vect_14_0); - - sFull_RNIL4A8 : OR2 - port map(A => \sFull\, B => data_wen(3), Y => - \data_mem_wen_i_0[3]\); - - \Raddr_vect_RNIF1K8_0[3]\ : OR2A - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, Y => N_73_i); - - un189_ready_0_0_ADD_7x7_fast_I3_G0N : OR2 - port map(A => N_74_i, B => N_73_i, Y => N114); - - un189_ready_0_0_ADD_7x7_fast_I21_Y : NOR2A - port map(A => N135, B => N140, Y => N151); - - sFull_RNO_3 : XA1 - port map(A => \data_mem_addr_r_3[3]\, B => - \un8_waddr_vect_s[3]\, C => \sFull_RNO_8\, Y => - un5_sfull_s_4_2); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - \ready_gen.un183_ready_0_I_11\ : OA1 - port map(A => N_13, B => N_12_1, C => N_11, Y => - un183_ready); - - \Raddr_vect_RNIF1K8[3]\ : XOR2 - port map(A => \data_mem_addr_w_3[3]\, B => - \data_mem_addr_r_3[3]\, Y => N_72_i); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNIH1K8_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_3[4]\, B => - \data_mem_addr_w_3[4]\, Y => N_75_1_i_0); - - \Raddr_vect[0]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[0]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[0]\); - - un174_ready_0_0_ADD_5x5_fast_I6_Y : NOR2A - port map(A => N94, B => N_71_1, Y => N99); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_r_3[0]\, Y => N_12_0); - - \Waddr_vect_RNI73R7[0]\ : OR2B - port map(A => \data_mem_addr_w_3[1]\, B => - \data_mem_addr_w_3[0]\, Y => Waddr_vect_c1); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_3[2]\, Y => - I_9_22); - - \Raddr_vect_RNIOEGN[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_3[4]\, Y => - un2_raddr_vect_s); - - \Raddr_vect_RNIEU6S[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_3[0]\, - Y => \un10_raddr_vect_s[0]\); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_3[3]\, Y => - I_13_27); - - sEmpty_RNIUBH42J : OR3 - port map(A => un5_time_write, B => \sEmpty\, C => - data_ren_1z, Y => \data_mem_ren_i_0[3]\); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, C => \data_mem_addr_r_3[2]\, Y - => N_9); - - \ready_gen.un183_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13); - - \Raddr_vect_RNI5ET01[4]\ : NOR2B - port map(A => I_5_23, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[1]\); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(3), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_3[4]\, Y => - I_20_15); - - un189_ready_0_0_ADD_7x7_fast_I10_Y : AXOI4 - port map(A => N_72_i, B => \data_mem_addr_r_3[2]\, C => - \data_mem_addr_w_3[2]\, Y => N135); - - sFull_RNO_1 : XA1 - port map(A => \data_mem_addr_r_3[1]\, B => - \un8_waddr_vect_s[1]\, C => \sFull_RNO_5\, Y => - un5_sfull_s_4_1); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_3[0]\, B => - \data_mem_addr_r_3[1]\, Y => I_5_23); - - un189_ready_0_0_ADD_7x7_fast_I3_P0N : NAND2 - port map(A => N_73_i, B => N_74_i, Y => N115); - - un189_ready_0_0_ADD_7x7_fast_I16_un1_Y : NAND2 - port map(A => N111, B => N115, Y => I16_un1_Y); - - \Waddr_vect_RNO_0[3]\ : XAI1 - port map(A => \data_mem_addr_w_3[3]\, B => Waddr_vect_c2, C - => un1_waddr_vect_s, Y => Waddr_vect_n3); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[4]\); - - un189_ready_0_0_ADD_7x7_fast_I2_G0N : NOR2 - port map(A => N_71_1, B => N_72_i, Y => N111); - - un189_ready_0_0_ADD_7x7_fast_I16_Y : OR3C - port map(A => N114, B => N_75_1_i_0, C => I16_un1_Y, Y => - N146); - - sFull_RNO_7 : OR2B - port map(A => I_13_26, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - \Waddr_vect_RNI9OJJ[4]\ : AO1B - port map(A => un1_waddr_vect_slto3_0, B => Waddr_vect_c1, C - => \data_mem_addr_w_3[4]\, Y => un1_waddr_vect_s); - - \Waddr_vect_RNO[3]\ : MX2A - port map(A => Waddr_vect_n3, B => \data_mem_addr_w_3[3]\, S - => \data_mem_wen_i_0[3]\, Y => Waddr_vect_e3); - - un174_ready_0_0_ADD_5x5_fast_I5_un1_Y : OR3B - port map(A => \data_mem_addr_w_3[2]\, B => N94, C => - \data_mem_addr_r_3[2]\, Y => I5_un1_Y); - - un174_ready_0_0_ADD_5x5_fast_I25_Y_0 : AX1E - port map(A => I12_un1_Y, B => ADD_5x5_fast_I17_un1_Y_1, C - => N_74_i, Y => un176_readylto4); - - sFull_RNO_0 : NOR3C - port map(A => un5_sfull_s_4_1, B => un5_sfull_s_4_0, C => - un5_sfull_s_4_2, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_3[4]\, Y => \sEmpty_RNO_6\); - - \Raddr_vect_RNIMDAA1[4]\ : NOR2B - port map(A => I_13_27, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un189_ready_0_0_ADD_7x7_fast_I27_un1_Y_0 : AO1D - port map(A => N_72_i, B => N_71_1, C => N151, Y => - ADD_7x7_fast_I27_un1_Y_0); - - \Raddr_vect_RNIHVC9[3]\ : NOR2 - port map(A => \data_mem_addr_r_3[3]\, B => - \data_mem_addr_r_3[2]\, Y => un2_raddr_vect_slto3_0); - - sFull : DFN1C0 - port map(D => sFull_RNO_9, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_3[4]\, Y => - I_20_14); - - un189_ready_0_0_ADD_7x7_fast_I25_un1_Y : AO1B - port map(A => N140, B => N139, C => - ADD_7x7_fast_I25_un1_Y_0, Y => I25_un1_Y); - - un174_ready_0_0_ADD_5x5_fast_I17_un1_Y_1 : NOR3C - port map(A => I5_un1_Y, B => N_73_i, C => N110, Y => - ADD_5x5_fast_I17_un1_Y_1); - - \ready_gen.un183_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_3[4]\, B => - \data_mem_addr_r_3[4]\, Y => N_11); - - \Waddr_vect_RNISKOB[2]\ : NOR2A - port map(A => \data_mem_addr_w_3[2]\, B => Waddr_vect_c1, Y - => Waddr_vect_c2); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_3[1]\); - - \ready_gen.un183_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_3[1]\, B => - \data_mem_addr_w_3[1]\, C => N_6, Y => N_8); - - \Raddr_vect[4]\ : DFN1E0C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[3]\, Q => - \data_mem_addr_r_3[4]\); - - un189_ready_0_0_ADD_7x7_fast_I36_Y_0 : AX1C - port map(A => I25_un1_Y, B => ADD_7x7_fast_I26_Y_0, C => - N_75_1_i_0, Y => \un189_ready_i[5]\); - - sFull_RNO_2 : XA1B - port map(A => \data_mem_addr_r_3[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(3), Y => - un5_sfull_s_4_0); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_3[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_3[2]\, Y => \sEmpty_RNO_5\); - - \Waddr_vect_RNO_0[4]\ : XAI1A - port map(A => \data_mem_addr_w_3[4]\, B => Waddr_vect_14_0, - C => un1_waddr_vect_s, Y => Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_3[0]\, B => - \data_mem_addr_w_3[1]\, C => \data_mem_addr_w_3[2]\, Y - => \DWACT_FINC_E[0]\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ0 is - - port( ready_i_0 : out std_logic_vector(0 to 0); - data_mem_wen_i_0 : out std_logic_vector(0 to 0); - data_mem_ren_i_0 : out std_logic_vector(0 to 0); - data_ren : in std_logic_vector(0 to 0); - data_wen : in std_logic_vector(0 to 0); - data_mem_addr_r_0 : out std_logic_vector(4 downto 0); - data_mem_addr_w_0 : out std_logic_vector(4 downto 0); - rstn : in std_logic; - lclk_c : in std_logic; - N_162 : out std_logic; - N_157 : in std_logic; - N_158 : out std_logic; - sEmpty_RNI6M6A4J : out std_logic; - N_89 : in std_logic; - sEmpty_RNI6M6A4J_0 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ0; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ0 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MIN3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_12, N_4, \DWACT_FINC_E[0]\, N_12_0, N_4_0, - \DWACT_FINC_E_0[0]\, un7_sempty_s_4, un7_sempty_s_1, - un7_sempty_s_0, un7_sempty_s_2, \data_mem_addr_w_0[3]\, - \un10_raddr_vect_s[3]\, sEmpty_RNO_6_0, - \data_mem_addr_w_0[1]\, \Raddr_vect_RNIMK1F1[4]_net_1\, - sEmpty_RNO_5_0, \data_mem_addr_w_0[0]\, - \Raddr_vect_RNIOHA81[0]_net_1\, un5_sfull_s_4_3, - sFull_RNO_4_3, sFull_RNO_5_0, un5_sfull_s_4_0, - \data_mem_addr_r_0[0]\, \un8_waddr_vect_s[0]\, - ADD_5x5_fast_I17_un1_Y_1, N130, ADD_5x5_fast_I13_Y_0, - ADD_5x5_fast_I17_un1_Y_0, ADD_5x5_fast_I5_un1_Y_0, - \data_mem_addr_r_0[3]\, ADD_5x5_fast_I11_Y_0, N_89_i, - N_73, N80, ADD_7x7_fast_I19_Y_i_o4_1_0, N_72, N91, N94, - N88, ADD_5x5_fast_I9_un1_Y_0, \data_mem_addr_w_0[2]\, - \data_mem_addr_r_0[2]\, un2_raddr_vect_slto3_0, - un1_waddr_vect_slt4, Waddr_vect_c1, N_11, - \data_mem_addr_r_0[1]\, I11_un1_Y, N81, N77, N98, - un5_sfull_s_4, \sFull_RNO_1\, \sFull_RNO_2\, - Waddr_vect_n4, Waddr_vect_14_0, Waddr_vect_c2, - Waddr_vect_n2, un1_waddr_vect_s, sFull_RNO_10, \sFull\, - un2_raddr_vect_s, I_5_25, \un10_raddr_vect_s[2]\, I_9_25, - I_13_29, \un10_raddr_vect_s[4]\, I_20_17, - \data_mem_addr_w_0[4]\, \data_mem_ren_i_0[0]\, N111, - un2_raddr_vect_slto1, \data_mem_wen_i_0[0]\, - Waddr_vect_e0, Waddr_vect_e1, Waddr_vect_n1_i, - Waddr_vect_e2, Waddr_vect_e3, Waddr_vect_n3_i, - Waddr_vect_e4, N_67, N165, N_14_1_i, N_23, N_75_i_0, - \data_mem_addr_r_0[4]\, N87, N83, \sEmpty\, un1_sempty_s, - sEmpty_RNO_10, I_20_16, I_13_28, I_9_24, I_5_24, - \un18_ready1[4]\, \un18_ready0[4]\, un5_readylto4, - un20_ready, un12_ready, N_166, N107, N161, N_165, - \un18_ready1[5]\, N_16_i_i_0, N_164, I12_un1_Y, N102, N_9, - N_13, N_12_1, N_11_0, N_8, N_10, N_9_0, N_7, N_4_1, N_5, - N_6, N_9_1, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - data_mem_wen_i_0(0) <= \data_mem_wen_i_0[0]\; - data_mem_ren_i_0(0) <= \data_mem_ren_i_0[0]\; - data_mem_addr_r_0(4) <= \data_mem_addr_r_0[4]\; - data_mem_addr_r_0(3) <= \data_mem_addr_r_0[3]\; - data_mem_addr_r_0(2) <= \data_mem_addr_r_0[2]\; - data_mem_addr_r_0(1) <= \data_mem_addr_r_0[1]\; - data_mem_addr_r_0(0) <= \data_mem_addr_r_0[0]\; - data_mem_addr_w_0(4) <= \data_mem_addr_w_0[4]\; - data_mem_addr_w_0(3) <= \data_mem_addr_w_0[3]\; - data_mem_addr_w_0(2) <= \data_mem_addr_w_0[2]\; - data_mem_addr_w_0(1) <= \data_mem_addr_w_0[1]\; - data_mem_addr_w_0(0) <= \data_mem_addr_w_0[0]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, C => \data_mem_addr_w_0[2]\, Y - => N_9_1); - - un3_ready_0_0_ADD_5x5_fast_I12_un1_Y : OR3B - port map(A => N91, B => N94, C => N102, Y => I12_un1_Y); - - \Waddr_vect_RNIEJON[3]\ : OR3A - port map(A => Waddr_vect_c1, B => \data_mem_addr_w_0[2]\, C - => \data_mem_addr_w_0[3]\, Y => un1_waddr_vect_slt4); - - sEmpty_RNIOP682J : NOR2 - port map(A => \sEmpty\, B => data_ren(0), Y => - \data_mem_ren_i_0[0]\); - - \ready_gen.un12_ready_0_I_2\ : OR2A - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, Y => N_5); - - \Raddr_vect_RNI970RU[0]\ : MX2 - port map(A => un5_readylto4, B => un20_ready, S => - un12_ready, Y => ready_i_0(0)); - - un18_ready_1_16_ADD_5x5_fast_I2_P0N : OR2B - port map(A => N_89_i, B => N_73, Y => N98); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0 : OR2B - port map(A => N_14_1_i, B => N_75_i_0, Y => N161); - - \Raddr_vect_RNIV7LC_0[4]\ : NOR2A - port map(A => \data_mem_addr_r_0[4]\, B => - \data_mem_addr_w_0[4]\, Y => N_75_i_0); - - \Raddr_vect_RNIHA7T6[0]\ : MX2C - port map(A => N107, B => N161, S => \data_mem_addr_r_0[0]\, - Y => N_166); - - \ready_gen.un12_ready_0_I_7\ : AO1C - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, C => N_4_1, Y => N_10); - - un8_raddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, C => \data_mem_addr_r_0[2]\, Y - => \DWACT_FINC_E_0[0]\); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, Y => N_12); - - sEmpty_RNO : AO1A - port map(A => data_ren(0), B => un7_sempty_s_4, C => - un1_sempty_s, Y => sEmpty_RNO_10); - - \Raddr_vect_RNII22HM[0]\ : AOI1 - port map(A => N_165, B => N_164, C => N_166, Y => - un20_ready); - - \ready_gen.un12_ready_0_I_4\ : OR2A - port map(A => \data_mem_addr_r_0[4]\, B => - \data_mem_addr_w_0[4]\, Y => N_7); - - \Raddr_vect[1]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIMK1F1[4]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[1]\); - - \Waddr_vect[3]\ : DFN1C0 - port map(D => Waddr_vect_e3, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[3]\); - - \Raddr_vect_RNIMK1F1[4]\ : NOR2B - port map(A => I_5_25, B => un2_raddr_vect_s, Y => - \Raddr_vect_RNIMK1F1[4]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_12_0, B => \data_mem_addr_r_0[2]\, Y => - I_9_25); - - un18_ready_0_0_0_ADD_7x7_fast_I20_Y_i_o2_0 : AO13 - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, C => \data_mem_addr_r_0[1]\, Y - => N_11); - - \ready_gen.un12_ready_0_I_9\ : AO1C - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, C => N_7, Y => N_12_1); - - \Raddr_vect_RNIMT632[4]\ : NOR2B - port map(A => I_20_17, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[4]\); - - \sEmpty_RNI6M6A4J\ : NOR2A - port map(A => \data_mem_ren_i_0[0]\, B => N_89, Y => - sEmpty_RNI6M6A4J); - - \Raddr_vect_RNI4E9H5[0]\ : MX2C - port map(A => \un18_ready1[4]\, B => \un18_ready0[4]\, S - => \data_mem_addr_r_0[0]\, Y => N_164); - - un18_ready_1_16_ADD_5x5_fast_I11_Y_0 : AO13 - port map(A => N_89_i, B => N_73, C => N80, Y => - ADD_5x5_fast_I11_Y_0); - - \Waddr_vect_RNO[4]\ : MX2B - port map(A => \data_mem_addr_w_0[4]\, B => Waddr_vect_n4, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e4); - - un3_ready_0_0_ADD_5x5_fast_I1_P0N : OR2A - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, Y => N88); - - \Raddr_vect_RNIREJ11[4]\ : AO1B - port map(A => un2_raddr_vect_slto3_0, B => - un2_raddr_vect_slto1, C => \data_mem_addr_r_0[4]\, Y => - un2_raddr_vect_s); - - sEmpty : DFN1P0 - port map(D => sEmpty_RNO_10, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI5 - port map(A => un1_waddr_vect_s, B => \data_mem_wen_i_0[0]\, - C => \data_mem_addr_w_0[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[2]\); - - un3_ready_0_0_ADD_5x5_fast_I9_Y : OA1A - port map(A => ADD_5x5_fast_I9_un1_Y_0, B => - \data_mem_addr_r_0[0]\, C => N87, Y => N102); - - \Raddr_vect_RNIR5ED[1]\ : OR2B - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_r_0[0]\, Y => un2_raddr_vect_slto1); - - \Waddr_vect_RNO[1]\ : MX2B - port map(A => \data_mem_addr_w_0[1]\, B => Waddr_vect_n1_i, - S => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - un18_ready_1_16_ADD_5x5_fast_I1_G0N : NOR2B - port map(A => N91, B => N_72, Y => N80); - - \Waddr_vect_RNO_0[2]\ : XAI1A - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_c1, C - => un1_waddr_vect_s, Y => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, Y => I_5_24); - - un3_ready_0_0_ADD_5x5_fast_I17_un1_Y_1 : OA1 - port map(A => N130, B => ADD_5x5_fast_I13_Y_0, C => - ADD_5x5_fast_I17_un1_Y_0, Y => ADD_5x5_fast_I17_un1_Y_1); - - \Waddr_vect_RNIHEQH[2]\ : NOR2A - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_c1, Y - => Waddr_vect_c2); - - \Raddr_vect_RNILQFS1[4]\ : NOR2B - port map(A => I_13_29, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un18_ready_0_0_0_ADD_7x7_fast_I33_Y_0_i_x2 : AX1E - port map(A => N_14_1_i, B => N83, C => N_75_i_0, Y => - N_16_i_i_0); - - \ready_gen.un12_ready_0_I_6\ : OA1A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, C => N_5, Y => N_9_0); - - \Raddr_vect[3]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[3]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[3]\); - - sEmpty_RNO_2 : XA1A - port map(A => \data_mem_addr_w_0[1]\, B => - \Raddr_vect_RNIMK1F1[4]_net_1\, C => sEmpty_RNO_5_0, Y - => un7_sempty_s_1); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_9_1, B => \data_mem_addr_w_0[3]\, Y => - I_13_28); - - \Raddr_vect_RNIV7LC[4]\ : XNOR2 - port map(A => \data_mem_addr_w_0[4]\, B => - \data_mem_addr_r_0[4]\, Y => N_89_i); - - sFull_RNO : OA1 - port map(A => \sFull\, B => un5_sfull_s_4, C => data_ren(0), - Y => sFull_RNO_10); - - un18_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4 : AO1 - port map(A => ADD_7x7_fast_I19_Y_i_o4_1_0, B => N_11, C => - N80, Y => N165); - - sFull_RNI92H8 : NOR2 - port map(A => \sFull\, B => data_wen(0), Y => - \data_mem_wen_i_0[0]\); - - \Raddr_vect_RNIT7LC[3]\ : XNOR2 - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, Y => N_72); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_24, C => - \data_mem_addr_r_0[2]\, Y => sFull_RNO_4_3); - - un3_ready_0_0_ADD_5x5_fast_I9_un1_Y_0 : NOR2B - port map(A => \data_mem_addr_w_0[0]\, B => N88, Y => - ADD_5x5_fast_I9_un1_Y_0); - - sFull_RNO_6 : XA1B - port map(A => \data_mem_addr_r_0[0]\, B => - \un8_waddr_vect_s[0]\, C => data_wen(0), Y => - un5_sfull_s_4_0); - - sEmpty_RNO_3 : XA1A - port map(A => \data_mem_addr_w_0[0]\, B => - \Raddr_vect_RNIOHA81[0]_net_1\, C => data_wen(0), Y => - un7_sempty_s_0); - - un18_ready_1_16_ADD_5x5_fast_I2_G0N : OR2 - port map(A => N_89_i, B => N_73, Y => N83); - - \Raddr_vect[2]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[2]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[2]\); - - sFull_RNI1GR81_0 : NOR2 - port map(A => \data_mem_wen_i_0[0]\, B => N_157, Y => N_158); - - \ready_gen.un12_ready_0_I_8\ : OR2A - port map(A => \data_mem_addr_w_0[4]\, B => - \data_mem_addr_r_0[4]\, Y => N_11_0); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[0]\); - - un6_waddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_w_0[3]\, B => - \DWACT_FINC_E[0]\, Y => N_4); - - sFull_RNO_5 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_24, C => - \data_mem_addr_r_0[1]\, Y => sFull_RNO_5_0); - - \Waddr_vect_RNO[2]\ : MX2B - port map(A => \data_mem_addr_w_0[2]\, B => Waddr_vect_n2, S - => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e2); - - un3_ready_0_0_ADD_5x5_fast_I13_Y_0 : OR3C - port map(A => N91, B => N94, C => N88, Y => - ADD_5x5_fast_I13_Y_0); - - sEmpty_RNO_4 : XA1A - port map(A => \data_mem_addr_w_0[3]\, B => - \un10_raddr_vect_s[3]\, C => sEmpty_RNO_6_0, Y => - un7_sempty_s_2); - - \Waddr_vect_RNO_1[4]\ : OR2B - port map(A => Waddr_vect_c2, B => \data_mem_addr_w_0[3]\, Y - => Waddr_vect_14_0); - - \Waddr_vect_RNICOMT[4]\ : OR2B - port map(A => un1_waddr_vect_slt4, B => - \data_mem_addr_w_0[4]\, Y => un1_waddr_vect_s); - - sFull_RNO_3 : NOR3C - port map(A => sFull_RNO_4_3, B => sFull_RNO_5_0, C => - un5_sfull_s_4_0, Y => un5_sfull_s_4_3); - - sEmpty_RNO_0 : NOR3C - port map(A => un7_sempty_s_1, B => un7_sempty_s_0, C => - un7_sempty_s_2, Y => un7_sempty_s_4); - - \ready_gen.un12_ready_0_I_3\ : NOR2A - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_w_0[0]\, Y => N_6); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0_a4 : OR3B - port map(A => N_11, B => ADD_7x7_fast_I19_Y_i_o4_1_0, C => - N_73, Y => N_23); - - un3_ready_0_0_ADD_5x5_fast_I5_un1_Y_0 : NOR2A - port map(A => \data_mem_addr_w_0[2]\, B => - \data_mem_addr_r_0[2]\, Y => ADD_5x5_fast_I5_un1_Y_0); - - GND_i : GND - port map(Y => \GND\); - - \Waddr_vect_RNO_1[3]\ : OR2A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_w_0[4]\, Y => N_67); - - un3_ready_0_0_ADD_5x5_fast_I0_P0N : NOR2A - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_w_0[0]\, Y => N130); - - \Raddr_vect[0]\ : DFN1E1C0 - port map(D => \Raddr_vect_RNIOHA81[0]_net_1\, CLK => lclk_c, - CLR => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[0]\); - - un18_ready_1_16_ADD_5x5_fast_I8_Y : MIN3 - port map(A => N_72, B => N91, C => N77, Y => N111); - - \sEmpty_RNI6M6A4J_0\ : NOR2 - port map(A => \data_mem_ren_i_0[0]\, B => N_89, Y => - sEmpty_RNI6M6A4J_0); - - \Raddr_vect_RNIT7LC_0[3]\ : OR2A - port map(A => \data_mem_addr_w_0[3]\, B => - \data_mem_addr_r_0[3]\, Y => N_73); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_r_0[0]\, Y => N_12_0); - - un18_ready_1_16_ADD_5x5_fast_I0_CO1 : XA1 - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, C => N88, Y => N77); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_12, B => \data_mem_addr_w_0[2]\, Y => - I_9_24); - - \Raddr_vect_RNIT9H2A[0]\ : MX2C - port map(A => \un18_ready1[5]\, B => N_16_i_i_0, S => - \data_mem_addr_r_0[0]\, Y => N_165); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_9, B => \data_mem_addr_r_0[3]\, Y => - I_13_29); - - \Raddr_vect_RNIV5ED[3]\ : NOR2 - port map(A => \data_mem_addr_r_0[3]\, B => - \data_mem_addr_r_0[2]\, Y => un2_raddr_vect_slto3_0); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, C => \data_mem_addr_r_0[2]\, Y - => N_9); - - un18_ready_0_0_0_ADD_7x7_fast_I23_Y_0_o2_1 : OA1A - port map(A => N165, B => N_89_i, C => N_23, Y => N_14_1_i); - - sFull_RNI1GR81 : NOR2A - port map(A => \data_mem_wen_i_0[0]\, B => N_157, Y => N_162); - - sEmpty_RNO_1 : NOR2B - port map(A => \sEmpty\, B => data_wen(0), Y => un1_sempty_s); - - un8_raddr_vect_s_I_20 : XOR2 - port map(A => N_4_0, B => \data_mem_addr_r_0[4]\, Y => - I_20_17); - - un3_ready_0_0_ADD_5x5_fast_I17_un1_Y_0 : AO18 - port map(A => ADD_5x5_fast_I5_un1_Y_0, B => - \data_mem_addr_r_0[3]\, C => \data_mem_addr_w_0[3]\, Y - => ADD_5x5_fast_I17_un1_Y_0); - - un18_ready_1_16_ADD_5x5_fast_I1_P0N : OR2 - port map(A => N91, B => N_72, Y => N81); - - sFull_RNO_1 : AX1E - port map(A => un1_waddr_vect_s, B => I_20_16, C => - \data_mem_addr_r_0[4]\, Y => \sFull_RNO_1\); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \data_mem_addr_r_0[0]\, B => - \data_mem_addr_r_0[1]\, Y => I_5_25); - - un18_ready_0_0_0_ADD_7x7_fast_I19_Y_i_o4_1_0 : AXOI5 - port map(A => N_72, B => \data_mem_addr_r_0[2]\, C => - \data_mem_addr_w_0[2]\, Y => ADD_7x7_fast_I19_Y_i_o4_1_0); - - \Waddr_vect_RNO_0[3]\ : AX1C - port map(A => Waddr_vect_c2, B => un1_waddr_vect_s, C => - N_67, Y => Waddr_vect_n3_i); - - \Waddr_vect[4]\ : DFN1C0 - port map(D => Waddr_vect_e4, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[4]\); - - un3_ready_0_0_ADD_5x5_fast_I2_P0N : OR2A - port map(A => \data_mem_addr_r_0[2]\, B => - \data_mem_addr_w_0[2]\, Y => N91); - - sFull_RNO_7 : OR2A - port map(A => un1_waddr_vect_s, B => \data_mem_addr_w_0[0]\, - Y => \un8_waddr_vect_s[0]\); - - un3_ready_0_0_ADD_5x5_fast_I3_P0N : OR2A - port map(A => \data_mem_addr_r_0[3]\, B => - \data_mem_addr_w_0[3]\, Y => N94); - - un18_ready_1_16_ADD_5x5_fast_I10_Y : OR2B - port map(A => N111, B => N_75_i_0, Y => N107); - - \Raddr_vect_RNILNOL1[4]\ : NOR2B - port map(A => I_9_25, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[2]\); - - \Waddr_vect_RNIL9SB[0]\ : OR2B - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_w_0[0]\, Y => Waddr_vect_c1); - - un3_ready_0_0_ADD_5x5_fast_I25_Y_0 : AX1E - port map(A => I12_un1_Y, B => ADD_5x5_fast_I17_un1_Y_1, C - => N_89_i, Y => un5_readylto4); - - un18_ready_1_16_ADD_5x5_fast_I11_un1_Y : OR3C - port map(A => N81, B => N77, C => N98, Y => I11_un1_Y); - - \Waddr_vect_RNO[3]\ : MX2B - port map(A => \data_mem_addr_w_0[3]\, B => Waddr_vect_n3_i, - S => \data_mem_wen_i_0[0]\, Y => Waddr_vect_e3); - - un18_ready_1_16_ADD_5x5_fast_I15_Y_0 : XNOR3 - port map(A => N_73, B => N_89_i, C => N111, Y => - \un18_ready1[4]\); - - sFull_RNO_0 : NOR3C - port map(A => \sFull_RNO_1\, B => \sFull_RNO_2\, C => - un5_sfull_s_4_3, Y => un5_sfull_s_4); - - sEmpty_RNO_6 : XNOR2 - port map(A => \un10_raddr_vect_s[4]\, B => - \data_mem_addr_w_0[4]\, Y => sEmpty_RNO_6_0); - - \ready_gen.un12_ready_0_I_11\ : OA1 - port map(A => N_13, B => N_12_1, C => N_11_0, Y => - un12_ready); - - \ready_gen.un12_ready_0_I_10\ : OA1A - port map(A => N_8, B => N_10, C => N_9_0, Y => N_13); - - sFull : DFN1C0 - port map(D => sFull_RNO_10, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \ready_gen.un12_ready_0_I_1\ : OR2A - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, Y => N_4_1); - - un6_waddr_vect_s_I_20 : XOR2 - port map(A => N_4, B => \data_mem_addr_w_0[4]\, Y => - I_20_16); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \data_mem_addr_w_0[1]\); - - \Raddr_vect[4]\ : DFN1E1C0 - port map(D => \un10_raddr_vect_s[4]\, CLK => lclk_c, CLR - => rstn, E => \data_mem_ren_i_0[0]\, Q => - \data_mem_addr_r_0[4]\); - - sFull_RNO_2 : AX1E - port map(A => un1_waddr_vect_s, B => I_13_28, C => - \data_mem_addr_r_0[3]\, Y => \sFull_RNO_2\); - - un8_raddr_vect_s_I_19 : NOR2B - port map(A => \data_mem_addr_r_0[3]\, B => - \DWACT_FINC_E_0[0]\, Y => N_4_0); - - un3_ready_0_0_ADD_5x5_fast_I1_G0N : OR2A - port map(A => \data_mem_addr_w_0[1]\, B => - \data_mem_addr_r_0[1]\, Y => N87); - - sEmpty_RNO_5 : XNOR2 - port map(A => \un10_raddr_vect_s[2]\, B => - \data_mem_addr_w_0[2]\, Y => sEmpty_RNO_5_0); - - un18_ready_1_16_ADD_5x5_fast_I16_Y_0 : AX1E - port map(A => I11_un1_Y, B => ADD_5x5_fast_I11_Y_0, C => - N_75_i_0, Y => \un18_ready1[5]\); - - un18_ready_0_0_0_ADD_7x7_fast_I32_Y_0 : XOR3 - port map(A => N_73, B => N_89_i, C => N165, Y => - \un18_ready0[4]\); - - \Waddr_vect_RNO_0[4]\ : AXO1 - port map(A => un1_waddr_vect_slt4, B => - \data_mem_addr_w_0[4]\, C => Waddr_vect_14_0, Y => - Waddr_vect_n4); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un6_waddr_vect_s_I_16 : AND3 - port map(A => \data_mem_addr_w_0[0]\, B => - \data_mem_addr_w_0[1]\, C => \data_mem_addr_w_0[2]\, Y - => \DWACT_FINC_E[0]\); - - \ready_gen.un12_ready_0_I_5\ : AO1C - port map(A => \data_mem_addr_r_0[1]\, B => - \data_mem_addr_w_0[1]\, C => N_6, Y => N_8); - - \Raddr_vect_RNIOHA81[0]\ : NOR2A - port map(A => un2_raddr_vect_s, B => \data_mem_addr_r_0[0]\, - Y => \Raddr_vect_RNIOHA81[0]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ4 is - - port( time_mem_wen_i_0 : out std_logic_vector(0 to 0); - time_mem_ren_i_0 : out std_logic_vector(0 to 0); - time_wen : in std_logic_vector(0 to 0); - time_ren : in std_logic_vector(0 to 0); - Waddr_vect_0 : out std_logic; - time_mem_addr_w_0_3 : out std_logic; - time_mem_addr_w_0_0 : out std_logic; - time_mem_addr_w_0_1 : out std_logic; - time_mem_addr_w_0_4 : out std_logic; - Raddr_vect_0 : out std_logic; - time_mem_addr_r_0_3 : out std_logic; - time_mem_addr_r_0_0 : out std_logic; - time_mem_addr_r_0_1 : out std_logic; - time_mem_addr_r_0_4 : out std_logic; - time_ren_1z : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - un27_time_write : in std_logic; - N_4_0 : out std_logic; - N_4 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ4; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ4 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \Raddr_vect[3]_net_1\, \Raddr_vect[2]_net_1\, - \Waddr_vect[3]_net_1\, \Waddr_vect[2]_net_1\, N_7, N_7_0, - un2_sfull_s_3_0_0, \un8_waddr_vect_s[3]\, - un10_sempty_s_3_0_0, \un10_raddr_vect_s[3]\, - un5_sfull_s_2, un7_sempty_s_2, un5_sfull_s_3, - sFull_RNO_3_1, sFull_RNO_4_1, un5_sfull_s_0, - \un8_waddr_vect_s[0]\, \time_mem_addr_r_0[0]\, - un7_sempty_s_3, sEmpty_RNO_3_1, sEmpty_RNO_4_1, - un7_sempty_s_0, \un10_raddr_vect_s[0]\, - \time_mem_addr_w_0[0]\, un2_raddr_vect_slt3, - \time_mem_addr_r_0[1]\, un1_waddr_vect_slt3, - \time_mem_addr_w_0[1]\, Raddr_vect_n3, Raddr_vect_7_0, - Waddr_vect_n3, Waddr_vect_15_0, Raddr_vect_n2, - \Raddr_vect_RNI2C4V[3]_net_1\, Raddr_vect_n2_tz, - Waddr_vect_n2, \Waddr_vect_RNIMJ0S[3]_net_1\, - Waddr_vect_n2_tz, I_5_17, I_9_17, I_9_16, I_5_16, - Raddr_vect_n1_i, Raddr_vect_e2, Raddr_vect_e1, - \time_mem_ren_i_0[0]\, Raddr_vect_e0, I_13_20, - \sFull_RNO_0\, un8_sfull_s, \sEmpty_RNO_0\, un2_sempty_s, - \sFull\, \sEmpty\, I_13_21, Waddr_vect_e0, - \time_mem_wen_i_0[0]\, Waddr_vect_e2, Waddr_vect_n1_i, - Waddr_vect_e1, N_4_1, N_4_2, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - time_mem_wen_i_0(0) <= \time_mem_wen_i_0[0]\; - time_mem_ren_i_0(0) <= \time_mem_ren_i_0[0]\; - Waddr_vect_0 <= \Waddr_vect[2]_net_1\; - time_mem_addr_w_0_0 <= \time_mem_addr_w_0[0]\; - time_mem_addr_w_0_1 <= \time_mem_addr_w_0[1]\; - Raddr_vect_0 <= \Raddr_vect[2]_net_1\; - time_mem_addr_r_0_0 <= \time_mem_addr_r_0[0]\; - time_mem_addr_r_0_1 <= \time_mem_addr_r_0[1]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_addr_w_0[0]\, C => - \Waddr_vect_RNIMJ0S[3]_net_1\, Y => Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4_1); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_addr_r_0[0]\, C => - \Raddr_vect_RNI2C4V[3]_net_1\, Y => Raddr_vect_n1_i); - - \Waddr_vect_RNINE0L[1]\ : OR3 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_0[1]\, B => - \time_mem_addr_w_0[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_0\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_0[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => \time_mem_wen_i_0[0]\, Q => \Waddr_vect[3]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_17); - - un2_sfull_s_3_0_RNO : OR2B - port map(A => I_13_20, B => \Waddr_vect_RNIMJ0S[3]_net_1\, - Y => \un8_waddr_vect_s[3]\); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_0\, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => - \time_mem_wen_i_0[0]\, C => \time_mem_addr_w_0[0]\, Y => - Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Waddr_vect[2]_net_1\); - - sFull_RNI8268 : OR2 - port map(A => time_wen(0), B => \sFull\, Y => - \time_mem_wen_i_0[0]\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_0[1]\, - S => \time_mem_wen_i_0[0]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => - Waddr_vect_n2_tz, Y => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, Y => I_5_16); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => - Raddr_vect_n2_tz, Y => Raddr_vect_n2); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => \time_mem_ren_i_0[0]\, Q => \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(0), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4_1, B => \Waddr_vect[3]_net_1\, Y => - I_13_20); - - un2_sfull_s_3_0 : XOR2 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, Y => un2_sfull_s_3_0_0); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO_0\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => - \time_mem_ren_i_0[0]\, C => \time_mem_addr_r_0[0]\, Y => - Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_0[1]\, - S => \time_mem_ren_i_0[0]\, Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => I_5_16, C - => \time_mem_addr_r_0[1]\, Y => sFull_RNO_4_1); - - \Raddr_vect_RNI09BN[1]\ : OR3 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - sFull_RNO_6 : OR2A - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => - \time_mem_addr_w_0[0]\, Y => \un8_waddr_vect_s[0]\); - - sEmpty_RNO_3 : AX1E - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => I_9_17, C - => \Waddr_vect[2]_net_1\, Y => sEmpty_RNO_3_1); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Raddr_vect[2]_net_1\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_0[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_0[0]\, C => time_wen(0), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[0]\, Y => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => I_5_17, C - => \time_mem_addr_w_0[1]\, Y => sEmpty_RNO_4_1); - - un10_sempty_s_3_0 : XOR2 - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, Y => un10_sempty_s_3_0_0); - - sFull_RNO_3 : AX1E - port map(A => \Waddr_vect_RNIMJ0S[3]_net_1\, B => I_9_16, C - => \Raddr_vect[2]_net_1\, Y => sFull_RNO_3_1); - - sEmpty_RNO_0 : NOR3C - port map(A => sEmpty_RNO_3_1, B => sEmpty_RNO_4_1, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - un25_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_0_4); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - un25_mem_addr_ren_I_12 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => N_4); - - GND_i : GND - port map(Y => \GND\); - - \Waddr_vect_RNIMJ0S[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => \Waddr_vect_RNIMJ0S[3]_net_1\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[0]\, Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_0[0]\); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_0[1]\, B => - \time_mem_addr_r_0[0]\, Y => N_7); - - un10_sempty_s_3_0_RNO : OR2B - port map(A => I_13_21, B => \Raddr_vect_RNI2C4V[3]_net_1\, - Y => \un10_raddr_vect_s[3]\); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => - I_9_16); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_2, B => \Raddr_vect[3]_net_1\, Y => - I_13_21); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_2); - - sEmpty_RNIV1VJ : OR3A - port map(A => time_ren_1z, B => un27_time_write, C => - \sEmpty\, Y => \time_mem_ren_i_0[0]\); - - sEmpty_RNO_1 : NOR2A - port map(A => un10_sempty_s_3_0_0, B => time_ren(0), Y => - un7_sempty_s_2); - - sFull_RNO_1 : AND2 - port map(A => time_ren(0), B => un2_sfull_s_3_0_0, Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, Y => I_5_17); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_0[0]\, B => - \time_mem_addr_w_0[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_0[0]\, B => - \time_mem_addr_r_0[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - un29_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_0_4); - - un25_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_0_3); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => sFull_RNO_3_1, B => sFull_RNO_4_1, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2A - port map(A => \Raddr_vect_RNI2C4V[3]_net_1\, B => - \time_mem_addr_r_0[0]\, Y => \un10_raddr_vect_s[0]\); - - un29_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_0_3); - - sFull : DFN1C0 - port map(D => \sFull_RNO_0\, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_0[1]\); - - un29_mem_addr_wen_I_12 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => N_4_0); - - sFull_RNO_2 : OA1A - port map(A => time_ren_1z, B => un27_time_write, C => - \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_0[0]\, C => time_wen(0), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - \Raddr_vect_RNI2C4V[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => \Raddr_vect_RNI2C4V[3]_net_1\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_ctrlZ6 is - - port( time_mem_wen_i_0_1 : in std_logic; - time_mem_wen_i_0_0 : in std_logic; - time_mem_ren_i_0_1 : in std_logic; - time_mem_ren_i_0_0 : in std_logic; - time_wen : in std_logic_vector(2 to 2); - time_ren : in std_logic_vector(2 to 2); - Waddr_vect_0 : out std_logic; - time_mem_addr_w_2_3 : out std_logic; - time_mem_addr_w_2_0 : out std_logic; - time_mem_addr_w_2_1 : out std_logic; - time_mem_addr_w_2_4 : out std_logic; - Raddr_vect_0 : out std_logic; - time_mem_addr_r_2_3 : out std_logic; - time_mem_addr_r_2_0 : out std_logic; - time_mem_addr_r_2_1 : out std_logic; - time_mem_addr_r_2_4 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - N_161 : out std_logic; - N_156 : out std_logic; - N_93 : out std_logic; - N_88 : out std_logic; - N_4_0 : out std_logic; - N_4 : out std_logic - ); - -end lpp_waveform_fifo_ctrlZ6; - -architecture DEF_ARCH of lpp_waveform_fifo_ctrlZ6 is - - component XAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AXOI7 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \Raddr_vect[3]_net_1\, \Raddr_vect[2]_net_1\, - \Waddr_vect[3]_net_1\, \Waddr_vect[2]_net_1\, N_7, N_7_0, - un5_sfull_s_3, sFull_RNO_3_0, sFull_RNO_4_0, - un5_sfull_s_0, un5_sfull_s_2, \un8_waddr_vect_s[3]\, - \un8_waddr_vect_s[0]\, \time_mem_addr_r_2[0]\, - un7_sempty_s_3, \sEmpty_RNO_3\, \sEmpty_RNO_4\, - un7_sempty_s_0, un7_sempty_s_2, \un10_raddr_vect_s[3]\, - \un10_raddr_vect_s[0]\, \time_mem_addr_w_2[0]\, - un1_waddr_vect_slt3, \time_mem_addr_w_2[1]\, - un2_raddr_vect_slt3, \time_mem_addr_r_2[1]\, - Raddr_vect_n3, Raddr_vect_7_0, Waddr_vect_n3, - Waddr_vect_15_0, Raddr_vect_n2, un2_raddr_vect_s, - Raddr_vect_n2_tz, Waddr_vect_n2, un1_waddr_vect_s, - Waddr_vect_n2_tz, \time_mem_ren_i_0[2]\, Raddr_vect_n1_i, - Raddr_vect_e2, Raddr_vect_e1, Raddr_vect_e0, I_9_18, - I_5_18, I_13_22, \sFull_RNO_6\, un8_sfull_s, - \sEmpty_RNO_1\, un2_sempty_s, \sFull\, \sEmpty\, - \time_mem_wen_i_0[2]\, Waddr_vect_e0, Waddr_vect_e1, - Waddr_vect_n1_i, Waddr_vect_e2, I_9_19, I_5_19, I_13_23, - N_4_1, N_4_2, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - Waddr_vect_0 <= \Waddr_vect[2]_net_1\; - time_mem_addr_w_2_0 <= \time_mem_addr_w_2[0]\; - time_mem_addr_w_2_1 <= \time_mem_addr_w_2[1]\; - Raddr_vect_0 <= \Raddr_vect[2]_net_1\; - time_mem_addr_r_2_0 <= \time_mem_addr_r_2[0]\; - time_mem_addr_r_2_1 <= \time_mem_addr_r_2[1]\; - - \Waddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_w_2[1]\, B => - \time_mem_addr_w_2[0]\, C => un1_waddr_vect_s, Y => - Waddr_vect_n1_i); - - un6_waddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - N_4_1); - - un37_mem_addr_ren_I_8 : OR2B - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_2_4); - - \Raddr_vect_RNO_0[1]\ : XAI1 - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_addr_r_2[0]\, C => un2_raddr_vect_s, Y => - Raddr_vect_n1_i); - - \Waddr_vect_RNI98V8[1]\ : OR3 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - un1_waddr_vect_slt3); - - \Raddr_vect_RNII2AB[1]\ : OR3 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - un2_raddr_vect_slt3); - - un6_waddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_w_2[1]\, B => - \time_mem_addr_w_2[0]\, Y => N_7_0); - - sEmpty_RNO : AO1 - port map(A => un7_sempty_s_3, B => un7_sempty_s_2, C => - un2_sempty_s, Y => \sEmpty_RNO_1\); - - \Raddr_vect[1]\ : DFN1C0 - port map(D => Raddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_2[1]\); - - \Waddr_vect[3]\ : DFN1E0C0 - port map(D => Waddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => \time_mem_wen_i_0[2]\, Q => \Waddr_vect[3]_net_1\); - - un8_raddr_vect_s_I_9 : XOR2 - port map(A => N_7, B => \Raddr_vect[2]_net_1\, Y => I_9_19); - - sEmpty : DFN1P0 - port map(D => \sEmpty_RNO_1\, CLK => lclk_c, PRE => rstn, Q - => \sEmpty\); - - \Waddr_vect_RNO[0]\ : AXOI7 - port map(A => un1_waddr_vect_s, B => \time_mem_wen_i_0[2]\, - C => \time_mem_addr_w_2[0]\, Y => Waddr_vect_e0); - - \Waddr_vect[2]\ : DFN1C0 - port map(D => Waddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Waddr_vect[2]_net_1\); - - \Waddr_vect_RNO[1]\ : MX2A - port map(A => Waddr_vect_n1_i, B => \time_mem_addr_w_2[1]\, - S => \time_mem_wen_i_0[2]\, Y => Waddr_vect_e1); - - VCC_i : VCC - port map(Y => \VCC\); - - \Waddr_vect_RNO_0[2]\ : OR2B - port map(A => un1_waddr_vect_s, B => Waddr_vect_n2_tz, Y - => Waddr_vect_n2); - - un6_waddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, Y => I_5_18); - - sFull_RNI49BO_0 : NOR3B - port map(A => time_mem_wen_i_0_0, B => - \time_mem_wen_i_0[2]\, C => time_mem_wen_i_0_1, Y => - N_156); - - \Raddr_vect_RNO_0[2]\ : OR2B - port map(A => un2_raddr_vect_s, B => Raddr_vect_n2_tz, Y - => Raddr_vect_n2); - - \Raddr_vect[3]\ : DFN1E0C0 - port map(D => Raddr_vect_n3, CLK => lclk_c, CLR => rstn, E - => \time_mem_ren_i_0[2]\, Q => \Raddr_vect[3]_net_1\); - - sEmpty_RNO_2 : NOR2B - port map(A => time_wen(2), B => \sEmpty\, Y => un2_sempty_s); - - un6_waddr_vect_s_I_13 : XOR2 - port map(A => N_4_1, B => \Waddr_vect[3]_net_1\, Y => - I_13_22); - - sFull_RNO : AO1 - port map(A => un5_sfull_s_3, B => un5_sfull_s_2, C => - un8_sfull_s, Y => \sFull_RNO_6\); - - \Raddr_vect_RNO[0]\ : AXOI7 - port map(A => un2_raddr_vect_s, B => \time_mem_ren_i_0[2]\, - C => \time_mem_addr_r_2[0]\, Y => Raddr_vect_e0); - - \Raddr_vect_RNO[1]\ : MX2A - port map(A => Raddr_vect_n1_i, B => \time_mem_addr_r_2[1]\, - S => \time_mem_ren_i_0[2]\, Y => Raddr_vect_e1); - - sFull_RNO_4 : AX1E - port map(A => un1_waddr_vect_s, B => I_5_18, C => - \time_mem_addr_r_2[1]\, Y => sFull_RNO_4_0); - - sEmpty_RNI60VK1_0 : NOR3B - port map(A => time_mem_ren_i_0_0, B => - \time_mem_ren_i_0[2]\, C => time_mem_ren_i_0_1, Y => N_88); - - sFull_RNO_6 : OR2B - port map(A => I_13_22, B => un1_waddr_vect_s, Y => - \un8_waddr_vect_s[3]\); - - sEmpty_RNO_3 : AX1E - port map(A => un2_raddr_vect_s, B => I_9_19, C => - \Waddr_vect[2]_net_1\, Y => \sEmpty_RNO_3\); - - sEmpty_RNI5UAF : OR2 - port map(A => time_ren(2), B => \sEmpty\, Y => - \time_mem_ren_i_0[2]\); - - \Raddr_vect[2]\ : DFN1C0 - port map(D => Raddr_vect_e2, CLK => lclk_c, CLR => rstn, Q - => \Raddr_vect[2]_net_1\); - - \Waddr_vect[0]\ : DFN1C0 - port map(D => Waddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_2[0]\); - - sFull_RNO_5 : XA1B - port map(A => \un8_waddr_vect_s[0]\, B => - \time_mem_addr_r_2[0]\, C => time_wen(2), Y => - un5_sfull_s_0); - - \Waddr_vect_RNO[2]\ : MX2A - port map(A => Waddr_vect_n2, B => \Waddr_vect[2]_net_1\, S - => \time_mem_wen_i_0[2]\, Y => Waddr_vect_e2); - - sEmpty_RNO_4 : AX1E - port map(A => un2_raddr_vect_s, B => I_5_19, C => - \time_mem_addr_w_2[1]\, Y => \sEmpty_RNO_4\); - - un43_mem_addr_wen_I_12 : NOR2B - port map(A => \Waddr_vect[3]_net_1\, B => - \Waddr_vect[2]_net_1\, Y => N_4_0); - - sFull_RNO_3 : AX1E - port map(A => un1_waddr_vect_s, B => I_9_18, C => - \Raddr_vect[2]_net_1\, Y => sFull_RNO_3_0); - - sEmpty_RNO_0 : NOR3C - port map(A => \sEmpty_RNO_3\, B => \sEmpty_RNO_4\, C => - un7_sempty_s_0, Y => un7_sempty_s_3); - - \Waddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_n2_tz); - - sEmpty_RNI60VK1 : OR3A - port map(A => time_mem_ren_i_0_0, B => time_mem_ren_i_0_1, - C => \time_mem_ren_i_0[2]\, Y => N_93); - - un43_mem_addr_wen_I_8 : OR2B - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_2_4); - - \Raddr_vect_RNO_1[2]\ : AX1C - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_n2_tz); - - sEmpty_RNO_7 : OR2A - port map(A => un2_raddr_vect_s, B => \time_mem_addr_r_2[0]\, - Y => \un10_raddr_vect_s[0]\); - - GND_i : GND - port map(Y => \GND\); - - \Raddr_vect_RNO[2]\ : MX2A - port map(A => Raddr_vect_n2, B => \Raddr_vect[2]_net_1\, S - => \time_mem_ren_i_0[2]\, Y => Raddr_vect_e2); - - \Raddr_vect[0]\ : DFN1C0 - port map(D => Raddr_vect_e0, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_r_2[0]\); - - sFull_RNI49BO : OR3A - port map(A => time_mem_wen_i_0_0, B => time_mem_wen_i_0_1, - C => \time_mem_wen_i_0[2]\, Y => N_161); - - un8_raddr_vect_s_I_8 : NOR2B - port map(A => \time_mem_addr_r_2[1]\, B => - \time_mem_addr_r_2[0]\, Y => N_7); - - un6_waddr_vect_s_I_9 : XOR2 - port map(A => N_7_0, B => \Waddr_vect[2]_net_1\, Y => - I_9_18); - - un8_raddr_vect_s_I_13 : XOR2 - port map(A => N_4_2, B => \Raddr_vect[3]_net_1\, Y => - I_13_23); - - \Raddr_vect_RNIQO2F[3]\ : OR2B - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, Y => un2_raddr_vect_s); - - un8_raddr_vect_s_I_12 : AND3 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - N_4_2); - - sEmpty_RNO_1 : XA1B - port map(A => \Waddr_vect[3]_net_1\, B => - \un10_raddr_vect_s[3]\, C => time_ren(2), Y => - un7_sempty_s_2); - - sFull_RNIGE18 : OR2 - port map(A => time_wen(2), B => \sFull\, Y => - \time_mem_wen_i_0[2]\); - - sFull_RNO_1 : XA1 - port map(A => \Raddr_vect[3]_net_1\, B => - \un8_waddr_vect_s[3]\, C => time_ren(2), Y => - un5_sfull_s_2); - - un8_raddr_vect_s_I_5 : XOR2 - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, Y => I_5_19); - - un43_mem_addr_wen_I_5 : XOR2 - port map(A => \Waddr_vect[2]_net_1\, B => - \Waddr_vect[3]_net_1\, Y => time_mem_addr_w_2_3); - - un37_mem_addr_ren_I_12 : NOR2B - port map(A => \Raddr_vect[3]_net_1\, B => - \Raddr_vect[2]_net_1\, Y => N_4); - - \Waddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_w_2[0]\, B => - \time_mem_addr_w_2[1]\, C => \Waddr_vect[2]_net_1\, Y => - Waddr_vect_15_0); - - sFull_RNO_7 : OR2A - port map(A => un1_waddr_vect_s, B => \time_mem_addr_w_2[0]\, - Y => \un8_waddr_vect_s[0]\); - - \Raddr_vect_RNO_0[3]\ : OR3C - port map(A => \time_mem_addr_r_2[0]\, B => - \time_mem_addr_r_2[1]\, C => \Raddr_vect[2]_net_1\, Y => - Raddr_vect_7_0); - - \Waddr_vect_RNIE0VB[3]\ : OR2B - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, Y => un1_waddr_vect_s); - - \Waddr_vect_RNO[3]\ : AXOI1 - port map(A => un1_waddr_vect_slt3, B => - \Waddr_vect[3]_net_1\, C => Waddr_vect_15_0, Y => - Waddr_vect_n3); - - sFull_RNO_0 : NOR3C - port map(A => sFull_RNO_3_0, B => sFull_RNO_4_0, C => - un5_sfull_s_0, Y => un5_sfull_s_3); - - sEmpty_RNO_6 : OR2B - port map(A => I_13_23, B => un2_raddr_vect_s, Y => - \un10_raddr_vect_s[3]\); - - un37_mem_addr_ren_I_5 : XOR2 - port map(A => \Raddr_vect[2]_net_1\, B => - \Raddr_vect[3]_net_1\, Y => time_mem_addr_r_2_3); - - sFull : DFN1C0 - port map(D => \sFull_RNO_6\, CLK => lclk_c, CLR => rstn, Q - => \sFull\); - - \Waddr_vect[1]\ : DFN1C0 - port map(D => Waddr_vect_e1, CLK => lclk_c, CLR => rstn, Q - => \time_mem_addr_w_2[1]\); - - sFull_RNO_2 : NOR2B - port map(A => time_ren(2), B => \sFull\, Y => un8_sfull_s); - - sEmpty_RNO_5 : XA1 - port map(A => \un10_raddr_vect_s[0]\, B => - \time_mem_addr_w_2[0]\, C => time_wen(2), Y => - un7_sempty_s_0); - - \Raddr_vect_RNO[3]\ : AXOI1 - port map(A => un2_raddr_vect_slt3, B => - \Raddr_vect[3]_net_1\, C => Raddr_vect_7_0, Y => - Raddr_vect_n3); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo is - - port( ready_i_0_i_0 : out std_logic_vector(1 to 1); - data_wen : in std_logic_vector(3 downto 0); - data_ren : in std_logic_vector(3 downto 0); - ready_i_0_2 : out std_logic; - ready_i_0_0 : out std_logic; - ready_i_0_3 : out std_logic; - time_ren : in std_logic_vector(3 downto 0); - time_wen : in std_logic_vector(3 downto 0); - hwdata : out std_logic_vector(31 downto 0); - wdata : in std_logic_vector(31 downto 0); - time_ren_1z : in std_logic; - data_ren_1z : in std_logic; - un13_time_write : in std_logic; - un20_time_write : in std_logic; - un27_time_write : in std_logic; - un5_time_write : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_waveform_fifo; - -architecture DEF_ARCH of lpp_waveform_fifo is - - component lpp_waveform_fifo_ctrlZ1 - port( ready_i_0_i_0 : out std_logic_vector(1 to 1); - data_mem_wen_i_0 : out std_logic_vector(1 to 1); - data_ren : in std_logic_vector(1 to 1) := (others => 'U'); - data_mem_ren_i_0 : out std_logic_vector(1 to 1); - data_wen : in std_logic_vector(1 to 1) := (others => 'U'); - data_mem_addr_r_1 : out std_logic_vector(4 downto 0); - data_mem_addr_w_1 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_158 : in std_logic := 'U'; - sFull_RNIE8AH1 : out std_logic; - sEmpty_RNI6M6A4J_0 : in std_logic := 'U'; - sEmpty_RNIU5CB661 : out std_logic; - un20_time_write : in std_logic := 'U' - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ7 - port( time_mem_wen_i_0 : out std_logic_vector(3 to 3); - time_mem_ren_i_0 : out std_logic_vector(3 to 3); - time_mem_addr_w_3_i_0_3 : out std_logic; - time_mem_addr_w_3_i_0_0 : out std_logic; - time_mem_addr_r_3_i_0_3 : out std_logic; - time_mem_addr_r_3_i_0_0 : out std_logic; - time_wen : in std_logic_vector(3 to 3) := (others => 'U'); - time_ren : in std_logic_vector(3 to 3) := (others => 'U'); - time_mem_addr_w_3_3 : out std_logic; - time_mem_addr_w_3_0 : out std_logic; - time_mem_addr_w_3_1 : out std_logic; - time_mem_addr_r_3_3 : out std_logic; - time_mem_addr_r_3_0 : out std_logic; - time_mem_addr_r_3_1 : out std_logic; - time_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_156 : in std_logic := 'U'; - N_157 : out std_logic; - sFull_RNIODA01_0 : out std_logic; - N_117 : out std_logic; - un5_time_write : in std_logic := 'U'; - N_89 : out std_logic; - N_88 : in std_logic := 'U'; - N_37 : out std_logic - ); - end component; - - component syncram_2pZ2 - port( wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - Waddr_vect_1 : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_0 : in std_logic_vector(2 to 2) := (others => 'U'); - time_mem_addr_w_1_0 : in std_logic := 'U'; - time_mem_addr_w_1_1 : in std_logic := 'U'; - time_mem_addr_w_1_3 : in std_logic := 'U'; - time_mem_addr_w_3_0 : in std_logic := 'U'; - time_mem_addr_w_3_1 : in std_logic := 'U'; - time_mem_addr_w_3_3 : in std_logic := 'U'; - DWACT_FINC_E_0 : in std_logic_vector(0 to 0) := (others => 'U'); - data_mem_addr_w_3 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_mem_addr_w_1 : in std_logic_vector(4 downto 0) := (others => 'U'); - time_mem_addr_r_3_3 : in std_logic := 'U'; - time_mem_addr_r_3_0 : in std_logic := 'U'; - time_mem_addr_r_3_1 : in std_logic := 'U'; - Raddr_vect_1 : in std_logic_vector(2 to 2) := (others => 'U'); - Raddr_vect_0 : in std_logic_vector(2 to 2) := (others => 'U'); - time_mem_addr_r_1_1 : in std_logic := 'U'; - time_mem_addr_r_1_0 : in std_logic := 'U'; - time_mem_addr_r_1_3 : in std_logic := 'U'; - data_mem_addr_r_3 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_mem_addr_r_1 : in std_logic_vector(4 downto 0) := (others => 'U'); - DWACT_FINC_E : in std_logic_vector(0 to 0) := (others => 'U'); - Raddr_vect : in std_logic_vector(2 to 2) := (others => 'U'); - time_mem_addr_r_2_0 : in std_logic := 'U'; - time_mem_addr_r_2_1 : in std_logic := 'U'; - time_mem_addr_r_2_3 : in std_logic := 'U'; - time_mem_addr_r_2_4 : in std_logic := 'U'; - data_mem_ren_i_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - time_mem_addr_r_3_i_0_0 : in std_logic := 'U'; - time_mem_addr_r_3_i_0_3 : in std_logic := 'U'; - time_mem_addr_w_3_i_0_0 : in std_logic := 'U'; - time_mem_addr_w_3_i_0_3 : in std_logic := 'U'; - data_mem_wen_i_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - Waddr_vect : in std_logic_vector(2 to 2) := (others => 'U'); - data_mem_addr_w_0 : in std_logic_vector(4 downto 0) := (others => 'U'); - time_mem_wen_i_0_1 : in std_logic := 'U'; - time_mem_wen_i_0_3 : in std_logic := 'U'; - time_mem_wen_i_0_0 : in std_logic := 'U'; - time_mem_addr_w_0_1 : in std_logic := 'U'; - time_mem_addr_w_0_3 : in std_logic := 'U'; - time_mem_addr_w_0_4 : in std_logic := 'U'; - time_mem_addr_w_0_0 : in std_logic := 'U'; - time_mem_addr_w_2_4 : in std_logic := 'U'; - time_mem_addr_w_2_3 : in std_logic := 'U'; - time_mem_addr_w_2_1 : in std_logic := 'U'; - time_mem_addr_w_2_0 : in std_logic := 'U'; - data_mem_addr_w_2 : in std_logic_vector(4 downto 0) := (others => 'U'); - time_mem_ren_i_0_3 : in std_logic := 'U'; - time_mem_ren_i_0_1 : in std_logic := 'U'; - time_mem_ren_i_0_0 : in std_logic := 'U'; - time_mem_addr_r_0_4 : in std_logic := 'U'; - time_mem_addr_r_0_3 : in std_logic := 'U'; - time_mem_addr_r_0_0 : in std_logic := 'U'; - time_mem_addr_r_0_1 : in std_logic := 'U'; - data_mem_addr_r_0 : in std_logic_vector(4 downto 0) := (others => 'U'); - data_mem_addr_r_2 : in std_logic_vector(4 downto 0) := (others => 'U'); - N_64_i_0 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sFull_RNIODA01_0 : in std_logic := 'U'; - sFull_RNIKQ9G : in std_logic := 'U'; - sFull_RNIE8AH1 : in std_logic := 'U'; - N_158 : in std_logic := 'U'; - N_4_0 : in std_logic := 'U'; - N_88 : in std_logic := 'U'; - sEmpty_RNIU5CB661 : in std_logic := 'U'; - sEmpty_RNI6M6A4J_0 : in std_logic := 'U'; - N_4 : in std_logic := 'U'; - N_115 : in std_logic := 'U'; - N_117 : in std_logic := 'U'; - N_93 : in std_logic := 'U'; - N_35 : in std_logic := 'U'; - N_37 : in std_logic := 'U'; - N_157 : in std_logic := 'U'; - N_162 : in std_logic := 'U'; - N_161 : in std_logic := 'U'; - N_165 : in std_logic := 'U'; - sEmpty_RNI6M6A4J : in std_logic := 'U'; - sEmpty_RNIPJ7A8P1 : in std_logic := 'U' - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ2 - port( ready_i_0 : out std_logic_vector(2 to 2); - data_mem_wen_i_0 : out std_logic_vector(2 to 2); - data_ren : in std_logic_vector(2 to 2) := (others => 'U'); - data_mem_ren_i_0 : out std_logic_vector(2 to 2); - data_wen : in std_logic_vector(2 to 2) := (others => 'U'); - data_mem_addr_r_2 : out std_logic_vector(4 downto 0); - data_mem_addr_w_2 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sFull_RNIE8AH1 : in std_logic := 'U'; - N_165 : out std_logic; - sEmpty_RNIU5CB661 : in std_logic := 'U'; - sEmpty_RNIPJ7A8P1 : out std_logic; - un13_time_write : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_ctrlZ5 - port( time_mem_wen_i_0 : inout std_logic_vector(1 downto 0); - time_mem_ren_i_0 : inout std_logic_vector(1 downto 0); - time_wen : in std_logic_vector(1 to 1) := (others => 'U'); - time_ren : in std_logic_vector(1 to 1) := (others => 'U'); - time_mem_addr_w_1_3 : out std_logic; - time_mem_addr_w_1_0 : out std_logic; - time_mem_addr_w_1_1 : out std_logic; - time_mem_addr_r_1_3 : out std_logic; - time_mem_addr_r_1_0 : out std_logic; - time_mem_addr_r_1_1 : out std_logic; - DWACT_FINC_E_0 : out std_logic_vector(0 to 0); - Waddr_vect_0 : out std_logic; - DWACT_FINC_E : out std_logic_vector(0 to 0); - Raddr_vect_0 : out std_logic; - time_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - un20_time_write : in std_logic := 'U'; - sFull_RNIKQ9G : out std_logic; - N_115 : out std_logic; - N_35 : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ3 - port( ready_i_0 : out std_logic_vector(3 to 3); - data_mem_wen_i_0 : out std_logic_vector(3 to 3); - data_ren : in std_logic_vector(3 to 3) := (others => 'U'); - data_mem_ren_i_0 : out std_logic_vector(3 to 3); - data_wen : in std_logic_vector(3 to 3) := (others => 'U'); - data_mem_addr_r_3 : out std_logic_vector(4 downto 0); - data_mem_addr_w_3 : out std_logic_vector(4 downto 0); - data_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - un5_time_write : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_ctrlZ0 - port( ready_i_0 : out std_logic_vector(0 to 0); - data_mem_wen_i_0 : out std_logic_vector(0 to 0); - data_mem_ren_i_0 : out std_logic_vector(0 to 0); - data_ren : in std_logic_vector(0 to 0) := (others => 'U'); - data_wen : in std_logic_vector(0 to 0) := (others => 'U'); - data_mem_addr_r_0 : out std_logic_vector(4 downto 0); - data_mem_addr_w_0 : out std_logic_vector(4 downto 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_162 : out std_logic; - N_157 : in std_logic := 'U'; - N_158 : out std_logic; - sEmpty_RNI6M6A4J : out std_logic; - N_89 : in std_logic := 'U'; - sEmpty_RNI6M6A4J_0 : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ4 - port( time_mem_wen_i_0 : out std_logic_vector(0 to 0); - time_mem_ren_i_0 : out std_logic_vector(0 to 0); - time_wen : in std_logic_vector(0 to 0) := (others => 'U'); - time_ren : in std_logic_vector(0 to 0) := (others => 'U'); - Waddr_vect_0 : out std_logic; - time_mem_addr_w_0_3 : out std_logic; - time_mem_addr_w_0_0 : out std_logic; - time_mem_addr_w_0_1 : out std_logic; - time_mem_addr_w_0_4 : out std_logic; - Raddr_vect_0 : out std_logic; - time_mem_addr_r_0_3 : out std_logic; - time_mem_addr_r_0_0 : out std_logic; - time_mem_addr_r_0_1 : out std_logic; - time_mem_addr_r_0_4 : out std_logic; - time_ren_1z : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - un27_time_write : in std_logic := 'U'; - N_4_0 : out std_logic; - N_4 : out std_logic - ); - end component; - - component lpp_waveform_fifo_ctrlZ6 - port( time_mem_wen_i_0_1 : in std_logic := 'U'; - time_mem_wen_i_0_0 : in std_logic := 'U'; - time_mem_ren_i_0_1 : in std_logic := 'U'; - time_mem_ren_i_0_0 : in std_logic := 'U'; - time_wen : in std_logic_vector(2 to 2) := (others => 'U'); - time_ren : in std_logic_vector(2 to 2) := (others => 'U'); - Waddr_vect_0 : out std_logic; - time_mem_addr_w_2_3 : out std_logic; - time_mem_addr_w_2_0 : out std_logic; - time_mem_addr_w_2_1 : out std_logic; - time_mem_addr_w_2_4 : out std_logic; - Raddr_vect_0 : out std_logic; - time_mem_addr_r_2_3 : out std_logic; - time_mem_addr_r_2_0 : out std_logic; - time_mem_addr_r_2_1 : out std_logic; - time_mem_addr_r_2_4 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_161 : out std_logic; - N_156 : out std_logic; - N_93 : out std_logic; - N_88 : out std_logic; - N_4_0 : out std_logic; - N_4 : out std_logic - ); - end component; - - signal N_64_i_0, \data_addr_r_0_iv_i_2[5]\, - \data_addr_r_0_iv_i_3[5]\, \data_addr_r_0_iv_i_1[5]\, - \data_addr_r_0_iv_i_0[5]\, - \data_addr_r_0_iv_i_RNO_2[5]_net_1\, sEmpty_RNI6M6A4J, - N_93, N_4, N_37, N_4_0, \time_mem_ren_i_0[0]\, N_35, - \data_mem_ren_i_0[2]\, \data_mem_ren_i_0[1]\, N_89, - \Waddr_vect[2]\, \Waddr_vect_0[2]\, - \time_mem_addr_w_1[0]\, \time_mem_addr_w_1[1]\, - \time_mem_addr_w_1[3]\, \time_mem_addr_w_3[0]\, - \time_mem_addr_w_3[1]\, \time_mem_addr_w_3[3]\, - \DWACT_FINC_E[0]\, \data_mem_addr_w_3[0]\, - \data_mem_addr_w_3[1]\, \data_mem_addr_w_3[2]\, - \data_mem_addr_w_3[3]\, \data_mem_addr_w_3[4]\, - \data_mem_addr_w_1[0]\, \data_mem_addr_w_1[1]\, - \data_mem_addr_w_1[2]\, \data_mem_addr_w_1[3]\, - \data_mem_addr_w_1[4]\, \time_mem_addr_r_3[3]\, - \time_mem_addr_r_3[0]\, \time_mem_addr_r_3[1]\, - \Raddr_vect[2]\, \Raddr_vect_0[2]\, - \time_mem_addr_r_1[1]\, \time_mem_addr_r_1[0]\, - \time_mem_addr_r_1[3]\, \data_mem_addr_r_3[0]\, - \data_mem_addr_r_3[1]\, \data_mem_addr_r_3[2]\, - \data_mem_addr_r_3[3]\, \data_mem_addr_r_3[4]\, - \data_mem_addr_r_1[0]\, \data_mem_addr_r_1[1]\, - \data_mem_addr_r_1[2]\, \data_mem_addr_r_1[3]\, - \data_mem_addr_r_1[4]\, \DWACT_FINC_E_0[0]\, - \Raddr_vect_1[2]\, \time_mem_addr_r_2[0]\, - \time_mem_addr_r_2[1]\, \time_mem_addr_r_2[3]\, - \time_mem_addr_r_2[4]\, \data_mem_ren_i_0[0]\, - \data_mem_ren_i_0[3]\, \time_mem_addr_r_3_i_0[2]\, - \time_mem_addr_r_3_i_0[5]\, \time_mem_addr_w_3_i_0[2]\, - \time_mem_addr_w_3_i_0[5]\, \data_mem_wen_i_0[0]\, - \data_mem_wen_i_0[1]\, \data_mem_wen_i_0[2]\, - \data_mem_wen_i_0[3]\, \Waddr_vect_1[2]\, - \data_mem_addr_w_0[0]\, \data_mem_addr_w_0[1]\, - \data_mem_addr_w_0[2]\, \data_mem_addr_w_0[3]\, - \data_mem_addr_w_0[4]\, \time_mem_wen_i_0[1]\, - \time_mem_wen_i_0[3]\, \time_mem_wen_i_0[0]\, - \time_mem_addr_w_0[1]\, \time_mem_addr_w_0[3]\, - \time_mem_addr_w_0[4]\, \time_mem_addr_w_0[0]\, - \time_mem_addr_w_2[4]\, \time_mem_addr_w_2[3]\, - \time_mem_addr_w_2[1]\, \time_mem_addr_w_2[0]\, - \data_mem_addr_w_2[0]\, \data_mem_addr_w_2[1]\, - \data_mem_addr_w_2[2]\, \data_mem_addr_w_2[3]\, - \data_mem_addr_w_2[4]\, \time_mem_ren_i_0[3]\, - \time_mem_ren_i_0[1]\, \time_mem_addr_r_0[4]\, - \time_mem_addr_r_0[3]\, \time_mem_addr_r_0[0]\, - \time_mem_addr_r_0[1]\, \data_mem_addr_r_0[0]\, - \data_mem_addr_r_0[1]\, \data_mem_addr_r_0[2]\, - \data_mem_addr_r_0[3]\, \data_mem_addr_r_0[4]\, - \data_mem_addr_r_2[0]\, \data_mem_addr_r_2[1]\, - \data_mem_addr_r_2[2]\, \data_mem_addr_r_2[3]\, - \data_mem_addr_r_2[4]\, sFull_RNIODA01_0, sFull_RNIKQ9G, - sFull_RNIE8AH1, N_158, N_4_1, N_88, sEmpty_RNIU5CB661, - sEmpty_RNI6M6A4J_0, N_4_2, N_115, N_117, N_157, N_162, - N_161, N_165, sEmpty_RNIPJ7A8P1, N_156, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - - for all : lpp_waveform_fifo_ctrlZ1 - Use entity work.lpp_waveform_fifo_ctrlZ1(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ7 - Use entity work.lpp_waveform_fifo_ctrlZ7(DEF_ARCH); - for all : syncram_2pZ2 - Use entity work.syncram_2pZ2(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ2 - Use entity work.lpp_waveform_fifo_ctrlZ2(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ5 - Use entity work.lpp_waveform_fifo_ctrlZ5(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ3 - Use entity work.lpp_waveform_fifo_ctrlZ3(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ0 - Use entity work.lpp_waveform_fifo_ctrlZ0(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ4 - Use entity work.lpp_waveform_fifo_ctrlZ4(DEF_ARCH); - for all : lpp_waveform_fifo_ctrlZ6 - Use entity work.lpp_waveform_fifo_ctrlZ6(DEF_ARCH); -begin - - - \gen_fifo_ctrl_data.1.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ1 - port map(ready_i_0_i_0(1) => ready_i_0_i_0(1), - data_mem_wen_i_0(1) => \data_mem_wen_i_0[1]\, data_ren(1) - => data_ren(1), data_mem_ren_i_0(1) => - \data_mem_ren_i_0[1]\, data_wen(1) => data_wen(1), - data_mem_addr_r_1(4) => \data_mem_addr_r_1[4]\, - data_mem_addr_r_1(3) => \data_mem_addr_r_1[3]\, - data_mem_addr_r_1(2) => \data_mem_addr_r_1[2]\, - data_mem_addr_r_1(1) => \data_mem_addr_r_1[1]\, - data_mem_addr_r_1(0) => \data_mem_addr_r_1[0]\, - data_mem_addr_w_1(4) => \data_mem_addr_w_1[4]\, - data_mem_addr_w_1(3) => \data_mem_addr_w_1[3]\, - data_mem_addr_w_1(2) => \data_mem_addr_w_1[2]\, - data_mem_addr_w_1(1) => \data_mem_addr_w_1[1]\, - data_mem_addr_w_1(0) => \data_mem_addr_w_1[0]\, - data_ren_1z => data_ren_1z, rstn => rstn, lclk_c => - lclk_c, N_158 => N_158, sFull_RNIE8AH1 => sFull_RNIE8AH1, - sEmpty_RNI6M6A4J_0 => sEmpty_RNI6M6A4J_0, - sEmpty_RNIU5CB661 => sEmpty_RNIU5CB661, un20_time_write - => un20_time_write); - - \data_addr_r_0_iv_i_RNO_1[5]\ : OA1B - port map(A => N_93, B => N_4, C => N_37, Y => - \data_addr_r_0_iv_i_1[5]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \gen_fifo_ctrl_time.3.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ7 - port map(time_mem_wen_i_0(3) => \time_mem_wen_i_0[3]\, - time_mem_ren_i_0(3) => \time_mem_ren_i_0[3]\, - time_mem_addr_w_3_i_0_3 => \time_mem_addr_w_3_i_0[5]\, - time_mem_addr_w_3_i_0_0 => \time_mem_addr_w_3_i_0[2]\, - time_mem_addr_r_3_i_0_3 => \time_mem_addr_r_3_i_0[5]\, - time_mem_addr_r_3_i_0_0 => \time_mem_addr_r_3_i_0[2]\, - time_wen(3) => time_wen(3), time_ren(3) => time_ren(3), - time_mem_addr_w_3_3 => \time_mem_addr_w_3[3]\, - time_mem_addr_w_3_0 => \time_mem_addr_w_3[0]\, - time_mem_addr_w_3_1 => \time_mem_addr_w_3[1]\, - time_mem_addr_r_3_3 => \time_mem_addr_r_3[3]\, - time_mem_addr_r_3_0 => \time_mem_addr_r_3[0]\, - time_mem_addr_r_3_1 => \time_mem_addr_r_3[1]\, - time_ren_1z => time_ren_1z, rstn => rstn, lclk_c => - lclk_c, N_156 => N_156, N_157 => N_157, sFull_RNIODA01_0 - => sFull_RNIODA01_0, N_117 => N_117, un5_time_write => - un5_time_write, N_89 => N_89, N_88 => N_88, N_37 => N_37); - - SRAM : syncram_2pZ2 - port map(wdata(31) => wdata(31), wdata(30) => wdata(30), - wdata(29) => wdata(29), wdata(28) => wdata(28), wdata(27) - => wdata(27), wdata(26) => wdata(26), wdata(25) => - wdata(25), wdata(24) => wdata(24), wdata(23) => wdata(23), - wdata(22) => wdata(22), wdata(21) => wdata(21), wdata(20) - => wdata(20), wdata(19) => wdata(19), wdata(18) => - wdata(18), wdata(17) => wdata(17), wdata(16) => wdata(16), - wdata(15) => wdata(15), wdata(14) => wdata(14), wdata(13) - => wdata(13), wdata(12) => wdata(12), wdata(11) => - wdata(11), wdata(10) => wdata(10), wdata(9) => wdata(9), - wdata(8) => wdata(8), wdata(7) => wdata(7), wdata(6) => - wdata(6), wdata(5) => wdata(5), wdata(4) => wdata(4), - wdata(3) => wdata(3), wdata(2) => wdata(2), wdata(1) => - wdata(1), wdata(0) => wdata(0), hwdata(31) => hwdata(31), - hwdata(30) => hwdata(30), hwdata(29) => hwdata(29), - hwdata(28) => hwdata(28), hwdata(27) => hwdata(27), - hwdata(26) => hwdata(26), hwdata(25) => hwdata(25), - hwdata(24) => hwdata(24), hwdata(23) => hwdata(23), - hwdata(22) => hwdata(22), hwdata(21) => hwdata(21), - hwdata(20) => hwdata(20), hwdata(19) => hwdata(19), - hwdata(18) => hwdata(18), hwdata(17) => hwdata(17), - hwdata(16) => hwdata(16), hwdata(15) => hwdata(15), - hwdata(14) => hwdata(14), hwdata(13) => hwdata(13), - hwdata(12) => hwdata(12), hwdata(11) => hwdata(11), - hwdata(10) => hwdata(10), hwdata(9) => hwdata(9), - hwdata(8) => hwdata(8), hwdata(7) => hwdata(7), hwdata(6) - => hwdata(6), hwdata(5) => hwdata(5), hwdata(4) => - hwdata(4), hwdata(3) => hwdata(3), hwdata(2) => hwdata(2), - hwdata(1) => hwdata(1), hwdata(0) => hwdata(0), - Waddr_vect_1(2) => \Waddr_vect[2]\, Waddr_vect_0(2) => - \Waddr_vect_0[2]\, time_mem_addr_w_1_0 => - \time_mem_addr_w_1[0]\, time_mem_addr_w_1_1 => - \time_mem_addr_w_1[1]\, time_mem_addr_w_1_3 => - \time_mem_addr_w_1[3]\, time_mem_addr_w_3_0 => - \time_mem_addr_w_3[0]\, time_mem_addr_w_3_1 => - \time_mem_addr_w_3[1]\, time_mem_addr_w_3_3 => - \time_mem_addr_w_3[3]\, DWACT_FINC_E_0(0) => - \DWACT_FINC_E[0]\, data_mem_addr_w_3(4) => - \data_mem_addr_w_3[4]\, data_mem_addr_w_3(3) => - \data_mem_addr_w_3[3]\, data_mem_addr_w_3(2) => - \data_mem_addr_w_3[2]\, data_mem_addr_w_3(1) => - \data_mem_addr_w_3[1]\, data_mem_addr_w_3(0) => - \data_mem_addr_w_3[0]\, data_mem_addr_w_1(4) => - \data_mem_addr_w_1[4]\, data_mem_addr_w_1(3) => - \data_mem_addr_w_1[3]\, data_mem_addr_w_1(2) => - \data_mem_addr_w_1[2]\, data_mem_addr_w_1(1) => - \data_mem_addr_w_1[1]\, data_mem_addr_w_1(0) => - \data_mem_addr_w_1[0]\, time_mem_addr_r_3_3 => - \time_mem_addr_r_3[3]\, time_mem_addr_r_3_0 => - \time_mem_addr_r_3[0]\, time_mem_addr_r_3_1 => - \time_mem_addr_r_3[1]\, Raddr_vect_1(2) => - \Raddr_vect[2]\, Raddr_vect_0(2) => \Raddr_vect_0[2]\, - time_mem_addr_r_1_1 => \time_mem_addr_r_1[1]\, - time_mem_addr_r_1_0 => \time_mem_addr_r_1[0]\, - time_mem_addr_r_1_3 => \time_mem_addr_r_1[3]\, - data_mem_addr_r_3(4) => \data_mem_addr_r_3[4]\, - data_mem_addr_r_3(3) => \data_mem_addr_r_3[3]\, - data_mem_addr_r_3(2) => \data_mem_addr_r_3[2]\, - data_mem_addr_r_3(1) => \data_mem_addr_r_3[1]\, - data_mem_addr_r_3(0) => \data_mem_addr_r_3[0]\, - data_mem_addr_r_1(4) => \data_mem_addr_r_1[4]\, - data_mem_addr_r_1(3) => \data_mem_addr_r_1[3]\, - data_mem_addr_r_1(2) => \data_mem_addr_r_1[2]\, - data_mem_addr_r_1(1) => \data_mem_addr_r_1[1]\, - data_mem_addr_r_1(0) => \data_mem_addr_r_1[0]\, - DWACT_FINC_E(0) => \DWACT_FINC_E_0[0]\, Raddr_vect(2) => - \Raddr_vect_1[2]\, time_mem_addr_r_2_0 => - \time_mem_addr_r_2[0]\, time_mem_addr_r_2_1 => - \time_mem_addr_r_2[1]\, time_mem_addr_r_2_3 => - \time_mem_addr_r_2[3]\, time_mem_addr_r_2_4 => - \time_mem_addr_r_2[4]\, data_mem_ren_i_0(3) => - \data_mem_ren_i_0[3]\, data_mem_ren_i_0(2) => - \data_mem_ren_i_0[2]\, data_mem_ren_i_0(1) => - \data_mem_ren_i_0[1]\, data_mem_ren_i_0(0) => - \data_mem_ren_i_0[0]\, time_mem_addr_r_3_i_0_0 => - \time_mem_addr_r_3_i_0[2]\, time_mem_addr_r_3_i_0_3 => - \time_mem_addr_r_3_i_0[5]\, time_mem_addr_w_3_i_0_0 => - \time_mem_addr_w_3_i_0[2]\, time_mem_addr_w_3_i_0_3 => - \time_mem_addr_w_3_i_0[5]\, data_mem_wen_i_0(3) => - \data_mem_wen_i_0[3]\, data_mem_wen_i_0(2) => - \data_mem_wen_i_0[2]\, data_mem_wen_i_0(1) => - \data_mem_wen_i_0[1]\, data_mem_wen_i_0(0) => - \data_mem_wen_i_0[0]\, Waddr_vect(2) => \Waddr_vect_1[2]\, - data_mem_addr_w_0(4) => \data_mem_addr_w_0[4]\, - data_mem_addr_w_0(3) => \data_mem_addr_w_0[3]\, - data_mem_addr_w_0(2) => \data_mem_addr_w_0[2]\, - data_mem_addr_w_0(1) => \data_mem_addr_w_0[1]\, - data_mem_addr_w_0(0) => \data_mem_addr_w_0[0]\, - time_mem_wen_i_0_1 => \time_mem_wen_i_0[1]\, - time_mem_wen_i_0_3 => \time_mem_wen_i_0[3]\, - time_mem_wen_i_0_0 => \time_mem_wen_i_0[0]\, - time_mem_addr_w_0_1 => \time_mem_addr_w_0[1]\, - time_mem_addr_w_0_3 => \time_mem_addr_w_0[3]\, - time_mem_addr_w_0_4 => \time_mem_addr_w_0[4]\, - time_mem_addr_w_0_0 => \time_mem_addr_w_0[0]\, - time_mem_addr_w_2_4 => \time_mem_addr_w_2[4]\, - time_mem_addr_w_2_3 => \time_mem_addr_w_2[3]\, - time_mem_addr_w_2_1 => \time_mem_addr_w_2[1]\, - time_mem_addr_w_2_0 => \time_mem_addr_w_2[0]\, - data_mem_addr_w_2(4) => \data_mem_addr_w_2[4]\, - data_mem_addr_w_2(3) => \data_mem_addr_w_2[3]\, - data_mem_addr_w_2(2) => \data_mem_addr_w_2[2]\, - data_mem_addr_w_2(1) => \data_mem_addr_w_2[1]\, - data_mem_addr_w_2(0) => \data_mem_addr_w_2[0]\, - time_mem_ren_i_0_3 => \time_mem_ren_i_0[3]\, - time_mem_ren_i_0_1 => \time_mem_ren_i_0[1]\, - time_mem_ren_i_0_0 => \time_mem_ren_i_0[0]\, - time_mem_addr_r_0_4 => \time_mem_addr_r_0[4]\, - time_mem_addr_r_0_3 => \time_mem_addr_r_0[3]\, - time_mem_addr_r_0_0 => \time_mem_addr_r_0[0]\, - time_mem_addr_r_0_1 => \time_mem_addr_r_0[1]\, - data_mem_addr_r_0(4) => \data_mem_addr_r_0[4]\, - data_mem_addr_r_0(3) => \data_mem_addr_r_0[3]\, - data_mem_addr_r_0(2) => \data_mem_addr_r_0[2]\, - data_mem_addr_r_0(1) => \data_mem_addr_r_0[1]\, - data_mem_addr_r_0(0) => \data_mem_addr_r_0[0]\, - data_mem_addr_r_2(4) => \data_mem_addr_r_2[4]\, - data_mem_addr_r_2(3) => \data_mem_addr_r_2[3]\, - data_mem_addr_r_2(2) => \data_mem_addr_r_2[2]\, - data_mem_addr_r_2(1) => \data_mem_addr_r_2[1]\, - data_mem_addr_r_2(0) => \data_mem_addr_r_2[0]\, N_64_i_0 - => N_64_i_0, lclk_c => lclk_c, sFull_RNIODA01_0 => - sFull_RNIODA01_0, sFull_RNIKQ9G => sFull_RNIKQ9G, - sFull_RNIE8AH1 => sFull_RNIE8AH1, N_158 => N_158, N_4_0 - => N_4_1, N_88 => N_88, sEmpty_RNIU5CB661 => - sEmpty_RNIU5CB661, sEmpty_RNI6M6A4J_0 => - sEmpty_RNI6M6A4J_0, N_4 => N_4_2, N_115 => N_115, N_117 - => N_117, N_93 => N_93, N_35 => N_35, N_37 => N_37, - N_157 => N_157, N_162 => N_162, N_161 => N_161, N_165 => - N_165, sEmpty_RNI6M6A4J => sEmpty_RNI6M6A4J, - sEmpty_RNIPJ7A8P1 => sEmpty_RNIPJ7A8P1); - - \data_addr_r_0_iv_i_RNO_0[5]\ : AND2 - port map(A => \data_addr_r_0_iv_i_1[5]\, B => - \data_addr_r_0_iv_i_0[5]\, Y => \data_addr_r_0_iv_i_3[5]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_addr_r_0_iv_i_RNO[5]\ : NOR2A - port map(A => \data_addr_r_0_iv_i_RNO_2[5]_net_1\, B => - sEmpty_RNI6M6A4J, Y => \data_addr_r_0_iv_i_2[5]\); - - \gen_fifo_ctrl_data.2.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ2 - port map(ready_i_0(2) => ready_i_0_2, data_mem_wen_i_0(2) - => \data_mem_wen_i_0[2]\, data_ren(2) => data_ren(2), - data_mem_ren_i_0(2) => \data_mem_ren_i_0[2]\, data_wen(2) - => data_wen(2), data_mem_addr_r_2(4) => - \data_mem_addr_r_2[4]\, data_mem_addr_r_2(3) => - \data_mem_addr_r_2[3]\, data_mem_addr_r_2(2) => - \data_mem_addr_r_2[2]\, data_mem_addr_r_2(1) => - \data_mem_addr_r_2[1]\, data_mem_addr_r_2(0) => - \data_mem_addr_r_2[0]\, data_mem_addr_w_2(4) => - \data_mem_addr_w_2[4]\, data_mem_addr_w_2(3) => - \data_mem_addr_w_2[3]\, data_mem_addr_w_2(2) => - \data_mem_addr_w_2[2]\, data_mem_addr_w_2(1) => - \data_mem_addr_w_2[1]\, data_mem_addr_w_2(0) => - \data_mem_addr_w_2[0]\, data_ren_1z => data_ren_1z, rstn - => rstn, lclk_c => lclk_c, sFull_RNIE8AH1 => - sFull_RNIE8AH1, N_165 => N_165, sEmpty_RNIU5CB661 => - sEmpty_RNIU5CB661, sEmpty_RNIPJ7A8P1 => sEmpty_RNIPJ7A8P1, - un13_time_write => un13_time_write); - - GND_i : GND - port map(Y => \GND\); - - \gen_fifo_ctrl_time.1.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ5 - port map(time_mem_wen_i_0(1) => \time_mem_wen_i_0[1]\, - time_mem_wen_i_0(0) => \time_mem_wen_i_0[0]\, - time_mem_ren_i_0(1) => \time_mem_ren_i_0[1]\, - time_mem_ren_i_0(0) => \time_mem_ren_i_0[0]\, time_wen(1) - => time_wen(1), time_ren(1) => time_ren(1), - time_mem_addr_w_1_3 => \time_mem_addr_w_1[3]\, - time_mem_addr_w_1_0 => \time_mem_addr_w_1[0]\, - time_mem_addr_w_1_1 => \time_mem_addr_w_1[1]\, - time_mem_addr_r_1_3 => \time_mem_addr_r_1[3]\, - time_mem_addr_r_1_0 => \time_mem_addr_r_1[0]\, - time_mem_addr_r_1_1 => \time_mem_addr_r_1[1]\, - DWACT_FINC_E_0(0) => \DWACT_FINC_E[0]\, Waddr_vect_0 => - \Waddr_vect[2]\, DWACT_FINC_E(0) => \DWACT_FINC_E_0[0]\, - Raddr_vect_0 => \Raddr_vect_0[2]\, time_ren_1z => - time_ren_1z, rstn => rstn, lclk_c => lclk_c, - un20_time_write => un20_time_write, sFull_RNIKQ9G => - sFull_RNIKQ9G, N_115 => N_115, N_35 => N_35); - - \gen_fifo_ctrl_data.3.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ3 - port map(ready_i_0(3) => ready_i_0_3, data_mem_wen_i_0(3) - => \data_mem_wen_i_0[3]\, data_ren(3) => data_ren(3), - data_mem_ren_i_0(3) => \data_mem_ren_i_0[3]\, data_wen(3) - => data_wen(3), data_mem_addr_r_3(4) => - \data_mem_addr_r_3[4]\, data_mem_addr_r_3(3) => - \data_mem_addr_r_3[3]\, data_mem_addr_r_3(2) => - \data_mem_addr_r_3[2]\, data_mem_addr_r_3(1) => - \data_mem_addr_r_3[1]\, data_mem_addr_r_3(0) => - \data_mem_addr_r_3[0]\, data_mem_addr_w_3(4) => - \data_mem_addr_w_3[4]\, data_mem_addr_w_3(3) => - \data_mem_addr_w_3[3]\, data_mem_addr_w_3(2) => - \data_mem_addr_w_3[2]\, data_mem_addr_w_3(1) => - \data_mem_addr_w_3[1]\, data_mem_addr_w_3(0) => - \data_mem_addr_w_3[0]\, data_ren_1z => data_ren_1z, rstn - => rstn, lclk_c => lclk_c, un5_time_write => - un5_time_write); - - \gen_fifo_ctrl_data.0.lpp_waveform_fifo_ctrl_data\ : - lpp_waveform_fifo_ctrlZ0 - port map(ready_i_0(0) => ready_i_0_0, data_mem_wen_i_0(0) - => \data_mem_wen_i_0[0]\, data_mem_ren_i_0(0) => - \data_mem_ren_i_0[0]\, data_ren(0) => data_ren(0), - data_wen(0) => data_wen(0), data_mem_addr_r_0(4) => - \data_mem_addr_r_0[4]\, data_mem_addr_r_0(3) => - \data_mem_addr_r_0[3]\, data_mem_addr_r_0(2) => - \data_mem_addr_r_0[2]\, data_mem_addr_r_0(1) => - \data_mem_addr_r_0[1]\, data_mem_addr_r_0(0) => - \data_mem_addr_r_0[0]\, data_mem_addr_w_0(4) => - \data_mem_addr_w_0[4]\, data_mem_addr_w_0(3) => - \data_mem_addr_w_0[3]\, data_mem_addr_w_0(2) => - \data_mem_addr_w_0[2]\, data_mem_addr_w_0(1) => - \data_mem_addr_w_0[1]\, data_mem_addr_w_0(0) => - \data_mem_addr_w_0[0]\, rstn => rstn, lclk_c => lclk_c, - N_162 => N_162, N_157 => N_157, N_158 => N_158, - sEmpty_RNI6M6A4J => sEmpty_RNI6M6A4J, N_89 => N_89, - sEmpty_RNI6M6A4J_0 => sEmpty_RNI6M6A4J_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_addr_r_0_iv_i_RNO_2[5]\ : OR3A - port map(A => \data_mem_ren_i_0[2]\, B => - \data_mem_ren_i_0[1]\, C => N_89, Y => - \data_addr_r_0_iv_i_RNO_2[5]_net_1\); - - \gen_fifo_ctrl_time.0.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ4 - port map(time_mem_wen_i_0(0) => \time_mem_wen_i_0[0]\, - time_mem_ren_i_0(0) => \time_mem_ren_i_0[0]\, time_wen(0) - => time_wen(0), time_ren(0) => time_ren(0), Waddr_vect_0 - => \Waddr_vect_0[2]\, time_mem_addr_w_0_3 => - \time_mem_addr_w_0[3]\, time_mem_addr_w_0_0 => - \time_mem_addr_w_0[0]\, time_mem_addr_w_0_1 => - \time_mem_addr_w_0[1]\, time_mem_addr_w_0_4 => - \time_mem_addr_w_0[4]\, Raddr_vect_0 => \Raddr_vect_1[2]\, - time_mem_addr_r_0_3 => \time_mem_addr_r_0[3]\, - time_mem_addr_r_0_0 => \time_mem_addr_r_0[0]\, - time_mem_addr_r_0_1 => \time_mem_addr_r_0[1]\, - time_mem_addr_r_0_4 => \time_mem_addr_r_0[4]\, - time_ren_1z => time_ren_1z, rstn => rstn, lclk_c => - lclk_c, un27_time_write => un27_time_write, N_4_0 => - N_4_1, N_4 => N_4_0); - - \gen_fifo_ctrl_time.2.lpp_waveform_fifo_ctrl_time\ : - lpp_waveform_fifo_ctrlZ6 - port map(time_mem_wen_i_0_1 => \time_mem_wen_i_0[1]\, - time_mem_wen_i_0_0 => \time_mem_wen_i_0[0]\, - time_mem_ren_i_0_1 => \time_mem_ren_i_0[1]\, - time_mem_ren_i_0_0 => \time_mem_ren_i_0[0]\, time_wen(2) - => time_wen(2), time_ren(2) => time_ren(2), Waddr_vect_0 - => \Waddr_vect_1[2]\, time_mem_addr_w_2_3 => - \time_mem_addr_w_2[3]\, time_mem_addr_w_2_0 => - \time_mem_addr_w_2[0]\, time_mem_addr_w_2_1 => - \time_mem_addr_w_2[1]\, time_mem_addr_w_2_4 => - \time_mem_addr_w_2[4]\, Raddr_vect_0 => \Raddr_vect[2]\, - time_mem_addr_r_2_3 => \time_mem_addr_r_2[3]\, - time_mem_addr_r_2_0 => \time_mem_addr_r_2[0]\, - time_mem_addr_r_2_1 => \time_mem_addr_r_2[1]\, - time_mem_addr_r_2_4 => \time_mem_addr_r_2[4]\, rstn => - rstn, lclk_c => lclk_c, N_161 => N_161, N_156 => N_156, - N_93 => N_93, N_88 => N_88, N_4_0 => N_4_2, N_4 => N_4); - - \data_addr_r_0_iv_i_RNO_3[5]\ : OA1B - port map(A => N_4_0, B => \time_mem_ren_i_0[0]\, C => N_35, - Y => \data_addr_r_0_iv_i_0[5]\); - - \data_addr_r_0_iv_i[5]\ : AND2 - port map(A => \data_addr_r_0_iv_i_2[5]\, B => - \data_addr_r_0_iv_i_3[5]\, Y => N_64_i_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_11 is - - port( sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - data_f0_out : out std_logic_vector(159 downto 64); - sample_f0_37 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_63 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_0 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_15 : in std_logic; - nb_snapshot_param : in std_logic_vector(10 downto 0); - rstn : in std_logic; - lclk_c : in std_logic; - data_f0_out_valid : out std_logic; - data_shaping_R0 : in std_logic; - data_shaping_R0_0 : in std_logic; - enable_f0 : in std_logic; - start_snapshot_f0 : in std_logic; - sample_f0_val_0 : in std_logic; - burst_f0 : in std_logic - ); - -end lpp_waveform_snapshot_160_11; - -architecture DEF_ARCH of lpp_waveform_snapshot_160_11 is - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \un1_data_out_valid_0_sqmuxa_1_3[31]\, - \counter_points_snapshot_0_sqmuxa_1_0\, - data_out_valid_0_sqmuxa_1, - \un1_data_out_valid_0_sqmuxa_1_2[31]\, - \un1_data_out_valid_0_sqmuxa_1_1[31]\, - \un1_data_out_valid_0_sqmuxa_1_0[31]\, - \data_out_valid_0_sqmuxa\, ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, - ADD_32x32_fast_I311_Y_0_0, - \counter_points_snapshot[31]_net_1\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I253_Y_0_0, N_43, N485, N481, - ADD_32x32_fast_I250_Y_3, N603, N618, - ADD_32x32_fast_I250_Y_2, N546, N539, - ADD_32x32_fast_I250_Y_1, N479, N476, - ADD_32x32_fast_I250_Y_0, \un1_counter_points_snapshot[1]\, - I32_un1_Y, ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I300_Y_0_0, - \un1_counter_points_snapshot[11]\, - ADD_32x32_fast_I309_Y_0_0, - \un1_counter_points_snapshot[2]\, - ADD_32x32_fast_I253_Y_0_a2_0, N486, - ADD_32x32_fast_I295_Y_0_0, - \un1_counter_points_snapshot[16]\, - ADD_32x32_fast_I250_un1_Y_0, N619, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I310_Y_0_0, ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, - ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot[5]\, ADD_32x32_fast_I252_Y_2, - N622, N607, ADD_32x32_fast_I252_Y_1, N543, N550, - ADD_32x32_fast_I252_Y_0, N483, ADD_32x32_fast_I301_Y_0_0, - \un1_counter_points_snapshot[10]\, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I251_Y_3, N605, N620, - ADD_32x32_fast_I251_Y_2, N548, N541, - ADD_32x32_fast_I251_Y_1, N464, ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I302_Y_0_0, - \un1_counter_points_snapshot[9]\, ADD_32x32_fast_I254_Y_1, - N626, N611, ADD_32x32_fast_I254_Y_0, N554, N547, - ADD_32x32_fast_I256_Y_1, N630, N615, - ADD_32x32_fast_I256_Y_0, N558, N551, - ADD_32x32_fast_I255_Y_0, N556, N549, - ADD_32x32_fast_I291_Y_0_0, - \un1_counter_points_snapshot[20]\, - ADD_32x32_fast_I293_Y_0_0, - \un1_counter_points_snapshot[18]\, - ADD_32x32_fast_I252_un1_Y_0, N623, - ADD_32x32_fast_I264_Y_0, N646, N631, - ADD_32x32_fast_I294_Y_0_0, - \un1_counter_points_snapshot[17]\, - ADD_32x32_fast_I289_Y_0_0, - \un1_counter_points_snapshot[22]\, - ADD_32x32_fast_I254_un1_Y_0, N627, - ADD_32x32_fast_I251_un1_Y_0, N621, - ADD_32x32_fast_I256_un1_Y_0, ADD_32x32_fast_I290_Y_0_0, - \un1_counter_points_snapshot[21]\, - ADD_32x32_fast_I255_un1_Y_0, N629, N557, - ADD_32x32_fast_I264_un1_Y_0, N583, N528, N380, - ADD_32x32_fast_I285_Y_0_0, - \un1_counter_points_snapshot[26]\, - ADD_32x32_fast_I286_Y_0_0, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I283_Y_0_0, - \un1_counter_points_snapshot[28]\, - ADD_32x32_fast_I126_Y_0, ADD_32x32_fast_I118_Y_0, - ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[23]\, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I119_Y_0, - \counter_points_snapshot[14]_net_1\, - ADD_32x32_fast_I135_Y_0, - \un1_counter_points_snapshot[24]\, ADD_32x32_fast_I95_Y_0, - \counter_points_snapshot[29]_net_1\, - \counter_points_snapshot[28]_net_1\, - data_out_valid_0_sqmuxa_1_1, un4_data_in_validlt30_27, - un4_data_in_validlt30_18, un4_data_in_validlt30_17, - un4_data_in_validlt30_23, un4_data_in_validlt30_26, - un4_data_in_validlt30_12, un4_data_in_validlt30_11, - un4_data_in_validlt30_22, un4_data_in_validlt30_25, - un4_data_in_validlt30_8, un4_data_in_validlt30_7, - un4_data_in_validlt30_20, un4_data_in_validlt30_2, - un4_data_in_validlt30_1, un4_data_in_validlt30_15, - un4_data_in_validlt30_14, - \counter_points_snapshot[26]_net_1\, - \counter_points_snapshot[23]_net_1\, - un4_data_in_validlt30_10, - \counter_points_snapshot[20]_net_1\, - \counter_points_snapshot[19]_net_1\, - un4_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un4_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot_i_0[30]\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[27]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[21]_net_1\, - \counter_points_snapshot[22]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[18]_net_1\, - \counter_points_snapshot[15]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[13]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, N750, N789, N443_i, - I50_un1_Y_i, I110_un1_Y, N744, N752, N756, I222_un1_Y, - I259_un1_Y, N637, N652, N588, N529, N526, N766, N581, - N518, N580, N521, N572, I126_un1_Y, N573, N510, N411, - N414, N444, N441, N_8, N565, N502, N564, N505, N738, N771, - I262_un1_Y, N643, N594, N762, I228_un1_Y, - un4_data_in_validlto30_i, - \un1_data_out_valid_0_sqmuxa_2[7]\, N650, - \un1_data_out_valid_0_sqmuxa_2[5]\, N654, - \un1_data_out_valid_0_sqmuxa_2[9]\, - \un1_data_out_valid_0_sqmuxa_2[10]\, I240_un1_Y, N644, - N746, N783, N740, N774, N748, I255_un1_Y, I214_un1_Y, - N742, N777, \un1_data_out_valid_0_sqmuxa_2[4]\, N592_i, - N754, I220_un1_Y, I258_un1_Y, N635, - \un1_data_out_valid_0_sqmuxa_2[8]\, N648_i, - \un1_data_out_valid_0_sqmuxa_2[2]\, - \un1_counter_points_snapshot[29]\, N533, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, - \un1_data_out_valid_0_sqmuxa_2[3]\, - \un1_data_out_valid_0_sqmuxa_2[6]\, N758, I224_un1_Y, - I260_un1_Y, N639, ADD_32x32_fast_I263_Y_0, - ADD_32x32_fast_I263_un1_Y_0, N589, N764, N628, N516, N559, - N515, N636, \counter_points_snapshot_10[25]\, - un1_counter_points_snapshot_0_sqmuxa_1_i, N480, - \counter_points_snapshot_10[28]\, N489, N484, N487, N488, - N491, N446_i, N_6, N447, \counter_points_snapshot_10[24]\, - N492, I198_un1_Y, I176_un1_Y, N530, N562, N503, N500, - N499, I241_un1_Y, N590, I199_un1_Y, N582, N531, N527, - N496, N495, N504, N563, N555, N524, N520, N523, N519, - N587, N586, N579, N578, \counter_points_snapshot_10[14]\, - N508, N511, N512, N566, N507, N513, - \counter_points_snapshot_RNITNU94_3[31]_net_1\, N760_i, - \counter_points_snapshot_10[20]\, N575, N638, N574, N567, - N571, N570, N642, \un1_data_out_valid_0_sqmuxa_2[0]\, - \un1_counter_points_snapshot[31]\, N_276, - \counter_points_snapshot_2_sqmuxa\, N_281, N_283, - \counter_points_snapshot_10[0]\, - \counter_points_snapshot_10[5]\, - \counter_points_snapshot_10[7]\, - \counter_points_snapshot_10[15]\, - \counter_points_snapshot_10[19]\, - \counter_points_snapshot_10[31]\, \sample_f0_wdata[32]\, - \sample_f0_wdata[33]\, \sample_f0_wdata[34]\, - \sample_f0_wdata[35]\, \sample_f0_wdata[19]\, - \sample_f0_wdata[20]\, \sample_f0_wdata[21]\, - \sample_f0_wdata[22]\, \sample_f0_wdata[23]\, - \sample_f0_wdata[24]\, \sample_f0_wdata[25]\, - \sample_f0_wdata[26]\, \sample_f0_wdata[27]\, - \sample_f0_wdata[28]\, \sample_f0_wdata[29]\, - \sample_f0_wdata[30]\, \sample_f0_wdata[31]\, - \sample_f0_wdata[43]\, \sample_f0_wdata[44]\, - \sample_f0_wdata[45]\, \sample_f0_wdata[46]\, - \sample_f0_wdata[47]\, \sample_f0_wdata[16]\, - \sample_f0_wdata[17]\, \sample_f0_wdata[18]\, - \sample_f0_wdata[36]\, \sample_f0_wdata[37]\, - \sample_f0_wdata[38]\, \sample_f0_wdata[39]\, - \sample_f0_wdata[40]\, \sample_f0_wdata[41]\, - \sample_f0_wdata[42]\, \counter_points_snapshot_10[10]\, - N_286, \counter_points_snapshot_10[9]\, N_285, - \counter_points_snapshot_2_sqmuxa_2\, - \counter_points_snapshot_10[18]\, - \counter_points_snapshot_10[27]\, - \counter_points_snapshot_10[30]\, - counter_points_snapshot_0_sqmuxa_i, - \counter_points_snapshot_3_sqmuxa\, - \counter_points_snapshot_0_sqmuxa_1\, data_out_valid_19, - un1_enable_2, \counter_points_snapshot_10[29]\, - \counter_points_snapshot_10[26]\, - \counter_points_snapshot_10[13]\, - \counter_points_snapshot_10[23]\, - \counter_points_snapshot_10[22]\, - \counter_points_snapshot_10[4]\, N_280, N634, N_277, - N_278, N_279, N_284, \counter_points_snapshot_10[1]\, - \counter_points_snapshot_10[2]\, - \counter_points_snapshot_10[3]\, - \counter_points_snapshot_10[8]\, - \counter_points_snapshot_10[17]\, - \counter_points_snapshot_10[16]\, N768_i, - \counter_points_snapshot_10[6]\, N_282, N780_i, - \counter_points_snapshot_10[11]\, - \counter_points_snapshot_10[21]\, - \counter_points_snapshot_10[12]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - - \counter_points_snapshot_RNIJ1PE[29]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[29]_net_1\, Y => - \un1_counter_points_snapshot[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_0 : - NOR3B - port map(A => N549, B => N629, C => N557, Y => - ADD_32x32_fast_I255_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y : - OAI1 - port map(A => I240_un1_Y, B => N644, C => - ADD_32x32_fast_I255_un1_Y_0, Y => I255_un1_Y); - - \counter_points_snapshot_RNISMQU3[31]\ : NOR2 - port map(A => data_out_valid_0_sqmuxa_1_1, B => - un4_data_in_validlto30_i, Y => data_out_valid_0_sqmuxa_1); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[13]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[27]\, C => N592_i, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I179_Y : NOR2B - port map(A => N575, B => N567, Y => N631); - - \data_out[110]\ : DFN1C0 - port map(D => \sample_f0_wdata[46]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(110)); - - \counter_points_snapshot_RNITNU94[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \un1_data_out_valid_0_sqmuxa_1_0[31]\); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[10]\, B => - nb_snapshot_param(10), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_286); - - \counter_points_snapshot_RNO[27]\ : XA1C - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[27]\); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[28]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[28]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y_0 : - NOR2B - port map(A => N607, B => N623, Y => - ADD_32x32_fast_I252_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_P0N : OR2A - port map(A => \un1_counter_points_snapshot[11]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N441); - - data_out_valid_0_sqmuxa : NOR2B - port map(A => sample_f0_val_0, B => start_snapshot_f0, Y - => \data_out_valid_0_sqmuxa\); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762, B => ADD_32x32_fast_I299_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[19]\); - - \data_out_RNO[96]\ : MX2 - port map(A => sample_f0_15, B => sample_f0_47, S => - data_shaping_R0_0, Y => \sample_f0_wdata[32]\); - - \data_out[91]\ : DFN1C0 - port map(D => \sample_f0_wdata[27]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(91)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I143_Y : OR2B - port map(A => N530, B => N526, Y => N589); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f0_wdata_56, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1B - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I93_Y : NOR2A - port map(A => N476, B => N480, Y => N539); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : OA1B - port map(A => N783, B => ADD_32x32_fast_I254_un1_Y_0, C => - ADD_32x32_fast_I254_Y_1, Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : AO1 - port map(A => N586, B => N579, C => N578, Y => N642); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I101_Y : NOR2B - port map(A => N488, B => N484, Y => N547); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f0_wdata_66, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => \sample_f0_wdata[40]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : NOR2 - port map(A => N491, B => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => nb_snapshot_param(4), B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_280); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I167_Y : NOR2B - port map(A => N563, B => N555, Y => N619); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[1]\, B => - nb_snapshot_param(1), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_277); - - \data_out[102]\ : DFN1C0 - port map(D => \sample_f0_wdata[38]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I64_Y : OA1A - port map(A => \un1_counter_points_snapshot[18]\, B => - \un1_counter_points_snapshot[17]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N507); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : AO1B - port map(A => ADD_32x32_fast_I252_un1_Y_0, B => N777, C => - ADD_32x32_fast_I252_Y_2, Y => N742); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I113_Y : NOR2B - port map(A => N500, B => N496, Y => N559); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_283, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[2]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1B - port map(A => N780_i, B => ADD_32x32_fast_I292_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[12]\); - - \counter_points_snapshot_RNIL0A7[21]\ : NOR2 - port map(A => \counter_points_snapshot[21]_net_1\, B => - \counter_points_snapshot[22]_net_1\, Y => - un4_data_in_validlt30_10); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : AO1 - port map(A => N650, B => N635, C => N634, Y => N771); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I137_Y : NOR2 - port map(A => N524, B => N520, Y => N583); - - \data_out[93]\ : DFN1C0 - port map(D => \sample_f0_wdata[29]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(93)); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[4]_net_1\); - - counter_points_snapshot_2_sqmuxa : OR3B - port map(A => enable_f0, B => - \counter_points_snapshot_2_sqmuxa_2\, C => burst_f0, Y - => \counter_points_snapshot_2_sqmuxa\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I33_Y : AO1A - port map(A => \counter_points_snapshot_i_0[30]\, B => - \counter_points_snapshot[29]_net_1\, C => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N476); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f0_wdata_95, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => \sample_f0_wdata[41]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(105)); - - \counter_points_snapshot_RNIVE7T[15]\ : NOR3C - port map(A => un4_data_in_validlt30_8, B => - un4_data_in_validlt30_7, C => un4_data_in_validlt30_20, Y - => un4_data_in_validlt30_25); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[15]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f0_wdata_77, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_un1_Y_0 : - NOR2B - port map(A => N605, B => N621, Y => - ADD_32x32_fast_I251_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : AO1 - port map(A => N495, B => N492, C => N491, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OAI1 - port map(A => N524, B => N527, C => N523, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => \sample_f0_wdata[17]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(81)); - - \data_out_RNO[99]\ : MX2 - port map(A => sample_f0_12, B => sample_f0_44, S => - data_shaping_R0_0, Y => \sample_f0_wdata[35]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[1]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I310_Y_0_0); - - \data_out_RNO[104]\ : MX2 - port map(A => sample_f0_7, B => sample_f0_39, S => - data_shaping_R0, Y => \sample_f0_wdata[40]\); - - \counter_points_snapshot_RNINCIG[0]\ : MX2 - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[31]\); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : AOI1B - port map(A => N558, B => N551, C => N550, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - AO18 - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[16]\, C => N771, Y => N768_i); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f0_wdata_50, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I97_Y : NOR2A - port map(A => N484, B => N480, Y => N543); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : AO1A - port map(A => N571, B => N578, C => N570, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : AOI1 - port map(A => N507, B => N504, C => N503, Y => N566); - - \counter_points_snapshot_RNIG1PE[26]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot[5]\); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[27]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f0_wdata_79, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : OR2 - port map(A => N590, B => I199_un1_Y, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3B - port map(A => N443_i, B => I50_un1_Y_i, C => I110_un1_Y, Y - => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f0_wdata_48, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f0_wdata_60, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(124)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I65_Y : AO1A - port map(A => \un1_counter_points_snapshot[18]\, B => - \counter_points_snapshot[14]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N508); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f0_wdata_70, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : AO1B - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[25]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N523); - - \counter_points_snapshot_RNO[28]\ : XA1B - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[28]\); - - \data_out[83]\ : DFN1C0 - port map(D => \sample_f0_wdata[19]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : AOI1B - port map(A => N546, B => N539, C => ADD_32x32_fast_I250_Y_1, - Y => ADD_32x32_fast_I250_Y_2); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f0_wdata_58, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f0_wdata_51, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(115)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : AOI1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : - AOI1B - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_counter_points_snapshot[4]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N481); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y : - OR3B - port map(A => N643, B => N594, C => N627, Y => I262_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AO1B - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[15]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f0_wdata_68, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(132)); - - \counter_points_snapshot[30]\ : DFN1P0 - port map(D => \counter_points_snapshot_10[30]\, CLK => - lclk_c, PRE => rstn, Q => - \counter_points_snapshot_i_0[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I37_Y : OA1C - port map(A => \counter_points_snapshot[28]_net_1\, B => - \un1_counter_points_snapshot[4]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N480); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I228_un1_Y : - OR2A - port map(A => N642, B => N627, Y => I228_un1_Y); - - \counter_points_snapshot_RNII1PE[28]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I69_Y : OA1A - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, C => N414, Y => - N512); - - \data_out[96]\ : DFN1C0 - port map(D => \sample_f0_wdata[32]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(96)); - - \counter_points_snapshot_RNIRKIG[2]\ : MX2C - port map(A => nb_snapshot_param(2), B => - \counter_points_snapshot[2]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[29]\); - - \counter_points_snapshot_RNIH1PE[27]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - \counter_points_snapshot_RNIETOE[17]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : OR3C - port map(A => I255_un1_Y, B => ADD_32x32_fast_I255_Y_0, C - => I214_un1_Y, Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f0_wdata_61, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(125)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I185_Y : NOR2 - port map(A => N581, B => N573, Y => N637); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f0_wdata_71, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(135)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I224_un1_Y : - NOR2B - port map(A => N638, B => N623, Y => I224_un1_Y); - - \data_out_RNO[87]\ : NOR2B - port map(A => sample_f0_56, B => data_shaping_R0_0, Y => - \sample_f0_wdata[23]\); - - \data_out_RNO[108]\ : MX2 - port map(A => sample_f0_3, B => sample_f0_35, S => - data_shaping_R0, Y => \sample_f0_wdata[44]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_un1_Y : - OR3C - port map(A => N621, B => N637, C => N652, Y => I259_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I290_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : OA1B - port map(A => N752, B => ADD_32x32_fast_I253_Y_0_a2_0, C - => ADD_32x32_fast_I253_Y_0_0, Y => N744); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I75_Y : AO1D - port map(A => \un1_counter_points_snapshot[23]\, B => - \un1_counter_points_snapshot[22]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N518); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I129_Y : NOR2A - port map(A => N512, B => N516, Y => N575); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y : NOR2B - port map(A => ADD_32x32_fast_I119_Y_0, B => N502, Y => N565); - - \counter_points_snapshot_RNI35JG[6]\ : MX2C - port map(A => nb_snapshot_param(6), B => - \counter_points_snapshot[6]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[25]\); - - \counter_points_snapshot_RNI31A7[28]\ : NOR2 - port map(A => \counter_points_snapshot[28]_net_1\, B => - \counter_points_snapshot[29]_net_1\, Y => - un4_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I171_Y : NOR2B - port map(A => N567, B => N559, Y => N623); - - data_out_valid : DFN1C0 - port map(D => data_out_valid_19, CLK => lclk_c, CLR => rstn, - Q => data_f0_out_valid); - - \data_out_RNO[90]\ : NOR2B - port map(A => sample_f0_53, B => data_shaping_R0_0, Y => - \sample_f0_wdata[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : AOI1 - port map(A => N570, B => N563, C => N562, Y => N626); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I29_G0N : OR2B - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[2]\, Y => I32_un1_Y); - - \counter_points_snapshot_RNID1PE[23]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f0_wdata_7, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f0_wdata_1, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[18]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : NOR3 - port map(A => I224_un1_Y, B => N622, C => I260_un1_Y, Y => - N758); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I45_Y : AO1A - port map(A => \un1_counter_points_snapshot[7]\, B => - \counter_points_snapshot[23]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N488); - - \data_out_RNO[98]\ : MX2 - port map(A => sample_f0_13, B => sample_f0_45, S => - data_shaping_R0_0, Y => \sample_f0_wdata[34]\); - - \data_out[86]\ : DFN1C0 - port map(D => \sample_f0_wdata[22]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(86)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : AOI1 - port map(A => N562, B => N555, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f0_wdata_86, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(150)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f0_wdata_84, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(148)); - - GND_i : GND - port map(Y => \GND\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I49_Y : NOR2B - port map(A => N447, B => N444, Y => N492); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[8]_net_1\); - - counter_points_snapshot_2_sqmuxa_2 : NOR2A - port map(A => start_snapshot_f0, B => sample_f0_val_0, Y - => \counter_points_snapshot_2_sqmuxa_2\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I61_Y : AO1D - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[15]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N504); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I178_Y : AO1B - port map(A => N574, B => N567, C => N566, Y => N630); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR2A - port map(A => N523, B => N519, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f0_wdata_9, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(73)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I59_Y : AO1D - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[14]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N502); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I283_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_3 : OA1A - port map(A => N603, B => N618, C => ADD_32x32_fast_I250_Y_2, - Y => ADD_32x32_fast_I250_Y_3); - - \data_out[92]\ : DFN1C0 - port map(D => \sample_f0_wdata[28]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f0_wdata_3, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => \sample_f0_wdata[43]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(107)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I83_Y : AO1D - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[26]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N526); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y_0 : OA1 - port map(A => ADD_32x32_fast_I263_un1_Y_0, B => N644, C => - N629, Y => ADD_32x32_fast_I263_Y_0); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_282, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : AX1B - port map(A => I240_un1_Y, B => N644, C => - ADD_32x32_fast_I290_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I220_un1_Y : - OR2B - port map(A => N634, B => N619, Y => I220_un1_Y); - - \counter_points_snapshot_RNIUGJE[10]\ : NOR3A - port map(A => un4_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un4_data_in_validlt30_18); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[29]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[29]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_3 : OA1A - port map(A => N605, B => N620, C => ADD_32x32_fast_I251_Y_2, - Y => ADD_32x32_fast_I251_Y_3); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I183_Y : NOR2A - port map(A => N579, B => N571, Y => N635); - - \data_out_RNO[94]\ : NOR2B - port map(A => sample_f0_49, B => data_shaping_R0_0, Y => - \sample_f0_wdata[30]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1C - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[25]\); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[20]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[9]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I302_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y_0 : - NOR2B - port map(A => N615, B => N631, Y => - ADD_32x32_fast_I256_un1_Y_0); - - \data_out_RNO[95]\ : NOR2B - port map(A => sample_f0_48, B => data_shaping_R0, Y => - \sample_f0_wdata[31]\); - - \counter_points_snapshot_RNIR7VB[0]\ : NOR3A - port map(A => \counter_points_snapshot_i_0[30]\, B => - \counter_points_snapshot[1]_net_1\, C => - \counter_points_snapshot[0]_net_1\, Y => - un4_data_in_validlt30_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I191_Y : NOR2B - port map(A => N587, B => N579, Y => N643); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_un1_Y : - OR2B - port map(A => N513, B => N510, Y => I126_un1_Y); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[17]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I194_Y : AO1 - port map(A => N590, B => N583, C => N582, Y => N646); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_un1_Y : - NOR2B - port map(A => N572, B => N565, Y => I176_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : AO1B - port map(A => \un1_counter_points_snapshot[29]\, B => - \un1_counter_points_snapshot[30]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N531); - - \counter_points_snapshot_RNIFTOE[18]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I28_G0N : OR2A - port map(A => \un1_data_out_valid_0_sqmuxa_1_2[31]\, B => - \un1_counter_points_snapshot[3]\, Y => N464); - - \counter_points_snapshot_RNIV3C8[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un4_data_in_validlt30_4); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : AO1B - port map(A => ADD_32x32_fast_I250_un1_Y_0, B => N771, C => - ADD_32x32_fast_I250_Y_3, Y => N738); - - \data_out_RNO[93]\ : NOR2B - port map(A => sample_f0_50, B => data_shaping_R0_0, Y => - \sample_f0_wdata[29]\); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f0_wdata_90, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(154)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - AOI1 - port map(A => N_8, B => N764, C => I110_un1_Y, Y => N760_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_un1_Y : - OR3C - port map(A => N619, B => N635, C => N650, Y => I258_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I11_P0N : OR2A - port map(A => \un1_counter_points_snapshot[20]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N414); - - \data_out[82]\ : DFN1C0 - port map(D => \sample_f0_wdata[18]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(82)); - - \counter_points_snapshot_RNIN3B8[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un4_data_in_validlt30_2); - - \counter_points_snapshot_RNID5PE[30]\ : NOR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot_i_0[30]\, Y => - \un1_counter_points_snapshot[1]\); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f0_wdata_53, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1B - port map(A => N760_i, B => ADD_32x32_fast_I300_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[20]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : AO1 - port map(A => N554, B => N547, C => N546, Y => - ADD_32x32_fast_I254_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I87_Y : AO1D - port map(A => \un1_counter_points_snapshot[29]\, B => - \un1_counter_points_snapshot[28]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N530); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I41_Y : AO1A - port map(A => \un1_counter_points_snapshot[6]\, B => - \counter_points_snapshot[26]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N484); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f0_wdata_12, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f0_wdata_88, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(152)); - - \counter_points_snapshot_RNIT70S1[10]\ : NOR3C - port map(A => un4_data_in_validlt30_18, B => - un4_data_in_validlt30_17, C => un4_data_in_validlt30_23, - Y => un4_data_in_validlt30_27); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f0_wdata_85, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(149)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I285_Y_0_0); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f0_wdata_63, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : AO1 - port map(A => N654, B => N639, C => N638, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : AO1 - port map(A => N652, B => N637, C => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2B - port map(A => N588, B => I198_un1_Y, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f0_wdata_73, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I141_Y : NOR2 - port map(A => N528, B => N524, Y => N587); - - \data_out_RNO[81]\ : NOR2B - port map(A => sample_f0_62, B => data_shaping_R0, Y => - \sample_f0_wdata[17]\); - - \counter_points_snapshot_RNIJJA8[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un4_data_in_validlt30_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : OAI1 - port map(A => N528, B => N531, C => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f0_wdata_91, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(155)); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNINO97[15]\ : NOR2 - port map(A => \counter_points_snapshot[15]_net_1\, B => - \counter_points_snapshot[16]_net_1\, Y => - un4_data_in_validlt30_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_a2_0_0 : - OR2 - port map(A => N_43, B => N486, Y => - ADD_32x32_fast_I253_Y_0_a2_0); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_281, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1C - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[17]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I177_Y : NOR2A - port map(A => N565, B => N573, Y => N629); - - data_out_valid_RNO_0 : OAI1 - port map(A => \data_out_valid_0_sqmuxa\, B => - data_out_valid_0_sqmuxa_1, C => enable_f0, Y => - un1_enable_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I121_Y : NOR2B - port map(A => N508, B => N504, Y => N567); - - \data_out[90]\ : DFN1C0 - port map(D => \sample_f0_wdata[26]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_0 : AO1B - port map(A => \un1_counter_points_snapshot[18]\, B => - \un1_counter_points_snapshot[19]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I126_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR2 - port map(A => N511, B => N507, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : AO1B - port map(A => ADD_32x32_fast_I251_un1_Y_0, B => N774, C => - ADD_32x32_fast_I251_Y_3, Y => N740); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_un1_Y_0 : - NOR2B - port map(A => N603, B => N619, Y => - ADD_32x32_fast_I250_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I111_Y : OR3C - port map(A => N444, B => N441, C => N_8, Y => N557); - - \counter_points_snapshot_RNO[14]\ : XA1B - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[14]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_G0N : OR2A - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[11]\, Y => I50_un1_Y_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : AO1A - port map(A => N516, B => N519, C => N515, Y => N578); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[29]\, C => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - \data_out_RNO[92]\ : NOR2B - port map(A => sample_f0_51, B => data_shaping_R0_0, Y => - \sample_f0_wdata[28]\); - - \data_out[99]\ : DFN1C0 - port map(D => \sample_f0_wdata[35]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(99)); - - \data_out_RNO[100]\ : MX2 - port map(A => sample_f0_11, B => sample_f0_43, S => - data_shaping_R0, Y => \sample_f0_wdata[36]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I76_Y : AOI1B - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_counter_points_snapshot[23]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N519); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I95_Y : NOR2 - port map(A => ADD_32x32_fast_I95_Y_0, B => N_43, Y => N541); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : OR3C - port map(A => I220_un1_Y, B => N618, C => I258_un1_Y, Y => - N754); - - \data_out[106]\ : DFN1C0 - port map(D => \sample_f0_wdata[42]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(106)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I70_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_counter_points_snapshot[21]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N513); - - \counter_points_snapshot_RNIA1PE[20]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[20]_net_1\, Y => - \un1_counter_points_snapshot[11]\); - - \counter_points_snapshot_RNO[21]\ : XA1B - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[21]\); - - \counter_points_snapshot_RNI9TOE[12]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_0 : AOI1B - port map(A => \un1_data_out_valid_0_sqmuxa_1_0[31]\, B => - \un1_counter_points_snapshot[1]\, C => I32_un1_Y, Y => - ADD_32x32_fast_I250_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y_0 : AOI1 - port map(A => N646, B => N631, C => N630, Y => - ADD_32x32_fast_I264_Y_0); - - \data_out_RNO[103]\ : MX2 - port map(A => sample_f0_8, B => sample_f0_40, S => - data_shaping_R0, Y => \sample_f0_wdata[39]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : AO1 - port map(A => N515, B => N512, C => N511, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => \sample_f0_wdata[34]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(98)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_un1_Y : - NOR3A - port map(A => N583, B => N528, C => N380, Y => I241_un1_Y); - - \counter_points_snapshot_RNIRO97[17]\ : NOR2 - port map(A => \counter_points_snapshot[17]_net_1\, B => - \counter_points_snapshot[18]_net_1\, Y => - un4_data_in_validlt30_8); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y : AO1B - port map(A => N505, B => N502, C => ADD_32x32_fast_I118_Y_0, - Y => N564); - - \data_out[80]\ : DFN1C0 - port map(D => \sample_f0_wdata[16]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f0_wdata_8, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : AO1B - port map(A => ADD_32x32_fast_I256_un1_Y_0, B => N789, C => - ADD_32x32_fast_I256_Y_1, Y => N750); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_G0N : OR2A - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[9]\, Y => N446_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AOI1B - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[14]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N499); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I135_Y : OR2B - port map(A => ADD_32x32_fast_I135_Y_0, B => N518, Y => N581); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[23]\, C => N648_i, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - \data_out_RNO[107]\ : MX2 - port map(A => sample_f0_4, B => sample_f0_36, S => - data_shaping_R0, Y => \sample_f0_wdata[43]\); - - \data_out[89]\ : DFN1C0 - port map(D => \sample_f0_wdata[25]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(89)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : OR2 - port map(A => N628, B => ADD_32x32_fast_I263_Y_0, Y => N764); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I289_Y_0_0, B => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out_RNO[101]\ : MX2 - port map(A => sample_f0_10, B => sample_f0_42, S => - data_shaping_R0, Y => \sample_f0_wdata[37]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f0_wdata_52, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(116)); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[19]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[2]\, B => - nb_snapshot_param(2), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_278); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : AO1 - port map(A => N594, B => N587, C => N586, Y => N650); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I285_Y_0_0, B => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNIQS97[27]\ : NOR2 - port map(A => \counter_points_snapshot[27]_net_1\, B => - \counter_points_snapshot[14]_net_1\, Y => - un4_data_in_validlt30_12); - - \counter_points_snapshot_RNO[18]\ : XA1C - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[18]\); - - \data_out[88]\ : DFN1C0 - port map(D => \sample_f0_wdata[24]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I10_P0N : OR2A - port map(A => \un1_counter_points_snapshot[21]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N411); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XOR2 - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[31]\, Y => - \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f0_wdata_62, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => \sample_f0_wdata[30]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f0_wdata_76, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f0_wdata_72, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(136)); - - \counter_points_snapshot_RNITNU94_3[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \counter_points_snapshot_RNITNU94_3[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I47_Y_i : OAI1 - port map(A => \counter_points_snapshot[23]_net_1\, B => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, C => N447, Y => - N_6); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[18]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I293_Y_0_0); - - \counter_points_snapshot_RNI8TOE[11]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[11]_net_1\, Y => - \un1_counter_points_snapshot[20]\); - - \counter_points_snapshot_RNIU1KE[23]\ : NOR3A - port map(A => un4_data_in_validlt30_14, B => - \counter_points_snapshot[26]_net_1\, C => - \counter_points_snapshot[23]_net_1\, Y => - un4_data_in_validlt30_22); - - \counter_points_snapshot_RNID0B8[31]\ : OR3A - port map(A => sample_f0_val_0, B => start_snapshot_f0, C - => \counter_points_snapshot[31]_net_1\, Y => - data_out_valid_0_sqmuxa_1_1); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[22]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[22]_net_1\); - - \data_out_RNO[86]\ : NOR2B - port map(A => sample_f0_57, B => data_shaping_R0_0, Y => - \sample_f0_wdata[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : OR2B - port map(A => N531, B => N380, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I304_Y_0_0); - - data_out_valid_RNO_1 : NOR2B - port map(A => enable_f0, B => burst_f0, Y => - counter_points_snapshot_0_sqmuxa_i); - - \data_out[101]\ : DFN1C0 - port map(D => \sample_f0_wdata[37]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(101)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I102_Y : AO1C - port map(A => N486, B => N489, C => N485, Y => N548); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I155_Y : NOR2B - port map(A => N551, B => N543, Y => N607); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f0_wdata_93, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_280, Y => - \counter_points_snapshot_10[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I163_Y : NOR2B - port map(A => N559, B => N551, Y => N615); - - \counter_points_snapshot_RNO[30]\ : XO1A - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[30]\); - - \counter_points_snapshot_RNI7DJG[8]\ : MX2C - port map(A => nb_snapshot_param(8), B => - \counter_points_snapshot[8]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[23]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I222_un1_Y : - OR2B - port map(A => N636, B => N621, Y => I222_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I127_Y : OR3C - port map(A => N510, B => N411, C => N414, Y => N573); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : - OA1A - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => - I110_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR2 - port map(A => N564, B => I176_un1_Y, Y => N628); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[23]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I134_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I117_Y : NOR2B - port map(A => N504, B => N500, Y => N563); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f0_wdata_6, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => nb_snapshot_param(5), B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_281); - - \data_out[84]\ : DFN1C0 - port map(D => \sample_f0_wdata[20]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => \sample_f0_wdata[39]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : AO1B - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[28]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N527); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I135_Y_0 : AO1D - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_counter_points_snapshot[25]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I135_Y_0); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[5]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I133_Y : NOR2 - port map(A => N520, B => N516, Y => N579); - - \counter_points_snapshot_RNITNU94_0[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \un1_data_out_valid_0_sqmuxa_1_1[31]\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[26]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I289_Y_0_0); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f0_wdata_15, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_2 : AOI1B - port map(A => N622, B => N607, C => ADD_32x32_fast_I252_Y_1, - Y => ADD_32x32_fast_I252_Y_2); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f0_wdata_80, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(144)); - - \data_out_RNO[89]\ : NOR2B - port map(A => sample_f0_54, B => data_shaping_R0_0, Y => - \sample_f0_wdata[25]\); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_284, Y => - \counter_points_snapshot_10[8]\); - - \data_out[111]\ : DFN1C0 - port map(D => \sample_f0_wdata[47]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I105_Y : NOR2B - port map(A => N492, B => N488, Y => N551); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2B - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[31]\, Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f0_wdata_78, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(142)); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f0_wdata_14, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1C - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[23]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I39_Y_i_o2 : - OA1C - port map(A => \counter_points_snapshot[26]_net_1\, B => - \un1_counter_points_snapshot[4]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N_43); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : AO1D - port map(A => N580, B => N573, C => N572, Y => N636); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[3]\, B => - nb_snapshot_param(3), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_279); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[26]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : OA1A - port map(A => N543, B => N550, C => ADD_32x32_fast_I252_Y_0, - Y => ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_un1_Y_0 : - NOR3A - port map(A => N533, B => N581, C => N589, Y => - ADD_32x32_fast_I263_un1_Y_0); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f0_wdata_57, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : AOI1B - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[16]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_276, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f0_wdata_67, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f0_wdata_49, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(113)); - - \counter_points_snapshot_RNIATOE[13]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[13]_net_1\, Y => - \un1_counter_points_snapshot[18]\); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f0_wdata_81, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(145)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_un1_Y_0 : - NOR3A - port map(A => N583, B => N528, C => N380, Y => - ADD_32x32_fast_I264_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I85_Y : OA1B - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[28]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N528); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[16]\, B => - \counter_points_snapshot[14]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I119_Y_0); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f0_wdata_2, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[1]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_1 : AO1D - port map(A => N626, B => N611, C => ADD_32x32_fast_I254_Y_0, - Y => ADD_32x32_fast_I254_Y_1); - - \counter_points_snapshot_RNO[31]\ : XA1C - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[31]\); - - \data_out_RNO[109]\ : MX2 - port map(A => sample_f0_2, B => sample_f0_34, S => - data_shaping_R0, Y => \sample_f0_wdata[45]\); - - \counter_points_snapshot_RNO_0[0]\ : MX2C - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_276); - - \counter_points_snapshot_RNO[15]\ : XA1C - port map(A => N771, B => ADD_32x32_fast_I295_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[15]\); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f0_wdata_59, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(123)); - - GND_i_0 : GND - port map(Y => GND_0); - - counter_points_snapshot_3_sqmuxa : OR2 - port map(A => start_snapshot_f0, B => burst_f0, Y => - \counter_points_snapshot_3_sqmuxa\); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f0_wdata_69, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : OR2A - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[10]\, Y => N443_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I153_Y : NOR2B - port map(A => N549, B => N541, Y => N605); - - \counter_points_snapshot_RNO[29]\ : XA1B - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[29]\); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[31]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[31]_net_1\); - - \counter_points_snapshot_RNIB1PE[21]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[21]_net_1\, Y => - \un1_counter_points_snapshot[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : AOI1B - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[3]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N479); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I55_Y_i : AO1A - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N_8); - - \data_out_RNO[97]\ : MX2 - port map(A => sample_f0_14, B => sample_f0_46, S => - data_shaping_R0_0, Y => \sample_f0_wdata[33]\); - - \counter_points_snapshot_RNITNU94_2[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \un1_data_out_valid_0_sqmuxa_1_3[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_1 : AOI1B - port map(A => N630, B => N615, C => ADD_32x32_fast_I256_Y_0, - Y => ADD_32x32_fast_I256_Y_1); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f0_wdata_10, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(74)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I169_Y : NOR2A - port map(A => N565, B => N557, Y => N621); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_286, Y => - \counter_points_snapshot_10[10]\); - - \data_out[108]\ : DFN1C0 - port map(D => \sample_f0_wdata[44]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => nb_snapshot_param(6), B => - \un1_data_out_valid_0_sqmuxa_2[6]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_282); - - \counter_points_snapshot_RNIJV7T[23]\ : NOR3C - port map(A => un4_data_in_validlt30_12, B => - un4_data_in_validlt30_11, C => un4_data_in_validlt30_22, - Y => un4_data_in_validlt30_26); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f0_wdata_92, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(156)); - - \data_out_RNO[106]\ : MX2 - port map(A => sample_f0_5, B => sample_f0_37, S => - data_shaping_R0, Y => \sample_f0_wdata[42]\); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[8]\, B => - nb_snapshot_param(8), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_284); - - \data_out_RNO[80]\ : NOR2B - port map(A => sample_f0_63, B => data_shaping_R0, Y => - \sample_f0_wdata[16]\); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_277, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : AOI1B - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[5]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - OA1C - port map(A => N756, B => N_6, C => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N756, B => ADD_32x32_fast_I302_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[22]\); - - \data_out_RNO[88]\ : NOR2B - port map(A => sample_f0_55, B => data_shaping_R0_0, Y => - \sample_f0_wdata[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_un1_Y : - NOR2 - port map(A => N528, B => N380, Y => I199_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I146_Y : AOI1 - port map(A => N533, B => N530, C => N529, Y => N592_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y : NOR2 - port map(A => N_6, B => N486, Y => N549); - - \counter_points_snapshot_RNIPGIG[1]\ : MX2C - port map(A => nb_snapshot_param(1), B => - \counter_points_snapshot[1]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[30]\); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[12]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot_RNITNU94_1[31]\ : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - data_out_valid_0_sqmuxa_1, Y => - \un1_data_out_valid_0_sqmuxa_1_2[31]\); - - \counter_points_snapshot_RNIGTOE[19]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[24]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[24]_net_1\); - - \data_out[95]\ : DFN1C0 - port map(D => \sample_f0_wdata[31]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(95)); - - \counter_points_snapshot_RNITOIG[3]\ : MX2C - port map(A => nb_snapshot_param(3), B => - \counter_points_snapshot[3]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1\, Y => - \un1_counter_points_snapshot[28]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_0 : NOR2 - port map(A => N483, B => N479, Y => ADD_32x32_fast_I252_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_un1_Y : - NOR3A - port map(A => N533, B => N581, C => N589, Y => I240_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I196_Y_0_o2 : - AO18 - port map(A => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, B => - \un1_counter_points_snapshot[24]\, C => N650, Y => N648_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : OR2B - port map(A => ADD_32x32_fast_I126_Y_0, B => I126_un1_Y, Y - => N572); - - \data_out_RNO[110]\ : MX2 - port map(A => sample_f0_1, B => sample_f0_33, S => - data_shaping_R0, Y => \sample_f0_wdata[46]\); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => \un1_data_out_valid_0_sqmuxa_2[9]\, B => - nb_snapshot_param(9), S => - \counter_points_snapshot_2_sqmuxa_2\, Y => N_285); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I116_Y : AO1 - port map(A => N503, B => N500, C => N499, Y => N562); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_279, Y => - \counter_points_snapshot_10[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[27]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f0_wdata_54, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(118)); - - \counter_points_snapshot_RNIQNNG[6]\ : NOR3A - port map(A => un4_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un4_data_in_validlt30_17); - - counter_points_snapshot_0_sqmuxa_1_0 : OR2A - port map(A => \data_out_valid_0_sqmuxa\, B => burst_f0, Y - => \counter_points_snapshot_0_sqmuxa_1_0\); - - \counter_points_snapshot_RNIE1PE[24]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - \counter_points_snapshot_RNICTOE[15]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - \un1_counter_points_snapshot[16]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR2 - port map(A => N646, B => I241_un1_Y, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I81_Y : OA1B - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_counter_points_snapshot[26]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N524); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : NOR3B - port map(A => N464, B => I32_un1_Y, C => N481, Y => - ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : AOI1 - port map(A => N643, B => N594, C => N642, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I175_Y : OR2A - port map(A => N563, B => N571, Y => N627); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XNOR3 - port map(A => \un1_data_out_valid_0_sqmuxa_1_1[31]\, B => - \un1_counter_points_snapshot[24]\, C => N650, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I286_Y_0_0, B => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - AO1C - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, C => N446_i, Y => - N489); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I100_Y : AO1 - port map(A => N487, B => N484, C => N483, Y => N546); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f0_wdata_64, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(128)); - - \counter_points_snapshot_RNO[11]\ : XA1B - port map(A => N783, B => ADD_32x32_fast_I291_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => \sample_f0_wdata[33]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f0_wdata_74, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(138)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I78_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_counter_points_snapshot[24]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N521); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I187_Y : NOR2B - port map(A => N583, B => N575, Y => N639); - - \data_out_RNO[84]\ : NOR2B - port map(A => sample_f0_59, B => data_shaping_R0_0, Y => - \sample_f0_wdata[20]\); - - \counter_points_snapshot_RNINELF[10]\ : MX2C - port map(A => nb_snapshot_param(10), B => - \counter_points_snapshot[10]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[21]\); - - \data_out[85]\ : DFN1C0 - port map(D => \sample_f0_wdata[21]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(85)); - - \counter_points_snapshot_RNIHO97[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un4_data_in_validlt30_6); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[3]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I159_Y : OR2B - port map(A => N555, B => N547, Y => N611); - - \counter_points_snapshot_RNIDTOE[16]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - \data_out_RNO[85]\ : NOR2B - port map(A => sample_f0_58, B => data_shaping_R0_0, Y => - \sample_f0_wdata[21]\); - - \data_out[109]\ : DFN1C0 - port map(D => \sample_f0_wdata[45]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(109)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_un1_Y : - OR2A - port map(A => N533, B => N589, Y => I198_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I68_Y : AOI1B - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_counter_points_snapshot[19]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N511); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I192_Y : OAI1 - port map(A => N581, B => N588, C => N580, Y => N644); - - \data_out_RNO[111]\ : MX2 - port map(A => sample_f0_0, B => sample_f0_32, S => - data_shaping_R0, Y => \sample_f0_wdata[47]\); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[23]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[21]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot_RNIDTJE[19]\ : NOR3A - port map(A => un4_data_in_validlt30_10, B => - \counter_points_snapshot[20]_net_1\, C => - \counter_points_snapshot[19]_net_1\, Y => - un4_data_in_validlt30_20); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[16]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[16]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I73_Y : OA1B - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[22]\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => N516); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : AOI1 - port map(A => N556, B => N549, C => N548, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f0_wdata_83, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(147)); - - \counter_points_snapshot_RNI11JG[5]\ : MX2C - port map(A => nb_snapshot_param(5), B => - \counter_points_snapshot[5]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[26]\); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f0_wdata_87, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(151)); - - \data_out_RNO[83]\ : NOR2B - port map(A => sample_f0_60, B => data_shaping_R0_0, Y => - \sample_f0_wdata[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I67_Y : AO1D - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[18]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N510); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I299_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => \sample_f0_wdata[23]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(87)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I43_Y : OA1B - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[7]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N486); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f0_wdata_89, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(153)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I283_Y_0_0, B => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I109_Y : NOR2B - port map(A => N496, B => N492, Y => N555); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR3C - port map(A => I222_un1_Y, B => N620, C => I259_un1_Y, Y => - N756); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_P0N : OR2A - port map(A => \un1_counter_points_snapshot[10]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N444); - - \counter_points_snapshot_RNI5VKS[0]\ : NOR3C - port map(A => un4_data_in_validlt30_2, B => - un4_data_in_validlt30_1, C => un4_data_in_validlt30_15, Y - => un4_data_in_validlt30_23); - - counter_points_snapshot_0_sqmuxa_1 : OR2A - port map(A => \data_out_valid_0_sqmuxa\, B => burst_f0, Y - => \counter_points_snapshot_0_sqmuxa_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AOI1B - port map(A => \un1_counter_points_snapshot[29]\, B => - \un1_counter_points_snapshot[28]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : AOI1 - port map(A => N529, B => N526, C => ADD_32x32_fast_I142_Y_0, - Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I307_Y_0_0); - - \data_out_RNO[91]\ : NOR2B - port map(A => sample_f0_52, B => data_shaping_R0_0, Y => - \sample_f0_wdata[27]\); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f0_wdata_55, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : AOI1B - port map(A => N479, B => N476, C => ADD_32x32_fast_I250_Y_0, - Y => ADD_32x32_fast_I250_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I53_Y : AO1A - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot[12]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N496); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_un1_Y : - NOR3C - port map(A => N623, B => N639, C => N654, Y => I260_un1_Y); - - \data_out_RNO[102]\ : MX2 - port map(A => sample_f0_9, B => sample_f0_41, S => - data_shaping_R0, Y => \sample_f0_wdata[38]\); - - \counter_points_snapshot_RNIF1PE[25]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : AOI1B - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[22]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N515); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => nb_snapshot_param(7), B => - \un1_data_out_valid_0_sqmuxa_2[7]\, S => - \counter_points_snapshot_2_sqmuxa\, Y => N_283); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_285, Y => - \counter_points_snapshot_10[9]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[20]\, B => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I291_Y_0_0); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f0_wdata_5, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f0_wdata_65, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I77_Y : OA1B - port map(A => \un1_counter_points_snapshot[23]\, B => - \un1_counter_points_snapshot[24]\, C => - \un1_data_out_valid_0_sqmuxa_1_3[31]\, Y => N520); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I112_Y : AO1 - port map(A => N499, B => N496, C => N495, Y => N558); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - AX1E - port map(A => \counter_points_snapshot[31]_net_1\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => - \un1_data_out_valid_0_sqmuxa_1_0[31]\, Y => - ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y_0 : - OR2 - port map(A => N611, B => N627, Y => - ADD_32x32_fast_I254_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : AOI1B - port map(A => N548, B => N541, C => ADD_32x32_fast_I251_Y_1, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f0_wdata_75, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[25]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[25]_net_1\); - - \counter_points_snapshot_RNIVSIG[4]\ : MX2C - port map(A => nb_snapshot_param(4), B => - \counter_points_snapshot[4]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[27]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I48_Y : OR2B - port map(A => N446_i, B => N443_i, Y => N491); - - \data_out_RNO[82]\ : NOR2B - port map(A => sample_f0_61, B => data_shaping_R0, Y => - \sample_f0_wdata[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : AOI1 - port map(A => N521, B => N518, C => ADD_32x32_fast_I134_Y_0, - Y => N580); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[20]\, B => N783, - C => \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y - => N780_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : AO1C - port map(A => \un1_counter_points_snapshot[30]\, B => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, C => N380, Y => - N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : AO1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[6]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N485); - - un1_counter_points_snapshot_0_sqmuxa_1 : AO1B - port map(A => \counter_points_snapshot_3_sqmuxa\, B => - \counter_points_snapshot_0_sqmuxa_1_0\, C => enable_f0, Y - => un1_counter_points_snapshot_0_sqmuxa_1_i); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f0_wdata_11, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(75)); - - \counter_points_snapshot_RNI59JG[7]\ : MX2C - port map(A => nb_snapshot_param(7), B => - \counter_points_snapshot[7]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[24]\); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f0_wdata_4, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(68)); - - \counter_points_snapshot_RNIR0A7[24]\ : NOR2 - port map(A => \counter_points_snapshot[24]_net_1\, B => - \counter_points_snapshot[25]_net_1\, Y => - un4_data_in_validlt30_11); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[14]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I52_Y : AO1B - port map(A => \un1_data_out_valid_0_sqmuxa_1_3[31]\, B => - \un1_counter_points_snapshot[12]\, C => I50_un1_Y_i, Y - => N495); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OA1C - port map(A => N564, B => N557, C => N556, Y => N620); - - \counter_points_snapshot_RNIFMFM3[10]\ : NOR3C - port map(A => un4_data_in_validlt30_26, B => - un4_data_in_validlt30_25, C => un4_data_in_validlt30_27, - Y => un4_data_in_validlto30_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : AO1B - port map(A => ADD_32x32_fast_I264_un1_Y_0, B => N631, C => - ADD_32x32_fast_I264_Y_0, Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768_i, B => ADD_32x32_fast_I296_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[16]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I57_Y : AO1D - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => - \un1_data_out_valid_0_sqmuxa_1_2[31]\, Y => N500); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I22_P0N : OR2A - port map(A => \un1_counter_points_snapshot[9]\, B => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N447); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : AO1A - port map(A => N566, B => N559, C => N558, Y => N622); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I125_Y : OR2B - port map(A => N512, B => N508, Y => N571); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I214_un1_Y : - OR3B - port map(A => N549, B => N628, C => N557, Y => I214_un1_Y); - - \counter_points_snapshot_RNIC1PE[22]\ : OR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1_0\, B => - \counter_points_snapshot[22]_net_1\, Y => - \un1_counter_points_snapshot[9]\); - - data_out_valid_RNO : MX2A - port map(A => un1_enable_2, B => sample_f0_val_0, S => - counter_points_snapshot_0_sqmuxa_i, Y => - data_out_valid_19); - - \data_out[100]\ : DFN1C0 - port map(D => \sample_f0_wdata[36]\, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : OR3C - port map(A => I262_un1_Y, B => N626, C => I228_un1_Y, Y => - N762); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : - AO1D - port map(A => N_43, B => N485, C => N481, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f0_wdata_13, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f0_wdata_82, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f0, B => burst_f0, C => N_278, Y => - \counter_points_snapshot_10[2]\); - - \counter_points_snapshot_RNI9HJG[9]\ : MX2C - port map(A => nb_snapshot_param(9), B => - \counter_points_snapshot[9]_net_1\, S => - \counter_points_snapshot_0_sqmuxa_1_0\, Y => - \un1_counter_points_snapshot[22]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : AO1 - port map(A => N582, B => N575, C => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1C - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - un1_counter_points_snapshot_0_sqmuxa_1_i, Y => - \counter_points_snapshot_10[13]\); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f0_wdata_94, CLK => lclk_c, CLR => - rstn, Q => data_f0_out(158)); - - \data_out_RNO[105]\ : MX2 - port map(A => sample_f0_6, B => sample_f0_38, S => - data_shaping_R0, Y => \sample_f0_wdata[41]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I95_Y_0 : AOI1 - port map(A => \counter_points_snapshot[29]_net_1\, B => - \counter_points_snapshot[28]_net_1\, C => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I95_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I62_Y_0 : OA1A - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[17]\, C => - \counter_points_snapshot_RNITNU94_3[31]_net_1\, Y => N505); - - \counter_points_snapshot_RNIBTOE[14]\ : NOR2B - port map(A => \counter_points_snapshot_0_sqmuxa_1\, B => - \counter_points_snapshot[14]_net_1\, Y => - \un1_counter_points_snapshot[17]\); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f0_wdata_0, CLK => lclk_c, CLR => rstn, - Q => data_f0_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[25]\, B => - \un1_data_out_valid_0_sqmuxa_1_1[31]\, Y => - ADD_32x32_fast_I286_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I151_Y : NOR2B - port map(A => N547, B => N539, Y => N603); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_snapshot_160_12_1 is - - port( sample_f2_wdata : in std_logic_vector(95 downto 0); - data_f2_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0); - rstn : in std_logic; - lclk_c : in std_logic; - data_f2_out_valid : out std_logic; - I_9_31 : in std_logic; - I_45_11 : in std_logic; - I_52_11 : in std_logic; - I_38_12 : in std_logic; - N_4 : in std_logic; - I_56_12 : in std_logic; - I_24_16 : in std_logic; - I_5_31 : in std_logic; - I_20_23 : in std_logic; - I_13_35 : in std_logic; - I_31_15 : in std_logic; - start_snapshot_f2 : in std_logic; - sample_f2_val : in std_logic; - enable_f2 : in std_logic; - burst_f2 : in std_logic - ); - -end lpp_waveform_snapshot_160_12_1; - -architecture DEF_ARCH of lpp_waveform_snapshot_160_12_1 is - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal counter_points_snapshot_0_sqmuxa_1_0, - \counter_points_snapshot_0_sqmuxa_1_0_a2_0\, N_47_2, - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, N_59, - N_47_1, N_47_0, ADD_32x32_fast_I311_Y_0_0, - \un1_counter_points_snapshot[0]\, - ADD_32x32_fast_I296_Y_0_0, - \un1_counter_points_snapshot[15]\, - ADD_32x32_fast_I250_Y_3, N618, N603, - ADD_32x32_fast_I250_Y_2, N539, N546, - ADD_32x32_fast_I250_Y_1, N479, N476, - ADD_32x32_fast_I250_Y_0, \un1_counter_points_snapshot[1]\, - \un1_counter_points_snapshot[2]\, - ADD_32x32_fast_I308_Y_0_0, - \un1_counter_points_snapshot[3]\, - ADD_32x32_fast_I310_Y_0_0, ADD_32x32_fast_I253_Y_0_0, - N481, N485, ADD_32x32_fast_I295_Y_0_0, - \un1_counter_points_snapshot[16]\, - ADD_32x32_fast_I250_un1_Y_0, N619, - ADD_32x32_fast_I307_Y_0_0, - \un1_counter_points_snapshot[4]\, ADD_32x32_fast_I251_Y_2, - N541, N548, ADD_32x32_fast_I251_Y_1, N478, - ADD_32x32_fast_I251_Y_0, ADD_32x32_fast_I303_Y_0_0, - \un1_counter_points_snapshot[8]\, - ADD_32x32_fast_I304_Y_0_0, - \un1_counter_points_snapshot[7]\, - ADD_32x32_fast_I253_Y_0_a2_0, N_43, N486, - ADD_32x32_fast_I306_Y_0_0, - \un1_counter_points_snapshot[5]\, - ADD_32x32_fast_I309_Y_0_0, ADD_32x32_fast_I305_Y_0_0, - \un1_counter_points_snapshot[6]\, - ADD_32x32_fast_I292_Y_0_0, - \un1_counter_points_snapshot[19]\, - ADD_32x32_fast_I299_Y_0_0, - \un1_counter_points_snapshot[12]\, - ADD_32x32_fast_I300_Y_0_0, - \un1_counter_points_snapshot[11]\, - ADD_32x32_fast_I254_Y_0, N554, N547, - ADD_32x32_fast_I302_Y_0_0, - \un1_counter_points_snapshot[9]\, - ADD_32x32_fast_I294_Y_0_0, - \un1_counter_points_snapshot[17]\, - ADD_32x32_fast_I251_un1_Y_0, N_8, ADD_32x32_fast_I111_Y_0, - N565, ADD_32x32_fast_I255_Y_0, N556, N549, - ADD_32x32_fast_I252_Y_1, N550, N543, - ADD_32x32_fast_I252_Y_0, N483, N480, - ADD_32x32_fast_I256_Y_0, N558, N551, - ADD_32x32_fast_I259_Y_0, N620, N636, - ADD_32x32_fast_I255_un1_Y_3, ADD_32x32_fast_I255_un1_Y_1, - ADD_32x32_fast_I255_un1_Y_0, - \un1_counter_points_snapshot[20]\, - \un1_counter_points_snapshot[21]\, - \un1_counter_points_snapshot[18]\, - ADD_32x32_fast_I301_Y_0_0, - \un1_counter_points_snapshot[10]\, - ADD_32x32_fast_I297_Y_0_0, - \un1_counter_points_snapshot[14]\, - ADD_32x32_fast_I298_Y_0_0, - \un1_counter_points_snapshot[13]\, - ADD_32x32_fast_I256_un1_Y_1, N512, N516, N567, - ADD_32x32_fast_I293_Y_0_0, ADD_32x32_fast_I252_un1_Y_0, - N496, N500, ADD_32x32_fast_I284_Y_0_0, - \un1_counter_points_snapshot[27]\, - ADD_32x32_fast_I262_un1_Y_0, ADD_32x32_fast_I133_Y_0, - ADD_32x32_fast_I262_un1_Y_2, ADD_32x32_fast_I264_Y_0, - N380, N582, N590, ADD_32x32_fast_I282_Y_0_0, - \un1_counter_points_snapshot[29]\, - ADD_32x32_fast_I103_Y_0, - \un1_counter_points_snapshot[24]\, - \un1_counter_points_snapshot[23]\, - ADD_32x32_fast_I142_Y_0, - \un1_counter_points_snapshot[26]\, - ADD_32x32_fast_I126_Y_1, N413, ADD_32x32_fast_I134_Y_1, - \un1_counter_points_snapshot[22]\, - ADD_32x32_fast_I134_Y_0, - \un1_counter_points_snapshot[25]\, - ADD_32x32_fast_I119_Y_1, ADD_32x32_fast_I119_Y_0, - ADD_32x32_fast_I118_Y_1, ADD_32x32_fast_I118_Y_0, - ADD_32x32_fast_I262_un1_Y_2_tz_0, - \un1_counter_points_snapshot[28]\, data_out_valid_9_i_0, - un1_data_in_validlt30_27, un1_data_in_validlt30_18, - un1_data_in_validlt30_17, un1_data_in_validlt30_23, - un1_data_in_validlt30_26, un1_data_in_validlt30_12, - un1_data_in_validlt30_11, un1_data_in_validlt30_22, - un1_data_in_validlt30_25, un1_data_in_validlt30_8, - un1_data_in_validlt30_7, un1_data_in_validlt30_20, - un1_data_in_validlt30_2, un1_data_in_validlt30_1, - un1_data_in_validlt30_15, un1_data_in_validlt30_14, - \counter_points_snapshot[28]_net_1\, - \counter_points_snapshot[27]_net_1\, - un1_data_in_validlt30_10, - \counter_points_snapshot[20]_net_1\, - \counter_points_snapshot[19]_net_1\, - un1_data_in_validlt30_6, - \counter_points_snapshot[11]_net_1\, - \counter_points_snapshot[10]_net_1\, - un1_data_in_validlt30_4, - \counter_points_snapshot[7]_net_1\, - \counter_points_snapshot[6]_net_1\, - \counter_points_snapshot[1]_net_1\, - \counter_points_snapshot[0]_net_1\, - \counter_points_snapshot[18]_net_1\, - \counter_points_snapshot[29]_net_1\, - \counter_points_snapshot[30]_net_1\, - \counter_points_snapshot[25]_net_1\, - \counter_points_snapshot[26]_net_1\, - \counter_points_snapshot[23]_net_1\, - \counter_points_snapshot[24]_net_1\, - \counter_points_snapshot[21]_net_1\, - \counter_points_snapshot[22]_net_1\, - \counter_points_snapshot[16]_net_1\, - \counter_points_snapshot[17]_net_1\, - \counter_points_snapshot[14]_net_1\, - \counter_points_snapshot[15]_net_1\, - \counter_points_snapshot[12]_net_1\, - \counter_points_snapshot[13]_net_1\, - \counter_points_snapshot[8]_net_1\, - \counter_points_snapshot[9]_net_1\, - \counter_points_snapshot[4]_net_1\, - \counter_points_snapshot[5]_net_1\, - \counter_points_snapshot[2]_net_1\, - \counter_points_snapshot[3]_net_1\, - \counter_points_snapshot_10_12_i_o2_0\, N572, N410, N416, - \un1_data_out_valid_0_sqmuxa_2[3]\, N594, - \un1_data_out_valid_0_sqmuxa_2[4]\, N529, N533, N764, - N644, N628, N588, N766, N566, N574, N_63, N652, - \un1_data_out_valid_0_sqmuxa_2[5]\, N654, - \un1_data_out_valid_0_sqmuxa_2[10]\, N786_i, N758, N638, - N622, N443, N440, N497, - \un1_data_out_valid_0_sqmuxa_2[11]\, N783, N580, - \un1_data_out_valid_0_sqmuxa_2[7]\, N650, - \un1_data_out_valid_0_sqmuxa_2[2]\, N738, N771, - I258_un1_Y, N635, N754, I220_un1_Y, I255_un1_Y_i, N613, - N748, I214_un1_Y, \un1_data_out_valid_0_sqmuxa_2[8]\, - N648_i, \un1_data_out_valid_0_sqmuxa_2[6]\, N740, - I206_un1_Y, I251_un1_Y, N605, N774, N750, I216_un1_Y, - I256_un1_Y, N615, N789, un1_data_in_validlto30_i, N_52, - N_60, N_49, counter_points_snapshot_0_sqmuxa_1, - I262_un1_Y, N627, N762_i, N626, I228_un1_Y, N_47, N742, - I208_un1_Y, I252_un1_Y_i, N607, N777, N744, N752, N746, - I212_un1_Y, I254_un1_Y, N611, - \un1_data_out_valid_0_sqmuxa_2[9]\, - \un1_data_out_valid_0_sqmuxa_2[1]\, - \un1_counter_points_snapshot[30]\, - ADD_32x32_fast_I262_un1_Y_2_tz, N508, N563, N555, N571, - N642, N586, I182_un1_Y, N507, N_11, - \counter_points_snapshot_RNO[18]_net_1\, - \counter_points_snapshot_10[3]\, N_20, - counter_points_snapshot_2_sqmuxa_i, N386, N527, N531, - N383, \counter_points_snapshot_10[4]\, N_21, - \counter_points_snapshot_RNO[17]_net_1\, N504, N499, N492, - N488, N491, N487, N456, N459, N489, N_22, - \counter_points_snapshot_10[5]\, N515, N570, N437, - \counter_points_snapshot_10[10]\, N_27, - \counter_points_snapshot_RNO[21]_net_1\, - \counter_points_snapshot_RNO[22]_net_1\, - \counter_points_snapshot_10[11]\, N_28, N503, N519, N523, - \counter_points_snapshot_10[7]\, N_24, N562, - \un1_counter_points_snapshot[31]\, N634, N760_i, N_23, - N_25, \counter_points_snapshot_10[6]\, - \counter_points_snapshot_10[8]\, - \counter_points_snapshot[31]_net_1\, - \counter_points_snapshot_RNO[20]_net_1\, - \counter_points_snapshot_RNO[23]_net_1\, N_31, N_35, N_45, - N_15, N768_i, N_13, N_43_0, N_33, - \counter_points_snapshot_RNO[19]_net_1\, N_41, N_7, - N780_i, N_39, N_37, N_9, N_26, - \counter_points_snapshot_10[9]\, N_18, - \counter_points_snapshot_10[1]\, - \un1_data_out_valid_0_sqmuxa_2[0]\, N_17, N_19, - \counter_points_snapshot_10[0]\, - \counter_points_snapshot_10[2]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_0 : - AO1C - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[18]\, C => N_47_0, Y => - ADD_32x32_fast_I255_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y : - OR3B - port map(A => N613, B => ADD_32x32_fast_I255_un1_Y_3, C => - N786_i, Y => I255_un1_Y_i); - - \counter_points_snapshot_RNI1G36[25]\ : NOR2 - port map(A => \counter_points_snapshot[25]_net_1\, B => - \counter_points_snapshot[26]_net_1\, Y => - un1_data_in_validlt30_12); - - \counter_points_snapshot_RNIBPKE[24]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[24]_net_1\, Y => - \un1_counter_points_snapshot[7]\); - - \counter_points_snapshot[13]\ : DFN1C0 - port map(D => N_9, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[13]_net_1\); - - \counter_points_snapshot[11]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[11]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[11]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0 : AX1D - port map(A => N529, B => N533, C => - ADD_32x32_fast_I284_Y_0_0, Y => - \un1_data_out_valid_0_sqmuxa_2[4]\); - - \counter_points_snapshot_RNIPF36[21]\ : NOR2 - port map(A => \counter_points_snapshot[21]_net_1\, B => - \counter_points_snapshot[22]_net_1\, Y => - un1_data_in_validlt30_10); - - \data_out[110]\ : DFN1C0 - port map(D => sample_f2_wdata(46), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(110)); - - \counter_points_snapshot_RNO_0[10]\ : MX2C - port map(A => I_56_12, B => - \un1_data_out_valid_0_sqmuxa_2[10]\, S => N_60, Y => N_27); - - \counter_points_snapshot_RNO[27]\ : XA1C - port map(A => N746, B => ADD_32x32_fast_I307_Y_0_0, C => - N_52, Y => N_37); - - \counter_points_snapshot[9]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[9]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[9]_net_1\); - - \counter_points_snapshot[28]\ : DFN1C0 - port map(D => N_39, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[28]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I216_un1_Y : OA1 - port map(A => N566, B => N574, C => N615, Y => I216_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y_0 : - NOR3C - port map(A => N496, B => N500, C => N567, Y => - ADD_32x32_fast_I252_un1_Y_0); - - \counter_points_snapshot_RNO[19]\ : XA1B - port map(A => N762_i, B => ADD_32x32_fast_I299_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[19]_net_1\); - - \counter_points_snapshot_RNITAJL[6]\ : MX2C - port map(A => I_31_15, B => - \counter_points_snapshot[6]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[25]\); - - \data_out[91]\ : DFN1C0 - port map(D => sample_f2_wdata(27), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(91)); - - \counter_points_snapshot_RNIS7BQ2_0[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_1); - - \counter_points_snapshot_RNICPKE[25]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[25]_net_1\, Y => - \un1_counter_points_snapshot[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_a2_0 : - OR2 - port map(A => N_43, B => N486, Y => - ADD_32x32_fast_I253_Y_0_a2_0); - - \counter_points_snapshot_RNI747C[27]\ : NOR3A - port map(A => un1_data_in_validlt30_14, B => - \counter_points_snapshot[28]_net_1\, C => - \counter_points_snapshot[27]_net_1\, Y => - un1_data_in_validlt30_22); - - \data_out[120]\ : DFN1C0 - port map(D => sample_f2_wdata(56), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(120)); - - \counter_points_snapshot_RNO[24]\ : XA1B - port map(A => N752, B => ADD_32x32_fast_I304_Y_0_0, C => - N_52, Y => N_31); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I93_Y : NOR2B - port map(A => N480, B => N476, Y => N539); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y : OR3C - port map(A => I212_un1_Y, B => ADD_32x32_fast_I254_Y_0, C - => I254_un1_Y, Y => N746); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I190_Y : OR2 - port map(A => N586, B => I182_un1_Y, Y => N642); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I101_Y : NOR3C - port map(A => N456, B => N459, C => N488, Y => N547); - - \data_out[130]\ : DFN1C0 - port map(D => sample_f2_wdata(66), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(130)); - - \data_out[104]\ : DFN1C0 - port map(D => sample_f2_wdata(40), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(104)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I104_Y : OR2 - port map(A => N491, B => N487, Y => N550); - - \counter_points_snapshot_RNO_0[4]\ : MX2C - port map(A => I_20_23, B => - \un1_data_out_valid_0_sqmuxa_2[4]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_21); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I111_Y_0 : AO1B - port map(A => \un1_counter_points_snapshot[11]\, B => - \un1_counter_points_snapshot[10]\, C => N_47_1, Y => - ADD_32x32_fast_I111_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I167_Y : NOR2B - port map(A => N563, B => N555, Y => N619); - - \counter_points_snapshot_RNIS7BQ2[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_0); - - \counter_points_snapshot_RNO_0[1]\ : MX2C - port map(A => I_5_31, B => - \un1_data_out_valid_0_sqmuxa_2[1]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_18); - - \data_out[102]\ : DFN1C0 - port map(D => sample_f2_wdata(38), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(102)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I64_Y : OA1C - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_counter_points_snapshot[18]\, C => N_47_2, Y => N507); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y : OR3C - port map(A => I208_un1_Y, B => ADD_32x32_fast_I252_Y_1, C - => I252_un1_Y_i, Y => N742); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[29]\, B => - N_47_1, Y => ADD_32x32_fast_I282_Y_0_0); - - \counter_points_snapshot_RNO[7]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_24, Y => - \counter_points_snapshot_10[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I309_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[2]\, B => N_47_0, - Y => ADD_32x32_fast_I309_Y_0_0); - - \counter_points_snapshot_RNO[12]\ : XA1B - port map(A => N780_i, B => ADD_32x32_fast_I292_Y_0_0, C => - N_52, Y => N_7); - - \counter_points_snapshot_RNI2K36[29]\ : NOR2 - port map(A => \counter_points_snapshot[29]_net_1\, B => - \counter_points_snapshot[30]_net_1\, Y => - un1_data_in_validlt30_14); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I235_Y : AO1 - port map(A => N650, B => N635, C => N634, Y => N771); - - \data_out[93]\ : DFN1C0 - port map(D => sample_f2_wdata(29), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(93)); - - \counter_points_snapshot[4]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[4]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[4]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_1 : - OAI1 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[20]\, C => N_47_0, Y => - ADD_32x32_fast_I255_un1_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I33_Y : OAI1 - port map(A => \un1_counter_points_snapshot[1]\, B => - \un1_counter_points_snapshot[2]\, C => N_47_2, Y => N476); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I301_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[10]\, B => - N_47_0, Y => ADD_32x32_fast_I301_Y_0_0); - - \data_out[159]\ : DFN1C0 - port map(D => sample_f2_wdata(95), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(159)); - - \data_out[105]\ : DFN1C0 - port map(D => sample_f2_wdata(41), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(105)); - - \counter_points_snapshot[15]\ : DFN1C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[15]_net_1\); - - \data_out[141]\ : DFN1C0 - port map(D => sample_f2_wdata(77), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(141)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_un1_Y_0 : - NOR3C - port map(A => N_8, B => ADD_32x32_fast_I111_Y_0, C => N565, - Y => ADD_32x32_fast_I251_un1_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I108_Y : OR3A - port map(A => N440, B => N437, C => N491, Y => N554); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I140_Y : OR2 - port map(A => N527, B => N523, Y => N586); - - \data_out[81]\ : DFN1C0 - port map(D => sample_f2_wdata(17), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(81)); - - counter_points_snapshot_10_12_i_o2 : OR2B - port map(A => \counter_points_snapshot_10_12_i_o2_0\, B => - N_60, Y => N_52); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I310_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[1]\, B => N_47_0, - Y => ADD_32x32_fast_I310_Y_0_0); - - \counter_points_snapshot[7]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[7]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[7]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y_0 : AO1 - port map(A => N558, B => N551, C => N550, Y => - ADD_32x32_fast_I256_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I234_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[16]\, B => N_47, - C => N771, Y => N768_i); - - \data_out[114]\ : DFN1C0 - port map(D => sample_f2_wdata(50), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(114)); - - \counter_points_snapshot[0]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[0]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[0]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I97_Y : NOR3C - port map(A => N456, B => N459, C => N480, Y => N543); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I182_Y : OR2 - port map(A => N570, B => I182_un1_Y, Y => N634); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I120_Y : OR2 - port map(A => N507, B => N503, Y => N566); - - \counter_points_snapshot_RNIVDS1[2]\ : NOR2 - port map(A => \counter_points_snapshot[2]_net_1\, B => - \counter_points_snapshot[3]_net_1\, Y => - un1_data_in_validlt30_1); - - \counter_points_snapshot[27]\ : DFN1C0 - port map(D => N_37, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[27]_net_1\); - - \data_out[143]\ : DFN1C0 - port map(D => sample_f2_wdata(79), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(143)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I199_Y : NOR2A - port map(A => N380, B => N590, Y => N654); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I110_Y : OR3C - port map(A => N443, B => N440, C => N497, Y => N556); - - \data_out[112]\ : DFN1C0 - port map(D => sample_f2_wdata(48), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(112)); - - \data_out[124]\ : DFN1C0 - port map(D => sample_f2_wdata(60), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(124)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I65_Y : AO1C - port map(A => \un1_counter_points_snapshot[17]\, B => - \un1_counter_points_snapshot[18]\, C => N_47_2, Y => N508); - - \data_out[134]\ : DFN1C0 - port map(D => sample_f2_wdata(70), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(134)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I80_Y : AOI1 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[25]\, C => N_47, Y => N523); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I11_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[20]\, B => N_47, - Y => N413); - - \counter_points_snapshot_RNO[28]\ : XA1B - port map(A => N744, B => ADD_32x32_fast_I308_Y_0_0, C => - N_52, Y => N_39); - - \data_out[83]\ : DFN1C0 - port map(D => sample_f2_wdata(19), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(83)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_2 : OA1A - port map(A => N539, B => N546, C => ADD_32x32_fast_I250_Y_1, - Y => ADD_32x32_fast_I250_Y_2); - - \data_out[122]\ : DFN1C0 - port map(D => sample_f2_wdata(58), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(122)); - - \data_out[115]\ : DFN1C0 - port map(D => sample_f2_wdata(51), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(115)); - - \counter_points_snapshot_RNIATKE[30]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[30]_net_1\, Y => - \un1_counter_points_snapshot[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I44_Y : OA1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[8]\, C => N_47_2, Y => N487); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I38_Y_0_o2 : - OA1C - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[5]\, C => N_47, Y => N481); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y : - NOR3 - port map(A => ADD_32x32_fast_I262_un1_Y_0, B => N594, C => - N627, Y => I262_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[17]\, C => N_47_1, Y => - ADD_32x32_fast_I118_Y_0); - - \data_out[132]\ : DFN1C0 - port map(D => sample_f2_wdata(68), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(132)); - - \counter_points_snapshot_RNI54EO[23]\ : NOR3C - port map(A => un1_data_in_validlt30_12, B => - un1_data_in_validlt30_11, C => un1_data_in_validlt30_22, - Y => un1_data_in_validlt30_26); - - \counter_points_snapshot[30]\ : DFN1C0 - port map(D => N_43_0, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[30]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I37_Y : AO1C - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[3]\, C => N_47, Y => N480); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I228_un1_Y : - NOR2A - port map(A => N642, B => N627, Y => I228_un1_Y); - - \counter_points_snapshot_RNI7LKE[13]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[13]_net_1\, Y => - \un1_counter_points_snapshot[18]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_un1_Y : - OR3C - port map(A => N605, B => ADD_32x32_fast_I251_un1_Y_0, C => - N774, Y => I251_un1_Y); - - \counter_points_snapshot_RNIBTKE[31]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[31]_net_1\, Y => - \un1_counter_points_snapshot[0]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I69_Y : OAI1 - port map(A => \un1_counter_points_snapshot[19]\, B => - \un1_counter_points_snapshot[20]\, C => N_47_2, Y => N512); - - \data_out[96]\ : DFN1C0 - port map(D => sample_f2_wdata(32), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(96)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y : OR3C - port map(A => I214_un1_Y, B => ADD_32x32_fast_I255_Y_0, C - => I255_un1_Y_i, Y => N748); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I294_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[17]\, B => - N_47_0, Y => ADD_32x32_fast_I294_Y_0_0); - - \data_out[125]\ : DFN1C0 - port map(D => sample_f2_wdata(61), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(125)); - - \counter_points_snapshot_RNIS7BQ2_2[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y_1 : - NOR3C - port map(A => N512, B => N516, C => N567, Y => - ADD_32x32_fast_I256_un1_Y_1); - - \data_out[135]\ : DFN1C0 - port map(D => sample_f2_wdata(71), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(135)); - - \counter_points_snapshot_RNIGPKE[29]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[29]_net_1\, Y => - \un1_counter_points_snapshot[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0 : OA1B - port map(A => N752, B => ADD_32x32_fast_I253_Y_0_a2_0, C - => ADD_32x32_fast_I253_Y_0_0, Y => N744); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y : NOR2 - port map(A => ADD_32x32_fast_I119_Y_1, B => - ADD_32x32_fast_I119_Y_0, Y => N565); - - data_out_valid : DFN1C0 - port map(D => N_49, CLK => lclk_c, CLR => rstn, Q => - data_f2_out_valid); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I174_Y : AO1 - port map(A => N570, B => N563, C => N562, Y => N626); - - \data_out[71]\ : DFN1C0 - port map(D => sample_f2_wdata(7), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(71)); - - \data_out[65]\ : DFN1C0 - port map(D => sample_f2_wdata(1), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(65)); - - \counter_points_snapshot[18]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[18]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[18]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I260_Y : OR3B - port map(A => N654, B => N638, C => N622, Y => N758); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I45_Y : AO1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[7]\, C => N_47_2, Y => N488); - - \data_out[86]\ : DFN1C0 - port map(D => sample_f2_wdata(22), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(86)); - - \counter_points_snapshot_RNITTM8[0]\ : NOR3C - port map(A => un1_data_in_validlt30_2, B => - un1_data_in_validlt30_1, C => un1_data_in_validlt30_15, Y - => un1_data_in_validlt30_23); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I166_Y : AO1 - port map(A => N562, B => N555, C => N554, Y => N618); - - \data_out[150]\ : DFN1C0 - port map(D => sample_f2_wdata(86), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(150)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I297_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[14]\, B => - N_47_0, Y => ADD_32x32_fast_I297_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I296_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[15]\, B => - N_47_0, Y => ADD_32x32_fast_I296_Y_0_0); - - \data_out[148]\ : DFN1C0 - port map(D => sample_f2_wdata(84), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(148)); - - GND_i : GND - port map(Y => \GND\); - - \counter_points_snapshot_RNI59K92[6]\ : NOR3C - port map(A => un1_data_in_validlt30_26, B => - un1_data_in_validlt30_25, C => un1_data_in_validlt30_27, - Y => un1_data_in_validlto30_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I49_Y : AO1B - port map(A => \un1_counter_points_snapshot[10]\, B => - \un1_counter_points_snapshot[9]\, C => N_47_2, Y => N492); - - \counter_points_snapshot_RNI3US1[4]\ : NOR2 - port map(A => \counter_points_snapshot[4]_net_1\, B => - \counter_points_snapshot[5]_net_1\, Y => - un1_data_in_validlt30_2); - - \counter_points_snapshot[8]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[8]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[8]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I61_Y : AO1C - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[15]\, C => N_47_2, Y => N504); - - \counter_points_snapshot_RNICB6O[8]\ : MX2 - port map(A => I_45_11, B => - \counter_points_snapshot[8]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[23]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I136_Y : OR2 - port map(A => N523, B => N519, Y => N582); - - \data_out[73]\ : DFN1C0 - port map(D => sample_f2_wdata(9), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(73)); - - \counter_points_snapshot_RNIRHT4[0]\ : NOR3 - port map(A => \counter_points_snapshot[1]_net_1\, B => - \counter_points_snapshot[0]_net_1\, C => - \counter_points_snapshot[18]_net_1\, Y => - un1_data_in_validlt30_15); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_3 : AOI1B - port map(A => N618, B => N603, C => ADD_32x32_fast_I250_Y_2, - Y => ADD_32x32_fast_I250_Y_3); - - \data_out[92]\ : DFN1C0 - port map(D => sample_f2_wdata(28), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(92)); - - \data_out[67]\ : DFN1C0 - port map(D => sample_f2_wdata(3), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(67)); - - \data_out[107]\ : DFN1C0 - port map(D => sample_f2_wdata(43), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(107)); - - \counter_points_snapshot_RNO[6]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_23, Y => - \counter_points_snapshot_10[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I290_Y_0 : XNOR3 - port map(A => \un1_counter_points_snapshot[21]\, B => - N_47_1, C => N786_i, Y => - \un1_data_out_valid_0_sqmuxa_2[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I220_un1_Y : - NOR2B - port map(A => N634, B => N619, Y => I220_un1_Y); - - \counter_points_snapshot[29]\ : DFN1C0 - port map(D => N_41, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[29]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I183_Y : NOR3C - port map(A => N516, B => ADD_32x32_fast_I133_Y_0, C => N571, - Y => N635); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I300_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[11]\, B => - N_47_0, Y => ADD_32x32_fast_I300_Y_0_0); - - \counter_points_snapshot_RNO[25]\ : XA1B - port map(A => N750, B => ADD_32x32_fast_I305_Y_0_0, C => - N_52, Y => N_33); - - \counter_points_snapshot[20]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[20]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I302_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[9]\, B => N_47_0, - Y => ADD_32x32_fast_I302_Y_0_0); - - \counter_points_snapshot_RNIALKE[16]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[16]_net_1\, Y => - \un1_counter_points_snapshot[15]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y_1 : OA1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[16]\, C => N_47_1, Y => - ADD_32x32_fast_I119_Y_1); - - \counter_points_snapshot[17]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[17]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[17]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I88_Y : OR2 - port map(A => N386, B => N383, Y => N531); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I292_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - N_47_0, Y => ADD_32x32_fast_I292_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y : AO1B - port map(A => ADD_32x32_fast_I250_un1_Y_0, B => N771, C => - ADD_32x32_fast_I250_Y_3, Y => N738); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I212_un1_Y : - OR2B - port map(A => N626, B => N611, Y => I212_un1_Y); - - \data_out[154]\ : DFN1C0 - port map(D => sample_f2_wdata(90), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(154)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I261_Y_0_o2 : - AOI1B - port map(A => N_8, B => N764, C => N497, Y => N760_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_un1_Y : - NOR3C - port map(A => N619, B => N635, C => N650, Y => I258_un1_Y); - - \data_out[82]\ : DFN1C0 - port map(D => sample_f2_wdata(18), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(82)); - - \data_out[117]\ : DFN1C0 - port map(D => sample_f2_wdata(53), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(117)); - - \counter_points_snapshot_RNO[20]\ : XA1B - port map(A => N760_i, B => ADD_32x32_fast_I300_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[20]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_Y_0 : AOI1B - port map(A => N554, B => N547, C => N546, Y => - ADD_32x32_fast_I254_Y_0); - - \data_out[76]\ : DFN1C0 - port map(D => sample_f2_wdata(12), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(76)); - - \data_out[152]\ : DFN1C0 - port map(D => sample_f2_wdata(88), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(152)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I133_Y_0 : AO1C - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_counter_points_snapshot[23]\, C => N_47_1, Y => - ADD_32x32_fast_I133_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I118_Y_1 : OA1C - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[15]\, C => N_47_1, Y => - ADD_32x32_fast_I118_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I254_un1_Y : - OR3B - port map(A => N611, B => N783, C => N627, Y => I254_un1_Y); - - \data_out[149]\ : DFN1C0 - port map(D => sample_f2_wdata(85), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(149)); - - \data_out[127]\ : DFN1C0 - port map(D => sample_f2_wdata(63), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(127)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I237_Y : OR2B - port map(A => N654, B => N638, Y => N777); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I236_Y : OR2 - port map(A => N652, B => N636, Y => N774); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I198_Y : OR2 - port map(A => N588, B => N533, Y => N652); - - \data_out[137]\ : DFN1C0 - port map(D => sample_f2_wdata(73), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(137)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I144_Y : OR2 - port map(A => N531, B => N527, Y => N590); - - \data_out[155]\ : DFN1C0 - port map(D => sample_f2_wdata(91), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(155)); - - VCC_i : VCC - port map(Y => \VCC\); - - \counter_points_snapshot_RNO[5]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_22, Y => - \counter_points_snapshot_10[5]\); - - \counter_points_snapshot_RNO[17]\ : XA1C - port map(A => N766, B => ADD_32x32_fast_I297_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[17]_net_1\); - - \counter_points_snapshot_RNI9Q3F[1]\ : MX2C - port map(A => I_5_31, B => - \counter_points_snapshot[1]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[30]\); - - data_out_valid_RNO_0 : NOR2B - port map(A => enable_f2, B => sample_f2_val, Y => - data_out_valid_9_i_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I121_Y : NOR2B - port map(A => N508, B => N504, Y => N567); - - \data_out[90]\ : DFN1C0 - port map(D => sample_f2_wdata(26), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(90)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I124_Y : OR3 - port map(A => N413, B => N416, C => N507, Y => N570); - - \counter_points_snapshot[2]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[2]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[2]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y : OR3C - port map(A => ADD_32x32_fast_I251_Y_2, B => I206_un1_Y, C - => I251_un1_Y, Y => N740); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_un1_Y_0 : - NOR2B - port map(A => N603, B => N619, Y => - ADD_32x32_fast_I250_un1_Y_0); - - \counter_points_snapshot_RNILRFP[9]\ : MX2 - port map(A => I_52_11, B => - \counter_points_snapshot[9]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[22]\); - - \counter_points_snapshot_RNO[14]\ : XA1C - port map(A => N774, B => ADD_32x32_fast_I294_Y_0_0, C => - N_52, Y => N_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I20_G0N : OR2A - port map(A => \un1_counter_points_snapshot[11]\, B => N_47, - Y => N440); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I132_Y : OR2 - port map(A => N519, B => N515, Y => I182_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I282_Y_0 : XNOR2 - port map(A => ADD_32x32_fast_I282_Y_0_0, B => N533, Y => - \un1_data_out_valid_0_sqmuxa_2[2]\); - - counter_points_snapshot_2_sqmuxa_0_a2 : OR3A - port map(A => enable_f2, B => burst_f2, C => N_60, Y => - counter_points_snapshot_2_sqmuxa_i); - - \data_out[99]\ : DFN1C0 - port map(D => sample_f2_wdata(35), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(99)); - - \counter_points_snapshot_RNILR6C[19]\ : NOR3A - port map(A => un1_data_in_validlt30_10, B => - \counter_points_snapshot[20]_net_1\, C => - \counter_points_snapshot[19]_net_1\, Y => - un1_data_in_validlt30_20); - - \counter_points_snapshot_RNI6LKE[12]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[12]_net_1\, Y => - \un1_counter_points_snapshot[19]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I76_Y : OA1C - port map(A => \un1_counter_points_snapshot[24]\, B => - \un1_counter_points_snapshot[23]\, C => N_47, Y => N519); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I95_Y : NOR2 - port map(A => N_43, B => N478, Y => N541); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I258_Y : NOR3 - port map(A => I220_un1_Y, B => N618, C => I258_un1_Y, Y => - N754); - - \data_out[106]\ : DFN1C0 - port map(D => sample_f2_wdata(42), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(106)); - - \counter_points_snapshot_RNO[21]\ : XA1C - port map(A => N758, B => ADD_32x32_fast_I301_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[21]_net_1\); - - \counter_points_snapshot_RNIL736[12]\ : NOR2 - port map(A => \counter_points_snapshot[12]_net_1\, B => - \counter_points_snapshot[13]_net_1\, Y => - un1_data_in_validlt30_6); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_0 : AO1 - port map(A => \un1_counter_points_snapshot[1]\, B => - \un1_counter_points_snapshot[2]\, C => N_47_0, Y => - ADD_32x32_fast_I250_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y_0 : NOR3A - port map(A => N380, B => N582, C => N590, Y => - ADD_32x32_fast_I264_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y_2_tz : - NOR3 - port map(A => \un1_counter_points_snapshot[27]\, B => - \un1_counter_points_snapshot[26]\, C => - ADD_32x32_fast_I262_un1_Y_2_tz_0, Y => - ADD_32x32_fast_I262_un1_Y_2_tz); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_un1_Y : - NOR3C - port map(A => N615, B => ADD_32x32_fast_I256_un1_Y_1, C => - N789, Y => I256_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I128_Y : OR3 - port map(A => N413, B => N416, C => N515, Y => N574); - - \data_out[98]\ : DFN1C0 - port map(D => sample_f2_wdata(34), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(98)); - - \data_out[80]\ : DFN1C0 - port map(D => sample_f2_wdata(16), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(80)); - - \data_out[72]\ : DFN1C0 - port map(D => sample_f2_wdata(8), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(72)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I256_Y : NOR3 - port map(A => I216_un1_Y, B => ADD_32x32_fast_I256_Y_0, C - => I256_un1_Y, Y => N750); - - \counter_points_snapshot_RNIT736[16]\ : NOR2 - port map(A => \counter_points_snapshot[16]_net_1\, B => - \counter_points_snapshot[17]_net_1\, Y => - un1_data_in_validlt30_8); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I35_Y : OA1A - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_counter_points_snapshot[2]\, C => N_47, Y => N478); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I56_Y : AOI1 - port map(A => \un1_counter_points_snapshot[14]\, B => - \un1_counter_points_snapshot[13]\, C => N_47_2, Y => N499); - - \counter_points_snapshot_RNIIA0J[4]\ : MX2C - port map(A => I_20_23, B => - \counter_points_snapshot[4]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[27]\); - - \counter_points_snapshot_RNI9LKE[15]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[15]_net_1\, Y => - \un1_counter_points_snapshot[16]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I288_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[23]\, C => N648_i, Y => - \un1_data_out_valid_0_sqmuxa_2[8]\); - - counter_points_snapshot_2_sqmuxa_0_a2_0 : OR2A - port map(A => start_snapshot_f2, B => sample_f2_val, Y => - N_60); - - \data_out[89]\ : DFN1C0 - port map(D => sample_f2_wdata(25), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(89)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I263_Y : OR3 - port map(A => N644, B => N628, C => N533, Y => N764); - - counter_points_snapshot_0_sqmuxa_1_0_a2 : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0_a2_0\, - B => burst_f2, Y => counter_points_snapshot_0_sqmuxa_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I289_Y_0 : XNOR3 - port map(A => \un1_counter_points_snapshot[22]\, B => - N_47_1, C => N789, Y => - \un1_data_out_valid_0_sqmuxa_2[9]\); - - \data_out[116]\ : DFN1C0 - port map(D => sample_f2_wdata(52), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(116)); - - \counter_points_snapshot_RNI9PKE[22]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[22]_net_1\, Y => - \un1_counter_points_snapshot[9]\); - - \counter_points_snapshot[19]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[19]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[19]_net_1\); - - \counter_points_snapshot_RNO_0[2]\ : MX2C - port map(A => I_9_31, B => - \un1_data_out_valid_0_sqmuxa_2[2]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_19); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I298_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[13]\, B => - N_47_0, Y => ADD_32x32_fast_I298_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I197_Y : OR2A - port map(A => N594, B => N586, Y => N650); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I285_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[26]\, C => N654, Y => - \un1_data_out_valid_0_sqmuxa_2[5]\); - - \counter_points_snapshot[10]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[10]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[10]_net_1\); - - \counter_points_snapshot_RNO[18]\ : XA1B - port map(A => N764, B => ADD_32x32_fast_I298_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[18]_net_1\); - - \data_out[88]\ : DFN1C0 - port map(D => sample_f2_wdata(24), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(88)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_S_0 : XNOR2 - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => \un1_data_out_valid_0_sqmuxa_2[0]\); - - \data_out[126]\ : DFN1C0 - port map(D => sample_f2_wdata(62), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(126)); - - \data_out[94]\ : DFN1C0 - port map(D => sample_f2_wdata(30), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(94)); - - \data_out[140]\ : DFN1C0 - port map(D => sample_f2_wdata(76), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(140)); - - \data_out[136]\ : DFN1C0 - port map(D => sample_f2_wdata(72), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(136)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I293_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[18]\, B => - N_47_1, Y => ADD_32x32_fast_I293_Y_0_0); - - \un1_data_out_valid_0_sqmuxa_1_i_0[31]\ : AOI1B - port map(A => start_snapshot_f2, B => burst_f2, C => - sample_f2_val, Y => - \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\); - - \counter_points_snapshot_RNIP736[14]\ : NOR2 - port map(A => \counter_points_snapshot[14]_net_1\, B => - \counter_points_snapshot[15]_net_1\, Y => - un1_data_in_validlt30_7); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I208_un1_Y : - OR2B - port map(A => N622, B => N607, Y => I208_un1_Y); - - \counter_points_snapshot_RNIDPKE[26]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[26]_net_1\, Y => - \un1_counter_points_snapshot[5]\); - - \counter_points_snapshot[22]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[22]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[22]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I147_Y : NOR2A - port map(A => N380, B => N531, Y => N594); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I304_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[7]\, B => N_47_0, - Y => ADD_32x32_fast_I304_Y_0_0); - - \data_out[101]\ : DFN1C0 - port map(D => sample_f2_wdata(37), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(101)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I102_Y : OA1C - port map(A => N489, B => N486, C => N485, Y => N548); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I155_Y : NOR2B - port map(A => N551, B => N543, Y => N607); - - \data_out[157]\ : DFN1C0 - port map(D => sample_f2_wdata(93), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(157)); - - \counter_points_snapshot_RNO[4]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_21, Y => - \counter_points_snapshot_10[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I163_Y : NOR3C - port map(A => N496, B => N500, C => N551, Y => N615); - - \counter_points_snapshot_RNO[30]\ : XA1C - port map(A => N740, B => ADD_32x32_fast_I310_Y_0_0, C => - N_52, Y => N_43_0); - - \counter_points_snapshot_RNIOVES[11]\ : MX2C - port map(A => N_4, B => \counter_points_snapshot[11]_net_1\, - S => counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[20]\); - - \counter_points_snapshot[6]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[6]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[6]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I54_Y_0_o2 : AO1 - port map(A => \un1_counter_points_snapshot[13]\, B => - \un1_counter_points_snapshot[12]\, C => N_47_2, Y => N497); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I176_Y : OR3A - port map(A => N572, B => ADD_32x32_fast_I118_Y_0, C => - ADD_32x32_fast_I118_Y_1, Y => N628); - - \counter_points_snapshot_RNIBBDO[14]\ : NOR3C - port map(A => un1_data_in_validlt30_8, B => - un1_data_in_validlt30_7, C => un1_data_in_validlt30_20, Y - => un1_data_in_validlt30_25); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[23]\, B => - \un1_counter_points_snapshot[25]\, C => N_47_1, Y => - ADD_32x32_fast_I134_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I117_Y : NOR2B - port map(A => N504, B => N500, Y => N563); - - \data_out[70]\ : DFN1C0 - port map(D => sample_f2_wdata(6), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(70)); - - \counter_points_snapshot_RNO_0[5]\ : MX2C - port map(A => I_24_16, B => - \un1_data_out_valid_0_sqmuxa_2[5]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_22); - - \data_out[84]\ : DFN1C0 - port map(D => sample_f2_wdata(20), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(84)); - - \data_out[103]\ : DFN1C0 - port map(D => sample_f2_wdata(39), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(103)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I84_Y : AOI1 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[27]\, C => N_47_2, Y => N527); - - \counter_points_snapshot[5]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[5]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[5]_net_1\); - - \counter_points_snapshot_RNO[26]\ : XA1C - port map(A => N748, B => ADD_32x32_fast_I306_Y_0_0, C => - N_52, Y => N_35); - - \data_out[79]\ : DFN1C0 - port map(D => sample_f2_wdata(15), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(79)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I281_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[30]\, C => N380, Y => - \un1_data_out_valid_0_sqmuxa_2[1]\); - - \data_out[144]\ : DFN1C0 - port map(D => sample_f2_wdata(80), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(144)); - - \counter_points_snapshot_RNINQ9K[5]\ : MX2C - port map(A => I_24_16, B => - \counter_points_snapshot[5]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[26]\); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0 : NOR2B - port map(A => start_snapshot_f2, B => sample_f2_val, Y => - \counter_points_snapshot_0_sqmuxa_1_0_a2_0\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I25_P0N : OR2A - port map(A => N_47_2, B => \un1_counter_points_snapshot[6]\, - Y => N456); - - \counter_points_snapshot_RNO[8]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_25, Y => - \counter_points_snapshot_10[8]\); - - \counter_points_snapshot_RNILPOO[6]\ : NOR3C - port map(A => un1_data_in_validlt30_18, B => - un1_data_in_validlt30_17, C => un1_data_in_validlt30_23, - Y => un1_data_in_validlt30_27); - - \data_out[111]\ : DFN1C0 - port map(D => sample_f2_wdata(47), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(111)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I105_Y : NOR2B - port map(A => N492, B => N488, Y => N551); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I295_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[16]\, B => - N_47_0, Y => ADD_32x32_fast_I295_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I0_CO1 : OR2A - port map(A => \un1_counter_points_snapshot[31]\, B => N_47, - Y => N380); - - \data_out[142]\ : DFN1C0 - port map(D => sample_f2_wdata(78), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(142)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I26_P0N : OR2A - port map(A => N_47, B => \un1_counter_points_snapshot[5]\, - Y => N459); - - \data_out[78]\ : DFN1C0 - port map(D => sample_f2_wdata(14), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(78)); - - \counter_points_snapshot_RNO[23]\ : XA1B - port map(A => N754, B => ADD_32x32_fast_I303_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[23]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I39_Y_i_o2 : - AO1B - port map(A => \un1_counter_points_snapshot[4]\, B => N_47, - C => N459, Y => N_43); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I184_Y : OR2A - port map(A => N572, B => N580, Y => N636); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y_1 : AO1A - port map(A => \un1_counter_points_snapshot[22]\, B => - \un1_counter_points_snapshot[24]\, C => N_47_1, Y => - ADD_32x32_fast_I134_Y_1); - - \counter_points_snapshot_RNO_0[3]\ : MX2C - port map(A => I_13_35, B => - \un1_data_out_valid_0_sqmuxa_2[3]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_20); - - \counter_points_snapshot[26]\ : DFN1C0 - port map(D => N_35, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[26]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I305_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[6]\, B => N_47_0, - Y => ADD_32x32_fast_I305_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_1 : AOI1B - port map(A => N550, B => N543, C => ADD_32x32_fast_I252_Y_0, - Y => ADD_32x32_fast_I252_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I206_un1_Y : - OR2B - port map(A => N620, B => N605, Y => I206_un1_Y); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I1_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[30]\, B => - N_47_2, Y => N383); - - \data_out[121]\ : DFN1C0 - port map(D => sample_f2_wdata(57), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(121)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I60_Y : OA1C - port map(A => \un1_counter_points_snapshot[16]\, B => - \un1_counter_points_snapshot[15]\, C => N_47, Y => N503); - - \counter_points_snapshot_RNO[0]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_17, Y => - \counter_points_snapshot_10[0]\); - - \data_out[131]\ : DFN1C0 - port map(D => sample_f2_wdata(67), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(131)); - - \data_out[113]\ : DFN1C0 - port map(D => sample_f2_wdata(49), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(113)); - - \data_out[145]\ : DFN1C0 - port map(D => sample_f2_wdata(81), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(145)); - - \counter_points_snapshot_RNI4RSM[7]\ : MX2C - port map(A => I_38_12, B => - \counter_points_snapshot[7]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[24]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I119_Y_0 : OA1A - port map(A => \un1_counter_points_snapshot[15]\, B => - \un1_counter_points_snapshot[17]\, C => N_47_1, Y => - ADD_32x32_fast_I119_Y_0); - - \data_out[66]\ : DFN1C0 - port map(D => sample_f2_wdata(2), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(66)); - - \counter_points_snapshot[1]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[1]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[1]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y_0 : AOI1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[9]\, C => N_47_1, Y => - ADD_32x32_fast_I103_Y_0); - - \counter_points_snapshot_RNO[31]\ : XA1B - port map(A => N738, B => ADD_32x32_fast_I311_Y_0_0, C => - N_52, Y => N_45); - - \counter_points_snapshot_RNO_0[0]\ : MX2B - port map(A => nb_snapshot_param(0), B => - \un1_data_out_valid_0_sqmuxa_2[0]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_17); - - \counter_points_snapshot_RNO[15]\ : XA1B - port map(A => N771, B => ADD_32x32_fast_I295_Y_0_0, C => - N_52, Y => N_13); - - \data_out[123]\ : DFN1C0 - port map(D => sample_f2_wdata(59), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(123)); - - \counter_points_snapshot_RNI6F6C[10]\ : NOR3A - port map(A => un1_data_in_validlt30_6, B => - \counter_points_snapshot[11]_net_1\, C => - \counter_points_snapshot[10]_net_1\, Y => - un1_data_in_validlt30_18); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_out[133]\ : DFN1C0 - port map(D => sample_f2_wdata(69), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(133)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I21_G0N : OR2A - port map(A => \un1_counter_points_snapshot[10]\, B => - N_47_2, Y => N443); - - \counter_points_snapshot_RNIAPKE[23]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[23]_net_1\, Y => - \un1_counter_points_snapshot[8]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I153_Y : NOR2B - port map(A => N549, B => N541, Y => N605); - - \counter_points_snapshot_RNO[29]\ : XA1C - port map(A => N742, B => ADD_32x32_fast_I309_Y_0_0, C => - N_52, Y => N_41); - - \counter_points_snapshot[31]\ : DFN1C0 - port map(D => N_45, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[31]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I36_Y : OA1C - port map(A => \un1_counter_points_snapshot[4]\, B => - \un1_counter_points_snapshot[3]\, C => N_47, Y => N479); - - \counter_points_snapshot_RNIEQMH[3]\ : MX2C - port map(A => I_13_35, B => - \counter_points_snapshot[3]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1_0, Y => - \un1_counter_points_snapshot[28]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I55_Y_i : AO1C - port map(A => \un1_counter_points_snapshot[12]\, B => - \counter_points_snapshot[18]_net_1\, C => N_47, Y => N_8); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I19_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - N_47_2, Y => N437); - - \data_out[74]\ : DFN1C0 - port map(D => sample_f2_wdata(10), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(74)); - - \counter_points_snapshot_RNI8LKE[14]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[14]_net_1\, Y => - \un1_counter_points_snapshot[17]\); - - \counter_points_snapshot_RNO[10]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_27, Y => - \counter_points_snapshot_10[10]\); - - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y_2_tz_0 : - OR2 - port map(A => \un1_counter_points_snapshot[28]\, B => - \un1_counter_points_snapshot[25]\, Y => - ADD_32x32_fast_I262_un1_Y_2_tz_0); - - \data_out[108]\ : DFN1C0 - port map(D => sample_f2_wdata(44), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(108)); - - \counter_points_snapshot_RNO_0[6]\ : MX2C - port map(A => I_31_15, B => - \un1_data_out_valid_0_sqmuxa_2[6]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_23); - - \data_out[156]\ : DFN1C0 - port map(D => sample_f2_wdata(92), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(156)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I240_Y : NOR2 - port map(A => N644, B => N533, Y => N786_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_un1_Y_3 : - NOR3C - port map(A => ADD_32x32_fast_I255_un1_Y_1, B => - ADD_32x32_fast_I255_un1_Y_0, C => N565, Y => - ADD_32x32_fast_I255_un1_Y_3); - - \counter_points_snapshot_RNO_0[8]\ : MX2C - port map(A => I_45_11, B => - \un1_data_out_valid_0_sqmuxa_2[8]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_25); - - \counter_points_snapshot_RNO[1]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_18, Y => - \counter_points_snapshot_10[1]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I303_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[8]\, B => N_47_0, - Y => ADD_32x32_fast_I303_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I40_Y : OA1B - port map(A => \un1_counter_points_snapshot[5]\, B => - \un1_counter_points_snapshot[6]\, C => N_47, Y => N483); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I257_Y_0_o2 : - NOR2 - port map(A => N_63, B => N489, Y => N752); - - \counter_points_snapshot_RNO[22]\ : XA1C - port map(A => N_63, B => ADD_32x32_fast_I302_Y_0_0, C => - N_52, Y => \counter_points_snapshot_RNO[22]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I103_Y : NOR2 - port map(A => ADD_32x32_fast_I103_Y_0, B => N486, Y => N549); - - \counter_points_snapshot[12]\ : DFN1C0 - port map(D => N_7, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[12]_net_1\); - - \counter_points_snapshot[24]\ : DFN1C0 - port map(D => N_31, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[24]_net_1\); - - \data_out[95]\ : DFN1C0 - port map(D => sample_f2_wdata(31), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(95)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_Y_0 : AOI1 - port map(A => N483, B => N480, C => N479, Y => - ADD_32x32_fast_I252_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I252_un1_Y : - OR3C - port map(A => N607, B => ADD_32x32_fast_I252_un1_Y_0, C => - N777, Y => I252_un1_Y_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I196_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[24]\, B => N_47, - C => N650, Y => N648_i); - - \counter_points_snapshot_RNIBUT1[8]\ : NOR2 - port map(A => \counter_points_snapshot[8]_net_1\, B => - \counter_points_snapshot[9]_net_1\, Y => - un1_data_in_validlt30_4); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y : NOR3 - port map(A => N410, B => N416, C => ADD_32x32_fast_I126_Y_1, - Y => N572); - - \counter_points_snapshot_RNO_0[9]\ : MX2C - port map(A => I_52_11, B => - \un1_data_out_valid_0_sqmuxa_2[9]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_26); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I126_Y_1 : AO1A - port map(A => N_47_1, B => - \un1_counter_points_snapshot[18]\, C => N413, Y => - ADD_32x32_fast_I126_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I116_Y : OR2 - port map(A => N503, B => N499, Y => N562); - - \counter_points_snapshot_RNO[3]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_20, Y => - \counter_points_snapshot_10[3]\); - - \counter_points_snapshot_RNI8AQD[0]\ : MX2A - port map(A => nb_snapshot_param(0), B => - \counter_points_snapshot[0]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[31]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y_0 : AOI1 - port map(A => \un1_counter_points_snapshot[26]\, B => - \un1_counter_points_snapshot[27]\, C => N_47_1, Y => - ADD_32x32_fast_I142_Y_0); - - \data_out[118]\ : DFN1C0 - port map(D => sample_f2_wdata(54), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(118)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I241_Y : OR3A - port map(A => N380, B => N582, C => N590, Y => N789); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I306_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[5]\, B => N_47_0, - Y => ADD_32x32_fast_I306_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_1 : OA1A - port map(A => N481, B => N478, C => ADD_32x32_fast_I251_Y_0, - Y => ADD_32x32_fast_I251_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I239_Y : OR2A - port map(A => N594, B => N642, Y => N783); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I175_Y : OR2B - port map(A => N571, B => N563, Y => N627); - - \counter_points_snapshot_RNIBLKE[17]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[17]_net_1\, Y => - \un1_counter_points_snapshot[14]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y_0 : - OR3B - port map(A => N516, B => ADD_32x32_fast_I133_Y_0, C => - ADD_32x32_fast_I262_un1_Y_2, Y => - ADD_32x32_fast_I262_un1_Y_0); - - \counter_points_snapshot_RNITF36[23]\ : NOR2 - port map(A => \counter_points_snapshot[23]_net_1\, B => - \counter_points_snapshot[24]_net_1\, Y => - un1_data_in_validlt30_11); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I287_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[24]\, C => N650, Y => - \un1_data_out_valid_0_sqmuxa_2[7]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I286_Y_0 : XOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[25]\, C => N652, Y => - \un1_data_out_valid_0_sqmuxa_2[6]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I46_Y_0_o2 : - OA1B - port map(A => \un1_counter_points_snapshot[8]\, B => - \un1_counter_points_snapshot[9]\, C => N_47_2, Y => N489); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I291_Y_0 : XOR3 - port map(A => \un1_counter_points_snapshot[20]\, B => - N_47_1, C => N783, Y => - \un1_data_out_valid_0_sqmuxa_2[11]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I100_Y : NOR2 - port map(A => N487, B => N483, Y => N546); - - \data_out[128]\ : DFN1C0 - port map(D => sample_f2_wdata(64), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(128)); - - \counter_points_snapshot_RNO[11]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_28, Y => - \counter_points_snapshot_10[11]\); - - \data_out[97]\ : DFN1C0 - port map(D => sample_f2_wdata(33), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(97)); - - \data_out[138]\ : DFN1C0 - port map(D => sample_f2_wdata(74), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(138)); - - \counter_points_snapshot_RNIFPKE[28]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[28]_net_1\, Y => - \un1_counter_points_snapshot[3]\); - - \data_out[85]\ : DFN1C0 - port map(D => sample_f2_wdata(21), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(85)); - - \counter_points_snapshot[3]\ : DFN1C0 - port map(D => \counter_points_snapshot_10[3]\, CLK => - lclk_c, CLR => rstn, Q => - \counter_points_snapshot[3]_net_1\); - - \counter_points_snapshot_RNI7PKE[20]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[20]_net_1\, Y => - \un1_counter_points_snapshot[11]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I159_Y : NOR2B - port map(A => N555, B => N547, Y => N611); - - \data_out[109]\ : DFN1C0 - port map(D => sample_f2_wdata(45), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(109)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y_0 : OR2 - port map(A => N620, B => N636, Y => ADD_32x32_fast_I259_Y_0); - - \counter_points_snapshot_RNIICR3[6]\ : NOR3A - port map(A => un1_data_in_validlt30_4, B => - \counter_points_snapshot[7]_net_1\, C => - \counter_points_snapshot[6]_net_1\, Y => - un1_data_in_validlt30_17); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I192_Y : OR2 - port map(A => N588, B => N580, Y => N644); - - \counter_points_snapshot[23]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[23]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[23]_net_1\); - - \counter_points_snapshot[21]\ : DFN1C0 - port map(D => \counter_points_snapshot_RNO[21]_net_1\, CLK - => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[21]_net_1\); - - \counter_points_snapshot[16]\ : DFN1C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[16]_net_1\); - - \counter_points_snapshot_RNIG6OE2[31]\ : AO1D - port map(A => un1_data_in_validlto30_i, B => - \counter_points_snapshot[31]_net_1\, C => - start_snapshot_f2, Y => N_59); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I73_Y : AO1C - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[22]\, C => N_47, Y => N516); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I255_Y_0 : AOI1B - port map(A => N556, B => N549, C => N548, Y => - ADD_32x32_fast_I255_Y_0); - - \data_out[147]\ : DFN1C0 - port map(D => sample_f2_wdata(83), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(147)); - - \counter_points_snapshot_RNIDLKE[19]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[19]_net_1\, Y => - \un1_counter_points_snapshot[12]\); - - \data_out[151]\ : DFN1C0 - port map(D => sample_f2_wdata(87), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(151)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_un1_Y_2 : - NOR2A - port map(A => N_47_2, B => ADD_32x32_fast_I262_un1_Y_2_tz, - Y => ADD_32x32_fast_I262_un1_Y_2); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I299_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[12]\, B => - N_47_0, Y => ADD_32x32_fast_I299_Y_0_0); - - \counter_points_snapshot_RNI8PKE[21]\ : NOR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[21]_net_1\, Y => - \un1_counter_points_snapshot[10]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I308_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[3]\, B => N_47_0, - Y => ADD_32x32_fast_I308_Y_0_0); - - \data_out[87]\ : DFN1C0 - port map(D => sample_f2_wdata(23), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(87)); - - counter_points_snapshot_10_12_i_o2_0 : NOR2A - port map(A => enable_f2, B => burst_f2, Y => - \counter_points_snapshot_10_12_i_o2_0\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I43_Y : AOI1B - port map(A => \un1_counter_points_snapshot[7]\, B => - \un1_counter_points_snapshot[6]\, C => N_47_2, Y => N486); - - \data_out[153]\ : DFN1C0 - port map(D => sample_f2_wdata(89), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(153)); - - \counter_points_snapshot_RNIBADG[2]\ : MX2 - port map(A => I_9_31, B => - \counter_points_snapshot[2]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[29]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I283_Y_0 : XNOR3 - port map(A => N_47_1, B => - \un1_counter_points_snapshot[28]\, C => N594, Y => - \un1_data_out_valid_0_sqmuxa_2[3]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I109_Y : NOR2B - port map(A => N496, B => N492, Y => N555); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I259_Y : OR2 - port map(A => ADD_32x32_fast_I259_Y_0, B => N652, Y => N_63); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I86_Y : AO1D - port map(A => \un1_counter_points_snapshot[28]\, B => - N_47_2, C => N386, Y => N529); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I142_Y : OR2 - port map(A => ADD_32x32_fast_I142_Y_0, B => N529, Y => N588); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I307_Y_0_0 : - XNOR2 - port map(A => \un1_counter_points_snapshot[4]\, B => N_47_0, - Y => ADD_32x32_fast_I307_Y_0_0); - - \data_out[119]\ : DFN1C0 - port map(D => sample_f2_wdata(55), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(119)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I250_Y_1 : AOI1B - port map(A => N479, B => N476, C => ADD_32x32_fast_I250_Y_0, - Y => ADD_32x32_fast_I250_Y_1); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I53_Y : AO1C - port map(A => \un1_counter_points_snapshot[12]\, B => - \un1_counter_points_snapshot[11]\, C => N_47, Y => N496); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I10_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[21]\, B => - N_47_2, Y => N410); - - \counter_points_snapshot_RNIEPKE[27]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1, B => - \counter_points_snapshot[27]_net_1\, Y => - \un1_counter_points_snapshot[4]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I72_Y : OA1C - port map(A => \un1_counter_points_snapshot[21]\, B => - \un1_counter_points_snapshot[22]\, C => N_47, Y => N515); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I161_Y : NOR3C - port map(A => N_8, B => ADD_32x32_fast_I111_Y_0, C => N549, - Y => N613); - - \counter_points_snapshot_RNO_0[7]\ : MX2C - port map(A => I_38_12, B => - \un1_data_out_valid_0_sqmuxa_2[7]\, S => - counter_points_snapshot_2_sqmuxa_i, Y => N_24); - - \counter_points_snapshot_RNO[9]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_26, Y => - \counter_points_snapshot_10[9]\); - - \data_out[69]\ : DFN1C0 - port map(D => sample_f2_wdata(5), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(69)); - - \data_out[129]\ : DFN1C0 - port map(D => sample_f2_wdata(65), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(129)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I112_Y : OR3A - port map(A => N440, B => N437, C => N499, Y => N558); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I311_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[0]\, B => N_47_0, - Y => ADD_32x32_fast_I311_Y_0_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_2 : OA1A - port map(A => N541, B => N548, C => ADD_32x32_fast_I251_Y_1, - Y => ADD_32x32_fast_I251_Y_2); - - \data_out[139]\ : DFN1C0 - port map(D => sample_f2_wdata(75), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(139)); - - \counter_points_snapshot[25]\ : DFN1C0 - port map(D => N_33, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[25]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I48_Y : AO1C - port map(A => N_47_2, B => \un1_counter_points_snapshot[9]\, - C => N443, Y => N491); - - counter_points_snapshot_0_sqmuxa_1_0_a2_0_0 : OR2A - port map(A => \counter_points_snapshot_0_sqmuxa_1_0_a2_0\, - B => burst_f2, Y => counter_points_snapshot_0_sqmuxa_1_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I134_Y : OR2B - port map(A => ADD_32x32_fast_I134_Y_1, B => - ADD_32x32_fast_I134_Y_0, Y => N580); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I238_Y_0_o2 : - AO13 - port map(A => \un1_counter_points_snapshot[20]\, B => N_47, - C => N783, Y => N780_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I90_Y : OR2A - port map(A => N380, B => N383, Y => N533); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I42_Y : OA1B - port map(A => \un1_counter_points_snapshot[6]\, B => - \un1_counter_points_snapshot[7]\, C => N_47_2, Y => N485); - - \counter_points_snapshot_RNICLKE[18]\ : OR2B - port map(A => counter_points_snapshot_0_sqmuxa_1_0, B => - \counter_points_snapshot[18]_net_1\, Y => - \un1_counter_points_snapshot[13]\); - - \data_out[75]\ : DFN1C0 - port map(D => sample_f2_wdata(11), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(75)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I284_Y_0_0 : - XOR2 - port map(A => \un1_counter_points_snapshot[27]\, B => - N_47_1, Y => ADD_32x32_fast_I284_Y_0_0); - - \data_out[68]\ : DFN1C0 - port map(D => sample_f2_wdata(4), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(68)); - - \counter_points_snapshot_RNO_0[11]\ : MX2C - port map(A => N_4, B => \un1_data_out_valid_0_sqmuxa_2[11]\, - S => counter_points_snapshot_2_sqmuxa_i, Y => N_28); - - \counter_points_snapshot[14]\ : DFN1C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, Q => - \counter_points_snapshot[14]_net_1\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I251_Y_0 : AO1A - port map(A => \un1_counter_points_snapshot[3]\, B => - \un1_counter_points_snapshot[2]\, C => N_47_0, Y => - ADD_32x32_fast_I251_Y_0); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I12_G0N : NOR2 - port map(A => \un1_counter_points_snapshot[19]\, B => - N_47_2, Y => N416); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I168_Y : OR3 - port map(A => ADD_32x32_fast_I118_Y_0, B => - ADD_32x32_fast_I118_Y_1, C => N556, Y => N620); - - \counter_points_snapshot_RNINVES[10]\ : MX2C - port map(A => I_56_12, B => - \counter_points_snapshot[10]_net_1\, S => - counter_points_snapshot_0_sqmuxa_1, Y => - \un1_counter_points_snapshot[21]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I264_Y : OR3A - port map(A => ADD_32x32_fast_I264_Y_0, B => N566, C => N574, - Y => N766); - - \counter_points_snapshot_RNO[16]\ : XA1B - port map(A => N768_i, B => ADD_32x32_fast_I296_Y_0_0, C => - N_52, Y => N_15); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I57_Y : AO1C - port map(A => \un1_counter_points_snapshot[14]\, B => - \counter_points_snapshot[18]_net_1\, C => N_47, Y => N500); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I170_Y : OR2 - port map(A => N566, B => N558, Y => N622); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I125_Y : NOR2B - port map(A => N512, B => N508, Y => N571); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I214_un1_Y : - OR2B - port map(A => N628, B => N613, Y => I214_un1_Y); - - data_out_valid_RNO : OA1 - port map(A => burst_f2, B => N_59, C => - data_out_valid_9_i_0, Y => N_49); - - \data_out[100]\ : DFN1C0 - port map(D => sample_f2_wdata(36), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(100)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I262_Y : NOR3 - port map(A => N626, B => I262_un1_Y, C => I228_un1_Y, Y => - N762_i); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I253_Y_0_0 : OR2 - port map(A => N481, B => N485, Y => - ADD_32x32_fast_I253_Y_0_0); - - \data_out[77]\ : DFN1C0 - port map(D => sample_f2_wdata(13), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(77)); - - \data_out[146]\ : DFN1C0 - port map(D => sample_f2_wdata(82), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(146)); - - \counter_points_snapshot_RNO[2]\ : NOR3A - port map(A => enable_f2, B => burst_f2, C => N_19, Y => - \counter_points_snapshot_10[2]\); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I186_Y : NOR2 - port map(A => N582, B => N574, Y => N638); - - \counter_points_snapshot_RNO[13]\ : XA1C - port map(A => N777, B => ADD_32x32_fast_I293_Y_0_0, C => - N_52, Y => N_9); - - \data_out[158]\ : DFN1C0 - port map(D => sample_f2_wdata(94), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(158)); - - \counter_points_snapshot_RNIS7BQ2_1[31]\ : OR2B - port map(A => \un1_data_out_valid_0_sqmuxa_1_i_0[31]_net_1\, - B => N_59, Y => N_47); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I2_G0N : NOR2A - port map(A => \un1_counter_points_snapshot[29]\, B => N_47, - Y => N386); - - \data_out[64]\ : DFN1C0 - port map(D => sample_f2_wdata(0), CLK => lclk_c, CLR => - rstn, Q => data_f2_out(64)); - - un1_data_out_valid_0_sqmuxa_2_ADD_32x32_fast_I151_Y : NOR2B - port map(A => N547, B => N539, Y => N603); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(2 to 2); - status_full : out std_logic_vector(2 to 2); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - addr_data_f2 : in std_logic_vector(31 downto 0); - update_and_sel_3 : in std_logic_vector(5 downto 4); - status_full_ack : in std_logic_vector(2 to 2); - addr_data_vector_30 : in std_logic; - addr_data_vector_31 : in std_logic; - addr_data_vector_5 : in std_logic; - addr_data_vector_8 : in std_logic; - addr_data_vector_7 : in std_logic; - addr_data_vector_6 : in std_logic; - addr_data_vector_3 : in std_logic; - addr_data_vector_14 : in std_logic; - addr_data_vector_11 : in std_logic; - addr_data_vector_10 : in std_logic; - addr_data_vector_9 : in std_logic; - addr_data_vector_21 : in std_logic; - addr_data_vector_19 : in std_logic; - addr_data_vector_18 : in std_logic; - addr_data_vector_17 : in std_logic; - addr_data_vector_29 : in std_logic; - addr_data_vector_26 : in std_logic; - addr_data_vector_25 : in std_logic; - addr_data_vector_24 : in std_logic; - addr_data_vector_1 : in std_logic; - addr_data_vector_68 : out std_logic; - addr_data_vector_66 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_91 : out std_logic; - addr_data_vector_15 : in std_logic; - addr_data_vector_12 : in std_logic; - addr_data_vector_20 : in std_logic; - addr_data_vector_16 : in std_logic; - addr_data_vector_28 : in std_logic; - addr_data_vector_23 : in std_logic; - addr_data_vector_0 : in std_logic; - addr_data_vector_86 : out std_logic; - N_1365 : out std_logic; - N_1366 : out std_logic; - N_1396 : out std_logic; - N_1399 : out std_logic; - N_1398 : out std_logic; - N_1397 : out std_logic; - N_1394 : out std_logic; - N_1391 : out std_logic; - N_1388 : out std_logic; - N_1387 : out std_logic; - N_1386 : out std_logic; - N_1384 : out std_logic; - N_1382 : out std_logic; - N_1381 : out std_logic; - N_1380 : out std_logic; - N_1378 : out std_logic; - N_1375 : out std_logic; - N_1374 : out std_logic; - N_1373 : out std_logic; - N_1350 : out std_logic; - N_1392 : out std_logic; - N_1389 : out std_logic; - N_1383 : out std_logic; - N_1379 : out std_logic; - N_1377 : out std_logic; - N_1372 : out std_logic; - N_1349 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, \un1_address[24]\, - \addr_data_vector[88]\, N_41, N_42, \un1_state_12_2[4]\, - state7, \state[3]_net_1\, m40_m6_0_a2_7, N_25_0, - \un1_state_12[4]\, \un1_state_12_3_0[4]\, - \update_r[0]_net_1\, \update_r[1]_net_1\, m40_m6_0_a2_6, - m40_m6_0_a2_5, \addr_data_vector[85]\, - \addr_data_vector[84]\, m40_m6_0_a2_4, - \addr_data_vector[81]\, \addr_data_vector[80]\, - m40_m6_0_a2_2, \addr_data_vector[79]\, - \addr_data_vector[87]\, \addr_data_vector[82]\, - \addr_data_vector[83]\, \state_ns_0[0]\, - \state_ns_a3_1_0[0]\, N_129, N_124, un1_state_5_i_0, - \state[4]_net_1\, \state_ns_i_0[3]\, \state[2]_net_1\, - \state[1]_net_1\, N_116, \state_ns[0]\, N_110, - address_0_sqmuxa_i_0, un3_update_r, \un1_address[6]\, - \addr_data_vector[70]\, N_5_0, \un1_address[20]\, N_32_0, - N_36_0, N_47, N_46, \addr_data_vector[93]\, - \un1_address[29]\, un1_state_9, \nb_send_5[0]\, - \nb_send_5[1]\, \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, N_127, N_113, \state_ns[2]\, - un1_state_11, \address_7[20]\, \address_7[29]\, - \addr_data_vector[64]\, \addr_data_vector[92]\, - \addr_data_vector[76]\, \address_7[28]\, - \un1_address[28]\, N_44, \addr_data_vector[91]\, - N_15_0_i_0, N_13_0, \addr_data_vector[71]\, - \addr_data_vector[72]\, N_16_0, N_17_0_i_0, - \addr_data_vector[73]\, N_18_0, N_19_0, - \addr_data_vector[74]\, N_20_0_i_0, - \addr_data_vector[75]\, N_22_0_i_0, N_23_0, - \addr_data_vector[78]\, N_26_0_i_0, N_28_0_i_0, N_29_0, - N_30_0_i_0, \un1_address[19]\, N_37_0, \un1_address[23]\, - \addr_data_vector[86]\, N_40_i_0, N_50_i_0, - \addr_data_vector[66]\, \addr_data_vector[67]\, N_51_i_0, - N_69, N_52_i_0, \addr_data_vector[68]\, - \addr_data_vector[69]\, N_1_i_0, N_54_0_i_0, N_55_0_i_0, - \addr_data_vector[77]\, N_56_0_i_0, \un1_address[18]\, - \un1_address[21]\, \un1_address[22]\, \un1_address[25]\, - \addr_data_vector[89]\, \un1_address[27]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[14]\, \address_7[15]\, - \state[0]_net_1\, \address_7[16]\, \address_7[17]\, - \address_7[18]\, \address_7[19]\, \address_7[21]\, - \address_7[22]\, \address_7[23]\, \address_7[25]\, - \address_7[27]\, \addr_data_vector[65]\, - \addr_data_vector[90]\, \addr_data_vector[95]\, - \addr_data_vector[94]\, \address_7[31]\, N_49_i_0, - \address_7[30]\, \un1_address[30]\, \address_7[26]\, - \un1_address[26]\, \address_7[24]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_68 <= \addr_data_vector[68]\; - addr_data_vector_66 <= \addr_data_vector[66]\; - addr_data_vector_77 <= \addr_data_vector[77]\; - addr_data_vector_91 <= \addr_data_vector[91]\; - addr_data_vector_86 <= \addr_data_vector[86]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[80]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[74]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[94]\); - - \address_RNIHBFB[8]\ : MX2C - port map(A => addr_data_vector_8, B => - \addr_data_vector[72]\, S => sel_data(1), Y => N_1399); - - \address_RNIHSH5[10]\ : MX2C - port map(A => addr_data_vector_10, B => - \addr_data_vector[74]\, S => sel_data_1(1), Y => N_1387); - - un1_address_m45 : NOR3B - port map(A => \addr_data_vector[91]\, B => - \addr_data_vector[92]\, C => N_44, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f2(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : AX1 - port map(A => N_42, B => \addr_data_vector[89]\, C => - \addr_data_vector[90]\, Y => \un1_address[26]\); - - un1_address_m31 : OR3B - port map(A => \addr_data_vector[81]\, B => - \addr_data_vector[82]\, C => N_29_0, Y => N_32_0); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[90]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[84]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3A - port map(A => \state[2]_net_1\, B => N_129, C => - status_full_ack(2), Y => N_127); - - \address_RNIL4I5[21]\ : MX2C - port map(A => addr_data_vector_21, B => - \addr_data_vector[85]\, S => sel_data_1(1), Y => N_1384); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1 - port map(A => N_69, B => \addr_data_vector[68]\, C => - \addr_data_vector[69]\, Y => N_52_i_0); - - \address_RNI35K5[19]\ : MX2C - port map(A => addr_data_vector_19, B => - \addr_data_vector[83]\, S => sel_data_1(1), Y => N_1382); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[76]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNI96K9[31]\ : MX2C - port map(A => addr_data_vector_31, B => - \addr_data_vector[95]\, S => sel_data(1), Y => N_1366); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f2(29), S - => \state_0[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XNOR2 - port map(A => N_19_0, B => \addr_data_vector[75]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[86]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f2(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[66]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \address_RNI1TJ5[18]\ : MX2C - port map(A => addr_data_vector_18, B => - \addr_data_vector[82]\, S => sel_data_1(1), Y => N_1381); - - \address_RNIL9D7[3]\ : MX2C - port map(A => addr_data_vector_3, B => - \addr_data_vector[67]\, S => sel_data_1(1), Y => N_1394); - - un1_address_m43 : OR3B - port map(A => \addr_data_vector[89]\, B => - \addr_data_vector[90]\, C => N_42, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f2(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f2(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_110, Q => status_full_err(2)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : OR2B - port map(A => N_18_0, B => \addr_data_vector[74]\, Y => - N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \address_RNIOKI5[15]\ : MX2C - port map(A => addr_data_vector_15, B => - \addr_data_vector[79]\, S => sel_data_0(1), Y => N_1392); - - \state_RNI7AQ3A_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - \address_RNIPSI5[14]\ : MX2C - port map(A => addr_data_vector_14, B => - \addr_data_vector[78]\, S => sel_data_1(1), Y => N_1391); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f2(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[69]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[79]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[77]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => lclk_c, PRE => rstn, Q - => \state[4]_net_1\); - - \address_RNICPC7[0]\ : MX2C - port map(A => addr_data_vector_0, B => - \addr_data_vector[64]\, S => sel_data_0(1), Y => N_1349); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[83]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[89]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[87]\); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[71]\, C => - \addr_data_vector[72]\, Y => N_15_0_i_0); - - un1_address_m29 : XNOR2 - port map(A => N_29_0, B => \addr_data_vector[81]\, Y => - N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \state_RNO_2[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => N_124); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[93]\); - - \update_r_RNI7DL5[0]\ : OR2A - port map(A => \update_r[1]_net_1\, B => \update_r[0]_net_1\, - Y => un3_update_r); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[82]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f2(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f2(16), S => - \state[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f2(0), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => \addr_data_vector[64]\); - - un1_address_m28 : OR3B - port map(A => \addr_data_vector[79]\, B => - \addr_data_vector[80]\, C => N_25_0, Y => N_29_0); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - \un1_state_12_3[4]\ : NAND2 - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, Y => \un1_state_12[4]\); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : NAND2 - port map(A => \addr_data_vector[88]\, B => N_41, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f2(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[68]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[92]\); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - un1_address_m17 : NOR2A - port map(A => \addr_data_vector[73]\, B => N_16_0, Y => - N_18_0); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OA1A - port map(A => \state_ns_a3_1_0[0]\, B => N_129, C => N_124, - Y => \state_ns_0[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR3 - port map(A => address_0_sqmuxa_i_0, B => - \addr_data_vector[70]\, C => N_5_0, Y => \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f2(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - un1_address_m24 : OR3B - port map(A => \addr_data_vector[77]\, B => - \addr_data_vector[78]\, C => N_23_0, Y => N_25_0); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[7]_net_1\); - - un1_address_m40_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[81]\, B => - \addr_data_vector[80]\, C => m40_m6_0_a2_2, Y => - m40_m6_0_a2_5); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f2(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address_RNIDBFB[6]\ : MX2C - port map(A => addr_data_vector_6, B => - \addr_data_vector[70]\, S => sel_data(1), Y => N_1397); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[78]\); - - \address_RNIFBFB[7]\ : MX2C - port map(A => addr_data_vector_7, B => - \addr_data_vector[71]\, S => sel_data(1), Y => N_1398); - - \state_RNO[1]\ : OA1B - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - un1_address_m40_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[79]\, B => - \addr_data_vector[87]\, C => \addr_data_vector[86]\, Y - => m40_m6_0_a2_4); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => lclk_c, CLR => rstn, - E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f2(14), S => - \state_0[0]_net_1\, Y => \address_7[14]\); - - \address_RNIJ4I5[11]\ : MX2C - port map(A => addr_data_vector_11, B => - \addr_data_vector[75]\, S => sel_data_1(1), Y => N_1388); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \state_RNI5FKD[1]\ : OA1 - port map(A => \state[1]_net_1\, B => \state[2]_net_1\, C - => status_full_ack(2), Y => N_118); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[88]\); - - un1_address_m27 : AX1 - port map(A => N_25_0, B => \addr_data_vector[79]\, C => - \addr_data_vector[80]\, Y => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[89]\, Y => - \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[73]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : AO1B - port map(A => \state[3]_net_1\, B => state7, C => - \state_ns_0[0]\, Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[72]\); - - un1_address_m40_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[82]\, B => - \addr_data_vector[83]\, Y => m40_m6_0_a2_2); - - un1_address_m50 : XNOR2 - port map(A => N_69, B => \addr_data_vector[68]\, Y => - N_51_i_0); - - un1_address_m39 : XNOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[66]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : OR2 - port map(A => update_and_sel_3(5), B => update_and_sel_3(4), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f2(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f2(28), S - => \state_0[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f2(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - \state_ns_a3[0]\ : NOR2B - port map(A => state7, B => \state[3]_net_1\, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1C - port map(A => \addr_data_vector[86]\, B => N_37_0, C => - \addr_data_vector[87]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa_i_0, C => - \addr_data_vector[70]\, Y => N_13_0); - - un1_address_m59 : XOR2 - port map(A => \addr_data_vector[88]\, B => N_41, Y => - \un1_address[24]\); - - \update_r[0]\ : DFN1C0 - port map(D => update_and_sel_3(4), CLK => lclk_c, CLR => - rstn, Q => \update_r[0]_net_1\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[85]\, B => - \addr_data_vector[84]\, C => m40_m6_0_a2_4, Y => - m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f2(17), S => - \state[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f2(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[71]\, B => - \addr_data_vector[72]\, C => N_13_0, Y => N_16_0); - - \address_RNIM4I5[23]\ : MX2C - port map(A => addr_data_vector_23, B => - \addr_data_vector[87]\, S => sel_data_0(1), Y => N_1372); - - un1_address_m58 : XOR2 - port map(A => N_37_0, B => \addr_data_vector[86]\, Y => - \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f2(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[67]\); - - \address_RNI55K5[29]\ : MX2C - port map(A => addr_data_vector_29, B => - \addr_data_vector[93]\, S => sel_data_1(1), Y => N_1378); - - \address_RNIRSI5[24]\ : MX2C - port map(A => addr_data_vector_24, B => - \addr_data_vector[88]\, S => sel_data_1(1), Y => N_1373); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XOR2 - port map(A => N_46, B => \addr_data_vector[93]\, Y => - \un1_address[29]\); - - un1_address_m34 : AX1 - port map(A => N_32_0, B => \addr_data_vector[83]\, C => - \addr_data_vector[84]\, Y => \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f2(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : AO1D - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, C - => status_full_ack(2), Y => \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : XNOR2 - port map(A => N_23_0, B => \addr_data_vector[77]\, Y => - N_55_0_i_0); - - un1_address_m22 : OR3B - port map(A => \addr_data_vector[75]\, B => - \addr_data_vector[76]\, C => N_19_0, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[71]\); - - \address_RNIBBFB[5]\ : MX2C - port map(A => addr_data_vector_5, B => - \addr_data_vector[69]\, S => sel_data(1), Y => N_1396); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - \address_RNIISH5[12]\ : MX2C - port map(A => addr_data_vector_12, B => - \addr_data_vector[76]\, S => sel_data_0(1), Y => N_1389); - - un1_address_m25 : XNOR2 - port map(A => N_25_0, B => \addr_data_vector[79]\, Y => - N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => lclk_c, CLR => rstn, Q => - \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_3(5), CLK => lclk_c, CLR => - rstn, Q => \update_r[1]_net_1\); - - un1_address_m40_m6_0_a2_7 : AND2 - port map(A => m40_m6_0_a2_6, B => m40_m6_0_a2_5, Y => - m40_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - un1_address_m57 : XNOR2 - port map(A => N_36_0, B => \addr_data_vector[85]\, Y => - \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - un1_address_m40_m6_0_a2 : NOR2A - port map(A => m40_m6_0_a2_7, B => N_25_0, Y => N_41); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f2(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[66]\, C => \addr_data_vector[67]\, Y - => N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[73]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f2(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f2(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[94]\, B => N_47, C => - \addr_data_vector[95]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[70]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - status_full_err_RNO : AO1A - port map(A => N_129, B => \state[2]_net_1\, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state_0[0]_net_1\); - - \address_RNIT4J5[25]\ : MX2C - port map(A => addr_data_vector_25, B => - \addr_data_vector[89]\, S => sel_data_1(1), Y => N_1374); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f2(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un1_address_m36 : NOR2A - port map(A => \addr_data_vector[85]\, B => N_36_0, Y => - N_37_0); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[75]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[95]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : AX1 - port map(A => N_29_0, B => \addr_data_vector[81]\, C => - \addr_data_vector[82]\, Y => \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f2(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - \address_RNIEPC7[1]\ : MX2C - port map(A => addr_data_vector_1, B => - \addr_data_vector[65]\, S => sel_data_0(1), Y => N_1350); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f2(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f2(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[85]\); - - \un1_state_12_3_RNO[4]\ : NOR2A - port map(A => \update_r[0]_net_1\, B => \update_r[1]_net_1\, - Y => \un1_state_12_3_0[4]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - \address_RNI0DJ5[28]\ : MX2C - port map(A => addr_data_vector_28, B => - \addr_data_vector[92]\, S => sel_data_0(1), Y => N_1377); - - un1_address_m62 : XNOR2 - port map(A => N_44, B => \addr_data_vector[91]\, Y => - \un1_address[27]\); - - un1_address_m32 : XNOR2 - port map(A => N_32_0, B => \addr_data_vector[83]\, Y => - \un1_address[19]\); - - un1_address_m12_e : OR3B - port map(A => \addr_data_vector[68]\, B => - \addr_data_vector[69]\, C => N_69, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => lclk_c, CLR => rstn, Q => - \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[81]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[94]\, Y => - \un1_address[30]\); - - \address_RNIGCH5[20]\ : MX2C - port map(A => addr_data_vector_20, B => - \addr_data_vector[84]\, S => sel_data_0(1), Y => N_1383); - - un1_address_m35 : OR3B - port map(A => \addr_data_vector[83]\, B => - \addr_data_vector[84]\, C => N_32_0, Y => N_36_0); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[71]\, Y => - N_1_i_0); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[91]\); - - \state_RNO[3]\ : NOR2B - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : AX1 - port map(A => N_19_0, B => \addr_data_vector[75]\, C => - \addr_data_vector[76]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : AX1 - port map(A => N_23_0, B => \addr_data_vector[77]\, C => - \addr_data_vector[78]\, Y => N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f2(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : OR3B - port map(A => \addr_data_vector[66]\, B => - \addr_data_vector[67]\, C => \un1_state_12[4]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f2(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - \address_RNI1AD7[9]\ : MX2C - port map(A => addr_data_vector_9, B => - \addr_data_vector[73]\, S => sel_data_1(1), Y => N_1386); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f2(1), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => \addr_data_vector[65]\); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_11, Q => status_full(2)); - - \state_RNI7AQ3A[3]\ : OR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa_i_0); - - un1_address_m63 : AX1 - port map(A => N_44, B => \addr_data_vector[91]\, C => - \addr_data_vector[92]\, Y => \un1_address[28]\); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f2(20), S - => \state_0[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR2B - port map(A => N_46, B => \addr_data_vector[93]\, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : XOR2 - port map(A => N_18_0, B => \addr_data_vector[74]\, Y => - N_54_0_i_0); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \address_RNI7UJ9[30]\ : MX2C - port map(A => addr_data_vector_30, B => - \addr_data_vector[94]\, S => sel_data(1), Y => N_1365); - - \state_RNO_1[4]\ : NOR3 - port map(A => \state[1]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => \state_ns_a3_1_0[0]\); - - \address_RNIQSI5[16]\ : MX2C - port map(A => addr_data_vector_16, B => - \addr_data_vector[80]\, S => sel_data_0(1), Y => N_1379); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f2(15), S => - \state[0]_net_1\, Y => \address_7[15]\); - - \address_RNIVCJ5[26]\ : MX2C - port map(A => addr_data_vector_26, B => - \addr_data_vector[90]\, S => sel_data_1(1), Y => N_1375); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - \address_RNIVKJ5[17]\ : MX2C - port map(A => addr_data_vector_17, B => - \addr_data_vector[81]\, S => sel_data_1(1), Y => N_1380); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(0 to 0); - status_full : out std_logic_vector(0 to 0); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - update_and_sel_7 : in std_logic_vector(1 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(0 to 0); - addr_data_vector_1 : out std_logic; - addr_data_vector_0 : out std_logic; - addr_data_vector_68 : in std_logic; - addr_data_vector_66 : in std_logic; - addr_data_vector_77 : in std_logic; - addr_data_vector_86 : in std_logic; - addr_data_vector_91 : in std_logic; - addr_data_vector_31 : out std_logic; - addr_data_vector_30 : out std_logic; - addr_data_vector_5 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_25 : out std_logic; - addr_data_vector_24 : out std_logic; - addr_data_vector_23 : out std_logic; - addr_data_vector_12 : out std_logic; - addr_data_vector_11 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_8 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_3 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_18 : out std_logic; - addr_data_vector_17 : out std_logic; - addr_data_vector_21 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_16 : out std_logic; - addr_data_vector_19 : out std_logic; - addr_data_vector_20 : out std_logic; - N_1395 : out std_logic; - N_1393 : out std_logic; - N_1390 : out std_logic; - N_1385 : out std_logic; - N_1376 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, m37_m6_0_a2_6, m37_m6_0_a2_4, - m37_m6_0_a2_5, m37_m6_0_a2_2, \addr_data_vector[22]\, - ADD_32x32_fast_I164_Y_0_0, address_0_sqmuxa_i_0, - \un1_state_12_3_0[4]\, \update_r[0]_net_1\, - \update_r[1]_net_1\, address_0_sqmuxa_0, \state[3]_net_1\, - un1_state_5_i_0, \state[4]_net_1\, \state_ns_i_0[3]\, - N_131, N_116, N_129, \state[1]_net_1\, \state_ns[0]\, - N_125, N_124, \un1_state_12_2[4]\, N_110, - \state[2]_net_1\, state7, \un1_address[6]\, N_5_0, - N_38_0_i, N_24_0, N_2, \addr_data_vector[2]\, N_4_0, - \addr_data_vector[4]\, N_15_0_i_0, N_13_0_i_0, N_16_0, - \addr_data_vector[7]\, \addr_data_vector[8]\, N_17_0_i_0, - N_19_0, \addr_data_vector[9]\, N_20_0_i_0, N_22_0_i_0, - \addr_data_vector[11]\, N_23_0, \addr_data_vector[12]\, - \addr_data_vector[13]\, N_25_0, \addr_data_vector[14]\, - N_26_0_i_0, \addr_data_vector[15]\, N_28_0_i_0, - \addr_data_vector[16]\, N_29_0, N_30_0_i_0, - \addr_data_vector[17]\, N_32_0, \addr_data_vector[18]\, - \un1_address[19]\, \addr_data_vector[19]\, - \un1_address[20]\, \addr_data_vector[20]\, N_36_0, - \un1_address[23]\, N_40_i_0, N_42, \addr_data_vector[23]\, - N_44, N_45, \addr_data_vector[27]\, N_47, N_50_i_0, - \addr_data_vector[3]\, N_51_i_0, N_52_i_0, N_1_i_0, - N_54_0_i_0, \addr_data_vector[10]\, N_55_0_i_0, - N_56_0_i_0, \un1_address[18]\, \un1_address[21]\, - \addr_data_vector[21]\, \un1_address[22]\, - \un1_address[24]\, \addr_data_vector[24]\, - \un1_address[25]\, \addr_data_vector[25]\, - \un1_address[26]\, \addr_data_vector[26]\, - \un1_address[27]\, \un1_address[28]\, - \addr_data_vector[28]\, \un1_address[29]\, - \addr_data_vector[29]\, \addr_data_vector[5]\, - nb_send_1_sqmuxa, un1_state_9, \nb_send_5[0]\, - \nb_send_5[1]\, \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[4]\, - \un2_nb_send_next[4]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, N_127, N_113, \state_ns[2]\, - un1_state_11, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[14]\, \address_7[15]\, - \address_7[16]\, \address_7[17]\, \address_7[18]\, - \state[0]_net_1\, \address_7[19]\, \address_7[20]\, - \address_7[21]\, \address_7[22]\, \address_7[23]\, - \address_7[24]\, \address_7[25]\, \address_7[26]\, - \address_7[27]\, \address_7[28]\, \address_7[29]\, - \address_7[31]\, N_49_i_0, \address_7[30]\, - \un1_address[30]\, \addr_data_vector[30]\, - \addr_data_vector[6]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, - \addr_data_vector[31]\, N_4, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[3]\, N_12, N_17, N_22, \DWACT_FINC_E[1]\, - N_27, N_35, \DWACT_COMP0_E[1]\, \DWACT_COMP0_E[2]\, - \DWACT_COMP0_E[0]\, \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_31 <= \addr_data_vector[31]\; - addr_data_vector_30 <= \addr_data_vector[30]\; - addr_data_vector_5 <= \addr_data_vector[5]\; - addr_data_vector_29 <= \addr_data_vector[29]\; - addr_data_vector_28 <= \addr_data_vector[28]\; - addr_data_vector_26 <= \addr_data_vector[26]\; - addr_data_vector_25 <= \addr_data_vector[25]\; - addr_data_vector_24 <= \addr_data_vector[24]\; - addr_data_vector_23 <= \addr_data_vector[23]\; - addr_data_vector_12 <= \addr_data_vector[12]\; - addr_data_vector_11 <= \addr_data_vector[11]\; - addr_data_vector_10 <= \addr_data_vector[10]\; - addr_data_vector_9 <= \addr_data_vector[9]\; - addr_data_vector_8 <= \addr_data_vector[8]\; - addr_data_vector_7 <= \addr_data_vector[7]\; - addr_data_vector_3 <= \addr_data_vector[3]\; - addr_data_vector_6 <= \addr_data_vector[6]\; - addr_data_vector_18 <= \addr_data_vector[18]\; - addr_data_vector_17 <= \addr_data_vector[17]\; - addr_data_vector_21 <= \addr_data_vector[21]\; - addr_data_vector_14 <= \addr_data_vector[14]\; - addr_data_vector_15 <= \addr_data_vector[15]\; - addr_data_vector_16 <= \addr_data_vector[16]\; - addr_data_vector_19 <= \addr_data_vector[19]\; - addr_data_vector_20 <= \addr_data_vector[20]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[16]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[10]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[30]\); - - \update_r_RNIATLE[0]\ : OR3B - port map(A => \update_r[1]_net_1\, B => \state[3]_net_1\, C - => \update_r[0]_net_1\, Y => address_0_sqmuxa_0); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f0(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : AX1 - port map(A => N_42, B => \addr_data_vector[25]\, C => - \addr_data_vector[26]\, Y => \un1_address[26]\); - - un1_address_m37_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[14]\, B => - \addr_data_vector[22]\, C => \addr_data_vector[21]\, Y - => m37_m6_0_a2_4); - - un1_address_m31 : NOR3C - port map(A => \addr_data_vector[17]\, B => N_29_0, C => - \addr_data_vector[18]\, Y => N_32_0); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[26]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[20]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3A - port map(A => \state[2]_net_1\, B => N_129, C => - status_full_ack(0), Y => N_127); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : XOR2 - port map(A => N_4_0, B => \addr_data_vector[5]\, Y => - N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[12]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f0(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : XOR2 - port map(A => N_19_0, B => \addr_data_vector[11]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[22]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f0(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[2]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \state_RNIN0L5[1]\ : NOR2A - port map(A => status_full_ack(0), B => N_131, Y => N_118); - - un1_address_m43 : OR3B - port map(A => \addr_data_vector[25]\, B => - \addr_data_vector[26]\, C => N_42, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f0(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f0(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_110, Q => status_full_err(0)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : NOR3C - port map(A => \addr_data_vector[9]\, B => N_16_0, C => - \addr_data_vector[10]\, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - un1_address_ADD_32x32_fast_I164_Y_0_0 : XOR2 - port map(A => \addr_data_vector[6]\, B => - address_0_sqmuxa_i_0, Y => ADD_32x32_fast_I164_Y_0_0); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f0(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[5]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[15]\); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[13]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => lclk_c, PRE => rstn, Q - => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[19]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[25]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[23]\); - - un1_address_m14 : AX1C - port map(A => \addr_data_vector[7]\, B => N_13_0_i_0, C => - \addr_data_vector[8]\, Y => N_15_0_i_0); - - un1_address_m29 : XOR2 - port map(A => N_29_0, B => \addr_data_vector[17]\, Y => - N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[29]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[18]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f0(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f0(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - \address_RNINKI5[13]\ : MX2C - port map(A => \addr_data_vector[13]\, B => - addr_data_vector_77, S => sel_data_1(1), Y => N_1390); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f0(0), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => addr_data_vector_0); - - un1_address_m28 : NOR3C - port map(A => \addr_data_vector[15]\, B => N_25_0, C => - \addr_data_vector[16]\, Y => N_29_0); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - \update_r_RNI691J01[0]\ : OA1A - port map(A => \update_r[1]_net_1\, B => \update_r[0]_net_1\, - C => state7, Y => nb_send_1_sqmuxa); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : OR3B - port map(A => \addr_data_vector[23]\, B => - \addr_data_vector[24]\, C => N_38_0_i, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f0(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[4]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[28]\); - - un1_address_m1 : NOR3C - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, C => \addr_data_vector[2]\, Y => - N_2); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3A - port map(A => N_131, B => \state[3]_net_1\, C => N_129, Y - => N_125); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR2 - port map(A => ADD_32x32_fast_I164_Y_0_0, B => N_5_0, Y => - \un1_address[6]\); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f0(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - un1_address_m24 : NOR2A - port map(A => \addr_data_vector[14]\, B => N_24_0, Y => - N_25_0); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f0(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[14]\); - - \state_RNO[1]\ : OA1B - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => lclk_c, CLR => rstn, - E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f0(14), S => - \state_0[0]_net_1\, Y => \address_7[14]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[24]\); - - un1_address_m27 : AX1C - port map(A => \addr_data_vector[15]\, B => N_25_0, C => - \addr_data_vector[16]\, Y => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \address_RNI9BFB[4]\ : MX2C - port map(A => \addr_data_vector[4]\, B => - addr_data_vector_68, S => sel_data(1), Y => N_1395); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[25]\, Y => - \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XOR2 - port map(A => N_16_0, B => \addr_data_vector[9]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \state_RNIAI1701[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3B - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[8]\); - - un1_address_m50 : AX1C - port map(A => \addr_data_vector[3]\, B => N_2, C => - \addr_data_vector[4]\, Y => N_51_i_0); - - un1_address_m39 : AX1C - port map(A => \un1_state_12_2[4]\, B => - \un1_state_12_3_0[4]\, C => \addr_data_vector[2]\, Y => - N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : OR2 - port map(A => update_and_sel_7(1), B => update_and_sel_7(0), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f0(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f0(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f0(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : XNOR2 - port map(A => N_38_0_i, B => \addr_data_vector[23]\, Y => - \un1_address[23]\); - - un1_address_m12 : AO18 - port map(A => N_5_0, B => \addr_data_vector[6]\, C => - address_0_sqmuxa_i_0, Y => N_13_0_i_0); - - un1_address_m59 : AX1 - port map(A => N_38_0_i, B => \addr_data_vector[23]\, C => - \addr_data_vector[24]\, Y => \un1_address[24]\); - - \update_r[0]\ : DFN1C0 - port map(D => update_and_sel_7(0), CLK => lclk_c, CLR => - rstn, Q => \update_r[0]_net_1\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f0(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f0(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : NOR3C - port map(A => \addr_data_vector[7]\, B => N_13_0_i_0, C => - \addr_data_vector[8]\, Y => N_16_0); - - un1_address_m58 : AX1C - port map(A => \addr_data_vector[21]\, B => N_36_0, C => - \addr_data_vector[22]\, Y => \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f0(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[3]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : AX1C - port map(A => \addr_data_vector[28]\, B => N_45, C => - \addr_data_vector[29]\, Y => \un1_address[29]\); - - un1_address_m34 : AX1C - port map(A => \addr_data_vector[19]\, B => N_32_0, C => - \addr_data_vector[20]\, Y => \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f0(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(0), B => N_131, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : XOR2 - port map(A => N_23_0, B => \addr_data_vector[13]\, Y => - N_55_0_i_0); - - un1_address_m22 : NOR3C - port map(A => \addr_data_vector[11]\, B => N_19_0, C => - \addr_data_vector[12]\, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[7]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[5]_net_1\); - - un1_address_m37_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[17]\, B => - \addr_data_vector[18]\, Y => m37_m6_0_a2_2); - - un1_address_m3 : NOR3C - port map(A => \addr_data_vector[3]\, B => N_2, C => - \addr_data_vector[4]\, Y => N_4_0); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - un1_address_m25 : XOR2 - port map(A => N_25_0, B => \addr_data_vector[15]\, Y => - N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => lclk_c, CLR => rstn, Q => - \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_7(1), CLK => lclk_c, CLR => - rstn, Q => \update_r[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - \update_r_RNI3QAD[0]\ : NOR2A - port map(A => \update_r[0]_net_1\, B => \update_r[1]_net_1\, - Y => \un1_state_12_3_0[4]\); - - un1_address_m57 : XOR2 - port map(A => N_36_0, B => \addr_data_vector[21]\, Y => - \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - un1_address_m37_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[16]\, B => - \addr_data_vector[15]\, C => m37_m6_0_a2_2, Y => - m37_m6_0_a2_5); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f0(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : XOR2 - port map(A => N_2, B => \addr_data_vector[3]\, Y => - N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[9]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f0(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f0(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m37_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[20]\, B => - \addr_data_vector[19]\, C => m37_m6_0_a2_4, Y => - m37_m6_0_a2_6); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[30]\, B => N_47, C => - \addr_data_vector[31]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - un1_address_m23 : OR2B - port map(A => N_23_0, B => \addr_data_vector[13]\, Y => - N_24_0); - - status_full_err_RNO : AO1A - port map(A => N_129, B => \state[2]_net_1\, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f0(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[11]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : AX1C - port map(A => \addr_data_vector[17]\, B => N_29_0, C => - \addr_data_vector[18]\, Y => \un1_address[18]\); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f0(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - un1_address_m44 : NOR2A - port map(A => \addr_data_vector[27]\, B => N_44, Y => N_45); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f0(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f0(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[21]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - un1_address_m62 : XNOR2 - port map(A => N_44, B => \addr_data_vector[27]\, Y => - \un1_address[27]\); - - un1_address_m32 : XOR2 - port map(A => N_32_0, B => \addr_data_vector[19]\, Y => - \un1_address[19]\); - - \state_RNIB6M2[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - un1_address_m12_e : OR2B - port map(A => N_4_0, B => \addr_data_vector[5]\, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => lclk_c, CLR => rstn, Q => - \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[17]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[30]\, Y => - \un1_address[30]\); - - un1_address_m35 : NOR3C - port map(A => \addr_data_vector[19]\, B => N_32_0, C => - \addr_data_vector[20]\, Y => N_36_0); - - un1_address_m52 : XOR2 - port map(A => N_13_0_i_0, B => \addr_data_vector[7]\, Y => - N_1_i_0); - - \update_r_RNIDCCK01[0]\ : OR2A - port map(A => state7, B => address_0_sqmuxa_0, Y => - address_0_sqmuxa_i_0); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[27]\); - - un1_address_m37_m6_0_a2 : OR3B - port map(A => m37_m6_0_a2_6, B => m37_m6_0_a2_5, C => - N_24_0, Y => N_38_0_i); - - \state_RNO[3]\ : NOR2B - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : AX1C - port map(A => \addr_data_vector[11]\, B => N_19_0, C => - \addr_data_vector[12]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : XNOR2 - port map(A => N_24_0, B => \addr_data_vector[14]\, Y => - N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f0(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f0(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - \state_RNIDCCK01[3]\ : OR2A - port map(A => \state[3]_net_1\, B => nb_send_1_sqmuxa, Y - => un1_state_9); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f0(1), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => addr_data_vector_1); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_11, Q => status_full(0)); - - un1_address_m63 : XOR2 - port map(A => N_45, B => \addr_data_vector[28]\, Y => - \un1_address[28]\); - - \address_RNINCI5[22]\ : MX2C - port map(A => \addr_data_vector[22]\, B => - addr_data_vector_86, S => sel_data_1(1), Y => N_1385); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f0(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR3C - port map(A => \addr_data_vector[28]\, B => N_45, C => - \addr_data_vector[29]\, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : AX1C - port map(A => \addr_data_vector[9]\, B => N_16_0, C => - \addr_data_vector[10]\, Y => N_54_0_i_0); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f0(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - \address_RNI1LJ5[27]\ : MX2C - port map(A => \addr_data_vector[27]\, B => - addr_data_vector_91, S => sel_data_1(1), Y => N_1376); - - \address_RNIJ9D7[2]\ : MX2C - port map(A => \addr_data_vector[2]\, B => - addr_data_vector_66, S => sel_data_1(1), Y => N_1393); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_dma_send_16word is - - port( un7_dmain : out std_logic_vector(66 to 66); - state_0_0 : in std_logic; - Address_RNIJ4SP : out std_logic_vector(20 to 20); - Address_RNIP8BS : out std_logic_vector(0 to 0); - data_address : in std_logic_vector(31 downto 0); - bco_msb_1_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - bco_msb_1 : in std_logic_vector(1 to 1); - hmaster_0 : in std_logic_vector(1 to 1); - l1_0_m : in std_logic_vector(1 to 1); - nhmaster_1_i : in std_logic_vector(0 to 0); - iosn_0 : in std_logic_vector(93 to 93); - Lock : out std_logic; - Request_0 : in std_logic; - N_1081 : out std_logic; - Store_0 : in std_logic; - N_1082 : out std_logic; - Fault : in std_logic; - N_1022 : out std_logic; - data_send_ok : out std_logic; - data_send_ko : out std_logic; - N_1102 : out std_logic; - N_1027 : out std_logic; - N_1026 : out std_logic; - N_1025 : out std_logic; - N_1024 : out std_logic; - N_1023 : out std_logic; - N_1021 : out std_logic; - N_1034 : out std_logic; - N_1033 : out std_logic; - N_1031 : out std_logic; - N_1030 : out std_logic; - N_1029 : out std_logic; - N_1028 : out std_logic; - N_1041 : out std_logic; - time_select : in std_logic; - N_1040 : out std_logic; - N_1039 : out std_logic; - N_1038 : out std_logic; - N_1036 : out std_logic; - N_1035 : out std_logic; - N_1048 : out std_logic; - N_1047 : out std_logic; - N_1046 : out std_logic; - N_1044 : out std_logic; - N_1043 : out std_logic; - N_1042 : out std_logic; - N_1020 : out std_logic; - N_1019 : out std_logic; - N_1018 : out std_logic; - data_fifo_ren : out std_logic; - N_1032 : out std_logic; - N_1045 : out std_logic; - time_select_0 : in std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - Grant_1_0 : in std_logic; - m19_0_N_15_i_0_li : in std_logic; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - OKAY : in std_logic; - Ready : in std_logic; - data_send : in std_logic; - Grant_0 : in std_logic; - Grant : in std_logic; - m26_m1_e : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_dma_send_16word; - -architecture DEF_ARCH of lpp_dma_send_16word is - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[5]_net_1\, N_4, N_154_0, N_235, - \state[3]_net_1\, N_242, N_202_0, N_200, N_198_0, N_348, - \grant_counter_0_i_0_0[17]\, \grant_counter_0_i_5[17]\, - \data_counter_8_i_0_0[0]\, N_516_2, N_508, - \data_counter_8_i_0[0]\, \grant_counter_0_i_a0_5[17]\, - \grant_counter_0_i_a0_0[17]\, - \grant_counter_0_i_a0_4[17]\, - \grant_counter_0_i_a0_2[17]\, \grant_counter[12]_net_1\, - \grant_counter[11]_net_1\, \grant_counter_0_i_a0_2_0[17]\, - \grant_counter[10]_net_1\, \grant_counter[14]_net_1\, - \grant_counter[16]_net_1\, \grant_counter[17]_net_1\, - ADD_32x32_fast_I129_un1_Y_12, ADD_32x32_fast_I129_un1_Y_9, - ADD_32x32_fast_I129_un1_Y_8, ADD_32x32_fast_I129_un1_Y_10, - ADD_32x32_fast_I129_un1_Y_2, ADD_32x32_fast_I129_un1_Y_1, - m49_m6_0_a2_0, ADD_32x32_fast_I129_un1_Y_0, - ADD_32x32_fast_I129_un1_Y_5, m75_m6_0_a2_1, - \grant_counter[25]_net_1\, \grant_counter[24]_net_1\, - ADD_32x32_fast_I129_un1_Y_4, \grant_counter[23]_net_1\, - \grant_counter[15]_net_1\, \grant_counter[18]_net_1\, - \grant_counter[21]_net_1\, \grant_counter[22]_net_1\, - \grant_counter[29]_net_1\, \grant_counter[19]_net_1\, - \grant_counter[20]_net_1\, \grant_counter[26]_net_1\, - m49_m6_0_a2_5, \grant_counter_0_i_6_tz_1_0[17]\, - m49_m6_0_a2_4, m49_m6_0_a2_2, m45_m6_0_a2_2, - \data_counter_8_i_a4_2_0[0]\, \state[0]_net_1\, m71_0, - \data_counter[28]_net_1\, \data_counter[27]_net_1\, - m63_m6_0_a2_6, m63_m6_0_a2_4, m23_m6_0_a2_4, - m63_m6_0_a2_3, m55_m6_0_a2_4, m63_m6_0_a2_0, - m63_m6_0_a2_1_0, m26_m6_e_0, m63_m6_0_a2_1, - grant_counter_0_i_20_b0_0_o2_4, - grant_counter_0_i_20_b0_0_o2_1, - grant_counter_0_i_20_b0_0_o2_2, - \grant_counter_0_i_6_tz_1[17]\, m45_m6_0_a2_6, - m45_m6_0_a2_4, \m26_m1_e\, \grant_counter[13]_net_1\, - \grant_counter[9]_net_1\, m26_m6_e_3, m26_m6_e_1, N_241, - m26_m6_e_0_0, ADD_32x32_fast_I129_un1_Y_13, - ADD_32x32_fast_I129_un1_Y_8_0, - ADD_32x32_fast_I129_un1_Y_7, - ADD_32x32_fast_I129_un1_Y_12_0, - ADD_32x32_fast_I129_un1_Y_4_0, - ADD_32x32_fast_I129_un1_Y_10_0, m57_m6_0_a2_7_1, - \data_counter[19]_net_1\, \data_counter[16]_net_1\, - ADD_32x32_fast_I129_un1_Y_6, \data_counter[26]_net_1\, - \data_counter[25]_net_1\, ADD_32x32_fast_I129_un1_Y_3, - \data_counter[22]_net_1\, \data_counter[21]_net_1\, - ADD_32x32_fast_I129_un1_Y_1_0, \data_counter[20]_net_1\, - \data_counter[14]_net_1\, \data_counter[15]_net_1\, - \data_counter[29]_net_1\, \data_counter[23]_net_1\, - \data_counter[24]_net_1\, m17_m2_e_3, m17_m2_e_2, - m17_m2_e_0, \grant_counter[1]_net_1\, - \grant_counter[2]_net_1\, \grant_counter[0]_net_1\, m59_0, - m28_m6_0_a2_4, m57_m6_0_a2_7_5, m43_0, un1_state_9_i_a4_0, - N_246, un1_state_2_i_a2_m8_i_2, un1_state_2_i_a2_m8_i_0, - un1_state_2_i_o2_0, \state[4]_net_1\, m19_0_m8_i_1, - m75_m6_0_a2_3, m75_m6_0_a2_2, m75_m6_0_a2_0, - \grant_counter[30]_net_1\, un1_state_5_i_o2_29, - un1_state_5_i_o2_21, un1_state_5_i_o2_20, - un1_state_5_i_o2_27, un1_state_5_i_o2_28, - un1_state_5_i_o2_17, un1_state_5_i_o2_16, - un1_state_5_i_o2_25, un1_state_5_i_o2_13, - un1_state_5_i_o2_12, un1_state_5_i_o2_23, - un1_state_5_i_o2_5, un1_state_5_i_o2_4, - un1_state_5_i_o2_19, \data_counter[1]_net_1\, - \data_counter[0]_net_1\, un1_state_5_i_o2_15, - un1_state_5_i_o2_11, \data_counter[11]_net_1\, - un1_state_5_i_o2_9, un1_state_5_i_o2_7, - \data_counter[18]_net_1\, un1_state_5_i_o2_3, - \data_counter[6]_net_1\, \data_counter[5]_net_1\, - un1_state_5_i_o2_1, \data_counter[13]_net_1\, - \data_counter[31]_net_1\, \data_counter[2]_net_1\, - \data_counter[3]_net_1\, \data_counter[12]_net_1\, - \data_counter[17]_net_1\, \data_counter[9]_net_1\, - \data_counter[10]_net_1\, \data_counter[7]_net_1\, - \data_counter[8]_net_1\, \data_counter[30]_net_1\, - \data_counter[4]_net_1\, m19_a1_6_4, m19_a1_6_3, - m19_a1_6_1, \state_ns_i_a2_i_0_0[0]\, \state[1]_net_1\, - un1_state_7_i_a4_0_1, N_518_1, m67_m6_0_a2_4_4, - m67_m6_0_a2_4_2, m67_m6_0_a2_4_3, m57_m6_0_a2_7_0, - m57_m6_0_a2_7_4, m57_m6_0_a2_7_2, m23_m6_0_a2_4_6, - \grant_counter[7]_net_1\, m23_m6_0_a2_4_4, - m23_m6_0_a2_4_5, \grant_counter[4]_net_1\, - \grant_counter[3]_net_1\, m23_m6_0_a2_4_2, - \grant_counter[8]_net_1\, \grant_counter[5]_net_1\, - \grant_counter[6]_net_1\, \state_ns_i_a2_0_i_o2_28[3]\, - \state_ns_i_a2_0_i_o2_19[3]\, - \state_ns_i_a2_0_i_o2_18[3]\, - \state_ns_i_a2_0_i_o2_24[3]\, - \state_ns_i_a2_0_i_o2_27[3]\, - \state_ns_i_a2_0_i_o2_13[3]\, - \state_ns_i_a2_0_i_o2_12[3]\, - \state_ns_i_a2_0_i_o2_23[3]\, - \state_ns_i_a2_0_i_o2_26[3]\, \state_ns_i_a2_0_i_o2_9[3]\, - \state_ns_i_a2_0_i_o2_8[3]\, \state_ns_i_a2_0_i_o2_21[3]\, - \state_ns_i_a2_0_i_o2_3[3]\, \state_ns_i_a2_0_i_o2_2[3]\, - \state_ns_i_a2_0_i_o2_16[3]\, - \state_ns_i_a2_0_i_o2_15[3]\, - \state_ns_i_a2_0_i_o2_11[3]\, \state_ns_i_a2_0_i_o2_7[3]\, - \state_ns_i_a2_0_i_o2_5[3]\, \grant_counter[27]_net_1\, - \grant_counter[31]_net_1\, \grant_counter[28]_net_1\, - m55_m6_0_a2_4_4, m55_m6_0_a2_4_0, m55_m6_0_a2_4_3, - m28_m6_0_a2_4_6, m28_m6_0_a2_4_4, m28_m6_0_a2_4_5, - m28_m6_0_a2_4_2, m19_a0_6_4, m19_a0_6_3, - \grant_counter_0_i_6_tz_3[17]\, - \grant_counter_0_i_6_tz_2[17]\, I129_un1_Y, N_28_0, N_75, - N_72, I129_un1_Y_0, N623, N_186, - \grant_counter_RNO[0]_net_1\, N_30_0, N_354, N_89, - \un1_hresetn_inv_2_i_i[27]\, N_346, N_526, N_194, N_522, - Burst, m19_0_m8_i, \un1_state_2_i_a2_m8_i_a4\, m26tt_N_7, - \state_RNI6R78T9[4]_net_1\, \state_RNI7ALP[4]_net_1\, - m67_m6_0_a2_4, N_50, m26_m3_e, - \grant_counter_RNO_0[17]_net_1\, N_115, - \grant_counter_RNO_2[17]_net_1\, m75_m6_0_a2, - un1_hresetn_inv_i_0_a2_0, N_28_0_0, N_26_0, N_68, - \un1_state_4_i[31]\, \data_counter_8_i_0_tz[0]\, N_58, - N_20_0, \un1_hresetn_inv_2_i[0]\, - grant_counter_0_i_20_N_14_i, N_121, N_68_0, - un1_state_2_i_a2_N_3_i_0_li, \state_RNITA375[4]_net_1\, - N_24_0, un1_hresetn_inv_i_0, N_56, \state[2]_net_1\, - N_243_i, N_13, N_59, N_75_0, \Address[0]\, \Address[28]\, - \Address[20]\, \Address[15]\, N_49, N_17_0, N_19_0, - N_20_0_0, N_21_0, N_22_0, N_23_0, N_25_0, N_26_0_0, - N_31_0_i_0, N_32_0_i_0, N_33_0_i_0, - \un1_hresetn_inv_2_i[19]\, \un1_hresetn_inv_2_i[18]\, - N_44, \un1_hresetn_inv_2_i[15]\, - \un1_hresetn_inv_2_i[13]\, \un1_hresetn_inv_2_i[12]\, - \un1_hresetn_inv_2_i[10]\, \un1_hresetn_inv_2_i[9]\, N_60, - N_62, \un1_hresetn_inv_2_i[6]\, N_66, - \un1_hresetn_inv_2_i[5]\, \un1_hresetn_inv_2_i[4]\, - \un1_hresetn_inv_2_i[3]\, N_72_0, - \un1_hresetn_inv_2_i_0[17]\, N_17_0_0, N_8, N_19_0_0, - N_22_0_0, N_23_0_0, N_24_0_0, N_25_0_0, N_27_0, - \un1_state_4_i[30]\, \un1_state_4_i[29]\, - \un1_state_4_i[28]\, N_36_0, N_45, N_46, N_48, N_50_0, - N_52, N_54, N_56_0, N_61, N_62_0, N_64, N_66_0, N_70, - N_249, Request_5, N_513, \data_counter_8[4]\, - \data_counter_8[5]\, \data_counter_8[6]\, - \data_counter_8[7]\, \data_counter_8[8]\, - \data_counter_8[9]\, \data_counter_8[10]\, - \data_counter_8[11]\, \data_counter_8[12]\, - \data_counter_8[13]\, \data_counter_8[14]\, - \data_counter_8[15]\, \data_counter_8[16]\, - \data_counter_8[17]\, \data_counter_8[18]\, N_198, - \data_counter_8[19]\, \data_counter_8[20]\, - \data_counter_8[21]\, \data_counter_8[22]\, - \data_counter_8[23]\, \data_counter_8[24]\, - \data_counter_8[25]\, \data_counter_8[26]\, - \data_counter_8[27]\, \data_counter_8[28]\, - \data_counter_8[29]\, \data_counter_8[30]\, - \data_counter_8[31]\, N_509, N_15, N_17, N_19, N_21, N_25, - N_27, N_29, N_31, N_33, N_35, N_43, N_45_0, N_47, N_51, - \state[5]_net_1\, N_53, N_55, N_57, N_61_0, N_63, N_65, - N_67, N_69, N_71, N_73, N_77, N_79, N_81, N_84, - \grant_counter_RNO[1]_net_1\, - \grant_counter_RNO[2]_net_1\, - \grant_counter_RNO[3]_net_1\, N_91, N_93, N_95, N_97, - N_99, N_101, N_103, N_105, N_107, N_109, N_202, N_111, - N_113, N_117, N_119, N_123, N_125, N_127, N_129, N_131, - N_133, N_135, N_137, N_139, N_141, N_143, N_188, N_343, - N_190, N_192, \Address[1]\, \Address[2]\, \Address[3]\, - \Address[25]\, \Address[26]\, \Address[27]\, - \Address[29]\, \Address[30]\, \Address[31]\, - \Address[18]\, \Address[19]\, \Address[21]\, - \Address[22]\, \Address[23]\, \Address[24]\, - \Address[11]\, \Address[12]\, \Address[13]\, - \Address[14]\, \Address[16]\, \Address[17]\, \Address[4]\, - \Address[6]\, \Address[7]\, \Address[8]\, \Address[9]\, - \Address[10]\, N_516, N_151, N_146, \Address[5]\, N_23, - N_523, \state_RNO[0]_net_1\, N_156, N_154, - \state_RNO[3]_net_1\, Store, Request, \data_send_ok\, - \data_send_ko\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - data_send_ok <= \data_send_ok\; - data_send_ko <= \data_send_ko\; - m26_m1_e <= \m26_m1_e\; - - \state_RNIVDV42_0[3]\ : OR2A - port map(A => \state[3]_net_1\, B => Fault, Y => N_522); - - \DMAIn.Address_RNI1PBS[1]\ : MX2 - port map(A => \Address[1]\, B => data_address(1), S => - time_select_0, Y => N_1018); - - un1_hresetn_inv_2_m66 : XOR2 - port map(A => N_66, B => \grant_counter[26]_net_1\, Y => - \un1_hresetn_inv_2_i[5]\); - - \state_RNIT2U41[4]\ : NOR3B - port map(A => un1_state_2_i_a2_m8_i_0, B => Grant_0, C => - un1_state_2_i_o2_0, Y => un1_state_2_i_a2_m8_i_2); - - \state_RNI3LQC[1]\ : OR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => un1_state_2_i_o2_0); - - \grant_counter_RNO_2[17]\ : OA1C - port map(A => \grant_counter[9]_net_1\, B => m26_m3_e, C - => \grant_counter[17]_net_1\, Y => - \grant_counter_RNO_2[17]_net_1\); - - \DMAIn.Address[7]\ : DFN1E1C0 - port map(D => N_27, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[7]\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_6 : NOR2B - port map(A => \data_counter[20]_net_1\, B => - \data_counter[27]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_6); - - \state[0]\ : DFN1C0 - port map(D => \state_RNO[0]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[0]_net_1\); - - \data_counter_RNILKKA[2]\ : NOR2B - port map(A => \data_counter[2]_net_1\, B => - \data_counter[3]_net_1\, Y => un1_state_5_i_o2_15); - - \state_RNI0P0IVI[4]\ : OR2B - port map(A => N_200, B => rstn, Y => N_202); - - \data_counter_RNO[31]\ : XA1C - port map(A => \data_counter[31]_net_1\, B => N_75, C => - N_198, Y => \data_counter_8[31]\); - - un1_hresetn_inv_2_m55_m6_0_a2_4_4 : NOR3B - port map(A => m55_m6_0_a2_4_0, B => - \grant_counter[14]_net_1\, C => m49_m6_0_a2_0, Y => - m55_m6_0_a2_4_4); - - un1_state_4_m51 : OR2B - port map(A => N_50_0, B => \data_counter[18]_net_1\, Y => - N_52); - - \data_counter_RNO[2]\ : AOI1 - port map(A => \un1_state_4_i[29]\, B => N_343, C => N_509, - Y => N_190); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_3 : OR2B - port map(A => \grant_counter[28]_net_1\, B => - \grant_counter[27]_net_1\, Y => m75_m6_0_a2_1); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y : NOR3C - port map(A => \grant_counter[13]_net_1\, B => N_28_0, C => - ADD_32x32_fast_I129_un1_Y_12, Y => I129_un1_Y); - - \data_counter_RNO[18]\ : XA1B - port map(A => \data_counter[18]_net_1\, B => N_50_0, C => - N_198, Y => \data_counter_8[18]\); - - \grant_counter_RNO[5]\ : XA1 - port map(A => \grant_counter[5]_net_1\, B => N_20_0_0, C - => N_202_0, Y => N_91); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_10 : NOR3C - port map(A => \data_counter[19]_net_1\, B => - \data_counter[16]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_6, Y => - ADD_32x32_fast_I129_un1_Y_10_0); - - \state_RNIKOCB2[3]\ : MX2A - port map(A => \state[5]_net_1\, B => Fault, S => - \state[3]_net_1\, Y => N_242); - - un1_state_4_m49 : NOR2B - port map(A => N_48, B => \data_counter[17]_net_1\, Y => - N_50_0); - - \DMAIn.Address_RNI99CS[2]\ : MX2C - port map(A => \Address[2]\, B => data_address(2), S => - time_select_0, Y => N_1019); - - \DMAIn.Address_RNI6BCP[17]\ : MX2C - port map(A => \Address[17]\, B => data_address(17), S => - time_select, Y => N_1034); - - un1_state_4_m19_a0_6_3 : NOR3B - port map(A => \data_counter[0]_net_1\, B => - \data_counter[4]_net_1\, C => \state[3]_net_1\, Y => - m19_a0_6_3); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_5 : OR2B - port map(A => \data_counter[18]_net_1\, B => - \data_counter[17]_net_1\, Y => m57_m6_0_a2_7_1); - - \grant_counter_RNO[26]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[5]\, Y => - N_133); - - \DMAIn.Address_RNINP361[30]\ : MX2C - port map(A => \Address[30]\, B => data_address(30), S => - time_select_0, Y => N_1047); - - \DMAIn.Address_RNO[20]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(20), Y - => N_59); - - un1_state_2_i_a2_m2 : MX2A - port map(A => hmaster_0(1), B => bco_msb_1(1), S => - un1_nhmaster_0_sqmuxa_1, Y => un1_state_2_i_a2_N_3_i_0_li); - - \grant_counter[0]\ : DFN1 - port map(D => \grant_counter_RNO[0]_net_1\, CLK => lclk_c, - Q => \grant_counter[0]_net_1\); - - \DMAIn.Address[6]\ : DFN1E1C0 - port map(D => N_25, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[6]\); - - un1_state_4_m53 : NOR2A - port map(A => \data_counter[19]_net_1\, B => N_52, Y => - N_54); - - un1_hresetn_inv_2_m52 : AX1E - port map(A => \grant_counter[18]_net_1\, B => N_50, C => - \grant_counter[19]_net_1\, Y => \un1_hresetn_inv_2_i[12]\); - - \grant_counter[20]\ : DFN1 - port map(D => N_121, CLK => lclk_c, Q => - \grant_counter[20]_net_1\); - - \DMAIn.Address_RNO[27]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(27), Y - => N_73); - - un1_hresetn_inv_2_m63_m6_0_a2_1 : OR2B - port map(A => \grant_counter[22]_net_1\, B => - \grant_counter[21]_net_1\, Y => m63_m6_0_a2_1); - - send_ko_RNIMB9E : OR3A - port map(A => state_0_0, B => \data_send_ko\, C => - \data_send_ok\, Y => N_1102); - - \data_counter_RNO[14]\ : XA1C - port map(A => \data_counter[14]_net_1\, B => N623, C => - N_198_0, Y => \data_counter_8[14]\); - - \data_counter_RNO[21]\ : XA1C - port map(A => \data_counter[21]_net_1\, B => N_56_0, C => - N_198, Y => \data_counter_8[21]\); - - \state_RNI4LQC[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => \state[0]_net_1\, Y - => un1_state_2_i_a2_m8_i_0); - - \DMAIn.Address[2]\ : DFN1E1C0 - port map(D => N_17, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[2]\); - - \DMAIn.Address[28]\ : DFN1E1C0 - port map(D => N_75_0, CLK => lclk_c, CLR => rstn, E => - N_154, Q => \Address[28]\); - - un1_state_4_m19 : MX2C - port map(A => nhmaster_1_i(0), B => - \state_RNITA375[4]_net_1\, S => m19_0_m8_i, Y => N_20_0); - - \grant_counter[26]\ : DFN1 - port map(D => N_133, CLK => lclk_c, Q => - \grant_counter[26]_net_1\); - - \grant_counter[29]\ : DFN1 - port map(D => N_139, CLK => lclk_c, Q => - \grant_counter[29]_net_1\); - - \grant_counter[1]\ : DFN1 - port map(D => \grant_counter_RNO[1]_net_1\, CLK => lclk_c, - Q => \grant_counter[1]_net_1\); - - \data_counter[16]\ : DFN1C0 - port map(D => \data_counter_8[16]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[16]_net_1\); - - \data_counter[13]\ : DFN1C0 - port map(D => \data_counter_8[13]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[13]_net_1\); - - un1_state_4_m74 : OR3C - port map(A => \data_counter[29]_net_1\, B => - \data_counter[30]_net_1\, C => N_72, Y => N_75); - - \grant_counter_RNISC3J[8]\ : NOR3 - port map(A => \grant_counter[30]_net_1\, B => - \grant_counter[8]_net_1\, C => \grant_counter[9]_net_1\, - Y => \state_ns_i_a2_0_i_o2_13[3]\); - - \state_RNI98EI[1]\ : AO1A - port map(A => data_send, B => \state_0[5]_net_1\, C => - \state[1]_net_1\, Y => \state_ns_i_a2_i_0_0[0]\); - - \state_RNIQDFIVJ_1[3]\ : AOI1 - port map(A => N_235, B => \state[3]_net_1\, C => N_348, Y - => N_198_0); - - un1_hresetn_inv_2_m21 : NOR2B - port map(A => N_21_0, B => \grant_counter[6]_net_1\, Y => - N_22_0); - - \state_0[5]\ : DFN1P0 - port map(D => N_4, CLK => lclk_c, PRE => rstn, Q => - \state_0[5]_net_1\); - - \DMAIn.Address[29]\ : DFN1E1C0 - port map(D => N_77, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[29]\); - - \grant_counter_RNO[3]\ : AO1 - port map(A => N_33_0_i_0, B => N_202_0, C => N_513, Y => - \grant_counter_RNO[3]_net_1\); - - \DMAIn.Address_RNI6E8P[10]\ : MX2C - port map(A => \Address[10]\, B => data_address(10), S => - time_select, Y => N_1027); - - un1_hresetn_inv_2_m20 : NOR2B - port map(A => N_20_0_0, B => \grant_counter[5]_net_1\, Y - => N_21_0); - - \grant_counter_RNI5E6K[31]\ : NOR3 - port map(A => \grant_counter[4]_net_1\, B => - \grant_counter[31]_net_1\, C => \grant_counter[14]_net_1\, - Y => \state_ns_i_a2_0_i_o2_16[3]\); - - un1_state_4_m28_m6_0_a2 : OR2B - port map(A => m28_m6_0_a2_4, B => N_20_0, Y => N623); - - un1_hresetn_inv_2_m26_m6_e_0_0 : NOR2A - port map(A => \grant_counter[10]_net_1\, B => m26_m6_e_0, Y - => m26_m6_e_0_0); - - \grant_counter_RNO[16]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[15]\, Y => - N_113); - - \grant_counter_RNITN6E[19]\ : NOR2 - port map(A => \grant_counter[19]_net_1\, B => - \grant_counter[21]_net_1\, Y => - \state_ns_i_a2_0_i_o2_7[3]\); - - \data_counter[11]\ : DFN1C0 - port map(D => \data_counter_8[11]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[11]_net_1\); - - \DMAIn.Address_RNIDD721[29]\ : MX2C - port map(A => \Address[29]\, B => data_address(29), S => - time_select_0, Y => N_1046); - - un1_hresetn_inv_2_m49_m6_0_a2_4 : NOR2A - port map(A => m45_m6_0_a2_2, B => m49_m6_0_a2_0, Y => - m49_m6_0_a2_4); - - \data_counter[8]\ : DFN1C0 - port map(D => \data_counter_8[8]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[8]_net_1\); - - \grant_counter_RNO[4]\ : NOR3C - port map(A => \un1_hresetn_inv_2_i_i[27]\, B => N_202_0, C - => N_354, Y => N_89); - - \DMAIn.Address[1]\ : DFN1E1C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[1]\); - - \DMAIn.Address[13]\ : DFN1E1C0 - port map(D => N_45_0, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[13]\); - - \data_counter_RNI3BF9[14]\ : NOR2 - port map(A => \data_counter[14]_net_1\, B => - \data_counter[15]_net_1\, Y => un1_state_5_i_o2_11); - - \DMAIn.Address[30]\ : DFN1E1C0 - port map(D => N_79, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[30]\); - - \DMAIn.Address_RNO[0]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(0), Y - => N_13); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \grant_counter[25]_net_1\, B => - \grant_counter[24]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_4, Y => - ADD_32x32_fast_I129_un1_Y_8); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_5 : NOR2B - port map(A => \grant_counter[23]_net_1\, B => - \grant_counter[14]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_5); - - \grant_counter_RNIQ76E[22]\ : NOR2 - port map(A => \grant_counter[22]_net_1\, B => - \grant_counter[24]_net_1\, Y => - \state_ns_i_a2_0_i_o2_8[3]\); - - \DMAIn.Address_RNO[10]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(10), Y - => N_33); - - \data_counter_RNIC7H61[10]\ : NOR3C - port map(A => un1_state_5_i_o2_5, B => un1_state_5_i_o2_4, - C => un1_state_5_i_o2_19, Y => un1_state_5_i_o2_25); - - un1_state_4_ADD_32x32_fast_I129_un1_Y : NOR2A - port map(A => ADD_32x32_fast_I129_un1_Y_13, B => N623, Y - => I129_un1_Y_0); - - \DMAIn.Address_RNO[5]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(5), Y => - N_23); - - un1_hresetn_inv_2_m75_m6_0_a2_3 : NOR2B - port map(A => m75_m6_0_a2_2, B => m23_m6_0_a2_4, Y => - m75_m6_0_a2_3); - - send_ok : DFN1E1C0 - port map(D => \state[0]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_146, Q => \data_send_ok\); - - \grant_counter_RNO[9]\ : XA1A - port map(A => \grant_counter[9]_net_1\, B => N_24_0, C => - N_202_0, Y => N_99); - - \DMAIn.Address_RNIA0321[22]\ : MX2C - port map(A => \Address[22]\, B => data_address(22), S => - time_select_0, Y => N_1039); - - \grant_counter_RNI7OKM1[1]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_9[3]\, B => - \state_ns_i_a2_0_i_o2_8[3]\, C => - \state_ns_i_a2_0_i_o2_21[3]\, Y => - \state_ns_i_a2_0_i_o2_26[3]\); - - \DMAIn.Address[31]\ : DFN1E1C0 - port map(D => N_81, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[31]\); - - \data_counter_RNIVSLA[7]\ : NOR2 - port map(A => \data_counter[7]_net_1\, B => - \data_counter[8]_net_1\, Y => un1_state_5_i_o2_3); - - \grant_counter[25]\ : DFN1 - port map(D => N_131, CLK => lclk_c, Q => - \grant_counter[25]_net_1\); - - \DMAIn.Address_RNO[17]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(17), Y - => N_53); - - un1_state_4_m18 : OR3C - port map(A => \data_counter[2]_net_1\, B => N_17_0_0, C => - \data_counter[3]_net_1\, Y => N_19_0_0); - - un1_state_4_m55 : OR2B - port map(A => N_54, B => \data_counter[20]_net_1\, Y => - N_56_0); - - un1_state_4_m28_m6_0_a2_4_6 : NOR3C - port map(A => \data_counter[12]_net_1\, B => - \data_counter[10]_net_1\, C => m28_m6_0_a2_4_4, Y => - m28_m6_0_a2_4_6); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \data_counter[23]_net_1\, B => - \data_counter[24]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_1_0); - - un1_hresetn_inv_2_m71 : OR3C - port map(A => \grant_counter[27]_net_1\, B => N_68_0, C => - \grant_counter[28]_net_1\, Y => N_72_0); - - \state[4]\ : DFN1C0 - port map(D => N_84, CLK => lclk_c, CLR => rstn, Q => - \state[4]_net_1\); - - \grant_counter_RNO[6]\ : XA1 - port map(A => \grant_counter[6]_net_1\, B => N_21_0, C => - N_202_0, Y => N_93); - - \state_0_RNIOT0C[5]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_send, Y => - Request_5); - - \data_counter_RNO[22]\ : XA1C - port map(A => \data_counter[22]_net_1\, B => N_58, C => - N_198, Y => \data_counter_8[22]\); - - \data_counter_RNI9IEF2[31]\ : NOR3C - port map(A => un1_state_5_i_o2_17, B => un1_state_5_i_o2_16, - C => un1_state_5_i_o2_25, Y => un1_state_5_i_o2_28); - - \data_counter_RNI6P8L[1]\ : NOR3C - port map(A => \data_counter[1]_net_1\, B => - \data_counter[0]_net_1\, C => un1_state_5_i_o2_15, Y => - un1_state_5_i_o2_23); - - un1_hresetn_inv_2_m70 : AX1E - port map(A => \grant_counter[27]_net_1\, B => N_68_0, C => - \grant_counter[28]_net_1\, Y => \un1_hresetn_inv_2_i[3]\); - - \state_RNIQDFIVJ_0[3]\ : AOI1 - port map(A => N_235, B => \state[3]_net_1\, C => N_348, Y - => N_198); - - \grant_counter_RNO_8[17]\ : NOR3C - port map(A => \grant_counter[11]_net_1\, B => - \grant_counter[16]_net_1\, C => \grant_counter[14]_net_1\, - Y => \grant_counter_0_i_6_tz_2[17]\); - - \DMAIn.Request_RNIBSA9\ : MX2 - port map(A => Request, B => Request_0, S => time_select, Y - => N_1081); - - \DMAIn.Address_RNO[28]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(28), Y - => N_75_0); - - \grant_counter_RNO[20]\ : NOR2A - port map(A => N_202_0, B => grant_counter_0_i_20_N_14_i, Y - => N_121); - - un1_state_4_m21 : NOR3C - port map(A => \data_counter[5]_net_1\, B => N_20_0, C => - \data_counter[6]_net_1\, Y => N_22_0_0); - - un1_hresetn_inv_2_m19 : NOR2B - port map(A => N_19_0, B => \grant_counter[4]_net_1\, Y => - N_20_0_0); - - un1_hresetn_inv_2_m59 : NOR3C - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - \grant_counter[22]_net_1\, Y => N_60); - - \DMAIn.Address_RNI35621[27]\ : MX2C - port map(A => \Address[27]\, B => data_address(27), S => - time_select_0, Y => N_1044); - - \grant_counter_RNO[22]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[9]\, Y => - N_125); - - un1_state_4_m22 : NOR2B - port map(A => N_22_0_0, B => \data_counter[7]_net_1\, Y => - N_23_0_0); - - \data_counter[3]\ : DFN1C0 - port map(D => N_192, CLK => lclk_c, CLR => rstn, Q => - \data_counter[3]_net_1\); - - un1_hresetn_inv_2_m67_m6_0_a2_4_2 : NOR2B - port map(A => \grant_counter[11]_net_1\, B => - \grant_counter[10]_net_1\, Y => m67_m6_0_a2_4_2); - - \DMAIn.Address_RNI9L8L[16]\ : MX2C - port map(A => \Address[16]\, B => data_address(16), S => - time_select, Y => N_1033); - - \state[5]\ : DFN1P0 - port map(D => N_4, CLK => lclk_c, PRE => rstn, Q => - \state[5]_net_1\); - - \grant_counter_RNO[30]\ : XA1 - port map(A => \grant_counter[30]_net_1\, B => I129_un1_Y, C - => N_202, Y => N_141); - - \data_counter_RNO[8]\ : XA1B - port map(A => \data_counter[8]_net_1\, B => N_23_0_0, C => - N_198_0, Y => \data_counter_8[8]\); - - \data_counter[28]\ : DFN1C0 - port map(D => \data_counter_8[28]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[28]_net_1\); - - \data_counter[10]\ : DFN1C0 - port map(D => \data_counter_8[10]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[10]_net_1\); - - \data_counter_RNO[13]\ : XA1C - port map(A => \data_counter[13]_net_1\, B => N_28_0_0, C - => N_198_0, Y => \data_counter_8[13]\); - - \data_counter[12]\ : DFN1C0 - port map(D => \data_counter_8[12]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[12]_net_1\); - - \data_counter[24]\ : DFN1C0 - port map(D => \data_counter_8[24]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[24]_net_1\); - - un1_hresetn_inv_2_m23_m6_0_a2_4_2 : NOR2B - port map(A => \grant_counter[5]_net_1\, B => - \grant_counter[6]_net_1\, Y => m23_m6_0_a2_4_2); - - GND_i : GND - port map(Y => \GND\); - - \DMAIn.Address_RNO[26]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(26), Y - => N_71); - - un1_state_4_m23 : NOR2B - port map(A => N_23_0_0, B => \data_counter[8]_net_1\, Y => - N_24_0_0); - - \DMAIn.Address_RNO[23]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(23), Y - => N_65); - - \DMAIn.Address[12]\ : DFN1E1C0 - port map(D => N_43, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[12]\); - - un1_state_4_m28_m6_0_a2_4_2 : NOR2B - port map(A => \data_counter[8]_net_1\, B => - \data_counter[9]_net_1\, Y => m28_m6_0_a2_4_2); - - un1_state_4_m19_a0_6_1 : NOR2B - port map(A => \data_counter[1]_net_1\, B => - \data_counter[2]_net_1\, Y => m19_a1_6_1); - - \data_counter[27]\ : DFN1C0 - port map(D => \data_counter_8[27]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[27]_net_1\); - - un1_hresetn_inv_2_m65 : OR3C - port map(A => un1_hresetn_inv_i_0_a2_0, B => m63_m6_0_a2_6, - C => \grant_counter[25]_net_1\, Y => N_66); - - \grant_counter_RNO[1]\ : AO1 - port map(A => N_31_0_i_0, B => N_202_0, C => N_513, Y => - \grant_counter_RNO[1]_net_1\); - - \DMAIn.Address[5]\ : DFN1E1C0 - port map(D => N_23, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[5]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_counter_RNO[10]\ : XA1B - port map(A => \data_counter[10]_net_1\, B => N_25_0_0, C - => N_198_0, Y => \data_counter_8[10]\); - - un1_hresetn_inv_2_m17_m2_e_2 : NOR3B - port map(A => m17_m2_e_0, B => \grant_counter[1]_net_1\, C - => N_241, Y => m17_m2_e_2); - - \grant_counter_RNO_5[17]\ : NOR2B - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[17]_net_1\, Y => - \grant_counter_0_i_a0_0[17]\); - - \grant_counter_RNO[28]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[3]\, Y => - N_137); - - un1_state_4_m19_a1_6_3 : NOR3C - port map(A => \data_counter[0]_net_1\, B => - \data_counter[4]_net_1\, C => m19_a1_6_1, Y => m19_a1_6_3); - - \grant_counter[17]\ : DFN1 - port map(D => N_115, CLK => lclk_c, Q => - \grant_counter[17]_net_1\); - - \DMAIn.Burst_RNILOR3\ : NOR2A - port map(A => Burst, B => time_select, Y => un7_dmain(66)); - - \DMAIn.Address_RNI23NR[4]\ : MX2C - port map(A => \Address[4]\, B => data_address(4), S => - time_select, Y => N_1021); - - un1_state_4_m19_a1_6_4 : NOR3A - port map(A => \data_counter[3]_net_1\, B => - \state[0]_net_1\, C => un1_state_2_i_o2_0, Y => - m19_a1_6_4); - - \DMAIn.Address_RNIR3NR[9]\ : MX2C - port map(A => \Address[9]\, B => data_address(9), S => - time_select, Y => N_1026); - - \data_counter_RNO[27]\ : XA1C - port map(A => \data_counter[27]_net_1\, B => N_68, C => - N_198, Y => \data_counter_8[27]\); - - \grant_counter_RNO[24]\ : XA1A - port map(A => \grant_counter[24]_net_1\, B => N_62, C => - N_202, Y => N_129); - - un1_state_4_m19_0_m8_i_1 : NOR3C - port map(A => Grant_0, B => \state[4]_net_1\, C => - iosn_0(93), Y => m19_0_m8_i_1); - - \data_counter[1]\ : DFN1C0 - port map(D => N_188, CLK => lclk_c, CLR => rstn, Q => - \data_counter[1]_net_1\); - - \grant_counter_RNO[10]\ : XA1 - port map(A => \grant_counter[10]_net_1\, B => N_25_0, C => - N_202_0, Y => N_101); - - \grant_counter[30]\ : DFN1 - port map(D => N_141, CLK => lclk_c, Q => - \grant_counter[30]_net_1\); - - \grant_counter[9]\ : DFN1 - port map(D => N_99, CLK => lclk_c, Q => - \grant_counter[9]_net_1\); - - \data_counter_RNO_1[0]\ : AO1D - port map(A => N_516_2, B => N_508, C => - \data_counter_8_i_0[0]\, Y => \data_counter_8_i_0_0[0]\); - - \data_counter_RNO[6]\ : NOR2 - port map(A => N_36_0, B => N_198_0, Y => - \data_counter_8[6]\); - - \state_RNIB9BF8J[4]\ : NOR2 - port map(A => \state[4]_net_1\, B => N_354, Y => N_513); - - \DMAIn.Address_RNO[30]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(30), Y - => N_79); - - un1_hresetn_inv_2_m26_m6_e_3 : NOR3B - port map(A => m26_m6_e_1, B => \m26_m1_e\, C => N_241, Y - => m26_m6_e_3); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[18]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_4); - - \grant_counter_RNO[12]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[19]\, Y - => N_105); - - \DMAIn.Address_RNO[8]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(8), Y - => N_29); - - \DMAIn.Address[9]\ : DFN1E1C0 - port map(D => N_31, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[9]\); - - un1_state_4_m61 : NOR3C - port map(A => N_20_0, B => m59_0, C => - \data_counter[23]_net_1\, Y => N_62_0); - - un1_state_4_m26 : OR2B - port map(A => N_26_0, B => \data_counter[11]_net_1\, Y => - N_27_0); - - \grant_counter[18]\ : DFN1 - port map(D => N_117, CLK => lclk_c, Q => - \grant_counter[18]_net_1\); - - \data_counter_RNIVD2A[30]\ : NOR2 - port map(A => \data_counter[30]_net_1\, B => - \data_counter[4]_net_1\, Y => un1_state_5_i_o2_1); - - un1_hresetn_inv_2_m75_m6_0_a2_0 : NOR2B - port map(A => \grant_counter[30]_net_1\, B => - \grant_counter[29]_net_1\, Y => m75_m6_0_a2_0); - - \data_counter_RNO[4]\ : XA1C - port map(A => \data_counter[4]_net_1\, B => N_19_0_0, C => - N_198_0, Y => \data_counter_8[4]\); - - \data_counter[29]\ : DFN1C0 - port map(D => \data_counter_8[29]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[29]_net_1\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_1 : NOR2B - port map(A => \grant_counter[29]_net_1\, B => - \grant_counter[19]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_1); - - \state_RNIGSLM7[1]\ : AO1D - port map(A => N_346, B => N_246, C => - \state_ns_i_a2_i_0_0[0]\, Y => N_4); - - \DMAIn.Address_RNO[18]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(18), Y - => N_55); - - \DMAIn.Address_RNIR51Q[28]\ : MX2C - port map(A => \Address[28]\, B => data_address(28), S => - time_select_0, Y => N_1045); - - \DMAIn.Address[10]\ : DFN1E1C0 - port map(D => N_33, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[10]\); - - un1_state_4_m31 : XNOR2 - port map(A => N_17_0_0, B => \data_counter[2]_net_1\, Y => - \un1_state_4_i[29]\); - - \DMAIn.Address_RNO[29]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(29), Y - => N_77); - - un1_state_4_m57_m6_0_a2_7_2 : NOR2B - port map(A => \data_counter[19]_net_1\, B => - \data_counter[20]_net_1\, Y => m57_m6_0_a2_7_2); - - \grant_counter_RNI6OES[26]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_5[3]\, B => - \grant_counter[27]_net_1\, C => \grant_counter[26]_net_1\, - Y => \state_ns_i_a2_0_i_o2_18[3]\); - - un1_state_4_m32 : AX1E - port map(A => \data_counter[2]_net_1\, B => N_17_0_0, C => - \data_counter[3]_net_1\, Y => \un1_state_4_i[28]\); - - \data_counter[2]\ : DFN1C0 - port map(D => N_190, CLK => lclk_c, CLR => rstn, Q => - \data_counter[2]_net_1\); - - \state_RNI9IFTVI[4]\ : AO1 - port map(A => \state[4]_net_1\, B => Grant, C => - un1_state_2_i_o2_0, Y => N_243_i); - - \DMAIn.Address_RNIUG521[26]\ : MX2C - port map(A => \Address[26]\, B => data_address(26), S => - time_select_0, Y => N_1043); - - \DMAIn.Address[11]\ : DFN1E1C0 - port map(D => N_35, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[11]\); - - un1_hresetn_inv_2_m23_m6_0_a2_4_5 : NOR3C - port map(A => \grant_counter[4]_net_1\, B => - \grant_counter[3]_net_1\, C => m23_m6_0_a2_4_2, Y => - m23_m6_0_a2_4_5); - - \grant_counter[21]\ : DFN1 - port map(D => N_123, CLK => lclk_c, Q => - \grant_counter[21]_net_1\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_7 : NOR3C - port map(A => \data_counter[22]_net_1\, B => - \data_counter[21]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_1_0, Y => - ADD_32x32_fast_I129_un1_Y_7); - - \grant_counter[22]\ : DFN1 - port map(D => N_125, CLK => lclk_c, Q => - \grant_counter[22]_net_1\); - - \DMAIn.Address_RNIE74U[18]\ : MX2C - port map(A => \Address[18]\, B => data_address(18), S => - time_select_0, Y => N_1035); - - \DMAIn.Address[14]\ : DFN1E1C0 - port map(D => N_47, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[14]\); - - un1_state_4_m63 : NOR2B - port map(A => N_62_0, B => \data_counter[24]_net_1\, Y => - N_64); - - un1_hresetn_inv_2_m23_m6_0_a2_4 : NOR2B - port map(A => m23_m6_0_a2_4_6, B => m23_m6_0_a2_4_5, Y => - m23_m6_0_a2_4); - - un1_state_4_m44 : AX1E - port map(A => N_20_0, B => m43_0, C => - \data_counter[15]_net_1\, Y => N_45); - - \DMAIn.Address_RNIPS421[25]\ : MX2C - port map(A => \Address[25]\, B => data_address(25), S => - time_select_0, Y => N_1042); - - un1_hresetn_inv_2_m45_m6_0_a2_1 : OR2B - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[11]_net_1\, Y => m49_m6_0_a2_2); - - \state_RNO_0[0]\ : OR2A - port map(A => \state[0]_net_1\, B => Ready, Y => N_523); - - \grant_counter_RNO[18]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[13]\, Y => - N_117); - - \DMAIn.Address_RNINEAP[14]\ : MX2C - port map(A => \Address[14]\, B => data_address(14), S => - time_select, Y => N_1031); - - \data_counter[0]\ : DFN1C0 - port map(D => N_186, CLK => lclk_c, CLR => rstn, Q => - \data_counter[0]_net_1\); - - \grant_counter_RNO[27]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[4]\, Y => - N_135); - - \DMAIn.Address_RNO[16]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(16), Y - => N_51); - - \grant_counter_RNO[14]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i_0[17]\, Y - => N_109); - - \DMAIn.Address_RNIB29P[11]\ : MX2C - port map(A => \Address[11]\, B => data_address(11), S => - time_select, Y => N_1028); - - un1_state_4_m57_m6_0_a2_7_0 : NOR2B - port map(A => \data_counter[21]_net_1\, B => - \data_counter[14]_net_1\, Y => m57_m6_0_a2_7_0); - - un1_hresetn_inv_2_m50 : XNOR2 - port map(A => N_50, B => \grant_counter[18]_net_1\, Y => - \un1_hresetn_inv_2_i[13]\); - - \DMAIn.Address_RNO[13]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(13), Y - => N_45_0); - - un1_state_4_m25 : NOR2B - port map(A => N_25_0_0, B => \data_counter[10]_net_1\, Y - => N_26_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_hresetn_inv_2_m55_m6_0_a2_4 : NOR2B - port map(A => m55_m6_0_a2_4_4, B => m55_m6_0_a2_4_3, Y => - m55_m6_0_a2_4); - - un1_state_4_m59_0 : NOR3C - port map(A => m28_m6_0_a2_4, B => m57_m6_0_a2_7_5, C => - \data_counter[22]_net_1\, Y => m59_0); - - \DMAIn.Address_RNIP8BS[0]\ : MX2 - port map(A => \Address[0]\, B => data_address(0), S => - time_select_0, Y => Address_RNIP8BS(0)); - - \state_RNI9ALP[0]\ : OR2 - port map(A => N_518_1, B => N_516_2, Y => N_516); - - \DMAIn.Address_RNO[7]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(7), Y - => N_27); - - \data_counter_RNO_2[0]\ : NOR2B - port map(A => \un1_state_4_i[31]\, B => - \data_counter_8_i_0_tz[0]\, Y => \data_counter_8_i_0[0]\); - - \data_counter_RNO[16]\ : XA1B - port map(A => \data_counter[16]_net_1\, B => N_46, C => - N_198_0, Y => \data_counter_8[16]\); - - un1_hresetn_inv_2_m68 : XNOR2 - port map(A => N_68_0, B => \grant_counter[27]_net_1\, Y => - \un1_hresetn_inv_2_i[4]\); - - \data_counter_RNO[29]\ : XA1B - port map(A => \data_counter[29]_net_1\, B => N_72, C => - N_198, Y => \data_counter_8[29]\); - - un1_hresetn_inv_2_m16 : OR3C - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => \grant_counter[1]_net_1\, Y => - N_17_0); - - un1_hresetn_inv_2_m56 : XNOR2 - port map(A => N_56, B => \grant_counter[21]_net_1\, Y => - \un1_hresetn_inv_2_i[10]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_2 : NOR2B - port map(A => \grant_counter[21]_net_1\, B => - \grant_counter[22]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_2); - - \state_RNIQDFIVJ[3]\ : OR3A - port map(A => \state[3]_net_1\, B => N_235, C => N_348, Y - => N_343); - - \grant_counter_RNI923D[7]\ : NOR2 - port map(A => \grant_counter[7]_net_1\, B => - \grant_counter[20]_net_1\, Y => - \state_ns_i_a2_0_i_o2_3[3]\); - - \DMAIn.Address[8]\ : DFN1E1C0 - port map(D => N_29, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[8]\); - - \state_RNO[4]\ : AO1 - port map(A => \state[4]_net_1\, B => Grant, C => Request_5, - Y => N_84); - - \grant_counter_RNIQF6E_0[15]\ : OR2B - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[13]_net_1\, Y => - \grant_counter_0_i_6_tz_1[17]\); - - \DMAIn.Address_RNO[19]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(19), Y - => N_57); - - \DMAIn.Address[0]\ : DFN1E1C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[0]\); - - un1_hresetn_inv_2_m25 : OR2B - port map(A => N_25_0, B => \grant_counter[10]_net_1\, Y => - N_26_0_0); - - un1_hresetn_inv_2_m26_m1_e : NOR3 - port map(A => m26tt_N_7, B => Grant_1_0, C => - nhmaster_1_i(0), Y => \m26_m1_e\); - - un1_hresetn_inv_2_m23_m6_0_a2 : OR2B - port map(A => un1_hresetn_inv_i_0, B => m23_m6_0_a2_4, Y - => N_24_0); - - \state_RNI3LQC[0]\ : OR2 - port map(A => \state[3]_net_1\, B => \state[0]_net_1\, Y - => N_516_2); - - \state_RNO[2]\ : AO1C - port map(A => N_346, B => N_246, C => N_522, Y => N_151); - - \grant_counter_RNO[17]\ : NOR3 - port map(A => \grant_counter_RNO_0[17]_net_1\, B => - \grant_counter_0_i_0_0[17]\, C => - \grant_counter_RNO_2[17]_net_1\, Y => N_115); - - \state_RNIBSIG1J[3]\ : NOR2A - port map(A => un1_hresetn_inv_i_0_a2_0, B => Grant, Y => - un1_hresetn_inv_i_0); - - \grant_counter_RNO_1[17]\ : OR2A - port map(A => N_202_0, B => \grant_counter_0_i_5[17]\, Y - => \grant_counter_0_i_0_0[17]\); - - un1_state_4_m71 : NOR2 - port map(A => m71_0, B => N_68, Y => N_72); - - \grant_counter[10]\ : DFN1 - port map(D => N_101, CLK => lclk_c, Q => - \grant_counter[10]_net_1\); - - \DMAIn.Address_RNIVO6L[23]\ : MX2C - port map(A => \Address[23]\, B => data_address(23), S => - time_select, Y => N_1040); - - \data_counter_RNI9BF9[16]\ : NOR2 - port map(A => \data_counter[16]_net_1\, B => - \data_counter[19]_net_1\, Y => un1_state_5_i_o2_12); - - \state_RNI6TKGVI[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => Grant, Y => N_200); - - \data_counter_RNO[28]\ : XA1C - port map(A => \data_counter[28]_net_1\, B => N_70, C => - N_198, Y => \data_counter_8[28]\); - - \grant_counter[24]\ : DFN1 - port map(D => N_129, CLK => lclk_c, Q => - \grant_counter[24]_net_1\); - - \data_counter_RNO[15]\ : NOR2 - port map(A => N_45, B => N_198_0, Y => \data_counter_8[15]\); - - \grant_counter_RNO_3[20]\ : NOR3C - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[19]_net_1\, C => \grant_counter[14]_net_1\, - Y => grant_counter_0_i_20_b0_0_o2_2); - - un1_state_4_m65 : NOR2B - port map(A => N_64, B => \data_counter[25]_net_1\, Y => - N_66_0); - - \grant_counter[16]\ : DFN1 - port map(D => N_113, CLK => lclk_c, Q => - \grant_counter[16]_net_1\); - - \DMAIn.Address[15]\ : DFN1E1C0 - port map(D => N_49, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[15]\); - - un1_state_4_m35 : AX1E - port map(A => \data_counter[5]_net_1\, B => N_20_0, C => - \data_counter[6]_net_1\, Y => N_36_0); - - \grant_counter[19]\ : DFN1 - port map(D => N_119, CLK => lclk_c, Q => - \grant_counter[19]_net_1\); - - \DMAIn.Store_RNIVHK6\ : MX2 - port map(A => Store, B => Store_0, S => time_select, Y => - N_1082); - - un1_hresetn_inv_2_m32 : AX1C - port map(A => rstn, B => m17_m2_e_3, C => - \grant_counter[3]_net_1\, Y => N_33_0_i_0); - - un1_hresetn_inv_2_m27 : NOR3C - port map(A => rstn, B => m26_m6_e_3, C => - \grant_counter[12]_net_1\, Y => N_28_0); - - un1_state_4_m28_m6_0_a2_4_4 : NOR3C - port map(A => \data_counter[5]_net_1\, B => - \data_counter[13]_net_1\, C => \data_counter[11]_net_1\, - Y => m28_m6_0_a2_4_4); - - \state_RNIJH0E9[3]\ : AO1C - port map(A => N_235, B => \state[3]_net_1\, C => N_242, Y - => N_154); - - \data_counter[18]\ : DFN1C0 - port map(D => \data_counter_8[18]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[18]_net_1\); - - un1_state_4_m27 : OR3C - port map(A => \data_counter[11]_net_1\, B => - \data_counter[12]_net_1\, C => N_26_0, Y => N_28_0_0); - - un1_hresetn_inv_2_m75_0 : AX1A - port map(A => rstoutl_RNIGJKSJO, B => m75_m6_0_a2, C => - \grant_counter[31]_net_1\, Y => \un1_hresetn_inv_2_i[0]\); - - \DMAIn.Address_RNO[3]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(3), Y - => N_19); - - \DMAIn.Address_RNIIQ9P[13]\ : MX2C - port map(A => \Address[13]\, B => data_address(13), S => - time_select, Y => N_1030); - - \data_counter_RNO[24]\ : XA1B - port map(A => \data_counter[24]_net_1\, B => N_62_0, C => - N_198, Y => \data_counter_8[24]\); - - un1_state_4_m43_0 : NOR2B - port map(A => \data_counter[14]_net_1\, B => m28_m6_0_a2_4, - Y => m43_0); - - \grant_counter_RNO_7[17]\ : NOR2A - port map(A => \grant_counter_0_i_6_tz_1_0[17]\, B => - \grant_counter_0_i_6_tz_1[17]\, Y => - \grant_counter_0_i_6_tz_3[17]\); - - \data_counter[14]\ : DFN1C0 - port map(D => \data_counter_8[14]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[14]_net_1\); - - \grant_counter_RNO[23]\ : XA1 - port map(A => \grant_counter[23]_net_1\, B => N_60, C => - N_202, Y => N_127); - - \DMAIn.Address_RNO[21]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(21), Y - => N_61_0); - - un1_hresetn_inv_2_m64 : AX1E - port map(A => un1_hresetn_inv_i_0_a2_0, B => m63_m6_0_a2_6, - C => \grant_counter[25]_net_1\, Y => - \un1_hresetn_inv_2_i[6]\); - - \grant_counter_RNO_0[20]\ : AX1E - port map(A => N_28_0, B => grant_counter_0_i_20_b0_0_o2_4, - C => \grant_counter[20]_net_1\, Y => - grant_counter_0_i_20_N_14_i); - - \DMAIn.Address[23]\ : DFN1E1C0 - port map(D => N_65, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[23]\); - - \grant_counter[23]\ : DFN1 - port map(D => N_127, CLK => lclk_c, Q => - \grant_counter[23]_net_1\); - - \data_counter[17]\ : DFN1C0 - port map(D => \data_counter_8[17]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[17]_net_1\); - - un1_state_4_m19_a0_6_4 : NOR3B - port map(A => \data_counter[3]_net_1\, B => m19_a1_6_1, C - => \state[0]_net_1\, Y => m19_a0_6_4); - - \data_counter_RNI31IJ[31]\ : NOR3A - port map(A => un1_state_5_i_o2_1, B => - \data_counter[13]_net_1\, C => \data_counter[31]_net_1\, - Y => un1_state_5_i_o2_16); - - un1_state_2_i_a2_m8_i_a4 : OR2B - port map(A => un1_state_2_i_a2_N_3_i_0_li, B => l1_0_m(1), - Y => \un1_state_2_i_a2_m8_i_a4\); - - \grant_counter_RNO_2[20]\ : NOR2B - port map(A => \grant_counter[17]_net_1\, B => - \grant_counter[18]_net_1\, Y => - grant_counter_0_i_20_b0_0_o2_1); - - \data_counter[31]\ : DFN1C0 - port map(D => \data_counter_8[31]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[31]_net_1\); - - un1_hresetn_inv_2_m17_m2_e_3 : NOR2A - port map(A => m17_m2_e_2, B => Grant, Y => m17_m2_e_3); - - un1_hresetn_inv_2_m26tt_m3_i_a4 : NOR2B - port map(A => nhmaster_1_iv_0(1), B => bco_msb_1_m(1), Y - => m26tt_N_7); - - \grant_counter_RNINUT88J[1]\ : OR2A - port map(A => un1_hresetn_inv_i_0, B => N_246, Y => N_354); - - un1_state_4_m29 : XNOR2 - port map(A => \data_counter[0]_net_1\, B => N_8, Y => - \un1_state_4_i[31]\); - - \DMAIn.Address_RNIEMR31[5]\ : MX2C - port map(A => \Address[5]\, B => data_address(5), S => - time_select, Y => N_1022); - - \data_counter_RNO_0[0]\ : OR2 - port map(A => \state[0]_net_1\, B => N_235, Y => - \data_counter_8_i_a4_2_0[0]\); - - \grant_counter[31]\ : DFN1 - port map(D => N_143, CLK => lclk_c, Q => - \grant_counter[31]_net_1\); - - \grant_counter[15]\ : DFN1 - port map(D => N_111, CLK => lclk_c, Q => - \grant_counter[15]_net_1\); - - \DMAIn.Address_RNO[1]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(1), Y - => N_15); - - un1_hresetn_inv_2_ADD_32x32_fast_I174_Y_0 : AX1E - port map(A => \grant_counter[13]_net_1\, B => N_28_0, C => - \grant_counter[14]_net_1\, Y => - \un1_hresetn_inv_2_i_0[17]\); - - \grant_counter[6]\ : DFN1 - port map(D => N_93, CLK => lclk_c, Q => - \grant_counter[6]_net_1\); - - \DMAIn.Address_RNO[22]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(22), Y - => N_63); - - \data_counter[19]\ : DFN1C0 - port map(D => \data_counter_8[19]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[19]_net_1\); - - \DMAIn.Address[16]\ : DFN1E1C0 - port map(D => N_51, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[16]\); - - un1_state_4_m60 : AX1E - port map(A => N_20_0, B => m59_0, C => - \data_counter[23]_net_1\, Y => N_61); - - \DMAIn.Address_RNI79VP[15]\ : MX2C - port map(A => \Address[15]\, B => data_address(15), S => - time_select_0, Y => N_1032); - - \grant_counter[8]\ : DFN1 - port map(D => N_97, CLK => lclk_c, Q => - \grant_counter[8]_net_1\); - - \state_RNI6R78T9[4]\ : OR3C - port map(A => iosn_0(93), B => un1_state_2_i_a2_m8_i_2, C - => \un1_state_2_i_a2_m8_i_a4\, Y => - \state_RNI6R78T9[4]_net_1\); - - un1_state_4_m30 : AX1E - port map(A => N_8, B => \data_counter[0]_net_1\, C => - \data_counter[1]_net_1\, Y => \un1_state_4_i[30]\); - - \DMAIn.Address_RNO[24]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(24), Y - => N_67); - - \data_counter_RNO[3]\ : AOI1 - port map(A => \un1_state_4_i[28]\, B => N_343, C => N_509, - Y => N_192); - - \DMAIn.Address_RNIEJMR[7]\ : MX2C - port map(A => \Address[7]\, B => data_address(7), S => - time_select, Y => N_1024); - - \DMAIn.Address_RNO[25]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(25), Y - => N_69); - - \data_counter_RNO[5]\ : XA1B - port map(A => \data_counter[5]_net_1\, B => N_20_0, C => - N_198_0, Y => \data_counter_8[5]\); - - un1_state_4_m67 : OR2B - port map(A => N_66_0, B => \data_counter[26]_net_1\, Y => - N_68); - - \grant_counter_RNO[13]\ : NOR2A - port map(A => N_202_0, B => \un1_hresetn_inv_2_i[18]\, Y - => N_107); - - \DMAIn.Address_RNIJ4SP[20]\ : MX2C - port map(A => \Address[20]\, B => data_address(20), S => - time_select_0, Y => Address_RNIJ4SP(20)); - - un1_hresetn_inv_2_m26_m3_e : OR3C - port map(A => \m26_m1_e\, B => m23_m6_0_a2_4, C => - un1_hresetn_inv_i_0_a2_0, Y => m26_m3_e); - - un1_hresetn_inv_2_m42 : XNOR2 - port map(A => N_28_0, B => \grant_counter[13]_net_1\, Y => - \un1_hresetn_inv_2_i[18]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_10 : NOR3B - port map(A => ADD_32x32_fast_I129_un1_Y_2, B => - ADD_32x32_fast_I129_un1_Y_1, C => m49_m6_0_a2_0, Y => - ADD_32x32_fast_I129_un1_Y_10); - - un1_hresetn_inv_2_m49_m6_0_a2_5 : NOR3B - port map(A => \grant_counter_0_i_6_tz_1_0[17]\, B => - m49_m6_0_a2_4, C => m49_m6_0_a2_2, Y => m49_m6_0_a2_5); - - \state_RNIRHSB[0]\ : OR2B - port map(A => \state[0]_net_1\, B => Ready, Y => N_346); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO[3]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[3]_net_1\); - - \DMAIn.Address_RNIH0DT[24]\ : MX2C - port map(A => \Address[24]\, B => data_address(24), S => - time_select, Y => N_1041); - - \data_counter_RNINO5E2[24]\ : NOR3C - port map(A => un1_state_5_i_o2_21, B => un1_state_5_i_o2_20, - C => un1_state_5_i_o2_27, Y => un1_state_5_i_o2_29); - - un1_hresetn_inv_2_m55_m6_0_a2_4_3 : NOR3B - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[18]_net_1\, C => - \grant_counter_0_i_a0_2[17]\, Y => m55_m6_0_a2_4_3); - - \data_counter_RNIAQUI[29]\ : NOR3A - port map(A => un1_state_5_i_o2_11, B => - \data_counter[11]_net_1\, C => \data_counter[29]_net_1\, - Y => un1_state_5_i_o2_21); - - \grant_counter_RNIANBS[11]\ : NOR3A - port map(A => \state_ns_i_a2_0_i_o2_15[3]\, B => - \grant_counter[13]_net_1\, C => \grant_counter[11]_net_1\, - Y => \state_ns_i_a2_0_i_o2_23[3]\); - - \data_counter[7]\ : DFN1C0 - port map(D => \data_counter_8[7]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[7]_net_1\); - - un1_hresetn_inv_2_m75_m6_0_a2_2 : NOR3B - port map(A => m75_m6_0_a2_0, B => \grant_counter[9]_net_1\, - C => m75_m6_0_a2_1, Y => m75_m6_0_a2_2); - - \grant_counter_RNO[21]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[10]\, Y => - N_123); - - \data_counter[5]\ : DFN1C0 - port map(D => \data_counter_8[5]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[5]_net_1\); - - un1_state_4_m28_m6_0_a2_4 : NOR2B - port map(A => m28_m6_0_a2_4_6, B => m28_m6_0_a2_4_5, Y => - m28_m6_0_a2_4); - - un1_state_4_m57_m6_0_a2_7_5 : NOR3B - port map(A => m57_m6_0_a2_7_0, B => m57_m6_0_a2_7_4, C => - m57_m6_0_a2_7_1, Y => m57_m6_0_a2_7_5); - - \DMAIn.Request\ : DFN1E1C0 - port map(D => Request_5, CLK => lclk_c, CLR => rstn, E => - N_156, Q => Request); - - \DMAIn.Address_RNO[11]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(11), Y - => N_35); - - \DMAIn.Address_RNO[6]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(6), Y - => N_25); - - \DMAIn.Address[17]\ : DFN1E1C0 - port map(D => N_53, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[17]\); - - \grant_counter_RNO[31]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[0]\, Y => - N_143); - - \DMAIn.Address[22]\ : DFN1E1C0 - port map(D => N_63, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[22]\); - - \data_counter_RNO[30]\ : XA1B - port map(A => \data_counter[30]_net_1\, B => I129_un1_Y_0, - C => N_198, Y => \data_counter_8[30]\); - - \data_counter[9]\ : DFN1C0 - port map(D => \data_counter_8[9]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[9]_net_1\); - - un1_hresetn_inv_2_m67_m6_0_a2_4_4 : NOR3C - port map(A => \grant_counter[23]_net_1\, B => - \grant_counter[25]_net_1\, C => m67_m6_0_a2_4_2, Y => - m67_m6_0_a2_4_4); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_6 : OR2B - port map(A => \grant_counter[17]_net_1\, B => - \grant_counter[16]_net_1\, Y => m49_m6_0_a2_0); - - \grant_counter_RNI6QAR[1]\ : NOR3B - port map(A => \grant_counter[1]_net_1\, B => - \state_ns_i_a2_0_i_o2_11[3]\, C => - \grant_counter[15]_net_1\, Y => - \state_ns_i_a2_0_i_o2_21[3]\); - - un1_state_4_m69 : OR2A - port map(A => \data_counter[27]_net_1\, B => N_68, Y => - N_70); - - un1_hresetn_inv_2_m63_m6_0_a2_1_0 : NOR2A - port map(A => \grant_counter[10]_net_1\, B => m63_m6_0_a2_1, - Y => m63_m6_0_a2_1_0); - - \state_RNI0P0IVI_0[4]\ : OR2B - port map(A => N_200, B => rstn, Y => N_202_0); - - \data_counter[30]\ : DFN1C0 - port map(D => \data_counter_8[30]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[30]_net_1\); - - un1_state_4_m19_a0_6 : OR3B - port map(A => m19_a0_6_3, B => m19_a0_6_4, C => - un1_state_2_i_o2_0, Y => m19_a0_6_i_0); - - un1_hresetn_inv_2_m23_m6_0_a2_4_6 : NOR3C - port map(A => \grant_counter[0]_net_1\, B => - \grant_counter[7]_net_1\, C => m23_m6_0_a2_4_4, Y => - m23_m6_0_a2_4_6); - - \data_counter_RNO[7]\ : XA1B - port map(A => \data_counter[7]_net_1\, B => N_22_0_0, C => - N_198_0, Y => \data_counter_8[7]\); - - \data_counter_RNO[11]\ : XA1B - port map(A => \data_counter[11]_net_1\, B => N_26_0, C => - N_198_0, Y => \data_counter_8[11]\); - - \grant_counter_RNO[2]\ : AO1 - port map(A => N_32_0_i_0, B => N_202_0, C => N_513, Y => - \grant_counter_RNO[2]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_counter_RNO[23]\ : NOR2 - port map(A => N_61, B => N_198, Y => \data_counter_8[23]\); - - un1_state_4_m19_a1_6 : OR3C - port map(A => m19_a1_6_4, B => m19_a1_6_3, C => OKAY, Y => - m19_a1_6_i_0); - - \grant_counter_RNO_3[17]\ : NOR3B - port map(A => \grant_counter_0_i_a0_0[17]\, B => - \grant_counter_0_i_a0_4[17]\, C => - \grant_counter_0_i_a0_2[17]\, Y => - \grant_counter_0_i_a0_5[17]\); - - un1_hresetn_inv_2_m24 : NOR2A - port map(A => \grant_counter[9]_net_1\, B => N_24_0, Y => - N_25_0); - - \grant_counter_RNIRK0C[5]\ : NOR2 - port map(A => \grant_counter[5]_net_1\, B => - \grant_counter[6]_net_1\, Y => - \state_ns_i_a2_0_i_o2_2[3]\); - - \DMAIn.Address_RNO[12]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(12), Y - => N_43); - - \grant_counter_RNO[25]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[6]\, Y => - N_131); - - \state_RNIHVV86J[3]\ : OR2A - port map(A => un1_state_9_i_a4_0, B => Grant, Y => N_526); - - \DMAIn.Address_RNO[14]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(14), Y - => N_47); - - \grant_counter_RNO[11]\ : XA1A - port map(A => \grant_counter[11]_net_1\, B => N_26_0_0, C - => N_202_0, Y => N_103); - - \DMAIn.Address[20]\ : DFN1E1C0 - port map(D => N_59, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[20]\); - - \data_counter_RNIMN781[16]\ : NOR3C - port map(A => un1_state_5_i_o2_13, B => un1_state_5_i_o2_12, - C => un1_state_5_i_o2_23, Y => un1_state_5_i_o2_27); - - un1_state_4_m57_m6_0_a2_7_4 : NOR3C - port map(A => \data_counter[16]_net_1\, B => - \data_counter[15]_net_1\, C => m57_m6_0_a2_7_2, Y => - m57_m6_0_a2_7_4); - - un1_hresetn_inv_2_m23_m6_0_a2_4_4 : NOR3C - port map(A => \grant_counter[2]_net_1\, B => - \grant_counter[8]_net_1\, C => \grant_counter[1]_net_1\, - Y => m23_m6_0_a2_4_4); - - \DMAIn.Address_RNO[15]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(15), Y - => N_49); - - un1_state_4_m28_m6_0_a2_4_5 : NOR3C - port map(A => \data_counter[7]_net_1\, B => - \data_counter[6]_net_1\, C => m28_m6_0_a2_4_2, Y => - m28_m6_0_a2_4_5); - - \state_RNIPJNA8[3]\ : OAI1 - port map(A => N_246, B => un1_state_7_i_a4_0_1, C => N_516, - Y => N_146); - - \state_RNI47NO[3]\ : OR3A - port map(A => Ready, B => \state[3]_net_1\, C => N_518_1, Y - => un1_state_7_i_a4_0_1); - - \data_counter_RNO[20]\ : XA1B - port map(A => \data_counter[20]_net_1\, B => N_54, C => - N_198, Y => \data_counter_8[20]\); - - \DMAIn.Address[21]\ : DFN1E1C0 - port map(D => N_61_0, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[21]\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_13 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_8_0, B => - ADD_32x32_fast_I129_un1_Y_7, C => - ADD_32x32_fast_I129_un1_Y_12_0, Y => - ADD_32x32_fast_I129_un1_Y_13); - - \grant_counter[5]\ : DFN1 - port map(D => N_91, CLK => lclk_c, Q => - \grant_counter[5]_net_1\); - - \DMAIn.Address_RNO[9]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(9), Y - => N_31); - - \DMAIn.Address[18]\ : DFN1E1C0 - port map(D => N_55, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[18]\); - - \data_counter[25]\ : DFN1C0 - port map(D => \data_counter_8[25]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[25]_net_1\); - - \state_RNIEV8MOJ[3]\ : NOR2 - port map(A => \state[3]_net_1\, B => N_348, Y => N_509); - - \grant_counter_RNIC2BO6[1]\ : OR3C - port map(A => \state_ns_i_a2_0_i_o2_27[3]\, B => - \state_ns_i_a2_0_i_o2_26[3]\, C => - \state_ns_i_a2_0_i_o2_28[3]\, Y => N_246); - - \grant_counter[4]\ : DFN1 - port map(D => N_89, CLK => lclk_c, Q => - \grant_counter[4]_net_1\); - - \grant_counter[11]\ : DFN1 - port map(D => N_103, CLK => lclk_c, Q => - \grant_counter[11]_net_1\); - - un1_hresetn_inv_2_m63_m6_0_a2_4 : NOR2B - port map(A => m63_m6_0_a2_3, B => m55_m6_0_a2_4, Y => - m63_m6_0_a2_4); - - \DMAIn.Address[24]\ : DFN1E1C0 - port map(D => N_67, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[24]\); - - \state_RNILNM4J71[3]\ : AO1A - port map(A => N_348, B => OKAY, C => N_509, Y => N_8); - - \grant_counter[12]\ : DFN1 - port map(D => N_105, CLK => lclk_c, Q => - \grant_counter[12]_net_1\); - - \DMAIn.Burst_RNO\ : NOR3C - port map(A => N_522, B => Burst, C => N_526, Y => N_194); - - un1_hresetn_inv_2_m67_m6_0_a2 : NOR3B - port map(A => \grant_counter[9]_net_1\, B => m67_m6_0_a2_4, - C => m26_m3_e, Y => N_68_0); - - \state_RNI5BKL1J[3]\ : OR2 - port map(A => N_249, B => N_200, Y => data_fifo_ren); - - \grant_counter_RNIQF6E[15]\ : OR2B - port map(A => \grant_counter[15]_net_1\, B => - \grant_counter[13]_net_1\, Y => - \grant_counter_0_i_a0_2[17]\); - - \grant_counter_RNI7M3D[25]\ : NOR2A - port map(A => \grant_counter[0]_net_1\, B => - \grant_counter[25]_net_1\, Y => - \state_ns_i_a2_0_i_o2_9[3]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_9 : NOR3B - port map(A => ADD_32x32_fast_I129_un1_Y_0, B => - ADD_32x32_fast_I129_un1_Y_5, C => m75_m6_0_a2_1, Y => - ADD_32x32_fast_I129_un1_Y_9); - - \DMAIn.Address[19]\ : DFN1E1C0 - port map(D => N_57, CLK => lclk_c, CLR => rstn, E => - N_154_0, Q => \Address[19]\); - - \data_counter_RNO[1]\ : AOI1 - port map(A => \un1_state_4_i[30]\, B => N_343, C => N_509, - Y => N_188); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_4 : NOR2B - port map(A => \data_counter[14]_net_1\, B => - \data_counter[15]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_4_0); - - \data_counter[4]\ : DFN1C0 - port map(D => \data_counter_8[4]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[4]_net_1\); - - un1_hresetn_inv_2_m49_m6_0_a2 : NOR2A - port map(A => m49_m6_0_a2_5, B => m26_m3_e, Y => N_50); - - \state_RNIJH0E9_0[3]\ : AO1C - port map(A => N_235, B => \state[3]_net_1\, C => N_242, Y - => N_154_0); - - \grant_counter_RNO[15]\ : XA1A - port map(A => \grant_counter[15]_net_1\, B => N_44, C => - N_202, Y => N_111); - - un1_state_4_m71_0 : OR2B - port map(A => \data_counter[28]_net_1\, B => - \data_counter[27]_net_1\, Y => m71_0); - - \grant_counter[7]\ : DFN1 - port map(D => N_95, CLK => lclk_c, Q => - \grant_counter[7]_net_1\); - - \DMAIn.Address_RNO[31]\ : NOR2B - port map(A => \state[5]_net_1\, B => data_address(31), Y - => N_81); - - \data_counter_RNICE6S6[24]\ : OR3C - port map(A => un1_state_5_i_o2_29, B => un1_state_5_i_o2_28, - C => OKAY, Y => N_235); - - \state[2]\ : DFN1C0 - port map(D => N_151, CLK => lclk_c, CLR => rstn, Q => - \state[2]_net_1\); - - un1_hresetn_inv_2_m55_m6_0_a2_4_0 : NOR2B - port map(A => \grant_counter[20]_net_1\, B => - \grant_counter[19]_net_1\, Y => m55_m6_0_a2_4_0); - - un1_hresetn_inv_2_m26_m6_e_1 : NOR2B - port map(A => m26_m6_e_0_0, B => m23_m6_0_a2_4, Y => - m26_m6_e_1); - - send_ko : DFN1E1C0 - port map(D => \state[1]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_146, Q => \data_send_ko\); - - \data_counter_RNO[12]\ : XA1C - port map(A => \data_counter[12]_net_1\, B => N_27_0, C => - N_198_0, Y => \data_counter_8[12]\); - - un1_hresetn_inv_2_m31 : XNOR2 - port map(A => N_17_0, B => \grant_counter[2]_net_1\, Y => - N_32_0_i_0); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_12 : NOR3C - port map(A => ADD_32x32_fast_I129_un1_Y_9, B => - ADD_32x32_fast_I129_un1_Y_8, C => - ADD_32x32_fast_I129_un1_Y_10, Y => - ADD_32x32_fast_I129_un1_Y_12); - - \state_RNIP9B62[3]\ : NOR2A - port map(A => rstn, B => N_241, Y => - un1_hresetn_inv_i_0_a2_0); - - \DMAIn.Store\ : DFN1E1C0 - port map(D => \state[5]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_156, Q => Store); - - \grant_counter_RNO[29]\ : XA1A - port map(A => \grant_counter[29]_net_1\, B => N_72_0, C => - N_202, Y => N_139); - - \DMAIn.Address[3]\ : DFN1E1C0 - port map(D => N_19, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[3]\); - - \state_RNIVDV42_1[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => OKAY, Y => N_249); - - \state_RNIVCOU6[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => N_246, Y => - un1_state_9_i_a4_0); - - \state[1]\ : DFN1C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[1]_net_1\); - - \DMAIn.Address_RNISD461[31]\ : MX2C - port map(A => \Address[31]\, B => data_address(31), S => - time_select_0, Y => N_1048); - - un1_hresetn_inv_2_m30 : AX1C - port map(A => \grant_counter[0]_net_1\, B => - un1_hresetn_inv_i_0, C => \grant_counter[1]_net_1\, Y => - N_31_0_i_0); - - \DMAIn.Burst\ : DFN1P0 - port map(D => N_194, CLK => lclk_c, PRE => rstn, Q => Burst); - - \DMAIn.Address_RNIJJMR[8]\ : MX2C - port map(A => \Address[8]\, B => data_address(8), S => - time_select, Y => N_1025); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_12 : NOR3B - port map(A => ADD_32x32_fast_I129_un1_Y_4_0, B => - ADD_32x32_fast_I129_un1_Y_10_0, C => m57_m6_0_a2_7_1, Y - => ADD_32x32_fast_I129_un1_Y_12_0); - - un1_hresetn_inv_2_m33 : XOR2 - port map(A => N_19_0, B => \grant_counter[4]_net_1\, Y => - \un1_hresetn_inv_2_i_i[27]\); - - un1_hresetn_inv_2_m18 : NOR3C - port map(A => rstn, B => m17_m2_e_3, C => - \grant_counter[3]_net_1\, Y => N_19_0); - - un1_hresetn_inv_2_m58 : AX1E - port map(A => \grant_counter[21]_net_1\, B => N_56, C => - \grant_counter[22]_net_1\, Y => \un1_hresetn_inv_2_i[9]\); - - \data_counter_RNO[9]\ : XA1B - port map(A => \data_counter[9]_net_1\, B => N_24_0_0, C => - N_198_0, Y => \data_counter_8[9]\); - - \grant_counter_RNO_9[17]\ : NOR2B - port map(A => \grant_counter[10]_net_1\, B => - \grant_counter[14]_net_1\, Y => - \grant_counter_0_i_a0_2_0[17]\); - - \grant_counter_RNIV37E[16]\ : NOR2 - port map(A => \grant_counter[16]_net_1\, B => - \grant_counter[17]_net_1\, Y => - \state_ns_i_a2_0_i_o2_11[3]\); - - \grant_counter_RNI5K7E[28]\ : NOR2 - port map(A => \grant_counter[28]_net_1\, B => - \grant_counter[29]_net_1\, Y => - \state_ns_i_a2_0_i_o2_5[3]\); - - \data_counter_RNO[26]\ : XA1B - port map(A => \data_counter[26]_net_1\, B => N_66_0, C => - N_198, Y => \data_counter_8[26]\); - - \state_RNI6LQC[2]\ : OR2 - port map(A => \state[4]_net_1\, B => \state[2]_net_1\, Y - => N_518_1); - - \grant_counter_RNIIC7Q[2]\ : NOR3C - port map(A => \grant_counter[3]_net_1\, B => - \grant_counter[2]_net_1\, C => - \state_ns_i_a2_0_i_o2_7[3]\, Y => - \state_ns_i_a2_0_i_o2_19[3]\); - - un1_hresetn_inv_2_m22 : OR2B - port map(A => N_22_0, B => \grant_counter[7]_net_1\, Y => - N_23_0); - - \DMAIn.Address_RNI5C221[21]\ : MX2C - port map(A => \Address[21]\, B => data_address(21), S => - time_select_0, Y => N_1038); - - \grant_counter_RNIUR6E[23]\ : NOR2 - port map(A => \grant_counter[18]_net_1\, B => - \grant_counter[23]_net_1\, Y => - \state_ns_i_a2_0_i_o2_12[3]\); - - \DMAIn.Address_RNI9JMR[6]\ : MX2C - port map(A => \Address[6]\, B => data_address(6), S => - time_select, Y => N_1023); - - un1_hresetn_inv_2_m63_m6_0_a2_6 : NOR3C - port map(A => m63_m6_0_a2_4, B => m23_m6_0_a2_4, C => - \m26_m1_e\, Y => m63_m6_0_a2_6); - - \state_RNO[3]\ : AO1A - port map(A => N_241, B => N_235, C => N_200, Y => - \state_RNO[3]_net_1\); - - \state_RNO[0]\ : AO1C - port map(A => N_235, B => \state[3]_net_1\, C => N_523, Y - => \state_RNO[0]_net_1\); - - \grant_counter_RNIKN5E_0[12]\ : NOR2 - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[10]_net_1\, Y => - \state_ns_i_a2_0_i_o2_15[3]\); - - \grant_counter[14]\ : DFN1 - port map(D => N_109, CLK => lclk_c, Q => - \grant_counter[14]_net_1\); - - \DMAIn.Address[4]\ : DFN1E1C0 - port map(D => N_21, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[4]\); - - \data_counter_RNIB2VI[18]\ : NOR3A - port map(A => un1_state_5_i_o2_7, B => - \data_counter[21]_net_1\, C => \data_counter[18]_net_1\, - Y => un1_state_5_i_o2_19); - - \grant_counter_RNO_1[20]\ : NOR3B - port map(A => grant_counter_0_i_20_b0_0_o2_1, B => - grant_counter_0_i_20_b0_0_o2_2, C => - \grant_counter_0_i_6_tz_1[17]\, Y => - grant_counter_0_i_20_b0_0_o2_4); - - \grant_counter[2]\ : DFN1 - port map(D => \grant_counter_RNO[2]_net_1\, CLK => lclk_c, - Q => \grant_counter[2]_net_1\); - - \data_counter[26]\ : DFN1C0 - port map(D => \data_counter_8[26]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[26]_net_1\); - - \data_counter[23]\ : DFN1C0 - port map(D => \data_counter_8[23]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[23]_net_1\); - - un1_state_4_m19_0_m8_i : OR3C - port map(A => m19_0_N_15_i_0_li, B => m19_0_m8_i_1, C => - \un1_state_2_i_a2_m8_i_a4\, Y => m19_0_m8_i); - - un1_state_4_m16 : NOR3C - port map(A => N_8, B => \data_counter[0]_net_1\, C => - \data_counter[1]_net_1\, Y => N_17_0_0); - - un1_hresetn_inv_2_m55_m6_0_a2 : NOR3C - port map(A => rstn, B => m26_m6_e_3, C => m55_m6_0_a2_4, Y - => N_56); - - \DMAIn.Address[25]\ : DFN1E1C0 - port map(D => N_69, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[25]\); - - \grant_counter_RNO_4[17]\ : AOI1 - port map(A => \grant_counter_0_i_6_tz_3[17]\, B => - \grant_counter_0_i_6_tz_2[17]\, C => - \grant_counter[17]_net_1\, Y => \grant_counter_0_i_5[17]\); - - \grant_counter_RNI95AD1[5]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_3[3]\, B => - \state_ns_i_a2_0_i_o2_2[3]\, C => - \state_ns_i_a2_0_i_o2_16[3]\, Y => - \state_ns_i_a2_0_i_o2_24[3]\); - - un1_state_4_m45 : NOR3C - port map(A => N_20_0, B => m43_0, C => - \data_counter[15]_net_1\, Y => N_46); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_8 : NOR3C - port map(A => \data_counter[26]_net_1\, B => - \data_counter[25]_net_1\, C => - ADD_32x32_fast_I129_un1_Y_3, Y => - ADD_32x32_fast_I129_un1_Y_8_0); - - \state_RNI7ALP[4]\ : OR3 - port map(A => \state[0]_net_1\, B => \state[4]_net_1\, C - => un1_state_2_i_o2_0, Y => \state_RNI7ALP[4]_net_1\); - - \grant_counter_RNO[19]\ : NOR2A - port map(A => N_202, B => \un1_hresetn_inv_2_i[12]\, Y => - N_119); - - \DMAIn.Address_RNO[2]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(2), Y - => N_17); - - \data_counter_RNO[17]\ : XA1B - port map(A => \data_counter[17]_net_1\, B => N_48, C => - N_198_0, Y => \data_counter_8[17]\); - - un1_state_4_m24 : NOR2B - port map(A => N_24_0_0, B => \data_counter[9]_net_1\, Y => - N_25_0_0); - - un1_hresetn_inv_2_m17_m2_e_0 : NOR2B - port map(A => \grant_counter[2]_net_1\, B => - \grant_counter[0]_net_1\, Y => m17_m2_e_0); - - un1_hresetn_inv_2_m67_m6_0_a2_4_3 : NOR3B - port map(A => \grant_counter[24]_net_1\, B => - \grant_counter[26]_net_1\, C => m63_m6_0_a2_1, Y => - m67_m6_0_a2_4_3); - - un1_hresetn_inv_2_m45_m6_0_a2_2 : NOR3C - port map(A => \grant_counter[13]_net_1\, B => - \grant_counter[9]_net_1\, C => \grant_counter[14]_net_1\, - Y => m45_m6_0_a2_2); - - \data_counter_RNO[25]\ : XA1B - port map(A => \data_counter[25]_net_1\, B => N_64, C => - N_198, Y => \data_counter_8[25]\); - - \data_counter[21]\ : DFN1C0 - port map(D => \data_counter_8[21]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[21]_net_1\); - - un1_hresetn_inv_2_m41 : AX1E - port map(A => rstn, B => m26_m6_e_3, C => - \grant_counter[12]_net_1\, Y => \un1_hresetn_inv_2_i[19]\); - - \DMAIn.Address_RNO[4]\ : NOR2B - port map(A => \state_0[5]_net_1\, B => data_address(4), Y - => N_21); - - \grant_counter_RNO[7]\ : XA1 - port map(A => \grant_counter[7]_net_1\, B => N_22_0, C => - N_202_0, Y => N_95); - - \DMAIn.Lock\ : DFN1E1C0 - port map(D => data_send, CLK => lclk_c, CLR => rstn, E => - \state[5]_net_1\, Q => Lock); - - \data_counter_RNO_3[0]\ : AO1 - port map(A => \state[3]_net_1\, B => N_235, C => - \state[0]_net_1\, Y => \data_counter_8_i_0_tz[0]\); - - un1_hresetn_inv_2_m63_m6_0_a2_0 : NOR2B - port map(A => \grant_counter[24]_net_1\, B => - \grant_counter[23]_net_1\, Y => m63_m6_0_a2_0); - - \state_RNI5OCK8J[3]\ : OR2B - port map(A => N_526, B => N_242, Y => N_156); - - \grant_counter[3]\ : DFN1 - port map(D => \grant_counter_RNO[3]_net_1\, CLK => lclk_c, - Q => \grant_counter[3]_net_1\); - - \grant_counter_RNO_0[17]\ : NOR3B - port map(A => \grant_counter[9]_net_1\, B => - \grant_counter_0_i_a0_5[17]\, C => m26_m3_e, Y => - \grant_counter_RNO_0[17]_net_1\); - - \grant_counter_RNI40MT1[8]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_13[3]\, B => - \state_ns_i_a2_0_i_o2_12[3]\, C => - \state_ns_i_a2_0_i_o2_23[3]\, Y => - \state_ns_i_a2_0_i_o2_27[3]\); - - \grant_counter[13]\ : DFN1 - port map(D => N_107, CLK => lclk_c, Q => - \grant_counter[13]_net_1\); - - \grant_counter[27]\ : DFN1 - port map(D => N_135, CLK => lclk_c, Q => - \grant_counter[27]_net_1\); - - un1_hresetn_inv_2_m43 : OR3C - port map(A => \grant_counter[13]_net_1\, B => N_28_0, C => - \grant_counter[14]_net_1\, Y => N_44); - - \data_counter_RNI3BF9[12]\ : NOR2 - port map(A => \data_counter[12]_net_1\, B => - \data_counter[17]_net_1\, Y => un1_state_5_i_o2_5); - - un1_state_4_m57_m6_0_a2 : OR3C - port map(A => m28_m6_0_a2_4, B => m57_m6_0_a2_7_5, C => - N_20_0, Y => N_58); - - \data_counter_RNI5JF9[22]\ : NOR2 - port map(A => \data_counter[22]_net_1\, B => - \data_counter[23]_net_1\, Y => un1_state_5_i_o2_7); - - \data_counter_RNIEJF9[26]\ : NOR2 - port map(A => \data_counter[26]_net_1\, B => - \data_counter[28]_net_1\, Y => un1_state_5_i_o2_9); - - \data_counter_RNI7JF9[20]\ : NOR2 - port map(A => \data_counter[20]_net_1\, B => - \data_counter[27]_net_1\, Y => un1_state_5_i_o2_13); - - \DMAIn.Address_RNI8D721[19]\ : MX2C - port map(A => \Address[19]\, B => data_address(19), S => - time_select_0, Y => N_1036); - - un1_hresetn_inv_2_m75_m6_0_a2 : NOR3B - port map(A => m75_m6_0_a2_3, B => m67_m6_0_a2_4, C => N_241, - Y => m75_m6_0_a2); - - \data_counter_RNIQ9BL[6]\ : NOR3A - port map(A => un1_state_5_i_o2_3, B => - \data_counter[6]_net_1\, C => \data_counter[5]_net_1\, Y - => un1_state_5_i_o2_17); - - \DMAIn.Address_RNIL46L[12]\ : MX2C - port map(A => \Address[12]\, B => data_address(12), S => - time_select, Y => N_1029); - - \state_RNITA375[4]\ : OR2A - port map(A => m19_0_N_15_i_0_li, B => \state[4]_net_1\, Y - => \state_RNITA375[4]_net_1\); - - \state_RNIRKRFOJ[4]\ : MX2 - port map(A => nhmaster_1_i(0), B => - \state_RNI7ALP[4]_net_1\, S => \state_RNI6R78T9[4]_net_1\, - Y => N_348); - - \state_RNIRKTDJQ1[5]\ : MX2C - port map(A => \state[5]_net_1\, B => \un1_state_4_i[31]\, S - => N_243_i, Y => N_508); - - \grant_counter_RNI1A043[2]\ : NOR3C - port map(A => \state_ns_i_a2_0_i_o2_19[3]\, B => - \state_ns_i_a2_0_i_o2_18[3]\, C => - \state_ns_i_a2_0_i_o2_24[3]\, Y => - \state_ns_i_a2_0_i_o2_28[3]\); - - \grant_counter[28]\ : DFN1 - port map(D => N_137, CLK => lclk_c, Q => - \grant_counter[28]_net_1\); - - un1_hresetn_inv_2_m46 : AX1E - port map(A => un1_hresetn_inv_i_0_a2_0, B => m45_m6_0_a2_6, - C => \grant_counter[16]_net_1\, Y => - \un1_hresetn_inv_2_i[15]\); - - \data_counter_RNIUP2A[10]\ : NOR2 - port map(A => \data_counter[9]_net_1\, B => - \data_counter[10]_net_1\, Y => un1_state_5_i_o2_4); - - un1_hresetn_inv_2_m63_m6_0_a2_3 : NOR3B - port map(A => m63_m6_0_a2_0, B => m63_m6_0_a2_1_0, C => - m26_m6_e_0, Y => m63_m6_0_a2_3); - - \DMAIn.Address[26]\ : DFN1E1C0 - port map(D => N_71, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[26]\); - - \grant_counter_RNIKN5E[12]\ : NOR2B - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[10]_net_1\, Y => - \grant_counter_0_i_6_tz_1_0[17]\); - - un1_hresetn_inv_2_ADD_32x32_fast_I129_un1_Y_0 : NOR2B - port map(A => \grant_counter[20]_net_1\, B => - \grant_counter[26]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_0); - - \data_counter_RNO[0]\ : OA1B - port map(A => N_508, B => \data_counter_8_i_a4_2_0[0]\, C - => \data_counter_8_i_0_0[0]\, Y => N_186); - - un1_hresetn_inv_2_m61 : OR2B - port map(A => N_60, B => \grant_counter[23]_net_1\, Y => - N_62); - - \grant_counter_RNO_6[17]\ : NOR3C - port map(A => \grant_counter[12]_net_1\, B => - \grant_counter[11]_net_1\, C => - \grant_counter_0_i_a0_2_0[17]\, Y => - \grant_counter_0_i_a0_4[17]\); - - un1_hresetn_inv_2_m26_m6_e_0 : OR2B - port map(A => \grant_counter[11]_net_1\, B => - \grant_counter[9]_net_1\, Y => m26_m6_e_0); - - \state_RNIVDV42[3]\ : OR2B - port map(A => \state[3]_net_1\, B => Fault, Y => N_241); - - \grant_counter_RNO[0]\ : OR3C - port map(A => N_30_0, B => N_202_0, C => N_354, Y => - \grant_counter_RNO[0]_net_1\); - - \data_counter_RNIN6VI[24]\ : NOR3A - port map(A => un1_state_5_i_o2_9, B => - \data_counter[25]_net_1\, C => \data_counter[24]_net_1\, - Y => un1_state_5_i_o2_20); - - \data_counter[6]\ : DFN1C0 - port map(D => \data_counter_8[6]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[6]_net_1\); - - \data_counter[15]\ : DFN1C0 - port map(D => \data_counter_8[15]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[15]_net_1\); - - un1_state_4_ADD_32x32_fast_I129_un1_Y_3 : NOR2B - port map(A => \data_counter[28]_net_1\, B => - \data_counter[29]_net_1\, Y => - ADD_32x32_fast_I129_un1_Y_3); - - un1_hresetn_inv_2_m29 : XNOR2 - port map(A => un1_hresetn_inv_i_0, B => - \grant_counter[0]_net_1\, Y => N_30_0); - - un1_state_4_m47 : NOR2B - port map(A => N_46, B => \data_counter[16]_net_1\, Y => - N_48); - - un1_hresetn_inv_2_m67_m6_0_a2_4 : NOR3C - port map(A => m67_m6_0_a2_4_4, B => m67_m6_0_a2_4_3, C => - m55_m6_0_a2_4, Y => m67_m6_0_a2_4); - - un1_hresetn_inv_2_m45_m6_0_a2_4 : NOR3B - port map(A => \grant_counter_0_i_6_tz_1_0[17]\, B => - m45_m6_0_a2_2, C => m49_m6_0_a2_2, Y => m45_m6_0_a2_4); - - \DMAIn.Address_RNIE9CS[3]\ : MX2C - port map(A => \Address[3]\, B => data_address(3), S => - time_select_0, Y => N_1020); - - \data_counter_RNO[19]\ : XA1C - port map(A => \data_counter[19]_net_1\, B => N_52, C => - N_198, Y => \data_counter_8[19]\); - - \grant_counter_RNO[8]\ : XA1A - port map(A => \grant_counter[8]_net_1\, B => N_23_0, C => - N_202_0, Y => N_97); - - \data_counter[20]\ : DFN1C0 - port map(D => \data_counter_8[20]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[20]_net_1\); - - \data_counter[22]\ : DFN1C0 - port map(D => \data_counter_8[22]\, CLK => lclk_c, CLR => - rstn, Q => \data_counter[22]_net_1\); - - un1_hresetn_inv_2_m45_m6_0_a2_6 : NOR3C - port map(A => m23_m6_0_a2_4, B => m45_m6_0_a2_4, C => - \m26_m1_e\, Y => m45_m6_0_a2_6); - - \DMAIn.Address[27]\ : DFN1E1C0 - port map(D => N_73, CLK => lclk_c, CLR => rstn, E => N_154, - Q => \Address[27]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(1 to 1); - status_full : out std_logic_vector(1 to 1); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - update_and_sel_5 : in std_logic_vector(3 downto 2); - sel_data_0 : in std_logic_vector(1 to 1); - addr_data_f1 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(1 to 1); - addr_data_vector_69 : in std_logic; - addr_data_vector_95 : in std_logic; - addr_data_vector_94 : in std_logic; - addr_data_vector_93 : in std_logic; - addr_data_vector_91 : in std_logic; - addr_data_vector_89 : in std_logic; - addr_data_vector_88 : in std_logic; - addr_data_vector_85 : in std_logic; - addr_data_vector_68 : in std_logic; - addr_data_vector_67 : in std_logic; - addr_data_vector_66 : in std_logic; - addr_data_vector_65 : in std_logic; - addr_data_vector_74 : in std_logic; - addr_data_vector_72 : in std_logic; - addr_data_vector_71 : in std_logic; - addr_data_vector_70 : in std_logic; - addr_data_vector_82 : in std_logic; - addr_data_vector_78 : in std_logic; - addr_data_vector_87 : in std_logic; - addr_data_vector_84 : in std_logic; - addr_data_vector_64 : in std_logic; - addr_data_vector_80 : in std_logic; - addr_data_vector_76 : in std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_13 : out std_logic; - addr_data_vector_11 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_17 : out std_logic; - addr_data_vector_19 : out std_logic; - addr_data_vector_22 : out std_logic; - N_1358 : out std_logic; - N_984 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_980 : out std_logic; - N_978 : out std_logic; - N_977 : out std_logic; - N_974 : out std_logic; - N_1371 : out std_logic; - N_1370 : out std_logic; - N_1369 : out std_logic; - N_1368 : out std_logic; - N_1363 : out std_logic; - N_1361 : out std_logic; - N_1360 : out std_logic; - N_1359 : out std_logic; - N_1357 : out std_logic; - N_1353 : out std_logic; - N_976 : out std_logic; - N_973 : out std_logic; - N_1367 : out std_logic; - N_1355 : out std_logic; - N_1351 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, N_118, N_38, \nb_send[1]_net_1\, - \nb_send[0]_net_1\, N_30, \nb_send[3]_net_1\, - \DWACT_FINC_E[0]\, N_7, \nb_send[8]_net_1\, - \DWACT_FINC_E[4]\, m40_m6_0_a2_7, m40_m6_0_a2_2, - m40_m6_0_a2_1, m40_m6_0_a2_6, \addr_data_vector[53]\, - \addr_data_vector[52]\, m40_m6_0_a2_4, m40_m6_0_a2_0, - \addr_data_vector[50]\, \addr_data_vector[48]\, - \addr_data_vector[55]\, \un1_state_12_3_0[4]\, - \update_r[0]_net_1\, \update_r[1]_net_1\, un1_state_5_i_0, - \state[4]_net_1\, \state[3]_net_1\, \state_ns_i_0[3]\, - N_131, \un1_address[6]\, address_0_sqmuxa_i_0, - \addr_data_vector[38]\, N_5_0, \un1_state_12[4]\, - \un1_state_12_2[4]\, N_116, N_129, \state[1]_net_1\, - \state_ns[0]\, N_125, N_124, N_110, \state[2]_net_1\, - state7, un3_update_r, N_15_0_i_0, N_13_0, - \addr_data_vector[39]\, \addr_data_vector[40]\, N_16_0, - N_17_0_i_0, N_19_0, \addr_data_vector[41]\, - \addr_data_vector[42]\, N_20_0_i_0, N_22_0_i_0, - \addr_data_vector[43]\, \addr_data_vector[44]\, N_23_0, - N_25_0, \addr_data_vector[46]\, N_26_0_i_0, - \addr_data_vector[47]\, N_28_0_i_0, N_29_0, N_30_0_i_0, - \addr_data_vector[49]\, N_32_0, \un1_address[19]\, - \addr_data_vector[51]\, N_37_0, N_36_0, \un1_address[23]\, - \addr_data_vector[54]\, N_40_i_0, \addr_data_vector[34]\, - N_42, \addr_data_vector[56]\, N_43, - \addr_data_vector[57]\, N_45, \addr_data_vector[59]\, - N_47, \addr_data_vector[61]\, N_49_i_0, - \addr_data_vector[62]\, \addr_data_vector[63]\, N_50_i_0, - \addr_data_vector[35]\, N_51_i_0, N_69, - \addr_data_vector[36]\, N_52_i_0, \addr_data_vector[37]\, - N_1_i_0, N_54_0_i_0, N_55_0_i_0, \addr_data_vector[45]\, - N_56_0_i_0, \un1_address[18]\, \un1_address[21]\, - \un1_address[22]\, \un1_address[24]\, \un1_address[25]\, - \un1_address[26]\, \addr_data_vector[58]\, - \un1_address[27]\, \un1_address[28]\, - \addr_data_vector[60]\, \un1_address[29]\, - \un1_address[30]\, \nb_send_5[0]\, \nb_send_5[1]\, - \un2_nb_send_next[1]\, \nb_send_5[2]\, - \un2_nb_send_next[2]\, \nb_send_5[3]\, - \un2_nb_send_next[3]\, \nb_send_5[5]\, - \un2_nb_send_next[5]\, \nb_send_5[6]\, - \un2_nb_send_next[6]\, \nb_send_5[7]\, - \un2_nb_send_next[7]\, \nb_send_5[8]\, - \un2_nb_send_next[8]\, \nb_send_5[9]\, - \un2_nb_send_next[9]\, \nb_send_5[10]\, - \un2_nb_send_next[10]\, \address_7[2]\, \address_7[3]\, - \address_7[4]\, \address_7[5]\, \address_7[6]\, - \address_7[7]\, \address_7[8]\, \address_7[9]\, - \address_7[10]\, \address_7[11]\, \address_7[12]\, - \address_7[13]\, \address_7[14]\, \address_7[15]\, - \address_7[16]\, \address_7[17]\, \address_7[18]\, - \state[0]_net_1\, \address_7[19]\, \address_7[21]\, - \address_7[22]\, \address_7[23]\, \address_7[24]\, - \address_7[25]\, \address_7[26]\, \address_7[27]\, - \address_7[28]\, \address_7[29]\, \address_7[30]\, - \address_7[31]\, \addr_data_vector[32]\, \address_7[20]\, - \un1_address[20]\, un1_state_9, \nb_send_5[4]\, - \un2_nb_send_next[4]\, N_127, N_113, \state_ns[2]\, - un1_state_11, \addr_data_vector[33]\, \nb_send[2]_net_1\, - \nb_send[4]_net_1\, \nb_send[5]_net_1\, - \nb_send[6]_net_1\, \nb_send[7]_net_1\, - \nb_send[9]_net_1\, \nb_send[10]_net_1\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_0, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_28 <= \addr_data_vector[60]\; - addr_data_vector_26 <= \addr_data_vector[58]\; - addr_data_vector_13 <= \addr_data_vector[45]\; - addr_data_vector_11 <= \addr_data_vector[43]\; - addr_data_vector_9 <= \addr_data_vector[41]\; - addr_data_vector_15 <= \addr_data_vector[47]\; - addr_data_vector_17 <= \addr_data_vector[49]\; - addr_data_vector_19 <= \addr_data_vector[51]\; - addr_data_vector_22 <= \addr_data_vector[54]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[48]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[42]\); - - \state[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[62]\); - - \address_RNO[26]\ : MX2 - port map(A => \un1_address[26]\, B => addr_data_f1(26), S - => \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_31, Y => N_36); - - un1_address_m61 : XOR2 - port map(A => N_43, B => \addr_data_vector[58]\, Y => - \un1_address[26]\); - - un1_address_m31 : OR3B - port map(A => \addr_data_vector[49]\, B => - \addr_data_vector[50]\, C => N_29_0, Y => N_32_0); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[58]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[52]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => \un2_nb_send_next[5]\, Y => - \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR3A - port map(A => \state[2]_net_1\, B => N_129, C => - status_full_ack(1), Y => N_127); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1 - port map(A => N_69, B => \addr_data_vector[36]\, C => - \addr_data_vector[37]\, Y => N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[44]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), C => N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => \un1_address[29]\, B => addr_data_f1(29), S - => \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - \address_RNI46N9[12]\ : MX2C - port map(A => \addr_data_vector[44]\, B => - addr_data_vector_76, S => sel_data_0(1), Y => N_1351); - - un1_address_m19 : XNOR2 - port map(A => N_19_0, B => \addr_data_vector[43]\, Y => - N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[54]\); - - \address_RNO[23]\ : MX2 - port map(A => \un1_address[23]\, B => addr_data_f1(23), S - => \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[34]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => - \un2_nb_send_next[3]\); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => \un1_address[24]\, B => addr_data_f1(24), S - => \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f1(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_110, Q => status_full_err(1)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - un1_address_m18 : OR3B - port map(A => \addr_data_vector[41]\, B => - \addr_data_vector[42]\, C => N_16_0, Y => N_19_0); - - \nb_send_RNO[1]\ : NOR2B - port map(A => \un2_nb_send_next[1]\, B => state7, Y => - \nb_send_5[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => - \un2_nb_send_next[6]\); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f1(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[37]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => \un2_nb_send_next[7]\, B => - nb_burst_available(7), Y => \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[47]\); - - \address_RNICRBB[7]\ : MX2C - port map(A => \addr_data_vector[39]\, B => - addr_data_vector_71, S => sel_data_0(1), Y => N_1360); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[45]\); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => lclk_c, PRE => rstn, Q - => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => \un2_nb_send_next[9]\, B => state7, Y => - \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[51]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[57]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[55]\); - - un1_address_m14 : AX1 - port map(A => N_13_0, B => \addr_data_vector[39]\, C => - \addr_data_vector[40]\, Y => N_15_0_i_0); - - un1_address_m29 : XNOR2 - port map(A => N_29_0, B => \addr_data_vector[49]\, Y => - N_30_0_i_0); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => - \un2_nb_send_next[6]\, Y => N_30_0); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[61]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[50]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => \un2_nb_send_next[6]\, B => state7, Y => - \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => \un1_address[21]\, B => addr_data_f1(21), S - => \state[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f1(16), S => - \state_0[0]_net_1\, Y => \address_7[16]\); - - \address_RNIRFPD[31]\ : MX2C - port map(A => \addr_data_vector[63]\, B => - addr_data_vector_95, S => sel_data(1), Y => N_984); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f1(0), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => \addr_data_vector[32]\); - - un1_address_m28 : OR3B - port map(A => \addr_data_vector[47]\, B => - \addr_data_vector[48]\, C => N_25_0, Y => N_29_0); - - status_full_err_RNO_0 : OR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => un1_state_5_i_0); - - GND_i : GND - port map(Y => \GND\); - - un1_address_m41 : OR3B - port map(A => m40_m6_0_a2_7, B => \addr_data_vector[56]\, C - => N_25_0, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => \un1_address[27]\, B => addr_data_f1(27), S - => \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[36]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[60]\); - - \state_RNIHPL6[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \address_RNI2MM9[20]\ : MX2C - port map(A => \addr_data_vector[52]\, B => - addr_data_vector_84, S => sel_data_0(1), Y => N_973); - - \nb_send_RNO[2]\ : NOR2B - port map(A => \un2_nb_send_next[2]\, B => state7, Y => - \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3A - port map(A => N_131, B => \state[3]_net_1\, C => N_129, Y - => N_125); - - \state_RNIUNK9[1]\ : NOR2A - port map(A => status_full_ack(1), B => N_131, Y => N_118); - - \address_RNIERBB[8]\ : MX2C - port map(A => \addr_data_vector[40]\, B => - addr_data_vector_72, S => sel_data_0(1), Y => N_1361); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => \un2_nb_send_next[2]\, B => - nb_burst_available(2), Y => \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => \un2_nb_send_next[7]\, B => state7, Y => - \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => - \un2_nb_send_next[5]\); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XOR3 - port map(A => address_0_sqmuxa_i_0, B => - \addr_data_vector[38]\, C => N_5_0, Y => \un1_address[6]\); - - \address_RNIUQBB[0]\ : MX2C - port map(A => \addr_data_vector[32]\, B => - addr_data_vector_64, S => sel_data_0(1), Y => N_1367); - - \address_RNO[19]\ : MX2 - port map(A => \un1_address[19]\, B => addr_data_f1(19), S - => \state[0]_net_1\, Y => \address_7[19]\); - - un1_address_m24 : OR3B - port map(A => \addr_data_vector[45]\, B => - \addr_data_vector[46]\, C => N_23_0, Y => N_25_0); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f1(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[46]\); - - \address_RNI8EN9[23]\ : MX2C - port map(A => \addr_data_vector[55]\, B => - addr_data_vector_87, S => sel_data_0(1), Y => N_976); - - \state_RNO[1]\ : OA1B - port map(A => N_129, B => \state[1]_net_1\, C => - \state_ns_i_0[3]\, Y => N_116); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[2]\); - - un1_address_m40_m6_0_a2_4 : NOR2B - port map(A => \addr_data_vector[54]\, B => m40_m6_0_a2_0, Y - => m40_m6_0_a2_4); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => lclk_c, CLR => rstn, - E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => - \un2_nb_send_next[3]\, Y => \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f1(14), S => - \state_0[0]_net_1\, Y => \address_7[14]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => \un2_nb_send_next[3]\, B => state7, Y => - \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_0, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[56]\); - - un1_address_m27 : AX1 - port map(A => N_25_0, B => \addr_data_vector[47]\, C => - \addr_data_vector[48]\, Y => N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[57]\, Y => - \un1_address[25]\); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XNOR2 - port map(A => N_16_0, B => \addr_data_vector[41]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => - \un2_nb_send_next[8]\); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \address_RNI8MN9[14]\ : MX2C - port map(A => \addr_data_vector[46]\, B => - addr_data_vector_78, S => sel_data_0(1), Y => N_1353); - - \nb_send_RNO[8]\ : NOR2B - port map(A => \un2_nb_send_next[8]\, B => state7, Y => - \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => - \un2_nb_send_next[5]\, Y => \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3B - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => \un2_nb_send_next[9]\, B => - nb_burst_available(9), Y => \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[40]\); - - un1_address_m40_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[50]\, B => - \addr_data_vector[51]\, Y => m40_m6_0_a2_2); - - un1_address_m50 : XNOR2 - port map(A => N_69, B => \addr_data_vector[36]\, Y => - N_51_i_0); - - un1_address_m39 : XNOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[34]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => N_35_0); - - \state_ns_i_a2[1]\ : OR2 - port map(A => update_and_sel_5(3), B => update_and_sel_5(2), - Y => N_129); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f1(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => \un1_address[28]\, B => addr_data_f1(28), S - => \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f1(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, C => N_30_0, Y => N_32); - - \address_RNIV7QD[24]\ : MX2C - port map(A => \addr_data_vector[56]\, B => - addr_data_vector_88, S => sel_data(1), Y => N_977); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => \un2_nb_send_next[5]\, B => - nb_burst_available(5), Y => \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => \un2_nb_send_next[6]\, B => - nb_burst_available(6), Y => \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : AX1C - port map(A => \addr_data_vector[54]\, B => N_37_0, C => - \addr_data_vector[55]\, Y => \un1_address[23]\); - - un1_address_m12 : AO13 - port map(A => N_5_0, B => address_0_sqmuxa_i_0, C => - \addr_data_vector[38]\, Y => N_13_0); - - un1_address_m59 : AX1 - port map(A => N_25_0, B => m40_m6_0_a2_7, C => - \addr_data_vector[56]\, Y => \un1_address[24]\); - - \update_r[0]\ : DFN1C0 - port map(D => update_and_sel_5(2), CLK => lclk_c, CLR => - rstn, Q => \update_r[0]_net_1\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => \un2_nb_send_next[1]\); - - un1_address_m40_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[53]\, B => - \addr_data_vector[52]\, C => m40_m6_0_a2_4, Y => - m40_m6_0_a2_6); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f1(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f1(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : OR3B - port map(A => \addr_data_vector[39]\, B => - \addr_data_vector[40]\, C => N_13_0, Y => N_16_0); - - un1_address_m58 : XOR2 - port map(A => N_37_0, B => \addr_data_vector[54]\, Y => - \un1_address[22]\); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => - \un2_nb_send_next[10]\); - - \update_r_RNIL3G9_0[0]\ : NOR2A - port map(A => \update_r[0]_net_1\, B => \update_r[1]_net_1\, - Y => \un1_state_12_3_0[4]\); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f1(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[35]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : AX1C - port map(A => \addr_data_vector[60]\, B => N_45, C => - \addr_data_vector[61]\, Y => \un1_address[29]\); - - un1_address_m34 : AX1 - port map(A => N_32_0, B => \addr_data_vector[51]\, C => - \addr_data_vector[52]\, Y => \un1_address[20]\); - - \address_RNO[30]\ : MX2 - port map(A => \un1_address[30]\, B => addr_data_f1(30), S - => \state[0]_net_1\, Y => \address_7[30]\); - - \address_RNI7BCB[3]\ : MX2C - port map(A => \addr_data_vector[35]\, B => - addr_data_vector_67, S => sel_data_1(1), Y => N_1370); - - \address_RNI36N9[10]\ : MX2C - port map(A => \addr_data_vector[42]\, B => - addr_data_vector_74, S => sel_data_1(1), Y => N_1363); - - \state_RNO_0[1]\ : OR2 - port map(A => status_full_ack(1), B => N_131, Y => - \state_ns_i_0[3]\); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[3]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => - \un2_nb_send_next[10]\, Y => N_31); - - un1_address_m54 : XNOR2 - port map(A => N_23_0, B => \addr_data_vector[45]\, Y => - N_55_0_i_0); - - un1_address_m22 : OR3B - port map(A => \addr_data_vector[43]\, B => - \addr_data_vector[44]\, C => N_19_0, Y => N_23_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[39]\); - - \address_RNITCEF[5]\ : MX2C - port map(A => \addr_data_vector[37]\, B => - addr_data_vector_69, S => sel_data(1), Y => N_1358); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => - \un2_nb_send_next[7]\); - - \state_RNIL7JMK[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[5]_net_1\); - - \nb_send_RNO[5]\ : NOR2B - port map(A => \un2_nb_send_next[5]\, B => state7, Y => - \nb_send_5[5]\); - - \address_RNI9GRD[29]\ : MX2C - port map(A => \addr_data_vector[61]\, B => - addr_data_vector_93, S => sel_data(1), Y => N_982); - - \address_RNIPFPD[21]\ : MX2C - port map(A => \addr_data_vector[53]\, B => - addr_data_vector_85, S => sel_data(1), Y => N_974); - - un1_address_m25 : XNOR2 - port map(A => N_25_0, B => \addr_data_vector[47]\, Y => - N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => N_113, CLK => lclk_c, CLR => rstn, Q => - \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_5(3), CLK => lclk_c, CLR => - rstn, Q => \update_r[1]_net_1\); - - un1_address_m40_m6_0_a2_7 : NOR3C - port map(A => m40_m6_0_a2_2, B => m40_m6_0_a2_1, C => - m40_m6_0_a2_6, Y => m40_m6_0_a2_7); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => - \un2_nb_send_next[7]\, Y => N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), C => nb_burst_available(5), Y => - \ACT_LT2_E[2]\); - - un1_address_m57 : XNOR2 - port map(A => N_36_0, B => \addr_data_vector[53]\, Y => - \un1_address[21]\); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - \address_RNIARBB[6]\ : MX2C - port map(A => \addr_data_vector[38]\, B => - addr_data_vector_70, S => sel_data_0(1), Y => N_1359); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), C => N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => \un1_address[22]\, B => addr_data_f1(22), S - => \state[0]_net_1\, Y => \address_7[22]\); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[34]\, C => \addr_data_vector[35]\, Y - => N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[41]\); - - \address_RNO[18]\ : MX2 - port map(A => \un1_address[18]\, B => addr_data_f1(18), S - => \state[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f1(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - \address_RNI50RD[27]\ : MX2C - port map(A => \addr_data_vector[59]\, B => - addr_data_vector_91, S => sel_data(1), Y => N_980); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[62]\, B => N_47, C => - \addr_data_vector[63]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[38]\); - - \state_RNIAB30L_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => \un2_nb_send_next[3]\, B => - nb_burst_available(3), Y => \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => \un2_nb_send_next[10]\, B => - nb_burst_available(10), Y => \DWACT_BL_EQUAL_0_E[4]\); - - status_full_err_RNO : AO1A - port map(A => N_129, B => \state[2]_net_1\, C => - un1_state_5_i_0, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => N_118, CLK => lclk_c, CLR => rstn, Q => - \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f1(8), S => - \state_0[0]_net_1\, Y => \address_7[8]\); - - un1_address_m36 : NOR2A - port map(A => \addr_data_vector[53]\, B => N_36_0, Y => - N_37_0); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => - \un2_nb_send_next[9]\); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[43]\); - - \state_RNIAB30L[3]\ : OR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa_i_0); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[63]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => - \un2_nb_send_next[2]\, Y => \ACT_LT4_E[4]\); - - un1_address_m56 : AX1 - port map(A => N_29_0, B => \addr_data_vector[49]\, C => - \addr_data_vector[50]\, Y => \un1_address[18]\); - - \address_RNI9BCB[4]\ : MX2C - port map(A => \addr_data_vector[36]\, B => - addr_data_vector_68, S => sel_data_1(1), Y => N_1371); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f1(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - un1_address_m44 : NOR3C - port map(A => \addr_data_vector[58]\, B => N_43, C => - \addr_data_vector[59]\, Y => N_45); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f1(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => \un1_address[25]\, B => addr_data_f1(25), S - => \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[53]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - un1_address_m62 : AX1C - port map(A => \addr_data_vector[58]\, B => N_43, C => - \addr_data_vector[59]\, Y => \un1_address[27]\); - - un1_address_m32 : XNOR2 - port map(A => N_32_0, B => \addr_data_vector[51]\, Y => - \un1_address[19]\); - - un1_address_m12_e : OR3B - port map(A => \addr_data_vector[36]\, B => - \addr_data_vector[37]\, C => N_69, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => - \un2_nb_send_next[2]\); - - \address_RNIC6O9[16]\ : MX2C - port map(A => \addr_data_vector[48]\, B => - addr_data_vector_80, S => sel_data_0(1), Y => N_1355); - - \state[1]\ : DFN1C0 - port map(D => N_116, CLK => lclk_c, CLR => rstn, Q => - \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[49]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => - \un2_nb_send_next[1]\, Y => \ACT_LT4_E[1]\); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[62]\, Y => - \un1_address[30]\); - - un1_address_m35 : OR3B - port map(A => \addr_data_vector[51]\, B => - \addr_data_vector[52]\, C => N_32_0, Y => N_36_0); - - un1_address_m52 : XNOR2 - port map(A => N_13_0, B => \addr_data_vector[39]\, Y => - N_1_i_0); - - \address_RNI5BCB[2]\ : MX2C - port map(A => \addr_data_vector[34]\, B => - addr_data_vector_66, S => sel_data_1(1), Y => N_1369); - - \update_r_RNIAB30L[0]\ : OR2B - port map(A => \un1_state_12_3_0[4]\, B => - \un1_state_12_2[4]\, Y => \un1_state_12[4]\); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[59]\); - - \state_RNO[3]\ : NOR2B - port map(A => \state[4]_net_1\, B => N_129, Y => N_113); - - un1_address_m21 : AX1 - port map(A => N_19_0, B => \addr_data_vector[43]\, C => - \addr_data_vector[44]\, Y => N_22_0_i_0); - - \nb_send_RNO[4]\ : NOR2B - port map(A => \un2_nb_send_next[4]\, B => state7, Y => - \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => \un2_nb_send_next[10]\, B => state7, Y => - \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => N_29); - - un1_address_m55 : AX1 - port map(A => N_23_0, B => \addr_data_vector[45]\, C => - \addr_data_vector[46]\, Y => N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f1(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : OR3B - port map(A => \addr_data_vector[34]\, B => - \addr_data_vector[35]\, C => \un1_state_12[4]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => \un2_nb_send_next[4]\, B => - nb_burst_available(4), Y => \DWACT_BL_EQUAL_0_E[0]\); - - \address_RNI3BCB[1]\ : MX2C - port map(A => \addr_data_vector[33]\, B => - addr_data_vector_65, S => sel_data_1(1), Y => N_1368); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f1(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => \un2_nb_send_next[8]\, B => - nb_burst_available(8), Y => \DWACT_BL_EQUAL_0_E[2]\); - - \address_RNIP7PD[30]\ : MX2C - port map(A => \addr_data_vector[62]\, B => - addr_data_vector_94, S => sel_data(1), Y => N_983); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f1(1), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => \addr_data_vector[33]\); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_11, Q => status_full(1)); - - \address_RNIGMO9[18]\ : MX2C - port map(A => \addr_data_vector[50]\, B => - addr_data_vector_82, S => sel_data_0(1), Y => N_1357); - - \address_RNI1GQD[25]\ : MX2C - port map(A => \addr_data_vector[57]\, B => - addr_data_vector_89, S => sel_data(1), Y => N_978); - - un1_address_m63 : XOR2 - port map(A => N_45, B => \addr_data_vector[60]\, Y => - \un1_address[28]\); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => \un1_address[20]\, B => addr_data_f1(20), S - => \state[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR3C - port map(A => \addr_data_vector[60]\, B => N_45, C => - \addr_data_vector[61]\, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : AX1 - port map(A => N_16_0, B => \addr_data_vector[41]\, C => - \addr_data_vector[42]\, Y => N_54_0_i_0); - - un1_address_m40_m6_0_a2_0 : NOR2B - port map(A => \addr_data_vector[55]\, B => - \addr_data_vector[47]\, Y => m40_m6_0_a2_0); - - un1_address_m40_m6_0_a2_1 : NOR2B - port map(A => \addr_data_vector[48]\, B => - \addr_data_vector[49]\, Y => m40_m6_0_a2_1); - - \update_r_RNIL3G9[0]\ : OR2A - port map(A => \update_r[1]_net_1\, B => \update_r[0]_net_1\, - Y => un3_update_r); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \state_RNO_1[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => N_124); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f1(15), S => - \state_0[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => - \un2_nb_send_next[4]\); - - un1_address_m42 : NOR2A - port map(A => \addr_data_vector[57]\, B => N_42, Y => N_43); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_dma_send_1word is - - port( Request : out std_logic; - Store : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - Grant : in std_logic; - un1_time_send_ok : out std_logic; - Fault : in std_logic; - Ready : in std_logic; - time_select_0 : in std_logic; - Lock : in std_logic; - Lock_RNIU86D : out std_logic; - time_send : in std_logic - ); - -end lpp_dma_send_1word; - -architecture DEF_ARCH of lpp_dma_send_1word is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal un1_state_4_i_0, \state[1]_net_1\, \state[3]_net_1\, - N_64, \state[2]_net_1\, \state[0]_net_1\, N_58, N_70, - un1_state_2, N_69, \state[4]_net_1\, N_66, Lock_0, - \state_RNO[4]_net_1\, time_send_ok, time_send_ko, - \state_ns[3]\, N_61, \state_ns[1]\, Request_4, - \state_ns[2]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \DMAIn.Lock_RNIU86D\ : MX2 - port map(A => Lock, B => Lock_0, S => time_select_0, Y => - Lock_RNIU86D); - - \state[1]\ : DFN1C0 - port map(D => \state_ns[3]\, CLK => lclk_c, CLR => rstn, Q - => \state[1]_net_1\); - - \state_RNIHJ68[4]\ : NOR2B - port map(A => time_send, B => \state[4]_net_1\, Y => - Request_4); - - GND_i_0 : GND - port map(Y => GND_0); - - \state_RNIRKN62[2]\ : AOI1B - port map(A => Ready, B => Fault, C => \state[2]_net_1\, Y - => N_70); - - \state_RNIO7CM1J[4]\ : OR3 - port map(A => N_69, B => \state[4]_net_1\, C => N_66, Y => - un1_state_2); - - un1_state_2_0_o3 : NOR2A - port map(A => Fault, B => Ready, Y => N_61); - - \state[4]\ : DFN1P0 - port map(D => \state_RNO[4]_net_1\, CLK => lclk_c, PRE => - rstn, Q => \state[4]_net_1\); - - \DMAIn.Request\ : DFN1E1C0 - port map(D => Request_4, CLK => lclk_c, CLR => rstn, E => - un1_state_2, Q => Request); - - VCC_i : VCC - port map(Y => \VCC\); - - \state_RNO[4]\ : NOR2 - port map(A => N_64, B => N_58, Y => \state_RNO[4]_net_1\); - - \state_RNI8KC5[1]\ : OR2 - port map(A => \state[1]_net_1\, B => \state[3]_net_1\, Y - => un1_state_4_i_0); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - send_ok : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_58, Q => time_send_ok); - - \state_RNO[1]\ : NOR2A - port map(A => \state[2]_net_1\, B => Fault, Y => - \state_ns[3]\); - - GND_i : GND - port map(Y => \GND\); - - \state_RNO_0[4]\ : NOR3A - port map(A => time_send, B => \state[2]_net_1\, C => - \state[0]_net_1\, Y => N_64); - - \state_RNIRKN62_0[2]\ : NOR2A - port map(A => \state[2]_net_1\, B => N_61, Y => N_69); - - \DMAIn.Store\ : DFN1E1C0 - port map(D => \state[4]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_2, Q => Store); - - \DMAIn.Lock\ : DFN1E1C0 - port map(D => time_send, CLK => lclk_c, CLR => rstn, E => - \state[4]_net_1\, Q => Lock_0); - - \state_RNO[2]\ : AO1 - port map(A => \state[2]_net_1\, B => N_61, C => N_66, Y => - \state_ns[2]\); - - send_ok_RNIGNLF : OR2 - port map(A => time_send_ok, B => time_send_ko, Y => - un1_time_send_ok); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNI394C2[1]\ : OR2 - port map(A => un1_state_4_i_0, B => N_70, Y => N_58); - - \state_RNO[3]\ : AO1 - port map(A => \state[3]_net_1\, B => Grant, C => Request_4, - Y => \state_ns[1]\); - - \state_RNIN0UCVI[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => Grant, Y => N_66); - - send_ko : DFN1E0C0 - port map(D => \state[0]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_58, Q => time_send_ko); - - \state[0]\ : DFN1C0 - port map(D => \state[1]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[0]_net_1\); - - \state[3]\ : DFN1C0 - port map(D => \state_ns[1]\, CLK => lclk_c, CLR => rstn, Q - => \state[3]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ is - - port( nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(3 to 3); - status_full : out std_logic_vector(3 to 3); - sel_data : in std_logic_vector(1 to 1); - sel_data_1 : in std_logic_vector(1 to 1); - sel_data_0 : in std_logic_vector(1 to 1); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full_ack : in std_logic_vector(3 to 3); - addr_data_vector_56 : out std_logic; - addr_data_vector_55 : out std_logic; - addr_data_vector_17 : in std_logic; - addr_data_vector_13 : in std_logic; - addr_data_vector_10 : in std_logic; - addr_data_vector_2 : in std_logic; - addr_data_vector_0 : in std_logic; - addr_data_vector_8 : in std_logic; - addr_data_vector_4 : in std_logic; - addr_data_vector_63 : out std_logic; - addr_data_vector_6 : in std_logic; - addr_data_vector_19 : in std_logic; - addr_data_vector_62 : out std_logic; - addr_data_vector_60 : out std_logic; - addr_data_vector_59 : out std_logic; - addr_data_vector_58 : out std_logic; - addr_data_vector_86 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_84 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_57 : out std_logic; - addr_data_vector_78 : out std_logic; - addr_data_vector_67 : out std_logic; - addr_data_vector_65 : out std_logic; - addr_data_vector_61 : out std_logic; - addr_data_vector_73 : out std_logic; - addr_data_vector_76 : out std_logic; - addr_data_vector_69 : out std_logic; - addr_data_vector_71 : out std_logic; - addr_data_vector_75 : out std_logic; - update_and_sel_1 : in std_logic_vector(7 downto 6); - N_979 : out std_logic; - N_975 : out std_logic; - N_972 : out std_logic; - N_1364 : out std_logic; - N_1362 : out std_logic; - N_1356 : out std_logic; - N_1352 : out std_logic; - N_1354 : out std_logic; - N_981 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\; - -architecture DEF_ARCH of - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ is - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[0]_net_1\, \state_RNIC6KH[1]_net_1\, N_38, - \nb_send[1]_net_1\, \nb_send[0]_net_1\, N_30, - \nb_send[3]_net_1\, \DWACT_FINC_E[0]\, N_7, - \nb_send[8]_net_1\, \DWACT_FINC_E[4]\, N_129_i, N_125, - \state_ns_a3_1_0[0]\, N_131, \state[3]_net_1\, - m37_m6_0_a2_6, \addr_data_vector[115]\, m37_m6_0_a2_4, - m37_m6_0_a2_5, \addr_data_vector[111]\, m37_m6_0_a2_2, - \addr_data_vector[118]\, \addr_data_vector[113]\, - \un1_state_12_3_0[4]\, \update_r[0]_net_1\, - \update_r[1]_net_1\, \un1_state_12[4]\, - \un1_state_12_2[4]\, \state_RNO[1]_net_1\, N_128, - \state_ns[0]\, N_124, N_110, \state[4]_net_1\, N_130, - \state[2]_net_1\, address_0_sqmuxa, state7, un3_update_r, - \un1_address[6]\, N_5_0, N_38_0_i, N_24_0, N_17_0_i_0, - N_16_0, \addr_data_vector[105]\, N_18_0, N_20_0_i_0, - \addr_data_vector[107]\, N_21_0, \addr_data_vector[106]\, - N_22_0_i_0, \addr_data_vector[108]\, - \addr_data_vector[109]\, N_30_0_i_0, N_27_0, - \addr_data_vector[112]\, N_31_0, N_35_0, N_34_0, - \addr_data_vector[116]\, N_36_0, N_39, N_40_i_0, N_42, - \addr_data_vector[119]\, N_44, \addr_data_vector[122]\, - N_46, \addr_data_vector[124]\, N_47, N_49_i_0, N_50_i_0, - \addr_data_vector[98]\, N_52_i_0, N_69, N_1_i_0, N_13_0, - N_54_0_i_0, N_55_0_i_0, N_56_0_i_0, - \addr_data_vector[110]\, N_57_0, \addr_data_vector[114]\, - N_58_0, \addr_data_vector[117]\, N_59_0, N_60_0, - \addr_data_vector[120]\, N_61_0, \addr_data_vector[121]\, - N_62, N_63_0, \addr_data_vector[123]\, N_64_0, N_65_0, - \addr_data_vector[125]\, N_66_0, \addr_data_vector[126]\, - \addr_data_vector[99]\, \addr_data_vector[100]\, - \addr_data_vector[101]\, \addr_data_vector[102]\, - un1_state_9, \nb_send_5[0]\, \nb_send_5[1]\, I_5_30, - \nb_send_5[2]\, I_9_30, \nb_send_5[3]\, I_13_34, - \nb_send_5[4]\, I_20_22, \nb_send_5[5]\, I_24_15, - \nb_send_5[6]\, I_31_14, \nb_send_5[7]\, I_38_11, - \nb_send_5[8]\, I_45_10, \nb_send_5[9]\, I_52_10, - \nb_send_5[10]\, I_56_11, N_127, \state[1]_net_1\, - \state_RNO_0[3]\, \state_ns[2]\, un1_state_11, - \address_7[2]\, \address_7[3]\, \address_7[4]\, N_51_i_0, - \address_7[5]\, \address_7[6]\, \address_7[7]\, - \address_7[9]\, \address_7[10]\, \address_7[11]\, - \address_7[12]\, \address_7[13]\, \address_7[14]\, - \address_7[17]\, \address_7[18]\, \address_7[20]\, - \address_7[21]\, \address_7[22]\, \state[0]_net_1\, - \address_7[23]\, \address_7[24]\, \address_7[25]\, - \address_7[26]\, \address_7[27]\, \address_7[28]\, - \address_7[29]\, \address_7[30]\, \address_7[31]\, - \address_7[19]\, N_33_0, \address_7[16]\, N_28_0_i_0, - \address_7[15]\, N_26_0_i_0, \address_7[8]\, N_15_0_i_0, - \addr_data_vector[103]\, \addr_data_vector[104]\, - \nb_send[2]_net_1\, \nb_send[4]_net_1\, - \nb_send[5]_net_1\, \nb_send[6]_net_1\, - \nb_send[7]_net_1\, \nb_send[9]_net_1\, - \nb_send[10]_net_1\, \addr_data_vector[127]\, N_4, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_12, N_17, N_22, - \DWACT_FINC_E[1]\, N_27, N_35, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E[1]\, \DWACT_BL_EQUAL_0_E[0]\, N_37, - N_36, N_35_1, N_32, N_34, N_33, N_31, N_28, N_29, N_30_0, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[4]\, \DWACT_BL_EQUAL_0_E[3]\, - \DWACT_BL_EQUAL_0_E_0[0]\, \DWACT_BL_EQUAL_0_E_0[1]\, - \DWACT_BL_EQUAL_0_E[2]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - addr_data_vector_63 <= \addr_data_vector[104]\; - addr_data_vector_62 <= \addr_data_vector[103]\; - addr_data_vector_60 <= \addr_data_vector[101]\; - addr_data_vector_59 <= \addr_data_vector[100]\; - addr_data_vector_58 <= \addr_data_vector[99]\; - addr_data_vector_86 <= \addr_data_vector[127]\; - addr_data_vector_85 <= \addr_data_vector[126]\; - addr_data_vector_84 <= \addr_data_vector[125]\; - addr_data_vector_82 <= \addr_data_vector[123]\; - addr_data_vector_80 <= \addr_data_vector[121]\; - addr_data_vector_79 <= \addr_data_vector[120]\; - addr_data_vector_57 <= \addr_data_vector[98]\; - addr_data_vector_78 <= \addr_data_vector[119]\; - addr_data_vector_67 <= \addr_data_vector[108]\; - addr_data_vector_65 <= \addr_data_vector[106]\; - addr_data_vector_61 <= \addr_data_vector[102]\; - addr_data_vector_73 <= \addr_data_vector[114]\; - addr_data_vector_76 <= \addr_data_vector[117]\; - addr_data_vector_69 <= \addr_data_vector[110]\; - addr_data_vector_71 <= \addr_data_vector[112]\; - addr_data_vector_75 <= \addr_data_vector[116]\; - - \address[16]\ : DFN1C0 - port map(D => \address_7[16]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[112]\); - - \address[10]\ : DFN1C0 - port map(D => \address_7[10]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[106]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNIC6KH[1]_net_1\, CLK => lclk_c, CLR - => rstn, Q => \state[0]_net_1\); - - \address[30]\ : DFN1C0 - port map(D => \address_7[30]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[126]\); - - un1_address_m45 : OR3B - port map(A => \addr_data_vector[123]\, B => - \addr_data_vector[124]\, C => N_44, Y => N_46); - - \address_RNO[26]\ : MX2 - port map(A => N_62, B => addr_data_f3(26), S => - \state[0]_net_1\, Y => \address_7[26]\); - - \FSM_SELECT_ADDRESS.state7_0_I_25\ : AO1C - port map(A => I_52_10, B => nb_burst_available(9), C => - N_31, Y => N_36); - - un1_address_m61 : AX1 - port map(A => N_42, B => \addr_data_vector[121]\, C => - \addr_data_vector[122]\, Y => N_62); - - un1_address_m37_m6_0_a2_4 : NOR3C - port map(A => \addr_data_vector[110]\, B => - \addr_data_vector[118]\, C => \addr_data_vector[117]\, Y - => m37_m6_0_a2_4); - - \address[26]\ : DFN1C0 - port map(D => \address_7[26]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[122]\); - - \address[20]\ : DFN1C0 - port map(D => \address_7[20]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[116]\); - - \FSM_SELECT_ADDRESS.state7_0_I_42\ : AO1C - port map(A => I_20_22, B => nb_burst_available(4), C => - I_24_15, Y => \ACT_LT2_E[1]\); - - \state_RNO_0[2]\ : NOR2A - port map(A => N_130, B => status_full_ack(3), Y => N_127); - - \address_RNIIMO9[28]\ : MX2C - port map(A => addr_data_vector_19, B => - \addr_data_vector[124]\, S => sel_data_0(1), Y => N_981); - - \FSM_SELECT_ADDRESS.state7_0_I_57\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - \FSM_SELECT_ADDRESS.state7_0_I_36\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[1]\, B => - \DWACT_BL_EQUAL_0_E[0]\, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - un1_address_m51 : AX1 - port map(A => N_69, B => \addr_data_vector[100]\, C => - \addr_data_vector[101]\, Y => N_52_i_0); - - \address[12]\ : DFN1C0 - port map(D => \address_7[12]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[108]\); - - \FSM_SELECT_ADDRESS.state7_0_I_22\ : OA1A - port map(A => I_52_10, B => nb_burst_available(9), C => - N_29, Y => N_33); - - \address_RNO[29]\ : MX2 - port map(A => N_65_0, B => addr_data_f3(29), S => - \state[0]_net_1\, Y => \address_7[29]\); - - \FSM_SELECT_ADDRESS.state7_0_I_8\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - un1_address_m19 : AX1 - port map(A => N_18_0, B => \addr_data_vector[106]\, C => - \addr_data_vector[107]\, Y => N_20_0_i_0); - - \address[22]\ : DFN1C0 - port map(D => \address_7[22]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[118]\); - - \address_RNO[23]\ : MX2 - port map(A => N_39, B => addr_data_f3(23), S => - \state[0]_net_1\, Y => \address_7[23]\); - - \address[2]\ : DFN1C0 - port map(D => \address_7[2]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[98]\); - - un2_nb_send_next_I_13 : XOR2 - port map(A => N_35, B => \nb_send[3]_net_1\, Y => I_13_34); - - \update_r_RNIPMQ1_0[0]\ : NOR2A - port map(A => \update_r[0]_net_1\, B => \update_r[1]_net_1\, - Y => \un1_state_12_3_0[4]\); - - un1_address_m43 : OR3B - port map(A => \addr_data_vector[121]\, B => - \addr_data_vector[122]\, C => N_42, Y => N_44); - - \FSM_SELECT_ADDRESS.state7_0_I_54\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \address_RNO[24]\ : MX2 - port map(A => N_60_0, B => addr_data_f3(24), S => - \state[0]_net_1\, Y => \address_7[24]\); - - \address_RNO[10]\ : MX2 - port map(A => N_54_0_i_0, B => addr_data_f3(10), S => - \state_0[0]_net_1\, Y => \address_7[10]\); - - \status_full_err\ : DFN1E0C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_110, Q => status_full_err(3)); - - un2_nb_send_next_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \nb_send[8]_net_1\, C - => \nb_send[9]_net_1\, Y => N_4); - - \nb_send_RNO[1]\ : NOR2B - port map(A => I_5_30, B => state7, Y => \nb_send_5[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_51\ : NOR2B - port map(A => \nb_send[0]_net_1\, B => - nb_burst_available(0), Y => \ACT_LT4_E[0]\); - - un2_nb_send_next_I_31 : XOR2 - port map(A => N_22, B => \nb_send[6]_net_1\, Y => I_31_14); - - \nb_send[9]\ : DFN1E0C0 - port map(D => \nb_send_5[9]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[9]_net_1\); - - \address_RNO[9]\ : MX2 - port map(A => N_17_0_i_0, B => addr_data_f3(9), S => - \state_0[0]_net_1\, Y => \address_7[9]\); - - \address[5]\ : DFN1C0 - port map(D => \address_7[5]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[101]\); - - \FSM_SELECT_ADDRESS.state7_0_I_5\ : XNOR2 - port map(A => I_38_11, B => nb_burst_available(7), Y => - \DWACT_BL_EQUAL_0_E_0[1]\); - - \address[15]\ : DFN1C0 - port map(D => \address_7[15]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[111]\); - - \address_RNIAUN9[15]\ : MX2C - port map(A => addr_data_vector_6, B => - \addr_data_vector[111]\, S => sel_data_0(1), Y => N_1354); - - \address[13]\ : DFN1C0 - port map(D => \address_7[13]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[109]\); - - un1_address_m20 : OR3B - port map(A => \addr_data_vector[106]\, B => - \addr_data_vector[107]\, C => N_18_0, Y => N_21_0); - - \state[4]\ : DFN1P0 - port map(D => \state_ns[0]\, CLK => lclk_c, PRE => rstn, Q - => \state[4]_net_1\); - - \nb_send_RNO[9]\ : NOR2B - port map(A => I_52_10, B => state7, Y => \nb_send_5[9]\); - - \address[19]\ : DFN1C0 - port map(D => \address_7[19]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[115]\); - - \address[25]\ : DFN1C0 - port map(D => \address_7[25]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[121]\); - - un2_nb_send_next_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \nb_send[5]_net_1\, Y => N_22); - - \address[23]\ : DFN1C0 - port map(D => \address_7[23]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[119]\); - - un1_address_m14 : AX1C - port map(A => \addr_data_vector[103]\, B => N_13_0, C => - \addr_data_vector[104]\, Y => N_15_0_i_0); - - \address_RNIRNPD[22]\ : MX2C - port map(A => addr_data_vector_13, B => - \addr_data_vector[118]\, S => sel_data(1), Y => N_975); - - \address_RNIGRBB[9]\ : MX2C - port map(A => addr_data_vector_0, B => - \addr_data_vector[105]\, S => sel_data_0(1), Y => N_1362); - - un1_address_m29 : AX1 - port map(A => N_27_0, B => \addr_data_vector[112]\, C => - \addr_data_vector[113]\, Y => N_30_0_i_0); - - \address_RNI3OQD[26]\ : MX2C - port map(A => addr_data_vector_17, B => - \addr_data_vector[122]\, S => sel_data(1), Y => N_979); - - un2_nb_send_next_I_12 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => N_35); - - \FSM_SELECT_ADDRESS.state7_0_I_19\ : NOR2A - port map(A => nb_burst_available(6), B => I_31_14, Y => - N_30_0); - - \address[29]\ : DFN1C0 - port map(D => \address_7[29]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[125]\); - - \address[18]\ : DFN1C0 - port map(D => \address_7[18]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[114]\); - - \nb_send_RNO[6]\ : NOR2B - port map(A => I_31_14, B => state7, Y => \nb_send_5[6]\); - - \address_RNO[21]\ : MX2 - port map(A => N_58_0, B => addr_data_f3(21), S => - \state_0[0]_net_1\, Y => \address_7[21]\); - - \address_RNO[16]\ : MX2 - port map(A => N_28_0_i_0, B => addr_data_f3(16), S => - \state[0]_net_1\, Y => \address_7[16]\); - - un2_nb_send_next_I_51 : NOR2B - port map(A => \nb_send[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_7); - - \address[0]\ : DFN1E1C0 - port map(D => addr_data_f3(0), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => addr_data_vector_55); - - \state_RNI49HNB1[3]\ : NOR3B - port map(A => \state[3]_net_1\, B => state7, C => - un3_update_r, Y => address_0_sqmuxa); - - GND_i : GND - port map(Y => \GND\); - - \address_RNIEEO9[17]\ : MX2C - port map(A => addr_data_vector_8, B => - \addr_data_vector[113]\, S => sel_data_0(1), Y => N_1356); - - un1_address_m41 : OR3B - port map(A => \addr_data_vector[119]\, B => - \addr_data_vector[120]\, C => N_38_0_i, Y => N_42); - - \address_RNO[27]\ : MX2 - port map(A => N_63_0, B => addr_data_f3(27), S => - \state[0]_net_1\, Y => \address_7[27]\); - - \address[4]\ : DFN1C0 - port map(D => \address_7[4]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[100]\); - - \address[28]\ : DFN1C0 - port map(D => \address_7[28]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[124]\); - - \FSM_SELECT_ADDRESS.state7_0_I_7\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E[4]\, B => - \DWACT_BL_EQUAL_0_E[3]\, Y => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - un1_address_m17 : OR2B - port map(A => N_16_0, B => \addr_data_vector[105]\, Y => - N_18_0); - - \nb_send_RNO[2]\ : NOR2B - port map(A => I_9_30, B => state7, Y => \nb_send_5[2]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNO_0[4]\ : OR3A - port map(A => \state_0[0]_net_1\, B => \state[2]_net_1\, C - => \state[3]_net_1\, Y => N_124); - - \state_RNIBIMLB1[3]\ : NOR2B - port map(A => \state[3]_net_1\, B => state7, Y => - \un1_state_12_2[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_58\ : NOR2A - port map(A => I_9_30, B => nb_burst_available(2), Y => - \ACT_LT4_E[7]\); - - \nb_send_RNO[7]\ : NOR2B - port map(A => I_38_11, B => state7, Y => \nb_send_5[7]\); - - un2_nb_send_next_I_24 : XOR2 - port map(A => N_27, B => \nb_send[5]_net_1\, Y => I_24_15); - - un2_nb_send_next_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \nb_send[3]_net_1\, C - => \nb_send[4]_net_1\, Y => N_27); - - un1_address_ADD_32x32_fast_I164_Y_0 : XNOR3 - port map(A => address_0_sqmuxa, B => - \addr_data_vector[102]\, C => N_5_0, Y => - \un1_address[6]\); - - \state_RNI8OU01[2]\ : NOR3A - port map(A => \state[2]_net_1\, B => update_and_sel_1(6), C - => update_and_sel_1(7), Y => N_130); - - \address_RNO[19]\ : MX2 - port map(A => N_33_0, B => addr_data_f3(19), S => - \state[0]_net_1\, Y => \address_7[19]\); - - \nb_send[7]\ : DFN1E0C0 - port map(D => \nb_send_5[7]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[7]_net_1\); - - \address_RNO[13]\ : MX2 - port map(A => N_55_0_i_0, B => addr_data_f3(13), S => - \state_0[0]_net_1\, Y => \address_7[13]\); - - \address[14]\ : DFN1C0 - port map(D => \address_7[14]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[110]\); - - \state_RNO[1]\ : NOR3 - port map(A => N_131, B => status_full_ack(3), C => N_128, Y - => \state_RNO[1]_net_1\); - - \nb_send[0]\ : DFN1E0C0 - port map(D => \nb_send_5[0]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[0]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_53\ : AND2A - port map(A => nb_burst_available(1), B => I_5_30, Y => - \ACT_LT4_E[2]\); - - \nb_send[6]\ : DFN1E0C0 - port map(D => \nb_send_5[6]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[6]_net_1\); - - \nb_send[10]\ : DFN1E0C0 - port map(D => \nb_send_5[10]\, CLK => lclk_c, CLR => rstn, - E => un1_state_9, Q => \nb_send[10]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_56\ : NOR2A - port map(A => nb_burst_available(3), B => I_13_34, Y => - \ACT_LT4_E[5]\); - - \address_RNO[14]\ : MX2 - port map(A => N_56_0_i_0, B => addr_data_f3(14), S => - \state_0[0]_net_1\, Y => \address_7[14]\); - - \nb_send_RNO[3]\ : NOR2B - port map(A => I_13_34, B => state7, Y => \nb_send_5[3]\); - - \nb_send[2]\ : DFN1E0C0 - port map(D => \nb_send_5[2]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[2]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_27\ : OA1 - port map(A => N_37, B => N_36, C => N_35_1, Y => - \DWACT_COMP0_E[0]\); - - \address[24]\ : DFN1C0 - port map(D => \address_7[24]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[120]\); - - un1_address_m27 : XNOR2 - port map(A => N_27_0, B => \addr_data_vector[112]\, Y => - N_28_0_i_0); - - VCC_i : VCC - port map(Y => \VCC\); - - un1_address_m60 : XNOR2 - port map(A => N_42, B => \addr_data_vector[121]\, Y => - N_61_0); - - \FSM_SELECT_ADDRESS.state7_0_I_44\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - un1_address_m30 : OR3B - port map(A => \addr_data_vector[112]\, B => - \addr_data_vector[113]\, C => N_27_0, Y => N_31_0); - - \nb_send[4]\ : DFN1E0C0 - port map(D => \nb_send_5[4]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[4]_net_1\); - - un1_address_m16 : XOR2 - port map(A => N_16_0, B => \addr_data_vector[105]\, Y => - N_17_0_i_0); - - un2_nb_send_next_I_45 : XOR2 - port map(A => N_12, B => \nb_send[8]_net_1\, Y => I_45_10); - - \nb_send_RNO[0]\ : NOR2A - port map(A => state7, B => \nb_send[0]_net_1\, Y => - \nb_send_5[0]\); - - \nb_send_RNO[8]\ : NOR2B - port map(A => I_45_10, B => state7, Y => \nb_send_5[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_41\ : AND2A - port map(A => nb_burst_available(5), B => I_24_15, Y => - \ACT_LT2_E[0]\); - - \state_RNO[4]\ : OR3B - port map(A => N_125, B => N_124, C => \un1_state_12_2[4]\, - Y => \state_ns[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_4\ : XNOR2 - port map(A => I_52_10, B => nb_burst_available(9), Y => - \DWACT_BL_EQUAL_0_E[3]\); - - \address[8]\ : DFN1C0 - port map(D => \address_7[8]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[104]\); - - un1_address_m50 : XNOR2 - port map(A => N_69, B => \addr_data_vector[100]\, Y => - N_51_i_0); - - \state_RNI49HNB1_0[3]\ : AO1B - port map(A => un3_update_r, B => state7, C => - \state[3]_net_1\, Y => un1_state_9); - - un1_address_m39 : XNOR2 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[98]\, Y => N_40_i_0); - - \FSM_SELECT_ADDRESS.state7_0_I_24\ : OR2A - port map(A => I_56_11, B => nb_burst_available(10), Y => - N_35_1); - - \state_ns_i_a2[1]\ : NOR2 - port map(A => update_and_sel_1(7), B => update_and_sel_1(6), - Y => N_129_i); - - \address_RNO[6]\ : MX2 - port map(A => \un1_address[6]\, B => addr_data_f3(6), S => - \state_0[0]_net_1\, Y => \address_7[6]\); - - \state_RNO[2]\ : AO1A - port map(A => state7, B => \state[3]_net_1\, C => N_127, Y - => \state_ns[2]\); - - \address_RNO[28]\ : MX2 - port map(A => N_64_0, B => addr_data_f3(28), S => - \state[0]_net_1\, Y => \address_7[28]\); - - \address_RNO[11]\ : MX2 - port map(A => N_20_0_i_0, B => addr_data_f3(11), S => - \state_0[0]_net_1\, Y => \address_7[11]\); - - \FSM_SELECT_ADDRESS.state7_0_I_21\ : AO1C - port map(A => nb_burst_available(7), B => I_38_11, C => - N_30_0, Y => N_32); - - \FSM_SELECT_ADDRESS.state7_0_I_73\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => state7); - - \FSM_SELECT_ADDRESS.state7_0_I_35\ : XNOR2 - port map(A => I_24_15, B => nb_burst_available(5), Y => - \DWACT_BL_EQUAL_0_E[1]\); - - \FSM_SELECT_ADDRESS.state7_0_I_2\ : XNOR2 - port map(A => I_31_14, B => nb_burst_available(6), Y => - \DWACT_BL_EQUAL_0_E_0[0]\); - - un1_address_m38 : XNOR2 - port map(A => N_38_0_i, B => \addr_data_vector[119]\, Y => - N_39); - - un1_address_m12 : AO13 - port map(A => address_0_sqmuxa, B => - \addr_data_vector[102]\, C => N_5_0, Y => N_13_0); - - un1_address_m59 : AX1 - port map(A => N_38_0_i, B => \addr_data_vector[119]\, C => - \addr_data_vector[120]\, Y => N_60_0); - - \update_r[0]\ : DFN1C0 - port map(D => update_and_sel_1(6), CLK => lclk_c, CLR => - rstn, Q => \update_r[0]_net_1\); - - un2_nb_send_next_I_5 : XOR2 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - Y => I_5_30); - - \address_RNO[17]\ : MX2 - port map(A => N_30_0_i_0, B => addr_data_f3(17), S => - \state_0[0]_net_1\, Y => \address_7[17]\); - - \address_RNO[5]\ : MX2 - port map(A => N_52_i_0, B => addr_data_f3(5), S => - \state_0[0]_net_1\, Y => \address_7[5]\); - - un1_address_m15 : NOR3C - port map(A => \addr_data_vector[103]\, B => N_13_0, C => - \addr_data_vector[104]\, Y => N_16_0); - - un1_address_m58 : AX1C - port map(A => \addr_data_vector[117]\, B => N_36_0, C => - \addr_data_vector[118]\, Y => N_59_0); - - un2_nb_send_next_I_56 : XOR2 - port map(A => N_4, B => \nb_send[10]_net_1\, Y => I_56_11); - - un1_address_m26 : OR3B - port map(A => \addr_data_vector[110]\, B => - \addr_data_vector[111]\, C => N_24_0, Y => N_27_0); - - un2_nb_send_next_I_41 : AND2 - port map(A => \nb_send[6]_net_1\, B => \nb_send[7]_net_1\, - Y => \DWACT_FINC_E[3]\); - - \address_RNO[3]\ : MX2 - port map(A => N_50_i_0, B => addr_data_f3(3), S => - \state_0[0]_net_1\, Y => \address_7[3]\); - - \address[3]\ : DFN1C0 - port map(D => \address_7[3]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[99]\); - - un2_nb_send_next_I_34 : AND3 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - C => \nb_send[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un1_address_m64 : XNOR2 - port map(A => N_46, B => \addr_data_vector[125]\, Y => - N_65_0); - - un1_address_m34 : XNOR2 - port map(A => N_34_0, B => \addr_data_vector[116]\, Y => - N_35_0); - - \address_RNO[30]\ : MX2 - port map(A => N_66_0, B => addr_data_f3(30), S => - \state[0]_net_1\, Y => \address_7[30]\); - - \state_RNO_0[1]\ : NOR3 - port map(A => update_and_sel_1(6), B => update_and_sel_1(7), - C => \state[1]_net_1\, Y => N_128); - - \nb_send[3]\ : DFN1E0C0 - port map(D => \nb_send_5[3]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[3]_net_1\); - - \update_r_RNI49HNB1[0]\ : OR2B - port map(A => \un1_state_12_3_0[4]\, B => - \un1_state_12_2[4]\, Y => \un1_state_12[4]\); - - \FSM_SELECT_ADDRESS.state7_0_I_20\ : OR2A - port map(A => nb_burst_available(10), B => I_56_11, Y => - N_31); - - un1_address_m54 : AX1 - port map(A => N_21_0, B => \addr_data_vector[108]\, C => - \addr_data_vector[109]\, Y => N_55_0_i_0); - - \address[7]\ : DFN1C0 - port map(D => \address_7[7]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[103]\); - - un2_nb_send_next_I_38 : XOR2 - port map(A => N_17, B => \nb_send[7]_net_1\, Y => I_38_11); - - \nb_send[5]\ : DFN1E0C0 - port map(D => \nb_send_5[5]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[5]_net_1\); - - un1_address_m37_m6_0_a2_2 : NOR2B - port map(A => \addr_data_vector[113]\, B => - \addr_data_vector[114]\, Y => m37_m6_0_a2_2); - - \nb_send_RNO[5]\ : NOR2B - port map(A => I_24_15, B => state7, Y => \nb_send_5[5]\); - - un1_address_m25 : AX1 - port map(A => N_24_0, B => \addr_data_vector[110]\, C => - \addr_data_vector[111]\, Y => N_26_0_i_0); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_0[3]\, CLK => lclk_c, CLR => rstn, - Q => \state[3]_net_1\); - - \update_r[1]\ : DFN1C0 - port map(D => update_and_sel_1(7), CLK => lclk_c, CLR => - rstn, Q => \update_r[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_17\ : OR2A - port map(A => nb_burst_available(7), B => I_38_11, Y => - N_28); - - \FSM_SELECT_ADDRESS.state7_0_I_43\ : AO1A - port map(A => I_20_22, B => nb_burst_available(4), C => - nb_burst_available(5), Y => \ACT_LT2_E[2]\); - - \state_RNITVKE[1]\ : NOR2 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, Y - => N_131); - - un1_address_m57 : XOR2 - port map(A => N_36_0, B => \addr_data_vector[117]\, Y => - N_58_0); - - un2_nb_send_next_I_8 : NOR2B - port map(A => \nb_send[1]_net_1\, B => \nb_send[0]_net_1\, - Y => N_38); - - un1_address_m37_m6_0_a2_5 : NOR3C - port map(A => \addr_data_vector[112]\, B => - \addr_data_vector[111]\, C => m37_m6_0_a2_2, Y => - m37_m6_0_a2_5); - - \FSM_SELECT_ADDRESS.state7_0_I_23\ : AO1C - port map(A => I_45_10, B => nb_burst_available(8), C => - N_28, Y => N_34); - - \FSM_SELECT_ADDRESS.state7_0_I_26\ : OA1A - port map(A => N_32, B => N_34, C => N_33, Y => N_37); - - \address_RNO[22]\ : MX2 - port map(A => N_59_0, B => addr_data_f3(22), S => - \state[0]_net_1\, Y => \address_7[22]\); - - \address_RNI5EN9[11]\ : MX2C - port map(A => addr_data_vector_2, B => - \addr_data_vector[107]\, S => sel_data_1(1), Y => N_1364); - - un2_nb_send_next_I_27 : AND2 - port map(A => \nb_send[3]_net_1\, B => \nb_send[4]_net_1\, - Y => \DWACT_FINC_E[1]\); - - un1_address_m49 : AX1 - port map(A => \un1_state_12[4]\, B => - \addr_data_vector[98]\, C => \addr_data_vector[99]\, Y - => N_50_i_0); - - \address[9]\ : DFN1C0 - port map(D => \address_7[9]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[105]\); - - \address_RNO[18]\ : MX2 - port map(A => N_57_0, B => addr_data_f3(18), S => - \state_0[0]_net_1\, Y => \address_7[18]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \address_RNO[7]\ : MX2 - port map(A => N_1_i_0, B => addr_data_f3(7), S => - \state_0[0]_net_1\, Y => \address_7[7]\); - - un1_address_m37_m6_0_a2_6 : NOR3C - port map(A => \addr_data_vector[116]\, B => - \addr_data_vector[115]\, C => m37_m6_0_a2_4, Y => - m37_m6_0_a2_6); - - un1_address_m48 : AX1C - port map(A => \addr_data_vector[126]\, B => N_47, C => - \addr_data_vector[127]\, Y => N_49_i_0); - - \address[6]\ : DFN1C0 - port map(D => \address_7[6]\, CLK => lclk_c, CLR => rstn, Q - => \addr_data_vector[102]\); - - \FSM_SELECT_ADDRESS.state7_0_I_59\ : OR2A - port map(A => I_13_34, B => nb_burst_available(3), Y => - \ACT_LT4_E[8]\); - - \FSM_SELECT_ADDRESS.state7_0_I_1\ : XNOR2 - port map(A => I_56_11, B => nb_burst_available(10), Y => - \DWACT_BL_EQUAL_0_E[4]\); - - \state_ns_a3_1_RNO[0]\ : NOR2A - port map(A => N_131, B => \state[3]_net_1\, Y => - \state_ns_a3_1_0[0]\); - - un1_address_m23 : OR3B - port map(A => \addr_data_vector[108]\, B => - \addr_data_vector[109]\, C => N_21_0, Y => N_24_0); - - status_full_err_RNO : OR3 - port map(A => \state[3]_net_1\, B => \state[4]_net_1\, C - => N_130, Y => N_110); - - \state_0[0]\ : DFN1C0 - port map(D => \state_RNIC6KH[1]_net_1\, CLK => lclk_c, CLR - => rstn, Q => \state_0[0]_net_1\); - - \address_RNO[8]\ : MX2 - port map(A => N_15_0_i_0, B => addr_data_f3(8), S => - \state[0]_net_1\, Y => \address_7[8]\); - - un2_nb_send_next_I_52 : XOR2 - port map(A => N_7, B => \nb_send[9]_net_1\, Y => I_52_10); - - \address[11]\ : DFN1C0 - port map(D => \address_7[11]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[107]\); - - \address[31]\ : DFN1C0 - port map(D => \address_7[31]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[127]\); - - \FSM_SELECT_ADDRESS.state7_0_I_55\ : OR2A - port map(A => nb_burst_available(2), B => I_9_30, Y => - \ACT_LT4_E[4]\); - - un1_address_m56 : XNOR2 - port map(A => N_31_0, B => \addr_data_vector[114]\, Y => - N_57_0); - - \address_RNO[2]\ : MX2 - port map(A => N_40_i_0, B => addr_data_f3(2), S => - \state_0[0]_net_1\, Y => \address_7[2]\); - - \address_RNO[4]\ : MX2 - port map(A => N_51_i_0, B => addr_data_f3(4), S => - \state_0[0]_net_1\, Y => \address_7[4]\); - - un2_nb_send_next_I_19 : NOR2B - port map(A => \nb_send[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_30); - - \address_RNO[25]\ : MX2 - port map(A => N_61_0, B => addr_data_f3(25), S => - \state[0]_net_1\, Y => \address_7[25]\); - - \address[21]\ : DFN1C0 - port map(D => \address_7[21]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[117]\); - - \state[2]\ : DFN1C0 - port map(D => \state_ns[2]\, CLK => lclk_c, CLR => rstn, Q - => \state[2]_net_1\); - - un1_address_m62 : XNOR2 - port map(A => N_44, B => \addr_data_vector[123]\, Y => - N_63_0); - - un1_address_m32 : AX1 - port map(A => N_31_0, B => \addr_data_vector[114]\, C => - \addr_data_vector[115]\, Y => N_33_0); - - un1_address_m12_e : OR3B - port map(A => \addr_data_vector[100]\, B => - \addr_data_vector[101]\, C => N_69, Y => N_5_0); - - un2_nb_send_next_I_9 : XOR2 - port map(A => N_38, B => \nb_send[2]_net_1\, Y => I_9_30); - - \state[1]\ : DFN1C0 - port map(D => \state_RNO[1]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[1]_net_1\); - - \address[17]\ : DFN1C0 - port map(D => \address_7[17]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[113]\); - - \FSM_SELECT_ADDRESS.state7_0_I_52\ : OR2A - port map(A => nb_burst_available(1), B => I_5_30, Y => - \ACT_LT4_E[1]\); - - \update_r_RNIPMQ1[0]\ : OR2A - port map(A => \update_r[1]_net_1\, B => \update_r[0]_net_1\, - Y => un3_update_r); - - un1_address_m65 : XOR2 - port map(A => N_47, B => \addr_data_vector[126]\, Y => - N_66_0); - - un1_address_m35 : NOR2A - port map(A => \addr_data_vector[116]\, B => N_34_0, Y => - N_36_0); - - un1_address_m52 : XOR2 - port map(A => N_13_0, B => \addr_data_vector[103]\, Y => - N_1_i_0); - - \address_RNI6EN9[13]\ : MX2C - port map(A => addr_data_vector_4, B => - \addr_data_vector[109]\, S => sel_data_0(1), Y => N_1352); - - \address[27]\ : DFN1C0 - port map(D => \address_7[27]\, CLK => lclk_c, CLR => rstn, - Q => \addr_data_vector[123]\); - - un1_address_m37_m6_0_a2 : OR3B - port map(A => m37_m6_0_a2_6, B => m37_m6_0_a2_5, C => - N_24_0, Y => N_38_0_i); - - \address_RNI7GRD[19]\ : MX2C - port map(A => addr_data_vector_10, B => - \addr_data_vector[115]\, S => sel_data(1), Y => N_972); - - \state_RNO[3]\ : OA1 - port map(A => update_and_sel_1(6), B => update_and_sel_1(7), - C => \state[4]_net_1\, Y => \state_RNO_0[3]\); - - un1_address_m21 : XNOR2 - port map(A => N_21_0, B => \addr_data_vector[108]\, Y => - N_22_0_i_0); - - \state_ns_a3_1[0]\ : NAND2 - port map(A => N_129_i, B => \state_ns_a3_1_0[0]\, Y => - N_125); - - \nb_send_RNO[4]\ : NOR2B - port map(A => I_20_22, B => state7, Y => \nb_send_5[4]\); - - \nb_send_RNO[10]\ : NOR2B - port map(A => I_56_11, B => state7, Y => \nb_send_5[10]\); - - \FSM_SELECT_ADDRESS.state7_0_I_18\ : OR2A - port map(A => I_45_10, B => nb_burst_available(8), Y => - N_29); - - un1_address_m55 : XNOR2 - port map(A => N_24_0, B => \addr_data_vector[110]\, Y => - N_56_0_i_0); - - \address_RNO[31]\ : MX2 - port map(A => N_49_i_0, B => addr_data_f3(31), S => - \state[0]_net_1\, Y => \address_7[31]\); - - \FSM_SELECT_ADDRESS.state7_0_I_61\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - un1_address_m10_e : OR3B - port map(A => \addr_data_vector[98]\, B => - \addr_data_vector[99]\, C => \un1_state_12[4]\, Y => N_69); - - \FSM_SELECT_ADDRESS.state7_0_I_34\ : XNOR2 - port map(A => I_20_22, B => nb_burst_available(4), Y => - \DWACT_BL_EQUAL_0_E[0]\); - - \FSM_SELECT_ADDRESS.state7_0_I_6\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_0[0]\, B => - \DWACT_BL_EQUAL_0_E_0[1]\, C => \DWACT_BL_EQUAL_0_E[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \address_RNO[12]\ : MX2 - port map(A => N_22_0_i_0, B => addr_data_f3(12), S => - \state_0[0]_net_1\, Y => \address_7[12]\); - - un2_nb_send_next_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \nb_send[6]_net_1\, Y => N_17); - - un2_nb_send_next_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_12); - - \FSM_SELECT_ADDRESS.state7_0_I_3\ : XNOR2 - port map(A => I_45_10, B => nb_burst_available(8), Y => - \DWACT_BL_EQUAL_0_E[2]\); - - status_full_RNO : AO1A - port map(A => state7, B => \state[3]_net_1\, C => - \state[2]_net_1\, Y => un1_state_11); - - \address[1]\ : DFN1E1C0 - port map(D => addr_data_f3(1), CLK => lclk_c, CLR => rstn, - E => \state[0]_net_1\, Q => addr_data_vector_56); - - \status_full\ : DFN1E1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_11, Q => status_full(3)); - - un1_address_m63 : AX1 - port map(A => N_44, B => \addr_data_vector[123]\, C => - \addr_data_vector[124]\, Y => N_64_0); - - un1_address_m33 : OR3B - port map(A => \addr_data_vector[114]\, B => - \addr_data_vector[115]\, C => N_31_0, Y => N_34_0); - - \state_RNIC6KH[1]\ : NOR2A - port map(A => status_full_ack(3), B => N_131, Y => - \state_RNIC6KH[1]_net_1\); - - un2_nb_send_next_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - \address_RNO[20]\ : MX2 - port map(A => N_35_0, B => addr_data_f3(20), S => - \state_0[0]_net_1\, Y => \address_7[20]\); - - un1_address_m46 : NOR2A - port map(A => \addr_data_vector[125]\, B => N_46, Y => N_47); - - \nb_send[8]\ : DFN1E0C0 - port map(D => \nb_send_5[8]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[8]_net_1\); - - un1_address_m53 : XNOR2 - port map(A => N_18_0, B => \addr_data_vector[106]\, Y => - N_54_0_i_0); - - \nb_send[1]\ : DFN1E0C0 - port map(D => \nb_send_5[1]\, CLK => lclk_c, CLR => rstn, E - => un1_state_9, Q => \nb_send[1]_net_1\); - - \FSM_SELECT_ADDRESS.state7_0_I_60\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \address_RNO[15]\ : MX2 - port map(A => N_26_0_i_0, B => addr_data_f3(15), S => - \state[0]_net_1\, Y => \address_7[15]\); - - un2_nb_send_next_I_20 : XOR2 - port map(A => N_30, B => \nb_send[4]_net_1\, Y => I_20_22); - - \FSM_SELECT_ADDRESS.state7_0_I_68\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - un2_nb_send_next_I_16 : AND3 - port map(A => \nb_send[0]_net_1\, B => \nb_send[1]_net_1\, - C => \nb_send[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity DMA2AHB is - - port( hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - Address_RNIP8BS : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - Address_RNIJ4SP : in std_logic_vector(20 to 20); - iosn_1 : in std_logic_vector(93 to 93); - nhmaster_1_i : in std_logic_vector(0 to 0); - hsize : out std_logic_vector(1 downto 0); - un7_dmain : in std_logic_vector(66 to 66); - hmaster_0 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - hgrant : in std_logic_vector(3 to 3); - iosn_0 : in std_logic_vector(93 to 93); - Ready : out std_logic; - N_1021 : in std_logic; - N_1032 : in std_logic; - N_1027 : in std_logic; - OKAY : out std_logic; - IdlePhase : out std_logic; - N_1018 : in std_logic; - N_1025 : in std_logic; - N_1042 : in std_logic; - N_1034 : in std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - N_1082 : in std_logic; - N_1048 : in std_logic; - N_1047 : in std_logic; - N_1036 : in std_logic; - N_1035 : in std_logic; - N_1019 : in std_logic; - N_1046 : in std_logic; - N_1044 : in std_logic; - N_1043 : in std_logic; - N_1041 : in std_logic; - N_1040 : in std_logic; - N_1039 : in std_logic; - N_1038 : in std_logic; - N_1033 : in std_logic; - N_1031 : in std_logic; - N_1030 : in std_logic; - N_1029 : in std_logic; - N_1028 : in std_logic; - N_1026 : in std_logic; - N_1024 : in std_logic; - N_1023 : in std_logic; - N_1022 : in std_logic; - N_1020 : in std_logic; - N_1045 : in std_logic; - Grant_0 : out std_logic; - Grant : out std_logic; - arb_1 : in std_logic; - N_1081 : in std_logic; - hbusreq_i_3 : out std_logic; - Grant_1_0 : out std_logic; - Fault : out std_logic; - time_select_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end DMA2AHB; - -architecture DEF_ARCH of DMA2AHB is - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \AddressPhase_0\, \AddressPhase_RNIGMGKAH1\, - hsize_0_sqmuxa_0, un5_ahbinhgrantx, - BoundaryPhase_2_sqmuxa_i_0_0, ReDataPhase_0_sqmuxa_i_0_0, - \ReDataPhase\, \un1_dmain_20_0\, - \hburst_11_i_a2_i_a3_0[1]\, hwrite_1_sqmuxa, - un1_AddressPhase_0_sqmuxa_1_0, - un1_AddressPhase_0_sqmuxa_1_0_0_tz, \hburst_11_0_a2_1[0]\, - un77_ahbinhgrantx, hburst_0_sqmuxa, un1_ahbin_3_0, - un1_ActivePhase, WriteAcc_m_0, \WriteAcc\, - un37_ahbinhgrantx, AddressPhase_1_sqmuxa_0, \ReAddrPhase\, - Grant_1_2, Grant_N_15, Grant_1_0_0, Grant_N_13, - Grant_m10_i_a5_1_0, Grant_m10_i_a5_0_0, - BoundaryPhase_0_sqmuxa_0, BoundaryPhase_0_sqmuxa_8_2, - BoundaryPhase_0_sqmuxa_8_1, BoundaryPhase_0_sqmuxa_6_0, - un84_ahbinhgrantx_0, un7_addressphase_0, \DataPhase\, - un46_ahbinhgrantx, AddressPhase_2_sqmuxa_0, - un84_ahbinhgrantx, N_30, hburst_2_sqmuxa_1, - \ReDataPhase_RNO\, \hsize_RNO[0]\, - BoundaryPhase_2_sqmuxa_i_0, N_343, \BoundaryPhase\, - BoundaryPhase_1_sqmuxa_1, un1_dmain_15, un78_ahbinhgrantx, - un1_dmain_20, AddressPhase_1_sqmuxa, un7_addressphase, - un23_ahbinhgrantx, un75_ahbinhgrantx, \ActivePhase\, - WriteAcc_m, BoundaryPhase_0_sqmuxa, - BoundaryPhase_0_sqmuxa_6, AddressSave_0_sqmuxa, - un1_ahbin_3, \hburst_11[0]\, \Grant_1_0\, \Grant_0\, - \EarlyPhase\, N_374, \AddressSave[20]_net_1\, - \AddressSave_4[20]\, N_382, \AddressSave[28]_net_1\, - \AddressSave_4[28]\, N_57_0, N_39, \Address_9[28]\, N_278, - \Address_RNO[28]_net_1\, \haddr[28]\, - \AddressSave_RNO[20]_net_1\, \AddressSave_RNO[28]_net_1\, - N_356, \AddressSave[2]_net_1\, \AddressSave_4[2]\, N_357, - \AddressSave[3]_net_1\, \AddressSave_4[3]\, N_359, - \AddressSave[5]_net_1\, \AddressSave_4[5]\, N_360, - \AddressSave[6]_net_1\, \AddressSave_4[6]\, N_361, - \AddressSave[7]_net_1\, \AddressSave_4[7]\, N_362, - \AddressSave[8]_net_1\, \AddressSave_4[8]\, N_363, - \AddressSave[9]_net_1\, \AddressSave_4[9]\, N_365, - \AddressSave[11]_net_1\, \AddressSave_4[11]\, N_366, - \AddressSave[12]_net_1\, \AddressSave_4[12]\, N_367, - \AddressSave[13]_net_1\, \AddressSave_4[13]\, N_368, - \AddressSave[14]_net_1\, \AddressSave_4[14]\, N_370, - \AddressSave[16]_net_1\, \AddressSave_4[16]\, N_372, - \AddressSave[18]_net_1\, \AddressSave_4[18]\, N_373, - \AddressSave[19]_net_1\, \AddressSave_4[19]\, N_375, - \AddressSave[21]_net_1\, \AddressSave_4[21]\, - hsize_0_sqmuxa, N_376, \AddressSave[22]_net_1\, - \AddressSave_4[22]\, N_377, \AddressSave[23]_net_1\, - \AddressSave_4[23]\, N_378, \AddressSave[24]_net_1\, - \AddressSave_4[24]\, N_380, \AddressSave[26]_net_1\, - \AddressSave_4[26]\, N_381, \AddressSave[27]_net_1\, - \AddressSave_4[27]\, N_383, \AddressSave[29]_net_1\, - \AddressSave_4[29]\, N_384, \AddressSave[30]_net_1\, - \AddressSave_4[30]\, N_385, \AddressSave[31]_net_1\, - \AddressSave_4[31]\, N_4, \haddr[2]\, N_6_0, \haddr[5]\, - N_5_0, N_13_0, N_15_0, N_16_0, N_19_0, N_18_0, N_23_0, - N_22_0, N_25_0, \haddr[18]\, N_26_0, \haddr[19]\, N_28_0, - N_29_0, \haddr[20]\, \haddr[21]\, N_30_0, N_32_0, - \haddr[22]\, N_33_0_i, N_37_i, N_36, \haddr[26]\, N_41, - N_42_i, N_43, \haddr[3]\, N_45, N_46, \haddr[6]\, N_84_i, - N_9_0, \haddr[9]\, N_49_0, \haddr[7]\, N_50_0, - \haddr[10]\, \haddr[11]\, N_51_0, \haddr[12]\, N_52_0, - \haddr[13]\, N_54_0, N_55_0_i, \haddr[23]\, N_56_0_i, - \haddr[27]\, N_58_0_i, \haddr[29]\, N_60_0, \haddr[30]\, - N_253, N_255, \Address_9[3]\, \Address_9[5]\, - \Address_9[6]\, N_256, \Address_9[7]\, N_257, - \Address_9[9]\, N_259, \Address_9[29]\, N_279, - \Address_RNO[3]_net_1\, \Address_RNO[5]_net_1\, - \Address_RNO[6]_net_1\, \Address_RNO[7]_net_1\, - \Address_RNO[9]_net_1\, \Address_RNO[29]_net_1\, N_261, - N_262, N_263, N_264, N_266, N_271, N_272, N_273, N_274, - N_276, N_277, \Address_9[22]\, \Address_9[23]\, - \Address_9[24]\, \Address_9[26]\, \Address_9[27]\, - \Address_9[30]\, N_280, \Address_9[31]\, N_281, - \haddr[14]\, \haddr[16]\, \AddressPhase\, \haddr[24]\, - \haddr[31]\, N_252, N_268, N_269, N_270, \Address_9[2]\, - \Address_9[11]\, \Address_9[12]\, - ReDataPhase_0_sqmuxa_i_0, \Address_9[13]\, - \Address_9[14]\, \Address_9[16]\, \Address_9[18]\, - \Address_9[19]\, \Address_9[20]\, \Address_9[21]\, - \Address_RNO[2]_net_1\, \Address_RNO[11]_net_1\, - \Address_RNO[12]_net_1\, \Address_RNO[13]_net_1\, - \Address_RNO[14]_net_1\, \Address_RNO[16]_net_1\, - \Address_RNO[18]_net_1\, \Address_RNO[19]_net_1\, - \Address_RNO[20]_net_1\, \Address_RNO[21]_net_1\, - \Address_RNO[22]_net_1\, \Address_RNO[23]_net_1\, - \Address_RNO[24]_net_1\, \Address_RNO[26]_net_1\, - \Address_RNO[27]_net_1\, \Address_RNO[30]_net_1\, - \Address_RNO[31]_net_1\, \AddressSave_RNO[6]_net_1\, - \AddressSave_RNO[7]_net_1\, \AddressSave_RNO[13]_net_1\, - \AddressSave_RNO[14]_net_1\, \AddressSave_RNO[21]_net_1\, - \AddressSave_RNO[27]_net_1\, \AddressSave_RNO[5]_net_1\, - \AddressSave_RNO[8]_net_1\, \AddressSave_RNO[12]_net_1\, - \AddressSave_RNO[19]_net_1\, \AddressSave_RNO[22]_net_1\, - \AddressSave_RNO[26]_net_1\, \AddressSave_RNO[29]_net_1\, - \AddressSave_RNO[9]_net_1\, \AddressSave_RNO[11]_net_1\, - \AddressSave_RNO[16]_net_1\, \AddressSave_RNO[18]_net_1\, - \AddressSave_RNO[23]_net_1\, \AddressSave_RNO[30]_net_1\, - \AddressSave_RNO[2]_net_1\, \AddressSave_RNO[3]_net_1\, - N_26, N_28, un45_ahbinhgrantx, un28_ahbinhgrantx_i_0, - BoundaryPhase_0_sqmuxa_1, N_422_i, \htrans_12[0]\, - \htrans_RNO_2[0]\, htrans_4_sqmuxa, hwrite_0_sqmuxa_1, - N_344, hwrite_2_sqmuxa, N_345, N_346, \SingleAcc\, - \SingleAcc_RNO\, \WriteAcc_RNO\, \ActivePhase_RNO\, - htrans_4_sqmuxa_1, htrans_1_sqmuxa, N_341, hwrite_8, - \DataPhase_RNI2ITCNO\, hwrite_RNO, - \AddressSave_RNO[17]_net_1\, N_371, - \AddressSave_RNO[25]_net_1\, N_379, - \AddressSave_RNO[1]_net_1\, N_355, - \Address_RNO[25]_net_1\, \Address_9[25]\, - \Address_RNO[17]_net_1\, \Address_9[17]\, - \Address_RNO[1]_net_1\, \Address_9[1]\, - \AddressSave[17]_net_1\, N_267, \AddressSave[1]_net_1\, - N_251, N_21_0, \AddressSave_4[25]\, \AddressSave_4[17]\, - \haddr[8]\, \AddressSave_4[1]\, \AddressSave[25]_net_1\, - N_275, N_35_i, N_258, N_83_i, \haddr[1]\, - \Address_RNO[8]_net_1\, \Address_9[8]\, \haddr[25]\, - \haddr[17]\, N_350, dataphase10, un1_redataphase21, - hburst_2_sqmuxa, data2, \IdlePhase_RNO\, Data_0_sqmuxa, - \hbusreq_i_3\, N_247, IdlePhase_net_1, N_351, - \EarlyPhase_RNO\, IdlePhase_1_sqmuxa, \Fault\, N_423_i, - N_349, \ReAddrPhase_RNO\, \AddressSave_RNO[10]_net_1\, - N_364, \AddressSave_RNO[15]_net_1\, N_369, - \Address_RNO[15]_net_1\, \Address_9[15]\, - \Address_RNO[10]_net_1\, \Address_9[10]\, - \AddressSave[15]_net_1\, N_265, \AddressSave[10]_net_1\, - N_260, N_11_0, \AddressSave_4[15]\, \AddressSave_4[10]\, - N_53_0, \haddr[15]\, N_354, \AddressSave[0]_net_1\, - \AddressSave_4[0]\, N_250, \haddr[0]\, \Address_9[0]\, - \Address_RNO[0]_net_1\, \AddressSave_RNO[0]_net_1\, - \AddressSave_RNO[4]_net_1\, N_358, \hsize_RNO[1]\, - \AddressSave_4[4]\, \haddr[4]\, \Address_RNO[4]_net_1\, - \Address_9[4]\, \AddressSave[4]_net_1\, N_254, N_44, - \hwrite\, \hsize[0]\, \hsize[1]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - hsize(1) <= \hsize[1]\; - hsize(0) <= \hsize[0]\; - haddr(31) <= \haddr[31]\; - haddr(30) <= \haddr[30]\; - haddr(29) <= \haddr[29]\; - haddr(28) <= \haddr[28]\; - haddr(27) <= \haddr[27]\; - haddr(26) <= \haddr[26]\; - haddr(25) <= \haddr[25]\; - haddr(24) <= \haddr[24]\; - haddr(23) <= \haddr[23]\; - haddr(22) <= \haddr[22]\; - haddr(21) <= \haddr[21]\; - haddr(20) <= \haddr[20]\; - haddr(19) <= \haddr[19]\; - haddr(18) <= \haddr[18]\; - haddr(17) <= \haddr[17]\; - haddr(16) <= \haddr[16]\; - haddr(15) <= \haddr[15]\; - haddr(14) <= \haddr[14]\; - haddr(13) <= \haddr[13]\; - haddr(12) <= \haddr[12]\; - haddr(11) <= \haddr[11]\; - haddr(10) <= \haddr[10]\; - haddr(9) <= \haddr[9]\; - haddr(8) <= \haddr[8]\; - haddr(7) <= \haddr[7]\; - haddr(6) <= \haddr[6]\; - haddr(5) <= \haddr[5]\; - haddr(4) <= \haddr[4]\; - haddr(3) <= \haddr[3]\; - haddr(2) <= \haddr[2]\; - haddr(1) <= \haddr[1]\; - haddr(0) <= \haddr[0]\; - IdlePhase <= IdlePhase_net_1; - hwrite <= \hwrite\; - Grant_0 <= \Grant_0\; - hbusreq_i_3 <= \hbusreq_i_3\; - Grant_1_0 <= \Grant_1_0\; - Fault <= \Fault\; - - \AHBOut.hwrite_RNO_0\ : MX2 - port map(A => hwrite_8, B => \hwrite\, S => - \DataPhase_RNI2ITCNO\, Y => N_341); - - \Address[16]\ : DFN1 - port map(D => \Address_RNO[16]_net_1\, CLK => lclk_c, Q => - \haddr[16]\); - - \Address[10]\ : DFN1 - port map(D => \Address_RNO[10]_net_1\, CLK => lclk_c, Q => - \haddr[10]\); - - \Address_RNO_1[3]\ : MX2C - port map(A => N_1020, B => N_43, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_253); - - \Address[30]\ : DFN1 - port map(D => \Address_RNO[30]_net_1\, CLK => lclk_c, Q => - \haddr[30]\); - - \AddressSave_RNO_0[30]\ : MX2 - port map(A => \AddressSave[30]_net_1\, B => - \AddressSave_4[30]\, S => hsize_0_sqmuxa, Y => N_384); - - \AddressSave[8]\ : DFN1 - port map(D => \AddressSave_RNO[8]_net_1\, CLK => lclk_c, Q - => \AddressSave[8]_net_1\); - - \Address_RNO_1[0]\ : MX2 - port map(A => Address_RNIP8BS(0), B => \haddr[0]\, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_250); - - ActivePhase_RNIEFSN : NOR2A - port map(A => \ActivePhase\, B => un46_ahbinhgrantx, Y => - hwrite_0_sqmuxa_1); - - IdlePhase_RNI439S49 : NOR3C - port map(A => Grant_N_15, B => Grant_1_0_0, C => Grant_N_13, - Y => Grant_1_2); - - \AHBOut.hsize_RNO[1]\ : OA1 - port map(A => \hsize[1]\, B => hsize_0_sqmuxa, C => rstn, Y - => \hsize_RNO[1]\); - - \Address_RNO[26]\ : NOR2A - port map(A => rstn, B => \Address_9[26]\, Y => - \Address_RNO[26]_net_1\); - - \AddressSave_RNO_0[12]\ : MX2 - port map(A => \AddressSave[12]_net_1\, B => - \AddressSave_4[12]\, S => hsize_0_sqmuxa_0, Y => N_366); - - \AddressSave_RNO_1[1]\ : MX2 - port map(A => N_1018, B => \haddr[1]\, S => \AddressPhase\, - Y => \AddressSave_4[1]\); - - un1_AddressSave_0_sqmuxa_1_m55 : AX1E - port map(A => \haddr[26]\, B => N_36, C => \haddr[27]\, Y - => N_56_0_i); - - \Address_RNO[1]\ : NOR2A - port map(A => rstn, B => \Address_9[1]\, Y => - \Address_RNO[1]_net_1\); - - DataPhase_RNI543F1 : OR2B - port map(A => \DataPhase\, B => iosn_2(93), Y => data2); - - \AddressSave_RNO_0[10]\ : MX2 - port map(A => \AddressSave[10]_net_1\, B => - \AddressSave_4[10]\, S => hsize_0_sqmuxa, Y => N_364); - - \AddressSave_RNO_0[27]\ : MX2 - port map(A => \AddressSave[27]_net_1\, B => - \AddressSave_4[27]\, S => hsize_0_sqmuxa, Y => N_381); - - \AddressSave[15]\ : DFN1 - port map(D => \AddressSave_RNO[15]_net_1\, CLK => lclk_c, Q - => \AddressSave[15]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m50 : XNOR2 - port map(A => N_13_0, B => \haddr[12]\, Y => N_51_0); - - \Address[26]\ : DFN1 - port map(D => \Address_RNO[26]_net_1\, CLK => lclk_c, Q => - \haddr[26]\); - - \Address[20]\ : DFN1 - port map(D => \Address_RNO[20]_net_1\, CLK => lclk_c, Q => - \haddr[20]\); - - ReDataPhase_RNIC49RKO : AO1D - port map(A => \ReDataPhase\, B => - un1_AddressPhase_0_sqmuxa_1_0_0_tz, C => hgrant(3), Y => - un1_AddressPhase_0_sqmuxa_1_0); - - \AddressSave[12]\ : DFN1 - port map(D => \AddressSave_RNO[12]_net_1\, CLK => lclk_c, Q - => \AddressSave[12]_net_1\); - - \AddressSave_RNO_1[16]\ : MX2A - port map(A => N_1033, B => \haddr[16]\, S => - \AddressPhase_0\, Y => \AddressSave_4[16]\); - - EarlyPhase_RNIPI2N : OR3B - port map(A => N_1081, B => un7_dmain(66), C => - un37_ahbinhgrantx, Y => un46_ahbinhgrantx); - - \Address_RNO_1[8]\ : MX2C - port map(A => N_1025, B => N_83_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_258); - - un1_dmain_20_0 : OR2B - port map(A => iosn_0(93), B => rstn, Y => \un1_dmain_20_0\); - - DataPhase_RNI6VTV1 : NOR2B - port map(A => un1_redataphase21, B => rstn, Y => - htrans_4_sqmuxa); - - BoundaryPhase_RNO : AOI1B - port map(A => N_343, B => BoundaryPhase_0_sqmuxa_1, C => - rstn, Y => N_422_i); - - un1_AddressSave_0_sqmuxa_1_m31 : NOR3C - port map(A => \haddr[22]\, B => N_29_0, C => \haddr[23]\, Y - => N_32_0); - - IdlePhase_RNO : NOR2B - port map(A => N_350, B => rstn, Y => \IdlePhase_RNO\); - - un1_AddressSave_0_sqmuxa_1_m47 : XOR2 - port map(A => N_9_0, B => \haddr[9]\, Y => N_84_i); - - \AHBOut.hsize[1]\ : DFN1 - port map(D => \hsize_RNO[1]\, CLK => lclk_c, Q => - \hsize[1]\); - - ActivePhase_RNO_2 : OR2 - port map(A => \DataPhase\, B => \AddressPhase_0\, Y => - un7_addressphase_0); - - \AHBOut.hburst_RNO_1[0]\ : OR2B - port map(A => un23_ahbinhgrantx, B => \SingleAcc\, Y => - hburst_0_sqmuxa); - - \Address_RNO_0[11]\ : MX2C - port map(A => \AddressSave[11]_net_1\, B => N_261, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[11]\); - - \Address_RNO_0[8]\ : MX2C - port map(A => \AddressSave[8]_net_1\, B => N_258, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[8]\); - - \Address_RNO_1[21]\ : MX2C - port map(A => N_1038, B => N_28_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_271); - - \AHBOut.hwrite\ : DFN1 - port map(D => hwrite_RNO, CLK => lclk_c, Q => \hwrite\); - - \Address[12]\ : DFN1 - port map(D => \Address_RNO[12]_net_1\, CLK => lclk_c, Q => - \haddr[12]\); - - \AddressSave[23]\ : DFN1 - port map(D => \AddressSave_RNO[23]_net_1\, CLK => lclk_c, Q - => \AddressSave[23]_net_1\); - - ActivePhase_RNIS76QLO : OA1 - port map(A => un84_ahbinhgrantx, B => hwrite_1_sqmuxa, C - => hburst_2_sqmuxa_1, Y => hwrite_2_sqmuxa); - - \AddressSave_RNO_0[8]\ : MX2 - port map(A => \AddressSave[8]_net_1\, B => - \AddressSave_4[8]\, S => hsize_0_sqmuxa_0, Y => N_362); - - \AddressSave_RNO_1[31]\ : MX2A - port map(A => N_1048, B => \haddr[31]\, S => \AddressPhase\, - Y => \AddressSave_4[31]\); - - \AddressSave_RNO[5]\ : NOR2B - port map(A => N_359, B => rstn, Y => - \AddressSave_RNO[5]_net_1\); - - \Address_RNO_1[11]\ : MX2C - port map(A => N_1028, B => N_50_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_261); - - \AddressSave_RNO[18]\ : NOR2B - port map(A => N_372, B => rstn, Y => - \AddressSave_RNO[18]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m41 : XNOR2 - port map(A => N_41, B => \haddr[30]\, Y => N_42_i); - - \Address_RNO[29]\ : NOR2A - port map(A => rstn, B => \Address_9[29]\, Y => - \Address_RNO[29]_net_1\); - - \AddressSave_RNO_1[28]\ : MX2A - port map(A => N_1045, B => \haddr[28]\, S => - \AddressPhase_0\, Y => \AddressSave_4[28]\); - - WriteAcc_RNO : NOR2B - port map(A => N_345, B => rstn, Y => \WriteAcc_RNO\); - - \AddressSave_RNO[11]\ : NOR2B - port map(A => N_365, B => rstn, Y => - \AddressSave_RNO[11]_net_1\); - - SingleAcc_RNO : NOR2B - port map(A => N_346, B => rstn, Y => \SingleAcc_RNO\); - - \Address[22]\ : DFN1 - port map(D => \Address_RNO[22]_net_1\, CLK => lclk_c, Q => - \haddr[22]\); - - \Address_RNO[23]\ : NOR2A - port map(A => rstn, B => \Address_9[23]\, Y => - \Address_RNO[23]_net_1\); - - \Address[2]\ : DFN1 - port map(D => \Address_RNO[2]_net_1\, CLK => lclk_c, Q => - \haddr[2]\); - - \Address_RNO_1[7]\ : MX2C - port map(A => N_1024, B => N_49_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_257); - - ReDataPhase_RNI5DK9 : OR2 - port map(A => N_1081, B => \ReDataPhase\, Y => un1_dmain_6); - - \Address_RNO[24]\ : NOR2A - port map(A => rstn, B => \Address_9[24]\, Y => - \Address_RNO[24]_net_1\); - - \Address_RNO[10]\ : NOR2A - port map(A => rstn, B => \Address_9[10]\, Y => - \Address_RNO[10]_net_1\); - - \AddressSave[20]\ : DFN1 - port map(D => \AddressSave_RNO[20]_net_1\, CLK => lclk_c, Q - => \AddressSave[20]_net_1\); - - \Address_RNO_1[30]\ : MX2C - port map(A => N_1047, B => N_42_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_280); - - \AddressSave_RNO_1[3]\ : MX2A - port map(A => N_1020, B => \haddr[3]\, S => - \AddressPhase_0\, Y => \AddressSave_4[3]\); - - \AddressSave_RNO_1[19]\ : MX2A - port map(A => N_1036, B => \haddr[19]\, S => - \AddressPhase_0\, Y => \AddressSave_4[19]\); - - ActivePhase_RNIEFSN_0 : NOR2 - port map(A => \ActivePhase\, B => un46_ahbinhgrantx, Y => - hwrite_1_sqmuxa); - - EarlyPhase_RNO_1 : OAI1 - port map(A => hgrant(3), B => un37_ahbinhgrantx, C => - un1_ahbin_3_0, Y => un1_ahbin_3); - - \AddressSave_RNO_1[24]\ : MX2A - port map(A => N_1041, B => \haddr[24]\, S => \AddressPhase\, - Y => \AddressSave_4[24]\); - - IdlePhase_RNIL9CU3 : AOI1 - port map(A => Grant_m10_i_a5_1_0, B => - hmaster_0_0_RNIFCVH1_0(1), C => \Grant_1_0\, Y => - Grant_1_0_0); - - \DMAOut.Ready_RNO\ : NOR2A - port map(A => rstn, B => data2, Y => Data_0_sqmuxa); - - \AddressSave_RNO[25]\ : NOR2B - port map(A => N_379, B => rstn, Y => - \AddressSave_RNO[25]_net_1\); - - \AddressSave_RNO_1[23]\ : MX2A - port map(A => N_1040, B => \haddr[23]\, S => \AddressPhase\, - Y => \AddressSave_4[23]\); - - \DMAOut.Grant_m10_i_a5_0_0\ : NOR2B - port map(A => hmaster_0_0_RNIFCVH1_0(1), B => bco_msb_1(1), - Y => Grant_m10_i_a5_0_0); - - \Address_RNO[9]\ : NOR2A - port map(A => rstn, B => \Address_9[9]\, Y => - \Address_RNO[9]_net_1\); - - \Address[5]\ : DFN1 - port map(D => \Address_RNO[5]_net_1\, CLK => lclk_c, Q => - \haddr[5]\); - - \AddressSave[30]\ : DFN1 - port map(D => \AddressSave_RNO[30]_net_1\, CLK => lclk_c, Q - => \AddressSave[30]_net_1\); - - AddressPhase_RNIM1LFIO : OR2A - port map(A => \AddressPhase\, B => AddressPhase_1_sqmuxa, Y - => htrans_1_sqmuxa); - - \Address[15]\ : DFN1 - port map(D => \Address_RNO[15]_net_1\, CLK => lclk_c, Q => - \haddr[15]\); - - ReAddrPhase_RNIBST1 : OR2 - port map(A => \ReDataPhase\, B => \ReAddrPhase\, Y => - un23_ahbinhgrantx); - - \AHBOut.hburst[2]\ : DFN1E0 - port map(D => N_30, CLK => lclk_c, E => - \DataPhase_RNI2ITCNO\, Q => hburst(2)); - - ActivePhase_RNI0PJVIO : OR2A - port map(A => hwrite_0_sqmuxa_1, B => hgrant(3), Y => - htrans_4_sqmuxa_1); - - \Address_RNO_0[9]\ : MX2C - port map(A => \AddressSave[9]_net_1\, B => N_259, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[9]\); - - \Address[13]\ : DFN1 - port map(D => \Address_RNO[13]_net_1\, CLK => lclk_c, Q => - \haddr[13]\); - - \AddressSave_RNO_1[15]\ : MX2A - port map(A => N_1032, B => \haddr[15]\, S => \AddressPhase\, - Y => \AddressSave_4[15]\); - - \AddressSave_RNO_1[11]\ : MX2A - port map(A => N_1028, B => \haddr[11]\, S => - \AddressPhase_0\, Y => \AddressSave_4[11]\); - - \AddressSave_RNO_0[18]\ : MX2 - port map(A => \AddressSave[18]_net_1\, B => - \AddressSave_4[18]\, S => hsize_0_sqmuxa_0, Y => N_372); - - \AddressSave[6]\ : DFN1 - port map(D => \AddressSave_RNO[6]_net_1\, CLK => lclk_c, Q - => \AddressSave[6]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m24 : AX1E - port map(A => \haddr[18]\, B => N_22_0, C => \haddr[19]\, Y - => N_25_0); - - \Address_RNO_1[4]\ : MX2C - port map(A => N_1021, B => N_44, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_254); - - \Address[19]\ : DFN1 - port map(D => \Address_RNO[19]_net_1\, CLK => lclk_c, Q => - \haddr[19]\); - - BoundaryPhase_RNO_0 : OR3B - port map(A => \BoundaryPhase\, B => - BoundaryPhase_2_sqmuxa_i_0_0, C => - BoundaryPhase_1_sqmuxa_1, Y => N_343); - - \Address[25]\ : DFN1 - port map(D => \Address_RNO[25]_net_1\, CLK => lclk_c, Q => - \haddr[25]\); - - \Address_RNIS61N1[9]\ : NOR3C - port map(A => BoundaryPhase_0_sqmuxa_6, B => - BoundaryPhase_0_sqmuxa_8_2, C => BoundaryPhase_0_sqmuxa_0, - Y => BoundaryPhase_0_sqmuxa); - - un1_AddressSave_0_sqmuxa_1_m12 : NOR3C - port map(A => \haddr[10]\, B => BoundaryPhase_0_sqmuxa, C - => \haddr[11]\, Y => N_13_0); - - \Address_RNO_0[27]\ : MX2C - port map(A => \AddressSave[27]_net_1\, B => N_277, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[27]\); - - \AddressSave_RNO[7]\ : NOR2B - port map(A => N_361, B => rstn, Y => - \AddressSave_RNO[7]_net_1\); - - \Address[23]\ : DFN1 - port map(D => \Address_RNO[23]_net_1\, CLK => lclk_c, Q => - \haddr[23]\); - - \AddressSave_RNO_1[7]\ : MX2A - port map(A => N_1024, B => \haddr[7]\, S => - \AddressPhase_0\, Y => \AddressSave_4[7]\); - - \AHBOut.htrans[1]\ : DFN1E0 - port map(D => un1_dmain_20, CLK => lclk_c, E => - htrans_4_sqmuxa, Q => htrans(1)); - - WriteAcc_RNO_0 : MX2 - port map(A => \WriteAcc\, B => N_1082, S => hwrite_2_sqmuxa, - Y => N_345); - - \AddressSave_RNO[29]\ : NOR2B - port map(A => N_383, B => rstn, Y => - \AddressSave_RNO[29]_net_1\); - - \AddressSave_RNO_0[14]\ : MX2 - port map(A => \AddressSave[14]_net_1\, B => - \AddressSave_4[14]\, S => hsize_0_sqmuxa_0, Y => N_368); - - \Address[29]\ : DFN1 - port map(D => \Address_RNO[29]_net_1\, CLK => lclk_c, Q => - \haddr[29]\); - - ReDataPhase_RNIQF9GJO_0 : OR3B - port map(A => \ReDataPhase\, B => iosn_1(93), C => - hgrant(3), Y => ReDataPhase_0_sqmuxa_i_0); - - \Address[18]\ : DFN1 - port map(D => \Address_RNO[18]_net_1\, CLK => lclk_c, Q => - \haddr[18]\); - - \AddressSave_RNO[10]\ : NOR2B - port map(A => N_364, B => rstn, Y => - \AddressSave_RNO[10]_net_1\); - - \AddressSave[16]\ : DFN1 - port map(D => \AddressSave_RNO[16]_net_1\, CLK => lclk_c, Q - => \AddressSave[16]_net_1\); - - \AddressSave_RNO_1[26]\ : MX2A - port map(A => N_1043, B => \haddr[26]\, S => \AddressPhase\, - Y => \AddressSave_4[26]\); - - \AddressSave_RNO_0[13]\ : MX2 - port map(A => \AddressSave[13]_net_1\, B => - \AddressSave_4[13]\, S => hsize_0_sqmuxa_0, Y => N_367); - - ActivePhase_RNO : NOR2B - port map(A => N_344, B => rstn, Y => \ActivePhase_RNO\); - - \Address_RNO[21]\ : NOR2A - port map(A => rstn, B => \Address_9[21]\, Y => - \Address_RNO[21]_net_1\); - - \Address_RNO[16]\ : NOR2A - port map(A => rstn, B => \Address_9[16]\, Y => - \Address_RNO[16]_net_1\); - - \Address_RNO_0[30]\ : MX2C - port map(A => \AddressSave[30]_net_1\, B => N_280, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[30]\); - - \Address_RNO_0[24]\ : MX2C - port map(A => \AddressSave[24]_net_1\, B => N_274, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[24]\); - - ActivePhase_RNIE4351 : OR2A - port map(A => un75_ahbinhgrantx, B => un45_ahbinhgrantx, Y - => un77_ahbinhgrantx); - - \Address_RNO_0[25]\ : MX2C - port map(A => \AddressSave[25]_net_1\, B => N_275, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[25]\); - - \Address[0]\ : DFN1 - port map(D => \Address_RNO[0]_net_1\, CLK => lclk_c, Q => - \haddr[0]\); - - \AddressSave_RNO[22]\ : NOR2B - port map(A => N_376, B => rstn, Y => - \AddressSave_RNO[22]_net_1\); - - BoundaryPhase_RNO_1 : OR2A - port map(A => BoundaryPhase_0_sqmuxa, B => - BoundaryPhase_1_sqmuxa_1, Y => BoundaryPhase_0_sqmuxa_1); - - GND_i : GND - port map(Y => \GND\); - - \AddressSave_RNO_0[6]\ : MX2 - port map(A => \AddressSave[6]_net_1\, B => - \AddressSave_4[6]\, S => hsize_0_sqmuxa_0, Y => N_360); - - \AHBOut.hburst_RNO_0[0]\ : NOR3C - port map(A => un77_ahbinhgrantx, B => hburst_0_sqmuxa, C - => \Fault\, Y => \hburst_11_0_a2_1[0]\); - - DataPhase_RNI2ITCNO : OA1 - port map(A => hburst_2_sqmuxa, B => un1_redataphase21, C - => rstn, Y => \DataPhase_RNI2ITCNO\); - - \AddressSave_RNO[16]\ : NOR2B - port map(A => N_370, B => rstn, Y => - \AddressSave_RNO[16]_net_1\); - - \Address_RNO[27]\ : NOR2A - port map(A => rstn, B => \Address_9[27]\, Y => - \Address_RNO[27]_net_1\); - - \Address[4]\ : DFN1 - port map(D => \Address_RNO[4]_net_1\, CLK => lclk_c, Q => - \haddr[4]\); - - \Address[28]\ : DFN1 - port map(D => \Address_RNO[28]_net_1\, CLK => lclk_c, Q => - \haddr[28]\); - - \AddressSave_RNO[23]\ : NOR2B - port map(A => N_377, B => rstn, Y => - \AddressSave_RNO[23]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m49 : AX1E - port map(A => \haddr[10]\, B => BoundaryPhase_0_sqmuxa, C - => \haddr[11]\, Y => N_50_0); - - un1_AddressSave_0_sqmuxa_1_m35 : NOR3C - port map(A => \haddr[24]\, B => N_32_0, C => \haddr[25]\, Y - => N_36); - - \Address_RNO_0[3]\ : MX2C - port map(A => \AddressSave[3]_net_1\, B => N_253, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un1_AddressSave_0_sqmuxa_1_m52 : AX1E - port map(A => \haddr[14]\, B => N_15_0, C => \haddr[15]\, Y - => N_53_0); - - EarlyPhase : DFN1 - port map(D => \EarlyPhase_RNO\, CLK => lclk_c, Q => - \EarlyPhase\); - - \Address_RNO_1[31]\ : MX2C - port map(A => N_1048, B => N_60_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_281); - - \Address_RNIL8G2[4]\ : NOR2B - port map(A => \haddr[4]\, B => \haddr[5]\, Y => - BoundaryPhase_0_sqmuxa_8_1); - - \AddressSave_RNO[4]\ : NOR2B - port map(A => N_358, B => rstn, Y => - \AddressSave_RNO[4]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m18 : XNOR2 - port map(A => N_18_0, B => \haddr[16]\, Y => N_19_0); - - \Address_RNO_0[4]\ : MX2C - port map(A => \AddressSave[4]_net_1\, B => N_254, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[4]\); - - \Address_RNO_0[5]\ : MX2C - port map(A => \AddressSave[5]_net_1\, B => N_255, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[5]\); - - \AHBOut.hsize[0]\ : DFN1 - port map(D => \hsize_RNO[0]\, CLK => lclk_c, Q => - \hsize[0]\); - - \Address_RNO_0[17]\ : MX2C - port map(A => \AddressSave[17]_net_1\, B => N_267, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[17]\); - - \AddressSave_RNO_1[2]\ : MX2A - port map(A => N_1019, B => \haddr[2]\, S => - \AddressPhase_0\, Y => \AddressSave_4[2]\); - - ReAddrPhase_RNO : NOR2B - port map(A => N_349, B => rstn, Y => \ReAddrPhase_RNO\); - - \AddressSave_RNO_1[17]\ : MX2A - port map(A => N_1034, B => \haddr[17]\, S => \AddressPhase\, - Y => \AddressSave_4[17]\); - - \Address_RNO_1[27]\ : MX2C - port map(A => N_1044, B => N_56_0_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_277); - - un1_AddressSave_0_sqmuxa_1_m45 : XNOR2 - port map(A => N_6_0, B => \haddr[6]\, Y => N_46); - - \Address_RNO[19]\ : NOR2A - port map(A => rstn, B => \Address_9[19]\, Y => - \Address_RNO[19]_net_1\); - - \AddressSave_RNO_0[16]\ : MX2 - port map(A => \AddressSave[16]_net_1\, B => - \AddressSave_4[16]\, S => hsize_0_sqmuxa_0, Y => N_370); - - \Address_RNO_1[17]\ : MX2C - port map(A => N_1034, B => N_21_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_267); - - \AHBOut.hburst[0]\ : DFN1E0 - port map(D => \hburst_11[0]\, CLK => lclk_c, E => - \DataPhase_RNI2ITCNO\, Q => hburst(0)); - - \AddressSave[9]\ : DFN1 - port map(D => \AddressSave_RNO[9]_net_1\, CLK => lclk_c, Q - => \AddressSave[9]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m40 : NOR3C - port map(A => \haddr[28]\, B => N_39, C => \haddr[29]\, Y - => N_41); - - \AddressSave_RNO_1[29]\ : MX2A - port map(A => N_1046, B => \haddr[29]\, S => \AddressPhase\, - Y => \AddressSave_4[29]\); - - \AddressSave_RNO[2]\ : NOR2B - port map(A => N_356, B => rstn, Y => - \AddressSave_RNO[2]_net_1\); - - \Address_RNO[13]\ : NOR2A - port map(A => rstn, B => \Address_9[13]\, Y => - \Address_RNO[13]_net_1\); - - \Address_RNO_0[14]\ : MX2C - port map(A => \AddressSave[14]_net_1\, B => N_264, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[14]\); - - \Address[14]\ : DFN1 - port map(D => \Address_RNO[14]_net_1\, CLK => lclk_c, Q => - \haddr[14]\); - - \AddressSave[29]\ : DFN1 - port map(D => \AddressSave_RNO[29]_net_1\, CLK => lclk_c, Q - => \AddressSave[29]_net_1\); - - \Address_RNO_0[15]\ : MX2C - port map(A => \AddressSave[15]_net_1\, B => N_265, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[15]\); - - \Address_RNO_1[24]\ : MX2C - port map(A => N_1041, B => N_33_0_i, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_274); - - \AddressSave_RNO_0[1]\ : MX2 - port map(A => \AddressSave[1]_net_1\, B => - \AddressSave_4[1]\, S => hsize_0_sqmuxa, Y => N_355); - - \Address_RNO_1[25]\ : MX2C - port map(A => N_1042, B => N_35_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_275); - - \Address_RNO[14]\ : NOR2A - port map(A => rstn, B => \Address_9[14]\, Y => - \Address_RNO[14]_net_1\); - - AddressPhase_0_RNI040D1 : OR2B - port map(A => \AddressPhase_0\, B => iosn_1(93), Y => - AddressSave_0_sqmuxa); - - \Address_RNO_1[14]\ : MX2C - port map(A => N_1031, B => N_16_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_264); - - ReAddrPhase_RNIT5L9IO : OR2A - port map(A => AddressPhase_1_sqmuxa_0, B => hgrant(3), Y - => AddressPhase_1_sqmuxa); - - \Address_RNO_1[15]\ : MX2C - port map(A => N_1032, B => N_53_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_265); - - \AddressSave[11]\ : DFN1 - port map(D => \AddressSave_RNO[11]_net_1\, CLK => lclk_c, Q - => \AddressSave[11]_net_1\); - - \AddressSave_RNO_1[25]\ : MX2A - port map(A => N_1042, B => \haddr[25]\, S => \AddressPhase\, - Y => \AddressSave_4[25]\); - - \AddressSave_RNO_1[21]\ : MX2A - port map(A => N_1038, B => \haddr[21]\, S => \AddressPhase\, - Y => \AddressSave_4[21]\); - - ActivePhase_RNILH0E : OR3B - port map(A => un7_dmain(66), B => \ActivePhase\, C => - N_1081, Y => un75_ahbinhgrantx); - - \Address[24]\ : DFN1 - port map(D => \Address_RNO[24]_net_1\, CLK => lclk_c, Q => - \haddr[24]\); - - \Address_RNO_0[22]\ : MX2C - port map(A => \AddressSave[22]_net_1\, B => N_272, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[22]\); - - ReAddrPhase_RNI4EHJ1 : OR2B - port map(A => \Grant_0\, B => iosn_0(93), Y => \Grant_1_0\); - - \AddressSave[1]\ : DFN1 - port map(D => \AddressSave_RNO[1]_net_1\, CLK => lclk_c, Q - => \AddressSave[1]_net_1\); - - \AHBOut.hwrite_RNO\ : NOR2B - port map(A => N_341, B => rstn, Y => hwrite_RNO); - - VCC_i : VCC - port map(Y => \VCC\); - - \Address_RNO_0[31]\ : MX2C - port map(A => \AddressSave[31]_net_1\, B => N_281, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[31]\); - - AddressPhase_RNI4GHN6H1 : AOI1B - port map(A => htrans_4_sqmuxa_1, B => htrans_1_sqmuxa, C - => iosn_1(93), Y => BoundaryPhase_1_sqmuxa_1); - - \AddressSave[25]\ : DFN1 - port map(D => \AddressSave_RNO[25]_net_1\, CLK => lclk_c, Q - => \AddressSave[25]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m27 : AX1E - port map(A => \haddr[20]\, B => N_26_0, C => \haddr[21]\, Y - => N_28_0); - - \AddressSave[22]\ : DFN1 - port map(D => \AddressSave_RNO[22]_net_1\, CLK => lclk_c, Q - => \AddressSave[22]_net_1\); - - ReAddrPhase_RNIMO8B : NOR2A - port map(A => N_1081, B => un23_ahbinhgrantx, Y => - \Grant_0\); - - \AddressSave_RNO_0[19]\ : MX2 - port map(A => \AddressSave[19]_net_1\, B => - \AddressSave_4[19]\, S => hsize_0_sqmuxa_0, Y => N_373); - - ActivePhase_RNII2SHIO : OR3A - port map(A => N_1081, B => \ActivePhase\, C => hgrant(3), Y - => un5_ahbinhgrantx); - - \AddressSave_RNO_0[31]\ : MX2 - port map(A => \AddressSave[31]_net_1\, B => - \AddressSave_4[31]\, S => hsize_0_sqmuxa, Y => N_385); - - \AddressSave_RNO[1]\ : NOR2B - port map(A => N_355, B => rstn, Y => - \AddressSave_RNO[1]_net_1\); - - \Address[8]\ : DFN1 - port map(D => \Address_RNO[8]_net_1\, CLK => lclk_c, Q => - \haddr[8]\); - - \Address_RNO_0[1]\ : MX2C - port map(A => \AddressSave[1]_net_1\, B => N_251, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[1]\); - - un1_AddressSave_0_sqmuxa_1_m21 : NOR3C - port map(A => \haddr[16]\, B => N_18_0, C => \haddr[17]\, Y - => N_22_0); - - BoundaryPhase : DFN1 - port map(D => N_422_i, CLK => lclk_c, Q => \BoundaryPhase\); - - \AddressSave_RNO_0[7]\ : MX2 - port map(A => \AddressSave[7]_net_1\, B => - \AddressSave_4[7]\, S => hsize_0_sqmuxa_0, Y => N_361); - - \AddressSave_RNO[24]\ : NOR2B - port map(A => N_378, B => rstn, Y => N_26); - - \DMAOut.Grant_m10_i_a5\ : OR2 - port map(A => hmaster_0(1), B => arb_1, Y => Grant_N_13); - - \AHBOut.htrans_RNO_0[0]\ : OR3C - port map(A => rstn, B => un78_ahbinhgrantx, C => - hburst_2_sqmuxa_1, Y => un1_dmain_15); - - \Address_RNIH8G2[3]\ : OR2B - port map(A => \haddr[3]\, B => \haddr[2]\, Y => - BoundaryPhase_0_sqmuxa_6_0); - - \AddressSave_RNO_1[9]\ : MX2A - port map(A => N_1026, B => \haddr[9]\, S => - \AddressPhase_0\, Y => \AddressSave_4[9]\); - - \AHBOut.hwrite_RNO_3\ : NOR2B - port map(A => \WriteAcc\, B => un37_ahbinhgrantx, Y => - WriteAcc_m_0); - - \Address_RNO[6]\ : NOR2A - port map(A => rstn, B => \Address_9[6]\, Y => - \Address_RNO[6]_net_1\); - - \IdlePhase\ : DFN1 - port map(D => \IdlePhase_RNO\, CLK => lclk_c, Q => - IdlePhase_net_1); - - AddressPhase_0_RNII6SUJO_1 : OA1A - port map(A => un5_ahbinhgrantx, B => \AddressPhase_0\, C - => iosn_0(93), Y => hsize_0_sqmuxa_0); - - \AddressSave_RNO_0[15]\ : MX2 - port map(A => \AddressSave[15]_net_1\, B => - \AddressSave_4[15]\, S => hsize_0_sqmuxa, Y => N_369); - - \AddressSave_RNO_0[11]\ : MX2 - port map(A => \AddressSave[11]_net_1\, B => - \AddressSave_4[11]\, S => hsize_0_sqmuxa_0, Y => N_365); - - ReAddrPhase : DFN1 - port map(D => \ReAddrPhase_RNO\, CLK => lclk_c, Q => - \ReAddrPhase\); - - \Address_RNO[28]\ : NOR2A - port map(A => rstn, B => \Address_9[28]\, Y => - \Address_RNO[28]_net_1\); - - \Address_RNO[11]\ : NOR2A - port map(A => rstn, B => \Address_9[11]\, Y => - \Address_RNO[11]_net_1\); - - \Address_RNO_0[12]\ : MX2C - port map(A => \AddressSave[12]_net_1\, B => N_262, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[12]\); - - \AddressSave_RNO_1[5]\ : MX2A - port map(A => N_1022, B => \haddr[5]\, S => - \AddressPhase_0\, Y => \AddressSave_4[5]\); - - DataPhase_RNO_0 : OR2A - port map(A => dataphase10, B => hresp(0), Y => - IdlePhase_1_sqmuxa); - - ReAddrPhase_RNIBST1_0 : NOR2A - port map(A => \ReAddrPhase\, B => \ReDataPhase\, Y => - AddressPhase_1_sqmuxa_0); - - \Address_RNO_1[22]\ : MX2C - port map(A => N_1039, B => N_30_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_272); - - ActivePhase_RNIEP9I1 : NOR2 - port map(A => un84_ahbinhgrantx_0, B => un77_ahbinhgrantx, - Y => un84_ahbinhgrantx); - - \Address_RNO[17]\ : NOR2A - port map(A => rstn, B => \Address_9[17]\, Y => - \Address_RNO[17]_net_1\); - - \AddressSave_RNO_0[0]\ : MX2 - port map(A => \AddressSave[0]_net_1\, B => - \AddressSave_4[0]\, S => hsize_0_sqmuxa, Y => N_354); - - \AddressSave_RNO[31]\ : NOR2B - port map(A => N_385, B => rstn, Y => N_28); - - \Address_RNO[5]\ : NOR2A - port map(A => rstn, B => \Address_9[5]\, Y => - \Address_RNO[5]_net_1\); - - \AddressSave[17]\ : DFN1 - port map(D => \AddressSave_RNO[17]_net_1\, CLK => lclk_c, Q - => \AddressSave[17]_net_1\); - - \Address_RNO_1[12]\ : MX2C - port map(A => N_1029, B => N_51_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_262); - - \AddressSave_RNO_1[27]\ : MX2A - port map(A => N_1044, B => \haddr[27]\, S => \AddressPhase\, - Y => \AddressSave_4[27]\); - - \AddressSave_RNO[15]\ : NOR2B - port map(A => N_369, B => rstn, Y => - \AddressSave_RNO[15]_net_1\); - - \AddressSave[4]\ : DFN1 - port map(D => \AddressSave_RNO[4]_net_1\, CLK => lclk_c, Q - => \AddressSave[4]_net_1\); - - \AddressSave[14]\ : DFN1 - port map(D => \AddressSave_RNO[14]_net_1\, CLK => lclk_c, Q - => \AddressSave[14]_net_1\); - - \Address_RNO[0]\ : NOR2A - port map(A => rstn, B => \Address_9[0]\, Y => - \Address_RNO[0]_net_1\); - - ActivePhase : DFN1 - port map(D => \ActivePhase_RNO\, CLK => lclk_c, Q => - \ActivePhase\); - - ReAddrPhase_RNO_0 : OA1A - port map(A => iosn_2(93), B => AddressPhase_1_sqmuxa, C => - \ReAddrPhase\, Y => N_349); - - \AddressSave[7]\ : DFN1 - port map(D => \AddressSave_RNO[7]_net_1\, CLK => lclk_c, Q - => \AddressSave[7]_net_1\); - - \DMAOut.Grant_m10_i_a5_0\ : OR2B - port map(A => Grant_m10_i_a5_0_0, B => arb_1, Y => - Grant_N_15); - - \Address_RNO_0[2]\ : MX2C - port map(A => \AddressSave[2]_net_1\, B => N_252, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[2]\); - - \AddressSave_RNO_0[22]\ : MX2 - port map(A => \AddressSave[22]_net_1\, B => - \AddressSave_4[22]\, S => hsize_0_sqmuxa, Y => N_376); - - un1_AddressSave_0_sqmuxa_1_m14 : NOR3C - port map(A => \haddr[12]\, B => N_13_0, C => \haddr[13]\, Y - => N_15_0); - - \AHBOut.hburst_2_sqmuxa_1\ : NOR2A - port map(A => iosn_2(93), B => hgrant(3), Y => - hburst_2_sqmuxa_1); - - \Address_RNO[3]\ : NOR2A - port map(A => rstn, B => \Address_9[3]\, Y => - \Address_RNO[3]_net_1\); - - EarlyPhase_RNIPTR9 : OR2 - port map(A => un23_ahbinhgrantx, B => \EarlyPhase\, Y => - un37_ahbinhgrantx); - - \Address[3]\ : DFN1 - port map(D => \Address_RNO[3]_net_1\, CLK => lclk_c, Q => - \haddr[3]\); - - \AddressSave_RNO_1[6]\ : MX2A - port map(A => N_1023, B => \haddr[6]\, S => - \AddressPhase_0\, Y => \AddressSave_4[6]\); - - ActivePhase_RNO_1 : NOR3 - port map(A => un7_addressphase_0, B => un23_ahbinhgrantx, C - => un7_dmain(66), Y => un7_addressphase); - - un1_AddressSave_0_sqmuxa_1_m32 : XNOR2 - port map(A => N_32_0, B => \haddr[24]\, Y => N_33_0_i); - - \AddressSave_RNO_0[20]\ : MX2 - port map(A => \AddressSave[20]_net_1\, B => - \AddressSave_4[20]\, S => hsize_0_sqmuxa_0, Y => N_374); - - \AddressSave_RNO[0]\ : NOR2B - port map(A => N_354, B => rstn, Y => - \AddressSave_RNO[0]_net_1\); - - \Address_RNO_1[2]\ : MX2C - port map(A => N_1019, B => N_4, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_252); - - \Address_RNO[30]\ : NOR2A - port map(A => rstn, B => \Address_9[30]\, Y => - \Address_RNO[30]_net_1\); - - \AddressSave[0]\ : DFN1 - port map(D => \AddressSave_RNO[0]_net_1\, CLK => lclk_c, Q - => \AddressSave[0]_net_1\); - - AddressPhase : DFN1 - port map(D => \AddressPhase_RNIGMGKAH1\, CLK => lclk_c, Q - => \AddressPhase\); - - \AddressSave_RNO_0[5]\ : MX2 - port map(A => \AddressSave[5]_net_1\, B => - \AddressSave_4[5]\, S => hsize_0_sqmuxa_0, Y => N_359); - - \AddressSave_RNO[3]\ : NOR2B - port map(A => N_357, B => rstn, Y => - \AddressSave_RNO[3]_net_1\); - - ActivePhase_RNIE4351_0 : NOR2 - port map(A => un75_ahbinhgrantx, B => un45_ahbinhgrantx, Y - => un78_ahbinhgrantx); - - IdlePhase_RNI2FRO : NOR2A - port map(A => \hbusreq_i_3\, B => hmaster_0(1), Y => - Grant_m10_i_a5_1_0); - - \AddressSave_RNO[19]\ : NOR2B - port map(A => N_373, B => rstn, Y => - \AddressSave_RNO[19]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m42 : AX1A - port map(A => AddressSave_0_sqmuxa, B => \haddr[2]\, C => - \haddr[3]\, Y => N_43); - - \Address_RNO_0[6]\ : MX2C - port map(A => \AddressSave[6]_net_1\, B => N_256, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[6]\); - - AddressPhase_0_RNII6SUJO : OR3A - port map(A => iosn_0(93), B => \AddressPhase_0\, C => - un5_ahbinhgrantx, Y => BoundaryPhase_2_sqmuxa_i_0_0); - - \AddressSave_RNO_0[17]\ : MX2 - port map(A => \AddressSave[17]_net_1\, B => - \AddressSave_4[17]\, S => hsize_0_sqmuxa, Y => N_371); - - \Address[7]\ : DFN1 - port map(D => \Address_RNO[7]_net_1\, CLK => lclk_c, Q => - \haddr[7]\); - - un1_AddressSave_0_sqmuxa_1_m1 : XOR2 - port map(A => AddressSave_0_sqmuxa, B => \haddr[2]\, Y => - N_4); - - \Address_RNO_0[28]\ : MX2C - port map(A => \AddressSave[28]_net_1\, B => N_278, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[28]\); - - \AddressSave_RNO[27]\ : NOR2B - port map(A => N_381, B => rstn, Y => - \AddressSave_RNO[27]_net_1\); - - \AddressSave_RNO[12]\ : NOR2B - port map(A => N_366, B => rstn, Y => - \AddressSave_RNO[12]_net_1\); - - \AddressSave[26]\ : DFN1 - port map(D => \AddressSave_RNO[26]_net_1\, CLK => lclk_c, Q - => \AddressSave[26]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m54 : AX1E - port map(A => \haddr[22]\, B => N_29_0, C => \haddr[23]\, Y - => N_55_0_i); - - un1_AddressSave_0_sqmuxa_1_m53 : XNOR2 - port map(A => N_26_0, B => \haddr[20]\, Y => N_54_0); - - \DMAOut.Ready\ : DFN1 - port map(D => Data_0_sqmuxa, CLK => lclk_c, Q => Ready); - - \AddressSave[18]\ : DFN1 - port map(D => \AddressSave_RNO[18]_net_1\, CLK => lclk_c, Q - => \AddressSave[18]_net_1\); - - \AddressSave_RNO[30]\ : NOR2B - port map(A => N_384, B => rstn, Y => - \AddressSave_RNO[30]_net_1\); - - \AddressSave_RNO[13]\ : NOR2B - port map(A => N_367, B => rstn, Y => - \AddressSave_RNO[13]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m29 : XNOR2 - port map(A => N_29_0, B => \haddr[22]\, Y => N_30_0); - - IdlePhase_RNIKJKM : OR2 - port map(A => N_247, B => IdlePhase_net_1, Y => - \hbusreq_i_3\); - - \Address_RNIT8G2[9]\ : NOR2B - port map(A => \haddr[9]\, B => \haddr[8]\, Y => - BoundaryPhase_0_sqmuxa_0); - - un1_AddressSave_0_sqmuxa_1_m38 : NOR3C - port map(A => \haddr[26]\, B => N_36, C => \haddr[27]\, Y - => N_39); - - \Address_RNO_0[26]\ : MX2C - port map(A => \AddressSave[26]_net_1\, B => N_276, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[26]\); - - WriteAcc : DFN1 - port map(D => \WriteAcc_RNO\, CLK => lclk_c, Q => - \WriteAcc\); - - EarlyPhase_RNO_0 : MX2 - port map(A => hgrant(3), B => \EarlyPhase\, S => - un1_ahbin_3, Y => N_351); - - \AddressSave_RNO_0[3]\ : MX2 - port map(A => \AddressSave[3]_net_1\, B => - \AddressSave_4[3]\, S => hsize_0_sqmuxa_0, Y => N_357); - - ActivePhase_RNICD7U : NOR2A - port map(A => hwrite_1_sqmuxa, B => time_select_0, Y => - \hburst_11_i_a2_i_a3_0[1]\); - - \Address_RNO_0[29]\ : MX2C - port map(A => \AddressSave[29]_net_1\, B => N_279, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[29]\); - - un1_AddressSave_0_sqmuxa_1_m56 : XNOR2 - port map(A => N_39, B => \haddr[28]\, Y => N_57_0); - - un1_AddressSave_0_sqmuxa_1_m25 : NOR3C - port map(A => \haddr[18]\, B => N_22_0, C => \haddr[19]\, Y - => N_26_0); - - un1_AddressSave_0_sqmuxa_1_m5 : NOR2A - port map(A => \haddr[5]\, B => N_5_0, Y => N_6_0); - - un1_AddressSave_0_sqmuxa_1_m48 : AX1E - port map(A => \haddr[6]\, B => N_6_0, C => \haddr[7]\, Y - => N_49_0); - - \Address_RNIEH05[7]\ : NOR3C - port map(A => \haddr[7]\, B => \haddr[6]\, C => - BoundaryPhase_0_sqmuxa_8_1, Y => - BoundaryPhase_0_sqmuxa_8_2); - - un1_AddressSave_0_sqmuxa_1_m20 : AX1E - port map(A => \haddr[16]\, B => N_18_0, C => \haddr[17]\, Y - => N_21_0); - - EarlyPhase_RNO_2 : AOI1B - port map(A => un1_ActivePhase, B => hgrant(3), C => - iosn_0(93), Y => un1_ahbin_3_0); - - \AHBOut.htrans_RNO_1[0]\ : OR2 - port map(A => BoundaryPhase_0_sqmuxa, B => \BoundaryPhase\, - Y => un28_ahbinhgrantx_i_0); - - \Address_RNO[22]\ : NOR2A - port map(A => rstn, B => \Address_9[22]\, Y => - \Address_RNO[22]_net_1\); - - \Address[9]\ : DFN1 - port map(D => \Address_RNO[9]_net_1\, CLK => lclk_c, Q => - \haddr[9]\); - - DataPhase_RNO : AOI1B - port map(A => IdlePhase_1_sqmuxa, B => AddressSave_0_sqmuxa, - C => rstn, Y => N_423_i); - - \Address_RNO[18]\ : NOR2A - port map(A => rstn, B => \Address_9[18]\, Y => - \Address_RNO[18]_net_1\); - - ReDataPhase_RNIQF9GJO : OR3B - port map(A => \ReDataPhase\, B => iosn_0(93), C => - hgrant(3), Y => ReDataPhase_0_sqmuxa_i_0_0); - - DataPhase_RNIC3IU1_0 : NOR2 - port map(A => data2, B => hresp(0), Y => OKAY); - - \Address_RNO_0[18]\ : MX2C - port map(A => \AddressSave[18]_net_1\, B => N_268, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[18]\); - - \AddressSave_RNO_0[28]\ : MX2 - port map(A => \AddressSave[28]_net_1\, B => - \AddressSave_4[28]\, S => hsize_0_sqmuxa_0, Y => N_382); - - GND_i_0 : GND - port map(Y => GND_0); - - AddressPhase_RNIPJ40KO : OA1A - port map(A => un5_ahbinhgrantx, B => \AddressPhase\, C => - iosn_1(93), Y => hsize_0_sqmuxa); - - \Address_RNO[7]\ : NOR2A - port map(A => rstn, B => \Address_9[7]\, Y => - \Address_RNO[7]_net_1\); - - \Address_RNO_1[28]\ : MX2C - port map(A => N_1045, B => N_57_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_278); - - \Address_RNO_0[7]\ : MX2C - port map(A => \AddressSave[7]_net_1\, B => N_257, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[7]\); - - SingleAcc : DFN1 - port map(D => \SingleAcc_RNO\, CLK => lclk_c, Q => - \SingleAcc\); - - \AddressSave_RNO_0[4]\ : MX2 - port map(A => \AddressSave[4]_net_1\, B => - \AddressSave_4[4]\, S => hsize_0_sqmuxa, Y => N_358); - - \Address_RNO_1[18]\ : MX2C - port map(A => N_1035, B => N_23_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_268); - - \Address[6]\ : DFN1 - port map(D => \Address_RNO[6]_net_1\, CLK => lclk_c, Q => - \haddr[6]\); - - \AddressSave_RNO_1[30]\ : MX2A - port map(A => N_1047, B => \haddr[30]\, S => \AddressPhase\, - Y => \AddressSave_4[30]\); - - \AddressSave_RNO[9]\ : NOR2B - port map(A => N_363, B => rstn, Y => - \AddressSave_RNO[9]_net_1\); - - EarlyPhase_RNO_3 : OAI1 - port map(A => N_1081, B => un7_dmain(66), C => - \ActivePhase\, Y => un1_ActivePhase); - - \AHBMaster.un84_ahbinhgrantx_0\ : OR2A - port map(A => N_1081, B => un7_dmain(66), Y => - un84_ahbinhgrantx_0); - - \Address_RNO_0[16]\ : MX2C - port map(A => \AddressSave[16]_net_1\, B => N_266, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[16]\); - - \AddressSave_RNO_1[0]\ : MX2 - port map(A => Address_RNIP8BS(0), B => \haddr[0]\, S => - \AddressPhase\, Y => \AddressSave_4[0]\); - - \Address_RNO[8]\ : NOR2A - port map(A => rstn, B => \Address_9[8]\, Y => - \Address_RNO[8]_net_1\); - - \AddressSave_RNO_0[24]\ : MX2 - port map(A => \AddressSave[24]_net_1\, B => - \AddressSave_4[24]\, S => hsize_0_sqmuxa, Y => N_378); - - \AddressSave[21]\ : DFN1 - port map(D => \AddressSave_RNO[21]_net_1\, CLK => lclk_c, Q - => \AddressSave[21]_net_1\); - - \Address_RNO_1[26]\ : MX2C - port map(A => N_1043, B => N_37_i, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_276); - - \AddressSave_RNO_0[9]\ : MX2 - port map(A => \AddressSave[9]_net_1\, B => - \AddressSave_4[9]\, S => hsize_0_sqmuxa_0, Y => N_363); - - ActivePhase_RNISIVCLO : OA1 - port map(A => un78_ahbinhgrantx, B => hwrite_0_sqmuxa_1, C - => hburst_2_sqmuxa_1, Y => hburst_2_sqmuxa); - - un1_AddressSave_0_sqmuxa_1_m17 : NOR3C - port map(A => \haddr[14]\, B => N_15_0, C => \haddr[15]\, Y - => N_18_0); - - \AHBOut.htrans_RNO_2[0]\ : NOR2B - port map(A => BoundaryPhase_1_sqmuxa_1, B => rstn, Y => - \htrans_RNO_2[0]\); - - \AddressSave_RNO_0[23]\ : MX2 - port map(A => \AddressSave[23]_net_1\, B => - \AddressSave_4[23]\, S => hsize_0_sqmuxa, Y => N_377); - - SingleAcc_RNO_0 : MX2 - port map(A => \SingleAcc\, B => un84_ahbinhgrantx, S => - hwrite_2_sqmuxa, Y => N_346); - - \Address_RNO_1[16]\ : MX2C - port map(A => N_1033, B => N_19_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_266); - - \Address_RNO_0[19]\ : MX2C - port map(A => \AddressSave[19]_net_1\, B => N_269, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[19]\); - - \Address[11]\ : DFN1 - port map(D => \Address_RNO[11]_net_1\, CLK => lclk_c, Q => - \haddr[11]\); - - \AddressSave[31]\ : DFN1 - port map(D => N_28, CLK => lclk_c, Q => - \AddressSave[31]_net_1\); - - \Address[31]\ : DFN1 - port map(D => \Address_RNO[31]_net_1\, CLK => lclk_c, Q => - \haddr[31]\); - - \Address_RNO_1[29]\ : MX2C - port map(A => N_1046, B => N_58_0_i, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_279); - - \AddressSave_RNO_0[2]\ : MX2 - port map(A => \AddressSave[2]_net_1\, B => - \AddressSave_4[2]\, S => hsize_0_sqmuxa_0, Y => N_356); - - \AddressSave[13]\ : DFN1 - port map(D => \AddressSave_RNO[13]_net_1\, CLK => lclk_c, Q - => \AddressSave[13]_net_1\); - - ReAddrPhase_RNIBH4F : NOR3 - port map(A => N_1081, B => un7_dmain(66), C => - un23_ahbinhgrantx, Y => N_247); - - \Address_RNO_1[19]\ : MX2C - port map(A => N_1036, B => N_25_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_269); - - \AHBOut.hwrite_RNO_1\ : AO1B - port map(A => N_1082, B => hwrite_2_sqmuxa, C => WriteAcc_m, - Y => hwrite_8); - - \Address_RNO[2]\ : NOR2A - port map(A => rstn, B => \Address_9[2]\, Y => - \Address_RNO[2]_net_1\); - - \Address_RNO_1[5]\ : MX2C - port map(A => N_1022, B => N_45, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_255); - - \Address_RNO[4]\ : NOR2A - port map(A => rstn, B => \Address_9[4]\, Y => - \Address_RNO[4]_net_1\); - - \AddressSave_RNO[14]\ : NOR2B - port map(A => N_368, B => rstn, Y => - \AddressSave_RNO[14]_net_1\); - - EarlyPhase_RNO : NOR2B - port map(A => N_351, B => rstn, Y => \EarlyPhase_RNO\); - - \Address_RNO[25]\ : NOR2A - port map(A => rstn, B => \Address_9[25]\, Y => - \Address_RNO[25]_net_1\); - - \Address[21]\ : DFN1 - port map(D => \Address_RNO[21]_net_1\, CLK => lclk_c, Q => - \haddr[21]\); - - \AddressSave_RNO[28]\ : NOR2B - port map(A => N_382, B => rstn, Y => - \AddressSave_RNO[28]_net_1\); - - \AddressSave_RNO_1[12]\ : MX2A - port map(A => N_1029, B => \haddr[12]\, S => - \AddressPhase_0\, Y => \AddressSave_4[12]\); - - ActivePhase_RNI68JFKO : NOR3C - port map(A => rstn, B => \hburst_11_i_a2_i_a3_0[1]\, C => - hburst_2_sqmuxa_1, Y => N_30); - - ReDataPhase_RNIHRIE8H1 : AOI1 - port map(A => un1_AddressPhase_0_sqmuxa_1_0, B => - AddressPhase_1_sqmuxa, C => \un1_dmain_20_0\, Y => - un1_dmain_20); - - \AddressSave_RNO_1[10]\ : MX2A - port map(A => N_1027, B => \haddr[10]\, S => \AddressPhase\, - Y => \AddressSave_4[10]\); - - ReDataPhase_RNO : NOR3C - port map(A => rstn, B => \ReDataPhase\, C => - ReDataPhase_0_sqmuxa_i_0_0, Y => \ReDataPhase_RNO\); - - \AHBOut.hsize_RNO[0]\ : NOR3B - port map(A => rstn, B => \hsize[0]\, C => hsize_0_sqmuxa_0, - Y => \hsize_RNO[0]\); - - \AddressSave_RNO[21]\ : NOR2B - port map(A => N_375, B => rstn, Y => - \AddressSave_RNO[21]_net_1\); - - IdlePhase_RNO_0 : MX2 - port map(A => dataphase10, B => IdlePhase_net_1, S => - un1_redataphase21, Y => N_350); - - EarlyPhase_RNI0A8J2 : OR3A - port map(A => un46_ahbinhgrantx, B => - AddressPhase_2_sqmuxa_0, C => un84_ahbinhgrantx, Y => - un1_AddressPhase_0_sqmuxa_1_0_0_tz); - - un1_AddressSave_0_sqmuxa_1_m57 : AX1E - port map(A => \haddr[28]\, B => N_39, C => \haddr[29]\, Y - => N_58_0_i); - - \Address[17]\ : DFN1 - port map(D => \Address_RNO[17]_net_1\, CLK => lclk_c, Q => - \haddr[17]\); - - \AddressSave[10]\ : DFN1 - port map(D => \AddressSave_RNO[10]_net_1\, CLK => lclk_c, Q - => \AddressSave[10]_net_1\); - - EarlyPhase_RNIPI2N_0 : AO1 - port map(A => un7_dmain(66), B => N_1081, C => - un37_ahbinhgrantx, Y => un45_ahbinhgrantx); - - \AddressSave_RNO_0[26]\ : MX2 - port map(A => \AddressSave[26]_net_1\, B => - \AddressSave_4[26]\, S => hsize_0_sqmuxa, Y => N_380); - - AddressPhase_0_RNII6SUJO_0 : OR3A - port map(A => iosn_0(93), B => \AddressPhase_0\, C => - un5_ahbinhgrantx, Y => BoundaryPhase_2_sqmuxa_i_0); - - IdlePhase_RNIII7AVI : OR2A - port map(A => Grant_1_2, B => nhmaster_1_i(0), Y => Grant); - - \Address_RNO_1[1]\ : MX2 - port map(A => N_1018, B => \haddr[1]\, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_251); - - \Address_RNO_1[6]\ : MX2C - port map(A => N_1023, B => N_46, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_256); - - un1_AddressSave_0_sqmuxa_1_m51 : AX1E - port map(A => \haddr[12]\, B => N_13_0, C => \haddr[13]\, Y - => N_52_0); - - un1_AddressSave_0_sqmuxa_1_m34 : AX1E - port map(A => \haddr[24]\, B => N_32_0, C => \haddr[25]\, Y - => N_35_i); - - \Address[27]\ : DFN1 - port map(D => \Address_RNO[27]_net_1\, CLK => lclk_c, Q => - \haddr[27]\); - - \AddressSave[3]\ : DFN1 - port map(D => \AddressSave_RNO[3]_net_1\, CLK => lclk_c, Q - => \AddressSave[3]_net_1\); - - DataPhase : DFN1 - port map(D => N_423_i, CLK => lclk_c, Q => \DataPhase\); - - \AddressSave[2]\ : DFN1 - port map(D => \AddressSave_RNO[2]_net_1\, CLK => lclk_c, Q - => \AddressSave[2]_net_1\); - - \AddressSave[27]\ : DFN1 - port map(D => \AddressSave_RNO[27]_net_1\, CLK => lclk_c, Q - => \AddressSave[27]_net_1\); - - AddressPhase_0 : DFN1 - port map(D => \AddressPhase_RNIGMGKAH1\, CLK => lclk_c, Q - => \AddressPhase_0\); - - \Address_RNO_0[20]\ : MX2C - port map(A => \AddressSave[20]_net_1\, B => N_270, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[20]\); - - \AddressSave_RNO[8]\ : NOR2B - port map(A => N_362, B => rstn, Y => - \AddressSave_RNO[8]_net_1\); - - \AddressSave[5]\ : DFN1 - port map(D => \AddressSave_RNO[5]_net_1\, CLK => lclk_c, Q - => \AddressSave[5]_net_1\); - - EarlyPhase_RNIPTR9_0 : NOR2A - port map(A => \EarlyPhase\, B => un23_ahbinhgrantx, Y => - AddressPhase_2_sqmuxa_0); - - \AddressSave[24]\ : DFN1 - port map(D => N_26, CLK => lclk_c, Q => - \AddressSave[24]_net_1\); - - \AddressSave_RNO_1[8]\ : MX2A - port map(A => N_1025, B => \haddr[8]\, S => \AddressPhase\, - Y => \AddressSave_4[8]\); - - \Address_RNO[31]\ : NOR2A - port map(A => rstn, B => \Address_9[31]\, Y => - \Address_RNO[31]_net_1\); - - \Address_RNIHCGF1[3]\ : NOR2 - port map(A => BoundaryPhase_0_sqmuxa_6_0, B => - AddressSave_0_sqmuxa, Y => BoundaryPhase_0_sqmuxa_6); - - \AHBOut.htrans_RNO[0]\ : MX2C - port map(A => un1_dmain_15, B => un28_ahbinhgrantx_i_0, S - => \htrans_RNO_2[0]\, Y => \htrans_12[0]\); - - un1_AddressSave_0_sqmuxa_1_m44 : XOR2 - port map(A => N_5_0, B => \haddr[5]\, Y => N_45); - - un1_AddressSave_0_sqmuxa_1_m43 : XNOR2 - port map(A => BoundaryPhase_0_sqmuxa_6, B => \haddr[4]\, Y - => N_44); - - \Address_RNO[12]\ : NOR2A - port map(A => rstn, B => \Address_9[12]\, Y => - \Address_RNO[12]_net_1\); - - DataPhase_RNIC3IU1 : AOI1 - port map(A => \DataPhase\, B => hresp(0), C => iosn_2(93), - Y => un1_redataphase21); - - un1_AddressSave_0_sqmuxa_1_m36 : XNOR2 - port map(A => N_36, B => \haddr[26]\, Y => N_37_i); - - DataPhase_RNI543F1_0 : NOR2A - port map(A => \DataPhase\, B => iosn_2(93), Y => - dataphase10); - - \Address_RNO_0[23]\ : MX2C - port map(A => \AddressSave[23]_net_1\, B => N_273, S => - ReDataPhase_0_sqmuxa_i_0_0, Y => \Address_9[23]\); - - un1_AddressSave_0_sqmuxa_1_m22 : XNOR2 - port map(A => N_22_0, B => \haddr[18]\, Y => N_23_0); - - \AddressSave_RNO[6]\ : NOR2B - port map(A => N_360, B => rstn, Y => - \AddressSave_RNO[6]_net_1\); - - \AddressSave_RNO_0[29]\ : MX2 - port map(A => \AddressSave[29]_net_1\, B => - \AddressSave_4[29]\, S => hsize_0_sqmuxa, Y => N_383); - - \Address[1]\ : DFN1 - port map(D => \Address_RNO[1]_net_1\, CLK => lclk_c, Q => - \haddr[1]\); - - \AddressSave_RNO[20]\ : NOR2B - port map(A => N_374, B => rstn, Y => - \AddressSave_RNO[20]_net_1\); - - \AddressSave_RNO[17]\ : NOR2B - port map(A => N_371, B => rstn, Y => - \AddressSave_RNO[17]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m46 : AX1E - port map(A => BoundaryPhase_0_sqmuxa_6, B => - BoundaryPhase_0_sqmuxa_8_2, C => \haddr[8]\, Y => N_83_i); - - \AHBOut.hburst[1]\ : DFN1E0 - port map(D => N_30, CLK => lclk_c, E => - \DataPhase_RNI2ITCNO\, Q => hburst(1)); - - un1_AddressSave_0_sqmuxa_1_m4 : OR2B - port map(A => BoundaryPhase_0_sqmuxa_6, B => \haddr[4]\, Y - => N_5_0); - - \AddressSave_RNO_1[18]\ : MX2A - port map(A => N_1035, B => \haddr[18]\, S => - \AddressPhase_0\, Y => \AddressSave_4[18]\); - - \AddressSave_RNO_0[25]\ : MX2 - port map(A => \AddressSave[25]_net_1\, B => - \AddressSave_4[25]\, S => hsize_0_sqmuxa, Y => N_379); - - \AddressSave_RNO_0[21]\ : MX2 - port map(A => \AddressSave[21]_net_1\, B => - \AddressSave_4[21]\, S => hsize_0_sqmuxa, Y => N_375); - - \Address_RNO_0[10]\ : MX2C - port map(A => \AddressSave[10]_net_1\, B => N_260, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[10]\); - - \Address_RNO[20]\ : NOR2A - port map(A => rstn, B => \Address_9[20]\, Y => - \Address_RNO[20]_net_1\); - - ActivePhase_RNO_0 : AO1A - port map(A => un7_addressphase, B => \ActivePhase\, C => - hwrite_2_sqmuxa, Y => N_344); - - \AddressSave_RNO[26]\ : NOR2B - port map(A => N_380, B => rstn, Y => - \AddressSave_RNO[26]_net_1\); - - AddressPhase_RNIGMGKAH1 : AO1 - port map(A => \AddressPhase\, B => htrans_4_sqmuxa, C => - un1_dmain_20, Y => \AddressPhase_RNIGMGKAH1\); - - \Address_RNO_1[20]\ : MX2C - port map(A => Address_RNIJ4SP(20), B => N_54_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_270); - - \AddressSave[28]\ : DFN1 - port map(D => \AddressSave_RNO[28]_net_1\, CLK => lclk_c, Q - => \AddressSave[28]_net_1\); - - \AddressSave_RNO_1[4]\ : MX2A - port map(A => N_1021, B => \haddr[4]\, S => \AddressPhase\, - Y => \AddressSave_4[4]\); - - \Address_RNO_1[10]\ : MX2C - port map(A => N_1027, B => N_11_0, S => - BoundaryPhase_2_sqmuxa_i_0, Y => N_260); - - \AddressSave_RNO_1[22]\ : MX2A - port map(A => N_1039, B => \haddr[22]\, S => \AddressPhase\, - Y => \AddressSave_4[22]\); - - ReDataPhase : DFN1 - port map(D => \ReDataPhase_RNO\, CLK => lclk_c, Q => - \ReDataPhase\); - - \AHBOut.htrans[0]\ : DFN1E0 - port map(D => \htrans_12[0]\, CLK => lclk_c, E => - htrans_4_sqmuxa, Q => htrans(0)); - - un1_AddressSave_0_sqmuxa_1_m15 : XNOR2 - port map(A => N_15_0, B => \haddr[14]\, Y => N_16_0); - - \AddressSave_RNO_1[20]\ : MX2A - port map(A => Address_RNIJ4SP(20), B => \haddr[20]\, S => - \AddressPhase_0\, Y => \AddressSave_4[20]\); - - \AddressSave_RNO_1[14]\ : MX2A - port map(A => N_1031, B => \haddr[14]\, S => - \AddressPhase_0\, Y => \AddressSave_4[14]\); - - un1_AddressSave_0_sqmuxa_1_m8 : OR3C - port map(A => BoundaryPhase_0_sqmuxa_6, B => - BoundaryPhase_0_sqmuxa_8_2, C => \haddr[8]\, Y => N_9_0); - - un1_AddressSave_0_sqmuxa_1_m28 : NOR3C - port map(A => \haddr[20]\, B => N_26_0, C => \haddr[21]\, Y - => N_29_0); - - \Address_RNO_0[13]\ : MX2C - port map(A => \AddressSave[13]_net_1\, B => N_263, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[13]\); - - \Address_RNO[15]\ : NOR2A - port map(A => rstn, B => \Address_9[15]\, Y => - \Address_RNO[15]_net_1\); - - un1_AddressSave_0_sqmuxa_1_m10 : XNOR2 - port map(A => BoundaryPhase_0_sqmuxa, B => \haddr[10]\, Y - => N_11_0); - - \AHBOut.hburst_RNO[0]\ : NOR3B - port map(A => \hburst_11_0_a2_1[0]\, B => rstn, C => - hgrant(3), Y => \hburst_11[0]\); - - \AddressSave_RNO_1[13]\ : MX2A - port map(A => N_1030, B => \haddr[13]\, S => - \AddressPhase_0\, Y => \AddressSave_4[13]\); - - \Address_RNO_1[23]\ : MX2C - port map(A => N_1040, B => N_55_0_i, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_273); - - \Address_RNO_0[21]\ : MX2C - port map(A => \AddressSave[21]_net_1\, B => N_271, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[21]\); - - \AHBOut.hwrite_RNO_2\ : OR3B - port map(A => iosn_0(93), B => WriteAcc_m_0, C => hgrant(3), - Y => WriteAcc_m); - - \AddressSave[19]\ : DFN1 - port map(D => \AddressSave_RNO[19]_net_1\, CLK => lclk_c, Q - => \AddressSave[19]_net_1\); - - \Address_RNO_1[13]\ : MX2C - port map(A => N_1030, B => N_52_0, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_263); - - un1_AddressSave_0_sqmuxa_1_m59 : AX1E - port map(A => \haddr[30]\, B => N_41, C => \haddr[31]\, Y - => N_60_0); - - \Address_RNO_1[9]\ : MX2C - port map(A => N_1026, B => N_84_i, S => - BoundaryPhase_2_sqmuxa_i_0_0, Y => N_259); - - \Address_RNO_0[0]\ : MX2C - port map(A => \AddressSave[0]_net_1\, B => N_250, S => - ReDataPhase_0_sqmuxa_i_0, Y => \Address_9[0]\); - - DataPhase_RNIC3IU1_1 : OR2B - port map(A => dataphase10, B => hresp(0), Y => \Fault\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_dma is - - port( addr_data_f0 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - l1_0_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - bco_msb_1_m : in std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - hgrant : in std_logic_vector(3 to 3); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - bco_msb_1 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - hmaster_0 : in std_logic_vector(1 to 1); - hsize : out std_logic_vector(1 downto 0); - nhmaster_1_i : in std_logic_vector(0 to 0); - iosn_1 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - htrans : out std_logic_vector(1 downto 0); - hburst : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0); - data_ren : out std_logic_vector(3 downto 0); - ready_i_0_i_0 : in std_logic_vector(1 to 1); - ready_i_0_2 : in std_logic; - ready_i_0_0 : in std_logic; - ready_i_0_3 : in std_logic; - time_ren : out std_logic_vector(3 downto 0); - time_ren_1z : out std_logic; - data_ren_1z : out std_logic; - m26_m1_e : out std_logic; - m19_a1_6_i_0 : out std_logic; - m19_a0_6_i_0 : out std_logic; - m19_0_N_15_i_0_li : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - Lock_RNIU86D : out std_logic; - hbusreq_i_3 : out std_logic; - arb_1 : in std_logic; - un1_dmain_6 : out std_logic; - hwrite : out std_logic; - IdlePhase : out std_logic; - un13_time_write : out std_logic; - un5_time_write : out std_logic; - un27_time_write : out std_logic; - un20_time_write : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_waveform_dma; - -architecture DEF_ARCH of lpp_waveform_dma is - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(2 to 2); - status_full : out std_logic_vector(2 to 2); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - update_and_sel_3 : in std_logic_vector(5 downto 4) := (others => 'U'); - status_full_ack : in std_logic_vector(2 to 2) := (others => 'U'); - addr_data_vector_30 : in std_logic := 'U'; - addr_data_vector_31 : in std_logic := 'U'; - addr_data_vector_5 : in std_logic := 'U'; - addr_data_vector_8 : in std_logic := 'U'; - addr_data_vector_7 : in std_logic := 'U'; - addr_data_vector_6 : in std_logic := 'U'; - addr_data_vector_3 : in std_logic := 'U'; - addr_data_vector_14 : in std_logic := 'U'; - addr_data_vector_11 : in std_logic := 'U'; - addr_data_vector_10 : in std_logic := 'U'; - addr_data_vector_9 : in std_logic := 'U'; - addr_data_vector_21 : in std_logic := 'U'; - addr_data_vector_19 : in std_logic := 'U'; - addr_data_vector_18 : in std_logic := 'U'; - addr_data_vector_17 : in std_logic := 'U'; - addr_data_vector_29 : in std_logic := 'U'; - addr_data_vector_26 : in std_logic := 'U'; - addr_data_vector_25 : in std_logic := 'U'; - addr_data_vector_24 : in std_logic := 'U'; - addr_data_vector_1 : in std_logic := 'U'; - addr_data_vector_68 : out std_logic; - addr_data_vector_66 : out std_logic; - addr_data_vector_77 : out std_logic; - addr_data_vector_91 : out std_logic; - addr_data_vector_15 : in std_logic := 'U'; - addr_data_vector_12 : in std_logic := 'U'; - addr_data_vector_20 : in std_logic := 'U'; - addr_data_vector_16 : in std_logic := 'U'; - addr_data_vector_28 : in std_logic := 'U'; - addr_data_vector_23 : in std_logic := 'U'; - addr_data_vector_0 : in std_logic := 'U'; - addr_data_vector_86 : out std_logic; - N_1365 : out std_logic; - N_1366 : out std_logic; - N_1396 : out std_logic; - N_1399 : out std_logic; - N_1398 : out std_logic; - N_1397 : out std_logic; - N_1394 : out std_logic; - N_1391 : out std_logic; - N_1388 : out std_logic; - N_1387 : out std_logic; - N_1386 : out std_logic; - N_1384 : out std_logic; - N_1382 : out std_logic; - N_1381 : out std_logic; - N_1380 : out std_logic; - N_1378 : out std_logic; - N_1375 : out std_logic; - N_1374 : out std_logic; - N_1373 : out std_logic; - N_1350 : out std_logic; - N_1392 : out std_logic; - N_1389 : out std_logic; - N_1383 : out std_logic; - N_1379 : out std_logic; - N_1377 : out std_logic; - N_1372 : out std_logic; - N_1349 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(0 to 0); - status_full : out std_logic_vector(0 to 0); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_7 : in std_logic_vector(1 downto 0) := (others => 'U'); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(0 to 0) := (others => 'U'); - addr_data_vector_1 : out std_logic; - addr_data_vector_0 : out std_logic; - addr_data_vector_68 : in std_logic := 'U'; - addr_data_vector_66 : in std_logic := 'U'; - addr_data_vector_77 : in std_logic := 'U'; - addr_data_vector_86 : in std_logic := 'U'; - addr_data_vector_91 : in std_logic := 'U'; - addr_data_vector_31 : out std_logic; - addr_data_vector_30 : out std_logic; - addr_data_vector_5 : out std_logic; - addr_data_vector_29 : out std_logic; - addr_data_vector_28 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_25 : out std_logic; - addr_data_vector_24 : out std_logic; - addr_data_vector_23 : out std_logic; - addr_data_vector_12 : out std_logic; - addr_data_vector_11 : out std_logic; - addr_data_vector_10 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_8 : out std_logic; - addr_data_vector_7 : out std_logic; - addr_data_vector_3 : out std_logic; - addr_data_vector_6 : out std_logic; - addr_data_vector_18 : out std_logic; - addr_data_vector_17 : out std_logic; - addr_data_vector_21 : out std_logic; - addr_data_vector_14 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_16 : out std_logic; - addr_data_vector_19 : out std_logic; - addr_data_vector_20 : out std_logic; - N_1395 : out std_logic; - N_1393 : out std_logic; - N_1390 : out std_logic; - N_1385 : out std_logic; - N_1376 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_dma_send_16word - port( un7_dmain : out std_logic_vector(66 to 66); - state_0_0 : in std_logic := 'U'; - Address_RNIJ4SP : out std_logic_vector(20 to 20); - Address_RNIP8BS : out std_logic_vector(0 to 0); - data_address : in std_logic_vector(31 downto 0) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - Lock : out std_logic; - Request_0 : in std_logic := 'U'; - N_1081 : out std_logic; - Store_0 : in std_logic := 'U'; - N_1082 : out std_logic; - Fault : in std_logic := 'U'; - N_1022 : out std_logic; - data_send_ok : out std_logic; - data_send_ko : out std_logic; - N_1102 : out std_logic; - N_1027 : out std_logic; - N_1026 : out std_logic; - N_1025 : out std_logic; - N_1024 : out std_logic; - N_1023 : out std_logic; - N_1021 : out std_logic; - N_1034 : out std_logic; - N_1033 : out std_logic; - N_1031 : out std_logic; - N_1030 : out std_logic; - N_1029 : out std_logic; - N_1028 : out std_logic; - N_1041 : out std_logic; - time_select : in std_logic := 'U'; - N_1040 : out std_logic; - N_1039 : out std_logic; - N_1038 : out std_logic; - N_1036 : out std_logic; - N_1035 : out std_logic; - N_1048 : out std_logic; - N_1047 : out std_logic; - N_1046 : out std_logic; - N_1044 : out std_logic; - N_1043 : out std_logic; - N_1042 : out std_logic; - N_1020 : out std_logic; - N_1019 : out std_logic; - N_1018 : out std_logic; - data_fifo_ren : out std_logic; - N_1032 : out std_logic; - N_1045 : out std_logic; - time_select_0 : in std_logic := 'U'; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - Grant_1_0 : in std_logic := 'U'; - m19_0_N_15_i_0_li : in std_logic := 'U'; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - OKAY : in std_logic := 'U'; - Ready : in std_logic := 'U'; - data_send : in std_logic := 'U'; - Grant_0 : in std_logic := 'U'; - Grant : in std_logic := 'U'; - m26_m1_e : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(1 to 1); - status_full : out std_logic_vector(1 to 1); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - update_and_sel_5 : in std_logic_vector(3 downto 2) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_vector_69 : in std_logic := 'U'; - addr_data_vector_95 : in std_logic := 'U'; - addr_data_vector_94 : in std_logic := 'U'; - addr_data_vector_93 : in std_logic := 'U'; - addr_data_vector_91 : in std_logic := 'U'; - addr_data_vector_89 : in std_logic := 'U'; - addr_data_vector_88 : in std_logic := 'U'; - addr_data_vector_85 : in std_logic := 'U'; - addr_data_vector_68 : in std_logic := 'U'; - addr_data_vector_67 : in std_logic := 'U'; - addr_data_vector_66 : in std_logic := 'U'; - addr_data_vector_65 : in std_logic := 'U'; - addr_data_vector_74 : in std_logic := 'U'; - addr_data_vector_72 : in std_logic := 'U'; - addr_data_vector_71 : in std_logic := 'U'; - addr_data_vector_70 : in std_logic := 'U'; - addr_data_vector_82 : in std_logic := 'U'; - addr_data_vector_78 : in std_logic := 'U'; - addr_data_vector_87 : in std_logic := 'U'; - addr_data_vector_84 : in std_logic := 'U'; - addr_data_vector_64 : in std_logic := 'U'; - addr_data_vector_80 : in std_logic := 'U'; - addr_data_vector_76 : in std_logic := 'U'; - addr_data_vector_28 : out std_logic; - addr_data_vector_26 : out std_logic; - addr_data_vector_13 : out std_logic; - addr_data_vector_11 : out std_logic; - addr_data_vector_9 : out std_logic; - addr_data_vector_15 : out std_logic; - addr_data_vector_17 : out std_logic; - addr_data_vector_19 : out std_logic; - addr_data_vector_22 : out std_logic; - N_1358 : out std_logic; - N_984 : out std_logic; - N_983 : out std_logic; - N_982 : out std_logic; - N_980 : out std_logic; - N_978 : out std_logic; - N_977 : out std_logic; - N_974 : out std_logic; - N_1371 : out std_logic; - N_1370 : out std_logic; - N_1369 : out std_logic; - N_1368 : out std_logic; - N_1363 : out std_logic; - N_1361 : out std_logic; - N_1360 : out std_logic; - N_1359 : out std_logic; - N_1357 : out std_logic; - N_1353 : out std_logic; - N_976 : out std_logic; - N_973 : out std_logic; - N_1367 : out std_logic; - N_1355 : out std_logic; - N_1351 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_dma_send_1word - port( Request : out std_logic; - Store : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - Grant : in std_logic := 'U'; - un1_time_send_ok : out std_logic; - Fault : in std_logic := 'U'; - Ready : in std_logic := 'U'; - time_select_0 : in std_logic := 'U'; - Lock : in std_logic := 'U'; - Lock_RNIU86D : out std_logic; - time_send : in std_logic := 'U' - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - port( nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(3 to 3); - status_full : out std_logic_vector(3 to 3); - sel_data : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_1 : in std_logic_vector(1 to 1) := (others => 'U'); - sel_data_0 : in std_logic_vector(1 to 1) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full_ack : in std_logic_vector(3 to 3) := (others => 'U'); - addr_data_vector_56 : out std_logic; - addr_data_vector_55 : out std_logic; - addr_data_vector_17 : in std_logic := 'U'; - addr_data_vector_13 : in std_logic := 'U'; - addr_data_vector_10 : in std_logic := 'U'; - addr_data_vector_2 : in std_logic := 'U'; - addr_data_vector_0 : in std_logic := 'U'; - addr_data_vector_8 : in std_logic := 'U'; - addr_data_vector_4 : in std_logic := 'U'; - addr_data_vector_63 : out std_logic; - addr_data_vector_6 : in std_logic := 'U'; - addr_data_vector_19 : in std_logic := 'U'; - addr_data_vector_62 : out std_logic; - addr_data_vector_60 : out std_logic; - addr_data_vector_59 : out std_logic; - addr_data_vector_58 : out std_logic; - addr_data_vector_86 : out std_logic; - addr_data_vector_85 : out std_logic; - addr_data_vector_84 : out std_logic; - addr_data_vector_82 : out std_logic; - addr_data_vector_80 : out std_logic; - addr_data_vector_79 : out std_logic; - addr_data_vector_57 : out std_logic; - addr_data_vector_78 : out std_logic; - addr_data_vector_67 : out std_logic; - addr_data_vector_65 : out std_logic; - addr_data_vector_61 : out std_logic; - addr_data_vector_73 : out std_logic; - addr_data_vector_76 : out std_logic; - addr_data_vector_69 : out std_logic; - addr_data_vector_71 : out std_logic; - addr_data_vector_75 : out std_logic; - update_and_sel_1 : in std_logic_vector(7 downto 6) := (others => 'U'); - N_979 : out std_logic; - N_975 : out std_logic; - N_972 : out std_logic; - N_1364 : out std_logic; - N_1362 : out std_logic; - N_1356 : out std_logic; - N_1352 : out std_logic; - N_1354 : out std_logic; - N_981 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component DMA2AHB - port( hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - Address_RNIP8BS : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - Address_RNIJ4SP : in std_logic_vector(20 to 20) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - un7_dmain : in std_logic_vector(66 to 66) := (others => 'U'); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - Ready : out std_logic; - N_1021 : in std_logic := 'U'; - N_1032 : in std_logic := 'U'; - N_1027 : in std_logic := 'U'; - OKAY : out std_logic; - IdlePhase : out std_logic; - N_1018 : in std_logic := 'U'; - N_1025 : in std_logic := 'U'; - N_1042 : in std_logic := 'U'; - N_1034 : in std_logic := 'U'; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - N_1082 : in std_logic := 'U'; - N_1048 : in std_logic := 'U'; - N_1047 : in std_logic := 'U'; - N_1036 : in std_logic := 'U'; - N_1035 : in std_logic := 'U'; - N_1019 : in std_logic := 'U'; - N_1046 : in std_logic := 'U'; - N_1044 : in std_logic := 'U'; - N_1043 : in std_logic := 'U'; - N_1041 : in std_logic := 'U'; - N_1040 : in std_logic := 'U'; - N_1039 : in std_logic := 'U'; - N_1038 : in std_logic := 'U'; - N_1033 : in std_logic := 'U'; - N_1031 : in std_logic := 'U'; - N_1030 : in std_logic := 'U'; - N_1029 : in std_logic := 'U'; - N_1028 : in std_logic := 'U'; - N_1026 : in std_logic := 'U'; - N_1024 : in std_logic := 'U'; - N_1023 : in std_logic := 'U'; - N_1022 : in std_logic := 'U'; - N_1020 : in std_logic := 'U'; - N_1045 : in std_logic := 'U'; - Grant_0 : out std_logic; - Grant : out std_logic; - arb_1 : in std_logic := 'U'; - N_1081 : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - Grant_1_0 : out std_logic; - Fault : out std_logic; - time_select_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal count_send_time_e30_0_0, count_send_time_e30_0_a2_0, - N_1161, N_1196, count_send_time_e30_0_a2_2_1, N_1216, - \count_send_time[27]_net_1\, count_send_time_e30_0_a2_2_0, - \count_send_time_RNO[28]_net_1\, N_1226, - \count_send_time[28]_net_1\, - \count_send_time_RNO[29]_net_1\, N_1230, - \count_send_time[29]_net_1\, count_send_time_e31, N_1264, - N_1261, N_1263, count_send_time_e30, N_1198, N_1197, - N_1215_0, count_send_time_e25, N_1250, N_1248, N_1247, - N_1231, \count_send_time[31]_net_1\, \state_0[2]_net_1\, - N_1232, N_1213, \count_send_time[25]_net_1\, - \state[2]_net_1\, count_send_time_e30_0_a2_0_0, N_1127, - \count_send_time[11]_net_1\, \count_send_time[12]_net_1\, - N_1229, N_1129, \count_send_time[13]_net_1\, - \count_send_time[14]_net_1\, N_1131, - \count_send_time[15]_net_1\, \count_send_time[16]_net_1\, - N_1133, \count_send_time[17]_net_1\, - \count_send_time[18]_net_1\, N_1136, - \count_send_time[19]_net_1\, \count_send_time[20]_net_1\, - N_1139, \count_send_time[21]_net_1\, - \count_send_time[22]_net_1\, - \count_send_time_RNO[26]_net_1\, N_1233, - \count_send_time[26]_net_1\, - \count_send_time_RNO[27]_net_1\, N_1234, - \count_send_time[23]_net_1\, \count_send_time[24]_net_1\, - N_1215, \count_send_time[9]_net_1\, - \count_send_time[10]_net_1\, N_1295, N_1287, - \count_send_time[0]_net_1\, \count_send_time[1]_net_1\, - \count_send_time[2]_net_1\, N_1289, - \count_send_time[3]_net_1\, \count_send_time[4]_net_1\, - N_1291, \count_send_time[5]_net_1\, N_1293, - \count_send_time[6]_net_1\, \count_send_time[7]_net_1\, - \count_send_time[8]_net_1\, \sel_data_0[0]_net_1\, N_1086, - \state[7]_net_1\, \sel_data_1[1]_net_1\, N_1085, - \sel_data_0[1]_net_1\, \state_RNI9NH4I4[4]_net_1\, - \time_select_0\, time_fifo_ren_1, N_868, - time_fifo_ren_1_i, \time_ren\, count_send_time_e12_0_0, - count_send_time_e12_0_a2_1_0, N_1151, - count_send_time_e18_0_0, N_1207, N_1169, - count_send_time_e20_0_0, count_send_time_e20_0_a2_1_0, - N_1177, count_send_time_e22_0_0, - count_send_time_e22_0_a2_1_0, N_1187, - count_send_time_e24_0_0, count_send_time_e24_0_a2_1_0, - N_1243, count_send_time_e1_0_0, - count_send_time_e1_0_a2_1_0, N_1307, - count_send_time_e8_0_0, count_send_time_e8_0_a2_1_0, - N_1330, count_send_time_e10_0_0, - count_send_time_e10_0_a2_1_0, N_1340, - count_send_time_e16_i_0, count_send_time_e14_i_0, - count_send_time_e2_0_a2_1_0, \count_send_time[30]_net_1\, - \data_data_ren_7_0[0]\, \un27_time_write\, - count_send_time_e24_0_a2_0_0, count_send_time_e22_0_a2_0, - count_send_time_e20_0_a2_0, count_send_time_e18_0_a2_0_0, - \state_ns_i_a2_0_1[5]\, N_899_tz, N_1120, N_1118, - state_tr2_i_0, \send_16_3_time[0]_net_1\, - \state_ns_i_a2_0_a3_0[5]\, \sel_data_3_i_0[0]\, - \send_16_3_time_1_sqmuxa_i_o3_0\, - count_send_time_e12_0_a2_0_0, count_send_time_e10_0_a2_0, - count_send_time_e8_0_a2_0, state_tr13_0_a2_15, - state_tr13_0_a2_9, state_tr13_0_a2_8, state_tr13_0_a2_12, - state_tr13_0_a2_14, state_tr13_0_a2_7, state_tr13_0_a2_10, - state_tr13_0_a2_17_0, state_tr13_0_a2_17_1, - state_tr13_0_a2_11, state_tr13_0_a2_6, state_tr13_0_a2_4, - state_tr13_0_a2_1, \state_ns_i_a2_0_a4_0_19_15[5]\, - N_1117_25, \state_ns_i_a2_0_a4_0_19_14[5]\, - \state_ns_i_a2_0_a4_0_19_11[5]\, N_1117_5, - \state_ns_i_a2_0_a4_0_25_4[5]\, - \state_ns_i_a2_0_a4_0_25_2[5]\, - \state_ns_i_a2_0_a4_0_25_1[5]\, - \state_ns_i_a2_0_a4_0_25_0[5]\, - count_send_time_e2_0_a2_0_0, un1_state_13_0_a4_0_0, - \state[1]_net_1\, \state[3]_net_1\, - \state_ns_i_a2_0_a4_0_19_11_0[5]\, N_1099, - \count_send_time_RNO[14]_net_1\, - \count_send_time_RNO_0[14]_net_1\, - \count_send_time_RNO[15]_net_1\, N_1147, N_1162, - \count_send_time_RNO[16]_net_1\, - \count_send_time_RNO[17]_net_1\, N_1166, - \count_send_time_RNO[6]_net_1\, N_1300, N_1323, - \count_send_time_RNO[7]_net_1\, \state_ns[6]\, - count_send_time_e10, N_1290, count_send_time_e9, N_1338, - N_1335, N_1337, count_send_time_e8, count_send_time_e3, - N_1319, N_1317, N_1316, count_send_time_e2, N_1314, - N_1312, N_1311, count_send_time_e1, count_send_time_e24, - count_send_time_e11, N_1240, N_1237, N_1239, - count_send_time_e23, N_1193, N_1191, N_1192, - count_send_time_e22, count_send_time_e21, N_1184, N_1182, - N_1183, count_send_time_e20, count_send_time_e19, N_1174, - N_1173, N_1172, count_send_time_e18, count_send_time_e13, - N_1157, N_1156, N_1155, count_send_time_e12, N_1106, - N_864, \state[0]_net_1\, \state_RNO[6]_net_1\, - \state[4]_net_1\, N_1096, data_fifo_ren, un7_time_write, - \time_write\, \un5_time_write\, un2_status_full_ack, - \data_ren\, \un13_time_write\, \update_and_sel_1[6]\, - \update[0]_net_1\, \update_and_sel_1[7]\, - \update[1]_net_1\, \update_and_sel_3[4]\, - \update_and_sel_3[5]\, un15_time_write, - un7_status_full_ack, un17_status_full_ack, - un29_time_write, \data_address[0]\, N_1349, N_1367, - \data_address[12]\, N_1389, N_1351, \data_address[16]\, - N_1379, N_1355, \data_address[20]\, N_1383, N_973, - \data_address[23]\, N_1372, N_976, \data_address[28]\, - N_1377, N_981, N_1094, \time_already_send[3]\, - \time_already_send[2]\, N_1095, \time_already_send[1]\, - \time_already_send[0]\, \data_address[15]\, N_1392, - N_1354, \sel_data[1]_net_1\, \un20_time_write\, - un22_time_write, un12_status_full_ack, \time_select\, - \update_and_sel_5[2]\, \update_and_sel_5[3]\, - \update_and_sel_7[0]\, \update_and_sel_7[1]\, - \data_address[1]\, N_1350, N_1368, \data_address[2]\, - N_1393, N_1369, \data_address[3]\, N_1394, N_1370, - \data_address[4]\, N_1395, N_1371, \data_address[6]\, - N_1397, N_1359, \data_address[7]\, N_1398, N_1360, - \data_address[8]\, N_1399, N_1361, \data_address[9]\, - N_1386, N_1362, \sel_data[0]_net_1\, \data_address[10]\, - N_1387, N_1363, \data_address[11]\, N_1388, N_1364, - \data_address[13]\, N_1390, N_1352, \data_address[14]\, - N_1391, N_1353, \data_address[17]\, N_1380, N_1356, - \data_address[18]\, N_1381, N_1357, \data_address[19]\, - N_1382, N_972, \data_address[21]\, N_1384, N_974, - \data_address[22]\, N_1385, N_975, \data_address[24]\, - N_1373, N_977, \data_address[25]\, N_1374, N_978, - \data_address[26]\, N_1375, N_979, \data_address[27]\, - N_1376, N_980, \data_address[29]\, N_1378, N_982, - \data_address[30]\, N_1365, N_983, \data_address[31]\, - N_1366, N_984, un1_state_12, N_1102, \state[6]_net_1\, - \state_RNO_0[0]\, count_send_time_e0, - \count_send_time_RNO[4]_net_1\, N_1297, - \count_send_time_RNO[5]_net_1\, N_1298, \state_RNO_1[3]\, - N_1103, \state_RNO_0[4]_net_1\, N_1114, - \state_RNO[5]_net_1\, N_1112, \state_RNO[7]_net_1\, - N_1109, un1_state_13, N_1084, un1_time_send_ok, - \state[5]_net_1\, data_send_ko, data_send_ok, - time_send_0_sqmuxa, update_0_sqmuxa, \time_fifo_ren\, - \data_address[5]\, N_1396, N_1358, N_867, \time_send\, - \data_send\, \send_16_3_time[2]_net_1\, - \send_16_3_time[1]_net_1\, \Address_RNIP8BS[0]\, - \Address_RNIJ4SP[20]\, \un7_dmain[66]\, Ready, N_1021, - N_1032, N_1027, OKAY, N_1018, N_1025, N_1042, N_1034, - N_1082, N_1048, N_1047, N_1036, N_1035, N_1019, N_1046, - N_1044, N_1043, N_1041, N_1040, N_1039, N_1038, N_1033, - N_1031, N_1030, N_1029, N_1028, N_1026, N_1024, N_1023, - N_1022, N_1020, N_1045, Grant_0, Grant, N_1081, Grant_1_0, - Fault, Request, Store, Lock, \addr_data_vector[97]\, - \addr_data_vector[96]\, \addr_data_vector[58]\, - \addr_data_vector[54]\, \addr_data_vector[51]\, - \addr_data_vector[43]\, \addr_data_vector[41]\, - \addr_data_vector[49]\, \addr_data_vector[45]\, - \addr_data_vector[104]\, \addr_data_vector[47]\, - \addr_data_vector[60]\, \addr_data_vector[103]\, - \addr_data_vector[101]\, \addr_data_vector[100]\, - \addr_data_vector[99]\, \addr_data_vector[127]\, - \addr_data_vector[126]\, \addr_data_vector[125]\, - \addr_data_vector[123]\, \addr_data_vector[121]\, - \addr_data_vector[120]\, \addr_data_vector[98]\, - \addr_data_vector[119]\, \addr_data_vector[108]\, - \addr_data_vector[106]\, \addr_data_vector[102]\, - \addr_data_vector[114]\, \addr_data_vector[117]\, - \addr_data_vector[110]\, \addr_data_vector[112]\, - \addr_data_vector[116]\, \addr_data_vector[30]\, - \addr_data_vector[31]\, \addr_data_vector[5]\, - \addr_data_vector[8]\, \addr_data_vector[7]\, - \addr_data_vector[6]\, \addr_data_vector[3]\, - \addr_data_vector[14]\, \addr_data_vector[11]\, - \addr_data_vector[10]\, \addr_data_vector[9]\, - \addr_data_vector[21]\, \addr_data_vector[19]\, - \addr_data_vector[18]\, \addr_data_vector[17]\, - \addr_data_vector[29]\, \addr_data_vector[26]\, - \addr_data_vector[25]\, \addr_data_vector[24]\, - \addr_data_vector[1]\, \addr_data_vector[68]\, - \addr_data_vector[66]\, \addr_data_vector[77]\, - \addr_data_vector[91]\, \addr_data_vector[15]\, - \addr_data_vector[12]\, \addr_data_vector[20]\, - \addr_data_vector[16]\, \addr_data_vector[28]\, - \addr_data_vector[23]\, \addr_data_vector[0]\, - \addr_data_vector[86]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\(DEF_ARCH); - for all : lpp_dma_send_16word - Use entity work.lpp_dma_send_16word(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\(DEF_ARCH); - for all : lpp_dma_send_1word - Use entity work.lpp_dma_send_1word(DEF_ARCH); - for all : \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - Use entity work. - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\(DEF_ARCH); - for all : DMA2AHB - Use entity work.DMA2AHB(DEF_ARCH); -begin - - time_ren_1z <= \time_ren\; - data_ren_1z <= \data_ren\; - un13_time_write <= \un13_time_write\; - un5_time_write <= \un5_time_write\; - un27_time_write <= \un27_time_write\; - un20_time_write <= \un20_time_write\; - - \update_RNI42QC_1[0]\ : NOR2A - port map(A => \update[0]_net_1\, B => \un13_time_write\, Y - => \update_and_sel_3[4]\); - - \state[0]\ : DFN1C0 - port map(D => \state_RNO_0[0]\, CLK => lclk_c, CLR => rstn, - Q => \state[0]_net_1\); - - \count_send_time_RNO_0[9]\ : OR3 - port map(A => N_1295, B => \count_send_time[9]_net_1\, C - => N_1215_0, Y => N_1338); - - \state_RNI7A1C_0[2]\ : OAI1 - port map(A => \state[2]_net_1\, B => \state[7]_net_1\, C - => rstn, Y => N_1290); - - \count_send_time_RNO_4[30]\ : AOI1B - port map(A => \count_send_time[29]_net_1\, B => - \count_send_time[28]_net_1\, C => - \count_send_time[30]_net_1\, Y => - count_send_time_e30_0_a2_0); - - time_select_RNIC84U1J_0 : OR2 - port map(A => \data_ren\, B => \un20_time_write\, Y => - data_ren(1)); - - \sel_data[0]\ : DFN1E1C0 - port map(D => N_1086, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data[0]_net_1\); - - \gen_select_address.2.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_1\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(2) => status_full_err(2), status_full(2) - => status_full(2), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, sel_data_0(1) => - \sel_data_0[1]_net_1\, addr_data_f2(31) => - addr_data_f2(31), addr_data_f2(30) => addr_data_f2(30), - addr_data_f2(29) => addr_data_f2(29), addr_data_f2(28) - => addr_data_f2(28), addr_data_f2(27) => - addr_data_f2(27), addr_data_f2(26) => addr_data_f2(26), - addr_data_f2(25) => addr_data_f2(25), addr_data_f2(24) - => addr_data_f2(24), addr_data_f2(23) => - addr_data_f2(23), addr_data_f2(22) => addr_data_f2(22), - addr_data_f2(21) => addr_data_f2(21), addr_data_f2(20) - => addr_data_f2(20), addr_data_f2(19) => - addr_data_f2(19), addr_data_f2(18) => addr_data_f2(18), - addr_data_f2(17) => addr_data_f2(17), addr_data_f2(16) - => addr_data_f2(16), addr_data_f2(15) => - addr_data_f2(15), addr_data_f2(14) => addr_data_f2(14), - addr_data_f2(13) => addr_data_f2(13), addr_data_f2(12) - => addr_data_f2(12), addr_data_f2(11) => - addr_data_f2(11), addr_data_f2(10) => addr_data_f2(10), - addr_data_f2(9) => addr_data_f2(9), addr_data_f2(8) => - addr_data_f2(8), addr_data_f2(7) => addr_data_f2(7), - addr_data_f2(6) => addr_data_f2(6), addr_data_f2(5) => - addr_data_f2(5), addr_data_f2(4) => addr_data_f2(4), - addr_data_f2(3) => addr_data_f2(3), addr_data_f2(2) => - addr_data_f2(2), addr_data_f2(1) => addr_data_f2(1), - addr_data_f2(0) => addr_data_f2(0), update_and_sel_3(5) - => \update_and_sel_3[5]\, update_and_sel_3(4) => - \update_and_sel_3[4]\, status_full_ack(2) => - status_full_ack(2), addr_data_vector_30 => - \addr_data_vector[30]\, addr_data_vector_31 => - \addr_data_vector[31]\, addr_data_vector_5 => - \addr_data_vector[5]\, addr_data_vector_8 => - \addr_data_vector[8]\, addr_data_vector_7 => - \addr_data_vector[7]\, addr_data_vector_6 => - \addr_data_vector[6]\, addr_data_vector_3 => - \addr_data_vector[3]\, addr_data_vector_14 => - \addr_data_vector[14]\, addr_data_vector_11 => - \addr_data_vector[11]\, addr_data_vector_10 => - \addr_data_vector[10]\, addr_data_vector_9 => - \addr_data_vector[9]\, addr_data_vector_21 => - \addr_data_vector[21]\, addr_data_vector_19 => - \addr_data_vector[19]\, addr_data_vector_18 => - \addr_data_vector[18]\, addr_data_vector_17 => - \addr_data_vector[17]\, addr_data_vector_29 => - \addr_data_vector[29]\, addr_data_vector_26 => - \addr_data_vector[26]\, addr_data_vector_25 => - \addr_data_vector[25]\, addr_data_vector_24 => - \addr_data_vector[24]\, addr_data_vector_1 => - \addr_data_vector[1]\, addr_data_vector_68 => - \addr_data_vector[68]\, addr_data_vector_66 => - \addr_data_vector[66]\, addr_data_vector_77 => - \addr_data_vector[77]\, addr_data_vector_91 => - \addr_data_vector[91]\, addr_data_vector_15 => - \addr_data_vector[15]\, addr_data_vector_12 => - \addr_data_vector[12]\, addr_data_vector_20 => - \addr_data_vector[20]\, addr_data_vector_16 => - \addr_data_vector[16]\, addr_data_vector_28 => - \addr_data_vector[28]\, addr_data_vector_23 => - \addr_data_vector[23]\, addr_data_vector_0 => - \addr_data_vector[0]\, addr_data_vector_86 => - \addr_data_vector[86]\, N_1365 => N_1365, N_1366 => - N_1366, N_1396 => N_1396, N_1399 => N_1399, N_1398 => - N_1398, N_1397 => N_1397, N_1394 => N_1394, N_1391 => - N_1391, N_1388 => N_1388, N_1387 => N_1387, N_1386 => - N_1386, N_1384 => N_1384, N_1382 => N_1382, N_1381 => - N_1381, N_1380 => N_1380, N_1378 => N_1378, N_1375 => - N_1375, N_1374 => N_1374, N_1373 => N_1373, N_1350 => - N_1350, N_1392 => N_1392, N_1389 => N_1389, N_1383 => - N_1383, N_1379 => N_1379, N_1377 => N_1377, N_1372 => - N_1372, N_1349 => N_1349, rstn => rstn, lclk_c => lclk_c); - - \sel_data_RNI1G8O[0]\ : MX2C - port map(A => N_1386, B => N_1362, S => \sel_data[0]_net_1\, - Y => \data_address[9]\); - - \count_send_time_RNO_0[16]\ : AO1C - port map(A => N_1215_0, B => N_1131, C => N_1161, Y => - count_send_time_e16_i_0); - - \count_send_time_RNIN93N3[24]\ : OR3B - port map(A => \count_send_time[23]_net_1\, B => - \count_send_time[24]_net_1\, C => N_1139, Y => N_1213); - - \count_send_time_RNO_2[1]\ : OR3B - port map(A => \count_send_time[1]_net_1\, B => - \state[2]_net_1\, C => \count_send_time[0]_net_1\, Y => - N_1307); - - \count_send_time_RNO[4]\ : XA1A - port map(A => N_1297, B => \count_send_time[4]_net_1\, C - => N_1161, Y => \count_send_time_RNO[4]_net_1\); - - \gen_select_address.0.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_3\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(0) => status_full_err(0), status_full(0) - => status_full(0), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, - update_and_sel_7(1) => \update_and_sel_7[1]\, - update_and_sel_7(0) => \update_and_sel_7[0]\, - addr_data_f0(31) => addr_data_f0(31), addr_data_f0(30) - => addr_data_f0(30), addr_data_f0(29) => - addr_data_f0(29), addr_data_f0(28) => addr_data_f0(28), - addr_data_f0(27) => addr_data_f0(27), addr_data_f0(26) - => addr_data_f0(26), addr_data_f0(25) => - addr_data_f0(25), addr_data_f0(24) => addr_data_f0(24), - addr_data_f0(23) => addr_data_f0(23), addr_data_f0(22) - => addr_data_f0(22), addr_data_f0(21) => - addr_data_f0(21), addr_data_f0(20) => addr_data_f0(20), - addr_data_f0(19) => addr_data_f0(19), addr_data_f0(18) - => addr_data_f0(18), addr_data_f0(17) => - addr_data_f0(17), addr_data_f0(16) => addr_data_f0(16), - addr_data_f0(15) => addr_data_f0(15), addr_data_f0(14) - => addr_data_f0(14), addr_data_f0(13) => - addr_data_f0(13), addr_data_f0(12) => addr_data_f0(12), - addr_data_f0(11) => addr_data_f0(11), addr_data_f0(10) - => addr_data_f0(10), addr_data_f0(9) => addr_data_f0(9), - addr_data_f0(8) => addr_data_f0(8), addr_data_f0(7) => - addr_data_f0(7), addr_data_f0(6) => addr_data_f0(6), - addr_data_f0(5) => addr_data_f0(5), addr_data_f0(4) => - addr_data_f0(4), addr_data_f0(3) => addr_data_f0(3), - addr_data_f0(2) => addr_data_f0(2), addr_data_f0(1) => - addr_data_f0(1), addr_data_f0(0) => addr_data_f0(0), - status_full_ack(0) => status_full_ack(0), - addr_data_vector_1 => \addr_data_vector[1]\, - addr_data_vector_0 => \addr_data_vector[0]\, - addr_data_vector_68 => \addr_data_vector[68]\, - addr_data_vector_66 => \addr_data_vector[66]\, - addr_data_vector_77 => \addr_data_vector[77]\, - addr_data_vector_86 => \addr_data_vector[86]\, - addr_data_vector_91 => \addr_data_vector[91]\, - addr_data_vector_31 => \addr_data_vector[31]\, - addr_data_vector_30 => \addr_data_vector[30]\, - addr_data_vector_5 => \addr_data_vector[5]\, - addr_data_vector_29 => \addr_data_vector[29]\, - addr_data_vector_28 => \addr_data_vector[28]\, - addr_data_vector_26 => \addr_data_vector[26]\, - addr_data_vector_25 => \addr_data_vector[25]\, - addr_data_vector_24 => \addr_data_vector[24]\, - addr_data_vector_23 => \addr_data_vector[23]\, - addr_data_vector_12 => \addr_data_vector[12]\, - addr_data_vector_11 => \addr_data_vector[11]\, - addr_data_vector_10 => \addr_data_vector[10]\, - addr_data_vector_9 => \addr_data_vector[9]\, - addr_data_vector_8 => \addr_data_vector[8]\, - addr_data_vector_7 => \addr_data_vector[7]\, - addr_data_vector_3 => \addr_data_vector[3]\, - addr_data_vector_6 => \addr_data_vector[6]\, - addr_data_vector_18 => \addr_data_vector[18]\, - addr_data_vector_17 => \addr_data_vector[17]\, - addr_data_vector_21 => \addr_data_vector[21]\, - addr_data_vector_14 => \addr_data_vector[14]\, - addr_data_vector_15 => \addr_data_vector[15]\, - addr_data_vector_16 => \addr_data_vector[16]\, - addr_data_vector_19 => \addr_data_vector[19]\, - addr_data_vector_20 => \addr_data_vector[20]\, N_1395 => - N_1395, N_1393 => N_1393, N_1390 => N_1390, N_1385 => - N_1385, N_1376 => N_1376, rstn => rstn, lclk_c => lclk_c); - - \count_send_time_RNO[26]\ : XA1A - port map(A => N_1233, B => \count_send_time[26]_net_1\, C - => N_1161, Y => \count_send_time_RNO[26]_net_1\); - - \count_send_time_RNIT30B[16]\ : NOR2 - port map(A => \count_send_time[16]_net_1\, B => - \count_send_time[17]_net_1\, Y => state_tr13_0_a2_1); - - \count_send_time[0]\ : DFN1 - port map(D => count_send_time_e0, CLK => lclk_c, Q => - \count_send_time[0]_net_1\); - - \count_send_time_RNO_3[2]\ : OR3B - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => - \count_send_time[2]_net_1\, Y => - count_send_time_e2_0_a2_1_0); - - \count_send_time_RNO_0[10]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e10_0_a2_1_0, - C => N_1340, Y => count_send_time_e10_0_0); - - \count_send_time_RNO[2]\ : OR3C - port map(A => N_1314, B => N_1312, C => N_1311, Y => - count_send_time_e2); - - \count_send_time_RNIR4B7[6]\ : NOR2 - port map(A => \count_send_time[6]_net_1\, B => - \count_send_time[7]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_1[5]\); - - \sel_data_0_RNI5D5K[0]\ : MX2C - port map(A => N_1349, B => N_1367, S => - \sel_data_0[0]_net_1\, Y => \data_address[0]\); - - \state_RNII50G[4]\ : OR3 - port map(A => \state[4]_net_1\, B => \state[6]_net_1\, C - => \state[2]_net_1\, Y => time_fifo_ren_1); - - \count_send_time_RNIK5324[26]\ : NOR3B - port map(A => \count_send_time[25]_net_1\, B => - \count_send_time[26]_net_1\, C => N_1213, Y => N_1216); - - time_fifo_ren_RNO : INV - port map(A => time_fifo_ren_1, Y => time_fifo_ren_1_i); - - lpp_dma_send_16word_1 : lpp_dma_send_16word - port map(un7_dmain(66) => \un7_dmain[66]\, state_0_0 => - \state[0]_net_1\, Address_RNIJ4SP(20) => - \Address_RNIJ4SP[20]\, Address_RNIP8BS(0) => - \Address_RNIP8BS[0]\, data_address(31) => - \data_address[31]\, data_address(30) => - \data_address[30]\, data_address(29) => - \data_address[29]\, data_address(28) => - \data_address[28]\, data_address(27) => - \data_address[27]\, data_address(26) => - \data_address[26]\, data_address(25) => - \data_address[25]\, data_address(24) => - \data_address[24]\, data_address(23) => - \data_address[23]\, data_address(22) => - \data_address[22]\, data_address(21) => - \data_address[21]\, data_address(20) => - \data_address[20]\, data_address(19) => - \data_address[19]\, data_address(18) => - \data_address[18]\, data_address(17) => - \data_address[17]\, data_address(16) => - \data_address[16]\, data_address(15) => - \data_address[15]\, data_address(14) => - \data_address[14]\, data_address(13) => - \data_address[13]\, data_address(12) => - \data_address[12]\, data_address(11) => - \data_address[11]\, data_address(10) => - \data_address[10]\, data_address(9) => \data_address[9]\, - data_address(8) => \data_address[8]\, data_address(7) => - \data_address[7]\, data_address(6) => \data_address[6]\, - data_address(5) => \data_address[5]\, data_address(4) => - \data_address[4]\, data_address(3) => \data_address[3]\, - data_address(2) => \data_address[2]\, data_address(1) => - \data_address[1]\, data_address(0) => \data_address[0]\, - bco_msb_1_m(1) => bco_msb_1_m(1), nhmaster_1_iv_0(1) => - nhmaster_1_iv_0(1), bco_msb_1(1) => bco_msb_1(1), - hmaster_0(1) => hmaster_0(1), l1_0_m(1) => l1_0_m(1), - nhmaster_1_i(0) => nhmaster_1_i(0), iosn_0(93) => - iosn_0(93), Lock => Lock, Request_0 => Request, N_1081 - => N_1081, Store_0 => Store, N_1082 => N_1082, Fault => - Fault, N_1022 => N_1022, data_send_ok => data_send_ok, - data_send_ko => data_send_ko, N_1102 => N_1102, N_1027 - => N_1027, N_1026 => N_1026, N_1025 => N_1025, N_1024 - => N_1024, N_1023 => N_1023, N_1021 => N_1021, N_1034 - => N_1034, N_1033 => N_1033, N_1031 => N_1031, N_1030 - => N_1030, N_1029 => N_1029, N_1028 => N_1028, N_1041 - => N_1041, time_select => \time_select\, N_1040 => - N_1040, N_1039 => N_1039, N_1038 => N_1038, N_1036 => - N_1036, N_1035 => N_1035, N_1048 => N_1048, N_1047 => - N_1047, N_1046 => N_1046, N_1044 => N_1044, N_1043 => - N_1043, N_1042 => N_1042, N_1020 => N_1020, N_1019 => - N_1019, N_1018 => N_1018, data_fifo_ren => data_fifo_ren, - N_1032 => N_1032, N_1045 => N_1045, time_select_0 => - \time_select_0\, un1_nhmaster_0_sqmuxa_1 => - un1_nhmaster_0_sqmuxa_1, rstoutl_RNIGJKSJO => - rstoutl_RNIGJKSJO, Grant_1_0 => Grant_1_0, - m19_0_N_15_i_0_li => m19_0_N_15_i_0_li, m19_a0_6_i_0 => - m19_a0_6_i_0, m19_a1_6_i_0 => m19_a1_6_i_0, OKAY => OKAY, - Ready => Ready, data_send => \data_send\, Grant_0 => - Grant_0, Grant => Grant, m26_m1_e => m26_m1_e, rstn => - rstn, lclk_c => lclk_c); - - \count_send_time_RNO_0[27]\ : OR2A - port map(A => N_1216, B => N_1215, Y => N_1234); - - \count_send_time_RNO_1[19]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[19]_net_1\, C => N_1133, Y => N_1173); - - \count_send_time[14]\ : DFN1 - port map(D => \count_send_time_RNO[14]_net_1\, CLK => - lclk_c, Q => \count_send_time[14]_net_1\); - - \state[6]\ : DFN1C0 - port map(D => \state_RNO[6]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[6]_net_1\); - - \count_send_time_RNO_2[18]\ : NOR2B - port map(A => \count_send_time[18]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e18_0_a2_0_0); - - \count_send_time[21]\ : DFN1 - port map(D => count_send_time_e21, CLK => lclk_c, Q => - \count_send_time[21]_net_1\); - - \send_16_3_time_RNI8PM9[0]\ : NOR2A - port map(A => \state[7]_net_1\, B => - \send_16_3_time[0]_net_1\, Y => \state_ns_i_a2_0_a3_0[5]\); - - \count_send_time_RNO[14]\ : OA1B - port map(A => \count_send_time_RNO_0[14]_net_1\, B => - \count_send_time[14]_net_1\, C => count_send_time_e14_i_0, - Y => \count_send_time_RNO[14]_net_1\); - - \count_send_time[31]\ : DFN1 - port map(D => count_send_time_e31, CLK => lclk_c, Q => - \count_send_time[31]_net_1\); - - \sel_data_0_RNIDF8O[0]\ : MX2C - port map(A => N_1395, B => N_1371, S => - \sel_data_0[0]_net_1\, Y => \data_address[4]\); - - \sel_data_0_RNIQV7O[0]\ : MX2C - port map(A => N_1399, B => N_1361, S => - \sel_data_0[0]_net_1\, Y => \data_address[8]\); - - \count_send_time_RNO[22]\ : AO1B - port map(A => \count_send_time[22]_net_1\, B => N_1290, C - => count_send_time_e22_0_0, Y => count_send_time_e22); - - time_write_RNO : AO1D - port map(A => un1_state_13_0_a4_0_0, B => \state[7]_net_1\, - C => N_1103, Y => un1_state_13); - - \count_send_time[17]\ : DFN1 - port map(D => \count_send_time_RNO[17]_net_1\, CLK => - lclk_c, Q => \count_send_time[17]_net_1\); - - \sel_data_RNIK0TS[0]\ : MX2C - port map(A => N_1366, B => N_984, S => \sel_data[0]_net_1\, - Y => \data_address[31]\); - - \count_send_time_RNO_0[3]\ : OR3 - port map(A => N_1287, B => \count_send_time[3]_net_1\, C - => N_1215_0, Y => N_1319); - - \sel_data_RNITDRK[0]\ : MX2C - port map(A => N_1380, B => N_1356, S => \sel_data[0]_net_1\, - Y => \data_address[17]\); - - \state_RNICG1QD2[7]\ : OR2B - port map(A => \state[7]_net_1\, B => N_1099, Y => N_1084); - - \count_send_time_RNO_2[8]\ : AO1B - port map(A => \count_send_time[7]_net_1\, B => N_1293, C - => count_send_time_e8_0_a2_0, Y => N_1330); - - \count_send_time_RNIJ4B7[2]\ : NOR2A - port map(A => \count_send_time[3]_net_1\, B => - \count_send_time[2]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_2[5]\); - - \count_send_time_RNO[7]\ : XA1 - port map(A => N_1300, B => \count_send_time[7]_net_1\, C - => N_1161, Y => \count_send_time_RNO[7]_net_1\); - - \all_time_write.0.time_already_send_RNIJMR8U1[0]\ : MX2 - port map(A => N_1095, B => \time_already_send[0]\, S => - ready_i_0_0, Y => N_1096); - - \count_send_time_RNO_2[9]\ : OR2B - port map(A => \count_send_time[9]_net_1\, B => N_1290, Y - => N_1337); - - \count_send_time[25]\ : DFN1 - port map(D => count_send_time_e25, CLK => lclk_c, Q => - \count_send_time[25]_net_1\); - - \count_send_time_RNO_7[30]\ : NOR2B - port map(A => \count_send_time[30]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e30_0_a2_0_0); - - \count_send_time[5]\ : DFN1 - port map(D => \count_send_time_RNO[5]_net_1\, CLK => lclk_c, - Q => \count_send_time[5]_net_1\); - - \update[1]\ : DFN1E0C0 - port map(D => \state[0]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_12, Q => \update[1]_net_1\); - - time_select : DFN1E1C0 - port map(D => time_fifo_ren_1, CLK => lclk_c, CLR => rstn, - E => N_868, Q => \time_select\); - - \count_send_time_RNO_0[2]\ : OR2 - port map(A => count_send_time_e2_0_a2_1_0, B => N_1215_0, Y - => N_1314); - - \count_send_time_RNO[27]\ : XA1A - port map(A => N_1234, B => \count_send_time[27]_net_1\, C - => N_1161, Y => \count_send_time_RNO[27]_net_1\); - - \state_RNIG9BMJ2[2]\ : NOR3C - port map(A => N_899_tz, B => N_1120, C => N_1118, Y => - \state_ns_i_a2_0_1[5]\); - - \count_send_time_RNO_1[10]\ : OR3A - port map(A => \count_send_time[9]_net_1\, B => N_1295, C - => \count_send_time[10]_net_1\, Y => - count_send_time_e10_0_a2_1_0); - - \count_send_time_RNO[0]\ : MX2A - port map(A => N_1215, B => N_1290, S => - \count_send_time[0]_net_1\, Y => count_send_time_e0); - - \count_send_time_RNITRFG[29]\ : NOR3C - port map(A => \count_send_time[28]_net_1\, B => - \count_send_time[29]_net_1\, C => - \count_send_time[30]_net_1\, Y => N_1231); - - \count_send_time_RNO[10]\ : AO1B - port map(A => \count_send_time[10]_net_1\, B => N_1290, C - => count_send_time_e10_0_0, Y => count_send_time_e10); - - \sel_data_0_RNIC84U1J[0]\ : OR2 - port map(A => \data_ren\, B => \un13_time_write\, Y => - data_ren(2)); - - \all_time_write.3.time_already_send[3]\ : DFN1E1C0 - port map(D => un7_time_write, CLK => lclk_c, CLR => rstn, E - => un2_status_full_ack, Q => \time_already_send[3]\); - - \sel_data_0[1]\ : DFN1E1C0 - port map(D => N_1085, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data_0[1]_net_1\); - - \state[4]\ : DFN1C0 - port map(D => \state_RNO_0[4]_net_1\, CLK => lclk_c, CLR - => rstn, Q => \state[4]_net_1\); - - \update_RNI56QC_2[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un27_time_write\, Y - => \update_and_sel_7[1]\); - - time_write : DFN1E0C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - E => un1_state_13, Q => \time_write\); - - data_send_RNO : NOR3 - port map(A => \state[0]_net_1\, B => \state[1]_net_1\, C - => \state[7]_net_1\, Y => N_864); - - \sel_data_1[1]\ : DFN1E1C0 - port map(D => N_1085, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data_1[1]_net_1\); - - \count_send_time[28]\ : DFN1 - port map(D => \count_send_time_RNO[28]_net_1\, CLK => - lclk_c, Q => \count_send_time[28]_net_1\); - - \sel_data_0_RNIC7S6[0]\ : OR2B - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => \un5_time_write\); - - \count_send_time_RNIGFVB1[14]\ : NOR3C - port map(A => state_tr13_0_a2_17_0, B => - state_tr13_0_a2_17_1, C => state_tr13_0_a2_7, Y => - \state_ns_i_a2_0_a4_0_19_11[5]\); - - \sel_data_RNI1URK[0]\ : MX2C - port map(A => N_1381, B => N_1357, S => \sel_data[0]_net_1\, - Y => \data_address[18]\); - - \count_send_time_RNIRJVA[24]\ : NOR2 - port map(A => \count_send_time[24]_net_1\, B => - \count_send_time[25]_net_1\, Y => state_tr13_0_a2_17_1); - - \count_send_time_RNIFE5M2[17]\ : OR3C - port map(A => N_1131, B => \count_send_time[17]_net_1\, C - => \count_send_time[18]_net_1\, Y => N_1133); - - \count_send_time[8]\ : DFN1 - port map(D => count_send_time_e8, CLK => lclk_c, Q => - \count_send_time[8]_net_1\); - - \count_send_time_RNO[13]\ : OR3C - port map(A => N_1157, B => N_1156, C => N_1155, Y => - count_send_time_e13); - - \state[7]\ : DFN1P0 - port map(D => \state_RNO[7]_net_1\, CLK => lclk_c, PRE => - rstn, Q => \state[7]_net_1\); - - \state_RNILE0L_0[3]\ : NOR2A - port map(A => \state[3]_net_1\, B => un1_time_send_ok, Y - => N_1103); - - \count_send_time_RNO[3]\ : OR3C - port map(A => N_1319, B => N_1317, C => N_1316, Y => - count_send_time_e3); - - \count_send_time[10]\ : DFN1 - port map(D => count_send_time_e10, CLK => lclk_c, Q => - \count_send_time[10]_net_1\); - - \count_send_time_RNO_2[30]\ : OR2B - port map(A => \count_send_time[30]_net_1\, B => N_1290, Y - => N_1197); - - \sel_data_0_RNITBNG[0]\ : MX2C - port map(A => N_1392, B => N_1354, S => - \sel_data_0[0]_net_1\, Y => \data_address[15]\); - - \state[5]\ : DFN1C0 - port map(D => \state_RNO[5]_net_1\, CLK => lclk_c, CLR => - rstn, Q => \state[5]_net_1\); - - \count_send_time_RNIBV6A1[10]\ : OR3B - port map(A => \count_send_time[9]_net_1\, B => - \count_send_time[10]_net_1\, C => N_1295, Y => N_1229); - - data_send : DFN1E0C0 - port map(D => \state[1]_net_1\, CLK => lclk_c, CLR => rstn, - E => N_864, Q => \data_send\); - - \count_send_time_RNIUT3C3[22]\ : OR3B - port map(A => \count_send_time[21]_net_1\, B => - \count_send_time[22]_net_1\, C => N_1136, Y => N_1139); - - \count_send_time_RNO_1[2]\ : OR2B - port map(A => count_send_time_e2_0_a2_0_0, B => - \state_0[2]_net_1\, Y => N_1312); - - GND_i : GND - port map(Y => \GND\); - - \count_send_time_RNIMRUA[30]\ : NOR2 - port map(A => \count_send_time[23]_net_1\, B => - \count_send_time[30]_net_1\, Y => state_tr13_0_a2_6); - - time_send_RNO : OA1B - port map(A => \state[4]_net_1\, B => \state[6]_net_1\, C - => N_1096, Y => time_send_0_sqmuxa); - - \state_RNIE50G[5]\ : NOR3 - port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C - => \state[0]_net_1\, Y => N_868); - - \count_send_time_RNO_3[24]\ : NOR2B - port map(A => \count_send_time[24]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e24_0_a2_0_0); - - \count_send_time_RNO_0[25]\ : OR3 - port map(A => N_1213, B => \count_send_time[25]_net_1\, C - => N_1215_0, Y => N_1250); - - \sel_data_RNIMVTO[0]\ : MX2C - port map(A => N_1376, B => N_980, S => \sel_data[0]_net_1\, - Y => \data_address[27]\); - - \count_send_time_RNIGLBC2[15]\ : NOR3B - port map(A => N_1129, B => \count_send_time[15]_net_1\, C - => N_1215, Y => N_1147); - - \count_send_time_RNO_3[12]\ : NOR2B - port map(A => \count_send_time[12]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e12_0_a2_0_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \state_RNI4QUO[4]\ : OR3A - port map(A => N_1102, B => \state[4]_net_1\, C => - \state[6]_net_1\, Y => un1_state_12); - - \DMAWriteFSM_p.sel_data_3_i[0]\ : OA1C - port map(A => ready_i_0_2, B => ready_i_0_i_0(1), C => - \sel_data_3_i_0[0]\, Y => N_1086); - - \state_RNO_0[5]\ : OR2A - port map(A => \state[5]_net_1\, B => un1_time_send_ok, Y - => N_1112); - - \state_RNO_0[4]\ : OR2B - port map(A => \state[5]_net_1\, B => un1_time_send_ok, Y - => N_1114); - - \sel_data_0_RNIIV7O[0]\ : MX2C - port map(A => N_1397, B => N_1359, S => - \sel_data_0[0]_net_1\, Y => \data_address[6]\); - - \count_send_time_RNO_3[31]\ : OR3C - port map(A => N_1216, B => \count_send_time[27]_net_1\, C - => N_1231, Y => N_1232); - - \count_send_time_RNO_1[25]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[25]_net_1\, C => N_1213, Y => N_1248); - - \count_send_time_RNO_2[25]\ : OR2B - port map(A => \count_send_time[25]_net_1\, B => N_1290, Y - => N_1247); - - \count_send_time_RNO_6[30]\ : OR3B - port map(A => \count_send_time[28]_net_1\, B => - \count_send_time[29]_net_1\, C => - \count_send_time[30]_net_1\, Y => - count_send_time_e30_0_a2_2_0); - - \state_RNO_0[7]\ : OAI1 - port map(A => data_send_ko, B => data_send_ok, C => - \state[0]_net_1\, Y => N_1109); - - \DMAWriteFSM_p.sel_data_3_i_0[0]\ : AO1D - port map(A => ready_i_0_3, B => ready_i_0_i_0(1), C => - ready_i_0_0, Y => \sel_data_3_i_0[0]\); - - time_write_RNIC7ID_1 : NOR2A - port map(A => \time_write\, B => \un13_time_write\, Y => - un15_time_write); - - \count_send_time_RNIV30B[26]\ : NOR2 - port map(A => \count_send_time[26]_net_1\, B => - \count_send_time[27]_net_1\, Y => state_tr13_0_a2_17_0); - - \count_send_time_RNIKICT[0]\ : NOR3C - port map(A => \state_ns_i_a2_0_a4_0_25_1[5]\, B => - \state_ns_i_a2_0_a4_0_25_0[5]\, C => - \state_ns_i_a2_0_a4_0_25_4[5]\, Y => N_1117_25); - - \count_send_time_RNI2PBI[29]\ : NOR3 - port map(A => \count_send_time[29]_net_1\, B => - \count_send_time[28]_net_1\, C => N_1117_5, Y => - state_tr13_0_a2_8); - - time_write_RNIC7ID : NOR2A - port map(A => \time_write\, B => \un5_time_write\, Y => - un7_time_write); - - \count_send_time[7]\ : DFN1 - port map(D => \count_send_time_RNO[7]_net_1\, CLK => lclk_c, - Q => \count_send_time[7]_net_1\); - - \count_send_time_RNO[25]\ : OR3C - port map(A => N_1250, B => N_1248, C => N_1247, Y => - count_send_time_e25); - - \all_data_ren.1.data_time_ren_5[1]\ : OR2A - port map(A => \time_ren\, B => \un20_time_write\, Y => - time_ren(1)); - - \count_send_time_RNICVTL[22]\ : NOR3A - port map(A => state_tr13_0_a2_6, B => - \count_send_time[22]_net_1\, C => - \count_send_time[13]_net_1\, Y => state_tr13_0_a2_10); - - \count_send_time_RNO_1[9]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[9]_net_1\, C => N_1295, Y => N_1335); - - \sel_data_RNIEVSO[0]\ : MX2C - port map(A => N_1374, B => N_978, S => \sel_data[0]_net_1\, - Y => \data_address[25]\); - - \count_send_time_RNO[31]\ : OR3C - port map(A => N_1264, B => N_1261, C => N_1263, Y => - count_send_time_e31); - - \state_RNO[1]\ : NOR3C - port map(A => state_tr13_0_a2_14, B => N_1117_25, C => - state_tr13_0_a2_15, Y => \state_ns[6]\); - - \count_send_time_RNIN4B7[4]\ : NOR2 - port map(A => \count_send_time[4]_net_1\, B => - \count_send_time[5]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_0[5]\); - - \count_send_time_RNO_3[22]\ : NOR2B - port map(A => \count_send_time[22]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e22_0_a2_0); - - \update_RNI42QC_2[0]\ : NOR2A - port map(A => \update[0]_net_1\, B => \un27_time_write\, Y - => \update_and_sel_7[0]\); - - time_write_RNIC7ID_0 : NOR2A - port map(A => \time_write\, B => \un20_time_write\, Y => - un22_time_write); - - \count_send_time_RNO_0[13]\ : OR3 - port map(A => N_1127, B => \count_send_time[13]_net_1\, C - => N_1215, Y => N_1157); - - time_select_RNIC84U1J : OR2 - port map(A => \data_ren\, B => \un5_time_write\, Y => - data_ren(3)); - - \sel_data_0[0]\ : DFN1E1C0 - port map(D => N_1086, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data_0[0]_net_1\); - - \count_send_time_RNO_0[14]\ : NOR3A - port map(A => \count_send_time[13]_net_1\, B => N_1127, C - => N_1215, Y => \count_send_time_RNO_0[14]_net_1\); - - \count_send_time_RNO[8]\ : AO1B - port map(A => \count_send_time[8]_net_1\, B => N_1290, C - => count_send_time_e8_0_0, Y => count_send_time_e8); - - \count_send_time[26]\ : DFN1 - port map(D => \count_send_time_RNO[26]_net_1\, CLK => - lclk_c, Q => \count_send_time[26]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \count_send_time_RNIK7VL[20]\ : OR3A - port map(A => \state_ns_i_a2_0_a4_0_19_11_0[5]\, B => - \count_send_time[21]_net_1\, C => - \count_send_time[20]_net_1\, Y => state_tr13_0_a2_11); - - \sel_data[1]\ : DFN1E1C0 - port map(D => N_1085, CLK => lclk_c, CLR => rstn, E => - \state[7]_net_1\, Q => \sel_data[1]_net_1\); - - \all_time_write.0.time_already_send[0]\ : DFN1E1C0 - port map(D => un29_time_write, CLK => lclk_c, CLR => rstn, - E => un17_status_full_ack, Q => \time_already_send[0]\); - - \count_send_time[29]\ : DFN1 - port map(D => \count_send_time_RNO[29]_net_1\, CLK => - lclk_c, Q => \count_send_time[29]_net_1\); - - \send_16_3_time[1]\ : DFN1E0C0 - port map(D => \send_16_3_time[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => N_1084, Q => \send_16_3_time[1]_net_1\); - - \count_send_time_RNI6GAK2[20]\ : NOR3B - port map(A => state_tr13_0_a2_8, B => - \state_ns_i_a2_0_a4_0_19_11[5]\, C => state_tr13_0_a2_11, - Y => \state_ns_i_a2_0_a4_0_19_14[5]\); - - \state_RNO[4]\ : AO1B - port map(A => \state[6]_net_1\, B => N_1096, C => N_1114, Y - => \state_RNO_0[4]_net_1\); - - \count_send_time_RNO[19]\ : OR3C - port map(A => N_1174, B => N_1173, C => N_1172, Y => - count_send_time_e19); - - send_16_3_time_1_sqmuxa_i_o3_0 : NOR3 - port map(A => ready_i_0_i_0(1), B => ready_i_0_3, C => - ready_i_0_2, Y => \send_16_3_time_1_sqmuxa_i_o3_0\); - - \state_RNI7A1C[2]\ : OR3B - port map(A => \state[7]_net_1\, B => rstn, C => - \state[2]_net_1\, Y => N_1161); - - \count_send_time_RNI60NP[6]\ : NOR2B - port map(A => \count_send_time[6]_net_1\, B => N_1291, Y - => N_1293); - - \all_time_write.3.time_already_send_RNO[3]\ : OR2 - port map(A => status_full_ack(3), B => un7_time_write, Y - => un2_status_full_ack); - - \sel_data_RNIHTPK[0]\ : MX2C - port map(A => N_1391, B => N_1353, S => \sel_data[0]_net_1\, - Y => \data_address[14]\); - - \count_send_time_RNO_1[30]\ : AOI1B - port map(A => count_send_time_e30_0_a2_0, B => N_1161, C - => N_1196, Y => count_send_time_e30_0_0); - - \count_send_time[13]\ : DFN1 - port map(D => count_send_time_e13, CLK => lclk_c, Q => - \count_send_time[13]_net_1\); - - \count_send_time[12]\ : DFN1 - port map(D => count_send_time_e12, CLK => lclk_c, Q => - \count_send_time[12]_net_1\); - - \DMAWriteFSM_p.sel_data_3_i[1]\ : NOR3 - port map(A => N_1106, B => ready_i_0_i_0(1), C => - ready_i_0_0, Y => N_1085); - - \count_send_time_RNO_0[12]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e12_0_a2_1_0, - C => N_1151, Y => count_send_time_e12_0_0); - - \count_send_time_RNO[24]\ : AO1B - port map(A => \count_send_time[24]_net_1\, B => N_1290, C - => count_send_time_e24_0_0, Y => count_send_time_e24); - - \count_send_time_RNO_2[3]\ : OR2B - port map(A => \count_send_time[3]_net_1\, B => N_1290, Y - => N_1316); - - \count_send_time_RNO_0[30]\ : OR2 - port map(A => count_send_time_e30_0_a2_2_1, B => N_1215_0, - Y => N_1198); - - \count_send_time_RNO_1[13]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[13]_net_1\, C => N_1127, Y => N_1156); - - \sel_data_RNIDDPK[0]\ : MX2C - port map(A => N_1390, B => N_1352, S => \sel_data[0]_net_1\, - Y => \data_address[13]\); - - \count_send_time_RNO_2[19]\ : OR2B - port map(A => \count_send_time[19]_net_1\, B => N_1290, Y - => N_1172); - - \count_send_time_RNO_1[14]\ : AO1C - port map(A => N_1215_0, B => N_1129, C => N_1161, Y => - count_send_time_e14_i_0); - - \count_send_time_RNO_0[6]\ : OA1C - port map(A => N_1291, B => N_1215, C => - \count_send_time[6]_net_1\, Y => N_1323); - - \count_send_time_RNO_0[11]\ : OR3 - port map(A => N_1229, B => \count_send_time[11]_net_1\, C - => N_1215_0, Y => N_1240); - - \all_time_write.2.time_already_send[2]\ : DFN1E1C0 - port map(D => un15_time_write, CLK => lclk_c, CLR => rstn, - E => un7_status_full_ack, Q => \time_already_send[2]\); - - \count_send_time_RNI35211[7]\ : OR3C - port map(A => N_1293, B => \count_send_time[7]_net_1\, C - => \count_send_time[8]_net_1\, Y => N_1295); - - \count_send_time[4]\ : DFN1 - port map(D => \count_send_time_RNO[4]_net_1\, CLK => lclk_c, - Q => \count_send_time[4]_net_1\); - - \state_RNO[6]\ : NOR2A - port map(A => N_1099, B => state_tr2_i_0, Y => - \state_RNO[6]_net_1\); - - \count_send_time[3]\ : DFN1 - port map(D => count_send_time_e3, CLK => lclk_c, Q => - \count_send_time[3]_net_1\); - - \count_send_time_RNO_0[29]\ : NOR2B - port map(A => \count_send_time[28]_net_1\, B => N_1226, Y - => N_1230); - - \count_send_time_RNO[1]\ : AO1B - port map(A => \count_send_time[1]_net_1\, B => N_1290, C - => count_send_time_e1_0_0, Y => count_send_time_e1); - - \count_send_time_RNO_1[3]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[3]_net_1\, C => N_1287, Y => N_1317); - - \sel_data_0_RNIND6K[0]\ : MX2C - port map(A => N_1394, B => N_1370, S => - \sel_data_0[0]_net_1\, Y => \data_address[3]\); - - \all_data_ren.0.data_time_ren_7[0]\ : OR2A - port map(A => \time_ren\, B => \un27_time_write\, Y => - time_ren(0)); - - \count_send_time_RNO[20]\ : AO1B - port map(A => \count_send_time[20]_net_1\, B => N_1290, C - => count_send_time_e20_0_0, Y => count_send_time_e20); - - \state_RNO[7]\ : AO1C - port map(A => N_1099, B => \state[7]_net_1\, C => N_1109, Y - => \state_RNO[7]_net_1\); - - \count_send_time[2]\ : DFN1 - port map(D => count_send_time_e2, CLK => lclk_c, Q => - \count_send_time[2]_net_1\); - - \count_send_time_RNO_2[10]\ : AO1C - port map(A => N_1295, B => \count_send_time[9]_net_1\, C - => count_send_time_e10_0_a2_0, Y => N_1340); - - \count_send_time_RNIIS9E4[27]\ : NOR3B - port map(A => N_1216, B => \count_send_time[27]_net_1\, C - => N_1215, Y => N_1226); - - \count_send_time_RNO_0[26]\ : OR3A - port map(A => \count_send_time[25]_net_1\, B => N_1213, C - => N_1215, Y => N_1233); - - \count_send_time_RNI61892[31]\ : NOR3C - port map(A => state_tr13_0_a2_10, B => state_tr13_0_a2_9, C - => N_1117_25, Y => \state_ns_i_a2_0_a4_0_19_15[5]\); - - \state_RNI9NH4I4[4]\ : AO1B - port map(A => \state[4]_net_1\, B => N_1096, C => - \state_ns_i_a2_0_1[5]\, Y => \state_RNI9NH4I4[4]_net_1\); - - \count_send_time_RNO[18]\ : AO1B - port map(A => \count_send_time[18]_net_1\, B => N_1290, C - => count_send_time_e18_0_0, Y => count_send_time_e18); - - \state_RNO_0[1]\ : NOR3C - port map(A => \state_0[2]_net_1\, B => state_tr13_0_a2_7, C - => state_tr13_0_a2_10, Y => state_tr13_0_a2_14); - - \state_RNO_2[1]\ : NOR3B - port map(A => state_tr13_0_a2_17_0, B => - state_tr13_0_a2_17_1, C => state_tr13_0_a2_11, Y => - state_tr13_0_a2_12); - - \count_send_time_RNO[6]\ : NOR3A - port map(A => N_1161, B => N_1300, C => N_1323, Y => - \count_send_time_RNO[6]_net_1\); - - \sel_data_0_RNIJD6K[0]\ : MX2C - port map(A => N_1393, B => N_1369, S => - \sel_data_0[0]_net_1\, Y => \data_address[2]\); - - \gen_select_address.1.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I_2\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(1) => status_full_err(1), status_full(1) - => status_full(1), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, - update_and_sel_5(3) => \update_and_sel_5[3]\, - update_and_sel_5(2) => \update_and_sel_5[2]\, - sel_data_0(1) => \sel_data_0[1]_net_1\, addr_data_f1(31) - => addr_data_f1(31), addr_data_f1(30) => - addr_data_f1(30), addr_data_f1(29) => addr_data_f1(29), - addr_data_f1(28) => addr_data_f1(28), addr_data_f1(27) - => addr_data_f1(27), addr_data_f1(26) => - addr_data_f1(26), addr_data_f1(25) => addr_data_f1(25), - addr_data_f1(24) => addr_data_f1(24), addr_data_f1(23) - => addr_data_f1(23), addr_data_f1(22) => - addr_data_f1(22), addr_data_f1(21) => addr_data_f1(21), - addr_data_f1(20) => addr_data_f1(20), addr_data_f1(19) - => addr_data_f1(19), addr_data_f1(18) => - addr_data_f1(18), addr_data_f1(17) => addr_data_f1(17), - addr_data_f1(16) => addr_data_f1(16), addr_data_f1(15) - => addr_data_f1(15), addr_data_f1(14) => - addr_data_f1(14), addr_data_f1(13) => addr_data_f1(13), - addr_data_f1(12) => addr_data_f1(12), addr_data_f1(11) - => addr_data_f1(11), addr_data_f1(10) => - addr_data_f1(10), addr_data_f1(9) => addr_data_f1(9), - addr_data_f1(8) => addr_data_f1(8), addr_data_f1(7) => - addr_data_f1(7), addr_data_f1(6) => addr_data_f1(6), - addr_data_f1(5) => addr_data_f1(5), addr_data_f1(4) => - addr_data_f1(4), addr_data_f1(3) => addr_data_f1(3), - addr_data_f1(2) => addr_data_f1(2), addr_data_f1(1) => - addr_data_f1(1), addr_data_f1(0) => addr_data_f1(0), - status_full_ack(1) => status_full_ack(1), - addr_data_vector_69 => \addr_data_vector[101]\, - addr_data_vector_95 => \addr_data_vector[127]\, - addr_data_vector_94 => \addr_data_vector[126]\, - addr_data_vector_93 => \addr_data_vector[125]\, - addr_data_vector_91 => \addr_data_vector[123]\, - addr_data_vector_89 => \addr_data_vector[121]\, - addr_data_vector_88 => \addr_data_vector[120]\, - addr_data_vector_85 => \addr_data_vector[117]\, - addr_data_vector_68 => \addr_data_vector[100]\, - addr_data_vector_67 => \addr_data_vector[99]\, - addr_data_vector_66 => \addr_data_vector[98]\, - addr_data_vector_65 => \addr_data_vector[97]\, - addr_data_vector_74 => \addr_data_vector[106]\, - addr_data_vector_72 => \addr_data_vector[104]\, - addr_data_vector_71 => \addr_data_vector[103]\, - addr_data_vector_70 => \addr_data_vector[102]\, - addr_data_vector_82 => \addr_data_vector[114]\, - addr_data_vector_78 => \addr_data_vector[110]\, - addr_data_vector_87 => \addr_data_vector[119]\, - addr_data_vector_84 => \addr_data_vector[116]\, - addr_data_vector_64 => \addr_data_vector[96]\, - addr_data_vector_80 => \addr_data_vector[112]\, - addr_data_vector_76 => \addr_data_vector[108]\, - addr_data_vector_28 => \addr_data_vector[60]\, - addr_data_vector_26 => \addr_data_vector[58]\, - addr_data_vector_13 => \addr_data_vector[45]\, - addr_data_vector_11 => \addr_data_vector[43]\, - addr_data_vector_9 => \addr_data_vector[41]\, - addr_data_vector_15 => \addr_data_vector[47]\, - addr_data_vector_17 => \addr_data_vector[49]\, - addr_data_vector_19 => \addr_data_vector[51]\, - addr_data_vector_22 => \addr_data_vector[54]\, N_1358 => - N_1358, N_984 => N_984, N_983 => N_983, N_982 => N_982, - N_980 => N_980, N_978 => N_978, N_977 => N_977, N_974 => - N_974, N_1371 => N_1371, N_1370 => N_1370, N_1369 => - N_1369, N_1368 => N_1368, N_1363 => N_1363, N_1361 => - N_1361, N_1360 => N_1360, N_1359 => N_1359, N_1357 => - N_1357, N_1353 => N_1353, N_976 => N_976, N_973 => N_973, - N_1367 => N_1367, N_1355 => N_1355, N_1351 => N_1351, - rstn => rstn, lclk_c => lclk_c); - - \count_send_time[24]\ : DFN1 - port map(D => count_send_time_e24, CLK => lclk_c, Q => - \count_send_time[24]_net_1\); - - \all_data_ren.3.data_time_ren_1[3]\ : OR2A - port map(A => \time_ren\, B => \un5_time_write\, Y => - time_ren(3)); - - \count_send_time_RNO_1[12]\ : OR3A - port map(A => \count_send_time[11]_net_1\, B => N_1229, C - => \count_send_time[12]_net_1\, Y => - count_send_time_e12_0_a2_1_0); - - \update_RNO[0]\ : OA1 - port map(A => \state[3]_net_1\, B => \state[5]_net_1\, C - => un1_time_send_ok, Y => update_0_sqmuxa); - - \count_send_time_RNO_0[20]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e20_0_a2_1_0, - C => N_1177, Y => count_send_time_e20_0_0); - - \count_send_time_RNO[23]\ : OR3C - port map(A => N_1193, B => N_1191, C => N_1192, Y => - count_send_time_e23); - - \count_send_time_RNO_1[11]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[11]_net_1\, C => N_1229, Y => N_1237); - - \count_send_time_RNO[11]\ : OR3C - port map(A => N_1240, B => N_1237, C => N_1239, Y => - count_send_time_e11); - - \count_send_time[27]\ : DFN1 - port map(D => \count_send_time_RNO[27]_net_1\, CLK => - lclk_c, Q => \count_send_time[27]_net_1\); - - \count_send_time_RNIV4B7[8]\ : OR2 - port map(A => \count_send_time[9]_net_1\, B => - \count_send_time[8]_net_1\, Y => N_1117_5); - - \count_send_time_RNO_1[20]\ : OR3A - port map(A => \count_send_time[19]_net_1\, B => N_1133, C - => \count_send_time[20]_net_1\, Y => - count_send_time_e20_0_a2_1_0); - - \count_send_time_RNO_4[2]\ : AOI1B - port map(A => \count_send_time[1]_net_1\, B => - \count_send_time[0]_net_1\, C => - \count_send_time[2]_net_1\, Y => - count_send_time_e2_0_a2_0_0); - - \count_send_time_RNO_2[20]\ : AO1C - port map(A => N_1133, B => \count_send_time[19]_net_1\, C - => count_send_time_e20_0_a2_0, Y => N_1177); - - time_fifo_ren_RNI89I5 : NOR2A - port map(A => \time_select\, B => \time_fifo_ren\, Y => - \time_ren\); - - \count_send_time_RNO_0[17]\ : OA1C - port map(A => N_1131, B => N_1215, C => - \count_send_time[17]_net_1\, Y => N_1166); - - \state[3]\ : DFN1C0 - port map(D => \state_RNO_1[3]\, CLK => lclk_c, CLR => rstn, - Q => \state[3]_net_1\); - - time_fifo_ren : DFN1E0P0 - port map(D => time_fifo_ren_1_i, CLK => lclk_c, PRE => rstn, - E => \state[0]_net_1\, Q => \time_fifo_ren\); - - time_write_RNO_0 : OR2 - port map(A => \state[1]_net_1\, B => \state[3]_net_1\, Y - => un1_state_13_0_a4_0_0); - - time_select_RNI018N1J : OR2A - port map(A => data_fifo_ren, B => \time_select\, Y => - \data_ren\); - - \count_send_time_RNO_1[1]\ : OR2A - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, Y => - count_send_time_e1_0_a2_1_0); - - time_select_0 : DFN1E1C0 - port map(D => time_fifo_ren_1, CLK => lclk_c, CLR => rstn, - E => N_868, Q => \time_select_0\); - - \sel_data_0_RNIDSOG[0]\ : MX2C - port map(A => N_1377, B => N_981, S => - \sel_data_0[0]_net_1\, Y => \data_address[28]\); - - \count_send_time_RNIDPBN2[17]\ : NOR3B - port map(A => N_1131, B => \count_send_time[17]_net_1\, C - => N_1215, Y => N_1207); - - \count_send_time_RNO_0[18]\ : OA1A - port map(A => N_1207, B => \count_send_time[18]_net_1\, C - => N_1169, Y => count_send_time_e18_0_0); - - lpp_dma_send_1word_1 : lpp_dma_send_1word - port map(Request => Request, Store => Store, rstn => rstn, - lclk_c => lclk_c, Grant => Grant, un1_time_send_ok => - un1_time_send_ok, Fault => Fault, Ready => Ready, - time_select_0 => \time_select_0\, Lock => Lock, - Lock_RNIU86D => Lock_RNIU86D, time_send => \time_send\); - - \all_time_write.1.time_already_send_RNI9NDDV[1]\ : MX2 - port map(A => N_1094, B => \time_already_send[1]\, S => - ready_i_0_i_0(1), Y => N_1095); - - \all_time_write.0.time_already_send_RNO[0]\ : OR2 - port map(A => status_full_ack(0), B => un29_time_write, Y - => un17_status_full_ack); - - \count_send_time_RNIPD1M[5]\ : NOR2B - port map(A => \count_send_time[5]_net_1\, B => N_1289, Y - => N_1291); - - \sel_data_RNIO2D01[0]\ : MX2C - port map(A => N_1396, B => N_1358, S => \sel_data[0]_net_1\, - Y => \data_address[5]\); - - \count_send_time_RNO_2[31]\ : OR2B - port map(A => \count_send_time[31]_net_1\, B => N_1290, Y - => N_1263); - - \count_send_time_RNIG25B2[16]\ : NOR3C - port map(A => N_1129, B => \count_send_time[15]_net_1\, C - => \count_send_time[16]_net_1\, Y => N_1131); - - \count_send_time[11]\ : DFN1 - port map(D => count_send_time_e11, CLK => lclk_c, Q => - \count_send_time[11]_net_1\); - - \state_RNIUIM6[2]\ : OR2B - port map(A => \state[2]_net_1\, B => rstn, Y => N_1215); - - \count_send_time[1]\ : DFN1 - port map(D => count_send_time_e1, CLK => lclk_c, Q => - \count_send_time[1]_net_1\); - - \count_send_time[9]\ : DFN1 - port map(D => count_send_time_e9, CLK => lclk_c, Q => - \count_send_time[9]_net_1\); - - \count_send_time_RNI29ME[0]\ : NOR3B - port map(A => \count_send_time[1]_net_1\, B => - \state_ns_i_a2_0_a4_0_25_2[5]\, C => - \count_send_time[0]_net_1\, Y => - \state_ns_i_a2_0_a4_0_25_4[5]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \count_send_time_RNO_1[8]\ : OR3B - port map(A => N_1293, B => \count_send_time[7]_net_1\, C - => \count_send_time[8]_net_1\, Y => - count_send_time_e8_0_a2_1_0); - - time_select_0_RNIA57D : NOR2 - port map(A => \time_select_0\, B => \un27_time_write\, Y - => \data_data_ren_7_0[0]\); - - \sel_data_RNIAFSO[0]\ : MX2C - port map(A => N_1373, B => N_977, S => \sel_data[0]_net_1\, - Y => \data_address[24]\); - - \count_send_time[20]\ : DFN1 - port map(D => count_send_time_e20, CLK => lclk_c, Q => - \count_send_time[20]_net_1\); - - \count_send_time[30]\ : DFN1 - port map(D => count_send_time_e30, CLK => lclk_c, Q => - \count_send_time[30]_net_1\); - - \count_send_time[15]\ : DFN1 - port map(D => \count_send_time_RNO[15]_net_1\, CLK => - lclk_c, Q => \count_send_time[15]_net_1\); - - \count_send_time_RNO[16]\ : OA1B - port map(A => N_1147, B => \count_send_time[16]_net_1\, C - => count_send_time_e16_i_0, Y => - \count_send_time_RNO[16]_net_1\); - - \send_16_3_time_RNIBIDUD2[0]\ : OR2B - port map(A => \state_ns_i_a2_0_a3_0[5]\, B => N_1099, Y => - N_1118); - - \DMAWriteFSM_p.sel_data_3_i_a4[1]\ : NOR2 - port map(A => ready_i_0_3, B => ready_i_0_2, Y => N_1106); - - \state_RNO[5]\ : AO1C - port map(A => N_1096, B => \state[6]_net_1\, C => N_1112, Y - => \state_RNO[5]_net_1\); - - \sel_data_0_RNIHRLG[0]\ : MX2C - port map(A => N_1389, B => N_1351, S => - \sel_data_0[0]_net_1\, Y => \data_address[12]\); - - \state_0_RNILB42[2]\ : OR2B - port map(A => \state_0[2]_net_1\, B => rstn, Y => N_1215_0); - - \sel_data_0_RNIC7S6_2[0]\ : OR2 - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => \un27_time_write\); - - \sel_data_0_RNIC7S6_1[0]\ : OR2A - port map(A => \sel_data[1]_net_1\, B => - \sel_data_0[0]_net_1\, Y => \un13_time_write\); - - \count_send_time_RNO_1[18]\ : AO1B - port map(A => \count_send_time[17]_net_1\, B => N_1131, C - => count_send_time_e18_0_a2_0_0, Y => N_1169); - - \update_RNI56QC_1[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un13_time_write\, Y - => \update_and_sel_3[5]\); - - \sel_data_0_RNIKGEC[0]\ : OR2A - port map(A => \time_ren\, B => \un13_time_write\, Y => - time_ren(2)); - - \sel_data_RNI2FRO[0]\ : MX2C - port map(A => N_1385, B => N_975, S => \sel_data[0]_net_1\, - Y => \data_address[22]\); - - \count_send_time[18]\ : DFN1 - port map(D => count_send_time_e18, CLK => lclk_c, Q => - \count_send_time[18]_net_1\); - - \count_send_time_RNIDRBI[4]\ : NOR3B - port map(A => \count_send_time[3]_net_1\, B => - \count_send_time[4]_net_1\, C => N_1287, Y => N_1289); - - \sel_data_0_RNIMV7O[0]\ : MX2C - port map(A => N_1398, B => N_1360, S => - \sel_data_0[0]_net_1\, Y => \data_address[7]\); - - \count_send_time_RNO_0[15]\ : OA1C - port map(A => N_1129, B => N_1215, C => - \count_send_time[15]_net_1\, Y => N_1162); - - \count_send_time_RNO[12]\ : AO1B - port map(A => \count_send_time[12]_net_1\, B => N_1290, C - => count_send_time_e12_0_0, Y => count_send_time_e12); - - \state[2]\ : DFN1C0 - port map(D => \state_RNI9NH4I4[4]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \state[2]_net_1\); - - \count_send_time_RNO_5[30]\ : AO1B - port map(A => \count_send_time[27]_net_1\, B => N_1216, C - => count_send_time_e30_0_a2_0_0, Y => N_1196); - - \send_16_3_time[0]\ : DFN1E0P0 - port map(D => \send_16_3_time[2]_net_1\, CLK => lclk_c, PRE - => rstn, E => N_1084, Q => \send_16_3_time[0]_net_1\); - - \count_send_time_RNO_3[8]\ : NOR2B - port map(A => \count_send_time[8]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e8_0_a2_0); - - \count_send_time_RNO_0[8]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e8_0_a2_1_0, C - => N_1330, Y => count_send_time_e8_0_0); - - \count_send_time_RNO[29]\ : XA1 - port map(A => N_1230, B => \count_send_time[29]_net_1\, C - => N_1161, Y => \count_send_time_RNO[29]_net_1\); - - \count_send_time_RNI1K0B[18]\ : NOR2 - port map(A => \count_send_time[18]_net_1\, B => - \count_send_time[19]_net_1\, Y => - \state_ns_i_a2_0_a4_0_19_11_0[5]\); - - \count_send_time[6]\ : DFN1 - port map(D => \count_send_time_RNO[6]_net_1\, CLK => lclk_c, - Q => \count_send_time[6]_net_1\); - - \send_16_3_time[2]\ : DFN1E0C0 - port map(D => \send_16_3_time[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => N_1084, Q => \send_16_3_time[2]_net_1\); - - \sel_data_RNIGGSS[0]\ : MX2C - port map(A => N_1365, B => N_983, S => \sel_data[0]_net_1\, - Y => \data_address[30]\); - - \state_0[2]\ : DFN1C0 - port map(D => \state_RNI9NH4I4[4]_net_1\, CLK => lclk_c, - CLR => rstn, Q => \state_0[2]_net_1\); - - \state[1]\ : DFN1C0 - port map(D => \state_ns[6]\, CLK => lclk_c, CLR => rstn, Q - => \state[1]_net_1\); - - send_16_3_time_1_sqmuxa_i_o3 : OR2A - port map(A => \send_16_3_time_1_sqmuxa_i_o3_0\, B => - ready_i_0_0, Y => N_1099); - - \state_RNIG8T25[2]\ : AO1B - port map(A => \state_ns_i_a2_0_a4_0_19_15[5]\, B => - \state_ns_i_a2_0_a4_0_19_14[5]\, C => \state[2]_net_1\, Y - => N_899_tz); - - \sel_data_0_RNICT5K[0]\ : MX2C - port map(A => N_1350, B => N_1368, S => - \sel_data_0[0]_net_1\, Y => \data_address[1]\); - - \count_send_time_RNO[17]\ : NOR3A - port map(A => N_1161, B => N_1207, C => N_1166, Y => - \count_send_time_RNO[17]_net_1\); - - time_send_RNO_0 : NOR2 - port map(A => \state[2]_net_1\, B => \state[0]_net_1\, Y - => N_867); - - \sel_data_0_RNIDRKG[0]\ : MX2C - port map(A => N_1383, B => N_973, S => - \sel_data_0[0]_net_1\, Y => \data_address[20]\); - - \state_RNO_0[6]\ : OR2B - port map(A => \send_16_3_time[0]_net_1\, B => - \state[7]_net_1\, Y => state_tr2_i_0); - - \count_send_time_RNO_2[2]\ : OR2B - port map(A => \count_send_time[2]_net_1\, B => N_1290, Y - => N_1311); - - \all_time_write.1.time_already_send_RNO[1]\ : OR2 - port map(A => status_full_ack(1), B => un22_time_write, Y - => un12_status_full_ack); - - \state_RNO[3]\ : AO1A - port map(A => N_1096, B => \state[4]_net_1\, C => N_1103, Y - => \state_RNO_1[3]\); - - \state_RNO[0]\ : OR2A - port map(A => N_1102, B => \state[1]_net_1\, Y => - \state_RNO_0[0]\); - - \count_send_time_RNIUQ5L1[12]\ : OR3B - port map(A => \count_send_time[11]_net_1\, B => - \count_send_time[12]_net_1\, C => N_1229, Y => N_1127); - - \count_send_time_RNO_2[13]\ : OR2B - port map(A => \count_send_time[13]_net_1\, B => N_1290, Y - => N_1155); - - \state_RNO_1[1]\ : NOR3C - port map(A => state_tr13_0_a2_9, B => state_tr13_0_a2_8, C - => state_tr13_0_a2_12, Y => state_tr13_0_a2_15); - - \count_send_time_RNO_0[4]\ : OR3A - port map(A => \count_send_time[3]_net_1\, B => N_1287, C - => N_1215, Y => N_1297); - - \update_RNI56QC[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un5_time_write\, Y - => \update_and_sel_1[7]\); - - time_select_0_RNIFGR22J : OR2B - port map(A => \data_data_ren_7_0[0]\, B => data_fifo_ren, Y - => data_ren(0)); - - \count_send_time_RNI4JD01[6]\ : NOR2A - port map(A => N_1293, B => N_1215, Y => N_1300); - - time_write_RNIC7ID_2 : NOR2A - port map(A => \time_write\, B => \un27_time_write\, Y => - un29_time_write); - - \sel_data_RNI4DOK[0]\ : MX2C - port map(A => N_1387, B => N_1363, S => \sel_data[0]_net_1\, - Y => \data_address[10]\); - - \count_send_time_RNO_1[31]\ : OR3C - port map(A => \state_0[2]_net_1\, B => - \count_send_time[31]_net_1\, C => N_1232, Y => N_1261); - - \count_send_time_RNO_0[5]\ : OR2A - port map(A => N_1289, B => N_1215, Y => N_1298); - - \sel_data_0_RNIPBMG[0]\ : MX2C - port map(A => N_1372, B => N_976, S => - \sel_data_0[0]_net_1\, Y => \data_address[23]\); - - \count_send_time_RNO_3[30]\ : OR3B - port map(A => N_1216, B => \count_send_time[27]_net_1\, C - => count_send_time_e30_0_a2_2_0, Y => - count_send_time_e30_0_a2_2_1); - - \count_send_time_RNO_0[23]\ : OR3 - port map(A => N_1139, B => \count_send_time[23]_net_1\, C - => N_1215_0, Y => N_1193); - - \count_send_time_RNO_0[24]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e24_0_a2_1_0, - C => N_1243, Y => count_send_time_e24_0_0); - - time_send : DFN1E1C0 - port map(D => time_send_0_sqmuxa, CLK => lclk_c, CLR => - rstn, E => N_867, Q => \time_send\); - - \sel_data_RNIQVUO[0]\ : MX2C - port map(A => N_1382, B => N_972, S => \sel_data[0]_net_1\, - Y => \data_address[19]\); - - \count_send_time_RNO_0[31]\ : OR3B - port map(A => N_1231, B => N_1226, C => - \count_send_time[31]_net_1\, Y => N_1264); - - \count_send_time_RNO_3[10]\ : NOR2B - port map(A => \count_send_time[10]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e10_0_a2_0); - - \all_time_write.2.time_already_send_RNINRRD9[2]\ : MX2 - port map(A => \time_already_send[3]\, B => - \time_already_send[2]\, S => ready_i_0_2, Y => N_1094); - - \count_send_time_RNO_0[1]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e1_0_a2_1_0, C - => N_1307, Y => count_send_time_e1_0_0); - - \update_RNI42QC_0[0]\ : NOR2A - port map(A => \update[0]_net_1\, B => \un20_time_write\, Y - => \update_and_sel_5[2]\); - - \update[0]\ : DFN1E0C0 - port map(D => update_0_sqmuxa, CLK => lclk_c, CLR => rstn, - E => un1_state_12, Q => \update[0]_net_1\); - - \count_send_time_RNO_1[23]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[23]_net_1\, C => N_1139, Y => N_1191); - - \count_send_time_RNO[28]\ : XA1 - port map(A => N_1226, B => \count_send_time[28]_net_1\, C - => N_1161, Y => \count_send_time_RNO[28]_net_1\); - - \count_send_time_RNO_2[23]\ : OR2B - port map(A => \count_send_time[23]_net_1\, B => N_1290, Y - => N_1192); - - \count_send_time_RNO_1[24]\ : OR3A - port map(A => \count_send_time[23]_net_1\, B => N_1139, C - => \count_send_time[24]_net_1\, Y => - count_send_time_e24_0_a2_1_0); - - \count_send_time_RNO_2[24]\ : AO1C - port map(A => N_1139, B => \count_send_time[23]_net_1\, C - => count_send_time_e24_0_a2_0_0, Y => N_1243); - - \sel_data_RNIUVUO[0]\ : MX2C - port map(A => N_1378, B => N_982, S => \sel_data[0]_net_1\, - Y => \data_address[29]\); - - \sel_data_RNIUUQO[0]\ : MX2C - port map(A => N_1384, B => N_974, S => \sel_data[0]_net_1\, - Y => \data_address[21]\); - - \count_send_time_RNIJRUA[12]\ : NOR2 - port map(A => \count_send_time[11]_net_1\, B => - \count_send_time[12]_net_1\, Y => state_tr13_0_a2_4); - - \count_send_time_RNI92513[20]\ : OR3B - port map(A => \count_send_time[19]_net_1\, B => - \count_send_time[20]_net_1\, C => N_1133, Y => N_1136); - - \count_send_time[23]\ : DFN1 - port map(D => count_send_time_e23, CLK => lclk_c, Q => - \count_send_time[23]_net_1\); - - \count_send_time[22]\ : DFN1 - port map(D => count_send_time_e22, CLK => lclk_c, Q => - \count_send_time[22]_net_1\); - - \count_send_time_RNIL6502[14]\ : NOR3B - port map(A => \count_send_time[13]_net_1\, B => - \count_send_time[14]_net_1\, C => N_1127, Y => N_1129); - - \sel_data_0_RNIC7S6_0[0]\ : OR2A - port map(A => \sel_data_0[0]_net_1\, B => - \sel_data[1]_net_1\, Y => \un20_time_write\); - - \sel_data_RNI8TOK[0]\ : MX2C - port map(A => N_1388, B => N_1364, S => \sel_data[0]_net_1\, - Y => \data_address[11]\); - - \count_send_time[16]\ : DFN1 - port map(D => \count_send_time_RNO[16]_net_1\, CLK => - lclk_c, Q => \count_send_time[16]_net_1\); - - \count_send_time_RNO[30]\ : OR3C - port map(A => N_1198, B => count_send_time_e30_0_0, C => - N_1197, Y => count_send_time_e30); - - \count_send_time_RNO[21]\ : OR3C - port map(A => N_1184, B => N_1182, C => N_1183, Y => - count_send_time_e21); - - \count_send_time_RNO_2[12]\ : AO1C - port map(A => N_1229, B => \count_send_time[11]_net_1\, C - => count_send_time_e12_0_a2_0_0, Y => N_1151); - - \all_time_write.2.time_already_send_RNO[2]\ : OR2 - port map(A => status_full_ack(2), B => un15_time_write, Y - => un7_status_full_ack); - - \all_time_write.1.time_already_send[1]\ : DFN1E1C0 - port map(D => un22_time_write, CLK => lclk_c, CLR => rstn, - E => un12_status_full_ack, Q => \time_already_send[1]\); - - \gen_select_address.3.lpp_waveform_dma_selectaddress_I\ : - \lpp_waveform_dma_selectaddress_gen_select_address.3.lpp_waveform_dma_selectaddress_I\ - port map(nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(3) => status_full_err(3), status_full(3) - => status_full(3), sel_data(1) => \sel_data[1]_net_1\, - sel_data_1(1) => \sel_data_1[1]_net_1\, sel_data_0(1) => - \sel_data_0[1]_net_1\, addr_data_f3(31) => - addr_data_f3(31), addr_data_f3(30) => addr_data_f3(30), - addr_data_f3(29) => addr_data_f3(29), addr_data_f3(28) - => addr_data_f3(28), addr_data_f3(27) => - addr_data_f3(27), addr_data_f3(26) => addr_data_f3(26), - addr_data_f3(25) => addr_data_f3(25), addr_data_f3(24) - => addr_data_f3(24), addr_data_f3(23) => - addr_data_f3(23), addr_data_f3(22) => addr_data_f3(22), - addr_data_f3(21) => addr_data_f3(21), addr_data_f3(20) - => addr_data_f3(20), addr_data_f3(19) => - addr_data_f3(19), addr_data_f3(18) => addr_data_f3(18), - addr_data_f3(17) => addr_data_f3(17), addr_data_f3(16) - => addr_data_f3(16), addr_data_f3(15) => - addr_data_f3(15), addr_data_f3(14) => addr_data_f3(14), - addr_data_f3(13) => addr_data_f3(13), addr_data_f3(12) - => addr_data_f3(12), addr_data_f3(11) => - addr_data_f3(11), addr_data_f3(10) => addr_data_f3(10), - addr_data_f3(9) => addr_data_f3(9), addr_data_f3(8) => - addr_data_f3(8), addr_data_f3(7) => addr_data_f3(7), - addr_data_f3(6) => addr_data_f3(6), addr_data_f3(5) => - addr_data_f3(5), addr_data_f3(4) => addr_data_f3(4), - addr_data_f3(3) => addr_data_f3(3), addr_data_f3(2) => - addr_data_f3(2), addr_data_f3(1) => addr_data_f3(1), - addr_data_f3(0) => addr_data_f3(0), status_full_ack(3) - => status_full_ack(3), addr_data_vector_56 => - \addr_data_vector[97]\, addr_data_vector_55 => - \addr_data_vector[96]\, addr_data_vector_17 => - \addr_data_vector[58]\, addr_data_vector_13 => - \addr_data_vector[54]\, addr_data_vector_10 => - \addr_data_vector[51]\, addr_data_vector_2 => - \addr_data_vector[43]\, addr_data_vector_0 => - \addr_data_vector[41]\, addr_data_vector_8 => - \addr_data_vector[49]\, addr_data_vector_4 => - \addr_data_vector[45]\, addr_data_vector_63 => - \addr_data_vector[104]\, addr_data_vector_6 => - \addr_data_vector[47]\, addr_data_vector_19 => - \addr_data_vector[60]\, addr_data_vector_62 => - \addr_data_vector[103]\, addr_data_vector_60 => - \addr_data_vector[101]\, addr_data_vector_59 => - \addr_data_vector[100]\, addr_data_vector_58 => - \addr_data_vector[99]\, addr_data_vector_86 => - \addr_data_vector[127]\, addr_data_vector_85 => - \addr_data_vector[126]\, addr_data_vector_84 => - \addr_data_vector[125]\, addr_data_vector_82 => - \addr_data_vector[123]\, addr_data_vector_80 => - \addr_data_vector[121]\, addr_data_vector_79 => - \addr_data_vector[120]\, addr_data_vector_57 => - \addr_data_vector[98]\, addr_data_vector_78 => - \addr_data_vector[119]\, addr_data_vector_67 => - \addr_data_vector[108]\, addr_data_vector_65 => - \addr_data_vector[106]\, addr_data_vector_61 => - \addr_data_vector[102]\, addr_data_vector_73 => - \addr_data_vector[114]\, addr_data_vector_76 => - \addr_data_vector[117]\, addr_data_vector_69 => - \addr_data_vector[110]\, addr_data_vector_71 => - \addr_data_vector[112]\, addr_data_vector_75 => - \addr_data_vector[116]\, update_and_sel_1(7) => - \update_and_sel_1[7]\, update_and_sel_1(6) => - \update_and_sel_1[6]\, N_979 => N_979, N_975 => N_975, - N_972 => N_972, N_1364 => N_1364, N_1362 => N_1362, - N_1356 => N_1356, N_1352 => N_1352, N_1354 => N_1354, - N_981 => N_981, rstn => rstn, lclk_c => lclk_c); - - \sel_data_RNIIFTO[0]\ : MX2C - port map(A => N_1375, B => N_979, S => \sel_data[0]_net_1\, - Y => \data_address[26]\); - - \count_send_time_RNI6FTL[31]\ : NOR3A - port map(A => state_tr13_0_a2_4, B => - \count_send_time[10]_net_1\, C => - \count_send_time[31]_net_1\, Y => state_tr13_0_a2_9); - - \count_send_time_RNO_2[11]\ : OR2B - port map(A => \count_send_time[11]_net_1\, B => N_1290, Y - => N_1239); - - \count_send_time_RNO[5]\ : XA1A - port map(A => N_1298, B => \count_send_time[5]_net_1\, C - => N_1161, Y => \count_send_time_RNO[5]_net_1\); - - \count_send_time[19]\ : DFN1 - port map(D => count_send_time_e19, CLK => lclk_c, Q => - \count_send_time[19]_net_1\); - - \update_RNI42QC[0]\ : NOR2A - port map(A => \update[0]_net_1\, B => \un5_time_write\, Y - => \update_and_sel_1[6]\); - - \count_send_time_RNO_3[20]\ : NOR2B - port map(A => \count_send_time[20]_net_1\, B => - \state_0[2]_net_1\, Y => count_send_time_e20_0_a2_0); - - \count_send_time_RNO_0[22]\ : OA1 - port map(A => N_1215_0, B => count_send_time_e22_0_a2_1_0, - C => N_1187, Y => count_send_time_e22_0_0); - - \count_send_time_RNO[15]\ : NOR3A - port map(A => N_1161, B => N_1147, C => N_1162, Y => - \count_send_time_RNO[15]_net_1\); - - \update_RNI56QC_0[1]\ : NOR2A - port map(A => \update[1]_net_1\, B => \un20_time_write\, Y - => \update_and_sel_5[3]\); - - \sel_data_0_RNI1SNG[0]\ : MX2C - port map(A => N_1379, B => N_1355, S => - \sel_data_0[0]_net_1\, Y => \data_address[16]\); - - \count_send_time_RNIMNVL[14]\ : NOR3A - port map(A => state_tr13_0_a2_1, B => - \count_send_time[15]_net_1\, C => - \count_send_time[14]_net_1\, Y => state_tr13_0_a2_7); - - \count_send_time_RNIOM0B[2]\ : OR3C - port map(A => \count_send_time[0]_net_1\, B => - \count_send_time[1]_net_1\, C => - \count_send_time[2]_net_1\, Y => N_1287); - - \count_send_time_RNO_0[21]\ : OR3 - port map(A => N_1136, B => \count_send_time[21]_net_1\, C - => N_1215, Y => N_1184); - - \count_send_time_RNO_1[22]\ : OR3A - port map(A => \count_send_time[21]_net_1\, B => N_1136, C - => \count_send_time[22]_net_1\, Y => - count_send_time_e22_0_a2_1_0); - - \count_send_time_RNO_2[22]\ : AO1C - port map(A => N_1136, B => \count_send_time[21]_net_1\, C - => count_send_time_e22_0_a2_0, Y => N_1187); - - DMA2AHB_1 : DMA2AHB - port map(hburst(2) => hburst(2), hburst(1) => hburst(1), - hburst(0) => hburst(0), htrans(1) => htrans(1), htrans(0) - => htrans(0), Address_RNIP8BS(0) => \Address_RNIP8BS[0]\, - iosn_2(93) => iosn_2(93), hresp(0) => hresp(0), - Address_RNIJ4SP(20) => \Address_RNIJ4SP[20]\, iosn_1(93) - => iosn_1(93), nhmaster_1_i(0) => nhmaster_1_i(0), - hsize(1) => hsize(1), hsize(0) => hsize(0), un7_dmain(66) - => \un7_dmain[66]\, hmaster_0(1) => hmaster_0(1), - haddr(31) => haddr(31), haddr(30) => haddr(30), haddr(29) - => haddr(29), haddr(28) => haddr(28), haddr(27) => - haddr(27), haddr(26) => haddr(26), haddr(25) => haddr(25), - haddr(24) => haddr(24), haddr(23) => haddr(23), haddr(22) - => haddr(22), haddr(21) => haddr(21), haddr(20) => - haddr(20), haddr(19) => haddr(19), haddr(18) => haddr(18), - haddr(17) => haddr(17), haddr(16) => haddr(16), haddr(15) - => haddr(15), haddr(14) => haddr(14), haddr(13) => - haddr(13), haddr(12) => haddr(12), haddr(11) => haddr(11), - haddr(10) => haddr(10), haddr(9) => haddr(9), haddr(8) - => haddr(8), haddr(7) => haddr(7), haddr(6) => haddr(6), - haddr(5) => haddr(5), haddr(4) => haddr(4), haddr(3) => - haddr(3), haddr(2) => haddr(2), haddr(1) => haddr(1), - haddr(0) => haddr(0), bco_msb_1(1) => bco_msb_1(1), - hmaster_0_0_RNIFCVH1_0(1) => hmaster_0_0_RNIFCVH1_0(1), - hgrant(3) => hgrant(3), iosn_0(93) => iosn_0(93), Ready - => Ready, N_1021 => N_1021, N_1032 => N_1032, N_1027 => - N_1027, OKAY => OKAY, IdlePhase => IdlePhase, N_1018 => - N_1018, N_1025 => N_1025, N_1042 => N_1042, N_1034 => - N_1034, hwrite => hwrite, un1_dmain_6 => un1_dmain_6, - N_1082 => N_1082, N_1048 => N_1048, N_1047 => N_1047, - N_1036 => N_1036, N_1035 => N_1035, N_1019 => N_1019, - N_1046 => N_1046, N_1044 => N_1044, N_1043 => N_1043, - N_1041 => N_1041, N_1040 => N_1040, N_1039 => N_1039, - N_1038 => N_1038, N_1033 => N_1033, N_1031 => N_1031, - N_1030 => N_1030, N_1029 => N_1029, N_1028 => N_1028, - N_1026 => N_1026, N_1024 => N_1024, N_1023 => N_1023, - N_1022 => N_1022, N_1020 => N_1020, N_1045 => N_1045, - Grant_0 => Grant_0, Grant => Grant, arb_1 => arb_1, - N_1081 => N_1081, hbusreq_i_3 => hbusreq_i_3, Grant_1_0 - => Grant_1_0, Fault => Fault, time_select_0 => - \time_select_0\, rstn => rstn, lclk_c => lclk_c); - - \count_send_time_RNO_1[21]\ : OR3C - port map(A => \state[2]_net_1\, B => - \count_send_time[21]_net_1\, C => N_1136, Y => N_1182); - - \count_send_time_RNO_0[19]\ : OR3 - port map(A => N_1133, B => \count_send_time[19]_net_1\, C - => N_1215, Y => N_1174); - - \state_RNILE0L[3]\ : OR2B - port map(A => \state[3]_net_1\, B => un1_time_send_ok, Y - => N_1120); - - \count_send_time_RNO_2[21]\ : OR2B - port map(A => \count_send_time[21]_net_1\, B => N_1290, Y - => N_1183); - - \count_send_time_RNO[9]\ : OR3C - port map(A => N_1338, B => N_1335, C => N_1337, Y => - count_send_time_e9); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform_fifo_arbiter is - - port( wdata : out std_logic_vector(31 downto 0); - data_wen : out std_logic_vector(3 downto 0); - valid_ack : out std_logic_vector(3 downto 0); - time_wen : out std_logic_vector(3 downto 0); - data_f3_out : in std_logic_vector(159 downto 64); - data_f2_out : in std_logic_vector(159 downto 64); - data_f1_out : in std_logic_vector(159 downto 64); - data_f0_out : in std_logic_vector(159 downto 64); - ready_i_0_i_0 : in std_logic_vector(1 to 1); - valid_out_i : in std_logic_vector(1 to 1); - ready_i_0_3 : in std_logic; - ready_i_0_0 : in std_logic; - ready_i_0_2 : in std_logic; - valid_out_3 : in std_logic; - valid_out_0 : in std_logic; - valid_out_2 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_waveform_fifo_arbiter; - -architecture DEF_ARCH of lpp_waveform_fifo_arbiter is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \data_valid_and_ready_3[2]_net_1\, - \data_valid_and_ready_2[2]_net_1\, - \data_valid_and_ready_1[2]_net_1\, - \data_valid_and_ready_0[2]_net_1\, N_863_2, - \data_temp_5_i_a2_0_0[32]_net_1\, N_911, N_863_1, N_863_0, - N_1580_2, \data_valid_and_ready_0[0]_net_1\, - \data_valid_and_ready[1]_net_1\, N_1580_1, N_1580_0, - \data_valid_and_ready_3[0]_net_1\, - \data_valid_and_ready_2[0]_net_1\, - \data_valid_and_ready_1[0]_net_1\, \state[4]_net_1\, - \state_0[4]\, N_857_i, N_857, N_860_i, N_860, - \time_wen_3_i[0]\, \time_wen_3[0]\, N_859_i, N_859, - \data_temp_5_i_0[32]\, N_912_i, N_769, N_864, - \data_temp_5_i_0[33]\, N_770, N_867, - \data_temp_5_i_0[34]\, N_848, N_870, - \data_temp_5_i_0[35]\, N_849, N_873, - \data_temp_5_i_0[36]\, N_850, N_1650, - \data_temp_5_i_0[37]\, N_851, N_1653, - \data_temp_5_i_0[38]\, N_852, N_1656, - \data_temp_5_i_0[39]\, N_853, N_1659, - \data_temp_5_i_0[40]\, N_854, N_1662, - \data_temp_5_i_0[41]\, N_841, N_1665, - \data_temp_5_i_0[42]\, N_842, N_1668, - \data_temp_5_i_0[43]\, N_843, N_897, - \data_valid_and_ready[3]_net_1\, \state_ns_i_i_a2_1[0]\, - \state[2]_net_1\, \state[1]_net_1\, \state[3]_net_1\, - N_239, N_898, N_237, N_1669, N_235, N_1666, N_233, N_1663, - N_231, N_1660, N_229, N_1657, N_227, N_1654, N_225, - N_1651, N_223, N_874, N_221, N_871, N_219, N_868, N_215, - N_865, N_251, N_910, N_909, N_1581, N_249, N_908, N_907, - N_247, N_906, N_905, N_1582, N_245, N_904, N_903, N_1583, - N_243, N_902, N_901, N_241, N_900, N_899, N_863, N_861, - N_1306, \state[0]_net_1\, \data_valid_and_ready[0]_net_1\, - \data_valid_and_ready[2]_net_1\, N_917, N_858, - \data_temp[64]_net_1\, N_1685, \data_temp[65]_net_1\, - N_1686, \data_temp[66]_net_1\, N_1687, - \data_temp[67]_net_1\, N_1688, \data_temp[68]_net_1\, - N_1689, \data_temp[69]_net_1\, N_762, - \data_temp[70]_net_1\, N_763, \data_temp[71]_net_1\, - N_764, \data_temp[72]_net_1\, N_765, - \data_temp[73]_net_1\, N_766, \data_temp[74]_net_1\, - N_767, \data_temp[75]_net_1\, N_768, N_794, N_1731, N_795, - N_1718, N_1681, N_1693, N_1682, N_1694, N_793, N_1730, - N_1680, N_1692, N_916, state_0_sqmuxa_i, N_1580, - \data_temp[123]_net_1\, \data_temp[125]_net_1\, - \data_temp[124]_net_1\, N_1675, N_1676, N_1677, N_1678, - N_1679, N_1683, N_1684, N_1690, N_1691, N_1695, N_1696, - N_1697, N_1698, N_1699, N_1700, N_1701, N_1702, N_1703, - N_1704, N_1705, N_1706, N_1707, N_1708, N_1709, N_1710, - N_1711, N_1712, N_1713, N_1714, N_1715, N_1716, N_1717, - N_1719, N_1720, N_1721, N_1722, N_1723, N_1724, N_1725, - N_1726, N_1727, N_1728, N_1729, N_1732, N_1733, N_1734, - N_1735, N_1736, N_1737, N_1738, N_1739, N_1740, N_729, - N_730, N_731, N_732, N_733, N_734, N_735, N_736, N_737, - N_738, N_739, N_740, N_741, N_742, N_743, N_744, N_745, - N_746, N_747, N_748, N_749, N_750, N_751, N_752, N_753, - N_754, N_755, N_756, N_757, N_758, N_759, N_760, N_761, - N_771, N_772, N_773, N_774, N_775, N_776, N_777, N_778, - N_779, N_780, N_781, N_782, N_783, N_784, N_785, N_786, - N_787, N_788, N_789, N_790, N_791, N_792, N_796, N_797, - N_798, N_799, N_800, N_801, N_802, N_803, N_804, N_805, - N_806, N_807, N_808, N_809, N_810, N_811, N_812, N_813, - N_814, N_815, N_816, N_817, N_818, N_819, N_820, N_821, - N_822, N_823, N_824, N_825, N_826, N_827, N_828, N_829, - N_830, N_831, N_832, N_833, N_834, N_835, N_836, N_837, - N_838, N_839, N_840, N_844, N_845, N_846, N_847, - \data_wen_3[0]\, \time_en_temp[0]_net_1\, \data_wen_3[1]\, - \time_en_temp[1]_net_1\, \data_wen_3[2]\, - \time_en_temp[2]_net_1\, \data_wen_3[3]\, - \time_en_temp[3]_net_1\, \data_selected[127]\, - \data_selected[159]\, N_696, \data_temp[127]_net_1\, - N_728, \data_temp_5[95]\, \data_temp_5[127]\, - \data_temp_5[14]\, \data_temp[46]_net_1\, - \data_temp_5[13]\, \data_temp[45]_net_1\, - \data_temp_5[12]\, \data_temp[44]_net_1\, - \data_temp_5[11]\, \data_temp[43]_net_1\, - \data_temp_5[10]\, \data_temp[42]_net_1\, - \data_temp_5[9]\, \data_temp[41]_net_1\, \data_temp_5[8]\, - \data_temp[40]_net_1\, \data_temp_5[7]\, - \data_temp[39]_net_1\, \data_temp_5[6]\, - \data_temp[38]_net_1\, \data_temp_5[5]\, - \data_temp[37]_net_1\, \data_temp_5[4]\, - \data_temp[36]_net_1\, \data_temp_5[3]\, - \data_temp[35]_net_1\, \data_temp_5[2]\, - \data_temp[34]_net_1\, \data_temp_5[1]\, - \data_temp[33]_net_1\, \data_temp_5[0]\, - \data_temp[32]_net_1\, \data_5[31]\, - \data_temp[31]_net_1\, \data_5[30]\, - \data_temp[30]_net_1\, \data_5[29]\, - \data_temp[29]_net_1\, \data_5[28]\, - \data_temp[28]_net_1\, \data_5[27]\, - \data_temp[27]_net_1\, \data_5[26]\, - \data_temp[26]_net_1\, \data_5[25]\, - \data_temp[25]_net_1\, \data_5[24]\, - \data_temp[24]_net_1\, \data_5[23]\, - \data_temp[23]_net_1\, \data_5[22]\, - \data_temp[22]_net_1\, \data_5[21]\, - \data_temp[21]_net_1\, \data_5[20]\, - \data_temp[20]_net_1\, \data_5[19]\, - \data_temp[19]_net_1\, \data_5[18]\, - \data_temp[18]_net_1\, \data_5[17]\, - \data_temp[17]_net_1\, \data_5[16]\, - \data_temp[16]_net_1\, \data_5[15]\, - \data_temp[15]_net_1\, \data_5[14]\, - \data_temp[14]_net_1\, \data_5[13]\, - \data_temp[13]_net_1\, \data_5[12]\, - \data_temp[12]_net_1\, \data_5[11]\, - \data_temp[11]_net_1\, \data_5[10]\, - \data_temp[10]_net_1\, \data_5[9]\, \data_temp[9]_net_1\, - \data_5[8]\, \data_temp[8]_net_1\, \data_5[7]\, - \data_temp[7]_net_1\, \data_5[6]\, \data_temp[6]_net_1\, - \data_selected[76]\, \data_selected[77]\, - \data_selected[78]\, \data_selected[79]\, - \data_selected[126]\, \data_selected[158]\, N_645, - \data_temp[76]_net_1\, N_646, \data_temp[77]_net_1\, - N_647, \data_temp[78]_net_1\, N_648, - \data_temp[79]_net_1\, N_695, \data_temp[126]_net_1\, - N_727, \data_temp_5[44]\, \data_temp_5[45]\, - \data_temp_5[46]\, \data_temp_5[47]\, \data_temp_5[94]\, - \data_temp_5[126]\, \data_temp_5[31]\, - \data_temp[63]_net_1\, \data_temp_5[30]\, - \data_temp[62]_net_1\, \data_temp_5[29]\, - \data_temp[61]_net_1\, \data_temp_5[28]\, - \data_temp[60]_net_1\, \data_temp_5[27]\, - \data_temp[59]_net_1\, \data_temp_5[26]\, - \data_temp[58]_net_1\, \data_temp_5[25]\, - \data_temp[57]_net_1\, \data_temp_5[24]\, - \data_temp[56]_net_1\, \data_temp_5[23]\, - \data_temp[55]_net_1\, \data_temp_5[22]\, - \data_temp[54]_net_1\, \data_temp_5[21]\, - \data_temp[53]_net_1\, \data_temp_5[20]\, - \data_temp[52]_net_1\, \data_temp_5[19]\, - \data_temp[51]_net_1\, \data_temp_5[18]\, - \data_temp[50]_net_1\, \data_temp_5[17]\, - \data_temp[49]_net_1\, \data_temp_5[16]\, - \data_temp[48]_net_1\, \data_temp_5[15]\, - \data_temp[47]_net_1\, N_928, \data_selected[80]\, - \data_selected[81]\, \data_selected[82]\, - \data_selected[83]\, \data_selected[84]\, - \data_selected[85]\, \data_selected[86]\, - \data_selected[87]\, \data_selected[88]\, - \data_selected[89]\, \data_selected[90]\, - \data_selected[91]\, \data_selected[92]\, - \data_selected[93]\, \data_selected[94]\, - \data_selected[95]\, \data_selected[112]\, - \data_selected[144]\, N_649, \data_temp[80]_net_1\, N_650, - \data_temp[81]_net_1\, N_651, \data_temp[82]_net_1\, - N_652, \data_temp[83]_net_1\, N_653, - \data_temp[84]_net_1\, N_654, \data_temp[85]_net_1\, - N_655, \data_temp[86]_net_1\, N_656, - \data_temp[87]_net_1\, N_657, \data_temp[88]_net_1\, - N_658, \data_temp[89]_net_1\, N_659, - \data_temp[90]_net_1\, N_660, \data_temp[91]_net_1\, - N_661, \data_temp[92]_net_1\, N_662, - \data_temp[93]_net_1\, N_663, \data_temp[94]_net_1\, - N_664, \data_temp[95]_net_1\, N_681, - \data_temp[112]_net_1\, N_713, \data_temp_5[48]\, - \data_temp_5[49]\, \data_temp_5[50]\, \data_temp_5[51]\, - \data_temp_5[52]\, \data_temp_5[53]\, \data_temp_5[54]\, - \data_temp_5[55]\, \data_temp_5[56]\, \data_temp_5[57]\, - \data_temp_5[58]\, \data_temp_5[59]\, \data_temp_5[60]\, - \data_temp_5[61]\, \data_temp_5[62]\, \data_temp_5[63]\, - \data_temp_5[80]\, \data_temp_5[112]\, \data_5[5]\, - \data_temp[5]_net_1\, \data_5[4]\, \data_temp[4]_net_1\, - \data_5[3]\, \data_temp[3]_net_1\, \data_5[2]\, - \data_temp[2]_net_1\, \data_5[1]\, \data_temp[1]_net_1\, - \data_5[0]\, \data_temp[0]_net_1\, \data_selected[108]\, - \data_selected[110]\, \data_selected[140]\, - \data_selected[142]\, N_677, \data_temp[108]_net_1\, - N_679, \data_temp[110]_net_1\, N_709, N_711, - \data_temp_5[76]\, \data_temp_5[78]\, \data_temp_5[108]\, - \data_temp_5[110]\, \data_selected[107]\, - \data_selected[111]\, \data_selected[139]\, - \data_selected[143]\, N_676, \data_temp[107]_net_1\, - N_680, \data_temp[111]_net_1\, N_708, N_712, - \data_temp_5[75]\, \data_temp_5[79]\, \data_temp_5[107]\, - \data_temp_5[111]\, \data_selected[106]\, - \data_selected[113]\, \data_selected[138]\, - \data_selected[145]\, N_675, \data_temp[106]_net_1\, - N_682, \data_temp[113]_net_1\, N_707, N_714, - \data_temp_5[74]\, \data_temp_5[81]\, \data_temp_5[106]\, - \data_temp_5[113]\, \data_selected[105]\, - \data_selected[114]\, \data_selected[137]\, - \data_selected[146]\, N_674, \data_temp[105]_net_1\, - N_683, \data_temp[114]_net_1\, N_706, N_715, - \data_temp_5[73]\, \data_temp_5[82]\, \data_temp_5[105]\, - \data_temp_5[114]\, \data_selected[104]\, - \data_selected[115]\, \data_selected[136]\, - \data_selected[147]\, N_673, \data_temp[104]_net_1\, - N_684, \data_temp[115]_net_1\, N_705, N_716, - \data_temp_5[72]\, \data_temp_5[83]\, \data_temp_5[104]\, - \data_temp_5[115]\, \data_selected[103]\, - \data_selected[116]\, \data_selected[135]\, - \data_selected[148]\, N_672, \data_temp[103]_net_1\, - N_685, \data_temp[116]_net_1\, N_704, N_717, - \data_temp_5[71]\, \data_temp_5[84]\, \data_temp_5[103]\, - \data_temp_5[116]\, \data_selected[102]\, - \data_selected[117]\, \data_selected[134]\, - \data_selected[149]\, N_671, \data_temp[102]_net_1\, - N_686, \data_temp[117]_net_1\, N_703, N_718, - \data_temp_5[70]\, \data_temp_5[85]\, \data_temp_5[102]\, - \data_temp_5[117]\, \data_selected[101]\, - \data_selected[118]\, \data_selected[133]\, - \data_selected[150]\, N_670, \data_temp[101]_net_1\, - N_687, \data_temp[118]_net_1\, N_702, N_719, - \data_temp_5[69]\, \data_temp_5[86]\, \data_temp_5[101]\, - \data_temp_5[118]\, \data_selected[100]\, - \data_selected[119]\, \data_selected[132]\, - \data_selected[151]\, N_669, \data_temp[100]_net_1\, - N_688, \data_temp[119]_net_1\, N_701, N_720, - \data_temp_5[68]\, \data_temp_5[87]\, \data_temp_5[100]\, - \data_temp_5[119]\, \data_selected[99]\, - \data_selected[120]\, \data_selected[131]\, - \data_selected[152]\, N_668, \data_temp[99]_net_1\, N_689, - \data_temp[120]_net_1\, N_700, N_721, \data_temp_5[67]\, - \data_temp_5[88]\, \data_temp_5[99]\, \data_temp_5[120]\, - \data_selected[98]\, \data_selected[121]\, - \data_selected[130]\, \data_selected[153]\, N_667, - \data_temp[98]_net_1\, N_690, \data_temp[121]_net_1\, - N_699, N_722, \data_temp_5[66]\, \data_temp_5[89]\, - \data_temp_5[98]\, \data_temp_5[121]\, - \data_selected[97]\, \data_selected[122]\, - \data_selected[129]\, \data_selected[154]\, N_666, - \data_temp[97]_net_1\, N_691, \data_temp[122]_net_1\, - N_698, N_723, \data_temp_5[65]\, \data_temp_5[90]\, - \data_temp_5[97]\, \data_temp_5[122]\, - \data_selected[96]\, \data_selected[109]\, - \data_selected[128]\, \data_selected[141]\, N_665, - \data_temp[96]_net_1\, N_678, \data_temp[109]_net_1\, - N_697, N_710, \data_temp_5[64]\, \data_temp_5[77]\, - \data_temp_5[96]\, \data_temp_5[109]\, N_929, \GND\, - \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \data_temp_RNO_2[65]\ : MX2C - port map(A => data_f2_out(97), B => data_f3_out(97), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_734); - - \data_temp[124]\ : DFN1C0 - port map(D => N_245, CLK => lclk_c, CLR => rstn, Q => - \data_temp[124]_net_1\); - - \data_temp_RNO_4[42]\ : MX2 - port map(A => data_f2_out(74), B => data_f3_out(74), S => - \data_valid_and_ready[2]_net_1\, Y => N_767); - - \data_temp[99]\ : DFN1C0 - port map(D => \data_temp_5[99]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[99]_net_1\); - - \data_temp_RNO_1[76]\ : MX2C - port map(A => N_731, B => N_806, S => N_1580_1, Y => - \data_selected[108]\); - - \data_temp_RNO_0[42]\ : AO1D - port map(A => N_912_i, B => N_842, C => N_1668, Y => - \data_temp_5_i_0[42]\); - - \data[3]\ : DFN1C0 - port map(D => \data_5[3]\, CLK => lclk_c, CLR => rstn, Q - => wdata(3)); - - \data_temp_RNO_2[32]\ : MX2 - port map(A => data_f0_out(64), B => data_f1_out(64), S => - \data_valid_and_ready_0[0]_net_1\, Y => N_769); - - \state_RNITQVJU1[4]\ : OR2 - port map(A => \data_valid_and_ready_0[2]_net_1\, B => N_911, - Y => N_859); - - \data_temp_RNO_2[64]\ : MX2C - port map(A => data_f2_out(96), B => data_f3_out(96), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_747); - - \time_en_temp[1]\ : DFN1E1C0 - port map(D => N_917, CLK => lclk_c, CLR => rstn, E => - state_0_sqmuxa_i, Q => \time_en_temp[1]_net_1\); - - \data_temp[127]\ : DFN1C0 - port map(D => \data_temp_5[127]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[127]_net_1\); - - \time_wen_RNO[1]\ : INV - port map(A => N_857, Y => N_857_i); - - \data_RNO[13]\ : NOR2A - port map(A => \data_temp[13]_net_1\, B => \state[4]_net_1\, - Y => \data_5[13]\); - - \data_temp_RNO_1[86]\ : MX2C - port map(A => N_1725, B => N_802, S => N_1580_2, Y => - \data_selected[118]\); - - \data_temp_RNO_1[73]\ : MX2C - port map(A => N_1740, B => N_817, S => N_1580_2, Y => - \data_selected[105]\); - - \data_temp_RNO_0[103]\ : MX2C - port map(A => \data_temp[103]_net_1\, B => - \data_selected[135]\, S => \state[4]_net_1\, Y => N_704); - - \data_temp_RNO_1[101]\ : MX2C - port map(A => N_1712, B => N_789, S => N_1580_2, Y => - \data_selected[133]\); - - \data_temp_RNO_2[124]\ : MX2 - port map(A => data_f2_out(156), B => data_f3_out(156), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1693); - - \data_temp_RNO_1[96]\ : MX2C - port map(A => N_1721, B => N_798, S => N_1580, Y => - \data_selected[128]\); - - \data_temp_RNO_1[83]\ : MX2C - port map(A => N_1736, B => N_799, S => N_1580_2, Y => - \data_selected[115]\); - - \data_temp[26]\ : DFN1C0 - port map(D => \data_temp_5[26]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[26]_net_1\); - - \data_RNO[17]\ : NOR2A - port map(A => \data_temp[17]_net_1\, B => \state[4]_net_1\, - Y => \data_5[17]\); - - \data_valid_ack[3]\ : DFN1E0C0 - port map(D => N_860_i, CLK => lclk_c, CLR => rstn, E => - N_929, Q => valid_ack(3)); - - \data_temp_RNO_1[39]\ : NOR2 - port map(A => N_911, B => N_764, Y => N_1660); - - \data_temp_RNO_1[93]\ : NOR2 - port map(A => N_912_i, B => N_795, Y => N_901); - - \data_temp[13]\ : DFN1C0 - port map(D => \data_temp_5[13]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[13]_net_1\); - - \data_temp[56]\ : DFN1C0 - port map(D => \data_temp_5[56]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[56]_net_1\); - - \data_temp_RNO_2[127]\ : MX2C - port map(A => data_f2_out(159), B => data_f3_out(159), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1696); - - \data_temp[125]\ : DFN1C0 - port map(D => N_247, CLK => lclk_c, CLR => rstn, Q => - \data_temp[125]_net_1\); - - \data_temp_RNO[65]\ : NOR2 - port map(A => N_863, B => N_666, Y => \data_temp_5[65]\); - - \data_temp_RNO[98]\ : NOR2 - port map(A => N_863, B => N_699, Y => \data_temp_5[98]\); - - \data_RNO[5]\ : NOR2A - port map(A => \data_temp[5]_net_1\, B => \state[4]_net_1\, - Y => \data_5[5]\); - - \data_temp_RNO_2[119]\ : MX2C - port map(A => data_f2_out(151), B => data_f3_out(151), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1702); - - \data_wen[3]\ : DFN1E0P0 - port map(D => \data_wen_3[3]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => data_wen(3)); - - \data_temp[70]\ : DFN1C0 - port map(D => \data_temp_5[70]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[70]_net_1\); - - \data_temp_RNO[39]\ : NOR3 - port map(A => \data_temp_5_i_0[39]\, B => N_1660, C => - N_863_0, Y => N_231); - - \data_temp_RNO[77]\ : NOR2 - port map(A => N_863, B => N_678, Y => \data_temp_5[77]\); - - \state_RNIU3KC[2]\ : NOR2 - port map(A => \state[4]_net_1\, B => \state[2]_net_1\, Y - => N_928); - - \data[13]\ : DFN1C0 - port map(D => \data_5[13]\, CLK => lclk_c, CLR => rstn, Q - => wdata(13)); - - \data_temp_RNO_2[57]\ : MX2C - port map(A => data_f2_out(89), B => data_f3_out(89), S => - \data_valid_and_ready[2]_net_1\, Y => N_754); - - \data_temp[64]\ : DFN1C0 - port map(D => \data_temp_5[64]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[64]_net_1\); - - \data_temp_RNO[93]\ : NOR3 - port map(A => N_902, B => N_901, C => N_1582, Y => N_243); - - \state_RNO_0[4]\ : OR3 - port map(A => \state[2]_net_1\, B => \state[1]_net_1\, C - => \state[3]_net_1\, Y => \state_ns_i_i_a2_1[0]\); - - \data_temp_RNO_1[50]\ : MX2C - port map(A => N_761, B => N_836, S => N_1580_0, Y => - \data_selected[82]\); - - \data_temp[6]\ : DFN1C0 - port map(D => \data_temp_5[6]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[6]_net_1\); - - \data[31]\ : DFN1C0 - port map(D => \data_5[31]\, CLK => lclk_c, CLR => rstn, Q - => wdata(31)); - - \data_temp[112]\ : DFN1C0 - port map(D => \data_temp_5[112]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[112]_net_1\); - - \data_temp_RNO[112]\ : NOR2 - port map(A => N_863_1, B => N_713, Y => \data_temp_5[112]\); - - \data_temp[100]\ : DFN1C0 - port map(D => \data_temp_5[100]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[100]_net_1\); - - \data_temp_RNO_2[70]\ : MX2C - port map(A => data_f2_out(102), B => data_f3_out(102), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_739); - - \data_temp_RNO_3[56]\ : MX2C - port map(A => data_f0_out(88), B => data_f1_out(88), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_828); - - \data_temp_RNO_0[37]\ : AO1D - port map(A => N_912_i, B => N_851, C => N_1653, Y => - \data_temp_5_i_0[37]\); - - \data_temp_RNO[36]\ : NOR3 - port map(A => \data_temp_5_i_0[36]\, B => N_1651, C => - N_863_0, Y => N_225); - - \data_temp_RNO_0[59]\ : MX2C - port map(A => \data_temp[91]_net_1\, B => - \data_selected[91]\, S => \state[4]_net_1\, Y => N_660); - - \data_temp_RNO_0[51]\ : MX2C - port map(A => \data_temp[83]_net_1\, B => - \data_selected[83]\, S => \state[4]_net_1\, Y => N_652); - - \data_temp_RNO_3[66]\ : MX2C - port map(A => data_f0_out(98), B => data_f1_out(98), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_824); - - \data_temp_RNO_3[86]\ : MX2C - port map(A => data_f0_out(118), B => data_f1_out(118), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_802); - - \data_temp_RNO_3[49]\ : MX2C - port map(A => data_f0_out(81), B => data_f1_out(81), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_835); - - \data_temp_RNO_3[41]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[73]_net_1\, - Y => N_1665); - - \data_temp_RNO_2[40]\ : MX2 - port map(A => data_f0_out(72), B => data_f1_out(72), S => - \data_valid_and_ready[0]_net_1\, Y => N_854); - - \data_temp_RNO_0[116]\ : MX2C - port map(A => \data_temp[116]_net_1\, B => - \data_selected[148]\, S => \state[4]_net_1\, Y => N_717); - - \data_temp_RNO_1[35]\ : NOR2 - port map(A => N_1688, B => N_911, Y => N_874); - - \data_temp_RNO_3[53]\ : MX2C - port map(A => data_f0_out(85), B => data_f1_out(85), S => - \data_valid_and_ready[0]_net_1\, Y => N_839); - - \data_temp_RNO[49]\ : NOR2 - port map(A => N_863_1, B => N_650, Y => \data_temp_5[49]\); - - \data_temp_RNO_3[63]\ : MX2C - port map(A => data_f0_out(95), B => data_f1_out(95), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_821); - - \data_temp_RNO_3[83]\ : MX2C - port map(A => data_f0_out(115), B => data_f1_out(115), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_799); - - \data_temp_RNO_2[120]\ : MX2C - port map(A => data_f2_out(152), B => data_f3_out(152), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1703); - - \state_RNI02A6[4]\ : CLKINT - port map(A => \state_0[4]\, Y => \state[4]_net_1\); - - \data_temp_RNO_1[52]\ : MX2C - port map(A => N_749, B => N_838, S => N_1580_0, Y => - \data_selected[84]\); - - \data_temp_RNO_1[34]\ : NOR2 - port map(A => N_1687, B => N_911, Y => N_871); - - \state[2]\ : DFN1C0 - port map(D => \state[3]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[2]_net_1\); - - \data_temp[36]\ : DFN1C0 - port map(D => N_225, CLK => lclk_c, CLR => rstn, Q => - \data_temp[36]_net_1\); - - un5_data_selected_i_i_a2 : OR2B - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_917); - - \data_wen_RNO[0]\ : OR2 - port map(A => \time_en_temp[0]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[0]\); - - \data_temp_RNO_2[72]\ : MX2C - port map(A => data_f2_out(104), B => data_f3_out(104), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1739); - - \data_temp_RNO_1[110]\ : MX2C - port map(A => N_1707, B => N_784, S => N_1580_1, Y => - \data_selected[142]\); - - \data_temp[82]\ : DFN1C0 - port map(D => \data_temp_5[82]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[82]_net_1\); - - \data_temp_RNO[46]\ : NOR2 - port map(A => N_863_0, B => N_647, Y => \data_temp_5[46]\); - - \data_temp[0]\ : DFN1C0 - port map(D => \data_temp_5[0]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[0]_net_1\); - - data_selected_sn_m2_0_o2_2 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_2); - - \data_temp_RNO_2[42]\ : MX2 - port map(A => data_f0_out(74), B => data_f1_out(74), S => - \data_valid_and_ready[0]_net_1\, Y => N_842); - - \data_temp_RNO_1[49]\ : MX2C - port map(A => N_760, B => N_835, S => N_1580_0, Y => - \data_selected[81]\); - - \data_temp_RNO_1[41]\ : NOR2 - port map(A => N_911, B => N_766, Y => N_1666); - - \data_RNO[2]\ : NOR2A - port map(A => \data_temp[2]_net_1\, B => \state[4]_net_1\, - Y => \data_5[2]\); - - \data_temp_RNO_2[86]\ : MX2C - port map(A => data_f2_out(118), B => data_f3_out(118), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1725); - - \data_temp[10]\ : DFN1C0 - port map(D => \data_temp_5[10]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[10]_net_1\); - - \data_temp[111]\ : DFN1C0 - port map(D => \data_temp_5[111]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[111]_net_1\); - - \data_temp_RNO_3[36]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[68]_net_1\, - Y => N_1650); - - \data_temp_RNO_0[55]\ : MX2C - port map(A => \data_temp[87]_net_1\, B => - \data_selected[87]\, S => \state[4]_net_1\, Y => N_656); - - \time_wen[1]\ : DFN1E0P0 - port map(D => N_857_i, CLK => lclk_c, PRE => rstn, E => - N_928, Q => time_wen(1)); - - \data_temp_RNO_1[127]\ : MX2C - port map(A => N_1696, B => N_1684, S => N_1580_0, Y => - \data_selected[159]\); - - \data_temp_RNO[10]\ : NOR2A - port map(A => \data_temp[42]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[10]\); - - \data_temp_RNO_3[45]\ : MX2C - port map(A => data_f0_out(77), B => data_f1_out(77), S => - \data_valid_and_ready[0]_net_1\, Y => N_845); - - \data_temp_RNO_3[108]\ : MX2C - port map(A => data_f0_out(140), B => data_f1_out(140), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_782); - - \data_temp[24]\ : DFN1C0 - port map(D => \data_temp_5[24]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[24]_net_1\); - - \data_temp_RNO_0[115]\ : MX2C - port map(A => \data_temp[115]_net_1\, B => - \data_selected[147]\, S => \state[4]_net_1\, Y => N_716); - - \data_temp_RNO_2[83]\ : MX2C - port map(A => data_f2_out(115), B => data_f3_out(115), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1736); - - \data_temp_RNO_0[54]\ : MX2C - port map(A => \data_temp[86]_net_1\, B => - \data_selected[86]\, S => \state[4]_net_1\, Y => N_655); - - \data_temp_RNO[4]\ : NOR2A - port map(A => \data_temp[36]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[4]\); - - \data_temp[119]\ : DFN1C0 - port map(D => \data_temp_5[119]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[119]_net_1\); - - \data_temp_RNO_3[33]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[65]_net_1\, - Y => N_867); - - \data_temp_RNO_2[66]\ : MX2C - port map(A => data_f2_out(98), B => data_f3_out(98), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_735); - - \data_temp[54]\ : DFN1C0 - port map(D => \data_temp_5[54]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[54]_net_1\); - - \data_temp_RNO_3[44]\ : MX2C - port map(A => data_f0_out(76), B => data_f1_out(76), S => - \data_valid_and_ready[0]_net_1\, Y => N_844); - - \data_temp_RNO[75]\ : NOR2 - port map(A => N_863_1, B => N_676, Y => \data_temp_5[75]\); - - \data_temp[81]\ : DFN1C0 - port map(D => \data_temp_5[81]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[81]_net_1\); - - \data_RNO[11]\ : NOR2A - port map(A => \data_temp[11]_net_1\, B => \state[4]_net_1\, - Y => \data_5[11]\); - - \data_temp_RNO_3[99]\ : MX2C - port map(A => data_f0_out(131), B => data_f1_out(131), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_787); - - \data_temp_RNO_3[91]\ : MX2 - port map(A => data_f0_out(123), B => data_f1_out(123), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_793); - - \state_RNIBMG5L1_1[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_917, Y => N_857); - - \data_temp_RNO[37]\ : NOR3 - port map(A => \data_temp_5_i_0[37]\, B => N_1654, C => - N_863_0, Y => N_227); - - \data_temp_RNO_2[63]\ : MX2C - port map(A => data_f2_out(95), B => data_f3_out(95), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_746); - - \data_RNO[12]\ : NOR2A - port map(A => \data_temp[12]_net_1\, B => \state[4]_net_1\, - Y => \data_5[12]\); - - \data_valid_ack_RNO[0]\ : INV - port map(A => \time_wen_3[0]\, Y => \time_wen_3_i[0]\); - - \data_temp_RNO_3[127]\ : MX2C - port map(A => data_f0_out(159), B => data_f1_out(159), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1684); - - \data_temp_RNO[2]\ : NOR2A - port map(A => \data_temp[34]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[2]\); - - \data_temp_RNO_1[68]\ : MX2C - port map(A => N_737, B => N_826, S => N_1580_2, Y => - \data_selected[100]\); - - \data_temp_RNO_0[120]\ : MX2C - port map(A => \data_temp[120]_net_1\, B => - \data_selected[152]\, S => \state[4]_net_1\, Y => N_721); - - \data_temp_RNO_1[45]\ : MX2C - port map(A => N_756, B => N_845, S => N_1580_0, Y => - \data_selected[77]\); - - \data_temp_RNO_0[98]\ : MX2C - port map(A => \data_temp[98]_net_1\, B => - \data_selected[130]\, S => \state[4]_net_1\, Y => N_699); - - \data_temp_RNO[91]\ : NOR3 - port map(A => N_908, B => N_907, C => N_1581, Y => N_249); - - \data_temp_RNO[115]\ : NOR2 - port map(A => N_863_2, B => N_716, Y => \data_temp_5[115]\); - - \data_temp[76]\ : DFN1C0 - port map(D => \data_temp_5[76]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[76]_net_1\); - - \data_temp_RNO_1[44]\ : MX2C - port map(A => N_755, B => N_844, S => N_1580_0, Y => - \data_selected[76]\); - - \data_RNO[28]\ : NOR2A - port map(A => \data_temp[28]_net_1\, B => \state[4]_net_1\, - Y => \data_5[28]\); - - \data_temp_RNO[68]\ : NOR2 - port map(A => N_863, B => N_669, Y => \data_temp_5[68]\); - - \data_temp_RNO_0[117]\ : MX2C - port map(A => \data_temp[117]_net_1\, B => - \data_selected[149]\, S => \state[4]_net_1\, Y => N_718); - - \data_temp_RNO[92]\ : NOR3 - port map(A => N_900, B => N_899, C => N_1583, Y => N_241); - - \time_en_temp_RNO[2]\ : OR2 - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - N_1580_0, Y => N_858); - - \data_temp_RNO_3[122]\ : MX2C - port map(A => data_f0_out(154), B => data_f1_out(154), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1679); - - \data_temp_RNO_2[50]\ : MX2C - port map(A => data_f2_out(82), B => data_f3_out(82), S => - \data_valid_and_ready[2]_net_1\, Y => N_761); - - \data_temp[88]\ : DFN1C0 - port map(D => \data_temp_5[88]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[88]_net_1\); - - \data[28]\ : DFN1C0 - port map(D => \data_5[28]\, CLK => lclk_c, CLR => rstn, Q - => wdata(28)); - - \data_temp_RNO[20]\ : NOR2A - port map(A => \data_temp[52]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[20]\); - - \data_temp_RNO[63]\ : NOR2 - port map(A => N_863_1, B => N_664, Y => \data_temp_5[63]\); - - \data_temp_RNO[47]\ : NOR2 - port map(A => N_863_0, B => N_648, Y => \data_temp_5[47]\); - - \data_temp_RNO[117]\ : NOR2 - port map(A => N_863_2, B => N_718, Y => \data_temp_5[117]\); - - \data_wen_RNO[1]\ : OR2 - port map(A => \time_en_temp[1]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[1]\); - - \data_temp[93]\ : DFN1C0 - port map(D => N_243, CLK => lclk_c, CLR => rstn, Q => - \data_temp[93]_net_1\); - - \data_temp[49]\ : DFN1C0 - port map(D => \data_temp_5[49]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[49]_net_1\); - - \data_temp_RNO_3[95]\ : MX2C - port map(A => data_f0_out(127), B => data_f1_out(127), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_797); - - \data_temp_RNO_2[109]\ : MX2C - port map(A => data_f2_out(141), B => data_f3_out(141), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1706); - - \data[5]\ : DFN1C0 - port map(D => \data_5[5]\, CLK => lclk_c, CLR => rstn, Q - => wdata(5)); - - \data_temp_RNO_4[41]\ : MX2 - port map(A => data_f2_out(73), B => data_f3_out(73), S => - \data_valid_and_ready[2]_net_1\, Y => N_766); - - \data_temp[34]\ : DFN1C0 - port map(D => N_221, CLK => lclk_c, CLR => rstn, Q => - \data_temp[34]_net_1\); - - \data[16]\ : DFN1C0 - port map(D => \data_5[16]\, CLK => lclk_c, CLR => rstn, Q - => wdata(16)); - - \data_temp_RNO_3[78]\ : MX2C - port map(A => data_f0_out(110), B => data_f1_out(110), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_808); - - \data_temp_RNO_0[49]\ : MX2C - port map(A => \data_temp[81]_net_1\, B => - \data_selected[81]\, S => \state[4]_net_1\, Y => N_650); - - \data_temp_RNO_0[41]\ : AO1D - port map(A => N_912_i, B => N_841, C => N_1665, Y => - \data_temp_5_i_0[41]\); - - \data_temp[62]\ : DFN1C0 - port map(D => \data_temp_5[62]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[62]_net_1\); - - \data_temp_RNO[94]\ : NOR2 - port map(A => N_863_0, B => N_695, Y => \data_temp_5[94]\); - - \data[7]\ : DFN1C0 - port map(D => \data_5[7]\, CLK => lclk_c, CLR => rstn, Q - => wdata(7)); - - \data_temp_RNO_3[114]\ : MX2C - port map(A => data_f0_out(146), B => data_f1_out(146), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_774); - - \data_temp_RNO_2[39]\ : MX2 - port map(A => data_f0_out(71), B => data_f1_out(71), S => - \data_valid_and_ready[0]_net_1\, Y => N_853); - - \data_temp_RNO[122]\ : NOR2 - port map(A => N_863, B => N_723, Y => \data_temp_5[122]\); - - \data_RNO[31]\ : NOR2A - port map(A => \data_temp[31]_net_1\, B => \state[4]_net_1\, - Y => \data_5[31]\); - - \data_temp_RNO_3[94]\ : MX2C - port map(A => data_f0_out(126), B => data_f1_out(126), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_796); - - \data_temp[87]\ : DFN1C0 - port map(D => \data_temp_5[87]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[87]_net_1\); - - \data_temp_RNO_3[126]\ : MX2C - port map(A => data_f0_out(158), B => data_f1_out(158), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1683); - - \data_temp_RNO_0[78]\ : MX2C - port map(A => \data_temp[110]_net_1\, B => - \data_selected[110]\, S => \state[4]_net_1\, Y => N_679); - - \data_temp_RNO_2[52]\ : MX2C - port map(A => data_f2_out(84), B => data_f3_out(84), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_749); - - \data_temp[108]\ : DFN1C0 - port map(D => \data_temp_5[108]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[108]_net_1\); - - \data_temp_RNO_1[112]\ : MX2C - port map(A => N_1709, B => N_772, S => N_1580_1, Y => - \data_selected[144]\); - - \data_temp_RNO_0[106]\ : MX2C - port map(A => \data_temp[106]_net_1\, B => - \data_selected[138]\, S => \state[4]_net_1\, Y => N_707); - - \data_temp_RNO[59]\ : NOR2 - port map(A => N_863_1, B => N_660, Y => \data_temp_5[59]\); - - \data_temp_RNO_0[32]\ : AO1D - port map(A => N_912_i, B => N_769, C => N_864, Y => - \data_temp_5_i_0[32]\); - - \data_temp[61]\ : DFN1C0 - port map(D => \data_temp_5[61]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[61]_net_1\); - - \data_temp_RNO_4[38]\ : MX2 - port map(A => data_f2_out(70), B => data_f3_out(70), S => - \data_valid_and_ready[2]_net_1\, Y => N_763); - - \data_temp[16]\ : DFN1C0 - port map(D => \data_temp_5[16]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[16]_net_1\); - - \data[21]\ : DFN1C0 - port map(D => \data_5[21]\, CLK => lclk_c, CLR => rstn, Q - => wdata(21)); - - \data_temp_RNO_1[36]\ : NOR2 - port map(A => N_1689, B => N_911, Y => N_1651); - - \data_temp_RNO[89]\ : NOR2 - port map(A => N_863, B => N_690, Y => \data_temp_5[89]\); - - \data_temp_RNO[35]\ : NOR3 - port map(A => \data_temp_5_i_0[35]\, B => N_874, C => - N_863_0, Y => N_223); - - \data_temp_RNO[102]\ : NOR2 - port map(A => N_863_2, B => N_703, Y => \data_temp_5[102]\); - - \data_temp_RNO_1[123]\ : NOR2 - port map(A => N_1680, B => N_912_i, Y => N_909); - - \data_temp_RNO_3[110]\ : MX2C - port map(A => data_f0_out(142), B => data_f1_out(142), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_784); - - \data_temp_RNO_2[122]\ : MX2C - port map(A => data_f2_out(154), B => data_f3_out(154), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1691); - - \data_temp_RNO_0[45]\ : MX2C - port map(A => \data_temp[77]_net_1\, B => - \data_selected[77]\, S => \state[4]_net_1\, Y => N_646); - - \data_temp_RNO_2[125]\ : MX2 - port map(A => data_f2_out(157), B => data_f3_out(157), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1694); - - \data[0]\ : DFN1C0 - port map(D => \data_5[0]\, CLK => lclk_c, CLR => rstn, Q - => wdata(0)); - - \data_temp_RNO[56]\ : NOR2 - port map(A => N_863_1, B => N_657, Y => \data_temp_5[56]\); - - \data_temp_RNO_2[35]\ : MX2 - port map(A => data_f0_out(67), B => data_f1_out(67), S => - \data_valid_and_ready[0]_net_1\, Y => N_849); - - \data_valid_ack[0]\ : DFN1E0C0 - port map(D => \time_wen_3_i[0]\, CLK => lclk_c, CLR => rstn, - E => N_929, Q => valid_ack(0)); - - \data_temp_RNO_1[33]\ : NOR2 - port map(A => N_1686, B => N_911, Y => N_868); - - \data_temp_RNO[86]\ : NOR2 - port map(A => N_863_2, B => N_687, Y => \data_temp_5[86]\); - - \data_temp_RNO_1[119]\ : MX2C - port map(A => N_1702, B => N_1676, S => N_1580, Y => - \data_selected[151]\); - - \data_temp_RNO_1[100]\ : MX2C - port map(A => N_1711, B => N_788, S => N_1580, Y => - \data_selected[132]\); - - \data_temp_RNO_1[118]\ : MX2C - port map(A => N_1701, B => N_1675, S => N_1580_2, Y => - \data_selected[150]\); - - GND_i : GND - port map(Y => \GND\); - - \data_temp_RNO_0[44]\ : MX2C - port map(A => \data_temp[76]_net_1\, B => - \data_selected[76]\, S => \state[4]_net_1\, Y => N_645); - - \data_temp_RNO_2[34]\ : MX2 - port map(A => data_f0_out(66), B => data_f1_out(66), S => - \data_valid_and_ready[0]_net_1\, Y => N_848); - - \data_RNO[16]\ : NOR2A - port map(A => \data_temp[16]_net_1\, B => \state[4]_net_1\, - Y => \data_5[16]\); - - \data_temp[74]\ : DFN1C0 - port map(D => \data_temp_5[74]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[74]_net_1\); - - \data_temp[90]\ : DFN1C0 - port map(D => \data_temp_5[90]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[90]_net_1\); - - \data_temp[22]\ : DFN1C0 - port map(D => \data_temp_5[22]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[22]_net_1\); - - \data_temp_RNO_0[56]\ : MX2C - port map(A => \data_temp[88]_net_1\, B => - \data_selected[88]\, S => \state[4]_net_1\, Y => N_657); - - \data_temp_RNO_0[88]\ : MX2C - port map(A => \data_temp[120]_net_1\, B => - \data_selected[120]\, S => \state[4]_net_1\, Y => N_689); - - \data_temp_RNO[78]\ : NOR2 - port map(A => N_863_1, B => N_679, Y => \data_temp_5[78]\); - - \data_temp_RNO_1[67]\ : MX2C - port map(A => N_736, B => N_825, S => N_1580, Y => - \data_selected[99]\); - - \data_temp_RNO[45]\ : NOR2 - port map(A => N_863_0, B => N_646, Y => \data_temp_5[45]\); - - \state_RNIBMG5L1[4]\ : OR2B - port map(A => \state[4]_net_1\, B => N_1580_0, Y => N_912_i); - - \data_temp_RNO_3[46]\ : MX2C - port map(A => data_f0_out(78), B => data_f1_out(78), S => - \data_valid_and_ready[0]_net_1\, Y => N_846); - - \data_temp_RNO_0[112]\ : MX2C - port map(A => \data_temp[112]_net_1\, B => - \data_selected[144]\, S => \state[4]_net_1\, Y => N_713); - - \data_temp[68]\ : DFN1C0 - port map(D => \data_temp_5[68]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[68]_net_1\); - - \time_en_temp[2]\ : DFN1E1C0 - port map(D => N_858, CLK => lclk_c, CLR => rstn, E => - state_0_sqmuxa_i, Q => \time_en_temp[2]_net_1\); - - \data_temp_RNO_2[98]\ : MX2C - port map(A => data_f2_out(130), B => data_f3_out(130), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1723); - - \data_temp_RNO_0[105]\ : MX2C - port map(A => \data_temp[105]_net_1\, B => - \data_selected[137]\, S => \state[4]_net_1\, Y => N_706); - - \data_temp[52]\ : DFN1C0 - port map(D => \data_temp_5[52]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[52]_net_1\); - - \data_temp_RNO_0[97]\ : MX2C - port map(A => \data_temp[97]_net_1\, B => - \data_selected[129]\, S => \state[4]_net_1\, Y => N_698); - - \data_temp_RNO_0[119]\ : MX2C - port map(A => \data_temp[119]_net_1\, B => - \data_selected[151]\, S => \state[4]_net_1\, Y => N_720); - - \data[2]\ : DFN1C0 - port map(D => \data_5[2]\, CLK => lclk_c, CLR => rstn, Q - => wdata(2)); - - \data_temp_RNO[73]\ : NOR2 - port map(A => N_863_2, B => N_674, Y => \data_temp_5[73]\); - - \data_temp[85]\ : DFN1C0 - port map(D => \data_temp_5[85]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[85]_net_1\); - - \data_temp_5_i_a2_0_0[32]\ : OR2A - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - \data_valid_and_ready[3]_net_1\, Y => - \data_temp_5_i_a2_0_0[32]_net_1\); - - \data_valid_and_ready_1[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready_1[2]_net_1\); - - \data_temp_RNO_0[53]\ : MX2C - port map(A => \data_temp[85]_net_1\, B => - \data_selected[85]\, S => \state[4]_net_1\, Y => N_654); - - \data_temp_RNO_3[43]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[75]_net_1\, - Y => N_897); - - \data[22]\ : DFN1C0 - port map(D => \data_5[22]\, CLK => lclk_c, CLR => rstn, Q - => wdata(22)); - - \data_temp_RNO_2[126]\ : MX2C - port map(A => data_f2_out(158), B => data_f3_out(158), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1695); - - \data_temp_RNO[61]\ : NOR2 - port map(A => N_863_1, B => N_662, Y => \data_temp_5[61]\); - - \data_temp_RNO_0[68]\ : MX2C - port map(A => \data_temp[100]_net_1\, B => - \data_selected[100]\, S => \state[4]_net_1\, Y => N_669); - - \data_temp[67]\ : DFN1C0 - port map(D => \data_temp_5[67]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[67]_net_1\); - - \data_temp[21]\ : DFN1C0 - port map(D => \data_temp_5[21]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[21]_net_1\); - - \data_wen[2]\ : DFN1E0P0 - port map(D => \data_wen_3[2]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => data_wen(2)); - - \data_temp[9]\ : DFN1C0 - port map(D => \data_temp_5[9]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[9]_net_1\); - - \data_temp_RNO[62]\ : NOR2 - port map(A => N_863_1, B => N_663, Y => \data_temp_5[62]\); - - \data_temp_RNO[125]\ : NOR3 - port map(A => N_906, B => N_905, C => N_1582, Y => N_247); - - \data_temp_RNO_1[59]\ : MX2C - port map(A => N_742, B => N_831, S => N_1580_1, Y => - \data_selected[91]\); - - \data_temp_RNO_1[51]\ : MX2C - port map(A => N_748, B => N_837, S => N_1580_0, Y => - \data_selected[83]\); - - \data_temp_RNO_1[46]\ : MX2C - port map(A => N_757, B => N_846, S => N_1580_0, Y => - \data_selected[78]\); - - \data_temp[51]\ : DFN1C0 - port map(D => \data_temp_5[51]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[51]_net_1\); - - \data_temp_RNO_2[79]\ : MX2C - port map(A => data_f2_out(111), B => data_f3_out(111), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1732); - - \data_temp_RNO_2[71]\ : MX2C - port map(A => data_f2_out(103), B => data_f3_out(103), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_740); - - \data_temp_RNO_3[77]\ : MX2C - port map(A => data_f0_out(109), B => data_f1_out(109), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_807); - - \data_temp[120]\ : DFN1C0 - port map(D => \data_temp_5[120]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[120]_net_1\); - - \data_temp[106]\ : DFN1C0 - port map(D => \data_temp_5[106]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[106]_net_1\); - - \time_wen[3]\ : DFN1E0P0 - port map(D => N_860, CLK => lclk_c, PRE => rstn, E => N_928, - Q => time_wen(3)); - - \data_temp_RNO_2[49]\ : MX2C - port map(A => data_f2_out(81), B => data_f3_out(81), S => - \data_valid_and_ready[2]_net_1\, Y => N_760); - - \data_temp_RNO_2[41]\ : MX2 - port map(A => data_f0_out(73), B => data_f1_out(73), S => - \data_valid_and_ready[0]_net_1\, Y => N_841); - - \data_temp_RNO[127]\ : NOR2 - port map(A => N_863_0, B => N_728, Y => \data_temp_5[127]\); - - \data_temp_RNO_0[107]\ : MX2C - port map(A => \data_temp[107]_net_1\, B => - \data_selected[139]\, S => \state[4]_net_1\, Y => N_708); - - \data_temp_RNO_0[77]\ : MX2C - port map(A => \data_temp[109]_net_1\, B => - \data_selected[109]\, S => \state[4]_net_1\, Y => N_678); - - \data_temp_RNO_1[43]\ : NOR2 - port map(A => N_911, B => N_768, Y => N_898); - - \data_temp_RNO[57]\ : NOR2 - port map(A => N_863_1, B => N_658, Y => \data_temp_5[57]\); - - \data_temp_RNO[64]\ : NOR2 - port map(A => N_863, B => N_665, Y => \data_temp_5[64]\); - - \data_temp[14]\ : DFN1C0 - port map(D => \data_temp_5[14]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[14]_net_1\); - - \data_temp_RNO[87]\ : NOR2 - port map(A => N_863, B => N_688, Y => \data_temp_5[87]\); - - \data_temp[114]\ : DFN1C0 - port map(D => \data_temp_5[114]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[114]_net_1\); - - \data_temp_RNO_0[124]\ : NOR2 - port map(A => N_1693, B => N_911, Y => N_904); - - \data_temp_RNO[110]\ : NOR2 - port map(A => N_863_1, B => N_711, Y => \data_temp_5[110]\); - - \data_temp_RNO_3[111]\ : MX2C - port map(A => data_f0_out(143), B => data_f1_out(143), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_771); - - \data_temp_RNO_0[121]\ : MX2C - port map(A => \data_temp[121]_net_1\, B => - \data_selected[153]\, S => \state[4]_net_1\, Y => N_722); - - \data_temp_RNO[105]\ : NOR2 - port map(A => N_863_2, B => N_706, Y => \data_temp_5[105]\); - - \data[29]\ : DFN1C0 - port map(D => \data_5[29]\, CLK => lclk_c, CLR => rstn, Q - => wdata(29)); - - \data_temp_RNO_1[78]\ : MX2C - port map(A => N_733, B => N_808, S => N_1580_1, Y => - \data_selected[110]\); - - \data_temp[32]\ : DFN1C0 - port map(D => N_215, CLK => lclk_c, CLR => rstn, Q => - \data_temp[32]_net_1\); - - \data_temp_RNO_0[118]\ : MX2C - port map(A => \data_temp[118]_net_1\, B => - \data_selected[150]\, S => \state[4]_net_1\, Y => N_719); - - \data_temp[28]\ : DFN1C0 - port map(D => \data_temp_5[28]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[28]_net_1\); - - \data_temp_RNO_3[96]\ : MX2C - port map(A => data_f0_out(128), B => data_f1_out(128), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_798); - - \data_temp[117]\ : DFN1C0 - port map(D => \data_temp_5[117]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[117]_net_1\); - - \data_RNO[19]\ : NOR2A - port map(A => \data_temp[19]_net_1\, B => \state[4]_net_1\, - Y => \data_5[19]\); - - \data_temp_RNO_4[37]\ : MX2 - port map(A => data_f2_out(69), B => data_f3_out(69), S => - \data_valid_and_ready[2]_net_1\, Y => N_762); - - data_selected_sn_m2_0_o2 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580); - - \data_temp[58]\ : DFN1C0 - port map(D => \data_temp_5[58]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[58]_net_1\); - - \data_temp_RNO_1[55]\ : MX2C - port map(A => N_752, B => N_827, S => N_1580_0, Y => - \data_selected[87]\); - - \data_temp_RNO_3[104]\ : MX2C - port map(A => data_f0_out(136), B => data_f1_out(136), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_778); - - \data_temp_RNO_1[88]\ : MX2C - port map(A => N_1727, B => N_804, S => N_1580, Y => - \data_selected[120]\); - - \data_temp_RNO[107]\ : NOR2 - port map(A => N_863_1, B => N_708, Y => \data_temp_5[107]\); - - \data[25]\ : DFN1C0 - port map(D => \data_5[25]\, CLK => lclk_c, CLR => rstn, Q - => wdata(25)); - - \data_temp_RNO_3[93]\ : MX2 - port map(A => data_f0_out(125), B => data_f1_out(125), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_795); - - \data_temp_RNO_2[75]\ : MX2C - port map(A => data_f2_out(107), B => data_f3_out(107), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_730); - - \data_valid_and_ready_0[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready_0[2]_net_1\); - - \data_temp_RNO_1[115]\ : MX2C - port map(A => N_1698, B => N_775, S => N_1580_2, Y => - \data_selected[147]\); - - \data_temp[27]\ : DFN1C0 - port map(D => \data_temp_5[27]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[27]_net_1\); - - \data_temp_RNO_1[54]\ : MX2C - port map(A => N_751, B => N_840, S => N_1580_0, Y => - \data_selected[86]\); - - \data_temp_RNO[38]\ : NOR3 - port map(A => \data_temp_5_i_0[38]\, B => N_1657, C => - N_863_0, Y => N_229); - - \data_temp_RNO_2[45]\ : MX2C - port map(A => data_f2_out(77), B => data_f3_out(77), S => - \data_valid_and_ready[2]_net_1\, Y => N_756); - - \data_temp_RNO_1[98]\ : MX2C - port map(A => N_1723, B => N_786, S => N_1580, Y => - \data_selected[130]\); - - \data_temp[31]\ : DFN1C0 - port map(D => \data_temp_5[31]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[31]_net_1\); - - \data_temp_RNO_1[102]\ : MX2C - port map(A => N_1713, B => N_790, S => N_1580_2, Y => - \data_selected[134]\); - - \data_temp[3]\ : DFN1C0 - port map(D => \data_temp_5[3]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[3]_net_1\); - - \data_temp_RNO_2[74]\ : MX2C - port map(A => data_f2_out(106), B => data_f3_out(106), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_729); - - \data_temp[65]\ : DFN1C0 - port map(D => \data_temp_5[65]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[65]_net_1\); - - \data_temp[57]\ : DFN1C0 - port map(D => \data_temp_5[57]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[57]_net_1\); - - \data_temp_RNO_3[115]\ : MX2C - port map(A => data_f0_out(147), B => data_f1_out(147), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_775); - - \data_temp[7]\ : DFN1C0 - port map(D => \data_temp_5[7]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[7]_net_1\); - - \data_temp_RNO[33]\ : NOR3 - port map(A => \data_temp_5_i_0[33]\, B => N_868, C => - N_863_0, Y => N_219); - - \data_temp_RNO_2[44]\ : MX2C - port map(A => data_f2_out(76), B => data_f3_out(76), S => - \data_valid_and_ready[2]_net_1\, Y => N_755); - - \data_temp_RNO_2[118]\ : MX2C - port map(A => data_f2_out(150), B => data_f3_out(150), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1701); - - \data_temp_RNO_1[116]\ : MX2C - port map(A => N_1699, B => N_776, S => N_1580_2, Y => - \data_selected[148]\); - - \data_temp[96]\ : DFN1C0 - port map(D => \data_temp_5[96]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[96]_net_1\); - - \data_temp_RNO_0[87]\ : MX2C - port map(A => \data_temp[119]_net_1\, B => - \data_selected[119]\, S => \state[4]_net_1\, Y => N_688); - - \data_temp[115]\ : DFN1C0 - port map(D => \data_temp_5[115]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[115]_net_1\); - - \data_temp_RNO_3[100]\ : MX2C - port map(A => data_f0_out(132), B => data_f1_out(132), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_788); - - \data[14]\ : DFN1C0 - port map(D => \data_5[14]\, CLK => lclk_c, CLR => rstn, Q - => wdata(14)); - - \data_temp_RNO_2[97]\ : MX2C - port map(A => data_f2_out(129), B => data_f3_out(129), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1722); - - \data_temp_RNO_0[123]\ : NOR2 - port map(A => N_1692, B => N_911, Y => N_910); - - \data_temp_RNO[71]\ : NOR2 - port map(A => N_863_2, B => N_672, Y => \data_temp_5[71]\); - - \data_temp[43]\ : DFN1C0 - port map(D => N_239, CLK => lclk_c, CLR => rstn, Q => - \data_temp[43]_net_1\); - - \data_temp_RNO_0[46]\ : MX2C - port map(A => \data_temp[78]_net_1\, B => - \data_selected[78]\, S => \state[4]_net_1\, Y => N_647); - - \data_temp_RNO_1[60]\ : MX2C - port map(A => N_743, B => N_832, S => N_1580_1, Y => - \data_selected[92]\); - - \data_temp_RNO_1[121]\ : MX2C - port map(A => N_1690, B => N_1678, S => N_1580, Y => - \data_selected[153]\); - - \data_temp_RNO_2[36]\ : MX2 - port map(A => data_f0_out(68), B => data_f1_out(68), S => - \data_valid_and_ready[0]_net_1\, Y => N_850); - - \data_temp_RNO[72]\ : NOR2 - port map(A => N_863_2, B => N_673, Y => \data_temp_5[72]\); - - \data_temp_RNO[116]\ : NOR2 - port map(A => N_863_2, B => N_717, Y => \data_temp_5[116]\); - - \data_temp_RNO_0[90]\ : MX2C - port map(A => \data_temp[122]_net_1\, B => - \data_selected[122]\, S => \state[4]_net_1\, Y => N_691); - - \data_RNO[24]\ : NOR2A - port map(A => \data_temp[24]_net_1\, B => \state[4]_net_1\, - Y => \data_5[24]\); - - \data_temp_RNO_1[109]\ : MX2C - port map(A => N_1706, B => N_783, S => N_1580, Y => - \data_selected[141]\); - - \data_temp_RNO[90]\ : NOR2 - port map(A => N_863, B => N_691, Y => \data_temp_5[90]\); - - \data_temp_RNO[48]\ : NOR2 - port map(A => N_863_0, B => N_649, Y => \data_temp_5[48]\); - - \data_temp_RNO_1[108]\ : MX2C - port map(A => N_1705, B => N_782, S => N_1580_1, Y => - \data_selected[140]\); - - \data_temp[72]\ : DFN1C0 - port map(D => \data_temp_5[72]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[72]_net_1\); - - \data_temp_RNO_2[111]\ : MX2C - port map(A => data_f2_out(143), B => data_f3_out(143), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1708); - - \data_temp_RNO[5]\ : NOR2A - port map(A => \data_temp[37]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[5]\); - - \data_temp_RNO_4[43]\ : MX2 - port map(A => data_f2_out(75), B => data_f3_out(75), S => - \data_valid_and_ready[2]_net_1\, Y => N_768); - - \data_temp_RNO[55]\ : NOR2 - port map(A => N_863_1, B => N_656, Y => \data_temp_5[55]\); - - \data_temp_RNO_0[67]\ : MX2C - port map(A => \data_temp[99]_net_1\, B => - \data_selected[99]\, S => \state[4]_net_1\, Y => N_668); - - \data_temp_RNO_0[43]\ : AO1D - port map(A => N_912_i, B => N_843, C => N_897, Y => - \data_temp_5_i_0[43]\); - - \data_temp[38]\ : DFN1C0 - port map(D => N_229, CLK => lclk_c, CLR => rstn, Q => - \data_temp[38]_net_1\); - - \data_RNO[20]\ : NOR2A - port map(A => \data_temp[20]_net_1\, B => \state[4]_net_1\, - Y => \data_5[20]\); - - \data_temp_RNO[85]\ : NOR2 - port map(A => N_863_2, B => N_686, Y => \data_temp_5[85]\); - - \data_temp_RNO[7]\ : NOR2A - port map(A => \data_temp[39]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[7]\); - - \data_temp_RNO[43]\ : NOR3 - port map(A => \data_temp_5_i_0[43]\, B => N_898, C => - N_863_0, Y => N_239); - - \data_temp[103]\ : DFN1C0 - port map(D => \data_temp_5[103]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[103]_net_1\); - - \data[10]\ : DFN1C0 - port map(D => \data_5[10]\, CLK => lclk_c, CLR => rstn, Q - => wdata(10)); - - \data_temp_RNO_2[33]\ : MX2 - port map(A => data_f0_out(65), B => data_f1_out(65), S => - \data_valid_and_ready_0[0]_net_1\, Y => N_770); - - \data_temp_RNO_3[58]\ : MX2C - port map(A => data_f0_out(90), B => data_f1_out(90), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_830); - - \data_temp_RNO_3[68]\ : MX2C - port map(A => data_f0_out(100), B => data_f1_out(100), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_826); - - \data_temp_RNO_0[102]\ : MX2C - port map(A => \data_temp[102]_net_1\, B => - \data_selected[134]\, S => \state[4]_net_1\, Y => N_703); - - \state[4]\ : DFN1P0 - port map(D => N_861, CLK => lclk_c, PRE => rstn, Q => - \state_0[4]\); - - \data_temp_RNO_3[88]\ : MX2C - port map(A => data_f0_out(120), B => data_f1_out(120), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_804); - - \data_temp_RNO[74]\ : NOR2 - port map(A => N_863_2, B => N_675, Y => \data_temp_5[74]\); - - \data_temp_RNO_2[59]\ : MX2C - port map(A => data_f2_out(91), B => data_f3_out(91), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_742); - - \data_temp_RNO_2[51]\ : MX2C - port map(A => data_f2_out(83), B => data_f3_out(83), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_748); - - \data_temp_RNO_0[109]\ : MX2C - port map(A => \data_temp[109]_net_1\, B => - \data_selected[141]\, S => \state[4]_net_1\, Y => N_710); - - \data_temp_RNO_3[113]\ : MX2C - port map(A => data_f0_out(145), B => data_f1_out(145), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_773); - - \data_temp_RNO_1[62]\ : MX2C - port map(A => N_745, B => N_820, S => N_1580_1, Y => - \data_selected[94]\); - - \data_temp_RNO_1[114]\ : MX2C - port map(A => N_1697, B => N_774, S => N_1580_2, Y => - \data_selected[146]\); - - \data_temp_RNO_0[92]\ : NOR2 - port map(A => N_1731, B => N_911, Y => N_900); - - \data_valid_and_ready[3]\ : NOR2A - port map(A => valid_out_3, B => ready_i_0_3, Y => - \data_valid_and_ready[3]_net_1\); - - \data_temp[37]\ : DFN1C0 - port map(D => N_227, CLK => lclk_c, CLR => rstn, Q => - \data_temp[37]_net_1\); - - \data_temp[71]\ : DFN1C0 - port map(D => \data_temp_5[71]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[71]_net_1\); - - \data_temp_RNO_3[70]\ : MX2C - port map(A => data_f0_out(102), B => data_f1_out(102), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_814); - - \data_temp_RNO_0[39]\ : AO1D - port map(A => N_912_i, B => N_853, C => N_1659, Y => - \data_temp_5_i_0[39]\); - - \data_temp[25]\ : DFN1C0 - port map(D => \data_temp_5[25]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[25]_net_1\); - - \data_temp_RNO[9]\ : NOR2A - port map(A => \data_temp[41]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[9]\); - - \state_RNIT8OCE2_4[4]\ : NOR2 - port map(A => \data_temp_5_i_a2_0_0[32]_net_1\, B => N_911, - Y => N_863); - - \data_RNO[25]\ : NOR2A - port map(A => \data_temp[25]_net_1\, B => \state[4]_net_1\, - Y => \data_5[25]\); - - \data_temp_RNO_0[70]\ : MX2C - port map(A => \data_temp[102]_net_1\, B => - \data_selected[102]\, S => \state[4]_net_1\, Y => N_671); - - \data_temp[55]\ : DFN1C0 - port map(D => \data_temp_5[55]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[55]_net_1\); - - \data_temp_RNO_1[77]\ : MX2C - port map(A => N_732, B => N_807, S => N_1580, Y => - \data_selected[109]\); - - \data_temp_RNO_2[88]\ : MX2C - port map(A => data_f2_out(120), B => data_f3_out(120), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1727); - - \data_temp_RNO_2[113]\ : MX2C - port map(A => data_f2_out(145), B => data_f3_out(145), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1710); - - \data_temp_RNO_3[38]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[70]_net_1\, - Y => N_1656); - - \data_temp[40]\ : DFN1C0 - port map(D => N_233, CLK => lclk_c, CLR => rstn, Q => - \data_temp[40]_net_1\); - - \data_temp_RNO[120]\ : NOR2 - port map(A => N_863, B => N_721, Y => \data_temp_5[120]\); - - \data_temp_RNO_1[87]\ : MX2C - port map(A => N_1726, B => N_803, S => N_1580, Y => - \data_selected[119]\); - - \data_temp[12]\ : DFN1C0 - port map(D => \data_temp_5[12]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[12]_net_1\); - - \data_temp_RNO_2[55]\ : MX2C - port map(A => data_f2_out(87), B => data_f3_out(87), S => - \data_valid_and_ready[2]_net_1\, Y => N_752); - - \data_temp_RNO_3[72]\ : MX2C - port map(A => data_f0_out(104), B => data_f1_out(104), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_816); - - \data_wen[1]\ : DFN1E0P0 - port map(D => \data_wen_3[1]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => data_wen(1)); - - \data_temp_RNO[19]\ : NOR2A - port map(A => \data_temp[51]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[19]\); - - \data_temp[94]\ : DFN1C0 - port map(D => \data_temp_5[94]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[94]_net_1\); - - \data_temp[78]\ : DFN1C0 - port map(D => \data_temp_5[78]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[78]_net_1\); - - \data_temp_RNO_2[68]\ : MX2C - port map(A => data_f2_out(100), B => data_f3_out(100), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_737); - - \data_temp_RNO_3[101]\ : MX2C - port map(A => data_f0_out(133), B => data_f1_out(133), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_789); - - \data_temp_RNO_2[54]\ : MX2C - port map(A => data_f2_out(86), B => data_f3_out(86), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_751); - - \data_temp_RNO_1[97]\ : MX2C - port map(A => N_1722, B => N_785, S => N_1580, Y => - \data_selected[129]\); - - \data_temp_RNO_0[72]\ : MX2C - port map(A => \data_temp[104]_net_1\, B => - \data_selected[104]\, S => \state[4]_net_1\, Y => N_673); - - \data_temp_RNO_0[35]\ : AO1D - port map(A => N_912_i, B => N_849, C => N_873, Y => - \data_temp_5_i_0[35]\); - - \data_RNO[7]\ : NOR2A - port map(A => \data_temp[7]_net_1\, B => \state[4]_net_1\, - Y => \data_5[7]\); - - \data_temp_RNO[31]\ : NOR2A - port map(A => \data_temp[63]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[31]\); - - \data_temp_RNO_0[108]\ : MX2C - port map(A => \data_temp[108]_net_1\, B => - \data_selected[140]\, S => \state[4]_net_1\, Y => N_709); - - \data[27]\ : DFN1C0 - port map(D => \data_5[27]\, CLK => lclk_c, CLR => rstn, Q - => wdata(27)); - - \data_temp[5]\ : DFN1C0 - port map(D => \data_temp_5[5]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[5]_net_1\); - - \data_temp_RNO[32]\ : NOR3 - port map(A => \data_temp_5_i_0[32]\, B => N_865, C => - N_863_0, Y => N_215); - - \data_temp_RNO[16]\ : NOR2A - port map(A => \data_temp[48]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[16]\); - - \data_temp_RNO_0[34]\ : AO1D - port map(A => N_912_i, B => N_848, C => N_870, Y => - \data_temp_5_i_0[34]\); - - \data_temp_RNO[100]\ : NOR2 - port map(A => N_863, B => N_701, Y => \data_temp_5[100]\); - - \state[1]\ : DFN1C0 - port map(D => \state[2]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[1]_net_1\); - - \data_temp_RNIVP6OE2[125]\ : AO1D - port map(A => \state[4]_net_1\, B => \data_temp[125]_net_1\, - C => N_863_0, Y => N_1582); - - \data_temp[102]\ : DFN1C0 - port map(D => \data_temp_5[102]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[102]_net_1\); - - \data_temp_RNO_1[56]\ : MX2C - port map(A => N_753, B => N_828, S => N_1580_0, Y => - \data_selected[88]\); - - \data_temp[77]\ : DFN1C0 - port map(D => \data_temp_5[77]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[77]_net_1\); - - \data_temp[11]\ : DFN1C0 - port map(D => \data_temp_5[11]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[11]_net_1\); - - \data_temp[89]\ : DFN1C0 - port map(D => \data_temp_5[89]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[89]_net_1\); - - \data_RNO[0]\ : NOR2A - port map(A => \data_temp[0]_net_1\, B => \state[4]_net_1\, - Y => \data_5[0]\); - - \data_temp_RNO_4[32]\ : MX2 - port map(A => data_f2_out(64), B => data_f3_out(64), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1685); - - \data_temp_RNO[118]\ : NOR2 - port map(A => N_863, B => N_719, Y => \data_temp_5[118]\); - - \data_temp_RNO_2[76]\ : MX2C - port map(A => data_f2_out(108), B => data_f3_out(108), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_731); - - \data_temp_RNO_0[80]\ : MX2C - port map(A => \data_temp[112]_net_1\, B => - \data_selected[112]\, S => \state[4]_net_1\, Y => N_681); - - \data_temp_RNO_1[105]\ : MX2C - port map(A => N_1716, B => N_779, S => N_1580_2, Y => - \data_selected[137]\); - - \data_temp[35]\ : DFN1C0 - port map(D => N_223, CLK => lclk_c, CLR => rstn, Q => - \data_temp[35]_net_1\); - - \data_temp_RNO_2[90]\ : MX2C - port map(A => data_f2_out(122), B => data_f3_out(122), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1729); - - \data_temp_RNO_2[114]\ : MX2C - port map(A => data_f2_out(146), B => data_f3_out(146), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1697); - - data_selected_sn_m2_0_o2_1 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_1); - - \data_temp_RNO_2[46]\ : MX2C - port map(A => data_f2_out(78), B => data_f3_out(78), S => - \data_valid_and_ready[2]_net_1\, Y => N_757); - - \data_valid_and_ready_2[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready_2[0]_net_1\); - - \data_temp_RNO_1[53]\ : MX2C - port map(A => N_750, B => N_839, S => N_1580_0, Y => - \data_selected[85]\); - - \data_temp_RNO[34]\ : NOR3 - port map(A => \data_temp_5_i_0[34]\, B => N_871, C => - N_863_0, Y => N_221); - - \data_temp_RNO[0]\ : NOR2A - port map(A => \data_temp[32]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[0]\); - - \state_RNIM4O5V[4]\ : OR2A - port map(A => \state[4]_net_1\, B => - \data_valid_and_ready_0[0]_net_1\, Y => \time_wen_3[0]\); - - \data_temp_RNO[41]\ : NOR3 - port map(A => \data_temp_5_i_0[41]\, B => N_1666, C => - N_863_0, Y => N_235); - - \data_temp_RNO_3[105]\ : MX2C - port map(A => data_f0_out(137), B => data_f1_out(137), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_779); - - \data[8]\ : DFN1C0 - port map(D => \data_5[8]\, CLK => lclk_c, CLR => rstn, Q - => wdata(8)); - - \data_temp_RNO_2[73]\ : MX2C - port map(A => data_f2_out(105), B => data_f3_out(105), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1740); - - state_0_sqmuxa_i_0_o2_0_a2 : NOR2 - port map(A => \data_valid_and_ready[3]_net_1\, B => N_916, - Y => N_1306); - - \data_temp_RNO_2[108]\ : MX2C - port map(A => data_f2_out(140), B => data_f3_out(140), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1705); - - \data_temp_RNO[60]\ : NOR2 - port map(A => N_863_1, B => N_661, Y => \data_temp_5[60]\); - - \data_temp_RNO_1[106]\ : MX2C - port map(A => N_1717, B => N_780, S => N_1580_1, Y => - \data_selected[138]\); - - \data_temp_RNO[42]\ : NOR3 - port map(A => \data_temp_5_i_0[42]\, B => N_1669, C => - N_863_0, Y => N_237); - - \data_temp_RNO_2[43]\ : MX2 - port map(A => data_f0_out(75), B => data_f1_out(75), S => - \data_valid_and_ready[0]_net_1\, Y => N_843); - - \data_RNO[4]\ : NOR2A - port map(A => \data_temp[4]_net_1\, B => \state[4]_net_1\, - Y => \data_5[4]\); - - \data_temp_RNO_3[57]\ : MX2C - port map(A => data_f0_out(89), B => data_f1_out(89), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_829); - - \data_temp_RNO[126]\ : NOR2 - port map(A => N_863_0, B => N_727, Y => \data_temp_5[126]\); - - \data_temp_RNO_0[60]\ : MX2C - port map(A => \data_temp[92]_net_1\, B => - \data_selected[92]\, S => \state[4]_net_1\, Y => N_661); - - \data_temp_RNO_3[67]\ : MX2C - port map(A => data_f0_out(99), B => data_f1_out(99), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_825); - - \data_temp_RNO_2[117]\ : MX2C - port map(A => data_f2_out(149), B => data_f3_out(149), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1700); - - \data_temp_RNO_3[87]\ : MX2C - port map(A => data_f0_out(119), B => data_f1_out(119), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_803); - - \data_temp_RNO[58]\ : NOR2 - port map(A => N_863_1, B => N_659, Y => \data_temp_5[58]\); - - \data_temp[2]\ : DFN1C0 - port map(D => \data_temp_5[2]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[2]_net_1\); - - \data_temp_RNO[29]\ : NOR2A - port map(A => \data_temp[61]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[29]\); - - \data_temp[18]\ : DFN1C0 - port map(D => \data_temp_5[18]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[18]_net_1\); - - \data_temp_RNO_0[82]\ : MX2C - port map(A => \data_temp[114]_net_1\, B => - \data_selected[114]\, S => \state[4]_net_1\, Y => N_683); - - \data_temp_RNO[88]\ : NOR2 - port map(A => N_863, B => N_689, Y => \data_temp_5[88]\); - - \data_temp_RNO_2[92]\ : MX2 - port map(A => data_f2_out(124), B => data_f3_out(124), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1731); - - \data_temp_RNO[8]\ : NOR2A - port map(A => \data_temp[40]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[8]\); - - \data_temp[101]\ : DFN1C0 - port map(D => \data_temp_5[101]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[101]_net_1\); - - \data_temp_RNO_2[101]\ : MX2C - port map(A => data_f2_out(133), B => data_f3_out(133), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1712); - - \data_temp_RNO[53]\ : NOR2 - port map(A => N_863_1, B => N_654, Y => \data_temp_5[53]\); - - \data_temp_RNO[44]\ : NOR2 - port map(A => N_863_0, B => N_645, Y => \data_temp_5[44]\); - - \data_temp_RNO[83]\ : NOR2 - port map(A => N_863_2, B => N_684, Y => \data_temp_5[83]\); - - \time_en_temp[0]\ : DFN1E1C0 - port map(D => \data_valid_and_ready[0]_net_1\, CLK => - lclk_c, CLR => rstn, E => state_0_sqmuxa_i, Q => - \time_en_temp[0]_net_1\); - - \data_temp_RNO[26]\ : NOR2A - port map(A => \data_temp[58]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[26]\); - - \data_temp[126]\ : DFN1C0 - port map(D => \data_temp_5[126]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[126]_net_1\); - - \data_temp_RNO[106]\ : NOR2 - port map(A => N_863_2, B => N_707, Y => \data_temp_5[106]\); - - \data_temp[17]\ : DFN1C0 - port map(D => \data_temp_5[17]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[17]_net_1\); - - \data_temp[109]\ : DFN1C0 - port map(D => \data_temp_5[109]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[109]_net_1\); - - \data_temp_RNO_0[62]\ : MX2C - port map(A => \data_temp[94]_net_1\, B => - \data_selected[94]\, S => \state[4]_net_1\, Y => N_663); - - \data_RNO[23]\ : NOR2A - port map(A => \data_temp[23]_net_1\, B => \state[4]_net_1\, - Y => \data_5[23]\); - - \data[6]\ : DFN1C0 - port map(D => \data_5[6]\, CLK => lclk_c, CLR => rstn, Q - => wdata(6)); - - \data_temp_RNO[17]\ : NOR2A - port map(A => \data_temp[49]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[17]\); - - un23_data_selected_i_a2 : OR2A - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - N_1580_0, Y => N_916); - - \data_temp_RNO_2[87]\ : MX2C - port map(A => data_f2_out(119), B => data_f3_out(119), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1726); - - \data_temp_RNO[114]\ : NOR2 - port map(A => N_863_2, B => N_715, Y => \data_temp_5[114]\); - - \data_temp_RNO_3[103]\ : MX2C - port map(A => data_f0_out(135), B => data_f1_out(135), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_791); - - \data_temp_RNO_1[70]\ : MX2C - port map(A => N_739, B => N_814, S => N_1580_2, Y => - \data_selected[102]\); - - \data_temp[75]\ : DFN1C0 - port map(D => \data_temp_5[75]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[75]_net_1\); - - \data_temp_RNO_3[37]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[69]_net_1\, - Y => N_1653); - - \data_temp_RNO_1[38]\ : NOR2 - port map(A => N_911, B => N_763, Y => N_1657); - - \data_temp_RNO_1[104]\ : MX2C - port map(A => N_1715, B => N_778, S => N_1580_2, Y => - \data_selected[136]\); - - \data_temp[46]\ : DFN1C0 - port map(D => \data_temp_5[46]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[46]_net_1\); - - \data_temp_RNO[111]\ : NOR2 - port map(A => N_863_2, B => N_712, Y => \data_temp_5[111]\); - - \data_temp_RNO_2[110]\ : MX2C - port map(A => data_f2_out(142), B => data_f3_out(142), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1707); - - \data_temp[69]\ : DFN1C0 - port map(D => \data_temp_5[69]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[69]_net_1\); - - \data_temp_RNO_1[80]\ : MX2C - port map(A => N_1733, B => N_810, S => N_1580_1, Y => - \data_selected[112]\); - - \data_temp_RNO_2[67]\ : MX2C - port map(A => data_f2_out(99), B => data_f3_out(99), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_736); - - \data_RNO[27]\ : NOR2A - port map(A => \data_temp[27]_net_1\, B => \state[4]_net_1\, - Y => \data_5[27]\); - - \data_temp_RNO[6]\ : NOR2A - port map(A => \data_temp[38]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[6]\); - - \data_temp_RNO_0[126]\ : MX2C - port map(A => \data_temp[126]_net_1\, B => - \data_selected[158]\, S => \state[4]_net_1\, Y => N_727); - - \data_temp_RNO_1[90]\ : MX2C - port map(A => N_1729, B => N_792, S => N_1580, Y => - \data_selected[122]\); - - \data[23]\ : DFN1C0 - port map(D => \data_5[23]\, CLK => lclk_c, CLR => rstn, Q - => wdata(23)); - - \data_temp_RNO_2[103]\ : MX2C - port map(A => data_f2_out(135), B => data_f3_out(135), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1714); - - \data_temp_RNO_1[72]\ : MX2C - port map(A => N_1739, B => N_816, S => N_1580_2, Y => - \data_selected[104]\); - - \data_temp_RNO_0[58]\ : MX2C - port map(A => \data_temp[90]_net_1\, B => - \data_selected[90]\, S => \state[4]_net_1\, Y => N_659); - - \data_temp_RNO_1[117]\ : MX2C - port map(A => N_1700, B => N_777, S => N_1580_2, Y => - \data_selected[149]\); - - \data_temp[4]\ : DFN1C0 - port map(D => \data_temp_5[4]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[4]_net_1\); - - \state_RNIBMG5L1_0[4]\ : OR2A - port map(A => \state[4]_net_1\, B => N_1580_0, Y => N_911); - - \data_wen_RNO[2]\ : OR2 - port map(A => \time_en_temp[2]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[2]\); - - \data_temp_RNO_3[48]\ : MX2C - port map(A => data_f0_out(80), B => data_f1_out(80), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_834); - - \data_temp[92]\ : DFN1C0 - port map(D => N_241, CLK => lclk_c, CLR => rstn, Q => - \data_temp[92]_net_1\); - - \data_temp_RNO_2[56]\ : MX2C - port map(A => data_f2_out(88), B => data_f3_out(88), S => - \data_valid_and_ready[2]_net_1\, Y => N_753); - - \data_temp_RNO[70]\ : NOR2 - port map(A => N_863_2, B => N_671, Y => \data_temp_5[70]\); - - \data_temp_RNO_1[82]\ : MX2C - port map(A => N_1735, B => N_812, S => N_1580_2, Y => - \data_selected[114]\); - - \data_RNO[18]\ : NOR2A - port map(A => \data_temp[18]_net_1\, B => \state[4]_net_1\, - Y => \data_5[18]\); - - \time_wen[0]\ : DFN1E0P0 - port map(D => \time_wen_3[0]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => time_wen(0)); - - \data_temp_RNO_1[120]\ : MX2C - port map(A => N_1703, B => N_1677, S => N_1580, Y => - \data_selected[152]\); - - \data_temp_RNO_0[36]\ : AO1D - port map(A => N_912_i, B => N_850, C => N_1650, Y => - \data_temp_5_i_0[36]\); - - \data_temp_RNO_2[53]\ : MX2C - port map(A => data_f2_out(85), B => data_f3_out(85), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_750); - - \data_temp_RNO_1[69]\ : MX2C - port map(A => N_738, B => N_813, S => N_1580_2, Y => - \data_selected[101]\); - - \data_temp_RNO_1[61]\ : MX2C - port map(A => N_744, B => N_833, S => N_1580_1, Y => - \data_selected[93]\); - - \state_RNIV3KC[3]\ : NOR2 - port map(A => \state[4]_net_1\, B => \state[3]_net_1\, Y - => N_929); - - \state[0]\ : DFN1C0 - port map(D => \state[1]_net_1\, CLK => lclk_c, CLR => rstn, - Q => \state[0]_net_1\); - - \data_temp_RNO[27]\ : NOR2A - port map(A => \data_temp[59]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[27]\); - - \data_temp_RNO_1[92]\ : NOR2 - port map(A => N_912_i, B => N_794, Y => N_899); - - \data_temp_RNO_0[99]\ : MX2C - port map(A => \data_temp[99]_net_1\, B => - \data_selected[131]\, S => \state[4]_net_1\, Y => N_700); - - \data_temp_RNO_0[91]\ : NOR2 - port map(A => N_1730, B => N_911, Y => N_908); - - \data_temp[15]\ : DFN1C0 - port map(D => \data_temp_5[15]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[15]_net_1\); - - \data_temp_RNO[119]\ : NOR2 - port map(A => N_863, B => N_720, Y => \data_temp_5[119]\); - - \data_RNO[1]\ : NOR2A - port map(A => \data_temp[1]_net_1\, B => \state[4]_net_1\, - Y => \data_5[1]\); - - \data_temp_RNO_3[117]\ : MX2C - port map(A => data_f0_out(149), B => data_f1_out(149), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_777); - - \state_RNIT8OCE2_0[4]\ : OR3B - port map(A => \data_valid_and_ready_0[2]_net_1\, B => - \data_valid_and_ready[3]_net_1\, C => N_911, Y => N_860); - - \data_temp_RNO_0[33]\ : AO1D - port map(A => N_912_i, B => N_770, C => N_867, Y => - \data_temp_5_i_0[33]\); - - \data_temp[91]\ : DFN1C0 - port map(D => N_249, CLK => lclk_c, CLR => rstn, Q => - \data_temp[91]_net_1\); - - \data_temp_RNO_0[125]\ : NOR2 - port map(A => N_1694, B => N_911, Y => N_906); - - \data_temp_RNO_0[110]\ : MX2C - port map(A => \data_temp[110]_net_1\, B => - \data_selected[142]\, S => \state[4]_net_1\, Y => N_711); - - \state_RNIT8OCE2[4]\ : NOR2A - port map(A => \state[4]_net_1\, B => N_1306, Y => - state_0_sqmuxa_i); - - \data_temp_RNO_1[48]\ : MX2C - port map(A => N_759, B => N_834, S => N_1580_0, Y => - \data_selected[80]\); - - \data_temp_RNO[15]\ : NOR2A - port map(A => \data_temp[47]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[15]\); - - \data[18]\ : DFN1C0 - port map(D => \data_5[18]\, CLK => lclk_c, CLR => rstn, Q - => wdata(18)); - - \data_temp[29]\ : DFN1C0 - port map(D => \data_temp_5[29]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[29]_net_1\); - - \data_temp_RNO_3[50]\ : MX2C - port map(A => data_f0_out(82), B => data_f1_out(82), S => - \data_valid_and_ready[0]_net_1\, Y => N_836); - - \data_temp[110]\ : DFN1C0 - port map(D => \data_temp_5[110]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[110]_net_1\); - - data_selected_sn_m2_0_o2_0 : OR2A - port map(A => \data_valid_and_ready_0[0]_net_1\, B => - \data_valid_and_ready[1]_net_1\, Y => N_1580_0); - - \data_temp_RNO[51]\ : NOR2 - port map(A => N_863_1, B => N_652, Y => \data_temp_5[51]\); - - \data_temp_RNO[113]\ : NOR2 - port map(A => N_863_2, B => N_714, Y => \data_temp_5[113]\); - - \data_temp_RNO_3[60]\ : MX2C - port map(A => data_f0_out(92), B => data_f1_out(92), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_832); - - \data_temp[123]\ : DFN1C0 - port map(D => N_251, CLK => lclk_c, CLR => rstn, Q => - \data_temp[123]_net_1\); - - \data_temp_RNO_3[80]\ : MX2C - port map(A => data_f0_out(112), B => data_f1_out(112), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_810); - - \data_temp_RNO_2[104]\ : MX2C - port map(A => data_f2_out(136), B => data_f3_out(136), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1715); - - \data_temp_RNO[81]\ : NOR2 - port map(A => N_863_2, B => N_682, Y => \data_temp_5[81]\); - - \data_temp_RNO[1]\ : NOR2A - port map(A => \data_temp[33]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[1]\); - - \data_temp[59]\ : DFN1C0 - port map(D => \data_temp_5[59]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[59]_net_1\); - - \data_temp_RNO[52]\ : NOR2 - port map(A => N_863_1, B => N_653, Y => \data_temp_5[52]\); - - \data_temp_RNO[82]\ : NOR2 - port map(A => N_863_2, B => N_683, Y => \data_temp_5[82]\); - - \data_temp_RNO[108]\ : NOR2 - port map(A => N_863_1, B => N_709, Y => \data_temp_5[108]\); - - \data_temp_RNO_3[112]\ : MX2C - port map(A => data_f0_out(144), B => data_f1_out(144), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_772); - - \data_temp_RNO_3[79]\ : MX2C - port map(A => data_f0_out(111), B => data_f1_out(111), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_809); - - \data_temp_RNO_3[71]\ : MX2C - port map(A => data_f0_out(103), B => data_f1_out(103), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_815); - - \data_temp[44]\ : DFN1C0 - port map(D => \data_temp_5[44]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[44]_net_1\); - - \data_temp_RNO_1[65]\ : MX2C - port map(A => N_734, B => N_823, S => N_1580, Y => - \data_selected[97]\); - - \data_temp_RNO_2[107]\ : MX2C - port map(A => data_f2_out(139), B => data_f3_out(139), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1704); - - \data_temp_RNO_3[98]\ : MX2C - port map(A => data_f0_out(130), B => data_f1_out(130), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_786); - - \data_temp_RNO_0[95]\ : MX2C - port map(A => \data_temp[127]_net_1\, B => - \data_selected[127]\, S => \state[4]_net_1\, Y => N_696); - - \data_temp_RNO_0[79]\ : MX2C - port map(A => \data_temp[111]_net_1\, B => - \data_selected[111]\, S => \state[4]_net_1\, Y => N_680); - - \data_temp_RNO_0[71]\ : MX2C - port map(A => \data_temp[103]_net_1\, B => - \data_selected[103]\, S => \state[4]_net_1\, Y => N_672); - - \data_valid_ack_RNO[3]\ : INV - port map(A => N_860, Y => N_860_i); - - \data_temp_RNO_3[52]\ : MX2C - port map(A => data_f0_out(84), B => data_f1_out(84), S => - \data_valid_and_ready[0]_net_1\, Y => N_838); - - \data_temp[98]\ : DFN1C0 - port map(D => \data_temp_5[98]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[98]_net_1\); - - \data_temp_RNO[54]\ : NOR2 - port map(A => N_863_1, B => N_655, Y => \data_temp_5[54]\); - - \data_valid_and_ready_1[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready_1[0]_net_1\); - - \data_temp_RNO_3[62]\ : MX2C - port map(A => data_f0_out(94), B => data_f1_out(94), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_820); - - \data_temp_RNO_1[37]\ : NOR2 - port map(A => N_911, B => N_762, Y => N_1654); - - \data_temp_RNO_3[82]\ : MX2C - port map(A => data_f0_out(114), B => data_f1_out(114), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_812); - - \data_temp_RNO_1[64]\ : MX2C - port map(A => N_747, B => N_822, S => N_1580, Y => - \data_selected[96]\); - - \data_temp_RNO[84]\ : NOR2 - port map(A => N_863_2, B => N_685, Y => \data_temp_5[84]\); - - \data_temp_RNO_2[80]\ : MX2C - port map(A => data_f2_out(112), B => data_f3_out(112), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1733); - - \data_temp_RNO_0[94]\ : MX2C - port map(A => \data_temp[126]_net_1\, B => - \data_selected[126]\, S => \state[4]_net_1\, Y => N_695); - - \data_temp_RNO_0[127]\ : MX2C - port map(A => \data_temp[127]_net_1\, B => - \data_selected[159]\, S => \state[4]_net_1\, Y => N_728); - - \data_temp[83]\ : DFN1C0 - port map(D => \data_temp_5[83]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[83]_net_1\); - - \data_temp_RNO_3[116]\ : MX2C - port map(A => data_f0_out(148), B => data_f1_out(148), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_776); - - \data[4]\ : DFN1C0 - port map(D => \data_5[4]\, CLK => lclk_c, CLR => rstn, Q - => wdata(4)); - - \data[11]\ : DFN1C0 - port map(D => \data_5[11]\, CLK => lclk_c, CLR => rstn, Q - => wdata(11)); - - \data_temp_RNO[124]\ : NOR3 - port map(A => N_904, B => N_903, C => N_1583, Y => N_245); - - \data_valid_and_ready_3[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready_3[0]_net_1\); - - \data_RNO[21]\ : NOR2A - port map(A => \data_temp[21]_net_1\, B => \state[4]_net_1\, - Y => \data_5[21]\); - - \data_temp_RNO_4[39]\ : MX2 - port map(A => data_f2_out(71), B => data_f3_out(71), S => - \data_valid_and_ready[2]_net_1\, Y => N_764); - - \data_temp[97]\ : DFN1C0 - port map(D => \data_temp_5[97]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[97]_net_1\); - - \data_RNO[22]\ : NOR2A - port map(A => \data_temp[22]_net_1\, B => \state[4]_net_1\, - Y => \data_5[22]\); - - \data_temp_RNO_2[60]\ : MX2C - port map(A => data_f2_out(92), B => data_f3_out(92), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_743); - - \data_temp_RNO[30]\ : NOR2A - port map(A => \data_temp[62]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[30]\); - - \data_temp_RNO[25]\ : NOR2A - port map(A => \data_temp[57]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[25]\); - - \data_temp_RNO[121]\ : NOR2 - port map(A => N_863, B => N_722, Y => \data_temp_5[121]\); - - \time_en_temp[3]\ : DFN1E1C0 - port map(D => N_916, CLK => lclk_c, CLR => rstn, E => - state_0_sqmuxa_i, Q => \time_en_temp[3]_net_1\); - - \data_temp_RNO_3[75]\ : MX2C - port map(A => data_f0_out(107), B => data_f1_out(107), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_819); - - \data_temp_RNO_3[124]\ : MX2 - port map(A => data_f0_out(156), B => data_f1_out(156), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1681); - - \data_temp_RNO_0[57]\ : MX2C - port map(A => \data_temp[89]_net_1\, B => - \data_selected[89]\, S => \state[4]_net_1\, Y => N_658); - - \data_temp[39]\ : DFN1C0 - port map(D => N_231, CLK => lclk_c, CLR => rstn, Q => - \data_temp[39]_net_1\); - - \data_temp_RNO_3[47]\ : MX2C - port map(A => data_f0_out(79), B => data_f1_out(79), S => - \data_valid_and_ready[0]_net_1\, Y => N_847); - - \data_temp_RNO_1[113]\ : MX2C - port map(A => N_1710, B => N_773, S => N_1580_1, Y => - \data_selected[145]\); - - \data_temp_RNO_2[82]\ : MX2C - port map(A => data_f2_out(114), B => data_f3_out(114), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1735); - - \data_temp_RNO_0[75]\ : MX2C - port map(A => \data_temp[107]_net_1\, B => - \data_selected[107]\, S => \state[4]_net_1\, Y => N_676); - - \data_temp_RNO_3[32]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[64]_net_1\, - Y => N_864); - - \data_temp_RNO_3[74]\ : MX2C - port map(A => data_f0_out(106), B => data_f1_out(106), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_818); - - \data_temp_RNO_2[100]\ : MX2C - port map(A => data_f2_out(132), B => data_f3_out(132), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1711); - - \data_temp_RNO_2[112]\ : MX2C - port map(A => data_f2_out(144), B => data_f3_out(144), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1709); - - \data_temp_RNO_0[48]\ : MX2C - port map(A => \data_temp[80]_net_1\, B => - \data_selected[80]\, S => \state[4]_net_1\, Y => N_649); - - \data_temp_RNO_2[115]\ : MX2C - port map(A => data_f2_out(147), B => data_f3_out(147), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1698); - - \data_temp_RNO[104]\ : NOR2 - port map(A => N_863_2, B => N_705, Y => \data_temp_5[104]\); - - \data_temp_RNO_2[38]\ : MX2 - port map(A => data_f0_out(70), B => data_f1_out(70), S => - \data_valid_and_ready[0]_net_1\, Y => N_852); - - \data_temp[122]\ : DFN1C0 - port map(D => \data_temp_5[122]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[122]_net_1\); - - \data_temp[8]\ : DFN1C0 - port map(D => \data_temp_5[8]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[8]_net_1\); - - \data[26]\ : DFN1C0 - port map(D => \data_5[26]\, CLK => lclk_c, CLR => rstn, Q - => wdata(26)); - - \data_temp_RNO_0[74]\ : MX2C - port map(A => \data_temp[106]_net_1\, B => - \data_selected[106]\, S => \state[4]_net_1\, Y => N_675); - - \data_temp_RNO_1[122]\ : MX2C - port map(A => N_1691, B => N_1679, S => N_1580, Y => - \data_selected[154]\); - - \data_temp_RNO_0[89]\ : MX2C - port map(A => \data_temp[121]_net_1\, B => - \data_selected[121]\, S => \state[4]_net_1\, Y => N_690); - - \data_temp_RNO_0[81]\ : MX2C - port map(A => \data_temp[113]_net_1\, B => - \data_selected[113]\, S => \state[4]_net_1\, Y => N_682); - - \data_temp_RNO[101]\ : NOR2 - port map(A => N_863_2, B => N_702, Y => \data_temp_5[101]\); - - \data_temp_RNO_2[99]\ : MX2C - port map(A => data_f2_out(131), B => data_f3_out(131), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1724); - - \data_temp_RNO_2[91]\ : MX2 - port map(A => data_f2_out(123), B => data_f3_out(123), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1730); - - \data_temp_RNO_2[62]\ : MX2C - port map(A => data_f2_out(94), B => data_f3_out(94), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_745); - - \data_temp_RNO_3[119]\ : MX2C - port map(A => data_f0_out(151), B => data_f1_out(151), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1676); - - \data_temp_RNO[40]\ : NOR3 - port map(A => \data_temp_5_i_0[40]\, B => N_1663, C => - N_863_0, Y => N_233); - - \data_temp_RNO[99]\ : NOR2 - port map(A => N_863, B => N_700, Y => \data_temp_5[99]\); - - \data_temp_RNO_4[35]\ : MX2 - port map(A => data_f2_out(67), B => data_f3_out(67), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1688); - - \data[12]\ : DFN1C0 - port map(D => \data_5[12]\, CLK => lclk_c, CLR => rstn, Q - => wdata(12)); - - \data_temp_RNO_1[107]\ : MX2C - port map(A => N_1704, B => N_781, S => N_1580_1, Y => - \data_selected[139]\); - - \data_temp[104]\ : DFN1C0 - port map(D => \data_temp_5[104]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[104]_net_1\); - - \data_temp_RNO_3[120]\ : MX2C - port map(A => data_f0_out(152), B => data_f1_out(152), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1677); - - \data_temp_RNO_1[47]\ : MX2C - port map(A => N_758, B => N_847, S => N_1580_0, Y => - \data_selected[79]\); - - \data_temp_RNO_4[34]\ : MX2 - port map(A => data_f2_out(66), B => data_f3_out(66), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1687); - - \data_temp_RNO_0[69]\ : MX2C - port map(A => \data_temp[101]_net_1\, B => - \data_selected[101]\, S => \state[4]_net_1\, Y => N_670); - - \data_temp_RNO_0[61]\ : MX2C - port map(A => \data_temp[93]_net_1\, B => - \data_selected[93]\, S => \state[4]_net_1\, Y => N_662); - - \data_temp_RNO[96]\ : NOR2 - port map(A => N_863, B => N_697, Y => \data_temp_5[96]\); - - \data_temp[107]\ : DFN1C0 - port map(D => \data_temp_5[107]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[107]_net_1\); - - \data_temp[80]\ : DFN1C0 - port map(D => \data_temp_5[80]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[80]_net_1\); - - \data_temp_RNO_2[116]\ : MX2C - port map(A => data_f2_out(148), B => data_f3_out(148), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1699); - - \data_temp_RNO[18]\ : NOR2A - port map(A => \data_temp[50]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[18]\); - - \data_temp[95]\ : DFN1C0 - port map(D => \data_temp_5[95]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[95]_net_1\); - - \data_temp[63]\ : DFN1C0 - port map(D => \data_temp_5[63]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[63]_net_1\); - - \data_temp_RNO[123]\ : NOR3 - port map(A => N_910, B => N_909, C => N_1581, Y => N_251); - - GND_i_0 : GND - port map(Y => GND_0); - - \data_temp_RNO_0[85]\ : MX2C - port map(A => \data_temp[117]_net_1\, B => - \data_selected[117]\, S => \state[4]_net_1\, Y => N_686); - - \data_temp[121]\ : DFN1C0 - port map(D => \data_temp_5[121]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[121]_net_1\); - - \data_temp[79]\ : DFN1C0 - port map(D => \data_temp_5[79]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[79]_net_1\); - - \data_temp_RNO_3[107]\ : MX2C - port map(A => data_f0_out(139), B => data_f1_out(139), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_781); - - \data[30]\ : DFN1C0 - port map(D => \data_5[30]\, CLK => lclk_c, CLR => rstn, Q - => wdata(30)); - - \data_temp_RNO_0[122]\ : MX2C - port map(A => \data_temp[122]_net_1\, B => - \data_selected[154]\, S => \state[4]_net_1\, Y => N_723); - - \data_temp_RNO_2[95]\ : MX2C - port map(A => data_f2_out(127), B => data_f3_out(127), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1720); - - \data_temp_RNO_0[100]\ : MX2C - port map(A => \data_temp[100]_net_1\, B => - \data_selected[132]\, S => \state[4]_net_1\, Y => N_701); - - \data_temp_RNO[13]\ : NOR2A - port map(A => \data_temp[45]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[13]\); - - \data_valid_and_ready[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready[0]_net_1\); - - \data_temp_RNO_3[97]\ : MX2C - port map(A => data_f0_out(129), B => data_f1_out(129), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_785); - - \data[19]\ : DFN1C0 - port map(D => \data_5[19]\, CLK => lclk_c, CLR => rstn, Q - => wdata(19)); - - \data_temp_RNO_0[84]\ : MX2C - port map(A => \data_temp[116]_net_1\, B => - \data_selected[116]\, S => \state[4]_net_1\, Y => N_685); - - \time_wen[2]\ : DFN1E0P0 - port map(D => N_859, CLK => lclk_c, PRE => rstn, E => N_928, - Q => time_wen(2)); - - \data_temp[118]\ : DFN1C0 - port map(D => \data_temp_5[118]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[118]_net_1\); - - \data_temp_RNO[109]\ : NOR2 - port map(A => N_863, B => N_710, Y => \data_temp_5[109]\); - - \data_temp_RNO_2[94]\ : MX2C - port map(A => data_f2_out(126), B => data_f3_out(126), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1719); - - \data_temp_RNO_1[79]\ : MX2C - port map(A => N_1732, B => N_809, S => N_1580_1, Y => - \data_selected[111]\); - - \data_temp_RNO_1[71]\ : MX2C - port map(A => N_740, B => N_815, S => N_1580_2, Y => - \data_selected[103]\); - - \data_temp[105]\ : DFN1C0 - port map(D => \data_temp_5[105]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[105]_net_1\); - - \data_temp[42]\ : DFN1C0 - port map(D => N_237, CLK => lclk_c, CLR => rstn, Q => - \data_temp[42]_net_1\); - - \data_temp_RNO_0[65]\ : MX2C - port map(A => \data_temp[97]_net_1\, B => - \data_selected[97]\, S => \state[4]_net_1\, Y => N_666); - - \data_temp_RNO[103]\ : NOR2 - port map(A => N_863_2, B => N_704, Y => \data_temp_5[103]\); - - \data_temp_RNO_3[102]\ : MX2C - port map(A => data_f0_out(134), B => data_f1_out(134), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_790); - - \data_temp_RNO_0[114]\ : MX2C - port map(A => \data_temp[114]_net_1\, B => - \data_selected[146]\, S => \state[4]_net_1\, Y => N_715); - - \data[15]\ : DFN1C0 - port map(D => \data_5[15]\, CLK => lclk_c, CLR => rstn, Q - => wdata(15)); - - \data_temp_RNO_0[111]\ : MX2C - port map(A => \data_temp[111]_net_1\, B => - \data_selected[143]\, S => \state[4]_net_1\, Y => N_712); - - \data_RNO[26]\ : NOR2A - port map(A => \data_temp[26]_net_1\, B => \state[4]_net_1\, - Y => \data_5[26]\); - - \data_temp[1]\ : DFN1C0 - port map(D => \data_temp_5[1]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[1]_net_1\); - - \data_temp_RNO_1[66]\ : MX2C - port map(A => N_735, B => N_824, S => N_1580, Y => - \data_selected[98]\); - - \data_temp_RNO_1[89]\ : MX2C - port map(A => N_1728, B => N_805, S => N_1580, Y => - \data_selected[121]\); - - \data_temp_RNO_1[81]\ : MX2C - port map(A => N_1734, B => N_811, S => N_1580_1, Y => - \data_selected[113]\); - - \data_temp_RNO_0[64]\ : MX2C - port map(A => \data_temp[96]_net_1\, B => - \data_selected[96]\, S => \state[4]_net_1\, Y => N_665); - - \data_temp_RNO_0[96]\ : MX2C - port map(A => \data_temp[96]_net_1\, B => - \data_selected[128]\, S => \state[4]_net_1\, Y => N_697); - - \data_temp_RNO_1[58]\ : MX2C - port map(A => N_741, B => N_830, S => N_1580_1, Y => - \data_selected[90]\); - - \data_temp_RNO_1[99]\ : MX2C - port map(A => N_1724, B => N_787, S => N_1580, Y => - \data_selected[131]\); - - \data_temp_RNO_1[91]\ : NOR2 - port map(A => N_912_i, B => N_793, Y => N_907); - - \data_temp_RNO_1[63]\ : MX2C - port map(A => N_746, B => N_821, S => N_1580_1, Y => - \data_selected[95]\); - - \data_temp_RNO_3[106]\ : MX2C - port map(A => data_f0_out(138), B => data_f1_out(138), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_780); - - \data_temp_RNO[28]\ : NOR2A - port map(A => \data_temp[60]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[28]\); - - \data_temp_RNO_1[32]\ : NOR2 - port map(A => N_1685, B => N_911, Y => N_865); - - \data_temp[41]\ : DFN1C0 - port map(D => N_235, CLK => lclk_c, CLR => rstn, Q => - \data_temp[41]_net_1\); - - \data_temp_RNO_2[78]\ : MX2C - port map(A => data_f2_out(110), B => data_f3_out(110), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_733); - - \data_temp_RNO_0[93]\ : NOR2 - port map(A => N_1718, B => N_911, Y => N_902); - - \data_temp_RNO_0[50]\ : MX2C - port map(A => \data_temp[82]_net_1\, B => - \data_selected[82]\, S => \state[4]_net_1\, Y => N_651); - - \data_temp_RNO[97]\ : NOR2 - port map(A => N_863, B => N_698, Y => \data_temp_5[97]\); - - \data_temp_RNO_0[47]\ : MX2C - port map(A => \data_temp[79]_net_1\, B => - \data_selected[79]\, S => \state[4]_net_1\, Y => N_648); - - \data_RNO[14]\ : NOR2A - port map(A => \data_temp[14]_net_1\, B => \state[4]_net_1\, - Y => \data_5[14]\); - - \data_temp_RNO_3[40]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[72]_net_1\, - Y => N_1662); - - \data_temp[23]\ : DFN1C0 - port map(D => \data_temp_5[23]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[23]_net_1\); - - \data_temp_RNO_3[121]\ : MX2C - port map(A => data_f0_out(153), B => data_f1_out(153), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1678); - - \data_temp_RNO_2[37]\ : MX2 - port map(A => data_f0_out(69), B => data_f1_out(69), S => - \data_valid_and_ready[0]_net_1\, Y => N_851); - - \data_temp[19]\ : DFN1C0 - port map(D => \data_temp_5[19]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[19]_net_1\); - - \data_temp_RNO_2[48]\ : MX2C - port map(A => data_f2_out(80), B => data_f3_out(80), S => - \data_valid_and_ready[2]_net_1\, Y => N_759); - - \data_temp_RNO_1[75]\ : MX2C - port map(A => N_730, B => N_819, S => N_1580_1, Y => - \data_selected[107]\); - - \data_valid_and_ready_0[0]\ : OR2A - port map(A => valid_out_0, B => ready_i_0_0, Y => - \data_valid_and_ready_0[0]_net_1\); - - \data_temp_RNO[23]\ : NOR2A - port map(A => \data_temp[55]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[23]\); - - \data_RNO[10]\ : NOR2A - port map(A => \data_temp[10]_net_1\, B => \state[4]_net_1\, - Y => \data_5[10]\); - - \data_temp[60]\ : DFN1C0 - port map(D => \data_temp_5[60]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[60]_net_1\); - - \state_RNIT8OCE2_1[4]\ : NOR2 - port map(A => \data_temp_5_i_a2_0_0[32]_net_1\, B => N_911, - Y => N_863_2); - - \data_temp[53]\ : DFN1C0 - port map(D => \data_temp_5[53]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[53]_net_1\); - - \data_valid_and_ready_3[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready_3[2]_net_1\); - - \data_temp_RNO_3[76]\ : MX2C - port map(A => data_f0_out(108), B => data_f1_out(108), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_806); - - \data_temp_RNO_1[74]\ : MX2C - port map(A => N_729, B => N_818, S => N_1580_1, Y => - \data_selected[106]\); - - \data_temp_RNO_1[85]\ : MX2C - port map(A => N_1738, B => N_801, S => N_1580_2, Y => - \data_selected[117]\); - - \data_wen_RNO[3]\ : OR2 - port map(A => \time_en_temp[3]_net_1\, B => - \state[4]_net_1\, Y => \data_wen_3[3]\); - - \data_temp_RNO_1[103]\ : MX2C - port map(A => N_1714, B => N_791, S => N_1580_2, Y => - \data_selected[135]\); - - \data_RNO[8]\ : NOR2A - port map(A => \data_temp[8]_net_1\, B => \state[4]_net_1\, - Y => \data_5[8]\); - - \data_temp_RNO_0[113]\ : MX2C - port map(A => \data_temp[113]_net_1\, B => - \data_selected[145]\, S => \state[4]_net_1\, Y => N_714); - - \data_temp_RNO_0[76]\ : MX2C - port map(A => \data_temp[108]_net_1\, B => - \data_selected[108]\, S => \state[4]_net_1\, Y => N_677); - - \data_temp_RNO[69]\ : NOR2 - port map(A => N_863_2, B => N_670, Y => \data_temp_5[69]\); - - \data_temp_RNO_2[102]\ : MX2C - port map(A => data_f2_out(134), B => data_f3_out(134), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1713); - - \data_temp_RNO_0[52]\ : MX2C - port map(A => \data_temp[84]_net_1\, B => - \data_selected[84]\, S => \state[4]_net_1\, Y => N_653); - - \data_temp_RNO_1[125]\ : NOR2 - port map(A => N_1682, B => N_912_i, Y => N_905); - - \data_RNO[9]\ : NOR2A - port map(A => \data_temp[9]_net_1\, B => \state[4]_net_1\, - Y => \data_5[9]\); - - \data_temp_RNO_2[105]\ : MX2C - port map(A => data_f2_out(137), B => data_f3_out(137), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1716); - - \data_temp_RNO_3[42]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[74]_net_1\, - Y => N_1668); - - \data_temp_RNO_1[111]\ : MX2C - port map(A => N_1708, B => N_771, S => N_1580_1, Y => - \data_selected[143]\); - - \data_valid_ack[1]\ : DFN1E0C0 - port map(D => N_857, CLK => lclk_c, CLR => rstn, E => N_929, - Q => valid_ack(1)); - - \data_temp_RNO_3[73]\ : MX2C - port map(A => data_f0_out(105), B => data_f1_out(105), S - => \data_valid_and_ready_3[0]_net_1\, Y => N_817); - - \data_temp_RNO_1[84]\ : MX2C - port map(A => N_1737, B => N_800, S => N_1580_2, Y => - \data_selected[116]\); - - \data_temp_RNO_1[95]\ : MX2C - port map(A => N_1720, B => N_797, S => N_1580_0, Y => - \data_selected[127]\); - - \data_temp_RNO_1[40]\ : NOR2 - port map(A => N_911, B => N_765, Y => N_1663); - - \data_temp[48]\ : DFN1C0 - port map(D => \data_temp_5[48]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[48]_net_1\); - - \data_temp_RNO[50]\ : NOR2 - port map(A => N_863_1, B => N_651, Y => \data_temp_5[50]\); - - \data_temp[86]\ : DFN1C0 - port map(D => \data_temp_5[86]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[86]_net_1\); - - \data_temp_RNO[3]\ : NOR2A - port map(A => \data_temp[35]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[3]\); - - \data_temp_RNO_3[59]\ : MX2C - port map(A => data_f0_out(91), B => data_f1_out(91), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_831); - - \data_temp_RNO_3[51]\ : MX2C - port map(A => data_f0_out(83), B => data_f1_out(83), S => - \data_valid_and_ready[0]_net_1\, Y => N_837); - - \data_temp_RNO[80]\ : NOR2 - port map(A => N_863_1, B => N_681, Y => \data_temp_5[80]\); - - \data_temp_RNO_3[125]\ : MX2 - port map(A => data_f0_out(157), B => data_f1_out(157), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1682); - - \data_temp_RNO_3[69]\ : MX2C - port map(A => data_f0_out(101), B => data_f1_out(101), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_813); - - \data_temp_RNO_3[61]\ : MX2C - port map(A => data_f0_out(93), B => data_f1_out(93), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_833); - - \data_temp_RNO_0[73]\ : MX2C - port map(A => \data_temp[105]_net_1\, B => - \data_selected[105]\, S => \state[4]_net_1\, Y => N_674); - - \data_RNO[15]\ : NOR2A - port map(A => \data_temp[15]_net_1\, B => \state[4]_net_1\, - Y => \data_5[15]\); - - \data_temp_RNO_3[89]\ : MX2C - port map(A => data_f0_out(121), B => data_f1_out(121), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_805); - - \data_temp_RNO_3[81]\ : MX2C - port map(A => data_f0_out(113), B => data_f1_out(113), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_811); - - \data_temp_RNO[66]\ : NOR2 - port map(A => N_863, B => N_667, Y => \data_temp_5[66]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \data_temp_RNO_3[109]\ : MX2C - port map(A => data_f0_out(141), B => data_f1_out(141), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_783); - - \data_temp[116]\ : DFN1C0 - port map(D => \data_temp_5[116]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[116]_net_1\); - - \data_temp_RNO_1[94]\ : MX2C - port map(A => N_1719, B => N_796, S => N_1580_0, Y => - \data_selected[126]\); - - \data_temp_RNO[11]\ : NOR2A - port map(A => \data_temp[43]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[11]\); - - \data_temp_RNO_1[126]\ : MX2C - port map(A => N_1695, B => N_1683, S => N_1580_0, Y => - \data_selected[158]\); - - \state_RNIT8OCE2_2[4]\ : NOR2 - port map(A => \data_temp_5_i_a2_0_0[32]_net_1\, B => N_911, - Y => N_863_1); - - \data_temp_RNO_4[36]\ : MX2 - port map(A => data_f2_out(68), B => data_f3_out(68), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1689); - - \data_RNO[29]\ : NOR2A - port map(A => \data_temp[29]_net_1\, B => \state[4]_net_1\, - Y => \data_5[29]\); - - \state[3]\ : DFN1C0 - port map(D => state_0_sqmuxa_i, CLK => lclk_c, CLR => rstn, - Q => \state[3]_net_1\); - - \data_temp_RNO[12]\ : NOR2A - port map(A => \data_temp[44]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[12]\); - - \data_temp[47]\ : DFN1C0 - port map(D => \data_temp_5[47]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[47]_net_1\); - - \data_valid_ack_RNO[2]\ : INV - port map(A => N_859, Y => N_859_i); - - \data_RNO[30]\ : NOR2A - port map(A => \data_temp[30]_net_1\, B => \state[4]_net_1\, - Y => \data_5[30]\); - - \data_temp_RNO_4[33]\ : MX2 - port map(A => data_f2_out(65), B => data_f3_out(65), S => - \data_valid_and_ready_0[2]_net_1\, Y => N_1686); - - \data_temp_RNO_3[90]\ : MX2C - port map(A => data_f0_out(122), B => data_f1_out(122), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_792); - - \data_temp_RNO_1[42]\ : NOR2 - port map(A => N_911, B => N_767, Y => N_1669); - - \state_RNIT8OCE2_3[4]\ : NOR2 - port map(A => \data_temp_5_i_a2_0_0[32]_net_1\, B => N_911, - Y => N_863_0); - - \data_temp_RNO_2[121]\ : MX2C - port map(A => data_f2_out(153), B => data_f3_out(153), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1690); - - \data_temp[33]\ : DFN1C0 - port map(D => N_219, CLK => lclk_c, CLR => rstn, Q => - \data_temp[33]_net_1\); - - \data_temp[20]\ : DFN1C0 - port map(D => \data_temp_5[20]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[20]_net_1\); - - \data_temp_RNO_2[106]\ : MX2C - port map(A => data_f2_out(138), B => data_f3_out(138), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1717); - - \data[24]\ : DFN1C0 - port map(D => \data_5[24]\, CLK => lclk_c, CLR => rstn, Q - => wdata(24)); - - \data_temp_RNO[95]\ : NOR2 - port map(A => N_863_0, B => N_696, Y => \data_temp_5[95]\); - - \data_temp_RNO[14]\ : NOR2A - port map(A => \data_temp[46]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[14]\); - - \data_temp_RNO_2[89]\ : MX2C - port map(A => data_f2_out(121), B => data_f3_out(121), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1728); - - \data_temp_RNO_2[81]\ : MX2C - port map(A => data_f2_out(113), B => data_f3_out(113), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1734); - - \data_temp_RNO_3[39]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[71]_net_1\, - Y => N_1659); - - \data_temp[50]\ : DFN1C0 - port map(D => \data_temp_5[50]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[50]_net_1\); - - \data_temp_RNO_3[55]\ : MX2C - port map(A => data_f0_out(87), B => data_f1_out(87), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_827); - - \data_temp_RNO_0[86]\ : MX2C - port map(A => \data_temp[118]_net_1\, B => - \data_selected[118]\, S => \state[4]_net_1\, Y => N_687); - - \data[1]\ : DFN1C0 - port map(D => \data_5[1]\, CLK => lclk_c, CLR => rstn, Q - => wdata(1)); - - \data_valid_and_ready_2[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready_2[2]_net_1\); - - \data_temp_RNO_3[65]\ : MX2C - port map(A => data_f0_out(97), B => data_f1_out(97), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_823); - - VCC_i : VCC - port map(Y => \VCC\); - - \data_valid_and_ready[1]\ : NOR2 - port map(A => valid_out_i(1), B => ready_i_0_i_0(1), Y => - \data_valid_and_ready[1]_net_1\); - - \data_temp_RNO_3[85]\ : MX2C - port map(A => data_f0_out(117), B => data_f1_out(117), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_801); - - \state_RNO[4]\ : OA1B - port map(A => N_1306, B => \state[0]_net_1\, C => - \state_ns_i_i_a2_1[0]\, Y => N_861); - - \data_temp_RNO_2[96]\ : MX2C - port map(A => data_f2_out(128), B => data_f3_out(128), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1721); - - \data[9]\ : DFN1C0 - port map(D => \data_5[9]\, CLK => lclk_c, CLR => rstn, Q - => wdata(9)); - - \data_temp_RNO_3[123]\ : MX2 - port map(A => data_f0_out(155), B => data_f1_out(155), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1680); - - \data_valid_and_ready[2]\ : OR2A - port map(A => valid_out_2, B => ready_i_0_2, Y => - \data_valid_and_ready[2]_net_1\); - - \data_temp_RNO_3[54]\ : MX2C - port map(A => data_f0_out(86), B => data_f1_out(86), S => - \data_valid_and_ready[0]_net_1\, Y => N_840); - - \data_temp_RNO_1[124]\ : NOR2 - port map(A => N_1681, B => N_912_i, Y => N_903); - - \data_temp_RNO_3[92]\ : MX2 - port map(A => data_f0_out(124), B => data_f1_out(124), S - => \data_valid_and_ready_1[0]_net_1\, Y => N_794); - - \data_temp_RNO_3[64]\ : MX2C - port map(A => data_f0_out(96), B => data_f1_out(96), S => - \data_valid_and_ready_3[0]_net_1\, Y => N_822); - - \data_temp_RNO_1[57]\ : MX2C - port map(A => N_754, B => N_829, S => N_1580_1, Y => - \data_selected[89]\); - - \data_temp_RNO_2[69]\ : MX2C - port map(A => data_f2_out(101), B => data_f3_out(101), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_738); - - \data_temp_RNO_2[61]\ : MX2C - port map(A => data_f2_out(93), B => data_f3_out(93), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_744); - - \data[17]\ : DFN1C0 - port map(D => \data_5[17]\, CLK => lclk_c, CLR => rstn, Q - => wdata(17)); - - \data_temp_RNO_3[84]\ : MX2C - port map(A => data_f0_out(116), B => data_f1_out(116), S - => \data_valid_and_ready_2[0]_net_1\, Y => N_800); - - \data_temp_RNITP6OE2[123]\ : AO1D - port map(A => \state[4]_net_1\, B => \data_temp[123]_net_1\, - C => N_863_0, Y => N_1581); - - \data_temp_RNO_0[83]\ : MX2C - port map(A => \data_temp[115]_net_1\, B => - \data_selected[115]\, S => \state[4]_net_1\, Y => N_684); - - \data_temp_RNIUP6OE2[124]\ : AO1D - port map(A => \state[4]_net_1\, B => \data_temp[124]_net_1\, - C => N_863_0, Y => N_1583); - - \data_temp_RNO_2[58]\ : MX2C - port map(A => data_f2_out(90), B => data_f3_out(90), S => - \data_valid_and_ready_3[2]_net_1\, Y => N_741); - - \data[20]\ : DFN1C0 - port map(D => \data_5[20]\, CLK => lclk_c, CLR => rstn, Q - => wdata(20)); - - \data_temp_RNO_2[93]\ : MX2 - port map(A => data_f2_out(125), B => data_f3_out(125), S - => \data_valid_and_ready_1[2]_net_1\, Y => N_1718); - - \data_RNO[6]\ : NOR2A - port map(A => \data_temp[6]_net_1\, B => \state[4]_net_1\, - Y => \data_5[6]\); - - \data_RNO[3]\ : NOR2A - port map(A => \data_temp[3]_net_1\, B => \state[4]_net_1\, - Y => \data_5[3]\); - - \data_temp_RNO_2[77]\ : MX2C - port map(A => data_f2_out(109), B => data_f3_out(109), S - => \data_valid_and_ready_3[2]_net_1\, Y => N_732); - - \data_temp_RNO_0[66]\ : MX2C - port map(A => \data_temp[98]_net_1\, B => - \data_selected[98]\, S => \state[4]_net_1\, Y => N_667); - - \data_temp_RNO[21]\ : NOR2A - port map(A => \data_temp[53]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[21]\); - - \data_wen[0]\ : DFN1E0P0 - port map(D => \data_wen_3[0]\, CLK => lclk_c, PRE => rstn, - E => N_928, Q => data_wen(0)); - - \data_temp_RNO_0[104]\ : MX2C - port map(A => \data_temp[104]_net_1\, B => - \data_selected[136]\, S => \state[4]_net_1\, Y => N_705); - - \data_temp_RNO_4[40]\ : MX2 - port map(A => data_f2_out(72), B => data_f3_out(72), S => - \data_valid_and_ready[2]_net_1\, Y => N_765); - - \data_temp_RNO_2[47]\ : MX2C - port map(A => data_f2_out(79), B => data_f3_out(79), S => - \data_valid_and_ready[2]_net_1\, Y => N_758); - - \data_temp_RNO_0[101]\ : MX2C - port map(A => \data_temp[101]_net_1\, B => - \data_selected[133]\, S => \state[4]_net_1\, Y => N_702); - - \data_temp_RNO_0[40]\ : AO1D - port map(A => N_912_i, B => N_854, C => N_1662, Y => - \data_temp_5_i_0[40]\); - - \data_temp_RNO_0[38]\ : AO1D - port map(A => N_912_i, B => N_852, C => N_1656, Y => - \data_temp_5_i_0[38]\); - - \data_temp_RNO[67]\ : NOR2 - port map(A => N_863, B => N_668, Y => \data_temp_5[67]\); - - \data_temp_RNO[22]\ : NOR2A - port map(A => \data_temp[54]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[22]\); - - \data_temp_RNO[79]\ : NOR2 - port map(A => N_863_1, B => N_680, Y => \data_temp_5[79]\); - - \data_temp[66]\ : DFN1C0 - port map(D => \data_temp_5[66]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[66]_net_1\); - - \data_temp_RNO_2[85]\ : MX2C - port map(A => data_f2_out(117), B => data_f3_out(117), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1738); - - \data_temp_RNO_2[123]\ : MX2 - port map(A => data_f2_out(155), B => data_f3_out(155), S - => \data_valid_and_ready_0[2]_net_1\, Y => N_1692); - - \data_temp_RNO_0[63]\ : MX2C - port map(A => \data_temp[95]_net_1\, B => - \data_selected[95]\, S => \state[4]_net_1\, Y => N_664); - - \data_temp_RNO_3[35]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[67]_net_1\, - Y => N_873); - - \data_temp[84]\ : DFN1C0 - port map(D => \data_temp_5[84]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[84]_net_1\); - - \data_temp[45]\ : DFN1C0 - port map(D => \data_temp_5[45]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[45]_net_1\); - - \data_valid_ack[2]\ : DFN1E0C0 - port map(D => N_859_i, CLK => lclk_c, CLR => rstn, E => - N_929, Q => valid_ack(2)); - - \data_temp[73]\ : DFN1C0 - port map(D => \data_temp_5[73]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[73]_net_1\); - - \data_temp_RNO_3[118]\ : MX2C - port map(A => data_f0_out(150), B => data_f1_out(150), S - => \data_valid_and_ready_0[0]_net_1\, Y => N_1675); - - \data_temp_RNO_2[84]\ : MX2C - port map(A => data_f2_out(116), B => data_f3_out(116), S - => \data_valid_and_ready_2[2]_net_1\, Y => N_1737); - - \data_temp_RNO[76]\ : NOR2 - port map(A => N_863_1, B => N_677, Y => \data_temp_5[76]\); - - \data_temp_RNO_3[34]\ : NOR2 - port map(A => \state[4]_net_1\, B => \data_temp[66]_net_1\, - Y => N_870); - - \data_temp[113]\ : DFN1C0 - port map(D => \data_temp_5[113]\, CLK => lclk_c, CLR => - rstn, Q => \data_temp[113]_net_1\); - - \data_temp_RNO[24]\ : NOR2A - port map(A => \data_temp[56]_net_1\, B => \state[4]_net_1\, - Y => \data_temp_5[24]\); - - \data_temp[30]\ : DFN1C0 - port map(D => \data_temp_5[30]\, CLK => lclk_c, CLR => rstn, - Q => \data_temp[30]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_waveform is - - port( status_full_ack : in std_logic_vector(3 downto 0); - hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - iosn_1 : in std_logic_vector(93 to 93); - nhmaster_1_i : in std_logic_vector(0 to 0); - hsize : out std_logic_vector(1 downto 0); - hmaster_0 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - hgrant : in std_logic_vector(3 to 3); - iosn_0 : in std_logic_vector(93 to 93); - bco_msb_1_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - l1_0_m : in std_logic_vector(1 to 1); - nb_burst_available : in std_logic_vector(10 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - status_full : out std_logic_vector(3 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - hwdata : out std_logic_vector(31 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - sample_f3_wdata : in std_logic_vector(95 downto 0); - sample_f2_wdata : in std_logic_vector(95 downto 0); - sample_f1_15 : in std_logic; - sample_f1_47 : in std_logic; - sample_f1_14 : in std_logic; - sample_f1_46 : in std_logic; - sample_f1_13 : in std_logic; - sample_f1_45 : in std_logic; - sample_f1_12 : in std_logic; - sample_f1_44 : in std_logic; - sample_f1_60 : in std_logic; - sample_f1_59 : in std_logic; - sample_f1_58 : in std_logic; - sample_f1_57 : in std_logic; - sample_f1_56 : in std_logic; - sample_f1_55 : in std_logic; - sample_f1_54 : in std_logic; - sample_f1_53 : in std_logic; - sample_f1_52 : in std_logic; - sample_f1_51 : in std_logic; - sample_f1_50 : in std_logic; - sample_f1_49 : in std_logic; - sample_f1_48 : in std_logic; - sample_f1_4 : in std_logic; - sample_f1_36 : in std_logic; - sample_f1_3 : in std_logic; - sample_f1_35 : in std_logic; - sample_f1_2 : in std_logic; - sample_f1_34 : in std_logic; - sample_f1_1 : in std_logic; - sample_f1_33 : in std_logic; - sample_f1_0 : in std_logic; - sample_f1_32 : in std_logic; - sample_f1_63 : in std_logic; - sample_f1_62 : in std_logic; - sample_f1_61 : in std_logic; - sample_f1_11 : in std_logic; - sample_f1_43 : in std_logic; - sample_f1_10 : in std_logic; - sample_f1_42 : in std_logic; - sample_f1_9 : in std_logic; - sample_f1_41 : in std_logic; - sample_f1_8 : in std_logic; - sample_f1_40 : in std_logic; - sample_f1_7 : in std_logic; - sample_f1_39 : in std_logic; - sample_f1_6 : in std_logic; - sample_f1_38 : in std_logic; - sample_f1_5 : in std_logic; - sample_f1_37 : in std_logic; - sample_f1_wdata_0 : in std_logic; - sample_f1_wdata_1 : in std_logic; - sample_f1_wdata_2 : in std_logic; - sample_f1_wdata_3 : in std_logic; - sample_f1_wdata_4 : in std_logic; - sample_f1_wdata_5 : in std_logic; - sample_f1_wdata_6 : in std_logic; - sample_f1_wdata_7 : in std_logic; - sample_f1_wdata_8 : in std_logic; - sample_f1_wdata_9 : in std_logic; - sample_f1_wdata_10 : in std_logic; - sample_f1_wdata_11 : in std_logic; - sample_f1_wdata_12 : in std_logic; - sample_f1_wdata_13 : in std_logic; - sample_f1_wdata_14 : in std_logic; - sample_f1_wdata_15 : in std_logic; - sample_f1_wdata_48 : in std_logic; - sample_f1_wdata_49 : in std_logic; - sample_f1_wdata_50 : in std_logic; - sample_f1_wdata_51 : in std_logic; - sample_f1_wdata_52 : in std_logic; - sample_f1_wdata_53 : in std_logic; - sample_f1_wdata_54 : in std_logic; - sample_f1_wdata_55 : in std_logic; - sample_f1_wdata_56 : in std_logic; - sample_f1_wdata_57 : in std_logic; - sample_f1_wdata_58 : in std_logic; - sample_f1_wdata_59 : in std_logic; - sample_f1_wdata_60 : in std_logic; - sample_f1_wdata_61 : in std_logic; - sample_f1_wdata_62 : in std_logic; - sample_f1_wdata_63 : in std_logic; - sample_f1_wdata_64 : in std_logic; - sample_f1_wdata_65 : in std_logic; - sample_f1_wdata_66 : in std_logic; - sample_f1_wdata_67 : in std_logic; - sample_f1_wdata_68 : in std_logic; - sample_f1_wdata_69 : in std_logic; - sample_f1_wdata_70 : in std_logic; - sample_f1_wdata_71 : in std_logic; - sample_f1_wdata_72 : in std_logic; - sample_f1_wdata_73 : in std_logic; - sample_f1_wdata_74 : in std_logic; - sample_f1_wdata_75 : in std_logic; - sample_f1_wdata_76 : in std_logic; - sample_f1_wdata_77 : in std_logic; - sample_f1_wdata_78 : in std_logic; - sample_f1_wdata_79 : in std_logic; - sample_f1_wdata_80 : in std_logic; - sample_f1_wdata_81 : in std_logic; - sample_f1_wdata_82 : in std_logic; - sample_f1_wdata_83 : in std_logic; - sample_f1_wdata_84 : in std_logic; - sample_f1_wdata_85 : in std_logic; - sample_f1_wdata_86 : in std_logic; - sample_f1_wdata_87 : in std_logic; - sample_f1_wdata_88 : in std_logic; - sample_f1_wdata_89 : in std_logic; - sample_f1_wdata_90 : in std_logic; - sample_f1_wdata_91 : in std_logic; - sample_f1_wdata_92 : in std_logic; - sample_f1_wdata_93 : in std_logic; - sample_f1_wdata_94 : in std_logic; - sample_f1_wdata_95 : in std_logic; - sample_f0_15 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_0 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_63 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_37 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_95 : in std_logic; - coarse_time : in std_logic_vector(0 to 0); - delta_snapshot : in std_logic_vector(15 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - coarse_time_i : in std_logic_vector(0 to 0); - nb_snapshot_param : in std_logic_vector(10 downto 0); - IdlePhase : out std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - arb_1 : in std_logic; - hbusreq_i_3 : out std_logic; - Lock_RNIU86D : out std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - m19_0_N_15_i_0_li : in std_logic; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - m26_m1_e : out std_logic; - sample_f3_val : in std_logic; - enable_f3 : in std_logic; - burst_f2 : in std_logic; - enable_f2 : in std_logic; - sample_f1_val_0 : in std_logic; - burst_f1 : in std_logic; - enable_f1 : in std_logic; - data_shaping_R1_0 : in std_logic; - data_shaping_R1 : in std_logic; - burst_f0 : in std_logic; - enable_f0 : in std_logic; - data_shaping_R0_0 : in std_logic; - data_shaping_R0 : in std_logic; - lclk_c : in std_logic; - rstn : in std_logic; - sample_f0_val_0 : in std_logic; - sample_f2_val : in std_logic - ); - -end lpp_waveform; - -architecture DEF_ARCH of lpp_waveform is - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform_snapshot_160_12 - port( sample_f1_wdata_95 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - data_f1_out : out std_logic_vector(159 downto 64); - sample_f1_37 : in std_logic := 'U'; - sample_f1_5 : in std_logic := 'U'; - sample_f1_38 : in std_logic := 'U'; - sample_f1_6 : in std_logic := 'U'; - sample_f1_39 : in std_logic := 'U'; - sample_f1_7 : in std_logic := 'U'; - sample_f1_40 : in std_logic := 'U'; - sample_f1_8 : in std_logic := 'U'; - sample_f1_41 : in std_logic := 'U'; - sample_f1_9 : in std_logic := 'U'; - sample_f1_42 : in std_logic := 'U'; - sample_f1_10 : in std_logic := 'U'; - sample_f1_43 : in std_logic := 'U'; - sample_f1_11 : in std_logic := 'U'; - sample_f1_61 : in std_logic := 'U'; - sample_f1_62 : in std_logic := 'U'; - sample_f1_63 : in std_logic := 'U'; - sample_f1_32 : in std_logic := 'U'; - sample_f1_0 : in std_logic := 'U'; - sample_f1_33 : in std_logic := 'U'; - sample_f1_1 : in std_logic := 'U'; - sample_f1_34 : in std_logic := 'U'; - sample_f1_2 : in std_logic := 'U'; - sample_f1_35 : in std_logic := 'U'; - sample_f1_3 : in std_logic := 'U'; - sample_f1_36 : in std_logic := 'U'; - sample_f1_4 : in std_logic := 'U'; - sample_f1_48 : in std_logic := 'U'; - sample_f1_49 : in std_logic := 'U'; - sample_f1_50 : in std_logic := 'U'; - sample_f1_51 : in std_logic := 'U'; - sample_f1_52 : in std_logic := 'U'; - sample_f1_53 : in std_logic := 'U'; - sample_f1_54 : in std_logic := 'U'; - sample_f1_55 : in std_logic := 'U'; - sample_f1_56 : in std_logic := 'U'; - sample_f1_57 : in std_logic := 'U'; - sample_f1_58 : in std_logic := 'U'; - sample_f1_59 : in std_logic := 'U'; - sample_f1_60 : in std_logic := 'U'; - sample_f1_44 : in std_logic := 'U'; - sample_f1_12 : in std_logic := 'U'; - sample_f1_45 : in std_logic := 'U'; - sample_f1_13 : in std_logic := 'U'; - sample_f1_46 : in std_logic := 'U'; - sample_f1_14 : in std_logic := 'U'; - sample_f1_47 : in std_logic := 'U'; - sample_f1_15 : in std_logic := 'U'; - nb_snapshot_param : in std_logic_vector(0 to 0) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f1_out_valid : out std_logic; - data_shaping_R1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - I_9_31 : in std_logic := 'U'; - I_45_11 : in std_logic := 'U'; - I_52_11 : in std_logic := 'U'; - I_56_12 : in std_logic := 'U'; - I_24_16 : in std_logic := 'U'; - N_4 : in std_logic := 'U'; - I_20_23 : in std_logic := 'U'; - I_13_35 : in std_logic := 'U'; - I_38_12 : in std_logic := 'U'; - I_31_15 : in std_logic := 'U'; - I_5_31 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U'; - start_snapshot_f1 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_controler - port( coarse_time_i : in std_logic_vector(0 to 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - coarse_time : in std_logic_vector(0 to 0) := (others => 'U'); - start_snapshot_f2 : out std_logic; - start_snapshot_f1 : out std_logic; - start_snapshot_f0 : out std_logic; - sample_f2_val : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - port( status_new_err : out std_logic_vector(3 to 3); - valid_ack : in std_logic_vector(3 to 3) := (others => 'U'); - valid_out : out std_logic_vector(3 to 3); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f3_out_valid : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - port( status_new_err : out std_logic_vector(1 to 1); - valid_out_i : out std_logic_vector(1 to 1); - valid_ack : in std_logic_vector(1 to 1) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f1_out_valid : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_waveform_burst - port( sample_f3_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - data_f3_out : out std_logic_vector(159 downto 64); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f3_out_valid : out std_logic; - enable_f3 : in std_logic := 'U'; - sample_f3_val : in std_logic := 'U' - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - port( status_new_err : out std_logic_vector(2 to 2); - valid_ack : in std_logic_vector(2 to 2) := (others => 'U'); - valid_out : out std_logic_vector(2 to 2); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f2_out_valid : in std_logic := 'U' - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - port( status_new_err : out std_logic_vector(0 to 0); - valid_ack : in std_logic_vector(0 to 0) := (others => 'U'); - valid_out : out std_logic_vector(0 to 0); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f0_out_valid : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo - port( ready_i_0_i_0 : out std_logic_vector(1 to 1); - data_wen : in std_logic_vector(3 downto 0) := (others => 'U'); - data_ren : in std_logic_vector(3 downto 0) := (others => 'U'); - ready_i_0_2 : out std_logic; - ready_i_0_0 : out std_logic; - ready_i_0_3 : out std_logic; - time_ren : in std_logic_vector(3 downto 0) := (others => 'U'); - time_wen : in std_logic_vector(3 downto 0) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - wdata : in std_logic_vector(31 downto 0) := (others => 'U'); - time_ren_1z : in std_logic := 'U'; - data_ren_1z : in std_logic := 'U'; - un13_time_write : in std_logic := 'U'; - un20_time_write : in std_logic := 'U'; - un27_time_write : in std_logic := 'U'; - un5_time_write : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_160_11 - port( sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - data_f0_out : out std_logic_vector(159 downto 64); - sample_f0_37 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_0 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f0_out_valid : out std_logic; - data_shaping_R0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - start_snapshot_f0 : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_snapshot_160_12_1 - port( sample_f2_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - data_f2_out : out std_logic_vector(159 downto 64); - nb_snapshot_param : in std_logic_vector(0 to 0) := (others => 'U'); - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_f2_out_valid : out std_logic; - I_9_31 : in std_logic := 'U'; - I_45_11 : in std_logic := 'U'; - I_52_11 : in std_logic := 'U'; - I_38_12 : in std_logic := 'U'; - N_4 : in std_logic := 'U'; - I_56_12 : in std_logic := 'U'; - I_24_16 : in std_logic := 'U'; - I_5_31 : in std_logic := 'U'; - I_20_23 : in std_logic := 'U'; - I_13_35 : in std_logic := 'U'; - I_31_15 : in std_logic := 'U'; - start_snapshot_f2 : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U' - ); - end component; - - component lpp_waveform_dma - port( addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : out std_logic_vector(1 downto 0); - hburst : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - data_ren : out std_logic_vector(3 downto 0); - ready_i_0_i_0 : in std_logic_vector(1 to 1) := (others => 'U'); - ready_i_0_2 : in std_logic := 'U'; - ready_i_0_0 : in std_logic := 'U'; - ready_i_0_3 : in std_logic := 'U'; - time_ren : out std_logic_vector(3 downto 0); - time_ren_1z : out std_logic; - data_ren_1z : out std_logic; - m26_m1_e : out std_logic; - m19_a1_6_i_0 : out std_logic; - m19_a0_6_i_0 : out std_logic; - m19_0_N_15_i_0_li : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - Lock_RNIU86D : out std_logic; - hbusreq_i_3 : out std_logic; - arb_1 : in std_logic := 'U'; - un1_dmain_6 : out std_logic; - hwrite : out std_logic; - IdlePhase : out std_logic; - un13_time_write : out std_logic; - un5_time_write : out std_logic; - un27_time_write : out std_logic; - un20_time_write : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component lpp_waveform_fifo_arbiter - port( wdata : out std_logic_vector(31 downto 0); - data_wen : out std_logic_vector(3 downto 0); - valid_ack : out std_logic_vector(3 downto 0); - time_wen : out std_logic_vector(3 downto 0); - data_f3_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f2_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f1_out : in std_logic_vector(159 downto 64) := (others => 'U'); - data_f0_out : in std_logic_vector(159 downto 64) := (others => 'U'); - ready_i_0_i_0 : in std_logic_vector(1 to 1) := (others => 'U'); - valid_out_i : in std_logic_vector(1 to 1) := (others => 'U'); - ready_i_0_3 : in std_logic := 'U'; - ready_i_0_0 : in std_logic := 'U'; - ready_i_0_2 : in std_logic := 'U'; - valid_out_3 : in std_logic := 'U'; - valid_out_0 : in std_logic := 'U'; - valid_out_2 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal N_45, N_37, \DWACT_FINC_E[0]\, N_14, - \DWACT_FINC_E[4]\, N_4, \DWACT_FINC_E[6]\, - \DWACT_FINC_E[2]\, \DWACT_FINC_E[5]\, I_56_12, N_11, - I_52_11, \DWACT_FINC_E[3]\, I_45_11, N_19, I_38_12, N_24, - I_31_15, N_29, \DWACT_FINC_E[1]\, I_24_16, N_34, I_20_23, - I_13_35, N_42, I_9_31, I_5_31, start_snapshot_f2, - start_snapshot_f1, start_snapshot_f0, \data_f0_out[64]\, - \data_f0_out[65]\, \data_f0_out[66]\, \data_f0_out[67]\, - \data_f0_out[68]\, \data_f0_out[69]\, \data_f0_out[70]\, - \data_f0_out[71]\, \data_f0_out[72]\, \data_f0_out[73]\, - \data_f0_out[74]\, \data_f0_out[75]\, \data_f0_out[76]\, - \data_f0_out[77]\, \data_f0_out[78]\, \data_f0_out[79]\, - \data_f0_out[80]\, \data_f0_out[81]\, \data_f0_out[82]\, - \data_f0_out[83]\, \data_f0_out[84]\, \data_f0_out[85]\, - \data_f0_out[86]\, \data_f0_out[87]\, \data_f0_out[88]\, - \data_f0_out[89]\, \data_f0_out[90]\, \data_f0_out[91]\, - \data_f0_out[92]\, \data_f0_out[93]\, \data_f0_out[94]\, - \data_f0_out[95]\, \data_f0_out[96]\, \data_f0_out[97]\, - \data_f0_out[98]\, \data_f0_out[99]\, \data_f0_out[100]\, - \data_f0_out[101]\, \data_f0_out[102]\, - \data_f0_out[103]\, \data_f0_out[104]\, - \data_f0_out[105]\, \data_f0_out[106]\, - \data_f0_out[107]\, \data_f0_out[108]\, - \data_f0_out[109]\, \data_f0_out[110]\, - \data_f0_out[111]\, \data_f0_out[112]\, - \data_f0_out[113]\, \data_f0_out[114]\, - \data_f0_out[115]\, \data_f0_out[116]\, - \data_f0_out[117]\, \data_f0_out[118]\, - \data_f0_out[119]\, \data_f0_out[120]\, - \data_f0_out[121]\, \data_f0_out[122]\, - \data_f0_out[123]\, \data_f0_out[124]\, - \data_f0_out[125]\, \data_f0_out[126]\, - \data_f0_out[127]\, \data_f0_out[128]\, - \data_f0_out[129]\, \data_f0_out[130]\, - \data_f0_out[131]\, \data_f0_out[132]\, - \data_f0_out[133]\, \data_f0_out[134]\, - \data_f0_out[135]\, \data_f0_out[136]\, - \data_f0_out[137]\, \data_f0_out[138]\, - \data_f0_out[139]\, \data_f0_out[140]\, - \data_f0_out[141]\, \data_f0_out[142]\, - \data_f0_out[143]\, \data_f0_out[144]\, - \data_f0_out[145]\, \data_f0_out[146]\, - \data_f0_out[147]\, \data_f0_out[148]\, - \data_f0_out[149]\, \data_f0_out[150]\, - \data_f0_out[151]\, \data_f0_out[152]\, - \data_f0_out[153]\, \data_f0_out[154]\, - \data_f0_out[155]\, \data_f0_out[156]\, - \data_f0_out[157]\, \data_f0_out[158]\, - \data_f0_out[159]\, data_f0_out_valid, \data_f1_out[64]\, - \data_f1_out[65]\, \data_f1_out[66]\, \data_f1_out[67]\, - \data_f1_out[68]\, \data_f1_out[69]\, \data_f1_out[70]\, - \data_f1_out[71]\, \data_f1_out[72]\, \data_f1_out[73]\, - \data_f1_out[74]\, \data_f1_out[75]\, \data_f1_out[76]\, - \data_f1_out[77]\, \data_f1_out[78]\, \data_f1_out[79]\, - \data_f1_out[80]\, \data_f1_out[81]\, \data_f1_out[82]\, - \data_f1_out[83]\, \data_f1_out[84]\, \data_f1_out[85]\, - \data_f1_out[86]\, \data_f1_out[87]\, \data_f1_out[88]\, - \data_f1_out[89]\, \data_f1_out[90]\, \data_f1_out[91]\, - \data_f1_out[92]\, \data_f1_out[93]\, \data_f1_out[94]\, - \data_f1_out[95]\, \data_f1_out[96]\, \data_f1_out[97]\, - \data_f1_out[98]\, \data_f1_out[99]\, \data_f1_out[100]\, - \data_f1_out[101]\, \data_f1_out[102]\, - \data_f1_out[103]\, \data_f1_out[104]\, - \data_f1_out[105]\, \data_f1_out[106]\, - \data_f1_out[107]\, \data_f1_out[108]\, - \data_f1_out[109]\, \data_f1_out[110]\, - \data_f1_out[111]\, \data_f1_out[112]\, - \data_f1_out[113]\, \data_f1_out[114]\, - \data_f1_out[115]\, \data_f1_out[116]\, - \data_f1_out[117]\, \data_f1_out[118]\, - \data_f1_out[119]\, \data_f1_out[120]\, - \data_f1_out[121]\, \data_f1_out[122]\, - \data_f1_out[123]\, \data_f1_out[124]\, - \data_f1_out[125]\, \data_f1_out[126]\, - \data_f1_out[127]\, \data_f1_out[128]\, - \data_f1_out[129]\, \data_f1_out[130]\, - \data_f1_out[131]\, \data_f1_out[132]\, - \data_f1_out[133]\, \data_f1_out[134]\, - \data_f1_out[135]\, \data_f1_out[136]\, - \data_f1_out[137]\, \data_f1_out[138]\, - \data_f1_out[139]\, \data_f1_out[140]\, - \data_f1_out[141]\, \data_f1_out[142]\, - \data_f1_out[143]\, \data_f1_out[144]\, - \data_f1_out[145]\, \data_f1_out[146]\, - \data_f1_out[147]\, \data_f1_out[148]\, - \data_f1_out[149]\, \data_f1_out[150]\, - \data_f1_out[151]\, \data_f1_out[152]\, - \data_f1_out[153]\, \data_f1_out[154]\, - \data_f1_out[155]\, \data_f1_out[156]\, - \data_f1_out[157]\, \data_f1_out[158]\, - \data_f1_out[159]\, data_f1_out_valid, \data_f2_out[64]\, - \data_f2_out[65]\, \data_f2_out[66]\, \data_f2_out[67]\, - \data_f2_out[68]\, \data_f2_out[69]\, \data_f2_out[70]\, - \data_f2_out[71]\, \data_f2_out[72]\, \data_f2_out[73]\, - \data_f2_out[74]\, \data_f2_out[75]\, \data_f2_out[76]\, - \data_f2_out[77]\, \data_f2_out[78]\, \data_f2_out[79]\, - \data_f2_out[80]\, \data_f2_out[81]\, \data_f2_out[82]\, - \data_f2_out[83]\, \data_f2_out[84]\, \data_f2_out[85]\, - \data_f2_out[86]\, \data_f2_out[87]\, \data_f2_out[88]\, - \data_f2_out[89]\, \data_f2_out[90]\, \data_f2_out[91]\, - \data_f2_out[92]\, \data_f2_out[93]\, \data_f2_out[94]\, - \data_f2_out[95]\, \data_f2_out[96]\, \data_f2_out[97]\, - \data_f2_out[98]\, \data_f2_out[99]\, \data_f2_out[100]\, - \data_f2_out[101]\, \data_f2_out[102]\, - \data_f2_out[103]\, \data_f2_out[104]\, - \data_f2_out[105]\, \data_f2_out[106]\, - \data_f2_out[107]\, \data_f2_out[108]\, - \data_f2_out[109]\, \data_f2_out[110]\, - \data_f2_out[111]\, \data_f2_out[112]\, - \data_f2_out[113]\, \data_f2_out[114]\, - \data_f2_out[115]\, \data_f2_out[116]\, - \data_f2_out[117]\, \data_f2_out[118]\, - \data_f2_out[119]\, \data_f2_out[120]\, - \data_f2_out[121]\, \data_f2_out[122]\, - \data_f2_out[123]\, \data_f2_out[124]\, - \data_f2_out[125]\, \data_f2_out[126]\, - \data_f2_out[127]\, \data_f2_out[128]\, - \data_f2_out[129]\, \data_f2_out[130]\, - \data_f2_out[131]\, \data_f2_out[132]\, - \data_f2_out[133]\, \data_f2_out[134]\, - \data_f2_out[135]\, \data_f2_out[136]\, - \data_f2_out[137]\, \data_f2_out[138]\, - \data_f2_out[139]\, \data_f2_out[140]\, - \data_f2_out[141]\, \data_f2_out[142]\, - \data_f2_out[143]\, \data_f2_out[144]\, - \data_f2_out[145]\, \data_f2_out[146]\, - \data_f2_out[147]\, \data_f2_out[148]\, - \data_f2_out[149]\, \data_f2_out[150]\, - \data_f2_out[151]\, \data_f2_out[152]\, - \data_f2_out[153]\, \data_f2_out[154]\, - \data_f2_out[155]\, \data_f2_out[156]\, - \data_f2_out[157]\, \data_f2_out[158]\, - \data_f2_out[159]\, data_f2_out_valid, \data_f3_out[64]\, - \data_f3_out[65]\, \data_f3_out[66]\, \data_f3_out[67]\, - \data_f3_out[68]\, \data_f3_out[69]\, \data_f3_out[70]\, - \data_f3_out[71]\, \data_f3_out[72]\, \data_f3_out[73]\, - \data_f3_out[74]\, \data_f3_out[75]\, \data_f3_out[76]\, - \data_f3_out[77]\, \data_f3_out[78]\, \data_f3_out[79]\, - \data_f3_out[80]\, \data_f3_out[81]\, \data_f3_out[82]\, - \data_f3_out[83]\, \data_f3_out[84]\, \data_f3_out[85]\, - \data_f3_out[86]\, \data_f3_out[87]\, \data_f3_out[88]\, - \data_f3_out[89]\, \data_f3_out[90]\, \data_f3_out[91]\, - \data_f3_out[92]\, \data_f3_out[93]\, \data_f3_out[94]\, - \data_f3_out[95]\, \data_f3_out[96]\, \data_f3_out[97]\, - \data_f3_out[98]\, \data_f3_out[99]\, \data_f3_out[100]\, - \data_f3_out[101]\, \data_f3_out[102]\, - \data_f3_out[103]\, \data_f3_out[104]\, - \data_f3_out[105]\, \data_f3_out[106]\, - \data_f3_out[107]\, \data_f3_out[108]\, - \data_f3_out[109]\, \data_f3_out[110]\, - \data_f3_out[111]\, \data_f3_out[112]\, - \data_f3_out[113]\, \data_f3_out[114]\, - \data_f3_out[115]\, \data_f3_out[116]\, - \data_f3_out[117]\, \data_f3_out[118]\, - \data_f3_out[119]\, \data_f3_out[120]\, - \data_f3_out[121]\, \data_f3_out[122]\, - \data_f3_out[123]\, \data_f3_out[124]\, - \data_f3_out[125]\, \data_f3_out[126]\, - \data_f3_out[127]\, \data_f3_out[128]\, - \data_f3_out[129]\, \data_f3_out[130]\, - \data_f3_out[131]\, \data_f3_out[132]\, - \data_f3_out[133]\, \data_f3_out[134]\, - \data_f3_out[135]\, \data_f3_out[136]\, - \data_f3_out[137]\, \data_f3_out[138]\, - \data_f3_out[139]\, \data_f3_out[140]\, - \data_f3_out[141]\, \data_f3_out[142]\, - \data_f3_out[143]\, \data_f3_out[144]\, - \data_f3_out[145]\, \data_f3_out[146]\, - \data_f3_out[147]\, \data_f3_out[148]\, - \data_f3_out[149]\, \data_f3_out[150]\, - \data_f3_out[151]\, \data_f3_out[152]\, - \data_f3_out[153]\, \data_f3_out[154]\, - \data_f3_out[155]\, \data_f3_out[156]\, - \data_f3_out[157]\, \data_f3_out[158]\, - \data_f3_out[159]\, data_f3_out_valid, \valid_ack[3]\, - \valid_out[3]\, \valid_ack[0]\, \valid_out[0]\, - \valid_out_i[1]\, \valid_ack[1]\, \valid_ack[2]\, - \valid_out[2]\, \wdata[0]\, \wdata[1]\, \wdata[2]\, - \wdata[3]\, \wdata[4]\, \wdata[5]\, \wdata[6]\, - \wdata[7]\, \wdata[8]\, \wdata[9]\, \wdata[10]\, - \wdata[11]\, \wdata[12]\, \wdata[13]\, \wdata[14]\, - \wdata[15]\, \wdata[16]\, \wdata[17]\, \wdata[18]\, - \wdata[19]\, \wdata[20]\, \wdata[21]\, \wdata[22]\, - \wdata[23]\, \wdata[24]\, \wdata[25]\, \wdata[26]\, - \wdata[27]\, \wdata[28]\, \wdata[29]\, \wdata[30]\, - \wdata[31]\, \data_wen[0]\, \data_wen[1]\, \data_wen[2]\, - \data_wen[3]\, \time_wen[0]\, \time_wen[1]\, - \time_wen[2]\, \time_wen[3]\, \ready_i_0_i_0[1]\, - \ready_i_0[3]\, \ready_i_0[0]\, \ready_i_0[2]\, - \data_ren[0]\, \data_ren[1]\, \data_ren[2]\, - \data_ren[3]\, \time_ren[0]\, \time_ren[1]\, - \time_ren[2]\, \time_ren[3]\, time_ren, data_ren, - un13_time_write, un20_time_write, un27_time_write, - un5_time_write, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : lpp_waveform_snapshot_160_12 - Use entity work.lpp_waveform_snapshot_160_12(DEF_ARCH); - for all : lpp_waveform_snapshot_controler - Use entity work.lpp_waveform_snapshot_controler(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\(DEF_ARCH); - for all : lpp_waveform_burst - Use entity work.lpp_waveform_burst(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\(DEF_ARCH); - for all : \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - Use entity work. - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\(DEF_ARCH); - for all : lpp_waveform_fifo - Use entity work.lpp_waveform_fifo(DEF_ARCH); - for all : lpp_waveform_snapshot_160_11 - Use entity work.lpp_waveform_snapshot_160_11(DEF_ARCH); - for all : lpp_waveform_snapshot_160_12_1 - Use entity work.lpp_waveform_snapshot_160_12_1(DEF_ARCH); - for all : lpp_waveform_dma - Use entity work.lpp_waveform_dma(DEF_ARCH); - for all : lpp_waveform_fifo_arbiter - Use entity work.lpp_waveform_fifo_arbiter(DEF_ARCH); -begin - - - un7_nb_snapshot_param_more_one_I_45 : XOR2 - port map(A => N_19, B => nb_snapshot_param(8), Y => I_45_11); - - un7_nb_snapshot_param_more_one_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => nb_snapshot_param(6), Y => N_24); - - un7_nb_snapshot_param_more_one_I_16 : AND3 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), C => nb_snapshot_param(2), Y => - \DWACT_FINC_E[0]\); - - lpp_waveform_snapshot_f1 : lpp_waveform_snapshot_160_12 - port map(sample_f1_wdata_95 => sample_f1_wdata_95, - sample_f1_wdata_94 => sample_f1_wdata_94, - sample_f1_wdata_93 => sample_f1_wdata_93, - sample_f1_wdata_92 => sample_f1_wdata_92, - sample_f1_wdata_91 => sample_f1_wdata_91, - sample_f1_wdata_90 => sample_f1_wdata_90, - sample_f1_wdata_89 => sample_f1_wdata_89, - sample_f1_wdata_88 => sample_f1_wdata_88, - sample_f1_wdata_87 => sample_f1_wdata_87, - sample_f1_wdata_86 => sample_f1_wdata_86, - sample_f1_wdata_85 => sample_f1_wdata_85, - sample_f1_wdata_84 => sample_f1_wdata_84, - sample_f1_wdata_83 => sample_f1_wdata_83, - sample_f1_wdata_82 => sample_f1_wdata_82, - sample_f1_wdata_81 => sample_f1_wdata_81, - sample_f1_wdata_80 => sample_f1_wdata_80, - sample_f1_wdata_79 => sample_f1_wdata_79, - sample_f1_wdata_78 => sample_f1_wdata_78, - sample_f1_wdata_77 => sample_f1_wdata_77, - sample_f1_wdata_76 => sample_f1_wdata_76, - sample_f1_wdata_75 => sample_f1_wdata_75, - sample_f1_wdata_74 => sample_f1_wdata_74, - sample_f1_wdata_73 => sample_f1_wdata_73, - sample_f1_wdata_72 => sample_f1_wdata_72, - sample_f1_wdata_71 => sample_f1_wdata_71, - sample_f1_wdata_70 => sample_f1_wdata_70, - sample_f1_wdata_69 => sample_f1_wdata_69, - sample_f1_wdata_68 => sample_f1_wdata_68, - sample_f1_wdata_67 => sample_f1_wdata_67, - sample_f1_wdata_66 => sample_f1_wdata_66, - sample_f1_wdata_65 => sample_f1_wdata_65, - sample_f1_wdata_64 => sample_f1_wdata_64, - sample_f1_wdata_63 => sample_f1_wdata_63, - sample_f1_wdata_62 => sample_f1_wdata_62, - sample_f1_wdata_61 => sample_f1_wdata_61, - sample_f1_wdata_60 => sample_f1_wdata_60, - sample_f1_wdata_59 => sample_f1_wdata_59, - sample_f1_wdata_58 => sample_f1_wdata_58, - sample_f1_wdata_57 => sample_f1_wdata_57, - sample_f1_wdata_56 => sample_f1_wdata_56, - sample_f1_wdata_55 => sample_f1_wdata_55, - sample_f1_wdata_54 => sample_f1_wdata_54, - sample_f1_wdata_53 => sample_f1_wdata_53, - sample_f1_wdata_52 => sample_f1_wdata_52, - sample_f1_wdata_51 => sample_f1_wdata_51, - sample_f1_wdata_50 => sample_f1_wdata_50, - sample_f1_wdata_49 => sample_f1_wdata_49, - sample_f1_wdata_48 => sample_f1_wdata_48, - sample_f1_wdata_15 => sample_f1_wdata_15, - sample_f1_wdata_14 => sample_f1_wdata_14, - sample_f1_wdata_13 => sample_f1_wdata_13, - sample_f1_wdata_12 => sample_f1_wdata_12, - sample_f1_wdata_11 => sample_f1_wdata_11, - sample_f1_wdata_10 => sample_f1_wdata_10, - sample_f1_wdata_9 => sample_f1_wdata_9, sample_f1_wdata_8 - => sample_f1_wdata_8, sample_f1_wdata_7 => - sample_f1_wdata_7, sample_f1_wdata_6 => sample_f1_wdata_6, - sample_f1_wdata_5 => sample_f1_wdata_5, sample_f1_wdata_4 - => sample_f1_wdata_4, sample_f1_wdata_3 => - sample_f1_wdata_3, sample_f1_wdata_2 => sample_f1_wdata_2, - sample_f1_wdata_1 => sample_f1_wdata_1, sample_f1_wdata_0 - => sample_f1_wdata_0, data_f1_out(159) => - \data_f1_out[159]\, data_f1_out(158) => - \data_f1_out[158]\, data_f1_out(157) => - \data_f1_out[157]\, data_f1_out(156) => - \data_f1_out[156]\, data_f1_out(155) => - \data_f1_out[155]\, data_f1_out(154) => - \data_f1_out[154]\, data_f1_out(153) => - \data_f1_out[153]\, data_f1_out(152) => - \data_f1_out[152]\, data_f1_out(151) => - \data_f1_out[151]\, data_f1_out(150) => - \data_f1_out[150]\, data_f1_out(149) => - \data_f1_out[149]\, data_f1_out(148) => - \data_f1_out[148]\, data_f1_out(147) => - \data_f1_out[147]\, data_f1_out(146) => - \data_f1_out[146]\, data_f1_out(145) => - \data_f1_out[145]\, data_f1_out(144) => - \data_f1_out[144]\, data_f1_out(143) => - \data_f1_out[143]\, data_f1_out(142) => - \data_f1_out[142]\, data_f1_out(141) => - \data_f1_out[141]\, data_f1_out(140) => - \data_f1_out[140]\, data_f1_out(139) => - \data_f1_out[139]\, data_f1_out(138) => - \data_f1_out[138]\, data_f1_out(137) => - \data_f1_out[137]\, data_f1_out(136) => - \data_f1_out[136]\, data_f1_out(135) => - \data_f1_out[135]\, data_f1_out(134) => - \data_f1_out[134]\, data_f1_out(133) => - \data_f1_out[133]\, data_f1_out(132) => - \data_f1_out[132]\, data_f1_out(131) => - \data_f1_out[131]\, data_f1_out(130) => - \data_f1_out[130]\, data_f1_out(129) => - \data_f1_out[129]\, data_f1_out(128) => - \data_f1_out[128]\, data_f1_out(127) => - \data_f1_out[127]\, data_f1_out(126) => - \data_f1_out[126]\, data_f1_out(125) => - \data_f1_out[125]\, data_f1_out(124) => - \data_f1_out[124]\, data_f1_out(123) => - \data_f1_out[123]\, data_f1_out(122) => - \data_f1_out[122]\, data_f1_out(121) => - \data_f1_out[121]\, data_f1_out(120) => - \data_f1_out[120]\, data_f1_out(119) => - \data_f1_out[119]\, data_f1_out(118) => - \data_f1_out[118]\, data_f1_out(117) => - \data_f1_out[117]\, data_f1_out(116) => - \data_f1_out[116]\, data_f1_out(115) => - \data_f1_out[115]\, data_f1_out(114) => - \data_f1_out[114]\, data_f1_out(113) => - \data_f1_out[113]\, data_f1_out(112) => - \data_f1_out[112]\, data_f1_out(111) => - \data_f1_out[111]\, data_f1_out(110) => - \data_f1_out[110]\, data_f1_out(109) => - \data_f1_out[109]\, data_f1_out(108) => - \data_f1_out[108]\, data_f1_out(107) => - \data_f1_out[107]\, data_f1_out(106) => - \data_f1_out[106]\, data_f1_out(105) => - \data_f1_out[105]\, data_f1_out(104) => - \data_f1_out[104]\, data_f1_out(103) => - \data_f1_out[103]\, data_f1_out(102) => - \data_f1_out[102]\, data_f1_out(101) => - \data_f1_out[101]\, data_f1_out(100) => - \data_f1_out[100]\, data_f1_out(99) => \data_f1_out[99]\, - data_f1_out(98) => \data_f1_out[98]\, data_f1_out(97) => - \data_f1_out[97]\, data_f1_out(96) => \data_f1_out[96]\, - data_f1_out(95) => \data_f1_out[95]\, data_f1_out(94) => - \data_f1_out[94]\, data_f1_out(93) => \data_f1_out[93]\, - data_f1_out(92) => \data_f1_out[92]\, data_f1_out(91) => - \data_f1_out[91]\, data_f1_out(90) => \data_f1_out[90]\, - data_f1_out(89) => \data_f1_out[89]\, data_f1_out(88) => - \data_f1_out[88]\, data_f1_out(87) => \data_f1_out[87]\, - data_f1_out(86) => \data_f1_out[86]\, data_f1_out(85) => - \data_f1_out[85]\, data_f1_out(84) => \data_f1_out[84]\, - data_f1_out(83) => \data_f1_out[83]\, data_f1_out(82) => - \data_f1_out[82]\, data_f1_out(81) => \data_f1_out[81]\, - data_f1_out(80) => \data_f1_out[80]\, data_f1_out(79) => - \data_f1_out[79]\, data_f1_out(78) => \data_f1_out[78]\, - data_f1_out(77) => \data_f1_out[77]\, data_f1_out(76) => - \data_f1_out[76]\, data_f1_out(75) => \data_f1_out[75]\, - data_f1_out(74) => \data_f1_out[74]\, data_f1_out(73) => - \data_f1_out[73]\, data_f1_out(72) => \data_f1_out[72]\, - data_f1_out(71) => \data_f1_out[71]\, data_f1_out(70) => - \data_f1_out[70]\, data_f1_out(69) => \data_f1_out[69]\, - data_f1_out(68) => \data_f1_out[68]\, data_f1_out(67) => - \data_f1_out[67]\, data_f1_out(66) => \data_f1_out[66]\, - data_f1_out(65) => \data_f1_out[65]\, data_f1_out(64) => - \data_f1_out[64]\, sample_f1_37 => sample_f1_37, - sample_f1_5 => sample_f1_5, sample_f1_38 => sample_f1_38, - sample_f1_6 => sample_f1_6, sample_f1_39 => sample_f1_39, - sample_f1_7 => sample_f1_7, sample_f1_40 => sample_f1_40, - sample_f1_8 => sample_f1_8, sample_f1_41 => sample_f1_41, - sample_f1_9 => sample_f1_9, sample_f1_42 => sample_f1_42, - sample_f1_10 => sample_f1_10, sample_f1_43 => - sample_f1_43, sample_f1_11 => sample_f1_11, sample_f1_61 - => sample_f1_61, sample_f1_62 => sample_f1_62, - sample_f1_63 => sample_f1_63, sample_f1_32 => - sample_f1_32, sample_f1_0 => sample_f1_0, sample_f1_33 - => sample_f1_33, sample_f1_1 => sample_f1_1, - sample_f1_34 => sample_f1_34, sample_f1_2 => sample_f1_2, - sample_f1_35 => sample_f1_35, sample_f1_3 => sample_f1_3, - sample_f1_36 => sample_f1_36, sample_f1_4 => sample_f1_4, - sample_f1_48 => sample_f1_48, sample_f1_49 => - sample_f1_49, sample_f1_50 => sample_f1_50, sample_f1_51 - => sample_f1_51, sample_f1_52 => sample_f1_52, - sample_f1_53 => sample_f1_53, sample_f1_54 => - sample_f1_54, sample_f1_55 => sample_f1_55, sample_f1_56 - => sample_f1_56, sample_f1_57 => sample_f1_57, - sample_f1_58 => sample_f1_58, sample_f1_59 => - sample_f1_59, sample_f1_60 => sample_f1_60, sample_f1_44 - => sample_f1_44, sample_f1_12 => sample_f1_12, - sample_f1_45 => sample_f1_45, sample_f1_13 => - sample_f1_13, sample_f1_46 => sample_f1_46, sample_f1_14 - => sample_f1_14, sample_f1_47 => sample_f1_47, - sample_f1_15 => sample_f1_15, nb_snapshot_param(0) => - nb_snapshot_param(0), rstn => rstn, lclk_c => lclk_c, - data_f1_out_valid => data_f1_out_valid, data_shaping_R1 - => data_shaping_R1, data_shaping_R1_0 => - data_shaping_R1_0, I_9_31 => I_9_31, I_45_11 => I_45_11, - I_52_11 => I_52_11, I_56_12 => I_56_12, I_24_16 => - I_24_16, N_4 => N_4, I_20_23 => I_20_23, I_13_35 => - I_13_35, I_38_12 => I_38_12, I_31_15 => I_31_15, I_5_31 - => I_5_31, enable_f1 => enable_f1, burst_f1 => burst_f1, - sample_f1_val_0 => sample_f1_val_0, start_snapshot_f1 => - start_snapshot_f1); - - lpp_waveform_snapshot_controler_1 : - lpp_waveform_snapshot_controler - port map(coarse_time_i(0) => coarse_time_i(0), - delta_f2_f0(9) => delta_f2_f0(9), delta_f2_f0(8) => - delta_f2_f0(8), delta_f2_f0(7) => delta_f2_f0(7), - delta_f2_f0(6) => delta_f2_f0(6), delta_f2_f0(5) => - delta_f2_f0(5), delta_f2_f0(4) => delta_f2_f0(4), - delta_f2_f0(3) => delta_f2_f0(3), delta_f2_f0(2) => - delta_f2_f0(2), delta_f2_f0(1) => delta_f2_f0(1), - delta_f2_f0(0) => delta_f2_f0(0), delta_f2_f1(9) => - delta_f2_f1(9), delta_f2_f1(8) => delta_f2_f1(8), - delta_f2_f1(7) => delta_f2_f1(7), delta_f2_f1(6) => - delta_f2_f1(6), delta_f2_f1(5) => delta_f2_f1(5), - delta_f2_f1(4) => delta_f2_f1(4), delta_f2_f1(3) => - delta_f2_f1(3), delta_f2_f1(2) => delta_f2_f1(2), - delta_f2_f1(1) => delta_f2_f1(1), delta_f2_f1(0) => - delta_f2_f1(0), delta_snapshot(15) => delta_snapshot(15), - delta_snapshot(14) => delta_snapshot(14), - delta_snapshot(13) => delta_snapshot(13), - delta_snapshot(12) => delta_snapshot(12), - delta_snapshot(11) => delta_snapshot(11), - delta_snapshot(10) => delta_snapshot(10), - delta_snapshot(9) => delta_snapshot(9), delta_snapshot(8) - => delta_snapshot(8), delta_snapshot(7) => - delta_snapshot(7), delta_snapshot(6) => delta_snapshot(6), - delta_snapshot(5) => delta_snapshot(5), delta_snapshot(4) - => delta_snapshot(4), delta_snapshot(3) => - delta_snapshot(3), delta_snapshot(2) => delta_snapshot(2), - delta_snapshot(1) => delta_snapshot(1), delta_snapshot(0) - => delta_snapshot(0), coarse_time(0) => coarse_time(0), - start_snapshot_f2 => start_snapshot_f2, start_snapshot_f1 - => start_snapshot_f1, start_snapshot_f0 => - start_snapshot_f0, sample_f2_val => sample_f2_val, - sample_f0_val_0 => sample_f0_val_0, rstn => rstn, lclk_c - => lclk_c); - - un7_nb_snapshot_param_more_one_I_20 : XOR2 - port map(A => N_37, B => nb_snapshot_param(4), Y => I_20_23); - - \all_input_valid.3.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I\ - port map(status_new_err(3) => status_new_err(3), - valid_ack(3) => \valid_ack[3]\, valid_out(3) => - \valid_out[3]\, rstn => rstn, lclk_c => lclk_c, - data_f3_out_valid => data_f3_out_valid); - - un7_nb_snapshot_param_more_one_I_52 : XOR2 - port map(A => N_14, B => nb_snapshot_param(9), Y => I_52_11); - - VCC_i : VCC - port map(Y => \VCC\); - - un7_nb_snapshot_param_more_one_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - un7_nb_snapshot_param_more_one_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => nb_snapshot_param(3), - C => nb_snapshot_param(4), Y => N_34); - - un7_nb_snapshot_param_more_one_I_56 : XOR2 - port map(A => N_11, B => nb_snapshot_param(10), Y => - I_56_12); - - un7_nb_snapshot_param_more_one_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un7_nb_snapshot_param_more_one_I_19 : NOR2B - port map(A => nb_snapshot_param(3), B => \DWACT_FINC_E[0]\, - Y => N_37); - - un7_nb_snapshot_param_more_one_I_24 : XOR2 - port map(A => N_34, B => nb_snapshot_param(5), Y => I_24_16); - - un7_nb_snapshot_param_more_one_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_19); - - \all_input_valid.1.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_2\ - port map(status_new_err(1) => status_new_err(1), - valid_out_i(1) => \valid_out_i[1]\, valid_ack(1) => - \valid_ack[1]\, rstn => rstn, lclk_c => lclk_c, - data_f1_out_valid => data_f1_out_valid); - - un7_nb_snapshot_param_more_one_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => nb_snapshot_param(8), - C => nb_snapshot_param(9), Y => N_11); - - un7_nb_snapshot_param_more_one_I_13 : XOR2 - port map(A => N_42, B => nb_snapshot_param(3), Y => I_13_35); - - un7_nb_snapshot_param_more_one_I_9 : XOR2 - port map(A => N_45, B => nb_snapshot_param(2), Y => I_9_31); - - un7_nb_snapshot_param_more_one_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => nb_snapshot_param(9), - C => nb_snapshot_param(10), Y => N_4); - - un7_nb_snapshot_param_more_one_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => nb_snapshot_param(5), Y => N_29); - - GND_i : GND - port map(Y => \GND\); - - un7_nb_snapshot_param_more_one_I_59 : AND3 - port map(A => nb_snapshot_param(6), B => - nb_snapshot_param(7), C => nb_snapshot_param(8), Y => - \DWACT_FINC_E[5]\); - - lpp_waveform_burst_f3 : lpp_waveform_burst - port map(sample_f3_wdata(95) => sample_f3_wdata(95), - sample_f3_wdata(94) => sample_f3_wdata(94), - sample_f3_wdata(93) => sample_f3_wdata(93), - sample_f3_wdata(92) => sample_f3_wdata(92), - sample_f3_wdata(91) => sample_f3_wdata(91), - sample_f3_wdata(90) => sample_f3_wdata(90), - sample_f3_wdata(89) => sample_f3_wdata(89), - sample_f3_wdata(88) => sample_f3_wdata(88), - sample_f3_wdata(87) => sample_f3_wdata(87), - sample_f3_wdata(86) => sample_f3_wdata(86), - sample_f3_wdata(85) => sample_f3_wdata(85), - sample_f3_wdata(84) => sample_f3_wdata(84), - sample_f3_wdata(83) => sample_f3_wdata(83), - sample_f3_wdata(82) => sample_f3_wdata(82), - sample_f3_wdata(81) => sample_f3_wdata(81), - sample_f3_wdata(80) => sample_f3_wdata(80), - sample_f3_wdata(79) => sample_f3_wdata(79), - sample_f3_wdata(78) => sample_f3_wdata(78), - sample_f3_wdata(77) => sample_f3_wdata(77), - sample_f3_wdata(76) => sample_f3_wdata(76), - sample_f3_wdata(75) => sample_f3_wdata(75), - sample_f3_wdata(74) => sample_f3_wdata(74), - sample_f3_wdata(73) => sample_f3_wdata(73), - sample_f3_wdata(72) => sample_f3_wdata(72), - sample_f3_wdata(71) => sample_f3_wdata(71), - sample_f3_wdata(70) => sample_f3_wdata(70), - sample_f3_wdata(69) => sample_f3_wdata(69), - sample_f3_wdata(68) => sample_f3_wdata(68), - sample_f3_wdata(67) => sample_f3_wdata(67), - sample_f3_wdata(66) => sample_f3_wdata(66), - sample_f3_wdata(65) => sample_f3_wdata(65), - sample_f3_wdata(64) => sample_f3_wdata(64), - sample_f3_wdata(63) => sample_f3_wdata(63), - sample_f3_wdata(62) => sample_f3_wdata(62), - sample_f3_wdata(61) => sample_f3_wdata(61), - sample_f3_wdata(60) => sample_f3_wdata(60), - sample_f3_wdata(59) => sample_f3_wdata(59), - sample_f3_wdata(58) => sample_f3_wdata(58), - sample_f3_wdata(57) => sample_f3_wdata(57), - sample_f3_wdata(56) => sample_f3_wdata(56), - sample_f3_wdata(55) => sample_f3_wdata(55), - sample_f3_wdata(54) => sample_f3_wdata(54), - sample_f3_wdata(53) => sample_f3_wdata(53), - sample_f3_wdata(52) => sample_f3_wdata(52), - sample_f3_wdata(51) => sample_f3_wdata(51), - sample_f3_wdata(50) => sample_f3_wdata(50), - sample_f3_wdata(49) => sample_f3_wdata(49), - sample_f3_wdata(48) => sample_f3_wdata(48), - sample_f3_wdata(47) => sample_f3_wdata(47), - sample_f3_wdata(46) => sample_f3_wdata(46), - sample_f3_wdata(45) => sample_f3_wdata(45), - sample_f3_wdata(44) => sample_f3_wdata(44), - sample_f3_wdata(43) => sample_f3_wdata(43), - sample_f3_wdata(42) => sample_f3_wdata(42), - sample_f3_wdata(41) => sample_f3_wdata(41), - sample_f3_wdata(40) => sample_f3_wdata(40), - sample_f3_wdata(39) => sample_f3_wdata(39), - sample_f3_wdata(38) => sample_f3_wdata(38), - sample_f3_wdata(37) => sample_f3_wdata(37), - sample_f3_wdata(36) => sample_f3_wdata(36), - sample_f3_wdata(35) => sample_f3_wdata(35), - sample_f3_wdata(34) => sample_f3_wdata(34), - sample_f3_wdata(33) => sample_f3_wdata(33), - sample_f3_wdata(32) => sample_f3_wdata(32), - sample_f3_wdata(31) => sample_f3_wdata(31), - sample_f3_wdata(30) => sample_f3_wdata(30), - sample_f3_wdata(29) => sample_f3_wdata(29), - sample_f3_wdata(28) => sample_f3_wdata(28), - sample_f3_wdata(27) => sample_f3_wdata(27), - sample_f3_wdata(26) => sample_f3_wdata(26), - sample_f3_wdata(25) => sample_f3_wdata(25), - sample_f3_wdata(24) => sample_f3_wdata(24), - sample_f3_wdata(23) => sample_f3_wdata(23), - sample_f3_wdata(22) => sample_f3_wdata(22), - sample_f3_wdata(21) => sample_f3_wdata(21), - sample_f3_wdata(20) => sample_f3_wdata(20), - sample_f3_wdata(19) => sample_f3_wdata(19), - sample_f3_wdata(18) => sample_f3_wdata(18), - sample_f3_wdata(17) => sample_f3_wdata(17), - sample_f3_wdata(16) => sample_f3_wdata(16), - sample_f3_wdata(15) => sample_f3_wdata(15), - sample_f3_wdata(14) => sample_f3_wdata(14), - sample_f3_wdata(13) => sample_f3_wdata(13), - sample_f3_wdata(12) => sample_f3_wdata(12), - sample_f3_wdata(11) => sample_f3_wdata(11), - sample_f3_wdata(10) => sample_f3_wdata(10), - sample_f3_wdata(9) => sample_f3_wdata(9), - sample_f3_wdata(8) => sample_f3_wdata(8), - sample_f3_wdata(7) => sample_f3_wdata(7), - sample_f3_wdata(6) => sample_f3_wdata(6), - sample_f3_wdata(5) => sample_f3_wdata(5), - sample_f3_wdata(4) => sample_f3_wdata(4), - sample_f3_wdata(3) => sample_f3_wdata(3), - sample_f3_wdata(2) => sample_f3_wdata(2), - sample_f3_wdata(1) => sample_f3_wdata(1), - sample_f3_wdata(0) => sample_f3_wdata(0), - data_f3_out(159) => \data_f3_out[159]\, data_f3_out(158) - => \data_f3_out[158]\, data_f3_out(157) => - \data_f3_out[157]\, data_f3_out(156) => - \data_f3_out[156]\, data_f3_out(155) => - \data_f3_out[155]\, data_f3_out(154) => - \data_f3_out[154]\, data_f3_out(153) => - \data_f3_out[153]\, data_f3_out(152) => - \data_f3_out[152]\, data_f3_out(151) => - \data_f3_out[151]\, data_f3_out(150) => - \data_f3_out[150]\, data_f3_out(149) => - \data_f3_out[149]\, data_f3_out(148) => - \data_f3_out[148]\, data_f3_out(147) => - \data_f3_out[147]\, data_f3_out(146) => - \data_f3_out[146]\, data_f3_out(145) => - \data_f3_out[145]\, data_f3_out(144) => - \data_f3_out[144]\, data_f3_out(143) => - \data_f3_out[143]\, data_f3_out(142) => - \data_f3_out[142]\, data_f3_out(141) => - \data_f3_out[141]\, data_f3_out(140) => - \data_f3_out[140]\, data_f3_out(139) => - \data_f3_out[139]\, data_f3_out(138) => - \data_f3_out[138]\, data_f3_out(137) => - \data_f3_out[137]\, data_f3_out(136) => - \data_f3_out[136]\, data_f3_out(135) => - \data_f3_out[135]\, data_f3_out(134) => - \data_f3_out[134]\, data_f3_out(133) => - \data_f3_out[133]\, data_f3_out(132) => - \data_f3_out[132]\, data_f3_out(131) => - \data_f3_out[131]\, data_f3_out(130) => - \data_f3_out[130]\, data_f3_out(129) => - \data_f3_out[129]\, data_f3_out(128) => - \data_f3_out[128]\, data_f3_out(127) => - \data_f3_out[127]\, data_f3_out(126) => - \data_f3_out[126]\, data_f3_out(125) => - \data_f3_out[125]\, data_f3_out(124) => - \data_f3_out[124]\, data_f3_out(123) => - \data_f3_out[123]\, data_f3_out(122) => - \data_f3_out[122]\, data_f3_out(121) => - \data_f3_out[121]\, data_f3_out(120) => - \data_f3_out[120]\, data_f3_out(119) => - \data_f3_out[119]\, data_f3_out(118) => - \data_f3_out[118]\, data_f3_out(117) => - \data_f3_out[117]\, data_f3_out(116) => - \data_f3_out[116]\, data_f3_out(115) => - \data_f3_out[115]\, data_f3_out(114) => - \data_f3_out[114]\, data_f3_out(113) => - \data_f3_out[113]\, data_f3_out(112) => - \data_f3_out[112]\, data_f3_out(111) => - \data_f3_out[111]\, data_f3_out(110) => - \data_f3_out[110]\, data_f3_out(109) => - \data_f3_out[109]\, data_f3_out(108) => - \data_f3_out[108]\, data_f3_out(107) => - \data_f3_out[107]\, data_f3_out(106) => - \data_f3_out[106]\, data_f3_out(105) => - \data_f3_out[105]\, data_f3_out(104) => - \data_f3_out[104]\, data_f3_out(103) => - \data_f3_out[103]\, data_f3_out(102) => - \data_f3_out[102]\, data_f3_out(101) => - \data_f3_out[101]\, data_f3_out(100) => - \data_f3_out[100]\, data_f3_out(99) => \data_f3_out[99]\, - data_f3_out(98) => \data_f3_out[98]\, data_f3_out(97) => - \data_f3_out[97]\, data_f3_out(96) => \data_f3_out[96]\, - data_f3_out(95) => \data_f3_out[95]\, data_f3_out(94) => - \data_f3_out[94]\, data_f3_out(93) => \data_f3_out[93]\, - data_f3_out(92) => \data_f3_out[92]\, data_f3_out(91) => - \data_f3_out[91]\, data_f3_out(90) => \data_f3_out[90]\, - data_f3_out(89) => \data_f3_out[89]\, data_f3_out(88) => - \data_f3_out[88]\, data_f3_out(87) => \data_f3_out[87]\, - data_f3_out(86) => \data_f3_out[86]\, data_f3_out(85) => - \data_f3_out[85]\, data_f3_out(84) => \data_f3_out[84]\, - data_f3_out(83) => \data_f3_out[83]\, data_f3_out(82) => - \data_f3_out[82]\, data_f3_out(81) => \data_f3_out[81]\, - data_f3_out(80) => \data_f3_out[80]\, data_f3_out(79) => - \data_f3_out[79]\, data_f3_out(78) => \data_f3_out[78]\, - data_f3_out(77) => \data_f3_out[77]\, data_f3_out(76) => - \data_f3_out[76]\, data_f3_out(75) => \data_f3_out[75]\, - data_f3_out(74) => \data_f3_out[74]\, data_f3_out(73) => - \data_f3_out[73]\, data_f3_out(72) => \data_f3_out[72]\, - data_f3_out(71) => \data_f3_out[71]\, data_f3_out(70) => - \data_f3_out[70]\, data_f3_out(69) => \data_f3_out[69]\, - data_f3_out(68) => \data_f3_out[68]\, data_f3_out(67) => - \data_f3_out[67]\, data_f3_out(66) => \data_f3_out[66]\, - data_f3_out(65) => \data_f3_out[65]\, data_f3_out(64) => - \data_f3_out[64]\, rstn => rstn, lclk_c => lclk_c, - data_f3_out_valid => data_f3_out_valid, enable_f3 => - enable_f3, sample_f3_val => sample_f3_val); - - \all_input_valid.2.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_3\ - port map(status_new_err(2) => status_new_err(2), - valid_ack(2) => \valid_ack[2]\, valid_out(2) => - \valid_out[2]\, rstn => rstn, lclk_c => lclk_c, - data_f2_out_valid => data_f2_out_valid); - - un7_nb_snapshot_param_more_one_I_41 : AND2 - port map(A => nb_snapshot_param(6), B => - nb_snapshot_param(7), Y => \DWACT_FINC_E[3]\); - - un7_nb_snapshot_param_more_one_I_38 : XOR2 - port map(A => N_24, B => nb_snapshot_param(7), Y => I_38_12); - - \all_input_valid.0.lpp_waveform_dma_gen_valid_I\ : - \lpp_waveform_dma_gen_valid_all_input_valid.3.lpp_waveform_dma_gen_valid_I_1\ - port map(status_new_err(0) => status_new_err(0), - valid_ack(0) => \valid_ack[0]\, valid_out(0) => - \valid_out[0]\, rstn => rstn, lclk_c => lclk_c, - data_f0_out_valid => data_f0_out_valid); - - un7_nb_snapshot_param_more_one_I_27 : AND2 - port map(A => nb_snapshot_param(3), B => - nb_snapshot_param(4), Y => \DWACT_FINC_E[1]\); - - un7_nb_snapshot_param_more_one_I_34 : AND3 - port map(A => nb_snapshot_param(3), B => - nb_snapshot_param(4), C => nb_snapshot_param(5), Y => - \DWACT_FINC_E[2]\); - - un7_nb_snapshot_param_more_one_I_8 : NOR2B - port map(A => nb_snapshot_param(1), B => - nb_snapshot_param(0), Y => N_45); - - lpp_waveform_fifo_1 : lpp_waveform_fifo - port map(ready_i_0_i_0(1) => \ready_i_0_i_0[1]\, - data_wen(3) => \data_wen[3]\, data_wen(2) => - \data_wen[2]\, data_wen(1) => \data_wen[1]\, data_wen(0) - => \data_wen[0]\, data_ren(3) => \data_ren[3]\, - data_ren(2) => \data_ren[2]\, data_ren(1) => - \data_ren[1]\, data_ren(0) => \data_ren[0]\, ready_i_0_2 - => \ready_i_0[2]\, ready_i_0_0 => \ready_i_0[0]\, - ready_i_0_3 => \ready_i_0[3]\, time_ren(3) => - \time_ren[3]\, time_ren(2) => \time_ren[2]\, time_ren(1) - => \time_ren[1]\, time_ren(0) => \time_ren[0]\, - time_wen(3) => \time_wen[3]\, time_wen(2) => - \time_wen[2]\, time_wen(1) => \time_wen[1]\, time_wen(0) - => \time_wen[0]\, hwdata(31) => hwdata(31), hwdata(30) - => hwdata(30), hwdata(29) => hwdata(29), hwdata(28) => - hwdata(28), hwdata(27) => hwdata(27), hwdata(26) => - hwdata(26), hwdata(25) => hwdata(25), hwdata(24) => - hwdata(24), hwdata(23) => hwdata(23), hwdata(22) => - hwdata(22), hwdata(21) => hwdata(21), hwdata(20) => - hwdata(20), hwdata(19) => hwdata(19), hwdata(18) => - hwdata(18), hwdata(17) => hwdata(17), hwdata(16) => - hwdata(16), hwdata(15) => hwdata(15), hwdata(14) => - hwdata(14), hwdata(13) => hwdata(13), hwdata(12) => - hwdata(12), hwdata(11) => hwdata(11), hwdata(10) => - hwdata(10), hwdata(9) => hwdata(9), hwdata(8) => - hwdata(8), hwdata(7) => hwdata(7), hwdata(6) => hwdata(6), - hwdata(5) => hwdata(5), hwdata(4) => hwdata(4), hwdata(3) - => hwdata(3), hwdata(2) => hwdata(2), hwdata(1) => - hwdata(1), hwdata(0) => hwdata(0), wdata(31) => - \wdata[31]\, wdata(30) => \wdata[30]\, wdata(29) => - \wdata[29]\, wdata(28) => \wdata[28]\, wdata(27) => - \wdata[27]\, wdata(26) => \wdata[26]\, wdata(25) => - \wdata[25]\, wdata(24) => \wdata[24]\, wdata(23) => - \wdata[23]\, wdata(22) => \wdata[22]\, wdata(21) => - \wdata[21]\, wdata(20) => \wdata[20]\, wdata(19) => - \wdata[19]\, wdata(18) => \wdata[18]\, wdata(17) => - \wdata[17]\, wdata(16) => \wdata[16]\, wdata(15) => - \wdata[15]\, wdata(14) => \wdata[14]\, wdata(13) => - \wdata[13]\, wdata(12) => \wdata[12]\, wdata(11) => - \wdata[11]\, wdata(10) => \wdata[10]\, wdata(9) => - \wdata[9]\, wdata(8) => \wdata[8]\, wdata(7) => - \wdata[7]\, wdata(6) => \wdata[6]\, wdata(5) => - \wdata[5]\, wdata(4) => \wdata[4]\, wdata(3) => - \wdata[3]\, wdata(2) => \wdata[2]\, wdata(1) => - \wdata[1]\, wdata(0) => \wdata[0]\, time_ren_1z => - time_ren, data_ren_1z => data_ren, un13_time_write => - un13_time_write, un20_time_write => un20_time_write, - un27_time_write => un27_time_write, un5_time_write => - un5_time_write, rstn => rstn, lclk_c => lclk_c); - - lpp_waveform_snapshot_f0 : lpp_waveform_snapshot_160_11 - port map(sample_f0_wdata_95 => sample_f0_wdata_95, - sample_f0_wdata_94 => sample_f0_wdata_94, - sample_f0_wdata_93 => sample_f0_wdata_93, - sample_f0_wdata_92 => sample_f0_wdata_92, - sample_f0_wdata_91 => sample_f0_wdata_91, - sample_f0_wdata_90 => sample_f0_wdata_90, - sample_f0_wdata_89 => sample_f0_wdata_89, - sample_f0_wdata_88 => sample_f0_wdata_88, - sample_f0_wdata_87 => sample_f0_wdata_87, - sample_f0_wdata_86 => sample_f0_wdata_86, - sample_f0_wdata_85 => sample_f0_wdata_85, - sample_f0_wdata_84 => sample_f0_wdata_84, - sample_f0_wdata_83 => sample_f0_wdata_83, - sample_f0_wdata_82 => sample_f0_wdata_82, - sample_f0_wdata_81 => sample_f0_wdata_81, - sample_f0_wdata_80 => sample_f0_wdata_80, - sample_f0_wdata_79 => sample_f0_wdata_79, - sample_f0_wdata_78 => sample_f0_wdata_78, - sample_f0_wdata_77 => sample_f0_wdata_77, - sample_f0_wdata_76 => sample_f0_wdata_76, - sample_f0_wdata_75 => sample_f0_wdata_75, - sample_f0_wdata_74 => sample_f0_wdata_74, - sample_f0_wdata_73 => sample_f0_wdata_73, - sample_f0_wdata_72 => sample_f0_wdata_72, - sample_f0_wdata_71 => sample_f0_wdata_71, - sample_f0_wdata_70 => sample_f0_wdata_70, - sample_f0_wdata_69 => sample_f0_wdata_69, - sample_f0_wdata_68 => sample_f0_wdata_68, - sample_f0_wdata_67 => sample_f0_wdata_67, - sample_f0_wdata_66 => sample_f0_wdata_66, - sample_f0_wdata_65 => sample_f0_wdata_65, - sample_f0_wdata_64 => sample_f0_wdata_64, - sample_f0_wdata_63 => sample_f0_wdata_63, - sample_f0_wdata_62 => sample_f0_wdata_62, - sample_f0_wdata_61 => sample_f0_wdata_61, - sample_f0_wdata_60 => sample_f0_wdata_60, - sample_f0_wdata_59 => sample_f0_wdata_59, - sample_f0_wdata_58 => sample_f0_wdata_58, - sample_f0_wdata_57 => sample_f0_wdata_57, - sample_f0_wdata_56 => sample_f0_wdata_56, - sample_f0_wdata_55 => sample_f0_wdata_55, - sample_f0_wdata_54 => sample_f0_wdata_54, - sample_f0_wdata_53 => sample_f0_wdata_53, - sample_f0_wdata_52 => sample_f0_wdata_52, - sample_f0_wdata_51 => sample_f0_wdata_51, - sample_f0_wdata_50 => sample_f0_wdata_50, - sample_f0_wdata_49 => sample_f0_wdata_49, - sample_f0_wdata_48 => sample_f0_wdata_48, - sample_f0_wdata_15 => sample_f0_wdata_15, - sample_f0_wdata_14 => sample_f0_wdata_14, - sample_f0_wdata_13 => sample_f0_wdata_13, - sample_f0_wdata_12 => sample_f0_wdata_12, - sample_f0_wdata_11 => sample_f0_wdata_11, - sample_f0_wdata_10 => sample_f0_wdata_10, - sample_f0_wdata_9 => sample_f0_wdata_9, sample_f0_wdata_8 - => sample_f0_wdata_8, sample_f0_wdata_7 => - sample_f0_wdata_7, sample_f0_wdata_6 => sample_f0_wdata_6, - sample_f0_wdata_5 => sample_f0_wdata_5, sample_f0_wdata_4 - => sample_f0_wdata_4, sample_f0_wdata_3 => - sample_f0_wdata_3, sample_f0_wdata_2 => sample_f0_wdata_2, - sample_f0_wdata_1 => sample_f0_wdata_1, sample_f0_wdata_0 - => sample_f0_wdata_0, data_f0_out(159) => - \data_f0_out[159]\, data_f0_out(158) => - \data_f0_out[158]\, data_f0_out(157) => - \data_f0_out[157]\, data_f0_out(156) => - \data_f0_out[156]\, data_f0_out(155) => - \data_f0_out[155]\, data_f0_out(154) => - \data_f0_out[154]\, data_f0_out(153) => - \data_f0_out[153]\, data_f0_out(152) => - \data_f0_out[152]\, data_f0_out(151) => - \data_f0_out[151]\, data_f0_out(150) => - \data_f0_out[150]\, data_f0_out(149) => - \data_f0_out[149]\, data_f0_out(148) => - \data_f0_out[148]\, data_f0_out(147) => - \data_f0_out[147]\, data_f0_out(146) => - \data_f0_out[146]\, data_f0_out(145) => - \data_f0_out[145]\, data_f0_out(144) => - \data_f0_out[144]\, data_f0_out(143) => - \data_f0_out[143]\, data_f0_out(142) => - \data_f0_out[142]\, data_f0_out(141) => - \data_f0_out[141]\, data_f0_out(140) => - \data_f0_out[140]\, data_f0_out(139) => - \data_f0_out[139]\, data_f0_out(138) => - \data_f0_out[138]\, data_f0_out(137) => - \data_f0_out[137]\, data_f0_out(136) => - \data_f0_out[136]\, data_f0_out(135) => - \data_f0_out[135]\, data_f0_out(134) => - \data_f0_out[134]\, data_f0_out(133) => - \data_f0_out[133]\, data_f0_out(132) => - \data_f0_out[132]\, data_f0_out(131) => - \data_f0_out[131]\, data_f0_out(130) => - \data_f0_out[130]\, data_f0_out(129) => - \data_f0_out[129]\, data_f0_out(128) => - \data_f0_out[128]\, data_f0_out(127) => - \data_f0_out[127]\, data_f0_out(126) => - \data_f0_out[126]\, data_f0_out(125) => - \data_f0_out[125]\, data_f0_out(124) => - \data_f0_out[124]\, data_f0_out(123) => - \data_f0_out[123]\, data_f0_out(122) => - \data_f0_out[122]\, data_f0_out(121) => - \data_f0_out[121]\, data_f0_out(120) => - \data_f0_out[120]\, data_f0_out(119) => - \data_f0_out[119]\, data_f0_out(118) => - \data_f0_out[118]\, data_f0_out(117) => - \data_f0_out[117]\, data_f0_out(116) => - \data_f0_out[116]\, data_f0_out(115) => - \data_f0_out[115]\, data_f0_out(114) => - \data_f0_out[114]\, data_f0_out(113) => - \data_f0_out[113]\, data_f0_out(112) => - \data_f0_out[112]\, data_f0_out(111) => - \data_f0_out[111]\, data_f0_out(110) => - \data_f0_out[110]\, data_f0_out(109) => - \data_f0_out[109]\, data_f0_out(108) => - \data_f0_out[108]\, data_f0_out(107) => - \data_f0_out[107]\, data_f0_out(106) => - \data_f0_out[106]\, data_f0_out(105) => - \data_f0_out[105]\, data_f0_out(104) => - \data_f0_out[104]\, data_f0_out(103) => - \data_f0_out[103]\, data_f0_out(102) => - \data_f0_out[102]\, data_f0_out(101) => - \data_f0_out[101]\, data_f0_out(100) => - \data_f0_out[100]\, data_f0_out(99) => \data_f0_out[99]\, - data_f0_out(98) => \data_f0_out[98]\, data_f0_out(97) => - \data_f0_out[97]\, data_f0_out(96) => \data_f0_out[96]\, - data_f0_out(95) => \data_f0_out[95]\, data_f0_out(94) => - \data_f0_out[94]\, data_f0_out(93) => \data_f0_out[93]\, - data_f0_out(92) => \data_f0_out[92]\, data_f0_out(91) => - \data_f0_out[91]\, data_f0_out(90) => \data_f0_out[90]\, - data_f0_out(89) => \data_f0_out[89]\, data_f0_out(88) => - \data_f0_out[88]\, data_f0_out(87) => \data_f0_out[87]\, - data_f0_out(86) => \data_f0_out[86]\, data_f0_out(85) => - \data_f0_out[85]\, data_f0_out(84) => \data_f0_out[84]\, - data_f0_out(83) => \data_f0_out[83]\, data_f0_out(82) => - \data_f0_out[82]\, data_f0_out(81) => \data_f0_out[81]\, - data_f0_out(80) => \data_f0_out[80]\, data_f0_out(79) => - \data_f0_out[79]\, data_f0_out(78) => \data_f0_out[78]\, - data_f0_out(77) => \data_f0_out[77]\, data_f0_out(76) => - \data_f0_out[76]\, data_f0_out(75) => \data_f0_out[75]\, - data_f0_out(74) => \data_f0_out[74]\, data_f0_out(73) => - \data_f0_out[73]\, data_f0_out(72) => \data_f0_out[72]\, - data_f0_out(71) => \data_f0_out[71]\, data_f0_out(70) => - \data_f0_out[70]\, data_f0_out(69) => \data_f0_out[69]\, - data_f0_out(68) => \data_f0_out[68]\, data_f0_out(67) => - \data_f0_out[67]\, data_f0_out(66) => \data_f0_out[66]\, - data_f0_out(65) => \data_f0_out[65]\, data_f0_out(64) => - \data_f0_out[64]\, sample_f0_37 => sample_f0_37, - sample_f0_5 => sample_f0_5, sample_f0_38 => sample_f0_38, - sample_f0_6 => sample_f0_6, sample_f0_39 => sample_f0_39, - sample_f0_7 => sample_f0_7, sample_f0_40 => sample_f0_40, - sample_f0_8 => sample_f0_8, sample_f0_41 => sample_f0_41, - sample_f0_9 => sample_f0_9, sample_f0_42 => sample_f0_42, - sample_f0_10 => sample_f0_10, sample_f0_43 => - sample_f0_43, sample_f0_11 => sample_f0_11, sample_f0_61 - => sample_f0_61, sample_f0_62 => sample_f0_62, - sample_f0_63 => sample_f0_63, sample_f0_32 => - sample_f0_32, sample_f0_0 => sample_f0_0, sample_f0_33 - => sample_f0_33, sample_f0_1 => sample_f0_1, - sample_f0_34 => sample_f0_34, sample_f0_2 => sample_f0_2, - sample_f0_35 => sample_f0_35, sample_f0_3 => sample_f0_3, - sample_f0_36 => sample_f0_36, sample_f0_4 => sample_f0_4, - sample_f0_48 => sample_f0_48, sample_f0_49 => - sample_f0_49, sample_f0_50 => sample_f0_50, sample_f0_51 - => sample_f0_51, sample_f0_52 => sample_f0_52, - sample_f0_53 => sample_f0_53, sample_f0_54 => - sample_f0_54, sample_f0_55 => sample_f0_55, sample_f0_56 - => sample_f0_56, sample_f0_57 => sample_f0_57, - sample_f0_58 => sample_f0_58, sample_f0_59 => - sample_f0_59, sample_f0_60 => sample_f0_60, sample_f0_44 - => sample_f0_44, sample_f0_12 => sample_f0_12, - sample_f0_45 => sample_f0_45, sample_f0_13 => - sample_f0_13, sample_f0_46 => sample_f0_46, sample_f0_14 - => sample_f0_14, sample_f0_47 => sample_f0_47, - sample_f0_15 => sample_f0_15, nb_snapshot_param(10) => - nb_snapshot_param(10), nb_snapshot_param(9) => - nb_snapshot_param(9), nb_snapshot_param(8) => - nb_snapshot_param(8), nb_snapshot_param(7) => - nb_snapshot_param(7), nb_snapshot_param(6) => - nb_snapshot_param(6), nb_snapshot_param(5) => - nb_snapshot_param(5), nb_snapshot_param(4) => - nb_snapshot_param(4), nb_snapshot_param(3) => - nb_snapshot_param(3), nb_snapshot_param(2) => - nb_snapshot_param(2), nb_snapshot_param(1) => - nb_snapshot_param(1), nb_snapshot_param(0) => - nb_snapshot_param(0), rstn => rstn, lclk_c => lclk_c, - data_f0_out_valid => data_f0_out_valid, data_shaping_R0 - => data_shaping_R0, data_shaping_R0_0 => - data_shaping_R0_0, enable_f0 => enable_f0, - start_snapshot_f0 => start_snapshot_f0, sample_f0_val_0 - => sample_f0_val_0, burst_f0 => burst_f0); - - un7_nb_snapshot_param_more_one_I_31 : XOR2 - port map(A => N_29, B => nb_snapshot_param(6), Y => I_31_15); - - lpp_waveform_snapshot_f2 : lpp_waveform_snapshot_160_12_1 - port map(sample_f2_wdata(95) => sample_f2_wdata(95), - sample_f2_wdata(94) => sample_f2_wdata(94), - sample_f2_wdata(93) => sample_f2_wdata(93), - sample_f2_wdata(92) => sample_f2_wdata(92), - sample_f2_wdata(91) => sample_f2_wdata(91), - sample_f2_wdata(90) => sample_f2_wdata(90), - sample_f2_wdata(89) => sample_f2_wdata(89), - sample_f2_wdata(88) => sample_f2_wdata(88), - sample_f2_wdata(87) => sample_f2_wdata(87), - sample_f2_wdata(86) => sample_f2_wdata(86), - sample_f2_wdata(85) => sample_f2_wdata(85), - sample_f2_wdata(84) => sample_f2_wdata(84), - sample_f2_wdata(83) => sample_f2_wdata(83), - sample_f2_wdata(82) => sample_f2_wdata(82), - sample_f2_wdata(81) => sample_f2_wdata(81), - sample_f2_wdata(80) => sample_f2_wdata(80), - sample_f2_wdata(79) => sample_f2_wdata(79), - sample_f2_wdata(78) => sample_f2_wdata(78), - sample_f2_wdata(77) => sample_f2_wdata(77), - sample_f2_wdata(76) => sample_f2_wdata(76), - sample_f2_wdata(75) => sample_f2_wdata(75), - sample_f2_wdata(74) => sample_f2_wdata(74), - sample_f2_wdata(73) => sample_f2_wdata(73), - sample_f2_wdata(72) => sample_f2_wdata(72), - sample_f2_wdata(71) => sample_f2_wdata(71), - sample_f2_wdata(70) => sample_f2_wdata(70), - sample_f2_wdata(69) => sample_f2_wdata(69), - sample_f2_wdata(68) => sample_f2_wdata(68), - sample_f2_wdata(67) => sample_f2_wdata(67), - sample_f2_wdata(66) => sample_f2_wdata(66), - sample_f2_wdata(65) => sample_f2_wdata(65), - sample_f2_wdata(64) => sample_f2_wdata(64), - sample_f2_wdata(63) => sample_f2_wdata(63), - sample_f2_wdata(62) => sample_f2_wdata(62), - sample_f2_wdata(61) => sample_f2_wdata(61), - sample_f2_wdata(60) => sample_f2_wdata(60), - sample_f2_wdata(59) => sample_f2_wdata(59), - sample_f2_wdata(58) => sample_f2_wdata(58), - sample_f2_wdata(57) => sample_f2_wdata(57), - sample_f2_wdata(56) => sample_f2_wdata(56), - sample_f2_wdata(55) => sample_f2_wdata(55), - sample_f2_wdata(54) => sample_f2_wdata(54), - sample_f2_wdata(53) => sample_f2_wdata(53), - sample_f2_wdata(52) => sample_f2_wdata(52), - sample_f2_wdata(51) => sample_f2_wdata(51), - sample_f2_wdata(50) => sample_f2_wdata(50), - sample_f2_wdata(49) => sample_f2_wdata(49), - sample_f2_wdata(48) => sample_f2_wdata(48), - sample_f2_wdata(47) => sample_f2_wdata(47), - sample_f2_wdata(46) => sample_f2_wdata(46), - sample_f2_wdata(45) => sample_f2_wdata(45), - sample_f2_wdata(44) => sample_f2_wdata(44), - sample_f2_wdata(43) => sample_f2_wdata(43), - sample_f2_wdata(42) => sample_f2_wdata(42), - sample_f2_wdata(41) => sample_f2_wdata(41), - sample_f2_wdata(40) => sample_f2_wdata(40), - sample_f2_wdata(39) => sample_f2_wdata(39), - sample_f2_wdata(38) => sample_f2_wdata(38), - sample_f2_wdata(37) => sample_f2_wdata(37), - sample_f2_wdata(36) => sample_f2_wdata(36), - sample_f2_wdata(35) => sample_f2_wdata(35), - sample_f2_wdata(34) => sample_f2_wdata(34), - sample_f2_wdata(33) => sample_f2_wdata(33), - sample_f2_wdata(32) => sample_f2_wdata(32), - sample_f2_wdata(31) => sample_f2_wdata(31), - sample_f2_wdata(30) => sample_f2_wdata(30), - sample_f2_wdata(29) => sample_f2_wdata(29), - sample_f2_wdata(28) => sample_f2_wdata(28), - sample_f2_wdata(27) => sample_f2_wdata(27), - sample_f2_wdata(26) => sample_f2_wdata(26), - sample_f2_wdata(25) => sample_f2_wdata(25), - sample_f2_wdata(24) => sample_f2_wdata(24), - sample_f2_wdata(23) => sample_f2_wdata(23), - sample_f2_wdata(22) => sample_f2_wdata(22), - sample_f2_wdata(21) => sample_f2_wdata(21), - sample_f2_wdata(20) => sample_f2_wdata(20), - sample_f2_wdata(19) => sample_f2_wdata(19), - sample_f2_wdata(18) => sample_f2_wdata(18), - sample_f2_wdata(17) => sample_f2_wdata(17), - sample_f2_wdata(16) => sample_f2_wdata(16), - sample_f2_wdata(15) => sample_f2_wdata(15), - sample_f2_wdata(14) => sample_f2_wdata(14), - sample_f2_wdata(13) => sample_f2_wdata(13), - sample_f2_wdata(12) => sample_f2_wdata(12), - sample_f2_wdata(11) => sample_f2_wdata(11), - sample_f2_wdata(10) => sample_f2_wdata(10), - sample_f2_wdata(9) => sample_f2_wdata(9), - sample_f2_wdata(8) => sample_f2_wdata(8), - sample_f2_wdata(7) => sample_f2_wdata(7), - sample_f2_wdata(6) => sample_f2_wdata(6), - sample_f2_wdata(5) => sample_f2_wdata(5), - sample_f2_wdata(4) => sample_f2_wdata(4), - sample_f2_wdata(3) => sample_f2_wdata(3), - sample_f2_wdata(2) => sample_f2_wdata(2), - sample_f2_wdata(1) => sample_f2_wdata(1), - sample_f2_wdata(0) => sample_f2_wdata(0), - data_f2_out(159) => \data_f2_out[159]\, data_f2_out(158) - => \data_f2_out[158]\, data_f2_out(157) => - \data_f2_out[157]\, data_f2_out(156) => - \data_f2_out[156]\, data_f2_out(155) => - \data_f2_out[155]\, data_f2_out(154) => - \data_f2_out[154]\, data_f2_out(153) => - \data_f2_out[153]\, data_f2_out(152) => - \data_f2_out[152]\, data_f2_out(151) => - \data_f2_out[151]\, data_f2_out(150) => - \data_f2_out[150]\, data_f2_out(149) => - \data_f2_out[149]\, data_f2_out(148) => - \data_f2_out[148]\, data_f2_out(147) => - \data_f2_out[147]\, data_f2_out(146) => - \data_f2_out[146]\, data_f2_out(145) => - \data_f2_out[145]\, data_f2_out(144) => - \data_f2_out[144]\, data_f2_out(143) => - \data_f2_out[143]\, data_f2_out(142) => - \data_f2_out[142]\, data_f2_out(141) => - \data_f2_out[141]\, data_f2_out(140) => - \data_f2_out[140]\, data_f2_out(139) => - \data_f2_out[139]\, data_f2_out(138) => - \data_f2_out[138]\, data_f2_out(137) => - \data_f2_out[137]\, data_f2_out(136) => - \data_f2_out[136]\, data_f2_out(135) => - \data_f2_out[135]\, data_f2_out(134) => - \data_f2_out[134]\, data_f2_out(133) => - \data_f2_out[133]\, data_f2_out(132) => - \data_f2_out[132]\, data_f2_out(131) => - \data_f2_out[131]\, data_f2_out(130) => - \data_f2_out[130]\, data_f2_out(129) => - \data_f2_out[129]\, data_f2_out(128) => - \data_f2_out[128]\, data_f2_out(127) => - \data_f2_out[127]\, data_f2_out(126) => - \data_f2_out[126]\, data_f2_out(125) => - \data_f2_out[125]\, data_f2_out(124) => - \data_f2_out[124]\, data_f2_out(123) => - \data_f2_out[123]\, data_f2_out(122) => - \data_f2_out[122]\, data_f2_out(121) => - \data_f2_out[121]\, data_f2_out(120) => - \data_f2_out[120]\, data_f2_out(119) => - \data_f2_out[119]\, data_f2_out(118) => - \data_f2_out[118]\, data_f2_out(117) => - \data_f2_out[117]\, data_f2_out(116) => - \data_f2_out[116]\, data_f2_out(115) => - \data_f2_out[115]\, data_f2_out(114) => - \data_f2_out[114]\, data_f2_out(113) => - \data_f2_out[113]\, data_f2_out(112) => - \data_f2_out[112]\, data_f2_out(111) => - \data_f2_out[111]\, data_f2_out(110) => - \data_f2_out[110]\, data_f2_out(109) => - \data_f2_out[109]\, data_f2_out(108) => - \data_f2_out[108]\, data_f2_out(107) => - \data_f2_out[107]\, data_f2_out(106) => - \data_f2_out[106]\, data_f2_out(105) => - \data_f2_out[105]\, data_f2_out(104) => - \data_f2_out[104]\, data_f2_out(103) => - \data_f2_out[103]\, data_f2_out(102) => - \data_f2_out[102]\, data_f2_out(101) => - \data_f2_out[101]\, data_f2_out(100) => - \data_f2_out[100]\, data_f2_out(99) => \data_f2_out[99]\, - data_f2_out(98) => \data_f2_out[98]\, data_f2_out(97) => - \data_f2_out[97]\, data_f2_out(96) => \data_f2_out[96]\, - data_f2_out(95) => \data_f2_out[95]\, data_f2_out(94) => - \data_f2_out[94]\, data_f2_out(93) => \data_f2_out[93]\, - data_f2_out(92) => \data_f2_out[92]\, data_f2_out(91) => - \data_f2_out[91]\, data_f2_out(90) => \data_f2_out[90]\, - data_f2_out(89) => \data_f2_out[89]\, data_f2_out(88) => - \data_f2_out[88]\, data_f2_out(87) => \data_f2_out[87]\, - data_f2_out(86) => \data_f2_out[86]\, data_f2_out(85) => - \data_f2_out[85]\, data_f2_out(84) => \data_f2_out[84]\, - data_f2_out(83) => \data_f2_out[83]\, data_f2_out(82) => - \data_f2_out[82]\, data_f2_out(81) => \data_f2_out[81]\, - data_f2_out(80) => \data_f2_out[80]\, data_f2_out(79) => - \data_f2_out[79]\, data_f2_out(78) => \data_f2_out[78]\, - data_f2_out(77) => \data_f2_out[77]\, data_f2_out(76) => - \data_f2_out[76]\, data_f2_out(75) => \data_f2_out[75]\, - data_f2_out(74) => \data_f2_out[74]\, data_f2_out(73) => - \data_f2_out[73]\, data_f2_out(72) => \data_f2_out[72]\, - data_f2_out(71) => \data_f2_out[71]\, data_f2_out(70) => - \data_f2_out[70]\, data_f2_out(69) => \data_f2_out[69]\, - data_f2_out(68) => \data_f2_out[68]\, data_f2_out(67) => - \data_f2_out[67]\, data_f2_out(66) => \data_f2_out[66]\, - data_f2_out(65) => \data_f2_out[65]\, data_f2_out(64) => - \data_f2_out[64]\, nb_snapshot_param(0) => - nb_snapshot_param(0), rstn => rstn, lclk_c => lclk_c, - data_f2_out_valid => data_f2_out_valid, I_9_31 => I_9_31, - I_45_11 => I_45_11, I_52_11 => I_52_11, I_38_12 => - I_38_12, N_4 => N_4, I_56_12 => I_56_12, I_24_16 => - I_24_16, I_5_31 => I_5_31, I_20_23 => I_20_23, I_13_35 - => I_13_35, I_31_15 => I_31_15, start_snapshot_f2 => - start_snapshot_f2, sample_f2_val => sample_f2_val, - enable_f2 => enable_f2, burst_f2 => burst_f2); - - un7_nb_snapshot_param_more_one_I_12 : AND3 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), C => nb_snapshot_param(2), Y => - N_42); - - un7_nb_snapshot_param_more_one_I_5 : XOR2 - port map(A => nb_snapshot_param(0), B => - nb_snapshot_param(1), Y => I_5_31); - - un7_nb_snapshot_param_more_one_I_51 : NOR2B - port map(A => nb_snapshot_param(8), B => \DWACT_FINC_E[4]\, - Y => N_14); - - pp_waveform_dma_1 : lpp_waveform_dma - port map(addr_data_f0(31) => addr_data_f0(31), - addr_data_f0(30) => addr_data_f0(30), addr_data_f0(29) - => addr_data_f0(29), addr_data_f0(28) => - addr_data_f0(28), addr_data_f0(27) => addr_data_f0(27), - addr_data_f0(26) => addr_data_f0(26), addr_data_f0(25) - => addr_data_f0(25), addr_data_f0(24) => - addr_data_f0(24), addr_data_f0(23) => addr_data_f0(23), - addr_data_f0(22) => addr_data_f0(22), addr_data_f0(21) - => addr_data_f0(21), addr_data_f0(20) => - addr_data_f0(20), addr_data_f0(19) => addr_data_f0(19), - addr_data_f0(18) => addr_data_f0(18), addr_data_f0(17) - => addr_data_f0(17), addr_data_f0(16) => - addr_data_f0(16), addr_data_f0(15) => addr_data_f0(15), - addr_data_f0(14) => addr_data_f0(14), addr_data_f0(13) - => addr_data_f0(13), addr_data_f0(12) => - addr_data_f0(12), addr_data_f0(11) => addr_data_f0(11), - addr_data_f0(10) => addr_data_f0(10), addr_data_f0(9) => - addr_data_f0(9), addr_data_f0(8) => addr_data_f0(8), - addr_data_f0(7) => addr_data_f0(7), addr_data_f0(6) => - addr_data_f0(6), addr_data_f0(5) => addr_data_f0(5), - addr_data_f0(4) => addr_data_f0(4), addr_data_f0(3) => - addr_data_f0(3), addr_data_f0(2) => addr_data_f0(2), - addr_data_f0(1) => addr_data_f0(1), addr_data_f0(0) => - addr_data_f0(0), addr_data_f1(31) => addr_data_f1(31), - addr_data_f1(30) => addr_data_f1(30), addr_data_f1(29) - => addr_data_f1(29), addr_data_f1(28) => - addr_data_f1(28), addr_data_f1(27) => addr_data_f1(27), - addr_data_f1(26) => addr_data_f1(26), addr_data_f1(25) - => addr_data_f1(25), addr_data_f1(24) => - addr_data_f1(24), addr_data_f1(23) => addr_data_f1(23), - addr_data_f1(22) => addr_data_f1(22), addr_data_f1(21) - => addr_data_f1(21), addr_data_f1(20) => - addr_data_f1(20), addr_data_f1(19) => addr_data_f1(19), - addr_data_f1(18) => addr_data_f1(18), addr_data_f1(17) - => addr_data_f1(17), addr_data_f1(16) => - addr_data_f1(16), addr_data_f1(15) => addr_data_f1(15), - addr_data_f1(14) => addr_data_f1(14), addr_data_f1(13) - => addr_data_f1(13), addr_data_f1(12) => - addr_data_f1(12), addr_data_f1(11) => addr_data_f1(11), - addr_data_f1(10) => addr_data_f1(10), addr_data_f1(9) => - addr_data_f1(9), addr_data_f1(8) => addr_data_f1(8), - addr_data_f1(7) => addr_data_f1(7), addr_data_f1(6) => - addr_data_f1(6), addr_data_f1(5) => addr_data_f1(5), - addr_data_f1(4) => addr_data_f1(4), addr_data_f1(3) => - addr_data_f1(3), addr_data_f1(2) => addr_data_f1(2), - addr_data_f1(1) => addr_data_f1(1), addr_data_f1(0) => - addr_data_f1(0), addr_data_f2(31) => addr_data_f2(31), - addr_data_f2(30) => addr_data_f2(30), addr_data_f2(29) - => addr_data_f2(29), addr_data_f2(28) => - addr_data_f2(28), addr_data_f2(27) => addr_data_f2(27), - addr_data_f2(26) => addr_data_f2(26), addr_data_f2(25) - => addr_data_f2(25), addr_data_f2(24) => - addr_data_f2(24), addr_data_f2(23) => addr_data_f2(23), - addr_data_f2(22) => addr_data_f2(22), addr_data_f2(21) - => addr_data_f2(21), addr_data_f2(20) => - addr_data_f2(20), addr_data_f2(19) => addr_data_f2(19), - addr_data_f2(18) => addr_data_f2(18), addr_data_f2(17) - => addr_data_f2(17), addr_data_f2(16) => - addr_data_f2(16), addr_data_f2(15) => addr_data_f2(15), - addr_data_f2(14) => addr_data_f2(14), addr_data_f2(13) - => addr_data_f2(13), addr_data_f2(12) => - addr_data_f2(12), addr_data_f2(11) => addr_data_f2(11), - addr_data_f2(10) => addr_data_f2(10), addr_data_f2(9) => - addr_data_f2(9), addr_data_f2(8) => addr_data_f2(8), - addr_data_f2(7) => addr_data_f2(7), addr_data_f2(6) => - addr_data_f2(6), addr_data_f2(5) => addr_data_f2(5), - addr_data_f2(4) => addr_data_f2(4), addr_data_f2(3) => - addr_data_f2(3), addr_data_f2(2) => addr_data_f2(2), - addr_data_f2(1) => addr_data_f2(1), addr_data_f2(0) => - addr_data_f2(0), addr_data_f3(31) => addr_data_f3(31), - addr_data_f3(30) => addr_data_f3(30), addr_data_f3(29) - => addr_data_f3(29), addr_data_f3(28) => - addr_data_f3(28), addr_data_f3(27) => addr_data_f3(27), - addr_data_f3(26) => addr_data_f3(26), addr_data_f3(25) - => addr_data_f3(25), addr_data_f3(24) => - addr_data_f3(24), addr_data_f3(23) => addr_data_f3(23), - addr_data_f3(22) => addr_data_f3(22), addr_data_f3(21) - => addr_data_f3(21), addr_data_f3(20) => - addr_data_f3(20), addr_data_f3(19) => addr_data_f3(19), - addr_data_f3(18) => addr_data_f3(18), addr_data_f3(17) - => addr_data_f3(17), addr_data_f3(16) => - addr_data_f3(16), addr_data_f3(15) => addr_data_f3(15), - addr_data_f3(14) => addr_data_f3(14), addr_data_f3(13) - => addr_data_f3(13), addr_data_f3(12) => - addr_data_f3(12), addr_data_f3(11) => addr_data_f3(11), - addr_data_f3(10) => addr_data_f3(10), addr_data_f3(9) => - addr_data_f3(9), addr_data_f3(8) => addr_data_f3(8), - addr_data_f3(7) => addr_data_f3(7), addr_data_f3(6) => - addr_data_f3(6), addr_data_f3(5) => addr_data_f3(5), - addr_data_f3(4) => addr_data_f3(4), addr_data_f3(3) => - addr_data_f3(3), addr_data_f3(2) => addr_data_f3(2), - addr_data_f3(1) => addr_data_f3(1), addr_data_f3(0) => - addr_data_f3(0), status_full(3) => status_full(3), - status_full(2) => status_full(2), status_full(1) => - status_full(1), status_full(0) => status_full(0), - status_full_err(3) => status_full_err(3), - status_full_err(2) => status_full_err(2), - status_full_err(1) => status_full_err(1), - status_full_err(0) => status_full_err(0), - nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), l1_0_m(1) - => l1_0_m(1), nhmaster_1_iv_0(1) => nhmaster_1_iv_0(1), - bco_msb_1_m(1) => bco_msb_1_m(1), iosn_0(93) => - iosn_0(93), hgrant(3) => hgrant(3), - hmaster_0_0_RNIFCVH1_0(1) => hmaster_0_0_RNIFCVH1_0(1), - bco_msb_1(1) => bco_msb_1(1), haddr(31) => haddr(31), - haddr(30) => haddr(30), haddr(29) => haddr(29), haddr(28) - => haddr(28), haddr(27) => haddr(27), haddr(26) => - haddr(26), haddr(25) => haddr(25), haddr(24) => haddr(24), - haddr(23) => haddr(23), haddr(22) => haddr(22), haddr(21) - => haddr(21), haddr(20) => haddr(20), haddr(19) => - haddr(19), haddr(18) => haddr(18), haddr(17) => haddr(17), - haddr(16) => haddr(16), haddr(15) => haddr(15), haddr(14) - => haddr(14), haddr(13) => haddr(13), haddr(12) => - haddr(12), haddr(11) => haddr(11), haddr(10) => haddr(10), - haddr(9) => haddr(9), haddr(8) => haddr(8), haddr(7) => - haddr(7), haddr(6) => haddr(6), haddr(5) => haddr(5), - haddr(4) => haddr(4), haddr(3) => haddr(3), haddr(2) => - haddr(2), haddr(1) => haddr(1), haddr(0) => haddr(0), - hmaster_0(1) => hmaster_0(1), hsize(1) => hsize(1), - hsize(0) => hsize(0), nhmaster_1_i(0) => nhmaster_1_i(0), - iosn_1(93) => iosn_1(93), hresp(0) => hresp(0), - iosn_2(93) => iosn_2(93), htrans(1) => htrans(1), - htrans(0) => htrans(0), hburst(2) => hburst(2), hburst(1) - => hburst(1), hburst(0) => hburst(0), status_full_ack(3) - => status_full_ack(3), status_full_ack(2) => - status_full_ack(2), status_full_ack(1) => - status_full_ack(1), status_full_ack(0) => - status_full_ack(0), data_ren(3) => \data_ren[3]\, - data_ren(2) => \data_ren[2]\, data_ren(1) => - \data_ren[1]\, data_ren(0) => \data_ren[0]\, - ready_i_0_i_0(1) => \ready_i_0_i_0[1]\, ready_i_0_2 => - \ready_i_0[2]\, ready_i_0_0 => \ready_i_0[0]\, - ready_i_0_3 => \ready_i_0[3]\, time_ren(3) => - \time_ren[3]\, time_ren(2) => \time_ren[2]\, time_ren(1) - => \time_ren[1]\, time_ren(0) => \time_ren[0]\, - time_ren_1z => time_ren, data_ren_1z => data_ren, - m26_m1_e => m26_m1_e, m19_a1_6_i_0 => m19_a1_6_i_0, - m19_a0_6_i_0 => m19_a0_6_i_0, m19_0_N_15_i_0_li => - m19_0_N_15_i_0_li, rstoutl_RNIGJKSJO => rstoutl_RNIGJKSJO, - un1_nhmaster_0_sqmuxa_1 => un1_nhmaster_0_sqmuxa_1, - Lock_RNIU86D => Lock_RNIU86D, hbusreq_i_3 => hbusreq_i_3, - arb_1 => arb_1, un1_dmain_6 => un1_dmain_6, hwrite => - hwrite, IdlePhase => IdlePhase, un13_time_write => - un13_time_write, un5_time_write => un5_time_write, - un27_time_write => un27_time_write, un20_time_write => - un20_time_write, rstn => rstn, lclk_c => lclk_c); - - lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter - port map(wdata(31) => \wdata[31]\, wdata(30) => \wdata[30]\, - wdata(29) => \wdata[29]\, wdata(28) => \wdata[28]\, - wdata(27) => \wdata[27]\, wdata(26) => \wdata[26]\, - wdata(25) => \wdata[25]\, wdata(24) => \wdata[24]\, - wdata(23) => \wdata[23]\, wdata(22) => \wdata[22]\, - wdata(21) => \wdata[21]\, wdata(20) => \wdata[20]\, - wdata(19) => \wdata[19]\, wdata(18) => \wdata[18]\, - wdata(17) => \wdata[17]\, wdata(16) => \wdata[16]\, - wdata(15) => \wdata[15]\, wdata(14) => \wdata[14]\, - wdata(13) => \wdata[13]\, wdata(12) => \wdata[12]\, - wdata(11) => \wdata[11]\, wdata(10) => \wdata[10]\, - wdata(9) => \wdata[9]\, wdata(8) => \wdata[8]\, wdata(7) - => \wdata[7]\, wdata(6) => \wdata[6]\, wdata(5) => - \wdata[5]\, wdata(4) => \wdata[4]\, wdata(3) => - \wdata[3]\, wdata(2) => \wdata[2]\, wdata(1) => - \wdata[1]\, wdata(0) => \wdata[0]\, data_wen(3) => - \data_wen[3]\, data_wen(2) => \data_wen[2]\, data_wen(1) - => \data_wen[1]\, data_wen(0) => \data_wen[0]\, - valid_ack(3) => \valid_ack[3]\, valid_ack(2) => - \valid_ack[2]\, valid_ack(1) => \valid_ack[1]\, - valid_ack(0) => \valid_ack[0]\, time_wen(3) => - \time_wen[3]\, time_wen(2) => \time_wen[2]\, time_wen(1) - => \time_wen[1]\, time_wen(0) => \time_wen[0]\, - data_f3_out(159) => \data_f3_out[159]\, data_f3_out(158) - => \data_f3_out[158]\, data_f3_out(157) => - \data_f3_out[157]\, data_f3_out(156) => - \data_f3_out[156]\, data_f3_out(155) => - \data_f3_out[155]\, data_f3_out(154) => - \data_f3_out[154]\, data_f3_out(153) => - \data_f3_out[153]\, data_f3_out(152) => - \data_f3_out[152]\, data_f3_out(151) => - \data_f3_out[151]\, data_f3_out(150) => - \data_f3_out[150]\, data_f3_out(149) => - \data_f3_out[149]\, data_f3_out(148) => - \data_f3_out[148]\, data_f3_out(147) => - \data_f3_out[147]\, data_f3_out(146) => - \data_f3_out[146]\, data_f3_out(145) => - \data_f3_out[145]\, data_f3_out(144) => - \data_f3_out[144]\, data_f3_out(143) => - \data_f3_out[143]\, data_f3_out(142) => - \data_f3_out[142]\, data_f3_out(141) => - \data_f3_out[141]\, data_f3_out(140) => - \data_f3_out[140]\, data_f3_out(139) => - \data_f3_out[139]\, data_f3_out(138) => - \data_f3_out[138]\, data_f3_out(137) => - \data_f3_out[137]\, data_f3_out(136) => - \data_f3_out[136]\, data_f3_out(135) => - \data_f3_out[135]\, data_f3_out(134) => - \data_f3_out[134]\, data_f3_out(133) => - \data_f3_out[133]\, data_f3_out(132) => - \data_f3_out[132]\, data_f3_out(131) => - \data_f3_out[131]\, data_f3_out(130) => - \data_f3_out[130]\, data_f3_out(129) => - \data_f3_out[129]\, data_f3_out(128) => - \data_f3_out[128]\, data_f3_out(127) => - \data_f3_out[127]\, data_f3_out(126) => - \data_f3_out[126]\, data_f3_out(125) => - \data_f3_out[125]\, data_f3_out(124) => - \data_f3_out[124]\, data_f3_out(123) => - \data_f3_out[123]\, data_f3_out(122) => - \data_f3_out[122]\, data_f3_out(121) => - \data_f3_out[121]\, data_f3_out(120) => - \data_f3_out[120]\, data_f3_out(119) => - \data_f3_out[119]\, data_f3_out(118) => - \data_f3_out[118]\, data_f3_out(117) => - \data_f3_out[117]\, data_f3_out(116) => - \data_f3_out[116]\, data_f3_out(115) => - \data_f3_out[115]\, data_f3_out(114) => - \data_f3_out[114]\, data_f3_out(113) => - \data_f3_out[113]\, data_f3_out(112) => - \data_f3_out[112]\, data_f3_out(111) => - \data_f3_out[111]\, data_f3_out(110) => - \data_f3_out[110]\, data_f3_out(109) => - \data_f3_out[109]\, data_f3_out(108) => - \data_f3_out[108]\, data_f3_out(107) => - \data_f3_out[107]\, data_f3_out(106) => - \data_f3_out[106]\, data_f3_out(105) => - \data_f3_out[105]\, data_f3_out(104) => - \data_f3_out[104]\, data_f3_out(103) => - \data_f3_out[103]\, data_f3_out(102) => - \data_f3_out[102]\, data_f3_out(101) => - \data_f3_out[101]\, data_f3_out(100) => - \data_f3_out[100]\, data_f3_out(99) => \data_f3_out[99]\, - data_f3_out(98) => \data_f3_out[98]\, data_f3_out(97) => - \data_f3_out[97]\, data_f3_out(96) => \data_f3_out[96]\, - data_f3_out(95) => \data_f3_out[95]\, data_f3_out(94) => - \data_f3_out[94]\, data_f3_out(93) => \data_f3_out[93]\, - data_f3_out(92) => \data_f3_out[92]\, data_f3_out(91) => - \data_f3_out[91]\, data_f3_out(90) => \data_f3_out[90]\, - data_f3_out(89) => \data_f3_out[89]\, data_f3_out(88) => - \data_f3_out[88]\, data_f3_out(87) => \data_f3_out[87]\, - data_f3_out(86) => \data_f3_out[86]\, data_f3_out(85) => - \data_f3_out[85]\, data_f3_out(84) => \data_f3_out[84]\, - data_f3_out(83) => \data_f3_out[83]\, data_f3_out(82) => - \data_f3_out[82]\, data_f3_out(81) => \data_f3_out[81]\, - data_f3_out(80) => \data_f3_out[80]\, data_f3_out(79) => - \data_f3_out[79]\, data_f3_out(78) => \data_f3_out[78]\, - data_f3_out(77) => \data_f3_out[77]\, data_f3_out(76) => - \data_f3_out[76]\, data_f3_out(75) => \data_f3_out[75]\, - data_f3_out(74) => \data_f3_out[74]\, data_f3_out(73) => - \data_f3_out[73]\, data_f3_out(72) => \data_f3_out[72]\, - data_f3_out(71) => \data_f3_out[71]\, data_f3_out(70) => - \data_f3_out[70]\, data_f3_out(69) => \data_f3_out[69]\, - data_f3_out(68) => \data_f3_out[68]\, data_f3_out(67) => - \data_f3_out[67]\, data_f3_out(66) => \data_f3_out[66]\, - data_f3_out(65) => \data_f3_out[65]\, data_f3_out(64) => - \data_f3_out[64]\, data_f2_out(159) => \data_f2_out[159]\, - data_f2_out(158) => \data_f2_out[158]\, data_f2_out(157) - => \data_f2_out[157]\, data_f2_out(156) => - \data_f2_out[156]\, data_f2_out(155) => - \data_f2_out[155]\, data_f2_out(154) => - \data_f2_out[154]\, data_f2_out(153) => - \data_f2_out[153]\, data_f2_out(152) => - \data_f2_out[152]\, data_f2_out(151) => - \data_f2_out[151]\, data_f2_out(150) => - \data_f2_out[150]\, data_f2_out(149) => - \data_f2_out[149]\, data_f2_out(148) => - \data_f2_out[148]\, data_f2_out(147) => - \data_f2_out[147]\, data_f2_out(146) => - \data_f2_out[146]\, data_f2_out(145) => - \data_f2_out[145]\, data_f2_out(144) => - \data_f2_out[144]\, data_f2_out(143) => - \data_f2_out[143]\, data_f2_out(142) => - \data_f2_out[142]\, data_f2_out(141) => - \data_f2_out[141]\, data_f2_out(140) => - \data_f2_out[140]\, data_f2_out(139) => - \data_f2_out[139]\, data_f2_out(138) => - \data_f2_out[138]\, data_f2_out(137) => - \data_f2_out[137]\, data_f2_out(136) => - \data_f2_out[136]\, data_f2_out(135) => - \data_f2_out[135]\, data_f2_out(134) => - \data_f2_out[134]\, data_f2_out(133) => - \data_f2_out[133]\, data_f2_out(132) => - \data_f2_out[132]\, data_f2_out(131) => - \data_f2_out[131]\, data_f2_out(130) => - \data_f2_out[130]\, data_f2_out(129) => - \data_f2_out[129]\, data_f2_out(128) => - \data_f2_out[128]\, data_f2_out(127) => - \data_f2_out[127]\, data_f2_out(126) => - \data_f2_out[126]\, data_f2_out(125) => - \data_f2_out[125]\, data_f2_out(124) => - \data_f2_out[124]\, data_f2_out(123) => - \data_f2_out[123]\, data_f2_out(122) => - \data_f2_out[122]\, data_f2_out(121) => - \data_f2_out[121]\, data_f2_out(120) => - \data_f2_out[120]\, data_f2_out(119) => - \data_f2_out[119]\, data_f2_out(118) => - \data_f2_out[118]\, data_f2_out(117) => - \data_f2_out[117]\, data_f2_out(116) => - \data_f2_out[116]\, data_f2_out(115) => - \data_f2_out[115]\, data_f2_out(114) => - \data_f2_out[114]\, data_f2_out(113) => - \data_f2_out[113]\, data_f2_out(112) => - \data_f2_out[112]\, data_f2_out(111) => - \data_f2_out[111]\, data_f2_out(110) => - \data_f2_out[110]\, data_f2_out(109) => - \data_f2_out[109]\, data_f2_out(108) => - \data_f2_out[108]\, data_f2_out(107) => - \data_f2_out[107]\, data_f2_out(106) => - \data_f2_out[106]\, data_f2_out(105) => - \data_f2_out[105]\, data_f2_out(104) => - \data_f2_out[104]\, data_f2_out(103) => - \data_f2_out[103]\, data_f2_out(102) => - \data_f2_out[102]\, data_f2_out(101) => - \data_f2_out[101]\, data_f2_out(100) => - \data_f2_out[100]\, data_f2_out(99) => \data_f2_out[99]\, - data_f2_out(98) => \data_f2_out[98]\, data_f2_out(97) => - \data_f2_out[97]\, data_f2_out(96) => \data_f2_out[96]\, - data_f2_out(95) => \data_f2_out[95]\, data_f2_out(94) => - \data_f2_out[94]\, data_f2_out(93) => \data_f2_out[93]\, - data_f2_out(92) => \data_f2_out[92]\, data_f2_out(91) => - \data_f2_out[91]\, data_f2_out(90) => \data_f2_out[90]\, - data_f2_out(89) => \data_f2_out[89]\, data_f2_out(88) => - \data_f2_out[88]\, data_f2_out(87) => \data_f2_out[87]\, - data_f2_out(86) => \data_f2_out[86]\, data_f2_out(85) => - \data_f2_out[85]\, data_f2_out(84) => \data_f2_out[84]\, - data_f2_out(83) => \data_f2_out[83]\, data_f2_out(82) => - \data_f2_out[82]\, data_f2_out(81) => \data_f2_out[81]\, - data_f2_out(80) => \data_f2_out[80]\, data_f2_out(79) => - \data_f2_out[79]\, data_f2_out(78) => \data_f2_out[78]\, - data_f2_out(77) => \data_f2_out[77]\, data_f2_out(76) => - \data_f2_out[76]\, data_f2_out(75) => \data_f2_out[75]\, - data_f2_out(74) => \data_f2_out[74]\, data_f2_out(73) => - \data_f2_out[73]\, data_f2_out(72) => \data_f2_out[72]\, - data_f2_out(71) => \data_f2_out[71]\, data_f2_out(70) => - \data_f2_out[70]\, data_f2_out(69) => \data_f2_out[69]\, - data_f2_out(68) => \data_f2_out[68]\, data_f2_out(67) => - \data_f2_out[67]\, data_f2_out(66) => \data_f2_out[66]\, - data_f2_out(65) => \data_f2_out[65]\, data_f2_out(64) => - \data_f2_out[64]\, data_f1_out(159) => \data_f1_out[159]\, - data_f1_out(158) => \data_f1_out[158]\, data_f1_out(157) - => \data_f1_out[157]\, data_f1_out(156) => - \data_f1_out[156]\, data_f1_out(155) => - \data_f1_out[155]\, data_f1_out(154) => - \data_f1_out[154]\, data_f1_out(153) => - \data_f1_out[153]\, data_f1_out(152) => - \data_f1_out[152]\, data_f1_out(151) => - \data_f1_out[151]\, data_f1_out(150) => - \data_f1_out[150]\, data_f1_out(149) => - \data_f1_out[149]\, data_f1_out(148) => - \data_f1_out[148]\, data_f1_out(147) => - \data_f1_out[147]\, data_f1_out(146) => - \data_f1_out[146]\, data_f1_out(145) => - \data_f1_out[145]\, data_f1_out(144) => - \data_f1_out[144]\, data_f1_out(143) => - \data_f1_out[143]\, data_f1_out(142) => - \data_f1_out[142]\, data_f1_out(141) => - \data_f1_out[141]\, data_f1_out(140) => - \data_f1_out[140]\, data_f1_out(139) => - \data_f1_out[139]\, data_f1_out(138) => - \data_f1_out[138]\, data_f1_out(137) => - \data_f1_out[137]\, data_f1_out(136) => - \data_f1_out[136]\, data_f1_out(135) => - \data_f1_out[135]\, data_f1_out(134) => - \data_f1_out[134]\, data_f1_out(133) => - \data_f1_out[133]\, data_f1_out(132) => - \data_f1_out[132]\, data_f1_out(131) => - \data_f1_out[131]\, data_f1_out(130) => - \data_f1_out[130]\, data_f1_out(129) => - \data_f1_out[129]\, data_f1_out(128) => - \data_f1_out[128]\, data_f1_out(127) => - \data_f1_out[127]\, data_f1_out(126) => - \data_f1_out[126]\, data_f1_out(125) => - \data_f1_out[125]\, data_f1_out(124) => - \data_f1_out[124]\, data_f1_out(123) => - \data_f1_out[123]\, data_f1_out(122) => - \data_f1_out[122]\, data_f1_out(121) => - \data_f1_out[121]\, data_f1_out(120) => - \data_f1_out[120]\, data_f1_out(119) => - \data_f1_out[119]\, data_f1_out(118) => - \data_f1_out[118]\, data_f1_out(117) => - \data_f1_out[117]\, data_f1_out(116) => - \data_f1_out[116]\, data_f1_out(115) => - \data_f1_out[115]\, data_f1_out(114) => - \data_f1_out[114]\, data_f1_out(113) => - \data_f1_out[113]\, data_f1_out(112) => - \data_f1_out[112]\, data_f1_out(111) => - \data_f1_out[111]\, data_f1_out(110) => - \data_f1_out[110]\, data_f1_out(109) => - \data_f1_out[109]\, data_f1_out(108) => - \data_f1_out[108]\, data_f1_out(107) => - \data_f1_out[107]\, data_f1_out(106) => - \data_f1_out[106]\, data_f1_out(105) => - \data_f1_out[105]\, data_f1_out(104) => - \data_f1_out[104]\, data_f1_out(103) => - \data_f1_out[103]\, data_f1_out(102) => - \data_f1_out[102]\, data_f1_out(101) => - \data_f1_out[101]\, data_f1_out(100) => - \data_f1_out[100]\, data_f1_out(99) => \data_f1_out[99]\, - data_f1_out(98) => \data_f1_out[98]\, data_f1_out(97) => - \data_f1_out[97]\, data_f1_out(96) => \data_f1_out[96]\, - data_f1_out(95) => \data_f1_out[95]\, data_f1_out(94) => - \data_f1_out[94]\, data_f1_out(93) => \data_f1_out[93]\, - data_f1_out(92) => \data_f1_out[92]\, data_f1_out(91) => - \data_f1_out[91]\, data_f1_out(90) => \data_f1_out[90]\, - data_f1_out(89) => \data_f1_out[89]\, data_f1_out(88) => - \data_f1_out[88]\, data_f1_out(87) => \data_f1_out[87]\, - data_f1_out(86) => \data_f1_out[86]\, data_f1_out(85) => - \data_f1_out[85]\, data_f1_out(84) => \data_f1_out[84]\, - data_f1_out(83) => \data_f1_out[83]\, data_f1_out(82) => - \data_f1_out[82]\, data_f1_out(81) => \data_f1_out[81]\, - data_f1_out(80) => \data_f1_out[80]\, data_f1_out(79) => - \data_f1_out[79]\, data_f1_out(78) => \data_f1_out[78]\, - data_f1_out(77) => \data_f1_out[77]\, data_f1_out(76) => - \data_f1_out[76]\, data_f1_out(75) => \data_f1_out[75]\, - data_f1_out(74) => \data_f1_out[74]\, data_f1_out(73) => - \data_f1_out[73]\, data_f1_out(72) => \data_f1_out[72]\, - data_f1_out(71) => \data_f1_out[71]\, data_f1_out(70) => - \data_f1_out[70]\, data_f1_out(69) => \data_f1_out[69]\, - data_f1_out(68) => \data_f1_out[68]\, data_f1_out(67) => - \data_f1_out[67]\, data_f1_out(66) => \data_f1_out[66]\, - data_f1_out(65) => \data_f1_out[65]\, data_f1_out(64) => - \data_f1_out[64]\, data_f0_out(159) => \data_f0_out[159]\, - data_f0_out(158) => \data_f0_out[158]\, data_f0_out(157) - => \data_f0_out[157]\, data_f0_out(156) => - \data_f0_out[156]\, data_f0_out(155) => - \data_f0_out[155]\, data_f0_out(154) => - \data_f0_out[154]\, data_f0_out(153) => - \data_f0_out[153]\, data_f0_out(152) => - \data_f0_out[152]\, data_f0_out(151) => - \data_f0_out[151]\, data_f0_out(150) => - \data_f0_out[150]\, data_f0_out(149) => - \data_f0_out[149]\, data_f0_out(148) => - \data_f0_out[148]\, data_f0_out(147) => - \data_f0_out[147]\, data_f0_out(146) => - \data_f0_out[146]\, data_f0_out(145) => - \data_f0_out[145]\, data_f0_out(144) => - \data_f0_out[144]\, data_f0_out(143) => - \data_f0_out[143]\, data_f0_out(142) => - \data_f0_out[142]\, data_f0_out(141) => - \data_f0_out[141]\, data_f0_out(140) => - \data_f0_out[140]\, data_f0_out(139) => - \data_f0_out[139]\, data_f0_out(138) => - \data_f0_out[138]\, data_f0_out(137) => - \data_f0_out[137]\, data_f0_out(136) => - \data_f0_out[136]\, data_f0_out(135) => - \data_f0_out[135]\, data_f0_out(134) => - \data_f0_out[134]\, data_f0_out(133) => - \data_f0_out[133]\, data_f0_out(132) => - \data_f0_out[132]\, data_f0_out(131) => - \data_f0_out[131]\, data_f0_out(130) => - \data_f0_out[130]\, data_f0_out(129) => - \data_f0_out[129]\, data_f0_out(128) => - \data_f0_out[128]\, data_f0_out(127) => - \data_f0_out[127]\, data_f0_out(126) => - \data_f0_out[126]\, data_f0_out(125) => - \data_f0_out[125]\, data_f0_out(124) => - \data_f0_out[124]\, data_f0_out(123) => - \data_f0_out[123]\, data_f0_out(122) => - \data_f0_out[122]\, data_f0_out(121) => - \data_f0_out[121]\, data_f0_out(120) => - \data_f0_out[120]\, data_f0_out(119) => - \data_f0_out[119]\, data_f0_out(118) => - \data_f0_out[118]\, data_f0_out(117) => - \data_f0_out[117]\, data_f0_out(116) => - \data_f0_out[116]\, data_f0_out(115) => - \data_f0_out[115]\, data_f0_out(114) => - \data_f0_out[114]\, data_f0_out(113) => - \data_f0_out[113]\, data_f0_out(112) => - \data_f0_out[112]\, data_f0_out(111) => - \data_f0_out[111]\, data_f0_out(110) => - \data_f0_out[110]\, data_f0_out(109) => - \data_f0_out[109]\, data_f0_out(108) => - \data_f0_out[108]\, data_f0_out(107) => - \data_f0_out[107]\, data_f0_out(106) => - \data_f0_out[106]\, data_f0_out(105) => - \data_f0_out[105]\, data_f0_out(104) => - \data_f0_out[104]\, data_f0_out(103) => - \data_f0_out[103]\, data_f0_out(102) => - \data_f0_out[102]\, data_f0_out(101) => - \data_f0_out[101]\, data_f0_out(100) => - \data_f0_out[100]\, data_f0_out(99) => \data_f0_out[99]\, - data_f0_out(98) => \data_f0_out[98]\, data_f0_out(97) => - \data_f0_out[97]\, data_f0_out(96) => \data_f0_out[96]\, - data_f0_out(95) => \data_f0_out[95]\, data_f0_out(94) => - \data_f0_out[94]\, data_f0_out(93) => \data_f0_out[93]\, - data_f0_out(92) => \data_f0_out[92]\, data_f0_out(91) => - \data_f0_out[91]\, data_f0_out(90) => \data_f0_out[90]\, - data_f0_out(89) => \data_f0_out[89]\, data_f0_out(88) => - \data_f0_out[88]\, data_f0_out(87) => \data_f0_out[87]\, - data_f0_out(86) => \data_f0_out[86]\, data_f0_out(85) => - \data_f0_out[85]\, data_f0_out(84) => \data_f0_out[84]\, - data_f0_out(83) => \data_f0_out[83]\, data_f0_out(82) => - \data_f0_out[82]\, data_f0_out(81) => \data_f0_out[81]\, - data_f0_out(80) => \data_f0_out[80]\, data_f0_out(79) => - \data_f0_out[79]\, data_f0_out(78) => \data_f0_out[78]\, - data_f0_out(77) => \data_f0_out[77]\, data_f0_out(76) => - \data_f0_out[76]\, data_f0_out(75) => \data_f0_out[75]\, - data_f0_out(74) => \data_f0_out[74]\, data_f0_out(73) => - \data_f0_out[73]\, data_f0_out(72) => \data_f0_out[72]\, - data_f0_out(71) => \data_f0_out[71]\, data_f0_out(70) => - \data_f0_out[70]\, data_f0_out(69) => \data_f0_out[69]\, - data_f0_out(68) => \data_f0_out[68]\, data_f0_out(67) => - \data_f0_out[67]\, data_f0_out(66) => \data_f0_out[66]\, - data_f0_out(65) => \data_f0_out[65]\, data_f0_out(64) => - \data_f0_out[64]\, ready_i_0_i_0(1) => \ready_i_0_i_0[1]\, - valid_out_i(1) => \valid_out_i[1]\, ready_i_0_3 => - \ready_i_0[3]\, ready_i_0_0 => \ready_i_0[0]\, - ready_i_0_2 => \ready_i_0[2]\, valid_out_3 => - \valid_out[3]\, valid_out_0 => \valid_out[0]\, - valid_out_2 => \valid_out[2]\, rstn => rstn, lclk_c => - lclk_c); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_8_16_4 is - - port( sample_f0_0 : out std_logic; - sample_f0_1 : out std_logic; - sample_f0_2 : out std_logic; - sample_f0_3 : out std_logic; - sample_f0_4 : out std_logic; - sample_f0_5 : out std_logic; - sample_f0_6 : out std_logic; - sample_f0_7 : out std_logic; - sample_f0_8 : out std_logic; - sample_f0_9 : out std_logic; - sample_f0_10 : out std_logic; - sample_f0_11 : out std_logic; - sample_f0_12 : out std_logic; - sample_f0_13 : out std_logic; - sample_f0_14 : out std_logic; - sample_f0_15 : out std_logic; - sample_f0_32 : out std_logic; - sample_f0_33 : out std_logic; - sample_f0_34 : out std_logic; - sample_f0_35 : out std_logic; - sample_f0_36 : out std_logic; - sample_f0_37 : out std_logic; - sample_f0_38 : out std_logic; - sample_f0_39 : out std_logic; - sample_f0_40 : out std_logic; - sample_f0_41 : out std_logic; - sample_f0_42 : out std_logic; - sample_f0_43 : out std_logic; - sample_f0_44 : out std_logic; - sample_f0_45 : out std_logic; - sample_f0_46 : out std_logic; - sample_f0_47 : out std_logic; - sample_f0_48 : out std_logic; - sample_f0_49 : out std_logic; - sample_f0_50 : out std_logic; - sample_f0_51 : out std_logic; - sample_f0_52 : out std_logic; - sample_f0_53 : out std_logic; - sample_f0_54 : out std_logic; - sample_f0_55 : out std_logic; - sample_f0_56 : out std_logic; - sample_f0_57 : out std_logic; - sample_f0_58 : out std_logic; - sample_f0_59 : out std_logic; - sample_f0_60 : out std_logic; - sample_f0_61 : out std_logic; - sample_f0_62 : out std_logic; - sample_f0_63 : out std_logic; - sample_data_shaping_out_0 : in std_logic; - sample_data_shaping_out_1 : in std_logic; - sample_data_shaping_out_2 : in std_logic; - sample_data_shaping_out_3 : in std_logic; - sample_data_shaping_out_4 : in std_logic; - sample_data_shaping_out_5 : in std_logic; - sample_data_shaping_out_6 : in std_logic; - sample_data_shaping_out_7 : in std_logic; - sample_data_shaping_out_8 : in std_logic; - sample_data_shaping_out_9 : in std_logic; - sample_data_shaping_out_10 : in std_logic; - sample_data_shaping_out_11 : in std_logic; - sample_data_shaping_out_12 : in std_logic; - sample_data_shaping_out_13 : in std_logic; - sample_data_shaping_out_14 : in std_logic; - sample_data_shaping_out_15 : in std_logic; - sample_data_shaping_out_18 : in std_logic; - sample_data_shaping_out_19 : in std_logic; - sample_data_shaping_out_20 : in std_logic; - sample_data_shaping_out_21 : in std_logic; - sample_data_shaping_out_22 : in std_logic; - sample_data_shaping_out_23 : in std_logic; - sample_data_shaping_out_24 : in std_logic; - sample_data_shaping_out_25 : in std_logic; - sample_data_shaping_out_26 : in std_logic; - sample_data_shaping_out_27 : in std_logic; - sample_data_shaping_out_28 : in std_logic; - sample_data_shaping_out_29 : in std_logic; - sample_data_shaping_out_30 : in std_logic; - sample_data_shaping_out_31 : in std_logic; - sample_data_shaping_out_32 : in std_logic; - sample_data_shaping_out_33 : in std_logic; - sample_data_shaping_out_36 : in std_logic; - sample_data_shaping_out_37 : in std_logic; - sample_data_shaping_out_38 : in std_logic; - sample_data_shaping_out_39 : in std_logic; - sample_data_shaping_out_40 : in std_logic; - sample_data_shaping_out_41 : in std_logic; - sample_data_shaping_out_42 : in std_logic; - sample_data_shaping_out_43 : in std_logic; - sample_data_shaping_out_44 : in std_logic; - sample_data_shaping_out_45 : in std_logic; - sample_data_shaping_out_46 : in std_logic; - sample_data_shaping_out_47 : in std_logic; - sample_data_shaping_out_48 : in std_logic; - sample_data_shaping_out_49 : in std_logic; - sample_data_shaping_out_50 : in std_logic; - sample_data_shaping_out_51 : in std_logic; - sample_data_shaping_out_54 : in std_logic; - sample_data_shaping_out_55 : in std_logic; - sample_data_shaping_out_56 : in std_logic; - sample_data_shaping_out_57 : in std_logic; - sample_data_shaping_out_58 : in std_logic; - sample_data_shaping_out_59 : in std_logic; - sample_data_shaping_out_60 : in std_logic; - sample_data_shaping_out_61 : in std_logic; - sample_data_shaping_out_62 : in std_logic; - sample_data_shaping_out_63 : in std_logic; - sample_data_shaping_out_64 : in std_logic; - sample_data_shaping_out_65 : in std_logic; - sample_data_shaping_out_66 : in std_logic; - sample_data_shaping_out_67 : in std_logic; - sample_data_shaping_out_68 : in std_logic; - sample_data_shaping_out_69 : in std_logic; - sample_data_shaping_out_90 : in std_logic; - sample_data_shaping_out_91 : in std_logic; - sample_data_shaping_out_92 : in std_logic; - sample_data_shaping_out_93 : in std_logic; - sample_data_shaping_out_94 : in std_logic; - sample_data_shaping_out_95 : in std_logic; - sample_data_shaping_out_96 : in std_logic; - sample_data_shaping_out_97 : in std_logic; - sample_data_shaping_out_98 : in std_logic; - sample_data_shaping_out_99 : in std_logic; - sample_data_shaping_out_100 : in std_logic; - sample_data_shaping_out_101 : in std_logic; - sample_data_shaping_out_102 : in std_logic; - sample_data_shaping_out_103 : in std_logic; - sample_data_shaping_out_104 : in std_logic; - sample_data_shaping_out_105 : in std_logic; - sample_data_shaping_out_108 : in std_logic; - sample_data_shaping_out_109 : in std_logic; - sample_data_shaping_out_110 : in std_logic; - sample_data_shaping_out_111 : in std_logic; - sample_data_shaping_out_112 : in std_logic; - sample_data_shaping_out_113 : in std_logic; - sample_data_shaping_out_114 : in std_logic; - sample_data_shaping_out_115 : in std_logic; - sample_data_shaping_out_116 : in std_logic; - sample_data_shaping_out_117 : in std_logic; - sample_data_shaping_out_118 : in std_logic; - sample_data_shaping_out_119 : in std_logic; - sample_data_shaping_out_120 : in std_logic; - sample_data_shaping_out_121 : in std_logic; - sample_data_shaping_out_122 : in std_logic; - sample_data_shaping_out_123 : in std_logic; - sample_data_shaping_out_126 : in std_logic; - sample_data_shaping_out_127 : in std_logic; - sample_data_shaping_out_128 : in std_logic; - sample_data_shaping_out_129 : in std_logic; - sample_data_shaping_out_130 : in std_logic; - sample_data_shaping_out_131 : in std_logic; - sample_data_shaping_out_132 : in std_logic; - sample_data_shaping_out_133 : in std_logic; - sample_data_shaping_out_134 : in std_logic; - sample_data_shaping_out_135 : in std_logic; - sample_data_shaping_out_136 : in std_logic; - sample_data_shaping_out_137 : in std_logic; - sample_data_shaping_out_138 : in std_logic; - sample_data_shaping_out_139 : in std_logic; - sample_data_shaping_out_140 : in std_logic; - sample_data_shaping_out_141 : in std_logic; - sample_f0_wdata_95 : out std_logic; - sample_f0_wdata_94 : out std_logic; - sample_f0_wdata_93 : out std_logic; - sample_f0_wdata_92 : out std_logic; - sample_f0_wdata_91 : out std_logic; - sample_f0_wdata_90 : out std_logic; - sample_f0_wdata_89 : out std_logic; - sample_f0_wdata_88 : out std_logic; - sample_f0_wdata_87 : out std_logic; - sample_f0_wdata_86 : out std_logic; - sample_f0_wdata_85 : out std_logic; - sample_f0_wdata_84 : out std_logic; - sample_f0_wdata_83 : out std_logic; - sample_f0_wdata_82 : out std_logic; - sample_f0_wdata_81 : out std_logic; - sample_f0_wdata_80 : out std_logic; - sample_f0_wdata_79 : out std_logic; - sample_f0_wdata_78 : out std_logic; - sample_f0_wdata_77 : out std_logic; - sample_f0_wdata_76 : out std_logic; - sample_f0_wdata_75 : out std_logic; - sample_f0_wdata_74 : out std_logic; - sample_f0_wdata_73 : out std_logic; - sample_f0_wdata_72 : out std_logic; - sample_f0_wdata_71 : out std_logic; - sample_f0_wdata_70 : out std_logic; - sample_f0_wdata_69 : out std_logic; - sample_f0_wdata_68 : out std_logic; - sample_f0_wdata_67 : out std_logic; - sample_f0_wdata_66 : out std_logic; - sample_f0_wdata_65 : out std_logic; - sample_f0_wdata_64 : out std_logic; - sample_f0_wdata_63 : out std_logic; - sample_f0_wdata_62 : out std_logic; - sample_f0_wdata_61 : out std_logic; - sample_f0_wdata_60 : out std_logic; - sample_f0_wdata_59 : out std_logic; - sample_f0_wdata_58 : out std_logic; - sample_f0_wdata_57 : out std_logic; - sample_f0_wdata_56 : out std_logic; - sample_f0_wdata_55 : out std_logic; - sample_f0_wdata_54 : out std_logic; - sample_f0_wdata_53 : out std_logic; - sample_f0_wdata_52 : out std_logic; - sample_f0_wdata_51 : out std_logic; - sample_f0_wdata_50 : out std_logic; - sample_f0_wdata_49 : out std_logic; - sample_f0_wdata_48 : out std_logic; - sample_f0_wdata_15 : out std_logic; - sample_f0_wdata_14 : out std_logic; - sample_f0_wdata_13 : out std_logic; - sample_f0_wdata_12 : out std_logic; - sample_f0_wdata_11 : out std_logic; - sample_f0_wdata_10 : out std_logic; - sample_f0_wdata_9 : out std_logic; - sample_f0_wdata_8 : out std_logic; - sample_f0_wdata_7 : out std_logic; - sample_f0_wdata_6 : out std_logic; - sample_f0_wdata_5 : out std_logic; - sample_f0_wdata_4 : out std_logic; - sample_f0_wdata_3 : out std_logic; - sample_f0_wdata_2 : out std_logic; - sample_f0_wdata_1 : out std_logic; - sample_f0_wdata_0 : out std_logic; - sample_data_shaping_out_val : in std_logic; - sample_f0_val : out std_logic; - sample_data_shaping_out_val_0 : in std_logic; - sample_f0_val_0 : out std_logic; - sample_f0_val_1 : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_f0_val_2 : out std_logic - ); - -end Downsampling_8_16_4; - -architecture DEF_ARCH of Downsampling_8_16_4 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal sample_out_val_19, sample_out_0_sqmuxa_3, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1, - sample_out_0_sqmuxa_0, un14_sample_in_val_i_0_0, - un14_sample_in_val_23, un14_sample_in_val_22, - un14_sample_in_val_24, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un14_sample_in_val_15, - un14_sample_in_val_14, un14_sample_in_val_20, - un14_sample_in_val_9, un14_sample_in_val_8, - un14_sample_in_val_19, un14_sample_in_val_5, - un14_sample_in_val_4, un14_sample_in_val_17, - un14_sample_in_val_13, \counter[24]_net_1\, - un14_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un14_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un14_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un14_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un14_sample_in_val_i_0, - sample_out_0_sqmuxa, \counter_4[0]\, I_9_10, - \counter_4[1]\, I_13_14, \counter_4[2]\, I_20_10, - \counter_4[3]\, I_24_11, \counter_4[4]\, I_31_10, - \counter_4[5]\, I_38_7, \counter_4[6]\, I_45_6, - \counter_4[7]\, I_52_6, \counter_4[8]\, I_56_7, - \counter_4[9]\, I_66_7, \counter_4[10]\, I_73_5, - \counter_4[11]\, I_77_5, \counter_4[12]\, I_84_5, - \counter_4[13]\, I_91_5, \counter_4[14]\, I_98_5, - \counter_4[15]\, I_105_5, \counter_4[16]\, I_115_5, - \counter_4[17]\, I_122_5, \counter_4[18]\, I_129_5, - \counter_4[19]\, I_136_4, \counter_4[20]\, I_143_4, - \counter_4[21]\, I_156_4, \counter_4[22]\, I_166_4, - \counter_4[23]\, I_173_4, \counter_4[24]\, I_186_4, - \counter_4[25]\, I_196_4, I_4, I_5_10, N_4, - \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[19]_net_1\); - - \sample_out[125]\ : DFN1E1 - port map(D => sample_data_shaping_out_139, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_2); - - \sample_out[102]\ : DFN1E1 - port map(D => sample_data_shaping_out_114, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_54); - - \sample_out[122]\ : DFN1E1 - port map(D => sample_data_shaping_out_136, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_5); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_data_shaping_out_24, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_73); - - \sample_out[101]\ : DFN1E1 - port map(D => sample_data_shaping_out_113, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_53); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_data_shaping_out_22, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_75); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_data_shaping_out_13, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_82); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_data_shaping_out_1, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_94); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_data_shaping_out_21, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_76); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_data_shaping_out_67, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_13); - - \sample_out[121]\ : DFN1E1 - port map(D => sample_data_shaping_out_135, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_6); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_data_shaping_out_42, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_57); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_data_shaping_out_105, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_47); - - \counter_RNO[11]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_66_7, Y => - \counter_4[9]\); - - \sample_out[104]\ : DFN1E1 - port map(D => sample_data_shaping_out_116, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_56); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_data_shaping_out_38, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_61); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4); - - \sample_out[124]\ : DFN1E1 - port map(D => sample_data_shaping_out_138, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_3); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val_0, Q => - \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \counter_RNIGPFA3_2[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa_3); - - \sample_out[97]\ : DFN1E1 - port map(D => sample_data_shaping_out_109, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_49); - - \counter_RNIRVM2[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un14_sample_in_val_13); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_4); - - \sample_out[108]\ : DFN1E1 - port map(D => sample_data_shaping_out_120, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_60); - - \counter_RNO[15]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_91_5, Y => - \counter_4[13]\); - - \counter_RNI201K[27]\ : NOR3A - port map(A => un14_sample_in_val_1, B => - \counter[11]_net_1\, C => \counter[27]_net_1\, Y => - un14_sample_in_val_14); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_data_shaping_out_57, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_3); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_data_shaping_out_62, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_8); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_data_shaping_out_0, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_95); - - \counter_RNO[7]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_38_7, Y => - \counter_4[5]\); - - \counter[6]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_14); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_data_shaping_out_91, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_33); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_data_shaping_out_96, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_38); - - \counter_RNIGPFA3[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa_1); - - \counter[3]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => \counter_4[0]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_5); - - \counter_RNO[8]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_45_6, Y => - \counter_4[6]\); - - \counter_RNO[13]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_77_5, Y => - \counter_4[11]\); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_6); - - \counter_RNICMR73_0[4]\ : OR3C - port map(A => un14_sample_in_val_23, B => - un14_sample_in_val_22, C => un14_sample_in_val_24, Y => - un14_sample_in_val_i_0); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_data_shaping_out_12, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_83); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_data_shaping_out_10, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_85); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_data_shaping_out_49, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_50); - - \counter_RNO[12]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_73_5, Y => - \counter_4[10]\); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_data_shaping_out_37, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_62); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_data_shaping_out_43, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_56); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[17]_net_1\); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_10); - - \counter_RNIUCC6[7]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un14_sample_in_val_4); - - \counter_RNIAKHP[4]\ : NOR3C - port map(A => un14_sample_in_val_9, B => - un14_sample_in_val_8, C => un14_sample_in_val_19, Y => - un14_sample_in_val_23); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val_0, Q => - \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_data_shaping_out_5, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_90); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_data_shaping_out_51, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_48); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[13]_net_1\); - - \counter_RNIGPFA3_1[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa_0); - - \counter_RNI2AP01[7]\ : NOR3C - port map(A => un14_sample_in_val_5, B => - un14_sample_in_val_4, C => un14_sample_in_val_17, Y => - un14_sample_in_val_22); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - \sample_out[115]\ : DFN1E1 - port map(D => sample_data_shaping_out_129, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_data_shaping_out_23, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_74); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_data_shaping_out_28, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_69); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_data_shaping_out_2, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_93); - - \sample_out[98]\ : DFN1E1 - port map(D => sample_data_shaping_out_110, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_50); - - \sample_out[112]\ : DFN1E1 - port map(D => sample_data_shaping_out_126, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_15); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[25]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[27]_net_1\); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_data_shaping_out_104, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_46); - - \sample_out[111]\ : DFN1E1 - port map(D => sample_data_shaping_out_123, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_63); - - \counter_RNIVV0K[12]\ : NOR3A - port map(A => un14_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un14_sample_in_val_19); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_4); - - \counter_RNO[17]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_105_5, Y => - \counter_4[15]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \counter_RNIQO29[24]\ : NOR3A - port map(A => un14_sample_in_val_13, B => - \counter[1]_net_1\, C => \counter[24]_net_1\, Y => - un14_sample_in_val_20); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_data_shaping_out_61, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_7); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \sample_out[114]\ : DFN1E1 - port map(D => sample_data_shaping_out_128, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_4); - - \counter_RNI0OGD1[20]\ : NOR3C - port map(A => un14_sample_in_val_15, B => - un14_sample_in_val_14, C => un14_sample_in_val_20, Y => - un14_sample_in_val_24); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_data_shaping_out_36, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_63); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_5); - - \sample_out[118]\ : DFN1E1 - port map(D => sample_data_shaping_out_132, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_9); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_data_shaping_out_63, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_9); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_data_shaping_out_32, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_65); - - \counter_RNO[14]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_84_5, Y => - \counter_4[12]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_data_shaping_out_95, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_37); - - \counter[1]\ : DFN1E1C0 - port map(D => I_5_10, CLK => lclk_c, CLR => rstn, E => - sample_data_shaping_out_val_0, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_186_4, Y => - \counter_4[24]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_data_shaping_out_4, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_91); - - \counter_RNO[5]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_24_11, Y => - \counter_4[3]\); - - \sample_out[103]\ : DFN1E1 - port map(D => sample_data_shaping_out_115, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_55); - - \sample_out[100]\ : DFN1E1 - port map(D => sample_data_shaping_out_112, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_52); - - \counter_RNIVD0A[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un14_sample_in_val_5); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[25]_net_1\); - - \sample_out[123]\ : DFN1E1 - port map(D => sample_data_shaping_out_137, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_4); - - \sample_out[120]\ : DFN1E1 - port map(D => sample_data_shaping_out_134, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_7); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_19, CLK => lclk_c, CLR => rstn, - Q => sample_f0_val); - - \counter_RNO[3]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_13_14, Y => - \counter_4[1]\); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_data_shaping_out_97, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_39); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_5); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_4); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_data_shaping_out_54, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_0); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_7); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_data_shaping_out_103, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_45); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_data_shaping_out_11, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_84); - - \sample_out[99]\ : DFN1E1 - port map(D => sample_data_shaping_out_111, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_51); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_data_shaping_out_18, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_79); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_data_shaping_out_48, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_51); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNO[10]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_56_7, Y => - \counter_4[8]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_10); - - \counter_RNO[21]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_136_4, Y => - \counter_4[19]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_10); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_data_shaping_out_27, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_70); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_7); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_173_4, Y => - \counter_4[23]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_10); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_5); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_data_shaping_out_29, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_68); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNO[6]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_31_10, Y => - \counter_4[4]\); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - \counter_RNICMR73[4]\ : OR3C - port map(A => un14_sample_in_val_23, B => - un14_sample_in_val_22, C => un14_sample_in_val_24, Y => - un14_sample_in_val_i_0_0); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_4); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - sample_out_val_2 : DFN1C0 - port map(D => sample_out_val_19, CLK => lclk_c, CLR => rstn, - Q => sample_f0_val_2); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_data_shaping_out_64, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_10); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_7); - - \counter_RNO[23]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_156_4, Y => - \counter_4[21]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_data_shaping_out_60, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_6); - - \counter_RNIGPFA3_0[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa_2); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_data_shaping_out_47, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_52); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_data_shaping_out_55, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_1); - - \counter_RNI1TB6[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un14_sample_in_val_7); - - sample_out_val_0 : DFN1C0 - port map(D => sample_out_val_19, CLK => lclk_c, CLR => rstn, - Q => sample_f0_val_0); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_6); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_11); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_data_shaping_out_102, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_44); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_4); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_data_shaping_out_98, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_40); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_data_shaping_out_100, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_42); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_5); - - \counter_RNO[22]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_143_4, Y => - \counter_4[20]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_data_shaping_out_33, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_64); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_data_shaping_out_40, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_59); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_data_shaping_out_94, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_36); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_data_shaping_out_69, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_15); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_data_shaping_out_15, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_80); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_5); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val, Q => - \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[113]\ : DFN1E1 - port map(D => sample_data_shaping_out_127, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_14); - - \sample_out[110]\ : DFN1E1 - port map(D => sample_data_shaping_out_122, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_62); - - \counter_RNO[4]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_20_10, Y => - \counter_4[2]\); - - \counter_RNI59C6[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un14_sample_in_val_3); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \sample_out[106]\ : DFN1E1 - port map(D => sample_data_shaping_out_118, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_58); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_5); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_data_shaping_out_19, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_78); - - \sample_out[107]\ : DFN1E1 - port map(D => sample_data_shaping_out_119, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_59); - - \counter_RNO[18]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_115_5, Y => - \counter_4[16]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[126]\ : DFN1E1 - port map(D => sample_data_shaping_out_140, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_1); - - \sample_out[127]\ : DFN1E1 - port map(D => sample_data_shaping_out_141, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_0); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_data_shaping_out_59, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_5); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_data_shaping_out_30, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_67); - - \counter_RNO[27]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_196_4, Y => - \counter_4[25]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_data_shaping_out_65, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_11); - - \sample_out[109]\ : DFN1E1 - port map(D => sample_data_shaping_out_121, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_61); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_data_shaping_out_26, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_71); - - \counter_RNIMT393[4]\ : NOR2A - port map(A => sample_data_shaping_out_val_0, B => - un14_sample_in_val_i_0_0, Y => sample_out_val_19); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_data_shaping_out_46, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_53); - - \counter_RNI4VCG[20]\ : NOR3A - port map(A => un14_sample_in_val_3, B => - \counter[23]_net_1\, C => \counter[20]_net_1\, Y => - un14_sample_in_val_15); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_data_shaping_out_44, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_55); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_data_shaping_out_93, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_35); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_data_shaping_out_99, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_41); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_166_4, Y => - \counter_4[22]\); - - \counter_RNI5FCG[19]\ : NOR3A - port map(A => un14_sample_in_val_7, B => - \counter[22]_net_1\, C => \counter[19]_net_1\, Y => - un14_sample_in_val_17); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[7]_net_1\); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_5); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_data_shaping_out_6, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_89); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - \counter_RNI2SN2[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un14_sample_in_val_8); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_data_shaping_out_68, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_14); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_data_shaping_out_66, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_12); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_data_shaping_out_39, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_60); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_data_shaping_out_101, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_43); - - \counter_RNI2I0A[18]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un14_sample_in_val_11); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - \sample_out[96]\ : DFN1E1 - port map(D => sample_data_shaping_out_108, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_48); - - \counter_RNIGPFA3_3[4]\ : NOR2B - port map(A => sample_out_val_19, B => rstn, Y => - sample_out_0_sqmuxa); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - \counter_RNI1E0A[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un14_sample_in_val_1); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - sample_out_val_1 : DFN1C0 - port map(D => sample_out_val_19, CLK => lclk_c, CLR => rstn, - Q => sample_f0_val_1); - - \counter_RNO[20]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_129_5, Y => - \counter_4[18]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_data_shaping_out_41, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_58); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_data_shaping_out_25, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_72); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_data_shaping_out_58, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_4); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_data_shaping_out_31, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_66); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_data_shaping_out_56, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_2); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_data_shaping_out_20, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_77); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_data_shaping_out_9, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_wdata_86); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_data_shaping_out_7, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_wdata_88); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_data_shaping_out_14, CLK => lclk_c, E - => sample_out_0_sqmuxa_1, Q => sample_f0_wdata_81); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_data_shaping_out_92, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_34); - - \counter_RNO[2]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_9_10, Y => - \counter_4[0]\); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[9]_net_1\); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_data_shaping_out_90, CLK => lclk_c, E - => sample_out_0_sqmuxa_3, Q => sample_f0_32); - - \counter_RNO[19]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_122_5, Y => - \counter_4[17]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNO[9]\ : NOR2B - port map(A => un14_sample_in_val_i_0_0, B => I_52_6, Y => - \counter_4[7]\); - - \counter_RNI9OO2[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un14_sample_in_val_9); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => lclk_c, CLR => rstn, E - => sample_data_shaping_out_val, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_5); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_4); - - \sample_out[116]\ : DFN1E1 - port map(D => sample_data_shaping_out_130, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_11); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => lclk_c, CLR => rstn, - E => sample_data_shaping_out_val_0, Q => - \counter[18]_net_1\); - - \sample_out[117]\ : DFN1E1 - port map(D => sample_data_shaping_out_131, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_10); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_data_shaping_out_8, CLK => lclk_c, E - => sample_out_0_sqmuxa, Q => sample_f0_wdata_87); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_data_shaping_out_45, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_54); - - \counter_RNO[16]\ : NOR2B - port map(A => un14_sample_in_val_i_0, B => I_98_5, Y => - \counter_4[14]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4, CLK => lclk_c, CLR => rstn, E => - sample_data_shaping_out_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_data_shaping_out_50, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_49); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_data_shaping_out_3, CLK => lclk_c, E - => sample_out_0_sqmuxa_2, Q => sample_f0_wdata_92); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - \sample_out[105]\ : DFN1E1 - port map(D => sample_data_shaping_out_117, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_57); - - \sample_out[119]\ : DFN1E1 - port map(D => sample_data_shaping_out_133, CLK => lclk_c, E - => sample_out_0_sqmuxa_0, Q => sample_f0_wdata_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Downsampling_8_16_6 is - - port( sample_f0_0 : in std_logic; - sample_f0_1 : in std_logic; - sample_f0_2 : in std_logic; - sample_f0_3 : in std_logic; - sample_f0_4 : in std_logic; - sample_f0_5 : in std_logic; - sample_f0_6 : in std_logic; - sample_f0_7 : in std_logic; - sample_f0_8 : in std_logic; - sample_f0_9 : in std_logic; - sample_f0_10 : in std_logic; - sample_f0_11 : in std_logic; - sample_f0_12 : in std_logic; - sample_f0_13 : in std_logic; - sample_f0_14 : in std_logic; - sample_f0_15 : in std_logic; - sample_f0_32 : in std_logic; - sample_f0_33 : in std_logic; - sample_f0_34 : in std_logic; - sample_f0_35 : in std_logic; - sample_f0_36 : in std_logic; - sample_f0_37 : in std_logic; - sample_f0_38 : in std_logic; - sample_f0_39 : in std_logic; - sample_f0_40 : in std_logic; - sample_f0_41 : in std_logic; - sample_f0_42 : in std_logic; - sample_f0_43 : in std_logic; - sample_f0_44 : in std_logic; - sample_f0_45 : in std_logic; - sample_f0_46 : in std_logic; - sample_f0_47 : in std_logic; - sample_f0_48 : in std_logic; - sample_f0_49 : in std_logic; - sample_f0_50 : in std_logic; - sample_f0_51 : in std_logic; - sample_f0_52 : in std_logic; - sample_f0_53 : in std_logic; - sample_f0_54 : in std_logic; - sample_f0_55 : in std_logic; - sample_f0_56 : in std_logic; - sample_f0_57 : in std_logic; - sample_f0_58 : in std_logic; - sample_f0_59 : in std_logic; - sample_f0_60 : in std_logic; - sample_f0_61 : in std_logic; - sample_f0_62 : in std_logic; - sample_f0_63 : in std_logic; - sample_f1_0 : out std_logic; - sample_f1_1 : out std_logic; - sample_f1_2 : out std_logic; - sample_f1_3 : out std_logic; - sample_f1_4 : out std_logic; - sample_f1_5 : out std_logic; - sample_f1_6 : out std_logic; - sample_f1_7 : out std_logic; - sample_f1_8 : out std_logic; - sample_f1_9 : out std_logic; - sample_f1_10 : out std_logic; - sample_f1_11 : out std_logic; - sample_f1_12 : out std_logic; - sample_f1_13 : out std_logic; - sample_f1_14 : out std_logic; - sample_f1_15 : out std_logic; - sample_f1_32 : out std_logic; - sample_f1_33 : out std_logic; - sample_f1_34 : out std_logic; - sample_f1_35 : out std_logic; - sample_f1_36 : out std_logic; - sample_f1_37 : out std_logic; - sample_f1_38 : out std_logic; - sample_f1_39 : out std_logic; - sample_f1_40 : out std_logic; - sample_f1_41 : out std_logic; - sample_f1_42 : out std_logic; - sample_f1_43 : out std_logic; - sample_f1_44 : out std_logic; - sample_f1_45 : out std_logic; - sample_f1_46 : out std_logic; - sample_f1_47 : out std_logic; - sample_f1_48 : out std_logic; - sample_f1_49 : out std_logic; - sample_f1_50 : out std_logic; - sample_f1_51 : out std_logic; - sample_f1_52 : out std_logic; - sample_f1_53 : out std_logic; - sample_f1_54 : out std_logic; - sample_f1_55 : out std_logic; - sample_f1_56 : out std_logic; - sample_f1_57 : out std_logic; - sample_f1_58 : out std_logic; - sample_f1_59 : out std_logic; - sample_f1_60 : out std_logic; - sample_f1_61 : out std_logic; - sample_f1_62 : out std_logic; - sample_f1_63 : out std_logic; - sample_f0_wdata_95 : in std_logic; - sample_f0_wdata_94 : in std_logic; - sample_f0_wdata_93 : in std_logic; - sample_f0_wdata_92 : in std_logic; - sample_f0_wdata_91 : in std_logic; - sample_f0_wdata_90 : in std_logic; - sample_f0_wdata_89 : in std_logic; - sample_f0_wdata_88 : in std_logic; - sample_f0_wdata_87 : in std_logic; - sample_f0_wdata_86 : in std_logic; - sample_f0_wdata_85 : in std_logic; - sample_f0_wdata_84 : in std_logic; - sample_f0_wdata_83 : in std_logic; - sample_f0_wdata_82 : in std_logic; - sample_f0_wdata_81 : in std_logic; - sample_f0_wdata_80 : in std_logic; - sample_f0_wdata_79 : in std_logic; - sample_f0_wdata_78 : in std_logic; - sample_f0_wdata_77 : in std_logic; - sample_f0_wdata_76 : in std_logic; - sample_f0_wdata_75 : in std_logic; - sample_f0_wdata_74 : in std_logic; - sample_f0_wdata_73 : in std_logic; - sample_f0_wdata_72 : in std_logic; - sample_f0_wdata_71 : in std_logic; - sample_f0_wdata_70 : in std_logic; - sample_f0_wdata_69 : in std_logic; - sample_f0_wdata_68 : in std_logic; - sample_f0_wdata_67 : in std_logic; - sample_f0_wdata_66 : in std_logic; - sample_f0_wdata_65 : in std_logic; - sample_f0_wdata_64 : in std_logic; - sample_f0_wdata_63 : in std_logic; - sample_f0_wdata_62 : in std_logic; - sample_f0_wdata_61 : in std_logic; - sample_f0_wdata_60 : in std_logic; - sample_f0_wdata_59 : in std_logic; - sample_f0_wdata_58 : in std_logic; - sample_f0_wdata_57 : in std_logic; - sample_f0_wdata_56 : in std_logic; - sample_f0_wdata_55 : in std_logic; - sample_f0_wdata_54 : in std_logic; - sample_f0_wdata_53 : in std_logic; - sample_f0_wdata_52 : in std_logic; - sample_f0_wdata_51 : in std_logic; - sample_f0_wdata_50 : in std_logic; - sample_f0_wdata_49 : in std_logic; - sample_f0_wdata_48 : in std_logic; - sample_f0_wdata_15 : in std_logic; - sample_f0_wdata_14 : in std_logic; - sample_f0_wdata_13 : in std_logic; - sample_f0_wdata_12 : in std_logic; - sample_f0_wdata_11 : in std_logic; - sample_f0_wdata_10 : in std_logic; - sample_f0_wdata_9 : in std_logic; - sample_f0_wdata_8 : in std_logic; - sample_f0_wdata_7 : in std_logic; - sample_f0_wdata_6 : in std_logic; - sample_f0_wdata_5 : in std_logic; - sample_f0_wdata_4 : in std_logic; - sample_f0_wdata_3 : in std_logic; - sample_f0_wdata_2 : in std_logic; - sample_f0_wdata_1 : in std_logic; - sample_f0_wdata_0 : in std_logic; - sample_f1_wdata_95 : out std_logic; - sample_f1_wdata_94 : out std_logic; - sample_f1_wdata_93 : out std_logic; - sample_f1_wdata_92 : out std_logic; - sample_f1_wdata_91 : out std_logic; - sample_f1_wdata_90 : out std_logic; - sample_f1_wdata_89 : out std_logic; - sample_f1_wdata_88 : out std_logic; - sample_f1_wdata_87 : out std_logic; - sample_f1_wdata_86 : out std_logic; - sample_f1_wdata_85 : out std_logic; - sample_f1_wdata_84 : out std_logic; - sample_f1_wdata_83 : out std_logic; - sample_f1_wdata_82 : out std_logic; - sample_f1_wdata_81 : out std_logic; - sample_f1_wdata_80 : out std_logic; - sample_f1_wdata_79 : out std_logic; - sample_f1_wdata_78 : out std_logic; - sample_f1_wdata_77 : out std_logic; - sample_f1_wdata_76 : out std_logic; - sample_f1_wdata_75 : out std_logic; - sample_f1_wdata_74 : out std_logic; - sample_f1_wdata_73 : out std_logic; - sample_f1_wdata_72 : out std_logic; - sample_f1_wdata_71 : out std_logic; - sample_f1_wdata_70 : out std_logic; - sample_f1_wdata_69 : out std_logic; - sample_f1_wdata_68 : out std_logic; - sample_f1_wdata_67 : out std_logic; - sample_f1_wdata_66 : out std_logic; - sample_f1_wdata_65 : out std_logic; - sample_f1_wdata_64 : out std_logic; - sample_f1_wdata_63 : out std_logic; - sample_f1_wdata_62 : out std_logic; - sample_f1_wdata_61 : out std_logic; - sample_f1_wdata_60 : out std_logic; - sample_f1_wdata_59 : out std_logic; - sample_f1_wdata_58 : out std_logic; - sample_f1_wdata_57 : out std_logic; - sample_f1_wdata_56 : out std_logic; - sample_f1_wdata_55 : out std_logic; - sample_f1_wdata_54 : out std_logic; - sample_f1_wdata_53 : out std_logic; - sample_f1_wdata_52 : out std_logic; - sample_f1_wdata_51 : out std_logic; - sample_f1_wdata_50 : out std_logic; - sample_f1_wdata_49 : out std_logic; - sample_f1_wdata_48 : out std_logic; - sample_f1_wdata_15 : out std_logic; - sample_f1_wdata_14 : out std_logic; - sample_f1_wdata_13 : out std_logic; - sample_f1_wdata_12 : out std_logic; - sample_f1_wdata_11 : out std_logic; - sample_f1_wdata_10 : out std_logic; - sample_f1_wdata_9 : out std_logic; - sample_f1_wdata_8 : out std_logic; - sample_f1_wdata_7 : out std_logic; - sample_f1_wdata_6 : out std_logic; - sample_f1_wdata_5 : out std_logic; - sample_f1_wdata_4 : out std_logic; - sample_f1_wdata_3 : out std_logic; - sample_f1_wdata_2 : out std_logic; - sample_f1_wdata_1 : out std_logic; - sample_f1_wdata_0 : out std_logic; - sample_f0_val_2 : in std_logic; - sample_f0_val_1 : in std_logic; - sample_f1_val : out std_logic; - sample_f0_val_0 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_f1_val_0 : out std_logic - ); - -end Downsampling_8_16_6; - -architecture DEF_ARCH of Downsampling_8_16_6 is - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal sample_out_val_14, un10_sample_in_val_0, - un10_sample_in_val_23, un10_sample_in_val_22, - un10_sample_in_val_24, sample_out_0_sqmuxa_3, - sample_out_0_sqmuxa_2, sample_out_0_sqmuxa_1, - sample_out_0_sqmuxa_0, N_137, \counter[1]_net_1\, - \counter[0]_net_1\, N_129, \counter[3]_net_1\, - \DWACT_FDEC_E[0]\, N_106, \counter[8]_net_1\, - \DWACT_FDEC_E[4]\, N_91, \DWACT_FDEC_E[7]\, - \DWACT_FDEC_E[6]\, un10_sample_in_val_15, - un10_sample_in_val_14, un10_sample_in_val_20, - un10_sample_in_val_9, un10_sample_in_val_8, - un10_sample_in_val_19, un10_sample_in_val_5, - un10_sample_in_val_4, un10_sample_in_val_17, - un10_sample_in_val_13, \counter[24]_net_1\, - un10_sample_in_val_11, \counter[15]_net_1\, - \counter[12]_net_1\, un10_sample_in_val_7, - \counter[22]_net_1\, \counter[19]_net_1\, - un10_sample_in_val_3, \counter[23]_net_1\, - \counter[20]_net_1\, un10_sample_in_val_1, - \counter[11]_net_1\, \counter[27]_net_1\, - \counter[18]_net_1\, \counter[21]_net_1\, - \counter[9]_net_1\, \counter[4]_net_1\, - \counter[6]_net_1\, \counter[25]_net_1\, - \counter[2]_net_1\, \counter[13]_net_1\, - \counter[16]_net_1\, \counter[7]_net_1\, - \counter[10]_net_1\, \counter[26]_net_1\, - \counter[5]_net_1\, \counter[14]_net_1\, - \counter[17]_net_1\, un10_sample_in_val, \counter_4[0]\, - I_13_15, \counter_4[1]\, I_20_11, \counter_4[2]\, I_24_12, - \counter_4[3]\, I_31_11, \counter_4[4]\, I_38_8, - \counter_4[5]\, I_45_7, \counter_4[6]\, I_52_7, - \counter_4[7]\, I_56_8, \counter_4[8]\, I_66_8, - \counter_4[9]\, I_73_6, \counter_4[10]\, I_77_6, - \counter_4[11]\, I_84_6, \counter_4[12]\, I_91_6, - \counter_4[13]\, I_98_6, \counter_4[14]\, I_105_6, - \counter_4[15]\, I_115_6, \counter_4[16]\, I_122_6, - \counter_4[17]\, I_129_6, \counter_4[18]\, I_136_5, - \counter_4[19]\, I_143_5, \counter_4[20]\, I_156_5, - \counter_4[21]\, I_166_5, \counter_4[22]\, I_173_5, - \counter_4[23]\, I_186_5, \counter_4[24]\, I_196_5, - \counter_4_1[1]\, I_5_11, sample_out_0_sqmuxa, I_4_0, - I_9_11, N_4, \DWACT_FDEC_E[29]\, \DWACT_FDEC_E[30]\, - \DWACT_FDEC_E[23]\, \DWACT_FDEC_E[15]\, - \DWACT_FDEC_E[17]\, \DWACT_FDEC_E[22]\, N_11, - \DWACT_FDEC_E[21]\, \DWACT_FDEC_E[9]\, \DWACT_FDEC_E[12]\, - \DWACT_FDEC_E[20]\, N_20, \DWACT_FDEC_E[13]\, - \DWACT_FDEC_E[19]\, N_25, \DWACT_FDEC_E[18]\, N_32, - \DWACT_FDEC_E[33]\, \DWACT_FDEC_E[34]\, \DWACT_FDEC_E[2]\, - \DWACT_FDEC_E[5]\, N_41, \DWACT_FDEC_E[28]\, - \DWACT_FDEC_E[16]\, N_46, N_51, \DWACT_FDEC_E[14]\, N_56, - N_61, \DWACT_FDEC_E[10]\, N_68, \DWACT_FDEC_E[11]\, N_73, - N_78, N_83, \DWACT_FDEC_E[8]\, N_88, N_96, N_103, - \DWACT_FDEC_E[3]\, N_111, N_116, N_121, \DWACT_FDEC_E[1]\, - N_126, N_134, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - - \counter[19]\ : DFN1E1C0 - port map(D => \counter_4[16]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[19]_net_1\); - - \sample_out[125]\ : DFN1E1 - port map(D => sample_f0_wdata_2, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_2); - - \sample_out[102]\ : DFN1E1 - port map(D => sample_f0_54, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_54); - - \counter_RNI8BJ5[4]\ : NOR2 - port map(A => \counter[4]_net_1\, B => \counter[6]_net_1\, - Y => un10_sample_in_val_8); - - \sample_out[122]\ : DFN1E1 - port map(D => sample_f0_wdata_5, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_5); - - \sample_out[22]\ : DFN1E1 - port map(D => sample_f0_wdata_73, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_73); - - \sample_out[101]\ : DFN1E1 - port map(D => sample_f0_53, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_53); - - \counter_RNISI4K4_3[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val_0, Y => sample_out_0_sqmuxa_3); - - \sample_out[20]\ : DFN1E1 - port map(D => sample_f0_wdata_75, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_75); - - \sample_out[13]\ : DFN1E1 - port map(D => sample_f0_wdata_82, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_82); - - \sample_out[1]\ : DFN1E1 - port map(D => sample_f0_wdata_94, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_94); - - \sample_out[19]\ : DFN1E1 - port map(D => sample_f0_wdata_76, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_76); - - un3_counter_I_142 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[16]\, Y => N_41); - - \sample_out[61]\ : DFN1E1 - port map(D => sample_f0_13, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_13); - - \sample_out[121]\ : DFN1E1 - port map(D => sample_f0_wdata_6, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_6); - - \counter_RNI2NOI4[4]\ : NOR2A - port map(A => sample_f0_val_0, B => un10_sample_in_val, Y - => sample_out_val_14); - - \sample_out[38]\ : DFN1E1 - port map(D => sample_f0_wdata_57, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_57); - - un3_counter_I_27 : OR2 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - Y => \DWACT_FDEC_E[1]\); - - \sample_out[95]\ : DFN1E1 - port map(D => sample_f0_47, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_47); - - \counter_RNIU1AC1[7]\ : NOR3C - port map(A => un10_sample_in_val_5, B => - un10_sample_in_val_4, C => un10_sample_in_val_17, Y => - un10_sample_in_val_22); - - \counter_RNO[11]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_66_8, Y => - \counter_4[8]\); - - \sample_out[104]\ : DFN1E1 - port map(D => sample_f0_56, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_56); - - \sample_out[34]\ : DFN1E1 - port map(D => sample_f0_wdata_61, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_61); - - un3_counter_I_4 : INV - port map(A => \counter[0]_net_1\, Y => I_4_0); - - \sample_out[124]\ : DFN1E1 - port map(D => sample_f0_wdata_3, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_3); - - \counter[11]\ : DFN1E1C0 - port map(D => \counter_4[8]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_1, Q => \counter[11]_net_1\); - - un3_counter_I_94 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, Y - => \DWACT_FDEC_E[10]\); - - \sample_out[97]\ : DFN1E1 - port map(D => sample_f0_49, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_49); - - un3_counter_I_186 : XNOR2 - port map(A => N_11, B => \counter[26]_net_1\, Y => I_186_5); - - \sample_out[108]\ : DFN1E1 - port map(D => sample_f0_60, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_60); - - \counter_RNO[15]\ : NOR2B - port map(A => un10_sample_in_val, B => I_91_6, Y => - \counter_4[12]\); - - un3_counter_I_108 : OR3 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - C => \counter[17]_net_1\, Y => \DWACT_FDEC_E[12]\); - - un3_counter_I_121 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \counter[18]_net_1\, Y => N_56); - - \sample_out[51]\ : DFN1E1 - port map(D => sample_f0_3, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_3); - - \sample_out[56]\ : DFN1E1 - port map(D => sample_f0_8, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_8); - - un3_counter_I_176 : OR2 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - Y => \DWACT_FDEC_E[20]\); - - \counter_RNIKCPU1[20]\ : NOR3C - port map(A => un10_sample_in_val_15, B => - un10_sample_in_val_14, C => un10_sample_in_val_20, Y => - un10_sample_in_val_24); - - \sample_out[0]\ : DFN1E1 - port map(D => sample_f0_wdata_95, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_95); - - \counter_RNO[7]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_38_8, Y => - \counter_4[4]\); - - \counter[6]\ : DFN1E1C0 - port map(D => \counter_4[3]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[6]_net_1\); - - un3_counter_I_48 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); - - un3_counter_I_114 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[10]\, - C => \DWACT_FDEC_E[12]\, Y => N_61); - - \counter[21]\ : DFN1E1C0 - port map(D => \counter_4[18]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[21]_net_1\); - - un3_counter_I_13 : XNOR2 - port map(A => N_134, B => \counter[3]_net_1\, Y => I_13_15); - - \sample_out[81]\ : DFN1E1 - port map(D => sample_f0_33, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_33); - - \sample_out[86]\ : DFN1E1 - port map(D => sample_f0_38, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_38); - - \counter[3]\ : DFN1E1C0 - port map(D => \counter_4[0]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[3]_net_1\); - - \counter[2]\ : DFN1E1C0 - port map(D => I_9_11, CLK => lclk_c, CLR => rstn, E => - sample_f0_val_1, Q => \counter[2]_net_1\); - - un3_counter_I_73 : XNOR2 - port map(A => N_91, B => \counter[12]_net_1\, Y => I_73_6); - - \counter_RNO[8]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_45_7, Y => - \counter_4[5]\); - - \counter_RNO[13]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_77_6, Y => - \counter_4[10]\); - - \counter_RNI3RPP[12]\ : NOR3A - port map(A => un10_sample_in_val_11, B => - \counter[15]_net_1\, C => \counter[12]_net_1\, Y => - un10_sample_in_val_19); - - \counter_RNIAB89[7]\ : NOR2 - port map(A => \counter[7]_net_1\, B => \counter[10]_net_1\, - Y => un10_sample_in_val_4); - - un3_counter_I_52 : XNOR2 - port map(A => N_106, B => \counter[9]_net_1\, Y => I_52_7); - - \sample_out[12]\ : DFN1E1 - port map(D => sample_f0_wdata_83, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_83); - - \sample_out[10]\ : DFN1E1 - port map(D => sample_f0_wdata_85, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_85); - - \sample_out[45]\ : DFN1E1 - port map(D => sample_f0_wdata_50, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_50); - - \counter_RNO[12]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_73_6, Y => - \counter_4[9]\); - - \sample_out[33]\ : DFN1E1 - port map(D => sample_f0_wdata_62, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_62); - - \sample_out[39]\ : DFN1E1 - port map(D => sample_f0_wdata_56, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_56); - - \counter_RNO[1]\ : NOR2B - port map(A => un10_sample_in_val, B => I_5_11, Y => - \counter_4_1[1]\); - - \counter[17]\ : DFN1E1C0 - port map(D => \counter_4[14]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[17]_net_1\); - - un3_counter_I_41 : OR2 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - Y => \DWACT_FDEC_E[3]\); - - un3_counter_I_159 : OR3 - port map(A => \counter[21]_net_1\, B => \counter[22]_net_1\, - C => \counter[23]_net_1\, Y => \DWACT_FDEC_E[17]\); - - \counter[4]\ : DFN1E1C0 - port map(D => \counter_4[1]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[4]_net_1\); - - un3_counter_I_5 : XNOR2 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - Y => I_5_11); - - \counter_RNISI4K4_2[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val_0, Y => sample_out_0_sqmuxa_0); - - un3_counter_I_125 : OR2 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - Y => \DWACT_FDEC_E[14]\); - - \counter_RNI1FI5[3]\ : NOR2 - port map(A => \counter[3]_net_1\, B => \counter[0]_net_1\, - Y => un10_sample_in_val_13); - - \counter[10]\ : DFN1E1C0 - port map(D => \counter_4[7]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_0, Q => \counter[10]_net_1\); - - \sample_out[5]\ : DFN1E1 - port map(D => sample_f0_wdata_90, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_90); - - \sample_out[47]\ : DFN1E1 - port map(D => sample_f0_wdata_48, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_48); - - GND_i : GND - port map(Y => \GND\); - - \counter[13]\ : DFN1E1C0 - port map(D => \counter_4[10]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[13]_net_1\); - - un3_counter_I_62 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); - - un3_counter_I_139 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - Y => \DWACT_FDEC_E[16]\); - - \sample_out[115]\ : DFN1E1 - port map(D => sample_f0_wdata_12, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_12); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sample_out[21]\ : DFN1E1 - port map(D => sample_f0_wdata_74, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_74); - - \counter[12]\ : DFN1E1C0 - port map(D => \counter_4[9]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_1, Q => \counter[12]_net_1\); - - \sample_out[26]\ : DFN1E1 - port map(D => sample_f0_wdata_69, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_69); - - \sample_out[2]\ : DFN1E1 - port map(D => sample_f0_wdata_93, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_93); - - \sample_out[98]\ : DFN1E1 - port map(D => sample_f0_50, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_50); - - \sample_out[112]\ : DFN1E1 - port map(D => sample_f0_wdata_15, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_15); - - \counter[27]\ : DFN1E1C0 - port map(D => \counter_4[24]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[27]_net_1\); - - un3_counter_I_111 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[28]\); - - \counter[20]\ : DFN1E1C0 - port map(D => \counter_4[17]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[20]_net_1\); - - \sample_out[94]\ : DFN1E1 - port map(D => sample_f0_46, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_46); - - \sample_out[111]\ : DFN1E1 - port map(D => sample_f0_63, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_63); - - \counter_RNI3R4M[19]\ : NOR3A - port map(A => un10_sample_in_val_7, B => - \counter[22]_net_1\, C => \counter[19]_net_1\, Y => - un10_sample_in_val_17); - - un3_counter_I_166 : XNOR2 - port map(A => N_25, B => \counter[24]_net_1\, Y => I_166_5); - - \counter_RNIH789[26]\ : NOR2 - port map(A => \counter[26]_net_1\, B => \counter[5]_net_1\, - Y => un10_sample_in_val_3); - - \counter_RNO[17]\ : NOR2B - port map(A => un10_sample_in_val, B => I_105_6, Y => - \counter_4[14]\); - - \counter[23]\ : DFN1E1C0 - port map(D => \counter_4[20]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[23]_net_1\); - - un3_counter_I_149 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[34]\); - - \sample_out[55]\ : DFN1E1 - port map(D => sample_f0_7, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_7); - - \counter[22]\ : DFN1E1C0 - port map(D => \counter_4[19]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[22]_net_1\); - - \counter[15]\ : DFN1E1C0 - port map(D => \counter_4[12]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[15]_net_1\); - - un3_counter_I_8 : OR2 - port map(A => \counter[1]_net_1\, B => \counter[0]_net_1\, - Y => N_137); - - un3_counter_I_185 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[21]\, Y => N_11); - - \sample_out[114]\ : DFN1E1 - port map(D => sample_f0_wdata_13, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_13); - - un3_counter_I_196 : XNOR2 - port map(A => N_4, B => \counter[27]_net_1\, Y => I_196_5); - - \counter_RNIF7K5[8]\ : NOR2 - port map(A => \counter[8]_net_1\, B => \counter[9]_net_1\, - Y => un10_sample_in_val_9); - - \sample_out[32]\ : DFN1E1 - port map(D => sample_f0_wdata_63, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_63); - - un3_counter_I_51 : OR2 - port map(A => \counter[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y - => N_106); - - un3_counter_I_122 : XNOR2 - port map(A => N_56, B => \counter[19]_net_1\, Y => I_122_6); - - \sample_out[118]\ : DFN1E1 - port map(D => sample_f0_wdata_9, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_9); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_out[57]\ : DFN1E1 - port map(D => sample_f0_9, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_9); - - \sample_out[30]\ : DFN1E1 - port map(D => sample_f0_wdata_65, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_65); - - \counter_RNO[14]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_84_6, Y => - \counter_4[11]\); - - \sample_out[85]\ : DFN1E1 - port map(D => sample_f0_37, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_37); - - \counter[1]\ : DFN1E1C0 - port map(D => \counter_4_1[1]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[1]_net_1\); - - \counter_RNO[26]\ : NOR2B - port map(A => un10_sample_in_val, B => I_186_5, Y => - \counter_4[23]\); - - \sample_out[4]\ : DFN1E1 - port map(D => sample_f0_wdata_91, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_91); - - \counter_RNO[5]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_24_12, Y => - \counter_4[2]\); - - \sample_out[103]\ : DFN1E1 - port map(D => sample_f0_55, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_55); - - \sample_out[100]\ : DFN1E1 - port map(D => sample_f0_52, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_52); - - \counter[25]\ : DFN1E1C0 - port map(D => \counter_4[22]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[25]_net_1\); - - \sample_out[123]\ : DFN1E1 - port map(D => sample_f0_wdata_4, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_4); - - \sample_out[120]\ : DFN1E1 - port map(D => sample_f0_wdata_7, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_7); - - \counter_RNIJRSC[14]\ : NOR2 - port map(A => \counter[14]_net_1\, B => \counter[17]_net_1\, - Y => un10_sample_in_val_1); - - sample_out_val : DFN1C0 - port map(D => sample_out_val_14, CLK => lclk_c, CLR => rstn, - Q => sample_f1_val); - - \counter_RNO[3]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_13_15, Y => - \counter_4[0]\); - - \sample_out[87]\ : DFN1E1 - port map(D => sample_f0_39, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_39); - - un3_counter_I_115 : XNOR2 - port map(A => N_61, B => \counter[18]_net_1\, Y => I_115_6); - - un3_counter_I_87 : OR3 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - C => \counter[14]_net_1\, Y => \DWACT_FDEC_E[9]\); - - un3_counter_I_173 : XNOR2 - port map(A => N_20, B => \counter[25]_net_1\, Y => I_173_5); - - \sample_out[48]\ : DFN1E1 - port map(D => sample_f0_0, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_0); - - un3_counter_I_38 : XNOR2 - port map(A => N_116, B => \counter[7]_net_1\, Y => I_38_8); - - \sample_out[93]\ : DFN1E1 - port map(D => sample_f0_45, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_45); - - \sample_out[11]\ : DFN1E1 - port map(D => sample_f0_wdata_84, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_84); - - \sample_out[99]\ : DFN1E1 - port map(D => sample_f0_51, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_51); - - \sample_out[16]\ : DFN1E1 - port map(D => sample_f0_wdata_79, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_79); - - \counter[5]\ : DFN1E1C0 - port map(D => \counter_4[2]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[5]_net_1\); - - \sample_out[44]\ : DFN1E1 - port map(D => sample_f0_wdata_51, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_51); - - un3_counter_I_37 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \counter[6]_net_1\, Y => N_116); - - \counter_RNIKVSC[18]\ : NOR2 - port map(A => \counter[18]_net_1\, B => \counter[21]_net_1\, - Y => un10_sample_in_val_11); - - \counter_RNO[10]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_56_8, Y => - \counter_4[7]\); - - un3_counter_I_9 : XNOR2 - port map(A => N_137, B => \counter[2]_net_1\, Y => I_9_11); - - \counter_RNO[21]\ : NOR2B - port map(A => un10_sample_in_val, B => I_136_5, Y => - \counter_4[18]\); - - un3_counter_I_20 : XNOR2 - port map(A => N_129, B => \counter[4]_net_1\, Y => I_20_11); - - un3_counter_I_182 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[30]\); - - \sample_out[25]\ : DFN1E1 - port map(D => sample_f0_wdata_70, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_70); - - \counter_RNISI4K4[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val, Y => sample_out_0_sqmuxa); - - un3_counter_I_56 : XNOR2 - port map(A => N_103, B => \counter[10]_net_1\, Y => I_56_8); - - \counter_RNIQD151[4]\ : NOR3C - port map(A => un10_sample_in_val_9, B => - un10_sample_in_val_8, C => un10_sample_in_val_19, Y => - un10_sample_in_val_23); - - \counter[16]\ : DFN1E1C0 - port map(D => \counter_4[13]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[16]_net_1\); - - \counter_RNO[25]\ : NOR2B - port map(A => un10_sample_in_val, B => I_173_5, Y => - \counter_4[22]\); - - un3_counter_I_172 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[19]\, Y => N_20); - - un3_counter_I_104 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \DWACT_FDEC_E[11]\, Y => N_68); - - un3_counter_I_31 : XNOR2 - port map(A => N_121, B => \counter[6]_net_1\, Y => I_31_11); - - un3_counter_I_98 : XNOR2 - port map(A => N_73, B => \counter[16]_net_1\, Y => I_98_6); - - un3_counter_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \counter[3]_net_1\, C - => \counter[4]_net_1\, Y => N_126); - - \sample_out[27]\ : DFN1E1 - port map(D => sample_f0_wdata_68, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_68); - - \counter_RNIHRSC[13]\ : NOR2 - port map(A => \counter[13]_net_1\, B => \counter[16]_net_1\, - Y => un10_sample_in_val_5); - - \counter_RNIC6QE[24]\ : NOR3A - port map(A => un10_sample_in_val_13, B => - \counter[1]_net_1\, C => \counter[24]_net_1\, Y => - un10_sample_in_val_20); - - un3_counter_I_59 : OR3 - port map(A => \counter[6]_net_1\, B => \counter[7]_net_1\, - C => \counter[8]_net_1\, Y => \DWACT_FDEC_E[5]\); - - un3_counter_I_12 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => N_134); - - \counter_RNO[6]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_31_11, Y => - \counter_4[3]\); - - un3_counter_I_165 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[18]\, Y => N_25); - - un3_counter_I_156 : XNOR2 - port map(A => N_32, B => \counter[23]_net_1\, Y => I_156_5); - - un3_counter_I_97 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[10]\, C - => \counter[15]_net_1\, Y => N_73); - - un3_counter_I_128 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[14]\, Y => N_51); - - un3_counter_I_72 : OR2 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y - => N_91); - - \sample_out[58]\ : DFN1E1 - port map(D => sample_f0_10, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_10); - - \counter[26]\ : DFN1E1C0 - port map(D => \counter_4[23]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[26]_net_1\); - - un3_counter_I_66 : XNOR2 - port map(A => N_96, B => \counter[11]_net_1\, Y => I_66_8); - - \counter_RNO[23]\ : NOR2B - port map(A => un10_sample_in_val, B => I_156_5, Y => - \counter_4[20]\); - - \sample_out[54]\ : DFN1E1 - port map(D => sample_f0_6, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_6); - - \sample_out[43]\ : DFN1E1 - port map(D => sample_f0_wdata_52, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_52); - - \sample_out[49]\ : DFN1E1 - port map(D => sample_f0_1, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_1); - - \counter_RNISI4K4_1[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val_0, Y => sample_out_0_sqmuxa_2); - - sample_out_val_0 : DFN1C0 - port map(D => sample_out_val_14, CLK => lclk_c, CLR => rstn, - Q => sample_f1_val_0); - - un3_counter_I_45 : XNOR2 - port map(A => N_111, B => \counter[8]_net_1\, Y => I_45_7); - - un3_counter_I_24 : XNOR2 - port map(A => N_126, B => \counter[5]_net_1\, Y => I_24_12); - - un3_counter_I_195 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[30]\, - C => \DWACT_FDEC_E[23]\, Y => N_4); - - \sample_out[92]\ : DFN1E1 - port map(D => sample_f0_44, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_44); - - \counter[14]\ : DFN1E1C0 - port map(D => \counter_4[11]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[14]_net_1\); - - un3_counter_I_136 : XNOR2 - port map(A => N_46, B => \counter[21]_net_1\, Y => I_136_5); - - \sample_out[88]\ : DFN1E1 - port map(D => sample_f0_40, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_40); - - \sample_out[90]\ : DFN1E1 - port map(D => sample_f0_42, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_42); - - un3_counter_I_91 : XNOR2 - port map(A => N_78, B => \counter[15]_net_1\, Y => I_91_6); - - \counter_RNO[22]\ : NOR2B - port map(A => un10_sample_in_val, B => I_143_5, Y => - \counter_4[19]\); - - \sample_out[31]\ : DFN1E1 - port map(D => sample_f0_wdata_64, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_64); - - \sample_out[36]\ : DFN1E1 - port map(D => sample_f0_wdata_59, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_59); - - un3_counter_I_69 : OR3 - port map(A => \counter[9]_net_1\, B => \counter[10]_net_1\, - C => \counter[11]_net_1\, Y => \DWACT_FDEC_E[7]\); - - \sample_out[84]\ : DFN1E1 - port map(D => sample_f0_36, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_36); - - \sample_out[63]\ : DFN1E1 - port map(D => sample_f0_15, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_15); - - \sample_out[15]\ : DFN1E1 - port map(D => sample_f0_wdata_80, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_80); - - un3_counter_I_129 : XNOR2 - port map(A => N_51, B => \counter[20]_net_1\, Y => I_129_6); - - GND_i_0 : GND - port map(Y => GND_0); - - un3_counter_I_146 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \counter[21]_net_1\, - C => \counter[22]_net_1\, Y => \DWACT_FDEC_E[33]\); - - \counter[24]\ : DFN1E1C0 - port map(D => \counter_4[21]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[24]_net_1\); - - un3_counter_I_101 : OR2 - port map(A => \counter[15]_net_1\, B => \counter[16]_net_1\, - Y => \DWACT_FDEC_E[11]\); - - \sample_out[113]\ : DFN1E1 - port map(D => sample_f0_wdata_14, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_14); - - \sample_out[110]\ : DFN1E1 - port map(D => sample_f0_62, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_62); - - \counter_RNO[4]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_20_11, Y => - \counter_4[1]\); - - un3_counter_I_162 : OR2 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - Y => \DWACT_FDEC_E[18]\); - - \sample_out[106]\ : DFN1E1 - port map(D => sample_f0_58, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_58); - - un3_counter_I_77 : XNOR2 - port map(A => N_88, B => \counter[13]_net_1\, Y => I_77_6); - - \sample_out[17]\ : DFN1E1 - port map(D => sample_f0_wdata_78, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_78); - - \sample_out[107]\ : DFN1E1 - port map(D => sample_f0_59, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_59); - - \counter_RNO[18]\ : NOR2B - port map(A => un10_sample_in_val, B => I_115_6, Y => - \counter_4[15]\); - - un3_counter_I_44 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[3]\, Y => N_111); - - \sample_out[126]\ : DFN1E1 - port map(D => sample_f0_wdata_1, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_1); - - \sample_out[127]\ : DFN1E1 - port map(D => sample_f0_wdata_0, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_0); - - \sample_out[53]\ : DFN1E1 - port map(D => sample_f0_5, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_5); - - \sample_out[28]\ : DFN1E1 - port map(D => sample_f0_wdata_67, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_67); - - \counter_RNO[27]\ : NOR2B - port map(A => un10_sample_in_val, B => I_196_5, Y => - \counter_4[24]\); - - \sample_out[59]\ : DFN1E1 - port map(D => sample_f0_11, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_11); - - \counter_RNICS4G4[4]\ : OR3C - port map(A => un10_sample_in_val_23, B => - un10_sample_in_val_22, C => un10_sample_in_val_24, Y => - un10_sample_in_val_0); - - \sample_out[109]\ : DFN1E1 - port map(D => sample_f0_61, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_61); - - un3_counter_I_192 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[22]\, Y => \DWACT_FDEC_E[23]\); - - \sample_out[24]\ : DFN1E1 - port map(D => sample_f0_wdata_71, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_71); - - un3_counter_I_55 : OR3 - port map(A => \DWACT_FDEC_E[4]\, B => \counter[8]_net_1\, C - => \counter[9]_net_1\, Y => N_103); - - \sample_out[42]\ : DFN1E1 - port map(D => sample_f0_wdata_53, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_53); - - un3_counter_I_118 : OR3 - port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[9]\, C - => \DWACT_FDEC_E[12]\, Y => \DWACT_FDEC_E[13]\); - - \counter_RNISI4K4_0[4]\ : NOR3B - port map(A => rstn, B => sample_f0_val_0, C => - un10_sample_in_val_0, Y => sample_out_0_sqmuxa_1); - - \sample_out[40]\ : DFN1E1 - port map(D => sample_f0_wdata_55, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_55); - - \sample_out[83]\ : DFN1E1 - port map(D => sample_f0_35, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_35); - - \sample_out[89]\ : DFN1E1 - port map(D => sample_f0_41, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_41); - - un3_counter_I_189 : OR3 - port map(A => \counter[24]_net_1\, B => \counter[25]_net_1\, - C => \counter[26]_net_1\, Y => \DWACT_FDEC_E[22]\); - - \counter_RNO[24]\ : NOR2B - port map(A => un10_sample_in_val, B => I_166_5, Y => - \counter_4[21]\); - - \counter[7]\ : DFN1E1C0 - port map(D => \counter_4[4]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[7]_net_1\); - - \counter_RNICS4G4_0[4]\ : OR3C - port map(A => un10_sample_in_val_23, B => - un10_sample_in_val_22, C => un10_sample_in_val_24, Y => - un10_sample_in_val); - - un3_counter_I_105 : XNOR2 - port map(A => N_68, B => \counter[17]_net_1\, Y => I_105_6); - - \counter_RNI2B5M[20]\ : NOR3A - port map(A => un10_sample_in_val_3, B => - \counter[23]_net_1\, C => \counter[20]_net_1\, Y => - un10_sample_in_val_15); - - \sample_out[6]\ : DFN1E1 - port map(D => sample_f0_wdata_89, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_89); - - un3_counter_I_155 : OR3 - port map(A => \DWACT_FDEC_E[29]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[33]\, Y => N_32); - - un3_counter_I_179 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \DWACT_FDEC_E[20]\, Y => \DWACT_FDEC_E[21]\); - - \sample_out[62]\ : DFN1E1 - port map(D => sample_f0_14, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_14); - - \sample_out[60]\ : DFN1E1 - port map(D => sample_f0_12, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_12); - - un3_counter_I_65 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \counter[9]_net_1\, C - => \counter[10]_net_1\, Y => N_96); - - \sample_out[35]\ : DFN1E1 - port map(D => sample_f0_wdata_60, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_60); - - \sample_out[91]\ : DFN1E1 - port map(D => sample_f0_43, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_43); - - un3_counter_I_135 : OR3 - port map(A => \DWACT_FDEC_E[28]\, B => \DWACT_FDEC_E[13]\, - C => \DWACT_FDEC_E[15]\, Y => N_46); - - \sample_out[96]\ : DFN1E1 - port map(D => sample_f0_48, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_48); - - un3_counter_I_80 : OR2 - port map(A => \counter[12]_net_1\, B => \counter[13]_net_1\, - Y => \DWACT_FDEC_E[8]\); - - un3_counter_I_16 : OR3 - port map(A => \counter[0]_net_1\, B => \counter[1]_net_1\, - C => \counter[2]_net_1\, Y => \DWACT_FDEC_E[0]\); - - \counter_RNO[20]\ : NOR2B - port map(A => un10_sample_in_val, B => I_129_6, Y => - \counter_4[17]\); - - \sample_out[37]\ : DFN1E1 - port map(D => sample_f0_wdata_58, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_58); - - \sample_out[23]\ : DFN1E1 - port map(D => sample_f0_wdata_72, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_72); - - \sample_out[52]\ : DFN1E1 - port map(D => sample_f0_4, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_4); - - \sample_out[29]\ : DFN1E1 - port map(D => sample_f0_wdata_66, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_66); - - un3_counter_I_76 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \counter[12]_net_1\, Y => N_88); - - un3_counter_I_30 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C - => \counter[5]_net_1\, Y => N_121); - - \sample_out[50]\ : DFN1E1 - port map(D => sample_f0_2, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_2); - - \sample_out[18]\ : DFN1E1 - port map(D => sample_f0_wdata_77, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_77); - - \sample_out[9]\ : DFN1E1 - port map(D => sample_f0_wdata_86, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_wdata_86); - - \sample_out[7]\ : DFN1E1 - port map(D => sample_f0_wdata_88, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_wdata_88); - - \counter_RNI6RPP[27]\ : NOR3A - port map(A => un10_sample_in_val_1, B => - \counter[11]_net_1\, C => \counter[27]_net_1\, Y => - un10_sample_in_val_14); - - un3_counter_I_83 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[8]\, Y => N_83); - - un3_counter_I_19 : OR2 - port map(A => \counter[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y - => N_129); - - \sample_out[14]\ : DFN1E1 - port map(D => sample_f0_wdata_81, CLK => lclk_c, E => - sample_out_0_sqmuxa_1, Q => sample_f1_wdata_81); - - \sample_out[82]\ : DFN1E1 - port map(D => sample_f0_34, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_34); - - \counter[9]\ : DFN1E1C0 - port map(D => \counter_4[6]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[9]_net_1\); - - \sample_out[80]\ : DFN1E1 - port map(D => sample_f0_32, CLK => lclk_c, E => - sample_out_0_sqmuxa_3, Q => sample_f1_32); - - \counter_RNO[19]\ : NOR2B - port map(A => un10_sample_in_val, B => I_122_6, Y => - \counter_4[16]\); - - un3_counter_I_152 : OR3 - port map(A => \DWACT_FDEC_E[34]\, B => \DWACT_FDEC_E[2]\, C - => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[29]\); - - \counter_RNIDR79[25]\ : NOR2 - port map(A => \counter[25]_net_1\, B => \counter[2]_net_1\, - Y => un10_sample_in_val_7); - - \counter_RNO[9]\ : NOR2B - port map(A => un10_sample_in_val_0, B => I_52_7, Y => - \counter_4[6]\); - - \counter[8]\ : DFN1E1C0 - port map(D => \counter_4[5]\, CLK => lclk_c, CLR => rstn, E - => sample_f0_val_2, Q => \counter[8]_net_1\); - - un3_counter_I_84 : XNOR2 - port map(A => N_83, B => \counter[14]_net_1\, Y => I_84_6); - - un3_counter_I_143 : XNOR2 - port map(A => N_41, B => \counter[22]_net_1\, Y => I_143_5); - - \sample_out[116]\ : DFN1E1 - port map(D => sample_f0_wdata_11, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_11); - - \counter[18]\ : DFN1E1C0 - port map(D => \counter_4[15]\, CLK => lclk_c, CLR => rstn, - E => sample_f0_val_1, Q => \counter[18]_net_1\); - - \sample_out[117]\ : DFN1E1 - port map(D => sample_f0_wdata_10, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_10); - - un3_counter_I_90 : OR3 - port map(A => \DWACT_FDEC_E[6]\, B => \DWACT_FDEC_E[7]\, C - => \DWACT_FDEC_E[9]\, Y => N_78); - - un3_counter_I_169 : OR3 - port map(A => \DWACT_FDEC_E[15]\, B => \DWACT_FDEC_E[17]\, - C => \counter[24]_net_1\, Y => \DWACT_FDEC_E[19]\); - - un3_counter_I_132 : OR3 - port map(A => \counter[18]_net_1\, B => \counter[19]_net_1\, - C => \counter[20]_net_1\, Y => \DWACT_FDEC_E[15]\); - - \sample_out[8]\ : DFN1E1 - port map(D => sample_f0_wdata_87, CLK => lclk_c, E => - sample_out_0_sqmuxa, Q => sample_f1_wdata_87); - - \sample_out[41]\ : DFN1E1 - port map(D => sample_f0_wdata_54, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_54); - - \counter_RNO[16]\ : NOR2B - port map(A => un10_sample_in_val, B => I_98_6, Y => - \counter_4[13]\); - - \counter[0]\ : DFN1E1C0 - port map(D => I_4_0, CLK => lclk_c, CLR => rstn, E => - sample_f0_val_0, Q => \counter[0]_net_1\); - - \sample_out[46]\ : DFN1E1 - port map(D => sample_f0_wdata_49, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_49); - - \sample_out[3]\ : DFN1E1 - port map(D => sample_f0_wdata_92, CLK => lclk_c, E => - sample_out_0_sqmuxa_2, Q => sample_f1_wdata_92); - - un3_counter_I_34 : OR3 - port map(A => \counter[3]_net_1\, B => \counter[4]_net_1\, - C => \counter[5]_net_1\, Y => \DWACT_FDEC_E[2]\); - - \sample_out[105]\ : DFN1E1 - port map(D => sample_f0_57, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_57); - - \sample_out[119]\ : DFN1E1 - port map(D => sample_f0_wdata_8, CLK => lclk_c, E => - sample_out_0_sqmuxa_0, Q => sample_f1_wdata_8); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity SYNC_FF_1 is - - port( sample_bit_counter_0 : in std_logic_vector(0 to 0); - SYNC_FF_1_VCC : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - sample_bit_counter_n0 : out std_logic; - cnv_done_i : in std_logic; - N_36 : out std_logic - ); - -end SYNC_FF_1; - -architecture DEF_ARCH of SYNC_FF_1 is - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal cnv_run_sync, \A_temp[1]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sync_loop.0.A_temp_RNI0P5E[0]\ : OR2B - port map(A => cnv_run_sync, B => cnv_done_i, Y => N_36); - - \sync_loop.0.A_temp[0]\ : DFN1C0 - port map(D => \A_temp[1]\, CLK => lclk_c, CLR => rstn, Q - => cnv_run_sync); - - GND_i_0 : GND - port map(Y => GND_0); - - \sync_loop.1.A_temp[1]\ : DFN1C0 - port map(D => SYNC_FF_1_VCC, CLK => lclk_c, CLR => rstn, Q - => \A_temp[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sync_loop.0.A_temp_RNIU1FG[0]\ : AOI1B - port map(A => sample_bit_counter_0(0), B => cnv_done_i, C - => cnv_run_sync, Y => sample_bit_counter_n0); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity SYNC_FF is - - port( cnv_ch1_c : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic; - cnv_sync : out std_logic; - cnv_sync_i : out std_logic - ); - -end SYNC_FF; - -architecture DEF_ARCH of SYNC_FF is - - component VCC - port( Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \cnv_sync\, \A_temp[1]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - cnv_sync <= \cnv_sync\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \sync_loop.0.A_temp[0]\ : DFN1C0 - port map(D => \A_temp[1]\, CLK => lclk_c, CLR => rstn, Q - => \cnv_sync\); - - GND_i_0 : GND - port map(Y => GND_0); - - \sync_loop.1.A_temp[1]\ : DFN1C0 - port map(D => cnv_ch1_c, CLK => lclk_c, CLR => rstn, Q => - \A_temp[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sync_loop.0.A_temp_RNI61R4[0]\ : INV - port map(A => \cnv_sync\, Y => cnv_sync_i); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity AD7688_drvr is - - port( sample_4 : out std_logic_vector(15 downto 0); - sample_5 : out std_logic_vector(15 downto 0); - sample_6 : out std_logic_vector(15 downto 0); - sample_7 : out std_logic_vector(15 downto 0); - sample_0 : out std_logic_vector(15 downto 0); - sample_1 : out std_logic_vector(15 downto 0); - sample_2 : out std_logic_vector(15 downto 0); - sdo_adc_c : in std_logic_vector(7 downto 0); - sample_3 : out std_logic_vector(15 downto 0); - AD7688_drvr_VCC : in std_logic; - clk49_152MHz_c : in std_logic; - cnv_ch1_c : out std_logic; - sample_val : out std_logic; - sck_ch1_c : out std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end AD7688_drvr; - -architecture DEF_ARCH of AD7688_drvr is - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1E - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component SYNC_FF_1 - port( sample_bit_counter_0 : in std_logic_vector(0 to 0) := (others => 'U'); - SYNC_FF_1_VCC : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_bit_counter_n0 : out std_logic; - cnv_done_i : in std_logic := 'U'; - N_36 : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component SYNC_FF - port( cnv_ch1_c : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - cnv_sync : out std_logic; - cnv_sync_i : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \sample_bit_counter_4[0]_net_1\, - sample_bit_counter_n0, N_6, - \sample_bit_counter_3[0]_net_1\, - \sample_bit_counter_2[0]_net_1\, - \sample_bit_counter_1[0]_net_1\, - \sample_bit_counter_0[0]_net_1\, sample_0_0_sqmuxa_4, - \sample_bit_counter_RNIU4A5[5]_net_1\, - sample_0_0_sqmuxa_3, sample_0_0_sqmuxa_2, - sample_0_0_sqmuxa_1, sample_0_0_sqmuxa_0, - \sample_bit_counter_i[0]\, cnv_cycle_counter_32_0, - \cnv_cycle_counter[7]_net_1\, cnv_s_0_sqmuxa, - sample_bit_counterlde_i_a3_0_1, - \sample_bit_counter[3]_net_1\, - \sample_bit_counter[2]_net_1\, - \sample_bit_counter[4]_net_1\, un3_cnv_runlto8_0, - \cnv_cycle_counter[8]_net_1\, un3_cnv_runlto5_0, - \cnv_cycle_counter[4]_net_1\, - \cnv_cycle_counter[5]_net_1\, un2_cnv_runlto8_2, - \cnv_cycle_counter[2]_net_1\, - \cnv_cycle_counter[3]_net_1\, un2_cnv_runlto8_1, - \cnv_cycle_counter[6]_net_1\, un2_cnv_runlto8_0, N_11, - N_38, N_36, N_20, N_13, N_15, N_21, N_17, N_35, N_23, - N_30, cnv_cycle_counter_n7, cnv_cycle_counter_c6, - cnv_cycle_counter_n6, cnv_cycle_counter_c5, - cnv_cycle_counter_n5, cnv_cycle_counter_c4, - cnv_cycle_counter_n4, cnv_cycle_counter_c3, - cnv_cycle_counter_n3, cnv_cycle_counter_c2, - cnv_cycle_counter_n2, cnv_cycle_counter_c1, - sample_0_0_sqmuxa, \sample_bit_counter[1]_net_1\, - \sample_bit_counter[5]_net_1\, N_19, cnv_cycle_counter_n8, - N_102, cnv_cycle_counter_n1, \cnv_cycle_counter[1]_net_1\, - \cnv_cycle_counter[0]_net_1\, cnv_cycle_counter_n0, - un3_cnv_runlt8, \cnv_s_RNO\, cnv_done_1, cnv_sync_r_i_0, - cnv_sync, cnv_sync_i, cnv_done_i, - \sample_bit_counter[0]_net_1\, \shift_reg_3[0]_net_1\, - \shift_reg_3[1]_net_1\, \shift_reg_3[2]_net_1\, - \shift_reg_3[3]_net_1\, \shift_reg_3[4]_net_1\, - \shift_reg_3[5]_net_1\, \shift_reg_3[6]_net_1\, - \shift_reg_3[7]_net_1\, \shift_reg_3[8]_net_1\, - \shift_reg_3[9]_net_1\, \shift_reg_3[10]_net_1\, - \shift_reg_3[11]_net_1\, \shift_reg_3[12]_net_1\, - \shift_reg_3[13]_net_1\, \shift_reg_3[14]_net_1\, - \shift_reg_2[0]_net_1\, \shift_reg_2[1]_net_1\, - \shift_reg_2[2]_net_1\, \shift_reg_2[3]_net_1\, - \shift_reg_2[4]_net_1\, \shift_reg_2[5]_net_1\, - \shift_reg_2[6]_net_1\, \shift_reg_2[7]_net_1\, - \shift_reg_2[8]_net_1\, \shift_reg_2[9]_net_1\, - \shift_reg_2[10]_net_1\, \shift_reg_2[11]_net_1\, - \shift_reg_2[12]_net_1\, \shift_reg_2[13]_net_1\, - \shift_reg_2[14]_net_1\, \shift_reg_1[0]_net_1\, - \shift_reg_1[1]_net_1\, \shift_reg_1[2]_net_1\, - \shift_reg_1[3]_net_1\, \shift_reg_1[4]_net_1\, - \shift_reg_1[5]_net_1\, \shift_reg_1[6]_net_1\, - \shift_reg_1[7]_net_1\, \shift_reg_1[8]_net_1\, - \shift_reg_1[9]_net_1\, \shift_reg_1[10]_net_1\, - \shift_reg_1[11]_net_1\, \shift_reg_1[12]_net_1\, - \shift_reg_1[13]_net_1\, \shift_reg_1[14]_net_1\, - \shift_reg_0[0]_net_1\, \shift_reg_0[1]_net_1\, - \shift_reg_0[2]_net_1\, \shift_reg_0[3]_net_1\, - \shift_reg_0[4]_net_1\, \shift_reg_0[5]_net_1\, - \shift_reg_0[6]_net_1\, \shift_reg_0[7]_net_1\, - \shift_reg_0[8]_net_1\, \shift_reg_0[9]_net_1\, - \shift_reg_0[10]_net_1\, \shift_reg_0[11]_net_1\, - \shift_reg_0[12]_net_1\, \shift_reg_0[13]_net_1\, - \shift_reg_0[14]_net_1\, \shift_reg_7[0]_net_1\, - \shift_reg_7[1]_net_1\, \shift_reg_7[2]_net_1\, - \shift_reg_7[3]_net_1\, \shift_reg_7[4]_net_1\, - \shift_reg_7[5]_net_1\, \shift_reg_7[6]_net_1\, - \shift_reg_7[7]_net_1\, \shift_reg_7[8]_net_1\, - \shift_reg_7[9]_net_1\, \shift_reg_7[10]_net_1\, - \shift_reg_7[11]_net_1\, \shift_reg_7[12]_net_1\, - \shift_reg_7[13]_net_1\, \shift_reg_7[14]_net_1\, - \shift_reg_6[0]_net_1\, \shift_reg_6[1]_net_1\, - \shift_reg_6[2]_net_1\, \shift_reg_6[3]_net_1\, - \shift_reg_6[4]_net_1\, \shift_reg_6[5]_net_1\, - \shift_reg_6[6]_net_1\, \shift_reg_6[7]_net_1\, - \shift_reg_6[8]_net_1\, \shift_reg_6[9]_net_1\, - \shift_reg_6[10]_net_1\, \shift_reg_6[11]_net_1\, - \shift_reg_6[12]_net_1\, \shift_reg_6[13]_net_1\, - \shift_reg_6[14]_net_1\, \shift_reg_5[0]_net_1\, - \shift_reg_5[1]_net_1\, \shift_reg_5[2]_net_1\, - \shift_reg_5[3]_net_1\, \shift_reg_5[4]_net_1\, - \shift_reg_5[5]_net_1\, \shift_reg_5[6]_net_1\, - \shift_reg_5[7]_net_1\, \shift_reg_5[8]_net_1\, - \shift_reg_5[9]_net_1\, \shift_reg_5[10]_net_1\, - \shift_reg_5[11]_net_1\, \shift_reg_5[12]_net_1\, - \shift_reg_5[13]_net_1\, \shift_reg_5[14]_net_1\, - \shift_reg_4[0]_net_1\, \shift_reg_4[1]_net_1\, - \shift_reg_4[2]_net_1\, \shift_reg_4[3]_net_1\, - \shift_reg_4[4]_net_1\, \shift_reg_4[5]_net_1\, - \shift_reg_4[6]_net_1\, \shift_reg_4[7]_net_1\, - \shift_reg_4[8]_net_1\, \shift_reg_4[9]_net_1\, - \shift_reg_4[10]_net_1\, \shift_reg_4[11]_net_1\, - \shift_reg_4[12]_net_1\, \shift_reg_4[13]_net_1\, - \shift_reg_4[14]_net_1\, \cnv_ch1_c\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : SYNC_FF_1 - Use entity work.SYNC_FF_1(DEF_ARCH); - for all : SYNC_FF - Use entity work.SYNC_FF(DEF_ARCH); -begin - - cnv_ch1_c <= \cnv_ch1_c\; - - \sample_bit_counter_RNIUML11[5]\ : AO1A - port map(A => N_36, B => \sample_bit_counter[5]_net_1\, C - => N_30, Y => N_6); - - \sample_bit_counter[2]\ : DFN1E0C0 - port map(D => N_13, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[2]_net_1\); - - \shift_reg_0[1]\ : DFN1E1C0 - port map(D => \shift_reg_0[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[1]_net_1\); - - \shift_reg_7[14]\ : DFN1E1C0 - port map(D => \shift_reg_7[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[14]_net_1\); - - \sample_6[13]\ : DFN1E1 - port map(D => \shift_reg_6[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(13)); - - \sample_7[11]\ : DFN1E1 - port map(D => \shift_reg_7[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(11)); - - \sample_0[3]\ : DFN1E1 - port map(D => \shift_reg_0[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(3)); - - \cnv_cycle_counter_RNIHA8[5]\ : NOR2B - port map(A => \cnv_cycle_counter[5]_net_1\, B => - \cnv_cycle_counter[6]_net_1\, Y => un2_cnv_runlto8_1); - - \shift_reg_6[12]\ : DFN1E1C0 - port map(D => \shift_reg_6[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[12]_net_1\); - - \sample_1[0]\ : DFN1E1 - port map(D => sdo_adc_c(1), CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(0)); - - \sample_0[12]\ : DFN1E1 - port map(D => \shift_reg_0[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(12)); - - \shift_reg_6[9]\ : DFN1E1C0 - port map(D => \shift_reg_6[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[9]_net_1\); - - \shift_reg_2[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(2), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[0]_net_1\); - - \shift_reg_5[11]\ : DFN1E1C0 - port map(D => \shift_reg_5[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[11]_net_1\); - - \sample_bit_counter_RNISKS2_0[1]\ : NOR2 - port map(A => \sample_bit_counter[1]_net_1\, B => - \sample_bit_counter_0[0]_net_1\, Y => N_38); - - \sample_bit_counter_RNIO0M6_2[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_1); - - cnv_s : DFN1C0 - port map(D => \cnv_s_RNO\, CLK => clk49_152MHz_c, CLR => - rstn, Q => \cnv_ch1_c\); - - \sample_6[11]\ : DFN1E1 - port map(D => \shift_reg_6[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(11)); - - \sample_3[9]\ : DFN1E1 - port map(D => \shift_reg_3[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(9)); - - \shift_reg_0[10]\ : DFN1E1C0 - port map(D => \shift_reg_0[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[10]_net_1\); - - \shift_reg_7[6]\ : DFN1E1C0 - port map(D => \shift_reg_7[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[6]_net_1\); - - \shift_reg_7[2]\ : DFN1E1C0 - port map(D => \shift_reg_7[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[2]_net_1\); - - \sample_2[6]\ : DFN1E1 - port map(D => \shift_reg_2[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_2(6)); - - \cnv_cycle_counter[4]\ : DFN1C0 - port map(D => cnv_cycle_counter_n4, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[4]_net_1\); - - \cnv_cycle_counter_RNO[2]\ : XA1 - port map(A => \cnv_cycle_counter[2]_net_1\, B => - cnv_cycle_counter_c1, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n2); - - \sample_6[2]\ : DFN1E1 - port map(D => \shift_reg_6[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(2)); - - \sample_7[5]\ : DFN1E1 - port map(D => \shift_reg_7[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(5)); - - \shift_reg_5[6]\ : DFN1E1C0 - port map(D => \shift_reg_5[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[6]_net_1\); - - \shift_reg_0[14]\ : DFN1E1C0 - port map(D => \shift_reg_0[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[14]_net_1\); - - \shift_reg_1[7]\ : DFN1E1C0 - port map(D => \shift_reg_1[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[7]_net_1\); - - \sample_0[15]\ : DFN1E1 - port map(D => \shift_reg_0[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(15)); - - \sample_2[4]\ : DFN1E1 - port map(D => \shift_reg_2[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(4)); - - \sample_bit_counter_RNO[3]\ : XA1B - port map(A => N_21, B => \sample_bit_counter[3]_net_1\, C - => N_36, Y => N_15); - - \sample_1[6]\ : DFN1E1 - port map(D => \shift_reg_1[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(6)); - - \cnv_cycle_counter_RNO[8]\ : AX1E - port map(A => cnv_cycle_counter_c6, B => - cnv_cycle_counter_32_0, C => N_102, Y => - cnv_cycle_counter_n8); - - \sample_2[14]\ : DFN1E1 - port map(D => \shift_reg_2[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(14)); - - \sample_5[10]\ : DFN1E1 - port map(D => \shift_reg_5[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(10)); - - \sample_2[0]\ : DFN1E1 - port map(D => sdo_adc_c(2), CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(0)); - - \sample_bit_counter_RNIR0G3[2]\ : NOR2B - port map(A => \sample_bit_counter[2]_net_1\, B => N_20, Y - => N_21); - - \sample_5[1]\ : DFN1E1 - port map(D => \shift_reg_5[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(1)); - - \shift_reg_4[13]\ : DFN1E1C0 - port map(D => \shift_reg_4[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[13]_net_1\); - - \cnv_cycle_counter_RNO[1]\ : XA1 - port map(A => \cnv_cycle_counter[1]_net_1\, B => - \cnv_cycle_counter[0]_net_1\, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n1); - - \shift_reg_7[5]\ : DFN1E1C0 - port map(D => \shift_reg_7[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[5]_net_1\); - - \sample_0[7]\ : DFN1E1 - port map(D => \shift_reg_0[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(7)); - - \sample_0[13]\ : DFN1E1 - port map(D => \shift_reg_0[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(13)); - - \shift_reg_1[10]\ : DFN1E1C0 - port map(D => \shift_reg_1[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_1[10]_net_1\); - - \sample_bit_counter_RNISOM4[4]\ : OR3C - port map(A => N_21, B => \sample_bit_counter[3]_net_1\, C - => \sample_bit_counter[4]_net_1\, Y => N_23); - - \cnv_cycle_counter_RNIIE8[8]\ : NOR2B - port map(A => \cnv_cycle_counter[8]_net_1\, B => - \cnv_cycle_counter[4]_net_1\, Y => un2_cnv_runlto8_0); - - \sample_6[3]\ : DFN1E1 - port map(D => \shift_reg_6[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(3)); - - \shift_reg_1[5]\ : DFN1E1C0 - port map(D => \shift_reg_1[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[5]_net_1\); - - \shift_reg_5[1]\ : DFN1E1C0 - port map(D => \shift_reg_5[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[1]_net_1\); - - \shift_reg_1[14]\ : DFN1E1C0 - port map(D => \shift_reg_1[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[14]_net_1\); - - \sample_bit_counter_RNISHSI[2]\ : NOR3B - port map(A => sample_bit_counterlde_i_a3_0_1, B => N_38, C - => N_36, Y => N_30); - - \sample_bit_counter_RNI04Q1[2]\ : NOR3 - port map(A => \sample_bit_counter[3]_net_1\, B => - \sample_bit_counter[2]_net_1\, C => - \sample_bit_counter[4]_net_1\, Y => - sample_bit_counterlde_i_a3_0_1); - - cnv_done_RNO : OR2 - port map(A => cnv_sync_r_i_0, B => cnv_sync, Y => - cnv_done_1); - - \shift_reg_6[2]\ : DFN1E1C0 - port map(D => \shift_reg_6[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[2]_net_1\); - - \shift_reg_3[5]\ : DFN1E1C0 - port map(D => \shift_reg_3[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[5]_net_1\); - - \sample_7[6]\ : DFN1E1 - port map(D => \shift_reg_7[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(6)); - - \sample_7[10]\ : DFN1E1 - port map(D => \shift_reg_7[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(10)); - - \sample_6[6]\ : DFN1E1 - port map(D => \shift_reg_6[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(6)); - - \sample_0[11]\ : DFN1E1 - port map(D => \shift_reg_0[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(11)); - - \cnv_cycle_counter_RNIOMS[2]\ : OR3C - port map(A => un2_cnv_runlto8_1, B => un2_cnv_runlto8_0, C - => un2_cnv_runlto8_2, Y => cnv_s_0_sqmuxa); - - \shift_reg_0[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(0), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[0]_net_1\); - - \sample_0[0]\ : DFN1E1 - port map(D => sdo_adc_c(0), CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(0)); - - \sample_5[4]\ : DFN1E1 - port map(D => \shift_reg_5[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(4)); - - \sample_7[9]\ : DFN1E1 - port map(D => \shift_reg_7[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(9)); - - \sample_4[9]\ : DFN1E1 - port map(D => \shift_reg_4[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(9)); - - \cnv_cycle_counter[6]\ : DFN1C0 - port map(D => cnv_cycle_counter_n6, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[6]_net_1\); - - \shift_reg_2[12]\ : DFN1E1C0 - port map(D => \shift_reg_2[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[12]_net_1\); - - \sample_bit_counter_1[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_1[0]_net_1\); - - \sample_5[9]\ : DFN1E1 - port map(D => \shift_reg_5[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(9)); - - \shift_reg_7[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(7), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[0]_net_1\); - - SYNC_FF_run : SYNC_FF_1 - port map(sample_bit_counter_0(0) => - \sample_bit_counter_0[0]_net_1\, SYNC_FF_1_VCC => - AD7688_drvr_VCC, rstn => rstn, lclk_c => lclk_c, - sample_bit_counter_n0 => sample_bit_counter_n0, - cnv_done_i => cnv_done_i, N_36 => N_36); - - \shift_reg_1[1]\ : DFN1E1C0 - port map(D => \shift_reg_1[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[1]_net_1\); - - \shift_reg_3[9]\ : DFN1E1C0 - port map(D => \shift_reg_3[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_3[9]_net_1\); - - \sample_5[7]\ : DFN1E1 - port map(D => \shift_reg_5[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(7)); - - \sample_bit_counter[5]\ : DFN1E0C0 - port map(D => N_19, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[5]_net_1\); - - \sample_6[10]\ : DFN1E1 - port map(D => \shift_reg_6[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(10)); - - \sample_3[12]\ : DFN1E1 - port map(D => \shift_reg_3[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(12)); - - \shift_reg_3[6]\ : DFN1E1C0 - port map(D => \shift_reg_3[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[6]_net_1\); - - \sample_5[0]\ : DFN1E1 - port map(D => sdo_adc_c(5), CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(0)); - - \sample_4[7]\ : DFN1E1 - port map(D => \shift_reg_4[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(7)); - - \shift_reg_0[5]\ : DFN1E1C0 - port map(D => \shift_reg_0[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[5]_net_1\); - - \cnv_cycle_counter_RNIAUQ[6]\ : NOR2A - port map(A => \cnv_cycle_counter[6]_net_1\, B => - cnv_cycle_counter_c5, Y => cnv_cycle_counter_c6); - - \sample_bit_counter[4]\ : DFN1E0C0 - port map(D => N_17, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[4]_net_1\); - - \sample_4[12]\ : DFN1E1 - port map(D => \shift_reg_4[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(12)); - - \sample_2[7]\ : DFN1E1 - port map(D => \shift_reg_2[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_2(7)); - - \cnv_cycle_counter_RNO_1[8]\ : OR2B - port map(A => cnv_s_0_sqmuxa, B => - \cnv_cycle_counter[8]_net_1\, Y => N_102); - - \sample_bit_counter_RNIO0M6_0[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_2); - - \shift_reg_7[8]\ : DFN1E1C0 - port map(D => \shift_reg_7[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[8]_net_1\); - - \sample_bit_counter_RNISKS2[1]\ : NOR2B - port map(A => \sample_bit_counter[1]_net_1\, B => - \sample_bit_counter_0[0]_net_1\, Y => N_20); - - GND_i : GND - port map(Y => \GND\); - - \shift_reg_0[3]\ : DFN1E1C0 - port map(D => \shift_reg_0[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[3]_net_1\); - - \shift_reg_6[11]\ : DFN1E1C0 - port map(D => \shift_reg_6[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[11]_net_1\); - - \sample_3[15]\ : DFN1E1 - port map(D => \shift_reg_3[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(15)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \shift_reg_3[8]\ : DFN1E1C0 - port map(D => \shift_reg_3[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[8]_net_1\); - - \shift_reg_4[10]\ : DFN1E1C0 - port map(D => \shift_reg_4[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[10]_net_1\); - - \sample_4[15]\ : DFN1E1 - port map(D => \shift_reg_4[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(15)); - - \shift_reg_5[13]\ : DFN1E1C0 - port map(D => \shift_reg_5[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[13]_net_1\); - - \shift_reg_3[7]\ : DFN1E1C0 - port map(D => \shift_reg_3[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[7]_net_1\); - - \sample_0[2]\ : DFN1E1 - port map(D => \shift_reg_0[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(2)); - - \shift_reg_4[14]\ : DFN1E1C0 - port map(D => \shift_reg_4[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[14]_net_1\); - - \sample_0[5]\ : DFN1E1 - port map(D => \shift_reg_0[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(5)); - - \sample_3[13]\ : DFN1E1 - port map(D => \shift_reg_3[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(13)); - - \sample_2[5]\ : DFN1E1 - port map(D => \shift_reg_2[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(5)); - - \shift_reg_2[5]\ : DFN1E1C0 - port map(D => \shift_reg_2[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[5]_net_1\); - - \sample_4[13]\ : DFN1E1 - port map(D => \shift_reg_4[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(13)); - - \sample_3[1]\ : DFN1E1 - port map(D => \shift_reg_3[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(1)); - - \cnv_cycle_counter_RNILTB[2]\ : OA1 - port map(A => \cnv_cycle_counter[2]_net_1\, B => - \cnv_cycle_counter[3]_net_1\, C => - \cnv_cycle_counter[7]_net_1\, Y => un2_cnv_runlto8_2); - - \cnv_cycle_counter_RNICPA[2]\ : NOR2B - port map(A => cnv_cycle_counter_c1, B => - \cnv_cycle_counter[2]_net_1\, Y => cnv_cycle_counter_c2); - - \sample_0[1]\ : DFN1E1 - port map(D => \shift_reg_0[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(1)); - - \sample_bit_counter_RNIO0M6_3[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_3); - - \sample_0[10]\ : DFN1E1 - port map(D => \shift_reg_0[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(10)); - - \shift_reg_0[2]\ : DFN1E1C0 - port map(D => \shift_reg_0[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[2]_net_1\); - - \sample_2[12]\ : DFN1E1 - port map(D => \shift_reg_2[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(12)); - - \sample_6[0]\ : DFN1E1 - port map(D => sdo_adc_c(6), CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(0)); - - \shift_reg_3[12]\ : DFN1E1C0 - port map(D => \shift_reg_3[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[12]_net_1\); - - \sample_val\ : DFN1C0 - port map(D => \sample_bit_counter_RNIU4A5[5]_net_1\, CLK - => lclk_c, CLR => rstn, Q => sample_val); - - \cnv_cycle_counter_RNO[3]\ : XA1 - port map(A => \cnv_cycle_counter[3]_net_1\, B => - cnv_cycle_counter_c2, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n3); - - \sample_3[11]\ : DFN1E1 - port map(D => \shift_reg_3[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(11)); - - \sample_0[9]\ : DFN1E1 - port map(D => \shift_reg_0[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(9)); - - \shift_reg_5[8]\ : DFN1E1C0 - port map(D => \shift_reg_5[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[8]_net_1\); - - \sample_bit_counter_RNO[4]\ : NOR3B - port map(A => N_35, B => N_23, C => N_36, Y => N_17); - - \cnv_cycle_counter[3]\ : DFN1C0 - port map(D => cnv_cycle_counter_n3, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[3]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - \sample_4[11]\ : DFN1E1 - port map(D => \shift_reg_4[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(11)); - - \shift_reg_7[12]\ : DFN1E1C0 - port map(D => \shift_reg_7[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[12]_net_1\); - - \sample_6[7]\ : DFN1E1 - port map(D => \shift_reg_6[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(7)); - - \sample_2[9]\ : DFN1E1 - port map(D => \shift_reg_2[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_2(9)); - - \cnv_cycle_counter_RNO_0[8]\ : NOR2B - port map(A => \cnv_cycle_counter[7]_net_1\, B => - cnv_s_0_sqmuxa, Y => cnv_cycle_counter_32_0); - - \shift_reg_6[1]\ : DFN1E1C0 - port map(D => \shift_reg_6[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[1]_net_1\); - - \shift_reg_7[7]\ : DFN1E1C0 - port map(D => \shift_reg_7[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[7]_net_1\); - - \sample_2[15]\ : DFN1E1 - port map(D => \shift_reg_2[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(15)); - - \sample_bit_counter_0[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_0[0]_net_1\); - - \shift_reg_6[3]\ : DFN1E1C0 - port map(D => \shift_reg_6[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[3]_net_1\); - - \sample_6[4]\ : DFN1E1 - port map(D => \shift_reg_6[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(4)); - - \sample_bit_counter_RNIO0M6[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_0); - - \sample_4[3]\ : DFN1E1 - port map(D => \shift_reg_4[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(3)); - - \sample_1[9]\ : DFN1E1 - port map(D => \shift_reg_1[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(9)); - - \shift_reg_5[5]\ : DFN1E1C0 - port map(D => \shift_reg_5[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[5]_net_1\); - - \cnv_cycle_counter_RNIPJI[4]\ : NOR2B - port map(A => cnv_cycle_counter_c3, B => - \cnv_cycle_counter[4]_net_1\, Y => cnv_cycle_counter_c4); - - \cnv_cycle_counter[7]\ : DFN1C0 - port map(D => cnv_cycle_counter_n7, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[7]_net_1\); - - \sample_1[14]\ : DFN1E1 - port map(D => \shift_reg_1[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(14)); - - \shift_reg_2[11]\ : DFN1E1C0 - port map(D => \shift_reg_2[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[11]_net_1\); - - \shift_reg_7[3]\ : DFN1E1C0 - port map(D => \shift_reg_7[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[3]_net_1\); - - \shift_reg_5[10]\ : DFN1E1C0 - port map(D => \shift_reg_5[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[10]_net_1\); - - \shift_reg_3[4]\ : DFN1E1C0 - port map(D => \shift_reg_3[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[4]_net_1\); - - \sample_2[13]\ : DFN1E1 - port map(D => \shift_reg_2[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(13)); - - \sample_3[0]\ : DFN1E1 - port map(D => sdo_adc_c(3), CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(0)); - - \shift_reg_0[12]\ : DFN1E1C0 - port map(D => \shift_reg_0[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[12]_net_1\); - - \sample_4[2]\ : DFN1E1 - port map(D => \shift_reg_4[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(2)); - - \sample_bit_counter[1]\ : DFN1E0C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[1]_net_1\); - - \shift_reg_5[14]\ : DFN1E1C0 - port map(D => \shift_reg_5[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[14]_net_1\); - - \sample_7[0]\ : DFN1E1 - port map(D => sdo_adc_c(7), CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(0)); - - \sample_2[3]\ : DFN1E1 - port map(D => \shift_reg_2[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(3)); - - \sample_3[7]\ : DFN1E1 - port map(D => \shift_reg_3[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(7)); - - \sample_7[1]\ : DFN1E1 - port map(D => \shift_reg_7[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(1)); - - \sample_2[11]\ : DFN1E1 - port map(D => \shift_reg_2[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(11)); - - cnv_sync_r : DFN1P0 - port map(D => cnv_sync_i, CLK => lclk_c, PRE => rstn, Q => - cnv_sync_r_i_0); - - \shift_reg_1[9]\ : DFN1E1C0 - port map(D => \shift_reg_1[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[9]_net_1\); - - \shift_reg_6[13]\ : DFN1E1C0 - port map(D => \shift_reg_6[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[13]_net_1\); - - \sample_6[1]\ : DFN1E1 - port map(D => \shift_reg_6[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(1)); - - \shift_reg_0[8]\ : DFN1E1C0 - port map(D => \shift_reg_0[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[8]_net_1\); - - \sample_3[10]\ : DFN1E1 - port map(D => \shift_reg_3[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(10)); - - \shift_reg_4[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(4), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[0]_net_1\); - - SYNC_FF_cnv : SYNC_FF - port map(cnv_ch1_c => \cnv_ch1_c\, rstn => rstn, lclk_c => - lclk_c, cnv_sync => cnv_sync, cnv_sync_i => cnv_sync_i); - - \shift_reg_2[2]\ : DFN1E1C0 - port map(D => \shift_reg_2[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[2]_net_1\); - - \shift_reg_1[3]\ : DFN1E1C0 - port map(D => \shift_reg_1[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[3]_net_1\); - - \shift_reg_1[12]\ : DFN1E1C0 - port map(D => \shift_reg_1[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[12]_net_1\); - - \sample_7[2]\ : DFN1E1 - port map(D => \shift_reg_7[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(2)); - - \sample_bit_counter_RNO_0[4]\ : AO1 - port map(A => \sample_bit_counter[3]_net_1\, B => N_21, C - => \sample_bit_counter[4]_net_1\, Y => N_35); - - \sample_4[10]\ : DFN1E1 - port map(D => \shift_reg_4[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_4(10)); - - \sample_3[8]\ : DFN1E1 - port map(D => \shift_reg_3[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(8)); - - \shift_reg_3[3]\ : DFN1E1C0 - port map(D => \shift_reg_3[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[3]_net_1\); - - \shift_reg_1[8]\ : DFN1E1C0 - port map(D => \shift_reg_1[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[8]_net_1\); - - \sample_bit_counter_3[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_3[0]_net_1\); - - \cnv_cycle_counter[8]\ : DFN1C0 - port map(D => cnv_cycle_counter_n8, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[8]_net_1\); - - \sample_bit_counter[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter[0]_net_1\); - - \sample_bit_counter_RNIO0M6_1[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa_4); - - \sample_1[1]\ : DFN1E1 - port map(D => \shift_reg_1[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(1)); - - \shift_reg_4[1]\ : DFN1E1C0 - port map(D => \shift_reg_4[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[1]_net_1\); - - \cnv_cycle_counter_RNO[0]\ : NOR2A - port map(A => cnv_s_0_sqmuxa, B => - \cnv_cycle_counter[0]_net_1\, Y => cnv_cycle_counter_n0); - - \sample_5[14]\ : DFN1E1 - port map(D => \shift_reg_5[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(14)); - - \shift_reg_3[1]\ : DFN1E1C0 - port map(D => \shift_reg_3[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[1]_net_1\); - - \shift_reg_2[8]\ : DFN1E1C0 - port map(D => \shift_reg_2[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[8]_net_1\); - - \sample_2[8]\ : DFN1E1 - port map(D => \shift_reg_2[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_2(8)); - - \shift_reg_3[11]\ : DFN1E1C0 - port map(D => \shift_reg_3[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[11]_net_1\); - - \shift_reg_0[4]\ : DFN1E1C0 - port map(D => \shift_reg_0[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[4]_net_1\); - - \sample_4[5]\ : DFN1E1 - port map(D => \shift_reg_4[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(5)); - - \sample_0[4]\ : DFN1E1 - port map(D => \shift_reg_0[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(4)); - - \shift_reg_7[11]\ : DFN1E1C0 - port map(D => \shift_reg_7[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[11]_net_1\); - - \shift_reg_3[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(3), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[0]_net_1\); - - \sample_3[4]\ : DFN1E1 - port map(D => \shift_reg_3[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(4)); - - \sample_5[5]\ : DFN1E1 - port map(D => \shift_reg_5[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(5)); - - \shift_reg_1[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(1), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_1[0]_net_1\); - - \shift_reg_4[9]\ : DFN1E1C0 - port map(D => \shift_reg_4[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[9]_net_1\); - - \shift_reg_1[6]\ : DFN1E1C0 - port map(D => \shift_reg_1[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[6]_net_1\); - - \sample_4[1]\ : DFN1E1 - port map(D => \shift_reg_4[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(1)); - - \shift_reg_2[9]\ : DFN1E1C0 - port map(D => \shift_reg_2[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[9]_net_1\); - - \shift_reg_4[2]\ : DFN1E1C0 - port map(D => \shift_reg_4[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[2]_net_1\); - - \sample_7[8]\ : DFN1E1 - port map(D => \shift_reg_7[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(8)); - - \sample_7[14]\ : DFN1E1 - port map(D => \shift_reg_7[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(14)); - - \sample_2[10]\ : DFN1E1 - port map(D => \shift_reg_2[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(10)); - - \shift_reg_6[10]\ : DFN1E1C0 - port map(D => \shift_reg_6[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[10]_net_1\); - - \shift_reg_3[2]\ : DFN1E1C0 - port map(D => \shift_reg_3[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[2]_net_1\); - - \shift_reg_4[12]\ : DFN1E1C0 - port map(D => \shift_reg_4[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[12]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - \shift_reg_7[4]\ : DFN1E1C0 - port map(D => \shift_reg_7[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[4]_net_1\); - - \shift_reg_2[13]\ : DFN1E1C0 - port map(D => \shift_reg_2[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[13]_net_1\); - - \sample_6[5]\ : DFN1E1 - port map(D => \shift_reg_6[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(5)); - - \shift_reg_6[14]\ : DFN1E1C0 - port map(D => \shift_reg_6[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[14]_net_1\); - - \cnv_cycle_counter_RNO[6]\ : XA1A - port map(A => \cnv_cycle_counter[6]_net_1\, B => - cnv_cycle_counter_c5, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n6); - - \sample_bit_counter_2[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_2[0]_net_1\); - - \sample_5[2]\ : DFN1E1 - port map(D => \shift_reg_5[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(2)); - - \sample_bit_counter_RNIU4A5[5]\ : NOR2 - port map(A => \sample_bit_counter[5]_net_1\, B => N_23, Y - => \sample_bit_counter_RNIU4A5[5]_net_1\); - - \sample_5[8]\ : DFN1E1 - port map(D => \shift_reg_5[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(8)); - - \sample_1[12]\ : DFN1E1 - port map(D => \shift_reg_1[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(12)); - - \shift_reg_2[6]\ : DFN1E1C0 - port map(D => \shift_reg_2[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[6]_net_1\); - - \shift_reg_0[11]\ : DFN1E1C0 - port map(D => \shift_reg_0[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[11]_net_1\); - - \sample_6[14]\ : DFN1E1 - port map(D => \shift_reg_6[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(14)); - - cnv_s_RNO_0 : OA1 - port map(A => cnv_cycle_counter_c3, B => un3_cnv_runlto5_0, - C => \cnv_cycle_counter[6]_net_1\, Y => un3_cnv_runlt8); - - \shift_reg_4[8]\ : DFN1E1C0 - port map(D => \shift_reg_4[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[8]_net_1\); - - cnv_s_RNO_1 : OR2 - port map(A => \cnv_cycle_counter[8]_net_1\, B => - \cnv_cycle_counter[7]_net_1\, Y => un3_cnv_runlto8_0); - - \cnv_cycle_counter[2]\ : DFN1C0 - port map(D => cnv_cycle_counter_n2, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[2]_net_1\); - - \sample_7[7]\ : DFN1E1 - port map(D => \shift_reg_7[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(7)); - - \sample_3[5]\ : DFN1E1 - port map(D => \shift_reg_3[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(5)); - - \shift_reg_7[1]\ : DFN1E1C0 - port map(D => \shift_reg_7[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[1]_net_1\); - - \sample_7[3]\ : DFN1E1 - port map(D => \shift_reg_7[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(3)); - - \sample_3[6]\ : DFN1E1 - port map(D => \shift_reg_3[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(6)); - - \cnv_cycle_counter_RNO[5]\ : XA1 - port map(A => \cnv_cycle_counter[5]_net_1\, B => - cnv_cycle_counter_c4, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n5); - - \shift_reg_5[9]\ : DFN1E1C0 - port map(D => \shift_reg_5[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[9]_net_1\); - - \shift_reg_4[6]\ : DFN1E1C0 - port map(D => \shift_reg_4[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[6]_net_1\); - - \shift_reg_1[4]\ : DFN1E1C0 - port map(D => \shift_reg_1[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[4]_net_1\); - - \shift_reg_4[5]\ : DFN1E1C0 - port map(D => \shift_reg_4[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[5]_net_1\); - - \sample_2[1]\ : DFN1E1 - port map(D => \shift_reg_2[0]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(1)); - - \sample_1[15]\ : DFN1E1 - port map(D => \shift_reg_1[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(15)); - - sck : DFN1P0 - port map(D => \sample_bit_counter_i[0]\, CLK => lclk_c, PRE - => rstn, Q => sck_ch1_c); - - \shift_reg_6[8]\ : DFN1E1C0 - port map(D => \shift_reg_6[7]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[8]_net_1\); - - \shift_reg_5[4]\ : DFN1E1C0 - port map(D => \shift_reg_5[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[4]_net_1\); - - \cnv_cycle_counter_RNO[4]\ : XA1 - port map(A => \cnv_cycle_counter[4]_net_1\, B => - cnv_cycle_counter_c3, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n4); - - \sample_bit_counter_RNO[2]\ : XA1B - port map(A => N_20, B => \sample_bit_counter[2]_net_1\, C - => N_36, Y => N_13); - - \sample_5[6]\ : DFN1E1 - port map(D => \shift_reg_5[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(6)); - - \sample_bit_counter_4[0]\ : DFN1E0C0 - port map(D => sample_bit_counter_n0, CLK => lclk_c, CLR => - rstn, E => N_6, Q => \sample_bit_counter_4[0]_net_1\); - - \shift_reg_0[6]\ : DFN1E1C0 - port map(D => \shift_reg_0[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[6]_net_1\); - - \sample_1[3]\ : DFN1E1 - port map(D => \shift_reg_1[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(3)); - - \shift_reg_5[3]\ : DFN1E1C0 - port map(D => \shift_reg_5[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[3]_net_1\); - - \sample_3[2]\ : DFN1E1 - port map(D => \shift_reg_3[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(2)); - - \sample_5[3]\ : DFN1E1 - port map(D => \shift_reg_5[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_5(3)); - - \shift_reg_1[11]\ : DFN1E1C0 - port map(D => \shift_reg_1[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[11]_net_1\); - - \sample_bit_counter_RNO[5]\ : NOR2 - port map(A => N_36, B => N_23, Y => N_19); - - \cnv_cycle_counter[5]\ : DFN1C0 - port map(D => cnv_cycle_counter_n5, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[5]_net_1\); - - \sample_1[7]\ : DFN1E1 - port map(D => \shift_reg_1[6]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(7)); - - \sample_1[13]\ : DFN1E1 - port map(D => \shift_reg_1[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(13)); - - sck_RNO : INV - port map(A => \sample_bit_counter_0[0]_net_1\, Y => - \sample_bit_counter_i[0]\); - - \shift_reg_5[2]\ : DFN1E1C0 - port map(D => \shift_reg_5[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[2]_net_1\); - - \sample_bit_counter_RNO[1]\ : NOR3 - port map(A => N_38, B => N_36, C => N_20, Y => N_11); - - \sample_6[8]\ : DFN1E1 - port map(D => \shift_reg_6[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_6(8)); - - \sample_1[2]\ : DFN1E1 - port map(D => \shift_reg_1[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(2)); - - \sample_0[8]\ : DFN1E1 - port map(D => \shift_reg_0[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(8)); - - \sample_0[14]\ : DFN1E1 - port map(D => \shift_reg_0[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(14)); - - \sample_5[12]\ : DFN1E1 - port map(D => \shift_reg_5[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(12)); - - \shift_reg_0[9]\ : DFN1E1C0 - port map(D => \shift_reg_0[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[9]_net_1\); - - \sample_1[11]\ : DFN1E1 - port map(D => \shift_reg_1[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(11)); - - \shift_reg_5[7]\ : DFN1E1C0 - port map(D => \shift_reg_5[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_5[7]_net_1\); - - \sample_0[6]\ : DFN1E1 - port map(D => \shift_reg_0[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_0(6)); - - \shift_reg_2[10]\ : DFN1E1C0 - port map(D => \shift_reg_2[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[10]_net_1\); - - \shift_reg_5[12]\ : DFN1E1C0 - port map(D => \shift_reg_5[11]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[12]_net_1\); - - \shift_reg_3[13]\ : DFN1E1C0 - port map(D => \shift_reg_3[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[13]_net_1\); - - cnv_done : DFN1P0 - port map(D => cnv_done_1, CLK => lclk_c, PRE => rstn, Q => - cnv_done_i); - - \shift_reg_2[1]\ : DFN1E1C0 - port map(D => \shift_reg_2[0]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[1]_net_1\); - - \sample_7[4]\ : DFN1E1 - port map(D => \shift_reg_7[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(4)); - - \sample_4[6]\ : DFN1E1 - port map(D => \shift_reg_4[5]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(6)); - - \shift_reg_1[2]\ : DFN1E1C0 - port map(D => \shift_reg_1[1]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[2]_net_1\); - - \shift_reg_7[13]\ : DFN1E1C0 - port map(D => \shift_reg_7[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[13]_net_1\); - - \shift_reg_2[14]\ : DFN1E1C0 - port map(D => \shift_reg_2[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_2[14]_net_1\); - - \shift_reg_6[5]\ : DFN1E1C0 - port map(D => \shift_reg_6[4]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[5]_net_1\); - - \sample_4[8]\ : DFN1E1 - port map(D => \shift_reg_4[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(8)); - - \sample_5[15]\ : DFN1E1 - port map(D => \shift_reg_5[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(15)); - - \shift_reg_2[3]\ : DFN1E1C0 - port map(D => \shift_reg_2[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[3]_net_1\); - - \cnv_cycle_counter_RNI727[1]\ : NOR2B - port map(A => \cnv_cycle_counter[1]_net_1\, B => - \cnv_cycle_counter[0]_net_1\, Y => cnv_cycle_counter_c1); - - cnv_s_RNO : OAI1 - port map(A => un3_cnv_runlt8, B => un3_cnv_runlto8_0, C => - cnv_s_0_sqmuxa, Y => \cnv_s_RNO\); - - \shift_reg_6[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(6), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[0]_net_1\); - - \cnv_cycle_counter[0]\ : DFN1C0 - port map(D => cnv_cycle_counter_n0, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[0]_net_1\); - - \shift_reg_2[7]\ : DFN1E1C0 - port map(D => \shift_reg_2[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[7]_net_1\); - - \shift_reg_6[4]\ : DFN1E1C0 - port map(D => \shift_reg_6[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_4[0]_net_1\, Q => - \shift_reg_6[4]_net_1\); - - \shift_reg_2[4]\ : DFN1E1C0 - port map(D => \shift_reg_2[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_2[4]_net_1\); - - \sample_6[9]\ : DFN1E1 - port map(D => \shift_reg_6[8]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_6(9)); - - \cnv_cycle_counter_RNI1NM[5]\ : OR2B - port map(A => cnv_cycle_counter_c4, B => - \cnv_cycle_counter[5]_net_1\, Y => cnv_cycle_counter_c5); - - \shift_reg_4[4]\ : DFN1E1C0 - port map(D => \shift_reg_4[3]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[4]_net_1\); - - \sample_7[12]\ : DFN1E1 - port map(D => \shift_reg_7[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(12)); - - \cnv_cycle_counter_RNIIKE[3]\ : NOR2B - port map(A => cnv_cycle_counter_c2, B => - \cnv_cycle_counter[3]_net_1\, Y => cnv_cycle_counter_c3); - - \shift_reg_4[3]\ : DFN1E1C0 - port map(D => \shift_reg_4[2]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[3]_net_1\); - - \shift_reg_4[11]\ : DFN1E1C0 - port map(D => \shift_reg_4[10]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[11]_net_1\); - - \sample_bit_counter[3]\ : DFN1E0C0 - port map(D => N_15, CLK => lclk_c, CLR => rstn, E => N_6, Q - => \sample_bit_counter[3]_net_1\); - - \sample_5[13]\ : DFN1E1 - port map(D => \shift_reg_5[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(13)); - - \shift_reg_0[7]\ : DFN1E1C0 - port map(D => \shift_reg_0[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[7]_net_1\); - - cnv_s_RNO_2 : OR2 - port map(A => \cnv_cycle_counter[4]_net_1\, B => - \cnv_cycle_counter[5]_net_1\, Y => un3_cnv_runlto5_0); - - \shift_reg_0[13]\ : DFN1E1C0 - port map(D => \shift_reg_0[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_0[0]_net_1\, Q => - \shift_reg_0[13]_net_1\); - - \sample_2[2]\ : DFN1E1 - port map(D => \shift_reg_2[1]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_2(2)); - - \sample_1[8]\ : DFN1E1 - port map(D => \shift_reg_1[7]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(8)); - - \sample_1[5]\ : DFN1E1 - port map(D => \shift_reg_1[4]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(5)); - - \sample_6[12]\ : DFN1E1 - port map(D => \shift_reg_6[11]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(12)); - - \cnv_cycle_counter_RNO[7]\ : XA1 - port map(A => \cnv_cycle_counter[7]_net_1\, B => - cnv_cycle_counter_c6, C => cnv_s_0_sqmuxa, Y => - cnv_cycle_counter_n7); - - \sample_bit_counter_RNIO0M6_4[5]\ : NOR2B - port map(A => \sample_bit_counter_RNIU4A5[5]_net_1\, B => - rstn, Y => sample_0_0_sqmuxa); - - \sample_7[15]\ : DFN1E1 - port map(D => \shift_reg_7[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(15)); - - \sample_4[0]\ : DFN1E1 - port map(D => sdo_adc_c(4), CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_4(0)); - - \shift_reg_5[0]\ : DFN1E1C0 - port map(D => sdo_adc_c(5), CLK => lclk_c, CLR => rstn, E - => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_5[0]_net_1\); - - \sample_3[3]\ : DFN1E1 - port map(D => \shift_reg_3[2]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(3)); - - \sample_5[11]\ : DFN1E1 - port map(D => \shift_reg_5[10]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_5(11)); - - \shift_reg_4[7]\ : DFN1E1C0 - port map(D => \shift_reg_4[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_3[0]_net_1\, Q => - \shift_reg_4[7]_net_1\); - - \shift_reg_6[6]\ : DFN1E1C0 - port map(D => \shift_reg_6[5]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[6]_net_1\); - - \sample_4[4]\ : DFN1E1 - port map(D => \shift_reg_4[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(4)); - - \sample_6[15]\ : DFN1E1 - port map(D => \shift_reg_6[14]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_4, Q => sample_6(15)); - - \shift_reg_3[10]\ : DFN1E1C0 - port map(D => \shift_reg_3[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[10]_net_1\); - - \sample_1[10]\ : DFN1E1 - port map(D => \shift_reg_1[9]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_0, Q => sample_1(10)); - - \sample_3[14]\ : DFN1E1 - port map(D => \shift_reg_3[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_2, Q => sample_3(14)); - - \sample_7[13]\ : DFN1E1 - port map(D => \shift_reg_7[12]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa, Q => sample_7(13)); - - \shift_reg_7[9]\ : DFN1E1C0 - port map(D => \shift_reg_7[8]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[9]_net_1\); - - \sample_1[4]\ : DFN1E1 - port map(D => \shift_reg_1[3]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_1, Q => sample_1(4)); - - \cnv_cycle_counter[1]\ : DFN1C0 - port map(D => cnv_cycle_counter_n1, CLK => clk49_152MHz_c, - CLR => rstn, Q => \cnv_cycle_counter[1]_net_1\); - - \shift_reg_7[10]\ : DFN1E1C0 - port map(D => \shift_reg_7[9]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_7[10]_net_1\); - - \sample_4[14]\ : DFN1E1 - port map(D => \shift_reg_4[13]_net_1\, CLK => lclk_c, E => - sample_0_0_sqmuxa_3, Q => sample_4(14)); - - \shift_reg_6[7]\ : DFN1E1C0 - port map(D => \shift_reg_6[6]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter[0]_net_1\, Q => - \shift_reg_6[7]_net_1\); - - \shift_reg_3[14]\ : DFN1E1C0 - port map(D => \shift_reg_3[13]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_2[0]_net_1\, Q => - \shift_reg_3[14]_net_1\); - - \shift_reg_1[13]\ : DFN1E1C0 - port map(D => \shift_reg_1[12]_net_1\, CLK => lclk_c, CLR - => rstn, E => \sample_bit_counter_1[0]_net_1\, Q => - \shift_reg_1[13]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_lfr_wf_picker_ip is - - port( nb_snapshot_param : in std_logic_vector(10 downto 0); - coarse_time_i : in std_logic_vector(0 to 0); - delta_f2_f0 : in std_logic_vector(9 downto 0); - delta_f2_f1 : in std_logic_vector(9 downto 0); - delta_snapshot : in std_logic_vector(15 downto 0); - coarse_time : in std_logic_vector(0 to 0); - status_new_err : out std_logic_vector(3 downto 0); - hwdata : out std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0); - addr_data_f1 : in std_logic_vector(31 downto 0); - addr_data_f2 : in std_logic_vector(31 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0); - l1_0_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - bco_msb_1_m : in std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93); - hgrant : in std_logic_vector(3 to 3); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - bco_msb_1 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - hmaster_0 : in std_logic_vector(1 to 1); - hsize : out std_logic_vector(1 downto 0); - nhmaster_1_i : in std_logic_vector(0 to 0); - iosn_1 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - iosn_2 : in std_logic_vector(93 to 93); - htrans : out std_logic_vector(1 downto 0); - hburst : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0); - sdo_adc_c : in std_logic_vector(7 downto 0); - data_shaping_R0 : in std_logic; - data_shaping_R0_0 : in std_logic; - enable_f0 : in std_logic; - burst_f0 : in std_logic; - data_shaping_R1 : in std_logic; - data_shaping_R1_0 : in std_logic; - enable_f1 : in std_logic; - burst_f1 : in std_logic; - enable_f2 : in std_logic; - burst_f2 : in std_logic; - enable_f3 : in std_logic; - m26_m1_e : out std_logic; - m19_a1_6_i_0 : out std_logic; - m19_a0_6_i_0 : out std_logic; - m19_0_N_15_i_0_li : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - Lock_RNIU86D : out std_logic; - hbusreq_i_3 : out std_logic; - arb_1 : in std_logic; - un1_dmain_6 : out std_logic; - hwrite : out std_logic; - IdlePhase : out std_logic; - lpp_top_lfr_wf_picker_ip_GND : in std_logic; - sck_ch1_c : out std_logic; - cnv_ch1_c : out std_logic; - clk49_152MHz_c : in std_logic; - lpp_top_lfr_wf_picker_ip_VCC : in std_logic; - data_shaping_SP0 : in std_logic; - data_shaping_SP1 : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end lpp_top_lfr_wf_picker_ip; - -architecture DEF_ARCH of lpp_top_lfr_wf_picker_ip is - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO18 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component IIR_CEL_CTRLR_v2 - port( sample_filter_v2_out_0 : out std_logic; - sample_filter_v2_out_1 : out std_logic; - sample_filter_v2_out_2 : out std_logic; - sample_filter_v2_out_3 : out std_logic; - sample_filter_v2_out_4 : out std_logic; - sample_filter_v2_out_5 : out std_logic; - sample_filter_v2_out_6 : out std_logic; - sample_filter_v2_out_7 : out std_logic; - sample_filter_v2_out_8 : out std_logic; - sample_filter_v2_out_9 : out std_logic; - sample_filter_v2_out_10 : out std_logic; - sample_filter_v2_out_11 : out std_logic; - sample_filter_v2_out_12 : out std_logic; - sample_filter_v2_out_13 : out std_logic; - sample_filter_v2_out_14 : out std_logic; - sample_filter_v2_out_15 : out std_logic; - sample_filter_v2_out_18 : out std_logic; - sample_filter_v2_out_19 : out std_logic; - sample_filter_v2_out_20 : out std_logic; - sample_filter_v2_out_21 : out std_logic; - sample_filter_v2_out_22 : out std_logic; - sample_filter_v2_out_23 : out std_logic; - sample_filter_v2_out_24 : out std_logic; - sample_filter_v2_out_25 : out std_logic; - sample_filter_v2_out_26 : out std_logic; - sample_filter_v2_out_27 : out std_logic; - sample_filter_v2_out_28 : out std_logic; - sample_filter_v2_out_29 : out std_logic; - sample_filter_v2_out_30 : out std_logic; - sample_filter_v2_out_31 : out std_logic; - sample_filter_v2_out_32 : out std_logic; - sample_filter_v2_out_33 : out std_logic; - sample_filter_v2_out_36 : out std_logic; - sample_filter_v2_out_37 : out std_logic; - sample_filter_v2_out_38 : out std_logic; - sample_filter_v2_out_39 : out std_logic; - sample_filter_v2_out_40 : out std_logic; - sample_filter_v2_out_41 : out std_logic; - sample_filter_v2_out_42 : out std_logic; - sample_filter_v2_out_43 : out std_logic; - sample_filter_v2_out_44 : out std_logic; - sample_filter_v2_out_45 : out std_logic; - sample_filter_v2_out_46 : out std_logic; - sample_filter_v2_out_47 : out std_logic; - sample_filter_v2_out_48 : out std_logic; - sample_filter_v2_out_49 : out std_logic; - sample_filter_v2_out_50 : out std_logic; - sample_filter_v2_out_51 : out std_logic; - sample_filter_v2_out_54 : out std_logic; - sample_filter_v2_out_55 : out std_logic; - sample_filter_v2_out_56 : out std_logic; - sample_filter_v2_out_57 : out std_logic; - sample_filter_v2_out_58 : out std_logic; - sample_filter_v2_out_59 : out std_logic; - sample_filter_v2_out_60 : out std_logic; - sample_filter_v2_out_61 : out std_logic; - sample_filter_v2_out_62 : out std_logic; - sample_filter_v2_out_63 : out std_logic; - sample_filter_v2_out_64 : out std_logic; - sample_filter_v2_out_65 : out std_logic; - sample_filter_v2_out_66 : out std_logic; - sample_filter_v2_out_67 : out std_logic; - sample_filter_v2_out_68 : out std_logic; - sample_filter_v2_out_69 : out std_logic; - sample_filter_v2_out_90 : out std_logic; - sample_filter_v2_out_91 : out std_logic; - sample_filter_v2_out_92 : out std_logic; - sample_filter_v2_out_93 : out std_logic; - sample_filter_v2_out_94 : out std_logic; - sample_filter_v2_out_95 : out std_logic; - sample_filter_v2_out_96 : out std_logic; - sample_filter_v2_out_97 : out std_logic; - sample_filter_v2_out_98 : out std_logic; - sample_filter_v2_out_99 : out std_logic; - sample_filter_v2_out_100 : out std_logic; - sample_filter_v2_out_101 : out std_logic; - sample_filter_v2_out_102 : out std_logic; - sample_filter_v2_out_103 : out std_logic; - sample_filter_v2_out_104 : out std_logic; - sample_filter_v2_out_105 : out std_logic; - sample_filter_v2_out_108 : out std_logic; - sample_filter_v2_out_126 : out std_logic; - sample_filter_v2_out_109 : out std_logic; - sample_filter_v2_out_127 : out std_logic; - sample_filter_v2_out_110 : out std_logic; - sample_filter_v2_out_128 : out std_logic; - sample_filter_v2_out_111 : out std_logic; - sample_filter_v2_out_129 : out std_logic; - sample_filter_v2_out_112 : out std_logic; - sample_filter_v2_out_130 : out std_logic; - sample_filter_v2_out_113 : out std_logic; - sample_filter_v2_out_131 : out std_logic; - sample_filter_v2_out_114 : out std_logic; - sample_filter_v2_out_132 : out std_logic; - sample_filter_v2_out_115 : out std_logic; - sample_filter_v2_out_133 : out std_logic; - sample_filter_v2_out_116 : out std_logic; - sample_filter_v2_out_134 : out std_logic; - sample_filter_v2_out_117 : out std_logic; - sample_filter_v2_out_135 : out std_logic; - sample_filter_v2_out_118 : out std_logic; - sample_filter_v2_out_136 : out std_logic; - sample_filter_v2_out_119 : out std_logic; - sample_filter_v2_out_137 : out std_logic; - sample_filter_v2_out_120 : out std_logic; - sample_filter_v2_out_138 : out std_logic; - sample_filter_v2_out_121 : out std_logic; - sample_filter_v2_out_139 : out std_logic; - sample_filter_v2_out_122 : out std_logic; - sample_filter_v2_out_140 : out std_logic; - sample_filter_v2_out_123 : out std_logic; - sample_filter_v2_out_141 : out std_logic; - sample_4 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_5 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_3 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_2 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_6 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_1 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - sample_7 : in std_logic_vector(15 downto 0) := (others => 'U'); - IIR_CEL_CTRLR_v2_VCC : in std_logic := 'U'; - IIR_CEL_CTRLR_v2_GND : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_filter_v2_out_val : out std_logic; - sample_val_delay : in std_logic := 'U'; - sample_val_delay_5 : in std_logic := 'U'; - sample_val_delay_4 : in std_logic := 'U'; - sample_val_delay_3 : in std_logic := 'U'; - sample_val_delay_2 : in std_logic := 'U'; - sample_val_delay_1 : in std_logic := 'U'; - sample_val_delay_0 : in std_logic := 'U' - ); - end component; - - component AX1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO13 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component Downsampling_6_16_256 - port( sample_f1 : in std_logic_vector(111 downto 80) := (others => 'U'); - sample_f1_wdata_95 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - sample_f3_wdata : out std_logic_vector(95 downto 0); - sample_f1_val : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_f3_val : out std_logic; - sample_f1_val_0 : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component Downsampling_6_16_96 - port( sample_f0 : in std_logic_vector(111 downto 80) := (others => 'U'); - sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f2_wdata : out std_logic_vector(95 downto 0); - sample_f0_val : in std_logic := 'U'; - sample_f0_val_2 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_f2_val : out std_logic; - sample_f0_val_0 : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_waveform - port( status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - status_full_err : out std_logic_vector(3 downto 0); - status_full : out std_logic_vector(3 downto 0); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - status_new_err : out std_logic_vector(3 downto 0); - sample_f3_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - sample_f2_wdata : in std_logic_vector(95 downto 0) := (others => 'U'); - sample_f1_15 : in std_logic := 'U'; - sample_f1_47 : in std_logic := 'U'; - sample_f1_14 : in std_logic := 'U'; - sample_f1_46 : in std_logic := 'U'; - sample_f1_13 : in std_logic := 'U'; - sample_f1_45 : in std_logic := 'U'; - sample_f1_12 : in std_logic := 'U'; - sample_f1_44 : in std_logic := 'U'; - sample_f1_60 : in std_logic := 'U'; - sample_f1_59 : in std_logic := 'U'; - sample_f1_58 : in std_logic := 'U'; - sample_f1_57 : in std_logic := 'U'; - sample_f1_56 : in std_logic := 'U'; - sample_f1_55 : in std_logic := 'U'; - sample_f1_54 : in std_logic := 'U'; - sample_f1_53 : in std_logic := 'U'; - sample_f1_52 : in std_logic := 'U'; - sample_f1_51 : in std_logic := 'U'; - sample_f1_50 : in std_logic := 'U'; - sample_f1_49 : in std_logic := 'U'; - sample_f1_48 : in std_logic := 'U'; - sample_f1_4 : in std_logic := 'U'; - sample_f1_36 : in std_logic := 'U'; - sample_f1_3 : in std_logic := 'U'; - sample_f1_35 : in std_logic := 'U'; - sample_f1_2 : in std_logic := 'U'; - sample_f1_34 : in std_logic := 'U'; - sample_f1_1 : in std_logic := 'U'; - sample_f1_33 : in std_logic := 'U'; - sample_f1_0 : in std_logic := 'U'; - sample_f1_32 : in std_logic := 'U'; - sample_f1_63 : in std_logic := 'U'; - sample_f1_62 : in std_logic := 'U'; - sample_f1_61 : in std_logic := 'U'; - sample_f1_11 : in std_logic := 'U'; - sample_f1_43 : in std_logic := 'U'; - sample_f1_10 : in std_logic := 'U'; - sample_f1_42 : in std_logic := 'U'; - sample_f1_9 : in std_logic := 'U'; - sample_f1_41 : in std_logic := 'U'; - sample_f1_8 : in std_logic := 'U'; - sample_f1_40 : in std_logic := 'U'; - sample_f1_7 : in std_logic := 'U'; - sample_f1_39 : in std_logic := 'U'; - sample_f1_6 : in std_logic := 'U'; - sample_f1_38 : in std_logic := 'U'; - sample_f1_5 : in std_logic := 'U'; - sample_f1_37 : in std_logic := 'U'; - sample_f1_wdata_0 : in std_logic := 'U'; - sample_f1_wdata_1 : in std_logic := 'U'; - sample_f1_wdata_2 : in std_logic := 'U'; - sample_f1_wdata_3 : in std_logic := 'U'; - sample_f1_wdata_4 : in std_logic := 'U'; - sample_f1_wdata_5 : in std_logic := 'U'; - sample_f1_wdata_6 : in std_logic := 'U'; - sample_f1_wdata_7 : in std_logic := 'U'; - sample_f1_wdata_8 : in std_logic := 'U'; - sample_f1_wdata_9 : in std_logic := 'U'; - sample_f1_wdata_10 : in std_logic := 'U'; - sample_f1_wdata_11 : in std_logic := 'U'; - sample_f1_wdata_12 : in std_logic := 'U'; - sample_f1_wdata_13 : in std_logic := 'U'; - sample_f1_wdata_14 : in std_logic := 'U'; - sample_f1_wdata_15 : in std_logic := 'U'; - sample_f1_wdata_48 : in std_logic := 'U'; - sample_f1_wdata_49 : in std_logic := 'U'; - sample_f1_wdata_50 : in std_logic := 'U'; - sample_f1_wdata_51 : in std_logic := 'U'; - sample_f1_wdata_52 : in std_logic := 'U'; - sample_f1_wdata_53 : in std_logic := 'U'; - sample_f1_wdata_54 : in std_logic := 'U'; - sample_f1_wdata_55 : in std_logic := 'U'; - sample_f1_wdata_56 : in std_logic := 'U'; - sample_f1_wdata_57 : in std_logic := 'U'; - sample_f1_wdata_58 : in std_logic := 'U'; - sample_f1_wdata_59 : in std_logic := 'U'; - sample_f1_wdata_60 : in std_logic := 'U'; - sample_f1_wdata_61 : in std_logic := 'U'; - sample_f1_wdata_62 : in std_logic := 'U'; - sample_f1_wdata_63 : in std_logic := 'U'; - sample_f1_wdata_64 : in std_logic := 'U'; - sample_f1_wdata_65 : in std_logic := 'U'; - sample_f1_wdata_66 : in std_logic := 'U'; - sample_f1_wdata_67 : in std_logic := 'U'; - sample_f1_wdata_68 : in std_logic := 'U'; - sample_f1_wdata_69 : in std_logic := 'U'; - sample_f1_wdata_70 : in std_logic := 'U'; - sample_f1_wdata_71 : in std_logic := 'U'; - sample_f1_wdata_72 : in std_logic := 'U'; - sample_f1_wdata_73 : in std_logic := 'U'; - sample_f1_wdata_74 : in std_logic := 'U'; - sample_f1_wdata_75 : in std_logic := 'U'; - sample_f1_wdata_76 : in std_logic := 'U'; - sample_f1_wdata_77 : in std_logic := 'U'; - sample_f1_wdata_78 : in std_logic := 'U'; - sample_f1_wdata_79 : in std_logic := 'U'; - sample_f1_wdata_80 : in std_logic := 'U'; - sample_f1_wdata_81 : in std_logic := 'U'; - sample_f1_wdata_82 : in std_logic := 'U'; - sample_f1_wdata_83 : in std_logic := 'U'; - sample_f1_wdata_84 : in std_logic := 'U'; - sample_f1_wdata_85 : in std_logic := 'U'; - sample_f1_wdata_86 : in std_logic := 'U'; - sample_f1_wdata_87 : in std_logic := 'U'; - sample_f1_wdata_88 : in std_logic := 'U'; - sample_f1_wdata_89 : in std_logic := 'U'; - sample_f1_wdata_90 : in std_logic := 'U'; - sample_f1_wdata_91 : in std_logic := 'U'; - sample_f1_wdata_92 : in std_logic := 'U'; - sample_f1_wdata_93 : in std_logic := 'U'; - sample_f1_wdata_94 : in std_logic := 'U'; - sample_f1_wdata_95 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_0 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_37 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_95 : in std_logic := 'U'; - coarse_time : in std_logic_vector(0 to 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - coarse_time_i : in std_logic_vector(0 to 0) := (others => 'U'); - nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - IdlePhase : out std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - arb_1 : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - Lock_RNIU86D : out std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - m19_0_N_15_i_0_li : in std_logic := 'U'; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - m26_m1_e : out std_logic; - sample_f3_val : in std_logic := 'U'; - enable_f3 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - sample_f1_val_0 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - data_shaping_R0 : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - rstn : in std_logic := 'U'; - sample_f0_val_0 : in std_logic := 'U'; - sample_f2_val : in std_logic := 'U' - ); - end component; - - component Downsampling_8_16_4 - port( sample_f0_0 : out std_logic; - sample_f0_1 : out std_logic; - sample_f0_2 : out std_logic; - sample_f0_3 : out std_logic; - sample_f0_4 : out std_logic; - sample_f0_5 : out std_logic; - sample_f0_6 : out std_logic; - sample_f0_7 : out std_logic; - sample_f0_8 : out std_logic; - sample_f0_9 : out std_logic; - sample_f0_10 : out std_logic; - sample_f0_11 : out std_logic; - sample_f0_12 : out std_logic; - sample_f0_13 : out std_logic; - sample_f0_14 : out std_logic; - sample_f0_15 : out std_logic; - sample_f0_32 : out std_logic; - sample_f0_33 : out std_logic; - sample_f0_34 : out std_logic; - sample_f0_35 : out std_logic; - sample_f0_36 : out std_logic; - sample_f0_37 : out std_logic; - sample_f0_38 : out std_logic; - sample_f0_39 : out std_logic; - sample_f0_40 : out std_logic; - sample_f0_41 : out std_logic; - sample_f0_42 : out std_logic; - sample_f0_43 : out std_logic; - sample_f0_44 : out std_logic; - sample_f0_45 : out std_logic; - sample_f0_46 : out std_logic; - sample_f0_47 : out std_logic; - sample_f0_48 : out std_logic; - sample_f0_49 : out std_logic; - sample_f0_50 : out std_logic; - sample_f0_51 : out std_logic; - sample_f0_52 : out std_logic; - sample_f0_53 : out std_logic; - sample_f0_54 : out std_logic; - sample_f0_55 : out std_logic; - sample_f0_56 : out std_logic; - sample_f0_57 : out std_logic; - sample_f0_58 : out std_logic; - sample_f0_59 : out std_logic; - sample_f0_60 : out std_logic; - sample_f0_61 : out std_logic; - sample_f0_62 : out std_logic; - sample_f0_63 : out std_logic; - sample_data_shaping_out_0 : in std_logic := 'U'; - sample_data_shaping_out_1 : in std_logic := 'U'; - sample_data_shaping_out_2 : in std_logic := 'U'; - sample_data_shaping_out_3 : in std_logic := 'U'; - sample_data_shaping_out_4 : in std_logic := 'U'; - sample_data_shaping_out_5 : in std_logic := 'U'; - sample_data_shaping_out_6 : in std_logic := 'U'; - sample_data_shaping_out_7 : in std_logic := 'U'; - sample_data_shaping_out_8 : in std_logic := 'U'; - sample_data_shaping_out_9 : in std_logic := 'U'; - sample_data_shaping_out_10 : in std_logic := 'U'; - sample_data_shaping_out_11 : in std_logic := 'U'; - sample_data_shaping_out_12 : in std_logic := 'U'; - sample_data_shaping_out_13 : in std_logic := 'U'; - sample_data_shaping_out_14 : in std_logic := 'U'; - sample_data_shaping_out_15 : in std_logic := 'U'; - sample_data_shaping_out_18 : in std_logic := 'U'; - sample_data_shaping_out_19 : in std_logic := 'U'; - sample_data_shaping_out_20 : in std_logic := 'U'; - sample_data_shaping_out_21 : in std_logic := 'U'; - sample_data_shaping_out_22 : in std_logic := 'U'; - sample_data_shaping_out_23 : in std_logic := 'U'; - sample_data_shaping_out_24 : in std_logic := 'U'; - sample_data_shaping_out_25 : in std_logic := 'U'; - sample_data_shaping_out_26 : in std_logic := 'U'; - sample_data_shaping_out_27 : in std_logic := 'U'; - sample_data_shaping_out_28 : in std_logic := 'U'; - sample_data_shaping_out_29 : in std_logic := 'U'; - sample_data_shaping_out_30 : in std_logic := 'U'; - sample_data_shaping_out_31 : in std_logic := 'U'; - sample_data_shaping_out_32 : in std_logic := 'U'; - sample_data_shaping_out_33 : in std_logic := 'U'; - sample_data_shaping_out_36 : in std_logic := 'U'; - sample_data_shaping_out_37 : in std_logic := 'U'; - sample_data_shaping_out_38 : in std_logic := 'U'; - sample_data_shaping_out_39 : in std_logic := 'U'; - sample_data_shaping_out_40 : in std_logic := 'U'; - sample_data_shaping_out_41 : in std_logic := 'U'; - sample_data_shaping_out_42 : in std_logic := 'U'; - sample_data_shaping_out_43 : in std_logic := 'U'; - sample_data_shaping_out_44 : in std_logic := 'U'; - sample_data_shaping_out_45 : in std_logic := 'U'; - sample_data_shaping_out_46 : in std_logic := 'U'; - sample_data_shaping_out_47 : in std_logic := 'U'; - sample_data_shaping_out_48 : in std_logic := 'U'; - sample_data_shaping_out_49 : in std_logic := 'U'; - sample_data_shaping_out_50 : in std_logic := 'U'; - sample_data_shaping_out_51 : in std_logic := 'U'; - sample_data_shaping_out_54 : in std_logic := 'U'; - sample_data_shaping_out_55 : in std_logic := 'U'; - sample_data_shaping_out_56 : in std_logic := 'U'; - sample_data_shaping_out_57 : in std_logic := 'U'; - sample_data_shaping_out_58 : in std_logic := 'U'; - sample_data_shaping_out_59 : in std_logic := 'U'; - sample_data_shaping_out_60 : in std_logic := 'U'; - sample_data_shaping_out_61 : in std_logic := 'U'; - sample_data_shaping_out_62 : in std_logic := 'U'; - sample_data_shaping_out_63 : in std_logic := 'U'; - sample_data_shaping_out_64 : in std_logic := 'U'; - sample_data_shaping_out_65 : in std_logic := 'U'; - sample_data_shaping_out_66 : in std_logic := 'U'; - sample_data_shaping_out_67 : in std_logic := 'U'; - sample_data_shaping_out_68 : in std_logic := 'U'; - sample_data_shaping_out_69 : in std_logic := 'U'; - sample_data_shaping_out_90 : in std_logic := 'U'; - sample_data_shaping_out_91 : in std_logic := 'U'; - sample_data_shaping_out_92 : in std_logic := 'U'; - sample_data_shaping_out_93 : in std_logic := 'U'; - sample_data_shaping_out_94 : in std_logic := 'U'; - sample_data_shaping_out_95 : in std_logic := 'U'; - sample_data_shaping_out_96 : in std_logic := 'U'; - sample_data_shaping_out_97 : in std_logic := 'U'; - sample_data_shaping_out_98 : in std_logic := 'U'; - sample_data_shaping_out_99 : in std_logic := 'U'; - sample_data_shaping_out_100 : in std_logic := 'U'; - sample_data_shaping_out_101 : in std_logic := 'U'; - sample_data_shaping_out_102 : in std_logic := 'U'; - sample_data_shaping_out_103 : in std_logic := 'U'; - sample_data_shaping_out_104 : in std_logic := 'U'; - sample_data_shaping_out_105 : in std_logic := 'U'; - sample_data_shaping_out_108 : in std_logic := 'U'; - sample_data_shaping_out_109 : in std_logic := 'U'; - sample_data_shaping_out_110 : in std_logic := 'U'; - sample_data_shaping_out_111 : in std_logic := 'U'; - sample_data_shaping_out_112 : in std_logic := 'U'; - sample_data_shaping_out_113 : in std_logic := 'U'; - sample_data_shaping_out_114 : in std_logic := 'U'; - sample_data_shaping_out_115 : in std_logic := 'U'; - sample_data_shaping_out_116 : in std_logic := 'U'; - sample_data_shaping_out_117 : in std_logic := 'U'; - sample_data_shaping_out_118 : in std_logic := 'U'; - sample_data_shaping_out_119 : in std_logic := 'U'; - sample_data_shaping_out_120 : in std_logic := 'U'; - sample_data_shaping_out_121 : in std_logic := 'U'; - sample_data_shaping_out_122 : in std_logic := 'U'; - sample_data_shaping_out_123 : in std_logic := 'U'; - sample_data_shaping_out_126 : in std_logic := 'U'; - sample_data_shaping_out_127 : in std_logic := 'U'; - sample_data_shaping_out_128 : in std_logic := 'U'; - sample_data_shaping_out_129 : in std_logic := 'U'; - sample_data_shaping_out_130 : in std_logic := 'U'; - sample_data_shaping_out_131 : in std_logic := 'U'; - sample_data_shaping_out_132 : in std_logic := 'U'; - sample_data_shaping_out_133 : in std_logic := 'U'; - sample_data_shaping_out_134 : in std_logic := 'U'; - sample_data_shaping_out_135 : in std_logic := 'U'; - sample_data_shaping_out_136 : in std_logic := 'U'; - sample_data_shaping_out_137 : in std_logic := 'U'; - sample_data_shaping_out_138 : in std_logic := 'U'; - sample_data_shaping_out_139 : in std_logic := 'U'; - sample_data_shaping_out_140 : in std_logic := 'U'; - sample_data_shaping_out_141 : in std_logic := 'U'; - sample_f0_wdata_95 : out std_logic; - sample_f0_wdata_94 : out std_logic; - sample_f0_wdata_93 : out std_logic; - sample_f0_wdata_92 : out std_logic; - sample_f0_wdata_91 : out std_logic; - sample_f0_wdata_90 : out std_logic; - sample_f0_wdata_89 : out std_logic; - sample_f0_wdata_88 : out std_logic; - sample_f0_wdata_87 : out std_logic; - sample_f0_wdata_86 : out std_logic; - sample_f0_wdata_85 : out std_logic; - sample_f0_wdata_84 : out std_logic; - sample_f0_wdata_83 : out std_logic; - sample_f0_wdata_82 : out std_logic; - sample_f0_wdata_81 : out std_logic; - sample_f0_wdata_80 : out std_logic; - sample_f0_wdata_79 : out std_logic; - sample_f0_wdata_78 : out std_logic; - sample_f0_wdata_77 : out std_logic; - sample_f0_wdata_76 : out std_logic; - sample_f0_wdata_75 : out std_logic; - sample_f0_wdata_74 : out std_logic; - sample_f0_wdata_73 : out std_logic; - sample_f0_wdata_72 : out std_logic; - sample_f0_wdata_71 : out std_logic; - sample_f0_wdata_70 : out std_logic; - sample_f0_wdata_69 : out std_logic; - sample_f0_wdata_68 : out std_logic; - sample_f0_wdata_67 : out std_logic; - sample_f0_wdata_66 : out std_logic; - sample_f0_wdata_65 : out std_logic; - sample_f0_wdata_64 : out std_logic; - sample_f0_wdata_63 : out std_logic; - sample_f0_wdata_62 : out std_logic; - sample_f0_wdata_61 : out std_logic; - sample_f0_wdata_60 : out std_logic; - sample_f0_wdata_59 : out std_logic; - sample_f0_wdata_58 : out std_logic; - sample_f0_wdata_57 : out std_logic; - sample_f0_wdata_56 : out std_logic; - sample_f0_wdata_55 : out std_logic; - sample_f0_wdata_54 : out std_logic; - sample_f0_wdata_53 : out std_logic; - sample_f0_wdata_52 : out std_logic; - sample_f0_wdata_51 : out std_logic; - sample_f0_wdata_50 : out std_logic; - sample_f0_wdata_49 : out std_logic; - sample_f0_wdata_48 : out std_logic; - sample_f0_wdata_15 : out std_logic; - sample_f0_wdata_14 : out std_logic; - sample_f0_wdata_13 : out std_logic; - sample_f0_wdata_12 : out std_logic; - sample_f0_wdata_11 : out std_logic; - sample_f0_wdata_10 : out std_logic; - sample_f0_wdata_9 : out std_logic; - sample_f0_wdata_8 : out std_logic; - sample_f0_wdata_7 : out std_logic; - sample_f0_wdata_6 : out std_logic; - sample_f0_wdata_5 : out std_logic; - sample_f0_wdata_4 : out std_logic; - sample_f0_wdata_3 : out std_logic; - sample_f0_wdata_2 : out std_logic; - sample_f0_wdata_1 : out std_logic; - sample_f0_wdata_0 : out std_logic; - sample_data_shaping_out_val : in std_logic := 'U'; - sample_f0_val : out std_logic; - sample_data_shaping_out_val_0 : in std_logic := 'U'; - sample_f0_val_0 : out std_logic; - sample_f0_val_1 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_f0_val_2 : out std_logic - ); - end component; - - component Downsampling_8_16_6 - port( sample_f0_0 : in std_logic := 'U'; - sample_f0_1 : in std_logic := 'U'; - sample_f0_2 : in std_logic := 'U'; - sample_f0_3 : in std_logic := 'U'; - sample_f0_4 : in std_logic := 'U'; - sample_f0_5 : in std_logic := 'U'; - sample_f0_6 : in std_logic := 'U'; - sample_f0_7 : in std_logic := 'U'; - sample_f0_8 : in std_logic := 'U'; - sample_f0_9 : in std_logic := 'U'; - sample_f0_10 : in std_logic := 'U'; - sample_f0_11 : in std_logic := 'U'; - sample_f0_12 : in std_logic := 'U'; - sample_f0_13 : in std_logic := 'U'; - sample_f0_14 : in std_logic := 'U'; - sample_f0_15 : in std_logic := 'U'; - sample_f0_32 : in std_logic := 'U'; - sample_f0_33 : in std_logic := 'U'; - sample_f0_34 : in std_logic := 'U'; - sample_f0_35 : in std_logic := 'U'; - sample_f0_36 : in std_logic := 'U'; - sample_f0_37 : in std_logic := 'U'; - sample_f0_38 : in std_logic := 'U'; - sample_f0_39 : in std_logic := 'U'; - sample_f0_40 : in std_logic := 'U'; - sample_f0_41 : in std_logic := 'U'; - sample_f0_42 : in std_logic := 'U'; - sample_f0_43 : in std_logic := 'U'; - sample_f0_44 : in std_logic := 'U'; - sample_f0_45 : in std_logic := 'U'; - sample_f0_46 : in std_logic := 'U'; - sample_f0_47 : in std_logic := 'U'; - sample_f0_48 : in std_logic := 'U'; - sample_f0_49 : in std_logic := 'U'; - sample_f0_50 : in std_logic := 'U'; - sample_f0_51 : in std_logic := 'U'; - sample_f0_52 : in std_logic := 'U'; - sample_f0_53 : in std_logic := 'U'; - sample_f0_54 : in std_logic := 'U'; - sample_f0_55 : in std_logic := 'U'; - sample_f0_56 : in std_logic := 'U'; - sample_f0_57 : in std_logic := 'U'; - sample_f0_58 : in std_logic := 'U'; - sample_f0_59 : in std_logic := 'U'; - sample_f0_60 : in std_logic := 'U'; - sample_f0_61 : in std_logic := 'U'; - sample_f0_62 : in std_logic := 'U'; - sample_f0_63 : in std_logic := 'U'; - sample_f1_0 : out std_logic; - sample_f1_1 : out std_logic; - sample_f1_2 : out std_logic; - sample_f1_3 : out std_logic; - sample_f1_4 : out std_logic; - sample_f1_5 : out std_logic; - sample_f1_6 : out std_logic; - sample_f1_7 : out std_logic; - sample_f1_8 : out std_logic; - sample_f1_9 : out std_logic; - sample_f1_10 : out std_logic; - sample_f1_11 : out std_logic; - sample_f1_12 : out std_logic; - sample_f1_13 : out std_logic; - sample_f1_14 : out std_logic; - sample_f1_15 : out std_logic; - sample_f1_32 : out std_logic; - sample_f1_33 : out std_logic; - sample_f1_34 : out std_logic; - sample_f1_35 : out std_logic; - sample_f1_36 : out std_logic; - sample_f1_37 : out std_logic; - sample_f1_38 : out std_logic; - sample_f1_39 : out std_logic; - sample_f1_40 : out std_logic; - sample_f1_41 : out std_logic; - sample_f1_42 : out std_logic; - sample_f1_43 : out std_logic; - sample_f1_44 : out std_logic; - sample_f1_45 : out std_logic; - sample_f1_46 : out std_logic; - sample_f1_47 : out std_logic; - sample_f1_48 : out std_logic; - sample_f1_49 : out std_logic; - sample_f1_50 : out std_logic; - sample_f1_51 : out std_logic; - sample_f1_52 : out std_logic; - sample_f1_53 : out std_logic; - sample_f1_54 : out std_logic; - sample_f1_55 : out std_logic; - sample_f1_56 : out std_logic; - sample_f1_57 : out std_logic; - sample_f1_58 : out std_logic; - sample_f1_59 : out std_logic; - sample_f1_60 : out std_logic; - sample_f1_61 : out std_logic; - sample_f1_62 : out std_logic; - sample_f1_63 : out std_logic; - sample_f0_wdata_95 : in std_logic := 'U'; - sample_f0_wdata_94 : in std_logic := 'U'; - sample_f0_wdata_93 : in std_logic := 'U'; - sample_f0_wdata_92 : in std_logic := 'U'; - sample_f0_wdata_91 : in std_logic := 'U'; - sample_f0_wdata_90 : in std_logic := 'U'; - sample_f0_wdata_89 : in std_logic := 'U'; - sample_f0_wdata_88 : in std_logic := 'U'; - sample_f0_wdata_87 : in std_logic := 'U'; - sample_f0_wdata_86 : in std_logic := 'U'; - sample_f0_wdata_85 : in std_logic := 'U'; - sample_f0_wdata_84 : in std_logic := 'U'; - sample_f0_wdata_83 : in std_logic := 'U'; - sample_f0_wdata_82 : in std_logic := 'U'; - sample_f0_wdata_81 : in std_logic := 'U'; - sample_f0_wdata_80 : in std_logic := 'U'; - sample_f0_wdata_79 : in std_logic := 'U'; - sample_f0_wdata_78 : in std_logic := 'U'; - sample_f0_wdata_77 : in std_logic := 'U'; - sample_f0_wdata_76 : in std_logic := 'U'; - sample_f0_wdata_75 : in std_logic := 'U'; - sample_f0_wdata_74 : in std_logic := 'U'; - sample_f0_wdata_73 : in std_logic := 'U'; - sample_f0_wdata_72 : in std_logic := 'U'; - sample_f0_wdata_71 : in std_logic := 'U'; - sample_f0_wdata_70 : in std_logic := 'U'; - sample_f0_wdata_69 : in std_logic := 'U'; - sample_f0_wdata_68 : in std_logic := 'U'; - sample_f0_wdata_67 : in std_logic := 'U'; - sample_f0_wdata_66 : in std_logic := 'U'; - sample_f0_wdata_65 : in std_logic := 'U'; - sample_f0_wdata_64 : in std_logic := 'U'; - sample_f0_wdata_63 : in std_logic := 'U'; - sample_f0_wdata_62 : in std_logic := 'U'; - sample_f0_wdata_61 : in std_logic := 'U'; - sample_f0_wdata_60 : in std_logic := 'U'; - sample_f0_wdata_59 : in std_logic := 'U'; - sample_f0_wdata_58 : in std_logic := 'U'; - sample_f0_wdata_57 : in std_logic := 'U'; - sample_f0_wdata_56 : in std_logic := 'U'; - sample_f0_wdata_55 : in std_logic := 'U'; - sample_f0_wdata_54 : in std_logic := 'U'; - sample_f0_wdata_53 : in std_logic := 'U'; - sample_f0_wdata_52 : in std_logic := 'U'; - sample_f0_wdata_51 : in std_logic := 'U'; - sample_f0_wdata_50 : in std_logic := 'U'; - sample_f0_wdata_49 : in std_logic := 'U'; - sample_f0_wdata_48 : in std_logic := 'U'; - sample_f0_wdata_15 : in std_logic := 'U'; - sample_f0_wdata_14 : in std_logic := 'U'; - sample_f0_wdata_13 : in std_logic := 'U'; - sample_f0_wdata_12 : in std_logic := 'U'; - sample_f0_wdata_11 : in std_logic := 'U'; - sample_f0_wdata_10 : in std_logic := 'U'; - sample_f0_wdata_9 : in std_logic := 'U'; - sample_f0_wdata_8 : in std_logic := 'U'; - sample_f0_wdata_7 : in std_logic := 'U'; - sample_f0_wdata_6 : in std_logic := 'U'; - sample_f0_wdata_5 : in std_logic := 'U'; - sample_f0_wdata_4 : in std_logic := 'U'; - sample_f0_wdata_3 : in std_logic := 'U'; - sample_f0_wdata_2 : in std_logic := 'U'; - sample_f0_wdata_1 : in std_logic := 'U'; - sample_f0_wdata_0 : in std_logic := 'U'; - sample_f1_wdata_95 : out std_logic; - sample_f1_wdata_94 : out std_logic; - sample_f1_wdata_93 : out std_logic; - sample_f1_wdata_92 : out std_logic; - sample_f1_wdata_91 : out std_logic; - sample_f1_wdata_90 : out std_logic; - sample_f1_wdata_89 : out std_logic; - sample_f1_wdata_88 : out std_logic; - sample_f1_wdata_87 : out std_logic; - sample_f1_wdata_86 : out std_logic; - sample_f1_wdata_85 : out std_logic; - sample_f1_wdata_84 : out std_logic; - sample_f1_wdata_83 : out std_logic; - sample_f1_wdata_82 : out std_logic; - sample_f1_wdata_81 : out std_logic; - sample_f1_wdata_80 : out std_logic; - sample_f1_wdata_79 : out std_logic; - sample_f1_wdata_78 : out std_logic; - sample_f1_wdata_77 : out std_logic; - sample_f1_wdata_76 : out std_logic; - sample_f1_wdata_75 : out std_logic; - sample_f1_wdata_74 : out std_logic; - sample_f1_wdata_73 : out std_logic; - sample_f1_wdata_72 : out std_logic; - sample_f1_wdata_71 : out std_logic; - sample_f1_wdata_70 : out std_logic; - sample_f1_wdata_69 : out std_logic; - sample_f1_wdata_68 : out std_logic; - sample_f1_wdata_67 : out std_logic; - sample_f1_wdata_66 : out std_logic; - sample_f1_wdata_65 : out std_logic; - sample_f1_wdata_64 : out std_logic; - sample_f1_wdata_63 : out std_logic; - sample_f1_wdata_62 : out std_logic; - sample_f1_wdata_61 : out std_logic; - sample_f1_wdata_60 : out std_logic; - sample_f1_wdata_59 : out std_logic; - sample_f1_wdata_58 : out std_logic; - sample_f1_wdata_57 : out std_logic; - sample_f1_wdata_56 : out std_logic; - sample_f1_wdata_55 : out std_logic; - sample_f1_wdata_54 : out std_logic; - sample_f1_wdata_53 : out std_logic; - sample_f1_wdata_52 : out std_logic; - sample_f1_wdata_51 : out std_logic; - sample_f1_wdata_50 : out std_logic; - sample_f1_wdata_49 : out std_logic; - sample_f1_wdata_48 : out std_logic; - sample_f1_wdata_15 : out std_logic; - sample_f1_wdata_14 : out std_logic; - sample_f1_wdata_13 : out std_logic; - sample_f1_wdata_12 : out std_logic; - sample_f1_wdata_11 : out std_logic; - sample_f1_wdata_10 : out std_logic; - sample_f1_wdata_9 : out std_logic; - sample_f1_wdata_8 : out std_logic; - sample_f1_wdata_7 : out std_logic; - sample_f1_wdata_6 : out std_logic; - sample_f1_wdata_5 : out std_logic; - sample_f1_wdata_4 : out std_logic; - sample_f1_wdata_3 : out std_logic; - sample_f1_wdata_2 : out std_logic; - sample_f1_wdata_1 : out std_logic; - sample_f1_wdata_0 : out std_logic; - sample_f0_val_2 : in std_logic := 'U'; - sample_f0_val_1 : in std_logic := 'U'; - sample_f1_val : out std_logic; - sample_f0_val_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - sample_f1_val_0 : out std_logic - ); - end component; - - component AD7688_drvr - port( sample_4 : out std_logic_vector(15 downto 0); - sample_5 : out std_logic_vector(15 downto 0); - sample_6 : out std_logic_vector(15 downto 0); - sample_7 : out std_logic_vector(15 downto 0); - sample_0 : out std_logic_vector(15 downto 0); - sample_1 : out std_logic_vector(15 downto 0); - sample_2 : out std_logic_vector(15 downto 0); - sdo_adc_c : in std_logic_vector(7 downto 0) := (others => 'U'); - sample_3 : out std_logic_vector(15 downto 0); - AD7688_drvr_VCC : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - cnv_ch1_c : out std_logic; - sample_val : out std_logic; - sck_ch1_c : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \sample_val_delay_5\, sample_val, - \sample_val_delay_4\, \sample_val_delay_3\, - \sample_val_delay_2\, \sample_val_delay_1\, - \sample_val_delay_0\, \sample_data_shaping_out_val_0\, - sample_filter_v2_out_val, SUB_16x16_medium_area_I57_Y_2, - N244, N229, SUB_16x16_medium_area_I57_Y_1, N254, N212, - SUB_16x16_medium_area_I57_Y_0, N206, - \sample_filter_v2_out[111]\, \sample_filter_v2_out[93]\, - SUB_16x16_medium_area_I57_Y_2_0, N244_0, N229_0, - SUB_16x16_medium_area_I57_Y_1_0, N212_0, N254_0, - SUB_16x16_medium_area_I57_Y_0_0, N206_0, - \sample_filter_v2_out[129]\, - SUB_16x16_medium_area_I57_un1_Y_0, N245, - SUB_16x16_medium_area_I57_un1_Y_0_0, N245_0, - SUB_16x16_medium_area_I56_Y_1, N274, N220, - SUB_16x16_medium_area_I56_Y_0, N190, - \sample_filter_v2_out[119]\, \sample_filter_v2_out[101]\, - SUB_16x16_medium_area_I56_Y_1_0, N274_0, N220_0, - SUB_16x16_medium_area_I56_Y_0_0, N190_0, - \sample_filter_v2_out[137]\, - SUB_16x16_medium_area_I56_un1_Y_0, N275, - SUB_16x16_medium_area_I56_un1_Y_0_0, N275_0, - SUB_16x16_medium_area_I49_Y_0, N198, - \sample_filter_v2_out[115]\, \sample_filter_v2_out[97]\, - SUB_16x16_medium_area_I49_Y_0_0, N198_0, - \sample_filter_v2_out[133]\, - SUB_16x16_medium_area_I53_Y_0, N182, - \sample_filter_v2_out[141]\, \sample_filter_v2_out[123]\, - SUB_16x16_medium_area_I53_Y_0_0, N182_0, - \sample_filter_v2_out[105]\, N264, N216, N240, N268, N278, - N264_0, N216_0, N240_0, N268_0, N278_0, - \sample_data_shaping_f2_f1_s[15]\, - \sample_filter_v2_out[110]\, \sample_filter_v2_out[92]\, - \sample_data_shaping_f1_f0_s[15]\, - \sample_filter_v2_out[128]\, I53_un1_Y, N225, N183, N181, - I53_un1_Y_0, N225_0, N183_0, N181_0, N194, - \sample_filter_v2_out[118]\, \sample_filter_v2_out[136]\, - \sample_filter_v2_out[116]\, \sample_filter_v2_out[134]\, - N202, \sample_filter_v2_out[114]\, - \sample_filter_v2_out[132]\, \sample_filter_v2_out[112]\, - \sample_filter_v2_out[130]\, N205, - \sample_filter_v2_out[131]\, \sample_filter_v2_out[113]\, - N255, N201, N197, \sample_filter_v2_out[117]\, - \sample_filter_v2_out[135]\, N265, N195, N258, N260, N270, - N282_i, N284_i, N286_i, SUB_16x16_medium_area_I89_un1_Y, - \sample_data_shaping_f1_f0_s[7]\, - \sample_data_shaping_f1_f0_s[8]\, - \sample_data_shaping_f1_f0_s[9]\, - \sample_data_shaping_f1_f0_s[10]\, - \sample_data_shaping_f1_f0_s[11]\, - \sample_data_shaping_f1_f0_s[12]\, - \sample_data_shaping_f1_f0_s[13]\, - \sample_data_shaping_f1_f0_s_i[14]\, N186, - \sample_filter_v2_out[122]\, \sample_filter_v2_out[140]\, - \sample_filter_v2_out[120]\, \sample_filter_v2_out[138]\, - N191, N189, \sample_filter_v2_out[121]\, - \sample_filter_v2_out[139]\, N187, N185, I85_un1_Y, - I90_un1_Y, SUB_16x16_medium_area_I91_un1_Y, - \sample_data_shaping_f1_f0_s[3]\, - \sample_data_shaping_f1_f0_s[4]\, - \sample_data_shaping_f1_f0_s[5]\, - \sample_data_shaping_f1_f0_s[6]\, N194_0, - \sample_filter_v2_out[100]\, \sample_filter_v2_out[98]\, - N202_0, \sample_filter_v2_out[96]\, - \sample_filter_v2_out[94]\, N205_0, - \sample_filter_v2_out[95]\, N255_0, N201_0, N197_0, - \sample_filter_v2_out[99]\, N265_0, N195_0, N258_0, - N260_0, N270_0, N282_i_0, N284_i_0, N286_i_0, - SUB_16x16_medium_area_I89_un1_Y_0, - \sample_data_shaping_f2_f1_s[7]\, - \sample_data_shaping_f2_f1_s[8]\, - \sample_data_shaping_f2_f1_s[9]\, - \sample_data_shaping_f2_f1_s[10]\, - \sample_data_shaping_f2_f1_s[11]\, - \sample_data_shaping_f2_f1_s[12]\, - \sample_data_shaping_f2_f1_s[13]\, - \sample_data_shaping_f2_f1_s[14]\, N186_0, - \sample_filter_v2_out[104]\, \sample_filter_v2_out[102]\, - N191_0, N189_0, \sample_filter_v2_out[103]\, N187_0, - N185_0, I85_un1_Y_0, I90_un1_Y_0, - SUB_16x16_medium_area_I91_un1_Y_0, - \sample_data_shaping_f2_f1_s[3]\, - \sample_data_shaping_f2_f1_s[4]\, - \sample_data_shaping_f2_f1_s[5]\, - \sample_data_shaping_f2_f1_s[6]\, - \sample_data_shaping_out_377[92]\, - \sample_data_shaping_out_353[93]\, - \sample_data_shaping_out_329[94]\, - \sample_data_shaping_out_305[95]\, - \sample_data_shaping_out_281[96]\, - \sample_data_shaping_out_257[97]\, - \sample_data_shaping_out_233[98]\, - \sample_data_shaping_out_209[99]\, - \sample_data_shaping_out_185[100]\, - \sample_data_shaping_out_161[101]\, - \sample_data_shaping_out_137[102]\, - \sample_data_shaping_out_113[103]\, - \sample_data_shaping_out_89[104]\, - \sample_data_shaping_out_373[110]\, - \sample_data_shaping_out_349[111]\, - \sample_data_shaping_out_325[112]\, - \sample_data_shaping_out_301[113]\, - \sample_data_shaping_out_277[114]\, - \sample_data_shaping_out_253[115]\, - \sample_data_shaping_out_229[116]\, - \sample_data_shaping_out_205[117]\, - \sample_data_shaping_out_181[118]\, - \sample_data_shaping_out_157[119]\, - \sample_data_shaping_out_133[120]\, - \sample_data_shaping_out_109[121]\, - \sample_data_shaping_out_85[122]\, - \sample_filter_v2_out[143]\, \sample_filter_v2_out[125]\, - \sample_filter_v2_out[107]\, - \sample_data_shaping_out_17[107]\, - \sample_data_shaping_out_13[125]\, - \sample_data_shaping_out_37[124]\, - \sample_filter_v2_out[124]\, - \sample_data_shaping_f1_f0_s[1]\, - \sample_data_shaping_out_61[123]\, - \sample_data_shaping_f1_f0_s[2]\, - \sample_data_shaping_out_41[106]\, - \sample_filter_v2_out[106]\, - \sample_data_shaping_f2_f1_s[1]\, - \sample_data_shaping_out_65[105]\, - \sample_data_shaping_f2_f1_s[2]\, N294_i, I92_un1_Y, - \sample_filter_v2_out[142]\, \sample_val_delay\, - \sample_data_shaping_out_val\, - \sample_data_shaping_out[20]\, \sample_filter_v2_out[20]\, - \sample_data_shaping_out[21]\, \sample_filter_v2_out[21]\, - \sample_data_shaping_out[22]\, \sample_filter_v2_out[22]\, - \sample_data_shaping_out[23]\, \sample_filter_v2_out[23]\, - \sample_data_shaping_out[24]\, \sample_filter_v2_out[24]\, - \sample_data_shaping_out[25]\, \sample_filter_v2_out[25]\, - \sample_data_shaping_out[26]\, \sample_filter_v2_out[26]\, - \sample_data_shaping_out[27]\, \sample_filter_v2_out[27]\, - \sample_data_shaping_out[28]\, \sample_filter_v2_out[28]\, - \sample_data_shaping_out[29]\, \sample_filter_v2_out[29]\, - \sample_data_shaping_out[30]\, \sample_filter_v2_out[30]\, - \sample_data_shaping_out[31]\, \sample_filter_v2_out[31]\, - \sample_data_shaping_out[32]\, \sample_filter_v2_out[32]\, - \sample_data_shaping_out[33]\, \sample_filter_v2_out[33]\, - \sample_data_shaping_out[34]\, \sample_filter_v2_out[34]\, - \sample_data_shaping_out[35]\, \sample_filter_v2_out[35]\, - \sample_data_shaping_out[38]\, \sample_filter_v2_out[38]\, - \sample_data_shaping_out[39]\, \sample_filter_v2_out[39]\, - \sample_data_shaping_out[40]\, \sample_filter_v2_out[40]\, - \sample_data_shaping_out[41]\, \sample_filter_v2_out[41]\, - \sample_data_shaping_out[42]\, \sample_filter_v2_out[42]\, - \sample_data_shaping_out[43]\, \sample_filter_v2_out[43]\, - \sample_data_shaping_out[44]\, \sample_filter_v2_out[44]\, - \sample_data_shaping_out[45]\, \sample_filter_v2_out[45]\, - \sample_data_shaping_out[46]\, \sample_filter_v2_out[46]\, - \sample_data_shaping_out[47]\, \sample_filter_v2_out[47]\, - \sample_data_shaping_out[48]\, \sample_filter_v2_out[48]\, - \sample_data_shaping_out[49]\, \sample_filter_v2_out[49]\, - \sample_data_shaping_out[50]\, \sample_filter_v2_out[50]\, - \sample_data_shaping_out[51]\, \sample_filter_v2_out[51]\, - \sample_data_shaping_out[52]\, \sample_filter_v2_out[52]\, - \sample_data_shaping_out[53]\, \sample_filter_v2_out[53]\, - \sample_data_shaping_out[56]\, \sample_filter_v2_out[56]\, - \sample_data_shaping_out[57]\, \sample_filter_v2_out[57]\, - \sample_data_shaping_out[58]\, \sample_filter_v2_out[58]\, - \sample_data_shaping_out[59]\, \sample_filter_v2_out[59]\, - \sample_data_shaping_out[60]\, \sample_filter_v2_out[60]\, - \sample_data_shaping_out[61]\, \sample_filter_v2_out[61]\, - \sample_data_shaping_out[62]\, \sample_filter_v2_out[62]\, - \sample_data_shaping_out[63]\, \sample_filter_v2_out[63]\, - \sample_data_shaping_out[64]\, \sample_filter_v2_out[64]\, - \sample_data_shaping_out[65]\, \sample_filter_v2_out[65]\, - \sample_data_shaping_out[66]\, \sample_filter_v2_out[66]\, - \sample_data_shaping_out[67]\, \sample_filter_v2_out[67]\, - \sample_data_shaping_out[68]\, \sample_filter_v2_out[68]\, - \sample_data_shaping_out[69]\, \sample_filter_v2_out[69]\, - \sample_data_shaping_out[70]\, \sample_filter_v2_out[70]\, - \sample_data_shaping_out[71]\, \sample_filter_v2_out[71]\, - \sample_data_shaping_out[128]\, - \sample_data_shaping_out[129]\, - \sample_data_shaping_out[130]\, - \sample_data_shaping_out[131]\, - \sample_data_shaping_out[132]\, - \sample_data_shaping_out[133]\, - \sample_data_shaping_out[134]\, - \sample_data_shaping_out[135]\, - \sample_data_shaping_out[136]\, - \sample_data_shaping_out[137]\, - \sample_data_shaping_out[138]\, - \sample_data_shaping_out[139]\, - \sample_data_shaping_out[140]\, - \sample_data_shaping_out[141]\, - \sample_data_shaping_out[142]\, - \sample_data_shaping_out[143]\, - \sample_data_shaping_out[2]\, \sample_filter_v2_out[2]\, - \sample_data_shaping_out[3]\, \sample_filter_v2_out[3]\, - \sample_data_shaping_out[4]\, \sample_filter_v2_out[4]\, - \sample_data_shaping_out[5]\, \sample_filter_v2_out[5]\, - \sample_data_shaping_out[6]\, \sample_filter_v2_out[6]\, - \sample_data_shaping_out[7]\, \sample_filter_v2_out[7]\, - \sample_data_shaping_out[8]\, \sample_filter_v2_out[8]\, - \sample_data_shaping_out[9]\, \sample_filter_v2_out[9]\, - \sample_data_shaping_out[10]\, \sample_filter_v2_out[10]\, - \sample_data_shaping_out[11]\, \sample_filter_v2_out[11]\, - \sample_data_shaping_out[12]\, \sample_filter_v2_out[12]\, - \sample_data_shaping_out[13]\, \sample_filter_v2_out[13]\, - \sample_data_shaping_out[14]\, \sample_filter_v2_out[14]\, - \sample_data_shaping_out[15]\, \sample_filter_v2_out[15]\, - \sample_data_shaping_out[16]\, \sample_filter_v2_out[16]\, - \sample_data_shaping_out[17]\, \sample_filter_v2_out[17]\, - \sample_data_shaping_out[92]\, - \sample_data_shaping_out[93]\, - \sample_data_shaping_out[94]\, - \sample_data_shaping_out[95]\, - \sample_data_shaping_out[96]\, - \sample_data_shaping_out[97]\, - \sample_data_shaping_out[98]\, - \sample_data_shaping_out[99]\, - \sample_data_shaping_out[100]\, - \sample_data_shaping_out[101]\, - \sample_data_shaping_out[102]\, - \sample_data_shaping_out[103]\, - \sample_data_shaping_out[104]\, - \sample_data_shaping_out[105]\, - \sample_data_shaping_out[106]\, - \sample_data_shaping_out[107]\, - \sample_data_shaping_out[110]\, - \sample_data_shaping_out[111]\, - \sample_data_shaping_out[112]\, - \sample_data_shaping_out[113]\, - \sample_data_shaping_out[114]\, - \sample_data_shaping_out[115]\, - \sample_data_shaping_out[116]\, - \sample_data_shaping_out[117]\, - \sample_data_shaping_out[118]\, - \sample_data_shaping_out[119]\, - \sample_data_shaping_out[120]\, - \sample_data_shaping_out[121]\, - \sample_data_shaping_out[122]\, - \sample_data_shaping_out[123]\, - \sample_data_shaping_out[124]\, - \sample_data_shaping_out[125]\, \sample_4[0]\, - \sample_4[1]\, \sample_4[2]\, \sample_4[3]\, - \sample_4[4]\, \sample_4[5]\, \sample_4[6]\, - \sample_4[7]\, \sample_4[8]\, \sample_4[9]\, - \sample_4[10]\, \sample_4[11]\, \sample_4[12]\, - \sample_4[13]\, \sample_4[14]\, \sample_4[15]\, - \sample_5[0]\, \sample_5[1]\, \sample_5[2]\, - \sample_5[3]\, \sample_5[4]\, \sample_5[5]\, - \sample_5[6]\, \sample_5[7]\, \sample_5[8]\, - \sample_5[9]\, \sample_5[10]\, \sample_5[11]\, - \sample_5[12]\, \sample_5[13]\, \sample_5[14]\, - \sample_5[15]\, \sample_6[0]\, \sample_6[1]\, - \sample_6[2]\, \sample_6[3]\, \sample_6[4]\, - \sample_6[5]\, \sample_6[6]\, \sample_6[7]\, - \sample_6[8]\, \sample_6[9]\, \sample_6[10]\, - \sample_6[11]\, \sample_6[12]\, \sample_6[13]\, - \sample_6[14]\, \sample_6[15]\, \sample_7[0]\, - \sample_7[1]\, \sample_7[2]\, \sample_7[3]\, - \sample_7[4]\, \sample_7[5]\, \sample_7[6]\, - \sample_7[7]\, \sample_7[8]\, \sample_7[9]\, - \sample_7[10]\, \sample_7[11]\, \sample_7[12]\, - \sample_7[13]\, \sample_7[14]\, \sample_7[15]\, - \sample_0[0]\, \sample_0[1]\, \sample_0[2]\, - \sample_0[3]\, \sample_0[4]\, \sample_0[5]\, - \sample_0[6]\, \sample_0[7]\, \sample_0[8]\, - \sample_0[9]\, \sample_0[10]\, \sample_0[11]\, - \sample_0[12]\, \sample_0[13]\, \sample_0[14]\, - \sample_0[15]\, \sample_1[0]\, \sample_1[1]\, - \sample_1[2]\, \sample_1[3]\, \sample_1[4]\, - \sample_1[5]\, \sample_1[6]\, \sample_1[7]\, - \sample_1[8]\, \sample_1[9]\, \sample_1[10]\, - \sample_1[11]\, \sample_1[12]\, \sample_1[13]\, - \sample_1[14]\, \sample_1[15]\, \sample_2[0]\, - \sample_2[1]\, \sample_2[2]\, \sample_2[3]\, - \sample_2[4]\, \sample_2[5]\, \sample_2[6]\, - \sample_2[7]\, \sample_2[8]\, \sample_2[9]\, - \sample_2[10]\, \sample_2[11]\, \sample_2[12]\, - \sample_2[13]\, \sample_2[14]\, \sample_2[15]\, - \sample_3[0]\, \sample_3[1]\, \sample_3[2]\, - \sample_3[3]\, \sample_3[4]\, \sample_3[5]\, - \sample_3[6]\, \sample_3[7]\, \sample_3[8]\, - \sample_3[9]\, \sample_3[10]\, \sample_3[11]\, - \sample_3[12]\, \sample_3[13]\, \sample_3[14]\, - \sample_3[15]\, \sample_f0[48]\, \sample_f0[49]\, - \sample_f0[50]\, \sample_f0[51]\, \sample_f0[52]\, - \sample_f0[53]\, \sample_f0[54]\, \sample_f0[55]\, - \sample_f0[56]\, \sample_f0[57]\, \sample_f0[58]\, - \sample_f0[59]\, \sample_f0[60]\, \sample_f0[61]\, - \sample_f0[62]\, \sample_f0[63]\, \sample_f0[80]\, - \sample_f0[81]\, \sample_f0[82]\, \sample_f0[83]\, - \sample_f0[84]\, \sample_f0[85]\, \sample_f0[86]\, - \sample_f0[87]\, \sample_f0[88]\, \sample_f0[89]\, - \sample_f0[90]\, \sample_f0[91]\, \sample_f0[92]\, - \sample_f0[93]\, \sample_f0[94]\, \sample_f0[95]\, - \sample_f0[96]\, \sample_f0[97]\, \sample_f0[98]\, - \sample_f0[99]\, \sample_f0[100]\, \sample_f0[101]\, - \sample_f0[102]\, \sample_f0[103]\, \sample_f0[104]\, - \sample_f0[105]\, \sample_f0[106]\, \sample_f0[107]\, - \sample_f0[108]\, \sample_f0[109]\, \sample_f0[110]\, - \sample_f0[111]\, \sample_f0_wdata[95]\, - \sample_f0_wdata[94]\, \sample_f0_wdata[93]\, - \sample_f0_wdata[92]\, \sample_f0_wdata[91]\, - \sample_f0_wdata[90]\, \sample_f0_wdata[89]\, - \sample_f0_wdata[88]\, \sample_f0_wdata[87]\, - \sample_f0_wdata[86]\, \sample_f0_wdata[85]\, - \sample_f0_wdata[84]\, \sample_f0_wdata[83]\, - \sample_f0_wdata[82]\, \sample_f0_wdata[81]\, - \sample_f0_wdata[80]\, \sample_f0_wdata[79]\, - \sample_f0_wdata[78]\, \sample_f0_wdata[77]\, - \sample_f0_wdata[76]\, \sample_f0_wdata[75]\, - \sample_f0_wdata[74]\, \sample_f0_wdata[73]\, - \sample_f0_wdata[72]\, \sample_f0_wdata[71]\, - \sample_f0_wdata[70]\, \sample_f0_wdata[69]\, - \sample_f0_wdata[68]\, \sample_f0_wdata[67]\, - \sample_f0_wdata[66]\, \sample_f0_wdata[65]\, - \sample_f0_wdata[64]\, \sample_f0_wdata[63]\, - \sample_f0_wdata[62]\, \sample_f0_wdata[61]\, - \sample_f0_wdata[60]\, \sample_f0_wdata[59]\, - \sample_f0_wdata[58]\, \sample_f0_wdata[57]\, - \sample_f0_wdata[56]\, \sample_f0_wdata[55]\, - \sample_f0_wdata[54]\, \sample_f0_wdata[53]\, - \sample_f0_wdata[52]\, \sample_f0_wdata[51]\, - \sample_f0_wdata[50]\, \sample_f0_wdata[49]\, - \sample_f0_wdata[48]\, \sample_f0_wdata[15]\, - \sample_f0_wdata[14]\, \sample_f0_wdata[13]\, - \sample_f0_wdata[12]\, \sample_f0_wdata[11]\, - \sample_f0_wdata[10]\, \sample_f0_wdata[9]\, - \sample_f0_wdata[8]\, \sample_f0_wdata[7]\, - \sample_f0_wdata[6]\, \sample_f0_wdata[5]\, - \sample_f0_wdata[4]\, \sample_f0_wdata[3]\, - \sample_f0_wdata[2]\, \sample_f0_wdata[1]\, - \sample_f0_wdata[0]\, sample_f0_val, sample_f0_val_0, - sample_f0_val_1, sample_f0_val_2, \sample_f1[48]\, - \sample_f1[49]\, \sample_f1[50]\, \sample_f1[51]\, - \sample_f1[52]\, \sample_f1[53]\, \sample_f1[54]\, - \sample_f1[55]\, \sample_f1[56]\, \sample_f1[57]\, - \sample_f1[58]\, \sample_f1[59]\, \sample_f1[60]\, - \sample_f1[61]\, \sample_f1[62]\, \sample_f1[63]\, - \sample_f1[80]\, \sample_f1[81]\, \sample_f1[82]\, - \sample_f1[83]\, \sample_f1[84]\, \sample_f1[85]\, - \sample_f1[86]\, \sample_f1[87]\, \sample_f1[88]\, - \sample_f1[89]\, \sample_f1[90]\, \sample_f1[91]\, - \sample_f1[92]\, \sample_f1[93]\, \sample_f1[94]\, - \sample_f1[95]\, \sample_f1[96]\, \sample_f1[97]\, - \sample_f1[98]\, \sample_f1[99]\, \sample_f1[100]\, - \sample_f1[101]\, \sample_f1[102]\, \sample_f1[103]\, - \sample_f1[104]\, \sample_f1[105]\, \sample_f1[106]\, - \sample_f1[107]\, \sample_f1[108]\, \sample_f1[109]\, - \sample_f1[110]\, \sample_f1[111]\, \sample_f1_wdata[95]\, - \sample_f1_wdata[94]\, \sample_f1_wdata[93]\, - \sample_f1_wdata[92]\, \sample_f1_wdata[91]\, - \sample_f1_wdata[90]\, \sample_f1_wdata[89]\, - \sample_f1_wdata[88]\, \sample_f1_wdata[87]\, - \sample_f1_wdata[86]\, \sample_f1_wdata[85]\, - \sample_f1_wdata[84]\, \sample_f1_wdata[83]\, - \sample_f1_wdata[82]\, \sample_f1_wdata[81]\, - \sample_f1_wdata[80]\, \sample_f1_wdata[79]\, - \sample_f1_wdata[78]\, \sample_f1_wdata[77]\, - \sample_f1_wdata[76]\, \sample_f1_wdata[75]\, - \sample_f1_wdata[74]\, \sample_f1_wdata[73]\, - \sample_f1_wdata[72]\, \sample_f1_wdata[71]\, - \sample_f1_wdata[70]\, \sample_f1_wdata[69]\, - \sample_f1_wdata[68]\, \sample_f1_wdata[67]\, - \sample_f1_wdata[66]\, \sample_f1_wdata[65]\, - \sample_f1_wdata[64]\, \sample_f1_wdata[63]\, - \sample_f1_wdata[62]\, \sample_f1_wdata[61]\, - \sample_f1_wdata[60]\, \sample_f1_wdata[59]\, - \sample_f1_wdata[58]\, \sample_f1_wdata[57]\, - \sample_f1_wdata[56]\, \sample_f1_wdata[55]\, - \sample_f1_wdata[54]\, \sample_f1_wdata[53]\, - \sample_f1_wdata[52]\, \sample_f1_wdata[51]\, - \sample_f1_wdata[50]\, \sample_f1_wdata[49]\, - \sample_f1_wdata[48]\, \sample_f1_wdata[15]\, - \sample_f1_wdata[14]\, \sample_f1_wdata[13]\, - \sample_f1_wdata[12]\, \sample_f1_wdata[11]\, - \sample_f1_wdata[10]\, \sample_f1_wdata[9]\, - \sample_f1_wdata[8]\, \sample_f1_wdata[7]\, - \sample_f1_wdata[6]\, \sample_f1_wdata[5]\, - \sample_f1_wdata[4]\, \sample_f1_wdata[3]\, - \sample_f1_wdata[2]\, \sample_f1_wdata[1]\, - \sample_f1_wdata[0]\, sample_f1_val, sample_f1_val_0, - \sample_f2_wdata[0]\, \sample_f2_wdata[1]\, - \sample_f2_wdata[2]\, \sample_f2_wdata[3]\, - \sample_f2_wdata[4]\, \sample_f2_wdata[5]\, - \sample_f2_wdata[6]\, \sample_f2_wdata[7]\, - \sample_f2_wdata[8]\, \sample_f2_wdata[9]\, - \sample_f2_wdata[10]\, \sample_f2_wdata[11]\, - \sample_f2_wdata[12]\, \sample_f2_wdata[13]\, - \sample_f2_wdata[14]\, \sample_f2_wdata[15]\, - \sample_f2_wdata[16]\, \sample_f2_wdata[17]\, - \sample_f2_wdata[18]\, \sample_f2_wdata[19]\, - \sample_f2_wdata[20]\, \sample_f2_wdata[21]\, - \sample_f2_wdata[22]\, \sample_f2_wdata[23]\, - \sample_f2_wdata[24]\, \sample_f2_wdata[25]\, - \sample_f2_wdata[26]\, \sample_f2_wdata[27]\, - \sample_f2_wdata[28]\, \sample_f2_wdata[29]\, - \sample_f2_wdata[30]\, \sample_f2_wdata[31]\, - \sample_f2_wdata[32]\, \sample_f2_wdata[33]\, - \sample_f2_wdata[34]\, \sample_f2_wdata[35]\, - \sample_f2_wdata[36]\, \sample_f2_wdata[37]\, - \sample_f2_wdata[38]\, \sample_f2_wdata[39]\, - \sample_f2_wdata[40]\, \sample_f2_wdata[41]\, - \sample_f2_wdata[42]\, \sample_f2_wdata[43]\, - \sample_f2_wdata[44]\, \sample_f2_wdata[45]\, - \sample_f2_wdata[46]\, \sample_f2_wdata[47]\, - \sample_f2_wdata[48]\, \sample_f2_wdata[49]\, - \sample_f2_wdata[50]\, \sample_f2_wdata[51]\, - \sample_f2_wdata[52]\, \sample_f2_wdata[53]\, - \sample_f2_wdata[54]\, \sample_f2_wdata[55]\, - \sample_f2_wdata[56]\, \sample_f2_wdata[57]\, - \sample_f2_wdata[58]\, \sample_f2_wdata[59]\, - \sample_f2_wdata[60]\, \sample_f2_wdata[61]\, - \sample_f2_wdata[62]\, \sample_f2_wdata[63]\, - \sample_f2_wdata[64]\, \sample_f2_wdata[65]\, - \sample_f2_wdata[66]\, \sample_f2_wdata[67]\, - \sample_f2_wdata[68]\, \sample_f2_wdata[69]\, - \sample_f2_wdata[70]\, \sample_f2_wdata[71]\, - \sample_f2_wdata[72]\, \sample_f2_wdata[73]\, - \sample_f2_wdata[74]\, \sample_f2_wdata[75]\, - \sample_f2_wdata[76]\, \sample_f2_wdata[77]\, - \sample_f2_wdata[78]\, \sample_f2_wdata[79]\, - \sample_f2_wdata[80]\, \sample_f2_wdata[81]\, - \sample_f2_wdata[82]\, \sample_f2_wdata[83]\, - \sample_f2_wdata[84]\, \sample_f2_wdata[85]\, - \sample_f2_wdata[86]\, \sample_f2_wdata[87]\, - \sample_f2_wdata[88]\, \sample_f2_wdata[89]\, - \sample_f2_wdata[90]\, \sample_f2_wdata[91]\, - \sample_f2_wdata[92]\, \sample_f2_wdata[93]\, - \sample_f2_wdata[94]\, \sample_f2_wdata[95]\, - sample_f2_val, \sample_f3_wdata[0]\, \sample_f3_wdata[1]\, - \sample_f3_wdata[2]\, \sample_f3_wdata[3]\, - \sample_f3_wdata[4]\, \sample_f3_wdata[5]\, - \sample_f3_wdata[6]\, \sample_f3_wdata[7]\, - \sample_f3_wdata[8]\, \sample_f3_wdata[9]\, - \sample_f3_wdata[10]\, \sample_f3_wdata[11]\, - \sample_f3_wdata[12]\, \sample_f3_wdata[13]\, - \sample_f3_wdata[14]\, \sample_f3_wdata[15]\, - \sample_f3_wdata[16]\, \sample_f3_wdata[17]\, - \sample_f3_wdata[18]\, \sample_f3_wdata[19]\, - \sample_f3_wdata[20]\, \sample_f3_wdata[21]\, - \sample_f3_wdata[22]\, \sample_f3_wdata[23]\, - \sample_f3_wdata[24]\, \sample_f3_wdata[25]\, - \sample_f3_wdata[26]\, \sample_f3_wdata[27]\, - \sample_f3_wdata[28]\, \sample_f3_wdata[29]\, - \sample_f3_wdata[30]\, \sample_f3_wdata[31]\, - \sample_f3_wdata[32]\, \sample_f3_wdata[33]\, - \sample_f3_wdata[34]\, \sample_f3_wdata[35]\, - \sample_f3_wdata[36]\, \sample_f3_wdata[37]\, - \sample_f3_wdata[38]\, \sample_f3_wdata[39]\, - \sample_f3_wdata[40]\, \sample_f3_wdata[41]\, - \sample_f3_wdata[42]\, \sample_f3_wdata[43]\, - \sample_f3_wdata[44]\, \sample_f3_wdata[45]\, - \sample_f3_wdata[46]\, \sample_f3_wdata[47]\, - \sample_f3_wdata[48]\, \sample_f3_wdata[49]\, - \sample_f3_wdata[50]\, \sample_f3_wdata[51]\, - \sample_f3_wdata[52]\, \sample_f3_wdata[53]\, - \sample_f3_wdata[54]\, \sample_f3_wdata[55]\, - \sample_f3_wdata[56]\, \sample_f3_wdata[57]\, - \sample_f3_wdata[58]\, \sample_f3_wdata[59]\, - \sample_f3_wdata[60]\, \sample_f3_wdata[61]\, - \sample_f3_wdata[62]\, \sample_f3_wdata[63]\, - \sample_f3_wdata[64]\, \sample_f3_wdata[65]\, - \sample_f3_wdata[66]\, \sample_f3_wdata[67]\, - \sample_f3_wdata[68]\, \sample_f3_wdata[69]\, - \sample_f3_wdata[70]\, \sample_f3_wdata[71]\, - \sample_f3_wdata[72]\, \sample_f3_wdata[73]\, - \sample_f3_wdata[74]\, \sample_f3_wdata[75]\, - \sample_f3_wdata[76]\, \sample_f3_wdata[77]\, - \sample_f3_wdata[78]\, \sample_f3_wdata[79]\, - \sample_f3_wdata[80]\, \sample_f3_wdata[81]\, - \sample_f3_wdata[82]\, \sample_f3_wdata[83]\, - \sample_f3_wdata[84]\, \sample_f3_wdata[85]\, - \sample_f3_wdata[86]\, \sample_f3_wdata[87]\, - \sample_f3_wdata[88]\, \sample_f3_wdata[89]\, - \sample_f3_wdata[90]\, \sample_f3_wdata[91]\, - \sample_f3_wdata[92]\, \sample_f3_wdata[93]\, - \sample_f3_wdata[94]\, \sample_f3_wdata[95]\, - sample_f3_val, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : IIR_CEL_CTRLR_v2 - Use entity work.IIR_CEL_CTRLR_v2(DEF_ARCH); - for all : Downsampling_6_16_256 - Use entity work.Downsampling_6_16_256(DEF_ARCH); - for all : Downsampling_6_16_96 - Use entity work.Downsampling_6_16_96(DEF_ARCH); - for all : lpp_waveform - Use entity work.lpp_waveform(DEF_ARCH); - for all : Downsampling_8_16_4 - Use entity work.Downsampling_8_16_4(DEF_ARCH); - for all : Downsampling_8_16_6 - Use entity work.Downsampling_8_16_6(DEF_ARCH); - for all : AD7688_drvr - Use entity work.AD7688_drvr(DEF_ARCH); -begin - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I78_Y : - AO1 - port map(A => N268_0, B => N265_0, C => N264_0, Y => N270_0); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I91_un1_Y : - NOR2B - port map(A => N278_0, B => N185_0, Y => - SUB_16x16_medium_area_I91_un1_Y_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I27_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[96]\, B => - \sample_filter_v2_out[114]\, Y => N202_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[29]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[29]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[29]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[97]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_257[97]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[97]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out_RNO[120]\ : - MX2 - port map(A => \sample_filter_v2_out[120]\, B => - \sample_data_shaping_f1_f0_s[5]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_133[120]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[138]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[138]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[138]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I86_Y : - AO18 - port map(A => N260, B => \sample_filter_v2_out[130]\, C => - \sample_filter_v2_out[112]\, Y => N282_i); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[117]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_205[117]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[117]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[23]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[23]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[23]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out_RNO[103]\ : - MX2 - port map(A => \sample_filter_v2_out[103]\, B => - \sample_data_shaping_f2_f1_s[4]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_113[103]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I106_Y_0 : - XOR2 - port map(A => N260_0, B => N205_0, Y => - \sample_data_shaping_f2_f1_s[13]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I100_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, C => N268_0, Y => - \sample_data_shaping_f2_f1_s[7]\); - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - port map(sample_filter_v2_out_0 => - \sample_filter_v2_out[2]\, sample_filter_v2_out_1 => - \sample_filter_v2_out[3]\, sample_filter_v2_out_2 => - \sample_filter_v2_out[4]\, sample_filter_v2_out_3 => - \sample_filter_v2_out[5]\, sample_filter_v2_out_4 => - \sample_filter_v2_out[6]\, sample_filter_v2_out_5 => - \sample_filter_v2_out[7]\, sample_filter_v2_out_6 => - \sample_filter_v2_out[8]\, sample_filter_v2_out_7 => - \sample_filter_v2_out[9]\, sample_filter_v2_out_8 => - \sample_filter_v2_out[10]\, sample_filter_v2_out_9 => - \sample_filter_v2_out[11]\, sample_filter_v2_out_10 => - \sample_filter_v2_out[12]\, sample_filter_v2_out_11 => - \sample_filter_v2_out[13]\, sample_filter_v2_out_12 => - \sample_filter_v2_out[14]\, sample_filter_v2_out_13 => - \sample_filter_v2_out[15]\, sample_filter_v2_out_14 => - \sample_filter_v2_out[16]\, sample_filter_v2_out_15 => - \sample_filter_v2_out[17]\, sample_filter_v2_out_18 => - \sample_filter_v2_out[20]\, sample_filter_v2_out_19 => - \sample_filter_v2_out[21]\, sample_filter_v2_out_20 => - \sample_filter_v2_out[22]\, sample_filter_v2_out_21 => - \sample_filter_v2_out[23]\, sample_filter_v2_out_22 => - \sample_filter_v2_out[24]\, sample_filter_v2_out_23 => - \sample_filter_v2_out[25]\, sample_filter_v2_out_24 => - \sample_filter_v2_out[26]\, sample_filter_v2_out_25 => - \sample_filter_v2_out[27]\, sample_filter_v2_out_26 => - \sample_filter_v2_out[28]\, sample_filter_v2_out_27 => - \sample_filter_v2_out[29]\, sample_filter_v2_out_28 => - \sample_filter_v2_out[30]\, sample_filter_v2_out_29 => - \sample_filter_v2_out[31]\, sample_filter_v2_out_30 => - \sample_filter_v2_out[32]\, sample_filter_v2_out_31 => - \sample_filter_v2_out[33]\, sample_filter_v2_out_32 => - \sample_filter_v2_out[34]\, sample_filter_v2_out_33 => - \sample_filter_v2_out[35]\, sample_filter_v2_out_36 => - \sample_filter_v2_out[38]\, sample_filter_v2_out_37 => - \sample_filter_v2_out[39]\, sample_filter_v2_out_38 => - \sample_filter_v2_out[40]\, sample_filter_v2_out_39 => - \sample_filter_v2_out[41]\, sample_filter_v2_out_40 => - \sample_filter_v2_out[42]\, sample_filter_v2_out_41 => - \sample_filter_v2_out[43]\, sample_filter_v2_out_42 => - \sample_filter_v2_out[44]\, sample_filter_v2_out_43 => - \sample_filter_v2_out[45]\, sample_filter_v2_out_44 => - \sample_filter_v2_out[46]\, sample_filter_v2_out_45 => - \sample_filter_v2_out[47]\, sample_filter_v2_out_46 => - \sample_filter_v2_out[48]\, sample_filter_v2_out_47 => - \sample_filter_v2_out[49]\, sample_filter_v2_out_48 => - \sample_filter_v2_out[50]\, sample_filter_v2_out_49 => - \sample_filter_v2_out[51]\, sample_filter_v2_out_50 => - \sample_filter_v2_out[52]\, sample_filter_v2_out_51 => - \sample_filter_v2_out[53]\, sample_filter_v2_out_54 => - \sample_filter_v2_out[56]\, sample_filter_v2_out_55 => - \sample_filter_v2_out[57]\, sample_filter_v2_out_56 => - \sample_filter_v2_out[58]\, sample_filter_v2_out_57 => - \sample_filter_v2_out[59]\, sample_filter_v2_out_58 => - \sample_filter_v2_out[60]\, sample_filter_v2_out_59 => - \sample_filter_v2_out[61]\, sample_filter_v2_out_60 => - \sample_filter_v2_out[62]\, sample_filter_v2_out_61 => - \sample_filter_v2_out[63]\, sample_filter_v2_out_62 => - \sample_filter_v2_out[64]\, sample_filter_v2_out_63 => - \sample_filter_v2_out[65]\, sample_filter_v2_out_64 => - \sample_filter_v2_out[66]\, sample_filter_v2_out_65 => - \sample_filter_v2_out[67]\, sample_filter_v2_out_66 => - \sample_filter_v2_out[68]\, sample_filter_v2_out_67 => - \sample_filter_v2_out[69]\, sample_filter_v2_out_68 => - \sample_filter_v2_out[70]\, sample_filter_v2_out_69 => - \sample_filter_v2_out[71]\, sample_filter_v2_out_90 => - \sample_filter_v2_out[92]\, sample_filter_v2_out_91 => - \sample_filter_v2_out[93]\, sample_filter_v2_out_92 => - \sample_filter_v2_out[94]\, sample_filter_v2_out_93 => - \sample_filter_v2_out[95]\, sample_filter_v2_out_94 => - \sample_filter_v2_out[96]\, sample_filter_v2_out_95 => - \sample_filter_v2_out[97]\, sample_filter_v2_out_96 => - \sample_filter_v2_out[98]\, sample_filter_v2_out_97 => - \sample_filter_v2_out[99]\, sample_filter_v2_out_98 => - \sample_filter_v2_out[100]\, sample_filter_v2_out_99 => - \sample_filter_v2_out[101]\, sample_filter_v2_out_100 => - \sample_filter_v2_out[102]\, sample_filter_v2_out_101 => - \sample_filter_v2_out[103]\, sample_filter_v2_out_102 => - \sample_filter_v2_out[104]\, sample_filter_v2_out_103 => - \sample_filter_v2_out[105]\, sample_filter_v2_out_104 => - \sample_filter_v2_out[106]\, sample_filter_v2_out_105 => - \sample_filter_v2_out[107]\, sample_filter_v2_out_108 => - \sample_filter_v2_out[110]\, sample_filter_v2_out_126 => - \sample_filter_v2_out[128]\, sample_filter_v2_out_109 => - \sample_filter_v2_out[111]\, sample_filter_v2_out_127 => - \sample_filter_v2_out[129]\, sample_filter_v2_out_110 => - \sample_filter_v2_out[112]\, sample_filter_v2_out_128 => - \sample_filter_v2_out[130]\, sample_filter_v2_out_111 => - \sample_filter_v2_out[113]\, sample_filter_v2_out_129 => - \sample_filter_v2_out[131]\, sample_filter_v2_out_112 => - \sample_filter_v2_out[114]\, sample_filter_v2_out_130 => - \sample_filter_v2_out[132]\, sample_filter_v2_out_113 => - \sample_filter_v2_out[115]\, sample_filter_v2_out_131 => - \sample_filter_v2_out[133]\, sample_filter_v2_out_114 => - \sample_filter_v2_out[116]\, sample_filter_v2_out_132 => - \sample_filter_v2_out[134]\, sample_filter_v2_out_115 => - \sample_filter_v2_out[117]\, sample_filter_v2_out_133 => - \sample_filter_v2_out[135]\, sample_filter_v2_out_116 => - \sample_filter_v2_out[118]\, sample_filter_v2_out_134 => - \sample_filter_v2_out[136]\, sample_filter_v2_out_117 => - \sample_filter_v2_out[119]\, sample_filter_v2_out_135 => - \sample_filter_v2_out[137]\, sample_filter_v2_out_118 => - \sample_filter_v2_out[120]\, sample_filter_v2_out_136 => - \sample_filter_v2_out[138]\, sample_filter_v2_out_119 => - \sample_filter_v2_out[121]\, sample_filter_v2_out_137 => - \sample_filter_v2_out[139]\, sample_filter_v2_out_120 => - \sample_filter_v2_out[122]\, sample_filter_v2_out_138 => - \sample_filter_v2_out[140]\, sample_filter_v2_out_121 => - \sample_filter_v2_out[123]\, sample_filter_v2_out_139 => - \sample_filter_v2_out[141]\, sample_filter_v2_out_122 => - \sample_filter_v2_out[124]\, sample_filter_v2_out_140 => - \sample_filter_v2_out[142]\, sample_filter_v2_out_123 => - \sample_filter_v2_out[125]\, sample_filter_v2_out_141 => - \sample_filter_v2_out[143]\, sample_4(15) => - \sample_4[15]\, sample_4(14) => \sample_4[14]\, - sample_4(13) => \sample_4[13]\, sample_4(12) => - \sample_4[12]\, sample_4(11) => \sample_4[11]\, - sample_4(10) => \sample_4[10]\, sample_4(9) => - \sample_4[9]\, sample_4(8) => \sample_4[8]\, sample_4(7) - => \sample_4[7]\, sample_4(6) => \sample_4[6]\, - sample_4(5) => \sample_4[5]\, sample_4(4) => - \sample_4[4]\, sample_4(3) => \sample_4[3]\, sample_4(2) - => \sample_4[2]\, sample_4(1) => \sample_4[1]\, - sample_4(0) => \sample_4[0]\, sample_5(15) => - \sample_5[15]\, sample_5(14) => \sample_5[14]\, - sample_5(13) => \sample_5[13]\, sample_5(12) => - \sample_5[12]\, sample_5(11) => \sample_5[11]\, - sample_5(10) => \sample_5[10]\, sample_5(9) => - \sample_5[9]\, sample_5(8) => \sample_5[8]\, sample_5(7) - => \sample_5[7]\, sample_5(6) => \sample_5[6]\, - sample_5(5) => \sample_5[5]\, sample_5(4) => - \sample_5[4]\, sample_5(3) => \sample_5[3]\, sample_5(2) - => \sample_5[2]\, sample_5(1) => \sample_5[1]\, - sample_5(0) => \sample_5[0]\, sample_3(15) => - \sample_3[15]\, sample_3(14) => \sample_3[14]\, - sample_3(13) => \sample_3[13]\, sample_3(12) => - \sample_3[12]\, sample_3(11) => \sample_3[11]\, - sample_3(10) => \sample_3[10]\, sample_3(9) => - \sample_3[9]\, sample_3(8) => \sample_3[8]\, sample_3(7) - => \sample_3[7]\, sample_3(6) => \sample_3[6]\, - sample_3(5) => \sample_3[5]\, sample_3(4) => - \sample_3[4]\, sample_3(3) => \sample_3[3]\, sample_3(2) - => \sample_3[2]\, sample_3(1) => \sample_3[1]\, - sample_3(0) => \sample_3[0]\, sample_2(15) => - \sample_2[15]\, sample_2(14) => \sample_2[14]\, - sample_2(13) => \sample_2[13]\, sample_2(12) => - \sample_2[12]\, sample_2(11) => \sample_2[11]\, - sample_2(10) => \sample_2[10]\, sample_2(9) => - \sample_2[9]\, sample_2(8) => \sample_2[8]\, sample_2(7) - => \sample_2[7]\, sample_2(6) => \sample_2[6]\, - sample_2(5) => \sample_2[5]\, sample_2(4) => - \sample_2[4]\, sample_2(3) => \sample_2[3]\, sample_2(2) - => \sample_2[2]\, sample_2(1) => \sample_2[1]\, - sample_2(0) => \sample_2[0]\, sample_6(15) => - \sample_6[15]\, sample_6(14) => \sample_6[14]\, - sample_6(13) => \sample_6[13]\, sample_6(12) => - \sample_6[12]\, sample_6(11) => \sample_6[11]\, - sample_6(10) => \sample_6[10]\, sample_6(9) => - \sample_6[9]\, sample_6(8) => \sample_6[8]\, sample_6(7) - => \sample_6[7]\, sample_6(6) => \sample_6[6]\, - sample_6(5) => \sample_6[5]\, sample_6(4) => - \sample_6[4]\, sample_6(3) => \sample_6[3]\, sample_6(2) - => \sample_6[2]\, sample_6(1) => \sample_6[1]\, - sample_6(0) => \sample_6[0]\, sample_1(15) => - \sample_1[15]\, sample_1(14) => \sample_1[14]\, - sample_1(13) => \sample_1[13]\, sample_1(12) => - \sample_1[12]\, sample_1(11) => \sample_1[11]\, - sample_1(10) => \sample_1[10]\, sample_1(9) => - \sample_1[9]\, sample_1(8) => \sample_1[8]\, sample_1(7) - => \sample_1[7]\, sample_1(6) => \sample_1[6]\, - sample_1(5) => \sample_1[5]\, sample_1(4) => - \sample_1[4]\, sample_1(3) => \sample_1[3]\, sample_1(2) - => \sample_1[2]\, sample_1(1) => \sample_1[1]\, - sample_1(0) => \sample_1[0]\, sample_0(15) => - \sample_0[15]\, sample_0(14) => \sample_0[14]\, - sample_0(13) => \sample_0[13]\, sample_0(12) => - \sample_0[12]\, sample_0(11) => \sample_0[11]\, - sample_0(10) => \sample_0[10]\, sample_0(9) => - \sample_0[9]\, sample_0(8) => \sample_0[8]\, sample_0(7) - => \sample_0[7]\, sample_0(6) => \sample_0[6]\, - sample_0(5) => \sample_0[5]\, sample_0(4) => - \sample_0[4]\, sample_0(3) => \sample_0[3]\, sample_0(2) - => \sample_0[2]\, sample_0(1) => \sample_0[1]\, - sample_0(0) => \sample_0[0]\, sample_7(15) => - \sample_7[15]\, sample_7(14) => \sample_7[14]\, - sample_7(13) => \sample_7[13]\, sample_7(12) => - \sample_7[12]\, sample_7(11) => \sample_7[11]\, - sample_7(10) => \sample_7[10]\, sample_7(9) => - \sample_7[9]\, sample_7(8) => \sample_7[8]\, sample_7(7) - => \sample_7[7]\, sample_7(6) => \sample_7[6]\, - sample_7(5) => \sample_7[5]\, sample_7(4) => - \sample_7[4]\, sample_7(3) => \sample_7[3]\, sample_7(2) - => \sample_7[2]\, sample_7(1) => \sample_7[1]\, - sample_7(0) => \sample_7[0]\, IIR_CEL_CTRLR_v2_VCC => - lpp_top_lfr_wf_picker_ip_VCC, IIR_CEL_CTRLR_v2_GND => - lpp_top_lfr_wf_picker_ip_GND, rstn => rstn, lclk_c => - lclk_c, sample_filter_v2_out_val => - sample_filter_v2_out_val, sample_val_delay => - \sample_val_delay\, sample_val_delay_5 => - \sample_val_delay_5\, sample_val_delay_4 => - \sample_val_delay_4\, sample_val_delay_3 => - \sample_val_delay_3\, sample_val_delay_2 => - \sample_val_delay_2\, sample_val_delay_1 => - \sample_val_delay_1\, sample_val_delay_0 => - \sample_val_delay_0\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I101_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I89_un1_Y, B => N194, C - => N195, Y => \sample_data_shaping_f1_f0_s[8]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[103]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_113[103]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[103]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I22_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[137]\, B => - \sample_filter_v2_out[119]\, Y => N191); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[135]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[135]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[135]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I98_Y_0 : - AX1D - port map(A => I85_un1_Y, B => N274_0, C => N189, Y => - \sample_data_shaping_f1_f0_s[5]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I90_un1_Y : - OA1 - port map(A => I85_un1_Y_0, B => N274, C => N189_0, Y => - I90_un1_Y_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I24_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[135]\, B => - \sample_filter_v2_out[117]\, Y => N195); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[28]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[28]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[28]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out_RNO[110]\ : - MX2 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_data_shaping_f1_f0_s[15]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_373[110]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I108_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_filter_v2_out[128]\, C => N240, Y => - \sample_data_shaping_f1_f0_s[15]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I78_Y : - AO1 - port map(A => N268, B => N265, C => N264, Y => N270); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I71_Y : - AO1C - port map(A => N255, B => N258, C => N254_0, Y => N260); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I49_Y_0 : - AO18 - port map(A => N198_0, B => \sample_filter_v2_out[133]\, C - => \sample_filter_v2_out[115]\, Y => - SUB_16x16_medium_area_I49_Y_0_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I17_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[124]\, B => - \sample_filter_v2_out[106]\, Y => N181); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[30]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[30]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[30]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I33_Y : - XAI1A - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[129]\, C => N205, Y => N212_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I17_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[124]\, B => - \sample_filter_v2_out[142]\, Y => N182); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I104_Y_0 : - XOR2 - port map(A => N258, B => N201, Y => - \sample_data_shaping_f1_f0_s[11]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[119]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_157[119]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[119]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I49_Y_0 : - AO18 - port map(A => N198, B => \sample_filter_v2_out[115]\, C => - \sample_filter_v2_out[97]\, Y => - SUB_16x16_medium_area_I49_Y_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out_RNO[101]\ : - MX2 - port map(A => \sample_filter_v2_out[101]\, B => - \sample_data_shaping_f2_f1_s[6]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_161[101]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I29_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[94]\, B => - \sample_filter_v2_out[112]\, Y => N206); - - \SampleLoop_data_shaping.14.sample_data_shaping_out_RNO[93]\ : - MX2 - port map(A => \sample_filter_v2_out[93]\, B => - \sample_data_shaping_f2_f1_s[14]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_353[93]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[47]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[47]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[47]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I19_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[122]\, B => - \sample_filter_v2_out[104]\, Y => N185_0); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[120]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_133[120]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[120]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[13]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[13]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[13]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[32]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[32]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[32]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I21_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[102]\, B => - \sample_filter_v2_out[120]\, Y => N190); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[15]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[15]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[15]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out_RNO[95]\ : - MX2 - port map(A => \sample_filter_v2_out[95]\, B => - \sample_data_shaping_f2_f1_s[12]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_305[95]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[113]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_301[113]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[113]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y_1 : - AOI1B - port map(A => N274_0, B => N220_0, C => - SUB_16x16_medium_area_I56_Y_0_0, Y => - SUB_16x16_medium_area_I56_Y_1_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I20_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[121]\, B => - \sample_filter_v2_out[103]\, Y => N187_0); - - \SampleLoop_data_shaping.2.sample_data_shaping_out_RNO[123]\ : - MX2 - port map(A => \sample_filter_v2_out[123]\, B => - \sample_data_shaping_f1_f0_s[2]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_61[123]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[67]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[67]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[67]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I37_Y : - XA1A - port map(A => \sample_filter_v2_out[97]\, B => - \sample_filter_v2_out[115]\, C => N197_0, Y => N216_0); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[104]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_89[104]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[104]\); - - sample_val_delay : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[35]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[35]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[35]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I48_Y : - NOR2B - port map(A => N255_0, B => N212, Y => N229); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_un1_Y_0 : - NOR2B - port map(A => N229, B => N245, Y => - SUB_16x16_medium_area_I57_un1_Y_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[129]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[129]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[129]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I94_Y_0 : - XOR2 - port map(A => N225_0, B => N181_0, Y => - \sample_data_shaping_f1_f0_s[1]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[107]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_17[107]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[107]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I107_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[111]\, B => - \sample_filter_v2_out[129]\, C => N282_i, Y => - \sample_data_shaping_f1_f0_s_i[14]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I19_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[140]\, B => - \sample_filter_v2_out[122]\, Y => N185); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[137]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[137]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[137]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[11]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[11]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[11]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[46]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[46]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[46]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[110]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_373[110]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[110]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[61]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[61]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[61]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I102_Y_0 : - XOR2 - port map(A => N270, B => N197, Y => - \sample_data_shaping_f1_f0_s[9]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[68]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[68]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[68]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I42_Y : - AO13 - port map(A => N186_0, B => \sample_filter_v2_out[103]\, C - => \sample_filter_v2_out[121]\, Y => N274); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[57]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[57]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[57]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I107_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[93]\, B => - \sample_filter_v2_out[111]\, C => N282_i_0, Y => - \sample_data_shaping_f2_f1_s[14]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[49]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[49]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[49]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out_RNO[104]\ : - MX2 - port map(A => \sample_filter_v2_out[104]\, B => - \sample_data_shaping_f2_f1_s[3]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_89[104]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[17]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[17]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[17]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I92_Y : - AO18 - port map(A => N225, B => \sample_filter_v2_out[124]\, C => - \sample_filter_v2_out[106]\, Y => N294_i); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I105_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[131]\, C => N284_i, Y => - \sample_data_shaping_f1_f0_s[12]\); - - \SampleLoop_data_shaping.9.sample_data_shaping_out_RNO[116]\ : - MX2 - port map(A => \sample_filter_v2_out[116]\, B => - \sample_data_shaping_f1_f0_s[9]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_229[116]\); - - Downsampling_f3 : Downsampling_6_16_256 - port map(sample_f1(111) => \sample_f1[111]\, sample_f1(110) - => \sample_f1[110]\, sample_f1(109) => \sample_f1[109]\, - sample_f1(108) => \sample_f1[108]\, sample_f1(107) => - \sample_f1[107]\, sample_f1(106) => \sample_f1[106]\, - sample_f1(105) => \sample_f1[105]\, sample_f1(104) => - \sample_f1[104]\, sample_f1(103) => \sample_f1[103]\, - sample_f1(102) => \sample_f1[102]\, sample_f1(101) => - \sample_f1[101]\, sample_f1(100) => \sample_f1[100]\, - sample_f1(99) => \sample_f1[99]\, sample_f1(98) => - \sample_f1[98]\, sample_f1(97) => \sample_f1[97]\, - sample_f1(96) => \sample_f1[96]\, sample_f1(95) => - \sample_f1[95]\, sample_f1(94) => \sample_f1[94]\, - sample_f1(93) => \sample_f1[93]\, sample_f1(92) => - \sample_f1[92]\, sample_f1(91) => \sample_f1[91]\, - sample_f1(90) => \sample_f1[90]\, sample_f1(89) => - \sample_f1[89]\, sample_f1(88) => \sample_f1[88]\, - sample_f1(87) => \sample_f1[87]\, sample_f1(86) => - \sample_f1[86]\, sample_f1(85) => \sample_f1[85]\, - sample_f1(84) => \sample_f1[84]\, sample_f1(83) => - \sample_f1[83]\, sample_f1(82) => \sample_f1[82]\, - sample_f1(81) => \sample_f1[81]\, sample_f1(80) => - \sample_f1[80]\, sample_f1_wdata_95 => - \sample_f1_wdata[95]\, sample_f1_wdata_94 => - \sample_f1_wdata[94]\, sample_f1_wdata_93 => - \sample_f1_wdata[93]\, sample_f1_wdata_92 => - \sample_f1_wdata[92]\, sample_f1_wdata_91 => - \sample_f1_wdata[91]\, sample_f1_wdata_90 => - \sample_f1_wdata[90]\, sample_f1_wdata_89 => - \sample_f1_wdata[89]\, sample_f1_wdata_88 => - \sample_f1_wdata[88]\, sample_f1_wdata_87 => - \sample_f1_wdata[87]\, sample_f1_wdata_86 => - \sample_f1_wdata[86]\, sample_f1_wdata_85 => - \sample_f1_wdata[85]\, sample_f1_wdata_84 => - \sample_f1_wdata[84]\, sample_f1_wdata_83 => - \sample_f1_wdata[83]\, sample_f1_wdata_82 => - \sample_f1_wdata[82]\, sample_f1_wdata_81 => - \sample_f1_wdata[81]\, sample_f1_wdata_80 => - \sample_f1_wdata[80]\, sample_f1_wdata_79 => - \sample_f1_wdata[79]\, sample_f1_wdata_78 => - \sample_f1_wdata[78]\, sample_f1_wdata_77 => - \sample_f1_wdata[77]\, sample_f1_wdata_76 => - \sample_f1_wdata[76]\, sample_f1_wdata_75 => - \sample_f1_wdata[75]\, sample_f1_wdata_74 => - \sample_f1_wdata[74]\, sample_f1_wdata_73 => - \sample_f1_wdata[73]\, sample_f1_wdata_72 => - \sample_f1_wdata[72]\, sample_f1_wdata_71 => - \sample_f1_wdata[71]\, sample_f1_wdata_70 => - \sample_f1_wdata[70]\, sample_f1_wdata_69 => - \sample_f1_wdata[69]\, sample_f1_wdata_68 => - \sample_f1_wdata[68]\, sample_f1_wdata_67 => - \sample_f1_wdata[67]\, sample_f1_wdata_66 => - \sample_f1_wdata[66]\, sample_f1_wdata_65 => - \sample_f1_wdata[65]\, sample_f1_wdata_64 => - \sample_f1_wdata[64]\, sample_f1_wdata_63 => - \sample_f1_wdata[63]\, sample_f1_wdata_62 => - \sample_f1_wdata[62]\, sample_f1_wdata_61 => - \sample_f1_wdata[61]\, sample_f1_wdata_60 => - \sample_f1_wdata[60]\, sample_f1_wdata_59 => - \sample_f1_wdata[59]\, sample_f1_wdata_58 => - \sample_f1_wdata[58]\, sample_f1_wdata_57 => - \sample_f1_wdata[57]\, sample_f1_wdata_56 => - \sample_f1_wdata[56]\, sample_f1_wdata_55 => - \sample_f1_wdata[55]\, sample_f1_wdata_54 => - \sample_f1_wdata[54]\, sample_f1_wdata_53 => - \sample_f1_wdata[53]\, sample_f1_wdata_52 => - \sample_f1_wdata[52]\, sample_f1_wdata_51 => - \sample_f1_wdata[51]\, sample_f1_wdata_50 => - \sample_f1_wdata[50]\, sample_f1_wdata_49 => - \sample_f1_wdata[49]\, sample_f1_wdata_48 => - \sample_f1_wdata[48]\, sample_f1_wdata_15 => - \sample_f1_wdata[15]\, sample_f1_wdata_14 => - \sample_f1_wdata[14]\, sample_f1_wdata_13 => - \sample_f1_wdata[13]\, sample_f1_wdata_12 => - \sample_f1_wdata[12]\, sample_f1_wdata_11 => - \sample_f1_wdata[11]\, sample_f1_wdata_10 => - \sample_f1_wdata[10]\, sample_f1_wdata_9 => - \sample_f1_wdata[9]\, sample_f1_wdata_8 => - \sample_f1_wdata[8]\, sample_f1_wdata_7 => - \sample_f1_wdata[7]\, sample_f1_wdata_6 => - \sample_f1_wdata[6]\, sample_f1_wdata_5 => - \sample_f1_wdata[5]\, sample_f1_wdata_4 => - \sample_f1_wdata[4]\, sample_f1_wdata_3 => - \sample_f1_wdata[3]\, sample_f1_wdata_2 => - \sample_f1_wdata[2]\, sample_f1_wdata_1 => - \sample_f1_wdata[1]\, sample_f1_wdata_0 => - \sample_f1_wdata[0]\, sample_f3_wdata(95) => - \sample_f3_wdata[95]\, sample_f3_wdata(94) => - \sample_f3_wdata[94]\, sample_f3_wdata(93) => - \sample_f3_wdata[93]\, sample_f3_wdata(92) => - \sample_f3_wdata[92]\, sample_f3_wdata(91) => - \sample_f3_wdata[91]\, sample_f3_wdata(90) => - \sample_f3_wdata[90]\, sample_f3_wdata(89) => - \sample_f3_wdata[89]\, sample_f3_wdata(88) => - \sample_f3_wdata[88]\, sample_f3_wdata(87) => - \sample_f3_wdata[87]\, sample_f3_wdata(86) => - \sample_f3_wdata[86]\, sample_f3_wdata(85) => - \sample_f3_wdata[85]\, sample_f3_wdata(84) => - \sample_f3_wdata[84]\, sample_f3_wdata(83) => - \sample_f3_wdata[83]\, sample_f3_wdata(82) => - \sample_f3_wdata[82]\, sample_f3_wdata(81) => - \sample_f3_wdata[81]\, sample_f3_wdata(80) => - \sample_f3_wdata[80]\, sample_f3_wdata(79) => - \sample_f3_wdata[79]\, sample_f3_wdata(78) => - \sample_f3_wdata[78]\, sample_f3_wdata(77) => - \sample_f3_wdata[77]\, sample_f3_wdata(76) => - \sample_f3_wdata[76]\, sample_f3_wdata(75) => - \sample_f3_wdata[75]\, sample_f3_wdata(74) => - \sample_f3_wdata[74]\, sample_f3_wdata(73) => - \sample_f3_wdata[73]\, sample_f3_wdata(72) => - \sample_f3_wdata[72]\, sample_f3_wdata(71) => - \sample_f3_wdata[71]\, sample_f3_wdata(70) => - \sample_f3_wdata[70]\, sample_f3_wdata(69) => - \sample_f3_wdata[69]\, sample_f3_wdata(68) => - \sample_f3_wdata[68]\, sample_f3_wdata(67) => - \sample_f3_wdata[67]\, sample_f3_wdata(66) => - \sample_f3_wdata[66]\, sample_f3_wdata(65) => - \sample_f3_wdata[65]\, sample_f3_wdata(64) => - \sample_f3_wdata[64]\, sample_f3_wdata(63) => - \sample_f3_wdata[63]\, sample_f3_wdata(62) => - \sample_f3_wdata[62]\, sample_f3_wdata(61) => - \sample_f3_wdata[61]\, sample_f3_wdata(60) => - \sample_f3_wdata[60]\, sample_f3_wdata(59) => - \sample_f3_wdata[59]\, sample_f3_wdata(58) => - \sample_f3_wdata[58]\, sample_f3_wdata(57) => - \sample_f3_wdata[57]\, sample_f3_wdata(56) => - \sample_f3_wdata[56]\, sample_f3_wdata(55) => - \sample_f3_wdata[55]\, sample_f3_wdata(54) => - \sample_f3_wdata[54]\, sample_f3_wdata(53) => - \sample_f3_wdata[53]\, sample_f3_wdata(52) => - \sample_f3_wdata[52]\, sample_f3_wdata(51) => - \sample_f3_wdata[51]\, sample_f3_wdata(50) => - \sample_f3_wdata[50]\, sample_f3_wdata(49) => - \sample_f3_wdata[49]\, sample_f3_wdata(48) => - \sample_f3_wdata[48]\, sample_f3_wdata(47) => - \sample_f3_wdata[47]\, sample_f3_wdata(46) => - \sample_f3_wdata[46]\, sample_f3_wdata(45) => - \sample_f3_wdata[45]\, sample_f3_wdata(44) => - \sample_f3_wdata[44]\, sample_f3_wdata(43) => - \sample_f3_wdata[43]\, sample_f3_wdata(42) => - \sample_f3_wdata[42]\, sample_f3_wdata(41) => - \sample_f3_wdata[41]\, sample_f3_wdata(40) => - \sample_f3_wdata[40]\, sample_f3_wdata(39) => - \sample_f3_wdata[39]\, sample_f3_wdata(38) => - \sample_f3_wdata[38]\, sample_f3_wdata(37) => - \sample_f3_wdata[37]\, sample_f3_wdata(36) => - \sample_f3_wdata[36]\, sample_f3_wdata(35) => - \sample_f3_wdata[35]\, sample_f3_wdata(34) => - \sample_f3_wdata[34]\, sample_f3_wdata(33) => - \sample_f3_wdata[33]\, sample_f3_wdata(32) => - \sample_f3_wdata[32]\, sample_f3_wdata(31) => - \sample_f3_wdata[31]\, sample_f3_wdata(30) => - \sample_f3_wdata[30]\, sample_f3_wdata(29) => - \sample_f3_wdata[29]\, sample_f3_wdata(28) => - \sample_f3_wdata[28]\, sample_f3_wdata(27) => - \sample_f3_wdata[27]\, sample_f3_wdata(26) => - \sample_f3_wdata[26]\, sample_f3_wdata(25) => - \sample_f3_wdata[25]\, sample_f3_wdata(24) => - \sample_f3_wdata[24]\, sample_f3_wdata(23) => - \sample_f3_wdata[23]\, sample_f3_wdata(22) => - \sample_f3_wdata[22]\, sample_f3_wdata(21) => - \sample_f3_wdata[21]\, sample_f3_wdata(20) => - \sample_f3_wdata[20]\, sample_f3_wdata(19) => - \sample_f3_wdata[19]\, sample_f3_wdata(18) => - \sample_f3_wdata[18]\, sample_f3_wdata(17) => - \sample_f3_wdata[17]\, sample_f3_wdata(16) => - \sample_f3_wdata[16]\, sample_f3_wdata(15) => - \sample_f3_wdata[15]\, sample_f3_wdata(14) => - \sample_f3_wdata[14]\, sample_f3_wdata(13) => - \sample_f3_wdata[13]\, sample_f3_wdata(12) => - \sample_f3_wdata[12]\, sample_f3_wdata(11) => - \sample_f3_wdata[11]\, sample_f3_wdata(10) => - \sample_f3_wdata[10]\, sample_f3_wdata(9) => - \sample_f3_wdata[9]\, sample_f3_wdata(8) => - \sample_f3_wdata[8]\, sample_f3_wdata(7) => - \sample_f3_wdata[7]\, sample_f3_wdata(6) => - \sample_f3_wdata[6]\, sample_f3_wdata(5) => - \sample_f3_wdata[5]\, sample_f3_wdata(4) => - \sample_f3_wdata[4]\, sample_f3_wdata(3) => - \sample_f3_wdata[3]\, sample_f3_wdata(2) => - \sample_f3_wdata[2]\, sample_f3_wdata(1) => - \sample_f3_wdata[1]\, sample_f3_wdata(0) => - \sample_f3_wdata[0]\, sample_f1_val => sample_f1_val, - lclk_c => lclk_c, sample_f3_val => sample_f3_val, - sample_f1_val_0 => sample_f1_val_0, rstn => rstn); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I34_Y : - AO18 - port map(A => N202, B => \sample_filter_v2_out[131]\, C => - \sample_filter_v2_out[113]\, Y => N254_0); - - \SampleLoop_data_shaping.10.sample_data_shaping_out_RNO[115]\ : - MX2 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_data_shaping_f1_f0_s[10]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_253[115]\); - - GND_i : GND - port map(Y => \GND\); - - Downsampling_f2 : Downsampling_6_16_96 - port map(sample_f0(111) => \sample_f0[111]\, sample_f0(110) - => \sample_f0[110]\, sample_f0(109) => \sample_f0[109]\, - sample_f0(108) => \sample_f0[108]\, sample_f0(107) => - \sample_f0[107]\, sample_f0(106) => \sample_f0[106]\, - sample_f0(105) => \sample_f0[105]\, sample_f0(104) => - \sample_f0[104]\, sample_f0(103) => \sample_f0[103]\, - sample_f0(102) => \sample_f0[102]\, sample_f0(101) => - \sample_f0[101]\, sample_f0(100) => \sample_f0[100]\, - sample_f0(99) => \sample_f0[99]\, sample_f0(98) => - \sample_f0[98]\, sample_f0(97) => \sample_f0[97]\, - sample_f0(96) => \sample_f0[96]\, sample_f0(95) => - \sample_f0[95]\, sample_f0(94) => \sample_f0[94]\, - sample_f0(93) => \sample_f0[93]\, sample_f0(92) => - \sample_f0[92]\, sample_f0(91) => \sample_f0[91]\, - sample_f0(90) => \sample_f0[90]\, sample_f0(89) => - \sample_f0[89]\, sample_f0(88) => \sample_f0[88]\, - sample_f0(87) => \sample_f0[87]\, sample_f0(86) => - \sample_f0[86]\, sample_f0(85) => \sample_f0[85]\, - sample_f0(84) => \sample_f0[84]\, sample_f0(83) => - \sample_f0[83]\, sample_f0(82) => \sample_f0[82]\, - sample_f0(81) => \sample_f0[81]\, sample_f0(80) => - \sample_f0[80]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_f2_wdata(95) => - \sample_f2_wdata[95]\, sample_f2_wdata(94) => - \sample_f2_wdata[94]\, sample_f2_wdata(93) => - \sample_f2_wdata[93]\, sample_f2_wdata(92) => - \sample_f2_wdata[92]\, sample_f2_wdata(91) => - \sample_f2_wdata[91]\, sample_f2_wdata(90) => - \sample_f2_wdata[90]\, sample_f2_wdata(89) => - \sample_f2_wdata[89]\, sample_f2_wdata(88) => - \sample_f2_wdata[88]\, sample_f2_wdata(87) => - \sample_f2_wdata[87]\, sample_f2_wdata(86) => - \sample_f2_wdata[86]\, sample_f2_wdata(85) => - \sample_f2_wdata[85]\, sample_f2_wdata(84) => - \sample_f2_wdata[84]\, sample_f2_wdata(83) => - \sample_f2_wdata[83]\, sample_f2_wdata(82) => - \sample_f2_wdata[82]\, sample_f2_wdata(81) => - \sample_f2_wdata[81]\, sample_f2_wdata(80) => - \sample_f2_wdata[80]\, sample_f2_wdata(79) => - \sample_f2_wdata[79]\, sample_f2_wdata(78) => - \sample_f2_wdata[78]\, sample_f2_wdata(77) => - \sample_f2_wdata[77]\, sample_f2_wdata(76) => - \sample_f2_wdata[76]\, sample_f2_wdata(75) => - \sample_f2_wdata[75]\, sample_f2_wdata(74) => - \sample_f2_wdata[74]\, sample_f2_wdata(73) => - \sample_f2_wdata[73]\, sample_f2_wdata(72) => - \sample_f2_wdata[72]\, sample_f2_wdata(71) => - \sample_f2_wdata[71]\, sample_f2_wdata(70) => - \sample_f2_wdata[70]\, sample_f2_wdata(69) => - \sample_f2_wdata[69]\, sample_f2_wdata(68) => - \sample_f2_wdata[68]\, sample_f2_wdata(67) => - \sample_f2_wdata[67]\, sample_f2_wdata(66) => - \sample_f2_wdata[66]\, sample_f2_wdata(65) => - \sample_f2_wdata[65]\, sample_f2_wdata(64) => - \sample_f2_wdata[64]\, sample_f2_wdata(63) => - \sample_f2_wdata[63]\, sample_f2_wdata(62) => - \sample_f2_wdata[62]\, sample_f2_wdata(61) => - \sample_f2_wdata[61]\, sample_f2_wdata(60) => - \sample_f2_wdata[60]\, sample_f2_wdata(59) => - \sample_f2_wdata[59]\, sample_f2_wdata(58) => - \sample_f2_wdata[58]\, sample_f2_wdata(57) => - \sample_f2_wdata[57]\, sample_f2_wdata(56) => - \sample_f2_wdata[56]\, sample_f2_wdata(55) => - \sample_f2_wdata[55]\, sample_f2_wdata(54) => - \sample_f2_wdata[54]\, sample_f2_wdata(53) => - \sample_f2_wdata[53]\, sample_f2_wdata(52) => - \sample_f2_wdata[52]\, sample_f2_wdata(51) => - \sample_f2_wdata[51]\, sample_f2_wdata(50) => - \sample_f2_wdata[50]\, sample_f2_wdata(49) => - \sample_f2_wdata[49]\, sample_f2_wdata(48) => - \sample_f2_wdata[48]\, sample_f2_wdata(47) => - \sample_f2_wdata[47]\, sample_f2_wdata(46) => - \sample_f2_wdata[46]\, sample_f2_wdata(45) => - \sample_f2_wdata[45]\, sample_f2_wdata(44) => - \sample_f2_wdata[44]\, sample_f2_wdata(43) => - \sample_f2_wdata[43]\, sample_f2_wdata(42) => - \sample_f2_wdata[42]\, sample_f2_wdata(41) => - \sample_f2_wdata[41]\, sample_f2_wdata(40) => - \sample_f2_wdata[40]\, sample_f2_wdata(39) => - \sample_f2_wdata[39]\, sample_f2_wdata(38) => - \sample_f2_wdata[38]\, sample_f2_wdata(37) => - \sample_f2_wdata[37]\, sample_f2_wdata(36) => - \sample_f2_wdata[36]\, sample_f2_wdata(35) => - \sample_f2_wdata[35]\, sample_f2_wdata(34) => - \sample_f2_wdata[34]\, sample_f2_wdata(33) => - \sample_f2_wdata[33]\, sample_f2_wdata(32) => - \sample_f2_wdata[32]\, sample_f2_wdata(31) => - \sample_f2_wdata[31]\, sample_f2_wdata(30) => - \sample_f2_wdata[30]\, sample_f2_wdata(29) => - \sample_f2_wdata[29]\, sample_f2_wdata(28) => - \sample_f2_wdata[28]\, sample_f2_wdata(27) => - \sample_f2_wdata[27]\, sample_f2_wdata(26) => - \sample_f2_wdata[26]\, sample_f2_wdata(25) => - \sample_f2_wdata[25]\, sample_f2_wdata(24) => - \sample_f2_wdata[24]\, sample_f2_wdata(23) => - \sample_f2_wdata[23]\, sample_f2_wdata(22) => - \sample_f2_wdata[22]\, sample_f2_wdata(21) => - \sample_f2_wdata[21]\, sample_f2_wdata(20) => - \sample_f2_wdata[20]\, sample_f2_wdata(19) => - \sample_f2_wdata[19]\, sample_f2_wdata(18) => - \sample_f2_wdata[18]\, sample_f2_wdata(17) => - \sample_f2_wdata[17]\, sample_f2_wdata(16) => - \sample_f2_wdata[16]\, sample_f2_wdata(15) => - \sample_f2_wdata[15]\, sample_f2_wdata(14) => - \sample_f2_wdata[14]\, sample_f2_wdata(13) => - \sample_f2_wdata[13]\, sample_f2_wdata(12) => - \sample_f2_wdata[12]\, sample_f2_wdata(11) => - \sample_f2_wdata[11]\, sample_f2_wdata(10) => - \sample_f2_wdata[10]\, sample_f2_wdata(9) => - \sample_f2_wdata[9]\, sample_f2_wdata(8) => - \sample_f2_wdata[8]\, sample_f2_wdata(7) => - \sample_f2_wdata[7]\, sample_f2_wdata(6) => - \sample_f2_wdata[6]\, sample_f2_wdata(5) => - \sample_f2_wdata[5]\, sample_f2_wdata(4) => - \sample_f2_wdata[4]\, sample_f2_wdata(3) => - \sample_f2_wdata[3]\, sample_f2_wdata(2) => - \sample_f2_wdata[2]\, sample_f2_wdata(1) => - \sample_f2_wdata[1]\, sample_f2_wdata(0) => - \sample_f2_wdata[0]\, sample_f0_val => sample_f0_val, - sample_f0_val_2 => sample_f0_val_2, lclk_c => lclk_c, - sample_f2_val => sample_f2_val, sample_f0_val_0 => - sample_f0_val_0, rstn => rstn); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I38_Y : - AO13 - port map(A => N194_0, B => \sample_filter_v2_out[99]\, C - => \sample_filter_v2_out[117]\, Y => N264_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I95_Y_0 : - XNOR2 - port map(A => N294_i, B => N183, Y => - \sample_data_shaping_f2_f1_s[2]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[33]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[33]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[33]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_Y : - OR2B - port map(A => SUB_16x16_medium_area_I53_Y_0, B => - I53_un1_Y_0, Y => N278); - - sample_val_delay_4 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_4\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y : - AO1B - port map(A => SUB_16x16_medium_area_I56_un1_Y_0_0, B => - N278, C => SUB_16x16_medium_area_I56_Y_1_0, Y => N268); - - \SampleLoop_data_shaping.14.sample_data_shaping_out_RNO[111]\ : - MX2B - port map(A => \sample_filter_v2_out[111]\, B => - \sample_data_shaping_f1_f0_s_i[14]\, S => - data_shaping_SP0, Y => \sample_data_shaping_out_349[111]\); - - sample_val_delay_0 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_0\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[122]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_85[122]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[122]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[20]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[20]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[20]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_Y : - OR2B - port map(A => SUB_16x16_medium_area_I53_Y_0_0, B => - I53_un1_Y, Y => N278_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I87_Y : - AO18 - port map(A => N258, B => \sample_filter_v2_out[132]\, C => - \sample_filter_v2_out[114]\, Y => N284_i); - - \SampleLoop_data_shaping.11.sample_data_shaping_out_RNO[96]\ : - MX2 - port map(A => \sample_filter_v2_out[96]\, B => - \sample_data_shaping_f2_f1_s[11]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_281[96]\); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[3]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[3]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[3]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_un1_Y_0 : - NOR2B - port map(A => N229_0, B => N245_0, Y => - SUB_16x16_medium_area_I57_un1_Y_0_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I43_Y : - NOR2B - port map(A => N187, B => N185, Y => N275_0); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[58]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[58]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[58]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I46_Y : - OR2A - port map(A => \sample_filter_v2_out[143]\, B => - \sample_filter_v2_out[125]\, Y => N225_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[26]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[26]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[26]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[56]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[56]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[56]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I102_Y_0 : - XOR2 - port map(A => N270_0, B => N197_0, Y => - \sample_data_shaping_f2_f1_s[9]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I21_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[138]\, B => - \sample_filter_v2_out[120]\, Y => N189); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[143]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[143]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[143]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out_RNO[107]\ : - AX1C - port map(A => \sample_filter_v2_out[125]\, B => - data_shaping_SP1, C => \sample_filter_v2_out[107]\, Y => - \sample_data_shaping_out_17[107]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[27]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[27]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[27]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_un1_Y : - OR3C - port map(A => N225, B => N183, C => N181, Y => I53_un1_Y); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I85_un1_Y : - NOR2B - port map(A => N278, B => N275_0, Y => I85_un1_Y); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[136]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[136]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[136]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I39_Y : - XA1A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N195, Y => N265); - - lpp_waveform_1 : lpp_waveform - port map(status_full_ack(3) => status_full_ack(3), - status_full_ack(2) => status_full_ack(2), - status_full_ack(1) => status_full_ack(1), - status_full_ack(0) => status_full_ack(0), hburst(2) => - hburst(2), hburst(1) => hburst(1), hburst(0) => hburst(0), - htrans(1) => htrans(1), htrans(0) => htrans(0), - iosn_2(93) => iosn_2(93), hresp(0) => hresp(0), - iosn_1(93) => iosn_1(93), nhmaster_1_i(0) => - nhmaster_1_i(0), hsize(1) => hsize(1), hsize(0) => - hsize(0), hmaster_0(1) => hmaster_0(1), haddr(31) => - haddr(31), haddr(30) => haddr(30), haddr(29) => haddr(29), - haddr(28) => haddr(28), haddr(27) => haddr(27), haddr(26) - => haddr(26), haddr(25) => haddr(25), haddr(24) => - haddr(24), haddr(23) => haddr(23), haddr(22) => haddr(22), - haddr(21) => haddr(21), haddr(20) => haddr(20), haddr(19) - => haddr(19), haddr(18) => haddr(18), haddr(17) => - haddr(17), haddr(16) => haddr(16), haddr(15) => haddr(15), - haddr(14) => haddr(14), haddr(13) => haddr(13), haddr(12) - => haddr(12), haddr(11) => haddr(11), haddr(10) => - haddr(10), haddr(9) => haddr(9), haddr(8) => haddr(8), - haddr(7) => haddr(7), haddr(6) => haddr(6), haddr(5) => - haddr(5), haddr(4) => haddr(4), haddr(3) => haddr(3), - haddr(2) => haddr(2), haddr(1) => haddr(1), haddr(0) => - haddr(0), bco_msb_1(1) => bco_msb_1(1), - hmaster_0_0_RNIFCVH1_0(1) => hmaster_0_0_RNIFCVH1_0(1), - hgrant(3) => hgrant(3), iosn_0(93) => iosn_0(93), - bco_msb_1_m(1) => bco_msb_1_m(1), nhmaster_1_iv_0(1) => - nhmaster_1_iv_0(1), l1_0_m(1) => l1_0_m(1), - nb_burst_available(10) => nb_burst_available(10), - nb_burst_available(9) => nb_burst_available(9), - nb_burst_available(8) => nb_burst_available(8), - nb_burst_available(7) => nb_burst_available(7), - nb_burst_available(6) => nb_burst_available(6), - nb_burst_available(5) => nb_burst_available(5), - nb_burst_available(4) => nb_burst_available(4), - nb_burst_available(3) => nb_burst_available(3), - nb_burst_available(2) => nb_burst_available(2), - nb_burst_available(1) => nb_burst_available(1), - nb_burst_available(0) => nb_burst_available(0), - status_full_err(3) => status_full_err(3), - status_full_err(2) => status_full_err(2), - status_full_err(1) => status_full_err(1), - status_full_err(0) => status_full_err(0), status_full(3) - => status_full(3), status_full(2) => status_full(2), - status_full(1) => status_full(1), status_full(0) => - status_full(0), addr_data_f3(31) => addr_data_f3(31), - addr_data_f3(30) => addr_data_f3(30), addr_data_f3(29) - => addr_data_f3(29), addr_data_f3(28) => - addr_data_f3(28), addr_data_f3(27) => addr_data_f3(27), - addr_data_f3(26) => addr_data_f3(26), addr_data_f3(25) - => addr_data_f3(25), addr_data_f3(24) => - addr_data_f3(24), addr_data_f3(23) => addr_data_f3(23), - addr_data_f3(22) => addr_data_f3(22), addr_data_f3(21) - => addr_data_f3(21), addr_data_f3(20) => - addr_data_f3(20), addr_data_f3(19) => addr_data_f3(19), - addr_data_f3(18) => addr_data_f3(18), addr_data_f3(17) - => addr_data_f3(17), addr_data_f3(16) => - addr_data_f3(16), addr_data_f3(15) => addr_data_f3(15), - addr_data_f3(14) => addr_data_f3(14), addr_data_f3(13) - => addr_data_f3(13), addr_data_f3(12) => - addr_data_f3(12), addr_data_f3(11) => addr_data_f3(11), - addr_data_f3(10) => addr_data_f3(10), addr_data_f3(9) => - addr_data_f3(9), addr_data_f3(8) => addr_data_f3(8), - addr_data_f3(7) => addr_data_f3(7), addr_data_f3(6) => - addr_data_f3(6), addr_data_f3(5) => addr_data_f3(5), - addr_data_f3(4) => addr_data_f3(4), addr_data_f3(3) => - addr_data_f3(3), addr_data_f3(2) => addr_data_f3(2), - addr_data_f3(1) => addr_data_f3(1), addr_data_f3(0) => - addr_data_f3(0), addr_data_f2(31) => addr_data_f2(31), - addr_data_f2(30) => addr_data_f2(30), addr_data_f2(29) - => addr_data_f2(29), addr_data_f2(28) => - addr_data_f2(28), addr_data_f2(27) => addr_data_f2(27), - addr_data_f2(26) => addr_data_f2(26), addr_data_f2(25) - => addr_data_f2(25), addr_data_f2(24) => - addr_data_f2(24), addr_data_f2(23) => addr_data_f2(23), - addr_data_f2(22) => addr_data_f2(22), addr_data_f2(21) - => addr_data_f2(21), addr_data_f2(20) => - addr_data_f2(20), addr_data_f2(19) => addr_data_f2(19), - addr_data_f2(18) => addr_data_f2(18), addr_data_f2(17) - => addr_data_f2(17), addr_data_f2(16) => - addr_data_f2(16), addr_data_f2(15) => addr_data_f2(15), - addr_data_f2(14) => addr_data_f2(14), addr_data_f2(13) - => addr_data_f2(13), addr_data_f2(12) => - addr_data_f2(12), addr_data_f2(11) => addr_data_f2(11), - addr_data_f2(10) => addr_data_f2(10), addr_data_f2(9) => - addr_data_f2(9), addr_data_f2(8) => addr_data_f2(8), - addr_data_f2(7) => addr_data_f2(7), addr_data_f2(6) => - addr_data_f2(6), addr_data_f2(5) => addr_data_f2(5), - addr_data_f2(4) => addr_data_f2(4), addr_data_f2(3) => - addr_data_f2(3), addr_data_f2(2) => addr_data_f2(2), - addr_data_f2(1) => addr_data_f2(1), addr_data_f2(0) => - addr_data_f2(0), addr_data_f1(31) => addr_data_f1(31), - addr_data_f1(30) => addr_data_f1(30), addr_data_f1(29) - => addr_data_f1(29), addr_data_f1(28) => - addr_data_f1(28), addr_data_f1(27) => addr_data_f1(27), - addr_data_f1(26) => addr_data_f1(26), addr_data_f1(25) - => addr_data_f1(25), addr_data_f1(24) => - addr_data_f1(24), addr_data_f1(23) => addr_data_f1(23), - addr_data_f1(22) => addr_data_f1(22), addr_data_f1(21) - => addr_data_f1(21), addr_data_f1(20) => - addr_data_f1(20), addr_data_f1(19) => addr_data_f1(19), - addr_data_f1(18) => addr_data_f1(18), addr_data_f1(17) - => addr_data_f1(17), addr_data_f1(16) => - addr_data_f1(16), addr_data_f1(15) => addr_data_f1(15), - addr_data_f1(14) => addr_data_f1(14), addr_data_f1(13) - => addr_data_f1(13), addr_data_f1(12) => - addr_data_f1(12), addr_data_f1(11) => addr_data_f1(11), - addr_data_f1(10) => addr_data_f1(10), addr_data_f1(9) => - addr_data_f1(9), addr_data_f1(8) => addr_data_f1(8), - addr_data_f1(7) => addr_data_f1(7), addr_data_f1(6) => - addr_data_f1(6), addr_data_f1(5) => addr_data_f1(5), - addr_data_f1(4) => addr_data_f1(4), addr_data_f1(3) => - addr_data_f1(3), addr_data_f1(2) => addr_data_f1(2), - addr_data_f1(1) => addr_data_f1(1), addr_data_f1(0) => - addr_data_f1(0), addr_data_f0(31) => addr_data_f0(31), - addr_data_f0(30) => addr_data_f0(30), addr_data_f0(29) - => addr_data_f0(29), addr_data_f0(28) => - addr_data_f0(28), addr_data_f0(27) => addr_data_f0(27), - addr_data_f0(26) => addr_data_f0(26), addr_data_f0(25) - => addr_data_f0(25), addr_data_f0(24) => - addr_data_f0(24), addr_data_f0(23) => addr_data_f0(23), - addr_data_f0(22) => addr_data_f0(22), addr_data_f0(21) - => addr_data_f0(21), addr_data_f0(20) => - addr_data_f0(20), addr_data_f0(19) => addr_data_f0(19), - addr_data_f0(18) => addr_data_f0(18), addr_data_f0(17) - => addr_data_f0(17), addr_data_f0(16) => - addr_data_f0(16), addr_data_f0(15) => addr_data_f0(15), - addr_data_f0(14) => addr_data_f0(14), addr_data_f0(13) - => addr_data_f0(13), addr_data_f0(12) => - addr_data_f0(12), addr_data_f0(11) => addr_data_f0(11), - addr_data_f0(10) => addr_data_f0(10), addr_data_f0(9) => - addr_data_f0(9), addr_data_f0(8) => addr_data_f0(8), - addr_data_f0(7) => addr_data_f0(7), addr_data_f0(6) => - addr_data_f0(6), addr_data_f0(5) => addr_data_f0(5), - addr_data_f0(4) => addr_data_f0(4), addr_data_f0(3) => - addr_data_f0(3), addr_data_f0(2) => addr_data_f0(2), - addr_data_f0(1) => addr_data_f0(1), addr_data_f0(0) => - addr_data_f0(0), hwdata(31) => hwdata(31), hwdata(30) => - hwdata(30), hwdata(29) => hwdata(29), hwdata(28) => - hwdata(28), hwdata(27) => hwdata(27), hwdata(26) => - hwdata(26), hwdata(25) => hwdata(25), hwdata(24) => - hwdata(24), hwdata(23) => hwdata(23), hwdata(22) => - hwdata(22), hwdata(21) => hwdata(21), hwdata(20) => - hwdata(20), hwdata(19) => hwdata(19), hwdata(18) => - hwdata(18), hwdata(17) => hwdata(17), hwdata(16) => - hwdata(16), hwdata(15) => hwdata(15), hwdata(14) => - hwdata(14), hwdata(13) => hwdata(13), hwdata(12) => - hwdata(12), hwdata(11) => hwdata(11), hwdata(10) => - hwdata(10), hwdata(9) => hwdata(9), hwdata(8) => - hwdata(8), hwdata(7) => hwdata(7), hwdata(6) => hwdata(6), - hwdata(5) => hwdata(5), hwdata(4) => hwdata(4), hwdata(3) - => hwdata(3), hwdata(2) => hwdata(2), hwdata(1) => - hwdata(1), hwdata(0) => hwdata(0), status_new_err(3) => - status_new_err(3), status_new_err(2) => status_new_err(2), - status_new_err(1) => status_new_err(1), status_new_err(0) - => status_new_err(0), sample_f3_wdata(95) => - \sample_f3_wdata[95]\, sample_f3_wdata(94) => - \sample_f3_wdata[94]\, sample_f3_wdata(93) => - \sample_f3_wdata[93]\, sample_f3_wdata(92) => - \sample_f3_wdata[92]\, sample_f3_wdata(91) => - \sample_f3_wdata[91]\, sample_f3_wdata(90) => - \sample_f3_wdata[90]\, sample_f3_wdata(89) => - \sample_f3_wdata[89]\, sample_f3_wdata(88) => - \sample_f3_wdata[88]\, sample_f3_wdata(87) => - \sample_f3_wdata[87]\, sample_f3_wdata(86) => - \sample_f3_wdata[86]\, sample_f3_wdata(85) => - \sample_f3_wdata[85]\, sample_f3_wdata(84) => - \sample_f3_wdata[84]\, sample_f3_wdata(83) => - \sample_f3_wdata[83]\, sample_f3_wdata(82) => - \sample_f3_wdata[82]\, sample_f3_wdata(81) => - \sample_f3_wdata[81]\, sample_f3_wdata(80) => - \sample_f3_wdata[80]\, sample_f3_wdata(79) => - \sample_f3_wdata[79]\, sample_f3_wdata(78) => - \sample_f3_wdata[78]\, sample_f3_wdata(77) => - \sample_f3_wdata[77]\, sample_f3_wdata(76) => - \sample_f3_wdata[76]\, sample_f3_wdata(75) => - \sample_f3_wdata[75]\, sample_f3_wdata(74) => - \sample_f3_wdata[74]\, sample_f3_wdata(73) => - \sample_f3_wdata[73]\, sample_f3_wdata(72) => - \sample_f3_wdata[72]\, sample_f3_wdata(71) => - \sample_f3_wdata[71]\, sample_f3_wdata(70) => - \sample_f3_wdata[70]\, sample_f3_wdata(69) => - \sample_f3_wdata[69]\, sample_f3_wdata(68) => - \sample_f3_wdata[68]\, sample_f3_wdata(67) => - \sample_f3_wdata[67]\, sample_f3_wdata(66) => - \sample_f3_wdata[66]\, sample_f3_wdata(65) => - \sample_f3_wdata[65]\, sample_f3_wdata(64) => - \sample_f3_wdata[64]\, sample_f3_wdata(63) => - \sample_f3_wdata[63]\, sample_f3_wdata(62) => - \sample_f3_wdata[62]\, sample_f3_wdata(61) => - \sample_f3_wdata[61]\, sample_f3_wdata(60) => - \sample_f3_wdata[60]\, sample_f3_wdata(59) => - \sample_f3_wdata[59]\, sample_f3_wdata(58) => - \sample_f3_wdata[58]\, sample_f3_wdata(57) => - \sample_f3_wdata[57]\, sample_f3_wdata(56) => - \sample_f3_wdata[56]\, sample_f3_wdata(55) => - \sample_f3_wdata[55]\, sample_f3_wdata(54) => - \sample_f3_wdata[54]\, sample_f3_wdata(53) => - \sample_f3_wdata[53]\, sample_f3_wdata(52) => - \sample_f3_wdata[52]\, sample_f3_wdata(51) => - \sample_f3_wdata[51]\, sample_f3_wdata(50) => - \sample_f3_wdata[50]\, sample_f3_wdata(49) => - \sample_f3_wdata[49]\, sample_f3_wdata(48) => - \sample_f3_wdata[48]\, sample_f3_wdata(47) => - \sample_f3_wdata[47]\, sample_f3_wdata(46) => - \sample_f3_wdata[46]\, sample_f3_wdata(45) => - \sample_f3_wdata[45]\, sample_f3_wdata(44) => - \sample_f3_wdata[44]\, sample_f3_wdata(43) => - \sample_f3_wdata[43]\, sample_f3_wdata(42) => - \sample_f3_wdata[42]\, sample_f3_wdata(41) => - \sample_f3_wdata[41]\, sample_f3_wdata(40) => - \sample_f3_wdata[40]\, sample_f3_wdata(39) => - \sample_f3_wdata[39]\, sample_f3_wdata(38) => - \sample_f3_wdata[38]\, sample_f3_wdata(37) => - \sample_f3_wdata[37]\, sample_f3_wdata(36) => - \sample_f3_wdata[36]\, sample_f3_wdata(35) => - \sample_f3_wdata[35]\, sample_f3_wdata(34) => - \sample_f3_wdata[34]\, sample_f3_wdata(33) => - \sample_f3_wdata[33]\, sample_f3_wdata(32) => - \sample_f3_wdata[32]\, sample_f3_wdata(31) => - \sample_f3_wdata[31]\, sample_f3_wdata(30) => - \sample_f3_wdata[30]\, sample_f3_wdata(29) => - \sample_f3_wdata[29]\, sample_f3_wdata(28) => - \sample_f3_wdata[28]\, sample_f3_wdata(27) => - \sample_f3_wdata[27]\, sample_f3_wdata(26) => - \sample_f3_wdata[26]\, sample_f3_wdata(25) => - \sample_f3_wdata[25]\, sample_f3_wdata(24) => - \sample_f3_wdata[24]\, sample_f3_wdata(23) => - \sample_f3_wdata[23]\, sample_f3_wdata(22) => - \sample_f3_wdata[22]\, sample_f3_wdata(21) => - \sample_f3_wdata[21]\, sample_f3_wdata(20) => - \sample_f3_wdata[20]\, sample_f3_wdata(19) => - \sample_f3_wdata[19]\, sample_f3_wdata(18) => - \sample_f3_wdata[18]\, sample_f3_wdata(17) => - \sample_f3_wdata[17]\, sample_f3_wdata(16) => - \sample_f3_wdata[16]\, sample_f3_wdata(15) => - \sample_f3_wdata[15]\, sample_f3_wdata(14) => - \sample_f3_wdata[14]\, sample_f3_wdata(13) => - \sample_f3_wdata[13]\, sample_f3_wdata(12) => - \sample_f3_wdata[12]\, sample_f3_wdata(11) => - \sample_f3_wdata[11]\, sample_f3_wdata(10) => - \sample_f3_wdata[10]\, sample_f3_wdata(9) => - \sample_f3_wdata[9]\, sample_f3_wdata(8) => - \sample_f3_wdata[8]\, sample_f3_wdata(7) => - \sample_f3_wdata[7]\, sample_f3_wdata(6) => - \sample_f3_wdata[6]\, sample_f3_wdata(5) => - \sample_f3_wdata[5]\, sample_f3_wdata(4) => - \sample_f3_wdata[4]\, sample_f3_wdata(3) => - \sample_f3_wdata[3]\, sample_f3_wdata(2) => - \sample_f3_wdata[2]\, sample_f3_wdata(1) => - \sample_f3_wdata[1]\, sample_f3_wdata(0) => - \sample_f3_wdata[0]\, sample_f2_wdata(95) => - \sample_f2_wdata[95]\, sample_f2_wdata(94) => - \sample_f2_wdata[94]\, sample_f2_wdata(93) => - \sample_f2_wdata[93]\, sample_f2_wdata(92) => - \sample_f2_wdata[92]\, sample_f2_wdata(91) => - \sample_f2_wdata[91]\, sample_f2_wdata(90) => - \sample_f2_wdata[90]\, sample_f2_wdata(89) => - \sample_f2_wdata[89]\, sample_f2_wdata(88) => - \sample_f2_wdata[88]\, sample_f2_wdata(87) => - \sample_f2_wdata[87]\, sample_f2_wdata(86) => - \sample_f2_wdata[86]\, sample_f2_wdata(85) => - \sample_f2_wdata[85]\, sample_f2_wdata(84) => - \sample_f2_wdata[84]\, sample_f2_wdata(83) => - \sample_f2_wdata[83]\, sample_f2_wdata(82) => - \sample_f2_wdata[82]\, sample_f2_wdata(81) => - \sample_f2_wdata[81]\, sample_f2_wdata(80) => - \sample_f2_wdata[80]\, sample_f2_wdata(79) => - \sample_f2_wdata[79]\, sample_f2_wdata(78) => - \sample_f2_wdata[78]\, sample_f2_wdata(77) => - \sample_f2_wdata[77]\, sample_f2_wdata(76) => - \sample_f2_wdata[76]\, sample_f2_wdata(75) => - \sample_f2_wdata[75]\, sample_f2_wdata(74) => - \sample_f2_wdata[74]\, sample_f2_wdata(73) => - \sample_f2_wdata[73]\, sample_f2_wdata(72) => - \sample_f2_wdata[72]\, sample_f2_wdata(71) => - \sample_f2_wdata[71]\, sample_f2_wdata(70) => - \sample_f2_wdata[70]\, sample_f2_wdata(69) => - \sample_f2_wdata[69]\, sample_f2_wdata(68) => - \sample_f2_wdata[68]\, sample_f2_wdata(67) => - \sample_f2_wdata[67]\, sample_f2_wdata(66) => - \sample_f2_wdata[66]\, sample_f2_wdata(65) => - \sample_f2_wdata[65]\, sample_f2_wdata(64) => - \sample_f2_wdata[64]\, sample_f2_wdata(63) => - \sample_f2_wdata[63]\, sample_f2_wdata(62) => - \sample_f2_wdata[62]\, sample_f2_wdata(61) => - \sample_f2_wdata[61]\, sample_f2_wdata(60) => - \sample_f2_wdata[60]\, sample_f2_wdata(59) => - \sample_f2_wdata[59]\, sample_f2_wdata(58) => - \sample_f2_wdata[58]\, sample_f2_wdata(57) => - \sample_f2_wdata[57]\, sample_f2_wdata(56) => - \sample_f2_wdata[56]\, sample_f2_wdata(55) => - \sample_f2_wdata[55]\, sample_f2_wdata(54) => - \sample_f2_wdata[54]\, sample_f2_wdata(53) => - \sample_f2_wdata[53]\, sample_f2_wdata(52) => - \sample_f2_wdata[52]\, sample_f2_wdata(51) => - \sample_f2_wdata[51]\, sample_f2_wdata(50) => - \sample_f2_wdata[50]\, sample_f2_wdata(49) => - \sample_f2_wdata[49]\, sample_f2_wdata(48) => - \sample_f2_wdata[48]\, sample_f2_wdata(47) => - \sample_f2_wdata[47]\, sample_f2_wdata(46) => - \sample_f2_wdata[46]\, sample_f2_wdata(45) => - \sample_f2_wdata[45]\, sample_f2_wdata(44) => - \sample_f2_wdata[44]\, sample_f2_wdata(43) => - \sample_f2_wdata[43]\, sample_f2_wdata(42) => - \sample_f2_wdata[42]\, sample_f2_wdata(41) => - \sample_f2_wdata[41]\, sample_f2_wdata(40) => - \sample_f2_wdata[40]\, sample_f2_wdata(39) => - \sample_f2_wdata[39]\, sample_f2_wdata(38) => - \sample_f2_wdata[38]\, sample_f2_wdata(37) => - \sample_f2_wdata[37]\, sample_f2_wdata(36) => - \sample_f2_wdata[36]\, sample_f2_wdata(35) => - \sample_f2_wdata[35]\, sample_f2_wdata(34) => - \sample_f2_wdata[34]\, sample_f2_wdata(33) => - \sample_f2_wdata[33]\, sample_f2_wdata(32) => - \sample_f2_wdata[32]\, sample_f2_wdata(31) => - \sample_f2_wdata[31]\, sample_f2_wdata(30) => - \sample_f2_wdata[30]\, sample_f2_wdata(29) => - \sample_f2_wdata[29]\, sample_f2_wdata(28) => - \sample_f2_wdata[28]\, sample_f2_wdata(27) => - \sample_f2_wdata[27]\, sample_f2_wdata(26) => - \sample_f2_wdata[26]\, sample_f2_wdata(25) => - \sample_f2_wdata[25]\, sample_f2_wdata(24) => - \sample_f2_wdata[24]\, sample_f2_wdata(23) => - \sample_f2_wdata[23]\, sample_f2_wdata(22) => - \sample_f2_wdata[22]\, sample_f2_wdata(21) => - \sample_f2_wdata[21]\, sample_f2_wdata(20) => - \sample_f2_wdata[20]\, sample_f2_wdata(19) => - \sample_f2_wdata[19]\, sample_f2_wdata(18) => - \sample_f2_wdata[18]\, sample_f2_wdata(17) => - \sample_f2_wdata[17]\, sample_f2_wdata(16) => - \sample_f2_wdata[16]\, sample_f2_wdata(15) => - \sample_f2_wdata[15]\, sample_f2_wdata(14) => - \sample_f2_wdata[14]\, sample_f2_wdata(13) => - \sample_f2_wdata[13]\, sample_f2_wdata(12) => - \sample_f2_wdata[12]\, sample_f2_wdata(11) => - \sample_f2_wdata[11]\, sample_f2_wdata(10) => - \sample_f2_wdata[10]\, sample_f2_wdata(9) => - \sample_f2_wdata[9]\, sample_f2_wdata(8) => - \sample_f2_wdata[8]\, sample_f2_wdata(7) => - \sample_f2_wdata[7]\, sample_f2_wdata(6) => - \sample_f2_wdata[6]\, sample_f2_wdata(5) => - \sample_f2_wdata[5]\, sample_f2_wdata(4) => - \sample_f2_wdata[4]\, sample_f2_wdata(3) => - \sample_f2_wdata[3]\, sample_f2_wdata(2) => - \sample_f2_wdata[2]\, sample_f2_wdata(1) => - \sample_f2_wdata[1]\, sample_f2_wdata(0) => - \sample_f2_wdata[0]\, sample_f1_15 => \sample_f1[63]\, - sample_f1_47 => \sample_f1[95]\, sample_f1_14 => - \sample_f1[62]\, sample_f1_46 => \sample_f1[94]\, - sample_f1_13 => \sample_f1[61]\, sample_f1_45 => - \sample_f1[93]\, sample_f1_12 => \sample_f1[60]\, - sample_f1_44 => \sample_f1[92]\, sample_f1_60 => - \sample_f1[108]\, sample_f1_59 => \sample_f1[107]\, - sample_f1_58 => \sample_f1[106]\, sample_f1_57 => - \sample_f1[105]\, sample_f1_56 => \sample_f1[104]\, - sample_f1_55 => \sample_f1[103]\, sample_f1_54 => - \sample_f1[102]\, sample_f1_53 => \sample_f1[101]\, - sample_f1_52 => \sample_f1[100]\, sample_f1_51 => - \sample_f1[99]\, sample_f1_50 => \sample_f1[98]\, - sample_f1_49 => \sample_f1[97]\, sample_f1_48 => - \sample_f1[96]\, sample_f1_4 => \sample_f1[52]\, - sample_f1_36 => \sample_f1[84]\, sample_f1_3 => - \sample_f1[51]\, sample_f1_35 => \sample_f1[83]\, - sample_f1_2 => \sample_f1[50]\, sample_f1_34 => - \sample_f1[82]\, sample_f1_1 => \sample_f1[49]\, - sample_f1_33 => \sample_f1[81]\, sample_f1_0 => - \sample_f1[48]\, sample_f1_32 => \sample_f1[80]\, - sample_f1_63 => \sample_f1[111]\, sample_f1_62 => - \sample_f1[110]\, sample_f1_61 => \sample_f1[109]\, - sample_f1_11 => \sample_f1[59]\, sample_f1_43 => - \sample_f1[91]\, sample_f1_10 => \sample_f1[58]\, - sample_f1_42 => \sample_f1[90]\, sample_f1_9 => - \sample_f1[57]\, sample_f1_41 => \sample_f1[89]\, - sample_f1_8 => \sample_f1[56]\, sample_f1_40 => - \sample_f1[88]\, sample_f1_7 => \sample_f1[55]\, - sample_f1_39 => \sample_f1[87]\, sample_f1_6 => - \sample_f1[54]\, sample_f1_38 => \sample_f1[86]\, - sample_f1_5 => \sample_f1[53]\, sample_f1_37 => - \sample_f1[85]\, sample_f1_wdata_0 => - \sample_f1_wdata[0]\, sample_f1_wdata_1 => - \sample_f1_wdata[1]\, sample_f1_wdata_2 => - \sample_f1_wdata[2]\, sample_f1_wdata_3 => - \sample_f1_wdata[3]\, sample_f1_wdata_4 => - \sample_f1_wdata[4]\, sample_f1_wdata_5 => - \sample_f1_wdata[5]\, sample_f1_wdata_6 => - \sample_f1_wdata[6]\, sample_f1_wdata_7 => - \sample_f1_wdata[7]\, sample_f1_wdata_8 => - \sample_f1_wdata[8]\, sample_f1_wdata_9 => - \sample_f1_wdata[9]\, sample_f1_wdata_10 => - \sample_f1_wdata[10]\, sample_f1_wdata_11 => - \sample_f1_wdata[11]\, sample_f1_wdata_12 => - \sample_f1_wdata[12]\, sample_f1_wdata_13 => - \sample_f1_wdata[13]\, sample_f1_wdata_14 => - \sample_f1_wdata[14]\, sample_f1_wdata_15 => - \sample_f1_wdata[15]\, sample_f1_wdata_48 => - \sample_f1_wdata[48]\, sample_f1_wdata_49 => - \sample_f1_wdata[49]\, sample_f1_wdata_50 => - \sample_f1_wdata[50]\, sample_f1_wdata_51 => - \sample_f1_wdata[51]\, sample_f1_wdata_52 => - \sample_f1_wdata[52]\, sample_f1_wdata_53 => - \sample_f1_wdata[53]\, sample_f1_wdata_54 => - \sample_f1_wdata[54]\, sample_f1_wdata_55 => - \sample_f1_wdata[55]\, sample_f1_wdata_56 => - \sample_f1_wdata[56]\, sample_f1_wdata_57 => - \sample_f1_wdata[57]\, sample_f1_wdata_58 => - \sample_f1_wdata[58]\, sample_f1_wdata_59 => - \sample_f1_wdata[59]\, sample_f1_wdata_60 => - \sample_f1_wdata[60]\, sample_f1_wdata_61 => - \sample_f1_wdata[61]\, sample_f1_wdata_62 => - \sample_f1_wdata[62]\, sample_f1_wdata_63 => - \sample_f1_wdata[63]\, sample_f1_wdata_64 => - \sample_f1_wdata[64]\, sample_f1_wdata_65 => - \sample_f1_wdata[65]\, sample_f1_wdata_66 => - \sample_f1_wdata[66]\, sample_f1_wdata_67 => - \sample_f1_wdata[67]\, sample_f1_wdata_68 => - \sample_f1_wdata[68]\, sample_f1_wdata_69 => - \sample_f1_wdata[69]\, sample_f1_wdata_70 => - \sample_f1_wdata[70]\, sample_f1_wdata_71 => - \sample_f1_wdata[71]\, sample_f1_wdata_72 => - \sample_f1_wdata[72]\, sample_f1_wdata_73 => - \sample_f1_wdata[73]\, sample_f1_wdata_74 => - \sample_f1_wdata[74]\, sample_f1_wdata_75 => - \sample_f1_wdata[75]\, sample_f1_wdata_76 => - \sample_f1_wdata[76]\, sample_f1_wdata_77 => - \sample_f1_wdata[77]\, sample_f1_wdata_78 => - \sample_f1_wdata[78]\, sample_f1_wdata_79 => - \sample_f1_wdata[79]\, sample_f1_wdata_80 => - \sample_f1_wdata[80]\, sample_f1_wdata_81 => - \sample_f1_wdata[81]\, sample_f1_wdata_82 => - \sample_f1_wdata[82]\, sample_f1_wdata_83 => - \sample_f1_wdata[83]\, sample_f1_wdata_84 => - \sample_f1_wdata[84]\, sample_f1_wdata_85 => - \sample_f1_wdata[85]\, sample_f1_wdata_86 => - \sample_f1_wdata[86]\, sample_f1_wdata_87 => - \sample_f1_wdata[87]\, sample_f1_wdata_88 => - \sample_f1_wdata[88]\, sample_f1_wdata_89 => - \sample_f1_wdata[89]\, sample_f1_wdata_90 => - \sample_f1_wdata[90]\, sample_f1_wdata_91 => - \sample_f1_wdata[91]\, sample_f1_wdata_92 => - \sample_f1_wdata[92]\, sample_f1_wdata_93 => - \sample_f1_wdata[93]\, sample_f1_wdata_94 => - \sample_f1_wdata[94]\, sample_f1_wdata_95 => - \sample_f1_wdata[95]\, sample_f0_15 => \sample_f0[63]\, - sample_f0_47 => \sample_f0[95]\, sample_f0_14 => - \sample_f0[62]\, sample_f0_46 => \sample_f0[94]\, - sample_f0_13 => \sample_f0[61]\, sample_f0_45 => - \sample_f0[93]\, sample_f0_12 => \sample_f0[60]\, - sample_f0_44 => \sample_f0[92]\, sample_f0_60 => - \sample_f0[108]\, sample_f0_59 => \sample_f0[107]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_57 => - \sample_f0[105]\, sample_f0_56 => \sample_f0[104]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_54 => - \sample_f0[102]\, sample_f0_53 => \sample_f0[101]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_51 => - \sample_f0[99]\, sample_f0_50 => \sample_f0[98]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_48 => - \sample_f0[96]\, sample_f0_4 => \sample_f0[52]\, - sample_f0_36 => \sample_f0[84]\, sample_f0_3 => - \sample_f0[51]\, sample_f0_35 => \sample_f0[83]\, - sample_f0_2 => \sample_f0[50]\, sample_f0_34 => - \sample_f0[82]\, sample_f0_1 => \sample_f0[49]\, - sample_f0_33 => \sample_f0[81]\, sample_f0_0 => - \sample_f0[48]\, sample_f0_32 => \sample_f0[80]\, - sample_f0_63 => \sample_f0[111]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_61 => \sample_f0[109]\, - sample_f0_11 => \sample_f0[59]\, sample_f0_43 => - \sample_f0[91]\, sample_f0_10 => \sample_f0[58]\, - sample_f0_42 => \sample_f0[90]\, sample_f0_9 => - \sample_f0[57]\, sample_f0_41 => \sample_f0[89]\, - sample_f0_8 => \sample_f0[56]\, sample_f0_40 => - \sample_f0[88]\, sample_f0_7 => \sample_f0[55]\, - sample_f0_39 => \sample_f0[87]\, sample_f0_6 => - \sample_f0[54]\, sample_f0_38 => \sample_f0[86]\, - sample_f0_5 => \sample_f0[53]\, sample_f0_37 => - \sample_f0[85]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, coarse_time(0) => coarse_time(0), - delta_snapshot(15) => delta_snapshot(15), - delta_snapshot(14) => delta_snapshot(14), - delta_snapshot(13) => delta_snapshot(13), - delta_snapshot(12) => delta_snapshot(12), - delta_snapshot(11) => delta_snapshot(11), - delta_snapshot(10) => delta_snapshot(10), - delta_snapshot(9) => delta_snapshot(9), delta_snapshot(8) - => delta_snapshot(8), delta_snapshot(7) => - delta_snapshot(7), delta_snapshot(6) => delta_snapshot(6), - delta_snapshot(5) => delta_snapshot(5), delta_snapshot(4) - => delta_snapshot(4), delta_snapshot(3) => - delta_snapshot(3), delta_snapshot(2) => delta_snapshot(2), - delta_snapshot(1) => delta_snapshot(1), delta_snapshot(0) - => delta_snapshot(0), delta_f2_f1(9) => delta_f2_f1(9), - delta_f2_f1(8) => delta_f2_f1(8), delta_f2_f1(7) => - delta_f2_f1(7), delta_f2_f1(6) => delta_f2_f1(6), - delta_f2_f1(5) => delta_f2_f1(5), delta_f2_f1(4) => - delta_f2_f1(4), delta_f2_f1(3) => delta_f2_f1(3), - delta_f2_f1(2) => delta_f2_f1(2), delta_f2_f1(1) => - delta_f2_f1(1), delta_f2_f1(0) => delta_f2_f1(0), - delta_f2_f0(9) => delta_f2_f0(9), delta_f2_f0(8) => - delta_f2_f0(8), delta_f2_f0(7) => delta_f2_f0(7), - delta_f2_f0(6) => delta_f2_f0(6), delta_f2_f0(5) => - delta_f2_f0(5), delta_f2_f0(4) => delta_f2_f0(4), - delta_f2_f0(3) => delta_f2_f0(3), delta_f2_f0(2) => - delta_f2_f0(2), delta_f2_f0(1) => delta_f2_f0(1), - delta_f2_f0(0) => delta_f2_f0(0), coarse_time_i(0) => - coarse_time_i(0), nb_snapshot_param(10) => - nb_snapshot_param(10), nb_snapshot_param(9) => - nb_snapshot_param(9), nb_snapshot_param(8) => - nb_snapshot_param(8), nb_snapshot_param(7) => - nb_snapshot_param(7), nb_snapshot_param(6) => - nb_snapshot_param(6), nb_snapshot_param(5) => - nb_snapshot_param(5), nb_snapshot_param(4) => - nb_snapshot_param(4), nb_snapshot_param(3) => - nb_snapshot_param(3), nb_snapshot_param(2) => - nb_snapshot_param(2), nb_snapshot_param(1) => - nb_snapshot_param(1), nb_snapshot_param(0) => - nb_snapshot_param(0), IdlePhase => IdlePhase, hwrite => - hwrite, un1_dmain_6 => un1_dmain_6, arb_1 => arb_1, - hbusreq_i_3 => hbusreq_i_3, Lock_RNIU86D => Lock_RNIU86D, - un1_nhmaster_0_sqmuxa_1 => un1_nhmaster_0_sqmuxa_1, - rstoutl_RNIGJKSJO => rstoutl_RNIGJKSJO, m19_0_N_15_i_0_li - => m19_0_N_15_i_0_li, m19_a0_6_i_0 => m19_a0_6_i_0, - m19_a1_6_i_0 => m19_a1_6_i_0, m26_m1_e => m26_m1_e, - sample_f3_val => sample_f3_val, enable_f3 => enable_f3, - burst_f2 => burst_f2, enable_f2 => enable_f2, - sample_f1_val_0 => sample_f1_val_0, burst_f1 => burst_f1, - enable_f1 => enable_f1, data_shaping_R1_0 => - data_shaping_R1_0, data_shaping_R1 => data_shaping_R1, - burst_f0 => burst_f0, enable_f0 => enable_f0, - data_shaping_R0_0 => data_shaping_R0_0, data_shaping_R0 - => data_shaping_R0, lclk_c => lclk_c, rstn => rstn, - sample_f0_val_0 => sample_f0_val_0, sample_f2_val => - sample_f2_val); - - Downsampling_f0 : Downsampling_8_16_4 - port map(sample_f0_0 => \sample_f0[48]\, sample_f0_1 => - \sample_f0[49]\, sample_f0_2 => \sample_f0[50]\, - sample_f0_3 => \sample_f0[51]\, sample_f0_4 => - \sample_f0[52]\, sample_f0_5 => \sample_f0[53]\, - sample_f0_6 => \sample_f0[54]\, sample_f0_7 => - \sample_f0[55]\, sample_f0_8 => \sample_f0[56]\, - sample_f0_9 => \sample_f0[57]\, sample_f0_10 => - \sample_f0[58]\, sample_f0_11 => \sample_f0[59]\, - sample_f0_12 => \sample_f0[60]\, sample_f0_13 => - \sample_f0[61]\, sample_f0_14 => \sample_f0[62]\, - sample_f0_15 => \sample_f0[63]\, sample_f0_32 => - \sample_f0[80]\, sample_f0_33 => \sample_f0[81]\, - sample_f0_34 => \sample_f0[82]\, sample_f0_35 => - \sample_f0[83]\, sample_f0_36 => \sample_f0[84]\, - sample_f0_37 => \sample_f0[85]\, sample_f0_38 => - \sample_f0[86]\, sample_f0_39 => \sample_f0[87]\, - sample_f0_40 => \sample_f0[88]\, sample_f0_41 => - \sample_f0[89]\, sample_f0_42 => \sample_f0[90]\, - sample_f0_43 => \sample_f0[91]\, sample_f0_44 => - \sample_f0[92]\, sample_f0_45 => \sample_f0[93]\, - sample_f0_46 => \sample_f0[94]\, sample_f0_47 => - \sample_f0[95]\, sample_f0_48 => \sample_f0[96]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_50 => - \sample_f0[98]\, sample_f0_51 => \sample_f0[99]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_53 => - \sample_f0[101]\, sample_f0_54 => \sample_f0[102]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_56 => - \sample_f0[104]\, sample_f0_57 => \sample_f0[105]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_59 => - \sample_f0[107]\, sample_f0_60 => \sample_f0[108]\, - sample_f0_61 => \sample_f0[109]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_63 => \sample_f0[111]\, - sample_data_shaping_out_0 => \sample_data_shaping_out[2]\, - sample_data_shaping_out_1 => \sample_data_shaping_out[3]\, - sample_data_shaping_out_2 => \sample_data_shaping_out[4]\, - sample_data_shaping_out_3 => \sample_data_shaping_out[5]\, - sample_data_shaping_out_4 => \sample_data_shaping_out[6]\, - sample_data_shaping_out_5 => \sample_data_shaping_out[7]\, - sample_data_shaping_out_6 => \sample_data_shaping_out[8]\, - sample_data_shaping_out_7 => \sample_data_shaping_out[9]\, - sample_data_shaping_out_8 => - \sample_data_shaping_out[10]\, sample_data_shaping_out_9 - => \sample_data_shaping_out[11]\, - sample_data_shaping_out_10 => - \sample_data_shaping_out[12]\, sample_data_shaping_out_11 - => \sample_data_shaping_out[13]\, - sample_data_shaping_out_12 => - \sample_data_shaping_out[14]\, sample_data_shaping_out_13 - => \sample_data_shaping_out[15]\, - sample_data_shaping_out_14 => - \sample_data_shaping_out[16]\, sample_data_shaping_out_15 - => \sample_data_shaping_out[17]\, - sample_data_shaping_out_18 => - \sample_data_shaping_out[20]\, sample_data_shaping_out_19 - => \sample_data_shaping_out[21]\, - sample_data_shaping_out_20 => - \sample_data_shaping_out[22]\, sample_data_shaping_out_21 - => \sample_data_shaping_out[23]\, - sample_data_shaping_out_22 => - \sample_data_shaping_out[24]\, sample_data_shaping_out_23 - => \sample_data_shaping_out[25]\, - sample_data_shaping_out_24 => - \sample_data_shaping_out[26]\, sample_data_shaping_out_25 - => \sample_data_shaping_out[27]\, - sample_data_shaping_out_26 => - \sample_data_shaping_out[28]\, sample_data_shaping_out_27 - => \sample_data_shaping_out[29]\, - sample_data_shaping_out_28 => - \sample_data_shaping_out[30]\, sample_data_shaping_out_29 - => \sample_data_shaping_out[31]\, - sample_data_shaping_out_30 => - \sample_data_shaping_out[32]\, sample_data_shaping_out_31 - => \sample_data_shaping_out[33]\, - sample_data_shaping_out_32 => - \sample_data_shaping_out[34]\, sample_data_shaping_out_33 - => \sample_data_shaping_out[35]\, - sample_data_shaping_out_36 => - \sample_data_shaping_out[38]\, sample_data_shaping_out_37 - => \sample_data_shaping_out[39]\, - sample_data_shaping_out_38 => - \sample_data_shaping_out[40]\, sample_data_shaping_out_39 - => \sample_data_shaping_out[41]\, - sample_data_shaping_out_40 => - \sample_data_shaping_out[42]\, sample_data_shaping_out_41 - => \sample_data_shaping_out[43]\, - sample_data_shaping_out_42 => - \sample_data_shaping_out[44]\, sample_data_shaping_out_43 - => \sample_data_shaping_out[45]\, - sample_data_shaping_out_44 => - \sample_data_shaping_out[46]\, sample_data_shaping_out_45 - => \sample_data_shaping_out[47]\, - sample_data_shaping_out_46 => - \sample_data_shaping_out[48]\, sample_data_shaping_out_47 - => \sample_data_shaping_out[49]\, - sample_data_shaping_out_48 => - \sample_data_shaping_out[50]\, sample_data_shaping_out_49 - => \sample_data_shaping_out[51]\, - sample_data_shaping_out_50 => - \sample_data_shaping_out[52]\, sample_data_shaping_out_51 - => \sample_data_shaping_out[53]\, - sample_data_shaping_out_54 => - \sample_data_shaping_out[56]\, sample_data_shaping_out_55 - => \sample_data_shaping_out[57]\, - sample_data_shaping_out_56 => - \sample_data_shaping_out[58]\, sample_data_shaping_out_57 - => \sample_data_shaping_out[59]\, - sample_data_shaping_out_58 => - \sample_data_shaping_out[60]\, sample_data_shaping_out_59 - => \sample_data_shaping_out[61]\, - sample_data_shaping_out_60 => - \sample_data_shaping_out[62]\, sample_data_shaping_out_61 - => \sample_data_shaping_out[63]\, - sample_data_shaping_out_62 => - \sample_data_shaping_out[64]\, sample_data_shaping_out_63 - => \sample_data_shaping_out[65]\, - sample_data_shaping_out_64 => - \sample_data_shaping_out[66]\, sample_data_shaping_out_65 - => \sample_data_shaping_out[67]\, - sample_data_shaping_out_66 => - \sample_data_shaping_out[68]\, sample_data_shaping_out_67 - => \sample_data_shaping_out[69]\, - sample_data_shaping_out_68 => - \sample_data_shaping_out[70]\, sample_data_shaping_out_69 - => \sample_data_shaping_out[71]\, - sample_data_shaping_out_90 => - \sample_data_shaping_out[92]\, sample_data_shaping_out_91 - => \sample_data_shaping_out[93]\, - sample_data_shaping_out_92 => - \sample_data_shaping_out[94]\, sample_data_shaping_out_93 - => \sample_data_shaping_out[95]\, - sample_data_shaping_out_94 => - \sample_data_shaping_out[96]\, sample_data_shaping_out_95 - => \sample_data_shaping_out[97]\, - sample_data_shaping_out_96 => - \sample_data_shaping_out[98]\, sample_data_shaping_out_97 - => \sample_data_shaping_out[99]\, - sample_data_shaping_out_98 => - \sample_data_shaping_out[100]\, - sample_data_shaping_out_99 => - \sample_data_shaping_out[101]\, - sample_data_shaping_out_100 => - \sample_data_shaping_out[102]\, - sample_data_shaping_out_101 => - \sample_data_shaping_out[103]\, - sample_data_shaping_out_102 => - \sample_data_shaping_out[104]\, - sample_data_shaping_out_103 => - \sample_data_shaping_out[105]\, - sample_data_shaping_out_104 => - \sample_data_shaping_out[106]\, - sample_data_shaping_out_105 => - \sample_data_shaping_out[107]\, - sample_data_shaping_out_108 => - \sample_data_shaping_out[110]\, - sample_data_shaping_out_109 => - \sample_data_shaping_out[111]\, - sample_data_shaping_out_110 => - \sample_data_shaping_out[112]\, - sample_data_shaping_out_111 => - \sample_data_shaping_out[113]\, - sample_data_shaping_out_112 => - \sample_data_shaping_out[114]\, - sample_data_shaping_out_113 => - \sample_data_shaping_out[115]\, - sample_data_shaping_out_114 => - \sample_data_shaping_out[116]\, - sample_data_shaping_out_115 => - \sample_data_shaping_out[117]\, - sample_data_shaping_out_116 => - \sample_data_shaping_out[118]\, - sample_data_shaping_out_117 => - \sample_data_shaping_out[119]\, - sample_data_shaping_out_118 => - \sample_data_shaping_out[120]\, - sample_data_shaping_out_119 => - \sample_data_shaping_out[121]\, - sample_data_shaping_out_120 => - \sample_data_shaping_out[122]\, - sample_data_shaping_out_121 => - \sample_data_shaping_out[123]\, - sample_data_shaping_out_122 => - \sample_data_shaping_out[124]\, - sample_data_shaping_out_123 => - \sample_data_shaping_out[125]\, - sample_data_shaping_out_126 => - \sample_data_shaping_out[128]\, - sample_data_shaping_out_127 => - \sample_data_shaping_out[129]\, - sample_data_shaping_out_128 => - \sample_data_shaping_out[130]\, - sample_data_shaping_out_129 => - \sample_data_shaping_out[131]\, - sample_data_shaping_out_130 => - \sample_data_shaping_out[132]\, - sample_data_shaping_out_131 => - \sample_data_shaping_out[133]\, - sample_data_shaping_out_132 => - \sample_data_shaping_out[134]\, - sample_data_shaping_out_133 => - \sample_data_shaping_out[135]\, - sample_data_shaping_out_134 => - \sample_data_shaping_out[136]\, - sample_data_shaping_out_135 => - \sample_data_shaping_out[137]\, - sample_data_shaping_out_136 => - \sample_data_shaping_out[138]\, - sample_data_shaping_out_137 => - \sample_data_shaping_out[139]\, - sample_data_shaping_out_138 => - \sample_data_shaping_out[140]\, - sample_data_shaping_out_139 => - \sample_data_shaping_out[141]\, - sample_data_shaping_out_140 => - \sample_data_shaping_out[142]\, - sample_data_shaping_out_141 => - \sample_data_shaping_out[143]\, sample_f0_wdata_95 => - \sample_f0_wdata[95]\, sample_f0_wdata_94 => - \sample_f0_wdata[94]\, sample_f0_wdata_93 => - \sample_f0_wdata[93]\, sample_f0_wdata_92 => - \sample_f0_wdata[92]\, sample_f0_wdata_91 => - \sample_f0_wdata[91]\, sample_f0_wdata_90 => - \sample_f0_wdata[90]\, sample_f0_wdata_89 => - \sample_f0_wdata[89]\, sample_f0_wdata_88 => - \sample_f0_wdata[88]\, sample_f0_wdata_87 => - \sample_f0_wdata[87]\, sample_f0_wdata_86 => - \sample_f0_wdata[86]\, sample_f0_wdata_85 => - \sample_f0_wdata[85]\, sample_f0_wdata_84 => - \sample_f0_wdata[84]\, sample_f0_wdata_83 => - \sample_f0_wdata[83]\, sample_f0_wdata_82 => - \sample_f0_wdata[82]\, sample_f0_wdata_81 => - \sample_f0_wdata[81]\, sample_f0_wdata_80 => - \sample_f0_wdata[80]\, sample_f0_wdata_79 => - \sample_f0_wdata[79]\, sample_f0_wdata_78 => - \sample_f0_wdata[78]\, sample_f0_wdata_77 => - \sample_f0_wdata[77]\, sample_f0_wdata_76 => - \sample_f0_wdata[76]\, sample_f0_wdata_75 => - \sample_f0_wdata[75]\, sample_f0_wdata_74 => - \sample_f0_wdata[74]\, sample_f0_wdata_73 => - \sample_f0_wdata[73]\, sample_f0_wdata_72 => - \sample_f0_wdata[72]\, sample_f0_wdata_71 => - \sample_f0_wdata[71]\, sample_f0_wdata_70 => - \sample_f0_wdata[70]\, sample_f0_wdata_69 => - \sample_f0_wdata[69]\, sample_f0_wdata_68 => - \sample_f0_wdata[68]\, sample_f0_wdata_67 => - \sample_f0_wdata[67]\, sample_f0_wdata_66 => - \sample_f0_wdata[66]\, sample_f0_wdata_65 => - \sample_f0_wdata[65]\, sample_f0_wdata_64 => - \sample_f0_wdata[64]\, sample_f0_wdata_63 => - \sample_f0_wdata[63]\, sample_f0_wdata_62 => - \sample_f0_wdata[62]\, sample_f0_wdata_61 => - \sample_f0_wdata[61]\, sample_f0_wdata_60 => - \sample_f0_wdata[60]\, sample_f0_wdata_59 => - \sample_f0_wdata[59]\, sample_f0_wdata_58 => - \sample_f0_wdata[58]\, sample_f0_wdata_57 => - \sample_f0_wdata[57]\, sample_f0_wdata_56 => - \sample_f0_wdata[56]\, sample_f0_wdata_55 => - \sample_f0_wdata[55]\, sample_f0_wdata_54 => - \sample_f0_wdata[54]\, sample_f0_wdata_53 => - \sample_f0_wdata[53]\, sample_f0_wdata_52 => - \sample_f0_wdata[52]\, sample_f0_wdata_51 => - \sample_f0_wdata[51]\, sample_f0_wdata_50 => - \sample_f0_wdata[50]\, sample_f0_wdata_49 => - \sample_f0_wdata[49]\, sample_f0_wdata_48 => - \sample_f0_wdata[48]\, sample_f0_wdata_15 => - \sample_f0_wdata[15]\, sample_f0_wdata_14 => - \sample_f0_wdata[14]\, sample_f0_wdata_13 => - \sample_f0_wdata[13]\, sample_f0_wdata_12 => - \sample_f0_wdata[12]\, sample_f0_wdata_11 => - \sample_f0_wdata[11]\, sample_f0_wdata_10 => - \sample_f0_wdata[10]\, sample_f0_wdata_9 => - \sample_f0_wdata[9]\, sample_f0_wdata_8 => - \sample_f0_wdata[8]\, sample_f0_wdata_7 => - \sample_f0_wdata[7]\, sample_f0_wdata_6 => - \sample_f0_wdata[6]\, sample_f0_wdata_5 => - \sample_f0_wdata[5]\, sample_f0_wdata_4 => - \sample_f0_wdata[4]\, sample_f0_wdata_3 => - \sample_f0_wdata[3]\, sample_f0_wdata_2 => - \sample_f0_wdata[2]\, sample_f0_wdata_1 => - \sample_f0_wdata[1]\, sample_f0_wdata_0 => - \sample_f0_wdata[0]\, sample_data_shaping_out_val => - \sample_data_shaping_out_val\, sample_f0_val => - sample_f0_val, sample_data_shaping_out_val_0 => - \sample_data_shaping_out_val_0\, sample_f0_val_0 => - sample_f0_val_0, sample_f0_val_1 => sample_f0_val_1, rstn - => rstn, lclk_c => lclk_c, sample_f0_val_2 => - sample_f0_val_2); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[51]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[51]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[51]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[141]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[141]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[141]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I95_Y_0 : - AX1D - port map(A => I92_un1_Y, B => N182, C => N183_0, Y => - \sample_data_shaping_f1_f0_s[2]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I37_Y : - XA1A - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[133]\, C => N197, Y => N216); - - \SampleLoop_data_shaping.1.sample_data_shaping_out_RNO[106]\ : - MX2 - port map(A => \sample_filter_v2_out[106]\, B => - \sample_data_shaping_f2_f1_s[1]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_41[106]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I49_Y : - AO1B - port map(A => N264_0, B => N216_0, C => - SUB_16x16_medium_area_I49_Y_0, Y => N244); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_0 : - AO18 - port map(A => N206_0, B => \sample_filter_v2_out[129]\, C - => \sample_filter_v2_out[111]\, Y => - SUB_16x16_medium_area_I57_Y_0_0); - - sample_data_shaping_out_val : DFN1C0 - port map(D => sample_filter_v2_out_val, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out_val\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out_RNO[125]\ : - AX1C - port map(A => \sample_filter_v2_out[143]\, B => - data_shaping_SP0, C => \sample_filter_v2_out[125]\, Y => - \sample_data_shaping_out_13[125]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I103_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[97]\, B => - \sample_filter_v2_out[115]\, C => N286_i_0, Y => - \sample_data_shaping_f2_f1_s[10]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I23_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, Y => N194); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[106]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_41[106]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[106]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[118]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_181[118]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[118]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I99_Y_0 : - AX1D - port map(A => I90_un1_Y_0, B => N190, C => N191_0, Y => - \sample_data_shaping_f2_f1_s[6]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[102]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_137[102]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[102]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I71_Y : - AO1 - port map(A => N258_0, B => N255_0, C => N254, Y => N260_0); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I90_un1_Y : - OA1 - port map(A => I85_un1_Y, B => N274_0, C => N189, Y => - I90_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I46_Y : - OR2A - port map(A => \sample_filter_v2_out[125]\, B => - \sample_filter_v2_out[107]\, Y => N225); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[4]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[4]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[4]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[125]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_13[125]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[125]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I99_Y_0 : - AX1D - port map(A => I90_un1_Y, B => N190_0, C => N191, Y => - \sample_data_shaping_f1_f0_s[6]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I29_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[130]\, B => - \sample_filter_v2_out[112]\, Y => N205); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[6]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[6]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[6]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[69]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[69]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[69]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[25]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[25]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[25]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[121]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_109[121]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[121]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[94]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_329[94]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[94]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_1 : - OA1 - port map(A => N212_0, B => N254_0, C => - SUB_16x16_medium_area_I57_Y_0_0, Y => - SUB_16x16_medium_area_I57_Y_1_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I39_Y : - XA1A - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, C => N195_0, Y => N265_0); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[53]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[53]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[53]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_0 : - AO18 - port map(A => N206, B => \sample_filter_v2_out[111]\, C => - \sample_filter_v2_out[93]\, Y => - SUB_16x16_medium_area_I57_Y_0); - - \SampleLoop_data_shaping.1.sample_data_shaping_out_RNO[124]\ : - MX2 - port map(A => \sample_filter_v2_out[124]\, B => - \sample_data_shaping_f1_f0_s[1]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_37[124]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I108_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[110]\, B => - \sample_filter_v2_out[92]\, C => N240_0, Y => - \sample_data_shaping_f2_f1_s[15]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I94_Y_0 : - XOR2 - port map(A => N225, B => N181, Y => - \sample_data_shaping_f2_f1_s[1]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I29_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[112]\, B => - \sample_filter_v2_out[130]\, Y => N206_0); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[99]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_209[99]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[99]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I88_Y : - AO18 - port map(A => N270, B => \sample_filter_v2_out[134]\, C => - \sample_filter_v2_out[116]\, Y => N286_i); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[116]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_229[116]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[116]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I50_Y : - NOR2B - port map(A => N265, B => N216, Y => N245_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I24_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[117]\, B => - \sample_filter_v2_out[99]\, Y => N195_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I18_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[141]\, B => - \sample_filter_v2_out[123]\, Y => N183_0); - - \SampleLoop_data_shaping.6.sample_data_shaping_out_RNO[119]\ : - MX2 - port map(A => \sample_filter_v2_out[119]\, B => - \sample_data_shaping_f1_f0_s[6]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_157[119]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[139]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[139]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[139]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[70]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[70]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[70]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I27_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[114]\, B => - \sample_filter_v2_out[96]\, Y => N201_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[8]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[8]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[8]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[112]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_325[112]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[112]\); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[98]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_233[98]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[98]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[128]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[128]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[128]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y_0 : - AO18 - port map(A => N190, B => \sample_filter_v2_out[119]\, C => - \sample_filter_v2_out[101]\, Y => - SUB_16x16_medium_area_I56_Y_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[134]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[134]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[134]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I25_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[116]\, B => - \sample_filter_v2_out[98]\, Y => N197_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I29_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[112]\, B => - \sample_filter_v2_out[94]\, Y => N205_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I64_Y : - AO1 - port map(A => N268, B => N245_0, C => N244_0, Y => N258); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y : - AO1B - port map(A => SUB_16x16_medium_area_I57_un1_Y_0_0, B => - N268, C => SUB_16x16_medium_area_I57_Y_2_0, Y => N240); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[59]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[59]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[59]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I34_Y : - AO13 - port map(A => N202_0, B => \sample_filter_v2_out[95]\, C - => \sample_filter_v2_out[113]\, Y => N254); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[10]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[10]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[10]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I96_Y_0 : - XOR2 - port map(A => N278, B => N185, Y => - \sample_data_shaping_f1_f0_s[3]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I21_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[120]\, B => - \sample_filter_v2_out[138]\, Y => N190_0); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[40]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[40]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[40]\); - - Downsampling_f1 : Downsampling_8_16_6 - port map(sample_f0_0 => \sample_f0[48]\, sample_f0_1 => - \sample_f0[49]\, sample_f0_2 => \sample_f0[50]\, - sample_f0_3 => \sample_f0[51]\, sample_f0_4 => - \sample_f0[52]\, sample_f0_5 => \sample_f0[53]\, - sample_f0_6 => \sample_f0[54]\, sample_f0_7 => - \sample_f0[55]\, sample_f0_8 => \sample_f0[56]\, - sample_f0_9 => \sample_f0[57]\, sample_f0_10 => - \sample_f0[58]\, sample_f0_11 => \sample_f0[59]\, - sample_f0_12 => \sample_f0[60]\, sample_f0_13 => - \sample_f0[61]\, sample_f0_14 => \sample_f0[62]\, - sample_f0_15 => \sample_f0[63]\, sample_f0_32 => - \sample_f0[80]\, sample_f0_33 => \sample_f0[81]\, - sample_f0_34 => \sample_f0[82]\, sample_f0_35 => - \sample_f0[83]\, sample_f0_36 => \sample_f0[84]\, - sample_f0_37 => \sample_f0[85]\, sample_f0_38 => - \sample_f0[86]\, sample_f0_39 => \sample_f0[87]\, - sample_f0_40 => \sample_f0[88]\, sample_f0_41 => - \sample_f0[89]\, sample_f0_42 => \sample_f0[90]\, - sample_f0_43 => \sample_f0[91]\, sample_f0_44 => - \sample_f0[92]\, sample_f0_45 => \sample_f0[93]\, - sample_f0_46 => \sample_f0[94]\, sample_f0_47 => - \sample_f0[95]\, sample_f0_48 => \sample_f0[96]\, - sample_f0_49 => \sample_f0[97]\, sample_f0_50 => - \sample_f0[98]\, sample_f0_51 => \sample_f0[99]\, - sample_f0_52 => \sample_f0[100]\, sample_f0_53 => - \sample_f0[101]\, sample_f0_54 => \sample_f0[102]\, - sample_f0_55 => \sample_f0[103]\, sample_f0_56 => - \sample_f0[104]\, sample_f0_57 => \sample_f0[105]\, - sample_f0_58 => \sample_f0[106]\, sample_f0_59 => - \sample_f0[107]\, sample_f0_60 => \sample_f0[108]\, - sample_f0_61 => \sample_f0[109]\, sample_f0_62 => - \sample_f0[110]\, sample_f0_63 => \sample_f0[111]\, - sample_f1_0 => \sample_f1[48]\, sample_f1_1 => - \sample_f1[49]\, sample_f1_2 => \sample_f1[50]\, - sample_f1_3 => \sample_f1[51]\, sample_f1_4 => - \sample_f1[52]\, sample_f1_5 => \sample_f1[53]\, - sample_f1_6 => \sample_f1[54]\, sample_f1_7 => - \sample_f1[55]\, sample_f1_8 => \sample_f1[56]\, - sample_f1_9 => \sample_f1[57]\, sample_f1_10 => - \sample_f1[58]\, sample_f1_11 => \sample_f1[59]\, - sample_f1_12 => \sample_f1[60]\, sample_f1_13 => - \sample_f1[61]\, sample_f1_14 => \sample_f1[62]\, - sample_f1_15 => \sample_f1[63]\, sample_f1_32 => - \sample_f1[80]\, sample_f1_33 => \sample_f1[81]\, - sample_f1_34 => \sample_f1[82]\, sample_f1_35 => - \sample_f1[83]\, sample_f1_36 => \sample_f1[84]\, - sample_f1_37 => \sample_f1[85]\, sample_f1_38 => - \sample_f1[86]\, sample_f1_39 => \sample_f1[87]\, - sample_f1_40 => \sample_f1[88]\, sample_f1_41 => - \sample_f1[89]\, sample_f1_42 => \sample_f1[90]\, - sample_f1_43 => \sample_f1[91]\, sample_f1_44 => - \sample_f1[92]\, sample_f1_45 => \sample_f1[93]\, - sample_f1_46 => \sample_f1[94]\, sample_f1_47 => - \sample_f1[95]\, sample_f1_48 => \sample_f1[96]\, - sample_f1_49 => \sample_f1[97]\, sample_f1_50 => - \sample_f1[98]\, sample_f1_51 => \sample_f1[99]\, - sample_f1_52 => \sample_f1[100]\, sample_f1_53 => - \sample_f1[101]\, sample_f1_54 => \sample_f1[102]\, - sample_f1_55 => \sample_f1[103]\, sample_f1_56 => - \sample_f1[104]\, sample_f1_57 => \sample_f1[105]\, - sample_f1_58 => \sample_f1[106]\, sample_f1_59 => - \sample_f1[107]\, sample_f1_60 => \sample_f1[108]\, - sample_f1_61 => \sample_f1[109]\, sample_f1_62 => - \sample_f1[110]\, sample_f1_63 => \sample_f1[111]\, - sample_f0_wdata_95 => \sample_f0_wdata[95]\, - sample_f0_wdata_94 => \sample_f0_wdata[94]\, - sample_f0_wdata_93 => \sample_f0_wdata[93]\, - sample_f0_wdata_92 => \sample_f0_wdata[92]\, - sample_f0_wdata_91 => \sample_f0_wdata[91]\, - sample_f0_wdata_90 => \sample_f0_wdata[90]\, - sample_f0_wdata_89 => \sample_f0_wdata[89]\, - sample_f0_wdata_88 => \sample_f0_wdata[88]\, - sample_f0_wdata_87 => \sample_f0_wdata[87]\, - sample_f0_wdata_86 => \sample_f0_wdata[86]\, - sample_f0_wdata_85 => \sample_f0_wdata[85]\, - sample_f0_wdata_84 => \sample_f0_wdata[84]\, - sample_f0_wdata_83 => \sample_f0_wdata[83]\, - sample_f0_wdata_82 => \sample_f0_wdata[82]\, - sample_f0_wdata_81 => \sample_f0_wdata[81]\, - sample_f0_wdata_80 => \sample_f0_wdata[80]\, - sample_f0_wdata_79 => \sample_f0_wdata[79]\, - sample_f0_wdata_78 => \sample_f0_wdata[78]\, - sample_f0_wdata_77 => \sample_f0_wdata[77]\, - sample_f0_wdata_76 => \sample_f0_wdata[76]\, - sample_f0_wdata_75 => \sample_f0_wdata[75]\, - sample_f0_wdata_74 => \sample_f0_wdata[74]\, - sample_f0_wdata_73 => \sample_f0_wdata[73]\, - sample_f0_wdata_72 => \sample_f0_wdata[72]\, - sample_f0_wdata_71 => \sample_f0_wdata[71]\, - sample_f0_wdata_70 => \sample_f0_wdata[70]\, - sample_f0_wdata_69 => \sample_f0_wdata[69]\, - sample_f0_wdata_68 => \sample_f0_wdata[68]\, - sample_f0_wdata_67 => \sample_f0_wdata[67]\, - sample_f0_wdata_66 => \sample_f0_wdata[66]\, - sample_f0_wdata_65 => \sample_f0_wdata[65]\, - sample_f0_wdata_64 => \sample_f0_wdata[64]\, - sample_f0_wdata_63 => \sample_f0_wdata[63]\, - sample_f0_wdata_62 => \sample_f0_wdata[62]\, - sample_f0_wdata_61 => \sample_f0_wdata[61]\, - sample_f0_wdata_60 => \sample_f0_wdata[60]\, - sample_f0_wdata_59 => \sample_f0_wdata[59]\, - sample_f0_wdata_58 => \sample_f0_wdata[58]\, - sample_f0_wdata_57 => \sample_f0_wdata[57]\, - sample_f0_wdata_56 => \sample_f0_wdata[56]\, - sample_f0_wdata_55 => \sample_f0_wdata[55]\, - sample_f0_wdata_54 => \sample_f0_wdata[54]\, - sample_f0_wdata_53 => \sample_f0_wdata[53]\, - sample_f0_wdata_52 => \sample_f0_wdata[52]\, - sample_f0_wdata_51 => \sample_f0_wdata[51]\, - sample_f0_wdata_50 => \sample_f0_wdata[50]\, - sample_f0_wdata_49 => \sample_f0_wdata[49]\, - sample_f0_wdata_48 => \sample_f0_wdata[48]\, - sample_f0_wdata_15 => \sample_f0_wdata[15]\, - sample_f0_wdata_14 => \sample_f0_wdata[14]\, - sample_f0_wdata_13 => \sample_f0_wdata[13]\, - sample_f0_wdata_12 => \sample_f0_wdata[12]\, - sample_f0_wdata_11 => \sample_f0_wdata[11]\, - sample_f0_wdata_10 => \sample_f0_wdata[10]\, - sample_f0_wdata_9 => \sample_f0_wdata[9]\, - sample_f0_wdata_8 => \sample_f0_wdata[8]\, - sample_f0_wdata_7 => \sample_f0_wdata[7]\, - sample_f0_wdata_6 => \sample_f0_wdata[6]\, - sample_f0_wdata_5 => \sample_f0_wdata[5]\, - sample_f0_wdata_4 => \sample_f0_wdata[4]\, - sample_f0_wdata_3 => \sample_f0_wdata[3]\, - sample_f0_wdata_2 => \sample_f0_wdata[2]\, - sample_f0_wdata_1 => \sample_f0_wdata[1]\, - sample_f0_wdata_0 => \sample_f0_wdata[0]\, - sample_f1_wdata_95 => \sample_f1_wdata[95]\, - sample_f1_wdata_94 => \sample_f1_wdata[94]\, - sample_f1_wdata_93 => \sample_f1_wdata[93]\, - sample_f1_wdata_92 => \sample_f1_wdata[92]\, - sample_f1_wdata_91 => \sample_f1_wdata[91]\, - sample_f1_wdata_90 => \sample_f1_wdata[90]\, - sample_f1_wdata_89 => \sample_f1_wdata[89]\, - sample_f1_wdata_88 => \sample_f1_wdata[88]\, - sample_f1_wdata_87 => \sample_f1_wdata[87]\, - sample_f1_wdata_86 => \sample_f1_wdata[86]\, - sample_f1_wdata_85 => \sample_f1_wdata[85]\, - sample_f1_wdata_84 => \sample_f1_wdata[84]\, - sample_f1_wdata_83 => \sample_f1_wdata[83]\, - sample_f1_wdata_82 => \sample_f1_wdata[82]\, - sample_f1_wdata_81 => \sample_f1_wdata[81]\, - sample_f1_wdata_80 => \sample_f1_wdata[80]\, - sample_f1_wdata_79 => \sample_f1_wdata[79]\, - sample_f1_wdata_78 => \sample_f1_wdata[78]\, - sample_f1_wdata_77 => \sample_f1_wdata[77]\, - sample_f1_wdata_76 => \sample_f1_wdata[76]\, - sample_f1_wdata_75 => \sample_f1_wdata[75]\, - sample_f1_wdata_74 => \sample_f1_wdata[74]\, - sample_f1_wdata_73 => \sample_f1_wdata[73]\, - sample_f1_wdata_72 => \sample_f1_wdata[72]\, - sample_f1_wdata_71 => \sample_f1_wdata[71]\, - sample_f1_wdata_70 => \sample_f1_wdata[70]\, - sample_f1_wdata_69 => \sample_f1_wdata[69]\, - sample_f1_wdata_68 => \sample_f1_wdata[68]\, - sample_f1_wdata_67 => \sample_f1_wdata[67]\, - sample_f1_wdata_66 => \sample_f1_wdata[66]\, - sample_f1_wdata_65 => \sample_f1_wdata[65]\, - sample_f1_wdata_64 => \sample_f1_wdata[64]\, - sample_f1_wdata_63 => \sample_f1_wdata[63]\, - sample_f1_wdata_62 => \sample_f1_wdata[62]\, - sample_f1_wdata_61 => \sample_f1_wdata[61]\, - sample_f1_wdata_60 => \sample_f1_wdata[60]\, - sample_f1_wdata_59 => \sample_f1_wdata[59]\, - sample_f1_wdata_58 => \sample_f1_wdata[58]\, - sample_f1_wdata_57 => \sample_f1_wdata[57]\, - sample_f1_wdata_56 => \sample_f1_wdata[56]\, - sample_f1_wdata_55 => \sample_f1_wdata[55]\, - sample_f1_wdata_54 => \sample_f1_wdata[54]\, - sample_f1_wdata_53 => \sample_f1_wdata[53]\, - sample_f1_wdata_52 => \sample_f1_wdata[52]\, - sample_f1_wdata_51 => \sample_f1_wdata[51]\, - sample_f1_wdata_50 => \sample_f1_wdata[50]\, - sample_f1_wdata_49 => \sample_f1_wdata[49]\, - sample_f1_wdata_48 => \sample_f1_wdata[48]\, - sample_f1_wdata_15 => \sample_f1_wdata[15]\, - sample_f1_wdata_14 => \sample_f1_wdata[14]\, - sample_f1_wdata_13 => \sample_f1_wdata[13]\, - sample_f1_wdata_12 => \sample_f1_wdata[12]\, - sample_f1_wdata_11 => \sample_f1_wdata[11]\, - sample_f1_wdata_10 => \sample_f1_wdata[10]\, - sample_f1_wdata_9 => \sample_f1_wdata[9]\, - sample_f1_wdata_8 => \sample_f1_wdata[8]\, - sample_f1_wdata_7 => \sample_f1_wdata[7]\, - sample_f1_wdata_6 => \sample_f1_wdata[6]\, - sample_f1_wdata_5 => \sample_f1_wdata[5]\, - sample_f1_wdata_4 => \sample_f1_wdata[4]\, - sample_f1_wdata_3 => \sample_f1_wdata[3]\, - sample_f1_wdata_2 => \sample_f1_wdata[2]\, - sample_f1_wdata_1 => \sample_f1_wdata[1]\, - sample_f1_wdata_0 => \sample_f1_wdata[0]\, - sample_f0_val_2 => sample_f0_val_2, sample_f0_val_1 => - sample_f0_val_1, sample_f1_val => sample_f1_val, - sample_f0_val_0 => sample_f0_val_0, rstn => rstn, lclk_c - => lclk_c, sample_f1_val_0 => sample_f1_val_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I87_Y : - AO18 - port map(A => N258_0, B => \sample_filter_v2_out[114]\, C - => \sample_filter_v2_out[96]\, Y => N284_i_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out_RNO[100]\ : - MX2 - port map(A => \sample_filter_v2_out[100]\, B => - \sample_data_shaping_f2_f1_s[7]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_185[100]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I49_Y : - AO1B - port map(A => N264, B => N216, C => - SUB_16x16_medium_area_I49_Y_0_0, Y => N244_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I41_Y : - NOR2B - port map(A => N191_0, B => N189_0, Y => N220); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y : - AO1B - port map(A => SUB_16x16_medium_area_I57_un1_Y_0, B => - N268_0, C => SUB_16x16_medium_area_I57_Y_2, Y => N240_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I17_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[142]\, B => - \sample_filter_v2_out[124]\, Y => N181_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out_RNO[98]\ : - MX2 - port map(A => \sample_filter_v2_out[98]\, B => - \sample_data_shaping_f2_f1_s[9]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_233[98]\); - - sample_data_shaping_out_val_0 : DFN1C0 - port map(D => sample_filter_v2_out_val, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out_val_0\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I38_Y : - AO13 - port map(A => N194, B => \sample_filter_v2_out[117]\, C => - \sample_filter_v2_out[135]\, Y => N264); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[41]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[41]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[41]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[140]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[140]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[140]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out_RNO[105]\ : - MX2 - port map(A => \sample_filter_v2_out[105]\, B => - \sample_data_shaping_f2_f1_s[2]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_65[105]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_1 : - AOI1B - port map(A => N254, B => N212, C => - SUB_16x16_medium_area_I57_Y_0, Y => - SUB_16x16_medium_area_I57_Y_1); - - \SampleLoop_data_shaping.5.sample_data_shaping_out_RNO[102]\ : - MX2 - port map(A => \sample_filter_v2_out[102]\, B => - \sample_data_shaping_f2_f1_s[5]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_137[102]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I57_Y_2 : - AOI1B - port map(A => N244_0, B => N229_0, C => - SUB_16x16_medium_area_I57_Y_1_0, Y => - SUB_16x16_medium_area_I57_Y_2_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[39]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[39]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[39]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[130]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[130]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[130]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I97_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I91_un1_Y_0, B => - N186_0, C => N187_0, Y => - \sample_data_shaping_f2_f1_s[4]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I21_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[120]\, B => - \sample_filter_v2_out[102]\, Y => N189_0); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[63]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[63]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[63]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[101]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_161[101]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[101]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I106_Y_0 : - XOR2 - port map(A => N260, B => N205, Y => - \sample_data_shaping_f1_f0_s[13]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[45]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[45]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[45]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[123]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_61[123]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[123]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[24]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[24]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[24]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out_RNO[122]\ : - MX2 - port map(A => \sample_filter_v2_out[122]\, B => - \sample_data_shaping_f1_f0_s[3]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_85[122]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[115]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_253[115]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[115]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[43]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[43]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[43]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[60]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[60]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[60]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I42_Y : - AO13 - port map(A => N186, B => \sample_filter_v2_out[121]\, C => - \sample_filter_v2_out[139]\, Y => N274_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[64]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[64]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[64]\); - - sample_val_delay_3 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_3\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I88_Y : - AO18 - port map(A => N270_0, B => \sample_filter_v2_out[116]\, C - => \sample_filter_v2_out[98]\, Y => N286_i_0); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[133]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[133]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[133]\); - - GND_i_0 : GND - port map(Y => GND_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I57_Y_2 : - AOI1B - port map(A => N244, B => N229, C => - SUB_16x16_medium_area_I57_Y_1, Y => - SUB_16x16_medium_area_I57_Y_2); - - \SampleLoop_data_shaping.4.sample_data_shaping_out_RNO[121]\ : - MX2 - port map(A => \sample_filter_v2_out[121]\, B => - \sample_data_shaping_f1_f0_s[4]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_109[121]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[142]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[142]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[142]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I96_Y_0 : - XOR2 - port map(A => N278_0, B => N185_0, Y => - \sample_data_shaping_f2_f1_s[3]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_un1_Y : - OR3C - port map(A => N225_0, B => N183_0, C => N181_0, Y => - I53_un1_Y_0); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[14]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[14]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[14]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out_RNO[99]\ : - MX2 - port map(A => \sample_filter_v2_out[99]\, B => - \sample_data_shaping_f2_f1_s[8]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_209[99]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I101_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I89_un1_Y_0, B => - N194_0, C => N195_0, Y => - \sample_data_shaping_f2_f1_s[8]\); - - \SampleLoop_data_shaping.7.sample_data_shaping_out_RNO[118]\ : - MX2 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_data_shaping_f1_f0_s[7]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_181[118]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I103_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[115]\, B => - \sample_filter_v2_out[133]\, C => N286_i, Y => - \sample_data_shaping_f1_f0_s[10]\); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[93]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_353[93]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[93]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I92_un1_Y : - NOR2B - port map(A => N225_0, B => N181_0, Y => I92_un1_Y); - - sample_val_delay_1 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_1\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out_RNO[117]\ : - MX2 - port map(A => \sample_filter_v2_out[117]\, B => - \sample_data_shaping_f1_f0_s[8]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_205[117]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out_RNO[112]\ : - MX2 - port map(A => \sample_filter_v2_out[112]\, B => - \sample_data_shaping_f1_f0_s[13]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_325[112]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I53_Y_0 : - AO18 - port map(A => N182_0, B => \sample_filter_v2_out[123]\, C - => \sample_filter_v2_out[105]\, Y => - SUB_16x16_medium_area_I53_Y_0_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[114]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_277[114]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[114]\); - - DIGITAL_acquisition : AD7688_drvr - port map(sample_4(15) => \sample_4[15]\, sample_4(14) => - \sample_4[14]\, sample_4(13) => \sample_4[13]\, - sample_4(12) => \sample_4[12]\, sample_4(11) => - \sample_4[11]\, sample_4(10) => \sample_4[10]\, - sample_4(9) => \sample_4[9]\, sample_4(8) => - \sample_4[8]\, sample_4(7) => \sample_4[7]\, sample_4(6) - => \sample_4[6]\, sample_4(5) => \sample_4[5]\, - sample_4(4) => \sample_4[4]\, sample_4(3) => - \sample_4[3]\, sample_4(2) => \sample_4[2]\, sample_4(1) - => \sample_4[1]\, sample_4(0) => \sample_4[0]\, - sample_5(15) => \sample_5[15]\, sample_5(14) => - \sample_5[14]\, sample_5(13) => \sample_5[13]\, - sample_5(12) => \sample_5[12]\, sample_5(11) => - \sample_5[11]\, sample_5(10) => \sample_5[10]\, - sample_5(9) => \sample_5[9]\, sample_5(8) => - \sample_5[8]\, sample_5(7) => \sample_5[7]\, sample_5(6) - => \sample_5[6]\, sample_5(5) => \sample_5[5]\, - sample_5(4) => \sample_5[4]\, sample_5(3) => - \sample_5[3]\, sample_5(2) => \sample_5[2]\, sample_5(1) - => \sample_5[1]\, sample_5(0) => \sample_5[0]\, - sample_6(15) => \sample_6[15]\, sample_6(14) => - \sample_6[14]\, sample_6(13) => \sample_6[13]\, - sample_6(12) => \sample_6[12]\, sample_6(11) => - \sample_6[11]\, sample_6(10) => \sample_6[10]\, - sample_6(9) => \sample_6[9]\, sample_6(8) => - \sample_6[8]\, sample_6(7) => \sample_6[7]\, sample_6(6) - => \sample_6[6]\, sample_6(5) => \sample_6[5]\, - sample_6(4) => \sample_6[4]\, sample_6(3) => - \sample_6[3]\, sample_6(2) => \sample_6[2]\, sample_6(1) - => \sample_6[1]\, sample_6(0) => \sample_6[0]\, - sample_7(15) => \sample_7[15]\, sample_7(14) => - \sample_7[14]\, sample_7(13) => \sample_7[13]\, - sample_7(12) => \sample_7[12]\, sample_7(11) => - \sample_7[11]\, sample_7(10) => \sample_7[10]\, - sample_7(9) => \sample_7[9]\, sample_7(8) => - \sample_7[8]\, sample_7(7) => \sample_7[7]\, sample_7(6) - => \sample_7[6]\, sample_7(5) => \sample_7[5]\, - sample_7(4) => \sample_7[4]\, sample_7(3) => - \sample_7[3]\, sample_7(2) => \sample_7[2]\, sample_7(1) - => \sample_7[1]\, sample_7(0) => \sample_7[0]\, - sample_0(15) => \sample_0[15]\, sample_0(14) => - \sample_0[14]\, sample_0(13) => \sample_0[13]\, - sample_0(12) => \sample_0[12]\, sample_0(11) => - \sample_0[11]\, sample_0(10) => \sample_0[10]\, - sample_0(9) => \sample_0[9]\, sample_0(8) => - \sample_0[8]\, sample_0(7) => \sample_0[7]\, sample_0(6) - => \sample_0[6]\, sample_0(5) => \sample_0[5]\, - sample_0(4) => \sample_0[4]\, sample_0(3) => - \sample_0[3]\, sample_0(2) => \sample_0[2]\, sample_0(1) - => \sample_0[1]\, sample_0(0) => \sample_0[0]\, - sample_1(15) => \sample_1[15]\, sample_1(14) => - \sample_1[14]\, sample_1(13) => \sample_1[13]\, - sample_1(12) => \sample_1[12]\, sample_1(11) => - \sample_1[11]\, sample_1(10) => \sample_1[10]\, - sample_1(9) => \sample_1[9]\, sample_1(8) => - \sample_1[8]\, sample_1(7) => \sample_1[7]\, sample_1(6) - => \sample_1[6]\, sample_1(5) => \sample_1[5]\, - sample_1(4) => \sample_1[4]\, sample_1(3) => - \sample_1[3]\, sample_1(2) => \sample_1[2]\, sample_1(1) - => \sample_1[1]\, sample_1(0) => \sample_1[0]\, - sample_2(15) => \sample_2[15]\, sample_2(14) => - \sample_2[14]\, sample_2(13) => \sample_2[13]\, - sample_2(12) => \sample_2[12]\, sample_2(11) => - \sample_2[11]\, sample_2(10) => \sample_2[10]\, - sample_2(9) => \sample_2[9]\, sample_2(8) => - \sample_2[8]\, sample_2(7) => \sample_2[7]\, sample_2(6) - => \sample_2[6]\, sample_2(5) => \sample_2[5]\, - sample_2(4) => \sample_2[4]\, sample_2(3) => - \sample_2[3]\, sample_2(2) => \sample_2[2]\, sample_2(1) - => \sample_2[1]\, sample_2(0) => \sample_2[0]\, - sdo_adc_c(7) => sdo_adc_c(7), sdo_adc_c(6) => - sdo_adc_c(6), sdo_adc_c(5) => sdo_adc_c(5), sdo_adc_c(4) - => sdo_adc_c(4), sdo_adc_c(3) => sdo_adc_c(3), - sdo_adc_c(2) => sdo_adc_c(2), sdo_adc_c(1) => - sdo_adc_c(1), sdo_adc_c(0) => sdo_adc_c(0), sample_3(15) - => \sample_3[15]\, sample_3(14) => \sample_3[14]\, - sample_3(13) => \sample_3[13]\, sample_3(12) => - \sample_3[12]\, sample_3(11) => \sample_3[11]\, - sample_3(10) => \sample_3[10]\, sample_3(9) => - \sample_3[9]\, sample_3(8) => \sample_3[8]\, sample_3(7) - => \sample_3[7]\, sample_3(6) => \sample_3[6]\, - sample_3(5) => \sample_3[5]\, sample_3(4) => - \sample_3[4]\, sample_3(3) => \sample_3[3]\, sample_3(2) - => \sample_3[2]\, sample_3(1) => \sample_3[1]\, - sample_3(0) => \sample_3[0]\, AD7688_drvr_VCC => - lpp_top_lfr_wf_picker_ip_VCC, clk49_152MHz_c => - clk49_152MHz_c, cnv_ch1_c => cnv_ch1_c, sample_val => - sample_val, sck_ch1_c => sck_ch1_c, rstn => rstn, lclk_c - => lclk_c); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I64_Y : - AO1 - port map(A => N268_0, B => N245, C => N244, Y => N258_0); - - \SampleLoop_data_shaping.10.sample_data_shaping_out_RNO[97]\ : - MX2 - port map(A => \sample_filter_v2_out[97]\, B => - \sample_data_shaping_f2_f1_s[10]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_257[97]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I85_un1_Y : - NOR2B - port map(A => N278_0, B => N275, Y => I85_un1_Y_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[96]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_281[96]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[96]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I20_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[139]\, B => - \sample_filter_v2_out[121]\, Y => N187); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I19_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[122]\, B => - \sample_filter_v2_out[140]\, Y => N186); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I18_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[123]\, B => - \sample_filter_v2_out[105]\, Y => N183); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[62]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[62]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[62]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I43_Y : - NOR2B - port map(A => N187_0, B => N185_0, Y => N275); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I48_Y : - NOR2 - port map(A => N255, B => N212_0, Y => N229_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I35_Y : - XAI1A - port map(A => \sample_filter_v2_out[113]\, B => - \sample_filter_v2_out[131]\, C => N201, Y => N255); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I41_Y : - NOR2B - port map(A => N191, B => N189, Y => N220_0); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[42]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[42]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[42]\); - - \SampleLoop_data_shaping.0.sample_data_shaping_out[71]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[71]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[71]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I27_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[132]\, B => - \sample_filter_v2_out[114]\, Y => N201); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I17_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[106]\, B => - \sample_filter_v2_out[124]\, Y => N182_0); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[52]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[52]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[52]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[34]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[34]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[34]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I22_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[119]\, B => - \sample_filter_v2_out[101]\, Y => N191_0); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I25_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[98]\, B => - \sample_filter_v2_out[116]\, Y => N198); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I25_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[116]\, B => - \sample_filter_v2_out[134]\, Y => N198_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I27_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[114]\, B => - \sample_filter_v2_out[132]\, Y => N202); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[111]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_349[111]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[111]\); - - \SampleLoop_data_shaping.8.sample_data_shaping_out[9]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[9]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[9]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I105_Y_0 : - XOR3 - port map(A => \sample_filter_v2_out[95]\, B => - \sample_filter_v2_out[113]\, C => N284_i_0, Y => - \sample_data_shaping_f2_f1_s[12]\); - - \SampleLoop_data_shaping.10.sample_data_shaping_out[7]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[7]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[7]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[48]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[48]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[48]\); - - \SampleLoop_data_shaping.11.sample_data_shaping_out[132]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[132]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[132]\); - - \SampleLoop_data_shaping.4.sample_data_shaping_out[31]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[31]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[31]\); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[16]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[16]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[16]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I33_Y : - XA1A - port map(A => \sample_filter_v2_out[93]\, B => - \sample_filter_v2_out[111]\, C => N205_0, Y => N212); - - \SampleLoop_data_shaping.11.sample_data_shaping_out_RNO[114]\ : - MX2 - port map(A => \sample_filter_v2_out[114]\, B => - \sample_data_shaping_f1_f0_s[11]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_277[114]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out_RNO[113]\ : - MX2 - port map(A => \sample_filter_v2_out[113]\, B => - \sample_data_shaping_f1_f0_s[12]\, S => data_shaping_SP0, - Y => \sample_data_shaping_out_301[113]\); - - \SampleLoop_data_shaping.3.sample_data_shaping_out[50]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[50]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[50]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out_RNO[94]\ : - MX2 - port map(A => \sample_filter_v2_out[94]\, B => - \sample_data_shaping_f2_f1_s[13]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_329[94]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[2]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[2]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[2]\); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[66]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[66]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[66]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I86_Y : - AO18 - port map(A => N260_0, B => \sample_filter_v2_out[112]\, C - => \sample_filter_v2_out[94]\, Y => N282_i_0); - - \SampleLoop_data_shaping.1.sample_data_shaping_out[124]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_37[124]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[124]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I19_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[104]\, B => - \sample_filter_v2_out[122]\, Y => N186_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I25_S_0 : - XNOR2 - port map(A => \sample_filter_v2_out[134]\, B => - \sample_filter_v2_out[116]\, Y => N197); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I89_un1_Y : - XA1A - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N268, Y => - SUB_16x16_medium_area_I89_un1_Y); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y : - AO1B - port map(A => SUB_16x16_medium_area_I56_un1_Y_0, B => - N278_0, C => SUB_16x16_medium_area_I56_Y_1, Y => N268_0); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[5]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[5]\, CLK => lclk_c, CLR - => rstn, Q => \sample_data_shaping_out[5]\); - - \SampleLoop_data_shaping.2.sample_data_shaping_out[105]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_65[105]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[105]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I104_Y_0 : - XOR2 - port map(A => N258_0, B => N201_0, Y => - \sample_data_shaping_f2_f1_s[11]\); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[92]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_377[92]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[92]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I89_un1_Y : - XA1A - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, C => N268_0, Y => - SUB_16x16_medium_area_I89_un1_Y_0); - - \SampleLoop_data_shaping.9.sample_data_shaping_out[44]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[44]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[44]\); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_Y_0 : - AO18 - port map(A => N190_0, B => \sample_filter_v2_out[137]\, C - => \sample_filter_v2_out[119]\, Y => - SUB_16x16_medium_area_I56_Y_0_0); - - \SampleLoop_data_shaping.14.sample_data_shaping_out[21]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[21]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[21]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I35_Y : - XA1A - port map(A => \sample_filter_v2_out[95]\, B => - \sample_filter_v2_out[113]\, C => N201_0, Y => N255_0); - - \SampleLoop_data_shaping.15.sample_data_shaping_out[38]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[38]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[38]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_Y_1 : - AOI1B - port map(A => N274, B => N220, C => - SUB_16x16_medium_area_I56_Y_0, Y => - SUB_16x16_medium_area_I56_Y_1); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I50_Y : - NOR2B - port map(A => N265_0, B => N216_0, Y => N245); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I56_un1_Y_0 : - NOR2B - port map(A => N220_0, B => N275_0, Y => - SUB_16x16_medium_area_I56_un1_Y_0_0); - - \SampleLoop_data_shaping.7.sample_data_shaping_out[100]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_185[100]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[100]\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I98_Y_0 : - AX1D - port map(A => I85_un1_Y_0, B => N274, C => N189_0, Y => - \sample_data_shaping_f2_f1_s[5]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[95]\ : - DFN1C0 - port map(D => \sample_data_shaping_out_305[95]\, CLK => - lclk_c, CLR => rstn, Q => \sample_data_shaping_out[95]\); - - \SampleLoop_data_shaping.6.sample_data_shaping_out[65]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[65]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[65]\); - - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I56_un1_Y_0 : - NOR2B - port map(A => N220, B => N275, Y => - SUB_16x16_medium_area_I56_un1_Y_0); - - \SampleLoop_data_shaping.15.sample_data_shaping_out_RNO[92]\ : - MX2 - port map(A => \sample_filter_v2_out[92]\, B => - \sample_data_shaping_f2_f1_s[15]\, S => data_shaping_SP1, - Y => \sample_data_shaping_out_377[92]\); - - \SampleLoop_data_shaping.12.sample_data_shaping_out[131]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[131]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[131]\); - - \SampleLoop_data_shaping.13.sample_data_shaping_out[22]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[22]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[22]\); - - sample_val_delay_5 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_5\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I91_un1_Y : - NOR2B - port map(A => N278, B => N185, Y => - SUB_16x16_medium_area_I91_un1_Y); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I53_Y_0 : - AO18 - port map(A => N182, B => \sample_filter_v2_out[141]\, C => - \sample_filter_v2_out[123]\, Y => - SUB_16x16_medium_area_I53_Y_0); - - \SampleLoop_data_shaping.5.sample_data_shaping_out[12]\ : - DFN1C0 - port map(D => \sample_filter_v2_out[12]\, CLK => lclk_c, - CLR => rstn, Q => \sample_data_shaping_out[12]\); - - sample_val_delay_2 : DFN1C0 - port map(D => sample_val, CLK => lclk_c, CLR => rstn, Q => - \sample_val_delay_2\); - - sample_data_shaping_f2_f1_s_0_0_SUB_16x16_medium_area_I23_CO1 : - NOR2A - port map(A => \sample_filter_v2_out[100]\, B => - \sample_filter_v2_out[118]\, Y => N194_0); - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I97_Y_0 : - AX1D - port map(A => SUB_16x16_medium_area_I91_un1_Y, B => N186, C - => N187, Y => \sample_data_shaping_f1_f0_s[4]\); - - - sample_data_shaping_f1_f0_s_0_0_SUB_16x16_medium_area_I100_Y_0 : - XNOR3 - port map(A => \sample_filter_v2_out[118]\, B => - \sample_filter_v2_out[136]\, C => N268, Y => - \sample_data_shaping_f1_f0_s[7]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lpp_top_lfr_wf_picker is - - port( sdo_adc_c : in std_logic_vector(7 downto 0); - hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93); - hresp : in std_logic_vector(0 to 0); - iosn_1 : in std_logic_vector(93 to 93); - nhmaster_1_i : in std_logic_vector(0 to 0); - hsize : out std_logic_vector(1 downto 0); - hmaster_0 : in std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1); - hgrant : in std_logic_vector(3 to 3); - iosn_0 : in std_logic_vector(93 to 93); - bco_msb_1_m : in std_logic_vector(1 to 1); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1); - l1_0_m : in std_logic_vector(1 to 1); - hwdata : out std_logic_vector(31 downto 0); - coarse_time : in std_logic_vector(0 to 0); - coarse_time_i : in std_logic_vector(0 to 0); - pwdata_0 : in std_logic_vector(11 downto 0); - paddr_0 : in std_logic_vector(4 downto 2); - paddr : in std_logic_vector(7 downto 3); - paddr_2 : in std_logic_vector(2 to 2); - pwdata_1_2 : in std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_0 : in std_logic; - pwdata : in std_logic_vector(31 downto 0); - pirq : out std_logic_vector(15 to 15); - prdata : out std_logic_vector(31 downto 0); - lpp_top_lfr_wf_picker_VCC : in std_logic; - clk49_152MHz_c : in std_logic; - cnv_ch1_c : out std_logic; - sck_ch1_c : out std_logic; - lpp_top_lfr_wf_picker_GND : in std_logic; - IdlePhase : out std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - arb_1 : in std_logic; - hbusreq_i_3 : out std_logic; - Lock_RNIU86D : out std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic; - rstoutl_RNIGJKSJO : in std_logic; - m19_0_N_15_i_0_li : in std_logic; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - m26_m1_e : out std_logic; - lclk_c : in std_logic; - rstn : in std_logic; - N_232 : in std_logic; - N_6455_0 : in std_logic; - Bias_Fails_c : out std_logic; - N_749 : in std_logic; - N_116 : in std_logic; - N_769 : in std_logic; - N_232_0 : in std_logic; - N_232_1 : in std_logic; - rdata61_2 : in std_logic; - N_6455 : in std_logic; - un1_apbi_0 : in std_logic - ); - -end lpp_top_lfr_wf_picker; - -architecture DEF_ARCH of lpp_top_lfr_wf_picker is - - component VCC - port( Y : out std_logic - ); - end component; - - component lpp_top_apbreg - port( status_full_ack : out std_logic_vector(3 downto 0); - prdata : out std_logic_vector(31 downto 0); - pirq : out std_logic_vector(15 to 15); - pwdata : in std_logic_vector(31 downto 0) := (others => 'U'); - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - paddr_2 : in std_logic_vector(2 to 2) := (others => 'U'); - addr_data_f2 : out std_logic_vector(31 downto 0); - status_new_err_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - status_full_err_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - status_full_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - addr_data_f3 : out std_logic_vector(31 downto 0); - addr_data_f1 : out std_logic_vector(31 downto 0); - nb_burst_available : out std_logic_vector(10 downto 0); - addr_data_f0 : out std_logic_vector(31 downto 0); - nb_snapshot_param : out std_logic_vector(10 downto 0); - delta_snapshot : out std_logic_vector(15 downto 0); - delta_f2_f0 : out std_logic_vector(9 downto 0); - delta_f2_f1 : out std_logic_vector(9 downto 0); - paddr : in std_logic_vector(7 downto 3) := (others => 'U'); - paddr_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - pwdata_0 : in std_logic_vector(11 downto 0) := (others => 'U'); - data_shaping_R0 : out std_logic; - data_shaping_R1 : out std_logic; - un1_apbi_0 : in std_logic := 'U'; - N_6455 : in std_logic := 'U'; - rdata61_2 : in std_logic := 'U'; - burst_f2 : out std_logic; - burst_f0 : out std_logic; - N_232_1 : in std_logic := 'U'; - enable_f3 : out std_logic; - enable_f2 : out std_logic; - data_shaping_SP1 : out std_logic; - enable_f1 : out std_logic; - N_232_0 : in std_logic := 'U'; - enable_f0 : out std_logic; - N_769 : in std_logic := 'U'; - N_116 : in std_logic := 'U'; - N_749 : in std_logic := 'U'; - burst_f1 : out std_logic; - data_shaping_SP0 : out std_logic; - Bias_Fails_c : out std_logic; - N_6455_0 : in std_logic := 'U'; - N_232 : in std_logic := 'U'; - data_shaping_R1_0 : out std_logic; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - data_shaping_R0_0 : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component lpp_top_lfr_wf_picker_ip - port( nb_snapshot_param : in std_logic_vector(10 downto 0) := (others => 'U'); - coarse_time_i : in std_logic_vector(0 to 0) := (others => 'U'); - delta_f2_f0 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_f2_f1 : in std_logic_vector(9 downto 0) := (others => 'U'); - delta_snapshot : in std_logic_vector(15 downto 0) := (others => 'U'); - coarse_time : in std_logic_vector(0 to 0) := (others => 'U'); - status_new_err : out std_logic_vector(3 downto 0); - hwdata : out std_logic_vector(31 downto 0); - addr_data_f0 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f1 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f2 : in std_logic_vector(31 downto 0) := (others => 'U'); - addr_data_f3 : in std_logic_vector(31 downto 0) := (others => 'U'); - status_full : out std_logic_vector(3 downto 0); - status_full_err : out std_logic_vector(3 downto 0); - nb_burst_available : in std_logic_vector(10 downto 0) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : out std_logic_vector(1 downto 0); - hburst : out std_logic_vector(2 downto 0); - status_full_ack : in std_logic_vector(3 downto 0) := (others => 'U'); - sdo_adc_c : in std_logic_vector(7 downto 0) := (others => 'U'); - data_shaping_R0 : in std_logic := 'U'; - data_shaping_R0_0 : in std_logic := 'U'; - enable_f0 : in std_logic := 'U'; - burst_f0 : in std_logic := 'U'; - data_shaping_R1 : in std_logic := 'U'; - data_shaping_R1_0 : in std_logic := 'U'; - enable_f1 : in std_logic := 'U'; - burst_f1 : in std_logic := 'U'; - enable_f2 : in std_logic := 'U'; - burst_f2 : in std_logic := 'U'; - enable_f3 : in std_logic := 'U'; - m26_m1_e : out std_logic; - m19_a1_6_i_0 : out std_logic; - m19_a0_6_i_0 : out std_logic; - m19_0_N_15_i_0_li : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - Lock_RNIU86D : out std_logic; - hbusreq_i_3 : out std_logic; - arb_1 : in std_logic := 'U'; - un1_dmain_6 : out std_logic; - hwrite : out std_logic; - IdlePhase : out std_logic; - lpp_top_lfr_wf_picker_ip_GND : in std_logic := 'U'; - sck_ch1_c : out std_logic; - cnv_ch1_c : out std_logic; - clk49_152MHz_c : in std_logic := 'U'; - lpp_top_lfr_wf_picker_ip_VCC : in std_logic := 'U'; - data_shaping_SP0 : in std_logic := 'U'; - data_shaping_SP1 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - signal \status_full_ack[0]\, \status_full_ack[1]\, - \status_full_ack[2]\, \status_full_ack[3]\, - \addr_data_f2[0]\, \addr_data_f2[1]\, \addr_data_f2[2]\, - \addr_data_f2[3]\, \addr_data_f2[4]\, \addr_data_f2[5]\, - \addr_data_f2[6]\, \addr_data_f2[7]\, \addr_data_f2[8]\, - \addr_data_f2[9]\, \addr_data_f2[10]\, \addr_data_f2[11]\, - \addr_data_f2[12]\, \addr_data_f2[13]\, - \addr_data_f2[14]\, \addr_data_f2[15]\, - \addr_data_f2[16]\, \addr_data_f2[17]\, - \addr_data_f2[18]\, \addr_data_f2[19]\, - \addr_data_f2[20]\, \addr_data_f2[21]\, - \addr_data_f2[22]\, \addr_data_f2[23]\, - \addr_data_f2[24]\, \addr_data_f2[25]\, - \addr_data_f2[26]\, \addr_data_f2[27]\, - \addr_data_f2[28]\, \addr_data_f2[29]\, - \addr_data_f2[30]\, \addr_data_f2[31]\, - \status_new_err[0]\, \status_new_err[1]\, - \status_new_err[2]\, \status_new_err[3]\, - \status_full_err[0]\, \status_full_err[1]\, - \status_full_err[2]\, \status_full_err[3]\, - \status_full[0]\, \status_full[1]\, \status_full[2]\, - \status_full[3]\, \addr_data_f3[0]\, \addr_data_f3[1]\, - \addr_data_f3[2]\, \addr_data_f3[3]\, \addr_data_f3[4]\, - \addr_data_f3[5]\, \addr_data_f3[6]\, \addr_data_f3[7]\, - \addr_data_f3[8]\, \addr_data_f3[9]\, \addr_data_f3[10]\, - \addr_data_f3[11]\, \addr_data_f3[12]\, - \addr_data_f3[13]\, \addr_data_f3[14]\, - \addr_data_f3[15]\, \addr_data_f3[16]\, - \addr_data_f3[17]\, \addr_data_f3[18]\, - \addr_data_f3[19]\, \addr_data_f3[20]\, - \addr_data_f3[21]\, \addr_data_f3[22]\, - \addr_data_f3[23]\, \addr_data_f3[24]\, - \addr_data_f3[25]\, \addr_data_f3[26]\, - \addr_data_f3[27]\, \addr_data_f3[28]\, - \addr_data_f3[29]\, \addr_data_f3[30]\, - \addr_data_f3[31]\, \addr_data_f1[0]\, \addr_data_f1[1]\, - \addr_data_f1[2]\, \addr_data_f1[3]\, \addr_data_f1[4]\, - \addr_data_f1[5]\, \addr_data_f1[6]\, \addr_data_f1[7]\, - \addr_data_f1[8]\, \addr_data_f1[9]\, \addr_data_f1[10]\, - \addr_data_f1[11]\, \addr_data_f1[12]\, - \addr_data_f1[13]\, \addr_data_f1[14]\, - \addr_data_f1[15]\, \addr_data_f1[16]\, - \addr_data_f1[17]\, \addr_data_f1[18]\, - \addr_data_f1[19]\, \addr_data_f1[20]\, - \addr_data_f1[21]\, \addr_data_f1[22]\, - \addr_data_f1[23]\, \addr_data_f1[24]\, - \addr_data_f1[25]\, \addr_data_f1[26]\, - \addr_data_f1[27]\, \addr_data_f1[28]\, - \addr_data_f1[29]\, \addr_data_f1[30]\, - \addr_data_f1[31]\, \nb_burst_available[0]\, - \nb_burst_available[1]\, \nb_burst_available[2]\, - \nb_burst_available[3]\, \nb_burst_available[4]\, - \nb_burst_available[5]\, \nb_burst_available[6]\, - \nb_burst_available[7]\, \nb_burst_available[8]\, - \nb_burst_available[9]\, \nb_burst_available[10]\, - \addr_data_f0[0]\, \addr_data_f0[1]\, \addr_data_f0[2]\, - \addr_data_f0[3]\, \addr_data_f0[4]\, \addr_data_f0[5]\, - \addr_data_f0[6]\, \addr_data_f0[7]\, \addr_data_f0[8]\, - \addr_data_f0[9]\, \addr_data_f0[10]\, \addr_data_f0[11]\, - \addr_data_f0[12]\, \addr_data_f0[13]\, - \addr_data_f0[14]\, \addr_data_f0[15]\, - \addr_data_f0[16]\, \addr_data_f0[17]\, - \addr_data_f0[18]\, \addr_data_f0[19]\, - \addr_data_f0[20]\, \addr_data_f0[21]\, - \addr_data_f0[22]\, \addr_data_f0[23]\, - \addr_data_f0[24]\, \addr_data_f0[25]\, - \addr_data_f0[26]\, \addr_data_f0[27]\, - \addr_data_f0[28]\, \addr_data_f0[29]\, - \addr_data_f0[30]\, \addr_data_f0[31]\, - \nb_snapshot_param[0]\, \nb_snapshot_param[1]\, - \nb_snapshot_param[2]\, \nb_snapshot_param[3]\, - \nb_snapshot_param[4]\, \nb_snapshot_param[5]\, - \nb_snapshot_param[6]\, \nb_snapshot_param[7]\, - \nb_snapshot_param[8]\, \nb_snapshot_param[9]\, - \nb_snapshot_param[10]\, \delta_snapshot[0]\, - \delta_snapshot[1]\, \delta_snapshot[2]\, - \delta_snapshot[3]\, \delta_snapshot[4]\, - \delta_snapshot[5]\, \delta_snapshot[6]\, - \delta_snapshot[7]\, \delta_snapshot[8]\, - \delta_snapshot[9]\, \delta_snapshot[10]\, - \delta_snapshot[11]\, \delta_snapshot[12]\, - \delta_snapshot[13]\, \delta_snapshot[14]\, - \delta_snapshot[15]\, \delta_f2_f0[0]\, \delta_f2_f0[1]\, - \delta_f2_f0[2]\, \delta_f2_f0[3]\, \delta_f2_f0[4]\, - \delta_f2_f0[5]\, \delta_f2_f0[6]\, \delta_f2_f0[7]\, - \delta_f2_f0[8]\, \delta_f2_f0[9]\, \delta_f2_f1[0]\, - \delta_f2_f1[1]\, \delta_f2_f1[2]\, \delta_f2_f1[3]\, - \delta_f2_f1[4]\, \delta_f2_f1[5]\, \delta_f2_f1[6]\, - \delta_f2_f1[7]\, \delta_f2_f1[8]\, \delta_f2_f1[9]\, - data_shaping_R0, data_shaping_R1, burst_f2, burst_f0, - enable_f3, enable_f2, data_shaping_SP1, enable_f1, - enable_f0, burst_f1, data_shaping_SP0, data_shaping_R1_0, - data_shaping_R0_0, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - - for all : lpp_top_apbreg - Use entity work.lpp_top_apbreg(DEF_ARCH); - for all : lpp_top_lfr_wf_picker_ip - Use entity work.lpp_top_lfr_wf_picker_ip(DEF_ARCH); -begin - - - VCC_i_0 : VCC - port map(Y => VCC_0); - - lpp_top_apbreg_1 : lpp_top_apbreg - port map(status_full_ack(3) => \status_full_ack[3]\, - status_full_ack(2) => \status_full_ack[2]\, - status_full_ack(1) => \status_full_ack[1]\, - status_full_ack(0) => \status_full_ack[0]\, prdata(31) - => prdata(31), prdata(30) => prdata(30), prdata(29) => - prdata(29), prdata(28) => prdata(28), prdata(27) => - prdata(27), prdata(26) => prdata(26), prdata(25) => - prdata(25), prdata(24) => prdata(24), prdata(23) => - prdata(23), prdata(22) => prdata(22), prdata(21) => - prdata(21), prdata(20) => prdata(20), prdata(19) => - prdata(19), prdata(18) => prdata(18), prdata(17) => - prdata(17), prdata(16) => prdata(16), prdata(15) => - prdata(15), prdata(14) => prdata(14), prdata(13) => - prdata(13), prdata(12) => prdata(12), prdata(11) => - prdata(11), prdata(10) => prdata(10), prdata(9) => - prdata(9), prdata(8) => prdata(8), prdata(7) => prdata(7), - prdata(6) => prdata(6), prdata(5) => prdata(5), prdata(4) - => prdata(4), prdata(3) => prdata(3), prdata(2) => - prdata(2), prdata(1) => prdata(1), prdata(0) => prdata(0), - pirq(15) => pirq(15), pwdata(31) => pwdata(31), - pwdata(30) => pwdata(30), pwdata(29) => pwdata(29), - pwdata(28) => pwdata(28), pwdata(27) => pwdata(27), - pwdata(26) => pwdata(26), pwdata(25) => pwdata(25), - pwdata(24) => pwdata(24), pwdata(23) => pwdata(23), - pwdata(22) => pwdata(22), pwdata(21) => pwdata(21), - pwdata(20) => pwdata(20), pwdata(19) => pwdata(19), - pwdata(18) => pwdata(18), pwdata(17) => pwdata(17), - pwdata(16) => pwdata(16), pwdata(15) => pwdata(15), - pwdata(14) => pwdata(14), pwdata(13) => pwdata(13), - pwdata(12) => pwdata(12), pwdata(11) => pwdata(11), - pwdata(10) => pwdata(10), pwdata(9) => pwdata(9), - pwdata(8) => pwdata(8), pwdata(7) => pwdata(7), pwdata(6) - => pwdata(6), pwdata(5) => pwdata(5), pwdata(4) => - pwdata(4), pwdata(3) => pwdata(3), pwdata(2) => pwdata(2), - pwdata(1) => pwdata(1), pwdata(0) => pwdata(0), - pwdata_1_0 => pwdata_1_0, pwdata_1_3 => pwdata_1_3, - pwdata_1_2 => pwdata_1_2, paddr_2(2) => paddr_2(2), - addr_data_f2(31) => \addr_data_f2[31]\, addr_data_f2(30) - => \addr_data_f2[30]\, addr_data_f2(29) => - \addr_data_f2[29]\, addr_data_f2(28) => - \addr_data_f2[28]\, addr_data_f2(27) => - \addr_data_f2[27]\, addr_data_f2(26) => - \addr_data_f2[26]\, addr_data_f2(25) => - \addr_data_f2[25]\, addr_data_f2(24) => - \addr_data_f2[24]\, addr_data_f2(23) => - \addr_data_f2[23]\, addr_data_f2(22) => - \addr_data_f2[22]\, addr_data_f2(21) => - \addr_data_f2[21]\, addr_data_f2(20) => - \addr_data_f2[20]\, addr_data_f2(19) => - \addr_data_f2[19]\, addr_data_f2(18) => - \addr_data_f2[18]\, addr_data_f2(17) => - \addr_data_f2[17]\, addr_data_f2(16) => - \addr_data_f2[16]\, addr_data_f2(15) => - \addr_data_f2[15]\, addr_data_f2(14) => - \addr_data_f2[14]\, addr_data_f2(13) => - \addr_data_f2[13]\, addr_data_f2(12) => - \addr_data_f2[12]\, addr_data_f2(11) => - \addr_data_f2[11]\, addr_data_f2(10) => - \addr_data_f2[10]\, addr_data_f2(9) => \addr_data_f2[9]\, - addr_data_f2(8) => \addr_data_f2[8]\, addr_data_f2(7) => - \addr_data_f2[7]\, addr_data_f2(6) => \addr_data_f2[6]\, - addr_data_f2(5) => \addr_data_f2[5]\, addr_data_f2(4) => - \addr_data_f2[4]\, addr_data_f2(3) => \addr_data_f2[3]\, - addr_data_f2(2) => \addr_data_f2[2]\, addr_data_f2(1) => - \addr_data_f2[1]\, addr_data_f2(0) => \addr_data_f2[0]\, - status_new_err_0(3) => \status_new_err[3]\, - status_new_err_0(2) => \status_new_err[2]\, - status_new_err_0(1) => \status_new_err[1]\, - status_new_err_0(0) => \status_new_err[0]\, - status_full_err_0(3) => \status_full_err[3]\, - status_full_err_0(2) => \status_full_err[2]\, - status_full_err_0(1) => \status_full_err[1]\, - status_full_err_0(0) => \status_full_err[0]\, - status_full_0(3) => \status_full[3]\, status_full_0(2) - => \status_full[2]\, status_full_0(1) => - \status_full[1]\, status_full_0(0) => \status_full[0]\, - addr_data_f3(31) => \addr_data_f3[31]\, addr_data_f3(30) - => \addr_data_f3[30]\, addr_data_f3(29) => - \addr_data_f3[29]\, addr_data_f3(28) => - \addr_data_f3[28]\, addr_data_f3(27) => - \addr_data_f3[27]\, addr_data_f3(26) => - \addr_data_f3[26]\, addr_data_f3(25) => - \addr_data_f3[25]\, addr_data_f3(24) => - \addr_data_f3[24]\, addr_data_f3(23) => - \addr_data_f3[23]\, addr_data_f3(22) => - \addr_data_f3[22]\, addr_data_f3(21) => - \addr_data_f3[21]\, addr_data_f3(20) => - \addr_data_f3[20]\, addr_data_f3(19) => - \addr_data_f3[19]\, addr_data_f3(18) => - \addr_data_f3[18]\, addr_data_f3(17) => - \addr_data_f3[17]\, addr_data_f3(16) => - \addr_data_f3[16]\, addr_data_f3(15) => - \addr_data_f3[15]\, addr_data_f3(14) => - \addr_data_f3[14]\, addr_data_f3(13) => - \addr_data_f3[13]\, addr_data_f3(12) => - \addr_data_f3[12]\, addr_data_f3(11) => - \addr_data_f3[11]\, addr_data_f3(10) => - \addr_data_f3[10]\, addr_data_f3(9) => \addr_data_f3[9]\, - addr_data_f3(8) => \addr_data_f3[8]\, addr_data_f3(7) => - \addr_data_f3[7]\, addr_data_f3(6) => \addr_data_f3[6]\, - addr_data_f3(5) => \addr_data_f3[5]\, addr_data_f3(4) => - \addr_data_f3[4]\, addr_data_f3(3) => \addr_data_f3[3]\, - addr_data_f3(2) => \addr_data_f3[2]\, addr_data_f3(1) => - \addr_data_f3[1]\, addr_data_f3(0) => \addr_data_f3[0]\, - addr_data_f1(31) => \addr_data_f1[31]\, addr_data_f1(30) - => \addr_data_f1[30]\, addr_data_f1(29) => - \addr_data_f1[29]\, addr_data_f1(28) => - \addr_data_f1[28]\, addr_data_f1(27) => - \addr_data_f1[27]\, addr_data_f1(26) => - \addr_data_f1[26]\, addr_data_f1(25) => - \addr_data_f1[25]\, addr_data_f1(24) => - \addr_data_f1[24]\, addr_data_f1(23) => - \addr_data_f1[23]\, addr_data_f1(22) => - \addr_data_f1[22]\, addr_data_f1(21) => - \addr_data_f1[21]\, addr_data_f1(20) => - \addr_data_f1[20]\, addr_data_f1(19) => - \addr_data_f1[19]\, addr_data_f1(18) => - \addr_data_f1[18]\, addr_data_f1(17) => - \addr_data_f1[17]\, addr_data_f1(16) => - \addr_data_f1[16]\, addr_data_f1(15) => - \addr_data_f1[15]\, addr_data_f1(14) => - \addr_data_f1[14]\, addr_data_f1(13) => - \addr_data_f1[13]\, addr_data_f1(12) => - \addr_data_f1[12]\, addr_data_f1(11) => - \addr_data_f1[11]\, addr_data_f1(10) => - \addr_data_f1[10]\, addr_data_f1(9) => \addr_data_f1[9]\, - addr_data_f1(8) => \addr_data_f1[8]\, addr_data_f1(7) => - \addr_data_f1[7]\, addr_data_f1(6) => \addr_data_f1[6]\, - addr_data_f1(5) => \addr_data_f1[5]\, addr_data_f1(4) => - \addr_data_f1[4]\, addr_data_f1(3) => \addr_data_f1[3]\, - addr_data_f1(2) => \addr_data_f1[2]\, addr_data_f1(1) => - \addr_data_f1[1]\, addr_data_f1(0) => \addr_data_f1[0]\, - nb_burst_available(10) => \nb_burst_available[10]\, - nb_burst_available(9) => \nb_burst_available[9]\, - nb_burst_available(8) => \nb_burst_available[8]\, - nb_burst_available(7) => \nb_burst_available[7]\, - nb_burst_available(6) => \nb_burst_available[6]\, - nb_burst_available(5) => \nb_burst_available[5]\, - nb_burst_available(4) => \nb_burst_available[4]\, - nb_burst_available(3) => \nb_burst_available[3]\, - nb_burst_available(2) => \nb_burst_available[2]\, - nb_burst_available(1) => \nb_burst_available[1]\, - nb_burst_available(0) => \nb_burst_available[0]\, - addr_data_f0(31) => \addr_data_f0[31]\, addr_data_f0(30) - => \addr_data_f0[30]\, addr_data_f0(29) => - \addr_data_f0[29]\, addr_data_f0(28) => - \addr_data_f0[28]\, addr_data_f0(27) => - \addr_data_f0[27]\, addr_data_f0(26) => - \addr_data_f0[26]\, addr_data_f0(25) => - \addr_data_f0[25]\, addr_data_f0(24) => - \addr_data_f0[24]\, addr_data_f0(23) => - \addr_data_f0[23]\, addr_data_f0(22) => - \addr_data_f0[22]\, addr_data_f0(21) => - \addr_data_f0[21]\, addr_data_f0(20) => - \addr_data_f0[20]\, addr_data_f0(19) => - \addr_data_f0[19]\, addr_data_f0(18) => - \addr_data_f0[18]\, addr_data_f0(17) => - \addr_data_f0[17]\, addr_data_f0(16) => - \addr_data_f0[16]\, addr_data_f0(15) => - \addr_data_f0[15]\, addr_data_f0(14) => - \addr_data_f0[14]\, addr_data_f0(13) => - \addr_data_f0[13]\, addr_data_f0(12) => - \addr_data_f0[12]\, addr_data_f0(11) => - \addr_data_f0[11]\, addr_data_f0(10) => - \addr_data_f0[10]\, addr_data_f0(9) => \addr_data_f0[9]\, - addr_data_f0(8) => \addr_data_f0[8]\, addr_data_f0(7) => - \addr_data_f0[7]\, addr_data_f0(6) => \addr_data_f0[6]\, - addr_data_f0(5) => \addr_data_f0[5]\, addr_data_f0(4) => - \addr_data_f0[4]\, addr_data_f0(3) => \addr_data_f0[3]\, - addr_data_f0(2) => \addr_data_f0[2]\, addr_data_f0(1) => - \addr_data_f0[1]\, addr_data_f0(0) => \addr_data_f0[0]\, - nb_snapshot_param(10) => \nb_snapshot_param[10]\, - nb_snapshot_param(9) => \nb_snapshot_param[9]\, - nb_snapshot_param(8) => \nb_snapshot_param[8]\, - nb_snapshot_param(7) => \nb_snapshot_param[7]\, - nb_snapshot_param(6) => \nb_snapshot_param[6]\, - nb_snapshot_param(5) => \nb_snapshot_param[5]\, - nb_snapshot_param(4) => \nb_snapshot_param[4]\, - nb_snapshot_param(3) => \nb_snapshot_param[3]\, - nb_snapshot_param(2) => \nb_snapshot_param[2]\, - nb_snapshot_param(1) => \nb_snapshot_param[1]\, - nb_snapshot_param(0) => \nb_snapshot_param[0]\, - delta_snapshot(15) => \delta_snapshot[15]\, - delta_snapshot(14) => \delta_snapshot[14]\, - delta_snapshot(13) => \delta_snapshot[13]\, - delta_snapshot(12) => \delta_snapshot[12]\, - delta_snapshot(11) => \delta_snapshot[11]\, - delta_snapshot(10) => \delta_snapshot[10]\, - delta_snapshot(9) => \delta_snapshot[9]\, - delta_snapshot(8) => \delta_snapshot[8]\, - delta_snapshot(7) => \delta_snapshot[7]\, - delta_snapshot(6) => \delta_snapshot[6]\, - delta_snapshot(5) => \delta_snapshot[5]\, - delta_snapshot(4) => \delta_snapshot[4]\, - delta_snapshot(3) => \delta_snapshot[3]\, - delta_snapshot(2) => \delta_snapshot[2]\, - delta_snapshot(1) => \delta_snapshot[1]\, - delta_snapshot(0) => \delta_snapshot[0]\, delta_f2_f0(9) - => \delta_f2_f0[9]\, delta_f2_f0(8) => \delta_f2_f0[8]\, - delta_f2_f0(7) => \delta_f2_f0[7]\, delta_f2_f0(6) => - \delta_f2_f0[6]\, delta_f2_f0(5) => \delta_f2_f0[5]\, - delta_f2_f0(4) => \delta_f2_f0[4]\, delta_f2_f0(3) => - \delta_f2_f0[3]\, delta_f2_f0(2) => \delta_f2_f0[2]\, - delta_f2_f0(1) => \delta_f2_f0[1]\, delta_f2_f0(0) => - \delta_f2_f0[0]\, delta_f2_f1(9) => \delta_f2_f1[9]\, - delta_f2_f1(8) => \delta_f2_f1[8]\, delta_f2_f1(7) => - \delta_f2_f1[7]\, delta_f2_f1(6) => \delta_f2_f1[6]\, - delta_f2_f1(5) => \delta_f2_f1[5]\, delta_f2_f1(4) => - \delta_f2_f1[4]\, delta_f2_f1(3) => \delta_f2_f1[3]\, - delta_f2_f1(2) => \delta_f2_f1[2]\, delta_f2_f1(1) => - \delta_f2_f1[1]\, delta_f2_f1(0) => \delta_f2_f1[0]\, - paddr(7) => paddr(7), paddr(6) => paddr(6), paddr(5) => - paddr(5), paddr(4) => paddr(4), paddr(3) => paddr(3), - paddr_0(4) => paddr_0(4), paddr_0(3) => paddr_0(3), - paddr_0(2) => paddr_0(2), pwdata_0(11) => pwdata_0(11), - pwdata_0(10) => pwdata_0(10), pwdata_0(9) => pwdata_0(9), - pwdata_0(8) => pwdata_0(8), pwdata_0(7) => pwdata_0(7), - pwdata_0(6) => pwdata_0(6), pwdata_0(5) => pwdata_0(5), - pwdata_0(4) => pwdata_0(4), pwdata_0(3) => pwdata_0(3), - pwdata_0(2) => pwdata_0(2), pwdata_0(1) => pwdata_0(1), - pwdata_0(0) => pwdata_0(0), data_shaping_R0 => - data_shaping_R0, data_shaping_R1 => data_shaping_R1, - un1_apbi_0 => un1_apbi_0, N_6455 => N_6455, rdata61_2 => - rdata61_2, burst_f2 => burst_f2, burst_f0 => burst_f0, - N_232_1 => N_232_1, enable_f3 => enable_f3, enable_f2 => - enable_f2, data_shaping_SP1 => data_shaping_SP1, - enable_f1 => enable_f1, N_232_0 => N_232_0, enable_f0 => - enable_f0, N_769 => N_769, N_116 => N_116, N_749 => N_749, - burst_f1 => burst_f1, data_shaping_SP0 => - data_shaping_SP0, Bias_Fails_c => Bias_Fails_c, N_6455_0 - => N_6455_0, N_232 => N_232, data_shaping_R1_0 => - data_shaping_R1_0, rstn => rstn, lclk_c => lclk_c, - data_shaping_R0_0 => data_shaping_R0_0); - - GND_i_0 : GND - port map(Y => GND_0); - - VCC_i : VCC - port map(Y => \VCC\); - - lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip - port map(nb_snapshot_param(10) => \nb_snapshot_param[10]\, - nb_snapshot_param(9) => \nb_snapshot_param[9]\, - nb_snapshot_param(8) => \nb_snapshot_param[8]\, - nb_snapshot_param(7) => \nb_snapshot_param[7]\, - nb_snapshot_param(6) => \nb_snapshot_param[6]\, - nb_snapshot_param(5) => \nb_snapshot_param[5]\, - nb_snapshot_param(4) => \nb_snapshot_param[4]\, - nb_snapshot_param(3) => \nb_snapshot_param[3]\, - nb_snapshot_param(2) => \nb_snapshot_param[2]\, - nb_snapshot_param(1) => \nb_snapshot_param[1]\, - nb_snapshot_param(0) => \nb_snapshot_param[0]\, - coarse_time_i(0) => coarse_time_i(0), delta_f2_f0(9) => - \delta_f2_f0[9]\, delta_f2_f0(8) => \delta_f2_f0[8]\, - delta_f2_f0(7) => \delta_f2_f0[7]\, delta_f2_f0(6) => - \delta_f2_f0[6]\, delta_f2_f0(5) => \delta_f2_f0[5]\, - delta_f2_f0(4) => \delta_f2_f0[4]\, delta_f2_f0(3) => - \delta_f2_f0[3]\, delta_f2_f0(2) => \delta_f2_f0[2]\, - delta_f2_f0(1) => \delta_f2_f0[1]\, delta_f2_f0(0) => - \delta_f2_f0[0]\, delta_f2_f1(9) => \delta_f2_f1[9]\, - delta_f2_f1(8) => \delta_f2_f1[8]\, delta_f2_f1(7) => - \delta_f2_f1[7]\, delta_f2_f1(6) => \delta_f2_f1[6]\, - delta_f2_f1(5) => \delta_f2_f1[5]\, delta_f2_f1(4) => - \delta_f2_f1[4]\, delta_f2_f1(3) => \delta_f2_f1[3]\, - delta_f2_f1(2) => \delta_f2_f1[2]\, delta_f2_f1(1) => - \delta_f2_f1[1]\, delta_f2_f1(0) => \delta_f2_f1[0]\, - delta_snapshot(15) => \delta_snapshot[15]\, - delta_snapshot(14) => \delta_snapshot[14]\, - delta_snapshot(13) => \delta_snapshot[13]\, - delta_snapshot(12) => \delta_snapshot[12]\, - delta_snapshot(11) => \delta_snapshot[11]\, - delta_snapshot(10) => \delta_snapshot[10]\, - delta_snapshot(9) => \delta_snapshot[9]\, - delta_snapshot(8) => \delta_snapshot[8]\, - delta_snapshot(7) => \delta_snapshot[7]\, - delta_snapshot(6) => \delta_snapshot[6]\, - delta_snapshot(5) => \delta_snapshot[5]\, - delta_snapshot(4) => \delta_snapshot[4]\, - delta_snapshot(3) => \delta_snapshot[3]\, - delta_snapshot(2) => \delta_snapshot[2]\, - delta_snapshot(1) => \delta_snapshot[1]\, - delta_snapshot(0) => \delta_snapshot[0]\, coarse_time(0) - => coarse_time(0), status_new_err(3) => - \status_new_err[3]\, status_new_err(2) => - \status_new_err[2]\, status_new_err(1) => - \status_new_err[1]\, status_new_err(0) => - \status_new_err[0]\, hwdata(31) => hwdata(31), hwdata(30) - => hwdata(30), hwdata(29) => hwdata(29), hwdata(28) => - hwdata(28), hwdata(27) => hwdata(27), hwdata(26) => - hwdata(26), hwdata(25) => hwdata(25), hwdata(24) => - hwdata(24), hwdata(23) => hwdata(23), hwdata(22) => - hwdata(22), hwdata(21) => hwdata(21), hwdata(20) => - hwdata(20), hwdata(19) => hwdata(19), hwdata(18) => - hwdata(18), hwdata(17) => hwdata(17), hwdata(16) => - hwdata(16), hwdata(15) => hwdata(15), hwdata(14) => - hwdata(14), hwdata(13) => hwdata(13), hwdata(12) => - hwdata(12), hwdata(11) => hwdata(11), hwdata(10) => - hwdata(10), hwdata(9) => hwdata(9), hwdata(8) => - hwdata(8), hwdata(7) => hwdata(7), hwdata(6) => hwdata(6), - hwdata(5) => hwdata(5), hwdata(4) => hwdata(4), hwdata(3) - => hwdata(3), hwdata(2) => hwdata(2), hwdata(1) => - hwdata(1), hwdata(0) => hwdata(0), addr_data_f0(31) => - \addr_data_f0[31]\, addr_data_f0(30) => - \addr_data_f0[30]\, addr_data_f0(29) => - \addr_data_f0[29]\, addr_data_f0(28) => - \addr_data_f0[28]\, addr_data_f0(27) => - \addr_data_f0[27]\, addr_data_f0(26) => - \addr_data_f0[26]\, addr_data_f0(25) => - \addr_data_f0[25]\, addr_data_f0(24) => - \addr_data_f0[24]\, addr_data_f0(23) => - \addr_data_f0[23]\, addr_data_f0(22) => - \addr_data_f0[22]\, addr_data_f0(21) => - \addr_data_f0[21]\, addr_data_f0(20) => - \addr_data_f0[20]\, addr_data_f0(19) => - \addr_data_f0[19]\, addr_data_f0(18) => - \addr_data_f0[18]\, addr_data_f0(17) => - \addr_data_f0[17]\, addr_data_f0(16) => - \addr_data_f0[16]\, addr_data_f0(15) => - \addr_data_f0[15]\, addr_data_f0(14) => - \addr_data_f0[14]\, addr_data_f0(13) => - \addr_data_f0[13]\, addr_data_f0(12) => - \addr_data_f0[12]\, addr_data_f0(11) => - \addr_data_f0[11]\, addr_data_f0(10) => - \addr_data_f0[10]\, addr_data_f0(9) => \addr_data_f0[9]\, - addr_data_f0(8) => \addr_data_f0[8]\, addr_data_f0(7) => - \addr_data_f0[7]\, addr_data_f0(6) => \addr_data_f0[6]\, - addr_data_f0(5) => \addr_data_f0[5]\, addr_data_f0(4) => - \addr_data_f0[4]\, addr_data_f0(3) => \addr_data_f0[3]\, - addr_data_f0(2) => \addr_data_f0[2]\, addr_data_f0(1) => - \addr_data_f0[1]\, addr_data_f0(0) => \addr_data_f0[0]\, - addr_data_f1(31) => \addr_data_f1[31]\, addr_data_f1(30) - => \addr_data_f1[30]\, addr_data_f1(29) => - \addr_data_f1[29]\, addr_data_f1(28) => - \addr_data_f1[28]\, addr_data_f1(27) => - \addr_data_f1[27]\, addr_data_f1(26) => - \addr_data_f1[26]\, addr_data_f1(25) => - \addr_data_f1[25]\, addr_data_f1(24) => - \addr_data_f1[24]\, addr_data_f1(23) => - \addr_data_f1[23]\, addr_data_f1(22) => - \addr_data_f1[22]\, addr_data_f1(21) => - \addr_data_f1[21]\, addr_data_f1(20) => - \addr_data_f1[20]\, addr_data_f1(19) => - \addr_data_f1[19]\, addr_data_f1(18) => - \addr_data_f1[18]\, addr_data_f1(17) => - \addr_data_f1[17]\, addr_data_f1(16) => - \addr_data_f1[16]\, addr_data_f1(15) => - \addr_data_f1[15]\, addr_data_f1(14) => - \addr_data_f1[14]\, addr_data_f1(13) => - \addr_data_f1[13]\, addr_data_f1(12) => - \addr_data_f1[12]\, addr_data_f1(11) => - \addr_data_f1[11]\, addr_data_f1(10) => - \addr_data_f1[10]\, addr_data_f1(9) => \addr_data_f1[9]\, - addr_data_f1(8) => \addr_data_f1[8]\, addr_data_f1(7) => - \addr_data_f1[7]\, addr_data_f1(6) => \addr_data_f1[6]\, - addr_data_f1(5) => \addr_data_f1[5]\, addr_data_f1(4) => - \addr_data_f1[4]\, addr_data_f1(3) => \addr_data_f1[3]\, - addr_data_f1(2) => \addr_data_f1[2]\, addr_data_f1(1) => - \addr_data_f1[1]\, addr_data_f1(0) => \addr_data_f1[0]\, - addr_data_f2(31) => \addr_data_f2[31]\, addr_data_f2(30) - => \addr_data_f2[30]\, addr_data_f2(29) => - \addr_data_f2[29]\, addr_data_f2(28) => - \addr_data_f2[28]\, addr_data_f2(27) => - \addr_data_f2[27]\, addr_data_f2(26) => - \addr_data_f2[26]\, addr_data_f2(25) => - \addr_data_f2[25]\, addr_data_f2(24) => - \addr_data_f2[24]\, addr_data_f2(23) => - \addr_data_f2[23]\, addr_data_f2(22) => - \addr_data_f2[22]\, addr_data_f2(21) => - \addr_data_f2[21]\, addr_data_f2(20) => - \addr_data_f2[20]\, addr_data_f2(19) => - \addr_data_f2[19]\, addr_data_f2(18) => - \addr_data_f2[18]\, addr_data_f2(17) => - \addr_data_f2[17]\, addr_data_f2(16) => - \addr_data_f2[16]\, addr_data_f2(15) => - \addr_data_f2[15]\, addr_data_f2(14) => - \addr_data_f2[14]\, addr_data_f2(13) => - \addr_data_f2[13]\, addr_data_f2(12) => - \addr_data_f2[12]\, addr_data_f2(11) => - \addr_data_f2[11]\, addr_data_f2(10) => - \addr_data_f2[10]\, addr_data_f2(9) => \addr_data_f2[9]\, - addr_data_f2(8) => \addr_data_f2[8]\, addr_data_f2(7) => - \addr_data_f2[7]\, addr_data_f2(6) => \addr_data_f2[6]\, - addr_data_f2(5) => \addr_data_f2[5]\, addr_data_f2(4) => - \addr_data_f2[4]\, addr_data_f2(3) => \addr_data_f2[3]\, - addr_data_f2(2) => \addr_data_f2[2]\, addr_data_f2(1) => - \addr_data_f2[1]\, addr_data_f2(0) => \addr_data_f2[0]\, - addr_data_f3(31) => \addr_data_f3[31]\, addr_data_f3(30) - => \addr_data_f3[30]\, addr_data_f3(29) => - \addr_data_f3[29]\, addr_data_f3(28) => - \addr_data_f3[28]\, addr_data_f3(27) => - \addr_data_f3[27]\, addr_data_f3(26) => - \addr_data_f3[26]\, addr_data_f3(25) => - \addr_data_f3[25]\, addr_data_f3(24) => - \addr_data_f3[24]\, addr_data_f3(23) => - \addr_data_f3[23]\, addr_data_f3(22) => - \addr_data_f3[22]\, addr_data_f3(21) => - \addr_data_f3[21]\, addr_data_f3(20) => - \addr_data_f3[20]\, addr_data_f3(19) => - \addr_data_f3[19]\, addr_data_f3(18) => - \addr_data_f3[18]\, addr_data_f3(17) => - \addr_data_f3[17]\, addr_data_f3(16) => - \addr_data_f3[16]\, addr_data_f3(15) => - \addr_data_f3[15]\, addr_data_f3(14) => - \addr_data_f3[14]\, addr_data_f3(13) => - \addr_data_f3[13]\, addr_data_f3(12) => - \addr_data_f3[12]\, addr_data_f3(11) => - \addr_data_f3[11]\, addr_data_f3(10) => - \addr_data_f3[10]\, addr_data_f3(9) => \addr_data_f3[9]\, - addr_data_f3(8) => \addr_data_f3[8]\, addr_data_f3(7) => - \addr_data_f3[7]\, addr_data_f3(6) => \addr_data_f3[6]\, - addr_data_f3(5) => \addr_data_f3[5]\, addr_data_f3(4) => - \addr_data_f3[4]\, addr_data_f3(3) => \addr_data_f3[3]\, - addr_data_f3(2) => \addr_data_f3[2]\, addr_data_f3(1) => - \addr_data_f3[1]\, addr_data_f3(0) => \addr_data_f3[0]\, - status_full(3) => \status_full[3]\, status_full(2) => - \status_full[2]\, status_full(1) => \status_full[1]\, - status_full(0) => \status_full[0]\, status_full_err(3) - => \status_full_err[3]\, status_full_err(2) => - \status_full_err[2]\, status_full_err(1) => - \status_full_err[1]\, status_full_err(0) => - \status_full_err[0]\, nb_burst_available(10) => - \nb_burst_available[10]\, nb_burst_available(9) => - \nb_burst_available[9]\, nb_burst_available(8) => - \nb_burst_available[8]\, nb_burst_available(7) => - \nb_burst_available[7]\, nb_burst_available(6) => - \nb_burst_available[6]\, nb_burst_available(5) => - \nb_burst_available[5]\, nb_burst_available(4) => - \nb_burst_available[4]\, nb_burst_available(3) => - \nb_burst_available[3]\, nb_burst_available(2) => - \nb_burst_available[2]\, nb_burst_available(1) => - \nb_burst_available[1]\, nb_burst_available(0) => - \nb_burst_available[0]\, l1_0_m(1) => l1_0_m(1), - nhmaster_1_iv_0(1) => nhmaster_1_iv_0(1), bco_msb_1_m(1) - => bco_msb_1_m(1), iosn_0(93) => iosn_0(93), hgrant(3) - => hgrant(3), hmaster_0_0_RNIFCVH1_0(1) => - hmaster_0_0_RNIFCVH1_0(1), bco_msb_1(1) => bco_msb_1(1), - haddr(31) => haddr(31), haddr(30) => haddr(30), haddr(29) - => haddr(29), haddr(28) => haddr(28), haddr(27) => - haddr(27), haddr(26) => haddr(26), haddr(25) => haddr(25), - haddr(24) => haddr(24), haddr(23) => haddr(23), haddr(22) - => haddr(22), haddr(21) => haddr(21), haddr(20) => - haddr(20), haddr(19) => haddr(19), haddr(18) => haddr(18), - haddr(17) => haddr(17), haddr(16) => haddr(16), haddr(15) - => haddr(15), haddr(14) => haddr(14), haddr(13) => - haddr(13), haddr(12) => haddr(12), haddr(11) => haddr(11), - haddr(10) => haddr(10), haddr(9) => haddr(9), haddr(8) - => haddr(8), haddr(7) => haddr(7), haddr(6) => haddr(6), - haddr(5) => haddr(5), haddr(4) => haddr(4), haddr(3) => - haddr(3), haddr(2) => haddr(2), haddr(1) => haddr(1), - haddr(0) => haddr(0), hmaster_0(1) => hmaster_0(1), - hsize(1) => hsize(1), hsize(0) => hsize(0), - nhmaster_1_i(0) => nhmaster_1_i(0), iosn_1(93) => - iosn_1(93), hresp(0) => hresp(0), iosn_2(93) => - iosn_2(93), htrans(1) => htrans(1), htrans(0) => - htrans(0), hburst(2) => hburst(2), hburst(1) => hburst(1), - hburst(0) => hburst(0), status_full_ack(3) => - \status_full_ack[3]\, status_full_ack(2) => - \status_full_ack[2]\, status_full_ack(1) => - \status_full_ack[1]\, status_full_ack(0) => - \status_full_ack[0]\, sdo_adc_c(7) => sdo_adc_c(7), - sdo_adc_c(6) => sdo_adc_c(6), sdo_adc_c(5) => - sdo_adc_c(5), sdo_adc_c(4) => sdo_adc_c(4), sdo_adc_c(3) - => sdo_adc_c(3), sdo_adc_c(2) => sdo_adc_c(2), - sdo_adc_c(1) => sdo_adc_c(1), sdo_adc_c(0) => - sdo_adc_c(0), data_shaping_R0 => data_shaping_R0, - data_shaping_R0_0 => data_shaping_R0_0, enable_f0 => - enable_f0, burst_f0 => burst_f0, data_shaping_R1 => - data_shaping_R1, data_shaping_R1_0 => data_shaping_R1_0, - enable_f1 => enable_f1, burst_f1 => burst_f1, enable_f2 - => enable_f2, burst_f2 => burst_f2, enable_f3 => - enable_f3, m26_m1_e => m26_m1_e, m19_a1_6_i_0 => - m19_a1_6_i_0, m19_a0_6_i_0 => m19_a0_6_i_0, - m19_0_N_15_i_0_li => m19_0_N_15_i_0_li, rstoutl_RNIGJKSJO - => rstoutl_RNIGJKSJO, un1_nhmaster_0_sqmuxa_1 => - un1_nhmaster_0_sqmuxa_1, Lock_RNIU86D => Lock_RNIU86D, - hbusreq_i_3 => hbusreq_i_3, arb_1 => arb_1, un1_dmain_6 - => un1_dmain_6, hwrite => hwrite, IdlePhase => IdlePhase, - lpp_top_lfr_wf_picker_ip_GND => lpp_top_lfr_wf_picker_GND, - sck_ch1_c => sck_ch1_c, cnv_ch1_c => cnv_ch1_c, - clk49_152MHz_c => clk49_152MHz_c, - lpp_top_lfr_wf_picker_ip_VCC => lpp_top_lfr_wf_picker_VCC, - data_shaping_SP0 => data_shaping_SP0, data_shaping_SP1 - => data_shaping_SP1, rstn => rstn, lclk_c => lclk_c); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity dcom_uart is - - port( data : out std_logic_vector(7 downto 0); - hwdata : in std_logic_vector(31 downto 24); - paddr : in std_logic_vector(3 downto 2); - pwdata_1 : in std_logic_vector(4 to 4); - prdata_5 : out std_logic; - prdata_0 : out std_logic; - state_i : in std_logic_vector(5 to 5); - psel_1 : in std_logic_vector(7 to 7); - pwdata : in std_logic_vector(17 downto 16); - un1_dcom0_16 : out std_logic; - un1_dcom0_13 : out std_logic; - un1_dcom0_12 : out std_logic; - un1_dcom0_11 : out std_logic; - un1_dcom0_15 : out std_logic; - un1_dcom0_14 : out std_logic; - un1_dcom0_17 : out std_logic; - un1_dcom0_10 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 0); - tcnt : out std_logic_vector(1 downto 0); - dsurx_c : in std_logic; - lclk_c : in std_logic; - N_335 : out std_logic; - un1_apbi_2 : in std_logic; - N_769 : in std_logic; - N_330 : out std_logic; - N_127 : out std_logic; - N_6455 : in std_logic; - N_331 : out std_logic; - N_336 : out std_logic; - N_334 : out std_logic; - N_333 : out std_logic; - N_332 : out std_logic; - N_6455_0 : in std_logic; - dsutx_c : out std_logic; - N_85 : out std_logic; - write : in std_logic; - thempty : out std_logic; - N_321 : in std_logic; - rdata60_1 : in std_logic; - N_86 : out std_logic; - rstn : in std_logic; - dready : out std_logic; - un1_apbi_0 : in std_logic; - N_78_0 : in std_logic - ); - -end dcom_uart; - -architecture DEF_ARCH of dcom_uart is - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXO5 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MAJ3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal N_61_1, N_61_0, \tcnt[1]\, \tcnt[0]\, N_136, - rxstate_0_sqmuxa, N_677, rxtick_0_0_a5, rxtick_0_0_a5_0, - tick, \rxclk[2]\, \scaler_1_0_iv_0_0[2]\, N_697, N_744, - \scaler_1_0_iv_0_0[12]\, N_716, \scaler_1_0_iv_0_0[11]\, - scaler_2_sqmuxa, \scaler[15]\, N_723, - \scaler_1_0_iv_0_1[10]\, scaler_0_sqmuxa_1, N_725, - \scaler_1_0_iv_0_0[9]\, N_728, \scaler_1_0_iv_0_0[8]\, - N_732, \scaler_1_0_iv_0_0[7]\, N_737, - \scaler_1_0_iv_0_1[5]\, \un1_dcom0[7]\, N_740, - \scaler_1_0_iv_0[0]\, \scaler_i_m_1[4]\, - \scaler_1_0_iv_0[1]\, \scaler[5]\, \apbi_i_m_0[51]\, - \scaler_1_0_iv_0[4]\, \scaler_i_m_1[8]\, - \scaler_1_0_iv_0[6]\, \scaler_i_m_1[10]\, - \scaler_1_0_iv_0[3]\, \scaler_i_m_1[7]\, - \scaler_1_0_iv_0[13]\, \scaler_i_m_0[17]\, - \scaler_1_0_iv_0_0[16]\, \scaler_1_0_iv_1[17]\, - \scaler_i_m[17]\, \brate_1_iv_0[14]\, brate_1_sqmuxa, - brate_3_sqmuxa_i, \brate_1_iv_0[15]\, \brate_1_iv_0[16]\, - \brate_1_iv_0[17]\, \scaler_1_0_iv_0[14]\, - \brate_i_m[14]\, \brate_1_iv_0[0]\, brate_0_sqmuxa_1_i, - \scaler[4]\, \apbi_i_m[50]\, \brate_1_iv_0_0[4]\, N_78, - \brate_1_iv_0_0[8]\, N_706, \brate_1_iv_0_0[10]\, - \scaler[14]\, N_82, \brate_1_iv_0_0[12]\, \scaler[16]\, - N_707, \brate_1_iv_0[3]\, \scaler[7]\, \apbi_i_m[53]\, - \brate_1_iv_0[5]\, \scaler[9]\, \apbi_i_m[55]\, - \brate_1_iv_0[7]\, \scaler[11]\, \apbi_i_m[57]\, - \brate_1_iv_0[9]\, \scaler_i_m[13]\, \brate_1_iv_0[11]\, - \apbi_i_m[61]\, \brate_1_iv_0[13]\, \scaler_i_m_1[17]\, - brate_i_m_14_m1_e_0, \tshift_1_0_0[0]\, txtick, N_138_i, - N_123, txtick_0_i_0, \txclk[2]\, rxen_0_sqmuxa_0, - un1_apbi_1, \rxstate_ns_0_0[0]\, N_640_2, - \rxstate_ns_0_a3_0_0[0]\, N_639, tcnt8_NE_10, tcnt8_NE_1, - tcnt8_NE_0, tcnt8_NE_6, tcnt8_NE_9, tcnt8_6_i, N_56_i_i, - tcnt8_NE_5, tcnt8_NE_8, tcnt8_3_i, tcnt8_1_i, tcnt8_NE_3, - N_58_i_i, tcnt8_9_i, \un1_dcom0[11]\, tcnt8_8_i, - \scaler[8]\, \un1_dcom0[10]\, N_59_i_i, \un1_dcom0[6]\, - N_54_i_i, dready_2_0, thempty_1_sqmuxa_1_i_o2_0, - \txstate[0]\, \txstate[1]\, rshift_0_sqmuxa_0_a2_0_0, - \rxstate[0]\, \rxstate[1]\, \tshift_1_0_a2_6[0]\, - \tshift[9]\, \tshift[8]\, \tshift_1_0_a2_4[0]\, - \tshift_1_0_a2_5[0]\, \tshift[5]\, \tshift[4]\, - \tshift_1_0_a2_2[0]\, \tshift[3]\, \tshift[2]\, - \tshift[6]\, \tshift[7]\, break10_5, break10_3, - \rshift[5]\, \rshift[4]\, break10_4, break10_1, - \rshift[1]\, \rshift[0]\, \rshift[6]\, \rshift[7]\, - \rshift[2]\, \rshift[3]\, rxtick, N_629, - \scaler_1_0_iv[17]\, \apbi_i_m[67]\, \scaler_1_0_iv[14]\, - \scaler_i_m[14]\, \scaler_1_0_iv[13]\, \scaler_i_m_0[13]\, - \brate_i_m[13]\, \scaler_1_0_iv[3]\, \scaler_i_m[3]\, - \brate_i_m[3]\, \scaler_1_0_iv[6]\, \scaler_i_m[6]\, - \brate_i_m[6]\, \scaler_1_0_iv[4]\, \scaler_i_m[4]\, - \brate_i_m[4]\, \scaler_1_0_iv[1]\, \scaler_i_m[1]\, - \brate_i_m[1]\, \scaler_1_0_iv[0]\, \scaler_i_m[0]\, - \brate_i_m[0]\, \scaler_1[2]\, N_742, N_743, - \scaler_1_0_iv[5]\, N_741, N_122, \scaler_1_0_iv[7]\, - N_736, N_738, \scaler_1_0_iv[8]\, N_733, N_734, - \scaler_1_0_iv[9]\, N_729, N_730, \scaler_1_0_iv[10]\, - N_724, N_727, \scaler_1_0_iv[11]\, N_721, N_722, - \scaler_1_0_iv[12]\, N_717, N_718, \scaler_1_0_iv[15]\, - N_715, \scaler_RNO_1[15]\, \scaler_1_0_iv[16]\, N_710, - N_711, \tshift_1[0]\, N_124, \brate_1_iv[13]\, - \scaler[13]\, brate_1_sqmuxa_4, \brate_1_iv[11]\, - \brate_1_iv[9]\, \brate_1_iv[7]\, \brate_1_iv[6]\, - \scaler_i_m[10]\, \apbi_i_m[56]\, \scaler_i_m_0[6]\, - \brate_1_iv[5]\, \brate_1_iv[3]\, \scaler[3]\, - \brate_1_iv[1]\, \scaler_i_m[5]\, \apbi_i_m[51]\, - \scaler_i_m_0[1]\, \brate_1_iv[12]\, \scaler[12]\, - \brate_1_iv[10]\, \scaler[10]\, \brate_1_iv[8]\, - \brate_1_iv[4]\, N_7, break_0_sqmuxa, N_701, - frame_0_sqmuxa, tcnt_1_sqmuxa_3, \tcnt_1_sqmuxa[0]\, - rxen_1_sqmuxa, tcnt_0_sqmuxa_2, \brate_1[17]\, - \scaler[17]\, \brate_1[16]\, \brate_1[15]\, \brate_1[14]\, - tcnt_0_sqmuxa, fedge_0_sqmuxa, scaler_2_sqmuxa_1, rxdb_3, - un1_scaler, rxen_0_sqmuxa_1, brate_0_sqmuxa, enable, - scaler_4_sqmuxa, \scaler7[0]\, tcnt_1_sqmuxa, tcnt9, - brate2, fedge, \rxdb[1]\, \rxdb[0]\, N_650, N_114, N_139, - \tshift_RNO[8]\, N_110, N_109, N_108, \tshift_RNO[7]\, - N_107, N_106, N_105, \tshift_RNO[6]\, N_104, N_103, N_102, - \tshift_RNO[5]\, N_101, N_100, N_99, \tshift_RNO[4]\, - N_98, N_97, N_96, N_31, N_95, N_94, N_93, N_29, N_92, - N_91, N_90, N_690, N_112, txtick_RNO, CO1, N_64, dready_2, - N_628, rsempty_1_sqmuxa, dready_0_sqmuxa, \dready\, - rsempty, N_622, break10_i_0, N_27, N_89, N_88, N_87, - \brate_1_iv[2]\, N_75, N_73, N_74, N_59, \brate_1_iv[0]\, - \scaler[0]\, scaler_0_sqmuxa, \scaler_RNO_3[15]\, - \scaler_0[15]\, \scaler_2_sqmuxa[0]\, \scaler_RNO_2[15]\, - \un1_dcom0[17]\, N_400, fedge_1_sqmuxa, N_419, break, - break_1, N_427, frame, frame_1, N_9, N_428, rxen_1, - rxen_1_sqmuxa_1, N_437, N_560, N_560s, N_561, N_561s, - N_439, rshift_0_sqmuxa, N_440, N_441, N_442, N_443, N_444, - N_445, N_446, N_402, \un1_dcom0[3]\, brate_2_sqmuxa, - N_404, \un1_dcom0[5]\, N_405, N_406, N_407, - \un1_dcom0[8]\, N_408, \un1_dcom0[9]\, N_409, N_410, - N_411, \un1_dcom0[12]\, N_412, \un1_dcom0[13]\, N_413, - N_414, N_415, \un1_dcom0[16]\, N_416, N_417, N_418, - \un1_dcom0[19]\, \un1_dcom0[14]\, N_329, N_77, N_126, - \thold[1]\, \thold[2]\, \thold[3]\, \thold[4]\, - \thold[5]\, \thold[6]\, \thold[7]\, \tshift[1]\, N_8, - \rxf[2]\, \rxf[4]\, \rxf[3]\, \tshift_10_0_iv[9]\, - \rxf_RNO[2]\, \rxf[1]\, N_62, \rxf_RNO[3]\, \rxf_RNO[4]\, - rxdb_1, \brate13[0]\, brate_1_sqmuxa_2, rxen_0_sqmuxa_2, - brate_1_sqmuxa_3, \scaler_0[17]\, tick_2, scaler_1_sqmuxa, - \apbi_m[51]_net_1\, rxen_RNO, frame_RNO, break_RNO, - fedge_RNO, thempty_RNO, \brate_RNO[1]\, \brate_RNO[3]\, - \brate_RNO[4]\, \brate_RNO[5]\, \brate_RNO[6]\, - \brate_RNO[7]\, \brate_RNO[8]\, \brate_RNO[9]\, - \brate_RNO[10]\, \brate_RNO[11]\, \brate_RNO[12]\, - \brate_RNO[13]\, \brate_RNO[14]\, \brate_RNO[15]\, - \brate_RNO[16]\, \brate_RNO[17]\, \scaler_0[16]\, - \un1_dcom0[18]\, \scaler_0[12]\, \scaler_0[11]\, - \scaler_0[10]\, \scaler_0[9]\, \scaler_0[8]\, - \scaler_0[7]\, \scaler_0[5]\, \scaler[6]\, \scaler[2]\, - \un1_dcom0[4]\, N_702_1, \scaler[1]\, \scaler_0[3]\, - \un1_dcom0[15]\, \scaler_0[13]\, \scaler_0[14]\, N_630, - N_328, \un1_dcom0[2]\, ovf, \scaler_0[1]\, \scaler_0[4]\, - \scaler_0[6]\, rxdb_4, \rshift_RNO[0]\, \rshift_RNO[1]\, - \rshift_RNO[2]\, \rshift_RNO[3]\, \rshift_RNO[4]\, - \rshift_RNO[5]\, \rshift_RNO[6]\, \rshift_RNO[7]\, N_15, - N_21_1, N_19, N_680_i_1, \txclk[1]\, N_21, N_23, N_133, - \rxclk_1[1]\, \rxclk[0]\, \rxclk[1]\, \rxclk_1[0]\, - rxclk_1_sqmuxa_1, rsempty_0_sqmuxa_1_1, dready_RNO, - dready_0_sqmuxa_0, ovf_0_sqmuxa, rsempty_2, N_627, - ovf_RNO, N_438, N_642, rxstate_1, \rxstate_nss[1]\, - \rxstate_nss[0]\, N_420, rsempty_1, rsempty_RNO, - rsempty_0_sqmuxa_2, rsempty_RNO_4, \thempty\, - \scaler_0[2]\, \brate_RNO[2]\, N_403, tsempty_RNO, N_447, - \thold[0]\, N_79, tsempty, \N_127\, N_61, \tcnt_RNO[1]\, - \tcnt_0_sqmuxa_1_m[0]\, \tcnt_RNO[0]\, - \tcnt_0_sqmuxa_1_m[1]\, CO0, tcnt_0_sqmuxa_1, N_401, - \brate_RNO[0]\, \dsutx_c\, \rxf[0]\, \DWACT_COMP0_E[1]\, - \DWACT_COMP0_E[2]\, \DWACT_COMP0_E[0]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, N_21_0, N_20, N_19_0, - N_16, N_18, N_17, N_15_0, N_12, N_13, N_14, - \ACT_LT3_E[3]\, \ACT_LT3_E[4]\, \ACT_LT3_E[5]\, - \ACT_LT3_E[0]\, \ACT_LT3_E[1]\, \ACT_LT3_E[2]\, - \DWACT_BL_EQUAL_0_E[2]\, \DWACT_BL_EQUAL_0_E[1]\, - \DWACT_BL_EQUAL_0_E[0]\, - \DWACT_CMPLE_PO0_DWACT_COMP0_E[1]\, - \DWACT_CMPLE_PO0_DWACT_COMP0_E[2]\, - \DWACT_CMPLE_PO0_DWACT_COMP0_E[0]\, \ACT_LT4_E[3]\, - \ACT_LT4_E[6]\, \ACT_LT4_E[10]\, \ACT_LT4_E[7]\, - \ACT_LT4_E[8]\, \ACT_LT4_E[5]\, \ACT_LT4_E[4]\, - \ACT_LT4_E[0]\, \ACT_LT4_E[1]\, \ACT_LT4_E[2]\, - \ACT_LT2_E[0]\, \ACT_LT2_E[1]\, \ACT_LT2_E[2]\, - \DWACT_BL_EQUAL_0_E_0[1]\, \DWACT_BL_EQUAL_0_E_0[0]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, - \DWACT_BL_EQUAL_0_E[3]\, \DWACT_BL_EQUAL_0_E[4]\, - \DWACT_BL_EQUAL_0_E[5]\, \DWACT_BL_EQUAL_0_E_1[0]\, - \DWACT_BL_EQUAL_0_E_1[1]\, \DWACT_BL_EQUAL_0_E_0[2]\, - \DWACT_ADD_CI_0_pog_array_1_6[0]\, - \DWACT_ADD_CI_0_pog_array_0_13[0]\, - \DWACT_ADD_CI_0_pog_array_0_14[0]\, - \DWACT_ADD_CI_0_pog_array_2_1[0]\, - \DWACT_ADD_CI_0_pog_array_1_3[0]\, - \DWACT_ADD_CI_0_pog_array_1_4[0]\, - \DWACT_ADD_CI_0_pog_array_2_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_5[0]\, - \DWACT_ADD_CI_0_pog_array_0_11[0]\, - \DWACT_ADD_CI_0_pog_array_0_12[0]\, - \DWACT_ADD_CI_0_pog_array_1_2[0]\, - \DWACT_ADD_CI_0_pog_array_0_5[0]\, - \DWACT_ADD_CI_0_pog_array_0_6[0]\, - \DWACT_ADD_CI_0_pog_array_0_9[0]\, - \DWACT_ADD_CI_0_pog_array_0_10[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_pog_array_0_3[0]\, - \DWACT_ADD_CI_0_pog_array_0_4[0]\, - \DWACT_ADD_CI_0_pog_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_0_7[0]\, - \DWACT_ADD_CI_0_pog_array_0_8[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_pog_array_0_1[0]\, - \DWACT_ADD_CI_0_pog_array_0_2[0]\, - \DWACT_ADD_CI_0_pog_array_3[0]\, - \DWACT_ADD_CI_0_g_array_12_7[0]\, - \DWACT_ADD_CI_0_pog_array_0_15[0]\, - \DWACT_ADD_CI_0_g_array_4[0]\, - \DWACT_ADD_CI_0_g_array_0_16[0]\, - \DWACT_ADD_CI_0_g_array_11_2[0]\, - \DWACT_ADD_CI_0_g_array_10[0]\, - \DWACT_ADD_CI_0_g_array_1_6[0]\, - \DWACT_ADD_CI_0_g_array_12[0]\, - \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_g_array_0_2[0]\, - \DWACT_ADD_CI_0_g_array_12_5[0]\, - \DWACT_ADD_CI_0_g_array_0_12[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_g_array_1_2[0]\, - \DWACT_ADD_CI_0_g_array_2_1[0]\, - \DWACT_ADD_CI_0_g_array_1_3[0]\, - \DWACT_ADD_CI_0_g_array_12_4[0]\, - \DWACT_ADD_CI_0_g_array_11_1[0]\, - \DWACT_ADD_CI_0_g_array_0_10[0]\, - \DWACT_ADD_CI_0_g_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_3[0]\, - \DWACT_ADD_CI_0_g_array_3_1[0]\, - \DWACT_ADD_CI_0_g_array_12_3[0]\, - \DWACT_ADD_CI_0_g_array_0_8[0]\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, - \DWACT_ADD_CI_0_g_array_0_6[0]\, - \DWACT_ADD_CI_0_g_array_2_2[0]\, - \DWACT_ADD_CI_0_g_array_2_3[0]\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, - \DWACT_ADD_CI_0_g_array_0_4[0]\, - \DWACT_ADD_CI_0_g_array_1_4[0]\, - \DWACT_ADD_CI_0_g_array_1_5[0]\, - \DWACT_ADD_CI_0_g_array_1_7[0]\, - \DWACT_ADD_CI_0_g_array_0_14[0]\, - \DWACT_ADD_CI_0_g_array_0_15[0]\, - \DWACT_ADD_CI_0_g_array_12_6[0]\, - \DWACT_ADD_CI_0_g_array_0_7[0]\, - \DWACT_ADD_CI_0_g_array_0_13[0]\, - \DWACT_ADD_CI_0_g_array_0_5[0]\, - \DWACT_ADD_CI_0_g_array_0_11[0]\, - \DWACT_ADD_CI_0_g_array_0_3[0]\, - \DWACT_ADD_CI_0_g_array_0_9[0]\, - \DWACT_ADD_CI_0_pog_array_0[0]\, - \DWACT_ADD_CI_0_g_array_0_1[0]\, - \DWACT_ADD_CI_0_partial_sum[17]\, - \DWACT_ADD_CI_0_partial_sum[10]\, - \DWACT_ADD_CI_0_partial_sum[3]\, - \DWACT_ADD_CI_0_partial_sum[16]\, - \DWACT_ADD_CI_0_partial_sum[9]\, - \DWACT_ADD_CI_0_partial_sum[8]\, - \DWACT_ADD_CI_0_partial_sum[2]\, - \DWACT_ADD_CI_0_partial_sum[7]\, - \DWACT_ADD_CI_0_partial_sum[15]\, - \DWACT_ADD_CI_0_partial_sum[6]\, - \DWACT_ADD_CI_0_partial_sum[14]\, - \DWACT_ADD_CI_0_partial_sum[5]\, - \DWACT_ADD_CI_0_partial_sum[1]\, - \DWACT_ADD_CI_0_partial_sum[4]\, - \DWACT_ADD_CI_0_partial_sum[12]\, - \DWACT_ADD_CI_0_partial_sum[13]\, - \DWACT_ADD_CI_0_partial_sum[11]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - -begin - - un1_dcom0_16 <= \un1_dcom0[18]\; - un1_dcom0_13 <= \un1_dcom0[15]\; - un1_dcom0_12 <= \un1_dcom0[14]\; - un1_dcom0_11 <= \un1_dcom0[13]\; - un1_dcom0_15 <= \un1_dcom0[17]\; - un1_dcom0_14 <= \un1_dcom0[16]\; - un1_dcom0_17 <= \un1_dcom0[19]\; - un1_dcom0_10 <= \un1_dcom0[12]\; - tcnt(1) <= \tcnt[1]\; - tcnt(0) <= \tcnt[0]\; - N_127 <= \N_127\; - dsutx_c <= \dsutx_c\; - thempty <= \thempty\; - dready <= \dready\; - - \r.scaler_RNO_3[13]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[17]\, Y => - \scaler_i_m_0[17]\); - - scaler_I_89 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_4[0]\, B => - \DWACT_ADD_CI_0_g_array_1_4[0]\, C => - \DWACT_ADD_CI_0_g_array_1_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_2_2[0]\); - - \r.brate_RNI09O8[17]\ : XNOR2 - port map(A => \un1_dcom0[19]\, B => \scaler[17]\, Y => - N_59_i_i); - - \r.tshift_RNO_0[4]\ : NOR2 - port map(A => \thold[3]\, B => N_64, Y => N_98); - - \r.rsempty_RNO_2\ : OR2B - port map(A => N_629, B => N_622, Y => rxstate_1); - - scaler_I_70 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[9]\, B => - \DWACT_ADD_CI_0_g_array_12_3[0]\, Y => \scaler_0[9]\); - - \r.dready_RNICJV3\ : NOR2B - port map(A => state_i(5), B => \dready\, Y => dready_2_0); - - \r.brate_RNI4Q3D[4]\ : XA1A - port map(A => \scaler[4]\, B => \un1_dcom0[6]\, C => - N_54_i_i, Y => tcnt8_NE_0); - - \uartop.op_gt.v.brate2_0_I_9\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\, B => - \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\, Y => - \DWACT_COMP0_E[1]\); - - \r.brate_RNI8UT7[0]\ : MX2 - port map(A => \dready\, B => \un1_dcom0[2]\, S => N_6455_0, - Y => N_328); - - \r.brate_RNO_1[15]\ : AO1C - port map(A => brate_1_sqmuxa_4, B => \scaler[15]\, C => - \brate_1_iv_0[15]\, Y => \brate_1[15]\); - - \r.scaler_RNO[1]\ : NOR3 - port map(A => \scaler_i_m[1]\, B => \brate_i_m[1]\, C => - \scaler_1_0_iv_0[1]\, Y => \scaler_1_0_iv[1]\); - - \r.tshift_RNO_1[6]\ : NOR2 - port map(A => \tshift[7]\, B => N_77, Y => N_103); - - \r.scaler[2]\ : DFN1E0 - port map(D => \scaler_1[2]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler_0[2]\); - - \r.rxf_RNO[4]\ : MX2 - port map(A => \rxf[4]\, B => \rxf[3]\, S => N_62, Y => - \rxf_RNO[4]\); - - scaler_I_9 : AND2 - port map(A => \scaler[3]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_3[0]\); - - \r.brate[9]\ : DFN1 - port map(D => \brate_RNO[9]\, CLK => lclk_c, Q => - \un1_dcom0[11]\); - - \r.rxdb_RNITI9[1]\ : OR2A - port map(A => \rxdb[1]\, B => \rxdb[0]\, Y => N_630); - - \r.txstate_RNO_0[1]\ : AXOI5 - port map(A => N_139, B => txtick, C => \txstate[1]\, Y => - N_561); - - \r.rxdb[1]\ : DFN1 - port map(D => \rxdb[0]\, CLK => lclk_c, Q => \rxdb[1]\); - - \r.scaler_RNO_2[7]\ : AO1D - port map(A => N_697, B => pwdata_0(7), C => N_737, Y => - \scaler_1_0_iv_0_0[7]\); - - \r.tcnt_RNO[1]\ : OA1 - port map(A => \apbi_m[51]_net_1\, B => - \tcnt_0_sqmuxa_1_m[0]\, C => rstn, Y => \tcnt_RNO[1]\); - - \r.break_RNO_2\ : OR3 - port map(A => break_0_sqmuxa, B => N_701, C => - frame_0_sqmuxa, Y => N_7); - - \r.txstate_RNO_0[0]\ : MX2 - port map(A => \txstate[0]\, B => N_650, S => txtick, Y => - N_560); - - scaler_I_40 : XOR2 - port map(A => \scaler[17]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[17]\); - - \r.tcnt_RNI73NE[1]\ : OR2A - port map(A => \tcnt[1]\, B => \tcnt[0]\, Y => - rxen_0_sqmuxa_0); - - \r.brate_RNO_0[12]\ : MX2 - port map(A => \brate_1_iv[12]\, B => \un1_dcom0[14]\, S => - brate_2_sqmuxa, Y => N_413); - - \uartop.op_gt.v.brate2_0_I_52\ : AO1 - port map(A => \DWACT_CMPLE_PO0_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO0_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO0_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[0]\); - - \r.scaler_RNO_3[10]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[10]\, Y => - N_725); - - \r.scaler_RNO[4]\ : NOR3 - port map(A => \scaler_i_m[4]\, B => \brate_i_m[4]\, C => - \scaler_1_0_iv_0[4]\, Y => \scaler_1_0_iv[4]\); - - \r.rxen_RNI4SKBP\ : OR2B - port map(A => scaler_0_sqmuxa, B => brate_0_sqmuxa, Y => - scaler_0_sqmuxa_1); - - \r.brate_RNO_3[12]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(12), Y => N_707); - - \r.brate[10]\ : DFN1 - port map(D => \brate_RNO[10]\, CLK => lclk_c, Q => - \un1_dcom0[12]\); - - \r.rxen_RNI30QL3\ : NOR3B - port map(A => \scaler7[0]\, B => brate_0_sqmuxa, C => - enable, Y => scaler_4_sqmuxa); - - \uartop.op_gt.v.brate2_0_I_38\ : AOI1A - port map(A => \ACT_LT4_E[0]\, B => \ACT_LT4_E[1]\, C => - \ACT_LT4_E[2]\, Y => \ACT_LT4_E[3]\); - - \r.brate[4]\ : DFN1 - port map(D => \brate_RNO[4]\, CLK => lclk_c, Q => - \un1_dcom0[6]\); - - scaler_I_110 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_5[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_6[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_2[0]\); - - \r.rshift_RNO_0[1]\ : MX2 - port map(A => \rshift[1]\, B => \rshift[2]\, S => - rshift_0_sqmuxa, Y => N_440); - - \r.brate_RNI84ES[5]\ : NOR3C - port map(A => tcnt8_3_i, B => tcnt8_1_i, C => tcnt8_NE_3, Y - => tcnt8_NE_8); - - \r.scaler_RNO_0[8]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[8]\, Y => - N_733); - - \r.txclk_RNO[1]\ : XA1B - port map(A => N_680_i_1, B => \txclk[1]\, C => N_21_1, Y - => N_19); - - \r.rxen_RNO_0\ : MX2 - port map(A => rxen_1, B => enable, S => rxen_1_sqmuxa_1, Y - => N_428); - - scaler_I_35 : XOR2 - port map(A => \scaler[7]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_6[0]\); - - \r.scaler_RNO[8]\ : NOR3 - port map(A => N_733, B => N_734, C => - \scaler_1_0_iv_0_0[8]\, Y => \scaler_1_0_iv[8]\); - - scaler_I_73 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[10]\, B => - \DWACT_ADD_CI_0_g_array_11_1[0]\, Y => \scaler_0[10]\); - - \r.txstate_RNI6D5T[1]\ : OR2B - port map(A => rstn, B => N_64, Y => N_21_1); - - \r.thempty_RNO_0\ : OA1A - port map(A => N_64, B => \thempty\, C => write, Y => N_437); - - scaler_I_11 : AND2 - port map(A => \scaler[4]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_4[0]\); - - \r.scaler[0]\ : DFN1E0 - port map(D => \scaler_1_0_iv[0]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[0]\); - - \r.rxf[4]\ : DFN1 - port map(D => \rxf_RNO[4]\, CLK => lclk_c, Q => \rxf[4]\); - - scaler_I_80 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_10[0]\, B => - \DWACT_ADD_CI_0_g_array_0_10[0]\, C => - \DWACT_ADD_CI_0_g_array_0_11[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_5[0]\); - - \r.scaler[6]\ : DFN1E0 - port map(D => \scaler_1_0_iv[6]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[6]\); - - \r.brate_RNI02AF[9]\ : XA1A - port map(A => \scaler[9]\, B => \un1_dcom0[11]\, C => - tcnt8_8_i, Y => tcnt8_NE_3); - - \r.brate_RNIOON8[13]\ : XNOR2 - port map(A => \un1_dcom0[15]\, B => \scaler[13]\, Y => - tcnt8_9_i); - - \r.brate_RNIG5H6[5]\ : NOR2B - port map(A => \un1_dcom0[7]\, B => \N_127\, Y => prdata_5); - - \r.brate_RNO_2[0]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[4]\, C => - \apbi_i_m[50]\, Y => \brate_1_iv_0[0]\); - - \r.brate_RNO_1[4]\ : OA1B - port map(A => \scaler[4]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0_0[4]\, Y => \brate_1_iv[4]\); - - \r.brate_RNO_0[9]\ : MX2 - port map(A => \brate_1_iv[9]\, B => \un1_dcom0[11]\, S => - brate_2_sqmuxa, Y => N_410); - - \r.scaler_RNO_3[8]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[12]\, Y => - N_732); - - \r.brate_RNO_2[8]\ : AO1A - port map(A => pwdata_0(8), B => brate_1_sqmuxa, C => N_706, - Y => \brate_1_iv_0_0[8]\); - - \r.tick_RNICIQQ\ : NOR2 - port map(A => tick, B => N_133, Y => rxclk_1_sqmuxa_1); - - \r.brate_RNO_0[8]\ : MX2 - port map(A => \brate_1_iv[8]\, B => \un1_dcom0[10]\, S => - brate_2_sqmuxa, Y => N_409); - - \r.brate_RNO[1]\ : OR2A - port map(A => rstn, B => N_402, Y => \brate_RNO[1]\); - - scaler_I_18 : AND2 - port map(A => \scaler[1]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_1[0]\); - - \r.brate_RNO[17]\ : OR2A - port map(A => rstn, B => N_418, Y => \brate_RNO[17]\); - - \r.tshift_RNO[9]\ : OA1A - port map(A => N_77, B => \tshift[9]\, C => N_64, Y => - \tshift_10_0_iv[9]\); - - \r.brate_RNIOIU21[10]\ : NOR3C - port map(A => tcnt8_6_i, B => N_56_i_i, C => tcnt8_NE_5, Y - => tcnt8_NE_9); - - scaler_I_43 : XOR2 - port map(A => \scaler[13]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[13]\); - - \r.rxdb_RNI18AI[1]\ : NOR2A - port map(A => N_61_0, B => rxdb_1, Y => break_0_sqmuxa); - - \r.scaler_RNO_3[9]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[13]\, Y => - N_728); - - \r.brate_RNI6IUD1[4]\ : NOR3C - port map(A => tcnt8_NE_1, B => tcnt8_NE_0, C => tcnt8_NE_6, - Y => tcnt8_NE_10); - - \r.scaler_RNO_0[9]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[9]\, Y => - N_729); - - \r.brate[6]\ : DFN1 - port map(D => \brate_RNO[6]\, CLK => lclk_c, Q => - \un1_dcom0[8]\); - - \r.rsempty_RNIS9GD\ : OR3 - port map(A => \dready\, B => rsempty, C => N_622, Y => - dready_0_sqmuxa); - - \r.scaler_RNO[10]\ : NOR3 - port map(A => N_724, B => N_727, C => - \scaler_1_0_iv_0_1[10]\, Y => \scaler_1_0_iv[10]\); - - \r.scaler[9]\ : DFN1E0 - port map(D => \scaler_1_0_iv[9]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[9]\); - - \uartop.un1_apbi_1\ : NOR3A - port map(A => psel_1(7), B => N_78_0, C => un1_apbi_0, Y - => un1_apbi_1); - - \r.brate[2]\ : DFN1 - port map(D => \brate_RNO[2]\, CLK => lclk_c, Q => - \un1_dcom0[4]\); - - \r.txtick_RNO\ : NOR3C - port map(A => txtick_0_i_0, B => CO1, C => N_64, Y => - txtick_RNO); - - \v.frame_0_sqmuxa_0_a2\ : NOR3B - port map(A => N_769, B => un1_apbi_1, C => N_6455, Y => - frame_0_sqmuxa); - - scaler_I_7 : AND2 - port map(A => \scaler[16]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_16[0]\); - - scaler_I_19 : AND2 - port map(A => \scaler[8]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_8[0]\); - - \r.scaler_RNI05N2S[16]\ : NOR2A - port map(A => \scaler_0[17]\, B => \scaler[16]\, Y => - un1_scaler); - - scaler_I_66 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[15]\, B => - \DWACT_ADD_CI_0_g_array_12_6[0]\, Y => \scaler_0[15]\); - - scaler_I_34 : XOR2 - port map(A => \scaler[9]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_8[0]\); - - \r.rhold[4]\ : DFN1E1 - port map(D => \rshift[4]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(4)); - - \r.rhold[3]\ : DFN1E1 - port map(D => \rshift[3]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(3)); - - \r.tcnt_RNIKFPA4[1]\ : AO1D - port map(A => rxen_0_sqmuxa_0, B => tcnt9, C => N_61_0, Y - => brate_1_sqmuxa_2); - - \uartop.op_gt.v.brate2_0_I_44\ : AOI1A - port map(A => \ACT_LT4_E[7]\, B => \ACT_LT4_E[8]\, C => - \ACT_LT4_E[5]\, Y => \ACT_LT4_E[10]\); - - \r.scaler_RNO_3[5]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[5]\, Y => - N_740); - - \r.scaler_RNO_3[1]\ : NOR2 - port map(A => N_697, B => pwdata_0(1), Y => - \apbi_i_m_0[51]\); - - \r.rxdb_RNIQ4J3[1]\ : OR2B - port map(A => \rxdb[1]\, B => break, Y => rxdb_1); - - \r.scaler_RNO_1[9]\ : NOR2 - port map(A => \un1_dcom0[11]\, B => scaler_0_sqmuxa_1, Y - => N_730); - - \uartop.op_gt.v.brate2_0_I_27\ : AO1A - port map(A => \scaler[16]\, B => \un1_dcom0[18]\, C => - \un1_dcom0[19]\, Y => \ACT_LT2_E[2]\); - - \r.tshift_RNO_0[7]\ : NOR2 - port map(A => \thold[6]\, B => N_64, Y => N_107); - - \r.rsempty_RNO_0\ : MX2 - port map(A => rsempty, B => rsempty_1, S => rxstate_1, Y - => N_420); - - \r.rxdb_RNIACTG3[1]\ : NOR2 - port map(A => tcnt9, B => rxdb_3, Y => tcnt_0_sqmuxa); - - scaler_I_83 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_2[0]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, C => - \DWACT_ADD_CI_0_g_array_2_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_3[0]\); - - scaler_I_22 : XOR2 - port map(A => \scaler[15]\, B => N_61, Y => - \DWACT_ADD_CI_0_pog_array_0_14[0]\); - - \r.txclk_RNO_0[0]\ : OR2B - port map(A => N_680_i_1, B => N_64, Y => N_112); - - scaler_I_52 : XOR2 - port map(A => \scaler[10]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[10]\); - - \r.brate_RNO_2[5]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[9]\, C => - \apbi_i_m[55]\, Y => \brate_1_iv_0[5]\); - - \r.rshift_RNO_0[4]\ : MX2 - port map(A => \rshift[4]\, B => \rshift[5]\, S => - rshift_0_sqmuxa, Y => N_443); - - \r.scaler_RNO_2[6]\ : AO1D - port map(A => N_697, B => pwdata_0(6), C => - \scaler_i_m_1[10]\, Y => \scaler_1_0_iv_0[6]\); - - \r.rshift_RNO[5]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_444, Y => - \rshift_RNO[5]\); - - \un1_v.tcnt_0_sqmuxa_1_1_CO0\ : OR2B - port map(A => tcnt_0_sqmuxa_1, B => \tcnt[0]\, Y => CO0); - - \r.rxstate_RNI7QOB_1[0]\ : OR2 - port map(A => \rxstate[1]\, B => \rxstate[0]\, Y => N_622); - - \r.brate_RNO_2[9]\ : AO1A - port map(A => pwdata_0(9), B => brate_1_sqmuxa, C => - \scaler_i_m[13]\, Y => \brate_1_iv_0[9]\); - - \r.brate_RNI41I6[6]\ : XNOR2 - port map(A => \un1_dcom0[8]\, B => \scaler[6]\, Y => - N_54_i_i); - - \r.scaler_RNO_1[2]\ : OR2A - port map(A => \scaler[2]\, B => scaler_1_sqmuxa, Y => N_743); - - \apbi_m[51]\ : NOR2B - port map(A => rxen_1_sqmuxa, B => pwdata_0(1), Y => - \apbi_m[51]_net_1\); - - \r.txstate_RNO[0]\ : NOR2B - port map(A => rstn, B => N_560, Y => N_560s); - - \r.brate_RNO_3[4]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[8]\, Y => - N_78); - - scaler_I_100 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_11[0]\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, C => - \DWACT_ADD_CI_0_g_array_0_12[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_5[0]\); - - \r.rxstate_RNO[0]\ : AOI1B - port map(A => \rxstate_ns_0_0[0]\, B => rxstate_0_sqmuxa, C - => rstn, Y => \rxstate_nss[0]\); - - \r.scaler_RNO[0]\ : NOR3 - port map(A => \scaler_i_m[0]\, B => \brate_i_m[0]\, C => - \scaler_1_0_iv_0[0]\, Y => \scaler_1_0_iv[0]\); - - \r.frame_RNI2V0A\ : MX2 - port map(A => frame, B => \un1_dcom0[8]\, S => N_6455_0, Y - => N_333); - - \r.tshift_RNO[3]\ : NOR3 - port map(A => N_95, B => N_94, C => N_93, Y => N_31); - - \r.scaler_RNO_1[3]\ : NOR2 - port map(A => \un1_dcom0[5]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[3]\); - - \r.rxdb_RNI2MHSC[1]\ : OR3B - port map(A => tcnt9, B => brate2, C => rxdb_3, Y => - tcnt_1_sqmuxa); - - \r.txstate_RNICHPR[1]\ : OR2A - port map(A => thempty_1_sqmuxa_1_i_o2_0, B => N_59, Y => - N_64); - - \uartop.op_gt.v.brate2_0_I_20\ : AND2 - port map(A => \DWACT_BL_EQUAL_0_E_0[1]\, B => - \DWACT_BL_EQUAL_0_E_0[0]\, Y => - \DWACT_CMPLE_PO0_DWACT_COMP0_E[1]\); - - scaler_I_10 : AND2 - port map(A => \scaler[10]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_10[0]\); - - \r.rhold[0]\ : DFN1E1 - port map(D => \rshift[0]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(0)); - - \r.tshift_RNO_2[4]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[4]\, Y => - N_96); - - \r.txclk[2]\ : DFN1E1 - port map(D => N_21, CLK => lclk_c, E => N_15, Q => - \txclk[2]\); - - \r.brate[15]\ : DFN1 - port map(D => \brate_RNO[15]\, CLK => lclk_c, Q => - \un1_dcom0[17]\); - - \r.brate_RNO_4[2]\ : NOR2 - port map(A => brate_1_sqmuxa_4, B => \scaler_0[2]\, Y => - N_74); - - \r.scaler_RNO[14]\ : NOR3A - port map(A => scaler_2_sqmuxa, B => \scaler_1_0_iv_0[14]\, - C => \scaler_i_m[14]\, Y => \scaler_1_0_iv[14]\); - - \r.tshift_RNIUUEJ[2]\ : NOR3C - port map(A => \tshift[3]\, B => \tshift[2]\, C => - \txstate[0]\, Y => \tshift_1_0_a2_4[0]\); - - \r.scaler_RNO_3[7]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[11]\, Y => - N_737); - - \r.fedge_RNI8OIL\ : MX2A - port map(A => fedge, B => rxdb_1, S => N_61_0, Y => - \scaler7[0]\); - - \r.scaler_RNO_2[11]\ : AO1D - port map(A => scaler_2_sqmuxa, B => \scaler[15]\, C => - N_723, Y => \scaler_1_0_iv_0_0[11]\); - - \r.scaler_RNO_0[3]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[3]\, Y => - \scaler_i_m[3]\); - - \r.scaler_RNO_0[13]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[13]\, Y => - \scaler_i_m_0[13]\); - - \uartop.op_gt.v.brate2_0_I_84\ : AO1C - port map(A => \scaler[6]\, B => \un1_dcom0[8]\, C => N_12, - Y => N_18); - - \r.rxen_RNI0C1J\ : MX2C - port map(A => enable, B => N_328, S => rdata60_1, Y => - prdata_0); - - \uartop.op_gt.v.brate2_0_I_2\ : XNOR2 - port map(A => \scaler[15]\, B => \un1_dcom0[17]\, Y => - \DWACT_BL_EQUAL_0_E[3]\); - - \uartop.op_gt.v.brate2_0_I_40\ : NOR2A - port map(A => \un1_dcom0[17]\, B => \scaler[15]\, Y => - \ACT_LT4_E[5]\); - - \uartop.op_gt.v.brate2_0_I_71\ : AOI1A - port map(A => \ACT_LT3_E[3]\, B => \ACT_LT3_E[4]\, C => - \ACT_LT3_E[5]\, Y => \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\); - - \r.scaler_RNO_3[12]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[16]\, Y => - N_716); - - \r.brate_RNO_2[6]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[10]\, Y => - \scaler_i_m[10]\); - - \r.brate_RNO[15]\ : OR2A - port map(A => rstn, B => N_416, Y => \brate_RNO[15]\); - - \r.brate_RNO[13]\ : OR2A - port map(A => rstn, B => N_414, Y => \brate_RNO[13]\); - - \r.tsempty_RNO\ : OR2A - port map(A => rstn, B => N_447, Y => tsempty_RNO); - - \r.scaler_RNO_1[0]\ : NOR2 - port map(A => \un1_dcom0[2]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[0]\); - - \r.rhold[5]\ : DFN1E1 - port map(D => \rshift[5]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(5)); - - \uartop.op_gt.v.brate2_0_I_4\ : XNOR2 - port map(A => \scaler[17]\, B => \un1_dcom0[19]\, Y => - \DWACT_BL_EQUAL_0_E[5]\); - - \r.tcnt_RNICPDMD[1]\ : OR2 - port map(A => brate_1_sqmuxa_2, B => brate2, Y => - brate_1_sqmuxa_3); - - \r.scaler_RNO_1[8]\ : NOR2 - port map(A => \un1_dcom0[10]\, B => scaler_0_sqmuxa_1, Y - => N_734); - - \r.brate_RNI8PSD[9]\ : MX2 - port map(A => \tcnt[1]\, B => \un1_dcom0[11]\, S => - N_6455_0, Y => N_336); - - \uartop.op_gt.v.brate2_0_I_87\ : OA1A - port map(A => N_16, B => N_18, C => N_17, Y => N_21_0); - - \r.scaler_RNO_2[4]\ : AO1D - port map(A => N_697, B => pwdata_0(4), C => - \scaler_i_m_1[8]\, Y => \scaler_1_0_iv_0[4]\); - - \r.scaler_RNO_0[10]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[14]\, Y => - N_724); - - \r.scaler_RNO_0[0]\ : NOR2A - port map(A => \scaler[0]\, B => scaler_1_sqmuxa, Y => - \scaler_i_m[0]\); - - \r.rxf_RNO[3]\ : MX2 - port map(A => \rxf[3]\, B => \rxf[2]\, S => N_62, Y => - \rxf_RNO[3]\); - - \r.rxen_RNICNRV6\ : OR3B - port map(A => rxen_0_sqmuxa_1, B => brate_0_sqmuxa, C => - enable, Y => scaler_2_sqmuxa); - - \r.fedge\ : DFN1 - port map(D => fedge_RNO, CLK => lclk_c, Q => fedge); - - scaler_I_13 : AND2 - port map(A => \scaler[9]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_9[0]\); - - \r.ovf_RNO_0\ : MX2 - port map(A => ovf, B => pwdata_1(4), S => frame_0_sqmuxa, Y - => N_438); - - \r.thempty_RNO\ : OR2A - port map(A => rstn, B => N_437, Y => thempty_RNO); - - \r.frame_RNO_1\ : AO1 - port map(A => break10_i_0, B => N_702_1, C => pwdata_0(6), - Y => frame_1); - - \r.brate[8]\ : DFN1 - port map(D => \brate_RNO[8]\, CLK => lclk_c, Q => - \un1_dcom0[10]\); - - \r.rshift[5]\ : DFN1 - port map(D => \rshift_RNO[5]\, CLK => lclk_c, Q => - \rshift[5]\); - - un2_rxclk_1_SUM2_0 : AX1C - port map(A => \rxclk[0]\, B => \rxclk[1]\, C => \rxclk[2]\, - Y => N_677); - - \r.rshift_RNO[6]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_445, Y => - \rshift_RNO[6]\); - - scaler_I_72 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[3]\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => \scaler_0[3]\); - - scaler_I_25 : XOR2 - port map(A => \scaler[13]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_12[0]\); - - \r.rxstate[1]\ : DFN1 - port map(D => \rxstate_nss[1]\, CLK => lclk_c, Q => - \rxstate[1]\); - - \r.brate_RNO_0[5]\ : MX2 - port map(A => \brate_1_iv[5]\, B => \un1_dcom0[7]\, S => - brate_2_sqmuxa, Y => N_406); - - \r.tshift[5]\ : DFN1 - port map(D => \tshift_RNO[5]\, CLK => lclk_c, Q => - \tshift[5]\); - - \r.rxclk_RNO[0]\ : NOR2 - port map(A => \rxclk[0]\, B => N_133, Y => \rxclk_1[0]\); - - scaler_I_55 : XOR2 - port map(A => \scaler[9]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[9]\); - - \r.rsempty_RNO_1\ : MX2C - port map(A => rsempty_2, B => rsempty_0_sqmuxa_2, S => - rsempty_RNO_4, Y => rsempty_1); - - scaler_I_61 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[4]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => \scaler_0[4]\); - - GND_i : GND - port map(Y => \GND\); - - \r.rshift_RNO_0[7]\ : MX2 - port map(A => \rshift[7]\, B => \rxdb[0]\, S => - rshift_0_sqmuxa, Y => N_446); - - \r.brate_RNO_2[7]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[11]\, C => - \apbi_i_m[57]\, Y => \brate_1_iv_0[7]\); - - scaler_I_95 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_3[0]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, C => - \DWACT_ADD_CI_0_g_array_3_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_4[0]\); - - \r.rxf[1]\ : DFN1 - port map(D => \rxf[0]\, CLK => lclk_c, Q => \rxf[1]\); - - \r.tshift_RNO_1[5]\ : NOR2 - port map(A => \tshift[6]\, B => N_77, Y => N_100); - - scaler_I_68 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[2]\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => \scaler[2]\); - - \r.tcnt[0]\ : DFN1 - port map(D => \tcnt_RNO[0]\, CLK => lclk_c, Q => \tcnt[0]\); - - scaler_I_42 : XOR2 - port map(A => \scaler[5]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[5]\); - - \r.scaler_RNO_1[11]\ : NOR2 - port map(A => \un1_dcom0[13]\, B => scaler_0_sqmuxa_1, Y - => N_722); - - \r.rxstate_RNO_1[0]\ : OR2A - port map(A => rxtick, B => \rshift[0]\, Y => - \rxstate_ns_0_a3_0_0[0]\); - - \r.break_RNO_1\ : AO1 - port map(A => frame_0_sqmuxa, B => pwdata_0(3), C => N_701, - Y => break_1); - - \uartop.op_gt.v.brate2_0_I_80\ : NOR2A - port map(A => \un1_dcom0[6]\, B => \scaler[4]\, Y => N_14); - - \r.brate_RNO_3[1]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(1), Y => - \apbi_i_m[51]\); - - \uartop.op_gt.v.brate2_0_I_66\ : OR2A - port map(A => \un1_dcom0[12]\, B => \scaler[10]\, Y => - \ACT_LT3_E[1]\); - - \r.rxtick_RNI0M9D\ : OR3C - port map(A => \rxstate[1]\, B => \rxstate[0]\, C => rxtick, - Y => N_629); - - scaler_I_37 : XOR2 - port map(A => \scaler[8]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_7[0]\); - - \r.brate[11]\ : DFN1 - port map(D => \brate_RNO[11]\, CLK => lclk_c, Q => - \un1_dcom0[13]\); - - \r.frame_RNO_2\ : AO1 - port map(A => break10_i_0, B => N_702_1, C => - frame_0_sqmuxa, Y => N_9); - - \r.tshift[8]\ : DFN1 - port map(D => \tshift_RNO[8]\, CLK => lclk_c, Q => - \tshift[8]\); - - \r.rxclk_RNO[1]\ : XA1B - port map(A => \rxclk[0]\, B => \rxclk[1]\, C => N_133, Y - => \rxclk_1[1]\); - - \r.brate[17]\ : DFN1 - port map(D => \brate_RNO[17]\, CLK => lclk_c, Q => - \un1_dcom0[19]\); - - scaler_I_69 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[8]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, Y => \scaler_0[8]\); - - \r.scaler[7]\ : DFN1E0 - port map(D => \scaler_1_0_iv[7]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[7]\); - - \r.brate_RNO_0[4]\ : MX2 - port map(A => \brate_1_iv[4]\, B => \un1_dcom0[6]\, S => - brate_2_sqmuxa, Y => N_405); - - \uartop.op_gt.v.brate2_0_I_43\ : OR2A - port map(A => \scaler[15]\, B => \un1_dcom0[17]\, Y => - \ACT_LT4_E[8]\); - - \uartop.op_gt.v.brate2_0_I_28\ : AND3A - port map(A => \ACT_LT2_E[0]\, B => \ACT_LT2_E[1]\, C => - \ACT_LT2_E[2]\, Y => \DWACT_CMPLE_PO0_DWACT_COMP0_E[0]\); - - \r.scaler_RNO_0[7]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[7]\, Y => - N_736); - - \r.brate_RNIQSN8[14]\ : XNOR2 - port map(A => \un1_dcom0[16]\, B => \scaler[14]\, Y => - N_56_i_i); - - scaler_I_24 : XOR2 - port map(A => \scaler[6]\, B => N_61, Y => - \DWACT_ADD_CI_0_pog_array_0_5[0]\); - - \uartop.op_gt.v.brate2_0_I_8\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E[3]\, B => - \DWACT_BL_EQUAL_0_E[4]\, C => \DWACT_BL_EQUAL_0_E[5]\, Y - => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1]\); - - \r.scaler_RNO_3[14]\ : OR2 - port map(A => \un1_dcom0[16]\, B => brate_1_sqmuxa, Y => - brate_i_m_14_m1_e_0); - - scaler_I_54 : XOR2 - port map(A => \scaler[14]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[14]\); - - \r.brate_RNO_0[10]\ : MX2 - port map(A => \brate_1_iv[10]\, B => \un1_dcom0[12]\, S => - brate_2_sqmuxa, Y => N_411); - - \r.txclk[0]\ : DFN1E1 - port map(D => N_690, CLK => lclk_c, E => N_15, Q => - N_680_i_1); - - \r.rsempty_RNO\ : OR2A - port map(A => rstn, B => N_420, Y => rsempty_RNO); - - \r.brate_RNO[10]\ : OR2A - port map(A => rstn, B => N_411, Y => \brate_RNO[10]\); - - \r.scaler_RNO_3[6]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[10]\, Y => - \scaler_i_m_1[10]\); - - \r.scaler_RNO_0[17]\ : NOR2 - port map(A => N_697, B => pwdata(17), Y => \apbi_i_m[67]\); - - \r.brate_RNO_3[10]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(10), Y => N_82); - - \r.rxf[3]\ : DFN1 - port map(D => \rxf_RNO[3]\, CLK => lclk_c, Q => \rxf[3]\); - - scaler_I_82 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, C => - \DWACT_ADD_CI_0_g_array_1_4[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_1[0]\); - - \r.rxtick_0_0_a5_RNO\ : AND2 - port map(A => tick, B => \rxclk[2]\, Y => rxtick_0_0_a5_0); - - \r.rxdb_RNIEDED[0]\ : NOR2 - port map(A => \rxdb[0]\, B => N_629, Y => N_702_1); - - \r.rshift[0]\ : DFN1 - port map(D => \rshift_RNO[0]\, CLK => lclk_c, Q => - \rshift[0]\); - - \r.brate_RNO_1[0]\ : OA1B - port map(A => \scaler[0]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[0]\, Y => \brate_1_iv[0]\); - - \r.tshift[0]\ : DFN1 - port map(D => \tshift_1[0]\, CLK => lclk_c, Q => \dsutx_c\); - - \r.scaler_RNIBB0LS[16]\ : OR3A - port map(A => rxdb_3, B => N_61_0, C => un1_scaler, Y => - scaler_2_sqmuxa_1); - - \r.scaler_RNO_1[1]\ : NOR2 - port map(A => \un1_dcom0[3]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[1]\); - - \uartop.op_gt.v.brate2_0_I_65\ : NOR2A - port map(A => \un1_dcom0[11]\, B => \scaler[9]\, Y => - \ACT_LT3_E[0]\); - - \r.thempty\ : DFN1 - port map(D => thempty_RNO, CLK => lclk_c, Q => \thempty\); - - scaler_I_94 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_7[0]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, C => - \DWACT_ADD_CI_0_g_array_0_8[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_3[0]\); - - \r.rxen_RNIF7L0M1\ : OR2A - port map(A => brate_0_sqmuxa, B => \scaler_2_sqmuxa[0]\, Y - => scaler_1_sqmuxa); - - \r.thold[2]\ : DFN1E0 - port map(D => hwdata(26), CLK => lclk_c, E => write, Q => - \thold[2]\); - - \r.brate_RNO_0[6]\ : MX2 - port map(A => \brate_1_iv[6]\, B => \un1_dcom0[8]\, S => - brate_2_sqmuxa, Y => N_407); - - \r.rhold[6]\ : DFN1E1 - port map(D => \rshift[6]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(6)); - - \r.tshift_RNO_2[5]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[5]\, Y => - N_99); - - \r.brate_RNO_0[14]\ : MX2 - port map(A => \brate_1[14]\, B => \un1_dcom0[16]\, S => - brate_2_sqmuxa, Y => N_415); - - \r.tsempty_RNI6SR6\ : MX2C - port map(A => tsempty, B => \un1_dcom0[3]\, S => N_6455, Y - => N_329); - - \r.rxstate_RNI7QOB[0]\ : OR2A - port map(A => \rxstate[1]\, B => \rxstate[0]\, Y => N_640_2); - - \r.dready\ : DFN1 - port map(D => dready_RNO, CLK => lclk_c, Q => \dready\); - - \r.brate[0]\ : DFN1 - port map(D => \brate_RNO[0]\, CLK => lclk_c, Q => - \un1_dcom0[2]\); - - \r.tcnt_RNI73NE_0[1]\ : NOR2B - port map(A => \tcnt[1]\, B => \tcnt[0]\, Y => N_61_1); - - \r.tshift_RNO_2[6]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[6]\, Y => - N_102); - - \r.brate_RNO[0]\ : OR2A - port map(A => rstn, B => N_401, Y => \brate_RNO[0]\); - - scaler_I_106 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_7[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_8[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_3[0]\); - - \r.rxclk[2]\ : DFN1E0 - port map(D => N_23, CLK => lclk_c, E => rxclk_1_sqmuxa_1, Q - => \rxclk[2]\); - - \r.fedge_RNI7LV5S\ : OR2B - port map(A => un1_scaler, B => fedge, Y => fedge_0_sqmuxa); - - \r.tshift_RNO_2[3]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[3]\, Y => - N_93); - - \r.rxstate_RNO[1]\ : AOI1B - port map(A => N_642, B => N_628, C => rstn, Y => - \rxstate_nss[1]\); - - \r.tshift_RNIUJ6R[4]\ : NOR3C - port map(A => \tshift[5]\, B => \tshift[4]\, C => - \tshift_1_0_a2_2[0]\, Y => \tshift_1_0_a2_5[0]\); - - \r.rshift_RNO[2]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_441, Y => - \rshift_RNO[2]\); - - \r.brate_RNO_2[1]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[5]\, Y => - \scaler_i_m[5]\); - - \r.brate_RNO_1[3]\ : OA1B - port map(A => \scaler[3]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[3]\, Y => \brate_1_iv[3]\); - - \r.brate_RNO_2[11]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[15]\, C => - \apbi_i_m[61]\, Y => \brate_1_iv_0[11]\); - - scaler_I_75 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0[0]\, B => - \scaler[0]\, C => \DWACT_ADD_CI_0_g_array_0_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_1[0]\); - - scaler_I_113 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_1[0]\); - - \r.rxen\ : DFN1 - port map(D => rxen_RNO, CLK => lclk_c, Q => enable); - - \r.rxdb_RNIDCQB3[1]\ : OR2B - port map(A => break_0_sqmuxa, B => brate_0_sqmuxa, Y => - brate_3_sqmuxa_i); - - \r.brate_RNO_0[7]\ : MX2 - port map(A => \brate_1_iv[7]\, B => \un1_dcom0[9]\, S => - brate_2_sqmuxa, Y => N_408); - - \r.txtick\ : DFN1 - port map(D => txtick_RNO, CLK => lclk_c, Q => txtick); - - \r.scaler[10]\ : DFN1E0 - port map(D => \scaler_1_0_iv[10]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[10]\); - - \r.scaler_RNO[5]\ : NOR3 - port map(A => N_741, B => N_122, C => - \scaler_1_0_iv_0_1[5]\, Y => \scaler_1_0_iv[5]\); - - \r.scaler_RNO[13]\ : NOR3 - port map(A => \scaler_i_m_0[13]\, B => \brate_i_m[13]\, C - => \scaler_1_0_iv_0[13]\, Y => \scaler_1_0_iv[13]\); - - \uartop.op_gt.v.brate2_0_I_83\ : OA1A - port map(A => \scaler[7]\, B => \un1_dcom0[9]\, C => N_13, - Y => N_17); - - \r.brate_RNO_0[13]\ : MX2 - port map(A => \brate_1_iv[13]\, B => \un1_dcom0[15]\, S => - brate_2_sqmuxa, Y => N_414); - - \r.tshift_RNO[5]\ : NOR3 - port map(A => N_101, B => N_100, C => N_99, Y => - \tshift_RNO[5]\); - - \r.ovf_RNO_1\ : NOR2A - port map(A => rsempty_2, B => rxstate_0_sqmuxa, Y => - ovf_0_sqmuxa); - - \r.brate_RNO_3[13]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[17]\, Y => - \scaler_i_m_1[17]\); - - \r.brate_RNO_0[2]\ : MX2 - port map(A => \brate_1_iv[2]\, B => \un1_dcom0[4]\, S => - brate_2_sqmuxa, Y => N_403); - - scaler_I_45 : XOR2 - port map(A => \scaler[12]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[12]\); - - \r.rshift[3]\ : DFN1 - port map(D => \rshift_RNO[3]\, CLK => lclk_c, Q => - \rshift[3]\); - - \r.scaler_RNI9KDBM[15]\ : NOR2A - port map(A => \scaler_0[15]\, B => \scaler[15]\, Y => - tick_2); - - \r.tshift[3]\ : DFN1 - port map(D => N_31, CLK => lclk_c, Q => \tshift[3]\); - - \r.brate_RNO_0[15]\ : MX2 - port map(A => \brate_1[15]\, B => \un1_dcom0[17]\, S => - brate_2_sqmuxa, Y => N_416); - - \r.txclk_RNO[0]\ : NOR3C - port map(A => N_112, B => tick, C => rstn, Y => N_690); - - \r.scaler_RNO_1[4]\ : NOR2 - port map(A => \un1_dcom0[6]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[4]\); - - \uartop.op_gt.v.brate2_0_I_88\ : OA1 - port map(A => N_21_0, B => N_20, C => N_19_0, Y => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\); - - \r.rxdb_RNIAKP32[0]\ : NOR2A - port map(A => N_702_1, B => break10_i_0, Y => N_701); - - \r.tshift_RNO_1[1]\ : NOR2 - port map(A => \tshift[2]\, B => N_77, Y => N_88); - - \r.scaler_RNO_0[12]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[12]\, Y => - N_717); - - \r.rsempty_RNILFN1\ : NOR2A - port map(A => \dready\, B => rsempty, Y => rsempty_2); - - \r.tshift_RNO_0[0]\ : OA1A - port map(A => txtick, B => N_138_i, C => N_123, Y => - \tshift_1_0_0[0]\); - - \r.rxen_RNO\ : OA1 - port map(A => N_428, B => rxen_0_sqmuxa_2, C => rstn, Y => - rxen_RNO); - - \r.thold[4]\ : DFN1E0 - port map(D => hwdata(28), CLK => lclk_c, E => write, Q => - \thold[4]\); - - \r.tshift_RNO_0[6]\ : NOR2 - port map(A => \thold[5]\, B => N_64, Y => N_104); - - \r.txclk_RNO[2]\ : XA1B - port map(A => \txclk[2]\, B => CO1, C => N_21_1, Y => N_21); - - \r.rxf_RNO[2]\ : MX2 - port map(A => \rxf[2]\, B => \rxf[1]\, S => N_62, Y => - \rxf_RNO[2]\); - - scaler_I_74 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[17]\, B => - \DWACT_ADD_CI_0_g_array_12_7[0]\, Y => \scaler_0[17]\); - - \r.scaler_RNO_2[13]\ : AO1D - port map(A => N_697, B => pwdata_0(13), C => - \scaler_i_m_0[17]\, Y => \scaler_1_0_iv_0[13]\); - - \r.rhold[1]\ : DFN1E1 - port map(D => \rshift[1]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(1)); - - \r.scaler_RNO_3[2]\ : OR2A - port map(A => \un1_dcom0[4]\, B => scaler_0_sqmuxa_1, Y => - N_744); - - \r.brate_RNO[12]\ : OR2A - port map(A => rstn, B => N_413, Y => \brate_RNO[12]\); - - scaler_I_12 : AND2 - port map(A => \scaler_0[2]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_2[0]\); - - \r.fedge_RNO_0\ : AXO5 - port map(A => un1_scaler, B => fedge, C => fedge_1_sqmuxa, - Y => N_400); - - scaler_I_63 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[5]\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => \scaler_0[5]\); - - \r.scaler_RNO_0[1]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[1]\, Y => - \scaler_i_m[1]\); - - \r.scaler[12]\ : DFN1E0 - port map(D => \scaler_1_0_iv[12]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[12]\); - - scaler_I_85 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_6[0]\, B => - \DWACT_ADD_CI_0_g_array_0_6[0]\, C => - \DWACT_ADD_CI_0_g_array_0_7[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_3[0]\); - - scaler_I_36 : XOR2 - port map(A => \scaler[16]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_15[0]\); - - \r.rxtick_RNIE3OQ\ : OR2B - port map(A => N_628, B => N_627, Y => rshift_0_sqmuxa); - - \r.brate_RNO_1[11]\ : OA1B - port map(A => \scaler[11]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[11]\, Y => \brate_1_iv[11]\); - - \r.rshift_RNO[7]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_446, Y => - \rshift_RNO[7]\); - - \r.brate_RNO_2[16]\ : AOI1B - port map(A => brate_1_sqmuxa, B => pwdata(16), C => - brate_3_sqmuxa_i, Y => \brate_1_iv_0[16]\); - - \r.rxen_RNIDC5K\ : OR2B - port map(A => rstn, B => rxstate_0_sqmuxa, Y => N_133); - - \r.rsempty_RNINR9C1\ : OAI1 - port map(A => N_629, B => rsempty_0_sqmuxa_1_1, C => - dready_0_sqmuxa, Y => dready_0_sqmuxa_0); - - \r.brate_RNO[4]\ : OR2A - port map(A => rstn, B => N_405, Y => \brate_RNO[4]\); - - \r.brate_RNO_2[17]\ : AOI1B - port map(A => brate_1_sqmuxa, B => pwdata(17), C => - brate_3_sqmuxa_i, Y => \brate_1_iv_0[17]\); - - \r.brate_RNI2TH6[5]\ : XNOR2 - port map(A => \un1_dcom0[7]\, B => \scaler[5]\, Y => - tcnt8_1_i); - - \uartop.op_gt.v.brate2_0_I_79\ : OR2A - port map(A => \scaler[6]\, B => \un1_dcom0[8]\, Y => N_13); - - \r.brate_RNO_3[3]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(3), Y => - \apbi_i_m[53]\); - - \r.tcnt[1]\ : DFN1 - port map(D => \tcnt_RNO[1]\, CLK => lclk_c, Q => \tcnt[1]\); - - \r.scaler_RNO[12]\ : NOR3 - port map(A => N_717, B => N_718, C => - \scaler_1_0_iv_0_0[12]\, Y => \scaler_1_0_iv[12]\); - - \r.brate_RNO[8]\ : OR2A - port map(A => rstn, B => N_409, Y => \brate_RNO[8]\); - - \r.rxstate_RNO_0[1]\ : AO1B - port map(A => rxtick, B => \rxstate[0]\, C => \rxstate[1]\, - Y => N_642); - - \r.thold[7]\ : DFN1E0 - port map(D => hwdata(31), CLK => lclk_c, E => write, Q => - \thold[7]\); - - \r.break_RNO\ : NOR2B - port map(A => rstn, B => N_419, Y => break_RNO); - - scaler_I_112 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_5[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_6[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_2[0]\); - - \r.txclk[1]\ : DFN1E1 - port map(D => N_19, CLK => lclk_c, E => N_15, Q => - \txclk[1]\); - - \r.thold[3]\ : DFN1E0 - port map(D => hwdata(27), CLK => lclk_c, E => write, Q => - \thold[3]\); - - \r.scaler_RNO_2[10]\ : AO1D - port map(A => \un1_dcom0[12]\, B => scaler_0_sqmuxa_1, C - => N_725, Y => \scaler_1_0_iv_0_1[10]\); - - \r.fedge_RNO\ : NOR2B - port map(A => rstn, B => N_400, Y => fedge_RNO); - - \r.brate_RNI6LSD[8]\ : MX2 - port map(A => \tcnt[0]\, B => \un1_dcom0[10]\, S => N_6455, - Y => N_335); - - \r.scaler[11]\ : DFN1E0 - port map(D => \scaler_1_0_iv[11]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[11]\); - - \uartop.op_gt.v.brate2_0_I_36\ : OR2A - port map(A => \un1_dcom0[15]\, B => \scaler[13]\, Y => - \ACT_LT4_E[1]\); - - \r.scaler_RNO_3[15]\ : OR3 - port map(A => \scaler_0[15]\, B => brate_1_sqmuxa, C => - \scaler_2_sqmuxa[0]\, Y => \scaler_RNO_3[15]\); - - scaler_I_114 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_13[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_14[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_6[0]\); - - \r.brate_RNIMKN8[12]\ : XNOR2 - port map(A => \un1_dcom0[14]\, B => \scaler[12]\, Y => - tcnt8_8_i); - - \r.scaler_RNO[15]\ : NOR3A - port map(A => scaler_2_sqmuxa, B => N_715, C => - \scaler_RNO_1[15]\, Y => \scaler_1_0_iv[15]\); - - \r.rxdb_RNIT8Q5H[1]\ : AOI1B - port map(A => brate_1_sqmuxa_3, B => \brate13[0]\, C => - brate_0_sqmuxa, Y => brate_2_sqmuxa); - - scaler_I_6 : AND2 - port map(A => \scaler[6]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_6[0]\); - - scaler_I_103 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_15[0]\, B => - \DWACT_ADD_CI_0_g_array_4[0]\, C => - \DWACT_ADD_CI_0_g_array_0_16[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_7[0]\); - - scaler_I_105 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1[0]\); - - \r.scaler_RNO_3[0]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[4]\, Y => - \scaler_i_m_1[4]\); - - scaler_I_27 : XOR2 - port map(A => \scaler[10]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_9[0]\); - - \r.tcnt_RNI73NE_1[1]\ : NOR2B - port map(A => \tcnt[1]\, B => \tcnt[0]\, Y => N_61_0); - - \r.brate_RNI4T9E[2]\ : MX2 - port map(A => \thempty\, B => \un1_dcom0[4]\, S => N_6455, - Y => N_330); - - \r.brate_RNO[5]\ : OR2A - port map(A => rstn, B => N_406, Y => \brate_RNO[5]\); - - \r.rxen_RNICM07\ : NOR2A - port map(A => enable, B => N_630, Y => rxdb_4); - - scaler_I_57 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[11]\, B => - \DWACT_ADD_CI_0_g_array_12_4[0]\, Y => \scaler_0[11]\); - - \uartop.op_gt.v.brate2_0_I_59\ : XNOR2 - port map(A => \scaler[11]\, B => \un1_dcom0[13]\, Y => - \DWACT_BL_EQUAL_0_E[2]\); - - \r.tshift_RNO[6]\ : NOR3 - port map(A => N_104, B => N_103, C => N_102, Y => - \tshift_RNO[6]\); - - scaler_I_84 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_12[0]\, B => - \DWACT_ADD_CI_0_g_array_0_12[0]\, C => - \DWACT_ADD_CI_0_g_array_0_13[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_6[0]\); - - \r.rxdb_RNO[0]\ : MAJ3 - port map(A => \rxf[2]\, B => \rxf[4]\, C => \rxf[3]\, Y => - N_8); - - \r.rshift_RNITHJD[6]\ : NOR2 - port map(A => \rshift[6]\, B => \rshift[7]\, Y => break10_3); - - \r.tshift_RNO_1[7]\ : NOR2 - port map(A => \tshift[8]\, B => N_77, Y => N_106); - - \r.brate_RNO_2[3]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[7]\, C => - \apbi_i_m[53]\, Y => \brate_1_iv_0[3]\); - - \r.brate_RNO_1[9]\ : OA1B - port map(A => \scaler[9]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[9]\, Y => \brate_1_iv[9]\); - - \r.brate_RNO_1[1]\ : NOR3 - port map(A => \scaler_i_m[5]\, B => \apbi_i_m[51]\, C => - \scaler_i_m_0[1]\, Y => \brate_1_iv[1]\); - - \r.rshift_RNO[4]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_443, Y => - \rshift_RNO[4]\); - - \r.ovf_RNO\ : OA1 - port map(A => N_438, B => ovf_0_sqmuxa, C => rstn, Y => - ovf_RNO); - - \r.brate_RNO_1[2]\ : NOR3 - port map(A => N_75, B => N_73, C => N_74, Y => - \brate_1_iv[2]\); - - \r.scaler_RNO_0[14]\ : AO1D - port map(A => N_697, B => pwdata_0(14), C => - \brate_i_m[14]\, Y => \scaler_1_0_iv_0[14]\); - - \r.txstate[0]\ : DFN1 - port map(D => N_560s, CLK => lclk_c, Q => \txstate[0]\); - - \r.tshift_RNO_0[3]\ : NOR2 - port map(A => \thold[2]\, B => N_64, Y => N_95); - - \r.scaler_RNO_1[13]\ : NOR2 - port map(A => \un1_dcom0[15]\, B => scaler_0_sqmuxa_1, Y - => \brate_i_m[13]\); - - \uartop.op_gt.v.brate2_0_I_57\ : XNOR2 - port map(A => \scaler[9]\, B => \un1_dcom0[11]\, Y => - \DWACT_BL_EQUAL_0_E[0]\); - - \v.brate_1_sqmuxa_1_i_o5\ : OR2B - port map(A => rstn, B => brate_1_sqmuxa, Y => N_697); - - scaler_I_97 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_9[0]\, B => - \DWACT_ADD_CI_0_g_array_11_1[0]\, C => - \DWACT_ADD_CI_0_g_array_0_10[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_4[0]\); - - \uartop.op_gt.v.brate2_0_I_35\ : NOR2A - port map(A => \un1_dcom0[14]\, B => \scaler[12]\, Y => - \ACT_LT4_E[0]\); - - \r.rhold[2]\ : DFN1E1 - port map(D => \rshift[2]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(2)); - - \r.thold[0]\ : DFN1E0 - port map(D => hwdata(24), CLK => lclk_c, E => write, Q => - \thold[0]\); - - \r.scaler[13]\ : DFN1E0 - port map(D => \scaler_1_0_iv[13]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[13]\); - - \r.rxdb_RNI3URED[1]\ : MX2C - port map(A => tcnt_1_sqmuxa, B => rxdb_1, S => N_61_0, Y - => \tcnt_1_sqmuxa[0]\); - - \r.brate_RNO_1[16]\ : AO1C - port map(A => brate_1_sqmuxa_4, B => \scaler[16]\, C => - \brate_1_iv_0[16]\, Y => \brate_1[16]\); - - \r.ovf\ : DFN1 - port map(D => ovf_RNO, CLK => lclk_c, Q => ovf); - - \r.brate_RNO_1[17]\ : AO1C - port map(A => brate_1_sqmuxa_4, B => \scaler[17]\, C => - \brate_1_iv_0[17]\, Y => \brate_1[17]\); - - \r.scaler_RNO_3[4]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[8]\, Y => - \scaler_i_m_1[8]\); - - \r.tshift_RNI1IJD[6]\ : NOR2B - port map(A => \tshift[6]\, B => \tshift[7]\, Y => - \tshift_1_0_a2_2[0]\); - - \r.rshift[6]\ : DFN1 - port map(D => \rshift_RNO[6]\, CLK => lclk_c, Q => - \rshift[6]\); - - \uartop.op_gt.v.brate2_0_I_70\ : AND2A - port map(A => \un1_dcom0[13]\, B => \scaler[11]\, Y => - \ACT_LT3_E[5]\); - - \r.tshift[6]\ : DFN1 - port map(D => \tshift_RNO[6]\, CLK => lclk_c, Q => - \tshift[6]\); - - \r.brate_RNO[7]\ : OR2A - port map(A => rstn, B => N_408, Y => \brate_RNO[7]\); - - \r.frame\ : DFN1 - port map(D => frame_RNO, CLK => lclk_c, Q => frame); - - \r.scaler_RNO_0[5]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[9]\, Y => N_741); - - \r.thold[6]\ : DFN1E0 - port map(D => hwdata(30), CLK => lclk_c, E => write, Q => - \thold[6]\); - - \r.scaler_RNO_1[6]\ : NOR2 - port map(A => \un1_dcom0[8]\, B => scaler_0_sqmuxa_1, Y => - \brate_i_m[6]\); - - \r.tshift_RNO[8]\ : NOR3 - port map(A => N_110, B => N_109, C => N_108, Y => - \tshift_RNO[8]\); - - \r.scaler_RNO_2[17]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[17]\, Y => - \scaler_i_m[17]\); - - \r.rshift[1]\ : DFN1 - port map(D => \rshift_RNO[1]\, CLK => lclk_c, Q => - \rshift[1]\); - - \r.brate_RNO_0[1]\ : MX2 - port map(A => \brate_1_iv[1]\, B => \un1_dcom0[3]\, S => - brate_2_sqmuxa, Y => N_402); - - \r.tshift_RNO_1[0]\ : OR2A - port map(A => \tshift[1]\, B => N_77, Y => N_124); - - \r.txstate_RNI6M9D_0[1]\ : NOR3A - port map(A => txtick, B => \txstate[0]\, C => \txstate[1]\, - Y => thempty_1_sqmuxa_1_i_o2_0); - - \r.brate_RNO_3[0]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(0), Y => - \apbi_i_m[50]\); - - \r.rshift_RNI6J4R[0]\ : NOR3A - port map(A => break10_1, B => \rshift[1]\, C => \rshift[0]\, - Y => break10_4); - - \r.tshift[1]\ : DFN1 - port map(D => N_27, CLK => lclk_c, Q => \tshift[1]\); - - \uartop.op_gt.v.brate2_0_I_7\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E_1[0]\, B => - \DWACT_BL_EQUAL_0_E_1[1]\, C => \DWACT_BL_EQUAL_0_E_0[2]\, - Y => \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0]\); - - \r.rshift[2]\ : DFN1 - port map(D => \rshift_RNO[2]\, CLK => lclk_c, Q => - \rshift[2]\); - - scaler_I_15 : AND2 - port map(A => \scaler[15]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_15[0]\); - - \r.scaler_RNO_1[10]\ : NOR2 - port map(A => N_697, B => pwdata_0(10), Y => N_727); - - \r.scaler_RNO_2[9]\ : AO1D - port map(A => N_697, B => pwdata_0(9), C => N_728, Y => - \scaler_1_0_iv_0_0[9]\); - - \r.tshift[2]\ : DFN1 - port map(D => N_29, CLK => lclk_c, Q => \tshift[2]\); - - \r.brate_RNI65I6[7]\ : XNOR2 - port map(A => \un1_dcom0[9]\, B => \scaler[7]\, Y => - tcnt8_3_i); - - \r.rshift_RNO_0[0]\ : MX2 - port map(A => \rshift[0]\, B => \rshift[1]\, S => - rshift_0_sqmuxa, Y => N_439); - - \r.brate_RNI69BD3[4]\ : OR3C - port map(A => tcnt8_NE_9, B => tcnt8_NE_8, C => tcnt8_NE_10, - Y => tcnt9); - - \r.txtick_RNO_0\ : NOR2B - port map(A => \txclk[2]\, B => tick, Y => txtick_0_i_0); - - \r.rshift_RNO_0[6]\ : MX2 - port map(A => \rshift[6]\, B => \rshift[7]\, S => - rshift_0_sqmuxa, Y => N_445); - - \r.thempty_RNI6RFE\ : OR2A - port map(A => enable, B => \thempty\, Y => N_59); - - \r.rxf[2]\ : DFN1 - port map(D => \rxf_RNO[2]\, CLK => lclk_c, Q => \rxf[2]\); - - \uartop.op_gt.v.brate2_0_I_19\ : XNOR2 - port map(A => \scaler[17]\, B => \un1_dcom0[19]\, Y => - \DWACT_BL_EQUAL_0_E_0[1]\); - - scaler_I_111 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_11[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_12[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_5[0]\); - - scaler_I_102 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_5[0]\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, C => - \DWACT_ADD_CI_0_g_array_1_6[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_2[0]\); - - \uartop.op_gt.v.brate2_0_I_95\ : AO1 - port map(A => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\, B => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[2]\, C => - \DWACT_CMPLE_PO2_DWACT_COMP0_E[0]\, Y => - \DWACT_COMP0_E[2]\); - - \r.brate_RNO_2[12]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[16]\, C => - N_707, Y => \brate_1_iv_0_0[12]\); - - \r.brate_RNIQ5GH[15]\ : XA1A - port map(A => \scaler[15]\, B => \un1_dcom0[17]\, C => - N_58_i_i, Y => tcnt8_NE_6); - - \r.scaler_RNO[9]\ : NOR3 - port map(A => N_729, B => N_730, C => - \scaler_1_0_iv_0_0[9]\, Y => \scaler_1_0_iv[9]\); - - \r.scaler[17]\ : DFN1E0 - port map(D => \scaler_1_0_iv[17]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[17]\); - - \uartop.op_gt.v.brate2_0_I_5\ : XNOR2 - port map(A => \scaler[12]\, B => \un1_dcom0[14]\, Y => - \DWACT_BL_EQUAL_0_E_1[0]\); - - \r.tsempty_RNIF68B\ : OR2B - port map(A => rdata60_1, B => N_329, Y => N_85); - - scaler_I_31 : XOR2 - port map(A => \scaler[5]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_4[0]\); - - scaler_I_104 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_2_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_3[0]\); - - \r.tshift_RNO_2[2]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[2]\, Y => - N_90); - - \r.rxf[0]\ : DFN1 - port map(D => dsurx_c, CLK => lclk_c, Q => \rxf[0]\); - - \r.brate_RNO[2]\ : OR2A - port map(A => rstn, B => N_403, Y => \brate_RNO[2]\); - - \r.brate_RNO[3]\ : OR2A - port map(A => rstn, B => N_404, Y => \brate_RNO[3]\); - - \r.txstate_RNO_1[0]\ : NOR3 - port map(A => N_114, B => \txstate[1]\, C => N_139, Y => - N_650); - - \r.brate_RNO_4[1]\ : NOR2 - port map(A => brate_1_sqmuxa_4, B => \scaler[1]\, Y => - \scaler_i_m_0[1]\); - - scaler_I_77 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_2[0]\, B => - \DWACT_ADD_CI_0_g_array_0_2[0]\, C => - \DWACT_ADD_CI_0_g_array_0_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_1[0]\); - - scaler_I_14 : AND2 - port map(A => \scaler[14]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_14[0]\); - - \r.tshift_RNO[2]\ : NOR3 - port map(A => N_92, B => N_91, C => N_90, Y => N_29); - - \r.rshift[4]\ : DFN1 - port map(D => \rshift_RNO[4]\, CLK => lclk_c, Q => - \rshift[4]\); - - \r.scaler[14]\ : DFN1E0 - port map(D => \scaler_1_0_iv[14]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[14]\); - - \r.tshift[4]\ : DFN1 - port map(D => \tshift_RNO[4]\, CLK => lclk_c, Q => - \tshift[4]\); - - \r.scaler_RNO_1[7]\ : NOR2 - port map(A => \un1_dcom0[9]\, B => scaler_0_sqmuxa_1, Y => - N_738); - - \r.rxstate_RNO_2[0]\ : OR2A - port map(A => \rxstate[0]\, B => rxtick, Y => N_639); - - scaler_I_62 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[1]\, B => - \scaler[0]\, Y => \scaler_0[1]\); - - \r.tshift[9]\ : DFN1 - port map(D => \tshift_10_0_iv[9]\, CLK => lclk_c, Q => - \tshift[9]\); - - \r.scaler_RNO_1[17]\ : AO1D - port map(A => \un1_dcom0[19]\, B => scaler_0_sqmuxa_1, C - => \scaler_i_m[17]\, Y => \scaler_1_0_iv_1[17]\); - - \r.scaler_RNO[11]\ : NOR3 - port map(A => N_721, B => N_722, C => - \scaler_1_0_iv_0_0[11]\, Y => \scaler_1_0_iv[11]\); - - \r.rxen_RNO_3\ : NOR2 - port map(A => rxen_1_sqmuxa, B => break_0_sqmuxa, Y => - rxen_1_sqmuxa_1); - - \r.brate_RNIC9FH[11]\ : XA1A - port map(A => \scaler[11]\, B => \un1_dcom0[13]\, C => - tcnt8_9_i, Y => tcnt8_NE_5); - - \v.brate_1_sqmuxa\ : NOR3B - port map(A => N_769, B => un1_apbi_1, C => un1_apbi_2, Y - => brate_1_sqmuxa); - - scaler_I_39 : XOR2 - port map(A => \scaler[11]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[11]\); - - \r.tshift_RNO_2[0]\ : AO1B - port map(A => txtick, B => N_126, C => \dsutx_c\, Y => - N_123); - - \r.tshift_RNO_1[4]\ : NOR2 - port map(A => \tshift[5]\, B => N_77, Y => N_97); - - \r.tshift_RNISN232[1]\ : NOR2 - port map(A => \tshift[1]\, B => N_138_i, Y => N_139); - - scaler_I_26 : XOR2 - port map(A => \scaler[1]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0[0]\); - - \r.rxstate_RNO_0[0]\ : OA1 - port map(A => N_640_2, B => \rxstate_ns_0_a3_0_0[0]\, C => - N_639, Y => \rxstate_ns_0_0[0]\); - - \r.dready_RNO\ : OA1A - port map(A => dready_2, B => dready_0_sqmuxa_0, C => rstn, - Y => dready_RNO); - - \r.txstate_RNO_2[0]\ : NOR2A - port map(A => N_59, B => \txstate[0]\, Y => N_114); - - scaler_I_47 : XOR2 - port map(A => \scaler[7]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[7]\); - - \r.scaler_RNO_2[12]\ : AO1D - port map(A => N_697, B => pwdata_0(12), C => N_716, Y => - \scaler_1_0_iv_0_0[12]\); - - \r.scaler[1]\ : DFN1E0 - port map(D => \scaler_1_0_iv[1]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[1]\); - - scaler_I_56 : XOR2 - port map(A => \scaler[6]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[6]\); - - \r.rxtick_RNI7JL1\ : OR2A - port map(A => rxtick, B => \rxdb[0]\, Y => rsempty_1_sqmuxa); - - \r.brate_RNO_3[7]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(7), Y => - \apbi_i_m[57]\); - - \uartop.op_gt.v.brate2_0_I_78\ : OR2A - port map(A => \un1_dcom0[7]\, B => \scaler[5]\, Y => N_12); - - \r.scaler_RNO[17]\ : NOR3A - port map(A => scaler_2_sqmuxa, B => \apbi_i_m[67]\, C => - \scaler_1_0_iv_1[17]\, Y => \scaler_1_0_iv[17]\); - - \r.rshift_RNO_0[3]\ : MX2 - port map(A => \rshift[3]\, B => \rshift[4]\, S => - rshift_0_sqmuxa, Y => N_442); - - \r.rxclk[0]\ : DFN1E0 - port map(D => \rxclk_1[0]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[0]\); - - \r.brate_RNO_1[12]\ : OA1B - port map(A => \scaler[12]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0_0[12]\, Y => \brate_1_iv[12]\); - - \r.brate_RNO_0[3]\ : MX2 - port map(A => \brate_1_iv[3]\, B => \un1_dcom0[5]\, S => - brate_2_sqmuxa, Y => N_404); - - scaler_I_96 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, C => - \DWACT_ADD_CI_0_g_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - \r.brate_RNIPEV9[3]\ : MX2 - port map(A => break, B => \un1_dcom0[5]\, S => N_6455, Y - => N_331); - - \r.txstate_RNO[1]\ : NOR2B - port map(A => rstn, B => N_561, Y => N_561s); - - un3_txclk_1_CO1 : NOR2B - port map(A => \txclk[1]\, B => N_680_i_1, Y => CO1); - - \r.tshift_RNO_1[8]\ : NOR2 - port map(A => \tshift[9]\, B => N_77, Y => N_109); - - \uartop.v.rxclk_1_i_a2[2]\ : NOR2A - port map(A => rxstate_0_sqmuxa, B => N_677, Y => N_136); - - \r.rsempty\ : DFN1 - port map(D => rsempty_RNO, CLK => lclk_c, Q => rsempty); - - \uartop.op_gt.v.brate2_0_I_1\ : XNOR2 - port map(A => \scaler[14]\, B => \un1_dcom0[16]\, Y => - \DWACT_BL_EQUAL_0_E_0[2]\); - - \r.tshift_RNO_0[2]\ : NOR2 - port map(A => \thold[1]\, B => N_64, Y => N_92); - - \r.rxtick_0_0_a5\ : AND2 - port map(A => N_136, B => rxtick_0_0_a5_0, Y => - rxtick_0_0_a5); - - \r.scaler_RNO_0[15]\ : NOR2 - port map(A => N_697, B => pwdata_0(15), Y => N_715); - - \r.scaler_RNO_3[3]\ : NOR2 - port map(A => scaler_2_sqmuxa, B => \scaler[7]\, Y => - \scaler_i_m_1[7]\); - - \r.scaler_RNO_2[8]\ : AO1D - port map(A => N_697, B => pwdata_0(8), C => N_732, Y => - \scaler_1_0_iv_0_0[8]\); - - scaler_I_87 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_13[0]\, B => - \DWACT_ADD_CI_0_g_array_11_2[0]\, C => - \DWACT_ADD_CI_0_g_array_0_14[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_6[0]\); - - \r.scaler_RNO_0[16]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[16]\, Y => - N_710); - - \uartop.op_gt.v.brate2_0_I_69\ : OR2A - port map(A => \un1_dcom0[13]\, B => \scaler[11]\, Y => - \ACT_LT3_E[4]\); - - \v.brate_0_sqmuxa\ : NOR2A - port map(A => rstn, B => brate_1_sqmuxa, Y => - brate_0_sqmuxa); - - \r.brate[1]\ : DFN1 - port map(D => \brate_RNO[1]\, CLK => lclk_c, Q => - \un1_dcom0[3]\); - - \uartop.op_gt.v.brate2_0_I_58\ : XNOR2 - port map(A => \scaler[10]\, B => \un1_dcom0[12]\, Y => - \DWACT_BL_EQUAL_0_E[1]\); - - \r.tshift_RNO[7]\ : NOR3 - port map(A => N_107, B => N_106, C => N_105, Y => - \tshift_RNO[7]\); - - \uartop.op_gt.v.brate2_0_I_42\ : NOR2A - port map(A => \scaler[14]\, B => \un1_dcom0[16]\, Y => - \ACT_LT4_E[7]\); - - scaler_I_101 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_1[0]\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, C => - \DWACT_ADD_CI_0_g_array_0_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_12[0]\); - - \r.tcnt_RNO_0[1]\ : XA1A - port map(A => \tcnt[1]\, B => CO0, C => tcnt_1_sqmuxa_3, Y - => \tcnt_0_sqmuxa_1_m[0]\); - - \r.rshift_RNO[1]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_440, Y => - \rshift_RNO[1]\); - - \r.brate_RNIU4O8[16]\ : XNOR2 - port map(A => \un1_dcom0[18]\, B => \scaler[16]\, Y => - N_58_i_i); - - \uartop.op_gt.v.brate2_0_I_67\ : AND2A - port map(A => \un1_dcom0[12]\, B => \scaler[10]\, Y => - \ACT_LT3_E[2]\); - - \r.brate_RNO_1[8]\ : OA1B - port map(A => \scaler[8]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0_0[8]\, Y => \brate_1_iv[8]\); - - \r.tcnt_RNI73NE_2[1]\ : NOR2B - port map(A => \tcnt[1]\, B => \tcnt[0]\, Y => N_61); - - \r.tshift_RNO_1[2]\ : NOR2 - port map(A => \tshift[3]\, B => N_77, Y => N_91); - - scaler_I_30 : XOR2 - port map(A => \scaler[12]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_11[0]\); - - \r.rshift_RNO[0]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_439, Y => - \rshift_RNO[0]\); - - \r.scaler_RNO_2[5]\ : AO1D - port map(A => \un1_dcom0[7]\, B => scaler_0_sqmuxa_1, C => - N_740, Y => \scaler_1_0_iv_0_1[5]\); - - \r.rxstate_RNI7QOB_0[0]\ : OR2A - port map(A => \rxstate[0]\, B => \rxstate[1]\, Y => - rshift_0_sqmuxa_0_a2_0_0); - - \r.brate_RNO[16]\ : OR2A - port map(A => rstn, B => N_417, Y => \brate_RNO[16]\); - - \r.brate[14]\ : DFN1 - port map(D => \brate_RNO[14]\, CLK => lclk_c, Q => - \un1_dcom0[16]\); - - \r.txstate[1]\ : DFN1 - port map(D => N_561s, CLK => lclk_c, Q => \txstate[1]\); - - \r.dready_RNID4BH\ : OR2B - port map(A => dready_2_0, B => N_321, Y => dready_2); - - \r.scaler_RNO_1[12]\ : NOR2 - port map(A => \un1_dcom0[14]\, B => scaler_0_sqmuxa_1, Y - => N_718); - - \r.frame_RNO\ : NOR2B - port map(A => rstn, B => N_427, Y => frame_RNO); - - \r.fedge_RNIO4K501\ : NOR3 - port map(A => tcnt_0_sqmuxa, B => N_61_0, C => - fedge_0_sqmuxa, Y => tcnt_0_sqmuxa_2); - - \r.tshift_RNO_2[7]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[7]\, Y => - N_105); - - \r.scaler_RNO[7]\ : NOR3 - port map(A => N_736, B => N_738, C => - \scaler_1_0_iv_0_0[7]\, Y => \scaler_1_0_iv[7]\); - - \r.rshift_RNIMJ6R[4]\ : NOR3A - port map(A => break10_3, B => \rshift[5]\, C => \rshift[4]\, - Y => break10_5); - - \r.scaler_RNO[2]\ : OR3C - port map(A => N_742, B => N_743, C => - \scaler_1_0_iv_0_0[2]\, Y => \scaler_1[2]\); - - \uartop.op_gt.v.brate2_0_I_26\ : AO1C - port map(A => \scaler[16]\, B => \un1_dcom0[18]\, C => - \scaler[17]\, Y => \ACT_LT2_E[1]\); - - \r.brate_RNO_3[8]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[12]\, Y => - N_706); - - \r.scaler_RNO_2[14]\ : NOR3B - port map(A => scaler_0_sqmuxa, B => rstn, C => - brate_i_m_14_m1_e_0, Y => \brate_i_m[14]\); - - \r.rxdb_RNIDBKCG1[1]\ : NOR3 - port map(A => \tcnt_1_sqmuxa[0]\, B => rxen_1_sqmuxa, C => - tcnt_0_sqmuxa_2, Y => tcnt_1_sqmuxa_3); - - scaler_I_65 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[6]\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => \scaler_0[6]\); - - \r.scaler_RNO_0[2]\ : OR2A - port map(A => \scaler[6]\, B => scaler_2_sqmuxa, Y => N_742); - - \r.fedge_RNO_1\ : AO1 - port map(A => fedge_0_sqmuxa, B => N_630, C => N_61_0, Y - => fedge_1_sqmuxa); - - \r.scaler[4]\ : DFN1E0 - port map(D => \scaler_1_0_iv[4]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[4]\); - - \r.tshift_RNO[4]\ : NOR3 - port map(A => N_98, B => N_97, C => N_96, Y => - \tshift_RNO[4]\); - - \r.rxstate_RNIEDED[0]\ : OR2 - port map(A => rshift_0_sqmuxa_0_a2_0_0, B => - rsempty_1_sqmuxa, Y => N_628); - - \r.tick\ : DFN1 - port map(D => scaler_0_sqmuxa, CLK => lclk_c, Q => tick); - - scaler_I_76 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_8[0]\, B => - \DWACT_ADD_CI_0_g_array_0_8[0]\, C => - \DWACT_ADD_CI_0_g_array_0_9[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_4[0]\); - - \uartop.op_gt.v.brate2_0_I_60\ : AND3 - port map(A => \DWACT_BL_EQUAL_0_E[2]\, B => - \DWACT_BL_EQUAL_0_E[1]\, C => \DWACT_BL_EQUAL_0_E[0]\, Y - => \DWACT_CMPLE_PO2_DWACT_COMP0_E[1]\); - - \r.rshift_RNIS6BM1[0]\ : OR2B - port map(A => break10_5, B => break10_4, Y => break10_i_0); - - \r.brate[12]\ : DFN1 - port map(D => \brate_RNO[12]\, CLK => lclk_c, Q => - \un1_dcom0[14]\); - - \r.brate_RNI0TL6[7]\ : MX2 - port map(A => \rxdb[0]\, B => \un1_dcom0[9]\, S => N_6455_0, - Y => N_334); - - \r.break_RNO_0\ : MX2 - port map(A => break, B => break_1, S => N_7, Y => N_419); - - \r.brate_RNI8IAF[8]\ : XA1A - port map(A => \scaler[8]\, B => \un1_dcom0[10]\, C => - N_59_i_i, Y => tcnt8_NE_1); - - scaler_I_33 : XOR2 - port map(A => \scaler[11]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_10[0]\); - - \r.tshift_RNO_0[5]\ : NOR2 - port map(A => \thold[4]\, B => N_64, Y => N_101); - - \r.brate[3]\ : DFN1 - port map(D => \brate_RNO[3]\, CLK => lclk_c, Q => - \un1_dcom0[5]\); - - \r.rxdb_RNIRRFH[0]\ : OR2B - port map(A => dready_2, B => \rxdb[0]\, Y => - rsempty_0_sqmuxa_1_1); - - \r.scaler_RNO_2[2]\ : OA1A - port map(A => pwdata_0(2), B => N_697, C => N_744, Y => - \scaler_1_0_iv_0_0[2]\); - - \r.rxen_RNO_1\ : NOR2A - port map(A => rxen_0_sqmuxa_1, B => rxen_1_sqmuxa, Y => - rxen_0_sqmuxa_2); - - \uartop.op_gt.v.brate2_0_I_18\ : XNOR2 - port map(A => \scaler[16]\, B => \un1_dcom0[18]\, Y => - \DWACT_BL_EQUAL_0_E_0[0]\); - - \uartop.op_gt.v.brate2_0_I_82\ : AO1C - port map(A => \un1_dcom0[7]\, B => \scaler[5]\, C => N_14, - Y => N_16); - - \r.tshift_RNI1L9S1[4]\ : OR2B - port map(A => \tshift_1_0_a2_6[0]\, B => - \tshift_1_0_a2_5[0]\, Y => N_138_i); - - \r.scaler[16]\ : DFN1E0 - port map(D => \scaler_1_0_iv[16]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[16]\); - - \r.rxen_RNO_2\ : NOR2B - port map(A => rxen_1_sqmuxa, B => pwdata_0(0), Y => rxen_1); - - \uartop.op_gt.v.brate2_0_I_6\ : XNOR2 - port map(A => \scaler[13]\, B => \un1_dcom0[15]\, Y => - \DWACT_BL_EQUAL_0_E_1[1]\); - - \uartop.op_gt.v.brate2_0_I_25\ : AND2A - port map(A => \un1_dcom0[19]\, B => \scaler[17]\, Y => - \ACT_LT2_E[0]\); - - \r.thold[5]\ : DFN1E0 - port map(D => hwdata(29), CLK => lclk_c, E => write, Q => - \thold[5]\); - - \r.tsempty\ : DFN1 - port map(D => tsempty_RNO, CLK => lclk_c, Q => tsempty); - - scaler_I_46 : XOR2 - port map(A => \scaler[1]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[1]\); - - \r.rsempty_RNO_3\ : AO1B - port map(A => rsempty_1_sqmuxa, B => rsempty_0_sqmuxa_1_1, - C => \rxstate[1]\, Y => rsempty_0_sqmuxa_2); - - scaler_I_21 : AND2 - port map(A => \scaler[5]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_5[0]\); - - \r.rxdb[0]\ : DFN1 - port map(D => N_8, CLK => lclk_c, Q => \rxdb[0]\); - - scaler_I_17 : AND2 - port map(A => \scaler[7]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_7[0]\); - - \r.scaler_RNO_3[11]\ : NOR2 - port map(A => N_697, B => pwdata_0(11), Y => N_723); - - \r.scaler_RNO_2[1]\ : AO1D - port map(A => scaler_2_sqmuxa, B => \scaler[5]\, C => - \apbi_i_m_0[51]\, Y => \scaler_1_0_iv_0[1]\); - - scaler_I_51 : XOR2 - port map(A => \scaler[15]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[15]\); - - \uartop.op_gt.v.brate2_0_I_45\ : AOI1A - port map(A => \ACT_LT4_E[3]\, B => \ACT_LT4_E[6]\, C => - \ACT_LT4_E[10]\, Y => \DWACT_CMPLE_PO0_DWACT_COMP0_E[2]\); - - scaler_I_64 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[14]\, B => - \DWACT_ADD_CI_0_g_array_11_2[0]\, Y => \scaler_0[14]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.scaler_RNO_1[5]\ : NOR2 - port map(A => N_697, B => pwdata_0(5), Y => N_122); - - \r.rxclk_RNO[2]\ : OA1A - port map(A => rxstate_0_sqmuxa, B => N_677, C => rstn, Y - => N_23); - - \r.brate_RNO_1[5]\ : OA1B - port map(A => \scaler[5]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[5]\, Y => \brate_1_iv[5]\); - - scaler_I_28 : XOR2 - port map(A => \scaler[14]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_13[0]\); - - \r.scaler_RNO_2[0]\ : AO1D - port map(A => N_697, B => pwdata_0(0), C => - \scaler_i_m_1[4]\, Y => \scaler_1_0_iv_0[0]\); - - scaler_I_58 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[13]\, B => - \DWACT_ADD_CI_0_g_array_12_5[0]\, Y => \scaler_0[13]\); - - \r.brate_RNO[11]\ : OR2A - port map(A => rstn, B => N_412, Y => \brate_RNO[11]\); - - scaler_I_91 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_2_2[0]\, B => - \DWACT_ADD_CI_0_g_array_2_2[0]\, C => - \DWACT_ADD_CI_0_g_array_2_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_3_1[0]\); - - \r.rshift_RNO_0[2]\ : MX2 - port map(A => \rshift[2]\, B => \rshift[3]\, S => - rshift_0_sqmuxa, Y => N_441); - - \r.brate_RNO[9]\ : OR2A - port map(A => rstn, B => N_410, Y => \brate_RNO[9]\); - - \r.rxstate[0]\ : DFN1 - port map(D => \rxstate_nss[0]\, CLK => lclk_c, Q => - \rxstate[0]\); - - \r.brate_RNO_1[6]\ : NOR3 - port map(A => \scaler_i_m[10]\, B => \apbi_i_m[56]\, C => - \scaler_i_m_0[6]\, Y => \brate_1_iv[6]\); - - \r.rxtick\ : DFN1 - port map(D => rxtick_0_0_a5, CLK => lclk_c, Q => rxtick); - - \apbo.prdata_5_0_a2\ : XNOR2 - port map(A => paddr(2), B => paddr(3), Y => \N_127\); - - \r.scaler_RNO_1[14]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[14]\, Y => - \scaler_i_m[14]\); - - scaler_I_29 : XOR2 - port map(A => \scaler[3]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_2[0]\); - - scaler_I_59 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[12]\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, Y => \scaler_0[12]\); - - \r.brate_RNO_2[4]\ : AO1A - port map(A => pwdata_0(4), B => brate_1_sqmuxa, C => N_78, - Y => \brate_1_iv_0_0[4]\); - - scaler_I_98 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_2[0]\, B => - \DWACT_ADD_CI_0_g_array_1_2[0]\, C => - \DWACT_ADD_CI_0_g_array_1_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_2_1[0]\); - - \r.tcnt_RNIHFKV3_0[1]\ : NOR2A - port map(A => tcnt_0_sqmuxa, B => N_61_0, Y => - tcnt_0_sqmuxa_1); - - \v.rxen_1_sqmuxa\ : NOR3B - port map(A => N_769, B => un1_apbi_1, C => rdata60_1, Y => - rxen_1_sqmuxa); - - \r.brate_RNO_4[6]\ : NOR2 - port map(A => brate_1_sqmuxa_4, B => \scaler[6]\, Y => - \scaler_i_m_0[6]\); - - \r.rxen_RNION4IM\ : NOR2B - port map(A => enable, B => tick_2, Y => scaler_0_sqmuxa); - - \uartop.op_gt.v.brate2_0_I_86\ : AO1C - port map(A => \scaler[7]\, B => \un1_dcom0[9]\, C => N_15_0, - Y => N_20); - - \r.brate_RNO_0[11]\ : MX2 - port map(A => \brate_1_iv[11]\, B => \un1_dcom0[13]\, S => - brate_2_sqmuxa, Y => N_412); - - \r.brate_RNO_3[11]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(11), Y => - \apbi_i_m[61]\); - - \r.brate_RNO_3[6]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(6), Y => - \apbi_i_m[56]\); - - \r.tshift_RNO_0[8]\ : NOR2 - port map(A => \thold[7]\, B => N_64, Y => N_110); - - \r.scaler[3]\ : DFN1E0 - port map(D => \scaler_1_0_iv[3]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[3]\); - - scaler_I_99 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, C => - \DWACT_ADD_CI_0_g_array_1_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - scaler_I_108 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - \r.brate_RNO_2[10]\ : AO1D - port map(A => brate_0_sqmuxa_1_i, B => \scaler[14]\, C => - N_82, Y => \brate_1_iv_0_0[10]\); - - \r.brate[13]\ : DFN1 - port map(D => \brate_RNO[13]\, CLK => lclk_c, Q => - \un1_dcom0[15]\); - - \uartop.op_gt.v.brate2_0_I_39\ : OR2A - port map(A => \un1_dcom0[16]\, B => \scaler[14]\, Y => - \ACT_LT4_E[4]\); - - \r.brate[7]\ : DFN1 - port map(D => \brate_RNO[7]\, CLK => lclk_c, Q => - \un1_dcom0[9]\); - - \r.brate_RNO[6]\ : OR2A - port map(A => rstn, B => N_407, Y => \brate_RNO[6]\); - - \uartop.op_gt.v.brate2_0_I_68\ : AOI1A - port map(A => \ACT_LT3_E[0]\, B => \ACT_LT3_E[1]\, C => - \ACT_LT3_E[2]\, Y => \ACT_LT3_E[3]\); - - \r.rxen_RNIJGPI\ : OR2A - port map(A => rxdb_4, B => N_622, Y => rxstate_0_sqmuxa); - - \uartop.op_gt.v.brate2_0_I_85\ : OR2A - port map(A => \scaler[8]\, B => \un1_dcom0[10]\, Y => - N_19_0); - - \r.rxen_RNI3357J1\ : MX2 - port map(A => scaler_2_sqmuxa_1, B => tick_2, S => enable, - Y => \scaler_2_sqmuxa[0]\); - - \r.rshift_RNILHID[2]\ : NOR2 - port map(A => \rshift[2]\, B => \rshift[3]\, Y => break10_1); - - \uartop.op_gt.v.brate2_0_I_37\ : AND2A - port map(A => \un1_dcom0[15]\, B => \scaler[13]\, Y => - \ACT_LT4_E[2]\); - - \r.scaler[5]\ : DFN1E0 - port map(D => \scaler_1_0_iv[5]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[5]\); - - \r.brate_RNO_2[14]\ : AOI1B - port map(A => brate_1_sqmuxa, B => pwdata_0(14), C => - brate_3_sqmuxa_i, Y => \brate_1_iv_0[14]\); - - \r.rhold[7]\ : DFN1E1 - port map(D => \rshift[7]\, CLK => lclk_c, E => - dready_0_sqmuxa_0, Q => data(7)); - - \r.tick_RNI5JQ31\ : OR2 - port map(A => tick, B => N_21_1, Y => N_15); - - \r.brate[5]\ : DFN1 - port map(D => \brate_RNO[5]\, CLK => lclk_c, Q => - \un1_dcom0[7]\); - - \r.scaler_RNO_2[15]\ : OR3A - port map(A => scaler_0_sqmuxa, B => brate_1_sqmuxa, C => - \un1_dcom0[17]\, Y => \scaler_RNO_2[15]\); - - \r.rxclk[1]\ : DFN1E0 - port map(D => \rxclk_1[1]\, CLK => lclk_c, E => - rxclk_1_sqmuxa_1, Q => \rxclk[1]\); - - scaler_I_20 : AND2 - port map(A => \scaler[11]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_11[0]\); - - \r.tshift_RNO_2[8]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[8]\, Y => - N_108); - - \r.rsempty_RNO_4\ : OR2 - port map(A => rxdb_4, B => \rxstate[1]\, Y => rsempty_RNO_4); - - \uartop.op_gt.v.brate2_0_I_41\ : NOR2A - port map(A => \ACT_LT4_E[4]\, B => \ACT_LT4_E[5]\, Y => - \ACT_LT4_E[6]\); - - scaler_I_71 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[16]\, B => - \DWACT_ADD_CI_0_g_array_4[0]\, Y => \scaler_0[16]\); - - \r.break\ : DFN1 - port map(D => break_RNO, CLK => lclk_c, Q => break); - - scaler_I_50 : XOR2 - port map(A => \scaler[3]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[3]\); - - \r.scaler_RNO_2[16]\ : OAI1 - port map(A => pwdata(16), B => N_697, C => scaler_2_sqmuxa, - Y => \scaler_1_0_iv_0_0[16]\); - - \r.rshift_RNO_0[5]\ : MX2 - port map(A => \rshift[5]\, B => \rshift[6]\, S => - rshift_0_sqmuxa, Y => N_444); - - \r.tcnt_RNIGD3J[1]\ : OR3 - port map(A => \tcnt[0]\, B => \tcnt[1]\, C => rdata60_1, Y - => N_86); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.brate_RNIICN8[10]\ : XNOR2 - port map(A => \un1_dcom0[12]\, B => \scaler[10]\, Y => - tcnt8_6_i); - - \r.brate_RNO_3[2]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(2), Y => N_73); - - \r.txstate_RNIHL8Q[1]\ : OR3A - port map(A => N_59, B => \txstate[0]\, C => \txstate[1]\, Y - => N_126); - - \r.thold[1]\ : DFN1E0 - port map(D => hwdata(25), CLK => lclk_c, E => write, Q => - \thold[1]\); - - \r.rxtick_RNI0M9D_0\ : OR2A - port map(A => rxtick, B => N_640_2, Y => N_627); - - \r.tcnt_RNI0K947[1]\ : OR2A - port map(A => brate_0_sqmuxa, B => brate_1_sqmuxa_2, Y => - brate_1_sqmuxa_4); - - \r.scaler_RNO[16]\ : NOR3 - port map(A => N_710, B => N_711, C => - \scaler_1_0_iv_0_0[16]\, Y => \scaler_1_0_iv[16]\); - - \r.brate_RNO_0[16]\ : MX2 - port map(A => \brate_1[16]\, B => \un1_dcom0[18]\, S => - brate_2_sqmuxa, Y => N_417); - - \r.brate_RNO_0[17]\ : MX2 - port map(A => \brate_1[17]\, B => \un1_dcom0[19]\, S => - brate_2_sqmuxa, Y => N_418); - - \r.rxdb_RNI5BSL[1]\ : MX2C - port map(A => rxdb_3, B => rxdb_1, S => N_61_0, Y => - \brate13[0]\); - - scaler_I_78 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_2_1[0]\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, C => - \DWACT_ADD_CI_0_g_array_2_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_10[0]\); - - scaler_I_109 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_0_9[0]\, B => - \DWACT_ADD_CI_0_pog_array_0_10[0]\, Y => - \DWACT_ADD_CI_0_pog_array_1_4[0]\); - - \r.brate[16]\ : DFN1 - port map(D => \brate_RNO[16]\, CLK => lclk_c, Q => - \un1_dcom0[18]\); - - scaler_I_90 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_3[0]\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, C => - \DWACT_ADD_CI_0_g_array_0_4[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_1[0]\); - - \r.tshift_RNO_0[1]\ : NOR2 - port map(A => \thold[0]\, B => N_64, Y => N_89); - - \r.brate_RNO_1[10]\ : OA1B - port map(A => \scaler[10]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0_0[10]\, Y => \brate_1_iv[10]\); - - \r.brate_RNO_2[13]\ : AO1A - port map(A => pwdata_0(13), B => brate_1_sqmuxa, C => - \scaler_i_m_1[17]\, Y => \brate_1_iv_0[13]\); - - scaler_I_41 : XOR2 - port map(A => \scaler[4]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_partial_sum[4]\); - - scaler_I_16 : AND2 - port map(A => \scaler[13]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_13[0]\); - - \r.tshift_RNO[1]\ : NOR3 - port map(A => N_89, B => N_88, C => N_87, Y => N_27); - - \r.brate_RNO_3[5]\ : NOR2A - port map(A => brate_1_sqmuxa, B => pwdata_0(5), Y => - \apbi_i_m[55]\); - - \r.tcnt_RNITJ4P6[1]\ : OR3B - port map(A => rxen_0_sqmuxa_1, B => rstn, C => - brate_1_sqmuxa, Y => brate_0_sqmuxa_1_i); - - scaler_I_79 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_1_6[0]\, B => - \DWACT_ADD_CI_0_g_array_1_6[0]\, C => - \DWACT_ADD_CI_0_g_array_1_7[0]\, Y => - \DWACT_ADD_CI_0_g_array_2_3[0]\); - - \r.brate_RNO[14]\ : OR2A - port map(A => rstn, B => N_415, Y => \brate_RNO[14]\); - - \r.scaler_RNO_2[3]\ : AO1D - port map(A => N_697, B => pwdata_0(3), C => - \scaler_i_m_1[7]\, Y => \scaler_1_0_iv_0[3]\); - - \r.frame_RNO_0\ : MX2 - port map(A => frame, B => frame_1, S => N_9, Y => N_427); - - \r.rshift_RNO[3]\ : OR2A - port map(A => rxstate_0_sqmuxa, B => N_442, Y => - \rshift_RNO[3]\); - - \r.brate_RNO_2[15]\ : AOI1B - port map(A => brate_1_sqmuxa, B => pwdata_0(15), C => - brate_3_sqmuxa_i, Y => \brate_1_iv_0[15]\); - - \r.scaler[8]\ : DFN1E0 - port map(D => \scaler_1_0_iv[8]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[8]\); - - \r.tshift_RNO[0]\ : OR3C - port map(A => \tshift_1_0_0[0]\, B => N_124, C => rstn, Y - => \tshift_1[0]\); - - \r.rxdb_RNI43I3[1]\ : OR3B - port map(A => fedge, B => \rxdb[1]\, C => \rxdb[0]\, Y => - rxdb_3); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.brate_RNO_3[9]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[13]\, Y => - \scaler_i_m[13]\); - - scaler_I_48 : XOR2 - port map(A => \scaler[16]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[16]\); - - scaler_I_32 : XOR2 - port map(A => \scaler_0[2]\, B => N_61_1, Y => - \DWACT_ADD_CI_0_pog_array_0_1[0]\); - - \r.scaler_RNO_0[6]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[6]\, Y => - \scaler_i_m[6]\); - - \r.scaler_RNO[3]\ : NOR3 - port map(A => \scaler_i_m[3]\, B => \brate_i_m[3]\, C => - \scaler_1_0_iv_0[3]\, Y => \scaler_1_0_iv[3]\); - - \uartop.op_gt.v.brate2_0_I_3\ : XNOR2 - port map(A => \scaler[16]\, B => \un1_dcom0[18]\, Y => - \DWACT_BL_EQUAL_0_E[4]\); - - scaler_I_23 : XOR2 - port map(A => \scaler[4]\, B => N_61, Y => - \DWACT_ADD_CI_0_pog_array_0_3[0]\); - - \r.brate_RNO_1[14]\ : AO1C - port map(A => brate_1_sqmuxa_4, B => \scaler[14]\, C => - \brate_1_iv_0[14]\, Y => \brate_1[14]\); - - scaler_I_53 : XOR2 - port map(A => \scaler_0[2]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[2]\); - - \r.tcnt_RNO_0[0]\ : XA1 - port map(A => \tcnt[0]\, B => tcnt_0_sqmuxa_1, C => - tcnt_1_sqmuxa_3, Y => \tcnt_0_sqmuxa_1_m[1]\); - - \r.rshift[7]\ : DFN1 - port map(D => \rshift_RNO[7]\, CLK => lclk_c, Q => - \rshift[7]\); - - \r.txstate_RNI6M9D[1]\ : OAI1 - port map(A => \txstate[0]\, B => \txstate[1]\, C => txtick, - Y => N_77); - - \r.tshift_RNO_2[1]\ : AOI1 - port map(A => txtick, B => N_126, C => \tshift[1]\, Y => - N_87); - - \r.tshift_RNO_1[3]\ : NOR2 - port map(A => \tshift[4]\, B => N_77, Y => N_94); - - \uartop.op_gt.v.brate2_0_I_100\ : AO1 - port map(A => \DWACT_COMP0_E[1]\, B => \DWACT_COMP0_E[2]\, - C => \DWACT_COMP0_E[0]\, Y => brate2); - - \r.scaler_RNO[6]\ : NOR3 - port map(A => \scaler_i_m[6]\, B => \brate_i_m[6]\, C => - \scaler_1_0_iv_0[6]\, Y => \scaler_1_0_iv[6]\); - - \r.ovf_RNICG8B\ : MX2 - port map(A => ovf, B => \un1_dcom0[6]\, S => N_6455_0, Y - => N_332); - - \r.tshift[7]\ : DFN1 - port map(D => \tshift_RNO[7]\, CLK => lclk_c, Q => - \tshift[7]\); - - \r.tsempty_RNO_1\ : NOR3A - port map(A => txtick, B => \txstate[0]\, C => \txstate[1]\, - Y => N_79); - - scaler_I_81 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_4[0]\, B => - \DWACT_ADD_CI_0_g_array_0_4[0]\, C => - \DWACT_ADD_CI_0_g_array_0_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_2[0]\); - - scaler_I_49 : XOR2 - port map(A => \scaler[8]\, B => N_61_0, Y => - \DWACT_ADD_CI_0_partial_sum[8]\); - - \r.brate_RNO_1[7]\ : OA1B - port map(A => \scaler[7]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[7]\, Y => \brate_1_iv[7]\); - - scaler_I_67 : XOR2 - port map(A => \DWACT_ADD_CI_0_partial_sum[7]\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => \scaler_0[7]\); - - \r.tcnt_RNIHFKV3[1]\ : NOR3 - port map(A => tcnt9, B => rxen_0_sqmuxa_0, C => rxdb_3, Y - => rxen_0_sqmuxa_1); - - \r.brate_RNO_0[0]\ : MX2 - port map(A => \brate_1_iv[0]\, B => \un1_dcom0[2]\, S => - brate_2_sqmuxa, Y => N_401); - - \r.tcnt_RNO[0]\ : OA1 - port map(A => \apbi_m[51]_net_1\, B => - \tcnt_0_sqmuxa_1_m[1]\, C => rstn, Y => \tcnt_RNO[0]\); - - \uartop.op_gt.v.brate2_0_I_81\ : OR2A - port map(A => \un1_dcom0[10]\, B => \scaler[8]\, Y => - N_15_0); - - scaler_I_93 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_5[0]\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, C => - \DWACT_ADD_CI_0_g_array_0_6[0]\, Y => - \DWACT_ADD_CI_0_g_array_12_2[0]\); - - \r.scaler_RNO_1[15]\ : AOI1B - port map(A => \scaler_RNO_2[15]\, B => \scaler_RNO_3[15]\, - C => rstn, Y => \scaler_RNO_1[15]\); - - \r.scaler_RNO_0[11]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[11]\, Y => - N_721); - - \r.tsempty_RNO_0\ : MX2 - port map(A => tsempty, B => N_59, S => N_79, Y => N_447); - - \r.scaler_RNO_0[4]\ : NOR2 - port map(A => scaler_1_sqmuxa, B => \scaler_0[4]\, Y => - \scaler_i_m[4]\); - - \r.scaler_RNO_1[16]\ : NOR2 - port map(A => \un1_dcom0[18]\, B => scaler_0_sqmuxa_1, Y - => N_711); - - scaler_I_107 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2[0]\); - - scaler_I_88 : AO1 - port map(A => \DWACT_ADD_CI_0_pog_array_0_14[0]\, B => - \DWACT_ADD_CI_0_g_array_0_14[0]\, C => - \DWACT_ADD_CI_0_g_array_0_15[0]\, Y => - \DWACT_ADD_CI_0_g_array_1_7[0]\); - - \r.scaler[15]\ : DFN1E0 - port map(D => \scaler_1_0_iv[15]\, CLK => lclk_c, E => - scaler_4_sqmuxa, Q => \scaler[15]\); - - \r.brate_RNO_2[2]\ : NOR2 - port map(A => brate_0_sqmuxa_1_i, B => \scaler[6]\, Y => - N_75); - - \r.tshift_RNI31311[8]\ : NOR3C - port map(A => \tshift[9]\, B => \tshift[8]\, C => - \tshift_1_0_a2_4[0]\, Y => \tshift_1_0_a2_6[0]\); - - \r.brate_RNO_1[13]\ : OA1B - port map(A => \scaler[13]\, B => brate_1_sqmuxa_4, C => - \brate_1_iv_0[13]\, Y => \brate_1_iv[13]\); - - \r.scaler_RNISMOP[0]\ : MX2 - port map(A => \scaler[0]\, B => tick, S => N_61_0, Y => - N_62); - - scaler_I_5 : AND2 - port map(A => \scaler[12]\, B => N_61, Y => - \DWACT_ADD_CI_0_g_array_0_12[0]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity dcom is - - port( tcnt : in std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93); - hrdata_0_d0 : in std_logic; - hrdata_1 : in std_logic; - hrdata_24 : in std_logic; - hrdata_26 : in std_logic; - hrdata_25 : in std_logic; - hrdata_23 : in std_logic; - hwdata : out std_logic_vector(31 downto 0); - hrdata_0_1 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_0 : in std_logic; - data : in std_logic_vector(7 downto 0); - iosn_0 : in std_logic_vector(93 to 93); - state_i : out std_logic_vector(5 to 5); - haddr : out std_logic_vector(31 downto 0); - rstn : in std_logic; - hbusreq_i_3 : out std_logic; - N_78_0 : in std_logic; - N_262_0 : in std_logic; - thempty : in std_logic; - N_321 : out std_logic; - N_264_0 : in std_logic; - active : in std_logic; - hwrite : out std_logic; - dready : in std_logic; - write : out std_logic; - lclk_c : in std_logic - ); - -end dcom; - -architecture DEF_ARCH of dcom is - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AXOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \state_0[4]\, \state_i_RNIIHN51[5]\, \state_0[3]\, - \state_0_RNIIOIE4[3]\, data_0_sqmuxa_0, N_438, N_721, - state_4_0, state_4_0_0_0_0, N_680_0, N_308, N_682_0, N_15, - \len[1]\, \len[0]\, N_7, \len[3]\, \DWACT_FDEC_E[0]\, - N_147, N_139, \DWACT_FINC_E[0]\, N_116, \DWACT_FINC_E[4]\, - N_101, \DWACT_FINC_E[7]\, \DWACT_FINC_E[6]\, - \state_srsts_0_0_0_a2_5_0[1]\, N_318, - \state_srsts_0_i_i_0_o2_0[3]\, \state[2]\, - \clen_1_i_0_0[1]\, \clen_1_i_0_a2_0_0[1]\, - \clen_1_i_0_0[0]\, \clen_1_i_0_a2_0_0[0]\, \state_i[5]\, - \state[0]\, N_411_i_1, \clen[1]\, N_634, N_574, N_580, - N_577, N_194, N_425, N_427, N_426, N_30, N_397, N_398, - N_396, \state_i_RNO[5]\, N_405, N_406, \un1_rst_0_o4\, - N_637, N_604, N_610, N_607, N_635, N_583, N_592, N_589, - N_633, N_562, N_571, N_568, N_632, N_550, N_558, N_554, - N_631, N_535, N_546, N_537, N_629, N_487, N_490, N_489, - N_625, N_448, N_456, N_449, N_624, N_445, N_447, N_446, - N_621, N_434, N_436, N_435, N_212, N_431, N_433, N_432, - N_204, N_428, N_430, N_429, N_172, N_422, N_424, N_423, - N_170, N_419, N_421, N_420, N_620, N_416, N_418, N_417, - N_619, N_413, N_415, N_414, N_39, N_410, N_650, N_409, - N_453, N_391, N_392, N_390, N_452, N_388, N_389, N_387, - N_626, N_457, N_459, N_458, N_622, N_439, N_441, N_440, - N_636, N_595, N_601, N_598, N_454, N_394, N_395, N_393, - N_627, N_460, N_652, N_461, N_628, N_653, N_465, N_654, - N_32, N_661, N_662, N_660, \state_RNO[0]\, N_404, N_403, - \state_0_RNIUUDG_0[4]\, N_450, N_668, N_328, N_451, N_664, - N_408, N_407, \state_RNIJ7F62[1]\, \write\, - \state_nsss[4]\, N_402, N_400, N_401, \state[1]\, N_655, - N_325, \state_srsts_0_i_i_0_1[3]\, N_656, N_623, N_442, - N_444, N_443, N_630, N_491, N_532, N_498, - \state_srsts_0_i_i_0_1_tz[3]\, \hwrite\, \state_RNO[2]\, - \state_srsts_0_i_0_i_a2_0[2]\, N_319, N_335, N_351, N_353, - N_354, N_355, N_357, N_363, N_374, N_376, N_377, N_365, - N_349, N_342, \haddr[5]\, I_13_6, I_186_0, \haddr[20]\, - I_115_0, N_358, N_375, N_322, N_720, N_722, N_316, N_320, - I_24_3, \len[5]\, N_343, N_344, I_5_3, N_345, I_9_3, - N_347, I_20_3, N_348, N_356, N_350, \state[3]\, N_346, - I_13_7, write_0_sqmuxa, write_0_sqmuxa_0, write_RNO, - N_215, \haddr[2]\, \haddr[3]\, I_5_2, I_24_2, I_143_0, - I_156_0, I_166_0, I_173_0, I_196_0, I_203_0, I_210_0, - \haddr[10]\, I_45_0, I_52_0, \state[4]\, - \state_RNIBAHA2_0[4]\, I_77_0, \state_RNIBAHA2[4]\, - \haddr[7]\, \haddr[17]\, I_91_0, \haddr[18]\, I_98_0, - \haddr[19]\, I_105_0, \haddr[11]\, \haddr[21]\, I_122_0, - \haddr[23]\, I_136_0, \haddr[15]\, N_338, N_367, N_368, - N_378, \state_RNIGT3N[4]\, N_352, I_56_0, \haddr[12]\, - \N_321\, I_129_0, \haddr[22]\, I_31_2, I_66_0, - \haddr[13]\, I_9_2, \haddr[4]\, I_20_2, \haddr[6]\, - I_73_0, \haddr[14]\, N_327, write_1_sqmuxa, N_339, N_379, - N_640, N_372, N_370, N_639, N_341, N_340, N_337, N_336, - \haddr[8]\, I_84_0, \haddr[16]\, I_38_0, \haddr[9]\, - \haddr[0]\, \haddr[1]\, \haddr[24]\, \haddr[25]\, - \haddr[26]\, \haddr[27]\, \haddr[28]\, \haddr[29]\, - \haddr[30]\, \haddr[31]\, \len[2]\, \len[4]\, \hwdata[0]\, - \hwdata[1]\, \hwdata[2]\, \hwdata[3]\, \hwdata[4]\, - \hwdata[5]\, \hwdata[6]\, \hwdata[7]\, \hwdata[8]\, - \hwdata[9]\, \hwdata[10]\, \hwdata[11]\, \hwdata[12]\, - \hwdata[13]\, \hwdata[14]\, \hwdata[15]\, \hwdata[16]\, - \hwdata[17]\, \hwdata[18]\, \hwdata[19]\, \hwdata[20]\, - \hwdata[21]\, \hwdata[22]\, \hwdata[23]\, N_4, - \DWACT_FINC_E[24]\, \DWACT_FINC_E[23]\, - \DWACT_FINC_E[25]\, N_9, \DWACT_FINC_E[29]\, - \DWACT_FINC_E[30]\, N_14, \DWACT_FINC_E[15]\, - \DWACT_FINC_E[17]\, \DWACT_FINC_E[22]\, N_21, - \DWACT_FINC_E[21]\, \DWACT_FINC_E[9]\, \DWACT_FINC_E[12]\, - \DWACT_FINC_E[20]\, N_30_0, \DWACT_FINC_E[13]\, - \DWACT_FINC_E[19]\, N_35, \DWACT_FINC_E[18]\, N_42, - \DWACT_FINC_E[33]\, \DWACT_FINC_E[34]\, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[5]\, N_51, \DWACT_FINC_E[28]\, - \DWACT_FINC_E[16]\, N_56, N_61, \DWACT_FINC_E[14]\, N_66, - N_71, \DWACT_FINC_E[10]\, N_78, \DWACT_FINC_E[11]\, N_83, - N_88, N_93, \DWACT_FINC_E[8]\, N_98, N_106, N_113, - \DWACT_FINC_E[3]\, N_121, N_126, N_131, \DWACT_FINC_E[1]\, - N_136, N_144, N_4_0, N_12, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - hwdata(23) <= \hwdata[23]\; - hwdata(22) <= \hwdata[22]\; - hwdata(21) <= \hwdata[21]\; - hwdata(20) <= \hwdata[20]\; - hwdata(19) <= \hwdata[19]\; - hwdata(18) <= \hwdata[18]\; - hwdata(17) <= \hwdata[17]\; - hwdata(16) <= \hwdata[16]\; - hwdata(15) <= \hwdata[15]\; - hwdata(14) <= \hwdata[14]\; - hwdata(13) <= \hwdata[13]\; - hwdata(12) <= \hwdata[12]\; - hwdata(11) <= \hwdata[11]\; - hwdata(10) <= \hwdata[10]\; - hwdata(9) <= \hwdata[9]\; - hwdata(8) <= \hwdata[8]\; - hwdata(7) <= \hwdata[7]\; - hwdata(6) <= \hwdata[6]\; - hwdata(5) <= \hwdata[5]\; - hwdata(4) <= \hwdata[4]\; - hwdata(3) <= \hwdata[3]\; - hwdata(2) <= \hwdata[2]\; - hwdata(1) <= \hwdata[1]\; - hwdata(0) <= \hwdata[0]\; - state_i(5) <= \state_i[5]\; - haddr(31) <= \haddr[31]\; - haddr(30) <= \haddr[30]\; - haddr(29) <= \haddr[29]\; - haddr(28) <= \haddr[28]\; - haddr(27) <= \haddr[27]\; - haddr(26) <= \haddr[26]\; - haddr(25) <= \haddr[25]\; - haddr(24) <= \haddr[24]\; - haddr(23) <= \haddr[23]\; - haddr(22) <= \haddr[22]\; - haddr(21) <= \haddr[21]\; - haddr(20) <= \haddr[20]\; - haddr(19) <= \haddr[19]\; - haddr(18) <= \haddr[18]\; - haddr(17) <= \haddr[17]\; - haddr(16) <= \haddr[16]\; - haddr(15) <= \haddr[15]\; - haddr(14) <= \haddr[14]\; - haddr(13) <= \haddr[13]\; - haddr(12) <= \haddr[12]\; - haddr(11) <= \haddr[11]\; - haddr(10) <= \haddr[10]\; - haddr(9) <= \haddr[9]\; - haddr(8) <= \haddr[8]\; - haddr(7) <= \haddr[7]\; - haddr(6) <= \haddr[6]\; - haddr(5) <= \haddr[5]\; - haddr(4) <= \haddr[4]\; - haddr(3) <= \haddr[3]\; - haddr(2) <= \haddr[2]\; - haddr(1) <= \haddr[1]\; - haddr(0) <= \haddr[0]\; - N_321 <= \N_321\; - hwrite <= \hwrite\; - write <= \write\; - - \r.state_RNIGGC11[2]\ : AO1A - port map(A => \state[2]\, B => \N_321\, C => N_327, Y => - N_328); - - un5_newaddr_I_172 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[19]\, Y => N_30_0); - - un5_newaddr_I_114 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[12]\, Y => N_71); - - \r.clen_RNO_1[1]\ : AXOI1 - port map(A => N_322, B => N_411_i_1, C => \clen[1]\, Y => - N_664); - - \r.state_RNIPBR32[0]\ : AO1A - port map(A => \state[0]\, B => N_319, C => N_720, Y => - N_308); - - \r.data[27]\ : DFN1E1 - port map(D => N_354, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(27)); - - \r.addr_RNO_0[10]\ : OR2B - port map(A => N_682_0, B => \haddr[10]\, Y => N_445); - - \r.addr[21]\ : DFN1E1 - port map(D => N_635, CLK => lclk_c, E => state_4_0, Q => - \haddr[21]\); - - \r.state_RNI7EEE_0[2]\ : NOR2A - port map(A => \state[2]\, B => thempty, Y => write_1_sqmuxa); - - \r.addr_RNO_1[22]\ : OR2B - port map(A => \state[4]\, B => \haddr[14]\, Y => N_601); - - un5_newaddr_I_87 : AND3 - port map(A => \haddr[14]\, B => \haddr[15]\, C => - \haddr[16]\, Y => \DWACT_FINC_E[9]\); - - un5_newaddr_I_27 : AND2 - port map(A => \haddr[5]\, B => \haddr[6]\, Y => - \DWACT_FINC_E[1]\); - - \r.data[17]\ : DFN1E1 - port map(D => N_375, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[17]\); - - un5_newaddr_I_115 : XOR2 - port map(A => N_71, B => \haddr[20]\, Y => I_115_0); - - \r.addr_RNO[3]\ : NOR3 - port map(A => N_391, B => N_392, C => N_390, Y => N_453); - - \r.len[2]\ : DFN1E1 - port map(D => N_345, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[2]\); - - \r.addr[15]\ : DFN1E1 - port map(D => N_629, CLK => lclk_c, E => state_4_0, Q => - \haddr[15]\); - - \r.addr_RNO[13]\ : OR3C - port map(A => N_460, B => N_652, C => N_461, Y => N_627); - - \r.addr_RNO_2[29]\ : OR2A - port map(A => I_196_0, B => N_680_0, Y => N_429); - - \r.addr_RNO_1[2]\ : NOR2A - port map(A => \state_0[4]\, B => data(2), Y => N_389); - - \r.state_0_RNISCH52[4]\ : OR2A - port map(A => N_308, B => \state_0[4]\, Y => N_680_0); - - \r.addr_RNO_0[20]\ : OR2B - port map(A => N_682_0, B => \haddr[20]\, Y => N_574); - - un5_newaddr_I_128 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[14]\, Y => N_61); - - \r.data[25]\ : DFN1E1 - port map(D => N_352, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(25)); - - un5_newaddr_I_159 : AND3 - port map(A => \haddr[23]\, B => \haddr[24]\, C => - \haddr[25]\, Y => \DWACT_FINC_E[17]\); - - \r.state_0[3]\ : DFN1 - port map(D => \state_0_RNIIOIE4[3]\, CLK => lclk_c, Q => - \state_0[3]\); - - \r.addr_RNO_2[31]\ : OR2A - port map(A => I_210_0, B => N_680_0, Y => N_435); - - \r.addr_RNO[12]\ : OR3C - port map(A => N_457, B => N_459, C => N_458, Y => N_626); - - un5_newaddr_I_196 : XOR2 - port map(A => N_14, B => \haddr[29]\, Y => I_196_0); - - \r.addr[19]\ : DFN1E1 - port map(D => N_633, CLK => lclk_c, E => state_4_0, Q => - \haddr[19]\); - - \r.data[15]\ : DFN1E1 - port map(D => N_640, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[15]\); - - \r.state_RNO_1[0]\ : AOI1 - port map(A => \state[1]\, B => N_318, C => \state[0]\, Y - => N_403); - - \r.addr_RNO_2[17]\ : OR2A - port map(A => I_91_0, B => \state_RNIBAHA2[4]\, Y => N_537); - - \r.addr_RNO_2[6]\ : NOR2A - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[6]\, Y => - N_660); - - \r.clen_RNO[0]\ : NOR3 - port map(A => N_668, B => \clen_1_i_0_0[0]\, C => N_328, Y - => N_450); - - \r.addr_RNO_2[16]\ : OR2A - port map(A => I_84_0, B => \state_RNIBAHA2[4]\, Y => N_498); - - \r.addr_RNO_1[10]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[2]\, Y => N_447); - - \r.clen_RNIKSR6[1]\ : NOR3C - port map(A => N_411_i_1, B => \clen[1]\, C => dready, Y => - N_318); - - \r.addr_RNO[10]\ : OR3C - port map(A => N_445, B => N_447, C => N_446, Y => N_624); - - \r.addr[28]\ : DFN1E1 - port map(D => N_194, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[28]\); - - \r.addr_RNO_0[9]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[9]\, Y => - N_442); - - un5_newaddr_I_206 : AND2 - port map(A => \haddr[29]\, B => \haddr[30]\, Y => - \DWACT_FINC_E[25]\); - - \r.state_RNI1HBD[1]\ : NOR2 - port map(A => \state[4]\, B => \state[1]\, Y => \N_321\); - - \r.addr_RNO_2[11]\ : OR2A - port map(A => I_52_0, B => N_680_0, Y => N_449); - - un5_newaddr_I_165 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[18]\, Y => N_35); - - \r.addr[5]\ : DFN1E1 - port map(D => N_30, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[5]\); - - un5_newaddr_I_13 : XOR2 - port map(A => N_144, B => \haddr[5]\, Y => I_13_6); - - \r.data_RNO[22]\ : MX2 - port map(A => \hwdata[14]\, B => hrdata_0_22, S => - \state_0[3]\, Y => N_349); - - \r.addr_RNO[14]\ : OR3C - port map(A => N_653, B => N_465, C => N_654, Y => N_628); - - un5_newaddr_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \haddr[11]\, C => - \haddr[12]\, Y => N_106); - - un5_newaddr_I_91 : XOR2 - port map(A => N_88, B => \haddr[17]\, Y => I_91_0); - - \r.addr_RNO_2[24]\ : OR2A - port map(A => I_143_0, B => N_680_0, Y => N_414); - - \r.addr_RNO[19]\ : OR3C - port map(A => N_562, B => N_571, C => N_568, Y => N_633); - - un5_newaddr_I_122 : XOR2 - port map(A => N_66, B => \haddr[21]\, Y => I_122_0); - - \r.data[23]\ : DFN1E1 - port map(D => N_350, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[23]\); - - \r.clen_RNO[1]\ : NOR3 - port map(A => N_328, B => \clen_1_i_0_0[1]\, C => N_664, Y - => N_451); - - un5_newaddr_I_5 : XOR2 - port map(A => \haddr[2]\, B => \haddr[3]\, Y => I_5_2); - - \r.state_RNIV8BD[0]\ : OR2 - port map(A => \state[3]\, B => \state[0]\, Y => N_327); - - un5_newaddr_I_118 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[13]\); - - \r.state_RNIJ7F62[1]\ : OR3C - port map(A => \write\, B => N_438, C => N_721, Y => - \state_RNIJ7F62[1]\); - - \r.data[13]\ : DFN1E1 - port map(D => N_370, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[13]\); - - \r.data[20]\ : DFN1E1 - port map(D => N_378, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[20]\); - - \r.data_RNO[26]\ : MX2 - port map(A => \hwdata[18]\, B => hrdata_0_26, S => - \state_0[3]\, Y => N_353); - - \r.addr_RNO_0[8]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[8]\, Y => - N_439); - - un5_newlen_I_9 : XNOR2 - port map(A => N_15, B => \len[2]\, Y => I_9_3); - - \r.state_RNIU4BD[0]\ : NOR2 - port map(A => \state[0]\, B => \state[2]\, Y => - state_4_0_0_0_0); - - \r.len_RNO[4]\ : MX2 - port map(A => data(4), B => I_20_3, S => \state_i[5]\, Y - => N_347); - - \r.data[26]\ : DFN1E1 - port map(D => N_353, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(26)); - - \r.data_RNO[19]\ : MX2 - port map(A => \hwdata[11]\, B => N_264_0, S => \state_0[3]\, - Y => N_377); - - \r.data[10]\ : DFN1E1 - port map(D => N_365, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[10]\); - - un5_newaddr_I_192 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[22]\, Y => \DWACT_FINC_E[23]\); - - \r.data_RNO[18]\ : MX2 - port map(A => \hwdata[10]\, B => hrdata_0_18, S => - \state_0[3]\, Y => N_376); - - \r.state_RNO_2[1]\ : OR3B - port map(A => N_316, B => N_720, C => \un1_rst_0_o4\, Y => - N_401); - - \r.len_RNO[2]\ : MX2 - port map(A => data(2), B => I_9_3, S => \state_i[5]\, Y => - N_345); - - \r.addr_RNO_1[31]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[23]\, Y => N_436); - - \r.data[16]\ : DFN1E1 - port map(D => N_374, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[16]\); - - \r.addr_RNO_0[30]\ : OR2B - port map(A => N_682_0, B => \haddr[30]\, Y => N_431); - - \r.len_RNIS3A[5]\ : OR2A - port map(A => I_24_3, B => \len[5]\, Y => N_316); - - un5_newlen_I_20 : XNOR2 - port map(A => N_7, B => \len[4]\, Y => I_20_3); - - un5_newaddr_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \haddr[7]\, Y => N_131); - - \r.data_RNO[1]\ : MX2 - port map(A => data(1), B => hrdata_0_1, S => \state[3]\, Y - => N_336); - - \r.addr_RNO_1[23]\ : OR2B - port map(A => \state[4]\, B => \haddr[15]\, Y => N_610); - - \r.state_0_RNIIOIE4[3]\ : OR3C - port map(A => \state_srsts_0_i_i_0_1[3]\, B => N_655, C => - N_656, Y => \state_0_RNIIOIE4[3]\); - - \r.len_RNIRKA41[5]\ : OR3B - port map(A => N_316, B => N_722, C => \un1_rst_0_o4\, Y => - N_656); - - \r.addr_RNO_1[25]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[17]\, Y => N_418); - - un5_newaddr_I_166 : XOR2 - port map(A => N_35, B => \haddr[26]\, Y => I_166_0); - - \r.data[30]\ : DFN1E1 - port map(D => N_357, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(30)); - - \r.addr_RNO_0[6]\ : NOR2 - port map(A => I_20_2, B => \state_RNIBAHA2[4]\, Y => N_661); - - \r.addr_RNO_2[22]\ : OR2A - port map(A => I_129_0, B => \state_RNIBAHA2[4]\, Y => N_598); - - \r.addr_RNO[16]\ : OR3C - port map(A => N_491, B => N_532, C => N_498, Y => N_630); - - \r.addr[14]\ : DFN1E1 - port map(D => N_628, CLK => lclk_c, E => state_4_0, Q => - \haddr[14]\); - - \r.addr_RNO_1[4]\ : NOR2A - port map(A => \state[4]\, B => data(4), Y => N_395); - - un5_newaddr_I_45 : XOR2 - port map(A => N_121, B => \haddr[10]\, Y => I_45_0); - - \r.state_RNO[2]\ : AOI1 - port map(A => \state_srsts_0_i_0_i_a2_0[2]\, B => N_721, C - => \un1_rst_0_o4\, Y => \state_RNO[2]\); - - \r.addr_RNO[2]\ : NOR3 - port map(A => N_388, B => N_389, C => N_387, Y => N_452); - - \r.state[1]\ : DFN1 - port map(D => \state_nsss[4]\, CLK => lclk_c, Q => - \state[1]\); - - \r.addr_RNO[8]\ : OR3C - port map(A => N_439, B => N_441, C => N_440, Y => N_622); - - \r.data_RNO[5]\ : MX2 - port map(A => data(5), B => hrdata_0_d0, S => \state[3]\, Y - => N_340); - - \r.data_RNO[11]\ : MX2 - port map(A => \hwdata[3]\, B => hrdata_0_11, S => - \state[3]\, Y => N_367); - - \r.data_RNO[17]\ : MX2 - port map(A => \hwdata[9]\, B => hrdata_0_17, S => - \state_0[3]\, Y => N_375); - - \r.clen_RNO_0[1]\ : OAI1 - port map(A => dready, B => \clen_1_i_0_a2_0_0[1]\, C => - \state_i[5]\, Y => \clen_1_i_0_0[1]\); - - \r.state[2]\ : DFN1 - port map(D => \state_RNO[2]\, CLK => lclk_c, Q => - \state[2]\); - - \r.addr_RNO_2[19]\ : OR2A - port map(A => I_105_0, B => \state_RNIBAHA2[4]\, Y => N_568); - - \r.addr[2]\ : DFN1E1 - port map(D => N_452, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[2]\); - - \r.state_RNO_0[0]\ : NOR3B - port map(A => active, B => iosn_2(93), C => \state[1]\, Y - => N_404); - - \r.state_RNI7EEE[2]\ : OR2B - port map(A => thempty, B => \state[2]\, Y => \write\); - - \r.addr[17]\ : DFN1E1 - port map(D => N_631, CLK => lclk_c, E => state_4_0, Q => - \haddr[17]\); - - un5_newaddr_I_146 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \haddr[23]\, C => - \haddr[24]\, Y => \DWACT_FINC_E[33]\); - - \r.state_i_RNO_1[5]\ : NOR2 - port map(A => \state_i[5]\, B => N_320, Y => N_406); - - \r.addr[13]\ : DFN1E1 - port map(D => N_627, CLK => lclk_c, E => state_4_0, Q => - \haddr[13]\); - - \r.state_RNO[0]\ : NOR3 - port map(A => N_404, B => N_403, C => \un1_rst_0_o4\, Y => - \state_RNO[0]\); - - un5_newaddr_I_203 : XOR2 - port map(A => N_9, B => \haddr[30]\, Y => I_203_0); - - un5_newaddr_I_94 : AND2 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, Y - => \DWACT_FINC_E[10]\); - - GND_i : GND - port map(Y => \GND\); - - un5_newaddr_I_179 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[20]\, Y => \DWACT_FINC_E[21]\); - - \r.addr_RNO[15]\ : OR3C - port map(A => N_487, B => N_490, C => N_489, Y => N_629); - - \r.write\ : DFN1 - port map(D => write_RNO, CLK => lclk_c, Q => \hwrite\); - - \r.addr[12]\ : DFN1E1 - port map(D => N_626, CLK => lclk_c, E => state_4_0, Q => - \haddr[12]\); - - \r.addr[20]\ : DFN1E1 - port map(D => N_634, CLK => lclk_c, E => state_4_0, Q => - \haddr[20]\); - - un5_newaddr_I_73 : XOR2 - port map(A => N_101, B => \haddr[14]\, Y => I_73_0); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un5_newlen_I_16 : OR3 - port map(A => \len[0]\, B => \len[1]\, C => \len[2]\, Y => - \DWACT_FDEC_E[0]\); - - \r.data_RNO[3]\ : MX2 - port map(A => data(3), B => hrdata_0_3, S => \state[3]\, Y - => N_338); - - \r.addr_RNO_1[5]\ : NOR2A - port map(A => \state_0[4]\, B => data(5), Y => N_398); - - un5_newaddr_I_162 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - Y => \DWACT_FINC_E[18]\); - - \r.addr[26]\ : DFN1E1 - port map(D => N_170, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[26]\); - - un5_newaddr_I_101 : AND2 - port map(A => \haddr[17]\, B => \haddr[18]\, Y => - \DWACT_FINC_E[11]\); - - \r.addr_RNO[9]\ : OR3C - port map(A => N_442, B => N_444, C => N_443, Y => N_623); - - \r.state_0_RNIUUDG_0[4]\ : AO1B - port map(A => dready, B => \state_0[4]\, C => - state_4_0_0_0_0, Y => \state_0_RNIUUDG_0[4]\); - - \r.addr_RNO_1[20]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[12]\, Y => N_580); - - \r.data[8]\ : DFN1E1 - port map(D => N_363, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[8]\); - - \r.addr_RNO_2[14]\ : OR2A - port map(A => I_73_0, B => \state_RNIBAHA2[4]\, Y => N_654); - - \r.data_RNO[20]\ : MX2 - port map(A => \hwdata[12]\, B => N_262_0, S => \state[3]\, - Y => N_378); - - un5_newaddr_I_142 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[16]\, Y => N_51); - - \r.addr_RNO_2[23]\ : OR2A - port map(A => I_136_0, B => \state_RNIBAHA2[4]\, Y => N_607); - - \r.addr_RNO_2[25]\ : OR2A - port map(A => I_156_0, B => N_680_0, Y => N_417); - - \r.addr_RNO_0[18]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[18]\, Y - => N_550); - - un5_newaddr_I_209 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[25]\, Y => N_4); - - \r.len[0]\ : DFN1E1 - port map(D => N_343, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[0]\); - - un5_newaddr_I_84 : XOR2 - port map(A => N_93, B => \haddr[16]\, Y => I_84_0); - - un5_newaddr_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \haddr[10]\, C => - \haddr[11]\, Y => N_113); - - un5_newaddr_I_24 : XOR2 - port map(A => N_136, B => \haddr[7]\, Y => I_24_2); - - un5_newaddr_I_185 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[21]\, Y => N_21); - - \r.addr[4]\ : DFN1E1 - port map(D => N_454, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[4]\); - - \r.addr_RNO_2[7]\ : NOR2A - port map(A => N_682_0, B => \haddr[7]\, Y => N_409); - - un5_newaddr_I_129 : XOR2 - port map(A => N_61, B => \haddr[22]\, Y => I_129_0); - - \r.data[1]\ : DFN1E1 - port map(D => N_336, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[1]\); - - \r.addr_RNO_2[12]\ : OR2A - port map(A => I_56_0, B => \state_RNIBAHA2[4]\, Y => N_458); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.addr_RNO_0[28]\ : OR2B - port map(A => N_682_0, B => \haddr[28]\, Y => N_425); - - \r.addr[31]\ : DFN1E1 - port map(D => N_621, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[31]\); - - \r.data[0]\ : DFN1E1 - port map(D => N_335, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[0]\); - - \r.addr_RNO[18]\ : OR3C - port map(A => N_550, B => N_558, C => N_554, Y => N_632); - - \r.addr[9]\ : DFN1E1 - port map(D => N_623, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[9]\); - - \r.data[3]\ : DFN1E1 - port map(D => N_338, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[3]\); - - un5_newaddr_I_199 : AND2 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - Y => \DWACT_FINC_E[24]\); - - \r.addr_RNO[7]\ : NOR3 - port map(A => N_410, B => N_650, C => N_409, Y => N_39); - - un5_newlen_I_12 : OR3 - port map(A => \len[0]\, B => \len[1]\, C => \len[2]\, Y => - N_12); - - \r.state_RNI2BKH1[2]\ : OR3C - port map(A => active, B => iosn_0(93), C => - \state_srsts_0_i_i_0_o2_0[3]\, Y => N_325); - - un5_newaddr_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \haddr[8]\, Y => N_126); - - \r.write_RNO_0\ : MX2 - port map(A => data(6), B => \hwrite\, S => write_0_sqmuxa_0, - Y => N_215); - - \r.addr_RNO_1[18]\ : OR2B - port map(A => \state[4]\, B => \haddr[10]\, Y => N_558); - - \r.addr_RNO[5]\ : NOR3 - port map(A => N_397, B => N_398, C => N_396, Y => N_30); - - \r.data_RNO[30]\ : MX2 - port map(A => \hwdata[22]\, B => hrdata_25, S => - \state_0[3]\, Y => N_357); - - \r.addr_RNO_2[8]\ : OR2A - port map(A => I_31_2, B => \state_RNIBAHA2[4]\, Y => N_440); - - \r.addr_RNO_0[17]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[17]\, Y - => N_535); - - \r.data_RNO[13]\ : MX2 - port map(A => \hwdata[5]\, B => hrdata_0_13, S => - \state[3]\, Y => N_370); - - \r.addr_RNO_2[3]\ : NOR2A - port map(A => N_682_0, B => \haddr[3]\, Y => N_390); - - \r.addr[25]\ : DFN1E1 - port map(D => N_620, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[25]\); - - un5_newaddr_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - \r.clen[1]\ : DFN1E0 - port map(D => N_451, CLK => lclk_c, E => write_1_sqmuxa, Q - => \clen[1]\); - - un5_newaddr_I_186 : XOR2 - port map(A => N_21, B => \haddr[28]\, Y => I_186_0); - - \r.addr_RNO_0[16]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[16]\, Y - => N_491); - - un5_newaddr_I_98 : XOR2 - port map(A => N_83, B => \haddr[18]\, Y => I_98_0); - - \r.data_RNO[6]\ : MX2 - port map(A => data(6), B => hrdata_1, S => \state[3]\, Y - => N_341); - - \r.state_RNIJNB8[2]\ : NOR2 - port map(A => \state[2]\, B => \state_0[4]\, Y => - \state_srsts_0_i_i_0_o2_0[3]\); - - \r.addr_RNO_0[11]\ : OR2B - port map(A => N_682_0, B => \haddr[11]\, Y => N_448); - - \r.len_RNO[5]\ : MX2 - port map(A => data(5), B => I_24_3, S => \state_i[5]\, Y - => N_348); - - \r.addr_RNO_0[27]\ : OR2B - port map(A => N_682_0, B => \haddr[27]\, Y => N_422); - - \r.addr[29]\ : DFN1E1 - port map(D => N_204, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[29]\); - - \r.addr_RNO_2[5]\ : NOR2A - port map(A => N_682_0, B => \haddr[5]\, Y => N_396); - - un5_newaddr_I_69 : AND3 - port map(A => \haddr[11]\, B => \haddr[12]\, C => - \haddr[13]\, Y => \DWACT_FINC_E[7]\); - - \r.addr_RNO_2[20]\ : OR2A - port map(A => I_115_0, B => N_680_0, Y => N_577); - - un5_newaddr_I_210 : XOR2 - port map(A => N_4, B => \haddr[31]\, Y => I_210_0); - - \r.addr_RNO_0[26]\ : OR2B - port map(A => N_682_0, B => \haddr[26]\, Y => N_419); - - \r.data[4]\ : DFN1E1 - port map(D => N_339, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[4]\); - - \r.addr_RNO_1[7]\ : NOR2A - port map(A => \state_0[4]\, B => data(7), Y => N_650); - - \r.len_RNO[0]\ : MX2B - port map(A => data(0), B => \len[0]\, S => \state_i[5]\, Y - => N_343); - - \r.addr_RNO_0[2]\ : NOR2A - port map(A => \haddr[2]\, B => N_680_0, Y => N_388); - - \r.addr_RNO_0[21]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[21]\, Y - => N_583); - - \r.addr[3]\ : DFN1E1 - port map(D => N_453, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[3]\); - - \r.state_RNICB28[1]\ : OR2B - port map(A => dready, B => \state[1]\, Y => N_438); - - \r.state_RNIBAHA2[4]\ : OR2A - port map(A => N_308, B => \state[4]\, Y => - \state_RNIBAHA2[4]\); - - \r.addr_RNO_1[9]\ : OR2B - port map(A => \state[4]\, B => \haddr[1]\, Y => N_444); - - un5_newaddr_I_9 : XOR2 - port map(A => N_147, B => \haddr[4]\, Y => I_9_2); - - \r.addr_RNO[27]\ : OR3C - port map(A => N_422, B => N_424, C => N_423, Y => N_172); - - \r.addr_RNO_1[17]\ : OR2B - port map(A => \state[4]\, B => \haddr[9]\, Y => N_546); - - \r.state_0[4]\ : DFN1 - port map(D => \state_i_RNIIHN51[5]\, CLK => lclk_c, Q => - \state_0[4]\); - - \r.data_RNO[0]\ : MX2 - port map(A => data(0), B => hrdata_0_0, S => \state_0[3]\, - Y => N_335); - - un5_newaddr_I_135 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[15]\, Y => N_56); - - \r.addr_RNO_1[16]\ : OR2B - port map(A => \state[4]\, B => \haddr[8]\, Y => N_532); - - \r.addr_RNO[6]\ : NOR3 - port map(A => N_661, B => N_662, C => N_660, Y => N_32); - - un5_newaddr_I_169 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \haddr[26]\, Y => \DWACT_FINC_E[19]\); - - \r.addr_RNO_2[13]\ : OR2A - port map(A => I_66_0, B => \state_RNIBAHA2[4]\, Y => N_461); - - \r.addr_RNO_1[11]\ : OR2B - port map(A => \state[4]\, B => \haddr[3]\, Y => N_456); - - un5_newaddr_I_173 : XOR2 - port map(A => N_30_0, B => \haddr[27]\, Y => I_173_0); - - \r.addr_RNO_2[15]\ : OR2A - port map(A => I_77_0, B => \state_RNIBAHA2[4]\, Y => N_489); - - un5_newaddr_I_12 : AND3 - port map(A => \haddr[2]\, B => \haddr[3]\, C => \haddr[4]\, - Y => N_144); - - \r.state_i_RNIER5C[5]\ : OA1C - port map(A => N_320, B => \state_i[5]\, C => \state[4]\, Y - => N_407); - - \r.data_RNO[29]\ : MX2 - port map(A => \hwdata[21]\, B => hrdata_24, S => - \state_0[3]\, Y => N_356); - - \r.state_RNO_3[1]\ : NOR2B - port map(A => \hwrite\, B => N_318, Y => - \state_srsts_0_0_0_a2_5_0[1]\); - - \r.data_RNO[28]\ : MX2 - port map(A => \hwdata[20]\, B => hrdata_23, S => - \state_0[3]\, Y => N_355); - - \r.addr_RNO[21]\ : OR3C - port map(A => N_583, B => N_592, C => N_589, Y => N_635); - - un5_newaddr_I_182 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[30]\); - - \r.data_RNO[15]\ : MX2 - port map(A => \hwdata[7]\, B => hrdata_0_15, S => - \state[3]\, Y => N_640); - - \r.clen_RNO_0[0]\ : NOR2A - port map(A => N_411_i_1, B => N_322, Y => N_668); - - un5_newaddr_I_104 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \DWACT_FINC_E[11]\, Y => N_78); - - un5_newaddr_I_19 : NOR2B - port map(A => \haddr[5]\, B => \DWACT_FINC_E[0]\, Y => - N_139); - - \r.addr_RNO_2[4]\ : NOR2A - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[4]\, Y => - N_393); - - un5_newaddr_I_77 : XOR2 - port map(A => N_98, B => \haddr[15]\, Y => I_77_0); - - un5_newaddr_I_149 : AND3 - port map(A => \haddr[2]\, B => \haddr[3]\, C => \haddr[4]\, - Y => \DWACT_FINC_E[34]\); - - un5_newaddr_I_105 : XOR2 - port map(A => N_78, B => \haddr[19]\, Y => I_105_0); - - \r.addr_RNO_0[19]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[19]\, Y - => N_562); - - \r.addr[24]\ : DFN1E1 - port map(D => N_619, CLK => lclk_c, E => state_4_0, Q => - \haddr[24]\); - - un5_newaddr_I_66 : XOR2 - port map(A => N_106, B => \haddr[13]\, Y => I_66_0); - - \r.data_RNO[21]\ : MX2 - port map(A => \hwdata[13]\, B => hrdata_0_21, S => - \state[3]\, Y => N_379); - - un5_newaddr_I_41 : AND2 - port map(A => \haddr[8]\, B => \haddr[9]\, Y => - \DWACT_FINC_E[3]\); - - \r.data_RNO[27]\ : MX2 - port map(A => \hwdata[19]\, B => hrdata_0_27, S => - \state_0[3]\, Y => N_354); - - un5_newaddr_I_136 : XOR2 - port map(A => N_56, B => \haddr[23]\, Y => I_136_0); - - \r.len[1]\ : DFN1E1 - port map(D => N_344, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[1]\); - - \r.addr_RNO_0[3]\ : NOR2 - port map(A => I_5_2, B => N_680_0, Y => N_391); - - un5_newaddr_I_8 : NOR2B - port map(A => \haddr[3]\, B => \haddr[2]\, Y => N_147); - - \r.addr_RNO_0[31]\ : OR2B - port map(A => N_682_0, B => \haddr[31]\, Y => N_434); - - \r.addr_RNO[4]\ : NOR3 - port map(A => N_394, B => N_395, C => N_393, Y => N_454); - - \r.data_RNO[14]\ : MX2 - port map(A => \hwdata[6]\, B => hrdata_0_14, S => - \state[3]\, Y => N_372); - - \r.clen_RNO_1[0]\ : OAI1 - port map(A => dready, B => \clen_1_i_0_a2_0_0[0]\, C => - \state_i[5]\, Y => \clen_1_i_0_0[0]\); - - \r.addr_RNO_2[30]\ : OR2A - port map(A => I_203_0, B => N_680_0, Y => N_432); - - \r.state_0_RNI57D32[3]\ : OR3B - port map(A => N_325, B => \state_0[3]\, C => \un1_rst_0_o4\, - Y => N_655); - - \r.addr_RNO_0[29]\ : OR2B - port map(A => N_682_0, B => \haddr[29]\, Y => N_428); - - \r.addr[11]\ : DFN1E1 - port map(D => N_625, CLK => lclk_c, E => state_4_0, Q => - \haddr[11]\); - - un5_newaddr_I_31 : XOR2 - port map(A => N_131, B => \haddr[8]\, Y => I_31_2); - - \r.addr[30]\ : DFN1E1 - port map(D => N_212, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[30]\); - - \r.addr_RNO[23]\ : OR3C - port map(A => N_604, B => N_610, C => N_607, Y => N_637); - - \r.addr[6]\ : DFN1E1 - port map(D => N_32, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[6]\); - - un5_newaddr_I_155 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[33]\, Y => N_42); - - \r.state_RNI07BE[0]\ : OR2A - port map(A => N_327, B => active, Y => hbusreq_i_3); - - \r.addr[27]\ : DFN1E1 - port map(D => N_172, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[27]\); - - \r.data_RNO[7]\ : MX2 - port map(A => data(7), B => hrdata_0_7, S => \state_0[3]\, - Y => N_342); - - \r.addr_RNO_1[8]\ : OR2B - port map(A => \state[4]\, B => \haddr[0]\, Y => N_441); - - \r.addr_RNO_1[28]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[20]\, Y => N_427); - - \r.addr[23]\ : DFN1E1 - port map(D => N_637, CLK => lclk_c, E => state_4_0, Q => - \haddr[23]\); - - \r.data[22]\ : DFN1E1 - port map(D => N_349, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[22]\); - - \r.addr_RNO[22]\ : OR3C - port map(A => N_595, B => N_601, C => N_598, Y => N_636); - - \r.addr[0]\ : DFN1E0 - port map(D => data(0), CLK => lclk_c, E => - \state_RNIGT3N[4]\, Q => \haddr[0]\); - - \r.state[4]\ : DFN1 - port map(D => \state_i_RNIIHN51[5]\, CLK => lclk_c, Q => - \state[4]\); - - \r.data[12]\ : DFN1E1 - port map(D => N_368, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[12]\); - - \r.addr_RNO_2[10]\ : OR2A - port map(A => I_45_0, B => N_680_0, Y => N_446); - - \r.addr[22]\ : DFN1E1 - port map(D => N_636, CLK => lclk_c, E => state_4_0, Q => - \haddr[22]\); - - un5_newaddr_I_121 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \haddr[20]\, Y => N_66); - - \r.addr_RNO_1[19]\ : OR2B - port map(A => \state[4]\, B => \haddr[11]\, Y => N_571); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.addr_RNO_0[14]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[14]\, Y - => N_653); - - un5_newaddr_I_52 : XOR2 - port map(A => N_116, B => \haddr[11]\, Y => I_52_0); - - un5_newaddr_I_90 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[9]\, Y => N_88); - - un5_newlen_I_23 : OR3 - port map(A => \DWACT_FDEC_E[0]\, B => \len[3]\, C => - \len[4]\, Y => N_4_0); - - \r.addr_RNO_2[2]\ : NOR2A - port map(A => N_682_0, B => \haddr[2]\, Y => N_387); - - \r.addr_RNO[20]\ : OR3C - port map(A => N_574, B => N_580, C => N_577, Y => N_634); - - \r.state_0_RNIUUDG[4]\ : AO1B - port map(A => dready, B => \state_0[4]\, C => - state_4_0_0_0_0, Y => state_4_0); - - \r.len_RNO[3]\ : MX2 - port map(A => data(3), B => I_13_7, S => \state_i[5]\, Y - => N_346); - - \r.data_RNO[31]\ : MX2 - port map(A => \hwdata[23]\, B => hrdata_26, S => - \state_0[3]\, Y => N_358); - - \r.addr_RNO_1[6]\ : NOR2A - port map(A => \state[4]\, B => data(6), Y => N_662); - - un5_newaddr_I_108 : AND3 - port map(A => \haddr[17]\, B => \haddr[18]\, C => - \haddr[19]\, Y => \DWACT_FINC_E[12]\); - - un5_newaddr_I_16 : AND3 - port map(A => \haddr[2]\, B => \haddr[3]\, C => \haddr[4]\, - Y => \DWACT_FINC_E[0]\); - - un5_newaddr_I_72 : NOR2B - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y - => N_101); - - \r.addr[18]\ : DFN1E1 - port map(D => N_632, CLK => lclk_c, E => state_4_0, Q => - \haddr[18]\); - - un5_newaddr_I_132 : AND3 - port map(A => \haddr[20]\, B => \haddr[21]\, C => - \haddr[22]\, Y => \DWACT_FINC_E[15]\); - - \r.state_RNIBAHA2_0[4]\ : NOR2 - port map(A => \state[4]\, B => N_308, Y => - \state_RNIBAHA2_0[4]\); - - \r.state[0]\ : DFN1 - port map(D => \state_RNO[0]\, CLK => lclk_c, Q => - \state[0]\); - - \r.addr_RNO[24]\ : OR3C - port map(A => N_413, B => N_415, C => N_414, Y => N_619); - - \r.addr_RNO_0[24]\ : OR2B - port map(A => N_682_0, B => \haddr[24]\, Y => N_413); - - un5_newaddr_I_59 : AND3 - port map(A => \haddr[8]\, B => \haddr[9]\, C => \haddr[10]\, - Y => \DWACT_FINC_E[5]\); - - \r.state_RNO_1[1]\ : OR3A - port map(A => \state[1]\, B => N_318, C => \un1_rst_0_o4\, - Y => N_400); - - un5_newaddr_I_156 : XOR2 - port map(A => N_42, B => \haddr[25]\, Y => I_156_0); - - \r.addr_RNO[29]\ : OR3C - port map(A => N_428, B => N_430, C => N_429, Y => N_204); - - un5_newaddr_I_83 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[8]\, Y => N_93); - - un5_newaddr_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \haddr[5]\, C => - \haddr[6]\, Y => N_136); - - \r.addr_RNO_1[27]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[19]\, Y => N_424); - - un5_newaddr_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_121); - - \r.addr_RNO_1[30]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[22]\, Y => N_433); - - \r.data_RNO[12]\ : MX2 - port map(A => \hwdata[4]\, B => hrdata_0_12, S => - \state[3]\, Y => N_368); - - \r.data[9]\ : DFN1E1 - port map(D => N_639, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[9]\); - - \r.addr_RNO_0[12]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[12]\, Y - => N_457); - - \r.addr_RNO_1[26]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[18]\, Y => N_421); - - \r.addr_RNO_0[7]\ : NOR2 - port map(A => I_24_2, B => N_680_0, Y => N_410); - - \r.state_0_RNISCH52_0[4]\ : NOR2 - port map(A => \state_0[4]\, B => N_308, Y => N_682_0); - - \r.addr_RNO_1[14]\ : OR2B - port map(A => \state[4]\, B => \haddr[6]\, Y => N_465); - - un5_newaddr_I_111 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\); - - un1_rst_0_o4 : OR3C - port map(A => tcnt(0), B => tcnt(1), C => rstn, Y => - \un1_rst_0_o4\); - - \r.len[4]\ : DFN1E1 - port map(D => N_347, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[4]\); - - \r.addr_RNO_1[21]\ : OR2B - port map(A => \state[4]\, B => \haddr[13]\, Y => N_592); - - un5_newaddr_I_34 : AND3 - port map(A => \haddr[5]\, B => \haddr[6]\, C => \haddr[7]\, - Y => \DWACT_FINC_E[2]\); - - \r.clen[0]\ : DFN1E0 - port map(D => N_450, CLK => lclk_c, E => write_1_sqmuxa, Q - => N_411_i_1); - - un5_newaddr_I_51 : NOR2B - port map(A => \haddr[10]\, B => \DWACT_FINC_E[4]\, Y => - N_116); - - \r.data[28]\ : DFN1E1 - port map(D => N_355, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(28)); - - \r.state_RNIGT3N[4]\ : OR2B - port map(A => state_4_0, B => \state[4]\, Y => - \state_RNIGT3N[4]\); - - \r.addr_RNO_0[4]\ : NOR2 - port map(A => I_9_2, B => \state_RNIBAHA2[4]\, Y => N_394); - - \r.addr_RNO_0[22]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[22]\, Y - => N_595); - - \r.addr[1]\ : DFN1E0 - port map(D => data(1), CLK => lclk_c, E => - \state_RNIGT3N[4]\, Q => \haddr[1]\); - - \r.len[3]\ : DFN1E1 - port map(D => N_346, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[3]\); - - \r.data_RNO[16]\ : MX2 - port map(A => \hwdata[8]\, B => hrdata_0_16, S => - \state_0[3]\, Y => N_374); - - \r.data[18]\ : DFN1E1 - port map(D => N_376, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[18]\); - - \r.addr_RNO[26]\ : OR3C - port map(A => N_419, B => N_421, C => N_420, Y => N_170); - - \r.state[3]\ : DFN1 - port map(D => \state_0_RNIIOIE4[3]\, CLK => lclk_c, Q => - \state[3]\); - - un5_newaddr_I_80 : AND2 - port map(A => \haddr[14]\, B => \haddr[15]\, Y => - \DWACT_FINC_E[8]\); - - un5_newaddr_I_20 : XOR2 - port map(A => N_139, B => \haddr[6]\, Y => I_20_2); - - un5_newaddr_I_189 : AND3 - port map(A => \haddr[26]\, B => \haddr[27]\, C => - \haddr[28]\, Y => \DWACT_FINC_E[22]\); - - \r.state_RNIU9OE[1]\ : NOR2 - port map(A => dready, B => \N_321\, Y => N_322); - - \r.addr_RNO_2[9]\ : OR2A - port map(A => I_38_0, B => \state_RNIBAHA2[4]\, Y => N_443); - - \r.state_i_RNIIHN51[5]\ : NOR3 - port map(A => N_408, B => N_407, C => \un1_rst_0_o4\, Y => - \state_i_RNIIHN51[5]\); - - \r.data[29]\ : DFN1E1 - port map(D => N_356, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(29)); - - un5_newlen_I_5 : XNOR2 - port map(A => \len[0]\, B => \len[1]\, Y => I_5_3); - - \r.state_i_RNO[5]\ : NOR3 - port map(A => N_405, B => N_406, C => \un1_rst_0_o4\, Y => - \state_i_RNO[5]\); - - \r.addr_RNO_2[28]\ : OR2A - port map(A => I_186_0, B => N_680_0, Y => N_426); - - \r.data[24]\ : DFN1E1 - port map(D => N_351, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(24)); - - \r.addr_RNO_1[12]\ : OR2B - port map(A => \state[4]\, B => \haddr[4]\, Y => N_459); - - \r.data_RNO[23]\ : MX2 - port map(A => \hwdata[15]\, B => hrdata_0_23, S => - \state[3]\, Y => N_350); - - \r.data[19]\ : DFN1E1 - port map(D => N_377, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[19]\); - - un5_newaddr_I_152 : AND3 - port map(A => \DWACT_FINC_E[34]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[29]\); - - \r.state_RNIT1UF1[0]\ : NOR3C - port map(A => active, B => iosn_2(93), C => \state[0]\, Y - => N_720); - - \r.addr[8]\ : DFN1E1 - port map(D => N_622, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[8]\); - - un5_newlen_I_19 : OR2 - port map(A => \len[3]\, B => \DWACT_FDEC_E[0]\, Y => N_7); - - \r.len[5]\ : DFN1E1 - port map(D => N_348, CLK => lclk_c, E => write_0_sqmuxa, Q - => \len[5]\); - - \r.data[14]\ : DFN1E1 - port map(D => N_372, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[14]\); - - \r.addr_RNO[31]\ : OR3C - port map(A => N_434, B => N_436, C => N_435, Y => N_621); - - un5_newlen_I_8 : OR2 - port map(A => \len[1]\, B => \len[0]\, Y => N_15); - - un5_newaddr_I_56 : XOR2 - port map(A => N_113, B => \haddr[12]\, Y => I_56_0); - - \r.data[6]\ : DFN1E1 - port map(D => N_341, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[6]\); - - \r.data[21]\ : DFN1E1 - port map(D => N_379, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[21]\); - - un5_newlen_I_13 : XNOR2 - port map(A => N_12, B => \len[3]\, Y => I_13_7); - - \r.state_RNO_0[2]\ : AO1C - port map(A => \state_0[3]\, B => N_319, C => \state[2]\, Y - => \state_srsts_0_i_0_i_a2_0[2]\); - - \r.state_0_RNIISQ61[4]\ : OR3B - port map(A => \state_0[4]\, B => - \state_srsts_0_i_i_0_1_tz[3]\, C => \un1_rst_0_o4\, Y => - \state_srsts_0_i_i_0_1[3]\); - - \r.state_nsss_i_i_0_0_o2[0]\ : NOR2B - port map(A => dready, B => data(7), Y => N_320); - - \r.addr[7]\ : DFN1E1 - port map(D => N_39, CLK => lclk_c, E => - \state_0_RNIUUDG_0[4]\, Q => \haddr[7]\); - - \r.write_RNIES1L\ : AO1A - port map(A => \hwrite\, B => N_318, C => \state[2]\, Y => - \state_srsts_0_i_i_0_1_tz[3]\); - - \r.data[11]\ : DFN1E1 - port map(D => N_367, CLK => lclk_c, E => data_0_sqmuxa_0, Q - => \hwdata[11]\); - - \r.state_RNO_0[1]\ : OR3B - port map(A => \state_0[4]\, B => - \state_srsts_0_0_0_a2_5_0[1]\, C => \un1_rst_0_o4\, Y => - N_402); - - \r.state_i_RNI77R72[5]\ : OR3A - port map(A => write_0_sqmuxa_0, B => N_720, C => N_722, Y - => write_0_sqmuxa); - - \r.addr_RNO[25]\ : OR3C - port map(A => N_416, B => N_418, C => N_417, Y => N_620); - - \r.data[2]\ : DFN1E1 - port map(D => N_337, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[2]\); - - un5_newaddr_I_76 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \haddr[14]\, Y => N_98); - - \r.len_RNO[1]\ : MX2 - port map(A => data(1), B => I_5_3, S => \state_i[5]\, Y => - N_344); - - \r.addr_RNO_0[5]\ : NOR2 - port map(A => I_13_6, B => N_680_0, Y => N_397); - - un5_newaddr_I_143 : XOR2 - port map(A => N_51, B => \haddr[24]\, Y => I_143_0); - - \r.data_RNO[2]\ : MX2 - port map(A => data(2), B => hrdata_0_2, S => \state[3]\, Y - => N_337); - - \r.data[31]\ : DFN1E1 - port map(D => N_358, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => hwdata(31)); - - \r.addr[10]\ : DFN1E1 - port map(D => N_624, CLK => lclk_c, E => state_4_0, Q => - \haddr[10]\); - - \r.addr_RNO_1[29]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[21]\, Y => N_430); - - \r.clen_RNO_2[1]\ : OR2 - port map(A => \clen[1]\, B => \state[2]\, Y => - \clen_1_i_0_a2_0_0[1]\); - - \r.addr_RNO_2[27]\ : OR2A - port map(A => I_173_0, B => N_680_0, Y => N_423); - - \r.addr_RNO_0[13]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[13]\, Y - => N_460); - - \r.state_RNIJ7F62_0[1]\ : OR3C - port map(A => \write\, B => N_438, C => N_721, Y => - data_0_sqmuxa_0); - - \r.addr[16]\ : DFN1E1 - port map(D => N_630, CLK => lclk_c, E => state_4_0, Q => - \haddr[16]\); - - \r.addr_RNO_0[15]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[15]\, Y - => N_487); - - \r.addr_RNO_2[26]\ : OR2A - port map(A => I_166_0, B => N_680_0, Y => N_420); - - un5_newaddr_I_176 : AND2 - port map(A => \haddr[26]\, B => \haddr[27]\, Y => - \DWACT_FINC_E[20]\); - - \r.state_i_RNICJV3[5]\ : OR2A - port map(A => dready, B => \state_i[5]\, Y => - write_0_sqmuxa_0); - - \r.addr_RNO_2[21]\ : OR2A - port map(A => I_122_0, B => \state_RNIBAHA2[4]\, Y => N_589); - - \r.write_RNO\ : NOR2A - port map(A => N_215, B => \un1_rst_0_o4\, Y => write_RNO); - - \r.addr_RNO[17]\ : OR3C - port map(A => N_535, B => N_546, C => N_537, Y => N_631); - - \r.data_RNO[9]\ : MX2 - port map(A => \hwdata[1]\, B => hrdata_0_9, S => \state[3]\, - Y => N_639); - - \r.clen_RNO_2[0]\ : OR2 - port map(A => N_411_i_1, B => \state[2]\, Y => - \clen_1_i_0_a2_0_0[0]\); - - un5_newaddr_I_97 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \haddr[17]\, Y => N_83); - - \r.data[7]\ : DFN1E1 - port map(D => N_342, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[7]\); - - \r.addr_RNO_0[23]\ : OR2B - port map(A => \state_RNIBAHA2_0[4]\, B => \haddr[23]\, Y - => N_604); - - un5_newlen_I_24 : XNOR2 - port map(A => N_4_0, B => \len[5]\, Y => I_24_3); - - \r.addr_RNO_0[25]\ : OR2B - port map(A => N_682_0, B => \haddr[25]\, Y => N_416); - - un5_newaddr_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un5_newaddr_I_202 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \haddr[29]\, Y => N_9); - - \r.state_RNIUHTJ[2]\ : NOR2B - port map(A => \state[2]\, B => N_319, Y => N_722); - - \r.data_RNO[25]\ : MX2 - port map(A => \hwdata[17]\, B => N_78_0, S => \state[3]\, Y - => N_352); - - un5_newaddr_I_139 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \haddr[23]\, Y => - \DWACT_FINC_E[16]\); - - un5_newaddr_I_125 : AND2 - port map(A => \haddr[20]\, B => \haddr[21]\, Y => - \DWACT_FINC_E[14]\); - - \r.data[5]\ : DFN1E1 - port map(D => N_340, CLK => lclk_c, E => - \state_RNIJ7F62[1]\, Q => \hwdata[5]\); - - \r.addr_RNO[30]\ : OR3C - port map(A => N_431, B => N_433, C => N_432, Y => N_212); - - un5_newaddr_I_38 : XOR2 - port map(A => N_126, B => \haddr[9]\, Y => I_38_0); - - \r.state_i_RNO_0[5]\ : OA1B - port map(A => N_720, B => N_722, C => N_316, Y => N_405); - - \r.data_RNO[10]\ : MX2 - port map(A => \hwdata[2]\, B => hrdata_0_10, S => - \state_0[3]\, Y => N_365); - - \r.addr_RNO[11]\ : OR3C - port map(A => N_448, B => N_456, C => N_449, Y => N_625); - - \r.addr_RNO_1[24]\ : OR2B - port map(A => \state_0[4]\, B => \haddr[16]\, Y => N_415); - - \r.addr_RNO_1[13]\ : OR2B - port map(A => \state[4]\, B => \haddr[5]\, Y => N_652); - - \r.state_RNO[1]\ : OR3C - port map(A => N_402, B => N_400, C => N_401, Y => - \state_nsss[4]\); - - \r.data_RNO[4]\ : MX2 - port map(A => data(4), B => hrdata_0_4, S => \state[3]\, Y - => N_339); - - \r.clen_RNIER7D[1]\ : NOR3C - port map(A => N_411_i_1, B => \clen[1]\, C => thempty, Y - => N_319); - - \r.addr_RNO_1[15]\ : OR2B - port map(A => \state[4]\, B => \haddr[7]\, Y => N_490); - - \r.state_i[5]\ : DFN1 - port map(D => \state_i_RNO[5]\, CLK => lclk_c, Q => - \state_i[5]\); - - \r.state_RNI0EUF1[3]\ : OR3C - port map(A => active, B => iosn_2(93), C => \state[3]\, Y - => N_721); - - \r.addr_RNO[28]\ : OR3C - port map(A => N_425, B => N_427, C => N_426, Y => N_194); - - un5_newaddr_I_195 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[23]\, Y => N_14); - - \r.state_i_RNI3NE9[5]\ : NOR2B - port map(A => \state_i[5]\, B => N_318, Y => N_408); - - \r.addr_RNO_1[3]\ : NOR2A - port map(A => \state_0[4]\, B => data(3), Y => N_392); - - \r.addr_RNO_2[18]\ : OR2A - port map(A => I_98_0, B => \state_RNIBAHA2[4]\, Y => N_554); - - \r.data_RNO[8]\ : MX2 - port map(A => \hwdata[0]\, B => hrdata_0_8, S => - \state_0[3]\, Y => N_363); - - \r.data_RNO[24]\ : MX2 - port map(A => \hwdata[16]\, B => hrdata_0_24, S => - \state_0[3]\, Y => N_351); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbmst is - - port( iosn : in std_logic_vector(93 to 93); - hgrant : in std_logic_vector(1 to 1); - htrans : out std_logic_vector(1 to 1); - iosn_2 : in std_logic_vector(93 to 93); - lclk_c : in std_logic; - hbusreq_i_3 : in std_logic; - active : out std_logic; - rstn : in std_logic - ); - -end ahbmst; - -architecture DEF_ARCH of ahbmst is - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal retry_RNO, retry, N_603, \active\, active_2, grant, - \htrans[1]\, active_RNO, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - htrans(1) <= \htrans[1]\; - active <= \active\; - - \r.retry\ : DFN1 - port map(D => retry_RNO, CLK => lclk_c, Q => retry); - - \r.active\ : DFN1 - port map(D => active_RNO, CLK => lclk_c, Q => \active\); - - \r.active_RNO_1\ : NOR2B - port map(A => grant, B => \htrans[1]\, Y => active_2); - - \r.active_RNO\ : NOR2B - port map(A => rstn, B => N_603, Y => active_RNO); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.retry_RNI3F2G\ : NOR2 - port map(A => retry, B => hbusreq_i_3, Y => \htrans[1]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.retry_RNO\ : NOR3B - port map(A => retry, B => rstn, C => \active\, Y => - retry_RNO); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \r.grant\ : DFN1E1 - port map(D => hgrant(1), CLK => lclk_c, E => iosn(93), Q - => grant); - - \r.active_RNO_0\ : MX2 - port map(A => \active\, B => active_2, S => iosn_2(93), Y - => N_603); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbuart is - - port( haddr : out std_logic_vector(31 downto 0); - iosn_0 : in std_logic_vector(93 to 93); - hrdata_0_0 : in std_logic; - hrdata_0_24 : in std_logic; - hrdata_0_26 : in std_logic; - hrdata_0_27 : in std_logic; - hrdata_0_8 : in std_logic; - hrdata_0_16 : in std_logic; - hrdata_0_18 : in std_logic; - hrdata_0_10 : in std_logic; - hrdata_0_22 : in std_logic; - hrdata_0_7 : in std_logic; - hrdata_0_17 : in std_logic; - hrdata_0_23 : in std_logic; - hrdata_0_3 : in std_logic; - hrdata_0_11 : in std_logic; - hrdata_0_12 : in std_logic; - hrdata_0_4 : in std_logic; - hrdata_0_21 : in std_logic; - hrdata_0_15 : in std_logic; - hrdata_0_14 : in std_logic; - hrdata_0_13 : in std_logic; - hrdata_0_9 : in std_logic; - hrdata_0_2 : in std_logic; - hrdata_0_1 : in std_logic; - hrdata_23 : in std_logic; - hrdata_25 : in std_logic; - hrdata_26 : in std_logic; - hrdata_24 : in std_logic; - hrdata_1 : in std_logic; - hrdata_0_d0 : in std_logic; - pwdata_0 : in std_logic_vector(15 downto 0); - un1_dcom0 : out std_logic_vector(19 downto 12); - pwdata : in std_logic_vector(17 downto 16); - psel_1 : in std_logic_vector(7 to 7); - prdata_0 : out std_logic; - prdata_5 : out std_logic; - pwdata_1 : in std_logic_vector(4 to 4); - paddr : in std_logic_vector(3 downto 2); - hwdata : out std_logic_vector(31 downto 0); - iosn_2 : in std_logic_vector(93 to 93); - htrans : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(1 to 1); - iosn : in std_logic_vector(93 to 93); - hwrite : out std_logic; - N_264_0 : in std_logic; - N_262_0 : in std_logic; - N_78_0 : in std_logic; - N_78 : in std_logic; - un1_apbi_0 : in std_logic; - N_86 : out std_logic; - rdata60_1 : in std_logic; - N_85 : out std_logic; - dsutx_c : out std_logic; - N_6455_0 : in std_logic; - N_332 : out std_logic; - N_333 : out std_logic; - N_334 : out std_logic; - N_336 : out std_logic; - N_331 : out std_logic; - N_6455 : in std_logic; - N_127 : out std_logic; - N_330 : out std_logic; - N_769 : in std_logic; - un1_apbi_2 : in std_logic; - N_335 : out std_logic; - dsurx_c : in std_logic; - rstn : in std_logic; - hbusreq_i_3 : out std_logic; - lclk_c : in std_logic - ); - -end ahbuart; - -architecture DEF_ARCH of ahbuart is - - component VCC - port( Y : out std_logic - ); - end component; - - component dcom_uart - port( data : out std_logic_vector(7 downto 0); - hwdata : in std_logic_vector(31 downto 24) := (others => 'U'); - paddr : in std_logic_vector(3 downto 2) := (others => 'U'); - pwdata_1 : in std_logic_vector(4 to 4) := (others => 'U'); - prdata_5 : out std_logic; - prdata_0 : out std_logic; - state_i : in std_logic_vector(5 to 5) := (others => 'U'); - psel_1 : in std_logic_vector(7 to 7) := (others => 'U'); - pwdata : in std_logic_vector(17 downto 16) := (others => 'U'); - un1_dcom0_16 : out std_logic; - un1_dcom0_13 : out std_logic; - un1_dcom0_12 : out std_logic; - un1_dcom0_11 : out std_logic; - un1_dcom0_15 : out std_logic; - un1_dcom0_14 : out std_logic; - un1_dcom0_17 : out std_logic; - un1_dcom0_10 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - tcnt : out std_logic_vector(1 downto 0); - dsurx_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - N_335 : out std_logic; - un1_apbi_2 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - N_330 : out std_logic; - N_127 : out std_logic; - N_6455 : in std_logic := 'U'; - N_331 : out std_logic; - N_336 : out std_logic; - N_334 : out std_logic; - N_333 : out std_logic; - N_332 : out std_logic; - N_6455_0 : in std_logic := 'U'; - dsutx_c : out std_logic; - N_85 : out std_logic; - write : in std_logic := 'U'; - thempty : out std_logic; - N_321 : in std_logic := 'U'; - rdata60_1 : in std_logic := 'U'; - N_86 : out std_logic; - rstn : in std_logic := 'U'; - dready : out std_logic; - un1_apbi_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U' - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component dcom - port( tcnt : in std_logic_vector(1 downto 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_25 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hwdata : out std_logic_vector(31 downto 0); - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - data : in std_logic_vector(7 downto 0) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - state_i : out std_logic_vector(5 to 5); - haddr : out std_logic_vector(31 downto 0); - rstn : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - thempty : in std_logic := 'U'; - N_321 : out std_logic; - N_264_0 : in std_logic := 'U'; - active : in std_logic := 'U'; - hwrite : out std_logic; - dready : in std_logic := 'U'; - write : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component ahbmst - port( iosn : in std_logic_vector(93 to 93) := (others => 'U'); - hgrant : in std_logic_vector(1 to 1) := (others => 'U'); - htrans : out std_logic_vector(1 to 1); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - lclk_c : in std_logic := 'U'; - hbusreq_i_3 : in std_logic := 'U'; - active : out std_logic; - rstn : in std_logic := 'U' - ); - end component; - - signal active, \data[0]\, \data[1]\, \data[2]\, \data[3]\, - \data[4]\, \data[5]\, \data[6]\, \data[7]\, \state_i[5]\, - \tcnt[0]\, \tcnt[1]\, write, thempty, N_321, dready, - \hwdata[24]\, \hwdata[25]\, \hwdata[26]\, \hwdata[27]\, - \hwdata[28]\, \hwdata[29]\, \hwdata[30]\, \hwdata[31]\, - \hbusreq_i_3\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : dcom_uart - Use entity work.dcom_uart(DEF_ARCH); - for all : dcom - Use entity work.dcom(DEF_ARCH); - for all : ahbmst - Use entity work.ahbmst(DEF_ARCH); -begin - - hwdata(31) <= \hwdata[31]\; - hwdata(30) <= \hwdata[30]\; - hwdata(29) <= \hwdata[29]\; - hwdata(28) <= \hwdata[28]\; - hwdata(27) <= \hwdata[27]\; - hwdata(26) <= \hwdata[26]\; - hwdata(25) <= \hwdata[25]\; - hwdata(24) <= \hwdata[24]\; - hbusreq_i_3 <= \hbusreq_i_3\; - - VCC_i_0 : VCC - port map(Y => VCC_0); - - dcom_uart0 : dcom_uart - port map(data(7) => \data[7]\, data(6) => \data[6]\, - data(5) => \data[5]\, data(4) => \data[4]\, data(3) => - \data[3]\, data(2) => \data[2]\, data(1) => \data[1]\, - data(0) => \data[0]\, hwdata(31) => \hwdata[31]\, - hwdata(30) => \hwdata[30]\, hwdata(29) => \hwdata[29]\, - hwdata(28) => \hwdata[28]\, hwdata(27) => \hwdata[27]\, - hwdata(26) => \hwdata[26]\, hwdata(25) => \hwdata[25]\, - hwdata(24) => \hwdata[24]\, paddr(3) => paddr(3), - paddr(2) => paddr(2), pwdata_1(4) => pwdata_1(4), - prdata_5 => prdata_5, prdata_0 => prdata_0, state_i(5) - => \state_i[5]\, psel_1(7) => psel_1(7), pwdata(17) => - pwdata(17), pwdata(16) => pwdata(16), un1_dcom0_16 => - un1_dcom0(18), un1_dcom0_13 => un1_dcom0(15), - un1_dcom0_12 => un1_dcom0(14), un1_dcom0_11 => - un1_dcom0(13), un1_dcom0_15 => un1_dcom0(17), - un1_dcom0_14 => un1_dcom0(16), un1_dcom0_17 => - un1_dcom0(19), un1_dcom0_10 => un1_dcom0(12), - pwdata_0(15) => pwdata_0(15), pwdata_0(14) => - pwdata_0(14), pwdata_0(13) => pwdata_0(13), pwdata_0(12) - => pwdata_0(12), pwdata_0(11) => pwdata_0(11), - pwdata_0(10) => pwdata_0(10), pwdata_0(9) => pwdata_0(9), - pwdata_0(8) => pwdata_0(8), pwdata_0(7) => pwdata_0(7), - pwdata_0(6) => pwdata_0(6), pwdata_0(5) => pwdata_0(5), - pwdata_0(4) => pwdata_0(4), pwdata_0(3) => pwdata_0(3), - pwdata_0(2) => pwdata_0(2), pwdata_0(1) => pwdata_0(1), - pwdata_0(0) => pwdata_0(0), tcnt(1) => \tcnt[1]\, tcnt(0) - => \tcnt[0]\, dsurx_c => dsurx_c, lclk_c => lclk_c, - N_335 => N_335, un1_apbi_2 => un1_apbi_2, N_769 => N_769, - N_330 => N_330, N_127 => N_127, N_6455 => N_6455, N_331 - => N_331, N_336 => N_336, N_334 => N_334, N_333 => N_333, - N_332 => N_332, N_6455_0 => N_6455_0, dsutx_c => dsutx_c, - N_85 => N_85, write => write, thempty => thempty, N_321 - => N_321, rdata60_1 => rdata60_1, N_86 => N_86, rstn => - rstn, dready => dready, un1_apbi_0 => un1_apbi_0, N_78_0 - => N_78); - - GND_i_0 : GND - port map(Y => GND_0); - - dcom0 : dcom - port map(tcnt(1) => \tcnt[1]\, tcnt(0) => \tcnt[0]\, - iosn_2(93) => iosn_2(93), hrdata_0_d0 => hrdata_0_d0, - hrdata_1 => hrdata_1, hrdata_24 => hrdata_24, hrdata_26 - => hrdata_26, hrdata_25 => hrdata_25, hrdata_23 => - hrdata_23, hwdata(31) => \hwdata[31]\, hwdata(30) => - \hwdata[30]\, hwdata(29) => \hwdata[29]\, hwdata(28) => - \hwdata[28]\, hwdata(27) => \hwdata[27]\, hwdata(26) => - \hwdata[26]\, hwdata(25) => \hwdata[25]\, hwdata(24) => - \hwdata[24]\, hwdata(23) => hwdata(23), hwdata(22) => - hwdata(22), hwdata(21) => hwdata(21), hwdata(20) => - hwdata(20), hwdata(19) => hwdata(19), hwdata(18) => - hwdata(18), hwdata(17) => hwdata(17), hwdata(16) => - hwdata(16), hwdata(15) => hwdata(15), hwdata(14) => - hwdata(14), hwdata(13) => hwdata(13), hwdata(12) => - hwdata(12), hwdata(11) => hwdata(11), hwdata(10) => - hwdata(10), hwdata(9) => hwdata(9), hwdata(8) => - hwdata(8), hwdata(7) => hwdata(7), hwdata(6) => hwdata(6), - hwdata(5) => hwdata(5), hwdata(4) => hwdata(4), hwdata(3) - => hwdata(3), hwdata(2) => hwdata(2), hwdata(1) => - hwdata(1), hwdata(0) => hwdata(0), hrdata_0_1 => - hrdata_0_1, hrdata_0_2 => hrdata_0_2, hrdata_0_9 => - hrdata_0_9, hrdata_0_13 => hrdata_0_13, hrdata_0_14 => - hrdata_0_14, hrdata_0_15 => hrdata_0_15, hrdata_0_21 => - hrdata_0_21, hrdata_0_4 => hrdata_0_4, hrdata_0_12 => - hrdata_0_12, hrdata_0_11 => hrdata_0_11, hrdata_0_3 => - hrdata_0_3, hrdata_0_23 => hrdata_0_23, hrdata_0_17 => - hrdata_0_17, hrdata_0_7 => hrdata_0_7, hrdata_0_22 => - hrdata_0_22, hrdata_0_10 => hrdata_0_10, hrdata_0_18 => - hrdata_0_18, hrdata_0_16 => hrdata_0_16, hrdata_0_8 => - hrdata_0_8, hrdata_0_27 => hrdata_0_27, hrdata_0_26 => - hrdata_0_26, hrdata_0_24 => hrdata_0_24, hrdata_0_0 => - hrdata_0_0, data(7) => \data[7]\, data(6) => \data[6]\, - data(5) => \data[5]\, data(4) => \data[4]\, data(3) => - \data[3]\, data(2) => \data[2]\, data(1) => \data[1]\, - data(0) => \data[0]\, iosn_0(93) => iosn_0(93), - state_i(5) => \state_i[5]\, haddr(31) => haddr(31), - haddr(30) => haddr(30), haddr(29) => haddr(29), haddr(28) - => haddr(28), haddr(27) => haddr(27), haddr(26) => - haddr(26), haddr(25) => haddr(25), haddr(24) => haddr(24), - haddr(23) => haddr(23), haddr(22) => haddr(22), haddr(21) - => haddr(21), haddr(20) => haddr(20), haddr(19) => - haddr(19), haddr(18) => haddr(18), haddr(17) => haddr(17), - haddr(16) => haddr(16), haddr(15) => haddr(15), haddr(14) - => haddr(14), haddr(13) => haddr(13), haddr(12) => - haddr(12), haddr(11) => haddr(11), haddr(10) => haddr(10), - haddr(9) => haddr(9), haddr(8) => haddr(8), haddr(7) => - haddr(7), haddr(6) => haddr(6), haddr(5) => haddr(5), - haddr(4) => haddr(4), haddr(3) => haddr(3), haddr(2) => - haddr(2), haddr(1) => haddr(1), haddr(0) => haddr(0), - rstn => rstn, hbusreq_i_3 => \hbusreq_i_3\, N_78_0 => - N_78_0, N_262_0 => N_262_0, thempty => thempty, N_321 => - N_321, N_264_0 => N_264_0, active => active, hwrite => - hwrite, dready => dready, write => write, lclk_c => - lclk_c); - - ahbmst0 : ahbmst - port map(iosn(93) => iosn(93), hgrant(1) => hgrant(1), - htrans(1) => htrans(1), iosn_2(93) => iosn_2(93), lclk_c - => lclk_c, hbusreq_i_3 => \hbusreq_i_3\, active => - active, rstn => rstn); - - VCC_i : VCC - port map(Y => \VCC\); - - GND_i : GND - port map(Y => \GND\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity ahbctrl is - - port( hmbsel : out std_logic_vector(0 to 0); - htrans_3 : in std_logic_vector(1 to 1); - htrans_2 : in std_logic_vector(1 to 1); - htrans_1 : in std_logic_vector(1 to 1); - htrans_0_0 : in std_logic; - bco_msb_1 : out std_logic_vector(1 to 1); - hresp_0 : out std_logic_vector(0 to 0); - nhmaster_1_i : out std_logic_vector(0 to 0); - hgrant_3 : out std_logic; - hgrant_1 : out std_logic; - hgrant_0 : out std_logic; - hsize_5 : in std_logic_vector(1 to 1); - hmbsel_1 : out std_logic_vector(0 to 0); - hburst_0 : in std_logic_vector(2 downto 0); - hsize_0 : in std_logic_vector(1 downto 0); - hsize : out std_logic_vector(1 downto 0); - haddr_3_4 : in std_logic; - haddr_3_5 : in std_logic; - haddr_3_0 : in std_logic; - haddr_3_3 : in std_logic; - haddr_3_8 : in std_logic; - haddr_3_6 : in std_logic; - haddr_3_1 : in std_logic; - haddr_3_7 : in std_logic; - hwdata_m_0_3 : out std_logic; - hwdata_m_0_0 : out std_logic; - hwdata_m_0_2 : out std_logic; - hwdata_m_8 : out std_logic; - hwdata_m_13 : out std_logic; - hwdata_m_5 : out std_logic; - hwdata_m_0_d0 : out std_logic; - hwdata_m_7 : out std_logic; - hwdata_2_15 : out std_logic; - hwdata_2_0 : in std_logic; - hwdata_2_9 : in std_logic; - hwdata_2_3 : in std_logic; - hwdata_2_14 : out std_logic; - hwdata_2_1 : in std_logic; - hwdata_2_28 : in std_logic; - hwdata_2_27 : in std_logic; - hwdata_2_25 : in std_logic; - hwdata_2_23 : in std_logic; - hwdata_2_13 : in std_logic; - hwdata_2_12 : in std_logic; - hwdata_2_11 : in std_logic; - hwdata_2_4 : in std_logic; - hwdata_2_16 : in std_logic; - hwdata_1 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - hwdata_0 : in std_logic_vector(31 downto 0); - hwdata : inout std_logic_vector(31 downto 0) := (others => 'Z'); - haddr_2 : inout std_logic_vector(30 downto 2) := (others => 'Z'); - haddr_1 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - haddr_0 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - hrdata_4_15 : in std_logic; - hrdata_4_13 : in std_logic; - hrdata_4_11 : in std_logic; - hrdata_4_27 : in std_logic; - hrdata_4_26 : in std_logic; - hrdata_4_4 : in std_logic; - hrdata_4_21 : in std_logic; - hrdata_4_1 : in std_logic; - hrdata_4_22 : in std_logic; - hrdata_4_23 : in std_logic; - hrdata_4_0 : in std_logic; - hrdata_4_14 : in std_logic; - hrdata_4_3 : in std_logic; - hrdata_4_2 : in std_logic; - hrdata_4_9 : in std_logic; - hrdata_4_12 : in std_logic; - hrdata_4_10 : in std_logic; - hrdata_4_7 : in std_logic; - hrdata_4_8 : in std_logic; - hrdata_4_16 : in std_logic; - hrdata_4_18 : in std_logic; - hrdata_4_17 : in std_logic; - hrdata_3_15 : in std_logic; - hrdata_3_13 : in std_logic; - hrdata_3_11 : in std_logic; - hrdata_3_28 : in std_logic; - hrdata_3_27 : in std_logic; - hrdata_3_26 : in std_logic; - hrdata_3_4 : in std_logic; - hrdata_3_1 : in std_logic; - hrdata_3_22 : in std_logic; - hrdata_3_23 : in std_logic; - hrdata_3_0 : in std_logic; - hrdata_3_24 : in std_logic; - hrdata_3_21 : in std_logic; - hrdata_3_14 : in std_logic; - hrdata_3_3 : in std_logic; - hrdata_3_2 : in std_logic; - hrdata_3_9 : in std_logic; - hrdata_3_12 : in std_logic; - hrdata_3_10 : in std_logic; - hrdata_3_7 : in std_logic; - hrdata_3_6 : in std_logic; - hrdata_3_8 : in std_logic; - hrdata_3_29 : in std_logic; - hrdata_3_16 : in std_logic; - hrdata_3_5 : in std_logic; - hrdata_3_30 : in std_logic; - hrdata_3_18 : in std_logic; - hrdata_3_17 : in std_logic; - hrdata_2_28 : in std_logic; - hrdata_2_25 : in std_logic; - hrdata_2_15 : out std_logic; - hrdata_2_11 : out std_logic; - hrdata_2_27 : out std_logic; - hrdata_2_26 : out std_logic; - hrdata_2_23 : in std_logic; - hrdata_2_22 : in std_logic; - hrdata_2_21 : in std_logic; - hrdata_2_13 : in std_logic; - hrdata_2_4 : in std_logic; - hrdata_2_1 : in std_logic; - hrdata_2_0 : in std_logic; - hrdata_2_24 : in std_logic; - hrdata_2_14 : in std_logic; - hrdata_2_3 : in std_logic; - hrdata_2_2 : in std_logic; - hrdata_2_31 : in std_logic; - hrdata_2_9 : out std_logic; - hrdata_2_19 : in std_logic; - hrdata_2_10 : out std_logic; - hrdata_2_7 : out std_logic; - hrdata_2_6 : in std_logic; - hrdata_2_29 : in std_logic; - hrdata_2_5 : in std_logic; - hrdata_2_30 : in std_logic; - hrdata_2_18 : in std_logic; - hrdata_2_16 : in std_logic; - hrdata_2_12 : in std_logic; - hrdata_2_8 : in std_logic; - hrdata_2_17 : in std_logic; - bco_msb_1_m : out std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : out std_logic_vector(1 to 1); - l1_0_m : out std_logic_vector(1 to 1); - nhmaster_1_iv_0 : out std_logic_vector(1 to 1); - hresp : in std_logic_vector(0 to 0); - htrans : out std_logic_vector(1 downto 0); - hrdata_1 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - data_0_5 : in std_logic; - data_0_21 : in std_logic; - data_0_16 : in std_logic; - data_0_2 : in std_logic; - data_0_0 : in std_logic; - data_8 : in std_logic; - data_24 : in std_logic; - data_0_d0 : in std_logic; - data_19 : in std_logic; - data_5 : in std_logic; - data_3 : in std_logic; - hrdata : inout std_logic_vector(31 downto 0) := (others => 'Z'); - size : in std_logic_vector(0 to 0); - nbo_5_0 : in std_logic_vector(1 downto 0); - address : in std_logic_vector(1 downto 0); - htrans_tz : in std_logic_vector(1 to 1); - haddr_1_d0 : out std_logic; - haddr_11 : out std_logic; - haddr_31 : in std_logic; - haddr_0_d0 : in std_logic; - haddr_4 : in std_logic; - haddr_15 : out std_logic; - haddr_14 : out std_logic; - haddr_19 : out std_logic; - haddr_18 : out std_logic; - haddr_21 : out std_logic; - haddr_20 : out std_logic; - haddr_23 : out std_logic; - haddr_22 : out std_logic; - haddr_27 : out std_logic; - haddr_26 : out std_logic; - haddr_29 : out std_logic; - haddr_28 : out std_logic; - haddr_12 : out std_logic; - haddr_13 : out std_logic; - haddr_16 : out std_logic; - haddr_17 : out std_logic; - haddr_24 : out std_logic; - haddr_25 : out std_logic; - haddr_30 : out std_logic; - hburst : out std_logic_vector(2 downto 0); - hsel_i : out std_logic_vector(0 to 0); - hrdata_1_0_1_0 : out std_logic; - hrdata_0 : inout std_logic_vector(31 downto 0) := (others => 'Z'); - iosn_0 : out std_logic_vector(93 to 93); - iosn_1_8 : out std_logic; - iosn_1_0 : out std_logic; - iosn_2 : out std_logic_vector(93 to 93); - iosn_8 : out std_logic; - iosn_7 : out std_logic; - iosn_0_d0 : out std_logic; - hmaster_0_1 : out std_logic; - N_5054 : in std_logic; - htrans_0_sqmuxa_2 : in std_logic; - lb_0_sqmuxa_1 : in std_logic; - N_466 : in std_logic; - N_95_i_0 : in std_logic; - bo_5842_d : in std_logic; - rstn : in std_logic; - hbusreq_i_3_0 : in std_logic; - N_90_i_0 : in std_logic; - N_262 : out std_logic; - hwrite_1_m_0 : in std_logic; - werr_2_m_0 : in std_logic; - hwrite_1 : in std_logic; - hwrite_0 : in std_logic; - N_458 : in std_logic; - N_459 : in std_logic; - N_468 : in std_logic; - N_463 : in std_logic; - N_461 : in std_logic; - N_510 : in std_logic; - N_138 : in std_logic; - N_139 : in std_logic; - N_6377 : in std_logic; - N_103_i_0 : in std_logic; - brmw_i : in std_logic; - N_6550 : in std_logic; - N_264 : out std_logic; - N_467 : in std_logic; - N_457 : in std_logic; - N_462 : in std_logic; - un1_nhmaster_0_sqmuxa_1 : out std_logic; - un1_htrans_1_sqmuxa_0 : in std_logic; - un60_nbo : in std_logic; - arb_1 : out std_logic; - hbusreq : in std_logic; - hlock : in std_logic; - hready_1 : in std_logic; - hready_0 : in std_logic; - N_78 : out std_logic; - un315_ioen_NE : out std_logic; - un51_ioen_NE : out std_logic; - un59_nbo : in std_logic; - un91_nbo_i_0 : in std_logic; - hready : in std_logic; - bo_5842_d_0 : in std_logic; - un6_ioen_NE_0 : out std_logic; - brmw_1 : in std_logic; - hwrite : out std_logic; - hwrite_m_0_0 : out std_logic; - hbusreq_i_3 : in std_logic; - IdlePhase : in std_logic; - un1_dmain_6 : in std_logic; - Lock_RNIU86D : in std_logic; - N_546 : out std_logic; - N_264_0 : out std_logic; - N_262_0 : out std_logic; - N_78_0 : out std_logic; - lclk_c : in std_logic - ); - -end ahbctrl; - -architecture DEF_ARCH of ahbctrl is - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal cfgsel_0, cfgsel_RNIQIMCBC, N_417_0, N_393, - \hmaster_0[0]\, N_5626_i, \hmaster_2[1]\, N_5627_i, - \hmaster_1[1]\, \hslave_1[0]\, \hslave_RNI6LMVPE[0]\, - \hslave_0[0]\, \hslave_0[2]\, \hslave_RNIQRGJS9[2]\, - \hmasterd_0[0]\, \hmasterd_1[1]\, \hmaster_0[1]\, - \iosn[93]\, \hmasterd_0[1]\, hready_1_iv_0_o2_0, N_660, - \hrdata_i_0_0[25]\, N_628, N_474, N_473, N_5325, N_6336, - N_663, \un34_hready[5]\, N_4876, \un34_hready[6]\, N_6339, - \hrdata_0_1[4]\, N_487, N_581, N_6343, \hrdata_0_0_1[8]\, - N_488, N_489, N_490, N_491, \hrdata_1_0[12]\, N_492, - \hrdata_1_0[13]\, \un34_hready[17]\, N_477, N_493, N_599, - N_6351, \hrdata_1_1[16]\, \un34_hready[20]\, N_4891, - N_6356, \hrdata_0_0[21]\, N_536, N_535, N_534, N_5348, - \un34_hready[27]\, N_478, N_465, N_525, N_475, N_572, - N_6353, \hrdata_0_0[18]\, hmasterlock_2_0, \iosn_0[93]\, - hmastlock, hlock_m, hlock_m_1, defslv_0_sqmuxa_1, - defslv_0_sqmuxa_0, un2_ioarea, \bco_msb_1_i_m_0[0]\, - arb_0_sqmuxa_1_a1_0, \vect[3]\, arb_1_sqmuxa_1_0, - un2_ioarea_17, un2_ioarea_11, un2_ioarea_10, - un2_ioarea_14, un2_ioarea_16, un2_ioarea_5, un2_ioarea_4, - un2_ioarea_13, \hsel_i[0]\, un2_ioarea_8, un2_ioarea_7, - un2_ioarea_3, un2_ioarea_1, un315_ioen_NE_1, - un315_ioen_NE_0, un51_ioen_NE_6, \haddr[29]\, \haddr[28]\, - un51_ioen_NE_1, un51_ioen_NE_0, un51_ioen_NE_10_5, - un51_ioen_NE_10_3, \haddr[25]\, \haddr[24]\, - un51_ioen_NE_10_4, un51_ioen_NE_10_1, \haddr[21]\, - \haddr[20]\, \haddr[26]\, \haddr[27]\, \haddr[22]\, - \haddr[23]\, \haddr[30]\, arb_0_sqmuxa_1_0, - arb_0_sqmuxa_1_a1_1, arb_0_sqmuxa_0, arb_0_sqmuxa_1_a2_0, - N_4617, \un34_haddr_1[5]\, \un34_haddr_1[4]\, - \un34_haddr_0[37]\, \hrdatas[13]\, N_657, N_594, - \hrdatas[12]\, \hrdata_1_1[5]\, N_587, N_585, N_588, - \hrdata_1_0_1[6]\, N_625, N_620, N_626, N_602, N_600, - N_603, N_664, N_576, N_583, N_584, \hrdata_1_0[28]\, - \hrdatas[28]\, N_580, N_460, N_622, N_623, - \hrdata_1_1[29]\, N_606, N_604, N_607, - \hrdatas_0_0_0[12]\, N_25, N_6470, hrdatas6, \hburst[1]\, - \hburst[2]\, hready_1_iv_0_a2_0_0, N_651_2, - hready_RNICLR2, \un1_acdm_3_0_a2_0[55]\, - \un1_acdm_3_0_a2_0[57]\, \un1_acdm_3_0_a3_0_0[71]_net_1\, - \hrdatam_1_0_a5_0[24]\, \haddr[7]\, - \hrdatam_1_0_a5_0[27]\, \haddr[6]\, hrdatas6_0_a5_1, - \haddr[9]\, \haddr[8]\, \haddr[10]\, N_6341, N_6364, - N_6340, N_4611, N_6465, \hrdatas_RNO[12]\, N_48, - \haddr_RNI726O[5]\, N_6469, N_6474, \hrdatam_1[28]\, - N_6467, N_94, N_6406, \hrdatas_RNO[15]\, N_43, N_50, - \hrdatas_RNO[14]\, N_6471, N_49, un271_ioen_NE, - arb_1_sqmuxa_1_i, N_4578_i, N_6404, N_569, N_417, N_476, - N_648, N_643, N_647, N_654, \hrdatam[13]\, cfga11, - \hrdatam[28]\, N_568, \htrans_0[1]\, defslv, N_403, - hready_2, hlock_m_0, \hmaster_3[1]\, \hmaster_3[0]\, - defslv_0_sqmuxa, un5_bnslave, \hmbsel_2[0]\, - \bco_msb_1_i_m[0]\, N_4579_i, \hrdata_1_0_1[1]\, N_547, - N_545, N_548, arb_0_sqmuxa_1, \hmaster_0_0_RNIFG08O[1]\, - \nhmaster_1[1]\, \nhmaster_1_iv_0[1]\, \l1_0_m[1]\, - \arb_1\, \hmaster_0_0_RNIFCVH1_0[1]\, N_5342, - \un34_hready[33]\, N_5355, cfgsel, N_4904, N_5274, N_5287, - N_6342, N_6345, N_6347, N_6352, N_6354, N_6365, - \hrdatas[30]\, \hrdatas[17]\, N_4622, N_4582, N_6286, - N_6494, N_6294, \haddr[18]\, N_4596, N_4604, N_4601, - N_4723, N_6523, N_6553, N_6506, N_6583, N_523, N_650, - \hrdatas[5]\, \hrdatas[16]\, \hrdatas[29]\, \hrdatas[8]\, - N_6551, N_469, N_479, N_481, N_483, N_4607, N_4709, - N_4599, N_4602, N_4603, N_4718, N_6586, N_4732, N_6600, - N_4734, N_6602, N_6344, N_6360, N_6366, N_4588, N_6481, - \haddr[3]\, \haddr[2]\, N_6476, N_44, N_24, \haddr_3[4]\, - \haddr_RNI726O[6]\, N_6461, N_6464, \hrdatam_1[13]\, - \hrdatam_1[14]\, \hrdatas_RNO[30]\, N_6477, - \hrdatas_RNO[28]\, N_6472, N_6466, N_6468, \haddr[5]\, - N_77, \hrdatas_RNO[1]\, \hrdatas_RNO[5]\, - \hrdatas_RNO[6]\, \hrdatas_RNO[13]\, \hrdatas_RNO[16]\, - \hrdatas_RNO[17]\, \hrdatas_RNO[29]\, \hrdatam_1[24]\, - \hrdatas_RNO[31]\, \hrdatas_RNO[24]\, N_4627, N_4587, - N_4621, N_4581, N_6500, N_6492, N_6495, N_6496, - \haddr[12]\, N_4590, N_6483, N_4600, N_6493, N_4626, - N_4586, N_4623, N_6485, N_6486, N_6490, N_6288, N_4583, - N_4598, \haddr[14]\, N_4592, \haddr[15]\, N_4593, - \haddr[19]\, N_4597, N_6577, N_4720, N_6520, N_6552, - N_6524, N_206, N_208, N_6531, N_6529, N_4711, N_6511, - N_4719, N_6519, N_4730, N_6530, N_4735, N_6535, N_6528, - N_6514, N_6305, N_6581, N_6593, N_6594, N_6595, N_4708, - \hmasterd[0]\, N_520, N_521, N_609, \hrdatas[31]\, - \hslave[1]\, N_637, N_639, N_640, N_645, \hmasterd[1]\, - N_494, N_480, N_486, N_6521, N_4721, N_6503, N_4610, - \hwrite\, N_470, N_6355, N_4580, N_4620, \hmaster[0]\, - N_6499, N_4606, N_6484, N_4591, \haddr[13]\, N_4612, - N_4652, N_4574, \haddr[5923]\, \iosn_1[101]\, - \un6_ioen_NE_0\, \un51_ioen_NE\, \hslave_3[2]\, - \hslave_RNO[1]\, \hslave_3[1]\, \un315_ioen_NE\, - \un34_haddr[0]\, N_4573, N_4618, N_6601, N_667, N_423, - N_5557, \iosn_1[93]\, \nhmaster_1_i[0]\, N_4608, N_6501, - N_4609, N_6502, N_5327, N_5328, N_5339, N_5349, N_5259, - N_5260, N_5271, N_5281, N_6335, N_6337, N_6338, N_6346, - N_6348, N_6349, N_6350, \hslave[0]\, N_6357, N_6358, - N_6359, N_6361, N_6362, N_6363, \hslave[2]\, \hrdatas[3]\, - N_4589, N_6482, N_4605, N_6498, N_4625, \hmaster[1]\, - N_4585, N_4624, N_6487, N_6488, N_4584, \haddr[16]\, - N_4594, \haddr[17]\, N_4595, N_6504, N_4710, N_6510, - N_5257, N_5280, N_6512, N_4716, N_6516, N_6573, N_6304, - N_6585, N_4707, \hrdatas[26]\, \hrdatas[1]\, N_556, N_454, - \hrdatas[9]\, \hrdatas[15]\, N_641, N_464, N_471, N_472, - \hrdatam[14]\, \hrdatas[14]\, \hrdatam[24]\, - \hrdatas[24]\, N_482, N_484, N_485, N_6522, N_4722, - hmasterlock_RNO, \htrans_RNO[1]\, N_5556, \htrans[1]\, - defslv_RNO, defslv_RNO_0, \un1_nhmaster_0_sqmuxa_1\, - \bco_msb_1_m[1]\, \bco_msb_1[1]\, \htrans[0]\, N_4576, - N_4616, \hburst[0]\, N_4613, N_4653, N_4577, - \hmbsel_1[0]\, \hslave_3[0]\, \iosn_2[93]\, N_4651, - N_4619, \haddr[11]\, \GND\, \VCC\, GND_0, VCC_0 - : std_logic; - -begin - - bco_msb_1(1) <= \bco_msb_1[1]\; - nhmaster_1_i(0) <= \nhmaster_1_i[0]\; - hmbsel_1(0) <= \hmbsel_1[0]\; - bco_msb_1_m(1) <= \bco_msb_1_m[1]\; - hmaster_0_0_RNIFCVH1_0(1) <= \hmaster_0_0_RNIFCVH1_0[1]\; - l1_0_m(1) <= \l1_0_m[1]\; - nhmaster_1_iv_0(1) <= \nhmaster_1_iv_0[1]\; - htrans(1) <= \htrans[1]\; - htrans(0) <= \htrans[0]\; - haddr_11 <= \haddr[11]\; - haddr_15 <= \haddr[15]\; - haddr_14 <= \haddr[14]\; - haddr_19 <= \haddr[19]\; - haddr_18 <= \haddr[18]\; - haddr_21 <= \haddr[21]\; - haddr_20 <= \haddr[20]\; - haddr_23 <= \haddr[23]\; - haddr_22 <= \haddr[22]\; - haddr_27 <= \haddr[27]\; - haddr_26 <= \haddr[26]\; - haddr_29 <= \haddr[29]\; - haddr_28 <= \haddr[28]\; - haddr_12 <= \haddr[12]\; - haddr_13 <= \haddr[13]\; - haddr_16 <= \haddr[16]\; - haddr_17 <= \haddr[17]\; - haddr_24 <= \haddr[24]\; - haddr_25 <= \haddr[25]\; - haddr_30 <= \haddr[30]\; - hburst(2) <= \hburst[2]\; - hburst(1) <= \hburst[1]\; - hburst(0) <= \hburst[0]\; - hsel_i(0) <= \hsel_i[0]\; - hrdata_1_0_1_0 <= \hrdata_1_0_1[1]\; - iosn_0(93) <= \iosn_0[93]\; - iosn_1_8 <= \iosn_1[101]\; - iosn_1_0 <= \iosn_1[93]\; - iosn_2(93) <= \iosn_2[93]\; - iosn_0_d0 <= \iosn[93]\; - hmaster_0_1 <= \hmaster_0[1]\; - un1_nhmaster_0_sqmuxa_1 <= \un1_nhmaster_0_sqmuxa_1\; - arb_1 <= \arb_1\; - un315_ioen_NE <= \un315_ioen_NE\; - un51_ioen_NE <= \un51_ioen_NE\; - un6_ioen_NE_0 <= \un6_ioen_NE_0\; - hwrite <= \hwrite\; - - \r.hslave_1_RNIODTNH[0]\ : MX2C - port map(A => hrdata(25), B => hrdata_0(25), S => - \hslave_1[0]\, Y => N_6360); - - \r.cfga11\ : DFN1E1 - port map(D => \haddr[11]\, CLK => lclk_c, E => \iosn_2[93]\, - Q => cfga11); - - \r.hslave_0_0_RNI16LM6[2]\ : AO1C - port map(A => N_417_0, B => N_491, C => \hrdata_1_0[12]\, Y - => hrdata(12)); - - \r.hslave_RNIDBK5[0]\ : MX2C - port map(A => hrdata_3_15, B => hrdata_4_15, S => - \hslave[0]\, Y => N_485); - - \r.hmaster_0_0_RNI35KKE2_0[0]\ : NOR3A - port map(A => un51_ioen_NE_10_3, B => \haddr[25]\, C => - \haddr[24]\, Y => un51_ioen_NE_10_5); - - \r.hmasterd_0_RNIM4M41[0]\ : OR2B - port map(A => hwdata(7), B => N_6377, Y => hwdata_m_0_d0); - - \r.hslave_1_RNI9PVG[0]\ : NOR2B - port map(A => hrdata_4_1, B => N_664, Y => N_548); - - \r.hmaster_2_RNIURLLM[1]\ : AO1 - port map(A => werr_2_m_0, B => hwrite_1_m_0, C => - \hmaster_2[1]\, Y => N_4610); - - \r.hmaster_0_0_RNITCAKK[1]\ : OR2A - port map(A => haddr_2(4), B => \hmaster_0[1]\, Y => N_4582); - - \r.hmaster_2_RNIPK71O[1]\ : AOI1 - port map(A => hsize_5(1), B => un91_nbo_i_0, C => - \hmaster_2[1]\, Y => N_4612); - - \r.hmasterlock_RNO_0\ : NOR3C - port map(A => \hmaster_3[1]\, B => hlock_m_1, C => - \hmaster_3[0]\, Y => hlock_m_0); - - \r.hslave_RNINRK5[0]\ : MX2C - port map(A => hrdata_2_28, B => hrdata_3_28, S => - \hslave[0]\, Y => N_472); - - \r.hmasterd_RNIOTSF1[0]\ : MX2 - port map(A => N_4721, B => N_6521, S => \hmasterd[0]\, Y - => hwdata_2_14); - - \r.hmaster_RNICBB7[1]\ : MX2 - port map(A => haddr_0(6), B => haddr_1(6), S => - \hmaster[1]\, Y => N_4624); - - \r.hmasterd_0_RNI9F2T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6514, C => N_6406, Y - => hwdata(10)); - - \r.haddr_RNI9EDF[2]\ : OR2A - port map(A => N_6466, B => \haddr[2]\, Y => N_6467); - - \r.hmasterd_0_RNII4GI[1]\ : OR3A - port map(A => N_462, B => \hmasterd_0[0]\, C => - \hmasterd_0[1]\, Y => N_523); - - \r.hslave_0_0_RNIE86V7[2]\ : OR2B - port map(A => N_5355, B => N_393, Y => \un34_hready[33]\); - - \r.hmaster_0_0_RNIFG08O[1]\ : OR3B - port map(A => un60_nbo, B => un1_htrans_1_sqmuxa_0, C => - arb_0_sqmuxa_1_a1_1, Y => \hmaster_0_0_RNIFG08O[1]\); - - \r.hrdatas_RNO[16]\ : AO1C - port map(A => N_6470, B => N_25, C => N_6477, Y => - \hrdatas_RNO[16]\); - - \r.hmaster_RNITFB6[1]\ : OR2B - port map(A => \hmaster[1]\, B => hburst_0(0), Y => N_4653); - - \r.cfgsel_0_0_RNI7JIUF\ : NOR3A - port map(A => N_393, B => cfgsel_0, C => N_5325, Y => - hrdata(0)); - - \r.hslave_1_RNIL1PA[0]\ : MX2C - port map(A => hrdata_3_12, B => hrdata_4_12, S => - \hslave_1[0]\, Y => N_483); - - \r.hmaster_2_RNIH90AJ[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(19), Y => N_4597); - - \r.haddr_RNIBTVL[3]\ : OR3C - port map(A => N_6468, B => N_6472, C => N_6466, Y => N_77); - - \r.hmaster_RNII9N7IO[0]\ : OR2A - port map(A => \nhmaster_1[1]\, B => \nhmaster_1_i[0]\, Y - => hgrant_3); - - \r.hmasterd_RNI97GN[0]\ : MX2C - port map(A => N_4708, B => N_6305, S => \hmasterd[0]\, Y - => hwdata_1(4)); - - \r.hmaster_1_RNIAJSB[1]\ : MX2 - port map(A => haddr_1(25), B => haddr_2(25), S => - \hmaster_1[1]\, Y => N_6496); - - \r.hslave_1_RNIHPOA[0]\ : MX2C - port map(A => hrdata_3_10, B => hrdata_4_10, S => - \hslave_1[0]\, Y => N_481); - - \r.hrdatam_RNI2S59[27]\ : OR3B - port map(A => \hrdatam[28]\, B => cfgsel_0, C => cfga11, Y - => N_572); - - \r.hslave_RNI2OB2D[0]\ : MX2C - port map(A => hrdata_0(28), B => hrdata_1(28), S => - \hslave[0]\, Y => N_6363); - - \r.hslave_RNICPAUPE[0]\ : MX2C - port map(A => \hslave[0]\, B => un5_bnslave, S => - \iosn_2[93]\, Y => \hslave_3[0]\); - - \r.hmaster_RNIN8M4R1[0]\ : OR2A - port map(A => \iosn_1[101]\, B => \hsel_i[0]\, Y => iosn_8); - - \r.hslave_RNITTOV6_0[0]\ : OR3C - port map(A => N_536, B => N_535, C => N_534, Y => - hrdata_0(22)); - - \r.hrdatas_RNO[24]\ : AO1D - port map(A => \haddr_3[4]\, B => N_6470, C => - \hrdatam_1[14]\, Y => \hrdatas_RNO[24]\); - - \r.hmaster_0_0_RNISA19[1]\ : MX2 - port map(A => haddr_0(26), B => haddr_1(26), S => - \hmaster_0[1]\, Y => N_6294); - - \r.hmasterd_0_RNILVI7[1]\ : MX2 - port map(A => hwdata_0(2), B => hwdata_1(2), S => - \hmasterd_0[1]\, Y => N_6506); - - \r.hmaster_RNI7U1OJ[1]\ : OR2A - port map(A => N_5054, B => \hmaster[1]\, Y => N_4613); - - \r.hmaster_0_0_RNIS83UE2_1[0]\ : NOR2B - port map(A => un315_ioen_NE_0, B => un51_ioen_NE_6, Y => - un315_ioen_NE_1); - - \r.hslave_RNIR7QVD[0]\ : MX2 - port map(A => hrdata_2_21, B => hrdata_3_21, S => - \hslave[0]\, Y => N_6356); - - \r.hrdatas_RNIUTR6[17]\ : OR2B - port map(A => \hrdatas[17]\, B => cfga11, Y => N_4891); - - \r.hmasterd_1_RNIATM9[1]\ : MX2 - port map(A => hwdata(22), B => hwdata_0(22), S => - \hmasterd_1[1]\, Y => N_6594); - - \r.defslv_RNO_0\ : NOR2A - port map(A => defslv, B => \iosn_1[93]\, Y => defslv_RNO_0); - - \r.hmaster_1_RNIGKEFK[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_3_1, Y => N_4581); - - \r.hmaster_RNIEU9A[1]\ : MX2 - port map(A => haddr_0(16), B => haddr_1(16), S => - \hmaster[1]\, Y => N_6487); - - \r.hmasterd_RNIUK4E[1]\ : MX2 - port map(A => hwdata_1(6), B => hwdata_2_3, S => - \hmasterd[1]\, Y => N_6510); - - \r.hslave_0_0_RNIG0NP7[2]\ : AO1A - port map(A => N_417_0, B => N_488, C => N_581, Y => - hrdata_0(9)); - - \r.hmasterd_1_RNISRTF[1]\ : OR3A - port map(A => N_461, B => \hmasterd[0]\, C => - \hmasterd_1[1]\, Y => N_521); - - \r.hmasterd_0_RNIDUUG[0]\ : MX2 - port map(A => N_4711, B => N_6511, S => \hmasterd_0[0]\, Y - => hwdata(7)); - - \r.hmaster_RNIKUG5PE[1]\ : MX2 - port map(A => \hmaster[1]\, B => \nhmaster_1[1]\, S => - \iosn_1[93]\, Y => \hmaster_3[1]\); - - \r.hmaster_RNII9N7IO_0[0]\ : OR2A - port map(A => \nhmaster_1_i[0]\, B => \nhmaster_1[1]\, Y - => hgrant_0); - - \r.hmaster_0_0_RNI9CME71_0[0]\ : NOR2A - port map(A => \haddr[29]\, B => \haddr[28]\, Y => - un315_ioen_NE_0); - - \r.hmaster_0_0_RNI5T47J[1]\ : OR2A - port map(A => haddr_0(29), B => \hmaster_0[1]\, Y => N_4607); - - \r.haddr[2]\ : DFN1E1 - port map(D => haddr_1(2), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[2]\); - - \r.hmaster_0_0_RNIBIVC71_0[0]\ : NOR2A - port map(A => \haddr[29]\, B => \haddr[30]\, Y => - \iosn_1[101]\); - - \r.hslave_0_0_RNI1PNSA[2]\ : NOR2A - port map(A => N_393, B => N_5328, Y => \un34_hready[6]\); - - \r.hmaster_1_RNI8BSB[1]\ : MX2 - port map(A => haddr_1(24), B => haddr_2(24), S => - \hmaster_1[1]\, Y => N_6495); - - \r.hmasterlock_RNO_2\ : NOR3B - port map(A => Lock_RNIU86D, B => un1_dmain_6, C => - IdlePhase, Y => hlock_m_1); - - \r.hmaster_1_RNIL0U9J[1]\ : OR2A - port map(A => haddr_1(10), B => \hmaster_1[1]\, Y => N_4588); - - \r.hmaster_1_RNIIJTB[1]\ : MX2C - port map(A => haddr_1(29), B => haddr_2(29), S => - \hmaster_1[1]\, Y => N_6500); - - \r.haddr[3]\ : DFN1E1 - port map(D => haddr_2(3), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[3]\); - - \r.hmasterd_0_RNI59M9[1]\ : MX2 - port map(A => hwdata(11), B => hwdata_0(11), S => - \hmasterd_0[1]\, Y => N_6583); - - \r.hslave_RNI31DPH[1]\ : OR2B - port map(A => \hslave[1]\, B => N_6360, Y => N_628); - - \r.hslave_0_0_RNI0VK6[0]\ : OR2A - port map(A => \hslave_0[0]\, B => hready, Y => - hready_1_iv_0_a2_0_0); - - \r.hslave_1_RNIBSG4A[0]\ : MX2 - port map(A => hrdata_3_3, B => hrdata_4_3, S => - \hslave_1[0]\, Y => N_6338); - - \r.hslave_0_0_RNIRT9A[0]\ : OR3A - port map(A => \hslave_0[0]\, B => hready_1, C => N_654, Y - => N_647); - - \r.hmaster_2_RNIR4U9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(20), Y => N_4598); - - \r.hmasterd_RNIJS6O[1]\ : NOR2 - port map(A => hwdata_1(18), B => \hmasterd[1]\, Y => N_4722); - - \r.hmaster_0_0_RNI9CME71_1[0]\ : NOR2 - port map(A => \haddr[29]\, B => \haddr[28]\, Y => - un51_ioen_NE_0); - - \r.hmaster_0_0_RNIKN26[1]\ : MX2C - port map(A => haddr_4, B => haddr_0(4), S => \hmaster_0[1]\, - Y => N_4622); - - \r.hmasterd_RNIMU0F[0]\ : OR2B - port map(A => \hmasterd[0]\, B => N_6581, Y => N_520); - - \r.hmaster_0_0_RNIEO4OJ[0]\ : MX2 - port map(A => N_4597, B => N_6490, S => \hmaster_0[0]\, Y - => \haddr[19]\); - - \r.cfgsel_0_0_RNIQSMT7\ : MX2C - port map(A => \un34_hready[20]\, B => N_4891, S => cfgsel_0, - Y => hrdata_0(17)); - - \r.haddr_RNI726O_1[5]\ : NOR2 - port map(A => N_6471, B => N_25, Y => \hrdatam_1[14]\); - - \r.hmaster_RNII9N7IO_1[0]\ : NOR2 - port map(A => \nhmaster_1_i[0]\, B => \nhmaster_1[1]\, Y - => hgrant_1); - - \r.hmaster_RNINF2RR9[0]\ : NOR2B - port map(A => rstn, B => \hmaster_3[0]\, Y => N_5626_i); - - \r.hmasterd_0_RNIIBLH[1]\ : OR2A - port map(A => hwdata_0(28), B => \hmasterd_0[1]\, Y => - N_4732); - - \r.hmaster_0_0_RNI76CA71_0[0]\ : NOR2 - port map(A => \haddr[22]\, B => \haddr[23]\, Y => - un51_ioen_NE_10_1); - - \r.hmaster_0_0_RNIUVJSK[0]\ : MX2C - port map(A => N_4582, B => N_4622, S => \hmaster_0[0]\, Y - => haddr_1(4)); - - \r.hmasterd_0_RNICSUF1[0]\ : NOR2A - port map(A => hwdata(14), B => N_6550, Y => hwdata_m_7); - - \r.hmaster_0_0_RNIFCVH1[1]\ : OA1C - port map(A => arb_0_sqmuxa_1_a1_0, B => hbusreq_i_3, C => - \vect[3]\, Y => \bco_msb_1_i_m_0[0]\); - - \r.hslave_0_0_RNIR58U7[0]\ : AO1B - port map(A => N_6364, B => N_663, C => \hrdata_1_1[29]\, Y - => hrdata(29)); - - \r.hmaster_0_0_RNI9EIMC7[0]\ : NOR3C - port map(A => un2_ioarea_11, B => un2_ioarea_10, C => - un2_ioarea_14, Y => un2_ioarea_17); - - \r.hmaster_0_0_RNIAA9AC7[0]\ : OR3C - port map(A => un51_ioen_NE_10_4, B => un51_ioen_NE_10_5, C - => un51_ioen_NE_1, Y => \un51_ioen_NE\); - - \r.hrdatas[28]\ : DFN1 - port map(D => \hrdatas_RNO[28]\, CLK => lclk_c, Q => - \hrdatas[28]\); - - \r.haddr_RNIT9C4_2[5]\ : NOR2 - port map(A => \haddr[5]\, B => \haddr_3[4]\, Y => N_6461); - - \r.hmaster_RNIESC8J[1]\ : NOR2 - port map(A => \hmaster[1]\, B => haddr_2(17), Y => N_4595); - - \r.cfgsel_0_0_RNI0VOMI\ : MX2C - port map(A => \un34_hready[17]\, B => N_477, S => cfgsel_0, - Y => hrdata_0(14)); - - \un1_acdm_3_0_o3_0_m2[60]\ : MX2 - port map(A => data_8, B => data_0_5, S => bo_5842_d, Y => - N_454); - - \r.hslave_RNI6LMVPE[0]\ : NOR2A - port map(A => rstn, B => \hslave_3[0]\, Y => - \hslave_RNI6LMVPE[0]\); - - \r.hrdatas_RNO[30]\ : NOR2A - port map(A => \haddr[3]\, B => N_6477, Y => - \hrdatas_RNO[30]\); - - \r.hrdatas_RNO_0[12]\ : OA1C - port map(A => N_25, B => N_6470, C => hrdatas6, Y => - \hrdatas_0_0_0[12]\); - - \r.hslave_1_RNINP8PK[0]\ : MX2C - port map(A => N_103_i_0, B => hrdata(31), S => - \hslave_1[0]\, Y => N_6366); - - \r.hslave_RNI005IS9[2]\ : MX2C - port map(A => \hslave[2]\, B => \hmbsel_2[0]\, S => - \iosn_2[93]\, Y => \hslave_3[2]\); - - \r.hrdatas_RNO[13]\ : AO1C - port map(A => N_6467, B => N_24, C => N_77, Y => - \hrdatas_RNO[13]\); - - \r.hslave_1_RNIP9PA[0]\ : MX2C - port map(A => hrdata_1(14), B => hrdata_2_14, S => - \hslave_1[0]\, Y => N_5271); - - \r.hmaster_RNI71U7O[0]\ : MX2C - port map(A => N_4579_i, B => N_4619, S => \hmaster[0]\, Y - => haddr_1_d0); - - \r.hslave_0_0_RNID26R[0]\ : AOI1 - port map(A => N_648, B => N_647, C => N_403, Y => N_660); - - \r.hmasterd_RNIIRI32[0]\ : OR2A - port map(A => hwdata(12), B => N_6550, Y => hwdata_m_5); - - \r.hslave_1_RNIS6UA[0]\ : OR2B - port map(A => hrdata_4_22, B => N_664, Y => N_536); - - \r.hmasterd_RNIJU8G[1]\ : MX2 - port map(A => hwdata_0(29), B => hwdata_1(29), S => - \hmasterd[1]\, Y => N_6601); - - \r.hmasterd_RNI0NJV[1]\ : OR3A - port map(A => N_454, B => \hmasterd[0]\, C => \hmasterd[1]\, - Y => N_556); - - \r.hmaster_RNIUQ7LK[0]\ : MX2 - port map(A => N_4580, B => N_4620, S => \hmaster[0]\, Y => - haddr_1(2)); - - \r.hrdatam_RNIQUFD[14]\ : MX2C - port map(A => \hrdatam[14]\, B => \hrdatas[14]\, S => - cfga11, Y => N_477); - - \r.hmaster_0_0_RNIBIOHJ[0]\ : MX2 - port map(A => N_4586, B => N_4626, S => \hmaster_0[0]\, Y - => haddr_2(8)); - - \r.hmaster_0_0_RNI74CUN[1]\ : OR3B - port map(A => \un34_haddr_0[37]\, B => un91_nbo_i_0, C => - un59_nbo, Y => N_4611); - - \r.hrdatas_RNISN57[29]\ : OR2B - port map(A => \hrdatas[29]\, B => N_657, Y => N_604); - - \r.hmaster_RNI5TS1K[0]\ : MX2C - port map(A => N_4613, B => N_4653, S => \hmaster[0]\, Y => - \hburst[0]\); - - \r.cfgsel_RNICGMR7\ : MX2C - port map(A => \un34_hready[20]\, B => N_4891, S => cfgsel, - Y => hrdata(17)); - - \r.hmasterd_1_RNIGLN9[1]\ : MX2C - port map(A => hwdata_1(28), B => hwdata_2_25, S => - \hmasterd_1[1]\, Y => N_6600); - - \r.hslave_RNI7A9PF[2]\ : MX2C - port map(A => N_5257, B => N_6335, S => \hslave[2]\, Y => - N_5325); - - \r.hmaster_1_RNI4RRB[1]\ : MX2 - port map(A => haddr_1(22), B => haddr_2(22), S => - \hmaster_1[1]\, Y => N_6493); - - \r.hmaster_0_0_RNIKKIKOE[0]\ : OR2B - port map(A => \un315_ioen_NE\, B => \un51_ioen_NE\, Y => - un5_bnslave); - - \r.hmasterd_RNI1C4H[0]\ : OR2B - port map(A => \hmasterd[0]\, B => N_6594, Y => N_640); - - \r.hmaster_2_RNI59V9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(15), Y => N_4593); - - \r.hmaster_0_0_RNIS5OHJ[0]\ : MX2 - port map(A => N_4583, B => N_4623, S => \hmaster_0[0]\, Y - => haddr_2(5)); - - \r.hmaster[1]\ : DFN1 - port map(D => N_5627_i, CLK => lclk_c, Q => \hmaster[1]\); - - \r.cfgsel_0_0_RNIBQIPG_0\ : NOR3A - port map(A => N_393, B => cfgsel_0, C => N_5348, Y => - hrdata_0(23)); - - \r.hslave_RNI6U06[0]\ : NOR3B - port map(A => \hslave[0]\, B => hrdata_3_1, C => N_650, Y - => N_547); - - \r.hmaster_1_RNIUARB[1]\ : MX2C - port map(A => haddr_2(10), B => haddr_3_8, S => - \hmaster_1[1]\, Y => N_6481); - - \r.hmasterd_0_RNI1FO21[0]\ : MX2 - port map(A => N_6552, B => N_6524, S => \hmasterd_0[0]\, Y - => hwdata(20)); - - \r.hmasterd_RNIRP0F[1]\ : OR2A - port map(A => hwdata_2_0, B => \hmasterd[1]\, Y => N_4707); - - \r.hslave_0_0_RNIH9OU[0]\ : NOR3C - port map(A => N_602, B => N_600, C => N_603, Y => - \hrdata_1_1[16]\); - - \r.hmaster_2_RNI3HU9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_31, Y => N_4609); - - \r.hmasterd_0_RNI467S[0]\ : MX2C - port map(A => N_4735, B => N_6535, S => \hmasterd_0[0]\, Y - => hwdata(31)); - - \un1_acdm_3_0_a3_0_0[71]\ : MX2 - port map(A => data_19, B => data_0_16, S => bo_5842_d_0, Y - => \un1_acdm_3_0_a3_0_0[71]_net_1\); - - \r.hmaster_RNIJSCF71[0]\ : OR2A - port map(A => \haddr[30]\, B => \hsel_i[0]\, Y => iosn_7); - - \r.hslave_RNIQRGJS9[2]\ : NOR2A - port map(A => rstn, B => \hslave_3[2]\, Y => - \hslave_RNIQRGJS9[2]\); - - \r.hslave_1_RNI93839[0]\ : MX2 - port map(A => hrdata_1(4), B => hrdata_2_4, S => - \hslave_1[0]\, Y => N_6339); - - \r.hmasterd_RNI746O[1]\ : NOR2 - port map(A => hwdata_0(12), B => \hmasterd[1]\, Y => N_4716); - - \r.hmaster_RNICG3AO[0]\ : MX2 - port map(A => N_4612, B => N_4652, S => \hmaster[0]\, Y => - hsize(1)); - - \r.hmaster_0_0_RNIBIVC71[0]\ : OR2 - port map(A => \haddr[29]\, B => \haddr[30]\, Y => - \un6_ioen_NE_0\); - - \r.hmaster_RNI28RFJ[0]\ : MX2 - port map(A => N_4585, B => N_4625, S => \hmaster[0]\, Y => - haddr_2(7)); - - \r.hrdatas_RNIB5JV[5]\ : NOR3C - port map(A => N_587, B => N_585, C => N_588, Y => - \hrdata_1_1[5]\); - - \r.hmaster_RNIEQS6PE[1]\ : NOR2B - port map(A => rstn, B => \hmaster_3[1]\, Y => N_5627_i); - - \r.hrdatas_RNO[1]\ : OR2B - port map(A => N_44, B => N_43, Y => \hrdatas_RNO[1]\); - - \r.hmasterd_0_RNI3M7S[0]\ : MX2 - port map(A => N_4718, B => N_6586, S => \hmasterd_0[0]\, Y - => hwdata(14)); - - \r.hmaster_0_0_RNI473TN[1]\ : OR3C - port map(A => nbo_5_0(0), B => \un34_haddr_1[5]\, C => - un91_nbo_i_0, Y => N_4579_i); - - \r.hmaster_RNIJSCF71_0[0]\ : NOR2A - port map(A => \hsel_i[0]\, B => \haddr[30]\, Y => - un51_ioen_NE_6); - - \r.hmasterd_RNIUL6A1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6593, C => N_637, Y => - hwdata_1(21)); - - \r.hmasterd_0[0]\ : DFN1E1 - port map(D => \hmaster_0[0]\, CLK => lclk_c, E => - \iosn[93]\, Q => \hmasterd_0[0]\); - - \r.haddr[10]\ : DFN1E1 - port map(D => haddr_0(10), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[10]\); - - \r.hmaster_0_0_RNI6J2P[0]\ : OA1 - port map(A => \hburst[1]\, B => \hburst[2]\, C => - \hmaster_0[0]\, Y => arb_0_sqmuxa_1_a2_0); - - \r.haddr[8]\ : DFN1E1 - port map(D => haddr_2(8), CLK => lclk_c, E => \iosn[93]\, Q - => \haddr[8]\); - - \r.hmaster_0_0_RNIMI09[1]\ : MX2 - port map(A => haddr_0(23), B => haddr_1(23), S => - \hmaster_0[1]\, Y => N_6494); - - \r.hslave_RNIFHUD8[2]\ : OAI1 - port map(A => N_417, B => N_475, C => N_572, Y => - hrdata_2_27); - - \r.hslave_0_0_RNIAEOPA[2]\ : MX2C - port map(A => N_5260, B => N_6338, S => \hslave_0[2]\, Y - => N_5328); - - \r.hmasterlock_RNITLJU\ : NOR3 - port map(A => \hburst[1]\, B => \hburst[2]\, C => hmastlock, - Y => arb_1_sqmuxa_1_0); - - \r.haddr[9]\ : DFN1E1 - port map(D => haddr_2(9), CLK => lclk_c, E => \iosn[93]\, Q - => \haddr[9]\); - - \r.haddr_RNI8TVL[4]\ : NOR2 - port map(A => \haddr_3[4]\, B => N_6471, Y => - \hrdatam_1[13]\); - - \r.haddr_RNIT9C4_0[5]\ : OR2A - port map(A => \haddr[5]\, B => \haddr_3[4]\, Y => N_25); - - \r.hslave_1_RNI3JVE[0]\ : MX2 - port map(A => hrdata_1(2), B => hrdata_2_2, S => - \hslave_1[0]\, Y => N_5259); - - \r.hmasterd_0_RNIUOGI[1]\ : OR3A - port map(A => N_138, B => \hmasterd_0[0]\, C => - \hmasterd_0[1]\, Y => N_208); - - \r.hmaster_0_0_RNI3DHK19[1]\ : OA1A - port map(A => \hmaster_0[1]\, B => - \un1_nhmaster_0_sqmuxa_1\, C => \l1_0_m[1]\, Y => - \nhmaster_1_iv_0[1]\); - - \r.hrdatam_RNO_0[24]\ : OR2 - port map(A => \haddr[7]\, B => N_25, Y => - \hrdatam_1_0_a5_0[24]\); - - \r.hmasterd_0_RNIGOE8[1]\ : NOR2 - port map(A => \hmasterd_0[1]\, B => N_457, Y => N_6551); - - \r.hslave_RNI1KG3G[0]\ : MX2C - port map(A => hrdata(15), B => hrdata_1(15), S => - \hslave[0]\, Y => N_6350); - - \r.htrans_RNO_0[1]\ : MX2 - port map(A => \htrans_0[1]\, B => \htrans[1]\, S => - \iosn_1[93]\, Y => N_5556); - - \r.hslave_RNI93K5[0]\ : MX2 - port map(A => hrdata_3_13, B => hrdata_4_13, S => - \hslave[0]\, Y => N_484); - - \r.hmaster_RNIBKC8J[1]\ : NOR2 - port map(A => \hmaster[1]\, B => haddr_2(16), Y => N_4594); - - \r.hrdatas[29]\ : DFN1 - port map(D => \hrdatas_RNO[29]\, CLK => lclk_c, Q => - \hrdatas[29]\); - - \r.hrdatas_RNIH7AG[13]\ : AO1B - port map(A => \hrdatas[13]\, B => N_657, C => N_594, Y => - \hrdata_1_0[13]\); - - \r.htrans_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5556, Y => \htrans_RNO[1]\); - - \r.htrans[1]\ : DFN1 - port map(D => \htrans_RNO[1]\, CLK => lclk_c, Q => - \htrans_0[1]\); - - \r.hslave_RNID2VT[2]\ : AO1C - port map(A => N_417, B => N_465, C => N_525, Y => - hrdata_2_26); - - \r.hmaster_0_0_RNIQN2OJ[0]\ : MX2 - port map(A => N_4593, B => N_6486, S => \hmaster_0[0]\, Y - => \haddr[15]\); - - \r.hrdatas_RNO_0[1]\ : OR3B - port map(A => N_24, B => \haddr_3[4]\, C => N_6467, Y => - N_44); - - \r.hrdatam_RNO[24]\ : AO1D - port map(A => \hrdatam_1_0_a5_0[24]\, B => N_6467, C => - \hrdatam_1[13]\, Y => \hrdatam_1[24]\); - - \r.haddr_RNI1AC4_0[6]\ : NOR2B - port map(A => \haddr[7]\, B => \haddr[6]\, Y => N_6469); - - \bco_msb_1_0_a2[1]\ : OR2A - port map(A => hbusreq_i_3, B => hbusreq, Y => - \bco_msb_1[1]\); - - GND_i : GND - port map(Y => \GND\); - - \r.hslave_RNI5RJ5[0]\ : MX2C - port map(A => hrdata_3_11, B => hrdata_4_11, S => - \hslave[0]\, Y => N_482); - - \r.hslave_0_0_RNISAP49[2]\ : MX2C - port map(A => N_479, B => N_6342, S => \hslave_0[2]\, Y => - N_487); - - \r.hmaster_2_RNITRDB[1]\ : NOR2B - port map(A => hburst_0(2), B => \haddr[5923]\, Y => - \hburst[2]\); - - \r.hmaster_RNIUDMNJ[0]\ : MX2C - port map(A => N_4589, B => N_6482, S => \hmaster[0]\, Y => - \haddr[11]\); - - \r.haddr_RNIG41B[8]\ : OR3 - port map(A => \haddr[9]\, B => \haddr[8]\, C => \haddr[10]\, - Y => N_6465); - - \r.hrdatam_RNO[27]\ : NOR3 - port map(A => N_25, B => \hrdatam_1_0_a5_0[27]\, C => - N_6467, Y => \hrdatam_1[28]\); - - \r.haddr_RNID97D[3]\ : NOR2 - port map(A => \haddr[3]\, B => N_6465, Y => N_6466); - - \r.hrdatas_RNO[5]\ : OR2 - port map(A => \haddr_RNI726O[5]\, B => \haddr_RNI726O[6]\, - Y => \hrdatas_RNO[5]\); - - \r.haddr_RNI1AC4[6]\ : XNOR2 - port map(A => \haddr[6]\, B => \haddr[7]\, Y => N_24); - - \r.hslave_0_0_RNIL8HF8[0]\ : MX2C - port map(A => hrdata(7), B => hrdata_1(7), S => - \hslave_0[0]\, Y => N_6342); - - \r.cfgsel_0_0_RNIIVH2B\ : MX2 - port map(A => \un34_hready[6]\, B => N_4876, S => cfgsel_0, - Y => hrdata_0(3)); - - \r.hmaster_0_0_RNIBR6LJ[0]\ : MX2 - port map(A => N_4602, B => N_6495, S => \hmaster_0[0]\, Y - => \haddr[24]\); - - \r.hslave_0_0_RNIAPN1D[0]\ : AO1B - port map(A => N_6341, B => N_663, C => \hrdata_1_0_1[6]\, Y - => hrdata(6)); - - \r.hmasterd_0_RNIRPTG[0]\ : MX2 - port map(A => N_6553, B => N_6506, S => \hmasterd_0[0]\, Y - => hwdata(2)); - - \r.hmasterd_1_RNI7LM9[1]\ : MX2 - port map(A => hwdata_0(10), B => hwdata_1(10), S => - \hmasterd_1[1]\, Y => N_6514); - - \r.hslave_1_RNI3UPA[0]\ : MX2C - port map(A => hrdata_1(19), B => hrdata_2_19, S => - \hslave_1[0]\, Y => N_469); - - \r.hmaster_RNIKBP3[1]\ : OR2B - port map(A => \hmaster[1]\, B => hsize_0(0), Y => N_4651); - - \r.hmaster_0_0_RNIEL59N[0]\ : MX2C - port map(A => N_4610, B => N_6503, S => \hmaster_0[0]\, Y - => \hwrite\); - - \r.hslave_0_0_RNID90B[0]\ : OR3B - port map(A => hresp(0), B => N_651_2, C => \hslave_0[0]\, Y - => N_569); - - \r.hslave_0_0_RNI16LM6_0[2]\ : AO1C - port map(A => N_417_0, B => N_491, C => \hrdata_1_0[12]\, Y - => hrdata_0(12)); - - \r.hslave_0_0_RNI0BKC[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_2_29, C => N_650, - Y => N_606); - - \r.hmasterd_1_RNIAPM9[1]\ : MX2C - port map(A => hwdata_1(31), B => hwdata_2_28, S => - \hmasterd_1[1]\, Y => N_6535); - - \r.haddr_RNI726O[6]\ : NOR3A - port map(A => N_24, B => N_6467, C => N_6474, Y => - \haddr_RNI726O[6]\); - - \r.cfgsel_RNIIIOKI\ : MX2C - port map(A => \un34_hready[17]\, B => N_477, S => cfgsel, Y - => hrdata(14)); - - \r.hslave_0_0_RNIQ8318_0[0]\ : AO1B - port map(A => N_6351, B => N_663, C => \hrdata_1_1[16]\, Y - => hrdata_0(16)); - - \r.hmaster_0_0_RNI87DIJ[0]\ : MX2 - port map(A => N_4596, B => N_6286, S => \hmaster_0[0]\, Y - => \haddr[18]\); - - \r.hslave_1[0]\ : DFN1 - port map(D => \hslave_RNI6LMVPE[0]\, CLK => lclk_c, Q => - \hslave_1[0]\); - - \r.hslave_1_RNILTOA[0]\ : MX2C - port map(A => hrdata(20), B => hrdata_0(20), S => - \hslave_1[0]\, Y => N_470); - - \r.hmaster_0_0_RNIE16CT4[0]\ : NOR3C - port map(A => un2_ioarea_5, B => un2_ioarea_4, C => - un2_ioarea_13, Y => un2_ioarea_16); - - \r.hslave_0_0_RNIBTJG7[2]\ : MX2C - port map(A => N_480, B => N_6344, S => \hslave_0[2]\, Y => - N_488); - - \r.hslave_RNITTOV6[0]\ : OR3C - port map(A => N_536, B => N_535, C => N_534, Y => - hrdata(22)); - - \r.hmasterd_RNIOK4E[1]\ : MX2 - port map(A => hwdata_0(0), B => hwdata_1(0), S => - \hmasterd[1]\, Y => N_6504); - - \r.hmaster_2_RNIKE6V[1]\ : NOR2 - port map(A => hbusreq_i_3_0, B => \haddr[5923]\, Y => - \vect[3]\); - - \r.hrdatam[24]\ : DFN1 - port map(D => \hrdatam_1[24]\, CLK => lclk_c, Q => - \hrdatam[24]\); - - \r.hslave_RNIHFK5[0]\ : MX2C - port map(A => hrdata_1(25), B => hrdata_2_25, S => - \hslave[0]\, Y => N_460); - - \r.hmasterd_0_RNIQJ3T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6528, C => N_94, Y - => hwdata(24)); - - \r.hmasterd_1_RNI9LM9[1]\ : MX2C - port map(A => hwdata_1(30), B => hwdata_2_27, S => - \hmasterd_1[1]\, Y => N_6602); - - \r.hmaster_0_0[1]\ : DFN1 - port map(D => N_5627_i, CLK => lclk_c, Q => \hmaster_0[1]\); - - \r.hmasterd_1_RNIB1N9[1]\ : MX2 - port map(A => hwdata(23), B => hwdata_0(23), S => - \hmasterd_1[1]\, Y => N_6595); - - \r.hmasterd_RNIGJKV[1]\ : OR3A - port map(A => N_423, B => \hmasterd[0]\, C => \hmasterd[1]\, - Y => N_667); - - \r.hmasterd_0_RNI7JA91[0]\ : NOR2B - port map(A => brmw_i, B => hwdata(14), Y => hwdata_m_0_2); - - \r.hslave_RNIH8Q9[0]\ : MX2 - port map(A => hrdata_3_0, B => hrdata_4_0, S => \hslave[0]\, - Y => N_5257); - - \r.cfgsel_0_0_RNIMR2TH\ : MX2C - port map(A => \un34_hready[27]\, B => N_478, S => cfgsel_0, - Y => hrdata_0(24)); - - \r.hmaster_RNI8M8A[1]\ : MX2 - port map(A => haddr_0(31), B => haddr_1(31), S => - \hmaster[1]\, Y => N_6502); - - \r.hmaster_2_RNI18U8[1]\ : MX2 - port map(A => haddr_2(2), B => haddr_3_0, S => - \hmaster_2[1]\, Y => N_4620); - - \r.hmaster_0_0_RNIFCVH1_0[1]\ : AO1C - port map(A => hbusreq_i_3, B => arb_0_sqmuxa_1_a1_0, C => - \vect[3]\, Y => \hmaster_0_0_RNIFCVH1_0[1]\); - - \r.hrdatas[30]\ : DFN1 - port map(D => \hrdatas_RNO[30]\, CLK => lclk_c, Q => - \hrdatas[30]\); - - \r.hslave_0_0_RNIN1N08_0[0]\ : AO1B - port map(A => N_6343, B => N_663, C => \hrdata_0_0_1[8]\, Y - => hrdata_0(8)); - - \r.hslave_0_0_RNIT75O8[0]\ : MX2 - port map(A => hrdata_2_18, B => hrdata_3_18, S => - \hslave_0[0]\, Y => N_6353); - - \r.hmaster_2_RNIGTV9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_0(27), Y => N_4605); - - \r.hmaster_RNITVPPN[0]\ : MX2C - port map(A => N_4576, B => N_4616, S => \hmaster[0]\, Y => - \htrans[0]\); - - \r.hmaster_0_0_RNIUO19[1]\ : NOR2A - port map(A => size(0), B => \hmaster_0[1]\, Y => - \un34_haddr_0[37]\); - - \r.hmasterd_RNIVR0U[0]\ : MX2 - port map(A => N_6551, B => N_6504, S => \hmasterd[0]\, Y - => hwdata(0)); - - \r.hmasterd_RNI4RJV[1]\ : OR3A - port map(A => N_459, B => \hmasterd[0]\, C => \hmasterd[1]\, - Y => N_645); - - \r.hslave_0_0_RNIPLPA[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_2_6, C => N_650, Y - => N_625); - - \r.hslave_RNI3R2LG[2]\ : AO1C - port map(A => N_417, B => N_493, C => N_599, Y => - hrdata_2_15); - - \r.hslave_RNIQJ9AH[2]\ : MX2C - port map(A => N_5281, B => N_6359, S => \hslave[2]\, Y => - N_5349); - - \r.hmasterd_0_RNI6FKH[1]\ : OR2A - port map(A => hwdata_0(30), B => \hmasterd_0[1]\, Y => - N_4734); - - \r.hmasterd_1[1]\ : DFN1E1 - port map(D => \hmaster_0[1]\, CLK => lclk_c, E => - \iosn[93]\, Q => \hmasterd_1[1]\); - - \r.hslave_0_0_RNI6NV3I[2]\ : MX2C - port map(A => N_5271, B => N_6349, S => \hslave_0[2]\, Y - => N_5339); - - \r.hmasterd_RNI6BOG1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6595, C => N_645, Y => - hwdata_1(23)); - - \r.hmasterd_RNIR5TF1[0]\ : MX2 - port map(A => N_4722, B => N_6522, S => \hmasterd[0]\, Y - => hwdata_2_15); - - \r.hslave_0_0[2]\ : DFN1 - port map(D => \hslave_RNIQRGJS9[2]\, CLK => lclk_c, Q => - \hslave_0[2]\); - - \r.hrdatas_RNIOB57[16]\ : OR2B - port map(A => \hrdatas[16]\, B => N_657, Y => N_600); - - \r.defslv_RNO_3\ : NOR2B - port map(A => \iosn_0[93]\, B => \hsel_i[0]\, Y => - defslv_0_sqmuxa_0); - - \r.hmaster_RNI1JVE79[0]\ : OAI1 - port map(A => \hsel_i[0]\, B => \un6_ioen_NE_0\, C => - \un51_ioen_NE\, Y => \hmbsel_1[0]\); - - \r.hrdatas[31]\ : DFN1 - port map(D => \hrdatas_RNO[31]\, CLK => lclk_c, Q => - \hrdatas[31]\); - - \r.hslave_1_RNICPVG[0]\ : OR2B - port map(A => hrdata_4_4, B => N_664, Y => N_584); - - \r.hslave_0_0_RNIN82MC[2]\ : NOR2A - port map(A => N_473, B => N_417, Y => N_264); - - \r.hrdatas_RNO[6]\ : AO1C - port map(A => N_6470, B => \haddr[5]\, C => N_48, Y => - \hrdatas_RNO[6]\); - - \r.hmasterd_1_RNI9PM9[1]\ : MX2 - port map(A => hwdata(21), B => hwdata_0(21), S => - \hmasterd_1[1]\, Y => N_6593); - - \r.haddr_RNIEOPJ_0[8]\ : NOR3B - port map(A => N_6468, B => N_6472, C => N_6465, Y => N_6476); - - \r.hslave_1_RNIDPVG[0]\ : OR2B - port map(A => hrdata_3_5, B => N_664, Y => N_588); - - \r.hmaster_RNIVV36[1]\ : OR2B - port map(A => \hmaster[1]\, B => htrans_0_0, Y => N_4616); - - \r.hmasterd_0_RNI21HI[1]\ : OR3A - port map(A => N_139, B => \hmasterd_0[0]\, C => - \hmasterd_0[1]\, Y => N_206); - - \r.defslv_RNO_1\ : NOR3A - port map(A => defslv_0_sqmuxa_1, B => un5_bnslave, C => - \hmbsel_2[0]\, Y => defslv_0_sqmuxa); - - \un1_acdm_3_0_a2_0_0[57]\ : MX2 - port map(A => data_5, B => data_0_2, S => bo_5842_d_0, Y - => \un1_acdm_3_0_a2_0[57]\); - - \r.hmasterd_0_RNINVI7[1]\ : MX2C - port map(A => hwdata(4), B => hwdata_0(4), S => - \hmasterd_0[1]\, Y => N_6305); - - \r.cfgsel_RNIIS83_0\ : OR2 - port map(A => cfgsel, B => N_643, Y => N_650); - - \r.hslave_RNI2QGJ[2]\ : MX2C - port map(A => N_464, B => N_6361, S => \hslave[2]\, Y => - N_465); - - \r.hmasterd_RNIU30C1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6573, C => N_641, Y => - hwdata_1(1)); - - \r.hmasterlock\ : DFN1 - port map(D => hmasterlock_RNO, CLK => lclk_c, Q => - hmastlock); - - \r.hslave_0_0_RNIRTPA[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_3_8, C => N_650, Y - => N_622); - - \r.hslave_RNIU7LO[2]\ : MX2C - port map(A => N_484, B => N_6348, S => \hslave[2]\, Y => - N_492); - - \r.hmaster_1_RNI0LU9J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_0(22), Y => N_4600); - - \r.hrdatam_RNIS759[12]\ : OR3B - port map(A => \hrdatam[13]\, B => cfgsel_0, C => cfga11, Y - => N_594); - - \r.hmasterd_1_RNIRFJ7[1]\ : MX2 - port map(A => hwdata_0(5), B => hwdata_1(5), S => - \hmasterd_1[1]\, Y => N_6577); - - \r.hrdatas_RNI5QP3[4]\ : NOR2B - port map(A => \hrdatas[9]\, B => N_657, Y => N_581); - - \r.hmasterd_0_RNIGBLH[1]\ : NOR2 - port map(A => hwdata_0(19), B => \hmasterd_0[1]\, Y => - N_4723); - - \r.hmasterd_0[1]\ : DFN1E1 - port map(D => \hmaster_0[1]\, CLK => lclk_c, E => - \iosn[93]\, Q => \hmasterd_0[1]\); - - \r.hmaster_1_RNI8JSB[1]\ : MX2 - port map(A => haddr_0(15), B => haddr_1(15), S => - \hmaster_1[1]\, Y => N_6486); - - \r.hslave_1_RNI8GIRG[0]\ : MX2 - port map(A => hrdata_3_2, B => hrdata_4_2, S => - \hslave_1[0]\, Y => N_6337); - - \r.haddr_RNIT9C4_1[5]\ : NOR2A - port map(A => \haddr_3[4]\, B => \haddr[5]\, Y => N_6472); - - \r.hmaster_0_0[0]\ : DFN1 - port map(D => N_5626_i, CLK => lclk_c, Q => \hmaster_0[0]\); - - \r.hslave_1_RNIAAVDF[0]\ : MX2 - port map(A => hrdata_1(0), B => hrdata_2_0, S => - \hslave_1[0]\, Y => N_6335); - - \r.hrdatas_RNI7QP3[6]\ : OR2B - port map(A => \hrdatas[8]\, B => N_657, Y => N_620); - - \r.hslave_1_RNI5FPNE[0]\ : MX2 - port map(A => hrdata_1(1), B => hrdata_2_1, S => - \hslave_1[0]\, Y => N_6336); - - \r.hslave_0_0_RNI5UPGH[2]\ : MX2C - port map(A => N_5259, B => N_6337, S => \hslave_0[2]\, Y - => N_5327); - - \r.haddr[6]\ : DFN1E1 - port map(D => haddr_2(6), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[6]\); - - \r.hmaster_2_RNI53SB[1]\ : MX2 - port map(A => haddr_0(13), B => haddr_1(13), S => - \hmaster_2[1]\, Y => N_6484); - - \r.hslave_0_0_RNIEL881_1[0]\ : NOR2 - port map(A => hready_1_iv_0_o2_0, B => N_660, Y => - \iosn_0[93]\); - - \r.hmaster[0]\ : DFN1 - port map(D => N_5626_i, CLK => lclk_c, Q => \hmaster[0]\); - - \r.hslave_1_RNIR5PA[0]\ : MX2C - port map(A => hrdata_1(31), B => hrdata_2_31, S => - \hslave_1[0]\, Y => N_486); - - \r.hmaster_0_0_RNIEUKP3[1]\ : NOR3A - port map(A => address(1), B => \hmaster_0[1]\, C => - nbo_5_0(1), Y => \un34_haddr_1[5]\); - - \r.hmasterlock_RNID01N1\ : AOI1 - port map(A => arb_0_sqmuxa_1_a2_0, B => N_4617, C => - hmastlock, Y => arb_0_sqmuxa_0); - - \r.cfgsel_RNIQIMCBC\ : NOR2B - port map(A => rstn, B => N_5557, Y => cfgsel_RNIQIMCBC); - - \r.hslave_1_RNI8TSLF_0[0]\ : AO1B - port map(A => N_6336, B => N_663, C => \hrdata_1_0_1[1]\, Y - => hrdata_0(1)); - - \r.hmaster_RNII6AA[1]\ : MX2 - port map(A => haddr_1(27), B => haddr_2(27), S => - \hmaster[1]\, Y => N_6498); - - \r.hslave_0_0_RNI34T07[0]\ : MX2C - port map(A => hrdata_3_17, B => hrdata_4_17, S => - \hslave_0[0]\, Y => N_6352); - - \r.hmasterd_0_RNIALFM1[0]\ : OR2A - port map(A => hwdata(20), B => N_510, Y => hwdata_m_13); - - \r.hmasterd_RNIHQ8G[1]\ : MX2 - port map(A => hwdata(18), B => hwdata_0(18), S => - \hmasterd[1]\, Y => N_6522); - - \r.hslave_0_0_RNIIK4A6[2]\ : AO1A - port map(A => N_417_0, B => N_489, C => N_581, Y => - hrdata_0(10)); - - \r.hslave_RNIBH9KG[2]\ : MX2C - port map(A => N_5280, B => N_6358, S => \hslave[2]\, Y => - N_5348); - - \r.hmasterd_RNIHO6O[1]\ : NOR2 - port map(A => hwdata_1(17), B => \hmasterd[1]\, Y => N_4721); - - \r.hslave_RNILNK5[0]\ : MX2 - port map(A => hrdata_3_27, B => hrdata_4_27, S => - \hslave[0]\, Y => N_471); - - \r.hmasterd_1_RNIC9N9[1]\ : MX2 - port map(A => hwdata_1(15), B => hwdata_2_12, S => - \hmasterd_1[1]\, Y => N_6519); - - \r.haddr_RNIATVL[2]\ : OR2A - port map(A => N_6476, B => \haddr[2]\, Y => N_6477); - - \r.hmaster_0_0_RNIUQ19[1]\ : MX2 - port map(A => haddr_0(18), B => haddr_1(18), S => - \hmaster_0[1]\, Y => N_6286); - - \r.hslave_RNIFO8E1[2]\ : AO1D - port map(A => N_492, B => N_417_0, C => \hrdata_1_0[13]\, Y - => hrdata_0(13)); - - \r.hslave_0_0_RNIE9JV[0]\ : NOR3C - port map(A => N_625, B => N_620, C => N_626, Y => - \hrdata_1_0_1[6]\); - - \r.hmasterd_RNIDTI41[0]\ : MX2C - port map(A => N_4707, B => N_6304, S => \hmasterd[0]\, Y - => hwdata_1(3)); - - \r.hmasterd_RNI161F[1]\ : NOR2 - port map(A => hwdata_0(6), B => \hmasterd[1]\, Y => N_4710); - - \r.hrdatas_RNO_0[15]\ : OR2A - port map(A => N_25, B => N_6471, Y => N_50); - - \r.hmasterd_RNIDIUS1[0]\ : OR2B - port map(A => brmw_i, B => hwdata(12), Y => hwdata_m_0_0); - - \r.hmaster_RNIEBB7[1]\ : MX2 - port map(A => haddr_0(7), B => haddr_1(7), S => - \hmaster[1]\, Y => N_4625); - - \r.hslave_0_0_RNIBJ5H[2]\ : OA1C - port map(A => N_460, B => \hslave_0[2]\, C => N_417_0, Y - => \hrdata_i_0_0[25]\); - - \r.hmasterd_1_RNID9N9[1]\ : MX2 - port map(A => hwdata_0(25), B => hwdata_1(25), S => - \hmasterd_1[1]\, Y => N_6529); - - \r.haddr_RNI1AC4_1[6]\ : NOR2 - port map(A => \haddr[7]\, B => \haddr[6]\, Y => N_6468); - - \r.defslv_RNO\ : OA1 - port map(A => defslv_RNO_0, B => defslv_0_sqmuxa, C => rstn, - Y => defslv_RNO); - - \r.hslave_0_0_RNISLHH7[2]\ : MX2C - port map(A => N_5274, B => N_6352, S => \hslave_0[2]\, Y - => N_5342); - - \r.hmaster_0_0_RNINFO2AC[0]\ : NOR2B - port map(A => un2_ioarea_17, B => un2_ioarea_16, Y => - un2_ioarea); - - \r.hmasterd_0_RNI8JKH[1]\ : OR2A - port map(A => hwdata_0(31), B => \hmasterd_0[1]\, Y => - N_4735); - - \r.hmaster_0_0_RNIMVHA71[0]\ : NOR2B - port map(A => \haddr[18]\, B => \haddr[19]\, Y => - un2_ioarea_3); - - \r.hmasterd_1_RNIB5N9[1]\ : MX2 - port map(A => hwdata_1(14), B => hwdata_2_11, S => - \hmasterd_1[1]\, Y => N_6586); - - \un1_acdm_3_0_o3_0_m2[76]\ : MX2 - port map(A => data_24, B => data_0_21, S => bo_5842_d, Y - => N_423); - - \r.hmaster_0_0_RNI35KKE2[0]\ : NOR3C - port map(A => \haddr[25]\, B => \haddr[24]\, C => - un2_ioarea_7, Y => un2_ioarea_13); - - \r.hslave_0_0_RNIV5PU[0]\ : NOR3C - port map(A => N_606, B => N_604, C => N_607, Y => - \hrdata_1_1[29]\); - - \r.hslave_0_0_RNIEL881_0[0]\ : NOR2 - port map(A => hready_1_iv_0_o2_0, B => N_660, Y => - \iosn_2[93]\); - - \r.hmaster_RNIQ16MJ[0]\ : MX2 - port map(A => N_4594, B => N_6487, S => \hmaster[0]\, Y => - \haddr[16]\); - - \r.hslave_RNIQFKV7[2]\ : MX2C - port map(A => N_482, B => N_6346, S => \hslave[2]\, Y => - N_490); - - \r.hmasterd_0_RNITR3T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6529, C => N_208, Y - => hwdata(25)); - - \r.hslave_1_RNI5NVE[0]\ : MX2 - port map(A => hrdata_1(3), B => hrdata_2_3, S => - \hslave_1[0]\, Y => N_5260); - - \r.hrdatas_RNI88G3[2]\ : NOR2B - port map(A => \hrdatas[3]\, B => cfga11, Y => N_4876); - - \r.hmasterd_1_RNIVFJ7[1]\ : MX2 - port map(A => hwdata(9), B => hwdata_0(9), S => - \hmasterd_1[1]\, Y => N_6581); - - \r.hmaster_RNI2BB7[1]\ : MX2C - port map(A => haddr_0(1), B => haddr_1(1), S => - \hmaster[1]\, Y => N_4619); - - \r.hmaster_RNI2T0MS[0]\ : MX2 - port map(A => N_4577, B => N_4617, S => \hmaster[0]\, Y => - \htrans[1]\); - - \r.hrdatas[14]\ : DFN1 - port map(D => \hrdatas_RNO[14]\, CLK => lclk_c, Q => - \hrdatas[14]\); - - \r.hmaster_RNI1D75M5[0]\ : OR2A - port map(A => \un1_nhmaster_0_sqmuxa_1\, B => - \bco_msb_1[1]\, Y => \bco_msb_1_m[1]\); - - \r.cfgsel_0_0_RNI0995\ : OR2A - port map(A => N_393, B => cfgsel_0, Y => N_417_0); - - \r.hmasterd_1_RNIUD2P[1]\ : OR3A - port map(A => N_463, B => \hmasterd[0]\, C => - \hmasterd_1[1]\, Y => N_637); - - \r.hrdatas[2]\ : DFN1 - port map(D => hrdatas6, CLK => lclk_c, Q => \hrdatas[3]\); - - \r.hslave_1_RNIJIUIH[0]\ : MX2C - port map(A => hrdata_3_14, B => hrdata_4_14, S => - \hslave_1[0]\, Y => N_6349); - - \r.hmaster_0_0_RNIS83UE2_0[0]\ : NOR2B - port map(A => un51_ioen_NE_0, B => un51_ioen_NE_6, Y => - un51_ioen_NE_1); - - \r.hmaster_RNIFJUME2[0]\ : NOR3C - port map(A => \haddr[17]\, B => \haddr[16]\, C => - un2_ioarea_3, Y => un2_ioarea_11); - - \r.hmaster_0_0_RNI4C9LJ[0]\ : MX2C - port map(A => N_4607, B => N_6500, S => \hmaster_0[0]\, Y - => \haddr[29]\); - - \r.hmaster_1_RNI2JRB[1]\ : MX2 - port map(A => haddr_1(21), B => haddr_2(21), S => - \hmaster_1[1]\, Y => N_6492); - - \r.hslave_1_RNIAET9[0]\ : NOR2 - port map(A => \hslave_1[0]\, B => N_650, Y => N_664); - - \r.hslave_RNO_0[1]\ : MX2C - port map(A => \hslave[1]\, B => \hmbsel_2[0]\, S => - \iosn_2[93]\, Y => \hslave_3[1]\); - - \r.hslave[0]\ : DFN1 - port map(D => \hslave_RNI6LMVPE[0]\, CLK => lclk_c, Q => - \hslave[0]\); - - \r.cfgsel_0_0_RNI7JIUF_0\ : NOR3A - port map(A => N_393, B => cfgsel_0, C => N_5325, Y => - hrdata_0(0)); - - \r.defslv_RNO_2\ : NOR2A - port map(A => defslv_0_sqmuxa_0, B => un2_ioarea, Y => - defslv_0_sqmuxa_1); - - \r.hmaster_2_RNI09U9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_0(30), Y => N_4608); - - \r.hrdatas_RNIP1R6[30]\ : OR2B - port map(A => \hrdatas[30]\, B => cfga11, Y => N_4904); - - \r.hslave_0_0_RNICA1J9_0[0]\ : AO1B - port map(A => N_6353, B => N_663, C => \hrdata_0_0[18]\, Y - => hrdata_0(18)); - - \r.hslave_0_0_RNI1J2D[0]\ : AO1A - port map(A => hready_1_iv_0_a2_0_0, B => N_651_2, C => - hready_RNICLR2, Y => hready_1_iv_0_o2_0); - - \r.hmasterd_0_RNIAVKH[1]\ : NOR2 - port map(A => hwdata_0(16), B => \hmasterd_0[1]\, Y => - N_4720); - - \r.hslave_0_0_RNIIU1HB[0]\ : AO1B - port map(A => N_6340, B => N_663, C => \hrdata_1_1[5]\, Y - => hrdata(5)); - - \r.hmaster_RNI50DPJ[0]\ : MX2 - port map(A => N_4606, B => N_6499, S => \hmaster[0]\, Y => - \haddr[28]\); - - \r.hmaster_1_RNI28U8[1]\ : MX2 - port map(A => haddr_0(3), B => haddr_1(3), S => - \hmaster_1[1]\, Y => N_4621); - - \r.hrdatas_RNO[28]\ : NOR2A - port map(A => N_6472, B => N_6470, Y => \hrdatas_RNO[28]\); - - \r.hmasterd_1_RNIEDN9[1]\ : MX2C - port map(A => hwdata_1(26), B => hwdata_2_23, S => - \hmasterd_1[1]\, Y => N_6530); - - \r.hmasterd_1_RNI0I2P[1]\ : OR3A - port map(A => N_468, B => \hmasterd[0]\, C => - \hmasterd_1[1]\, Y => N_639); - - \r.hmaster_0_0_RNIRMD4[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => \hmaster_0[0]\, Y => - arb_0_sqmuxa_1_a1_0); - - \r.hslave_0_0_RNI2T0G5_0[0]\ : MX2C - port map(A => hrdata(10), B => hrdata_1(10), S => - \hslave_0[0]\, Y => N_6345); - - \r.hmasterd_RNI0L4E[1]\ : MX2 - port map(A => hwdata_0(8), B => hwdata_1(8), S => - \hmasterd[1]\, Y => N_6512); - - \r.hslave_0_0_RNIS8PJH[2]\ : NOR2A - port map(A => N_393, B => N_5327, Y => \un34_hready[5]\); - - \r.hslave_RNIHHQQ[0]\ : NOR3 - port map(A => N_547, B => N_545, C => N_548, Y => - \hrdata_1_0_1[1]\); - - \r.hrdatas[12]\ : DFN1 - port map(D => \hrdatas_RNO[12]\, CLK => lclk_c, Q => - \hrdatas[12]\); - - \r.hmaster_0_0_RNIPS37J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_0(25), Y => N_4603); - - \r.cfgsel_RNIIS83\ : OR2A - port map(A => N_393, B => cfgsel, Y => N_417); - - \r.hrdatas_RNIN757[15]\ : OR2B - port map(A => \hrdatas[15]\, B => N_657, Y => N_599); - - \r.hmaster_2_RNIVOU9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(13), Y => N_4591); - - \r.hmaster_1_RNIIEJ6J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_3_6, Y => N_4586); - - \r.hmaster_RNIT3RFJ[0]\ : MX2 - port map(A => N_4584, B => N_4624, S => \hmaster[0]\, Y => - haddr_2(6)); - - \r.hmasterd_RNI706O[1]\ : NOR2 - port map(A => \hmasterd[1]\, B => N_458, Y => N_6552); - - \r.hmasterd_0_RNIG0GI[1]\ : OR3A - port map(A => \un1_acdm_3_0_a2_0[57]\, B => \hmasterd_0[0]\, - C => \hmasterd_0[1]\, Y => N_6406); - - \r.hslave_RNIQTQQ[0]\ : NOR3B - port map(A => N_583, B => N_584, C => N_581, Y => - \hrdata_0_1[4]\); - - \r.hmaster_RNIJD05J[1]\ : NOR2 - port map(A => \hmaster[1]\, B => haddr_3_5, Y => N_4585); - - \r.hmaster_1_RNIC8U8[1]\ : MX2 - port map(A => haddr_0(8), B => haddr_1(8), S => - \hmaster_1[1]\, Y => N_4626); - - \r.hmaster_2_RNIHBTB[1]\ : MX2 - port map(A => haddr_0(28), B => haddr_1(28), S => - \hmaster_2[1]\, Y => N_6499); - - \r.cfgsel_RNIV2JNH\ : MX2 - port map(A => \un34_hready[5]\, B => N_4876, S => cfgsel, Y - => hrdata(2)); - - \r.hmaster_2_RNIT7U8[1]\ : MX2C - port map(A => haddr_0_d0, B => haddr_0(0), S => - \hmaster_2[1]\, Y => N_4618); - - \r.hmaster_1_RNILIJ6J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_3_7, Y => N_4587); - - \r.hslave_0_0_RNI8P64J[2]\ : NOR2A - port map(A => N_474, B => N_417_0, Y => N_262_0); - - \r.hmasterd_RNI3C9N1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6585, C => N_556, Y => - hwdata_1(13)); - - \r.hrdatas[24]\ : DFN1 - port map(D => \hrdatas_RNO[24]\, CLK => lclk_c, Q => - \hrdatas[24]\); - - \r.hmaster_0_0_RNIGB7LJ[0]\ : MX2 - port map(A => N_4603, B => N_6496, S => \hmaster_0[0]\, Y - => \haddr[25]\); - - \r.hslave_RNIIETLE_0[0]\ : AO1B - port map(A => N_6356, B => N_663, C => \hrdata_0_0[21]\, Y - => hrdata_0(21)); - - \r.hmaster_0_0_RNIHB1OJ[0]\ : MX2 - port map(A => N_4600, B => N_6493, S => \hmaster_0[0]\, Y - => \haddr[22]\); - - \r.hmaster_RNICMMNJ[0]\ : MX2 - port map(A => N_4609, B => N_6502, S => \hmaster[0]\, Y => - \hsel_i[0]\); - - \r.hslave_1_RNID70F[0]\ : MX2C - port map(A => hrdata_3_7, B => hrdata_4_7, S => - \hslave_1[0]\, Y => N_479); - - \r.hmaster_0_0_RNIMQAIJ[0]\ : MX2 - port map(A => N_4601, B => N_6494, S => \hmaster_0[0]\, Y - => \haddr[23]\); - - \r.hmaster_RNI6E8A[1]\ : MX2 - port map(A => haddr_1(30), B => haddr_2(30), S => - \hmaster[1]\, Y => N_6501); - - \r.hmaster_1_RNI0BRB[1]\ : MX2 - port map(A => haddr_0(20), B => haddr_1(20), S => - \hmaster_1[1]\, Y => N_6288); - - \r.hmasterd_RNIGM8G[1]\ : MX2 - port map(A => hwdata(17), B => hwdata_0(17), S => - \hmasterd[1]\, Y => N_6521); - - \r.hslave_RNIII5DG[0]\ : MX2 - port map(A => hrdata_1(23), B => hrdata_2_23, S => - \hslave[0]\, Y => N_6358); - - \r.hslave_RNIMFUC6[0]\ : OR2B - port map(A => N_6357, B => N_663, Y => N_534); - - \r.hslave_1_RNIHF0F[0]\ : MX2C - port map(A => hrdata_3_9, B => hrdata_4_9, S => - \hslave_1[0]\, Y => N_480); - - \r.hrdatas_RNILN47[31]\ : OR2B - port map(A => \hrdatas[31]\, B => N_657, Y => N_609); - - \r.hmasterd_0_RNIEA8S[0]\ : MX2C - port map(A => N_4730, B => N_6530, S => \hmasterd_0[0]\, Y - => hwdata(26)); - - \r.hslave_1_RNI0JBR6[0]\ : MX2C - port map(A => hrdata(9), B => hrdata_1(9), S => - \hslave_1[0]\, Y => N_6344); - - \r.hslave_0_0[0]\ : DFN1 - port map(D => \hslave_RNI6LMVPE[0]\, CLK => lclk_c, Q => - \hslave_0[0]\); - - \r.hmaster_RNI4M8A[1]\ : MX2C - port map(A => haddr_1(11), B => haddr_2(11), S => - \hmaster[1]\, Y => N_6482); - - \r.hmaster_RNI3F6M[1]\ : MX2 - port map(A => htrans_1(1), B => htrans_2(1), S => - \hmaster[1]\, Y => N_4617); - - \un1_acdm_3_0_a2_0_0[55]\ : MX2 - port map(A => data_3, B => data_0_0, S => bo_5842_d_0, Y - => \un1_acdm_3_0_a2_0[55]\); - - \r.hmaster_0_0_RNIDUKP3[1]\ : NOR3A - port map(A => address(0), B => \hmaster_0[1]\, C => - nbo_5_0(1), Y => \un34_haddr_1[4]\); - - \r.hslave_RNI3FCC[0]\ : MX2C - port map(A => hrdata(26), B => hrdata_1(26), S => - \hslave[0]\, Y => N_6361); - - \r.hslave_RNIHU8DH[2]\ : OR2B - port map(A => N_5349, B => N_393, Y => \un34_hready[27]\); - - \r.hslave_0_0_RNILS5EA[0]\ : MX2 - port map(A => hrdata_0(5), B => hrdata_1(5), S => - \hslave_0[0]\, Y => N_6340); - - \r.cfgsel_RNI4JH0B\ : MX2 - port map(A => \un34_hready[6]\, B => N_4876, S => cfgsel, Y - => hrdata(3)); - - \r.hmaster_1_RNIRGU9J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_0(12), Y => N_4590); - - \r.hslave_RNIKN4TD[2]\ : AO1C - port map(A => N_417, B => N_476, C => \hrdata_1_0[28]\, Y - => hrdata(28)); - - \r.cfga11_RNIHMG\ : NOR2B - port map(A => cfgsel, B => cfga11, Y => N_657); - - \r.cfgsel_0_0_RNIDFJPH\ : MX2 - port map(A => \un34_hready[5]\, B => N_4876, S => cfgsel_0, - Y => hrdata_0(2)); - - \r.hslave_1_RNILTB1A[0]\ : AO1B - port map(A => N_6339, B => N_663, C => \hrdata_0_1[4]\, Y - => hrdata(4)); - - \r.hmasterd_RNIE0EM[1]\ : OR3A - port map(A => N_466, B => \hmasterd[0]\, C => \hmasterd[1]\, - Y => N_641); - - \r.hslave_1_RNILTB1A_0[0]\ : AO1B - port map(A => N_6339, B => N_663, C => \hrdata_0_1[4]\, Y - => hrdata_0(4)); - - \r.hmasterlock_RNO\ : OA1 - port map(A => hlock_m_0, B => hmasterlock_2_0, C => rstn, Y - => hmasterlock_RNO); - - \r.hslave_RNINAV2_0[1]\ : OR2B - port map(A => \hslave[2]\, B => \hslave[1]\, Y => N_654); - - \r.hrdatas[16]\ : DFN1 - port map(D => \hrdatas_RNO[16]\, CLK => lclk_c, Q => - \hrdatas[16]\); - - \r.hmaster_1_RNI92J6J[1]\ : NOR2 - port map(A => \hmaster_1[1]\, B => haddr_3_3, Y => N_4583); - - \r.hrdatas_RNI6QP3[5]\ : OR2B - port map(A => \hrdatas[5]\, B => N_657, Y => N_585); - - \r.hmaster_0_0_RNIVNJQK[0]\ : MX2 - port map(A => N_4581, B => N_4621, S => \hmaster_0[0]\, Y - => haddr_2(3)); - - \r.hslave_RNINAV2_1[1]\ : OR2 - port map(A => \hslave[2]\, B => \hslave[1]\, Y => N_643); - - \r.hmaster_1_RNIGJTB[1]\ : MX2 - port map(A => haddr_0(19), B => haddr_1(19), S => - \hmaster_1[1]\, Y => N_6490); - - \r.cfgsel_RNI8F2RH\ : MX2C - port map(A => \un34_hready[27]\, B => N_478, S => cfgsel, Y - => hrdata(24)); - - \r.hmasterlock_RNI4GHMH1\ : NOR3C - port map(A => \hburst[0]\, B => arb_1_sqmuxa_1_0, C => - \htrans[1]\, Y => arb_1_sqmuxa_1_i); - - \r.hslave_0_0_RNIA36S6[0]\ : MX2 - port map(A => hrdata_0(29), B => hrdata_1(29), S => - \hslave_0[0]\, Y => N_6364); - - \r.hrdatam_RNO_0[27]\ : OR2A - port map(A => \haddr[6]\, B => \haddr[7]\, Y => - \hrdatam_1_0_a5_0[27]\); - - \r.hslave_0_0_RNIJ1SB9[2]\ : AO1A - port map(A => N_417, B => N_487, C => N_581, Y => - hrdata_2_7); - - \r.hmaster_0_0_RNI5BCIJ[0]\ : MX2 - port map(A => N_4604, B => N_6294, S => \hmaster_0[0]\, Y - => \haddr[26]\); - - \r.hslave_0_0_RNIP2CA[0]\ : MX2C - port map(A => hrdata_0(30), B => hrdata_1(30), S => - \hslave_0[0]\, Y => N_5287); - - \r.hmaster_2_RNIP8U9J[1]\ : OR2A - port map(A => haddr_0(11), B => \hmaster_2[1]\, Y => N_4589); - - \r.hmaster_0_0_RNITG47J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_2(18), Y => N_4596); - - \r.hmasterd_1_RNI8LM9[1]\ : MX2 - port map(A => hwdata_0(20), B => hwdata_1(20), S => - \hmasterd_1[1]\, Y => N_6524); - - \r.hmasterd_1_RNI1U6A1[1]\ : OR2B - port map(A => N_640, B => N_639, Y => hwdata_1(22)); - - \r.hmaster_2_RNIS3Q8K[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_0(2), Y => N_4580); - - \r.hslave_0_0_RNIN1N08[0]\ : AO1B - port map(A => N_6343, B => N_663, C => \hrdata_0_0_1[8]\, Y - => hrdata(8)); - - \r.cfgsel_0_0_RNIBQIPG\ : NOR3A - port map(A => N_393, B => cfgsel_0, C => N_5348, Y => - hrdata(23)); - - \r.hrdatas_RNO[29]\ : AO1C - port map(A => N_77, B => \haddr[2]\, C => N_6464, Y => - \hrdatas_RNO[29]\); - - \r.hrdatas_RNO[15]\ : OR3C - port map(A => N_6470, B => N_43, C => N_50, Y => - \hrdatas_RNO[15]\); - - \r.hslave_0_0_RNIQC62J[2]\ : NOR2A - port map(A => N_474, B => N_417, Y => N_262); - - \r.hslave_0_0_RNI8JN1C[0]\ : MX2C - port map(A => hrdata(19), B => hrdata_0(19), S => - \hslave_0[0]\, Y => N_6354); - - \r.hslave_0_0_RNIVMCA[0]\ : MX2C - port map(A => hrdata_1(17), B => hrdata_2_17, S => - \hslave_0[0]\, Y => N_5274); - - \r.hmaster_0_0_RNIA71OJ[0]\ : MX2 - port map(A => N_4590, B => N_6483, S => \hmaster_0[0]\, Y - => \haddr[12]\); - - \r.hready\ : DFN1 - port map(D => hready_RNICLR2, CLK => lclk_c, Q => hready_2); - - \r.hmasterd_RNIB28G[1]\ : MX2 - port map(A => hwdata_1(12), B => hwdata_2_9, S => - \hmasterd[1]\, Y => N_6516); - - \r.hslave_RNITTUF8[2]\ : OAI1 - port map(A => N_417_0, B => N_475, C => N_572, Y => - hrdata_0(27)); - - \r.hslave_0_0_RNIQ6KC[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_3_16, C => N_650, - Y => N_602); - - \r.hrdatas_RNITFBG[28]\ : AOI1B - port map(A => \hrdatas[28]\, B => N_657, C => N_572, Y => - \hrdata_1_0[28]\); - - \r.hmaster_2_RNIJ62A1[1]\ : MX2C - port map(A => hbusreq_i_3, B => hbusreq_i_3_0, S => - \hmaster_2[1]\, Y => N_4574); - - \r.hmasterd_1_RNIFHN9[1]\ : MX2 - port map(A => hwdata_0(27), B => hwdata_1(27), S => - \hmasterd_1[1]\, Y => N_6531); - - \r.hmaster_RNIG905J[1]\ : NOR2 - port map(A => \hmaster[1]\, B => haddr_3_4, Y => N_4584); - - \r.hslave_RNIB7S7[0]\ : OR3B - port map(A => \hslave[0]\, B => hrdata_3_22, C => N_650, Y - => N_535); - - \r.hslave_RNIQMKAG[2]\ : MX2C - port map(A => N_485, B => N_6350, S => \hslave[2]\, Y => - N_493); - - \r.hslave_0_0_RNICQ9AL[2]\ : MX2C - port map(A => N_486, B => N_6366, S => \hslave_0[2]\, Y => - N_494); - - \r.haddr[4]\ : DFN1E1 - port map(D => haddr_1(4), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr_3[4]\); - - \r.hmasterd_0_RNIFE8S[0]\ : MX2 - port map(A => N_4723, B => N_6523, S => \hmasterd_0[0]\, Y - => hwdata(19)); - - \r.hslave_RNI5BG9D[2]\ : MX2C - port map(A => N_472, B => N_6363, S => \hslave[2]\, Y => - N_476); - - \r.hslave_0_0_RNIOHPA[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_2_5, C => N_650, Y - => N_587); - - \r.defslv_RNI7VEF\ : OR2B - port map(A => N_569, B => N_568, Y => hresp_0(0)); - - \r.cfgsel_RNIIS83_1\ : NOR2 - port map(A => cfgsel, B => N_654, Y => N_663); - - \r.hmasterlock_RNO_1\ : AO1A - port map(A => \iosn_0[93]\, B => hmastlock, C => hlock_m, Y - => hmasterlock_2_0); - - \r.hrdatas_RNO[14]\ : OR3C - port map(A => N_6471, B => N_43, C => N_49, Y => - \hrdatas_RNO[14]\); - - \r.hmaster_0_0_RNICQIJ44[1]\ : OR2A - port map(A => \arb_1\, B => \hmaster_0_0_RNIFCVH1_0[1]\, Y - => \l1_0_m[1]\); - - \r.hrdatas[26]\ : DFN1 - port map(D => \haddr_RNI726O[5]\, CLK => lclk_c, Q => - \hrdatas[26]\); - - \r.hmasterd_0_RNID9N9[1]\ : MX2 - port map(A => hwdata_1(19), B => hwdata_2_16, S => - \hmasterd_0[1]\, Y => N_6523); - - \r.hmasterd_1_RNITFJ7[1]\ : MX2 - port map(A => hwdata_1(7), B => hwdata_2_4, S => - \hmasterd_1[1]\, Y => N_6511); - - \r.hmaster_RNIUUASR[1]\ : NOR2A - port map(A => htrans_3(1), B => \hmaster[1]\, Y => N_4577); - - \r.hmaster_0_0_RNIL72OJ[0]\ : MX2 - port map(A => N_4592, B => N_6485, S => \hmaster_0[0]\, Y - => \haddr[14]\); - - \r.hslave_0_0_RNI5CPIC[2]\ : MX2C - port map(A => N_469, B => N_6354, S => \hslave_0[2]\, Y => - N_473); - - \r.hslave_0_0_RNI48486[2]\ : AO1A - port map(A => N_417, B => N_489, C => N_581, Y => - hrdata_2_10); - - \r.hmaster_2_RNISRDB[1]\ : NOR2B - port map(A => hburst_0(1), B => \haddr[5923]\, Y => - \hburst[1]\); - - \r.hrdatas_RNO[17]\ : AO1C - port map(A => N_6470, B => \haddr_3[4]\, C => N_6477, Y => - \hrdatas_RNO[17]\); - - \r.hmaster_1[1]\ : DFN1 - port map(D => N_5627_i, CLK => lclk_c, Q => \hmaster_1[1]\); - - \r.hslave_0_0_RNIDH116[2]\ : MX2C - port map(A => N_481, B => N_6345, S => \hslave_0[2]\, Y => - N_489); - - \r.hmasterd_0_RNIARA91[0]\ : OR2B - port map(A => brmw_i, B => hwdata(15), Y => hwdata_m_0_3); - - \r.hmasterd_0_RNI1U6S[0]\ : MX2C - port map(A => N_4734, B => N_6602, S => \hmasterd_0[0]\, Y - => hwdata(30)); - - \r.hslave_0_0_RNIAJRUB[0]\ : MX2 - port map(A => hrdata_0(6), B => hrdata_1(6), S => - \hslave_0[0]\, Y => N_6341); - - \r.hmaster_0_0_RNI8U5A71_0[0]\ : NOR2 - port map(A => \haddr[26]\, B => \haddr[27]\, Y => - un51_ioen_NE_10_3); - - \r.hslave_RNINAV2[1]\ : XNOR2 - port map(A => \hslave[1]\, B => \hslave[2]\, Y => N_393); - - \r.hslave_RNIH73NG[2]\ : AO1C - port map(A => N_417_0, B => N_493, C => N_599, Y => - hrdata_0(15)); - - \r.hslave_0_0_RNIJJQT6[0]\ : MX2 - port map(A => hrdata_1(8), B => hrdata_2_8, S => - \hslave_0[0]\, Y => N_6343); - - \r.hslave_0_0_RNIKG9G[0]\ : OR3 - port map(A => \hslave_0[0]\, B => hready_0, C => N_643, Y - => N_648); - - \r.hslave[1]\ : DFN1 - port map(D => \hslave_RNO[1]\, CLK => lclk_c, Q => - \hslave[1]\); - - \r.hslave_0_0_RNIEL881_2[0]\ : NOR2 - port map(A => hready_1_iv_0_o2_0, B => N_660, Y => - \iosn_1[93]\); - - \r.hmasterd_0_RNI7UP5[1]\ : OA1C - port map(A => bo_5842_d_0, B => data_0_d0, C => - \hmasterd_0[1]\, Y => N_4709); - - \r.cfgsel_0_0\ : DFN1 - port map(D => cfgsel_RNIQIMCBC, CLK => lclk_c, Q => - cfgsel_0); - - \r.hmaster_0_0_RNIS83UE2[0]\ : OR3B - port map(A => \haddr[28]\, B => un51_ioen_NE_6, C => - \haddr[29]\, Y => un271_ioen_NE); - - \r.hslave_RNIHE0UG[0]\ : MX2C - port map(A => N_95_i_0, B => hrdata_3_24, S => \hslave[0]\, - Y => N_6359); - - \r.haddr_RNIEOPJ[8]\ : NOR3B - port map(A => N_6469, B => hrdatas6_0_a5_1, C => N_6474, Y - => hrdatas6); - - \r.hmaster_0_0_RNI4U71R2[0]\ : OR2A - port map(A => \hwrite\, B => brmw_1, Y => hwrite_m_0_0); - - \r.hmasterd_RNIQ0BN1[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6601, C => N_667, Y => - hwdata(29)); - - \r.hmaster_RNITJMPR9[0]\ : MX2B - port map(A => \hmaster[0]\, B => \nhmaster_1_i[0]\, S => - \iosn_1[93]\, Y => \hmaster_3[0]\); - - \r.hmaster_2_RNI3U8H[1]\ : MX2C - port map(A => hwrite_0, B => hwrite_1, S => \hmaster_2[1]\, - Y => N_6503); - - \r.hmaster_1_RNI2RRB[1]\ : MX2 - port map(A => haddr_1(12), B => haddr_2(12), S => - \hmaster_1[1]\, Y => N_6483); - - \r.hslave_0_0_RNIQ8318[0]\ : AO1B - port map(A => N_6351, B => N_663, C => \hrdata_1_1[16]\, Y - => hrdata(16)); - - \r.hmasterd_RNIM9J41[0]\ : MX2 - port map(A => N_4710, B => N_6510, S => \hmasterd[0]\, Y - => hwdata(6)); - - \r.hmasterd_0_RNI3C4T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6531, C => N_206, Y - => hwdata(27)); - - \r.hmaster_RNIBGOAQ[0]\ : MX2C - port map(A => N_4573, B => N_4574, S => \hmaster[0]\, Y => - \un34_haddr[0]\); - - \r.hmasterd[0]\ : DFN1E1 - port map(D => \hmaster[0]\, CLK => lclk_c, E => \iosn[93]\, - Q => \hmasterd[0]\); - - \r.hmaster_RNISUK5O[0]\ : MX2C - port map(A => N_4611, B => N_4651, S => \hmaster[0]\, Y => - hsize(0)); - - \r.defslv_RNIQLE4\ : OR3B - port map(A => \htrans_0[1]\, B => defslv, C => cfgsel_0, Y - => N_568); - - \r.hrdatas[1]\ : DFN1 - port map(D => \hrdatas_RNO[1]\, CLK => lclk_c, Q => - \hrdatas[1]\); - - \r.hmaster_0_0_RNIGMOHJ[0]\ : MX2 - port map(A => N_4587, B => N_4627, S => \hmaster_0[0]\, Y - => haddr_2(9)); - - \r.hmaster_1_RNI68U8[1]\ : MX2 - port map(A => haddr_0(5), B => haddr_1(5), S => - \hmaster_1[1]\, Y => N_4623); - - \r.hslave_1_RNIEPVG[0]\ : OR2B - port map(A => hrdata_3_6, B => N_664, Y => N_626); - - \r.hmasterd_0_RNI8RKH[1]\ : NOR2 - port map(A => hwdata_0(15), B => \hmasterd_0[1]\, Y => - N_4719); - - \r.hrdatas[6]\ : DFN1 - port map(D => \hrdatas_RNO[6]\, CLK => lclk_c, Q => - \hrdatas[8]\); - - \r.hslave_0_0_RNI8GTUI[2]\ : MX2C - port map(A => N_470, B => N_6355, S => \hslave_0[2]\, Y => - N_474); - - \r.cfgsel\ : DFN1 - port map(D => cfgsel_RNIQIMCBC, CLK => lclk_c, Q => cfgsel); - - \r.hmaster_RNITG6GN[1]\ : AO1 - port map(A => lb_0_sqmuxa_1, B => htrans_0_sqmuxa_2, C => - \hmaster[1]\, Y => N_4576); - - \r.hslave_1_RNITDPA[0]\ : MX2C - port map(A => hrdata_1(24), B => hrdata_2_24, S => - \hslave_1[0]\, Y => N_5281); - - \r.hmaster_0_0_RNI8U5A71[0]\ : NOR2B - port map(A => \haddr[26]\, B => \haddr[27]\, Y => - un2_ioarea_7); - - \r.hmaster_2_RNIICC5[1]\ : OR2A - port map(A => \hmaster_2[1]\, B => hsize_0(1), Y => N_4652); - - \r.hslave_RNI1C8C1[2]\ : AO1D - port map(A => N_492, B => N_417, C => \hrdata_1_0[13]\, Y - => hrdata(13)); - - \r.hrdatas[5]\ : DFN1 - port map(D => \hrdatas_RNO[5]\, CLK => lclk_c, Q => - \hrdatas[5]\); - - \r.hmaster_2_RNI21V9J[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(14), Y => N_4592); - - \r.haddr_RNI726O_0[5]\ : OR2 - port map(A => N_6474, B => N_6471, Y => N_48); - - \r.hslave_1_RNIVMUA[0]\ : OR2B - port map(A => hrdata_4_16, B => N_664, Y => N_603); - - \r.hslave_0_0_RNINT6S7[2]\ : MX2C - port map(A => N_5287, B => N_6365, S => \hslave_0[2]\, Y - => N_5355); - - \r.hslave_RNID7K5[0]\ : MX2 - port map(A => hrdata_3_23, B => hrdata_4_23, S => - \hslave[0]\, Y => N_5280); - - \r.hmaster_0_0_RNIKE9R[1]\ : OAI1 - port map(A => \hburst[1]\, B => \hburst[2]\, C => - arb_0_sqmuxa_1_a1_0, Y => arb_0_sqmuxa_1_a1_1); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.hmaster_RNITDJ134[0]\ : MX2 - port map(A => arb_0_sqmuxa_1, B => \un34_haddr[0]\, S => - arb_1_sqmuxa_1_i, Y => \arb_1\); - - \r.hmaster_RNI5BAPJ[0]\ : MX2 - port map(A => N_4591, B => N_6484, S => \hmaster[0]\, Y => - \haddr[13]\); - - \r.hmasterd[1]\ : DFN1E1 - port map(D => \hmaster[1]\, CLK => lclk_c, E => \iosn[93]\, - Q => \hmasterd[1]\); - - \r.haddr_RNI726O[5]\ : NOR2A - port map(A => N_6461, B => N_6471, Y => \haddr_RNI726O[5]\); - - \r.hslave_1_RNIGPVG[0]\ : OR2B - port map(A => hrdata_4_8, B => N_664, Y => N_623); - - \r.hrdatam_RNISUFD[24]\ : MX2C - port map(A => \hrdatam[24]\, B => \hrdatas[24]\, S => - cfga11, Y => N_478); - - \r.hslave_RNIQ9BQ7[0]\ : MX2 - port map(A => hrdata(27), B => hrdata_1(27), S => - \hslave[0]\, Y => N_6362); - - \r.hmaster_1_RNI6BSB[1]\ : MX2 - port map(A => haddr_0(14), B => haddr_1(14), S => - \hmaster_1[1]\, Y => N_6485); - - \r.hrdatam[27]\ : DFN1 - port map(D => \hrdatam_1[28]\, CLK => lclk_c, Q => - \hrdatam[28]\); - - \r.hslave_0_0_RNIT5JN[0]\ : AOI1B - port map(A => hrdata(18), B => N_664, C => N_580, Y => - \hrdata_0_0[18]\); - - \r.hmaster_0_0_RNI4M5D71[0]\ : NOR2B - port map(A => \haddr[20]\, B => \haddr[21]\, Y => - un2_ioarea_4); - - \r.hslave_0_0_RNI5L2OC[2]\ : NOR2A - port map(A => N_473, B => N_417_0, Y => N_264_0); - - \r.hslave_1_RNI8TSLF[0]\ : AO1B - port map(A => N_6336, B => N_663, C => \hrdata_1_0_1[1]\, Y - => hrdata(1)); - - \r.hmaster_RNIED90N1[0]\ : NOR3B - port map(A => \hmaster_0_0_RNIFG08O[1]\, B => - arb_0_sqmuxa_1_0, C => \htrans[0]\, Y => arb_0_sqmuxa_1); - - \r.haddr_RNIAOPJ_0[6]\ : OR2A - port map(A => N_6468, B => N_6467, Y => N_6471); - - \r.hrdatas_RNO_0[29]\ : OR2 - port map(A => N_6474, B => N_6470, Y => N_6464); - - \r.hrdatas_RNIPB57[26]\ : OR2B - port map(A => \hrdatas[26]\, B => N_657, Y => N_525); - - \r.hmaster_RNIS83UE2[0]\ : NOR3C - port map(A => \hsel_i[0]\, B => \haddr[30]\, C => - un2_ioarea_8, Y => un2_ioarea_14); - - \r.hmaster_0_0_RNIJC37J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_2(23), Y => N_4601); - - \r.hmasterd_0_RNIK79E[0]\ : MX2 - port map(A => N_4709, B => N_6577, S => \hmasterd_0[0]\, Y - => hwdata(5)); - - \r.hmasterd_1_RNIROF8[1]\ : OR2A - port map(A => hwdata_2_1, B => \hmasterd_1[1]\, Y => N_4708); - - \r.hmasterd_0_RNIKQ8S[0]\ : MX2C - port map(A => N_4732, B => N_6600, S => \hmasterd_0[0]\, Y - => hwdata(28)); - - \r.hslave_0_0_RNI2KMN7[2]\ : AO1A - port map(A => N_417, B => N_488, C => N_581, Y => - hrdata_2_9); - - \r.hrdatas[4]\ : DFN1 - port map(D => \haddr_RNI726O[6]\, CLK => lclk_c, Q => - \hrdatas[9]\); - - \r.hmaster_0_0_RNI373TN[1]\ : OR3C - port map(A => nbo_5_0(0), B => \un34_haddr_1[4]\, C => - un91_nbo_i_0, Y => N_4578_i); - - \r.hmasterlock_RNI2TEU6\ : OA1 - port map(A => arb_0_sqmuxa_1_a1_1, B => htrans_tz(1), C => - arb_0_sqmuxa_0, Y => arb_0_sqmuxa_1_0); - - \r.hmasterd_0_RNIK0F8[1]\ : NOR2 - port map(A => \hmasterd_0[1]\, B => N_467, Y => N_6553); - - \r.hslave_RNI4JL96[0]\ : MX2 - port map(A => hrdata_1(22), B => hrdata_2_22, S => - \hslave[0]\, Y => N_6357); - - \r.hmaster_0_0_RNIAA9AC7_0[0]\ : OR3C - port map(A => un51_ioen_NE_10_4, B => un51_ioen_NE_10_5, C - => un315_ioen_NE_1, Y => \un315_ioen_NE\); - - \r.hslave_0_0_RNIHP116[2]\ : MX2C - port map(A => N_483, B => N_6347, S => \hslave_0[2]\, Y => - N_491); - - \r.hmasterd_0_RNI968S[0]\ : MX2 - port map(A => N_4720, B => N_6520, S => \hmasterd_0[0]\, Y - => hwdata(16)); - - \r.hmaster_0_0_RNIS447J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_2(26), Y => N_4604); - - \r.hmasterd_0_RNI6U7S[0]\ : MX2 - port map(A => N_4719, B => N_6519, S => \hmasterd_0[0]\, Y - => hwdata(15)); - - \r.hmasterd_0_RNIIIB9[1]\ : OR3A - port map(A => \un1_acdm_3_0_a2_0[55]\, B => \hmasterd_0[0]\, - C => \hmasterd_0[1]\, Y => N_6404); - - \r.defslv\ : DFN1 - port map(D => defslv_RNO, CLK => lclk_c, Q => defslv); - - \r.hmasterd_0_RNIE3LH[1]\ : OR2A - port map(A => hwdata_0(26), B => \hmasterd_0[1]\, Y => - N_4730); - - \r.hrdatas_RNIG3AG[12]\ : AOI1B - port map(A => \hrdatas[12]\, B => N_657, C => N_594, Y => - \hrdata_1_0[12]\); - - \r.hmaster_0_0_RNI9CME71[0]\ : NOR2B - port map(A => \haddr[28]\, B => \haddr[29]\, Y => - un2_ioarea_8); - - \r.haddr[7]\ : DFN1E1 - port map(D => haddr_2(7), CLK => lclk_c, E => \iosn[93]\, Q - => \haddr[7]\); - - \r.hmaster_0_0_RNIUHG1F2[0]\ : NOR3C - port map(A => \haddr[13]\, B => \haddr[12]\, C => - un2_ioarea_1, Y => un2_ioarea_10); - - \r.hslave_1_RNI9DHH[0]\ : MX2 - port map(A => hrdata_1(13), B => hrdata_2_13, S => - \hslave_1[0]\, Y => N_6348); - - \r.hmaster_RNIEFUDQ9[0]\ : OAI1 - port map(A => \un1_nhmaster_0_sqmuxa_1\, B => \hmaster[0]\, - C => \bco_msb_1_i_m[0]\, Y => \nhmaster_1_i[0]\); - - \r.hslave_RNIH6N68[2]\ : AO1A - port map(A => N_417, B => N_490, C => N_581, Y => - hrdata_2_11); - - \r.hmasterd_1_RNIIQUU[1]\ : OR2B - port map(A => N_521, B => N_520, Y => hwdata_1(9)); - - \r.haddr[5]\ : DFN1E1 - port map(D => haddr_2(5), CLK => lclk_c, E => \iosn_2[93]\, - Q => \haddr[5]\); - - \r.hrdatas_RNO[12]\ : OR3B - port map(A => N_48, B => \hrdatas_0_0_0[12]\, C => - \haddr_RNI726O[5]\, Y => \hrdatas_RNO[12]\); - - \r.hmaster_0_0_RNIFV4G71[0]\ : NOR2B - port map(A => \haddr[14]\, B => \haddr[15]\, Y => - un2_ioarea_1); - - \r.haddr_RNIAOPJ[6]\ : OR2A - port map(A => N_6469, B => N_6467, Y => N_6470); - - \r.hslave_RNIREVV[2]\ : AO1C - port map(A => N_417_0, B => N_465, C => N_525, Y => - hrdata_0(26)); - - \r.hslave_0_0_RNI40JB7[0]\ : MX2C - port map(A => hrdata_2_30, B => hrdata_3_30, S => - \hslave_0[0]\, Y => N_6365); - - \r.hslave_0_0_RNI1ESD9[2]\ : AO1A - port map(A => N_417_0, B => N_487, C => N_581, Y => - hrdata_0(7)); - - \r.hmaster_0_0_RNISA5LJ[0]\ : MX2 - port map(A => N_4599, B => N_6492, S => \hmaster_0[0]\, Y - => \haddr[21]\); - - \r.hmaster_0_0_RNI070OJ[0]\ : MX2C - port map(A => N_4588, B => N_6481, S => \hmaster_0[0]\, Y - => haddr_0(10)); - - \r.hrdatas_RNO[31]\ : AO1C - port map(A => N_6470, B => \haddr_3[4]\, C => N_48, Y => - \hrdatas_RNO[31]\); - - \r.hmaster_RNIG6AA[1]\ : MX2 - port map(A => haddr_0(17), B => haddr_1(17), S => - \hmaster[1]\, Y => N_6488); - - \r.hrdatas[13]\ : DFN1 - port map(D => \hrdatas_RNO[13]\, CLK => lclk_c, Q => - \hrdatas[13]\); - - \r.hmaster_0_0_RNI8B0OJ[0]\ : MX2 - port map(A => N_4598, B => N_6288, S => \hmaster_0[0]\, Y - => \haddr[20]\); - - \r.hmaster_0_0_RNIDS27J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_0(21), Y => N_4599); - - \r.hslave_RNIVIN88[2]\ : AO1A - port map(A => N_417_0, B => N_490, C => N_581, Y => - hrdata_0(11)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.hrdatam[14]\ : DFN1 - port map(D => \hrdatam_1[14]\, CLK => lclk_c, Q => - \hrdatam[14]\); - - \r.hmasterlock_RNO_3\ : NOR3 - port map(A => \hmaster_3[1]\, B => hlock, C => - \hmaster_3[0]\, Y => hlock_m); - - \r.hmasterd_0_RNISKGI[1]\ : OR3A - port map(A => \un1_acdm_3_0_a3_0_0[71]_net_1\, B => - \hmasterd_0[0]\, C => \hmasterd_0[1]\, Y => N_94); - - \r.cfgsel_RNI2SA68\ : MX2C - port map(A => \un34_hready[33]\, B => N_4904, S => cfgsel, - Y => hrdata(30)); - - \r.hslave_RNIA7S7[0]\ : OR3B - port map(A => \hslave[0]\, B => hrdata_4_21, C => N_650, Y - => N_576); - - \r.hmaster_RNI9NNUS4[0]\ : OA1A - port map(A => hbusreq_i_3_0, B => \bco_msb_1[1]\, C => - \arb_1\, Y => \un1_nhmaster_0_sqmuxa_1\); - - \r.hslave_0_0_RNIJ0HK7[2]\ : OR2B - port map(A => N_5342, B => N_393, Y => \un34_hready[20]\); - - \r.hrdatas[15]\ : DFN1 - port map(D => \hrdatas_RNO[15]\, CLK => lclk_c, Q => - \hrdatas[15]\); - - \r.hslave[2]\ : DFN1 - port map(D => \hslave_RNIQRGJS9[2]\, CLK => lclk_c, Q => - \hslave[2]\); - - \r.hmaster_RNI1UG9O[0]\ : MX2C - port map(A => N_4578_i, B => N_4618, S => \hmaster[0]\, Y - => haddr_1(0)); - - \r.hmaster_0_0_RNI4QOPNE[1]\ : OR2B - port map(A => \nhmaster_1_iv_0[1]\, B => \bco_msb_1_m[1]\, - Y => \nhmaster_1[1]\); - - \r.hmasterd_0_RNI972T[0]\ : AO1B - port map(A => \hmasterd_0[0]\, B => N_6583, C => N_523, Y - => hwdata_1(11)); - - \hrdata_1_0_a2_0[1]\ : NAND2 - port map(A => N_663, B => N_6336, Y => N_546); - - \r.hmasterd_1_RNIDDN9[1]\ : MX2 - port map(A => hwdata_1(16), B => hwdata_2_13, S => - \hmasterd_1[1]\, Y => N_6520); - - \r.hslave_RNIJJK5[0]\ : MX2C - port map(A => hrdata_3_26, B => hrdata_4_26, S => - \hslave[0]\, Y => N_464); - - \r.hmaster_2_RNIJ50AJ[1]\ : NOR2 - port map(A => \hmaster_2[1]\, B => haddr_2(28), Y => N_4606); - - \r.hmasterd_RNI9LRF1[0]\ : MX2 - port map(A => N_4716, B => N_6516, S => \hmasterd[0]\, Y - => hwdata(12)); - - \r.hmaster_2_RNINQ6TO[1]\ : NOR2A - port map(A => hbusreq, B => \hmaster_2[1]\, Y => N_4573); - - \r.hslave_0_0_RNIN22V6[0]\ : MX2 - port map(A => hrdata_1(16), B => hrdata_2_16, S => - \hslave_0[0]\, Y => N_6351); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.hslave_RNIIETLE[0]\ : AO1B - port map(A => N_6356, B => N_663, C => \hrdata_0_0[21]\, Y - => hrdata_1(21)); - - \r.hmasterd_RNI9MTU[0]\ : AO1B - port map(A => \hmasterd[0]\, B => N_6512, C => N_6404, Y - => hwdata(8)); - - \r.hmasterd_1_RNIC5N9[1]\ : MX2 - port map(A => hwdata_0(24), B => hwdata_1(24), S => - \hmasterd_1[1]\, Y => N_6528); - - \r.hmaster_RNIVH6MJ[0]\ : MX2 - port map(A => N_4595, B => N_6488, S => \hmaster[0]\, Y => - \haddr[17]\); - - \r.hmaster_RNI76MNJ[0]\ : MX2 - port map(A => N_4608, B => N_6501, S => \hmaster[0]\, Y => - \haddr[30]\); - - \r.hslave_1_RNIPNSDI[0]\ : MX2C - port map(A => N_90_i_0, B => hrdata_1(20), S => - \hslave_1[0]\, Y => N_6355); - - \r.hslave_1_RNI33VA[0]\ : OR2B - port map(A => hrdata_3_29, B => N_664, Y => N_607); - - \r.hrdatam[12]\ : DFN1 - port map(D => \hrdatam_1[13]\, CLK => lclk_c, Q => - \hrdatam[13]\); - - \r.defslv_RNILUH3\ : NOR2 - port map(A => N_643, B => N_403, Y => N_651_2); - - \r.hready_RNICLR2\ : NOR3B - port map(A => \htrans_0[1]\, B => N_403, C => hready_2, Y - => hready_RNICLR2); - - \r.hslave_RNIROF18[2]\ : MX2C - port map(A => N_471, B => N_6362, S => \hslave[2]\, Y => - N_475); - - \r.hslave_RNI5AQI[0]\ : AOI1B - port map(A => hrdata(21), B => N_664, C => N_576, Y => - \hrdata_0_0[21]\); - - \r.hslave_0_0_RNIIHJV[0]\ : NOR3C - port map(A => N_622, B => N_620, C => N_623, Y => - \hrdata_0_0_1[8]\); - - \r.hslave_RNIEKIAI_0[1]\ : NOR2B - port map(A => \hrdata_i_0_0[25]\, B => N_628, Y => N_78_0); - - \r.hslave_RNIEKIAI[1]\ : NOR2B - port map(A => \hrdata_i_0_0[25]\, B => N_628, Y => N_78); - - \r.hslave_1_RNI9TGO7[0]\ : MX2C - port map(A => hrdata(11), B => hrdata_1(11), S => - \hslave_1[0]\, Y => N_6346); - - \r.haddr_RNIG41B_0[8]\ : NOR3C - port map(A => \haddr[9]\, B => \haddr[8]\, C => \haddr[10]\, - Y => hrdatas6_0_a5_1); - - \r.hmaster_0_0_RNI49NBT4[1]\ : OR3C - port map(A => hbusreq, B => \bco_msb_1_i_m_0[0]\, C => - \arb_1\, Y => \bco_msb_1_i_m[0]\); - - \r.hmasterd_RNIC68G[1]\ : MX2 - port map(A => hwdata(13), B => hwdata_0(13), S => - \hmasterd[1]\, Y => N_6585); - - \r.defslv_RNIUJI\ : OR2 - port map(A => defslv, B => cfgsel, Y => N_403); - - \r.hmaster_2_RNI0RH8[1]\ : NOR2B - port map(A => \hmaster_2[1]\, B => \hmaster[0]\, Y => - \haddr[5923]\); - - \r.hmaster_2[1]\ : DFN1 - port map(D => N_5627_i, CLK => lclk_c, Q => \hmaster_2[1]\); - - \r.hslave_0_0_RNICA1J9[0]\ : AO1B - port map(A => N_6353, B => N_663, C => \hrdata_0_0[18]\, Y - => hrdata_1(18)); - - \r.hrdatas_RNI2QP3[1]\ : NOR2B - port map(A => \hrdatas[1]\, B => N_657, Y => N_545); - - \r.hmaster_1_RNIE8U8[1]\ : MX2 - port map(A => haddr_0(9), B => haddr_1(9), S => - \hmaster_1[1]\, Y => N_4627); - - \r.haddr_RNI726O[3]\ : AO1B - port map(A => \haddr[3]\, B => \haddr[2]\, C => N_6476, Y - => N_43); - - \r.hslave_RNO[1]\ : NOR2A - port map(A => rstn, B => \hslave_3[1]\, Y => - \hslave_RNO[1]\); - - \r.hrdatas_RNO_0[14]\ : OR2 - port map(A => N_6470, B => N_6461, Y => N_49); - - \r.hmaster_RNI3JPNJ[0]\ : MX2 - port map(A => N_4605, B => N_6498, S => \hmaster[0]\, Y => - \haddr[27]\); - - \r.hmaster_0_0_RNIMK37J[1]\ : NOR2 - port map(A => \hmaster_0[1]\, B => haddr_0(24), Y => N_4602); - - \r.hslave_0_0_RNIJENKL[2]\ : AO1C - port map(A => N_417, B => N_494, C => N_609, Y => - hrdata_0(31)); - - \r.hmaster_RNI76CN2J[0]\ : NOR2 - port map(A => \hmbsel_2[0]\, B => \hmbsel_1[0]\, Y => - hmbsel(0)); - - \r.hrdatas[17]\ : DFN1 - port map(D => \hrdatas_RNO[17]\, CLK => lclk_c, Q => - \hrdatas[17]\); - - \r.hmasterd_RNIRK4E[1]\ : MX2C - port map(A => hwdata(3), B => hwdata_0(3), S => - \hmasterd[1]\, Y => N_6304); - - \r.hslave_RNI9A16[0]\ : OR3B - port map(A => \hslave[0]\, B => hrdata_3_4, C => N_650, Y - => N_583); - - \r.hslave_0_0_RNIEL881[0]\ : NOR2 - port map(A => hready_1_iv_0_o2_0, B => N_660, Y => - \iosn[93]\); - - \r.hslave_0_0_RNIT1V6I[2]\ : OR2B - port map(A => N_5339, B => N_393, Y => \un34_hready[17]\); - - \r.hmasterd_0_RNIUKF8[1]\ : NOR2 - port map(A => hwdata_0(7), B => \hmasterd_0[1]\, Y => - N_4711); - - \r.hmaster_0_0_RNI6JC8R9[0]\ : OR2B - port map(A => \un315_ioen_NE\, B => un271_ioen_NE, Y => - \hmbsel_2[0]\); - - \r.hmasterd_0_RNI6NKH[1]\ : NOR2 - port map(A => hwdata_0(14), B => \hmasterd_0[1]\, Y => - N_4718); - - \r.hmaster_0_0_RNIBSHNE2[0]\ : NOR3A - port map(A => un51_ioen_NE_10_1, B => \haddr[21]\, C => - \haddr[20]\, Y => un51_ioen_NE_10_4); - - \r.hmasterd_RNIPK4E[1]\ : MX2 - port map(A => hwdata(1), B => hwdata_0(1), S => - \hmasterd[1]\, Y => N_6573); - - \r.hslave_0_0_RNIS6KC[0]\ : OR3B - port map(A => \hslave_0[0]\, B => hrdata_4_18, C => N_650, - Y => N_580); - - \r.hmasterd_0_RNIF4VF1[0]\ : OR2A - port map(A => hwdata(15), B => N_6550, Y => hwdata_m_8); - - \r.cfgsel_RNI0NABBC\ : MX2 - port map(A => cfgsel, B => un2_ioarea, S => \iosn_1[93]\, Y - => N_5557); - - \r.hslave_0_0_RNI2T0G5[0]\ : MX2C - port map(A => hrdata_1(12), B => hrdata_2_12, S => - \hslave_0[0]\, Y => N_6347); - - \r.hmaster_0_0_RNI76CA71[0]\ : NOR2B - port map(A => \haddr[22]\, B => \haddr[23]\, Y => - un2_ioarea_5); - - \r.haddr_RNIT9C4[5]\ : OR2B - port map(A => \haddr[5]\, B => \haddr_3[4]\, Y => N_6474); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity Clk_divider is - - port( reset_i_0_1 : in std_logic; - clk49_152MHz_c : in std_logic; - reset_i_0_0 : in std_logic; - clk49_152MHz_c_0 : in std_logic; - clk_div_0 : out std_logic; - clk_div_1 : out std_logic; - clk_div_2 : out std_logic; - clk_int : out std_logic; - clk_div_3 : out std_logic - ); - -end Clk_divider; - -architecture DEF_ARCH of Clk_divider is - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component BUFF - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal clk_int_net_1, N_157, \cpt1[1]_net_1\, - \cpt1[0]_net_1\, N_149, \cpt1[3]_net_1\, - \DWACT_FINC_E[0]\, N_126, \cpt1[8]_net_1\, - \DWACT_FINC_E[4]\, N_111, \DWACT_FINC_E[7]\, - \DWACT_FINC_E[6]\, un1_cpt1_28, un1_cpt1_20, un1_cpt1_19, - un1_cpt1_26, un1_cpt1_27, un1_cpt1_18, un1_cpt1_17, - un1_cpt1_23, un1_cpt1_12, un1_cpt1_11, un1_cpt1_22, - un1_cpt1_2, un1_cpt1_1, un1_cpt1_15, un1_cpt1_14, - \cpt1[24]_net_1\, \cpt1[21]_net_1\, \cpt1[6]_net_1\, - \cpt1[4]_net_1\, un1_cpt1_10, un1_cpt1_8, - \cpt1[22]_net_1\, \cpt1[19]_net_1\, un1_cpt1_6, - \cpt1[10]_net_1\, \cpt1[7]_net_1\, un1_cpt1_4, - \cpt1[29]_net_1\, \cpt1[26]_net_1\, \cpt1[11]_net_1\, - \cpt1[31]_net_1\, \cpt1[27]_net_1\, \cpt1[15]_net_1\, - \cpt1[18]_net_1\, \cpt1[9]_net_1\, \cpt1[12]_net_1\, - \cpt1[2]_net_1\, \cpt1[25]_net_1\, \cpt1[28]_net_1\, - \cpt1[13]_net_1\, \cpt1[16]_net_1\, \cpt1[5]_net_1\, - \cpt1[30]_net_1\, \cpt1[20]_net_1\, \cpt1[23]_net_1\, - \cpt1[14]_net_1\, \cpt1[17]_net_1\, \clk_int_RNO\, - \cpt1_3[6]\, I_31_6, \cpt1_3[5]\, I_24_8, \cpt1_3[4]\, - I_20_7, \cpt1_3[3]\, I_13_11, \cpt1_3[0]\, \cpt1_3[8]\, - I_45_3, I_5_7, I_9_7, I_38_4, I_52_3, I_56_3, I_66_3, - I_73_2, I_77_2, I_84_2, I_91_2, I_98_2, I_105_2, I_115_2, - I_122_2, I_129_2, I_136_2, I_143_2, I_156_2, I_166_2, - I_173_2, I_186_2, I_196_2, I_203_2, I_210_2, I_217_0, - I_224_0, N_4, \DWACT_FINC_E[24]\, \DWACT_FINC_E[23]\, - \DWACT_FINC_E[27]\, \DWACT_FINC_E[26]\, N_9, N_14, - \DWACT_FINC_E[25]\, N_19, \DWACT_FINC_E[29]\, - \DWACT_FINC_E[30]\, N_24, \DWACT_FINC_E[15]\, - \DWACT_FINC_E[17]\, \DWACT_FINC_E[22]\, N_31, - \DWACT_FINC_E[21]\, \DWACT_FINC_E[9]\, \DWACT_FINC_E[12]\, - \DWACT_FINC_E[20]\, N_40, \DWACT_FINC_E[13]\, - \DWACT_FINC_E[19]\, N_45, \DWACT_FINC_E[18]\, N_52, - \DWACT_FINC_E[33]\, \DWACT_FINC_E[34]\, \DWACT_FINC_E[2]\, - \DWACT_FINC_E[5]\, N_61, \DWACT_FINC_E[28]\, - \DWACT_FINC_E[16]\, N_66, N_71, \DWACT_FINC_E[14]\, N_76, - N_81, \DWACT_FINC_E[10]\, N_88, \DWACT_FINC_E[11]\, N_93, - N_98, N_103, \DWACT_FINC_E[8]\, N_108, N_116, N_123, - \DWACT_FINC_E[3]\, N_131, N_136, N_141, \DWACT_FINC_E[1]\, - N_146, N_154, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - clk_int <= clk_int_net_1; - - un3_cpt1_I_9 : XOR2 - port map(A => N_157, B => \cpt1[2]_net_1\, Y => I_9_7); - - un3_cpt1_I_220 : AND2 - port map(A => \DWACT_FINC_E[26]\, B => \cpt1[30]_net_1\, Y - => \DWACT_FINC_E[27]\); - - \cpt1[31]\ : DFN1C1 - port map(D => I_224_0, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[31]_net_1\); - - un3_cpt1_I_213 : AND3 - port map(A => \cpt1[27]_net_1\, B => \cpt1[28]_net_1\, C - => \cpt1[29]_net_1\, Y => \DWACT_FINC_E[26]\); - - un3_cpt1_I_128 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[14]\, Y => N_71); - - \cpt1[11]\ : DFN1C1 - port map(D => I_66_3, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[11]_net_1\); - - \cpt1[23]\ : DFN1C1 - port map(D => I_156_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[23]_net_1\); - - un3_cpt1_I_136 : XOR2 - port map(A => N_66, B => \cpt1[21]_net_1\, Y => I_136_2); - - \cpt1[7]\ : DFN1C1 - port map(D => I_38_4, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[7]_net_1\); - - un3_cpt1_I_216 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[26]\, Y => N_9); - - un3_cpt1_I_111 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\); - - \cpt1[0]\ : DFN1C1 - port map(D => \cpt1_3[0]\, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[0]_net_1\); - - \cpt1_RNISQL23[7]\ : NOR3C - port map(A => un1_cpt1_18, B => un1_cpt1_17, C => - un1_cpt1_23, Y => un1_cpt1_27); - - un3_cpt1_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \cpt1[9]_net_1\, C - => \cpt1[10]_net_1\, Y => N_116); - - un3_cpt1_I_66 : XOR2 - port map(A => N_116, B => \cpt1[11]_net_1\, Y => I_66_3); - - un3_cpt1_I_146 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \cpt1[21]_net_1\, C - => \cpt1[22]_net_1\, Y => \DWACT_FINC_E[33]\); - - \cpt1_RNO[3]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_13_11, - Y => \cpt1_3[3]\); - - un3_cpt1_I_202 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \cpt1[27]_net_1\, Y => N_19); - - un3_cpt1_I_139 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \cpt1[21]_net_1\, Y - => \DWACT_FINC_E[16]\); - - \cpt1[29]\ : DFN1C1 - port map(D => I_210_2, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[29]_net_1\); - - clk_int_RNO : AX1C - port map(A => un1_cpt1_27, B => un1_cpt1_28, C => - clk_int_net_1, Y => \clk_int_RNO\); - - \cpt1[13]\ : DFN1C1 - port map(D => I_77_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[13]_net_1\); - - un3_cpt1_I_16 : AND3 - port map(A => \cpt1[0]_net_1\, B => \cpt1[1]_net_1\, C => - \cpt1[2]_net_1\, Y => \DWACT_FINC_E[0]\); - - un3_cpt1_I_149 : AND3 - port map(A => \cpt1[0]_net_1\, B => \cpt1[1]_net_1\, C => - \cpt1[2]_net_1\, Y => \DWACT_FINC_E[34]\); - - \cpt1_RNI57UF[13]\ : NOR2 - port map(A => \cpt1[13]_net_1\, B => \cpt1[16]_net_1\, Y - => un1_cpt1_6); - - un3_cpt1_I_27 : AND2 - port map(A => \cpt1[3]_net_1\, B => \cpt1[4]_net_1\, Y => - \DWACT_FINC_E[1]\); - - \cpt1[5]\ : DFN1C1 - port map(D => \cpt1_3[5]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[5]_net_1\); - - \cpt1[19]\ : DFN1C1 - port map(D => I_122_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[19]_net_1\); - - un3_cpt1_I_20 : XOR2 - port map(A => N_149, B => \cpt1[4]_net_1\, Y => I_20_7); - - un3_cpt1_I_114 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[12]\, Y => N_81); - - \cpt1_RNIPSTO[21]\ : NOR3A - port map(A => un1_cpt1_14, B => \cpt1[24]_net_1\, C => - \cpt1[21]_net_1\, Y => un1_cpt1_22); - - un3_cpt1_I_8 : NOR2B - port map(A => \cpt1[1]_net_1\, B => \cpt1[0]_net_1\, Y => - N_157); - - un3_cpt1_I_72 : NOR2B - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y - => N_111); - - un3_cpt1_I_152 : AND3 - port map(A => \DWACT_FINC_E[34]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[29]\); - - un3_cpt1_I_162 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - Y => \DWACT_FINC_E[18]\); - - clk_int_inferred_clock_RNIIC66_0 : BUFF - port map(A => clk_int_net_1, Y => clk_div_3); - - un3_cpt1_I_155 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[33]\, Y => N_52); - - un3_cpt1_I_165 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[18]\, Y => N_45); - - un3_cpt1_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \cpt1[3]_net_1\, C - => \cpt1[4]_net_1\, Y => N_146); - - GND_i : GND - port map(Y => \GND\); - - un3_cpt1_I_115 : XOR2 - port map(A => N_81, B => \cpt1[18]_net_1\, Y => I_115_2); - - un3_cpt1_I_52 : XOR2 - port map(A => N_126, B => \cpt1[9]_net_1\, Y => I_52_3); - - un3_cpt1_I_203 : XOR2 - port map(A => N_19, B => \cpt1[28]_net_1\, Y => I_203_2); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - un3_cpt1_I_206 : AND2 - port map(A => \cpt1[27]_net_1\, B => \cpt1[28]_net_1\, Y - => \DWACT_FINC_E[25]\); - - un3_cpt1_I_101 : AND2 - port map(A => \cpt1[15]_net_1\, B => \cpt1[16]_net_1\, Y - => \DWACT_FINC_E[11]\); - - un3_cpt1_I_24 : XOR2 - port map(A => N_146, B => \cpt1[5]_net_1\, Y => I_24_8); - - \cpt1_RNI4G12[2]\ : NOR2A - port map(A => \cpt1[8]_net_1\, B => \cpt1[2]_net_1\, Y => - un1_cpt1_10); - - un3_cpt1_I_31 : XOR2 - port map(A => N_141, B => \cpt1[6]_net_1\, Y => I_31_6); - - \cpt1[26]\ : DFN1C1 - port map(D => I_186_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[26]_net_1\); - - un3_cpt1_I_129 : XOR2 - port map(A => N_71, B => \cpt1[20]_net_1\, Y => I_129_2); - - \cpt1[4]\ : DFN1C1 - port map(D => \cpt1_3[4]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[4]_net_1\); - - un3_cpt1_I_5 : XOR2 - port map(A => \cpt1[0]_net_1\, B => \cpt1[1]_net_1\, Y => - I_5_7); - - clk_int_inferred_clock_RNIIC66_2 : BUFF - port map(A => clk_int_net_1, Y => clk_div_1); - - \cpt1[25]\ : DFN1C1 - port map(D => I_173_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[25]_net_1\); - - un3_cpt1_I_45 : XOR2 - port map(A => N_131, B => \cpt1[8]_net_1\, Y => I_45_3); - - \cpt1[9]\ : DFN1C1 - port map(D => I_52_3, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[9]_net_1\); - - \cpt1_RNI7FUF[14]\ : NOR2 - port map(A => \cpt1[14]_net_1\, B => \cpt1[17]_net_1\, Y - => un1_cpt1_1); - - \cpt1_RNI9NUF[15]\ : NOR2 - port map(A => \cpt1[15]_net_1\, B => \cpt1[18]_net_1\, Y - => un1_cpt1_12); - - un3_cpt1_I_91 : XOR2 - port map(A => N_98, B => \cpt1[15]_net_1\, Y => I_91_2); - - un3_cpt1_I_59 : AND3 - port map(A => \cpt1[6]_net_1\, B => \cpt1[7]_net_1\, C => - \cpt1[8]_net_1\, Y => \DWACT_FINC_E[5]\); - - \cpt1[16]\ : DFN1C1 - port map(D => I_98_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[16]_net_1\); - - un3_cpt1_I_41 : AND2 - port map(A => \cpt1[6]_net_1\, B => \cpt1[7]_net_1\, Y => - \DWACT_FINC_E[3]\); - - \cpt1[24]\ : DFN1C1 - port map(D => I_166_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[24]_net_1\); - - VCC_i : VCC - port map(Y => \VCC\); - - un3_cpt1_I_182 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[30]\); - - un3_cpt1_I_196 : XOR2 - port map(A => N_24, B => \cpt1[27]_net_1\, Y => I_196_2); - - \cpt1[3]\ : DFN1C1 - port map(D => \cpt1_3[3]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[3]_net_1\); - - \cpt1_RNIJ6TV[22]\ : NOR3A - port map(A => un1_cpt1_8, B => \cpt1[22]_net_1\, C => - \cpt1[19]_net_1\, Y => un1_cpt1_19); - - un3_cpt1_I_185 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[21]\, Y => N_31); - - un3_cpt1_I_172 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[19]\, Y => N_40); - - \cpt1[15]\ : DFN1C1 - port map(D => I_91_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[15]_net_1\); - - un3_cpt1_I_199 : AND2 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - Y => \DWACT_FINC_E[24]\); - - un3_cpt1_I_13 : XOR2 - port map(A => N_154, B => \cpt1[3]_net_1\, Y => I_13_11); - - un3_cpt1_I_104 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \DWACT_FINC_E[11]\, Y => N_88); - - clk_int_inferred_clock_RNIIC66 : BUFF - port map(A => clk_int_net_1, Y => clk_div_0); - - \cpt1[14]\ : DFN1C1 - port map(D => I_84_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[14]_net_1\); - - un3_cpt1_I_38 : XOR2 - port map(A => N_136, B => \cpt1[7]_net_1\, Y => I_38_4); - - un3_cpt1_I_210 : XOR2 - port map(A => N_14, B => \cpt1[29]_net_1\, Y => I_210_2); - - \cpt1[1]\ : DFN1C1 - port map(D => I_5_7, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[1]_net_1\); - - \clk_int\ : DFN1C1 - port map(D => \clk_int_RNO\, CLK => clk49_152MHz_c_0, CLR - => reset_i_0_0, Q => clk_int_net_1); - - un3_cpt1_I_173 : XOR2 - port map(A => N_40, B => \cpt1[25]_net_1\, Y => I_173_2); - - un3_cpt1_I_118 : AND3 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, C - => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[13]\); - - \cpt1_RNIM509[27]\ : NOR2A - port map(A => \cpt1[3]_net_1\, B => \cpt1[27]_net_1\, Y => - un1_cpt1_14); - - \cpt1_RNI1FTF[20]\ : NOR2 - port map(A => \cpt1[20]_net_1\, B => \cpt1[23]_net_1\, Y - => un1_cpt1_2); - - un3_cpt1_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \cpt1[6]_net_1\, Y => N_136); - - un3_cpt1_I_105 : XOR2 - port map(A => N_88, B => \cpt1[17]_net_1\, Y => I_105_2); - - un3_cpt1_I_217 : XOR2 - port map(A => N_9, B => \cpt1[30]_net_1\, Y => I_217_0); - - \cpt1_RNIV8UO[26]\ : NOR3A - port map(A => un1_cpt1_4, B => \cpt1[29]_net_1\, C => - \cpt1[26]_net_1\, Y => un1_cpt1_17); - - un3_cpt1_I_98 : XOR2 - port map(A => N_93, B => \cpt1[16]_net_1\, Y => I_98_2); - - un3_cpt1_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E[4]\); - - un3_cpt1_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[1]\, C - => \cpt1[5]_net_1\, Y => N_141); - - un3_cpt1_I_132 : AND3 - port map(A => \cpt1[18]_net_1\, B => \cpt1[19]_net_1\, C - => \cpt1[20]_net_1\, Y => \DWACT_FINC_E[15]\); - - \cpt1[22]\ : DFN1C1 - port map(D => I_143_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[22]_net_1\); - - \cpt1_RNO[0]\ : AOI1 - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => - \cpt1[0]_net_1\, Y => \cpt1_3[0]\); - - un3_cpt1_I_135 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[15]\, Y => N_66); - - un3_cpt1_I_97 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[10]\, C - => \cpt1[15]_net_1\, Y => N_93); - - un3_cpt1_I_223 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[27]\, Y => N_4); - - un3_cpt1_I_142 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[16]\, Y => N_61); - - \cpt1_RNIBNUF[25]\ : NOR2 - port map(A => \cpt1[25]_net_1\, B => \cpt1[28]_net_1\, Y - => un1_cpt1_8); - - un3_cpt1_I_121 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \cpt1[18]_net_1\, Y => N_76); - - un3_cpt1_I_90 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[9]\, Y => N_98); - - un3_cpt1_I_143 : XOR2 - port map(A => N_61, B => \cpt1[22]_net_1\, Y => I_143_2); - - \cpt1[12]\ : DFN1C1 - port map(D => I_73_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[12]_net_1\); - - \cpt1_RNO[6]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_31_6, Y - => \cpt1_3[6]\); - - un3_cpt1_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[6]\); - - un3_cpt1_I_34 : AND3 - port map(A => \cpt1[3]_net_1\, B => \cpt1[4]_net_1\, C => - \cpt1[5]_net_1\, Y => \DWACT_FINC_E[2]\); - - un3_cpt1_I_76 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \cpt1[12]_net_1\, Y => N_108); - - GND_i_0 : GND - port map(Y => GND_0); - - \cpt1_RNIMHV8[9]\ : NOR2 - port map(A => \cpt1[9]_net_1\, B => \cpt1[12]_net_1\, Y => - un1_cpt1_11); - - un3_cpt1_I_12 : AND3 - port map(A => \cpt1[0]_net_1\, B => \cpt1[1]_net_1\, C => - \cpt1[2]_net_1\, Y => N_154); - - \cpt1[2]\ : DFN1C1 - port map(D => I_9_7, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[2]_net_1\); - - \cpt1[28]\ : DFN1C1 - port map(D => I_203_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[28]_net_1\); - - \cpt1_RNO[4]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_20_7, Y - => \cpt1_3[4]\); - - un3_cpt1_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \cpt1[8]_net_1\, C - => \cpt1[9]_net_1\, Y => N_123); - - un3_cpt1_I_56 : XOR2 - port map(A => N_123, B => \cpt1[10]_net_1\, Y => I_56_3); - - un3_cpt1_I_156 : XOR2 - port map(A => N_52, B => \cpt1[23]_net_1\, Y => I_156_2); - - un3_cpt1_I_51 : NOR2B - port map(A => \cpt1[8]_net_1\, B => \DWACT_FINC_E[4]\, Y - => N_126); - - un3_cpt1_I_166 : XOR2 - port map(A => N_45, B => \cpt1[24]_net_1\, Y => I_166_2); - - un3_cpt1_I_108 : AND3 - port map(A => \cpt1[15]_net_1\, B => \cpt1[16]_net_1\, C - => \cpt1[17]_net_1\, Y => \DWACT_FINC_E[12]\); - - un3_cpt1_I_94 : AND2 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[9]\, Y - => \DWACT_FINC_E[10]\); - - un3_cpt1_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[3]\, Y => N_131); - - un3_cpt1_I_69 : AND3 - port map(A => \cpt1[9]_net_1\, B => \cpt1[10]_net_1\, C => - \cpt1[11]_net_1\, Y => \DWACT_FINC_E[7]\); - - \cpt1_RNINGTO[7]\ : NOR3A - port map(A => un1_cpt1_6, B => \cpt1[10]_net_1\, C => - \cpt1[7]_net_1\, Y => un1_cpt1_18); - - un3_cpt1_I_159 : AND3 - port map(A => \cpt1[21]_net_1\, B => \cpt1[22]_net_1\, C - => \cpt1[23]_net_1\, Y => \DWACT_FINC_E[17]\); - - \cpt1[18]\ : DFN1C1 - port map(D => I_115_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[18]_net_1\); - - \cpt1[6]\ : DFN1C1 - port map(D => \cpt1_3[6]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[6]_net_1\); - - un3_cpt1_I_169 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \cpt1[24]_net_1\, Y => \DWACT_FINC_E[19]\); - - un3_cpt1_I_224 : XOR2 - port map(A => N_4, B => \cpt1[31]_net_1\, Y => I_224_0); - - un3_cpt1_I_87 : AND3 - port map(A => \cpt1[12]_net_1\, B => \cpt1[13]_net_1\, C - => \cpt1[14]_net_1\, Y => \DWACT_FINC_E[9]\); - - un3_cpt1_I_122 : XOR2 - port map(A => N_76, B => \cpt1[19]_net_1\, Y => I_122_2); - - un3_cpt1_I_209 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[25]\, Y => N_14); - - un3_cpt1_I_19 : NOR2B - port map(A => \cpt1[3]_net_1\, B => \DWACT_FINC_E[0]\, Y - => N_149); - - un3_cpt1_I_125 : AND2 - port map(A => \cpt1[18]_net_1\, B => \cpt1[19]_net_1\, Y - => \DWACT_FINC_E[14]\); - - \cpt1_RNI8034[4]\ : NOR3C - port map(A => \cpt1[6]_net_1\, B => \cpt1[4]_net_1\, C => - un1_cpt1_10, Y => un1_cpt1_20); - - un3_cpt1_I_80 : AND2 - port map(A => \cpt1[12]_net_1\, B => \cpt1[13]_net_1\, Y - => \DWACT_FINC_E[8]\); - - \cpt1_RNIU2UG[31]\ : NOR3 - port map(A => \cpt1[11]_net_1\, B => \cpt1[31]_net_1\, C - => \cpt1[1]_net_1\, Y => un1_cpt1_15); - - \cpt1_RNO[8]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_45_3, Y - => \cpt1_3[8]\); - - \cpt1_RNIJCSL2[4]\ : NOR3C - port map(A => un1_cpt1_20, B => un1_cpt1_19, C => - un1_cpt1_26, Y => un1_cpt1_28); - - un3_cpt1_I_77 : XOR2 - port map(A => N_108, B => \cpt1[13]_net_1\, Y => I_77_2); - - un3_cpt1_I_186 : XOR2 - port map(A => N_31, B => \cpt1[26]_net_1\, Y => I_186_2); - - \cpt1[27]\ : DFN1C1 - port map(D => I_196_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[27]_net_1\); - - un3_cpt1_I_83 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E[8]\, Y => N_103); - - un3_cpt1_I_192 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[22]\, Y => \DWACT_FINC_E[23]\); - - \cpt1_RNII9V8[30]\ : NOR2A - port map(A => \cpt1[5]_net_1\, B => \cpt1[30]_net_1\, Y => - un1_cpt1_4); - - \cpt1[20]\ : DFN1C1 - port map(D => I_129_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[20]_net_1\); - - un3_cpt1_I_176 : AND2 - port map(A => \cpt1[24]_net_1\, B => \cpt1[25]_net_1\, Y - => \DWACT_FINC_E[20]\); - - un3_cpt1_I_195 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[23]\, Y => N_24); - - un3_cpt1_I_189 : AND3 - port map(A => \cpt1[24]_net_1\, B => \cpt1[25]_net_1\, C - => \cpt1[26]_net_1\, Y => \DWACT_FINC_E[22]\); - - un3_cpt1_I_84 : XOR2 - port map(A => N_103, B => \cpt1[14]_net_1\, Y => I_84_2); - - \cpt1_RNIO5SH1[9]\ : NOR3C - port map(A => un1_cpt1_12, B => un1_cpt1_11, C => - un1_cpt1_22, Y => un1_cpt1_26); - - \cpt1_RNO[5]\ : AOI1B - port map(A => un1_cpt1_28, B => un1_cpt1_27, C => I_24_8, Y - => \cpt1_3[5]\); - - \cpt1_RNI61QG1[20]\ : NOR3C - port map(A => un1_cpt1_2, B => un1_cpt1_1, C => un1_cpt1_15, - Y => un1_cpt1_23); - - \cpt1[21]\ : DFN1C1 - port map(D => I_136_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[21]_net_1\); - - \cpt1[17]\ : DFN1C1 - port map(D => I_105_2, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[17]_net_1\); - - clk_int_inferred_clock_RNIIC66_1 : BUFF - port map(A => clk_int_net_1, Y => clk_div_2); - - \cpt1[30]\ : DFN1C1 - port map(D => I_217_0, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[30]_net_1\); - - un3_cpt1_I_179 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[20]\, Y => \DWACT_FINC_E[21]\); - - un3_cpt1_I_73 : XOR2 - port map(A => N_111, B => \cpt1[12]_net_1\, Y => I_73_2); - - \cpt1[10]\ : DFN1C1 - port map(D => I_56_3, CLK => clk49_152MHz_c_0, CLR => - reset_i_0_0, Q => \cpt1[10]_net_1\); - - \cpt1[8]\ : DFN1C1 - port map(D => \cpt1_3[8]\, CLK => clk49_152MHz_c, CLR => - reset_i_0_1, Q => \cpt1[8]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity lfr_time_management is - - port( pirq : out std_logic_vector(13 downto 12); - coarse_time_load : in std_logic_vector(31 downto 0); - next_commutation : in std_logic_vector(31 downto 0); - coarse_time : out std_logic_vector(31 downto 0); - coarse_time_i : out std_logic_vector(0 to 0); - fine_time : out std_logic_vector(16 downto 0); - clk49_152MHz_c_0 : in std_logic; - clk49_152MHz_c : in std_logic; - lclk_c : in std_logic; - soft_tick : in std_logic; - rstn_i : in std_logic; - soft_tick_3 : in std_logic; - soft_tick_2 : in std_logic; - soft_tick_1 : in std_logic; - soft_tick_0 : in std_logic; - rstn : in std_logic - ); - -end lfr_time_management; - -architecture DEF_ARCH of lfr_time_management is - - component XA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AND3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1P1C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XNOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1C1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component Clk_divider - port( reset_i_0_1 : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - reset_i_0_0 : in std_logic := 'U'; - clk49_152MHz_c_0 : in std_logic := 'U'; - clk_div_0 : out std_logic; - clk_div_1 : out std_logic; - clk_div_2 : out std_logic; - clk_int : out std_logic; - clk_div_3 : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - signal reset_i_0_1, reset_i_0_0, \flag_0\, clk_div_0, flag_1, - flag_1_sqmuxa_1, \un1_cpt_1[0]\, N_25, N_24, - \un1_cpt_0[0]\, un1_commutation_timer_3_0, - un1_commutation_timer_3_0_a2_30, s_coarse_time_1_NE, - \commutation_timer[0]_net_1\, s_coarse_time_1_NE_0, - s_coarse_time_1_NE_29, s_coarse_time_1_NE_28, - \DWACT_ADD_CI_0_g_array_4[0]\, - \DWACT_ADD_CI_0_g_array_3[0]\, - \DWACT_ADD_CI_0_pog_array_3[0]\, - \DWACT_ADD_CI_0_g_array_10[0]\, - \DWACT_ADD_CI_0_pog_array_2_1[0]\, - \DWACT_ADD_CI_0_g_array_2[0]\, - \DWACT_ADD_CI_0_pog_array_2[0]\, - \DWACT_ADD_CI_0_g_array_11_1[0]\, - \DWACT_ADD_CI_0_pog_array_1_3[0]\, - \DWACT_ADD_CI_0_g_array_1[0]\, - \DWACT_ADD_CI_0_pog_array_1[0]\, - \DWACT_ADD_CI_0_g_array_11[0]\, - \DWACT_ADD_CI_0_pog_array_1_1[0]\, - \DWACT_ADD_CI_0_g_array_11_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_5[0]\, - \DWACT_ADD_CI_0_g_array_12_2[0]\, - \cpt_next_commutation[6]_net_1\, - \DWACT_ADD_CI_0_g_array_12[0]\, - \cpt_next_commutation[2]_net_1\, - \DWACT_ADD_CI_0_g_array_12_4[0]\, - \cpt_next_commutation[10]_net_1\, \DWACT_ADD_CI_0_TMP[0]\, - \cpt_next_commutation[1]_net_1\, - \DWACT_ADD_CI_0_g_array_12_5[0]\, - \cpt_next_commutation[12]_net_1\, - \DWACT_ADD_CI_0_g_array_12_6[0]\, - \cpt_next_commutation[14]_net_1\, - \DWACT_ADD_CI_0_g_array_12_3[0]\, - \cpt_next_commutation[8]_net_1\, - \DWACT_ADD_CI_0_g_array_12_1[0]\, - \cpt_next_commutation[4]_net_1\, N_68, N_60, - \DWACT_FINC_E[0]\, N_37, \DWACT_FINC_E[4]\, N_22, - \DWACT_FINC_E[7]\, \DWACT_FINC_E[6]\, N_157, - \s_coarse_time[1]_net_1\, \s_coarse_time[0]_net_1\, N_149, - \s_coarse_time[3]_net_1\, \DWACT_FINC_E_0[0]\, N_126, - \s_coarse_time[8]_net_1\, \DWACT_FINC_E_0[4]\, N_111, - \DWACT_FINC_E_0[7]\, \DWACT_FINC_E_0[6]\, - un1_s_coarse_time_3_m_0, s_coarse_time38, - un1_commutation_timer_3_0_a2_25, - un1_commutation_timer_3_0_a2_24, - un1_commutation_timer_3_0_a2_29, - un1_commutation_timer_3_0_a2_21, - un1_commutation_timer_3_0_a2_20, - un1_commutation_timer_3_0_a2_27, - un1_commutation_timer_3_0_a2_13, - un1_commutation_timer_3_0_a2_12, - un1_commutation_timer_3_0_a2_23, - un1_commutation_timer_3_0_a2_5, - un1_commutation_timer_3_0_a2_4, - un1_commutation_timer_3_0_a2_19, - un1_commutation_timer_3_0_a2_1, - un1_commutation_timer_3_0_a2_0, - un1_commutation_timer_3_0_a2_17, N_139_i_i_0, N_138_i_i_0, - un1_commutation_timer_3_0_a2_15, N_131_i_i_0, N_130_i_i_0, - un1_commutation_timer_3_0_a2_11, N_127_i_i_0, N_126_i_i_0, - un1_commutation_timer_3_0_a2_9, N_123_i_i_0, N_122_i_i_0, - un1_commutation_timer_3_0_a2_7, N_115_i_i_0, N_114_i_i_0, - un1_commutation_timer_3_0_a2_3, - \p_next_commutation[30]_net_1\, N_141_i_i_0, - \p_next_commutation[26]_net_1\, N_137_i_i_0, - \p_next_commutation[24]_net_1\, N_135_i_i_0, - \p_next_commutation[22]_net_1\, N_133_i_i_0, - \p_next_commutation[18]_net_1\, N_129_i_i_0, - \p_next_commutation[14]_net_1\, N_125_i_i_0, - \p_next_commutation[10]_net_1\, N_121_i_i_0, - \p_next_commutation[8]_net_1\, N_119_i_i_0, - \p_next_commutation[6]_net_1\, N_117_i_i_0, - \p_next_commutation[2]_net_1\, N_113_i_i_0, - \p_next_commutation[0]_net_1\, N_111_i_i_0, - secondary_cpt_c12_m6_0_a2_5, \secondary_cpt[10]_net_1\, - \secondary_cpt[9]_net_1\, secondary_cpt_c12_m6_0_a2_3, - secondary_cpt_c12_m6_0_a2_4, \secondary_cpt[6]_net_1\, - \secondary_cpt[12]_net_1\, secondary_cpt_c12_m6_0_a2_1, - \secondary_cpt[11]_net_1\, s_coarse_time38lto5_1, - \secondary_cpt[7]_net_1\, \secondary_cpt[8]_net_1\, - s_coarse_time_1_NE_21, s_coarse_time_1_NE_20, - s_coarse_time_1_NE_27, s_coarse_time_1_NE_17, - s_coarse_time_1_NE_16, s_coarse_time_1_NE_25, - s_coarse_time_1_NE_13, s_coarse_time_1_NE_12, - s_coarse_time_1_NE_23, s_coarse_time_1_NE_5, - s_coarse_time_1_NE_4, s_coarse_time_1_NE_19, - s_coarse_time_1_29_i, s_coarse_time_1_28_i, - s_coarse_time_1_NE_15, s_coarse_time_1_21_i, - s_coarse_time_1_20_i, s_coarse_time_1_NE_11, - s_coarse_time_1_17_i, s_coarse_time_1_16_i, - s_coarse_time_1_NE_9, s_coarse_time_1_13_i, - s_coarse_time_1_12_i, s_coarse_time_1_NE_7, - s_coarse_time_1_5_i, s_coarse_time_1_4_i, - s_coarse_time_1_NE_3, s_coarse_time_1_1_i, - s_coarse_time_1_0_i, s_coarse_time_1_NE_1, - \latched_next_commutation[30]_net_1\, - \s_coarse_time[30]_net_1\, s_coarse_time_1_31_i, - \latched_next_commutation[26]_net_1\, - \s_coarse_time[26]_net_1\, s_coarse_time_1_27_i, - \latched_next_commutation[24]_net_1\, - \s_coarse_time[24]_net_1\, s_coarse_time_1_25_i, - \latched_next_commutation[22]_net_1\, - \s_coarse_time[22]_net_1\, s_coarse_time_1_23_i, - \latched_next_commutation[18]_net_1\, - \s_coarse_time[18]_net_1\, s_coarse_time_1_19_i, - \latched_next_commutation[14]_net_1\, - \s_coarse_time[14]_net_1\, s_coarse_time_1_15_i, - \latched_next_commutation[10]_net_1\, - \s_coarse_time[10]_net_1\, s_coarse_time_1_11_i, - \latched_next_commutation[8]_net_1\, s_coarse_time_1_9_i, - \latched_next_commutation[6]_net_1\, - \s_coarse_time[6]_net_1\, s_coarse_time_1_7_i, - \latched_next_commutation[2]_net_1\, - \s_coarse_time[2]_net_1\, s_coarse_time_1_3_i, - sirq2_1_sqmuxa_i_a2_15, sirq2_1_sqmuxa_i_a2_13, - \cpt_next_commutation[15]_net_1\, sirq2_1_sqmuxa_i_a2_11, - \cpt_next_commutation[13]_net_1\, sirq2_1_sqmuxa_i_a2_9, - \cpt_next_commutation[11]_net_1\, sirq2_1_sqmuxa_i_a2_7, - \cpt_next_commutation[9]_net_1\, sirq2_1_sqmuxa_i_a2_5, - \cpt_next_commutation[7]_net_1\, sirq2_1_sqmuxa_i_a2_2, - sirq2_1_sqmuxa_i_a2_3, \cpt_next_commutation[5]_net_1\, - \cpt_next_commutation[16]_net_1\, - \cpt_next_commutation[0]_net_1\, - \cpt_next_commutation[3]_net_1\, s_coarse_time38lto16_8, - s_coarse_time38lto16_2, s_coarse_time38lto16_1, - s_coarse_time38lto16_5, s_coarse_time38lto16_7, - s_coarse_time38lto16_4, \secondary_cpt[16]_net_1\, - \secondary_cpt[15]_net_1\, \secondary_cpt[13]_net_1\, - \secondary_cpt[14]_net_1\, \un1_cpt_0_a3_15[0]\, - \un1_cpt_0_a3_9[0]\, \un1_cpt_0_a3_8[0]\, - \un1_cpt_0_a3_12[0]\, \fine_time[8]\, \un1_cpt_0_a3_7[0]\, - \un1_cpt_0_a3_11[0]\, \un1_cpt_0_a3_5[0]\, - \un1_cpt_0_a3_10[0]\, \un1_cpt_0_a3_3[0]\, - \un1_cpt_0_a3_1[0]\, \state[0]_net_1\, \fine_time[0]\, - \fine_time[3]\, \fine_time[1]\, - previous_coarse_time_load_1_NE_29, - previous_coarse_time_load_1_NE_21, - previous_coarse_time_load_1_NE_20, - previous_coarse_time_load_1_NE_27, - previous_coarse_time_load_1_NE_28, - previous_coarse_time_load_1_NE_17, - previous_coarse_time_load_1_NE_16, - previous_coarse_time_load_1_NE_25, - previous_coarse_time_load_1_NE_15, - previous_coarse_time_load_1_NE_14, - previous_coarse_time_load_1_NE_22, - previous_coarse_time_load_1_NE_5, - previous_coarse_time_load_1_NE_4, - previous_coarse_time_load_1_NE_19, - previous_coarse_time_load_1_25_i, - previous_coarse_time_load_1_24_i, - previous_coarse_time_load_1_NE_13, - previous_coarse_time_load_1_21_i, - previous_coarse_time_load_1_20_i, - previous_coarse_time_load_1_NE_11, - previous_coarse_time_load_1_17_i, - previous_coarse_time_load_1_16_i, - previous_coarse_time_load_1_NE_9, - previous_coarse_time_load_1_13_i, - previous_coarse_time_load_1_12_i, - previous_coarse_time_load_1_NE_7, - previous_coarse_time_load_1_5_i, - previous_coarse_time_load_1_4_i, - previous_coarse_time_load_1_NE_3, - previous_coarse_time_load_1_1_i, - previous_coarse_time_load_1_0_i, - previous_coarse_time_load_1_NE_1, - \previous_coarse_time_load[30]_net_1\, - previous_coarse_time_load_1_31_i, - \previous_coarse_time_load[28]_net_1\, - previous_coarse_time_load_1_29_i, - \previous_coarse_time_load[26]_net_1\, - previous_coarse_time_load_1_27_i, - \previous_coarse_time_load[22]_net_1\, - previous_coarse_time_load_1_23_i, - \previous_coarse_time_load[18]_net_1\, - previous_coarse_time_load_1_19_i, - \previous_coarse_time_load[14]_net_1\, - previous_coarse_time_load_1_15_i, - \previous_coarse_time_load[10]_net_1\, - previous_coarse_time_load_1_11_i, - \previous_coarse_time_load[8]_net_1\, - previous_coarse_time_load_1_9_i, - \previous_coarse_time_load[6]_net_1\, - previous_coarse_time_load_1_7_i, - \previous_coarse_time_load[2]_net_1\, - previous_coarse_time_load_1_3_i, flag_1_sqmuxa_i_o3_14, - flag_1_sqmuxa_i_o3_6, flag_1_sqmuxa_i_o3_5, - flag_1_sqmuxa_i_o3_12, flag_1_sqmuxa_i_o3_13, - flag_1_sqmuxa_i_o3_2, flag_1_sqmuxa_i_o3_1, - flag_1_sqmuxa_i_o3_10, flag_1_sqmuxa_i_o3_8, - \fine_time[12]\, flag_1_sqmuxa_i_o3_4, \fine_time[10]\, - \fine_time[7]\, \fine_time[16]\, \fine_time[11]\, - \fine_time[9]\, \fine_time[4]\, \fine_time[6]\, - \fine_time[13]\, \fine_time[2]\, \fine_time[5]\, - \fine_time[14]\, \fine_time[15]\, s_coarse_time38lto5_0, - \secondary_cpt[2]_net_1\, \secondary_cpt[3]_net_1\, - s_coarse_time38lt16, s_coarse_time38lto1, N_243, - un1_p_clk_div, \s_coarse_time_i_m[31]\, - \s_coarse_time[31]_net_1\, secondary_cpt_c12, - secondary_cpt_c3, \secondary_cpt[5]_net_1\, - \secondary_cpt[4]_net_1\, \p_clk_div\, reset_i_0, - un1_soft_tick_44_i, \s_coarse_time_4[31]\, un1_resetn_2_i, - \cpt_5[1]\, I_5_9, \cpt_5[16]\, I_98_4, - \s_coarse_time_10_iv[31]\, secondary_cpt_c2, - \secondary_cpt[0]_net_1\, \secondary_cpt[1]_net_1\, - secondary_cpt_c4, secondary_cpt_c6, secondary_cpt_c8, - secondary_cpt_c10, secondary_cpt_c14, I_224_1, - secondary_cpt_n1, \secondary_cpt_RNO[0]_net_1\, - secondary_cpt_n2, secondary_cpt_n3, secondary_cpt_n4, - secondary_cpt_n5, secondary_cpt_n6, secondary_cpt_n7, - secondary_cpt_n8, secondary_cpt_n9, secondary_cpt_n10, - secondary_cpt_n11, secondary_cpt_n12, secondary_cpt_n13, - secondary_cpt_n14, secondary_cpt_n15, secondary_cpt_n16, - \previous_coarse_time_load[31]_net_1\, - \latched_next_commutation[31]_net_1\, un1_soft_tick_16_i, - \s_coarse_time_4[30]\, un1_resetn_7_i, - \s_coarse_time_7[30]\, I_217_1, un1_soft_tick_29_i, - \s_coarse_time_4[29]\, un1_resetn_11_i, - \s_coarse_time_7[29]\, \s_coarse_time[29]_net_1\, I_210_3, - \previous_coarse_time_load[29]_net_1\, - \latched_next_commutation[29]_net_1\, un1_soft_tick_15_i, - \s_coarse_time_4[28]\, un1_resetn_15_i, - \s_coarse_time_7[28]\, \s_coarse_time[28]_net_1\, I_203_3, - \latched_next_commutation[28]_net_1\, un1_soft_tick_21_i, - \s_coarse_time_4[27]\, un1_resetn_20_i, - \s_coarse_time_7[27]\, \s_coarse_time[27]_net_1\, I_196_3, - \previous_coarse_time_load[27]_net_1\, - \latched_next_commutation[27]_net_1\, un1_soft_tick_20_i, - \s_coarse_time_4[26]\, un1_resetn_8_i, - \s_coarse_time_7[26]\, I_186_3, un1_soft_tick_31_i, - \s_coarse_time_4[25]\, un1_resetn_6_i, - \s_coarse_time_7[25]\, \s_coarse_time[25]_net_1\, I_173_3, - \previous_coarse_time_load[25]_net_1\, - \latched_next_commutation[25]_net_1\, un1_soft_tick_9_i, - \s_coarse_time_4[24]\, un1_resetn_19_i, - \s_coarse_time_7[24]\, I_166_3, - \previous_coarse_time_load[24]_net_1\, un1_soft_tick_2_i, - \s_coarse_time_4[23]\, un1_resetn_16_i, - \s_coarse_time_7[23]\, \s_coarse_time[23]_net_1\, I_156_3, - \previous_coarse_time_load[23]_net_1\, un1_soft_tick_24_i, - \s_coarse_time_4[22]\, un1_resetn_5_i, - \s_coarse_time_7[22]\, I_143_3, un1_soft_tick_28_i, - \s_coarse_time_4[21]\, un1_resetn_10_i, - \s_coarse_time_7[21]\, \s_coarse_time[21]_net_1\, I_136_3, - \previous_coarse_time_load[21]_net_1\, - \previous_coarse_time_load[20]_net_1\, un1_soft_tick_1_i, - \s_coarse_time_4[19]\, un1_resetn_12_i, - \s_coarse_time_7[19]\, \s_coarse_time[19]_net_1\, I_122_3, - \previous_coarse_time_load[19]_net_1\, - \latched_next_commutation[19]_net_1\, un1_soft_tick_27_i, - \s_coarse_time_4[18]\, un1_resetn_4_i, - \s_coarse_time_7[18]\, I_115_3, un1_soft_tick_26_i, - \s_coarse_time_4[17]\, un1_resetn_14_i, - \s_coarse_time_7[17]\, \s_coarse_time[17]_net_1\, I_105_3, - \previous_coarse_time_load[17]_net_1\, - \latched_next_commutation[17]_net_1\, un1_soft_tick_17_i, - \s_coarse_time_4[16]\, un1_resetn_27_i, - \s_coarse_time_7[16]\, \s_coarse_time[16]_net_1\, I_98_3, - \previous_coarse_time_load[16]_net_1\, - \latched_next_commutation[16]_net_1\, un1_soft_tick_3_i, - \s_coarse_time_4[15]\, un1_resetn_24_i, - \s_coarse_time_7[15]\, \s_coarse_time[15]_net_1\, I_91_3, - \previous_coarse_time_load[15]_net_1\, - \latched_next_commutation[15]_net_1\, un1_soft_tick_18_i, - \s_coarse_time_4[14]\, un1_resetn_3_i, - \s_coarse_time_7[14]\, I_84_3, \flag\, un1_soft_tick_12_i, - \s_coarse_time_4[13]\, un1_resetn_18_i, - \s_coarse_time_7[13]\, \s_coarse_time[13]_net_1\, I_77_3, - \previous_coarse_time_load[13]_net_1\, - \latched_next_commutation[13]_net_1\, un1_soft_tick_13_i, - \s_coarse_time_4[12]\, un1_resetn_25_i, - \s_coarse_time_7[12]\, \s_coarse_time[12]_net_1\, I_73_3, - \previous_coarse_time_load[12]_net_1\, - \latched_next_commutation[12]_net_1\, un1_soft_tick_7_i, - \s_coarse_time_4[11]\, un1_resetn_28_i, - \s_coarse_time_7[11]\, \s_coarse_time[11]_net_1\, I_66_5, - \previous_coarse_time_load[11]_net_1\, - \latched_next_commutation[11]_net_1\, un1_soft_tick_22_i, - \s_coarse_time_4[10]\, un1_resetn_9_i, - \s_coarse_time_7[10]\, I_56_5, un1_soft_tick_30_i, - \s_coarse_time_4[9]\, un1_resetn_22_i, - \s_coarse_time_7[9]\, \s_coarse_time[9]_net_1\, I_52_4, - \previous_coarse_time_load[9]_net_1\, - \latched_next_commutation[9]_net_1\, un1_soft_tick_i, - \s_coarse_time_4[8]\, un1_resetn_21_i, - \s_coarse_time_7[8]\, I_45_4, un1_soft_tick_11_i, - \s_coarse_time_4[7]\, un1_resetn_32_i, - \s_coarse_time_7[7]\, \s_coarse_time[7]_net_1\, I_38_5, - \previous_coarse_time_load[7]_net_1\, - \latched_next_commutation[7]_net_1\, un1_soft_tick_10_i, - \s_coarse_time_4[6]\, un1_resetn_13_i, - \s_coarse_time_7[6]\, I_31_7, un1_soft_tick_4_i, - \s_coarse_time_4[5]\, un1_resetn_26_i, - \s_coarse_time_7[5]\, \s_coarse_time[5]_net_1\, I_24_9, - \previous_coarse_time_load[5]_net_1\, - \latched_next_commutation[5]_net_1\, un1_soft_tick_5_i, - \s_coarse_time_4[4]\, un1_resetn_17_i, - \s_coarse_time_7[4]\, \s_coarse_time[4]_net_1\, I_20_8, - \previous_coarse_time_load[4]_net_1\, - \latched_next_commutation[4]_net_1\, un1_soft_tick_6_i, - \s_coarse_time_4[3]\, un1_resetn_31_i, - \s_coarse_time_7[3]\, I_13_12, - \previous_coarse_time_load[3]_net_1\, - \latched_next_commutation[3]_net_1\, un1_soft_tick_14_i, - \s_coarse_time_4[2]\, un1_resetn_30_i, - \s_coarse_time_7[2]\, I_9_8, un1_soft_tick_19_i, - \s_coarse_time_4[1]\, un1_resetn_33_i, - \s_coarse_time_7[1]\, I_5_8, - \previous_coarse_time_load[1]_net_1\, - \latched_next_commutation[1]_net_1\, un1_soft_tick_25_i, - \s_coarse_time_4[0]\, un1_resetn_29_i, - \s_coarse_time_7[0]\, - \previous_coarse_time_load[0]_net_1\, - \latched_next_commutation[0]_net_1\, - commutation_timer_0_sqmuxa_1, N_146, N_147, N_148, - N_149_0, N_150, N_151, N_152, N_153, N_154, N_155, N_156, - N_157_0, N_158, N_159, N_160, N_161, N_162, N_163, N_164, - N_165, N_166, N_167, N_168, N_170, N_171, N_172, N_173, - N_174, N_175, N_176, \commutation_timer_RNI3EI8[0]_net_1\, - N_6, un1_commutation_timer_3, N_9, I_70, N_11, - \DWACT_ADD_CI_0_partial_sum[0]\, N_77, - \p_next_commutation[1]_net_1\, - \p_next_commutation[3]_net_1\, - \p_next_commutation[4]_net_1\, - \p_next_commutation[5]_net_1\, - \p_next_commutation[7]_net_1\, - \p_next_commutation[9]_net_1\, - \p_next_commutation[11]_net_1\, - \p_next_commutation[12]_net_1\, - \p_next_commutation[13]_net_1\, - \p_next_commutation[15]_net_1\, - \p_next_commutation[16]_net_1\, - \p_next_commutation[17]_net_1\, - \p_next_commutation[19]_net_1\, - \p_next_commutation[20]_net_1\, - \p_next_commutation[21]_net_1\, - \p_next_commutation[23]_net_1\, - \p_next_commutation[25]_net_1\, - \p_next_commutation[27]_net_1\, - \p_next_commutation[28]_net_1\, - \p_next_commutation[29]_net_1\, - \p_next_commutation[31]_net_1\, N_169, - \s_coarse_time[20]_net_1\, - \latched_next_commutation[20]_net_1\, - \latched_next_commutation[21]_net_1\, - \latched_next_commutation[23]_net_1\, N_7, N_5, - \un1_cpt[0]\, N_177, \s_coarse_time_4[20]\, I_129_3, - \s_coarse_time_7[20]\, un1_resetn_23_i, - un1_soft_tick_23_i, clk_int, clk_div_3, clk_div_2, I_63, - I_68, I_54, I_58, I_60, I_62, I_64, I_66_4, I_69, I_55, - I_56_4, I_57, I_59, I_65, I_67, I_9_9, I_13_13, I_20_9, - I_24_10, I_31_8, I_38_6, I_45_5, I_52_5, I_56_6, I_66_6, - I_73_4, I_77_4, I_84_4, I_91_4, clk_div_1, - \coarse_time[0]_net_1\, N_4, \DWACT_FINC_E[24]\, - \DWACT_FINC_E[23]\, \DWACT_FINC_E[27]\, - \DWACT_FINC_E[26]\, N_9_0, N_14, \DWACT_FINC_E[25]\, N_19, - \DWACT_FINC_E[29]\, \DWACT_FINC_E[30]\, N_24_0, - \DWACT_FINC_E[15]\, \DWACT_FINC_E[17]\, - \DWACT_FINC_E[22]\, N_31, \DWACT_FINC_E[21]\, - \DWACT_FINC_E[9]\, \DWACT_FINC_E[12]\, \DWACT_FINC_E[20]\, - N_40, \DWACT_FINC_E[13]\, \DWACT_FINC_E[19]\, N_45, - \DWACT_FINC_E[18]\, N_52, \DWACT_FINC_E[33]\, - \DWACT_FINC_E[34]\, \DWACT_FINC_E[2]\, \DWACT_FINC_E[5]\, - N_61, \DWACT_FINC_E[28]\, \DWACT_FINC_E[16]\, N_66, N_71, - \DWACT_FINC_E[14]\, N_76, N_81, \DWACT_FINC_E[10]\, N_88, - \DWACT_FINC_E[11]\, N_93, N_98, N_103, \DWACT_FINC_E[8]\, - N_108, N_116, N_123, \DWACT_FINC_E[3]\, N_131, N_136, - N_141, \DWACT_FINC_E[1]\, N_146_0, N_154_0, N_4_0, - \DWACT_FINC_E_0[10]\, \DWACT_FINC_E_0[9]\, N_9_1, N_14_0, - \DWACT_FINC_E_0[8]\, N_19_0, N_27, \DWACT_FINC_E_0[2]\, - \DWACT_FINC_E_0[5]\, N_34, \DWACT_FINC_E_0[3]\, N_42, - N_47, N_52_0, \DWACT_FINC_E_0[1]\, N_57, N_65, - \DWACT_ADD_CI_0_pog_array_2_2[0]\, - \DWACT_ADD_CI_0_pog_array_1_6[0]\, - \DWACT_ADD_CI_0_pog_array_1_4[0]\, - \DWACT_ADD_CI_0_pog_array_1_2[0]\, \GND\, \VCC\, GND_0, - VCC_0 : std_logic; - - for all : Clk_divider - Use entity work.Clk_divider(DEF_ARCH); -begin - - coarse_time(0) <= \coarse_time[0]_net_1\; - fine_time(16) <= \fine_time[16]\; - fine_time(15) <= \fine_time[15]\; - fine_time(14) <= \fine_time[14]\; - fine_time(13) <= \fine_time[13]\; - fine_time(12) <= \fine_time[12]\; - fine_time(11) <= \fine_time[11]\; - fine_time(10) <= \fine_time[10]\; - fine_time(9) <= \fine_time[9]\; - fine_time(8) <= \fine_time[8]\; - fine_time(7) <= \fine_time[7]\; - fine_time(6) <= \fine_time[6]\; - fine_time(5) <= \fine_time[5]\; - fine_time(4) <= \fine_time[4]\; - fine_time(3) <= \fine_time[3]\; - fine_time(2) <= \fine_time[2]\; - fine_time(1) <= \fine_time[1]\; - fine_time(0) <= \fine_time[0]\; - - \p_next_commutation_RNIGF5L[14]\ : XA1A - port map(A => \p_next_commutation[14]_net_1\, B => - next_commutation(14), C => N_125_i_i_0, Y => - un1_commutation_timer_3_0_a2_7); - - un4_s_coarse_time_I_105 : XOR2 - port map(A => N_88, B => \s_coarse_time[17]_net_1\, Y => - I_105_3); - - \coarse_time[4]\ : DFN1C0 - port map(D => \s_coarse_time[4]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(4)); - - un4_s_coarse_time_I_23 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => - \s_coarse_time[3]_net_1\, C => \s_coarse_time[4]_net_1\, - Y => N_146_0); - - \s_coarse_time_RNO[0]\ : AO1B - port map(A => soft_tick_3, B => \s_coarse_time_4[0]\, C => - rstn, Y => un1_resetn_29_i); - - \latched_next_commutation_RNIK6O5[10]\ : XA1A - port map(A => \latched_next_commutation[10]_net_1\, B => - \s_coarse_time[10]_net_1\, C => s_coarse_time_1_11_i, Y - => s_coarse_time_1_NE_5); - - un1_cpt_next_commutation_I_60 : XOR2 - port map(A => \cpt_next_commutation[5]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => I_60); - - \cpt_next_commutation[16]\ : DFN1C0 - port map(D => N_9, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[16]_net_1\); - - \s_coarse_time_RNO_1[3]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[3]\, Y => - un1_soft_tick_6_i); - - sirq1 : DFN1C0 - port map(D => commutation_timer_0_sqmuxa_1, CLK => lclk_c, - CLR => rstn, Q => pirq(12)); - - \latched_next_commutation[11]\ : DFN1E0P0 - port map(D => N_157_0, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[11]_net_1\); - - \previous_coarse_time_load_RNISK4P[20]\ : NOR3C - port map(A => previous_coarse_time_load_1_21_i, B => - previous_coarse_time_load_1_20_i, C => - previous_coarse_time_load_1_NE_11, Y => - previous_coarse_time_load_1_NE_21); - - un4_s_coarse_time_I_176 : AND2 - port map(A => \s_coarse_time[24]_net_1\, B => - \s_coarse_time[25]_net_1\, Y => \DWACT_FINC_E[20]\); - - \cpt_RNI9038[16]\ : NOR3B - port map(A => \fine_time[16]\, B => \fine_time[0]\, C => - \fine_time[11]\, Y => flag_1_sqmuxa_i_o3_8); - - un4_s_coarse_time_I_72 : NOR2B - port map(A => \DWACT_FINC_E_0[7]\, B => \DWACT_FINC_E_0[6]\, - Y => N_111); - - \s_coarse_time_RNO_1[21]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[21]\, Y - => un1_soft_tick_28_i); - - \previous_coarse_time_load[4]\ : DFN1E0C0 - port map(D => coarse_time_load(4), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[4]_net_1\); - - un1_cpt_next_commutation_I_58 : XOR2 - port map(A => \cpt_next_commutation[4]_net_1\, B => - \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_58); - - un1_cpt_next_commutation_I_56 : XOR2 - port map(A => \cpt_next_commutation[11]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_4[0]\, Y => I_56_4); - - \s_coarse_time_RNO_1[23]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[23]\, Y - => un1_soft_tick_2_i); - - un4_s_coarse_time_I_213 : AND3 - port map(A => \s_coarse_time[27]_net_1\, B => - \s_coarse_time[28]_net_1\, C => \s_coarse_time[29]_net_1\, - Y => \DWACT_FINC_E[26]\); - - \s_coarse_time[19]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[19]\, CLK => clk_div_3, PRE - => un1_soft_tick_1_i, CLR => un1_resetn_12_i, Q => - \s_coarse_time[19]_net_1\); - - \secondary_cpt_RNI1V9P1[14]\ : NOR3C - port map(A => \secondary_cpt[13]_net_1\, B => - secondary_cpt_c12, C => \secondary_cpt[14]_net_1\, Y => - secondary_cpt_c14); - - flag_0_RNIF5RG2 : MX2 - port map(A => I_91_3, B => coarse_time_load(15), S => - \flag_0\, Y => \s_coarse_time_4[15]\); - - un9_cpt_I_31 : XOR2 - port map(A => N_52_0, B => \fine_time[6]\, Y => I_31_8); - - un1_cpt_next_commutation_I_75 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_2[0]\, Y => - \DWACT_ADD_CI_0_g_array_3[0]\); - - un4_s_coarse_time_I_185 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[21]\, Y => N_31); - - \secondary_cpt_RNICLEB[11]\ : NOR2B - port map(A => \secondary_cpt[11]_net_1\, B => - s_coarse_time38lto5_1, Y => secondary_cpt_c12_m6_0_a2_3); - - \s_coarse_time_RNO_1[31]\ : AO1B - port map(A => soft_tick_0, B => \s_coarse_time_4[31]\, C - => rstn, Y => un1_resetn_2_i); - - \previous_coarse_time_load_RNIAU45[5]\ : XNOR2 - port map(A => coarse_time_load(5), B => - \previous_coarse_time_load[5]_net_1\, Y => - previous_coarse_time_load_1_5_i); - - \previous_coarse_time_load[11]\ : DFN1E0C0 - port map(D => coarse_time_load(11), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[11]_net_1\); - - \p_next_commutation[24]\ : DFN1E1 - port map(D => next_commutation(24), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[24]_net_1\); - - un9_cpt_I_27 : AND2 - port map(A => \fine_time[3]\, B => \fine_time[4]\, Y => - \DWACT_FINC_E_0[1]\); - - \latched_next_commutation_RNO[8]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(8), Y => N_154); - - \p_next_commutation_RNIP8D5[4]\ : XNOR2 - port map(A => next_commutation(4), B => - \p_next_commutation[4]_net_1\, Y => N_114_i_i_0); - - \s_coarse_time_RNO_1[24]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[24]\, Y - => un1_soft_tick_9_i); - - \s_coarse_time_RNO_0[11]\ : MX2 - port map(A => \s_coarse_time_4[11]\, B => - \s_coarse_time[11]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[11]\); - - un4_s_coarse_time_I_90 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E_0[7]\, - C => \DWACT_FINC_E[9]\, Y => N_98); - - \s_coarse_time_RNO[21]\ : AO1C - port map(A => \s_coarse_time_4[21]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_10_i); - - un4_s_coarse_time_I_20 : XOR2 - port map(A => N_149, B => \s_coarse_time[4]_net_1\, Y => - I_20_8); - - \s_coarse_time_RNO_0[13]\ : MX2 - port map(A => \s_coarse_time_4[13]\, B => - \s_coarse_time[13]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[13]\); - - \cpt_next_commutation[13]\ : DFN1C0 - port map(D => I_59, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[13]_net_1\); - - flag_0_RNIGVE03 : MX2 - port map(A => I_196_3, B => coarse_time_load(27), S => - \flag_0\, Y => \s_coarse_time_4[27]\); - - un4_s_coarse_time_I_165 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[18]\, Y => N_45); - - \latched_next_commutation_RNI0VJB[16]\ : NOR3C - port map(A => s_coarse_time_1_17_i, B => - s_coarse_time_1_16_i, C => s_coarse_time_1_NE_9, Y => - s_coarse_time_1_NE_20); - - \cpt_RNIC6G2[5]\ : NOR2B - port map(A => \fine_time[5]\, B => \fine_time[7]\, Y => - \un1_cpt_0_a3_3[0]\); - - \previous_coarse_time_load[31]\ : DFN1E0P0 - port map(D => coarse_time_load(31), CLK => clk_div_2, PRE - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[31]_net_1\); - - \cpt_RNIP61P[0]\ : NOR3C - port map(A => \un1_cpt_0_a3_9[0]\, B => \un1_cpt_0_a3_8[0]\, - C => \un1_cpt_0_a3_12[0]\, Y => \un1_cpt_0_a3_15[0]\); - - \s_coarse_time_RNO_1[25]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[25]\, Y - => un1_soft_tick_31_i); - - un1_cpt_next_commutation_I_101 : AND2 - port map(A => \cpt_next_commutation[4]_net_1\, B => - \cpt_next_commutation[5]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_1[0]\); - - \previous_coarse_time_load_RNIARLC[28]\ : XA1A - port map(A => \previous_coarse_time_load[28]_net_1\, B => - coarse_time_load(28), C => - previous_coarse_time_load_1_29_i, Y => - previous_coarse_time_load_1_NE_14); - - \p_next_commutation[15]\ : DFN1E1 - port map(D => next_commutation(15), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[15]_net_1\); - - \latched_next_commutation_RNO[20]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(20), - Y => N_166); - - \s_coarse_time_RNO_0[14]\ : MX2 - port map(A => \s_coarse_time_4[14]\, B => - \s_coarse_time[14]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[14]\); - - un9_cpt_I_45 : XOR2 - port map(A => N_42, B => \fine_time[8]\, Y => I_45_5); - - \previous_coarse_time_load_RNI6196[21]\ : XNOR2 - port map(A => coarse_time_load(21), B => - \previous_coarse_time_load[21]_net_1\, Y => - previous_coarse_time_load_1_21_i); - - \previous_coarse_time_load[22]\ : DFN1E0C0 - port map(D => coarse_time_load(22), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[22]_net_1\); - - un4_s_coarse_time_I_98 : XOR2 - port map(A => N_93, B => \s_coarse_time[16]_net_1\, Y => - I_98_3); - - \secondary_cpt[9]\ : DFN1E0C1 - port map(D => secondary_cpt_n9, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[9]_net_1\); - - \previous_coarse_time_load_RNIK1B6[19]\ : XNOR2 - port map(A => coarse_time_load(19), B => - \previous_coarse_time_load[19]_net_1\, Y => - previous_coarse_time_load_1_19_i); - - \p_next_commutation[0]\ : DFN1E1 - port map(D => next_commutation(0), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[0]_net_1\); - - un9_cpt_I_38 : XOR2 - port map(A => N_47, B => \fine_time[7]\, Y => I_38_6); - - \s_coarse_time_RNO_0[15]\ : MX2 - port map(A => \s_coarse_time_4[15]\, B => - \s_coarse_time[15]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[15]\); - - \previous_coarse_time_load_RNI4196[11]\ : XNOR2 - port map(A => coarse_time_load(11), B => - \previous_coarse_time_load[11]_net_1\, Y => - previous_coarse_time_load_1_11_i); - - \latched_next_commutation_RNO[6]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(6), Y => N_152); - - un9_cpt_I_20 : XOR2 - port map(A => N_60, B => \fine_time[4]\, Y => I_20_9); - - \latched_next_commutation_RNO[24]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(24), - Y => N_170); - - \latched_next_commutation[23]\ : DFN1E0P0 - port map(D => N_169, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[23]_net_1\); - - \commutation_timer[0]\ : DFN1C0 - port map(D => N_77, CLK => lclk_c, CLR => rstn, Q => - \commutation_timer[0]_net_1\); - - un4_s_coarse_time_I_8 : NOR2B - port map(A => \s_coarse_time[1]_net_1\, B => - \s_coarse_time[0]_net_1\, Y => N_157); - - un4_s_coarse_time_I_52 : XOR2 - port map(A => N_126, B => \s_coarse_time[9]_net_1\, Y => - I_52_4); - - un4_s_coarse_time_I_199 : AND2 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - Y => \DWACT_FINC_E[24]\); - - \cpt[8]\ : DFN1C1 - port map(D => I_45_5, CLK => clk_div_0, CLR => reset_i_0, Q - => \fine_time[8]\); - - \coarse_time[10]\ : DFN1C0 - port map(D => \s_coarse_time[10]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(10)); - - \secondary_cpt_RNO[5]\ : XOR2 - port map(A => secondary_cpt_c4, B => - \secondary_cpt[5]_net_1\, Y => secondary_cpt_n5); - - \latched_next_commutation_RNI09NR3[10]\ : NOR3C - port map(A => s_coarse_time_1_NE_17, B => - s_coarse_time_1_NE_16, C => s_coarse_time_1_NE_25, Y => - s_coarse_time_1_NE_28); - - \latched_next_commutation[2]\ : DFN1E0P0 - port map(D => N_148, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[2]_net_1\); - - \previous_coarse_time_load_RNIEQHC[30]\ : XA1A - port map(A => \previous_coarse_time_load[30]_net_1\, B => - coarse_time_load(30), C => - previous_coarse_time_load_1_31_i, Y => - previous_coarse_time_load_1_NE_15); - - \previous_coarse_time_load[29]\ : DFN1E0C0 - port map(D => coarse_time_load(29), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[29]_net_1\); - - \s_coarse_time_RNO[25]\ : AO1C - port map(A => \s_coarse_time_4[25]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_6_i); - - \previous_coarse_time_load_RNI4L6P[12]\ : NOR3C - port map(A => previous_coarse_time_load_1_13_i, B => - previous_coarse_time_load_1_12_i, C => - previous_coarse_time_load_1_NE_7, Y => - previous_coarse_time_load_1_NE_19); - - \previous_coarse_time_load_RNIIHA6[27]\ : XNOR2 - port map(A => coarse_time_load(27), B => - \previous_coarse_time_load[27]_net_1\, Y => - previous_coarse_time_load_1_27_i); - - \p_next_commutation[2]\ : DFN1E1 - port map(D => next_commutation(2), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[2]_net_1\); - - \s_coarse_time_RNO[20]\ : AO1C - port map(A => \s_coarse_time_4[20]\, B => soft_tick_3, C - => rstn, Y => un1_resetn_23_i); - - \s_coarse_time_RNO_1[22]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[22]\, Y - => un1_soft_tick_24_i); - - \previous_coarse_time_load_RNI4P86[20]\ : XNOR2 - port map(A => coarse_time_load(20), B => - \previous_coarse_time_load[20]_net_1\, Y => - previous_coarse_time_load_1_20_i); - - \s_coarse_time_RNO[11]\ : AO1C - port map(A => \s_coarse_time_4[11]\, B => soft_tick_2, C - => rstn, Y => un1_resetn_28_i); - - un4_s_coarse_time_I_13 : XOR2 - port map(A => N_154_0, B => \s_coarse_time[3]_net_1\, Y => - I_13_12); - - un4_s_coarse_time_I_192 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[22]\, Y => \DWACT_FINC_E[23]\); - - \s_coarse_time_RNO[1]\ : AO1C - port map(A => \s_coarse_time_4[1]\, B => soft_tick_3, C => - rstn, Y => un1_resetn_33_i); - - un4_s_coarse_time_I_66 : XOR2 - port map(A => N_116, B => \s_coarse_time[11]_net_1\, Y => - I_66_5); - - un4_s_coarse_time_I_84 : XOR2 - port map(A => N_103, B => \s_coarse_time[14]_net_1\, Y => - I_84_3); - - \latched_next_commutation_RNO[26]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(26), - Y => N_172); - - \secondary_cpt_RNIUSF41[14]\ : NOR3C - port map(A => s_coarse_time38lto16_2, B => - s_coarse_time38lto16_1, C => s_coarse_time38lto16_5, Y - => s_coarse_time38lto16_8); - - un9_cpt_I_9 : XOR2 - port map(A => N_68, B => \fine_time[2]\, Y => I_9_9); - - un9_cpt_I_24 : XOR2 - port map(A => N_57, B => \fine_time[5]\, Y => I_24_10); - - \latched_next_commutation[27]\ : DFN1E0P0 - port map(D => N_173, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[27]_net_1\); - - \p_next_commutation[20]\ : DFN1E1 - port map(D => next_commutation(20), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[20]_net_1\); - - \secondary_cpt[12]\ : DFN1E0C1 - port map(D => secondary_cpt_n12, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[12]_net_1\); - - un4_s_coarse_time_I_77 : XOR2 - port map(A => N_108, B => \s_coarse_time[13]_net_1\, Y => - I_77_3); - - \p_next_commutation_RNI06E95[16]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_21, B => - un1_commutation_timer_3_0_a2_20, C => - un1_commutation_timer_3_0_a2_27, Y => - un1_commutation_timer_3_0_a2_29); - - \latched_next_commutation_RNO[5]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(5), Y => N_151); - - \s_coarse_time_RNO_0[12]\ : MX2 - port map(A => \s_coarse_time_4[12]\, B => - \s_coarse_time[12]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[12]\); - - un9_cpt_I_76 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \fine_time[12]\, Y => N_19_0); - - un1_cpt_next_commutation_I_105 : AND2 - port map(A => \cpt_next_commutation[10]_net_1\, B => - \cpt_next_commutation[11]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_4[0]\); - - \s_coarse_time[24]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[24]\, CLK => clk_div_3, PRE - => un1_soft_tick_9_i, CLR => un1_resetn_19_i, Q => - \s_coarse_time[24]_net_1\); - - \latched_next_commutation_RNIB5S2[11]\ : XNOR2 - port map(A => \s_coarse_time[11]_net_1\, B => - \latched_next_commutation[11]_net_1\, Y => - s_coarse_time_1_11_i); - - un1_cpt_next_commutation_I_62 : XOR2 - port map(A => \cpt_next_commutation[6]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_62); - - \coarse_time[23]\ : DFN1C0 - port map(D => \s_coarse_time[23]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(23)); - - \coarse_time[18]\ : DFN1C0 - port map(D => \s_coarse_time[18]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(18)); - - un1_cpt_next_commutation_I_73 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11[0]\, B => - \cpt_next_commutation[6]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_2[0]\); - - \secondary_cpt[11]\ : DFN1E0C1 - port map(D => secondary_cpt_n11, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[11]_net_1\); - - \previous_coarse_time_load_RNI4U9P2[10]\ : NOR3C - port map(A => previous_coarse_time_load_1_NE_17, B => - previous_coarse_time_load_1_NE_16, C => - previous_coarse_time_load_1_NE_25, Y => - previous_coarse_time_load_1_NE_28); - - un1_cpt_next_commutation_I_107 : AND2 - port map(A => \cpt_next_commutation[14]_net_1\, B => - \cpt_next_commutation[15]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_6[0]\); - - \previous_coarse_time_load[21]\ : DFN1E0C0 - port map(D => coarse_time_load(21), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[21]_net_1\); - - \latched_next_commutation_RNIJLS2[15]\ : XNOR2 - port map(A => \s_coarse_time[15]_net_1\, B => - \latched_next_commutation[15]_net_1\, Y => - s_coarse_time_1_15_i); - - \previous_coarse_time_load[9]\ : DFN1E0C0 - port map(D => coarse_time_load(9), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[9]_net_1\); - - \state_RNI65DH8[0]\ : NOR2A - port map(A => \un1_cpt_0[0]\, B => flag_1, Y => - flag_1_sqmuxa_1); - - \secondary_cpt[15]\ : DFN1E0C1 - port map(D => secondary_cpt_n15, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[15]_net_1\); - - \latched_next_commutation[12]\ : DFN1E0P0 - port map(D => N_158, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[12]_net_1\); - - \coarse_time[25]\ : DFN1C0 - port map(D => \s_coarse_time[25]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(25)); - - \s_coarse_time[13]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[13]\, CLK => clk_div_2, PRE - => un1_soft_tick_12_i, CLR => un1_resetn_18_i, Q => - \s_coarse_time[13]_net_1\); - - \s_coarse_time[18]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[18]\, CLK => clk_div_2, PRE - => un1_soft_tick_27_i, CLR => un1_resetn_4_i, Q => - \s_coarse_time[18]_net_1\); - - \secondary_cpt_RNO[9]\ : XOR2 - port map(A => secondary_cpt_c8, B => - \secondary_cpt[9]_net_1\, Y => secondary_cpt_n9); - - \s_coarse_time_RNO[15]\ : AO1C - port map(A => \s_coarse_time_4[15]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_24_i); - - \latched_next_commutation_RNIJDS2[31]\ : XNOR2 - port map(A => \s_coarse_time[31]_net_1\, B => - \latched_next_commutation[31]_net_1\, Y => - s_coarse_time_1_31_i); - - \latched_next_commutation_RNO[2]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(2), Y => N_148); - - un4_s_coarse_time_I_195 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[30]\, - C => \DWACT_FINC_E[23]\, Y => N_24_0); - - \s_coarse_time_RNO[10]\ : AO1C - port map(A => \s_coarse_time_4[10]\, B => soft_tick_2, C - => rstn, Y => un1_resetn_9_i); - - \secondary_cpt_RNO[8]\ : AX1C - port map(A => \secondary_cpt[7]_net_1\, B => - secondary_cpt_c6, C => \secondary_cpt[8]_net_1\, Y => - secondary_cpt_n8); - - \p_next_commutation_RNIOEAA1[12]\ : NOR3C - port map(A => N_123_i_i_0, B => N_122_i_i_0, C => - un1_commutation_timer_3_0_a2_7, Y => - un1_commutation_timer_3_0_a2_19); - - un4_s_coarse_time_I_31 : XOR2 - port map(A => N_141, B => \s_coarse_time[6]_net_1\, Y => - I_31_7); - - \cpt[4]\ : DFN1C1 - port map(D => I_20_9, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[4]\); - - \p_next_commutation_RNIGV4L[30]\ : XA1A - port map(A => \p_next_commutation[30]_net_1\, B => - next_commutation(30), C => N_141_i_i_0, Y => - un1_commutation_timer_3_0_a2_15); - - \cpt[5]\ : DFN1C1 - port map(D => I_24_10, CLK => clk_div_0, CLR => reset_i_0, - Q => \fine_time[5]\); - - flag_RNI02MA2 : MX2 - port map(A => I_66_5, B => coarse_time_load(11), S => - \flag\, Y => \s_coarse_time_4[11]\); - - \p_next_commutation[7]\ : DFN1E1 - port map(D => next_commutation(7), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[7]_net_1\); - - \secondary_cpt_RNIIVNB[3]\ : NOR2B - port map(A => secondary_cpt_c2, B => - \secondary_cpt[3]_net_1\, Y => secondary_cpt_c3); - - \secondary_cpt[14]\ : DFN1E0C1 - port map(D => secondary_cpt_n14, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[14]_net_1\); - - \p_next_commutation_RNI5EJA[29]\ : XNOR2 - port map(A => next_commutation(29), B => - \p_next_commutation[29]_net_1\, Y => N_139_i_i_0); - - \s_coarse_time[7]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[7]\, CLK => clk_div_3, PRE - => un1_soft_tick_11_i, CLR => un1_resetn_32_i, Q => - \s_coarse_time[7]_net_1\); - - \secondary_cpt_RNIIVHK[5]\ : NOR3C - port map(A => \secondary_cpt[5]_net_1\, B => - secondary_cpt_c4, C => \secondary_cpt[6]_net_1\, Y => - secondary_cpt_c6); - - \p_next_commutation_RNION5L[24]\ : XA1A - port map(A => \p_next_commutation[24]_net_1\, B => - next_commutation(24), C => N_135_i_i_0, Y => - un1_commutation_timer_3_0_a2_12); - - un4_s_coarse_time_I_16 : AND3 - port map(A => \s_coarse_time[0]_net_1\, B => - \s_coarse_time[1]_net_1\, C => \s_coarse_time[2]_net_1\, - Y => \DWACT_FINC_E_0[0]\); - - un4_s_coarse_time_I_34 : AND3 - port map(A => \s_coarse_time[3]_net_1\, B => - \s_coarse_time[4]_net_1\, C => \s_coarse_time[5]_net_1\, - Y => \DWACT_FINC_E[2]\); - - un1_cpt_next_commutation_I_100 : AND2 - port map(A => \cpt_next_commutation[6]_net_1\, B => - \cpt_next_commutation[7]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_2[0]\); - - \p_next_commutation_RNI1AJA[19]\ : XNOR2 - port map(A => next_commutation(19), B => - \p_next_commutation[19]_net_1\, Y => N_129_i_i_0); - - flag_RNI9PC92 : MX2 - port map(A => I_56_5, B => coarse_time_load(10), S => - \flag\, Y => \s_coarse_time_4[10]\); - - un1_cpt_next_commutation_I_82 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_1[0]\, B => - \cpt_next_commutation[10]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_4[0]\); - - un4_s_coarse_time_I_104 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[11]\, Y => N_88); - - \p_next_commutation[27]\ : DFN1E1 - port map(D => next_commutation(27), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[27]_net_1\); - - \s_coarse_time_RNO[22]\ : AO1C - port map(A => \s_coarse_time_4[22]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_5_i); - - \secondary_cpt_RNIHVJH[1]\ : OR3C - port map(A => s_coarse_time38lto5_0, B => - s_coarse_time38lto1, C => s_coarse_time38lto5_1, Y => - s_coarse_time38lt16); - - flag_0_RNI68PK2 : MX2 - port map(A => I_115_3, B => coarse_time_load(18), S => - \flag_0\, Y => \s_coarse_time_4[18]\); - - un9_cpt_I_56 : XOR2 - port map(A => N_34, B => \fine_time[10]\, Y => I_56_6); - - un4_s_coarse_time_I_216 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[26]\, Y => N_9_0); - - \s_coarse_time[3]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[3]\, CLK => clk_div_3, PRE - => un1_soft_tick_6_i, CLR => un1_resetn_31_i, Q => - \s_coarse_time[3]_net_1\); - - \latched_next_commutation_RNIN2LA[9]\ : XNOR2 - port map(A => \s_coarse_time[9]_net_1\, B => - \latched_next_commutation[9]_net_1\, Y => - s_coarse_time_1_9_i); - - \p_next_commutation[19]\ : DFN1E1 - port map(D => next_commutation(19), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[19]_net_1\); - - \cpt_RNIVBOC[12]\ : NOR3A - port map(A => flag_1_sqmuxa_i_o3_8, B => \fine_time[3]\, C - => \fine_time[12]\, Y => flag_1_sqmuxa_i_o3_12); - - \previous_coarse_time_load[5]\ : DFN1E0C0 - port map(D => coarse_time_load(5), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[5]_net_1\); - - flag_0_RNIUJ7R2 : MX2 - port map(A => I_156_3, B => coarse_time_load(23), S => - \flag_0\, Y => \s_coarse_time_4[23]\); - - \s_coarse_time[2]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[2]\, CLK => clk_div_3, PRE - => un1_soft_tick_14_i, CLR => un1_resetn_30_i, Q => - \s_coarse_time[2]_net_1\); - - un9_cpt_I_66 : XOR2 - port map(A => N_27, B => \fine_time[11]\, Y => I_66_6); - - \s_coarse_time_RNO_0[21]\ : MX2 - port map(A => \s_coarse_time_4[21]\, B => - \s_coarse_time[21]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[21]\); - - un4_s_coarse_time_I_69 : AND3 - port map(A => \s_coarse_time[9]_net_1\, B => - \s_coarse_time[10]_net_1\, C => \s_coarse_time[11]_net_1\, - Y => \DWACT_FINC_E_0[7]\); - - \s_coarse_time_RNO_0[23]\ : MX2 - port map(A => \s_coarse_time_4[23]\, B => - \s_coarse_time[23]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[23]\); - - \state_RNICEBF[0]\ : NOR3A - port map(A => \un1_cpt_0_a3_1[0]\, B => \fine_time[16]\, C - => \state[0]_net_1\, Y => \un1_cpt_0_a3_9[0]\); - - \secondary_cpt[13]\ : DFN1E0C1 - port map(D => secondary_cpt_n13, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[13]_net_1\); - - \latched_next_commutation_RNIJHS2[23]\ : XNOR2 - port map(A => \s_coarse_time[23]_net_1\, B => - \latched_next_commutation[23]_net_1\, Y => - s_coarse_time_1_23_i); - - un1_cpt_next_commutation_I_108 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_5[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_6[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_2[0]\); - - \commutation_timer_6_0__m3_i\ : MX2A - port map(A => s_coarse_time_1_NE, B => N_243, S => - \commutation_timer[0]_net_1\, Y => N_77); - - \s_coarse_time_RNO_0[24]\ : MX2 - port map(A => \s_coarse_time_4[24]\, B => - \s_coarse_time[24]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[24]\); - - un4_s_coarse_time_I_121 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \s_coarse_time[18]_net_1\, Y => N_76); - - \latched_next_commutation_RNO[9]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(9), Y => N_155); - - un1_cpt_next_commutation_I_70 : XOR2 - port map(A => \cpt_next_commutation[16]_net_1\, B => - \DWACT_ADD_CI_0_g_array_4[0]\, Y => I_70); - - \previous_coarse_time_load_RNICP96[24]\ : XNOR2 - port map(A => coarse_time_load(24), B => - \previous_coarse_time_load[24]_net_1\, Y => - previous_coarse_time_load_1_24_i); - - sirq1_RNO : NOR2 - port map(A => s_coarse_time_1_NE_0, B => - \commutation_timer[0]_net_1\, Y => - commutation_timer_0_sqmuxa_1); - - \secondary_cpt_RNI7HU21[10]\ : NOR3C - port map(A => \secondary_cpt[9]_net_1\, B => - secondary_cpt_c8, C => \secondary_cpt[10]_net_1\, Y => - secondary_cpt_c10); - - \latched_next_commutation_RNO[4]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(4), Y => N_150); - - \s_coarse_time_RNO_0[25]\ : MX2 - port map(A => \s_coarse_time_4[25]\, B => - \s_coarse_time[25]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[25]\); - - \s_coarse_time_RNO_1[11]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[11]\, Y - => un1_soft_tick_7_i); - - un4_s_coarse_time_I_202 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \s_coarse_time[27]_net_1\, Y => N_19); - - \latched_next_commutation_RNI03CE1[16]\ : NOR3C - port map(A => s_coarse_time_1_NE_21, B => - s_coarse_time_1_NE_20, C => s_coarse_time_1_NE_27, Y => - s_coarse_time_1_NE_29); - - un9_cpt_I_91 : XOR2 - port map(A => N_9_1, B => \fine_time[15]\, Y => I_91_4); - - \latched_next_commutation_RNILPS2[16]\ : XNOR2 - port map(A => \s_coarse_time[16]_net_1\, B => - \latched_next_commutation[16]_net_1\, Y => - s_coarse_time_1_16_i); - - \s_coarse_time_RNO_1[13]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[13]\, Y - => un1_soft_tick_12_i); - - \s_coarse_time[16]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[16]\, CLK => clk_div_2, PRE - => un1_soft_tick_17_i, CLR => un1_resetn_27_i, Q => - \s_coarse_time[16]_net_1\); - - \p_next_commutation[13]\ : DFN1E1 - port map(D => next_commutation(13), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[13]_net_1\); - - \latched_next_commutation[26]\ : DFN1E0P0 - port map(D => N_172, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[26]_net_1\); - - \s_coarse_time_RNO_1[2]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[2]\, Y => - un1_soft_tick_14_i); - - un1_cpt_next_commutation_I_59 : XOR2 - port map(A => \cpt_next_commutation[13]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_5[0]\, Y => I_59); - - \cpt_RNIAJA9[10]\ : NOR3C - port map(A => \fine_time[13]\, B => \fine_time[10]\, C => - \un1_cpt_0_a3_5[0]\, Y => \un1_cpt_0_a3_11[0]\); - - \s_coarse_time_RNO[12]\ : AO1C - port map(A => \s_coarse_time_4[12]\, B => soft_tick_2, C - => rstn, Y => un1_resetn_25_i); - - flag_RNIU3QU1 : MX2 - port map(A => I_45_4, B => coarse_time_load(8), S => \flag\, - Y => \s_coarse_time_4[8]\); - - flag_0_RNIL1RT2 : MX2 - port map(A => I_173_3, B => coarse_time_load(25), S => - \flag_0\, Y => \s_coarse_time_4[25]\); - - \previous_coarse_time_load_RNIE9A6[16]\ : XNOR2 - port map(A => coarse_time_load(16), B => - \previous_coarse_time_load[16]_net_1\, Y => - previous_coarse_time_load_1_16_i); - - un9_cpt_I_37 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\, - C => \fine_time[6]\, Y => N_47); - - un4_s_coarse_time_I_108 : AND3 - port map(A => \s_coarse_time[15]_net_1\, B => - \s_coarse_time[16]_net_1\, C => \s_coarse_time[17]_net_1\, - Y => \DWACT_FINC_E[12]\); - - \secondary_cpt_RNINVR5[1]\ : OR2 - port map(A => \secondary_cpt[1]_net_1\, B => - \secondary_cpt[0]_net_1\, Y => s_coarse_time38lto1); - - \latched_next_commutation_RNINPS2[25]\ : XNOR2 - port map(A => \s_coarse_time[25]_net_1\, B => - \latched_next_commutation[25]_net_1\, Y => - s_coarse_time_1_25_i); - - \s_coarse_time_RNO_0[1]\ : MX2 - port map(A => \s_coarse_time_4[1]\, B => - \s_coarse_time[1]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[1]\); - - un9_cpt_I_8 : NOR2B - port map(A => \fine_time[1]\, B => \fine_time[0]\, Y => - N_68); - - \s_coarse_time_RNO_1[14]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[14]\, Y - => un1_soft_tick_18_i); - - \latched_next_commutation_RNIBAKA[3]\ : XNOR2 - port map(A => \s_coarse_time[3]_net_1\, B => - \latched_next_commutation[3]_net_1\, Y => - s_coarse_time_1_3_i); - - \s_coarse_time_RNO_0[5]\ : MX2 - port map(A => \s_coarse_time_4[5]\, B => - \s_coarse_time[5]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[5]\); - - un9_cpt_I_59 : AND3 - port map(A => \fine_time[6]\, B => \fine_time[7]\, C => - \fine_time[8]\, Y => \DWACT_FINC_E_0[5]\); - - \previous_coarse_time_load_RNIAS9A[2]\ : XA1A - port map(A => \previous_coarse_time_load[2]_net_1\, B => - coarse_time_load(2), C => previous_coarse_time_load_1_3_i, - Y => previous_coarse_time_load_1_NE_1); - - un9_cpt_I_69 : AND3 - port map(A => \fine_time[9]\, B => \fine_time[10]\, C => - \fine_time[11]\, Y => \DWACT_FINC_E[7]\); - - \s_coarse_time_RNO_1[15]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[15]\, Y - => un1_soft_tick_3_i); - - \p_next_commutation[1]\ : DFN1E1 - port map(D => next_commutation(1), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[1]_net_1\); - - flag_0_RNIBMKO2 : MX2 - port map(A => I_136_3, B => coarse_time_load(21), S => - \flag_0\, Y => \s_coarse_time_4[21]\); - - \s_coarse_time_RNO_0[22]\ : MX2 - port map(A => \s_coarse_time_4[22]\, B => - \s_coarse_time[22]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[22]\); - - \latched_next_commutation_RNIV9T2[29]\ : XNOR2 - port map(A => \s_coarse_time[29]_net_1\, B => - \latched_next_commutation[29]_net_1\, Y => - s_coarse_time_1_29_i); - - \p_next_commutation_RNIPLIA[23]\ : XNOR2 - port map(A => next_commutation(23), B => - \p_next_commutation[23]_net_1\, Y => N_133_i_i_0); - - un4_s_coarse_time_I_19 : NOR2B - port map(A => \s_coarse_time[3]_net_1\, B => - \DWACT_FINC_E_0[0]\, Y => N_149); - - un1_cpt_next_commutation_I_92 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_11_2[0]\, B => - \cpt_next_commutation[14]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_6[0]\); - - \s_coarse_time_RNO[27]\ : AO1C - port map(A => \s_coarse_time_4[27]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_20_i); - - un9_cpt_I_98 : XOR2 - port map(A => N_4_0, B => \fine_time[16]\, Y => I_98_4); - - un4_s_coarse_time_I_203 : XOR2 - port map(A => N_19, B => \s_coarse_time[28]_net_1\, Y => - I_203_3); - - un9_cpt_I_41 : AND2 - port map(A => \fine_time[6]\, B => \fine_time[7]\, Y => - \DWACT_FINC_E_0[3]\); - - un9_cpt_I_30 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[1]\, - C => \fine_time[5]\, Y => N_52_0); - - \latched_next_commutation_RNIJQKA[7]\ : XNOR2 - port map(A => \s_coarse_time[7]_net_1\, B => - \latched_next_commutation[7]_net_1\, Y => - s_coarse_time_1_7_i); - - un3_grspw_tick_0 : OR2A - port map(A => rstn, B => soft_tick_0, Y => reset_i_0_0); - - GND_i : GND - port map(Y => \GND\); - - \s_coarse_time[4]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[4]\, CLK => clk_div_3, PRE - => un1_soft_tick_5_i, CLR => un1_resetn_17_i, Q => - \s_coarse_time[4]_net_1\); - - un4_s_coarse_time_I_83 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E_0[7]\, - C => \DWACT_FINC_E[8]\, Y => N_103); - - \latched_next_commutation_RNI0UHB[12]\ : NOR3C - port map(A => s_coarse_time_1_13_i, B => - s_coarse_time_1_12_i, C => s_coarse_time_1_NE_7, Y => - s_coarse_time_1_NE_19); - - \s_coarse_time[12]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[12]\, CLK => clk_div_2, PRE - => un1_soft_tick_13_i, CLR => un1_resetn_25_i, Q => - \s_coarse_time[12]_net_1\); - - \secondary_cpt_RNII5H8[15]\ : NOR2 - port map(A => \secondary_cpt[15]_net_1\, B => - \secondary_cpt[6]_net_1\, Y => s_coarse_time38lto16_2); - - \latched_next_commutation_RNI06K61[10]\ : NOR3C - port map(A => s_coarse_time_1_NE_5, B => - s_coarse_time_1_NE_4, C => s_coarse_time_1_NE_19, Y => - s_coarse_time_1_NE_25); - - un1_cpt_next_commutation_I_1 : AND2 - port map(A => \cpt_next_commutation[0]_net_1\, B => - \commutation_timer_RNI3EI8[0]_net_1\, Y => - \DWACT_ADD_CI_0_TMP[0]\); - - \s_coarse_time_RNO_1[12]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[12]\, Y - => un1_soft_tick_13_i); - - \latched_next_commutation[13]\ : DFN1E0P0 - port map(D => N_159, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[13]_net_1\); - - \p_next_commutation_RNI3AJA[28]\ : XNOR2 - port map(A => next_commutation(28), B => - \p_next_commutation[28]_net_1\, Y => N_138_i_i_0); - - \p_next_commutation_RNIG75L[22]\ : XA1A - port map(A => \p_next_commutation[22]_net_1\, B => - next_commutation(22), C => N_133_i_i_0, Y => - un1_commutation_timer_3_0_a2_11); - - un9_cpt_I_72 : NOR2B - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E[6]\, Y - => N_22); - - un1_cpt_next_commutation_I_91 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_4[0]\); - - \previous_coarse_time_load_RNI6996[12]\ : XNOR2 - port map(A => coarse_time_load(12), B => - \previous_coarse_time_load[12]_net_1\, Y => - previous_coarse_time_load_1_12_i); - - flag_0_RNIF4P13 : MX2 - port map(A => I_203_3, B => coarse_time_load(28), S => - \flag_0\, Y => \s_coarse_time_4[28]\); - - \secondary_cpt_RNO[13]\ : XOR2 - port map(A => secondary_cpt_c12, B => - \secondary_cpt[13]_net_1\, Y => secondary_cpt_n13); - - un9_cpt_I_34 : AND3 - port map(A => \fine_time[3]\, B => \fine_time[4]\, C => - \fine_time[5]\, Y => \DWACT_FINC_E_0[2]\); - - \coarse_time[7]\ : DFN1C0 - port map(D => \s_coarse_time[7]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(7)); - - un1_cpt_next_commutation_I_57 : XOR2 - port map(A => \cpt_next_commutation[12]_net_1\, B => - \DWACT_ADD_CI_0_g_array_10[0]\, Y => I_57); - - \cpt_next_commutation_RNIMQPB[16]\ : NOR3A - port map(A => \cpt_next_commutation[16]_net_1\, B => - \cpt_next_commutation[0]_net_1\, C => - \cpt_next_commutation[4]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_3); - - \secondary_cpt_RNIKPCE[12]\ : NOR3C - port map(A => \secondary_cpt[6]_net_1\, B => - \secondary_cpt[12]_net_1\, C => - secondary_cpt_c12_m6_0_a2_1, Y => - secondary_cpt_c12_m6_0_a2_4); - - un9_cpt_I_73 : XOR2 - port map(A => N_22, B => \fine_time[12]\, Y => I_73_4); - - flag_RNI73OT : MX2 - port map(A => I_13_12, B => coarse_time_load(3), S => - \flag\, Y => \s_coarse_time_4[3]\); - - \coarse_time[13]\ : DFN1C0 - port map(D => \s_coarse_time[13]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(13)); - - \p_next_commutation[5]\ : DFN1E1 - port map(D => next_commutation(5), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[5]_net_1\); - - \cpt_RNO[1]\ : NOR2B - port map(A => I_5_9, B => \un1_cpt_0[0]\, Y => \cpt_5[1]\); - - \secondary_cpt[8]\ : DFN1E0C1 - port map(D => secondary_cpt_n8, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[8]_net_1\); - - \latched_next_commutation_RNINTS2[17]\ : XNOR2 - port map(A => \s_coarse_time[17]_net_1\, B => - \latched_next_commutation[17]_net_1\, Y => - s_coarse_time_1_17_i); - - un9_cpt_I_48 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\, - C => \DWACT_FINC_E_0[3]\, Y => \DWACT_FINC_E[4]\); - - \p_next_commutation[28]\ : DFN1E1 - port map(D => next_commutation(28), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[28]_net_1\); - - \s_coarse_time_RNO[17]\ : AO1C - port map(A => \s_coarse_time_4[17]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_14_i); - - \p_next_commutation_RNIOU9A1[20]\ : NOR3C - port map(A => N_131_i_i_0, B => N_130_i_i_0, C => - un1_commutation_timer_3_0_a2_11, Y => - un1_commutation_timer_3_0_a2_21); - - un4_s_coarse_time_I_80 : AND2 - port map(A => \s_coarse_time[12]_net_1\, B => - \s_coarse_time[13]_net_1\, Y => \DWACT_FINC_E[8]\); - - \s_coarse_time_RNO[23]\ : AO1C - port map(A => \s_coarse_time_4[23]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_16_i); - - \secondary_cpt_RNO[6]\ : AX1C - port map(A => \secondary_cpt[5]_net_1\, B => - secondary_cpt_c4, C => \secondary_cpt[6]_net_1\, Y => - secondary_cpt_n6); - - \latched_next_commutation_RNO[17]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(17), - Y => N_163); - - flag_0_RNI43UP2 : MX2 - port map(A => I_143_3, B => coarse_time_load(22), S => - \flag_0\, Y => \s_coarse_time_4[22]\); - - \latched_next_commutation[17]\ : DFN1E0P0 - port map(D => N_163, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[17]_net_1\); - - \s_coarse_time_RNO_0[8]\ : MX2 - port map(A => \s_coarse_time_4[8]\, B => - \s_coarse_time[8]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[8]\); - - \cpt_next_commutation[5]\ : DFN1C0 - port map(D => I_60, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[5]_net_1\); - - \coarse_time[15]\ : DFN1C0 - port map(D => \s_coarse_time[15]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(15)); - - \latched_next_commutation_RNO[3]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(3), Y => N_149_0); - - \cpt_next_commutation[8]\ : DFN1C0 - port map(D => I_66_4, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[8]_net_1\); - - \s_coarse_time_RNO[3]\ : AO1C - port map(A => \s_coarse_time_4[3]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_31_i); - - \previous_coarse_time_load_RNICPJK[4]\ : NOR3C - port map(A => previous_coarse_time_load_1_5_i, B => - previous_coarse_time_load_1_4_i, C => - previous_coarse_time_load_1_NE_3, Y => - previous_coarse_time_load_1_NE_17); - - \s_coarse_time[5]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[5]\, CLK => clk_div_3, PRE - => un1_soft_tick_4_i, CLR => un1_resetn_26_i, Q => - \s_coarse_time[5]_net_1\); - - un1_cpt_next_commutation_I_40 : XOR2 - port map(A => \cpt_next_commutation[0]_net_1\, B => - \commutation_timer_RNI3EI8[0]_net_1\, Y => - \DWACT_ADD_CI_0_partial_sum[0]\); - - \cpt_RNIVULI[2]\ : NOR3C - port map(A => flag_1_sqmuxa_i_o3_2, B => - flag_1_sqmuxa_i_o3_1, C => flag_1_sqmuxa_i_o3_10, Y => - flag_1_sqmuxa_i_o3_13); - - un1_cpt_next_commutation_I_54 : XOR2 - port map(A => \cpt_next_commutation[3]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12[0]\, Y => I_54); - - \s_coarse_time_RNO[29]\ : AO1C - port map(A => \s_coarse_time_4[29]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_11_i); - - \p_next_commutation[14]\ : DFN1E1 - port map(D => next_commutation(14), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[14]_net_1\); - - \latched_next_commutation_RNO[31]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(31), - Y => N_177); - - flag_RNIBKIE2 : MX2 - port map(A => I_84_3, B => coarse_time_load(14), S => - \flag\, Y => \s_coarse_time_4[14]\); - - un4_s_coarse_time_I_146 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => - \s_coarse_time[21]_net_1\, C => \s_coarse_time[22]_net_1\, - Y => \DWACT_FINC_E[33]\); - - un4_s_coarse_time_I_129 : XOR2 - port map(A => N_71, B => \s_coarse_time[20]_net_1\, Y => - I_129_3); - - \cpt_next_commutation[11]\ : DFN1C0 - port map(D => I_56_4, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[11]_net_1\); - - \state_RNIEG3J2_1[0]\ : NOR2 - port map(A => N_25, B => N_24, Y => \un1_cpt[0]\); - - \state_RNIEG3J2[0]\ : NOR2 - port map(A => N_25, B => N_24, Y => \un1_cpt_0[0]\); - - flag_RNIOEVB2 : MX2 - port map(A => I_73_3, B => coarse_time_load(12), S => - \flag\, Y => \s_coarse_time_4[12]\); - - \secondary_cpt_RNI204E1[10]\ : NOR3C - port map(A => secondary_cpt_c12_m6_0_a2_5, B => - secondary_cpt_c12_m6_0_a2_4, C => secondary_cpt_c3, Y => - secondary_cpt_c12); - - \p_next_commutation_RNI4LPA[0]\ : XA1A - port map(A => \p_next_commutation[0]_net_1\, B => - next_commutation(0), C => N_111_i_i_0, Y => - un1_commutation_timer_3_0_a2_0); - - \latched_next_commutation[9]\ : DFN1E0P0 - port map(D => N_155, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[9]_net_1\); - - un4_s_coarse_time_I_122 : XOR2 - port map(A => N_76, B => \s_coarse_time[19]_net_1\, Y => - I_122_3); - - \p_next_commutation_RNI086L[26]\ : XA1A - port map(A => \p_next_commutation[26]_net_1\, B => - next_commutation(26), C => N_137_i_i_0, Y => - un1_commutation_timer_3_0_a2_13); - - \latched_next_commutation[24]\ : DFN1E0P0 - port map(D => N_170, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[24]_net_1\); - - \s_coarse_time_RNO[13]\ : AO1C - port map(A => \s_coarse_time_4[13]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_18_i); - - un9_cpt_I_52 : XOR2 - port map(A => N_37, B => \fine_time[9]\, Y => I_52_5); - - \latched_next_commutation_RNI0M6N[24]\ : NOR3C - port map(A => s_coarse_time_1_NE_13, B => - s_coarse_time_1_NE_12, C => s_coarse_time_1_NE_23, Y => - s_coarse_time_1_NE_27); - - \s_coarse_time[0]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[0]\, CLK => clk_div_2, PRE - => un1_soft_tick_25_i, CLR => un1_resetn_29_i, Q => - \s_coarse_time[0]_net_1\); - - un9_cpt_I_62 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\, - C => \DWACT_FINC_E_0[5]\, Y => \DWACT_FINC_E[6]\); - - \coarse_time_RNIGHP5[0]\ : INV - port map(A => \coarse_time[0]_net_1\, Y => coarse_time_i(0)); - - flag_RNIHG6O1 : MX2 - port map(A => I_38_5, B => coarse_time_load(7), S => \flag\, - Y => \s_coarse_time_4[7]\); - - \s_coarse_time_RNO[19]\ : AO1C - port map(A => \s_coarse_time_4[19]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_12_i); - - un4_s_coarse_time_I_30 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[1]\, - C => \s_coarse_time[5]_net_1\, Y => N_141); - - \latched_next_commutation_RNI0C3A5_0[10]\ : OR2B - port map(A => s_coarse_time_1_NE_29, B => - s_coarse_time_1_NE_28, Y => s_coarse_time_1_NE); - - \latched_next_commutation[28]\ : DFN1E0P0 - port map(D => N_174, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[28]_net_1\); - - un9_cpt_I_23 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \fine_time[3]\, C => - \fine_time[4]\, Y => N_57); - - sirq2 : DFN1E1C0 - port map(D => \commutation_timer[0]_net_1\, CLK => lclk_c, - CLR => rstn, E => N_6, Q => pirq(13)); - - flag_0_RNIP8HS2 : MX2 - port map(A => I_166_3, B => coarse_time_load(24), S => - \flag_0\, Y => \s_coarse_time_4[24]\); - - \latched_next_commutation[29]\ : DFN1E0P0 - port map(D => N_175, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[29]_net_1\); - - \coarse_time[1]\ : DFN1C0 - port map(D => \s_coarse_time[1]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(1)); - - flag_0_RNIB25I2 : MX2 - port map(A => I_98_3, B => coarse_time_load(16), S => - \flag_0\, Y => \s_coarse_time_4[16]\); - - \s_coarse_time[14]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[14]\, CLK => clk_div_2, PRE - => un1_soft_tick_18_i, CLR => un1_resetn_3_i, Q => - \s_coarse_time[14]_net_1\); - - \s_coarse_time_RNO_1[4]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[4]\, Y => - un1_soft_tick_5_i); - - \previous_coarse_time_load_RNIM1B6[29]\ : XNOR2 - port map(A => coarse_time_load(29), B => - \previous_coarse_time_load[29]_net_1\, Y => - previous_coarse_time_load_1_29_i); - - un4_s_coarse_time_I_125 : AND2 - port map(A => \s_coarse_time[18]_net_1\, B => - \s_coarse_time[19]_net_1\, Y => \DWACT_FINC_E[14]\); - - flag_RNIVF4N : MX2 - port map(A => I_9_8, B => coarse_time_load(2), S => \flag\, - Y => \s_coarse_time_4[2]\); - - un4_s_coarse_time_I_38 : XOR2 - port map(A => N_136, B => \s_coarse_time[7]_net_1\, Y => - I_38_5); - - \cpt[10]\ : DFN1C1 - port map(D => I_56_6, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[10]\); - - \p_next_commutation[10]\ : DFN1E1 - port map(D => next_commutation(10), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[10]_net_1\); - - \latched_next_commutation[20]\ : DFN1E0P0 - port map(D => N_166, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[20]_net_1\); - - \latched_next_commutation_RNIK7Q5[18]\ : XA1A - port map(A => \latched_next_commutation[18]_net_1\, B => - \s_coarse_time[18]_net_1\, C => s_coarse_time_1_19_i, Y - => s_coarse_time_1_NE_9); - - \commutation_timer_RNINQD9E_0[0]\ : AO1 - port map(A => un1_commutation_timer_3_0_a2_30, B => - s_coarse_time_1_NE, C => \commutation_timer[0]_net_1\, Y - => un1_commutation_timer_3); - - \latched_next_commutation_RNO[27]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(27), - Y => N_173); - - \p_next_commutation[30]\ : DFN1E1 - port map(D => next_commutation(30), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[30]_net_1\); - - \s_coarse_time[21]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[21]\, CLK => clk_div_3, PRE - => un1_soft_tick_28_i, CLR => un1_resetn_10_i, Q => - \s_coarse_time[21]_net_1\); - - \p_next_commutation[3]\ : DFN1E1 - port map(D => next_commutation(3), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[3]_net_1\); - - \cpt_next_commutation_RNO[0]\ : OA1A - port map(A => \commutation_timer[0]_net_1\, B => N_243, C - => \DWACT_ADD_CI_0_partial_sum[0]\, Y => N_11); - - \s_coarse_time[27]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[27]\, CLK => clk_div_3, PRE - => un1_soft_tick_21_i, CLR => un1_resetn_20_i, Q => - \s_coarse_time[27]_net_1\); - - \previous_coarse_time_load[14]\ : DFN1E0C0 - port map(D => coarse_time_load(14), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[14]_net_1\); - - \s_coarse_time_RNO_0[3]\ : MX2 - port map(A => \s_coarse_time_4[3]\, B => - \s_coarse_time[3]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[3]\); - - \secondary_cpt_RNIVVR5[4]\ : NOR2B - port map(A => \secondary_cpt[5]_net_1\, B => - \secondary_cpt[4]_net_1\, Y => s_coarse_time38lto5_1); - - \s_coarse_time_RNO_0[30]\ : MX2 - port map(A => \s_coarse_time_4[30]\, B => - \s_coarse_time[30]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[30]\); - - un4_s_coarse_time_I_206 : AND2 - port map(A => \s_coarse_time[27]_net_1\, B => - \s_coarse_time[28]_net_1\, Y => \DWACT_FINC_E[25]\); - - un9_cpt_I_97 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E_0[10]\, - C => \fine_time[15]\, Y => N_4_0); - - \previous_coarse_time_load_RNIKMV43[20]\ : NOR3C - port map(A => previous_coarse_time_load_1_NE_21, B => - previous_coarse_time_load_1_NE_20, C => - previous_coarse_time_load_1_NE_27, Y => - previous_coarse_time_load_1_NE_29); - - flag : DFN1E0C1 - port map(D => flag_1, CLK => clk_div_0, CLR => reset_i_0, E - => flag_1_sqmuxa_1, Q => \flag\); - - un1_cpt_next_commutation_I_55 : XOR2 - port map(A => \cpt_next_commutation[10]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_1[0]\, Y => I_55); - - un4_s_coarse_time_I_179 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \DWACT_FINC_E[20]\, Y => \DWACT_FINC_E[21]\); - - \secondary_cpt_RNO[7]\ : XOR2 - port map(A => secondary_cpt_c6, B => - \secondary_cpt[7]_net_1\, Y => secondary_cpt_n7); - - \previous_coarse_time_load[6]\ : DFN1E0C0 - port map(D => coarse_time_load(6), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[6]_net_1\); - - \latched_next_commutation[25]\ : DFN1E0P0 - port map(D => N_171, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[25]_net_1\); - - \latched_next_commutation[16]\ : DFN1E0P0 - port map(D => N_162, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[16]_net_1\); - - \secondary_cpt_RNI50S5[8]\ : NOR2B - port map(A => \secondary_cpt[7]_net_1\, B => - \secondary_cpt[8]_net_1\, Y => - secondary_cpt_c12_m6_0_a2_1); - - \s_coarse_time_RNO_0[0]\ : MX2A - port map(A => \s_coarse_time_4[0]\, B => - \s_coarse_time[0]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[0]\); - - \latched_next_commutation_RNO[18]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(18), - Y => N_164); - - \secondary_cpt_RNIVU5B[14]\ : NOR2 - port map(A => \secondary_cpt[13]_net_1\, B => - \secondary_cpt[14]_net_1\, Y => s_coarse_time38lto16_1); - - un4_s_coarse_time_I_172 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[19]\, Y => N_40); - - flag_RNI5TIH1 : MX2 - port map(A => I_31_7, B => coarse_time_load(6), S => \flag\, - Y => \s_coarse_time_4[6]\); - - un1_cpt_next_commutation_I_68 : XOR2 - port map(A => \cpt_next_commutation[2]_net_1\, B => - \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_68); - - un1_cpt_next_commutation_I_66 : XOR2 - port map(A => \cpt_next_commutation[8]_net_1\, B => - \DWACT_ADD_CI_0_g_array_3[0]\, Y => I_66_4); - - \s_coarse_time_RNO_1[5]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[5]\, Y => - un1_soft_tick_4_i); - - \cpt_RNIDJA9[7]\ : NOR3A - port map(A => flag_1_sqmuxa_i_o3_4, B => \fine_time[10]\, C - => \fine_time[7]\, Y => flag_1_sqmuxa_i_o3_10); - - \coarse_time[21]\ : DFN1C0 - port map(D => \s_coarse_time[21]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(21)); - - un4_s_coarse_time_I_62 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E_0[6]\); - - \previous_coarse_time_load[2]\ : DFN1E0C0 - port map(D => coarse_time_load(2), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[2]_net_1\); - - \latched_next_commutation[30]\ : DFN1E0P0 - port map(D => N_176, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[30]_net_1\); - - \coarse_time[30]\ : DFN1C0 - port map(D => \s_coarse_time[30]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(30)); - - \previous_coarse_time_load_RNI8196[31]\ : XNOR2 - port map(A => coarse_time_load(31), B => - \previous_coarse_time_load[31]_net_1\, Y => - previous_coarse_time_load_1_31_i); - - un4_s_coarse_time_I_51 : NOR2B - port map(A => \s_coarse_time[8]_net_1\, B => - \DWACT_FINC_E_0[4]\, Y => N_126); - - un4_s_coarse_time_I_41 : AND2 - port map(A => \s_coarse_time[6]_net_1\, B => - \s_coarse_time[7]_net_1\, Y => \DWACT_FINC_E[3]\); - - un9_cpt_I_90 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E_0[9]\, Y => N_9_1); - - \latched_next_commutation[5]\ : DFN1E0P0 - port map(D => N_151, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[5]_net_1\); - - \s_coarse_time_RNO_1[20]\ : NOR2B - port map(A => soft_tick_3, B => \s_coarse_time_4[20]\, Y - => un1_soft_tick_23_i); - - un4_s_coarse_time_I_5 : XOR2 - port map(A => \s_coarse_time[0]_net_1\, B => - \s_coarse_time[1]_net_1\, Y => I_5_8); - - \latched_next_commutation_RNO[15]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(15), Y => N_161); - - \cpt_next_commutation_RNO[16]\ : OA1A - port map(A => \commutation_timer[0]_net_1\, B => N_243, C - => I_70, Y => N_9); - - \p_next_commutation_RNISJAA2[8]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_5, B => - un1_commutation_timer_3_0_a2_4, C => - un1_commutation_timer_3_0_a2_19, Y => - un1_commutation_timer_3_0_a2_25); - - \cpt[15]\ : DFN1C1 - port map(D => I_91_4, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[15]\); - - \previous_coarse_time_load[17]\ : DFN1E0C0 - port map(D => coarse_time_load(17), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[17]_net_1\); - - \secondary_cpt_RNO[1]\ : XOR2 - port map(A => \secondary_cpt[1]_net_1\, B => - \secondary_cpt[0]_net_1\, Y => secondary_cpt_n1); - - \previous_coarse_time_load[10]\ : DFN1E0C0 - port map(D => coarse_time_load(10), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[10]_net_1\); - - \p_next_commutation[26]\ : DFN1E1 - port map(D => next_commutation(26), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[26]_net_1\); - - \previous_coarse_time_load_RNIQS9A[6]\ : XA1A - port map(A => \previous_coarse_time_load[6]_net_1\, B => - coarse_time_load(6), C => previous_coarse_time_load_1_7_i, - Y => previous_coarse_time_load_1_NE_3); - - \cpt_next_commutation_RNILU1P[5]\ : NOR3B - port map(A => sirq2_1_sqmuxa_i_a2_2, B => - sirq2_1_sqmuxa_i_a2_3, C => - \cpt_next_commutation[5]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_5); - - \previous_coarse_time_load_RNI8U45[4]\ : XNOR2 - port map(A => coarse_time_load(4), B => - \previous_coarse_time_load[4]_net_1\, Y => - previous_coarse_time_load_1_4_i); - - \p_next_commutation[17]\ : DFN1E1 - port map(D => next_commutation(17), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[17]_net_1\); - - \s_coarse_time_RNO_1[30]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[30]\, Y - => un1_soft_tick_16_i); - - un4_s_coarse_time_I_156 : XOR2 - port map(A => N_52, B => \s_coarse_time[23]_net_1\, Y => - I_156_3); - - un1_cpt_next_commutation_I_106 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_4[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2_1[0]\); - - \s_coarse_time_RNO_0[10]\ : MX2 - port map(A => \s_coarse_time_4[10]\, B => - \s_coarse_time[10]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[10]\); - - un4_s_coarse_time_I_173 : XOR2 - port map(A => N_40, B => \s_coarse_time[25]_net_1\, Y => - I_173_3); - - \s_coarse_time_RNO_1[7]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[7]\, Y => - un1_soft_tick_11_i); - - \cpt[1]\ : DFN1C1 - port map(D => \cpt_5[1]\, CLK => clk_div_0, CLR => - reset_i_0_1, Q => \fine_time[1]\); - - \latched_next_commutation_RNO[30]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(30), - Y => N_176); - - \cpt[9]\ : DFN1C1 - port map(D => I_52_5, CLK => clk_div_0, CLR => reset_i_0, Q - => \fine_time[9]\); - - un4_s_coarse_time_I_44 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \DWACT_FINC_E[3]\, Y => N_131); - - un9_cpt_I_94 : AND2 - port map(A => \DWACT_FINC_E[7]\, B => \DWACT_FINC_E_0[9]\, - Y => \DWACT_FINC_E_0[10]\); - - \previous_coarse_time_load[30]\ : DFN1E0C0 - port map(D => coarse_time_load(30), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[30]_net_1\); - - \p_next_commutation[4]\ : DFN1E1 - port map(D => next_commutation(4), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[4]_net_1\); - - \previous_coarse_time_load[3]\ : DFN1E0C0 - port map(D => coarse_time_load(3), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[3]_net_1\); - - \p_next_commutation_RNI0M9B1[0]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_1, B => - un1_commutation_timer_3_0_a2_0, C => - un1_commutation_timer_3_0_a2_17, Y => - un1_commutation_timer_3_0_a2_24); - - \latched_next_commutation_RNI0HGA1[0]\ : NOR3C - port map(A => s_coarse_time_1_1_i, B => s_coarse_time_1_0_i, - C => s_coarse_time_1_NE_1, Y => s_coarse_time_1_NE_16); - - \previous_coarse_time_load_RNI6QHC[10]\ : XA1A - port map(A => \previous_coarse_time_load[10]_net_1\, B => - coarse_time_load(10), C => - previous_coarse_time_load_1_11_i, Y => - previous_coarse_time_load_1_NE_5); - - \coarse_time[27]\ : DFN1C0 - port map(D => \s_coarse_time[27]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(27)); - - \p_next_commutation[22]\ : DFN1E1 - port map(D => next_commutation(22), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[22]_net_1\); - - \cpt[13]\ : DFN1C1 - port map(D => I_77_4, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[13]\); - - \cpt_RNIA6G2[4]\ : NOR2 - port map(A => \fine_time[4]\, B => \fine_time[6]\, Y => - flag_1_sqmuxa_i_o3_5); - - \previous_coarse_time_load[24]\ : DFN1E0C0 - port map(D => coarse_time_load(24), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[24]_net_1\); - - \p_next_commutation_RNIOFCA1[16]\ : NOR3C - port map(A => N_127_i_i_0, B => N_126_i_i_0, C => - un1_commutation_timer_3_0_a2_9, Y => - un1_commutation_timer_3_0_a2_20); - - \s_coarse_time[9]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[9]\, CLK => clk_int, PRE => - un1_soft_tick_30_i, CLR => un1_resetn_22_i, Q => - \s_coarse_time[9]_net_1\); - - \p_next_commutation_RNIS5RA[6]\ : XA1A - port map(A => \p_next_commutation[6]_net_1\, B => - next_commutation(6), C => N_117_i_i_0, Y => - un1_commutation_timer_3_0_a2_3); - - un1_cpt_next_commutation_I_88 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_2[0]\); - - flag_RNIOSGG : MX2 - port map(A => I_5_8, B => coarse_time_load(1), S => \flag\, - Y => \s_coarse_time_4[1]\); - - un4_s_coarse_time_I_209 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[25]\, Y => N_14); - - \p_next_commutation[8]\ : DFN1E1 - port map(D => next_commutation(8), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[8]_net_1\); - - \state_RNI7OH91[0]\ : NOR3C - port map(A => flag_1_sqmuxa_i_o3_13, B => - flag_1_sqmuxa_i_o3_14, C => \state[0]_net_1\, Y => N_24); - - \cpt_next_commutation[10]\ : DFN1C0 - port map(D => I_55, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[10]_net_1\); - - \coarse_time[26]\ : DFN1C0 - port map(D => \s_coarse_time[26]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(26)); - - un4_s_coarse_time_I_136 : XOR2 - port map(A => N_66, B => \s_coarse_time[21]_net_1\, Y => - I_136_3); - - \secondary_cpt_RNO[3]\ : XOR2 - port map(A => secondary_cpt_c2, B => - \secondary_cpt[3]_net_1\, Y => secondary_cpt_n3); - - \cpt[12]\ : DFN1C1 - port map(D => I_73_4, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[12]\); - - un4_s_coarse_time_I_12 : AND3 - port map(A => \s_coarse_time[0]_net_1\, B => - \s_coarse_time[1]_net_1\, C => \s_coarse_time[2]_net_1\, - Y => N_154_0); - - un4_s_coarse_time_I_97 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E[10]\, - C => \s_coarse_time[15]_net_1\, Y => N_93); - - \latched_next_commutation_RNO[13]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(13), Y => N_159); - - un4_s_coarse_time_I_27 : AND2 - port map(A => \s_coarse_time[3]_net_1\, B => - \s_coarse_time[4]_net_1\, Y => \DWACT_FINC_E[1]\); - - p_clk_div_RNI8FA8 : NOR2A - port map(A => clk_div_0, B => \p_clk_div\, Y => - un1_p_clk_div); - - \latched_next_commutation_RNIF9S2[21]\ : XNOR2 - port map(A => \s_coarse_time[21]_net_1\, B => - \latched_next_commutation[21]_net_1\, Y => - s_coarse_time_1_21_i); - - \secondary_cpt_RNI4EG42[8]\ : OR3C - port map(A => s_coarse_time38lt16, B => - s_coarse_time38lto16_7, C => s_coarse_time38lto16_8, Y - => s_coarse_time38); - - \coarse_time[24]\ : DFN1C0 - port map(D => \s_coarse_time[24]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(24)); - - un9_cpt_I_44 : AND3 - port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\, - C => \DWACT_FINC_E_0[3]\, Y => N_42); - - \s_coarse_time_RNO[2]\ : AO1C - port map(A => \s_coarse_time_4[2]\, B => soft_tick_3, C => - rstn, Y => un1_resetn_30_i); - - flag_RNICND52 : MX2 - port map(A => I_52_4, B => coarse_time_load(9), S => \flag\, - Y => \s_coarse_time_4[9]\); - - \previous_coarse_time_load_RNIIU45[9]\ : XNOR2 - port map(A => coarse_time_load(9), B => - \previous_coarse_time_load[9]_net_1\, Y => - previous_coarse_time_load_1_9_i); - - \latched_next_commutation_RNO[28]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(28), - Y => N_174); - - \s_coarse_time_RNO_1[28]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[28]\, Y - => un1_soft_tick_15_i); - - \p_next_commutation_RNILHIA[13]\ : XNOR2 - port map(A => next_commutation(13), B => - \p_next_commutation[13]_net_1\, Y => N_123_i_i_0); - - \cpt[2]\ : DFN1C1 - port map(D => I_9_9, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[2]\); - - \p_next_commutation_RNIT1JA[17]\ : XNOR2 - port map(A => next_commutation(17), B => - \p_next_commutation[17]_net_1\, Y => N_127_i_i_0); - - \latched_next_commutation[3]\ : DFN1E0P0 - port map(D => N_149_0, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[3]_net_1\); - - \p_next_commutation_RNIPPIA[15]\ : XNOR2 - port map(A => next_commutation(15), B => - \p_next_commutation[15]_net_1\, Y => N_125_i_i_0); - - \latched_next_commutation_RNIFIKA[5]\ : XNOR2 - port map(A => \s_coarse_time[5]_net_1\, B => - \latched_next_commutation[5]_net_1\, Y => - s_coarse_time_1_5_i); - - \previous_coarse_time_load[27]\ : DFN1E0C0 - port map(D => coarse_time_load(27), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[27]_net_1\); - - \s_coarse_time_RNII9T9[0]\ : MX2B - port map(A => \s_coarse_time[0]_net_1\, B => - coarse_time_load(0), S => \flag\, Y => - \s_coarse_time_4[0]\); - - \p_next_commutation_RNIJSC5[1]\ : XNOR2 - port map(A => next_commutation(1), B => - \p_next_commutation[1]_net_1\, Y => N_111_i_i_0); - - \previous_coarse_time_load[20]\ : DFN1E0C0 - port map(D => coarse_time_load(20), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[20]_net_1\); - - un9_cpt_I_87 : AND3 - port map(A => \fine_time[12]\, B => \fine_time[13]\, C => - \fine_time[14]\, Y => \DWACT_FINC_E_0[9]\); - - \s_coarse_time_RNO_0[18]\ : MX2 - port map(A => \s_coarse_time_4[18]\, B => - \s_coarse_time[18]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[18]\); - - \s_coarse_time[20]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[20]\, CLK => clk_div_3, PRE - => un1_soft_tick_23_i, CLR => un1_resetn_23_i, Q => - \s_coarse_time[20]_net_1\); - - \latched_next_commutation_RNO[25]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(25), - Y => N_171); - - flag_0_RNI83FJ2 : MX2 - port map(A => I_105_3, B => coarse_time_load(17), S => - \flag_0\, Y => \s_coarse_time_4[17]\); - - \cpt_next_commutation_RNITPT9[1]\ : NOR3 - port map(A => \cpt_next_commutation[2]_net_1\, B => - \cpt_next_commutation[1]_net_1\, C => - \cpt_next_commutation[3]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_2); - - \latched_next_commutation[14]\ : DFN1E0P0 - port map(D => N_160, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[14]_net_1\); - - \s_coarse_time_RNO[8]\ : AO1C - port map(A => \s_coarse_time_4[8]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_21_i); - - \p_next_commutation_RNIGRLL[4]\ : NOR3C - port map(A => N_115_i_i_0, B => N_114_i_i_0, C => - un1_commutation_timer_3_0_a2_3, Y => - un1_commutation_timer_3_0_a2_17); - - \previous_coarse_time_load[1]\ : DFN1E0C0 - port map(D => coarse_time_load(1), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[1]_net_1\); - - un4_s_coarse_time_I_224 : XOR2 - port map(A => N_4, B => \s_coarse_time[31]_net_1\, Y => - I_224_1); - - \cpt_RNO[0]\ : OA1C - port map(A => \fine_time[0]\, B => N_24, C => N_25, Y => - N_7); - - un4_s_coarse_time_I_186 : XOR2 - port map(A => N_31, B => \s_coarse_time[26]_net_1\, Y => - I_186_3); - - \secondary_cpt_RNO[12]\ : AX1C - port map(A => \secondary_cpt[11]_net_1\, B => - secondary_cpt_c10, C => \secondary_cpt[12]_net_1\, Y => - secondary_cpt_n12); - - un9_cpt_I_16 : AND3 - port map(A => \fine_time[0]\, B => \fine_time[1]\, C => - \fine_time[2]\, Y => \DWACT_FINC_E[0]\); - - \coarse_time[22]\ : DFN1C0 - port map(D => \s_coarse_time[22]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(22)); - - p_clk_div : DFN1E1 - port map(D => clk_div_0, CLK => lclk_c, E => rstn, Q => - \p_clk_div\); - - un4_s_coarse_time_I_220 : AND2 - port map(A => \DWACT_FINC_E[26]\, B => - \s_coarse_time[30]_net_1\, Y => \DWACT_FINC_E[27]\); - - flag_0_RNIU9B43 : MX2 - port map(A => I_217_1, B => coarse_time_load(30), S => - \flag_0\, Y => \s_coarse_time_4[30]\); - - \secondary_cpt_RNIDOOG[16]\ : NOR3 - port map(A => \secondary_cpt[12]_net_1\, B => - \secondary_cpt[16]_net_1\, C => \secondary_cpt[11]_net_1\, - Y => s_coarse_time38lto16_5); - - un4_s_coarse_time_I_111 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[28]\); - - \latched_next_commutation_RNI47P5[14]\ : XA1A - port map(A => \latched_next_commutation[14]_net_1\, B => - \s_coarse_time[14]_net_1\, C => s_coarse_time_1_15_i, Y - => s_coarse_time_1_NE_7); - - \s_coarse_time_RNO_1[27]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[27]\, Y - => un1_soft_tick_21_i); - - un4_s_coarse_time_I_166 : XOR2 - port map(A => N_45, B => \s_coarse_time[24]_net_1\, Y => - I_166_3); - - un1_cpt_next_commutation_I_98 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_2_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_3[0]\); - - un1_cpt_next_commutation_I_96 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_5[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_2[0]\); - - \cpt_next_commutation[6]\ : DFN1C0 - port map(D => I_62, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[6]_net_1\); - - \previous_coarse_time_load_RNI6U45[3]\ : XNOR2 - port map(A => coarse_time_load(3), B => - \previous_coarse_time_load[3]_net_1\, Y => - previous_coarse_time_load_1_3_i); - - \latched_next_commutation[18]\ : DFN1E0P0 - port map(D => N_164, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[18]_net_1\); - - \secondary_cpt_RNO[0]\ : XNOR2 - port map(A => \un1_cpt_0[0]\, B => \secondary_cpt[0]_net_1\, - Y => \secondary_cpt_RNO[0]_net_1\); - - un9_cpt_I_80 : AND2 - port map(A => \fine_time[12]\, B => \fine_time[13]\, Y => - \DWACT_FINC_E_0[8]\); - - \latched_next_commutation[19]\ : DFN1E0P0 - port map(D => N_165, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[19]_net_1\); - - \latched_next_commutation[8]\ : DFN1E0P0 - port map(D => N_154, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[8]_net_1\); - - un4_s_coarse_time_I_73 : XOR2 - port map(A => N_111, B => \s_coarse_time[12]_net_1\, Y => - I_73_3); - - \latched_next_commutation_RNO[12]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(12), Y => N_158); - - \cpt_next_commutation[9]\ : DFN1C0 - port map(D => I_69, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[9]_net_1\); - - \s_coarse_time_RNO_0[17]\ : MX2 - port map(A => \s_coarse_time_4[17]\, B => - \s_coarse_time[17]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[17]\); - - \secondary_cpt_RNIS6VJ[10]\ : NOR3C - port map(A => \secondary_cpt[10]_net_1\, B => - \secondary_cpt[9]_net_1\, C => - secondary_cpt_c12_m6_0_a2_3, Y => - secondary_cpt_c12_m6_0_a2_5); - - \s_coarse_time_RNO_1[1]\ : NOR2B - port map(A => soft_tick_3, B => \s_coarse_time_4[1]\, Y => - un1_soft_tick_19_i); - - \p_next_commutation[18]\ : DFN1E1 - port map(D => next_commutation(18), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[18]_net_1\); - - \latched_next_commutation_RNO[19]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(19), - Y => N_165); - - \cpt_next_commutation[0]\ : DFN1C0 - port map(D => N_11, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[0]_net_1\); - - \p_next_commutation_RNI3TD5[9]\ : XNOR2 - port map(A => next_commutation(9), B => - \p_next_commutation[9]_net_1\, Y => N_119_i_i_0); - - \cpt[7]\ : DFN1C1 - port map(D => I_38_6, CLK => clk_div_0, CLR => reset_i_0, Q - => \fine_time[7]\); - - \cpt[0]\ : DFN1C1 - port map(D => N_7, CLK => clk_div_0, CLR => reset_i_0_1, Q - => \fine_time[0]\); - - \latched_next_commutation[10]\ : DFN1E0P0 - port map(D => N_156, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[10]_net_1\); - - \latched_next_commutation[0]\ : DFN1E0P0 - port map(D => N_146, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[0]_net_1\); - - \previous_coarse_time_load_RNICOJK[0]\ : NOR3C - port map(A => previous_coarse_time_load_1_1_i, B => - previous_coarse_time_load_1_0_i, C => - previous_coarse_time_load_1_NE_1, Y => - previous_coarse_time_load_1_NE_16); - - \previous_coarse_time_load_RNI0U45[0]\ : XNOR2 - port map(A => coarse_time_load(0), B => - \previous_coarse_time_load[0]_net_1\, Y => - previous_coarse_time_load_1_0_i); - - \latched_next_commutation_RNO[23]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(23), - Y => N_169); - - sirq2_RNO : OR2B - port map(A => \commutation_timer[0]_net_1\, B => N_243, Y - => N_6); - - un4_s_coarse_time_I_128 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[14]\, Y => N_71); - - un9_cpt_I_84 : XOR2 - port map(A => N_14_0, B => \fine_time[14]\, Y => I_84_4); - - \latched_next_commutation_RNI5UJA[0]\ : XNOR2 - port map(A => \s_coarse_time[0]_net_1\, B => - \latched_next_commutation[0]_net_1\, Y => - s_coarse_time_1_0_i); - - un4_s_coarse_time_I_55 : AND3 - port map(A => \DWACT_FINC_E_0[4]\, B => - \s_coarse_time[8]_net_1\, C => \s_coarse_time[9]_net_1\, - Y => N_123); - - un4_s_coarse_time_I_45 : XOR2 - port map(A => N_131, B => \s_coarse_time[8]_net_1\, Y => - I_45_4); - - \latched_next_commutation_RNO[0]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(0), Y => N_146); - - \s_coarse_time_RNO[9]\ : AO1C - port map(A => \s_coarse_time_4[9]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_22_i); - - \s_coarse_time_RNO_0[20]\ : MX2 - port map(A => \s_coarse_time_4[20]\, B => - \s_coarse_time[20]_net_1\, S => \un1_cpt[0]\, Y => - \s_coarse_time_7[20]\); - - flag_0_RNI5H3M2 : MX2 - port map(A => I_122_3, B => coarse_time_load(19), S => - \flag_0\, Y => \s_coarse_time_4[19]\); - - un9_cpt_I_55 : AND3 - port map(A => \DWACT_FINC_E[4]\, B => \fine_time[8]\, C => - \fine_time[9]\, Y => N_34); - - \previous_coarse_time_load_RNIMQJC[14]\ : XA1A - port map(A => \previous_coarse_time_load[14]_net_1\, B => - coarse_time_load(14), C => - previous_coarse_time_load_1_15_i, Y => - previous_coarse_time_load_1_NE_7); - - \previous_coarse_time_load_RNI4MAP[16]\ : NOR3C - port map(A => previous_coarse_time_load_1_17_i, B => - previous_coarse_time_load_1_16_i, C => - previous_coarse_time_load_1_NE_9, Y => - previous_coarse_time_load_1_NE_20); - - un9_cpt_I_65 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \fine_time[9]\, C => - \fine_time[10]\, Y => N_27); - - \previous_coarse_time_load_RNISL8P[24]\ : NOR3C - port map(A => previous_coarse_time_load_1_25_i, B => - previous_coarse_time_load_1_24_i, C => - previous_coarse_time_load_1_NE_13, Y => - previous_coarse_time_load_1_NE_22); - - \coarse_time[11]\ : DFN1C0 - port map(D => \s_coarse_time[11]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(11)); - - un9_cpt_I_19 : NOR2B - port map(A => \fine_time[3]\, B => \DWACT_FINC_E[0]\, Y => - N_60); - - \s_coarse_time_RNO[7]\ : AO1C - port map(A => \s_coarse_time_4[7]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_32_i); - - un1_cpt_next_commutation_I_78 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => - \cpt_next_commutation[2]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12[0]\); - - \p_next_commutation_RNI0G6L[18]\ : XA1A - port map(A => \p_next_commutation[18]_net_1\, B => - next_commutation(18), C => N_129_i_i_0, Y => - un1_commutation_timer_3_0_a2_9); - - \cpt_RNI56G2[1]\ : NOR2B - port map(A => \fine_time[1]\, B => \fine_time[4]\, Y => - \un1_cpt_0_a3_5[0]\); - - \latched_next_commutation[15]\ : DFN1E0P0 - port map(D => N_161, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[15]_net_1\); - - \latched_next_commutation_RNI0EHB[20]\ : NOR3C - port map(A => s_coarse_time_1_21_i, B => - s_coarse_time_1_20_i, C => s_coarse_time_1_NE_11, Y => - s_coarse_time_1_NE_21); - - \s_coarse_time[25]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[25]\, CLK => clk_div_3, PRE - => un1_soft_tick_31_i, CLR => un1_resetn_6_i, Q => - \s_coarse_time[25]_net_1\); - - un1_cpt_next_commutation_I_69 : XOR2 - port map(A => \cpt_next_commutation[9]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_3[0]\, Y => I_69); - - \cpt_next_commutation_RNIL94R1[13]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_11, B => - \cpt_next_commutation[12]_net_1\, C => - \cpt_next_commutation[13]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_13); - - \s_coarse_time_RNO_0[2]\ : MX2 - port map(A => \s_coarse_time_4[2]\, B => - \s_coarse_time[2]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[2]\); - - \state[0]\ : DFN1P1C1 - port map(D => N_5, CLK => clk_int, PRE => soft_tick, CLR - => rstn_i, Q => \state[0]_net_1\); - - \s_coarse_time_RNO_1[0]\ : NOR2A - port map(A => soft_tick_3, B => \s_coarse_time_4[0]\, Y => - un1_soft_tick_25_i); - - un4_s_coarse_time_I_223 : AND3 - port map(A => \DWACT_FINC_E[24]\, B => \DWACT_FINC_E[23]\, - C => \DWACT_FINC_E[27]\, Y => N_4); - - \state_RNO[0]\ : AOI1B - port map(A => flag_1_sqmuxa_i_o3_14, B => - flag_1_sqmuxa_i_o3_13, C => \state[0]_net_1\, Y => N_5); - - \s_coarse_time[1]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[1]\, CLK => clk_div_3, PRE - => un1_soft_tick_19_i, CLR => un1_resetn_33_i, Q => - \s_coarse_time[1]_net_1\); - - \secondary_cpt[1]\ : DFN1E0C1 - port map(D => secondary_cpt_n1, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[1]_net_1\); - - \cpt_next_commutation[4]\ : DFN1C0 - port map(D => I_58, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[4]_net_1\); - - \commutation_timer_RNINQD9E[0]\ : AO1 - port map(A => un1_commutation_timer_3_0_a2_30, B => - s_coarse_time_1_NE, C => \commutation_timer[0]_net_1\, Y - => un1_commutation_timer_3_0); - - \previous_coarse_time_load[8]\ : DFN1E0C0 - port map(D => coarse_time_load(8), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[8]_net_1\); - - un3_grspw_tick_1 : OR2A - port map(A => rstn, B => soft_tick_0, Y => reset_i_0_1); - - \s_coarse_time_RNO_3[31]\ : NOR3A - port map(A => \un1_cpt_0[0]\, B => s_coarse_time38, C => - \s_coarse_time[31]_net_1\, Y => \s_coarse_time_i_m[31]\); - - \s_coarse_time_RNO_1[10]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[10]\, Y - => un1_soft_tick_22_i); - - \s_coarse_time_RNO_1[26]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[26]\, Y - => un1_soft_tick_20_i); - - \s_coarse_time_RNO_0[9]\ : MX2 - port map(A => \s_coarse_time_4[9]\, B => - \s_coarse_time[9]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[9]\); - - \latched_next_commutation_RNIR1T2[27]\ : XNOR2 - port map(A => \s_coarse_time[27]_net_1\, B => - \latched_next_commutation[27]_net_1\, Y => - s_coarse_time_1_27_i); - - un1_cpt_next_commutation_I_103 : AND2 - port map(A => \cpt_next_commutation[8]_net_1\, B => - \cpt_next_commutation[9]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_3[0]\); - - \latched_next_commutation_RNI72KA[1]\ : XNOR2 - port map(A => \s_coarse_time[1]_net_1\, B => - \latched_next_commutation[1]_net_1\, Y => - s_coarse_time_1_1_i); - - \commutation_timer_RNI3EI8[0]\ : NOR2B - port map(A => un1_p_clk_div, B => - \commutation_timer[0]_net_1\, Y => - \commutation_timer_RNI3EI8[0]_net_1\); - - \s_coarse_time_RNO_1[29]\ : NOR2B - port map(A => soft_tick_0, B => \s_coarse_time_4[29]\, Y - => un1_soft_tick_29_i); - - \secondary_cpt_RNO[4]\ : XOR2 - port map(A => secondary_cpt_c3, B => - \secondary_cpt[4]_net_1\, Y => secondary_cpt_n4); - - \previous_coarse_time_load[0]\ : DFN1E0C0 - port map(D => coarse_time_load(0), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[0]_net_1\); - - un4_s_coarse_time_I_76 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => \DWACT_FINC_E_0[7]\, - C => \s_coarse_time[12]_net_1\, Y => N_108); - - un4_s_coarse_time_I_196 : XOR2 - port map(A => N_24_0, B => \s_coarse_time[27]_net_1\, Y => - I_196_3); - - \s_coarse_time[8]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[8]\, CLK => clk_div_3, PRE - => un1_soft_tick_i, CLR => un1_resetn_21_i, Q => - \s_coarse_time[8]_net_1\); - - \p_next_commutation[21]\ : DFN1E1 - port map(D => next_commutation(21), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[21]_net_1\); - - \cpt_next_commutation[12]\ : DFN1C0 - port map(D => I_57, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[12]_net_1\); - - \coarse_time[29]\ : DFN1C0 - port map(D => \s_coarse_time[29]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(29)); - - \coarse_time[17]\ : DFN1C0 - port map(D => \s_coarse_time[17]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(17)); - - \s_coarse_time_RNO_0[16]\ : MX2 - port map(A => \s_coarse_time_4[16]\, B => - \s_coarse_time[16]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[16]\); - - un1_cpt_next_commutation_I_102 : AND2 - port map(A => \cpt_next_commutation[2]_net_1\, B => - \cpt_next_commutation[3]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1[0]\); - - \previous_coarse_time_load[13]\ : DFN1E0C0 - port map(D => coarse_time_load(13), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[13]_net_1\); - - \s_coarse_time_RNO[28]\ : AO1C - port map(A => \s_coarse_time_4[28]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_15_i); - - \secondary_cpt_RNO[11]\ : XOR2 - port map(A => secondary_cpt_c10, B => - \secondary_cpt[11]_net_1\, Y => secondary_cpt_n11); - - \p_next_commutation_RNI0F4L[10]\ : XA1A - port map(A => \p_next_commutation[10]_net_1\, B => - next_commutation(10), C => N_121_i_i_0, Y => - un1_commutation_timer_3_0_a2_5); - - \secondary_cpt_RNIKVP8[2]\ : NOR3C - port map(A => \secondary_cpt[0]_net_1\, B => - \secondary_cpt[1]_net_1\, C => \secondary_cpt[2]_net_1\, - Y => secondary_cpt_c2); - - \secondary_cpt[10]\ : DFN1E0C1 - port map(D => secondary_cpt_n10, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[10]_net_1\); - - \s_coarse_time_RNO_0[19]\ : MX2 - port map(A => \s_coarse_time_4[19]\, B => - \s_coarse_time[19]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[19]\); - - \cpt_next_commutation[7]\ : DFN1C0 - port map(D => I_64, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[7]_net_1\); - - \s_coarse_time[11]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[11]\, CLK => clk_div_2, PRE - => un1_soft_tick_7_i, CLR => un1_resetn_28_i, Q => - \s_coarse_time[11]_net_1\); - - \p_next_commutation_RNISF2V8[0]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_25, B => - un1_commutation_timer_3_0_a2_24, C => - un1_commutation_timer_3_0_a2_29, Y => - un1_commutation_timer_3_0_a2_30); - - \s_coarse_time[17]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[17]\, CLK => clk_div_2, PRE - => un1_soft_tick_26_i, CLR => un1_resetn_14_i, Q => - \s_coarse_time[17]_net_1\); - - \secondary_cpt[5]\ : DFN1E0C1 - port map(D => secondary_cpt_n5, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[5]_net_1\); - - \previous_coarse_time_load[7]\ : DFN1E0C0 - port map(D => coarse_time_load(7), CLK => clk_div_2, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[7]_net_1\); - - \s_coarse_time_RNO_0[28]\ : MX2 - port map(A => \s_coarse_time_4[28]\, B => - \s_coarse_time[28]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[28]\); - - Clk_divider0 : Clk_divider - port map(reset_i_0_1 => reset_i_0_1, clk49_152MHz_c => - clk49_152MHz_c, reset_i_0_0 => reset_i_0_0, - clk49_152MHz_c_0 => clk49_152MHz_c_0, clk_div_0 => - clk_div_0, clk_div_1 => clk_div_1, clk_div_2 => clk_div_2, - clk_int => clk_int, clk_div_3 => clk_div_3); - - \coarse_time[0]\ : DFN1C0 - port map(D => \s_coarse_time[0]_net_1\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time[0]_net_1\); - - un1_cpt_next_commutation_I_89 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_10[0]\, B => - \cpt_next_commutation[12]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_5[0]\); - - \latched_next_commutation_RNO[22]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(22), - Y => N_168); - - \coarse_time[16]\ : DFN1C0 - port map(D => \s_coarse_time[16]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(16)); - - \cpt_next_commutation[15]\ : DFN1C0 - port map(D => I_67, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[15]_net_1\); - - \coarse_time[6]\ : DFN1C0 - port map(D => \s_coarse_time[6]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(6)); - - \secondary_cpt[6]\ : DFN1E0C1 - port map(D => secondary_cpt_n6, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[6]_net_1\); - - \latched_next_commutation_RNO[29]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(29), - Y => N_175); - - \latched_next_commutation_RNI0C3A5[10]\ : OR2B - port map(A => s_coarse_time_1_NE_29, B => - s_coarse_time_1_NE_28, Y => s_coarse_time_1_NE_0); - - \cpt_next_commutation_RNI7FC61[9]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_7, B => - \cpt_next_commutation[8]_net_1\, C => - \cpt_next_commutation[9]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_9); - - \cpt_RNI7LQ6[11]\ : NOR2B - port map(A => \fine_time[11]\, B => \fine_time[14]\, Y => - \un1_cpt_0_a3_1[0]\); - - \p_next_commutation_RNIPHIA[31]\ : XNOR2 - port map(A => next_commutation(31), B => - \p_next_commutation[31]_net_1\, Y => N_141_i_i_0); - - un9_cpt_I_5 : XOR2 - port map(A => \fine_time[0]\, B => \fine_time[1]\, Y => - I_5_9); - - \coarse_time[14]\ : DFN1C0 - port map(D => \s_coarse_time[14]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(14)); - - \latched_next_commutation_RNIDEKA[4]\ : XNOR2 - port map(A => \s_coarse_time[4]_net_1\, B => - \latched_next_commutation[4]_net_1\, Y => - s_coarse_time_1_4_i); - - \coarse_time[2]\ : DFN1C0 - port map(D => \s_coarse_time[2]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(2)); - - \secondary_cpt_RNIRVR5[2]\ : NOR2B - port map(A => \secondary_cpt[2]_net_1\, B => - \secondary_cpt[3]_net_1\, Y => s_coarse_time38lto5_0); - - \coarse_time[8]\ : DFN1C0 - port map(D => \s_coarse_time[8]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(8)); - - un1_cpt_next_commutation_I_67 : XOR2 - port map(A => \cpt_next_commutation[15]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_6[0]\, Y => I_67); - - \s_coarse_time_RNO_2[31]\ : OR2 - port map(A => s_coarse_time38, B => \un1_cpt_0[0]\, Y => - un1_s_coarse_time_3_m_0); - - un4_s_coarse_time_I_48 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E_0[4]\); - - flag_RNIHV8D2 : MX2 - port map(A => I_77_3, B => coarse_time_load(13), S => - \flag\, Y => \s_coarse_time_4[13]\); - - \secondary_cpt_RNIHVLE[4]\ : NOR2B - port map(A => secondary_cpt_c3, B => - \secondary_cpt[4]_net_1\, Y => secondary_cpt_c4); - - \cpt_next_commutation_RNISUMV[7]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_5, B => - \cpt_next_commutation[6]_net_1\, C => - \cpt_next_commutation[7]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_7); - - \p_next_commutation_RNI4MRA[8]\ : XA1A - port map(A => \p_next_commutation[8]_net_1\, B => - next_commutation(8), C => N_119_i_i_0, Y => - un1_commutation_timer_3_0_a2_4); - - \latched_next_commutation_RNIC1AL[8]\ : XA1A - port map(A => \latched_next_commutation[8]_net_1\, B => - \s_coarse_time[8]_net_1\, C => s_coarse_time_1_9_i, Y => - s_coarse_time_1_NE_4); - - \secondary_cpt[16]\ : DFN1E0C1 - port map(D => secondary_cpt_n16, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[16]_net_1\); - - \s_coarse_time_RNO_1[18]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[18]\, Y - => un1_soft_tick_27_i); - - \p_next_commutation_RNIJ9IA[20]\ : XNOR2 - port map(A => next_commutation(20), B => - \p_next_commutation[20]_net_1\, Y => N_130_i_i_0); - - un4_s_coarse_time_I_56 : XOR2 - port map(A => N_123, B => \s_coarse_time[10]_net_1\, Y => - I_56_5); - - \s_coarse_time[6]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[6]\, CLK => clk_div_3, PRE - => un1_soft_tick_10_i, CLR => un1_resetn_13_i, Q => - \s_coarse_time[6]_net_1\); - - \s_coarse_time_RNO[18]\ : AO1C - port map(A => \s_coarse_time_4[18]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_4_i); - - \cpt[3]\ : DFN1C1 - port map(D => I_13_13, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[3]\); - - \cpt_RNIQOOH[4]\ : NOR3C - port map(A => flag_1_sqmuxa_i_o3_6, B => - flag_1_sqmuxa_i_o3_5, C => flag_1_sqmuxa_i_o3_12, Y => - flag_1_sqmuxa_i_o3_14); - - un4_s_coarse_time_I_149 : AND3 - port map(A => \s_coarse_time[0]_net_1\, B => - \s_coarse_time[1]_net_1\, C => \s_coarse_time[2]_net_1\, - Y => \DWACT_FINC_E[34]\); - - \cpt_next_commutation[14]\ : DFN1C0 - port map(D => I_65, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[14]_net_1\); - - un1_cpt_next_commutation_I_64 : XOR2 - port map(A => \cpt_next_commutation[7]_net_1\, B => - \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => I_64); - - \s_coarse_time_RNO_0[27]\ : MX2 - port map(A => \s_coarse_time_4[27]\, B => - \s_coarse_time[27]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[27]\); - - \secondary_cpt[3]\ : DFN1E0C1 - port map(D => secondary_cpt_n3, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[3]_net_1\); - - un9_cpt_I_12 : AND3 - port map(A => \fine_time[0]\, B => \fine_time[1]\, C => - \fine_time[2]\, Y => N_65); - - \s_coarse_time[29]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[29]\, CLK => clk_div_3, PRE - => un1_soft_tick_29_i, CLR => un1_resetn_11_i, Q => - \s_coarse_time[29]_net_1\); - - flag_0_RNIFD333 : MX2 - port map(A => I_210_3, B => coarse_time_load(29), S => - \flag_0\, Y => \s_coarse_time_4[29]\); - - \cpt_RNILFL4[13]\ : NOR2 - port map(A => \fine_time[13]\, B => \fine_time[1]\, Y => - flag_1_sqmuxa_i_o3_4); - - \secondary_cpt_RNO[2]\ : AX1C - port map(A => \secondary_cpt[0]_net_1\, B => - \secondary_cpt[1]_net_1\, C => \secondary_cpt[2]_net_1\, - Y => secondary_cpt_n2); - - \latched_next_commutation_RNID9S2[12]\ : XNOR2 - port map(A => \s_coarse_time[12]_net_1\, B => - \latched_next_commutation[12]_net_1\, Y => - s_coarse_time_1_12_i); - - \p_next_commutation_RNIH9IA[11]\ : XNOR2 - port map(A => next_commutation(11), B => - \p_next_commutation[11]_net_1\, Y => N_121_i_i_0); - - un4_s_coarse_time_I_142 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[16]\, Y => N_61); - - \secondary_cpt_RNO[15]\ : XOR2 - port map(A => secondary_cpt_c14, B => - \secondary_cpt[15]_net_1\, Y => secondary_cpt_n15); - - un9_cpt_I_13 : XOR2 - port map(A => N_65, B => \fine_time[3]\, Y => I_13_13); - - \p_next_commutation_RNIRCD5[5]\ : XNOR2 - port map(A => next_commutation(5), B => - \p_next_commutation[5]_net_1\, Y => N_115_i_i_0); - - \cpt_next_commutation_RNICCOG1[11]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_9, B => - \cpt_next_commutation[10]_net_1\, C => - \cpt_next_commutation[11]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_11); - - \coarse_time[12]\ : DFN1C0 - port map(D => \s_coarse_time[12]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(12)); - - \cpt_next_commutation_RNIAMQD2[15]\ : OR2B - port map(A => sirq2_1_sqmuxa_i_a2_15, B => un1_p_clk_div, Y - => N_243); - - \latched_next_commutation_RNICFP5[24]\ : XA1A - port map(A => \latched_next_commutation[24]_net_1\, B => - \s_coarse_time[24]_net_1\, C => s_coarse_time_1_25_i, Y - => s_coarse_time_1_NE_12); - - \p_next_commutation[25]\ : DFN1E1 - port map(D => next_commutation(25), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[25]_net_1\); - - \cpt_next_commutation[3]\ : DFN1C0 - port map(D => I_54, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[3]_net_1\); - - \p_next_commutation_RNIJDIA[12]\ : XNOR2 - port map(A => next_commutation(12), B => - \p_next_commutation[12]_net_1\, Y => N_122_i_i_0); - - \s_coarse_time_RNO_0[4]\ : MX2 - port map(A => \s_coarse_time_4[4]\, B => - \s_coarse_time[4]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[4]\); - - \previous_coarse_time_load_RNIGHA6[17]\ : XNOR2 - port map(A => coarse_time_load(17), B => - \previous_coarse_time_load[17]_net_1\, Y => - previous_coarse_time_load_1_17_i); - - \latched_next_commutation_RNI4H9L[6]\ : XA1A - port map(A => \latched_next_commutation[6]_net_1\, B => - \s_coarse_time[6]_net_1\, C => s_coarse_time_1_7_i, Y => - s_coarse_time_1_NE_3); - - \p_next_commutation[16]\ : DFN1E1 - port map(D => next_commutation(16), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[16]_net_1\); - - \previous_coarse_time_load[23]\ : DFN1E0C0 - port map(D => coarse_time_load(23), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[23]_net_1\); - - flag_RNIALCM2 : MX2 - port map(A => I_129_3, B => coarse_time_load(20), S => - \flag\, Y => \s_coarse_time_4[20]\); - - \s_coarse_time_RNO_0[6]\ : MX2 - port map(A => \s_coarse_time_4[6]\, B => - \s_coarse_time[6]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[6]\); - - \latched_next_commutation_RNIT5T2[28]\ : XNOR2 - port map(A => \s_coarse_time[28]_net_1\, B => - \latched_next_commutation[28]_net_1\, Y => - s_coarse_time_1_28_i); - - un1_cpt_next_commutation_I_87 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_3[0]\, Y => - \DWACT_ADD_CI_0_g_array_11_1[0]\); - - un4_s_coarse_time_I_115 : XOR2 - port map(A => N_81, B => \s_coarse_time[18]_net_1\, Y => - I_115_3); - - \s_coarse_time_RNO_1[17]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[17]\, Y - => un1_soft_tick_26_i); - - un4_s_coarse_time_I_87 : AND3 - port map(A => \s_coarse_time[12]_net_1\, B => - \s_coarse_time[13]_net_1\, C => \s_coarse_time[14]_net_1\, - Y => \DWACT_FINC_E[9]\); - - \previous_coarse_time_load_RNIEU45[7]\ : XNOR2 - port map(A => coarse_time_load(7), B => - \previous_coarse_time_load[7]_net_1\, Y => - previous_coarse_time_load_1_7_i); - - \cpt_RNI4U57[15]\ : NOR3C - port map(A => \fine_time[2]\, B => \fine_time[15]\, C => - \un1_cpt_0_a3_3[0]\, Y => \un1_cpt_0_a3_10[0]\); - - \previous_coarse_time_load[16]\ : DFN1E0C0 - port map(D => coarse_time_load(16), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[16]_net_1\); - - un1_cpt_next_commutation_I_99 : AND2 - port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_2[0]\, Y => - \DWACT_ADD_CI_0_pog_array_2[0]\); - - \s_coarse_time_RNO_1[9]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[9]\, Y => - un1_soft_tick_30_i); - - \s_coarse_time_RNO[5]\ : AO1C - port map(A => \s_coarse_time_4[5]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_26_i); - - \s_coarse_time[31]\ : DFN1P1C1 - port map(D => \s_coarse_time_10_iv[31]\, CLK => clk_div_3, - PRE => un1_resetn_2_i, CLR => un1_soft_tick_44_i, Q => - \s_coarse_time[31]_net_1\); - - \coarse_time[5]\ : DFN1C0 - port map(D => \s_coarse_time[5]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(5)); - - \p_next_commutation[6]\ : DFN1E1 - port map(D => next_commutation(6), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[6]_net_1\); - - \s_coarse_time_RNO[6]\ : AO1C - port map(A => \s_coarse_time_4[6]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_13_i); - - \p_next_commutation[12]\ : DFN1E1 - port map(D => next_commutation(12), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[12]_net_1\); - - \latched_next_commutation[1]\ : DFN1E0P0 - port map(D => N_147, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[1]_net_1\); - - \latched_next_commutation_RNIKG8L[2]\ : XA1A - port map(A => \latched_next_commutation[2]_net_1\, B => - \s_coarse_time[2]_net_1\, C => s_coarse_time_1_3_i, Y => - s_coarse_time_1_NE_1); - - un4_s_coarse_time_I_143 : XOR2 - port map(A => N_61, B => \s_coarse_time[22]_net_1\, Y => - I_143_3); - - GND_i_0 : GND - port map(Y => GND_0); - - \previous_coarse_time_load_RNICC2G1[10]\ : NOR3C - port map(A => previous_coarse_time_load_1_NE_5, B => - previous_coarse_time_load_1_NE_4, C => - previous_coarse_time_load_1_NE_19, Y => - previous_coarse_time_load_1_NE_25); - - un1_cpt_next_commutation_I_84 : NOR2B - port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => - \cpt_next_commutation[1]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_1[0]\); - - \latched_next_commutation_RNO[7]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(7), Y => N_153); - - un4_s_coarse_time_I_91 : XOR2 - port map(A => N_98, B => \s_coarse_time[15]_net_1\, Y => - I_91_3); - - \latched_next_commutation[21]\ : DFN1E0P0 - port map(D => N_167, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[21]_net_1\); - - \cpt_next_commutation[1]\ : DFN1C0 - port map(D => I_63, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[1]_net_1\); - - un4_s_coarse_time_I_9 : XOR2 - port map(A => N_157, B => \s_coarse_time[2]_net_1\, Y => - I_9_8); - - flag_0 : DFN1E0C1 - port map(D => flag_1, CLK => clk_div_0, CLR => reset_i_0_0, - E => flag_1_sqmuxa_1, Q => \flag_0\); - - un4_s_coarse_time_I_101 : AND2 - port map(A => \s_coarse_time[15]_net_1\, B => - \s_coarse_time[16]_net_1\, Y => \DWACT_FINC_E[11]\); - - \latched_next_commutation_RNO[11]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(11), Y => N_157_0); - - \cpt_RNISBL4[9]\ : NOR2B - port map(A => \fine_time[9]\, B => \fine_time[12]\, Y => - \un1_cpt_0_a3_7[0]\); - - un4_s_coarse_time_I_59 : AND3 - port map(A => \s_coarse_time[6]_net_1\, B => - \s_coarse_time[7]_net_1\, C => \s_coarse_time[8]_net_1\, - Y => \DWACT_FINC_E[5]\); - - \s_coarse_time_RNO_0[26]\ : MX2 - port map(A => \s_coarse_time_4[26]\, B => - \s_coarse_time[26]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[26]\); - - \s_coarse_time_RNO[4]\ : AO1C - port map(A => \s_coarse_time_4[4]\, B => soft_tick_2, C => - rstn, Y => un1_resetn_17_i); - - \coarse_time[3]\ : DFN1C0 - port map(D => \s_coarse_time[3]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(3)); - - un9_cpt_I_51 : NOR2B - port map(A => \fine_time[8]\, B => \DWACT_FINC_E[4]\, Y => - N_37); - - \cpt_RNIB5R6[14]\ : NOR2 - port map(A => \fine_time[14]\, B => \fine_time[15]\, Y => - flag_1_sqmuxa_i_o3_1); - - un4_s_coarse_time_I_217 : XOR2 - port map(A => N_9_0, B => \s_coarse_time[30]_net_1\, Y => - I_217_1); - - \latched_next_commutation_RNIKVP5[26]\ : XA1A - port map(A => \latched_next_commutation[26]_net_1\, B => - \s_coarse_time[26]_net_1\, C => s_coarse_time_1_27_i, Y - => s_coarse_time_1_NE_13); - - \secondary_cpt_RNO[16]\ : AX1C - port map(A => \secondary_cpt[15]_net_1\, B => - secondary_cpt_c14, C => \secondary_cpt[16]_net_1\, Y => - secondary_cpt_n16); - - \s_coarse_time_RNO_0[29]\ : MX2 - port map(A => \s_coarse_time_4[29]\, B => - \s_coarse_time[29]_net_1\, S => \un1_cpt_0[0]\, Y => - \s_coarse_time_7[29]\); - - \s_coarse_time[10]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[10]\, CLK => clk_div_2, PRE - => un1_soft_tick_22_i, CLR => un1_resetn_9_i, Q => - \s_coarse_time[10]_net_1\); - - un4_s_coarse_time_I_94 : AND2 - port map(A => \DWACT_FINC_E_0[7]\, B => \DWACT_FINC_E[9]\, - Y => \DWACT_FINC_E[10]\); - - \latched_next_commutation_RNI07JB[28]\ : NOR3C - port map(A => s_coarse_time_1_29_i, B => - s_coarse_time_1_28_i, C => s_coarse_time_1_NE_15, Y => - s_coarse_time_1_NE_23); - - \cpt_next_commutation_RNI27G52[15]\ : NOR3A - port map(A => sirq2_1_sqmuxa_i_a2_13, B => - \cpt_next_commutation[14]_net_1\, C => - \cpt_next_commutation[15]_net_1\, Y => - sirq2_1_sqmuxa_i_a2_15); - - un4_s_coarse_time_I_24 : XOR2 - port map(A => N_146_0, B => \s_coarse_time[5]_net_1\, Y => - I_24_9); - - un3_grspw_tick : OR2A - port map(A => rstn, B => soft_tick_0, Y => reset_i_0); - - un1_cpt_next_commutation_I_65 : XOR2 - port map(A => \cpt_next_commutation[14]_net_1\, B => - \DWACT_ADD_CI_0_g_array_11_2[0]\, Y => I_65); - - flag_RNIQ9VA1 : MX2 - port map(A => I_24_9, B => coarse_time_load(5), S => \flag\, - Y => \s_coarse_time_4[5]\); - - \cpt[14]\ : DFN1C1 - port map(D => I_84_4, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[14]\); - - \p_next_commutation_RNI16JA[27]\ : XNOR2 - port map(A => next_commutation(27), B => - \p_next_commutation[27]_net_1\, Y => N_137_i_i_0); - - un4_s_coarse_time_I_37 : AND3 - port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\, - C => \s_coarse_time[6]_net_1\, Y => N_136); - - \s_coarse_time[23]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[23]\, CLK => clk_div_3, PRE - => un1_soft_tick_2_i, CLR => un1_resetn_16_i, Q => - \s_coarse_time[23]_net_1\); - - \s_coarse_time[28]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[28]\, CLK => clk_div_3, PRE - => un1_soft_tick_15_i, CLR => un1_resetn_15_i, Q => - \s_coarse_time[28]_net_1\); - - \s_coarse_time_RNO_1[16]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[16]\, Y - => un1_soft_tick_17_i); - - \cpt[16]\ : DFN1C1 - port map(D => \cpt_5[16]\, CLK => clk_div_0, CLR => - reset_i_0_1, Q => \fine_time[16]\); - - \secondary_cpt[4]\ : DFN1E0C1 - port map(D => secondary_cpt_n4, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[4]_net_1\); - - \latched_next_commutation[31]\ : DFN1E0P0 - port map(D => N_177, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[31]_net_1\); - - un1_cpt_next_commutation_I_97 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \cpt_next_commutation[4]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_1[0]\); - - flag_RNIGMB41 : MX2 - port map(A => I_20_8, B => coarse_time_load(4), S => \flag\, - Y => \s_coarse_time_4[4]\); - - flag_0_RNIIU4V2 : MX2 - port map(A => I_186_3, B => coarse_time_load(26), S => - \flag_0\, Y => \s_coarse_time_4[26]\); - - \s_coarse_time_RNO_1[19]\ : NOR2B - port map(A => soft_tick_1, B => \s_coarse_time_4[19]\, Y - => un1_soft_tick_1_i); - - \coarse_time[19]\ : DFN1C0 - port map(D => \s_coarse_time[19]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(19)); - - \p_next_commutation_RNIRTIA[16]\ : XNOR2 - port map(A => next_commutation(16), B => - \p_next_commutation[16]_net_1\, Y => N_126_i_i_0); - - \previous_coarse_time_load[26]\ : DFN1E0C0 - port map(D => coarse_time_load(26), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[26]_net_1\); - - \previous_coarse_time_load_RNIC1A6[15]\ : XNOR2 - port map(A => coarse_time_load(15), B => - \previous_coarse_time_load[15]_net_1\, Y => - previous_coarse_time_load_1_15_i); - - \secondary_cpt_RNILHCE[8]\ : NOR3A - port map(A => s_coarse_time38lto16_4, B => - \secondary_cpt[8]_net_1\, C => \secondary_cpt[7]_net_1\, - Y => s_coarse_time38lto16_7); - - un4_s_coarse_time_I_159 : AND3 - port map(A => \s_coarse_time[21]_net_1\, B => - \s_coarse_time[22]_net_1\, C => \s_coarse_time[23]_net_1\, - Y => \DWACT_FINC_E[17]\); - - \previous_coarse_time_load_RNI2RKC[26]\ : XA1A - port map(A => \previous_coarse_time_load[26]_net_1\, B => - coarse_time_load(26), C => - previous_coarse_time_load_1_27_i, Y => - previous_coarse_time_load_1_NE_13); - - \latched_next_commutation_RNID5S2[20]\ : XNOR2 - port map(A => \s_coarse_time[20]_net_1\, B => - \latched_next_commutation[20]_net_1\, Y => - s_coarse_time_1_20_i); - - \p_next_commutation[29]\ : DFN1E1 - port map(D => next_commutation(29), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[29]_net_1\); - - un1_cpt_next_commutation_I_94 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_2[0]\, B => - \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_11[0]\); - - \coarse_time[9]\ : DFN1C0 - port map(D => \s_coarse_time[9]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(9)); - - \previous_coarse_time_load_RNI6RLC[18]\ : XA1A - port map(A => \previous_coarse_time_load[18]_net_1\, B => - coarse_time_load(18), C => - previous_coarse_time_load_1_19_i, Y => - previous_coarse_time_load_1_NE_9); - - \secondary_cpt[0]\ : DFN1C1 - port map(D => \secondary_cpt_RNO[0]_net_1\, CLK => clk_int, - CLR => reset_i_0, Q => \secondary_cpt[0]_net_1\); - - \coarse_time[20]\ : DFN1C0 - port map(D => \s_coarse_time[20]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(20)); - - un4_s_coarse_time_I_152 : AND3 - port map(A => \DWACT_FINC_E[34]\, B => \DWACT_FINC_E[2]\, C - => \DWACT_FINC_E[5]\, Y => \DWACT_FINC_E[29]\); - - un9_cpt_I_83 : AND3 - port map(A => \DWACT_FINC_E[6]\, B => \DWACT_FINC_E[7]\, C - => \DWACT_FINC_E_0[8]\, Y => N_14_0); - - \previous_coarse_time_load[18]\ : DFN1E0C0 - port map(D => coarse_time_load(18), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[18]_net_1\); - - \latched_next_commutation_RNIFDS2[13]\ : XNOR2 - port map(A => \s_coarse_time[13]_net_1\, B => - \latched_next_commutation[13]_net_1\, Y => - s_coarse_time_1_13_i); - - \previous_coarse_time_load[15]\ : DFN1E0C0 - port map(D => coarse_time_load(15), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[15]_net_1\); - - \latched_next_commutation_RNI4NO5[30]\ : XA1A - port map(A => \latched_next_commutation[30]_net_1\, B => - \s_coarse_time[30]_net_1\, C => s_coarse_time_1_31_i, Y - => s_coarse_time_1_NE_15); - - \s_coarse_time_RNO[26]\ : AO1C - port map(A => \s_coarse_time_4[26]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_8_i); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \p_next_commutation_RNIVKD5[7]\ : XNOR2 - port map(A => next_commutation(7), B => - \p_next_commutation[7]_net_1\, Y => N_117_i_i_0); - - \s_coarse_time_RNO_1[8]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[8]\, Y => - un1_soft_tick_i); - - flag_0_RNINIK53 : MX2 - port map(A => I_224_1, B => coarse_time_load(31), S => - \flag_0\, Y => \s_coarse_time_4[31]\); - - \p_next_commutation_RNITTIA[25]\ : XNOR2 - port map(A => next_commutation(25), B => - \p_next_commutation[25]_net_1\, Y => N_135_i_i_0); - - \p_next_commutation_RNIGNNK2[24]\ : NOR3C - port map(A => un1_commutation_timer_3_0_a2_13, B => - un1_commutation_timer_3_0_a2_12, C => - un1_commutation_timer_3_0_a2_23, Y => - un1_commutation_timer_3_0_a2_27); - - \latched_next_commutation_RNO[21]\ : OR2A - port map(A => s_coarse_time_1_NE, B => next_commutation(21), - Y => N_167); - - un4_s_coarse_time_I_139 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => - \s_coarse_time[21]_net_1\, Y => \DWACT_FINC_E[16]\); - - \s_coarse_time[15]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[15]\, CLK => clk_div_2, PRE - => un1_soft_tick_3_i, CLR => un1_resetn_24_i, Q => - \s_coarse_time[15]_net_1\); - - \latched_next_commutation[22]\ : DFN1E0P0 - port map(D => N_168, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3_0, Q => - \latched_next_commutation[22]_net_1\); - - un1_cpt_next_commutation_I_63 : XOR2 - port map(A => \cpt_next_commutation[1]_net_1\, B => - \DWACT_ADD_CI_0_TMP[0]\, Y => I_63); - - \p_next_commutation[23]\ : DFN1E1 - port map(D => next_commutation(23), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[23]_net_1\); - - \coarse_time[28]\ : DFN1C0 - port map(D => \s_coarse_time[28]_net_1\, CLK => lclk_c, CLR - => rstn, Q => coarse_time(28)); - - \cpt_RNIAI57[6]\ : NOR3C - port map(A => \fine_time[8]\, B => \fine_time[6]\, C => - \un1_cpt_0_a3_7[0]\, Y => \un1_cpt_0_a3_12[0]\); - - \s_coarse_time[30]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[30]\, CLK => clk_div_3, PRE - => un1_soft_tick_16_i, CLR => un1_resetn_7_i, Q => - \s_coarse_time[30]_net_1\); - - un1_cpt_next_commutation_I_74 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \DWACT_ADD_CI_0_pog_array_2_1[0]\, Y => - \DWACT_ADD_CI_0_g_array_10[0]\); - - un4_s_coarse_time_I_132 : AND3 - port map(A => \s_coarse_time[18]_net_1\, B => - \s_coarse_time[19]_net_1\, C => \s_coarse_time[20]_net_1\, - Y => \DWACT_FINC_E[15]\); - - \previous_coarse_time_load_RNIAH96[23]\ : XNOR2 - port map(A => coarse_time_load(23), B => - \previous_coarse_time_load[23]_net_1\, Y => - previous_coarse_time_load_1_23_i); - - \s_coarse_time_RNO_0[7]\ : MX2 - port map(A => \s_coarse_time_4[7]\, B => - \s_coarse_time[7]_net_1\, S => \un1_cpt_1[0]\, Y => - \s_coarse_time_7[7]\); - - un4_s_coarse_time_I_114 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[10]\, - C => \DWACT_FINC_E[12]\, Y => N_81); - - \cpt_RNI36G2[0]\ : NOR2B - port map(A => \fine_time[0]\, B => \fine_time[3]\, Y => - \un1_cpt_0_a3_8[0]\); - - \s_coarse_time_RNO[24]\ : AO1C - port map(A => \s_coarse_time_4[24]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_19_i); - - un4_s_coarse_time_I_155 : AND3 - port map(A => \DWACT_FINC_E[29]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[33]\, Y => N_52); - - \latched_next_commutation_RNIR5T2[19]\ : XNOR2 - port map(A => \s_coarse_time[19]_net_1\, B => - \latched_next_commutation[19]_net_1\, Y => - s_coarse_time_1_19_i); - - \secondary_cpt_RNINVDQ[8]\ : NOR3C - port map(A => \secondary_cpt[7]_net_1\, B => - secondary_cpt_c6, C => \secondary_cpt[8]_net_1\, Y => - secondary_cpt_c8); - - \p_next_commutation_RNILDIA[21]\ : XNOR2 - port map(A => next_commutation(21), B => - \p_next_commutation[21]_net_1\, Y => N_131_i_i_0); - - \secondary_cpt_RNO[10]\ : AX1C - port map(A => \secondary_cpt[9]_net_1\, B => - secondary_cpt_c8, C => \secondary_cpt[10]_net_1\, Y => - secondary_cpt_n10); - - \p_next_commutation_RNIN4D5[3]\ : XNOR2 - port map(A => next_commutation(3), B => - \p_next_commutation[3]_net_1\, Y => N_113_i_i_0); - - \s_coarse_time[26]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[26]\, CLK => clk_div_3, PRE - => un1_soft_tick_20_i, CLR => un1_resetn_8_i, Q => - \s_coarse_time[26]_net_1\); - - \cpt[11]\ : DFN1C1 - port map(D => I_66_6, CLK => clk_div_0, CLR => reset_i_0_1, - Q => \fine_time[11]\); - - \latched_next_commutation_RNI4VO5[22]\ : XA1A - port map(A => \latched_next_commutation[22]_net_1\, B => - \s_coarse_time[22]_net_1\, C => s_coarse_time_1_23_i, Y - => s_coarse_time_1_NE_11); - - VCC_i : VCC - port map(Y => \VCC\); - - \s_coarse_time_RNO[16]\ : AO1C - port map(A => \s_coarse_time_4[16]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_27_i); - - \s_coarse_time_RNO[31]\ : NOR2A - port map(A => soft_tick_0, B => \s_coarse_time_4[31]\, Y - => un1_soft_tick_44_i); - - un4_s_coarse_time_I_210 : XOR2 - port map(A => N_14, B => \s_coarse_time[29]_net_1\, Y => - I_210_3); - - \secondary_cpt_RNIGHG8[10]\ : NOR2 - port map(A => \secondary_cpt[9]_net_1\, B => - \secondary_cpt[10]_net_1\, Y => s_coarse_time38lto16_4); - - un9_cpt_I_77 : XOR2 - port map(A => N_19_0, B => \fine_time[13]\, Y => I_77_4); - - \latched_next_commutation_RNO[1]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(1), Y => N_147); - - \previous_coarse_time_load_RNIE1A6[25]\ : XNOR2 - port map(A => coarse_time_load(25), B => - \previous_coarse_time_load[25]_net_1\, Y => - previous_coarse_time_load_1_25_i); - - \state_RNIEG3J2_0[0]\ : NOR2 - port map(A => N_25, B => N_24, Y => \un1_cpt_1[0]\); - - \secondary_cpt[7]\ : DFN1E0C1 - port map(D => secondary_cpt_n7, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[7]_net_1\); - - \latched_next_commutation_RNO[10]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(10), Y => N_156); - - \s_coarse_time_RNO_1[6]\ : NOR2B - port map(A => soft_tick_2, B => \s_coarse_time_4[6]\, Y => - un1_soft_tick_10_i); - - \latched_next_commutation_RNI0IIA1[4]\ : NOR3C - port map(A => s_coarse_time_1_5_i, B => s_coarse_time_1_4_i, - C => s_coarse_time_1_NE_3, Y => s_coarse_time_1_NE_17); - - \cpt[6]\ : DFN1C1 - port map(D => I_31_8, CLK => clk_div_0, CLR => reset_i_0, Q - => \fine_time[6]\); - - \previous_coarse_time_load_RNIIQIC[22]\ : XA1A - port map(A => \previous_coarse_time_load[22]_net_1\, B => - coarse_time_load(22), C => - previous_coarse_time_load_1_23_i, Y => - previous_coarse_time_load_1_NE_11); - - \previous_coarse_time_load_RNIOK9U5[10]\ : OR2B - port map(A => previous_coarse_time_load_1_NE_29, B => - previous_coarse_time_load_1_NE_28, Y => flag_1); - - \cpt_RNI7OH91[10]\ : NOR3C - port map(A => \un1_cpt_0_a3_11[0]\, B => - \un1_cpt_0_a3_10[0]\, C => \un1_cpt_0_a3_15[0]\, Y => - N_25); - - un4_s_coarse_time_I_189 : AND3 - port map(A => \s_coarse_time[24]_net_1\, B => - \s_coarse_time[25]_net_1\, C => \s_coarse_time[26]_net_1\, - Y => \DWACT_FINC_E[22]\); - - \p_next_commutation[11]\ : DFN1E1 - port map(D => next_commutation(11), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[11]_net_1\); - - \latched_next_commutation[7]\ : DFN1E0P0 - port map(D => N_153, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[7]_net_1\); - - un4_s_coarse_time_I_135 : AND3 - port map(A => \DWACT_FINC_E[28]\, B => \DWACT_FINC_E[13]\, - C => \DWACT_FINC_E[15]\, Y => N_66); - - \s_coarse_time_RNO_0[31]\ : OA1B - port map(A => \s_coarse_time_4[31]\, B => - un1_s_coarse_time_3_m_0, C => \s_coarse_time_i_m[31]\, Y - => \s_coarse_time_10_iv[31]\); - - \p_next_commutation[31]\ : DFN1E1 - port map(D => next_commutation(31), CLK => lclk_c, E => - rstn, Q => \p_next_commutation[31]_net_1\); - - \latched_next_commutation[4]\ : DFN1E0P0 - port map(D => N_150, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[4]_net_1\); - - \previous_coarse_time_load[28]\ : DFN1E0C0 - port map(D => coarse_time_load(28), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[28]_net_1\); - - \previous_coarse_time_load_RNI2T9A[8]\ : XA1A - port map(A => \previous_coarse_time_load[8]_net_1\, B => - coarse_time_load(8), C => previous_coarse_time_load_1_9_i, - Y => previous_coarse_time_load_1_NE_4); - - \latched_next_commutation_RNO[14]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(14), Y => N_160); - - \previous_coarse_time_load[12]\ : DFN1E0C0 - port map(D => coarse_time_load(12), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[12]_net_1\); - - \p_next_commutation_RNIONBA1[28]\ : NOR3C - port map(A => N_139_i_i_0, B => N_138_i_i_0, C => - un1_commutation_timer_3_0_a2_15, Y => - un1_commutation_timer_3_0_a2_23); - - \previous_coarse_time_load[25]\ : DFN1E0C0 - port map(D => coarse_time_load(25), CLK => clk_div_1, CLR - => rstn, E => soft_tick, Q => - \previous_coarse_time_load[25]_net_1\); - - un1_cpt_next_commutation_I_95 : NOR2B - port map(A => \DWACT_ADD_CI_0_g_array_3[0]\, B => - \cpt_next_commutation[8]_net_1\, Y => - \DWACT_ADD_CI_0_g_array_12_3[0]\); - - \previous_coarse_time_load_RNI8H96[13]\ : XNOR2 - port map(A => coarse_time_load(13), B => - \previous_coarse_time_load[13]_net_1\, Y => - previous_coarse_time_load_1_13_i); - - \s_coarse_time_RNO[14]\ : AO1C - port map(A => \s_coarse_time_4[14]\, B => soft_tick_1, C - => rstn, Y => un1_resetn_3_i); - - \latched_next_commutation[6]\ : DFN1E0P0 - port map(D => N_152, CLK => lclk_c, PRE => rstn, E => - un1_commutation_timer_3, Q => - \latched_next_commutation[6]_net_1\); - - un4_s_coarse_time_I_65 : AND3 - port map(A => \DWACT_FINC_E_0[6]\, B => - \s_coarse_time[9]_net_1\, C => \s_coarse_time[10]_net_1\, - Y => N_116); - - un4_s_coarse_time_I_169 : AND3 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - C => \s_coarse_time[24]_net_1\, Y => \DWACT_FINC_E[19]\); - - \secondary_cpt_RNO[14]\ : AX1C - port map(A => \secondary_cpt[13]_net_1\, B => - secondary_cpt_c12, C => \secondary_cpt[14]_net_1\, Y => - secondary_cpt_n14); - - un4_s_coarse_time_I_182 : AND3 - port map(A => \DWACT_FINC_E_0[7]\, B => \DWACT_FINC_E[9]\, - C => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[30]\); - - un1_cpt_next_commutation_I_104 : AND2 - port map(A => \cpt_next_commutation[12]_net_1\, B => - \cpt_next_commutation[13]_net_1\, Y => - \DWACT_ADD_CI_0_pog_array_1_5[0]\); - - \p_next_commutation_RNIC5QA[2]\ : XA1A - port map(A => \p_next_commutation[2]_net_1\, B => - next_commutation(2), C => N_113_i_i_0, Y => - un1_commutation_timer_3_0_a2_1); - - \previous_coarse_time_load_RNI2U45[1]\ : XNOR2 - port map(A => coarse_time_load(1), B => - \previous_coarse_time_load[1]_net_1\, Y => - previous_coarse_time_load_1_1_i); - - un4_s_coarse_time_I_118 : AND3 - port map(A => \DWACT_FINC_E_0[7]\, B => \DWACT_FINC_E[9]\, - C => \DWACT_FINC_E[12]\, Y => \DWACT_FINC_E[13]\); - - \cpt_RNIH6G2[8]\ : NOR2 - port map(A => \fine_time[8]\, B => \fine_time[9]\, Y => - flag_1_sqmuxa_i_o3_6); - - \p_next_commutation[9]\ : DFN1E1 - port map(D => next_commutation(9), CLK => lclk_c, E => rstn, - Q => \p_next_commutation[9]_net_1\); - - \s_coarse_time_RNO[30]\ : AO1C - port map(A => \s_coarse_time_4[30]\, B => soft_tick_0, C - => rstn, Y => un1_resetn_7_i); - - \cpt_next_commutation[2]\ : DFN1C0 - port map(D => I_68, CLK => lclk_c, CLR => rstn, Q => - \cpt_next_commutation[2]_net_1\); - - \previous_coarse_time_load_RNIKBGI1[30]\ : NOR3C - port map(A => previous_coarse_time_load_1_NE_15, B => - previous_coarse_time_load_1_NE_14, C => - previous_coarse_time_load_1_NE_22, Y => - previous_coarse_time_load_1_NE_27); - - \previous_coarse_time_load[19]\ : DFN1E0C0 - port map(D => coarse_time_load(19), CLK => clk_div_1, CLR - => rstn, E => soft_tick_3, Q => - \previous_coarse_time_load[19]_net_1\); - - \s_coarse_time[22]\ : DFN1P1C1 - port map(D => \s_coarse_time_7[22]\, CLK => clk_div_3, PRE - => un1_soft_tick_24_i, CLR => un1_resetn_5_i, Q => - \s_coarse_time[22]_net_1\); - - \cpt_RNO[16]\ : NOR2B - port map(A => I_98_4, B => \un1_cpt_0[0]\, Y => \cpt_5[16]\); - - \cpt_RNI76G2[2]\ : NOR2 - port map(A => \fine_time[2]\, B => \fine_time[5]\, Y => - flag_1_sqmuxa_i_o3_2); - - \latched_next_commutation_RNO[16]\ : OR2A - port map(A => s_coarse_time_1_NE_0, B => - next_commutation(16), Y => N_162); - - \secondary_cpt[2]\ : DFN1E0C1 - port map(D => secondary_cpt_n2, CLK => clk_int, CLR => - reset_i_0, E => \un1_cpt[0]\, Q => - \secondary_cpt[2]_net_1\); - - \coarse_time[31]\ : DFN1P0 - port map(D => \s_coarse_time[31]_net_1\, CLK => lclk_c, PRE - => rstn, Q => coarse_time(31)); - - un4_s_coarse_time_I_162 : AND2 - port map(A => \DWACT_FINC_E[15]\, B => \DWACT_FINC_E[17]\, - Y => \DWACT_FINC_E[18]\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity apb_lfr_time_management is - - port( coarse_time_i : out std_logic_vector(0 to 0); - pirq : out std_logic_vector(13 downto 12); - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - pwdata_1_0 : in std_logic; - prdata : out std_logic_vector(31 downto 0); - coarse_time_0 : out std_logic; - pwdata_10 : in std_logic; - pwdata_8 : in std_logic; - pwdata_7 : in std_logic; - pwdata_13 : in std_logic; - pwdata_12 : in std_logic; - pwdata_11 : in std_logic; - pwdata_9 : in std_logic; - pwdata_6 : in std_logic; - pwdata_5 : in std_logic; - pwdata_4 : in std_logic; - pwdata_3 : in std_logic; - pwdata_0_d0 : in std_logic; - pwdata_18 : in std_logic; - pwdata_29 : in std_logic; - pwdata_28 : in std_logic; - pwdata_27 : in std_logic; - pwdata_25 : in std_logic; - pwdata_24 : in std_logic; - pwdata_23 : in std_logic; - pwdata_22 : in std_logic; - pwdata_21 : in std_logic; - pwdata_20 : in std_logic; - pwdata_19 : in std_logic; - pwdata_17 : in std_logic; - pwdata_26 : in std_logic; - pwdata_16 : in std_logic; - pwdata_15 : in std_logic; - pwdata_14 : in std_logic; - pwdata_0 : in std_logic_vector(15 downto 0); - paddr : in std_logic_vector(7 downto 3); - psel : in std_logic_vector(15 to 15); - rstn_i : in std_logic; - clk49_152MHz_c : in std_logic; - clk49_152MHz_c_0 : in std_logic; - un1_apbi_7_1 : out std_logic; - rdata60 : out std_logic; - ctrl2 : out std_logic; - rdata59 : out std_logic; - N_232_0 : in std_logic; - un1_apbi_2 : in std_logic; - rdata61_2 : in std_logic; - N_770 : out std_logic; - rdata62_0 : in std_logic; - rdata61 : out std_logic; - un1_apbi_8 : out std_logic; - un1_apbi_7_3 : in std_logic; - un1_apbi_0 : in std_logic; - rdata62 : in std_logic; - rdata60_4 : in std_logic; - rdata59_4 : in std_logic; - readdata55_3 : in std_logic; - rdata62_3 : out std_logic; - pwrite : in std_logic; - rstn : in std_logic; - lclk_c : in std_logic - ); - -end apb_lfr_time_management; - -architecture DEF_ARCH of apb_lfr_time_management is - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lfr_time_management - port( pirq : out std_logic_vector(13 downto 12); - coarse_time_load : in std_logic_vector(31 downto 0) := (others => 'U'); - next_commutation : in std_logic_vector(31 downto 0) := (others => 'U'); - coarse_time : out std_logic_vector(31 downto 0); - coarse_time_i : out std_logic_vector(0 to 0); - fine_time : out std_logic_vector(16 downto 0); - clk49_152MHz_c_0 : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - soft_tick : in std_logic := 'U'; - rstn_i : in std_logic := 'U'; - soft_tick_3 : in std_logic := 'U'; - soft_tick_2 : in std_logic := 'U'; - soft_tick_1 : in std_logic := 'U'; - soft_tick_0 : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - signal \soft_tick_3\, \previous_force_tick_RNIKV47\, - \soft_tick_2\, \soft_tick_1\, \soft_tick_0\, - \Rdata_0_sqmuxa_0\, ctrl2_0, rdata59_0, \rdata62_3\, - rdata60_0, N_380_0, \un1_apbi_4\, - next_commutation_1_sqmuxa_0, \un1_apbi_4_0\, - coarse_time_load_1_sqmuxa_i_0, - coarse_time_load_2_sqmuxa_0_0, \ctrl_m[8]\, \ctrl[8]\, - \coarse_time_load_m[14]\, \coarse_time_load[14]\, - \ctrl_m[14]\, \ctrl[14]\, \coarse_time_load_m[8]\, - \coarse_time_load[8]\, \ctrl_m[15]\, \ctrl[15]\, - \coarse_time_load_m[15]\, \coarse_time_load[15]\, - \ctrl_m[3]\, \ctrl[3]\, \coarse_time_load_m[3]\, - \coarse_time_load[3]\, \ctrl_m[4]\, \ctrl[4]\, - \coarse_time_load_m[4]\, \coarse_time_load[4]\, - \ctrl_m[11]\, \ctrl[11]\, \coarse_time_load_m[11]\, - \coarse_time_load[11]\, \ctrl_1_iv_2[3]\, - \ctrl_1_iv_2[4]\, \ctrl_1_iv_2[11]\, \ctrl_1_iv_2[15]\, - \ctrl_1_iv_2[8]\, \ctrl_1_iv_2[14]\, \ctrl_1_iv_0[8]\, - \fine_time[8]\, \next_commutation_m[8]\, - \ctrl_1_iv_0[14]\, \rdata61\, \fine_time[14]\, - \next_commutation_m[14]\, \ctrl_1_iv_2[1]\, \ctrl[1]\, - \coarse_time_load_m[1]\, \ctrl_1_iv_0[1]\, \fine_time[1]\, - \next_commutation_m[1]\, \ctrl_1_iv_2[2]\, \ctrl[2]\, - \coarse_time_load_m[2]\, \ctrl_1_iv_0[2]\, \fine_time[2]\, - \next_commutation_m[2]\, \ctrl_1_iv_2[0]\, \ctrl[0]\, - \coarse_time_load_m[0]\, \ctrl_1_iv_0[0]\, \fine_time[0]\, - \next_commutation_m[0]\, \ctrl_1_iv_2[6]\, \ctrl[6]\, - \coarse_time_load_m[6]\, \ctrl_1_iv_0[6]\, \fine_time[6]\, - \next_commutation_m[6]\, \ctrl_1_iv_2[7]\, \ctrl[7]\, - \coarse_time_load_m[7]\, \ctrl_1_iv_0[7]\, \fine_time[7]\, - \next_commutation_m[7]\, \ctrl_1_iv_2[9]\, \ctrl[9]\, - \coarse_time_load_m[9]\, \ctrl_1_iv_0[9]\, \fine_time[9]\, - \next_commutation_m[9]\, \ctrl_1_iv_2[12]\, \ctrl[12]\, - \coarse_time_load_m[12]\, \ctrl_1_iv_0[12]\, - \fine_time[12]\, \next_commutation_m[12]\, - \ctrl_1_iv_2[16]\, \ctrl[16]\, \coarse_time_load_m[16]\, - \ctrl_1_iv_0[16]\, \fine_time[16]\, - \next_commutation_m[16]\, \ctrl_1_iv_0[3]\, - \fine_time[3]\, \next_commutation_m[3]\, \ctrl_1_iv_0[4]\, - \fine_time[4]\, \next_commutation_m[4]\, - \ctrl_1_iv_2[10]\, \ctrl[10]\, \coarse_time_load_m[10]\, - \ctrl_1_iv_0[10]\, \fine_time[10]\, - \next_commutation_m[10]\, \ctrl_1_iv_0[11]\, - \fine_time[11]\, \next_commutation_m[11]\, - \ctrl_1_iv_2[5]\, \ctrl[5]\, \coarse_time_load_m[5]\, - \ctrl_1_iv_0[5]\, \fine_time[5]\, \next_commutation_m[5]\, - \ctrl_1_iv_2[13]\, \ctrl[13]\, \coarse_time_load_m[13]\, - \ctrl_1_iv_0[13]\, \fine_time[13]\, - \next_commutation_m[13]\, \ctrl_1_iv_0[15]\, - \fine_time[15]\, \next_commutation_m[15]\, - \ctrl_1_0_iv_0[20]\, \next_commutation[20]\, - \coarse_time_m[20]\, \ctrl_1_0_iv_0[31]\, - \next_commutation[31]\, \coarse_time_m[31]\, - \ctrl_1_0_iv_0[23]\, \next_commutation[23]\, - \coarse_time_m[23]\, \ctrl_1_0_iv_0[25]\, - \next_commutation[25]\, \coarse_time_m[25]\, - \ctrl_1_0_iv_0[26]\, \next_commutation[26]\, - \coarse_time_m[26]\, \ctrl_1_0_iv_0[27]\, - \next_commutation[27]\, \coarse_time_m[27]\, - \ctrl_1_0_iv_0[30]\, \next_commutation[30]\, - \coarse_time_m[30]\, \ctrl_1_0_iv_0[17]\, - \next_commutation[17]\, \coarse_time_m[17]\, - \ctrl_1_0_iv_0[18]\, \next_commutation[18]\, - \coarse_time_m[18]\, \ctrl_1_0_iv_0[19]\, - \next_commutation[19]\, \coarse_time_m[19]\, - \ctrl_1_0_iv_0[21]\, \next_commutation[21]\, - \coarse_time_m[21]\, \ctrl_1_0_iv_0[22]\, - \next_commutation[22]\, \coarse_time_m[22]\, - \ctrl_1_0_iv_0[24]\, \next_commutation[24]\, - \coarse_time_m[24]\, \ctrl_1_0_iv_0[28]\, - \next_commutation[28]\, \coarse_time_m[28]\, - \ctrl_1_0_iv_0[29]\, \next_commutation[29]\, - \coarse_time_m[29]\, coarse_time_load_2_sqmuxa_0, - un1_apbi_8_net_1, \un1_apbi_8_0\, \ctrl_1[15]\, - \coarse_time_m[15]\, \ctrl_1[13]\, \coarse_time_m[13]\, - \ctrl_1[5]\, \coarse_time_m[5]\, \ctrl_1[11]\, - \coarse_time_m[11]\, \ctrl_1[10]\, \coarse_time_m[10]\, - \ctrl_1[4]\, \coarse_time_m[4]\, \ctrl_1[3]\, - \coarse_time_m[3]\, \ctrl_1[29]\, - \coarse_time_load_m[29]\, \ctrl_m[29]\, \ctrl_1[28]\, - \coarse_time_load_m[28]\, \ctrl_m[28]\, \ctrl_1[24]\, - \coarse_time_load_m[24]\, \ctrl_m[24]\, \ctrl_1[22]\, - \coarse_time_load_m[22]\, \ctrl_m[22]\, \ctrl_1[21]\, - \coarse_time_load_m[21]\, \ctrl_m[21]\, \ctrl_1[19]\, - \coarse_time_load_m[19]\, \ctrl_m[19]\, \ctrl_1[18]\, - \coarse_time_load_m[18]\, \ctrl_m[18]\, \ctrl_1[17]\, - \coarse_time_load_m[17]\, \ctrl_m[17]\, \ctrl_1[16]\, - \coarse_time_m[16]\, \ctrl_1[12]\, \coarse_time_m[12]\, - \ctrl_1[9]\, \coarse_time_m[9]\, \ctrl_1[7]\, - \coarse_time_m[7]\, \ctrl_1[6]\, \coarse_time_m[6]\, - \ctrl_1[30]\, \coarse_time_load_m[30]\, \ctrl_m[30]\, - \ctrl_1[27]\, \coarse_time_load_m[27]\, \ctrl_m[27]\, - \ctrl_1[26]\, \coarse_time_load_m[26]\, \ctrl_m[26]\, - \ctrl_1[25]\, \coarse_time_load_m[25]\, \ctrl_m[25]\, - \ctrl_1[23]\, \coarse_time_load_m[23]\, \ctrl_m[23]\, - \ctrl_1[0]\, \coarse_time_m[0]\, \ctrl_1[2]\, - \coarse_time_m[2]\, \ctrl_1[1]\, \coarse_time_m[1]\, - \ctrl_1[14]\, \coarse_time_m[14]\, \ctrl_1[31]\, - \coarse_time_load_m[31]\, \ctrl_m[31]\, \ctrl_1[20]\, - \coarse_time_load_m[20]\, \ctrl_m[20]\, \ctrl_1[8]\, - \coarse_time_m[8]\, \coarse_time_load[5]\, - \coarse_time[5]\, \next_commutation[5]\, - \coarse_time_load[13]\, \coarse_time[13]\, - \next_commutation[13]\, \coarse_time[15]\, - \next_commutation[15]\, N_120, \coarse_time_load[1]\, - N_125, \coarse_time_load[6]\, N_131, - \coarse_time_load[12]\, N_133, \coarse_time_load_3[1]\, - \coarse_time_load_3[6]\, \coarse_time_load_3[12]\, - \coarse_time_load_3[14]\, \coarse_time[3]\, - \next_commutation[3]\, \coarse_time[4]\, - \next_commutation[4]\, \coarse_time_load[10]\, - \coarse_time[10]\, \next_commutation[10]\, - \coarse_time[11]\, \next_commutation[11]\, N_123, N_126, - \coarse_time_load[7]\, N_127, N_128, - \coarse_time_load[9]\, N_129, N_130, - \coarse_time_load_3[4]\, \coarse_time_load_3[7]\, - \coarse_time_load_3[8]\, \coarse_time_load_3[9]\, - \coarse_time_load_3[10]\, \coarse_time_load_3[11]\, - \Rdata_0_sqmuxa\, \coarse_time[6]\, \next_commutation[6]\, - \coarse_time[7]\, \next_commutation[7]\, \coarse_time[9]\, - \next_commutation[9]\, \coarse_time[12]\, - \next_commutation[12]\, \coarse_time_load[16]\, - \coarse_time[16]\, \next_commutation[16]\, \ctrl[17]\, - \ctrl2\, \coarse_time_load[17]\, \coarse_time[17]\, - \ctrl[18]\, \coarse_time_load[18]\, \coarse_time[18]\, - \ctrl[19]\, \coarse_time_load[19]\, \coarse_time[19]\, - \ctrl[21]\, \coarse_time_load[21]\, \rdata59\, - \coarse_time[21]\, \ctrl[22]\, \coarse_time_load[22]\, - \coarse_time[22]\, \ctrl[24]\, \coarse_time_load[24]\, - \coarse_time[24]\, \ctrl[28]\, \coarse_time_load[28]\, - \rdata60\, \coarse_time[28]\, \ctrl[29]\, - \coarse_time_load[29]\, \coarse_time[29]\, N_121, - \coarse_time_load[2]\, N_122, N_135, N_136, N_137, N_147, - \coarse_time_load_3[2]\, \coarse_time_load_3[3]\, - \coarse_time_load_3[16]\, \coarse_time_load_3[17]\, - \coarse_time_load_3[18]\, \coarse_time_load_3[28]\, - \ctrl[23]\, \coarse_time_load[23]\, \coarse_time[23]\, - \ctrl[25]\, \coarse_time_load[25]\, \coarse_time[25]\, - \ctrl[26]\, \coarse_time_load[26]\, \coarse_time[26]\, - \ctrl[27]\, \coarse_time_load[27]\, \coarse_time[27]\, - \ctrl[30]\, \coarse_time_load[30]\, \coarse_time[30]\, - N_119, \coarse_time_load[0]\, coarse_time_load_1_sqmuxa_i, - N_124, N_134, N_138, N_140, N_141, N_142, N_143, N_144, - N_145, N_146, N_148, N_149, \coarse_time_load_3[0]\, - \coarse_time_load_3[5]\, \coarse_time_load_3[15]\, - \coarse_time_load_3[19]\, \coarse_time_load_3[21]\, - \coarse_time_load_3[22]\, \coarse_time_load_3[23]\, - \coarse_time_load_3[24]\, \coarse_time_load_3[25]\, - \coarse_time_load_3[26]\, \coarse_time_load_3[27]\, - \coarse_time_load_3[29]\, \coarse_time_load_3[30]\, - \next_commutation[0]\, \ctrl_0[0]\, - next_commutation_1_sqmuxa, N_380, ctrl_1_sqmuxa, - \next_commutation[2]\, \coarse_time[2]\, - \next_commutation[1]\, \coarse_time[1]\, \N_770\, - \next_commutation[14]\, \coarse_time[14]\, - \coarse_time_load_3[31]\, N_150, \coarse_time_load[31]\, - \coarse_time[31]\, \ctrl[31]\, \coarse_time_load_3[13]\, - N_132, \coarse_time[20]\, \coarse_time_load[20]\, - \ctrl[20]\, \coarse_time_load_3[20]\, N_139, - \next_commutation[8]\, \coarse_time[8]\, \force_tick\, - \previous_force_tick\, \soft_tick\, \coarse_time[0]\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - - for all : lfr_time_management - Use entity work.lfr_time_management(DEF_ARCH); -begin - - coarse_time_0 <= \coarse_time[0]\; - rdata60 <= \rdata60\; - ctrl2 <= \ctrl2\; - rdata59 <= \rdata59\; - N_770 <= \N_770\; - rdata61 <= \rdata61\; - un1_apbi_8 <= un1_apbi_8_net_1; - rdata62_3 <= \rdata62_3\; - - \Rdata_RNO_5[11]\ : OR2A - port map(A => \ctrl[11]\, B => ctrl2_0, Y => \ctrl_m[11]\); - - \Rdata_RNO_3[7]\ : OR2A - port map(A => \next_commutation[7]\, B => rdata62, Y => - \next_commutation_m[7]\); - - \r.ctrl_RNO[0]\ : NOR2A - port map(A => pwdata_0(0), B => \un1_apbi_4\, Y => - \ctrl_0[0]\); - - \Rdata_RNO_0[20]\ : OR2A - port map(A => \coarse_time_load[20]\, B => \rdata59\, Y => - \coarse_time_load_m[20]\); - - \r.coarse_time_load[11]\ : DFN1C0 - port map(D => \coarse_time_load_3[11]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[11]\); - - \Rdata_RNO_4[8]\ : OR2A - port map(A => \coarse_time_load[8]\, B => rdata59_0, Y => - \coarse_time_load_m[8]\); - - \r.ctrl[24]\ : DFN1E1C0 - port map(D => pwdata_22, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[24]\); - - \Rdata_RNO_1[30]\ : OR2A - port map(A => \ctrl[30]\, B => \ctrl2\, Y => \ctrl_m[30]\); - - \r.coarse_time_load_RNO_0[19]\ : MX2C - port map(A => pwdata_17, B => \coarse_time_load[19]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_138); - - \Rdata_RNO_3[20]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[20]\, Y => - \coarse_time_m[20]\); - - \r.coarse_time_load_RNO_0[18]\ : MX2C - port map(A => pwdata_16, B => \coarse_time_load[18]\, S => - coarse_time_load_1_sqmuxa_i_0, Y => N_137); - - \Rdata_RNO_3[4]\ : OR2A - port map(A => \next_commutation[4]\, B => rdata62, Y => - \next_commutation_m[4]\); - - \Rdata[15]\ : DFN1E1C0 - port map(D => \ctrl_1[15]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(15)); - - \r.coarse_time_load_RNO[29]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_148, Y => - \coarse_time_load_3[29]\); - - \Rdata[9]\ : DFN1E1C0 - port map(D => \ctrl_1[9]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(9)); - - \Rdata_RNO_0[8]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[8]\, Y => - \coarse_time_m[8]\); - - \r.coarse_time_load_RNO_0[26]\ : MX2C - port map(A => pwdata_24, B => \coarse_time_load[26]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_145); - - \r.coarse_time_load_RNO[7]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_126, Y => - \coarse_time_load_3[7]\); - - \r.coarse_time_load[25]\ : DFN1C0 - port map(D => \coarse_time_load_3[25]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[25]\); - - \Rdata_RNO[31]\ : OR3C - port map(A => \coarse_time_load_m[31]\, B => \ctrl_m[31]\, - C => \ctrl_1_0_iv_0[31]\, Y => \ctrl_1[31]\); - - \r.coarse_time_load_RNO_0[6]\ : MX2C - port map(A => pwdata_0(6), B => \coarse_time_load[6]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_125); - - \Rdata_RNO_1[6]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[6]\, C => - \next_commutation_m[6]\, Y => \ctrl_1_iv_0[6]\); - - \r.coarse_time_load_RNO[1]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_120, Y => - \coarse_time_load_3[1]\); - - \r.coarse_time_load_2_sqmuxa_0_0\ : AO1A - port map(A => paddr(7), B => un1_apbi_7_3, C => - un1_apbi_8_net_1, Y => coarse_time_load_2_sqmuxa_0_0); - - \Rdata_RNO_1[21]\ : OR2A - port map(A => \ctrl[21]\, B => \ctrl2\, Y => \ctrl_m[21]\); - - soft_tick : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick\); - - \Rdata_RNO_0[27]\ : OR2A - port map(A => \coarse_time_load[27]\, B => \rdata59\, Y => - \coarse_time_load_m[27]\); - - \r.coarse_time_load[30]\ : DFN1C0 - port map(D => \coarse_time_load_3[30]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[30]\); - - \Rdata_RNO_5[4]\ : OR2A - port map(A => \ctrl[4]\, B => ctrl2_0, Y => \ctrl_m[4]\); - - \r.next_commutation_1_sqmuxa_0\ : NOR2 - port map(A => rdata62, B => \un1_apbi_4\, Y => - next_commutation_1_sqmuxa_0); - - \Rdata_RNO_4[3]\ : OR2A - port map(A => \coarse_time_load[3]\, B => rdata59_0, Y => - \coarse_time_load_m[3]\); - - \r.coarse_time_load_RNO[17]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_136, Y => - \coarse_time_load_3[17]\); - - \Rdata_RNO_2[25]\ : OA1A - port map(A => \next_commutation[25]\, B => rdata62_0, C => - \coarse_time_m[25]\, Y => \ctrl_1_0_iv_0[25]\); - - \Rdata_RNO_0[13]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[13]\, Y => - \coarse_time_m[13]\); - - \r.ctrl[14]\ : DFN1E1C0 - port map(D => pwdata_12, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[14]\); - - \r.coarse_time_load[31]\ : DFN1P0 - port map(D => \coarse_time_load_3[31]\, CLK => lclk_c, PRE - => rstn, Q => \coarse_time_load[31]\); - - \Rdata[31]\ : DFN1E1C0 - port map(D => \ctrl_1[31]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(31)); - - \Rdata_RNO_3[27]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[27]\, Y => - \coarse_time_m[27]\); - - \Rdata_RNO_1[19]\ : OR2A - port map(A => \ctrl[19]\, B => \ctrl2\, Y => \ctrl_m[19]\); - - \r.coarse_time_load[13]\ : DFN1C0 - port map(D => \coarse_time_load_3[13]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[13]\); - - \Rdata_RNO_0[24]\ : OR2A - port map(A => \coarse_time_load[24]\, B => \rdata59\, Y => - \coarse_time_load_m[24]\); - - \Rdata_RNO_2[28]\ : OA1A - port map(A => \next_commutation[28]\, B => rdata62_0, C => - \coarse_time_m[28]\, Y => \ctrl_1_0_iv_0[28]\); - - \r.next_commutation[7]\ : DFN1E1P0 - port map(D => pwdata_5, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[7]\); - - \r.ctrl2_0\ : OR2 - port map(A => \rdata62_3\, B => readdata55_3, Y => ctrl2_0); - - \Rdata[26]\ : DFN1E1C0 - port map(D => \ctrl_1[26]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(26)); - - \r.coarse_time_load_RNO[16]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_135, Y => - \coarse_time_load_3[16]\); - - \Rdata[6]\ : DFN1E1C0 - port map(D => \ctrl_1[6]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(6)); - - \Rdata_RNO_3[24]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[24]\, Y => - \coarse_time_m[24]\); - - \Rdata[24]\ : DFN1E1C0 - port map(D => \ctrl_1[24]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(24)); - - \r.next_commutation[0]\ : DFN1E1P0 - port map(D => pwdata_0(0), CLK => lclk_c, PRE => rstn, E - => next_commutation_1_sqmuxa_0, Q => - \next_commutation[0]\); - - \Rdata[27]\ : DFN1E1C0 - port map(D => \ctrl_1[27]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(27)); - - \r.ctrl_RNO_0[0]\ : AO1 - port map(A => \un1_apbi_4\, B => \ctrl[0]\, C => N_380_0, Y - => ctrl_1_sqmuxa); - - \Rdata_RNO[29]\ : OR3C - port map(A => \coarse_time_load_m[29]\, B => \ctrl_m[29]\, - C => \ctrl_1_0_iv_0[29]\, Y => \ctrl_1[29]\); - - \un1_apbi_8\ : NOR2 - port map(A => \un1_apbi_8_0\, B => N_232_0, Y => - un1_apbi_8_net_1); - - \r.coarse_time_load_RNO[21]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_140, Y => - \coarse_time_load_3[21]\); - - \Rdata_RNO_2[1]\ : OA1A - port map(A => \ctrl[1]\, B => ctrl2_0, C => - \coarse_time_load_m[1]\, Y => \ctrl_1_iv_2[1]\); - - \Rdata_RNO_3[30]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[30]\, Y => - \coarse_time_m[30]\); - - \r.ctrl[30]\ : DFN1E1C0 - port map(D => pwdata_28, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[30]\); - - \Rdata_RNO_1[4]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[4]\, C => - \next_commutation_m[4]\, Y => \ctrl_1_iv_0[4]\); - - \r.ctrl[28]\ : DFN1E1C0 - port map(D => pwdata_26, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[28]\); - - \r.coarse_time_load_RNO[14]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_133, Y => - \coarse_time_load_3[14]\); - - \Rdata_RNO[23]\ : OR3C - port map(A => \coarse_time_load_m[23]\, B => \ctrl_m[23]\, - C => \ctrl_1_0_iv_0[23]\, Y => \ctrl_1[23]\); - - \r.coarse_time_load_RNO_0[23]\ : MX2C - port map(A => pwdata_21, B => \coarse_time_load[23]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_142); - - \Rdata_RNO_1[22]\ : OR2A - port map(A => \ctrl[22]\, B => \ctrl2\, Y => \ctrl_m[22]\); - - \Rdata_RNO_2[8]\ : AND2 - port map(A => \coarse_time_load_m[8]\, B => \ctrl_m[8]\, Y - => \ctrl_1_iv_2[8]\); - - \Rdata_RNO_2[6]\ : OA1A - port map(A => \ctrl[6]\, B => ctrl2_0, C => - \coarse_time_load_m[6]\, Y => \ctrl_1_iv_2[6]\); - - \Rdata_RNO[20]\ : OR3C - port map(A => \coarse_time_load_m[20]\, B => \ctrl_m[20]\, - C => \ctrl_1_0_iv_0[20]\, Y => \ctrl_1[20]\); - - \Rdata_RNO_2[21]\ : OA1A - port map(A => \next_commutation[21]\, B => rdata62_0, C => - \coarse_time_m[21]\, Y => \ctrl_1_0_iv_0[21]\); - - \Rdata_RNO_2[19]\ : OA1A - port map(A => \next_commutation[19]\, B => rdata62_0, C => - \coarse_time_m[19]\, Y => \ctrl_1_0_iv_0[19]\); - - \Rdata_RNO_0[30]\ : OR2A - port map(A => \coarse_time_load[30]\, B => \rdata59\, Y => - \coarse_time_load_m[30]\); - - \Rdata[5]\ : DFN1E1C0 - port map(D => \ctrl_1[5]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(5)); - - \r.next_commutation[2]\ : DFN1E1P0 - port map(D => pwdata_0_d0, CLK => lclk_c, PRE => rstn, E - => next_commutation_1_sqmuxa, Q => \next_commutation[2]\); - - \Rdata_RNO[24]\ : OR3C - port map(A => \coarse_time_load_m[24]\, B => \ctrl_m[24]\, - C => \ctrl_1_0_iv_0[24]\, Y => \ctrl_1[24]\); - - \Rdata_RNO_1[26]\ : OR2A - port map(A => \ctrl[26]\, B => \ctrl2\, Y => \ctrl_m[26]\); - - \Rdata_RNO_0[0]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[0]\, Y => - \coarse_time_m[0]\); - - \Rdata_RNO_0[15]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[15]\, Y => - \coarse_time_m[15]\); - - \Rdata_RNO[27]\ : OR3C - port map(A => \coarse_time_load_m[27]\, B => \ctrl_m[27]\, - C => \ctrl_1_0_iv_0[27]\, Y => \ctrl_1[27]\); - - \r.ctrl[9]\ : DFN1E1C0 - port map(D => pwdata_0(9), CLK => lclk_c, CLR => rstn, E - => N_380, Q => \ctrl[9]\); - - \Rdata_RNO_0[18]\ : OR2A - port map(A => \coarse_time_load[18]\, B => rdata59_0, Y => - \coarse_time_load_m[18]\); - - \r.coarse_time_load_RNO[0]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0, C => N_119, Y => - \coarse_time_load_3[0]\); - - \r.ctrl[4]\ : DFN1E1C0 - port map(D => pwdata_1_3, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[4]\); - - \Rdata_RNO_1[7]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[7]\, C => - \next_commutation_m[7]\, Y => \ctrl_1_iv_0[7]\); - - \r.coarse_time_load_RNO_0[31]\ : MX2C - port map(A => pwdata_29, B => \coarse_time_load[31]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_150); - - \r.coarse_time_load_RNO[18]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_137, Y => - \coarse_time_load_3[18]\); - - \r.ctrl[18]\ : DFN1E1C0 - port map(D => pwdata_16, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[18]\); - - \r.next_commutation[18]\ : DFN1E1P0 - port map(D => pwdata_16, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[18]\); - - \Rdata_RNO[22]\ : OR3C - port map(A => \coarse_time_load_m[22]\, B => \ctrl_m[22]\, - C => \ctrl_1_0_iv_0[22]\, Y => \ctrl_1[22]\); - - \r.coarse_time_load_RNO[22]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_141, Y => - \coarse_time_load_3[22]\); - - un1_apbi_4_0 : OR2 - port map(A => un1_apbi_0, B => psel(15), Y => - \un1_apbi_4_0\); - - \Rdata_RNO_4[13]\ : OR2A - port map(A => \coarse_time_load[13]\, B => rdata59_0, Y => - \coarse_time_load_m[13]\); - - GND_i : GND - port map(Y => \GND\); - - \Rdata_RNO_2[0]\ : OA1A - port map(A => \ctrl[0]\, B => ctrl2_0, C => - \coarse_time_load_m[0]\, Y => \ctrl_1_iv_2[0]\); - - \r.ctrl[6]\ : DFN1E1C0 - port map(D => pwdata_4, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[6]\); - - \r.coarse_time_load_RNO_0[5]\ : MX2C - port map(A => pwdata_0(5), B => \coarse_time_load[5]\, S - => coarse_time_load_1_sqmuxa_i, Y => N_124); - - \Rdata[22]\ : DFN1E1C0 - port map(D => \ctrl_1[22]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(22)); - - \r.ctrl[0]\ : DFN1E1C0 - port map(D => \ctrl_0[0]\, CLK => lclk_c, CLR => rstn, E - => ctrl_1_sqmuxa, Q => \ctrl[0]\); - - \r.coarse_time_load[5]\ : DFN1C0 - port map(D => \coarse_time_load_3[5]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[5]\); - - \Rdata[3]\ : DFN1E1C0 - port map(D => \ctrl_1[3]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(3)); - - \Rdata[16]\ : DFN1E1C0 - port map(D => \ctrl_1[16]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(16)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \Rdata_RNO_2[22]\ : OA1A - port map(A => \next_commutation[22]\, B => rdata62_0, C => - \coarse_time_m[22]\, Y => \ctrl_1_0_iv_0[22]\); - - \Rdata_RNO_3[13]\ : OR2A - port map(A => \next_commutation[13]\, B => rdata62_0, Y => - \next_commutation_m[13]\); - - \r.coarse_time_load_RNO_0[16]\ : MX2C - port map(A => pwdata_14, B => \coarse_time_load[16]\, S => - coarse_time_load_1_sqmuxa_i_0, Y => N_135); - - \Rdata[14]\ : DFN1E1C0 - port map(D => \ctrl_1[14]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(14)); - - \r.coarse_time_load_RNO_0[21]\ : MX2C - port map(A => pwdata_19, B => \coarse_time_load[21]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_140); - - \Rdata_RNO_1[20]\ : OR2A - port map(A => \ctrl[20]\, B => \ctrl2\, Y => \ctrl_m[20]\); - - \r.coarse_time_load_RNO_0[25]\ : MX2C - port map(A => pwdata_23, B => \coarse_time_load[25]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_144); - - \Rdata_RNO_0[29]\ : OR2A - port map(A => \coarse_time_load[29]\, B => \rdata59\, Y => - \coarse_time_load_m[29]\); - - \Rdata[17]\ : DFN1E1C0 - port map(D => \ctrl_1[17]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(17)); - - \Rdata_RNO_0[11]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[11]\, Y => - \coarse_time_m[11]\); - - \Rdata[20]\ : DFN1E1C0 - port map(D => \ctrl_1[20]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(20)); - - \Rdata_RNO_3[29]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[29]\, Y => - \coarse_time_m[29]\); - - \Rdata_RNO_5[14]\ : OR2A - port map(A => \ctrl[14]\, B => ctrl2_0, Y => \ctrl_m[14]\); - - \Rdata_RNO[18]\ : OR3C - port map(A => \coarse_time_load_m[18]\, B => \ctrl_m[18]\, - C => \ctrl_1_0_iv_0[18]\, Y => \ctrl_1[18]\); - - \r.ctrl[29]\ : DFN1E1C0 - port map(D => pwdata_27, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[29]\); - - \Rdata_RNO_2[26]\ : OA1A - port map(A => \next_commutation[26]\, B => rdata62_0, C => - \coarse_time_m[26]\, Y => \ctrl_1_0_iv_0[26]\); - - \Rdata_RNO_1[5]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[5]\, C => - \next_commutation_m[5]\, Y => \ctrl_1_iv_0[5]\); - - \r.coarse_time_load_RNO_0[8]\ : MX2C - port map(A => pwdata_0(8), B => \coarse_time_load[8]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_127); - - \Rdata_RNO_3[1]\ : OR2A - port map(A => \next_commutation[1]\, B => rdata62, Y => - \next_commutation_m[1]\); - - \Rdata_RNO_1[1]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[1]\, C => - \next_commutation_m[1]\, Y => \ctrl_1_iv_0[1]\); - - \r.coarse_time_load[4]\ : DFN1C0 - port map(D => \coarse_time_load_3[4]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[4]\); - - \r.coarse_time_load_RNO[5]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0, C => N_124, Y => - \coarse_time_load_3[5]\); - - \Rdata_RNO[11]\ : OR3C - port map(A => \coarse_time_m[11]\, B => \ctrl_1_iv_0[11]\, - C => \ctrl_1_iv_2[11]\, Y => \ctrl_1[11]\); - - \r.coarse_time_load_RNO[20]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_139, Y => - \coarse_time_load_3[20]\); - - \Rdata_RNO_4[7]\ : OR2A - port map(A => \coarse_time_load[7]\, B => rdata59_0, Y => - \coarse_time_load_m[7]\); - - rdata78 : NOR2 - port map(A => \rdata62_3\, B => rdata60_4, Y => \rdata60\); - - \r.ctrl2\ : OR2 - port map(A => \rdata62_3\, B => readdata55_3, Y => \ctrl2\); - - \Rdata_RNO[5]\ : OR3C - port map(A => \coarse_time_m[5]\, B => \ctrl_1_iv_0[5]\, C - => \ctrl_1_iv_2[5]\, Y => \ctrl_1[5]\); - - rdata78_3 : OR2 - port map(A => paddr(7), B => paddr(6), Y => \rdata62_3\); - - \Rdata_RNO_1[27]\ : OR2A - port map(A => \ctrl[27]\, B => \ctrl2\, Y => \ctrl_m[27]\); - - \r.coarse_time_load_RNO[6]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_125, Y => - \coarse_time_load_3[6]\); - - \r.coarse_time_load[20]\ : DFN1C0 - port map(D => \coarse_time_load_3[20]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[20]\); - - \Rdata_RNO_4[9]\ : OR2A - port map(A => \coarse_time_load[9]\, B => rdata59_0, Y => - \coarse_time_load_m[9]\); - - \Rdata_RNO_4[15]\ : OR2A - port map(A => \coarse_time_load[15]\, B => rdata59_0, Y => - \coarse_time_load_m[15]\); - - \r.coarse_time_load[21]\ : DFN1C0 - port map(D => \coarse_time_load_3[21]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[21]\); - - \r.coarse_time_load[18]\ : DFN1C0 - port map(D => \coarse_time_load_3[18]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[18]\); - - \Rdata_RNO_1[24]\ : OR2A - port map(A => \ctrl[24]\, B => \ctrl2\, Y => \ctrl_m[24]\); - - \r.ctrl[26]\ : DFN1E1C0 - port map(D => pwdata_24, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[26]\); - - \Rdata_RNO_1[9]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[9]\, C => - \next_commutation_m[9]\, Y => \ctrl_1_iv_0[9]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.coarse_time_load_RNO_0[24]\ : MX2C - port map(A => pwdata_22, B => \coarse_time_load[24]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_143); - - \r.coarse_time_load[14]\ : DFN1C0 - port map(D => \coarse_time_load_3[14]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[14]\); - - \r.ctrl[19]\ : DFN1E1C0 - port map(D => pwdata_17, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[19]\); - - soft_tick_0 : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick_0\); - - \r.ctrl_0_sqmuxa_0\ : NOR2 - port map(A => \un1_apbi_4\, B => ctrl2_0, Y => N_380_0); - - \Rdata_RNO_0[12]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[12]\, Y => - \coarse_time_m[12]\); - - \Rdata_RNO_3[15]\ : OR2A - port map(A => \next_commutation[15]\, B => rdata62, Y => - \next_commutation_m[15]\); - - \Rdata_RNO[3]\ : OR3C - port map(A => \coarse_time_m[3]\, B => \ctrl_1_iv_0[3]\, C - => \ctrl_1_iv_2[3]\, Y => \ctrl_1[3]\); - - \r.coarse_time_load_RNO_0[13]\ : MX2C - port map(A => pwdata_0(13), B => \coarse_time_load[13]\, S - => coarse_time_load_1_sqmuxa_i, Y => N_132); - - \Rdata_RNO_1[13]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[13]\, C => - \next_commutation_m[13]\, Y => \ctrl_1_iv_0[13]\); - - \Rdata_RNO_2[20]\ : OA1A - port map(A => \next_commutation[20]\, B => rdata62_0, C => - \coarse_time_m[20]\, Y => \ctrl_1_0_iv_0[20]\); - - \Rdata_RNO_1[3]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[3]\, C => - \next_commutation_m[3]\, Y => \ctrl_1_iv_0[3]\); - - \Rdata_RNO_3[18]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[18]\, Y => - \coarse_time_m[18]\); - - \r.coarse_time_load_2_sqmuxa_0\ : AO1A - port map(A => paddr(7), B => un1_apbi_7_3, C => - un1_apbi_8_net_1, Y => coarse_time_load_2_sqmuxa_0); - - \Rdata_RNO_1[2]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[2]\, C => - \next_commutation_m[2]\, Y => \ctrl_1_iv_0[2]\); - - \r.ctrl[23]\ : DFN1E1C0 - port map(D => pwdata_21, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[23]\); - - \r.next_commutation[28]\ : DFN1E1P0 - port map(D => pwdata_26, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[28]\); - - \r.coarse_time_load_RNO[2]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_121, Y => - \coarse_time_load_3[2]\); - - \Rdata_RNO_3[5]\ : OR2A - port map(A => \next_commutation[5]\, B => rdata62_0, Y => - \next_commutation_m[5]\); - - \Rdata_RNO_0[4]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[4]\, Y => - \coarse_time_m[4]\); - - \r.coarse_time_load[6]\ : DFN1C0 - port map(D => \coarse_time_load_3[6]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[6]\); - - \Rdata_RNO_0[16]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[16]\, Y => - \coarse_time_m[16]\); - - \Rdata[12]\ : DFN1E1C0 - port map(D => \ctrl_1[12]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(12)); - - \r.coarse_time_load[16]\ : DFN1C0 - port map(D => \coarse_time_load_3[16]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[16]\); - - \r.coarse_time_load_RNO[13]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_132, Y => - \coarse_time_load_3[13]\); - - \r.coarse_time_load_RNO_0[7]\ : MX2C - port map(A => pwdata_0(7), B => \coarse_time_load[7]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_126); - - \r.coarse_time_load_RNO[31]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_150, Y => - \coarse_time_load_3[31]\); - - \r.next_commutation[8]\ : DFN1E1P0 - port map(D => pwdata_6, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[8]\); - - \r.coarse_time_load[9]\ : DFN1C0 - port map(D => \coarse_time_load_3[9]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[9]\); - - \r.ctrl[16]\ : DFN1E1C0 - port map(D => pwdata_14, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[16]\); - - \r.coarse_time_load[23]\ : DFN1C0 - port map(D => \coarse_time_load_3[23]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[23]\); - - \un1_apbi_7_1\ : OR2 - port map(A => paddr(4), B => paddr(3), Y => un1_apbi_7_1); - - \r.coarse_time_load_RNO[3]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_122, Y => - \coarse_time_load_3[3]\); - - \Rdata_RNO_4[11]\ : OR2A - port map(A => \coarse_time_load[11]\, B => rdata59_0, Y => - \coarse_time_load_m[11]\); - - \Rdata[10]\ : DFN1E1C0 - port map(D => \ctrl_1[10]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(10)); - - \Rdata_RNO_2[27]\ : OA1A - port map(A => \next_commutation[27]\, B => rdata62_0, C => - \coarse_time_m[27]\, Y => \ctrl_1_0_iv_0[27]\); - - \Rdata_RNO_4[2]\ : OR2A - port map(A => \coarse_time_load[2]\, B => \rdata59\, Y => - \coarse_time_load_m[2]\); - - \Rdata_RNO_3[2]\ : OR2A - port map(A => \next_commutation[2]\, B => rdata62, Y => - \next_commutation_m[2]\); - - \Rdata_RNO_2[7]\ : OA1A - port map(A => \ctrl[7]\, B => ctrl2_0, C => - \coarse_time_load_m[7]\, Y => \ctrl_1_iv_2[7]\); - - \Rdata_RNO_0[7]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[7]\, Y => - \coarse_time_m[7]\); - - \r.ctrl[1]\ : DFN1E1C0 - port map(D => pwdata_1_0, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[1]\); - - \Rdata_RNO_3[11]\ : OR2A - port map(A => \next_commutation[11]\, B => rdata62, Y => - \next_commutation_m[11]\); - - \Rdata_RNO_2[13]\ : OA1A - port map(A => \ctrl[13]\, B => ctrl2_0, C => - \coarse_time_load_m[13]\, Y => \ctrl_1_iv_2[13]\); - - un1_apbi_4 : OR2 - port map(A => un1_apbi_0, B => psel(15), Y => \un1_apbi_4\); - - \Rdata_RNO_2[24]\ : OA1A - port map(A => \next_commutation[24]\, B => rdata62_0, C => - \coarse_time_m[24]\, Y => \ctrl_1_0_iv_0[24]\); - - \r.ctrl[13]\ : DFN1E1C0 - port map(D => pwdata_11, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[13]\); - - \Rdata_RNO[0]\ : OR3C - port map(A => \coarse_time_m[0]\, B => \ctrl_1_iv_0[0]\, C - => \ctrl_1_iv_2[0]\, Y => \ctrl_1[0]\); - - \r.ctrl[27]\ : DFN1E1C0 - port map(D => pwdata_25, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[27]\); - - \r.coarse_time_load_RNO[15]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_134, Y => - \coarse_time_load_3[15]\); - - \Rdata_RNO_2[31]\ : OA1A - port map(A => \next_commutation[31]\, B => rdata62_0, C => - \coarse_time_m[31]\, Y => \ctrl_1_0_iv_0[31]\); - - \Rdata_RNO_0[2]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[2]\, Y => - \coarse_time_m[2]\); - - \r.ctrl[8]\ : DFN1E1C0 - port map(D => pwdata_6, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[8]\); - - \Rdata[2]\ : DFN1E1C0 - port map(D => \ctrl_1[2]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(2)); - - \Rdata_RNO_1[15]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[15]\, C => - \next_commutation_m[15]\, Y => \ctrl_1_iv_0[15]\); - - \r.coarse_time_load_RNO_0[22]\ : MX2C - port map(A => pwdata_20, B => \coarse_time_load[22]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_141); - - \Rdata_RNO_0[10]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[10]\, Y => - \coarse_time_m[10]\); - - \r.next_commutation[6]\ : DFN1E1P0 - port map(D => pwdata_4, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[6]\); - - \r.coarse_time_load[12]\ : DFN1C0 - port map(D => \coarse_time_load_3[12]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[12]\); - - \r.coarse_time_load_RNO_0[11]\ : MX2C - port map(A => pwdata_0(11), B => \coarse_time_load[11]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_130); - - \Rdata_RNO_4[0]\ : OR2A - port map(A => \coarse_time_load[0]\, B => \rdata59\, Y => - \coarse_time_load_m[0]\); - - \Rdata_RNO_1[18]\ : OR2A - port map(A => \ctrl[18]\, B => \ctrl2\, Y => \ctrl_m[18]\); - - \Rdata[4]\ : DFN1E1C0 - port map(D => \ctrl_1[4]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(4)); - - \r.coarse_time_load_RNO_0[15]\ : MX2C - port map(A => pwdata_0(15), B => \coarse_time_load[15]\, S - => coarse_time_load_1_sqmuxa_i, Y => N_134); - - \r.coarse_time_load_RNO[27]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_146, Y => - \coarse_time_load_3[27]\); - - \Rdata_RNO_0[5]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[5]\, Y => - \coarse_time_m[5]\); - - \r.next_commutation[11]\ : DFN1E1P0 - port map(D => pwdata_9, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[11]\); - - \r.next_commutation[15]\ : DFN1E1P0 - port map(D => pwdata_13, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[15]\); - - \Rdata_RNO_2[9]\ : OA1A - port map(A => \ctrl[9]\, B => ctrl2_0, C => - \coarse_time_load_m[9]\, Y => \ctrl_1_iv_2[9]\); - - \r.coarse_time_load_RNO[26]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_145, Y => - \coarse_time_load_3[26]\); - - \Rdata_RNO[8]\ : OR3C - port map(A => \coarse_time_m[8]\, B => \ctrl_1_iv_0[8]\, C - => \ctrl_1_iv_2[8]\, Y => \ctrl_1[8]\); - - \Rdata_RNO_4[12]\ : OR2A - port map(A => \coarse_time_load[12]\, B => rdata59_0, Y => - \coarse_time_load_m[12]\); - - \Rdata_RNO[28]\ : OR3C - port map(A => \coarse_time_load_m[28]\, B => \ctrl_m[28]\, - C => \ctrl_1_0_iv_0[28]\, Y => \ctrl_1[28]\); - - \Rdata_RNO_0[6]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[6]\, Y => - \coarse_time_m[6]\); - - \r.coarse_time_load[19]\ : DFN1C0 - port map(D => \coarse_time_load_3[19]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[19]\); - - \Rdata_RNO_1[29]\ : OR2A - port map(A => \ctrl[29]\, B => \ctrl2\, Y => \ctrl_m[29]\); - - \r.coarse_time_load_RNO[4]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_123, Y => - \coarse_time_load_3[4]\); - - \r.coarse_time_load_RNO_0[2]\ : MX2C - port map(A => pwdata_0(2), B => \coarse_time_load[2]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_121); - - \r.ctrl[17]\ : DFN1E1C0 - port map(D => pwdata_15, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[17]\); - - \Rdata[21]\ : DFN1E1C0 - port map(D => \ctrl_1[21]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(21)); - - \r.next_commutation[10]\ : DFN1E1P0 - port map(D => pwdata_8, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[10]\); - - \Rdata_RNO_3[12]\ : OR2A - port map(A => \next_commutation[12]\, B => rdata62, Y => - \next_commutation_m[12]\); - - \Rdata_RNO[21]\ : OR3C - port map(A => \coarse_time_load_m[21]\, B => \ctrl_m[21]\, - C => \ctrl_1_0_iv_0[21]\, Y => \ctrl_1[21]\); - - \Rdata_RNO_0[17]\ : OR2A - port map(A => \coarse_time_load[17]\, B => rdata59_0, Y => - \coarse_time_load_m[17]\); - - \r.coarse_time_load_RNO_0[27]\ : MX2C - port map(A => pwdata_25, B => \coarse_time_load[27]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_146); - - un1_apbi_8_0 : OR2 - port map(A => paddr(7), B => \N_770\, Y => \un1_apbi_8_0\); - - \r.coarse_time_load_RNO[24]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_143, Y => - \coarse_time_load_3[24]\); - - \Rdata_RNO_0[23]\ : OR2A - port map(A => \coarse_time_load[23]\, B => \rdata59\, Y => - \coarse_time_load_m[23]\); - - \r.coarse_time_load_1_sqmuxa\ : OR2 - port map(A => \rdata59\, B => \un1_apbi_4\, Y => - coarse_time_load_1_sqmuxa_i); - - \Rdata_RNO_4[16]\ : OR2A - port map(A => \coarse_time_load[16]\, B => rdata59_0, Y => - \coarse_time_load_m[16]\); - - \Rdata_RNO_2[15]\ : AND2 - port map(A => \coarse_time_load_m[15]\, B => \ctrl_m[15]\, - Y => \ctrl_1_iv_2[15]\); - - \Rdata_RNO_0[14]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[14]\, Y => - \coarse_time_m[14]\); - - \Rdata_RNO_1[11]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[11]\, C => - \next_commutation_m[11]\, Y => \ctrl_1_iv_0[11]\); - - \Rdata[8]\ : DFN1E1C0 - port map(D => \ctrl_1[8]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(8)); - - \Rdata_RNO_3[23]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[23]\, Y => - \coarse_time_m[23]\); - - \Rdata_RNO_2[18]\ : OA1A - port map(A => \next_commutation[18]\, B => rdata62_0, C => - \coarse_time_m[18]\, Y => \ctrl_1_0_iv_0[18]\); - - \r.coarse_time_load_RNO[19]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_138, Y => - \coarse_time_load_3[19]\); - - \r.coarse_time_load[17]\ : DFN1C0 - port map(D => \coarse_time_load_3[17]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[17]\); - - \r.coarse_time_load_RNO_0[14]\ : MX2C - port map(A => pwdata_0(14), B => \coarse_time_load[14]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_133); - - \Rdata_RNO_3[16]\ : OR2A - port map(A => \next_commutation[16]\, B => rdata62, Y => - \next_commutation_m[16]\); - - \r.next_commutation[3]\ : DFN1E1P0 - port map(D => pwdata_1_2, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[3]\); - - \r.next_commutation[13]\ : DFN1E1P0 - port map(D => pwdata_11, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[13]\); - - \Rdata_RNO_4[5]\ : OR2A - port map(A => \coarse_time_load[5]\, B => rdata59_0, Y => - \coarse_time_load_m[5]\); - - \Rdata_RNO_2[2]\ : OA1A - port map(A => \ctrl[2]\, B => ctrl2_0, C => - \coarse_time_load_m[2]\, Y => \ctrl_1_iv_2[2]\); - - \r.coarse_time_load_RNO[30]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_149, Y => - \coarse_time_load_3[30]\); - - \Rdata_RNO_1[8]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[8]\, C => - \next_commutation_m[8]\, Y => \ctrl_1_iv_0[8]\); - - \r.coarse_time_load_RNO_0[30]\ : MX2C - port map(A => pwdata_28, B => \coarse_time_load[30]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_149); - - \Rdata_RNO_3[3]\ : OR2A - port map(A => \next_commutation[3]\, B => rdata62, Y => - \next_commutation_m[3]\); - - \Rdata[28]\ : DFN1E1C0 - port map(D => \ctrl_1[28]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(28)); - - \Rdata_RNO[16]\ : OR3C - port map(A => \coarse_time_m[16]\, B => \ctrl_1_iv_0[16]\, - C => \ctrl_1_iv_2[16]\, Y => \ctrl_1[16]\); - - \Rdata_RNO_2[5]\ : OA1A - port map(A => \ctrl[5]\, B => ctrl2_0, C => - \coarse_time_load_m[5]\, Y => \ctrl_1_iv_2[5]\); - - \r.coarse_time_load_RNO[28]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_147, Y => - \coarse_time_load_3[28]\); - - \Rdata_RNO[30]\ : OR3C - port map(A => \coarse_time_load_m[30]\, B => \ctrl_m[30]\, - C => \ctrl_1_0_iv_0[30]\, Y => \ctrl_1[30]\); - - \Rdata[29]\ : DFN1E1C0 - port map(D => \ctrl_1[29]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(29)); - - \r.ctrl[25]\ : DFN1E1C0 - port map(D => pwdata_23, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[25]\); - - \r.coarse_time_load_RNO[8]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_127, Y => - \coarse_time_load_3[8]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \Rdata_RNO_3[0]\ : OR2A - port map(A => \next_commutation[0]\, B => rdata62, Y => - \next_commutation_m[0]\); - - \Rdata_RNO_4[10]\ : OR2A - port map(A => \coarse_time_load[10]\, B => rdata59_0, Y => - \coarse_time_load_m[10]\); - - \Rdata_RNO_2[29]\ : OA1A - port map(A => \next_commutation[29]\, B => rdata62_0, C => - \coarse_time_m[29]\, Y => \ctrl_1_0_iv_0[29]\); - - \Rdata_RNO[15]\ : OR3C - port map(A => \coarse_time_m[15]\, B => \ctrl_1_iv_0[15]\, - C => \ctrl_1_iv_2[15]\, Y => \ctrl_1[15]\); - - \Rdata_RNO_4[4]\ : OR2A - port map(A => \coarse_time_load[4]\, B => rdata59_0, Y => - \coarse_time_load_m[4]\); - - \Rdata_RNO_5[8]\ : OR2A - port map(A => \ctrl[8]\, B => ctrl2_0, Y => \ctrl_m[8]\); - - \Rdata_RNO_4[1]\ : OR2A - port map(A => \coarse_time_load[1]\, B => \rdata59\, Y => - \coarse_time_load_m[1]\); - - \Rdata_RNO[9]\ : OR3C - port map(A => \coarse_time_m[9]\, B => \ctrl_1_iv_0[9]\, C - => \ctrl_1_iv_2[9]\, Y => \ctrl_1[9]\); - - \Rdata_RNO_2[11]\ : AND2 - port map(A => \coarse_time_load_m[11]\, B => \ctrl_m[11]\, - Y => \ctrl_1_iv_2[11]\); - - rdata78_0 : NOR2 - port map(A => \rdata62_3\, B => rdata60_4, Y => rdata60_0); - - \r.ctrl[22]\ : DFN1E1C0 - port map(D => pwdata_20, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[22]\); - - \r.coarse_time_load[15]\ : DFN1C0 - port map(D => \coarse_time_load_3[15]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[15]\); - - \Rdata_RNO_1[12]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[12]\, C => - \next_commutation_m[12]\, Y => \ctrl_1_iv_0[12]\); - - \Rdata_RNO_3[10]\ : OR2A - port map(A => \next_commutation[10]\, B => rdata62, Y => - \next_commutation_m[10]\); - - \Rdata_RNO_0[25]\ : OR2A - port map(A => \coarse_time_load[25]\, B => \rdata59\, Y => - \coarse_time_load_m[25]\); - - \r.coarse_time_load_RNO[11]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_130, Y => - \coarse_time_load_3[11]\); - - \r.coarse_time_load_RNO_0[20]\ : MX2C - port map(A => pwdata_18, B => \coarse_time_load[20]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_139); - - \r.coarse_time_load[0]\ : DFN1C0 - port map(D => \coarse_time_load_3[0]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[0]\); - - \r.next_commutation[5]\ : DFN1E1P0 - port map(D => pwdata_3, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[5]\); - - \r.next_commutation[21]\ : DFN1E1P0 - port map(D => pwdata_19, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[21]\); - - \Rdata_RNO_0[28]\ : OR2A - port map(A => \coarse_time_load[28]\, B => \rdata59\, Y => - \coarse_time_load_m[28]\); - - Rdata_0_sqmuxa : NOR2 - port map(A => pwrite, B => psel(15), Y => \Rdata_0_sqmuxa\); - - \r.next_commutation[25]\ : DFN1E1P0 - port map(D => pwdata_23, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[25]\); - - \Rdata_RNO_2[30]\ : OA1A - port map(A => \next_commutation[30]\, B => rdata62_0, C => - \coarse_time_m[30]\, Y => \ctrl_1_0_iv_0[30]\); - - \Rdata_RNO_3[25]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[25]\, Y => - \coarse_time_m[25]\); - - \Rdata_RNO_2[4]\ : AND2 - port map(A => \coarse_time_load_m[4]\, B => \ctrl_m[4]\, Y - => \ctrl_1_iv_2[4]\); - - \r.next_commutation[19]\ : DFN1E1P0 - port map(D => pwdata_17, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[19]\); - - \r.ctrl[21]\ : DFN1E1C0 - port map(D => pwdata_19, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[21]\); - - \r.coarse_time_load_RNO[9]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_128, Y => - \coarse_time_load_3[9]\); - - \r.coarse_time_load[28]\ : DFN1C0 - port map(D => \coarse_time_load_3[28]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[28]\); - - \Rdata_RNO_3[28]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[28]\, Y => - \coarse_time_m[28]\); - - \Rdata_RNO_1[16]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[16]\, C => - \next_commutation_m[16]\, Y => \ctrl_1_iv_0[16]\); - - \Rdata[11]\ : DFN1E1C0 - port map(D => \ctrl_1[11]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(11)); - - \r.ctrl[15]\ : DFN1E1C0 - port map(D => pwdata_13, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[15]\); - - \r.coarse_time_load_RNO_0[0]\ : MX2C - port map(A => pwdata_0(0), B => \coarse_time_load[0]\, S - => coarse_time_load_1_sqmuxa_i, Y => N_119); - - \r.coarse_time_load[24]\ : DFN1C0 - port map(D => \coarse_time_load_3[24]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[24]\); - - \Rdata_RNO[2]\ : OR3C - port map(A => \coarse_time_m[2]\, B => \ctrl_1_iv_0[2]\, C - => \ctrl_1_iv_2[2]\, Y => \ctrl_1[2]\); - - \r.next_commutation[31]\ : DFN1E1P0 - port map(D => pwdata_29, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[31]\); - - \r.coarse_time_load_RNO_0[12]\ : MX2C - port map(A => pwdata_0(12), B => \coarse_time_load[12]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_131); - - \r.ctrl3_0\ : OR2A - port map(A => rdata59_4, B => \rdata62_3\, Y => rdata59_0); - - \r.next_commutation[14]\ : DFN1E1P0 - port map(D => pwdata_12, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[14]\); - - \r.next_commutation[20]\ : DFN1E1P0 - port map(D => pwdata_18, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[20]\); - - \Rdata_RNO_4[6]\ : OR2A - port map(A => \coarse_time_load[6]\, B => rdata59_0, Y => - \coarse_time_load_m[6]\); - - \r.ctrl[2]\ : DFN1E1C0 - port map(D => pwdata_0_d0, CLK => lclk_c, CLR => rstn, E - => N_380, Q => \ctrl[2]\); - - \Rdata_RNO_4[14]\ : OR2A - port map(A => \coarse_time_load[14]\, B => rdata59_0, Y => - \coarse_time_load_m[14]\); - - Rdata_0_sqmuxa_0 : NOR2 - port map(A => pwrite, B => psel(15), Y => - \Rdata_0_sqmuxa_0\); - - \r.ctrl[12]\ : DFN1E1C0 - port map(D => pwdata_0(12), CLK => lclk_c, CLR => rstn, E - => N_380_0, Q => \ctrl[12]\); - - \Rdata_RNO_3[17]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[17]\, Y => - \coarse_time_m[17]\); - - \r.next_commutation[16]\ : DFN1E1P0 - port map(D => pwdata_14, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[16]\); - - \Rdata_RNO_1[0]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[0]\, C => - \next_commutation_m[0]\, Y => \ctrl_1_iv_0[0]\); - - \r.ctrl_0_sqmuxa\ : NOR2 - port map(A => \un1_apbi_4\, B => \ctrl2\, Y => N_380); - - \r.coarse_time_load_RNO_0[3]\ : MX2C - port map(A => pwdata_0(3), B => \coarse_time_load[3]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_122); - - \Rdata_RNO_2[12]\ : OA1A - port map(A => \ctrl[12]\, B => ctrl2_0, C => - \coarse_time_load_m[12]\, Y => \ctrl_1_iv_2[12]\); - - \r.next_commutation[12]\ : DFN1E1P0 - port map(D => pwdata_10, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[12]\); - - \r.coarse_time_load_RNO_0[4]\ : MX2C - port map(A => pwdata_0(4), B => \coarse_time_load[4]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_123); - - rdata79 : NOR3 - port map(A => rdata61_2, B => \rdata62_3\, C => un1_apbi_2, - Y => \rdata61\); - - previous_force_tick : DFN1C0 - port map(D => \force_tick\, CLK => lclk_c, CLR => rstn, Q - => \previous_force_tick\); - - \r.ctrl[7]\ : DFN1E1C0 - port map(D => pwdata_5, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[7]\); - - \r.coarse_time_load[26]\ : DFN1C0 - port map(D => \coarse_time_load_3[26]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[26]\); - - \Rdata_RNO_3[14]\ : OR2A - port map(A => \next_commutation[14]\, B => rdata62, Y => - \next_commutation_m[14]\); - - \Rdata_RNO_0[19]\ : OR2A - port map(A => \coarse_time_load[19]\, B => rdata59_0, Y => - \coarse_time_load_m[19]\); - - un1_apbi_7_2 : OR2 - port map(A => paddr(6), B => paddr(5), Y => \N_770\); - - \Rdata[1]\ : DFN1E1C0 - port map(D => \ctrl_1[1]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(1)); - - \r.next_commutation[30]\ : DFN1E1P0 - port map(D => pwdata_28, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[30]\); - - \r.coarse_time_load_RNO_0[29]\ : MX2C - port map(A => pwdata_27, B => \coarse_time_load[29]\, S => - coarse_time_load_1_sqmuxa_i, Y => N_148); - - \Rdata_RNO_0[21]\ : OR2A - port map(A => \coarse_time_load[21]\, B => \rdata59\, Y => - \coarse_time_load_m[21]\); - - \r.coarse_time_load_RNO_0[28]\ : MX2C - port map(A => pwdata_26, B => \coarse_time_load[28]\, S => - coarse_time_load_1_sqmuxa_i_0, Y => N_147); - - \r.next_commutation[17]\ : DFN1E1P0 - port map(D => pwdata_15, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[17]\); - - \r.ctrl[11]\ : DFN1E1C0 - port map(D => pwdata_9, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[11]\); - - \r.next_commutation[9]\ : DFN1E1P0 - port map(D => pwdata_7, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[9]\); - - \Rdata_RNO_1[31]\ : OR2A - port map(A => \ctrl[31]\, B => \ctrl2\, Y => \ctrl_m[31]\); - - \r.coarse_time_load[7]\ : DFN1C0 - port map(D => \coarse_time_load_3[7]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[7]\); - - \Rdata_RNO_0[1]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[1]\, Y => - \coarse_time_m[1]\); - - \r.next_commutation_1_sqmuxa\ : NOR2 - port map(A => rdata62, B => \un1_apbi_4\, Y => - next_commutation_1_sqmuxa); - - \Rdata_RNO_3[21]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[21]\, Y => - \coarse_time_m[21]\); - - \Rdata[18]\ : DFN1E1C0 - port map(D => \ctrl_1[18]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(18)); - - \r.coarse_time_load_RNO[12]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_131, Y => - \coarse_time_load_3[12]\); - - \Rdata[30]\ : DFN1E1C0 - port map(D => \ctrl_1[30]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(30)); - - \r.next_commutation[23]\ : DFN1E1P0 - port map(D => pwdata_21, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[23]\); - - \Rdata_RNO_1[10]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[10]\, C => - \next_commutation_m[10]\, Y => \ctrl_1_iv_0[10]\); - - \Rdata[23]\ : DFN1E1C0 - port map(D => \ctrl_1[23]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(23)); - - soft_tick_1 : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick_1\); - - \r.coarse_time_load_RNO_0[17]\ : MX2C - port map(A => pwdata_15, B => \coarse_time_load[17]\, S => - coarse_time_load_1_sqmuxa_i_0, Y => N_136); - - \Rdata_RNO_2[16]\ : OA1A - port map(A => \ctrl[16]\, B => ctrl2_0, C => - \coarse_time_load_m[16]\, Y => \ctrl_1_iv_2[16]\); - - \Rdata_RNO[1]\ : OR3C - port map(A => \coarse_time_m[1]\, B => \ctrl_1_iv_0[1]\, C - => \ctrl_1_iv_2[1]\, Y => \ctrl_1[1]\); - - \Rdata[19]\ : DFN1E1C0 - port map(D => \ctrl_1[19]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(19)); - - \r.next_commutation[1]\ : DFN1E1P0 - port map(D => pwdata_1_0, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[1]\); - - soft_tick_2 : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick_2\); - - \r.ctrl[3]\ : DFN1E1C0 - port map(D => pwdata_1_2, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[3]\); - - \Rdata_RNO_3[8]\ : OR2A - port map(A => \next_commutation[8]\, B => rdata62, Y => - \next_commutation_m[8]\); - - \Rdata[0]\ : DFN1E1C0 - port map(D => \ctrl_1[0]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(0)); - - force_tick : DFN1C0 - port map(D => \ctrl[0]\, CLK => lclk_c, CLR => rstn, Q => - \force_tick\); - - \Rdata_RNO_3[6]\ : OR2A - port map(A => \next_commutation[6]\, B => rdata62, Y => - \next_commutation_m[6]\); - - \Rdata_RNO_0[3]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[3]\, Y => - \coarse_time_m[3]\); - - \r.coarse_time_load[8]\ : DFN1C0 - port map(D => \coarse_time_load_3[8]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[8]\); - - \Rdata_RNO_1[23]\ : OR2A - port map(A => \ctrl[23]\, B => \ctrl2\, Y => \ctrl_m[23]\); - - \Rdata_RNO[7]\ : OR3C - port map(A => \coarse_time_m[7]\, B => \ctrl_1_iv_0[7]\, C - => \ctrl_1_iv_2[7]\, Y => \ctrl_1[7]\); - - \r.coarse_time_load_RNO[23]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_142, Y => - \coarse_time_load_3[23]\); - - \r.coarse_time_load[22]\ : DFN1C0 - port map(D => \coarse_time_load_3[22]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[22]\); - - \Rdata[25]\ : DFN1E1C0 - port map(D => \ctrl_1[25]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(25)); - - \r.coarse_time_load_1_sqmuxa_0\ : OR2 - port map(A => rdata59_0, B => \un1_apbi_4_0\, Y => - coarse_time_load_1_sqmuxa_i_0); - - \Rdata_RNO_3[9]\ : OR2A - port map(A => \next_commutation[9]\, B => rdata62, Y => - \next_commutation_m[9]\); - - \Rdata_RNO_1[17]\ : OR2A - port map(A => \ctrl[17]\, B => \ctrl2\, Y => \ctrl_m[17]\); - - \Rdata_RNO_0[22]\ : OR2A - port map(A => \coarse_time_load[22]\, B => \rdata59\, Y => - \coarse_time_load_m[22]\); - - lfrtimemanagement0 : lfr_time_management - port map(pirq(13) => pirq(13), pirq(12) => pirq(12), - coarse_time_load(31) => \coarse_time_load[31]\, - coarse_time_load(30) => \coarse_time_load[30]\, - coarse_time_load(29) => \coarse_time_load[29]\, - coarse_time_load(28) => \coarse_time_load[28]\, - coarse_time_load(27) => \coarse_time_load[27]\, - coarse_time_load(26) => \coarse_time_load[26]\, - coarse_time_load(25) => \coarse_time_load[25]\, - coarse_time_load(24) => \coarse_time_load[24]\, - coarse_time_load(23) => \coarse_time_load[23]\, - coarse_time_load(22) => \coarse_time_load[22]\, - coarse_time_load(21) => \coarse_time_load[21]\, - coarse_time_load(20) => \coarse_time_load[20]\, - coarse_time_load(19) => \coarse_time_load[19]\, - coarse_time_load(18) => \coarse_time_load[18]\, - coarse_time_load(17) => \coarse_time_load[17]\, - coarse_time_load(16) => \coarse_time_load[16]\, - coarse_time_load(15) => \coarse_time_load[15]\, - coarse_time_load(14) => \coarse_time_load[14]\, - coarse_time_load(13) => \coarse_time_load[13]\, - coarse_time_load(12) => \coarse_time_load[12]\, - coarse_time_load(11) => \coarse_time_load[11]\, - coarse_time_load(10) => \coarse_time_load[10]\, - coarse_time_load(9) => \coarse_time_load[9]\, - coarse_time_load(8) => \coarse_time_load[8]\, - coarse_time_load(7) => \coarse_time_load[7]\, - coarse_time_load(6) => \coarse_time_load[6]\, - coarse_time_load(5) => \coarse_time_load[5]\, - coarse_time_load(4) => \coarse_time_load[4]\, - coarse_time_load(3) => \coarse_time_load[3]\, - coarse_time_load(2) => \coarse_time_load[2]\, - coarse_time_load(1) => \coarse_time_load[1]\, - coarse_time_load(0) => \coarse_time_load[0]\, - next_commutation(31) => \next_commutation[31]\, - next_commutation(30) => \next_commutation[30]\, - next_commutation(29) => \next_commutation[29]\, - next_commutation(28) => \next_commutation[28]\, - next_commutation(27) => \next_commutation[27]\, - next_commutation(26) => \next_commutation[26]\, - next_commutation(25) => \next_commutation[25]\, - next_commutation(24) => \next_commutation[24]\, - next_commutation(23) => \next_commutation[23]\, - next_commutation(22) => \next_commutation[22]\, - next_commutation(21) => \next_commutation[21]\, - next_commutation(20) => \next_commutation[20]\, - next_commutation(19) => \next_commutation[19]\, - next_commutation(18) => \next_commutation[18]\, - next_commutation(17) => \next_commutation[17]\, - next_commutation(16) => \next_commutation[16]\, - next_commutation(15) => \next_commutation[15]\, - next_commutation(14) => \next_commutation[14]\, - next_commutation(13) => \next_commutation[13]\, - next_commutation(12) => \next_commutation[12]\, - next_commutation(11) => \next_commutation[11]\, - next_commutation(10) => \next_commutation[10]\, - next_commutation(9) => \next_commutation[9]\, - next_commutation(8) => \next_commutation[8]\, - next_commutation(7) => \next_commutation[7]\, - next_commutation(6) => \next_commutation[6]\, - next_commutation(5) => \next_commutation[5]\, - next_commutation(4) => \next_commutation[4]\, - next_commutation(3) => \next_commutation[3]\, - next_commutation(2) => \next_commutation[2]\, - next_commutation(1) => \next_commutation[1]\, - next_commutation(0) => \next_commutation[0]\, - coarse_time(31) => \coarse_time[31]\, coarse_time(30) => - \coarse_time[30]\, coarse_time(29) => \coarse_time[29]\, - coarse_time(28) => \coarse_time[28]\, coarse_time(27) => - \coarse_time[27]\, coarse_time(26) => \coarse_time[26]\, - coarse_time(25) => \coarse_time[25]\, coarse_time(24) => - \coarse_time[24]\, coarse_time(23) => \coarse_time[23]\, - coarse_time(22) => \coarse_time[22]\, coarse_time(21) => - \coarse_time[21]\, coarse_time(20) => \coarse_time[20]\, - coarse_time(19) => \coarse_time[19]\, coarse_time(18) => - \coarse_time[18]\, coarse_time(17) => \coarse_time[17]\, - coarse_time(16) => \coarse_time[16]\, coarse_time(15) => - \coarse_time[15]\, coarse_time(14) => \coarse_time[14]\, - coarse_time(13) => \coarse_time[13]\, coarse_time(12) => - \coarse_time[12]\, coarse_time(11) => \coarse_time[11]\, - coarse_time(10) => \coarse_time[10]\, coarse_time(9) => - \coarse_time[9]\, coarse_time(8) => \coarse_time[8]\, - coarse_time(7) => \coarse_time[7]\, coarse_time(6) => - \coarse_time[6]\, coarse_time(5) => \coarse_time[5]\, - coarse_time(4) => \coarse_time[4]\, coarse_time(3) => - \coarse_time[3]\, coarse_time(2) => \coarse_time[2]\, - coarse_time(1) => \coarse_time[1]\, coarse_time(0) => - \coarse_time[0]\, coarse_time_i(0) => coarse_time_i(0), - fine_time(16) => \fine_time[16]\, fine_time(15) => - \fine_time[15]\, fine_time(14) => \fine_time[14]\, - fine_time(13) => \fine_time[13]\, fine_time(12) => - \fine_time[12]\, fine_time(11) => \fine_time[11]\, - fine_time(10) => \fine_time[10]\, fine_time(9) => - \fine_time[9]\, fine_time(8) => \fine_time[8]\, - fine_time(7) => \fine_time[7]\, fine_time(6) => - \fine_time[6]\, fine_time(5) => \fine_time[5]\, - fine_time(4) => \fine_time[4]\, fine_time(3) => - \fine_time[3]\, fine_time(2) => \fine_time[2]\, - fine_time(1) => \fine_time[1]\, fine_time(0) => - \fine_time[0]\, clk49_152MHz_c_0 => clk49_152MHz_c_0, - clk49_152MHz_c => clk49_152MHz_c, lclk_c => lclk_c, - soft_tick => \soft_tick\, rstn_i => rstn_i, soft_tick_3 - => \soft_tick_3\, soft_tick_2 => \soft_tick_2\, - soft_tick_1 => \soft_tick_1\, soft_tick_0 => - \soft_tick_0\, rstn => rstn); - - \Rdata_RNO[19]\ : OR3C - port map(A => \coarse_time_load_m[19]\, B => \ctrl_m[19]\, - C => \ctrl_1_0_iv_0[19]\, Y => \ctrl_1[19]\); - - \r.ctrl3\ : OR2A - port map(A => rdata59_4, B => \rdata62_3\, Y => \rdata59\); - - \Rdata_RNO[26]\ : OR3C - port map(A => \coarse_time_load_m[26]\, B => \ctrl_m[26]\, - C => \ctrl_1_0_iv_0[26]\, Y => \ctrl_1[26]\); - - \r.ctrl[5]\ : DFN1E1C0 - port map(D => pwdata_3, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[5]\); - - \r.coarse_time_load_RNO[10]\ : OA1B - port map(A => \un1_apbi_4_0\, B => - coarse_time_load_2_sqmuxa_0_0, C => N_129, Y => - \coarse_time_load_3[10]\); - - \Rdata_RNO_3[22]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[22]\, Y => - \coarse_time_m[22]\); - - \Rdata_RNO_2[10]\ : OA1A - port map(A => \ctrl[10]\, B => ctrl2_0, C => - \coarse_time_load_m[10]\, Y => \ctrl_1_iv_2[10]\); - - \Rdata_RNO_1[14]\ : AOI1B - port map(A => \rdata61\, B => \fine_time[14]\, C => - \next_commutation_m[14]\, Y => \ctrl_1_iv_0[14]\); - - \Rdata_RNO[6]\ : OR3C - port map(A => \coarse_time_m[6]\, B => \ctrl_1_iv_0[6]\, C - => \ctrl_1_iv_2[6]\, Y => \ctrl_1[6]\); - - \Rdata[7]\ : DFN1E1C0 - port map(D => \ctrl_1[7]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa\, Q => prdata(7)); - - \r.coarse_time_load_RNO_0[9]\ : MX2C - port map(A => pwdata_0(9), B => \coarse_time_load[9]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_128); - - \r.next_commutation[29]\ : DFN1E1P0 - port map(D => pwdata_27, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[29]\); - - \Rdata_RNO_5[15]\ : OR2A - port map(A => \ctrl[15]\, B => ctrl2_0, Y => \ctrl_m[15]\); - - \Rdata_RNO[13]\ : OR3C - port map(A => \coarse_time_m[13]\, B => \ctrl_1_iv_0[13]\, - C => \ctrl_1_iv_2[13]\, Y => \ctrl_1[13]\); - - \r.ctrl[20]\ : DFN1E1C0 - port map(D => pwdata_18, CLK => lclk_c, CLR => rstn, E => - N_380_0, Q => \ctrl[20]\); - - \r.coarse_time_load[29]\ : DFN1C0 - port map(D => \coarse_time_load_3[29]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[29]\); - - \Rdata_RNO[25]\ : OR3C - port map(A => \coarse_time_load_m[25]\, B => \ctrl_m[25]\, - C => \ctrl_1_0_iv_0[25]\, Y => \ctrl_1[25]\); - - \r.coarse_time_load[3]\ : DFN1C0 - port map(D => \coarse_time_load_3[3]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[3]\); - - \r.coarse_time_load[2]\ : DFN1C0 - port map(D => \coarse_time_load_3[2]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[2]\); - - \Rdata_RNO_0[9]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[9]\, Y => - \coarse_time_m[9]\); - - \Rdata_RNO_0[26]\ : OR2A - port map(A => \coarse_time_load[26]\, B => \rdata59\, Y => - \coarse_time_load_m[26]\); - - \Rdata_RNO_3[31]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[31]\, Y => - \coarse_time_m[31]\); - - \r.coarse_time_load_RNO[25]\ : OA1B - port map(A => \un1_apbi_4\, B => - coarse_time_load_2_sqmuxa_0, C => N_144, Y => - \coarse_time_load_3[25]\); - - \Rdata_RNO[10]\ : OR3C - port map(A => \coarse_time_m[10]\, B => \ctrl_1_iv_0[10]\, - C => \ctrl_1_iv_2[10]\, Y => \ctrl_1[10]\); - - \r.coarse_time_load_RNO_0[10]\ : MX2C - port map(A => pwdata_0(10), B => \coarse_time_load[10]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_129); - - \r.next_commutation[24]\ : DFN1E1P0 - port map(D => pwdata_22, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[24]\); - - \Rdata_RNO_3[26]\ : OR2B - port map(A => \rdata60\, B => \coarse_time[26]\, Y => - \coarse_time_m[26]\); - - \r.next_commutation[4]\ : DFN1E1P0 - port map(D => pwdata_1_3, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[4]\); - - \Rdata_RNO[14]\ : OR3C - port map(A => \coarse_time_m[14]\, B => \ctrl_1_iv_0[14]\, - C => \ctrl_1_iv_2[14]\, Y => \ctrl_1[14]\); - - \r.next_commutation[26]\ : DFN1E1P0 - port map(D => pwdata_24, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[26]\); - - \r.ctrl[31]\ : DFN1E1C0 - port map(D => pwdata_29, CLK => lclk_c, CLR => rstn, E => - N_380, Q => \ctrl[31]\); - - \Rdata_RNO[17]\ : OR3C - port map(A => \coarse_time_load_m[17]\, B => \ctrl_m[17]\, - C => \ctrl_1_0_iv_0[17]\, Y => \ctrl_1[17]\); - - \Rdata_RNO_5[3]\ : OR2A - port map(A => \ctrl[3]\, B => ctrl2_0, Y => \ctrl_m[3]\); - - \r.next_commutation[22]\ : DFN1E1P0 - port map(D => pwdata_20, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa_0, Q => \next_commutation[22]\); - - \r.coarse_time_load[27]\ : DFN1C0 - port map(D => \coarse_time_load_3[27]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[27]\); - - \r.coarse_time_load[1]\ : DFN1C0 - port map(D => \coarse_time_load_3[1]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[1]\); - - \Rdata_RNO_2[17]\ : OA1A - port map(A => \next_commutation[17]\, B => rdata62_0, C => - \coarse_time_m[17]\, Y => \ctrl_1_0_iv_0[17]\); - - \Rdata_RNO_0[31]\ : OR2A - port map(A => \coarse_time_load[31]\, B => \rdata59\, Y => - \coarse_time_load_m[31]\); - - \Rdata_RNO_2[3]\ : AND2 - port map(A => \coarse_time_load_m[3]\, B => \ctrl_m[3]\, Y - => \ctrl_1_iv_2[3]\); - - \r.coarse_time_load_RNO_0[1]\ : MX2C - port map(A => pwdata_0(1), B => \coarse_time_load[1]\, S - => coarse_time_load_1_sqmuxa_i_0, Y => N_120); - - \Rdata_RNO_3[19]\ : OR2B - port map(A => rdata60_0, B => \coarse_time[19]\, Y => - \coarse_time_m[19]\); - - \Rdata_RNO_2[23]\ : OA1A - port map(A => \next_commutation[23]\, B => rdata62_0, C => - \coarse_time_m[23]\, Y => \ctrl_1_0_iv_0[23]\); - - \Rdata_RNO_1[25]\ : OR2A - port map(A => \ctrl[25]\, B => \ctrl2\, Y => \ctrl_m[25]\); - - previous_force_tick_RNIKV47 : NOR2A - port map(A => \force_tick\, B => \previous_force_tick\, Y - => \previous_force_tick_RNIKV47\); - - \Rdata[13]\ : DFN1E1C0 - port map(D => \ctrl_1[13]\, CLK => lclk_c, CLR => rstn, E - => \Rdata_0_sqmuxa_0\, Q => prdata(13)); - - \r.next_commutation[27]\ : DFN1E1P0 - port map(D => pwdata_25, CLK => lclk_c, PRE => rstn, E => - next_commutation_1_sqmuxa, Q => \next_commutation[27]\); - - \Rdata_RNO[4]\ : OR3C - port map(A => \coarse_time_m[4]\, B => \ctrl_1_iv_0[4]\, C - => \ctrl_1_iv_2[4]\, Y => \ctrl_1[4]\); - - \Rdata_RNO_1[28]\ : OR2A - port map(A => \ctrl[28]\, B => \ctrl2\, Y => \ctrl_m[28]\); - - \Rdata_RNO_2[14]\ : AND2 - port map(A => \coarse_time_load_m[14]\, B => \ctrl_m[14]\, - Y => \ctrl_1_iv_2[14]\); - - \r.ctrl[10]\ : DFN1E1C0 - port map(D => pwdata_0(10), CLK => lclk_c, CLR => rstn, E - => N_380_0, Q => \ctrl[10]\); - - \r.coarse_time_load[10]\ : DFN1C0 - port map(D => \coarse_time_load_3[10]\, CLK => lclk_c, CLR - => rstn, Q => \coarse_time_load[10]\); - - \Rdata_RNO[12]\ : OR3C - port map(A => \coarse_time_m[12]\, B => \ctrl_1_iv_0[12]\, - C => \ctrl_1_iv_2[12]\, Y => \ctrl_1[12]\); - - soft_tick_3 : DFN1C0 - port map(D => \previous_force_tick_RNIKV47\, CLK => lclk_c, - CLR => rstn, Q => \soft_tick_3\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity rstgen is - - port( rstgen_VCC : in std_logic; - rstraw_c : in std_logic; - lclk_c : in std_logic; - m26_m1_e : in std_logic; - rstoutl_RNIGJKSJO : out std_logic; - rstn_i : out std_logic; - rstn : out std_logic - ); - -end rstgen; - -architecture DEF_ARCH of rstgen is - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1C0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - CLR : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - signal \rstoutl\, \rstn\, rstoutl_1, \r[2]_net_1\, - \r[4]_net_1\, \r[3]_net_1\, \r[0]_net_1\, \r[1]_net_1\, - \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - rstn <= \rstn\; - - rstoutl_RNIQRB1_0 : INV - port map(A => \rstn\, Y => rstn_i); - - \rstoutl_RNIGJKSJO\ : OR2B - port map(A => m26_m1_e, B => \rstn\, Y => rstoutl_RNIGJKSJO); - - \r[2]\ : DFN1C0 - port map(D => \r[1]_net_1\, CLK => lclk_c, CLR => rstraw_c, - Q => \r[2]_net_1\); - - \r[0]\ : DFN1C0 - port map(D => rstgen_VCC, CLK => lclk_c, CLR => rstraw_c, Q - => \r[0]_net_1\); - - rstoutl_RNO : NOR3C - port map(A => \r[2]_net_1\, B => \r[4]_net_1\, C => - \r[3]_net_1\, Y => rstoutl_1); - - rstoutl : DFN1C0 - port map(D => rstoutl_1, CLK => lclk_c, CLR => rstraw_c, Q - => \rstoutl\); - - rstoutl_RNIQRB1 : CLKINT - port map(A => \rstoutl\, Y => \rstn\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - VCC_i : VCC - port map(Y => \VCC\); - - \r[4]\ : DFN1C0 - port map(D => \r[3]_net_1\, CLK => lclk_c, CLR => rstraw_c, - Q => \r[4]_net_1\); - - GND_i_0 : GND - port map(Y => GND_0); - - GND_i : GND - port map(Y => \GND\); - - \r[3]\ : DFN1C0 - port map(D => \r[2]_net_1\, CLK => lclk_c, CLR => rstraw_c, - Q => \r[3]_net_1\); - - \r[1]\ : DFN1C0 - port map(D => \r[0]_net_1\, CLK => lclk_c, CLR => rstraw_c, - Q => \r[1]_net_1\); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity mctrl is - - port( data_in : in std_logic_vector(31 downto 0); - hresp : out std_logic_vector(0 to 0); - address : out std_logic_vector(31 downto 28); - romsn_c : out std_logic_vector(1 downto 0); - ramoen_c : out std_logic_vector(3 downto 0); - hmbsel_1 : in std_logic_vector(0 to 0); - hburst_0 : in std_logic_vector(2 downto 0); - hmbsel : in std_logic_vector(0 to 0); - ramrws_1 : out std_logic; - ramwws : out std_logic_vector(1 downto 0); - pwdata_1_3 : in std_logic; - pwdata_1_0 : in std_logic; - pwdata_1_2 : in std_logic; - rwen_c : out std_logic_vector(3 downto 0); - iosn_1_8 : in std_logic; - iosn_1_0 : in std_logic; - ramsn_c : out std_logic_vector(3 downto 0); - rambanksz_0 : out std_logic; - rambanksz_1 : out std_logic; - rambanksz_3 : out std_logic; - paddr_2 : in std_logic_vector(2 to 2); - iows_3 : out std_logic; - iows_2 : out std_logic; - pwdata_23 : in std_logic; - pwdata_22 : in std_logic; - pwdata_0_d0 : in std_logic; - pwdata_7 : in std_logic; - pwdata_6 : in std_logic; - pwdata_5 : in std_logic; - pwdata_4 : in std_logic; - pwdata_1_d0 : in std_logic; - pwdata_18 : in std_logic; - pwdata_17 : in std_logic; - pwdata_16 : in std_logic; - pwdata_15 : in std_logic; - pwdata_20 : in std_logic; - pwdata_21 : in std_logic; - pwdata_14 : in std_logic; - pwdata_0_5 : in std_logic; - pwdata_0_7 : in std_logic; - pwdata_0_8 : in std_logic; - pwdata_0_9 : in std_logic; - pwdata_0_2 : in std_logic; - pwdata_0_1 : in std_logic; - pwdata_0_0 : in std_logic; - pwdata_0_6 : in std_logic; - pwdata_0_11 : in std_logic; - hsize : in std_logic_vector(1 downto 0); - romrws_1 : out std_logic; - romrws_3 : out std_logic; - romrws_2 : out std_logic; - hwdata_m_0_3 : in std_logic; - hwdata_m_0_2 : in std_logic; - hwdata_m_0_0 : in std_logic; - psel : in std_logic_vector(0 to 0); - romwidth : out std_logic_vector(1 downto 0); - iosn_100 : in std_logic; - iosn_99 : in std_logic; - address_c : out std_logic_vector(27 downto 0); - hwdata_m_8 : in std_logic; - hwdata_m_7 : in std_logic; - hwdata_m_5 : in std_logic; - hwdata_m_0_d0 : in std_logic; - hwdata_m_13 : in std_logic; - data : out std_logic_vector(31 downto 0); - haddr : in std_logic_vector(30 downto 0); - ramwidth : out std_logic_vector(1 downto 0); - htrans : in std_logic_vector(1 downto 0); - iosn_0 : in std_logic_vector(93 to 93); - hsel_i : in std_logic_vector(0 to 0); - romwws : out std_logic_vector(3 downto 0); - prdata_0 : out std_logic; - prdata_1 : out std_logic; - prdata_8 : out std_logic; - prdata_7 : out std_logic; - hrdata : out std_logic_vector(31 downto 0); - hwdata_4 : in std_logic; - hwdata_3 : in std_logic; - hwdata_8 : in std_logic; - hwdata_13 : in std_logic; - hwdata_24 : in std_logic; - hwdata_23 : in std_logic; - hwdata_22 : in std_logic; - hwdata_20 : in std_logic; - hwdata_10 : in std_logic; - hwdata_26 : in std_logic; - hwdata_9 : in std_logic; - hwdata_16 : in std_logic; - hwdata_17 : in std_logic; - hwdata_7 : in std_logic; - hwdata_30 : in std_logic; - hwdata_28 : in std_logic; - hwdata_5 : in std_logic; - hwdata_31 : in std_logic; - hwdata_1 : in std_logic; - hwdata_19 : in std_logic; - hwdata_29 : in std_logic; - hwdata_21 : in std_logic; - hwdata_18 : in std_logic; - hwdata_0 : in std_logic; - hwdata_6 : in std_logic; - hwdata_2 : in std_logic; - hwdata_27 : in std_logic; - hwdata_11 : in std_logic; - hwdata_25 : in std_logic; - bdrive_i : out std_logic_vector(3 downto 0); - paddr : in std_logic_vector(3 downto 2); - iosn_c : out std_logic; - lclk_c : in std_logic; - N_6455 : out std_logic; - N_5062 : out std_logic; - un6_ioen_NE_0 : in std_logic; - N_510 : out std_logic; - N_6459 : in std_logic; - N_5070 : out std_logic; - bexcen : out std_logic; - brdyen : out std_logic; - ioen : out std_logic; - writen_c : out std_logic; - hwrite_m_0_0 : in std_logic; - hwrite : in std_logic; - brmw_1 : out std_logic; - N_6550 : out std_logic; - oen_c : out std_logic; - rdata61_2 : in std_logic; - un1_apbi_0 : in std_logic; - brmw_i : out std_logic; - N_6377 : out std_logic; - rmw : out std_logic; - rstn : in std_logic; - read_c : out std_logic; - hready : out std_logic; - N_232_0 : in std_logic; - N_6455_0 : out std_logic - ); - -end mctrl; - -architecture DEF_ARCH of mctrl is - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OAI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1E0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1E0P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component OR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XAI1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AX1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1C - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR3B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component XA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component MX2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component XO1A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NAND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AOI1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AO1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component AND2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component AO1D - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal writedata_0_sqmuxa_0, \bstate[7]\, \bdrive[0]\, - N_36_0, ws, address_1_sqmuxa_i_a2_1, srhsel_0_sqmuxa, - \bdrive[1]\, \bdrive[2]\, \bdrive[3]\, N_185, N_111, - N_187, \address_RNI96NJ_5[0]\, \iowidth[0]\, \iowidth[1]\, - \iows[1]\, ws_0_sqmuxa, \bstate[5]\, \un1_wsnew_0_sqmuxa\, - \wsnew_0_sqmuxa\, \iows[0]\, \writedata_12_iv_0_0[25]\, - \ws_0_0_0[3]\, \ws_0_0_a2_0[3]\, N_6449, \ws_0_0_1[2]\, - \ws_0_0_a2_2_0[2]\, N_6457, N_6444, N_6458, N90_i, - ADD_4x4_fast_I13_Y_0_0, bstate_3, ready_0_0_o2_0, N_419, - ramoen_0_sqmuxa, ready_0_0_a2_0_1, ws_1_sqmuxa, - ready_0_0_a2_0_0, brmw, N_413, \iosn_1_iv_0_a2_0[1]\, - \iosn[1]\, \un1_romsn_0_sqmuxa_1_0[0]_net_1\, bstate16, - bstate_0_sqmuxa_1, bstate_0_sqmuxa_0, \hready\, - ramoen10_i_a2_1, hburst_i_0, \area[1]\, brmw_1_1, - \writedata_12_iv_i_2[24]\, N_440, \writedata[8]\, - \writedata_12_iv_i_1[24]\, N_190, \writedata_RNO_3[24]\, - N_193, \writedata_12_0_iv_0[23]\, \writedata[23]\, - N_123_i, \data_m[23]\, \writedata_12_0_iv_0_0[16]\, - N_5160, N_532, \writedata_12_iv_1[31]\, \writedata[15]\, - \writedata_12_iv_0[31]\, \writedata[31]\, - \writedata_m_0[23]\, \writedata_12_0_iv_0[20]\, - \writedata_m[4]\, \writedata_12_iv_0[28]\, \writedata[4]\, - N_46_i_0, \writedata_m[28]\, \writedata_12_iv_0[30]\, - \writedata[6]\, \writedata_m[30]\, - \writedata_12_iv_0_1[27]\, \writedata_12_iv_0_0[27]\, - N_182, \writedata_12_iv_0[26]\, \writedata_m[10]\, - wrn_5_sqmuxa_s6_0_1, N_394, wrn35, wrn_5_sqmuxa_s6_0_0, - N_126_i, N_6547, wrn_4_sqmuxa_s5_0_1, wrn_4_sqmuxa_s5_0_0, - N_117, wrn_3_sqmuxa_s4_0_1, wrn_3_sqmuxa_s4_0_0, wrn8, - wrn_2_sqmuxa_s3_0_1, wrn_2_sqmuxa_s3_0_0, N_425, - \writedata_12_iv_0_2[25]\, N_186, N_188, - \writedata_0_iv_1[20]\, \hrdata_m[20]\, \hrdata_m_0[20]\, - \writedata_12_0_iv_i_i_0[22]\, N_632, - \writedata_1_iv_0[0]\, \hrdata_m[0]\, - \writedata_1_iv_0[7]\, N_5112, - \writedata_12_0_iv_i_1[18]\, N_16464_tz, N_106, - \writedata_12_0_iv_i_0[18]\, \writedata_RNO_3[18]\, N_160, - \writedata_12_iv_0_0_1[29]\, writedata_1_sqmuxa, N_555, - \writedata_12_iv_0_0_0[29]\, - \writedata_12_iv_0_0_a2_0[29]\, N_552, - wrn_2_sqmuxa_s3_0_6_1, \busw[1]\, N_424, - \writedata_m_1[19]\, N_439, \writedata_m_0[19]\, - \writedata_0_iv_i_a2_0[19]\, \writedata_1_iv_i_0[2]\, - \writedata_1_iv_i_a2_2_0[2]\, N_150, - \writedata_12_0_iv_0_0[17]\, N_514, \writedata_4_m_0[20]\, - \brmw_i\, \writedata_m_0_0[18]\, - \writedata_12_0_iv_i_a3_i_0[21]\, N_539, - \writedata_1_iv_0[28]\, N_6555_i_0, N_38_i, - \writedata_1_iv_0[30]\, \writedata_1_iv_0[26]\, - \writedata_1_iv_0[31]\, \ws_3_iv_3[1]\, \ws_3_iv_1[1]\, - \ramrws_m[1]\, \iows_m[1]\, \ramwws_m[1]\, \romwws_m[1]\, - \romrws_m[1]\, \ws[3]\, \A_i[0]\, \ws_3_iv_3[0]\, - \ws_3_iv_1[0]\, \ramrws_m[0]\, \iows_m[0]\, \ramwws_m[0]\, - \romwws_m[0]\, \romrws_m[0]\, bexcen_0_sqmuxa_0_a2_0, - ADD_4x4_fast_I12_Y_0_0, \ws[2]\, ADD_4x4_fast_I11_Y_0_0, - \ws[1]\, \writedata_12_0_iv_i_a3_i_2_0_tz_0[21]\, N_6563, - wrn_6_sqmuxa_0_i_1, \size[0]\, \size[1]\, - \writedata_1_iv_0_a2_1_0[3]\, N_108, N_122_i_i_o2_1, - \busw[0]\, N_122_i_i_o2_0, \address_c[1]\, - \writedata_12_0_iv_i_a2_4_0[18]\, bstate_2_sqmuxa_1_0, - srhsel, \read_c\, ws_1, ws_0, \ws[0]\, N_155, - \writedata_12[30]\, \writedata_m[14]\, - \writedata_m_0[22]\, \writedata_12[28]\, - \writedata_m[12]\, \writedata_m_0[20]\, \romwidth_m[1]\, - \ws_RNO[2]\, N_6445, N_6443, bexcen_0_sqmuxa, - \writedata_m_0[18]\, N_448, \writedata_12[31]\, - \writedata[7]\, \writedata_12[26]\, \writedata_m[26]\, - \writedata_4_m[20]\, \writedata_4[20]\, \writedata[20]\, - \wrn_RNO[0]\, \wrn_90[0]\, \wrn_RNO[1]\, \wrn_90[1]\, - \wrn_RNO[2]\, \wrn_90[2]\, \wrn_RNO[3]\, \wrn_90[3]\, - wrn_1_sqmuxa_s2_0_3, un1_wrn35_1, wrn_5_sqmuxa_s6_0_6, - writen_0_sqmuxa_1_0, N_45, N_149, N_148, N_671, N_649, - N_6554, \writedata_12_0_iv_i_a3_i_2_0[21]\, N_543, - \writedata_12[16]\, N_530, N_531, N_6549, N_438, N_661, - N_6568_i_0, N_6565, N_6567_i_0, N_634, \writedata[12]\, - \hrdata_m[12]\, N_152, \writedata_12[23]\, - \writedata_10[7]\, \busw_1[1]\, \iowidth_m[1]\, - \ramwidth_m[1]\, \writedata[14]\, \hrdata_m[14]\, N_6450, - \ws_RNO[3]\, N_6448, N_538, bstate_0_sqmuxa, N_195, - bstate_2_sqmuxa, N_412, \hburst[1]\, \hburst[0]\, - \hburst[2]\, ramoen_0_sqmuxa_1, un1_iosn, bstate_4, - oen_1_sqmuxa, N_451, N_431, \oen_c\, N_297, N_619, N_618, - N_446, N_295, N_616, N_617, \iosn_i_m[1]\, - iosn_1_sqmuxa_1, bstate_5_1, \ws_1_sqmuxa_2[1]\, N_4, - N_16, \writedata_m[19]\, N_82_i_0, \writedata[0]\, - \writedata_12[25]\, \writedata[1]\, \writedata_12[27]\, - N_183, N_184, N_308, N_630, N_515, \writedata_12[29]\, - N_554, \writedata_12[17]\, N_511, N_513, - \writedata_12[20]\, \hrdata_m[15]\, \writedata_12[19]\, - \data_m[19]\, \writedata_m[3]\, \N_6550\, - \writedata_10[0]\, N_62_i_0, N_163, \busw_1[0]\, - \iowidth_m[0]\, \romwidth_m[0]\, \ramwidth_m[0]\, - hresp2_i_0, \area[0]\, romwrite, \ramsn_1[3]\, - \adec_2[0]\, \adec_2[1]\, \ramsn_1[2]\, \ramsn_1[1]\, - \ramsn_1[0]\, N_420, read_8_iv_0_tz, N_669, - un1_rws_0_sqmuxa, un18_srhsel, hwrite_0, iosn_0_sqmuxa_1, - \writedata[11]\, \address_RNI96NJ_3[0]\, N_5425, - iosn_0_sqmuxa, N_280, N_5525, N_5526, N_5527, N_5528, - N_5503, \romwws[2]\, N_5505, \romrws[0]\, N_5506, N_5507, - \romrws[2]\, N_5509, N_5510, N_5511, \hwdata_m[28]\, - \hwdata_m[30]\, N_6564, \rambanksz[2]\, N_5082, N_5084, - N_5107, N_5088, N_5106, N_5091, N_5097, N_5098, N_5094, - N_5100, N_5101, N_5103, \rambanksz[3]\, \rambanksz[1]\, - N_5108, N_5109, N_5110, \rambanksz[0]\, \ramwidth[1]\, - rmw_1_sqmuxa, rws_1_sqmuxa, N_5085, N_5086, N_5176, - ramoen_1_sqmuxa_1, N_5177, N_5179, \ramoen_1[0]\, - ramoen_2_sqmuxa, \ramoen_1[1]\, \ramoen_1[3]\, - \romrws_RNO[2]\, \romwws_RNO[2]\, \hrdata[7]\, - \hrdata[2]\, N_199, \writedata[9]\, N_517, \address_c[0]\, - \hwdata_m[26]\, \writedata[10]\, N_6385, N_112, - \romwidth_1[1]\, writen_RNO, \hrdata[20]\, N_435, N_5194, - N_5195, N_5196, N_5197, N_5200, N_5201, N_5202, N_5203, - \rmw\, \area[2]\, N_633, N_558, N_559, N_564, N_565, - N_566, N_396, N_449, N_635, N_636, N_6539, bexcen_RNO, - brdyen_RNO, ioen_RNO, romwrite_RNO, \N_6377\, N_610, - N_286, N_288, N_290, N_292, \brdyen\, rws_0_sqmuxa, - \iows[2]\, N_560, \romwws_RNO[3]\, N_5504, - \romrws_RNO[3]\, N_5508, \romrws[3]\, \romwws[3]\, - romsn_1_sqmuxa, N_442, \bstate[4]\, \bstate[6]\, - \hresp_6[0]\, N_500, \bstate_RNO[6]\, N_36, ready10, - \ioen\, N_653, writedata_0_sqmuxa, read_RNO_0, - \romwws_RNO[1]\, N_5502, un1_ahbsi_1, \ramsn_1_0[3]\, - bstate16_1, ramoen_2_sqmuxa_1, \ramsn_1_0[1]\, N_5178, - \ramoen_1[2]\, \iosn_1_iv[1]\, \ramsn_1_0[2]\, - \ramsn_1_0[0]\, iosn_1_sqmuxa, bstate_2_sqmuxa_1, - iosn_1_sqmuxa_1_0, \bstate_RNO[7]\, N_5512, \iows[3]\, - N_5518, N_14, N_563, N_567, \ramrws_RNO[0]\, N_5519, - N_562, N_5517, N_561, N_5520, \ws_RNO[1]\, - \ws_1_sqmuxa_2_m[2]\, \romwws[1]\, \ramwws[1]\, - \romrws[1]\, \romwws_RNO[0]\, N_5501, \ws_RNO[0]\, - \ws_1_sqmuxa_2_m[3]\, \ramrws[0]\, \ramrws[1]\, - \ramwws[0]\, \romwws[0]\, \writedata[3]\, \hrdata[0]\, - N_6410, N_6411, \writedata[13]\, romsn_0_sqmuxa_1, N_506, - N_507, N_549, N_550, \writedata[5]\, \romsn_1[0]\, - \romsn_1[1]\, N_80, srhsel_RNO_0, ready_RNO, \brmw_1\, - \writen_c\, \bexcen\, \rwen_c[0]\, \rwen_c[1]\, - \rwen_c[2]\, \rwen_c[3]\, \ramwidth[0]\, \ramsn_c[0]\, - \ramsn_c[1]\, \ramsn_c[2]\, \ramsn_c[3]\, \data[16]\, - \data[17]\, \data[18]\, \data[19]\, \data[20]\, - \data[21]\, \data[22]\, \data[23]\, \romwidth[0]\, - \romwidth[1]\, \hrdata[1]\, \hrdata[3]\, \hrdata[4]\, - \hrdata[5]\, \hrdata[6]\, \hrdata[8]\, \hrdata[9]\, - \hrdata[10]\, \hrdata[11]\, \hrdata[12]\, \hrdata[13]\, - \hrdata[14]\, \hrdata[15]\, \hrdata[16]\, \hrdata[17]\, - \hrdata[18]\, \hrdata[19]\, \hrdata[21]\, \hrdata[22]\, - \hrdata[23]\, \hrdata[24]\, \hrdata[25]\, \hrdata[26]\, - \hrdata[27]\, \hrdata[28]\, \hrdata[29]\, \hrdata[30]\, - \hrdata[31]\, \GND\, \VCC\, GND_0, VCC_0 : std_logic; - -begin - - ramrws_1 <= \ramrws[1]\; - ramwws(1) <= \ramwws[1]\; - ramwws(0) <= \ramwws[0]\; - rwen_c(3) <= \rwen_c[3]\; - rwen_c(2) <= \rwen_c[2]\; - rwen_c(1) <= \rwen_c[1]\; - rwen_c(0) <= \rwen_c[0]\; - ramsn_c(3) <= \ramsn_c[3]\; - ramsn_c(2) <= \ramsn_c[2]\; - ramsn_c(1) <= \ramsn_c[1]\; - ramsn_c(0) <= \ramsn_c[0]\; - rambanksz_0 <= \rambanksz[0]\; - rambanksz_1 <= \rambanksz[1]\; - rambanksz_3 <= \rambanksz[3]\; - iows_3 <= \iows[3]\; - iows_2 <= \iows[2]\; - romrws_1 <= \romrws[1]\; - romrws_3 <= \romrws[3]\; - romrws_2 <= \romrws[2]\; - romwidth(1) <= \romwidth[1]\; - romwidth(0) <= \romwidth[0]\; - address_c(1) <= \address_c[1]\; - address_c(0) <= \address_c[0]\; - data(23) <= \data[23]\; - data(22) <= \data[22]\; - data(21) <= \data[21]\; - data(20) <= \data[20]\; - data(19) <= \data[19]\; - data(18) <= \data[18]\; - data(17) <= \data[17]\; - data(16) <= \data[16]\; - ramwidth(1) <= \ramwidth[1]\; - ramwidth(0) <= \ramwidth[0]\; - romwws(3) <= \romwws[3]\; - romwws(2) <= \romwws[2]\; - romwws(1) <= \romwws[1]\; - romwws(0) <= \romwws[0]\; - hrdata(31) <= \hrdata[31]\; - hrdata(30) <= \hrdata[30]\; - hrdata(29) <= \hrdata[29]\; - hrdata(28) <= \hrdata[28]\; - hrdata(27) <= \hrdata[27]\; - hrdata(26) <= \hrdata[26]\; - hrdata(25) <= \hrdata[25]\; - hrdata(24) <= \hrdata[24]\; - hrdata(23) <= \hrdata[23]\; - hrdata(22) <= \hrdata[22]\; - hrdata(21) <= \hrdata[21]\; - hrdata(20) <= \hrdata[20]\; - hrdata(19) <= \hrdata[19]\; - hrdata(18) <= \hrdata[18]\; - hrdata(17) <= \hrdata[17]\; - hrdata(16) <= \hrdata[16]\; - hrdata(15) <= \hrdata[15]\; - hrdata(14) <= \hrdata[14]\; - hrdata(13) <= \hrdata[13]\; - hrdata(12) <= \hrdata[12]\; - hrdata(11) <= \hrdata[11]\; - hrdata(10) <= \hrdata[10]\; - hrdata(9) <= \hrdata[9]\; - hrdata(8) <= \hrdata[8]\; - hrdata(7) <= \hrdata[7]\; - hrdata(6) <= \hrdata[6]\; - hrdata(5) <= \hrdata[5]\; - hrdata(4) <= \hrdata[4]\; - hrdata(3) <= \hrdata[3]\; - hrdata(2) <= \hrdata[2]\; - hrdata(1) <= \hrdata[1]\; - hrdata(0) <= \hrdata[0]\; - bexcen <= \bexcen\; - brdyen <= \brdyen\; - ioen <= \ioen\; - writen_c <= \writen_c\; - brmw_1 <= \brmw_1\; - N_6550 <= \N_6550\; - oen_c <= \oen_c\; - brmw_i <= \brmw_i\; - N_6377 <= \N_6377\; - rmw <= \rmw\; - read_c <= \read_c\; - hready <= \hready\; - - \v.mcfg1.bexcen_0_sqmuxa_0_a2_0\ : NOR2 - port map(A => un1_apbi_0, B => rdata61_2, Y => - bexcen_0_sqmuxa_0_a2_0); - - \r.ws_RNO[2]\ : OR3C - port map(A => N_6445, B => N_6443, C => \ws_0_0_1[2]\, Y - => \ws_RNO[2]\); - - \r.writedata_RNO_3[26]\ : OAI1 - port map(A => N_6555_i_0, B => N_38_i, C => \hrdata[26]\, Y - => \writedata_1_iv_0[26]\); - - \r.address[23]\ : DFN1E1 - port map(D => haddr(23), CLK => lclk_c, E => N_36_0, Q => - address_c(23)); - - \r.mcfg1.romwidth[1]\ : DFN1E0 - port map(D => \romwidth_1[1]\, CLK => lclk_c, E => N_560, Q - => \romwidth[1]\); - - \r.mcfg1.romrws_RNO[1]\ : OR2A - port map(A => rstn, B => N_5506, Y => N_559); - - \r.data[26]\ : DFN1 - port map(D => data_in(26), CLK => lclk_c, Q => \hrdata[26]\); - - \r.writedata_RNO_4[2]\ : NOR2 - port map(A => \hrdata[2]\, B => N_5112, Y => N_150); - - \r.wrn_RNO_4[0]\ : OR2 - port map(A => N_425, B => N_6547, Y => wrn_2_sqmuxa_s3_0_0); - - \r.ramoen_RNO[0]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => ramoen_2_sqmuxa, C => - N_5176, Y => \ramoen_1[0]\); - - \r.writedata_RNO_2[25]\ : OR2A - port map(A => hwdata_9, B => N_440, Y => N_186); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I8_Y_0\ : NOR3 - port map(A => N_4, B => N_16, C => N_14, Y => N90_i); - - \r.wrn_RNO_0[0]\ : MX2C - port map(A => N_5194, B => N_5200, S => writen_0_sqmuxa_1_0, - Y => \wrn_90[0]\); - - \r.writedata_RNO_4[26]\ : OR2B - port map(A => hwdata_26, B => \address_RNI96NJ_5[0]\, Y => - \hwdata_m[26]\); - - \apbo.prdata_10_0_a2_0\ : OR2A - port map(A => paddr(2), B => paddr(3), Y => N_6455); - - \r.mcfg1.iows_RNO[0]\ : NOR2B - port map(A => rstn, B => N_5509, Y => N_564); - - \r.mcfg1.romwws[1]\ : DFN1 - port map(D => \romwws_RNO[1]\, CLK => lclk_c, Q => - \romwws[1]\); - - \r.busw_RNO_0[0]\ : OR2B - port map(A => \iowidth[0]\, B => iosn_1_8, Y => - \iowidth_m[0]\); - - \r.wrn_RNO[3]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => \wrn_90[3]\, C => rstn, - Y => \wrn_RNO[3]\); - - \r.ramoen_RNO_0[2]\ : MX2C - port map(A => \ramsn_1[2]\, B => \ramsn_c[2]\, S => - un1_iosn, Y => N_5178); - - \r.brmw_RNIPQ7A1\ : OR2 - port map(A => \brmw_i\, B => N_439, Y => N_448); - - \r.ws_RNO_0[0]\ : NOR3C - port map(A => \ws_3_iv_1[0]\, B => \ramrws_m[0]\, C => - \iows_m[0]\, Y => \ws_3_iv_3[0]\); - - \r.writedata[31]\ : DFN1E1 - port map(D => \writedata_12[31]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(31)); - - \r.romsn[0]\ : DFN1E0P0 - port map(D => \romsn_1[0]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => romsn_c(0)); - - \r.ws_RNO_5[0]\ : OR3A - port map(A => \romwws[0]\, B => N_6458, C => rws_1_sqmuxa, - Y => \romwws_m[0]\); - - \v.ramoen_0_sqmuxa\ : OR2B - port map(A => iosn_1_0, B => bstate16, Y => ramoen_0_sqmuxa); - - \r.ramsn[2]\ : DFN1E0P0 - port map(D => \ramsn_1_0[2]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => \ramsn_c[2]\); - - \r.data[1]\ : DFN1 - port map(D => data_in(1), CLK => lclk_c, Q => \hrdata[1]\); - - \un1_v.ws_1_sqmuxa_2_m[3]\ : XAI1A - port map(A => \ws[0]\, B => \A_i[0]\, C => bstate_3, Y => - \ws_1_sqmuxa_2_m[3]\); - - \r.writedata_RNO_0[24]\ : OA1 - port map(A => N_440, B => \writedata[8]\, C => - \writedata_12_iv_i_1[24]\, Y => \writedata_12_iv_i_2[24]\); - - \r.bstate_RNI8E2SK1[6]\ : NOR3A - port map(A => ramoen_0_sqmuxa, B => N_419, C => N_438, Y - => N_6567_i_0); - - \r.size[0]\ : DFN1E1 - port map(D => hsize(0), CLK => lclk_c, E => un1_ahbsi_1, Q - => \size[0]\); - - \r.mcfg2.rambanksz_RNI4PTI71[3]\ : MX2 - port map(A => haddr(17), B => haddr(25), S => - \rambanksz[3]\, Y => N_5107); - - \r.writedata_RNO_1[16]\ : AO1B - port map(A => N_669, B => N_420, C => hwdata_16, Y => N_530); - - \r.mcfg1.romwws_RNO_0[3]\ : MX2 - port map(A => \romwws[3]\, B => pwdata_0_7, S => - bexcen_0_sqmuxa, Y => N_5504); - - \r.wrn_RNO_0[2]\ : MX2C - port map(A => N_5196, B => N_5202, S => writen_0_sqmuxa_1_0, - Y => \wrn_90[2]\); - - \r.bdrive_RNITBR7[1]\ : INV - port map(A => \bdrive[1]\, Y => bdrive_i(1)); - - \r.area_RNI4DTB1[0]\ : OA1C - port map(A => N_412, B => N_653, C => N_424, Y => N_6565); - - \r.mcfg1.brdyen_RNII5OD\ : NOR2B - port map(A => \brdyen\, B => \area[1]\, Y => N_413); - - \r.busw_RNO_1[0]\ : OR3A - port map(A => \romwidth[0]\, B => hsel_i(0), C => - un6_ioen_NE_0, Y => \romwidth_m[0]\); - - \r.area_RNI2L73O[1]\ : NOR3B - port map(A => hburst_i_0, B => htrans(0), C => \area[1]\, Y - => ramoen10_i_a2_1); - - \r.mcfg1.romrws_RNO[3]\ : OR2A - port map(A => rstn, B => N_5508, Y => \romrws_RNO[3]\); - - \r.area_RNISN3H[0]\ : OA1C - port map(A => \area[0]\, B => romwrite, C => \read_c\, Y - => hresp2_i_0); - - \r.bdrive_RNO[0]\ : OA1C - port map(A => N_6568_i_0, B => \bdrive[0]\, C => N_6567_i_0, - Y => N_286); - - \r.srhsel_RNI5PCD\ : OR2B - port map(A => srhsel, B => \bstate[7]\, Y => N_424); - - \r.mcfg1.romrws_RNO[0]\ : OR2A - port map(A => rstn, B => N_5505, Y => N_558); - - \r.writedata_RNO_2[24]\ : OR2A - port map(A => N_111, B => hwdata_24, Y => N_190); - - \r.writen_RNO\ : OR2A - port map(A => rstn, B => N_5425, Y => writen_RNO); - - \r.wrn_RNO_0[3]\ : MX2C - port map(A => N_5197, B => N_5203, S => writen_0_sqmuxa_1_0, - Y => \wrn_90[3]\); - - \r.srhsel_RNIR3LD1\ : AOI1B - port map(A => bstate_2_sqmuxa, B => srhsel, C => - \bstate[7]\, Y => bstate_2_sqmuxa_1); - - \r.mcfg2.rambanksz_RNIMHVL71[3]\ : MX2 - port map(A => haddr(13), B => haddr(21), S => - \rambanksz[3]\, Y => N_5082); - - \r.writedata_RNO_3[27]\ : AOI1B - port map(A => hwdata_27, B => N_111, C => N_182, Y => - \writedata_12_iv_0_0[27]\); - - \r.mcfg1.iows_RNO[2]\ : NOR2B - port map(A => rstn, B => N_5511, Y => N_566); - - \r.writedata_RNO[31]\ : AO1B - port map(A => \writedata[7]\, B => N_46_i_0, C => - \writedata_12_iv_1[31]\, Y => \writedata_12[31]\); - - \r.ws_RNO_1[2]\ : OR3C - port map(A => \ws_1_sqmuxa_2[1]\, B => bstate_3, C => rstn, - Y => N_6443); - - \r.size[1]\ : DFN1E1 - port map(D => hsize(1), CLK => lclk_c, E => un1_ahbsi_1, Q - => \size[1]\); - - \r.writedata_RNO_4[27]\ : OR2A - port map(A => \hrdata[27]\, B => \address_RNI96NJ_5[0]\, Y - => N_182); - - \r.address_RNITD6J[0]\ : OR2A - port map(A => N_394, B => \address_c[0]\, Y => N_108); - - \r.data[23]\ : DFN1 - port map(D => data_in(23), CLK => lclk_c, Q => \hrdata[23]\); - - \r.mcfg2.ramwidth_RNIM82O32[1]\ : NOR3B - port map(A => hwrite, B => brmw_1_1, C => hsize(1), Y => - \brmw_1\); - - \r.wrn_RNO_0[1]\ : MX2C - port map(A => N_5195, B => N_5201, S => writen_0_sqmuxa_1_0, - Y => \wrn_90[1]\); - - \r.mcfg1.bexcen_RNO\ : NOR2B - port map(A => rstn, B => N_5528, Y => bexcen_RNO); - - \r.mcfg2.ramwidth[1]\ : DFN1E1 - port map(D => pwdata_0_d0, CLK => lclk_c, E => rmw_1_sqmuxa, - Q => \ramwidth[1]\); - - \r.brmw_RNIF8931\ : NOR2A - port map(A => brmw, B => N_439, Y => N_449); - - \r.writedata[8]\ : DFN1E1 - port map(D => \writedata[8]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(8)); - - \r.writedata[0]\ : DFN1E1 - port map(D => \writedata[0]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(0)); - - \r.bdrive_RNO[3]\ : OA1C - port map(A => N_6568_i_0, B => \bdrive[3]\, C => N_6567_i_0, - Y => N_292); - - \r.writedata_RNO_1[17]\ : OR2A - port map(A => \hrdata[17]\, B => N_448, Y => N_513); - - \un1_romsn_0_sqmuxa_1_0[0]\ : OR2A - port map(A => iosn_0(93), B => bstate16, Y => - \un1_romsn_0_sqmuxa_1_0[0]_net_1\); - - \r.data_RNIFM1E3[14]\ : OR3 - port map(A => hwdata_m_7, B => \hrdata_m[14]\, C => - hwdata_m_0_2, Y => \writedata[14]\); - - \r.data[28]\ : DFN1 - port map(D => data_in(28), CLK => lclk_c, Q => \hrdata[28]\); - - \r.writedata[26]\ : DFN1E1 - port map(D => \writedata_12[26]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(26)); - - \r.mcfg2.ramrws_RNO_0[0]\ : MX2 - port map(A => \ramrws[0]\, B => pwdata_0_0, S => - rmw_1_sqmuxa, Y => N_5519); - - \r.data[8]\ : DFN1 - port map(D => data_in(8), CLK => lclk_c, Q => \hrdata[8]\); - - \r.writedata_RNO_0[22]\ : AO1A - port map(A => N_440, B => hwdata_6, C => N_632, Y => - \writedata_12_0_iv_i_i_0[22]\); - - \r.mcfg1.iows_RNO_0[3]\ : MX2 - port map(A => \iows[3]\, B => pwdata_18, S => - bexcen_0_sqmuxa, Y => N_5512); - - \r.writedata[23]\ : DFN1E1 - port map(D => \writedata_12[23]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[23]\); - - \r.wrn_RNO_4[3]\ : OR2 - port map(A => N_126_i, B => N_6547, Y => - wrn_5_sqmuxa_s6_0_0); - - \r.address[14]\ : DFN1E1 - port map(D => haddr(14), CLK => lclk_c, E => N_36_0, Q => - address_c(14)); - - \r.mcfg2.ramrws_RNO[0]\ : NOR2B - port map(A => rstn, B => N_5519, Y => \ramrws_RNO[0]\); - - \r.writedata_RNO_3[29]\ : OR2B - port map(A => N_46_i_0, B => hwdata_5, Y => N_555); - - \r.writedata[7]\ : DFN1E1 - port map(D => \writedata[7]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(7)); - - \r.hwrite\ : DFN1E1 - port map(D => hwrite, CLK => lclk_c, E => un1_ahbsi_1, Q - => hwrite_0); - - \r.ws_RNIVJ8E[3]\ : NOR2 - port map(A => \ws[3]\, B => \ws[0]\, Y => ws_0); - - \r.data_RNIR5AH1[4]\ : OR2B - port map(A => \hrdata[4]\, B => N_671, Y => N_550); - - \r.bdrive_RNISBR7[0]\ : INV - port map(A => \bdrive[0]\, Y => bdrive_i(0)); - - \r.writedata_RNO[25]\ : AO1B - port map(A => \writedata[1]\, B => N_46_i_0, C => - \writedata_12_iv_0_2[25]\, Y => \writedata_12[25]\); - - \r.busw_RNO[0]\ : OR3C - port map(A => \iowidth_m[0]\, B => \romwidth_m[0]\, C => - \ramwidth_m[0]\, Y => \busw_1[0]\); - - \r.address_RNI96NJ_0[0]\ : NOR2A - port map(A => wrn8, B => \brmw_i\, Y => N_510); - - \r.writedata[1]\ : DFN1E1 - port map(D => \writedata[1]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(1)); - - \r.mcfg2.rambanksz_RNI67EN71[3]\ : MX2 - port map(A => haddr(19), B => haddr(27), S => - \rambanksz[3]\, Y => N_5086); - - \r.data_RNIS2VV2[20]\ : NOR3C - port map(A => \hrdata_m[20]\, B => \hrdata_m_0[20]\, C => - hwdata_m_13, Y => \writedata_0_iv_1[20]\); - - \r.writedata_RNO_4[29]\ : NOR2B - port map(A => \address_RNI96NJ_5[0]\, B => N_123_i, Y => - \writedata_12_iv_0_0_a2_0[29]\); - - \r.writedata_RNO_2[18]\ : AO1A - port map(A => N_16464_tz, B => N_106, C => hwdata_18, Y => - \writedata_12_0_iv_i_1[18]\); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I12_Y_0\ : AX1B - port map(A => N_4, B => N_16, C => ADD_4x4_fast_I12_Y_0_0, - Y => \ws_1_sqmuxa_2[1]\); - - \r.data_RNIS6OK[14]\ : NOR2A - port map(A => \hrdata[14]\, B => \address_RNI96NJ_3[0]\, Y - => \hrdata_m[14]\); - - \r.address[9]\ : DFN1E1 - port map(D => haddr(9), CLK => lclk_c, E => N_36, Q => - address_c(9)); - - \r.mcfg1.romwws[3]\ : DFN1 - port map(D => \romwws_RNO[3]\, CLK => lclk_c, Q => - \romwws[3]\); - - \r.iosn_RNI6PIF1[1]\ : OR2 - port map(A => \iosn[1]\, B => iosn_0(93), Y => - \iosn_1_iv_0_a2_0[1]\); - - \r.writedata_RNO_2[22]\ : NOR2A - port map(A => \data[22]\, B => N_5160, Y => N_632); - - \r.bstate_RNI9O4Q1[4]\ : OA1C - port map(A => \bstate[4]\, B => ready10, C => \bstate[7]\, - Y => bstate_5_1); - - \r.mcfg2.rambanksz_RNIU17O4L_0[0]\ : OR3A - port map(A => \adec_2[0]\, B => \adec_2[1]\, C => iosn_99, - Y => \ramsn_1[3]\); - - \r.address[13]\ : DFN1E1 - port map(D => haddr(13), CLK => lclk_c, E => N_36_0, Q => - address_c(13)); - - \r.data[4]\ : DFN1 - port map(D => data_in(4), CLK => lclk_c, Q => \hrdata[4]\); - - \r.writedata_RNO_1[19]\ : OR2A - port map(A => \data[19]\, B => N_5160, Y => \data_m[19]\); - - \r.writedata_RNO_3[21]\ : OA1A - port map(A => \busw[1]\, B => wrn8, C => N_6563, Y => - \writedata_12_0_iv_i_a3_i_2_0_tz_0[21]\); - - \r.bstate_RNIHU8AA2[5]\ : OR2B - port map(A => bstate_0_sqmuxa, B => \bstate[5]\, Y => - iosn_0_sqmuxa_1); - - \r.data[15]\ : DFN1 - port map(D => data_in(15), CLK => lclk_c, Q => \hrdata[15]\); - - \r.ws_RNO_4[3]\ : OR3C - port map(A => \un1_wsnew_0_sqmuxa\, B => \romrws[3]\, C => - N_6457, Y => N_6449); - - \r.bstate_RNIHU8AA2_0[5]\ : OR2A - port map(A => \bstate[5]\, B => bstate_0_sqmuxa, Y => - iosn_1_sqmuxa_1); - - \apbo.prdata[27]\ : NOR2A - port map(A => \iowidth[0]\, B => N_232_0, Y => prdata_7); - - \r.romsn[1]\ : DFN1E0P0 - port map(D => \romsn_1[1]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => romsn_c(1)); - - \r.bstate_RNO_0[5]\ : NOR2 - port map(A => iosn_1_sqmuxa, B => N_451, Y => N_616); - - \r.writedata_RNO[18]\ : NOR3C - port map(A => \writedata_12_0_iv_i_0[18]\, B => N_163, C - => \writedata_12_0_iv_i_1[18]\, Y => N_62_i_0); - - \r.mcfg1.romwidth_RNO[0]\ : NOR2B - port map(A => rstn, B => pwdata_0_8, Y => N_6539); - - \r.data[2]\ : DFN1 - port map(D => data_in(2), CLK => lclk_c, Q => \hrdata[2]\); - - \r.wrn_RNO_1[2]\ : OA1B - port map(A => wrn_5_sqmuxa_s6_0_6, B => wrn_4_sqmuxa_s5_0_1, - C => wrn_1_sqmuxa_s2_0_3, Y => N_5196); - - \r.writedata_RNO_2[2]\ : NOR3B - port map(A => N_108, B => \address_c[1]\, C => hwdata_2, Y - => N_148); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I11_Y_0_0\ : XOR2 - port map(A => \ws[1]\, B => \A_i[0]\, Y => - ADD_4x4_fast_I11_Y_0_0); - - \r.data_RNIACH52[10]\ : OR2B - port map(A => N_6385, B => N_112, Y => \writedata[10]\); - - \r.ws_RNO[3]\ : OR3C - port map(A => N_6448, B => N_6450, C => \ws_0_0_0[3]\, Y - => \ws_RNO[3]\); - - \r.writedata_RNO_4[21]\ : OR3A - port map(A => \hrdata[21]\, B => \brmw_i\, C => N_439, Y - => N_539); - - \r.writedata_RNO[11]\ : AO1B - port map(A => hwdata_11, B => \address_RNI96NJ_3[0]\, C => - N_155, Y => \writedata[11]\); - - \r.size_RNI3PDH2[0]\ : OR3A - port map(A => wrn_6_sqmuxa_0_i_1, B => wrn35, C => N_438, Y - => N_6549); - - \r.area_RNIHHBD_0[2]\ : OR2 - port map(A => \area[2]\, B => \area[1]\, Y => rws_1_sqmuxa); - - \r.data_RNIOEQN3[7]\ : AO1C - port map(A => \N_6550\, B => \writedata_10[7]\, C => - \writedata_1_iv_0[7]\, Y => \writedata[7]\); - - \r.writedata_RNO_1[26]\ : AO1C - port map(A => hwdata_18, B => N_448, C => - \writedata_m_0_0[18]\, Y => \writedata_m_0[18]\); - - \r.ws_RNO_3[2]\ : NOR2A - port map(A => \romwws[2]\, B => N_6458, Y => - \ws_0_0_a2_2_0[2]\); - - \r.address[30]\ : DFN1E1 - port map(D => haddr(30), CLK => lclk_c, E => N_36, Q => - address(30)); - - \r.size_RNIA6IT[1]\ : NOR3A - port map(A => \busw[1]\, B => \size[1]\, C => wrn35, Y => - un1_wrn35_1); - - \r.data_RNIJFTL2[6]\ : MX2 - port map(A => hwdata_6, B => \hrdata[6]\, S => N_671, Y => - \writedata[6]\); - - \r.ramsn_RNO[1]\ : OR2 - port map(A => srhsel_0_sqmuxa, B => \ramsn_1[1]\, Y => - \ramsn_1_0[1]\); - - \r.ramoen_RNO_0[1]\ : MX2C - port map(A => \ramsn_c[1]\, B => \ramsn_1[1]\, S => - ramoen_1_sqmuxa_1, Y => N_5177); - - \r.data[3]\ : DFN1 - port map(D => data_in(3), CLK => lclk_c, Q => \hrdata[3]\); - - \r.data[22]\ : DFN1 - port map(D => data_in(22), CLK => lclk_c, Q => \hrdata[22]\); - - \r.data[20]\ : DFN1 - port map(D => data_in(20), CLK => lclk_c, Q => \hrdata[20]\); - - \r.oen_RNIJERI\ : NOR3C - port map(A => srhsel, B => \oen_c\, C => \read_c\, Y => - bstate_2_sqmuxa_1_0); - - \r.bstate_RNIR27I1[4]\ : OR2B - port map(A => \bstate[4]\, B => ready10, Y => N_610); - - \r.bstate_RNIM6SV2[4]\ : OA1C - port map(A => \bstate[4]\, B => ready10, C => - bstate_2_sqmuxa_1, Y => iosn_1_sqmuxa_1_0); - - \r.ramoen_RNO_0[3]\ : MX2C - port map(A => \ramsn_c[3]\, B => \ramsn_1[3]\, S => - ramoen_1_sqmuxa_1, Y => N_5179); - - \r.writedata_RNO[30]\ : OR3C - port map(A => \writedata_m[14]\, B => - \writedata_12_iv_0[30]\, C => \writedata_m_0[22]\, Y => - \writedata_12[30]\); - - \r.mcfg1.iows_RNO[3]\ : NOR2B - port map(A => rstn, B => N_5512, Y => N_567); - - \r.wrn_RNO[2]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => \wrn_90[2]\, C => rstn, - Y => \wrn_RNO[2]\); - - \r.data[7]\ : DFN1 - port map(D => data_in(7), CLK => lclk_c, Q => \hrdata[7]\); - - \r.mcfg1.romwws_RNO[1]\ : OR2A - port map(A => rstn, B => N_5502, Y => \romwws_RNO[1]\); - - \r.wrn_RNO_3[0]\ : OR3A - port map(A => N_394, B => wrn35, C => wrn_2_sqmuxa_s3_0_0, - Y => wrn_2_sqmuxa_s3_0_1); - - \r.mcfg2.rambanksz_RNILIUH71[3]\ : MX2 - port map(A => haddr(21), B => haddr(29), S => - \rambanksz[3]\, Y => N_5108); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I13_Y_0_0\ : XOR2 - port map(A => \ws[3]\, B => \A_i[0]\, Y => - ADD_4x4_fast_I13_Y_0_0); - - \r.ws_RNO_6[0]\ : OR3B - port map(A => \un1_wsnew_0_sqmuxa\, B => \romrws[0]\, C => - rws_1_sqmuxa, Y => \romrws_m[0]\); - - \r.bstate_RNI7RCR1[6]\ : OR2A - port map(A => N_500, B => \bstate[6]\, Y => \A_i[0]\); - - \r.busw[1]\ : DFN1E0 - port map(D => \busw_1[1]\, CLK => lclk_c, E => - srhsel_0_sqmuxa, Q => \busw[1]\); - - \r.busw_RNIIOLQ[0]\ : OR2B - port map(A => N_122_i_i_o2_1, B => N_122_i_i_o2_0, Y => - N_440); - - \r.writedata[25]\ : DFN1E1 - port map(D => \writedata_12[25]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(25)); - - \r.oen\ : DFN1E0P0 - port map(D => ramoen_2_sqmuxa_1, CLK => lclk_c, PRE => rstn, - E => ramoen_0_sqmuxa_1, Q => \oen_c\); - - \r.writedata[28]\ : DFN1E1 - port map(D => \writedata_12[28]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(28)); - - \r.mcfg2.rmw\ : DFN1E1 - port map(D => pwdata_1_d0, CLK => lclk_c, E => rmw_1_sqmuxa, - Q => \rmw\); - - \r.writedata_RNO_4[19]\ : OA1 - port map(A => N_439, B => \writedata_0_iv_i_a2_0[19]\, C - => N_123_i, Y => \writedata_m_0[19]\); - - \r.hwrite_RNI0B0398\ : AO1C - port map(A => bstate16, B => un18_srhsel, C => iosn_1_0, Y - => un1_iosn); - - \r.mcfg1.romwws[2]\ : DFN1 - port map(D => \romwws_RNO[2]\, CLK => lclk_c, Q => - \romwws[2]\); - - \r.writedata_RNO_0[9]\ : OR3B - port map(A => N_117, B => \hrdata[9]\, C => \brmw_i\, Y => - N_152); - - \r.mcfg1.bexcen\ : DFN1 - port map(D => bexcen_RNO, CLK => lclk_c, Q => \bexcen\); - - \r.data_RNI8IVK1[0]\ : MX2 - port map(A => hwdata_0, B => \hrdata[0]\, S => N_394, Y => - \writedata_10[0]\); - - \r.ws_RNO_6[1]\ : OR3B - port map(A => \un1_wsnew_0_sqmuxa\, B => \romrws[1]\, C => - rws_1_sqmuxa, Y => \romrws_m[1]\); - - \r.writedata_RNO_1[27]\ : OR2B - port map(A => writedata_1_sqmuxa, B => hwdata_19, Y => - N_183); - - \r.mcfg2.rambanksz_RNIU17O4L_1[0]\ : OR3 - port map(A => \adec_2[1]\, B => iosn_99, C => \adec_2[0]\, - Y => \ramsn_1[2]\); - - \r.hburst[1]\ : DFN1E1 - port map(D => hburst_0(1), CLK => lclk_c, E => un1_ahbsi_1, - Q => \hburst[1]\); - - \r.mcfg2.ramrws_RNI9JIA[0]\ : MX2 - port map(A => \romrws[0]\, B => \ramrws[0]\, S => paddr(2), - Y => N_5062); - - \r.mcfg1.ioen_RNO_0\ : MX2 - port map(A => \ioen\, B => pwdata_14, S => bexcen_0_sqmuxa, - Y => N_5526); - - \r.ws_RNO_3[3]\ : XA1 - port map(A => N90_i, B => ADD_4x4_fast_I13_Y_0_0, C => - bstate_3, Y => \ws_0_0_a2_0[3]\); - - \r.ws_RNO_2[2]\ : AOI1B - port map(A => \ws_0_0_a2_2_0[2]\, B => N_6457, C => N_6444, - Y => \ws_0_0_1[2]\); - - \r.data_RNIIJ5S1[7]\ : OA1A - port map(A => \hrdata[7]\, B => N_5112, C => hwdata_m_0_d0, - Y => \writedata_1_iv_0[7]\); - - \r.ws[1]\ : DFN1 - port map(D => \ws_RNO[1]\, CLK => lclk_c, Q => \ws[1]\); - - \r.data[31]\ : DFN1 - port map(D => data_in(31), CLK => lclk_c, Q => \hrdata[31]\); - - \r.address_RNI96NJ[0]\ : NOR2A - port map(A => \address_c[0]\, B => N_5112, Y => N_38_i); - - GND_i : GND - port map(Y => \GND\); - - \r.address[31]\ : DFN1E1 - port map(D => hsel_i(0), CLK => lclk_c, E => N_36, Q => - address(31)); - - \r.writedata_RNO[22]\ : OR3 - port map(A => \writedata_12_0_iv_i_i_0[22]\, B => N_630, C - => N_515, Y => N_308); - - \r.mcfg2.ramwws_RNO[0]\ : NOR2B - port map(A => rstn, B => N_5517, Y => N_562); - - \r.mcfg1.romwws_RNO[3]\ : OR2A - port map(A => rstn, B => N_5504, Y => \romwws_RNO[3]\); - - \r.hresp_RNO[0]\ : OR2 - port map(A => \bstate[6]\, B => N_6565, Y => \hresp_6[0]\); - - \r.writedata[14]\ : DFN1E1 - port map(D => \writedata[14]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(14)); - - \r.mcfg1.bexcen_RNO_0\ : MX2 - port map(A => \bexcen\, B => pwdata_20, S => - bexcen_0_sqmuxa, Y => N_5528); - - \r.busw_RNIRAK11[1]\ : OR2 - port map(A => \busw[1]\, B => N_396, Y => N_123_i); - - \r.ws_RNO_3[0]\ : OR2B - port map(A => un1_rws_0_sqmuxa, B => \iows[0]\, Y => - \iows_m[0]\); - - \r.brmw_RNICGSJ\ : NOR2 - port map(A => brmw, B => N_413, Y => ready_0_0_a2_0_0); - - \r.ws_RNO_5[1]\ : OR3A - port map(A => \romwws[1]\, B => N_6458, C => rws_1_sqmuxa, - Y => \romwws_m[1]\); - - \r.mcfg2.rambanksz_RNI27TO71[3]\ : MX2 - port map(A => haddr(20), B => haddr(28), S => - \rambanksz[3]\, Y => N_5101); - - \r.brmw_RNILLO71\ : MX2A - port map(A => N_396, B => brmw, S => \busw[1]\, Y => N_420); - - \r.mcfg2.ramwidth[0]\ : DFN1E1 - port map(D => pwdata_1_3, CLK => lclk_c, E => rmw_1_sqmuxa, - Q => \ramwidth[0]\); - - \r.mcfg1.romwws_RNO_0[0]\ : MX2 - port map(A => \romwws[0]\, B => pwdata_1_3, S => - bexcen_0_sqmuxa, Y => N_5501); - - \r.mcfg2.rambanksz_RNI2E9C71[3]\ : MX2 - port map(A => haddr(18), B => haddr(26), S => - \rambanksz[3]\, Y => N_5098); - - \r.srhsel\ : DFN1 - port map(D => N_80, CLK => lclk_c, Q => srhsel); - - \r.address_RNI96NJ_6[0]\ : NOR2 - port map(A => N_425, B => \brmw_i\, Y => - \writedata_4_m_0[20]\); - - \r.writedata_RNO_1[29]\ : AOI1B - port map(A => \writedata_12_iv_0_0_a2_0[29]\, B => - hwdata_29, C => N_552, Y => \writedata_12_iv_0_0_0[29]\); - - \r.iosn[0]\ : DFN1P0 - port map(D => \iosn_i_m[1]\, CLK => lclk_c, PRE => rstn, Q - => iosn_c); - - \r.data_RNITAOK[15]\ : OR2A - port map(A => \hrdata[15]\, B => \address_RNI96NJ_3[0]\, Y - => \hrdata_m[15]\); - - \r.address_RNI6OQE2[0]\ : OR2A - port map(A => hwdata_3, B => N_671, Y => N_506); - - \r.address[25]\ : DFN1E1 - port map(D => haddr(25), CLK => lclk_c, E => N_36, Q => - address_c(25)); - - \r.mcfg2.rambanksz[1]\ : DFN1E1 - port map(D => pwdata_5, CLK => lclk_c, E => rmw_1_sqmuxa, Q - => \rambanksz[1]\); - - \r.address_RNIPQ7A1[0]\ : NOR2 - port map(A => \writedata_1_iv_0_a2_1_0[3]\, B => N_649, Y - => N_671); - - \r.busw_RNITO8A[1]\ : NOR2A - port map(A => \address_c[1]\, B => \busw[1]\, Y => - N_122_i_i_o2_0); - - \r.address_RNI59K6[0]\ : OR2B - port map(A => \address_c[1]\, B => \address_c[0]\, Y => - N_126_i); - - \r.writedata_RNO_3[28]\ : AO1B - port map(A => \writedata_1_iv_0[28]\, B => \hwdata_m[28]\, - C => N_123_i, Y => \writedata_m[28]\); - - \r.writedata[10]\ : DFN1E1 - port map(D => \writedata[10]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(10)); - - \r.busw_RNIBG5H1[1]\ : NOR2A - port map(A => hwdata_22, B => \busw[1]\, Y => N_6564); - - \r.hburst_RNIDSN2[0]\ : OR3 - port map(A => \hburst[1]\, B => \hburst[0]\, C => - \hburst[2]\, Y => hburst_i_0); - - \r.writedata_RNO_4[28]\ : OAI1 - port map(A => N_6555_i_0, B => N_38_i, C => \hrdata[28]\, Y - => \writedata_1_iv_0[28]\); - - \r.ramoen_RNO[2]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => ramoen_2_sqmuxa, C => - N_5178, Y => \ramoen_1[2]\); - - \r.bstate_RNO[7]\ : XO1A - port map(A => \bstate[7]\, B => iosn_1_sqmuxa, C => N_446, - Y => \bstate_RNO[7]\); - - \r.address_RNIGKGM_0[0]\ : OR2 - port map(A => N_425, B => N_394, Y => N_6563); - - \r.address[26]\ : DFN1E1 - port map(D => haddr(26), CLK => lclk_c, E => N_36, Q => - address_c(26)); - - \apbo.prdata_10_0_a2_0_0\ : OR2A - port map(A => paddr(2), B => paddr(3), Y => N_6455_0); - - \r.mcfg2.ramrws_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5520, Y => N_561); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I0_CO1_i\ : NOR2A - port map(A => \ws[0]\, B => \A_i[0]\, Y => N_4); - - \r.writedata_RNO_1[21]\ : OA1A - port map(A => \data[21]\, B => N_5160, C => N_539, Y => - \writedata_12_0_iv_i_a3_i_0[21]\); - - \r.srhsel_RNO\ : OA1A - port map(A => srhsel_0_sqmuxa, B => srhsel_RNO_0, C => rstn, - Y => N_80); - - \r.busw_RNO_0[1]\ : OR2A - port map(A => \iowidth[1]\, B => iosn_100, Y => - \iowidth_m[1]\); - - \r.ramsn[0]\ : DFN1E0P0 - port map(D => \ramsn_1_0[0]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => \ramsn_c[0]\); - - \r.data_RNITG792[0]\ : AOI1B - port map(A => hwdata_0, B => \N_6377\, C => \hrdata_m[0]\, - Y => \writedata_1_iv_0[0]\); - - \r.writedata[6]\ : DFN1E1 - port map(D => \writedata[6]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(6)); - - \r.writedata_RNO_1[18]\ : OR2 - port map(A => hwdata_2, B => N_440, Y => N_163); - - \r.ws_RNIU7HS[1]\ : OR2B - port map(A => ws_1, B => ws_0, Y => ws); - - \r.mcfg1.romrws[1]\ : DFN1 - port map(D => N_559, CLK => lclk_c, Q => \romrws[1]\); - - \r.bstate[5]\ : DFN1 - port map(D => N_295, CLK => lclk_c, Q => \bstate[5]\); - - \r.address[28]\ : DFN1E1 - port map(D => haddr(28), CLK => lclk_c, E => N_36, Q => - address(28)); - - \r.writedata[29]\ : DFN1E1 - port map(D => \writedata_12[29]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(29)); - - \r.address_RNI96NJ_4[0]\ : OR2 - port map(A => \brmw_i\, B => N_117, Y => \N_6550\); - - wsnew_0_sqmuxa : NAND2 - port map(A => \read_c\, B => \bstate[7]\, Y => - \wsnew_0_sqmuxa\); - - \r.mcfg2.ramwws_RNO_0[0]\ : MX2 - port map(A => \ramwws[0]\, B => pwdata_0_2, S => - rmw_1_sqmuxa, Y => N_5517); - - \r.address[29]\ : DFN1E1 - port map(D => haddr(29), CLK => lclk_c, E => N_36, Q => - address(29)); - - \r.wrn_RNO_1[1]\ : OA1B - port map(A => wrn_5_sqmuxa_s6_0_6, B => wrn_3_sqmuxa_s4_0_1, - C => wrn_1_sqmuxa_s2_0_3, Y => N_5195); - - \r.mcfg1.romrws_RNO_0[1]\ : MX2 - port map(A => \romrws[1]\, B => pwdata_0_1, S => - bexcen_0_sqmuxa, Y => N_5506); - - \r.ws_RNO_4[1]\ : OR3A - port map(A => \ramwws[1]\, B => N_6458, C => rws_0_sqmuxa, - Y => \ramwws_m[1]\); - - un1_wsnew_0_sqmuxa : NAND2 - port map(A => ws_0_sqmuxa, B => \wsnew_0_sqmuxa\, Y => - \un1_wsnew_0_sqmuxa\); - - \r.bdrive_RNO[1]\ : OA1C - port map(A => N_6568_i_0, B => \bdrive[1]\, C => N_6567_i_0, - Y => N_288); - - \r.busw[0]\ : DFN1E0 - port map(D => \busw_1[0]\, CLK => lclk_c, E => - srhsel_0_sqmuxa, Q => \busw[0]\); - - \r.ramoen_RNO[1]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => ramoen_2_sqmuxa, C => - N_5177, Y => \ramoen_1[1]\); - - \r.writedata_RNO_1[20]\ : OR2A - port map(A => \writedata[4]\, B => N_440, Y => - \writedata_m[4]\); - - \r.writedata[9]\ : DFN1E1 - port map(D => \writedata[9]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(9)); - - \r.writedata[21]\ : DFN1E1 - port map(D => N_6554, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[21]\); - - \r.area_RNITSBEJ1_0[1]\ : AO1C - port map(A => ws, B => address_1_sqmuxa_i_a2_1, C => - srhsel_0_sqmuxa, Y => N_36); - - \r.area_RNIHHBD[2]\ : OR2A - port map(A => \area[2]\, B => \area[1]\, Y => rws_0_sqmuxa); - - \r.bstate_RNI40681[7]\ : NOR2A - port map(A => \bstate[7]\, B => bstate_2_sqmuxa, Y => - oen_1_sqmuxa); - - \un1_v.ws_1_sqmuxa_2_m[2]\ : XAI1A - port map(A => N_4, B => ADD_4x4_fast_I11_Y_0_0, C => - bstate_3, Y => \ws_1_sqmuxa_2_m[2]\); - - \r.data_RNIPMNK_0[20]\ : OR2A - port map(A => \hrdata[20]\, B => \N_6550\, Y => - \hrdata_m[20]\); - - \r.ws[2]\ : DFN1 - port map(D => \ws_RNO[2]\, CLK => lclk_c, Q => \ws[2]\); - - \r.wrn[2]\ : DFN1 - port map(D => \wrn_RNO[2]\, CLK => lclk_c, Q => \rwen_c[2]\); - - \r.address_RNI59K6_1[0]\ : OR2A - port map(A => \address_c[0]\, B => \address_c[1]\, Y => - wrn8); - - \r.ws_RNO_2[0]\ : OR3B - port map(A => \un1_wsnew_0_sqmuxa\, B => \ramrws[0]\, C => - rws_0_sqmuxa, Y => \ramrws_m[0]\); - - \r.ready_RNINOQK\ : OR2 - port map(A => \hready\, B => N_413, Y => bstate_0_sqmuxa_0); - - \r.address[0]\ : DFN1E1 - port map(D => haddr(0), CLK => lclk_c, E => N_36_0, Q => - \address_c[0]\); - - \r.ready_RNO\ : OR3A - port map(A => rstn, B => N_661, C => ready_0_0_o2_0, Y => - ready_RNO); - - \r.mcfg2.rambanksz_RNI6IDMU9[0]\ : MX2 - port map(A => N_5088, B => N_5103, S => \rambanksz[0]\, Y - => \adec_2[0]\); - - \r.data[25]\ : DFN1 - port map(D => data_in(25), CLK => lclk_c, Q => \hrdata[25]\); - - \r.mcfg2.rambanksz_RNI5ETH71[3]\ : MX2 - port map(A => haddr(15), B => haddr(23), S => - \rambanksz[3]\, Y => N_5085); - - \r.busw_RNILVCG[0]\ : MX2C - port map(A => \address_c[0]\, B => brmw, S => \busw[0]\, Y - => N_122_i_i_o2_1); - - \r.area[0]\ : DFN1E0 - port map(D => hmbsel_1(0), CLK => lclk_c, E => - srhsel_0_sqmuxa, Q => \area[0]\); - - \r.mcfg2.rambanksz_RNIGN9JF2[2]\ : MX2C - port map(A => N_5100, B => N_5101, S => \rambanksz[2]\, Y - => N_5094); - - \r.data[11]\ : DFN1 - port map(D => data_in(11), CLK => lclk_c, Q => \hrdata[11]\); - - \r.srhsel_RNI8LPQ\ : NOR2A - port map(A => N_412, B => N_424, Y => N_431); - - \r.data_RNI11A41[22]\ : OR3B - port map(A => brmw, B => \hrdata[22]\, C => N_439, Y => - N_634); - - \r.wrn[0]\ : DFN1 - port map(D => \wrn_RNO[0]\, CLK => lclk_c, Q => \rwen_c[0]\); - - \r.mcfg2.rambanksz_RNIKV56V4[1]\ : MX2C - port map(A => N_5091, B => N_5094, S => \rambanksz[1]\, Y - => N_5103); - - \r.writedata_RNO[28]\ : OR3C - port map(A => \writedata_12_iv_0[28]\, B => - \writedata_m[12]\, C => \writedata_m_0[20]\, Y => - \writedata_12[28]\); - - \r.data_RNI7LOV2[13]\ : OR2B - port map(A => N_6411, B => N_6410, Y => \writedata[13]\); - - \r.writedata_RNO[21]\ : OR3C - port map(A => \writedata_12_0_iv_i_a3_i_2_0[21]\, B => - \writedata_12_0_iv_i_a3_i_0[21]\, C => N_543, Y => N_6554); - - \r.ready_RNIL0CH1\ : OR2 - port map(A => ws, B => bstate_0_sqmuxa_0, Y => - bstate_0_sqmuxa_1); - - \r.area_RNI59B2A2[1]\ : NOR2 - port map(A => bstate_0_sqmuxa_1, B => N_195, Y => - bstate_0_sqmuxa); - - \r.writedata[12]\ : DFN1E1 - port map(D => \writedata[12]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(12)); - - \r.writedata_RNO_3[16]\ : OR2A - port map(A => \hrdata[16]\, B => N_448, Y => N_532); - - \r.mcfg2.ramwidth_RNIS2P4K[1]\ : NOR3C - port map(A => \rmw\, B => \ramwidth[1]\, C => haddr(30), Y - => brmw_1_1); - - \r.writedata_RNO_4[18]\ : OAI1 - port map(A => N_425, B => \busw[1]\, C => N_669, Y => - N_16464_tz); - - \r.writedata_RNO_0[16]\ : OA1A - port map(A => \data[16]\, B => N_5160, C => N_532, Y => - \writedata_12_0_iv_0_0[16]\); - - \r.mcfg2.rambanksz_RNIV3N4V4[1]\ : MX2C - port map(A => N_5106, B => N_5109, S => \rambanksz[1]\, Y - => N_5110); - - \r.writedata_RNO_0[2]\ : NOR2A - port map(A => \brmw_i\, B => hwdata_2, Y => N_149); - - \r.brmw_RNI4JE41\ : OA1B - port map(A => N_517, B => \writedata_12_0_iv_i_a2_4_0[18]\, - C => N_199, Y => N_106); - - \r.wrn_RNO_2[3]\ : MX2A - port map(A => \address_c[1]\, B => \rwen_c[3]\, S => N_6549, - Y => N_5203); - - \r.wrn_RNO_3[3]\ : OR3A - port map(A => N_394, B => wrn35, C => wrn_5_sqmuxa_s6_0_0, - Y => wrn_5_sqmuxa_s6_0_1); - - \r.area_RNIVJGU[0]\ : OR2B - port map(A => hresp2_i_0, B => N_412, Y => N_6547); - - \r.bstate_RNI2NQID2[5]\ : AOI1 - port map(A => romsn_1_sqmuxa, B => bstate_5_1, C => - iosn_1_0, Y => romsn_0_sqmuxa_1); - - \r.bstate_0_i_o2[5]\ : OR2B - port map(A => ramoen_0_sqmuxa, B => rstn, Y => N_446); - - \r.address[20]\ : DFN1E1 - port map(D => haddr(20), CLK => lclk_c, E => N_36_0, Q => - address_c(20)); - - \r.busw_RNI3T2D[0]\ : NOR2B - port map(A => \busw[0]\, B => brmw, Y => N_635); - - \r.address[15]\ : DFN1E1 - port map(D => haddr(15), CLK => lclk_c, E => N_36_0, Q => - address_c(15)); - - \r.data_RNISALJ1[20]\ : MX2 - port map(A => hwdata_20, B => \hrdata[20]\, S => N_394, Y - => \writedata_4[20]\); - - \r.area_RNISN3H_0[0]\ : NOR3A - port map(A => \area[0]\, B => romwrite, C => \read_c\, Y - => N_653); - - \r.data_RNIQUNK[12]\ : OR2A - port map(A => \hrdata[12]\, B => \address_RNI96NJ_3[0]\, Y - => \hrdata_m[12]\); - - \r.data[17]\ : DFN1 - port map(D => data_in(17), CLK => lclk_c, Q => \hrdata[17]\); - - \r.data_RNIR2OK[13]\ : OR2A - port map(A => \hrdata[13]\, B => \address_RNI96NJ_3[0]\, Y - => N_6410); - - \r.busw_RNIVF341[1]\ : OR2B - port map(A => \busw[1]\, B => N_439, Y => N_669); - - \r.data_RNIPMNK[20]\ : OR3A - port map(A => \hrdata[20]\, B => N_126_i, C => \brmw_i\, Y - => \hrdata_m_0[20]\); - - \r.mcfg1.romwws_RNO[0]\ : OR2A - port map(A => rstn, B => N_5501, Y => \romwws_RNO[0]\); - - \r.mcfg1.iowidth[0]\ : DFN1E1 - port map(D => pwdata_22, CLK => lclk_c, E => - bexcen_0_sqmuxa, Q => \iowidth[0]\); - - \r.data[9]\ : DFN1 - port map(D => data_in(9), CLK => lclk_c, Q => \hrdata[9]\); - - \r.writedata_RNO[19]\ : OR3C - port map(A => \writedata_m[19]\, B => \data_m[19]\, C => - \writedata_m[3]\, Y => \writedata_12[19]\); - - \r.writedata[27]\ : DFN1E1 - port map(D => \writedata_12[27]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(27)); - - \r.mcfg1.iows_RNO_0[2]\ : MX2 - port map(A => \iows[2]\, B => pwdata_17, S => - bexcen_0_sqmuxa, Y => N_5511); - - \r.address[16]\ : DFN1E1 - port map(D => haddr(16), CLK => lclk_c, E => N_36_0, Q => - address_c(16)); - - \r.romsn_RNO[1]\ : OR3A - port map(A => haddr(28), B => hmbsel(0), C => - \un1_romsn_0_sqmuxa_1_0[0]_net_1\, Y => \romsn_1[1]\); - - \r.ramsn[1]\ : DFN1E0P0 - port map(D => \ramsn_1_0[1]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => \ramsn_c[1]\); - - \r.writedata_RNO_3[25]\ : OR2B - port map(A => writedata_1_sqmuxa, B => hwdata_17, Y => - N_188); - - \r.writedata_RNO_1[28]\ : OR2A - port map(A => \writedata[12]\, B => N_440, Y => - \writedata_m[12]\); - - \r.ramoen_RNO[3]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => ramoen_2_sqmuxa, C => - N_5179, Y => \ramoen_1[3]\); - - \r.mcfg1.iows[3]\ : DFN1 - port map(D => N_567, CLK => lclk_c, Q => \iows[3]\); - - \r.iosn_RNO[1]\ : OA1A - port map(A => iosn_1_8, B => srhsel_0_sqmuxa, C => - \iosn_i_m[1]\, Y => \iosn_1_iv[1]\); - - \r.writedata_RNO_3[17]\ : OR2A - port map(A => \data[17]\, B => N_5160, Y => N_514); - - \apbo.prdata[28]\ : NOR2A - port map(A => \iowidth[1]\, B => N_232_0, Y => prdata_8); - - \r.mcfg1.romwws_RNO_0[1]\ : MX2 - port map(A => \romwws[1]\, B => pwdata_0_5, S => - bexcen_0_sqmuxa, Y => N_5502); - - \r.mcfg1.romwws_RNO[2]\ : OR2A - port map(A => rstn, B => N_5503, Y => \romwws_RNO[2]\); - - \r.address[18]\ : DFN1E1 - port map(D => haddr(18), CLK => lclk_c, E => N_36_0, Q => - address_c(18)); - - \r.address_RNI96NJ_2[0]\ : OR2A - port map(A => N_126_i, B => \brmw_i\, Y => - \writedata_1_iv_0_a2_1_0[3]\); - - \r.writedata_RNO_0[17]\ : AO1B - port map(A => N_669, B => N_420, C => hwdata_17, Y => N_511); - - \r.brmw_RNI4T2D_0\ : NOR2A - port map(A => \busw[1]\, B => brmw, Y => N_199); - - \r.busw_RNO[1]\ : OR3C - port map(A => \iowidth_m[1]\, B => \ramwidth_m[1]\, C => - \romwidth_m[1]\, Y => \busw_1[1]\); - - \r.address[19]\ : DFN1E1 - port map(D => haddr(19), CLK => lclk_c, E => N_36_0, Q => - address_c(19)); - - \r.writedata_RNO_5[30]\ : OR2B - port map(A => hwdata_30, B => \address_RNI96NJ_5[0]\, Y => - \hwdata_m[30]\); - - \r.busw_RNI577H[0]\ : OR3A - port map(A => \address_c[0]\, B => \busw[0]\, C => - \busw[1]\, Y => N_5160); - - \r.data_RNITKT71[7]\ : MX2 - port map(A => hwdata_7, B => \hrdata[7]\, S => N_394, Y => - \writedata_10[7]\); - - \r.writedata_RNO_0[31]\ : OA1A - port map(A => \writedata[15]\, B => N_440, C => - \writedata_12_iv_0[31]\, Y => \writedata_12_iv_1[31]\); - - \r.bdrive_RNIA1PF[0]\ : NOR2B - port map(A => \bstate[7]\, B => \bdrive[0]\, Y => - writedata_0_sqmuxa_0); - - \r.mcfg2.rambanksz_RNIU17O4L_2[0]\ : NOR3A - port map(A => \adec_2[1]\, B => iosn_99, C => \adec_2[0]\, - Y => \ramsn_1[0]\); - - \r.ws_RNO_4[2]\ : OR3C - port map(A => rstn, B => un1_rws_0_sqmuxa, C => \iows[2]\, - Y => N_6444); - - \r.data_RNIO7NP1[8]\ : MX2 - port map(A => \hrdata[8]\, B => hwdata_8, S => - \address_RNI96NJ_3[0]\, Y => \writedata[8]\); - - \r.writedata_RNO[23]\ : AO1C - port map(A => N_440, B => \writedata[7]\, C => - \writedata_12_0_iv_0[23]\, Y => \writedata_12[23]\); - - \r.writedata_RNO_5[26]\ : NOR2B - port map(A => writedata_1_sqmuxa, B => N_160, Y => - \writedata_m_0_0[18]\); - - \r.ramsn_RNO[0]\ : OR2A - port map(A => \ramsn_1[0]\, B => srhsel_0_sqmuxa, Y => - \ramsn_1_0[0]\); - - \r.writedata_RNO_0[26]\ : AO1B - port map(A => \writedata_1_iv_0[26]\, B => \hwdata_m[26]\, - C => N_123_i, Y => \writedata_m[26]\); - - \r.data_RNIPC9L4[12]\ : OR3C - port map(A => hwdata_m_5, B => \hrdata_m[12]\, C => - hwdata_m_0_0, Y => \writedata[12]\); - - \r.size_RNIEJF92[1]\ : NOR3 - port map(A => un1_wrn35_1, B => N_424, C => N_6547, Y => - wrn_1_sqmuxa_s2_0_3); - - \r.ramoen[0]\ : DFN1E0P0 - port map(D => \ramoen_1[0]\, CLK => lclk_c, PRE => rstn, E - => ramoen_0_sqmuxa_1, Q => ramoen_c(0)); - - \r.size_RNIBBSF[0]\ : NOR2 - port map(A => \size[1]\, B => \size[0]\, Y => N_394); - - \r.bstate[6]\ : DFN1 - port map(D => \bstate_RNO[6]\, CLK => lclk_c, Q => - \bstate[6]\); - - \r.address[27]\ : DFN1E1 - port map(D => haddr(27), CLK => lclk_c, E => N_36, Q => - address_c(27)); - - \r.wrn_RNO_1[0]\ : OA1B - port map(A => wrn_5_sqmuxa_s6_0_6, B => wrn_2_sqmuxa_s3_0_1, - C => wrn_1_sqmuxa_s2_0_3, Y => N_5194); - - \r.writedata_RNO[20]\ : AO1B - port map(A => \writedata[20]\, B => N_123_i, C => - \writedata_12_0_iv_0[20]\, Y => \writedata_12[20]\); - - \r.writedata_RNO_3[24]\ : OR2 - port map(A => \hrdata[24]\, B => \address_RNI96NJ_5[0]\, Y - => \writedata_RNO_3[24]\); - - \r.bstate_RNO_1[4]\ : NOR2A - port map(A => N_438, B => iosn_1_sqmuxa, Y => N_618); - - \r.mcfg1.romrws[0]\ : DFN1 - port map(D => N_558, CLK => lclk_c, Q => \romrws[0]\); - - \r.writedata[4]\ : DFN1E1 - port map(D => \writedata[4]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(4)); - - \r.mcfg2.rambanksz_RNIVCRGF2[2]\ : MX2C - port map(A => N_5085, B => N_5086, S => \rambanksz[2]\, Y - => N_5106); - - \r.mcfg2.ramrws[0]\ : DFN1 - port map(D => \ramrws_RNO[0]\, CLK => lclk_c, Q => - \ramrws[0]\); - - \r.address[21]\ : DFN1E1 - port map(D => haddr(21), CLK => lclk_c, E => N_36_0, Q => - address_c(21)); - - \r.writedata_RNO_3[19]\ : OA1A - port map(A => N_439, B => hwdata_19, C => - \writedata_m_0[19]\, Y => \writedata_m_1[19]\); - - \r.mcfg1.brdyen_RNO\ : NOR2B - port map(A => rstn, B => N_5527, Y => brdyen_RNO); - - \r.bstate[7]\ : DFN1 - port map(D => \bstate_RNO[7]\, CLK => lclk_c, Q => - \bstate[7]\); - - \r.writedata_RNO_0[30]\ : OR2A - port map(A => \writedata[14]\, B => N_440, Y => - \writedata_m[14]\); - - \r.writedata[16]\ : DFN1E1 - port map(D => \writedata_12[16]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[16]\); - - \r.writedata_RNO_1[23]\ : OR2A - port map(A => \data[23]\, B => N_5160, Y => \data_m[23]\); - - \r.writedata_RNO[16]\ : OR3C - port map(A => \writedata_12_0_iv_0_0[16]\, B => N_530, C - => N_531, Y => \writedata_12[16]\); - - \r.ramoen[3]\ : DFN1E0P0 - port map(D => \ramoen_1[3]\, CLK => lclk_c, PRE => rstn, E - => ramoen_0_sqmuxa_1, Q => ramoen_c(3)); - - \r.writedata_RNO_5[19]\ : OR2 - port map(A => \hrdata[19]\, B => \brmw_i\, Y => - \writedata_0_iv_i_a2_0[19]\); - - \r.mcfg2.ramwws_RNO_0[1]\ : MX2 - port map(A => \ramwws[1]\, B => pwdata_1_2, S => - rmw_1_sqmuxa, Y => N_5518); - - \r.writedata_RNO_4[24]\ : OR2A - port map(A => writedata_1_sqmuxa, B => hwdata_16, Y => - N_193); - - \r.writedata[13]\ : DFN1E1 - port map(D => \writedata[13]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(13)); - - \ctrl.v.writedata_12_iv_0_a2[25]\ : NAND2 - port map(A => N_111, B => hwdata_25, Y => N_185); - - \r.writedata_RNO_0[19]\ : AO1C - port map(A => hwdata_19, B => \brmw_i\, C => - \writedata_m_1[19]\, Y => \writedata_m[19]\); - - \r.data_RNILEFN[0]\ : OR2A - port map(A => \hrdata[0]\, B => N_5112, Y => \hrdata_m[0]\); - - \r.area[2]\ : DFN1E0 - port map(D => haddr(30), CLK => lclk_c, E => - srhsel_0_sqmuxa, Q => \area[2]\); - - \r.writedata_RNO_2[26]\ : AOI1B - port map(A => hwdata_2, B => N_46_i_0, C => - \writedata_m[10]\, Y => \writedata_12_iv_0[26]\); - - \r.bstate_RNO_1[5]\ : NOR2 - port map(A => iosn_1_sqmuxa_1_0, B => \bstate[5]\, Y => - N_617); - - \r.address[22]\ : DFN1E1 - port map(D => haddr(22), CLK => lclk_c, E => N_36_0, Q => - address_c(22)); - - \r.area_RNIAELE[2]\ : NOR2B - port map(A => \rmw\, B => \area[2]\, Y => wrn35); - - \r.address[2]\ : DFN1E1 - port map(D => haddr(2), CLK => lclk_c, E => N_36, Q => - address_c(2)); - - \r.writen\ : DFN1 - port map(D => writen_RNO, CLK => lclk_c, Q => \writen_c\); - - \r.mcfg1.romwrite_RNO\ : NOR2B - port map(A => rstn, B => N_5525, Y => romwrite_RNO); - - \r.writedata[30]\ : DFN1E1 - port map(D => \writedata_12[30]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(30)); - - \r.mcfg2.rambanksz_RNIU17O4L[0]\ : OR3B - port map(A => \adec_2[1]\, B => \adec_2[0]\, C => iosn_99, - Y => \ramsn_1[1]\); - - \r.data_RNICN8B1[23]\ : OR3A - port map(A => \hrdata[23]\, B => \brmw_i\, C => N_439, Y - => N_538); - - \r.writen_RNO_2\ : OR2A - port map(A => ramoen_0_sqmuxa, B => N_435, Y => N_280); - - \r.wrn_RNO_2[2]\ : MX2A - port map(A => \address_c[1]\, B => \rwen_c[2]\, S => N_6549, - Y => N_5202); - - \r.mcfg2.ramrws[1]\ : DFN1 - port map(D => N_561, CLK => lclk_c, Q => \ramrws[1]\); - - \r.bstate_RNI29IF5[4]\ : OR2B - port map(A => N_6549, B => N_435, Y => writen_0_sqmuxa_1_0); - - \r.mcfg2.ramwws[0]\ : DFN1 - port map(D => N_562, CLK => lclk_c, Q => \ramwws[0]\); - - \ctrl.v.writedata_12_iv_0_a2_1[25]\ : OR2A - port map(A => \hrdata[25]\, B => \address_RNI96NJ_5[0]\, Y - => N_187); - - \r.read\ : DFN1 - port map(D => read_RNO_0, CLK => lclk_c, Q => \read_c\); - - \r.bstate_RNI4B6BA8[7]\ : OR2B - port map(A => oen_1_sqmuxa, B => un1_iosn, Y => - ramoen_1_sqmuxa_1); - - \r.bstate[4]\ : DFN1 - port map(D => N_297, CLK => lclk_c, Q => \bstate[4]\); - - \r.writedata_RNO_0[11]\ : OR3B - port map(A => N_117, B => \hrdata[11]\, C => \brmw_i\, Y - => N_155); - - \r.iosn_RNI0G0KD2[1]\ : AO1 - port map(A => iosn_1_sqmuxa_1, B => bstate_5_1, C => - \iosn_1_iv_0_a2_0[1]\, Y => \iosn_i_m[1]\); - - \r.address_RNICI0B2[0]\ : OR2B - port map(A => hwdata_13, B => \address_RNI96NJ_3[0]\, Y => - N_6411); - - \r.writedata_RNO_0[27]\ : OA1A - port map(A => hwdata_11, B => N_440, C => - \writedata_12_iv_0_0[27]\, Y => \writedata_12_iv_0_1[27]\); - - \r.ws_RNO_0[2]\ : OR3C - port map(A => \un1_wsnew_0_sqmuxa\, B => \romrws[2]\, C => - N_6457, Y => N_6445); - - \r.bdrive_RNIA1PF_0[0]\ : NOR2B - port map(A => \bstate[7]\, B => \bdrive[0]\, Y => - writedata_0_sqmuxa); - - \r.ws_RNO[1]\ : AOI1B - port map(A => \ws_3_iv_3[1]\, B => \ws_1_sqmuxa_2_m[2]\, C - => rstn, Y => \ws_RNO[1]\); - - \r.writedata[3]\ : DFN1E1 - port map(D => \writedata[3]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(3)); - - \r.address[10]\ : DFN1E1 - port map(D => haddr(10), CLK => lclk_c, E => N_36_0, Q => - address_c(10)); - - \r.ws_RNO_3[1]\ : OR2B - port map(A => un1_rws_0_sqmuxa, B => \iows[1]\, Y => - \iows_m[1]\); - - \r.read_RNO\ : OR2B - port map(A => un18_srhsel, B => rstn, Y => read_RNO_0); - - \r.mcfg1.iows[0]\ : DFN1 - port map(D => N_564, CLK => lclk_c, Q => \iows[0]\); - - \r.address[7]\ : DFN1E1 - port map(D => haddr(7), CLK => lclk_c, E => N_36, Q => - address_c(7)); - - \r.data_RNIBT864[23]\ : AO1B - port map(A => hwdata_23, B => N_448, C => N_538, Y => - \writedata[23]\); - - \r.mcfg1.romwidth_RNO[1]\ : OR2A - port map(A => rstn, B => pwdata_0_9, Y => \romwidth_1[1]\); - - \r.mcfg1.romrws_RNO_0[0]\ : MX2 - port map(A => \romrws[0]\, B => pwdata_0_0, S => - bexcen_0_sqmuxa, Y => N_5505); - - \r.ws_RNO_1[0]\ : NOR3C - port map(A => \ramwws_m[0]\, B => \romwws_m[0]\, C => - \romrws_m[0]\, Y => \ws_3_iv_1[0]\); - - \r.data_RNI1KB75[20]\ : OR2B - port map(A => \writedata_0_iv_1[20]\, B => - \writedata_4_m[20]\, Y => \writedata[20]\); - - \r.hresp[0]\ : DFN1 - port map(D => \hresp_6[0]\, CLK => lclk_c, Q => hresp(0)); - - \r.bdrive[1]\ : DFN1P0 - port map(D => N_288, CLK => lclk_c, PRE => rstn, Q => - \bdrive[1]\); - - \r.data[14]\ : DFN1 - port map(D => data_in(14), CLK => lclk_c, Q => \hrdata[14]\); - - \r.busw_RNO_2[0]\ : OR2A - port map(A => \ramwidth[0]\, B => iosn_99, Y => - \ramwidth_m[0]\); - - \r.wrn_RNO[1]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => \wrn_90[1]\, C => rstn, - Y => \wrn_RNO[1]\); - - \r.writedata_RNO_3[2]\ : OR2 - port map(A => \hrdata[2]\, B => N_108, Y => - \writedata_1_iv_i_a2_2_0[2]\); - - \r.writedata_RNO_2[27]\ : OR2B - port map(A => \writedata[3]\, B => N_46_i_0, Y => N_184); - - \r.data[21]\ : DFN1 - port map(D => data_in(21), CLK => lclk_c, Q => \hrdata[21]\); - - \r.mcfg2.rambanksz_RNI03O8V4[1]\ : MX2C - port map(A => N_5084, B => N_5106, S => \rambanksz[1]\, Y - => N_5088); - - \r.mcfg1.iows_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5510, Y => N_565); - - \r.brmw_RNI4T2D\ : OR2B - port map(A => \busw[1]\, B => brmw, Y => \brmw_i\); - - \r.mcfg1.ioen_RNI3SCD\ : OR2A - port map(A => \area[1]\, B => \ioen\, Y => N_412); - - \r.writedata_RNO_5[29]\ : OR3B - port map(A => N_425, B => \hrdata[29]\, C => \brmw_i\, Y - => N_552); - - \r.writedata_RNO_0[29]\ : AOI1B - port map(A => writedata_1_sqmuxa, B => hwdata_21, C => - N_555, Y => \writedata_12_iv_0_0_1[29]\); - - \apbo.prdata[21]\ : NOR2A - port map(A => \iows[1]\, B => N_232_0, Y => prdata_1); - - \r.bdrive[2]\ : DFN1P0 - port map(D => N_290, CLK => lclk_c, PRE => rstn, Q => - \bdrive[2]\); - - \r.mcfg2.rambanksz_RNIREJN71[3]\ : MX2 - port map(A => haddr(14), B => haddr(22), S => - \rambanksz[3]\, Y => N_5097); - - \r.mcfg2.rambanksz_RNIE2DGF2[2]\ : MX2C - port map(A => N_5082, B => N_5107, S => \rambanksz[2]\, Y - => N_5084); - - \r.data_RNIE9UH4[0]\ : AO1C - port map(A => \N_6550\, B => \writedata_10[0]\, C => - \writedata_1_iv_0[0]\, Y => \writedata[0]\); - - \r.ready\ : DFN1 - port map(D => ready_RNO, CLK => lclk_c, Q => \hready\); - - \r.ws_RNIVJ8E[1]\ : NOR2 - port map(A => \ws[1]\, B => \ws[2]\, Y => ws_1); - - \r.brmw_RNIG6GD2\ : OR2A - port map(A => hwdata_22, B => N_449, Y => N_633); - - \r.writedata[15]\ : DFN1E1 - port map(D => \writedata[15]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(15)); - - \r.address_RNILT4T[0]\ : OR2B - port map(A => wrn8, B => N_6563, Y => N_439); - - \r.writedata_RNO_1[25]\ : AND2 - port map(A => N_185, B => N_187, Y => - \writedata_12_iv_0_0[25]\); - - \r.mcfg1.iowidth[1]\ : DFN1E1 - port map(D => pwdata_23, CLK => lclk_c, E => - bexcen_0_sqmuxa, Q => \iowidth[1]\); - - \r.writedata[18]\ : DFN1E1 - port map(D => N_62_i_0, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[18]\); - - \r.address[6]\ : DFN1E1 - port map(D => haddr(6), CLK => lclk_c, E => N_36, Q => - address_c(6)); - - \r.bstate_RNIVF4U2[4]\ : OR2B - port map(A => N_610, B => N_438, Y => N_435); - - \r.writedata_RNO_2[29]\ : OR2A - port map(A => \writedata[13]\, B => N_440, Y => N_554); - - \r.busw_RNIERID[0]\ : OA1C - port map(A => \address_c[0]\, B => \busw[0]\, C => - \address_c[1]\, Y => N_636); - - \r.bstate_RNISTTM[4]\ : OR2 - port map(A => ws_1_sqmuxa, B => \bstate[4]\, Y => N_442); - - \r.ramoen[1]\ : DFN1E0P0 - port map(D => \ramoen_1[1]\, CLK => lclk_c, PRE => rstn, E - => ramoen_0_sqmuxa_1, Q => ramoen_c(1)); - - \r.address[17]\ : DFN1E1 - port map(D => haddr(17), CLK => lclk_c, E => N_36_0, Q => - address_c(17)); - - \r.writedata_RNO_0[21]\ : AO1B - port map(A => \writedata_12_0_iv_i_a3_i_2_0_tz_0[21]\, B - => N_420, C => hwdata_21, Y => - \writedata_12_0_iv_i_a3_i_2_0[21]\); - - \r.srhsel_RNO_0\ : NOR3A - port map(A => srhsel, B => N_661, C => ready_0_0_o2_0, Y - => srhsel_RNO_0); - - \r.ws_RNO_1[1]\ : NOR3C - port map(A => \ramwws_m[1]\, B => \romwws_m[1]\, C => - \romrws_m[1]\, Y => \ws_3_iv_1[1]\); - - \r.writedata_RNO_2[31]\ : AO1B - port map(A => hwdata_31, B => \address_RNI96NJ_5[0]\, C => - \writedata_1_iv_0[31]\, Y => \writedata[31]\); - - \r.bstate_RNO_2[5]\ : NOR3B - port map(A => \read_c\, B => N_431, C => \oen_c\, Y => - N_451); - - \r.mcfg1.romwrite_RNO_0\ : MX2 - port map(A => romwrite, B => pwdata_0_11, S => - bexcen_0_sqmuxa, Y => N_5525); - - \r.data[27]\ : DFN1 - port map(D => data_in(27), CLK => lclk_c, Q => \hrdata[27]\); - - \r.address_RNIILPG1[0]\ : OR2B - port map(A => hwdata_10, B => \address_RNI96NJ_3[0]\, Y => - N_6385); - - \r.address[11]\ : DFN1E1 - port map(D => haddr(11), CLK => lclk_c, E => N_36_0, Q => - address_c(11)); - - \r.data[19]\ : DFN1 - port map(D => data_in(19), CLK => lclk_c, Q => \hrdata[19]\); - - \r.data_RNIT72J3[4]\ : OR2B - port map(A => N_550, B => N_549, Y => \writedata[4]\); - - \r.data_RNIGB9B1[18]\ : OR2 - port map(A => \hrdata[18]\, B => N_448, Y => N_160); - - \r.oen_RNIMA801\ : OR2B - port map(A => bstate_2_sqmuxa_1_0, B => N_412, Y => - bstate_2_sqmuxa); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I12_Y_0_0\ : XOR2 - port map(A => \ws[2]\, B => \A_i[0]\, Y => - ADD_4x4_fast_I12_Y_0_0); - - \r.address[12]\ : DFN1E1 - port map(D => haddr(12), CLK => lclk_c, E => N_36_0, Q => - address_c(12)); - - \r.address_RNI96NJ_1[0]\ : OR2A - port map(A => N_126_i, B => \brmw_i\, Y => \N_6377\); - - \r.mcfg2.rambanksz[2]\ : DFN1E1 - port map(D => pwdata_6, CLK => lclk_c, E => rmw_1_sqmuxa, Q - => \rambanksz[2]\); - - \r.writedata_RNO[29]\ : OR3C - port map(A => \writedata_12_iv_0_0_1[29]\, B => - \writedata_12_iv_0_0_0[29]\, C => N_554, Y => - \writedata_12[29]\); - - \r.mcfg1.romrws_RNO[2]\ : OR2A - port map(A => rstn, B => N_5507, Y => \romrws_RNO[2]\); - - \r.writedata_RNO_1[24]\ : NOR3C - port map(A => N_190, B => \writedata_RNO_3[24]\, C => N_193, - Y => \writedata_12_iv_i_1[24]\); - - \r.writedata_RNO_2[21]\ : OR2A - port map(A => hwdata_5, B => N_440, Y => N_543); - - \r.ramoen_RNO_0[0]\ : MX2A - port map(A => \ramsn_c[0]\, B => \ramsn_1[0]\, S => - ramoen_1_sqmuxa_1, Y => N_5176); - - \r.writedata_RNO_0[20]\ : OA1A - port map(A => \data[20]\, B => N_5160, C => - \writedata_m[4]\, Y => \writedata_12_0_iv_0[20]\); - - \r.address[4]\ : DFN1E1 - port map(D => haddr(4), CLK => lclk_c, E => N_36, Q => - address_c(4)); - - \r.wrn_RNO_1[3]\ : OA1B - port map(A => wrn_5_sqmuxa_s6_0_6, B => wrn_5_sqmuxa_s6_0_1, - C => wrn_1_sqmuxa_s2_0_3, Y => N_5197); - - \r.area_RNITSBEJ1[1]\ : AO1C - port map(A => ws, B => address_1_sqmuxa_i_a2_1, C => - srhsel_0_sqmuxa, Y => N_36_0); - - \r.writedata_RNO_2[30]\ : OAI1 - port map(A => N_515, B => N_6564, C => writedata_1_sqmuxa, - Y => \writedata_m_0[22]\); - - \r.mcfg2.rambanksz[3]\ : DFN1E1 - port map(D => pwdata_7, CLK => lclk_c, E => rmw_1_sqmuxa, Q - => \rambanksz[3]\); - - \r.writedata_RNO[17]\ : OR3C - port map(A => N_511, B => N_513, C => - \writedata_12_0_iv_0_0[17]\, Y => \writedata_12[17]\); - - \r.writen_RNO_1\ : OR2B - port map(A => ramoen_0_sqmuxa, B => N_610, Y => - iosn_0_sqmuxa); - - \r.writedata_RNO_3[18]\ : OR2 - port map(A => \data[18]\, B => N_5160, Y => - \writedata_RNO_3[18]\); - - \r.oen_RNO\ : AO1C - port map(A => bstate16_1, B => iosn_1_0, C => - ramoen_2_sqmuxa, Y => ramoen_2_sqmuxa_1); - - \r.mcfg2.rambanksz[0]\ : DFN1E1 - port map(D => pwdata_4, CLK => lclk_c, E => rmw_1_sqmuxa, Q - => \rambanksz[0]\); - - \r.area_RNIBDNE[2]\ : NOR2A - port map(A => rstn, B => rws_1_sqmuxa, Y => N_6457); - - \r.writedata_RNO_3[31]\ : OR2B - port map(A => \writedata[23]\, B => writedata_1_sqmuxa, Y - => \writedata_m_0[23]\); - - \r.writedata_RNO_0[18]\ : NOR2B - port map(A => \writedata_RNO_3[18]\, B => N_160, Y => - \writedata_12_0_iv_i_0[18]\); - - \r.mcfg1.romwws_RNO_0[2]\ : MX2 - port map(A => \romwws[2]\, B => pwdata_0_6, S => - bexcen_0_sqmuxa, Y => N_5503); - - \r.busw_RNIFBBK[1]\ : OR2A - port map(A => \busw[1]\, B => N_424, Y => - wrn_2_sqmuxa_s3_0_6_1); - - \r.bdrive_RNIUBR7[2]\ : INV - port map(A => \bdrive[2]\, Y => bdrive_i(2)); - - \r.bstate_RNIUU6LJA[6]\ : OR2B - port map(A => bstate_4, B => un1_iosn, Y => ramoen_2_sqmuxa); - - \r.address_RNI59K6_2[0]\ : OR2 - port map(A => \address_c[1]\, B => \address_c[0]\, Y => - N_425); - - \r.writedata_RNO[5]\ : MX2 - port map(A => hwdata_5, B => \hrdata[5]\, S => N_671, Y => - \writedata[5]\); - - \r.busw_RNIHOLQ[0]\ : OR2 - port map(A => N_636, B => N_635, Y => N_396); - - \r.address_RNI22O12[0]\ : OR2A - port map(A => hwdata_4, B => N_671, Y => N_549); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I6_Y_0_a3_0\ : NOR2A - port map(A => \ws[1]\, B => \A_i[0]\, Y => N_16); - - \r.busw_RNIHKT36[1]\ : OR2 - port map(A => wrn_2_sqmuxa_s3_0_6_1, B => - writen_0_sqmuxa_1_0, Y => wrn_5_sqmuxa_s6_0_6); - - \r.ramoen[2]\ : DFN1E0P0 - port map(D => \ramoen_1[2]\, CLK => lclk_c, PRE => rstn, E - => ramoen_0_sqmuxa_1, Q => ramoen_c(2)); - - \r.mcfg1.iows[2]\ : DFN1 - port map(D => N_566, CLK => lclk_c, Q => \iows[2]\); - - \r.mcfg1.ioen_RNO\ : NOR2B - port map(A => rstn, B => N_5526, Y => ioen_RNO); - - \r.data_RNIMA2E3[15]\ : OR3C - port map(A => hwdata_m_8, B => \hrdata_m[15]\, C => - hwdata_m_0_3, Y => \writedata[15]\); - - \r.area_RNI3CQR[1]\ : NOR3A - port map(A => ws_1_sqmuxa, B => brmw, C => \area[1]\, Y => - address_1_sqmuxa_i_a2_1); - - \r.mcfg1.iows_RNO_0[0]\ : MX2 - port map(A => \iows[0]\, B => pwdata_15, S => - bexcen_0_sqmuxa, Y => N_5509); - - \r.busw_RNIRPOO3[1]\ : AOI1B - port map(A => N_634, B => N_633, C => \busw[1]\, Y => N_515); - - \v.mcfg1.bexcen_1_sqmuxa_i_i_a2\ : NOR2A - port map(A => rstn, B => bexcen_0_sqmuxa, Y => N_560); - - \r.address_RNI96NJ_3[0]\ : OR2A - port map(A => N_117, B => \brmw_i\, Y => - \address_RNI96NJ_3[0]\); - - \r.brmw\ : DFN1E0 - port map(D => \brmw_1\, CLK => lclk_c, E => srhsel_0_sqmuxa, - Q => brmw); - - \r.writedata_RNO[9]\ : AO1B - port map(A => hwdata_9, B => \address_RNI96NJ_3[0]\, C => - N_152, Y => \writedata[9]\); - - \r.wrn[1]\ : DFN1 - port map(D => \wrn_RNO[1]\, CLK => lclk_c, Q => \rwen_c[1]\); - - \r.writedata_RNO_3[30]\ : AO1B - port map(A => \writedata_1_iv_0[30]\, B => \hwdata_m[30]\, - C => N_123_i, Y => \writedata_m[30]\); - - \r.brmw_RNIDHE9\ : NOR2A - port map(A => \address_c[1]\, B => brmw, Y => N_517); - - \r.ready_RNIFGHB1\ : NOR2A - port map(A => ws_1_sqmuxa, B => ws, Y => ready_0_0_a2_0_1); - - \r.hburst[2]\ : DFN1E1 - port map(D => hburst_0(2), CLK => lclk_c, E => un1_ahbsi_1, - Q => \hburst[2]\); - - \r.writedata[19]\ : DFN1E1 - port map(D => \writedata_12[19]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[19]\); - - \r.mcfg2.rambanksz_RNID3CCF2[2]\ : MX2C - port map(A => N_5107, B => N_5108, S => \rambanksz[2]\, Y - => N_5109); - - \r.mcfg1.brdyen_RNIGD9A1\ : NOR2 - port map(A => ws, B => N_413, Y => ready10); - - \r.writen_RNO_0\ : MX2 - port map(A => \writen_c\, B => iosn_0_sqmuxa, S => N_280, Y - => N_5425); - - \r.read_RNIU1JTC4\ : MX2 - port map(A => hwrite_m_0_0, B => \read_c\, S => - srhsel_0_sqmuxa, Y => read_8_iv_0_tz); - - \r.mcfg1.romrws[2]\ : DFN1 - port map(D => \romrws_RNO[2]\, CLK => lclk_c, Q => - \romrws[2]\); - - \r.bdrive[3]\ : DFN1P0 - port map(D => N_292, CLK => lclk_c, PRE => rstn, Q => - \bdrive[3]\); - - \r.writedata_RNO[26]\ : OR3C - port map(A => \writedata_m[26]\, B => \writedata_m_0[18]\, - C => \writedata_12_iv_0[26]\, Y => \writedata_12[26]\); - - \r.address_RNI96NJ_5[0]\ : OR2A - port map(A => N_425, B => \brmw_i\, Y => - \address_RNI96NJ_5[0]\); - - \r.busw_RNO_1[1]\ : OR2A - port map(A => \ramwidth[1]\, B => iosn_99, Y => - \ramwidth_m[1]\); - - \r.address[5]\ : DFN1E1 - port map(D => haddr(5), CLK => lclk_c, E => N_36, Q => - address_c(5)); - - \r.writedata_RNO_1[22]\ : NOR2B - port map(A => N_6564, B => N_396, Y => N_630); - - \r.mcfg2.ramwws[1]\ : DFN1 - port map(D => N_563, CLK => lclk_c, Q => \ramwws[1]\); - - \r.mcfg2.ramrws_RNO_0[1]\ : MX2 - port map(A => \ramrws[1]\, B => pwdata_1_0, S => - rmw_1_sqmuxa, Y => N_5520); - - \r.ws_RNO_4[0]\ : OR3A - port map(A => \ramwws[0]\, B => N_6458, C => rws_0_sqmuxa, - Y => \ramwws_m[0]\); - - \r.data_RNIM9AT2[1]\ : MX2 - port map(A => hwdata_1, B => \hrdata[1]\, S => N_671, Y => - \writedata[1]\); - - \r.ready_RNIH80F\ : NOR2A - port map(A => \bstate[5]\, B => \hready\, Y => ws_1_sqmuxa); - - \r.ramsn_RNO[3]\ : OR2 - port map(A => srhsel_0_sqmuxa, B => \ramsn_1[3]\, Y => - \ramsn_1_0[3]\); - - \r.data[16]\ : DFN1 - port map(D => data_in(16), CLK => lclk_c, Q => \hrdata[16]\); - - \v.mcfg2.rmw_1_sqmuxa_0_a2\ : NOR2 - port map(A => psel(0), B => N_6459, Y => rmw_1_sqmuxa); - - \r.writedata[11]\ : DFN1E1 - port map(D => \writedata[11]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => data(11)); - - \r.wrn_RNO_2[0]\ : MX2 - port map(A => \address_c[1]\, B => \rwen_c[0]\, S => N_6549, - Y => N_5200); - - \r.mcfg1.romwrite\ : DFN1 - port map(D => romwrite_RNO, CLK => lclk_c, Q => romwrite); - - \v.mcfg1.bexcen_0_sqmuxa_0_a2\ : NOR3A - port map(A => bexcen_0_sqmuxa_0_a2_0, B => psel(0), C => - N_232_0, Y => bexcen_0_sqmuxa); - - \r.area[1]\ : DFN1E0 - port map(D => iosn_1_8, CLK => lclk_c, E => srhsel_0_sqmuxa, - Q => \area[1]\); - - \r.busw_RNO_2[1]\ : OR3C - port map(A => iosn_99, B => \romwidth[1]\, C => iosn_100, Y - => \romwidth_m[1]\); - - GND_i_0 : GND - port map(Y => GND_0); - - \r.address_RNIN3DG_0[1]\ : NOR2A - port map(A => \address_c[1]\, B => \brmw_i\, Y => - N_6555_i_0); - - \r.ramsn[3]\ : DFN1E0P0 - port map(D => \ramsn_1_0[3]\, CLK => lclk_c, PRE => rstn, E - => romsn_0_sqmuxa_1, Q => \ramsn_c[3]\); - - \r.romsn_RNO[0]\ : OR3 - port map(A => hmbsel(0), B => - \un1_romsn_0_sqmuxa_1_0[0]_net_1\, C => haddr(28), Y => - \romsn_1[0]\); - - \r.mcfg1.romwidth[0]\ : DFN1E0 - port map(D => N_6539, CLK => lclk_c, E => N_560, Q => - \romwidth[0]\); - - \r.wrn[3]\ : DFN1 - port map(D => \wrn_RNO[3]\, CLK => lclk_c, Q => \rwen_c[3]\); - - \r.mcfg1.romwws[0]\ : DFN1 - port map(D => \romwws_RNO[0]\, CLK => lclk_c, Q => - \romwws[0]\); - - \r.data_RNI5HC72[20]\ : OR2B - port map(A => \writedata_4_m_0[20]\, B => \writedata_4[20]\, - Y => \writedata_4_m[20]\); - - \r.writedata_RNO_6[26]\ : OR2A - port map(A => \writedata[10]\, B => N_440, Y => - \writedata_m[10]\); - - \r.bstate_RNO[6]\ : NOR2A - port map(A => N_6565, B => N_446, Y => \bstate_RNO[6]\); - - \r.writedata_RNO_5[28]\ : OR2B - port map(A => hwdata_28, B => \address_RNI96NJ_5[0]\, Y => - \hwdata_m[28]\); - - \r.writedata_RNO_0[28]\ : AOI1B - port map(A => \writedata[4]\, B => N_46_i_0, C => - \writedata_m[28]\, Y => \writedata_12_iv_0[28]\); - - \r.mcfg1.romwrite_RNIGG9C\ : MX2 - port map(A => romwrite, B => \rambanksz[2]\, S => - paddr_2(2), Y => N_5070); - - \r.data_RNIOMNK[10]\ : OR2A - port map(A => \hrdata[10]\, B => \address_RNI96NJ_3[0]\, Y - => N_112); - - \r.bdrive[0]\ : DFN1P0 - port map(D => N_286, CLK => lclk_c, PRE => rstn, Q => - \bdrive[0]\); - - \r.oen_RNO_0\ : OA1C - port map(A => iosn_1_8, B => un18_srhsel, C => bstate16, Y - => bstate16_1); - - \r.data[24]\ : DFN1 - port map(D => data_in(24), CLK => lclk_c, Q => \hrdata[24]\); - - \r.mcfg1.romrws_RNO_0[3]\ : MX2 - port map(A => \romrws[3]\, B => pwdata_1_2, S => - bexcen_0_sqmuxa, Y => N_5508); - - \r.ws[0]\ : DFN1 - port map(D => \ws_RNO[0]\, CLK => lclk_c, Q => \ws[0]\); - - \r.bstate_RNI3PAI2[4]\ : OR2 - port map(A => \A_i[0]\, B => N_442, Y => bstate_3); - - \r.writedata_RNO_2[16]\ : OR2A - port map(A => \writedata[0]\, B => N_440, Y => N_531); - - \r.mcfg1.ioen\ : DFN1 - port map(D => ioen_RNO, CLK => lclk_c, Q => \ioen\); - - \r.bstate_RNI2VCTKA[6]\ : NOR3A - port map(A => un1_iosn, B => bstate_4, C => oen_1_sqmuxa, Y - => ramoen_0_sqmuxa_1); - - \r.data[30]\ : DFN1 - port map(D => data_in(30), CLK => lclk_c, Q => \hrdata[30]\); - - \r.read_RNICG8E\ : OR2A - port map(A => \bstate[7]\, B => \read_c\, Y => N_6458); - - \r.writedata[5]\ : DFN1E1 - port map(D => \writedata[5]\, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(5)); - - \r.data_RNI0U404[3]\ : OR2B - port map(A => N_507, B => N_506, Y => \writedata[3]\); - - \r.data[0]\ : DFN1 - port map(D => data_in(0), CLK => lclk_c, Q => \hrdata[0]\); - - \r.wrn_RNO_3[2]\ : OR3A - port map(A => N_394, B => wrn35, C => wrn_4_sqmuxa_s5_0_0, - Y => wrn_4_sqmuxa_s5_0_1); - - \r.wrn_RNO_3[1]\ : OR3A - port map(A => N_394, B => wrn35, C => wrn_3_sqmuxa_s4_0_0, - Y => wrn_3_sqmuxa_s4_0_1); - - \r.writedata_RNO_2[28]\ : OR2B - port map(A => \writedata[20]\, B => writedata_1_sqmuxa, Y - => \writedata_m_0[20]\); - - \r.writedata[2]\ : DFN1E1 - port map(D => N_45, CLK => lclk_c, E => writedata_0_sqmuxa, - Q => data(2)); - - \r.writedata[24]\ : DFN1E1 - port map(D => N_82_i_0, CLK => lclk_c, E => - writedata_0_sqmuxa, Q => data(24)); - - \r.address_RNIN3DG[1]\ : OR2 - port map(A => \brmw_i\, B => \address_c[1]\, Y => N_5112); - - \r.hwrite_RNI420DN6\ : MX2B - port map(A => hwrite_0, B => read_8_iv_0_tz, S => - iosn_0_sqmuxa_1, Y => un18_srhsel); - - \r.mcfg2.rambanksz_RNI5JCIU9[0]\ : MX2C - port map(A => N_5103, B => N_5110, S => \rambanksz[0]\, Y - => \adec_2[1]\); - - \apbo.prdata[20]\ : NOR2A - port map(A => \iows[0]\, B => N_232_0, Y => prdata_0); - - \r.bstate_RNO[5]\ : NOR3 - port map(A => N_616, B => N_617, C => N_446, Y => N_295); - - \r.bdrive_RNIVBR7[3]\ : INV - port map(A => \bdrive[3]\, Y => bdrive_i(3)); - - \r.data[5]\ : DFN1 - port map(D => data_in(5), CLK => lclk_c, Q => \hrdata[5]\); - - \r.bstate_RNI8O4Q1[6]\ : OR2A - port map(A => N_610, B => \bstate[6]\, Y => N_419); - - \r.bstate_RNIB9DGA2[5]\ : AO1C - port map(A => brmw, B => bstate_0_sqmuxa, C => \bstate[5]\, - Y => romsn_1_sqmuxa); - - \r.address[1]\ : DFN1E1 - port map(D => haddr(1), CLK => lclk_c, E => N_36_0, Q => - \address_c[1]\); - - \ctrl.v.bstate16\ : OR2A - port map(A => htrans(1), B => hsel_i(0), Y => bstate16); - - \r.data[13]\ : DFN1 - port map(D => data_in(13), CLK => lclk_c, Q => \hrdata[13]\); - - \r.writedata_RNO_0[23]\ : AOI1B - port map(A => \writedata[23]\, B => N_123_i, C => - \data_m[23]\, Y => \writedata_12_0_iv_0[23]\); - - \r.ws_RNO_0[1]\ : NOR3C - port map(A => \ws_3_iv_1[1]\, B => \ramrws_m[1]\, C => - \iows_m[1]\, Y => \ws_3_iv_3[1]\); - - \r.mcfg1.brdyen\ : DFN1 - port map(D => brdyen_RNO, CLK => lclk_c, Q => \brdyen\); - - un1_wsnew_0_sqmuxa_RNI8N8F : OA1 - port map(A => \bstate[7]\, B => \un1_wsnew_0_sqmuxa\, C => - \area[1]\, Y => un1_rws_0_sqmuxa); - - \r.writedata[17]\ : DFN1E1 - port map(D => \writedata_12[17]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[17]\); - - \v.ws_0_sqmuxa\ : NAND2 - port map(A => \hready\, B => \bstate[5]\, Y => ws_0_sqmuxa); - - \r.ramsn_RNO[2]\ : OR2 - port map(A => srhsel_0_sqmuxa, B => \ramsn_1[2]\, Y => - \ramsn_1_0[2]\); - - \r.ws_RNO_0[3]\ : OR3C - port map(A => rstn, B => un1_rws_0_sqmuxa, C => \iows[3]\, - Y => N_6448); - - \r.data[18]\ : DFN1 - port map(D => data_in(18), CLK => lclk_c, Q => \hrdata[18]\); - - \r.writedata[20]\ : DFN1E1 - port map(D => \writedata_12[20]\, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[20]\); - - \r.size_RNILTQM[0]\ : NOR3B - port map(A => \size[0]\, B => \busw[1]\, C => \size[1]\, Y - => wrn_6_sqmuxa_0_i_1); - - \ctrl.un1_ahbsi_1\ : NOR2A - port map(A => iosn_1_0, B => hsel_i(0), Y => un1_ahbsi_1); - - \r.mcfg1.romrws[3]\ : DFN1 - port map(D => \romrws_RNO[3]\, CLK => lclk_c, Q => - \romrws[3]\); - - \r.bstate_RNO_0[4]\ : NOR2A - port map(A => iosn_1_sqmuxa, B => \bstate[4]\, Y => N_619); - - \r.ws_RNO_2[3]\ : AOI1B - port map(A => \ws_0_0_a2_0[3]\, B => rstn, C => N_6449, Y - => \ws_0_0_0[3]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \r.area_RNIG8VG82[1]\ : NOR3B - port map(A => ramoen10_i_a2_1, B => htrans(1), C => - hsel_i(0), Y => N_195); - - \r.wrn_RNO[0]\ : OR3C - port map(A => ramoen_0_sqmuxa, B => \wrn_90[0]\, C => rstn, - Y => \wrn_RNO[0]\); - - \r.writedata_RNO_2[17]\ : OA1A - port map(A => hwdata_1, B => N_440, C => N_514, Y => - \writedata_12_0_iv_0_0[17]\); - - \r.data[29]\ : DFN1 - port map(D => data_in(29), CLK => lclk_c, Q => \hrdata[29]\); - - \r.address_RNI59K6_0[0]\ : OR2A - port map(A => \address_c[1]\, B => \address_c[0]\, Y => - N_117); - - \r.mcfg1.iows_RNO_0[1]\ : MX2 - port map(A => \iows[1]\, B => pwdata_16, S => - bexcen_0_sqmuxa, Y => N_5510); - - \r.ws[3]\ : DFN1 - port map(D => \ws_RNO[3]\, CLK => lclk_c, Q => \ws[3]\); - - \r.mcfg1.brdyen_RNO_0\ : MX2 - port map(A => \brdyen\, B => pwdata_21, S => - bexcen_0_sqmuxa, Y => N_5527); - - \r.address[8]\ : DFN1E1 - port map(D => haddr(8), CLK => lclk_c, E => N_36, Q => - address_c(8)); - - \un1_v.ws_1_sqmuxa_2_ADD_4x4_fast_I8_Y_0_a2_0\ : NOR2A - port map(A => \ws[2]\, B => \A_i[0]\, Y => N_14); - - \r.address[3]\ : DFN1E1 - port map(D => haddr(3), CLK => lclk_c, E => N_36, Q => - address_c(3)); - - \r.ws_RNO_1[3]\ : OR3B - port map(A => \romwws[3]\, B => N_6457, C => N_6458, Y => - N_6450); - - \r.bdrive_RNO[2]\ : OA1C - port map(A => N_6568_i_0, B => \bdrive[2]\, C => N_6567_i_0, - Y => N_290); - - \r.ws_RNO[0]\ : AOI1B - port map(A => \ws_3_iv_3[0]\, B => \ws_1_sqmuxa_2_m[3]\, C - => rstn, Y => \ws_RNO[0]\); - - \r.address_RNIODHK[1]\ : NOR2A - port map(A => \address_c[1]\, B => N_5160, Y => N_46_i_0); - - \r.writedata_RNO[2]\ : NOR3 - port map(A => N_149, B => \writedata_1_iv_i_0[2]\, C => - N_148, Y => N_45); - - \r.writedata_RNO_4[31]\ : OAI1 - port map(A => N_6555_i_0, B => N_38_i, C => \hrdata[31]\, Y - => \writedata_1_iv_0[31]\); - - \r.bstate_RNIQ5FJ1[4]\ : OR2A - port map(A => N_442, B => ws, Y => N_500); - - \r.writedata_RNO_1[31]\ : AOI1B - port map(A => \writedata[31]\, B => N_123_i, C => - \writedata_m_0[23]\, Y => \writedata_12_iv_0[31]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.address_RNIGKGM[0]\ : NOR2 - port map(A => N_394, B => N_117, Y => N_649); - - \r.address_RNIODHK_0[1]\ : NOR2 - port map(A => \address_c[1]\, B => N_5160, Y => - writedata_1_sqmuxa); - - \r.writedata_RNO[27]\ : OR3C - port map(A => \writedata_12_iv_0_1[27]\, B => N_183, C => - N_184, Y => \writedata_12[27]\); - - \r.data_RNIQ5AH1[3]\ : OR2B - port map(A => \hrdata[3]\, B => N_671, Y => N_507); - - \r.mcfg1.iows[1]\ : DFN1 - port map(D => N_565, CLK => lclk_c, Q => \iows[1]\); - - \r.ws_RNO_2[1]\ : OR3B - port map(A => \un1_wsnew_0_sqmuxa\, B => \ramrws[1]\, C => - rws_0_sqmuxa, Y => \ramrws_m[1]\); - - \r.writedata_RNO_2[19]\ : OR2A - port map(A => \writedata[3]\, B => N_440, Y => - \writedata_m[3]\); - - \r.writedata_RNO[24]\ : OA1A - port map(A => N_46_i_0, B => \writedata[0]\, C => - \writedata_12_iv_i_2[24]\, Y => N_82_i_0); - - \v.srhsel_0_sqmuxa\ : OR2B - port map(A => un1_ahbsi_1, B => htrans(1), Y => - srhsel_0_sqmuxa); - - \r.busw_RNIJ4TD[0]\ : OR2A - port map(A => \busw[0]\, B => \busw[1]\, Y => - \writedata_12_0_iv_i_a2_4_0[18]\); - - \r.data[6]\ : DFN1 - port map(D => data_in(6), CLK => lclk_c, Q => \hrdata[6]\); - - \r.mcfg2.rambanksz_RNIQOSI71[3]\ : MX2 - port map(A => haddr(16), B => haddr(24), S => - \rambanksz[3]\, Y => N_5100); - - \r.mcfg1.romrws_RNO_0[2]\ : MX2 - port map(A => \romrws[2]\, B => pwdata_0_2, S => - bexcen_0_sqmuxa, Y => N_5507); - - \r.data[12]\ : DFN1 - port map(D => data_in(12), CLK => lclk_c, Q => \hrdata[12]\); - - \r.data[10]\ : DFN1 - port map(D => data_in(10), CLK => lclk_c, Q => \hrdata[10]\); - - \r.bstate_RNO[4]\ : NOR3 - port map(A => N_619, B => N_618, C => N_446, Y => N_297); - - \r.bstate_RNIUJ6IA2[6]\ : OR2A - port map(A => iosn_0_sqmuxa_1, B => \bstate[6]\, Y => - bstate_4); - - \r.brmw_RNIN9ELJ1\ : NOR3C - port map(A => ready_0_0_a2_0_1, B => ready_0_0_a2_0_0, C - => ramoen_0_sqmuxa, Y => N_661); - - \r.writedata_RNO_4[30]\ : OAI1 - port map(A => N_6555_i_0, B => N_38_i, C => \hrdata[30]\, Y - => \writedata_1_iv_0[30]\); - - \r.writedata_RNO_1[2]\ : AO1D - port map(A => \writedata_1_iv_i_a2_2_0[2]\, B => \brmw_i\, - C => N_150, Y => \writedata_1_iv_i_0[2]\); - - \r.wrn_RNO_4[1]\ : OR2 - port map(A => wrn8, B => N_6547, Y => wrn_3_sqmuxa_s4_0_0); - - \r.bstate_RNI755AD2[4]\ : OR2B - port map(A => iosn_1_sqmuxa_1, B => iosn_1_sqmuxa_1_0, Y - => iosn_1_sqmuxa); - - \r.address[24]\ : DFN1E1 - port map(D => haddr(24), CLK => lclk_c, E => N_36, Q => - address_c(24)); - - \r.writedata_RNO_1[30]\ : AOI1B - port map(A => \writedata[6]\, B => N_46_i_0, C => - \writedata_m[30]\, Y => \writedata_12_iv_0[30]\); - - \r.iosn[1]\ : DFN1P0 - port map(D => \iosn_1_iv[1]\, CLK => lclk_c, PRE => rstn, Q - => \iosn[1]\); - - \r.hburst[0]\ : DFN1E1 - port map(D => hburst_0(0), CLK => lclk_c, E => un1_ahbsi_1, - Q => \hburst[0]\); - - \r.address_RNI9S2B1[0]\ : OR2B - port map(A => N_425, B => N_106, Y => N_111); - - \r.wrn_RNO_2[1]\ : MX2 - port map(A => \address_c[1]\, B => \rwen_c[1]\, S => N_6549, - Y => N_5201); - - \r.bstate_RNIGNR772[6]\ : MX2A - port map(A => hsel_i(0), B => N_419, S => ramoen_0_sqmuxa, - Y => ready_0_0_o2_0); - - \r.mcfg2.rambanksz_RNIHKCBF2[2]\ : MX2C - port map(A => N_5097, B => N_5098, S => \rambanksz[2]\, Y - => N_5091); - - \r.writedata_RNO_0[25]\ : NOR3C - port map(A => \writedata_12_iv_0_0[25]\, B => N_186, C => - N_188, Y => \writedata_12_iv_0_2[25]\); - - \r.area_RNI4DTB1_0[0]\ : OR2B - port map(A => hresp2_i_0, B => N_431, Y => N_438); - - \r.mcfg2.ramwws_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5518, Y => N_563); - - \r.writedata[22]\ : DFN1E1 - port map(D => N_308, CLK => lclk_c, E => - writedata_0_sqmuxa_0, Q => \data[22]\); - - \r.wrn_RNO_4[2]\ : OR2 - port map(A => N_117, B => N_6547, Y => wrn_4_sqmuxa_s5_0_0); - - \r.bstate_RNI8E2SK1_0[6]\ : NOR3A - port map(A => ramoen_0_sqmuxa, B => N_419, C => N_6565, Y - => N_6568_i_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity grgpio is - - port( un1_grgpio0_7 : out std_logic; - un1_grgpio0_5 : out std_logic; - gpio_in : in std_logic_vector(7 downto 0); - pwdata_i : in std_logic_vector(7 downto 0); - paddr : in std_logic_vector(5 downto 2); - readdata_2_m : out std_logic_vector(5 to 5); - pwdata_1_0 : in std_logic; - pwdata_1_3 : in std_logic; - pwdata_1_2 : in std_logic; - pwdata_0_5 : in std_logic; - pwdata_0_7 : in std_logic; - pwdata_0_6 : in std_logic; - pwdata_0_2 : in std_logic; - pwdata_0_0 : in std_logic; - dout : out std_logic_vector(7 downto 0); - psel : in std_logic_vector(11 to 11); - prdata_iv_0_0_d0 : out std_logic; - prdata_iv_0_2 : out std_logic; - prdata_iv_0_0 : out std_logic_vector(2 to 2); - oen_7 : out std_logic; - oen_i : out std_logic_vector(7 downto 0); - paddr_0 : in std_logic_vector(3 downto 2); - lclk_c : in std_logic; - N_232_2 : out std_logic; - rdata61_2 : out std_logic; - N_6432 : out std_logic; - rstn : in std_logic; - N_6439 : out std_logic; - N_6437 : out std_logic; - N_6436 : out std_logic; - N_6435 : out std_logic; - N_6434 : out std_logic; - rdata60_4 : in std_logic; - N_6430 : out std_logic; - rdata59_4 : in std_logic; - N_6429 : out std_logic; - N_6428 : out std_logic; - N_6459 : out std_logic; - readdata55_3 : in std_logic; - un1_apbi_0 : in std_logic; - rdata60_4_0 : in std_logic; - N_232_0 : out std_logic; - N_232_1 : out std_logic - ); - -end grgpio; - -architecture DEF_ARCH of grgpio is - - component DFN1E1P0 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - PRE : in std_logic := 'U'; - E : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component NOR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2A - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component NOR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component MX2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - S : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component OA1 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component OR2 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component NOR3 - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - C : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal \oen[4]\, \oen[5]\, \oen[6]\, \oen[0]\, \oen[1]\, - \oen[2]\, \oen[3]\, N_6431, \un1_grgpio0_m[67]\, - \un1_grgpio0_m[65]\, dir_1_sqmuxa, N_5412, dout_1_sqmuxa, - N_5414, N_5415, N_5416, N_5418, N_5419, \un1_grgpio0[65]\, - \un1_grgpio0[64]\, \dout[0]\, \un1_grgpio0[68]\, - \dout[4]\, \un1_grgpio0[70]\, \N_6459\, N_87, N_90, N_224, - N_228, N_230, N_232, \dout[2]\, \un1_grgpio0[66]\, - \un1_grgpio0[67]\, N_234, N_5417, N_226, N_5413, - \dout[1]\, \dout[3]\, \dout[5]\, \dout[6]\, \dout[7]\, - \oen[7]\, \din1[0]\, \din1[1]\, \din1[2]\, \din1[3]\, - \din1[4]\, \din1[5]\, \din1[6]\, \din1[7]\, \GND\, \VCC\, - GND_0, VCC_0 : std_logic; - -begin - - dout(7) <= \dout[7]\; - dout(6) <= \dout[6]\; - dout(5) <= \dout[5]\; - dout(4) <= \dout[4]\; - dout(3) <= \dout[3]\; - dout(2) <= \dout[2]\; - dout(1) <= \dout[1]\; - dout(0) <= \dout[0]\; - oen_7 <= \oen[7]\; - N_6459 <= \N_6459\; - - \r.dir[3]\ : DFN1E1P0 - port map(D => pwdata_i(3), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[3]\); - - \r.din2[3]\ : DFN1 - port map(D => \din1[3]\, CLK => lclk_c, Q => - \un1_grgpio0[67]\); - - \r.dout_RNO[5]\ : NOR2B - port map(A => rstn, B => N_5417, Y => N_234); - - \r.din2_RNICS37[6]\ : OR2A - port map(A => \un1_grgpio0[70]\, B => readdata55_3, Y => - N_6437); - - \r.dout_RNIHH6A[2]\ : OR2B - port map(A => rdata59_4, B => \dout[2]\, Y => N_6432); - - \v.dout_1_sqmuxa_0_a2\ : NOR2 - port map(A => psel(11), B => \N_6459\, Y => dout_1_sqmuxa); - - \r.dout_RNO_0[6]\ : MX2 - port map(A => \dout[6]\, B => pwdata_0_6, S => - dout_1_sqmuxa, Y => N_5418); - - \r.din2_RNI6S37[0]\ : OR2A - port map(A => \un1_grgpio0[64]\, B => readdata55_3, Y => - N_6428); - - \r.dir_RNICB4G[2]\ : OA1 - port map(A => \oen[2]\, B => rdata60_4_0, C => N_6431, Y - => prdata_iv_0_0(2)); - - \r.dir_RNIIA8[6]\ : INV - port map(A => \oen[6]\, Y => oen_i(6)); - - \r.dir[6]\ : DFN1E1P0 - port map(D => pwdata_i(6), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[6]\); - - \r.dir[5]\ : DFN1E1P0 - port map(D => pwdata_i(5), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[5]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \r.dout[4]\ : DFN1 - port map(D => N_232, CLK => lclk_c, Q => \dout[4]\); - - \r.dout_RNO[7]\ : NOR2B - port map(A => rstn, B => N_5419, Y => N_90); - - \r.dout_RNO[6]\ : NOR2B - port map(A => rstn, B => N_5418, Y => N_87); - - \r.dout_RNO[1]\ : NOR2B - port map(A => rstn, B => N_5413, Y => N_226); - - \r.dout[0]\ : DFN1 - port map(D => N_224, CLK => lclk_c, Q => \dout[0]\); - - \r.dir_RNIJE8[7]\ : INV - port map(A => \oen[7]\, Y => oen_i(7)); - - \r.din2[7]\ : DFN1 - port map(D => \din1[7]\, CLK => lclk_c, Q => un1_grgpio0_7); - - \r.din1[0]\ : DFN1 - port map(D => gpio_in(0), CLK => lclk_c, Q => \din1[0]\); - - \r.dir_RNI7R09[5]\ : OR2 - port map(A => rdata60_4, B => \oen[5]\, Y => - readdata_2_m(5)); - - \r.din2[2]\ : DFN1 - port map(D => \din1[2]\, CLK => lclk_c, Q => - \un1_grgpio0[66]\); - - \r.dout[7]\ : DFN1 - port map(D => N_90, CLK => lclk_c, Q => \dout[7]\); - - \r.dir[4]\ : DFN1E1P0 - port map(D => pwdata_i(4), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[4]\); - - \r.din2[0]\ : DFN1 - port map(D => \din1[0]\, CLK => lclk_c, Q => - \un1_grgpio0[64]\); - - \r.dout[5]\ : DFN1 - port map(D => N_234, CLK => lclk_c, Q => \dout[5]\); - - \r.dir[0]\ : DFN1E1P0 - port map(D => pwdata_i(0), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[0]\); - - \r.dout_RNO_0[5]\ : MX2 - port map(A => \dout[5]\, B => pwdata_0_5, S => - dout_1_sqmuxa, Y => N_5417); - - \r.dout_RNO[3]\ : NOR2B - port map(A => rstn, B => N_5415, Y => N_230); - - \r.dout_RNO[0]\ : NOR2B - port map(A => rstn, B => N_5412, Y => N_224); - - \r.dir[7]\ : DFN1E1P0 - port map(D => pwdata_i(7), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[7]\); - - \r.dout_RNO_0[1]\ : MX2 - port map(A => \dout[1]\, B => pwdata_1_0, S => - dout_1_sqmuxa, Y => N_5413); - - \r.din1[7]\ : DFN1 - port map(D => gpio_in(7), CLK => lclk_c, Q => \din1[7]\); - - \r.dir_RNI2709[0]\ : OR2 - port map(A => rdata60_4, B => \oen[0]\, Y => N_6430); - - \r.dir_RNICI7[0]\ : INV - port map(A => \oen[0]\, Y => oen_i(0)); - - \comb.readdata16_0_a2_0\ : OR2 - port map(A => paddr(5), B => paddr(4), Y => rdata61_2); - - \r.dout_RNO[4]\ : NOR2B - port map(A => rstn, B => N_5416, Y => N_232); - - \r.dir[2]\ : DFN1E1P0 - port map(D => pwdata_i(2), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[2]\); - - \r.dout[3]\ : DFN1 - port map(D => N_230, CLK => lclk_c, Q => \dout[3]\); - - GND_i : GND - port map(Y => \GND\); - - \r.dir_RNIDM7[1]\ : INV - port map(A => \oen[1]\, Y => oen_i(1)); - - \r.din1[4]\ : DFN1 - port map(D => gpio_in(4), CLK => lclk_c, Q => \din1[4]\); - - \r.dout_RNO_0[0]\ : MX2 - port map(A => \dout[0]\, B => pwdata_0_0, S => - dout_1_sqmuxa, Y => N_5412); - - \r.dout[1]\ : DFN1 - port map(D => N_226, CLK => lclk_c, Q => \dout[1]\); - - \r.dir_RNIEF4G[3]\ : OA1 - port map(A => \oen[3]\, B => rdata60_4_0, C => - \un1_grgpio0_m[67]\, Y => prdata_iv_0_2); - - \r.dir_RNI8V09[6]\ : OR2 - port map(A => rdata60_4, B => \oen[6]\, Y => N_6439); - - \r.dir[1]\ : DFN1E1P0 - port map(D => pwdata_i(1), CLK => lclk_c, PRE => rstn, E - => dir_1_sqmuxa, Q => \oen[1]\); - - \r.din2_RNI8S37[2]\ : OR2A - port map(A => \un1_grgpio0[66]\, B => readdata55_3, Y => - N_6431); - - \comb.readdata15_1_0\ : OR2 - port map(A => paddr_0(3), B => paddr_0(2), Y => N_232_0); - - \r.din2_RNI7S37[1]\ : OR2A - port map(A => \un1_grgpio0[65]\, B => readdata55_3, Y => - \un1_grgpio0_m[65]\); - - \r.din1[2]\ : DFN1 - port map(D => gpio_in(2), CLK => lclk_c, Q => \din1[2]\); - - \r.din2_RNI9S37[3]\ : OR2A - port map(A => \un1_grgpio0[67]\, B => readdata55_3, Y => - \un1_grgpio0_m[67]\); - - \r.din2[4]\ : DFN1 - port map(D => \din1[4]\, CLK => lclk_c, Q => - \un1_grgpio0[68]\); - - \r.dir_RNIEQ7[2]\ : INV - port map(A => \oen[2]\, Y => oen_i(2)); - - \r.din1[1]\ : DFN1 - port map(D => gpio_in(1), CLK => lclk_c, Q => \din1[1]\); - - \r.din1[3]\ : DFN1 - port map(D => gpio_in(3), CLK => lclk_c, Q => \din1[3]\); - - \r.dout_RNO_0[7]\ : MX2 - port map(A => \dout[7]\, B => pwdata_0_7, S => - dout_1_sqmuxa, Y => N_5419); - - \r.dout_RNIFH6A[0]\ : OR2B - port map(A => rdata59_4, B => \dout[0]\, Y => N_6429); - - \r.dout_RNO_0[2]\ : MX2 - port map(A => \dout[2]\, B => pwdata_0_2, S => - dout_1_sqmuxa, Y => N_5414); - - \r.dir_RNIA74G[1]\ : OA1 - port map(A => \oen[1]\, B => rdata60_4_0, C => - \un1_grgpio0_m[65]\, Y => prdata_iv_0_0_d0); - - \r.dout_RNO[2]\ : NOR2B - port map(A => rstn, B => N_5414, Y => N_228); - - \v.dout_1_sqmuxa_0_a2_0\ : OR2A - port map(A => rdata59_4, B => un1_apbi_0, Y => \N_6459\); - - \r.din2_RNIAS37[4]\ : OR2A - port map(A => \un1_grgpio0[68]\, B => readdata55_3, Y => - N_6434); - - \r.din1[6]\ : DFN1 - port map(D => gpio_in(6), CLK => lclk_c, Q => \din1[6]\); - - \r.dir_RNI6N09[4]\ : OR2 - port map(A => rdata60_4, B => \oen[4]\, Y => N_6436); - - \r.din2[6]\ : DFN1 - port map(D => \din1[6]\, CLK => lclk_c, Q => - \un1_grgpio0[70]\); - - \v.dir_1_sqmuxa_0_a2\ : NOR3 - port map(A => psel(11), B => un1_apbi_0, C => rdata60_4_0, - Y => dir_1_sqmuxa); - - \r.dout[6]\ : DFN1 - port map(D => N_87, CLK => lclk_c, Q => \dout[6]\); - - \r.dir_RNIG28[4]\ : INV - port map(A => \oen[4]\, Y => oen_i(4)); - - \comb.readdata15_1\ : OR2 - port map(A => paddr(3), B => paddr(2), Y => N_232_2); - - \r.din2[5]\ : DFN1 - port map(D => \din1[5]\, CLK => lclk_c, Q => un1_grgpio0_5); - - \r.dout_RNO_0[3]\ : MX2 - port map(A => \dout[3]\, B => pwdata_1_2, S => - dout_1_sqmuxa, Y => N_5415); - - \r.dout[2]\ : DFN1 - port map(D => N_228, CLK => lclk_c, Q => \dout[2]\); - - \r.dout_RNO_0[4]\ : MX2 - port map(A => \dout[4]\, B => pwdata_1_3, S => - dout_1_sqmuxa, Y => N_5416); - - \r.dout_RNIJH6A[4]\ : OR2B - port map(A => rdata59_4, B => \dout[4]\, Y => N_6435); - - \r.din1[5]\ : DFN1 - port map(D => gpio_in(5), CLK => lclk_c, Q => \din1[5]\); - - \comb.readdata15_1_1\ : OR2 - port map(A => paddr_0(3), B => paddr_0(2), Y => N_232_1); - - \r.dir_RNIH68[5]\ : INV - port map(A => \oen[5]\, Y => oen_i(5)); - - \r.dir_RNIFU7[3]\ : INV - port map(A => \oen[3]\, Y => oen_i(3)); - - \r.din2[1]\ : DFN1 - port map(D => \din1[1]\, CLK => lclk_c, Q => - \un1_grgpio0[65]\); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - GND_i_0 : GND - port map(Y => GND_0); - - -end DEF_ARCH; - -library ieee; -use ieee.std_logic_1164.all; -library proasic3e; -use proasic3e.all; - -entity leon3mp_wfp is - - port( resetn : in std_logic; - clk : in std_logic; - pllref : in std_logic; - errorn : out std_logic; - address : out std_logic_vector(27 downto 0); - data : inout std_logic_vector(31 downto 0) := (others => 'Z'); - dsutx : out std_logic; - dsurx : in std_logic; - dsuen : in std_logic; - dsubre : in std_logic; - dsuact : out std_logic; - txd1 : out std_logic; - rxd1 : in std_logic; - txd2 : out std_logic; - rxd2 : in std_logic; - ramsn : out std_logic_vector(4 downto 0); - ramoen : out std_logic_vector(4 downto 0); - rwen : out std_logic_vector(3 downto 0); - oen : out std_logic; - writen : out std_logic; - read : out std_logic; - iosn : out std_logic; - romsn : out std_logic_vector(1 downto 0); - gpio : inout std_logic_vector(7 downto 0) := (others => 'Z'); - emddis : out std_logic; - epwrdwn : out std_logic; - ereset : out std_logic; - esleep : out std_logic; - epause : out std_logic; - pci_rst : out std_logic; - pci_clk : in std_logic; - pci_gnt : in std_logic; - pci_idsel : in std_logic; - pci_lock : out std_logic; - pci_ad : out std_logic_vector(31 downto 0); - pci_cbe : out std_logic_vector(3 downto 0); - pci_frame : out std_logic; - pci_irdy : out std_logic; - pci_trdy : out std_logic; - pci_devsel : out std_logic; - pci_stop : out std_logic; - pci_perr : out std_logic; - pci_par : out std_logic; - pci_req : out std_logic; - pci_serr : out std_logic; - pci_host : in std_logic; - pci_66 : in std_logic; - pci_arb_req : in std_logic_vector(0 to 3); - pci_arb_gnt : out std_logic_vector(0 to 3); - spw_clk : in std_logic; - spw_rxd : in std_logic_vector(0 to 2); - spw_rxdn : in std_logic_vector(0 to 2); - spw_rxs : in std_logic_vector(0 to 2); - spw_rxsn : in std_logic_vector(0 to 2); - spw_txd : out std_logic_vector(0 to 2); - spw_txdn : out std_logic_vector(0 to 2); - spw_txs : out std_logic_vector(0 to 2); - spw_txsn : out std_logic_vector(0 to 2); - ramclk : out std_logic; - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; - tck : in std_logic; - tms : in std_logic; - tdi : in std_logic; - tdo : out std_logic; - clk49_152MHz : in std_logic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic - ); - -end leon3mp_wfp; - -architecture DEF_ARCH of leon3mp_wfp is - - component OUTBUF - port( D : in std_logic := 'U'; - PAD : out std_logic - ); - end component; - - component BIBUF - port( PAD : inout std_logic; - D : in std_logic := 'U'; - E : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component gptimer - port( scaler_4 : out std_logic; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - paddr : in std_logic_vector(6 downto 2) := (others => 'U'); - value_6 : out std_logic; - value_0 : out std_logic; - paddr_2 : in std_logic_vector(2 to 2) := (others => 'U'); - pirq : out std_logic_vector(9 downto 8); - readdata_9_5 : out std_logic; - readdata_9_0 : out std_logic; - readdata_9_27 : out std_logic; - readdata_9_4 : out std_logic; - paddr_1 : in std_logic_vector(2 to 2) := (others => 'U'); - reload_RNIRDRG : out std_logic_vector(1 to 1); - value_RNIBAHH : out std_logic_vector(1 to 1); - reload_RNI6SNI : out std_logic_vector(1 to 1); - scaler_i_m : out std_logic_vector(1 to 1); - reload_m_0_2 : out std_logic; - reload_m_0_3 : out std_logic; - reload_m_0_0 : out std_logic; - scaler_m_5 : out std_logic; - scaler_m_7 : out std_logic; - scaler_m_6 : out std_logic; - scaler_m_0 : out std_logic; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_25 : in std_logic := 'U'; - pwdata_12 : in std_logic := 'U'; - pwdata_24 : in std_logic := 'U'; - pwdata_23 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_19 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_13 : in std_logic := 'U'; - pwdata_11 : in std_logic := 'U'; - pwdata_10 : in std_logic := 'U'; - reload_28 : out std_logic; - reload_12 : out std_logic; - reload_11 : out std_logic; - reload_10 : out std_logic; - reload_8 : out std_logic; - reload_7 : out std_logic; - reload_6 : out std_logic; - reload_5 : out std_logic; - reload_0_7 : out std_logic; - reload_0_6 : out std_logic; - reload_0_4 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - prdata_17 : out std_logic; - prdata_0 : out std_logic; - prdata_2 : out std_logic; - prdata_4 : out std_logic; - prdata_16 : out std_logic; - prdata_3 : out std_logic; - prdata_5 : out std_logic; - prdata_11 : out std_logic; - prdata_15 : out std_logic; - prdata_9 : out std_logic; - readdata_9_i_m : out std_logic_vector(1 to 1); - readdata_1_iv_0_0 : out std_logic; - readdata_1_iv_0_2 : out std_logic; - readdata_1_iv_0_11 : out std_logic; - readdata_1_iv_0_13 : out std_logic; - readdata_1_iv_0_9 : out std_logic; - readdata_iv_3 : out std_logic_vector(3 downto 2); - reload_m_20 : out std_logic; - reload_m_5 : out std_logic; - reload_m_9 : out std_logic; - reload_m_21 : out std_logic; - reload_m_0_d0 : out std_logic; - reload_m_27 : out std_logic; - reload_m_4 : out std_logic; - value_m_1 : out std_logic; - value_m_9 : out std_logic; - value_m_5 : out std_logic; - value_m_23 : out std_logic; - value_m_17 : out std_logic; - value_m_11 : out std_logic; - value_m_3 : out std_logic; - value_m_20 : out std_logic; - value_m_6 : out std_logic; - value_m_4 : out std_logic; - value_m_7 : out std_logic; - value_m_0 : out std_logic; - value_m_24 : out std_logic; - value_m_22 : out std_logic; - value_m_18 : out std_logic; - value_m_8 : out std_logic; - value_m_16 : out std_logic; - paddr_0 : in std_logic_vector(3 downto 2) := (others => 'U'); - N_228 : out std_logic; - readdata51_1 : out std_logic; - N_6455 : in std_logic := 'U'; - chain_m : out std_logic; - rdata60_1 : out std_logic; - rdata60_4 : in std_logic := 'U'; - enable_m : out std_logic; - rdata59_4 : in std_logic := 'U'; - N_217 : out std_logic; - N_229 : out std_logic; - N_215 : out std_logic; - rdata61_2 : in std_logic := 'U'; - readdata55_3 : out std_logic; - N_218 : out std_logic; - N_216 : out std_logic; - N_214 : out std_logic; - irqpen_m : out std_logic; - N_219 : out std_logic; - N_236 : out std_logic; - N_220 : out std_logic; - rstn : in std_logic := 'U'; - restart_RNIIKBB : out std_logic; - N_240 : out std_logic; - readdata55 : out std_logic; - dishlt : out std_logic; - penable : in std_logic := 'U'; - pwrite : in std_logic := 'U'; - N_773 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - readdata57 : out std_logic; - un1_apbi_0 : out std_logic; - N_78 : in std_logic := 'U'; - un1_apbi_7_3 : in std_logic := 'U'; - un1_apbi_2 : out std_logic; - readdata56 : out std_logic; - N_232_0 : in std_logic := 'U'; - N_240_0 : out std_logic; - readdata_1_sqmuxa_1_0 : out std_logic; - N_232 : in std_logic := 'U'; - value_0_sqmuxa_0 : out std_logic; - N_6455_0 : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component INBUF - port( PAD : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component DFN1 - port( D : in std_logic := 'U'; - CLK : in std_logic := 'U'; - Q : out std_logic - ); - end component; - - component ssram_plugin - port( state_RNIFS55 : out std_logic_vector(4 to 4); - ramsn_c : in std_logic_vector(0 to 0) := (others => 'U'); - rwen_c : in std_logic_vector(3 downto 0) := (others => 'U'); - address_c : in std_logic_vector(27 downto 20) := (others => 'U'); - address : in std_logic_vector(31 downto 28) := (others => 'U'); - state_i : out std_logic_vector(3 to 3); - ssram_plugin_GND : in std_logic := 'U'; - clk_c : in std_logic := 'U'; - writen_c : in std_logic := 'U'; - nBWE_c : out std_logic; - nBWd_c : out std_logic; - nBWc_c : out std_logic; - nBWb_c : out std_logic; - nBWa_c : out std_logic; - nCE1_c : out std_logic; - nCE3_c : out std_logic; - CE2_c : out std_logic - ); - end component; - - component INV - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component TRIBUFF - port( D : in std_logic := 'U'; - E : in std_logic := 'U'; - PAD : out std_logic - ); - end component; - - component leon3s - port( irl_0 : in std_logic_vector(3 downto 0) := (others => 'U'); - irl : out std_logic_vector(3 downto 0); - hrdata_1_0_1 : in std_logic_vector(1 to 1) := (others => 'U'); - data_0_21 : out std_logic; - data_0_16 : out std_logic; - data_0_5 : out std_logic; - data_0_2 : out std_logic; - data_0_0 : out std_logic; - nbo_5_0 : out std_logic_vector(1 downto 0); - htrans : out std_logic_vector(1 to 1); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans_tz : out std_logic_vector(1 to 1); - haddr : out std_logic_vector(31 downto 2); - hwdata_16 : out std_logic; - hwdata_3 : out std_logic; - hwdata_9 : out std_logic; - hwdata_11 : out std_logic; - hwdata_25 : out std_logic; - hwdata_27 : out std_logic; - hwdata_13 : out std_logic; - hwdata_4 : out std_logic; - hwdata_12 : out std_logic; - hwdata_23 : out std_logic; - hwdata_28 : out std_logic; - hwdata_1 : out std_logic; - hwdata_14 : out std_logic; - hwdata_0 : out std_logic; - hwdata_15 : out std_logic; - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - hsize_5 : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(0 to 0) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - address : out std_logic_vector(1 downto 0); - size : out std_logic_vector(0 to 0); - data_0_d0 : out std_logic; - data_5 : out std_logic; - data_3 : out std_logic; - data_8 : out std_logic; - data_19 : out std_logic; - data_24 : out std_logic; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_9 : in std_logic := 'U'; - hrdata_10 : in std_logic := 'U'; - hrdata_11 : in std_logic := 'U'; - hrdata_13 : in std_logic := 'U'; - hrdata_14 : in std_logic := 'U'; - hrdata_17 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_8 : in std_logic := 'U'; - hrdata_12 : in std_logic := 'U'; - hrdata_15 : in std_logic := 'U'; - hrdata_16 : in std_logic := 'U'; - hrdata_18 : in std_logic := 'U'; - hrdata_21 : in std_logic := 'U'; - hrdata_22 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_27 : in std_logic := 'U'; - hrdata_2 : in std_logic := 'U'; - hrdata_3 : in std_logic := 'U'; - hrdata_4 : in std_logic := 'U'; - hrdata_7 : in std_logic := 'U'; - hrdata_5 : in std_logic := 'U'; - hrdata_6 : in std_logic := 'U'; - hrdata_28 : in std_logic := 'U'; - hrdata_29 : in std_logic := 'U'; - hrdata_30 : in std_logic := 'U'; - hrdata_31 : in std_logic := 'U'; - error_i_2 : out std_logic; - intack : out std_logic; - N_546 : in std_logic := 'U'; - leon3s_VCC : in std_logic := 'U'; - N_264 : in std_logic := 'U'; - N_262 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - bo_5842_d_0 : out std_logic; - un1_htrans_1_sqmuxa_0 : out std_logic; - hlock : out std_logic; - N_5054 : out std_logic; - lb_0_sqmuxa_1 : out std_logic; - hbusreq : out std_logic; - un60_nbo : out std_logic; - N_457 : out std_logic; - N_462 : out std_logic; - N_467 : out std_logic; - werr_2_m_0 : out std_logic; - un91_nbo_i_0 : out std_logic; - N_138 : out std_logic; - N_139 : out std_logic; - bo_5842_d : out std_logic; - N_458 : out std_logic; - N_459 : out std_logic; - N_461 : out std_logic; - N_463 : out std_logic; - N_468 : out std_logic; - hwrite_1_m_0 : out std_logic; - N_466 : out std_logic; - htrans_0_sqmuxa_2 : out std_logic; - un59_nbo : out std_logic; - N_78_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_264_0 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component irqmp - port( irl_2 : out std_logic_vector(2 to 2); - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - irl_3 : in std_logic := 'U'; - irl_1 : in std_logic := 'U'; - irl_0_d0 : in std_logic := 'U'; - irl_0 : inout std_logic_vector(3 downto 0); - ipend_10 : out std_logic; - pwdata_4 : in std_logic := 'U'; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_23 : in std_logic := 'U'; - pwdata_26 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_25 : in std_logic := 'U'; - pwdata_27 : in std_logic := 'U'; - pwdata_28 : in std_logic := 'U'; - pwdata_29 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_19 : in std_logic := 'U'; - pwdata_24 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - iforce_0_11 : out std_logic; - iforce_0_5 : out std_logic; - iforce_0_9 : out std_logic; - iforce_0_4 : out std_logic; - iforce_0_6 : out std_logic; - ipend_m : out std_logic_vector(4 to 4); - prdata_0 : out std_logic; - prdata_13 : out std_logic; - prdata_1 : out std_logic; - iforce_0_m : out std_logic_vector(4 to 4); - ilevel_5 : out std_logic; - ilevel_4 : out std_logic; - ilevel_6 : out std_logic; - ilevel_3 : out std_logic; - ilevel_11 : out std_logic; - ilevel_7 : out std_logic; - ilevel_9 : out std_logic; - prdata_11_m_1_0 : out std_logic_vector(4 to 4); - prdata_13_m_1_0 : out std_logic_vector(4 to 4); - paddr : in std_logic_vector(7 downto 3) := (others => 'U'); - prdata_0_iv_0_0_0_12 : out std_logic; - prdata_0_iv_0_0_0_0 : out std_logic; - prdata_0_iv_0_0_0_13 : out std_logic; - prdata_0_iv_0_0_1_12 : out std_logic; - prdata_0_iv_0_0_1_0 : out std_logic; - prdata_0_iv_0_0_1_13 : out std_logic; - pwdata_0 : in std_logic_vector(15 downto 1) := (others => 'U'); - pirq_10 : in std_logic := 'U'; - pirq_11 : in std_logic := 'U'; - pirq_13 : in std_logic := 'U'; - pirq_7 : in std_logic := 'U'; - pirq_6 : in std_logic := 'U'; - pirq_0 : in std_logic := 'U'; - paddr_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - lclk_c : in std_logic := 'U'; - N_365 : out std_logic; - N_367 : out std_logic; - N_863 : out std_logic; - intack : in std_logic := 'U'; - N_865 : out std_logic; - N_861 : out std_logic; - N_859 : out std_logic; - N_478 : out std_logic; - N_476 : out std_logic; - N_474 : out std_logic; - N_473 : out std_logic; - N_472 : out std_logic; - N_471 : out std_logic; - N_470 : out std_logic; - N_468 : out std_logic; - N_467 : out std_logic; - N_842 : out std_logic; - N_841 : out std_logic; - N_839 : out std_logic; - N_363 : out std_logic; - N_361 : out std_logic; - N_773 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - N_749 : in std_logic := 'U'; - prdata_0_sqmuxa : out std_logic; - N_898 : out std_logic; - prdata_1_sqmuxa : out std_logic - ); - end component; - - component GND - port( Y : out std_logic - ); - end component; - - component VCC - port( Y : out std_logic - ); - end component; - - component apbuart - port( pwdata_12 : in std_logic := 'U'; - pwdata_13 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_2 : in std_logic := 'U'; - pwdata_5 : in std_logic := 'U'; - pwdata_6 : in std_logic := 'U'; - pwdata_7 : in std_logic := 'U'; - pwdata_8 : in std_logic := 'U'; - pwdata_9 : in std_logic := 'U'; - pwdata_10 : in std_logic := 'U'; - pwdata_11 : in std_logic := 'U'; - pirq : out std_logic_vector(2 to 2); - rcnt_RNI8FBM3 : out std_logic_vector(1 to 1); - rdata_2_0 : out std_logic; - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - paddr : in std_logic_vector(4 to 4) := (others => 'U'); - rdata_2_m_3 : out std_logic; - rdata_2_m_4 : out std_logic; - rdata_2_m_2 : out std_logic; - brate_0 : out std_logic; - brate_10 : out std_logic; - brate_9 : out std_logic; - brate_8 : out std_logic; - brate_7 : out std_logic; - brate_6 : out std_logic; - brate_m_3 : out std_logic; - brate_m_2 : out std_logic; - brate_m_9 : out std_logic; - pwdata_0 : in std_logic_vector(11 downto 0) := (others => 'U'); - rcnt_0 : out std_logic; - rcnt_1 : out std_logic; - rdata_17_m_0_d0 : out std_logic; - rdata_17_m_5 : out std_logic; - rdata_17_m_4 : out std_logic; - un1_uart1_34 : out std_logic; - rdata_17_m_0_4 : out std_logic; - rdata_iv_0_a2_3_0 : out std_logic_vector(7 to 7); - tcnt_0 : out std_logic; - tcnt_1 : out std_logic; - rdata_iv_2 : out std_logic_vector(3 downto 2); - rdata_iv_0_2 : out std_logic_vector(1 to 1); - prdata_6 : out std_logic; - prdata_0 : out std_logic; - prdata_9 : out std_logic; - paddr_0 : in std_logic_vector(4 to 4) := (others => 'U'); - apbuart_VCC : in std_logic := 'U'; - apbuart_GND : in std_logic := 'U'; - rxd1_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - txd1_c : out std_logic; - N_227 : out std_logic; - thempty_1_m : out std_logic; - debug_m : out std_logic; - N_232 : in std_logic := 'U'; - rdata60 : in std_logic := 'U'; - frame : out std_logic; - rdata59 : in std_logic := 'U'; - parerr_m : out std_logic; - rdata60_4 : out std_logic; - rdata62 : out std_logic; - N_6455_0 : in std_logic := 'U'; - rdata59_4 : out std_logic; - parsel_m_0 : out std_logic; - ovf_m : out std_logic; - break_m : out std_logic; - N_223 : out std_logic; - N_220 : out std_logic; - rfifoirqen_m : out std_logic; - tfifoirqen_m : out std_logic; - N_156 : out std_logic; - rhalffull_1_m : out std_logic; - rdata_3_sqmuxa : out std_logic; - ctrl2 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - tsemptyirqen_0 : out std_logic; - N_773 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - paren : out std_logic; - N_750 : in std_logic := 'U'; - penable : in std_logic := 'U'; - breakirqen : out std_logic; - delayirqen : out std_logic; - rdata_4_sqmuxa : out std_logic; - rdata_0_sqmuxa : out std_logic; - tcnt_i : out std_logic; - flow_m : out std_logic; - extclken_m : out std_logic; - rdata61 : in std_logic := 'U'; - pwrite : in std_logic := 'U'; - un1_apbi_8 : in std_logic := 'U'; - rdata62_0 : out std_logic; - rdata60_1 : in std_logic := 'U'; - rdata61_2 : in std_logic := 'U'; - rdata60_4_0 : out std_logic - ); - end component; - - component apbctrl - port( hrdata : out std_logic_vector(31 downto 0); - pwdata : out std_logic_vector(31 downto 0); - psel_1 : out std_logic_vector(7 to 7); - prdata_4 : in std_logic_vector(31 to 31) := (others => 'U'); - rdata_iv_0_2 : in std_logic_vector(1 to 1) := (others => 'U'); - prdata_iv_0_0 : in std_logic_vector(2 to 2) := (others => 'U'); - ramrws : in std_logic_vector(1 to 1) := (others => 'U'); - ramwws : in std_logic_vector(1 downto 0) := (others => 'U'); - romrws : in std_logic_vector(3 downto 1) := (others => 'U'); - prdata_iv_0_2 : in std_logic := 'U'; - prdata_iv_0_0_d0 : in std_logic := 'U'; - un1_grgpio0_0 : in std_logic := 'U'; - un1_grgpio0_2 : in std_logic := 'U'; - ramwidth : in std_logic_vector(1 downto 0) := (others => 'U'); - rdata_iv_2 : in std_logic_vector(3 downto 2) := (others => 'U'); - readdata_iv_3 : in std_logic_vector(3 downto 2) := (others => 'U'); - tcnt : in std_logic_vector(1 downto 0) := (others => 'U'); - prdata_3_29 : in std_logic := 'U'; - prdata_3_12 : in std_logic := 'U'; - prdata_3_0 : in std_logic := 'U'; - prdata_3_1 : in std_logic := 'U'; - prdata_3_14 : in std_logic := 'U'; - prdata_3_13 : in std_logic := 'U'; - prdata_3_26 : in std_logic := 'U'; - prdata_3_23 : in std_logic := 'U'; - prdata_3_16 : in std_logic := 'U'; - prdata_3_28 : in std_logic := 'U'; - prdata_3_27 : in std_logic := 'U'; - prdata_3_17 : in std_logic := 'U'; - prdata_3_15 : in std_logic := 'U'; - romwws : in std_logic_vector(3 downto 0) := (others => 'U'); - romwidth : in std_logic_vector(1 downto 0) := (others => 'U'); - rambanksz_0 : in std_logic := 'U'; - rambanksz_1 : in std_logic := 'U'; - rambanksz_3 : in std_logic := 'U'; - prdata_0_iv_0_0_0_13 : in std_logic := 'U'; - prdata_0_iv_0_0_0_0 : in std_logic := 'U'; - prdata_0_iv_0_0_0_12 : in std_logic := 'U'; - prdata_0_iv_0_0_1_13 : in std_logic := 'U'; - prdata_0_iv_0_0_1_0 : in std_logic := 'U'; - prdata_0_iv_0_0_1_12 : in std_logic := 'U'; - readdata_1_iv_0_13 : in std_logic := 'U'; - readdata_1_iv_0_2 : in std_logic := 'U'; - readdata_1_iv_0_0 : in std_logic := 'U'; - readdata_1_iv_0_9 : in std_logic := 'U'; - readdata_1_iv_0_11 : in std_logic := 'U'; - prdata_2_20 : in std_logic := 'U'; - prdata_2_31 : in std_logic := 'U'; - prdata_2_14 : in std_logic := 'U'; - prdata_2_1 : in std_logic := 'U'; - prdata_2_2 : in std_logic := 'U'; - prdata_2_5 : in std_logic := 'U'; - prdata_2_0 : in std_logic := 'U'; - prdata_2_3 : in std_logic := 'U'; - prdata_2_16 : in std_logic := 'U'; - prdata_2_21 : in std_logic := 'U'; - prdata_2_23 : in std_logic := 'U'; - prdata_2_15 : in std_logic := 'U'; - prdata_2_27 : in std_logic := 'U'; - prdata_2_28 : in std_logic := 'U'; - prdata_2_25 : in std_logic := 'U'; - prdata_2_18 : in std_logic := 'U'; - prdata_2_30 : in std_logic := 'U'; - prdata_2_29 : in std_logic := 'U'; - prdata_2_19 : in std_logic := 'U'; - prdata_2_17 : in std_logic := 'U'; - prdata_2_9 : in std_logic := 'U'; - prdata_2_13 : in std_logic := 'U'; - prdata_2_22 : in std_logic := 'U'; - prdata_2_24 : in std_logic := 'U'; - prdata_2_26 : in std_logic := 'U'; - prdata_11_m_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - prdata_13_m_1_0 : in std_logic_vector(4 to 4) := (others => 'U'); - psel_0 : out std_logic; - psel_15 : out std_logic; - psel_11 : out std_logic; - reload_RNI6SNI : in std_logic_vector(1 to 1) := (others => 'U'); - readdata_9_i_m : in std_logic_vector(1 to 1) := (others => 'U'); - un1_uart1 : in std_logic_vector(36 to 36) := (others => 'U'); - reload_m_0 : in std_logic_vector(0 to 0) := (others => 'U'); - reload_0 : in std_logic_vector(7 downto 6) := (others => 'U'); - un1_dcom0 : in std_logic_vector(19 downto 12) := (others => 'U'); - iows : in std_logic_vector(3 downto 2) := (others => 'U'); - ipend : in std_logic_vector(11 to 11) := (others => 'U'); - iforce_0_m : in std_logic_vector(4 to 4) := (others => 'U'); - ipend_m : in std_logic_vector(4 to 4) := (others => 'U'); - iforce_0_5 : in std_logic := 'U'; - iforce_0_2 : in std_logic := 'U'; - iforce_0_1 : in std_logic := 'U'; - iforce_0_7 : in std_logic := 'U'; - iforce_0_0 : in std_logic := 'U'; - ilevel_6 : in std_logic := 'U'; - ilevel_4 : in std_logic := 'U'; - ilevel_3 : in std_logic := 'U'; - ilevel_2 : in std_logic := 'U'; - ilevel_0 : in std_logic := 'U'; - ilevel_8 : in std_logic := 'U'; - ilevel_1 : in std_logic := 'U'; - oen : in std_logic_vector(7 to 7) := (others => 'U'); - readdata_2_m : in std_logic_vector(5 to 5) := (others => 'U'); - dout_2 : in std_logic := 'U'; - dout_0 : in std_logic := 'U'; - dout_6 : in std_logic := 'U'; - dout_5 : in std_logic := 'U'; - dout_4 : in std_logic := 'U'; - value_RNIBAHH : in std_logic_vector(1 to 1) := (others => 'U'); - reload_RNIRDRG : in std_logic_vector(1 to 1) := (others => 'U'); - scaler_i_m : in std_logic_vector(1 to 1) := (others => 'U'); - scaler : in std_logic_vector(4 to 4) := (others => 'U'); - value_6 : in std_logic := 'U'; - value_0 : in std_logic := 'U'; - reload_8 : in std_logic := 'U'; - reload_7 : in std_logic := 'U'; - reload_6 : in std_logic := 'U'; - reload_24 : in std_logic := 'U'; - reload_4 : in std_logic := 'U'; - reload_3 : in std_logic := 'U'; - reload_2 : in std_logic := 'U'; - reload_0_d0 : in std_logic := 'U'; - reload_1 : in std_logic := 'U'; - scaler_m_7 : in std_logic := 'U'; - scaler_m_6 : in std_logic := 'U'; - scaler_m_0 : in std_logic := 'U'; - scaler_m_5 : in std_logic := 'U'; - rcnt : in std_logic_vector(1 downto 0) := (others => 'U'); - rdata_2 : in std_logic_vector(0 to 0) := (others => 'U'); - rcnt_RNI8FBM3 : in std_logic_vector(1 to 1) := (others => 'U'); - rdata_iv_0_a2_3_0 : in std_logic_vector(7 to 7) := (others => 'U'); - brate_9 : in std_logic := 'U'; - brate_8 : in std_logic := 'U'; - brate_0 : in std_logic := 'U'; - brate_10 : in std_logic := 'U'; - brate_7 : in std_logic := 'U'; - brate_6 : in std_logic := 'U'; - rdata_17_m_0 : in std_logic_vector(6 to 6) := (others => 'U'); - brate_m_7 : in std_logic := 'U'; - brate_m_0 : in std_logic := 'U'; - brate_m_1 : in std_logic := 'U'; - rdata_17_m_0_d0 : in std_logic := 'U'; - rdata_17_m_4 : in std_logic := 'U'; - rdata_17_m_5 : in std_logic := 'U'; - rdata_2_m : in std_logic_vector(6 downto 4) := (others => 'U'); - prdata_1_20 : in std_logic := 'U'; - prdata_1_5 : in std_logic := 'U'; - prdata_1_12 : in std_logic := 'U'; - prdata_1_21 : in std_logic := 'U'; - prdata_1_23 : in std_logic := 'U'; - prdata_1_27 : in std_logic := 'U'; - prdata_1_0 : in std_logic := 'U'; - prdata_1_4 : in std_logic := 'U'; - prdata_1_6 : in std_logic := 'U'; - prdata_1_7 : in std_logic := 'U'; - prdata_1_8 : in std_logic := 'U'; - prdata_1_9 : in std_logic := 'U'; - prdata_1_10 : in std_logic := 'U'; - prdata_1_11 : in std_logic := 'U'; - prdata_1_22 : in std_logic := 'U'; - prdata_1_28 : in std_logic := 'U'; - paddr_5 : out std_logic; - paddr_2_d0 : out std_logic; - paddr_0_d0 : out std_logic; - paddr_1_d0 : out std_logic; - paddr_3 : out std_logic; - paddr_4 : out std_logic; - htrans : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - readdata_9_4 : in std_logic := 'U'; - readdata_9_0 : in std_logic := 'U'; - readdata_9_5 : in std_logic := 'U'; - readdata_9_27 : in std_logic := 'U'; - reload_m_2 : in std_logic := 'U'; - reload_m_3 : in std_logic := 'U'; - reload_m_21 : in std_logic := 'U'; - reload_m_9 : in std_logic := 'U'; - reload_m_0_d0 : in std_logic := 'U'; - reload_m_5 : in std_logic := 'U'; - reload_m_27 : in std_logic := 'U'; - reload_m_20 : in std_logic := 'U'; - reload_m_4 : in std_logic := 'U'; - value_m_22 : in std_logic := 'U'; - value_m_11 : in std_logic := 'U'; - value_m_9 : in std_logic := 'U'; - value_m_18 : in std_logic := 'U'; - value_m_20 : in std_logic := 'U'; - value_m_17 : in std_logic := 'U'; - value_m_4 : in std_logic := 'U'; - value_m_5 : in std_logic := 'U'; - value_m_3 : in std_logic := 'U'; - value_m_0 : in std_logic := 'U'; - value_m_1 : in std_logic := 'U'; - value_m_8 : in std_logic := 'U'; - value_m_7 : in std_logic := 'U'; - value_m_6 : in std_logic := 'U'; - value_m_23 : in std_logic := 'U'; - value_m_24 : in std_logic := 'U'; - value_m_16 : in std_logic := 'U'; - prdata_0_1 : in std_logic := 'U'; - prdata_0_23 : in std_logic := 'U'; - prdata_0_18 : in std_logic := 'U'; - prdata_0_30 : in std_logic := 'U'; - prdata_0_29 : in std_logic := 'U'; - prdata_0_0 : in std_logic := 'U'; - prdata_0_8 : in std_logic := 'U'; - prdata_0_10 : in std_logic := 'U'; - prdata_0_11 : in std_logic := 'U'; - prdata_0_12 : in std_logic := 'U'; - prdata_0_13 : in std_logic := 'U'; - prdata_0_24 : in std_logic := 'U'; - prdata_0_26 : in std_logic := 'U'; - prdata_0_17 : in std_logic := 'U'; - prdata_0_19 : in std_logic := 'U'; - prdata_0_25 : in std_logic := 'U'; - prdata_0_16 : in std_logic := 'U'; - prdata_0_22 : in std_logic := 'U'; - prdata_0_15 : in std_logic := 'U'; - prdata_0_31 : in std_logic := 'U'; - prdata_0_14 : in std_logic := 'U'; - prdata_0_21 : in std_logic := 'U'; - prdata_0_27 : in std_logic := 'U'; - prdata_0_20 : in std_logic := 'U'; - prdata_0_4 : in std_logic := 'U'; - prdata_0_6 : in std_logic := 'U'; - prdata_0_7 : in std_logic := 'U'; - prdata_0_5 : in std_logic := 'U'; - prdata_0_3 : in std_logic := 'U'; - prdata_0_2 : in std_logic := 'U'; - prdata_0_28 : in std_logic := 'U'; - prdata : in std_logic_vector(31 downto 0) := (others => 'U'); - pwdata_i : out std_logic_vector(7 downto 0); - pwdata_1_3 : out std_logic; - pwdata_1_2 : out std_logic; - pwdata_1_0 : out std_logic; - hwdata : in std_logic_vector(31 downto 0) := (others => 'U'); - pwdata_0 : out std_logic_vector(15 downto 0); - paddr_0 : out std_logic_vector(4 downto 2); - paddr_1 : out std_logic_vector(2 to 2); - haddr : in std_logic_vector(19 downto 2) := (others => 'U'); - paddr_2 : out std_logic_vector(2 to 2); - hready : out std_logic; - readdata51_1 : in std_logic := 'U'; - N_227 : in std_logic := 'U'; - thempty_1_m : in std_logic := 'U'; - N_6432 : in std_logic := 'U'; - rmw : in std_logic := 'U'; - penable : out std_logic; - un1_apbi_2 : in std_logic := 'U'; - N_5062 : in std_logic := 'U'; - break_m : in std_logic := 'U'; - N_332 : in std_logic := 'U'; - N_333 : in std_logic := 'U'; - N_334 : in std_logic := 'U'; - N_335 : in std_logic := 'U'; - N_336 : in std_logic := 'U'; - N_5070 : in std_logic := 'U'; - breakirqen : in std_logic := 'U'; - N_6455_0 : in std_logic := 'U'; - N_773 : out std_logic; - hwrite : in std_logic := 'U'; - un1_apbi_7_3 : out std_logic; - N_330 : in std_logic := 'U'; - parerr_m : in std_logic := 'U'; - rdata60_1 : in std_logic := 'U'; - N_331 : in std_logic := 'U'; - N_86 : in std_logic := 'U'; - N_85 : in std_logic := 'U'; - un1_apbi_7_1 : in std_logic := 'U'; - rstn : in std_logic := 'U'; - bexcen : in std_logic := 'U'; - ioen : in std_logic := 'U'; - ovf_m : in std_logic := 'U'; - parsel_m_0 : in std_logic := 'U'; - frame : in std_logic := 'U'; - tcnt_i : in std_logic := 'U'; - N_156 : in std_logic := 'U'; - readdata56 : in std_logic := 'U'; - tfifoirqen_m : in std_logic := 'U'; - rfifoirqen_m : in std_logic := 'U'; - debug_m : in std_logic := 'U'; - delayirqen : in std_logic := 'U'; - N_127 : in std_logic := 'U'; - N_78 : out std_logic; - N_232_0 : in std_logic := 'U'; - brdyen : in std_logic := 'U'; - N_839 : in std_logic := 'U'; - prdata_1_sqmuxa : in std_logic := 'U'; - N_842 : in std_logic := 'U'; - N_841 : in std_logic := 'U'; - N_476 : in std_logic := 'U'; - N_478 : in std_logic := 'U'; - N_474 : in std_logic := 'U'; - N_473 : in std_logic := 'U'; - N_471 : in std_logic := 'U'; - N_472 : in std_logic := 'U'; - N_470 : in std_logic := 'U'; - N_467 : in std_logic := 'U'; - N_468 : in std_logic := 'U'; - N_859 : in std_logic := 'U'; - N_861 : in std_logic := 'U'; - N_361 : in std_logic := 'U'; - N_363 : in std_logic := 'U'; - readdata55_3 : in std_logic := 'U'; - N_863 : in std_logic := 'U'; - N_865 : in std_logic := 'U'; - N_365 : in std_logic := 'U'; - N_898 : in std_logic := 'U'; - N_367 : in std_logic := 'U'; - prdata_0_sqmuxa : in std_logic := 'U'; - rdata60_4_0 : in std_logic := 'U'; - N_6437 : in std_logic := 'U'; - N_6439 : in std_logic := 'U'; - N_6435 : in std_logic := 'U'; - N_6436 : in std_logic := 'U'; - N_6434 : in std_logic := 'U'; - N_6429 : in std_logic := 'U'; - N_6430 : in std_logic := 'U'; - N_6428 : in std_logic := 'U'; - rdata59_4 : in std_logic := 'U'; - N_220_0 : in std_logic := 'U'; - N_219 : in std_logic := 'U'; - N_240 : in std_logic := 'U'; - N_218 : in std_logic := 'U'; - N_236 : in std_logic := 'U'; - N_229 : in std_logic := 'U'; - N_228 : in std_logic := 'U'; - N_216 : in std_logic := 'U'; - N_217 : in std_logic := 'U'; - dishlt : in std_logic := 'U'; - restart_RNIIKBB : in std_logic := 'U'; - N_215 : in std_logic := 'U'; - N_214 : in std_logic := 'U'; - N_240_0 : in std_logic := 'U'; - readdata57 : in std_logic := 'U'; - irqpen_m : in std_logic := 'U'; - readdata55 : in std_logic := 'U'; - enable_m : in std_logic := 'U'; - value_0_sqmuxa_0 : in std_logic := 'U'; - chain_m : in std_logic := 'U'; - readdata_1_sqmuxa_1_0 : in std_logic := 'U'; - tsemptyirqen : in std_logic := 'U'; - rdata_0_sqmuxa : in std_logic := 'U'; - N_223 : in std_logic := 'U'; - N_220 : in std_logic := 'U'; - rdata_3_sqmuxa : in std_logic := 'U'; - rdata_4_sqmuxa : in std_logic := 'U'; - paren : in std_logic := 'U'; - N_770 : in std_logic := 'U'; - rhalffull_1_m : in std_logic := 'U'; - flow_m : in std_logic := 'U'; - extclken_m : in std_logic := 'U'; - N_769 : out std_logic; - N_116 : out std_logic; - N_796 : out std_logic; - N_750 : out std_logic; - N_749 : out std_logic; - lclk_c : in std_logic := 'U'; - pwrite : out std_logic; - un51_ioen_NE : in std_logic := 'U' - ); - end component; - - component CLKINT - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component ahbram - port( hwdata : in std_logic_vector(31 downto 0) := (others => 'U'); - hrdata : out std_logic_vector(31 downto 0); - hsize : in std_logic_vector(1 downto 0) := (others => 'U'); - iosn : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : in std_logic_vector(1 to 1) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - haddr : in std_logic_vector(9 downto 0) := (others => 'U'); - lclk_c : in std_logic := 'U'; - un315_ioen_NE : in std_logic := 'U'; - hready : out std_logic; - hwrite_1 : in std_logic := 'U'; - rstn : in std_logic := 'U' - ); - end component; - - component CLKBUF - port( PAD : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component lpp_bootloader - port( haddr : in std_logic_vector(9 downto 2) := (others => 'U'); - hrdata_26 : out std_logic; - hrdata_13 : out std_logic; - hrdata_8 : out std_logic; - hrdata_5 : out std_logic; - hrdata_29 : out std_logic; - hrdata_18 : out std_logic; - hrdata_6 : out std_logic; - hrdata_19 : out std_logic; - hrdata_17 : out std_logic; - hrdata_7 : out std_logic; - hrdata_16 : out std_logic; - hrdata_30 : out std_logic; - hrdata_9 : out std_logic; - hrdata_25 : out std_logic; - hrdata_27 : out std_logic; - hrdata_21 : out std_logic; - hrdata_3 : out std_logic; - hrdata_0 : out std_logic; - hrdata_1 : out std_logic; - hrdata_23 : out std_logic; - hrdata_4 : out std_logic; - hrdata_28 : out std_logic; - hrdata_14 : out std_logic; - hrdata_22 : out std_logic; - hrdata_15 : out std_logic; - hrdata_2 : out std_logic; - hrdata_11 : out std_logic; - hrdata_10 : out std_logic; - hrdata_12 : out std_logic; - prdata : out std_logic_vector(31 downto 0); - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - pwdata_31 : in std_logic := 'U'; - pwdata_30 : in std_logic := 'U'; - pwdata_29 : in std_logic := 'U'; - pwdata_28 : in std_logic := 'U'; - pwdata_27 : in std_logic := 'U'; - pwdata_26 : in std_logic := 'U'; - pwdata_25 : in std_logic := 'U'; - pwdata_24 : in std_logic := 'U'; - pwdata_23 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_19 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_13 : in std_logic := 'U'; - pwdata_12 : in std_logic := 'U'; - pwdata_11 : in std_logic := 'U'; - pwdata_10 : in std_logic := 'U'; - pwdata_9 : in std_logic := 'U'; - pwdata_8 : in std_logic := 'U'; - pwdata_7 : in std_logic := 'U'; - pwdata_6 : in std_logic := 'U'; - pwdata_5 : in std_logic := 'U'; - pwdata_2 : in std_logic := 'U'; - pwdata_0 : in std_logic := 'U'; - N_103_i_0 : out std_logic; - N_90_i_0 : out std_logic; - N_95_i_0 : out std_logic; - rstraw_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - rdata60_4 : in std_logic := 'U'; - N_6459 : in std_logic := 'U'; - rdata59_4 : in std_logic := 'U'; - readdata55_3 : in std_logic := 'U'; - rdata62_3 : in std_logic := 'U'; - N_750 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - rdata60_4_0 : in std_logic := 'U'; - N_796 : in std_logic := 'U' - ); - end component; - - component lpp_top_lfr_wf_picker - port( sdo_adc_c : in std_logic_vector(7 downto 0) := (others => 'U'); - hburst : out std_logic_vector(2 downto 0); - htrans : out std_logic_vector(1 downto 0); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - iosn_1 : in std_logic_vector(93 to 93) := (others => 'U'); - nhmaster_1_i : in std_logic_vector(0 to 0) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - hmaster_0 : in std_logic_vector(1 to 1) := (others => 'U'); - haddr : out std_logic_vector(31 downto 0); - bco_msb_1 : in std_logic_vector(1 to 1) := (others => 'U'); - hmaster_0_0_RNIFCVH1_0 : in std_logic_vector(1 to 1) := (others => 'U'); - hgrant : in std_logic_vector(3 to 3) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - bco_msb_1_m : in std_logic_vector(1 to 1) := (others => 'U'); - nhmaster_1_iv_0 : in std_logic_vector(1 to 1) := (others => 'U'); - l1_0_m : in std_logic_vector(1 to 1) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - coarse_time : in std_logic_vector(0 to 0) := (others => 'U'); - coarse_time_i : in std_logic_vector(0 to 0) := (others => 'U'); - pwdata_0 : in std_logic_vector(11 downto 0) := (others => 'U'); - paddr_0 : in std_logic_vector(4 downto 2) := (others => 'U'); - paddr : in std_logic_vector(7 downto 3) := (others => 'U'); - paddr_2 : in std_logic_vector(2 to 2) := (others => 'U'); - pwdata_1_2 : in std_logic := 'U'; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - pwdata : in std_logic_vector(31 downto 0) := (others => 'U'); - pirq : out std_logic_vector(15 to 15); - prdata : out std_logic_vector(31 downto 0); - lpp_top_lfr_wf_picker_VCC : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - cnv_ch1_c : out std_logic; - sck_ch1_c : out std_logic; - lpp_top_lfr_wf_picker_GND : in std_logic := 'U'; - IdlePhase : out std_logic; - hwrite : out std_logic; - un1_dmain_6 : out std_logic; - arb_1 : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - Lock_RNIU86D : out std_logic; - un1_nhmaster_0_sqmuxa_1 : in std_logic := 'U'; - rstoutl_RNIGJKSJO : in std_logic := 'U'; - m19_0_N_15_i_0_li : in std_logic := 'U'; - m19_a0_6_i_0 : out std_logic; - m19_a1_6_i_0 : out std_logic; - m26_m1_e : out std_logic; - lclk_c : in std_logic := 'U'; - rstn : in std_logic := 'U'; - N_232 : in std_logic := 'U'; - N_6455_0 : in std_logic := 'U'; - Bias_Fails_c : out std_logic; - N_749 : in std_logic := 'U'; - N_116 : in std_logic := 'U'; - N_769 : in std_logic := 'U'; - N_232_0 : in std_logic := 'U'; - N_232_1 : in std_logic := 'U'; - rdata61_2 : in std_logic := 'U'; - N_6455 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U' - ); - end component; - - component ahbuart - port( haddr : out std_logic_vector(31 downto 0); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - hrdata_0_0 : in std_logic := 'U'; - hrdata_0_24 : in std_logic := 'U'; - hrdata_0_26 : in std_logic := 'U'; - hrdata_0_27 : in std_logic := 'U'; - hrdata_0_8 : in std_logic := 'U'; - hrdata_0_16 : in std_logic := 'U'; - hrdata_0_18 : in std_logic := 'U'; - hrdata_0_10 : in std_logic := 'U'; - hrdata_0_22 : in std_logic := 'U'; - hrdata_0_7 : in std_logic := 'U'; - hrdata_0_17 : in std_logic := 'U'; - hrdata_0_23 : in std_logic := 'U'; - hrdata_0_3 : in std_logic := 'U'; - hrdata_0_11 : in std_logic := 'U'; - hrdata_0_12 : in std_logic := 'U'; - hrdata_0_4 : in std_logic := 'U'; - hrdata_0_21 : in std_logic := 'U'; - hrdata_0_15 : in std_logic := 'U'; - hrdata_0_14 : in std_logic := 'U'; - hrdata_0_13 : in std_logic := 'U'; - hrdata_0_9 : in std_logic := 'U'; - hrdata_0_2 : in std_logic := 'U'; - hrdata_0_1 : in std_logic := 'U'; - hrdata_23 : in std_logic := 'U'; - hrdata_25 : in std_logic := 'U'; - hrdata_26 : in std_logic := 'U'; - hrdata_24 : in std_logic := 'U'; - hrdata_1 : in std_logic := 'U'; - hrdata_0_d0 : in std_logic := 'U'; - pwdata_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - un1_dcom0 : out std_logic_vector(19 downto 12); - pwdata : in std_logic_vector(17 downto 16) := (others => 'U'); - psel_1 : in std_logic_vector(7 to 7) := (others => 'U'); - prdata_0 : out std_logic; - prdata_5 : out std_logic; - pwdata_1 : in std_logic_vector(4 to 4) := (others => 'U'); - paddr : in std_logic_vector(3 downto 2) := (others => 'U'); - hwdata : out std_logic_vector(31 downto 0); - iosn_2 : in std_logic_vector(93 to 93) := (others => 'U'); - htrans : out std_logic_vector(1 to 1); - hgrant : in std_logic_vector(1 to 1) := (others => 'U'); - iosn : in std_logic_vector(93 to 93) := (others => 'U'); - hwrite : out std_logic; - N_264_0 : in std_logic := 'U'; - N_262_0 : in std_logic := 'U'; - N_78_0 : in std_logic := 'U'; - N_78 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - N_86 : out std_logic; - rdata60_1 : in std_logic := 'U'; - N_85 : out std_logic; - dsutx_c : out std_logic; - N_6455_0 : in std_logic := 'U'; - N_332 : out std_logic; - N_333 : out std_logic; - N_334 : out std_logic; - N_336 : out std_logic; - N_331 : out std_logic; - N_6455 : in std_logic := 'U'; - N_127 : out std_logic; - N_330 : out std_logic; - N_769 : in std_logic := 'U'; - un1_apbi_2 : in std_logic := 'U'; - N_335 : out std_logic; - dsurx_c : in std_logic := 'U'; - rstn : in std_logic := 'U'; - hbusreq_i_3 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component ahbctrl - port( hmbsel : out std_logic_vector(0 to 0); - htrans_3 : in std_logic_vector(1 to 1) := (others => 'U'); - htrans_2 : in std_logic_vector(1 to 1) := (others => 'U'); - htrans_1 : in std_logic_vector(1 to 1) := (others => 'U'); - htrans_0_0 : in std_logic := 'U'; - bco_msb_1 : out std_logic_vector(1 to 1); - hresp_0 : out std_logic_vector(0 to 0); - nhmaster_1_i : out std_logic_vector(0 to 0); - hgrant_3 : out std_logic; - hgrant_1 : out std_logic; - hgrant_0 : out std_logic; - hsize_5 : in std_logic_vector(1 to 1) := (others => 'U'); - hmbsel_1 : out std_logic_vector(0 to 0); - hburst_0 : in std_logic_vector(2 downto 0) := (others => 'U'); - hsize_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - hsize : out std_logic_vector(1 downto 0); - haddr_3_4 : in std_logic := 'U'; - haddr_3_5 : in std_logic := 'U'; - haddr_3_0 : in std_logic := 'U'; - haddr_3_3 : in std_logic := 'U'; - haddr_3_8 : in std_logic := 'U'; - haddr_3_6 : in std_logic := 'U'; - haddr_3_1 : in std_logic := 'U'; - haddr_3_7 : in std_logic := 'U'; - hwdata_m_0_3 : out std_logic; - hwdata_m_0_0 : out std_logic; - hwdata_m_0_2 : out std_logic; - hwdata_m_8 : out std_logic; - hwdata_m_13 : out std_logic; - hwdata_m_5 : out std_logic; - hwdata_m_0_d0 : out std_logic; - hwdata_m_7 : out std_logic; - hwdata_2_15 : out std_logic; - hwdata_2_0 : in std_logic := 'U'; - hwdata_2_9 : in std_logic := 'U'; - hwdata_2_3 : in std_logic := 'U'; - hwdata_2_14 : out std_logic; - hwdata_2_1 : in std_logic := 'U'; - hwdata_2_28 : in std_logic := 'U'; - hwdata_2_27 : in std_logic := 'U'; - hwdata_2_25 : in std_logic := 'U'; - hwdata_2_23 : in std_logic := 'U'; - hwdata_2_13 : in std_logic := 'U'; - hwdata_2_12 : in std_logic := 'U'; - hwdata_2_11 : in std_logic := 'U'; - hwdata_2_4 : in std_logic := 'U'; - hwdata_2_16 : in std_logic := 'U'; - hwdata_1 : inout std_logic_vector(31 downto 0); - hwdata_0 : in std_logic_vector(31 downto 0) := (others => 'U'); - hwdata : inout std_logic_vector(31 downto 0); - haddr_2 : inout std_logic_vector(30 downto 2); - haddr_1 : inout std_logic_vector(31 downto 0); - haddr_0 : inout std_logic_vector(31 downto 0); - hrdata_4_15 : in std_logic := 'U'; - hrdata_4_13 : in std_logic := 'U'; - hrdata_4_11 : in std_logic := 'U'; - hrdata_4_27 : in std_logic := 'U'; - hrdata_4_26 : in std_logic := 'U'; - hrdata_4_4 : in std_logic := 'U'; - hrdata_4_21 : in std_logic := 'U'; - hrdata_4_1 : in std_logic := 'U'; - hrdata_4_22 : in std_logic := 'U'; - hrdata_4_23 : in std_logic := 'U'; - hrdata_4_0 : in std_logic := 'U'; - hrdata_4_14 : in std_logic := 'U'; - hrdata_4_3 : in std_logic := 'U'; - hrdata_4_2 : in std_logic := 'U'; - hrdata_4_9 : in std_logic := 'U'; - hrdata_4_12 : in std_logic := 'U'; - hrdata_4_10 : in std_logic := 'U'; - hrdata_4_7 : in std_logic := 'U'; - hrdata_4_8 : in std_logic := 'U'; - hrdata_4_16 : in std_logic := 'U'; - hrdata_4_18 : in std_logic := 'U'; - hrdata_4_17 : in std_logic := 'U'; - hrdata_3_15 : in std_logic := 'U'; - hrdata_3_13 : in std_logic := 'U'; - hrdata_3_11 : in std_logic := 'U'; - hrdata_3_28 : in std_logic := 'U'; - hrdata_3_27 : in std_logic := 'U'; - hrdata_3_26 : in std_logic := 'U'; - hrdata_3_4 : in std_logic := 'U'; - hrdata_3_1 : in std_logic := 'U'; - hrdata_3_22 : in std_logic := 'U'; - hrdata_3_23 : in std_logic := 'U'; - hrdata_3_0 : in std_logic := 'U'; - hrdata_3_24 : in std_logic := 'U'; - hrdata_3_21 : in std_logic := 'U'; - hrdata_3_14 : in std_logic := 'U'; - hrdata_3_3 : in std_logic := 'U'; - hrdata_3_2 : in std_logic := 'U'; - hrdata_3_9 : in std_logic := 'U'; - hrdata_3_12 : in std_logic := 'U'; - hrdata_3_10 : in std_logic := 'U'; - hrdata_3_7 : in std_logic := 'U'; - hrdata_3_6 : in std_logic := 'U'; - hrdata_3_8 : in std_logic := 'U'; - hrdata_3_29 : in std_logic := 'U'; - hrdata_3_16 : in std_logic := 'U'; - hrdata_3_5 : in std_logic := 'U'; - hrdata_3_30 : in std_logic := 'U'; - hrdata_3_18 : in std_logic := 'U'; - hrdata_3_17 : in std_logic := 'U'; - hrdata_2_28 : in std_logic := 'U'; - hrdata_2_25 : in std_logic := 'U'; - hrdata_2_15 : out std_logic; - hrdata_2_11 : out std_logic; - hrdata_2_27 : out std_logic; - hrdata_2_26 : out std_logic; - hrdata_2_23 : in std_logic := 'U'; - hrdata_2_22 : in std_logic := 'U'; - hrdata_2_21 : in std_logic := 'U'; - hrdata_2_13 : in std_logic := 'U'; - hrdata_2_4 : in std_logic := 'U'; - hrdata_2_1 : in std_logic := 'U'; - hrdata_2_0 : in std_logic := 'U'; - hrdata_2_24 : in std_logic := 'U'; - hrdata_2_14 : in std_logic := 'U'; - hrdata_2_3 : in std_logic := 'U'; - hrdata_2_2 : in std_logic := 'U'; - hrdata_2_31 : in std_logic := 'U'; - hrdata_2_9 : out std_logic; - hrdata_2_19 : in std_logic := 'U'; - hrdata_2_10 : out std_logic; - hrdata_2_7 : out std_logic; - hrdata_2_6 : in std_logic := 'U'; - hrdata_2_29 : in std_logic := 'U'; - hrdata_2_5 : in std_logic := 'U'; - hrdata_2_30 : in std_logic := 'U'; - hrdata_2_18 : in std_logic := 'U'; - hrdata_2_16 : in std_logic := 'U'; - hrdata_2_12 : in std_logic := 'U'; - hrdata_2_8 : in std_logic := 'U'; - hrdata_2_17 : in std_logic := 'U'; - bco_msb_1_m : out std_logic_vector(1 to 1); - hmaster_0_0_RNIFCVH1_0 : out std_logic_vector(1 to 1); - l1_0_m : out std_logic_vector(1 to 1); - nhmaster_1_iv_0 : out std_logic_vector(1 to 1); - hresp : in std_logic_vector(0 to 0) := (others => 'U'); - htrans : out std_logic_vector(1 downto 0); - hrdata_1 : inout std_logic_vector(31 downto 0); - data_0_5 : in std_logic := 'U'; - data_0_21 : in std_logic := 'U'; - data_0_16 : in std_logic := 'U'; - data_0_2 : in std_logic := 'U'; - data_0_0 : in std_logic := 'U'; - data_8 : in std_logic := 'U'; - data_24 : in std_logic := 'U'; - data_0_d0 : in std_logic := 'U'; - data_19 : in std_logic := 'U'; - data_5 : in std_logic := 'U'; - data_3 : in std_logic := 'U'; - hrdata : inout std_logic_vector(31 downto 0); - size : in std_logic_vector(0 to 0) := (others => 'U'); - nbo_5_0 : in std_logic_vector(1 downto 0) := (others => 'U'); - address : in std_logic_vector(1 downto 0) := (others => 'U'); - htrans_tz : in std_logic_vector(1 to 1) := (others => 'U'); - haddr_1_d0 : out std_logic; - haddr_11 : out std_logic; - haddr_31 : in std_logic := 'U'; - haddr_0_d0 : in std_logic := 'U'; - haddr_4 : in std_logic := 'U'; - haddr_15 : out std_logic; - haddr_14 : out std_logic; - haddr_19 : out std_logic; - haddr_18 : out std_logic; - haddr_21 : out std_logic; - haddr_20 : out std_logic; - haddr_23 : out std_logic; - haddr_22 : out std_logic; - haddr_27 : out std_logic; - haddr_26 : out std_logic; - haddr_29 : out std_logic; - haddr_28 : out std_logic; - haddr_12 : out std_logic; - haddr_13 : out std_logic; - haddr_16 : out std_logic; - haddr_17 : out std_logic; - haddr_24 : out std_logic; - haddr_25 : out std_logic; - haddr_30 : out std_logic; - hburst : out std_logic_vector(2 downto 0); - hsel_i : out std_logic_vector(0 to 0); - hrdata_1_0_1_0 : out std_logic; - hrdata_0 : inout std_logic_vector(31 downto 0); - iosn_0 : out std_logic_vector(93 to 93); - iosn_1_8 : out std_logic; - iosn_1_0 : out std_logic; - iosn_2 : out std_logic_vector(93 to 93); - iosn_8 : out std_logic; - iosn_7 : out std_logic; - iosn_0_d0 : out std_logic; - hmaster_0_1 : out std_logic; - N_5054 : in std_logic := 'U'; - htrans_0_sqmuxa_2 : in std_logic := 'U'; - lb_0_sqmuxa_1 : in std_logic := 'U'; - N_466 : in std_logic := 'U'; - N_95_i_0 : in std_logic := 'U'; - bo_5842_d : in std_logic := 'U'; - rstn : in std_logic := 'U'; - hbusreq_i_3_0 : in std_logic := 'U'; - N_90_i_0 : in std_logic := 'U'; - N_262 : out std_logic; - hwrite_1_m_0 : in std_logic := 'U'; - werr_2_m_0 : in std_logic := 'U'; - hwrite_1 : in std_logic := 'U'; - hwrite_0 : in std_logic := 'U'; - N_458 : in std_logic := 'U'; - N_459 : in std_logic := 'U'; - N_468 : in std_logic := 'U'; - N_463 : in std_logic := 'U'; - N_461 : in std_logic := 'U'; - N_510 : in std_logic := 'U'; - N_138 : in std_logic := 'U'; - N_139 : in std_logic := 'U'; - N_6377 : in std_logic := 'U'; - N_103_i_0 : in std_logic := 'U'; - brmw_i : in std_logic := 'U'; - N_6550 : in std_logic := 'U'; - N_264 : out std_logic; - N_467 : in std_logic := 'U'; - N_457 : in std_logic := 'U'; - N_462 : in std_logic := 'U'; - un1_nhmaster_0_sqmuxa_1 : out std_logic; - un1_htrans_1_sqmuxa_0 : in std_logic := 'U'; - un60_nbo : in std_logic := 'U'; - arb_1 : out std_logic; - hbusreq : in std_logic := 'U'; - hlock : in std_logic := 'U'; - hready_1 : in std_logic := 'U'; - hready_0 : in std_logic := 'U'; - N_78 : out std_logic; - un315_ioen_NE : out std_logic; - un51_ioen_NE : out std_logic; - un59_nbo : in std_logic := 'U'; - un91_nbo_i_0 : in std_logic := 'U'; - hready : in std_logic := 'U'; - bo_5842_d_0 : in std_logic := 'U'; - un6_ioen_NE_0 : out std_logic; - brmw_1 : in std_logic := 'U'; - hwrite : out std_logic; - hwrite_m_0_0 : out std_logic; - hbusreq_i_3 : in std_logic := 'U'; - IdlePhase : in std_logic := 'U'; - un1_dmain_6 : in std_logic := 'U'; - Lock_RNIU86D : in std_logic := 'U'; - N_546 : out std_logic; - N_264_0 : out std_logic; - N_262_0 : out std_logic; - N_78_0 : out std_logic; - lclk_c : in std_logic := 'U' - ); - end component; - - component apb_lfr_time_management - port( coarse_time_i : out std_logic_vector(0 to 0); - pirq : out std_logic_vector(13 downto 12); - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - prdata : out std_logic_vector(31 downto 0); - coarse_time_0 : out std_logic; - pwdata_10 : in std_logic := 'U'; - pwdata_8 : in std_logic := 'U'; - pwdata_7 : in std_logic := 'U'; - pwdata_13 : in std_logic := 'U'; - pwdata_12 : in std_logic := 'U'; - pwdata_11 : in std_logic := 'U'; - pwdata_9 : in std_logic := 'U'; - pwdata_6 : in std_logic := 'U'; - pwdata_5 : in std_logic := 'U'; - pwdata_4 : in std_logic := 'U'; - pwdata_3 : in std_logic := 'U'; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_29 : in std_logic := 'U'; - pwdata_28 : in std_logic := 'U'; - pwdata_27 : in std_logic := 'U'; - pwdata_25 : in std_logic := 'U'; - pwdata_24 : in std_logic := 'U'; - pwdata_23 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_19 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_26 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_0 : in std_logic_vector(15 downto 0) := (others => 'U'); - paddr : in std_logic_vector(7 downto 3) := (others => 'U'); - psel : in std_logic_vector(15 to 15) := (others => 'U'); - rstn_i : in std_logic := 'U'; - clk49_152MHz_c : in std_logic := 'U'; - clk49_152MHz_c_0 : in std_logic := 'U'; - un1_apbi_7_1 : out std_logic; - rdata60 : out std_logic; - ctrl2 : out std_logic; - rdata59 : out std_logic; - N_232_0 : in std_logic := 'U'; - un1_apbi_2 : in std_logic := 'U'; - rdata61_2 : in std_logic := 'U'; - N_770 : out std_logic; - rdata62_0 : in std_logic := 'U'; - rdata61 : out std_logic; - un1_apbi_8 : out std_logic; - un1_apbi_7_3 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - rdata62 : in std_logic := 'U'; - rdata60_4 : in std_logic := 'U'; - rdata59_4 : in std_logic := 'U'; - readdata55_3 : in std_logic := 'U'; - rdata62_3 : out std_logic; - pwrite : in std_logic := 'U'; - rstn : in std_logic := 'U'; - lclk_c : in std_logic := 'U' - ); - end component; - - component BUFF - port( A : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - component rstgen - port( rstgen_VCC : in std_logic := 'U'; - rstraw_c : in std_logic := 'U'; - lclk_c : in std_logic := 'U'; - m26_m1_e : in std_logic := 'U'; - rstoutl_RNIGJKSJO : out std_logic; - rstn_i : out std_logic; - rstn : out std_logic - ); - end component; - - component mctrl - port( data_in : in std_logic_vector(31 downto 0) := (others => 'U'); - hresp : out std_logic_vector(0 to 0); - address : out std_logic_vector(31 downto 28); - romsn_c : out std_logic_vector(1 downto 0); - ramoen_c : out std_logic_vector(3 downto 0); - hmbsel_1 : in std_logic_vector(0 to 0) := (others => 'U'); - hburst_0 : in std_logic_vector(2 downto 0) := (others => 'U'); - hmbsel : in std_logic_vector(0 to 0) := (others => 'U'); - ramrws_1 : out std_logic; - ramwws : out std_logic_vector(1 downto 0); - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - rwen_c : out std_logic_vector(3 downto 0); - iosn_1_8 : in std_logic := 'U'; - iosn_1_0 : in std_logic := 'U'; - ramsn_c : out std_logic_vector(3 downto 0); - rambanksz_0 : out std_logic; - rambanksz_1 : out std_logic; - rambanksz_3 : out std_logic; - paddr_2 : in std_logic_vector(2 to 2) := (others => 'U'); - iows_3 : out std_logic; - iows_2 : out std_logic; - pwdata_23 : in std_logic := 'U'; - pwdata_22 : in std_logic := 'U'; - pwdata_0_d0 : in std_logic := 'U'; - pwdata_7 : in std_logic := 'U'; - pwdata_6 : in std_logic := 'U'; - pwdata_5 : in std_logic := 'U'; - pwdata_4 : in std_logic := 'U'; - pwdata_1_d0 : in std_logic := 'U'; - pwdata_18 : in std_logic := 'U'; - pwdata_17 : in std_logic := 'U'; - pwdata_16 : in std_logic := 'U'; - pwdata_15 : in std_logic := 'U'; - pwdata_20 : in std_logic := 'U'; - pwdata_21 : in std_logic := 'U'; - pwdata_14 : in std_logic := 'U'; - pwdata_0_5 : in std_logic := 'U'; - pwdata_0_7 : in std_logic := 'U'; - pwdata_0_8 : in std_logic := 'U'; - pwdata_0_9 : in std_logic := 'U'; - pwdata_0_2 : in std_logic := 'U'; - pwdata_0_1 : in std_logic := 'U'; - pwdata_0_0 : in std_logic := 'U'; - pwdata_0_6 : in std_logic := 'U'; - pwdata_0_11 : in std_logic := 'U'; - hsize : in std_logic_vector(1 downto 0) := (others => 'U'); - romrws_1 : out std_logic; - romrws_3 : out std_logic; - romrws_2 : out std_logic; - hwdata_m_0_3 : in std_logic := 'U'; - hwdata_m_0_2 : in std_logic := 'U'; - hwdata_m_0_0 : in std_logic := 'U'; - psel : in std_logic_vector(0 to 0) := (others => 'U'); - romwidth : out std_logic_vector(1 downto 0); - iosn_100 : in std_logic := 'U'; - iosn_99 : in std_logic := 'U'; - address_c : out std_logic_vector(27 downto 0); - hwdata_m_8 : in std_logic := 'U'; - hwdata_m_7 : in std_logic := 'U'; - hwdata_m_5 : in std_logic := 'U'; - hwdata_m_0_d0 : in std_logic := 'U'; - hwdata_m_13 : in std_logic := 'U'; - data : out std_logic_vector(31 downto 0); - haddr : in std_logic_vector(30 downto 0) := (others => 'U'); - ramwidth : out std_logic_vector(1 downto 0); - htrans : in std_logic_vector(1 downto 0) := (others => 'U'); - iosn_0 : in std_logic_vector(93 to 93) := (others => 'U'); - hsel_i : in std_logic_vector(0 to 0) := (others => 'U'); - romwws : out std_logic_vector(3 downto 0); - prdata_0 : out std_logic; - prdata_1 : out std_logic; - prdata_8 : out std_logic; - prdata_7 : out std_logic; - hrdata : out std_logic_vector(31 downto 0); - hwdata_4 : in std_logic := 'U'; - hwdata_3 : in std_logic := 'U'; - hwdata_8 : in std_logic := 'U'; - hwdata_13 : in std_logic := 'U'; - hwdata_24 : in std_logic := 'U'; - hwdata_23 : in std_logic := 'U'; - hwdata_22 : in std_logic := 'U'; - hwdata_20 : in std_logic := 'U'; - hwdata_10 : in std_logic := 'U'; - hwdata_26 : in std_logic := 'U'; - hwdata_9 : in std_logic := 'U'; - hwdata_16 : in std_logic := 'U'; - hwdata_17 : in std_logic := 'U'; - hwdata_7 : in std_logic := 'U'; - hwdata_30 : in std_logic := 'U'; - hwdata_28 : in std_logic := 'U'; - hwdata_5 : in std_logic := 'U'; - hwdata_31 : in std_logic := 'U'; - hwdata_1 : in std_logic := 'U'; - hwdata_19 : in std_logic := 'U'; - hwdata_29 : in std_logic := 'U'; - hwdata_21 : in std_logic := 'U'; - hwdata_18 : in std_logic := 'U'; - hwdata_0 : in std_logic := 'U'; - hwdata_6 : in std_logic := 'U'; - hwdata_2 : in std_logic := 'U'; - hwdata_27 : in std_logic := 'U'; - hwdata_11 : in std_logic := 'U'; - hwdata_25 : in std_logic := 'U'; - bdrive_i : out std_logic_vector(3 downto 0); - paddr : in std_logic_vector(3 downto 2) := (others => 'U'); - iosn_c : out std_logic; - lclk_c : in std_logic := 'U'; - N_6455 : out std_logic; - N_5062 : out std_logic; - un6_ioen_NE_0 : in std_logic := 'U'; - N_510 : out std_logic; - N_6459 : in std_logic := 'U'; - N_5070 : out std_logic; - bexcen : out std_logic; - brdyen : out std_logic; - ioen : out std_logic; - writen_c : out std_logic; - hwrite_m_0_0 : in std_logic := 'U'; - hwrite : in std_logic := 'U'; - brmw_1 : out std_logic; - N_6550 : out std_logic; - oen_c : out std_logic; - rdata61_2 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - brmw_i : out std_logic; - N_6377 : out std_logic; - rmw : out std_logic; - rstn : in std_logic := 'U'; - read_c : out std_logic; - hready : out std_logic; - N_232_0 : in std_logic := 'U'; - N_6455_0 : out std_logic - ); - end component; - - component grgpio - port( un1_grgpio0_7 : out std_logic; - un1_grgpio0_5 : out std_logic; - gpio_in : in std_logic_vector(7 downto 0) := (others => 'U'); - pwdata_i : in std_logic_vector(7 downto 0) := (others => 'U'); - paddr : in std_logic_vector(5 downto 2) := (others => 'U'); - readdata_2_m : out std_logic_vector(5 to 5); - pwdata_1_0 : in std_logic := 'U'; - pwdata_1_3 : in std_logic := 'U'; - pwdata_1_2 : in std_logic := 'U'; - pwdata_0_5 : in std_logic := 'U'; - pwdata_0_7 : in std_logic := 'U'; - pwdata_0_6 : in std_logic := 'U'; - pwdata_0_2 : in std_logic := 'U'; - pwdata_0_0 : in std_logic := 'U'; - dout : out std_logic_vector(7 downto 0); - psel : in std_logic_vector(11 to 11) := (others => 'U'); - prdata_iv_0_0_d0 : out std_logic; - prdata_iv_0_2 : out std_logic; - prdata_iv_0_0 : out std_logic_vector(2 to 2); - oen_7 : out std_logic; - oen_i : out std_logic_vector(7 downto 0); - paddr_0 : in std_logic_vector(3 downto 2) := (others => 'U'); - lclk_c : in std_logic := 'U'; - N_232_2 : out std_logic; - rdata61_2 : out std_logic; - N_6432 : out std_logic; - rstn : in std_logic := 'U'; - N_6439 : out std_logic; - N_6437 : out std_logic; - N_6436 : out std_logic; - N_6435 : out std_logic; - N_6434 : out std_logic; - rdata60_4 : in std_logic := 'U'; - N_6430 : out std_logic; - rdata59_4 : in std_logic := 'U'; - N_6429 : out std_logic; - N_6428 : out std_logic; - N_6459 : out std_logic; - readdata55_3 : in std_logic := 'U'; - un1_apbi_0 : in std_logic := 'U'; - rdata60_4_0 : in std_logic := 'U'; - N_232_0 : out std_logic; - N_232_1 : out std_logic - ); - end component; - - component OR2B - port( A : in std_logic := 'U'; - B : in std_logic := 'U'; - Y : out std_logic - ); - end component; - - signal rstn, \apbi.pirq[2]\, \apbi.pirq[12]\, - \apbi.pirq[13]\, \apbi.pirq[15]\, \ahbsi.haddr[2]\, - \ahbsi.haddr[3]\, \ahbsi.haddr[4]\, \ahbsi.haddr[5]\, - \ahbsi.haddr[6]\, \ahbsi.haddr[7]\, \ahbsi.haddr[8]\, - \ahbsi.haddr[9]\, \ahbsi.haddr[16]\, \ahbsi.haddr[17]\, - \ahbsi.haddr[18]\, \ahbsi.haddr[20]\, \ahbsi.haddr[21]\, - \ahbsi.haddr[22]\, \ahbsi.haddr[23]\, \ahbsi.haddr[26]\, - \ahbsi.haddr[27]\, \ahbsi.haddr[28]\, \ahbsi.haddr[30]\, - \ahbsi.hsel_i[0]\, \ahbsi.htrans[0]\, \ahbsi.htrans[1]\, - \ahbsi.hsize[1]\, \ahbsi.hburst[0]\, \ahbsi.hwdata[0]\, - \ahbsi.hwdata[1]\, \ahbsi.hwdata[2]\, \ahbsi.hwdata[3]\, - \ahbsi.hwdata[4]\, \ahbsi.hwdata[5]\, \ahbsi.hwdata[6]\, - \ahbsi.hwdata[7]\, \ahbsi.hwdata[8]\, \ahbsi.hwdata[9]\, - \ahbsi.hwdata[10]\, \ahbsi.hwdata[11]\, - \ahbsi.hwdata[12]\, \ahbsi.hwdata[13]\, - \ahbsi.hwdata[14]\, \ahbsi.hwdata[15]\, - \ahbsi.hwdata[16]\, \ahbsi.hwdata[17]\, - \ahbsi.hwdata[18]\, \ahbsi.hwdata[19]\, - \ahbsi.hwdata[20]\, \ahbsi.hwdata[21]\, - \ahbsi.hwdata[22]\, \ahbsi.hwdata[23]\, - \ahbsi.hwdata[24]\, \ahbsi.hwdata[25]\, - \ahbsi.hwdata[26]\, \ahbsi.hwdata[27]\, - \ahbsi.hwdata[28]\, \ahbsi.hwdata[29]\, - \ahbsi.hwdata[30]\, \ahbsi.hwdata[31]\, \ahbmo_0.hbusreq\, - \irqo_0.irl[0]\, \irqo_0.irl[1]\, \irqo_0.irl[2]\, - \irqo_0.irl[3]\, \dcomgen.un1_dcom0[12]\, - \dcomgen.un1_dcom0[13]\, \dcomgen.un1_dcom0[14]\, - \dcomgen.un1_dcom0[15]\, \dcomgen.un1_dcom0[16]\, - \dcomgen.un1_dcom0[17]\, \dcomgen.un1_dcom0[18]\, - \dcomgen.un1_dcom0[19]\, \ahbmo_1.haddr[0]\, - \ahbmo_1.haddr[1]\, \ahbmo_1.haddr[2]\, - \ahbmo_1.haddr[3]\, \ahbmo_1.haddr[4]\, - \ahbmo_1.haddr[5]\, \ahbmo_1.haddr[6]\, - \ahbmo_1.haddr[7]\, \ahbmo_1.haddr[8]\, - \ahbmo_1.haddr[9]\, \ahbmo_1.haddr[10]\, - \ahbmo_1.haddr[11]\, \ahbmo_1.haddr[12]\, - \ahbmo_1.haddr[13]\, \ahbmo_1.haddr[14]\, - \ahbmo_1.haddr[15]\, \ahbmo_1.haddr[16]\, - \ahbmo_1.haddr[17]\, \ahbmo_1.haddr[18]\, - \ahbmo_1.haddr[19]\, \ahbmo_1.haddr[20]\, - \ahbmo_1.haddr[21]\, \ahbmo_1.haddr[22]\, - \ahbmo_1.haddr[23]\, \ahbmo_1.haddr[24]\, - \ahbmo_1.haddr[25]\, \ahbmo_1.haddr[26]\, - \ahbmo_1.haddr[27]\, \ahbmo_1.haddr[28]\, - \ahbmo_1.haddr[29]\, \ahbmo_1.haddr[30]\, - \ahbmo_1.haddr[31]\, \ahbmo_1.hwrite\, - \ahbmo_1.hwdata[0]\, \ahbmo_1.hwdata[1]\, - \ahbmo_1.hwdata[2]\, \ahbmo_1.hwdata[3]\, - \ahbmo_1.hwdata[4]\, \ahbmo_1.hwdata[5]\, - \ahbmo_1.hwdata[6]\, \ahbmo_1.hwdata[7]\, - \ahbmo_1.hwdata[8]\, \ahbmo_1.hwdata[9]\, - \ahbmo_1.hwdata[10]\, \ahbmo_1.hwdata[11]\, - \ahbmo_1.hwdata[12]\, \ahbmo_1.hwdata[13]\, - \ahbmo_1.hwdata[14]\, \ahbmo_1.hwdata[15]\, - \ahbmo_1.hwdata[16]\, \ahbmo_1.hwdata[17]\, - \ahbmo_1.hwdata[18]\, \ahbmo_1.hwdata[19]\, - \ahbmo_1.hwdata[20]\, \ahbmo_1.hwdata[21]\, - \ahbmo_1.hwdata[22]\, \ahbmo_1.hwdata[23]\, - \ahbmo_1.hwdata[24]\, \ahbmo_1.hwdata[25]\, - \ahbmo_1.hwdata[26]\, \ahbmo_1.hwdata[27]\, - \ahbmo_1.hwdata[28]\, \ahbmo_1.hwdata[29]\, - \ahbmo_1.hwdata[30]\, \ahbmo_1.hwdata[31]\, - \memo.address[28]\, \memo.address[29]\, - \memo.address[30]\, \memo.address[31]\, \memo.data[0]\, - \memo.data[1]\, \memo.data[2]\, \memo.data[3]\, - \memo.data[4]\, \memo.data[5]\, \memo.data[6]\, - \memo.data[7]\, \memo.data[8]\, \memo.data[9]\, - \memo.data[10]\, \memo.data[11]\, \memo.data[12]\, - \memo.data[13]\, \memo.data[14]\, \memo.data[15]\, - \memo.data[16]\, \memo.data[17]\, \memo.data[18]\, - \memo.data[19]\, \memo.data[20]\, \memo.data[21]\, - \memo.data[22]\, \memo.data[23]\, \memo.data[24]\, - \memo.data[25]\, \memo.data[26]\, \memo.data[27]\, - \memo.data[28]\, \memo.data[29]\, \memo.data[30]\, - \memo.data[31]\, \ahbso_0.hready\, \ahbso_0.hresp[0]\, - \ahbso_0.hrdata[0]\, \ahbso_0.hrdata[1]\, - \ahbso_0.hrdata[2]\, \ahbso_0.hrdata[3]\, - \ahbso_0.hrdata[4]\, \ahbso_0.hrdata[5]\, - \ahbso_0.hrdata[6]\, \ahbso_0.hrdata[7]\, - \ahbso_0.hrdata[8]\, \ahbso_0.hrdata[9]\, - \ahbso_0.hrdata[10]\, \ahbso_0.hrdata[11]\, - \ahbso_0.hrdata[12]\, \ahbso_0.hrdata[13]\, - \ahbso_0.hrdata[14]\, \ahbso_0.hrdata[15]\, - \ahbso_0.hrdata[16]\, \ahbso_0.hrdata[17]\, - \ahbso_0.hrdata[18]\, \ahbso_0.hrdata[19]\, - \ahbso_0.hrdata[20]\, \ahbso_0.hrdata[21]\, - \ahbso_0.hrdata[22]\, \ahbso_0.hrdata[23]\, - \ahbso_0.hrdata[24]\, \ahbso_0.hrdata[25]\, - \ahbso_0.hrdata[26]\, \ahbso_0.hrdata[27]\, - \ahbso_0.hrdata[28]\, \ahbso_0.hrdata[29]\, - \ahbso_0.hrdata[30]\, \ahbso_0.hrdata[31]\, - \ahbso_1.hready\, \ahbso_1.hrdata[0]\, - \ahbso_1.hrdata[1]\, \ahbso_1.hrdata[2]\, - \ahbso_1.hrdata[3]\, \ahbso_1.hrdata[4]\, - \ahbso_1.hrdata[5]\, \ahbso_1.hrdata[6]\, - \ahbso_1.hrdata[7]\, \ahbso_1.hrdata[8]\, - \ahbso_1.hrdata[9]\, \ahbso_1.hrdata[10]\, - \ahbso_1.hrdata[11]\, \ahbso_1.hrdata[12]\, - \ahbso_1.hrdata[13]\, \ahbso_1.hrdata[14]\, - \ahbso_1.hrdata[15]\, \ahbso_1.hrdata[16]\, - \ahbso_1.hrdata[17]\, \ahbso_1.hrdata[18]\, - \ahbso_1.hrdata[19]\, \ahbso_1.hrdata[20]\, - \ahbso_1.hrdata[21]\, \ahbso_1.hrdata[22]\, - \ahbso_1.hrdata[23]\, \ahbso_1.hrdata[24]\, - \ahbso_1.hrdata[25]\, \ahbso_1.hrdata[26]\, - \ahbso_1.hrdata[27]\, \ahbso_1.hrdata[28]\, - \ahbso_1.hrdata[29]\, \ahbso_1.hrdata[30]\, - \ahbso_1.hrdata[31]\, \apbi.penable\, \apbi.paddr[2]\, - \apbi.paddr[3]\, \apbi.paddr[4]\, \apbi.paddr[5]\, - \apbi.paddr[6]\, \apbi.paddr[7]\, \apbi.pwrite\, - \apbi.pwdata[0]\, \apbi.pwdata[1]\, \apbi.pwdata[2]\, - \apbi.pwdata[3]\, \apbi.pwdata[4]\, \apbi.pwdata[5]\, - \apbi.pwdata[6]\, \apbi.pwdata[7]\, \apbi.pwdata[8]\, - \apbi.pwdata[9]\, \apbi.pwdata[10]\, \apbi.pwdata[11]\, - \apbi.pwdata[12]\, \apbi.pwdata[13]\, \apbi.pwdata[14]\, - \apbi.pwdata[15]\, \apbi.pwdata[16]\, \apbi.pwdata[17]\, - \apbi.pwdata[18]\, \apbi.pwdata[19]\, \apbi.pwdata[20]\, - \apbi.pwdata[21]\, \apbi.pwdata[22]\, \apbi.pwdata[23]\, - \apbi.pwdata[24]\, \apbi.pwdata[25]\, \apbi.pwdata[26]\, - \apbi.pwdata[27]\, \apbi.pwdata[28]\, \apbi.pwdata[29]\, - \apbi.pwdata[30]\, \apbi.pwdata[31]\, \ua1.un1_uart1[36]\, - \irqi_0.irl[0]\, \irqi_0.irl[1]\, \irqi_0.irl[2]\, - \irqi_0.irl[3]\, \gpioo.dout[0]\, \gpioo.dout[1]\, - \gpioo.dout[2]\, \gpioo.dout[3]\, \gpioo.dout[4]\, - \gpioo.dout[5]\, \gpioo.dout[6]\, \gpioo.dout[7]\, - \gpioo.oen[7]\, \gpio0.un1_grgpio0[69]\, - \gpio0.un1_grgpio0[71]\, \ahbso_7.hready\, - \ahbso_7.hrdata[0]\, \ahbso_7.hrdata[1]\, - \ahbso_7.hrdata[2]\, \ahbso_7.hrdata[3]\, - \ahbso_7.hrdata[4]\, \ahbso_7.hrdata[5]\, - \ahbso_7.hrdata[6]\, \ahbso_7.hrdata[7]\, - \ahbso_7.hrdata[8]\, \ahbso_7.hrdata[9]\, - \ahbso_7.hrdata[10]\, \ahbso_7.hrdata[11]\, - \ahbso_7.hrdata[12]\, \ahbso_7.hrdata[13]\, - \ahbso_7.hrdata[14]\, \ahbso_7.hrdata[15]\, - \ahbso_7.hrdata[16]\, \ahbso_7.hrdata[17]\, - \ahbso_7.hrdata[18]\, \ahbso_7.hrdata[19]\, - \ahbso_7.hrdata[20]\, \ahbso_7.hrdata[21]\, - \ahbso_7.hrdata[22]\, \ahbso_7.hrdata[23]\, - \ahbso_7.hrdata[24]\, \ahbso_7.hrdata[25]\, - \ahbso_7.hrdata[26]\, \ahbso_7.hrdata[27]\, - \ahbso_7.hrdata[28]\, \ahbso_7.hrdata[29]\, - \ahbso_7.hrdata[30]\, \ahbso_7.hrdata[31]\, - \apbo_13.prdata[0]\, \apbo_13.prdata[1]\, - \apbo_13.prdata[2]\, \apbo_13.prdata[3]\, - \apbo_13.prdata[4]\, \apbo_13.prdata[5]\, - \apbo_13.prdata[6]\, \apbo_13.prdata[7]\, - \apbo_13.prdata[8]\, \apbo_13.prdata[9]\, - \apbo_13.prdata[10]\, \apbo_13.prdata[11]\, - \apbo_13.prdata[12]\, \apbo_13.prdata[13]\, - \apbo_13.prdata[14]\, \apbo_13.prdata[15]\, - \apbo_13.prdata[16]\, \apbo_13.prdata[17]\, - \apbo_13.prdata[18]\, \apbo_13.prdata[19]\, - \apbo_13.prdata[20]\, \apbo_13.prdata[21]\, - \apbo_13.prdata[22]\, \apbo_13.prdata[23]\, - \apbo_13.prdata[24]\, \apbo_13.prdata[25]\, - \apbo_13.prdata[26]\, \apbo_13.prdata[27]\, - \apbo_13.prdata[28]\, \apbo_13.prdata[29]\, - \apbo_13.prdata[30]\, \apbo_13.prdata[31]\, - \apbo_15.prdata[0]\, \apbo_15.prdata[1]\, - \apbo_15.prdata[2]\, \apbo_15.prdata[3]\, - \apbo_15.prdata[4]\, \apbo_15.prdata[5]\, - \apbo_15.prdata[6]\, \apbo_15.prdata[7]\, - \apbo_15.prdata[8]\, \apbo_15.prdata[9]\, - \apbo_15.prdata[10]\, \apbo_15.prdata[11]\, - \apbo_15.prdata[12]\, \apbo_15.prdata[13]\, - \apbo_15.prdata[14]\, \apbo_15.prdata[15]\, - \apbo_15.prdata[16]\, \apbo_15.prdata[17]\, - \apbo_15.prdata[18]\, \apbo_15.prdata[19]\, - \apbo_15.prdata[20]\, \apbo_15.prdata[21]\, - \apbo_15.prdata[22]\, \apbo_15.prdata[23]\, - \apbo_15.prdata[24]\, \apbo_15.prdata[25]\, - \apbo_15.prdata[26]\, \apbo_15.prdata[27]\, - \apbo_15.prdata[28]\, \apbo_15.prdata[29]\, - \apbo_15.prdata[30]\, \apbo_15.prdata[31]\, - \coarse_time[0]\, \apbo_14.prdata[0]\, - \apbo_14.prdata[1]\, \apbo_14.prdata[2]\, - \apbo_14.prdata[3]\, \apbo_14.prdata[4]\, - \apbo_14.prdata[5]\, \apbo_14.prdata[6]\, - \apbo_14.prdata[7]\, \apbo_14.prdata[8]\, - \apbo_14.prdata[9]\, \apbo_14.prdata[10]\, - \apbo_14.prdata[11]\, \apbo_14.prdata[12]\, - \apbo_14.prdata[13]\, \apbo_14.prdata[14]\, - \apbo_14.prdata[15]\, \apbo_14.prdata[16]\, - \apbo_14.prdata[17]\, \apbo_14.prdata[18]\, - \apbo_14.prdata[19]\, \apbo_14.prdata[20]\, - \apbo_14.prdata[21]\, \apbo_14.prdata[22]\, - \apbo_14.prdata[23]\, \apbo_14.prdata[24]\, - \apbo_14.prdata[25]\, \apbo_14.prdata[26]\, - \apbo_14.prdata[27]\, \apbo_14.prdata[28]\, - \apbo_14.prdata[29]\, \apbo_14.prdata[30]\, - \apbo_14.prdata[31]\, \ahbmo_3.htrans[0]\, - \ahbmo_3.htrans[1]\, \ahbmo_3.haddr[0]\, - \ahbmo_3.haddr[1]\, \ahbmo_3.haddr[2]\, - \ahbmo_3.haddr[3]\, \ahbmo_3.haddr[4]\, - \ahbmo_3.haddr[5]\, \ahbmo_3.haddr[6]\, - \ahbmo_3.haddr[7]\, \ahbmo_3.haddr[8]\, - \ahbmo_3.haddr[9]\, \ahbmo_3.haddr[10]\, - \ahbmo_3.haddr[11]\, \ahbmo_3.haddr[12]\, - \ahbmo_3.haddr[13]\, \ahbmo_3.haddr[14]\, - \ahbmo_3.haddr[15]\, \ahbmo_3.haddr[16]\, - \ahbmo_3.haddr[17]\, \ahbmo_3.haddr[18]\, - \ahbmo_3.haddr[19]\, \ahbmo_3.haddr[20]\, - \ahbmo_3.haddr[21]\, \ahbmo_3.haddr[22]\, - \ahbmo_3.haddr[23]\, \ahbmo_3.haddr[24]\, - \ahbmo_3.haddr[25]\, \ahbmo_3.haddr[26]\, - \ahbmo_3.haddr[27]\, \ahbmo_3.haddr[28]\, - \ahbmo_3.haddr[29]\, \ahbmo_3.haddr[30]\, - \ahbmo_3.haddr[31]\, \ahbmo_3.hwrite\, \ahbmo_3.hsize[0]\, - \ahbmo_3.hsize[1]\, \ahbmo_3.hburst[0]\, - \ahbmo_3.hburst[1]\, \ahbmo_3.hburst[2]\, - \sr1.r.mcfg1.ioen\, \sr1.r.mcfg1.brdyen\, - \sr1.r.mcfg2.rmw\, \sr1.r.mcfg1.bexcen\, - \sr1.r.mcfg2.rambanksz[0]\, \sr1.r.mcfg2.rambanksz[1]\, - \sr1.r.mcfg2.rambanksz[3]\, \sr1.r.mcfg2.ramwidth[1]\, - \sr1.r.mcfg1.iows[2]\, \sr1.r.mcfg1.iows[3]\, - \sr1.r.mcfg2.ramwidth[0]\, \sr1.r.mcfg2.ramrws[1]\, - \sr1.r.mcfg2.ramwws[0]\, \sr1.r.mcfg2.ramwws[1]\, - \sr1.r.mcfg1.romrws[1]\, \sr1.r.mcfg1.romrws[2]\, - \sr1.r.mcfg1.romrws[3]\, \sr1.r.mcfg1.romwws[0]\, - \sr1.r.mcfg1.romwws[1]\, \sr1.r.mcfg1.romwws[2]\, - \sr1.r.mcfg1.romwws[3]\, \sr1.r.mcfg1.romwidth[0]\, - \sr1.r.mcfg1.romwidth[1]\, \irqo_0.intack\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.address[0]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.address[1]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[5]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[8]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[10]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[13]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[24]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[29]\, - \l3.cpu.0.u0.p0.c0mmu.mcdi.size[0]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[8]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[10]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[13]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[24]\, - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[29]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un59_nbo\, - \ahb0.comb.arb_1\, lclk_i, \sr1.iosn[93]\, - \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d\, \state_RNIFS55[4]\, - \sr1.ctrl.un1_r.brmw_i\, N_78, N_262, N_264, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.v.werr_2_m_0\, N_6377, - \ahbmo_0.hwdata[6]\, N_6550, \ahbmo_0.hwdata[12]\, - \ahbmo_3.hwdata[0]\, \ahbmo_3.hwdata[1]\, - \ahbmo_3.hwdata[2]\, \ahbmo_3.hwdata[3]\, - \ahbmo_3.hwdata[4]\, \ahbmo_3.hwdata[5]\, - \ahbmo_3.hwdata[6]\, \ahbmo_3.hwdata[7]\, - \ahbmo_3.hwdata[8]\, \ahbmo_3.hwdata[9]\, - \ahbmo_3.hwdata[10]\, \ahbmo_3.hwdata[11]\, - \ahbmo_3.hwdata[12]\, \ahbmo_3.hwdata[13]\, - \ahbmo_3.hwdata[14]\, \ahbmo_3.hwdata[15]\, - \ahbmo_3.hwdata[16]\, \ahbmo_3.hwdata[17]\, - \ahbmo_3.hwdata[18]\, \ahbmo_3.hwdata[19]\, - \ahbmo_3.hwdata[20]\, \ahbmo_3.hwdata[21]\, - \ahbmo_3.hwdata[22]\, \ahbmo_3.hwdata[23]\, - \ahbmo_3.hwdata[24]\, \ahbmo_3.hwdata[25]\, - \ahbmo_3.hwdata[26]\, \ahbmo_3.hwdata[27]\, - \ahbmo_3.hwdata[28]\, \ahbmo_3.hwdata[29]\, - \ahbmo_3.hwdata[30]\, \ahbmo_3.hwdata[31]\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.IdlePhase\, - \apb0.N_770\, \gpt.timer0.r.timers_2.value[0]\, - \gpt.timer0.r.timers_2.value[6]\, \gpt.timer0.r.dishlt\, - \gpt.timer0.r.reload[6]\, \gpt.timer0.r.reload[7]\, - \gpt.timer0.r.timers_2.reload[4]\, - \gpt.timer0.r.timers_2.reload[5]\, - \gpt.timer0.r.timers_2.reload[6]\, - \gpt.timer0.r.timers_2.reload[7]\, - \gpt.timer0.r.timers_2.reload[8]\, - \gpt.timer0.r.timers_2.reload[10]\, - \gpt.timer0.r.timers_2.reload[11]\, - \gpt.timer0.r.timers_2.reload[12]\, - \gpt.timer0.r.timers_2.reload[28]\, - \gpt.timer0.r.scaler[4]\, \irqctrl.irqctrl0.r.ilevel[4]\, - \irqctrl.irqctrl0.r.ilevel[5]\, - \irqctrl.irqctrl0.r.ilevel[6]\, - \irqctrl.irqctrl0.r.ilevel[7]\, - \irqctrl.irqctrl0.r.ilevel[8]\, - \irqctrl.irqctrl0.r.ilevel[10]\, - \irqctrl.irqctrl0.r.ilevel[12]\, - \irqctrl.irqctrl0.r.iforce_0[5]\, - \irqctrl.irqctrl0.r.iforce_0[6]\, - \irqctrl.irqctrl0.r.iforce_0[7]\, - \irqctrl.irqctrl0.r.iforce_0[10]\, - \irqctrl.irqctrl0.r.iforce_0[12]\, - \irqctrl.irqctrl0.r.ipend[11]\, \ua1.uart1.r.tcnt[0]\, - \ua1.uart1.r.tcnt[1]\, \ua1.uart1.r.rcnt[0]\, - \ua1.uart1.r.rcnt[1]\, \ua1.uart1.r.paren\, - \ua1.uart1.r.delayirqen\, \ua1.uart1.r.breakirqen\, - \ua1.uart1.r.tsemptyirqen\, \ua1.uart1.r.brate[0]\, - \ua1.uart1.r.brate[6]\, \ua1.uart1.r.brate[7]\, - \ua1.uart1.r.brate[8]\, \ua1.uart1.r.brate[9]\, - \ua1.uart1.r.brate[10]\, \ua1.uart1.r.frame\, - \ua1.uart1.N_156\, \ahbmo_1.hbusreq_i_3\, - \ahbmi.hrdata[0]\, \ahbmi.hrdata[1]\, \ahbmi.hrdata[2]\, - \ahbmi.hrdata[3]\, \ahbmi.hrdata[4]\, \ahbmi.hrdata[5]\, - \ahbmi.hrdata[7]\, \ahbmi.hrdata[8]\, \ahbmi.hrdata[9]\, - \ahbmi.hrdata[10]\, \ahbmi.hrdata[11]\, - \ahbmi.hrdata[12]\, \ahbmi.hrdata[13]\, - \ahbmi.hrdata[14]\, \ahbmi.hrdata[15]\, - \ahbmi.hrdata[16]\, \ahbmi.hrdata[17]\, - \ahbmi.hrdata[21]\, \ahbmi.hrdata[22]\, - \ahbmi.hrdata[23]\, \ahbmi.hrdata[24]\, - \ahbmi.hrdata[26]\, \ahbmi.hrdata[27]\, - \ahbmi.hrdata[28]\, \ahbmi.hrdata[29]\, - \ahbmi.hrdata[31]\, \ahbmi.hrdata[6]\, \dbgo_0.error_i_2\, - \data_in[0]\, \data_in[1]\, \data_in[2]\, \data_in[3]\, - \data_in[4]\, \data_in[5]\, \data_in[6]\, \data_in[7]\, - \data_in[8]\, \data_in[9]\, \data_in[10]\, \data_in[11]\, - \data_in[12]\, \data_in[13]\, \data_in[14]\, - \data_in[15]\, \data_in[16]\, \data_in[17]\, - \data_in[18]\, \data_in[19]\, \data_in[20]\, - \data_in[21]\, \data_in[22]\, \data_in[23]\, - \data_in[24]\, \data_in[25]\, \data_in[26]\, - \data_in[27]\, \data_in[28]\, \data_in[29]\, - \data_in[30]\, \data_in[31]\, \gpio_in[0]\, \gpio_in[1]\, - \gpio_in[2]\, \gpio_in[3]\, \gpio_in[4]\, \gpio_in[5]\, - \gpio_in[6]\, \gpio_in[7]\, rstraw_c, clk_c, - \address_c[0]\, \address_c[1]\, \address_c[2]\, - \address_c[3]\, \address_c[4]\, \address_c[5]\, - \address_c[6]\, \address_c[7]\, \address_c[8]\, - \address_c[9]\, \address_c[10]\, \address_c[11]\, - \address_c[12]\, \address_c[13]\, \address_c[14]\, - \address_c[15]\, \address_c[16]\, \address_c[17]\, - \address_c[18]\, \address_c[19]\, \address_c[20]\, - \address_c[21]\, \address_c[22]\, \address_c[23]\, - \address_c[24]\, \address_c[25]\, \address_c[26]\, - \address_c[27]\, dsutx_c, dsurx_c, txd1_c, rxd1_c, - \ramsn_c[0]\, \ramsn_c[1]\, \ramsn_c[2]\, \ramsn_c[3]\, - \ramoen_c[0]\, \ramoen_c[1]\, \ramoen_c[2]\, - \ramoen_c[3]\, \rwen_c[0]\, \rwen_c[1]\, \rwen_c[2]\, - \rwen_c[3]\, oen_c, writen_c, read_c, iosn_c, - \romsn_c[0]\, \romsn_c[1]\, lclk_c, nBWa_c, nBWb_c, - nBWc_c, nBWd_c, nBWE_c, \VCC\, nCE1_c, CE2_c, nCE3_c, - \GND\, clk49_152MHz_c, \sdo_adc_c[0]\, \sdo_adc_c[1]\, - \sdo_adc_c[2]\, \sdo_adc_c[3]\, \sdo_adc_c[4]\, - \sdo_adc_c[5]\, \sdo_adc_c[6]\, \sdo_adc_c[7]\, cnv_ch1_c, - sck_ch1_c, Bias_Fails_c, \ahbsi.hsize[0]\, - \ahbsi.haddr[0]\, \ahbmo_3.hbusreq_i_3\, \sr1.iosn[100]\, - \sr1.iosn_1[101]\, \ahbsi.hmbsel_1[0]\, \ahbsi.haddr[1]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un60_nbo\, N_5054, - \ahbmo_0.htrans[1]\, \ahbsi.hmbsel[0]\, - \ahbmo_1.htrans[1]\, \ahbmi.hgrant[3]\, - \l3.cpu.0.u0.p0.c0mmu.a0.htrans_0_sqmuxa_2\, - \l3.cpu.0.u0.p0.c0mmu.a0.v.lb_0_sqmuxa_1\, - \ahbmi.hresp[0]\, \ahb0.bco_msb_1[1]\, - \ahb0.bco_msb_1_m[1]\, \ahb0.l1_0_m[1]\, - \ahb0.un1_nhmaster_0_sqmuxa_1\, - \ahb0.comb.nhmaster_1_i[0]\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.un1_dmain_6\, - \ahbmo_0.hlock\, \ahbmo_0.hwdata[18]\, - \ahbso_6.hrdata[26]\, \ahbso_6.hrdata[11]\, - \ahbsi.hwdata_m_0[15]\, \ahbsi.hwdata_m[15]\, N_546, - N_466, \ahbmo_0.hwdata[3]\, \ahbmo_0.haddr[17]\, - \ahbmo_0.haddr[16]\, \ahbmo_0.haddr[6]\, - \ahbmo_0.haddr[7]\, \ahbmo_0.haddr[27]\, - \ahbmo_0.haddr[11]\, \ahbsi.haddr[11]\, \ahbmi.hgrant[0]\, - \ahbso_6.hrdata[28]\, \ahbso_6.hrdata[27]\, - \ahbso_6.hrdata[23]\, \ahbso_6.hrdata[22]\, - \ahbso_6.hrdata[21]\, \ahbso_6.hrdata[15]\, - \ahbso_6.hrdata[14]\, \ahbso_6.hrdata[13]\, - \ahbso_6.hrdata[4]\, \ahbso_6.hrdata[3]\, - \ahbso_6.hrdata[2]\, \ahbso_6.hrdata[1]\, - \ahbso_6.hrdata[0]\, \ahbmo_0.haddr[31]\, - \ahbmo_0.haddr[30]\, \ahbmi.hgrant[1]\, - \l3.cpu.0.u0.p0.c0mmu.a0.hsize_5[1]\, \apbo_0.prdata[20]\, - \apb0.N_78\, \apb0.N_749\, \apb0.N_750\, \apb0.N_769\, - \apb0.N_773\, \apb0.N_796\, \apb0.N_116\, - \gpt.timer0.N_228\, \gpt.timer0.r.timers_2.value_m[20]\, - \gpt.timer0.r.timers_2.reload_m[20]\, \gpt.timer0.N_240\, - \lfrtimemanagement_0.r.ctrl2\, \ua1.uart1.uartop.rdata59\, - \ua1.uart1.uartop.rdata60\, \ua1.uart1.uartop.rdata61\, - \ua1.uart1.N_232\, \apbi.psel_1[7]\, \apbi.psel[11]\, - N_6455, \apbo_3.prdata[31]\, - \dcomgen.dcom0.dcom_uart0.N_127\, \apbo_3.prdata[14]\, - \lfrtimemanagement_0.un1_apbi_7_1\, \apbo_1.prdata[31]\, - \irqctrl.irqctrl0.N_898\, - \irqctrl.irqctrl0.prdata_1_sqmuxa\, - \irqctrl.irqctrl0.prdata_0_sqmuxa\, - \gpt.timer0.comb.readdata55\, - \gpt.timer0.comb.readdata55_3\, - \gpt.timer0.comb.2.readdata51_1\, - \ua1.uart1.uartop.rdata61_2\, - \dcomgen.dcom0.dcom_uart0.N_335\, \ua1.uart1.N_227\, - \ua1.uart1.uartop.rdata60_1\, - \gpt.timer0.comb.1.un1_apbi_2\, - \ua1.uart1.uartop.rdata62_3\, - \ua1.uart1.uartop.rdata59_4\, \ua1.uart1.rdata_3_sqmuxa\, - \ua1.uart1.uartop.thempty_1_m\, - \ua1.uart1.rdata_4_sqmuxa\, - \dcomgen.dcom0.dcom_uart0.N_330\, \apbo_1.prdata[28]\, - \apbo_1.prdata[22]\, \ua1.uart1.rdata_0_sqmuxa\, - \ua1.uart1.uartop.un1_r.tcnt_i\, - \ua1.uart1.uartop.rdata_2[0]\, \ua1.uart1.r.debug_m\, - \ua1.uart1.uartop.rdata_17_m[0]\, N_5062, - \ahb0.comb.1.4.un51_ioen_NE\, \sr1.ctrl.brmw_1\, - \ahb0.comb.7.4.un315_ioen_NE\, \sr1.iosn[101]\, - \ahbsi.hwrite\, \ahbsi.haddr[29]\, \ahbsi.hburst[2]\, - \ahbsi.hburst[1]\, \apbo_7.prdata[5]\, - \ua1.uart1.uartop.rdata_2_m[5]\, \ua1.uart1.r.parerr_m\, - \ua1.uart1.r.brate_m[5]\, - \ua1.uart1.uartop.rdata_17_m[5]\, - \irqctrl.irqctrl0.N_365\, \irqctrl.irqctrl0.N_367\, - \gpt.timer0.comb.1.readdata_9[5]\, - \gpt.timer0.r.scaler_m[5]\, \gpt.timer0.r.reload_m[5]\, - \gpt.timer0.comb.readdata56\, - \gpt.timer0.r.timers_2.value_m[5]\, - \gpt.timer0.r.timers_2.chain_m\, - \gpio0.grgpio0.comb.readdata_2_m[5]\, \ahbsi.haddr[13]\, - \ahbmo_0.haddr[13]\, \lfrtimemanagement_0.un1_apbi_8\, - \ahbmo_0.haddr[28]\, \ahbmo_0.haddr[2]\, - \dcomgen.dcom0.dcom_uart0.N_331\, - \ua1.uart1.uartop.rdata60_4\, \gpt.timer0.r.reload_m[3]\, - \gpt.timer0.comb.readdata57\, \ua1.uart1.uartop.rdata62\, - \irqctrl.irqctrl0.N_863\, \irqctrl.irqctrl0.N_865\, - \gpt.timer0.r.reload_m[2]\, N_6432, - \gpt.timer0.comb.1.readdata_9[0]\, - \gpt.timer0.r.timers_2.enable_m\, - \gpt.timer0.r.reload_m[0]\, \gpt.timer0.r.scaler_m[0]\, - \gpt.timer0.r.timers_2.reload_m[0]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.hwrite_1_m_0\, - \ahbmo_0.hwdata[17]\, \dcomgen.dcom0.dcom_uart0.N_86\, - \ua1.uart1.uartop.rhalffull_1_m\, - \ua1.uart1.r.extclken_m\, \ua1.uart1.r.tfifoirqen_m\, - \ua1.uart1.r.rfifoirqen_m\, - \ua1.uart1.uartop.rdata_17_m[4]\, \apbi.pirq[8]\, - \apbi.pirq[9]\, \gpt.timer0.r.timers_2.value_m[12]\, - \apbo_3.prdata[16]\, \apbo_3.prdata[18]\, - \gpt.timer0.r.timers_2.value_m[22]\, - \gpt.timer0.r.timers_2.value_m[26]\, - \gpt.timer0.r.timers_2.value_m[28]\, \apbo_3.prdata[30]\, - \gpt.timer0.r.timers_2.value_m[11]\, \apbo_3.prdata[17]\, - \apbo_3.prdata[19]\, \apbo_3.prdata[25]\, - \apbo_3.prdata[29]\, \gpt.timer0.r.timers_2.value_m[10]\, - \gpt.timer0.r.timers_2.value_m[24]\, - \gpt.timer0.r.timers_2.value_m[15]\, - \gpt.timer0.r.timers_2.value_m[21]\, - \gpt.timer0.r.timers_2.reload_m[21]\, - \gpt.timer0.comb.1.readdata_9[27]\, - \gpt.timer0.r.timers_2.value_m[27]\, - \gpt.timer0.r.timers_2.reload_m[27]\, - \gpt.timer0.r.timers_2.value_m[13]\, \apbo_3.prdata[23]\, - \apbi.psel[15]\, \ahbsi.hwdata_m_0[14]\, - \ahbsi.hwdata_m[14]\, N_6430, N_6428, N_6429, N_6436, - N_6434, N_6435, N_6439, N_6437, \ahbsi.hwdata_m[7]\, - \ahbsi.hwdata_m_0[12]\, \ahbsi.hwdata_m[12]\, N_468, - N_463, N_461, N_459, N_458, N_510, \ahbmo_0.hwdata[4]\, - \ahbsi.hwdata_m[20]\, \ahbmo_0.hwdata[31]\, - \ahbmo_0.hwdata[26]\, \ahbmo_0.hwdata[15]\, - \ahbmo_0.hwdata[7]\, N_139, N_138, \ahbmo_0.hwdata[16]\, - \apbi.psel[0]\, \ahbmo_0.haddr[19]\, \ahbsi.haddr[19]\, - \ahbsi.haddr[15]\, \ahbmo_0.haddr[15]\, - \ahbmo_0.haddr[14]\, \ahbsi.haddr[14]\, - \ahbmo_0.haddr[20]\, \ahbmo_0.haddr[5]\, N_6459, - \ahbmo_0.haddr[8]\, \apbo_0.prdata[21]\, - \apbo_0.prdata[28]\, \apbo_0.prdata[27]\, - \ahbsi.haddr[25]\, \ahbsi.haddr[24]\, \ahbmo_0.haddr[22]\, - \ahbmo_0.haddr[12]\, \ahbsi.haddr[12]\, N_5070, - \ahbmo_0.haddr[3]\, \ahbmo_0.haddr[9]\, - \ahbmo_0.haddr[10]\, \ahbsi.haddr[10]\, - \ahbmo_0.hwdata[30]\, \ahbmo_0.hwdata[28]\, - \ahbmo_0.hwdata[14]\, \ahbso_6.hrdata[25]\, - \ahbso_6.hrdata[9]\, \ahbmo_0.haddr[25]\, - \ahbmo_0.haddr[24]\, \ahbmo_0.haddr[21]\, - \ahbmo_0.haddr[29]\, \gpt.timer0.r.timers_2.reload_m[9]\, - \gpt.timer0.r.timers_2.value_m[9]\, \gpt.timer0.N_217\, - \gpt.timer0.r.timers_2.value_m[7]\, - \gpt.timer0.r.scaler_m[7]\, \gpt.timer0.N_229\, - \gpt.timer0.N_215\, \gpt.timer0.N_218\, - \gpt.timer0.r.scaler_m[6]\, - \gpt.timer0.r.timers_2.value_m[8]\, \gpt.timer0.N_216\, - \gpt.timer0.N_214\, \gpt.timer0.r.timers_2.irqpen_m\, - \gpt.timer0.comb.1.readdata_9[4]\, - \gpt.timer0.r.timers_2.value_m[4]\, - \gpt.timer0.r.reload_m[4]\, \gpt.timer0.N_219\, - \gpt.timer0.N_236\, \gpt.timer0.N_220\, - \gpt.timer0.comb.1.readdata_9_i_m[1]\, - \gpt.timer0.r.scaler_i_m[1]\, \irqctrl.irqctrl0.N_363\, - \irqctrl.irqctrl0.N_361\, \irqctrl.irqctrl0.N_841\, - \irqctrl.irqctrl0.N_842\, \irqctrl.irqctrl0.N_839\, - \apbo_2.prdata[2]\, \irqctrl.irqctrl0.N_470\, - \irqctrl.irqctrl0.N_467\, \irqctrl.irqctrl0.N_468\, - \irqctrl.irqctrl0.N_473\, \irqctrl.irqctrl0.N_474\, - \irqctrl.irqctrl0.N_471\, \irqctrl.irqctrl0.N_472\, - \irqctrl.irqctrl0.N_478\, \irqctrl.irqctrl0.N_476\, - \apbo_2.prdata[15]\, \apbo_2.prdata[3]\, - \irqctrl.irqctrl0.N_861\, \irqctrl.irqctrl0.N_859\, - \irqctrl.irqctrl0.r.iforce_0_m[4]\, - \irqctrl.irqctrl0.r.ipend_m[4]\, \ua1.uart1.N_223\, - \ua1.uart1.N_220\, \ua1.uart1.r.break_m\, - \ua1.uart1.r.parsel_m_0\, \ua1.uart1.r.brate_m[4]\, - \ua1.uart1.uartop.rdata_2_m[4]\, \ua1.uart1.r.ovf_m\, - \ua1.uart1.r.flow_m\, \ua1.uart1.uartop.rdata_2_m[6]\, - \ua1.uart1.r.brate_m[11]\, \apbo_7.prdata[0]\, - \dcomgen.dcom0.dcom_uart0.N_336\, - \dcomgen.dcom0.dcom_uart0.N_334\, - \dcomgen.dcom0.dcom_uart0.N_333\, - \dcomgen.dcom0.dcom_uart0.N_332\, - \dcomgen.dcom0.dcom_uart0.N_85\, \ahbmi.hrdata[18]\, - \ahbso_6.hrdata[30]\, \ahbso_6.hrdata[16]\, N_467, N_462, - N_457, \ahbmo_0.hwdata[19]\, \ahbmo_0.haddr[23]\, - \ahbmo_0.haddr[26]\, \ahbmo_0.haddr[18]\, - \ahbmo_0.haddr[4]\, \ahbso_6.hrdata[29]\, - \ahbso_6.hrdata[19]\, \ahbso_6.hrdata[18]\, - \ahbso_6.hrdata[17]\, \ahbso_6.hrdata[12]\, - \ahbso_6.hrdata[10]\, \ahbso_6.hrdata[8]\, - \ahbso_6.hrdata[7]\, \ahbso_6.hrdata[6]\, - \ahbso_6.hrdata[5]\, \ahbmi.hrdata[30]\, - \r.hmaster_0_0_RNIFCVH1_0[1]\, \ahb0.hrdata_1_0_1[1]\, - \ahb0.comb.nhmaster_1_iv_0[1]\, \ahbmo_0.htrans_tz[1]\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_0_N_15_i_0_li\, - m26_m1_e, rstoutl_RNIGJKSJO, - \lfrtimemanagement_0.un1_apbi_7_3\, - \gpt.timer0.comb.un1_apbi_0\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un91_nbo_i_0\, - \lpp_bootloader_1.ahbrom_1.N_95_i_0\, - \lpp_bootloader_1.ahbrom_1.N_90_i_0\, - \lpp_bootloader_1.ahbrom_1.N_103_i_0\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a0_6_i_0\, - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a1_6_i_0\, - \DMAIn.Lock_RNIU86D\, \r.timers_2.value_RNIBAHH[1]\, - \r.timers_2.restart_RNIIKBB\, - \r.timers_2.reload_RNIRDRG[1]\, \r.reload_RNI6SNI[1]\, - \r.rcnt_RNI8FBM3[1]\, - \irqctrl.irqctrl0.prdata_11_m_1_0[4]\, - \irqctrl.irqctrl0.prdata_13_m_1_0[4]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[13]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[13]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[1]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[1]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[14]\, - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[14]\, - \gpio0.grgpio0.apbo.prdata_iv_0[1]\, - \gpio0.grgpio0.apbo.prdata_iv_0[3]\, - \gpio0.grgpio0.apbo.prdata_iv_0_0[2]\, - \gpt.timer0.readdata_1_iv_0[13]\, - \gpt.timer0.readdata_1_iv_0[15]\, - \gpt.timer0.readdata_1_iv_0[24]\, - \gpt.timer0.readdata_1_iv_0[26]\, - \gpt.timer0.readdata_1_iv_0[22]\, - \ua1.uart1.uartop.rdata_17_m_0[6]\, - \ua1.uart1.rdata_iv_0_a2_3_0[7]\, - \gpt.timer0.readdata_iv_3[3]\, - \gpt.timer0.readdata_iv_3[2]\, - \l3.cpu.0.u0.p0.c0mmu.a0.un1_htrans_1_sqmuxa_0\, - \ua1.uart1.rdata_iv_2[3]\, \ua1.uart1.rdata_iv_2[2]\, - \ua1.uart1.rdata_iv_0_2[1]\, - \ahb0.comb.0.4.un6_ioen_NE_0\, \ahbsi.hwrite_m_0_0\, - clk_c_i, \SSRAM_0.state_i[3]\, lclk_i_i, - \coarse_time_i[0]\, \gpioo.oen_i[7]\, \gpioo.oen_i[6]\, - \gpioo.oen_i[5]\, \gpioo.oen_i[4]\, \gpioo.oen_i[3]\, - \gpioo.oen_i[2]\, \gpioo.oen_i[1]\, \gpioo.oen_i[0]\, - \apbi.pwdata_i[7]\, \apbi.pwdata_i[6]\, - \apbi.pwdata_i[5]\, \apbi.pwdata_i[4]\, - \apbi.pwdata_i[3]\, \apbi.pwdata_i[2]\, - \apbi.pwdata_i[1]\, \apbi.pwdata_i[0]\, - \memo.bdrive_i[3]\, \memo.bdrive_i[2]\, - \memo.bdrive_i[1]\, \memo.bdrive_i[0]\, rstn_i, - \ahbmi.hrdata_0[18]\, \ua1.uart1.uartop.rdata62_0\, - \ua1.uart1.uartop.rdata60_4_0\, \ua1.uart1.N_232_0\, - \ua1.uart1.N_232_1\, \gpt.timer0.N_240_0\, - \gpt.timer0.readdata_1_sqmuxa_1_0\, - \gpt.timer0.v.timers_2.value_0_sqmuxa_0\, - clk49_152MHz_c_0, \ahbmi.hrdata_0[27]\, - \ahbmi.hrdata_0[26]\, \ahbmi.hrdata_0[24]\, - \ahbmi.hrdata_0[23]\, \ahbmi.hrdata_0[22]\, - \ahbmi.hrdata_0[21]\, \ahbmi.hrdata_0[17]\, - \ahbmi.hrdata_0[16]\, \ahbmi.hrdata_0[15]\, - \ahbmi.hrdata_0[14]\, \ahbmi.hrdata_0[13]\, - \ahbmi.hrdata_0[12]\, \ahbmi.hrdata_0[11]\, - \ahbmi.hrdata_0[10]\, \ahbmi.hrdata_0[9]\, - \ahbmi.hrdata_0[8]\, \ahbmi.hrdata_0[7]\, - \ahbmi.hrdata_0[4]\, \ahbmi.hrdata_0[3]\, - \ahbmi.hrdata_0[2]\, \ahbmi.hrdata_0[1]\, - \ahbmi.hrdata_0[0]\, N_264_0, N_262_0, N_78_0, - \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d_0\, \sr1.iosn_0[93]\, - \sr1.iosn_1[93]\, \sr1.iosn_2[93]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[1]\, - \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[0]\, - \apbi.pwdata_0[15]\, \apbi.pwdata_0[14]\, - \apbi.pwdata_0[13]\, \apbi.pwdata_0[12]\, - \apbi.pwdata_0[11]\, \apbi.pwdata_0[10]\, - \apbi.pwdata_0[9]\, \apbi.pwdata_0[8]\, - \apbi.pwdata_0[7]\, \apbi.pwdata_0[6]\, - \apbi.pwdata_0[5]\, \apbi.pwdata_0[4]\, - \apbi.pwdata_1[4]\, \apbi.pwdata_0[3]\, - \apbi.pwdata_1[3]\, \apbi.pwdata_0[2]\, - \apbi.pwdata_0[1]\, \apbi.pwdata_1[1]\, - \apbi.pwdata_0[0]\, \apbi.paddr_0[4]\, \apbi.paddr_0[3]\, - \apbi.paddr_0[2]\, \apbi.paddr_1[2]\, \apbi.paddr_2[2]\, - \ahbsi.hmaster_0[1]\, N_6455_0, GND_0, VCC_0 : std_logic; - - for all : gptimer - Use entity work.gptimer(DEF_ARCH); - for all : ssram_plugin - Use entity work.ssram_plugin(DEF_ARCH); - for all : leon3s - Use entity work.leon3s(DEF_ARCH); - for all : irqmp - Use entity work.irqmp(DEF_ARCH); - for all : apbuart - Use entity work.apbuart(DEF_ARCH); - for all : apbctrl - Use entity work.apbctrl(DEF_ARCH); - for all : ahbram - Use entity work.ahbram(DEF_ARCH); - for all : lpp_bootloader - Use entity work.lpp_bootloader(DEF_ARCH); - for all : lpp_top_lfr_wf_picker - Use entity work.lpp_top_lfr_wf_picker(DEF_ARCH); - for all : ahbuart - Use entity work.ahbuart(DEF_ARCH); - for all : ahbctrl - Use entity work.ahbctrl(DEF_ARCH); - for all : apb_lfr_time_management - Use entity work.apb_lfr_time_management(DEF_ARCH); - for all : rstgen - Use entity work.rstgen(DEF_ARCH); - for all : mctrl - Use entity work.mctrl(DEF_ARCH); - for all : grgpio - Use entity work.grgpio(DEF_ARCH); -begin - - - writen_pad : OUTBUF - port map(D => writen_c, PAD => writen); - - \spw_txsn_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => spw_txsn(1)); - - \spw_txdn_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => spw_txdn(1)); - - \rwen_pad[2]\ : OUTBUF - port map(D => \rwen_c[2]\, PAD => rwen(2)); - - \pci_ad_pad[20]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(20)); - - \address_pad[16]\ : OUTBUF - port map(D => \address_c[16]\, PAD => address(16)); - - \data_pad[20]\ : BIBUF - port map(PAD => data(20), D => \memo.data[20]\, E => - \memo.bdrive_i[1]\, Y => \data_in[20]\); - - \spw_txsn_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => spw_txsn(0)); - - \spw_txdn_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => spw_txdn(0)); - - \gpt.timer0\ : gptimer - port map(scaler_4 => \gpt.timer0.r.scaler[4]\, pwdata_1_3 - => \apbi.pwdata_1[4]\, pwdata_1_0 => \apbi.pwdata_1[1]\, - pwdata_1_2 => \apbi.pwdata_1[3]\, paddr(6) => - \apbi.paddr[6]\, paddr(5) => \apbi.paddr[5]\, paddr(4) - => \apbi.paddr[4]\, paddr(3) => \apbi.paddr[3]\, - paddr(2) => \apbi.paddr[2]\, value_6 => - \gpt.timer0.r.timers_2.value[6]\, value_0 => - \gpt.timer0.r.timers_2.value[0]\, paddr_2(2) => - \apbi.paddr_2[2]\, pirq(9) => \apbi.pirq[9]\, pirq(8) => - \apbi.pirq[8]\, readdata_9_5 => - \gpt.timer0.comb.1.readdata_9[5]\, readdata_9_0 => - \gpt.timer0.comb.1.readdata_9[0]\, readdata_9_27 => - \gpt.timer0.comb.1.readdata_9[27]\, readdata_9_4 => - \gpt.timer0.comb.1.readdata_9[4]\, paddr_1(2) => - \apbi.paddr_1[2]\, reload_RNIRDRG(1) => - \r.timers_2.reload_RNIRDRG[1]\, value_RNIBAHH(1) => - \r.timers_2.value_RNIBAHH[1]\, reload_RNI6SNI(1) => - \r.reload_RNI6SNI[1]\, scaler_i_m(1) => - \gpt.timer0.r.scaler_i_m[1]\, reload_m_0_2 => - \gpt.timer0.r.reload_m[2]\, reload_m_0_3 => - \gpt.timer0.r.reload_m[3]\, reload_m_0_0 => - \gpt.timer0.r.timers_2.reload_m[0]\, scaler_m_5 => - \gpt.timer0.r.scaler_m[5]\, scaler_m_7 => - \gpt.timer0.r.scaler_m[7]\, scaler_m_6 => - \gpt.timer0.r.scaler_m[6]\, scaler_m_0 => - \gpt.timer0.r.scaler_m[0]\, pwdata_0_d0 => - \apbi.pwdata[6]\, pwdata_14 => \apbi.pwdata[20]\, - pwdata_25 => \apbi.pwdata[31]\, pwdata_12 => - \apbi.pwdata[18]\, pwdata_24 => \apbi.pwdata[30]\, - pwdata_23 => \apbi.pwdata[29]\, pwdata_22 => - \apbi.pwdata[28]\, pwdata_21 => \apbi.pwdata[27]\, - pwdata_20 => \apbi.pwdata[26]\, pwdata_19 => - \apbi.pwdata[25]\, pwdata_18 => \apbi.pwdata[24]\, - pwdata_17 => \apbi.pwdata[23]\, pwdata_16 => - \apbi.pwdata[22]\, pwdata_15 => \apbi.pwdata[21]\, - pwdata_13 => \apbi.pwdata[19]\, pwdata_11 => - \apbi.pwdata[17]\, pwdata_10 => \apbi.pwdata[16]\, - reload_28 => \gpt.timer0.r.timers_2.reload[28]\, - reload_12 => \gpt.timer0.r.timers_2.reload[12]\, - reload_11 => \gpt.timer0.r.timers_2.reload[11]\, - reload_10 => \gpt.timer0.r.timers_2.reload[10]\, reload_8 - => \gpt.timer0.r.timers_2.reload[8]\, reload_7 => - \gpt.timer0.r.timers_2.reload[7]\, reload_6 => - \gpt.timer0.r.timers_2.reload[6]\, reload_5 => - \gpt.timer0.r.timers_2.reload[5]\, reload_0_7 => - \gpt.timer0.r.reload[7]\, reload_0_6 => - \gpt.timer0.r.reload[6]\, reload_0_4 => - \gpt.timer0.r.timers_2.reload[4]\, pwdata_0(15) => - \apbi.pwdata_0[15]\, pwdata_0(14) => \apbi.pwdata_0[14]\, - pwdata_0(13) => \apbi.pwdata_0[13]\, pwdata_0(12) => - \apbi.pwdata_0[12]\, pwdata_0(11) => \apbi.pwdata_0[11]\, - pwdata_0(10) => \apbi.pwdata_0[10]\, pwdata_0(9) => - \apbi.pwdata_0[9]\, pwdata_0(8) => \apbi.pwdata_0[8]\, - pwdata_0(7) => \apbi.pwdata_0[7]\, pwdata_0(6) => - \apbi.pwdata_0[6]\, pwdata_0(5) => \apbi.pwdata_0[5]\, - pwdata_0(4) => \apbi.pwdata_0[4]\, pwdata_0(3) => - \apbi.pwdata_0[3]\, pwdata_0(2) => \apbi.pwdata_0[2]\, - pwdata_0(1) => \apbi.pwdata_0[1]\, pwdata_0(0) => - \apbi.pwdata_0[0]\, prdata_17 => \apbo_3.prdata[31]\, - prdata_0 => \apbo_3.prdata[14]\, prdata_2 => - \apbo_3.prdata[16]\, prdata_4 => \apbo_3.prdata[18]\, - prdata_16 => \apbo_3.prdata[30]\, prdata_3 => - \apbo_3.prdata[17]\, prdata_5 => \apbo_3.prdata[19]\, - prdata_11 => \apbo_3.prdata[25]\, prdata_15 => - \apbo_3.prdata[29]\, prdata_9 => \apbo_3.prdata[23]\, - readdata_9_i_m(1) => - \gpt.timer0.comb.1.readdata_9_i_m[1]\, readdata_1_iv_0_0 - => \gpt.timer0.readdata_1_iv_0[13]\, readdata_1_iv_0_2 - => \gpt.timer0.readdata_1_iv_0[15]\, readdata_1_iv_0_11 - => \gpt.timer0.readdata_1_iv_0[24]\, readdata_1_iv_0_13 - => \gpt.timer0.readdata_1_iv_0[26]\, readdata_1_iv_0_9 - => \gpt.timer0.readdata_1_iv_0[22]\, readdata_iv_3(3) - => \gpt.timer0.readdata_iv_3[3]\, readdata_iv_3(2) => - \gpt.timer0.readdata_iv_3[2]\, reload_m_20 => - \gpt.timer0.r.timers_2.reload_m[20]\, reload_m_5 => - \gpt.timer0.r.reload_m[5]\, reload_m_9 => - \gpt.timer0.r.timers_2.reload_m[9]\, reload_m_21 => - \gpt.timer0.r.timers_2.reload_m[21]\, reload_m_0_d0 => - \gpt.timer0.r.reload_m[0]\, reload_m_27 => - \gpt.timer0.r.timers_2.reload_m[27]\, reload_m_4 => - \gpt.timer0.r.reload_m[4]\, value_m_1 => - \gpt.timer0.r.timers_2.value_m[5]\, value_m_9 => - \gpt.timer0.r.timers_2.value_m[13]\, value_m_5 => - \gpt.timer0.r.timers_2.value_m[9]\, value_m_23 => - \gpt.timer0.r.timers_2.value_m[27]\, value_m_17 => - \gpt.timer0.r.timers_2.value_m[21]\, value_m_11 => - \gpt.timer0.r.timers_2.value_m[15]\, value_m_3 => - \gpt.timer0.r.timers_2.value_m[7]\, value_m_20 => - \gpt.timer0.r.timers_2.value_m[24]\, value_m_6 => - \gpt.timer0.r.timers_2.value_m[10]\, value_m_4 => - \gpt.timer0.r.timers_2.value_m[8]\, value_m_7 => - \gpt.timer0.r.timers_2.value_m[11]\, value_m_0 => - \gpt.timer0.r.timers_2.value_m[4]\, value_m_24 => - \gpt.timer0.r.timers_2.value_m[28]\, value_m_22 => - \gpt.timer0.r.timers_2.value_m[26]\, value_m_18 => - \gpt.timer0.r.timers_2.value_m[22]\, value_m_8 => - \gpt.timer0.r.timers_2.value_m[12]\, value_m_16 => - \gpt.timer0.r.timers_2.value_m[20]\, paddr_0(3) => - \apbi.paddr_0[3]\, paddr_0(2) => \apbi.paddr_0[2]\, N_228 - => \gpt.timer0.N_228\, readdata51_1 => - \gpt.timer0.comb.2.readdata51_1\, N_6455 => N_6455, - chain_m => \gpt.timer0.r.timers_2.chain_m\, rdata60_1 => - \ua1.uart1.uartop.rdata60_1\, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, enable_m => - \gpt.timer0.r.timers_2.enable_m\, rdata59_4 => - \ua1.uart1.uartop.rdata59_4\, N_217 => \gpt.timer0.N_217\, - N_229 => \gpt.timer0.N_229\, N_215 => \gpt.timer0.N_215\, - rdata61_2 => \ua1.uart1.uartop.rdata61_2\, readdata55_3 - => \gpt.timer0.comb.readdata55_3\, N_218 => - \gpt.timer0.N_218\, N_216 => \gpt.timer0.N_216\, N_214 - => \gpt.timer0.N_214\, irqpen_m => - \gpt.timer0.r.timers_2.irqpen_m\, N_219 => - \gpt.timer0.N_219\, N_236 => \gpt.timer0.N_236\, N_220 - => \gpt.timer0.N_220\, rstn => rstn, restart_RNIIKBB => - \r.timers_2.restart_RNIIKBB\, N_240 => \gpt.timer0.N_240\, - readdata55 => \gpt.timer0.comb.readdata55\, dishlt => - \gpt.timer0.r.dishlt\, penable => \apbi.penable\, pwrite - => \apbi.pwrite\, N_773 => \apb0.N_773\, N_769 => - \apb0.N_769\, readdata57 => \gpt.timer0.comb.readdata57\, - un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\, N_78 => - \apb0.N_78\, un1_apbi_7_3 => - \lfrtimemanagement_0.un1_apbi_7_3\, un1_apbi_2 => - \gpt.timer0.comb.1.un1_apbi_2\, readdata56 => - \gpt.timer0.comb.readdata56\, N_232_0 => - \ua1.uart1.N_232_0\, N_240_0 => \gpt.timer0.N_240_0\, - readdata_1_sqmuxa_1_0 => - \gpt.timer0.readdata_1_sqmuxa_1_0\, N_232 => - \ua1.uart1.N_232\, value_0_sqmuxa_0 => - \gpt.timer0.v.timers_2.value_0_sqmuxa_0\, N_6455_0 => - N_6455_0, lclk_c => lclk_c); - - \sdo_adc_pad[5]\ : INBUF - port map(PAD => sdo_adc(5), Y => \sdo_adc_c[5]\); - - \spw_txs_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => spw_txs(0)); - - \spw_txs_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => spw_txs(2)); - - lclk : DFN1 - port map(D => lclk_i_i, CLK => clk_c, Q => lclk_i); - - \ramsn_pad[3]\ : OUTBUF - port map(D => \ramsn_c[3]\, PAD => ramsn(3)); - - \data_pad[29]\ : BIBUF - port map(PAD => data(29), D => \memo.data[29]\, E => - \memo.bdrive_i[0]\, Y => \data_in[29]\); - - MODE_pad : OUTBUF - port map(D => \GND\, PAD => MODE); - - \ramoen_pad[0]\ : OUTBUF - port map(D => \ramoen_c[0]\, PAD => ramoen(0)); - - pci_irdy_pad : OUTBUF - port map(D => \GND\, PAD => pci_irdy); - - SSRAM_0 : ssram_plugin - port map(state_RNIFS55(4) => \state_RNIFS55[4]\, ramsn_c(0) - => \ramsn_c[0]\, rwen_c(3) => \rwen_c[3]\, rwen_c(2) => - \rwen_c[2]\, rwen_c(1) => \rwen_c[1]\, rwen_c(0) => - \rwen_c[0]\, address_c(27) => \address_c[27]\, - address_c(26) => \address_c[26]\, address_c(25) => - \address_c[25]\, address_c(24) => \address_c[24]\, - address_c(23) => \address_c[23]\, address_c(22) => - \address_c[22]\, address_c(21) => \address_c[21]\, - address_c(20) => \address_c[20]\, address(31) => - \memo.address[31]\, address(30) => \memo.address[30]\, - address(29) => \memo.address[29]\, address(28) => - \memo.address[28]\, state_i(3) => \SSRAM_0.state_i[3]\, - ssram_plugin_GND => \GND\, clk_c => clk_c, writen_c => - writen_c, nBWE_c => nBWE_c, nBWd_c => nBWd_c, nBWc_c => - nBWc_c, nBWb_c => nBWb_c, nBWa_c => nBWa_c, nCE1_c => - nCE1_c, nCE3_c => nCE3_c, CE2_c => CE2_c); - - pci_devsel_pad : OUTBUF - port map(D => \GND\, PAD => pci_devsel); - - \data_pad[1]\ : BIBUF - port map(PAD => data(1), D => \memo.data[1]\, E => - \memo.bdrive_i[3]\, Y => \data_in[1]\); - - \address_pad[23]\ : OUTBUF - port map(D => \address_c[23]\, PAD => address(23)); - - ereset_pad : OUTBUF - port map(D => \GND\, PAD => ereset); - - \address_pad[8]\ : OUTBUF - port map(D => \address_c[8]\, PAD => address(8)); - - \address_pad[21]\ : OUTBUF - port map(D => \address_c[21]\, PAD => address(21)); - - lclk_RNO : INV - port map(A => lclk_i, Y => lclk_i_i); - - \pci_ad_pad[23]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(23)); - - \pci_cbe_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => pci_cbe(2)); - - \gpio_pad[6]\ : BIBUF - port map(PAD => gpio(6), D => \gpioo.dout[6]\, E => - \gpioo.oen_i[6]\, Y => \gpio_in[6]\); - - \pci_ad_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(2)); - - \spw_txd_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => spw_txd(1)); - - \data_pad[27]\ : BIBUF - port map(PAD => data(27), D => \memo.data[27]\, E => - \memo.bdrive_i[0]\, Y => \data_in[27]\); - - \ramsn_pad[4]\ : OUTBUF - port map(D => \VCC\, PAD => ramsn(4)); - - errorn_pad : TRIBUFF - port map(D => \GND\, E => \dbgo_0.error_i_2\, PAD => errorn); - - \data_pad[13]\ : BIBUF - port map(PAD => data(13), D => \memo.data[13]\, E => - \memo.bdrive_i[2]\, Y => \data_in[13]\); - - \ramoen_pad[2]\ : OUTBUF - port map(D => \ramoen_c[2]\, PAD => ramoen(2)); - - \sdo_adc_pad[2]\ : INBUF - port map(PAD => sdo_adc(2), Y => \sdo_adc_c[2]\); - - read_pad : OUTBUF - port map(D => read_c, PAD => read); - - nBWa_pad : OUTBUF - port map(D => nBWa_c, PAD => nBWa); - - \address_pad[19]\ : OUTBUF - port map(D => \address_c[19]\, PAD => address(19)); - - \rwen_pad[3]\ : OUTBUF - port map(D => \rwen_c[3]\, PAD => rwen(3)); - - nADV_pad : OUTBUF - port map(D => \VCC\, PAD => nADV); - - \l3.cpu.0.u0\ : leon3s - port map(irl_0(3) => \irqi_0.irl[3]\, irl_0(2) => - \irqi_0.irl[2]\, irl_0(1) => \irqi_0.irl[1]\, irl_0(0) - => \irqi_0.irl[0]\, irl(3) => \irqo_0.irl[3]\, irl(2) - => \irqo_0.irl[2]\, irl(1) => \irqo_0.irl[1]\, irl(0) - => \irqo_0.irl[0]\, hrdata_1_0_1(1) => - \ahb0.hrdata_1_0_1[1]\, data_0_21 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[29]\, data_0_16 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[24]\, data_0_5 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[13]\, data_0_2 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[10]\, data_0_0 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[8]\, nbo_5_0(1) => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[1]\, nbo_5_0(0) => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[0]\, htrans(1) => - \ahbmo_0.htrans[1]\, iosn_0(93) => \sr1.iosn_0[93]\, - htrans_tz(1) => \ahbmo_0.htrans_tz[1]\, haddr(31) => - \ahbmo_0.haddr[31]\, haddr(30) => \ahbmo_0.haddr[30]\, - haddr(29) => \ahbmo_0.haddr[29]\, haddr(28) => - \ahbmo_0.haddr[28]\, haddr(27) => \ahbmo_0.haddr[27]\, - haddr(26) => \ahbmo_0.haddr[26]\, haddr(25) => - \ahbmo_0.haddr[25]\, haddr(24) => \ahbmo_0.haddr[24]\, - haddr(23) => \ahbmo_0.haddr[23]\, haddr(22) => - \ahbmo_0.haddr[22]\, haddr(21) => \ahbmo_0.haddr[21]\, - haddr(20) => \ahbmo_0.haddr[20]\, haddr(19) => - \ahbmo_0.haddr[19]\, haddr(18) => \ahbmo_0.haddr[18]\, - haddr(17) => \ahbmo_0.haddr[17]\, haddr(16) => - \ahbmo_0.haddr[16]\, haddr(15) => \ahbmo_0.haddr[15]\, - haddr(14) => \ahbmo_0.haddr[14]\, haddr(13) => - \ahbmo_0.haddr[13]\, haddr(12) => \ahbmo_0.haddr[12]\, - haddr(11) => \ahbmo_0.haddr[11]\, haddr(10) => - \ahbmo_0.haddr[10]\, haddr(9) => \ahbmo_0.haddr[9]\, - haddr(8) => \ahbmo_0.haddr[8]\, haddr(7) => - \ahbmo_0.haddr[7]\, haddr(6) => \ahbmo_0.haddr[6]\, - haddr(5) => \ahbmo_0.haddr[5]\, haddr(4) => - \ahbmo_0.haddr[4]\, haddr(3) => \ahbmo_0.haddr[3]\, - haddr(2) => \ahbmo_0.haddr[2]\, hwdata_16 => - \ahbmo_0.hwdata[19]\, hwdata_3 => \ahbmo_0.hwdata[6]\, - hwdata_9 => \ahbmo_0.hwdata[12]\, hwdata_11 => - \ahbmo_0.hwdata[14]\, hwdata_25 => \ahbmo_0.hwdata[28]\, - hwdata_27 => \ahbmo_0.hwdata[30]\, hwdata_13 => - \ahbmo_0.hwdata[16]\, hwdata_4 => \ahbmo_0.hwdata[7]\, - hwdata_12 => \ahbmo_0.hwdata[15]\, hwdata_23 => - \ahbmo_0.hwdata[26]\, hwdata_28 => \ahbmo_0.hwdata[31]\, - hwdata_1 => \ahbmo_0.hwdata[4]\, hwdata_14 => - \ahbmo_0.hwdata[17]\, hwdata_0 => \ahbmo_0.hwdata[3]\, - hwdata_15 => \ahbmo_0.hwdata[18]\, iosn_1(93) => - \sr1.iosn_1[93]\, hsize_5(1) => - \l3.cpu.0.u0.p0.c0mmu.a0.hsize_5[1]\, hgrant(0) => - \ahbmi.hgrant[0]\, hresp(0) => \ahbmi.hresp[0]\, - iosn_2(93) => \sr1.iosn_2[93]\, address(1) => - \l3.cpu.0.u0.p0.c0mmu.mcdi.address[1]\, address(0) => - \l3.cpu.0.u0.p0.c0mmu.mcdi.address[0]\, size(0) => - \l3.cpu.0.u0.p0.c0mmu.mcdi.size[0]\, data_0_d0 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[5]\, data_5 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[10]\, data_3 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[8]\, data_8 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[13]\, data_19 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[24]\, data_24 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[29]\, hrdata_0_15 => - \ahbmi.hrdata_0[15]\, hrdata_0_0 => \ahbmi.hrdata_0[0]\, - hrdata_0_26 => \ahbmi.hrdata_0[26]\, hrdata_0_2 => - \ahbmi.hrdata_0[2]\, hrdata_0_1 => \ahbmi.hrdata_0[1]\, - hrdata_0_7 => \ahbmi.hrdata_0[7]\, hrdata_0_10 => - \ahbmi.hrdata_0[10]\, hrdata_0_11 => \ahbmi.hrdata_0[11]\, - hrdata_0_12 => \ahbmi.hrdata_0[12]\, hrdata_0_27 => - \ahbmi.hrdata_0[27]\, hrdata_0_21 => \ahbmi.hrdata_0[21]\, - hrdata_0_8 => \ahbmi.hrdata_0[8]\, hrdata_0_9 => - \ahbmi.hrdata_0[9]\, hrdata_0_13 => \ahbmi.hrdata_0[13]\, - hrdata_0_14 => \ahbmi.hrdata_0[14]\, hrdata_0_22 => - \ahbmi.hrdata_0[22]\, hrdata_0_23 => \ahbmi.hrdata_0[23]\, - hrdata_0_16 => \ahbmi.hrdata_0[16]\, hrdata_0_17 => - \ahbmi.hrdata_0[17]\, hrdata_0_18 => \ahbmi.hrdata_0[18]\, - hrdata_0_4 => \ahbmi.hrdata_0[4]\, hrdata_0_24 => - \ahbmi.hrdata_0[24]\, hrdata_0_3 => \ahbmi.hrdata_0[3]\, - hrdata_9 => \ahbmi.hrdata[9]\, hrdata_10 => - \ahbmi.hrdata[10]\, hrdata_11 => \ahbmi.hrdata[11]\, - hrdata_13 => \ahbmi.hrdata[13]\, hrdata_14 => - \ahbmi.hrdata[14]\, hrdata_17 => \ahbmi.hrdata[17]\, - hrdata_24 => \ahbmi.hrdata[24]\, hrdata_0_d0 => - \ahbmi.hrdata[0]\, hrdata_1 => \ahbmi.hrdata[1]\, - hrdata_8 => \ahbmi.hrdata[8]\, hrdata_12 => - \ahbmi.hrdata[12]\, hrdata_15 => \ahbmi.hrdata[15]\, - hrdata_16 => \ahbmi.hrdata[16]\, hrdata_18 => - \ahbmi.hrdata[18]\, hrdata_21 => \ahbmi.hrdata[21]\, - hrdata_22 => \ahbmi.hrdata[22]\, hrdata_23 => - \ahbmi.hrdata[23]\, hrdata_26 => \ahbmi.hrdata[26]\, - hrdata_27 => \ahbmi.hrdata[27]\, hrdata_2 => - \ahbmi.hrdata[2]\, hrdata_3 => \ahbmi.hrdata[3]\, - hrdata_4 => \ahbmi.hrdata[4]\, hrdata_7 => - \ahbmi.hrdata[7]\, hrdata_5 => \ahbmi.hrdata[5]\, - hrdata_6 => \ahbmi.hrdata[6]\, hrdata_28 => - \ahbmi.hrdata[28]\, hrdata_29 => \ahbmi.hrdata[29]\, - hrdata_30 => \ahbmi.hrdata[30]\, hrdata_31 => - \ahbmi.hrdata[31]\, error_i_2 => \dbgo_0.error_i_2\, - intack => \irqo_0.intack\, N_546 => N_546, leon3s_VCC => - \VCC\, N_264 => N_264, N_262 => N_262, N_78 => N_78, - bo_5842_d_0 => \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d_0\, - un1_htrans_1_sqmuxa_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.un1_htrans_1_sqmuxa_0\, hlock - => \ahbmo_0.hlock\, N_5054 => N_5054, lb_0_sqmuxa_1 => - \l3.cpu.0.u0.p0.c0mmu.a0.v.lb_0_sqmuxa_1\, hbusreq => - \ahbmo_0.hbusreq\, un60_nbo => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un60_nbo\, N_457 => N_457, - N_462 => N_462, N_467 => N_467, werr_2_m_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.v.werr_2_m_0\, un91_nbo_i_0 - => \l3.cpu.0.u0.p0.c0mmu.a0.comb.un91_nbo_i_0\, N_138 - => N_138, N_139 => N_139, bo_5842_d => - \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d\, N_458 => N_458, - N_459 => N_459, N_461 => N_461, N_463 => N_463, N_468 => - N_468, hwrite_1_m_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.hwrite_1_m_0\, N_466 => - N_466, htrans_0_sqmuxa_2 => - \l3.cpu.0.u0.p0.c0mmu.a0.htrans_0_sqmuxa_2\, un59_nbo => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un59_nbo\, N_78_0 => N_78_0, - N_262_0 => N_262_0, N_264_0 => N_264_0, rstn => rstn, - lclk_c => lclk_c); - - \data_pad[9]\ : BIBUF - port map(PAD => data(9), D => \memo.data[9]\, E => - \memo.bdrive_i[2]\, Y => \data_in[9]\); - - \address_pad[13]\ : OUTBUF - port map(D => \address_c[13]\, PAD => address(13)); - - \data_pad[30]\ : BIBUF - port map(PAD => data(30), D => \memo.data[30]\, E => - \memo.bdrive_i[0]\, Y => \data_in[30]\); - - \ramsn_pad[2]\ : OUTBUF - port map(D => \ramsn_c[2]\, PAD => ramsn(2)); - - \address_pad[11]\ : OUTBUF - port map(D => \address_c[11]\, PAD => address(11)); - - \pci_ad_pad[15]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(15)); - - nADSP_pad : OUTBUF - port map(D => \SSRAM_0.state_i[3]\, PAD => nADSP); - - \romsn_pad[0]\ : OUTBUF - port map(D => \romsn_c[0]\, PAD => romsn(0)); - - \address_pad[1]\ : OUTBUF - port map(D => \address_c[1]\, PAD => address(1)); - - \pci_cbe_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => pci_cbe(0)); - - \ramoen_pad[1]\ : OUTBUF - port map(D => \ramoen_c[1]\, PAD => ramoen(1)); - - ZZ_pad : OUTBUF - port map(D => \GND\, PAD => ZZ); - - pci_frame_pad : OUTBUF - port map(D => \GND\, PAD => pci_frame); - - \irqctrl.irqctrl0\ : irqmp - port map(irl_2(2) => \irqi_0.irl[2]\, pwdata_1_3 => - \apbi.pwdata_1[4]\, pwdata_1_2 => \apbi.pwdata_1[3]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, irl_3 => - \irqo_0.irl[3]\, irl_1 => \irqo_0.irl[1]\, irl_0_d0 => - \irqo_0.irl[0]\, irl_0(3) => \irqi_0.irl[3]\, irl_0(2) - => \irqo_0.irl[2]\, irl_0(1) => \irqi_0.irl[1]\, - irl_0(0) => \irqi_0.irl[0]\, ipend_10 => - \irqctrl.irqctrl0.r.ipend[11]\, pwdata_4 => - \apbi.pwdata[6]\, pwdata_0_d0 => \apbi.pwdata[2]\, - pwdata_17 => \apbi.pwdata[19]\, pwdata_21 => - \apbi.pwdata[23]\, pwdata_23 => \apbi.pwdata[25]\, - pwdata_26 => \apbi.pwdata[28]\, pwdata_16 => - \apbi.pwdata[18]\, pwdata_18 => \apbi.pwdata[20]\, - pwdata_15 => \apbi.pwdata[17]\, pwdata_25 => - \apbi.pwdata[27]\, pwdata_27 => \apbi.pwdata[29]\, - pwdata_28 => \apbi.pwdata[30]\, pwdata_29 => - \apbi.pwdata[31]\, pwdata_20 => \apbi.pwdata[22]\, - pwdata_19 => \apbi.pwdata[21]\, pwdata_24 => - \apbi.pwdata[26]\, pwdata_22 => \apbi.pwdata[24]\, - iforce_0_11 => \irqctrl.irqctrl0.r.iforce_0[12]\, - iforce_0_5 => \irqctrl.irqctrl0.r.iforce_0[6]\, - iforce_0_9 => \irqctrl.irqctrl0.r.iforce_0[10]\, - iforce_0_4 => \irqctrl.irqctrl0.r.iforce_0[5]\, - iforce_0_6 => \irqctrl.irqctrl0.r.iforce_0[7]\, - ipend_m(4) => \irqctrl.irqctrl0.r.ipend_m[4]\, prdata_0 - => \apbo_2.prdata[2]\, prdata_13 => \apbo_2.prdata[15]\, - prdata_1 => \apbo_2.prdata[3]\, iforce_0_m(4) => - \irqctrl.irqctrl0.r.iforce_0_m[4]\, ilevel_5 => - \irqctrl.irqctrl0.r.ilevel[6]\, ilevel_4 => - \irqctrl.irqctrl0.r.ilevel[5]\, ilevel_6 => - \irqctrl.irqctrl0.r.ilevel[7]\, ilevel_3 => - \irqctrl.irqctrl0.r.ilevel[4]\, ilevel_11 => - \irqctrl.irqctrl0.r.ilevel[12]\, ilevel_7 => - \irqctrl.irqctrl0.r.ilevel[8]\, ilevel_9 => - \irqctrl.irqctrl0.r.ilevel[10]\, prdata_11_m_1_0(4) => - \irqctrl.irqctrl0.prdata_11_m_1_0[4]\, prdata_13_m_1_0(4) - => \irqctrl.irqctrl0.prdata_13_m_1_0[4]\, paddr(7) => - \apbi.paddr[7]\, paddr(6) => \apbi.paddr[6]\, paddr(5) - => \apbi.paddr[5]\, paddr(4) => \apbi.paddr[4]\, - paddr(3) => \apbi.paddr[3]\, prdata_0_iv_0_0_0_12 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[13]\, - prdata_0_iv_0_0_0_0 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[1]\, - prdata_0_iv_0_0_0_13 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[14]\, - prdata_0_iv_0_0_1_12 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[13]\, - prdata_0_iv_0_0_1_0 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[1]\, - prdata_0_iv_0_0_1_13 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[14]\, pwdata_0(15) - => \apbi.pwdata_0[15]\, pwdata_0(14) => - \apbi.pwdata_0[14]\, pwdata_0(13) => \apbi.pwdata_0[13]\, - pwdata_0(12) => \apbi.pwdata_0[12]\, pwdata_0(11) => - \apbi.pwdata_0[11]\, pwdata_0(10) => \apbi.pwdata_0[10]\, - pwdata_0(9) => \apbi.pwdata_0[9]\, pwdata_0(8) => - \apbi.pwdata_0[8]\, pwdata_0(7) => \apbi.pwdata_0[7]\, - pwdata_0(6) => \apbi.pwdata_0[6]\, pwdata_0(5) => - \apbi.pwdata_0[5]\, pwdata_0(4) => \apbi.pwdata_0[4]\, - pwdata_0(3) => \apbi.pwdata_0[3]\, pwdata_0(2) => - \apbi.pwdata_0[2]\, pwdata_0(1) => \apbi.pwdata_0[1]\, - pirq_10 => \apbi.pirq[12]\, pirq_11 => \apbi.pirq[13]\, - pirq_13 => \apbi.pirq[15]\, pirq_7 => \apbi.pirq[9]\, - pirq_6 => \apbi.pirq[8]\, pirq_0 => \apbi.pirq[2]\, - paddr_0(4) => \apbi.paddr_0[4]\, paddr_0(3) => - \apbi.paddr_0[3]\, paddr_0(2) => \apbi.paddr_0[2]\, - lclk_c => lclk_c, N_365 => \irqctrl.irqctrl0.N_365\, - N_367 => \irqctrl.irqctrl0.N_367\, N_863 => - \irqctrl.irqctrl0.N_863\, intack => \irqo_0.intack\, - N_865 => \irqctrl.irqctrl0.N_865\, N_861 => - \irqctrl.irqctrl0.N_861\, N_859 => - \irqctrl.irqctrl0.N_859\, N_478 => - \irqctrl.irqctrl0.N_478\, N_476 => - \irqctrl.irqctrl0.N_476\, N_474 => - \irqctrl.irqctrl0.N_474\, N_473 => - \irqctrl.irqctrl0.N_473\, N_472 => - \irqctrl.irqctrl0.N_472\, N_471 => - \irqctrl.irqctrl0.N_471\, N_470 => - \irqctrl.irqctrl0.N_470\, N_468 => - \irqctrl.irqctrl0.N_468\, N_467 => - \irqctrl.irqctrl0.N_467\, N_842 => - \irqctrl.irqctrl0.N_842\, N_841 => - \irqctrl.irqctrl0.N_841\, N_839 => - \irqctrl.irqctrl0.N_839\, N_363 => - \irqctrl.irqctrl0.N_363\, N_361 => - \irqctrl.irqctrl0.N_361\, N_773 => \apb0.N_773\, N_769 - => \apb0.N_769\, rstn => rstn, un1_apbi_0 => - \gpt.timer0.comb.un1_apbi_0\, N_749 => \apb0.N_749\, - prdata_0_sqmuxa => \irqctrl.irqctrl0.prdata_0_sqmuxa\, - N_898 => \irqctrl.irqctrl0.N_898\, prdata_1_sqmuxa => - \irqctrl.irqctrl0.prdata_1_sqmuxa\); - - \gpio_pad[7]\ : BIBUF - port map(PAD => gpio(7), D => \gpioo.dout[7]\, E => - \gpioo.oen_i[7]\, Y => \gpio_in[7]\); - - \rwen_pad[1]\ : OUTBUF - port map(D => \rwen_c[1]\, PAD => rwen(1)); - - Bias_Fails_pad : OUTBUF - port map(D => Bias_Fails_c, PAD => Bias_Fails); - - \pci_ad_pad[22]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(22)); - - \address_pad[4]\ : OUTBUF - port map(D => \address_c[4]\, PAD => address(4)); - - GND_i : GND - port map(Y => \GND\); - - \pci_ad_pad[14]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(14)); - - \address_pad[3]\ : OUTBUF - port map(D => \address_c[3]\, PAD => address(3)); - - \pci_ad_pad[19]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(19)); - - VCC_i_0 : VCC - port map(Y => VCC_0); - - \pci_ad_pad[5]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(5)); - - \address_pad[24]\ : OUTBUF - port map(D => \address_c[24]\, PAD => address(24)); - - \spw_txd_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => spw_txd(0)); - - \pci_ad_pad[30]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(30)); - - \ua1.uart1\ : apbuart - port map(pwdata_12 => \apbi.pwdata[12]\, pwdata_13 => - \apbi.pwdata[13]\, pwdata_14 => \apbi.pwdata[14]\, - pwdata_0_d0 => \apbi.pwdata[0]\, pwdata_2 => - \apbi.pwdata[2]\, pwdata_5 => \apbi.pwdata[5]\, pwdata_6 - => \apbi.pwdata[6]\, pwdata_7 => \apbi.pwdata[7]\, - pwdata_8 => \apbi.pwdata[8]\, pwdata_9 => - \apbi.pwdata[9]\, pwdata_10 => \apbi.pwdata[10]\, - pwdata_11 => \apbi.pwdata[11]\, pirq(2) => \apbi.pirq[2]\, - rcnt_RNI8FBM3(1) => \r.rcnt_RNI8FBM3[1]\, rdata_2_0 => - \ua1.uart1.uartop.rdata_2[0]\, pwdata_1_0 => - \apbi.pwdata_1[1]\, pwdata_1_3 => \apbi.pwdata_1[4]\, - pwdata_1_2 => \apbi.pwdata_1[3]\, paddr(4) => - \apbi.paddr[4]\, rdata_2_m_3 => - \ua1.uart1.uartop.rdata_2_m[5]\, rdata_2_m_4 => - \ua1.uart1.uartop.rdata_2_m[6]\, rdata_2_m_2 => - \ua1.uart1.uartop.rdata_2_m[4]\, brate_0 => - \ua1.uart1.r.brate[0]\, brate_10 => - \ua1.uart1.r.brate[10]\, brate_9 => - \ua1.uart1.r.brate[9]\, brate_8 => \ua1.uart1.r.brate[8]\, - brate_7 => \ua1.uart1.r.brate[7]\, brate_6 => - \ua1.uart1.r.brate[6]\, brate_m_3 => - \ua1.uart1.r.brate_m[5]\, brate_m_2 => - \ua1.uart1.r.brate_m[4]\, brate_m_9 => - \ua1.uart1.r.brate_m[11]\, pwdata_0(11) => - \apbi.pwdata_0[11]\, pwdata_0(10) => \apbi.pwdata_0[10]\, - pwdata_0(9) => \apbi.pwdata_0[9]\, pwdata_0(8) => - \apbi.pwdata_0[8]\, pwdata_0(7) => \apbi.pwdata_0[7]\, - pwdata_0(6) => \apbi.pwdata_0[6]\, pwdata_0(5) => - \apbi.pwdata_0[5]\, pwdata_0(4) => \apbi.pwdata_0[4]\, - pwdata_0(3) => \apbi.pwdata_0[3]\, pwdata_0(2) => - \apbi.pwdata_0[2]\, pwdata_0(1) => \apbi.pwdata_0[1]\, - pwdata_0(0) => \apbi.pwdata_0[0]\, rcnt_0 => - \ua1.uart1.r.rcnt[0]\, rcnt_1 => \ua1.uart1.r.rcnt[1]\, - rdata_17_m_0_d0 => \ua1.uart1.uartop.rdata_17_m[0]\, - rdata_17_m_5 => \ua1.uart1.uartop.rdata_17_m[5]\, - rdata_17_m_4 => \ua1.uart1.uartop.rdata_17_m[4]\, - un1_uart1_34 => \ua1.un1_uart1[36]\, rdata_17_m_0_4 => - \ua1.uart1.uartop.rdata_17_m_0[6]\, rdata_iv_0_a2_3_0(7) - => \ua1.uart1.rdata_iv_0_a2_3_0[7]\, tcnt_0 => - \ua1.uart1.r.tcnt[0]\, tcnt_1 => \ua1.uart1.r.tcnt[1]\, - rdata_iv_2(3) => \ua1.uart1.rdata_iv_2[3]\, rdata_iv_2(2) - => \ua1.uart1.rdata_iv_2[2]\, rdata_iv_0_2(1) => - \ua1.uart1.rdata_iv_0_2[1]\, prdata_6 => - \apbo_1.prdata[28]\, prdata_0 => \apbo_1.prdata[22]\, - prdata_9 => \apbo_1.prdata[31]\, paddr_0(4) => - \apbi.paddr_0[4]\, apbuart_VCC => \VCC\, apbuart_GND => - \GND\, rxd1_c => rxd1_c, lclk_c => lclk_c, txd1_c => - txd1_c, N_227 => \ua1.uart1.N_227\, thempty_1_m => - \ua1.uart1.uartop.thempty_1_m\, debug_m => - \ua1.uart1.r.debug_m\, N_232 => \ua1.uart1.N_232\, - rdata60 => \ua1.uart1.uartop.rdata60\, frame => - \ua1.uart1.r.frame\, rdata59 => - \ua1.uart1.uartop.rdata59\, parerr_m => - \ua1.uart1.r.parerr_m\, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, rdata62 => - \ua1.uart1.uartop.rdata62\, N_6455_0 => N_6455_0, - rdata59_4 => \ua1.uart1.uartop.rdata59_4\, parsel_m_0 => - \ua1.uart1.r.parsel_m_0\, ovf_m => \ua1.uart1.r.ovf_m\, - break_m => \ua1.uart1.r.break_m\, N_223 => - \ua1.uart1.N_223\, N_220 => \ua1.uart1.N_220\, - rfifoirqen_m => \ua1.uart1.r.rfifoirqen_m\, tfifoirqen_m - => \ua1.uart1.r.tfifoirqen_m\, N_156 => - \ua1.uart1.N_156\, rhalffull_1_m => - \ua1.uart1.uartop.rhalffull_1_m\, rdata_3_sqmuxa => - \ua1.uart1.rdata_3_sqmuxa\, ctrl2 => - \lfrtimemanagement_0.r.ctrl2\, rstn => rstn, - tsemptyirqen_0 => \ua1.uart1.r.tsemptyirqen\, N_773 => - \apb0.N_773\, N_769 => \apb0.N_769\, paren => - \ua1.uart1.r.paren\, N_750 => \apb0.N_750\, penable => - \apbi.penable\, breakirqen => \ua1.uart1.r.breakirqen\, - delayirqen => \ua1.uart1.r.delayirqen\, rdata_4_sqmuxa - => \ua1.uart1.rdata_4_sqmuxa\, rdata_0_sqmuxa => - \ua1.uart1.rdata_0_sqmuxa\, tcnt_i => - \ua1.uart1.uartop.un1_r.tcnt_i\, flow_m => - \ua1.uart1.r.flow_m\, extclken_m => - \ua1.uart1.r.extclken_m\, rdata61 => - \ua1.uart1.uartop.rdata61\, pwrite => \apbi.pwrite\, - un1_apbi_8 => \lfrtimemanagement_0.un1_apbi_8\, rdata62_0 - => \ua1.uart1.uartop.rdata62_0\, rdata60_1 => - \ua1.uart1.uartop.rdata60_1\, rdata61_2 => - \ua1.uart1.uartop.rdata61_2\, rdata60_4_0 => - \ua1.uart1.uartop.rdata60_4_0\); - - \pci_ad_pad[11]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(11)); - - \address_pad[22]\ : OUTBUF - port map(D => \address_c[22]\, PAD => address(22)); - - sck_ch1_pad : OUTBUF - port map(D => sck_ch1_c, PAD => sck_ch1); - - \pci_ad_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(1)); - - dsurx_pad : INBUF - port map(PAD => dsurx, Y => dsurx_c); - - \ramsn_pad[0]\ : OUTBUF - port map(D => \ramsn_c[0]\, PAD => ramsn(0)); - - \pci_ad_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(0)); - - apb0 : apbctrl - port map(hrdata(31) => \ahbso_1.hrdata[31]\, hrdata(30) => - \ahbso_1.hrdata[30]\, hrdata(29) => \ahbso_1.hrdata[29]\, - hrdata(28) => \ahbso_1.hrdata[28]\, hrdata(27) => - \ahbso_1.hrdata[27]\, hrdata(26) => \ahbso_1.hrdata[26]\, - hrdata(25) => \ahbso_1.hrdata[25]\, hrdata(24) => - \ahbso_1.hrdata[24]\, hrdata(23) => \ahbso_1.hrdata[23]\, - hrdata(22) => \ahbso_1.hrdata[22]\, hrdata(21) => - \ahbso_1.hrdata[21]\, hrdata(20) => \ahbso_1.hrdata[20]\, - hrdata(19) => \ahbso_1.hrdata[19]\, hrdata(18) => - \ahbso_1.hrdata[18]\, hrdata(17) => \ahbso_1.hrdata[17]\, - hrdata(16) => \ahbso_1.hrdata[16]\, hrdata(15) => - \ahbso_1.hrdata[15]\, hrdata(14) => \ahbso_1.hrdata[14]\, - hrdata(13) => \ahbso_1.hrdata[13]\, hrdata(12) => - \ahbso_1.hrdata[12]\, hrdata(11) => \ahbso_1.hrdata[11]\, - hrdata(10) => \ahbso_1.hrdata[10]\, hrdata(9) => - \ahbso_1.hrdata[9]\, hrdata(8) => \ahbso_1.hrdata[8]\, - hrdata(7) => \ahbso_1.hrdata[7]\, hrdata(6) => - \ahbso_1.hrdata[6]\, hrdata(5) => \ahbso_1.hrdata[5]\, - hrdata(4) => \ahbso_1.hrdata[4]\, hrdata(3) => - \ahbso_1.hrdata[3]\, hrdata(2) => \ahbso_1.hrdata[2]\, - hrdata(1) => \ahbso_1.hrdata[1]\, hrdata(0) => - \ahbso_1.hrdata[0]\, pwdata(31) => \apbi.pwdata[31]\, - pwdata(30) => \apbi.pwdata[30]\, pwdata(29) => - \apbi.pwdata[29]\, pwdata(28) => \apbi.pwdata[28]\, - pwdata(27) => \apbi.pwdata[27]\, pwdata(26) => - \apbi.pwdata[26]\, pwdata(25) => \apbi.pwdata[25]\, - pwdata(24) => \apbi.pwdata[24]\, pwdata(23) => - \apbi.pwdata[23]\, pwdata(22) => \apbi.pwdata[22]\, - pwdata(21) => \apbi.pwdata[21]\, pwdata(20) => - \apbi.pwdata[20]\, pwdata(19) => \apbi.pwdata[19]\, - pwdata(18) => \apbi.pwdata[18]\, pwdata(17) => - \apbi.pwdata[17]\, pwdata(16) => \apbi.pwdata[16]\, - pwdata(15) => \apbi.pwdata[15]\, pwdata(14) => - \apbi.pwdata[14]\, pwdata(13) => \apbi.pwdata[13]\, - pwdata(12) => \apbi.pwdata[12]\, pwdata(11) => - \apbi.pwdata[11]\, pwdata(10) => \apbi.pwdata[10]\, - pwdata(9) => \apbi.pwdata[9]\, pwdata(8) => - \apbi.pwdata[8]\, pwdata(7) => \apbi.pwdata[7]\, - pwdata(6) => \apbi.pwdata[6]\, pwdata(5) => - \apbi.pwdata[5]\, pwdata(4) => \apbi.pwdata[4]\, - pwdata(3) => \apbi.pwdata[3]\, pwdata(2) => - \apbi.pwdata[2]\, pwdata(1) => \apbi.pwdata[1]\, - pwdata(0) => \apbi.pwdata[0]\, psel_1(7) => - \apbi.psel_1[7]\, prdata_4(31) => \apbo_15.prdata[31]\, - rdata_iv_0_2(1) => \ua1.uart1.rdata_iv_0_2[1]\, - prdata_iv_0_0(2) => \gpio0.grgpio0.apbo.prdata_iv_0_0[2]\, - ramrws(1) => \sr1.r.mcfg2.ramrws[1]\, ramwws(1) => - \sr1.r.mcfg2.ramwws[1]\, ramwws(0) => - \sr1.r.mcfg2.ramwws[0]\, romrws(3) => - \sr1.r.mcfg1.romrws[3]\, romrws(2) => - \sr1.r.mcfg1.romrws[2]\, romrws(1) => - \sr1.r.mcfg1.romrws[1]\, prdata_iv_0_2 => - \gpio0.grgpio0.apbo.prdata_iv_0[3]\, prdata_iv_0_0_d0 => - \gpio0.grgpio0.apbo.prdata_iv_0[1]\, un1_grgpio0_0 => - \gpio0.un1_grgpio0[69]\, un1_grgpio0_2 => - \gpio0.un1_grgpio0[71]\, ramwidth(1) => - \sr1.r.mcfg2.ramwidth[1]\, ramwidth(0) => - \sr1.r.mcfg2.ramwidth[0]\, rdata_iv_2(3) => - \ua1.uart1.rdata_iv_2[3]\, rdata_iv_2(2) => - \ua1.uart1.rdata_iv_2[2]\, readdata_iv_3(3) => - \gpt.timer0.readdata_iv_3[3]\, readdata_iv_3(2) => - \gpt.timer0.readdata_iv_3[2]\, tcnt(1) => - \ua1.uart1.r.tcnt[1]\, tcnt(0) => \ua1.uart1.r.tcnt[0]\, - prdata_3_29 => \apbo_14.prdata[31]\, prdata_3_12 => - \apbo_15.prdata[14]\, prdata_3_0 => \apbo_15.prdata[2]\, - prdata_3_1 => \apbo_13.prdata[3]\, prdata_3_14 => - \apbo_13.prdata[16]\, prdata_3_13 => \apbo_13.prdata[15]\, - prdata_3_26 => \apbo_14.prdata[28]\, prdata_3_23 => - \apbo_13.prdata[25]\, prdata_3_16 => \apbo_13.prdata[18]\, - prdata_3_28 => \apbo_13.prdata[30]\, prdata_3_27 => - \apbo_13.prdata[29]\, prdata_3_17 => \apbo_13.prdata[19]\, - prdata_3_15 => \apbo_14.prdata[17]\, romwws(3) => - \sr1.r.mcfg1.romwws[3]\, romwws(2) => - \sr1.r.mcfg1.romwws[2]\, romwws(1) => - \sr1.r.mcfg1.romwws[1]\, romwws(0) => - \sr1.r.mcfg1.romwws[0]\, romwidth(1) => - \sr1.r.mcfg1.romwidth[1]\, romwidth(0) => - \sr1.r.mcfg1.romwidth[0]\, rambanksz_0 => - \sr1.r.mcfg2.rambanksz[0]\, rambanksz_1 => - \sr1.r.mcfg2.rambanksz[1]\, rambanksz_3 => - \sr1.r.mcfg2.rambanksz[3]\, prdata_0_iv_0_0_0_13 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[14]\, - prdata_0_iv_0_0_0_0 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[1]\, - prdata_0_iv_0_0_0_12 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_0[13]\, - prdata_0_iv_0_0_1_13 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[14]\, - prdata_0_iv_0_0_1_0 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[1]\, - prdata_0_iv_0_0_1_12 => - \irqctrl.irqctrl0.prdata_0_iv_0_0_1[13]\, - readdata_1_iv_0_13 => \gpt.timer0.readdata_1_iv_0[26]\, - readdata_1_iv_0_2 => \gpt.timer0.readdata_1_iv_0[15]\, - readdata_1_iv_0_0 => \gpt.timer0.readdata_1_iv_0[13]\, - readdata_1_iv_0_9 => \gpt.timer0.readdata_1_iv_0[22]\, - readdata_1_iv_0_11 => \gpt.timer0.readdata_1_iv_0[24]\, - prdata_2_20 => \apbo_15.prdata[20]\, prdata_2_31 => - \apbo_13.prdata[31]\, prdata_2_14 => \apbo_13.prdata[14]\, - prdata_2_1 => \apbo_13.prdata[1]\, prdata_2_2 => - \apbo_13.prdata[2]\, prdata_2_5 => \apbo_7.prdata[5]\, - prdata_2_0 => \apbo_15.prdata[0]\, prdata_2_3 => - \apbo_15.prdata[3]\, prdata_2_16 => \apbo_15.prdata[16]\, - prdata_2_21 => \apbo_14.prdata[21]\, prdata_2_23 => - \apbo_13.prdata[23]\, prdata_2_15 => \apbo_15.prdata[15]\, - prdata_2_27 => \apbo_14.prdata[27]\, prdata_2_28 => - \apbo_15.prdata[28]\, prdata_2_25 => \apbo_15.prdata[25]\, - prdata_2_18 => \apbo_14.prdata[18]\, prdata_2_30 => - \apbo_14.prdata[30]\, prdata_2_29 => \apbo_14.prdata[29]\, - prdata_2_19 => \apbo_14.prdata[19]\, prdata_2_17 => - \apbo_15.prdata[17]\, prdata_2_9 => \apbo_13.prdata[9]\, - prdata_2_13 => \apbo_13.prdata[13]\, prdata_2_22 => - \apbo_13.prdata[22]\, prdata_2_24 => \apbo_13.prdata[24]\, - prdata_2_26 => \apbo_13.prdata[26]\, prdata_11_m_1_0(4) - => \irqctrl.irqctrl0.prdata_11_m_1_0[4]\, - prdata_13_m_1_0(4) => - \irqctrl.irqctrl0.prdata_13_m_1_0[4]\, psel_0 => - \apbi.psel[0]\, psel_15 => \apbi.psel[15]\, psel_11 => - \apbi.psel[11]\, reload_RNI6SNI(1) => - \r.reload_RNI6SNI[1]\, readdata_9_i_m(1) => - \gpt.timer0.comb.1.readdata_9_i_m[1]\, un1_uart1(36) => - \ua1.un1_uart1[36]\, reload_m_0(0) => - \gpt.timer0.r.reload_m[0]\, reload_0(7) => - \gpt.timer0.r.reload[7]\, reload_0(6) => - \gpt.timer0.r.reload[6]\, un1_dcom0(19) => - \dcomgen.un1_dcom0[19]\, un1_dcom0(18) => - \dcomgen.un1_dcom0[18]\, un1_dcom0(17) => - \dcomgen.un1_dcom0[17]\, un1_dcom0(16) => - \dcomgen.un1_dcom0[16]\, un1_dcom0(15) => - \dcomgen.un1_dcom0[15]\, un1_dcom0(14) => - \dcomgen.un1_dcom0[14]\, un1_dcom0(13) => - \dcomgen.un1_dcom0[13]\, un1_dcom0(12) => - \dcomgen.un1_dcom0[12]\, iows(3) => \sr1.r.mcfg1.iows[3]\, - iows(2) => \sr1.r.mcfg1.iows[2]\, ipend(11) => - \irqctrl.irqctrl0.r.ipend[11]\, iforce_0_m(4) => - \irqctrl.irqctrl0.r.iforce_0_m[4]\, ipend_m(4) => - \irqctrl.irqctrl0.r.ipend_m[4]\, iforce_0_5 => - \irqctrl.irqctrl0.r.iforce_0[10]\, iforce_0_2 => - \irqctrl.irqctrl0.r.iforce_0[7]\, iforce_0_1 => - \irqctrl.irqctrl0.r.iforce_0[6]\, iforce_0_7 => - \irqctrl.irqctrl0.r.iforce_0[12]\, iforce_0_0 => - \irqctrl.irqctrl0.r.iforce_0[5]\, ilevel_6 => - \irqctrl.irqctrl0.r.ilevel[10]\, ilevel_4 => - \irqctrl.irqctrl0.r.ilevel[8]\, ilevel_3 => - \irqctrl.irqctrl0.r.ilevel[7]\, ilevel_2 => - \irqctrl.irqctrl0.r.ilevel[6]\, ilevel_0 => - \irqctrl.irqctrl0.r.ilevel[4]\, ilevel_8 => - \irqctrl.irqctrl0.r.ilevel[12]\, ilevel_1 => - \irqctrl.irqctrl0.r.ilevel[5]\, oen(7) => \gpioo.oen[7]\, - readdata_2_m(5) => \gpio0.grgpio0.comb.readdata_2_m[5]\, - dout_2 => \gpioo.dout[3]\, dout_0 => \gpioo.dout[1]\, - dout_6 => \gpioo.dout[7]\, dout_5 => \gpioo.dout[6]\, - dout_4 => \gpioo.dout[5]\, value_RNIBAHH(1) => - \r.timers_2.value_RNIBAHH[1]\, reload_RNIRDRG(1) => - \r.timers_2.reload_RNIRDRG[1]\, scaler_i_m(1) => - \gpt.timer0.r.scaler_i_m[1]\, scaler(4) => - \gpt.timer0.r.scaler[4]\, value_6 => - \gpt.timer0.r.timers_2.value[6]\, value_0 => - \gpt.timer0.r.timers_2.value[0]\, reload_8 => - \gpt.timer0.r.timers_2.reload[12]\, reload_7 => - \gpt.timer0.r.timers_2.reload[11]\, reload_6 => - \gpt.timer0.r.timers_2.reload[10]\, reload_24 => - \gpt.timer0.r.timers_2.reload[28]\, reload_4 => - \gpt.timer0.r.timers_2.reload[8]\, reload_3 => - \gpt.timer0.r.timers_2.reload[7]\, reload_2 => - \gpt.timer0.r.timers_2.reload[6]\, reload_0_d0 => - \gpt.timer0.r.timers_2.reload[4]\, reload_1 => - \gpt.timer0.r.timers_2.reload[5]\, scaler_m_7 => - \gpt.timer0.r.scaler_m[7]\, scaler_m_6 => - \gpt.timer0.r.scaler_m[6]\, scaler_m_0 => - \gpt.timer0.r.scaler_m[0]\, scaler_m_5 => - \gpt.timer0.r.scaler_m[5]\, rcnt(1) => - \ua1.uart1.r.rcnt[1]\, rcnt(0) => \ua1.uart1.r.rcnt[0]\, - rdata_2(0) => \ua1.uart1.uartop.rdata_2[0]\, - rcnt_RNI8FBM3(1) => \r.rcnt_RNI8FBM3[1]\, - rdata_iv_0_a2_3_0(7) => \ua1.uart1.rdata_iv_0_a2_3_0[7]\, - brate_9 => \ua1.uart1.r.brate[9]\, brate_8 => - \ua1.uart1.r.brate[8]\, brate_0 => \ua1.uart1.r.brate[0]\, - brate_10 => \ua1.uart1.r.brate[10]\, brate_7 => - \ua1.uart1.r.brate[7]\, brate_6 => \ua1.uart1.r.brate[6]\, - rdata_17_m_0(6) => \ua1.uart1.uartop.rdata_17_m_0[6]\, - brate_m_7 => \ua1.uart1.r.brate_m[11]\, brate_m_0 => - \ua1.uart1.r.brate_m[4]\, brate_m_1 => - \ua1.uart1.r.brate_m[5]\, rdata_17_m_0_d0 => - \ua1.uart1.uartop.rdata_17_m[0]\, rdata_17_m_4 => - \ua1.uart1.uartop.rdata_17_m[4]\, rdata_17_m_5 => - \ua1.uart1.uartop.rdata_17_m[5]\, rdata_2_m(6) => - \ua1.uart1.uartop.rdata_2_m[6]\, rdata_2_m(5) => - \ua1.uart1.uartop.rdata_2_m[5]\, rdata_2_m(4) => - \ua1.uart1.uartop.rdata_2_m[4]\, prdata_1_20 => - \apbo_14.prdata[20]\, prdata_1_5 => \apbo_13.prdata[5]\, - prdata_1_12 => \apbo_13.prdata[12]\, prdata_1_21 => - \apbo_15.prdata[21]\, prdata_1_23 => \apbo_14.prdata[23]\, - prdata_1_27 => \apbo_15.prdata[27]\, prdata_1_0 => - \apbo_13.prdata[0]\, prdata_1_4 => \apbo_13.prdata[4]\, - prdata_1_6 => \apbo_13.prdata[6]\, prdata_1_7 => - \apbo_13.prdata[7]\, prdata_1_8 => \apbo_13.prdata[8]\, - prdata_1_9 => \apbo_15.prdata[9]\, prdata_1_10 => - \apbo_13.prdata[10]\, prdata_1_11 => \apbo_13.prdata[11]\, - prdata_1_22 => \apbo_15.prdata[22]\, prdata_1_28 => - \apbo_13.prdata[28]\, paddr_5 => \apbi.paddr[7]\, - paddr_2_d0 => \apbi.paddr[4]\, paddr_0_d0 => - \apbi.paddr[2]\, paddr_1_d0 => \apbi.paddr[3]\, paddr_3 - => \apbi.paddr[5]\, paddr_4 => \apbi.paddr[6]\, - htrans(1) => \ahbsi.htrans[1]\, iosn_0(93) => - \sr1.iosn_0[93]\, readdata_9_4 => - \gpt.timer0.comb.1.readdata_9[4]\, readdata_9_0 => - \gpt.timer0.comb.1.readdata_9[0]\, readdata_9_5 => - \gpt.timer0.comb.1.readdata_9[5]\, readdata_9_27 => - \gpt.timer0.comb.1.readdata_9[27]\, reload_m_2 => - \gpt.timer0.r.reload_m[2]\, reload_m_3 => - \gpt.timer0.r.reload_m[3]\, reload_m_21 => - \gpt.timer0.r.timers_2.reload_m[21]\, reload_m_9 => - \gpt.timer0.r.timers_2.reload_m[9]\, reload_m_0_d0 => - \gpt.timer0.r.timers_2.reload_m[0]\, reload_m_5 => - \gpt.timer0.r.reload_m[5]\, reload_m_27 => - \gpt.timer0.r.timers_2.reload_m[27]\, reload_m_20 => - \gpt.timer0.r.timers_2.reload_m[20]\, reload_m_4 => - \gpt.timer0.r.reload_m[4]\, value_m_22 => - \gpt.timer0.r.timers_2.value_m[26]\, value_m_11 => - \gpt.timer0.r.timers_2.value_m[15]\, value_m_9 => - \gpt.timer0.r.timers_2.value_m[13]\, value_m_18 => - \gpt.timer0.r.timers_2.value_m[22]\, value_m_20 => - \gpt.timer0.r.timers_2.value_m[24]\, value_m_17 => - \gpt.timer0.r.timers_2.value_m[21]\, value_m_4 => - \gpt.timer0.r.timers_2.value_m[8]\, value_m_5 => - \gpt.timer0.r.timers_2.value_m[9]\, value_m_3 => - \gpt.timer0.r.timers_2.value_m[7]\, value_m_0 => - \gpt.timer0.r.timers_2.value_m[4]\, value_m_1 => - \gpt.timer0.r.timers_2.value_m[5]\, value_m_8 => - \gpt.timer0.r.timers_2.value_m[12]\, value_m_7 => - \gpt.timer0.r.timers_2.value_m[11]\, value_m_6 => - \gpt.timer0.r.timers_2.value_m[10]\, value_m_23 => - \gpt.timer0.r.timers_2.value_m[27]\, value_m_24 => - \gpt.timer0.r.timers_2.value_m[28]\, value_m_16 => - \gpt.timer0.r.timers_2.value_m[20]\, prdata_0_1 => - \apbo_15.prdata[1]\, prdata_0_23 => \apbo_15.prdata[23]\, - prdata_0_18 => \apbo_15.prdata[18]\, prdata_0_30 => - \apbo_15.prdata[30]\, prdata_0_29 => \apbo_15.prdata[29]\, - prdata_0_0 => \apbo_7.prdata[0]\, prdata_0_8 => - \apbo_14.prdata[8]\, prdata_0_10 => \apbo_15.prdata[10]\, - prdata_0_11 => \apbo_15.prdata[11]\, prdata_0_12 => - \apbo_15.prdata[12]\, prdata_0_13 => \apbo_15.prdata[13]\, - prdata_0_24 => \apbo_15.prdata[24]\, prdata_0_26 => - \apbo_15.prdata[26]\, prdata_0_17 => \apbo_3.prdata[17]\, - prdata_0_19 => \apbo_3.prdata[19]\, prdata_0_25 => - \apbo_3.prdata[25]\, prdata_0_16 => \apbo_3.prdata[16]\, - prdata_0_22 => \apbo_1.prdata[22]\, prdata_0_15 => - \apbo_14.prdata[15]\, prdata_0_31 => \apbo_3.prdata[31]\, - prdata_0_14 => \apbo_14.prdata[14]\, prdata_0_21 => - \apbo_13.prdata[21]\, prdata_0_27 => \apbo_13.prdata[27]\, - prdata_0_20 => \apbo_13.prdata[20]\, prdata_0_4 => - \apbo_15.prdata[4]\, prdata_0_6 => \apbo_15.prdata[6]\, - prdata_0_7 => \apbo_15.prdata[7]\, prdata_0_5 => - \apbo_15.prdata[5]\, prdata_0_3 => \apbo_14.prdata[3]\, - prdata_0_2 => \apbo_14.prdata[2]\, prdata_0_28 => - \apbo_1.prdata[28]\, prdata(31) => \apbo_1.prdata[31]\, - prdata(30) => \apbo_3.prdata[30]\, prdata(29) => - \apbo_3.prdata[29]\, prdata(28) => \apbo_0.prdata[28]\, - prdata(27) => \apbo_0.prdata[27]\, prdata(26) => - \apbo_14.prdata[26]\, prdata(25) => \apbo_14.prdata[25]\, - prdata(24) => \apbo_14.prdata[24]\, prdata(23) => - \apbo_3.prdata[23]\, prdata(22) => \apbo_14.prdata[22]\, - prdata(21) => \apbo_0.prdata[21]\, prdata(20) => - \apbo_0.prdata[20]\, prdata(19) => \apbo_15.prdata[19]\, - prdata(18) => \apbo_3.prdata[18]\, prdata(17) => - \apbo_13.prdata[17]\, prdata(16) => \apbo_14.prdata[16]\, - prdata(15) => \apbo_2.prdata[15]\, prdata(14) => - \apbo_3.prdata[14]\, prdata(13) => \apbo_14.prdata[13]\, - prdata(12) => \apbo_14.prdata[12]\, prdata(11) => - \apbo_14.prdata[11]\, prdata(10) => \apbo_14.prdata[10]\, - prdata(9) => \apbo_14.prdata[9]\, prdata(8) => - \apbo_15.prdata[8]\, prdata(7) => \apbo_14.prdata[7]\, - prdata(6) => \apbo_14.prdata[6]\, prdata(5) => - \apbo_14.prdata[5]\, prdata(4) => \apbo_14.prdata[4]\, - prdata(3) => \apbo_2.prdata[3]\, prdata(2) => - \apbo_2.prdata[2]\, prdata(1) => \apbo_14.prdata[1]\, - prdata(0) => \apbo_14.prdata[0]\, pwdata_i(7) => - \apbi.pwdata_i[7]\, pwdata_i(6) => \apbi.pwdata_i[6]\, - pwdata_i(5) => \apbi.pwdata_i[5]\, pwdata_i(4) => - \apbi.pwdata_i[4]\, pwdata_i(3) => \apbi.pwdata_i[3]\, - pwdata_i(2) => \apbi.pwdata_i[2]\, pwdata_i(1) => - \apbi.pwdata_i[1]\, pwdata_i(0) => \apbi.pwdata_i[0]\, - pwdata_1_3 => \apbi.pwdata_1[4]\, pwdata_1_2 => - \apbi.pwdata_1[3]\, pwdata_1_0 => \apbi.pwdata_1[1]\, - hwdata(31) => \ahbsi.hwdata[31]\, hwdata(30) => - \ahbsi.hwdata[30]\, hwdata(29) => \ahbsi.hwdata[29]\, - hwdata(28) => \ahbsi.hwdata[28]\, hwdata(27) => - \ahbsi.hwdata[27]\, hwdata(26) => \ahbsi.hwdata[26]\, - hwdata(25) => \ahbsi.hwdata[25]\, hwdata(24) => - \ahbsi.hwdata[24]\, hwdata(23) => \ahbsi.hwdata[23]\, - hwdata(22) => \ahbsi.hwdata[22]\, hwdata(21) => - \ahbsi.hwdata[21]\, hwdata(20) => \ahbsi.hwdata[20]\, - hwdata(19) => \ahbsi.hwdata[19]\, hwdata(18) => - \ahbsi.hwdata[18]\, hwdata(17) => \ahbsi.hwdata[17]\, - hwdata(16) => \ahbsi.hwdata[16]\, hwdata(15) => - \ahbsi.hwdata[15]\, hwdata(14) => \ahbsi.hwdata[14]\, - hwdata(13) => \ahbsi.hwdata[13]\, hwdata(12) => - \ahbsi.hwdata[12]\, hwdata(11) => \ahbsi.hwdata[11]\, - hwdata(10) => \ahbsi.hwdata[10]\, hwdata(9) => - \ahbsi.hwdata[9]\, hwdata(8) => \ahbsi.hwdata[8]\, - hwdata(7) => \ahbsi.hwdata[7]\, hwdata(6) => - \ahbsi.hwdata[6]\, hwdata(5) => \ahbsi.hwdata[5]\, - hwdata(4) => \ahbsi.hwdata[4]\, hwdata(3) => - \ahbsi.hwdata[3]\, hwdata(2) => \ahbsi.hwdata[2]\, - hwdata(1) => \ahbsi.hwdata[1]\, hwdata(0) => - \ahbsi.hwdata[0]\, pwdata_0(15) => \apbi.pwdata_0[15]\, - pwdata_0(14) => \apbi.pwdata_0[14]\, pwdata_0(13) => - \apbi.pwdata_0[13]\, pwdata_0(12) => \apbi.pwdata_0[12]\, - pwdata_0(11) => \apbi.pwdata_0[11]\, pwdata_0(10) => - \apbi.pwdata_0[10]\, pwdata_0(9) => \apbi.pwdata_0[9]\, - pwdata_0(8) => \apbi.pwdata_0[8]\, pwdata_0(7) => - \apbi.pwdata_0[7]\, pwdata_0(6) => \apbi.pwdata_0[6]\, - pwdata_0(5) => \apbi.pwdata_0[5]\, pwdata_0(4) => - \apbi.pwdata_0[4]\, pwdata_0(3) => \apbi.pwdata_0[3]\, - pwdata_0(2) => \apbi.pwdata_0[2]\, pwdata_0(1) => - \apbi.pwdata_0[1]\, pwdata_0(0) => \apbi.pwdata_0[0]\, - paddr_0(4) => \apbi.paddr_0[4]\, paddr_0(3) => - \apbi.paddr_0[3]\, paddr_0(2) => \apbi.paddr_0[2]\, - paddr_1(2) => \apbi.paddr_1[2]\, haddr(19) => - \ahbsi.haddr[19]\, haddr(18) => \ahbsi.haddr[18]\, - haddr(17) => \ahbsi.haddr[17]\, haddr(16) => - \ahbsi.haddr[16]\, haddr(15) => \ahbsi.haddr[15]\, - haddr(14) => \ahbsi.haddr[14]\, haddr(13) => - \ahbsi.haddr[13]\, haddr(12) => \ahbsi.haddr[12]\, - haddr(11) => \ahbsi.haddr[11]\, haddr(10) => - \ahbsi.haddr[10]\, haddr(9) => \ahbsi.haddr[9]\, haddr(8) - => \ahbsi.haddr[8]\, haddr(7) => \ahbsi.haddr[7]\, - haddr(6) => \ahbsi.haddr[6]\, haddr(5) => - \ahbsi.haddr[5]\, haddr(4) => \ahbsi.haddr[4]\, haddr(3) - => \ahbsi.haddr[3]\, haddr(2) => \ahbsi.haddr[2]\, - paddr_2(2) => \apbi.paddr_2[2]\, hready => - \ahbso_1.hready\, readdata51_1 => - \gpt.timer0.comb.2.readdata51_1\, N_227 => - \ua1.uart1.N_227\, thempty_1_m => - \ua1.uart1.uartop.thempty_1_m\, N_6432 => N_6432, rmw => - \sr1.r.mcfg2.rmw\, penable => \apbi.penable\, un1_apbi_2 - => \gpt.timer0.comb.1.un1_apbi_2\, N_5062 => N_5062, - break_m => \ua1.uart1.r.break_m\, N_332 => - \dcomgen.dcom0.dcom_uart0.N_332\, N_333 => - \dcomgen.dcom0.dcom_uart0.N_333\, N_334 => - \dcomgen.dcom0.dcom_uart0.N_334\, N_335 => - \dcomgen.dcom0.dcom_uart0.N_335\, N_336 => - \dcomgen.dcom0.dcom_uart0.N_336\, N_5070 => N_5070, - breakirqen => \ua1.uart1.r.breakirqen\, N_6455_0 => - N_6455_0, N_773 => \apb0.N_773\, hwrite => \ahbsi.hwrite\, - un1_apbi_7_3 => \lfrtimemanagement_0.un1_apbi_7_3\, N_330 - => \dcomgen.dcom0.dcom_uart0.N_330\, parerr_m => - \ua1.uart1.r.parerr_m\, rdata60_1 => - \ua1.uart1.uartop.rdata60_1\, N_331 => - \dcomgen.dcom0.dcom_uart0.N_331\, N_86 => - \dcomgen.dcom0.dcom_uart0.N_86\, N_85 => - \dcomgen.dcom0.dcom_uart0.N_85\, un1_apbi_7_1 => - \lfrtimemanagement_0.un1_apbi_7_1\, rstn => rstn, bexcen - => \sr1.r.mcfg1.bexcen\, ioen => \sr1.r.mcfg1.ioen\, - ovf_m => \ua1.uart1.r.ovf_m\, parsel_m_0 => - \ua1.uart1.r.parsel_m_0\, frame => \ua1.uart1.r.frame\, - tcnt_i => \ua1.uart1.uartop.un1_r.tcnt_i\, N_156 => - \ua1.uart1.N_156\, readdata56 => - \gpt.timer0.comb.readdata56\, tfifoirqen_m => - \ua1.uart1.r.tfifoirqen_m\, rfifoirqen_m => - \ua1.uart1.r.rfifoirqen_m\, debug_m => - \ua1.uart1.r.debug_m\, delayirqen => - \ua1.uart1.r.delayirqen\, N_127 => - \dcomgen.dcom0.dcom_uart0.N_127\, N_78 => \apb0.N_78\, - N_232_0 => \ua1.uart1.N_232_0\, brdyen => - \sr1.r.mcfg1.brdyen\, N_839 => \irqctrl.irqctrl0.N_839\, - prdata_1_sqmuxa => \irqctrl.irqctrl0.prdata_1_sqmuxa\, - N_842 => \irqctrl.irqctrl0.N_842\, N_841 => - \irqctrl.irqctrl0.N_841\, N_476 => - \irqctrl.irqctrl0.N_476\, N_478 => - \irqctrl.irqctrl0.N_478\, N_474 => - \irqctrl.irqctrl0.N_474\, N_473 => - \irqctrl.irqctrl0.N_473\, N_471 => - \irqctrl.irqctrl0.N_471\, N_472 => - \irqctrl.irqctrl0.N_472\, N_470 => - \irqctrl.irqctrl0.N_470\, N_467 => - \irqctrl.irqctrl0.N_467\, N_468 => - \irqctrl.irqctrl0.N_468\, N_859 => - \irqctrl.irqctrl0.N_859\, N_861 => - \irqctrl.irqctrl0.N_861\, N_361 => - \irqctrl.irqctrl0.N_361\, N_363 => - \irqctrl.irqctrl0.N_363\, readdata55_3 => - \gpt.timer0.comb.readdata55_3\, N_863 => - \irqctrl.irqctrl0.N_863\, N_865 => - \irqctrl.irqctrl0.N_865\, N_365 => - \irqctrl.irqctrl0.N_365\, N_898 => - \irqctrl.irqctrl0.N_898\, N_367 => - \irqctrl.irqctrl0.N_367\, prdata_0_sqmuxa => - \irqctrl.irqctrl0.prdata_0_sqmuxa\, rdata60_4_0 => - \ua1.uart1.uartop.rdata60_4_0\, N_6437 => N_6437, N_6439 - => N_6439, N_6435 => N_6435, N_6436 => N_6436, N_6434 - => N_6434, N_6429 => N_6429, N_6430 => N_6430, N_6428 - => N_6428, rdata59_4 => \ua1.uart1.uartop.rdata59_4\, - N_220_0 => \gpt.timer0.N_220\, N_219 => - \gpt.timer0.N_219\, N_240 => \gpt.timer0.N_240\, N_218 - => \gpt.timer0.N_218\, N_236 => \gpt.timer0.N_236\, - N_229 => \gpt.timer0.N_229\, N_228 => \gpt.timer0.N_228\, - N_216 => \gpt.timer0.N_216\, N_217 => \gpt.timer0.N_217\, - dishlt => \gpt.timer0.r.dishlt\, restart_RNIIKBB => - \r.timers_2.restart_RNIIKBB\, N_215 => \gpt.timer0.N_215\, - N_214 => \gpt.timer0.N_214\, N_240_0 => - \gpt.timer0.N_240_0\, readdata57 => - \gpt.timer0.comb.readdata57\, irqpen_m => - \gpt.timer0.r.timers_2.irqpen_m\, readdata55 => - \gpt.timer0.comb.readdata55\, enable_m => - \gpt.timer0.r.timers_2.enable_m\, value_0_sqmuxa_0 => - \gpt.timer0.v.timers_2.value_0_sqmuxa_0\, chain_m => - \gpt.timer0.r.timers_2.chain_m\, readdata_1_sqmuxa_1_0 - => \gpt.timer0.readdata_1_sqmuxa_1_0\, tsemptyirqen => - \ua1.uart1.r.tsemptyirqen\, rdata_0_sqmuxa => - \ua1.uart1.rdata_0_sqmuxa\, N_223 => \ua1.uart1.N_223\, - N_220 => \ua1.uart1.N_220\, rdata_3_sqmuxa => - \ua1.uart1.rdata_3_sqmuxa\, rdata_4_sqmuxa => - \ua1.uart1.rdata_4_sqmuxa\, paren => \ua1.uart1.r.paren\, - N_770 => \apb0.N_770\, rhalffull_1_m => - \ua1.uart1.uartop.rhalffull_1_m\, flow_m => - \ua1.uart1.r.flow_m\, extclken_m => - \ua1.uart1.r.extclken_m\, N_769 => \apb0.N_769\, N_116 - => \apb0.N_116\, N_796 => \apb0.N_796\, N_750 => - \apb0.N_750\, N_749 => \apb0.N_749\, lclk_c => lclk_c, - pwrite => \apbi.pwrite\, un51_ioen_NE => - \ahb0.comb.1.4.un51_ioen_NE\); - - \address_pad[0]\ : OUTBUF - port map(D => \address_c[0]\, PAD => address(0)); - - \pci_ad_pad[26]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(26)); - - lclk_RNIU342 : CLKINT - port map(A => lclk_i, Y => lclk_c); - - nOE_pad : OUTBUF - port map(D => \state_RNIFS55[4]\, PAD => nOE); - - \data_pad[16]\ : BIBUF - port map(PAD => data(16), D => \memo.data[16]\, E => - \memo.bdrive_i[1]\, Y => \data_in[16]\); - - nBWb_pad : OUTBUF - port map(D => nBWb_c, PAD => nBWb); - - cnv_ch1_pad : OUTBUF - port map(D => cnv_ch1_c, PAD => cnv_ch1); - - \address_pad[14]\ : OUTBUF - port map(D => \address_c[14]\, PAD => address(14)); - - \ocram.ahbram0\ : ahbram - port map(hwdata(31) => \ahbsi.hwdata[31]\, hwdata(30) => - \ahbsi.hwdata[30]\, hwdata(29) => \ahbsi.hwdata[29]\, - hwdata(28) => \ahbsi.hwdata[28]\, hwdata(27) => - \ahbsi.hwdata[27]\, hwdata(26) => \ahbsi.hwdata[26]\, - hwdata(25) => \ahbsi.hwdata[25]\, hwdata(24) => - \ahbsi.hwdata[24]\, hwdata(23) => \ahbsi.hwdata[23]\, - hwdata(22) => \ahbsi.hwdata[22]\, hwdata(21) => - \ahbsi.hwdata[21]\, hwdata(20) => \ahbsi.hwdata[20]\, - hwdata(19) => \ahbsi.hwdata[19]\, hwdata(18) => - \ahbsi.hwdata[18]\, hwdata(17) => \ahbsi.hwdata[17]\, - hwdata(16) => \ahbsi.hwdata[16]\, hwdata(15) => - \ahbsi.hwdata[15]\, hwdata(14) => \ahbsi.hwdata[14]\, - hwdata(13) => \ahbsi.hwdata[13]\, hwdata(12) => - \ahbsi.hwdata[12]\, hwdata(11) => \ahbsi.hwdata[11]\, - hwdata(10) => \ahbsi.hwdata[10]\, hwdata(9) => - \ahbsi.hwdata[9]\, hwdata(8) => \ahbsi.hwdata[8]\, - hwdata(7) => \ahbsi.hwdata[7]\, hwdata(6) => - \ahbsi.hwdata[6]\, hwdata(5) => \ahbsi.hwdata[5]\, - hwdata(4) => \ahbsi.hwdata[4]\, hwdata(3) => - \ahbsi.hwdata[3]\, hwdata(2) => \ahbsi.hwdata[2]\, - hwdata(1) => \ahbsi.hwdata[1]\, hwdata(0) => - \ahbsi.hwdata[0]\, hrdata(31) => \ahbso_7.hrdata[31]\, - hrdata(30) => \ahbso_7.hrdata[30]\, hrdata(29) => - \ahbso_7.hrdata[29]\, hrdata(28) => \ahbso_7.hrdata[28]\, - hrdata(27) => \ahbso_7.hrdata[27]\, hrdata(26) => - \ahbso_7.hrdata[26]\, hrdata(25) => \ahbso_7.hrdata[25]\, - hrdata(24) => \ahbso_7.hrdata[24]\, hrdata(23) => - \ahbso_7.hrdata[23]\, hrdata(22) => \ahbso_7.hrdata[22]\, - hrdata(21) => \ahbso_7.hrdata[21]\, hrdata(20) => - \ahbso_7.hrdata[20]\, hrdata(19) => \ahbso_7.hrdata[19]\, - hrdata(18) => \ahbso_7.hrdata[18]\, hrdata(17) => - \ahbso_7.hrdata[17]\, hrdata(16) => \ahbso_7.hrdata[16]\, - hrdata(15) => \ahbso_7.hrdata[15]\, hrdata(14) => - \ahbso_7.hrdata[14]\, hrdata(13) => \ahbso_7.hrdata[13]\, - hrdata(12) => \ahbso_7.hrdata[12]\, hrdata(11) => - \ahbso_7.hrdata[11]\, hrdata(10) => \ahbso_7.hrdata[10]\, - hrdata(9) => \ahbso_7.hrdata[9]\, hrdata(8) => - \ahbso_7.hrdata[8]\, hrdata(7) => \ahbso_7.hrdata[7]\, - hrdata(6) => \ahbso_7.hrdata[6]\, hrdata(5) => - \ahbso_7.hrdata[5]\, hrdata(4) => \ahbso_7.hrdata[4]\, - hrdata(3) => \ahbso_7.hrdata[3]\, hrdata(2) => - \ahbso_7.hrdata[2]\, hrdata(1) => \ahbso_7.hrdata[1]\, - hrdata(0) => \ahbso_7.hrdata[0]\, hsize(1) => - \ahbsi.hsize[1]\, hsize(0) => \ahbsi.hsize[0]\, iosn(93) - => \sr1.iosn[93]\, htrans(1) => \ahbsi.htrans[1]\, - iosn_1(93) => \sr1.iosn_1[93]\, haddr(9) => - \ahbsi.haddr[9]\, haddr(8) => \ahbsi.haddr[8]\, haddr(7) - => \ahbsi.haddr[7]\, haddr(6) => \ahbsi.haddr[6]\, - haddr(5) => \ahbsi.haddr[5]\, haddr(4) => - \ahbsi.haddr[4]\, haddr(3) => \ahbsi.haddr[3]\, haddr(2) - => \ahbsi.haddr[2]\, haddr(1) => \ahbsi.haddr[1]\, - haddr(0) => \ahbsi.haddr[0]\, lclk_c => lclk_c, - un315_ioen_NE => \ahb0.comb.7.4.un315_ioen_NE\, hready - => \ahbso_7.hready\, hwrite_1 => \ahbsi.hwrite\, rstn - => rstn); - - \gpio_pad[4]\ : BIBUF - port map(PAD => gpio(4), D => \gpioo.dout[4]\, E => - \gpioo.oen_i[4]\, Y => \gpio_in[4]\); - - \data_pad[21]\ : BIBUF - port map(PAD => data(21), D => \memo.data[21]\, E => - \memo.bdrive_i[1]\, Y => \data_in[21]\); - - VCC_i : VCC - port map(Y => \VCC\); - - \address_pad[12]\ : OUTBUF - port map(D => \address_c[12]\, PAD => address(12)); - - resetn_pad : CLKBUF - port map(PAD => resetn, Y => rstraw_c); - - dsuact_pad : OUTBUF - port map(D => \GND\, PAD => dsuact); - - txd1_pad : OUTBUF - port map(D => txd1_c, PAD => txd1); - - SSRAM_CLK_pad : OUTBUF - port map(D => clk_c_i, PAD => SSRAM_CLK); - - esleep_pad : OUTBUF - port map(D => \GND\, PAD => esleep); - - \data_pad[28]\ : BIBUF - port map(PAD => data(28), D => \memo.data[28]\, E => - \memo.bdrive_i[0]\, Y => \data_in[28]\); - - pci_serr_pad : OUTBUF - port map(D => \GND\, PAD => pci_serr); - - pci_par_pad : OUTBUF - port map(D => \GND\, PAD => pci_par); - - lpp_bootloader_1 : lpp_bootloader - port map(haddr(9) => \ahbsi.haddr[9]\, haddr(8) => - \ahbsi.haddr[8]\, haddr(7) => \ahbsi.haddr[7]\, haddr(6) - => \ahbsi.haddr[6]\, haddr(5) => \ahbsi.haddr[5]\, - haddr(4) => \ahbsi.haddr[4]\, haddr(3) => - \ahbsi.haddr[3]\, haddr(2) => \ahbsi.haddr[2]\, hrdata_26 - => \ahbso_6.hrdata[26]\, hrdata_13 => - \ahbso_6.hrdata[13]\, hrdata_8 => \ahbso_6.hrdata[8]\, - hrdata_5 => \ahbso_6.hrdata[5]\, hrdata_29 => - \ahbso_6.hrdata[29]\, hrdata_18 => \ahbso_6.hrdata[18]\, - hrdata_6 => \ahbso_6.hrdata[6]\, hrdata_19 => - \ahbso_6.hrdata[19]\, hrdata_17 => \ahbso_6.hrdata[17]\, - hrdata_7 => \ahbso_6.hrdata[7]\, hrdata_16 => - \ahbso_6.hrdata[16]\, hrdata_30 => \ahbso_6.hrdata[30]\, - hrdata_9 => \ahbso_6.hrdata[9]\, hrdata_25 => - \ahbso_6.hrdata[25]\, hrdata_27 => \ahbso_6.hrdata[27]\, - hrdata_21 => \ahbso_6.hrdata[21]\, hrdata_3 => - \ahbso_6.hrdata[3]\, hrdata_0 => \ahbso_6.hrdata[0]\, - hrdata_1 => \ahbso_6.hrdata[1]\, hrdata_23 => - \ahbso_6.hrdata[23]\, hrdata_4 => \ahbso_6.hrdata[4]\, - hrdata_28 => \ahbso_6.hrdata[28]\, hrdata_14 => - \ahbso_6.hrdata[14]\, hrdata_22 => \ahbso_6.hrdata[22]\, - hrdata_15 => \ahbso_6.hrdata[15]\, hrdata_2 => - \ahbso_6.hrdata[2]\, hrdata_11 => \ahbso_6.hrdata[11]\, - hrdata_10 => \ahbso_6.hrdata[10]\, hrdata_12 => - \ahbso_6.hrdata[12]\, prdata(31) => \apbo_13.prdata[31]\, - prdata(30) => \apbo_13.prdata[30]\, prdata(29) => - \apbo_13.prdata[29]\, prdata(28) => \apbo_13.prdata[28]\, - prdata(27) => \apbo_13.prdata[27]\, prdata(26) => - \apbo_13.prdata[26]\, prdata(25) => \apbo_13.prdata[25]\, - prdata(24) => \apbo_13.prdata[24]\, prdata(23) => - \apbo_13.prdata[23]\, prdata(22) => \apbo_13.prdata[22]\, - prdata(21) => \apbo_13.prdata[21]\, prdata(20) => - \apbo_13.prdata[20]\, prdata(19) => \apbo_13.prdata[19]\, - prdata(18) => \apbo_13.prdata[18]\, prdata(17) => - \apbo_13.prdata[17]\, prdata(16) => \apbo_13.prdata[16]\, - prdata(15) => \apbo_13.prdata[15]\, prdata(14) => - \apbo_13.prdata[14]\, prdata(13) => \apbo_13.prdata[13]\, - prdata(12) => \apbo_13.prdata[12]\, prdata(11) => - \apbo_13.prdata[11]\, prdata(10) => \apbo_13.prdata[10]\, - prdata(9) => \apbo_13.prdata[9]\, prdata(8) => - \apbo_13.prdata[8]\, prdata(7) => \apbo_13.prdata[7]\, - prdata(6) => \apbo_13.prdata[6]\, prdata(5) => - \apbo_13.prdata[5]\, prdata(4) => \apbo_13.prdata[4]\, - prdata(3) => \apbo_13.prdata[3]\, prdata(2) => - \apbo_13.prdata[2]\, prdata(1) => \apbo_13.prdata[1]\, - prdata(0) => \apbo_13.prdata[0]\, pwdata_1_3 => - \apbi.pwdata_1[4]\, pwdata_1_2 => \apbi.pwdata_1[3]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, pwdata_31 => - \apbi.pwdata[31]\, pwdata_30 => \apbi.pwdata[30]\, - pwdata_29 => \apbi.pwdata[29]\, pwdata_28 => - \apbi.pwdata[28]\, pwdata_27 => \apbi.pwdata[27]\, - pwdata_26 => \apbi.pwdata[26]\, pwdata_25 => - \apbi.pwdata[25]\, pwdata_24 => \apbi.pwdata[24]\, - pwdata_23 => \apbi.pwdata[23]\, pwdata_22 => - \apbi.pwdata[22]\, pwdata_21 => \apbi.pwdata[21]\, - pwdata_20 => \apbi.pwdata[20]\, pwdata_19 => - \apbi.pwdata[19]\, pwdata_18 => \apbi.pwdata[18]\, - pwdata_17 => \apbi.pwdata[17]\, pwdata_16 => - \apbi.pwdata[16]\, pwdata_15 => \apbi.pwdata[15]\, - pwdata_14 => \apbi.pwdata[14]\, pwdata_13 => - \apbi.pwdata[13]\, pwdata_12 => \apbi.pwdata[12]\, - pwdata_11 => \apbi.pwdata[11]\, pwdata_10 => - \apbi.pwdata[10]\, pwdata_9 => \apbi.pwdata[9]\, pwdata_8 - => \apbi.pwdata[8]\, pwdata_7 => \apbi.pwdata[7]\, - pwdata_6 => \apbi.pwdata[6]\, pwdata_5 => - \apbi.pwdata[5]\, pwdata_2 => \apbi.pwdata[2]\, pwdata_0 - => \apbi.pwdata[0]\, N_103_i_0 => - \lpp_bootloader_1.ahbrom_1.N_103_i_0\, N_90_i_0 => - \lpp_bootloader_1.ahbrom_1.N_90_i_0\, N_95_i_0 => - \lpp_bootloader_1.ahbrom_1.N_95_i_0\, rstraw_c => - rstraw_c, lclk_c => lclk_c, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, N_6459 => N_6459, rdata59_4 - => \ua1.uart1.uartop.rdata59_4\, readdata55_3 => - \gpt.timer0.comb.readdata55_3\, rdata62_3 => - \ua1.uart1.uartop.rdata62_3\, N_750 => \apb0.N_750\, - un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\, rdata60_4_0 - => \ua1.uart1.uartop.rdata60_4_0\, N_796 => \apb0.N_796\); - - \pci_ad_pad[18]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(18)); - - \gpio_pad[5]\ : BIBUF - port map(PAD => gpio(5), D => \gpioo.dout[5]\, E => - \gpioo.oen_i[5]\, Y => \gpio_in[5]\); - - \sdo_adc_pad[7]\ : INBUF - port map(PAD => sdo_adc(7), Y => \sdo_adc_c[7]\); - - \data_pad[25]\ : BIBUF - port map(PAD => data(25), D => \memo.data[25]\, E => - \memo.bdrive_i[0]\, Y => \data_in[25]\); - - nBWd_pad : OUTBUF - port map(D => nBWd_c, PAD => nBWd); - - emddis_pad : OUTBUF - port map(D => \GND\, PAD => emddis); - - \address_pad[18]\ : OUTBUF - port map(D => \address_c[18]\, PAD => address(18)); - - \pci_ad_pad[7]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(7)); - - \data_pad[14]\ : BIBUF - port map(PAD => data(14), D => \memo.data[14]\, E => - \memo.bdrive_i[2]\, Y => \data_in[14]\); - - nCE1_pad : OUTBUF - port map(D => nCE1_c, PAD => nCE1); - - nGW_pad : OUTBUF - port map(D => \VCC\, PAD => nGW); - - \data_pad[7]\ : BIBUF - port map(PAD => data(7), D => \memo.data[7]\, E => - \memo.bdrive_i[3]\, Y => \data_in[7]\); - - nCE3_pad : OUTBUF - port map(D => nCE3_c, PAD => nCE3); - - iosn_pad : OUTBUF - port map(D => iosn_c, PAD => iosn); - - waveform_picker0 : lpp_top_lfr_wf_picker - port map(sdo_adc_c(7) => \sdo_adc_c[7]\, sdo_adc_c(6) => - \sdo_adc_c[6]\, sdo_adc_c(5) => \sdo_adc_c[5]\, - sdo_adc_c(4) => \sdo_adc_c[4]\, sdo_adc_c(3) => - \sdo_adc_c[3]\, sdo_adc_c(2) => \sdo_adc_c[2]\, - sdo_adc_c(1) => \sdo_adc_c[1]\, sdo_adc_c(0) => - \sdo_adc_c[0]\, hburst(2) => \ahbmo_3.hburst[2]\, - hburst(1) => \ahbmo_3.hburst[1]\, hburst(0) => - \ahbmo_3.hburst[0]\, htrans(1) => \ahbmo_3.htrans[1]\, - htrans(0) => \ahbmo_3.htrans[0]\, iosn_2(93) => - \sr1.iosn_2[93]\, hresp(0) => \ahbmi.hresp[0]\, - iosn_1(93) => \sr1.iosn_1[93]\, nhmaster_1_i(0) => - \ahb0.comb.nhmaster_1_i[0]\, hsize(1) => - \ahbmo_3.hsize[1]\, hsize(0) => \ahbmo_3.hsize[0]\, - hmaster_0(1) => \ahbsi.hmaster_0[1]\, haddr(31) => - \ahbmo_3.haddr[31]\, haddr(30) => \ahbmo_3.haddr[30]\, - haddr(29) => \ahbmo_3.haddr[29]\, haddr(28) => - \ahbmo_3.haddr[28]\, haddr(27) => \ahbmo_3.haddr[27]\, - haddr(26) => \ahbmo_3.haddr[26]\, haddr(25) => - \ahbmo_3.haddr[25]\, haddr(24) => \ahbmo_3.haddr[24]\, - haddr(23) => \ahbmo_3.haddr[23]\, haddr(22) => - \ahbmo_3.haddr[22]\, haddr(21) => \ahbmo_3.haddr[21]\, - haddr(20) => \ahbmo_3.haddr[20]\, haddr(19) => - \ahbmo_3.haddr[19]\, haddr(18) => \ahbmo_3.haddr[18]\, - haddr(17) => \ahbmo_3.haddr[17]\, haddr(16) => - \ahbmo_3.haddr[16]\, haddr(15) => \ahbmo_3.haddr[15]\, - haddr(14) => \ahbmo_3.haddr[14]\, haddr(13) => - \ahbmo_3.haddr[13]\, haddr(12) => \ahbmo_3.haddr[12]\, - haddr(11) => \ahbmo_3.haddr[11]\, haddr(10) => - \ahbmo_3.haddr[10]\, haddr(9) => \ahbmo_3.haddr[9]\, - haddr(8) => \ahbmo_3.haddr[8]\, haddr(7) => - \ahbmo_3.haddr[7]\, haddr(6) => \ahbmo_3.haddr[6]\, - haddr(5) => \ahbmo_3.haddr[5]\, haddr(4) => - \ahbmo_3.haddr[4]\, haddr(3) => \ahbmo_3.haddr[3]\, - haddr(2) => \ahbmo_3.haddr[2]\, haddr(1) => - \ahbmo_3.haddr[1]\, haddr(0) => \ahbmo_3.haddr[0]\, - bco_msb_1(1) => \ahb0.bco_msb_1[1]\, - hmaster_0_0_RNIFCVH1_0(1) => - \r.hmaster_0_0_RNIFCVH1_0[1]\, hgrant(3) => - \ahbmi.hgrant[3]\, iosn_0(93) => \sr1.iosn_0[93]\, - bco_msb_1_m(1) => \ahb0.bco_msb_1_m[1]\, - nhmaster_1_iv_0(1) => \ahb0.comb.nhmaster_1_iv_0[1]\, - l1_0_m(1) => \ahb0.l1_0_m[1]\, hwdata(31) => - \ahbmo_3.hwdata[31]\, hwdata(30) => \ahbmo_3.hwdata[30]\, - hwdata(29) => \ahbmo_3.hwdata[29]\, hwdata(28) => - \ahbmo_3.hwdata[28]\, hwdata(27) => \ahbmo_3.hwdata[27]\, - hwdata(26) => \ahbmo_3.hwdata[26]\, hwdata(25) => - \ahbmo_3.hwdata[25]\, hwdata(24) => \ahbmo_3.hwdata[24]\, - hwdata(23) => \ahbmo_3.hwdata[23]\, hwdata(22) => - \ahbmo_3.hwdata[22]\, hwdata(21) => \ahbmo_3.hwdata[21]\, - hwdata(20) => \ahbmo_3.hwdata[20]\, hwdata(19) => - \ahbmo_3.hwdata[19]\, hwdata(18) => \ahbmo_3.hwdata[18]\, - hwdata(17) => \ahbmo_3.hwdata[17]\, hwdata(16) => - \ahbmo_3.hwdata[16]\, hwdata(15) => \ahbmo_3.hwdata[15]\, - hwdata(14) => \ahbmo_3.hwdata[14]\, hwdata(13) => - \ahbmo_3.hwdata[13]\, hwdata(12) => \ahbmo_3.hwdata[12]\, - hwdata(11) => \ahbmo_3.hwdata[11]\, hwdata(10) => - \ahbmo_3.hwdata[10]\, hwdata(9) => \ahbmo_3.hwdata[9]\, - hwdata(8) => \ahbmo_3.hwdata[8]\, hwdata(7) => - \ahbmo_3.hwdata[7]\, hwdata(6) => \ahbmo_3.hwdata[6]\, - hwdata(5) => \ahbmo_3.hwdata[5]\, hwdata(4) => - \ahbmo_3.hwdata[4]\, hwdata(3) => \ahbmo_3.hwdata[3]\, - hwdata(2) => \ahbmo_3.hwdata[2]\, hwdata(1) => - \ahbmo_3.hwdata[1]\, hwdata(0) => \ahbmo_3.hwdata[0]\, - coarse_time(0) => \coarse_time[0]\, coarse_time_i(0) => - \coarse_time_i[0]\, pwdata_0(11) => \apbi.pwdata_0[11]\, - pwdata_0(10) => \apbi.pwdata_0[10]\, pwdata_0(9) => - \apbi.pwdata_0[9]\, pwdata_0(8) => \apbi.pwdata_0[8]\, - pwdata_0(7) => \apbi.pwdata_0[7]\, pwdata_0(6) => - \apbi.pwdata_0[6]\, pwdata_0(5) => \apbi.pwdata_0[5]\, - pwdata_0(4) => \apbi.pwdata_0[4]\, pwdata_0(3) => - \apbi.pwdata_0[3]\, pwdata_0(2) => \apbi.pwdata_0[2]\, - pwdata_0(1) => \apbi.pwdata_0[1]\, pwdata_0(0) => - \apbi.pwdata_0[0]\, paddr_0(4) => \apbi.paddr_0[4]\, - paddr_0(3) => \apbi.paddr_0[3]\, paddr_0(2) => - \apbi.paddr_0[2]\, paddr(7) => \apbi.paddr[7]\, paddr(6) - => \apbi.paddr[6]\, paddr(5) => \apbi.paddr[5]\, - paddr(4) => \apbi.paddr[4]\, paddr(3) => \apbi.paddr[3]\, - paddr_2(2) => \apbi.paddr_2[2]\, pwdata_1_2 => - \apbi.pwdata_1[3]\, pwdata_1_3 => \apbi.pwdata_1[4]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, pwdata(31) => - \apbi.pwdata[31]\, pwdata(30) => \apbi.pwdata[30]\, - pwdata(29) => \apbi.pwdata[29]\, pwdata(28) => - \apbi.pwdata[28]\, pwdata(27) => \apbi.pwdata[27]\, - pwdata(26) => \apbi.pwdata[26]\, pwdata(25) => - \apbi.pwdata[25]\, pwdata(24) => \apbi.pwdata[24]\, - pwdata(23) => \apbi.pwdata[23]\, pwdata(22) => - \apbi.pwdata[22]\, pwdata(21) => \apbi.pwdata[21]\, - pwdata(20) => \apbi.pwdata[20]\, pwdata(19) => - \apbi.pwdata[19]\, pwdata(18) => \apbi.pwdata[18]\, - pwdata(17) => \apbi.pwdata[17]\, pwdata(16) => - \apbi.pwdata[16]\, pwdata(15) => \apbi.pwdata[15]\, - pwdata(14) => \apbi.pwdata[14]\, pwdata(13) => - \apbi.pwdata[13]\, pwdata(12) => \apbi.pwdata[12]\, - pwdata(11) => \apbi.pwdata[11]\, pwdata(10) => - \apbi.pwdata[10]\, pwdata(9) => \apbi.pwdata[9]\, - pwdata(8) => \apbi.pwdata[8]\, pwdata(7) => - \apbi.pwdata[7]\, pwdata(6) => \apbi.pwdata[6]\, - pwdata(5) => \apbi.pwdata[5]\, pwdata(4) => - \apbi.pwdata[4]\, pwdata(3) => \apbi.pwdata[3]\, - pwdata(2) => \apbi.pwdata[2]\, pwdata(1) => - \apbi.pwdata[1]\, pwdata(0) => \apbi.pwdata[0]\, pirq(15) - => \apbi.pirq[15]\, prdata(31) => \apbo_14.prdata[31]\, - prdata(30) => \apbo_14.prdata[30]\, prdata(29) => - \apbo_14.prdata[29]\, prdata(28) => \apbo_14.prdata[28]\, - prdata(27) => \apbo_14.prdata[27]\, prdata(26) => - \apbo_14.prdata[26]\, prdata(25) => \apbo_14.prdata[25]\, - prdata(24) => \apbo_14.prdata[24]\, prdata(23) => - \apbo_14.prdata[23]\, prdata(22) => \apbo_14.prdata[22]\, - prdata(21) => \apbo_14.prdata[21]\, prdata(20) => - \apbo_14.prdata[20]\, prdata(19) => \apbo_14.prdata[19]\, - prdata(18) => \apbo_14.prdata[18]\, prdata(17) => - \apbo_14.prdata[17]\, prdata(16) => \apbo_14.prdata[16]\, - prdata(15) => \apbo_14.prdata[15]\, prdata(14) => - \apbo_14.prdata[14]\, prdata(13) => \apbo_14.prdata[13]\, - prdata(12) => \apbo_14.prdata[12]\, prdata(11) => - \apbo_14.prdata[11]\, prdata(10) => \apbo_14.prdata[10]\, - prdata(9) => \apbo_14.prdata[9]\, prdata(8) => - \apbo_14.prdata[8]\, prdata(7) => \apbo_14.prdata[7]\, - prdata(6) => \apbo_14.prdata[6]\, prdata(5) => - \apbo_14.prdata[5]\, prdata(4) => \apbo_14.prdata[4]\, - prdata(3) => \apbo_14.prdata[3]\, prdata(2) => - \apbo_14.prdata[2]\, prdata(1) => \apbo_14.prdata[1]\, - prdata(0) => \apbo_14.prdata[0]\, - lpp_top_lfr_wf_picker_VCC => \VCC\, clk49_152MHz_c => - clk49_152MHz_c, cnv_ch1_c => cnv_ch1_c, sck_ch1_c => - sck_ch1_c, lpp_top_lfr_wf_picker_GND => \GND\, IdlePhase - => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.IdlePhase\, - hwrite => \ahbmo_3.hwrite\, un1_dmain_6 => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.un1_dmain_6\, - arb_1 => \ahb0.comb.arb_1\, hbusreq_i_3 => - \ahbmo_3.hbusreq_i_3\, Lock_RNIU86D => - \DMAIn.Lock_RNIU86D\, un1_nhmaster_0_sqmuxa_1 => - \ahb0.un1_nhmaster_0_sqmuxa_1\, rstoutl_RNIGJKSJO => - rstoutl_RNIGJKSJO, m19_0_N_15_i_0_li => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_0_N_15_i_0_li\, - m19_a0_6_i_0 => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a0_6_i_0\, - m19_a1_6_i_0 => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a1_6_i_0\, - m26_m1_e => m26_m1_e, lclk_c => lclk_c, rstn => rstn, - N_232 => \ua1.uart1.N_232\, N_6455_0 => N_6455_0, - Bias_Fails_c => Bias_Fails_c, N_749 => \apb0.N_749\, - N_116 => \apb0.N_116\, N_769 => \apb0.N_769\, N_232_0 => - \ua1.uart1.N_232_0\, N_232_1 => \ua1.uart1.N_232_1\, - rdata61_2 => \ua1.uart1.uartop.rdata61_2\, N_6455 => - N_6455, un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\); - - nBWc_pad : OUTBUF - port map(D => nBWc_c, PAD => nBWc); - - \gpio_pad[0]\ : BIBUF - port map(PAD => gpio(0), D => \gpioo.dout[0]\, E => - \gpioo.oen_i[0]\, Y => \gpio_in[0]\); - - clk49_152MHz_pad : INBUF - port map(PAD => clk49_152MHz, Y => clk49_152MHz_c); - - \sdo_adc_pad[0]\ : INBUF - port map(PAD => sdo_adc(0), Y => \sdo_adc_c[0]\); - - \address_pad[9]\ : OUTBUF - port map(D => \address_c[9]\, PAD => address(9)); - - \data_pad[12]\ : BIBUF - port map(PAD => data(12), D => \memo.data[12]\, E => - \memo.bdrive_i[2]\, Y => \data_in[12]\); - - txd2_pad : OUTBUF - port map(D => \GND\, PAD => txd2); - - \pci_ad_pad[9]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(9)); - - \pci_ad_pad[17]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(17)); - - \pci_ad_pad[8]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(8)); - - pci_lock_pad : OUTBUF - port map(D => \GND\, PAD => pci_lock); - - \ramoen_pad[3]\ : OUTBUF - port map(D => \ramoen_c[3]\, PAD => ramoen(3)); - - \gpio_pad[1]\ : BIBUF - port map(PAD => gpio(1), D => \gpioo.dout[1]\, E => - \gpioo.oen_i[1]\, Y => \gpio_in[1]\); - - \sdo_adc_pad[3]\ : INBUF - port map(PAD => sdo_adc(3), Y => \sdo_adc_c[3]\); - - \romsn_pad[1]\ : OUTBUF - port map(D => \romsn_c[1]\, PAD => romsn(1)); - - \data_pad[31]\ : BIBUF - port map(PAD => data(31), D => \memo.data[31]\, E => - \memo.bdrive_i[0]\, Y => \data_in[31]\); - - \dcomgen.dcom0\ : ahbuart - port map(haddr(31) => \ahbmo_1.haddr[31]\, haddr(30) => - \ahbmo_1.haddr[30]\, haddr(29) => \ahbmo_1.haddr[29]\, - haddr(28) => \ahbmo_1.haddr[28]\, haddr(27) => - \ahbmo_1.haddr[27]\, haddr(26) => \ahbmo_1.haddr[26]\, - haddr(25) => \ahbmo_1.haddr[25]\, haddr(24) => - \ahbmo_1.haddr[24]\, haddr(23) => \ahbmo_1.haddr[23]\, - haddr(22) => \ahbmo_1.haddr[22]\, haddr(21) => - \ahbmo_1.haddr[21]\, haddr(20) => \ahbmo_1.haddr[20]\, - haddr(19) => \ahbmo_1.haddr[19]\, haddr(18) => - \ahbmo_1.haddr[18]\, haddr(17) => \ahbmo_1.haddr[17]\, - haddr(16) => \ahbmo_1.haddr[16]\, haddr(15) => - \ahbmo_1.haddr[15]\, haddr(14) => \ahbmo_1.haddr[14]\, - haddr(13) => \ahbmo_1.haddr[13]\, haddr(12) => - \ahbmo_1.haddr[12]\, haddr(11) => \ahbmo_1.haddr[11]\, - haddr(10) => \ahbmo_1.haddr[10]\, haddr(9) => - \ahbmo_1.haddr[9]\, haddr(8) => \ahbmo_1.haddr[8]\, - haddr(7) => \ahbmo_1.haddr[7]\, haddr(6) => - \ahbmo_1.haddr[6]\, haddr(5) => \ahbmo_1.haddr[5]\, - haddr(4) => \ahbmo_1.haddr[4]\, haddr(3) => - \ahbmo_1.haddr[3]\, haddr(2) => \ahbmo_1.haddr[2]\, - haddr(1) => \ahbmo_1.haddr[1]\, haddr(0) => - \ahbmo_1.haddr[0]\, iosn_0(93) => \sr1.iosn_0[93]\, - hrdata_0_0 => \ahbmi.hrdata_0[0]\, hrdata_0_24 => - \ahbmi.hrdata_0[24]\, hrdata_0_26 => \ahbmi.hrdata_0[26]\, - hrdata_0_27 => \ahbmi.hrdata_0[27]\, hrdata_0_8 => - \ahbmi.hrdata_0[8]\, hrdata_0_16 => \ahbmi.hrdata_0[16]\, - hrdata_0_18 => \ahbmi.hrdata_0[18]\, hrdata_0_10 => - \ahbmi.hrdata_0[10]\, hrdata_0_22 => \ahbmi.hrdata_0[22]\, - hrdata_0_7 => \ahbmi.hrdata_0[7]\, hrdata_0_17 => - \ahbmi.hrdata_0[17]\, hrdata_0_23 => \ahbmi.hrdata_0[23]\, - hrdata_0_3 => \ahbmi.hrdata_0[3]\, hrdata_0_11 => - \ahbmi.hrdata_0[11]\, hrdata_0_12 => \ahbmi.hrdata_0[12]\, - hrdata_0_4 => \ahbmi.hrdata_0[4]\, hrdata_0_21 => - \ahbmi.hrdata_0[21]\, hrdata_0_15 => \ahbmi.hrdata_0[15]\, - hrdata_0_14 => \ahbmi.hrdata_0[14]\, hrdata_0_13 => - \ahbmi.hrdata_0[13]\, hrdata_0_9 => \ahbmi.hrdata_0[9]\, - hrdata_0_2 => \ahbmi.hrdata_0[2]\, hrdata_0_1 => - \ahbmi.hrdata_0[1]\, hrdata_23 => \ahbmi.hrdata[28]\, - hrdata_25 => \ahbmi.hrdata[30]\, hrdata_26 => - \ahbmi.hrdata[31]\, hrdata_24 => \ahbmi.hrdata[29]\, - hrdata_1 => \ahbmi.hrdata[6]\, hrdata_0_d0 => - \ahbmi.hrdata[5]\, pwdata_0(15) => \apbi.pwdata_0[15]\, - pwdata_0(14) => \apbi.pwdata_0[14]\, pwdata_0(13) => - \apbi.pwdata_0[13]\, pwdata_0(12) => \apbi.pwdata_0[12]\, - pwdata_0(11) => \apbi.pwdata_0[11]\, pwdata_0(10) => - \apbi.pwdata_0[10]\, pwdata_0(9) => \apbi.pwdata_0[9]\, - pwdata_0(8) => \apbi.pwdata_0[8]\, pwdata_0(7) => - \apbi.pwdata_0[7]\, pwdata_0(6) => \apbi.pwdata_0[6]\, - pwdata_0(5) => \apbi.pwdata_0[5]\, pwdata_0(4) => - \apbi.pwdata_0[4]\, pwdata_0(3) => \apbi.pwdata_0[3]\, - pwdata_0(2) => \apbi.pwdata_0[2]\, pwdata_0(1) => - \apbi.pwdata_0[1]\, pwdata_0(0) => \apbi.pwdata_0[0]\, - un1_dcom0(19) => \dcomgen.un1_dcom0[19]\, un1_dcom0(18) - => \dcomgen.un1_dcom0[18]\, un1_dcom0(17) => - \dcomgen.un1_dcom0[17]\, un1_dcom0(16) => - \dcomgen.un1_dcom0[16]\, un1_dcom0(15) => - \dcomgen.un1_dcom0[15]\, un1_dcom0(14) => - \dcomgen.un1_dcom0[14]\, un1_dcom0(13) => - \dcomgen.un1_dcom0[13]\, un1_dcom0(12) => - \dcomgen.un1_dcom0[12]\, pwdata(17) => \apbi.pwdata[17]\, - pwdata(16) => \apbi.pwdata[16]\, psel_1(7) => - \apbi.psel_1[7]\, prdata_0 => \apbo_7.prdata[0]\, - prdata_5 => \apbo_7.prdata[5]\, pwdata_1(4) => - \apbi.pwdata_1[4]\, paddr(3) => \apbi.paddr[3]\, paddr(2) - => \apbi.paddr[2]\, hwdata(31) => \ahbmo_1.hwdata[31]\, - hwdata(30) => \ahbmo_1.hwdata[30]\, hwdata(29) => - \ahbmo_1.hwdata[29]\, hwdata(28) => \ahbmo_1.hwdata[28]\, - hwdata(27) => \ahbmo_1.hwdata[27]\, hwdata(26) => - \ahbmo_1.hwdata[26]\, hwdata(25) => \ahbmo_1.hwdata[25]\, - hwdata(24) => \ahbmo_1.hwdata[24]\, hwdata(23) => - \ahbmo_1.hwdata[23]\, hwdata(22) => \ahbmo_1.hwdata[22]\, - hwdata(21) => \ahbmo_1.hwdata[21]\, hwdata(20) => - \ahbmo_1.hwdata[20]\, hwdata(19) => \ahbmo_1.hwdata[19]\, - hwdata(18) => \ahbmo_1.hwdata[18]\, hwdata(17) => - \ahbmo_1.hwdata[17]\, hwdata(16) => \ahbmo_1.hwdata[16]\, - hwdata(15) => \ahbmo_1.hwdata[15]\, hwdata(14) => - \ahbmo_1.hwdata[14]\, hwdata(13) => \ahbmo_1.hwdata[13]\, - hwdata(12) => \ahbmo_1.hwdata[12]\, hwdata(11) => - \ahbmo_1.hwdata[11]\, hwdata(10) => \ahbmo_1.hwdata[10]\, - hwdata(9) => \ahbmo_1.hwdata[9]\, hwdata(8) => - \ahbmo_1.hwdata[8]\, hwdata(7) => \ahbmo_1.hwdata[7]\, - hwdata(6) => \ahbmo_1.hwdata[6]\, hwdata(5) => - \ahbmo_1.hwdata[5]\, hwdata(4) => \ahbmo_1.hwdata[4]\, - hwdata(3) => \ahbmo_1.hwdata[3]\, hwdata(2) => - \ahbmo_1.hwdata[2]\, hwdata(1) => \ahbmo_1.hwdata[1]\, - hwdata(0) => \ahbmo_1.hwdata[0]\, iosn_2(93) => - \sr1.iosn_2[93]\, htrans(1) => \ahbmo_1.htrans[1]\, - hgrant(1) => \ahbmi.hgrant[1]\, iosn(93) => - \sr1.iosn[93]\, hwrite => \ahbmo_1.hwrite\, N_264_0 => - N_264_0, N_262_0 => N_262_0, N_78_0 => N_78_0, N_78 => - \apb0.N_78\, un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\, - N_86 => \dcomgen.dcom0.dcom_uart0.N_86\, rdata60_1 => - \ua1.uart1.uartop.rdata60_1\, N_85 => - \dcomgen.dcom0.dcom_uart0.N_85\, dsutx_c => dsutx_c, - N_6455_0 => N_6455_0, N_332 => - \dcomgen.dcom0.dcom_uart0.N_332\, N_333 => - \dcomgen.dcom0.dcom_uart0.N_333\, N_334 => - \dcomgen.dcom0.dcom_uart0.N_334\, N_336 => - \dcomgen.dcom0.dcom_uart0.N_336\, N_331 => - \dcomgen.dcom0.dcom_uart0.N_331\, N_6455 => N_6455, N_127 - => \dcomgen.dcom0.dcom_uart0.N_127\, N_330 => - \dcomgen.dcom0.dcom_uart0.N_330\, N_769 => \apb0.N_769\, - un1_apbi_2 => \gpt.timer0.comb.1.un1_apbi_2\, N_335 => - \dcomgen.dcom0.dcom_uart0.N_335\, dsurx_c => dsurx_c, - rstn => rstn, hbusreq_i_3 => \ahbmo_1.hbusreq_i_3\, - lclk_c => lclk_c); - - \address_pad[2]\ : OUTBUF - port map(D => \address_c[2]\, PAD => address(2)); - - \sdo_adc_pad[1]\ : INBUF - port map(PAD => sdo_adc(1), Y => \sdo_adc_c[1]\); - - \pci_ad_pad[10]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(10)); - - \data_pad[10]\ : BIBUF - port map(PAD => data(10), D => \memo.data[10]\, E => - \memo.bdrive_i[2]\, Y => \data_in[10]\); - - ahb0 : ahbctrl - port map(hmbsel(0) => \ahbsi.hmbsel[0]\, htrans_3(1) => - \ahbmo_0.htrans[1]\, htrans_2(1) => \ahbmo_3.htrans[1]\, - htrans_1(1) => \ahbmo_1.htrans[1]\, htrans_0_0 => - \ahbmo_3.htrans[0]\, bco_msb_1(1) => \ahb0.bco_msb_1[1]\, - hresp_0(0) => \ahbmi.hresp[0]\, nhmaster_1_i(0) => - \ahb0.comb.nhmaster_1_i[0]\, hgrant_3 => - \ahbmi.hgrant[3]\, hgrant_1 => \ahbmi.hgrant[1]\, - hgrant_0 => \ahbmi.hgrant[0]\, hsize_5(1) => - \l3.cpu.0.u0.p0.c0mmu.a0.hsize_5[1]\, hmbsel_1(0) => - \ahbsi.hmbsel_1[0]\, hburst_0(2) => \ahbmo_3.hburst[2]\, - hburst_0(1) => \ahbmo_3.hburst[1]\, hburst_0(0) => - \ahbmo_3.hburst[0]\, hsize_0(1) => \ahbmo_3.hsize[1]\, - hsize_0(0) => \ahbmo_3.hsize[0]\, hsize(1) => - \ahbsi.hsize[1]\, hsize(0) => \ahbsi.hsize[0]\, haddr_3_4 - => \ahbmo_0.haddr[6]\, haddr_3_5 => \ahbmo_0.haddr[7]\, - haddr_3_0 => \ahbmo_3.haddr[2]\, haddr_3_3 => - \ahbmo_0.haddr[5]\, haddr_3_8 => \ahbmo_3.haddr[10]\, - haddr_3_6 => \ahbmo_0.haddr[8]\, haddr_3_1 => - \ahbmo_0.haddr[3]\, haddr_3_7 => \ahbmo_0.haddr[9]\, - hwdata_m_0_3 => \ahbsi.hwdata_m_0[15]\, hwdata_m_0_0 => - \ahbsi.hwdata_m_0[12]\, hwdata_m_0_2 => - \ahbsi.hwdata_m_0[14]\, hwdata_m_8 => - \ahbsi.hwdata_m[15]\, hwdata_m_13 => \ahbsi.hwdata_m[20]\, - hwdata_m_5 => \ahbsi.hwdata_m[12]\, hwdata_m_0_d0 => - \ahbsi.hwdata_m[7]\, hwdata_m_7 => \ahbsi.hwdata_m[14]\, - hwdata_2_15 => \ahbsi.hwdata[18]\, hwdata_2_0 => - \ahbmo_0.hwdata[3]\, hwdata_2_9 => \ahbmo_3.hwdata[12]\, - hwdata_2_3 => \ahbmo_3.hwdata[6]\, hwdata_2_14 => - \ahbsi.hwdata[17]\, hwdata_2_1 => \ahbmo_0.hwdata[4]\, - hwdata_2_28 => \ahbmo_3.hwdata[31]\, hwdata_2_27 => - \ahbmo_3.hwdata[30]\, hwdata_2_25 => \ahbmo_3.hwdata[28]\, - hwdata_2_23 => \ahbmo_3.hwdata[26]\, hwdata_2_13 => - \ahbmo_3.hwdata[16]\, hwdata_2_12 => \ahbmo_3.hwdata[15]\, - hwdata_2_11 => \ahbmo_3.hwdata[14]\, hwdata_2_4 => - \ahbmo_3.hwdata[7]\, hwdata_2_16 => \ahbmo_3.hwdata[19]\, - hwdata_1(31) => \ahbmo_1.hwdata[31]\, hwdata_1(30) => - \ahbmo_1.hwdata[30]\, hwdata_1(29) => - \ahbmo_3.hwdata[29]\, hwdata_1(28) => - \ahbmo_1.hwdata[28]\, hwdata_1(27) => - \ahbmo_3.hwdata[27]\, hwdata_1(26) => - \ahbmo_1.hwdata[26]\, hwdata_1(25) => - \ahbmo_3.hwdata[25]\, hwdata_1(24) => - \ahbmo_3.hwdata[24]\, hwdata_1(23) => \ahbsi.hwdata[23]\, - hwdata_1(22) => \ahbsi.hwdata[22]\, hwdata_1(21) => - \ahbsi.hwdata[21]\, hwdata_1(20) => \ahbmo_3.hwdata[20]\, - hwdata_1(19) => \ahbmo_1.hwdata[19]\, hwdata_1(18) => - \ahbmo_0.hwdata[18]\, hwdata_1(17) => - \ahbmo_0.hwdata[17]\, hwdata_1(16) => - \ahbmo_1.hwdata[16]\, hwdata_1(15) => - \ahbmo_1.hwdata[15]\, hwdata_1(14) => - \ahbmo_1.hwdata[14]\, hwdata_1(13) => \ahbsi.hwdata[13]\, - hwdata_1(12) => \ahbmo_1.hwdata[12]\, hwdata_1(11) => - \ahbsi.hwdata[11]\, hwdata_1(10) => \ahbmo_3.hwdata[10]\, - hwdata_1(9) => \ahbsi.hwdata[9]\, hwdata_1(8) => - \ahbmo_3.hwdata[8]\, hwdata_1(7) => \ahbmo_1.hwdata[7]\, - hwdata_1(6) => \ahbmo_1.hwdata[6]\, hwdata_1(5) => - \ahbmo_3.hwdata[5]\, hwdata_1(4) => \ahbsi.hwdata[4]\, - hwdata_1(3) => \ahbsi.hwdata[3]\, hwdata_1(2) => - \ahbmo_3.hwdata[2]\, hwdata_1(1) => \ahbsi.hwdata[1]\, - hwdata_1(0) => \ahbmo_3.hwdata[0]\, hwdata_0(31) => - \ahbmo_0.hwdata[31]\, hwdata_0(30) => - \ahbmo_0.hwdata[30]\, hwdata_0(29) => - \ahbmo_1.hwdata[29]\, hwdata_0(28) => - \ahbmo_0.hwdata[28]\, hwdata_0(27) => - \ahbmo_1.hwdata[27]\, hwdata_0(26) => - \ahbmo_0.hwdata[26]\, hwdata_0(25) => - \ahbmo_1.hwdata[25]\, hwdata_0(24) => - \ahbmo_1.hwdata[24]\, hwdata_0(23) => - \ahbmo_3.hwdata[23]\, hwdata_0(22) => - \ahbmo_3.hwdata[22]\, hwdata_0(21) => - \ahbmo_3.hwdata[21]\, hwdata_0(20) => - \ahbmo_1.hwdata[20]\, hwdata_0(19) => - \ahbmo_0.hwdata[19]\, hwdata_0(18) => - \ahbmo_3.hwdata[18]\, hwdata_0(17) => - \ahbmo_3.hwdata[17]\, hwdata_0(16) => - \ahbmo_0.hwdata[16]\, hwdata_0(15) => - \ahbmo_0.hwdata[15]\, hwdata_0(14) => - \ahbmo_0.hwdata[14]\, hwdata_0(13) => - \ahbmo_3.hwdata[13]\, hwdata_0(12) => - \ahbmo_0.hwdata[12]\, hwdata_0(11) => - \ahbmo_3.hwdata[11]\, hwdata_0(10) => - \ahbmo_1.hwdata[10]\, hwdata_0(9) => \ahbmo_3.hwdata[9]\, - hwdata_0(8) => \ahbmo_1.hwdata[8]\, hwdata_0(7) => - \ahbmo_0.hwdata[7]\, hwdata_0(6) => \ahbmo_0.hwdata[6]\, - hwdata_0(5) => \ahbmo_1.hwdata[5]\, hwdata_0(4) => - \ahbmo_3.hwdata[4]\, hwdata_0(3) => \ahbmo_3.hwdata[3]\, - hwdata_0(2) => \ahbmo_1.hwdata[2]\, hwdata_0(1) => - \ahbmo_3.hwdata[1]\, hwdata_0(0) => \ahbmo_1.hwdata[0]\, - hwdata(31) => \ahbsi.hwdata[31]\, hwdata(30) => - \ahbsi.hwdata[30]\, hwdata(29) => \ahbsi.hwdata[29]\, - hwdata(28) => \ahbsi.hwdata[28]\, hwdata(27) => - \ahbsi.hwdata[27]\, hwdata(26) => \ahbsi.hwdata[26]\, - hwdata(25) => \ahbsi.hwdata[25]\, hwdata(24) => - \ahbsi.hwdata[24]\, hwdata(23) => \ahbmo_1.hwdata[23]\, - hwdata(22) => \ahbmo_1.hwdata[22]\, hwdata(21) => - \ahbmo_1.hwdata[21]\, hwdata(20) => \ahbsi.hwdata[20]\, - hwdata(19) => \ahbsi.hwdata[19]\, hwdata(18) => - \ahbmo_1.hwdata[18]\, hwdata(17) => \ahbmo_1.hwdata[17]\, - hwdata(16) => \ahbsi.hwdata[16]\, hwdata(15) => - \ahbsi.hwdata[15]\, hwdata(14) => \ahbsi.hwdata[14]\, - hwdata(13) => \ahbmo_1.hwdata[13]\, hwdata(12) => - \ahbsi.hwdata[12]\, hwdata(11) => \ahbmo_1.hwdata[11]\, - hwdata(10) => \ahbsi.hwdata[10]\, hwdata(9) => - \ahbmo_1.hwdata[9]\, hwdata(8) => \ahbsi.hwdata[8]\, - hwdata(7) => \ahbsi.hwdata[7]\, hwdata(6) => - \ahbsi.hwdata[6]\, hwdata(5) => \ahbsi.hwdata[5]\, - hwdata(4) => \ahbmo_1.hwdata[4]\, hwdata(3) => - \ahbmo_1.hwdata[3]\, hwdata(2) => \ahbsi.hwdata[2]\, - hwdata(1) => \ahbmo_1.hwdata[1]\, hwdata(0) => - \ahbsi.hwdata[0]\, haddr_2(30) => \ahbmo_3.haddr[30]\, - haddr_2(29) => \ahbmo_3.haddr[29]\, haddr_2(28) => - \ahbmo_0.haddr[28]\, haddr_2(27) => \ahbmo_3.haddr[27]\, - haddr_2(26) => \ahbmo_0.haddr[26]\, haddr_2(25) => - \ahbmo_3.haddr[25]\, haddr_2(24) => \ahbmo_3.haddr[24]\, - haddr_2(23) => \ahbmo_0.haddr[23]\, haddr_2(22) => - \ahbmo_3.haddr[22]\, haddr_2(21) => \ahbmo_3.haddr[21]\, - haddr_2(20) => \ahbmo_0.haddr[20]\, haddr_2(19) => - \ahbmo_0.haddr[19]\, haddr_2(18) => \ahbmo_0.haddr[18]\, - haddr_2(17) => \ahbmo_0.haddr[17]\, haddr_2(16) => - \ahbmo_0.haddr[16]\, haddr_2(15) => \ahbmo_0.haddr[15]\, - haddr_2(14) => \ahbmo_0.haddr[14]\, haddr_2(13) => - \ahbmo_0.haddr[13]\, haddr_2(12) => \ahbmo_3.haddr[12]\, - haddr_2(11) => \ahbmo_3.haddr[11]\, haddr_2(10) => - \ahbmo_1.haddr[10]\, haddr_2(9) => \ahbsi.haddr[9]\, - haddr_2(8) => \ahbsi.haddr[8]\, haddr_2(7) => - \ahbsi.haddr[7]\, haddr_2(6) => \ahbsi.haddr[6]\, - haddr_2(5) => \ahbsi.haddr[5]\, haddr_2(4) => - \ahbmo_0.haddr[4]\, haddr_2(3) => \ahbsi.haddr[3]\, - haddr_2(2) => \ahbmo_1.haddr[2]\, haddr_1(31) => - \ahbmo_3.haddr[31]\, haddr_1(30) => \ahbmo_1.haddr[30]\, - haddr_1(29) => \ahbmo_1.haddr[29]\, haddr_1(28) => - \ahbmo_3.haddr[28]\, haddr_1(27) => \ahbmo_1.haddr[27]\, - haddr_1(26) => \ahbmo_3.haddr[26]\, haddr_1(25) => - \ahbmo_1.haddr[25]\, haddr_1(24) => \ahbmo_1.haddr[24]\, - haddr_1(23) => \ahbmo_3.haddr[23]\, haddr_1(22) => - \ahbmo_1.haddr[22]\, haddr_1(21) => \ahbmo_1.haddr[21]\, - haddr_1(20) => \ahbmo_3.haddr[20]\, haddr_1(19) => - \ahbmo_3.haddr[19]\, haddr_1(18) => \ahbmo_3.haddr[18]\, - haddr_1(17) => \ahbmo_3.haddr[17]\, haddr_1(16) => - \ahbmo_3.haddr[16]\, haddr_1(15) => \ahbmo_3.haddr[15]\, - haddr_1(14) => \ahbmo_3.haddr[14]\, haddr_1(13) => - \ahbmo_3.haddr[13]\, haddr_1(12) => \ahbmo_1.haddr[12]\, - haddr_1(11) => \ahbmo_1.haddr[11]\, haddr_1(10) => - \ahbmo_0.haddr[10]\, haddr_1(9) => \ahbmo_3.haddr[9]\, - haddr_1(8) => \ahbmo_3.haddr[8]\, haddr_1(7) => - \ahbmo_3.haddr[7]\, haddr_1(6) => \ahbmo_3.haddr[6]\, - haddr_1(5) => \ahbmo_3.haddr[5]\, haddr_1(4) => - \ahbsi.haddr[4]\, haddr_1(3) => \ahbmo_3.haddr[3]\, - haddr_1(2) => \ahbsi.haddr[2]\, haddr_1(1) => - \ahbmo_3.haddr[1]\, haddr_1(0) => \ahbsi.haddr[0]\, - haddr_0(31) => \ahbmo_1.haddr[31]\, haddr_0(30) => - \ahbmo_0.haddr[30]\, haddr_0(29) => \ahbmo_0.haddr[29]\, - haddr_0(28) => \ahbmo_1.haddr[28]\, haddr_0(27) => - \ahbmo_0.haddr[27]\, haddr_0(26) => \ahbmo_1.haddr[26]\, - haddr_0(25) => \ahbmo_0.haddr[25]\, haddr_0(24) => - \ahbmo_0.haddr[24]\, haddr_0(23) => \ahbmo_1.haddr[23]\, - haddr_0(22) => \ahbmo_0.haddr[22]\, haddr_0(21) => - \ahbmo_0.haddr[21]\, haddr_0(20) => \ahbmo_1.haddr[20]\, - haddr_0(19) => \ahbmo_1.haddr[19]\, haddr_0(18) => - \ahbmo_1.haddr[18]\, haddr_0(17) => \ahbmo_1.haddr[17]\, - haddr_0(16) => \ahbmo_1.haddr[16]\, haddr_0(15) => - \ahbmo_1.haddr[15]\, haddr_0(14) => \ahbmo_1.haddr[14]\, - haddr_0(13) => \ahbmo_1.haddr[13]\, haddr_0(12) => - \ahbmo_0.haddr[12]\, haddr_0(11) => \ahbmo_0.haddr[11]\, - haddr_0(10) => \ahbsi.haddr[10]\, haddr_0(9) => - \ahbmo_1.haddr[9]\, haddr_0(8) => \ahbmo_1.haddr[8]\, - haddr_0(7) => \ahbmo_1.haddr[7]\, haddr_0(6) => - \ahbmo_1.haddr[6]\, haddr_0(5) => \ahbmo_1.haddr[5]\, - haddr_0(4) => \ahbmo_3.haddr[4]\, haddr_0(3) => - \ahbmo_1.haddr[3]\, haddr_0(2) => \ahbmo_0.haddr[2]\, - haddr_0(1) => \ahbmo_1.haddr[1]\, haddr_0(0) => - \ahbmo_3.haddr[0]\, hrdata_4_15 => \ahbso_1.hrdata[15]\, - hrdata_4_13 => \ahbso_1.hrdata[13]\, hrdata_4_11 => - \ahbso_1.hrdata[11]\, hrdata_4_27 => \ahbso_1.hrdata[27]\, - hrdata_4_26 => \ahbso_1.hrdata[26]\, hrdata_4_4 => - \ahbso_0.hrdata[4]\, hrdata_4_21 => \ahbso_1.hrdata[21]\, - hrdata_4_1 => \ahbso_0.hrdata[1]\, hrdata_4_22 => - \ahbso_0.hrdata[22]\, hrdata_4_23 => \ahbso_1.hrdata[23]\, - hrdata_4_0 => \ahbso_1.hrdata[0]\, hrdata_4_14 => - \ahbso_7.hrdata[14]\, hrdata_4_3 => \ahbso_7.hrdata[3]\, - hrdata_4_2 => \ahbso_7.hrdata[2]\, hrdata_4_9 => - \ahbso_1.hrdata[9]\, hrdata_4_12 => \ahbso_1.hrdata[12]\, - hrdata_4_10 => \ahbso_1.hrdata[10]\, hrdata_4_7 => - \ahbso_1.hrdata[7]\, hrdata_4_8 => \ahbso_0.hrdata[8]\, - hrdata_4_16 => \ahbso_0.hrdata[16]\, hrdata_4_18 => - \ahbso_1.hrdata[18]\, hrdata_4_17 => \ahbso_7.hrdata[17]\, - hrdata_3_15 => \ahbso_0.hrdata[15]\, hrdata_3_13 => - \ahbso_0.hrdata[13]\, hrdata_3_11 => \ahbso_0.hrdata[11]\, - hrdata_3_28 => \ahbso_1.hrdata[28]\, hrdata_3_27 => - \ahbso_0.hrdata[27]\, hrdata_3_26 => \ahbso_0.hrdata[26]\, - hrdata_3_4 => \ahbso_1.hrdata[4]\, hrdata_3_1 => - \ahbso_1.hrdata[1]\, hrdata_3_22 => \ahbso_1.hrdata[22]\, - hrdata_3_23 => \ahbso_0.hrdata[23]\, hrdata_3_0 => - \ahbso_0.hrdata[0]\, hrdata_3_24 => \ahbso_7.hrdata[24]\, - hrdata_3_21 => \ahbso_7.hrdata[21]\, hrdata_3_14 => - \ahbso_6.hrdata[14]\, hrdata_3_3 => \ahbso_6.hrdata[3]\, - hrdata_3_2 => \ahbso_6.hrdata[2]\, hrdata_3_9 => - \ahbso_0.hrdata[9]\, hrdata_3_12 => \ahbso_0.hrdata[12]\, - hrdata_3_10 => \ahbso_0.hrdata[10]\, hrdata_3_7 => - \ahbso_0.hrdata[7]\, hrdata_3_6 => \ahbso_0.hrdata[6]\, - hrdata_3_8 => \ahbso_1.hrdata[8]\, hrdata_3_29 => - \ahbso_0.hrdata[29]\, hrdata_3_16 => \ahbso_1.hrdata[16]\, - hrdata_3_5 => \ahbso_0.hrdata[5]\, hrdata_3_30 => - \ahbso_7.hrdata[30]\, hrdata_3_18 => \ahbso_7.hrdata[18]\, - hrdata_3_17 => \ahbso_6.hrdata[17]\, hrdata_2_28 => - \ahbso_0.hrdata[28]\, hrdata_2_25 => \ahbso_1.hrdata[25]\, - hrdata_2_15 => \ahbmi.hrdata[15]\, hrdata_2_11 => - \ahbmi.hrdata[11]\, hrdata_2_27 => \ahbmi.hrdata[27]\, - hrdata_2_26 => \ahbmi.hrdata[26]\, hrdata_2_23 => - \ahbso_7.hrdata[23]\, hrdata_2_22 => \ahbso_7.hrdata[22]\, - hrdata_2_21 => \ahbso_6.hrdata[21]\, hrdata_2_13 => - \ahbso_7.hrdata[13]\, hrdata_2_4 => \ahbso_7.hrdata[4]\, - hrdata_2_1 => \ahbso_7.hrdata[1]\, hrdata_2_0 => - \ahbso_7.hrdata[0]\, hrdata_2_24 => \ahbso_1.hrdata[24]\, - hrdata_2_14 => \ahbso_1.hrdata[14]\, hrdata_2_3 => - \ahbso_1.hrdata[3]\, hrdata_2_2 => \ahbso_1.hrdata[2]\, - hrdata_2_31 => \ahbso_1.hrdata[31]\, hrdata_2_9 => - \ahbmi.hrdata[9]\, hrdata_2_19 => \ahbso_1.hrdata[19]\, - hrdata_2_10 => \ahbmi.hrdata[10]\, hrdata_2_7 => - \ahbmi.hrdata[7]\, hrdata_2_6 => \ahbso_1.hrdata[6]\, - hrdata_2_29 => \ahbso_1.hrdata[29]\, hrdata_2_5 => - \ahbso_1.hrdata[5]\, hrdata_2_30 => \ahbso_6.hrdata[30]\, - hrdata_2_18 => \ahbso_6.hrdata[18]\, hrdata_2_16 => - \ahbso_7.hrdata[16]\, hrdata_2_12 => \ahbso_7.hrdata[12]\, - hrdata_2_8 => \ahbso_7.hrdata[8]\, hrdata_2_17 => - \ahbso_1.hrdata[17]\, bco_msb_1_m(1) => - \ahb0.bco_msb_1_m[1]\, hmaster_0_0_RNIFCVH1_0(1) => - \r.hmaster_0_0_RNIFCVH1_0[1]\, l1_0_m(1) => - \ahb0.l1_0_m[1]\, nhmaster_1_iv_0(1) => - \ahb0.comb.nhmaster_1_iv_0[1]\, hresp(0) => - \ahbso_0.hresp[0]\, htrans(1) => \ahbsi.htrans[1]\, - htrans(0) => \ahbsi.htrans[0]\, hrdata_1(31) => - \ahbso_0.hrdata[31]\, hrdata_1(30) => - \ahbso_1.hrdata[30]\, hrdata_1(29) => - \ahbso_7.hrdata[29]\, hrdata_1(28) => - \ahbso_7.hrdata[28]\, hrdata_1(27) => - \ahbso_7.hrdata[27]\, hrdata_1(26) => - \ahbso_7.hrdata[26]\, hrdata_1(25) => - \ahbso_0.hrdata[25]\, hrdata_1(24) => - \ahbso_0.hrdata[24]\, hrdata_1(23) => - \ahbso_6.hrdata[23]\, hrdata_1(22) => - \ahbso_6.hrdata[22]\, hrdata_1(21) => \ahbmi.hrdata[21]\, - hrdata_1(20) => \ahbso_7.hrdata[20]\, hrdata_1(19) => - \ahbso_0.hrdata[19]\, hrdata_1(18) => \ahbmi.hrdata[18]\, - hrdata_1(17) => \ahbso_0.hrdata[17]\, hrdata_1(16) => - \ahbso_6.hrdata[16]\, hrdata_1(15) => - \ahbso_7.hrdata[15]\, hrdata_1(14) => - \ahbso_0.hrdata[14]\, hrdata_1(13) => - \ahbso_6.hrdata[13]\, hrdata_1(12) => - \ahbso_6.hrdata[12]\, hrdata_1(11) => - \ahbso_7.hrdata[11]\, hrdata_1(10) => - \ahbso_7.hrdata[10]\, hrdata_1(9) => \ahbso_7.hrdata[9]\, - hrdata_1(8) => \ahbso_6.hrdata[8]\, hrdata_1(7) => - \ahbso_7.hrdata[7]\, hrdata_1(6) => \ahbso_7.hrdata[6]\, - hrdata_1(5) => \ahbso_7.hrdata[5]\, hrdata_1(4) => - \ahbso_6.hrdata[4]\, hrdata_1(3) => \ahbso_0.hrdata[3]\, - hrdata_1(2) => \ahbso_0.hrdata[2]\, hrdata_1(1) => - \ahbso_6.hrdata[1]\, hrdata_1(0) => \ahbso_6.hrdata[0]\, - data_0_5 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[13]\, - data_0_21 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[29]\, - data_0_16 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[24]\, - data_0_2 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[10]\, - data_0_0 => \l3.cpu.0.u0.p0.c0mmu.mcdi.data[8]\, data_8 - => \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[13]\, data_24 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[29]\, data_0_d0 => - \l3.cpu.0.u0.p0.c0mmu.mcdi.data[5]\, data_19 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[24]\, data_5 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[10]\, data_3 => - \l3.cpu.0.u0.p0.c0mmu.mcmmi.data[8]\, hrdata(31) => - \ahbso_7.hrdata[31]\, hrdata(30) => \ahbmi.hrdata[30]\, - hrdata(29) => \ahbmi.hrdata[29]\, hrdata(28) => - \ahbmi.hrdata[28]\, hrdata(27) => \ahbso_6.hrdata[27]\, - hrdata(26) => \ahbso_6.hrdata[26]\, hrdata(25) => - \ahbso_6.hrdata[25]\, hrdata(24) => \ahbmi.hrdata[24]\, - hrdata(23) => \ahbmi.hrdata[23]\, hrdata(22) => - \ahbmi.hrdata[22]\, hrdata(21) => \ahbso_0.hrdata[21]\, - hrdata(20) => \ahbso_0.hrdata[20]\, hrdata(19) => - \ahbso_6.hrdata[19]\, hrdata(18) => \ahbso_0.hrdata[18]\, - hrdata(17) => \ahbmi.hrdata[17]\, hrdata(16) => - \ahbmi.hrdata[16]\, hrdata(15) => \ahbso_6.hrdata[15]\, - hrdata(14) => \ahbmi.hrdata[14]\, hrdata(13) => - \ahbmi.hrdata[13]\, hrdata(12) => \ahbmi.hrdata[12]\, - hrdata(11) => \ahbso_6.hrdata[11]\, hrdata(10) => - \ahbso_6.hrdata[10]\, hrdata(9) => \ahbso_6.hrdata[9]\, - hrdata(8) => \ahbmi.hrdata[8]\, hrdata(7) => - \ahbso_6.hrdata[7]\, hrdata(6) => \ahbmi.hrdata[6]\, - hrdata(5) => \ahbmi.hrdata[5]\, hrdata(4) => - \ahbmi.hrdata[4]\, hrdata(3) => \ahbmi.hrdata[3]\, - hrdata(2) => \ahbmi.hrdata[2]\, hrdata(1) => - \ahbmi.hrdata[1]\, hrdata(0) => \ahbmi.hrdata[0]\, - size(0) => \l3.cpu.0.u0.p0.c0mmu.mcdi.size[0]\, - nbo_5_0(1) => \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[1]\, - nbo_5_0(0) => \l3.cpu.0.u0.p0.c0mmu.a0.comb.nbo_5_0[0]\, - address(1) => \l3.cpu.0.u0.p0.c0mmu.mcdi.address[1]\, - address(0) => \l3.cpu.0.u0.p0.c0mmu.mcdi.address[0]\, - htrans_tz(1) => \ahbmo_0.htrans_tz[1]\, haddr_1_d0 => - \ahbsi.haddr[1]\, haddr_11 => \ahbsi.haddr[11]\, haddr_31 - => \ahbmo_0.haddr[31]\, haddr_0_d0 => \ahbmo_1.haddr[0]\, - haddr_4 => \ahbmo_1.haddr[4]\, haddr_15 => - \ahbsi.haddr[15]\, haddr_14 => \ahbsi.haddr[14]\, - haddr_19 => \ahbsi.haddr[19]\, haddr_18 => - \ahbsi.haddr[18]\, haddr_21 => \ahbsi.haddr[21]\, - haddr_20 => \ahbsi.haddr[20]\, haddr_23 => - \ahbsi.haddr[23]\, haddr_22 => \ahbsi.haddr[22]\, - haddr_27 => \ahbsi.haddr[27]\, haddr_26 => - \ahbsi.haddr[26]\, haddr_29 => \ahbsi.haddr[29]\, - haddr_28 => \ahbsi.haddr[28]\, haddr_12 => - \ahbsi.haddr[12]\, haddr_13 => \ahbsi.haddr[13]\, - haddr_16 => \ahbsi.haddr[16]\, haddr_17 => - \ahbsi.haddr[17]\, haddr_24 => \ahbsi.haddr[24]\, - haddr_25 => \ahbsi.haddr[25]\, haddr_30 => - \ahbsi.haddr[30]\, hburst(2) => \ahbsi.hburst[2]\, - hburst(1) => \ahbsi.hburst[1]\, hburst(0) => - \ahbsi.hburst[0]\, hsel_i(0) => \ahbsi.hsel_i[0]\, - hrdata_1_0_1_0 => \ahb0.hrdata_1_0_1[1]\, hrdata_0(31) - => \ahbmi.hrdata[31]\, hrdata_0(30) => - \ahbso_0.hrdata[30]\, hrdata_0(29) => - \ahbso_6.hrdata[29]\, hrdata_0(28) => - \ahbso_6.hrdata[28]\, hrdata_0(27) => - \ahbmi.hrdata_0[27]\, hrdata_0(26) => - \ahbmi.hrdata_0[26]\, hrdata_0(25) => - \ahbso_7.hrdata[25]\, hrdata_0(24) => - \ahbmi.hrdata_0[24]\, hrdata_0(23) => - \ahbmi.hrdata_0[23]\, hrdata_0(22) => - \ahbmi.hrdata_0[22]\, hrdata_0(21) => - \ahbmi.hrdata_0[21]\, hrdata_0(20) => - \ahbso_1.hrdata[20]\, hrdata_0(19) => - \ahbso_7.hrdata[19]\, hrdata_0(18) => - \ahbmi.hrdata_0[18]\, hrdata_0(17) => - \ahbmi.hrdata_0[17]\, hrdata_0(16) => - \ahbmi.hrdata_0[16]\, hrdata_0(15) => - \ahbmi.hrdata_0[15]\, hrdata_0(14) => - \ahbmi.hrdata_0[14]\, hrdata_0(13) => - \ahbmi.hrdata_0[13]\, hrdata_0(12) => - \ahbmi.hrdata_0[12]\, hrdata_0(11) => - \ahbmi.hrdata_0[11]\, hrdata_0(10) => - \ahbmi.hrdata_0[10]\, hrdata_0(9) => \ahbmi.hrdata_0[9]\, - hrdata_0(8) => \ahbmi.hrdata_0[8]\, hrdata_0(7) => - \ahbmi.hrdata_0[7]\, hrdata_0(6) => \ahbso_6.hrdata[6]\, - hrdata_0(5) => \ahbso_6.hrdata[5]\, hrdata_0(4) => - \ahbmi.hrdata_0[4]\, hrdata_0(3) => \ahbmi.hrdata_0[3]\, - hrdata_0(2) => \ahbmi.hrdata_0[2]\, hrdata_0(1) => - \ahbmi.hrdata_0[1]\, hrdata_0(0) => \ahbmi.hrdata_0[0]\, - iosn_0(93) => \sr1.iosn_0[93]\, iosn_1_8 => - \sr1.iosn_1[101]\, iosn_1_0 => \sr1.iosn_1[93]\, - iosn_2(93) => \sr1.iosn_2[93]\, iosn_8 => \sr1.iosn[101]\, - iosn_7 => \sr1.iosn[100]\, iosn_0_d0 => \sr1.iosn[93]\, - hmaster_0_1 => \ahbsi.hmaster_0[1]\, N_5054 => N_5054, - htrans_0_sqmuxa_2 => - \l3.cpu.0.u0.p0.c0mmu.a0.htrans_0_sqmuxa_2\, - lb_0_sqmuxa_1 => - \l3.cpu.0.u0.p0.c0mmu.a0.v.lb_0_sqmuxa_1\, N_466 => N_466, - N_95_i_0 => \lpp_bootloader_1.ahbrom_1.N_95_i_0\, - bo_5842_d => \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d\, rstn - => rstn, hbusreq_i_3_0 => \ahbmo_3.hbusreq_i_3\, - N_90_i_0 => \lpp_bootloader_1.ahbrom_1.N_90_i_0\, N_262 - => N_262, hwrite_1_m_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.hwrite_1_m_0\, werr_2_m_0 - => \l3.cpu.0.u0.p0.c0mmu.a0.comb.v.werr_2_m_0\, hwrite_1 - => \ahbmo_3.hwrite\, hwrite_0 => \ahbmo_1.hwrite\, N_458 - => N_458, N_459 => N_459, N_468 => N_468, N_463 => N_463, - N_461 => N_461, N_510 => N_510, N_138 => N_138, N_139 => - N_139, N_6377 => N_6377, N_103_i_0 => - \lpp_bootloader_1.ahbrom_1.N_103_i_0\, brmw_i => - \sr1.ctrl.un1_r.brmw_i\, N_6550 => N_6550, N_264 => N_264, - N_467 => N_467, N_457 => N_457, N_462 => N_462, - un1_nhmaster_0_sqmuxa_1 => \ahb0.un1_nhmaster_0_sqmuxa_1\, - un1_htrans_1_sqmuxa_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.un1_htrans_1_sqmuxa_0\, un60_nbo - => \l3.cpu.0.u0.p0.c0mmu.a0.comb.un60_nbo\, arb_1 => - \ahb0.comb.arb_1\, hbusreq => \ahbmo_0.hbusreq\, hlock - => \ahbmo_0.hlock\, hready_1 => \ahbso_7.hready\, - hready_0 => \ahbso_0.hready\, N_78 => N_78, un315_ioen_NE - => \ahb0.comb.7.4.un315_ioen_NE\, un51_ioen_NE => - \ahb0.comb.1.4.un51_ioen_NE\, un59_nbo => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un59_nbo\, un91_nbo_i_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.comb.un91_nbo_i_0\, hready => - \ahbso_1.hready\, bo_5842_d_0 => - \l3.cpu.0.u0.p0.c0mmu.a0.r.bo_5842_d_0\, un6_ioen_NE_0 - => \ahb0.comb.0.4.un6_ioen_NE_0\, brmw_1 => - \sr1.ctrl.brmw_1\, hwrite => \ahbsi.hwrite\, hwrite_m_0_0 - => \ahbsi.hwrite_m_0_0\, hbusreq_i_3 => - \ahbmo_1.hbusreq_i_3\, IdlePhase => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.IdlePhase\, - un1_dmain_6 => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.DMA2AHB_1.un1_dmain_6\, - Lock_RNIU86D => \DMAIn.Lock_RNIU86D\, N_546 => N_546, - N_264_0 => N_264_0, N_262_0 => N_262_0, N_78_0 => N_78_0, - lclk_c => lclk_c); - - \data_pad[19]\ : BIBUF - port map(PAD => data(19), D => \memo.data[19]\, E => - \memo.bdrive_i[1]\, Y => \data_in[19]\); - - clk_pad : INBUF - port map(PAD => clk, Y => clk_c); - - \pci_arb_gnt_pad[3]\ : OUTBUF - port map(D => \GND\, PAD => pci_arb_gnt(3)); - - \data_pad[23]\ : BIBUF - port map(PAD => data(23), D => \memo.data[23]\, E => - \memo.bdrive_i[1]\, Y => \data_in[23]\); - - \ramsn_pad[1]\ : OUTBUF - port map(D => \ramsn_c[1]\, PAD => ramsn(1)); - - \address_pad[20]\ : OUTBUF - port map(D => \address_c[20]\, PAD => address(20)); - - \data_pad[5]\ : BIBUF - port map(PAD => data(5), D => \memo.data[5]\, E => - \memo.bdrive_i[3]\, Y => \data_in[5]\); - - lfrtimemanagement_0 : apb_lfr_time_management - port map(coarse_time_i(0) => \coarse_time_i[0]\, pirq(13) - => \apbi.pirq[13]\, pirq(12) => \apbi.pirq[12]\, - pwdata_1_3 => \apbi.pwdata_1[4]\, pwdata_1_2 => - \apbi.pwdata_1[3]\, pwdata_1_0 => \apbi.pwdata_1[1]\, - prdata(31) => \apbo_15.prdata[31]\, prdata(30) => - \apbo_15.prdata[30]\, prdata(29) => \apbo_15.prdata[29]\, - prdata(28) => \apbo_15.prdata[28]\, prdata(27) => - \apbo_15.prdata[27]\, prdata(26) => \apbo_15.prdata[26]\, - prdata(25) => \apbo_15.prdata[25]\, prdata(24) => - \apbo_15.prdata[24]\, prdata(23) => \apbo_15.prdata[23]\, - prdata(22) => \apbo_15.prdata[22]\, prdata(21) => - \apbo_15.prdata[21]\, prdata(20) => \apbo_15.prdata[20]\, - prdata(19) => \apbo_15.prdata[19]\, prdata(18) => - \apbo_15.prdata[18]\, prdata(17) => \apbo_15.prdata[17]\, - prdata(16) => \apbo_15.prdata[16]\, prdata(15) => - \apbo_15.prdata[15]\, prdata(14) => \apbo_15.prdata[14]\, - prdata(13) => \apbo_15.prdata[13]\, prdata(12) => - \apbo_15.prdata[12]\, prdata(11) => \apbo_15.prdata[11]\, - prdata(10) => \apbo_15.prdata[10]\, prdata(9) => - \apbo_15.prdata[9]\, prdata(8) => \apbo_15.prdata[8]\, - prdata(7) => \apbo_15.prdata[7]\, prdata(6) => - \apbo_15.prdata[6]\, prdata(5) => \apbo_15.prdata[5]\, - prdata(4) => \apbo_15.prdata[4]\, prdata(3) => - \apbo_15.prdata[3]\, prdata(2) => \apbo_15.prdata[2]\, - prdata(1) => \apbo_15.prdata[1]\, prdata(0) => - \apbo_15.prdata[0]\, coarse_time_0 => \coarse_time[0]\, - pwdata_10 => \apbi.pwdata[12]\, pwdata_8 => - \apbi.pwdata[10]\, pwdata_7 => \apbi.pwdata[9]\, - pwdata_13 => \apbi.pwdata[15]\, pwdata_12 => - \apbi.pwdata[14]\, pwdata_11 => \apbi.pwdata[13]\, - pwdata_9 => \apbi.pwdata[11]\, pwdata_6 => - \apbi.pwdata[8]\, pwdata_5 => \apbi.pwdata[7]\, pwdata_4 - => \apbi.pwdata[6]\, pwdata_3 => \apbi.pwdata[5]\, - pwdata_0_d0 => \apbi.pwdata[2]\, pwdata_18 => - \apbi.pwdata[20]\, pwdata_29 => \apbi.pwdata[31]\, - pwdata_28 => \apbi.pwdata[30]\, pwdata_27 => - \apbi.pwdata[29]\, pwdata_25 => \apbi.pwdata[27]\, - pwdata_24 => \apbi.pwdata[26]\, pwdata_23 => - \apbi.pwdata[25]\, pwdata_22 => \apbi.pwdata[24]\, - pwdata_21 => \apbi.pwdata[23]\, pwdata_20 => - \apbi.pwdata[22]\, pwdata_19 => \apbi.pwdata[21]\, - pwdata_17 => \apbi.pwdata[19]\, pwdata_26 => - \apbi.pwdata[28]\, pwdata_16 => \apbi.pwdata[18]\, - pwdata_15 => \apbi.pwdata[17]\, pwdata_14 => - \apbi.pwdata[16]\, pwdata_0(15) => \apbi.pwdata_0[15]\, - pwdata_0(14) => \apbi.pwdata_0[14]\, pwdata_0(13) => - \apbi.pwdata_0[13]\, pwdata_0(12) => \apbi.pwdata_0[12]\, - pwdata_0(11) => \apbi.pwdata_0[11]\, pwdata_0(10) => - \apbi.pwdata_0[10]\, pwdata_0(9) => \apbi.pwdata_0[9]\, - pwdata_0(8) => \apbi.pwdata_0[8]\, pwdata_0(7) => - \apbi.pwdata_0[7]\, pwdata_0(6) => \apbi.pwdata_0[6]\, - pwdata_0(5) => \apbi.pwdata_0[5]\, pwdata_0(4) => - \apbi.pwdata_0[4]\, pwdata_0(3) => \apbi.pwdata_0[3]\, - pwdata_0(2) => \apbi.pwdata_0[2]\, pwdata_0(1) => - \apbi.pwdata_0[1]\, pwdata_0(0) => \apbi.pwdata_0[0]\, - paddr(7) => \apbi.paddr[7]\, paddr(6) => \apbi.paddr[6]\, - paddr(5) => \apbi.paddr[5]\, paddr(4) => \apbi.paddr[4]\, - paddr(3) => \apbi.paddr[3]\, psel(15) => \apbi.psel[15]\, - rstn_i => rstn_i, clk49_152MHz_c => clk49_152MHz_c, - clk49_152MHz_c_0 => clk49_152MHz_c_0, un1_apbi_7_1 => - \lfrtimemanagement_0.un1_apbi_7_1\, rdata60 => - \ua1.uart1.uartop.rdata60\, ctrl2 => - \lfrtimemanagement_0.r.ctrl2\, rdata59 => - \ua1.uart1.uartop.rdata59\, N_232_0 => - \ua1.uart1.N_232_0\, un1_apbi_2 => - \gpt.timer0.comb.1.un1_apbi_2\, rdata61_2 => - \ua1.uart1.uartop.rdata61_2\, N_770 => \apb0.N_770\, - rdata62_0 => \ua1.uart1.uartop.rdata62_0\, rdata61 => - \ua1.uart1.uartop.rdata61\, un1_apbi_8 => - \lfrtimemanagement_0.un1_apbi_8\, un1_apbi_7_3 => - \lfrtimemanagement_0.un1_apbi_7_3\, un1_apbi_0 => - \gpt.timer0.comb.un1_apbi_0\, rdata62 => - \ua1.uart1.uartop.rdata62\, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, rdata59_4 => - \ua1.uart1.uartop.rdata59_4\, readdata55_3 => - \gpt.timer0.comb.readdata55_3\, rdata62_3 => - \ua1.uart1.uartop.rdata62_3\, pwrite => \apbi.pwrite\, - rstn => rstn, lclk_c => lclk_c); - - \spw_txd_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => spw_txd(2)); - - \pci_ad_pad[3]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(3)); - - epwrdwn_pad : OUTBUF - port map(D => \GND\, PAD => epwrdwn); - - \pci_ad_pad[25]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(25)); - - \ramoen_pad[4]\ : OUTBUF - port map(D => \VCC\, PAD => ramoen(4)); - - \gpio_pad[3]\ : BIBUF - port map(PAD => gpio(3), D => \gpioo.dout[3]\, E => - \gpioo.oen_i[3]\, Y => \gpio_in[3]\); - - GND_i_0 : GND - port map(Y => GND_0); - - pci_stop_pad : OUTBUF - port map(D => \GND\, PAD => pci_stop); - - \gpio_pad[2]\ : BIBUF - port map(PAD => gpio(2), D => \gpioo.dout[2]\, E => - \gpioo.oen_i[2]\, Y => \gpio_in[2]\); - - \address_pad[25]\ : OUTBUF - port map(D => \address_c[25]\, PAD => address(25)); - - pci_req_pad : OUTBUF - port map(D => \GND\, PAD => pci_req); - - ramclk_pad : OUTBUF - port map(D => lclk_c, PAD => ramclk); - - \pci_ad_pad[13]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(13)); - - \spw_txsn_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => spw_txsn(2)); - - \spw_txdn_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => spw_txdn(2)); - - \pci_cbe_pad[3]\ : OUTBUF - port map(D => \GND\, PAD => pci_cbe(3)); - - nBWE_pad : OUTBUF - port map(D => nBWE_c, PAD => nBWE); - - \pci_ad_pad[24]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(24)); - - \pci_ad_pad[29]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(29)); - - pci_rst_pad : OUTBUF - port map(D => \GND\, PAD => pci_rst); - - \data_pad[17]\ : BIBUF - port map(PAD => data(17), D => \memo.data[17]\, E => - \memo.bdrive_i[1]\, Y => \data_in[17]\); - - \address_pad[10]\ : OUTBUF - port map(D => \address_c[10]\, PAD => address(10)); - - rxd1_pad : INBUF - port map(PAD => rxd1, Y => rxd1_c); - - \data_pad[4]\ : BIBUF - port map(PAD => data(4), D => \memo.data[4]\, E => - \memo.bdrive_i[3]\, Y => \data_in[4]\); - - clk49_152MHz_pad_RNIB5E4 : BUFF - port map(A => clk49_152MHz_c, Y => clk49_152MHz_c_0); - - \pci_ad_pad[21]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(21)); - - nADSC_pad : OUTBUF - port map(D => \VCC\, PAD => nADSC); - - tdo_pad : OUTBUF - port map(D => \GND\, PAD => tdo); - - \pci_arb_gnt_pad[2]\ : OUTBUF - port map(D => \GND\, PAD => pci_arb_gnt(2)); - - \data_pad[3]\ : BIBUF - port map(PAD => data(3), D => \memo.data[3]\, E => - \memo.bdrive_i[3]\, Y => \data_in[3]\); - - \address_pad[7]\ : OUTBUF - port map(D => \address_c[7]\, PAD => address(7)); - - \address_pad[15]\ : OUTBUF - port map(D => \address_c[15]\, PAD => address(15)); - - \spw_txs_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => spw_txs(1)); - - \data_pad[6]\ : BIBUF - port map(PAD => data(6), D => \memo.data[6]\, E => - \memo.bdrive_i[3]\, Y => \data_in[6]\); - - \pci_arb_gnt_pad[0]\ : OUTBUF - port map(D => \GND\, PAD => pci_arb_gnt(0)); - - rst0 : rstgen - port map(rstgen_VCC => \VCC\, rstraw_c => rstraw_c, lclk_c - => lclk_c, m26_m1_e => m26_m1_e, rstoutl_RNIGJKSJO => - rstoutl_RNIGJKSJO, rstn_i => rstn_i, rstn => rstn); - - \data_pad[26]\ : BIBUF - port map(PAD => data(26), D => \memo.data[26]\, E => - \memo.bdrive_i[0]\, Y => \data_in[26]\); - - dsutx_pad : OUTBUF - port map(D => dsutx_c, PAD => dsutx); - - sr1 : mctrl - port map(data_in(31) => \data_in[31]\, data_in(30) => - \data_in[30]\, data_in(29) => \data_in[29]\, data_in(28) - => \data_in[28]\, data_in(27) => \data_in[27]\, - data_in(26) => \data_in[26]\, data_in(25) => - \data_in[25]\, data_in(24) => \data_in[24]\, data_in(23) - => \data_in[23]\, data_in(22) => \data_in[22]\, - data_in(21) => \data_in[21]\, data_in(20) => - \data_in[20]\, data_in(19) => \data_in[19]\, data_in(18) - => \data_in[18]\, data_in(17) => \data_in[17]\, - data_in(16) => \data_in[16]\, data_in(15) => - \data_in[15]\, data_in(14) => \data_in[14]\, data_in(13) - => \data_in[13]\, data_in(12) => \data_in[12]\, - data_in(11) => \data_in[11]\, data_in(10) => - \data_in[10]\, data_in(9) => \data_in[9]\, data_in(8) => - \data_in[8]\, data_in(7) => \data_in[7]\, data_in(6) => - \data_in[6]\, data_in(5) => \data_in[5]\, data_in(4) => - \data_in[4]\, data_in(3) => \data_in[3]\, data_in(2) => - \data_in[2]\, data_in(1) => \data_in[1]\, data_in(0) => - \data_in[0]\, hresp(0) => \ahbso_0.hresp[0]\, address(31) - => \memo.address[31]\, address(30) => \memo.address[30]\, - address(29) => \memo.address[29]\, address(28) => - \memo.address[28]\, romsn_c(1) => \romsn_c[1]\, - romsn_c(0) => \romsn_c[0]\, ramoen_c(3) => \ramoen_c[3]\, - ramoen_c(2) => \ramoen_c[2]\, ramoen_c(1) => - \ramoen_c[1]\, ramoen_c(0) => \ramoen_c[0]\, hmbsel_1(0) - => \ahbsi.hmbsel_1[0]\, hburst_0(2) => \ahbsi.hburst[2]\, - hburst_0(1) => \ahbsi.hburst[1]\, hburst_0(0) => - \ahbsi.hburst[0]\, hmbsel(0) => \ahbsi.hmbsel[0]\, - ramrws_1 => \sr1.r.mcfg2.ramrws[1]\, ramwws(1) => - \sr1.r.mcfg2.ramwws[1]\, ramwws(0) => - \sr1.r.mcfg2.ramwws[0]\, pwdata_1_3 => \apbi.pwdata_1[4]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, pwdata_1_2 => - \apbi.pwdata_1[3]\, rwen_c(3) => \rwen_c[3]\, rwen_c(2) - => \rwen_c[2]\, rwen_c(1) => \rwen_c[1]\, rwen_c(0) => - \rwen_c[0]\, iosn_1_8 => \sr1.iosn_1[101]\, iosn_1_0 => - \sr1.iosn_1[93]\, ramsn_c(3) => \ramsn_c[3]\, ramsn_c(2) - => \ramsn_c[2]\, ramsn_c(1) => \ramsn_c[1]\, ramsn_c(0) - => \ramsn_c[0]\, rambanksz_0 => - \sr1.r.mcfg2.rambanksz[0]\, rambanksz_1 => - \sr1.r.mcfg2.rambanksz[1]\, rambanksz_3 => - \sr1.r.mcfg2.rambanksz[3]\, paddr_2(2) => - \apbi.paddr_2[2]\, iows_3 => \sr1.r.mcfg1.iows[3]\, - iows_2 => \sr1.r.mcfg1.iows[2]\, pwdata_23 => - \apbi.pwdata[28]\, pwdata_22 => \apbi.pwdata[27]\, - pwdata_0_d0 => \apbi.pwdata[5]\, pwdata_7 => - \apbi.pwdata[12]\, pwdata_6 => \apbi.pwdata[11]\, - pwdata_5 => \apbi.pwdata[10]\, pwdata_4 => - \apbi.pwdata[9]\, pwdata_1_d0 => \apbi.pwdata[6]\, - pwdata_18 => \apbi.pwdata[23]\, pwdata_17 => - \apbi.pwdata[22]\, pwdata_16 => \apbi.pwdata[21]\, - pwdata_15 => \apbi.pwdata[20]\, pwdata_20 => - \apbi.pwdata[25]\, pwdata_21 => \apbi.pwdata[26]\, - pwdata_14 => \apbi.pwdata[19]\, pwdata_0_5 => - \apbi.pwdata_0[5]\, pwdata_0_7 => \apbi.pwdata_0[7]\, - pwdata_0_8 => \apbi.pwdata_0[8]\, pwdata_0_9 => - \apbi.pwdata_0[9]\, pwdata_0_2 => \apbi.pwdata_0[2]\, - pwdata_0_1 => \apbi.pwdata_0[1]\, pwdata_0_0 => - \apbi.pwdata_0[0]\, pwdata_0_6 => \apbi.pwdata_0[6]\, - pwdata_0_11 => \apbi.pwdata_0[11]\, hsize(1) => - \ahbsi.hsize[1]\, hsize(0) => \ahbsi.hsize[0]\, romrws_1 - => \sr1.r.mcfg1.romrws[1]\, romrws_3 => - \sr1.r.mcfg1.romrws[3]\, romrws_2 => - \sr1.r.mcfg1.romrws[2]\, hwdata_m_0_3 => - \ahbsi.hwdata_m_0[15]\, hwdata_m_0_2 => - \ahbsi.hwdata_m_0[14]\, hwdata_m_0_0 => - \ahbsi.hwdata_m_0[12]\, psel(0) => \apbi.psel[0]\, - romwidth(1) => \sr1.r.mcfg1.romwidth[1]\, romwidth(0) => - \sr1.r.mcfg1.romwidth[0]\, iosn_100 => \sr1.iosn[101]\, - iosn_99 => \sr1.iosn[100]\, address_c(27) => - \address_c[27]\, address_c(26) => \address_c[26]\, - address_c(25) => \address_c[25]\, address_c(24) => - \address_c[24]\, address_c(23) => \address_c[23]\, - address_c(22) => \address_c[22]\, address_c(21) => - \address_c[21]\, address_c(20) => \address_c[20]\, - address_c(19) => \address_c[19]\, address_c(18) => - \address_c[18]\, address_c(17) => \address_c[17]\, - address_c(16) => \address_c[16]\, address_c(15) => - \address_c[15]\, address_c(14) => \address_c[14]\, - address_c(13) => \address_c[13]\, address_c(12) => - \address_c[12]\, address_c(11) => \address_c[11]\, - address_c(10) => \address_c[10]\, address_c(9) => - \address_c[9]\, address_c(8) => \address_c[8]\, - address_c(7) => \address_c[7]\, address_c(6) => - \address_c[6]\, address_c(5) => \address_c[5]\, - address_c(4) => \address_c[4]\, address_c(3) => - \address_c[3]\, address_c(2) => \address_c[2]\, - address_c(1) => \address_c[1]\, address_c(0) => - \address_c[0]\, hwdata_m_8 => \ahbsi.hwdata_m[15]\, - hwdata_m_7 => \ahbsi.hwdata_m[14]\, hwdata_m_5 => - \ahbsi.hwdata_m[12]\, hwdata_m_0_d0 => - \ahbsi.hwdata_m[7]\, hwdata_m_13 => \ahbsi.hwdata_m[20]\, - data(31) => \memo.data[31]\, data(30) => \memo.data[30]\, - data(29) => \memo.data[29]\, data(28) => \memo.data[28]\, - data(27) => \memo.data[27]\, data(26) => \memo.data[26]\, - data(25) => \memo.data[25]\, data(24) => \memo.data[24]\, - data(23) => \memo.data[23]\, data(22) => \memo.data[22]\, - data(21) => \memo.data[21]\, data(20) => \memo.data[20]\, - data(19) => \memo.data[19]\, data(18) => \memo.data[18]\, - data(17) => \memo.data[17]\, data(16) => \memo.data[16]\, - data(15) => \memo.data[15]\, data(14) => \memo.data[14]\, - data(13) => \memo.data[13]\, data(12) => \memo.data[12]\, - data(11) => \memo.data[11]\, data(10) => \memo.data[10]\, - data(9) => \memo.data[9]\, data(8) => \memo.data[8]\, - data(7) => \memo.data[7]\, data(6) => \memo.data[6]\, - data(5) => \memo.data[5]\, data(4) => \memo.data[4]\, - data(3) => \memo.data[3]\, data(2) => \memo.data[2]\, - data(1) => \memo.data[1]\, data(0) => \memo.data[0]\, - haddr(30) => \ahbsi.haddr[30]\, haddr(29) => - \ahbsi.haddr[29]\, haddr(28) => \ahbsi.haddr[28]\, - haddr(27) => \ahbsi.haddr[27]\, haddr(26) => - \ahbsi.haddr[26]\, haddr(25) => \ahbsi.haddr[25]\, - haddr(24) => \ahbsi.haddr[24]\, haddr(23) => - \ahbsi.haddr[23]\, haddr(22) => \ahbsi.haddr[22]\, - haddr(21) => \ahbsi.haddr[21]\, haddr(20) => - \ahbsi.haddr[20]\, haddr(19) => \ahbsi.haddr[19]\, - haddr(18) => \ahbsi.haddr[18]\, haddr(17) => - \ahbsi.haddr[17]\, haddr(16) => \ahbsi.haddr[16]\, - haddr(15) => \ahbsi.haddr[15]\, haddr(14) => - \ahbsi.haddr[14]\, haddr(13) => \ahbsi.haddr[13]\, - haddr(12) => \ahbsi.haddr[12]\, haddr(11) => - \ahbsi.haddr[11]\, haddr(10) => \ahbsi.haddr[10]\, - haddr(9) => \ahbsi.haddr[9]\, haddr(8) => - \ahbsi.haddr[8]\, haddr(7) => \ahbsi.haddr[7]\, haddr(6) - => \ahbsi.haddr[6]\, haddr(5) => \ahbsi.haddr[5]\, - haddr(4) => \ahbsi.haddr[4]\, haddr(3) => - \ahbsi.haddr[3]\, haddr(2) => \ahbsi.haddr[2]\, haddr(1) - => \ahbsi.haddr[1]\, haddr(0) => \ahbsi.haddr[0]\, - ramwidth(1) => \sr1.r.mcfg2.ramwidth[1]\, ramwidth(0) => - \sr1.r.mcfg2.ramwidth[0]\, htrans(1) => \ahbsi.htrans[1]\, - htrans(0) => \ahbsi.htrans[0]\, iosn_0(93) => - \sr1.iosn_0[93]\, hsel_i(0) => \ahbsi.hsel_i[0]\, - romwws(3) => \sr1.r.mcfg1.romwws[3]\, romwws(2) => - \sr1.r.mcfg1.romwws[2]\, romwws(1) => - \sr1.r.mcfg1.romwws[1]\, romwws(0) => - \sr1.r.mcfg1.romwws[0]\, prdata_0 => \apbo_0.prdata[20]\, - prdata_1 => \apbo_0.prdata[21]\, prdata_8 => - \apbo_0.prdata[28]\, prdata_7 => \apbo_0.prdata[27]\, - hrdata(31) => \ahbso_0.hrdata[31]\, hrdata(30) => - \ahbso_0.hrdata[30]\, hrdata(29) => \ahbso_0.hrdata[29]\, - hrdata(28) => \ahbso_0.hrdata[28]\, hrdata(27) => - \ahbso_0.hrdata[27]\, hrdata(26) => \ahbso_0.hrdata[26]\, - hrdata(25) => \ahbso_0.hrdata[25]\, hrdata(24) => - \ahbso_0.hrdata[24]\, hrdata(23) => \ahbso_0.hrdata[23]\, - hrdata(22) => \ahbso_0.hrdata[22]\, hrdata(21) => - \ahbso_0.hrdata[21]\, hrdata(20) => \ahbso_0.hrdata[20]\, - hrdata(19) => \ahbso_0.hrdata[19]\, hrdata(18) => - \ahbso_0.hrdata[18]\, hrdata(17) => \ahbso_0.hrdata[17]\, - hrdata(16) => \ahbso_0.hrdata[16]\, hrdata(15) => - \ahbso_0.hrdata[15]\, hrdata(14) => \ahbso_0.hrdata[14]\, - hrdata(13) => \ahbso_0.hrdata[13]\, hrdata(12) => - \ahbso_0.hrdata[12]\, hrdata(11) => \ahbso_0.hrdata[11]\, - hrdata(10) => \ahbso_0.hrdata[10]\, hrdata(9) => - \ahbso_0.hrdata[9]\, hrdata(8) => \ahbso_0.hrdata[8]\, - hrdata(7) => \ahbso_0.hrdata[7]\, hrdata(6) => - \ahbso_0.hrdata[6]\, hrdata(5) => \ahbso_0.hrdata[5]\, - hrdata(4) => \ahbso_0.hrdata[4]\, hrdata(3) => - \ahbso_0.hrdata[3]\, hrdata(2) => \ahbso_0.hrdata[2]\, - hrdata(1) => \ahbso_0.hrdata[1]\, hrdata(0) => - \ahbso_0.hrdata[0]\, hwdata_4 => \ahbsi.hwdata[4]\, - hwdata_3 => \ahbsi.hwdata[3]\, hwdata_8 => - \ahbsi.hwdata[8]\, hwdata_13 => \ahbsi.hwdata[13]\, - hwdata_24 => \ahbsi.hwdata[24]\, hwdata_23 => - \ahbsi.hwdata[23]\, hwdata_22 => \ahbsi.hwdata[22]\, - hwdata_20 => \ahbsi.hwdata[20]\, hwdata_10 => - \ahbsi.hwdata[10]\, hwdata_26 => \ahbsi.hwdata[26]\, - hwdata_9 => \ahbsi.hwdata[9]\, hwdata_16 => - \ahbsi.hwdata[16]\, hwdata_17 => \ahbsi.hwdata[17]\, - hwdata_7 => \ahbsi.hwdata[7]\, hwdata_30 => - \ahbsi.hwdata[30]\, hwdata_28 => \ahbsi.hwdata[28]\, - hwdata_5 => \ahbsi.hwdata[5]\, hwdata_31 => - \ahbsi.hwdata[31]\, hwdata_1 => \ahbsi.hwdata[1]\, - hwdata_19 => \ahbsi.hwdata[19]\, hwdata_29 => - \ahbsi.hwdata[29]\, hwdata_21 => \ahbsi.hwdata[21]\, - hwdata_18 => \ahbsi.hwdata[18]\, hwdata_0 => - \ahbsi.hwdata[0]\, hwdata_6 => \ahbsi.hwdata[6]\, - hwdata_2 => \ahbsi.hwdata[2]\, hwdata_27 => - \ahbsi.hwdata[27]\, hwdata_11 => \ahbsi.hwdata[11]\, - hwdata_25 => \ahbsi.hwdata[25]\, bdrive_i(3) => - \memo.bdrive_i[3]\, bdrive_i(2) => \memo.bdrive_i[2]\, - bdrive_i(1) => \memo.bdrive_i[1]\, bdrive_i(0) => - \memo.bdrive_i[0]\, paddr(3) => \apbi.paddr[3]\, paddr(2) - => \apbi.paddr[2]\, iosn_c => iosn_c, lclk_c => lclk_c, - N_6455 => N_6455, N_5062 => N_5062, un6_ioen_NE_0 => - \ahb0.comb.0.4.un6_ioen_NE_0\, N_510 => N_510, N_6459 => - N_6459, N_5070 => N_5070, bexcen => \sr1.r.mcfg1.bexcen\, - brdyen => \sr1.r.mcfg1.brdyen\, ioen => - \sr1.r.mcfg1.ioen\, writen_c => writen_c, hwrite_m_0_0 - => \ahbsi.hwrite_m_0_0\, hwrite => \ahbsi.hwrite\, - brmw_1 => \sr1.ctrl.brmw_1\, N_6550 => N_6550, oen_c => - oen_c, rdata61_2 => \ua1.uart1.uartop.rdata61_2\, - un1_apbi_0 => \gpt.timer0.comb.un1_apbi_0\, brmw_i => - \sr1.ctrl.un1_r.brmw_i\, N_6377 => N_6377, rmw => - \sr1.r.mcfg2.rmw\, rstn => rstn, read_c => read_c, hready - => \ahbso_0.hready\, N_232_0 => \ua1.uart1.N_232_0\, - N_6455_0 => N_6455_0); - - SSRAM_CLK_pad_RNO : INV - port map(A => clk_c, Y => clk_c_i); - - \pci_ad_pad[12]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(12)); - - \gpio0.grgpio0\ : grgpio - port map(un1_grgpio0_7 => \gpio0.un1_grgpio0[71]\, - un1_grgpio0_5 => \gpio0.un1_grgpio0[69]\, gpio_in(7) => - \gpio_in[7]\, gpio_in(6) => \gpio_in[6]\, gpio_in(5) => - \gpio_in[5]\, gpio_in(4) => \gpio_in[4]\, gpio_in(3) => - \gpio_in[3]\, gpio_in(2) => \gpio_in[2]\, gpio_in(1) => - \gpio_in[1]\, gpio_in(0) => \gpio_in[0]\, pwdata_i(7) => - \apbi.pwdata_i[7]\, pwdata_i(6) => \apbi.pwdata_i[6]\, - pwdata_i(5) => \apbi.pwdata_i[5]\, pwdata_i(4) => - \apbi.pwdata_i[4]\, pwdata_i(3) => \apbi.pwdata_i[3]\, - pwdata_i(2) => \apbi.pwdata_i[2]\, pwdata_i(1) => - \apbi.pwdata_i[1]\, pwdata_i(0) => \apbi.pwdata_i[0]\, - paddr(5) => \apbi.paddr[5]\, paddr(4) => \apbi.paddr[4]\, - paddr(3) => \apbi.paddr[3]\, paddr(2) => \apbi.paddr[2]\, - readdata_2_m(5) => \gpio0.grgpio0.comb.readdata_2_m[5]\, - pwdata_1_0 => \apbi.pwdata_1[1]\, pwdata_1_3 => - \apbi.pwdata_1[4]\, pwdata_1_2 => \apbi.pwdata_1[3]\, - pwdata_0_5 => \apbi.pwdata_0[5]\, pwdata_0_7 => - \apbi.pwdata_0[7]\, pwdata_0_6 => \apbi.pwdata_0[6]\, - pwdata_0_2 => \apbi.pwdata_0[2]\, pwdata_0_0 => - \apbi.pwdata_0[0]\, dout(7) => \gpioo.dout[7]\, dout(6) - => \gpioo.dout[6]\, dout(5) => \gpioo.dout[5]\, dout(4) - => \gpioo.dout[4]\, dout(3) => \gpioo.dout[3]\, dout(2) - => \gpioo.dout[2]\, dout(1) => \gpioo.dout[1]\, dout(0) - => \gpioo.dout[0]\, psel(11) => \apbi.psel[11]\, - prdata_iv_0_0_d0 => \gpio0.grgpio0.apbo.prdata_iv_0[1]\, - prdata_iv_0_2 => \gpio0.grgpio0.apbo.prdata_iv_0[3]\, - prdata_iv_0_0(2) => \gpio0.grgpio0.apbo.prdata_iv_0_0[2]\, - oen_7 => \gpioo.oen[7]\, oen_i(7) => \gpioo.oen_i[7]\, - oen_i(6) => \gpioo.oen_i[6]\, oen_i(5) => - \gpioo.oen_i[5]\, oen_i(4) => \gpioo.oen_i[4]\, oen_i(3) - => \gpioo.oen_i[3]\, oen_i(2) => \gpioo.oen_i[2]\, - oen_i(1) => \gpioo.oen_i[1]\, oen_i(0) => - \gpioo.oen_i[0]\, paddr_0(3) => \apbi.paddr_0[3]\, - paddr_0(2) => \apbi.paddr_0[2]\, lclk_c => lclk_c, - N_232_2 => \ua1.uart1.N_232\, rdata61_2 => - \ua1.uart1.uartop.rdata61_2\, N_6432 => N_6432, rstn => - rstn, N_6439 => N_6439, N_6437 => N_6437, N_6436 => - N_6436, N_6435 => N_6435, N_6434 => N_6434, rdata60_4 => - \ua1.uart1.uartop.rdata60_4\, N_6430 => N_6430, rdata59_4 - => \ua1.uart1.uartop.rdata59_4\, N_6429 => N_6429, - N_6428 => N_6428, N_6459 => N_6459, readdata55_3 => - \gpt.timer0.comb.readdata55_3\, un1_apbi_0 => - \gpt.timer0.comb.un1_apbi_0\, rdata60_4_0 => - \ua1.uart1.uartop.rdata60_4_0\, N_232_0 => - \ua1.uart1.N_232_0\, N_232_1 => \ua1.uart1.N_232_1\); - - \data_pad[2]\ : BIBUF - port map(PAD => data(2), D => \memo.data[2]\, E => - \memo.bdrive_i[3]\, Y => \data_in[2]\); - - \sdo_adc_pad[4]\ : INBUF - port map(PAD => sdo_adc(4), Y => \sdo_adc_c[4]\); - - pci_perr_pad : OUTBUF - port map(D => \GND\, PAD => pci_perr); - - \rwen_pad[0]\ : OUTBUF - port map(D => \rwen_c[0]\, PAD => rwen(0)); - - \pci_ad_pad[28]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(28)); - - \address_pad[27]\ : OUTBUF - port map(D => \address_c[27]\, PAD => address(27)); - - \pci_ad_pad[4]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(4)); - - \pci_ad_pad[16]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(16)); - - \address_pad[6]\ : OUTBUF - port map(D => \address_c[6]\, PAD => address(6)); - - \address_pad[5]\ : OUTBUF - port map(D => \address_c[5]\, PAD => address(5)); - - d_m2_e : OR2B - port map(A => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a1_6_i_0\, - B => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_a0_6_i_0\, - Y => - \waveform_picker0.lpp_top_lfr_wf_picker_ip_1.lpp_waveform_1.pp_waveform_dma_1.lpp_dma_send_16word_1.un1_state_4.m19_0_N_15_i_0_li\); - - \data_pad[24]\ : BIBUF - port map(PAD => data(24), D => \memo.data[24]\, E => - \memo.bdrive_i[0]\, Y => \data_in[24]\); - - \pci_arb_gnt_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => pci_arb_gnt(1)); - - \data_pad[11]\ : BIBUF - port map(PAD => data(11), D => \memo.data[11]\, E => - \memo.bdrive_i[2]\, Y => \data_in[11]\); - - CE2_pad : OUTBUF - port map(D => CE2_c, PAD => CE2); - - \data_pad[8]\ : BIBUF - port map(PAD => data(8), D => \memo.data[8]\, E => - \memo.bdrive_i[2]\, Y => \data_in[8]\); - - \address_pad[26]\ : OUTBUF - port map(D => \address_c[26]\, PAD => address(26)); - - epause_pad : OUTBUF - port map(D => \GND\, PAD => epause); - - pci_trdy_pad : OUTBUF - port map(D => \GND\, PAD => pci_trdy); - - \pci_ad_pad[27]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(27)); - - oen_pad : OUTBUF - port map(D => oen_c, PAD => oen); - - \data_pad[22]\ : BIBUF - port map(PAD => data(22), D => \memo.data[22]\, E => - \memo.bdrive_i[1]\, Y => \data_in[22]\); - - \sdo_adc_pad[6]\ : INBUF - port map(PAD => sdo_adc(6), Y => \sdo_adc_c[6]\); - - \address_pad[17]\ : OUTBUF - port map(D => \address_c[17]\, PAD => address(17)); - - \data_pad[18]\ : BIBUF - port map(PAD => data(18), D => \memo.data[18]\, E => - \memo.bdrive_i[1]\, Y => \data_in[18]\); - - \data_pad[15]\ : BIBUF - port map(PAD => data(15), D => \memo.data[15]\, E => - \memo.bdrive_i[2]\, Y => \data_in[15]\); - - \pci_cbe_pad[1]\ : OUTBUF - port map(D => \GND\, PAD => pci_cbe(1)); - - \data_pad[0]\ : BIBUF - port map(PAD => data(0), D => \memo.data[0]\, E => - \memo.bdrive_i[3]\, Y => \data_in[0]\); - - \pci_ad_pad[31]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(31)); - - \pci_ad_pad[6]\ : OUTBUF - port map(D => \GND\, PAD => pci_ad(6)); - - -end DEF_ARCH; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/lpp-dm-sheldon-a3pe3000/config.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/lpp-dm-sheldon-a3pe3000/config.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/lpp-dm-sheldon-a3pe3000/config.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3e; - constant CFG_MEMTECH : integer := apa3e; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - --constant CFG_NWIN : integer := (7); -- PLE - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist - --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (3); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/lpp-dm-sheldon-a3pe3000/leon3mp.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/lpp-dm-sheldon-a3pe3000/leon3mp.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/lpp-dm-sheldon-a3pe3000/leon3mp.vhd +++ /dev/null @@ -1,508 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -library techmap; -use techmap.gencomp.all; -library gaisler; -use gaisler.memctrl.all; -use gaisler.leon3.all; -use gaisler.uart.all; -use gaisler.misc.all; -use gaisler.spacewire.all; -- PLE -library esa; -use esa.memoryctrl.all; -use work.config.all; -library lpp; ---use lpp.lpp_amba.all; -use lpp.lpp_memory.all; ---use lpp.lpp_uart.all; ---use lpp.lpp_matrix.all; ---use lpp.lpp_delay.all; ---use lpp.lpp_fft.all; ---use lpp.fft_components.all; ---use lpp.lpp_ad_conv.all; ---use lpp.iir_filter.all; -use lpp.general_purpose.all; ---use lpp.Filtercfg.all; -use lpp.lpp_lfr_time_management.all; -- PLE -use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE -use lpp.lpp_top_lfr_pkg.all; - -entity leon3mp is - generic ( - fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console - pclow : integer := CFG_PCLOW - ); - port ( - clk100MHz : in std_ulogic; - clk49_152MHz : in std_ulogic; - reset : in std_ulogic; - ramclk : out std_logic; - - ahbrxd : in std_ulogic; -- DSU rx data - ahbtxd : out std_ulogic; -- DSU tx data - dsubre : in std_ulogic; - dsuact : out std_ulogic; - urxd1 : in std_ulogic; -- UART1 rx data - utxd1 : out std_ulogic; -- UART1 tx data - errorn : out std_ulogic; - - address : out std_logic_vector(18 downto 0); - data : inout std_logic_vector(31 downto 0); - gpio : inout std_logic_vector(6 downto 0); -- I/O port - - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------In/Out----------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - led : out std_logic_vector(1 downto 0); - - -- waveform picker------ - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic; - - -- SPACEWIRE ----------- - spw1_din : in std_logic; -- PLE - spw1_sin : in std_logic; -- PLE - spw1_dout : out std_logic; -- PLE - spw1_sout : out std_logic; -- PLE - spw1_en_bar : out std_logic; - spw2_en_bar : out std_logic - ); -end; - -architecture Behavioral of leon3mp is - ---constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ --- CFG_GRETH+CFG_AHB_JTAG; -constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+1 -- 1 is for the SpaceWire module grspw2, which is a master - +1; -- 1 is for the waveform picker top -constant maxahbm : integer := maxahbmsp; - ---Clk & Rst géné -signal vcc : std_logic_vector(4 downto 0); -signal gnd : std_logic_vector(4 downto 0); -signal resetnl : std_ulogic; -signal clk2x : std_ulogic; -signal lclk2x : std_ulogic; -signal lclk25MHz : std_ulogic; -signal lclk50MHz : std_ulogic; -signal lclk100MHz : std_ulogic; -signal clkm : std_ulogic; -signal rstn : std_ulogic; -signal rstraw : std_ulogic; -signal pciclk : std_ulogic; -signal sdclkl : std_ulogic; -signal cgi : clkgen_in_type; -signal cgo : clkgen_out_type; ---- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); ---UART -signal ahbuarti : uart_in_type; -signal ahbuarto : uart_out_type; -signal apbuarti : uart_in_type; -signal apbuarto : uart_out_type; ---MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal wpo : wprot_out_type; -signal sdo : sdram_out_type; ---IRQ -signal irqi : irq_in_vector(0 to CFG_NCPU-1); -signal irqo : irq_out_vector(0 to CFG_NCPU-1); ---Timer -signal gpti : gptimer_in_type; -signal gpto : gptimer_out_type; ---GPIO -signal gpioi : gpio_in_type; -signal gpioo : gpio_out_type; ---DSU -signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); -signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); -signal dsui : dsu_in_type; -signal dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- -constant IOAEN : integer := CFG_CAN; -constant boardfreq : integer := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - signal coarse_time : std_logic_vector(31 downto 0); - signal fine_time : std_logic_vector(31 downto 0); - --- Spacewire signals - signal dtmp : std_ulogic; -- PLE - signal stmp : std_ulogic; -- PLE - signal rxclko : std_ulogic; -- PLE - signal swni : grspw_in_type; -- PLE - signal swno : grspw_out_type; -- PLE - signal clkmn : std_ulogic; -- PLE - signal txclk : std_ulogic; -- PLE 2013 02 14 - --- ahb status signals - signal stati : ahbstat_in_type; - -begin - ---------------------------------------------------------------------- ---- AJOUT TEST -------------------------------------IPs------------- ---------------------------------------------------------------------- - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (others => '1'); gnd <= (others => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad generic map (tech => padtech) port map (clk100MHz, lclk100MHz); - - -- IT SEEMS THAT THE PLL IS NOT INSTANTIATED AND THAT lclk2x is a 50 MHz CLOCK - clkgen0 : clkgen -- clock generator - generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - --port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); -- PLE - port map (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); -- PLE - - ramclk <= clkm; - -process(lclk100MHz) -begin - if lclk100MHz'event and lclk100MHz = '1' then - lclk50MHz <= not lclk50MHz; - end if; -end process; - -process(lclk50MHz) -begin - if lclk50MHz'event and lclk50MHz = '1' then - lclk25MHz <= not lclk25MHz; - end if; -end process; - -lclk2x <= lclk50MHz; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : if CFG_LEON3 = 1 generate - cpu : for i in 0 to CFG_NCPU-1 generate - u0 : leon3s -- LEON3 processor - generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - end generate; - errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); - - dsugen : if CFG_DSU = 1 generate - dsu0 : dsu3 -- LEON3 Debug Support Unit - generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); --- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); - dsui.enable <= '1'; - dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); - dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); - end generate; - end generate; - - nodsu : if CFG_DSU = 0 generate - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - end generate; - - irqctrl : if CFG_IRQ3_ENABLE /= 0 generate - irqctrl0 : irqmp -- interrupt controller - generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - port map (rstn, clkm, apbi, apbo(2), irqo, irqi); - end generate; - irq3 : if CFG_IRQ3_ENABLE = 0 generate - x : for i in 0 to CFG_NCPU-1 generate - irqi(i).irl <= "0000"; - end generate; - apbo(2) <= apb_none; - end generate; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - - memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - bdr : for i in 0 to 3 generate - data_pad : iopadv generic map (tech => padtech, width => 8) - port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), - memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); - end generate; - - - addr_pad : outpadv generic map (width => 19, tech => padtech) - port map (address, memo.address(20 downto 2)); - - - SSRAM_0:entity ssram_plugin - generic map (tech => padtech) - port map - (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - dcomgen : if CFG_AHB_UART = 1 generate - dcom0: ahbuart -- Debug UART - generic map (hindex => 3, pindex => 4, paddr => 4) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); - dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); - led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; - end generate; - nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR) - port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - - gpt : if CFG_GPT_ENABLE /= 0 generate - timer0 : gptimer -- timer unit - generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - port map (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; --- led(4) <= gpto.wdog; - end generate; - notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - ua1 : if CFG_UART1_ENABLE /= 0 generate - uart1 : apbuart -- UART 1 - generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; --- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; - end generate; - noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit - grgpio0: grgpio - generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) - port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : for i in 0 to 6 generate - pio_pad : iopad generic map (tech => padtech) - port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - end generate; - end generate; - --------------------------- --- APB_LFR_TIME_MANAGEMENT --------------------------- - lfrtimemanagement0 : apb_lfr_time_management - generic map(pindex => 6, paddr => 6, pmask => 16#fff#, - masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536, - pirq => 12) -- the IP uses 2 consecutive IRQ lines - port map(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6), - coarse_time, fine_time); - --------------------------------- --- APB_LFR_SPECTRAL_MATRICES_DMA --------------------------------- --- lfrspectralmatricesdma0 : apb_lfr_spectral_matrices_DMA --- generic map(pindex => 7, paddr =>7, pmask => 16#fff#) --- port map(clkm, rstn, apbi, apbo(7)); - ------------------------------- ---- AHB STATUS --------------- ------------------------------- - ---astat0 : ahbstat generic map(pindex => 13, paddr => 13, pirq => 14, nftslv => 3) --- port map(rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13)); --- stati.cerror(3 to NAHBSLV-1) <= (others => '0'); - ------------------- --- WAVEFORM PICKER ------------------- - -waveform_picker0 : lpp_top_lfr_wf_picker generic map( - hindex => 2, - pindex => 8, - paddr => 8, - pmask => 16#fff#, - pirq => 15, - tech => CFG_FABTECH, - nb_burst_available_size => 11, -- size of the register holding the nb of burst - nb_snapshot_param_size => 11, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 10, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 10 -- nb f0 ticks before starting the f1 snapshot - ) - port map( - -- ADS7886 - cnv_run => '1', -- stop the sampling request - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(8), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(2), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => Bias_Fails - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - -spw_phy0 : grspw2_phy generic map( - scantest => 0, - tech => memtech, - input_type => 0) -- self_clocking mode - port map( - rstn => rstn, - rxclki => clkm, rxclkin => clkmn, nrxclki => clkm, -- not used in self-clocking - di => dtmp, - si => stmp, - do => swni.d(1 downto 0), - dov => swni.dv(1 downto 0), - dconnect => swni.dconnect(1 downto 0), - rxclko => rxclko); - -sw0 : grspwm generic map(tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, usegen => 1, -- sysfreq not used by the core version 2? usegen? - nsync => 1, -- nsync not used by the core version 2? - rmap => 1, rmapcrc => 1, - fifosize1 => 16, fifosize2 => 16, - rxclkbuftype => 2, rxunaligned => 0, - spwcore => 2, - memtech => apa3e, - nodeaddr => 254, destkey => 2, - rmapbufs => 4, netlist => 0, ft => 0, ports => 2) - port map(rstn, clkm, rxclko, rxclko, txclk, txclk, - ahbmi, ahbmo(1), apbi, apbo(5), swni, swno); - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00001001"; -- divisor to get a 10M Hz tx clock from the txclk input - - - spw1_dout <= swno.d(0); - spw1_sout <= swno.s(0); - dtmp <= not(spw1_din); - stmp <= not(spw1_sin); - spw1_en_bar <= '0'; -- V16, connected to spw2_en - spw2_en_bar <= '1'; -- T18, connected to spw1_en - - txclk <= lclk100MHz; - -end Behavioral; \ No newline at end of file diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/modelsim/gaisler/i2c_slave_model/_primary.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/modelsim/gaisler/i2c_slave_model/_primary.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/modelsim/gaisler/i2c_slave_model/_primary.vhd +++ /dev/null @@ -1,17 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity i2c_slave_model is - generic( - I2C_ADR : integer := 80; - idle : integer := 0; - slave_ack : integer := 1; - get_mem_adr : integer := 2; - gma_ack : integer := 3; - data : integer := 4; - data_ack : integer := 5 - ); - port( - scl : in vl_logic; - sda : inout vl_logic - ); -end i2c_slave_model; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/testbench.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/testbench.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/testbench.vhd +++ /dev/null @@ -1,589 +0,0 @@ ------------------------------------------------------------------------------- --- LEON3 Demonstration design test bench --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2010, Aeroflex Gaisler --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; ---LIBRARY micron; ---USE micron.components.ALL; -USE work.debug.ALL; - -USE work.config.ALL; -- configuration - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -ENTITY testbench IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW; - - clkperiod : INTEGER := 20; -- system clock period - romwidth : INTEGER := 32; -- rom data width (8/32) - romdepth : INTEGER := 16; -- rom address depth - sramwidth : INTEGER := 32; -- ram data width (8/16/32) - sramdepth : INTEGER := 21; -- ram address depth - srambanks : INTEGER := 2 -- number of ram banks - ); - PORT ( - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC - ); -END; - -ARCHITECTURE behav OF testbench IS - - CONSTANT promfile : STRING := "prom.srec"; -- rom contents - CONSTANT sramfile : STRING := "sram.srec"; -- ram contents - CONSTANT sdramfile : STRING := "sdram.srec"; -- sdram contents - - COMPONENT leon3mp - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - resetn : IN STD_ULOGIC; - clk : IN STD_ULOGIC; - pllref : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dsutx : OUT STD_ULOGIC; -- DSU tx data - dsurx : IN STD_ULOGIC; -- DSU rx data - dsuen : IN STD_ULOGIC; - dsubre : IN STD_ULOGIC; - dsuact : OUT STD_ULOGIC; - txd1 : OUT STD_ULOGIC; -- UART1 tx data - rxd1 : IN STD_ULOGIC; -- UART1 rx data - txd2 : OUT STD_ULOGIC; -- UART1 tx data - rxd2 : IN STD_ULOGIC; -- UART1 rx datax - ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - oen : OUT STD_ULOGIC; - writen : OUT STD_ULOGIC; - read : OUT STD_ULOGIC; - iosn : OUT STD_ULOGIC; - romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - - emddis : OUT STD_LOGIC; - epwrdwn : OUT STD_LOGIC; - ereset : OUT STD_LOGIC; - esleep : OUT STD_LOGIC; - epause : OUT STD_LOGIC; - - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC; - pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - spw_clk : IN STD_ULOGIC; - spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - ramclk : OUT STD_LOGIC; - - nBWa : OUT STD_LOGIC; - nBWb : OUT STD_LOGIC; - nBWc : OUT STD_LOGIC; - nBWd : OUT STD_LOGIC; - nBWE : OUT STD_LOGIC; - nADSC : OUT STD_LOGIC; - nADSP : OUT STD_LOGIC; - nADV : OUT STD_LOGIC; - nGW : OUT STD_LOGIC; - nCE1 : OUT STD_LOGIC; - CE2 : OUT STD_LOGIC; - nCE3 : OUT STD_LOGIC; - nOE : OUT STD_LOGIC; - MODE : OUT STD_LOGIC; - SSRAM_CLK : OUT STD_LOGIC; - ZZ : OUT STD_LOGIC; - - tck, tms, tdi : IN STD_ULOGIC; - tdo : OUT STD_ULOGIC; - -- waveform picker------ - clk49_152MHz : in std_ulogic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic - - - - ); - END COMPONENT; - - COMPONENT CY7C1360C - GENERIC ( - addr_bits : INTEGER; - data_bits : INTEGER; - Cyp_tCO : TIME; - Cyp_tCYC : TIME; - Cyp_tCH : TIME; - Cyp_tCL : TIME; - Cyp_tCHZ : TIME; - Cyp_tCLZ : TIME; - Cyp_tOEHZ : TIME; - Cyp_tOELZ : TIME; - Cyp_tOEV : TIME; - Cyp_tAS : TIME; - Cyp_tADS : TIME; - Cyp_tADVS : TIME; - Cyp_tWES : TIME; - Cyp_tDS : TIME; - Cyp_tCES : TIME; - Cyp_tAH : TIME; - Cyp_tADH : TIME; - Cyp_tADVH : TIME; - Cyp_tWEH : TIME; - Cyp_tDH : TIME; - Cyp_tCEH : TIME); - PORT ( - iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) DOWNTO 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) DOWNTO 0); - iCLK : IN STD_LOGIC); - END COMPONENT; - - - SIGNAL clk : STD_LOGIC := '0'; - SIGNAL Rst : STD_LOGIC := '0'; -- Reset - CONSTANT ct : INTEGER := clkperiod/2; - - SIGNAL address : STD_LOGIC_VECTOR(27 DOWNTO 0); - SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL ioData : STD_LOGIC_VECTOR(35 DOWNTO 0); - - SIGNAL ramsn : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL ramoen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL rwen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL rwenx : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL romsn : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL iosn : STD_ULOGIC; - SIGNAL oen : STD_ULOGIC; - SIGNAL read : STD_ULOGIC; - SIGNAL writen : STD_ULOGIC; - SIGNAL brdyn : STD_ULOGIC; - SIGNAL bexcn : STD_ULOGIC; - SIGNAL wdog : STD_ULOGIC; - SIGNAL dsuen, dsutx, dsurx, dsubre, dsuact : STD_ULOGIC; - SIGNAL dsurst : STD_ULOGIC; - SIGNAL test : STD_ULOGIC; - SIGNAL error : STD_LOGIC; - SIGNAL gpio : STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); - SIGNAL GND : STD_ULOGIC := '0'; - SIGNAL VCC : STD_ULOGIC := '1'; - SIGNAL NC : STD_ULOGIC := 'Z'; - SIGNAL clk2 : STD_ULOGIC := '1'; - - SIGNAL sdcke : STD_LOGIC_VECTOR (1 DOWNTO 0); -- clk en - SIGNAL sdcsn : STD_LOGIC_VECTOR (1 DOWNTO 0); -- chip sel - SIGNAL sdwen : STD_ULOGIC; -- write en - SIGNAL sdrasn : STD_ULOGIC; -- row addr stb - SIGNAL sdcasn : STD_ULOGIC; -- col addr stb - SIGNAL sddqm : STD_LOGIC_VECTOR (7 DOWNTO 0); -- data i/o mask - SIGNAL sdclk : STD_ULOGIC; - SIGNAL plllock : STD_ULOGIC; - SIGNAL txd1, rxd1 : STD_ULOGIC; - SIGNAL txd2, rxd2 : STD_ULOGIC; - - SIGNAL etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : STD_LOGIC := '0'; - SIGNAL erxd, etxd : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); - SIGNAL erxdt, etxdt : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); - SIGNAL emdc : STD_LOGIC; - SIGNAL gtx_clk : STD_ULOGIC; - - SIGNAL emddis : STD_LOGIC; - SIGNAL epwrdwn : STD_LOGIC; - SIGNAL ereset : STD_LOGIC; - SIGNAL esleep : STD_LOGIC; - SIGNAL epause : STD_LOGIC; - - CONSTANT lresp : BOOLEAN := false; - - SIGNAL sa : STD_LOGIC_VECTOR(14 DOWNTO 0); - SIGNAL sd : STD_LOGIC_VECTOR(63 DOWNTO 0); - - SIGNAL pci_arb_req, pci_arb_gnt : STD_LOGIC_VECTOR(0 TO 3); - - - SIGNAL spw_clk : STD_ULOGIC := '0'; - SIGNAL spw_rxd : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxdn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxs : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxsn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_txd : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txdn : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txs : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txsn : STD_LOGIC_VECTOR(0 TO 2); - - SIGNAL tck, tms, tdi, tdo : STD_ULOGIC; - - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - CONSTANT CFG_SD64 : INTEGER := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64; - - ----------------------------------------------------------------------------- - - SIGNAL ramclk : STD_LOGIC; - - SIGNAL nBWa : STD_LOGIC; - SIGNAL nBWb : STD_LOGIC; - SIGNAL nBWc : STD_LOGIC; - SIGNAL nBWd : STD_LOGIC; - SIGNAL nBWE : STD_LOGIC; - SIGNAL nADSC : STD_LOGIC; - SIGNAL nADSP : STD_LOGIC; - SIGNAL nADV : STD_LOGIC; - SIGNAL nGW : STD_LOGIC; - SIGNAL nCE1 : STD_LOGIC; - SIGNAL CE2 : STD_LOGIC; - SIGNAL nCE3 : STD_LOGIC; - SIGNAL nOE : STD_LOGIC; - SIGNAL MODE : STD_LOGIC; - SIGNAL SSRAM_CLK : STD_LOGIC; - SIGNAL ZZ : STD_LOGIC; - - -- - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - - SIGNAL clk49_152MHz : STD_LOGIC := '0'; - SIGNAL sdo_adc : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL cnv_ch1 : STD_LOGIC; - SIGNAL sck_ch1 : STD_LOGIC; - SIGNAL Bias_Fails : STD_LOGIC; - -BEGIN - --- clock and reset - - spw_clk <= NOT spw_clk AFTER 20 ns; - spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0); - spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0); - spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1); - spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1); - spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2); - spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2); - clk <= NOT clk AFTER ct * 1 ns; - clk49_152MHz <= NOT clk49_152MHz AFTER 203 * 100 ps; - rst <= dsurst; - dsuen <= '1'; dsubre <= '0'; rxd1 <= '1'; - - d3 : leon3mp - GENERIC MAP (fabtech, - memtech, - padtech, - clktech, - disas, - dbguart, - pclow) - PORT MAP (rst, clk, sdclk, error, address(27 DOWNTO 0), data, - dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2, - ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio, - - emddis, epwrdwn, ereset, esleep, epause, - pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par, - pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt, - spw_clk, spw_rxd, spw_rxdn, spw_rxs, - spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, - - - ramclk , - nBWa , - nBWb , - nBWc , - nBWd , - nBWE , - nADSC , - nADSP , - nADV , - nGW , - nCE1 , - CE2 , - nCE3 , - nOE , - MODE , - SSRAM_CLK , - ZZ , - - tck, tms, tdi, tdo, - clk49_152MHz, - sdo_adc , - cnv_ch1 , - sck_ch1 , - Bias_Fails); - - - -- component instantiation - ----------------------------------------------------------------------------- - - MODULE_ADS7886 : FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => '1', - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => '1', - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc(7)); - - - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - - prom0 : FOR i IN 0 TO (romwidth/8)-1 GENERATE - sr0 : sram GENERIC MAP (index => i, abits => romdepth, fname => promfile) - PORT MAP (address(romdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), romsn(0), - rwen(i), oen); - END GENERATE; - - ----------------------------------------------------------------------------- - CY7C1360C_2 : CY7C1360C - GENERIC MAP ( - - - addr_bits => 19, - data_bits => 36, - - Cyp_tCO => 3.5 ns, -- Data Output Valid After CLK Rise - Cyp_tCYC => 6.0 ns, -- Clock cycle time - Cyp_tCH => 2.4 ns, -- Clock HIGH time - Cyp_tCL => 2.4 ns, -- Clock LOW time - Cyp_tCHZ => 3.5 ns, -- Clock to High-Z - Cyp_tCLZ => 1.25 ns, -- Clock to Low-Z - Cyp_tOEHZ => 3.5 ns, -- OE# HIGH to Output High-Z - Cyp_tOELZ => 0.0 ns, -- OE# LOW to Output Low-Z - Cyp_tOEV => 3.5 ns, -- OE# LOW to Output Valid - Cyp_tAS => 1.5 ns, -- Address Set-up Before CLK Rise - Cyp_tADS => 1.5 ns, -- ADSC#, ADSP# Set-up Before CLK Rise - Cyp_tADVS => 1.5 ns, -- ADV# Set-up Before CLK Rise - Cyp_tWES => 1.5 ns, -- BWx#, GW#, BWE# Set-up Before CLK Rise - Cyp_tDS => 1.5 ns, -- Data Input Set-up Before CLK Rise - Cyp_tCES => 1.5 ns, -- Chip Enable Set-up - Cyp_tAH => 0.5 ns, -- Address Hold After CLK Rise - Cyp_tADH => 0.5 ns, -- ADSC#, ADSP# Hold After CLK Rise - Cyp_tADVH => 0.5 ns, -- ADV# Hold After CLK Rise - Cyp_tWEH => 0.5 ns, -- BWx#, GW#, BWE# Hold After CLK Rise - Cyp_tDH => 0.5 ns, -- Data Input Hold After CLK Rise - Cyp_tCEH => 0.5 ns -- Chip Enable Hold After CLK Rise - - - --Cyp_tCO => 2.8 ns, - --Cyp_tCYC => 4.0 ns, - --Cyp_tCH => 1.8 ns, - --Cyp_tCL => 1.8 ns, - --Cyp_tCHZ => 2.8 ns, - --Cyp_tCLZ => 1.25 ns, - --Cyp_tOEHZ => 2.8 ns, - --Cyp_tOELZ => 0.0 ns, - --Cyp_tOEV => 2.8 ns, - --Cyp_tAS => 1.4 ns, - --Cyp_tADS => 1.4 ns, - --Cyp_tADVS => 1.4 ns, - --Cyp_tWES => 1.4 ns, - --Cyp_tDS => 1.4 ns, - --Cyp_tCES => 1.4 ns, - --Cyp_tAH => 0.4 ns, - --Cyp_tADH => 0.4 ns, - --Cyp_tADVH => 0.4 ns, - --Cyp_tWEH => 0.4 ns, - --Cyp_tDH => 0.4 ns, - --Cyp_tCEH => 0.4 ns - ) - PORT MAP ( - iZZ => ZZ, - iMode => MODE, - iADDR => address(20 DOWNTO 2), - inGW => nGW, - inBWE => nBWE, - inBWd => nBWd, - inBWc => nBWc, - inBWb => nBWb, - inBWa => nBWa, - inCE1 => nCE1, - iCE2 => CE2, - inCE3 => nCE3, - inADSP => nADSP, - inADSC => nADSC, - inADV => nADV, - inOE => nOE, - ioDQ => ioData, -- - iCLK => SSRAM_CLK); -- ?? - - - ioData <= "0" & data(31 DOWNTO 24) & - "0" & data(23 DOWNTO 16) & - "0" & data(15 DOWNTO 8) & - "0" & data(7 DOWNTO 0); - - --sbanks : FOR k IN 0 TO srambanks-1 GENERATE - -- sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE - -- sr0 : sram GENERIC MAP (index => i, abits => sramdepth, fname => sramfile) - -- PORT MAP (address(sramdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), - -- ramsn(k), rwen(i), ramoen(k)); - -- END GENERATE; - --END GENERATE; - - error <= 'H'; -- ERROR pull-up - - iuerr : PROCESS - BEGIN - WAIT FOR 2500 ns; - IF to_x01(error) = '1' THEN WAIT ON error; END IF; - ASSERT (to_x01(error) = '1') - REPORT "*** IU in error mode, simulation halted ***" - SEVERITY failure; - END PROCESS; - - data <= buskeep(data), (OTHERS => 'H') AFTER 250 ns; - sd <= buskeep(sd), (OTHERS => 'H') AFTER 250 ns; - - test0 : grtestmod - PORT MAP (rst, clk, error, address(21 DOWNTO 2), data, iosn, oen, writen, brdyn); - - - dsucom : PROCESS - PROCEDURE dsucfg(SIGNAL dsurx : IN STD_ULOGIC; SIGNAL dsutx : OUT STD_ULOGIC) IS - VARIABLE w32 : STD_LOGIC_VECTOR(31 DOWNTO 0); - VARIABLE c8 : STD_LOGIC_VECTOR(7 DOWNTO 0); - CONSTANT txp : TIME := 160 * 1 ns; - BEGIN - dsutx <= '1'; - dsurst <= '0'; - WAIT FOR 500 ns; - dsurst <= '1'; - WAIT; - WAIT FOR 5000 ns; - END; - BEGIN - - dsucfg(dsutx, dsurx); - WAIT; - - END PROCESS; - -END; diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/testbench_post.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/testbench_post.vhd deleted file mode 100644 --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-wfp/testbench_post.vhd +++ /dev/null @@ -1,770 +0,0 @@ ------------------------------------------------------------------------------- --- LEON3 Demonstration design test bench --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2010, Aeroflex Gaisler --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; ---LIBRARY micron; ---USE micron.components.ALL; -USE work.debug.ALL; - -USE work.config.ALL; -- configuration - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; - -ENTITY testbench IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - ncpu : INTEGER := CFG_NCPU; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW; - - clkperiod : INTEGER := 20; -- system clock period - romwidth : INTEGER := 32; -- rom data width (8/32) - romdepth : INTEGER := 16; -- rom address depth - sramwidth : INTEGER := 32; -- ram data width (8/16/32) - sramdepth : INTEGER := 21; -- ram address depth - srambanks : INTEGER := 2 -- number of ram banks - ); - PORT ( - pci_rst : INOUT STD_LOGIC; -- PCI bus - pci_clk : IN STD_ULOGIC; - pci_gnt : IN STD_ULOGIC; - pci_idsel : IN STD_ULOGIC; - pci_lock : INOUT STD_ULOGIC; - pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - pci_frame : INOUT STD_ULOGIC; - pci_irdy : INOUT STD_ULOGIC; - pci_trdy : INOUT STD_ULOGIC; - pci_devsel : INOUT STD_ULOGIC; - pci_stop : INOUT STD_ULOGIC; - pci_perr : INOUT STD_ULOGIC; - pci_par : INOUT STD_ULOGIC; - pci_req : INOUT STD_ULOGIC; - pci_serr : INOUT STD_ULOGIC; - pci_host : IN STD_ULOGIC; - pci_66 : IN STD_ULOGIC - ); -END; - -ARCHITECTURE behav OF testbench IS - - CONSTANT promfile : STRING := "prom.srec"; -- rom contents - CONSTANT sramfile : STRING := "sram.srec"; -- ram contents - CONSTANT sdramfile : STRING := "sdram.srec"; -- sdram contents - - COMPONENT leon3mp_wfp - PORT ( - resetn : in std_logic; - clk : in std_logic; - pllref : in std_logic; - errorn : out std_logic; - address : out std_logic_vector(27 downto 0); - data : inout std_logic_vector(31 downto 0) := (others => 'Z'); - dsutx : out std_logic; - dsurx : in std_logic; - dsuen : in std_logic; - dsubre : in std_logic; - dsuact : out std_logic; - txd1 : out std_logic; - rxd1 : in std_logic; - txd2 : out std_logic; - rxd2 : in std_logic; - ramsn : out std_logic_vector(4 downto 0); - ramoen : out std_logic_vector(4 downto 0); - rwen : out std_logic_vector(3 downto 0); - oen : out std_logic; - writen : out std_logic; - read : out std_logic; - iosn : out std_logic; - romsn : out std_logic_vector(1 downto 0); - gpio : inout std_logic_vector(7 downto 0) := (others => 'Z'); - emddis : out std_logic; - epwrdwn : out std_logic; - ereset : out std_logic; - esleep : out std_logic; - epause : out std_logic; - pci_rst : out std_logic; - pci_clk : in std_logic; - pci_gnt : in std_logic; - pci_idsel : in std_logic; - pci_lock : out std_logic; - pci_ad : out std_logic_vector(31 downto 0); - pci_cbe : out std_logic_vector(3 downto 0); - pci_frame : out std_logic; - pci_irdy : out std_logic; - pci_trdy : out std_logic; - pci_devsel : out std_logic; - pci_stop : out std_logic; - pci_perr : out std_logic; - pci_par : out std_logic; - pci_req : out std_logic; - pci_serr : out std_logic; - pci_host : in std_logic; - pci_66 : in std_logic; - pci_arb_req : in std_logic_vector(0 to 3); - pci_arb_gnt : out std_logic_vector(0 to 3); - spw_clk : in std_logic; - spw_rxd : in std_logic_vector(0 to 2); - spw_rxdn : in std_logic_vector(0 to 2); - spw_rxs : in std_logic_vector(0 to 2); - spw_rxsn : in std_logic_vector(0 to 2); - spw_txd : out std_logic_vector(0 to 2); - spw_txdn : out std_logic_vector(0 to 2); - spw_txs : out std_logic_vector(0 to 2); - spw_txsn : out std_logic_vector(0 to 2); - ramclk : out std_logic; - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; - tck : in std_logic; - tms : in std_logic; - tdi : in std_logic; - tdo : out std_logic; - clk49_152MHz : in std_logic; - sdo_adc : in std_logic_vector(7 downto 0); - cnv_ch1 : out std_logic; - sck_ch1 : out std_logic; - Bias_Fails : out std_logic); - END COMPONENT; - - - - --COMPONENT leon3mp - -- GENERIC ( - -- fabtech : INTEGER := CFG_FABTECH; - -- memtech : INTEGER := CFG_MEMTECH; - -- padtech : INTEGER := CFG_PADTECH; - -- clktech : INTEGER := CFG_CLKTECH; - -- disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - -- dbguart : INTEGER := CFG_DUART; -- Print UART on console - -- pclow : INTEGER := CFG_PCLOW - -- ); - -- PORT ( - -- resetn : IN STD_ULOGIC; - -- clk : IN STD_ULOGIC; - -- pllref : IN STD_ULOGIC; - -- errorn : OUT STD_ULOGIC; - -- address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); - -- data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - -- dsutx : OUT STD_ULOGIC; -- DSU tx data - -- dsurx : IN STD_ULOGIC; -- DSU rx data - -- dsuen : IN STD_ULOGIC; - -- dsubre : IN STD_ULOGIC; - -- dsuact : OUT STD_ULOGIC; - -- txd1 : OUT STD_ULOGIC; -- UART1 tx data - -- rxd1 : IN STD_ULOGIC; -- UART1 rx data - -- txd2 : OUT STD_ULOGIC; -- UART1 tx data - -- rxd2 : IN STD_ULOGIC; -- UART1 rx datax - -- ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - -- ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - -- rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - -- oen : OUT STD_ULOGIC; - -- writen : OUT STD_ULOGIC; - -- read : OUT STD_ULOGIC; - -- iosn : OUT STD_ULOGIC; - -- romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - -- gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port - - - -- emddis : OUT STD_LOGIC; - -- epwrdwn : OUT STD_LOGIC; - -- ereset : OUT STD_LOGIC; - -- esleep : OUT STD_LOGIC; - -- epause : OUT STD_LOGIC; - - -- pci_rst : INOUT STD_LOGIC; -- PCI bus - -- pci_clk : IN STD_ULOGIC; - -- pci_gnt : IN STD_ULOGIC; - -- pci_idsel : IN STD_ULOGIC; - -- pci_lock : INOUT STD_ULOGIC; - -- pci_ad : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - -- pci_cbe : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- pci_frame : INOUT STD_ULOGIC; - -- pci_irdy : INOUT STD_ULOGIC; - -- pci_trdy : INOUT STD_ULOGIC; - -- pci_devsel : INOUT STD_ULOGIC; - -- pci_stop : INOUT STD_ULOGIC; - -- pci_perr : INOUT STD_ULOGIC; - -- pci_par : INOUT STD_ULOGIC; - -- pci_req : INOUT STD_ULOGIC; - -- pci_serr : INOUT STD_ULOGIC; - -- pci_host : IN STD_ULOGIC; - -- pci_66 : IN STD_ULOGIC; - -- pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3); - -- pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3); - - -- spw_clk : IN STD_ULOGIC; - -- spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2); - -- spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2); - -- spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2); - -- spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2); - -- spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2); - -- spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2); - -- spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2); - -- spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2); - - -- ramclk : OUT STD_LOGIC; - - -- nBWa : OUT STD_LOGIC; - -- nBWb : OUT STD_LOGIC; - -- nBWc : OUT STD_LOGIC; - -- nBWd : OUT STD_LOGIC; - -- nBWE : OUT STD_LOGIC; - -- nADSC : OUT STD_LOGIC; - -- nADSP : OUT STD_LOGIC; - -- nADV : OUT STD_LOGIC; - -- nGW : OUT STD_LOGIC; - -- nCE1 : OUT STD_LOGIC; - -- CE2 : OUT STD_LOGIC; - -- nCE3 : OUT STD_LOGIC; - -- nOE : OUT STD_LOGIC; - -- MODE : OUT STD_LOGIC; - -- SSRAM_CLK : OUT STD_LOGIC; - -- ZZ : OUT STD_LOGIC; - - -- tck, tms, tdi : IN STD_ULOGIC; - -- tdo : OUT STD_ULOGIC; - -- -- waveform picker------ - -- clk49_152MHz : in std_ulogic; - -- sdo_adc : in std_logic_vector(7 downto 0); - -- cnv_ch1 : out std_logic; - -- sck_ch1 : out std_logic; - -- Bias_Fails : out std_logic - - - - -- ); - --END COMPONENT; - - COMPONENT CY7C1360C - GENERIC ( - addr_bits : INTEGER; - data_bits : INTEGER; - Cyp_tCO : TIME; - Cyp_tCYC : TIME; - Cyp_tCH : TIME; - Cyp_tCL : TIME; - Cyp_tCHZ : TIME; - Cyp_tCLZ : TIME; - Cyp_tOEHZ : TIME; - Cyp_tOELZ : TIME; - Cyp_tOEV : TIME; - Cyp_tAS : TIME; - Cyp_tADS : TIME; - Cyp_tADVS : TIME; - Cyp_tWES : TIME; - Cyp_tDS : TIME; - Cyp_tCES : TIME; - Cyp_tAH : TIME; - Cyp_tADH : TIME; - Cyp_tADVH : TIME; - Cyp_tWEH : TIME; - Cyp_tDH : TIME; - Cyp_tCEH : TIME); - PORT ( - iZZ : IN STD_LOGIC; - iMode : IN STD_LOGIC; - iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) DOWNTO 0); - inGW : IN STD_LOGIC; - inBWE : IN STD_LOGIC; - inBWd : IN STD_LOGIC; - inBWc : IN STD_LOGIC; - inBWb : IN STD_LOGIC; - inBWa : IN STD_LOGIC; - inCE1 : IN STD_LOGIC; - iCE2 : IN STD_LOGIC; - inCE3 : IN STD_LOGIC; - inADSP : IN STD_LOGIC; - inADSC : IN STD_LOGIC; - inADV : IN STD_LOGIC; - inOE : IN STD_LOGIC; - ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) DOWNTO 0); - iCLK : IN STD_LOGIC); - END COMPONENT; - - - SIGNAL clk : STD_LOGIC := '0'; - SIGNAL Rst : STD_LOGIC := '0'; -- Reset - CONSTANT ct : INTEGER := clkperiod/2; - - SIGNAL address : STD_LOGIC_VECTOR(27 DOWNTO 0); - SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL ioData : STD_LOGIC_VECTOR(35 DOWNTO 0); - - SIGNAL ramsn : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL ramoen : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL rwen : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL rwenx : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL romsn : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL iosn : STD_ULOGIC; - SIGNAL oen : STD_ULOGIC; - SIGNAL read : STD_ULOGIC; - SIGNAL writen : STD_ULOGIC; - SIGNAL brdyn : STD_ULOGIC; - SIGNAL bexcn : STD_ULOGIC; - SIGNAL wdog : STD_ULOGIC; - SIGNAL dsuen, dsutx, dsurx, dsubre, dsuact : STD_ULOGIC; - SIGNAL dsurst : STD_ULOGIC; - SIGNAL test : STD_ULOGIC; - SIGNAL error : STD_LOGIC; - SIGNAL gpio : STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); - SIGNAL GND : STD_ULOGIC := '0'; - SIGNAL VCC : STD_ULOGIC := '1'; - SIGNAL NC : STD_ULOGIC := 'Z'; - SIGNAL clk2 : STD_ULOGIC := '1'; - - SIGNAL sdcke : STD_LOGIC_VECTOR (1 DOWNTO 0); -- clk en - SIGNAL sdcsn : STD_LOGIC_VECTOR (1 DOWNTO 0); -- chip sel - SIGNAL sdwen : STD_ULOGIC; -- write en - SIGNAL sdrasn : STD_ULOGIC; -- row addr stb - SIGNAL sdcasn : STD_ULOGIC; -- col addr stb - SIGNAL sddqm : STD_LOGIC_VECTOR (7 DOWNTO 0); -- data i/o mask - SIGNAL sdclk : STD_ULOGIC; - SIGNAL plllock : STD_ULOGIC; - SIGNAL txd1, rxd1 : STD_ULOGIC; - SIGNAL txd2, rxd2 : STD_ULOGIC; - - SIGNAL etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : STD_LOGIC := '0'; - SIGNAL erxd, etxd : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); - SIGNAL erxdt, etxdt : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); - SIGNAL emdc : STD_LOGIC; - SIGNAL gtx_clk : STD_ULOGIC; - - SIGNAL emddis : STD_LOGIC; - SIGNAL epwrdwn : STD_LOGIC; - SIGNAL ereset : STD_LOGIC; - SIGNAL esleep : STD_LOGIC; - SIGNAL epause : STD_LOGIC; - - CONSTANT lresp : BOOLEAN := false; - - SIGNAL sa : STD_LOGIC_VECTOR(14 DOWNTO 0); - SIGNAL sd : STD_LOGIC_VECTOR(63 DOWNTO 0); - - SIGNAL pci_arb_req, pci_arb_gnt : STD_LOGIC_VECTOR(0 TO 3); - - - SIGNAL spw_clk : STD_ULOGIC := '0'; - SIGNAL spw_rxd : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxdn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxs : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_rxsn : STD_LOGIC_VECTOR(0 TO 2) := "000"; - SIGNAL spw_txd : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txdn : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txs : STD_LOGIC_VECTOR(0 TO 2); - SIGNAL spw_txsn : STD_LOGIC_VECTOR(0 TO 2); - - SIGNAL tck, tms, tdi, tdo : STD_ULOGIC; - - CONSTANT CFG_SDEN : INTEGER := CFG_SDCTRL + CFG_MCTRL_SDEN; - CONSTANT CFG_SD64 : INTEGER := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64; - - ----------------------------------------------------------------------------- - - SIGNAL ramclk : STD_LOGIC; - - SIGNAL nBWa : STD_LOGIC; - SIGNAL nBWb : STD_LOGIC; - SIGNAL nBWc : STD_LOGIC; - SIGNAL nBWd : STD_LOGIC; - SIGNAL nBWE : STD_LOGIC; - SIGNAL nADSC : STD_LOGIC; - SIGNAL nADSP : STD_LOGIC; - SIGNAL nADV : STD_LOGIC; - SIGNAL nGW : STD_LOGIC; - SIGNAL nCE1 : STD_LOGIC; - SIGNAL CE2 : STD_LOGIC; - SIGNAL nCE3 : STD_LOGIC; - SIGNAL nOE : STD_LOGIC; - SIGNAL MODE : STD_LOGIC; - SIGNAL SSRAM_CLK : STD_LOGIC; - SIGNAL ZZ : STD_LOGIC; - - -- - COMPONENT TestModule_ADS7886 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : IN STD_LOGIC; - sck : IN STD_LOGIC; - sdo : OUT STD_LOGIC); - END COMPONENT; - - - SIGNAL clk49_152MHz : STD_LOGIC := '0'; - SIGNAL sdo_adc : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL cnv_ch1 : STD_LOGIC; - SIGNAL sck_ch1 : STD_LOGIC; - SIGNAL Bias_Fails : STD_LOGIC; - -BEGIN - --- clock and reset - - spw_clk <= NOT spw_clk AFTER 20 ns; - spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0); - spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0); - spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1); - spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1); - spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2); - spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2); - clk <= NOT clk AFTER ct * 1 ns; - clk49_152MHz <= NOT clk49_152MHz AFTER 203 * 100 ps; - rst <= dsurst; - dsuen <= '1'; dsubre <= '0'; rxd1 <= '1'; - - --d3 : leon3mp - -- GENERIC MAP (fabtech, - -- memtech, - -- padtech, - -- clktech, - -- disas, - -- dbguart, - -- pclow) - -- PORT MAP (rst, clk, sdclk, error, address(27 DOWNTO 0), data, - -- dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2, - -- ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio, - - -- emddis, epwrdwn, ereset, esleep, epause, - -- pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, - -- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par, - -- pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt, - -- spw_clk, spw_rxd, spw_rxdn, spw_rxs, - -- spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, - - - -- ramclk , - -- nBWa , - -- nBWb , - -- nBWc , - -- nBWd , - -- nBWE , - -- nADSC , - -- nADSP , - -- nADV , - -- nGW , - -- nCE1 , - -- CE2 , - -- nCE3 , - -- nOE , - -- MODE , - -- SSRAM_CLK , - -- ZZ , - - -- tck, tms, tdi, tdo, - -- clk49_152MHz, - -- sdo_adc , - -- cnv_ch1 , - -- sck_ch1 , - -- Bias_Fails); - - - leon3mp_wfp_1: ENTITY work.leon3mp_wfp - PORT MAP ( - resetn => rst, - clk => clk, - pllref => sdclk, - errorn => error, - address => address(27 DOWNTO 0), - data => data(31 DOWNTO 0), - dsutx => dsutx, - dsurx => dsurx, - dsuen => dsuen, - dsubre => dsubre, - dsuact => dsuact, - txd1 => txd1, - rxd1 => rxd1, - txd2 => txd2, - rxd2 => rxd2, - ramsn => ramsn, - ramoen => ramoen, - rwen => rwen, - oen => oen, - writen => writen, - read => read, - iosn => iosn, - romsn => romsn, - gpio => gpio, - emddis => emddis, - epwrdwn => epwrdwn, - ereset => ereset, - esleep => esleep, - epause => epause, - - pci_rst => pci_rst, - pci_clk => pci_clk, - pci_gnt => pci_gnt, - pci_idsel => pci_idsel, - pci_lock => pci_lock, - pci_ad => pci_ad, - pci_cbe => pci_cbe, - pci_frame => pci_frame, - pci_irdy => pci_irdy, - pci_trdy => pci_trdy, - pci_devsel => pci_devsel, - pci_stop => pci_stop, - pci_perr => pci_perr, - pci_par => pci_par, - pci_req => pci_req, - pci_serr => pci_serr, - pci_host => pci_host, - pci_66 => pci_66, - pci_arb_req => pci_arb_req, - pci_arb_gnt => pci_arb_gnt, - spw_clk => spw_clk, - spw_rxd => spw_rxd, - spw_rxdn => spw_rxdn, - spw_rxs => spw_rxs, - spw_rxsn => spw_rxsn, - spw_txd => spw_txd, - spw_txdn => spw_txdn, - spw_txs => spw_txs, - spw_txsn => spw_txsn, - - ramclk => ramclk, - nBWa => nBWa, - nBWb => nBWb, - nBWc => nBWc, - nBWd => nBWd, - nBWE => nBWE, - nADSC => nADSC, - nADSP => nADSP, - nADV => nADV, - nGW => nGW, - nCE1 => nCE1, - CE2 => CE2, - nCE3 => nCE3, - nOE => nOE, - MODE => MODE, - SSRAM_CLK => SSRAM_CLK, - ZZ => ZZ, - - tck => tck, - tms => tms, - tdi => tdi, - tdo => tdo, - - clk49_152MHz => clk49_152MHz, - sdo_adc => sdo_adc, - cnv_ch1 => cnv_ch1, - sck_ch1 => sck_ch1, - Bias_Fails => Bias_Fails); - - -- component instantiation - ----------------------------------------------------------------------------- - - MODULE_ADS7886 : FOR I IN 0 TO 6 GENERATE - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 30000/(I+1), - impulsion => 0) - PORT MAP ( - cnv_run => '1', - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc(I)); - END GENERATE MODULE_ADS7886; - - TestModule_ADS7886_u : TestModule_ADS7886 - GENERIC MAP ( - freq => 0, - amplitude => 30000, - impulsion => 1) - PORT MAP ( - cnv_run => '1', - cnv => cnv_ch1, - sck => sck_ch1, - sdo => sdo_adc(7)); - - - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - - prom0 : FOR i IN 0 TO (romwidth/8)-1 GENERATE - sr0 : sram GENERIC MAP (index => i, abits => romdepth, fname => promfile) - PORT MAP (address(romdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), romsn(0), - rwen(i), oen); - END GENERATE; - - ----------------------------------------------------------------------------- - CY7C1360C_2 : CY7C1360C - GENERIC MAP ( - - - addr_bits => 19, - data_bits => 36, - - Cyp_tCO => 3.5 ns, -- Data Output Valid After CLK Rise - Cyp_tCYC => 6.0 ns, -- Clock cycle time - Cyp_tCH => 2.4 ns, -- Clock HIGH time - Cyp_tCL => 2.4 ns, -- Clock LOW time - Cyp_tCHZ => 3.5 ns, -- Clock to High-Z - Cyp_tCLZ => 1.25 ns, -- Clock to Low-Z - Cyp_tOEHZ => 3.5 ns, -- OE# HIGH to Output High-Z - Cyp_tOELZ => 0.0 ns, -- OE# LOW to Output Low-Z - Cyp_tOEV => 3.5 ns, -- OE# LOW to Output Valid - Cyp_tAS => 1.5 ns, -- Address Set-up Before CLK Rise - Cyp_tADS => 1.5 ns, -- ADSC#, ADSP# Set-up Before CLK Rise - Cyp_tADVS => 1.5 ns, -- ADV# Set-up Before CLK Rise - Cyp_tWES => 1.5 ns, -- BWx#, GW#, BWE# Set-up Before CLK Rise - Cyp_tDS => 1.5 ns, -- Data Input Set-up Before CLK Rise - Cyp_tCES => 1.5 ns, -- Chip Enable Set-up - Cyp_tAH => 0.5 ns, -- Address Hold After CLK Rise - Cyp_tADH => 0.5 ns, -- ADSC#, ADSP# Hold After CLK Rise - Cyp_tADVH => 0.5 ns, -- ADV# Hold After CLK Rise - Cyp_tWEH => 0.5 ns, -- BWx#, GW#, BWE# Hold After CLK Rise - Cyp_tDH => 0.5 ns, -- Data Input Hold After CLK Rise - Cyp_tCEH => 0.5 ns -- Chip Enable Hold After CLK Rise - - - --Cyp_tCO => 2.8 ns, - --Cyp_tCYC => 4.0 ns, - --Cyp_tCH => 1.8 ns, - --Cyp_tCL => 1.8 ns, - --Cyp_tCHZ => 2.8 ns, - --Cyp_tCLZ => 1.25 ns, - --Cyp_tOEHZ => 2.8 ns, - --Cyp_tOELZ => 0.0 ns, - --Cyp_tOEV => 2.8 ns, - --Cyp_tAS => 1.4 ns, - --Cyp_tADS => 1.4 ns, - --Cyp_tADVS => 1.4 ns, - --Cyp_tWES => 1.4 ns, - --Cyp_tDS => 1.4 ns, - --Cyp_tCES => 1.4 ns, - --Cyp_tAH => 0.4 ns, - --Cyp_tADH => 0.4 ns, - --Cyp_tADVH => 0.4 ns, - --Cyp_tWEH => 0.4 ns, - --Cyp_tDH => 0.4 ns, - --Cyp_tCEH => 0.4 ns - ) - PORT MAP ( - iZZ => ZZ, - iMode => MODE, - iADDR => address(20 DOWNTO 2), - inGW => nGW, - inBWE => nBWE, - inBWd => nBWd, - inBWc => nBWc, - inBWb => nBWb, - inBWa => nBWa, - inCE1 => nCE1, - iCE2 => CE2, - inCE3 => nCE3, - inADSP => nADSP, - inADSC => nADSC, - inADV => nADV, - inOE => nOE, - ioDQ => ioData, -- - iCLK => SSRAM_CLK); -- ?? - - - ioData <= "0" & data(31 DOWNTO 24) & - "0" & data(23 DOWNTO 16) & - "0" & data(15 DOWNTO 8) & - "0" & data(7 DOWNTO 0); - - --sbanks : FOR k IN 0 TO srambanks-1 GENERATE - -- sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE - -- sr0 : sram GENERIC MAP (index => i, abits => sramdepth, fname => sramfile) - -- PORT MAP (address(sramdepth+1 DOWNTO 2), data(31-i*8 DOWNTO 24-i*8), - -- ramsn(k), rwen(i), ramoen(k)); - -- END GENERATE; - --END GENERATE; - - error <= 'H'; -- ERROR pull-up - - iuerr : PROCESS - BEGIN - WAIT FOR 2500 ns; - IF to_x01(error) = '1' THEN WAIT ON error; END IF; - ASSERT (to_x01(error) = '1') - REPORT "*** IU in error mode, simulation halted ***" - SEVERITY failure; - END PROCESS; - - data <= buskeep(data), (OTHERS => 'H') AFTER 250 ns; - sd <= buskeep(sd), (OTHERS => 'H') AFTER 250 ns; - - test0 : grtestmod - PORT MAP (rst, clk, error, address(21 DOWNTO 2), data, iosn, oen, writen, brdyn); - - - dsucom : PROCESS - PROCEDURE dsucfg(SIGNAL dsurx : IN STD_ULOGIC; SIGNAL dsutx : OUT STD_ULOGIC) IS - VARIABLE w32 : STD_LOGIC_VECTOR(31 DOWNTO 0); - VARIABLE c8 : STD_LOGIC_VECTOR(7 DOWNTO 0); - CONSTANT txp : TIME := 160 * 1 ns; - BEGIN - dsutx <= '1'; - dsurst <= '0'; - WAIT FOR 500 ns; - dsurst <= '1'; - WAIT; - WAIT FOR 5000 ns; - END; - BEGIN - - dsucfg(dsutx, dsurx); - WAIT; - - END PROCESS; - -END; diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/.config b/designs/ProjetBlanc-LeonLPP-A3PE3kL/.config deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/971A_lqfp.bsd b/designs/ProjetBlanc-LeonLPP-A3PE3kL/971A_lqfp.bsd deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/971A_lqfp.bsd +++ /dev/null @@ -1,262 +0,0 @@ --- --- Device: LXT971A --- Package: LQFP --- File Name: 971A_lqfp.bsdl --- --- Revision History --- 1.0 - Tim Jackson (4/29/2002) --- Legacy file 971Alqfp.txt renamed to 971A_lqfp.bsdl. --- Updated attribute IDCODE_REGISTER to handle revision ids 1 --- and 2 and their appropriate jedec continuation codes. --- Changed PWRDWN to a compliance enable and added a design --- warning to that effect. --- --- Notes --- This file has successfully compiled on the Agilent Technologies 3070 --- BSDL compiler. --- --- Disclaimer --- Intel Corporation ("Intel") hereby grants the user of this BSDL file --- ("User") a non-exclusive, nontransferable license to use the file --- under the following terms. User may only to use the BSDL file and --- is not granted rights to sell, copy (except as needed to run the BSDL --- file), rent, lease or sub-license the BSDL file in whole or in part, --- or in modified form to anyone. User may modify the BSDL file to suit --- its specific applications, but rights to derivative works and such --- modifications shall belong to Intel. This BSDL file is provided on an --- "AS IS" basis and Intel makes absolutely no warranty with respect to --- the information contained herein. INTEL DISCLAIMS AND USER WAIVES --- ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF --- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY --- OF NON-INFRINGEMENT OF THE INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD --- PARTY. THE ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH USER. --- ACCORDINGLY, IN NO EVENT SHALL INTEL BE LIABLE FOR ANY DIRECT OR --- INDIRECT DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING, WITHOUT --- LIMITATION, LOST PROFITS, BUSINESS INTERRUPTION, OR LOST INFORMATION) --- ARISING OUT OF THE USE OF OR INABILITY TO USE THE FILE, EVEN IF INTEL --- HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. --- --- This file is the legal property of Copyright (c) 2002, Intel --- Corporation. --- - -entity shark is - generic (PHYSICAL_PIN_MAP : string := "LQFP64"); - - port ( - GND : linkage bit_vector (1 to 7); - VCCIO : linkage bit_vector (1 to 2); - VCCA : linkage bit_vector (1 to 2); - VCCD : linkage bit ; - NC : linkage bit_vector (1 to 3); - XI : linkage bit ; - XO : linkage bit ; - MDDIS : in bit ; - Reset : in bit ; - TXSLEW0: in bit ; - TXSLEW1: in bit ; - ADDR0 : in bit ; - ADDR1 : in bit ; - ADDR2 : in bit ; - ADDR3 : in bit ; - ADDR4 : in bit ; - RBIAS : linkage bit ; - TPFOP : linkage bit ; - TPFON : linkage bit ; - TPFIP : linkage bit ; - TPFIN : linkage bit ; - SD_TP : in bit ; - TDI : in bit ; - TDO : out bit ; - TMS : in bit ; - TCK : in bit ; - TRST : in bit ; - SLEEP : in bit ; - PAUSE : in bit ; - TEST0 : in bit ; - TEST1 : in bit ; - LEDCFG2: inout bit ; - LEDCFG1: inout bit ; - LEDCFG0: inout bit ; - PWRDWN : in bit ; - MDIO : inout bit ; - MDC : in bit ; - RXD3 : out bit ; - RXD2 : out bit ; - RXD1 : out bit ; - RXD0 : out bit ; - RX_DV : out bit ; - RX_CLK : out bit ; - RX_ER : out bit ; - TX_ER : in bit ; - TX_CLK : out bit ; - TX_EN : in bit ; - TXD0 : in bit ; - TXD1 : in bit ; - TXD2 : in bit ; - TXD3 : in bit ; - COL : out bit ; - CRS : out bit ; - MDINT : out bit - - ); - - use STD_1149_1_1994.all; - use LXT971A_BSCAN.all; - - attribute COMPONENT_CONFORMANCE of shark: entity is "STD_1149_1_1993"; - - -- Pin mappings - - attribute PIN_MAP of shark: entity is PHYSICAL_PIN_MAP; - - constant LQFP64: PIN_MAP_STRING:= - "GND : (7,11,18,25,41,50,61),"& - "VCCIO : (8,40) ,"& - "VCCA : (21,22) ,"& - "VCCD : 51 ,"& - "NC : (9,10,44) ,"& - "XI : 1 ,"& - "XO : 2 ,"& - "MDDIS : 3 ,"& - "Reset : 4 ,"& - "TXSLEW0: 5 ,"& - "TXSLEW1: 6 ,"& - "ADDR0 : 12 ,"& - "ADDR1 : 13 ,"& - "ADDR2 : 14 ,"& - "ADDR3 : 15 ,"& - "ADDR4 : 16 ,"& - "RBIAS : 17 ,"& - "TPFOP : 19 ,"& - "TPFON : 20 ,"& - "TPFIP : 23 ,"& - "TPFIN : 24 ,"& - "SD_TP : 26 ,"& - "TDI : 27 ,"& - "TDO : 28 ,"& - "TMS : 29 ,"& - "TCK : 30 ,"& - "TRST : 31 ,"& - "SLEEP : 32 ,"& - "PAUSE : 33 ,"& - "TEST0 : 34 ,"& - "TEST1 : 35 ,"& - "LEDCFG2: 36 ,"& - "LEDCFG1: 37 ,"& - "LEDCFG0: 38 ,"& - "PWRDWN : 39 ,"& - "MDIO : 42 ,"& - "MDC : 43 ,"& - "RXD3 : 45 ,"& - "RXD2 : 46 ,"& - "RXD1 : 47 ,"& - "RXD0 : 48 ,"& - "RX_DV : 49 ,"& - "RX_CLK : 52 ,"& - "RX_ER : 53 ,"& - "TX_ER : 54 ,"& - "TX_CLK : 55 ,"& - "TX_EN : 56 ,"& - "TXD0 : 57 ,"& - "TXD1 : 58 ,"& - "TXD2 : 59 ,"& - "TXD3 : 60 ,"& - "COL : 62 ,"& - "CRS : 63 ,"& - "MDINT : 64 "; - - - - -- IEEE 1149.1 pin definition - attribute TAP_SCAN_RESET of TRST : signal is true; - attribute TAP_SCAN_IN of TDI : signal is true; - attribute TAP_SCAN_MODE of TMS : signal is true; - attribute TAP_SCAN_OUT of TDO : signal is true; - attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); - - -- IEEE 1149.1 compliance enable - attribute COMPLIANCE_PATTERNS of shark: entity is - "(PWRDWN) (0)"; - - -- IEEE 1149.1 definition for LV Software TAP - attribute INSTRUCTION_LENGTH of shark: entity is 16; - - attribute INSTRUCTION_OPCODE of shark: entity is - "IDCODE (1111111111111110)," & - "BYPASS (1111111111111111)," & - "EXTEST (0000000000000000,1111111111101000)," & - "SAMPLE (1111111111111000)," & - "HIGHZ (1111111111001111)," & - "CLAMP (1111111111101111)" ; - attribute INSTRUCTION_CAPTURE of shark: entity is "xxxxxxxxxxxxxx01"; - - attribute IDCODE_REGISTER of shark: entity is - "0001" & -- revision id 1 - "0000001111001011" & -- part number - "11101111110" & -- manufacturer's ID - "1," & -- required by 1149.1 - "0010" & -- revision id 2 - "0000001111001011" & -- part number - "00001111110" & -- manufacturer's ID - "1"; -- required by 1149.1 - - attribute REGISTER_ACCESS of shark: entity is - "BYPASS (HIGHZ, CLAMP) " ; - - --Boundary scan definition - attribute BOUNDARY_LENGTH of shark: entity is 40; - - attribute BOUNDARY_REGISTER of shark: entity is - -- num cell port function safe [ccell disval rslt] - " 0 (BC_2 , MDDIS , input , X ) ,"& - " 1 (BC_2 , Reset , input , X ) ,"& - " 2 (BC_2 , TXSLEW0 , input , X ) ,"& - " 3 (BC_2 , TXSLEW1 , input , X ) ,"& - " 4 (BC_2 , ADDR0 , input , X ) ,"& - " 5 (BC_2 , ADDR1 , input , X ) ,"& - " 6 (BC_2 , ADDR2 , input , X ) ,"& - " 7 (BC_2 , ADDR3 , input , X ) ,"& - " 8 (BC_2 , ADDR4 , input , X ) ,"& - " 9 (BC_2 , SD_TP , input , X ) ,"& - " 10 (BC_2 , SLEEP , input , X ) ,"& - " 11 (BC_2 , PAUSE , input , X ) ,"& - " 12 (BC_2 , TEST0 , input , X ) ,"& - " 13 (BC_2 , TEST1 , input , X ) ,"& - " 14 (BC_2 , * , control , 1 ) ,"& - " 15 (LV_BC_7 , LEDCFG2 , bidir , X , 14 , 1 , Z ),"& - " 16 (LV_BC_7 , LEDCFG1 , bidir , X , 14 , 1 , Z ),"& - " 17 (LV_BC_7 , LEDCFG0 , bidir , X , 14 , 1 , Z ),"& - " 18 (BC_2 , * , internal , 0 ) ,"& - " 19 (LV_BC_7 , MDIO , bidir , X , 14 , 1 , Z ),"& - " 20 (BC_2 , MDC , input , X ) ,"& - " 21 (BC_2 , * , internal , X ) ,"& - " 22 (BC_2 , RXD3 , output3 , X , 14 , 1 , Z ),"& - " 23 (BC_2 , RXD2 , output3 , X , 14 , 1 , Z ),"& - " 24 (BC_2 , RXD1 , output3 , X , 14 , 1 , Z ),"& - " 25 (BC_2 , RXD0 , output3 , X , 14 , 1 , Z ),"& - " 26 (BC_2 , RX_DV , output3 , X , 14 , 1 , Z ),"& - " 27 (BC_2 , RX_CLK , output3 , X , 14 , 1 , Z ),"& - " 28 (BC_2 , RX_ER , output3 , X , 14 , 1 , Z ),"& - " 29 (BC_2 , TX_ER , input , X ) ,"& - " 30 (BC_2 , TX_CLK , output3 , X , 14 , 1 , Z ),"& - " 31 (BC_2 , TX_EN , input , X ) ,"& - " 32 (BC_2 , TXD0 , input , X ) ,"& - " 33 (BC_2 , TXD1 , input , X ) ,"& - " 34 (BC_2 , TXD2 , input , X ) ,"& - " 35 (BC_2 , TXD3 , input , X ) ,"& - " 36 (BC_2 , * , internal , 0 ) ,"& - " 37 (BC_2 , COL , output3 , X , 14 , 1 , Z ),"& - " 38 (BC_2 , CRS , output3 , X , 14 , 1 , Z ),"& - " 39 (BC_2 , MDINT , output3 , X , 14 , 1 , Z ) "; - --- 1149.1 Design Warnings - attribute DESIGN_WARNING of shark: entity is - "PWRDWN pin should be kept low to allow proper operation" & - "of TAP circuitry. There is a compliance enable on this" & - "pin to force the safe value. The boundary scan cell" & - "associated with the PWRDWN pin has been changed to an" & - "internal pin. It is cell number 18 in the boundary scan" & - "register description and has a safe value of 0 specified"; - -end shark; diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/Makefile b/designs/ProjetBlanc-LeonLPP-A3PE3kL/Makefile deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -#GRLIB=../.. -VHDLIB=../.. -TOP=top -BOARD=LeonLPP-A3PE3kL -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSIMFILES=testbench.vhd -SIMTOP=testbench -SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/Projet-Blanc-A3PE3kL.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3 -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 - -FILESKIP = i2cmst.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/ahbrom.vhd b/designs/ProjetBlanc-LeonLPP-A3PE3kL/ahbrom.vhd deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/ahbrom.vhd +++ /dev/null @@ -1,232 +0,0 @@ - ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2009 Aeroflex Gaisler ----------------------------------------------------------------------------- --- Entity: ahbrom --- File: ahbrom.vhd --- Author: Jiri Gaisler - Gaisler Research --- Description: AHB rom. 0/1-waitstate read ----------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; - -entity ahbrom is - generic ( - hindex : integer := 0; - haddr : integer := 0; - hmask : integer := 16#fff#; - pipe : integer := 0; - tech : integer := 0; - kbytes : integer := 1); - port ( - rst : in std_ulogic; - clk : in std_ulogic; - ahbsi : in ahb_slv_in_type; - ahbso : out ahb_slv_out_type - ); -end; - -architecture rtl of ahbrom is -constant abits : integer := 10; -constant bytes : integer := 560; - -constant hconfig : ahb_config_type := ( - 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), - 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); - -signal romdata : std_logic_vector(31 downto 0); -signal addr : std_logic_vector(abits-1 downto 2); -signal hsel, hready : std_ulogic; - -begin - - ahbso.hresp <= "00"; - ahbso.hsplit <= (others => '0'); - ahbso.hirq <= (others => '0'); - ahbso.hcache <= '1'; - ahbso.hconfig <= hconfig; - ahbso.hindex <= hindex; - - reg : process (clk) - begin - if rising_edge(clk) then - addr <= ahbsi.haddr(abits-1 downto 2); - end if; - end process; - - p0 : if pipe = 0 generate - ahbso.hrdata <= ahbdrivedata(romdata); - ahbso.hready <= '1'; - end generate; - - p1 : if pipe = 1 generate - reg2 : process (clk) - begin - if rising_edge(clk) then - hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1); - hready <= ahbsi.hready; - ahbso.hready <= (not rst) or (hsel and hready) or - (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready); - ahbso.hrdata <= ahbdrivedata(romdata); - end if; - end process; - end generate; - - comb : process (addr) - begin - case conv_integer(addr) is - when 16#00000# => romdata <= X"81D82000"; - when 16#00001# => romdata <= X"03000004"; - when 16#00002# => romdata <= X"821060E0"; - when 16#00003# => romdata <= X"81884000"; - when 16#00004# => romdata <= X"81900000"; - when 16#00005# => romdata <= X"81980000"; - when 16#00006# => romdata <= X"81800000"; - when 16#00007# => romdata <= X"A1800000"; - when 16#00008# => romdata <= X"01000000"; - when 16#00009# => romdata <= X"03002040"; - when 16#0000A# => romdata <= X"8210600F"; - when 16#0000B# => romdata <= X"C2A00040"; - when 16#0000C# => romdata <= X"84100000"; - when 16#0000D# => romdata <= X"01000000"; - when 16#0000E# => romdata <= X"01000000"; - when 16#0000F# => romdata <= X"01000000"; - when 16#00010# => romdata <= X"01000000"; - when 16#00011# => romdata <= X"01000000"; - when 16#00012# => romdata <= X"80108002"; - when 16#00013# => romdata <= X"01000000"; - when 16#00014# => romdata <= X"01000000"; - when 16#00015# => romdata <= X"01000000"; - when 16#00016# => romdata <= X"01000000"; - when 16#00017# => romdata <= X"01000000"; - when 16#00018# => romdata <= X"87444000"; - when 16#00019# => romdata <= X"8608E01F"; - when 16#0001A# => romdata <= X"88100000"; - when 16#0001B# => romdata <= X"8A100000"; - when 16#0001C# => romdata <= X"8C100000"; - when 16#0001D# => romdata <= X"8E100000"; - when 16#0001E# => romdata <= X"A0100000"; - when 16#0001F# => romdata <= X"A2100000"; - when 16#00020# => romdata <= X"A4100000"; - when 16#00021# => romdata <= X"A6100000"; - when 16#00022# => romdata <= X"A8100000"; - when 16#00023# => romdata <= X"AA100000"; - when 16#00024# => romdata <= X"AC100000"; - when 16#00025# => romdata <= X"AE100000"; - when 16#00026# => romdata <= X"90100000"; - when 16#00027# => romdata <= X"92100000"; - when 16#00028# => romdata <= X"94100000"; - when 16#00029# => romdata <= X"96100000"; - when 16#0002A# => romdata <= X"98100000"; - when 16#0002B# => romdata <= X"9A100000"; - when 16#0002C# => romdata <= X"9C100000"; - when 16#0002D# => romdata <= X"9E100000"; - when 16#0002E# => romdata <= X"86A0E001"; - when 16#0002F# => romdata <= X"16BFFFEF"; - when 16#00030# => romdata <= X"81E00000"; - when 16#00031# => romdata <= X"82102002"; - when 16#00032# => romdata <= X"81904000"; - when 16#00033# => romdata <= X"03000004"; - when 16#00034# => romdata <= X"821060E0"; - when 16#00035# => romdata <= X"81884000"; - when 16#00036# => romdata <= X"01000000"; - when 16#00037# => romdata <= X"01000000"; - when 16#00038# => romdata <= X"01000000"; - when 16#00039# => romdata <= X"83480000"; - when 16#0003A# => romdata <= X"8330600C"; - when 16#0003B# => romdata <= X"80886001"; - when 16#0003C# => romdata <= X"02800024"; - when 16#0003D# => romdata <= X"01000000"; - when 16#0003E# => romdata <= X"07000000"; - when 16#0003F# => romdata <= X"8610E178"; - when 16#00040# => romdata <= X"C108C000"; - when 16#00041# => romdata <= X"C118C000"; - when 16#00042# => romdata <= X"C518C000"; - when 16#00043# => romdata <= X"C918C000"; - when 16#00044# => romdata <= X"CD18C000"; - when 16#00045# => romdata <= X"D118C000"; - when 16#00046# => romdata <= X"D518C000"; - when 16#00047# => romdata <= X"D918C000"; - when 16#00048# => romdata <= X"DD18C000"; - when 16#00049# => romdata <= X"E118C000"; - when 16#0004A# => romdata <= X"E518C000"; - when 16#0004B# => romdata <= X"E918C000"; - when 16#0004C# => romdata <= X"ED18C000"; - when 16#0004D# => romdata <= X"F118C000"; - when 16#0004E# => romdata <= X"F518C000"; - when 16#0004F# => romdata <= X"F918C000"; - when 16#00050# => romdata <= X"FD18C000"; - when 16#00051# => romdata <= X"01000000"; - when 16#00052# => romdata <= X"01000000"; - when 16#00053# => romdata <= X"01000000"; - when 16#00054# => romdata <= X"01000000"; - when 16#00055# => romdata <= X"01000000"; - when 16#00056# => romdata <= X"89A00842"; - when 16#00057# => romdata <= X"01000000"; - when 16#00058# => romdata <= X"01000000"; - when 16#00059# => romdata <= X"01000000"; - when 16#0005A# => romdata <= X"01000000"; - when 16#0005B# => romdata <= X"10800005"; - when 16#0005C# => romdata <= X"01000000"; - when 16#0005D# => romdata <= X"01000000"; - when 16#0005E# => romdata <= X"00000000"; - when 16#0005F# => romdata <= X"00000000"; - when 16#00060# => romdata <= X"87444000"; - when 16#00061# => romdata <= X"8730E01C"; - when 16#00062# => romdata <= X"8688E00F"; - when 16#00063# => romdata <= X"12800016"; - when 16#00064# => romdata <= X"03200000"; - when 16#00065# => romdata <= X"05040E00"; - when 16#00066# => romdata <= X"8410A233"; - when 16#00067# => romdata <= X"C4204000"; - when 16#00068# => romdata <= X"0539A89B"; - when 16#00069# => romdata <= X"8410A260"; - when 16#0006A# => romdata <= X"C4206004"; - when 16#0006B# => romdata <= X"050003FC"; - when 16#0006C# => romdata <= X"C4206008"; - when 16#0006D# => romdata <= X"82103860"; - when 16#0006E# => romdata <= X"C4004000"; - when 16#0006F# => romdata <= X"8530A00C"; - when 16#00070# => romdata <= X"03000004"; - when 16#00071# => romdata <= X"82106009"; - when 16#00072# => romdata <= X"80A04002"; - when 16#00073# => romdata <= X"12800006"; - when 16#00074# => romdata <= X"033FFC00"; - when 16#00075# => romdata <= X"82106100"; - when 16#00076# => romdata <= X"0539A81B"; - when 16#00077# => romdata <= X"8410A260"; - when 16#00078# => romdata <= X"C4204000"; - when 16#00079# => romdata <= X"05000080"; - when 16#0007A# => romdata <= X"82100000"; - when 16#0007B# => romdata <= X"80A0E000"; - when 16#0007C# => romdata <= X"02800005"; - when 16#0007D# => romdata <= X"01000000"; - when 16#0007E# => romdata <= X"82004002"; - when 16#0007F# => romdata <= X"10BFFFFC"; - when 16#00080# => romdata <= X"8620E001"; - when 16#00081# => romdata <= X"3D1003FF"; - when 16#00082# => romdata <= X"BC17A3E0"; - when 16#00083# => romdata <= X"BC278001"; - when 16#00084# => romdata <= X"9C27A060"; - when 16#00085# => romdata <= X"03100000"; - when 16#00086# => romdata <= X"81C04000"; - when 16#00087# => romdata <= X"01000000"; - when 16#00088# => romdata <= X"00000000"; - when 16#00089# => romdata <= X"00000000"; - when 16#0008A# => romdata <= X"00000000"; - when 16#0008B# => romdata <= X"00000000"; - when 16#0008C# => romdata <= X"00000000"; - when others => romdata <= (others => '-'); - end case; - end process; - -- pragma translate_off - bootmsg : report_version - generic map ("ahbrom" & tost(hindex) & - ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" ); - -- pragma translate_on - end; diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18.dc b/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18.dc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18.dc +++ /dev/null @@ -1,102 +0,0 @@ -/*******************************************/ -/* Script to compile leon with synopsys DC */ -/* Jiri Gaisler, Gaisler Research, 2004 */ -/*******************************************/ - -search_path = {"." "/usr/local/synopsys/libraries/syn" "c:/Synopsys/libraries/syn"} -target_library = "SClib-max+ind.db" -link_library = "SClib-max+ind.db IO33lib-max+ind.db atc18mem.db PCIlib-max+ind.db" -link_library = "*" + link_library -symbol_library = "IO33lib-max+ind.sdb SClib-max+ind.sdb generic.sdb" -allow_newer_db_files = "true"; - -/* constraints - tailor to your own technology. An average 0.35 std-cell tech - should give you 80 - 100 MHz depending on ram access time. A 0.25 tech - should run at +150 MHz. Frequency in MHz, delays in ns ... */ - -frequency = 200 -clock_skew = 0.10 -input_setup = 2.0 -output_delay = 4.0 - -/* don't touch anything from here unless you know what you are doing */ - -include leon3mp.dc -include atc18cond.dc - -ungroup find(cell, "*pad*") -flatten - -group find(cell, {"sr*", "sdc", "apb*", "uart*", "timer*", "irq*" \ - "ahb*", "dsu0", "rst0", "dcom*" }) -design_name amod \ - -cell_name amod0 - -current_instance u0_0/p0 -ungroup -all -flatten -current_instance ../rf0 -ungroup -all -flatten -current_instance ../cmem0 -ungroup -all -flatten -current_instance ../../amod0 -ungroup -all -flatten -current_instance .. - -peri = 1000.0 / frequency -input_delay = peri - input_setup -tdelay = output_delay + 2 -create_clock -name "clk" -period peri -waveform { 0.0, peri / 2.0 } { "clk" } -set_wire_load_mode segmented - -set_clock_skew -plus_uncertainty clock_skew "clk" -set_clock_skew -minus_uncertainty clock_skew "clk" - -/* -set_input_delay input_delay -clock clk { \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" "brdyn" "bexcn" } - -set_max_delay tdelay -to { "errorn" "wdogn" \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" } - -set_max_delay output_delay -to { \ - "writen" "romsn[1]" "romsn[0]" "read" "oen" \ - "iosn" "rwen[3]" "rwen[2]" "rwen[1]" "rwen[0]" "ramsn[3]" \ - "ramsn[2]" "ramsn[1]" "ramsn[0]" \ - "ramoen[3]" "ramoen[2]" "ramoen[1]" "ramoen[0]" \ - "sdcsn[1]" "sdcsn[0]" "sdwen" "sdrasn" "sdcasn" \ - "sddqm[3]" "sddqm[2]" "sddqm[1]" "sddqm[0]" \ - "address[27]" "address[26]" "address[25]" "address[24]" \ - "address[23]" "address[22]" "address[21]" "address[20]" \ - "address[19]" "address[18]" "address[17]" "address[16]" \ - "address[15]" "address[14]" "address[13]" "address[12]" \ - "address[11]" "address[10]" "address[9]" "address[8]" \ - "address[7]" "address[6]" "address[5]" "address[4]" \ - "address[3]" "address[2]" "address[1]" "address[0]"} - -*/ -set_max_area 0 -set_max_transition 2.0 leon3mp -set_flatten false -design {"leon3mp.db:leon3mp"} -set_structure true -design {"leon3mp.db:leon3mp"} -boolean false -timing true - - -compile -map_effort medium -boundary_optimization - -write -f db -hier leon3mp -output leon3mp.db - -report_timing -report_area diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18.rc b/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18.rc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18.rc +++ /dev/null @@ -1,8 +0,0 @@ -set_attribute lib_search_path {. /usr/local/rs41/libs} -set_attribute library {"SClib-max+ind.lib" "IO33lib-max+ind.lib" "/home/jiri/ibm/vhdl/temic/atc18/allmem.lib" } / -include leon3mp.rc -include atc18cond.rc -define_clock -period 5000 -name clock1 clk -synthesize -to_mapped -report_area -report_timing diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18cond.dc b/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18cond.dc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18cond.dc +++ /dev/null @@ -1,536 +0,0 @@ -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[31] -to do[31] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[32] -to do[32] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[33] -to do[33] - -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[31] -to do[31] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[32] -to do[32] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[33] -to do[33] - -set_disable_timing IO33lib-max+ind/pt33b01 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b02 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b03 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b04 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b01u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b02u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b03u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b04u -from pad -to cin diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18cond.rc b/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18cond.rc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/atc18cond.rc +++ /dev/null @@ -1,528 +0,0 @@ -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[31] -to do[31] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[32] -to do[32] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[33] -to do[33] - -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[31] -to do[31] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[32] -to do[32] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[33] -to do[33] - diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.help b/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.help deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.help +++ /dev/null @@ -1,1171 +0,0 @@ - - -Prompt for target technology -CONFIG_SYN_INFERRED - Selects the target technology for memory and pads. - The following are available: - - - Inferred: Generic FPGA or ASIC targets if your synthesis tool - is capable of inferring RAMs and pads automatically. - - - Actel ProAsic/P/3 and Axellerator FPGAs - - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS - - Altera: Most Altera FPGA families - - Altera-Stratix: Altera Stratix FPGA family - - Altera-StratixII: Altera Stratix-II FPGA family - - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS - - IHP25: IHP 0.25 um CMOS - - IHP25RH: IHP Rad-Hard 0.25 um CMOS - - Lattice : EC/ECP/XP FPGAs - - Quicklogic : Eclipse/E/II FPGAs - - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries - - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries - - Xilinx-Spartan3E: Xilinx Spartan3E libraries - - Xilinx-Virtex/E: Xilinx Virtex/E libraries - - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries - - -Ram library -CONFIG_MEM_VIRAGE - Select RAM generators for ASIC targets. - -Infer ram -CONFIG_SYN_INFER_RAM - Say Y here if you want the synthesis tool to infer your - RAM automatically. Say N to directly instantiate technology- - specific RAM cells for the selected target technology package. - -Infer pads -CONFIG_SYN_INFER_PADS - Say Y here if you want the synthesis tool to infer pads. - Say N to directly instantiate technology-specific pads from - the selected target technology package. - -No async reset -CONFIG_SYN_NO_ASYNC - Say Y here if you disable asynchronous reset in some of the IP cores. - Might be necessary if the target library does not have cells with - asynchronous set/reset. - -Scan support -CONFIG_SYN_SCAN - Say Y here to enable scan support in some cores. This will enable - the scan support generics where available and add logic to make - the design testable using full-scan. - -Use Virtex CLKDLL for clock synchronisation -CONFIG_CLK_INFERRED - Certain target technologies include clock generators to scale or - phase-adjust the system and SDRAM clocks. This is currently supported - for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you - can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2), - the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL - (Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred' - option to skip a clock generator. - -Clock multiplier -CONFIG_CLK_MUL - When using the Xilinx DCM or Altera ALTPLL, the system clock can - be multiplied with a factor of 2 - 32, and divided by a factor of - 1 - 32. This makes it possible to generate almost any desired - processor frequency. When using the Xilinx CLKDLL generator, - the resulting frequency scale factor (mul/div) must be one of - 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128. - - WARNING: The resulting clock must be within the limits specified - by the target FPGA family. - -Clock divider -CONFIG_CLK_DIV - When using the Xilinx DCM or Altera ALTPLL, the system clock can - be multiplied with a factor of 2 - 32, and divided by a factor of - 1 - 32. This makes it possible to generate almost any desired - processor frequency. When using the Xilinx CLKDLL generator, - the resulting frequency scale factor (mul/div) must be one of - 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128. - - WARNING: The resulting clock must be within the limits specified - by the target FPGA family. - -Output clock divider -CONFIG_OCLK_DIV - When using the Proasic3 PLL, the system clock is generated by three - parameters: input clock multiplication, input clock division and - output clock division. Only certain values of these parameters - are allowed, but unfortunately this is not documented by Actel. - To find the correct values, run the Libero Smartgen tool and - insert you desired input and output clock frequencies in the - Static PLL configurator. The mul/div factors can then be read - out from tool. - -System clock multiplier -CONFIG_CLKDLL_1_2 - The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0, - or 2.0. Useful when the target board has an oscillator with a too high - (or low) frequency for your design. The divided clock will be used as the - main clock for the whole processor (except PCI and ethernet clocks). - -System clock multiplier -CONFIG_DCM_2_3 - The Xilinx DCM and Altera ALTDLL can scale the input clock with a large - range of factors. Useful when the target board has an oscillator with a - too high (or low) frequency for your design. The divided clock will - be used as the main clock for the whole processor (except PCI and - ethernet clocks). NOTE: the resulting frequency must be at least - 24 MHz or the DCM and ALTDLL might not work. - -Enable CLKDLL for PCI clock -CONFIG_PCI_CLKDLL - Say Y here to re-synchronize the PCI clock using a - Virtex BUFGDLL macro. Will improve PCI clock-to-output - delays on the expense of input-setup requirements. - -Use PCI clock system clock -CONFIG_PCI_SYSCLK - Say Y here to the PCI clock to generate the system clock. - The PCI clock can be scaled using the DCM or CLKDLL to - generate a suitable processor clock. - -External SDRAM clock feedback -CONFIG_CLK_NOFB - Say Y here to disable the external clock feedback to synchronize the - SDRAM clock. This option is necessary if your board or design does not - have an external clock feedback that is connected to the pllref input - of the clock generator. - -Number of processors -CONFIG_PROC_NUM - The number of processor cores. The LEON3MP design can accomodate - up to 4 LEON3 processor cores. Use 1 unless you know what you are - doing ... - -Number of SPARC register windows -CONFIG_IU_NWINDOWS - The SPARC architecture (and LEON) allows 2 - 32 register windows. - However, any number except 8 will require that you modify and - recompile your run-time system or kernel. Unless you know what - you are doing, use 8. - -SPARC V8 multiply and divide instruction -CONFIG_IU_V8MULDIV - If you say Y here, the SPARC V8 multiply and divide instructions - will be implemented. The instructions are: UMUL, UMULCC, SMUL, - SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent - integer multiplications and divisions, significant performance - increase can be achieved. Emulated floating-point operations will - also benefit from this option. - - By default, the gcc compiler does not emit multiply or divide - instructions and your code must be compiled with -mv8 to see any - performance increase. On the other hand, code compiled with -mv8 - will generate an illegal instruction trap when executed on processors - with this option disabled. - - The divider consumes approximately 2 kgates, the multiplier 6 kgates. - -Multiplier latency -CONFIG_IU_MUL_LATENCY_2 - Implementation options for the integer multiplier. - - Type Implementation issue-rate/latency - 2-clocks 32x32 pipelined multiplier 1/2 - 4-clocks 16x16 standard multiplier 4/4 - 5-clocks 16x16 pipelined multiplier 4/5 - -Multiplier latency -CONFIG_IU_MUL_MAC - If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate) - instructions will be enabled. The instructions implement a - single-cycle 16x16->32 bits multiply with a 40-bits accumulator. - The details of these instructions can be found in the LEON manual, - This option is only available when 16x16 multiplier is used. - -Single vector trapping -CONFIG_IU_SVT - Single-vector trapping is a SPARC V8e option to reduce code-size - in small applications. If enabled, the processor will jump to - the address of trap 0 (tt = 0x00) for all traps. No trap table - is then needed. The trap type is present in %psr.tt and must - be decoded by the O/S. Saves 4 Kbyte of code, but increases - trap and interrupt overhead. Currently, the only O/S supporting - this option is eCos. To enable SVT, the O/S must also set bit 13 - in %asr17. - -Load latency -CONFIG_IU_LDELAY - Defines the pipeline load delay (= pipeline cycles before the data - from a load instruction is available for the next instruction). - One cycle gives best performance, but might create a critical path - on targets with slow (data) cache memories. A 2-cycle delay can - improve timing but will reduce performance with about 5%. - -Reset address -CONFIG_IU_RSTADDR - By default, a SPARC processor starts execution at address 0. - With this option, any 4-kbyte aligned reset start address can be - choosen. Keep at 0 unless you really know what you are doing. - -Power-down -CONFIG_PWD - Say Y here to enable the power-down feature of the processor. - Might reduce the maximum frequency slightly on FPGA targets. - For details on the power-down operation, see the LEON3 manual. - -Hardware watchpoints -CONFIG_IU_WATCHPOINTS - The processor can have up to 4 hardware watchpoints, allowing to - create both data and instruction breakpoints at any memory location, - also in PROM. Each watchpoint will use approximately 500 gates. - Use 0 to disable the watchpoint function. - -Floating-point enable -CONFIG_FPU_ENABLE - Say Y here to enable the floating-point interface for the MEIKO - or GRFPU. Note that no FPU's are provided with the GPL version - of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial - cores and must be obtained separately. - -FPU selection -CONFIG_FPU_GRFPU - Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun - Meiko FPU core. All cores are fully IEEE-754 compatible and support - all SPARC FPU instructions. - -GRFPU Multiplier -CONFIG_FPU_GRFPU_INFMUL - On FPGA targets choose inferred multiplier. For ASIC implementations - choose between Synopsys Design Ware (DW) multiplier or Module - Generator (ModGen) multiplier. The DW multiplier gives better results - (smaller area and better timing) but requires a DW license. - The ModGen multiplier is part of GRLIB and does not require a license. - -Shared GRFPU -CONFIG_FPU_GRFPU_SH - If enabled multiple CPU cores will share one GRFPU. - -GRFPC Configuration -CONFIG_FPU_GRFPC0 - Configures the GRFPU-LITE controller. - - In simple configuration controller executes FP instructions - in parallel with integer instructions. FP operands are fetched - in the register file stage and the result is written in the write - stage. This option uses least area resources. - - Data forwarding configuration gives ~ 10 % higher FP performance than - the simple configuration by adding data forwarding between the pipeline - stages. - - Non-blocking controller allows FP load and store instructions to - execute in parallel with FP instructions. The performance increase is - ~ 20 % for FP applications. This option uses most logic resources and - is suitable for ASIC implementations. - -Floating-point netlist -CONFIG_FPU_NETLIST - Say Y here to use a VHDL netlist of the GRFPU-Lite. This is - only available in certain versions of grlib. - -Enable Instruction cache -CONFIG_ICACHE_ENABLE - The instruction cache should always be enabled to allow - maximum performance. Some low-end system might want to - save area and disable the cache, but this will reduce - the performance with a factor of 2 - 3. - -Enable Data cache -CONFIG_DCACHE_ENABLE - The data cache should always be enabled to allow - maximum performance. Some low-end system might want to - save area and disable the cache, but this will reduce - the performance with a factor of 2 at least. - -Instruction cache associativity -CONFIG_ICACHE_ASSO1 - The instruction cache can be implemented as a multi-set cache with - 1 - 4 sets. Higher associativity usually increases the cache hit - rate and thereby the performance. The downside is higher power - consumption and increased gate-count for tag comparators. - - Note that a 1-set cache is effectively a direct-mapped cache. - -Instruction cache set size -CONFIG_ICACHE_SZ1 - The size of each set in the instuction cache (kbytes). Valid values - are 1 - 64 in binary steps. Note that the full range is only supported - by the generic and virtex2 targets. Most target packages are limited - to 2 - 16 kbyte. Large set size gives higher performance but might - affect the maximum frequency (on ASIC targets). The total instruction - cache size is the number of set multiplied with the set size. - -Instruction cache line size -CONFIG_ICACHE_LZ16 - The instruction cache line size. Can be set to either 16 or 32 - bytes per line. Instruction caches typically benefit from larger - line sizes, but on small caches it migh be better with 16 bytes/line - to limit eviction miss rate. - -Instruction cache replacement algorithm -CONFIG_ICACHE_ALGORND - Cache replacement algorithm for caches with 2 - 4 sets. The 'random' - algorithm selects the set to evict randomly. The least-recently-replaced - (LRR) algorithm evicts the set least recently replaced. The least- - recently-used (LRU) algorithm evicts the set least recently accessed. - The random algorithm uses a simple 1- or 2-bit counter to select - the eviction set and has low area overhead. The LRR scheme uses one - extra bit in the tag ram and has therefore also low area overhead. - However, the LRR scheme can only be used with 2-set caches. The LRU - scheme has typically the best performance but also highest area overhead. - A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops - per line, and a 4-set LRU uses 5 flip-flops per line to store the access - history. - -Instruction cache locking -CONFIG_ICACHE_LOCK - Say Y here to enable cache locking in the instruction cache. - Locking can be done on cache-line level, but will increase the - width of the tag ram with one bit. If you don't know what - locking is good for, it is safe to say N. - -Data cache associativity -CONFIG_DCACHE_ASSO1 - The data cache can be implemented as a multi-set cache with - 1 - 4 sets. Higher associativity usually increases the cache hit - rate and thereby the performance. The downside is higher power - consumption and increased gate-count for tag comparators. - - Note that a 1-set cache is effectively a direct-mapped cache. - -Data cache set size -CONFIG_DCACHE_SZ1 - The size of each set in the data cache (kbytes). Valid values are - 1 - 64 in binary steps. Note that the full range is only supported - by the generic and virtex2 targets. Most target packages are limited - to 2 - 16 kbyte. A large cache gives higher performance but the - data cache is timing critical an a too large setting might affect - the maximum frequency (on ASIC targets). The total data cache size - is the number of set multiplied with the set size. - -Data cache line size -CONFIG_DCACHE_LZ16 - The data cache line size. Can be set to either 16 or 32 bytes per - line. A smaller line size gives better associativity and higher - cache hit rate, but requires a larger tag memory. - -Data cache replacement algorithm -CONFIG_DCACHE_ALGORND - See the explanation for instruction cache replacement algorithm. - -Data cache locking -CONFIG_DCACHE_LOCK - Say Y here to enable cache locking in the data cache. - Locking can be done on cache-line level, but will increase the - width of the tag ram with one bit. If you don't know what - locking is good for, it is safe to say N. - -Data cache snooping -CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. - -Separate snoop tags -CONFIG_DCACHE_SNOOP_SEPTAG - Enable a separate memory to store the data tags used for snooping. - This is necessary when snooping support is wanted in systems - with MMU, typically for SMP systems. In this case, the snoop - tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. - -Fixed cacheability map -CONFIG_CACHE_FIXED - If this variable is 0, the cacheable memory regions are defined - by the AHB plug&play information (default). To overriden the - plug&play settings, this variable can be set to indicate which - areas should be cached. The value is treated as a 16-bit hex value - with each bit defining if a 256 Mbyte segment should be cached or not. - The right-most (LSB) bit defines the cacheability of AHB address - 0 - 256 MByte, while the left-most bit (MSB) defines AHB address - 3840 - 4096 MByte. If the bit is set, the corresponding area is - cacheable. A value of 00F3 defines address 0 - 0x20000000 and - 0x40000000 - 0x80000000 as cacheable. - -Local data ram -CONFIG_DCACHE_LRAM - Say Y here to add a local ram to the data cache controller. - Accesses to the ram (load/store) will be performed at 0 waitstates - and store data will never be written back to the AHB bus. - -Size of local data ram -CONFIG_DCACHE_LRAM_SZ1 - Defines the size of the local data ram in Kbytes. Note that most - technology libraries do not support larger rams than 16 Kbyte. - -Start address of local data ram -CONFIG_DCACHE_LRSTART - Defines the 8 MSB bits of start address of the local data ram. - By default set to 8f (start address = 0x8f000000), but any value - (except 0) is possible. Note that the local data ram 'shadows' - a 16 Mbyte block of the address space. - -MMU enable -CONFIG_MMU_ENABLE - Say Y here to enable the Memory Management Unit. - -MMU split icache/dcache table lookaside buffer -CONFIG_MMU_COMBINED - Select "combined" for a combined icache/dcache table lookaside buffer, - "split" for a split icache/dcache table lookaside buffer - -MMU tlb replacement scheme -CONFIG_MMU_REPARRAY - Select "LRU" to use the "least recently used" algorithm for TLB - replacement, or "Increment" for a simple incremental replacement - scheme. - -Combined i/dcache tlb -CONFIG_MMU_I2 - Select the number of entries for the instruction TLB, or the - combined icache/dcache TLB if such is used. - -Split tlb, dcache -CONFIG_MMU_D2 - Select the number of entries for the dcache TLB. - -Fast writebuffer -CONFIG_MMU_FASTWB - Only selectable if split tlb is enabled. In case fast writebuffer is - enabled the tlb hit will be made concurrent to the cache hit. This - leads to higher store performance, but increased power and area. - -MMU pagesize -CONFIG_MMU_PAGE_4K - The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the - cache way size to 4 Kbyte, and total data cache size to 16 Kbyte, - when the MMU is used. To increase the maximum data cache size, - the MMU pages size can be increased to up 32 Kbyte. This will - give a maximum data cache size of 128 Kbyte. - - Note that an MMU page size different than 4 Kbyte will require - a special linux tool-chain if glibc is used. If you don't know - what you are doing, stay with 4 Kbyte ... - -DSU enable -CONFIG_DSU_ENABLE - The debug support unit (DSU) allows non-intrusive debugging and tracing - of both executed instructions and AHB transfers. If you want to enable - the DSU, say Y here and select the configuration below. - -Trace buffer enable -CONFIG_DSU_TRACEBUF - Say Y to enable the trace buffer. The buffer is not necessary for - debugging, only for tracing instructions and data transfers. - -Enable instruction tracing -CONFIG_DSU_ITRACE - If you say Y here, an instruction trace buffer will be implemented - in each processor. The trace buffer will trace executed instructions - and their results, and place them in a circular buffer. The buffer - can be read out by any AHB master, and in particular by the debug - communication link. - -Size of trace buffer -CONFIG_DSU_ITRACESZ1 - Select the buffer size (in kbytes) for the instruction trace buffer. - Each line in the buffer needs 16 bytes. A 128-entry buffer will thus - need 2 kbyte. - -Enable AHB tracing -CONFIG_DSU_ATRACE - If you say Y here, an AHB trace buffer will be implemented in the - debug support unit processor. The AHB buffer will trace all transfers - on the AHB bus and save them in a circular buffer. The trace buffer - can be read out by any AHB master, and in particular by the debug - communication link. - -Size of trace buffer -CONFIG_DSU_ATRACESZ1 - Select the buffer size (in kbytes) for the AHB trace buffer. - Each line in the buffer needs 16 bytes. A 128-entry buffer will thus - need 2 kbyte. - - -LEON3FT enable -CONFIG_LEON3FT_EN - Say Y here to use the fault-tolerant LEON3FT core instead of the - standard non-FT LEON3. - -IU Register file protection -CONFIG_IUFT_NONE - Select the FT implementation in the LEON3FT integer unit - register file. The options include parity, parity with - sparing, 7-bit BCH and TMR. - -FPU Register file protection -CONFIG_FPUFT_EN - Say Y to enable SEU protection of the FPU register file. - The GRFPU will be protected using 8-bit parity without restart, while - the GRFPU-Lite will be protected with 4-bit parity with restart. If - disabled the FPU register file will be implemented using flip-flops. - -Cache memory error injection -CONFIG_RF_ERRINJ - Say Y here to enable error injection in to the IU/FPU regfiles. - Affects only simulation. - -Cache memory protection -CONFIG_CACHE_FT_EN - Enable SEU error-correction in the cache memories. - -Cache memory error injection -CONFIG_CACHE_ERRINJ - Say Y here to enable error injection in to the cache memories. - Affects only simulation. - -Leon3ft netlist -CONFIG_LEON3_NETLIST - Say Y here to use a VHDL netlist of the LEON3FT. This is - only available in certain versions of grlib. - -IU assembly printing -CONFIG_IU_DISAS - Enable printing of executed instructions to the console. - -IU assembly printing in netlist -CONFIG_IU_DISAS_NET - Enable printing of executed instructions to the console also - when simulating a netlist. NOTE: with this option enabled, it - will not be possible to pass place&route. - -32-bit program counters -CONFIG_DEBUG_PC32 - Since the LSB 2 bits of the program counters always are zero, they are - normally not implemented. If you say Y here, the program counters will - be implemented with full 32 bits, making debugging of the VHDL model - much easier. Turn of this option for synthesis or you will be wasting - area. -CONFIG_AHB_DEFMST - Sets the default AHB master (see AMBA 2.0 specification for definition). - Should not be set to a value larger than the number of AHB masters - 1. - For highest processor performance, leave it at 0. - -Default AHB master -CONFIG_AHB_RROBIN - Say Y here to enable round-robin arbitration of the AHB bus. A N will - select fixed priority, with the master with the highest bus index having - the highest priority. - -Support AHB split-transactions -CONFIG_AHB_SPLIT - Say Y here to enable AHB split-transaction support in the AHB arbiter. - Unless you actually have an AHB slave that can generate AHB split - responses, say N and save some gates. - -Default AHB master -CONFIG_AHB_IOADDR - Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined - in the plug&play extentions of the AMBA bus. Should be kept to FFF - unless you really know what you are doing. - -APB bridge address -CONFIG_APB_HADDR - Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be - kept at 800 for software compatibility. - -AHB monitor -CONFIG_AHB_MON - Say Y to enable the AHB bus monitor. The monitor will check for - illegal AHB transactions during simulation. It has no impact on - synthesis. - -Report AHB errors -CONFIG_AHB_MONERR - Print out detected AHB violations on console. - -Report AHB warnings -CONFIG_AHB_MONWAR - Print out detected AHB warnings on console. - - -DSU enable -CONFIG_DSU_UART - Say Y to enable the AHB uart (serial-to-AHB). This is the most - commonly used debug communication link. - -JTAG Enable -CONFIG_DSU_JTAG - Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done - with GRMON through the boards JTAG chain at speed of 300 kbits/s. - Supported JTAG cables are Xilinx Parallel Cable III and IV. - -Ethernet DSU enable -CONFIG_DSU_ETH - Say Y to enable the Ethernet Debug Communication Link (EDCL). The link - provides a DSU gateway between ethernet and the AHB bus. Debugging is - done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must - enable the GRETH Ethernet MAC for this option to become active. - -Size of EDCL trace buffer -CONFIG_DSU_ETHSZ1 - Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is - usually enough, while a larger buffer will increase the transfer rate. - When operating at 100 Mbit, use a buffer size of at least 8 kbyte for - maximum throughput. - -MSB IP address -CONFIG_DSU_IPMSB - Set the MSB 16 bits of the IP address of the EDCL. - -LSB IP address -CONFIG_DSU_IPLSB - Set the LSB 16 bits of the IP address of the EDCL. - -MSB ethernet address -CONFIG_DSU_ETHMSB - Set the MSB 24 bits of the ethernet address of the EDCL. - -LSB ethernet address -CONFIG_DSU_ETHLSB - Set the LSB 24 bits of the ethernet address of the EDCL. - -Programmable MAC/IP address -CONFIG_DSU_ETH_PROG - Say Y to make the LSB 4 bits of the EDCL MAC and IP address - configurable using the ethi.edcladdr inputs. -PROM/SRAM memory controller -CONFIG_SRCTRL - Say Y here to enable a simple (and small) PROM/SRAM memory controller. - The controller has a fixed number of waitstates, and is primarily - intended for FPGA implementations. The RAM data bus is always 32 bits, - the PROM can be configured to either 8 or 32 bits (hardwired). - -8-bit memory support -CONFIG_SRCTRL_8BIT - If you say Y here, the simple PROM/SRAM memory controller will - implement 8-bit PROM mode. - -PROM waitstates -CONFIG_SRCTRL_PROMWS - Select the number of waitstates for PROM access. - -RAM waitstates -CONFIG_SRCTRL_RAMWS - Select the number of waitstates for RAM access. - -IO waitstates -CONFIG_SRCTRL_IOWS - Select the number of waitstates for IO access. - -Read-modify-write support -CONFIG_SRCTRL_RMW - Say Y here to perform byte- and half-word writes as a - read-modify-write sequence. This is necessary if your - SRAM does not have individual byte enables. If you are - unsure, it is safe to say Y. - -SRAM bank select -CONFIG_SRCTRL_SRBANKS - Select number of SRAM banks. - -SRAM bank size select -CONFIG_SRCTRL_BANKSZ - Select size of SRAM banks in kBytes. - -PROM address bit select -CONFIG_SRCTRL_ROMASEL - Select address bit for PROM bank decoding. -Leon2 memory controller -CONFIG_MCTRL_LEON2 - Say Y here to enable the LEON2 memory controller. The controller - can access PROM, I/O, SRAM and SDRAM. The bus width for PROM - and SRAM is programmable to 8-, 16- or 32-bits. - -8-bit memory support -CONFIG_MCTRL_8BIT - If you say Y here, the PROM/SRAM memory controller will support - 8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit. - Say N to save a few hundred gates. - -16-bit memory support -CONFIG_MCTRL_16BIT - If you say Y here, the PROM/SRAM memory controller will support - 16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit. - Say N to save a few hundred gates. - -Write strobe feedback -CONFIG_MCTRL_WFB - If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will - be used to enable the data bus drivers during write cycles. This - will guarantee that the data is still valid on the rising edge of - the write strobe. If you say N, the write strobes and the data bus - drivers will be clocked on the rising edge, potentially creating - a hold time problem in external memory or I/O. However, in all - practical cases, there is enough capacitance in the data bus lines - to keep the value stable for a few (many?) nano-seconds after the - buffers have been disabled, making it safe to say N and remove a - combinational path in the netlist that might be difficult to - analyze. - -Write strobe feedback -CONFIG_MCTRL_5CS - If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will - be enabled. If you don't intend to use it, say N and save some gates. - -SDRAM controller enable -CONFIG_MCTRL_SDRAM - Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't - intend to use SDRAM, say N and save about 1 kgates. - -SDRAM controller inverted clock -CONFIG_MCTRL_SDRAM_INVCLK - If you say Y here, the SDRAM controller output signals will be delayed - with 1/2 clock in respect to the SDRAM clock. This will allow the used - of an SDRAM clock which in not strictly in phase with the internal - clock. This option will limit the SDRAM frequency to 40 - 50 MHz. - - On FPGA targets without SDRAM clock synchronizations through PLL/DLL, - say Y. On ASIC targets, say N and tell your foundry to balance the - SDRAM clock output. - -SDRAM separate address buses -CONFIG_MCTRL_SDRAM_SEPBUS - Say Y here if your SDRAM is connected through separate address - and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000 - board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards. - -64-bit data bus -CONFIG_MCTRL_SDRAM_BUS64 - Say Y here to enable 64-bit SDRAM data bus. - -Page burst enable -CONFIG_MCTRL_PAGE - Say Y here to enable SDRAM page burst operation. This will implement - read operations using page bursts rather than 8-word bursts and save - about 500 gates (100 LUTs). Note that not all SDRAM supports page - burst, so use this option with care. - -Programmable page burst enable -CONFIG_MCTRL_PROGPAGE - Say Y here to enable programmable SDRAM page burst operation. This - will allow to dynamically enable/disable page burst by setting - bit 17 in MCFG2. - -SDRAM controller enable -CONFIG_SDCTRL - Say Y here to enabled a 32/64-bit PC133 SDRAM controller. - -SDRAM controller inverted clock -CONFIG_SDCTRL_INVCLK - If you say Y here, the SDRAM clock will be inverted in respect to the - system clock and the SDRAM signals. This will limit the SDRAM frequency - to 50/66 MHz, but has the benefit that you will not need a PLL to - generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets, - say N and tell your foundry to balance the SDRAM clock output. - -64-bit data bus -CONFIG_SDCTRL_BUS64 - Say Y here to enable 64-bit data bus. - -Page burst enable -CONFIG_SDCTRL_PAGE - Say Y here to enable SDRAM page burst operation. This will implement - read operations using page bursts rather than 8-word bursts and save - about 500 gates (100 LUTs). Note that not all SDRAM supports page - burst, so use this option with care. - -Programmable page burst enable -CONFIG_SDCTRL_PROGPAGE - Say Y here to enable programmable SDRAM page burst operation. This - will allow to dynamically enable/disable page burst by setting - bit 17 in MCFG2. - -On-chip rom -CONFIG_AHBROM_ENABLE - Say Y here to add a block on on-chip rom to the AHB bus. The ram - provides 0-waitstates read access, burst support, and 8-, 16- - and 32-bit data size. The rom will be syntheised into block rams - on Xilinx and Altera FPGA devices, and into gates on ASIC - technologies. GRLIB includes a utility to automatically create - the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB - documentation for details. - -On-chip rom address -CONFIG_AHBROM_START - Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy - a 1 Mbyte slot at the selected address. Default is 000, corresponding - to AHB address 0x00000000. When address 0x0 is selected, the rom area - of any other memory controller is set to 0x10000000 to avoid conflicts. - -Enable pipeline register for on-chip rom -CONFIG_AHBROM_PIPE - Say Y here to add a data pipeline register to the on-chip rom. - This should be done when the rom is implemenented in (ASIC) gates, - or in logic cells on FPGAs. Do not use this option when the rom is - implemented in block rams. If enabled, the rom will operate with - one waitstate. - -On-chip ram -CONFIG_AHBRAM_ENABLE - Say Y here to add a block on on-chip ram to the AHB bus. The ram - provides 0-waitstates read access and 0/1 waitstates write access. - All AHB burst types are supported, as well as 8-, 16- and 32-bit - data size. - -On-chip ram size -CONFIG_AHBRAM_SZ1 - Set the size of the on-chip AHB ram. The ram is infered/instantiated - as four byte-wide ram slices to allow byte and half-word write - accesses. It is therefore essential that the target package can - infer byte-wide rams. This is currently supported on the generic, - virtex, virtex2, proasic and axellerator targets. - -On-chip ram address -CONFIG_AHBRAM_START - Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy - a 1 Mbyte slot at the selected address. Default is A00, corresponding - to AHB address 0xA0000000. - -Gaisler Ethernet MAC enable -CONFIG_GRETH_ENABLE - Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has - one AHB master interface to read and write packets to memory, and one - APB slave interface for accessing the control registers. - -Gaisler Ethernet 1G MAC enable -CONFIG_GRETH_GIGA - Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC . - The 1G MAC is only available in the commercial version of GRLIB, - so do NOT enable it if you are using the GPL version. - -CONFIG_GRETH_FIFO4 - Set the depth of the receive and transmit FIFOs in the MAC core. - The MAC core will perform AHB burst read/writes with half the - size of the FIFO depth. - - -CAN interface enable -CONFIG_CAN_ENABLE - Say Y here to enable the CAN interace from OpenCores. The core has one - AHB slave interface for accessing the control registers. The CAN core - ir register-compatible with the SAJ1000 core from Philips. - -CAN register address -CONFIG_CANIO - The control registers of the CAN core occupy 4 kbyte, and are - mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting - defines at which address in the I/O area the registers appear (HADDR[19:8]). - -CAN interrupt -CONFIG_CANIRQ - Defines which interrupt number the CAN core will generate. - -CAN loob-back testing -CONFIG_CANLOOP - If you say Y here, the receiver and trasmitter of the CAN core will - be connected together in a loop-back fashion. This will make it - possible to perform loop-back test, but not data will be sent - or received from the outside. ONLY for testing! - -CAN Synchronous reset -CONFIG_CAN_SYNCRST - If you say Y here, the CAN core will be implemented with - synchronous reset rather than asynchronous. This is needed - when the target library does not implement registers with - async reset. Unless you know what you are doing, say N. - -CAN FT memories -CONFIG_CAN_FT - If you say Y here, the CAN FIFOs will be implemented using - SEU protected RAM blocks. Only applicable to the FT version - of grlib. -PCI interface type -CONFIG_PCI_SIMPLE_TARGET - The target-only PCI interface provides a simple target interface - without fifos. It is small and robust, and is suitable to be used - for DSU communications via PCI. - -PCI interface type -CONFIG_PCI_MASTER_TARGET - The master-target PCI interface provides a high-performance 32-bit - PCI interface with configurable FIFOs and optional DMA channel. - -PCI interface type -CONFIG_PCI_MASTER_TARGET_DMA - Say Y here to enable a DMA controller in the PCI master-target core. - The DMA controller can perform PCI<->memory data transfers - independently of the processor. - -PCI vendor id -CONFIG_PCI_VENDORID - Sets the PCI vendor ID in the PCI configuration area. - -PCI device id -CONFIG_PCI_DEVICEID - Sets the PCI device ID in the PCI configuration area. - -PCI initiator address -CONFIG_PCI_HADDR - Sets the MSB AHB adress (HADDR[31:20]) of the PCI initiator area. - -PCI FIFO depth -CONFIG_PCI_FIFO8 - The number words in the PCI FIFO buffers in the master-target - core. The master interface uses four 33-bit wide FIFOs, while the - target interface uses two. - - -PCI arbiter enable -CONFIG_PCI_ARBITER - To enable a PCI arbiter, say Y here. - -PCI APB interface enable -CONFIG_PCI_ARBITER_APB - Say Y here to enable the APB interface on the PCI arbiter. This makes - it possible to dynamically re-assign PCI master priorities. See the - PCI arbiter manual for details. - -PCI arbiter request signals -CONFIG_PCI_ARBITER_NREQ - The number of PCI bus request/grant pairs. Should be not - be more than 8. Note that the processor needs one, so the - minimum should be 2. - -PCI trace buffer -CONFIG_PCI_TRACE - The PCI trace buffer implements a simple on-chip logic analyzer - to trace the PCI signals. The PCI AD bus and most control signals - are stored in a circular buffer, and can be read out by the DSU - or any other AHB master. See the manual for detailed operation. - Only available for target technologies with dual-port rams. - -PCI trace buffer depth -CONFIG_PCI_TRACE256 - Select the number of entries in the PCI trace buffer. Each entry - will use 6 bytes of on-chip (block) ram. - - -Spacewire link -CONFIG_SPW_ENABLE - Say Y here to enable one or more Spacewire serial links. The links - are based on the GRSPW core from Gaisler Research. - -Number of spacewire links -CONFIG_SPW_NUM - Select the number of links to implement. Each link will be a - separate AHB master and APB slave for configuration. - -AHB FIFO depth -CONFIG_SPW_AHBFIFO4 - Select the AHB FIFO depth (in 32-bit words). - -RX FIFO depth -CONFIG_SPW_RXFIFO16 - Select the receiver FIFO depth (in bytes). - -RMAP protocol -CONFIG_SPW_RMAP - Enable hardware target support for the RMAP protocol ( - draft C for GRSPW1 and ECSS-E-ST-50-11C Draft V1.3 - for GRSPW2). - -RMAP Buffer depth -CONFIG_SPW_RMAPBUF2 - Select the size of the RMAP buffer (in bytes). - -RMAP CRC -CONFIG_SPW_RMAPCRC - Enable hardware calculation of the RMAP CRC checksum. RMAP CRC - is always enabled when the RMAP hardware target is enabled so this - parameter will have no effect in that case. - -Rx unaligned -CONFIG_SPW_RXUNAL - Enable support for byte writes used for non word-aligned - receiver buffer addresses. Without this enabled data will - still be written at the correct location but complete words - will always be written so data outside the intended boundaries - might be overwritten. - -Netlists -CONFIG_SPW_NETLIST - Use the netlist version of GRSPWC. This option is required if - you have not licensed the source code of the Spacewire core. - Currently only supported for Virtex and Axcelerator FPGAs. - The AHB/RX FIFO sizes should be set to 16 word/byte, and the - RMAP should be disabled. - -Spacewire FT -CONFIG_SPW_FT - Say Y here to implement the Spacewire block rams with fault-tolerance - against SEU errors. - -Spacewire core -CONFIG_SPW_GRSPW1 - Select to use GRSPW1 core or GRSPW2 core. - -DMA channels -CONFIG_SPW_DMACHAN - Set the number of DMA channels for the GRSPW2 core - -Ports -CONFIG_SPW_PORTS - Set the number of SpaceWire ports for the GRSPW2 core - -Same clock for SpaceWire receiver and transmitter -CONFIG_SPW_RTSAME - Say Y here if the same clock is connected to both the receiver - and transmitter in the GRSPW2 core. This will remove two - asynchronous resets and some synchronization logic. This is only - applicable for the SDR and DDR inputs modes. - - -Receiver clock type -CONFIG_SPW_RX_SDR - Selects the input clocking scheme for the GRSPW2. SDR means that the - core samples data and strobe using single data rate registers at the - receiver clock frequency. DDR is the same except DDR registers are used. - Xor selects the traditional self clocking scheme using a xor gate. - Aeroflex sets the receiver in a mode compatible with the Aeroflex - SpaceWire transceiver. - -Receiver clock type -CONFIG_SPW_TX_SDR - Selects the output clocking scheme for the GRSPW2. SDR means that the - core transmits data and strobe using single data rate registers at the - transmitter clock frequency. DDR is the same except DDR registers are used. - Aeroflex sets the transmitter in a mode compatible with the Aeroflex - SpaceWire transceiver. -UART1 enable -CONFIG_UART1_ENABLE - Say Y here to enable UART1, or the console UART. This is needed to - get any print-out from LEON3 systems regardless of operating system. - -UART1 FIFO -CONFIG_UA1_FIFO1 - The UART has configurable transmitt and receive FIFO's, which can - be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for - maximum throughput. - - -UART2 enable -CONFIG_UART2_ENABLE - Say Y here to enable UART2, or the secondary UART. This UART can be - used to connect a second console (uClinux) or to control external - equipment. - -UART2 FIFO -CONFIG_UA2_FIFO1 - The UART has configurable transmitt and receive FIFO's, which can - be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for - maximum throughput. - -LEON3 interrupt controller -CONFIG_IRQ3_ENABLE - Say Y here to enable the LEON3 interrupt controller. This is needed - if you want to be able to receive interrupts. Operating systems like - Linux, RTEMS and eCos needs this option to be enabled. If you intend - to use the Bare-C run-time and not use interrupts, you could disable - the interrupt controller and save about 500 gates. - -LEON3 interrupt controller broadcast -CONFIG_IRQ3_BROADCAST_ENABLE - If enabled the broadcast register is used to determine which - interrupt should be sent to all cpus instead of just the first - one that consumes it. - -Secondary interrupts -CONFIG_IRQ3_SEC - The interrupt controller handles 15 interrupts by default (1 - 15). - These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F), - and AMBA interrupts 1 - 15. This option will enable 16 additional - (secondary) interrupts, corresponding to AMBA interrupts 16 - 31. - The secondary interrupts will be multiplexed onto one of the first - 15 interrupts. The total number of handled interrupts can then - be up to 30 (14 primary and 16 secondary). - -Number of interrupts -CONFIG_IRQ3_NSEC - Defines which of the first 15 interrupts should be used for the - secondary (16 - 31) interrupts. Interrupt 15 should be avoided - since it is not maskable by the processor. -Timer module enable -CONFIG_GPT_ENABLE - Say Y here to enable the Modular Timer Unit. The timer unit consists - of one common scaler and up to 7 independent timers. The timer unit - is needed for Linux, RTEMS, eCos and the Bare-C run-times. - -Timer module enable -CONFIG_GPT_NTIM - Set the number of timers in the timer unit (1 - 7). - -Scaler width -CONFIG_GPT_SW - Set the width if the common pre-scaler (2 - 16 bits). The scaler - is used to divide the system clock down to 1 MHz, so 8 bits should - be sufficient for most implementations (allows clocks up to 256 MHz). - -Timer width -CONFIG_GPT_TW - Set the width if the timers (2 - 32 bits). 32 bits is recommended - for the Bare-C run-time, lower values (e.g. 16 bits) can work with - RTEMS and Linux. - -Timer Interrupt -CONFIG_GPT_IRQ - Set the interrupt number for the first timer. Remaining timers will - have incrementing interrupts, unless the separate-interrupts option - below is disabled. - -Watchdog enable -CONFIG_GPT_WDOGEN - Say Y here to enable the watchdog functionality in the timer unit. - -Watchdog time-out value -CONFIG_GPT_WDOG - This value will be loaded in the watchdog timer at reset. - -GPIO port -CONFIG_GRGPIO_ENABLE - Say Y here to enable a general purpose I/O port. The port can be - configured from 1 - 32 bits, whith each port signal individually - programmable as input or output. The port signals can also serve - as interrupt inputs. - -GPIO port witdth -CONFIG_GRGPIO_WIDTH - Number of bits in the I/O port. Must be in the range of 1 - 32. - -GPIO interrupt mask -CONFIG_GRGPIO_IMASK - The I/O port interrupt mask defines which bits in the I/O port - should be able to create an interrupt. - -UART debugging -CONFIG_DEBUG_UART - During simulation, the output from the UARTs is printed on the - simulator console. Since the ratio between the system clock and - UART baud-rate is quite high, simulating UART output will be very - slow. If you say Y here, the UARTs will print a character as soon - as it is stored in the transmitter data register. The transmitter - ready flag will be permanently set, speeding up simulation. However, - the output on the UART tx line will be garbled. Has not impact on - synthesis, but will cause the LEON test bench to fail. - -FPU register tracing -CONFIG_DEBUG_FPURF - If you say Y here, all writes to the floating-point unit register file - will be printed on the simulator console. - diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.in b/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.in deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.in +++ /dev/null @@ -1,89 +0,0 @@ -# -# LEON3 configuration written in linux configuration language -# -# Written by Jiri Gaisler, Gaisler Research -# -# Comments and bug reports to jiri@gaisler.com -# -# - -#define_bool CONFIG_MCTRL_RMW y - -mainmenu_name "LEON3MP Design Configuration" - -mainmenu_option next_comment - comment 'Synthesis ' - source lib/techmap/gencomp/tech.in -endmenu - -mainmenu_option next_comment - comment 'Clock generation' - source lib/techmap/clocks/clkgen.in -endmenu - -source lib/gaisler/leon3/leon3.in -source lib/grlib/amba/amba.in - -mainmenu_option next_comment - comment 'Debug Link ' - source lib/gaisler/uart/dcom.in - source lib/gaisler/jtag/jtag.in - source lib/gaisler/net/edcl.in -endmenu - -mainmenu_option next_comment -comment 'Peripherals ' - - mainmenu_option next_comment - comment 'Memory controllers ' - source lib/gaisler/memctrl/srctrl.in - source lib/esa/memoryctrl/mctrl.in - source lib/gaisler/memctrl/sdctrl.in - endmenu - - mainmenu_option next_comment - comment 'On-chip RAM/ROM ' - source lib/gaisler/misc/ahbrom.in - source lib/gaisler/misc/ahbram.in - endmenu - - mainmenu_option next_comment - comment 'Ethernet ' - source lib/gaisler/greth/greth.in - endmenu - - mainmenu_option next_comment - comment 'CAN ' - source lib/gaisler/can/can_oc.in - endmenu - - mainmenu_option next_comment - comment 'PCI ' - source lib/gaisler/pci/pci_target.in - source lib/gaisler/pci/pci_mtf.in - source lib/gaisler/pci/pcidma.in - source lib/gaisler/pci/pci.in - source lib/esa/pci/pci_arb.in - source lib/gaisler/pci/pcitrace.in - endmenu - - mainmenu_option next_comment - comment 'Spacewire ' - source lib/gaisler/spacewire/spacewire.in - endmenu - - mainmenu_option next_comment - comment 'UARTs, timers and irq control ' - source lib/gaisler/uart/uart1.in - source lib/gaisler/uart/uart2.in - source lib/gaisler/leon3/irqmp.in - source lib/gaisler/misc/gptimer.in - source lib/gaisler/misc/grgpio.in - endmenu - -endmenu - -mainmenu_option next_comment -comment 'VHDL Debugging ' - source lib/grlib/util/debug.in -endmenu diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd b/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd +++ /dev/null @@ -1,180 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3; - constant CFG_MEMTECH : integer := apa3; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (5); - constant CFG_CLKDIV : integer := (10); - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - constant CFG_NWIN : integer := (7); - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 0 + 16*0; - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (2); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd.h b/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd.h deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd.h +++ /dev/null @@ -1,208 +0,0 @@ --- Technology and synthesis options - constant CFG_FABTECH : integer := CONFIG_SYN_TECH; - constant CFG_MEMTECH : integer := CFG_RAM_TECH; - constant CFG_PADTECH : integer := CFG_PAD_TECH; - constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; - constant CFG_SCAN : integer := CONFIG_SYN_SCAN; - --- Clock generator - constant CFG_CLKTECH : integer := CFG_CLK_TECH; - constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; - constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; - constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; - constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; - constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; - constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; - --- LEON3 processor core - constant CFG_LEON3 : integer := CONFIG_LEON3; - constant CFG_NCPU : integer := CONFIG_PROC_NUM; - constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; - constant CFG_V8 : integer := CFG_IU_V8; - constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; - constant CFG_SVT : integer := CONFIG_IU_SVT; - constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; - constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; - constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; - constant CFG_PWD : integer := CONFIG_PWD*2; - constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST; - constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; - constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; - constant CFG_ISETS : integer := CFG_IU_ISETS; - constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; - constant CFG_ILINE : integer := CFG_ILINE_SZ; - constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; - constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; - constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; - constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; - constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; - constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; - constant CFG_DSETS : integer := CFG_IU_DSETS; - constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; - constant CFG_DLINE : integer := CFG_DLINE_SZ; - constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; - constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; - constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; - constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; - constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; - constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; - constant CFG_MMUEN : integer := CONFIG_MMUEN; - constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; - constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; - constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; - constant CFG_TLB_REP : integer := CONFIG_TLB_REP; - constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; - constant CFG_DSU : integer := CONFIG_DSU_ENABLE; - constant CFG_ITBSZ : integer := CFG_DSU_ITB; - constant CFG_ATBSZ : integer := CFG_DSU_ATB; - constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; - constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; - constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; - constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; - constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; - constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; - constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; - constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; - constant CFG_PCLOW : integer := CFG_DEBUG_PC32; - --- AMBA settings - constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; - constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; - constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; - constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; - constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; - constant CFG_AHB_MON : integer := CONFIG_AHB_MON; - constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; - constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; - --- DSU UART - constant CFG_AHB_UART : integer := CONFIG_DSU_UART; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG; - constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; - constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; - constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; - constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; - constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; - --- PROM/SRAM controller - constant CFG_SRCTRL : integer := CONFIG_SRCTRL; - constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS; - constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS; - constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS; - constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW; - constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT; - - constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS; - constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ; - constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL; --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; - constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; - constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; - constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; - constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; - constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; - constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; - constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; - constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; - --- SDRAM controller - constant CFG_SDCTRL : integer := CONFIG_SDCTRL; - constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK; - constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64; - constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE; - --- AHB ROM - constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; - constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; - constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; - constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; - constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; - constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; - constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; - constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; - constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; - --- CAN 2.0 interface - constant CFG_CAN : integer := CONFIG_CAN_ENABLE; - constant CFG_CANIO : integer := 16#CONFIG_CANIO#; - constant CFG_CANIRQ : integer := CONFIG_CANIRQ; - constant CFG_CANLOOP : integer := CONFIG_CANLOOP; - constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST; - constant CFG_CANFT : integer := CONFIG_CAN_FT; - --- PCI interface - constant CFG_PCI : integer := CFG_PCITYPE; - constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#; - constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#; - constant CFG_PCIDEPTH : integer := CFG_PCIFIFO; - constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO; - --- PCI arbiter - constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER; - constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB; - constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ; - --- PCI trace buffer - constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE; - constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF; - --- Spacewire interface - constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE; - constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM; - constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO; - constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO; - constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP; - constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF; - constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC; - constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST; - constant CFG_SPW_FT : integer := CONFIG_SPW_FT; - constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW; - constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL; - constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN; - constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS; - constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT; - constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT; - constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME; --- UART 1 - constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; - constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; - --- UART 2 - constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE; - constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; - constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; - --- Modular timer - constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; - constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; - constant CFG_GPT_SW : integer := CONFIG_GPT_SW; - constant CFG_GPT_TW : integer := CONFIG_GPT_TW; - constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; - constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; - constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; - constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; - constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; - constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; - --- GRLIB debugging - constant CFG_DUART : integer := CONFIG_DEBUG_UART; - diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd.in b/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd.in deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/config.vhd.in +++ /dev/null @@ -1,16 +0,0 @@ -#include "config.h" -#include "tkconfig.h" ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - -#include "config.vhd.h" - -end; diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/defconfig b/designs/ProjetBlanc-LeonLPP-A3PE3kL/defconfig deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/defconfig +++ /dev/null @@ -1,209 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -CONFIG_SYN_INFERRED=y -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -# CONFIG_SYN_PROASIC3 is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -CONFIG_MEM_INFERRED=y -# CONFIG_MEM_RHUMC is not set -# CONFIG_MEM_IHP25 is not set -# CONFIG_MEM_VIRAGE is not set - -# -# Clock generation -# -CONFIG_CLK_INFERRED=y -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -# CONFIG_PCI_SYSCLK is not set -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=2 -CONFIG_PWD=y -CONFIG_IU_RSTADDR=00000 -# CONFIG_IU_NOHALT is not set - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -# CONFIG_ICACHE_ASSO1 is not set -CONFIG_ICACHE_ASSO2=y -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -CONFIG_ICACHE_SZ2=y -# CONFIG_ICACHE_SZ4 is not set -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -# CONFIG_ICACHE_ALGORND is not set -CONFIG_ICACHE_ALGOLRR=y -# CONFIG_ICACHE_ALGOLRU is not set -# CONFIG_ICACHE_LOCK is not set -# CONFIG_ICACHE_LRAM is not set -CONFIG_DCACHE_ENABLE=y -# CONFIG_DCACHE_ASSO1 is not set -CONFIG_DCACHE_ASSO2=y -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -CONFIG_DCACHE_SZ2=y -# CONFIG_DCACHE_SZ4 is not set -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_ALGORND is not set -CONFIG_DCACHE_ALGOLRR=y -# CONFIG_DCACHE_ALGOLRU is not set -# CONFIG_DCACHE_LOCK is not set -# CONFIG_DCACHE_LRAM is not set - -# -# MMU -# -# CONFIG_MMU_ENABLE is not set - -# -# Debug Support Unit -# -CONFIG_DSU_ENABLE=y -CONFIG_DSU_ITRACE=y -CONFIG_DSU_ITRACESZ1=y -# CONFIG_DSU_ITRACESZ2 is not set -# CONFIG_DSU_ITRACESZ4 is not set -# CONFIG_DSU_ITRACESZ8 is not set -# CONFIG_DSU_ITRACESZ16 is not set -CONFIG_DSU_ATRACE=y -CONFIG_DSU_ATRACESZ1=y -# CONFIG_DSU_ATRACESZ2 is not set -# CONFIG_DSU_ATRACESZ4 is not set -# CONFIG_DSU_ATRACESZ8 is not set -# CONFIG_DSU_ATRACESZ16 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_ETH is not set - -# -# Peripherals -# - -# -# Memory controllers -# -CONFIG_MCTRL_SMALL=y -# CONFIG_MCTRL_SMALL_8BIT is not set -CONFIG_MCTRL_PROMWS=3 -CONFIG_MCTRL_RAMWS=0 -CONFIG_MCTRL_RMW=y -# CONFIG_MCTRL_SDRAM is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_ETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER_APB is not set -# CONFIG_PCI_TRACE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -CONFIG_UART2_ENABLE=y -# CONFIG_UA2_FIFO1 is not set -# CONFIG_UA2_FIFO2 is not set -CONFIG_UA2_FIFO4=y -# CONFIG_UA2_FIFO8 is not set -# CONFIG_UA2_FIFO16 is not set -# CONFIG_UA2_FIFO32 is not set -CONFIG_IRQ3_ENABLE=y -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y - -# -# VHDL Debugging -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_UART is not set -# CONFIG_DEBUG_PC32 is not set diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/hello.c b/designs/ProjetBlanc-LeonLPP-A3PE3kL/hello.c deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/hello.c +++ /dev/null @@ -1,6 +0,0 @@ - -main() -{ - printf("\n\n Hello LEON3 World!!!\n"); - printf("\n Simulation will now be halted through error mode...\n\n"); -} diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/indata b/designs/ProjetBlanc-LeonLPP-A3PE3kL/indata deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/indata +++ /dev/null @@ -1,2370 +0,0 @@ -NYTT1 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -0101 -1101 -0000 -0000 -0000 -0000 -1010 -0111 -0000 -0000 -0000 -0000 -0000 -0000 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1111 -1000 -0000 -0000 -0000 -0101 -1000 -0000 -0000 -0011 -0000 -1110 -1110 -0000 -0000 -0000 -0000 -0000 -0000 -0000 -0000 -0000 -0100 -0001 -0001 -0000 -0000 -0000 -0000 -0000 -1100 -1000 -1010 -0000 -0000 -1000 -0001 -0000 -1100 -1000 -1010 -0000 -0000 -0010 -0011 -0000 -0000 -0000 -0000 -0111 -0010 -0000 -0001 -0011 -0000 -1010 -1101 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xconfig'. -# -# CHANGES -# ======= -# -# 8 January 1999, Michael Elizabeth Chastain, -# - Remove unused do_cmd function (part of the 2.0 sound support). -# - Arrange buttons in three columns for better screen fitting. -# - Add CONSTANT_Y, CONSTANT_M, CONSTANT_N for commands like: -# dep_tristate 'foo' CONFIG_FOO m -# -# 23 January 1999, Michael Elizabeth Chastain, -# - Shut vfix the hell up. -# -# 24 January 1999, Michael Elizabeth Chastain, -# - Improve the exit message (Jeff Ronne). - -# -# This is a handy replacement for ".widget cget" that requires neither tk4 -# nor additional source code uglification. -# -proc cget { w option } { - return "[lindex [$w configure $option] 4]" -} - -# -# Function to compensate for broken config.in scripts like the sound driver, -# which make dependencies on variables that are never even conditionally -# defined. -# -proc vfix { var } { - global $var - if [ catch {eval concat $$var} ] { - set $var 4 - } -} - -# -# Constant values used by certain dep_tristate commands. -# -set CONSTANT_Y 1 -set CONSTANT_M 2 -set CONSTANT_N 0 -set CONSTANT_E 4 - -# -# Create a "reference" object to steal colors from. -# -button .ref - -# -# On monochrome displays, -disabledforeground is blank by default; that's -# bad. Fill it with -foreground instead. -# -if { [cget .ref -disabledforeground] == "" } { - .ref configure -disabledforeground [cget .ref -foreground] -} - - -# -# Define some macros we will need to parse the config.in file. -# - -proc mainmenu_name { text } { - wm title . "$text" -} - -proc menu_option { w menu_num text } { - global menus_per_column - global processed_top_level - set processed_top_level [expr $processed_top_level + 1] - if { $processed_top_level <= $menus_per_column } then { - set myframe left - } elseif { $processed_top_level <= [expr 2 * $menus_per_column] } then { - set myframe middle - } else { - set myframe right - } - button .f0.x$menu_num -anchor w -text "$text" \ - -command "$w .$w \"$text\"" - pack .f0.x$menu_num -pady 0 -side top -fill x -in .f0.$myframe -} - -proc load_configfile { w title func } { - catch {destroy $w} - toplevel $w -class Dialog - global loadfile - frame $w.x - label $w.bm -bitmap questhead - pack $w.bm -pady 10 -side top -padx 10 - label $w.x.l -text "Enter filename:" -relief raised - entry $w.x.x -width 35 -relief sunken -borderwidth 2 \ - -textvariable loadfile - pack $w.x.l $w.x.x -anchor w -side left - pack $w.x -side top -pady 10 - wm title $w "$title" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" -width 20 \ - -command "destroy $w; focus $oldFocus;$func .fileio" - button $w.f.canc -text "Cancel" \ - -width 20 -command "destroy $w; focus $oldFocus" - pack $w.f.back $w.f.canc -side left -pady 10 -padx 45 - pack $w.f -pady 10 -side bottom -padx 10 -anchor w - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy -} - -bind all {maybe_exit .maybe} - -proc maybe_exit { w } { - catch {destroy $w} - toplevel $w -class Dialog - label $w.bm -bitmap questhead - pack $w.bm -pady 10 -side top -padx 10 - message $w.m -width 400 -aspect 300 \ - -text "Changes will be lost. Are you sure?" -relief flat - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Are you sure?" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" -width 20 \ - -command "exit 1" - button $w.f.canc -text "Cancel" \ - -width 20 -command "destroy $w; focus $oldFocus" - pack $w.f.back $w.f.canc -side left -pady 10 -padx 45 - pack $w.f -pady 10 -side bottom -padx 10 -anchor w - bind $w "exit 1" - bind $w "destroy $w; focus $oldFocus" - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy -} - -proc read_config_file { w } { - global loadfile - if { [string length $loadfile] != 0 && [file readable $loadfile] == 1 } then { - read_config $loadfile - } else { - catch {destroy $w} - toplevel $w -class Dialog - message $w.m -width 400 -aspect 300 -text \ - "Unable to read file $loadfile" \ - -relief raised - label $w.bm -bitmap error - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "Xconfig Internal Error" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "Bummer" \ - -width 10 -command "destroy $w; focus $oldFocus" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - } -} - -proc write_config_file { w } { - global loadfile - if { [string length $loadfile] != 0 - && ([file writable $loadfile] == 1 || ([file exists $loadfile] == 0 && [file writable [file dirname $loadfile]] == 1)) } then { - writeconfig $loadfile .null - } else { - catch {destroy $w} - toplevel $w -class Dialog - message $w.m -width 400 -aspect 300 -text \ - "Unable to write file $loadfile" \ - -relief raised - label $w.bm -bitmap error - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "Xconfig Internal Error" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" \ - -width 10 -command "destroy $w; focus $oldFocus" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - } -} - -proc read_config { filename } { - set file1 [open $filename r] - clear_choices - while { [gets $file1 line] >= 0} { - if [regexp {([0-9A-Za-z_]+)=([ynm])} $line foo var value] { - if { $value == "y" } then { set cmd "global $var; set $var 1" } - if { $value == "n" } then { set cmd "global $var; set $var 0" } - if { $value == "m" } then { set cmd "global $var; set $var 2" } - eval $cmd - } - if [regexp {# ([0-9A-Za-z_]+) is not set} $line foo var] { - set cmd "global $var; set $var 0" - eval $cmd - } - if [regexp {([0-9A-Za-z_]+)=([0-9A-Fa-f]+)} $line foo var value] { - set cmd "global $var; set $var $value" - eval $cmd - } - if [regexp {([0-9A-Za-z_]+)="([^"]*)"} $line foo var value] { - set cmd "global $var; set $var \"$value\"" - eval $cmd - } - } - close $file1 - update_choices - update_mainmenu -} -proc write_comment { file1 file2 text } { - puts $file1 "" - puts $file1 "#" - puts $file1 "# $text" - puts $file1 "#" - puts $file2 "/*" - puts $file2 " * $text" - puts $file2 " */" -} - -proc effective_dep { deplist } { - global CONFIG_MODULES - set depend 1 - foreach i $deplist { - if {$i == 0} then {set depend 0} - if {$i == 2 && $depend == 1} then {set depend 2} - } - if {$depend == 2 && $CONFIG_MODULES == 0} then {set depend 0} - return $depend -} - -proc sync_tristate { var dep } { - global CONFIG_MODULES - if {$dep == 0 && ($var == 1 || $var == 2)} then { - set var 0 - } elseif {$dep == 2 && $var == 1} then { - set var 2 - } elseif {$var == 2 && $CONFIG_MODULES == 0} then { - if {$dep == 1} then {set var 1} else {set var 0} - } - return $var -} - -proc sync_bool { var dep modset } { - set var [sync_tristate $var $dep] - if {$dep == 2 && $var == 2} then { - set var $modset - } - return $var -} - -proc write_tristate { file1 file2 varname variable deplist modset } { - set variable [sync_tristate $variable [effective_dep $deplist]] - if { $variable == 2 } \ - then { set variable $modset } - if { $variable == 1 } \ - then { puts $file1 "$varname=y"; \ - puts $file2 "#define $varname 1" } \ - elseif { $variable == 2 } \ - then { puts $file1 "$varname=m"; \ - puts $file2 "#undef $varname"; \ - puts $file2 "#define ${varname}_MODULE 1" } \ - elseif { $variable == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { \ - puts stdout "ERROR - Attempting to write value for unconfigured variable ($varname)." \ - } -} - -proc write_int { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=$variable"; \ - puts $file2 "#define $varname ($variable)"; \ - } -} - -proc write_hex { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=$variable"; \ - puts -nonewline $file2 "#define $varname "; \ - puts $file2 [exec echo $variable | sed s/^0\[xX\]//]; \ - } -} - -proc write_string { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=\"$variable\""; \ - puts $file2 "#define $varname \"$variable\""; \ - } -} - -proc option_name {w mnum line text helpidx} { - button $w.x$line.l -text "$text" -relief groove -anchor w - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] - button $w.x$line.help -text "Help" -relief raised \ - -command "dohelp .dohelp $helpidx .menu$mnum" - pack $w.x$line.help -side right -fill y - pack $w.x$line.l -side right -fill both -expand on -} - -proc toggle_switch2 {w mnum line text variable} { - frame $w.x$line -relief sunken - radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \ - -relief groove -width 2 -command "update_active" -# radiobutton $w.x$line.m -text "-" -variable $variable -value 2 \ -# -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \ - -relief groove -width 2 -command "update_active" - - option_name $w $mnum $line $text $variable - - pack $w.x$line.n $w.x$line.y -side right -fill y -} - -proc toggle_switch3 {w mnum line text variable} { - frame $w.x$line -relief sunken - radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \ - -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.m -text "m" -variable $variable -value 2 \ - -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \ - -relief groove -width 2 -command "update_active" - - option_name $w $mnum $line $text $variable - - global CONFIG_MODULES - if {($CONFIG_MODULES == 0)} then { - $w.x$line.m configure -state disabled - } - pack $w.x$line.n $w.x$line.m $w.x$line.y -side right -fill y -} - -proc bool {w mnum line text variable} { - toggle_switch2 $w $mnum $line $text $variable -# $w.x$line.m configure -state disabled - pack $w.x$line -anchor w -fill both -expand on -} - -proc tristate {w mnum line text variable } { - toggle_switch3 $w $mnum $line $text $variable - pack $w.x$line -anchor w -fill both -expand on -} - -proc dep_tristate {w mnum line text variable } { - tristate $w $mnum $line $text $variable -} - -proc dep_bool {w mnum line text variable } { - bool $w $mnum $line $text $variable -} - -proc int { w mnum line text variable } { - frame $w.x$line - entry $w.x$line.x -width 11 -relief sunken -borderwidth 2 \ - -textvariable $variable - option_name $w $mnum $line $text $variable - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc hex { w mnum line text variable } { - int $w $mnum $line $text $variable -} - -proc istring { w mnum line text variable } { - frame $w.x$line - entry $w.x$line.x -width 18 -relief sunken -borderwidth 2 \ - -textvariable $variable - option_name $w $mnum $line $text $variable - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc minimenu { w mnum line text variable helpidx } { - frame $w.x$line - menubutton $w.x$line.x -textvariable $variable -menu \ - $w.x$line.x.menu -relief raised \ - -anchor w - option_name $w $mnum $line $text $helpidx - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc menusplit {w m n} { - if { $n > 2 } then { - update idletasks - set menuoptsize [expr [$m yposition 2] - [$m yposition 1]] - set maxsize [winfo screenheight $w] - set splitpoint [expr $maxsize * 4 / 5 / $menuoptsize - 1] - for {set i [expr $splitpoint + 1]} {$i <= $n} {incr i $splitpoint} { - $m entryconfigure $i -columnbreak 1 - } - } -} - -proc menutitle {text menu w} { - wm title $w "$text" -} - -proc submenu { w mnum line text subnum } { - frame $w.x$line - button $w.x$line.l -text "" -width 9 -relief groove - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] -state disabled - button $w.x$line.m -text "$text" -relief raised -anchor w \ - -command "catch {destroy .menu$subnum}; menu$subnum .menu$subnum \"$text\"" - pack $w.x$line.l -side left -fill both - pack $w.x$line.m -anchor w -side right -fill both -expand on - pack $w.x$line -anchor w -fill both -expand on -} - -proc comment {w mnum line text } { - frame $w.x$line - button $w.x$line.l -text "" -width 15 -relief groove - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] -state disabled - button $w.x$line.m -text "$text" -relief groove -anchor w - $w.x$line.m configure -activefore [cget $w.x$line.m -fg] \ - -activeback [cget $w.x$line.m -bg] - pack $w.x$line.l -side left -fill both - pack $w.x$line.m -anchor w -side right -fill both -expand on - pack $w.x$line -anchor w -fill both -expand on -} - -proc readhelp {tag fn} { - set message "" - set b 0 - if { [file readable $fn] == 1} then { - set fhandle [open $fn r] - while {[gets $fhandle inline] >= 0} { - if { $b == 0 } { - if { [regexp $tag $inline ] } { - set b 1 - set message "$inline:\n" - } - } else { - if { [regexp {^[^ \t]} $inline]} { - break - } - set message "$message\n$inline" - } - } - close $fhandle - } - return $message -} - -proc dohelp {w var parent} { - catch {destroy $w} - toplevel $w -class Dialog - - set filefound 0 - set found 0 - set lineno 0 - - if { [file readable config.help] == 1} then { - set filefound 1 - # First escape sed regexp special characters in var: - set var [exec echo "$var" | sed s/\[\]\[\/.^$*\]/\\\\&/g] - # Now pick out right help text: - set message [readhelp $var config.help] - set found [expr [string length "$message"] > 0] - } - - frame $w.f1 - pack $w.f1 -fill both -expand on - - # Do the OK button - # - set oldFocus [focus] - frame $w.f2 - button $w.f2.ok -text "OK" \ - -width 10 -command "destroy $w; catch {focus $oldFocus}" - pack $w.f2.ok -side bottom -pady 6 -anchor n - pack $w.f2 -side bottom -padx 10 -anchor s - - scrollbar $w.f1.vscroll -command "$w.f1.canvas yview" - pack $w.f1.vscroll -side right -fill y - - canvas $w.f1.canvas -relief flat -borderwidth 0 \ - -yscrollcommand "$w.f1.vscroll set" - frame $w.f1.f - pack $w.f1.canvas -side right -fill y -expand on - - if { $found == 0 } then { - if { $filefound == 0 } then { - message $w.f1.f.m -width 750 -aspect 300 -relief flat -text \ - "No help available - unable to open file config.help." - } else { - message $w.f1.f.m -width 400 -aspect 300 -relief flat -text \ - "No help available for $var" - } - label $w.f1.bm -bitmap error - wm title $w "RTFM" - } else { - text $w.f1.f.m -width 73 -relief flat -wrap word - $w.f1.f.m insert 0.0 $message - $w.f1.f.m conf -state disabled -height [$w.f1.f.m index end] - - label $w.f1.bm -bitmap info - wm title $w "Configuration help" - } - pack $w.f1.f.m -side left - pack $w.f1.bm $w.f1.f -side left -padx 10 - - focus $w - set winx [expr [winfo x $parent]+20] - set winy [expr [winfo y $parent]+20] - wm geometry $w +$winx+$winy - set sizok [expr [winfo reqheight $w.f2.ok] + 12] - set maxy [expr [winfo screenheight .] * 3 / 4] - set canvtotal [winfo reqheight $w.f1.f.m] - if [expr $sizok + $canvtotal < $maxy] { - set sizy $canvtotal - } else { - set sizy [expr $maxy - $sizok] - } - $w.f1.canvas configure -height $sizy -width [winfo reqwidth $w.f1.f.m] \ - -scrollregion "0 0 [winfo reqwidth $w.f1.f.m] \ - [winfo reqheight $w.f1.f.m]" - $w.f1.canvas create window 0 0 -anchor nw -window $w.f1.f - update idletasks - - set maxy [winfo screenheight .] - if [expr $sizok + $canvtotal < $maxy] { - set sizy [expr $sizok + $canvtotal] - } else { - set sizy $maxy - } - wm maxsize $w [winfo width $w] $sizy -} - -bind all { catch {exec cp -f .config .config.old}; \ - writeconfig .config config.h; wrapup .wrap } - -proc wrapup {w } { - catch {destroy $w} - toplevel $w -class Dialog - - global CONFIG_MODVERSIONS; vfix CONFIG_MODVERSIONS - message $w.m -width 460 -aspect 300 -relief raised -text \ - "End of design configuration. " - label $w.bm -bitmap info - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "LEON build instructions" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" \ - -width 10 -command "exit 2" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - bind $w "exit 2" - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - -} - -proc unregister_active {num} { - global active_menus - set index [lsearch -exact $active_menus $num] - if {$index != -1} then {set active_menus [lreplace $active_menus $index $index]} -} - -proc update_active {} { - global active_menus total_menus - set max 0 - if {[llength $active_menus] > 0} then { - set max [lindex $active_menus end] - update_define [toplevel_menu [lindex $active_menus 0]] $max 0 - } - foreach i $active_menus { - if {[winfo exists .menu$i] == 0} then { - unregister_active $i - } else { - update_menu$i - } - } - update_define [expr $max + 1] $total_menus 1 - update_mainmenu -} - -proc configure_entry {w option items} { - foreach i $items { - $w.$i configure -state $option - } -} - -proc validate_int {name val default} { - if {([exec echo $val | sed s/^-//g | tr -d \[:digit:\] ] != "")} then { - global $name; set $name $default - } -} - -proc validate_hex {name val default} { - if {([exec echo $val | tr -d \[:xdigit:\] ] != "")} then { - global $name; set $name $default - } -} - -proc update_define {first last allow_update} { - for {set i $first} {$i <= $last} {incr i} { - update_define_menu$i - if {$allow_update == 1} then update - } -} - -# -# Next set up the particulars for the top level menu, and define a few -# buttons which we will stick down at the bottom. -# - -frame .f0 -frame .f0.left -frame .f0.middle -frame .f0.right - -set active_menus [list] -set processed_top_level 0 -set ARCH sparc -set menus_per_column 4 -set total_menus 24 - -proc toplevel_menu {num} { - if {$num == 4} then {return 3} - if {$num == 5} then {return 3} - if {$num == 6} then {return 3} - if {$num == 7} then {return 3} - if {$num == 8} then {return 3} - if {$num == 9} then {return 3} - if {$num == 10} then {return 3} - if {$num == 14} then {return 13} - if {$num == 15} then {return 14} - if {$num == 16} then {return 14} - if {$num == 17} then {return 14} - if {$num == 18} then {return 13} - if {$num == 19} then {return 13} - if {$num == 20} then {return 13} - if {$num == 21} then {return 13} - if {$num == 22} then {return 13} - if {$num == 23} then {return 13} - return $num -} - -mainmenu_name "LEON3MP Design Configuration" -menu_option menu1 1 "Synthesis " -proc menu1 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 1} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 1]] - message $w.m -width 400 -aspect 300 -text \ - "Synthesis " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Synthesis " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 1; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu2 .menu2 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu0 .menu0 \"$title\"" - $w.f.prev configure -state disabled - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - global tmpvar_0 - minimenu $w.config.f 1 0 "Target technology " tmpvar_0 CONFIG_SYN_INFERRED - menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Target technology \"" - $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_0 -value "Inferred" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-Stratix" -variable tmpvar_0 -value "Altera-Stratix" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixII" -variable tmpvar_0 -value "Altera-StratixII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixIII" -variable tmpvar_0 -value "Altera-StratixIII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-CycloneIII" -variable tmpvar_0 -value "Altera-CycloneIII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-Others" -variable tmpvar_0 -value "Altera-Others" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator" -variable tmpvar_0 -value "Actel-Axcelerator" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic" -variable tmpvar_0 -value "Actel-Proasic" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-ProasicPlus" -variable tmpvar_0 -value "Actel-ProasicPlus" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic3" -variable tmpvar_0 -value "Actel-Proasic3" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT025CRH" -variable tmpvar_0 -value "Aeroflex-UT025CRH" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18" -variable tmpvar_0 -value "Atmel-ATC18" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18RHA" -variable tmpvar_0 -value "Atmel-ATC18RHA" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Custom1" -variable tmpvar_0 -value "Custom1" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "eASIC90" -variable tmpvar_0 -value "eASIC90" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "IHP25" -variable tmpvar_0 -value "IHP25" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "IHP25RH" -variable tmpvar_0 -value "IHP25RH" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Lattice-EC/ECP/XP" -variable tmpvar_0 -value "Lattice-EC/ECP/XP" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Quicklogic-Eclipse" -variable tmpvar_0 -value "Quicklogic-Eclipse" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Peregrine" -variable tmpvar_0 -value "Peregrine" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T" -variable tmpvar_0 -value "RH-LIB18T" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_0 -value "RH-UMC" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "SMIC130" -variable tmpvar_0 -value "SMIC130" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan2" -variable tmpvar_0 -value "Xilinx-Spartan2" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3" -variable tmpvar_0 -value "Xilinx-Spartan3" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3E" -variable tmpvar_0 -value "Xilinx-Spartan3E" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex" -variable tmpvar_0 -value "Xilinx-Virtex" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-VirtexE" -variable tmpvar_0 -value "Xilinx-VirtexE" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex2" -variable tmpvar_0 -value "Xilinx-Virtex2" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex4" -variable tmpvar_0 -value "Xilinx-Virtex4" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex5" -variable tmpvar_0 -value "Xilinx-Virtex5" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "UMC180" -variable tmpvar_0 -value "UMC180" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "TSMC90" -variable tmpvar_0 -value "TSMC90" -command "update_active" - menusplit $w $w.config.f.x0.x.menu 33 - global tmpvar_1 - minimenu $w.config.f 1 1 "Memory Library " tmpvar_1 CONFIG_MEM_INFERRED - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Memory Library \"" - $w.config.f.x1.x.menu add radiobutton -label "Inferred" -variable tmpvar_1 -value "Inferred" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "UMC18" -variable tmpvar_1 -value "UMC18" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_1 -value "RH-UMC" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Artisan" -variable tmpvar_1 -value "Artisan" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Custom1" -variable tmpvar_1 -value "Custom1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Virage" -variable tmpvar_1 -value "Virage" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Virage-TSMC90" -variable tmpvar_1 -value "Virage-TSMC90" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 7 - bool $w.config.f 1 2 "Infer RAM" CONFIG_SYN_INFER_RAM - bool $w.config.f 1 3 "Infer pads" CONFIG_SYN_INFER_PADS - bool $w.config.f 1 4 "Disable asynchronous reset" CONFIG_SYN_NO_ASYNC - bool $w.config.f 1 5 "Enable scan support " CONFIG_SYN_SCAN - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu1 {} { - global CONFIG_SYN_INFERRED - global CONFIG_SYN_CUSTOM1 - global CONFIG_SYN_ATC18 - global CONFIG_SYN_TSMC90 - global CONFIG_SYN_UMC - global CONFIG_SYN_RHUMC - global CONFIG_SYN_ARTISAN - if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then {configure_entry .menu1.config.f.x1 normal {x l}} else {configure_entry .menu1.config.f.x1 disabled {x l}} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then { - configure_entry .menu1.config.f.x2 normal {n l y}} else {configure_entry .menu1.config.f.x2 disabled {y n l}} - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then { - configure_entry .menu1.config.f.x3 normal {n l y}} else {configure_entry .menu1.config.f.x3 disabled {y n l}} -} - - -proc update_define_menu1 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_0 - global CONFIG_SYN_INFERRED - if {$tmpvar_0 == "Inferred"} then {set CONFIG_SYN_INFERRED 1} else {set CONFIG_SYN_INFERRED 0} - global CONFIG_SYN_STRATIX - if {$tmpvar_0 == "Altera-Stratix"} then {set CONFIG_SYN_STRATIX 1} else {set CONFIG_SYN_STRATIX 0} - global CONFIG_SYN_STRATIXII - if {$tmpvar_0 == "Altera-StratixII"} then {set CONFIG_SYN_STRATIXII 1} else {set CONFIG_SYN_STRATIXII 0} - global CONFIG_SYN_STRATIXIII - if {$tmpvar_0 == "Altera-StratixIII"} then {set CONFIG_SYN_STRATIXIII 1} else {set CONFIG_SYN_STRATIXIII 0} - global CONFIG_SYN_CYCLONEIII - if {$tmpvar_0 == "Altera-CycloneIII"} then {set CONFIG_SYN_CYCLONEIII 1} else {set CONFIG_SYN_CYCLONEIII 0} - global CONFIG_SYN_ALTERA - if {$tmpvar_0 == "Altera-Others"} then {set CONFIG_SYN_ALTERA 1} else {set CONFIG_SYN_ALTERA 0} - global CONFIG_SYN_AXCEL - if {$tmpvar_0 == "Actel-Axcelerator"} then {set CONFIG_SYN_AXCEL 1} else {set CONFIG_SYN_AXCEL 0} - global CONFIG_SYN_PROASIC - if {$tmpvar_0 == "Actel-Proasic"} then {set CONFIG_SYN_PROASIC 1} else {set CONFIG_SYN_PROASIC 0} - global CONFIG_SYN_PROASICPLUS - if {$tmpvar_0 == "Actel-ProasicPlus"} then {set CONFIG_SYN_PROASICPLUS 1} else {set CONFIG_SYN_PROASICPLUS 0} - global CONFIG_SYN_PROASIC3 - if {$tmpvar_0 == "Actel-Proasic3"} then {set CONFIG_SYN_PROASIC3 1} else {set CONFIG_SYN_PROASIC3 0} - global CONFIG_SYN_UT025CRH - if {$tmpvar_0 == "Aeroflex-UT025CRH"} then {set CONFIG_SYN_UT025CRH 1} else {set CONFIG_SYN_UT025CRH 0} - global CONFIG_SYN_ATC18 - if {$tmpvar_0 == "Atmel-ATC18"} then {set CONFIG_SYN_ATC18 1} else {set CONFIG_SYN_ATC18 0} - global CONFIG_SYN_ATC18RHA - if {$tmpvar_0 == "Atmel-ATC18RHA"} then {set CONFIG_SYN_ATC18RHA 1} else {set CONFIG_SYN_ATC18RHA 0} - global CONFIG_SYN_CUSTOM1 - if {$tmpvar_0 == "Custom1"} then {set CONFIG_SYN_CUSTOM1 1} else {set CONFIG_SYN_CUSTOM1 0} - global CONFIG_SYN_EASIC90 - if {$tmpvar_0 == "eASIC90"} then {set CONFIG_SYN_EASIC90 1} else {set CONFIG_SYN_EASIC90 0} - global CONFIG_SYN_IHP25 - if {$tmpvar_0 == "IHP25"} then {set CONFIG_SYN_IHP25 1} else {set CONFIG_SYN_IHP25 0} - global CONFIG_SYN_IHP25RH - if {$tmpvar_0 == "IHP25RH"} then {set CONFIG_SYN_IHP25RH 1} else {set CONFIG_SYN_IHP25RH 0} - global CONFIG_SYN_LATTICE - if {$tmpvar_0 == "Lattice-EC/ECP/XP"} then {set CONFIG_SYN_LATTICE 1} else {set CONFIG_SYN_LATTICE 0} - global CONFIG_SYN_ECLIPSE - if {$tmpvar_0 == "Quicklogic-Eclipse"} then {set CONFIG_SYN_ECLIPSE 1} else {set CONFIG_SYN_ECLIPSE 0} - global CONFIG_SYN_PEREGRINE - if {$tmpvar_0 == "Peregrine"} then {set CONFIG_SYN_PEREGRINE 1} else {set CONFIG_SYN_PEREGRINE 0} - global CONFIG_SYN_RH_LIB18T - if {$tmpvar_0 == "RH-LIB18T"} then {set CONFIG_SYN_RH_LIB18T 1} else {set CONFIG_SYN_RH_LIB18T 0} - global CONFIG_SYN_RHUMC - if {$tmpvar_0 == "RH-UMC"} then {set CONFIG_SYN_RHUMC 1} else {set CONFIG_SYN_RHUMC 0} - global CONFIG_SYN_SMIC13 - if {$tmpvar_0 == "SMIC130"} then {set CONFIG_SYN_SMIC13 1} else {set CONFIG_SYN_SMIC13 0} - global CONFIG_SYN_SPARTAN2 - if {$tmpvar_0 == "Xilinx-Spartan2"} then {set CONFIG_SYN_SPARTAN2 1} else {set CONFIG_SYN_SPARTAN2 0} - global CONFIG_SYN_SPARTAN3 - if {$tmpvar_0 == "Xilinx-Spartan3"} then {set CONFIG_SYN_SPARTAN3 1} else {set CONFIG_SYN_SPARTAN3 0} - global CONFIG_SYN_SPARTAN3E - if {$tmpvar_0 == "Xilinx-Spartan3E"} then {set CONFIG_SYN_SPARTAN3E 1} else {set CONFIG_SYN_SPARTAN3E 0} - global CONFIG_SYN_VIRTEX - if {$tmpvar_0 == "Xilinx-Virtex"} then {set CONFIG_SYN_VIRTEX 1} else {set CONFIG_SYN_VIRTEX 0} - global CONFIG_SYN_VIRTEXE - if {$tmpvar_0 == "Xilinx-VirtexE"} then {set CONFIG_SYN_VIRTEXE 1} else {set CONFIG_SYN_VIRTEXE 0} - global CONFIG_SYN_VIRTEX2 - if {$tmpvar_0 == "Xilinx-Virtex2"} then {set CONFIG_SYN_VIRTEX2 1} else {set CONFIG_SYN_VIRTEX2 0} - global CONFIG_SYN_VIRTEX4 - if {$tmpvar_0 == "Xilinx-Virtex4"} then {set CONFIG_SYN_VIRTEX4 1} else {set CONFIG_SYN_VIRTEX4 0} - global CONFIG_SYN_VIRTEX5 - if {$tmpvar_0 == "Xilinx-Virtex5"} then {set CONFIG_SYN_VIRTEX5 1} else {set CONFIG_SYN_VIRTEX5 0} - global CONFIG_SYN_UMC - if {$tmpvar_0 == "UMC180"} then {set CONFIG_SYN_UMC 1} else {set CONFIG_SYN_UMC 0} - global CONFIG_SYN_TSMC90 - if {$tmpvar_0 == "TSMC90"} then {set CONFIG_SYN_TSMC90 1} else {set CONFIG_SYN_TSMC90 0} - global tmpvar_1 - global CONFIG_MEM_INFERRED - if {$tmpvar_1 == "Inferred"} then {set CONFIG_MEM_INFERRED 1} else {set CONFIG_MEM_INFERRED 0} - global CONFIG_MEM_UMC - if {$tmpvar_1 == "UMC18"} then {set CONFIG_MEM_UMC 1} else {set CONFIG_MEM_UMC 0} - global CONFIG_MEM_RHUMC - if {$tmpvar_1 == "RH-UMC"} then {set CONFIG_MEM_RHUMC 1} else {set CONFIG_MEM_RHUMC 0} - global CONFIG_MEM_ARTISAN - if {$tmpvar_1 == "Artisan"} then {set CONFIG_MEM_ARTISAN 1} else {set CONFIG_MEM_ARTISAN 0} - global CONFIG_MEM_CUSTOM1 - if {$tmpvar_1 == "Custom1"} then {set CONFIG_MEM_CUSTOM1 1} else {set CONFIG_MEM_CUSTOM1 0} - global CONFIG_MEM_VIRAGE - if {$tmpvar_1 == "Virage"} then {set CONFIG_MEM_VIRAGE 1} else {set CONFIG_MEM_VIRAGE 0} - global CONFIG_MEM_VIRAGE90 - if {$tmpvar_1 == "Virage-TSMC90"} then {set CONFIG_MEM_VIRAGE90 1} else {set CONFIG_MEM_VIRAGE90 0} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then { - set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM&15]} else {set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM|16]} - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then { - set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS&15]} else {set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS|16]} -} - - -menu_option menu2 2 "Clock generation" -proc menu2 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 2} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 2]] - message $w.m -width 400 -aspect 300 -text \ - "Clock generation" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Clock generation" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 2; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu3 .menu3 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - global tmpvar_2 - minimenu $w.config.f 2 0 "Clock generator " tmpvar_2 CONFIG_CLK_INFERRED - menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Clock generator \"" - $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_2 -value "Inferred" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-HCLKBUF" -variable tmpvar_2 -value "Actel-HCLKBUF" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-ALTPLL" -variable tmpvar_2 -value "Altera-ALTPLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Lattice-EXPLL" -variable tmpvar_2 -value "Lattice-EXPLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Proasic3-PLLL" -variable tmpvar_2 -value "Proasic3-PLLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T-PLL" -variable tmpvar_2 -value "RH-LIB18T-PLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "DARE-PLL" -variable tmpvar_2 -value "DARE-PLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-CLKDLL" -variable tmpvar_2 -value "Xilinx-CLKDLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-DCM" -variable tmpvar_2 -value "Xilinx-DCM" -command "update_active" - menusplit $w $w.config.f.x0.x.menu 9 - int $w.config.f 2 1 "Clock multiplication factor (2 - 32)" CONFIG_CLK_MUL - int $w.config.f 2 2 "Clock division factor (2 - 32)" CONFIG_CLK_DIV - int $w.config.f 2 3 "Outout division factor (2 - 32)" CONFIG_OCLK_DIV - bool $w.config.f 2 4 "Enable Xilinx CLKDLL for PCI clock" CONFIG_PCI_CLKDLL - bool $w.config.f 2 5 "Disable external feedback for SDRAM clock" CONFIG_CLK_NOFB - bool $w.config.f 2 6 "Use PCI clock as system clock" CONFIG_PCI_SYSCLK - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu2 {} { - global CONFIG_CLK_DCM - global CONFIG_CLK_ALTDLL - global CONFIG_CLK_LATDLL - global CONFIG_CLK_PRO3PLL - global CONFIG_CLK_CLKDLL - global CONFIG_CLK_LIB18T - global CONFIG_CLK_MUL - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x1.l configure -state normal; } else {.menu2.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x1.l configure -state disabled} - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x2.l configure -state normal; } else {.menu2.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x2.l configure -state disabled} - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {.menu2.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x3.l configure -state normal; } else {.menu2.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x3.l configure -state disabled} - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then { - configure_entry .menu2.config.f.x4 normal {n l y}} else {configure_entry .menu2.config.f.x4 disabled {y n l}} - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then { - configure_entry .menu2.config.f.x5 normal {n l y}} else {configure_entry .menu2.config.f.x5 disabled {y n l}} - global CONFIG_PCI_ENABLE - global CONFIG_PCI_SYSCLK - if {($CONFIG_PCI_ENABLE != 1)} then { - configure_entry .menu2.config.f.x6 normal {n l y}} else {configure_entry .menu2.config.f.x6 disabled {y n l}} -} - - -proc update_define_menu2 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_2 - global CONFIG_CLK_INFERRED - if {$tmpvar_2 == "Inferred"} then {set CONFIG_CLK_INFERRED 1} else {set CONFIG_CLK_INFERRED 0} - global CONFIG_CLK_HCLKBUF - if {$tmpvar_2 == "Actel-HCLKBUF"} then {set CONFIG_CLK_HCLKBUF 1} else {set CONFIG_CLK_HCLKBUF 0} - global CONFIG_CLK_ALTDLL - if {$tmpvar_2 == "Altera-ALTPLL"} then {set CONFIG_CLK_ALTDLL 1} else {set CONFIG_CLK_ALTDLL 0} - global CONFIG_CLK_LATDLL - if {$tmpvar_2 == "Lattice-EXPLL"} then {set CONFIG_CLK_LATDLL 1} else {set CONFIG_CLK_LATDLL 0} - global CONFIG_CLK_PRO3PLL - if {$tmpvar_2 == "Proasic3-PLLL"} then {set CONFIG_CLK_PRO3PLL 1} else {set CONFIG_CLK_PRO3PLL 0} - global CONFIG_CLK_LIB18T - if {$tmpvar_2 == "RH-LIB18T-PLL"} then {set CONFIG_CLK_LIB18T 1} else {set CONFIG_CLK_LIB18T 0} - global CONFIG_CLK_RHUMC - if {$tmpvar_2 == "DARE-PLL"} then {set CONFIG_CLK_RHUMC 1} else {set CONFIG_CLK_RHUMC 0} - global CONFIG_CLK_CLKDLL - if {$tmpvar_2 == "Xilinx-CLKDLL"} then {set CONFIG_CLK_CLKDLL 1} else {set CONFIG_CLK_CLKDLL 0} - global CONFIG_CLK_DCM - if {$tmpvar_2 == "Xilinx-DCM"} then {set CONFIG_CLK_DCM 1} else {set CONFIG_CLK_DCM 0} - global CONFIG_CLK_MUL - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_MUL "$CONFIG_CLK_MUL" 2} - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_DIV "$CONFIG_CLK_DIV" 2} - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {validate_int CONFIG_OCLK_DIV "$CONFIG_OCLK_DIV" 2} - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then { - set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL&15]} else {set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL|16]} - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then { - set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB&15]} else {set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB|16]} - global CONFIG_PCI_ENABLE - global CONFIG_PCI_SYSCLK - if {($CONFIG_PCI_ENABLE != 1)} then { - set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK&15]} else {set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK|16]} -} - - -menu_option menu3 3 "Processor " -proc menu3 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 3} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 3]] - message $w.m -width 400 -aspect 300 -text \ - "Processor " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Processor " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 3; break" - set nextscript "catch {focus $oldFocus}; menu4 .menu4 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 3 0 "Enable LEON3 SPARC V8 Processor" CONFIG_LEON3 - int $w.config.f 3 1 "Number of processors" CONFIG_PROC_NUM - submenu $w.config.f 3 2 "Integer unit " 4 - submenu $w.config.f 3 3 "Floating-point unit" 5 - submenu $w.config.f 3 4 "Cache system" 6 - submenu $w.config.f 3 5 "MMU" 7 - submenu $w.config.f 3 6 "Debug Support Unit " 8 - submenu $w.config.f 3 7 "Fault-tolerance " 9 - submenu $w.config.f 3 8 "VHDL debug settings " 10 - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu3 {} { - global CONFIG_LEON3 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {.menu3.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu3.config.f.x1.l configure -state normal; } else {.menu3.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu3.config.f.x1.l configure -state disabled} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x2 normal {m}} else {configure_entry .menu3.config.f.x2 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x3 normal {m}} else {configure_entry .menu3.config.f.x3 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x4 normal {m}} else {configure_entry .menu3.config.f.x4 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x5 normal {m}} else {configure_entry .menu3.config.f.x5 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x6 normal {m}} else {configure_entry .menu3.config.f.x6 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x7 normal {m}} else {configure_entry .menu3.config.f.x7 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x8 normal {m}} else {configure_entry .menu3.config.f.x8 disabled {m}} -} - - -proc update_define_menu3 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_PROC_NUM "$CONFIG_PROC_NUM" 1} -} - - -proc menu4 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 4} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 4]] - message $w.m -width 400 -aspect 300 -text \ - "Integer unit " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Integer unit " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 4; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu5 .menu5 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - int $w.config.f 4 0 "SPARC register windows" CONFIG_IU_NWINDOWS - bool $w.config.f 4 1 "SPARC V8 MUL/DIV instructions" CONFIG_IU_V8MULDIV - global tmpvar_3 - minimenu $w.config.f 4 2 "Hardware multiplier latency" tmpvar_3 CONFIG_IU_MUL_LATENCY_2 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Hardware multiplier latency\"" - $w.config.f.x2.x.menu add radiobutton -label "2-cycles" -variable tmpvar_3 -value "2-cycles" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4-cycles" -variable tmpvar_3 -value "4-cycles" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "5-cycles" -variable tmpvar_3 -value "5-cycles" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 3 - bool $w.config.f 4 3 "SPARC V8e SMAC/UMAC instructions " CONFIG_IU_MUL_MAC - bool $w.config.f 4 4 "Single-vector trapping" CONFIG_IU_SVT - int $w.config.f 4 5 "Load delay" CONFIG_IU_LDELAY - int $w.config.f 4 6 "Hardware watchpoints" CONFIG_IU_WATCHPOINTS - bool $w.config.f 4 7 "Enable power-down mode " CONFIG_PWD - hex $w.config.f 4 8 " Reset start address (addr\[31:12\]) " CONFIG_IU_RSTADDR - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu4 {} { - global CONFIG_LEON3 - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x0.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x0.l configure -state normal; } else {.menu4.config.f.x0.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x0.l configure -state disabled} - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x1 normal {n l y}} else {configure_entry .menu4.config.f.x1 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {configure_entry .menu4.config.f.x2 normal {x l}} else {configure_entry .menu4.config.f.x2 disabled {x l}} - global CONFIG_IU_MUL_LATENCY_4 - global CONFIG_IU_MUL_LATENCY_5 - global CONFIG_IU_MUL_MAC - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then { - configure_entry .menu4.config.f.x3 normal {n l y}} else {configure_entry .menu4.config.f.x3 disabled {y n l}} - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x4 normal {n l y}} else {configure_entry .menu4.config.f.x4 disabled {y n l}} - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x5.l configure -state normal; } else {.menu4.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x5.l configure -state disabled} - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x6.l configure -state normal; } else {.menu4.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x6.l configure -state disabled} - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x7 normal {n l y}} else {configure_entry .menu4.config.f.x7 disabled {y n l}} - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x8.l configure -state normal; } else {.menu4.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x8.l configure -state disabled} -} - - -proc update_define_menu4 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_NWINDOWS "$CONFIG_IU_NWINDOWS" 8} - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV&15]} else {set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV|16]} - global tmpvar_3 - global CONFIG_IU_MUL_LATENCY_2 - if {$tmpvar_3 == "2-cycles"} then {set CONFIG_IU_MUL_LATENCY_2 1} else {set CONFIG_IU_MUL_LATENCY_2 0} - global CONFIG_IU_MUL_LATENCY_4 - if {$tmpvar_3 == "4-cycles"} then {set CONFIG_IU_MUL_LATENCY_4 1} else {set CONFIG_IU_MUL_LATENCY_4 0} - global CONFIG_IU_MUL_LATENCY_5 - if {$tmpvar_3 == "5-cycles"} then {set CONFIG_IU_MUL_LATENCY_5 1} else {set CONFIG_IU_MUL_LATENCY_5 0} - global CONFIG_IU_MUL_MAC - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then { - set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC&15]} else {set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC|16]} - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_SVT [expr $CONFIG_IU_SVT&15]} else {set CONFIG_IU_SVT [expr $CONFIG_IU_SVT|16]} - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_LDELAY "$CONFIG_IU_LDELAY" 1} - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_WATCHPOINTS "$CONFIG_IU_WATCHPOINTS" 0} - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_PWD [expr $CONFIG_PWD&15]} else {set CONFIG_PWD [expr $CONFIG_PWD|16]} - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {validate_hex CONFIG_IU_RSTADDR "$CONFIG_IU_RSTADDR" 00000} -} - - -proc menu5 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 5} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 5]] - message $w.m -width 400 -aspect 300 -text \ - "Floating-point unit" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Floating-point unit" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 5; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu6 .menu6 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 5 0 "Enable FPU " CONFIG_FPU_ENABLE - global tmpvar_4 - minimenu $w.config.f 5 1 "FPU core" tmpvar_4 CONFIG_FPU_GRFPU - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"FPU core\"" - $w.config.f.x1.x.menu add radiobutton -label "GRFPU" -variable tmpvar_4 -value "GRFPU" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "GRFPU-LITE" -variable tmpvar_4 -value "GRFPU-LITE" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Meiko" -variable tmpvar_4 -value "Meiko" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 3 - global tmpvar_5 - minimenu $w.config.f 5 2 "GRFPU multiplier" tmpvar_5 CONFIG_FPU_GRFPU_INFMUL - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"GRFPU multiplier\"" - $w.config.f.x2.x.menu add radiobutton -label "Inferred" -variable tmpvar_5 -value "Inferred" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "DW" -variable tmpvar_5 -value "DW" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "ModGen" -variable tmpvar_5 -value "ModGen" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 3 - global tmpvar_6 - minimenu $w.config.f 5 3 "GRFPU-LITE controller" tmpvar_6 CONFIG_FPU_GRFPC0 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"GRFPU-LITE controller\"" - $w.config.f.x3.x.menu add radiobutton -label "Simple" -variable tmpvar_6 -value "Simple" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "Data-forwarding" -variable tmpvar_6 -value "Data-forwarding" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "Non-blocking" -variable tmpvar_6 -value "Non-blocking" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 3 - bool $w.config.f 5 4 "Use VHDL netlist " CONFIG_FPU_NETLIST - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu5 {} { - global CONFIG_LEON3 - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu5.config.f.x0 normal {n l y}} else {configure_entry .menu5.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {configure_entry .menu5.config.f.x1 normal {x l}} else {configure_entry .menu5.config.f.x1 disabled {x l}} - global CONFIG_FPU_GRFPU - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then {configure_entry .menu5.config.f.x2 normal {x l}} else {configure_entry .menu5.config.f.x2 disabled {x l}} - global CONFIG_FPU_GRFPULITE - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then {configure_entry .menu5.config.f.x3 normal {x l}} else {configure_entry .menu5.config.f.x3 disabled {x l}} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - configure_entry .menu5.config.f.x4 normal {n l y}} else {configure_entry .menu5.config.f.x4 disabled {y n l}} -} - - -proc update_define_menu5 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE&15]} else {set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE|16]} - global tmpvar_4 - global CONFIG_FPU_GRFPU - if {$tmpvar_4 == "GRFPU"} then {set CONFIG_FPU_GRFPU 1} else {set CONFIG_FPU_GRFPU 0} - global CONFIG_FPU_GRFPULITE - if {$tmpvar_4 == "GRFPU-LITE"} then {set CONFIG_FPU_GRFPULITE 1} else {set CONFIG_FPU_GRFPULITE 0} - global CONFIG_FPU_MEIKO - if {$tmpvar_4 == "Meiko"} then {set CONFIG_FPU_MEIKO 1} else {set CONFIG_FPU_MEIKO 0} - global tmpvar_5 - global CONFIG_FPU_GRFPU_INFMUL - if {$tmpvar_5 == "Inferred"} then {set CONFIG_FPU_GRFPU_INFMUL 1} else {set CONFIG_FPU_GRFPU_INFMUL 0} - global CONFIG_FPU_GRFPU_DWMUL - if {$tmpvar_5 == "DW"} then {set CONFIG_FPU_GRFPU_DWMUL 1} else {set CONFIG_FPU_GRFPU_DWMUL 0} - global CONFIG_FPU_GRFPU_MODGEN - if {$tmpvar_5 == "ModGen"} then {set CONFIG_FPU_GRFPU_MODGEN 1} else {set CONFIG_FPU_GRFPU_MODGEN 0} - global tmpvar_6 - global CONFIG_FPU_GRFPC0 - if {$tmpvar_6 == "Simple"} then {set CONFIG_FPU_GRFPC0 1} else {set CONFIG_FPU_GRFPC0 0} - global CONFIG_FPU_GRFPC1 - if {$tmpvar_6 == "Data-forwarding"} then {set CONFIG_FPU_GRFPC1 1} else {set CONFIG_FPU_GRFPC1 0} - global CONFIG_FPU_GRFPC2 - if {$tmpvar_6 == "Non-blocking"} then {set CONFIG_FPU_GRFPC2 1} else {set CONFIG_FPU_GRFPC2 0} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST&15]} else {set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST|16]} -} - - -proc menu6 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 6} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 6]] - message $w.m -width 400 -aspect 300 -text \ - "Cache system" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Cache system" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 6; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu7 .menu7 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 6 0 "Enable instruction cache " CONFIG_ICACHE_ENABLE - global tmpvar_7 - minimenu $w.config.f 6 1 "Associativity (sets) " tmpvar_7 CONFIG_ICACHE_ASSO1 - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Associativity (sets) \"" - $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_7 -value "1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_7 -value "2" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "3" -variable tmpvar_7 -value "3" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_7 -value "4" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 4 - global tmpvar_8 - minimenu $w.config.f 6 2 "Set size (kbytes/set)" tmpvar_8 CONFIG_ICACHE_SZ1 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\"" - $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_8 -value "1" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_8 -value "2" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_8 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_8 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_8 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_8 -value "32" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_8 -value "64" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "128" -variable tmpvar_8 -value "128" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "256" -variable tmpvar_8 -value "256" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 9 - global tmpvar_9 - minimenu $w.config.f 6 3 "Line size (bytes/line)" tmpvar_9 CONFIG_ICACHE_LZ16 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\"" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_9 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_9 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 2 - global tmpvar_10 - minimenu $w.config.f 6 4 "Replacement alorithm" tmpvar_10 CONFIG_ICACHE_ALGORND - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Replacement alorithm\"" - $w.config.f.x4.x.menu add radiobutton -label "Random" -variable tmpvar_10 -value "Random" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "LRR" -variable tmpvar_10 -value "LRR" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "LRU" -variable tmpvar_10 -value "LRU" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 3 - bool $w.config.f 6 5 "Cache locking " CONFIG_ICACHE_LOCK - bool $w.config.f 6 6 "Enable local instruction RAM " CONFIG_ICACHE_LRAM - global tmpvar_11 - minimenu $w.config.f 6 7 "Local data RAM size (kbytes)" tmpvar_11 CONFIG_ICACHE_LRAM_SZ1 - menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x7.x.menu add radiobutton -label "1" -variable tmpvar_11 -value "1" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "2" -variable tmpvar_11 -value "2" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "4" -variable tmpvar_11 -value "4" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_11 -value "8" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_11 -value "16" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_11 -value "32" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_11 -value "64" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_11 -value "128" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_11 -value "256" -command "update_active" - menusplit $w $w.config.f.x7.x.menu 9 - hex $w.config.f 6 8 " Local instruction RAM start address (8 MSB) " CONFIG_ICACHE_LRSTART - bool $w.config.f 6 9 "Enable data cache " CONFIG_DCACHE_ENABLE - global tmpvar_12 - minimenu $w.config.f 6 10 "Associativity (sets)" tmpvar_12 CONFIG_DCACHE_ASSO1 - menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Associativity (sets)\"" - $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_12 -value "1" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_12 -value "2" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "3" -variable tmpvar_12 -value "3" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "4" -variable tmpvar_12 -value "4" -command "update_active" - menusplit $w $w.config.f.x10.x.menu 4 - global tmpvar_13 - minimenu $w.config.f 6 11 "Set size (kbytes/set)" tmpvar_13 CONFIG_DCACHE_SZ1 - menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\"" - $w.config.f.x11.x.menu add radiobutton -label "1" -variable tmpvar_13 -value "1" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "2" -variable tmpvar_13 -value "2" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "4" -variable tmpvar_13 -value "4" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "8" -variable tmpvar_13 -value "8" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "16" -variable tmpvar_13 -value "16" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "32" -variable tmpvar_13 -value "32" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "64" -variable tmpvar_13 -value "64" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "128" -variable tmpvar_13 -value "128" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_13 -value "256" -command "update_active" - menusplit $w $w.config.f.x11.x.menu 9 - global tmpvar_14 - minimenu $w.config.f 6 12 "Line size (bytes/line)" tmpvar_14 CONFIG_DCACHE_LZ16 - menu $w.config.f.x12.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\"" - $w.config.f.x12.x.menu add radiobutton -label "16" -variable tmpvar_14 -value "16" -command "update_active" - $w.config.f.x12.x.menu add radiobutton -label "32" -variable tmpvar_14 -value "32" -command "update_active" - menusplit $w $w.config.f.x12.x.menu 2 - global tmpvar_15 - minimenu $w.config.f 6 13 "Replacement alorithm" tmpvar_15 CONFIG_DCACHE_ALGORND - menu $w.config.f.x13.x.menu -tearoffcommand "menutitle \"Replacement alorithm\"" - $w.config.f.x13.x.menu add radiobutton -label "Random" -variable tmpvar_15 -value "Random" -command "update_active" - $w.config.f.x13.x.menu add radiobutton -label "LRR" -variable tmpvar_15 -value "LRR" -command "update_active" - $w.config.f.x13.x.menu add radiobutton -label "LRU" -variable tmpvar_15 -value "LRU" -command "update_active" - menusplit $w $w.config.f.x13.x.menu 3 - bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK - bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM - global tmpvar_16 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_16 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_16 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_16 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_16 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_16 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_16 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_16 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_16 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_16 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_16 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu6 {} { - global CONFIG_LEON3 - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu6.config.f.x0 normal {n l y}} else {configure_entry .menu6.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x1 normal {x l}} else {configure_entry .menu6.config.f.x1 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x2 normal {x l}} else {configure_entry .menu6.config.f.x2 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x3 normal {x l}} else {configure_entry .menu6.config.f.x3 disabled {x l}} - global CONFIG_ICACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x4 normal {x l}} else {configure_entry .menu6.config.f.x4 disabled {x l}} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - configure_entry .menu6.config.f.x5 normal {n l y}} else {configure_entry .menu6.config.f.x5 disabled {y n l}} - global CONFIG_MMU_ENABLE - global CONFIG_ICACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x6 normal {n l y}} else {configure_entry .menu6.config.f.x6 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x7 normal {x l}} else {configure_entry .menu6.config.f.x7 disabled {x l}} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {.menu6.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x8.l configure -state normal; } else {.menu6.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x8.l configure -state disabled} - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu6.config.f.x9 normal {n l y}} else {configure_entry .menu6.config.f.x9 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x10 normal {x l}} else {configure_entry .menu6.config.f.x10 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x11 normal {x l}} else {configure_entry .menu6.config.f.x11 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x12 normal {x l}} else {configure_entry .menu6.config.f.x12 disabled {x l}} - global CONFIG_DCACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x13 normal {x l}} else {configure_entry .menu6.config.f.x13 disabled {x l}} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - configure_entry .menu6.config.f.x14 normal {n l y}} else {configure_entry .menu6.config.f.x14 disabled {y n l}} - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} -} - - -proc update_define_menu6 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE&15]} else {set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE|16]} - global tmpvar_7 - global CONFIG_ICACHE_ASSO1 - if {$tmpvar_7 == "1"} then {set CONFIG_ICACHE_ASSO1 1} else {set CONFIG_ICACHE_ASSO1 0} - global CONFIG_ICACHE_ASSO2 - if {$tmpvar_7 == "2"} then {set CONFIG_ICACHE_ASSO2 1} else {set CONFIG_ICACHE_ASSO2 0} - global CONFIG_ICACHE_ASSO3 - if {$tmpvar_7 == "3"} then {set CONFIG_ICACHE_ASSO3 1} else {set CONFIG_ICACHE_ASSO3 0} - global CONFIG_ICACHE_ASSO4 - if {$tmpvar_7 == "4"} then {set CONFIG_ICACHE_ASSO4 1} else {set CONFIG_ICACHE_ASSO4 0} - global tmpvar_8 - global CONFIG_ICACHE_SZ1 - if {$tmpvar_8 == "1"} then {set CONFIG_ICACHE_SZ1 1} else {set CONFIG_ICACHE_SZ1 0} - global CONFIG_ICACHE_SZ2 - if {$tmpvar_8 == "2"} then {set CONFIG_ICACHE_SZ2 1} else {set CONFIG_ICACHE_SZ2 0} - global CONFIG_ICACHE_SZ4 - if {$tmpvar_8 == "4"} then {set CONFIG_ICACHE_SZ4 1} else {set CONFIG_ICACHE_SZ4 0} - global CONFIG_ICACHE_SZ8 - if {$tmpvar_8 == "8"} then {set CONFIG_ICACHE_SZ8 1} else {set CONFIG_ICACHE_SZ8 0} - global CONFIG_ICACHE_SZ16 - if {$tmpvar_8 == "16"} then {set CONFIG_ICACHE_SZ16 1} else {set CONFIG_ICACHE_SZ16 0} - global CONFIG_ICACHE_SZ32 - if {$tmpvar_8 == "32"} then {set CONFIG_ICACHE_SZ32 1} else {set CONFIG_ICACHE_SZ32 0} - global CONFIG_ICACHE_SZ64 - if {$tmpvar_8 == "64"} then {set CONFIG_ICACHE_SZ64 1} else {set CONFIG_ICACHE_SZ64 0} - global CONFIG_ICACHE_SZ128 - if {$tmpvar_8 == "128"} then {set CONFIG_ICACHE_SZ128 1} else {set CONFIG_ICACHE_SZ128 0} - global CONFIG_ICACHE_SZ256 - if {$tmpvar_8 == "256"} then {set CONFIG_ICACHE_SZ256 1} else {set CONFIG_ICACHE_SZ256 0} - global tmpvar_9 - global CONFIG_ICACHE_LZ16 - if {$tmpvar_9 == "16"} then {set CONFIG_ICACHE_LZ16 1} else {set CONFIG_ICACHE_LZ16 0} - global CONFIG_ICACHE_LZ32 - if {$tmpvar_9 == "32"} then {set CONFIG_ICACHE_LZ32 1} else {set CONFIG_ICACHE_LZ32 0} - global tmpvar_10 - global CONFIG_ICACHE_ALGORND - if {$tmpvar_10 == "Random"} then {set CONFIG_ICACHE_ALGORND 1} else {set CONFIG_ICACHE_ALGORND 0} - global CONFIG_ICACHE_ALGOLRR - if {$tmpvar_10 == "LRR"} then {set CONFIG_ICACHE_ALGOLRR 1} else {set CONFIG_ICACHE_ALGOLRR 0} - global CONFIG_ICACHE_ALGOLRU - if {$tmpvar_10 == "LRU"} then {set CONFIG_ICACHE_ALGOLRU 1} else {set CONFIG_ICACHE_ALGOLRU 0} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK&15]} else {set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK|16]} - global CONFIG_MMU_ENABLE - global CONFIG_ICACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM&15]} else {set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM|16]} - global tmpvar_11 - global CONFIG_ICACHE_LRAM_SZ1 - if {$tmpvar_11 == "1"} then {set CONFIG_ICACHE_LRAM_SZ1 1} else {set CONFIG_ICACHE_LRAM_SZ1 0} - global CONFIG_ICACHE_LRAM_SZ2 - if {$tmpvar_11 == "2"} then {set CONFIG_ICACHE_LRAM_SZ2 1} else {set CONFIG_ICACHE_LRAM_SZ2 0} - global CONFIG_ICACHE_LRAM_SZ4 - if {$tmpvar_11 == "4"} then {set CONFIG_ICACHE_LRAM_SZ4 1} else {set CONFIG_ICACHE_LRAM_SZ4 0} - global CONFIG_ICACHE_LRAM_SZ8 - if {$tmpvar_11 == "8"} then {set CONFIG_ICACHE_LRAM_SZ8 1} else {set CONFIG_ICACHE_LRAM_SZ8 0} - global CONFIG_ICACHE_LRAM_SZ16 - if {$tmpvar_11 == "16"} then {set CONFIG_ICACHE_LRAM_SZ16 1} else {set CONFIG_ICACHE_LRAM_SZ16 0} - global CONFIG_ICACHE_LRAM_SZ32 - if {$tmpvar_11 == "32"} then {set CONFIG_ICACHE_LRAM_SZ32 1} else {set CONFIG_ICACHE_LRAM_SZ32 0} - global CONFIG_ICACHE_LRAM_SZ64 - if {$tmpvar_11 == "64"} then {set CONFIG_ICACHE_LRAM_SZ64 1} else {set CONFIG_ICACHE_LRAM_SZ64 0} - global CONFIG_ICACHE_LRAM_SZ128 - if {$tmpvar_11 == "128"} then {set CONFIG_ICACHE_LRAM_SZ128 1} else {set CONFIG_ICACHE_LRAM_SZ128 0} - global CONFIG_ICACHE_LRAM_SZ256 - if {$tmpvar_11 == "256"} then {set CONFIG_ICACHE_LRAM_SZ256 1} else {set CONFIG_ICACHE_LRAM_SZ256 0} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {validate_hex CONFIG_ICACHE_LRSTART "$CONFIG_ICACHE_LRSTART" 8e} - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE&15]} else {set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE|16]} - global tmpvar_12 - global CONFIG_DCACHE_ASSO1 - if {$tmpvar_12 == "1"} then {set CONFIG_DCACHE_ASSO1 1} else {set CONFIG_DCACHE_ASSO1 0} - global CONFIG_DCACHE_ASSO2 - if {$tmpvar_12 == "2"} then {set CONFIG_DCACHE_ASSO2 1} else {set CONFIG_DCACHE_ASSO2 0} - global CONFIG_DCACHE_ASSO3 - if {$tmpvar_12 == "3"} then {set CONFIG_DCACHE_ASSO3 1} else {set CONFIG_DCACHE_ASSO3 0} - global CONFIG_DCACHE_ASSO4 - if {$tmpvar_12 == "4"} then {set CONFIG_DCACHE_ASSO4 1} else {set CONFIG_DCACHE_ASSO4 0} - global tmpvar_13 - global CONFIG_DCACHE_SZ1 - if {$tmpvar_13 == "1"} then {set CONFIG_DCACHE_SZ1 1} else {set CONFIG_DCACHE_SZ1 0} - global CONFIG_DCACHE_SZ2 - if {$tmpvar_13 == "2"} then {set CONFIG_DCACHE_SZ2 1} else {set CONFIG_DCACHE_SZ2 0} - global CONFIG_DCACHE_SZ4 - if {$tmpvar_13 == "4"} then {set CONFIG_DCACHE_SZ4 1} else {set CONFIG_DCACHE_SZ4 0} - global CONFIG_DCACHE_SZ8 - if {$tmpvar_13 == "8"} then {set CONFIG_DCACHE_SZ8 1} else {set CONFIG_DCACHE_SZ8 0} - global CONFIG_DCACHE_SZ16 - if {$tmpvar_13 == "16"} then {set CONFIG_DCACHE_SZ16 1} else {set CONFIG_DCACHE_SZ16 0} - global CONFIG_DCACHE_SZ32 - if {$tmpvar_13 == "32"} then {set CONFIG_DCACHE_SZ32 1} else {set CONFIG_DCACHE_SZ32 0} - global CONFIG_DCACHE_SZ64 - if {$tmpvar_13 == "64"} then {set CONFIG_DCACHE_SZ64 1} else {set CONFIG_DCACHE_SZ64 0} - global CONFIG_DCACHE_SZ128 - if {$tmpvar_13 == "128"} then {set CONFIG_DCACHE_SZ128 1} else {set CONFIG_DCACHE_SZ128 0} - global CONFIG_DCACHE_SZ256 - if {$tmpvar_13 == "256"} then {set CONFIG_DCACHE_SZ256 1} else {set CONFIG_DCACHE_SZ256 0} - global tmpvar_14 - global CONFIG_DCACHE_LZ16 - if {$tmpvar_14 == "16"} then {set CONFIG_DCACHE_LZ16 1} else {set CONFIG_DCACHE_LZ16 0} - global CONFIG_DCACHE_LZ32 - if {$tmpvar_14 == "32"} then {set CONFIG_DCACHE_LZ32 1} else {set CONFIG_DCACHE_LZ32 0} - global tmpvar_15 - global CONFIG_DCACHE_ALGORND - if {$tmpvar_15 == "Random"} then {set CONFIG_DCACHE_ALGORND 1} else {set CONFIG_DCACHE_ALGORND 0} - global CONFIG_DCACHE_ALGOLRR - if {$tmpvar_15 == "LRR"} then {set CONFIG_DCACHE_ALGOLRR 1} else {set CONFIG_DCACHE_ALGOLRR 0} - global CONFIG_DCACHE_ALGOLRU - if {$tmpvar_15 == "LRU"} then {set CONFIG_DCACHE_ALGOLRU 1} else {set CONFIG_DCACHE_ALGOLRU 0} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK&15]} else {set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK|16]} - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {validate_hex CONFIG_CACHE_FIXED "$CONFIG_CACHE_FIXED" 0} - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM&15]} else {set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM|16]} - global tmpvar_16 - global CONFIG_DCACHE_LRAM_SZ1 - if {$tmpvar_16 == "1"} then {set CONFIG_DCACHE_LRAM_SZ1 1} else {set CONFIG_DCACHE_LRAM_SZ1 0} - global CONFIG_DCACHE_LRAM_SZ2 - if {$tmpvar_16 == "2"} then {set CONFIG_DCACHE_LRAM_SZ2 1} else {set CONFIG_DCACHE_LRAM_SZ2 0} - global CONFIG_DCACHE_LRAM_SZ4 - if {$tmpvar_16 == "4"} then {set CONFIG_DCACHE_LRAM_SZ4 1} else {set CONFIG_DCACHE_LRAM_SZ4 0} - global CONFIG_DCACHE_LRAM_SZ8 - if {$tmpvar_16 == "8"} then {set CONFIG_DCACHE_LRAM_SZ8 1} else {set CONFIG_DCACHE_LRAM_SZ8 0} - global CONFIG_DCACHE_LRAM_SZ16 - if {$tmpvar_16 == "16"} then {set CONFIG_DCACHE_LRAM_SZ16 1} else {set CONFIG_DCACHE_LRAM_SZ16 0} - global CONFIG_DCACHE_LRAM_SZ32 - if {$tmpvar_16 == "32"} then {set CONFIG_DCACHE_LRAM_SZ32 1} else {set CONFIG_DCACHE_LRAM_SZ32 0} - global CONFIG_DCACHE_LRAM_SZ64 - if {$tmpvar_16 == "64"} then {set CONFIG_DCACHE_LRAM_SZ64 1} else {set CONFIG_DCACHE_LRAM_SZ64 0} - global CONFIG_DCACHE_LRAM_SZ128 - if {$tmpvar_16 == "128"} then {set CONFIG_DCACHE_LRAM_SZ128 1} else {set CONFIG_DCACHE_LRAM_SZ128 0} - global CONFIG_DCACHE_LRAM_SZ256 - if {$tmpvar_16 == "256"} then {set CONFIG_DCACHE_LRAM_SZ256 1} else {set CONFIG_DCACHE_LRAM_SZ256 0} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {validate_hex CONFIG_DCACHE_LRSTART "$CONFIG_DCACHE_LRSTART" 8f} -} - - -proc menu7 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 7} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 7]] - message $w.m -width 400 -aspect 300 -text \ - "MMU" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "MMU" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 7; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu8 .menu8 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 7 0 "Enable MMU " CONFIG_MMU_ENABLE - global tmpvar_17 - minimenu $w.config.f 7 1 "MMU type " tmpvar_17 CONFIG_MMU_COMBINED - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"MMU type \"" - $w.config.f.x1.x.menu add radiobutton -label "combined" -variable tmpvar_17 -value "combined" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "split" -variable tmpvar_17 -value "split" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 2 - global tmpvar_18 - minimenu $w.config.f 7 2 "TLB replacement sheme " tmpvar_18 CONFIG_MMU_REPARRAY - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"TLB replacement sheme \"" - $w.config.f.x2.x.menu add radiobutton -label "LRU" -variable tmpvar_18 -value "LRU" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "Increment" -variable tmpvar_18 -value "Increment" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 2 - global tmpvar_19 - minimenu $w.config.f 7 3 "Instruction (or combined) TLB entries" tmpvar_19 CONFIG_MMU_I2 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Instruction (or combined) TLB entries\"" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 5 - global tmpvar_20 - minimenu $w.config.f 7 4 "Data TLB entries" tmpvar_20 CONFIG_MMU_D2 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Data TLB entries\"" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_20 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_20 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_20 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_20 -value "16" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_20 -value "32" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 5 - bool $w.config.f 7 5 "Fast writebuffer " CONFIG_MMU_FASTWB - global tmpvar_21 - minimenu $w.config.f 7 6 "MMU page size" tmpvar_21 CONFIG_MMU_PAGE_4K - menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"MMU page size\"" - $w.config.f.x6.x.menu add radiobutton -label "4K" -variable tmpvar_21 -value "4K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "8K" -variable tmpvar_21 -value "8K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "16K" -variable tmpvar_21 -value "16K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "32K" -variable tmpvar_21 -value "32K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "Programmable" -variable tmpvar_21 -value "Programmable" -command "update_active" - menusplit $w $w.config.f.x6.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu7 {} { - global CONFIG_LEON3 - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu7.config.f.x0 normal {n l y}} else {configure_entry .menu7.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x1 normal {x l}} else {configure_entry .menu7.config.f.x1 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x2 normal {x l}} else {configure_entry .menu7.config.f.x2 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x3 normal {x l}} else {configure_entry .menu7.config.f.x3 disabled {x l}} - global CONFIG_MMU_SPLIT - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {configure_entry .menu7.config.f.x4 normal {x l}} else {configure_entry .menu7.config.f.x4 disabled {x l}} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - configure_entry .menu7.config.f.x5 normal {n l y}} else {configure_entry .menu7.config.f.x5 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x6 normal {x l}} else {configure_entry .menu7.config.f.x6 disabled {x l}} -} - - -proc update_define_menu7 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE&15]} else {set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE|16]} - global tmpvar_17 - global CONFIG_MMU_COMBINED - if {$tmpvar_17 == "combined"} then {set CONFIG_MMU_COMBINED 1} else {set CONFIG_MMU_COMBINED 0} - global CONFIG_MMU_SPLIT - if {$tmpvar_17 == "split"} then {set CONFIG_MMU_SPLIT 1} else {set CONFIG_MMU_SPLIT 0} - global tmpvar_18 - global CONFIG_MMU_REPARRAY - if {$tmpvar_18 == "LRU"} then {set CONFIG_MMU_REPARRAY 1} else {set CONFIG_MMU_REPARRAY 0} - global CONFIG_MMU_REPINCREMENT - if {$tmpvar_18 == "Increment"} then {set CONFIG_MMU_REPINCREMENT 1} else {set CONFIG_MMU_REPINCREMENT 0} - global tmpvar_19 - global CONFIG_MMU_I2 - if {$tmpvar_19 == "2"} then {set CONFIG_MMU_I2 1} else {set CONFIG_MMU_I2 0} - global CONFIG_MMU_I4 - if {$tmpvar_19 == "4"} then {set CONFIG_MMU_I4 1} else {set CONFIG_MMU_I4 0} - global CONFIG_MMU_I8 - if {$tmpvar_19 == "8"} then {set CONFIG_MMU_I8 1} else {set CONFIG_MMU_I8 0} - global CONFIG_MMU_I16 - if {$tmpvar_19 == "16"} then {set CONFIG_MMU_I16 1} else {set CONFIG_MMU_I16 0} - global CONFIG_MMU_I32 - if {$tmpvar_19 == "32"} then {set CONFIG_MMU_I32 1} else {set CONFIG_MMU_I32 0} - global tmpvar_20 - global CONFIG_MMU_D2 - if {$tmpvar_20 == "2"} then {set CONFIG_MMU_D2 1} else {set CONFIG_MMU_D2 0} - global CONFIG_MMU_D4 - if {$tmpvar_20 == "4"} then {set CONFIG_MMU_D4 1} else {set CONFIG_MMU_D4 0} - global CONFIG_MMU_D8 - if {$tmpvar_20 == "8"} then {set CONFIG_MMU_D8 1} else {set CONFIG_MMU_D8 0} - global CONFIG_MMU_D16 - if {$tmpvar_20 == "16"} then {set CONFIG_MMU_D16 1} else {set CONFIG_MMU_D16 0} - global CONFIG_MMU_D32 - if {$tmpvar_20 == "32"} then {set CONFIG_MMU_D32 1} else {set CONFIG_MMU_D32 0} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB&15]} else {set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB|16]} - global tmpvar_21 - global CONFIG_MMU_PAGE_4K - if {$tmpvar_21 == "4K"} then {set CONFIG_MMU_PAGE_4K 1} else {set CONFIG_MMU_PAGE_4K 0} - global CONFIG_MMU_PAGE_8K - if {$tmpvar_21 == "8K"} then {set CONFIG_MMU_PAGE_8K 1} else {set CONFIG_MMU_PAGE_8K 0} - global CONFIG_MMU_PAGE_16K - if {$tmpvar_21 == "16K"} then {set CONFIG_MMU_PAGE_16K 1} else {set CONFIG_MMU_PAGE_16K 0} - global CONFIG_MMU_PAGE_32K - if {$tmpvar_21 == "32K"} then {set CONFIG_MMU_PAGE_32K 1} else {set CONFIG_MMU_PAGE_32K 0} - global CONFIG_MMU_PAGE_PROG - if {$tmpvar_21 == "Programmable"} then {set CONFIG_MMU_PAGE_PROG 1} else {set CONFIG_MMU_PAGE_PROG 0} -} - - -proc menu8 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 8} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 8]] - message $w.m -width 400 -aspect 300 -text \ - "Debug Support Unit " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Debug Support Unit " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 8; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu9 .menu9 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 8 0 "Enable LEON3 Debug support unit " CONFIG_DSU_ENABLE - bool $w.config.f 8 1 "Instruction trace buffer" CONFIG_DSU_ITRACE - global tmpvar_22 - minimenu $w.config.f 8 2 "Instruction trace buffer size (kbytes)" tmpvar_22 CONFIG_DSU_ITRACESZ1 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Instruction trace buffer size (kbytes)\"" - $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_22 -value "1" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_22 -value "2" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_22 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_22 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_22 -value "16" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 5 - bool $w.config.f 8 3 "AHB trace buffer" CONFIG_DSU_ATRACE - global tmpvar_23 - minimenu $w.config.f 8 4 "AHB trace buffer size (kbytes)" tmpvar_23 CONFIG_DSU_ATRACESZ1 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB trace buffer size (kbytes)\"" - $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_23 -value "1" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_23 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_23 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_23 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_23 -value "16" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu8 {} { - global CONFIG_LEON3 - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu8.config.f.x0 normal {n l y}} else {configure_entry .menu8.config.f.x0 disabled {y n l}} - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - configure_entry .menu8.config.f.x1 normal {n l y}} else {configure_entry .menu8.config.f.x1 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then {configure_entry .menu8.config.f.x2 normal {x l}} else {configure_entry .menu8.config.f.x2 disabled {x l}} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - configure_entry .menu8.config.f.x3 normal {n l y}} else {configure_entry .menu8.config.f.x3 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then {configure_entry .menu8.config.f.x4 normal {x l}} else {configure_entry .menu8.config.f.x4 disabled {x l}} -} - - -proc update_define_menu8 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE&15]} else {set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE|16]} - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE&15]} else {set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE|16]} - global tmpvar_22 - global CONFIG_DSU_ITRACESZ1 - if {$tmpvar_22 == "1"} then {set CONFIG_DSU_ITRACESZ1 1} else {set CONFIG_DSU_ITRACESZ1 0} - global CONFIG_DSU_ITRACESZ2 - if {$tmpvar_22 == "2"} then {set CONFIG_DSU_ITRACESZ2 1} else {set CONFIG_DSU_ITRACESZ2 0} - global CONFIG_DSU_ITRACESZ4 - if {$tmpvar_22 == "4"} then {set CONFIG_DSU_ITRACESZ4 1} else {set CONFIG_DSU_ITRACESZ4 0} - global CONFIG_DSU_ITRACESZ8 - if {$tmpvar_22 == "8"} then {set CONFIG_DSU_ITRACESZ8 1} else {set CONFIG_DSU_ITRACESZ8 0} - global CONFIG_DSU_ITRACESZ16 - if {$tmpvar_22 == "16"} then {set CONFIG_DSU_ITRACESZ16 1} else {set CONFIG_DSU_ITRACESZ16 0} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE&15]} else {set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE|16]} - global tmpvar_23 - global CONFIG_DSU_ATRACESZ1 - if {$tmpvar_23 == "1"} then {set CONFIG_DSU_ATRACESZ1 1} else {set CONFIG_DSU_ATRACESZ1 0} - global CONFIG_DSU_ATRACESZ2 - if {$tmpvar_23 == "2"} then {set CONFIG_DSU_ATRACESZ2 1} else {set CONFIG_DSU_ATRACESZ2 0} - global CONFIG_DSU_ATRACESZ4 - if {$tmpvar_23 == "4"} then {set CONFIG_DSU_ATRACESZ4 1} else {set CONFIG_DSU_ATRACESZ4 0} - global CONFIG_DSU_ATRACESZ8 - if {$tmpvar_23 == "8"} then {set CONFIG_DSU_ATRACESZ8 1} else {set CONFIG_DSU_ATRACESZ8 0} - global CONFIG_DSU_ATRACESZ16 - if {$tmpvar_23 == "16"} then {set CONFIG_DSU_ATRACESZ16 1} else {set CONFIG_DSU_ATRACESZ16 0} -} - - -proc menu9 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 9} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 9]] - message $w.m -width 400 -aspect 300 -text \ - "Fault-tolerance " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Fault-tolerance " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 9; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu10 .menu10 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu9 {} { -} - - -proc update_define_menu9 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu10 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 10} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 10]] - message $w.m -width 400 -aspect 300 -text \ - "VHDL debug settings " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "VHDL debug settings " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 10; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 10; catch {destroy .menu3}; unregister_active 3; menu11 .menu11 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 10 0 "Processor disassembly to console " CONFIG_IU_DISAS - bool $w.config.f 10 1 "Processor disassembly in netlist " CONFIG_IU_DISAS_NET - bool $w.config.f 10 2 "32-bit program counters " CONFIG_DEBUG_PC32 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu10 {} { - global CONFIG_LEON3 - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu10.config.f.x0 normal {n l y}} else {configure_entry .menu10.config.f.x0 disabled {y n l}} - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then { - configure_entry .menu10.config.f.x1 normal {n l y}} else {configure_entry .menu10.config.f.x1 disabled {y n l}} - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu10.config.f.x2 normal {n l y}} else {configure_entry .menu10.config.f.x2 disabled {y n l}} -} - - -proc update_define_menu10 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS&15]} else {set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS|16]} - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then { - set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET&15]} else {set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET|16]} - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32&15]} else {set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32|16]} -} - - -menu_option menu11 11 "AMBA configuration" -proc menu11 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 11} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 11]] - message $w.m -width 400 -aspect 300 -text \ - "AMBA configuration" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "AMBA configuration" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu12 .menu12 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - int $w.config.f 11 0 "Default AHB master" CONFIG_AHB_DEFMST - bool $w.config.f 11 1 "Round-robin arbiter " CONFIG_AHB_RROBIN - bool $w.config.f 11 2 "AHB split-transaction support " CONFIG_AHB_SPLIT - hex $w.config.f 11 3 "I/O area start address (haddr\[31:20\]) " CONFIG_AHB_IOADDR - hex $w.config.f 11 4 "AHB/APB bridge address (haddr\[31:20\]) " CONFIG_APB_HADDR - bool $w.config.f 11 5 "Enable AMBA AHB monitor " CONFIG_AHB_MON - bool $w.config.f 11 6 "Report AHB errors " CONFIG_AHB_MONERR - bool $w.config.f 11 7 "Report AHB warings " CONFIG_AHB_MONWAR - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu11 {} { - global CONFIG_AHB_MON - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then { - configure_entry .menu11.config.f.x6 normal {n l y}} else {configure_entry .menu11.config.f.x6 disabled {y n l}} - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then { - configure_entry .menu11.config.f.x7 normal {n l y}} else {configure_entry .menu11.config.f.x7 disabled {y n l}} -} - - -proc update_define_menu11 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_AHB_MON - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then { - set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR&15]} else {set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR|16]} - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then { - set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR&15]} else {set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR|16]} -} - - -menu_option menu12 12 "Debug Link " -proc menu12 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 12} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 12]] - message $w.m -width 400 -aspect 300 -text \ - "Debug Link " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Debug Link " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu13 .menu13 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 12 0 "Serial Debug Link (RS232) " CONFIG_DSU_UART - bool $w.config.f 12 1 "JTAG Debug Link" CONFIG_DSU_JTAG - bool $w.config.f 12 2 "Ethernet Debug Communication Link (EDCL)" CONFIG_DSU_ETH - global tmpvar_25 - minimenu $w.config.f 12 3 "Ethernet/AHB bridge buffer size (kbytes)" tmpvar_25 CONFIG_DSU_ETHSZ1 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Ethernet/AHB bridge buffer size (kbytes)\"" - $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_25 -value "1" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_25 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_25 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_25 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_25 -value "16" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 5 - hex $w.config.f 12 4 "MSB 16 bits of IP address (hex) " CONFIG_DSU_IPMSB - hex $w.config.f 12 5 "LSB 16 bits of IP address (hex) " CONFIG_DSU_IPLSB - hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB - hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB - bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu12 {} { - global CONFIG_GRETH_ENABLE - global CONFIG_DSU_ETH - if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu12.config.f.x2 normal {n l y}} else {configure_entry .menu12.config.f.x2 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {configure_entry .menu12.config.f.x3 normal {x l}} else {configure_entry .menu12.config.f.x3 disabled {x l}} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x4.l configure -state normal; } else {.menu12.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x4.l configure -state disabled} - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x5.l configure -state normal; } else {.menu12.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x5.l configure -state disabled} - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA - global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} -} - - -proc update_define_menu12 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_GRETH_ENABLE - global CONFIG_DSU_ETH - if {($CONFIG_GRETH_ENABLE == 1)} then { - set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH&15]} else {set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH|16]} - global tmpvar_25 - global CONFIG_DSU_ETHSZ1 - if {$tmpvar_25 == "1"} then {set CONFIG_DSU_ETHSZ1 1} else {set CONFIG_DSU_ETHSZ1 0} - global CONFIG_DSU_ETHSZ2 - if {$tmpvar_25 == "2"} then {set CONFIG_DSU_ETHSZ2 1} else {set CONFIG_DSU_ETHSZ2 0} - global CONFIG_DSU_ETHSZ4 - if {$tmpvar_25 == "4"} then {set CONFIG_DSU_ETHSZ4 1} else {set CONFIG_DSU_ETHSZ4 0} - global CONFIG_DSU_ETHSZ8 - if {$tmpvar_25 == "8"} then {set CONFIG_DSU_ETHSZ8 1} else {set CONFIG_DSU_ETHSZ8 0} - global CONFIG_DSU_ETHSZ16 - if {$tmpvar_25 == "16"} then {set CONFIG_DSU_ETHSZ16 1} else {set CONFIG_DSU_ETHSZ16 0} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPMSB "$CONFIG_DSU_IPMSB" C0A8} - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPLSB "$CONFIG_DSU_IPLSB" 0033} - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA - global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} -} - - -menu_option menu13 13 "Peripherals " -proc menu13 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 13} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 13]] - message $w.m -width 400 -aspect 300 -text \ - "Peripherals " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Peripherals " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; break" - set nextscript "catch {focus $oldFocus}; menu14 .menu14 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - submenu $w.config.f 13 0 "Memory controllers " 14 - submenu $w.config.f 13 1 "On-chip RAM/ROM " 18 - submenu $w.config.f 13 2 "Ethernet " 19 - submenu $w.config.f 13 3 "CAN " 20 - submenu $w.config.f 13 4 "PCI " 21 - submenu $w.config.f 13 5 "Spacewire " 22 - submenu $w.config.f 13 6 "UARTs, timers and irq control " 23 - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu13 {} { -} - - -proc update_define_menu13 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu14 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 14} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 14]] - message $w.m -width 400 -aspect 300 -text \ - "Memory controllers " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Memory controllers " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; break" - set nextscript "catch {focus $oldFocus}; menu15 .menu15 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - submenu $w.config.f 14 0 "8/32-bit PROM/SRAM controller " 15 - submenu $w.config.f 14 1 "Leon2 memory controller " 16 - submenu $w.config.f 14 2 "PC133 SDRAM controller " 17 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu14 {} { -} - - -proc update_define_menu14 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu15 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 15} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 15]] - message $w.m -width 400 -aspect 300 -text \ - "8/32-bit PROM/SRAM controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "8/32-bit PROM/SRAM controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu16 .menu16 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 15 0 "Enable 8/32-bit PROM/SRAM controller " CONFIG_SRCTRL - bool $w.config.f 15 1 "8-bit PROM interface " CONFIG_SRCTRL_8BIT - int $w.config.f 15 2 "PROM waitstates" CONFIG_SRCTRL_PROMWS - int $w.config.f 15 3 "RAM waitstates" CONFIG_SRCTRL_RAMWS - int $w.config.f 15 4 "IO waitstates" CONFIG_SRCTRL_IOWS - bool $w.config.f 15 5 "Use read-modify-write for sub-word writes " CONFIG_SRCTRL_RMW - global tmpvar_26 - minimenu $w.config.f 15 6 "SRAM banks" tmpvar_26 CONFIG_SRCTRL_SRBANKS1 - menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"SRAM banks\"" - $w.config.f.x6.x.menu add radiobutton -label "1" -variable tmpvar_26 -value "1" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "2" -variable tmpvar_26 -value "2" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "3" -variable tmpvar_26 -value "3" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "4" -variable tmpvar_26 -value "4" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "5" -variable tmpvar_26 -value "5" -command "update_active" - menusplit $w $w.config.f.x6.x.menu 5 - global tmpvar_27 - minimenu $w.config.f 15 7 "SRAM bank size (kb) (0 for programmable)" tmpvar_27 CONFIG_SRCTRL_BANKSZ0 - menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"SRAM bank size (kb) (0 for programmable)\"" - $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_27 -value "8" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_27 -value "16" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_27 -value "32" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_27 -value "64" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_27 -value "128" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_27 -value "256" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "512" -variable tmpvar_27 -value "512" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "1024" -variable tmpvar_27 -value "1024" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "2048" -variable tmpvar_27 -value "2048" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "4096" -variable tmpvar_27 -value "4096" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "8192" -variable tmpvar_27 -value "8192" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16384" -variable tmpvar_27 -value "16384" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32768" -variable tmpvar_27 -value "32768" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "65536" -variable tmpvar_27 -value "65536" -command "update_active" - menusplit $w $w.config.f.x7.x.menu 14 - int $w.config.f 15 8 "PROM bank select address bit (0 - 28)" CONFIG_SRCTRL_ROMASEL - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu15 {} { - global CONFIG_SRCTRL - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then { - configure_entry .menu15.config.f.x1 normal {n l y}} else {configure_entry .menu15.config.f.x1 disabled {y n l}} - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x2.l configure -state normal; } else {.menu15.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x2.l configure -state disabled} - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x3.l configure -state normal; } else {.menu15.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x3.l configure -state disabled} - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x4.l configure -state normal; } else {.menu15.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x4.l configure -state disabled} - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then { - configure_entry .menu15.config.f.x5 normal {n l y}} else {configure_entry .menu15.config.f.x5 disabled {y n l}} - if {($CONFIG_SRCTRL == 1)} then {configure_entry .menu15.config.f.x6 normal {x l}} else {configure_entry .menu15.config.f.x6 disabled {x l}} - if {($CONFIG_SRCTRL == 1)} then {configure_entry .menu15.config.f.x7 normal {x l}} else {configure_entry .menu15.config.f.x7 disabled {x l}} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x8.l configure -state normal; } else {.menu15.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x8.l configure -state disabled} -} - - -proc update_define_menu15 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SRCTRL - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then { - set CONFIG_SRCTRL_8BIT [expr $CONFIG_SRCTRL_8BIT&15]} else {set CONFIG_SRCTRL_8BIT [expr $CONFIG_SRCTRL_8BIT|16]} - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_PROMWS "$CONFIG_SRCTRL_PROMWS" 3} - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_RAMWS "$CONFIG_SRCTRL_RAMWS" 0} - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_IOWS "$CONFIG_SRCTRL_IOWS" 0} - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then { - set CONFIG_SRCTRL_RMW [expr $CONFIG_SRCTRL_RMW&15]} else {set CONFIG_SRCTRL_RMW [expr $CONFIG_SRCTRL_RMW|16]} - global tmpvar_26 - global CONFIG_SRCTRL_SRBANKS1 - if {$tmpvar_26 == "1"} then {set CONFIG_SRCTRL_SRBANKS1 1} else {set CONFIG_SRCTRL_SRBANKS1 0} - global CONFIG_SRCTRL_SRBANKS2 - if {$tmpvar_26 == "2"} then {set CONFIG_SRCTRL_SRBANKS2 1} else {set CONFIG_SRCTRL_SRBANKS2 0} - global CONFIG_SRCTRL_SRBANKS3 - if {$tmpvar_26 == "3"} then {set CONFIG_SRCTRL_SRBANKS3 1} else {set CONFIG_SRCTRL_SRBANKS3 0} - global CONFIG_SRCTRL_SRBANKS4 - if {$tmpvar_26 == "4"} then {set CONFIG_SRCTRL_SRBANKS4 1} else {set CONFIG_SRCTRL_SRBANKS4 0} - global CONFIG_SRCTRL_SRBANKS5 - if {$tmpvar_26 == "5"} then {set CONFIG_SRCTRL_SRBANKS5 1} else {set CONFIG_SRCTRL_SRBANKS5 0} - global tmpvar_27 - global CONFIG_SRCTRL_BANKSZ0 - if {$tmpvar_27 == "8"} then {set CONFIG_SRCTRL_BANKSZ0 1} else {set CONFIG_SRCTRL_BANKSZ0 0} - global CONFIG_SRCTRL_BANKSZ1 - if {$tmpvar_27 == "16"} then {set CONFIG_SRCTRL_BANKSZ1 1} else {set CONFIG_SRCTRL_BANKSZ1 0} - global CONFIG_SRCTRL_BANKSZ2 - if {$tmpvar_27 == "32"} then {set CONFIG_SRCTRL_BANKSZ2 1} else {set CONFIG_SRCTRL_BANKSZ2 0} - global CONFIG_SRCTRL_BANKSZ3 - if {$tmpvar_27 == "64"} then {set CONFIG_SRCTRL_BANKSZ3 1} else {set CONFIG_SRCTRL_BANKSZ3 0} - global CONFIG_SRCTRL_BANKSZ4 - if {$tmpvar_27 == "128"} then {set CONFIG_SRCTRL_BANKSZ4 1} else {set CONFIG_SRCTRL_BANKSZ4 0} - global CONFIG_SRCTRL_BANKSZ5 - if {$tmpvar_27 == "256"} then {set CONFIG_SRCTRL_BANKSZ5 1} else {set CONFIG_SRCTRL_BANKSZ5 0} - global CONFIG_SRCTRL_BANKSZ6 - if {$tmpvar_27 == "512"} then {set CONFIG_SRCTRL_BANKSZ6 1} else {set CONFIG_SRCTRL_BANKSZ6 0} - global CONFIG_SRCTRL_BANKSZ7 - if {$tmpvar_27 == "1024"} then {set CONFIG_SRCTRL_BANKSZ7 1} else {set CONFIG_SRCTRL_BANKSZ7 0} - global CONFIG_SRCTRL_BANKSZ8 - if {$tmpvar_27 == "2048"} then {set CONFIG_SRCTRL_BANKSZ8 1} else {set CONFIG_SRCTRL_BANKSZ8 0} - global CONFIG_SRCTRL_BANKSZ9 - if {$tmpvar_27 == "4096"} then {set CONFIG_SRCTRL_BANKSZ9 1} else {set CONFIG_SRCTRL_BANKSZ9 0} - global CONFIG_SRCTRL_BANKSZ10 - if {$tmpvar_27 == "8192"} then {set CONFIG_SRCTRL_BANKSZ10 1} else {set CONFIG_SRCTRL_BANKSZ10 0} - global CONFIG_SRCTRL_BANKSZ11 - if {$tmpvar_27 == "16384"} then {set CONFIG_SRCTRL_BANKSZ11 1} else {set CONFIG_SRCTRL_BANKSZ11 0} - global CONFIG_SRCTRL_BANKSZ12 - if {$tmpvar_27 == "32768"} then {set CONFIG_SRCTRL_BANKSZ12 1} else {set CONFIG_SRCTRL_BANKSZ12 0} - global CONFIG_SRCTRL_BANKSZ13 - if {$tmpvar_27 == "65536"} then {set CONFIG_SRCTRL_BANKSZ13 1} else {set CONFIG_SRCTRL_BANKSZ13 0} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_ROMASEL "$CONFIG_SRCTRL_ROMASEL" 19} -} - - -proc menu16 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 16} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 16]] - message $w.m -width 400 -aspect 300 -text \ - "Leon2 memory controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Leon2 memory controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu17 .menu17 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 16 0 "Enable Leon2 memory controller " CONFIG_MCTRL_LEON2 - bool $w.config.f 16 1 "8-bit PROM/SRAM bus support " CONFIG_MCTRL_8BIT - bool $w.config.f 16 2 "16-bit PROM/SRAM bus support " CONFIG_MCTRL_16BIT - bool $w.config.f 16 3 "5th SRAM chip-select " CONFIG_MCTRL_5CS - bool $w.config.f 16 4 "SDRAM controller " CONFIG_MCTRL_SDRAM - bool $w.config.f 16 5 "Separate address and data buses" CONFIG_MCTRL_SDRAM_SEPBUS - bool $w.config.f 16 6 "64-bit SDRAM data bus" CONFIG_MCTRL_SDRAM_BUS64 - bool $w.config.f 16 7 "Unsynchronized sdclock" CONFIG_MCTRL_SDRAM_INVCLK - bool $w.config.f 16 8 "Enable page burst operation " CONFIG_MCTRL_PAGE - bool $w.config.f 16 9 "Enable programmable page burst " CONFIG_MCTRL_PROGPAGE - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu16 {} { - global CONFIG_MCTRL_LEON2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x1 normal {n l y}} else {configure_entry .menu16.config.f.x1 disabled {y n l}} - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x2 normal {n l y}} else {configure_entry .menu16.config.f.x2 disabled {y n l}} - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x3 normal {n l y}} else {configure_entry .menu16.config.f.x3 disabled {y n l}} - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x4 normal {n l y}} else {configure_entry .menu16.config.f.x4 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - configure_entry .menu16.config.f.x5 normal {n l y}} else {configure_entry .menu16.config.f.x5 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - configure_entry .menu16.config.f.x6 normal {n l y}} else {configure_entry .menu16.config.f.x6 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - configure_entry .menu16.config.f.x7 normal {n l y}} else {configure_entry .menu16.config.f.x7 disabled {y n l}} - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - configure_entry .menu16.config.f.x8 normal {n l y}} else {configure_entry .menu16.config.f.x8 disabled {y n l}} - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { - configure_entry .menu16.config.f.x9 normal {n l y}} else {configure_entry .menu16.config.f.x9 disabled {y n l}} -} - - -proc update_define_menu16 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_MCTRL_LEON2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT&15]} else {set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT|16]} - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT&15]} else {set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT|16]} - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS&15]} else {set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS|16]} - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM&15]} else {set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM|16]} - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS&15]} else {set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS|16]} - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64&15]} else {set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64|16]} - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK&15]} else {set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK|16]} - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE&15]} else {set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE|16]} - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { - set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE&15]} else {set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE|16]} -} - - -proc menu17 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 17} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 17]] - message $w.m -width 400 -aspect 300 -text \ - "PC133 SDRAM controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "PC133 SDRAM controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 17; catch {destroy .menu14}; unregister_active 14; menu18 .menu18 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 17 0 "Enable PC133 SDRAM controller " CONFIG_SDCTRL - bool $w.config.f 17 1 "64-bit SDRAM data bus" CONFIG_SDCTRL_BUS64 - bool $w.config.f 17 2 "Unsynchronized sdclock" CONFIG_SDCTRL_INVCLK - bool $w.config.f 17 3 "Enable page burst operation " CONFIG_SDCTRL_PAGE - bool $w.config.f 17 4 "Enable programmable page burst " CONFIG_SDCTRL_PROGPAGE - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu17 {} { - global CONFIG_SDCTRL - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x1 normal {n l y}} else {configure_entry .menu17.config.f.x1 disabled {y n l}} - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x2 normal {n l y}} else {configure_entry .menu17.config.f.x2 disabled {y n l}} - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x3 normal {n l y}} else {configure_entry .menu17.config.f.x3 disabled {y n l}} - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then { - configure_entry .menu17.config.f.x4 normal {n l y}} else {configure_entry .menu17.config.f.x4 disabled {y n l}} -} - - -proc update_define_menu17 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SDCTRL - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_BUS64 [expr $CONFIG_SDCTRL_BUS64&15]} else {set CONFIG_SDCTRL_BUS64 [expr $CONFIG_SDCTRL_BUS64|16]} - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_INVCLK [expr $CONFIG_SDCTRL_INVCLK&15]} else {set CONFIG_SDCTRL_INVCLK [expr $CONFIG_SDCTRL_INVCLK|16]} - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_PAGE [expr $CONFIG_SDCTRL_PAGE&15]} else {set CONFIG_SDCTRL_PAGE [expr $CONFIG_SDCTRL_PAGE|16]} - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then { - set CONFIG_SDCTRL_PROGPAGE [expr $CONFIG_SDCTRL_PROGPAGE&15]} else {set CONFIG_SDCTRL_PROGPAGE [expr $CONFIG_SDCTRL_PROGPAGE|16]} -} - - -proc menu18 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 18} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 18]] - message $w.m -width 400 -aspect 300 -text \ - "On-chip RAM/ROM " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "On-chip RAM/ROM " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu19 .menu19 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 18 0 "On-chip AHB ROM " CONFIG_AHBROM_ENABLE - hex $w.config.f 18 1 "ROM start address (haddr\[31:20\]) " CONFIG_AHBROM_START - bool $w.config.f 18 2 "Pipelined ROM access " CONFIG_AHBROM_PIPE - bool $w.config.f 18 3 "On-chip AHB RAM " CONFIG_AHBRAM_ENABLE - global tmpvar_28 - minimenu $w.config.f 18 4 "AHB RAM size (Kbyte)" tmpvar_28 CONFIG_AHBRAM_SZ1 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB RAM size (Kbyte)\"" - $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_28 -value "1" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_28 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_28 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_28 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_28 -value "16" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_28 -value "32" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "64" -variable tmpvar_28 -value "64" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 7 - hex $w.config.f 18 5 "RAM start address (haddr\[31:20\]) " CONFIG_AHBRAM_START - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu18 {} { - global CONFIG_AHBROM_ENABLE - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {.menu18.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x1.l configure -state normal; } else {.menu18.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x1.l configure -state disabled} - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then { - configure_entry .menu18.config.f.x2 normal {n l y}} else {configure_entry .menu18.config.f.x2 disabled {y n l}} - global CONFIG_AHBRAM_ENABLE - if {($CONFIG_AHBRAM_ENABLE == 1)} then {configure_entry .menu18.config.f.x4 normal {x l}} else {configure_entry .menu18.config.f.x4 disabled {x l}} - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {.menu18.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x5.l configure -state normal; } else {.menu18.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x5.l configure -state disabled} -} - - -proc update_define_menu18 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_AHBROM_ENABLE - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {validate_hex CONFIG_AHBROM_START "$CONFIG_AHBROM_START" 000} - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then { - set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE&15]} else {set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE|16]} - global tmpvar_28 - global CONFIG_AHBRAM_SZ1 - if {$tmpvar_28 == "1"} then {set CONFIG_AHBRAM_SZ1 1} else {set CONFIG_AHBRAM_SZ1 0} - global CONFIG_AHBRAM_SZ2 - if {$tmpvar_28 == "2"} then {set CONFIG_AHBRAM_SZ2 1} else {set CONFIG_AHBRAM_SZ2 0} - global CONFIG_AHBRAM_SZ4 - if {$tmpvar_28 == "4"} then {set CONFIG_AHBRAM_SZ4 1} else {set CONFIG_AHBRAM_SZ4 0} - global CONFIG_AHBRAM_SZ8 - if {$tmpvar_28 == "8"} then {set CONFIG_AHBRAM_SZ8 1} else {set CONFIG_AHBRAM_SZ8 0} - global CONFIG_AHBRAM_SZ16 - if {$tmpvar_28 == "16"} then {set CONFIG_AHBRAM_SZ16 1} else {set CONFIG_AHBRAM_SZ16 0} - global CONFIG_AHBRAM_SZ32 - if {$tmpvar_28 == "32"} then {set CONFIG_AHBRAM_SZ32 1} else {set CONFIG_AHBRAM_SZ32 0} - global CONFIG_AHBRAM_SZ64 - if {$tmpvar_28 == "64"} then {set CONFIG_AHBRAM_SZ64 1} else {set CONFIG_AHBRAM_SZ64 0} - global CONFIG_AHBRAM_ENABLE - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {validate_hex CONFIG_AHBRAM_START "$CONFIG_AHBRAM_START" A00} -} - - -proc menu19 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 19} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 19]] - message $w.m -width 400 -aspect 300 -text \ - "Ethernet " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Ethernet " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu20 .menu20 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 19 0 "Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH_ENABLE - bool $w.config.f 19 1 "Enable 1000 Mbit support " CONFIG_GRETH_GIGA - global tmpvar_29 - minimenu $w.config.f 19 2 "AHB FIFO size (words) " tmpvar_29 CONFIG_GRETH_FIFO4 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB FIFO size (words) \"" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_29 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_29 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_29 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_29 -value "32" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_29 -value "64" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu19 {} { - global CONFIG_GRETH_ENABLE - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu19.config.f.x1 normal {n l y}} else {configure_entry .menu19.config.f.x1 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {configure_entry .menu19.config.f.x2 normal {x l}} else {configure_entry .menu19.config.f.x2 disabled {x l}} -} - - -proc update_define_menu19 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_GRETH_ENABLE - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1)} then { - set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA&15]} else {set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA|16]} - global tmpvar_29 - global CONFIG_GRETH_FIFO4 - if {$tmpvar_29 == "4"} then {set CONFIG_GRETH_FIFO4 1} else {set CONFIG_GRETH_FIFO4 0} - global CONFIG_GRETH_FIFO8 - if {$tmpvar_29 == "8"} then {set CONFIG_GRETH_FIFO8 1} else {set CONFIG_GRETH_FIFO8 0} - global CONFIG_GRETH_FIFO16 - if {$tmpvar_29 == "16"} then {set CONFIG_GRETH_FIFO16 1} else {set CONFIG_GRETH_FIFO16 0} - global CONFIG_GRETH_FIFO32 - if {$tmpvar_29 == "32"} then {set CONFIG_GRETH_FIFO32 1} else {set CONFIG_GRETH_FIFO32 0} - global CONFIG_GRETH_FIFO64 - if {$tmpvar_29 == "64"} then {set CONFIG_GRETH_FIFO64 1} else {set CONFIG_GRETH_FIFO64 0} -} - - -proc menu20 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 20} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 20]] - message $w.m -width 400 -aspect 300 -text \ - "CAN " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "CAN " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu21 .menu21 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 20 0 "Enable CAN interface " CONFIG_CAN_ENABLE - hex $w.config.f 20 1 "CAN I/O area start address (haddr\[19:8\]) " CONFIG_CANIO - int $w.config.f 20 2 "Interrupt number " CONFIG_CANIRQ - bool $w.config.f 20 3 "Enable loop-back testing " CONFIG_CANLOOP - bool $w.config.f 20 4 "Enable synchronous reset " CONFIG_CAN_SYNCRST - bool $w.config.f 20 5 "Enable FT FIFO memory " CONFIG_CAN_FT - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu20 {} { - global CONFIG_CAN_ENABLE - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {.menu20.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x1.l configure -state normal; } else {.menu20.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x1.l configure -state disabled} - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {.menu20.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x2.l configure -state normal; } else {.menu20.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x2.l configure -state disabled} - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x3 normal {n l y}} else {configure_entry .menu20.config.f.x3 disabled {y n l}} - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x4 normal {n l y}} else {configure_entry .menu20.config.f.x4 disabled {y n l}} - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x5 normal {n l y}} else {configure_entry .menu20.config.f.x5 disabled {y n l}} -} - - -proc update_define_menu20 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_CAN_ENABLE - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {validate_hex CONFIG_CANIO "$CONFIG_CANIO" C00} - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {validate_int CONFIG_CANIRQ "$CONFIG_CANIRQ" 13} - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CANLOOP [expr $CONFIG_CANLOOP&15]} else {set CONFIG_CANLOOP [expr $CONFIG_CANLOOP|16]} - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CAN_SYNCRST [expr $CONFIG_CAN_SYNCRST&15]} else {set CONFIG_CAN_SYNCRST [expr $CONFIG_CAN_SYNCRST|16]} - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CAN_FT [expr $CONFIG_CAN_FT&15]} else {set CONFIG_CAN_FT [expr $CONFIG_CAN_FT|16]} -} - - -proc menu21 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 21} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 21]] - message $w.m -width 400 -aspect 300 -text \ - "PCI " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "PCI " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu22 .menu22 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 21 0 "PCI interface, target-only " CONFIG_PCI_SIMPLE_TARGET - bool $w.config.f 21 1 "PCI interface, master-target " CONFIG_PCI_MASTER_TARGET - bool $w.config.f 21 2 "PCI DMA controller " CONFIG_PCI_MASTER_TARGET_DMA - hex $w.config.f 21 3 "PCI vendor ID" CONFIG_PCI_VENDORID - hex $w.config.f 21 4 "PCI device ID" CONFIG_PCI_DEVICEID - global tmpvar_30 - minimenu $w.config.f 21 5 "PCI FIFO depth" tmpvar_30 CONFIG_PCI_FIFO0 - menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"PCI FIFO depth\"" - $w.config.f.x5.x.menu add radiobutton -label "None" -variable tmpvar_30 -value "None" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "8" -variable tmpvar_30 -value "8" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "16" -variable tmpvar_30 -value "16" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "32" -variable tmpvar_30 -value "32" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_30 -value "64" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "128" -variable tmpvar_30 -value "128" -command "update_active" - menusplit $w $w.config.f.x5.x.menu 6 - hex $w.config.f 21 6 "PCI initiator address (haddr\[31:20\]) " CONFIG_PCI_HADDR - bool $w.config.f 21 7 "PCI arbiter " CONFIG_PCI_ARBITER - bool $w.config.f 21 8 "PCI arbiter APB interface " CONFIG_PCI_ARBITER_APB - int $w.config.f 21 9 "Number of PCI REQ/GNT pairs" CONFIG_PCI_ARBITER_NREQ - bool $w.config.f 21 10 "Enable PCI trace buffer " CONFIG_PCI_TRACE - global tmpvar_31 - minimenu $w.config.f 21 11 "PCI trace buffer depth" tmpvar_31 CONFIG_PCI_TRACE256 - menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"PCI trace buffer depth\"" - $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_31 -value "256" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "512" -variable tmpvar_31 -value "512" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "1024" -variable tmpvar_31 -value "1024" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "2048" -variable tmpvar_31 -value "2048" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "4096" -variable tmpvar_31 -value "4096" -command "update_active" - menusplit $w $w.config.f.x11.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu21 {} { - global CONFIG_PCI_ACTEL - global CONFIG_PCI_SIMPLE_TARGET - if {($CONFIG_PCI_ACTEL != 1)} then { - configure_entry .menu21.config.f.x0 normal {n l y}} else {configure_entry .menu21.config.f.x0 disabled {y n l}} - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then { - configure_entry .menu21.config.f.x1 normal {n l y}} else {configure_entry .menu21.config.f.x1 disabled {y n l}} - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then { - configure_entry .menu21.config.f.x2 normal {n l y}} else {configure_entry .menu21.config.f.x2 disabled {y n l}} - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x3.l configure -state normal; } else {.menu21.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x3.l configure -state disabled} - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x4.l configure -state normal; } else {.menu21.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x4.l configure -state disabled} - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {configure_entry .menu21.config.f.x5 normal {x l}} else {configure_entry .menu21.config.f.x5 disabled {x l}} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x6.l configure -state normal; } else {.menu21.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x6.l configure -state disabled} - global CONFIG_PCI_ARBITER - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then { - configure_entry .menu21.config.f.x8 normal {n l y}} else {configure_entry .menu21.config.f.x8 disabled {y n l}} - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {.menu21.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x9.l configure -state normal; } else {.menu21.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x9.l configure -state disabled} - global CONFIG_PCI_TRACE - if {($CONFIG_PCI_TRACE == 1)} then {configure_entry .menu21.config.f.x11 normal {x l}} else {configure_entry .menu21.config.f.x11 disabled {x l}} -} - - -proc update_define_menu21 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_PCI_ACTEL - global CONFIG_PCI_SIMPLE_TARGET - if {($CONFIG_PCI_ACTEL != 1)} then { - set CONFIG_PCI_SIMPLE_TARGET [expr $CONFIG_PCI_SIMPLE_TARGET&15]} else {set CONFIG_PCI_SIMPLE_TARGET [expr $CONFIG_PCI_SIMPLE_TARGET|16]} - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then { - set CONFIG_PCI_MASTER_TARGET [expr $CONFIG_PCI_MASTER_TARGET&15]} else {set CONFIG_PCI_MASTER_TARGET [expr $CONFIG_PCI_MASTER_TARGET|16]} - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then { - set CONFIG_PCI_MASTER_TARGET_DMA [expr $CONFIG_PCI_MASTER_TARGET_DMA&15]} else {set CONFIG_PCI_MASTER_TARGET_DMA [expr $CONFIG_PCI_MASTER_TARGET_DMA|16]} - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_VENDORID "$CONFIG_PCI_VENDORID" 1AC8} - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_DEVICEID "$CONFIG_PCI_DEVICEID" 0054} - global tmpvar_30 - global CONFIG_PCI_FIFO0 - if {$tmpvar_30 == "None"} then {set CONFIG_PCI_FIFO0 1} else {set CONFIG_PCI_FIFO0 0} - global CONFIG_PCI_FIFO8 - if {$tmpvar_30 == "8"} then {set CONFIG_PCI_FIFO8 1} else {set CONFIG_PCI_FIFO8 0} - global CONFIG_PCI_FIFO16 - if {$tmpvar_30 == "16"} then {set CONFIG_PCI_FIFO16 1} else {set CONFIG_PCI_FIFO16 0} - global CONFIG_PCI_FIFO32 - if {$tmpvar_30 == "32"} then {set CONFIG_PCI_FIFO32 1} else {set CONFIG_PCI_FIFO32 0} - global CONFIG_PCI_FIFO64 - if {$tmpvar_30 == "64"} then {set CONFIG_PCI_FIFO64 1} else {set CONFIG_PCI_FIFO64 0} - global CONFIG_PCI_FIFO128 - if {$tmpvar_30 == "128"} then {set CONFIG_PCI_FIFO128 1} else {set CONFIG_PCI_FIFO128 0} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_HADDR "$CONFIG_PCI_HADDR" E00} - global CONFIG_PCI_ARBITER - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then { - set CONFIG_PCI_ARBITER_APB [expr $CONFIG_PCI_ARBITER_APB&15]} else {set CONFIG_PCI_ARBITER_APB [expr $CONFIG_PCI_ARBITER_APB|16]} - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {validate_int CONFIG_PCI_ARBITER_NREQ "$CONFIG_PCI_ARBITER_NREQ" 4} - global tmpvar_31 - global CONFIG_PCI_TRACE256 - if {$tmpvar_31 == "256"} then {set CONFIG_PCI_TRACE256 1} else {set CONFIG_PCI_TRACE256 0} - global CONFIG_PCI_TRACE512 - if {$tmpvar_31 == "512"} then {set CONFIG_PCI_TRACE512 1} else {set CONFIG_PCI_TRACE512 0} - global CONFIG_PCI_TRACE1024 - if {$tmpvar_31 == "1024"} then {set CONFIG_PCI_TRACE1024 1} else {set CONFIG_PCI_TRACE1024 0} - global CONFIG_PCI_TRACE2048 - if {$tmpvar_31 == "2048"} then {set CONFIG_PCI_TRACE2048 1} else {set CONFIG_PCI_TRACE2048 0} - global CONFIG_PCI_TRACE4096 - if {$tmpvar_31 == "4096"} then {set CONFIG_PCI_TRACE4096 1} else {set CONFIG_PCI_TRACE4096 0} -} - - -proc menu22 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 22} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 22]] - message $w.m -width 400 -aspect 300 -text \ - "Spacewire " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Spacewire " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu23 .menu23 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 22 0 "Enable Spacewire links " CONFIG_SPW_ENABLE - int $w.config.f 22 1 "Number of links (1 - 3)" CONFIG_SPW_NUM - global tmpvar_32 - minimenu $w.config.f 22 2 "AHB RX/TX FIFO size (32-bit words) " tmpvar_32 CONFIG_SPW_AHBFIFO4 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB RX/TX FIFO size (32-bit words) \"" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_32 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_32 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_32 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_32 -value "32" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 4 - global tmpvar_33 - minimenu $w.config.f 22 3 "Receiver FIFO size (bytes) " tmpvar_33 CONFIG_SPW_RXFIFO16 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Receiver FIFO size (bytes) \"" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_33 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_33 -value "32" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "64" -variable tmpvar_33 -value "64" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 3 - bool $w.config.f 22 4 "Enable RMAP protocol " CONFIG_SPW_RMAP - global tmpvar_34 - minimenu $w.config.f 22 5 "RMAP buffer size (bytes) " tmpvar_34 CONFIG_SPW_RMAPBUF2 - menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"RMAP buffer size (bytes) \"" - $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_34 -value "64" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "128" -variable tmpvar_34 -value "128" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "192" -variable tmpvar_34 -value "192" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "256" -variable tmpvar_34 -value "256" -command "update_active" - menusplit $w $w.config.f.x5.x.menu 4 - bool $w.config.f 22 6 "Enable RMAP CRC check " CONFIG_SPW_RMAPCRC - bool $w.config.f 22 7 "Enable Rx unaligned transfers " CONFIG_SPW_RXUNAL - bool $w.config.f 22 8 "Spacewire FIFO protection " CONFIG_SPW_FT - bool $w.config.f 22 9 "Use GRSPWC netlist " CONFIG_SPW_NETLIST - global tmpvar_35 - minimenu $w.config.f 22 10 "Select GRSPW core (GRSPW1/GRSPW2) " tmpvar_35 CONFIG_SPW_GRSPW1 - menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Select GRSPW core (GRSPW1/GRSPW2) \"" - $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_35 -value "1" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_35 -value "2" -command "update_active" - menusplit $w $w.config.f.x10.x.menu 2 - int $w.config.f 22 11 "Number of DMA channels (1 - 4)" CONFIG_SPW_DMACHAN - int $w.config.f 22 12 "Number of ports (1 - 2)" CONFIG_SPW_PORTS - bool $w.config.f 22 13 "Receiver and transmitter uses same clock " CONFIG_SPW_RTSAME - global tmpvar_36 - minimenu $w.config.f 22 14 "Select receiver clock type " tmpvar_36 CONFIG_SPW_RX_SDR - menu $w.config.f.x14.x.menu -tearoffcommand "menutitle \"Select receiver clock type \"" - $w.config.f.x14.x.menu add radiobutton -label "SDR" -variable tmpvar_36 -value "SDR" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "DDR" -variable tmpvar_36 -value "DDR" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "Xor" -variable tmpvar_36 -value "Xor" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "Aeroflex" -variable tmpvar_36 -value "Aeroflex" -command "update_active" - menusplit $w $w.config.f.x14.x.menu 4 - global tmpvar_37 - minimenu $w.config.f 22 15 "Select transmitter clock type " tmpvar_37 CONFIG_SPW_TX_SDR - menu $w.config.f.x15.x.menu -tearoffcommand "menutitle \"Select transmitter clock type \"" - $w.config.f.x15.x.menu add radiobutton -label "SDR" -variable tmpvar_37 -value "SDR" -command "update_active" - $w.config.f.x15.x.menu add radiobutton -label "DDR" -variable tmpvar_37 -value "DDR" -command "update_active" - $w.config.f.x15.x.menu add radiobutton -label "Aeroflex" -variable tmpvar_37 -value "Aeroflex" -command "update_active" - menusplit $w $w.config.f.x15.x.menu 3 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu22 {} { - global CONFIG_SPW_ENABLE - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {.menu22.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x1.l configure -state normal; } else {.menu22.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x1.l configure -state disabled} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x2 normal {x l}} else {configure_entry .menu22.config.f.x2 disabled {x l}} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x3 normal {x l}} else {configure_entry .menu22.config.f.x3 disabled {x l}} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x4 normal {n l y}} else {configure_entry .menu22.config.f.x4 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_RMAP == 1)} then {configure_entry .menu22.config.f.x5 normal {x l}} else {configure_entry .menu22.config.f.x5 disabled {x l}} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x6 normal {n l y}} else {configure_entry .menu22.config.f.x6 disabled {y n l}} - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x7 normal {n l y}} else {configure_entry .menu22.config.f.x7 disabled {y n l}} - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x8 normal {n l y}} else {configure_entry .menu22.config.f.x8 disabled {y n l}} - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x9 normal {n l y}} else {configure_entry .menu22.config.f.x9 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x10 normal {x l}} else {configure_entry .menu22.config.f.x10 disabled {x l}} - global CONFIG_SPW_GRSPW2 - global CONFIG_SPW_DMACHAN - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {.menu22.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x11.l configure -state normal; } else {.menu22.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x11.l configure -state disabled} - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {.menu22.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x12.l configure -state normal; } else {.menu22.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x12.l configure -state disabled} - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - configure_entry .menu22.config.f.x13 normal {n l y}} else {configure_entry .menu22.config.f.x13 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {configure_entry .menu22.config.f.x14 normal {x l}} else {configure_entry .menu22.config.f.x14 disabled {x l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {configure_entry .menu22.config.f.x15 normal {x l}} else {configure_entry .menu22.config.f.x15 disabled {x l}} -} - - -proc update_define_menu22 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SPW_ENABLE - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {validate_int CONFIG_SPW_NUM "$CONFIG_SPW_NUM" 1} - global tmpvar_32 - global CONFIG_SPW_AHBFIFO4 - if {$tmpvar_32 == "4"} then {set CONFIG_SPW_AHBFIFO4 1} else {set CONFIG_SPW_AHBFIFO4 0} - global CONFIG_SPW_AHBFIFO8 - if {$tmpvar_32 == "8"} then {set CONFIG_SPW_AHBFIFO8 1} else {set CONFIG_SPW_AHBFIFO8 0} - global CONFIG_SPW_AHBFIFO16 - if {$tmpvar_32 == "16"} then {set CONFIG_SPW_AHBFIFO16 1} else {set CONFIG_SPW_AHBFIFO16 0} - global CONFIG_SPW_AHBFIFO32 - if {$tmpvar_32 == "32"} then {set CONFIG_SPW_AHBFIFO32 1} else {set CONFIG_SPW_AHBFIFO32 0} - global tmpvar_33 - global CONFIG_SPW_RXFIFO16 - if {$tmpvar_33 == "16"} then {set CONFIG_SPW_RXFIFO16 1} else {set CONFIG_SPW_RXFIFO16 0} - global CONFIG_SPW_RXFIFO32 - if {$tmpvar_33 == "32"} then {set CONFIG_SPW_RXFIFO32 1} else {set CONFIG_SPW_RXFIFO32 0} - global CONFIG_SPW_RXFIFO64 - if {$tmpvar_33 == "64"} then {set CONFIG_SPW_RXFIFO64 1} else {set CONFIG_SPW_RXFIFO64 0} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RMAP [expr $CONFIG_SPW_RMAP&15]} else {set CONFIG_SPW_RMAP [expr $CONFIG_SPW_RMAP|16]} - global tmpvar_34 - global CONFIG_SPW_RMAPBUF2 - if {$tmpvar_34 == "64"} then {set CONFIG_SPW_RMAPBUF2 1} else {set CONFIG_SPW_RMAPBUF2 0} - global CONFIG_SPW_RMAPBUF4 - if {$tmpvar_34 == "128"} then {set CONFIG_SPW_RMAPBUF4 1} else {set CONFIG_SPW_RMAPBUF4 0} - global CONFIG_SPW_RMAPBUF6 - if {$tmpvar_34 == "192"} then {set CONFIG_SPW_RMAPBUF6 1} else {set CONFIG_SPW_RMAPBUF6 0} - global CONFIG_SPW_RMAPBUF8 - if {$tmpvar_34 == "256"} then {set CONFIG_SPW_RMAPBUF8 1} else {set CONFIG_SPW_RMAPBUF8 0} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RMAPCRC [expr $CONFIG_SPW_RMAPCRC&15]} else {set CONFIG_SPW_RMAPCRC [expr $CONFIG_SPW_RMAPCRC|16]} - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RXUNAL [expr $CONFIG_SPW_RXUNAL&15]} else {set CONFIG_SPW_RXUNAL [expr $CONFIG_SPW_RXUNAL|16]} - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_FT [expr $CONFIG_SPW_FT&15]} else {set CONFIG_SPW_FT [expr $CONFIG_SPW_FT|16]} - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_NETLIST [expr $CONFIG_SPW_NETLIST&15]} else {set CONFIG_SPW_NETLIST [expr $CONFIG_SPW_NETLIST|16]} - global tmpvar_35 - global CONFIG_SPW_GRSPW1 - if {$tmpvar_35 == "1"} then {set CONFIG_SPW_GRSPW1 1} else {set CONFIG_SPW_GRSPW1 0} - global CONFIG_SPW_GRSPW2 - if {$tmpvar_35 == "2"} then {set CONFIG_SPW_GRSPW2 1} else {set CONFIG_SPW_GRSPW2 0} - global CONFIG_SPW_DMACHAN - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {validate_int CONFIG_SPW_DMACHAN "$CONFIG_SPW_DMACHAN" 1} - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {validate_int CONFIG_SPW_PORTS "$CONFIG_SPW_PORTS" 1} - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - set CONFIG_SPW_RTSAME [expr $CONFIG_SPW_RTSAME&15]} else {set CONFIG_SPW_RTSAME [expr $CONFIG_SPW_RTSAME|16]} - global tmpvar_36 - global CONFIG_SPW_RX_SDR - if {$tmpvar_36 == "SDR"} then {set CONFIG_SPW_RX_SDR 1} else {set CONFIG_SPW_RX_SDR 0} - global CONFIG_SPW_RX_DDR - if {$tmpvar_36 == "DDR"} then {set CONFIG_SPW_RX_DDR 1} else {set CONFIG_SPW_RX_DDR 0} - global CONFIG_SPW_RX_XOR - if {$tmpvar_36 == "Xor"} then {set CONFIG_SPW_RX_XOR 1} else {set CONFIG_SPW_RX_XOR 0} - global CONFIG_SPW_RX_AFLEX - if {$tmpvar_36 == "Aeroflex"} then {set CONFIG_SPW_RX_AFLEX 1} else {set CONFIG_SPW_RX_AFLEX 0} - global tmpvar_37 - global CONFIG_SPW_TX_SDR - if {$tmpvar_37 == "SDR"} then {set CONFIG_SPW_TX_SDR 1} else {set CONFIG_SPW_TX_SDR 0} - global CONFIG_SPW_TX_DDR - if {$tmpvar_37 == "DDR"} then {set CONFIG_SPW_TX_DDR 1} else {set CONFIG_SPW_TX_DDR 0} - global CONFIG_SPW_TX_AFLEX - if {$tmpvar_37 == "Aeroflex"} then {set CONFIG_SPW_TX_AFLEX 1} else {set CONFIG_SPW_TX_AFLEX 0} -} - - -proc menu23 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 23} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 23]] - message $w.m -width 400 -aspect 300 -text \ - "UARTs, timers and irq control " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "UARTs, timers and irq control " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 23; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 23; catch {destroy .menu13}; unregister_active 13; menu24 .menu24 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 23 0 "Enable console UART " CONFIG_UART1_ENABLE - global tmpvar_38 - minimenu $w.config.f 23 1 "UART1 FIFO depth" tmpvar_38 CONFIG_UA1_FIFO1 - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"UART1 FIFO depth\"" - $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_38 -value "1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_38 -value "2" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_38 -value "4" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_38 -value "8" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_38 -value "16" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_38 -value "32" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 6 - bool $w.config.f 23 2 "Enable secondary UART " CONFIG_UART2_ENABLE - global tmpvar_39 - minimenu $w.config.f 23 3 "UART2 FIFO depth" tmpvar_39 CONFIG_UA2_FIFO1 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"UART2 FIFO depth\"" - $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_39 -value "1" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_39 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_39 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_39 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_39 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_39 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 6 - bool $w.config.f 23 4 "Enable LEON3 interrupt controller " CONFIG_IRQ3_ENABLE - bool $w.config.f 23 5 "Enable secondary interrupts " CONFIG_IRQ3_SEC - int $w.config.f 23 6 "Secondary interrupt number (1 - 15) " CONFIG_IRQ3_NSEC - bool $w.config.f 23 7 "Enable Timer Unit " CONFIG_GPT_ENABLE - int $w.config.f 23 8 "Number of timers (1 - 7) " CONFIG_GPT_NTIM - int $w.config.f 23 9 "Scaler width (2 - 16) " CONFIG_GPT_SW - int $w.config.f 23 10 "Timer width (2 - 32) " CONFIG_GPT_TW - int $w.config.f 23 11 "Timer unit interrupt " CONFIG_GPT_IRQ - bool $w.config.f 23 12 "Separate interrupts " CONFIG_GPT_SEPIRQ - bool $w.config.f 23 13 "Watchdog enable " CONFIG_GPT_WDOGEN - hex $w.config.f 23 14 "Initial watchdog time-out value " CONFIG_GPT_WDOG - bool $w.config.f 23 15 "Enable generic GPIO port " CONFIG_GRGPIO_ENABLE - int $w.config.f 23 16 "GPIO width " CONFIG_GRGPIO_WIDTH - hex $w.config.f 23 17 "GPIO interrupt mask " CONFIG_GRGPIO_IMASK - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu23 {} { - global CONFIG_UART1_ENABLE - if {($CONFIG_UART1_ENABLE == 1)} then {configure_entry .menu23.config.f.x1 normal {x l}} else {configure_entry .menu23.config.f.x1 disabled {x l}} - global CONFIG_UART2_ENABLE - if {($CONFIG_UART2_ENABLE == 1)} then {configure_entry .menu23.config.f.x3 normal {x l}} else {configure_entry .menu23.config.f.x3 disabled {x l}} - global CONFIG_IRQ3_ENABLE - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then { - configure_entry .menu23.config.f.x5 normal {n l y}} else {configure_entry .menu23.config.f.x5 disabled {y n l}} - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {.menu23.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x6.l configure -state normal; } else {.menu23.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x6.l configure -state disabled} - global CONFIG_GPT_ENABLE - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x8.l configure -state normal; } else {.menu23.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x8.l configure -state disabled} - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x9.l configure -state normal; } else {.menu23.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x9.l configure -state disabled} - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x10.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x10.l configure -state normal; } else {.menu23.config.f.x10.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x10.l configure -state disabled} - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x11.l configure -state normal; } else {.menu23.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x11.l configure -state disabled} - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then { - configure_entry .menu23.config.f.x12 normal {n l y}} else {configure_entry .menu23.config.f.x12 disabled {y n l}} - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then { - configure_entry .menu23.config.f.x13 normal {n l y}} else {configure_entry .menu23.config.f.x13 disabled {y n l}} - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {.menu23.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x14.l configure -state normal; } else {.menu23.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x14.l configure -state disabled} - global CONFIG_GRGPIO_ENABLE - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu23.config.f.x16.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x16.l configure -state normal; } else {.menu23.config.f.x16.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x16.l configure -state disabled} - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu23.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x17.l configure -state normal; } else {.menu23.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x17.l configure -state disabled} -} - - -proc update_define_menu23 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_38 - global CONFIG_UA1_FIFO1 - if {$tmpvar_38 == "1"} then {set CONFIG_UA1_FIFO1 1} else {set CONFIG_UA1_FIFO1 0} - global CONFIG_UA1_FIFO2 - if {$tmpvar_38 == "2"} then {set CONFIG_UA1_FIFO2 1} else {set CONFIG_UA1_FIFO2 0} - global CONFIG_UA1_FIFO4 - if {$tmpvar_38 == "4"} then {set CONFIG_UA1_FIFO4 1} else {set CONFIG_UA1_FIFO4 0} - global CONFIG_UA1_FIFO8 - if {$tmpvar_38 == "8"} then {set CONFIG_UA1_FIFO8 1} else {set CONFIG_UA1_FIFO8 0} - global CONFIG_UA1_FIFO16 - if {$tmpvar_38 == "16"} then {set CONFIG_UA1_FIFO16 1} else {set CONFIG_UA1_FIFO16 0} - global CONFIG_UA1_FIFO32 - if {$tmpvar_38 == "32"} then {set CONFIG_UA1_FIFO32 1} else {set CONFIG_UA1_FIFO32 0} - global tmpvar_39 - global CONFIG_UA2_FIFO1 - if {$tmpvar_39 == "1"} then {set CONFIG_UA2_FIFO1 1} else {set CONFIG_UA2_FIFO1 0} - global CONFIG_UA2_FIFO2 - if {$tmpvar_39 == "2"} then {set CONFIG_UA2_FIFO2 1} else {set CONFIG_UA2_FIFO2 0} - global CONFIG_UA2_FIFO4 - if {$tmpvar_39 == "4"} then {set CONFIG_UA2_FIFO4 1} else {set CONFIG_UA2_FIFO4 0} - global CONFIG_UA2_FIFO8 - if {$tmpvar_39 == "8"} then {set CONFIG_UA2_FIFO8 1} else {set CONFIG_UA2_FIFO8 0} - global CONFIG_UA2_FIFO16 - if {$tmpvar_39 == "16"} then {set CONFIG_UA2_FIFO16 1} else {set CONFIG_UA2_FIFO16 0} - global CONFIG_UA2_FIFO32 - if {$tmpvar_39 == "32"} then {set CONFIG_UA2_FIFO32 1} else {set CONFIG_UA2_FIFO32 0} - global CONFIG_IRQ3_ENABLE - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then { - set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC&15]} else {set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC|16]} - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {validate_int CONFIG_IRQ3_NSEC "$CONFIG_IRQ3_NSEC" 12} - global CONFIG_GPT_ENABLE - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_NTIM "$CONFIG_GPT_NTIM" 2} - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_SW "$CONFIG_GPT_SW" 8} - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_TW "$CONFIG_GPT_TW" 32} - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_IRQ "$CONFIG_GPT_IRQ" 8} - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then { - set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ&15]} else {set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ|16]} - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then { - set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN&15]} else {set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN|16]} - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {validate_hex CONFIG_GPT_WDOG "$CONFIG_GPT_WDOG" FFFF} - global CONFIG_GRGPIO_ENABLE - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_int CONFIG_GRGPIO_WIDTH "$CONFIG_GRGPIO_WIDTH" 8} - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_hex CONFIG_GRGPIO_IMASK "$CONFIG_GRGPIO_IMASK" 0000} -} - - -menu_option menu24 24 "VHDL Debugging " -proc menu24 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 24} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 24]] - message $w.m -width 400 -aspect 300 -text \ - "VHDL Debugging " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "VHDL Debugging " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 24; break" - set nextscript "catch {focus $oldFocus}; menu25 .menu25 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - $w.f.next configure -state disabled - bind all "puts \"no more menus\" " - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 24 0 "Accelerated UART tracing " CONFIG_DEBUG_UART - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu24 {} { -} - - -proc update_define_menu24 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc update_mainmenu {} { -} - - -set tmpvar_0 "(not set)" -set CONFIG_SYN_INFERRED 0 -set CONFIG_SYN_STRATIX 0 -set CONFIG_SYN_STRATIXII 0 -set CONFIG_SYN_STRATIXIII 0 -set CONFIG_SYN_CYCLONEIII 0 -set CONFIG_SYN_ALTERA 0 -set CONFIG_SYN_AXCEL 0 -set CONFIG_SYN_PROASIC 0 -set CONFIG_SYN_PROASICPLUS 0 -set CONFIG_SYN_PROASIC3 0 -set CONFIG_SYN_UT025CRH 0 -set CONFIG_SYN_ATC18 0 -set CONFIG_SYN_ATC18RHA 0 -set CONFIG_SYN_CUSTOM1 0 -set CONFIG_SYN_EASIC90 0 -set CONFIG_SYN_IHP25 0 -set CONFIG_SYN_IHP25RH 0 -set CONFIG_SYN_LATTICE 0 -set CONFIG_SYN_ECLIPSE 0 -set CONFIG_SYN_PEREGRINE 0 -set CONFIG_SYN_RH_LIB18T 0 -set CONFIG_SYN_RHUMC 0 -set CONFIG_SYN_SMIC13 0 -set CONFIG_SYN_SPARTAN2 0 -set CONFIG_SYN_SPARTAN3 0 -set CONFIG_SYN_SPARTAN3E 0 -set CONFIG_SYN_VIRTEX 0 -set CONFIG_SYN_VIRTEXE 0 -set CONFIG_SYN_VIRTEX2 0 -set CONFIG_SYN_VIRTEX4 0 -set CONFIG_SYN_VIRTEX5 0 -set CONFIG_SYN_UMC 0 -set CONFIG_SYN_TSMC90 0 -set tmpvar_1 "(not set)" -set CONFIG_MEM_INFERRED 0 -set CONFIG_MEM_UMC 0 -set CONFIG_MEM_RHUMC 0 -set CONFIG_MEM_ARTISAN 0 -set CONFIG_MEM_CUSTOM1 0 -set CONFIG_MEM_VIRAGE 0 -set CONFIG_MEM_VIRAGE90 0 -set CONFIG_SYN_INFER_RAM 0 -set CONFIG_SYN_INFER_PADS 0 -set CONFIG_SYN_NO_ASYNC 0 -set CONFIG_SYN_SCAN 0 -set tmpvar_2 "(not set)" -set CONFIG_CLK_INFERRED 0 -set CONFIG_CLK_HCLKBUF 0 -set CONFIG_CLK_ALTDLL 0 -set CONFIG_CLK_LATDLL 0 -set CONFIG_CLK_PRO3PLL 0 -set CONFIG_CLK_LIB18T 0 -set CONFIG_CLK_RHUMC 0 -set CONFIG_CLK_CLKDLL 0 -set CONFIG_CLK_DCM 0 -set CONFIG_CLK_MUL 2 -set CONFIG_CLK_DIV 2 -set CONFIG_OCLK_DIV 2 -set CONFIG_PCI_CLKDLL 0 -set CONFIG_CLK_NOFB 0 -set CONFIG_PCI_SYSCLK 0 -set CONFIG_LEON3 0 -set CONFIG_PROC_NUM 1 -set CONFIG_IU_NWINDOWS 8 -set CONFIG_IU_V8MULDIV 0 -set tmpvar_3 "(not set)" -set CONFIG_IU_MUL_LATENCY_2 0 -set CONFIG_IU_MUL_LATENCY_4 0 -set CONFIG_IU_MUL_LATENCY_5 0 -set CONFIG_IU_MUL_MAC 0 -set CONFIG_IU_SVT 0 -set CONFIG_IU_LDELAY 1 -set CONFIG_IU_WATCHPOINTS 0 -set CONFIG_PWD 0 -set CONFIG_IU_RSTADDR 00000 -set CONFIG_FPU_ENABLE 0 -set tmpvar_4 "(not set)" -set CONFIG_FPU_GRFPU 0 -set CONFIG_FPU_GRFPULITE 0 -set CONFIG_FPU_MEIKO 0 -set tmpvar_5 "(not set)" -set CONFIG_FPU_GRFPU_INFMUL 0 -set CONFIG_FPU_GRFPU_DWMUL 0 -set CONFIG_FPU_GRFPU_MODGEN 0 -set tmpvar_6 "(not set)" -set CONFIG_FPU_GRFPC0 0 -set CONFIG_FPU_GRFPC1 0 -set CONFIG_FPU_GRFPC2 0 -set CONFIG_FPU_NETLIST 0 -set CONFIG_ICACHE_ENABLE 0 -set tmpvar_7 "(not set)" -set CONFIG_ICACHE_ASSO1 0 -set CONFIG_ICACHE_ASSO2 0 -set CONFIG_ICACHE_ASSO3 0 -set CONFIG_ICACHE_ASSO4 0 -set tmpvar_8 "(not set)" -set CONFIG_ICACHE_SZ1 0 -set CONFIG_ICACHE_SZ2 0 -set CONFIG_ICACHE_SZ4 0 -set CONFIG_ICACHE_SZ8 0 -set CONFIG_ICACHE_SZ16 0 -set CONFIG_ICACHE_SZ32 0 -set CONFIG_ICACHE_SZ64 0 -set CONFIG_ICACHE_SZ128 0 -set CONFIG_ICACHE_SZ256 0 -set tmpvar_9 "(not set)" -set CONFIG_ICACHE_LZ16 0 -set CONFIG_ICACHE_LZ32 0 -set tmpvar_10 "(not set)" -set CONFIG_ICACHE_ALGORND 0 -set CONFIG_ICACHE_ALGOLRR 0 -set CONFIG_ICACHE_ALGOLRU 0 -set CONFIG_ICACHE_LOCK 0 -set CONFIG_ICACHE_LRAM 0 -set tmpvar_11 "(not set)" -set CONFIG_ICACHE_LRAM_SZ1 0 -set CONFIG_ICACHE_LRAM_SZ2 0 -set CONFIG_ICACHE_LRAM_SZ4 0 -set CONFIG_ICACHE_LRAM_SZ8 0 -set CONFIG_ICACHE_LRAM_SZ16 0 -set CONFIG_ICACHE_LRAM_SZ32 0 -set CONFIG_ICACHE_LRAM_SZ64 0 -set CONFIG_ICACHE_LRAM_SZ128 0 -set CONFIG_ICACHE_LRAM_SZ256 0 -set CONFIG_ICACHE_LRSTART 8e -set CONFIG_DCACHE_ENABLE 0 -set tmpvar_12 "(not set)" -set CONFIG_DCACHE_ASSO1 0 -set CONFIG_DCACHE_ASSO2 0 -set CONFIG_DCACHE_ASSO3 0 -set CONFIG_DCACHE_ASSO4 0 -set tmpvar_13 "(not set)" -set CONFIG_DCACHE_SZ1 0 -set CONFIG_DCACHE_SZ2 0 -set CONFIG_DCACHE_SZ4 0 -set CONFIG_DCACHE_SZ8 0 -set CONFIG_DCACHE_SZ16 0 -set CONFIG_DCACHE_SZ32 0 -set CONFIG_DCACHE_SZ64 0 -set CONFIG_DCACHE_SZ128 0 -set CONFIG_DCACHE_SZ256 0 -set tmpvar_14 "(not set)" -set CONFIG_DCACHE_LZ16 0 -set CONFIG_DCACHE_LZ32 0 -set tmpvar_15 "(not set)" -set CONFIG_DCACHE_ALGORND 0 -set CONFIG_DCACHE_ALGOLRR 0 -set CONFIG_DCACHE_ALGOLRU 0 -set CONFIG_DCACHE_LOCK 0 -set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 -set CONFIG_DCACHE_SNOOP_SEPTAG 0 -set CONFIG_CACHE_FIXED 0 -set CONFIG_DCACHE_LRAM 0 -set tmpvar_16 "(not set)" -set CONFIG_DCACHE_LRAM_SZ1 0 -set CONFIG_DCACHE_LRAM_SZ2 0 -set CONFIG_DCACHE_LRAM_SZ4 0 -set CONFIG_DCACHE_LRAM_SZ8 0 -set CONFIG_DCACHE_LRAM_SZ16 0 -set CONFIG_DCACHE_LRAM_SZ32 0 -set CONFIG_DCACHE_LRAM_SZ64 0 -set CONFIG_DCACHE_LRAM_SZ128 0 -set CONFIG_DCACHE_LRAM_SZ256 0 -set CONFIG_DCACHE_LRSTART 8f -set CONFIG_MMU_ENABLE 0 -set tmpvar_17 "(not set)" -set CONFIG_MMU_COMBINED 0 -set CONFIG_MMU_SPLIT 0 -set tmpvar_18 "(not set)" -set CONFIG_MMU_REPARRAY 0 -set CONFIG_MMU_REPINCREMENT 0 -set tmpvar_19 "(not set)" -set CONFIG_MMU_I2 0 -set CONFIG_MMU_I4 0 -set CONFIG_MMU_I8 0 -set CONFIG_MMU_I16 0 -set CONFIG_MMU_I32 0 -set tmpvar_20 "(not set)" -set CONFIG_MMU_D2 0 -set CONFIG_MMU_D4 0 -set CONFIG_MMU_D8 0 -set CONFIG_MMU_D16 0 -set CONFIG_MMU_D32 0 -set CONFIG_MMU_FASTWB 0 -set tmpvar_21 "(not set)" -set CONFIG_MMU_PAGE_4K 0 -set CONFIG_MMU_PAGE_8K 0 -set CONFIG_MMU_PAGE_16K 0 -set CONFIG_MMU_PAGE_32K 0 -set CONFIG_MMU_PAGE_PROG 0 -set CONFIG_DSU_ENABLE 0 -set CONFIG_DSU_ITRACE 0 -set tmpvar_22 "(not set)" -set CONFIG_DSU_ITRACESZ1 0 -set CONFIG_DSU_ITRACESZ2 0 -set CONFIG_DSU_ITRACESZ4 0 -set CONFIG_DSU_ITRACESZ8 0 -set CONFIG_DSU_ITRACESZ16 0 -set CONFIG_DSU_ATRACE 0 -set tmpvar_23 "(not set)" -set CONFIG_DSU_ATRACESZ1 0 -set CONFIG_DSU_ATRACESZ2 0 -set CONFIG_DSU_ATRACESZ4 0 -set CONFIG_DSU_ATRACESZ8 0 -set CONFIG_DSU_ATRACESZ16 0 -set CONFIG_IU_DISAS 0 -set CONFIG_IU_DISAS_NET 0 -set CONFIG_DEBUG_PC32 0 -set CONFIG_AHB_DEFMST 0 -set CONFIG_AHB_RROBIN 0 -set CONFIG_AHB_SPLIT 0 -set CONFIG_AHB_IOADDR FFF -set CONFIG_APB_HADDR 800 -set CONFIG_AHB_MON 0 -set CONFIG_AHB_MONERR 0 -set CONFIG_AHB_MONWAR 0 -set CONFIG_DSU_UART 0 -set CONFIG_DSU_JTAG 0 -set CONFIG_DSU_ETH 0 -set tmpvar_25 "(not set)" -set CONFIG_DSU_ETHSZ1 0 -set CONFIG_DSU_ETHSZ2 0 -set CONFIG_DSU_ETHSZ4 0 -set CONFIG_DSU_ETHSZ8 0 -set CONFIG_DSU_ETHSZ16 0 -set CONFIG_DSU_IPMSB C0A8 -set CONFIG_DSU_IPLSB 0033 -set CONFIG_DSU_ETHMSB 020000 -set CONFIG_DSU_ETHLSB 000000 -set CONFIG_DSU_ETH_PROG 0 -set CONFIG_SRCTRL 0 -set CONFIG_SRCTRL_8BIT 0 -set CONFIG_SRCTRL_PROMWS 3 -set CONFIG_SRCTRL_RAMWS 0 -set CONFIG_SRCTRL_IOWS 0 -set CONFIG_SRCTRL_RMW 0 -set tmpvar_26 "(not set)" -set CONFIG_SRCTRL_SRBANKS1 0 -set CONFIG_SRCTRL_SRBANKS2 0 -set CONFIG_SRCTRL_SRBANKS3 0 -set CONFIG_SRCTRL_SRBANKS4 0 -set CONFIG_SRCTRL_SRBANKS5 0 -set tmpvar_27 "(not set)" -set CONFIG_SRCTRL_BANKSZ0 0 -set CONFIG_SRCTRL_BANKSZ1 0 -set CONFIG_SRCTRL_BANKSZ2 0 -set CONFIG_SRCTRL_BANKSZ3 0 -set CONFIG_SRCTRL_BANKSZ4 0 -set CONFIG_SRCTRL_BANKSZ5 0 -set CONFIG_SRCTRL_BANKSZ6 0 -set CONFIG_SRCTRL_BANKSZ7 0 -set CONFIG_SRCTRL_BANKSZ8 0 -set CONFIG_SRCTRL_BANKSZ9 0 -set CONFIG_SRCTRL_BANKSZ10 0 -set CONFIG_SRCTRL_BANKSZ11 0 -set CONFIG_SRCTRL_BANKSZ12 0 -set CONFIG_SRCTRL_BANKSZ13 0 -set CONFIG_SRCTRL_ROMASEL 19 -set CONFIG_MCTRL_LEON2 0 -set CONFIG_MCTRL_8BIT 0 -set CONFIG_MCTRL_16BIT 0 -set CONFIG_MCTRL_5CS 0 -set CONFIG_MCTRL_SDRAM 0 -set CONFIG_MCTRL_SDRAM_SEPBUS 0 -set CONFIG_MCTRL_SDRAM_BUS64 0 -set CONFIG_MCTRL_SDRAM_INVCLK 0 -set CONFIG_MCTRL_PAGE 0 -set CONFIG_MCTRL_PROGPAGE 0 -set CONFIG_SDCTRL 0 -set CONFIG_SDCTRL_BUS64 0 -set CONFIG_SDCTRL_INVCLK 0 -set CONFIG_SDCTRL_PAGE 0 -set CONFIG_SDCTRL_PROGPAGE 0 -set CONFIG_AHBROM_ENABLE 0 -set CONFIG_AHBROM_START 000 -set CONFIG_AHBROM_PIPE 0 -set CONFIG_AHBRAM_ENABLE 0 -set tmpvar_28 "(not set)" -set CONFIG_AHBRAM_SZ1 0 -set CONFIG_AHBRAM_SZ2 0 -set CONFIG_AHBRAM_SZ4 0 -set CONFIG_AHBRAM_SZ8 0 -set CONFIG_AHBRAM_SZ16 0 -set CONFIG_AHBRAM_SZ32 0 -set CONFIG_AHBRAM_SZ64 0 -set CONFIG_AHBRAM_START A00 -set CONFIG_GRETH_ENABLE 0 -set CONFIG_GRETH_GIGA 0 -set tmpvar_29 "(not set)" -set CONFIG_GRETH_FIFO4 0 -set CONFIG_GRETH_FIFO8 0 -set CONFIG_GRETH_FIFO16 0 -set CONFIG_GRETH_FIFO32 0 -set CONFIG_GRETH_FIFO64 0 -set CONFIG_CAN_ENABLE 0 -set CONFIG_CANIO C00 -set CONFIG_CANIRQ 13 -set CONFIG_CANLOOP 0 -set CONFIG_CAN_SYNCRST 0 -set CONFIG_CAN_FT 0 -set CONFIG_PCI_SIMPLE_TARGET 0 -set CONFIG_PCI_MASTER_TARGET 0 -set CONFIG_PCI_MASTER_TARGET_DMA 0 -set CONFIG_PCI_VENDORID 1AC8 -set CONFIG_PCI_DEVICEID 0054 -set tmpvar_30 "(not set)" -set CONFIG_PCI_FIFO0 0 -set CONFIG_PCI_FIFO8 0 -set CONFIG_PCI_FIFO16 0 -set CONFIG_PCI_FIFO32 0 -set CONFIG_PCI_FIFO64 0 -set CONFIG_PCI_FIFO128 0 -set CONFIG_PCI_HADDR E00 -set CONFIG_PCI_ARBITER 0 -set CONFIG_PCI_ARBITER_APB 0 -set CONFIG_PCI_ARBITER_NREQ 4 -set CONFIG_PCI_TRACE 0 -set tmpvar_31 "(not set)" -set CONFIG_PCI_TRACE256 0 -set CONFIG_PCI_TRACE512 0 -set CONFIG_PCI_TRACE1024 0 -set CONFIG_PCI_TRACE2048 0 -set CONFIG_PCI_TRACE4096 0 -set CONFIG_SPW_ENABLE 0 -set CONFIG_SPW_NUM 1 -set tmpvar_32 "(not set)" -set CONFIG_SPW_AHBFIFO4 0 -set CONFIG_SPW_AHBFIFO8 0 -set CONFIG_SPW_AHBFIFO16 0 -set CONFIG_SPW_AHBFIFO32 0 -set tmpvar_33 "(not set)" -set CONFIG_SPW_RXFIFO16 0 -set CONFIG_SPW_RXFIFO32 0 -set CONFIG_SPW_RXFIFO64 0 -set CONFIG_SPW_RMAP 0 -set tmpvar_34 "(not set)" -set CONFIG_SPW_RMAPBUF2 0 -set CONFIG_SPW_RMAPBUF4 0 -set CONFIG_SPW_RMAPBUF6 0 -set CONFIG_SPW_RMAPBUF8 0 -set CONFIG_SPW_RMAPCRC 0 -set CONFIG_SPW_RXUNAL 0 -set CONFIG_SPW_FT 0 -set CONFIG_SPW_NETLIST 0 -set tmpvar_35 "(not set)" -set CONFIG_SPW_GRSPW1 0 -set CONFIG_SPW_GRSPW2 0 -set CONFIG_SPW_DMACHAN 1 -set CONFIG_SPW_PORTS 1 -set CONFIG_SPW_RTSAME 0 -set tmpvar_36 "(not set)" -set CONFIG_SPW_RX_SDR 0 -set CONFIG_SPW_RX_DDR 0 -set CONFIG_SPW_RX_XOR 0 -set CONFIG_SPW_RX_AFLEX 0 -set tmpvar_37 "(not set)" -set CONFIG_SPW_TX_SDR 0 -set CONFIG_SPW_TX_DDR 0 -set CONFIG_SPW_TX_AFLEX 0 -set CONFIG_UART1_ENABLE 0 -set tmpvar_38 "(not set)" -set CONFIG_UA1_FIFO1 0 -set CONFIG_UA1_FIFO2 0 -set CONFIG_UA1_FIFO4 0 -set CONFIG_UA1_FIFO8 0 -set CONFIG_UA1_FIFO16 0 -set CONFIG_UA1_FIFO32 0 -set CONFIG_UART2_ENABLE 0 -set tmpvar_39 "(not set)" -set CONFIG_UA2_FIFO1 0 -set CONFIG_UA2_FIFO2 0 -set CONFIG_UA2_FIFO4 0 -set CONFIG_UA2_FIFO8 0 -set CONFIG_UA2_FIFO16 0 -set CONFIG_UA2_FIFO32 0 -set CONFIG_IRQ3_ENABLE 0 -set CONFIG_IRQ3_SEC 0 -set CONFIG_IRQ3_NSEC 12 -set CONFIG_GPT_ENABLE 0 -set CONFIG_GPT_NTIM 2 -set CONFIG_GPT_SW 8 -set CONFIG_GPT_TW 32 -set CONFIG_GPT_IRQ 8 -set CONFIG_GPT_SEPIRQ 0 -set CONFIG_GPT_WDOGEN 0 -set CONFIG_GPT_WDOG FFFF -set CONFIG_GRGPIO_ENABLE 0 -set CONFIG_GRGPIO_WIDTH 8 -set CONFIG_GRGPIO_IMASK 0000 -set CONFIG_DEBUG_UART 0 -set CONFIG_SYN_ARTISAN 4 -set CONFIG_PCI_ENABLE 4 -set CONFIG_HAS_SHARED_GRFPU 4 -set CONFIG_FPU_GRFPU_SH 4 -set CONFIG_LEON3FT_PRESENT 4 -set CONFIG_LEON3FT_EN 4 -set CONFIG_IUFT_NONE 4 -set CONFIG_IUFT_PAR 4 -set CONFIG_IUFT_DMR 4 -set CONFIG_IUFT_BCH 4 -set CONFIG_IUFT_TMR 4 -set CONFIG_FPUFT_EN 4 -set CONFIG_RF_ERRINJ 4 -set CONFIG_CACHE_FT_EN 4 -set CONFIG_CACHE_ERRINJ 4 -set CONFIG_LEON3_NETLIST 4 -set CONFIG_PCI_ACTEL 4 -set CONFIG_MODULES 4 -proc writeconfig {file1 file2} { - set cfg [open $file1 w] - set autocfg [open $file2 w] - set notmod 1 - set notset 0 - puts $cfg "#" - puts $cfg "# Automatically generated make config: don't edit" - puts $cfg "#" - puts $autocfg "/*" - puts $autocfg " * Automatically generated C config: don't edit" - puts $autocfg " */" - puts $autocfg "#define AUTOCONF_INCLUDED" - write_comment $cfg $autocfg "Synthesis " - global tmpvar_0 - - if { $tmpvar_0 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-Stratix" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-StratixII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-StratixIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-CycloneIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-Others" } then { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Axcelerator" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Proasic" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-ProasicPlus" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Proasic3" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 0 [list $notmod] 2 } - if { $tmpvar_0 == "Aeroflex-UT025CRH" } then { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 0 [list $notmod] 2 } - if { $tmpvar_0 == "Atmel-ATC18" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 0 [list $notmod] 2 } - if { $tmpvar_0 == "Atmel-ATC18RHA" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 0 [list $notmod] 2 } - if { $tmpvar_0 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 0 [list $notmod] 2 } - if { $tmpvar_0 == "eASIC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 0 [list $notmod] 2 } - if { $tmpvar_0 == "IHP25" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 0 [list $notmod] 2 } - if { $tmpvar_0 == "IHP25RH" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 0 [list $notmod] 2 } - if { $tmpvar_0 == "Lattice-EC/ECP/XP" } then { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Quicklogic-Eclipse" } then { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Peregrine" } then { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 0 [list $notmod] 2 } - if { $tmpvar_0 == "RH-LIB18T" } then { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 0 [list $notmod] 2 } - if { $tmpvar_0 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_0 == "SMIC130" } then { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan2" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan3" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan3E" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-VirtexE" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex2" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex4" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex5" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 0 [list $notmod] 2 } - if { $tmpvar_0 == "UMC180" } then { write_tristate $cfg $autocfg CONFIG_SYN_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UMC 0 [list $notmod] 2 } - if { $tmpvar_0 == "TSMC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 0 [list $notmod] 2 } - global tmpvar_1 - global CONFIG_SYN_INFERRED - global CONFIG_SYN_CUSTOM1 - global CONFIG_SYN_ATC18 - global CONFIG_SYN_TSMC90 - global CONFIG_SYN_UMC - global CONFIG_SYN_RHUMC - global CONFIG_SYN_ARTISAN - if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then { - if { $tmpvar_1 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_1 == "UMC18" } then { write_tristate $cfg $autocfg CONFIG_MEM_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_UMC 0 [list $notmod] 2 } - if { $tmpvar_1 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_1 == "Artisan" } then { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 0 [list $notmod] 2 } - if { $tmpvar_1 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 0 [list $notmod] 2 } - if { $tmpvar_1 == "Virage" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 0 [list $notmod] 2 } - if { $tmpvar_1 == "Virage-TSMC90" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 0 [list $notmod] 2 }} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_RAM $CONFIG_SYN_INFER_RAM [list $notmod] 2 } - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_PADS $CONFIG_SYN_INFER_PADS [list $notmod] 2 } - global CONFIG_SYN_NO_ASYNC - write_tristate $cfg $autocfg CONFIG_SYN_NO_ASYNC $CONFIG_SYN_NO_ASYNC [list $notmod] 2 - global CONFIG_SYN_SCAN - write_tristate $cfg $autocfg CONFIG_SYN_SCAN $CONFIG_SYN_SCAN [list $notmod] 2 - write_comment $cfg $autocfg "Clock generation" - global tmpvar_2 - - if { $tmpvar_2 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_2 == "Actel-HCLKBUF" } then { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 0 [list $notmod] 2 } - if { $tmpvar_2 == "Altera-ALTPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Lattice-EXPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Proasic3-PLLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "RH-LIB18T-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 0 [list $notmod] 2 } - if { $tmpvar_2 == "DARE-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_2 == "Xilinx-CLKDLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Xilinx-DCM" } then { write_tristate $cfg $autocfg CONFIG_CLK_DCM 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_DCM 0 [list $notmod] 2 } - global CONFIG_CLK_MUL - global CONFIG_CLK_DCM - global CONFIG_CLK_ALTDLL - global CONFIG_CLK_LATDLL - global CONFIG_CLK_PRO3PLL - global CONFIG_CLK_CLKDLL - global CONFIG_CLK_LIB18T - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_MUL $CONFIG_CLK_MUL $notmod } - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_DIV $CONFIG_CLK_DIV $notmod } - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {write_int $cfg $autocfg CONFIG_OCLK_DIV $CONFIG_OCLK_DIV $notmod } - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_CLKDLL $CONFIG_PCI_CLKDLL [list $notmod] 2 } - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_CLK_NOFB $CONFIG_CLK_NOFB [list $notmod] 2 } - global CONFIG_PCI_SYSCLK - global CONFIG_PCI_ENABLE - if {($CONFIG_PCI_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SYSCLK $CONFIG_PCI_SYSCLK [list $notmod] 2 } - global CONFIG_LEON3 - write_tristate $cfg $autocfg CONFIG_LEON3 $CONFIG_LEON3 [list $notmod] 2 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_PROC_NUM $CONFIG_PROC_NUM $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Processor "} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Integer unit "} - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS $CONFIG_IU_NWINDOWS $notmod } - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONFIG_IU_V8MULDIV [list $notmod] 2 } - global tmpvar_3 - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then { - if { $tmpvar_3 == "2-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 0 [list $notmod] 2 } - if { $tmpvar_3 == "4-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 0 [list $notmod] 2 } - if { $tmpvar_3 == "5-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 0 [list $notmod] 2 }} - global CONFIG_IU_MUL_MAC - global CONFIG_IU_MUL_LATENCY_4 - global CONFIG_IU_MUL_LATENCY_5 - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_MAC $CONFIG_IU_MUL_MAC [list $notmod] 2 } - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONFIG_IU_SVT [list $notmod] 2 } - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY $CONFIG_IU_LDELAY $notmod } - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS $CONFIG_IU_WATCHPOINTS $notmod } - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONFIG_PWD [list $notmod] 2 } - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR $CONFIG_IU_RSTADDR $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Floating-point unit"} - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONFIG_FPU_ENABLE [list $notmod] 2 } - global tmpvar_4 - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - if { $tmpvar_4 == "GRFPU" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 0 [list $notmod] 2 } - if { $tmpvar_4 == "GRFPU-LITE" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 0 [list $notmod] 2 } - if { $tmpvar_4 == "Meiko" } then { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 0 [list $notmod] 2 }} - global tmpvar_5 - global CONFIG_FPU_GRFPU - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then { - if { $tmpvar_5 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 0 [list $notmod] 2 } - if { $tmpvar_5 == "DW" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 0 [list $notmod] 2 } - if { $tmpvar_5 == "ModGen" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 0 [list $notmod] 2 }} - global tmpvar_6 - global CONFIG_FPU_GRFPULITE - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then { - if { $tmpvar_6 == "Simple" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 0 [list $notmod] 2 } - if { $tmpvar_6 == "Data-forwarding" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 0 [list $notmod] 2 } - if { $tmpvar_6 == "Non-blocking" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 0 [list $notmod] 2 }} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_NETLIST $CONFIG_FPU_NETLIST [list $notmod] 2 } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Cache system"} - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONFIG_ICACHE_ENABLE [list $notmod] 2 } - global tmpvar_7 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_7 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 0 [list $notmod] 2 } - if { $tmpvar_7 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 0 [list $notmod] 2 } - if { $tmpvar_7 == "3" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 0 [list $notmod] 2 } - if { $tmpvar_7 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 0 [list $notmod] 2 }} - global tmpvar_8 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_8 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 0 [list $notmod] 2 } - if { $tmpvar_8 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 0 [list $notmod] 2 } - if { $tmpvar_8 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 0 [list $notmod] 2 } - if { $tmpvar_8 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 0 [list $notmod] 2 } - if { $tmpvar_8 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 0 [list $notmod] 2 } - if { $tmpvar_8 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 0 [list $notmod] 2 } - if { $tmpvar_8 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 0 [list $notmod] 2 } - if { $tmpvar_8 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 0 [list $notmod] 2 } - if { $tmpvar_8 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 0 [list $notmod] 2 }} - global tmpvar_9 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_9 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 0 [list $notmod] 2 } - if { $tmpvar_9 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 0 [list $notmod] 2 }} - global tmpvar_10 - global CONFIG_ICACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - if { $tmpvar_10 == "Random" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 0 [list $notmod] 2 } - if { $tmpvar_10 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 0 [list $notmod] 2 } - if { $tmpvar_10 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 0 [list $notmod] 2 }} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONFIG_ICACHE_LOCK [list $notmod] 2 } - global CONFIG_ICACHE_LRAM - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM $CONFIG_ICACHE_LRAM [list $notmod] 2 } - global tmpvar_11 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then { - if { $tmpvar_11 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_11 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_11 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_11 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_11 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_11 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_11 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 0 [list $notmod] 2 } - if { $tmpvar_11 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 0 [list $notmod] 2 } - if { $tmpvar_11 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 0 [list $notmod] 2 }} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_ICACHE_LRSTART $CONFIG_ICACHE_LRSTART $notmod } - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONFIG_DCACHE_ENABLE [list $notmod] 2 } - global tmpvar_12 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_12 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 0 [list $notmod] 2 } - if { $tmpvar_12 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 0 [list $notmod] 2 } - if { $tmpvar_12 == "3" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 0 [list $notmod] 2 } - if { $tmpvar_12 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 0 [list $notmod] 2 }} - global tmpvar_13 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_13 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 0 [list $notmod] 2 } - if { $tmpvar_13 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 0 [list $notmod] 2 } - if { $tmpvar_13 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 0 [list $notmod] 2 } - if { $tmpvar_13 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 0 [list $notmod] 2 } - if { $tmpvar_13 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 0 [list $notmod] 2 } - if { $tmpvar_13 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 0 [list $notmod] 2 } - if { $tmpvar_13 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 0 [list $notmod] 2 } - if { $tmpvar_13 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 0 [list $notmod] 2 } - if { $tmpvar_13 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 0 [list $notmod] 2 }} - global tmpvar_14 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_14 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 0 [list $notmod] 2 } - if { $tmpvar_14 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 0 [list $notmod] 2 }} - global tmpvar_15 - global CONFIG_DCACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - if { $tmpvar_15 == "Random" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 0 [list $notmod] 2 } - if { $tmpvar_15 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 0 [list $notmod] 2 } - if { $tmpvar_15 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } - global tmpvar_16 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then { - if { $tmpvar_16 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_16 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_16 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_16 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_16 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_16 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_16 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 0 [list $notmod] 2 } - if { $tmpvar_16 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 0 [list $notmod] 2 } - if { $tmpvar_16 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 0 [list $notmod] 2 }} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_DCACHE_LRSTART $CONFIG_DCACHE_LRSTART $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "MMU"} - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONFIG_MMU_ENABLE [list $notmod] 2 } - global tmpvar_17 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_17 == "combined" } then { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 0 [list $notmod] 2 } - if { $tmpvar_17 == "split" } then { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 0 [list $notmod] 2 }} - global tmpvar_18 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 0 [list $notmod] 2 } - if { $tmpvar_18 == "Increment" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 0 [list $notmod] 2 }} - global tmpvar_19 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_19 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_I2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I2 0 [list $notmod] 2 } - if { $tmpvar_19 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_I4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I4 0 [list $notmod] 2 } - if { $tmpvar_19 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_I8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I8 0 [list $notmod] 2 } - if { $tmpvar_19 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_I16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I16 0 [list $notmod] 2 } - if { $tmpvar_19 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_I32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I32 0 [list $notmod] 2 }} - global tmpvar_20 - global CONFIG_MMU_SPLIT - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - if { $tmpvar_20 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_D2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D2 0 [list $notmod] 2 } - if { $tmpvar_20 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_D4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D4 0 [list $notmod] 2 } - if { $tmpvar_20 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_D8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D8 0 [list $notmod] 2 } - if { $tmpvar_20 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_D16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D16 0 [list $notmod] 2 } - if { $tmpvar_20 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_D32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D32 0 [list $notmod] 2 }} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_FASTWB $CONFIG_MMU_FASTWB [list $notmod] 2 } - global tmpvar_21 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_21 == "4K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 0 [list $notmod] 2 } - if { $tmpvar_21 == "8K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 0 [list $notmod] 2 } - if { $tmpvar_21 == "16K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 0 [list $notmod] 2 } - if { $tmpvar_21 == "32K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 0 [list $notmod] 2 } - if { $tmpvar_21 == "Programmable" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 0 [list $notmod] 2 }} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Debug Support Unit "} - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONFIG_DSU_ENABLE [list $notmod] 2 } - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACE $CONFIG_DSU_ITRACE [list $notmod] 2 } - global tmpvar_22 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then { - if { $tmpvar_22 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 0 [list $notmod] 2 } - if { $tmpvar_22 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 0 [list $notmod] 2 } - if { $tmpvar_22 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 0 [list $notmod] 2 } - if { $tmpvar_22 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 0 [list $notmod] 2 } - if { $tmpvar_22 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 0 [list $notmod] 2 }} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ATRACE $CONFIG_DSU_ATRACE [list $notmod] 2 } - global tmpvar_23 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then { - if { $tmpvar_23 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 0 [list $notmod] 2 } - if { $tmpvar_23 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 0 [list $notmod] 2 } - if { $tmpvar_23 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 0 [list $notmod] 2 } - if { $tmpvar_23 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 0 [list $notmod] 2 } - if { $tmpvar_23 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 0 [list $notmod] 2 }} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Fault-tolerance "} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "VHDL debug settings "} - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS $CONFIG_IU_DISAS [list $notmod] 2 } - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS_NET $CONFIG_IU_DISAS_NET [list $notmod] 2 } - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DEBUG_PC32 $CONFIG_DEBUG_PC32 [list $notmod] 2 } - write_comment $cfg $autocfg "AMBA configuration" - global CONFIG_AHB_DEFMST - write_int $cfg $autocfg CONFIG_AHB_DEFMST $CONFIG_AHB_DEFMST $notmod - global CONFIG_AHB_RROBIN - write_tristate $cfg $autocfg CONFIG_AHB_RROBIN $CONFIG_AHB_RROBIN [list $notmod] 2 - global CONFIG_AHB_SPLIT - write_tristate $cfg $autocfg CONFIG_AHB_SPLIT $CONFIG_AHB_SPLIT [list $notmod] 2 - global CONFIG_AHB_IOADDR - write_hex $cfg $autocfg CONFIG_AHB_IOADDR $CONFIG_AHB_IOADDR $notmod - global CONFIG_APB_HADDR - write_hex $cfg $autocfg CONFIG_APB_HADDR $CONFIG_APB_HADDR $notmod - global CONFIG_AHB_MON - write_tristate $cfg $autocfg CONFIG_AHB_MON $CONFIG_AHB_MON [list $notmod] 2 - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONERR $CONFIG_AHB_MONERR [list $notmod] 2 } - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONWAR $CONFIG_AHB_MONWAR [list $notmod] 2 } - write_comment $cfg $autocfg "Debug Link " - global CONFIG_DSU_UART - write_tristate $cfg $autocfg CONFIG_DSU_UART $CONFIG_DSU_UART [list $notmod] 2 - global CONFIG_DSU_JTAG - write_tristate $cfg $autocfg CONFIG_DSU_JTAG $CONFIG_DSU_JTAG [list $notmod] 2 - global CONFIG_DSU_ETH - global CONFIG_GRETH_ENABLE - if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH $CONFIG_DSU_ETH [list $notmod] 2 } - global tmpvar_25 - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { - if { $tmpvar_25 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 0 [list $notmod] 2 } - if { $tmpvar_25 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 0 [list $notmod] 2 } - if { $tmpvar_25 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 0 [list $notmod] 2 } - if { $tmpvar_25 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 0 [list $notmod] 2 } - if { $tmpvar_25 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 0 [list $notmod] 2 }} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPMSB $CONFIG_DSU_IPMSB $notmod } - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPLSB $CONFIG_DSU_IPLSB $notmod } - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHMSB $CONFIG_DSU_ETHMSB $notmod } - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } - global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } - write_comment $cfg $autocfg "Peripherals " - write_comment $cfg $autocfg "Memory controllers " - write_comment $cfg $autocfg "8/32-bit PROM/SRAM controller " - global CONFIG_SRCTRL - write_tristate $cfg $autocfg CONFIG_SRCTRL $CONFIG_SRCTRL [list $notmod] 2 - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SRCTRL_8BIT $CONFIG_SRCTRL_8BIT [list $notmod] 2 } - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_PROMWS $CONFIG_SRCTRL_PROMWS $notmod } - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_RAMWS $CONFIG_SRCTRL_RAMWS $notmod } - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_IOWS $CONFIG_SRCTRL_IOWS $notmod } - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SRCTRL_RMW $CONFIG_SRCTRL_RMW [list $notmod] 2 } - global tmpvar_26 - if {($CONFIG_SRCTRL == 1)} then { - if { $tmpvar_26 == "1" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS1 0 [list $notmod] 2 } - if { $tmpvar_26 == "2" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS2 0 [list $notmod] 2 } - if { $tmpvar_26 == "3" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS3 0 [list $notmod] 2 } - if { $tmpvar_26 == "4" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS4 0 [list $notmod] 2 } - if { $tmpvar_26 == "5" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS5 0 [list $notmod] 2 }} - global tmpvar_27 - if {($CONFIG_SRCTRL == 1)} then { - if { $tmpvar_27 == "8" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ0 0 [list $notmod] 2 } - if { $tmpvar_27 == "16" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ1 0 [list $notmod] 2 } - if { $tmpvar_27 == "32" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ2 0 [list $notmod] 2 } - if { $tmpvar_27 == "64" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ3 0 [list $notmod] 2 } - if { $tmpvar_27 == "128" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ4 0 [list $notmod] 2 } - if { $tmpvar_27 == "256" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ5 0 [list $notmod] 2 } - if { $tmpvar_27 == "512" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ6 0 [list $notmod] 2 } - if { $tmpvar_27 == "1024" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ7 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ7 0 [list $notmod] 2 } - if { $tmpvar_27 == "2048" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ8 0 [list $notmod] 2 } - if { $tmpvar_27 == "4096" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ9 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ9 0 [list $notmod] 2 } - if { $tmpvar_27 == "8192" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ10 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ10 0 [list $notmod] 2 } - if { $tmpvar_27 == "16384" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ11 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ11 0 [list $notmod] 2 } - if { $tmpvar_27 == "32768" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ12 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ12 0 [list $notmod] 2 } - if { $tmpvar_27 == "65536" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ13 0 [list $notmod] 2 }} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_ROMASEL $CONFIG_SRCTRL_ROMASEL $notmod } - write_comment $cfg $autocfg "Leon2 memory controller " - global CONFIG_MCTRL_LEON2 - write_tristate $cfg $autocfg CONFIG_MCTRL_LEON2 $CONFIG_MCTRL_LEON2 [list $notmod] 2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_8BIT $CONFIG_MCTRL_8BIT [list $notmod] 2 } - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_16BIT $CONFIG_MCTRL_16BIT [list $notmod] 2 } - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_5CS $CONFIG_MCTRL_5CS [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM $CONFIG_MCTRL_SDRAM [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_SEPBUS $CONFIG_MCTRL_SDRAM_SEPBUS [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_BUS64 $CONFIG_MCTRL_SDRAM_BUS64 [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_INVCLK $CONFIG_MCTRL_SDRAM_INVCLK [list $notmod] 2 } - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PAGE $CONFIG_MCTRL_PAGE [list $notmod] 2 } - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PROGPAGE $CONFIG_MCTRL_PROGPAGE [list $notmod] 2 } - write_comment $cfg $autocfg "PC133 SDRAM controller " - global CONFIG_SDCTRL - write_tristate $cfg $autocfg CONFIG_SDCTRL $CONFIG_SDCTRL [list $notmod] 2 - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_BUS64 $CONFIG_SDCTRL_BUS64 [list $notmod] 2 } - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_INVCLK $CONFIG_SDCTRL_INVCLK [list $notmod] 2 } - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_PAGE $CONFIG_SDCTRL_PAGE [list $notmod] 2 } - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_PROGPAGE $CONFIG_SDCTRL_PROGPAGE [list $notmod] 2 } - write_comment $cfg $autocfg "On-chip RAM/ROM " - global CONFIG_AHBROM_ENABLE - write_tristate $cfg $autocfg CONFIG_AHBROM_ENABLE $CONFIG_AHBROM_ENABLE [list $notmod] 2 - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBROM_START $CONFIG_AHBROM_START $notmod } - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBROM_PIPE $CONFIG_AHBROM_PIPE [list $notmod] 2 } - global CONFIG_AHBRAM_ENABLE - write_tristate $cfg $autocfg CONFIG_AHBRAM_ENABLE $CONFIG_AHBRAM_ENABLE [list $notmod] 2 - global tmpvar_28 - if {($CONFIG_AHBRAM_ENABLE == 1)} then { - if { $tmpvar_28 == "1" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_28 == "2" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_28 == "4" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_28 == "8" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_28 == "16" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_28 == "32" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_28 == "64" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 0 [list $notmod] 2 }} - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBRAM_START $CONFIG_AHBRAM_START $notmod } - write_comment $cfg $autocfg "Ethernet " - write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 - if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } - global tmpvar_29 - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - if { $tmpvar_29 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_29 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_29 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_29 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 0 [list $notmod] 2 } - if { $tmpvar_29 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "CAN " - global CONFIG_CAN_ENABLE - write_tristate $cfg $autocfg CONFIG_CAN_ENABLE $CONFIG_CAN_ENABLE [list $notmod] 2 - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CANIO $CONFIG_CANIO $notmod } - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_CANIRQ $CONFIG_CANIRQ $notmod } - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CANLOOP $CONFIG_CANLOOP [list $notmod] 2 } - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CAN_SYNCRST $CONFIG_CAN_SYNCRST [list $notmod] 2 } - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CAN_FT $CONFIG_CAN_FT [list $notmod] 2 } - write_comment $cfg $autocfg "PCI " - global CONFIG_PCI_SIMPLE_TARGET - global CONFIG_PCI_ACTEL - if {($CONFIG_PCI_ACTEL != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SIMPLE_TARGET $CONFIG_PCI_SIMPLE_TARGET [list $notmod] 2 } - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_MASTER_TARGET $CONFIG_PCI_MASTER_TARGET [list $notmod] 2 } - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_MASTER_TARGET_DMA $CONFIG_PCI_MASTER_TARGET_DMA [list $notmod] 2 } - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_VENDORID $CONFIG_PCI_VENDORID $notmod } - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_DEVICEID $CONFIG_PCI_DEVICEID $notmod } - global tmpvar_30 - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then { - if { $tmpvar_30 == "None" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO0 0 [list $notmod] 2 } - if { $tmpvar_30 == "8" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_30 == "16" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_30 == "32" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO32 0 [list $notmod] 2 } - if { $tmpvar_30 == "64" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO64 0 [list $notmod] 2 } - if { $tmpvar_30 == "128" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO128 0 [list $notmod] 2 }} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_HADDR $CONFIG_PCI_HADDR $notmod } - global CONFIG_PCI_ARBITER - write_tristate $cfg $autocfg CONFIG_PCI_ARBITER $CONFIG_PCI_ARBITER [list $notmod] 2 - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_ARBITER_APB $CONFIG_PCI_ARBITER_APB [list $notmod] 2 } - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {write_int $cfg $autocfg CONFIG_PCI_ARBITER_NREQ $CONFIG_PCI_ARBITER_NREQ $notmod } - global CONFIG_PCI_TRACE - write_tristate $cfg $autocfg CONFIG_PCI_TRACE $CONFIG_PCI_TRACE [list $notmod] 2 - global tmpvar_31 - if {($CONFIG_PCI_TRACE == 1)} then { - if { $tmpvar_31 == "256" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE256 0 [list $notmod] 2 } - if { $tmpvar_31 == "512" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE512 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE512 0 [list $notmod] 2 } - if { $tmpvar_31 == "1024" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE1024 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE1024 0 [list $notmod] 2 } - if { $tmpvar_31 == "2048" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE2048 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE2048 0 [list $notmod] 2 } - if { $tmpvar_31 == "4096" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE4096 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE4096 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "Spacewire " - global CONFIG_SPW_ENABLE - write_tristate $cfg $autocfg CONFIG_SPW_ENABLE $CONFIG_SPW_ENABLE [list $notmod] 2 - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPW_NUM $CONFIG_SPW_NUM $notmod } - global tmpvar_32 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_32 == "4" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO4 0 [list $notmod] 2 } - if { $tmpvar_32 == "8" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO8 0 [list $notmod] 2 } - if { $tmpvar_32 == "16" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO16 0 [list $notmod] 2 } - if { $tmpvar_32 == "32" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO32 0 [list $notmod] 2 }} - global tmpvar_33 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_33 == "16" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO16 0 [list $notmod] 2 } - if { $tmpvar_33 == "32" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO32 0 [list $notmod] 2 } - if { $tmpvar_33 == "64" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO64 0 [list $notmod] 2 }} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RMAP $CONFIG_SPW_RMAP [list $notmod] 2 } - global tmpvar_34 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_RMAP == 1)} then { - if { $tmpvar_34 == "64" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF2 0 [list $notmod] 2 } - if { $tmpvar_34 == "128" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF4 0 [list $notmod] 2 } - if { $tmpvar_34 == "192" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF6 0 [list $notmod] 2 } - if { $tmpvar_34 == "256" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF8 0 [list $notmod] 2 }} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RMAPCRC $CONFIG_SPW_RMAPCRC [list $notmod] 2 } - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RXUNAL $CONFIG_SPW_RXUNAL [list $notmod] 2 } - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_FT $CONFIG_SPW_FT [list $notmod] 2 } - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_NETLIST $CONFIG_SPW_NETLIST [list $notmod] 2 } - global tmpvar_35 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_35 == "1" } then { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW1 0 [list $notmod] 2 } - if { $tmpvar_35 == "2" } then { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW2 0 [list $notmod] 2 }} - global CONFIG_SPW_DMACHAN - global CONFIG_SPW_GRSPW2 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_int $cfg $autocfg CONFIG_SPW_DMACHAN $CONFIG_SPW_DMACHAN $notmod } - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_int $cfg $autocfg CONFIG_SPW_PORTS $CONFIG_SPW_PORTS $notmod } - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RTSAME $CONFIG_SPW_RTSAME [list $notmod] 2 } - global tmpvar_36 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - if { $tmpvar_36 == "SDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_SDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_SDR 0 [list $notmod] 2 } - if { $tmpvar_36 == "DDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_DDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_DDR 0 [list $notmod] 2 } - if { $tmpvar_36 == "Xor" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_XOR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_XOR 0 [list $notmod] 2 } - if { $tmpvar_36 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_AFLEX 0 [list $notmod] 2 }} - global tmpvar_37 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - if { $tmpvar_37 == "SDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_SDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_SDR 0 [list $notmod] 2 } - if { $tmpvar_37 == "DDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_DDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_DDR 0 [list $notmod] 2 } - if { $tmpvar_37 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "UARTs, timers and irq control " - global CONFIG_UART1_ENABLE - write_tristate $cfg $autocfg CONFIG_UART1_ENABLE $CONFIG_UART1_ENABLE [list $notmod] 2 - global tmpvar_38 - if {($CONFIG_UART1_ENABLE == 1)} then { - if { $tmpvar_38 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 0 [list $notmod] 2 } - if { $tmpvar_38 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 0 [list $notmod] 2 } - if { $tmpvar_38 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_38 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_38 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_38 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 0 [list $notmod] 2 }} - global CONFIG_UART2_ENABLE - write_tristate $cfg $autocfg CONFIG_UART2_ENABLE $CONFIG_UART2_ENABLE [list $notmod] 2 - global tmpvar_39 - if {($CONFIG_UART2_ENABLE == 1)} then { - if { $tmpvar_39 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO1 0 [list $notmod] 2 } - if { $tmpvar_39 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO2 0 [list $notmod] 2 } - if { $tmpvar_39 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_39 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_39 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_39 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO32 0 [list $notmod] 2 }} - global CONFIG_IRQ3_ENABLE - write_tristate $cfg $autocfg CONFIG_IRQ3_ENABLE $CONFIG_IRQ3_ENABLE [list $notmod] 2 - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_IRQ3_SEC $CONFIG_IRQ3_SEC [list $notmod] 2 } - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {write_int $cfg $autocfg CONFIG_IRQ3_NSEC $CONFIG_IRQ3_NSEC $notmod } - global CONFIG_GPT_ENABLE - write_tristate $cfg $autocfg CONFIG_GPT_ENABLE $CONFIG_GPT_ENABLE [list $notmod] 2 - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_NTIM $CONFIG_GPT_NTIM $notmod } - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_SW $CONFIG_GPT_SW $notmod } - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_TW $CONFIG_GPT_TW $notmod } - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_IRQ $CONFIG_GPT_IRQ $notmod } - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_SEPIRQ $CONFIG_GPT_SEPIRQ [list $notmod] 2 } - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_WDOGEN $CONFIG_GPT_WDOGEN [list $notmod] 2 } - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {write_hex $cfg $autocfg CONFIG_GPT_WDOG $CONFIG_GPT_WDOG $notmod } - global CONFIG_GRGPIO_ENABLE - write_tristate $cfg $autocfg CONFIG_GRGPIO_ENABLE $CONFIG_GRGPIO_ENABLE [list $notmod] 2 - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRGPIO_WIDTH $CONFIG_GRGPIO_WIDTH $notmod } - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_GRGPIO_IMASK $CONFIG_GRGPIO_IMASK $notmod } - write_comment $cfg $autocfg "VHDL Debugging " - global CONFIG_DEBUG_UART - write_tristate $cfg $autocfg CONFIG_DEBUG_UART $CONFIG_DEBUG_UART [list $notmod] 2 - close $cfg - close $autocfg -} - - -proc clear_choices { } { - global CONFIG_SYN_INFERRED; set CONFIG_SYN_INFERRED 0 - global CONFIG_SYN_STRATIX; set CONFIG_SYN_STRATIX 0 - global CONFIG_SYN_STRATIXII; set CONFIG_SYN_STRATIXII 0 - global CONFIG_SYN_STRATIXIII; set CONFIG_SYN_STRATIXIII 0 - global CONFIG_SYN_CYCLONEIII; set CONFIG_SYN_CYCLONEIII 0 - global CONFIG_SYN_ALTERA; set CONFIG_SYN_ALTERA 0 - global CONFIG_SYN_AXCEL; set CONFIG_SYN_AXCEL 0 - global CONFIG_SYN_PROASIC; set CONFIG_SYN_PROASIC 0 - global CONFIG_SYN_PROASICPLUS; set CONFIG_SYN_PROASICPLUS 0 - global CONFIG_SYN_PROASIC3; set CONFIG_SYN_PROASIC3 0 - global CONFIG_SYN_UT025CRH; set CONFIG_SYN_UT025CRH 0 - global CONFIG_SYN_ATC18; set CONFIG_SYN_ATC18 0 - global CONFIG_SYN_ATC18RHA; set CONFIG_SYN_ATC18RHA 0 - global CONFIG_SYN_CUSTOM1; set CONFIG_SYN_CUSTOM1 0 - global CONFIG_SYN_EASIC90; set CONFIG_SYN_EASIC90 0 - global CONFIG_SYN_IHP25; set CONFIG_SYN_IHP25 0 - global CONFIG_SYN_IHP25RH; set CONFIG_SYN_IHP25RH 0 - global CONFIG_SYN_LATTICE; set CONFIG_SYN_LATTICE 0 - global CONFIG_SYN_ECLIPSE; set CONFIG_SYN_ECLIPSE 0 - global CONFIG_SYN_PEREGRINE; set CONFIG_SYN_PEREGRINE 0 - global CONFIG_SYN_RH_LIB18T; set CONFIG_SYN_RH_LIB18T 0 - global CONFIG_SYN_RHUMC; set CONFIG_SYN_RHUMC 0 - global CONFIG_SYN_SMIC13; set CONFIG_SYN_SMIC13 0 - global CONFIG_SYN_SPARTAN2; set CONFIG_SYN_SPARTAN2 0 - global CONFIG_SYN_SPARTAN3; set CONFIG_SYN_SPARTAN3 0 - global CONFIG_SYN_SPARTAN3E; set CONFIG_SYN_SPARTAN3E 0 - global CONFIG_SYN_VIRTEX; set CONFIG_SYN_VIRTEX 0 - global CONFIG_SYN_VIRTEXE; set CONFIG_SYN_VIRTEXE 0 - global CONFIG_SYN_VIRTEX2; set CONFIG_SYN_VIRTEX2 0 - global CONFIG_SYN_VIRTEX4; set CONFIG_SYN_VIRTEX4 0 - global CONFIG_SYN_VIRTEX5; set CONFIG_SYN_VIRTEX5 0 - global CONFIG_SYN_UMC; set CONFIG_SYN_UMC 0 - global CONFIG_SYN_TSMC90; set CONFIG_SYN_TSMC90 0 - global CONFIG_MEM_INFERRED; set CONFIG_MEM_INFERRED 0 - global CONFIG_MEM_UMC; set CONFIG_MEM_UMC 0 - global CONFIG_MEM_RHUMC; set CONFIG_MEM_RHUMC 0 - global CONFIG_MEM_ARTISAN; set CONFIG_MEM_ARTISAN 0 - global CONFIG_MEM_CUSTOM1; set CONFIG_MEM_CUSTOM1 0 - global CONFIG_MEM_VIRAGE; set CONFIG_MEM_VIRAGE 0 - global CONFIG_MEM_VIRAGE90; set CONFIG_MEM_VIRAGE90 0 - global CONFIG_CLK_INFERRED; set CONFIG_CLK_INFERRED 0 - global CONFIG_CLK_HCLKBUF; set CONFIG_CLK_HCLKBUF 0 - global CONFIG_CLK_ALTDLL; set CONFIG_CLK_ALTDLL 0 - global CONFIG_CLK_LATDLL; set CONFIG_CLK_LATDLL 0 - global CONFIG_CLK_PRO3PLL; set CONFIG_CLK_PRO3PLL 0 - global CONFIG_CLK_LIB18T; set CONFIG_CLK_LIB18T 0 - global CONFIG_CLK_RHUMC; set CONFIG_CLK_RHUMC 0 - global CONFIG_CLK_CLKDLL; set CONFIG_CLK_CLKDLL 0 - global CONFIG_CLK_DCM; set CONFIG_CLK_DCM 0 - global CONFIG_IU_MUL_LATENCY_2; set CONFIG_IU_MUL_LATENCY_2 0 - global CONFIG_IU_MUL_LATENCY_4; set CONFIG_IU_MUL_LATENCY_4 0 - global CONFIG_IU_MUL_LATENCY_5; set CONFIG_IU_MUL_LATENCY_5 0 - global CONFIG_FPU_GRFPU; set CONFIG_FPU_GRFPU 0 - global CONFIG_FPU_GRFPULITE; set CONFIG_FPU_GRFPULITE 0 - global CONFIG_FPU_MEIKO; set CONFIG_FPU_MEIKO 0 - global CONFIG_FPU_GRFPU_INFMUL; set CONFIG_FPU_GRFPU_INFMUL 0 - global CONFIG_FPU_GRFPU_DWMUL; set CONFIG_FPU_GRFPU_DWMUL 0 - global CONFIG_FPU_GRFPU_MODGEN; set CONFIG_FPU_GRFPU_MODGEN 0 - global CONFIG_FPU_GRFPC0; set CONFIG_FPU_GRFPC0 0 - global CONFIG_FPU_GRFPC1; set CONFIG_FPU_GRFPC1 0 - global CONFIG_FPU_GRFPC2; set CONFIG_FPU_GRFPC2 0 - global CONFIG_ICACHE_ASSO1; set CONFIG_ICACHE_ASSO1 0 - global CONFIG_ICACHE_ASSO2; set CONFIG_ICACHE_ASSO2 0 - global CONFIG_ICACHE_ASSO3; set CONFIG_ICACHE_ASSO3 0 - global CONFIG_ICACHE_ASSO4; set CONFIG_ICACHE_ASSO4 0 - global CONFIG_ICACHE_SZ1; set CONFIG_ICACHE_SZ1 0 - global CONFIG_ICACHE_SZ2; set CONFIG_ICACHE_SZ2 0 - global CONFIG_ICACHE_SZ4; set CONFIG_ICACHE_SZ4 0 - global CONFIG_ICACHE_SZ8; set CONFIG_ICACHE_SZ8 0 - global CONFIG_ICACHE_SZ16; set CONFIG_ICACHE_SZ16 0 - global CONFIG_ICACHE_SZ32; set CONFIG_ICACHE_SZ32 0 - global CONFIG_ICACHE_SZ64; set CONFIG_ICACHE_SZ64 0 - global CONFIG_ICACHE_SZ128; set CONFIG_ICACHE_SZ128 0 - global CONFIG_ICACHE_SZ256; set CONFIG_ICACHE_SZ256 0 - global CONFIG_ICACHE_LZ16; set CONFIG_ICACHE_LZ16 0 - global CONFIG_ICACHE_LZ32; set CONFIG_ICACHE_LZ32 0 - global CONFIG_ICACHE_ALGORND; set CONFIG_ICACHE_ALGORND 0 - global CONFIG_ICACHE_ALGOLRR; set CONFIG_ICACHE_ALGOLRR 0 - global CONFIG_ICACHE_ALGOLRU; set CONFIG_ICACHE_ALGOLRU 0 - global CONFIG_ICACHE_LRAM_SZ1; set CONFIG_ICACHE_LRAM_SZ1 0 - global CONFIG_ICACHE_LRAM_SZ2; set CONFIG_ICACHE_LRAM_SZ2 0 - global CONFIG_ICACHE_LRAM_SZ4; set CONFIG_ICACHE_LRAM_SZ4 0 - global CONFIG_ICACHE_LRAM_SZ8; set CONFIG_ICACHE_LRAM_SZ8 0 - global CONFIG_ICACHE_LRAM_SZ16; set CONFIG_ICACHE_LRAM_SZ16 0 - global CONFIG_ICACHE_LRAM_SZ32; set CONFIG_ICACHE_LRAM_SZ32 0 - global CONFIG_ICACHE_LRAM_SZ64; set CONFIG_ICACHE_LRAM_SZ64 0 - global CONFIG_ICACHE_LRAM_SZ128; set CONFIG_ICACHE_LRAM_SZ128 0 - global CONFIG_ICACHE_LRAM_SZ256; set CONFIG_ICACHE_LRAM_SZ256 0 - global CONFIG_DCACHE_ASSO1; set CONFIG_DCACHE_ASSO1 0 - global CONFIG_DCACHE_ASSO2; set CONFIG_DCACHE_ASSO2 0 - global CONFIG_DCACHE_ASSO3; set CONFIG_DCACHE_ASSO3 0 - global CONFIG_DCACHE_ASSO4; set CONFIG_DCACHE_ASSO4 0 - global CONFIG_DCACHE_SZ1; set CONFIG_DCACHE_SZ1 0 - global CONFIG_DCACHE_SZ2; set CONFIG_DCACHE_SZ2 0 - global CONFIG_DCACHE_SZ4; set CONFIG_DCACHE_SZ4 0 - global CONFIG_DCACHE_SZ8; set CONFIG_DCACHE_SZ8 0 - global CONFIG_DCACHE_SZ16; set CONFIG_DCACHE_SZ16 0 - global CONFIG_DCACHE_SZ32; set CONFIG_DCACHE_SZ32 0 - global CONFIG_DCACHE_SZ64; set CONFIG_DCACHE_SZ64 0 - global CONFIG_DCACHE_SZ128; set CONFIG_DCACHE_SZ128 0 - global CONFIG_DCACHE_SZ256; set CONFIG_DCACHE_SZ256 0 - global CONFIG_DCACHE_LZ16; set CONFIG_DCACHE_LZ16 0 - global CONFIG_DCACHE_LZ32; set CONFIG_DCACHE_LZ32 0 - global CONFIG_DCACHE_ALGORND; set CONFIG_DCACHE_ALGORND 0 - global CONFIG_DCACHE_ALGOLRR; set CONFIG_DCACHE_ALGOLRR 0 - global CONFIG_DCACHE_ALGOLRU; set CONFIG_DCACHE_ALGOLRU 0 - global CONFIG_DCACHE_LRAM_SZ1; set CONFIG_DCACHE_LRAM_SZ1 0 - global CONFIG_DCACHE_LRAM_SZ2; set CONFIG_DCACHE_LRAM_SZ2 0 - global CONFIG_DCACHE_LRAM_SZ4; set CONFIG_DCACHE_LRAM_SZ4 0 - global CONFIG_DCACHE_LRAM_SZ8; set CONFIG_DCACHE_LRAM_SZ8 0 - global CONFIG_DCACHE_LRAM_SZ16; set CONFIG_DCACHE_LRAM_SZ16 0 - global CONFIG_DCACHE_LRAM_SZ32; set CONFIG_DCACHE_LRAM_SZ32 0 - global CONFIG_DCACHE_LRAM_SZ64; set CONFIG_DCACHE_LRAM_SZ64 0 - global CONFIG_DCACHE_LRAM_SZ128; set CONFIG_DCACHE_LRAM_SZ128 0 - global CONFIG_DCACHE_LRAM_SZ256; set CONFIG_DCACHE_LRAM_SZ256 0 - global CONFIG_MMU_COMBINED; set CONFIG_MMU_COMBINED 0 - global CONFIG_MMU_SPLIT; set CONFIG_MMU_SPLIT 0 - global CONFIG_MMU_REPARRAY; set CONFIG_MMU_REPARRAY 0 - global CONFIG_MMU_REPINCREMENT; set CONFIG_MMU_REPINCREMENT 0 - global CONFIG_MMU_I2; set CONFIG_MMU_I2 0 - global CONFIG_MMU_I4; set CONFIG_MMU_I4 0 - global CONFIG_MMU_I8; set CONFIG_MMU_I8 0 - global CONFIG_MMU_I16; set CONFIG_MMU_I16 0 - global CONFIG_MMU_I32; set CONFIG_MMU_I32 0 - global CONFIG_MMU_D2; set CONFIG_MMU_D2 0 - global CONFIG_MMU_D4; set CONFIG_MMU_D4 0 - global CONFIG_MMU_D8; set CONFIG_MMU_D8 0 - global CONFIG_MMU_D16; set CONFIG_MMU_D16 0 - global CONFIG_MMU_D32; set CONFIG_MMU_D32 0 - global CONFIG_MMU_PAGE_4K; set CONFIG_MMU_PAGE_4K 0 - global CONFIG_MMU_PAGE_8K; set CONFIG_MMU_PAGE_8K 0 - global CONFIG_MMU_PAGE_16K; set CONFIG_MMU_PAGE_16K 0 - global CONFIG_MMU_PAGE_32K; set CONFIG_MMU_PAGE_32K 0 - global CONFIG_MMU_PAGE_PROG; set CONFIG_MMU_PAGE_PROG 0 - global CONFIG_DSU_ITRACESZ1; set CONFIG_DSU_ITRACESZ1 0 - global CONFIG_DSU_ITRACESZ2; set CONFIG_DSU_ITRACESZ2 0 - global CONFIG_DSU_ITRACESZ4; set CONFIG_DSU_ITRACESZ4 0 - global CONFIG_DSU_ITRACESZ8; set CONFIG_DSU_ITRACESZ8 0 - global CONFIG_DSU_ITRACESZ16; set CONFIG_DSU_ITRACESZ16 0 - global CONFIG_DSU_ATRACESZ1; set CONFIG_DSU_ATRACESZ1 0 - global CONFIG_DSU_ATRACESZ2; set CONFIG_DSU_ATRACESZ2 0 - global CONFIG_DSU_ATRACESZ4; set CONFIG_DSU_ATRACESZ4 0 - global CONFIG_DSU_ATRACESZ8; set CONFIG_DSU_ATRACESZ8 0 - global CONFIG_DSU_ATRACESZ16; set CONFIG_DSU_ATRACESZ16 0 - global CONFIG_DSU_ETHSZ1; set CONFIG_DSU_ETHSZ1 0 - global CONFIG_DSU_ETHSZ2; set CONFIG_DSU_ETHSZ2 0 - global CONFIG_DSU_ETHSZ4; set CONFIG_DSU_ETHSZ4 0 - global CONFIG_DSU_ETHSZ8; set CONFIG_DSU_ETHSZ8 0 - global CONFIG_DSU_ETHSZ16; set CONFIG_DSU_ETHSZ16 0 - global CONFIG_SRCTRL_SRBANKS1; set CONFIG_SRCTRL_SRBANKS1 0 - global CONFIG_SRCTRL_SRBANKS2; set CONFIG_SRCTRL_SRBANKS2 0 - global CONFIG_SRCTRL_SRBANKS3; set CONFIG_SRCTRL_SRBANKS3 0 - global CONFIG_SRCTRL_SRBANKS4; set CONFIG_SRCTRL_SRBANKS4 0 - global CONFIG_SRCTRL_SRBANKS5; set CONFIG_SRCTRL_SRBANKS5 0 - global CONFIG_SRCTRL_BANKSZ0; set CONFIG_SRCTRL_BANKSZ0 0 - global CONFIG_SRCTRL_BANKSZ1; set CONFIG_SRCTRL_BANKSZ1 0 - global CONFIG_SRCTRL_BANKSZ2; set CONFIG_SRCTRL_BANKSZ2 0 - global CONFIG_SRCTRL_BANKSZ3; set CONFIG_SRCTRL_BANKSZ3 0 - global CONFIG_SRCTRL_BANKSZ4; set CONFIG_SRCTRL_BANKSZ4 0 - global CONFIG_SRCTRL_BANKSZ5; set CONFIG_SRCTRL_BANKSZ5 0 - global CONFIG_SRCTRL_BANKSZ6; set CONFIG_SRCTRL_BANKSZ6 0 - global CONFIG_SRCTRL_BANKSZ7; set CONFIG_SRCTRL_BANKSZ7 0 - global CONFIG_SRCTRL_BANKSZ8; set CONFIG_SRCTRL_BANKSZ8 0 - global CONFIG_SRCTRL_BANKSZ9; set CONFIG_SRCTRL_BANKSZ9 0 - global CONFIG_SRCTRL_BANKSZ10; set CONFIG_SRCTRL_BANKSZ10 0 - global CONFIG_SRCTRL_BANKSZ11; set CONFIG_SRCTRL_BANKSZ11 0 - global CONFIG_SRCTRL_BANKSZ12; set CONFIG_SRCTRL_BANKSZ12 0 - global CONFIG_SRCTRL_BANKSZ13; set CONFIG_SRCTRL_BANKSZ13 0 - global CONFIG_AHBRAM_SZ1; set CONFIG_AHBRAM_SZ1 0 - global CONFIG_AHBRAM_SZ2; set CONFIG_AHBRAM_SZ2 0 - global CONFIG_AHBRAM_SZ4; set CONFIG_AHBRAM_SZ4 0 - global CONFIG_AHBRAM_SZ8; set CONFIG_AHBRAM_SZ8 0 - global CONFIG_AHBRAM_SZ16; set CONFIG_AHBRAM_SZ16 0 - global CONFIG_AHBRAM_SZ32; set CONFIG_AHBRAM_SZ32 0 - global CONFIG_AHBRAM_SZ64; set CONFIG_AHBRAM_SZ64 0 - global CONFIG_GRETH_FIFO4; set CONFIG_GRETH_FIFO4 0 - global CONFIG_GRETH_FIFO8; set CONFIG_GRETH_FIFO8 0 - global CONFIG_GRETH_FIFO16; set CONFIG_GRETH_FIFO16 0 - global CONFIG_GRETH_FIFO32; set CONFIG_GRETH_FIFO32 0 - global CONFIG_GRETH_FIFO64; set CONFIG_GRETH_FIFO64 0 - global CONFIG_PCI_FIFO0; set CONFIG_PCI_FIFO0 0 - global CONFIG_PCI_FIFO8; set CONFIG_PCI_FIFO8 0 - global CONFIG_PCI_FIFO16; set CONFIG_PCI_FIFO16 0 - global CONFIG_PCI_FIFO32; set CONFIG_PCI_FIFO32 0 - global CONFIG_PCI_FIFO64; set CONFIG_PCI_FIFO64 0 - global CONFIG_PCI_FIFO128; set CONFIG_PCI_FIFO128 0 - global CONFIG_PCI_TRACE256; set CONFIG_PCI_TRACE256 0 - global CONFIG_PCI_TRACE512; set CONFIG_PCI_TRACE512 0 - global CONFIG_PCI_TRACE1024; set CONFIG_PCI_TRACE1024 0 - global CONFIG_PCI_TRACE2048; set CONFIG_PCI_TRACE2048 0 - global CONFIG_PCI_TRACE4096; set CONFIG_PCI_TRACE4096 0 - global CONFIG_SPW_AHBFIFO4; set CONFIG_SPW_AHBFIFO4 0 - global CONFIG_SPW_AHBFIFO8; set CONFIG_SPW_AHBFIFO8 0 - global CONFIG_SPW_AHBFIFO16; set CONFIG_SPW_AHBFIFO16 0 - global CONFIG_SPW_AHBFIFO32; set CONFIG_SPW_AHBFIFO32 0 - global CONFIG_SPW_RXFIFO16; set CONFIG_SPW_RXFIFO16 0 - global CONFIG_SPW_RXFIFO32; set CONFIG_SPW_RXFIFO32 0 - global CONFIG_SPW_RXFIFO64; set CONFIG_SPW_RXFIFO64 0 - global CONFIG_SPW_RMAPBUF2; set CONFIG_SPW_RMAPBUF2 0 - global CONFIG_SPW_RMAPBUF4; set CONFIG_SPW_RMAPBUF4 0 - global CONFIG_SPW_RMAPBUF6; set CONFIG_SPW_RMAPBUF6 0 - global CONFIG_SPW_RMAPBUF8; set CONFIG_SPW_RMAPBUF8 0 - global CONFIG_SPW_GRSPW1; set CONFIG_SPW_GRSPW1 0 - global CONFIG_SPW_GRSPW2; set CONFIG_SPW_GRSPW2 0 - global CONFIG_SPW_RX_SDR; set CONFIG_SPW_RX_SDR 0 - global CONFIG_SPW_RX_DDR; set CONFIG_SPW_RX_DDR 0 - global CONFIG_SPW_RX_XOR; set CONFIG_SPW_RX_XOR 0 - global CONFIG_SPW_RX_AFLEX; set CONFIG_SPW_RX_AFLEX 0 - global CONFIG_SPW_TX_SDR; set CONFIG_SPW_TX_SDR 0 - global CONFIG_SPW_TX_DDR; set CONFIG_SPW_TX_DDR 0 - global CONFIG_SPW_TX_AFLEX; set CONFIG_SPW_TX_AFLEX 0 - global CONFIG_UA1_FIFO1; set CONFIG_UA1_FIFO1 0 - global CONFIG_UA1_FIFO2; set CONFIG_UA1_FIFO2 0 - global CONFIG_UA1_FIFO4; set CONFIG_UA1_FIFO4 0 - global CONFIG_UA1_FIFO8; set CONFIG_UA1_FIFO8 0 - global CONFIG_UA1_FIFO16; set CONFIG_UA1_FIFO16 0 - global CONFIG_UA1_FIFO32; set CONFIG_UA1_FIFO32 0 - global CONFIG_UA2_FIFO1; set CONFIG_UA2_FIFO1 0 - global CONFIG_UA2_FIFO2; set CONFIG_UA2_FIFO2 0 - global CONFIG_UA2_FIFO4; set CONFIG_UA2_FIFO4 0 - global CONFIG_UA2_FIFO8; set CONFIG_UA2_FIFO8 0 - global CONFIG_UA2_FIFO16; set CONFIG_UA2_FIFO16 0 - global CONFIG_UA2_FIFO32; set CONFIG_UA2_FIFO32 0 -} - - -proc update_choices { } { - global tmpvar_0 - set tmpvar_0 "Inferred" - global CONFIG_SYN_INFERRED - if { $CONFIG_SYN_INFERRED == 1 } then { set tmpvar_0 "Inferred" } - global CONFIG_SYN_STRATIX - if { $CONFIG_SYN_STRATIX == 1 } then { set tmpvar_0 "Altera-Stratix" } - global CONFIG_SYN_STRATIXII - if { $CONFIG_SYN_STRATIXII == 1 } then { set tmpvar_0 "Altera-StratixII" } - global CONFIG_SYN_STRATIXIII - if { $CONFIG_SYN_STRATIXIII == 1 } then { set tmpvar_0 "Altera-StratixIII" } - global CONFIG_SYN_CYCLONEIII - if { $CONFIG_SYN_CYCLONEIII == 1 } then { set tmpvar_0 "Altera-CycloneIII" } - global CONFIG_SYN_ALTERA - if { $CONFIG_SYN_ALTERA == 1 } then { set tmpvar_0 "Altera-Others" } - global CONFIG_SYN_AXCEL - if { $CONFIG_SYN_AXCEL == 1 } then { set tmpvar_0 "Actel-Axcelerator" } - global CONFIG_SYN_PROASIC - if { $CONFIG_SYN_PROASIC == 1 } then { set tmpvar_0 "Actel-Proasic" } - global CONFIG_SYN_PROASICPLUS - if { $CONFIG_SYN_PROASICPLUS == 1 } then { set tmpvar_0 "Actel-ProasicPlus" } - global CONFIG_SYN_PROASIC3 - if { $CONFIG_SYN_PROASIC3 == 1 } then { set tmpvar_0 "Actel-Proasic3" } - global CONFIG_SYN_UT025CRH - if { $CONFIG_SYN_UT025CRH == 1 } then { set tmpvar_0 "Aeroflex-UT025CRH" } - global CONFIG_SYN_ATC18 - if { $CONFIG_SYN_ATC18 == 1 } then { set tmpvar_0 "Atmel-ATC18" } - global CONFIG_SYN_ATC18RHA - if { $CONFIG_SYN_ATC18RHA == 1 } then { set tmpvar_0 "Atmel-ATC18RHA" } - global CONFIG_SYN_CUSTOM1 - if { $CONFIG_SYN_CUSTOM1 == 1 } then { set tmpvar_0 "Custom1" } - global CONFIG_SYN_EASIC90 - if { $CONFIG_SYN_EASIC90 == 1 } then { set tmpvar_0 "eASIC90" } - global CONFIG_SYN_IHP25 - if { $CONFIG_SYN_IHP25 == 1 } then { set tmpvar_0 "IHP25" } - global CONFIG_SYN_IHP25RH - if { $CONFIG_SYN_IHP25RH == 1 } then { set tmpvar_0 "IHP25RH" } - global CONFIG_SYN_LATTICE - if { $CONFIG_SYN_LATTICE == 1 } then { set tmpvar_0 "Lattice-EC/ECP/XP" } - global CONFIG_SYN_ECLIPSE - if { $CONFIG_SYN_ECLIPSE == 1 } then { set tmpvar_0 "Quicklogic-Eclipse" } - global CONFIG_SYN_PEREGRINE - if { $CONFIG_SYN_PEREGRINE == 1 } then { set tmpvar_0 "Peregrine" } - global CONFIG_SYN_RH_LIB18T - if { $CONFIG_SYN_RH_LIB18T == 1 } then { set tmpvar_0 "RH-LIB18T" } - global CONFIG_SYN_RHUMC - if { $CONFIG_SYN_RHUMC == 1 } then { set tmpvar_0 "RH-UMC" } - global CONFIG_SYN_SMIC13 - if { $CONFIG_SYN_SMIC13 == 1 } then { set tmpvar_0 "SMIC130" } - global CONFIG_SYN_SPARTAN2 - if { $CONFIG_SYN_SPARTAN2 == 1 } then { set tmpvar_0 "Xilinx-Spartan2" } - global CONFIG_SYN_SPARTAN3 - if { $CONFIG_SYN_SPARTAN3 == 1 } then { set tmpvar_0 "Xilinx-Spartan3" } - global CONFIG_SYN_SPARTAN3E - if { $CONFIG_SYN_SPARTAN3E == 1 } then { set tmpvar_0 "Xilinx-Spartan3E" } - global CONFIG_SYN_VIRTEX - if { $CONFIG_SYN_VIRTEX == 1 } then { set tmpvar_0 "Xilinx-Virtex" } - global CONFIG_SYN_VIRTEXE - if { $CONFIG_SYN_VIRTEXE == 1 } then { set tmpvar_0 "Xilinx-VirtexE" } - global CONFIG_SYN_VIRTEX2 - if { $CONFIG_SYN_VIRTEX2 == 1 } then { set tmpvar_0 "Xilinx-Virtex2" } - global CONFIG_SYN_VIRTEX4 - if { $CONFIG_SYN_VIRTEX4 == 1 } then { set tmpvar_0 "Xilinx-Virtex4" } - global CONFIG_SYN_VIRTEX5 - if { $CONFIG_SYN_VIRTEX5 == 1 } then { set tmpvar_0 "Xilinx-Virtex5" } - global CONFIG_SYN_UMC - if { $CONFIG_SYN_UMC == 1 } then { set tmpvar_0 "UMC180" } - global CONFIG_SYN_TSMC90 - if { $CONFIG_SYN_TSMC90 == 1 } then { set tmpvar_0 "TSMC90" } - global tmpvar_1 - set tmpvar_1 "Inferred" - global CONFIG_MEM_INFERRED - if { $CONFIG_MEM_INFERRED == 1 } then { set tmpvar_1 "Inferred" } - global CONFIG_MEM_UMC - if { $CONFIG_MEM_UMC == 1 } then { set tmpvar_1 "UMC18" } - global CONFIG_MEM_RHUMC - if { $CONFIG_MEM_RHUMC == 1 } then { set tmpvar_1 "RH-UMC" } - global CONFIG_MEM_ARTISAN - if { $CONFIG_MEM_ARTISAN == 1 } then { set tmpvar_1 "Artisan" } - global CONFIG_MEM_CUSTOM1 - if { $CONFIG_MEM_CUSTOM1 == 1 } then { set tmpvar_1 "Custom1" } - global CONFIG_MEM_VIRAGE - if { $CONFIG_MEM_VIRAGE == 1 } then { set tmpvar_1 "Virage" } - global CONFIG_MEM_VIRAGE90 - if { $CONFIG_MEM_VIRAGE90 == 1 } then { set tmpvar_1 "Virage-TSMC90" } - global tmpvar_2 - set tmpvar_2 "Inferred" - global CONFIG_CLK_INFERRED - if { $CONFIG_CLK_INFERRED == 1 } then { set tmpvar_2 "Inferred" } - global CONFIG_CLK_HCLKBUF - if { $CONFIG_CLK_HCLKBUF == 1 } then { set tmpvar_2 "Actel-HCLKBUF" } - global CONFIG_CLK_ALTDLL - if { $CONFIG_CLK_ALTDLL == 1 } then { set tmpvar_2 "Altera-ALTPLL" } - global CONFIG_CLK_LATDLL - if { $CONFIG_CLK_LATDLL == 1 } then { set tmpvar_2 "Lattice-EXPLL" } - global CONFIG_CLK_PRO3PLL - if { $CONFIG_CLK_PRO3PLL == 1 } then { set tmpvar_2 "Proasic3-PLLL" } - global CONFIG_CLK_LIB18T - if { $CONFIG_CLK_LIB18T == 1 } then { set tmpvar_2 "RH-LIB18T-PLL" } - global CONFIG_CLK_RHUMC - if { $CONFIG_CLK_RHUMC == 1 } then { set tmpvar_2 "DARE-PLL" } - global CONFIG_CLK_CLKDLL - if { $CONFIG_CLK_CLKDLL == 1 } then { set tmpvar_2 "Xilinx-CLKDLL" } - global CONFIG_CLK_DCM - if { $CONFIG_CLK_DCM == 1 } then { set tmpvar_2 "Xilinx-DCM" } - global tmpvar_3 - set tmpvar_3 "5-cycles" - global CONFIG_IU_MUL_LATENCY_2 - if { $CONFIG_IU_MUL_LATENCY_2 == 1 } then { set tmpvar_3 "2-cycles" } - global CONFIG_IU_MUL_LATENCY_4 - if { $CONFIG_IU_MUL_LATENCY_4 == 1 } then { set tmpvar_3 "4-cycles" } - global CONFIG_IU_MUL_LATENCY_5 - if { $CONFIG_IU_MUL_LATENCY_5 == 1 } then { set tmpvar_3 "5-cycles" } - global tmpvar_4 - set tmpvar_4 "GRFPU" - global CONFIG_FPU_GRFPU - if { $CONFIG_FPU_GRFPU == 1 } then { set tmpvar_4 "GRFPU" } - global CONFIG_FPU_GRFPULITE - if { $CONFIG_FPU_GRFPULITE == 1 } then { set tmpvar_4 "GRFPU-LITE" } - global CONFIG_FPU_MEIKO - if { $CONFIG_FPU_MEIKO == 1 } then { set tmpvar_4 "Meiko" } - global tmpvar_5 - set tmpvar_5 "Inferred" - global CONFIG_FPU_GRFPU_INFMUL - if { $CONFIG_FPU_GRFPU_INFMUL == 1 } then { set tmpvar_5 "Inferred" } - global CONFIG_FPU_GRFPU_DWMUL - if { $CONFIG_FPU_GRFPU_DWMUL == 1 } then { set tmpvar_5 "DW" } - global CONFIG_FPU_GRFPU_MODGEN - if { $CONFIG_FPU_GRFPU_MODGEN == 1 } then { set tmpvar_5 "ModGen" } - global tmpvar_6 - set tmpvar_6 "Simple" - global CONFIG_FPU_GRFPC0 - if { $CONFIG_FPU_GRFPC0 == 1 } then { set tmpvar_6 "Simple" } - global CONFIG_FPU_GRFPC1 - if { $CONFIG_FPU_GRFPC1 == 1 } then { set tmpvar_6 "Data-forwarding" } - global CONFIG_FPU_GRFPC2 - if { $CONFIG_FPU_GRFPC2 == 1 } then { set tmpvar_6 "Non-blocking" } - global tmpvar_7 - set tmpvar_7 "1" - global CONFIG_ICACHE_ASSO1 - if { $CONFIG_ICACHE_ASSO1 == 1 } then { set tmpvar_7 "1" } - global CONFIG_ICACHE_ASSO2 - if { $CONFIG_ICACHE_ASSO2 == 1 } then { set tmpvar_7 "2" } - global CONFIG_ICACHE_ASSO3 - if { $CONFIG_ICACHE_ASSO3 == 1 } then { set tmpvar_7 "3" } - global CONFIG_ICACHE_ASSO4 - if { $CONFIG_ICACHE_ASSO4 == 1 } then { set tmpvar_7 "4" } - global tmpvar_8 - set tmpvar_8 "4" - global CONFIG_ICACHE_SZ1 - if { $CONFIG_ICACHE_SZ1 == 1 } then { set tmpvar_8 "1" } - global CONFIG_ICACHE_SZ2 - if { $CONFIG_ICACHE_SZ2 == 1 } then { set tmpvar_8 "2" } - global CONFIG_ICACHE_SZ4 - if { $CONFIG_ICACHE_SZ4 == 1 } then { set tmpvar_8 "4" } - global CONFIG_ICACHE_SZ8 - if { $CONFIG_ICACHE_SZ8 == 1 } then { set tmpvar_8 "8" } - global CONFIG_ICACHE_SZ16 - if { $CONFIG_ICACHE_SZ16 == 1 } then { set tmpvar_8 "16" } - global CONFIG_ICACHE_SZ32 - if { $CONFIG_ICACHE_SZ32 == 1 } then { set tmpvar_8 "32" } - global CONFIG_ICACHE_SZ64 - if { $CONFIG_ICACHE_SZ64 == 1 } then { set tmpvar_8 "64" } - global CONFIG_ICACHE_SZ128 - if { $CONFIG_ICACHE_SZ128 == 1 } then { set tmpvar_8 "128" } - global CONFIG_ICACHE_SZ256 - if { $CONFIG_ICACHE_SZ256 == 1 } then { set tmpvar_8 "256" } - global tmpvar_9 - set tmpvar_9 "32" - global CONFIG_ICACHE_LZ16 - if { $CONFIG_ICACHE_LZ16 == 1 } then { set tmpvar_9 "16" } - global CONFIG_ICACHE_LZ32 - if { $CONFIG_ICACHE_LZ32 == 1 } then { set tmpvar_9 "32" } - global tmpvar_10 - set tmpvar_10 "Random" - global CONFIG_ICACHE_ALGORND - if { $CONFIG_ICACHE_ALGORND == 1 } then { set tmpvar_10 "Random" } - global CONFIG_ICACHE_ALGOLRR - if { $CONFIG_ICACHE_ALGOLRR == 1 } then { set tmpvar_10 "LRR" } - global CONFIG_ICACHE_ALGOLRU - if { $CONFIG_ICACHE_ALGOLRU == 1 } then { set tmpvar_10 "LRU" } - global tmpvar_11 - set tmpvar_11 "4" - global CONFIG_ICACHE_LRAM_SZ1 - if { $CONFIG_ICACHE_LRAM_SZ1 == 1 } then { set tmpvar_11 "1" } - global CONFIG_ICACHE_LRAM_SZ2 - if { $CONFIG_ICACHE_LRAM_SZ2 == 1 } then { set tmpvar_11 "2" } - global CONFIG_ICACHE_LRAM_SZ4 - if { $CONFIG_ICACHE_LRAM_SZ4 == 1 } then { set tmpvar_11 "4" } - global CONFIG_ICACHE_LRAM_SZ8 - if { $CONFIG_ICACHE_LRAM_SZ8 == 1 } then { set tmpvar_11 "8" } - global CONFIG_ICACHE_LRAM_SZ16 - if { $CONFIG_ICACHE_LRAM_SZ16 == 1 } then { set tmpvar_11 "16" } - global CONFIG_ICACHE_LRAM_SZ32 - if { $CONFIG_ICACHE_LRAM_SZ32 == 1 } then { set tmpvar_11 "32" } - global CONFIG_ICACHE_LRAM_SZ64 - if { $CONFIG_ICACHE_LRAM_SZ64 == 1 } then { set tmpvar_11 "64" } - global CONFIG_ICACHE_LRAM_SZ128 - if { $CONFIG_ICACHE_LRAM_SZ128 == 1 } then { set tmpvar_11 "128" } - global CONFIG_ICACHE_LRAM_SZ256 - if { $CONFIG_ICACHE_LRAM_SZ256 == 1 } then { set tmpvar_11 "256" } - global tmpvar_12 - set tmpvar_12 "1" - global CONFIG_DCACHE_ASSO1 - if { $CONFIG_DCACHE_ASSO1 == 1 } then { set tmpvar_12 "1" } - global CONFIG_DCACHE_ASSO2 - if { $CONFIG_DCACHE_ASSO2 == 1 } then { set tmpvar_12 "2" } - global CONFIG_DCACHE_ASSO3 - if { $CONFIG_DCACHE_ASSO3 == 1 } then { set tmpvar_12 "3" } - global CONFIG_DCACHE_ASSO4 - if { $CONFIG_DCACHE_ASSO4 == 1 } then { set tmpvar_12 "4" } - global tmpvar_13 - set tmpvar_13 "4" - global CONFIG_DCACHE_SZ1 - if { $CONFIG_DCACHE_SZ1 == 1 } then { set tmpvar_13 "1" } - global CONFIG_DCACHE_SZ2 - if { $CONFIG_DCACHE_SZ2 == 1 } then { set tmpvar_13 "2" } - global CONFIG_DCACHE_SZ4 - if { $CONFIG_DCACHE_SZ4 == 1 } then { set tmpvar_13 "4" } - global CONFIG_DCACHE_SZ8 - if { $CONFIG_DCACHE_SZ8 == 1 } then { set tmpvar_13 "8" } - global CONFIG_DCACHE_SZ16 - if { $CONFIG_DCACHE_SZ16 == 1 } then { set tmpvar_13 "16" } - global CONFIG_DCACHE_SZ32 - if { $CONFIG_DCACHE_SZ32 == 1 } then { set tmpvar_13 "32" } - global CONFIG_DCACHE_SZ64 - if { $CONFIG_DCACHE_SZ64 == 1 } then { set tmpvar_13 "64" } - global CONFIG_DCACHE_SZ128 - if { $CONFIG_DCACHE_SZ128 == 1 } then { set tmpvar_13 "128" } - global CONFIG_DCACHE_SZ256 - if { $CONFIG_DCACHE_SZ256 == 1 } then { set tmpvar_13 "256" } - global tmpvar_14 - set tmpvar_14 "32" - global CONFIG_DCACHE_LZ16 - if { $CONFIG_DCACHE_LZ16 == 1 } then { set tmpvar_14 "16" } - global CONFIG_DCACHE_LZ32 - if { $CONFIG_DCACHE_LZ32 == 1 } then { set tmpvar_14 "32" } - global tmpvar_15 - set tmpvar_15 "Random" - global CONFIG_DCACHE_ALGORND - if { $CONFIG_DCACHE_ALGORND == 1 } then { set tmpvar_15 "Random" } - global CONFIG_DCACHE_ALGOLRR - if { $CONFIG_DCACHE_ALGOLRR == 1 } then { set tmpvar_15 "LRR" } - global CONFIG_DCACHE_ALGOLRU - if { $CONFIG_DCACHE_ALGOLRU == 1 } then { set tmpvar_15 "LRU" } - global tmpvar_16 - set tmpvar_16 "4" - global CONFIG_DCACHE_LRAM_SZ1 - if { $CONFIG_DCACHE_LRAM_SZ1 == 1 } then { set tmpvar_16 "1" } - global CONFIG_DCACHE_LRAM_SZ2 - if { $CONFIG_DCACHE_LRAM_SZ2 == 1 } then { set tmpvar_16 "2" } - global CONFIG_DCACHE_LRAM_SZ4 - if { $CONFIG_DCACHE_LRAM_SZ4 == 1 } then { set tmpvar_16 "4" } - global CONFIG_DCACHE_LRAM_SZ8 - if { $CONFIG_DCACHE_LRAM_SZ8 == 1 } then { set tmpvar_16 "8" } - global CONFIG_DCACHE_LRAM_SZ16 - if { $CONFIG_DCACHE_LRAM_SZ16 == 1 } then { set tmpvar_16 "16" } - global CONFIG_DCACHE_LRAM_SZ32 - if { $CONFIG_DCACHE_LRAM_SZ32 == 1 } then { set tmpvar_16 "32" } - global CONFIG_DCACHE_LRAM_SZ64 - if { $CONFIG_DCACHE_LRAM_SZ64 == 1 } then { set tmpvar_16 "64" } - global CONFIG_DCACHE_LRAM_SZ128 - if { $CONFIG_DCACHE_LRAM_SZ128 == 1 } then { set tmpvar_16 "128" } - global CONFIG_DCACHE_LRAM_SZ256 - if { $CONFIG_DCACHE_LRAM_SZ256 == 1 } then { set tmpvar_16 "256" } - global tmpvar_17 - set tmpvar_17 "combined" - global CONFIG_MMU_COMBINED - if { $CONFIG_MMU_COMBINED == 1 } then { set tmpvar_17 "combined" } - global CONFIG_MMU_SPLIT - if { $CONFIG_MMU_SPLIT == 1 } then { set tmpvar_17 "split" } - global tmpvar_18 - set tmpvar_18 "Increment" - global CONFIG_MMU_REPARRAY - if { $CONFIG_MMU_REPARRAY == 1 } then { set tmpvar_18 "LRU" } - global CONFIG_MMU_REPINCREMENT - if { $CONFIG_MMU_REPINCREMENT == 1 } then { set tmpvar_18 "Increment" } - global tmpvar_19 - set tmpvar_19 "8" - global CONFIG_MMU_I2 - if { $CONFIG_MMU_I2 == 1 } then { set tmpvar_19 "2" } - global CONFIG_MMU_I4 - if { $CONFIG_MMU_I4 == 1 } then { set tmpvar_19 "4" } - global CONFIG_MMU_I8 - if { $CONFIG_MMU_I8 == 1 } then { set tmpvar_19 "8" } - global CONFIG_MMU_I16 - if { $CONFIG_MMU_I16 == 1 } then { set tmpvar_19 "16" } - global CONFIG_MMU_I32 - if { $CONFIG_MMU_I32 == 1 } then { set tmpvar_19 "32" } - global tmpvar_20 - set tmpvar_20 "8" - global CONFIG_MMU_D2 - if { $CONFIG_MMU_D2 == 1 } then { set tmpvar_20 "2" } - global CONFIG_MMU_D4 - if { $CONFIG_MMU_D4 == 1 } then { set tmpvar_20 "4" } - global CONFIG_MMU_D8 - if { $CONFIG_MMU_D8 == 1 } then { set tmpvar_20 "8" } - global CONFIG_MMU_D16 - if { $CONFIG_MMU_D16 == 1 } then { set tmpvar_20 "16" } - global CONFIG_MMU_D32 - if { $CONFIG_MMU_D32 == 1 } then { set tmpvar_20 "32" } - global tmpvar_21 - set tmpvar_21 "4K" - global CONFIG_MMU_PAGE_4K - if { $CONFIG_MMU_PAGE_4K == 1 } then { set tmpvar_21 "4K" } - global CONFIG_MMU_PAGE_8K - if { $CONFIG_MMU_PAGE_8K == 1 } then { set tmpvar_21 "8K" } - global CONFIG_MMU_PAGE_16K - if { $CONFIG_MMU_PAGE_16K == 1 } then { set tmpvar_21 "16K" } - global CONFIG_MMU_PAGE_32K - if { $CONFIG_MMU_PAGE_32K == 1 } then { set tmpvar_21 "32K" } - global CONFIG_MMU_PAGE_PROG - if { $CONFIG_MMU_PAGE_PROG == 1 } then { set tmpvar_21 "Programmable" } - global tmpvar_22 - set tmpvar_22 "1" - global CONFIG_DSU_ITRACESZ1 - if { $CONFIG_DSU_ITRACESZ1 == 1 } then { set tmpvar_22 "1" } - global CONFIG_DSU_ITRACESZ2 - if { $CONFIG_DSU_ITRACESZ2 == 1 } then { set tmpvar_22 "2" } - global CONFIG_DSU_ITRACESZ4 - if { $CONFIG_DSU_ITRACESZ4 == 1 } then { set tmpvar_22 "4" } - global CONFIG_DSU_ITRACESZ8 - if { $CONFIG_DSU_ITRACESZ8 == 1 } then { set tmpvar_22 "8" } - global CONFIG_DSU_ITRACESZ16 - if { $CONFIG_DSU_ITRACESZ16 == 1 } then { set tmpvar_22 "16" } - global tmpvar_23 - set tmpvar_23 "1" - global CONFIG_DSU_ATRACESZ1 - if { $CONFIG_DSU_ATRACESZ1 == 1 } then { set tmpvar_23 "1" } - global CONFIG_DSU_ATRACESZ2 - if { $CONFIG_DSU_ATRACESZ2 == 1 } then { set tmpvar_23 "2" } - global CONFIG_DSU_ATRACESZ4 - if { $CONFIG_DSU_ATRACESZ4 == 1 } then { set tmpvar_23 "4" } - global CONFIG_DSU_ATRACESZ8 - if { $CONFIG_DSU_ATRACESZ8 == 1 } then { set tmpvar_23 "8" } - global CONFIG_DSU_ATRACESZ16 - if { $CONFIG_DSU_ATRACESZ16 == 1 } then { set tmpvar_23 "16" } - global tmpvar_25 - set tmpvar_25 "2" - global CONFIG_DSU_ETHSZ1 - if { $CONFIG_DSU_ETHSZ1 == 1 } then { set tmpvar_25 "1" } - global CONFIG_DSU_ETHSZ2 - if { $CONFIG_DSU_ETHSZ2 == 1 } then { set tmpvar_25 "2" } - global CONFIG_DSU_ETHSZ4 - if { $CONFIG_DSU_ETHSZ4 == 1 } then { set tmpvar_25 "4" } - global CONFIG_DSU_ETHSZ8 - if { $CONFIG_DSU_ETHSZ8 == 1 } then { set tmpvar_25 "8" } - global CONFIG_DSU_ETHSZ16 - if { $CONFIG_DSU_ETHSZ16 == 1 } then { set tmpvar_25 "16" } - global tmpvar_26 - set tmpvar_26 "1" - global CONFIG_SRCTRL_SRBANKS1 - if { $CONFIG_SRCTRL_SRBANKS1 == 1 } then { set tmpvar_26 "1" } - global CONFIG_SRCTRL_SRBANKS2 - if { $CONFIG_SRCTRL_SRBANKS2 == 1 } then { set tmpvar_26 "2" } - global CONFIG_SRCTRL_SRBANKS3 - if { $CONFIG_SRCTRL_SRBANKS3 == 1 } then { set tmpvar_26 "3" } - global CONFIG_SRCTRL_SRBANKS4 - if { $CONFIG_SRCTRL_SRBANKS4 == 1 } then { set tmpvar_26 "4" } - global CONFIG_SRCTRL_SRBANKS5 - if { $CONFIG_SRCTRL_SRBANKS5 == 1 } then { set tmpvar_26 "5" } - global tmpvar_27 - set tmpvar_27 "0" - global CONFIG_SRCTRL_BANKSZ0 - if { $CONFIG_SRCTRL_BANKSZ0 == 1 } then { set tmpvar_27 "8" } - global CONFIG_SRCTRL_BANKSZ1 - if { $CONFIG_SRCTRL_BANKSZ1 == 1 } then { set tmpvar_27 "16" } - global CONFIG_SRCTRL_BANKSZ2 - if { $CONFIG_SRCTRL_BANKSZ2 == 1 } then { set tmpvar_27 "32" } - global CONFIG_SRCTRL_BANKSZ3 - if { $CONFIG_SRCTRL_BANKSZ3 == 1 } then { set tmpvar_27 "64" } - global CONFIG_SRCTRL_BANKSZ4 - if { $CONFIG_SRCTRL_BANKSZ4 == 1 } then { set tmpvar_27 "128" } - global CONFIG_SRCTRL_BANKSZ5 - if { $CONFIG_SRCTRL_BANKSZ5 == 1 } then { set tmpvar_27 "256" } - global CONFIG_SRCTRL_BANKSZ6 - if { $CONFIG_SRCTRL_BANKSZ6 == 1 } then { set tmpvar_27 "512" } - global CONFIG_SRCTRL_BANKSZ7 - if { $CONFIG_SRCTRL_BANKSZ7 == 1 } then { set tmpvar_27 "1024" } - global CONFIG_SRCTRL_BANKSZ8 - if { $CONFIG_SRCTRL_BANKSZ8 == 1 } then { set tmpvar_27 "2048" } - global CONFIG_SRCTRL_BANKSZ9 - if { $CONFIG_SRCTRL_BANKSZ9 == 1 } then { set tmpvar_27 "4096" } - global CONFIG_SRCTRL_BANKSZ10 - if { $CONFIG_SRCTRL_BANKSZ10 == 1 } then { set tmpvar_27 "8192" } - global CONFIG_SRCTRL_BANKSZ11 - if { $CONFIG_SRCTRL_BANKSZ11 == 1 } then { set tmpvar_27 "16384" } - global CONFIG_SRCTRL_BANKSZ12 - if { $CONFIG_SRCTRL_BANKSZ12 == 1 } then { set tmpvar_27 "32768" } - global CONFIG_SRCTRL_BANKSZ13 - if { $CONFIG_SRCTRL_BANKSZ13 == 1 } then { set tmpvar_27 "65536" } - global tmpvar_28 - set tmpvar_28 "4" - global CONFIG_AHBRAM_SZ1 - if { $CONFIG_AHBRAM_SZ1 == 1 } then { set tmpvar_28 "1" } - global CONFIG_AHBRAM_SZ2 - if { $CONFIG_AHBRAM_SZ2 == 1 } then { set tmpvar_28 "2" } - global CONFIG_AHBRAM_SZ4 - if { $CONFIG_AHBRAM_SZ4 == 1 } then { set tmpvar_28 "4" } - global CONFIG_AHBRAM_SZ8 - if { $CONFIG_AHBRAM_SZ8 == 1 } then { set tmpvar_28 "8" } - global CONFIG_AHBRAM_SZ16 - if { $CONFIG_AHBRAM_SZ16 == 1 } then { set tmpvar_28 "16" } - global CONFIG_AHBRAM_SZ32 - if { $CONFIG_AHBRAM_SZ32 == 1 } then { set tmpvar_28 "32" } - global CONFIG_AHBRAM_SZ64 - if { $CONFIG_AHBRAM_SZ64 == 1 } then { set tmpvar_28 "64" } - global tmpvar_29 - set tmpvar_29 "8" - global CONFIG_GRETH_FIFO4 - if { $CONFIG_GRETH_FIFO4 == 1 } then { set tmpvar_29 "4" } - global CONFIG_GRETH_FIFO8 - if { $CONFIG_GRETH_FIFO8 == 1 } then { set tmpvar_29 "8" } - global CONFIG_GRETH_FIFO16 - if { $CONFIG_GRETH_FIFO16 == 1 } then { set tmpvar_29 "16" } - global CONFIG_GRETH_FIFO32 - if { $CONFIG_GRETH_FIFO32 == 1 } then { set tmpvar_29 "32" } - global CONFIG_GRETH_FIFO64 - if { $CONFIG_GRETH_FIFO64 == 1 } then { set tmpvar_29 "64" } - global tmpvar_30 - set tmpvar_30 "8" - global CONFIG_PCI_FIFO0 - if { $CONFIG_PCI_FIFO0 == 1 } then { set tmpvar_30 "None" } - global CONFIG_PCI_FIFO8 - if { $CONFIG_PCI_FIFO8 == 1 } then { set tmpvar_30 "8" } - global CONFIG_PCI_FIFO16 - if { $CONFIG_PCI_FIFO16 == 1 } then { set tmpvar_30 "16" } - global CONFIG_PCI_FIFO32 - if { $CONFIG_PCI_FIFO32 == 1 } then { set tmpvar_30 "32" } - global CONFIG_PCI_FIFO64 - if { $CONFIG_PCI_FIFO64 == 1 } then { set tmpvar_30 "64" } - global CONFIG_PCI_FIFO128 - if { $CONFIG_PCI_FIFO128 == 1 } then { set tmpvar_30 "128" } - global tmpvar_31 - set tmpvar_31 "256" - global CONFIG_PCI_TRACE256 - if { $CONFIG_PCI_TRACE256 == 1 } then { set tmpvar_31 "256" } - global CONFIG_PCI_TRACE512 - if { $CONFIG_PCI_TRACE512 == 1 } then { set tmpvar_31 "512" } - global CONFIG_PCI_TRACE1024 - if { $CONFIG_PCI_TRACE1024 == 1 } then { set tmpvar_31 "1024" } - global CONFIG_PCI_TRACE2048 - if { $CONFIG_PCI_TRACE2048 == 1 } then { set tmpvar_31 "2048" } - global CONFIG_PCI_TRACE4096 - if { $CONFIG_PCI_TRACE4096 == 1 } then { set tmpvar_31 "4096" } - global tmpvar_32 - set tmpvar_32 "16" - global CONFIG_SPW_AHBFIFO4 - if { $CONFIG_SPW_AHBFIFO4 == 1 } then { set tmpvar_32 "4" } - global CONFIG_SPW_AHBFIFO8 - if { $CONFIG_SPW_AHBFIFO8 == 1 } then { set tmpvar_32 "8" } - global CONFIG_SPW_AHBFIFO16 - if { $CONFIG_SPW_AHBFIFO16 == 1 } then { set tmpvar_32 "16" } - global CONFIG_SPW_AHBFIFO32 - if { $CONFIG_SPW_AHBFIFO32 == 1 } then { set tmpvar_32 "32" } - global tmpvar_33 - set tmpvar_33 "16" - global CONFIG_SPW_RXFIFO16 - if { $CONFIG_SPW_RXFIFO16 == 1 } then { set tmpvar_33 "16" } - global CONFIG_SPW_RXFIFO32 - if { $CONFIG_SPW_RXFIFO32 == 1 } then { set tmpvar_33 "32" } - global CONFIG_SPW_RXFIFO64 - if { $CONFIG_SPW_RXFIFO64 == 1 } then { set tmpvar_33 "64" } - global tmpvar_34 - set tmpvar_34 "64" - global CONFIG_SPW_RMAPBUF2 - if { $CONFIG_SPW_RMAPBUF2 == 1 } then { set tmpvar_34 "64" } - global CONFIG_SPW_RMAPBUF4 - if { $CONFIG_SPW_RMAPBUF4 == 1 } then { set tmpvar_34 "128" } - global CONFIG_SPW_RMAPBUF6 - if { $CONFIG_SPW_RMAPBUF6 == 1 } then { set tmpvar_34 "192" } - global CONFIG_SPW_RMAPBUF8 - if { $CONFIG_SPW_RMAPBUF8 == 1 } then { set tmpvar_34 "256" } - global tmpvar_35 - set tmpvar_35 "2" - global CONFIG_SPW_GRSPW1 - if { $CONFIG_SPW_GRSPW1 == 1 } then { set tmpvar_35 "1" } - global CONFIG_SPW_GRSPW2 - if { $CONFIG_SPW_GRSPW2 == 1 } then { set tmpvar_35 "2" } - global tmpvar_36 - set tmpvar_36 "DDR" - global CONFIG_SPW_RX_SDR - if { $CONFIG_SPW_RX_SDR == 1 } then { set tmpvar_36 "SDR" } - global CONFIG_SPW_RX_DDR - if { $CONFIG_SPW_RX_DDR == 1 } then { set tmpvar_36 "DDR" } - global CONFIG_SPW_RX_XOR - if { $CONFIG_SPW_RX_XOR == 1 } then { set tmpvar_36 "Xor" } - global CONFIG_SPW_RX_AFLEX - if { $CONFIG_SPW_RX_AFLEX == 1 } then { set tmpvar_36 "Aeroflex" } - global tmpvar_37 - set tmpvar_37 "SDR" - global CONFIG_SPW_TX_SDR - if { $CONFIG_SPW_TX_SDR == 1 } then { set tmpvar_37 "SDR" } - global CONFIG_SPW_TX_DDR - if { $CONFIG_SPW_TX_DDR == 1 } then { set tmpvar_37 "DDR" } - global CONFIG_SPW_TX_AFLEX - if { $CONFIG_SPW_TX_AFLEX == 1 } then { set tmpvar_37 "Aeroflex" } - global tmpvar_38 - set tmpvar_38 "1" - global CONFIG_UA1_FIFO1 - if { $CONFIG_UA1_FIFO1 == 1 } then { set tmpvar_38 "1" } - global CONFIG_UA1_FIFO2 - if { $CONFIG_UA1_FIFO2 == 1 } then { set tmpvar_38 "2" } - global CONFIG_UA1_FIFO4 - if { $CONFIG_UA1_FIFO4 == 1 } then { set tmpvar_38 "4" } - global CONFIG_UA1_FIFO8 - if { $CONFIG_UA1_FIFO8 == 1 } then { set tmpvar_38 "8" } - global CONFIG_UA1_FIFO16 - if { $CONFIG_UA1_FIFO16 == 1 } then { set tmpvar_38 "16" } - global CONFIG_UA1_FIFO32 - if { $CONFIG_UA1_FIFO32 == 1 } then { set tmpvar_38 "32" } - global tmpvar_39 - set tmpvar_39 "1" - global CONFIG_UA2_FIFO1 - if { $CONFIG_UA2_FIFO1 == 1 } then { set tmpvar_39 "1" } - global CONFIG_UA2_FIFO2 - if { $CONFIG_UA2_FIFO2 == 1 } then { set tmpvar_39 "2" } - global CONFIG_UA2_FIFO4 - if { $CONFIG_UA2_FIFO4 == 1 } then { set tmpvar_39 "4" } - global CONFIG_UA2_FIFO8 - if { $CONFIG_UA2_FIFO8 == 1 } then { set tmpvar_39 "8" } - global CONFIG_UA2_FIFO16 - if { $CONFIG_UA2_FIFO16 == 1 } then { set tmpvar_39 "16" } - global CONFIG_UA2_FIFO32 - if { $CONFIG_UA2_FIFO32 == 1 } then { set tmpvar_39 "32" } -} - - -proc update_define_mainmenu {} { - global CONFIG_MODULES -} - - -# FILE: tail.tk -# This file is boilerplate TCL/TK function definitions for 'make xconfig'. -# -# CHANGES -# ======= -# -# 8 January 1998, Michael Elizabeth Chastain, -# Arrange buttons in three columns for better screen fitting. -# - -# -# Read the user's settings from .config. These will override whatever is -# in config.in. Don't do this if the user specified a -D to force -# the defaults. -# - -set defaults defconfig - -if { [file readable .config] == 1} then { - if { $argc > 0 } then { - if { [lindex $argv 0] != "-D" } then { - read_config .config - } - else - { - read_config $defaults - } - } else { - read_config .config - } -} else { - read_config $defaults -} - -update_define 1 $total_menus 0 -update_mainmenu - -button .f0.right.save -anchor w -text "Save and Exit" -underline 0\ - -command { catch {exec cp -f .config .config.old}; \ - writeconfig .config config.h; wrapup .wrap } - -button .f0.right.quit -anchor w -text "Quit Without Saving" -underline 0\ - -command { maybe_exit .maybe } - -button .f0.right.load -anchor w -text "Load Configuration from File" \ - -command { load_configfile .load "Load Configuration from file" read_config_file -} - -button .f0.right.store -anchor w -text "Store Configuration to File" \ - -command { load_configfile .load "Store Configuration to file" write_config_file } - -# -# Now pack everything. -# - -pack .f0.right.store .f0.right.load .f0.right.quit .f0.right.save \ - -padx 0 -pady 0 -side bottom -fill x -pack .f0.left .f0.middle .f0.right -side left -padx 5 -pady 0 -fill y -pack .f0 -padx 5 -pady 5 - -update idletasks -set winy [expr 10 + [winfo reqheight .f0]] -set scry [lindex [wm maxsize .] 1] -set winx [expr 10 + [winfo reqwidth .f0]] -set scrx [lindex [wm maxsize .] 0] -if {$winx < $scrx} then {set maxx -1} else {set maxx $winx} -if {$winy < $scry} then {set maxy -1} else {set maxy $winy} -.f0 configure -width $winx -height $winy -wm maxsize . $maxx $maxy - -# -# If we cannot write our config files, disable the write button. -# -if { [file exists .config] == 1 } then { - if { [file writable .config] == 0 } then { - .f0.right.save configure -state disabled - } - } else { - if { [file writable .] == 0 } then { - .f0.right.save configure -state disabled - } - } - -#if { [file exists include/linux/autoconf.h] == 1 } then { -# if { [file writable include/linux/autoconf.h] == 0 } then { -# .f0.right.save configure -state disabled -# } -# } else { -# if { [file writable include/linux/] == 0 } then { -# .f0.right.save configure -state disabled -# } -# } diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/leon3mp.vhd b/designs/ProjetBlanc-LeonLPP-A3PE3kL/leon3mp.vhd deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/leon3mp.vhd +++ /dev/null @@ -1,343 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -library techmap; -use techmap.gencomp.all; -library gaisler; -use gaisler.memctrl.all; -use gaisler.leon3.all; -use gaisler.uart.all; -use gaisler.misc.all; -library esa; -use esa.memoryctrl.all; -use work.config.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.lpp_memory.all; -use lpp.lpp_uart.all; -use lpp.lpp_matrix.all; -use lpp.lpp_delay.all; -use lpp.lpp_fft.all; -use lpp.fft_components.all; -use lpp.lpp_ad_conv.all; -use lpp.iir_filter.all; -use lpp.general_purpose.all; -use lpp.Filtercfg.all; - -entity leon3mp is - generic ( - fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console - pclow : integer := CFG_PCLOW - ); - port ( - clk50MHz : in std_ulogic; - reset : in std_ulogic; - ramclk : out std_logic; - - ahbrxd : in std_ulogic; -- DSU rx data - ahbtxd : out std_ulogic; -- DSU tx data - dsubre : in std_ulogic; - dsuact : out std_ulogic; - urxd1 : in std_ulogic; -- UART1 rx data - utxd1 : out std_ulogic; -- UART1 tx data - errorn : out std_ulogic; - - address : out std_logic_vector(18 downto 0); - data : inout std_logic_vector(31 downto 0); - gpio : inout std_logic_vector(6 downto 0); -- I/O port - - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------In/Out----------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - led : out std_logic_vector(1 downto 0) - ); -end; - -architecture Behavioral of leon3mp is - -constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG; -constant maxahbm : integer := maxahbmsp; - ---Clk & Rst géné -signal vcc : std_logic_vector(4 downto 0); -signal gnd : std_logic_vector(4 downto 0); -signal resetnl : std_ulogic; -signal clk2x : std_ulogic; -signal lclk : std_ulogic; -signal lclk2x : std_ulogic; -signal clkm : std_ulogic; -signal rstn : std_ulogic; -signal rstraw : std_ulogic; -signal pciclk : std_ulogic; -signal sdclkl : std_ulogic; -signal cgi : clkgen_in_type; -signal cgo : clkgen_out_type; ---- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); ---UART -signal ahbuarti : uart_in_type; -signal ahbuarto : uart_out_type; -signal apbuarti : uart_in_type; -signal apbuarto : uart_out_type; ---MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal wpo : wprot_out_type; -signal sdo : sdram_out_type; ---IRQ -signal irqi : irq_in_vector(0 to CFG_NCPU-1); -signal irqo : irq_out_vector(0 to CFG_NCPU-1); ---Timer -signal gpti : gptimer_in_type; -signal gpto : gptimer_out_type; ---GPIO -signal gpioi : gpio_in_type; -signal gpioo : gpio_out_type; ---DSU -signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); -signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); -signal dsui : dsu_in_type; -signal dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- -constant IOAEN : integer := CFG_CAN; -constant boardfreq : integer := 50000; - -begin - ---------------------------------------------------------------------- ---- AJOUT TEST -------------------------------------IPs------------- ---------------------------------------------------------------------- - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (others => '1'); gnd <= (others => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); - - clkgen0 : clkgen -- clock generator - generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; -process(lclk2x) -begin - if lclk2x'event and lclk2x = '1' then - lclk <= not lclk; - end if; -end process; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : if CFG_LEON3 = 1 generate - cpu : for i in 0 to CFG_NCPU-1 generate - u0 : leon3s -- LEON3 processor - generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - end generate; - errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); - - dsugen : if CFG_DSU = 1 generate - dsu0 : dsu3 -- LEON3 Debug Support Unit - generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); --- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); - dsui.enable <= '1'; - dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); - dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); - end generate; - end generate; - - nodsu : if CFG_DSU = 0 generate - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - end generate; - - irqctrl : if CFG_IRQ3_ENABLE /= 0 generate - irqctrl0 : irqmp -- interrupt controller - generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - port map (rstn, clkm, apbi, apbo(2), irqo, irqi); - end generate; - irq3 : if CFG_IRQ3_ENABLE = 0 generate - x : for i in 0 to CFG_NCPU-1 generate - irqi(i).irl <= "0000"; - end generate; - apbo(2) <= apb_none; - end generate; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - - memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - bdr : for i in 0 to 3 generate - data_pad : iopadv generic map (tech => padtech, width => 8) - port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), - memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); - end generate; - - - addr_pad : outpadv generic map (width => 19, tech => padtech) - port map (address, memo.address(20 downto 2)); - - - SSRAM_0:entity ssram_plugin - generic map (tech => padtech) - port map - (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - dcomgen : if CFG_AHB_UART = 1 generate - dcom0: ahbuart -- Debug UART - generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); - dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); - led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; - end generate; - nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR) - port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - - gpt : if CFG_GPT_ENABLE /= 0 generate - timer0 : gptimer -- timer unit - generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - port map (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; --- led(4) <= gpto.wdog; - end generate; - notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - ua1 : if CFG_UART1_ENABLE /= 0 generate - uart1 : apbuart -- UART 1 - generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); - apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; --- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; - end generate; - noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit - grgpio0: grgpio - generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) - port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : for i in 0 to 6 generate - pio_pad : iopad generic map (tech => padtech) - port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - end generate; - end generate; - - -end Behavioral; \ No newline at end of file diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/leon3mp_libero.prj.convert.8.6.bak b/designs/ProjetBlanc-LeonLPP-A3PE3kL/leon3mp_libero.prj.convert.8.6.bak deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/leon3mp_libero.prj.convert.8.6.bak +++ /dev/null @@ -1,2622 +0,0 @@ -KEY LIBERO "8.6" -KEY CAPTURE "8.6.2.10" -KEY HDLTechnology "VHDL" -KEY VendorTechnology_Family "Virtex2" -KEY VendorTechnology_Die "" -KEY VendorTechnology_Package "" -KEY ProjectLocation "." -KEY SimulationType "VHDL" -KEY Vendor "Actel" -KEY ActiveRoot "leon3mp" -LIST REVISIONS -VALUE="Impl1",NUM=1 -CURREV=1 -ENDLIST -LIST LIBRARIES -grlib -secureip -eclipsee -synplify -techmap -spw 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"/../../lib/gleichmann/ac97/ac97.vhd,hdl" -VALUE "/../../lib/gleichmann/ac97/ac97_oc.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/spi_slave_model.v,hdl" -VALUE "/../../lib/gleichmann/sim/txt_util.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/phy_ext.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/uart_ext.vhd,hdl" -VALUE "/../../lib/fmf/utilities/conversions.vhd,hdl" -VALUE "/../../lib/fmf/utilities/gen_utils.vhd,hdl" -VALUE "/../../lib/fmf/flash/flash.vhd,hdl" -VALUE "/../../lib/fmf/flash/s25fl064a.vhd,hdl" -VALUE "/../../lib/fmf/flash/m25p80.vhd,hdl" -VALUE "/../../lib/fmf/fifo/idt7202.vhd,hdl" -VALUE "/../../lib/gsi/ssram/functions.vhd,hdl" -VALUE "/../../lib/gsi/ssram/core_burst.vhd,hdl" -VALUE "/../../lib/gsi/ssram/g880e18bt.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTER.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/ALU.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Adder.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Clk_divider.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_MUX.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_REG.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MUX2.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Multiplier.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/REG.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Shifter.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/general_purpose.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/ApbDriver.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/UART.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" -VALUE "/../../lib/cypress/ssram/components.vhd,hdl" -VALUE "/../../lib/cypress/ssram/package_utility.vhd,hdl" -VALUE "/../../lib/cypress/ssram/cy7c1354b.vhd,hdl" -VALUE "/../../lib/cypress/ssram/cy7c1380d.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/HY5PS121621F.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/components.vhd,hdl" -VALUE "/../../lib/micron/sdram/mobile_sdr.v,hdl" -VALUE "/../../lib/micron/sdram/components.vhd,hdl" -VALUE "/../../lib/micron/sdram/mt48lc16m16a2.vhd,hdl" -VALUE "/../../lib/micron/ddr/ddr2.v,hdl" -VALUE "/../../lib/micron/ddr/mobile_ddr.v,hdl" -VALUE "/../../lib/micron/ddr/ddr3.v,hdl" -VALUE "/../../lib/micron/ddr/mt46v16m16.vhd,hdl" -VALUE "/../../lib/openchip/gpio/gpio.vhd,hdl" -VALUE "/../../lib/openchip/gpio/apbgpio.vhd,hdl" -VALUE "/../../lib/openchip/charlcd/charlcd.vhd,hdl" -VALUE "/../../lib/openchip/charlcd/apbcharlcd.vhd,hdl" -VALUE "/../../lib/openchip/sui/sui.vhd,hdl" -VALUE "/../../lib/openchip/sui/apbsui.vhd,hdl" -VALUE "/../../lib/work/debug/debug.vhd,hdl" -VALUE "/../../lib/work/debug/grtestmod.vhd,hdl" -VALUE "/../../lib/work/debug/cpu_disas.vhd,hdl" -VALUE "/config.vhd,hdl" -VALUE "/ahbrom.vhd,hdl" -VALUE "/leon3mp.vhd,hdl" -ENDFILELIST -ENDLIST -ENDLIST -ENDLIST diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/linkprom b/designs/ProjetBlanc-LeonLPP-A3PE3kL/linkprom deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/linkprom +++ /dev/null @@ -1,155 +0,0 @@ -/* linkcmds - * - * $Id: linkcmds,v 1.8.2.1 2000/05/24 17:06:38 joel Exp $ - */ - -OUTPUT_ARCH(sparc) -__DYNAMIC = 0; - -/* - * The memory map looks like this: - * +--------------------+ <- low memory - * | .text | - * | etext | - * | ctor list | the ctor and dtor lists are for - * | dtor list | C++ support - * | _endtext | - * +--------------------+ - * | .data | initialized data goes here - * | _sdata | - * | _edata | - * +--------------------+ - * | .bss | - * | __bss_start | start of bss, cleared by crt0 - * | _end | start of heap, used by sbrk() - * +--------------------+ - * | heap space | - * | _ENDHEAP | - * | stack space | - * | __stack | top of stack - * +--------------------+ <- high memory - */ - - -/* Default values, can be overridden */ - -_PROM_SIZE = 2M; -_RAM_SIZE = 4M; - -_RAM_START = 0x02000000; -_RAM_END = _RAM_START + _RAM_SIZE; - -_PROM_START = 0x00000000; -_PROM_END = _PROM_START + _PROM_SIZE; - -/* - * Alternate names without leading _. - */ - -PROM_START = _PROM_START; -PROM_SIZE = _PROM_SIZE; -PROM_END = _PROM_END; - -RAM_START = _RAM_START; -RAM_SIZE = _RAM_SIZE; -RAM_END = _RAM_END; - -_LEON_REG = 0x80000000; -LEON_REG = 0x80000000; - -/* these are the maximum values */ - -MEMORY -{ - rom : ORIGIN = 0x00000000, LENGTH = 16M - ram : ORIGIN = 0x40000000, LENGTH = 1024M -} - -SECTIONS -{ - .text : - { - CREATE_OBJECT_SYMBOLS - text_start = .; - _text_start = .; - *(.text) - . = ALIGN (16); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t*) - - /* - * C++ constructors - */ - __CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - __CTOR_END__ = .; - __DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - __DTOR_END__ = .; - - _rodata_start = . ; - *(.rodata*) - *(.gnu.linkonce.r*) - _erodata = ALIGN( 0x10 ) ; - - etext = ALIGN(0x10); - _etext = .; - *(.init) - *(.fini) - *(.lit) - *(.shdata) - . = ALIGN (16); - _endtext = .; - } > rom - .dynamic : { *(.dynamic) } >ram - .got : { *(.got) } >ram - .plt : { *(.plt) } >ram - .hash : { *(.hash) } >ram - .dynrel : { *(.dynrel) } >ram - .dynsym : { *(.dynsym) } >ram - .dynstr : { *(.dynstr) } >ram - .hash : { *(.hash) } >ram - .data : - { - data_start = .; - _data_start = .; - _sdata = . ; - *(.data) - *(.gnu.linkonce.d*) - *(.gcc_except_table) - . = ALIGN(0x10); - edata = .; - _edata = .; - } > ram - .shbss : - { - *(.shbss) - } > ram - .bss : - { - __bss_start = ALIGN(0x8); - _bss_start = .; - bss_start = .; - *(.bss) - *(COMMON) - end = .; - _end = ALIGN(0x8); - __end = ALIGN(0x8); - } > ram - .jcr . (NOLOAD) : { *(.jcr) } - .stab . (NOLOAD) : - { - [ .stab ] - } - .stabstr . (NOLOAD) : - { - [ .stabstr ] - } -} diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/prom.h b/designs/ProjetBlanc-LeonLPP-A3PE3kL/prom.h deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/prom.h +++ /dev/null @@ -1,10 +0,0 @@ -#define MCFG1 0x10380233 -#define MCFG2 0xe6A26e60 -#define MCFG3 0x000ff000 -#define ASDCFG 0xfff00100 -#define DSDCFG 0xe6A06e60 -#define L2MCTRLIO 0x80000000 -#define IRQCTRL 0x80000200 -#define RAMSTART 0x40000000 -#define RAMSIZE 0x00100000 - diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/prom.srec b/designs/ProjetBlanc-LeonLPP-A3PE3kL/prom.srec deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/prom.srec +++ /dev/null @@ -1,37 +0,0 @@ -S00C000070726F6D2E737265635A -S113000081D8200003000004821060E08188400051 -S1130010819000008198000081800000A180000090 -S113002001000000030020408210600FC2A00040C5 -S11300308410000001000000010000000100000025 -S11300400100000001000000801080020100000097 -S11300500100000001000000010000000100000098 -S1130060874440008608E01F881000008A100000C2 -S11300708C1000008E100000A0100000A2100000E0 -S1130080A4100000A6100000A8100000AA10000090 -S1130090AC100000AE1000009010000092100000A0 -S11300A09410000096100000981000009A100000B0 -S11300B09C1000009E10000086A0E00116BFFFEF18 -S11300C081E00000821020028190400003000004BF -S11300D0821060E0818840000100000001000000FF -S11300E001000000834800008330600C80886001B8 -S11300F00280002401000000070000008610E1785F -S1130100C108C000C118C000C518C000C918C0008B -S1130110CD18C000D118C000D518C000D918C0002F -S1130120DD18C000E118C000E518C000E918C000DF -S1130130ED18C000F118C000F518C000F918C0008F -S1130140FD18C000010000000100000001000000D3 -S1130150010000000100000089A008420100000025 -S113016001000000010000000100000010800005F3 -S11301700100000001000000000000000000000079 -S1130180874440008730E01C8688E00F1280001608 -S11301900320000005040E008410A233C420400094 -S11301A00539A89B8410A260C4206004050003FCE8 -S11301B0C420600882103860C40040008530A00C60 -S11301C0030000048210600980A04002128000062F -S11301D0033FFC00821061000539A81B8410A26053 -S11301E0C4204000050000808210000080A0E000D0 -S11301F002800005010000008200400210BFFFFCE5 -S11302008620E0013D1003FFBC17A3E0BC2780015A -S11302109C27A0600310000081C040000100000082 -S113022000000000000000000000000000000000CA -S9030000FC diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/rhumc.dc b/designs/ProjetBlanc-LeonLPP-A3PE3kL/rhumc.dc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/rhumc.dc +++ /dev/null @@ -1,101 +0,0 @@ -/*******************************************/ -/* Script to compile leon with synopsys DC */ -/* Jiri Gaisler, Gaisler Research, 2004 */ -/*******************************************/ - -search_path = {"." "/usr/local/synlibs/DesignKit_DARE_V2.0/DesignKit/IO/syn" "/usr/local/synlibs/DesignKit_DARE_V2.0/DesignKit/CORE/syn" "/usr/local/synlibs/rhumc" "/usr/local/synopsys/libraries/syn"} -target_library = "RadHardUMC18_CORE_WCMIL.db" -link_library = "RadHardUMC18_CORE_WCMIL.db rhmem_wcmil.db Post_RH_UMC018_IOLIB_WCMIL.db" -link_library = "*" + link_library -symbol_library = "generic.sdb" -allow_newer_db_files = "true"; - -/* constraints - tailor to your own technology. An average 0.35 std-cell tech - should give you 80 - 100 MHz depending on ram access time. A 0.25 tech - should run at +150 MHz. Frequency in MHz, delays in ns ... */ - -frequency = 200 -clock_skew = 0.10 -input_setup = 2.0 -output_delay = 4.0 - -/* don't touch anything from here unless you know what you are doing */ - -include leon3mp.dc - -ungroup find(cell, "*pad*") -flatten - -group find(cell, {"sr*", "sdc", "apb*", "uart*", "timer*", "irq*" \ - "ahb*", "dsu0", "rst0", "dcom*" }) -design_name amod \ - -cell_name amod0 - -current_instance u0_0/p0 -ungroup -all -flatten -current_instance ../rf0 -ungroup -all -flatten -current_instance ../cmem0 -ungroup -all -flatten -current_instance ../../amod0 -ungroup -all -flatten -current_instance .. - -peri = 1000.0 / frequency -input_delay = peri - input_setup -tdelay = output_delay + 2 -create_clock -name "clk" -period peri -waveform { 0.0, peri / 2.0 } { "clk" } -set_wire_load_mode segmented - -set_clock_skew -plus_uncertainty clock_skew "clk" -set_clock_skew -minus_uncertainty clock_skew "clk" - -/* -set_input_delay input_delay -clock clk { \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" "brdyn" "bexcn" } - -set_max_delay tdelay -to { "errorn" "wdogn" \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" } - -set_max_delay output_delay -to { \ - "writen" "romsn[1]" "romsn[0]" "read" "oen" \ - "iosn" "rwen[3]" "rwen[2]" "rwen[1]" "rwen[0]" "ramsn[3]" \ - "ramsn[2]" "ramsn[1]" "ramsn[0]" \ - "ramoen[3]" "ramoen[2]" "ramoen[1]" "ramoen[0]" \ - "sdcsn[1]" "sdcsn[0]" "sdwen" "sdrasn" "sdcasn" \ - "sddqm[3]" "sddqm[2]" "sddqm[1]" "sddqm[0]" \ - "address[27]" "address[26]" "address[25]" "address[24]" \ - "address[23]" "address[22]" "address[21]" "address[20]" \ - "address[19]" "address[18]" "address[17]" "address[16]" \ - "address[15]" "address[14]" "address[13]" "address[12]" \ - "address[11]" "address[10]" "address[9]" "address[8]" \ - "address[7]" "address[6]" "address[5]" "address[4]" \ - "address[3]" "address[2]" "address[1]" "address[0]"} - -*/ -set_max_area 0 -set_max_transition 2.0 leon3mp -set_flatten false -design {"leon3mp.db:leon3mp"} -set_structure true -design {"leon3mp.db:leon3mp"} -boolean false -timing true - - -compile -map_effort medium -boundary_optimization - -write -f db -hier leon3mp -output leon3mp.db - -report_timing -report_area diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/sdram.srec b/designs/ProjetBlanc-LeonLPP-A3PE3kL/sdram.srec deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/sdram.srec +++ /dev/null @@ -1,19492 +0,0 @@ -S00D0000736472616D2E7372656300 -S31540000000881000000910006C81C1206C01000000BE -S31540000010A1480000A75000001080203BAC102001F2 -S3154000002091D0200001000000010000000100000006 -S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006B81C523A401000000CF -S31540000050A14800002910006981C522C8010000009E -S31540000060A14800002910006981C523340100000021 -S3154000007091D02000010000000100000001000000B6 -S3154000008091D02000010000000100000001000000A6 -S31540000090A1480000A75000001080201BAC1020098A -S315400000A091D0200001000000010000000100000086 -S315400000B091D0200001000000010000000100000076 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a/designs/ProjetBlanc-LeonLPP-A3PE3kL/tkconfig.h +++ /dev/null @@ -1,1189 +0,0 @@ -#if defined CONFIG_SYN_INFERRED -#define CONFIG_SYN_TECH inferred -#elif defined CONFIG_SYN_UMC -#define CONFIG_SYN_TECH umc -#elif defined CONFIG_SYN_RHUMC -#define CONFIG_SYN_TECH rhumc -#elif defined CONFIG_SYN_ATC18 -#define CONFIG_SYN_TECH atc18s -#elif defined CONFIG_SYN_ATC18RHA -#define CONFIG_SYN_TECH atc18rha -#elif defined CONFIG_SYN_AXCEL -#define CONFIG_SYN_TECH axcel -#elif defined CONFIG_SYN_PROASICPLUS -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_ALTERA -#define CONFIG_SYN_TECH altera -#elif defined CONFIG_SYN_STRATIX -#define CONFIG_SYN_TECH stratix1 -#elif defined CONFIG_SYN_STRATIXII -#define CONFIG_SYN_TECH stratix2 -#elif defined CONFIG_SYN_STRATIXIII -#define CONFIG_SYN_TECH stratix3 -#elif defined CONFIG_SYN_CYCLONEIII -#define CONFIG_SYN_TECH cyclone3 -#elif defined CONFIG_SYN_EASIC90 -#define CONFIG_SYN_TECH easic90 -#elif defined CONFIG_SYN_IHP25 -#define CONFIG_SYN_TECH ihp25 -#elif defined CONFIG_SYN_IHP25RH -#define CONFIG_SYN_TECH ihp25rh -#elif defined CONFIG_SYN_LATTICE -#define CONFIG_SYN_TECH lattice -#elif defined CONFIG_SYN_ECLIPSE -#define CONFIG_SYN_TECH eclipse -#elif defined CONFIG_SYN_PEREGRINE -#define CONFIG_SYN_TECH peregrine -#elif defined CONFIG_SYN_PROASIC -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_PROASIC3 -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_SPARTAN2 -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEX -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEXE -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_SPARTAN3 -#define CONFIG_SYN_TECH spartan3 -#elif defined CONFIG_SYN_SPARTAN3E -#define CONFIG_SYN_TECH spartan3e -#elif defined CONFIG_SYN_VIRTEX2 -#define CONFIG_SYN_TECH virtex2 -#elif defined CONFIG_SYN_VIRTEX4 -#define CONFIG_SYN_TECH virtex4 -#elif defined CONFIG_SYN_VIRTEX5 -#define CONFIG_SYN_TECH virtex5 -#elif defined CONFIG_SYN_RH_LIB18T -#define CONFIG_SYN_TECH rhlib18t -#elif defined CONFIG_SYN_SMIC13 -#define CONFIG_SYN_TECH smic013 -#elif defined CONFIG_SYN_UT025CRH -#define CONFIG_SYN_TECH ut25 -#elif defined CONFIG_SYN_TSMC90 -#define CONFIG_SYN_TECH tsmc90 -#elif defined CONFIG_SYN_CUSTOM1 -#define CONFIG_SYN_TECH custom1 -#else -#error "unknown target technology" -#endif - -#if defined CONFIG_SYN_INFER_RAM -#define CFG_RAM_TECH inferred -#elif defined CONFIG_MEM_UMC -#define CFG_RAM_TECH umc -#elif defined CONFIG_MEM_RHUMC -#define CFG_RAM_TECH rhumc -#elif defined CONFIG_MEM_VIRAGE -#define CFG_RAM_TECH memvirage -#elif defined CONFIG_MEM_ARTISAN -#define CFG_RAM_TECH memartisan -#elif defined CONFIG_MEM_CUSTOM1 -#define CFG_RAM_TECH custom1 -#elif defined CONFIG_MEM_VIRAGE90 -#define CFG_RAM_TECH memvirage90 -#elif defined CONFIG_MEM_INFERRED -#define CFG_RAM_TECH inferred -#else -#define CFG_RAM_TECH CONFIG_SYN_TECH -#endif - -#if defined CONFIG_SYN_INFER_PADS -#define CFG_PAD_TECH inferred -#else -#define CFG_PAD_TECH CONFIG_SYN_TECH -#endif - -#ifndef CONFIG_SYN_NO_ASYNC -#define CONFIG_SYN_NO_ASYNC 0 -#endif - -#ifndef CONFIG_SYN_SCAN -#define CONFIG_SYN_SCAN 0 -#endif - - -#if defined CONFIG_CLK_ALTDLL -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_HCLKBUF -#define CFG_CLK_TECH axcel -#elif defined CONFIG_CLK_LATDLL -#define CFG_CLK_TECH lattice -#elif defined CONFIG_CLK_PRO3PLL -#define CFG_CLK_TECH apa3 -#elif defined CONFIG_CLK_CLKDLL -#define CFG_CLK_TECH virtex -#elif defined CONFIG_CLK_DCM -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_LIB18T -#define CFG_CLK_TECH rhlib18t -#elif defined CONFIG_CLK_RHUMC -#define CFG_CLK_TECH rhumc -#else -#define CFG_CLK_TECH inferred -#endif - -#ifndef CONFIG_CLK_MUL -#define CONFIG_CLK_MUL 2 -#endif - -#ifndef CONFIG_CLK_DIV -#define CONFIG_CLK_DIV 2 -#endif - -#ifndef CONFIG_OCLK_DIV -#define CONFIG_OCLK_DIV 2 -#endif - -#ifndef CONFIG_PCI_CLKDLL -#define CONFIG_PCI_CLKDLL 0 -#endif - -#ifndef CONFIG_PCI_SYSCLK -#define CONFIG_PCI_SYSCLK 0 -#endif - -#ifndef CONFIG_CLK_NOFB -#define CONFIG_CLK_NOFB 0 -#endif -#ifndef CONFIG_LEON3 -#define CONFIG_LEON3 0 -#endif - -#ifndef CONFIG_PROC_NUM -#define CONFIG_PROC_NUM 1 -#endif - -#ifndef CONFIG_IU_NWINDOWS -#define CONFIG_IU_NWINDOWS 8 -#endif - -#ifndef CONFIG_IU_RSTADDR -#define CONFIG_IU_RSTADDR 8 -#endif - -#ifndef CONFIG_IU_LDELAY -#define CONFIG_IU_LDELAY 1 -#endif - -#ifndef CONFIG_IU_WATCHPOINTS -#define CONFIG_IU_WATCHPOINTS 0 -#endif - -#ifdef CONFIG_IU_V8MULDIV -#ifdef CONFIG_IU_MUL_LATENCY_4 -#define CFG_IU_V8 1 -#elif defined CONFIG_IU_MUL_LATENCY_5 -#define CFG_IU_V8 2 -#elif defined CONFIG_IU_MUL_LATENCY_2 -#define CFG_IU_V8 16#32# -#endif -#else -#define CFG_IU_V8 0 -#endif - -#ifndef CONFIG_PWD -#define CONFIG_PWD 0 -#endif - -#ifndef CONFIG_IU_MUL_MAC -#define CONFIG_IU_MUL_MAC 0 -#endif - -#ifndef CONFIG_IU_SVT -#define CONFIG_IU_SVT 0 -#endif - -#if defined CONFIG_FPU_GRFPC1 -#define CONFIG_FPU_GRFPC 1 -#elif defined CONFIG_FPU_GRFPC2 -#define CONFIG_FPU_GRFPC 2 -#else -#define CONFIG_FPU_GRFPC 0 -#endif - -#if defined CONFIG_FPU_GRFPU_INFMUL -#define CONFIG_FPU_GRFPU_MUL 0 -#elif defined CONFIG_FPU_GRFPU_DWMUL -#define CONFIG_FPU_GRFPU_MUL 1 -#elif defined CONFIG_FPU_GRFPU_MODGEN -#define CONFIG_FPU_GRFPU_MUL 2 -#else -#define CONFIG_FPU_GRFPU_MUL 0 -#endif - -#if defined CONFIG_FPU_GRFPU_SH -#define CONFIG_FPU_GRFPU_SHARED 1 -#else -#define CONFIG_FPU_GRFPU_SHARED 0 -#endif - -#if defined CONFIG_FPU_GRFPU -#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) -#elif defined CONFIG_FPU_MEIKO -#define CONFIG_FPU 15 -#elif defined CONFIG_FPU_GRFPULITE -#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) -#else -#define CONFIG_FPU 0 -#endif - -#ifndef CONFIG_FPU_NETLIST -#define CONFIG_FPU_NETLIST 0 -#endif - -#ifndef CONFIG_ICACHE_ENABLE -#define CONFIG_ICACHE_ENABLE 0 -#endif - -#if defined CONFIG_ICACHE_ASSO1 -#define CFG_IU_ISETS 1 -#elif defined CONFIG_ICACHE_ASSO2 -#define CFG_IU_ISETS 2 -#elif defined CONFIG_ICACHE_ASSO3 -#define CFG_IU_ISETS 3 -#elif defined CONFIG_ICACHE_ASSO4 -#define CFG_IU_ISETS 4 -#else -#define CFG_IU_ISETS 1 -#endif - -#if defined CONFIG_ICACHE_SZ1 -#define CFG_ICACHE_SZ 1 -#elif defined CONFIG_ICACHE_SZ2 -#define CFG_ICACHE_SZ 2 -#elif defined CONFIG_ICACHE_SZ4 -#define CFG_ICACHE_SZ 4 -#elif defined CONFIG_ICACHE_SZ8 -#define CFG_ICACHE_SZ 8 -#elif defined CONFIG_ICACHE_SZ16 -#define CFG_ICACHE_SZ 16 -#elif defined CONFIG_ICACHE_SZ32 -#define CFG_ICACHE_SZ 32 -#elif defined CONFIG_ICACHE_SZ64 -#define CFG_ICACHE_SZ 64 -#elif defined CONFIG_ICACHE_SZ128 -#define CFG_ICACHE_SZ 128 -#elif defined CONFIG_ICACHE_SZ256 -#define CFG_ICACHE_SZ 256 -#else -#define CFG_ICACHE_SZ 1 -#endif - -#ifdef CONFIG_ICACHE_LZ16 -#define CFG_ILINE_SZ 4 -#else -#define CFG_ILINE_SZ 8 -#endif - -#if defined CONFIG_ICACHE_ALGORND -#define CFG_ICACHE_ALGORND 2 -#elif defined CONFIG_ICACHE_ALGOLRR -#define CFG_ICACHE_ALGORND 1 -#else -#define CFG_ICACHE_ALGORND 0 -#endif - -#ifndef CONFIG_ICACHE_LOCK -#define CONFIG_ICACHE_LOCK 0 -#endif - -#ifndef CONFIG_ICACHE_LRAM -#define CONFIG_ICACHE_LRAM 0 -#endif - -#ifndef CONFIG_ICACHE_LRSTART -#define CONFIG_ICACHE_LRSTART 8E -#endif - -#if defined CONFIG_ICACHE_LRAM_SZ2 -#define CFG_ILRAM_SIZE 2 -#elif defined CONFIG_ICACHE_LRAM_SZ4 -#define CFG_ILRAM_SIZE 4 -#elif defined CONFIG_ICACHE_LRAM_SZ8 -#define CFG_ILRAM_SIZE 8 -#elif defined CONFIG_ICACHE_LRAM_SZ16 -#define CFG_ILRAM_SIZE 16 -#elif defined CONFIG_ICACHE_LRAM_SZ32 -#define CFG_ILRAM_SIZE 32 -#elif defined CONFIG_ICACHE_LRAM_SZ64 -#define CFG_ILRAM_SIZE 64 -#elif defined CONFIG_ICACHE_LRAM_SZ128 -#define CFG_ILRAM_SIZE 128 -#elif defined CONFIG_ICACHE_LRAM_SZ256 -#define CFG_ILRAM_SIZE 256 -#else -#define CFG_ILRAM_SIZE 1 -#endif - - -#ifndef CONFIG_DCACHE_ENABLE -#define CONFIG_DCACHE_ENABLE 0 -#endif - -#if defined CONFIG_DCACHE_ASSO1 -#define CFG_IU_DSETS 1 -#elif defined CONFIG_DCACHE_ASSO2 -#define CFG_IU_DSETS 2 -#elif defined CONFIG_DCACHE_ASSO3 -#define CFG_IU_DSETS 3 -#elif defined CONFIG_DCACHE_ASSO4 -#define CFG_IU_DSETS 4 -#else -#define CFG_IU_DSETS 1 -#endif - -#if defined CONFIG_DCACHE_SZ1 -#define CFG_DCACHE_SZ 1 -#elif defined CONFIG_DCACHE_SZ2 -#define CFG_DCACHE_SZ 2 -#elif defined CONFIG_DCACHE_SZ4 -#define CFG_DCACHE_SZ 4 -#elif defined CONFIG_DCACHE_SZ8 -#define CFG_DCACHE_SZ 8 -#elif defined CONFIG_DCACHE_SZ16 -#define CFG_DCACHE_SZ 16 -#elif defined CONFIG_DCACHE_SZ32 -#define CFG_DCACHE_SZ 32 -#elif defined CONFIG_DCACHE_SZ64 -#define CFG_DCACHE_SZ 64 -#elif defined CONFIG_DCACHE_SZ128 -#define CFG_DCACHE_SZ 128 -#elif defined CONFIG_DCACHE_SZ256 -#define CFG_DCACHE_SZ 256 -#else -#define CFG_DCACHE_SZ 1 -#endif - -#ifdef CONFIG_DCACHE_LZ16 -#define CFG_DLINE_SZ 4 -#else -#define CFG_DLINE_SZ 8 -#endif - -#if defined CONFIG_DCACHE_ALGORND -#define CFG_DCACHE_ALGORND 2 -#elif defined CONFIG_DCACHE_ALGOLRR -#define CFG_DCACHE_ALGORND 1 -#else -#define CFG_DCACHE_ALGORND 0 -#endif - -#ifndef CONFIG_DCACHE_LOCK -#define CONFIG_DCACHE_LOCK 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP -#define CONFIG_DCACHE_SNOOP 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_SEPTAG -#define CONFIG_DCACHE_SNOOP_SEPTAG 0 -#endif - -#ifndef CONFIG_CACHE_FIXED -#define CONFIG_CACHE_FIXED 0 -#endif - -#ifndef CONFIG_DCACHE_LRAM -#define CONFIG_DCACHE_LRAM 0 -#endif - -#ifndef CONFIG_DCACHE_LRSTART -#define CONFIG_DCACHE_LRSTART 8F -#endif - -#if defined CONFIG_DCACHE_LRAM_SZ2 -#define CFG_DLRAM_SIZE 2 -#elif defined CONFIG_DCACHE_LRAM_SZ4 -#define CFG_DLRAM_SIZE 4 -#elif defined CONFIG_DCACHE_LRAM_SZ8 -#define CFG_DLRAM_SIZE 8 -#elif defined CONFIG_DCACHE_LRAM_SZ16 -#define CFG_DLRAM_SIZE 16 -#elif defined CONFIG_DCACHE_LRAM_SZ32 -#define CFG_DLRAM_SIZE 32 -#elif defined CONFIG_DCACHE_LRAM_SZ64 -#define CFG_DLRAM_SIZE 64 -#elif defined CONFIG_DCACHE_LRAM_SZ128 -#define CFG_DLRAM_SIZE 128 -#elif defined CONFIG_DCACHE_LRAM_SZ256 -#define CFG_DLRAM_SIZE 256 -#else -#define CFG_DLRAM_SIZE 1 -#endif - -#if defined CONFIG_MMU_PAGE_4K -#define CONFIG_MMU_PAGE 0 -#elif defined CONFIG_MMU_PAGE_8K -#define CONFIG_MMU_PAGE 1 -#elif defined CONFIG_MMU_PAGE_16K -#define CONFIG_MMU_PAGE 2 -#elif defined CONFIG_MMU_PAGE_32K -#define CONFIG_MMU_PAGE 3 -#elif defined CONFIG_MMU_PAGE_PROG -#define CONFIG_MMU_PAGE 4 -#else -#define CONFIG_MMU_PAGE 0 -#endif - -#ifdef CONFIG_MMU_ENABLE -#define CONFIG_MMUEN 1 - -#ifdef CONFIG_MMU_SPLIT -#define CONFIG_TLB_TYPE 0 -#endif -#ifdef CONFIG_MMU_COMBINED -#define CONFIG_TLB_TYPE 1 -#endif - -#ifdef CONFIG_MMU_REPARRAY -#define CONFIG_TLB_REP 0 -#endif -#ifdef CONFIG_MMU_REPINCREMENT -#define CONFIG_TLB_REP 1 -#endif - -#ifdef CONFIG_MMU_I2 -#define CONFIG_ITLBNUM 2 -#endif -#ifdef CONFIG_MMU_I4 -#define CONFIG_ITLBNUM 4 -#endif -#ifdef CONFIG_MMU_I8 -#define CONFIG_ITLBNUM 8 -#endif -#ifdef CONFIG_MMU_I16 -#define CONFIG_ITLBNUM 16 -#endif -#ifdef CONFIG_MMU_I32 -#define CONFIG_ITLBNUM 32 -#endif - -#define CONFIG_DTLBNUM 2 -#ifdef CONFIG_MMU_D2 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 2 -#endif -#ifdef CONFIG_MMU_D4 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 4 -#endif -#ifdef CONFIG_MMU_D8 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 8 -#endif -#ifdef CONFIG_MMU_D16 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 16 -#endif -#ifdef CONFIG_MMU_D32 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 32 -#endif -#ifdef CONFIG_MMU_FASTWB -#define CFG_MMU_FASTWB 1 -#else -#define CFG_MMU_FASTWB 0 -#endif - -#else -#define CONFIG_MMUEN 0 -#define CONFIG_ITLBNUM 2 -#define CONFIG_DTLBNUM 2 -#define CONFIG_TLB_TYPE 1 -#define CONFIG_TLB_REP 1 -#define CFG_MMU_FASTWB 0 -#endif - -#ifndef CONFIG_DSU_ENABLE -#define CONFIG_DSU_ENABLE 0 -#endif - -#if defined CONFIG_DSU_ITRACESZ1 -#define CFG_DSU_ITB 1 -#elif CONFIG_DSU_ITRACESZ2 -#define CFG_DSU_ITB 2 -#elif CONFIG_DSU_ITRACESZ4 -#define CFG_DSU_ITB 4 -#elif CONFIG_DSU_ITRACESZ8 -#define CFG_DSU_ITB 8 -#elif CONFIG_DSU_ITRACESZ16 -#define CFG_DSU_ITB 16 -#else -#define CFG_DSU_ITB 0 -#endif - -#if defined CONFIG_DSU_ATRACESZ1 -#define CFG_DSU_ATB 1 -#elif CONFIG_DSU_ATRACESZ2 -#define CFG_DSU_ATB 2 -#elif CONFIG_DSU_ATRACESZ4 -#define CFG_DSU_ATB 4 -#elif CONFIG_DSU_ATRACESZ8 -#define CFG_DSU_ATB 8 -#elif CONFIG_DSU_ATRACESZ16 -#define CFG_DSU_ATB 16 -#else -#define CFG_DSU_ATB 0 -#endif - -#ifndef CONFIG_LEON3FT_EN -#define CONFIG_LEON3FT_EN 0 -#endif - -#if defined CONFIG_IUFT_PAR -#define CONFIG_IUFT_EN 1 -#elif defined CONFIG_IUFT_DMR -#define CONFIG_IUFT_EN 2 -#elif defined CONFIG_IUFT_BCH -#define CONFIG_IUFT_EN 3 -#elif defined CONFIG_IUFT_TMR -#define CONFIG_IUFT_EN 4 -#else -#define CONFIG_IUFT_EN 0 -#endif -#ifndef CONFIG_RF_ERRINJ -#define CONFIG_RF_ERRINJ 0 -#endif - -#ifndef CONFIG_FPUFT_EN -#define CONFIG_FPUFT 0 -#else -#ifdef CONFIG_FPU_GRFPU -#define CONFIG_FPUFT 2 -#else -#define CONFIG_FPUFT 1 -#endif -#endif - -#ifndef CONFIG_CACHE_FT_EN -#define CONFIG_CACHE_FT_EN 0 -#endif -#ifndef CONFIG_CACHE_ERRINJ -#define CONFIG_CACHE_ERRINJ 0 -#endif - -#ifndef CONFIG_LEON3_NETLIST -#define CONFIG_LEON3_NETLIST 0 -#endif - -#ifdef CONFIG_DEBUG_PC32 -#define CFG_DEBUG_PC32 0 -#else -#define CFG_DEBUG_PC32 2 -#endif -#ifndef CONFIG_IU_DISAS -#define CONFIG_IU_DISAS 0 -#endif -#ifndef CONFIG_IU_DISAS_NET -#define CONFIG_IU_DISAS_NET 0 -#endif - - -#ifndef CONFIG_AHB_SPLIT -#define CONFIG_AHB_SPLIT 0 -#endif - -#ifndef CONFIG_AHB_RROBIN -#define CONFIG_AHB_RROBIN 0 -#endif - -#ifndef CONFIG_AHB_IOADDR -#define CONFIG_AHB_IOADDR FFF -#endif - -#ifndef CONFIG_APB_HADDR -#define CONFIG_APB_HADDR 800 -#endif - -#ifndef CONFIG_AHB_MON -#define CONFIG_AHB_MON 0 -#endif - -#ifndef CONFIG_AHB_MONERR -#define CONFIG_AHB_MONERR 0 -#endif - -#ifndef CONFIG_AHB_MONWAR -#define CONFIG_AHB_MONWAR 0 -#endif - -#ifndef CONFIG_DSU_UART -#define CONFIG_DSU_UART 0 -#endif - - -#ifndef CONFIG_DSU_JTAG -#define CONFIG_DSU_JTAG 0 -#endif - -#ifndef CONFIG_DSU_ETH -#define CONFIG_DSU_ETH 0 -#endif - -#ifndef CONFIG_DSU_IPMSB -#define CONFIG_DSU_IPMSB C0A8 -#endif - -#ifndef CONFIG_DSU_IPLSB -#define CONFIG_DSU_IPLSB 0033 -#endif - -#ifndef CONFIG_DSU_ETHMSB -#define CONFIG_DSU_ETHMSB 020000 -#endif - -#ifndef CONFIG_DSU_ETHLSB -#define CONFIG_DSU_ETHLSB 000009 -#endif - -#if defined CONFIG_DSU_ETHSZ1 -#define CFG_DSU_ETHB 1 -#elif CONFIG_DSU_ETHSZ2 -#define CFG_DSU_ETHB 2 -#elif CONFIG_DSU_ETHSZ4 -#define CFG_DSU_ETHB 4 -#elif CONFIG_DSU_ETHSZ8 -#define CFG_DSU_ETHB 8 -#elif CONFIG_DSU_ETHSZ16 -#define CFG_DSU_ETHB 16 -#elif CONFIG_DSU_ETHSZ32 -#define CFG_DSU_ETHB 32 -#else -#define CFG_DSU_ETHB 1 -#endif - -#ifndef CONFIG_DSU_ETH_PROG -#define CONFIG_DSU_ETH_PROG 0 -#endif - - -#ifndef CONFIG_SRCTRL -#define CONFIG_SRCTRL 0 -#endif - -#ifndef CONFIG_SRCTRL_PROMWS -#define CONFIG_SRCTRL_PROMWS 0 -#endif - -#ifndef CONFIG_SRCTRL_RAMWS -#define CONFIG_SRCTRL_RAMWS 0 -#endif - -#ifndef CONFIG_SRCTRL_IOWS -#define CONFIG_SRCTRL_IOWS 0 -#endif - -#ifndef CONFIG_SRCTRL_RMW -#define CONFIG_SRCTRL_RMW 0 -#endif - -#ifndef CONFIG_SRCTRL_8BIT -#define CONFIG_SRCTRL_8BIT 0 -#endif - - -#ifndef CONFIG_SRCTRL_ROMASEL -#define CONFIG_SRCTRL_ROMASEL 0 -#endif - -#if defined CONFIG_SRCTRL_SRBANKS1 -#define CFG_SR_CTRL_SRBANKS 1 -#elif defined CONFIG_SRCTRL_SRBANKS2 -#define CFG_SR_CTRL_SRBANKS 2 -#elif defined CONFIG_SRCTRL_SRBANKS3 -#define CFG_SR_CTRL_SRBANKS 3 -#elif defined CONFIG_SRCTRL_SRBANKS4 -#define CFG_SR_CTRL_SRBANKS 4 -#elif defined CONFIG_SRCTRL_SRBANKS5 -#define CFG_SR_CTRL_SRBANKS 5 -#else -#define CFG_SR_CTRL_SRBANKS 1 -#endif - -#if defined CONFIG_SRCTRL_BANKSZ0 -#define CFG_SR_CTRL_BANKSZ 0 -#elif defined CONFIG_SRCTRL_BANKSZ1 -#define CFG_SR_CTRL_BANKSZ 1 -#elif defined CONFIG_SRCTRL_BANKSZ2 -#define CFG_SR_CTRL_BANKSZ 2 -#elif defined CONFIG_SRCTRL_BANKSZ3 -#define CFG_SR_CTRL_BANKSZ 3 -#elif defined CONFIG_SRCTRL_BANKSZ4 -#define CFG_SR_CTRL_BANKSZ 4 -#elif defined CONFIG_SRCTRL_BANKSZ5 -#define CFG_SR_CTRL_BANKSZ 5 -#elif defined CONFIG_SRCTRL_BANKSZ6 -#define CFG_SR_CTRL_BANKSZ 6 -#elif defined CONFIG_SRCTRL_BANKSZ7 -#define CFG_SR_CTRL_BANKSZ 7 -#elif defined CONFIG_SRCTRL_BANKSZ8 -#define CFG_SR_CTRL_BANKSZ 8 -#elif defined CONFIG_SRCTRL_BANKSZ9 -#define CFG_SR_CTRL_BANKSZ 9 -#elif defined CONFIG_SRCTRL_BANKSZ10 -#define CFG_SR_CTRL_BANKSZ 10 -#elif defined CONFIG_SRCTRL_BANKSZ11 -#define CFG_SR_CTRL_BANKSZ 11 -#elif defined CONFIG_SRCTRL_BANKSZ12 -#define CFG_SR_CTRL_BANKSZ 12 -#elif defined CONFIG_SRCTRL_BANKSZ13 -#define CFG_SR_CTRL_BANKSZ 13 -#else -#define CFG_SR_CTRL_BANKSZ 0 -#endif -#ifndef CONFIG_MCTRL_LEON2 -#define CONFIG_MCTRL_LEON2 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM -#define CONFIG_MCTRL_SDRAM 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_SEPBUS -#define CONFIG_MCTRL_SDRAM_SEPBUS 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_INVCLK -#define CONFIG_MCTRL_SDRAM_INVCLK 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_BUS64 -#define CONFIG_MCTRL_SDRAM_BUS64 0 -#endif - -#ifndef CONFIG_MCTRL_8BIT -#define CONFIG_MCTRL_8BIT 0 -#endif - -#ifndef CONFIG_MCTRL_16BIT -#define CONFIG_MCTRL_16BIT 0 -#endif - -#ifndef CONFIG_MCTRL_5CS -#define CONFIG_MCTRL_5CS 0 -#endif - -#ifndef CONFIG_MCTRL_EDAC -#define CONFIG_MCTRL_EDAC 0 -#endif - -#ifndef CONFIG_MCTRL_PAGE -#define CONFIG_MCTRL_PAGE 0 -#endif - -#ifndef CONFIG_MCTRL_PROGPAGE -#define CONFIG_MCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_SDCTRL -#define CONFIG_SDCTRL 0 -#endif - -#ifndef CONFIG_SDCTRL_SEPBUS -#define CONFIG_SDCTRL_SEPBUS 0 -#endif - -#ifndef CONFIG_SDCTRL_INVCLK -#define CONFIG_SDCTRL_INVCLK 0 -#endif - -#ifndef CONFIG_SDCTRL_BUS64 -#define CONFIG_SDCTRL_BUS64 0 -#endif - -#ifndef CONFIG_SDCTRL_PAGE -#define CONFIG_SDCTRL_PAGE 0 -#endif - -#ifndef CONFIG_SDCTRL_PROGPAGE -#define CONFIG_SDCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBROM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBROM_START -#define CONFIG_AHBROM_START 000 -#endif - -#ifndef CONFIG_AHBROM_PIPE -#define CONFIG_AHBROM_PIPE 0 -#endif - -#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) -#define CONFIG_ROM_START 100 -#else -#define CONFIG_ROM_START 000 -#endif - - -#ifndef CONFIG_AHBRAM_ENABLE -#define CONFIG_AHBRAM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBRAM_START -#define CONFIG_AHBRAM_START A00 -#endif - -#if defined CONFIG_AHBRAM_SZ1 -#define CFG_AHBRAMSZ 1 -#elif CONFIG_AHBRAM_SZ2 -#define CFG_AHBRAMSZ 2 -#elif CONFIG_AHBRAM_SZ4 -#define CFG_AHBRAMSZ 4 -#elif CONFIG_AHBRAM_SZ8 -#define CFG_AHBRAMSZ 8 -#elif CONFIG_AHBRAM_SZ16 -#define CFG_AHBRAMSZ 16 -#elif CONFIG_AHBRAM_SZ32 -#define CFG_AHBRAMSZ 32 -#elif CONFIG_AHBRAM_SZ64 -#define CFG_AHBRAMSZ 64 -#else -#define CFG_AHBRAMSZ 1 -#endif - -#ifndef CONFIG_GRETH_ENABLE -#define CONFIG_GRETH_ENABLE 0 -#endif - -#ifndef CONFIG_GRETH_GIGA -#define CONFIG_GRETH_GIGA 0 -#endif - -#if defined CONFIG_GRETH_FIFO4 -#define CFG_GRETH_FIFO 4 -#elif defined CONFIG_GRETH_FIFO8 -#define CFG_GRETH_FIFO 8 -#elif defined CONFIG_GRETH_FIFO16 -#define CFG_GRETH_FIFO 16 -#elif defined CONFIG_GRETH_FIFO32 -#define CFG_GRETH_FIFO 32 -#elif defined CONFIG_GRETH_FIFO64 -#define CFG_GRETH_FIFO 64 -#else -#define CFG_GRETH_FIFO 8 -#endif - -#ifndef CONFIG_CAN_ENABLE -#define CONFIG_CAN_ENABLE 0 -#endif - -#ifndef CONFIG_CANIO -#define CONFIG_CANIO 0 -#endif - -#ifndef CONFIG_CANIRQ -#define CONFIG_CANIRQ 0 -#endif - -#ifndef CONFIG_CANLOOP -#define CONFIG_CANLOOP 0 -#endif - -#ifndef CONFIG_CAN_SYNCRST -#define CONFIG_CAN_SYNCRST 0 -#endif - - -#ifndef CONFIG_CAN_FT -#define CONFIG_CAN_FT 0 -#endif -#if defined CONFIG_PCI_SIMPLE_TARGET -#define CFG_PCITYPE 1 -#elif defined CONFIG_PCI_MASTER_TARGET_DMA -#define CFG_PCITYPE 3 -#elif defined CONFIG_PCI_MASTER_TARGET -#define CFG_PCITYPE 2 -#else -#define CFG_PCITYPE 0 -#endif - -#ifndef CONFIG_PCI_VENDORID -#define CONFIG_PCI_VENDORID 0 -#endif - -#ifndef CONFIG_PCI_DEVICEID -#define CONFIG_PCI_DEVICEID 0 -#endif - -#ifndef CONFIG_PCI_REVID -#define CONFIG_PCI_REVID 0 -#endif - -#if defined CONFIG_PCI_FIFO0 -#define CFG_PCIFIFO 8 -#define CFG_PCI_ENFIFO 0 -#elif defined CONFIG_PCI_FIFO16 -#define CFG_PCIFIFO 16 -#elif defined CONFIG_PCI_FIFO32 -#define CFG_PCIFIFO 32 -#elif defined CONFIG_PCI_FIFO64 -#define CFG_PCIFIFO 64 -#elif defined CONFIG_PCI_FIFO128 -#define CFG_PCIFIFO 128 -#elif defined CONFIG_PCI_FIFO256 -#define CFG_PCIFIFO 256 -#else -#define CFG_PCIFIFO 8 -#endif - -#ifndef CFG_PCI_ENFIFO -#define CFG_PCI_ENFIFO 1 -#endif - - -#ifndef CONFIG_PCI_ARBITER_APB -#define CONFIG_PCI_ARBITER_APB 0 -#endif - -#ifndef CONFIG_PCI_ARBITER -#define CONFIG_PCI_ARBITER 0 -#endif - -#ifndef CONFIG_PCI_ARBITER_NREQ -#define CONFIG_PCI_ARBITER_NREQ 4 -#endif - -#ifndef CONFIG_PCI_TRACE -#define CONFIG_PCI_TRACE 0 -#endif - -#if defined CONFIG_PCI_TRACE512 -#define CFG_PCI_TRACEBUF 512 -#elif defined CONFIG_PCI_TRACE1024 -#define CFG_PCI_TRACEBUF 1024 -#elif defined CONFIG_PCI_TRACE2048 -#define CFG_PCI_TRACEBUF 2048 -#elif defined CONFIG_PCI_TRACE4096 -#define CFG_PCI_TRACEBUF 4096 -#else -#define CFG_PCI_TRACEBUF 256 -#endif - - -#ifndef CONFIG_SPW_ENABLE -#define CONFIG_SPW_ENABLE 0 -#endif - -#ifndef CONFIG_SPW_NUM -#define CONFIG_SPW_NUM 1 -#endif - -#if defined CONFIG_SPW_AHBFIFO4 -#define CONFIG_SPW_AHBFIFO 4 -#elif defined CONFIG_SPW_AHBFIFO8 -#define CONFIG_SPW_AHBFIFO 8 -#elif defined CONFIG_SPW_AHBFIFO16 -#define CONFIG_SPW_AHBFIFO 16 -#elif defined CONFIG_SPW_AHBFIFO32 -#define CONFIG_SPW_AHBFIFO 32 -#elif defined CONFIG_SPW_AHBFIFO64 -#define CONFIG_SPW_AHBFIFO 64 -#else -#define CONFIG_SPW_AHBFIFO 4 -#endif - -#if defined CONFIG_SPW_RXFIFO16 -#define CONFIG_SPW_RXFIFO 16 -#elif defined CONFIG_SPW_RXFIFO32 -#define CONFIG_SPW_RXFIFO 32 -#elif defined CONFIG_SPW_RXFIFO64 -#define CONFIG_SPW_RXFIFO 64 -#else -#define CONFIG_SPW_RXFIFO 16 -#endif - -#ifndef CONFIG_SPW_RMAP -#define CONFIG_SPW_RMAP 0 -#endif - -#if defined CONFIG_SPW_RMAPBUF2 -#define CONFIG_SPW_RMAPBUF 2 -#elif defined CONFIG_SPW_RMAPBUF4 -#define CONFIG_SPW_RMAPBUF 4 -#elif defined CONFIG_SPW_RMAPBUF6 -#define CONFIG_SPW_RMAPBUF 6 -#elif defined CONFIG_SPW_RMAPBUF8 -#define CONFIG_SPW_RMAPBUF 8 -#else -#define CONFIG_SPW_RMAPBUF 4 -#endif - -#ifndef CONFIG_SPW_RMAPCRC -#define CONFIG_SPW_RMAPCRC 0 -#endif - -#ifndef CONFIG_SPW_RXUNAL -#define CONFIG_SPW_RXUNAL 0 -#endif - -#ifndef CONFIG_SPW_NETLIST -#define CONFIG_SPW_NETLIST 0 -#endif - -#ifndef CONFIG_SPW_FT -#define CONFIG_SPW_FT 0 -#endif - -#if defined CONFIG_SPW_GRSPW1 -#define CONFIG_SPW_GRSPW 1 -#else -#define CONFIG_SPW_GRSPW 2 -#endif - -#ifndef CONFIG_SPW_DMACHAN -#define CONFIG_SPW_DMACHAN 1 -#endif - -#ifndef CONFIG_SPW_PORTS -#define CONFIG_SPW_PORTS 1 -#endif - -#if defined CONFIG_SPW_RX_SDR -#define CONFIG_SPW_INPUT 2 -#elif defined CONFIG_SPW_RX_DDR -#define CONFIG_SPW_INPUT 3 -#elif defined CONFIG_SPW_RX_XOR -#define CONFIG_SPW_INPUT 0 -#elif defined CONFIG_SPW_RX_AFLEX -#define CONFIG_SPW_INPUT 1 -#else -#define CONFIG_SPW_INPUT 2 -#endif - -#if defined CONFIG_SPW_TX_SDR -#define CONFIG_SPW_OUTPUT 0 -#elif defined CONFIG_SPW_TX_DDR -#define CONFIG_SPW_OUTPUT 1 -#elif defined CONFIG_SPW_TX_AFLEX -#define CONFIG_SPW_OUTPUT 2 -#else -#define CONFIG_SPW_OUTPUT 0 -#endif - -#ifndef CONFIG_SPW_RTSAME -#define CONFIG_SPW_RTSAME 0 -#endif -#ifndef CONFIG_UART1_ENABLE -#define CONFIG_UART1_ENABLE 0 -#endif - -#if defined CONFIG_UA1_FIFO1 -#define CFG_UA1_FIFO 1 -#elif defined CONFIG_UA1_FIFO2 -#define CFG_UA1_FIFO 2 -#elif defined CONFIG_UA1_FIFO4 -#define CFG_UA1_FIFO 4 -#elif defined CONFIG_UA1_FIFO8 -#define CFG_UA1_FIFO 8 -#elif defined CONFIG_UA1_FIFO16 -#define CFG_UA1_FIFO 16 -#elif defined CONFIG_UA1_FIFO32 -#define CFG_UA1_FIFO 32 -#else -#define CFG_UA1_FIFO 1 -#endif - -#ifndef CONFIG_UART2_ENABLE -#define CONFIG_UART2_ENABLE 0 -#endif - -#if defined CONFIG_UA2_FIFO1 -#define CFG_UA2_FIFO 1 -#elif defined CONFIG_UA2_FIFO2 -#define CFG_UA2_FIFO 2 -#elif defined CONFIG_UA2_FIFO4 -#define CFG_UA2_FIFO 4 -#elif defined CONFIG_UA2_FIFO8 -#define CFG_UA2_FIFO 8 -#elif defined CONFIG_UA2_FIFO16 -#define CFG_UA2_FIFO 16 -#elif defined CONFIG_UA2_FIFO32 -#define CFG_UA2_FIFO 32 -#else -#define CFG_UA2_FIFO 1 -#endif - -#ifndef CONFIG_IRQ3_ENABLE -#define CONFIG_IRQ3_ENABLE 0 -#endif -#ifndef CONFIG_IRQ3_NSEC -#define CONFIG_IRQ3_NSEC 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif - -#ifndef CONFIG_GPT_WDOGEN -#define CONFIG_GPT_WDOGEN 0 -#endif - -#ifndef CONFIG_GPT_WDOG -#define CONFIG_GPT_WDOG 0 -#endif - -#ifndef CONFIG_GRGPIO_ENABLE -#define CONFIG_GRGPIO_ENABLE 0 -#endif -#ifndef CONFIG_GRGPIO_IMASK -#define CONFIG_GRGPIO_IMASK 0000 -#endif -#ifndef CONFIG_GRGPIO_WIDTH -#define CONFIG_GRGPIO_WIDTH 1 -#endif - - -#ifndef CONFIG_DEBUG_UART -#define CONFIG_DEBUG_UART 0 -#endif diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/top_libero.prj.convert.8.6.bak b/designs/ProjetBlanc-LeonLPP-A3PE3kL/top_libero.prj.convert.8.6.bak deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/top_libero.prj.convert.8.6.bak +++ /dev/null @@ -1,2766 +0,0 @@ -KEY LIBERO "8.6" -KEY CAPTURE "8.6.2.10" -KEY HDLTechnology "VHDL" -KEY VendorTechnology_Family "PROASIC3" -KEY VendorTechnology_Die "IT14X14M4LDP" -KEY VendorTechnology_Package "fg324" -KEY ProjectLocation "." -KEY SimulationType "VHDL" -KEY Vendor "Actel" -KEY ActiveRoot "top" -LIST REVISIONS -VALUE="Impl1",NUM=1 -CURREV=1 -ENDLIST -LIST LIBRARIES -grlib -synplify -techmap -spw -eth -opencores -gaisler -esa -fmf -spansion -gsi -lpp -lpp -cypress -work -ENDLIST -LIST LIBRARIES_grlib -ALIAS=grlib -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_synplify -ALIAS=synplify -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_techmap -ALIAS=techmap -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_spw -ALIAS=spw -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_eth -ALIAS=eth -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_opencores -ALIAS=opencores -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_gaisler -ALIAS=gaisler -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_esa -ALIAS=esa -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_fmf -ALIAS=fmf -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_spansion -ALIAS=spansion -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_gsi -ALIAS=gsi -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_lpp -ALIAS=lpp -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_lpp -ALIAS=lpp -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_cypress -ALIAS=cypress -COMPILE_OPTION=COMPILE -ENDLIST -LIST LIBRARIES_work -ALIAS=work -COMPILE_OPTION=COMPILE -ENDLIST -LIST FileManager -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/version.vhd,hdl" -STATE="utd" -LIBRARY="grlib" -ENDFILE -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/config.vhd,hdl" -STATE="utd" -LIBRARY="grlib" -ENDFILE -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/stdlib.vhd,hdl" -STATE="utd" -LIBRARY="grlib" -ENDFILE -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/stdio.vhd,hdl" -STATE="utd" -LIBRARY="grlib" -ENDFILE -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/stdlib/testlib.vhd,hdl" -STATE="utd" -LIBRARY="grlib" -ENDFILE -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/util/util.vhd,hdl" -STATE="utd" -LIBRARY="grlib" -ENDFILE -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/grlib/sparc/sparc.vhd,hdl" -STATE="utd" -LIBRARY="grlib" -ENDFILE -VALUE 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"/C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/syncram156bw.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/techmult.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/spictrl_net.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/techmap/maps/scanreg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/comp/spwcomp.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/wrapper/grspw_gen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/spw/wrapper/grspw2_gen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/comp/ethcomp.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_pkg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_rstgen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_edcl_ahb_mst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/eth_ahb_mst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_tx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/greth_rx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/core/grethc.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/wrapper/greth_gen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/eth/wrapper/greth_gbit_gen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/occomp/occomp.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/can/cancomp.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/opencores/can/can_top.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/arith.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/mul32.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/arith/div32.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/memctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdctrl64.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/sdmctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/srctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/memctrl/spimctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmuconfig.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmuiface.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libmmu.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libiu.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libcache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/libproc3.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/cachemem.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_icache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_dcache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_acache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutlbcam.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmulrue.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmulru.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutlb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutw.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_cache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/cpu_disasx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/iu3.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpwx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mfpwx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grlfpwx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/tbufmem.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/dsu3x.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/dsu3.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/proc3.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3s.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3cg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/irqmp.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpwxsh.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpushwx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3sh.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3ft/leon3ft.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_mod.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_oc.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_mc.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/canmux.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_rd.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/misc.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/rstgen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gptimer.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbram.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbdpram.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mmb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpio.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbstat.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/logan.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbps2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom_package.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbvga.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/svgactrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/i2cmst_gen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/spictrlx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/spictrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/i2cslv.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/wild.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/wild2ahb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grsysmon.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gracectrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpreg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahb_mst_iface.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/net/net.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/libdcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/apbuart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/dcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/dcom_uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/ahbuart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtag.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/libjtagcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtagcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregs.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregsbd.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/ethernet_mac.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/grethm.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/spacewire.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspwm.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/gr1553b/gr1553b_pkg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/memoryctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/mctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/RAM.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/ALU.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/Adder.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/Clk_divider.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC_MUX.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MUX2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/Multiplier.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/Shifter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/general_purpose.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_amba/lpp_amba.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/Serialize.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/lpp_cna.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/ApbDriver.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Link_Reg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/APB_UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/BaudGen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_Filter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_IIR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT_half.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTamont.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTaval.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/ALU.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Adder.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_Divider2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_divider.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MUX2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MUXN.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Multiplier.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/SYNC_FF.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Shifter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/general_purpose.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/APB_AMR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Clock_multi.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Dephaseur.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Gene_Rz.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/bclk_reg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/lpp_AMR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/APB_Balise.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/lpp_balise.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/APB_Delay.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/TimerDelay.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/lpp_delay.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1274_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1278_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/WriteGen_ADC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/dual_ADS1278_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl" -VALUE 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"/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/cachemem.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_icache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_dcache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_acache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutlbcam.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmulrue.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmulru.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutlb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmutw.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mmu_cache.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/cpu_disasx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/iu3.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpwx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/mfpwx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grlfpwx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/tbufmem.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/dsu3x.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/dsu3.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/proc3.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3s.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3cg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/irqmp.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpwxsh.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/grfpushwx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3/leon3sh.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/leon3ft/leon3ft.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_mod.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_oc.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_mc.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/canmux.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/can/can_rd.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/misc.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/rstgen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gptimer.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbram.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbdpram.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbtrace_mmb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpio.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbstat.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/logan.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbps2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom_package.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/charrom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/apbvga.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/svgactrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/i2cmst_gen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/spictrlx.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/spictrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/i2cslv.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/wild.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/wild2ahb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grsysmon.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/gracectrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/grgpreg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahbmst2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/misc/ahb_mst_iface.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/ambatest/ahbtbp.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/ambatest/ahbtbm.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/net/net.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/libdcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/apbuart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/dcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/dcom_uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/uart/ahbuart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/i2c_slave_model.v,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/sim.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/sram.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/ata_device.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/sram16.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/phy.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/ahbrep.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/delay_wire.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/spi_flash.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/pwm_check.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/usbsim.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/grusbdcsim.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/sim/grusb_dclsim.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtag.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/libjtagcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtagcom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregs.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/bscanregsbd.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/jtag/jtagtst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/ethernet_mac.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/greth_gbit_mb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/greth/grethm.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/spacewire.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspw2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/spacewire/grspwm.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gaisler/gr1553b/gr1553b_pkg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/memoryctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/esa/memoryctrl/mctrl.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/utilities/conversions.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/utilities/gen_utils.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/flash.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/s25fl064a.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/flash/m25p80.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/fmf/fifo/idt7202.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/functions.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/core_burst.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/gsi/ssram/g880e18bt.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/RAM.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/ALU.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/Adder.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/Clk_divider.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC_MUX.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MAC_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/MUX2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/Multiplier.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/Shifter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./general_purpose/general_purpose.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_amba/lpp_amba.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/Serialize.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_cna/lpp_cna.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/ApbDriver.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Link_Reg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/APB_UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/BaudGen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/APB_IIR_Filter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/Top_IIR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/APB_FFT_half.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTamont.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFTaval.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/ALU.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Adder.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_Divider2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Clk_divider.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MAC_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MUX2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/MUXN.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Multiplier.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/SYNC_FF.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/Shifter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/general_purpose.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/APB_AMR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Clock_multi.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Dephaseur.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/Gene_Rz.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/bclk_reg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_AMR/lpp_AMR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/APB_Balise.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_balise/lpp_balise.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/APB_Delay.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/TimerDelay.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./general_purpose/lpp_delay/lpp_delay.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1274_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS1278_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/WriteGen_ADC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/dual_ADS1278_drvr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_amba/lpp_amba.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/bootrom.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Serialize.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_cna/lpp_cna.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_demux/DEMUX.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_demux/WatchFlag.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_demux/lpp_demux.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_fsm.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopMatrix_PDR.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Top_MatrixSpec.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/Bridge.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOx5.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lppFIFOxN.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_FIFO.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/APB_UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/BaudGen.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/UART.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/APB_USB.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/RWbuf.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./lpp_usb/lpp_usb.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/MinF_Cntr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Rocket_PCM_Encoder.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Serial_Driver_Multiplexor.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/../../VHD_Lib/lib/lpp/./Rocket_PCM_Encoder/Word_Cntr.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/components.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/package_utility.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/cy7c1354b.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/cypress/ssram/cy7c1380d.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/debug.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/grtestmod.vhd,hdl" -VALUE "/C:/opt/grlib-gpl-1.1.0-b4108/lib/work/debug/cpu_disas.vhd,hdl" -VALUE "/config.vhd,hdl" -VALUE "/ahbrom.vhd,hdl" -VALUE "/leon3mp.vhd,hdl" -ENDFILELIST -ENDLIST -ENDLIST -ENDLIST diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/tsmc13.rc b/designs/ProjetBlanc-LeonLPP-A3PE3kL/tsmc13.rc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/tsmc13.rc +++ /dev/null @@ -1,8 +0,0 @@ -set_attribute lib_search_path {. /usr/local/synlibs/TSMG13F210D3_1.1/lib} -set_attribute library {"tsmg13f210t3_wc_108V_125C.lib" "/home/jiri/ibm/vhdl/temic/atc18/allmem.lib" } / -include leon3mp.rc -include atc18cond.rc -define_clock -period 5000 -name clock1 clk -synthesize -to_mapped -report_area -report_timing diff --git a/designs/ProjetBlanc-LeonLPP-A3PE3kL/wave.do b/designs/ProjetBlanc-LeonLPP-A3PE3kL/wave.do deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-A3PE3kL/wave.do +++ /dev/null @@ -1,66 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /testbench/clk -add wave -noupdate -format Logic /testbench/rst -add wave -noupdate -format Literal -radix hexadecimal /testbench/address -add wave -noupdate -format Literal -radix hexadecimal /testbench/data -add wave -noupdate -format Literal /testbench/ramsn -add wave -noupdate -format Literal /testbench/ramoen -add wave -noupdate -format Literal /testbench/rwen -add wave -noupdate -format Literal /testbench/rwenx -add wave -noupdate -format Literal /testbench/romsn -add wave -noupdate -format Logic /testbench/iosn -add wave -noupdate -format Logic /testbench/oen -add wave -noupdate -format Logic /testbench/read -add wave -noupdate -format Logic /testbench/writen -add wave -noupdate -format Literal -radix hexadecimal /testbench/sa -add wave -noupdate -format Literal -radix hexadecimal /testbench/sd -add wave -noupdate -format Literal /testbench/sdcke -add wave -noupdate -format Literal /testbench/sdcsn -add wave -noupdate -format Logic /testbench/sdwen -add wave -noupdate -format Logic /testbench/sdrasn -add wave -noupdate -format Logic /testbench/sdcasn -add wave -noupdate -format Literal /testbench/sddqm -add wave -noupdate -format Logic /testbench/sdclk -add wave -noupdate -divider {CPU 1} -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ici -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ico -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dci -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dco -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/rfi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/rfo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/irqi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/irqo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dbgi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dbgo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/wpr -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dsur -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ir -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/cmem0/crami -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/cmem0/cramo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/m0/c0/dcache0/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/mg2/sr1/sd0/sdctrl/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/apbi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/apbo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbsi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbso -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbmi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbmo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/mg2/sr1/r -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {35452000 ps} 0} -configure wave -namecolwidth 212 -configure wave -valuecolwidth 117 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {689872312 ps} {690294089 ps} diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/.config b/designs/ProjetBlanc-LeonLPP-M7A3P1k/.config deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/971A_lqfp.bsd b/designs/ProjetBlanc-LeonLPP-M7A3P1k/971A_lqfp.bsd deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/971A_lqfp.bsd +++ /dev/null @@ -1,262 +0,0 @@ --- --- Device: LXT971A --- Package: LQFP --- File Name: 971A_lqfp.bsdl --- --- Revision History --- 1.0 - Tim Jackson (4/29/2002) --- Legacy file 971Alqfp.txt renamed to 971A_lqfp.bsdl. --- Updated attribute IDCODE_REGISTER to handle revision ids 1 --- and 2 and their appropriate jedec continuation codes. --- Changed PWRDWN to a compliance enable and added a design --- warning to that effect. --- --- Notes --- This file has successfully compiled on the Agilent Technologies 3070 --- BSDL compiler. --- --- Disclaimer --- Intel Corporation ("Intel") hereby grants the user of this BSDL file --- ("User") a non-exclusive, nontransferable license to use the file --- under the following terms. User may only to use the BSDL file and --- is not granted rights to sell, copy (except as needed to run the BSDL --- file), rent, lease or sub-license the BSDL file in whole or in part, --- or in modified form to anyone. User may modify the BSDL file to suit --- its specific applications, but rights to derivative works and such --- modifications shall belong to Intel. This BSDL file is provided on an --- "AS IS" basis and Intel makes absolutely no warranty with respect to --- the information contained herein. INTEL DISCLAIMS AND USER WAIVES --- ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF --- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY --- OF NON-INFRINGEMENT OF THE INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD --- PARTY. THE ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH USER. --- ACCORDINGLY, IN NO EVENT SHALL INTEL BE LIABLE FOR ANY DIRECT OR --- INDIRECT DAMAGES, WHETHER IN CONTRACT OR TORT, INCLUDING, WITHOUT --- LIMITATION, LOST PROFITS, BUSINESS INTERRUPTION, OR LOST INFORMATION) --- ARISING OUT OF THE USE OF OR INABILITY TO USE THE FILE, EVEN IF INTEL --- HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. --- --- This file is the legal property of Copyright (c) 2002, Intel --- Corporation. --- - -entity shark is - generic (PHYSICAL_PIN_MAP : string := "LQFP64"); - - port ( - GND : linkage bit_vector (1 to 7); - VCCIO : linkage bit_vector (1 to 2); - VCCA : linkage bit_vector (1 to 2); - VCCD : linkage bit ; - NC : linkage bit_vector (1 to 3); - XI : linkage bit ; - XO : linkage bit ; - MDDIS : in bit ; - Reset : in bit ; - TXSLEW0: in bit ; - TXSLEW1: in bit ; - ADDR0 : in bit ; - ADDR1 : in bit ; - ADDR2 : in bit ; - ADDR3 : in bit ; - ADDR4 : in bit ; - RBIAS : linkage bit ; - TPFOP : linkage bit ; - TPFON : linkage bit ; - TPFIP : linkage bit ; - TPFIN : linkage bit ; - SD_TP : in bit ; - TDI : in bit ; - TDO : out bit ; - TMS : in bit ; - TCK : in bit ; - TRST : in bit ; - SLEEP : in bit ; - PAUSE : in bit ; - TEST0 : in bit ; - TEST1 : in bit ; - LEDCFG2: inout bit ; - LEDCFG1: inout bit ; - LEDCFG0: inout bit ; - PWRDWN : in bit ; - MDIO : inout bit ; - MDC : in bit ; - RXD3 : out bit ; - RXD2 : out bit ; - RXD1 : out bit ; - RXD0 : out bit ; - RX_DV : out bit ; - RX_CLK : out bit ; - RX_ER : out bit ; - TX_ER : in bit ; - TX_CLK : out bit ; - TX_EN : in bit ; - TXD0 : in bit ; - TXD1 : in bit ; - TXD2 : in bit ; - TXD3 : in bit ; - COL : out bit ; - CRS : out bit ; - MDINT : out bit - - ); - - use STD_1149_1_1994.all; - use LXT971A_BSCAN.all; - - attribute COMPONENT_CONFORMANCE of shark: entity is "STD_1149_1_1993"; - - -- Pin mappings - - attribute PIN_MAP of shark: entity is PHYSICAL_PIN_MAP; - - constant LQFP64: PIN_MAP_STRING:= - "GND : (7,11,18,25,41,50,61),"& - "VCCIO : (8,40) ,"& - "VCCA : (21,22) ,"& - "VCCD : 51 ,"& - "NC : (9,10,44) ,"& - "XI : 1 ,"& - "XO : 2 ,"& - "MDDIS : 3 ,"& - "Reset : 4 ,"& - "TXSLEW0: 5 ,"& - "TXSLEW1: 6 ,"& - "ADDR0 : 12 ,"& - "ADDR1 : 13 ,"& - "ADDR2 : 14 ,"& - "ADDR3 : 15 ,"& - "ADDR4 : 16 ,"& - "RBIAS : 17 ,"& - "TPFOP : 19 ,"& - "TPFON : 20 ,"& - "TPFIP : 23 ,"& - "TPFIN : 24 ,"& - "SD_TP : 26 ,"& - "TDI : 27 ,"& - "TDO : 28 ,"& - "TMS : 29 ,"& - "TCK : 30 ,"& - "TRST : 31 ,"& - "SLEEP : 32 ,"& - "PAUSE : 33 ,"& - "TEST0 : 34 ,"& - "TEST1 : 35 ,"& - "LEDCFG2: 36 ,"& - "LEDCFG1: 37 ,"& - "LEDCFG0: 38 ,"& - "PWRDWN : 39 ,"& - "MDIO : 42 ,"& - "MDC : 43 ,"& - "RXD3 : 45 ,"& - "RXD2 : 46 ,"& - "RXD1 : 47 ,"& - "RXD0 : 48 ,"& - "RX_DV : 49 ,"& - "RX_CLK : 52 ,"& - "RX_ER : 53 ,"& - "TX_ER : 54 ,"& - "TX_CLK : 55 ,"& - "TX_EN : 56 ,"& - "TXD0 : 57 ,"& - "TXD1 : 58 ,"& - "TXD2 : 59 ,"& - "TXD3 : 60 ,"& - "COL : 62 ,"& - "CRS : 63 ,"& - "MDINT : 64 "; - - - - -- IEEE 1149.1 pin definition - attribute TAP_SCAN_RESET of TRST : signal is true; - attribute TAP_SCAN_IN of TDI : signal is true; - attribute TAP_SCAN_MODE of TMS : signal is true; - attribute TAP_SCAN_OUT of TDO : signal is true; - attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); - - -- IEEE 1149.1 compliance enable - attribute COMPLIANCE_PATTERNS of shark: entity is - "(PWRDWN) (0)"; - - -- IEEE 1149.1 definition for LV Software TAP - attribute INSTRUCTION_LENGTH of shark: entity is 16; - - attribute INSTRUCTION_OPCODE of shark: entity is - "IDCODE (1111111111111110)," & - "BYPASS (1111111111111111)," & - "EXTEST (0000000000000000,1111111111101000)," & - "SAMPLE (1111111111111000)," & - "HIGHZ (1111111111001111)," & - "CLAMP (1111111111101111)" ; - attribute INSTRUCTION_CAPTURE of shark: entity is "xxxxxxxxxxxxxx01"; - - attribute IDCODE_REGISTER of shark: entity is - "0001" & -- revision id 1 - "0000001111001011" & -- part number - "11101111110" & -- manufacturer's ID - "1," & -- required by 1149.1 - "0010" & -- revision id 2 - "0000001111001011" & -- part number - "00001111110" & -- manufacturer's ID - "1"; -- required by 1149.1 - - attribute REGISTER_ACCESS of shark: entity is - "BYPASS (HIGHZ, CLAMP) " ; - - --Boundary scan definition - attribute BOUNDARY_LENGTH of shark: entity is 40; - - attribute BOUNDARY_REGISTER of shark: entity is - -- num cell port function safe [ccell disval rslt] - " 0 (BC_2 , MDDIS , input , X ) ,"& - " 1 (BC_2 , Reset , input , X ) ,"& - " 2 (BC_2 , TXSLEW0 , input , X ) ,"& - " 3 (BC_2 , TXSLEW1 , input , X ) ,"& - " 4 (BC_2 , ADDR0 , input , X ) ,"& - " 5 (BC_2 , ADDR1 , input , X ) ,"& - " 6 (BC_2 , ADDR2 , input , X ) ,"& - " 7 (BC_2 , ADDR3 , input , X ) ,"& - " 8 (BC_2 , ADDR4 , input , X ) ,"& - " 9 (BC_2 , SD_TP , input , X ) ,"& - " 10 (BC_2 , SLEEP , input , X ) ,"& - " 11 (BC_2 , PAUSE , input , X ) ,"& - " 12 (BC_2 , TEST0 , input , X ) ,"& - " 13 (BC_2 , TEST1 , input , X ) ,"& - " 14 (BC_2 , * , control , 1 ) ,"& - " 15 (LV_BC_7 , LEDCFG2 , bidir , X , 14 , 1 , Z ),"& - " 16 (LV_BC_7 , LEDCFG1 , bidir , X , 14 , 1 , Z ),"& - " 17 (LV_BC_7 , LEDCFG0 , bidir , X , 14 , 1 , Z ),"& - " 18 (BC_2 , * , internal , 0 ) ,"& - " 19 (LV_BC_7 , MDIO , bidir , X , 14 , 1 , Z ),"& - " 20 (BC_2 , MDC , input , X ) ,"& - " 21 (BC_2 , * , internal , X ) ,"& - " 22 (BC_2 , RXD3 , output3 , X , 14 , 1 , Z ),"& - " 23 (BC_2 , RXD2 , output3 , X , 14 , 1 , Z ),"& - " 24 (BC_2 , RXD1 , output3 , X , 14 , 1 , Z ),"& - " 25 (BC_2 , RXD0 , output3 , X , 14 , 1 , Z ),"& - " 26 (BC_2 , RX_DV , output3 , X , 14 , 1 , Z ),"& - " 27 (BC_2 , RX_CLK , output3 , X , 14 , 1 , Z ),"& - " 28 (BC_2 , RX_ER , output3 , X , 14 , 1 , Z ),"& - " 29 (BC_2 , TX_ER , input , X ) ,"& - " 30 (BC_2 , TX_CLK , output3 , X , 14 , 1 , Z ),"& - " 31 (BC_2 , TX_EN , input , X ) ,"& - " 32 (BC_2 , TXD0 , input , X ) ,"& - " 33 (BC_2 , TXD1 , input , X ) ,"& - " 34 (BC_2 , TXD2 , input , X ) ,"& - " 35 (BC_2 , TXD3 , input , X ) ,"& - " 36 (BC_2 , * , internal , 0 ) ,"& - " 37 (BC_2 , COL , output3 , X , 14 , 1 , Z ),"& - " 38 (BC_2 , CRS , output3 , X , 14 , 1 , Z ),"& - " 39 (BC_2 , MDINT , output3 , X , 14 , 1 , Z ) "; - --- 1149.1 Design Warnings - attribute DESIGN_WARNING of shark: entity is - "PWRDWN pin should be kept low to allow proper operation" & - "of TAP circuitry. There is a compliance enable on this" & - "pin to force the safe value. The boundary scan cell" & - "associated with the PWRDWN pin has been changed to an" & - "internal pin. It is cell number 18 in the boundary scan" & - "register description and has a safe value of 0 specified"; - -end shark; diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/Makefile b/designs/ProjetBlanc-LeonLPP-M7A3P1k/Makefile deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -#GRLIB=../.. -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=top -BOARD=LeonLPP-M7A3P1k -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSIMFILES=testbench.vhd -SIMTOP=testbench -SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/Projet-Blanc-M7A3P1k.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3 -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm spi ac97 - -FILESKIP = i2cmst.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/ahbrom.vhd b/designs/ProjetBlanc-LeonLPP-M7A3P1k/ahbrom.vhd deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/ahbrom.vhd +++ /dev/null @@ -1,232 +0,0 @@ - ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2009 Aeroflex Gaisler ----------------------------------------------------------------------------- --- Entity: ahbrom --- File: ahbrom.vhd --- Author: Jiri Gaisler - Gaisler Research --- Description: AHB rom. 0/1-waitstate read ----------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; - -entity ahbrom is - generic ( - hindex : integer := 0; - haddr : integer := 0; - hmask : integer := 16#fff#; - pipe : integer := 0; - tech : integer := 0; - kbytes : integer := 1); - port ( - rst : in std_ulogic; - clk : in std_ulogic; - ahbsi : in ahb_slv_in_type; - ahbso : out ahb_slv_out_type - ); -end; - -architecture rtl of ahbrom is -constant abits : integer := 10; -constant bytes : integer := 560; - -constant hconfig : ahb_config_type := ( - 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), - 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); - -signal romdata : std_logic_vector(31 downto 0); -signal addr : std_logic_vector(abits-1 downto 2); -signal hsel, hready : std_ulogic; - -begin - - ahbso.hresp <= "00"; - ahbso.hsplit <= (others => '0'); - ahbso.hirq <= (others => '0'); - ahbso.hcache <= '1'; - ahbso.hconfig <= hconfig; - ahbso.hindex <= hindex; - - reg : process (clk) - begin - if rising_edge(clk) then - addr <= ahbsi.haddr(abits-1 downto 2); - end if; - end process; - - p0 : if pipe = 0 generate - ahbso.hrdata <= romdata; --ahbdrivedata(romdata); - ahbso.hready <= '1'; - end generate; - - p1 : if pipe = 1 generate - reg2 : process (clk) - begin - if rising_edge(clk) then - hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1); - hready <= ahbsi.hready; - ahbso.hready <= (not rst) or (hsel and hready) or - (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready); - ahbso.hrdata <= romdata; --ahbdrivedata(romdata); - end if; - end process; - end generate; - - comb : process (addr) - begin - case conv_integer(addr) is - when 16#00000# => romdata <= X"81D82000"; - when 16#00001# => romdata <= X"03000004"; - when 16#00002# => romdata <= X"821060E0"; - when 16#00003# => romdata <= X"81884000"; - when 16#00004# => romdata <= X"81900000"; - when 16#00005# => romdata <= X"81980000"; - when 16#00006# => romdata <= X"81800000"; - when 16#00007# => romdata <= X"A1800000"; - when 16#00008# => romdata <= X"01000000"; - when 16#00009# => romdata <= X"03002040"; - when 16#0000A# => romdata <= X"8210600F"; - when 16#0000B# => romdata <= X"C2A00040"; - when 16#0000C# => romdata <= X"84100000"; - when 16#0000D# => romdata <= X"01000000"; - when 16#0000E# => romdata <= X"01000000"; - when 16#0000F# => romdata <= X"01000000"; - when 16#00010# => romdata <= X"01000000"; - when 16#00011# => romdata <= X"01000000"; - when 16#00012# => romdata <= X"80108002"; - when 16#00013# => romdata <= X"01000000"; - when 16#00014# => romdata <= X"01000000"; - when 16#00015# => romdata <= X"01000000"; - when 16#00016# => romdata <= X"01000000"; - when 16#00017# => romdata <= X"01000000"; - when 16#00018# => romdata <= X"87444000"; - when 16#00019# => romdata <= X"8608E01F"; - when 16#0001A# => romdata <= X"88100000"; - when 16#0001B# => romdata <= X"8A100000"; - when 16#0001C# => romdata <= X"8C100000"; - when 16#0001D# => romdata <= X"8E100000"; - when 16#0001E# => romdata <= X"A0100000"; - when 16#0001F# => romdata <= X"A2100000"; - when 16#00020# => romdata <= X"A4100000"; - when 16#00021# => romdata <= X"A6100000"; - when 16#00022# => romdata <= X"A8100000"; - when 16#00023# => romdata <= X"AA100000"; - when 16#00024# => romdata <= X"AC100000"; - when 16#00025# => romdata <= X"AE100000"; - when 16#00026# => romdata <= X"90100000"; - when 16#00027# => romdata <= X"92100000"; - when 16#00028# => romdata <= X"94100000"; - when 16#00029# => romdata <= X"96100000"; - when 16#0002A# => romdata <= X"98100000"; - when 16#0002B# => romdata <= X"9A100000"; - when 16#0002C# => romdata <= X"9C100000"; - when 16#0002D# => romdata <= X"9E100000"; - when 16#0002E# => romdata <= X"86A0E001"; - when 16#0002F# => romdata <= X"16BFFFEF"; - when 16#00030# => romdata <= X"81E00000"; - when 16#00031# => romdata <= X"82102002"; - when 16#00032# => romdata <= X"81904000"; - when 16#00033# => romdata <= X"03000004"; - when 16#00034# => romdata <= X"821060E0"; - when 16#00035# => romdata <= X"81884000"; - when 16#00036# => romdata <= X"01000000"; - when 16#00037# => romdata <= X"01000000"; - when 16#00038# => romdata <= X"01000000"; - when 16#00039# => romdata <= X"83480000"; - when 16#0003A# => romdata <= X"8330600C"; - when 16#0003B# => romdata <= X"80886001"; - when 16#0003C# => romdata <= X"02800024"; - when 16#0003D# => romdata <= X"01000000"; - when 16#0003E# => romdata <= X"07000000"; - when 16#0003F# => romdata <= X"8610E178"; - when 16#00040# => romdata <= X"C108C000"; - when 16#00041# => romdata <= X"C118C000"; - when 16#00042# => romdata <= X"C518C000"; - when 16#00043# => romdata <= X"C918C000"; - when 16#00044# => romdata <= X"CD18C000"; - when 16#00045# => romdata <= X"D118C000"; - when 16#00046# => romdata <= X"D518C000"; - when 16#00047# => romdata <= X"D918C000"; - when 16#00048# => romdata <= X"DD18C000"; - when 16#00049# => romdata <= X"E118C000"; - when 16#0004A# => romdata <= X"E518C000"; - when 16#0004B# => romdata <= X"E918C000"; - when 16#0004C# => romdata <= X"ED18C000"; - when 16#0004D# => romdata <= X"F118C000"; - when 16#0004E# => romdata <= X"F518C000"; - when 16#0004F# => romdata <= X"F918C000"; - when 16#00050# => romdata <= X"FD18C000"; - when 16#00051# => romdata <= X"01000000"; - when 16#00052# => romdata <= X"01000000"; - when 16#00053# => romdata <= X"01000000"; - when 16#00054# => romdata <= X"01000000"; - when 16#00055# => romdata <= X"01000000"; - when 16#00056# => romdata <= X"89A00842"; - when 16#00057# => romdata <= X"01000000"; - when 16#00058# => romdata <= X"01000000"; - when 16#00059# => romdata <= X"01000000"; - when 16#0005A# => romdata <= X"01000000"; - when 16#0005B# => romdata <= X"10800005"; - when 16#0005C# => romdata <= X"01000000"; - when 16#0005D# => romdata <= X"01000000"; - when 16#0005E# => romdata <= X"00000000"; - when 16#0005F# => romdata <= X"00000000"; - when 16#00060# => romdata <= X"87444000"; - when 16#00061# => romdata <= X"8730E01C"; - when 16#00062# => romdata <= X"8688E00F"; - when 16#00063# => romdata <= X"12800016"; - when 16#00064# => romdata <= X"03200000"; - when 16#00065# => romdata <= X"05040E00"; - when 16#00066# => romdata <= X"8410A233"; - when 16#00067# => romdata <= X"C4204000"; - when 16#00068# => romdata <= X"0539A89B"; - when 16#00069# => romdata <= X"8410A260"; - when 16#0006A# => romdata <= X"C4206004"; - when 16#0006B# => romdata <= X"050003FC"; - when 16#0006C# => romdata <= X"C4206008"; - when 16#0006D# => romdata <= X"82103860"; - when 16#0006E# => romdata <= X"C4004000"; - when 16#0006F# => romdata <= X"8530A00C"; - when 16#00070# => romdata <= X"03000004"; - when 16#00071# => romdata <= X"82106009"; - when 16#00072# => romdata <= X"80A04002"; - when 16#00073# => romdata <= X"12800006"; - when 16#00074# => romdata <= X"033FFC00"; - when 16#00075# => romdata <= X"82106100"; - when 16#00076# => romdata <= X"0539A81B"; - when 16#00077# => romdata <= X"8410A260"; - when 16#00078# => romdata <= X"C4204000"; - when 16#00079# => romdata <= X"05000080"; - when 16#0007A# => romdata <= X"82100000"; - when 16#0007B# => romdata <= X"80A0E000"; - when 16#0007C# => romdata <= X"02800005"; - when 16#0007D# => romdata <= X"01000000"; - when 16#0007E# => romdata <= X"82004002"; - when 16#0007F# => romdata <= X"10BFFFFC"; - when 16#00080# => romdata <= X"8620E001"; - when 16#00081# => romdata <= X"3D1003FF"; - when 16#00082# => romdata <= X"BC17A3E0"; - when 16#00083# => romdata <= X"BC278001"; - when 16#00084# => romdata <= X"9C27A060"; - when 16#00085# => romdata <= X"03100000"; - when 16#00086# => romdata <= X"81C04000"; - when 16#00087# => romdata <= X"01000000"; - when 16#00088# => romdata <= X"00000000"; - when 16#00089# => romdata <= X"00000000"; - when 16#0008A# => romdata <= X"00000000"; - when 16#0008B# => romdata <= X"00000000"; - when 16#0008C# => romdata <= X"00000000"; - when others => romdata <= (others => '-'); - end case; - end process; - -- pragma translate_off - bootmsg : report_version - generic map ("ahbrom" & tost(hindex) & - ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" ); - -- pragma translate_on - end; diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18.dc b/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18.dc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18.dc +++ /dev/null @@ -1,102 +0,0 @@ -/*******************************************/ -/* Script to compile leon with synopsys DC */ -/* Jiri Gaisler, Gaisler Research, 2004 */ -/*******************************************/ - -search_path = {"." "/usr/local/synopsys/libraries/syn" "c:/Synopsys/libraries/syn"} -target_library = "SClib-max+ind.db" -link_library = "SClib-max+ind.db IO33lib-max+ind.db atc18mem.db PCIlib-max+ind.db" -link_library = "*" + link_library -symbol_library = "IO33lib-max+ind.sdb SClib-max+ind.sdb generic.sdb" -allow_newer_db_files = "true"; - -/* constraints - tailor to your own technology. An average 0.35 std-cell tech - should give you 80 - 100 MHz depending on ram access time. A 0.25 tech - should run at +150 MHz. Frequency in MHz, delays in ns ... */ - -frequency = 200 -clock_skew = 0.10 -input_setup = 2.0 -output_delay = 4.0 - -/* don't touch anything from here unless you know what you are doing */ - -include leon3mp.dc -include atc18cond.dc - -ungroup find(cell, "*pad*") -flatten - -group find(cell, {"sr*", "sdc", "apb*", "uart*", "timer*", "irq*" \ - "ahb*", "dsu0", "rst0", "dcom*" }) -design_name amod \ - -cell_name amod0 - -current_instance u0_0/p0 -ungroup -all -flatten -current_instance ../rf0 -ungroup -all -flatten -current_instance ../cmem0 -ungroup -all -flatten -current_instance ../../amod0 -ungroup -all -flatten -current_instance .. - -peri = 1000.0 / frequency -input_delay = peri - input_setup -tdelay = output_delay + 2 -create_clock -name "clk" -period peri -waveform { 0.0, peri / 2.0 } { "clk" } -set_wire_load_mode segmented - -set_clock_skew -plus_uncertainty clock_skew "clk" -set_clock_skew -minus_uncertainty clock_skew "clk" - -/* -set_input_delay input_delay -clock clk { \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" "brdyn" "bexcn" } - -set_max_delay tdelay -to { "errorn" "wdogn" \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" } - -set_max_delay output_delay -to { \ - "writen" "romsn[1]" "romsn[0]" "read" "oen" \ - "iosn" "rwen[3]" "rwen[2]" "rwen[1]" "rwen[0]" "ramsn[3]" \ - "ramsn[2]" "ramsn[1]" "ramsn[0]" \ - "ramoen[3]" "ramoen[2]" "ramoen[1]" "ramoen[0]" \ - "sdcsn[1]" "sdcsn[0]" "sdwen" "sdrasn" "sdcasn" \ - "sddqm[3]" "sddqm[2]" "sddqm[1]" "sddqm[0]" \ - "address[27]" "address[26]" "address[25]" "address[24]" \ - "address[23]" "address[22]" "address[21]" "address[20]" \ - "address[19]" "address[18]" "address[17]" "address[16]" \ - "address[15]" "address[14]" "address[13]" "address[12]" \ - "address[11]" "address[10]" "address[9]" "address[8]" \ - "address[7]" "address[6]" "address[5]" "address[4]" \ - "address[3]" "address[2]" "address[1]" "address[0]"} - -*/ -set_max_area 0 -set_max_transition 2.0 leon3mp -set_flatten false -design {"leon3mp.db:leon3mp"} -set_structure true -design {"leon3mp.db:leon3mp"} -boolean false -timing true - - -compile -map_effort medium -boundary_optimization - -write -f db -hier leon3mp -output leon3mp.db - -report_timing -report_area diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18.rc b/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18.rc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18.rc +++ /dev/null @@ -1,8 +0,0 @@ -set_attribute lib_search_path {. /usr/local/rs41/libs} -set_attribute library {"SClib-max+ind.lib" "IO33lib-max+ind.lib" "/home/jiri/ibm/vhdl/temic/atc18/allmem.lib" } / -include leon3mp.rc -include atc18cond.rc -define_clock -period 5000 -name clock1 clk -synthesize -to_mapped -report_area -report_timing diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18cond.dc b/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18cond.dc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18cond.dc +++ /dev/null @@ -1,536 +0,0 @@ -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[31] -to do[31] - -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[0] -to doa[0] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[1] -to doa[1] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[2] -to doa[2] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[3] -to doa[3] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[4] -to doa[4] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[5] -to doa[5] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[6] -to doa[6] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[7] -to doa[7] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[8] -to doa[8] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[9] -to doa[9] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[10] -to doa[10] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[11] -to doa[11] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[12] -to doa[12] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[13] -to doa[13] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[14] -to doa[14] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[15] -to doa[15] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[16] -to doa[16] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[17] -to doa[17] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[18] -to doa[18] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[19] -to doa[19] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[20] -to doa[20] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[21] -to doa[21] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[22] -to doa[22] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[23] -to doa[23] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[24] -to doa[24] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[25] -to doa[25] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[26] -to doa[26] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[27] -to doa[27] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[28] -to doa[28] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[29] -to doa[29] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[30] -to doa[30] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[31] -to doa[31] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[0] -to dob[0] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[1] -to dob[1] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[2] -to dob[2] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[3] -to dob[3] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[4] -to dob[4] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[5] -to dob[5] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[6] -to dob[6] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[7] -to dob[7] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[8] -to dob[8] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[9] -to dob[9] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[10] -to dob[10] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[11] -to dob[11] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[12] -to dob[12] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[13] -to dob[13] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[14] -to dob[14] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[15] -to dob[15] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[16] -to dob[16] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[17] -to dob[17] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[18] -to dob[18] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[19] -to dob[19] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[20] -to dob[20] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[21] -to dob[21] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[22] -to dob[22] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[23] -to dob[23] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[24] -to dob[24] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[25] -to dob[25] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[26] -to dob[26] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[27] -to dob[27] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[28] -to dob[28] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[29] -to dob[29] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[30] -to dob[30] -set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[31] -to dob[31] - -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[31] -to do[31] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[32] -to do[32] -set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[33] -to do[33] - -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[0] -to do[0] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[1] -to do[1] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[2] -to do[2] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[3] -to do[3] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[4] -to do[4] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[5] -to do[5] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[6] -to do[6] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[7] -to do[7] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[8] -to do[8] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[9] -to do[9] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[10] -to do[10] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[11] -to do[11] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[12] -to do[12] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[13] -to do[13] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[14] -to do[14] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[15] -to do[15] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[16] -to do[16] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[17] -to do[17] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[18] -to do[18] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[19] -to do[19] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[20] -to do[20] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[21] -to do[21] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[22] -to do[22] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[23] -to do[23] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[24] -to do[24] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[25] -to do[25] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[26] -to do[26] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[27] -to do[27] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[28] -to do[28] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[29] -to do[29] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[30] -to do[30] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[31] -to do[31] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[32] -to do[32] -set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[33] -to do[33] - -set_disable_timing IO33lib-max+ind/pt33b01 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b02 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b03 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b04 -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b01u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b02u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b03u -from pad -to cin -set_disable_timing IO33lib-max+ind/pt33b04u -from pad -to cin diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18cond.rc b/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18cond.rc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/atc18cond.rc +++ /dev/null @@ -1,528 +0,0 @@ -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_1024x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_128x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_256x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_512x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_64x32cm4sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_2048x32cm8sw0 -from di[31] -to do[31] - -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_64x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_128x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_256x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[0] -to doa[0] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[1] -to doa[1] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[2] -to doa[2] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[3] -to doa[3] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[4] -to doa[4] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[5] -to doa[5] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[6] -to doa[6] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[7] -to doa[7] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[8] -to doa[8] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[9] -to doa[9] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[10] -to doa[10] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[11] -to doa[11] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[12] -to doa[12] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[13] -to doa[13] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[14] -to doa[14] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[15] -to doa[15] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[16] -to doa[16] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[17] -to doa[17] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[18] -to doa[18] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[19] -to doa[19] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[20] -to doa[20] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[21] -to doa[21] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[22] -to doa[22] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[23] -to doa[23] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[24] -to doa[24] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[25] -to doa[25] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[26] -to doa[26] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[27] -to doa[27] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[28] -to doa[28] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[29] -to doa[29] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[30] -to doa[30] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dia[31] -to doa[31] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[0] -to dob[0] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[1] -to dob[1] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[2] -to dob[2] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[3] -to dob[3] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[4] -to dob[4] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[5] -to dob[5] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[6] -to dob[6] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[7] -to dob[7] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[8] -to dob[8] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[9] -to dob[9] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[10] -to dob[10] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[11] -to dob[11] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[12] -to dob[12] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[13] -to dob[13] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[14] -to dob[14] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[15] -to dob[15] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[16] -to dob[16] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[17] -to dob[17] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[18] -to dob[18] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[19] -to dob[19] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[20] -to dob[20] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[21] -to dob[21] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[22] -to dob[22] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[23] -to dob[23] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[24] -to dob[24] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[25] -to dob[25] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[26] -to dob[26] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[27] -to dob[27] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[28] -to dob[28] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[29] -to dob[29] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[30] -to dob[30] -dc::set_disable_timing atc18mem/hdss2_512x32cm4sw0 -from dib[31] -to dob[31] - -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[31] -to do[31] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[32] -to do[32] -dc::set_disable_timing atc18mem/hdss1_1024x34cm4sw0 -from di[33] -to do[33] - -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[0] -to do[0] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[1] -to do[1] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[2] -to do[2] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[3] -to do[3] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[4] -to do[4] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[5] -to do[5] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[6] -to do[6] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[7] -to do[7] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[8] -to do[8] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[9] -to do[9] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[10] -to do[10] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[11] -to do[11] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[12] -to do[12] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[13] -to do[13] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[14] -to do[14] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[15] -to do[15] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[16] -to do[16] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[17] -to do[17] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[18] -to do[18] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[19] -to do[19] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[20] -to do[20] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[21] -to do[21] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[22] -to do[22] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[23] -to do[23] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[24] -to do[24] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[25] -to do[25] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[26] -to do[26] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[27] -to do[27] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[28] -to do[28] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[29] -to do[29] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[30] -to do[30] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[31] -to do[31] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[32] -to do[32] -dc::set_disable_timing atc18mem/hdss1_2048x34cm8sw0 -from di[33] -to do[33] - diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.help b/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.help deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.help +++ /dev/null @@ -1,1171 +0,0 @@ - - -Prompt for target technology -CONFIG_SYN_INFERRED - Selects the target technology for memory and pads. - The following are available: - - - Inferred: Generic FPGA or ASIC targets if your synthesis tool - is capable of inferring RAMs and pads automatically. - - - Actel ProAsic/P/3 and Axellerator FPGAs - - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS - - Altera: Most Altera FPGA families - - Altera-Stratix: Altera Stratix FPGA family - - Altera-StratixII: Altera Stratix-II FPGA family - - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS - - IHP25: IHP 0.25 um CMOS - - IHP25RH: IHP Rad-Hard 0.25 um CMOS - - Lattice : EC/ECP/XP FPGAs - - Quicklogic : Eclipse/E/II FPGAs - - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries - - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries - - Xilinx-Spartan3E: Xilinx Spartan3E libraries - - Xilinx-Virtex/E: Xilinx Virtex/E libraries - - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries - - -Ram library -CONFIG_MEM_VIRAGE - Select RAM generators for ASIC targets. - -Infer ram -CONFIG_SYN_INFER_RAM - Say Y here if you want the synthesis tool to infer your - RAM automatically. Say N to directly instantiate technology- - specific RAM cells for the selected target technology package. - -Infer pads -CONFIG_SYN_INFER_PADS - Say Y here if you want the synthesis tool to infer pads. - Say N to directly instantiate technology-specific pads from - the selected target technology package. - -No async reset -CONFIG_SYN_NO_ASYNC - Say Y here if you disable asynchronous reset in some of the IP cores. - Might be necessary if the target library does not have cells with - asynchronous set/reset. - -Scan support -CONFIG_SYN_SCAN - Say Y here to enable scan support in some cores. This will enable - the scan support generics where available and add logic to make - the design testable using full-scan. - -Use Virtex CLKDLL for clock synchronisation -CONFIG_CLK_INFERRED - Certain target technologies include clock generators to scale or - phase-adjust the system and SDRAM clocks. This is currently supported - for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you - can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2), - the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL - (Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred' - option to skip a clock generator. - -Clock multiplier -CONFIG_CLK_MUL - When using the Xilinx DCM or Altera ALTPLL, the system clock can - be multiplied with a factor of 2 - 32, and divided by a factor of - 1 - 32. This makes it possible to generate almost any desired - processor frequency. When using the Xilinx CLKDLL generator, - the resulting frequency scale factor (mul/div) must be one of - 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128. - - WARNING: The resulting clock must be within the limits specified - by the target FPGA family. - -Clock divider -CONFIG_CLK_DIV - When using the Xilinx DCM or Altera ALTPLL, the system clock can - be multiplied with a factor of 2 - 32, and divided by a factor of - 1 - 32. This makes it possible to generate almost any desired - processor frequency. When using the Xilinx CLKDLL generator, - the resulting frequency scale factor (mul/div) must be one of - 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128. - - WARNING: The resulting clock must be within the limits specified - by the target FPGA family. - -Output clock divider -CONFIG_OCLK_DIV - When using the Proasic3 PLL, the system clock is generated by three - parameters: input clock multiplication, input clock division and - output clock division. Only certain values of these parameters - are allowed, but unfortunately this is not documented by Actel. - To find the correct values, run the Libero Smartgen tool and - insert you desired input and output clock frequencies in the - Static PLL configurator. The mul/div factors can then be read - out from tool. - -System clock multiplier -CONFIG_CLKDLL_1_2 - The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0, - or 2.0. Useful when the target board has an oscillator with a too high - (or low) frequency for your design. The divided clock will be used as the - main clock for the whole processor (except PCI and ethernet clocks). - -System clock multiplier -CONFIG_DCM_2_3 - The Xilinx DCM and Altera ALTDLL can scale the input clock with a large - range of factors. Useful when the target board has an oscillator with a - too high (or low) frequency for your design. The divided clock will - be used as the main clock for the whole processor (except PCI and - ethernet clocks). NOTE: the resulting frequency must be at least - 24 MHz or the DCM and ALTDLL might not work. - -Enable CLKDLL for PCI clock -CONFIG_PCI_CLKDLL - Say Y here to re-synchronize the PCI clock using a - Virtex BUFGDLL macro. Will improve PCI clock-to-output - delays on the expense of input-setup requirements. - -Use PCI clock system clock -CONFIG_PCI_SYSCLK - Say Y here to the PCI clock to generate the system clock. - The PCI clock can be scaled using the DCM or CLKDLL to - generate a suitable processor clock. - -External SDRAM clock feedback -CONFIG_CLK_NOFB - Say Y here to disable the external clock feedback to synchronize the - SDRAM clock. This option is necessary if your board or design does not - have an external clock feedback that is connected to the pllref input - of the clock generator. - -Number of processors -CONFIG_PROC_NUM - The number of processor cores. The LEON3MP design can accomodate - up to 4 LEON3 processor cores. Use 1 unless you know what you are - doing ... - -Number of SPARC register windows -CONFIG_IU_NWINDOWS - The SPARC architecture (and LEON) allows 2 - 32 register windows. - However, any number except 8 will require that you modify and - recompile your run-time system or kernel. Unless you know what - you are doing, use 8. - -SPARC V8 multiply and divide instruction -CONFIG_IU_V8MULDIV - If you say Y here, the SPARC V8 multiply and divide instructions - will be implemented. The instructions are: UMUL, UMULCC, SMUL, - SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent - integer multiplications and divisions, significant performance - increase can be achieved. Emulated floating-point operations will - also benefit from this option. - - By default, the gcc compiler does not emit multiply or divide - instructions and your code must be compiled with -mv8 to see any - performance increase. On the other hand, code compiled with -mv8 - will generate an illegal instruction trap when executed on processors - with this option disabled. - - The divider consumes approximately 2 kgates, the multiplier 6 kgates. - -Multiplier latency -CONFIG_IU_MUL_LATENCY_2 - Implementation options for the integer multiplier. - - Type Implementation issue-rate/latency - 2-clocks 32x32 pipelined multiplier 1/2 - 4-clocks 16x16 standard multiplier 4/4 - 5-clocks 16x16 pipelined multiplier 4/5 - -Multiplier latency -CONFIG_IU_MUL_MAC - If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate) - instructions will be enabled. The instructions implement a - single-cycle 16x16->32 bits multiply with a 40-bits accumulator. - The details of these instructions can be found in the LEON manual, - This option is only available when 16x16 multiplier is used. - -Single vector trapping -CONFIG_IU_SVT - Single-vector trapping is a SPARC V8e option to reduce code-size - in small applications. If enabled, the processor will jump to - the address of trap 0 (tt = 0x00) for all traps. No trap table - is then needed. The trap type is present in %psr.tt and must - be decoded by the O/S. Saves 4 Kbyte of code, but increases - trap and interrupt overhead. Currently, the only O/S supporting - this option is eCos. To enable SVT, the O/S must also set bit 13 - in %asr17. - -Load latency -CONFIG_IU_LDELAY - Defines the pipeline load delay (= pipeline cycles before the data - from a load instruction is available for the next instruction). - One cycle gives best performance, but might create a critical path - on targets with slow (data) cache memories. A 2-cycle delay can - improve timing but will reduce performance with about 5%. - -Reset address -CONFIG_IU_RSTADDR - By default, a SPARC processor starts execution at address 0. - With this option, any 4-kbyte aligned reset start address can be - choosen. Keep at 0 unless you really know what you are doing. - -Power-down -CONFIG_PWD - Say Y here to enable the power-down feature of the processor. - Might reduce the maximum frequency slightly on FPGA targets. - For details on the power-down operation, see the LEON3 manual. - -Hardware watchpoints -CONFIG_IU_WATCHPOINTS - The processor can have up to 4 hardware watchpoints, allowing to - create both data and instruction breakpoints at any memory location, - also in PROM. Each watchpoint will use approximately 500 gates. - Use 0 to disable the watchpoint function. - -Floating-point enable -CONFIG_FPU_ENABLE - Say Y here to enable the floating-point interface for the MEIKO - or GRFPU. Note that no FPU's are provided with the GPL version - of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial - cores and must be obtained separately. - -FPU selection -CONFIG_FPU_GRFPU - Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun - Meiko FPU core. All cores are fully IEEE-754 compatible and support - all SPARC FPU instructions. - -GRFPU Multiplier -CONFIG_FPU_GRFPU_INFMUL - On FPGA targets choose inferred multiplier. For ASIC implementations - choose between Synopsys Design Ware (DW) multiplier or Module - Generator (ModGen) multiplier. The DW multiplier gives better results - (smaller area and better timing) but requires a DW license. - The ModGen multiplier is part of GRLIB and does not require a license. - -Shared GRFPU -CONFIG_FPU_GRFPU_SH - If enabled multiple CPU cores will share one GRFPU. - -GRFPC Configuration -CONFIG_FPU_GRFPC0 - Configures the GRFPU-LITE controller. - - In simple configuration controller executes FP instructions - in parallel with integer instructions. FP operands are fetched - in the register file stage and the result is written in the write - stage. This option uses least area resources. - - Data forwarding configuration gives ~ 10 % higher FP performance than - the simple configuration by adding data forwarding between the pipeline - stages. - - Non-blocking controller allows FP load and store instructions to - execute in parallel with FP instructions. The performance increase is - ~ 20 % for FP applications. This option uses most logic resources and - is suitable for ASIC implementations. - -Floating-point netlist -CONFIG_FPU_NETLIST - Say Y here to use a VHDL netlist of the GRFPU-Lite. This is - only available in certain versions of grlib. - -Enable Instruction cache -CONFIG_ICACHE_ENABLE - The instruction cache should always be enabled to allow - maximum performance. Some low-end system might want to - save area and disable the cache, but this will reduce - the performance with a factor of 2 - 3. - -Enable Data cache -CONFIG_DCACHE_ENABLE - The data cache should always be enabled to allow - maximum performance. Some low-end system might want to - save area and disable the cache, but this will reduce - the performance with a factor of 2 at least. - -Instruction cache associativity -CONFIG_ICACHE_ASSO1 - The instruction cache can be implemented as a multi-set cache with - 1 - 4 sets. Higher associativity usually increases the cache hit - rate and thereby the performance. The downside is higher power - consumption and increased gate-count for tag comparators. - - Note that a 1-set cache is effectively a direct-mapped cache. - -Instruction cache set size -CONFIG_ICACHE_SZ1 - The size of each set in the instuction cache (kbytes). Valid values - are 1 - 64 in binary steps. Note that the full range is only supported - by the generic and virtex2 targets. Most target packages are limited - to 2 - 16 kbyte. Large set size gives higher performance but might - affect the maximum frequency (on ASIC targets). The total instruction - cache size is the number of set multiplied with the set size. - -Instruction cache line size -CONFIG_ICACHE_LZ16 - The instruction cache line size. Can be set to either 16 or 32 - bytes per line. Instruction caches typically benefit from larger - line sizes, but on small caches it migh be better with 16 bytes/line - to limit eviction miss rate. - -Instruction cache replacement algorithm -CONFIG_ICACHE_ALGORND - Cache replacement algorithm for caches with 2 - 4 sets. The 'random' - algorithm selects the set to evict randomly. The least-recently-replaced - (LRR) algorithm evicts the set least recently replaced. The least- - recently-used (LRU) algorithm evicts the set least recently accessed. - The random algorithm uses a simple 1- or 2-bit counter to select - the eviction set and has low area overhead. The LRR scheme uses one - extra bit in the tag ram and has therefore also low area overhead. - However, the LRR scheme can only be used with 2-set caches. The LRU - scheme has typically the best performance but also highest area overhead. - A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops - per line, and a 4-set LRU uses 5 flip-flops per line to store the access - history. - -Instruction cache locking -CONFIG_ICACHE_LOCK - Say Y here to enable cache locking in the instruction cache. - Locking can be done on cache-line level, but will increase the - width of the tag ram with one bit. If you don't know what - locking is good for, it is safe to say N. - -Data cache associativity -CONFIG_DCACHE_ASSO1 - The data cache can be implemented as a multi-set cache with - 1 - 4 sets. Higher associativity usually increases the cache hit - rate and thereby the performance. The downside is higher power - consumption and increased gate-count for tag comparators. - - Note that a 1-set cache is effectively a direct-mapped cache. - -Data cache set size -CONFIG_DCACHE_SZ1 - The size of each set in the data cache (kbytes). Valid values are - 1 - 64 in binary steps. Note that the full range is only supported - by the generic and virtex2 targets. Most target packages are limited - to 2 - 16 kbyte. A large cache gives higher performance but the - data cache is timing critical an a too large setting might affect - the maximum frequency (on ASIC targets). The total data cache size - is the number of set multiplied with the set size. - -Data cache line size -CONFIG_DCACHE_LZ16 - The data cache line size. Can be set to either 16 or 32 bytes per - line. A smaller line size gives better associativity and higher - cache hit rate, but requires a larger tag memory. - -Data cache replacement algorithm -CONFIG_DCACHE_ALGORND - See the explanation for instruction cache replacement algorithm. - -Data cache locking -CONFIG_DCACHE_LOCK - Say Y here to enable cache locking in the data cache. - Locking can be done on cache-line level, but will increase the - width of the tag ram with one bit. If you don't know what - locking is good for, it is safe to say N. - -Data cache snooping -CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. - -Separate snoop tags -CONFIG_DCACHE_SNOOP_SEPTAG - Enable a separate memory to store the data tags used for snooping. - This is necessary when snooping support is wanted in systems - with MMU, typically for SMP systems. In this case, the snoop - tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. - -Fixed cacheability map -CONFIG_CACHE_FIXED - If this variable is 0, the cacheable memory regions are defined - by the AHB plug&play information (default). To overriden the - plug&play settings, this variable can be set to indicate which - areas should be cached. The value is treated as a 16-bit hex value - with each bit defining if a 256 Mbyte segment should be cached or not. - The right-most (LSB) bit defines the cacheability of AHB address - 0 - 256 MByte, while the left-most bit (MSB) defines AHB address - 3840 - 4096 MByte. If the bit is set, the corresponding area is - cacheable. A value of 00F3 defines address 0 - 0x20000000 and - 0x40000000 - 0x80000000 as cacheable. - -Local data ram -CONFIG_DCACHE_LRAM - Say Y here to add a local ram to the data cache controller. - Accesses to the ram (load/store) will be performed at 0 waitstates - and store data will never be written back to the AHB bus. - -Size of local data ram -CONFIG_DCACHE_LRAM_SZ1 - Defines the size of the local data ram in Kbytes. Note that most - technology libraries do not support larger rams than 16 Kbyte. - -Start address of local data ram -CONFIG_DCACHE_LRSTART - Defines the 8 MSB bits of start address of the local data ram. - By default set to 8f (start address = 0x8f000000), but any value - (except 0) is possible. Note that the local data ram 'shadows' - a 16 Mbyte block of the address space. - -MMU enable -CONFIG_MMU_ENABLE - Say Y here to enable the Memory Management Unit. - -MMU split icache/dcache table lookaside buffer -CONFIG_MMU_COMBINED - Select "combined" for a combined icache/dcache table lookaside buffer, - "split" for a split icache/dcache table lookaside buffer - -MMU tlb replacement scheme -CONFIG_MMU_REPARRAY - Select "LRU" to use the "least recently used" algorithm for TLB - replacement, or "Increment" for a simple incremental replacement - scheme. - -Combined i/dcache tlb -CONFIG_MMU_I2 - Select the number of entries for the instruction TLB, or the - combined icache/dcache TLB if such is used. - -Split tlb, dcache -CONFIG_MMU_D2 - Select the number of entries for the dcache TLB. - -Fast writebuffer -CONFIG_MMU_FASTWB - Only selectable if split tlb is enabled. In case fast writebuffer is - enabled the tlb hit will be made concurrent to the cache hit. This - leads to higher store performance, but increased power and area. - -MMU pagesize -CONFIG_MMU_PAGE_4K - The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the - cache way size to 4 Kbyte, and total data cache size to 16 Kbyte, - when the MMU is used. To increase the maximum data cache size, - the MMU pages size can be increased to up 32 Kbyte. This will - give a maximum data cache size of 128 Kbyte. - - Note that an MMU page size different than 4 Kbyte will require - a special linux tool-chain if glibc is used. If you don't know - what you are doing, stay with 4 Kbyte ... - -DSU enable -CONFIG_DSU_ENABLE - The debug support unit (DSU) allows non-intrusive debugging and tracing - of both executed instructions and AHB transfers. If you want to enable - the DSU, say Y here and select the configuration below. - -Trace buffer enable -CONFIG_DSU_TRACEBUF - Say Y to enable the trace buffer. The buffer is not necessary for - debugging, only for tracing instructions and data transfers. - -Enable instruction tracing -CONFIG_DSU_ITRACE - If you say Y here, an instruction trace buffer will be implemented - in each processor. The trace buffer will trace executed instructions - and their results, and place them in a circular buffer. The buffer - can be read out by any AHB master, and in particular by the debug - communication link. - -Size of trace buffer -CONFIG_DSU_ITRACESZ1 - Select the buffer size (in kbytes) for the instruction trace buffer. - Each line in the buffer needs 16 bytes. A 128-entry buffer will thus - need 2 kbyte. - -Enable AHB tracing -CONFIG_DSU_ATRACE - If you say Y here, an AHB trace buffer will be implemented in the - debug support unit processor. The AHB buffer will trace all transfers - on the AHB bus and save them in a circular buffer. The trace buffer - can be read out by any AHB master, and in particular by the debug - communication link. - -Size of trace buffer -CONFIG_DSU_ATRACESZ1 - Select the buffer size (in kbytes) for the AHB trace buffer. - Each line in the buffer needs 16 bytes. A 128-entry buffer will thus - need 2 kbyte. - - -LEON3FT enable -CONFIG_LEON3FT_EN - Say Y here to use the fault-tolerant LEON3FT core instead of the - standard non-FT LEON3. - -IU Register file protection -CONFIG_IUFT_NONE - Select the FT implementation in the LEON3FT integer unit - register file. The options include parity, parity with - sparing, 7-bit BCH and TMR. - -FPU Register file protection -CONFIG_FPUFT_EN - Say Y to enable SEU protection of the FPU register file. - The GRFPU will be protected using 8-bit parity without restart, while - the GRFPU-Lite will be protected with 4-bit parity with restart. If - disabled the FPU register file will be implemented using flip-flops. - -Cache memory error injection -CONFIG_RF_ERRINJ - Say Y here to enable error injection in to the IU/FPU regfiles. - Affects only simulation. - -Cache memory protection -CONFIG_CACHE_FT_EN - Enable SEU error-correction in the cache memories. - -Cache memory error injection -CONFIG_CACHE_ERRINJ - Say Y here to enable error injection in to the cache memories. - Affects only simulation. - -Leon3ft netlist -CONFIG_LEON3_NETLIST - Say Y here to use a VHDL netlist of the LEON3FT. This is - only available in certain versions of grlib. - -IU assembly printing -CONFIG_IU_DISAS - Enable printing of executed instructions to the console. - -IU assembly printing in netlist -CONFIG_IU_DISAS_NET - Enable printing of executed instructions to the console also - when simulating a netlist. NOTE: with this option enabled, it - will not be possible to pass place&route. - -32-bit program counters -CONFIG_DEBUG_PC32 - Since the LSB 2 bits of the program counters always are zero, they are - normally not implemented. If you say Y here, the program counters will - be implemented with full 32 bits, making debugging of the VHDL model - much easier. Turn of this option for synthesis or you will be wasting - area. -CONFIG_AHB_DEFMST - Sets the default AHB master (see AMBA 2.0 specification for definition). - Should not be set to a value larger than the number of AHB masters - 1. - For highest processor performance, leave it at 0. - -Default AHB master -CONFIG_AHB_RROBIN - Say Y here to enable round-robin arbitration of the AHB bus. A N will - select fixed priority, with the master with the highest bus index having - the highest priority. - -Support AHB split-transactions -CONFIG_AHB_SPLIT - Say Y here to enable AHB split-transaction support in the AHB arbiter. - Unless you actually have an AHB slave that can generate AHB split - responses, say N and save some gates. - -Default AHB master -CONFIG_AHB_IOADDR - Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined - in the plug&play extentions of the AMBA bus. Should be kept to FFF - unless you really know what you are doing. - -APB bridge address -CONFIG_APB_HADDR - Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be - kept at 800 for software compatibility. - -AHB monitor -CONFIG_AHB_MON - Say Y to enable the AHB bus monitor. The monitor will check for - illegal AHB transactions during simulation. It has no impact on - synthesis. - -Report AHB errors -CONFIG_AHB_MONERR - Print out detected AHB violations on console. - -Report AHB warnings -CONFIG_AHB_MONWAR - Print out detected AHB warnings on console. - - -DSU enable -CONFIG_DSU_UART - Say Y to enable the AHB uart (serial-to-AHB). This is the most - commonly used debug communication link. - -JTAG Enable -CONFIG_DSU_JTAG - Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done - with GRMON through the boards JTAG chain at speed of 300 kbits/s. - Supported JTAG cables are Xilinx Parallel Cable III and IV. - -Ethernet DSU enable -CONFIG_DSU_ETH - Say Y to enable the Ethernet Debug Communication Link (EDCL). The link - provides a DSU gateway between ethernet and the AHB bus. Debugging is - done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must - enable the GRETH Ethernet MAC for this option to become active. - -Size of EDCL trace buffer -CONFIG_DSU_ETHSZ1 - Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is - usually enough, while a larger buffer will increase the transfer rate. - When operating at 100 Mbit, use a buffer size of at least 8 kbyte for - maximum throughput. - -MSB IP address -CONFIG_DSU_IPMSB - Set the MSB 16 bits of the IP address of the EDCL. - -LSB IP address -CONFIG_DSU_IPLSB - Set the LSB 16 bits of the IP address of the EDCL. - -MSB ethernet address -CONFIG_DSU_ETHMSB - Set the MSB 24 bits of the ethernet address of the EDCL. - -LSB ethernet address -CONFIG_DSU_ETHLSB - Set the LSB 24 bits of the ethernet address of the EDCL. - -Programmable MAC/IP address -CONFIG_DSU_ETH_PROG - Say Y to make the LSB 4 bits of the EDCL MAC and IP address - configurable using the ethi.edcladdr inputs. -PROM/SRAM memory controller -CONFIG_SRCTRL - Say Y here to enable a simple (and small) PROM/SRAM memory controller. - The controller has a fixed number of waitstates, and is primarily - intended for FPGA implementations. The RAM data bus is always 32 bits, - the PROM can be configured to either 8 or 32 bits (hardwired). - -8-bit memory support -CONFIG_SRCTRL_8BIT - If you say Y here, the simple PROM/SRAM memory controller will - implement 8-bit PROM mode. - -PROM waitstates -CONFIG_SRCTRL_PROMWS - Select the number of waitstates for PROM access. - -RAM waitstates -CONFIG_SRCTRL_RAMWS - Select the number of waitstates for RAM access. - -IO waitstates -CONFIG_SRCTRL_IOWS - Select the number of waitstates for IO access. - -Read-modify-write support -CONFIG_SRCTRL_RMW - Say Y here to perform byte- and half-word writes as a - read-modify-write sequence. This is necessary if your - SRAM does not have individual byte enables. If you are - unsure, it is safe to say Y. - -SRAM bank select -CONFIG_SRCTRL_SRBANKS - Select number of SRAM banks. - -SRAM bank size select -CONFIG_SRCTRL_BANKSZ - Select size of SRAM banks in kBytes. - -PROM address bit select -CONFIG_SRCTRL_ROMASEL - Select address bit for PROM bank decoding. -Leon2 memory controller -CONFIG_MCTRL_LEON2 - Say Y here to enable the LEON2 memory controller. The controller - can access PROM, I/O, SRAM and SDRAM. The bus width for PROM - and SRAM is programmable to 8-, 16- or 32-bits. - -8-bit memory support -CONFIG_MCTRL_8BIT - If you say Y here, the PROM/SRAM memory controller will support - 8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit. - Say N to save a few hundred gates. - -16-bit memory support -CONFIG_MCTRL_16BIT - If you say Y here, the PROM/SRAM memory controller will support - 16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit. - Say N to save a few hundred gates. - -Write strobe feedback -CONFIG_MCTRL_WFB - If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will - be used to enable the data bus drivers during write cycles. This - will guarantee that the data is still valid on the rising edge of - the write strobe. If you say N, the write strobes and the data bus - drivers will be clocked on the rising edge, potentially creating - a hold time problem in external memory or I/O. However, in all - practical cases, there is enough capacitance in the data bus lines - to keep the value stable for a few (many?) nano-seconds after the - buffers have been disabled, making it safe to say N and remove a - combinational path in the netlist that might be difficult to - analyze. - -Write strobe feedback -CONFIG_MCTRL_5CS - If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will - be enabled. If you don't intend to use it, say N and save some gates. - -SDRAM controller enable -CONFIG_MCTRL_SDRAM - Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't - intend to use SDRAM, say N and save about 1 kgates. - -SDRAM controller inverted clock -CONFIG_MCTRL_SDRAM_INVCLK - If you say Y here, the SDRAM controller output signals will be delayed - with 1/2 clock in respect to the SDRAM clock. This will allow the used - of an SDRAM clock which in not strictly in phase with the internal - clock. This option will limit the SDRAM frequency to 40 - 50 MHz. - - On FPGA targets without SDRAM clock synchronizations through PLL/DLL, - say Y. On ASIC targets, say N and tell your foundry to balance the - SDRAM clock output. - -SDRAM separate address buses -CONFIG_MCTRL_SDRAM_SEPBUS - Say Y here if your SDRAM is connected through separate address - and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000 - board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards. - -64-bit data bus -CONFIG_MCTRL_SDRAM_BUS64 - Say Y here to enable 64-bit SDRAM data bus. - -Page burst enable -CONFIG_MCTRL_PAGE - Say Y here to enable SDRAM page burst operation. This will implement - read operations using page bursts rather than 8-word bursts and save - about 500 gates (100 LUTs). Note that not all SDRAM supports page - burst, so use this option with care. - -Programmable page burst enable -CONFIG_MCTRL_PROGPAGE - Say Y here to enable programmable SDRAM page burst operation. This - will allow to dynamically enable/disable page burst by setting - bit 17 in MCFG2. - -SDRAM controller enable -CONFIG_SDCTRL - Say Y here to enabled a 32/64-bit PC133 SDRAM controller. - -SDRAM controller inverted clock -CONFIG_SDCTRL_INVCLK - If you say Y here, the SDRAM clock will be inverted in respect to the - system clock and the SDRAM signals. This will limit the SDRAM frequency - to 50/66 MHz, but has the benefit that you will not need a PLL to - generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets, - say N and tell your foundry to balance the SDRAM clock output. - -64-bit data bus -CONFIG_SDCTRL_BUS64 - Say Y here to enable 64-bit data bus. - -Page burst enable -CONFIG_SDCTRL_PAGE - Say Y here to enable SDRAM page burst operation. This will implement - read operations using page bursts rather than 8-word bursts and save - about 500 gates (100 LUTs). Note that not all SDRAM supports page - burst, so use this option with care. - -Programmable page burst enable -CONFIG_SDCTRL_PROGPAGE - Say Y here to enable programmable SDRAM page burst operation. This - will allow to dynamically enable/disable page burst by setting - bit 17 in MCFG2. - -On-chip rom -CONFIG_AHBROM_ENABLE - Say Y here to add a block on on-chip rom to the AHB bus. The ram - provides 0-waitstates read access, burst support, and 8-, 16- - and 32-bit data size. The rom will be syntheised into block rams - on Xilinx and Altera FPGA devices, and into gates on ASIC - technologies. GRLIB includes a utility to automatically create - the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB - documentation for details. - -On-chip rom address -CONFIG_AHBROM_START - Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy - a 1 Mbyte slot at the selected address. Default is 000, corresponding - to AHB address 0x00000000. When address 0x0 is selected, the rom area - of any other memory controller is set to 0x10000000 to avoid conflicts. - -Enable pipeline register for on-chip rom -CONFIG_AHBROM_PIPE - Say Y here to add a data pipeline register to the on-chip rom. - This should be done when the rom is implemenented in (ASIC) gates, - or in logic cells on FPGAs. Do not use this option when the rom is - implemented in block rams. If enabled, the rom will operate with - one waitstate. - -On-chip ram -CONFIG_AHBRAM_ENABLE - Say Y here to add a block on on-chip ram to the AHB bus. The ram - provides 0-waitstates read access and 0/1 waitstates write access. - All AHB burst types are supported, as well as 8-, 16- and 32-bit - data size. - -On-chip ram size -CONFIG_AHBRAM_SZ1 - Set the size of the on-chip AHB ram. The ram is infered/instantiated - as four byte-wide ram slices to allow byte and half-word write - accesses. It is therefore essential that the target package can - infer byte-wide rams. This is currently supported on the generic, - virtex, virtex2, proasic and axellerator targets. - -On-chip ram address -CONFIG_AHBRAM_START - Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy - a 1 Mbyte slot at the selected address. Default is A00, corresponding - to AHB address 0xA0000000. - -Gaisler Ethernet MAC enable -CONFIG_GRETH_ENABLE - Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has - one AHB master interface to read and write packets to memory, and one - APB slave interface for accessing the control registers. - -Gaisler Ethernet 1G MAC enable -CONFIG_GRETH_GIGA - Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC . - The 1G MAC is only available in the commercial version of GRLIB, - so do NOT enable it if you are using the GPL version. - -CONFIG_GRETH_FIFO4 - Set the depth of the receive and transmit FIFOs in the MAC core. - The MAC core will perform AHB burst read/writes with half the - size of the FIFO depth. - - -CAN interface enable -CONFIG_CAN_ENABLE - Say Y here to enable the CAN interace from OpenCores. The core has one - AHB slave interface for accessing the control registers. The CAN core - ir register-compatible with the SAJ1000 core from Philips. - -CAN register address -CONFIG_CANIO - The control registers of the CAN core occupy 4 kbyte, and are - mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting - defines at which address in the I/O area the registers appear (HADDR[19:8]). - -CAN interrupt -CONFIG_CANIRQ - Defines which interrupt number the CAN core will generate. - -CAN loob-back testing -CONFIG_CANLOOP - If you say Y here, the receiver and trasmitter of the CAN core will - be connected together in a loop-back fashion. This will make it - possible to perform loop-back test, but not data will be sent - or received from the outside. ONLY for testing! - -CAN Synchronous reset -CONFIG_CAN_SYNCRST - If you say Y here, the CAN core will be implemented with - synchronous reset rather than asynchronous. This is needed - when the target library does not implement registers with - async reset. Unless you know what you are doing, say N. - -CAN FT memories -CONFIG_CAN_FT - If you say Y here, the CAN FIFOs will be implemented using - SEU protected RAM blocks. Only applicable to the FT version - of grlib. -PCI interface type -CONFIG_PCI_SIMPLE_TARGET - The target-only PCI interface provides a simple target interface - without fifos. It is small and robust, and is suitable to be used - for DSU communications via PCI. - -PCI interface type -CONFIG_PCI_MASTER_TARGET - The master-target PCI interface provides a high-performance 32-bit - PCI interface with configurable FIFOs and optional DMA channel. - -PCI interface type -CONFIG_PCI_MASTER_TARGET_DMA - Say Y here to enable a DMA controller in the PCI master-target core. - The DMA controller can perform PCI<->memory data transfers - independently of the processor. - -PCI vendor id -CONFIG_PCI_VENDORID - Sets the PCI vendor ID in the PCI configuration area. - -PCI device id -CONFIG_PCI_DEVICEID - Sets the PCI device ID in the PCI configuration area. - -PCI initiator address -CONFIG_PCI_HADDR - Sets the MSB AHB adress (HADDR[31:20]) of the PCI initiator area. - -PCI FIFO depth -CONFIG_PCI_FIFO8 - The number words in the PCI FIFO buffers in the master-target - core. The master interface uses four 33-bit wide FIFOs, while the - target interface uses two. - - -PCI arbiter enable -CONFIG_PCI_ARBITER - To enable a PCI arbiter, say Y here. - -PCI APB interface enable -CONFIG_PCI_ARBITER_APB - Say Y here to enable the APB interface on the PCI arbiter. This makes - it possible to dynamically re-assign PCI master priorities. See the - PCI arbiter manual for details. - -PCI arbiter request signals -CONFIG_PCI_ARBITER_NREQ - The number of PCI bus request/grant pairs. Should be not - be more than 8. Note that the processor needs one, so the - minimum should be 2. - -PCI trace buffer -CONFIG_PCI_TRACE - The PCI trace buffer implements a simple on-chip logic analyzer - to trace the PCI signals. The PCI AD bus and most control signals - are stored in a circular buffer, and can be read out by the DSU - or any other AHB master. See the manual for detailed operation. - Only available for target technologies with dual-port rams. - -PCI trace buffer depth -CONFIG_PCI_TRACE256 - Select the number of entries in the PCI trace buffer. Each entry - will use 6 bytes of on-chip (block) ram. - - -Spacewire link -CONFIG_SPW_ENABLE - Say Y here to enable one or more Spacewire serial links. The links - are based on the GRSPW core from Gaisler Research. - -Number of spacewire links -CONFIG_SPW_NUM - Select the number of links to implement. Each link will be a - separate AHB master and APB slave for configuration. - -AHB FIFO depth -CONFIG_SPW_AHBFIFO4 - Select the AHB FIFO depth (in 32-bit words). - -RX FIFO depth -CONFIG_SPW_RXFIFO16 - Select the receiver FIFO depth (in bytes). - -RMAP protocol -CONFIG_SPW_RMAP - Enable hardware target support for the RMAP protocol ( - draft C for GRSPW1 and ECSS-E-ST-50-11C Draft V1.3 - for GRSPW2). - -RMAP Buffer depth -CONFIG_SPW_RMAPBUF2 - Select the size of the RMAP buffer (in bytes). - -RMAP CRC -CONFIG_SPW_RMAPCRC - Enable hardware calculation of the RMAP CRC checksum. RMAP CRC - is always enabled when the RMAP hardware target is enabled so this - parameter will have no effect in that case. - -Rx unaligned -CONFIG_SPW_RXUNAL - Enable support for byte writes used for non word-aligned - receiver buffer addresses. Without this enabled data will - still be written at the correct location but complete words - will always be written so data outside the intended boundaries - might be overwritten. - -Netlists -CONFIG_SPW_NETLIST - Use the netlist version of GRSPWC. This option is required if - you have not licensed the source code of the Spacewire core. - Currently only supported for Virtex and Axcelerator FPGAs. - The AHB/RX FIFO sizes should be set to 16 word/byte, and the - RMAP should be disabled. - -Spacewire FT -CONFIG_SPW_FT - Say Y here to implement the Spacewire block rams with fault-tolerance - against SEU errors. - -Spacewire core -CONFIG_SPW_GRSPW1 - Select to use GRSPW1 core or GRSPW2 core. - -DMA channels -CONFIG_SPW_DMACHAN - Set the number of DMA channels for the GRSPW2 core - -Ports -CONFIG_SPW_PORTS - Set the number of SpaceWire ports for the GRSPW2 core - -Same clock for SpaceWire receiver and transmitter -CONFIG_SPW_RTSAME - Say Y here if the same clock is connected to both the receiver - and transmitter in the GRSPW2 core. This will remove two - asynchronous resets and some synchronization logic. This is only - applicable for the SDR and DDR inputs modes. - - -Receiver clock type -CONFIG_SPW_RX_SDR - Selects the input clocking scheme for the GRSPW2. SDR means that the - core samples data and strobe using single data rate registers at the - receiver clock frequency. DDR is the same except DDR registers are used. - Xor selects the traditional self clocking scheme using a xor gate. - Aeroflex sets the receiver in a mode compatible with the Aeroflex - SpaceWire transceiver. - -Receiver clock type -CONFIG_SPW_TX_SDR - Selects the output clocking scheme for the GRSPW2. SDR means that the - core transmits data and strobe using single data rate registers at the - transmitter clock frequency. DDR is the same except DDR registers are used. - Aeroflex sets the transmitter in a mode compatible with the Aeroflex - SpaceWire transceiver. -UART1 enable -CONFIG_UART1_ENABLE - Say Y here to enable UART1, or the console UART. This is needed to - get any print-out from LEON3 systems regardless of operating system. - -UART1 FIFO -CONFIG_UA1_FIFO1 - The UART has configurable transmitt and receive FIFO's, which can - be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for - maximum throughput. - - -UART2 enable -CONFIG_UART2_ENABLE - Say Y here to enable UART2, or the secondary UART. This UART can be - used to connect a second console (uClinux) or to control external - equipment. - -UART2 FIFO -CONFIG_UA2_FIFO1 - The UART has configurable transmitt and receive FIFO's, which can - be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for - maximum throughput. - -LEON3 interrupt controller -CONFIG_IRQ3_ENABLE - Say Y here to enable the LEON3 interrupt controller. This is needed - if you want to be able to receive interrupts. Operating systems like - Linux, RTEMS and eCos needs this option to be enabled. If you intend - to use the Bare-C run-time and not use interrupts, you could disable - the interrupt controller and save about 500 gates. - -LEON3 interrupt controller broadcast -CONFIG_IRQ3_BROADCAST_ENABLE - If enabled the broadcast register is used to determine which - interrupt should be sent to all cpus instead of just the first - one that consumes it. - -Secondary interrupts -CONFIG_IRQ3_SEC - The interrupt controller handles 15 interrupts by default (1 - 15). - These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F), - and AMBA interrupts 1 - 15. This option will enable 16 additional - (secondary) interrupts, corresponding to AMBA interrupts 16 - 31. - The secondary interrupts will be multiplexed onto one of the first - 15 interrupts. The total number of handled interrupts can then - be up to 30 (14 primary and 16 secondary). - -Number of interrupts -CONFIG_IRQ3_NSEC - Defines which of the first 15 interrupts should be used for the - secondary (16 - 31) interrupts. Interrupt 15 should be avoided - since it is not maskable by the processor. -Timer module enable -CONFIG_GPT_ENABLE - Say Y here to enable the Modular Timer Unit. The timer unit consists - of one common scaler and up to 7 independent timers. The timer unit - is needed for Linux, RTEMS, eCos and the Bare-C run-times. - -Timer module enable -CONFIG_GPT_NTIM - Set the number of timers in the timer unit (1 - 7). - -Scaler width -CONFIG_GPT_SW - Set the width if the common pre-scaler (2 - 16 bits). The scaler - is used to divide the system clock down to 1 MHz, so 8 bits should - be sufficient for most implementations (allows clocks up to 256 MHz). - -Timer width -CONFIG_GPT_TW - Set the width if the timers (2 - 32 bits). 32 bits is recommended - for the Bare-C run-time, lower values (e.g. 16 bits) can work with - RTEMS and Linux. - -Timer Interrupt -CONFIG_GPT_IRQ - Set the interrupt number for the first timer. Remaining timers will - have incrementing interrupts, unless the separate-interrupts option - below is disabled. - -Watchdog enable -CONFIG_GPT_WDOGEN - Say Y here to enable the watchdog functionality in the timer unit. - -Watchdog time-out value -CONFIG_GPT_WDOG - This value will be loaded in the watchdog timer at reset. - -GPIO port -CONFIG_GRGPIO_ENABLE - Say Y here to enable a general purpose I/O port. The port can be - configured from 1 - 32 bits, whith each port signal individually - programmable as input or output. The port signals can also serve - as interrupt inputs. - -GPIO port witdth -CONFIG_GRGPIO_WIDTH - Number of bits in the I/O port. Must be in the range of 1 - 32. - -GPIO interrupt mask -CONFIG_GRGPIO_IMASK - The I/O port interrupt mask defines which bits in the I/O port - should be able to create an interrupt. - -UART debugging -CONFIG_DEBUG_UART - During simulation, the output from the UARTs is printed on the - simulator console. Since the ratio between the system clock and - UART baud-rate is quite high, simulating UART output will be very - slow. If you say Y here, the UARTs will print a character as soon - as it is stored in the transmitter data register. The transmitter - ready flag will be permanently set, speeding up simulation. However, - the output on the UART tx line will be garbled. Has not impact on - synthesis, but will cause the LEON test bench to fail. - -FPU register tracing -CONFIG_DEBUG_FPURF - If you say Y here, all writes to the floating-point unit register file - will be printed on the simulator console. - diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.in b/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.in deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.in +++ /dev/null @@ -1,89 +0,0 @@ -# -# LEON3 configuration written in linux configuration language -# -# Written by Jiri Gaisler, Gaisler Research -# -# Comments and bug reports to jiri@gaisler.com -# -# - -#define_bool CONFIG_MCTRL_RMW y - -mainmenu_name "LEON3MP Design Configuration" - -mainmenu_option next_comment - comment 'Synthesis ' - source lib/techmap/gencomp/tech.in -endmenu - -mainmenu_option next_comment - comment 'Clock generation' - source lib/techmap/clocks/clkgen.in -endmenu - -source lib/gaisler/leon3/leon3.in -source lib/grlib/amba/amba.in - -mainmenu_option next_comment - comment 'Debug Link ' - source lib/gaisler/uart/dcom.in - source lib/gaisler/jtag/jtag.in - source lib/gaisler/net/edcl.in -endmenu - -mainmenu_option next_comment -comment 'Peripherals ' - - mainmenu_option next_comment - comment 'Memory controllers ' - source lib/gaisler/memctrl/srctrl.in - source lib/esa/memoryctrl/mctrl.in - source lib/gaisler/memctrl/sdctrl.in - endmenu - - mainmenu_option next_comment - comment 'On-chip RAM/ROM ' - source lib/gaisler/misc/ahbrom.in - source lib/gaisler/misc/ahbram.in - endmenu - - mainmenu_option next_comment - comment 'Ethernet ' - source lib/gaisler/greth/greth.in - endmenu - - mainmenu_option next_comment - comment 'CAN ' - source lib/gaisler/can/can_oc.in - endmenu - - mainmenu_option next_comment - comment 'PCI ' - source lib/gaisler/pci/pci_target.in - source lib/gaisler/pci/pci_mtf.in - source lib/gaisler/pci/pcidma.in - source lib/gaisler/pci/pci.in - source lib/esa/pci/pci_arb.in - source lib/gaisler/pci/pcitrace.in - endmenu - - mainmenu_option next_comment - comment 'Spacewire ' - source lib/gaisler/spacewire/spacewire.in - endmenu - - mainmenu_option next_comment - comment 'UARTs, timers and irq control ' - source lib/gaisler/uart/uart1.in - source lib/gaisler/uart/uart2.in - source lib/gaisler/leon3/irqmp.in - source lib/gaisler/misc/gptimer.in - source lib/gaisler/misc/grgpio.in - endmenu - -endmenu - -mainmenu_option next_comment -comment 'VHDL Debugging ' - source lib/grlib/util/debug.in -endmenu diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd b/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd +++ /dev/null @@ -1,180 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3; - constant CFG_MEMTECH : integer := apa3; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := apa3; - constant CFG_CLKMUL : integer := (5); - constant CFG_CLKDIV : integer := (10); - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - constant CFG_NWIN : integer := (7); - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 0 + 16*0; - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (2); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd.h b/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd.h deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd.h +++ /dev/null @@ -1,208 +0,0 @@ --- Technology and synthesis options - constant CFG_FABTECH : integer := CONFIG_SYN_TECH; - constant CFG_MEMTECH : integer := CFG_RAM_TECH; - constant CFG_PADTECH : integer := CFG_PAD_TECH; - constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; - constant CFG_SCAN : integer := CONFIG_SYN_SCAN; - --- Clock generator - constant CFG_CLKTECH : integer := CFG_CLK_TECH; - constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; - constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; - constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; - constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; - constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; - constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; - --- LEON3 processor core - constant CFG_LEON3 : integer := CONFIG_LEON3; - constant CFG_NCPU : integer := CONFIG_PROC_NUM; - constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; - constant CFG_V8 : integer := CFG_IU_V8; - constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; - constant CFG_SVT : integer := CONFIG_IU_SVT; - constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; - constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; - constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; - constant CFG_PWD : integer := CONFIG_PWD*2; - constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST; - constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; - constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; - constant CFG_ISETS : integer := CFG_IU_ISETS; - constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; - constant CFG_ILINE : integer := CFG_ILINE_SZ; - constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; - constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; - constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; - constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; - constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; - constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; - constant CFG_DSETS : integer := CFG_IU_DSETS; - constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; - constant CFG_DLINE : integer := CFG_DLINE_SZ; - constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; - constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; - constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; - constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; - constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; - constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; - constant CFG_MMUEN : integer := CONFIG_MMUEN; - constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; - constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; - constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; - constant CFG_TLB_REP : integer := CONFIG_TLB_REP; - constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; - constant CFG_DSU : integer := CONFIG_DSU_ENABLE; - constant CFG_ITBSZ : integer := CFG_DSU_ITB; - constant CFG_ATBSZ : integer := CFG_DSU_ATB; - constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; - constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; - constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; - constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; - constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; - constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; - constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; - constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; - constant CFG_PCLOW : integer := CFG_DEBUG_PC32; - --- AMBA settings - constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; - constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; - constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; - constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; - constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; - constant CFG_AHB_MON : integer := CONFIG_AHB_MON; - constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; - constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; - --- DSU UART - constant CFG_AHB_UART : integer := CONFIG_DSU_UART; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG; - constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; - constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; - constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; - constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; - constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; - --- PROM/SRAM controller - constant CFG_SRCTRL : integer := CONFIG_SRCTRL; - constant CFG_SRCTRL_PROMWS : integer := CONFIG_SRCTRL_PROMWS; - constant CFG_SRCTRL_RAMWS : integer := CONFIG_SRCTRL_RAMWS; - constant CFG_SRCTRL_IOWS : integer := CONFIG_SRCTRL_IOWS; - constant CFG_SRCTRL_RMW : integer := CONFIG_SRCTRL_RMW; - constant CFG_SRCTRL_8BIT : integer := CONFIG_SRCTRL_8BIT; - - constant CFG_SRCTRL_SRBANKS : integer := CFG_SR_CTRL_SRBANKS; - constant CFG_SRCTRL_BANKSZ : integer := CFG_SR_CTRL_BANKSZ; - constant CFG_SRCTRL_ROMASEL : integer := CONFIG_SRCTRL_ROMASEL; --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; - constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; - constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; - constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; - constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; - constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; - constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; - constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; - constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; - --- SDRAM controller - constant CFG_SDCTRL : integer := CONFIG_SDCTRL; - constant CFG_SDCTRL_INVCLK : integer := CONFIG_SDCTRL_INVCLK; - constant CFG_SDCTRL_SD64 : integer := CONFIG_SDCTRL_BUS64; - constant CFG_SDCTRL_PAGE : integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE; - --- AHB ROM - constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; - constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; - constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; - constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; - constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; - constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; - constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; - constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; - constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; - --- CAN 2.0 interface - constant CFG_CAN : integer := CONFIG_CAN_ENABLE; - constant CFG_CANIO : integer := 16#CONFIG_CANIO#; - constant CFG_CANIRQ : integer := CONFIG_CANIRQ; - constant CFG_CANLOOP : integer := CONFIG_CANLOOP; - constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST; - constant CFG_CANFT : integer := CONFIG_CAN_FT; - --- PCI interface - constant CFG_PCI : integer := CFG_PCITYPE; - constant CFG_PCIVID : integer := 16#CONFIG_PCI_VENDORID#; - constant CFG_PCIDID : integer := 16#CONFIG_PCI_DEVICEID#; - constant CFG_PCIDEPTH : integer := CFG_PCIFIFO; - constant CFG_PCI_MTF : integer := CFG_PCI_ENFIFO; - --- PCI arbiter - constant CFG_PCI_ARB : integer := CONFIG_PCI_ARBITER; - constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB; - constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ; - --- PCI trace buffer - constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE; - constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF; - --- Spacewire interface - constant CFG_SPW_EN : integer := CONFIG_SPW_ENABLE; - constant CFG_SPW_NUM : integer := CONFIG_SPW_NUM; - constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO; - constant CFG_SPW_RXFIFO : integer := CONFIG_SPW_RXFIFO; - constant CFG_SPW_RMAP : integer := CONFIG_SPW_RMAP; - constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF; - constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC; - constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST; - constant CFG_SPW_FT : integer := CONFIG_SPW_FT; - constant CFG_SPW_GRSPW : integer := CONFIG_SPW_GRSPW; - constant CFG_SPW_RXUNAL : integer := CONFIG_SPW_RXUNAL; - constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN; - constant CFG_SPW_PORTS : integer := CONFIG_SPW_PORTS; - constant CFG_SPW_INPUT : integer := CONFIG_SPW_INPUT; - constant CFG_SPW_OUTPUT : integer := CONFIG_SPW_OUTPUT; - constant CFG_SPW_RTSAME : integer := CONFIG_SPW_RTSAME; --- UART 1 - constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; - constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; - --- UART 2 - constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE; - constant CFG_UART2_FIFO : integer := CFG_UA2_FIFO; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; - constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; - --- Modular timer - constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; - constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; - constant CFG_GPT_SW : integer := CONFIG_GPT_SW; - constant CFG_GPT_TW : integer := CONFIG_GPT_TW; - constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; - constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; - constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; - constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; - constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; - constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; - --- GRLIB debugging - constant CFG_DUART : integer := CONFIG_DEBUG_UART; - diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd.in b/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd.in deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/config.vhd.in +++ /dev/null @@ -1,16 +0,0 @@ -#include "config.h" -#include "tkconfig.h" ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - -#include "config.vhd.h" - -end; diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/data/leon3mp.pdc.ce b/designs/ProjetBlanc-LeonLPP-M7A3P1k/data/leon3mp.pdc.ce deleted file mode 100644 index 15cb0ecb3e219d1701294bfdf0fe3f5cb5d208e7..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 GIT binary patch literal 0 Hc$@ -# - Remove unused do_cmd function (part of the 2.0 sound support). -# - Arrange buttons in three columns for better screen fitting. -# - Add CONSTANT_Y, CONSTANT_M, CONSTANT_N for commands like: -# dep_tristate 'foo' CONFIG_FOO m -# -# 23 January 1999, Michael Elizabeth Chastain, -# - Shut vfix the hell up. -# -# 24 January 1999, Michael Elizabeth Chastain, -# - Improve the exit message (Jeff Ronne). - -# -# This is a handy replacement for ".widget cget" that requires neither tk4 -# nor additional source code uglification. -# -proc cget { w option } { - return "[lindex [$w configure $option] 4]" -} - -# -# Function to compensate for broken config.in scripts like the sound driver, -# which make dependencies on variables that are never even conditionally -# defined. -# -proc vfix { var } { - global $var - if [ catch {eval concat $$var} ] { - set $var 4 - } -} - -# -# Constant values used by certain dep_tristate commands. -# -set CONSTANT_Y 1 -set CONSTANT_M 2 -set CONSTANT_N 0 -set CONSTANT_E 4 - -# -# Create a "reference" object to steal colors from. -# -button .ref - -# -# On monochrome displays, -disabledforeground is blank by default; that's -# bad. Fill it with -foreground instead. -# -if { [cget .ref -disabledforeground] == "" } { - .ref configure -disabledforeground [cget .ref -foreground] -} - - -# -# Define some macros we will need to parse the config.in file. -# - -proc mainmenu_name { text } { - wm title . "$text" -} - -proc menu_option { w menu_num text } { - global menus_per_column - global processed_top_level - set processed_top_level [expr $processed_top_level + 1] - if { $processed_top_level <= $menus_per_column } then { - set myframe left - } elseif { $processed_top_level <= [expr 2 * $menus_per_column] } then { - set myframe middle - } else { - set myframe right - } - button .f0.x$menu_num -anchor w -text "$text" \ - -command "$w .$w \"$text\"" - pack .f0.x$menu_num -pady 0 -side top -fill x -in .f0.$myframe -} - -proc load_configfile { w title func } { - catch {destroy $w} - toplevel $w -class Dialog - global loadfile - frame $w.x - label $w.bm -bitmap questhead - pack $w.bm -pady 10 -side top -padx 10 - label $w.x.l -text "Enter filename:" -relief raised - entry $w.x.x -width 35 -relief sunken -borderwidth 2 \ - -textvariable loadfile - pack $w.x.l $w.x.x -anchor w -side left - pack $w.x -side top -pady 10 - wm title $w "$title" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" -width 20 \ - -command "destroy $w; focus $oldFocus;$func .fileio" - button $w.f.canc -text "Cancel" \ - -width 20 -command "destroy $w; focus $oldFocus" - pack $w.f.back $w.f.canc -side left -pady 10 -padx 45 - pack $w.f -pady 10 -side bottom -padx 10 -anchor w - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy -} - -bind all {maybe_exit .maybe} - -proc maybe_exit { w } { - catch {destroy $w} - toplevel $w -class Dialog - label $w.bm -bitmap questhead - pack $w.bm -pady 10 -side top -padx 10 - message $w.m -width 400 -aspect 300 \ - -text "Changes will be lost. Are you sure?" -relief flat - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Are you sure?" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" -width 20 \ - -command "exit 1" - button $w.f.canc -text "Cancel" \ - -width 20 -command "destroy $w; focus $oldFocus" - pack $w.f.back $w.f.canc -side left -pady 10 -padx 45 - pack $w.f -pady 10 -side bottom -padx 10 -anchor w - bind $w "exit 1" - bind $w "destroy $w; focus $oldFocus" - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy -} - -proc read_config_file { w } { - global loadfile - if { [string length $loadfile] != 0 && [file readable $loadfile] == 1 } then { - read_config $loadfile - } else { - catch {destroy $w} - toplevel $w -class Dialog - message $w.m -width 400 -aspect 300 -text \ - "Unable to read file $loadfile" \ - -relief raised - label $w.bm -bitmap error - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "Xconfig Internal Error" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "Bummer" \ - -width 10 -command "destroy $w; focus $oldFocus" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - } -} - -proc write_config_file { w } { - global loadfile - if { [string length $loadfile] != 0 - && ([file writable $loadfile] == 1 || ([file exists $loadfile] == 0 && [file writable [file dirname $loadfile]] == 1)) } then { - writeconfig $loadfile .null - } else { - catch {destroy $w} - toplevel $w -class Dialog - message $w.m -width 400 -aspect 300 -text \ - "Unable to write file $loadfile" \ - -relief raised - label $w.bm -bitmap error - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "Xconfig Internal Error" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" \ - -width 10 -command "destroy $w; focus $oldFocus" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - } -} - -proc read_config { filename } { - set file1 [open $filename r] - clear_choices - while { [gets $file1 line] >= 0} { - if [regexp {([0-9A-Za-z_]+)=([ynm])} $line foo var value] { - if { $value == "y" } then { set cmd "global $var; set $var 1" } - if { $value == "n" } then { set cmd "global $var; set $var 0" } - if { $value == "m" } then { set cmd "global $var; set $var 2" } - eval $cmd - } - if [regexp {# ([0-9A-Za-z_]+) is not set} $line foo var] { - set cmd "global $var; set $var 0" - eval $cmd - } - if [regexp {([0-9A-Za-z_]+)=([0-9A-Fa-f]+)} $line foo var value] { - set cmd "global $var; set $var $value" - eval $cmd - } - if [regexp {([0-9A-Za-z_]+)="([^"]*)"} $line foo var value] { - set cmd "global $var; set $var \"$value\"" - eval $cmd - } - } - close $file1 - update_choices - update_mainmenu -} -proc write_comment { file1 file2 text } { - puts $file1 "" - puts $file1 "#" - puts $file1 "# $text" - puts $file1 "#" - puts $file2 "/*" - puts $file2 " * $text" - puts $file2 " */" -} - -proc effective_dep { deplist } { - global CONFIG_MODULES - set depend 1 - foreach i $deplist { - if {$i == 0} then {set depend 0} - if {$i == 2 && $depend == 1} then {set depend 2} - } - if {$depend == 2 && $CONFIG_MODULES == 0} then {set depend 0} - return $depend -} - -proc sync_tristate { var dep } { - global CONFIG_MODULES - if {$dep == 0 && ($var == 1 || $var == 2)} then { - set var 0 - } elseif {$dep == 2 && $var == 1} then { - set var 2 - } elseif {$var == 2 && $CONFIG_MODULES == 0} then { - if {$dep == 1} then {set var 1} else {set var 0} - } - return $var -} - -proc sync_bool { var dep modset } { - set var [sync_tristate $var $dep] - if {$dep == 2 && $var == 2} then { - set var $modset - } - return $var -} - -proc write_tristate { file1 file2 varname variable deplist modset } { - set variable [sync_tristate $variable [effective_dep $deplist]] - if { $variable == 2 } \ - then { set variable $modset } - if { $variable == 1 } \ - then { puts $file1 "$varname=y"; \ - puts $file2 "#define $varname 1" } \ - elseif { $variable == 2 } \ - then { puts $file1 "$varname=m"; \ - puts $file2 "#undef $varname"; \ - puts $file2 "#define ${varname}_MODULE 1" } \ - elseif { $variable == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { \ - puts stdout "ERROR - Attempting to write value for unconfigured variable ($varname)." \ - } -} - -proc write_int { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=$variable"; \ - puts $file2 "#define $varname ($variable)"; \ - } -} - -proc write_hex { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=$variable"; \ - puts -nonewline $file2 "#define $varname "; \ - puts $file2 [exec echo $variable | sed s/^0\[xX\]//]; \ - } -} - -proc write_string { file1 file2 varname variable dep } { - if { $dep == 0 } \ - then { puts $file1 "# $varname is not set"; \ - puts $file2 "#undef $varname"} \ - else { - puts $file1 "$varname=\"$variable\""; \ - puts $file2 "#define $varname \"$variable\""; \ - } -} - -proc option_name {w mnum line text helpidx} { - button $w.x$line.l -text "$text" -relief groove -anchor w - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] - button $w.x$line.help -text "Help" -relief raised \ - -command "dohelp .dohelp $helpidx .menu$mnum" - pack $w.x$line.help -side right -fill y - pack $w.x$line.l -side right -fill both -expand on -} - -proc toggle_switch2 {w mnum line text variable} { - frame $w.x$line -relief sunken - radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \ - -relief groove -width 2 -command "update_active" -# radiobutton $w.x$line.m -text "-" -variable $variable -value 2 \ -# -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \ - -relief groove -width 2 -command "update_active" - - option_name $w $mnum $line $text $variable - - pack $w.x$line.n $w.x$line.y -side right -fill y -} - -proc toggle_switch3 {w mnum line text variable} { - frame $w.x$line -relief sunken - radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \ - -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.m -text "m" -variable $variable -value 2 \ - -relief groove -width 2 -command "update_active" - radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \ - -relief groove -width 2 -command "update_active" - - option_name $w $mnum $line $text $variable - - global CONFIG_MODULES - if {($CONFIG_MODULES == 0)} then { - $w.x$line.m configure -state disabled - } - pack $w.x$line.n $w.x$line.m $w.x$line.y -side right -fill y -} - -proc bool {w mnum line text variable} { - toggle_switch2 $w $mnum $line $text $variable -# $w.x$line.m configure -state disabled - pack $w.x$line -anchor w -fill both -expand on -} - -proc tristate {w mnum line text variable } { - toggle_switch3 $w $mnum $line $text $variable - pack $w.x$line -anchor w -fill both -expand on -} - -proc dep_tristate {w mnum line text variable } { - tristate $w $mnum $line $text $variable -} - -proc dep_bool {w mnum line text variable } { - bool $w $mnum $line $text $variable -} - -proc int { w mnum line text variable } { - frame $w.x$line - entry $w.x$line.x -width 11 -relief sunken -borderwidth 2 \ - -textvariable $variable - option_name $w $mnum $line $text $variable - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc hex { w mnum line text variable } { - int $w $mnum $line $text $variable -} - -proc istring { w mnum line text variable } { - frame $w.x$line - entry $w.x$line.x -width 18 -relief sunken -borderwidth 2 \ - -textvariable $variable - option_name $w $mnum $line $text $variable - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc minimenu { w mnum line text variable helpidx } { - frame $w.x$line - menubutton $w.x$line.x -textvariable $variable -menu \ - $w.x$line.x.menu -relief raised \ - -anchor w - option_name $w $mnum $line $text $helpidx - pack $w.x$line.x -anchor w -side right -fill y - pack $w.x$line -anchor w -fill both -expand on -} - -proc menusplit {w m n} { - if { $n > 2 } then { - update idletasks - set menuoptsize [expr [$m yposition 2] - [$m yposition 1]] - set maxsize [winfo screenheight $w] - set splitpoint [expr $maxsize * 4 / 5 / $menuoptsize - 1] - for {set i [expr $splitpoint + 1]} {$i <= $n} {incr i $splitpoint} { - $m entryconfigure $i -columnbreak 1 - } - } -} - -proc menutitle {text menu w} { - wm title $w "$text" -} - -proc submenu { w mnum line text subnum } { - frame $w.x$line - button $w.x$line.l -text "" -width 9 -relief groove - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] -state disabled - button $w.x$line.m -text "$text" -relief raised -anchor w \ - -command "catch {destroy .menu$subnum}; menu$subnum .menu$subnum \"$text\"" - pack $w.x$line.l -side left -fill both - pack $w.x$line.m -anchor w -side right -fill both -expand on - pack $w.x$line -anchor w -fill both -expand on -} - -proc comment {w mnum line text } { - frame $w.x$line - button $w.x$line.l -text "" -width 15 -relief groove - $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ - -activeback [cget $w.x$line.l -bg] -state disabled - button $w.x$line.m -text "$text" -relief groove -anchor w - $w.x$line.m configure -activefore [cget $w.x$line.m -fg] \ - -activeback [cget $w.x$line.m -bg] - pack $w.x$line.l -side left -fill both - pack $w.x$line.m -anchor w -side right -fill both -expand on - pack $w.x$line -anchor w -fill both -expand on -} - -proc readhelp {tag fn} { - set message "" - set b 0 - if { [file readable $fn] == 1} then { - set fhandle [open $fn r] - while {[gets $fhandle inline] >= 0} { - if { $b == 0 } { - if { [regexp $tag $inline ] } { - set b 1 - set message "$inline:\n" - } - } else { - if { [regexp {^[^ \t]} $inline]} { - break - } - set message "$message\n$inline" - } - } - close $fhandle - } - return $message -} - -proc dohelp {w var parent} { - catch {destroy $w} - toplevel $w -class Dialog - - set filefound 0 - set found 0 - set lineno 0 - - if { [file readable config.help] == 1} then { - set filefound 1 - # First escape sed regexp special characters in var: - set var [exec echo "$var" | sed s/\[\]\[\/.^$*\]/\\\\&/g] - # Now pick out right help text: - set message [readhelp $var config.help] - set found [expr [string length "$message"] > 0] - } - - frame $w.f1 - pack $w.f1 -fill both -expand on - - # Do the OK button - # - set oldFocus [focus] - frame $w.f2 - button $w.f2.ok -text "OK" \ - -width 10 -command "destroy $w; catch {focus $oldFocus}" - pack $w.f2.ok -side bottom -pady 6 -anchor n - pack $w.f2 -side bottom -padx 10 -anchor s - - scrollbar $w.f1.vscroll -command "$w.f1.canvas yview" - pack $w.f1.vscroll -side right -fill y - - canvas $w.f1.canvas -relief flat -borderwidth 0 \ - -yscrollcommand "$w.f1.vscroll set" - frame $w.f1.f - pack $w.f1.canvas -side right -fill y -expand on - - if { $found == 0 } then { - if { $filefound == 0 } then { - message $w.f1.f.m -width 750 -aspect 300 -relief flat -text \ - "No help available - unable to open file config.help." - } else { - message $w.f1.f.m -width 400 -aspect 300 -relief flat -text \ - "No help available for $var" - } - label $w.f1.bm -bitmap error - wm title $w "RTFM" - } else { - text $w.f1.f.m -width 73 -relief flat -wrap word - $w.f1.f.m insert 0.0 $message - $w.f1.f.m conf -state disabled -height [$w.f1.f.m index end] - - label $w.f1.bm -bitmap info - wm title $w "Configuration help" - } - pack $w.f1.f.m -side left - pack $w.f1.bm $w.f1.f -side left -padx 10 - - focus $w - set winx [expr [winfo x $parent]+20] - set winy [expr [winfo y $parent]+20] - wm geometry $w +$winx+$winy - set sizok [expr [winfo reqheight $w.f2.ok] + 12] - set maxy [expr [winfo screenheight .] * 3 / 4] - set canvtotal [winfo reqheight $w.f1.f.m] - if [expr $sizok + $canvtotal < $maxy] { - set sizy $canvtotal - } else { - set sizy [expr $maxy - $sizok] - } - $w.f1.canvas configure -height $sizy -width [winfo reqwidth $w.f1.f.m] \ - -scrollregion "0 0 [winfo reqwidth $w.f1.f.m] \ - [winfo reqheight $w.f1.f.m]" - $w.f1.canvas create window 0 0 -anchor nw -window $w.f1.f - update idletasks - - set maxy [winfo screenheight .] - if [expr $sizok + $canvtotal < $maxy] { - set sizy [expr $sizok + $canvtotal] - } else { - set sizy $maxy - } - wm maxsize $w [winfo width $w] $sizy -} - -bind all { catch {exec cp -f .config .config.old}; \ - writeconfig .config config.h; wrapup .wrap } - -proc wrapup {w } { - catch {destroy $w} - toplevel $w -class Dialog - - global CONFIG_MODVERSIONS; vfix CONFIG_MODVERSIONS - message $w.m -width 460 -aspect 300 -relief raised -text \ - "End of design configuration. " - label $w.bm -bitmap info - pack $w.bm $w.m -pady 10 -side top -padx 10 - wm title $w "LEON build instructions" - - set oldFocus [focus] - frame $w.f - button $w.f.back -text "OK" \ - -width 10 -command "exit 2" - pack $w.f.back -side bottom -pady 10 -anchor s - pack $w.f -pady 10 -side top -padx 10 -anchor s - focus $w - bind $w "exit 2" - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - wm geometry $w +$winx+$winy - -} - -proc unregister_active {num} { - global active_menus - set index [lsearch -exact $active_menus $num] - if {$index != -1} then {set active_menus [lreplace $active_menus $index $index]} -} - -proc update_active {} { - global active_menus total_menus - set max 0 - if {[llength $active_menus] > 0} then { - set max [lindex $active_menus end] - update_define [toplevel_menu [lindex $active_menus 0]] $max 0 - } - foreach i $active_menus { - if {[winfo exists .menu$i] == 0} then { - unregister_active $i - } else { - update_menu$i - } - } - update_define [expr $max + 1] $total_menus 1 - update_mainmenu -} - -proc configure_entry {w option items} { - foreach i $items { - $w.$i configure -state $option - } -} - -proc validate_int {name val default} { - if {([exec echo $val | sed s/^-//g | tr -d \[:digit:\] ] != "")} then { - global $name; set $name $default - } -} - -proc validate_hex {name val default} { - if {([exec echo $val | tr -d \[:xdigit:\] ] != "")} then { - global $name; set $name $default - } -} - -proc update_define {first last allow_update} { - for {set i $first} {$i <= $last} {incr i} { - update_define_menu$i - if {$allow_update == 1} then update - } -} - -# -# Next set up the particulars for the top level menu, and define a few -# buttons which we will stick down at the bottom. -# - -frame .f0 -frame .f0.left -frame .f0.middle -frame .f0.right - -set active_menus [list] -set processed_top_level 0 -set ARCH sparc -set menus_per_column 4 -set total_menus 24 - -proc toplevel_menu {num} { - if {$num == 4} then {return 3} - if {$num == 5} then {return 3} - if {$num == 6} then {return 3} - if {$num == 7} then {return 3} - if {$num == 8} then {return 3} - if {$num == 9} then {return 3} - if {$num == 10} then {return 3} - if {$num == 14} then {return 13} - if {$num == 15} then {return 14} - if {$num == 16} then {return 14} - if {$num == 17} then {return 14} - if {$num == 18} then {return 13} - if {$num == 19} then {return 13} - if {$num == 20} then {return 13} - if {$num == 21} then {return 13} - if {$num == 22} then {return 13} - if {$num == 23} then {return 13} - return $num -} - -mainmenu_name "LEON3MP Design Configuration" -menu_option menu1 1 "Synthesis " -proc menu1 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 1} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 1]] - message $w.m -width 400 -aspect 300 -text \ - "Synthesis " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Synthesis " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 1; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu2 .menu2 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu0 .menu0 \"$title\"" - $w.f.prev configure -state disabled - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - global tmpvar_0 - minimenu $w.config.f 1 0 "Target technology " tmpvar_0 CONFIG_SYN_INFERRED - menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Target technology \"" - $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_0 -value "Inferred" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-Stratix" -variable tmpvar_0 -value "Altera-Stratix" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixII" -variable tmpvar_0 -value "Altera-StratixII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixIII" -variable tmpvar_0 -value "Altera-StratixIII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-CycloneIII" -variable tmpvar_0 -value "Altera-CycloneIII" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-Others" -variable tmpvar_0 -value "Altera-Others" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator" -variable tmpvar_0 -value "Actel-Axcelerator" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic" -variable tmpvar_0 -value "Actel-Proasic" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-ProasicPlus" -variable tmpvar_0 -value "Actel-ProasicPlus" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic3" -variable tmpvar_0 -value "Actel-Proasic3" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT025CRH" -variable tmpvar_0 -value "Aeroflex-UT025CRH" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18" -variable tmpvar_0 -value "Atmel-ATC18" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18RHA" -variable tmpvar_0 -value "Atmel-ATC18RHA" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Custom1" -variable tmpvar_0 -value "Custom1" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "eASIC90" -variable tmpvar_0 -value "eASIC90" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "IHP25" -variable tmpvar_0 -value "IHP25" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "IHP25RH" -variable tmpvar_0 -value "IHP25RH" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Lattice-EC/ECP/XP" -variable tmpvar_0 -value "Lattice-EC/ECP/XP" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Quicklogic-Eclipse" -variable tmpvar_0 -value "Quicklogic-Eclipse" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Peregrine" -variable tmpvar_0 -value "Peregrine" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T" -variable tmpvar_0 -value "RH-LIB18T" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_0 -value "RH-UMC" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "SMIC130" -variable tmpvar_0 -value "SMIC130" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan2" -variable tmpvar_0 -value "Xilinx-Spartan2" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3" -variable tmpvar_0 -value "Xilinx-Spartan3" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3E" -variable tmpvar_0 -value "Xilinx-Spartan3E" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex" -variable tmpvar_0 -value "Xilinx-Virtex" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-VirtexE" -variable tmpvar_0 -value "Xilinx-VirtexE" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex2" -variable tmpvar_0 -value "Xilinx-Virtex2" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex4" -variable tmpvar_0 -value "Xilinx-Virtex4" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex5" -variable tmpvar_0 -value "Xilinx-Virtex5" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "UMC180" -variable tmpvar_0 -value "UMC180" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "TSMC90" -variable tmpvar_0 -value "TSMC90" -command "update_active" - menusplit $w $w.config.f.x0.x.menu 33 - global tmpvar_1 - minimenu $w.config.f 1 1 "Memory Library " tmpvar_1 CONFIG_MEM_INFERRED - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Memory Library \"" - $w.config.f.x1.x.menu add radiobutton -label "Inferred" -variable tmpvar_1 -value "Inferred" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "UMC18" -variable tmpvar_1 -value "UMC18" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_1 -value "RH-UMC" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Artisan" -variable tmpvar_1 -value "Artisan" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Custom1" -variable tmpvar_1 -value "Custom1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Virage" -variable tmpvar_1 -value "Virage" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Virage-TSMC90" -variable tmpvar_1 -value "Virage-TSMC90" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 7 - bool $w.config.f 1 2 "Infer RAM" CONFIG_SYN_INFER_RAM - bool $w.config.f 1 3 "Infer pads" CONFIG_SYN_INFER_PADS - bool $w.config.f 1 4 "Disable asynchronous reset" CONFIG_SYN_NO_ASYNC - bool $w.config.f 1 5 "Enable scan support " CONFIG_SYN_SCAN - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu1 {} { - global CONFIG_SYN_INFERRED - global CONFIG_SYN_CUSTOM1 - global CONFIG_SYN_ATC18 - global CONFIG_SYN_TSMC90 - global CONFIG_SYN_UMC - global CONFIG_SYN_RHUMC - global CONFIG_SYN_ARTISAN - if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then {configure_entry .menu1.config.f.x1 normal {x l}} else {configure_entry .menu1.config.f.x1 disabled {x l}} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then { - configure_entry .menu1.config.f.x2 normal {n l y}} else {configure_entry .menu1.config.f.x2 disabled {y n l}} - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then { - configure_entry .menu1.config.f.x3 normal {n l y}} else {configure_entry .menu1.config.f.x3 disabled {y n l}} -} - - -proc update_define_menu1 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_0 - global CONFIG_SYN_INFERRED - if {$tmpvar_0 == "Inferred"} then {set CONFIG_SYN_INFERRED 1} else {set CONFIG_SYN_INFERRED 0} - global CONFIG_SYN_STRATIX - if {$tmpvar_0 == "Altera-Stratix"} then {set CONFIG_SYN_STRATIX 1} else {set CONFIG_SYN_STRATIX 0} - global CONFIG_SYN_STRATIXII - if {$tmpvar_0 == "Altera-StratixII"} then {set CONFIG_SYN_STRATIXII 1} else {set CONFIG_SYN_STRATIXII 0} - global CONFIG_SYN_STRATIXIII - if {$tmpvar_0 == "Altera-StratixIII"} then {set CONFIG_SYN_STRATIXIII 1} else {set CONFIG_SYN_STRATIXIII 0} - global CONFIG_SYN_CYCLONEIII - if {$tmpvar_0 == "Altera-CycloneIII"} then {set CONFIG_SYN_CYCLONEIII 1} else {set CONFIG_SYN_CYCLONEIII 0} - global CONFIG_SYN_ALTERA - if {$tmpvar_0 == "Altera-Others"} then {set CONFIG_SYN_ALTERA 1} else {set CONFIG_SYN_ALTERA 0} - global CONFIG_SYN_AXCEL - if {$tmpvar_0 == "Actel-Axcelerator"} then {set CONFIG_SYN_AXCEL 1} else {set CONFIG_SYN_AXCEL 0} - global CONFIG_SYN_PROASIC - if {$tmpvar_0 == "Actel-Proasic"} then {set CONFIG_SYN_PROASIC 1} else {set CONFIG_SYN_PROASIC 0} - global CONFIG_SYN_PROASICPLUS - if {$tmpvar_0 == "Actel-ProasicPlus"} then {set CONFIG_SYN_PROASICPLUS 1} else {set CONFIG_SYN_PROASICPLUS 0} - global CONFIG_SYN_PROASIC3 - if {$tmpvar_0 == "Actel-Proasic3"} then {set CONFIG_SYN_PROASIC3 1} else {set CONFIG_SYN_PROASIC3 0} - global CONFIG_SYN_UT025CRH - if {$tmpvar_0 == "Aeroflex-UT025CRH"} then {set CONFIG_SYN_UT025CRH 1} else {set CONFIG_SYN_UT025CRH 0} - global CONFIG_SYN_ATC18 - if {$tmpvar_0 == "Atmel-ATC18"} then {set CONFIG_SYN_ATC18 1} else {set CONFIG_SYN_ATC18 0} - global CONFIG_SYN_ATC18RHA - if {$tmpvar_0 == "Atmel-ATC18RHA"} then {set CONFIG_SYN_ATC18RHA 1} else {set CONFIG_SYN_ATC18RHA 0} - global CONFIG_SYN_CUSTOM1 - if {$tmpvar_0 == "Custom1"} then {set CONFIG_SYN_CUSTOM1 1} else {set CONFIG_SYN_CUSTOM1 0} - global CONFIG_SYN_EASIC90 - if {$tmpvar_0 == "eASIC90"} then {set CONFIG_SYN_EASIC90 1} else {set CONFIG_SYN_EASIC90 0} - global CONFIG_SYN_IHP25 - if {$tmpvar_0 == "IHP25"} then {set CONFIG_SYN_IHP25 1} else {set CONFIG_SYN_IHP25 0} - global CONFIG_SYN_IHP25RH - if {$tmpvar_0 == "IHP25RH"} then {set CONFIG_SYN_IHP25RH 1} else {set CONFIG_SYN_IHP25RH 0} - global CONFIG_SYN_LATTICE - if {$tmpvar_0 == "Lattice-EC/ECP/XP"} then {set CONFIG_SYN_LATTICE 1} else {set CONFIG_SYN_LATTICE 0} - global CONFIG_SYN_ECLIPSE - if {$tmpvar_0 == "Quicklogic-Eclipse"} then {set CONFIG_SYN_ECLIPSE 1} else {set CONFIG_SYN_ECLIPSE 0} - global CONFIG_SYN_PEREGRINE - if {$tmpvar_0 == "Peregrine"} then {set CONFIG_SYN_PEREGRINE 1} else {set CONFIG_SYN_PEREGRINE 0} - global CONFIG_SYN_RH_LIB18T - if {$tmpvar_0 == "RH-LIB18T"} then {set CONFIG_SYN_RH_LIB18T 1} else {set CONFIG_SYN_RH_LIB18T 0} - global CONFIG_SYN_RHUMC - if {$tmpvar_0 == "RH-UMC"} then {set CONFIG_SYN_RHUMC 1} else {set CONFIG_SYN_RHUMC 0} - global CONFIG_SYN_SMIC13 - if {$tmpvar_0 == "SMIC130"} then {set CONFIG_SYN_SMIC13 1} else {set CONFIG_SYN_SMIC13 0} - global CONFIG_SYN_SPARTAN2 - if {$tmpvar_0 == "Xilinx-Spartan2"} then {set CONFIG_SYN_SPARTAN2 1} else {set CONFIG_SYN_SPARTAN2 0} - global CONFIG_SYN_SPARTAN3 - if {$tmpvar_0 == "Xilinx-Spartan3"} then {set CONFIG_SYN_SPARTAN3 1} else {set CONFIG_SYN_SPARTAN3 0} - global CONFIG_SYN_SPARTAN3E - if {$tmpvar_0 == "Xilinx-Spartan3E"} then {set CONFIG_SYN_SPARTAN3E 1} else {set CONFIG_SYN_SPARTAN3E 0} - global CONFIG_SYN_VIRTEX - if {$tmpvar_0 == "Xilinx-Virtex"} then {set CONFIG_SYN_VIRTEX 1} else {set CONFIG_SYN_VIRTEX 0} - global CONFIG_SYN_VIRTEXE - if {$tmpvar_0 == "Xilinx-VirtexE"} then {set CONFIG_SYN_VIRTEXE 1} else {set CONFIG_SYN_VIRTEXE 0} - global CONFIG_SYN_VIRTEX2 - if {$tmpvar_0 == "Xilinx-Virtex2"} then {set CONFIG_SYN_VIRTEX2 1} else {set CONFIG_SYN_VIRTEX2 0} - global CONFIG_SYN_VIRTEX4 - if {$tmpvar_0 == "Xilinx-Virtex4"} then {set CONFIG_SYN_VIRTEX4 1} else {set CONFIG_SYN_VIRTEX4 0} - global CONFIG_SYN_VIRTEX5 - if {$tmpvar_0 == "Xilinx-Virtex5"} then {set CONFIG_SYN_VIRTEX5 1} else {set CONFIG_SYN_VIRTEX5 0} - global CONFIG_SYN_UMC - if {$tmpvar_0 == "UMC180"} then {set CONFIG_SYN_UMC 1} else {set CONFIG_SYN_UMC 0} - global CONFIG_SYN_TSMC90 - if {$tmpvar_0 == "TSMC90"} then {set CONFIG_SYN_TSMC90 1} else {set CONFIG_SYN_TSMC90 0} - global tmpvar_1 - global CONFIG_MEM_INFERRED - if {$tmpvar_1 == "Inferred"} then {set CONFIG_MEM_INFERRED 1} else {set CONFIG_MEM_INFERRED 0} - global CONFIG_MEM_UMC - if {$tmpvar_1 == "UMC18"} then {set CONFIG_MEM_UMC 1} else {set CONFIG_MEM_UMC 0} - global CONFIG_MEM_RHUMC - if {$tmpvar_1 == "RH-UMC"} then {set CONFIG_MEM_RHUMC 1} else {set CONFIG_MEM_RHUMC 0} - global CONFIG_MEM_ARTISAN - if {$tmpvar_1 == "Artisan"} then {set CONFIG_MEM_ARTISAN 1} else {set CONFIG_MEM_ARTISAN 0} - global CONFIG_MEM_CUSTOM1 - if {$tmpvar_1 == "Custom1"} then {set CONFIG_MEM_CUSTOM1 1} else {set CONFIG_MEM_CUSTOM1 0} - global CONFIG_MEM_VIRAGE - if {$tmpvar_1 == "Virage"} then {set CONFIG_MEM_VIRAGE 1} else {set CONFIG_MEM_VIRAGE 0} - global CONFIG_MEM_VIRAGE90 - if {$tmpvar_1 == "Virage-TSMC90"} then {set CONFIG_MEM_VIRAGE90 1} else {set CONFIG_MEM_VIRAGE90 0} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then { - set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM&15]} else {set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM|16]} - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then { - set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS&15]} else {set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS|16]} -} - - -menu_option menu2 2 "Clock generation" -proc menu2 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 2} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 2]] - message $w.m -width 400 -aspect 300 -text \ - "Clock generation" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Clock generation" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 2; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu3 .menu3 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - global tmpvar_2 - minimenu $w.config.f 2 0 "Clock generator " tmpvar_2 CONFIG_CLK_INFERRED - menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Clock generator \"" - $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_2 -value "Inferred" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Actel-HCLKBUF" -variable tmpvar_2 -value "Actel-HCLKBUF" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Altera-ALTPLL" -variable tmpvar_2 -value "Altera-ALTPLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Lattice-EXPLL" -variable tmpvar_2 -value "Lattice-EXPLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Proasic3-PLLL" -variable tmpvar_2 -value "Proasic3-PLLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T-PLL" -variable tmpvar_2 -value "RH-LIB18T-PLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "DARE-PLL" -variable tmpvar_2 -value "DARE-PLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-CLKDLL" -variable tmpvar_2 -value "Xilinx-CLKDLL" -command "update_active" - $w.config.f.x0.x.menu add radiobutton -label "Xilinx-DCM" -variable tmpvar_2 -value "Xilinx-DCM" -command "update_active" - menusplit $w $w.config.f.x0.x.menu 9 - int $w.config.f 2 1 "Clock multiplication factor (2 - 32)" CONFIG_CLK_MUL - int $w.config.f 2 2 "Clock division factor (2 - 32)" CONFIG_CLK_DIV - int $w.config.f 2 3 "Outout division factor (2 - 32)" CONFIG_OCLK_DIV - bool $w.config.f 2 4 "Enable Xilinx CLKDLL for PCI clock" CONFIG_PCI_CLKDLL - bool $w.config.f 2 5 "Disable external feedback for SDRAM clock" CONFIG_CLK_NOFB - bool $w.config.f 2 6 "Use PCI clock as system clock" CONFIG_PCI_SYSCLK - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu2 {} { - global CONFIG_CLK_DCM - global CONFIG_CLK_ALTDLL - global CONFIG_CLK_LATDLL - global CONFIG_CLK_PRO3PLL - global CONFIG_CLK_CLKDLL - global CONFIG_CLK_LIB18T - global CONFIG_CLK_MUL - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x1.l configure -state normal; } else {.menu2.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x1.l configure -state disabled} - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {.menu2.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x2.l configure -state normal; } else {.menu2.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x2.l configure -state disabled} - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {.menu2.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x3.l configure -state normal; } else {.menu2.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x3.l configure -state disabled} - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then { - configure_entry .menu2.config.f.x4 normal {n l y}} else {configure_entry .menu2.config.f.x4 disabled {y n l}} - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then { - configure_entry .menu2.config.f.x5 normal {n l y}} else {configure_entry .menu2.config.f.x5 disabled {y n l}} - global CONFIG_PCI_ENABLE - global CONFIG_PCI_SYSCLK - if {($CONFIG_PCI_ENABLE != 1)} then { - configure_entry .menu2.config.f.x6 normal {n l y}} else {configure_entry .menu2.config.f.x6 disabled {y n l}} -} - - -proc update_define_menu2 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_2 - global CONFIG_CLK_INFERRED - if {$tmpvar_2 == "Inferred"} then {set CONFIG_CLK_INFERRED 1} else {set CONFIG_CLK_INFERRED 0} - global CONFIG_CLK_HCLKBUF - if {$tmpvar_2 == "Actel-HCLKBUF"} then {set CONFIG_CLK_HCLKBUF 1} else {set CONFIG_CLK_HCLKBUF 0} - global CONFIG_CLK_ALTDLL - if {$tmpvar_2 == "Altera-ALTPLL"} then {set CONFIG_CLK_ALTDLL 1} else {set CONFIG_CLK_ALTDLL 0} - global CONFIG_CLK_LATDLL - if {$tmpvar_2 == "Lattice-EXPLL"} then {set CONFIG_CLK_LATDLL 1} else {set CONFIG_CLK_LATDLL 0} - global CONFIG_CLK_PRO3PLL - if {$tmpvar_2 == "Proasic3-PLLL"} then {set CONFIG_CLK_PRO3PLL 1} else {set CONFIG_CLK_PRO3PLL 0} - global CONFIG_CLK_LIB18T - if {$tmpvar_2 == "RH-LIB18T-PLL"} then {set CONFIG_CLK_LIB18T 1} else {set CONFIG_CLK_LIB18T 0} - global CONFIG_CLK_RHUMC - if {$tmpvar_2 == "DARE-PLL"} then {set CONFIG_CLK_RHUMC 1} else {set CONFIG_CLK_RHUMC 0} - global CONFIG_CLK_CLKDLL - if {$tmpvar_2 == "Xilinx-CLKDLL"} then {set CONFIG_CLK_CLKDLL 1} else {set CONFIG_CLK_CLKDLL 0} - global CONFIG_CLK_DCM - if {$tmpvar_2 == "Xilinx-DCM"} then {set CONFIG_CLK_DCM 1} else {set CONFIG_CLK_DCM 0} - global CONFIG_CLK_MUL - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_MUL "$CONFIG_CLK_MUL" 2} - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {validate_int CONFIG_CLK_DIV "$CONFIG_CLK_DIV" 2} - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {validate_int CONFIG_OCLK_DIV "$CONFIG_OCLK_DIV" 2} - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then { - set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL&15]} else {set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL|16]} - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then { - set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB&15]} else {set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB|16]} - global CONFIG_PCI_ENABLE - global CONFIG_PCI_SYSCLK - if {($CONFIG_PCI_ENABLE != 1)} then { - set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK&15]} else {set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK|16]} -} - - -menu_option menu3 3 "Processor " -proc menu3 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 3} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 3]] - message $w.m -width 400 -aspect 300 -text \ - "Processor " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Processor " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 3; break" - set nextscript "catch {focus $oldFocus}; menu4 .menu4 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 3 0 "Enable LEON3 SPARC V8 Processor" CONFIG_LEON3 - int $w.config.f 3 1 "Number of processors" CONFIG_PROC_NUM - submenu $w.config.f 3 2 "Integer unit " 4 - submenu $w.config.f 3 3 "Floating-point unit" 5 - submenu $w.config.f 3 4 "Cache system" 6 - submenu $w.config.f 3 5 "MMU" 7 - submenu $w.config.f 3 6 "Debug Support Unit " 8 - submenu $w.config.f 3 7 "Fault-tolerance " 9 - submenu $w.config.f 3 8 "VHDL debug settings " 10 - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu3 {} { - global CONFIG_LEON3 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {.menu3.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu3.config.f.x1.l configure -state normal; } else {.menu3.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu3.config.f.x1.l configure -state disabled} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x2 normal {m}} else {configure_entry .menu3.config.f.x2 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x3 normal {m}} else {configure_entry .menu3.config.f.x3 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x4 normal {m}} else {configure_entry .menu3.config.f.x4 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x5 normal {m}} else {configure_entry .menu3.config.f.x5 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x6 normal {m}} else {configure_entry .menu3.config.f.x6 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x7 normal {m}} else {configure_entry .menu3.config.f.x7 disabled {m}} - if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x8 normal {m}} else {configure_entry .menu3.config.f.x8 disabled {m}} -} - - -proc update_define_menu3 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_PROC_NUM "$CONFIG_PROC_NUM" 1} -} - - -proc menu4 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 4} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 4]] - message $w.m -width 400 -aspect 300 -text \ - "Integer unit " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Integer unit " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 4; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu5 .menu5 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - int $w.config.f 4 0 "SPARC register windows" CONFIG_IU_NWINDOWS - bool $w.config.f 4 1 "SPARC V8 MUL/DIV instructions" CONFIG_IU_V8MULDIV - global tmpvar_3 - minimenu $w.config.f 4 2 "Hardware multiplier latency" tmpvar_3 CONFIG_IU_MUL_LATENCY_2 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Hardware multiplier latency\"" - $w.config.f.x2.x.menu add radiobutton -label "2-cycles" -variable tmpvar_3 -value "2-cycles" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4-cycles" -variable tmpvar_3 -value "4-cycles" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "5-cycles" -variable tmpvar_3 -value "5-cycles" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 3 - bool $w.config.f 4 3 "SPARC V8e SMAC/UMAC instructions " CONFIG_IU_MUL_MAC - bool $w.config.f 4 4 "Single-vector trapping" CONFIG_IU_SVT - int $w.config.f 4 5 "Load delay" CONFIG_IU_LDELAY - int $w.config.f 4 6 "Hardware watchpoints" CONFIG_IU_WATCHPOINTS - bool $w.config.f 4 7 "Enable power-down mode " CONFIG_PWD - hex $w.config.f 4 8 " Reset start address (addr\[31:12\]) " CONFIG_IU_RSTADDR - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu4 {} { - global CONFIG_LEON3 - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x0.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x0.l configure -state normal; } else {.menu4.config.f.x0.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x0.l configure -state disabled} - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x1 normal {n l y}} else {configure_entry .menu4.config.f.x1 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {configure_entry .menu4.config.f.x2 normal {x l}} else {configure_entry .menu4.config.f.x2 disabled {x l}} - global CONFIG_IU_MUL_LATENCY_4 - global CONFIG_IU_MUL_LATENCY_5 - global CONFIG_IU_MUL_MAC - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then { - configure_entry .menu4.config.f.x3 normal {n l y}} else {configure_entry .menu4.config.f.x3 disabled {y n l}} - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x4 normal {n l y}} else {configure_entry .menu4.config.f.x4 disabled {y n l}} - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x5.l configure -state normal; } else {.menu4.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x5.l configure -state disabled} - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x6.l configure -state normal; } else {.menu4.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x6.l configure -state disabled} - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu4.config.f.x7 normal {n l y}} else {configure_entry .menu4.config.f.x7 disabled {y n l}} - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {.menu4.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x8.l configure -state normal; } else {.menu4.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x8.l configure -state disabled} -} - - -proc update_define_menu4 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_NWINDOWS "$CONFIG_IU_NWINDOWS" 8} - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV&15]} else {set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV|16]} - global tmpvar_3 - global CONFIG_IU_MUL_LATENCY_2 - if {$tmpvar_3 == "2-cycles"} then {set CONFIG_IU_MUL_LATENCY_2 1} else {set CONFIG_IU_MUL_LATENCY_2 0} - global CONFIG_IU_MUL_LATENCY_4 - if {$tmpvar_3 == "4-cycles"} then {set CONFIG_IU_MUL_LATENCY_4 1} else {set CONFIG_IU_MUL_LATENCY_4 0} - global CONFIG_IU_MUL_LATENCY_5 - if {$tmpvar_3 == "5-cycles"} then {set CONFIG_IU_MUL_LATENCY_5 1} else {set CONFIG_IU_MUL_LATENCY_5 0} - global CONFIG_IU_MUL_MAC - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then { - set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC&15]} else {set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC|16]} - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_SVT [expr $CONFIG_IU_SVT&15]} else {set CONFIG_IU_SVT [expr $CONFIG_IU_SVT|16]} - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_LDELAY "$CONFIG_IU_LDELAY" 1} - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_IU_WATCHPOINTS "$CONFIG_IU_WATCHPOINTS" 0} - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_PWD [expr $CONFIG_PWD&15]} else {set CONFIG_PWD [expr $CONFIG_PWD|16]} - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {validate_hex CONFIG_IU_RSTADDR "$CONFIG_IU_RSTADDR" 00000} -} - - -proc menu5 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 5} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 5]] - message $w.m -width 400 -aspect 300 -text \ - "Floating-point unit" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Floating-point unit" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 5; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu6 .menu6 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 5 0 "Enable FPU " CONFIG_FPU_ENABLE - global tmpvar_4 - minimenu $w.config.f 5 1 "FPU core" tmpvar_4 CONFIG_FPU_GRFPU - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"FPU core\"" - $w.config.f.x1.x.menu add radiobutton -label "GRFPU" -variable tmpvar_4 -value "GRFPU" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "GRFPU-LITE" -variable tmpvar_4 -value "GRFPU-LITE" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "Meiko" -variable tmpvar_4 -value "Meiko" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 3 - global tmpvar_5 - minimenu $w.config.f 5 2 "GRFPU multiplier" tmpvar_5 CONFIG_FPU_GRFPU_INFMUL - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"GRFPU multiplier\"" - $w.config.f.x2.x.menu add radiobutton -label "Inferred" -variable tmpvar_5 -value "Inferred" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "DW" -variable tmpvar_5 -value "DW" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "ModGen" -variable tmpvar_5 -value "ModGen" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 3 - global tmpvar_6 - minimenu $w.config.f 5 3 "GRFPU-LITE controller" tmpvar_6 CONFIG_FPU_GRFPC0 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"GRFPU-LITE controller\"" - $w.config.f.x3.x.menu add radiobutton -label "Simple" -variable tmpvar_6 -value "Simple" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "Data-forwarding" -variable tmpvar_6 -value "Data-forwarding" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "Non-blocking" -variable tmpvar_6 -value "Non-blocking" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 3 - bool $w.config.f 5 4 "Use VHDL netlist " CONFIG_FPU_NETLIST - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu5 {} { - global CONFIG_LEON3 - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu5.config.f.x0 normal {n l y}} else {configure_entry .menu5.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {configure_entry .menu5.config.f.x1 normal {x l}} else {configure_entry .menu5.config.f.x1 disabled {x l}} - global CONFIG_FPU_GRFPU - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then {configure_entry .menu5.config.f.x2 normal {x l}} else {configure_entry .menu5.config.f.x2 disabled {x l}} - global CONFIG_FPU_GRFPULITE - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then {configure_entry .menu5.config.f.x3 normal {x l}} else {configure_entry .menu5.config.f.x3 disabled {x l}} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - configure_entry .menu5.config.f.x4 normal {n l y}} else {configure_entry .menu5.config.f.x4 disabled {y n l}} -} - - -proc update_define_menu5 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE&15]} else {set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE|16]} - global tmpvar_4 - global CONFIG_FPU_GRFPU - if {$tmpvar_4 == "GRFPU"} then {set CONFIG_FPU_GRFPU 1} else {set CONFIG_FPU_GRFPU 0} - global CONFIG_FPU_GRFPULITE - if {$tmpvar_4 == "GRFPU-LITE"} then {set CONFIG_FPU_GRFPULITE 1} else {set CONFIG_FPU_GRFPULITE 0} - global CONFIG_FPU_MEIKO - if {$tmpvar_4 == "Meiko"} then {set CONFIG_FPU_MEIKO 1} else {set CONFIG_FPU_MEIKO 0} - global tmpvar_5 - global CONFIG_FPU_GRFPU_INFMUL - if {$tmpvar_5 == "Inferred"} then {set CONFIG_FPU_GRFPU_INFMUL 1} else {set CONFIG_FPU_GRFPU_INFMUL 0} - global CONFIG_FPU_GRFPU_DWMUL - if {$tmpvar_5 == "DW"} then {set CONFIG_FPU_GRFPU_DWMUL 1} else {set CONFIG_FPU_GRFPU_DWMUL 0} - global CONFIG_FPU_GRFPU_MODGEN - if {$tmpvar_5 == "ModGen"} then {set CONFIG_FPU_GRFPU_MODGEN 1} else {set CONFIG_FPU_GRFPU_MODGEN 0} - global tmpvar_6 - global CONFIG_FPU_GRFPC0 - if {$tmpvar_6 == "Simple"} then {set CONFIG_FPU_GRFPC0 1} else {set CONFIG_FPU_GRFPC0 0} - global CONFIG_FPU_GRFPC1 - if {$tmpvar_6 == "Data-forwarding"} then {set CONFIG_FPU_GRFPC1 1} else {set CONFIG_FPU_GRFPC1 0} - global CONFIG_FPU_GRFPC2 - if {$tmpvar_6 == "Non-blocking"} then {set CONFIG_FPU_GRFPC2 1} else {set CONFIG_FPU_GRFPC2 0} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST&15]} else {set CONFIG_FPU_NETLIST [expr $CONFIG_FPU_NETLIST|16]} -} - - -proc menu6 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 6} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 6]] - message $w.m -width 400 -aspect 300 -text \ - "Cache system" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Cache system" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 6; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu7 .menu7 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 6 0 "Enable instruction cache " CONFIG_ICACHE_ENABLE - global tmpvar_7 - minimenu $w.config.f 6 1 "Associativity (sets) " tmpvar_7 CONFIG_ICACHE_ASSO1 - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Associativity (sets) \"" - $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_7 -value "1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_7 -value "2" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "3" -variable tmpvar_7 -value "3" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_7 -value "4" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 4 - global tmpvar_8 - minimenu $w.config.f 6 2 "Set size (kbytes/set)" tmpvar_8 CONFIG_ICACHE_SZ1 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\"" - $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_8 -value "1" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_8 -value "2" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_8 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_8 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_8 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_8 -value "32" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_8 -value "64" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "128" -variable tmpvar_8 -value "128" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "256" -variable tmpvar_8 -value "256" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 9 - global tmpvar_9 - minimenu $w.config.f 6 3 "Line size (bytes/line)" tmpvar_9 CONFIG_ICACHE_LZ16 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\"" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_9 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_9 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 2 - global tmpvar_10 - minimenu $w.config.f 6 4 "Replacement alorithm" tmpvar_10 CONFIG_ICACHE_ALGORND - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Replacement alorithm\"" - $w.config.f.x4.x.menu add radiobutton -label "Random" -variable tmpvar_10 -value "Random" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "LRR" -variable tmpvar_10 -value "LRR" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "LRU" -variable tmpvar_10 -value "LRU" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 3 - bool $w.config.f 6 5 "Cache locking " CONFIG_ICACHE_LOCK - bool $w.config.f 6 6 "Enable local instruction RAM " CONFIG_ICACHE_LRAM - global tmpvar_11 - minimenu $w.config.f 6 7 "Local data RAM size (kbytes)" tmpvar_11 CONFIG_ICACHE_LRAM_SZ1 - menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x7.x.menu add radiobutton -label "1" -variable tmpvar_11 -value "1" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "2" -variable tmpvar_11 -value "2" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "4" -variable tmpvar_11 -value "4" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_11 -value "8" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_11 -value "16" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_11 -value "32" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_11 -value "64" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_11 -value "128" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_11 -value "256" -command "update_active" - menusplit $w $w.config.f.x7.x.menu 9 - hex $w.config.f 6 8 " Local instruction RAM start address (8 MSB) " CONFIG_ICACHE_LRSTART - bool $w.config.f 6 9 "Enable data cache " CONFIG_DCACHE_ENABLE - global tmpvar_12 - minimenu $w.config.f 6 10 "Associativity (sets)" tmpvar_12 CONFIG_DCACHE_ASSO1 - menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Associativity (sets)\"" - $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_12 -value "1" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_12 -value "2" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "3" -variable tmpvar_12 -value "3" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "4" -variable tmpvar_12 -value "4" -command "update_active" - menusplit $w $w.config.f.x10.x.menu 4 - global tmpvar_13 - minimenu $w.config.f 6 11 "Set size (kbytes/set)" tmpvar_13 CONFIG_DCACHE_SZ1 - menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\"" - $w.config.f.x11.x.menu add radiobutton -label "1" -variable tmpvar_13 -value "1" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "2" -variable tmpvar_13 -value "2" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "4" -variable tmpvar_13 -value "4" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "8" -variable tmpvar_13 -value "8" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "16" -variable tmpvar_13 -value "16" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "32" -variable tmpvar_13 -value "32" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "64" -variable tmpvar_13 -value "64" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "128" -variable tmpvar_13 -value "128" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_13 -value "256" -command "update_active" - menusplit $w $w.config.f.x11.x.menu 9 - global tmpvar_14 - minimenu $w.config.f 6 12 "Line size (bytes/line)" tmpvar_14 CONFIG_DCACHE_LZ16 - menu $w.config.f.x12.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\"" - $w.config.f.x12.x.menu add radiobutton -label "16" -variable tmpvar_14 -value "16" -command "update_active" - $w.config.f.x12.x.menu add radiobutton -label "32" -variable tmpvar_14 -value "32" -command "update_active" - menusplit $w $w.config.f.x12.x.menu 2 - global tmpvar_15 - minimenu $w.config.f 6 13 "Replacement alorithm" tmpvar_15 CONFIG_DCACHE_ALGORND - menu $w.config.f.x13.x.menu -tearoffcommand "menutitle \"Replacement alorithm\"" - $w.config.f.x13.x.menu add radiobutton -label "Random" -variable tmpvar_15 -value "Random" -command "update_active" - $w.config.f.x13.x.menu add radiobutton -label "LRR" -variable tmpvar_15 -value "LRR" -command "update_active" - $w.config.f.x13.x.menu add radiobutton -label "LRU" -variable tmpvar_15 -value "LRU" -command "update_active" - menusplit $w $w.config.f.x13.x.menu 3 - bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK - bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM - global tmpvar_16 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_16 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_16 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_16 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_16 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_16 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_16 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_16 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_16 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_16 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_16 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu6 {} { - global CONFIG_LEON3 - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu6.config.f.x0 normal {n l y}} else {configure_entry .menu6.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x1 normal {x l}} else {configure_entry .menu6.config.f.x1 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x2 normal {x l}} else {configure_entry .menu6.config.f.x2 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x3 normal {x l}} else {configure_entry .menu6.config.f.x3 disabled {x l}} - global CONFIG_ICACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x4 normal {x l}} else {configure_entry .menu6.config.f.x4 disabled {x l}} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - configure_entry .menu6.config.f.x5 normal {n l y}} else {configure_entry .menu6.config.f.x5 disabled {y n l}} - global CONFIG_MMU_ENABLE - global CONFIG_ICACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x6 normal {n l y}} else {configure_entry .menu6.config.f.x6 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x7 normal {x l}} else {configure_entry .menu6.config.f.x7 disabled {x l}} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {.menu6.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x8.l configure -state normal; } else {.menu6.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x8.l configure -state disabled} - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu6.config.f.x9 normal {n l y}} else {configure_entry .menu6.config.f.x9 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x10 normal {x l}} else {configure_entry .menu6.config.f.x10 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x11 normal {x l}} else {configure_entry .menu6.config.f.x11 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x12 normal {x l}} else {configure_entry .menu6.config.f.x12 disabled {x l}} - global CONFIG_DCACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x13 normal {x l}} else {configure_entry .menu6.config.f.x13 disabled {x l}} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - configure_entry .menu6.config.f.x14 normal {n l y}} else {configure_entry .menu6.config.f.x14 disabled {y n l}} - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} -} - - -proc update_define_menu6 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE&15]} else {set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE|16]} - global tmpvar_7 - global CONFIG_ICACHE_ASSO1 - if {$tmpvar_7 == "1"} then {set CONFIG_ICACHE_ASSO1 1} else {set CONFIG_ICACHE_ASSO1 0} - global CONFIG_ICACHE_ASSO2 - if {$tmpvar_7 == "2"} then {set CONFIG_ICACHE_ASSO2 1} else {set CONFIG_ICACHE_ASSO2 0} - global CONFIG_ICACHE_ASSO3 - if {$tmpvar_7 == "3"} then {set CONFIG_ICACHE_ASSO3 1} else {set CONFIG_ICACHE_ASSO3 0} - global CONFIG_ICACHE_ASSO4 - if {$tmpvar_7 == "4"} then {set CONFIG_ICACHE_ASSO4 1} else {set CONFIG_ICACHE_ASSO4 0} - global tmpvar_8 - global CONFIG_ICACHE_SZ1 - if {$tmpvar_8 == "1"} then {set CONFIG_ICACHE_SZ1 1} else {set CONFIG_ICACHE_SZ1 0} - global CONFIG_ICACHE_SZ2 - if {$tmpvar_8 == "2"} then {set CONFIG_ICACHE_SZ2 1} else {set CONFIG_ICACHE_SZ2 0} - global CONFIG_ICACHE_SZ4 - if {$tmpvar_8 == "4"} then {set CONFIG_ICACHE_SZ4 1} else {set CONFIG_ICACHE_SZ4 0} - global CONFIG_ICACHE_SZ8 - if {$tmpvar_8 == "8"} then {set CONFIG_ICACHE_SZ8 1} else {set CONFIG_ICACHE_SZ8 0} - global CONFIG_ICACHE_SZ16 - if {$tmpvar_8 == "16"} then {set CONFIG_ICACHE_SZ16 1} else {set CONFIG_ICACHE_SZ16 0} - global CONFIG_ICACHE_SZ32 - if {$tmpvar_8 == "32"} then {set CONFIG_ICACHE_SZ32 1} else {set CONFIG_ICACHE_SZ32 0} - global CONFIG_ICACHE_SZ64 - if {$tmpvar_8 == "64"} then {set CONFIG_ICACHE_SZ64 1} else {set CONFIG_ICACHE_SZ64 0} - global CONFIG_ICACHE_SZ128 - if {$tmpvar_8 == "128"} then {set CONFIG_ICACHE_SZ128 1} else {set CONFIG_ICACHE_SZ128 0} - global CONFIG_ICACHE_SZ256 - if {$tmpvar_8 == "256"} then {set CONFIG_ICACHE_SZ256 1} else {set CONFIG_ICACHE_SZ256 0} - global tmpvar_9 - global CONFIG_ICACHE_LZ16 - if {$tmpvar_9 == "16"} then {set CONFIG_ICACHE_LZ16 1} else {set CONFIG_ICACHE_LZ16 0} - global CONFIG_ICACHE_LZ32 - if {$tmpvar_9 == "32"} then {set CONFIG_ICACHE_LZ32 1} else {set CONFIG_ICACHE_LZ32 0} - global tmpvar_10 - global CONFIG_ICACHE_ALGORND - if {$tmpvar_10 == "Random"} then {set CONFIG_ICACHE_ALGORND 1} else {set CONFIG_ICACHE_ALGORND 0} - global CONFIG_ICACHE_ALGOLRR - if {$tmpvar_10 == "LRR"} then {set CONFIG_ICACHE_ALGOLRR 1} else {set CONFIG_ICACHE_ALGOLRR 0} - global CONFIG_ICACHE_ALGOLRU - if {$tmpvar_10 == "LRU"} then {set CONFIG_ICACHE_ALGOLRU 1} else {set CONFIG_ICACHE_ALGOLRU 0} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK&15]} else {set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK|16]} - global CONFIG_MMU_ENABLE - global CONFIG_ICACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM&15]} else {set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM|16]} - global tmpvar_11 - global CONFIG_ICACHE_LRAM_SZ1 - if {$tmpvar_11 == "1"} then {set CONFIG_ICACHE_LRAM_SZ1 1} else {set CONFIG_ICACHE_LRAM_SZ1 0} - global CONFIG_ICACHE_LRAM_SZ2 - if {$tmpvar_11 == "2"} then {set CONFIG_ICACHE_LRAM_SZ2 1} else {set CONFIG_ICACHE_LRAM_SZ2 0} - global CONFIG_ICACHE_LRAM_SZ4 - if {$tmpvar_11 == "4"} then {set CONFIG_ICACHE_LRAM_SZ4 1} else {set CONFIG_ICACHE_LRAM_SZ4 0} - global CONFIG_ICACHE_LRAM_SZ8 - if {$tmpvar_11 == "8"} then {set CONFIG_ICACHE_LRAM_SZ8 1} else {set CONFIG_ICACHE_LRAM_SZ8 0} - global CONFIG_ICACHE_LRAM_SZ16 - if {$tmpvar_11 == "16"} then {set CONFIG_ICACHE_LRAM_SZ16 1} else {set CONFIG_ICACHE_LRAM_SZ16 0} - global CONFIG_ICACHE_LRAM_SZ32 - if {$tmpvar_11 == "32"} then {set CONFIG_ICACHE_LRAM_SZ32 1} else {set CONFIG_ICACHE_LRAM_SZ32 0} - global CONFIG_ICACHE_LRAM_SZ64 - if {$tmpvar_11 == "64"} then {set CONFIG_ICACHE_LRAM_SZ64 1} else {set CONFIG_ICACHE_LRAM_SZ64 0} - global CONFIG_ICACHE_LRAM_SZ128 - if {$tmpvar_11 == "128"} then {set CONFIG_ICACHE_LRAM_SZ128 1} else {set CONFIG_ICACHE_LRAM_SZ128 0} - global CONFIG_ICACHE_LRAM_SZ256 - if {$tmpvar_11 == "256"} then {set CONFIG_ICACHE_LRAM_SZ256 1} else {set CONFIG_ICACHE_LRAM_SZ256 0} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {validate_hex CONFIG_ICACHE_LRSTART "$CONFIG_ICACHE_LRSTART" 8e} - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE&15]} else {set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE|16]} - global tmpvar_12 - global CONFIG_DCACHE_ASSO1 - if {$tmpvar_12 == "1"} then {set CONFIG_DCACHE_ASSO1 1} else {set CONFIG_DCACHE_ASSO1 0} - global CONFIG_DCACHE_ASSO2 - if {$tmpvar_12 == "2"} then {set CONFIG_DCACHE_ASSO2 1} else {set CONFIG_DCACHE_ASSO2 0} - global CONFIG_DCACHE_ASSO3 - if {$tmpvar_12 == "3"} then {set CONFIG_DCACHE_ASSO3 1} else {set CONFIG_DCACHE_ASSO3 0} - global CONFIG_DCACHE_ASSO4 - if {$tmpvar_12 == "4"} then {set CONFIG_DCACHE_ASSO4 1} else {set CONFIG_DCACHE_ASSO4 0} - global tmpvar_13 - global CONFIG_DCACHE_SZ1 - if {$tmpvar_13 == "1"} then {set CONFIG_DCACHE_SZ1 1} else {set CONFIG_DCACHE_SZ1 0} - global CONFIG_DCACHE_SZ2 - if {$tmpvar_13 == "2"} then {set CONFIG_DCACHE_SZ2 1} else {set CONFIG_DCACHE_SZ2 0} - global CONFIG_DCACHE_SZ4 - if {$tmpvar_13 == "4"} then {set CONFIG_DCACHE_SZ4 1} else {set CONFIG_DCACHE_SZ4 0} - global CONFIG_DCACHE_SZ8 - if {$tmpvar_13 == "8"} then {set CONFIG_DCACHE_SZ8 1} else {set CONFIG_DCACHE_SZ8 0} - global CONFIG_DCACHE_SZ16 - if {$tmpvar_13 == "16"} then {set CONFIG_DCACHE_SZ16 1} else {set CONFIG_DCACHE_SZ16 0} - global CONFIG_DCACHE_SZ32 - if {$tmpvar_13 == "32"} then {set CONFIG_DCACHE_SZ32 1} else {set CONFIG_DCACHE_SZ32 0} - global CONFIG_DCACHE_SZ64 - if {$tmpvar_13 == "64"} then {set CONFIG_DCACHE_SZ64 1} else {set CONFIG_DCACHE_SZ64 0} - global CONFIG_DCACHE_SZ128 - if {$tmpvar_13 == "128"} then {set CONFIG_DCACHE_SZ128 1} else {set CONFIG_DCACHE_SZ128 0} - global CONFIG_DCACHE_SZ256 - if {$tmpvar_13 == "256"} then {set CONFIG_DCACHE_SZ256 1} else {set CONFIG_DCACHE_SZ256 0} - global tmpvar_14 - global CONFIG_DCACHE_LZ16 - if {$tmpvar_14 == "16"} then {set CONFIG_DCACHE_LZ16 1} else {set CONFIG_DCACHE_LZ16 0} - global CONFIG_DCACHE_LZ32 - if {$tmpvar_14 == "32"} then {set CONFIG_DCACHE_LZ32 1} else {set CONFIG_DCACHE_LZ32 0} - global tmpvar_15 - global CONFIG_DCACHE_ALGORND - if {$tmpvar_15 == "Random"} then {set CONFIG_DCACHE_ALGORND 1} else {set CONFIG_DCACHE_ALGORND 0} - global CONFIG_DCACHE_ALGOLRR - if {$tmpvar_15 == "LRR"} then {set CONFIG_DCACHE_ALGOLRR 1} else {set CONFIG_DCACHE_ALGOLRR 0} - global CONFIG_DCACHE_ALGOLRU - if {$tmpvar_15 == "LRU"} then {set CONFIG_DCACHE_ALGOLRU 1} else {set CONFIG_DCACHE_ALGOLRU 0} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK&15]} else {set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK|16]} - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {validate_hex CONFIG_CACHE_FIXED "$CONFIG_CACHE_FIXED" 0} - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM&15]} else {set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM|16]} - global tmpvar_16 - global CONFIG_DCACHE_LRAM_SZ1 - if {$tmpvar_16 == "1"} then {set CONFIG_DCACHE_LRAM_SZ1 1} else {set CONFIG_DCACHE_LRAM_SZ1 0} - global CONFIG_DCACHE_LRAM_SZ2 - if {$tmpvar_16 == "2"} then {set CONFIG_DCACHE_LRAM_SZ2 1} else {set CONFIG_DCACHE_LRAM_SZ2 0} - global CONFIG_DCACHE_LRAM_SZ4 - if {$tmpvar_16 == "4"} then {set CONFIG_DCACHE_LRAM_SZ4 1} else {set CONFIG_DCACHE_LRAM_SZ4 0} - global CONFIG_DCACHE_LRAM_SZ8 - if {$tmpvar_16 == "8"} then {set CONFIG_DCACHE_LRAM_SZ8 1} else {set CONFIG_DCACHE_LRAM_SZ8 0} - global CONFIG_DCACHE_LRAM_SZ16 - if {$tmpvar_16 == "16"} then {set CONFIG_DCACHE_LRAM_SZ16 1} else {set CONFIG_DCACHE_LRAM_SZ16 0} - global CONFIG_DCACHE_LRAM_SZ32 - if {$tmpvar_16 == "32"} then {set CONFIG_DCACHE_LRAM_SZ32 1} else {set CONFIG_DCACHE_LRAM_SZ32 0} - global CONFIG_DCACHE_LRAM_SZ64 - if {$tmpvar_16 == "64"} then {set CONFIG_DCACHE_LRAM_SZ64 1} else {set CONFIG_DCACHE_LRAM_SZ64 0} - global CONFIG_DCACHE_LRAM_SZ128 - if {$tmpvar_16 == "128"} then {set CONFIG_DCACHE_LRAM_SZ128 1} else {set CONFIG_DCACHE_LRAM_SZ128 0} - global CONFIG_DCACHE_LRAM_SZ256 - if {$tmpvar_16 == "256"} then {set CONFIG_DCACHE_LRAM_SZ256 1} else {set CONFIG_DCACHE_LRAM_SZ256 0} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {validate_hex CONFIG_DCACHE_LRSTART "$CONFIG_DCACHE_LRSTART" 8f} -} - - -proc menu7 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 7} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 7]] - message $w.m -width 400 -aspect 300 -text \ - "MMU" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "MMU" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 7; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu8 .menu8 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 7 0 "Enable MMU " CONFIG_MMU_ENABLE - global tmpvar_17 - minimenu $w.config.f 7 1 "MMU type " tmpvar_17 CONFIG_MMU_COMBINED - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"MMU type \"" - $w.config.f.x1.x.menu add radiobutton -label "combined" -variable tmpvar_17 -value "combined" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "split" -variable tmpvar_17 -value "split" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 2 - global tmpvar_18 - minimenu $w.config.f 7 2 "TLB replacement sheme " tmpvar_18 CONFIG_MMU_REPARRAY - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"TLB replacement sheme \"" - $w.config.f.x2.x.menu add radiobutton -label "LRU" -variable tmpvar_18 -value "LRU" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "Increment" -variable tmpvar_18 -value "Increment" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 2 - global tmpvar_19 - minimenu $w.config.f 7 3 "Instruction (or combined) TLB entries" tmpvar_19 CONFIG_MMU_I2 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Instruction (or combined) TLB entries\"" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 5 - global tmpvar_20 - minimenu $w.config.f 7 4 "Data TLB entries" tmpvar_20 CONFIG_MMU_D2 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Data TLB entries\"" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_20 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_20 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_20 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_20 -value "16" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_20 -value "32" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 5 - bool $w.config.f 7 5 "Fast writebuffer " CONFIG_MMU_FASTWB - global tmpvar_21 - minimenu $w.config.f 7 6 "MMU page size" tmpvar_21 CONFIG_MMU_PAGE_4K - menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"MMU page size\"" - $w.config.f.x6.x.menu add radiobutton -label "4K" -variable tmpvar_21 -value "4K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "8K" -variable tmpvar_21 -value "8K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "16K" -variable tmpvar_21 -value "16K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "32K" -variable tmpvar_21 -value "32K" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "Programmable" -variable tmpvar_21 -value "Programmable" -command "update_active" - menusplit $w $w.config.f.x6.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu7 {} { - global CONFIG_LEON3 - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu7.config.f.x0 normal {n l y}} else {configure_entry .menu7.config.f.x0 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x1 normal {x l}} else {configure_entry .menu7.config.f.x1 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x2 normal {x l}} else {configure_entry .menu7.config.f.x2 disabled {x l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x3 normal {x l}} else {configure_entry .menu7.config.f.x3 disabled {x l}} - global CONFIG_MMU_SPLIT - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {configure_entry .menu7.config.f.x4 normal {x l}} else {configure_entry .menu7.config.f.x4 disabled {x l}} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - configure_entry .menu7.config.f.x5 normal {n l y}} else {configure_entry .menu7.config.f.x5 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x6 normal {x l}} else {configure_entry .menu7.config.f.x6 disabled {x l}} -} - - -proc update_define_menu7 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE&15]} else {set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE|16]} - global tmpvar_17 - global CONFIG_MMU_COMBINED - if {$tmpvar_17 == "combined"} then {set CONFIG_MMU_COMBINED 1} else {set CONFIG_MMU_COMBINED 0} - global CONFIG_MMU_SPLIT - if {$tmpvar_17 == "split"} then {set CONFIG_MMU_SPLIT 1} else {set CONFIG_MMU_SPLIT 0} - global tmpvar_18 - global CONFIG_MMU_REPARRAY - if {$tmpvar_18 == "LRU"} then {set CONFIG_MMU_REPARRAY 1} else {set CONFIG_MMU_REPARRAY 0} - global CONFIG_MMU_REPINCREMENT - if {$tmpvar_18 == "Increment"} then {set CONFIG_MMU_REPINCREMENT 1} else {set CONFIG_MMU_REPINCREMENT 0} - global tmpvar_19 - global CONFIG_MMU_I2 - if {$tmpvar_19 == "2"} then {set CONFIG_MMU_I2 1} else {set CONFIG_MMU_I2 0} - global CONFIG_MMU_I4 - if {$tmpvar_19 == "4"} then {set CONFIG_MMU_I4 1} else {set CONFIG_MMU_I4 0} - global CONFIG_MMU_I8 - if {$tmpvar_19 == "8"} then {set CONFIG_MMU_I8 1} else {set CONFIG_MMU_I8 0} - global CONFIG_MMU_I16 - if {$tmpvar_19 == "16"} then {set CONFIG_MMU_I16 1} else {set CONFIG_MMU_I16 0} - global CONFIG_MMU_I32 - if {$tmpvar_19 == "32"} then {set CONFIG_MMU_I32 1} else {set CONFIG_MMU_I32 0} - global tmpvar_20 - global CONFIG_MMU_D2 - if {$tmpvar_20 == "2"} then {set CONFIG_MMU_D2 1} else {set CONFIG_MMU_D2 0} - global CONFIG_MMU_D4 - if {$tmpvar_20 == "4"} then {set CONFIG_MMU_D4 1} else {set CONFIG_MMU_D4 0} - global CONFIG_MMU_D8 - if {$tmpvar_20 == "8"} then {set CONFIG_MMU_D8 1} else {set CONFIG_MMU_D8 0} - global CONFIG_MMU_D16 - if {$tmpvar_20 == "16"} then {set CONFIG_MMU_D16 1} else {set CONFIG_MMU_D16 0} - global CONFIG_MMU_D32 - if {$tmpvar_20 == "32"} then {set CONFIG_MMU_D32 1} else {set CONFIG_MMU_D32 0} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB&15]} else {set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB|16]} - global tmpvar_21 - global CONFIG_MMU_PAGE_4K - if {$tmpvar_21 == "4K"} then {set CONFIG_MMU_PAGE_4K 1} else {set CONFIG_MMU_PAGE_4K 0} - global CONFIG_MMU_PAGE_8K - if {$tmpvar_21 == "8K"} then {set CONFIG_MMU_PAGE_8K 1} else {set CONFIG_MMU_PAGE_8K 0} - global CONFIG_MMU_PAGE_16K - if {$tmpvar_21 == "16K"} then {set CONFIG_MMU_PAGE_16K 1} else {set CONFIG_MMU_PAGE_16K 0} - global CONFIG_MMU_PAGE_32K - if {$tmpvar_21 == "32K"} then {set CONFIG_MMU_PAGE_32K 1} else {set CONFIG_MMU_PAGE_32K 0} - global CONFIG_MMU_PAGE_PROG - if {$tmpvar_21 == "Programmable"} then {set CONFIG_MMU_PAGE_PROG 1} else {set CONFIG_MMU_PAGE_PROG 0} -} - - -proc menu8 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 8} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 8]] - message $w.m -width 400 -aspect 300 -text \ - "Debug Support Unit " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Debug Support Unit " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 8; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu9 .menu9 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 8 0 "Enable LEON3 Debug support unit " CONFIG_DSU_ENABLE - bool $w.config.f 8 1 "Instruction trace buffer" CONFIG_DSU_ITRACE - global tmpvar_22 - minimenu $w.config.f 8 2 "Instruction trace buffer size (kbytes)" tmpvar_22 CONFIG_DSU_ITRACESZ1 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Instruction trace buffer size (kbytes)\"" - $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_22 -value "1" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_22 -value "2" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_22 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_22 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_22 -value "16" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 5 - bool $w.config.f 8 3 "AHB trace buffer" CONFIG_DSU_ATRACE - global tmpvar_23 - minimenu $w.config.f 8 4 "AHB trace buffer size (kbytes)" tmpvar_23 CONFIG_DSU_ATRACESZ1 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB trace buffer size (kbytes)\"" - $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_23 -value "1" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_23 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_23 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_23 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_23 -value "16" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu8 {} { - global CONFIG_LEON3 - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu8.config.f.x0 normal {n l y}} else {configure_entry .menu8.config.f.x0 disabled {y n l}} - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - configure_entry .menu8.config.f.x1 normal {n l y}} else {configure_entry .menu8.config.f.x1 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then {configure_entry .menu8.config.f.x2 normal {x l}} else {configure_entry .menu8.config.f.x2 disabled {x l}} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - configure_entry .menu8.config.f.x3 normal {n l y}} else {configure_entry .menu8.config.f.x3 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then {configure_entry .menu8.config.f.x4 normal {x l}} else {configure_entry .menu8.config.f.x4 disabled {x l}} -} - - -proc update_define_menu8 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE&15]} else {set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE|16]} - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE&15]} else {set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE|16]} - global tmpvar_22 - global CONFIG_DSU_ITRACESZ1 - if {$tmpvar_22 == "1"} then {set CONFIG_DSU_ITRACESZ1 1} else {set CONFIG_DSU_ITRACESZ1 0} - global CONFIG_DSU_ITRACESZ2 - if {$tmpvar_22 == "2"} then {set CONFIG_DSU_ITRACESZ2 1} else {set CONFIG_DSU_ITRACESZ2 0} - global CONFIG_DSU_ITRACESZ4 - if {$tmpvar_22 == "4"} then {set CONFIG_DSU_ITRACESZ4 1} else {set CONFIG_DSU_ITRACESZ4 0} - global CONFIG_DSU_ITRACESZ8 - if {$tmpvar_22 == "8"} then {set CONFIG_DSU_ITRACESZ8 1} else {set CONFIG_DSU_ITRACESZ8 0} - global CONFIG_DSU_ITRACESZ16 - if {$tmpvar_22 == "16"} then {set CONFIG_DSU_ITRACESZ16 1} else {set CONFIG_DSU_ITRACESZ16 0} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then { - set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE&15]} else {set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE|16]} - global tmpvar_23 - global CONFIG_DSU_ATRACESZ1 - if {$tmpvar_23 == "1"} then {set CONFIG_DSU_ATRACESZ1 1} else {set CONFIG_DSU_ATRACESZ1 0} - global CONFIG_DSU_ATRACESZ2 - if {$tmpvar_23 == "2"} then {set CONFIG_DSU_ATRACESZ2 1} else {set CONFIG_DSU_ATRACESZ2 0} - global CONFIG_DSU_ATRACESZ4 - if {$tmpvar_23 == "4"} then {set CONFIG_DSU_ATRACESZ4 1} else {set CONFIG_DSU_ATRACESZ4 0} - global CONFIG_DSU_ATRACESZ8 - if {$tmpvar_23 == "8"} then {set CONFIG_DSU_ATRACESZ8 1} else {set CONFIG_DSU_ATRACESZ8 0} - global CONFIG_DSU_ATRACESZ16 - if {$tmpvar_23 == "16"} then {set CONFIG_DSU_ATRACESZ16 1} else {set CONFIG_DSU_ATRACESZ16 0} -} - - -proc menu9 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 9} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 9]] - message $w.m -width 400 -aspect 300 -text \ - "Fault-tolerance " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Fault-tolerance " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 9; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu10 .menu10 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu9 {} { -} - - -proc update_define_menu9 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu10 {w title} { - set oldFocus [focus] - catch {focus .menu3} - catch {destroy $w; unregister_active 10} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 10]] - message $w.m -width 400 -aspect 300 -text \ - "VHDL debug settings " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "VHDL debug settings " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 10; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 10; catch {destroy .menu3}; unregister_active 3; menu11 .menu11 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 10 0 "Processor disassembly to console " CONFIG_IU_DISAS - bool $w.config.f 10 1 "Processor disassembly in netlist " CONFIG_IU_DISAS_NET - bool $w.config.f 10 2 "32-bit program counters " CONFIG_DEBUG_PC32 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} - set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu10 {} { - global CONFIG_LEON3 - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu10.config.f.x0 normal {n l y}} else {configure_entry .menu10.config.f.x0 disabled {y n l}} - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then { - configure_entry .menu10.config.f.x1 normal {n l y}} else {configure_entry .menu10.config.f.x1 disabled {y n l}} - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then { - configure_entry .menu10.config.f.x2 normal {n l y}} else {configure_entry .menu10.config.f.x2 disabled {y n l}} -} - - -proc update_define_menu10 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_LEON3 - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS&15]} else {set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS|16]} - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then { - set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET&15]} else {set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET|16]} - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then { - set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32&15]} else {set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32|16]} -} - - -menu_option menu11 11 "AMBA configuration" -proc menu11 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 11} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 11]] - message $w.m -width 400 -aspect 300 -text \ - "AMBA configuration" -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "AMBA configuration" - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu12 .menu12 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - int $w.config.f 11 0 "Default AHB master" CONFIG_AHB_DEFMST - bool $w.config.f 11 1 "Round-robin arbiter " CONFIG_AHB_RROBIN - bool $w.config.f 11 2 "AHB split-transaction support " CONFIG_AHB_SPLIT - hex $w.config.f 11 3 "I/O area start address (haddr\[31:20\]) " CONFIG_AHB_IOADDR - hex $w.config.f 11 4 "AHB/APB bridge address (haddr\[31:20\]) " CONFIG_APB_HADDR - bool $w.config.f 11 5 "Enable AMBA AHB monitor " CONFIG_AHB_MON - bool $w.config.f 11 6 "Report AHB errors " CONFIG_AHB_MONERR - bool $w.config.f 11 7 "Report AHB warings " CONFIG_AHB_MONWAR - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu11 {} { - global CONFIG_AHB_MON - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then { - configure_entry .menu11.config.f.x6 normal {n l y}} else {configure_entry .menu11.config.f.x6 disabled {y n l}} - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then { - configure_entry .menu11.config.f.x7 normal {n l y}} else {configure_entry .menu11.config.f.x7 disabled {y n l}} -} - - -proc update_define_menu11 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_AHB_MON - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then { - set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR&15]} else {set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR|16]} - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then { - set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR&15]} else {set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR|16]} -} - - -menu_option menu12 12 "Debug Link " -proc menu12 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 12} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 12]] - message $w.m -width 400 -aspect 300 -text \ - "Debug Link " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Debug Link " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu13 .menu13 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 12 0 "Serial Debug Link (RS232) " CONFIG_DSU_UART - bool $w.config.f 12 1 "JTAG Debug Link" CONFIG_DSU_JTAG - bool $w.config.f 12 2 "Ethernet Debug Communication Link (EDCL)" CONFIG_DSU_ETH - global tmpvar_25 - minimenu $w.config.f 12 3 "Ethernet/AHB bridge buffer size (kbytes)" tmpvar_25 CONFIG_DSU_ETHSZ1 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Ethernet/AHB bridge buffer size (kbytes)\"" - $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_25 -value "1" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_25 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_25 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_25 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_25 -value "16" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 5 - hex $w.config.f 12 4 "MSB 16 bits of IP address (hex) " CONFIG_DSU_IPMSB - hex $w.config.f 12 5 "LSB 16 bits of IP address (hex) " CONFIG_DSU_IPLSB - hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB - hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB - bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu12 {} { - global CONFIG_GRETH_ENABLE - global CONFIG_DSU_ETH - if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu12.config.f.x2 normal {n l y}} else {configure_entry .menu12.config.f.x2 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {configure_entry .menu12.config.f.x3 normal {x l}} else {configure_entry .menu12.config.f.x3 disabled {x l}} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x4.l configure -state normal; } else {.menu12.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x4.l configure -state disabled} - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x5.l configure -state normal; } else {.menu12.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x5.l configure -state disabled} - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA - global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} -} - - -proc update_define_menu12 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_GRETH_ENABLE - global CONFIG_DSU_ETH - if {($CONFIG_GRETH_ENABLE == 1)} then { - set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH&15]} else {set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH|16]} - global tmpvar_25 - global CONFIG_DSU_ETHSZ1 - if {$tmpvar_25 == "1"} then {set CONFIG_DSU_ETHSZ1 1} else {set CONFIG_DSU_ETHSZ1 0} - global CONFIG_DSU_ETHSZ2 - if {$tmpvar_25 == "2"} then {set CONFIG_DSU_ETHSZ2 1} else {set CONFIG_DSU_ETHSZ2 0} - global CONFIG_DSU_ETHSZ4 - if {$tmpvar_25 == "4"} then {set CONFIG_DSU_ETHSZ4 1} else {set CONFIG_DSU_ETHSZ4 0} - global CONFIG_DSU_ETHSZ8 - if {$tmpvar_25 == "8"} then {set CONFIG_DSU_ETHSZ8 1} else {set CONFIG_DSU_ETHSZ8 0} - global CONFIG_DSU_ETHSZ16 - if {$tmpvar_25 == "16"} then {set CONFIG_DSU_ETHSZ16 1} else {set CONFIG_DSU_ETHSZ16 0} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPMSB "$CONFIG_DSU_IPMSB" C0A8} - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPLSB "$CONFIG_DSU_IPLSB" 0033} - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA - global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} -} - - -menu_option menu13 13 "Peripherals " -proc menu13 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 13} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 13]] - message $w.m -width 400 -aspect 300 -text \ - "Peripherals " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Peripherals " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; break" - set nextscript "catch {focus $oldFocus}; menu14 .menu14 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - submenu $w.config.f 13 0 "Memory controllers " 14 - submenu $w.config.f 13 1 "On-chip RAM/ROM " 18 - submenu $w.config.f 13 2 "Ethernet " 19 - submenu $w.config.f 13 3 "CAN " 20 - submenu $w.config.f 13 4 "PCI " 21 - submenu $w.config.f 13 5 "Spacewire " 22 - submenu $w.config.f 13 6 "UARTs, timers and irq control " 23 - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu13 {} { -} - - -proc update_define_menu13 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu14 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 14} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 14]] - message $w.m -width 400 -aspect 300 -text \ - "Memory controllers " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Memory controllers " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; break" - set nextscript "catch {focus $oldFocus}; menu15 .menu15 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - submenu $w.config.f 14 0 "8/32-bit PROM/SRAM controller " 15 - submenu $w.config.f 14 1 "Leon2 memory controller " 16 - submenu $w.config.f 14 2 "PC133 SDRAM controller " 17 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu14 {} { -} - - -proc update_define_menu14 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc menu15 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 15} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 15]] - message $w.m -width 400 -aspect 300 -text \ - "8/32-bit PROM/SRAM controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "8/32-bit PROM/SRAM controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu16 .menu16 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 15 0 "Enable 8/32-bit PROM/SRAM controller " CONFIG_SRCTRL - bool $w.config.f 15 1 "8-bit PROM interface " CONFIG_SRCTRL_8BIT - int $w.config.f 15 2 "PROM waitstates" CONFIG_SRCTRL_PROMWS - int $w.config.f 15 3 "RAM waitstates" CONFIG_SRCTRL_RAMWS - int $w.config.f 15 4 "IO waitstates" CONFIG_SRCTRL_IOWS - bool $w.config.f 15 5 "Use read-modify-write for sub-word writes " CONFIG_SRCTRL_RMW - global tmpvar_26 - minimenu $w.config.f 15 6 "SRAM banks" tmpvar_26 CONFIG_SRCTRL_SRBANKS1 - menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"SRAM banks\"" - $w.config.f.x6.x.menu add radiobutton -label "1" -variable tmpvar_26 -value "1" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "2" -variable tmpvar_26 -value "2" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "3" -variable tmpvar_26 -value "3" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "4" -variable tmpvar_26 -value "4" -command "update_active" - $w.config.f.x6.x.menu add radiobutton -label "5" -variable tmpvar_26 -value "5" -command "update_active" - menusplit $w $w.config.f.x6.x.menu 5 - global tmpvar_27 - minimenu $w.config.f 15 7 "SRAM bank size (kb) (0 for programmable)" tmpvar_27 CONFIG_SRCTRL_BANKSZ0 - menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"SRAM bank size (kb) (0 for programmable)\"" - $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_27 -value "8" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_27 -value "16" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_27 -value "32" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_27 -value "64" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_27 -value "128" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_27 -value "256" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "512" -variable tmpvar_27 -value "512" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "1024" -variable tmpvar_27 -value "1024" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "2048" -variable tmpvar_27 -value "2048" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "4096" -variable tmpvar_27 -value "4096" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "8192" -variable tmpvar_27 -value "8192" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "16384" -variable tmpvar_27 -value "16384" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "32768" -variable tmpvar_27 -value "32768" -command "update_active" - $w.config.f.x7.x.menu add radiobutton -label "65536" -variable tmpvar_27 -value "65536" -command "update_active" - menusplit $w $w.config.f.x7.x.menu 14 - int $w.config.f 15 8 "PROM bank select address bit (0 - 28)" CONFIG_SRCTRL_ROMASEL - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu15 {} { - global CONFIG_SRCTRL - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then { - configure_entry .menu15.config.f.x1 normal {n l y}} else {configure_entry .menu15.config.f.x1 disabled {y n l}} - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x2.l configure -state normal; } else {.menu15.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x2.l configure -state disabled} - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x3.l configure -state normal; } else {.menu15.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x3.l configure -state disabled} - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x4.l configure -state normal; } else {.menu15.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x4.l configure -state disabled} - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then { - configure_entry .menu15.config.f.x5 normal {n l y}} else {configure_entry .menu15.config.f.x5 disabled {y n l}} - if {($CONFIG_SRCTRL == 1)} then {configure_entry .menu15.config.f.x6 normal {x l}} else {configure_entry .menu15.config.f.x6 disabled {x l}} - if {($CONFIG_SRCTRL == 1)} then {configure_entry .menu15.config.f.x7 normal {x l}} else {configure_entry .menu15.config.f.x7 disabled {x l}} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {.menu15.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu15.config.f.x8.l configure -state normal; } else {.menu15.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu15.config.f.x8.l configure -state disabled} -} - - -proc update_define_menu15 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SRCTRL - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then { - set CONFIG_SRCTRL_8BIT [expr $CONFIG_SRCTRL_8BIT&15]} else {set CONFIG_SRCTRL_8BIT [expr $CONFIG_SRCTRL_8BIT|16]} - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_PROMWS "$CONFIG_SRCTRL_PROMWS" 3} - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_RAMWS "$CONFIG_SRCTRL_RAMWS" 0} - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_IOWS "$CONFIG_SRCTRL_IOWS" 0} - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then { - set CONFIG_SRCTRL_RMW [expr $CONFIG_SRCTRL_RMW&15]} else {set CONFIG_SRCTRL_RMW [expr $CONFIG_SRCTRL_RMW|16]} - global tmpvar_26 - global CONFIG_SRCTRL_SRBANKS1 - if {$tmpvar_26 == "1"} then {set CONFIG_SRCTRL_SRBANKS1 1} else {set CONFIG_SRCTRL_SRBANKS1 0} - global CONFIG_SRCTRL_SRBANKS2 - if {$tmpvar_26 == "2"} then {set CONFIG_SRCTRL_SRBANKS2 1} else {set CONFIG_SRCTRL_SRBANKS2 0} - global CONFIG_SRCTRL_SRBANKS3 - if {$tmpvar_26 == "3"} then {set CONFIG_SRCTRL_SRBANKS3 1} else {set CONFIG_SRCTRL_SRBANKS3 0} - global CONFIG_SRCTRL_SRBANKS4 - if {$tmpvar_26 == "4"} then {set CONFIG_SRCTRL_SRBANKS4 1} else {set CONFIG_SRCTRL_SRBANKS4 0} - global CONFIG_SRCTRL_SRBANKS5 - if {$tmpvar_26 == "5"} then {set CONFIG_SRCTRL_SRBANKS5 1} else {set CONFIG_SRCTRL_SRBANKS5 0} - global tmpvar_27 - global CONFIG_SRCTRL_BANKSZ0 - if {$tmpvar_27 == "8"} then {set CONFIG_SRCTRL_BANKSZ0 1} else {set CONFIG_SRCTRL_BANKSZ0 0} - global CONFIG_SRCTRL_BANKSZ1 - if {$tmpvar_27 == "16"} then {set CONFIG_SRCTRL_BANKSZ1 1} else {set CONFIG_SRCTRL_BANKSZ1 0} - global CONFIG_SRCTRL_BANKSZ2 - if {$tmpvar_27 == "32"} then {set CONFIG_SRCTRL_BANKSZ2 1} else {set CONFIG_SRCTRL_BANKSZ2 0} - global CONFIG_SRCTRL_BANKSZ3 - if {$tmpvar_27 == "64"} then {set CONFIG_SRCTRL_BANKSZ3 1} else {set CONFIG_SRCTRL_BANKSZ3 0} - global CONFIG_SRCTRL_BANKSZ4 - if {$tmpvar_27 == "128"} then {set CONFIG_SRCTRL_BANKSZ4 1} else {set CONFIG_SRCTRL_BANKSZ4 0} - global CONFIG_SRCTRL_BANKSZ5 - if {$tmpvar_27 == "256"} then {set CONFIG_SRCTRL_BANKSZ5 1} else {set CONFIG_SRCTRL_BANKSZ5 0} - global CONFIG_SRCTRL_BANKSZ6 - if {$tmpvar_27 == "512"} then {set CONFIG_SRCTRL_BANKSZ6 1} else {set CONFIG_SRCTRL_BANKSZ6 0} - global CONFIG_SRCTRL_BANKSZ7 - if {$tmpvar_27 == "1024"} then {set CONFIG_SRCTRL_BANKSZ7 1} else {set CONFIG_SRCTRL_BANKSZ7 0} - global CONFIG_SRCTRL_BANKSZ8 - if {$tmpvar_27 == "2048"} then {set CONFIG_SRCTRL_BANKSZ8 1} else {set CONFIG_SRCTRL_BANKSZ8 0} - global CONFIG_SRCTRL_BANKSZ9 - if {$tmpvar_27 == "4096"} then {set CONFIG_SRCTRL_BANKSZ9 1} else {set CONFIG_SRCTRL_BANKSZ9 0} - global CONFIG_SRCTRL_BANKSZ10 - if {$tmpvar_27 == "8192"} then {set CONFIG_SRCTRL_BANKSZ10 1} else {set CONFIG_SRCTRL_BANKSZ10 0} - global CONFIG_SRCTRL_BANKSZ11 - if {$tmpvar_27 == "16384"} then {set CONFIG_SRCTRL_BANKSZ11 1} else {set CONFIG_SRCTRL_BANKSZ11 0} - global CONFIG_SRCTRL_BANKSZ12 - if {$tmpvar_27 == "32768"} then {set CONFIG_SRCTRL_BANKSZ12 1} else {set CONFIG_SRCTRL_BANKSZ12 0} - global CONFIG_SRCTRL_BANKSZ13 - if {$tmpvar_27 == "65536"} then {set CONFIG_SRCTRL_BANKSZ13 1} else {set CONFIG_SRCTRL_BANKSZ13 0} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {validate_int CONFIG_SRCTRL_ROMASEL "$CONFIG_SRCTRL_ROMASEL" 19} -} - - -proc menu16 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 16} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 16]] - message $w.m -width 400 -aspect 300 -text \ - "Leon2 memory controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Leon2 memory controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu17 .menu17 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 16 0 "Enable Leon2 memory controller " CONFIG_MCTRL_LEON2 - bool $w.config.f 16 1 "8-bit PROM/SRAM bus support " CONFIG_MCTRL_8BIT - bool $w.config.f 16 2 "16-bit PROM/SRAM bus support " CONFIG_MCTRL_16BIT - bool $w.config.f 16 3 "5th SRAM chip-select " CONFIG_MCTRL_5CS - bool $w.config.f 16 4 "SDRAM controller " CONFIG_MCTRL_SDRAM - bool $w.config.f 16 5 "Separate address and data buses" CONFIG_MCTRL_SDRAM_SEPBUS - bool $w.config.f 16 6 "64-bit SDRAM data bus" CONFIG_MCTRL_SDRAM_BUS64 - bool $w.config.f 16 7 "Unsynchronized sdclock" CONFIG_MCTRL_SDRAM_INVCLK - bool $w.config.f 16 8 "Enable page burst operation " CONFIG_MCTRL_PAGE - bool $w.config.f 16 9 "Enable programmable page burst " CONFIG_MCTRL_PROGPAGE - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu16 {} { - global CONFIG_MCTRL_LEON2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x1 normal {n l y}} else {configure_entry .menu16.config.f.x1 disabled {y n l}} - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x2 normal {n l y}} else {configure_entry .menu16.config.f.x2 disabled {y n l}} - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x3 normal {n l y}} else {configure_entry .menu16.config.f.x3 disabled {y n l}} - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu16.config.f.x4 normal {n l y}} else {configure_entry .menu16.config.f.x4 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - configure_entry .menu16.config.f.x5 normal {n l y}} else {configure_entry .menu16.config.f.x5 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - configure_entry .menu16.config.f.x6 normal {n l y}} else {configure_entry .menu16.config.f.x6 disabled {y n l}} - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - configure_entry .menu16.config.f.x7 normal {n l y}} else {configure_entry .menu16.config.f.x7 disabled {y n l}} - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - configure_entry .menu16.config.f.x8 normal {n l y}} else {configure_entry .menu16.config.f.x8 disabled {y n l}} - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { - configure_entry .menu16.config.f.x9 normal {n l y}} else {configure_entry .menu16.config.f.x9 disabled {y n l}} -} - - -proc update_define_menu16 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_MCTRL_LEON2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT&15]} else {set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT|16]} - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT&15]} else {set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT|16]} - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS&15]} else {set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS|16]} - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then { - set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM&15]} else {set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM|16]} - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS&15]} else {set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS|16]} - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64&15]} else {set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64|16]} - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK&15]} else {set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK|16]} - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE&15]} else {set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE|16]} - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { - set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE&15]} else {set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE|16]} -} - - -proc menu17 {w title} { - set oldFocus [focus] - catch {focus .menu14} - catch {destroy $w; unregister_active 17} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 17]] - message $w.m -width 400 -aspect 300 -text \ - "PC133 SDRAM controller " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "PC133 SDRAM controller " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 17; catch {destroy .menu14}; unregister_active 14; menu18 .menu18 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 17 0 "Enable PC133 SDRAM controller " CONFIG_SDCTRL - bool $w.config.f 17 1 "64-bit SDRAM data bus" CONFIG_SDCTRL_BUS64 - bool $w.config.f 17 2 "Unsynchronized sdclock" CONFIG_SDCTRL_INVCLK - bool $w.config.f 17 3 "Enable page burst operation " CONFIG_SDCTRL_PAGE - bool $w.config.f 17 4 "Enable programmable page burst " CONFIG_SDCTRL_PROGPAGE - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} - set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu17 {} { - global CONFIG_SDCTRL - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x1 normal {n l y}} else {configure_entry .menu17.config.f.x1 disabled {y n l}} - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x2 normal {n l y}} else {configure_entry .menu17.config.f.x2 disabled {y n l}} - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then { - configure_entry .menu17.config.f.x3 normal {n l y}} else {configure_entry .menu17.config.f.x3 disabled {y n l}} - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then { - configure_entry .menu17.config.f.x4 normal {n l y}} else {configure_entry .menu17.config.f.x4 disabled {y n l}} -} - - -proc update_define_menu17 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SDCTRL - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_BUS64 [expr $CONFIG_SDCTRL_BUS64&15]} else {set CONFIG_SDCTRL_BUS64 [expr $CONFIG_SDCTRL_BUS64|16]} - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_INVCLK [expr $CONFIG_SDCTRL_INVCLK&15]} else {set CONFIG_SDCTRL_INVCLK [expr $CONFIG_SDCTRL_INVCLK|16]} - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then { - set CONFIG_SDCTRL_PAGE [expr $CONFIG_SDCTRL_PAGE&15]} else {set CONFIG_SDCTRL_PAGE [expr $CONFIG_SDCTRL_PAGE|16]} - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then { - set CONFIG_SDCTRL_PROGPAGE [expr $CONFIG_SDCTRL_PROGPAGE&15]} else {set CONFIG_SDCTRL_PROGPAGE [expr $CONFIG_SDCTRL_PROGPAGE|16]} -} - - -proc menu18 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 18} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 18]] - message $w.m -width 400 -aspect 300 -text \ - "On-chip RAM/ROM " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "On-chip RAM/ROM " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu19 .menu19 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 18 0 "On-chip AHB ROM " CONFIG_AHBROM_ENABLE - hex $w.config.f 18 1 "ROM start address (haddr\[31:20\]) " CONFIG_AHBROM_START - bool $w.config.f 18 2 "Pipelined ROM access " CONFIG_AHBROM_PIPE - bool $w.config.f 18 3 "On-chip AHB RAM " CONFIG_AHBRAM_ENABLE - global tmpvar_28 - minimenu $w.config.f 18 4 "AHB RAM size (Kbyte)" tmpvar_28 CONFIG_AHBRAM_SZ1 - menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB RAM size (Kbyte)\"" - $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_28 -value "1" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_28 -value "2" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_28 -value "4" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_28 -value "8" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_28 -value "16" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_28 -value "32" -command "update_active" - $w.config.f.x4.x.menu add radiobutton -label "64" -variable tmpvar_28 -value "64" -command "update_active" - menusplit $w $w.config.f.x4.x.menu 7 - hex $w.config.f 18 5 "RAM start address (haddr\[31:20\]) " CONFIG_AHBRAM_START - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu18 {} { - global CONFIG_AHBROM_ENABLE - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {.menu18.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x1.l configure -state normal; } else {.menu18.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x1.l configure -state disabled} - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then { - configure_entry .menu18.config.f.x2 normal {n l y}} else {configure_entry .menu18.config.f.x2 disabled {y n l}} - global CONFIG_AHBRAM_ENABLE - if {($CONFIG_AHBRAM_ENABLE == 1)} then {configure_entry .menu18.config.f.x4 normal {x l}} else {configure_entry .menu18.config.f.x4 disabled {x l}} - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {.menu18.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x5.l configure -state normal; } else {.menu18.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x5.l configure -state disabled} -} - - -proc update_define_menu18 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_AHBROM_ENABLE - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {validate_hex CONFIG_AHBROM_START "$CONFIG_AHBROM_START" 000} - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then { - set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE&15]} else {set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE|16]} - global tmpvar_28 - global CONFIG_AHBRAM_SZ1 - if {$tmpvar_28 == "1"} then {set CONFIG_AHBRAM_SZ1 1} else {set CONFIG_AHBRAM_SZ1 0} - global CONFIG_AHBRAM_SZ2 - if {$tmpvar_28 == "2"} then {set CONFIG_AHBRAM_SZ2 1} else {set CONFIG_AHBRAM_SZ2 0} - global CONFIG_AHBRAM_SZ4 - if {$tmpvar_28 == "4"} then {set CONFIG_AHBRAM_SZ4 1} else {set CONFIG_AHBRAM_SZ4 0} - global CONFIG_AHBRAM_SZ8 - if {$tmpvar_28 == "8"} then {set CONFIG_AHBRAM_SZ8 1} else {set CONFIG_AHBRAM_SZ8 0} - global CONFIG_AHBRAM_SZ16 - if {$tmpvar_28 == "16"} then {set CONFIG_AHBRAM_SZ16 1} else {set CONFIG_AHBRAM_SZ16 0} - global CONFIG_AHBRAM_SZ32 - if {$tmpvar_28 == "32"} then {set CONFIG_AHBRAM_SZ32 1} else {set CONFIG_AHBRAM_SZ32 0} - global CONFIG_AHBRAM_SZ64 - if {$tmpvar_28 == "64"} then {set CONFIG_AHBRAM_SZ64 1} else {set CONFIG_AHBRAM_SZ64 0} - global CONFIG_AHBRAM_ENABLE - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {validate_hex CONFIG_AHBRAM_START "$CONFIG_AHBRAM_START" A00} -} - - -proc menu19 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 19} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 19]] - message $w.m -width 400 -aspect 300 -text \ - "Ethernet " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Ethernet " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu20 .menu20 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 19 0 "Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH_ENABLE - bool $w.config.f 19 1 "Enable 1000 Mbit support " CONFIG_GRETH_GIGA - global tmpvar_29 - minimenu $w.config.f 19 2 "AHB FIFO size (words) " tmpvar_29 CONFIG_GRETH_FIFO4 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB FIFO size (words) \"" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_29 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_29 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_29 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_29 -value "32" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_29 -value "64" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu19 {} { - global CONFIG_GRETH_ENABLE - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu19.config.f.x1 normal {n l y}} else {configure_entry .menu19.config.f.x1 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {configure_entry .menu19.config.f.x2 normal {x l}} else {configure_entry .menu19.config.f.x2 disabled {x l}} -} - - -proc update_define_menu19 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_GRETH_ENABLE - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1)} then { - set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA&15]} else {set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA|16]} - global tmpvar_29 - global CONFIG_GRETH_FIFO4 - if {$tmpvar_29 == "4"} then {set CONFIG_GRETH_FIFO4 1} else {set CONFIG_GRETH_FIFO4 0} - global CONFIG_GRETH_FIFO8 - if {$tmpvar_29 == "8"} then {set CONFIG_GRETH_FIFO8 1} else {set CONFIG_GRETH_FIFO8 0} - global CONFIG_GRETH_FIFO16 - if {$tmpvar_29 == "16"} then {set CONFIG_GRETH_FIFO16 1} else {set CONFIG_GRETH_FIFO16 0} - global CONFIG_GRETH_FIFO32 - if {$tmpvar_29 == "32"} then {set CONFIG_GRETH_FIFO32 1} else {set CONFIG_GRETH_FIFO32 0} - global CONFIG_GRETH_FIFO64 - if {$tmpvar_29 == "64"} then {set CONFIG_GRETH_FIFO64 1} else {set CONFIG_GRETH_FIFO64 0} -} - - -proc menu20 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 20} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 20]] - message $w.m -width 400 -aspect 300 -text \ - "CAN " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "CAN " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu21 .menu21 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 20 0 "Enable CAN interface " CONFIG_CAN_ENABLE - hex $w.config.f 20 1 "CAN I/O area start address (haddr\[19:8\]) " CONFIG_CANIO - int $w.config.f 20 2 "Interrupt number " CONFIG_CANIRQ - bool $w.config.f 20 3 "Enable loop-back testing " CONFIG_CANLOOP - bool $w.config.f 20 4 "Enable synchronous reset " CONFIG_CAN_SYNCRST - bool $w.config.f 20 5 "Enable FT FIFO memory " CONFIG_CAN_FT - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu20 {} { - global CONFIG_CAN_ENABLE - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {.menu20.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x1.l configure -state normal; } else {.menu20.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x1.l configure -state disabled} - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {.menu20.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x2.l configure -state normal; } else {.menu20.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x2.l configure -state disabled} - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x3 normal {n l y}} else {configure_entry .menu20.config.f.x3 disabled {y n l}} - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x4 normal {n l y}} else {configure_entry .menu20.config.f.x4 disabled {y n l}} - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then { - configure_entry .menu20.config.f.x5 normal {n l y}} else {configure_entry .menu20.config.f.x5 disabled {y n l}} -} - - -proc update_define_menu20 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_CAN_ENABLE - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {validate_hex CONFIG_CANIO "$CONFIG_CANIO" C00} - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {validate_int CONFIG_CANIRQ "$CONFIG_CANIRQ" 13} - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CANLOOP [expr $CONFIG_CANLOOP&15]} else {set CONFIG_CANLOOP [expr $CONFIG_CANLOOP|16]} - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CAN_SYNCRST [expr $CONFIG_CAN_SYNCRST&15]} else {set CONFIG_CAN_SYNCRST [expr $CONFIG_CAN_SYNCRST|16]} - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then { - set CONFIG_CAN_FT [expr $CONFIG_CAN_FT&15]} else {set CONFIG_CAN_FT [expr $CONFIG_CAN_FT|16]} -} - - -proc menu21 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 21} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 21]] - message $w.m -width 400 -aspect 300 -text \ - "PCI " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "PCI " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu22 .menu22 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 21 0 "PCI interface, target-only " CONFIG_PCI_SIMPLE_TARGET - bool $w.config.f 21 1 "PCI interface, master-target " CONFIG_PCI_MASTER_TARGET - bool $w.config.f 21 2 "PCI DMA controller " CONFIG_PCI_MASTER_TARGET_DMA - hex $w.config.f 21 3 "PCI vendor ID" CONFIG_PCI_VENDORID - hex $w.config.f 21 4 "PCI device ID" CONFIG_PCI_DEVICEID - global tmpvar_30 - minimenu $w.config.f 21 5 "PCI FIFO depth" tmpvar_30 CONFIG_PCI_FIFO0 - menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"PCI FIFO depth\"" - $w.config.f.x5.x.menu add radiobutton -label "None" -variable tmpvar_30 -value "None" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "8" -variable tmpvar_30 -value "8" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "16" -variable tmpvar_30 -value "16" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "32" -variable tmpvar_30 -value "32" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_30 -value "64" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "128" -variable tmpvar_30 -value "128" -command "update_active" - menusplit $w $w.config.f.x5.x.menu 6 - hex $w.config.f 21 6 "PCI initiator address (haddr\[31:20\]) " CONFIG_PCI_HADDR - bool $w.config.f 21 7 "PCI arbiter " CONFIG_PCI_ARBITER - bool $w.config.f 21 8 "PCI arbiter APB interface " CONFIG_PCI_ARBITER_APB - int $w.config.f 21 9 "Number of PCI REQ/GNT pairs" CONFIG_PCI_ARBITER_NREQ - bool $w.config.f 21 10 "Enable PCI trace buffer " CONFIG_PCI_TRACE - global tmpvar_31 - minimenu $w.config.f 21 11 "PCI trace buffer depth" tmpvar_31 CONFIG_PCI_TRACE256 - menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"PCI trace buffer depth\"" - $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_31 -value "256" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "512" -variable tmpvar_31 -value "512" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "1024" -variable tmpvar_31 -value "1024" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "2048" -variable tmpvar_31 -value "2048" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "4096" -variable tmpvar_31 -value "4096" -command "update_active" - menusplit $w $w.config.f.x11.x.menu 5 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu21 {} { - global CONFIG_PCI_ACTEL - global CONFIG_PCI_SIMPLE_TARGET - if {($CONFIG_PCI_ACTEL != 1)} then { - configure_entry .menu21.config.f.x0 normal {n l y}} else {configure_entry .menu21.config.f.x0 disabled {y n l}} - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then { - configure_entry .menu21.config.f.x1 normal {n l y}} else {configure_entry .menu21.config.f.x1 disabled {y n l}} - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then { - configure_entry .menu21.config.f.x2 normal {n l y}} else {configure_entry .menu21.config.f.x2 disabled {y n l}} - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x3.l configure -state normal; } else {.menu21.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x3.l configure -state disabled} - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x4.l configure -state normal; } else {.menu21.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x4.l configure -state disabled} - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {configure_entry .menu21.config.f.x5 normal {x l}} else {configure_entry .menu21.config.f.x5 disabled {x l}} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {.menu21.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x6.l configure -state normal; } else {.menu21.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x6.l configure -state disabled} - global CONFIG_PCI_ARBITER - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then { - configure_entry .menu21.config.f.x8 normal {n l y}} else {configure_entry .menu21.config.f.x8 disabled {y n l}} - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {.menu21.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x9.l configure -state normal; } else {.menu21.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x9.l configure -state disabled} - global CONFIG_PCI_TRACE - if {($CONFIG_PCI_TRACE == 1)} then {configure_entry .menu21.config.f.x11 normal {x l}} else {configure_entry .menu21.config.f.x11 disabled {x l}} -} - - -proc update_define_menu21 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_PCI_ACTEL - global CONFIG_PCI_SIMPLE_TARGET - if {($CONFIG_PCI_ACTEL != 1)} then { - set CONFIG_PCI_SIMPLE_TARGET [expr $CONFIG_PCI_SIMPLE_TARGET&15]} else {set CONFIG_PCI_SIMPLE_TARGET [expr $CONFIG_PCI_SIMPLE_TARGET|16]} - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then { - set CONFIG_PCI_MASTER_TARGET [expr $CONFIG_PCI_MASTER_TARGET&15]} else {set CONFIG_PCI_MASTER_TARGET [expr $CONFIG_PCI_MASTER_TARGET|16]} - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then { - set CONFIG_PCI_MASTER_TARGET_DMA [expr $CONFIG_PCI_MASTER_TARGET_DMA&15]} else {set CONFIG_PCI_MASTER_TARGET_DMA [expr $CONFIG_PCI_MASTER_TARGET_DMA|16]} - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_VENDORID "$CONFIG_PCI_VENDORID" 1AC8} - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_DEVICEID "$CONFIG_PCI_DEVICEID" 0054} - global tmpvar_30 - global CONFIG_PCI_FIFO0 - if {$tmpvar_30 == "None"} then {set CONFIG_PCI_FIFO0 1} else {set CONFIG_PCI_FIFO0 0} - global CONFIG_PCI_FIFO8 - if {$tmpvar_30 == "8"} then {set CONFIG_PCI_FIFO8 1} else {set CONFIG_PCI_FIFO8 0} - global CONFIG_PCI_FIFO16 - if {$tmpvar_30 == "16"} then {set CONFIG_PCI_FIFO16 1} else {set CONFIG_PCI_FIFO16 0} - global CONFIG_PCI_FIFO32 - if {$tmpvar_30 == "32"} then {set CONFIG_PCI_FIFO32 1} else {set CONFIG_PCI_FIFO32 0} - global CONFIG_PCI_FIFO64 - if {$tmpvar_30 == "64"} then {set CONFIG_PCI_FIFO64 1} else {set CONFIG_PCI_FIFO64 0} - global CONFIG_PCI_FIFO128 - if {$tmpvar_30 == "128"} then {set CONFIG_PCI_FIFO128 1} else {set CONFIG_PCI_FIFO128 0} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {validate_hex CONFIG_PCI_HADDR "$CONFIG_PCI_HADDR" E00} - global CONFIG_PCI_ARBITER - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then { - set CONFIG_PCI_ARBITER_APB [expr $CONFIG_PCI_ARBITER_APB&15]} else {set CONFIG_PCI_ARBITER_APB [expr $CONFIG_PCI_ARBITER_APB|16]} - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {validate_int CONFIG_PCI_ARBITER_NREQ "$CONFIG_PCI_ARBITER_NREQ" 4} - global tmpvar_31 - global CONFIG_PCI_TRACE256 - if {$tmpvar_31 == "256"} then {set CONFIG_PCI_TRACE256 1} else {set CONFIG_PCI_TRACE256 0} - global CONFIG_PCI_TRACE512 - if {$tmpvar_31 == "512"} then {set CONFIG_PCI_TRACE512 1} else {set CONFIG_PCI_TRACE512 0} - global CONFIG_PCI_TRACE1024 - if {$tmpvar_31 == "1024"} then {set CONFIG_PCI_TRACE1024 1} else {set CONFIG_PCI_TRACE1024 0} - global CONFIG_PCI_TRACE2048 - if {$tmpvar_31 == "2048"} then {set CONFIG_PCI_TRACE2048 1} else {set CONFIG_PCI_TRACE2048 0} - global CONFIG_PCI_TRACE4096 - if {$tmpvar_31 == "4096"} then {set CONFIG_PCI_TRACE4096 1} else {set CONFIG_PCI_TRACE4096 0} -} - - -proc menu22 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 22} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 22]] - message $w.m -width 400 -aspect 300 -text \ - "Spacewire " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "Spacewire " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu23 .menu23 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 22 0 "Enable Spacewire links " CONFIG_SPW_ENABLE - int $w.config.f 22 1 "Number of links (1 - 3)" CONFIG_SPW_NUM - global tmpvar_32 - minimenu $w.config.f 22 2 "AHB RX/TX FIFO size (32-bit words) " tmpvar_32 CONFIG_SPW_AHBFIFO4 - menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB RX/TX FIFO size (32-bit words) \"" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_32 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_32 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_32 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_32 -value "32" -command "update_active" - menusplit $w $w.config.f.x2.x.menu 4 - global tmpvar_33 - minimenu $w.config.f 22 3 "Receiver FIFO size (bytes) " tmpvar_33 CONFIG_SPW_RXFIFO16 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Receiver FIFO size (bytes) \"" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_33 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_33 -value "32" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "64" -variable tmpvar_33 -value "64" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 3 - bool $w.config.f 22 4 "Enable RMAP protocol " CONFIG_SPW_RMAP - global tmpvar_34 - minimenu $w.config.f 22 5 "RMAP buffer size (bytes) " tmpvar_34 CONFIG_SPW_RMAPBUF2 - menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"RMAP buffer size (bytes) \"" - $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_34 -value "64" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "128" -variable tmpvar_34 -value "128" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "192" -variable tmpvar_34 -value "192" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "256" -variable tmpvar_34 -value "256" -command "update_active" - menusplit $w $w.config.f.x5.x.menu 4 - bool $w.config.f 22 6 "Enable RMAP CRC check " CONFIG_SPW_RMAPCRC - bool $w.config.f 22 7 "Enable Rx unaligned transfers " CONFIG_SPW_RXUNAL - bool $w.config.f 22 8 "Spacewire FIFO protection " CONFIG_SPW_FT - bool $w.config.f 22 9 "Use GRSPWC netlist " CONFIG_SPW_NETLIST - global tmpvar_35 - minimenu $w.config.f 22 10 "Select GRSPW core (GRSPW1/GRSPW2) " tmpvar_35 CONFIG_SPW_GRSPW1 - menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Select GRSPW core (GRSPW1/GRSPW2) \"" - $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_35 -value "1" -command "update_active" - $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_35 -value "2" -command "update_active" - menusplit $w $w.config.f.x10.x.menu 2 - int $w.config.f 22 11 "Number of DMA channels (1 - 4)" CONFIG_SPW_DMACHAN - int $w.config.f 22 12 "Number of ports (1 - 2)" CONFIG_SPW_PORTS - bool $w.config.f 22 13 "Receiver and transmitter uses same clock " CONFIG_SPW_RTSAME - global tmpvar_36 - minimenu $w.config.f 22 14 "Select receiver clock type " tmpvar_36 CONFIG_SPW_RX_SDR - menu $w.config.f.x14.x.menu -tearoffcommand "menutitle \"Select receiver clock type \"" - $w.config.f.x14.x.menu add radiobutton -label "SDR" -variable tmpvar_36 -value "SDR" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "DDR" -variable tmpvar_36 -value "DDR" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "Xor" -variable tmpvar_36 -value "Xor" -command "update_active" - $w.config.f.x14.x.menu add radiobutton -label "Aeroflex" -variable tmpvar_36 -value "Aeroflex" -command "update_active" - menusplit $w $w.config.f.x14.x.menu 4 - global tmpvar_37 - minimenu $w.config.f 22 15 "Select transmitter clock type " tmpvar_37 CONFIG_SPW_TX_SDR - menu $w.config.f.x15.x.menu -tearoffcommand "menutitle \"Select transmitter clock type \"" - $w.config.f.x15.x.menu add radiobutton -label "SDR" -variable tmpvar_37 -value "SDR" -command "update_active" - $w.config.f.x15.x.menu add radiobutton -label "DDR" -variable tmpvar_37 -value "DDR" -command "update_active" - $w.config.f.x15.x.menu add radiobutton -label "Aeroflex" -variable tmpvar_37 -value "Aeroflex" -command "update_active" - menusplit $w $w.config.f.x15.x.menu 3 - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu22 {} { - global CONFIG_SPW_ENABLE - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {.menu22.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x1.l configure -state normal; } else {.menu22.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x1.l configure -state disabled} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x2 normal {x l}} else {configure_entry .menu22.config.f.x2 disabled {x l}} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x3 normal {x l}} else {configure_entry .menu22.config.f.x3 disabled {x l}} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x4 normal {n l y}} else {configure_entry .menu22.config.f.x4 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_RMAP == 1)} then {configure_entry .menu22.config.f.x5 normal {x l}} else {configure_entry .menu22.config.f.x5 disabled {x l}} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x6 normal {n l y}} else {configure_entry .menu22.config.f.x6 disabled {y n l}} - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x7 normal {n l y}} else {configure_entry .menu22.config.f.x7 disabled {y n l}} - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x8 normal {n l y}} else {configure_entry .menu22.config.f.x8 disabled {y n l}} - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then { - configure_entry .menu22.config.f.x9 normal {n l y}} else {configure_entry .menu22.config.f.x9 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1)} then {configure_entry .menu22.config.f.x10 normal {x l}} else {configure_entry .menu22.config.f.x10 disabled {x l}} - global CONFIG_SPW_GRSPW2 - global CONFIG_SPW_DMACHAN - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {.menu22.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x11.l configure -state normal; } else {.menu22.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x11.l configure -state disabled} - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {.menu22.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu22.config.f.x12.l configure -state normal; } else {.menu22.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu22.config.f.x12.l configure -state disabled} - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - configure_entry .menu22.config.f.x13 normal {n l y}} else {configure_entry .menu22.config.f.x13 disabled {y n l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {configure_entry .menu22.config.f.x14 normal {x l}} else {configure_entry .menu22.config.f.x14 disabled {x l}} - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {configure_entry .menu22.config.f.x15 normal {x l}} else {configure_entry .menu22.config.f.x15 disabled {x l}} -} - - -proc update_define_menu22 {} { - update_define_mainmenu - global CONFIG_MODULES - global CONFIG_SPW_ENABLE - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {validate_int CONFIG_SPW_NUM "$CONFIG_SPW_NUM" 1} - global tmpvar_32 - global CONFIG_SPW_AHBFIFO4 - if {$tmpvar_32 == "4"} then {set CONFIG_SPW_AHBFIFO4 1} else {set CONFIG_SPW_AHBFIFO4 0} - global CONFIG_SPW_AHBFIFO8 - if {$tmpvar_32 == "8"} then {set CONFIG_SPW_AHBFIFO8 1} else {set CONFIG_SPW_AHBFIFO8 0} - global CONFIG_SPW_AHBFIFO16 - if {$tmpvar_32 == "16"} then {set CONFIG_SPW_AHBFIFO16 1} else {set CONFIG_SPW_AHBFIFO16 0} - global CONFIG_SPW_AHBFIFO32 - if {$tmpvar_32 == "32"} then {set CONFIG_SPW_AHBFIFO32 1} else {set CONFIG_SPW_AHBFIFO32 0} - global tmpvar_33 - global CONFIG_SPW_RXFIFO16 - if {$tmpvar_33 == "16"} then {set CONFIG_SPW_RXFIFO16 1} else {set CONFIG_SPW_RXFIFO16 0} - global CONFIG_SPW_RXFIFO32 - if {$tmpvar_33 == "32"} then {set CONFIG_SPW_RXFIFO32 1} else {set CONFIG_SPW_RXFIFO32 0} - global CONFIG_SPW_RXFIFO64 - if {$tmpvar_33 == "64"} then {set CONFIG_SPW_RXFIFO64 1} else {set CONFIG_SPW_RXFIFO64 0} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RMAP [expr $CONFIG_SPW_RMAP&15]} else {set CONFIG_SPW_RMAP [expr $CONFIG_SPW_RMAP|16]} - global tmpvar_34 - global CONFIG_SPW_RMAPBUF2 - if {$tmpvar_34 == "64"} then {set CONFIG_SPW_RMAPBUF2 1} else {set CONFIG_SPW_RMAPBUF2 0} - global CONFIG_SPW_RMAPBUF4 - if {$tmpvar_34 == "128"} then {set CONFIG_SPW_RMAPBUF4 1} else {set CONFIG_SPW_RMAPBUF4 0} - global CONFIG_SPW_RMAPBUF6 - if {$tmpvar_34 == "192"} then {set CONFIG_SPW_RMAPBUF6 1} else {set CONFIG_SPW_RMAPBUF6 0} - global CONFIG_SPW_RMAPBUF8 - if {$tmpvar_34 == "256"} then {set CONFIG_SPW_RMAPBUF8 1} else {set CONFIG_SPW_RMAPBUF8 0} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RMAPCRC [expr $CONFIG_SPW_RMAPCRC&15]} else {set CONFIG_SPW_RMAPCRC [expr $CONFIG_SPW_RMAPCRC|16]} - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_RXUNAL [expr $CONFIG_SPW_RXUNAL&15]} else {set CONFIG_SPW_RXUNAL [expr $CONFIG_SPW_RXUNAL|16]} - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_FT [expr $CONFIG_SPW_FT&15]} else {set CONFIG_SPW_FT [expr $CONFIG_SPW_FT|16]} - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then { - set CONFIG_SPW_NETLIST [expr $CONFIG_SPW_NETLIST&15]} else {set CONFIG_SPW_NETLIST [expr $CONFIG_SPW_NETLIST|16]} - global tmpvar_35 - global CONFIG_SPW_GRSPW1 - if {$tmpvar_35 == "1"} then {set CONFIG_SPW_GRSPW1 1} else {set CONFIG_SPW_GRSPW1 0} - global CONFIG_SPW_GRSPW2 - if {$tmpvar_35 == "2"} then {set CONFIG_SPW_GRSPW2 1} else {set CONFIG_SPW_GRSPW2 0} - global CONFIG_SPW_DMACHAN - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {validate_int CONFIG_SPW_DMACHAN "$CONFIG_SPW_DMACHAN" 1} - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {validate_int CONFIG_SPW_PORTS "$CONFIG_SPW_PORTS" 1} - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - set CONFIG_SPW_RTSAME [expr $CONFIG_SPW_RTSAME&15]} else {set CONFIG_SPW_RTSAME [expr $CONFIG_SPW_RTSAME|16]} - global tmpvar_36 - global CONFIG_SPW_RX_SDR - if {$tmpvar_36 == "SDR"} then {set CONFIG_SPW_RX_SDR 1} else {set CONFIG_SPW_RX_SDR 0} - global CONFIG_SPW_RX_DDR - if {$tmpvar_36 == "DDR"} then {set CONFIG_SPW_RX_DDR 1} else {set CONFIG_SPW_RX_DDR 0} - global CONFIG_SPW_RX_XOR - if {$tmpvar_36 == "Xor"} then {set CONFIG_SPW_RX_XOR 1} else {set CONFIG_SPW_RX_XOR 0} - global CONFIG_SPW_RX_AFLEX - if {$tmpvar_36 == "Aeroflex"} then {set CONFIG_SPW_RX_AFLEX 1} else {set CONFIG_SPW_RX_AFLEX 0} - global tmpvar_37 - global CONFIG_SPW_TX_SDR - if {$tmpvar_37 == "SDR"} then {set CONFIG_SPW_TX_SDR 1} else {set CONFIG_SPW_TX_SDR 0} - global CONFIG_SPW_TX_DDR - if {$tmpvar_37 == "DDR"} then {set CONFIG_SPW_TX_DDR 1} else {set CONFIG_SPW_TX_DDR 0} - global CONFIG_SPW_TX_AFLEX - if {$tmpvar_37 == "Aeroflex"} then {set CONFIG_SPW_TX_AFLEX 1} else {set CONFIG_SPW_TX_AFLEX 0} -} - - -proc menu23 {w title} { - set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 23} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 23]] - message $w.m -width 400 -aspect 300 -text \ - "UARTs, timers and irq control " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "UARTs, timers and irq control " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 23; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 23; catch {destroy .menu13}; unregister_active 13; menu24 .menu24 \"$title\"" - frame $w.f - button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - bind all $nextscript - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 23 0 "Enable console UART " CONFIG_UART1_ENABLE - global tmpvar_38 - minimenu $w.config.f 23 1 "UART1 FIFO depth" tmpvar_38 CONFIG_UA1_FIFO1 - menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"UART1 FIFO depth\"" - $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_38 -value "1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_38 -value "2" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_38 -value "4" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_38 -value "8" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_38 -value "16" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_38 -value "32" -command "update_active" - menusplit $w $w.config.f.x1.x.menu 6 - bool $w.config.f 23 2 "Enable secondary UART " CONFIG_UART2_ENABLE - global tmpvar_39 - minimenu $w.config.f 23 3 "UART2 FIFO depth" tmpvar_39 CONFIG_UA2_FIFO1 - menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"UART2 FIFO depth\"" - $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_39 -value "1" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_39 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_39 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_39 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_39 -value "16" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_39 -value "32" -command "update_active" - menusplit $w $w.config.f.x3.x.menu 6 - bool $w.config.f 23 4 "Enable LEON3 interrupt controller " CONFIG_IRQ3_ENABLE - bool $w.config.f 23 5 "Enable secondary interrupts " CONFIG_IRQ3_SEC - int $w.config.f 23 6 "Secondary interrupt number (1 - 15) " CONFIG_IRQ3_NSEC - bool $w.config.f 23 7 "Enable Timer Unit " CONFIG_GPT_ENABLE - int $w.config.f 23 8 "Number of timers (1 - 7) " CONFIG_GPT_NTIM - int $w.config.f 23 9 "Scaler width (2 - 16) " CONFIG_GPT_SW - int $w.config.f 23 10 "Timer width (2 - 32) " CONFIG_GPT_TW - int $w.config.f 23 11 "Timer unit interrupt " CONFIG_GPT_IRQ - bool $w.config.f 23 12 "Separate interrupts " CONFIG_GPT_SEPIRQ - bool $w.config.f 23 13 "Watchdog enable " CONFIG_GPT_WDOGEN - hex $w.config.f 23 14 "Initial watchdog time-out value " CONFIG_GPT_WDOG - bool $w.config.f 23 15 "Enable generic GPIO port " CONFIG_GRGPIO_ENABLE - int $w.config.f 23 16 "GPIO width " CONFIG_GRGPIO_WIDTH - hex $w.config.f 23 17 "GPIO interrupt mask " CONFIG_GRGPIO_IMASK - - - - focus $w - update_active - global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu23 {} { - global CONFIG_UART1_ENABLE - if {($CONFIG_UART1_ENABLE == 1)} then {configure_entry .menu23.config.f.x1 normal {x l}} else {configure_entry .menu23.config.f.x1 disabled {x l}} - global CONFIG_UART2_ENABLE - if {($CONFIG_UART2_ENABLE == 1)} then {configure_entry .menu23.config.f.x3 normal {x l}} else {configure_entry .menu23.config.f.x3 disabled {x l}} - global CONFIG_IRQ3_ENABLE - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then { - configure_entry .menu23.config.f.x5 normal {n l y}} else {configure_entry .menu23.config.f.x5 disabled {y n l}} - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {.menu23.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x6.l configure -state normal; } else {.menu23.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x6.l configure -state disabled} - global CONFIG_GPT_ENABLE - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x8.l configure -state normal; } else {.menu23.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x8.l configure -state disabled} - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x9.l configure -state normal; } else {.menu23.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x9.l configure -state disabled} - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x10.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x10.l configure -state normal; } else {.menu23.config.f.x10.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x10.l configure -state disabled} - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {.menu23.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x11.l configure -state normal; } else {.menu23.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x11.l configure -state disabled} - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then { - configure_entry .menu23.config.f.x12 normal {n l y}} else {configure_entry .menu23.config.f.x12 disabled {y n l}} - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then { - configure_entry .menu23.config.f.x13 normal {n l y}} else {configure_entry .menu23.config.f.x13 disabled {y n l}} - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {.menu23.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x14.l configure -state normal; } else {.menu23.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x14.l configure -state disabled} - global CONFIG_GRGPIO_ENABLE - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu23.config.f.x16.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x16.l configure -state normal; } else {.menu23.config.f.x16.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x16.l configure -state disabled} - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu23.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x17.l configure -state normal; } else {.menu23.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x17.l configure -state disabled} -} - - -proc update_define_menu23 {} { - update_define_mainmenu - global CONFIG_MODULES - global tmpvar_38 - global CONFIG_UA1_FIFO1 - if {$tmpvar_38 == "1"} then {set CONFIG_UA1_FIFO1 1} else {set CONFIG_UA1_FIFO1 0} - global CONFIG_UA1_FIFO2 - if {$tmpvar_38 == "2"} then {set CONFIG_UA1_FIFO2 1} else {set CONFIG_UA1_FIFO2 0} - global CONFIG_UA1_FIFO4 - if {$tmpvar_38 == "4"} then {set CONFIG_UA1_FIFO4 1} else {set CONFIG_UA1_FIFO4 0} - global CONFIG_UA1_FIFO8 - if {$tmpvar_38 == "8"} then {set CONFIG_UA1_FIFO8 1} else {set CONFIG_UA1_FIFO8 0} - global CONFIG_UA1_FIFO16 - if {$tmpvar_38 == "16"} then {set CONFIG_UA1_FIFO16 1} else {set CONFIG_UA1_FIFO16 0} - global CONFIG_UA1_FIFO32 - if {$tmpvar_38 == "32"} then {set CONFIG_UA1_FIFO32 1} else {set CONFIG_UA1_FIFO32 0} - global tmpvar_39 - global CONFIG_UA2_FIFO1 - if {$tmpvar_39 == "1"} then {set CONFIG_UA2_FIFO1 1} else {set CONFIG_UA2_FIFO1 0} - global CONFIG_UA2_FIFO2 - if {$tmpvar_39 == "2"} then {set CONFIG_UA2_FIFO2 1} else {set CONFIG_UA2_FIFO2 0} - global CONFIG_UA2_FIFO4 - if {$tmpvar_39 == "4"} then {set CONFIG_UA2_FIFO4 1} else {set CONFIG_UA2_FIFO4 0} - global CONFIG_UA2_FIFO8 - if {$tmpvar_39 == "8"} then {set CONFIG_UA2_FIFO8 1} else {set CONFIG_UA2_FIFO8 0} - global CONFIG_UA2_FIFO16 - if {$tmpvar_39 == "16"} then {set CONFIG_UA2_FIFO16 1} else {set CONFIG_UA2_FIFO16 0} - global CONFIG_UA2_FIFO32 - if {$tmpvar_39 == "32"} then {set CONFIG_UA2_FIFO32 1} else {set CONFIG_UA2_FIFO32 0} - global CONFIG_IRQ3_ENABLE - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then { - set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC&15]} else {set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC|16]} - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {validate_int CONFIG_IRQ3_NSEC "$CONFIG_IRQ3_NSEC" 12} - global CONFIG_GPT_ENABLE - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_NTIM "$CONFIG_GPT_NTIM" 2} - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_SW "$CONFIG_GPT_SW" 8} - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_TW "$CONFIG_GPT_TW" 32} - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_IRQ "$CONFIG_GPT_IRQ" 8} - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then { - set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ&15]} else {set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ|16]} - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then { - set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN&15]} else {set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN|16]} - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {validate_hex CONFIG_GPT_WDOG "$CONFIG_GPT_WDOG" FFFF} - global CONFIG_GRGPIO_ENABLE - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_int CONFIG_GRGPIO_WIDTH "$CONFIG_GRGPIO_WIDTH" 8} - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_hex CONFIG_GRGPIO_IMASK "$CONFIG_GRGPIO_IMASK" 0000} -} - - -menu_option menu24 24 "VHDL Debugging " -proc menu24 {w title} { - set oldFocus [focus] - catch {destroy $w; unregister_active 24} - toplevel $w -class Dialog - wm withdraw $w - global active_menus - set active_menus [lsort -integer [linsert $active_menus end 24]] - message $w.m -width 400 -aspect 300 -text \ - "VHDL Debugging " -relief raised - pack $w.m -pady 10 -side top -padx 10 - wm title $w "VHDL Debugging " - - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 24; break" - set nextscript "catch {focus $oldFocus}; menu25 .menu25 \"$title\"" - frame $w.f - button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24" - button $w.f.next -text "Next" -underline 0\ - -width 15 -command $nextscript - $w.f.next configure -state disabled - bind all "puts \"no more menus\" " - button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\";break" - pack $w.f.back $w.f.next $w.f.prev -side left -expand on - pack $w.f -pady 10 -side bottom -anchor w -fill x - frame $w.topline -relief ridge -borderwidth 2 -height 2 - pack $w.topline -side top -fill x - - frame $w.botline -relief ridge -borderwidth 2 -height 2 - pack $w.botline -side bottom -fill x - - frame $w.config - pack $w.config -fill y -expand on - - scrollbar $w.config.vscroll -command "$w.config.canvas yview" - pack $w.config.vscroll -side right -fill y - - canvas $w.config.canvas -height 1\ - -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ - -width [expr [winfo screenwidth .] * 1 / 2] - frame $w.config.f - bind $w "$w.config.canvas yview scroll 1 unit;break;" - bind $w "$w.config.canvas yview scroll -1 unit;break;" - bind $w "$w.config.canvas yview scroll 1 page;break;" - bind $w "$w.config.canvas yview scroll -1 page;break;" - bind $w "$w.config.canvas yview moveto 0;break;" - bind $w "$w.config.canvas yview moveto 1 ;break;" - pack $w.config.canvas -side right -fill y - - - bool $w.config.f 24 0 "Accelerated UART tracing " CONFIG_DEBUG_UART - - - - focus $w - update_active - global winx; global winy - set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] - if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} - update idletasks - if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f - - $w.config.canvas configure \ - -width [expr [winfo reqwidth $w.config.f] + 1]\ - -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ - [expr [winfo reqheight $w.config.f] + 1]" - - set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] - set scry [expr [winfo screenh $w] / 2] - set maxy [expr [winfo screenh $w] * 3 / 4] - set canvtotal [expr [winfo reqh $w.config.f] + 2] - if [expr $winy + $canvtotal < $maxy] { - $w.config.canvas configure -height $canvtotal - } else { - $w.config.canvas configure -height [expr $scry - $winy] - } - } - update idletasks - if {[winfo exists $w]} then { - wm maxsize $w [winfo width $w] [winfo screenheight $w] - wm minsize $w [winfo width $w] 100 - - wm deiconify $w -} -} - -proc update_menu24 {} { -} - - -proc update_define_menu24 {} { - update_define_mainmenu - global CONFIG_MODULES -} - - -proc update_mainmenu {} { -} - - -set tmpvar_0 "(not set)" -set CONFIG_SYN_INFERRED 0 -set CONFIG_SYN_STRATIX 0 -set CONFIG_SYN_STRATIXII 0 -set CONFIG_SYN_STRATIXIII 0 -set CONFIG_SYN_CYCLONEIII 0 -set CONFIG_SYN_ALTERA 0 -set CONFIG_SYN_AXCEL 0 -set CONFIG_SYN_PROASIC 0 -set CONFIG_SYN_PROASICPLUS 0 -set CONFIG_SYN_PROASIC3 0 -set CONFIG_SYN_UT025CRH 0 -set CONFIG_SYN_ATC18 0 -set CONFIG_SYN_ATC18RHA 0 -set CONFIG_SYN_CUSTOM1 0 -set CONFIG_SYN_EASIC90 0 -set CONFIG_SYN_IHP25 0 -set CONFIG_SYN_IHP25RH 0 -set CONFIG_SYN_LATTICE 0 -set CONFIG_SYN_ECLIPSE 0 -set CONFIG_SYN_PEREGRINE 0 -set CONFIG_SYN_RH_LIB18T 0 -set CONFIG_SYN_RHUMC 0 -set CONFIG_SYN_SMIC13 0 -set CONFIG_SYN_SPARTAN2 0 -set CONFIG_SYN_SPARTAN3 0 -set CONFIG_SYN_SPARTAN3E 0 -set CONFIG_SYN_VIRTEX 0 -set CONFIG_SYN_VIRTEXE 0 -set CONFIG_SYN_VIRTEX2 0 -set CONFIG_SYN_VIRTEX4 0 -set CONFIG_SYN_VIRTEX5 0 -set CONFIG_SYN_UMC 0 -set CONFIG_SYN_TSMC90 0 -set tmpvar_1 "(not set)" -set CONFIG_MEM_INFERRED 0 -set CONFIG_MEM_UMC 0 -set CONFIG_MEM_RHUMC 0 -set CONFIG_MEM_ARTISAN 0 -set CONFIG_MEM_CUSTOM1 0 -set CONFIG_MEM_VIRAGE 0 -set CONFIG_MEM_VIRAGE90 0 -set CONFIG_SYN_INFER_RAM 0 -set CONFIG_SYN_INFER_PADS 0 -set CONFIG_SYN_NO_ASYNC 0 -set CONFIG_SYN_SCAN 0 -set tmpvar_2 "(not set)" -set CONFIG_CLK_INFERRED 0 -set CONFIG_CLK_HCLKBUF 0 -set CONFIG_CLK_ALTDLL 0 -set CONFIG_CLK_LATDLL 0 -set CONFIG_CLK_PRO3PLL 0 -set CONFIG_CLK_LIB18T 0 -set CONFIG_CLK_RHUMC 0 -set CONFIG_CLK_CLKDLL 0 -set CONFIG_CLK_DCM 0 -set CONFIG_CLK_MUL 2 -set CONFIG_CLK_DIV 2 -set CONFIG_OCLK_DIV 2 -set CONFIG_PCI_CLKDLL 0 -set CONFIG_CLK_NOFB 0 -set CONFIG_PCI_SYSCLK 0 -set CONFIG_LEON3 0 -set CONFIG_PROC_NUM 1 -set CONFIG_IU_NWINDOWS 8 -set CONFIG_IU_V8MULDIV 0 -set tmpvar_3 "(not set)" -set CONFIG_IU_MUL_LATENCY_2 0 -set CONFIG_IU_MUL_LATENCY_4 0 -set CONFIG_IU_MUL_LATENCY_5 0 -set CONFIG_IU_MUL_MAC 0 -set CONFIG_IU_SVT 0 -set CONFIG_IU_LDELAY 1 -set CONFIG_IU_WATCHPOINTS 0 -set CONFIG_PWD 0 -set CONFIG_IU_RSTADDR 00000 -set CONFIG_FPU_ENABLE 0 -set tmpvar_4 "(not set)" -set CONFIG_FPU_GRFPU 0 -set CONFIG_FPU_GRFPULITE 0 -set CONFIG_FPU_MEIKO 0 -set tmpvar_5 "(not set)" -set CONFIG_FPU_GRFPU_INFMUL 0 -set CONFIG_FPU_GRFPU_DWMUL 0 -set CONFIG_FPU_GRFPU_MODGEN 0 -set tmpvar_6 "(not set)" -set CONFIG_FPU_GRFPC0 0 -set CONFIG_FPU_GRFPC1 0 -set CONFIG_FPU_GRFPC2 0 -set CONFIG_FPU_NETLIST 0 -set CONFIG_ICACHE_ENABLE 0 -set tmpvar_7 "(not set)" -set CONFIG_ICACHE_ASSO1 0 -set CONFIG_ICACHE_ASSO2 0 -set CONFIG_ICACHE_ASSO3 0 -set CONFIG_ICACHE_ASSO4 0 -set tmpvar_8 "(not set)" -set CONFIG_ICACHE_SZ1 0 -set CONFIG_ICACHE_SZ2 0 -set CONFIG_ICACHE_SZ4 0 -set CONFIG_ICACHE_SZ8 0 -set CONFIG_ICACHE_SZ16 0 -set CONFIG_ICACHE_SZ32 0 -set CONFIG_ICACHE_SZ64 0 -set CONFIG_ICACHE_SZ128 0 -set CONFIG_ICACHE_SZ256 0 -set tmpvar_9 "(not set)" -set CONFIG_ICACHE_LZ16 0 -set CONFIG_ICACHE_LZ32 0 -set tmpvar_10 "(not set)" -set CONFIG_ICACHE_ALGORND 0 -set CONFIG_ICACHE_ALGOLRR 0 -set CONFIG_ICACHE_ALGOLRU 0 -set CONFIG_ICACHE_LOCK 0 -set CONFIG_ICACHE_LRAM 0 -set tmpvar_11 "(not set)" -set CONFIG_ICACHE_LRAM_SZ1 0 -set CONFIG_ICACHE_LRAM_SZ2 0 -set CONFIG_ICACHE_LRAM_SZ4 0 -set CONFIG_ICACHE_LRAM_SZ8 0 -set CONFIG_ICACHE_LRAM_SZ16 0 -set CONFIG_ICACHE_LRAM_SZ32 0 -set CONFIG_ICACHE_LRAM_SZ64 0 -set CONFIG_ICACHE_LRAM_SZ128 0 -set CONFIG_ICACHE_LRAM_SZ256 0 -set CONFIG_ICACHE_LRSTART 8e -set CONFIG_DCACHE_ENABLE 0 -set tmpvar_12 "(not set)" -set CONFIG_DCACHE_ASSO1 0 -set CONFIG_DCACHE_ASSO2 0 -set CONFIG_DCACHE_ASSO3 0 -set CONFIG_DCACHE_ASSO4 0 -set tmpvar_13 "(not set)" -set CONFIG_DCACHE_SZ1 0 -set CONFIG_DCACHE_SZ2 0 -set CONFIG_DCACHE_SZ4 0 -set CONFIG_DCACHE_SZ8 0 -set CONFIG_DCACHE_SZ16 0 -set CONFIG_DCACHE_SZ32 0 -set CONFIG_DCACHE_SZ64 0 -set CONFIG_DCACHE_SZ128 0 -set CONFIG_DCACHE_SZ256 0 -set tmpvar_14 "(not set)" -set CONFIG_DCACHE_LZ16 0 -set CONFIG_DCACHE_LZ32 0 -set tmpvar_15 "(not set)" -set CONFIG_DCACHE_ALGORND 0 -set CONFIG_DCACHE_ALGOLRR 0 -set CONFIG_DCACHE_ALGOLRU 0 -set CONFIG_DCACHE_LOCK 0 -set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 -set CONFIG_DCACHE_SNOOP_SEPTAG 0 -set CONFIG_CACHE_FIXED 0 -set CONFIG_DCACHE_LRAM 0 -set tmpvar_16 "(not set)" -set CONFIG_DCACHE_LRAM_SZ1 0 -set CONFIG_DCACHE_LRAM_SZ2 0 -set CONFIG_DCACHE_LRAM_SZ4 0 -set CONFIG_DCACHE_LRAM_SZ8 0 -set CONFIG_DCACHE_LRAM_SZ16 0 -set CONFIG_DCACHE_LRAM_SZ32 0 -set CONFIG_DCACHE_LRAM_SZ64 0 -set CONFIG_DCACHE_LRAM_SZ128 0 -set CONFIG_DCACHE_LRAM_SZ256 0 -set CONFIG_DCACHE_LRSTART 8f -set CONFIG_MMU_ENABLE 0 -set tmpvar_17 "(not set)" -set CONFIG_MMU_COMBINED 0 -set CONFIG_MMU_SPLIT 0 -set tmpvar_18 "(not set)" -set CONFIG_MMU_REPARRAY 0 -set CONFIG_MMU_REPINCREMENT 0 -set tmpvar_19 "(not set)" -set CONFIG_MMU_I2 0 -set CONFIG_MMU_I4 0 -set CONFIG_MMU_I8 0 -set CONFIG_MMU_I16 0 -set CONFIG_MMU_I32 0 -set tmpvar_20 "(not set)" -set CONFIG_MMU_D2 0 -set CONFIG_MMU_D4 0 -set CONFIG_MMU_D8 0 -set CONFIG_MMU_D16 0 -set CONFIG_MMU_D32 0 -set CONFIG_MMU_FASTWB 0 -set tmpvar_21 "(not set)" -set CONFIG_MMU_PAGE_4K 0 -set CONFIG_MMU_PAGE_8K 0 -set CONFIG_MMU_PAGE_16K 0 -set CONFIG_MMU_PAGE_32K 0 -set CONFIG_MMU_PAGE_PROG 0 -set CONFIG_DSU_ENABLE 0 -set CONFIG_DSU_ITRACE 0 -set tmpvar_22 "(not set)" -set CONFIG_DSU_ITRACESZ1 0 -set CONFIG_DSU_ITRACESZ2 0 -set CONFIG_DSU_ITRACESZ4 0 -set CONFIG_DSU_ITRACESZ8 0 -set CONFIG_DSU_ITRACESZ16 0 -set CONFIG_DSU_ATRACE 0 -set tmpvar_23 "(not set)" -set CONFIG_DSU_ATRACESZ1 0 -set CONFIG_DSU_ATRACESZ2 0 -set CONFIG_DSU_ATRACESZ4 0 -set CONFIG_DSU_ATRACESZ8 0 -set CONFIG_DSU_ATRACESZ16 0 -set CONFIG_IU_DISAS 0 -set CONFIG_IU_DISAS_NET 0 -set CONFIG_DEBUG_PC32 0 -set CONFIG_AHB_DEFMST 0 -set CONFIG_AHB_RROBIN 0 -set CONFIG_AHB_SPLIT 0 -set CONFIG_AHB_IOADDR FFF -set CONFIG_APB_HADDR 800 -set CONFIG_AHB_MON 0 -set CONFIG_AHB_MONERR 0 -set CONFIG_AHB_MONWAR 0 -set CONFIG_DSU_UART 0 -set CONFIG_DSU_JTAG 0 -set CONFIG_DSU_ETH 0 -set tmpvar_25 "(not set)" -set CONFIG_DSU_ETHSZ1 0 -set CONFIG_DSU_ETHSZ2 0 -set CONFIG_DSU_ETHSZ4 0 -set CONFIG_DSU_ETHSZ8 0 -set CONFIG_DSU_ETHSZ16 0 -set CONFIG_DSU_IPMSB C0A8 -set CONFIG_DSU_IPLSB 0033 -set CONFIG_DSU_ETHMSB 020000 -set CONFIG_DSU_ETHLSB 000000 -set CONFIG_DSU_ETH_PROG 0 -set CONFIG_SRCTRL 0 -set CONFIG_SRCTRL_8BIT 0 -set CONFIG_SRCTRL_PROMWS 3 -set CONFIG_SRCTRL_RAMWS 0 -set CONFIG_SRCTRL_IOWS 0 -set CONFIG_SRCTRL_RMW 0 -set tmpvar_26 "(not set)" -set CONFIG_SRCTRL_SRBANKS1 0 -set CONFIG_SRCTRL_SRBANKS2 0 -set CONFIG_SRCTRL_SRBANKS3 0 -set CONFIG_SRCTRL_SRBANKS4 0 -set CONFIG_SRCTRL_SRBANKS5 0 -set tmpvar_27 "(not set)" -set CONFIG_SRCTRL_BANKSZ0 0 -set CONFIG_SRCTRL_BANKSZ1 0 -set CONFIG_SRCTRL_BANKSZ2 0 -set CONFIG_SRCTRL_BANKSZ3 0 -set CONFIG_SRCTRL_BANKSZ4 0 -set CONFIG_SRCTRL_BANKSZ5 0 -set CONFIG_SRCTRL_BANKSZ6 0 -set CONFIG_SRCTRL_BANKSZ7 0 -set CONFIG_SRCTRL_BANKSZ8 0 -set CONFIG_SRCTRL_BANKSZ9 0 -set CONFIG_SRCTRL_BANKSZ10 0 -set CONFIG_SRCTRL_BANKSZ11 0 -set CONFIG_SRCTRL_BANKSZ12 0 -set CONFIG_SRCTRL_BANKSZ13 0 -set CONFIG_SRCTRL_ROMASEL 19 -set CONFIG_MCTRL_LEON2 0 -set CONFIG_MCTRL_8BIT 0 -set CONFIG_MCTRL_16BIT 0 -set CONFIG_MCTRL_5CS 0 -set CONFIG_MCTRL_SDRAM 0 -set CONFIG_MCTRL_SDRAM_SEPBUS 0 -set CONFIG_MCTRL_SDRAM_BUS64 0 -set CONFIG_MCTRL_SDRAM_INVCLK 0 -set CONFIG_MCTRL_PAGE 0 -set CONFIG_MCTRL_PROGPAGE 0 -set CONFIG_SDCTRL 0 -set CONFIG_SDCTRL_BUS64 0 -set CONFIG_SDCTRL_INVCLK 0 -set CONFIG_SDCTRL_PAGE 0 -set CONFIG_SDCTRL_PROGPAGE 0 -set CONFIG_AHBROM_ENABLE 0 -set CONFIG_AHBROM_START 000 -set CONFIG_AHBROM_PIPE 0 -set CONFIG_AHBRAM_ENABLE 0 -set tmpvar_28 "(not set)" -set CONFIG_AHBRAM_SZ1 0 -set CONFIG_AHBRAM_SZ2 0 -set CONFIG_AHBRAM_SZ4 0 -set CONFIG_AHBRAM_SZ8 0 -set CONFIG_AHBRAM_SZ16 0 -set CONFIG_AHBRAM_SZ32 0 -set CONFIG_AHBRAM_SZ64 0 -set CONFIG_AHBRAM_START A00 -set CONFIG_GRETH_ENABLE 0 -set CONFIG_GRETH_GIGA 0 -set tmpvar_29 "(not set)" -set CONFIG_GRETH_FIFO4 0 -set CONFIG_GRETH_FIFO8 0 -set CONFIG_GRETH_FIFO16 0 -set CONFIG_GRETH_FIFO32 0 -set CONFIG_GRETH_FIFO64 0 -set CONFIG_CAN_ENABLE 0 -set CONFIG_CANIO C00 -set CONFIG_CANIRQ 13 -set CONFIG_CANLOOP 0 -set CONFIG_CAN_SYNCRST 0 -set CONFIG_CAN_FT 0 -set CONFIG_PCI_SIMPLE_TARGET 0 -set CONFIG_PCI_MASTER_TARGET 0 -set CONFIG_PCI_MASTER_TARGET_DMA 0 -set CONFIG_PCI_VENDORID 1AC8 -set CONFIG_PCI_DEVICEID 0054 -set tmpvar_30 "(not set)" -set CONFIG_PCI_FIFO0 0 -set CONFIG_PCI_FIFO8 0 -set CONFIG_PCI_FIFO16 0 -set CONFIG_PCI_FIFO32 0 -set CONFIG_PCI_FIFO64 0 -set CONFIG_PCI_FIFO128 0 -set CONFIG_PCI_HADDR E00 -set CONFIG_PCI_ARBITER 0 -set CONFIG_PCI_ARBITER_APB 0 -set CONFIG_PCI_ARBITER_NREQ 4 -set CONFIG_PCI_TRACE 0 -set tmpvar_31 "(not set)" -set CONFIG_PCI_TRACE256 0 -set CONFIG_PCI_TRACE512 0 -set CONFIG_PCI_TRACE1024 0 -set CONFIG_PCI_TRACE2048 0 -set CONFIG_PCI_TRACE4096 0 -set CONFIG_SPW_ENABLE 0 -set CONFIG_SPW_NUM 1 -set tmpvar_32 "(not set)" -set CONFIG_SPW_AHBFIFO4 0 -set CONFIG_SPW_AHBFIFO8 0 -set CONFIG_SPW_AHBFIFO16 0 -set CONFIG_SPW_AHBFIFO32 0 -set tmpvar_33 "(not set)" -set CONFIG_SPW_RXFIFO16 0 -set CONFIG_SPW_RXFIFO32 0 -set CONFIG_SPW_RXFIFO64 0 -set CONFIG_SPW_RMAP 0 -set tmpvar_34 "(not set)" -set CONFIG_SPW_RMAPBUF2 0 -set CONFIG_SPW_RMAPBUF4 0 -set CONFIG_SPW_RMAPBUF6 0 -set CONFIG_SPW_RMAPBUF8 0 -set CONFIG_SPW_RMAPCRC 0 -set CONFIG_SPW_RXUNAL 0 -set CONFIG_SPW_FT 0 -set CONFIG_SPW_NETLIST 0 -set tmpvar_35 "(not set)" -set CONFIG_SPW_GRSPW1 0 -set CONFIG_SPW_GRSPW2 0 -set CONFIG_SPW_DMACHAN 1 -set CONFIG_SPW_PORTS 1 -set CONFIG_SPW_RTSAME 0 -set tmpvar_36 "(not set)" -set CONFIG_SPW_RX_SDR 0 -set CONFIG_SPW_RX_DDR 0 -set CONFIG_SPW_RX_XOR 0 -set CONFIG_SPW_RX_AFLEX 0 -set tmpvar_37 "(not set)" -set CONFIG_SPW_TX_SDR 0 -set CONFIG_SPW_TX_DDR 0 -set CONFIG_SPW_TX_AFLEX 0 -set CONFIG_UART1_ENABLE 0 -set tmpvar_38 "(not set)" -set CONFIG_UA1_FIFO1 0 -set CONFIG_UA1_FIFO2 0 -set CONFIG_UA1_FIFO4 0 -set CONFIG_UA1_FIFO8 0 -set CONFIG_UA1_FIFO16 0 -set CONFIG_UA1_FIFO32 0 -set CONFIG_UART2_ENABLE 0 -set tmpvar_39 "(not set)" -set CONFIG_UA2_FIFO1 0 -set CONFIG_UA2_FIFO2 0 -set CONFIG_UA2_FIFO4 0 -set CONFIG_UA2_FIFO8 0 -set CONFIG_UA2_FIFO16 0 -set CONFIG_UA2_FIFO32 0 -set CONFIG_IRQ3_ENABLE 0 -set CONFIG_IRQ3_SEC 0 -set CONFIG_IRQ3_NSEC 12 -set CONFIG_GPT_ENABLE 0 -set CONFIG_GPT_NTIM 2 -set CONFIG_GPT_SW 8 -set CONFIG_GPT_TW 32 -set CONFIG_GPT_IRQ 8 -set CONFIG_GPT_SEPIRQ 0 -set CONFIG_GPT_WDOGEN 0 -set CONFIG_GPT_WDOG FFFF -set CONFIG_GRGPIO_ENABLE 0 -set CONFIG_GRGPIO_WIDTH 8 -set CONFIG_GRGPIO_IMASK 0000 -set CONFIG_DEBUG_UART 0 -set CONFIG_SYN_ARTISAN 4 -set CONFIG_PCI_ENABLE 4 -set CONFIG_HAS_SHARED_GRFPU 4 -set CONFIG_FPU_GRFPU_SH 4 -set CONFIG_LEON3FT_PRESENT 4 -set CONFIG_LEON3FT_EN 4 -set CONFIG_IUFT_NONE 4 -set CONFIG_IUFT_PAR 4 -set CONFIG_IUFT_DMR 4 -set CONFIG_IUFT_BCH 4 -set CONFIG_IUFT_TMR 4 -set CONFIG_FPUFT_EN 4 -set CONFIG_RF_ERRINJ 4 -set CONFIG_CACHE_FT_EN 4 -set CONFIG_CACHE_ERRINJ 4 -set CONFIG_LEON3_NETLIST 4 -set CONFIG_PCI_ACTEL 4 -set CONFIG_MODULES 4 -proc writeconfig {file1 file2} { - set cfg [open $file1 w] - set autocfg [open $file2 w] - set notmod 1 - set notset 0 - puts $cfg "#" - puts $cfg "# Automatically generated make config: don't edit" - puts $cfg "#" - puts $autocfg "/*" - puts $autocfg " * Automatically generated C config: don't edit" - puts $autocfg " */" - puts $autocfg "#define AUTOCONF_INCLUDED" - write_comment $cfg $autocfg "Synthesis " - global tmpvar_0 - - if { $tmpvar_0 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-Stratix" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-StratixII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-StratixIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-CycloneIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 0 [list $notmod] 2 } - if { $tmpvar_0 == "Altera-Others" } then { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Axcelerator" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Proasic" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-ProasicPlus" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 0 [list $notmod] 2 } - if { $tmpvar_0 == "Actel-Proasic3" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 0 [list $notmod] 2 } - if { $tmpvar_0 == "Aeroflex-UT025CRH" } then { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 0 [list $notmod] 2 } - if { $tmpvar_0 == "Atmel-ATC18" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 0 [list $notmod] 2 } - if { $tmpvar_0 == "Atmel-ATC18RHA" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 0 [list $notmod] 2 } - if { $tmpvar_0 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 0 [list $notmod] 2 } - if { $tmpvar_0 == "eASIC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 0 [list $notmod] 2 } - if { $tmpvar_0 == "IHP25" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 0 [list $notmod] 2 } - if { $tmpvar_0 == "IHP25RH" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 0 [list $notmod] 2 } - if { $tmpvar_0 == "Lattice-EC/ECP/XP" } then { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Quicklogic-Eclipse" } then { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Peregrine" } then { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 0 [list $notmod] 2 } - if { $tmpvar_0 == "RH-LIB18T" } then { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 0 [list $notmod] 2 } - if { $tmpvar_0 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_0 == "SMIC130" } then { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan2" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN2 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan3" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Spartan3E" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-VirtexE" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex2" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex4" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 0 [list $notmod] 2 } - if { $tmpvar_0 == "Xilinx-Virtex5" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 0 [list $notmod] 2 } - if { $tmpvar_0 == "UMC180" } then { write_tristate $cfg $autocfg CONFIG_SYN_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UMC 0 [list $notmod] 2 } - if { $tmpvar_0 == "TSMC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 0 [list $notmod] 2 } - global tmpvar_1 - global CONFIG_SYN_INFERRED - global CONFIG_SYN_CUSTOM1 - global CONFIG_SYN_ATC18 - global CONFIG_SYN_TSMC90 - global CONFIG_SYN_UMC - global CONFIG_SYN_RHUMC - global CONFIG_SYN_ARTISAN - if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_ARTISAN == 1)} then { - if { $tmpvar_1 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_1 == "UMC18" } then { write_tristate $cfg $autocfg CONFIG_MEM_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_UMC 0 [list $notmod] 2 } - if { $tmpvar_1 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_1 == "Artisan" } then { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 0 [list $notmod] 2 } - if { $tmpvar_1 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 0 [list $notmod] 2 } - if { $tmpvar_1 == "Virage" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 0 [list $notmod] 2 } - if { $tmpvar_1 == "Virage-TSMC90" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 0 [list $notmod] 2 }} - global CONFIG_SYN_INFER_RAM - if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_RAM $CONFIG_SYN_INFER_RAM [list $notmod] 2 } - global CONFIG_SYN_INFER_PADS - if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_PADS $CONFIG_SYN_INFER_PADS [list $notmod] 2 } - global CONFIG_SYN_NO_ASYNC - write_tristate $cfg $autocfg CONFIG_SYN_NO_ASYNC $CONFIG_SYN_NO_ASYNC [list $notmod] 2 - global CONFIG_SYN_SCAN - write_tristate $cfg $autocfg CONFIG_SYN_SCAN $CONFIG_SYN_SCAN [list $notmod] 2 - write_comment $cfg $autocfg "Clock generation" - global tmpvar_2 - - if { $tmpvar_2 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 0 [list $notmod] 2 } - if { $tmpvar_2 == "Actel-HCLKBUF" } then { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 0 [list $notmod] 2 } - if { $tmpvar_2 == "Altera-ALTPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Lattice-EXPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Proasic3-PLLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "RH-LIB18T-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 0 [list $notmod] 2 } - if { $tmpvar_2 == "DARE-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 0 [list $notmod] 2 } - if { $tmpvar_2 == "Xilinx-CLKDLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 0 [list $notmod] 2 } - if { $tmpvar_2 == "Xilinx-DCM" } then { write_tristate $cfg $autocfg CONFIG_CLK_DCM 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_DCM 0 [list $notmod] 2 } - global CONFIG_CLK_MUL - global CONFIG_CLK_DCM - global CONFIG_CLK_ALTDLL - global CONFIG_CLK_LATDLL - global CONFIG_CLK_PRO3PLL - global CONFIG_CLK_CLKDLL - global CONFIG_CLK_LIB18T - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_MUL $CONFIG_CLK_MUL $notmod } - global CONFIG_CLK_DIV - if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1)} then {write_int $cfg $autocfg CONFIG_CLK_DIV $CONFIG_CLK_DIV $notmod } - global CONFIG_OCLK_DIV - if {($CONFIG_CLK_PRO3PLL == 1)} then {write_int $cfg $autocfg CONFIG_OCLK_DIV $CONFIG_OCLK_DIV $notmod } - global CONFIG_PCI_CLKDLL - if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_CLKDLL $CONFIG_PCI_CLKDLL [list $notmod] 2 } - global CONFIG_CLK_NOFB - if {($CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_CLK_NOFB $CONFIG_CLK_NOFB [list $notmod] 2 } - global CONFIG_PCI_SYSCLK - global CONFIG_PCI_ENABLE - if {($CONFIG_PCI_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SYSCLK $CONFIG_PCI_SYSCLK [list $notmod] 2 } - global CONFIG_LEON3 - write_tristate $cfg $autocfg CONFIG_LEON3 $CONFIG_LEON3 [list $notmod] 2 - global CONFIG_PROC_NUM - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_PROC_NUM $CONFIG_PROC_NUM $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Processor "} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Integer unit "} - global CONFIG_IU_NWINDOWS - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS $CONFIG_IU_NWINDOWS $notmod } - global CONFIG_IU_V8MULDIV - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONFIG_IU_V8MULDIV [list $notmod] 2 } - global tmpvar_3 - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1)} then { - if { $tmpvar_3 == "2-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 0 [list $notmod] 2 } - if { $tmpvar_3 == "4-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 0 [list $notmod] 2 } - if { $tmpvar_3 == "5-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 0 [list $notmod] 2 }} - global CONFIG_IU_MUL_MAC - global CONFIG_IU_MUL_LATENCY_4 - global CONFIG_IU_MUL_LATENCY_5 - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_MAC $CONFIG_IU_MUL_MAC [list $notmod] 2 } - global CONFIG_IU_SVT - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONFIG_IU_SVT [list $notmod] 2 } - global CONFIG_IU_LDELAY - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY $CONFIG_IU_LDELAY $notmod } - global CONFIG_IU_WATCHPOINTS - if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS $CONFIG_IU_WATCHPOINTS $notmod } - global CONFIG_PWD - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONFIG_PWD [list $notmod] 2 } - global CONFIG_IU_RSTADDR - if {($CONFIG_LEON3 == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR $CONFIG_IU_RSTADDR $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Floating-point unit"} - global CONFIG_FPU_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONFIG_FPU_ENABLE [list $notmod] 2 } - global tmpvar_4 - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then { - if { $tmpvar_4 == "GRFPU" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 0 [list $notmod] 2 } - if { $tmpvar_4 == "GRFPU-LITE" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 0 [list $notmod] 2 } - if { $tmpvar_4 == "Meiko" } then { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 0 [list $notmod] 2 }} - global tmpvar_5 - global CONFIG_FPU_GRFPU - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then { - if { $tmpvar_5 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 0 [list $notmod] 2 } - if { $tmpvar_5 == "DW" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 0 [list $notmod] 2 } - if { $tmpvar_5 == "ModGen" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 0 [list $notmod] 2 }} - global tmpvar_6 - global CONFIG_FPU_GRFPULITE - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then { - if { $tmpvar_6 == "Simple" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 0 [list $notmod] 2 } - if { $tmpvar_6 == "Data-forwarding" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 0 [list $notmod] 2 } - if { $tmpvar_6 == "Non-blocking" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 0 [list $notmod] 2 }} - global CONFIG_FPU_NETLIST - if {($CONFIG_LEON3 == 1) && ($CONFIG_FPU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_NETLIST $CONFIG_FPU_NETLIST [list $notmod] 2 } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Cache system"} - global CONFIG_ICACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONFIG_ICACHE_ENABLE [list $notmod] 2 } - global tmpvar_7 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_7 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 0 [list $notmod] 2 } - if { $tmpvar_7 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 0 [list $notmod] 2 } - if { $tmpvar_7 == "3" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 0 [list $notmod] 2 } - if { $tmpvar_7 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 0 [list $notmod] 2 }} - global tmpvar_8 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_8 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 0 [list $notmod] 2 } - if { $tmpvar_8 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 0 [list $notmod] 2 } - if { $tmpvar_8 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 0 [list $notmod] 2 } - if { $tmpvar_8 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 0 [list $notmod] 2 } - if { $tmpvar_8 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 0 [list $notmod] 2 } - if { $tmpvar_8 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 0 [list $notmod] 2 } - if { $tmpvar_8 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 0 [list $notmod] 2 } - if { $tmpvar_8 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 0 [list $notmod] 2 } - if { $tmpvar_8 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 0 [list $notmod] 2 }} - global tmpvar_9 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { - if { $tmpvar_9 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 0 [list $notmod] 2 } - if { $tmpvar_9 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 0 [list $notmod] 2 }} - global tmpvar_10 - global CONFIG_ICACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { - if { $tmpvar_10 == "Random" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 0 [list $notmod] 2 } - if { $tmpvar_10 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 0 [list $notmod] 2 } - if { $tmpvar_10 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 0 [list $notmod] 2 }} - global CONFIG_ICACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONFIG_ICACHE_LOCK [list $notmod] 2 } - global CONFIG_ICACHE_LRAM - global CONFIG_MMU_ENABLE - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM $CONFIG_ICACHE_LRAM [list $notmod] 2 } - global tmpvar_11 - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then { - if { $tmpvar_11 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_11 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_11 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_11 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_11 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_11 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_11 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 0 [list $notmod] 2 } - if { $tmpvar_11 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 0 [list $notmod] 2 } - if { $tmpvar_11 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 0 [list $notmod] 2 }} - global CONFIG_ICACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_ICACHE_LRSTART $CONFIG_ICACHE_LRSTART $notmod } - global CONFIG_DCACHE_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONFIG_DCACHE_ENABLE [list $notmod] 2 } - global tmpvar_12 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_12 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 0 [list $notmod] 2 } - if { $tmpvar_12 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 0 [list $notmod] 2 } - if { $tmpvar_12 == "3" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 0 [list $notmod] 2 } - if { $tmpvar_12 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 0 [list $notmod] 2 }} - global tmpvar_13 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_13 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 0 [list $notmod] 2 } - if { $tmpvar_13 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 0 [list $notmod] 2 } - if { $tmpvar_13 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 0 [list $notmod] 2 } - if { $tmpvar_13 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 0 [list $notmod] 2 } - if { $tmpvar_13 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 0 [list $notmod] 2 } - if { $tmpvar_13 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 0 [list $notmod] 2 } - if { $tmpvar_13 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 0 [list $notmod] 2 } - if { $tmpvar_13 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 0 [list $notmod] 2 } - if { $tmpvar_13 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 0 [list $notmod] 2 }} - global tmpvar_14 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { - if { $tmpvar_14 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 0 [list $notmod] 2 } - if { $tmpvar_14 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 0 [list $notmod] 2 }} - global tmpvar_15 - global CONFIG_DCACHE_ASSO1 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { - if { $tmpvar_15 == "Random" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 0 [list $notmod] 2 } - if { $tmpvar_15 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 0 [list $notmod] 2 } - if { $tmpvar_15 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} - global CONFIG_DCACHE_LOCK - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } - global CONFIG_DCACHE_SNOOP_SEPTAG - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } - global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } - global CONFIG_DCACHE_LRAM - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } - global tmpvar_16 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then { - if { $tmpvar_16 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_16 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_16 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_16 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_16 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_16 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_16 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 0 [list $notmod] 2 } - if { $tmpvar_16 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 0 [list $notmod] 2 } - if { $tmpvar_16 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 0 [list $notmod] 2 }} - global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_DCACHE_LRSTART $CONFIG_DCACHE_LRSTART $notmod } - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "MMU"} - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONFIG_MMU_ENABLE [list $notmod] 2 } - global tmpvar_17 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_17 == "combined" } then { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 0 [list $notmod] 2 } - if { $tmpvar_17 == "split" } then { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 0 [list $notmod] 2 }} - global tmpvar_18 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 0 [list $notmod] 2 } - if { $tmpvar_18 == "Increment" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 0 [list $notmod] 2 }} - global tmpvar_19 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_19 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_I2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I2 0 [list $notmod] 2 } - if { $tmpvar_19 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_I4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I4 0 [list $notmod] 2 } - if { $tmpvar_19 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_I8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I8 0 [list $notmod] 2 } - if { $tmpvar_19 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_I16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I16 0 [list $notmod] 2 } - if { $tmpvar_19 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_I32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I32 0 [list $notmod] 2 }} - global tmpvar_20 - global CONFIG_MMU_SPLIT - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { - if { $tmpvar_20 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_D2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D2 0 [list $notmod] 2 } - if { $tmpvar_20 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_D4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D4 0 [list $notmod] 2 } - if { $tmpvar_20 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_D8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D8 0 [list $notmod] 2 } - if { $tmpvar_20 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_D16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D16 0 [list $notmod] 2 } - if { $tmpvar_20 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_D32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D32 0 [list $notmod] 2 }} - global CONFIG_MMU_FASTWB - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_FASTWB $CONFIG_MMU_FASTWB [list $notmod] 2 } - global tmpvar_21 - if {($CONFIG_LEON3 == 1) && ($CONFIG_MMU_ENABLE == 1)} then { - if { $tmpvar_21 == "4K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 0 [list $notmod] 2 } - if { $tmpvar_21 == "8K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 0 [list $notmod] 2 } - if { $tmpvar_21 == "16K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 0 [list $notmod] 2 } - if { $tmpvar_21 == "32K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 0 [list $notmod] 2 } - if { $tmpvar_21 == "Programmable" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 0 [list $notmod] 2 }} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Debug Support Unit "} - global CONFIG_DSU_ENABLE - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONFIG_DSU_ENABLE [list $notmod] 2 } - global CONFIG_DSU_ITRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACE $CONFIG_DSU_ITRACE [list $notmod] 2 } - global tmpvar_22 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then { - if { $tmpvar_22 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 0 [list $notmod] 2 } - if { $tmpvar_22 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 0 [list $notmod] 2 } - if { $tmpvar_22 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 0 [list $notmod] 2 } - if { $tmpvar_22 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 0 [list $notmod] 2 } - if { $tmpvar_22 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 0 [list $notmod] 2 }} - global CONFIG_DSU_ATRACE - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ATRACE $CONFIG_DSU_ATRACE [list $notmod] 2 } - global tmpvar_23 - if {($CONFIG_LEON3 == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then { - if { $tmpvar_23 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 0 [list $notmod] 2 } - if { $tmpvar_23 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 0 [list $notmod] 2 } - if { $tmpvar_23 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 0 [list $notmod] 2 } - if { $tmpvar_23 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 0 [list $notmod] 2 } - if { $tmpvar_23 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 0 [list $notmod] 2 }} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Fault-tolerance "} - if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "VHDL debug settings "} - global CONFIG_IU_DISAS - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS $CONFIG_IU_DISAS [list $notmod] 2 } - global CONFIG_IU_DISAS_NET - if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS_NET $CONFIG_IU_DISAS_NET [list $notmod] 2 } - global CONFIG_DEBUG_PC32 - if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DEBUG_PC32 $CONFIG_DEBUG_PC32 [list $notmod] 2 } - write_comment $cfg $autocfg "AMBA configuration" - global CONFIG_AHB_DEFMST - write_int $cfg $autocfg CONFIG_AHB_DEFMST $CONFIG_AHB_DEFMST $notmod - global CONFIG_AHB_RROBIN - write_tristate $cfg $autocfg CONFIG_AHB_RROBIN $CONFIG_AHB_RROBIN [list $notmod] 2 - global CONFIG_AHB_SPLIT - write_tristate $cfg $autocfg CONFIG_AHB_SPLIT $CONFIG_AHB_SPLIT [list $notmod] 2 - global CONFIG_AHB_IOADDR - write_hex $cfg $autocfg CONFIG_AHB_IOADDR $CONFIG_AHB_IOADDR $notmod - global CONFIG_APB_HADDR - write_hex $cfg $autocfg CONFIG_APB_HADDR $CONFIG_APB_HADDR $notmod - global CONFIG_AHB_MON - write_tristate $cfg $autocfg CONFIG_AHB_MON $CONFIG_AHB_MON [list $notmod] 2 - global CONFIG_AHB_MONERR - if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONERR $CONFIG_AHB_MONERR [list $notmod] 2 } - global CONFIG_AHB_MONWAR - if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONWAR $CONFIG_AHB_MONWAR [list $notmod] 2 } - write_comment $cfg $autocfg "Debug Link " - global CONFIG_DSU_UART - write_tristate $cfg $autocfg CONFIG_DSU_UART $CONFIG_DSU_UART [list $notmod] 2 - global CONFIG_DSU_JTAG - write_tristate $cfg $autocfg CONFIG_DSU_JTAG $CONFIG_DSU_JTAG [list $notmod] 2 - global CONFIG_DSU_ETH - global CONFIG_GRETH_ENABLE - if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH $CONFIG_DSU_ETH [list $notmod] 2 } - global tmpvar_25 - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { - if { $tmpvar_25 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 0 [list $notmod] 2 } - if { $tmpvar_25 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 0 [list $notmod] 2 } - if { $tmpvar_25 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 0 [list $notmod] 2 } - if { $tmpvar_25 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 0 [list $notmod] 2 } - if { $tmpvar_25 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 0 [list $notmod] 2 }} - global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPMSB $CONFIG_DSU_IPMSB $notmod } - global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPLSB $CONFIG_DSU_IPLSB $notmod } - global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHMSB $CONFIG_DSU_ETHMSB $notmod } - global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } - global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } - write_comment $cfg $autocfg "Peripherals " - write_comment $cfg $autocfg "Memory controllers " - write_comment $cfg $autocfg "8/32-bit PROM/SRAM controller " - global CONFIG_SRCTRL - write_tristate $cfg $autocfg CONFIG_SRCTRL $CONFIG_SRCTRL [list $notmod] 2 - global CONFIG_SRCTRL_8BIT - if {($CONFIG_SRCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SRCTRL_8BIT $CONFIG_SRCTRL_8BIT [list $notmod] 2 } - global CONFIG_SRCTRL_PROMWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_PROMWS $CONFIG_SRCTRL_PROMWS $notmod } - global CONFIG_SRCTRL_RAMWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_RAMWS $CONFIG_SRCTRL_RAMWS $notmod } - global CONFIG_SRCTRL_IOWS - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_IOWS $CONFIG_SRCTRL_IOWS $notmod } - global CONFIG_SRCTRL_RMW - if {($CONFIG_SRCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SRCTRL_RMW $CONFIG_SRCTRL_RMW [list $notmod] 2 } - global tmpvar_26 - if {($CONFIG_SRCTRL == 1)} then { - if { $tmpvar_26 == "1" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS1 0 [list $notmod] 2 } - if { $tmpvar_26 == "2" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS2 0 [list $notmod] 2 } - if { $tmpvar_26 == "3" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS3 0 [list $notmod] 2 } - if { $tmpvar_26 == "4" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS4 0 [list $notmod] 2 } - if { $tmpvar_26 == "5" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_SRBANKS5 0 [list $notmod] 2 }} - global tmpvar_27 - if {($CONFIG_SRCTRL == 1)} then { - if { $tmpvar_27 == "8" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ0 0 [list $notmod] 2 } - if { $tmpvar_27 == "16" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ1 0 [list $notmod] 2 } - if { $tmpvar_27 == "32" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ2 0 [list $notmod] 2 } - if { $tmpvar_27 == "64" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ3 0 [list $notmod] 2 } - if { $tmpvar_27 == "128" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ4 0 [list $notmod] 2 } - if { $tmpvar_27 == "256" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ5 0 [list $notmod] 2 } - if { $tmpvar_27 == "512" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ6 0 [list $notmod] 2 } - if { $tmpvar_27 == "1024" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ7 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ7 0 [list $notmod] 2 } - if { $tmpvar_27 == "2048" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ8 0 [list $notmod] 2 } - if { $tmpvar_27 == "4096" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ9 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ9 0 [list $notmod] 2 } - if { $tmpvar_27 == "8192" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ10 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ10 0 [list $notmod] 2 } - if { $tmpvar_27 == "16384" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ11 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ11 0 [list $notmod] 2 } - if { $tmpvar_27 == "32768" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ12 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ12 0 [list $notmod] 2 } - if { $tmpvar_27 == "65536" } then { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SRCTRL_BANKSZ13 0 [list $notmod] 2 }} - global CONFIG_SRCTRL_ROMASEL - if {($CONFIG_SRCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SRCTRL_ROMASEL $CONFIG_SRCTRL_ROMASEL $notmod } - write_comment $cfg $autocfg "Leon2 memory controller " - global CONFIG_MCTRL_LEON2 - write_tristate $cfg $autocfg CONFIG_MCTRL_LEON2 $CONFIG_MCTRL_LEON2 [list $notmod] 2 - global CONFIG_MCTRL_8BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_8BIT $CONFIG_MCTRL_8BIT [list $notmod] 2 } - global CONFIG_MCTRL_16BIT - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_16BIT $CONFIG_MCTRL_16BIT [list $notmod] 2 } - global CONFIG_MCTRL_5CS - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_5CS $CONFIG_MCTRL_5CS [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM - if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM $CONFIG_MCTRL_SDRAM [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_SEPBUS - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_SEPBUS $CONFIG_MCTRL_SDRAM_SEPBUS [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_BUS64 - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_BUS64 $CONFIG_MCTRL_SDRAM_BUS64 [list $notmod] 2 } - global CONFIG_MCTRL_SDRAM_INVCLK - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_INVCLK $CONFIG_MCTRL_SDRAM_INVCLK [list $notmod] 2 } - global CONFIG_MCTRL_PAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PAGE $CONFIG_MCTRL_PAGE [list $notmod] 2 } - global CONFIG_MCTRL_PROGPAGE - if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PROGPAGE $CONFIG_MCTRL_PROGPAGE [list $notmod] 2 } - write_comment $cfg $autocfg "PC133 SDRAM controller " - global CONFIG_SDCTRL - write_tristate $cfg $autocfg CONFIG_SDCTRL $CONFIG_SDCTRL [list $notmod] 2 - global CONFIG_SDCTRL_BUS64 - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_BUS64 $CONFIG_SDCTRL_BUS64 [list $notmod] 2 } - global CONFIG_SDCTRL_INVCLK - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_INVCLK $CONFIG_SDCTRL_INVCLK [list $notmod] 2 } - global CONFIG_SDCTRL_PAGE - if {($CONFIG_SDCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_PAGE $CONFIG_SDCTRL_PAGE [list $notmod] 2 } - global CONFIG_SDCTRL_PROGPAGE - if {($CONFIG_SDCTRL == 1) && ($CONFIG_SDCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_SDCTRL_PROGPAGE $CONFIG_SDCTRL_PROGPAGE [list $notmod] 2 } - write_comment $cfg $autocfg "On-chip RAM/ROM " - global CONFIG_AHBROM_ENABLE - write_tristate $cfg $autocfg CONFIG_AHBROM_ENABLE $CONFIG_AHBROM_ENABLE [list $notmod] 2 - global CONFIG_AHBROM_START - if {($CONFIG_AHBROM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBROM_START $CONFIG_AHBROM_START $notmod } - global CONFIG_AHBROM_PIPE - if {($CONFIG_AHBROM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBROM_PIPE $CONFIG_AHBROM_PIPE [list $notmod] 2 } - global CONFIG_AHBRAM_ENABLE - write_tristate $cfg $autocfg CONFIG_AHBRAM_ENABLE $CONFIG_AHBRAM_ENABLE [list $notmod] 2 - global tmpvar_28 - if {($CONFIG_AHBRAM_ENABLE == 1)} then { - if { $tmpvar_28 == "1" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_28 == "2" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_28 == "4" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_28 == "8" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_28 == "16" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_28 == "32" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_28 == "64" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 0 [list $notmod] 2 }} - global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBRAM_START $CONFIG_AHBRAM_START $notmod } - write_comment $cfg $autocfg "Ethernet " - write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 - if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } - global tmpvar_29 - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - if { $tmpvar_29 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_29 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_29 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_29 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 0 [list $notmod] 2 } - if { $tmpvar_29 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "CAN " - global CONFIG_CAN_ENABLE - write_tristate $cfg $autocfg CONFIG_CAN_ENABLE $CONFIG_CAN_ENABLE [list $notmod] 2 - global CONFIG_CANIO - if {($CONFIG_CAN_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CANIO $CONFIG_CANIO $notmod } - global CONFIG_CANIRQ - if {($CONFIG_CAN_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_CANIRQ $CONFIG_CANIRQ $notmod } - global CONFIG_CANLOOP - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CANLOOP $CONFIG_CANLOOP [list $notmod] 2 } - global CONFIG_CAN_SYNCRST - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CAN_SYNCRST $CONFIG_CAN_SYNCRST [list $notmod] 2 } - global CONFIG_CAN_FT - if {($CONFIG_CAN_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_CAN_FT $CONFIG_CAN_FT [list $notmod] 2 } - write_comment $cfg $autocfg "PCI " - global CONFIG_PCI_SIMPLE_TARGET - global CONFIG_PCI_ACTEL - if {($CONFIG_PCI_ACTEL != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SIMPLE_TARGET $CONFIG_PCI_SIMPLE_TARGET [list $notmod] 2 } - global CONFIG_PCI_MASTER_TARGET - if {($CONFIG_PCI_SIMPLE_TARGET != 1 && $CONFIG_PCI_ACTEL != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_MASTER_TARGET $CONFIG_PCI_MASTER_TARGET [list $notmod] 2 } - global CONFIG_PCI_MASTER_TARGET_DMA - if {($CONFIG_PCI_MASTER_TARGET == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_MASTER_TARGET_DMA $CONFIG_PCI_MASTER_TARGET_DMA [list $notmod] 2 } - global CONFIG_PCI_VENDORID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_VENDORID $CONFIG_PCI_VENDORID $notmod } - global CONFIG_PCI_DEVICEID - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_DEVICEID $CONFIG_PCI_DEVICEID $notmod } - global tmpvar_30 - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then { - if { $tmpvar_30 == "None" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO0 0 [list $notmod] 2 } - if { $tmpvar_30 == "8" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_30 == "16" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_30 == "32" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO32 0 [list $notmod] 2 } - if { $tmpvar_30 == "64" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO64 0 [list $notmod] 2 } - if { $tmpvar_30 == "128" } then { write_tristate $cfg $autocfg CONFIG_PCI_FIFO128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_FIFO128 0 [list $notmod] 2 }} - global CONFIG_PCI_HADDR - if {($CONFIG_PCI_SIMPLE_TARGET == 1 || $CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1) && ($CONFIG_PCI_MASTER_TARGET == 1 || $CONFIG_PCI_ACTEL == 1)} then {write_hex $cfg $autocfg CONFIG_PCI_HADDR $CONFIG_PCI_HADDR $notmod } - global CONFIG_PCI_ARBITER - write_tristate $cfg $autocfg CONFIG_PCI_ARBITER $CONFIG_PCI_ARBITER [list $notmod] 2 - global CONFIG_PCI_ARBITER_APB - if {($CONFIG_PCI_ARBITER == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_ARBITER_APB $CONFIG_PCI_ARBITER_APB [list $notmod] 2 } - global CONFIG_PCI_ARBITER_NREQ - if {($CONFIG_PCI_ARBITER == 1)} then {write_int $cfg $autocfg CONFIG_PCI_ARBITER_NREQ $CONFIG_PCI_ARBITER_NREQ $notmod } - global CONFIG_PCI_TRACE - write_tristate $cfg $autocfg CONFIG_PCI_TRACE $CONFIG_PCI_TRACE [list $notmod] 2 - global tmpvar_31 - if {($CONFIG_PCI_TRACE == 1)} then { - if { $tmpvar_31 == "256" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE256 0 [list $notmod] 2 } - if { $tmpvar_31 == "512" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE512 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE512 0 [list $notmod] 2 } - if { $tmpvar_31 == "1024" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE1024 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE1024 0 [list $notmod] 2 } - if { $tmpvar_31 == "2048" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE2048 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE2048 0 [list $notmod] 2 } - if { $tmpvar_31 == "4096" } then { write_tristate $cfg $autocfg CONFIG_PCI_TRACE4096 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_PCI_TRACE4096 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "Spacewire " - global CONFIG_SPW_ENABLE - write_tristate $cfg $autocfg CONFIG_SPW_ENABLE $CONFIG_SPW_ENABLE [list $notmod] 2 - global CONFIG_SPW_NUM - if {($CONFIG_SPW_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPW_NUM $CONFIG_SPW_NUM $notmod } - global tmpvar_32 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_32 == "4" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO4 0 [list $notmod] 2 } - if { $tmpvar_32 == "8" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO8 0 [list $notmod] 2 } - if { $tmpvar_32 == "16" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO16 0 [list $notmod] 2 } - if { $tmpvar_32 == "32" } then { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_AHBFIFO32 0 [list $notmod] 2 }} - global tmpvar_33 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_33 == "16" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO16 0 [list $notmod] 2 } - if { $tmpvar_33 == "32" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO32 0 [list $notmod] 2 } - if { $tmpvar_33 == "64" } then { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RXFIFO64 0 [list $notmod] 2 }} - global CONFIG_SPW_RMAP - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RMAP $CONFIG_SPW_RMAP [list $notmod] 2 } - global tmpvar_34 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_RMAP == 1)} then { - if { $tmpvar_34 == "64" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF2 0 [list $notmod] 2 } - if { $tmpvar_34 == "128" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF4 0 [list $notmod] 2 } - if { $tmpvar_34 == "192" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF6 0 [list $notmod] 2 } - if { $tmpvar_34 == "256" } then { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RMAPBUF8 0 [list $notmod] 2 }} - global CONFIG_SPW_RMAPCRC - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RMAPCRC $CONFIG_SPW_RMAPCRC [list $notmod] 2 } - global CONFIG_SPW_RXUNAL - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RXUNAL $CONFIG_SPW_RXUNAL [list $notmod] 2 } - global CONFIG_SPW_FT - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_FT $CONFIG_SPW_FT [list $notmod] 2 } - global CONFIG_SPW_NETLIST - if {($CONFIG_SPW_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_NETLIST $CONFIG_SPW_NETLIST [list $notmod] 2 } - global tmpvar_35 - if {($CONFIG_SPW_ENABLE == 1)} then { - if { $tmpvar_35 == "1" } then { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW1 0 [list $notmod] 2 } - if { $tmpvar_35 == "2" } then { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_GRSPW2 0 [list $notmod] 2 }} - global CONFIG_SPW_DMACHAN - global CONFIG_SPW_GRSPW2 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_int $cfg $autocfg CONFIG_SPW_DMACHAN $CONFIG_SPW_DMACHAN $notmod } - global CONFIG_SPW_PORTS - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_int $cfg $autocfg CONFIG_SPW_PORTS $CONFIG_SPW_PORTS $notmod } - global CONFIG_SPW_RTSAME - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then {write_tristate $cfg $autocfg CONFIG_SPW_RTSAME $CONFIG_SPW_RTSAME [list $notmod] 2 } - global tmpvar_36 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - if { $tmpvar_36 == "SDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_SDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_SDR 0 [list $notmod] 2 } - if { $tmpvar_36 == "DDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_DDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_DDR 0 [list $notmod] 2 } - if { $tmpvar_36 == "Xor" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_XOR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_XOR 0 [list $notmod] 2 } - if { $tmpvar_36 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_RX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_RX_AFLEX 0 [list $notmod] 2 }} - global tmpvar_37 - if {($CONFIG_SPW_ENABLE == 1) && ($CONFIG_SPW_GRSPW2 == 1)} then { - if { $tmpvar_37 == "SDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_SDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_SDR 0 [list $notmod] 2 } - if { $tmpvar_37 == "DDR" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_DDR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_DDR 0 [list $notmod] 2 } - if { $tmpvar_37 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 0 [list $notmod] 2 }} - write_comment $cfg $autocfg "UARTs, timers and irq control " - global CONFIG_UART1_ENABLE - write_tristate $cfg $autocfg CONFIG_UART1_ENABLE $CONFIG_UART1_ENABLE [list $notmod] 2 - global tmpvar_38 - if {($CONFIG_UART1_ENABLE == 1)} then { - if { $tmpvar_38 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 0 [list $notmod] 2 } - if { $tmpvar_38 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 0 [list $notmod] 2 } - if { $tmpvar_38 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_38 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_38 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_38 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 0 [list $notmod] 2 }} - global CONFIG_UART2_ENABLE - write_tristate $cfg $autocfg CONFIG_UART2_ENABLE $CONFIG_UART2_ENABLE [list $notmod] 2 - global tmpvar_39 - if {($CONFIG_UART2_ENABLE == 1)} then { - if { $tmpvar_39 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO1 0 [list $notmod] 2 } - if { $tmpvar_39 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO2 0 [list $notmod] 2 } - if { $tmpvar_39 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_39 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_39 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_39 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA2_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA2_FIFO32 0 [list $notmod] 2 }} - global CONFIG_IRQ3_ENABLE - write_tristate $cfg $autocfg CONFIG_IRQ3_ENABLE $CONFIG_IRQ3_ENABLE [list $notmod] 2 - global CONFIG_IRQ3_SEC - if {($CONFIG_IRQ3_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_IRQ3_SEC $CONFIG_IRQ3_SEC [list $notmod] 2 } - global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {write_int $cfg $autocfg CONFIG_IRQ3_NSEC $CONFIG_IRQ3_NSEC $notmod } - global CONFIG_GPT_ENABLE - write_tristate $cfg $autocfg CONFIG_GPT_ENABLE $CONFIG_GPT_ENABLE [list $notmod] 2 - global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_NTIM $CONFIG_GPT_NTIM $notmod } - global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_SW $CONFIG_GPT_SW $notmod } - global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_TW $CONFIG_GPT_TW $notmod } - global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_IRQ $CONFIG_GPT_IRQ $notmod } - global CONFIG_GPT_SEPIRQ - if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_SEPIRQ $CONFIG_GPT_SEPIRQ [list $notmod] 2 } - global CONFIG_GPT_WDOGEN - if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_WDOGEN $CONFIG_GPT_WDOGEN [list $notmod] 2 } - global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {write_hex $cfg $autocfg CONFIG_GPT_WDOG $CONFIG_GPT_WDOG $notmod } - global CONFIG_GRGPIO_ENABLE - write_tristate $cfg $autocfg CONFIG_GRGPIO_ENABLE $CONFIG_GRGPIO_ENABLE [list $notmod] 2 - global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRGPIO_WIDTH $CONFIG_GRGPIO_WIDTH $notmod } - global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_GRGPIO_IMASK $CONFIG_GRGPIO_IMASK $notmod } - write_comment $cfg $autocfg "VHDL Debugging " - global CONFIG_DEBUG_UART - write_tristate $cfg $autocfg CONFIG_DEBUG_UART $CONFIG_DEBUG_UART [list $notmod] 2 - close $cfg - close $autocfg -} - - -proc clear_choices { } { - global CONFIG_SYN_INFERRED; set CONFIG_SYN_INFERRED 0 - global CONFIG_SYN_STRATIX; set CONFIG_SYN_STRATIX 0 - global CONFIG_SYN_STRATIXII; set CONFIG_SYN_STRATIXII 0 - global CONFIG_SYN_STRATIXIII; set CONFIG_SYN_STRATIXIII 0 - global CONFIG_SYN_CYCLONEIII; set CONFIG_SYN_CYCLONEIII 0 - global CONFIG_SYN_ALTERA; set CONFIG_SYN_ALTERA 0 - global CONFIG_SYN_AXCEL; set CONFIG_SYN_AXCEL 0 - global CONFIG_SYN_PROASIC; set CONFIG_SYN_PROASIC 0 - global CONFIG_SYN_PROASICPLUS; set CONFIG_SYN_PROASICPLUS 0 - global CONFIG_SYN_PROASIC3; set CONFIG_SYN_PROASIC3 0 - global CONFIG_SYN_UT025CRH; set CONFIG_SYN_UT025CRH 0 - global CONFIG_SYN_ATC18; set CONFIG_SYN_ATC18 0 - global CONFIG_SYN_ATC18RHA; set CONFIG_SYN_ATC18RHA 0 - global CONFIG_SYN_CUSTOM1; set CONFIG_SYN_CUSTOM1 0 - global CONFIG_SYN_EASIC90; set CONFIG_SYN_EASIC90 0 - global CONFIG_SYN_IHP25; set CONFIG_SYN_IHP25 0 - global CONFIG_SYN_IHP25RH; set CONFIG_SYN_IHP25RH 0 - global CONFIG_SYN_LATTICE; set CONFIG_SYN_LATTICE 0 - global CONFIG_SYN_ECLIPSE; set CONFIG_SYN_ECLIPSE 0 - global CONFIG_SYN_PEREGRINE; set CONFIG_SYN_PEREGRINE 0 - global CONFIG_SYN_RH_LIB18T; set CONFIG_SYN_RH_LIB18T 0 - global CONFIG_SYN_RHUMC; set CONFIG_SYN_RHUMC 0 - global CONFIG_SYN_SMIC13; set CONFIG_SYN_SMIC13 0 - global CONFIG_SYN_SPARTAN2; set CONFIG_SYN_SPARTAN2 0 - global CONFIG_SYN_SPARTAN3; set CONFIG_SYN_SPARTAN3 0 - global CONFIG_SYN_SPARTAN3E; set CONFIG_SYN_SPARTAN3E 0 - global CONFIG_SYN_VIRTEX; set CONFIG_SYN_VIRTEX 0 - global CONFIG_SYN_VIRTEXE; set CONFIG_SYN_VIRTEXE 0 - global CONFIG_SYN_VIRTEX2; set CONFIG_SYN_VIRTEX2 0 - global CONFIG_SYN_VIRTEX4; set CONFIG_SYN_VIRTEX4 0 - global CONFIG_SYN_VIRTEX5; set CONFIG_SYN_VIRTEX5 0 - global CONFIG_SYN_UMC; set CONFIG_SYN_UMC 0 - global CONFIG_SYN_TSMC90; set CONFIG_SYN_TSMC90 0 - global CONFIG_MEM_INFERRED; set CONFIG_MEM_INFERRED 0 - global CONFIG_MEM_UMC; set CONFIG_MEM_UMC 0 - global CONFIG_MEM_RHUMC; set CONFIG_MEM_RHUMC 0 - global CONFIG_MEM_ARTISAN; set CONFIG_MEM_ARTISAN 0 - global CONFIG_MEM_CUSTOM1; set CONFIG_MEM_CUSTOM1 0 - global CONFIG_MEM_VIRAGE; set CONFIG_MEM_VIRAGE 0 - global CONFIG_MEM_VIRAGE90; set CONFIG_MEM_VIRAGE90 0 - global CONFIG_CLK_INFERRED; set CONFIG_CLK_INFERRED 0 - global CONFIG_CLK_HCLKBUF; set CONFIG_CLK_HCLKBUF 0 - global CONFIG_CLK_ALTDLL; set CONFIG_CLK_ALTDLL 0 - global CONFIG_CLK_LATDLL; set CONFIG_CLK_LATDLL 0 - global CONFIG_CLK_PRO3PLL; set CONFIG_CLK_PRO3PLL 0 - global CONFIG_CLK_LIB18T; set CONFIG_CLK_LIB18T 0 - global CONFIG_CLK_RHUMC; set CONFIG_CLK_RHUMC 0 - global CONFIG_CLK_CLKDLL; set CONFIG_CLK_CLKDLL 0 - global CONFIG_CLK_DCM; set CONFIG_CLK_DCM 0 - global CONFIG_IU_MUL_LATENCY_2; set CONFIG_IU_MUL_LATENCY_2 0 - global CONFIG_IU_MUL_LATENCY_4; set CONFIG_IU_MUL_LATENCY_4 0 - global CONFIG_IU_MUL_LATENCY_5; set CONFIG_IU_MUL_LATENCY_5 0 - global CONFIG_FPU_GRFPU; set CONFIG_FPU_GRFPU 0 - global CONFIG_FPU_GRFPULITE; set CONFIG_FPU_GRFPULITE 0 - global CONFIG_FPU_MEIKO; set CONFIG_FPU_MEIKO 0 - global CONFIG_FPU_GRFPU_INFMUL; set CONFIG_FPU_GRFPU_INFMUL 0 - global CONFIG_FPU_GRFPU_DWMUL; set CONFIG_FPU_GRFPU_DWMUL 0 - global CONFIG_FPU_GRFPU_MODGEN; set CONFIG_FPU_GRFPU_MODGEN 0 - global CONFIG_FPU_GRFPC0; set CONFIG_FPU_GRFPC0 0 - global CONFIG_FPU_GRFPC1; set CONFIG_FPU_GRFPC1 0 - global CONFIG_FPU_GRFPC2; set CONFIG_FPU_GRFPC2 0 - global CONFIG_ICACHE_ASSO1; set CONFIG_ICACHE_ASSO1 0 - global CONFIG_ICACHE_ASSO2; set CONFIG_ICACHE_ASSO2 0 - global CONFIG_ICACHE_ASSO3; set CONFIG_ICACHE_ASSO3 0 - global CONFIG_ICACHE_ASSO4; set CONFIG_ICACHE_ASSO4 0 - global CONFIG_ICACHE_SZ1; set CONFIG_ICACHE_SZ1 0 - global CONFIG_ICACHE_SZ2; set CONFIG_ICACHE_SZ2 0 - global CONFIG_ICACHE_SZ4; set CONFIG_ICACHE_SZ4 0 - global CONFIG_ICACHE_SZ8; set CONFIG_ICACHE_SZ8 0 - global CONFIG_ICACHE_SZ16; set CONFIG_ICACHE_SZ16 0 - global CONFIG_ICACHE_SZ32; set CONFIG_ICACHE_SZ32 0 - global CONFIG_ICACHE_SZ64; set CONFIG_ICACHE_SZ64 0 - global CONFIG_ICACHE_SZ128; set CONFIG_ICACHE_SZ128 0 - global CONFIG_ICACHE_SZ256; set CONFIG_ICACHE_SZ256 0 - global CONFIG_ICACHE_LZ16; set CONFIG_ICACHE_LZ16 0 - global CONFIG_ICACHE_LZ32; set CONFIG_ICACHE_LZ32 0 - global CONFIG_ICACHE_ALGORND; set CONFIG_ICACHE_ALGORND 0 - global CONFIG_ICACHE_ALGOLRR; set CONFIG_ICACHE_ALGOLRR 0 - global CONFIG_ICACHE_ALGOLRU; set CONFIG_ICACHE_ALGOLRU 0 - global CONFIG_ICACHE_LRAM_SZ1; set CONFIG_ICACHE_LRAM_SZ1 0 - global CONFIG_ICACHE_LRAM_SZ2; set CONFIG_ICACHE_LRAM_SZ2 0 - global CONFIG_ICACHE_LRAM_SZ4; set CONFIG_ICACHE_LRAM_SZ4 0 - global CONFIG_ICACHE_LRAM_SZ8; set CONFIG_ICACHE_LRAM_SZ8 0 - global CONFIG_ICACHE_LRAM_SZ16; set CONFIG_ICACHE_LRAM_SZ16 0 - global CONFIG_ICACHE_LRAM_SZ32; set CONFIG_ICACHE_LRAM_SZ32 0 - global CONFIG_ICACHE_LRAM_SZ64; set CONFIG_ICACHE_LRAM_SZ64 0 - global CONFIG_ICACHE_LRAM_SZ128; set CONFIG_ICACHE_LRAM_SZ128 0 - global CONFIG_ICACHE_LRAM_SZ256; set CONFIG_ICACHE_LRAM_SZ256 0 - global CONFIG_DCACHE_ASSO1; set CONFIG_DCACHE_ASSO1 0 - global CONFIG_DCACHE_ASSO2; set CONFIG_DCACHE_ASSO2 0 - global CONFIG_DCACHE_ASSO3; set CONFIG_DCACHE_ASSO3 0 - global CONFIG_DCACHE_ASSO4; set CONFIG_DCACHE_ASSO4 0 - global CONFIG_DCACHE_SZ1; set CONFIG_DCACHE_SZ1 0 - global CONFIG_DCACHE_SZ2; set CONFIG_DCACHE_SZ2 0 - global CONFIG_DCACHE_SZ4; set CONFIG_DCACHE_SZ4 0 - global CONFIG_DCACHE_SZ8; set CONFIG_DCACHE_SZ8 0 - global CONFIG_DCACHE_SZ16; set CONFIG_DCACHE_SZ16 0 - global CONFIG_DCACHE_SZ32; set CONFIG_DCACHE_SZ32 0 - global CONFIG_DCACHE_SZ64; set CONFIG_DCACHE_SZ64 0 - global CONFIG_DCACHE_SZ128; set CONFIG_DCACHE_SZ128 0 - global CONFIG_DCACHE_SZ256; set CONFIG_DCACHE_SZ256 0 - global CONFIG_DCACHE_LZ16; set CONFIG_DCACHE_LZ16 0 - global CONFIG_DCACHE_LZ32; set CONFIG_DCACHE_LZ32 0 - global CONFIG_DCACHE_ALGORND; set CONFIG_DCACHE_ALGORND 0 - global CONFIG_DCACHE_ALGOLRR; set CONFIG_DCACHE_ALGOLRR 0 - global CONFIG_DCACHE_ALGOLRU; set CONFIG_DCACHE_ALGOLRU 0 - global CONFIG_DCACHE_LRAM_SZ1; set CONFIG_DCACHE_LRAM_SZ1 0 - global CONFIG_DCACHE_LRAM_SZ2; set CONFIG_DCACHE_LRAM_SZ2 0 - global CONFIG_DCACHE_LRAM_SZ4; set CONFIG_DCACHE_LRAM_SZ4 0 - global CONFIG_DCACHE_LRAM_SZ8; set CONFIG_DCACHE_LRAM_SZ8 0 - global CONFIG_DCACHE_LRAM_SZ16; set CONFIG_DCACHE_LRAM_SZ16 0 - global CONFIG_DCACHE_LRAM_SZ32; set CONFIG_DCACHE_LRAM_SZ32 0 - global CONFIG_DCACHE_LRAM_SZ64; set CONFIG_DCACHE_LRAM_SZ64 0 - global CONFIG_DCACHE_LRAM_SZ128; set CONFIG_DCACHE_LRAM_SZ128 0 - global CONFIG_DCACHE_LRAM_SZ256; set CONFIG_DCACHE_LRAM_SZ256 0 - global CONFIG_MMU_COMBINED; set CONFIG_MMU_COMBINED 0 - global CONFIG_MMU_SPLIT; set CONFIG_MMU_SPLIT 0 - global CONFIG_MMU_REPARRAY; set CONFIG_MMU_REPARRAY 0 - global CONFIG_MMU_REPINCREMENT; set CONFIG_MMU_REPINCREMENT 0 - global CONFIG_MMU_I2; set CONFIG_MMU_I2 0 - global CONFIG_MMU_I4; set CONFIG_MMU_I4 0 - global CONFIG_MMU_I8; set CONFIG_MMU_I8 0 - global CONFIG_MMU_I16; set CONFIG_MMU_I16 0 - global CONFIG_MMU_I32; set CONFIG_MMU_I32 0 - global CONFIG_MMU_D2; set CONFIG_MMU_D2 0 - global CONFIG_MMU_D4; set CONFIG_MMU_D4 0 - global CONFIG_MMU_D8; set CONFIG_MMU_D8 0 - global CONFIG_MMU_D16; set CONFIG_MMU_D16 0 - global CONFIG_MMU_D32; set CONFIG_MMU_D32 0 - global CONFIG_MMU_PAGE_4K; set CONFIG_MMU_PAGE_4K 0 - global CONFIG_MMU_PAGE_8K; set CONFIG_MMU_PAGE_8K 0 - global CONFIG_MMU_PAGE_16K; set CONFIG_MMU_PAGE_16K 0 - global CONFIG_MMU_PAGE_32K; set CONFIG_MMU_PAGE_32K 0 - global CONFIG_MMU_PAGE_PROG; set CONFIG_MMU_PAGE_PROG 0 - global CONFIG_DSU_ITRACESZ1; set CONFIG_DSU_ITRACESZ1 0 - global CONFIG_DSU_ITRACESZ2; set CONFIG_DSU_ITRACESZ2 0 - global CONFIG_DSU_ITRACESZ4; set CONFIG_DSU_ITRACESZ4 0 - global CONFIG_DSU_ITRACESZ8; set CONFIG_DSU_ITRACESZ8 0 - global CONFIG_DSU_ITRACESZ16; set CONFIG_DSU_ITRACESZ16 0 - global CONFIG_DSU_ATRACESZ1; set CONFIG_DSU_ATRACESZ1 0 - global CONFIG_DSU_ATRACESZ2; set CONFIG_DSU_ATRACESZ2 0 - global CONFIG_DSU_ATRACESZ4; set CONFIG_DSU_ATRACESZ4 0 - global CONFIG_DSU_ATRACESZ8; set CONFIG_DSU_ATRACESZ8 0 - global CONFIG_DSU_ATRACESZ16; set CONFIG_DSU_ATRACESZ16 0 - global CONFIG_DSU_ETHSZ1; set CONFIG_DSU_ETHSZ1 0 - global CONFIG_DSU_ETHSZ2; set CONFIG_DSU_ETHSZ2 0 - global CONFIG_DSU_ETHSZ4; set CONFIG_DSU_ETHSZ4 0 - global CONFIG_DSU_ETHSZ8; set CONFIG_DSU_ETHSZ8 0 - global CONFIG_DSU_ETHSZ16; set CONFIG_DSU_ETHSZ16 0 - global CONFIG_SRCTRL_SRBANKS1; set CONFIG_SRCTRL_SRBANKS1 0 - global CONFIG_SRCTRL_SRBANKS2; set CONFIG_SRCTRL_SRBANKS2 0 - global CONFIG_SRCTRL_SRBANKS3; set CONFIG_SRCTRL_SRBANKS3 0 - global CONFIG_SRCTRL_SRBANKS4; set CONFIG_SRCTRL_SRBANKS4 0 - global CONFIG_SRCTRL_SRBANKS5; set CONFIG_SRCTRL_SRBANKS5 0 - global CONFIG_SRCTRL_BANKSZ0; set CONFIG_SRCTRL_BANKSZ0 0 - global CONFIG_SRCTRL_BANKSZ1; set CONFIG_SRCTRL_BANKSZ1 0 - global CONFIG_SRCTRL_BANKSZ2; set CONFIG_SRCTRL_BANKSZ2 0 - global CONFIG_SRCTRL_BANKSZ3; set CONFIG_SRCTRL_BANKSZ3 0 - global CONFIG_SRCTRL_BANKSZ4; set CONFIG_SRCTRL_BANKSZ4 0 - global CONFIG_SRCTRL_BANKSZ5; set CONFIG_SRCTRL_BANKSZ5 0 - global CONFIG_SRCTRL_BANKSZ6; set CONFIG_SRCTRL_BANKSZ6 0 - global CONFIG_SRCTRL_BANKSZ7; set CONFIG_SRCTRL_BANKSZ7 0 - global CONFIG_SRCTRL_BANKSZ8; set CONFIG_SRCTRL_BANKSZ8 0 - global CONFIG_SRCTRL_BANKSZ9; set CONFIG_SRCTRL_BANKSZ9 0 - global CONFIG_SRCTRL_BANKSZ10; set CONFIG_SRCTRL_BANKSZ10 0 - global CONFIG_SRCTRL_BANKSZ11; set CONFIG_SRCTRL_BANKSZ11 0 - global CONFIG_SRCTRL_BANKSZ12; set CONFIG_SRCTRL_BANKSZ12 0 - global CONFIG_SRCTRL_BANKSZ13; set CONFIG_SRCTRL_BANKSZ13 0 - global CONFIG_AHBRAM_SZ1; set CONFIG_AHBRAM_SZ1 0 - global CONFIG_AHBRAM_SZ2; set CONFIG_AHBRAM_SZ2 0 - global CONFIG_AHBRAM_SZ4; set CONFIG_AHBRAM_SZ4 0 - global CONFIG_AHBRAM_SZ8; set CONFIG_AHBRAM_SZ8 0 - global CONFIG_AHBRAM_SZ16; set CONFIG_AHBRAM_SZ16 0 - global CONFIG_AHBRAM_SZ32; set CONFIG_AHBRAM_SZ32 0 - global CONFIG_AHBRAM_SZ64; set CONFIG_AHBRAM_SZ64 0 - global CONFIG_GRETH_FIFO4; set CONFIG_GRETH_FIFO4 0 - global CONFIG_GRETH_FIFO8; set CONFIG_GRETH_FIFO8 0 - global CONFIG_GRETH_FIFO16; set CONFIG_GRETH_FIFO16 0 - global CONFIG_GRETH_FIFO32; set CONFIG_GRETH_FIFO32 0 - global CONFIG_GRETH_FIFO64; set CONFIG_GRETH_FIFO64 0 - global CONFIG_PCI_FIFO0; set CONFIG_PCI_FIFO0 0 - global CONFIG_PCI_FIFO8; set CONFIG_PCI_FIFO8 0 - global CONFIG_PCI_FIFO16; set CONFIG_PCI_FIFO16 0 - global CONFIG_PCI_FIFO32; set CONFIG_PCI_FIFO32 0 - global CONFIG_PCI_FIFO64; set CONFIG_PCI_FIFO64 0 - global CONFIG_PCI_FIFO128; set CONFIG_PCI_FIFO128 0 - global CONFIG_PCI_TRACE256; set CONFIG_PCI_TRACE256 0 - global CONFIG_PCI_TRACE512; set CONFIG_PCI_TRACE512 0 - global CONFIG_PCI_TRACE1024; set CONFIG_PCI_TRACE1024 0 - global CONFIG_PCI_TRACE2048; set CONFIG_PCI_TRACE2048 0 - global CONFIG_PCI_TRACE4096; set CONFIG_PCI_TRACE4096 0 - global CONFIG_SPW_AHBFIFO4; set CONFIG_SPW_AHBFIFO4 0 - global CONFIG_SPW_AHBFIFO8; set CONFIG_SPW_AHBFIFO8 0 - global CONFIG_SPW_AHBFIFO16; set CONFIG_SPW_AHBFIFO16 0 - global CONFIG_SPW_AHBFIFO32; set CONFIG_SPW_AHBFIFO32 0 - global CONFIG_SPW_RXFIFO16; set CONFIG_SPW_RXFIFO16 0 - global CONFIG_SPW_RXFIFO32; set CONFIG_SPW_RXFIFO32 0 - global CONFIG_SPW_RXFIFO64; set CONFIG_SPW_RXFIFO64 0 - global CONFIG_SPW_RMAPBUF2; set CONFIG_SPW_RMAPBUF2 0 - global CONFIG_SPW_RMAPBUF4; set CONFIG_SPW_RMAPBUF4 0 - global CONFIG_SPW_RMAPBUF6; set CONFIG_SPW_RMAPBUF6 0 - global CONFIG_SPW_RMAPBUF8; set CONFIG_SPW_RMAPBUF8 0 - global CONFIG_SPW_GRSPW1; set CONFIG_SPW_GRSPW1 0 - global CONFIG_SPW_GRSPW2; set CONFIG_SPW_GRSPW2 0 - global CONFIG_SPW_RX_SDR; set CONFIG_SPW_RX_SDR 0 - global CONFIG_SPW_RX_DDR; set CONFIG_SPW_RX_DDR 0 - global CONFIG_SPW_RX_XOR; set CONFIG_SPW_RX_XOR 0 - global CONFIG_SPW_RX_AFLEX; set CONFIG_SPW_RX_AFLEX 0 - global CONFIG_SPW_TX_SDR; set CONFIG_SPW_TX_SDR 0 - global CONFIG_SPW_TX_DDR; set CONFIG_SPW_TX_DDR 0 - global CONFIG_SPW_TX_AFLEX; set CONFIG_SPW_TX_AFLEX 0 - global CONFIG_UA1_FIFO1; set CONFIG_UA1_FIFO1 0 - global CONFIG_UA1_FIFO2; set CONFIG_UA1_FIFO2 0 - global CONFIG_UA1_FIFO4; set CONFIG_UA1_FIFO4 0 - global CONFIG_UA1_FIFO8; set CONFIG_UA1_FIFO8 0 - global CONFIG_UA1_FIFO16; set CONFIG_UA1_FIFO16 0 - global CONFIG_UA1_FIFO32; set CONFIG_UA1_FIFO32 0 - global CONFIG_UA2_FIFO1; set CONFIG_UA2_FIFO1 0 - global CONFIG_UA2_FIFO2; set CONFIG_UA2_FIFO2 0 - global CONFIG_UA2_FIFO4; set CONFIG_UA2_FIFO4 0 - global CONFIG_UA2_FIFO8; set CONFIG_UA2_FIFO8 0 - global CONFIG_UA2_FIFO16; set CONFIG_UA2_FIFO16 0 - global CONFIG_UA2_FIFO32; set CONFIG_UA2_FIFO32 0 -} - - -proc update_choices { } { - global tmpvar_0 - set tmpvar_0 "Inferred" - global CONFIG_SYN_INFERRED - if { $CONFIG_SYN_INFERRED == 1 } then { set tmpvar_0 "Inferred" } - global CONFIG_SYN_STRATIX - if { $CONFIG_SYN_STRATIX == 1 } then { set tmpvar_0 "Altera-Stratix" } - global CONFIG_SYN_STRATIXII - if { $CONFIG_SYN_STRATIXII == 1 } then { set tmpvar_0 "Altera-StratixII" } - global CONFIG_SYN_STRATIXIII - if { $CONFIG_SYN_STRATIXIII == 1 } then { set tmpvar_0 "Altera-StratixIII" } - global CONFIG_SYN_CYCLONEIII - if { $CONFIG_SYN_CYCLONEIII == 1 } then { set tmpvar_0 "Altera-CycloneIII" } - global CONFIG_SYN_ALTERA - if { $CONFIG_SYN_ALTERA == 1 } then { set tmpvar_0 "Altera-Others" } - global CONFIG_SYN_AXCEL - if { $CONFIG_SYN_AXCEL == 1 } then { set tmpvar_0 "Actel-Axcelerator" } - global CONFIG_SYN_PROASIC - if { $CONFIG_SYN_PROASIC == 1 } then { set tmpvar_0 "Actel-Proasic" } - global CONFIG_SYN_PROASICPLUS - if { $CONFIG_SYN_PROASICPLUS == 1 } then { set tmpvar_0 "Actel-ProasicPlus" } - global CONFIG_SYN_PROASIC3 - if { $CONFIG_SYN_PROASIC3 == 1 } then { set tmpvar_0 "Actel-Proasic3" } - global CONFIG_SYN_UT025CRH - if { $CONFIG_SYN_UT025CRH == 1 } then { set tmpvar_0 "Aeroflex-UT025CRH" } - global CONFIG_SYN_ATC18 - if { $CONFIG_SYN_ATC18 == 1 } then { set tmpvar_0 "Atmel-ATC18" } - global CONFIG_SYN_ATC18RHA - if { $CONFIG_SYN_ATC18RHA == 1 } then { set tmpvar_0 "Atmel-ATC18RHA" } - global CONFIG_SYN_CUSTOM1 - if { $CONFIG_SYN_CUSTOM1 == 1 } then { set tmpvar_0 "Custom1" } - global CONFIG_SYN_EASIC90 - if { $CONFIG_SYN_EASIC90 == 1 } then { set tmpvar_0 "eASIC90" } - global CONFIG_SYN_IHP25 - if { $CONFIG_SYN_IHP25 == 1 } then { set tmpvar_0 "IHP25" } - global CONFIG_SYN_IHP25RH - if { $CONFIG_SYN_IHP25RH == 1 } then { set tmpvar_0 "IHP25RH" } - global CONFIG_SYN_LATTICE - if { $CONFIG_SYN_LATTICE == 1 } then { set tmpvar_0 "Lattice-EC/ECP/XP" } - global CONFIG_SYN_ECLIPSE - if { $CONFIG_SYN_ECLIPSE == 1 } then { set tmpvar_0 "Quicklogic-Eclipse" } - global CONFIG_SYN_PEREGRINE - if { $CONFIG_SYN_PEREGRINE == 1 } then { set tmpvar_0 "Peregrine" } - global CONFIG_SYN_RH_LIB18T - if { $CONFIG_SYN_RH_LIB18T == 1 } then { set tmpvar_0 "RH-LIB18T" } - global CONFIG_SYN_RHUMC - if { $CONFIG_SYN_RHUMC == 1 } then { set tmpvar_0 "RH-UMC" } - global CONFIG_SYN_SMIC13 - if { $CONFIG_SYN_SMIC13 == 1 } then { set tmpvar_0 "SMIC130" } - global CONFIG_SYN_SPARTAN2 - if { $CONFIG_SYN_SPARTAN2 == 1 } then { set tmpvar_0 "Xilinx-Spartan2" } - global CONFIG_SYN_SPARTAN3 - if { $CONFIG_SYN_SPARTAN3 == 1 } then { set tmpvar_0 "Xilinx-Spartan3" } - global CONFIG_SYN_SPARTAN3E - if { $CONFIG_SYN_SPARTAN3E == 1 } then { set tmpvar_0 "Xilinx-Spartan3E" } - global CONFIG_SYN_VIRTEX - if { $CONFIG_SYN_VIRTEX == 1 } then { set tmpvar_0 "Xilinx-Virtex" } - global CONFIG_SYN_VIRTEXE - if { $CONFIG_SYN_VIRTEXE == 1 } then { set tmpvar_0 "Xilinx-VirtexE" } - global CONFIG_SYN_VIRTEX2 - if { $CONFIG_SYN_VIRTEX2 == 1 } then { set tmpvar_0 "Xilinx-Virtex2" } - global CONFIG_SYN_VIRTEX4 - if { $CONFIG_SYN_VIRTEX4 == 1 } then { set tmpvar_0 "Xilinx-Virtex4" } - global CONFIG_SYN_VIRTEX5 - if { $CONFIG_SYN_VIRTEX5 == 1 } then { set tmpvar_0 "Xilinx-Virtex5" } - global CONFIG_SYN_UMC - if { $CONFIG_SYN_UMC == 1 } then { set tmpvar_0 "UMC180" } - global CONFIG_SYN_TSMC90 - if { $CONFIG_SYN_TSMC90 == 1 } then { set tmpvar_0 "TSMC90" } - global tmpvar_1 - set tmpvar_1 "Inferred" - global CONFIG_MEM_INFERRED - if { $CONFIG_MEM_INFERRED == 1 } then { set tmpvar_1 "Inferred" } - global CONFIG_MEM_UMC - if { $CONFIG_MEM_UMC == 1 } then { set tmpvar_1 "UMC18" } - global CONFIG_MEM_RHUMC - if { $CONFIG_MEM_RHUMC == 1 } then { set tmpvar_1 "RH-UMC" } - global CONFIG_MEM_ARTISAN - if { $CONFIG_MEM_ARTISAN == 1 } then { set tmpvar_1 "Artisan" } - global CONFIG_MEM_CUSTOM1 - if { $CONFIG_MEM_CUSTOM1 == 1 } then { set tmpvar_1 "Custom1" } - global CONFIG_MEM_VIRAGE - if { $CONFIG_MEM_VIRAGE == 1 } then { set tmpvar_1 "Virage" } - global CONFIG_MEM_VIRAGE90 - if { $CONFIG_MEM_VIRAGE90 == 1 } then { set tmpvar_1 "Virage-TSMC90" } - global tmpvar_2 - set tmpvar_2 "Inferred" - global CONFIG_CLK_INFERRED - if { $CONFIG_CLK_INFERRED == 1 } then { set tmpvar_2 "Inferred" } - global CONFIG_CLK_HCLKBUF - if { $CONFIG_CLK_HCLKBUF == 1 } then { set tmpvar_2 "Actel-HCLKBUF" } - global CONFIG_CLK_ALTDLL - if { $CONFIG_CLK_ALTDLL == 1 } then { set tmpvar_2 "Altera-ALTPLL" } - global CONFIG_CLK_LATDLL - if { $CONFIG_CLK_LATDLL == 1 } then { set tmpvar_2 "Lattice-EXPLL" } - global CONFIG_CLK_PRO3PLL - if { $CONFIG_CLK_PRO3PLL == 1 } then { set tmpvar_2 "Proasic3-PLLL" } - global CONFIG_CLK_LIB18T - if { $CONFIG_CLK_LIB18T == 1 } then { set tmpvar_2 "RH-LIB18T-PLL" } - global CONFIG_CLK_RHUMC - if { $CONFIG_CLK_RHUMC == 1 } then { set tmpvar_2 "DARE-PLL" } - global CONFIG_CLK_CLKDLL - if { $CONFIG_CLK_CLKDLL == 1 } then { set tmpvar_2 "Xilinx-CLKDLL" } - global CONFIG_CLK_DCM - if { $CONFIG_CLK_DCM == 1 } then { set tmpvar_2 "Xilinx-DCM" } - global tmpvar_3 - set tmpvar_3 "5-cycles" - global CONFIG_IU_MUL_LATENCY_2 - if { $CONFIG_IU_MUL_LATENCY_2 == 1 } then { set tmpvar_3 "2-cycles" } - global CONFIG_IU_MUL_LATENCY_4 - if { $CONFIG_IU_MUL_LATENCY_4 == 1 } then { set tmpvar_3 "4-cycles" } - global CONFIG_IU_MUL_LATENCY_5 - if { $CONFIG_IU_MUL_LATENCY_5 == 1 } then { set tmpvar_3 "5-cycles" } - global tmpvar_4 - set tmpvar_4 "GRFPU" - global CONFIG_FPU_GRFPU - if { $CONFIG_FPU_GRFPU == 1 } then { set tmpvar_4 "GRFPU" } - global CONFIG_FPU_GRFPULITE - if { $CONFIG_FPU_GRFPULITE == 1 } then { set tmpvar_4 "GRFPU-LITE" } - global CONFIG_FPU_MEIKO - if { $CONFIG_FPU_MEIKO == 1 } then { set tmpvar_4 "Meiko" } - global tmpvar_5 - set tmpvar_5 "Inferred" - global CONFIG_FPU_GRFPU_INFMUL - if { $CONFIG_FPU_GRFPU_INFMUL == 1 } then { set tmpvar_5 "Inferred" } - global CONFIG_FPU_GRFPU_DWMUL - if { $CONFIG_FPU_GRFPU_DWMUL == 1 } then { set tmpvar_5 "DW" } - global CONFIG_FPU_GRFPU_MODGEN - if { $CONFIG_FPU_GRFPU_MODGEN == 1 } then { set tmpvar_5 "ModGen" } - global tmpvar_6 - set tmpvar_6 "Simple" - global CONFIG_FPU_GRFPC0 - if { $CONFIG_FPU_GRFPC0 == 1 } then { set tmpvar_6 "Simple" } - global CONFIG_FPU_GRFPC1 - if { $CONFIG_FPU_GRFPC1 == 1 } then { set tmpvar_6 "Data-forwarding" } - global CONFIG_FPU_GRFPC2 - if { $CONFIG_FPU_GRFPC2 == 1 } then { set tmpvar_6 "Non-blocking" } - global tmpvar_7 - set tmpvar_7 "1" - global CONFIG_ICACHE_ASSO1 - if { $CONFIG_ICACHE_ASSO1 == 1 } then { set tmpvar_7 "1" } - global CONFIG_ICACHE_ASSO2 - if { $CONFIG_ICACHE_ASSO2 == 1 } then { set tmpvar_7 "2" } - global CONFIG_ICACHE_ASSO3 - if { $CONFIG_ICACHE_ASSO3 == 1 } then { set tmpvar_7 "3" } - global CONFIG_ICACHE_ASSO4 - if { $CONFIG_ICACHE_ASSO4 == 1 } then { set tmpvar_7 "4" } - global tmpvar_8 - set tmpvar_8 "4" - global CONFIG_ICACHE_SZ1 - if { $CONFIG_ICACHE_SZ1 == 1 } then { set tmpvar_8 "1" } - global CONFIG_ICACHE_SZ2 - if { $CONFIG_ICACHE_SZ2 == 1 } then { set tmpvar_8 "2" } - global CONFIG_ICACHE_SZ4 - if { $CONFIG_ICACHE_SZ4 == 1 } then { set tmpvar_8 "4" } - global CONFIG_ICACHE_SZ8 - if { $CONFIG_ICACHE_SZ8 == 1 } then { set tmpvar_8 "8" } - global CONFIG_ICACHE_SZ16 - if { $CONFIG_ICACHE_SZ16 == 1 } then { set tmpvar_8 "16" } - global CONFIG_ICACHE_SZ32 - if { $CONFIG_ICACHE_SZ32 == 1 } then { set tmpvar_8 "32" } - global CONFIG_ICACHE_SZ64 - if { $CONFIG_ICACHE_SZ64 == 1 } then { set tmpvar_8 "64" } - global CONFIG_ICACHE_SZ128 - if { $CONFIG_ICACHE_SZ128 == 1 } then { set tmpvar_8 "128" } - global CONFIG_ICACHE_SZ256 - if { $CONFIG_ICACHE_SZ256 == 1 } then { set tmpvar_8 "256" } - global tmpvar_9 - set tmpvar_9 "32" - global CONFIG_ICACHE_LZ16 - if { $CONFIG_ICACHE_LZ16 == 1 } then { set tmpvar_9 "16" } - global CONFIG_ICACHE_LZ32 - if { $CONFIG_ICACHE_LZ32 == 1 } then { set tmpvar_9 "32" } - global tmpvar_10 - set tmpvar_10 "Random" - global CONFIG_ICACHE_ALGORND - if { $CONFIG_ICACHE_ALGORND == 1 } then { set tmpvar_10 "Random" } - global CONFIG_ICACHE_ALGOLRR - if { $CONFIG_ICACHE_ALGOLRR == 1 } then { set tmpvar_10 "LRR" } - global CONFIG_ICACHE_ALGOLRU - if { $CONFIG_ICACHE_ALGOLRU == 1 } then { set tmpvar_10 "LRU" } - global tmpvar_11 - set tmpvar_11 "4" - global CONFIG_ICACHE_LRAM_SZ1 - if { $CONFIG_ICACHE_LRAM_SZ1 == 1 } then { set tmpvar_11 "1" } - global CONFIG_ICACHE_LRAM_SZ2 - if { $CONFIG_ICACHE_LRAM_SZ2 == 1 } then { set tmpvar_11 "2" } - global CONFIG_ICACHE_LRAM_SZ4 - if { $CONFIG_ICACHE_LRAM_SZ4 == 1 } then { set tmpvar_11 "4" } - global CONFIG_ICACHE_LRAM_SZ8 - if { $CONFIG_ICACHE_LRAM_SZ8 == 1 } then { set tmpvar_11 "8" } - global CONFIG_ICACHE_LRAM_SZ16 - if { $CONFIG_ICACHE_LRAM_SZ16 == 1 } then { set tmpvar_11 "16" } - global CONFIG_ICACHE_LRAM_SZ32 - if { $CONFIG_ICACHE_LRAM_SZ32 == 1 } then { set tmpvar_11 "32" } - global CONFIG_ICACHE_LRAM_SZ64 - if { $CONFIG_ICACHE_LRAM_SZ64 == 1 } then { set tmpvar_11 "64" } - global CONFIG_ICACHE_LRAM_SZ128 - if { $CONFIG_ICACHE_LRAM_SZ128 == 1 } then { set tmpvar_11 "128" } - global CONFIG_ICACHE_LRAM_SZ256 - if { $CONFIG_ICACHE_LRAM_SZ256 == 1 } then { set tmpvar_11 "256" } - global tmpvar_12 - set tmpvar_12 "1" - global CONFIG_DCACHE_ASSO1 - if { $CONFIG_DCACHE_ASSO1 == 1 } then { set tmpvar_12 "1" } - global CONFIG_DCACHE_ASSO2 - if { $CONFIG_DCACHE_ASSO2 == 1 } then { set tmpvar_12 "2" } - global CONFIG_DCACHE_ASSO3 - if { $CONFIG_DCACHE_ASSO3 == 1 } then { set tmpvar_12 "3" } - global CONFIG_DCACHE_ASSO4 - if { $CONFIG_DCACHE_ASSO4 == 1 } then { set tmpvar_12 "4" } - global tmpvar_13 - set tmpvar_13 "4" - global CONFIG_DCACHE_SZ1 - if { $CONFIG_DCACHE_SZ1 == 1 } then { set tmpvar_13 "1" } - global CONFIG_DCACHE_SZ2 - if { $CONFIG_DCACHE_SZ2 == 1 } then { set tmpvar_13 "2" } - global CONFIG_DCACHE_SZ4 - if { $CONFIG_DCACHE_SZ4 == 1 } then { set tmpvar_13 "4" } - global CONFIG_DCACHE_SZ8 - if { $CONFIG_DCACHE_SZ8 == 1 } then { set tmpvar_13 "8" } - global CONFIG_DCACHE_SZ16 - if { $CONFIG_DCACHE_SZ16 == 1 } then { set tmpvar_13 "16" } - global CONFIG_DCACHE_SZ32 - if { $CONFIG_DCACHE_SZ32 == 1 } then { set tmpvar_13 "32" } - global CONFIG_DCACHE_SZ64 - if { $CONFIG_DCACHE_SZ64 == 1 } then { set tmpvar_13 "64" } - global CONFIG_DCACHE_SZ128 - if { $CONFIG_DCACHE_SZ128 == 1 } then { set tmpvar_13 "128" } - global CONFIG_DCACHE_SZ256 - if { $CONFIG_DCACHE_SZ256 == 1 } then { set tmpvar_13 "256" } - global tmpvar_14 - set tmpvar_14 "32" - global CONFIG_DCACHE_LZ16 - if { $CONFIG_DCACHE_LZ16 == 1 } then { set tmpvar_14 "16" } - global CONFIG_DCACHE_LZ32 - if { $CONFIG_DCACHE_LZ32 == 1 } then { set tmpvar_14 "32" } - global tmpvar_15 - set tmpvar_15 "Random" - global CONFIG_DCACHE_ALGORND - if { $CONFIG_DCACHE_ALGORND == 1 } then { set tmpvar_15 "Random" } - global CONFIG_DCACHE_ALGOLRR - if { $CONFIG_DCACHE_ALGOLRR == 1 } then { set tmpvar_15 "LRR" } - global CONFIG_DCACHE_ALGOLRU - if { $CONFIG_DCACHE_ALGOLRU == 1 } then { set tmpvar_15 "LRU" } - global tmpvar_16 - set tmpvar_16 "4" - global CONFIG_DCACHE_LRAM_SZ1 - if { $CONFIG_DCACHE_LRAM_SZ1 == 1 } then { set tmpvar_16 "1" } - global CONFIG_DCACHE_LRAM_SZ2 - if { $CONFIG_DCACHE_LRAM_SZ2 == 1 } then { set tmpvar_16 "2" } - global CONFIG_DCACHE_LRAM_SZ4 - if { $CONFIG_DCACHE_LRAM_SZ4 == 1 } then { set tmpvar_16 "4" } - global CONFIG_DCACHE_LRAM_SZ8 - if { $CONFIG_DCACHE_LRAM_SZ8 == 1 } then { set tmpvar_16 "8" } - global CONFIG_DCACHE_LRAM_SZ16 - if { $CONFIG_DCACHE_LRAM_SZ16 == 1 } then { set tmpvar_16 "16" } - global CONFIG_DCACHE_LRAM_SZ32 - if { $CONFIG_DCACHE_LRAM_SZ32 == 1 } then { set tmpvar_16 "32" } - global CONFIG_DCACHE_LRAM_SZ64 - if { $CONFIG_DCACHE_LRAM_SZ64 == 1 } then { set tmpvar_16 "64" } - global CONFIG_DCACHE_LRAM_SZ128 - if { $CONFIG_DCACHE_LRAM_SZ128 == 1 } then { set tmpvar_16 "128" } - global CONFIG_DCACHE_LRAM_SZ256 - if { $CONFIG_DCACHE_LRAM_SZ256 == 1 } then { set tmpvar_16 "256" } - global tmpvar_17 - set tmpvar_17 "combined" - global CONFIG_MMU_COMBINED - if { $CONFIG_MMU_COMBINED == 1 } then { set tmpvar_17 "combined" } - global CONFIG_MMU_SPLIT - if { $CONFIG_MMU_SPLIT == 1 } then { set tmpvar_17 "split" } - global tmpvar_18 - set tmpvar_18 "Increment" - global CONFIG_MMU_REPARRAY - if { $CONFIG_MMU_REPARRAY == 1 } then { set tmpvar_18 "LRU" } - global CONFIG_MMU_REPINCREMENT - if { $CONFIG_MMU_REPINCREMENT == 1 } then { set tmpvar_18 "Increment" } - global tmpvar_19 - set tmpvar_19 "8" - global CONFIG_MMU_I2 - if { $CONFIG_MMU_I2 == 1 } then { set tmpvar_19 "2" } - global CONFIG_MMU_I4 - if { $CONFIG_MMU_I4 == 1 } then { set tmpvar_19 "4" } - global CONFIG_MMU_I8 - if { $CONFIG_MMU_I8 == 1 } then { set tmpvar_19 "8" } - global CONFIG_MMU_I16 - if { $CONFIG_MMU_I16 == 1 } then { set tmpvar_19 "16" } - global CONFIG_MMU_I32 - if { $CONFIG_MMU_I32 == 1 } then { set tmpvar_19 "32" } - global tmpvar_20 - set tmpvar_20 "8" - global CONFIG_MMU_D2 - if { $CONFIG_MMU_D2 == 1 } then { set tmpvar_20 "2" } - global CONFIG_MMU_D4 - if { $CONFIG_MMU_D4 == 1 } then { set tmpvar_20 "4" } - global CONFIG_MMU_D8 - if { $CONFIG_MMU_D8 == 1 } then { set tmpvar_20 "8" } - global CONFIG_MMU_D16 - if { $CONFIG_MMU_D16 == 1 } then { set tmpvar_20 "16" } - global CONFIG_MMU_D32 - if { $CONFIG_MMU_D32 == 1 } then { set tmpvar_20 "32" } - global tmpvar_21 - set tmpvar_21 "4K" - global CONFIG_MMU_PAGE_4K - if { $CONFIG_MMU_PAGE_4K == 1 } then { set tmpvar_21 "4K" } - global CONFIG_MMU_PAGE_8K - if { $CONFIG_MMU_PAGE_8K == 1 } then { set tmpvar_21 "8K" } - global CONFIG_MMU_PAGE_16K - if { $CONFIG_MMU_PAGE_16K == 1 } then { set tmpvar_21 "16K" } - global CONFIG_MMU_PAGE_32K - if { $CONFIG_MMU_PAGE_32K == 1 } then { set tmpvar_21 "32K" } - global CONFIG_MMU_PAGE_PROG - if { $CONFIG_MMU_PAGE_PROG == 1 } then { set tmpvar_21 "Programmable" } - global tmpvar_22 - set tmpvar_22 "1" - global CONFIG_DSU_ITRACESZ1 - if { $CONFIG_DSU_ITRACESZ1 == 1 } then { set tmpvar_22 "1" } - global CONFIG_DSU_ITRACESZ2 - if { $CONFIG_DSU_ITRACESZ2 == 1 } then { set tmpvar_22 "2" } - global CONFIG_DSU_ITRACESZ4 - if { $CONFIG_DSU_ITRACESZ4 == 1 } then { set tmpvar_22 "4" } - global CONFIG_DSU_ITRACESZ8 - if { $CONFIG_DSU_ITRACESZ8 == 1 } then { set tmpvar_22 "8" } - global CONFIG_DSU_ITRACESZ16 - if { $CONFIG_DSU_ITRACESZ16 == 1 } then { set tmpvar_22 "16" } - global tmpvar_23 - set tmpvar_23 "1" - global CONFIG_DSU_ATRACESZ1 - if { $CONFIG_DSU_ATRACESZ1 == 1 } then { set tmpvar_23 "1" } - global CONFIG_DSU_ATRACESZ2 - if { $CONFIG_DSU_ATRACESZ2 == 1 } then { set tmpvar_23 "2" } - global CONFIG_DSU_ATRACESZ4 - if { $CONFIG_DSU_ATRACESZ4 == 1 } then { set tmpvar_23 "4" } - global CONFIG_DSU_ATRACESZ8 - if { $CONFIG_DSU_ATRACESZ8 == 1 } then { set tmpvar_23 "8" } - global CONFIG_DSU_ATRACESZ16 - if { $CONFIG_DSU_ATRACESZ16 == 1 } then { set tmpvar_23 "16" } - global tmpvar_25 - set tmpvar_25 "2" - global CONFIG_DSU_ETHSZ1 - if { $CONFIG_DSU_ETHSZ1 == 1 } then { set tmpvar_25 "1" } - global CONFIG_DSU_ETHSZ2 - if { $CONFIG_DSU_ETHSZ2 == 1 } then { set tmpvar_25 "2" } - global CONFIG_DSU_ETHSZ4 - if { $CONFIG_DSU_ETHSZ4 == 1 } then { set tmpvar_25 "4" } - global CONFIG_DSU_ETHSZ8 - if { $CONFIG_DSU_ETHSZ8 == 1 } then { set tmpvar_25 "8" } - global CONFIG_DSU_ETHSZ16 - if { $CONFIG_DSU_ETHSZ16 == 1 } then { set tmpvar_25 "16" } - global tmpvar_26 - set tmpvar_26 "1" - global CONFIG_SRCTRL_SRBANKS1 - if { $CONFIG_SRCTRL_SRBANKS1 == 1 } then { set tmpvar_26 "1" } - global CONFIG_SRCTRL_SRBANKS2 - if { $CONFIG_SRCTRL_SRBANKS2 == 1 } then { set tmpvar_26 "2" } - global CONFIG_SRCTRL_SRBANKS3 - if { $CONFIG_SRCTRL_SRBANKS3 == 1 } then { set tmpvar_26 "3" } - global CONFIG_SRCTRL_SRBANKS4 - if { $CONFIG_SRCTRL_SRBANKS4 == 1 } then { set tmpvar_26 "4" } - global CONFIG_SRCTRL_SRBANKS5 - if { $CONFIG_SRCTRL_SRBANKS5 == 1 } then { set tmpvar_26 "5" } - global tmpvar_27 - set tmpvar_27 "0" - global CONFIG_SRCTRL_BANKSZ0 - if { $CONFIG_SRCTRL_BANKSZ0 == 1 } then { set tmpvar_27 "8" } - global CONFIG_SRCTRL_BANKSZ1 - if { $CONFIG_SRCTRL_BANKSZ1 == 1 } then { set tmpvar_27 "16" } - global CONFIG_SRCTRL_BANKSZ2 - if { $CONFIG_SRCTRL_BANKSZ2 == 1 } then { set tmpvar_27 "32" } - global CONFIG_SRCTRL_BANKSZ3 - if { $CONFIG_SRCTRL_BANKSZ3 == 1 } then { set tmpvar_27 "64" } - global CONFIG_SRCTRL_BANKSZ4 - if { $CONFIG_SRCTRL_BANKSZ4 == 1 } then { set tmpvar_27 "128" } - global CONFIG_SRCTRL_BANKSZ5 - if { $CONFIG_SRCTRL_BANKSZ5 == 1 } then { set tmpvar_27 "256" } - global CONFIG_SRCTRL_BANKSZ6 - if { $CONFIG_SRCTRL_BANKSZ6 == 1 } then { set tmpvar_27 "512" } - global CONFIG_SRCTRL_BANKSZ7 - if { $CONFIG_SRCTRL_BANKSZ7 == 1 } then { set tmpvar_27 "1024" } - global CONFIG_SRCTRL_BANKSZ8 - if { $CONFIG_SRCTRL_BANKSZ8 == 1 } then { set tmpvar_27 "2048" } - global CONFIG_SRCTRL_BANKSZ9 - if { $CONFIG_SRCTRL_BANKSZ9 == 1 } then { set tmpvar_27 "4096" } - global CONFIG_SRCTRL_BANKSZ10 - if { $CONFIG_SRCTRL_BANKSZ10 == 1 } then { set tmpvar_27 "8192" } - global CONFIG_SRCTRL_BANKSZ11 - if { $CONFIG_SRCTRL_BANKSZ11 == 1 } then { set tmpvar_27 "16384" } - global CONFIG_SRCTRL_BANKSZ12 - if { $CONFIG_SRCTRL_BANKSZ12 == 1 } then { set tmpvar_27 "32768" } - global CONFIG_SRCTRL_BANKSZ13 - if { $CONFIG_SRCTRL_BANKSZ13 == 1 } then { set tmpvar_27 "65536" } - global tmpvar_28 - set tmpvar_28 "4" - global CONFIG_AHBRAM_SZ1 - if { $CONFIG_AHBRAM_SZ1 == 1 } then { set tmpvar_28 "1" } - global CONFIG_AHBRAM_SZ2 - if { $CONFIG_AHBRAM_SZ2 == 1 } then { set tmpvar_28 "2" } - global CONFIG_AHBRAM_SZ4 - if { $CONFIG_AHBRAM_SZ4 == 1 } then { set tmpvar_28 "4" } - global CONFIG_AHBRAM_SZ8 - if { $CONFIG_AHBRAM_SZ8 == 1 } then { set tmpvar_28 "8" } - global CONFIG_AHBRAM_SZ16 - if { $CONFIG_AHBRAM_SZ16 == 1 } then { set tmpvar_28 "16" } - global CONFIG_AHBRAM_SZ32 - if { $CONFIG_AHBRAM_SZ32 == 1 } then { set tmpvar_28 "32" } - global CONFIG_AHBRAM_SZ64 - if { $CONFIG_AHBRAM_SZ64 == 1 } then { set tmpvar_28 "64" } - global tmpvar_29 - set tmpvar_29 "8" - global CONFIG_GRETH_FIFO4 - if { $CONFIG_GRETH_FIFO4 == 1 } then { set tmpvar_29 "4" } - global CONFIG_GRETH_FIFO8 - if { $CONFIG_GRETH_FIFO8 == 1 } then { set tmpvar_29 "8" } - global CONFIG_GRETH_FIFO16 - if { $CONFIG_GRETH_FIFO16 == 1 } then { set tmpvar_29 "16" } - global CONFIG_GRETH_FIFO32 - if { $CONFIG_GRETH_FIFO32 == 1 } then { set tmpvar_29 "32" } - global CONFIG_GRETH_FIFO64 - if { $CONFIG_GRETH_FIFO64 == 1 } then { set tmpvar_29 "64" } - global tmpvar_30 - set tmpvar_30 "8" - global CONFIG_PCI_FIFO0 - if { $CONFIG_PCI_FIFO0 == 1 } then { set tmpvar_30 "None" } - global CONFIG_PCI_FIFO8 - if { $CONFIG_PCI_FIFO8 == 1 } then { set tmpvar_30 "8" } - global CONFIG_PCI_FIFO16 - if { $CONFIG_PCI_FIFO16 == 1 } then { set tmpvar_30 "16" } - global CONFIG_PCI_FIFO32 - if { $CONFIG_PCI_FIFO32 == 1 } then { set tmpvar_30 "32" } - global CONFIG_PCI_FIFO64 - if { $CONFIG_PCI_FIFO64 == 1 } then { set tmpvar_30 "64" } - global CONFIG_PCI_FIFO128 - if { $CONFIG_PCI_FIFO128 == 1 } then { set tmpvar_30 "128" } - global tmpvar_31 - set tmpvar_31 "256" - global CONFIG_PCI_TRACE256 - if { $CONFIG_PCI_TRACE256 == 1 } then { set tmpvar_31 "256" } - global CONFIG_PCI_TRACE512 - if { $CONFIG_PCI_TRACE512 == 1 } then { set tmpvar_31 "512" } - global CONFIG_PCI_TRACE1024 - if { $CONFIG_PCI_TRACE1024 == 1 } then { set tmpvar_31 "1024" } - global CONFIG_PCI_TRACE2048 - if { $CONFIG_PCI_TRACE2048 == 1 } then { set tmpvar_31 "2048" } - global CONFIG_PCI_TRACE4096 - if { $CONFIG_PCI_TRACE4096 == 1 } then { set tmpvar_31 "4096" } - global tmpvar_32 - set tmpvar_32 "16" - global CONFIG_SPW_AHBFIFO4 - if { $CONFIG_SPW_AHBFIFO4 == 1 } then { set tmpvar_32 "4" } - global CONFIG_SPW_AHBFIFO8 - if { $CONFIG_SPW_AHBFIFO8 == 1 } then { set tmpvar_32 "8" } - global CONFIG_SPW_AHBFIFO16 - if { $CONFIG_SPW_AHBFIFO16 == 1 } then { set tmpvar_32 "16" } - global CONFIG_SPW_AHBFIFO32 - if { $CONFIG_SPW_AHBFIFO32 == 1 } then { set tmpvar_32 "32" } - global tmpvar_33 - set tmpvar_33 "16" - global CONFIG_SPW_RXFIFO16 - if { $CONFIG_SPW_RXFIFO16 == 1 } then { set tmpvar_33 "16" } - global CONFIG_SPW_RXFIFO32 - if { $CONFIG_SPW_RXFIFO32 == 1 } then { set tmpvar_33 "32" } - global CONFIG_SPW_RXFIFO64 - if { $CONFIG_SPW_RXFIFO64 == 1 } then { set tmpvar_33 "64" } - global tmpvar_34 - set tmpvar_34 "64" - global CONFIG_SPW_RMAPBUF2 - if { $CONFIG_SPW_RMAPBUF2 == 1 } then { set tmpvar_34 "64" } - global CONFIG_SPW_RMAPBUF4 - if { $CONFIG_SPW_RMAPBUF4 == 1 } then { set tmpvar_34 "128" } - global CONFIG_SPW_RMAPBUF6 - if { $CONFIG_SPW_RMAPBUF6 == 1 } then { set tmpvar_34 "192" } - global CONFIG_SPW_RMAPBUF8 - if { $CONFIG_SPW_RMAPBUF8 == 1 } then { set tmpvar_34 "256" } - global tmpvar_35 - set tmpvar_35 "2" - global CONFIG_SPW_GRSPW1 - if { $CONFIG_SPW_GRSPW1 == 1 } then { set tmpvar_35 "1" } - global CONFIG_SPW_GRSPW2 - if { $CONFIG_SPW_GRSPW2 == 1 } then { set tmpvar_35 "2" } - global tmpvar_36 - set tmpvar_36 "DDR" - global CONFIG_SPW_RX_SDR - if { $CONFIG_SPW_RX_SDR == 1 } then { set tmpvar_36 "SDR" } - global CONFIG_SPW_RX_DDR - if { $CONFIG_SPW_RX_DDR == 1 } then { set tmpvar_36 "DDR" } - global CONFIG_SPW_RX_XOR - if { $CONFIG_SPW_RX_XOR == 1 } then { set tmpvar_36 "Xor" } - global CONFIG_SPW_RX_AFLEX - if { $CONFIG_SPW_RX_AFLEX == 1 } then { set tmpvar_36 "Aeroflex" } - global tmpvar_37 - set tmpvar_37 "SDR" - global CONFIG_SPW_TX_SDR - if { $CONFIG_SPW_TX_SDR == 1 } then { set tmpvar_37 "SDR" } - global CONFIG_SPW_TX_DDR - if { $CONFIG_SPW_TX_DDR == 1 } then { set tmpvar_37 "DDR" } - global CONFIG_SPW_TX_AFLEX - if { $CONFIG_SPW_TX_AFLEX == 1 } then { set tmpvar_37 "Aeroflex" } - global tmpvar_38 - set tmpvar_38 "1" - global CONFIG_UA1_FIFO1 - if { $CONFIG_UA1_FIFO1 == 1 } then { set tmpvar_38 "1" } - global CONFIG_UA1_FIFO2 - if { $CONFIG_UA1_FIFO2 == 1 } then { set tmpvar_38 "2" } - global CONFIG_UA1_FIFO4 - if { $CONFIG_UA1_FIFO4 == 1 } then { set tmpvar_38 "4" } - global CONFIG_UA1_FIFO8 - if { $CONFIG_UA1_FIFO8 == 1 } then { set tmpvar_38 "8" } - global CONFIG_UA1_FIFO16 - if { $CONFIG_UA1_FIFO16 == 1 } then { set tmpvar_38 "16" } - global CONFIG_UA1_FIFO32 - if { $CONFIG_UA1_FIFO32 == 1 } then { set tmpvar_38 "32" } - global tmpvar_39 - set tmpvar_39 "1" - global CONFIG_UA2_FIFO1 - if { $CONFIG_UA2_FIFO1 == 1 } then { set tmpvar_39 "1" } - global CONFIG_UA2_FIFO2 - if { $CONFIG_UA2_FIFO2 == 1 } then { set tmpvar_39 "2" } - global CONFIG_UA2_FIFO4 - if { $CONFIG_UA2_FIFO4 == 1 } then { set tmpvar_39 "4" } - global CONFIG_UA2_FIFO8 - if { $CONFIG_UA2_FIFO8 == 1 } then { set tmpvar_39 "8" } - global CONFIG_UA2_FIFO16 - if { $CONFIG_UA2_FIFO16 == 1 } then { set tmpvar_39 "16" } - global CONFIG_UA2_FIFO32 - if { $CONFIG_UA2_FIFO32 == 1 } then { set tmpvar_39 "32" } -} - - -proc update_define_mainmenu {} { - global CONFIG_MODULES -} - - -# FILE: tail.tk -# This file is boilerplate TCL/TK function definitions for 'make xconfig'. -# -# CHANGES -# ======= -# -# 8 January 1998, Michael Elizabeth Chastain, -# Arrange buttons in three columns for better screen fitting. -# - -# -# Read the user's settings from .config. These will override whatever is -# in config.in. Don't do this if the user specified a -D to force -# the defaults. -# - -set defaults defconfig - -if { [file readable .config] == 1} then { - if { $argc > 0 } then { - if { [lindex $argv 0] != "-D" } then { - read_config .config - } - else - { - read_config $defaults - } - } else { - read_config .config - } -} else { - read_config $defaults -} - -update_define 1 $total_menus 0 -update_mainmenu - -button .f0.right.save -anchor w -text "Save and Exit" -underline 0\ - -command { catch {exec cp -f .config .config.old}; \ - writeconfig .config config.h; wrapup .wrap } - -button .f0.right.quit -anchor w -text "Quit Without Saving" -underline 0\ - -command { maybe_exit .maybe } - -button .f0.right.load -anchor w -text "Load Configuration from File" \ - -command { load_configfile .load "Load Configuration from file" read_config_file -} - -button .f0.right.store -anchor w -text "Store Configuration to File" \ - -command { load_configfile .load "Store Configuration to file" write_config_file } - -# -# Now pack everything. -# - -pack .f0.right.store .f0.right.load .f0.right.quit .f0.right.save \ - -padx 0 -pady 0 -side bottom -fill x -pack .f0.left .f0.middle .f0.right -side left -padx 5 -pady 0 -fill y -pack .f0 -padx 5 -pady 5 - -update idletasks -set winy [expr 10 + [winfo reqheight .f0]] -set scry [lindex [wm maxsize .] 1] -set winx [expr 10 + [winfo reqwidth .f0]] -set scrx [lindex [wm maxsize .] 0] -if {$winx < $scrx} then {set maxx -1} else {set maxx $winx} -if {$winy < $scry} then {set maxy -1} else {set maxy $winy} -.f0 configure -width $winx -height $winy -wm maxsize . $maxx $maxy - -# -# If we cannot write our config files, disable the write button. -# -if { [file exists .config] == 1 } then { - if { [file writable .config] == 0 } then { - .f0.right.save configure -state disabled - } - } else { - if { [file writable .] == 0 } then { - .f0.right.save configure -state disabled - } - } - -#if { [file exists include/linux/autoconf.h] == 1 } then { -# if { [file writable include/linux/autoconf.h] == 0 } then { -# .f0.right.save configure -state disabled -# } -# } else { -# if { [file writable include/linux/] == 0 } then { -# .f0.right.save configure -state disabled -# } -# } diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/leon3mp.vhd b/designs/ProjetBlanc-LeonLPP-M7A3P1k/leon3mp.vhd deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/leon3mp.vhd +++ /dev/null @@ -1,359 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -library techmap; -use techmap.gencomp.all; -library gaisler; -use gaisler.memctrl.all; -use gaisler.leon3.all; -use gaisler.uart.all; -use gaisler.misc.all; -library esa; -use esa.memoryctrl.all; -use work.config.all; -library lpp; -use lpp.lpp_amba.all; - - -entity leon3mp is - generic ( - fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console - pclow : integer := CFG_PCLOW - ); - port ( - clk50MHz : in std_ulogic; - reset : in std_ulogic; - ramclk : out std_logic; - - ahbrxd : in std_ulogic; -- DSU rx data - ahbtxd : out std_ulogic; -- DSU tx data - dsubre : in std_ulogic; - dsuact : out std_ulogic; - urxd1 : in std_ulogic; -- UART1 rx data - utxd1 : out std_ulogic; -- UART1 tx data - errorn : out std_ulogic; - - address : out std_logic_vector(18 downto 0); - data : inout std_logic_vector(31 downto 0); - gpio : inout std_logic_vector(6 downto 0); -- I/O port - - ramben : out std_logic_vector (3 downto 0); - ramsn : out std_logic; - romsn : out std_logic; - iosn : out std_logic; - rwen : out std_logic; - oen : out std_ulogic; - ramoen : out std_logic; - writen : out std_ulogic; - sram_adv : out std_logic; - sram_pwrdwn : out std_logic; - sram_gwen : out std_logic; - sram_adsc : out std_logic; - sram_adsp : out std_logic; ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------In/Out----------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - led : out std_logic_vector(5 downto 0) - ); -end; - -architecture Behavioral of leon3mp is - -constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG; -constant maxahbm : integer := maxahbmsp; - ---Clk & Rst géné -signal vcc : std_logic_vector(4 downto 0); -signal gnd : std_logic_vector(4 downto 0); -signal resetnl : std_ulogic; -signal clk2x : std_ulogic; -signal lclk : std_ulogic; -signal lclk2x : std_ulogic; -signal clkm : std_ulogic; -signal rstn : std_ulogic; -signal rstraw : std_ulogic; -signal pciclk : std_ulogic; -signal sdclkl : std_ulogic; -signal cgi : clkgen_in_type; -signal cgo : clkgen_out_type; ---- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); ---UART -signal ahbuarti : uart_in_type; -signal ahbuarto : uart_out_type; -signal apbuarti : uart_in_type; -signal apbuarto : uart_out_type; ---MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal wpo : wprot_out_type; -signal sdo : sdram_out_type; ---IRQ -signal irqi : irq_in_vector(0 to CFG_NCPU-1); -signal irqo : irq_out_vector(0 to CFG_NCPU-1); ---Timer -signal gpti : gptimer_in_type; -signal gpto : gptimer_out_type; ---GPIO -signal gpioi : gpio_in_type; -signal gpioo : gpio_out_type; ---DSU -signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); -signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); -signal dsui : dsu_in_type; -signal dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- -constant IOAEN : integer := CFG_CAN; -constant boardfreq : integer := 50000; - -begin - ---------------------------------------------------------------------- ---- AJOUT TEST -------------------------------------IPs------------- ---------------------------------------------------------------------- -led(1 downto 0) <= gpio(1 downto 0); - - ----------------------------------------------------------------------- - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (others => '1'); gnd <= (others => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); - - clkgen0 : clkgen -- clock generator - generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; -process(lclk2x) -begin - if lclk2x'event and lclk2x = '1' then - lclk <= not lclk; - end if; -end process; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : if CFG_LEON3 = 1 generate - cpu : for i in 0 to CFG_NCPU-1 generate - u0 : leon3s -- LEON3 processor - generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - end generate; - errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); - - dsugen : if CFG_DSU = 1 generate - dsu0 : dsu3 -- LEON3 Debug Support Unit - generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); --- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); - dsui.enable <= '1'; - dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); - dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); - end generate; - end generate; - - nodsu : if CFG_DSU = 0 generate - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - end generate; - - irqctrl : if CFG_IRQ3_ENABLE /= 0 generate - irqctrl0 : irqmp -- interrupt controller - generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - port map (rstn, clkm, apbi, apbo(2), irqo, irqi); - end generate; - irq3 : if CFG_IRQ3_ENABLE = 0 generate - x : for i in 0 to CFG_NCPU-1 generate - irqi(i).irl <= "0000"; - end generate; - apbo(2) <= apb_none; - end generate; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - sram_pwrdwn <= '0'; - sram_gwen <= '1'; - sram_adsc <= '0'; - sram_adsp <= '1'; - - - mctrl2 : if (CFG_MCTRL_LEON2 = 1) and (CFG_SSCTRL = 0) generate -- LEON2 memory controller - sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0, - srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT, - ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - sram_adv <= '1'; - ramben_pads : for i in 0 to 3 generate - x : outpad generic map (tech => padtech) - port map (ramben(i), memo.mben(3-i)); - end generate; - end generate; - - mempads : if (CFG_MCTRL_LEON2 = 1) or (CFG_SSCTRL = 1) generate -- LEON2 memory controller - addr_pad : outpadv generic map (width => 19, tech => padtech) - port map (address, memo.address(20 downto 2)); - rams_pad : outpad generic map (tech => padtech) - port map (ramsn, memo.ramsn(0)); - roms_pad : outpad generic map (tech => padtech) - port map (romsn, memo.romsn(0)); - iosn_pad : outpad generic map (tech => padtech) - port map (iosn, memo.iosn); - oen_pad : outpad generic map (tech => padtech) - port map (oen, memo.oen); - rwen_pad : outpad generic map (tech => padtech) - port map (rwen, memo.writen); - roen_pad : outpad generic map (tech => padtech) - port map (ramoen, memo.ramoen(0)); - wri_pad : outpad generic map (tech => padtech) - port map (writen, memo.writen); - - bdr : for i in 0 to 3 generate - data_pad : iopadv generic map (tech => padtech, width => 8) - port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), - memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); - end generate; - - end generate; - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - dcomgen : if CFG_AHB_UART = 1 generate - dcom0: ahbuart -- Debug UART - generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU)); - dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); --- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; - end generate; - nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR) - port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - - gpt : if CFG_GPT_ENABLE /= 0 generate - timer0 : gptimer -- timer unit - generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - port map (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; --- led(4) <= gpto.wdog; - end generate; - notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - ua1 : if CFG_UART1_ENABLE /= 0 generate - uart1 : apbuart -- UART 1 - generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); - apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; --- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; - end generate; - noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit - grgpio0: grgpio - generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) - port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : for i in 0 to 6 generate - pio_pad : iopad generic map (tech => padtech) - port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - end generate; - end generate; - - -end Behavioral; \ No newline at end of file diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/leon3mp_libero.prj.convert.8.6.bak b/designs/ProjetBlanc-LeonLPP-M7A3P1k/leon3mp_libero.prj.convert.8.6.bak deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/leon3mp_libero.prj.convert.8.6.bak +++ /dev/null @@ -1,2622 +0,0 @@ -KEY LIBERO "8.6" -KEY CAPTURE "8.6.2.10" -KEY HDLTechnology "VHDL" -KEY VendorTechnology_Family "Virtex2" -KEY VendorTechnology_Die "" -KEY VendorTechnology_Package "" -KEY ProjectLocation "." -KEY SimulationType "VHDL" -KEY Vendor "Actel" -KEY ActiveRoot "leon3mp" -LIST REVISIONS -VALUE="Impl1",NUM=1 -CURREV=1 -ENDLIST -LIST LIBRARIES -grlib -secureip -eclipsee -synplify -techmap -spw -eth -opencores -core1553bbc -core1553brt -core1553brm -corePCIF -gaisler -esa -gleichmann -fmf -spansion -gsi -lpp -cypress -hynix -micron -openchip -work -ENDLIST -LIST LIBRARIES_grlib -ALIAS=grlib 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"/../../lib/gleichmann/ac97/ac97.vhd,hdl" -VALUE "/../../lib/gleichmann/ac97/ac97_oc.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/spi_slave_model.v,hdl" -VALUE "/../../lib/gleichmann/sim/txt_util.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/phy_ext.vhd,hdl" -VALUE "/../../lib/gleichmann/sim/uart_ext.vhd,hdl" -VALUE "/../../lib/fmf/utilities/conversions.vhd,hdl" -VALUE "/../../lib/fmf/utilities/gen_utils.vhd,hdl" -VALUE "/../../lib/fmf/flash/flash.vhd,hdl" -VALUE "/../../lib/fmf/flash/s25fl064a.vhd,hdl" -VALUE "/../../lib/fmf/flash/m25p80.vhd,hdl" -VALUE "/../../lib/fmf/fifo/idt7202.vhd,hdl" -VALUE "/../../lib/gsi/ssram/functions.vhd,hdl" -VALUE "/../../lib/gsi/ssram/core_burst.vhd,hdl" -VALUE "/../../lib/gsi/ssram/g880e18bt.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl" -VALUE "/../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTER.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl" -VALUE "/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/ALU.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Adder.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Clk_divider.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_MUX.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MAC_REG.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/MUX2.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Multiplier.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/REG.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/Shifter.vhd,hdl" -VALUE "/../../lib/lpp/./general_purpose/general_purpose.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/ApbDriver.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/UART.vhd,hdl" -VALUE "/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl" -VALUE "/../../lib/cypress/ssram/components.vhd,hdl" -VALUE "/../../lib/cypress/ssram/package_utility.vhd,hdl" -VALUE "/../../lib/cypress/ssram/cy7c1354b.vhd,hdl" -VALUE "/../../lib/cypress/ssram/cy7c1380d.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/HY5PS121621F.vhd,hdl" -VALUE "/../../lib/hynix/ddr2/components.vhd,hdl" -VALUE "/../../lib/micron/sdram/mobile_sdr.v,hdl" -VALUE "/../../lib/micron/sdram/components.vhd,hdl" -VALUE "/../../lib/micron/sdram/mt48lc16m16a2.vhd,hdl" -VALUE "/../../lib/micron/ddr/ddr2.v,hdl" -VALUE "/../../lib/micron/ddr/mobile_ddr.v,hdl" -VALUE "/../../lib/micron/ddr/ddr3.v,hdl" -VALUE "/../../lib/micron/ddr/mt46v16m16.vhd,hdl" -VALUE "/../../lib/openchip/gpio/gpio.vhd,hdl" -VALUE "/../../lib/openchip/gpio/apbgpio.vhd,hdl" -VALUE "/../../lib/openchip/charlcd/charlcd.vhd,hdl" -VALUE "/../../lib/openchip/charlcd/apbcharlcd.vhd,hdl" -VALUE "/../../lib/openchip/sui/sui.vhd,hdl" -VALUE "/../../lib/openchip/sui/apbsui.vhd,hdl" -VALUE "/../../lib/work/debug/debug.vhd,hdl" -VALUE "/../../lib/work/debug/grtestmod.vhd,hdl" -VALUE "/../../lib/work/debug/cpu_disas.vhd,hdl" -VALUE "/config.vhd,hdl" -VALUE "/ahbrom.vhd,hdl" -VALUE "/leon3mp.vhd,hdl" -ENDFILELIST -ENDLIST -ENDLIST -ENDLIST diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/linkprom b/designs/ProjetBlanc-LeonLPP-M7A3P1k/linkprom deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/linkprom +++ /dev/null @@ -1,155 +0,0 @@ -/* linkcmds - * - * $Id: linkcmds,v 1.8.2.1 2000/05/24 17:06:38 joel Exp $ - */ - -OUTPUT_ARCH(sparc) -__DYNAMIC = 0; - -/* - * The memory map looks like this: - * +--------------------+ <- low memory - * | .text | - * | etext | - * | ctor list | the ctor and dtor lists are for - * | dtor list | C++ support - * | _endtext | - * +--------------------+ - * | .data | initialized data goes here - * | _sdata | - * | _edata | - * +--------------------+ - * | .bss | - * | __bss_start | start of bss, cleared by crt0 - * | _end | start of heap, used by sbrk() - * +--------------------+ - * | heap space | - * | _ENDHEAP | - * | stack space | - * | __stack | top of stack - * +--------------------+ <- high memory - */ - - -/* Default values, can be overridden */ - -_PROM_SIZE = 2M; -_RAM_SIZE = 4M; - -_RAM_START = 0x02000000; -_RAM_END = _RAM_START + _RAM_SIZE; - -_PROM_START = 0x00000000; -_PROM_END = _PROM_START + _PROM_SIZE; - -/* - * Alternate names without leading _. - */ - -PROM_START = _PROM_START; -PROM_SIZE = _PROM_SIZE; -PROM_END = _PROM_END; - -RAM_START = _RAM_START; -RAM_SIZE = _RAM_SIZE; -RAM_END = _RAM_END; - -_LEON_REG = 0x80000000; -LEON_REG = 0x80000000; - -/* these are the maximum values */ - -MEMORY -{ - rom : ORIGIN = 0x00000000, LENGTH = 16M - ram : ORIGIN = 0x40000000, LENGTH = 1024M -} - -SECTIONS -{ - .text : - { - CREATE_OBJECT_SYMBOLS - text_start = .; - _text_start = .; - *(.text) - . = ALIGN (16); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t*) - - /* - * C++ constructors - */ - __CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - __CTOR_END__ = .; - __DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - __DTOR_END__ = .; - - _rodata_start = . ; - *(.rodata*) - *(.gnu.linkonce.r*) - _erodata = ALIGN( 0x10 ) ; - - etext = ALIGN(0x10); - _etext = .; - *(.init) - *(.fini) - *(.lit) - *(.shdata) - . = ALIGN (16); - _endtext = .; - } > rom - .dynamic : { *(.dynamic) } >ram - .got : { *(.got) } >ram - .plt : { *(.plt) } >ram - .hash : { *(.hash) } >ram - .dynrel : { *(.dynrel) } >ram - .dynsym : { *(.dynsym) } >ram - .dynstr : { *(.dynstr) } >ram - .hash : { *(.hash) } >ram - .data : - { - data_start = .; - _data_start = .; - _sdata = . ; - *(.data) - *(.gnu.linkonce.d*) - *(.gcc_except_table) - . = ALIGN(0x10); - edata = .; - _edata = .; - } > ram - .shbss : - { - *(.shbss) - } > ram - .bss : - { - __bss_start = ALIGN(0x8); - _bss_start = .; - bss_start = .; - *(.bss) - *(COMMON) - end = .; - _end = ALIGN(0x8); - __end = ALIGN(0x8); - } > ram - .jcr . (NOLOAD) : { *(.jcr) } - .stab . (NOLOAD) : - { - [ .stab ] - } - .stabstr . (NOLOAD) : - { - [ .stabstr ] - } -} diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/prom.h b/designs/ProjetBlanc-LeonLPP-M7A3P1k/prom.h deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/prom.h +++ /dev/null @@ -1,10 +0,0 @@ -#define MCFG1 0x10380233 -#define MCFG2 0xe6A26e60 -#define MCFG3 0x000ff000 -#define ASDCFG 0xfff00100 -#define DSDCFG 0xe6A06e60 -#define L2MCTRLIO 0x80000000 -#define IRQCTRL 0x80000200 -#define RAMSTART 0x40000000 -#define RAMSIZE 0x00100000 - diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/prom.srec b/designs/ProjetBlanc-LeonLPP-M7A3P1k/prom.srec deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/prom.srec +++ /dev/null @@ -1,37 +0,0 @@ -S00C000070726F6D2E737265635A -S113000081D8200003000004821060E08188400051 -S1130010819000008198000081800000A180000090 -S113002001000000030020408210600FC2A00040C5 -S11300308410000001000000010000000100000025 -S11300400100000001000000801080020100000097 -S11300500100000001000000010000000100000098 -S1130060874440008608E01F881000008A100000C2 -S11300708C1000008E100000A0100000A2100000E0 -S1130080A4100000A6100000A8100000AA10000090 -S1130090AC100000AE1000009010000092100000A0 -S11300A09410000096100000981000009A100000B0 -S11300B09C1000009E10000086A0E00116BFFFEF18 -S11300C081E00000821020028190400003000004BF -S11300D0821060E0818840000100000001000000FF -S11300E001000000834800008330600C80886001B8 -S11300F00280002401000000070000008610E1785F -S1130100C108C000C118C000C518C000C918C0008B -S1130110CD18C000D118C000D518C000D918C0002F -S1130120DD18C000E118C000E518C000E918C000DF -S1130130ED18C000F118C000F518C000F918C0008F -S1130140FD18C000010000000100000001000000D3 -S1130150010000000100000089A008420100000025 -S113016001000000010000000100000010800005F3 -S11301700100000001000000000000000000000079 -S1130180874440008730E01C8688E00F1280001608 -S11301900320000005040E008410A233C420400094 -S11301A00539A89B8410A260C4206004050003FCE8 -S11301B0C420600882103860C40040008530A00C60 -S11301C0030000048210600980A04002128000062F -S11301D0033FFC00821061000539A81B8410A26053 -S11301E0C4204000050000808210000080A0E000D0 -S11301F002800005010000008200400210BFFFFCE5 -S11302008620E0013D1003FFBC17A3E0BC2780015A -S11302109C27A0600310000081C040000100000082 -S113022000000000000000000000000000000000CA -S9030000FC diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/rhumc.dc b/designs/ProjetBlanc-LeonLPP-M7A3P1k/rhumc.dc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/rhumc.dc +++ /dev/null @@ -1,101 +0,0 @@ -/*******************************************/ -/* Script to compile leon with synopsys DC */ -/* Jiri Gaisler, Gaisler Research, 2004 */ -/*******************************************/ - -search_path = {"." "/usr/local/synlibs/DesignKit_DARE_V2.0/DesignKit/IO/syn" "/usr/local/synlibs/DesignKit_DARE_V2.0/DesignKit/CORE/syn" "/usr/local/synlibs/rhumc" "/usr/local/synopsys/libraries/syn"} -target_library = "RadHardUMC18_CORE_WCMIL.db" -link_library = "RadHardUMC18_CORE_WCMIL.db rhmem_wcmil.db Post_RH_UMC018_IOLIB_WCMIL.db" -link_library = "*" + link_library -symbol_library = "generic.sdb" -allow_newer_db_files = "true"; - -/* constraints - tailor to your own technology. An average 0.35 std-cell tech - should give you 80 - 100 MHz depending on ram access time. A 0.25 tech - should run at +150 MHz. Frequency in MHz, delays in ns ... */ - -frequency = 200 -clock_skew = 0.10 -input_setup = 2.0 -output_delay = 4.0 - -/* don't touch anything from here unless you know what you are doing */ - -include leon3mp.dc - -ungroup find(cell, "*pad*") -flatten - -group find(cell, {"sr*", "sdc", "apb*", "uart*", "timer*", "irq*" \ - "ahb*", "dsu0", "rst0", "dcom*" }) -design_name amod \ - -cell_name amod0 - -current_instance u0_0/p0 -ungroup -all -flatten -current_instance ../rf0 -ungroup -all -flatten -current_instance ../cmem0 -ungroup -all -flatten -current_instance ../../amod0 -ungroup -all -flatten -current_instance .. - -peri = 1000.0 / frequency -input_delay = peri - input_setup -tdelay = output_delay + 2 -create_clock -name "clk" -period peri -waveform { 0.0, peri / 2.0 } { "clk" } -set_wire_load_mode segmented - -set_clock_skew -plus_uncertainty clock_skew "clk" -set_clock_skew -minus_uncertainty clock_skew "clk" - -/* -set_input_delay input_delay -clock clk { \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" "brdyn" "bexcn" } - -set_max_delay tdelay -to { "errorn" "wdogn" \ - "pio[15]" "pio[14]" "pio[13]" \ - "pio[12]" "pio[11]" "pio[10]" "pio[9]" "pio[8]" "pio[7]" \ - "pio[6]" "pio[5]" "pio[4]" "pio[3]" "pio[2]" "pio[1]" "pio[0]" \ - "data[31]" "data[30]" "data[29]" "data[28]" "data[27]" "data[26]" \ - "data[25]" "data[24]" "data[23]" "data[22]" "data[21]" "data[20]" \ - "data[19]" "data[18]" "data[17]" "data[16]" "data[15]" "data[14]" \ - "data[13]" "data[12]" "data[11]" "data[10]" "data[9]" "data[8]" \ - "data[7]" "data[6]" "data[5]" "data[4]" "data[3]" "data[2]" \ - "data[1]" "data[0]" } - -set_max_delay output_delay -to { \ - "writen" "romsn[1]" "romsn[0]" "read" "oen" \ - "iosn" "rwen[3]" "rwen[2]" "rwen[1]" "rwen[0]" "ramsn[3]" \ - "ramsn[2]" "ramsn[1]" "ramsn[0]" \ - "ramoen[3]" "ramoen[2]" "ramoen[1]" "ramoen[0]" \ - "sdcsn[1]" "sdcsn[0]" "sdwen" "sdrasn" "sdcasn" \ - "sddqm[3]" "sddqm[2]" "sddqm[1]" "sddqm[0]" \ - "address[27]" "address[26]" "address[25]" "address[24]" \ - "address[23]" "address[22]" "address[21]" "address[20]" \ - "address[19]" "address[18]" "address[17]" "address[16]" \ - "address[15]" "address[14]" "address[13]" "address[12]" \ - "address[11]" "address[10]" "address[9]" "address[8]" \ - "address[7]" "address[6]" "address[5]" "address[4]" \ - "address[3]" "address[2]" "address[1]" "address[0]"} - -*/ -set_max_area 0 -set_max_transition 2.0 leon3mp -set_flatten false -design {"leon3mp.db:leon3mp"} -set_structure true -design {"leon3mp.db:leon3mp"} -boolean false -timing true - - -compile -map_effort medium -boundary_optimization - -write -f db -hier leon3mp -output leon3mp.db - -report_timing -report_area diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/sdram.srec b/designs/ProjetBlanc-LeonLPP-M7A3P1k/sdram.srec deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/sdram.srec +++ /dev/null @@ -1,19492 +0,0 @@ -S00D0000736472616D2E7372656300 -S31540000000881000000910006C81C1206C01000000BE -S31540000010A1480000A75000001080203BAC102001F2 -S3154000002091D0200001000000010000000100000006 -S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006B81C523A401000000CF -S31540000050A14800002910006981C522C8010000009E -S31540000060A14800002910006981C523340100000021 -S3154000007091D02000010000000100000001000000B6 -S3154000008091D02000010000000100000001000000A6 -S31540000090A1480000A75000001080201BAC1020098A -S315400000A091D0200001000000010000000100000086 -S315400000B091D0200001000000010000000100000076 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a/designs/ProjetBlanc-LeonLPP-M7A3P1k/tkconfig.h +++ /dev/null @@ -1,1189 +0,0 @@ -#if defined CONFIG_SYN_INFERRED -#define CONFIG_SYN_TECH inferred -#elif defined CONFIG_SYN_UMC -#define CONFIG_SYN_TECH umc -#elif defined CONFIG_SYN_RHUMC -#define CONFIG_SYN_TECH rhumc -#elif defined CONFIG_SYN_ATC18 -#define CONFIG_SYN_TECH atc18s -#elif defined CONFIG_SYN_ATC18RHA -#define CONFIG_SYN_TECH atc18rha -#elif defined CONFIG_SYN_AXCEL -#define CONFIG_SYN_TECH axcel -#elif defined CONFIG_SYN_PROASICPLUS -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_ALTERA -#define CONFIG_SYN_TECH altera -#elif defined CONFIG_SYN_STRATIX -#define CONFIG_SYN_TECH stratix1 -#elif defined CONFIG_SYN_STRATIXII -#define CONFIG_SYN_TECH stratix2 -#elif defined CONFIG_SYN_STRATIXIII -#define CONFIG_SYN_TECH stratix3 -#elif defined CONFIG_SYN_CYCLONEIII -#define CONFIG_SYN_TECH cyclone3 -#elif defined CONFIG_SYN_EASIC90 -#define CONFIG_SYN_TECH easic90 -#elif defined CONFIG_SYN_IHP25 -#define CONFIG_SYN_TECH ihp25 -#elif defined CONFIG_SYN_IHP25RH -#define CONFIG_SYN_TECH ihp25rh -#elif defined CONFIG_SYN_LATTICE -#define CONFIG_SYN_TECH lattice -#elif defined CONFIG_SYN_ECLIPSE -#define CONFIG_SYN_TECH eclipse -#elif defined CONFIG_SYN_PEREGRINE -#define CONFIG_SYN_TECH peregrine -#elif defined CONFIG_SYN_PROASIC -#define CONFIG_SYN_TECH proasic -#elif defined CONFIG_SYN_PROASIC3 -#define CONFIG_SYN_TECH apa3 -#elif defined CONFIG_SYN_SPARTAN2 -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEX -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_VIRTEXE -#define CONFIG_SYN_TECH virtex -#elif defined CONFIG_SYN_SPARTAN3 -#define CONFIG_SYN_TECH spartan3 -#elif defined CONFIG_SYN_SPARTAN3E -#define CONFIG_SYN_TECH spartan3e -#elif defined CONFIG_SYN_VIRTEX2 -#define CONFIG_SYN_TECH virtex2 -#elif defined CONFIG_SYN_VIRTEX4 -#define CONFIG_SYN_TECH virtex4 -#elif defined CONFIG_SYN_VIRTEX5 -#define CONFIG_SYN_TECH virtex5 -#elif defined CONFIG_SYN_RH_LIB18T -#define CONFIG_SYN_TECH rhlib18t -#elif defined CONFIG_SYN_SMIC13 -#define CONFIG_SYN_TECH smic013 -#elif defined CONFIG_SYN_UT025CRH -#define CONFIG_SYN_TECH ut25 -#elif defined CONFIG_SYN_TSMC90 -#define CONFIG_SYN_TECH tsmc90 -#elif defined CONFIG_SYN_CUSTOM1 -#define CONFIG_SYN_TECH custom1 -#else -#error "unknown target technology" -#endif - -#if defined CONFIG_SYN_INFER_RAM -#define CFG_RAM_TECH inferred -#elif defined CONFIG_MEM_UMC -#define CFG_RAM_TECH umc -#elif defined CONFIG_MEM_RHUMC -#define CFG_RAM_TECH rhumc -#elif defined CONFIG_MEM_VIRAGE -#define CFG_RAM_TECH memvirage -#elif defined CONFIG_MEM_ARTISAN -#define CFG_RAM_TECH memartisan -#elif defined CONFIG_MEM_CUSTOM1 -#define CFG_RAM_TECH custom1 -#elif defined CONFIG_MEM_VIRAGE90 -#define CFG_RAM_TECH memvirage90 -#elif defined CONFIG_MEM_INFERRED -#define CFG_RAM_TECH inferred -#else -#define CFG_RAM_TECH CONFIG_SYN_TECH -#endif - -#if defined CONFIG_SYN_INFER_PADS -#define CFG_PAD_TECH inferred -#else -#define CFG_PAD_TECH CONFIG_SYN_TECH -#endif - -#ifndef CONFIG_SYN_NO_ASYNC -#define CONFIG_SYN_NO_ASYNC 0 -#endif - -#ifndef CONFIG_SYN_SCAN -#define CONFIG_SYN_SCAN 0 -#endif - - -#if defined CONFIG_CLK_ALTDLL -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_HCLKBUF -#define CFG_CLK_TECH axcel -#elif defined CONFIG_CLK_LATDLL -#define CFG_CLK_TECH lattice -#elif defined CONFIG_CLK_PRO3PLL -#define CFG_CLK_TECH apa3 -#elif defined CONFIG_CLK_CLKDLL -#define CFG_CLK_TECH virtex -#elif defined CONFIG_CLK_DCM -#define CFG_CLK_TECH CONFIG_SYN_TECH -#elif defined CONFIG_CLK_LIB18T -#define CFG_CLK_TECH rhlib18t -#elif defined CONFIG_CLK_RHUMC -#define CFG_CLK_TECH rhumc -#else -#define CFG_CLK_TECH inferred -#endif - -#ifndef CONFIG_CLK_MUL -#define CONFIG_CLK_MUL 2 -#endif - -#ifndef CONFIG_CLK_DIV -#define CONFIG_CLK_DIV 2 -#endif - -#ifndef CONFIG_OCLK_DIV -#define CONFIG_OCLK_DIV 2 -#endif - -#ifndef CONFIG_PCI_CLKDLL -#define CONFIG_PCI_CLKDLL 0 -#endif - -#ifndef CONFIG_PCI_SYSCLK -#define CONFIG_PCI_SYSCLK 0 -#endif - -#ifndef CONFIG_CLK_NOFB -#define CONFIG_CLK_NOFB 0 -#endif -#ifndef CONFIG_LEON3 -#define CONFIG_LEON3 0 -#endif - -#ifndef CONFIG_PROC_NUM -#define CONFIG_PROC_NUM 1 -#endif - -#ifndef CONFIG_IU_NWINDOWS -#define CONFIG_IU_NWINDOWS 8 -#endif - -#ifndef CONFIG_IU_RSTADDR -#define CONFIG_IU_RSTADDR 8 -#endif - -#ifndef CONFIG_IU_LDELAY -#define CONFIG_IU_LDELAY 1 -#endif - -#ifndef CONFIG_IU_WATCHPOINTS -#define CONFIG_IU_WATCHPOINTS 0 -#endif - -#ifdef CONFIG_IU_V8MULDIV -#ifdef CONFIG_IU_MUL_LATENCY_4 -#define CFG_IU_V8 1 -#elif defined CONFIG_IU_MUL_LATENCY_5 -#define CFG_IU_V8 2 -#elif defined CONFIG_IU_MUL_LATENCY_2 -#define CFG_IU_V8 16#32# -#endif -#else -#define CFG_IU_V8 0 -#endif - -#ifndef CONFIG_PWD -#define CONFIG_PWD 0 -#endif - -#ifndef CONFIG_IU_MUL_MAC -#define CONFIG_IU_MUL_MAC 0 -#endif - -#ifndef CONFIG_IU_SVT -#define CONFIG_IU_SVT 0 -#endif - -#if defined CONFIG_FPU_GRFPC1 -#define CONFIG_FPU_GRFPC 1 -#elif defined CONFIG_FPU_GRFPC2 -#define CONFIG_FPU_GRFPC 2 -#else -#define CONFIG_FPU_GRFPC 0 -#endif - -#if defined CONFIG_FPU_GRFPU_INFMUL -#define CONFIG_FPU_GRFPU_MUL 0 -#elif defined CONFIG_FPU_GRFPU_DWMUL -#define CONFIG_FPU_GRFPU_MUL 1 -#elif defined CONFIG_FPU_GRFPU_MODGEN -#define CONFIG_FPU_GRFPU_MUL 2 -#else -#define CONFIG_FPU_GRFPU_MUL 0 -#endif - -#if defined CONFIG_FPU_GRFPU_SH -#define CONFIG_FPU_GRFPU_SHARED 1 -#else -#define CONFIG_FPU_GRFPU_SHARED 0 -#endif - -#if defined CONFIG_FPU_GRFPU -#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) -#elif defined CONFIG_FPU_MEIKO -#define CONFIG_FPU 15 -#elif defined CONFIG_FPU_GRFPULITE -#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) -#else -#define CONFIG_FPU 0 -#endif - -#ifndef CONFIG_FPU_NETLIST -#define CONFIG_FPU_NETLIST 0 -#endif - -#ifndef CONFIG_ICACHE_ENABLE -#define CONFIG_ICACHE_ENABLE 0 -#endif - -#if defined CONFIG_ICACHE_ASSO1 -#define CFG_IU_ISETS 1 -#elif defined CONFIG_ICACHE_ASSO2 -#define CFG_IU_ISETS 2 -#elif defined CONFIG_ICACHE_ASSO3 -#define CFG_IU_ISETS 3 -#elif defined CONFIG_ICACHE_ASSO4 -#define CFG_IU_ISETS 4 -#else -#define CFG_IU_ISETS 1 -#endif - -#if defined CONFIG_ICACHE_SZ1 -#define CFG_ICACHE_SZ 1 -#elif defined CONFIG_ICACHE_SZ2 -#define CFG_ICACHE_SZ 2 -#elif defined CONFIG_ICACHE_SZ4 -#define CFG_ICACHE_SZ 4 -#elif defined CONFIG_ICACHE_SZ8 -#define CFG_ICACHE_SZ 8 -#elif defined CONFIG_ICACHE_SZ16 -#define CFG_ICACHE_SZ 16 -#elif defined CONFIG_ICACHE_SZ32 -#define CFG_ICACHE_SZ 32 -#elif defined CONFIG_ICACHE_SZ64 -#define CFG_ICACHE_SZ 64 -#elif defined CONFIG_ICACHE_SZ128 -#define CFG_ICACHE_SZ 128 -#elif defined CONFIG_ICACHE_SZ256 -#define CFG_ICACHE_SZ 256 -#else -#define CFG_ICACHE_SZ 1 -#endif - -#ifdef CONFIG_ICACHE_LZ16 -#define CFG_ILINE_SZ 4 -#else -#define CFG_ILINE_SZ 8 -#endif - -#if defined CONFIG_ICACHE_ALGORND -#define CFG_ICACHE_ALGORND 2 -#elif defined CONFIG_ICACHE_ALGOLRR -#define CFG_ICACHE_ALGORND 1 -#else -#define CFG_ICACHE_ALGORND 0 -#endif - -#ifndef CONFIG_ICACHE_LOCK -#define CONFIG_ICACHE_LOCK 0 -#endif - -#ifndef CONFIG_ICACHE_LRAM -#define CONFIG_ICACHE_LRAM 0 -#endif - -#ifndef CONFIG_ICACHE_LRSTART -#define CONFIG_ICACHE_LRSTART 8E -#endif - -#if defined CONFIG_ICACHE_LRAM_SZ2 -#define CFG_ILRAM_SIZE 2 -#elif defined CONFIG_ICACHE_LRAM_SZ4 -#define CFG_ILRAM_SIZE 4 -#elif defined CONFIG_ICACHE_LRAM_SZ8 -#define CFG_ILRAM_SIZE 8 -#elif defined CONFIG_ICACHE_LRAM_SZ16 -#define CFG_ILRAM_SIZE 16 -#elif defined CONFIG_ICACHE_LRAM_SZ32 -#define CFG_ILRAM_SIZE 32 -#elif defined CONFIG_ICACHE_LRAM_SZ64 -#define CFG_ILRAM_SIZE 64 -#elif defined CONFIG_ICACHE_LRAM_SZ128 -#define CFG_ILRAM_SIZE 128 -#elif defined CONFIG_ICACHE_LRAM_SZ256 -#define CFG_ILRAM_SIZE 256 -#else -#define CFG_ILRAM_SIZE 1 -#endif - - -#ifndef CONFIG_DCACHE_ENABLE -#define CONFIG_DCACHE_ENABLE 0 -#endif - -#if defined CONFIG_DCACHE_ASSO1 -#define CFG_IU_DSETS 1 -#elif defined CONFIG_DCACHE_ASSO2 -#define CFG_IU_DSETS 2 -#elif defined CONFIG_DCACHE_ASSO3 -#define CFG_IU_DSETS 3 -#elif defined CONFIG_DCACHE_ASSO4 -#define CFG_IU_DSETS 4 -#else -#define CFG_IU_DSETS 1 -#endif - -#if defined CONFIG_DCACHE_SZ1 -#define CFG_DCACHE_SZ 1 -#elif defined CONFIG_DCACHE_SZ2 -#define CFG_DCACHE_SZ 2 -#elif defined CONFIG_DCACHE_SZ4 -#define CFG_DCACHE_SZ 4 -#elif defined CONFIG_DCACHE_SZ8 -#define CFG_DCACHE_SZ 8 -#elif defined CONFIG_DCACHE_SZ16 -#define CFG_DCACHE_SZ 16 -#elif defined CONFIG_DCACHE_SZ32 -#define CFG_DCACHE_SZ 32 -#elif defined CONFIG_DCACHE_SZ64 -#define CFG_DCACHE_SZ 64 -#elif defined CONFIG_DCACHE_SZ128 -#define CFG_DCACHE_SZ 128 -#elif defined CONFIG_DCACHE_SZ256 -#define CFG_DCACHE_SZ 256 -#else -#define CFG_DCACHE_SZ 1 -#endif - -#ifdef CONFIG_DCACHE_LZ16 -#define CFG_DLINE_SZ 4 -#else -#define CFG_DLINE_SZ 8 -#endif - -#if defined CONFIG_DCACHE_ALGORND -#define CFG_DCACHE_ALGORND 2 -#elif defined CONFIG_DCACHE_ALGOLRR -#define CFG_DCACHE_ALGORND 1 -#else -#define CFG_DCACHE_ALGORND 0 -#endif - -#ifndef CONFIG_DCACHE_LOCK -#define CONFIG_DCACHE_LOCK 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP -#define CONFIG_DCACHE_SNOOP 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - -#ifndef CONFIG_DCACHE_SNOOP_SEPTAG -#define CONFIG_DCACHE_SNOOP_SEPTAG 0 -#endif - -#ifndef CONFIG_CACHE_FIXED -#define CONFIG_CACHE_FIXED 0 -#endif - -#ifndef CONFIG_DCACHE_LRAM -#define CONFIG_DCACHE_LRAM 0 -#endif - -#ifndef CONFIG_DCACHE_LRSTART -#define CONFIG_DCACHE_LRSTART 8F -#endif - -#if defined CONFIG_DCACHE_LRAM_SZ2 -#define CFG_DLRAM_SIZE 2 -#elif defined CONFIG_DCACHE_LRAM_SZ4 -#define CFG_DLRAM_SIZE 4 -#elif defined CONFIG_DCACHE_LRAM_SZ8 -#define CFG_DLRAM_SIZE 8 -#elif defined CONFIG_DCACHE_LRAM_SZ16 -#define CFG_DLRAM_SIZE 16 -#elif defined CONFIG_DCACHE_LRAM_SZ32 -#define CFG_DLRAM_SIZE 32 -#elif defined CONFIG_DCACHE_LRAM_SZ64 -#define CFG_DLRAM_SIZE 64 -#elif defined CONFIG_DCACHE_LRAM_SZ128 -#define CFG_DLRAM_SIZE 128 -#elif defined CONFIG_DCACHE_LRAM_SZ256 -#define CFG_DLRAM_SIZE 256 -#else -#define CFG_DLRAM_SIZE 1 -#endif - -#if defined CONFIG_MMU_PAGE_4K -#define CONFIG_MMU_PAGE 0 -#elif defined CONFIG_MMU_PAGE_8K -#define CONFIG_MMU_PAGE 1 -#elif defined CONFIG_MMU_PAGE_16K -#define CONFIG_MMU_PAGE 2 -#elif defined CONFIG_MMU_PAGE_32K -#define CONFIG_MMU_PAGE 3 -#elif defined CONFIG_MMU_PAGE_PROG -#define CONFIG_MMU_PAGE 4 -#else -#define CONFIG_MMU_PAGE 0 -#endif - -#ifdef CONFIG_MMU_ENABLE -#define CONFIG_MMUEN 1 - -#ifdef CONFIG_MMU_SPLIT -#define CONFIG_TLB_TYPE 0 -#endif -#ifdef CONFIG_MMU_COMBINED -#define CONFIG_TLB_TYPE 1 -#endif - -#ifdef CONFIG_MMU_REPARRAY -#define CONFIG_TLB_REP 0 -#endif -#ifdef CONFIG_MMU_REPINCREMENT -#define CONFIG_TLB_REP 1 -#endif - -#ifdef CONFIG_MMU_I2 -#define CONFIG_ITLBNUM 2 -#endif -#ifdef CONFIG_MMU_I4 -#define CONFIG_ITLBNUM 4 -#endif -#ifdef CONFIG_MMU_I8 -#define CONFIG_ITLBNUM 8 -#endif -#ifdef CONFIG_MMU_I16 -#define CONFIG_ITLBNUM 16 -#endif -#ifdef CONFIG_MMU_I32 -#define CONFIG_ITLBNUM 32 -#endif - -#define CONFIG_DTLBNUM 2 -#ifdef CONFIG_MMU_D2 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 2 -#endif -#ifdef CONFIG_MMU_D4 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 4 -#endif -#ifdef CONFIG_MMU_D8 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 8 -#endif -#ifdef CONFIG_MMU_D16 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 16 -#endif -#ifdef CONFIG_MMU_D32 -#undef CONFIG_DTLBNUM -#define CONFIG_DTLBNUM 32 -#endif -#ifdef CONFIG_MMU_FASTWB -#define CFG_MMU_FASTWB 1 -#else -#define CFG_MMU_FASTWB 0 -#endif - -#else -#define CONFIG_MMUEN 0 -#define CONFIG_ITLBNUM 2 -#define CONFIG_DTLBNUM 2 -#define CONFIG_TLB_TYPE 1 -#define CONFIG_TLB_REP 1 -#define CFG_MMU_FASTWB 0 -#endif - -#ifndef CONFIG_DSU_ENABLE -#define CONFIG_DSU_ENABLE 0 -#endif - -#if defined CONFIG_DSU_ITRACESZ1 -#define CFG_DSU_ITB 1 -#elif CONFIG_DSU_ITRACESZ2 -#define CFG_DSU_ITB 2 -#elif CONFIG_DSU_ITRACESZ4 -#define CFG_DSU_ITB 4 -#elif CONFIG_DSU_ITRACESZ8 -#define CFG_DSU_ITB 8 -#elif CONFIG_DSU_ITRACESZ16 -#define CFG_DSU_ITB 16 -#else -#define CFG_DSU_ITB 0 -#endif - -#if defined CONFIG_DSU_ATRACESZ1 -#define CFG_DSU_ATB 1 -#elif CONFIG_DSU_ATRACESZ2 -#define CFG_DSU_ATB 2 -#elif CONFIG_DSU_ATRACESZ4 -#define CFG_DSU_ATB 4 -#elif CONFIG_DSU_ATRACESZ8 -#define CFG_DSU_ATB 8 -#elif CONFIG_DSU_ATRACESZ16 -#define CFG_DSU_ATB 16 -#else -#define CFG_DSU_ATB 0 -#endif - -#ifndef CONFIG_LEON3FT_EN -#define CONFIG_LEON3FT_EN 0 -#endif - -#if defined CONFIG_IUFT_PAR -#define CONFIG_IUFT_EN 1 -#elif defined CONFIG_IUFT_DMR -#define CONFIG_IUFT_EN 2 -#elif defined CONFIG_IUFT_BCH -#define CONFIG_IUFT_EN 3 -#elif defined CONFIG_IUFT_TMR -#define CONFIG_IUFT_EN 4 -#else -#define CONFIG_IUFT_EN 0 -#endif -#ifndef CONFIG_RF_ERRINJ -#define CONFIG_RF_ERRINJ 0 -#endif - -#ifndef CONFIG_FPUFT_EN -#define CONFIG_FPUFT 0 -#else -#ifdef CONFIG_FPU_GRFPU -#define CONFIG_FPUFT 2 -#else -#define CONFIG_FPUFT 1 -#endif -#endif - -#ifndef CONFIG_CACHE_FT_EN -#define CONFIG_CACHE_FT_EN 0 -#endif -#ifndef CONFIG_CACHE_ERRINJ -#define CONFIG_CACHE_ERRINJ 0 -#endif - -#ifndef CONFIG_LEON3_NETLIST -#define CONFIG_LEON3_NETLIST 0 -#endif - -#ifdef CONFIG_DEBUG_PC32 -#define CFG_DEBUG_PC32 0 -#else -#define CFG_DEBUG_PC32 2 -#endif -#ifndef CONFIG_IU_DISAS -#define CONFIG_IU_DISAS 0 -#endif -#ifndef CONFIG_IU_DISAS_NET -#define CONFIG_IU_DISAS_NET 0 -#endif - - -#ifndef CONFIG_AHB_SPLIT -#define CONFIG_AHB_SPLIT 0 -#endif - -#ifndef CONFIG_AHB_RROBIN -#define CONFIG_AHB_RROBIN 0 -#endif - -#ifndef CONFIG_AHB_IOADDR -#define CONFIG_AHB_IOADDR FFF -#endif - -#ifndef CONFIG_APB_HADDR -#define CONFIG_APB_HADDR 800 -#endif - -#ifndef CONFIG_AHB_MON -#define CONFIG_AHB_MON 0 -#endif - -#ifndef CONFIG_AHB_MONERR -#define CONFIG_AHB_MONERR 0 -#endif - -#ifndef CONFIG_AHB_MONWAR -#define CONFIG_AHB_MONWAR 0 -#endif - -#ifndef CONFIG_DSU_UART -#define CONFIG_DSU_UART 0 -#endif - - -#ifndef CONFIG_DSU_JTAG -#define CONFIG_DSU_JTAG 0 -#endif - -#ifndef CONFIG_DSU_ETH -#define CONFIG_DSU_ETH 0 -#endif - -#ifndef CONFIG_DSU_IPMSB -#define CONFIG_DSU_IPMSB C0A8 -#endif - -#ifndef CONFIG_DSU_IPLSB -#define CONFIG_DSU_IPLSB 0033 -#endif - -#ifndef CONFIG_DSU_ETHMSB -#define CONFIG_DSU_ETHMSB 020000 -#endif - -#ifndef CONFIG_DSU_ETHLSB -#define CONFIG_DSU_ETHLSB 000009 -#endif - -#if defined CONFIG_DSU_ETHSZ1 -#define CFG_DSU_ETHB 1 -#elif CONFIG_DSU_ETHSZ2 -#define CFG_DSU_ETHB 2 -#elif CONFIG_DSU_ETHSZ4 -#define CFG_DSU_ETHB 4 -#elif CONFIG_DSU_ETHSZ8 -#define CFG_DSU_ETHB 8 -#elif CONFIG_DSU_ETHSZ16 -#define CFG_DSU_ETHB 16 -#elif CONFIG_DSU_ETHSZ32 -#define CFG_DSU_ETHB 32 -#else -#define CFG_DSU_ETHB 1 -#endif - -#ifndef CONFIG_DSU_ETH_PROG -#define CONFIG_DSU_ETH_PROG 0 -#endif - - -#ifndef CONFIG_SRCTRL -#define CONFIG_SRCTRL 0 -#endif - -#ifndef CONFIG_SRCTRL_PROMWS -#define CONFIG_SRCTRL_PROMWS 0 -#endif - -#ifndef CONFIG_SRCTRL_RAMWS -#define CONFIG_SRCTRL_RAMWS 0 -#endif - -#ifndef CONFIG_SRCTRL_IOWS -#define CONFIG_SRCTRL_IOWS 0 -#endif - -#ifndef CONFIG_SRCTRL_RMW -#define CONFIG_SRCTRL_RMW 0 -#endif - -#ifndef CONFIG_SRCTRL_8BIT -#define CONFIG_SRCTRL_8BIT 0 -#endif - - -#ifndef CONFIG_SRCTRL_ROMASEL -#define CONFIG_SRCTRL_ROMASEL 0 -#endif - -#if defined CONFIG_SRCTRL_SRBANKS1 -#define CFG_SR_CTRL_SRBANKS 1 -#elif defined CONFIG_SRCTRL_SRBANKS2 -#define CFG_SR_CTRL_SRBANKS 2 -#elif defined CONFIG_SRCTRL_SRBANKS3 -#define CFG_SR_CTRL_SRBANKS 3 -#elif defined CONFIG_SRCTRL_SRBANKS4 -#define CFG_SR_CTRL_SRBANKS 4 -#elif defined CONFIG_SRCTRL_SRBANKS5 -#define CFG_SR_CTRL_SRBANKS 5 -#else -#define CFG_SR_CTRL_SRBANKS 1 -#endif - -#if defined CONFIG_SRCTRL_BANKSZ0 -#define CFG_SR_CTRL_BANKSZ 0 -#elif defined CONFIG_SRCTRL_BANKSZ1 -#define CFG_SR_CTRL_BANKSZ 1 -#elif defined CONFIG_SRCTRL_BANKSZ2 -#define CFG_SR_CTRL_BANKSZ 2 -#elif defined CONFIG_SRCTRL_BANKSZ3 -#define CFG_SR_CTRL_BANKSZ 3 -#elif defined CONFIG_SRCTRL_BANKSZ4 -#define CFG_SR_CTRL_BANKSZ 4 -#elif defined CONFIG_SRCTRL_BANKSZ5 -#define CFG_SR_CTRL_BANKSZ 5 -#elif defined CONFIG_SRCTRL_BANKSZ6 -#define CFG_SR_CTRL_BANKSZ 6 -#elif defined CONFIG_SRCTRL_BANKSZ7 -#define CFG_SR_CTRL_BANKSZ 7 -#elif defined CONFIG_SRCTRL_BANKSZ8 -#define CFG_SR_CTRL_BANKSZ 8 -#elif defined CONFIG_SRCTRL_BANKSZ9 -#define CFG_SR_CTRL_BANKSZ 9 -#elif defined CONFIG_SRCTRL_BANKSZ10 -#define CFG_SR_CTRL_BANKSZ 10 -#elif defined CONFIG_SRCTRL_BANKSZ11 -#define CFG_SR_CTRL_BANKSZ 11 -#elif defined CONFIG_SRCTRL_BANKSZ12 -#define CFG_SR_CTRL_BANKSZ 12 -#elif defined CONFIG_SRCTRL_BANKSZ13 -#define CFG_SR_CTRL_BANKSZ 13 -#else -#define CFG_SR_CTRL_BANKSZ 0 -#endif -#ifndef CONFIG_MCTRL_LEON2 -#define CONFIG_MCTRL_LEON2 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM -#define CONFIG_MCTRL_SDRAM 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_SEPBUS -#define CONFIG_MCTRL_SDRAM_SEPBUS 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_INVCLK -#define CONFIG_MCTRL_SDRAM_INVCLK 0 -#endif - -#ifndef CONFIG_MCTRL_SDRAM_BUS64 -#define CONFIG_MCTRL_SDRAM_BUS64 0 -#endif - -#ifndef CONFIG_MCTRL_8BIT -#define CONFIG_MCTRL_8BIT 0 -#endif - -#ifndef CONFIG_MCTRL_16BIT -#define CONFIG_MCTRL_16BIT 0 -#endif - -#ifndef CONFIG_MCTRL_5CS -#define CONFIG_MCTRL_5CS 0 -#endif - -#ifndef CONFIG_MCTRL_EDAC -#define CONFIG_MCTRL_EDAC 0 -#endif - -#ifndef CONFIG_MCTRL_PAGE -#define CONFIG_MCTRL_PAGE 0 -#endif - -#ifndef CONFIG_MCTRL_PROGPAGE -#define CONFIG_MCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_SDCTRL -#define CONFIG_SDCTRL 0 -#endif - -#ifndef CONFIG_SDCTRL_SEPBUS -#define CONFIG_SDCTRL_SEPBUS 0 -#endif - -#ifndef CONFIG_SDCTRL_INVCLK -#define CONFIG_SDCTRL_INVCLK 0 -#endif - -#ifndef CONFIG_SDCTRL_BUS64 -#define CONFIG_SDCTRL_BUS64 0 -#endif - -#ifndef CONFIG_SDCTRL_PAGE -#define CONFIG_SDCTRL_PAGE 0 -#endif - -#ifndef CONFIG_SDCTRL_PROGPAGE -#define CONFIG_SDCTRL_PROGPAGE 0 -#endif - -#ifndef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBROM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBROM_START -#define CONFIG_AHBROM_START 000 -#endif - -#ifndef CONFIG_AHBROM_PIPE -#define CONFIG_AHBROM_PIPE 0 -#endif - -#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) -#define CONFIG_ROM_START 100 -#else -#define CONFIG_ROM_START 000 -#endif - - -#ifndef CONFIG_AHBRAM_ENABLE -#define CONFIG_AHBRAM_ENABLE 0 -#endif - -#ifndef CONFIG_AHBRAM_START -#define CONFIG_AHBRAM_START A00 -#endif - -#if defined CONFIG_AHBRAM_SZ1 -#define CFG_AHBRAMSZ 1 -#elif CONFIG_AHBRAM_SZ2 -#define CFG_AHBRAMSZ 2 -#elif CONFIG_AHBRAM_SZ4 -#define CFG_AHBRAMSZ 4 -#elif CONFIG_AHBRAM_SZ8 -#define CFG_AHBRAMSZ 8 -#elif CONFIG_AHBRAM_SZ16 -#define CFG_AHBRAMSZ 16 -#elif CONFIG_AHBRAM_SZ32 -#define CFG_AHBRAMSZ 32 -#elif CONFIG_AHBRAM_SZ64 -#define CFG_AHBRAMSZ 64 -#else -#define CFG_AHBRAMSZ 1 -#endif - -#ifndef CONFIG_GRETH_ENABLE -#define CONFIG_GRETH_ENABLE 0 -#endif - -#ifndef CONFIG_GRETH_GIGA -#define CONFIG_GRETH_GIGA 0 -#endif - -#if defined CONFIG_GRETH_FIFO4 -#define CFG_GRETH_FIFO 4 -#elif defined CONFIG_GRETH_FIFO8 -#define CFG_GRETH_FIFO 8 -#elif defined CONFIG_GRETH_FIFO16 -#define CFG_GRETH_FIFO 16 -#elif defined CONFIG_GRETH_FIFO32 -#define CFG_GRETH_FIFO 32 -#elif defined CONFIG_GRETH_FIFO64 -#define CFG_GRETH_FIFO 64 -#else -#define CFG_GRETH_FIFO 8 -#endif - -#ifndef CONFIG_CAN_ENABLE -#define CONFIG_CAN_ENABLE 0 -#endif - -#ifndef CONFIG_CANIO -#define CONFIG_CANIO 0 -#endif - -#ifndef CONFIG_CANIRQ -#define CONFIG_CANIRQ 0 -#endif - -#ifndef CONFIG_CANLOOP -#define CONFIG_CANLOOP 0 -#endif - -#ifndef CONFIG_CAN_SYNCRST -#define CONFIG_CAN_SYNCRST 0 -#endif - - -#ifndef CONFIG_CAN_FT -#define CONFIG_CAN_FT 0 -#endif -#if defined CONFIG_PCI_SIMPLE_TARGET -#define CFG_PCITYPE 1 -#elif defined CONFIG_PCI_MASTER_TARGET_DMA -#define CFG_PCITYPE 3 -#elif defined CONFIG_PCI_MASTER_TARGET -#define CFG_PCITYPE 2 -#else -#define CFG_PCITYPE 0 -#endif - -#ifndef CONFIG_PCI_VENDORID -#define CONFIG_PCI_VENDORID 0 -#endif - -#ifndef CONFIG_PCI_DEVICEID -#define CONFIG_PCI_DEVICEID 0 -#endif - -#ifndef CONFIG_PCI_REVID -#define CONFIG_PCI_REVID 0 -#endif - -#if defined CONFIG_PCI_FIFO0 -#define CFG_PCIFIFO 8 -#define CFG_PCI_ENFIFO 0 -#elif defined CONFIG_PCI_FIFO16 -#define CFG_PCIFIFO 16 -#elif defined CONFIG_PCI_FIFO32 -#define CFG_PCIFIFO 32 -#elif defined CONFIG_PCI_FIFO64 -#define CFG_PCIFIFO 64 -#elif defined CONFIG_PCI_FIFO128 -#define CFG_PCIFIFO 128 -#elif defined CONFIG_PCI_FIFO256 -#define CFG_PCIFIFO 256 -#else -#define CFG_PCIFIFO 8 -#endif - -#ifndef CFG_PCI_ENFIFO -#define CFG_PCI_ENFIFO 1 -#endif - - -#ifndef CONFIG_PCI_ARBITER_APB -#define CONFIG_PCI_ARBITER_APB 0 -#endif - -#ifndef CONFIG_PCI_ARBITER -#define CONFIG_PCI_ARBITER 0 -#endif - -#ifndef CONFIG_PCI_ARBITER_NREQ -#define CONFIG_PCI_ARBITER_NREQ 4 -#endif - -#ifndef CONFIG_PCI_TRACE -#define CONFIG_PCI_TRACE 0 -#endif - -#if defined CONFIG_PCI_TRACE512 -#define CFG_PCI_TRACEBUF 512 -#elif defined CONFIG_PCI_TRACE1024 -#define CFG_PCI_TRACEBUF 1024 -#elif defined CONFIG_PCI_TRACE2048 -#define CFG_PCI_TRACEBUF 2048 -#elif defined CONFIG_PCI_TRACE4096 -#define CFG_PCI_TRACEBUF 4096 -#else -#define CFG_PCI_TRACEBUF 256 -#endif - - -#ifndef CONFIG_SPW_ENABLE -#define CONFIG_SPW_ENABLE 0 -#endif - -#ifndef CONFIG_SPW_NUM -#define CONFIG_SPW_NUM 1 -#endif - -#if defined CONFIG_SPW_AHBFIFO4 -#define CONFIG_SPW_AHBFIFO 4 -#elif defined CONFIG_SPW_AHBFIFO8 -#define CONFIG_SPW_AHBFIFO 8 -#elif defined CONFIG_SPW_AHBFIFO16 -#define CONFIG_SPW_AHBFIFO 16 -#elif defined CONFIG_SPW_AHBFIFO32 -#define CONFIG_SPW_AHBFIFO 32 -#elif defined CONFIG_SPW_AHBFIFO64 -#define CONFIG_SPW_AHBFIFO 64 -#else -#define CONFIG_SPW_AHBFIFO 4 -#endif - -#if defined CONFIG_SPW_RXFIFO16 -#define CONFIG_SPW_RXFIFO 16 -#elif defined CONFIG_SPW_RXFIFO32 -#define CONFIG_SPW_RXFIFO 32 -#elif defined CONFIG_SPW_RXFIFO64 -#define CONFIG_SPW_RXFIFO 64 -#else -#define CONFIG_SPW_RXFIFO 16 -#endif - -#ifndef CONFIG_SPW_RMAP -#define CONFIG_SPW_RMAP 0 -#endif - -#if defined CONFIG_SPW_RMAPBUF2 -#define CONFIG_SPW_RMAPBUF 2 -#elif defined CONFIG_SPW_RMAPBUF4 -#define CONFIG_SPW_RMAPBUF 4 -#elif defined CONFIG_SPW_RMAPBUF6 -#define CONFIG_SPW_RMAPBUF 6 -#elif defined CONFIG_SPW_RMAPBUF8 -#define CONFIG_SPW_RMAPBUF 8 -#else -#define CONFIG_SPW_RMAPBUF 4 -#endif - -#ifndef CONFIG_SPW_RMAPCRC -#define CONFIG_SPW_RMAPCRC 0 -#endif - -#ifndef CONFIG_SPW_RXUNAL -#define CONFIG_SPW_RXUNAL 0 -#endif - -#ifndef CONFIG_SPW_NETLIST -#define CONFIG_SPW_NETLIST 0 -#endif - -#ifndef CONFIG_SPW_FT -#define CONFIG_SPW_FT 0 -#endif - -#if defined CONFIG_SPW_GRSPW1 -#define CONFIG_SPW_GRSPW 1 -#else -#define CONFIG_SPW_GRSPW 2 -#endif - -#ifndef CONFIG_SPW_DMACHAN -#define CONFIG_SPW_DMACHAN 1 -#endif - -#ifndef CONFIG_SPW_PORTS -#define CONFIG_SPW_PORTS 1 -#endif - -#if defined CONFIG_SPW_RX_SDR -#define CONFIG_SPW_INPUT 2 -#elif defined CONFIG_SPW_RX_DDR -#define CONFIG_SPW_INPUT 3 -#elif defined CONFIG_SPW_RX_XOR -#define CONFIG_SPW_INPUT 0 -#elif defined CONFIG_SPW_RX_AFLEX -#define CONFIG_SPW_INPUT 1 -#else -#define CONFIG_SPW_INPUT 2 -#endif - -#if defined CONFIG_SPW_TX_SDR -#define CONFIG_SPW_OUTPUT 0 -#elif defined CONFIG_SPW_TX_DDR -#define CONFIG_SPW_OUTPUT 1 -#elif defined CONFIG_SPW_TX_AFLEX -#define CONFIG_SPW_OUTPUT 2 -#else -#define CONFIG_SPW_OUTPUT 0 -#endif - -#ifndef CONFIG_SPW_RTSAME -#define CONFIG_SPW_RTSAME 0 -#endif -#ifndef CONFIG_UART1_ENABLE -#define CONFIG_UART1_ENABLE 0 -#endif - -#if defined CONFIG_UA1_FIFO1 -#define CFG_UA1_FIFO 1 -#elif defined CONFIG_UA1_FIFO2 -#define CFG_UA1_FIFO 2 -#elif defined CONFIG_UA1_FIFO4 -#define CFG_UA1_FIFO 4 -#elif defined CONFIG_UA1_FIFO8 -#define CFG_UA1_FIFO 8 -#elif defined CONFIG_UA1_FIFO16 -#define CFG_UA1_FIFO 16 -#elif defined CONFIG_UA1_FIFO32 -#define CFG_UA1_FIFO 32 -#else -#define CFG_UA1_FIFO 1 -#endif - -#ifndef CONFIG_UART2_ENABLE -#define CONFIG_UART2_ENABLE 0 -#endif - -#if defined CONFIG_UA2_FIFO1 -#define CFG_UA2_FIFO 1 -#elif defined CONFIG_UA2_FIFO2 -#define CFG_UA2_FIFO 2 -#elif defined CONFIG_UA2_FIFO4 -#define CFG_UA2_FIFO 4 -#elif defined CONFIG_UA2_FIFO8 -#define CFG_UA2_FIFO 8 -#elif defined CONFIG_UA2_FIFO16 -#define CFG_UA2_FIFO 16 -#elif defined CONFIG_UA2_FIFO32 -#define CFG_UA2_FIFO 32 -#else -#define CFG_UA2_FIFO 1 -#endif - -#ifndef CONFIG_IRQ3_ENABLE -#define CONFIG_IRQ3_ENABLE 0 -#endif -#ifndef CONFIG_IRQ3_NSEC -#define CONFIG_IRQ3_NSEC 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif -#ifndef CONFIG_GPT_ENABLE -#define CONFIG_GPT_ENABLE 0 -#endif - -#ifndef CONFIG_GPT_NTIM -#define CONFIG_GPT_NTIM 1 -#endif - -#ifndef CONFIG_GPT_SW -#define CONFIG_GPT_SW 8 -#endif - -#ifndef CONFIG_GPT_TW -#define CONFIG_GPT_TW 8 -#endif - -#ifndef CONFIG_GPT_IRQ -#define CONFIG_GPT_IRQ 8 -#endif - -#ifndef CONFIG_GPT_SEPIRQ -#define CONFIG_GPT_SEPIRQ 0 -#endif - -#ifndef CONFIG_GPT_WDOGEN -#define CONFIG_GPT_WDOGEN 0 -#endif - -#ifndef CONFIG_GPT_WDOG -#define CONFIG_GPT_WDOG 0 -#endif - -#ifndef CONFIG_GRGPIO_ENABLE -#define CONFIG_GRGPIO_ENABLE 0 -#endif -#ifndef CONFIG_GRGPIO_IMASK -#define CONFIG_GRGPIO_IMASK 0000 -#endif -#ifndef CONFIG_GRGPIO_WIDTH -#define CONFIG_GRGPIO_WIDTH 1 -#endif - - -#ifndef CONFIG_DEBUG_UART -#define CONFIG_DEBUG_UART 0 -#endif diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/top_libero.prj.convert.8.1.bak b/designs/ProjetBlanc-LeonLPP-M7A3P1k/top_libero.prj.convert.8.1.bak deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/top_libero.prj.convert.8.1.bak +++ /dev/null @@ -1,1860 +0,0 @@ -KEY LIBERO "8.1" -KEY CAPTURE "8.1.0.32" -KEY HDLTechnology "VHDL" -KEY VendorTechnology_Family "PROASIC3" -KEY VendorTechnology_Die "IT14X14M4LDP" -KEY VendorTechnology_Package "fg324" -KEY ProjectLocation "." -KEY SimulationType "VHDL" -KEY Vendor "Actel" -KEY ActiveRoot "top" -LIST REVISIONS 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-TIME="1210769968" -SIZE="6173" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\maps\syncram64.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="4010" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\maps\syncram_2p.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="6732" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\maps\syncram_dp.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="5126" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\maps\tap.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="4941" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\maps\techbuf.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="2814" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\maps\toutpad.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="5195" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\maps\usbhc_net.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="49497" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\proasic3\buffer_apa3.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="2154" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="6738" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\proasic3\memory_apa3.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="17067" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\techmap\proasic3\tap_proasic3.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="3674" -LIBRARY="techmap" -ENDFILE -VALUE "\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="115108" -LIBRARY="proasic3" -ENDFILE -VALUE "\..\..\\lib\work\debug\cpu_disas.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="4162" -ENDFILE -VALUE "\..\..\\lib\work\debug\debug.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="1675" -ENDFILE -VALUE "\..\..\\lib\work\debug\grtestmod.vhd,hdl" -STATE="utd" -TIME="1210769968" -SIZE="4683" -ENDFILE -VALUE "\ahbrom.vhd,hdl" -STATE="utd" -TIME="1314194813" -SIZE="9014" -ENDFILE -VALUE "\config.vhd,hdl" -STATE="utd" -TIME="1316609032" -SIZE="6145" -ENDFILE -VALUE "\designer\impl2\top.adb,adb" -STATE="ood" -TIME="1316518304" -SIZE="3168256" -ENDFILE -VALUE "\designer\impl2\top.pdb,pdb" -STATE="ood" -TIME="1316518292" -SIZE="1591296" -ENDFILE -VALUE "\designer\impl2\top_fp\top.pro,pro" -STATE="utd" -TIME="1316092826" -SIZE="2023" -ENDFILE -VALUE "\leon3mp.vhd,hdl" -STATE="utd" -TIME="1316444842" -SIZE="13491" -ENDFILE -VALUE "\synthesis\top.edn,syn_edn" -STATE="ood" -TIME="1316518141" -SIZE="1633458" -ENDFILE -VALUE "\synthesis\top_sdc.sdc,syn_sdc" -STATE="ood" -TIME="1316518141" -SIZE="381" -ENDFILE -VALUE "C:\opt\GRLIB\grlib-ft-fpga-1.0.21-b4003\boards\TEST-LEON-M7-LPP\TEST-LEON-M7-LPP.pdc,pdc" -STATE="utd" -TIME="1314194811" -SIZE="5135" -IS_READONLY="TRUE" -ENDFILE -ENDLIST -LIST UsedFile -ENDLIST -LIST NewModulesInfo -LIST "top::work" -FILE "\leon3mp.vhd,hdl" -LIST ExcludePackageForSynthesis -VALUE "\..\..\\lib\grlib\stdlib\stdio.vhd,hdl" -VALUE "\..\..\\lib\grlib\util\util.vhd,hdl" -VALUE "\..\..\\lib\grlib\sparc\sparc_disas.vhd,hdl" -VALUE "\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl" -VALUE "\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl" -VALUE "\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl" -VALUE "\..\..\\lib\synplify\sim\synplify.vhd,hdl" -VALUE "\..\..\\lib\synplify\sim\synattr.vhd,hdl" -VALUE "\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl" -VALUE "\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl" -VALUE "\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl" -VALUE "\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl" -VALUE "\..\..\\lib\gaisler\sim\sim.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\sram.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\ata_device.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\sram16.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\phy.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl" -VALUE "\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl" -VALUE "\..\..\\lib\fmf\utilities\conversions.vhd,hdl" -VALUE "\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl" -VALUE "\..\..\\lib\gsi\ssram\functions.vhd,hdl" -VALUE "\..\..\\lib\gsi\ssram\core_burst.vhd,hdl" -VALUE "\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl" -VALUE "\..\..\\lib\cypress\ssram\components.vhd,hdl" -VALUE "\..\..\\lib\cypress\ssram\package_utility.vhd,hdl" -VALUE "\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl" -VALUE "\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl" -VALUE "\..\..\\lib\work\debug\debug.vhd,hdl" -VALUE "\..\..\\lib\work\debug\grtestmod.vhd,hdl" -VALUE "\..\..\\lib\work\debug\cpu_disas.vhd,hdl" -VALUE "\config.vhd,hdl" -VALUE "\ahbrom.vhd,hdl" -VALUE "\leon3mp.vhd,hdl" -ENDLIST -ENDLIST -ENDLIST -LIST AssociatedStimulus -ENDLIST -LIST Other_Association -ENDLIST -LIST SimulationOptions -UseAutomaticDoFile=true -IncludeWaveDo=false -Type=max -RunTime=1000ns -Resolution=1ps -VsimOpt= -EntityName=testbench -TopInstanceName=_0 -DoFileName= -DoFileName2=wave.do -DoFileParams= -DisplayDUTWave=false -LogAllSignals=false -DumpVCD=false -VCDFileName=power.vcd -ENDLIST -LIST ModelSimLibPath -UseCustomPath=FALSE -LibraryPath= -ENDLIST -LIST GlobalFlowOptions -GenerateHDLAfterSynthesis=FALSE -GenerateHDLAfterPhySynthesis=FALSE -RunDRCAfterSynthesis=FALSE -AutoCheckConstraints=TRUE -UpdateViewDrawIni=TRUE -UpdateModelSimIni=TRUE -NoIOMode=FALSE -GenerateHDLFromSchematic=TRUE -FlashProInputFile=pdb -SmartGenCompileReport=T -ENDLIST -LIST PhySynthesisOptions -ENDLIST -LIST Profiles -NAME="Synplify AE" -FUNCTION="Synthesis" -TOOL="Synplify" -LOCATION="C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\bin\synplify_pro.exe" -PARAM="" -BATCH=0 -EndProfile -NAME="ModelSim AE" -FUNCTION="Simulation" -TOOL="ModelSim" -LOCATION="C:\Actel\Libero_v9.0\Model\win32acoem\modelsim.exe" -PARAM="" -BATCH=0 -EndProfile -NAME="WFL" -FUNCTION="Stimulus" -TOOL="WFL" -LOCATION="syncad.exe" -PARAM="-pwflite" -BATCH=0 -EndProfile -NAME="FlashPro" -FUNCTION="Program" -TOOL="FlashPro" -LOCATION="C:\Actel\Libero_v9.0\Designer\bin\FlashPro.exe" -PARAM="" -BATCH=0 -EndProfile -ENDLIST -LIST ProjectState5.1 -ENDLIST -LIST ExcludePackageForSimulation -ENDLIST -LIST ExcludePackageForSynthesis -LIST top -VALUE "\..\..\\lib\grlib\stdlib\stdio.vhd,hdl" -VALUE "\..\..\\lib\grlib\util\util.vhd,hdl" -VALUE "\..\..\\lib\grlib\sparc\sparc_disas.vhd,hdl" -VALUE "\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl" -VALUE "\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl" -VALUE "\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl" -VALUE "\..\..\\lib\synplify\sim\synplify.vhd,hdl" -VALUE "\..\..\\lib\synplify\sim\synattr.vhd,hdl" -VALUE "\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl" -VALUE "\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl" -VALUE "\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl" -VALUE "\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl" -VALUE "\..\..\\lib\gaisler\sim\sim.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\sram.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\ata_device.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\sram16.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\phy.vhd,hdl" -VALUE "\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl" -VALUE "\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl" -VALUE "\..\..\\lib\fmf\utilities\conversions.vhd,hdl" -VALUE "\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl" -VALUE "\..\..\\lib\gsi\ssram\functions.vhd,hdl" -VALUE "\..\..\\lib\gsi\ssram\core_burst.vhd,hdl" -VALUE "\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl" -VALUE "\..\..\\lib\cypress\ssram\components.vhd,hdl" -VALUE "\..\..\\lib\cypress\ssram\package_utility.vhd,hdl" -VALUE "\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl" -VALUE "\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl" -VALUE "\..\..\\lib\work\debug\debug.vhd,hdl" -VALUE "\..\..\\lib\work\debug\grtestmod.vhd,hdl" -VALUE "\..\..\\lib\work\debug\cpu_disas.vhd,hdl" -VALUE "\config.vhd,hdl" -VALUE "\ahbrom.vhd,hdl" -VALUE "\leon3mp.vhd,hdl" -ENDLIST -ENDLIST -LIST IncludeModuleForSimulation -ENDLIST -LIST CDBOrder -ENDLIST -LIST UserCustomizedFileList -ENDLIST -LIST OpenedFileList -DESIGNFLOW: -FILE:\leon3mp.vhd,hdl -FILE:\config.vhd,hdl -FILE:\..\..\\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl -ACTIVE_VIEW:1 -ENDLIST diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/tsmc13.rc b/designs/ProjetBlanc-LeonLPP-M7A3P1k/tsmc13.rc deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/tsmc13.rc +++ /dev/null @@ -1,8 +0,0 @@ -set_attribute lib_search_path {. /usr/local/synlibs/TSMG13F210D3_1.1/lib} -set_attribute library {"tsmg13f210t3_wc_108V_125C.lib" "/home/jiri/ibm/vhdl/temic/atc18/allmem.lib" } / -include leon3mp.rc -include atc18cond.rc -define_clock -period 5000 -name clock1 clk -synthesize -to_mapped -report_area -report_timing diff --git a/designs/ProjetBlanc-LeonLPP-M7A3P1k/wave.do b/designs/ProjetBlanc-LeonLPP-M7A3P1k/wave.do deleted file mode 100644 --- a/designs/ProjetBlanc-LeonLPP-M7A3P1k/wave.do +++ /dev/null @@ -1,66 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /testbench/clk -add wave -noupdate -format Logic /testbench/rst -add wave -noupdate -format Literal -radix hexadecimal /testbench/address -add wave -noupdate -format Literal -radix hexadecimal /testbench/data -add wave -noupdate -format Literal /testbench/ramsn -add wave -noupdate -format Literal /testbench/ramoen -add wave -noupdate -format Literal /testbench/rwen -add wave -noupdate -format Literal /testbench/rwenx -add wave -noupdate -format Literal /testbench/romsn -add wave -noupdate -format Logic /testbench/iosn -add wave -noupdate -format Logic /testbench/oen -add wave -noupdate -format Logic /testbench/read -add wave -noupdate -format Logic /testbench/writen -add wave -noupdate -format Literal -radix hexadecimal /testbench/sa -add wave -noupdate -format Literal -radix hexadecimal /testbench/sd -add wave -noupdate -format Literal /testbench/sdcke -add wave -noupdate -format Literal /testbench/sdcsn -add wave -noupdate -format Logic /testbench/sdwen -add wave -noupdate -format Logic /testbench/sdrasn -add wave -noupdate -format Logic /testbench/sdcasn -add wave -noupdate -format Literal /testbench/sddqm -add wave -noupdate -format Logic /testbench/sdclk -add wave -noupdate -divider {CPU 1} -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ici -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ico -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dci -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dco -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/rfi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/rfo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/irqi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/irqo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dbgi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dbgo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/wpr -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/dsur -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/iu0/ir -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/cmem0/crami -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/cmem0/cramo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/l3/cpu__0/u0/p0/m0/c0/dcache0/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/mg2/sr1/sd0/sdctrl/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/apbi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/apbo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbsi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbso -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbmi -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/ahbmo -add wave -noupdate -format Literal -radix hexadecimal /testbench/d3/mg2/sr1/r -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {35452000 ps} 0} -configure wave -namecolwidth 212 -configure wave -valuecolwidth 117 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {689872312 ps} {690294089 ps}